Slideshare uses cookies to improve functionality and performance, and to provide you with relevant advertising. If you continue browsing the site, you agree to the use of cookies on this website. See our User Agreement and Privacy Policy.

Slideshare uses cookies to improve functionality and performance, and to provide you with relevant advertising. If you continue browsing the site, you agree to the use of cookies on this website. See our Privacy Policy and User Agreement for details.

A survey of Flash Translation Layer

1.
Journal of Systems Architecture 55 (2009) 332–343
Contents lists available at ScienceDirect
Journal of Systems Architecture
journal homepage: www.elsevier.com/locate/sysarc
A survey of Flash Translation Layer q
Tae-Sun Chung a,*, Dong-Joo Park b, Sangwon Park c, Dong-Ho Lee d, Sang-Won Lee e, Ha-Joo Song f
a
College of Information Technology, Ajou University, Suwon 443-749, Korea
b
School of Computing, Soongsil University, Seoul 156-743, Korea
c
Information Communication Engineering, Hankook University of Foreign Studies, Yongin 449-791, Korea
d
Department of Computer Science, Hanyang University, Ansan 426-791, Korea
e
School of Information and Communications Engineering, Sungkyunkwan University, Suwon 440-746, Korea
f
Division of Computer, Pukyung National University, Busan 608-737, Korea
a r t i c l e i n f o a b s t r a c t
Article history: Recently, ﬂash memory is widely adopted in embedded applications as it has several strong points,
Received 9 May 2007 including its non-volatility, fast access speed, shock resistance, and low power consumption. However,
Received in revised form 11 February 2009 due to its hardware characteristics, speciﬁcally its ‘‘erase-before-write” feature, it requires a software
Accepted 23 March 2009
layer known as FTL (Flash Translation Layer). This paper surveys the state-of-the-art FTL software for
Available online 17 April 2009
ﬂash memory. It deﬁnes the problems, addresses algorithms to solve them, and discusses related research
issues. In addition, the paper provides performance results based on our implementation of each FTL
Keywords:
algorithm.
Flash memory
Embedded system
Ó 2009 Elsevier B.V. All rights reserved.
File system
1. Introduction location in which no data were previously written. The mapping
table is then updated due to the newly changed logical/physical
Flash memory has inherently strong points compared to a tradi- address mapping. This protects one block from being erased by
tional hard disk. These points include its non-volatility, fast access an overwrite operation.
speed, resistance to shocks, and low power consumption. Due to When applying the FTL algorithm to embedded applications,
these advantages, it has been widely adopted in embedded appli- there are two major considerations: storage performance and
cations such as MMC or CF card ﬂash memory, mobile devices RAM memory requirements. With respect to storage performance,
including cellular phones and mp3 players, and many others. How- as ﬂash memory has the special hardware characteristics men-
ever, due to its hardware characteristics, a ﬂash memory system tioned above, the overall system performance is mainly affected
requires special software modules to read (write) data from (to) by the write performance. In particular, as the erase cost is much
ﬂash memory. more expensive compared to the write or read cost, it is very
One basic hardware characteristics of ﬂash memory is that it important to minimize erase operations. Additionally, RAM mem-
has an erase-before-write architecture [5]. That is, to update a loca- ory required to maintain the mapping information is a valuable
tion in ﬂash memory, the location must ﬁrst be erased before new resource in embedded applications. Thus, if an FTL algorithm
data can be written to it. The memory portion for erasing differs in requires a large amount of RAM memory, the product cost will
size from that for reading or writing [2], resulting in the major per- be increased.
formance degradation of the overall ﬂash memory system. This paper surveys the-state-of-the-art FTL algorithms. Gal and
Therefore, a type of system software termed FTL (Flash Transla- Toledo [7] also provided algorithms and data structures for ﬂash
tion Layer) has been introduced [1,2,6,9,13,14]. At the core an FTL memory systems. Compared to their work, the present study
is using a logical-to-physical address mapping table. That is, if a focuses on FTL algorithms and does not discuss ﬁle system issues
physical address location mapped to a logical address contains pre- [12,16,8]. Here, the problem is deﬁned, FTL algorithms are
viously written data, the input data is written to an empty physical discussed, and related research issues are addressed. Performance
results based on our implementation of each of FTL algorithms are
also provided.
q
The preliminary version of the paper was presented at the 2006 IFIP interna- This paper is organized as follows: In Section 2 the problem is
tional conference on embedded and ubiquitous computing (EUC 2006). deﬁned. Section 3 shows how previous FTL algorithms can be clas-
* Corresponding author.
E-mail addresses: tschung@ajou.ac.kr (T.-S. Chung), djpart@computing.ssu.ac.kr
siﬁed, each of which is explained in depth in Section 4. Section 5
(D.-J. Park), swpark@hufs.ac.kr (S. Park), dhlee72@cse.hanyang.ac.kr (D.-H. Lee), presents performance results. Finally, Section 6 concludes the
swlee@skku.edu (S.-W. Lee), hajusong@pknu.ac.kr (H.-J. Song). paper.
1383-7621/$ - see front matter Ó 2009 Elsevier B.V. All rights reserved.
doi:10.1016/j.sysarc.2009.03.005

2.
T.-S. Chung et al. / Journal of Systems Architecture 55 (2009) 332–343 333
2. Problem deﬁnition & FTL functionalities Applications
file system API
2.1. Problem deﬁnition
File System
First, operation units in the ﬂash memory system are deﬁned as
I/O with logical sector number
follows:
FTL (Flash Translation Layer)
Deﬁnition 1. A sector is the smallest amount of data which is read
I/O with physical sector number
or written at a time. That is, a sector is the unit of a read or a write
operations. Flash Memory
Deﬁnition 2. A block is the unit of an erase operation in ﬂash Fig. 1. Overall architecture of ﬂash memory system.
memory. The size of a block is some multiples of the size of a
sector.
Fig. 1 shows the software architecture of the ﬂash ﬁle system. physical pages in total, where each page is organized into a data
This section focuses on the FTL layer shown in Fig. 1. The ﬁle sys- sector and a spare area. Additionally, if it is assumed that 16 log-
tem layer issues a series of read or write commands each with a ical sectors exist, the row size of the mapping table is 16. When
logical sector number, to read data from, or write data to, speciﬁc the ﬁle system issues the command – ‘‘write(9, A): write data ‘A’
addresses in ﬂash memory. The logical sector number is converted to lsn (logical sector number) 9”, the FTL algorithm writes the
to a real physical sector number of ﬂash memory by some mapping data ‘A’ to psn (physical sector number) 3 according to the map-
algorithm in the FTL layer. ping table if psn 3 has not had data written to it at an earlier
Thus, the problem deﬁnition of FTL is as follows: It is assumed time.
that ﬂash memory is composed of n physical sectors. The ﬁle sys- However, in another case, the FTL algorithm determines the
tem – the upper layer – considers a ﬂash memory as a block-I/O de- location of an empty physical sector, writes data to it, and adjusts
vice that consists of m logical sectors. Given that a logical sector the mapping table. If an empty sector does not exist, the FTL algo-
must be mapped to at least one physical sector, the number m is rithm will select a victim block from ﬂash memory, copy the valid
less than or equal to n. data in the victim block to the spare free block, and update the
mapping table. Finally, it will erase the victim block, which will be-
Deﬁnition 3. Flash memory is composed of a number of blocks,
come the spare block.
and each block is composed of multiple sectors. Flash memory has
To rebuild the mapping table after a power outage, the FTL algo-
the following characteristics: If a physical sector location in ﬂash
rithm either stores the mapping table to ﬂash memory or records
memory contains previously written data, it must be erased in
the logical sector number in the spare area upon each write oper-
units of blocks before new data overwrites the existing data. The
ation to the sector area.
FTL algorithm produces a physical sector number in ﬂash memory
from the logical sector number given by the ﬁle system.
3.1.2. Block mapping
As the sector mapping algorithm requires a large amount of
2.2. FTL functionalities
memory space (RAM), it is hardly feasible for small embedded sys-
tems. For this reason, block mapping-based FTL algorithms [2,6,13]
An FTL algorithm should provide the following functionalities:
are proposed. Some detailed algorithms will be presented in Sec-
tion 4. The basic idea of block mapping is that the logical sector off-
Logical-to-physical address mapping: The main functionality of
set within a logical block is identical to the physical sector offset
an FTL algorithm is to convert logical addresses from the ﬁle sys-
within the physical block.
tem to physical addresses in ﬂash memory.
In the block mapping scheme, if there are m logical blocks de-
Power-off recovery: Even when a sudden power-off event occurs
tected by the ﬁle system, the row size of the logical-to-physical
during FTL operations, FTL data structures should be preserved
mapping table is m. Fig. 3 shows an example of the block mapping
and data consistency should be guaranteed.
algorithm. Assuming that there are four logical blocks, the row size
Wear-leveling: FTL should include a wear-leveling function to
of the mapping table is four. If the ﬁle system issues the command
wear down memory blocks as evenly as possible.
‘‘write(9, A)”, the FTL algorithm calculates logical block number
2(=9/4) and sector offset 1(=9%4), and then locates physical block
number 1 using the mapping table. As the physical sector offset
3. A taxonomy for FTL algorithms
equals the logical sector offset in the block mapping algorithm,
the physical sector location can be easily determined.
In this section, a taxonomy for FTL algorithms is suggested
It is clear that the block mapping algorithm requires a smaller
according to features that include addressing mapping, mapping
amount of mapping information when compared to sector map-
information management, and the size of the RAM table.
ping. However, if the ﬁle system issues write commands with iden-
tical logical sector numbers, many copy and erase operations are
3.1. Addressing mapping
required, which severely degrades performance. When implement-
ing the block mapping algorithm, block-level mapping information
3.1.1. Sector mapping
should be stored in ﬂash memory to recover from a power-off
A naive and intuitive FTL algorithm is the sector mapping algo-
event.
rithm [1]. In sector mapping, every logical sector is mapped to a
corresponding physical sector. Therefore, if there are m logical sec-
3.1.3. Hybrid mapping
tors recognized by the ﬁle system, the row size of the logical-to-
As both sector and block mapping have some disadvantages, as
physical mapping table is m.
mentioned in the previous two subsections, hybrid mapping ap-
Fig. 2 shows an example of sector mapping. In the example, it
proaches were introduced [9,10,14]. A hybrid technique, as its
is assumed that a block is composed of four pages, resulting in 16

3.
334 T.-S. Chung et al. / Journal of Systems Architecture 55 (2009) 332–343
lsn: logical sector number
psn: physical sector number
sector area spare area
lsn psn psn 0
psn 1 Block 0
psn 2
A
“write(9, A)”
… Block 1
Block 2
Block 3
mapping table psn 15
flash memory
Fig. 2. Sector mapping.
sector area spare area
lbn: logical block number
pbn : physical block number psn 0
psn 1 Block 0
psn 2
“write(9, A)” … A Block 1
lbn pbn
lbn: 9/4 =2
offset: 1 pbn: 1 Block 2
offset: 1
mapping table
Block 3
psn 15
flash memory
Fig. 3. Block mapping.
name suggests, ﬁrst uses a block mapping technique to obtain the 3.1.4. Comparison
corresponding physical block. It, then, uses a sector mapping tech- The performance levels of FTL algorithms are compared in
nique to locate an available empty sector within the physical block. terms of the ﬁle system-issued read/write performance and mem-
Fig. 4 shows an example of the hybrid technique. When the ﬁle ory requirements to store the mapping information.
system issues the command ‘‘write(9,A)”, the FTL algorithm calcu- The read/write performance of an FTL algorithm can be mea-
lates the logical block number 2(=9/4) for the lsn, and then, locates sured according to the number of ﬂash I/O operations (read, write,
physical block number 1 from the mapping table. After obtaining and erase), as the read/write performance is I/O-bounded. It is as-
the physical block number, the FTL algorithm allocates an empty sumed here that the mapping table of an FTL algorithm is main-
sector for the update. In the example, because the ﬁrst sector of tained in RAM, and that access cost of the mapping table is zero.
physical block 1 is empty, the data is written to the ﬁrst sector The read and write costs can then be computed using, respectively,
location. In this case, in that the two logical and physical sector off- the following two equations. Though the following equations are
sets (i.e., 1 and 0, respectively) differ from each other, logical sector general, they can be a starting point in design and analysis of FTL
number 9 should be written to the spare area in page 0 of physical algorithms.
block 1. To rebuild the mapping table, not only this information but
also the logical block numbers have to be recorded in the spare C read ¼ xT r ð1Þ
areas of the physical blocks. C write ¼ pi T w þ po ðxT r þ T w Þ þ pe ðT e þ T w þ T c Þ ð2Þ
When reading data from ﬂash memory, the FTL algorithm ﬁrst
locates the physical block number from the mapping table using C read and C write denote the costs of the read and write commands is-
the given lsn. Subsequently, by reading the logical sector numbers sued from the ﬁle system layer, respectively. T r , T w , and T e are the
from the spare areas of the physical block, it can obtain the most costs of the read, write, and erase commands processed in the ﬂash
recent value for the requested data. memory layer.

4.
T.-S. Chung et al. / Journal of Systems Architecture 55 (2009) 332–343 335
psn 0
psn 1 Block 0
psn 2
lbn pbn A 9
“write(9, A)”
… Block 1
lbn: 9/4 =2
lsn: 9 pbn: 1
lsn: 9
mapping table Block 2
Block 3
psn 15
flash memory
Fig. 4. Hybrid mapping.
When reading, variable x in Eq. (1) is 1 in the sector and block It is clear that block mapping requires the smallest amount of
mapping techniques, as the sector to be read can be determined RAM memory as expected.
directly from the mapping table. However, in the hybrid technique,
the value of variable x ranges from 1 6 x 6 n, where n is the num- 3.2. Managing address mapping information
ber of sectors within a block. Here, the requested data can be read
only after scanning the logical sector numbers stored in the spare When implementing an FTL algorithm, it is necessary to con-
areas of a physical block. Thus, the hybrid mapping scheme has a sider a scheme to store mapping information. To be able to rebuild
higher read cost compared to the sector and the block mapping the mapping table during a power-on process, mapping informa-
techniques. tion should not be lost in the sudden power-off events, therefore
During a write operation, there are three cases. First, the write this information must be persistently kept somewhere in ﬂash
operation may be performed in the in-place location directly. pi memory. The techniques for storing mapping information in ﬂash
is the probability that a write request is performed in the in-place memory can be classiﬁed into two categories: the map block meth-
location. Second, the write operation should be performed after od and the per block method.
scanning the empty position in a block. po is the probability of this
event. In this case, additional read operations may be required. Fi- 3.2.1. Map block method
nally, the write operation may incur an erase operation. When a A map block method stores mapping information into some
write request incurs an erase operation, it is assumed that FTL dedicated blocks of ﬂash memory termed map blocks. Though a
algorithms perform in as follows: First, valid data in the block to block can sufﬁciently store all mapping information in the case
be erased is copied to another block that is a free block, and is cop- of block mapping, most FTL implementations provide more than
ied back to a new block (T c ). Second, the write operation is per- one map block. If one map block is used, erase operations on the
formed (T w ), third, the mapping table is changed accordingly; map block occur very frequently. Hence, several map blocks are
and fourth, the source block is erased (T e ). used to lessen such frequent erases. Fig. 6 shows how map blocks
Given that T e and T c are high cost operations relative to T r and can be conﬁgured to store the mapping information for a block
T w , the variable pe is a key point when computing the write cost. In mapping scheme. Mapping information – pairs of a logical block
sector mapping, the probability of requiring an erase operation per number and a physical block number – is recorded to one of the
write is relatively low, in block mapping, conversely, it is relatively unused sectors in the latest map block. Physical block numbers
high. are stored in the sector in the order of the logical block number.
Another measure of comparison is the memory requirement for Of course, if one sector cannot sufﬁciently store all physical block
storing mapping information. Mapping information should be numbers, two or more sectors are used.
stored in persistent storage, and it can be cashed in RAM for better If mapping information changes due to writes issued by the ﬁle
performance. Some FTL algorithms use combinations of sector, system, the above recording job will be done. When performing the
block, and hybrid mapping in the previous section. However, this recording job, if there is no unused sector in the map blocks pool,
paper assumes that each FTL algorithm is used in the overall ﬂash erase operations have to be executed to free some map blocks. The
memory system in the following analysis. Fig. 5 shows such mem- mapping table can be cached in RAM for fast mapping lookups. In
ory requirements for the three address mapping techniques. Here, this case, the mapping table has to be rebuilt in RAM by reading the
we assume that the capacities of ﬂash memory are 128 MB (with latest sector of the latest map block from ﬂash memory during a
8192 blocks) and 8 GB (524288 blocks). Furthermore, each block power-on process.
is composed of 32 sectors [5]. In sector mapping, three bytes are
needed to represent all sector numbers in both 128 MB and 8 GB 3.2.2. Per block method
ﬂash memory, whereas in block mapping, only two bytes are Mapping information can be stored to each physical block of
needed to represent all block numbers in 128 MB ﬂash memory ﬂash memory. This process assumes that hybrid mapping is being
and three bytes in 8 GB ﬂash memory. Hybrid mapping requires used in Fig. 7. In contrast to the map block method, logical block
two bytes for block mapping and one byte for sector mapping numbers are stored in the spare area of the ﬁrst page of each phys-
within a block in 128 MB ﬂash memory. In 8 GB ﬂash memory, ical block. In addition, to maintain the mapping from a logical
three bytes for block mapping and one byte for sector mapping. sector number to the sectors in a physical block, logical sector

5.
336 T.-S. Chung et al. / Journal of Systems Architecture 55 (2009) 332–343
Bytes for
Total
addressing
128MB 8GB 128MB 8GB
Sector 3B 3B 3B*8192*32=768KB 3B*524288*32=48MB
mapping
Block 2B 3B 2B*8192=16KB 3B*524288=1536KB
mapping
Hybrid (2+1) B (3+1) B 2B*8192+1B*32*8192=272KB 3B*524288+1B*32*524288
mapping =17920KB
Fig. 5. Memory requirement for mapping information.
pbn1 pbn2 smaller the RAM size, the lower the system cost. However, if a sys-
tem has enough RAM, performance can be improved. FTL algo-
rithms have their own RAM structures and the FTL algorithms
can be classiﬁed according to their RAM structures. RAM is used
map … to store following information of FTL algorithms.
block 1
Logical-to-physical mapping information: The major usage of
map RAM is to store the logical-to-physical mapping information.
block 2 By accessing RAM, the physical ﬂash memory location for read-
ing or writing data can be found efﬁciently.
Free memory space information: Once free memory space infor-
mation in ﬂash memory is stored in RAM, an FTL algorithm can
manage the memory space without further ﬂash memory
map accesses.
block n Information for wear-leveling: Wear-leveling information may
be stored in RAM. For example, the erase count of ﬂash memory
flash memory blocks may be stored in RAM.
Fig. 6. Map block method.
For example, Fig. 8 shows an example of a RAM table [6]. The
ﬂash memory block of this system is composed of 16 sectors. In
lbn3
the example, a 1:2 block mapping method is used. That is, a logical
block can be mapped to at most two physical block of ﬂash mem-
block 0
ory. PBN1 and PBN2 show the ﬁrst and second physical block ad-
dresses. Logical block 00 is mapped to physical blocks 00 and 10
lbn2 in Fig. 8. The right side of Fig. 8 shows where the valid data is
block 1 stored. For example, sector 0 of logical block 00 is stored in sector
0 of physical block 10.
In the example RAM table, several ﬂags are used. The ‘move’ ﬂag
indicates that some sectors of one block are stored in another
block. The ‘used’ ﬂag shows that a block is being used. The ‘old’ ﬂag
shows that data in a block is no longer valid, and the ‘defect’ ﬂag
lbnk shows that a block is a bad block.
block n
4. Case study
flash memory 4.1. Mitsubishi
Fig. 7. Per block method.
The Mitsubishi algorithm [13] is based on block mapping in Sec-
tion 3.1.2. Its goal was to overcome the limitations of the sector
numbers are recorded in each sector in the block. When rebuilding mapping scheme, that is, (1) the large storage necessary for the
the mapping table due to a power-off event, both the logical block map table, (2) the high overhead of the map table construction cost
numbers and logical sector numbers in the spare areas of ﬂash when the power is turned on. One logical block is mapped to one
memory are used. physical block, representing 1:1 block mapping. Compared to the
In Fig. 7, logical block number 3 is mapped to physical block block mapping technique in Section 3.1.2, the Mitsubishi technique
number 0, logical block number 2 to physical block number 1, suggested a concept of space sectors. That is, a physical block is
and so on. composed of a general sector area and a space sector area. If a
logical block consists of m sectors, a physical block consists of m
3.3. RAM table sectors and some additional n space sectors. Here, the physical sec-
tor offsets and the logical sector offsets are identical in the general
The size of the RAM is very important in designing FTL algo- sector area, and the offsets of the space sectors need not be
rithms because it is a key factor in the overall system cost. The identical.

6.
T.-S. Chung et al. / Journal of Systems Architecture 55 (2009) 332–343 337
Fig. 8. RAM table.
block-level mapping
table
write(0, A)
write(1, B) lbn pbn1
write(2, C)
write(3, D) 0 9
sequence of writes write(4, E) 1 10
from file system write(5, F)
write(0, G) 2 11
write(1, H)
… … …
pbn=9 pbn=10 pbn=11 pbn=12
… A B G H C D E F … Sector area
0 1 Spare area
general space
sector sector
Fig. 9. Running example: Mitsubishi.
Fig. 9 shows an example. This example assumes that a physical A reorganization process is as follows. The FTL algorithm ob-
block is composed of two general sectors and two space sectors. tains a free block and copies valid sectors from the old physical
When processing the ﬁrst write request ‘write(0, A)’, the logical block to the new block. The content of the logical/physical conver-
block number 0(=0/2) and the logical page offset 0(=0%2) are calcu- sion table is changed appropriately. After the sectors in the original
lated and the physical block number (9) is obtained using the physical block are completely transferred to the new block, the
block-level mapping table. As physical page offset 0 of pbn ¼ 9 is original block is erased and returned to the free block list. The
empty initially, the data A is written to the ﬁrst sector location of Mitsubishi scheme always keeps at least one free block for
pbn ¼ 9. Additional write operations are performed in the same reorganization.
way. When processing the write request of ‘write(0, G)’, as the The Mitsubishi scheme uses the map block method in Section
physical page offset 0 of pbn ¼ 9 is already occupied, it is written 3.2.1 for the mapping information; the size of the conversion table
to the ﬁrst space sector area. In this case, the logical sector number is relatively small as it is based on block mapping.
(0) is written to the spare area of ﬂash memory. In the pure block
mapping technique, the ‘write(0, G)’ request incurs a copy and 4.2. M-systems
erase operation. When reading the logical sector number 0, the
most up-to-date version can be found by scanning the spare areas M-systems proposed the algorithms known as ANAND and
of ﬂash memory. FMAX for ﬂash memory management systems. Basically, their

7.
338 T.-S. Chung et al. / Journal of Systems Architecture 55 (2009) 332–343
block-level mapping
table
write(4, A)
write(5, B) lbn pbn1 pbn2
write(6, C)
write(7, D) 0 5 6
sequence of writes write(8, E) 1 10 11
from file system write(9, F)
write(8, G) 2 12 9
write(8, H)
… … … …
pbn=9 pbn=10 pbn=11 pbn=12
… G H A B C D E F … Sector area
8 Spare area
Fig. 10. Running example: M-Systems.
techniques are also based on the block mapping technique. How- Fig. 11 shows a running example (clustered mode). It is as-
ever, compared to the block mapping technique in Section 3.1.2, sumed here that a physical block is composed of four sectors.
in their schemes, one logical block can be mapped to more than When processing the ﬁrst write request ‘write(5, A)’, the logical
one physical block. As the basic structure of ANAND is similar to block number 1(=5/4) is calculated, and the physical block number
that of FMAX, only the FMAX algorithm is explained in this paper. (10) is then obtained using a block-level mapping table. As the
In FMAX, one logical block can be mapped to the two physical physical page offset 0 of pbn ¼ 10 is empty initially, the data A is
blocks known as primary block and a replacement block. Here, written to the ﬁrst sector location of pbn ¼ 10 and the logical sec-
the logical sector offset is identical to the physical sector offset in tor number (5) is written to a spare area in ﬂash memory. In SSR,
the primary block. However, in the replacement block, the logical the logical sector offset need not be identical to the physical sector
sector offset may differ from the physical sector offset. offset. Thus, the logical sector number should be written to the
Fig. 10 shows an example. This example assumes, that a physi- spare area of ﬂash memory. More write operations are performed
cal block is composed of four sectors. When processing the ﬁrst in the same way. When the read operation is performed, if there
write request ‘write(4, A)’, the logical block number 1(=4/4) and is more than one instance of data with the same logical sector
the logical page offset 0(=4%4) are calculated, and the physical number, the most recent data is the ﬁrst sector from the back
block number (10) is obtained using the block-level mapping table. end of the block. In the example, the valid data corresponding to
Given that the physical page offset 0 of pbn ¼ 10’s is empty ini- logical sector number 9 is the fourth data (H) of pbn ¼ 11. If a phys-
tially, the data A is written to the ﬁrst sector location of pbn ¼ ical block has no free sectors, copy and erase operation are
10. Additional write operations are performed in the same way. preformed.
When processing the write request of ‘write(8, G)’, as pbn ¼ 12 is
already occupied, the write request is performed in the second 4.4. Log block scheme
physical block (pbn ¼ 9). If the second physical block has no free
sectors, copy and the erase operation are performed. Kim et al. [9] proposed a log block based FTL scheme. The main
FMAX uses the per-block method to store mapping information. objective of this scheme is to efﬁciently handle both access pat-
In addition, FMAX manages a RAM table to map a logical block to terns efﬁciently: numerous long sequential writes and a small
two physical blocks. This requires more RAM size compared to number of random overwrite operations. To achieve this purpose,
the block mapping in Section 3.1.2. the log block scheme maintains most of the physical blocks at
the block addressing level – data blocks – and a small ﬁxed number
4.3. SSR of physical blocks at the sector addressing level – log blocks. Data
blocks mainly use storage spaces for long sequential writes and log
SSR [14] uses the hybrid address mapping scheme in Section blocks for random overwrites. Once a sector is initially written to a
3.1.3. Compared to the previous techniques, the inventors of SSR data block, a overwrite operation to the same logical sector is for-
provide two hash functions when determining a logical block num- warded to a log block that has been allocated from a pool of log
ber from a logical sector number. The hash functions are as follows. blocks. All subsequent overwrites to the same logical sector are
In the equations, lsn is the logical sector number and ns is the num- then processed using the log block. If there are no free sectors in
ber of sectors in a block. the log block, data of the log block is merged to that of correspond-
ing data block and the log block is returned to the pool of log blocks
H1ðlsnÞ ¼ lsn=ns ¼ lbn ð3Þ for later overwrites.
H2ðlsnÞ ¼ lsn%ns ¼ lbn ð4Þ If the FTL algorithm cannot locate any free log blocks for the
overwrite, it ﬁrst chooses a victim log block among the log blocks
The SSR algorithms based on the hash functions H1 and H2 are in use, and data of the victim log block is merged with that of cor-
known as a ‘‘clustered mode” and a ‘‘scattered mode” respectively. responding data block. The victim log block is then erased and ﬁ-
Previous FTL algorithms are based on the hash function H1. nally allocated for the current overwrite.

8.
T.-S. Chung et al. / Journal of Systems Architecture 55 (2009) 332–343 339
block-level mapping
table
write(5, A)
lbn pbn1
write(4, B)
write(6, C)
write(7, D) 0 5
sequence of writes write(8, E) 1 10
from file system write(9, F)
write(8, G) 2 11
write(9, H)
… … …
pbn=9 pbn=10 pbn=11 pbn=12
… A B C D E F G H … Sector area
5 4 6 7 8 9 8 9 Spare area
Fig. 11. Running example: SSR.
For address mapping, the log block scheme maintains two dif- It is assumed that the ﬁle system layer in Fig. 1 is the FAT ﬁle
ferent types of mapping tables in RAM: the ﬁrst is a block mapping system [4], which is widely used in many embedded systems.
table for data blocks and the second is a sector mapping table for Fig. 13 shows the disk format of the FAT ﬁle system. It includes a
log blocks. boot sector, one or more ﬁle allocation tables, a root directory,
Fig. 12 shows an example. This example, assumes that a physi- and the volume ﬁles. A recent study [4] contains a more detailed
cal block is composed of four sectors. When processing the ﬁrst description of the FAT ﬁle system. Here, it is clear that logical
write request ‘write(4, A)’, the logical block number 1(=4/4) and spaces corresponding to the boot sector, ﬁle allocation tables,
the logical page offset 0(=4%4) are calculated and the physical and the root directory are accessed more frequently compared to
block number (10) is obtained using the block-level mapping table. the volume ﬁles.
As the physical page offset 0 of pbn ¼ 10 is empty initially, the data For the simulation, various access patterns that the FAT ﬁle sys-
A is written to the ﬁrst sector location of pbn ¼ 10. When process- tem issues to the block device driver when it receives a ﬁle write
ing the write request of ‘write(4, C)’, given that the physical page request were obtained. The performance results over real work-
offset 0 of pbn ¼ 10 is already occupied, it is written to log block loads of Symbian [15] and Digicam are reported. The ﬁrst of these
pbn ¼ 20. The logical sector offset need not be identical to the is the workload of a 1M byte ﬁle copy operation in the Symbian
physical sector offset; hence, the logical sector number is written operating system, and the second is the workload of a digital cam-
to the spare area of ﬂash memory. For the log blocks, the sector-le- era. It was found that the access pattern of Digicam is mostly
vel mapping table is constructed as in Fig. 12. More write opera- sequential while that of Symbian has many random patterns. In de-
tions are performed in the same way. tail, the access pattern of Digicam contains small random writes
In the log block scheme, the map block method of Section 3.2.1 and frequent large sequential writes. On the other hand, the access
is adopted to manage the mapping information. The aforemen- pattern of Symbian contains many random writes and infrequent
tioned block mapping table for data blocks is stored into one of large sequential writes.
the map blocks. To obtain the latest version of the block mapping
table in the pool of map blocks, a map directory is maintained in 5.2. Result
RAM. For recovery from a power-off event, the map directory is
also stored in a speciﬁc block of ﬂash memory (a checkpoint block) Fig. 14 shows the total elapsed time for the Digicam pattern.
whenever the sector mapping table for log blocks is updated. The x axis is the test count that is the iteration count of workloads
Recently, some variations of the log scheme, including those and the y axis is the total elapsed time in milliseconds. As the size
known as FAST [11] and STAFF [3] have been proposed. In the FAST of this workload is small, ﬂash memory is not occupied after per-
scheme, more than one logical block can be mapped to a physical forming the workload one time. Thus, to determine the character-
block, which improves the space utilization of a log block. The istics of FTL algorithms when ﬂash memory is occupied, the
key idea of STAFF is to minimize the erase operation by introducing processing of the workloads was done many times. Initially, the
states that are assigned to blocks and used to control address map- ﬂash memory was empty. It became occupied as the test count
ping. The detailed algorithms are omitted due to a lack of space. increased.
The result shows that the Log scheme provides the best perfor-
5. Evaluation mance. It is interesting that the Log scheme shows better perfor-
mance than sector mapping which requires a considerable
5.1. Simulation methodology amount of RAM resources for mapping. This can be explained in
that the workload of the Digicam is mostly composed of sequential
In the overall ﬂash system architecture presented in Fig. 1, the write operations. Moreover, the Log scheme operates almost ide-
FTL algorithms presented in Section 4 are implemented. The phys- ally in the sequential write patterns. As sector mapping uses the
ical ﬂash memory layer is simulated by a ﬂash emulator that has LSN-to-PSN mapping table, it must update the mapping table with
the same characteristics as a real ﬂash memory. every overwrite operation. This implies that it has to write the

10.
T.-S. Chung et al. / Journal of Systems Architecture 55 (2009) 332–343 341
mapping scheme incurs less erase operations (Fig. 15, it has a long- writes, the merging algorithm of the Log scheme is more efﬁcient
er overall execution time than the Log scheme. than the Mitsubishi and FMAX schemes.
The SSR technique shows the poor performance compared to Fig. 15 shows the erase count. The result is similar to the result
the other techniques because one logical block is mapped to only of the total elapsed time because the erase count is the most dom-
one physical block in the SSR technique. In particular, when erasing inant factor in the overall system performance. A recent study [5]
a block in the SSR technique, as many valid sectors exist in the found a running time ratio of read (1 page), write (1 page), and
erased block, many copy operations are necessary and the proba- erase (1 block) is approximately 1:7:63. It is clear that the sector
bility that the erased block will be erased again in the future is very mapping requires the smallest erase counts. In the sector mapping
high. By allowing a logical block to be mapped to more than one scheme, a logical sector can be mapped to any free physical sector.
block (as in the Log scheme and FMAX), FTL algorithms have better Most of the blocks are either full of invalid blocks or full of valid
performance. In the Mitsubishi technique, a logical block can be blocks. Therefore merge operations between blocks with valid sec-
mapped to a physical block. However, space sectors play the role tors are uncommon, causing fewer erase operations.
of another block. Additionally, in the Mitsubishi technique, there Fig. 16 and Fig. 17 show the performance result in the Symbian
is a periodic drop in the total elapsed time because the same work- workload. In the Symbian workload, the sector mapping shows
load is performed repeatedly and many merge operations are peri- the best performance. This result comes from the fact that
odically required. The Log scheme shows better performance than the workload of Symbian, in contrast to that of Digicam, has
FMAX and Mitsubishi; as there are a few log blocks for random many random write operations. Thus, in the Log scheme, erase
The erase count
FMAX
LOG
MSBS
100000 SSR
Sector
Count
10000
1000
0 20 40 60 80 100
Test count
Fig. 15. Digicam: The total erase counts.
The total elapsed time
FMAX
LOG
MSBS
SSR
Sector
100000
Elapsed time (ms)
10000
1000
0 20 40 60 80 100
Test count
Fig. 16. Symbian: The total elapsed time.

11.
342 T.-S. Chung et al. / Journal of Systems Architecture 55 (2009) 332–343
The erase count
10000
FMAX
LOG
MSBS
SSR
Sector
Count
1000
100
0 20 40 60 80 100
Test count
Fig. 17. Symbian: The total erase counts.
operations occur frequently compared to the sector mapping. In a future study, intensive workloads in real embedded appli-
Particularly, there is a lack of points in sector mapping, as shown cations will be generated and the theoretical performance opti-
in Fig. 17, due to the full-associativity of the sector mapping mum for ﬂash memory will be explored under a given workload.
scheme.
Acknowledgements
6. Conclusion This work was supported in part by the Defense Acquisition
Program Administration and Agency for Defense Development
This paper surveys state-of-the-art FTL algorithms. A taxonomy under Contract Number UD060048AD, was partly supported by
of FTL algorithms is provided based on sector, block, and hybrid ad- MKE, Korea under ITRC IITA-2009-(C1090-0902-0046) and also
dress mapping. To overcome the ‘‘erase before write” architecture, supported partly by KRF, Korea under KRF-2008-0641.
the sector mapping scheme shows the best performance in that it
can delay the erase operation as much as possible if there are free
References
sectors in ﬂash memory. However, because the sector mapping
scheme requires a considerable amount of mapping information, [1] Amir Ban, Flash File System, United States Patent, No. 5,404,485, 1995.
it is not be applicable in embedded applications. Thus, the block [2] Amir Ban, Flash File System Optimized for Page-mode Flash Technologies,
mapping and the hybrid scheme are addressed. The block mapping United States Patent, No. 5,937,425, 1999.
[3] Tae-Sun Chung, Hyung-Seok Park, STAFF: a ﬂash driver algorithm minimizing
scheme requires the least mapping information. However, it shows block erasures, Journal of Systems Architecture 53 (12) (2007).
very poor performance when the same logical sector numbers are [4] Microsoft Corporation, Fat32 File System Speciﬁcation, Technical Report,
frequently updated. The hybrid mapping scheme overcomes the Microsoft Corporation, 2000.
[5] Samsung Electronics, Nand Flash Memory Smartmedia Data Book, 2007.
problems of ‘updating the same logical sector numbers frequently’
[6] Petro Estakhri, Berhanu Iman, Moving sequential sectors within a block of
but requires more mapping information than the block mapping information in a ﬂash memory mass storage architecture, United States Patent,
scheme. No. 5,930,815, 1999.
Another issue when designing FTL algorithms involves manag- [7] Eran Gal, Sivan Toledo, Algorithms and data structures for ﬂash memories,
ACM Computing Surveys 37 (2) (2005) 123.
ing mapping information. Current FTL techniques can be classiﬁed [8] A. Kawaguchi, S. Nishioka, H. Motoda, Flash Memory based File System, in:
into the map block and the per block method. The map block meth- USENIX 1995 Winter Technical Conference, 1995.
od requires number of dedicated blocks to store mapping informa- [9] Jesung Kim, Jong Min Kim, Sam H. Noh, Sang Lyul Min, Yookun Cho, A space-
efﬁcient ﬂash translation layer for compactﬂash systems, IEEE Transactions on
tion, whereas the per block method stores mapping information in Consumer Electronics 48 (2) (2002).
each block of ﬂash memory. When implementing FTL algorithms, [10] Se Jin Kwon, Tae-Sun Chung, An efﬁcient and advanced space-management
the RAM usage is also important. Current FTL algorithms use technique for ﬂash memory using reallocation blocks, IEEE Transaction on
Transactions on Consumer Electronics 54 (2) (2008).
RAM to the store information of logical-to-physical mapping, of [11] Sang-Won Lee, Dong-Joo Park, Tae-Sun Chung, Dong-Ho Lee, Sangwon Park,
free memory space, and of wear-leveling. Ha-Joo Song, Log buffer based ﬂash translation layer using fully associative
Various FTL algorithms, in this case FMAX, sector mapping, Log sector translation, ACM Transactions on Embedded Computing Systems 6 (3)
(2007).
scheme, SSR, and Mitsubishi were implemented, and the perfor- [12] M. Resenblum, J. Ousterhout, The design and implementation of a log-
mance results were shown. If one logical block is mapped to only structured ﬁle system, ACM Transactions on Computer Systems 10 (1) (1992).
one physical block (as in SSR), it is clear that the FTL performance [13] Takayuki Shinohara, Flash Memory Card with Block Memory Address
Arrangement, United States Patent, No. 5,905,993, 1999.
is poor. Using space sectors (Mitsubishi) and replacement blocks
[14] Bum Soo Kim, Gui Young Lee. Method of Driving Remapping in Flash Memory
(FMAX), the FTL performance can be improved. If a logical block and Flash Memory Architecture Suitable Therefore, United States Patent, No.
can be mapped to more than one block in FTL algorithms, the 6,381,176, 2002.
merging operation becomes a key factor in the overall perfor- [15] Symbian, 2007, http://www.symbian.com.
[16] M. Wu, W. Zwaenepoel, eNVy: a non-volatile, main memory storage system,
mance. The Log scheme shows a good solution with its use small in: International Conference on Architectural Support for Programming
log blocks and many data blocks. Languages and Operating Systems, 1994.

12.
T.-S. Chung et al. / Journal of Systems Architecture 55 (2009) 332–343 343
Tae-Sun Chung received the B.S. degree in Computer Dong-Ho Lee received the BS degree from Hong-Ik
Science from KAIST, in February 1995, and the M.S. and University, and the MS and PhD degrees in computer
Ph.D. degree in Computer Science from Seoul National engineering from Seoul National University, South
University, in February 1997 and August 2002, respec- Korea, in 1995, 1997, and 2001, respectively. From 2001
tively. He is currently an associate professor at School of until 2004, he worked in software center, SAMSUNG
Information and Computer Engineering at Ajou Uni- Electronics Ltd., where he was involved in several digital
versity. His current research interests include ﬂash TV projects. He is currently an assistant professor in
memory storages, XML databases, and database Department of Computer Science and Engineering at
systems. Hanyang University, South Korea. His research interests
include system software for ﬂash memory, embedded
database systems, and multimedia information retrieval
systems.
Dong-Joo Park received the B.S. and M.S. degrees in the Sang-Won Lee is an associate professor with the School
Computer Engineering Department from Seoul National of Information and Communication Engineering at
University, February 1995 and February 1997, respec- Sungkyunkwan University, Suwon, South Korea. Before
tively, and the Ph.D. degree in School of CSE from Seoul that, he was a research professor at Ewha Womans
National University, August 2001. He is currently an University and a technical staff at Oracle, Korea. He
assistant professor in School of Computing at Soongsil received a Ph.D. degree from the Computer Science
University. His research interests include ﬂash memory- Department of Seoul National University in 1999. His
based DBMSs, multimedia databases, and database research interest is in ﬂash-based database technology.
systems. He can be reached at swlee@skku.edu.
Sangwon Park received the B.S. and M.S. degrees in the Ha-Joo Song received the B.S. and M.S. degrees in the
Computer Engineering Department from Seoul National Computer Engineering Department from Seoul National
University, February 1995 and February 1997, respec- University, February 1993and February 1995, respec-
tively, and the Ph.D. degree in School of CSE from Seoul tively, and the Ph.D. degree in School of CSE from Seoul
National University, February 2002. He is currently an National University, August 2000. He is currently an
associate professor in Hankuk University of Foreign assistant professor in Pukyong National University. His
Studies. His research interests include ﬂash memory- research interests include ﬂash memory based database
based DBMSs, multimedia databases, and database systems and sensor networks.
systems.