Energy Consumption Modeling and Optimization for SRAMs

This thesis
is the second in a series that will be made available on this server.

The recent trends in portable computing technologies have established the
need for energy efficient design strategies to maximize the operation time
available between rechargings of the battery systems. There has been a
significant amount of work directed at reducing the energy consumption
through system level design changes. Opportunities exist for improving the
energy consumption at the circuit level by altering the individual
architectures and circuit designs of the CMOS chips.

To achieve these minimum energy design goals, system designers need a
technique to accurately model the energy consumption of their design
alternatives without performing a full physical design and full-circuit
simulation. This technique must provide the designer with the appropriate
amount of modeling detail to achieve their required accuracy goals while
minimizing the development effort.

This dissertation presents and compares five approaches for modeling the
energy consumption of CMOS circuits. These five modeling approaches have
been chosen to represent the various levels of model complexity and
accuracy found in the current literature. These modeling approaches are
applied to the energy consumption of SRAMs to provide examples of their use
and to allow for the comparison of their modeling qualities.

A mixed characterization model, built from a simple CV^2 energy model on
digital- behavior circuit subsections, and circuit simulations on
analog-behavior subsections, is best to use for estimations of the absolute
energy consumption of a circuit. The mixed characterization model is also
the best for predictions of the optimum organizations for minimizing the
energy consumption in a given circuit.

The optimum organizations for minimized energy consumption in our SRAM
designs are found to be non-square, containing more rows than columns. As
the size and density of the memories increase, the number of rows and
subarrays increases while the number of columns remains small. The scaling
of the technology to smaller feature sizes does not affect the optimum
energy organization. The optimum organizations for minimizing the memory
access time are much more square (more equal number of rows and columns)
than those for minimizing the energy consumption. The choice of the optimum
energy organization will result in a significant tradeoff in the access
time of the device.

An analysis of several common architectures and circuit designs for SRAMs
shows that global, rather than local improvements, produce the largest
energy savings. The best architecture determined for our process is a
Multiplexed Internal Address Lines design, which distributes the internal
address lines to the subarrays through a multiplexor, as opposed to the
usual bussing architecture. The best architecture for minimizing the access
time of the memory is also the Multiplexed design. Multi-bit word
organizations produce a savings in the energy per bit read, suggesting that
the energy consumption can be further optimized by placing as many bits per
word accessed in the same physical memory device. Sequential-address
access memories do not provide a significant energy savings over
singly-addressed devices, although they can save energy at the system
level. Sharing sense amps amongst multiple columns and subarrays will lead
to a small energy savings, but this should ideally be minimized as the
speed penalty is substantial.

The best precharge design for minimizing energy consumption contains two
strong pullup transistors to limit the voltage swing of the column lines
during the read cycles. The through-current associated with the pullup
transistors during the read/write cycles is not significant in the
selection of an optimum design. For timing considerations, the best
precharge designs contain no pullup transistors, which produces the fastest
bitline voltage response.

The analysis of the standard SRAM decoder circuits shows that the best
design is an intermixed repeater/driver design, with the rows/columns
physically arranged in Gray Coding order. These decoder design options
offer no improvements in the time delay through the decoder stages of the
device.