Reproduction micros

> On Jul 22, 2016, at 8:10 PM, Cameron Kaiser <spectre at floodgap.com> wrote:
>>>> It's not. Peter is talking about a four-bit field in the
>>> instructions. You're talking about a six-bit field in the program
>>> counter.
>>>> Something that's always bothered me about three-address architectures
>> like ARM is why there is the insistence on that scheduling bottleneck,
>> the condition code register? You can see how two-address architectures
>> like the x80 and x86 try to get around the problem by having certain
>> instructions not modify certain condition code bits
>> I realize I'm a broken record here, but PowerPC does the same thing.
It seems that a great many things that some modern reporter thinks are new, or recent, and unusual, have been done in any number of places. And possibly (as in this case) at least 20 years earlier than the reporter is aware of.
paul