Abstract

Healthcare issues arose from population aging. Meanwhile, electrocardiogram (ECG) is a powerful measurement tool. The first step of ECG is to detect QRS complexes. A state-of-the-art QRS detection algorithm was modified and implemented to an application-specific integrated circuit (ASIC). By the dedicated architecture design, the novel ASIC is proposed with 0.68 mm2 core area and 2.21 μW power consumption. It is the smallest QRS detection ASIC based on 0.18 μm technology. In addition, the sensitivity is 95.65% and the positive prediction of the ASIC is 99.36% based on the MIT/BIH arrhythmia database certification.

1. Introduction

Many healthcare issues arose out of population aging [1] and experts hoped to monitor people’s health through various physiological sensors [2]. Electrocardiogram (ECG) is one of the physiological signals [3]. Since the milestone paper proposed in 1996, the study of ECG is still an ongoing hot research topic [4–7]. Some software (S/W) application for ECG analysis had been developed on personal computer (PC) [8].

Figure 1 shows a standard routine of ECG signal processing. The detection of heartbeats (QRS complexes) is the first step, while R is the peak of the complex and heart rate variability (HRV) is the standard deviation of time sequence (RR-intervals). The time domain analysis reports the activity of circulatory system and the frequency domain analysis reflects the sympathovagal balance of autonomic nervous system (ANS) [9–13]. In our previous works, this standard routine had been modified to MATLAB codes [14, 15] and the QRS detection algorithm had also been implemented in field programmable gate array (FPGA) [16].

Beyond PC, mobile phone is another S/W solution [17, 18]. In the other way, the QRS detection algorithm can be found in hardware (H/W) implementations, such as ARM [19], DSP [20, 21], FPGA [22–24], or ASP [25]. For the purpose of long time use, an application-specific integrated circuit (ASIC) solution of real-time and very low-power consumption should be considered. Some previous chip designs were surveyed as the comparison targets [26–38]. We will give a detailed description for our design, which had been presented briefly in 2010 [39], in this paper. For the application, one [27] of above ECG chips had been embedded into a biomedical system already [40].

The remainder of this paper is structured as follows. In Section 2, the algorithm design is briefly described. In Section 3, we state the architecture design. In Section 4, the evaluation and comparison with other designs are discussed. Finally, in Section 5, we summarize this paper and offer directions for future work.

2. Algorithm Design

The ECG signals were captured by a 3-channel portable device (MSI E3-80, FDA proven) at 500 Hz sampling rate in our study. Of all the ECG features, the QRS complex is most notable [41, 42]. There were many QRS detection algorithms in various methods [43–47]. Considered the trade-off among algorithm complexity, robustness, and performance, Hamilton and Tompkins’, a real-time QRS detection algorithm, was chosen and modified for our ASIC implementation [48].

2.1. Overview of the QRS Detection Flow

There are some types of noise appeared in the ECG signals such as 60 Hz from power line, electromyogram (EMG) signals from muscle electrical activity, and motion artifact from the skin and electrode interface. Besides, large P and T waves can also be identified as noise signals when detecting the QRS complexes. Figure 4 in [49] summarizes the relative power spectra of the ECG, QRS complexes, P and T waves, motion artifact, and muscle noise.

The QRS complex is the most significant waveform of the ECG signal. It records the electrical activity of the heartbeat (ventricular contraction). QRS complexes also lead to the determination of the heart rate and other important features of HRV. In other words, QRS detection is the basis for almost all ECG analysis programs [43].

The signal processing flow of QRS detection and the corresponding results are shown in Figures 2 and 3. There are two main stages in the QRS detection flow. One is the preprocessing stage, which is composed of various filters for removing noise and acquiring the QRS complex information. The other stage, peak detection, makes use of the information acquired by the preprocessing stage and some criteria to detect the QRS complex peaks.

2.2. Band-Pass Filter

In the beginning of the preprocessing stage, the band-pass filter is used to reduce the influence of muscle noise, 60 Hz interference, baseline wander, and T-wave interference. The desirable pass-band to maximize the QRS energy is approximately 5–15 Hz [49].

The band-pass filter is composed of cascaded low-pass and high-pass filters. Their difference equations are listed as (1). The amplitude response of the band-pass filter, which is composed of the cascade of the low-pass and high-pass filters, is shown in Figure 4. The center frequency of the pass-band is at 10 Hz. The amplitude response of this filter is designed to approximate the spectrum of the average QRS complex. Thus this filter optimally passes the frequencies characteristic of a QRS complex while attenuating lower and higher frequency signals:

2.3. Derivative

After been filtered, the signal is differentiated to acquire the slope of the QRS complex. This derivative is implemented with the difference equation (2). The performance characteristics of this derivative implementation are shown in Figure 5. The amplitude response approximates a true derivative up to about 20 Hz. This is the important frequency range since all higher frequencies are significantly attenuated by the band-pass filter:

2.4. Square

The signal is squared sequentially after differentiation, as shown in (3). All data points become positive, the output of the derivative is amplified nonlinearly, and the higher frequencies (QRS complexes) are emphasized:

2.5. Moving Window Average

The slope of the R wave alone is not a guaranteed way to detect a QRS event. Many abnormal QRS complexes that have large amplitudes and long durations (not very steep slopes) might not be detected using information about slope of the R wave only. Thus, we need to extract more information from the signal to detect a QRS event. Moving window integration extracts features in addition to the slope of the R wave. It is implemented with the following difference equation (4).

Basically, the window should be selected as the width of the widest possible QRS complex. If the window is too wide, it merges the QRS and T complexes together. If the window is too narrow, some QRS complexes will derive several redundant peaks in the integration waveform. The width of the window should be determined empirically. For our sample rate (500 samples/s), the integration window is 64 samples wide (which correspond to 128 ms):

2.6. Peak Detection

The peak detection stage detects peaks in the signals after moving window average. Four main techniques introduced in Hamilton and Tompkins’ algorithm included ripple-ignored, fiducial mark, adaptive detection threshold, and search back [48]. First three of them were modified for our design of hardware implementation. Details of the peak detection flow are described in the following paragraphs and the flowchart is depicted in Figure 6. Finally, the corresponding relation between ECG raw data and the signals after moving window average is shown in Figure 5 of [48], and the peak detection is shown in Figure 7.

Figure 6: Flowchart of peak detection.

Figure 7: Peak detection after moving window average.

There are three main steps to detect a peak and avoid the ripples around the tops of the peaks.(1)Store the value of one point to local_max.(2)If the value of the newer point is larger than local_max, store it to local_max.(3)If the value of the newer point is smaller than half of local_max, a peak is detected. Otherwise go to step 2.

After a peak is detected, it is classified as either a QRS complex or noise, or it is saved for later classification. This work uses the peak height and peak location to classify peaks. The principles of the basic detection rules in the peak detection stage are listed as follows.(1)To avoid both prominent T waves and multiple detection of QRS waves, ignore all peaks that precede or follow larger peaks by less than a refractory blanking 200 ms [48].(2)The peak is recognized as a QRS complex instead of noise if the peak is larger than the adaptive detection threshold (5). DT means the detection threshold, where TC is the threshold coefficient. NPL is the noise peak level and QRSPL is the QRS peak level. QRSPL is the mean of an 8-point QRS buffer. The buffer collects 8 records of latest QRS peak value, and similarly the noise buffer stores 8 records of latest noise peak value:

Mean, median, and iterative estimators were examined in our reference algorithm [48]. Although the general performance of the median estimator was best, the mean estimator was employed for the easy implementation of hardware design with little loss of performance. After choosing the mean estimator, a value 0.375 for TC was fine tuned according to MIT-BIH database.

3. Architecture Design

Measurement of HRV provides a noninvasive method to obtain reliable information on autonomic modulation of heart rate and has become an important tool for risk assessment to millions of patients who suffer from chronic diseases. A compact, high-accuracy, real-time HRV assessment system could provide a valuable feature for implantable and portable cardiac monitoring and intervention devices. The reliable QRS detection is crucial for HRV analysis. This work focused on the balance among low-power, small area, and high accuracy.

3.1. Accuracy Simulation

For achieving the high-accuracy, the word-length of each processing stage needs to be decided carefully. The word-length of each processing block is shown in Figure 8, where means the word-length is composed of bit integer and bit decimal fraction. The deviation of each processing stage between the software QRS detector and the hardware QRS detector is simulated through all the MIT-BIH Arrhythmia Database. The deviation of detected R peak between the software QRS detector and the hardware QRS detector is shown in Figure 9. It can be seen that the detection results is very close between them. The maximum deviation is 0.00304 samples, it is just 8.45 μs (0.00304/360 = 8.444, 360 Hz sampling rate) differences. So the accuracy of the hardware QRS detector is almost the same as the software QRS detector. The detailed deviation of each record is listed in Table 1.

Table 1: The detailed deviation between the hardware and software QRS detector of each record.

Figure 8: The word-length of each processing block.

Figure 9: The deviation of detected R peak between the software QRS detector and the hardware QRS detector.

The deviation of each processing stage between the software QRS detector and the hardware QRS detector is simulated through all the MIT-BIH Arrhythmia Database, but just first ten minutes data are used to evaluate the QRS detector performance for simplicity. The deviation is represented by averaging the differences of each stage outcomes between the hardware (HDL code in Altera FPGA design kits, DE2, and TS2) and software (MATLAB) simulations.

3.2. Hardware Architecture

As mentioned in Section 2, the QRS detection can be divided into two stages. The preprocessing stage emphasizes the desired components in order to maximize the signal-to-noise ratio. The peak detection stage decides if an incoming peak is a true QRS complex based on a user-specified threshold. It can be seen that the preprocessing stage of the QRS detection algorithm adopted in this study is composed of several digital filters.

The systolic array architecture for these digital filters is adopted in this work [50]. For computing one-dimensional recursive convolution characterized by the transfer function shown as (6), where (for to ) and (for to ) are real coefficients, the array structure shown in Figure 10 can be used to achieve an appropriate trade-off between throughput and the amount of hardware required. Because these digital filters mentioned in (1) and (2) all can be represented as (6), they can be implemented by these continuously connecting array structures.

Figure 10: The systolic array architecture for digital filters.

For reducing the amount of hardware required in the chip, observing the arrangement of the registers shown in Figure 10, it can be found that the area closed by the red rectangular can be used as a basic processing element (PE) in the array. The basic PE can be reused continuously to update the different registers and the same result will be obtained. Observing the difference equations listed in (1) and (2), there are only five possibilities of coefficients. They are 0, 1, −1, 2, and −2. So the four multiplication operation in the PE can be simplified to four shifting operation. The proposed PE reusing architecture is shown in Figure 11 and the final layout and IC package photo of our design are shown in Figure 12.

The procedure for peak detection was described in Section 2.6. According to Figure 6, the procedure was implemented in hardware description language (HDL):

4. Discussion

4.1. MIT-BIH Arrhythmia Database Certification

Many algorithms of HRV analysis, such as heart rate calculation, PAV detection, and PVC detection, require a very accurate QRS recognition capability. Several standard ECG database are available for the evaluation of software QRS detection algorithms. Tests on these well-annotated and validated databases provide reproducible and comparable results. Furthermore, these databases contain many selected signals representative for the large variety observed but clinically important. The MIT-BIH Arrhythmia Database is the most frequently used database. It contains 48 half-hour recordings of annotated ECG with sampling rate of 360 Hz and 11-bit resolution over a 10 mV range. The sampling rate of our 3-channel portable device (MSI E3-80, FDA proven) is 500 Hz. Both kinds of data can be processed by adjusting the system clock of our proposed ASIC. Twenty-five recordings with less common arrhythmias were selected from over 4000 24-hour ambulatory ECG recordings, and the rest was chosen randomly. While some records contain clear R-peaks and few artifacts (e.g., records 100–107), for some records the detection of QRS complexes is very difficult due to abnormal shapes, noise, and artifacts (e.g., records 108 and 207).

The MIT-BIH Arrhythmia Database is acquired from the PhysioNet which offers free access via the web to large collections of recorded physiologic signals and related open-source software. There are forty-eight recordings in this database. Each recording includes annotations that indicate the times of occurrence and types of each individual heart beat (“beat-by-beat annotations”). The standard set of annotation codes includes both beat annotations and nonbeat annotations. According to [51], essentially three parameters should be used to evaluate the QRS detection algorithm. They are formulated as (7) where TP denotes the number of true positive detection, FN denotes the number of false negatives, and FP denotes the number of false positives. Therefore, TP represents the QRS detector successfully detects the beats which are coded by beat annotations, FN represents the QRS detector misses the beats which are coded by beat annotations and FP means the QRS detector detects the beats which are coded by nonbeat annotations or nonexisted actually.

In this study, all the forty-eight recordings in the MIT-BIH Arrhythmia Database are used to evaluate the QRS detector algorithm. Each recording records half-hour annotated ECG, but just first ten minutes data are used to evaluate the QRS detector performance for simplicity. The evaluation result of each recording is listed in Table 2. For the performance measures of the modified algorithm, the sensitivity (Se) is 95.65%, and the positive predictivity () is 99.36%. The average time error is 5.33 ms.

Table 2: The evaluation results of the simplified QRS detector.

4.2. CHIP Comparison

Thirteen QRS detection chip papers were collected in the literature review [26–38], and Table 3 shows the comparison details. There existed two types for these solutions, one is system on chip (SoC) [26–28, 30, 31, 33, 35–37], the other is ASIC [29, 32, 34, 38]. Although dedicated for ECG signal processing, the consideration of these two kinds of design is different. One main target of SoC solutions is flexible, hence the area and power consumption are not the first priority. The area range distribution of SoC is between 1.11 mm2 and 13 mm2, which are larger than our 0.68 mm2 design. Hence we compare our ASIC design with our main competitors (the ASIC solutions) first, with SoC solutions followed.

Table 3: Comparison of fourteen chips.

The four ASIC solutions are the major competitors [29, 32, 34, 38]. The performance of a chip depends both on process and design. Smaller chip size and lower power consumption are derived from the advanced process. However, it is reasonable to compare the circuit design in the same process. The state-of-the-art QRS detector [34] employed advanced 65 nm technology, which derived the smallest area 0.02 mm2 among all QRS chips [26–38]. Besides, the database performance is very good (Se: 99.7%, : 99.9%). However, the advantage of size came from the 65 nm technology instead of the circuit design, if its previous version [52] was considered. The area [52] is 1 mm2 using 0.13 μm UMC process, which is larger than our 0.68 mm2 using 0.18 μm tsmc process. The next competitor [32], using 0.35 μm process, has larger area and power consumption (5.74 mm2, 9.6 μW) than ours. The most important point is no database verification had been reported in this paper. An excellent QRS detection algorithm (Se: 99.81%, : 99.80%) [44] was modified for this ASIC design [32]. However, it did not guarantee the ASIC performed as well as the algorithm. The authors did not provide enough evidence in their paper. It is a pity that even the brief QRS detection circuit design was not mentioned also. [29] is an ideal competitor candidate, since it used the same 0.18 μm technology with our design. The other benefit is that it employed similar wavelet QRS detection method with [34]. Both of these two wavelet-based ASIC adapted Mallat’s algorithm [53, 54], which gave us an indirect chance to compare the performance of circuit design of [34] with ours. The database performance (Se: 99.63%, : 99.89%) of [29] is better than our design (Se: 95.65%, : 99.36%). However, based on the same 0.18 μm technology, the area 1.1 mm2 is 161% of our area 0.68 mm2 and the power consumption 176 μW is 7964% of our power consumption 2.21 μW. This leaves improvement space for its circuit design beyond advanced process technology for an ambulatory device. Finally, a recently proposed QRS detection ASIC [38] integrated in an ECG SoC is compared. This ASIC has very good database performance (Se: 99.80%, : 99.86%). However, based on the same 0.18 μm technology, the area and power (1.2 mm2, 9 μW) are worse than our design.

There were three earlier SoC solutions [26–28], two of them [26, 28] are based on 0.18 μm technology, the same with ours. However, the area and power (13 mm2, N/A; 6.25 mm2, 155 μW) is larger than ours (0.68 mm2, 2.21 μW). The other 0.5 μm technology SoC solution [27] has 1.5 μW, small power consumption. However, all of them [26–28] lack any medical database certification. Some technique details are briefly described as follows. The first one presents the design which incorporates an ARh4922T hard macrocell as its processor core [26]. The second one categorizes and stores HRV measures in an internal memory. The chip detects all R peaks with millisecond accuracy after the initial 2 seconds of data, and stores up to 2 minutes of continuous ECG data and up to 4 minutes of HRV histogram [27]. The third one stores the difference between every two adjacent R-R intervals in a single-port synchronous, high-performance SRAM, up to 24 hours of continuous ECG data can be stored on chip with a fixed resolution of 1 ms [28].

The technology used by ECG SoC solutions [30, 31, 33, 35–37] evolved from 0.35 μm [37] to 0.18 μm [33], 0.13 μm [30, 36], and 0.09 μm [31, 35] in recent years. The function is powerful, even the EEG signal processing function was included [31, 36]. However, with advanced technology (0.13 μm and 0.09 μm) than ours (0.18 μm), the area distribution (3.97 mm2 to 12 mm2) is still larger than ours (0.68 mm2). Three of them [30, 33, 35] were not seriously tested by any medical database. The other two performed well [31, 36]. A recent QRS SoC design [37] that used quadratic spline wavelet transform has good performance, although the 0.35 μm technology is not very advanced. The sensitivity (Se: 99.31%) and the predictivity (: 99.70%) are high and the power consumption is very low (0.83 μW). Although the chip size (1.11 mm2) is lager than ours (0.68 mm2), it is smaller than most other works. To sum up, SoC is a good try for general physiological measurement, but ASIC is a better solution for ambulatory device if the die size is really cared.

5. Conclusions

HRV is a measure of variations in the heart rate and very useful for understanding many diseases, while QRS detection is the first step of HRV analysis. The low cost ASIC proposed in this paper can be embedded into many daily life systems for both health and clinical purposes. Our proposed ASIC has smaller core area and very low-power consumption, compared with the main competitive target [29] based on the same 0.18 μm technology. One important spec is accuracy, the ability of real time. It was provided by only three papers, our design (±6 ms) and the other two (±7 ms, ±8 ms) [27, 30]. The sensibility (99.69%) and predictivity (99.77%) of the algorithm [48] we used are very high. However, to achieve the accuracy, the simplification of decision circuit derives a side effect, the lower sensibility (95.65%) and predictivity (99.36%). To improve the performance of peak detection, especially in sensitivity, the search back technique [48] will be implemented in the future design.

Acknowledgments

The authors thank Shih-Hsiang Lin, Tzu-Der Chuang, and You-Liang Lai for their support in both ASIC design and document writing.

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