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AMD to support Intel AVX instructions

Doing the math on SSE compatibility

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Chip designer and erstwhile maker Advanced Micro Devices will support a bunch of Advanced Vector Extensions (AVX) instructions, part of the family of extended Single Instruction, Multiple Data (SIMD) instructions for x64 chips that Intel announced last year.

The move, announced today, will make AMD's Opteron, Athlon, and Turion chips a bit more compatible with the Core and Xeon chips from Intel, making the lives of software developers a bit easier because they won't have to tune applications to take advantage of two different sets of vector extensions.

Intel first introduced Streaming SIMD Extensions (SSE) for its processors back in 1999 with the Pentium III processors, and these SSE instructions were a reaction to the multimedia processing instructions that AMD added to its x86 chips called 3DNow.

Intel continued to add SSE instructions over time, and was at the SSE 4.1 level in the "Penryn" Core 2 processors and has added some more instructions with the SSE 4.2 set with the "Nehalem" cores used in the i7 desktop and Xeon 5500 server processors.

Back in August 2007, as it became apparent to AMD that Intel had finally woken up from its capitalistic and technological slumber, AMD opened up a set of Streaming SIMD Extensions (SSE) for its x64 processors that, in a cheeky move, it called SSE5. These comprised 128-bit extension to the 64-bit X64 architecture of the Opterons, including 46 base instructions and 124 additional instructions that were to be implemented in AMD's "Bulldozer" processor cores, slated for 2009 back then but now coming out in 2011. (There are already some 128-bit instructions in the Opterons, such as the 128-bit floating point units that made their debut with the "Barcelona" Opterons.)

While AMD's proposed SSE5 instructions would speed up certain algorithms used in high performance computing, multimedia and security applications, SSE5 is not a superset of Intel's SSE4 instructions, even though there is quite a bit of overlap. And that means programmers and their compilers having to be mindful of the underlying instruction set when they optimize their code for a Xeon or Opteron chip.

Last April, as part of its SSE instruction set, Intel put forward a proposal for a bunch of new instructions, including a set of instructions collectively called Advanced Vector Extensions (AVX), which include XOP (for eXtended Operations), CVT16 (half-precision floating point converts), and FMA4 (four-operand Fused Multiply/Add).

While AMD had similar functions in its SSE5 proposal, Dave Christie, senior chip architect at AMD, said in a blog posting that AMD is trying to strike a balance between innovation and standardization and that is why it has embraced Intel's way of implementing these instructions. (The blog post has some details on the instructions, and if you really want to get into it, read the specification here (pdf). Knock yourself out.) Christie says that a version of the AMD64 SimNow simulator will support these Intel instructions "in very short order".

AMD says that the AVX instructions will make their way into the Bulldozer cores in 2011. If you need a refresh on the updated AMD processor roadmap, see our previous coverage here. ®