With the advent of deep submicron technology, the number of transistors in a chip has increased very rapidly. As the complexity of VLSI circuits increases fast, the automation of the VLSI design has become very crucial not only to reduce design time and cost, but also to improve design quality. There are several criteria to measure design quality: area, delay, testability and power consumption. Among them, the research is particularly focused on power consumption which is becoming more and more important with the advent of portable, high-speed, and high-density devices. There are four problems addressed in this work. First, we develop an algorithm for automatic synthesis of combination interface circuits while minimizing the area and the switching activity in the interface circuit. Secondly, we propose a new model for glitch analysis in logic circuits. This model is capable of modeling the generation, propagation and elimination of glitches in standard logic gates. Thirdly, we propose a new re-synthesis algorithm for power reduction utilizing circuit symmetries. We propose an algorithm for detecting symmetries in a given circuit implementation of a Boolean function. Resynthesis techniques utilizing four types of symmetries are proposed. These techniques enable us to optimize power consumption and delay with no (or very little) area overhead. Lastly, a power optimization technique based on input vector conversion is presented. We first propose an algorithm which determines a set of preferred input vectors which will lead to low switching activities in the circuit. After determining the set of preferred vectors, we re-synthesize the original circuit by adding a conversion logic which converts a set of bad vectors into a set of good ones. The experimental results indicate that our algorithms are very promising.