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Abstract

We consider the problem of representing timing information associated
with functions in a dataflow graph. This information is used for
behavioral synthesis of appropriate architectures for implementing the
graph. Conventional models for timing suffer from shortcomings that
make it difficult to easily represent timing information in a
hierarchical manner, especially for multirate systems.
We identify some of these shortcomings, and provide an alternate
timing model for hardware implementations that does not have these
problems. This model is capable of providing a unified view of
hierarchical combinational and sequential circuits under the
assumptions of high-level scheduling. The resulting compact
representation of the timing information can be used to streamline
system performance analysis.
We show that with some reasonable assumptions on the way hardware
implementations of multirate systems operate, we can derive general
hierarchical descriptions of multirate systems in a similar manner to
single sample-rate systems. Several analytical results that previously
applied only to single sample-rate systems can also easily be extended to
multirate systems under the new assumptions.
We have applied our model to several signal processing applications,
and obtained favorable results. We present an algorithm to compute the
timing parameters, and have used this to compute timing parameters for
a number of benchmarks circuits. We present the results obtained on
several ISCAS benchmark circuits and also several multirate dataflow
graphs corresponding to useful signal processing applications.
(Also cross-referenced as UMIACS-TR-2000-75)