Abstract:

The need for high-performance, low-power and low-cost systems for wireless communications is driving silicon technology towards higher speed, higher integration and more complex functionality. This higher speed and higher integration leads by the end of this decade to the so-called Deep Submicron (DS) technology that will provide chips with billions of transistors. Chips will no longer be stand-alone system components but "silicon boards" encapsulating complex system knowledge, implemented in novel, heterogeneous architectures at the process-memory level. Time-to-market and low Non-Recuring Engineering (NRE) costs are key issues in successful System-on-a-Chip (SOC) designs. The current abstraction level is not sufficient for modern SOC designs. The current abstraction level is not sufficient for modern SOC designs, and thus a higher abstraction level is a necessity in modern SOC designs. The traditional Application Specific Integrated Circuits (ASIC) development flow goes from specification through synthesis and place and route to actual physical chip fabrication. For future SOC designs this is far too slow and causes high NREs. One progressive solution to fast time-to-market and low NREs is to use Programmable Logic Devices (PLDs), that are manufactured as standard products. The use of such devices leads us to the concept of System-on-a-Programmable-Chip (SOPC). In these Platform FPGA type approaches the processor block can be implemented either as a hardcore next to the logic elements or as a softcore on the actual logical elements. This SOPC term is also called System-on-a-Reprogrammable-Chip (SORC) or Programmable System-on-a-Chip (PSOC). As specifications are moving toward higher abstraction levels and the technology is moving into deep submicron, the gap between these elements is ever widening. DS physics causes that power and performance are dominated by wires instead of gates. This means that on-chip networks and the global clocking in the chip must be taken into special consideration. One solution to decrease this physical gap is the use of reusable Intellectual Property (IP) blocks, since they are offering an efficient link between Register Transfer Level (RTL) and deep submicron layout structures. The IP blocks have also a great effect on the time-to-market issue.This thesis presents IP-centric SOPC implementation of a Wideband Code Division Multiple access (WCDMA) baseband modem. This presented implementation is based on the issues of IP blocks, SOPC and a Field Programmable Gate Array (FPGA) device. The correlator and the code generators for the modem were implemented as IP blocks and the NIOS softcore processor was used as controlling device. The main target in this implementation was as much as possible the computation power of the control processor is left for other purposes. Thus the IP blocks can rather be treated as hardware accelerators or co-processors.The modem was implemented on an Altera APEX EP20K200EFC484 device. This implementation took 27% (2245/8320) of the Logical Elements (LE) of the chip. The NIOS processor uses 1360 LEs and the IP blocks use 885 LEs. The controlling software was written in C-language. The control program left about 90% (54/60 MIPS) of the computation power for other purposes. /Kir10