This is Part 1 of a 5-part discussion of the International Workshop on Design Automation for Cyber-Physical Systems co-located with the Design Automation Conference in Austin in June. Attending this all-day event on Sunday, June 5th, required a commitment of 9 hours and a $200 registration fee, albeit it came with a generous box lunch.

Over the course of the day, 10 speakers expounded on everything from complexity to reliability, from resilience to resource management, from smart buildings to smart grids to smart cars, and threw in a large dollop, as well, of how to deal with those miscreants among us who see opportunities in the emerging world of CPS to do small, medium, and large amounts of harm to our fellow humans and institutions.

Now it’s true, the thought leaders who spoke at CPSDA were consistently articulate, intelligent and well-informed. Nonetheless – even after 9 hours of intense listening, and quite a bit of caffeine – I was still not exactly sure what a cyber-physical system is. So let’s be creative and make up our own definition.

It’s fantastic to see that the ESD Alliance is following through with its new-found commitment to promote discussion about the IP industry. On Wednesday, September 14th, the Alliance is hosting an evening panel at their headquarters in Santa Clara to discuss semiconductor IP issues that “Keep You Awake at Night”.

As background, consider that the massive amounts of IP involved in building a modern SoC may translate into IP vendors losing millions of dollars if their IP is used therein without proper licensing. At the same time, semiconductor companies also wrestle with troubling issues if their engineers accidentally reuse a core without proper licensing, possibly exposing their employers to huge liabilities. The ESD Alliance event in September promises to address these thorny problems.

Moderated by industry leader Warren Savage – formerly CEO of IPextreme, but now GM of IP at Silvaco with the acquisition announced just prior to DAC – the evening’s two panelists come from interesting backgrounds.

The semiconductor IP industry is reeling at news of the tragic death of Mark Templeton while white water kayaking last weekend in Oregon. Well known, widely admired, and held in great esteem for both his intelligence and unassuming style, Templeton will be sorely missed, not just in the IP industry, but across the entire tech sector.

Per the Press Release: “Mark R. Templeton, 57, was a highly respected venture capitalist in Silicon Valley who used his background as an engineer to foster scientific advancement. In his capacity as a director and board member of numerous tech companies and organizations, he was instrumental in driving growth in the intellectual property market through a combination of technical and business innovation.”

Who better qualified to post reactions to this week’s astonishing news out of Tokyo and Cambridge – SoftBank is buying ARM in an all-cash deal for 24.3 billion British pounds – than the leaders of two highly regarded IP companies and an articulate Brit with total street cred in EDA.

Long-time EDA investor Lucio Lanza lead a fascinating, albeit mystifying, discussion in the DAC Pavilion on Monday, July 6th, in Austin. His panelists included IPextreme’s Warren Savage, Scientific Ventures’ Mark Templeton, and eFabless’ Michael Wishart, with the topic under discussion being open source.

The session was titled “Daring to Move to Open Source” and was described thusly: “The emerging Internet of Things market is destined to upend that time-tested ‘advanced-node’ model, as developers opt for older, less costly process technologies, using commodity design tools and selecting proven IP blocks to quickly and efficiently assemble chips. As demand for IoT devices grows exponentially, might open source EDA tools and IP become viable, or even the winning combination that enables the low-cost design of an IoT SoC?”

At this writing, midnight is approaching here in California, it’s June 23rd, and highly anticipated news is arriving out of the UK. It’s Friday morning there and the results of the Should I stay or Should I go referendum have been announced. To the astonishment of some subset of the world, and undoubtedly their stock markets, the UK is leaving the European Union.

And so a page turns, another chapter begins, and now there’s a twist in the plot line that few saw coming. Although it’s a dark and starry night here, the sun is up in the UK and the future looks suddenly different, no matter if you’re standing on the streets of London, York, Edinburgh – or Cambridge.

Menta is a French startup, founded in 2007, that provides embedded FPGA IP for SoCs, ASICs and ASSPs. The company exhibited last week at the Design Automation Conference in Austin and will exhibit next week at the TSMC Technology Workshop in Herzliya.

This month is clearly a busy one for Menta, and for more reasons than just exhibiting in conference venues 7000 miles apart. On June 6th, the company announced its “next generation of embedded programmable logic IP cores for SoCs.”

When SRC’s Bill Joyner took the podium this past Sunday evening at the 53rd DAC in Austin, he did something that’s never been done before: Present a panel about careers that wasn’t part of a Workshop for Women in EDA.

Up until 7 o’clock on June 5, 2016, a conversation about career perspectives was such a non-technical topic, it could only be found in Marie Pistilli’s beloved workshop, a venue where work/life balance, Academia vs. Industry, and how to promote your brand within the organization were thoroughly discussed every year for 15 years at DAC.

Now IEEE’s Council on EDA, CEDA, has made the bold decision to pick up where Marie’s workshop left off, sponsoring this week’s event and broadening the audience and the appeal.

Joyner had four people on his panel, a generous two hours to hash out various universal questions, and enough of a sense of humor to offer to wear the necktie he’d brought with him to add gravitas, or not to wear the tie to appear hipster and cool. He quickly decided to go without the tie, and the ensuing conversation went something like this.

The first thing to do on Wednesday at DAC 2016 in Austin is take in an hour of the Exhibit Hall. This is the last day for the booths, people are zippy in the morning like horses sensing the stable at the end of their journey, and conversations on the floor are still about the technology. By the end of the afternoon, it’ll be about wistful goodbyes and, “Will we even be here next year when DAC again returns to the Lone Star State?”

Then from 10:30 to noon genuflect to Academia and check out ‘Accelerated Simulation for Circuit Reliability and Stability’. With speakers from Texas A&M, USC, Brown, and Michigan Tech. If you attend, you’ll learn what the future holds for simulation: power supply stability, soft error in logic circuits, thermal noise in ultra-low voltage designs, and the sparsification of spectral graphs used in various design problems. Nobody from industry is speaking, so if you want to get in on the ground floor commercializing some of this stuff, sit in the front row.