A little more than six months ago we wrote an editorial
about Intel's future technology after Core 2 Duo, titled "Life After Conroe."
Life after Conroe inches closer, but, in the meantime, more details on the
architecture are available today.

DailyTech had the opportunity to chat with Mark Bohr, Intel Senior Fellow, and
Steve Smith, Intel Vice President DEG Group Operations, about the
upcoming CPU design.

The primary focus of Intel's next-generation process technology is
Penryn. Penryn is the specific codename a 45nm mobile shrink of the Conroe core,
but the codename may also be used to describe the entire product family.
Early last year Intel announced it would optically shrink to the next process
node every two years. Staggered one year later, the company would also
announce a new microarchitecture. This philosophy of shrink followed by
architecture revision will undergo its first real milestone with the node
shrink from 65nm to 45nm Penryn. One year after the 45nm Penryn
shrink, Intel is also expected to announce its next-generation
microarchitecture successor, Nehalem.

Intel claims the upcoming Penryn will fit 410 million transistors for the
dual-core model, and 820 million transistors for the quad-core variants -- dual-core Conroe utilizes just 298 million transistors.
Intel's 45nm SRAM shuttle chip, announced last year, had a little over 1 billion
transistors and fit on a 119mm^2 package. However, the initial Penryn
quad-core processors will use a multi-die packaging, so it's realistic to expect only 410 million transistors per die at launch.

The optical shrink allows the engineers to boost clock speed, but the
additional real estate means the company can put more logic on the processor as
well. "Most of that transistor savings is spent on increasing the cache
over Core 2" added Smith.

Penryn is still not without its mysteries; a primary concern for enthusiasts is
motherboard and socket support. Penryn will launch on Socket 775 -- meaning
existing motherboards can physically harbor the new CPU, but electrically might
not. "Motherboard developers will have to make some minor changes to
support [Penryn]. We can't guarantee that a person could just plug the
chip into every motherboard on the market today." However, Smith
also claimed the Penryn
boot test that grabbed so many headlines last week occurred on unmodified
hardware that included a notebook, several desktop motherboards and several
server motherboards.

The lithography process for Penryn, dubbed P1266, is not just a shrink from
65nm to 45nm. Perhaps the most significant advance on P1266 is the use of
high-k dielectrics and metal gate transistors. In a nutshell, the
polysilicon gate used on transistors today is replaced with a metal layer and
the silicon dioxide dielectric that sits between the substrate and the
transistor is replaced by a high-k dielectric.

Intel's push for high-k dielectrics and metal gate transistors may be more
significant than the node shrink. Intel's guidance documentation claims
with the new high-k dielectric, metal gate transistors offer a 20% increase in
current, which can translate to a 20% increase in performance. When the
new transistor technologies run at the same current and frequencies as Core 2
Duo processors today, translates to a 5-fold reduction in source-drain leakage
and a 10-fold reduction in dielectric leakage.

"The implementation of high-k and metal gate materials marks the biggest
change in transistor technology since the introduction of polysilicongate MOS
transistors in the late 1960s" claims Gordon Moore, Intel co-founder
attributed with coining "Moore's Law."

Intel would not reveal the materials used in its metal gate technology, though
Smith announced that the dielectric is hafnium based. Hafnium dioxide has
been the leading candidate to replace silicon oxide inside academia for
years. A different material is used for PMOS and NMOS gates.

Intel's lithography roadmap no longer ends at P1268, the 32nm node.
Earlier today Intel revealed its 22nm node, dubbed 1270, slated for first
production in 2011.

Smith closed our conversation with "In 2008, we'll have Nehalem."

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AMD had high K long before Intel and that is why AMD CPUs crushed the P4/Xeon for the past two years. Intel knows how to manipulate the media and it works well for them. Those not in the information loop would think AMD is just sitting around doing nothing.

You can count on AMD and IBM to continue their technology leadership over Intel as they roll out new products. It took Intel 2 years just to catch up to AMD's 90 nano products and Intel had to move to 65 nano to achieve this. AMD has already made it known their Barcelona will run up to 40% faster than Clovertown on certain apps so that should be a wake-up call.

Don't believe everything you read in the tabloids, kid. I'd take that 40% with a grain of salt.

Secondly, the high-k stuff is in AMD's 65 nano products, not 90.

Also Intel's lact-luster performance for the past two years has nothing to do with process technology, it's architectures. K8 is why AMD crushed Intel P4/Xeon performance in the past.

Don't look at Intel's process advancement (they are several months ahead of AMD on shrinks, I mean 6 months+ -- it's always been atleast that big of a gap) as a cheap hack to get past AMD -- look at Intel's 65 nano P4's and Pent D's, they still suck just as bad as the 90 nano versions -- it's their superiority in being several months ahead on their process shrinks.

Hi K is absolutly NOT in AMD's 65nm. AMD is using the same old boring nitrided oxide they used in previous generations.

AMD/IBM have already stated they are NOT using HiK in their 65nm. All they could do was lower the K a bit for the backend and throw immersion in because they couldn't figure out how to pattern with 193nm dry.

Remember also that there is a difference between the 2 HK/MG processes here...
Unlike Intel, IBM has figured out how to embed its new metal gates directly into silicon (Intel's gates must still sit atop a silicon architecture structure).
This will be even more important as they shrink to 32nm and 22nm...

Intel's manufacturing lead should allow it to bring chips to market before its rivals, but IBM could get a greater return from this technology in the long term because it uses the high-k metal gates in a different way, one analyst said. "It's a wonderfully parallel development of a technology that should lead to faster, more efficient chips in everything from PCs to cell phones and iPods," said Richard Doherty, senior analyst with The Envisioneering Group.

"Intel has the advantage that they're already in production, but IBM's advance may be even more significant and lead to faster, smaller chips. The IBM breakthrough is to integrate the metal gate so it's embedded in the silicon. Intel put the metal gates on top of a proven silicon architecture."

quote: AMD plans to produce its first 45nm chips in mid-2008, in the wake of the launch of its first 65nm product, the quadcore "Barcelona", due out in mid-2007.

Reading some articles is indeed rather humorous. Anyway, quotes from analysts don't tend to mean much to me. Far more interesting is to look at the IBM research paper on the matter that the register posted up: http://regmedia.co.uk/2007/01/28/ibmhighk.pdf

Their 'embedded in the silicon' is actually a conventional poly-Si deposited over the metal gate, something that really -should- be quite unnecessary. Anyway, what I love about the paper is the info on their HK/MG pFET devices, the fact that their test SRAM array was using conventional SiON/Poly-Si pFETs says something about how 'ready' their high-k process is.

quote: the fact that their test SRAM array was using conventional SiON/Poly-Si pFETs says something about how 'ready' their high-k process is

I believe that East Fishkill has already been converted to HK/MG...the key is that the IBM conversion appear to be a much simpler process...

"We don't build Vespa scooters, we build Ferraris. We've been talking about high-k for five years now, and if we wanted to, we could ship it out the door tomorrow. But there's no reason to do that because it doesn't solve any problem for us. We're not addressing a crisis issue that hit us in the head when we didn't see it coming," Meyerson said.

"Ours is a more fundamental implementation; it's a drop-in, or a one-for-one replacement, for SiO2 ," he said, referring to existing silicon dioxide technology. "I've said for years that gate oxide scaling is ending. The gates are literally five atoms thick. What are you going to do, build one that's two-and-a-half atoms thick?"

The interesting questions for me are
1. What is Intel's goal/need for HK/MG? (meaning from a marketing or performance standpoint)
2. How will ultra-low k connects compare to Intel's process and what will that mean for marketing/performance?

Yay, yes, the quote from the engineer was the highlight of that little article =D Granted, he has the typical bias towards his company, but, don't we all? Anyway, my little comment on the bolded portion is that it can't be a one for one replacement of SiO2 with HfO2, since there are problems with using Poly-Silicon directly on the halfnium oxide (it'll work, but not near so well as with metal gate.) But, eh, they don't get into enough detail to say how it's 'drop in'.

1. I would assume it's more a marketing point - performance per watt. True, the average consumer doesn't care as much about it. But system integrators love it for easing the cost of cooling designs. And it has fast become -the- metric in many server applications. So what if server X outperforms server Y by a small amount if two X's consume the same amount of energy as one Y?

2. That is indeed an interesting query. Heh, at the current dimensions interconnects are getting to be far more of a factor, no question. Still, on Intel's 45nm info page, they have the interesting little statement of, "Approximately 30 percent reduction in transistor-switching power." This is indeed a tad bit vague, if in comparison to 65nm, the majority could be due to voltage decrease. But, the remaining amount would be due to reduced capacitances, and I would guess that amount is at least as much as what the ultra low-k interconnect dielectrics would offer.

Short channel HK/MG devices were fabricated from <20Å HfO2 with
thermally stable BE metal gates in a gate-first approach where
conventional poly-Si is deposited over the metal gates. Following a
lithographic patterning and gate stack etch process, a conventional selfaligned
implant process flow with a final S/D spike RTA (T>1080°C) +
advanced annealing (AA) and dual stress liner (DSL) with conventional
MOL and BEOL was used

I'll freely admit that I shied away from the 8000 level semiconductor properties course after having gotten through the 5000 level one, so I don't understand quite everything either, lol.

What I find mildly confusing about all the stuff IBM has said is that they're being rather mute on a change to metal gate electrodes. Technically, they'd have a high-k metal gate by simply using hafnium as the gate dielectric and continuing to use poly-Si for the gate electrode. (After all, hafnium is a transition metal.) I'd hope it's simply the press releases dumbing it down that make it seem as such. But the fact that the paper lacks any mention of a metal gate electrode and -does- say that poly-Si is deposited over the metal gates is a tad bit worrysome. Maybe they'll have further information in time, just seems odd that they're not mentioning anything about the gate electrodes really.

Some more details are reported in another paper at the 2004 VLSI symposium on VLSI Technology "Thermally robust dual-work function ALD-MNx MOSFETs using conventional CMOS process flow".

The metal gate (TaN for N, WN for P) is thin (~10 nm) and deposited by ALD. The polysilicon is needed to be on top to enhance the thermal stability. I also know it shields the gate dielectric better from lithography radiation; the metal is too thin.