NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A NAND type flash memory having a program verifying function is provided, which can search for stored data at high speed. The flash memory reads search data that corresponds to stored data stored in a block in a front page of the block in a reverse-order search mode, compares the search data with the non-search data from a controller, and returns a block address and a page address of the search data that matches with the non-search data to the controller. At this time, the flash memory checks the match between the search data and the non-search data by comparing “0” data using the program verifying function provided in the flash memory itself.

2010-12-16

20100318730

Dual Channel Memory Architecture Having Reduced Interface Pin Requirements Using a Double Data Rate Scheme for the Address/Control Signals - Apparatuses and methods for dual channel memory architecture with reduced interface pin requirements are presented. One memory architecture includes a memory controller, a first memory device coupled to the memory controller by a shared address bus and a first clock signal, and a second memory device coupled to the memory controller by the shared address bus and a second clock signal, where the polarity of the second clock signal is opposite of the first clock signal. A method for performing data transactions is presented. The method includes providing addressing signals over a shared address bus to a first memory device and a second memory device, providing clock signals to the memory devices which are reversed in polarity, where the clock signals are derived from a common clock signal, and transferring data to the memory devices over separate narrow data buses in an alternating manner based upon the clock signals.

2010-12-16

20100318731

OVERRIDE BOOT SEQUENCE BY PRESENCE OF FILE ON USB MEMORY STICK - Consistent with embodiments of the present invention, systems and methods are disclosed for operating an override boot sequence. In some embodiments, a system may comprise a computing device. The computing device may contain client software configured to boot the computing device to a normal state. The computing device may further contain a first memory, wherein the client software may be stored on the first memory. The system may further comprise an interface capable of communicating with a portable memory. The portable memory may contain an override application. The system may further comprise a bootloader program associated with the computing device, wherein the bootloader device may be configured to detect the presence of a connection of the portable memory and the interface. The bootloader program may further be configured to copy the override application to a second memory associated with the computing device and execute the override application instead of the client software.

2010-12-16

20100318732

DATA PROCESSOR - The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external memory. The data processor includes a memory control unit being capable of controlling in response to a clock an external memory having plural banks that are individually independently controllable, plural buses connected to the memory control unit, and circuit modules capable of commanding memory accesses, which are provided in correspondence with each of the buses. The memory control unit contains bank caches each corresponding to the banks of the external memory. Thereby, the data processor enhances the bus throughput or data throughput of the external memory, since the data processor stores the data read out from the external memory temporarily in the bank caches and to use the stored data without invalidating them, when performing a continuous data read with a smaller data size than the data bus width of the external memory.

2010-12-16

20100318733

Memory system performing refresh operation - The memory system includes a memory cell array including a plurality of memory sectors and a controller configured to write data in the memory cell array in response to a writing signal. The controller is configured to refresh at least one of the plurality memory sectors when the writing signal is provided.

2010-12-16

20100318734

APPLICATION-TRANSPARENT HYBRIDIZED CACHING FOR HIGH-PERFORMANCE STORAGE - Systems, apparatus, and computer-implemented methods are provided for the hybridization of cache memory utilizing both magnetic and solid-state memory media. A solid-state cache controller apparatus can be coupled to a host computing system to maximize efficiency of the system in a manner that is transparent to the high-level applications using the system. The apparatus includes an associative memory component and a solid-state cache control component. Solid-state memory is configured to store data blocks of host read operations. If a host-read operation is requested, the controller communicates with a solid-state cache memory controller to determine whether a tag array data structure indicates a cached copy of the requested data block is available in solid-state memory.

2010-12-16

20100318735

STORAGE SYSTEM - The storage system includes a disk controller for receiving write commands from a computer, and a plurality of disk devices in which data is written in accordance with the control of the disk controller. The size of the first block which constitutes the data unit handled in the execution of the input/output processing of the data in accordance with the write command by the disk controller is different from the size of the second block which constitutes the data unit handled in the execution of the input/output processing of data by the plurality of disk devices. The disk controller issues an instruction for the writing of data to the disk devices using a third block unit of a size corresponding to a common multiple of the size of the first block and the size of the second block.

2010-12-16

20100318736

METHOD AND SYSTEM OF AN ADAPTIVE INPUT/OUTPUT SCHEDULER FOR STORAGE ARRAYS - An adaptive input/output (I/O) scheduler for storage arrays is disclosed. In one embodiment, a method of a redundant array of independent disks (RAID) controller for deploying an optimal I/O scheduler type per a storage array configuration includes generating performance data by assessing respective performances of a plurality of I/O scheduler types on different RAID level test volumes with at least one I/O pattern generated internally within a storage subsystem which comprises the RAID controller. The method also includes storing the associativeness of the performance data with respect to a particular I/O scheduler most suited for a given I/O workload to a nonvolatile memory of the RAID controller. The method further includes deploying an optimal one of the plurality of I/O scheduler types and at least one performance parameter for at least one subsequent I/O operation associated with the storage subsystem based on the performance data.

2010-12-16

20100318737

PROVIDING DATA REDUNDANCY USING AN INTERNAL MASS STORAGE DEVICE AND AN EXTERNAL MASS STORAGE DEVICE - A computer includes an enclosure, an internal mass storage device within the enclosure, and a redundancy controller within the enclosure. At least one port enables direct connection of the computer to at least one external mass storage device. The redundancy controller is configured to provide data redundancy using the internal mass storage device and the at least one external storage device if the at least one external mass storage device is connected to the at least one port.

2010-12-16

20100318738

HARD DISK SYSTEM AND METHOD FOR ACCESSING THE SAME - A hard disk system and a method for accessing the hard disk system are provided. The hard disk system includes a first hard disk and a second hard disk. The first hard disk is used to store system data that is read-only. The second hard disk includes a mapped data storage section and a variable data storage section, wherein the mapped data storage section is used to store a mapped data generated by mapping the system data of the first hard disk. A maximum number of writes for the first hard disk is less than a maximum number of writes for the second hard disk, wherein the hard disk system performs data modification via the variable data section of the second hard disk.

2010-12-16

20100318739

MANAGEMENT METHOD FOR A VIRTUAL VOLUME ACROSS A PLURALITY OF STORAGES - To enhance capacity expansion property of a storage system for providing a thin provisioning volume, this invention provides a computer system including: a first storage system; and a second storage system for providing a second volume to the first storage system. The first storage system is configured to: define at least one first volumes; define a first storage pool including the defined first volume and the provided second volume; provide to the host computer a first thin provisioning volume that is recognized as a volume having a capacity equal to or larger than that of storage areas assigned from the first storage pool. The first thin provisioning volume is thus assigned with both storage areas of the first volume and storage areas of the second volume, which are included in the first storage pool.

2010-12-16

20100318740

Method and System for Storing Real Time Values - A <> is inserted between the archiving subsystem (e.g. relational database writing API) and the tag data flow from the acquisition server. Then client data requests must be routed always through the <>. The dynamic data cache module>> is able to manage tag data that is not only coming from real-time acquisition (i.e. keeping the last n values of tag data in the cache) but also <> of data in a different time span. For this usage, the cache will be size-limited and a last recently used (LRU) algorithm may be used to free up space when needed.

Partitioned Replacement For Cache Memory - In a particular embodiment, a circuit device includes a translation look-aside buffer (TLB) configured to receive a virtual address and to translate the virtual address to a physical address of a cache having at least two partitions. The circuit device also includes a control logic circuit adapted to identify a partition replacement policy associated with the identified one of the at least two partitions based on a partition indicator. The control logic circuit controls replacement of data within the cache according to the identified partition replacement policy in response to a cache miss event.

2010-12-16

20100318743

DYNAMIC SCREENTIP LANGUAGE TRANSLATION - When a user interface cursor hovers over a user interface item, a determination is made as to whether the user interface item has an associated screentip. If the user interface item has an associated screentip, text associated with the screentip is identified, a translated text string is located for the text string, and the translated text string is displayed in the screentip. If the user interface item does not have an associated screentip, a determination is made as to whether the user interface item contains a text string. If so, a determination is made as to whether a translated text string is available that corresponds to the text in the user interface item. If so, the translated text string is displayed in a screentip for the user interface item.

2010-12-16

20100318744

DIFFERENTIAL CACHING MECHANISM BASED ON MEDIA I/O SPEED - A method for allocating space in a cache based on media I/O speed is disclosed herein. In certain embodiments, such a method may include storing, in a read cache, cache entries associated with faster-responding storage devices and cache entries associated with slower-responding storage devices. The method may further include implementing an eviction policy in the read cache. This eviction policy may include demoting, from the read cache, the cache entries of faster-responding storage devices faster than the cache entries of slower-responding storage devices, all other variables being equal. In certain embodiments, the eviction policy may further include demoting, from the read cache, cache entries having a lower read-hit ratio faster than cache entries having a higher read-hit ratio, all other variables being equal. A corresponding computer program product and apparatus are also disclosed and claimed herein.

2010-12-16

20100318745

Dynamic Content Caching and Retrieval - This disclosure provides techniques for dynamic content caching and retrieval. For example, a computing device includes cache memory dedicated to temporarily caching data of one or more applications of the computing device. The computing device also includes storage memory to store data in response to requests by the applications. The storage memory may also temporarily cache data. Further, the computing device includes system software to represent to the applications of the computing device that the portions of the storage memory utilized to cache content are available to store data of the applications. In addition, the computing device includes application programming interfaces to provide content to a requesting application from a cache of the computing device and/or from a remote content source.

2010-12-16

20100318746

MEMORY CHANGE TRACK LOGGING - A method for tracking memory changes includes defining a change-track area of memory including at least one memory address range for which changes will be tracked. The method also includes allocating a protected log region of memory for storing a change-track log and selecting an operational mode for change tracking from among a plurality of modes, the selected operational mode having criteria for tracking memory changes. The method includes detecting memory transactions using a memory logging module and generating a transaction record for each memory transaction that occurs in the change-track are of memory and which meets the criteria. The transaction records can be stored in the change-track log.

2010-12-16

20100318747

ATOMIC MEMORY OPERATION CACHE PROTOCOL WITH OPPORTUNISTIC COMBINING - An atomic memory operation cache comprises a cache memory operable to cache atomic memory operation data, a write timer, and a cache controller. The cache controller is operable to update main memory with one or more dirty atomic memory operation cache entries stored in the cache memory upon expiration of the write timer, and is further operable to update main memory with one or more dirty atomic memory operation cache entries stored in the cache memory upon eviction of the one or more dirty atomic memory operation cache entries from the cache memory.

2010-12-16

20100318748

DATA RECORDER - A data recorder includes a first memory element including read/write capability, a second memory element including non-volatile memory and a controller for realizing memory management functions. The controller responds to a predetermined triggering event by writing selected data from the first memory element to the second memory element. The selected data include data units that have been modified after a prior triggering event.

2010-12-16

20100318749

SCALABLE MULTI-BANK MEMORY ARCHITECTURE - According to one general aspect, a method may include, in one embodiment, grouping a plurality of at least single-ported memory banks together to substantially act as a single at least dual-ported aggregated memory element. In various embodiments, the method may also include controlling read access to the memory banks such that a read operation may occur from any memory bank in which data is stored. In some embodiments, the method may include controlling write access to the memory banks such that a write operation may occur to any memory bank which is not being accessed by a read operation.

2010-12-16

20100318750

METHOD AND SYSTEM FOR SCHEDULING MEMORY REQUESTS - A system for selecting memory requests. The system includes arbiters and a time ordered list scheduler. Each arbiter selects a memory request for transmission from at least one client. The scheduler is operable to receive and store memory requests from the arbiters and selects a selected memory request for forwarding to a memory system. The scheduler includes a list structure operable to store memory requests received from the arbiters in a fashion to preserve relative time of arrival of the memory requests. The scheduler includes scanners that are prioritized with respect to one another. Scanners are operable to simultaneously scan contents of the list structure from the oldest to newest requests and determine whether a memory request match is found based on associated programmable rules to locate a memory request candidate. A memory request candidate of a highest priority scanner is selected by the scheduler as the selected memory request.

2010-12-16

20100318751

Multiple error management in a multiprocessor computer system - An error message handling buffer comprises a first buffer and a second buffer. A first index is associated with the first buffer and a second index is associated with the second buffer. A buffer controller is operable to write and read messages in the buffer, such that messages are written to the buffer of the first and second buffers that has a buffer index value lesser than the buffer size, and read from the other of the first and second buffers, the other buffer having an index value greater than or equal to the buffer size.

2010-12-16

20100318752

Event Triggered Memory Mapped Access - In one or more embodiments, a data processing system can include at least one core capable of executing instructions of an instruction set architecture and a triggered memory map access (tMMA) system coupled to the at least one core. The tMMA system can receive one or more events and, in response, perform one or more actions. For example, the actions can include transactions which can include a write to a an address of the memory map, a read from an address of the memory map, a read followed by write to two respective addresses of the memory map, and/or a fetch transaction. A result of a transaction (e.g., data read, data written, error, etc.) can be used in generating a trace message. For example, the tMMA system can generate a trace message that includes the result of the transaction and send the trace message to a trace message bus.

2010-12-16

20100318753

MEMORY ARCHITECTURE OF DISPLAY DEVICE AND READING METHOD THEREOF - A memory architecture of a display device including a display data memory block and a processor is provided. The display data memory block includes N sub-memories and N arbiters respectfully coupled to the N sub-memories, wherein N is a positive integer larger than 1. The processor is used for respectfully and continuously outputting corresponding N control signals and N address signals to the N arbiters. After receiving the corresponding control signals, the N arbiters respectfully output the corresponding address signals to corresponding sub-memories, such that the N sub-memories simultaneously access data respectfully according to the N address signals.

2010-12-16

20100318754

APPARATUS AND METHODS USING INVALIDITY INDICATORS FOR BUFFERED MEMORY - A storage system includes a storage medium configured to store data and a buffer memory configured to buffer data to be written to the storage medium. The storage system further includes a controller configured to selectively transfer the buffered data to the storage medium responsive to an invalidity indicator received from an external source. For example, the invalidity indicator may comprise unwrite information received from an external source, e.g., information that indicates that selected buffered data corresponds to deleted file data.

2010-12-16

20100318755

REDUCED CONTENTION STORAGE FOR CHANNEL CODING - A decoder for decoding a concatenated code includes a storage input interleaver for storage-interleaving of received data using a storage interleaving operation. A data memory is coupled to an output of the storage input interleaver for temporary storage of storage-interleaved data. A first storage output interleaver is coupled to an output of the data memory for interleaving of data read from the data memory, and a plurality of processors are coupled to an output of the first storage output interleaver to access the data memory. Further, an encoder for generating a concatenated code sequence includes a code interleaver coupled to an input of the encoder for applying a code generation interleaving operation, a first convolutional encoder having an input coupled to an output of the code interleaver, and a storage interleaver coupled to an input of the encoder for applying a storage interleaving operation.

2010-12-16

20100318756

SYSTEM AND METHOD FOR CONTROLLING TIMING OF COPY START - A volume group is a group of two or more copy-source volumes and two or more copy-destination volumes. A computer system stores access rate information, which is information denoting an access rate for a copy-source volume at respective time periods. The computer system estimates the access rate for a future target period for each copy-source volume based on information denoting the access rate of each copy-source volume for one or more past target periods in a predetermined period from among the access rate information. The computer system determines the start timing of a copy for each copy-source volume based on the result of this estimation. A start time and an end time of the past target period are the same as the start time and the end time of a future target period.

2010-12-16

20100318757

APPARATUS AND METHOD FOR DATA BACKUP - A backup control apparatus for periodic data backup, in a virtualized storage system having a point-in-time copy function operable to copy first data into a cascade, comprises a storage targeting component for selecting a target virtual disk for one of a full copy or an incremental copy of the first data; a periodic backup component for triggering a periodic point-in-time copy of the first data to a virtual disk in the cascade; a testing component for testing a status of the full copy, the incremental copy and the periodic point-in-time copy; and a cascade splitting component responsive to the status for splitting the cascade to remove a dependency relationship of at least one of the full copy, the incremental copy and the periodic point-in-time copy on the first data.

2010-12-16

20100318758

EFFICIENT TRANSFER OF MATRICES FOR MATRIX BASED OPERATIONS - Techniques for transferring a matrix for performing one or more operations are provided. The techniques include applying a permutation on at least one of one or more columns and one or more rows of a matrix to group each of at least one of one or more columns and one or more rows of the matrix with a same alignment, blocking at least one of the grouped columns and grouped rows, and performing one or more operations on each matrix block.

2010-12-16

20100318759

DISTRIBUTED RDC CHUNK STORE - The claimed subject matter provides a system and/or a method that facilitates differential transfer and storage of data for network-based backup architectures. A differential compression component can segment a portion of backup information into one or more blocks. In addition, signatures can be generated for each of the one or more blocks. The differential compression component can identify unique blocks from the one or more blocks based upon the generated signatures and signatures of chunks stored in a distributed chunk store. Moreover, a storage component can transfer the unique blocks of the portion of backup information to the distributed chunk store once identified.

2010-12-16

20100318760

MEMORY CONTROLLER, NONVOLATILE STORAGE DEVICE, AND NONVOLATILE STORAGE SYSTEM - A method for use in a nonvolatile storage device that can resize one or more partitions prevents an address management table from becoming complicated after repeated resizing of partitions. When a partition is resized, a logical-to-physical conversion table is updated by shifting a physical block address corresponding to a partition subsequent to the resized partition by the resized amount of the partition. The method enables both logical addresses corresponding to partitions and logical addresses not corresponding to partitions to be constantly continuous to one another.

2010-12-16

20100318761

PROCESSOR AND METHOD FOR DYNAMIC AND SELECTIVE ALTERATION OF ADDRESS TRANSLATION - Non-intrusive techniques have been developed to dynamically and selectively alter address translations performed by, or for, a processor. For example, in some embodiments, a memory management unit is configured to map from effective addresses in respective effective (or virtual) address spaces to physical addresses in the memory, wherein the mappings performed by the memory management unit are based on address translation entries of an address translation table. For a subset of less than all processes, entry selection logic selects from amongst plural alternative mappings coded in respective ones of the address translation entries. For at least some effective addresses mapped for a particular process of the subset, selection of a particular address translation entry is based on an externally sourced value. In some embodiments, only a subset of effective addresses mapped for the particular process are subject to dynamic runtime alteration of the address translation entry selection.

2010-12-16

20100318762

Synchronizing A Translation Lookaside Buffer with Page Tables - The translation lookaside buffer (TLB) of a processor is kept in synchronization with a guest page table by use of an indicator referred to as a “T” bit. The T bit of the NPT/EPT entries mapping the guest page table are set when a page walk is performed on the NPT/EPT. When modifications are made to pages mapped by NPT/EPT entries with their T bit set, changes to the TLB are made so that the TLB remains in synchronization with the guest page table. Accordingly, record/replay of virtual machines of virtualized computer systems may be performed reliably with no non-determinism introduced by stale TLBs that fall out of synchronization with the guest page table.

2010-12-16

20100318763

SYSTEMS AND METHODS FOR UTILIZING AN EXTENDED TRANSLATION LOOK-ASIDE BUFFER HAVING A HYBRID MEMORY STRUCTURE - Extended translation look-aside buffers (eTLB) for converting virtual addresses into physical addresses are presented, the eTLB including, a physical memory address storage having a number of physical addresses, a virtual memory address storage configured to store a number of virtual memory addresses corresponding with the physical addresses, the virtual memory address storage including, a set associative memory structure (SAM), and a content addressable memory (CAM) structure; and comparison circuitry for determining whether a requested address is present in the virtual memory address storage, wherein the eTLB is configured to receive an index register for identifying the SAM structure and the CAM structure, and wherein the eTLB is configured to receive an entry register for providing a virtual page number corresponding with the plurality of virtual memory addresses.

2010-12-16

20100318764

SYSTEM AND METHOD FOR MANAGING PROCESSOR-IN-MEMORY (PIM) OPERATIONS - A system and method of compiling program code, wherein the program code includes an operation on an array of data elements stored in memory of a computer system. The program code is scanned for operations that are vectorizable. The vectorizable operations are examined to determine whether they should be executed at least in part in a vector atomic memory operation (AMO) functional unit attached to memory. If so, the compiled code includes vector AMO instructions.

2010-12-16

20100318765

ACTIVE MEMORY COMMAND ENGINE AND METHOD - A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the command engine, and the ACU command include instruction memory addresses corresponding to an address in an array control unit where processing array instructions are stored.

2010-12-16

20100318766

PROCESSOR AND INFORMATION PROCESSING SYSTEM - A processor includes a processing unit capable of executing single-instruction multiple-data operations; a register file configured to store data that is to be supplied to the processing unit and to be subjected to operations, and a buffer provided separately from the register file, the buffer being a buffer where an integer “n” number of data columns each having a plurality of data elements are written on a column-by-column basis, and data elements at the same location are selected and read as “n” data elements from the respective “n” data columns, wherein the “n” data elements read from the buffer is supplied to the processing unit as data to be subjected to a single-instruction multiple-data operation.

2010-12-16

20100318767

MULTIPLEXING AUXILIARY PROCESSING ELEMENT AND SEMICONDUCTOR INTEGRATED CIRCUIT - A multiplexing auxiliary processing element (PE) performs a process that includes the operations of receiving signals of a plurality of upstream processing elements (PEs) including a plurality of pairs of PEs arranged on the input side; supplying the signals from the upstream PEs to a multiplex PE that is multiplexed and used so that the signals are subjected to a predetermined process by the multiplex PE; receiving the processed signals subjected to the predetermined process by the multiplex PE and sequentially supplying the signals to a plurality of downstream PEs arranged on the output side; and performing operations of the upstream PEs synchronously with the supply of the processed signals to the corresponding downstream PEs on the basis of setting of the multiplexing auxiliary PE.

2010-12-16

20100318768

CHANNEL-BASED RUNTIME ENGINE FOR STREAM PROCESSING - An apparatus, including a memory device for storing a program, and a processor in communication with the memory device, the processor operative with the program to facilitate design of a stream processing flow that satisfies an objective, wherein the stream processing flow includes at least three processing groups, wherein a first processing group includes a data source and an operator, a second processing group includes a data source and an operator and a third processing group includes a join operator at its input and another operator, wherein data inside each group is organized by channels and each channel is a sequence of data, wherein an operator producing a data channel does not generate new data for the channel until old data of the channel is received by all other operators in the same group, and wherein data that flows from the first and second groups to the third group is done asynchronously and is stored in a queue if not ready for processing by an operator of the third group, and deploy the stream processing flow in a concurrent computing system to produce an output.

2010-12-16

20100318769

USING VECTOR ATOMIC MEMORY OPERATION TO HANDLE DATA OF DIFFERENT LENGTHS - A system and method of compiling program code, wherein the program code includes an operation on an array of data elements stored in memory of a computer system. The program code is scanned for an equation which operates on data of lengths other than the limited number of vector supported data lengths. The equation is then replaced with vectorized machine executable code, wherein the machine executable code comprises a nested loop and wherein the nested loop comprises an exterior loop and a virtual interior loop. The exterior loop decomposes the equation into a plurality of loops of length N, wherein N is an integer greater than one. The virtual interior loop executes vector operations corresponding to the N length loop to form a result vector of length N, wherein the virtual interior loop includes one or more vector atomic memory operation (AMO) instructions, used to resolve false conflicts.

2010-12-16

20100318770

ELECTRONIC DEVICE, COMPUTER-IMPLEMENTED SYSTEM, AND APPLICATION DISPLAY CONTROL METHOD THEREFOR - An electronic device, a computer-implemented system, and an application display control method thereof are disclosed. The electronic device has a process unit that executes an operating system kernel, and then executes a first and a second software platform via the operating system kernel. When a first application is executed on the first software platform, a first window manager of the first software platform controls a screen area within which the first application being executed is displayed. The second software platform is notified by the first application to execute a second application, and a second window manager of the second software platform displays in the screen area a screen image that is generated when the second application is executed. Therefore, a user is given the flexibility of executing applications for different software platforms on the same one electronic device.

2010-12-16

20100318771

COMBINED BYTE-PERMUTE AND BIT SHIFT UNIT - A processor includes a decode unit and a byte permute unit. The byte permute unit receives an instruction from the decode unit. The byte permute unit determines whether the instruction corresponds to a shuffle instruction or a shift instruction. For a shuffle instruction, the byte permute unit uses a byte shuffler to perform a shuffle operation indicated by the instruction. For a shift instruction that indicates a shift magnitude, the byte permute unit uses the byte shuffler to byte-level shift a source operand corresponding to the instruction by an integer number of bytes. The byte permute unit also generates a sequence of output bits by bit-shifting the byte-level shifted source operand by a number of bits such that the sum of the number of bits and the integer number of bytes is equal to the shift magnitude.

2010-12-16

20100318772

SUPERSCALAR REGISTER-RENAMING FOR A STACK-ADDRESSED ARCHITECTURE - A system and method for increasing processor throughput by decreasing a loop critical path. In one embodiment, a table comprises multiple stack entries, each comprising an x87 floating-point (FP) stack specifier. The combinatorial logic for operand translation of N FP instructions per clock cycle may require N instantiated copies of a combinatorial logic block. Each instantiated copy may determine a new ordering of the stack entries. Control logic may receive necessary information from the corresponding N FP instructions and determine a corresponding combined computational effect, or stack reordering, on entries within the table based on two or more instructions. Resulting control signals are conveyed to the N instantiated copies. A resulting accumulative delay from an input of the first copy to the output of the Nth copy may be less than or equal to (N−1)*time_delay versus a longer N*time_delay.

2010-12-16

20100318773

INCLUSIVE "OR" BIT MATRIX COMPARE RESOLUTION OF VECTOR UPDATE CONFLICT MASKS - A computer system is operable to identify index elements in a vector index array that cannot be processed in parallel by calculating a complement modified bit matrix compare function between a first matrix filled with elements from the vector index array and a second matrix filled with the same elements from the vector index array.

2010-12-16

20100318774

PROCESSOR INSTRUCTION GRADUATION TIMEOUT - A multiprocessor computer system comprises a plurality of processors distributed across a plurality of node coupled by a processor interconnect network. One or more of the processors is operable to manage hung processor instructions by setting a graduation timeout counter after a first program instruction graduates, resetting the graduation timeout counter if a subsequent program instruction graduates before the graduation timeout counter expires, and resetting the processor if the graduation timeout counter expires before the subsequent program instruction graduates.

2010-12-16

20100318775

Methods and Apparatus for Adapting Pipeline Stage Latency Based on Instruction Type - Processor pipeline controlling techniques are described which take advantage of the variation in critical path lengths of different instructions to achieve increased performance. By examining a processor's instruction set and execution unit implementation's critical timing paths, instructions are classified into speed classes. Based on these speed classes, one pipeline is presented where hold signals are used to dynamically control the pipeline based on the instruction class in execution. An alternative pipeline supporting multiple classes of instructions is presented where the pipeline clocking is dynamically changed as a result of decoded instruction class signals. A single pass synthesis methodology for multi-class execution stage logic is also described. For dynamic class variable pipeline processors, the mix of instructions can have a great effect on processor performance and power utilization since both can vary by the program mix of instruction classes. Application code can be given new degrees of optimization freedom where instruction class and the mix of instructions can be chosen based on performance and power requirements.

HIERARCHICAL SERVICES STARTUP SEQUENCING - Exemplary methods, system, and computer program product embodiments for managing services within a data storage subsystem using a processor in communication with a memory device during a startup sequence are provided. At least one service facilitated by a provider is provided. At least one requirement is linked to the at least one service. The at least one service and the at least one requirement are incorporated into a specification file. A directed acyclic graph, interrelating the at least one service and an additional service based on the at least one requirement, is constructed. The directed acyclic graph is traversed using an initialization process to generate a determination which of an available plurality of services to provide. The determination further includes an analysis of the which of the available plurality of services to provide in view of at least one hardware resource in the data storage subsystem.

2010-12-16

20100318781

SECURE BOOT WITH OPTIONAL COMPONENTS METHOD - A method to allow a device to boot in a secure fashion, even though some of the components within the secure device's firmware may not be present, not correctly authorized, or not correctly operating.

2010-12-16

20100318782

SECURE AND PRIVATE BACKUP STORAGE AND PROCESSING FOR TRUSTED COMPUTING AND DATA SERVICES - A digital escrow pattern is provided for backup data services including searchable encryption techniques for backup data, such as synthetic full backup data, stored at remote site or in a cloud service, distributing trust across multiple entities to avoid a single point of data compromise. In one embodiment, an operational synthetic full is maintained with encrypted data as a data service in a cryptographically secure manner that addresses integrity and privacy requirements for external or remote storage of potentially sensitive data. The storage techniques supported include backup, data protection, disaster recovery, and analytics on second copies of primary device data. Some examples of cost-effective cryptographic techniques that can be applied to facilitate establishing a high level of trust over security and privacy of backup data include, but are not limited to, size-preserving encryption, searchable-encryption, or Proof of Application, blind fingerprints, Proof of Retrievability, and others.

2010-12-16

20100318783

SERVICE ACTIVATION USING ALGORITHMICALLY DEFINED KEY - Systems and methods for service activation using algorithmically defined keys are disclosed. A consumer who has a relationship with a first party may wish to enroll in a service provided by a third party. The first party can maintain control of such enrollments through the use of algorithmically defined keys. The algorithmically defined keys also allow the third party service provider to verify data provided by the consumer as matching data stored by the first party. The verification provides for data synchronization without requiring the third party to have access to the first parties data systems.

2010-12-16

20100318784

CLIENT IDENTIFICATION FOR TRANSPORTATION LAYER SECURITY SESSIONS - Systems, methods, and other embodiments associated with client identification for transportation layer security sessions are described. One example method includes monitoring a first transportation layer security (TLS) communication between a server and a client. The example method may also include interrupting the first TLS communication and causing the first TLS communication to be interrupted. The example method may also include initiating a second TLS communication with a client side device. The second TLS communication may request a certificate from the client side device. The certificate may include secure information that identifies the client. The example method may also include receiving the certificate from the client side device. The example method may also include authenticating the client, the client side device, and so on, based, at least in part, on the certificate.

2010-12-16

20100318785

VIRTUAL AIR GAP - VAG SYSTEM - This invention consists of a virtual air gap—VAG system developed in order to provide Internet and computer security. The virtual air gap system developed in this invention is characterized by the principal elements of: “Virtual air gap (

2010-12-16

20100318786

Trusted Hardware Component for Distributed Systems - Techniques for utilizing trusted hardware components for mitigating the effects of equivocation amongst participant computing devices of a distributed system are described herein. For instance, a distributed system employing a byzantine-fault-resilient protocol—that is, a protocol intended to mitigate (e.g., tolerate, detect, isolate, etc.) the effects of byzantine faults—may employ the techniques. To do so, the techniques may utilize a trusted hardware component comprising a non-decreasing counter and a key. This hardware component may be “trusted” in that the respective participant computing device cannot modify or observe the contents of the component in any manner other than according to the prescribed procedures, as described herein. Furthermore, the trusted hardware component may couple to the participant computing device in any suitable manner, such as via a universal serial bus (USB) connection or the like.

2010-12-16

20100318787

Method for Certifying a Public Key by an Uncertified Provider - The invention concerns a method for guaranteeing certification of a user's public key by reducing requests to key-certifying appropriate authorities. More particularly, the invention concerns a method for managing a public key of a user capable of being implemented in an asymmetric cryptosystem. According to the invention, a certification, or validation of the correspondence between a public key and a user, is performed by a validating entity, a provider separate from the certifying authority via a validation step. The password is verifiable by the validating entity, but without the latter being aware of it.

2010-12-16

20100318788

METHOD OF MANAGING SECURE COMMUNICATIONS - An exemplary method of managing secure communications between nodes includes receiving a public key of a node associated with a certification authority. A root node certificate is provided to the node responsive to the received public key. The root node certificate indicates that the received public key belongs to the node. A root self-signed certificate corresponding to a public key of the certification authority is also provided to the node.

2010-12-16

20100318789

METHOD AND SYSTEM FOR LICENSE MANAGEMENT - System and method are disclosed for securing and managing individual end-user platforms as part of an enterprise network. The method/system of the invention has three main components: a security module, a manager appliance, and a console appliance. The security module enforces the enterprise licenses and security policies for the end-user platforms while the manager appliance provides secure, centralized communication with, and oversight of, the security module. The console appliance allows an administrator to access the manager appliance for purposes of monitoring and changing the licenses. Security is established and maintained through an innovative use of data encryption and authentication procedures. The use of these procedures allows the appliances to be uniquely identified to one another, which in turn provides a way to dynamically create unique identifiers for the security modules. These various components together form an infrastructure over the enterprise network to securely manage the end-user platforms.

2010-12-16

20100318790

CARD MANAGEMENT DEVICE AND CARD MANAGEMENT SYSTEM - A card management device includes: a card device configured to include a controller on which a cryptographic IP is mounted in advance; and an individual information writing device configured to allow the card device to be connected to the individual information writing device in such a way that the card device is capable of data transfer to the individual information writing device, individual information assigned to the card device in advance being set in the individual information writing device, the individual information writing device being capable of writing the individual information to the card device connected to the individual information writing device.

2010-12-16

20100318791

CERTIFICATE STATUS INFORMATION PROTOCOL (CSIP) PROXY AND RESPONDER - Systems and methods are disclosed for providing certificate status information about a certificate includes receiving, at a Certificate Status Information Protocol (CSIP) proxy device the certificate identity information about the certificate of the second device. Then determining, using the CSIP proxy device, whether the certificate status information is stored in a CSIP proxy device memory. If the certificate status information is not stored in the CSIP proxy device memory, creating a CSIP request based on the certificate identity information and sending the CSIP request, including the certificate identity information, to a CSIP responder computer outside the local network domain. If the certificate status information is stored in the CSIP proxy device memory, sending the certificate status information to the first device. Also, a system and method are disclosed for using a CSIP responder computer.

2010-12-16

20100318792

ELECTRONIC SIGNATURE VERIFICATION METHOD IMPLEMENTED BY SECRET KEY INFRASTRUCTURE - An electronic signature verification method implemented by SKI infrastructure adopts a secret key infrastructure (SKI) system for registering a secret key and issuing a signature key and a verification key. After a signer has completed a signature, a signature data, a verification data and a verification key encrypted by the secret key of a signature verification unit are sent to a recipient. After the recipient has received the data, a user needs to send the verification data and the encrypted verification key to a signature verification unit if the user wants to confirm the signature on the signature data. The signature verification unit uses a secret key authorized by the SKI for the decryption to obtain the verification key and uses the verification key to verify the verification data and confirm the existence of the signature of the signature data, so as to authenticate the signature of the signature data.

2010-12-16

20100318793

Permission-Based Dynamically Tunable Operating System Kernel - A server includes a central processing unit and electronic memory communicatively coupled to the central processing unit. The memory stores a dynamically tunable operating system kernel that includes at least one tunable implemented as a plurality of states. Each application managed by the operating system is assigned to one of these states according to a permission level association with the application. Each state defines a range of automated tuning of the tunable that is authorized to applications assigned to the state.

2010-12-16

20100318794

System and Method for Providing Security Aboard a Moving Platform - A system for providing network security on a vehicle information system and methods for manufacturing and using same. The security system comprises an all-in-one security system that facilitates security system functions for the vehicle information system. Exemplary security system functions include secure storage of keys used to encrypt and/or decrypt system data, security-related application programming interfaces, a security log file, and/or private data. The security system likewise can utilize antivirus software, anti-spyware software, an application firewall, and/or a network firewall. As desired, the security system can include an intrusion prevention system and/or an intrusion detection system. If the information system includes a wireless distribution system, the security system can include an intrusion prevention (and/or detection) system that is suitable for use with wireless network systems. Thereby, the security system advantageously can provide a defense in depth approach by adding multiple layers of security to the information system.

2010-12-16

20100318795

BLOOM FILTER BASED DEVICE DISCOVERY - Aspects describe enabling two peers that have already paired together under some circumstances to re-identify themselves under different circumstances so that the peers can bypass performing another pairing only to discover that they are already paired. A Bloom filter is constructed from an available pool of locally selected identifiers and is sent to a peer node in a first message. Upon receiving the message with the Bloom filter, peer node checks all its known identifiers. If peer node finds that one of its identifiers is a member of the Bloom filter, peer node sends a reply in order to achieve a mutual identification.

2010-12-16

20100318796

METHOD AND SYSTEM FOR SECURING WIRELESS COMMUNICATIONS - A method for transmitting an encrypted signal to a wireless transmit/receive unit (WTRU) such that decryption of the encrypted signal depends on a trust zone associated with the WTRU is disclosed. The encryption may be performed using hierarchical modulation, scrambling, authentication, location validation, or a combination thereof. The size of a trust zone may also be adjusted.

2010-12-16

20100318797

SECURE DATA GATHERING FROM RENDERED DOCUMENTS - A facility for securing text captured from a rendered document is described. The facility receives data including an encryption of text captured from a rendered document. The facility decrypts the captured text included in the received data.

2010-12-16

20100318798

MESSAGE HANDLING AT A MOBILE DEVICE - A method for sending a message from a mobile device via a first application running on the mobile device is proposed. The method comprises a challenge step for supplying the first application with a challenge, a response step for receiving a response to the challenge, an equality check step for determining whether the received response corresponds to an expected response, a signature step for providing a signature for the message, using a cryptographic key and the result of the equality check step, and a send step for sending the signed message via the first application from the mobile device to a backend system.

2010-12-16

20100318799

DISCOVERY OF SECURE NETWORK ENCLAVES - A hierarchical key generation and distribution mechanism for a computer system in which devices are organized into secure enclaves. The mechanism enables network access to be tailored to approximate minimum needed privileges for each device. At the lowest level of the hierarchy, keys are used to form security associations between devices. Keys at each level of the hierarchy are generated from keys at a higher level of the hierarchy and key derivation information. Key derivation information is readily ascertainable, either from identifiers for devices or from within messages, supporting hardware offload of cryptographic functions. Because keys may be generated based on the enclaves in which the hosts participating in a security association are located, the system includes a mechanism by which devices can discover the enclave in which they are located.

2010-12-16

20100318800

KEY MANAGEMENT IN SECURE NETWORK ENCLAVES - A hierarchical key generation and distribution mechanism for a computer system in which devices are organized into secure enclaves. The mechanism enables network access to be tailored to approximate minimum needed privileges for each device. At the lowest level of the hierarchy, keys are used to form security associations between devices. Keys at each level of the hierarchy are generated from keys at a higher level of the hierarchy and key derivation information. Key derivation information is readily ascertainable, either from identifiers for devices or from within messages, supporting hardware offload of cryptographic functions. Because keys may be generated based on the enclaves in which the hosts participating in a security association are located, the system includes a mechanism by which devices can discover the enclave in which they are located.

2010-12-16

20100318801

METHOD AND SYSTEM FOR PROTECTING REAL ESTATE FROM FRADULENT TITLE CHANGES - A method of effecting secure communication over a network begins by interfacing a hardware token with a computer host. The hardware token includes security software and communication software stored thereon. The security software is stored in a memory of the hardware token. The computer host has a memory distinct from the hardware token memory. The authenticity of the security software is determined on the hardware token. Upon successful validation of the authenticity of the security software on the hardware token, the authenticity of the communication software is determined by loading the security software from the hardware token memory into the computer host memory and executing the loaded security software from the computer host memory. After successful validation of the authenticity of the communication software, the computer host facilitates communication between the hardware token and a remote computer by executing the communication software from the computer host memory.

2010-12-16

20100318802

SYSTEMS AND METHODS FOR ESTABLISHING A SECURE COMMUNICATION CHANNEL USING A BROWSER COMPONENT - A system for providing a secure channel for communication comprises a client comprising a browser, a secure server and a browser component installed on the client that enables a user to establish a connection with the secure server, the browser component configured to generate a first token. The secure server is configured to generate a second token, and wherein the client is provided with access to the secure server upon verification of the first token and the second token.

2010-12-16

20100318803

System and Methods for Assignation and Use of Media Content Subscription Service Privileges - This invention describes a system and methods for media content subscription service distribution; typical services include cable television, premium content channels, pay-per-view, XM radio, and online mp3 services. Subscribers use portable electronic devices to store digital certificates certifying the subscriber's privileges and an assigned public key. The devices can communicate with specially enabled televisions, radios, computers, or other media presentation apparatuses. These, in turn, can communicate with central databases owned by the provider, for verification purposes. Methods of the invention describe media content subscription service privilege issuing and use. The invention additionally describes methods for protecting media content transmitted to users with a variety of encryption schemes. The invention also comprises methods for subscribed users to bestow a subset of their privileges to a number of secondary users, with appropriate permission from the media content subscription service provider.

2010-12-16

20100318804

SCHEME OF APPLYING THE MODIFIED POLYNOMIAL-BASED HASH FUNCTION IN THE DIGITAL SIGNATURE ALGORITHM BASED ON THE DIVISION ALGORITHM - The present invention relates specifically to a modified digital signature algorithm together with a polynomial-based hash function, in which the last step of the calculation of the final hash value, the exponentiation, is omitted. Such a modification eliminates some of the potential attacks to which a basic hash function algorithm is susceptible. It further introduces several flexibilities to a digital signature scheme. For example, hashing and MAC-ing procedures omit an exponentiations step, whereby the security of data is increased as the possibility of successful attack is diminished. Furthermore, the present invention may be implemented either by way of hardware or software. It may also be capable of generating a digital signature for any set of parameters extracted from a message. Generation of a digital signature may occur without the step of a hashing or MAC-ing procedure.

2010-12-16

20100318805

PROTECTION AGAINST UNINTENTIONAL FILE CHANGING - Files are protected against intrusion. A first embodiment protects certain files against changes. A second embodiment encrypts the files that are stored using user's personal information.

2010-12-16

20100318806

MULTI-FACTOR AUTHENTICATION WITH RECOVERY MECHANISMS - A single sign on facility provides redundancy and recovery functions through the use of a plurality of identifiers. Users prove identity to relying parties by demonstrating control over each of the plurality of identifiers. A user can employ a subset of the identifiers recognized by an RP to change an identifier that has been lost or which the user has lost control over.

2010-12-16

20100318807

SYSTEM AND METHOD FOR GENERATING A DISGUISED PASSWORD BASED ON A REAL PASSWORD - A system and method for generating a disguised password are provided. The method presets a real password via an input device, selects one or more characters from the real password as a verification code. The method further generates an encryption code corresponding to the verification code according to an encryption algorithm, generates a character string based on the encryption code, and displays a verification box on a display screen to receive an input key from the input device. In addition, the method determines whether the input key matches the encryption code of the character string, and generates a disguised password by replacing the verification code with the encryption code in the real password if the input key matches the encryption code of the character string.

2010-12-16

20100318808

METHOD AND A SYSTEM FOR THE CUSTOMISATION OF SMART OBJECTS - This present invention concerns a customization method that represents a saving in time and an increase in yield, in the electronic customization of smart objects in particular, by virtue of:—a stage for establishing communication links between a multiplicity of smart objects held on a portable support, and communication interfaces,—a stage for simultaneous unlocking of the smart objects by means of a first key,—a stage for the parallel transfer into the memory of the smart objects of customization data proper to each of the smart objects, with these data being transferred into at least one memory zone of each smart object,—a stage for the locking of each smart object by means of second keys, each proper to one of the smart objects and each associated with the customization data proper to this object.

2010-12-16

20100318809

METHOD AND SYSTEM FOR CONTROLLING PRESENTATION OF COMPUTER READABLE MEDIA ON A MEDIA STORAGE DEVICE - A method of controlling presentation of content on a media storage device is described. The method is comprised of verifying the presence of a media presentation mechanism and a usage compliance mechanism on a computer system operated by a recipient to whom the media storage device is distributed. The usage compliance mechanism includes a file system filter driver for controlling data reads associated with the computer readable media. The media presentation mechanism is communicatively coupled with the usage compliance mechanism. The present method further includes the file system driver performing a first decryption of the computer readable media. The present method further includes the media presentation mechanism performing a second decrypting of the computer readable media concurrent with presenting the computer readable media to the recipient.

2010-12-16

20100318810

INSTRUCTION CARDS FOR STORAGE DEVICES - A card can be communicationally coupled to a storage device. The card can then cause the storage device to perform stand-alone tasks without a computing device. The card can invoke instructions already present in the firmware of the storage device or the card can first copy instructions to the firmware and then invoke them. The card can cause the storage device to perform actions, such as a secure erase, and the storage device can remain inaccessible until such actions are performed, even if power is interrupted. The card can also receive information from the storage devices and then use that information with a new storage device to, for example, enable the new storage device to take the place of, and reconstruct the data of, the old storage device in a storage array directly from other storage devices in the array and without burdening a computing device or array controller.

2010-12-16

20100318811

CRYPTOGRAPHIC PROCESSOR - A cryptographic processor includes: first and second round function operation circuits, each of which executes cryptographic processing; and a control circuit configured to operate the first and second round function operation circuits by randomly switching between a parallel operation mode used to operate the first and second round function operation circuits in parallel and a serial operation mode used to operate the first and second round function operation circuits in series.

2010-12-16

20100318812

SECURE AND PRIVATE BACKUP STORAGE AND PROCESSING FOR TRUSTED COMPUTING AND DATA SERVICES - A digital escrow pattern is provided for backup data services including searchable encryption techniques for backup data, such as synthetic full backup data, stored at remote site or in a cloud service, distributing trust across multiple entities to avoid a single point of data compromise. In one embodiment, an operational synthetic full is maintained with encrypted data as a data service in a cryptographically secure manner that addresses integrity and privacy requirements for external or remote storage of potentially sensitive data. The storage techniques supported include backup, data protection, disaster recovery, and analytics on second copies of primary device data. Some examples of cost-effective cryptographic techniques that can be applied to facilitate establishing a high level of trust over security and privacy of backup data include, but are not limited to, size-preserving encryption, searchable-encryption, or Proof of Application, blind fingerprints, Proof of Retrievability, and others.

2010-12-16

20100318813

NETWORK SECURITY DEVICE AND METHOD - The invention describes a method for hardening a security mechanism against physical intrusion and substitution attacks. A user establishes a connection between a network peripheral device and a network via a security mechanism. The security mechanism includes read only memory (ROM) that contains code that initiates operation of the mechanism and performs authentication functions. A persistent memory contains configuration information. A volatile memory stores user and device identification information that remains valid only for a given session and is erased thereafter to prevent a future security breach. A tamper-evident enclosure surrounds the memory elements, which if breached, becomes readily apparent to the user.

2010-12-16

20100318814

POWER MANAGEMENT DEVICE AND POINT OF SALES TERMINAL APPARATUS USING THEREOF - A point of sales (POS) terminal apparatus including a POS device, a peripheral device, which is controlled by the POS device, an adapter, and a power management device is provided. The adapter provides a first power signal based on a wall-outlet power signal. The power management device provides the first power signal to drive the POS device and determines whether the first power signal satisfies a predetermined condition. When the first power signal fails to satisfy the predetermined condition, the power management device generates a second power signal and drives the peripheral device with the second power signal. When the first power signal satisfies the predetermined condition, the power management device drives the peripheral device with the first power signal.

2010-12-16

20100318815

POWER SUPPLY CIRCUIT FOR AUDIO CODEC CHIP - A power supply circuit for an audio codec chip includes a power supply output terminal configured for providing a working voltage for the audio codec chip, a first filter circuit, a regulator circuit, and a second filter circuit. The first filter circuit is coupled to the power supply output terminal. The regulator circuit has an input terminal and an output terminal. The regulator circuit input terminal is connected to the first filter circuit. The second filter circuit is connected to the regulator circuit output terminal, and is coupled to a power source input terminal of the audio codec chip.

2010-12-16

20100318816

Separating Power Domains of Central Processing Units - A circuit includes a central processing unit (CPU), which includes a first memory block having a first power domain; and a core block signally connected to the first memory block and having a second power domain disconnected from the first power domain.

2010-12-16

20100318817

Information Processing Apparatus and System State Control Method - According to an aspect of the present invention, there is provided an information processing apparatus operable in an ordinary mode, a standby mode and a hibernation mode, the apparatus including: a sensor that measures a working-environment parameter of the apparatus; a backup circuit that is connected to the sensor and that supplies an electric power to the sensor when the apparatus is in the standby mode; a controller that includes an allowable range storage portion storing an allowable range for the working-environment parameter and that controls a supply of an electric power to the backup circuit; and a first unit that changes the apparatus from the standby mode to the hibernation mode based on the measured working-environment parameter and the stored allowable range.

2010-12-16

20100318818

Power consumption management - Embodiments include a system, an apparatus, a device, and a method. A system includes a power module operable to determine respective indicia of power consumed in executing at least one instruction by a first subcircuit and by a second subcircuit of a synchronous circuit. The system also includes a scheduler module operable to direct an execution task to a subcircuit selected from the first subcircuit and the second subcircuit. The subcircuit selection is responsive to the determined respective indicia of power consumption by the first subcircuit and by the second subcircuit.

2010-12-16

20100318819

System and Method for Integrated Temperature Measurement in Power over Ethernet Applications - A system and method for integrated thermal monitoring in Power over Ethernet (PoE) applications. Headroom in a particular cable installation is identified using ambient temperature measurement alone or in combination with determined cable characteristics. In calculating an amount of headroom for a particular cable installation, the current capable of being carried over the cable would not be limited by worst-case cable assumptions.

2010-12-16

20100318820

STORAGE SYSTEM POWER MANAGEMENT - A method for managing power consumed by storage systems and other devices is disclosed herein. In certain embodiments, such a method may include initially monitoring conditions (such as data traffic conditions) on a communication link between a first device and a second device. The method may further include determining whether the conditions on the communication link warrant powering down or powering up the second device. In the event the conditions warrant powering down the second device, a power-down command may be generated and transmitted from the first device to the second device. In the event the conditions warrant powering up the second device, a power-up command may be generated and transmitted from the first device to the second device. In selected embodiments, the power-up and power-down commands are one of SCSI commands and FICON commands. A corresponding apparatus, system, and computer-usable medium are also disclosed and claimed herein.

2010-12-16

20100318821

SCALABLE, DYNAMIC POWER MANAGEMENT SCHEME FOR SWITCHING ARCHITECTURES UTILIZING MULTIPLE BANKS - According to one general aspect, a method may include receiving data from a network device. In some embodiments, the method may include writing the data to a memory bank that is part of a plurality of at least single-ported memory banks that have been grouped to act as a single at least dual-ported aggregated memory element. In various embodiments, the method may include monitoring the usage of the plurality of memory banks. In one embodiment, the method may include, based upon a predefined set of criteria, placing a memory bank that meets the predefined criteria in a low-power mode.

2010-12-16

20100318822

ENERGY SAVING IN SYSTEMS-ON-CHIP - A System-on-Chip may include initiators, targets exchanging information with the initiators, and a control module. The control module may be configured to selectively set to one of different reduced power consumption modes each of the initiators and each of the targets based upon external reduced power consumption instructions, and selectively wake-up from the reduced power consumption mode each initiator and each target.

2010-12-16

20100318823

COMPUTER AND CONTROL METHOD THEREOF - A computer includes a CPU and a system unit, and further includes a power source, a system driving power generator which converts source power input from the power source to be outputted to the system unit, a CPU driving power generator which outputs driving power to drive the CPU, and a controller which selectively supplies either the source power from the power source or the system power converted from the system driving power generator to an input terminal of the CPU driving power generator according to an operation mode of the CPU. Thus, a computer adjusts a level of power supplied to a CPU driving power generator according to a CPU mode and improves power efficiency, and includes a control method thereof.

2010-12-16

20100318824

STORAGE DEVICE WITH ADVANCED POWER MANAGEMENT - In a particular embodiment, a data storage device includes a controller. The controller includes device performance management logic to retrieve an advanced power management (APM) setting from an APM register of a host system. The APM register includes a plurality of register settings adapted to represent a respective plurality of APM settings. The controller further includes policy selection logic to select at least one storage device (SD) policy from a plurality of SD policies based on the determined APM setting and configuration logic to apply the selected at least one SD policy to adjust at least one of a performance characteristic and a power characteristic associated with first and second data storage media.

2010-12-16

20100318825

Power Conservation During A Power Mode Transition - An apparatus and associated method to begin performing a power reduction enablement sequence based on a first predetermined value of elapsed time after an execution of a data access command is completed. The power reduction enablement sequence is performed at an adaptively selected rate that is related to a second predetermined value of elapsed time after the execution that calls for a switch to a reduced power mode for the apparatus.

ENERGY USE PROFILING FOR WORKLOAD TRANSFER - Embodiments of energy profiling for workload transfer are disclosed. In accordance with at least one embodiment, the energy profiling for workload transfer includes determining a baseline wattage of a first server. Further, a load wattage of a workload is derived using a difference between the baseline wattage consumption and an overall wattage consumption. The workload is transferred to a second server when the load wattage is less than an available wattage on the second server.

2010-12-16

20100318828

Method And System For Generating A Power Consumption Model Of At Least One Server - A system for generating a power consumption model of at least one server includes one or more computers configured to obtain n time series telemetry signals indicative of operating parameters of the at least one server, obtain a time series power signal indicative of power consumed by the at least one server, and correlate each of the n time series telemetry signals with the time series power signal. The one or more computers are further configured to select a set of the n time series telemetry signals having an overall correlation with the time series power signal greater than a predetermined threshold, and generate a power consumption model of the at least one server based on at least the set of the n time series telemetry signals.