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Xilinx Vivado: Faster and Better

When you think of Xilinx the word FPGA is the first that comes to mind. But Xilinx has really moved beyond the sort of simple glue-logic arrays that their first success was built on. A modern array contains processors as well as programmable fabric, hence the Xilinx tag-line “all programmable”. But another area that doesn’t always get as much recognition as it should is Xilinx’s software toolchain. Today they announced a new version of their Vivado tool suite, 2014.3. The headline news is that it is significantly faster and so allows users to focus on the differentiated part of doing their design and less on the routine of getting the design into silicon. There is also an increased focus on high-level synthesis (HLS), basically programming your design in C rather than RTL.

The IP Integrator has been improved in many ways. It used to be that to connect a stream interface to a memory mapped interface you had to create your own DMA device but now that is handled automatically. There is also support for 3rd party IP being evaluated/purchased directly from within the tool. A large part of many designs is simply picking the IP required and hooking it up.

One the HLS front there are now over 1000 users with huge increases in productivity from using C for versus using RTL. They reckon design productivity is up 10X since it is possible to explore multiple microarchtectures in a way that you simply cannot do with RTL. And verification productivity using C versus RTL is about 1000 times faster. For those designs that can make use of HLS this is now an industrial strength technology ready for real-world designs.

With the Ultrafast design methodology you don’t need to do a P&R of the design before closing power, timing etc. You just need to do synthesis (which is much faster than P&R) and then use the new design analysis and reporting capabilities. So of course it is possible to iterate quickly.

The overall performance and QoR of the basic algorithms have been improved across the board: