Hysteretic dc SQUIDs provide an easy method to read the state of hundreds of qubits\footnote{Supercond. Sci. Technol. \textbf{23}, 105014 (2010)}. However, this approach becomes impractical for circuits with an even larger number of qubits due to heating when dc SQUIDs switch, the relatively slow retrapping dynamics of high quality devices, and suboptimal scaling of the number of control lines with increasing numbers of qubits.
The D-Wave Two processor uses an architecture that addresses all three of these issues. This new architecture makes use of Quantum Flux Parametron based shift registers that transfer the classical information produced as the output of the quantum annealing algorithm to a small number of fast non-dissipative and high fidelity microwave readout devices. We will provide an introduction to our implementation, and present data pertaining to readout performance from a 512-qubit quantum annealing processor.

To cite this abstract, use the following reference: http://meetings.aps.org/link/BAPS.2014.MAR.D35.12