topic Re: Constraining Clock Domain Crossing for Related Phase Shifted Clocks in Timing Analysishttps://forums.xilinx.com/t5/Timing-Analysis/Constraining-Clock-Domain-Crossing-for-Related-Phase-Shifted/m-p/1074852#M18805
<P>We replaced the -early/-late constraints in the -set_clock_latency with -min/-max... we got the same results, and as far as we can tell there is no difference.&nbsp; The data capture at the I/O fails because of the added skew between clock and data; but the clock-domain crossings are being analyzed and passing.</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="image (34).png" style="width: 999px;"><img src="https://xlnx.i.lithium.com/t5/image/serverpage/image-id/70971i5850122856842F79/image-size/large?v=1.0&amp;px=999" title="image (34).png" alt="image (34).png" /></span><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="image (33).png" style="width: 999px;"><img src="https://xlnx.i.lithium.com/t5/image/serverpage/image-id/70972i1F57B2DA933C4D9E/image-size/large?v=1.0&amp;px=999" title="image (33).png" alt="image (33).png" /></span></P><P>So, we are still trying to figure out how to properly constrain the data catpure at the I/O in such a manner that the data follows the clock.</P>Thu, 13 Feb 2020 15:13:15 GMTbgiesing2020-02-13T15:13:15ZConstraining Clock Domain Crossing for Related Phase Shifted Clockshttps://forums.xilinx.com/t5/Timing-Analysis/Constraining-Clock-Domain-Crossing-for-Related-Phase-Shifted/m-p/1073640#M18787
<P>We have a situation very similar to that described in:</P><P><A href="https://forums.xilinx.com/t5/Timing-Analysis/Direct-data-crossing-between-synchronous-clocks/td-p/1002173" target="_blank">https://forums.xilinx.com/t5/Timing-Analysis/Direct-data-crossing-between-synchronous-clocks/td-p/1002173</A></P><P>In our case, we are using an Ultrascale KCKU060, capturing source-synchronous DDR data from 18 ADCs.&nbsp; Each ADC drives a data clock (DCO) to the FPGA for capturing their respective data streams.&nbsp; We also forward the actual sample clock as a common clock, as we need to reconcile all 18 streams and assure they remain synchronous and processed on the same clock edge.</P><P>The delay of the sample clock through the ADCs, combined with the differences in routing delays across 18 ADCs, gives DCOs that are phase-shifted from the the common clock in the FPGA.&nbsp; However, the phase shift is not arbitrary and can be bounded, so we figured we could write some constraints to force the tool to analyze the clock domain crossing.&nbsp; We use an MMCM on the common clock to allow us to place the common clock in the optimal window for the domain crossing.</P><P>We have attempted to use the set_clock_latency on the DCO clocks, setting both a min and a max, expecting that to force the tool to analyze the domain crossing (since all clocks are related in Vivado unless constrained otherwise).&nbsp; It turned out that applying the latency to the DCOs broke the capture of the data itself at the input - which makes sense because apparently the tool has no idea that the input data moves with the clock when the clock latency goes min or max (this is the case for the ADCs).&nbsp;</P><P>Then we applied the set_clock_latency min/max to the common clock.&nbsp; This "fixed" the input data capture for each of the DCOs, but there is no indication that our min/max latency's are being applied at the clock domain crossing.&nbsp; Indeed, the only thing applied was the phase shift on the common clock introduced by the MMCM.&nbsp; Timing closed, but again the variation due to the latency did not appear to be applied.</P><P>We have tried multiple other variations, including using -include_generated_clocks directives and various virtual clock constraints per the directions of some of the ARs and forum posts without any success.</P><P>Is there any way to get the tool to analyze a clock domain crossing with min/max latency being applied to one of the clocks?</P><P>Thank you,</P><P>Brian</P><P>&nbsp;</P>Tue, 11 Feb 2020 00:09:37 GMThttps://forums.xilinx.com/t5/Timing-Analysis/Constraining-Clock-Domain-Crossing-for-Related-Phase-Shifted/m-p/1073640#M18787bgiesing2020-02-11T00:09:37ZRe: Constraining Clock Domain Crossing for Related Phase Shifted Clockshttps://forums.xilinx.com/t5/Timing-Analysis/Constraining-Clock-Domain-Crossing-for-Related-Phase-Shifted/m-p/1073656#M18790
<P>Can you provide a diagram to show the signal connections on this interface.</P><P>And can you give some screenshots of the timing report to explain what you saw or the entire timing report?</P><P>-vivian</P>Tue, 11 Feb 2020 01:47:17 GMThttps://forums.xilinx.com/t5/Timing-Analysis/Constraining-Clock-Domain-Crossing-for-Related-Phase-Shifted/m-p/1073656#M18790viviany2020-02-11T01:47:17ZRe: Constraining Clock Domain Crossing for Related Phase Shifted Clockshttps://forums.xilinx.com/t5/Timing-Analysis/Constraining-Clock-Domain-Crossing-for-Related-Phase-Shifted/m-p/1073935#M18798
<P>A PDF of one of the interfaces is attached.&nbsp; The "common clock" is called&nbsp;<FONT>DSP1_ADC_CLK_P/N in the schematic.&nbsp; It enters the differential buffer then flows to the MMCM and onto a global clock tree.&nbsp; The MMCM is set to delay the clock 5/8 cycle.<BR /></FONT></P><P>The source-sync clock from the ADC is called&nbsp;<FONT>RF0_ADC2_DCO_P/N in the schematic, and the data is&nbsp;RF0_ADC2_D_P/N[7:2].&nbsp; The data is routed to an IDELAY3 to allow for fixed-time delay with voltage-temperature compensation.&nbsp; The ADC data/clock are routed to an IDDRE1 in same-edge pipelined mode (technically speaking, routed to an ISERDES3 that is set as an IDDRE1).&nbsp;<BR /></FONT></P><P><FONT>We have attempted a number of variations of timing constraints, applying latency to the DCO and applying latency to the common clock, as well as attempting to constrain the input data capture using the clock pin and "virtual clocks".&nbsp; My first post was somewhat inaccurate.&nbsp; Whenever we try to constrain the input delay of the ADC data/DCO interface using the "virtual clock" method, we cannot close timing on the data capture.&nbsp; When we constrain the input delay of the ADC data/DCO interface using the actual clock pin, then we close timing on that capture.&nbsp; In no cases have we been able to see the latency getting included in the clock domain cross between the DCO and common clock.&nbsp; Here are a set of constraints as examples of what we have tried.&nbsp; I will run fresh builds, and post fresh constraints and timing results, to ensure I am posting timing reports reflective of specific constraint sets (we have tried so many things, I don't want to post something inconsistent).</FONT></P><P><FONT>Note that the -set_clock_latency is being used with -early/-late rather than -min/-max.&nbsp; Is this a potential issue?&nbsp; Also note that -set_clock_latency is being applied to a clock that has been defined with a -waveform directive.&nbsp; Is this a potential issue? Does -waveform override -set_clock_latency?</FONT></P><P><FONT>Here are the constraints for our attempt to apply latency to the common clock:</FONT></P><DIV><FONT face="courier new,courier">create_clock -period&nbsp; 4.568 -name RF0_ADC2_DCO_P [get_ports RF0_ADC2_DCO_P]<BR />create_clock -period 4.568 -name DSP1_ADC_CLK_P -waveform {0.000 2.284} [get_ports DSP1_ADC_CLK_P]<BR />set_clock_latency -rise -fall -source -early -1.061 [get_ports DSP1_ADC_CLK_P]<BR />set_clock_latency -rise -fall -source -late&nbsp;&nbsp; 1.061 [get_ports DSP1_ADC_CLK_P]</FONT></DIV><DIV><FONT face="courier new,courier"><BR /># Edge-Aligned Double Data Rate Source Synchronous Inputs -- FROM TEMPLATE<BR />set input_adcclk_period 4.568;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; # Period of input clock (full-period)<BR />create_clock -name virt_adcclk -period $input_adcclk_period;<BR />set skew_bre&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0.280;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; # Data invalid before the rising clock edge<BR />set skew_are&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0.100;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; # Data invalid after the rising clock edge<BR />set skew_bfe&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0.280;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; # Data invalid before the falling clock edge<BR />set skew_afe&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0.100;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; # Data invalid after the falling clock edge<BR />set_input_delay -clock RF0_ADC2_DCO_P -max [expr $input_adcclk_period/2 + $skew_afe] [get_ports {RF0_ADC2_D_P[*]}];<BR />set_input_delay -clock RF0_ADC2_DCO_P -min [expr $input_adcclk_period/2 - $skew_bfe] [get_ports {RF0_ADC2_D_P[*]}];<BR />set_input_delay -clock RF0_ADC2_DCO_P -max [expr $input_adcclk_period/2 + $skew_are] [get_ports {RF0_ADC2_D_P[*]}] -clock_fall -add_delay;<BR />set_input_delay -clock RF0_ADC2_DCO_P -min [expr $input_adcclk_period/2 - $skew_bre] [get_ports {RF0_ADC2_D_P[*]}] -clock_fall -add_delay;</FONT></DIV><DIV>&nbsp;</DIV><DIV><FONT>And here are the constraints for our attempt at setting latency for the DCO rather than the common clock:</FONT></DIV><DIV>&nbsp;</DIV><DIV><DIV><FONT face="courier new,courier">create_clock -period 4.568 -name DSP1_ADC_CLK_P -waveform {0.000 2.284} [get_ports DSP1_ADC_CLK_P]<BR />create_clock -period&nbsp; 4.568 -name RF0_ADC2_DCO_P -waveform {0.000&nbsp; 2.284} [get_ports RF0_ADC2_DCO_P]<BR />set_clock_latency -rise -fall -source -early -0.991 [get_ports RF0_ADC2_DCO_P]<BR />set_clock_latency -rise -fall -source -late&nbsp;&nbsp; 0.009 [get_ports RF0_ADC2_DCO_P]</FONT></DIV><DIV><FONT><FONT face="courier new,courier"># Edge-Aligned Double Data Rate Source Synchronous Inputs -- FROM TEMPLATE</FONT><BR /><FONT face="courier new,courier">set input_adcclk_period 4.568;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; # Period of input clock (full-period)</FONT><BR /><FONT face="courier new,courier">create_clock -name virt_adcclk_02 -period $input_adcclk_period;</FONT><BR /><FONT face="courier new,courier">set skew_bre&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0.280;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; # Data invalid before the rising clock edge</FONT><BR /><FONT face="courier new,courier">set skew_are&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0.100;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; # Data invalid after the rising clock edge</FONT><BR /><FONT face="courier new,courier">set skew_bfe&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0.280;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; # Data invalid before the falling clock edge</FONT><BR /><FONT face="courier new,courier">set skew_afe&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 0.100;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; # Data invalid after the falling clock edge</FONT><BR /><FONT face="courier new,courier"># Input Delay Constraint (Proto)</FONT><BR /><FONT face="courier new,courier">set_input_delay -clock virt_adcclk_02 -max [expr $input_adcclk_period/2 + $skew_afe] [get_ports {RFDC0_ADC2_D_P[*]}];</FONT><BR /><FONT face="courier new,courier">set_input_delay -clock virt_adcclk_02 -min [expr $input_adcclk_period/2 - $skew_bfe] [get_ports {RFDC0_ADC2_D_P[*]}];</FONT><BR /><FONT face="courier new,courier">set_input_delay -clock virt_adcclk_02 -max [expr $input_adcclk_period/2 + $skew_are] [get_ports {RFDC0_ADC2_D_P[*]}] -clock_fall -add_delay;</FONT><BR /><FONT face="courier new,courier">set_input_delay -clock virt_adcclk_02 -min [expr $input_adcclk_period/2 - $skew_bre] [get_ports {RFDC0_ADC2_D_P[*]}] -clock_fall -add_delay;</FONT><BR /></FONT></DIV></DIV><P>&nbsp;</P><P>Thanks,</P><P>Brian</P>Tue, 11 Feb 2020 16:47:15 GMThttps://forums.xilinx.com/t5/Timing-Analysis/Constraining-Clock-Domain-Crossing-for-Related-Phase-Shifted/m-p/1073935#M18798bgiesing2020-02-11T16:47:15ZRe: Constraining Clock Domain Crossing for Related Phase Shifted Clockshttps://forums.xilinx.com/t5/Timing-Analysis/Constraining-Clock-Domain-Crossing-for-Related-Phase-Shifted/m-p/1074100#M18800
<P>I have a couple of ideas...</P>
<P>First, are you sure this is doable? The differences in the paths inside the FPGA will already be pretty significant (since one is going through an MMCM and BUFG with clock deskew, and the other is going to a BUFGCE_DIV directly. This is in addition to the path through the ADC (from the reference clock to the DCO) - all this uncertainty has to be fairly significantly less than the 4.568ns...</P>
<P>First thing is to revisit the set_clock_latency. There are a couple of things to look at.</P>
<P>It looks like in your attempt to add the latency to the DCO clock you constrain the I/O with a virtual clock. You definitely don't want to do this. If you do so then you are explicitly saying "the virtual clock has no variation, but the DCO clock does, so when you are looking at the timing between them (i.e. the set_input_delay), take the uncertaintly into account". This is the exact opposite of what you want - you are trying to convince it that the I/O "moves" with the DCO clock. So specify the I/O with respect to the same clock that you define on the DCO input pin (RF*_ADC*_DCO_P) - so in your second set of constraints, replace virt_adc_clk with RF2_ADC0_DCO_P.</P>
<P>Next, while the description is fairly vague, I seem to remember that the uncertainty is treated differently if it is attached to the <STRONG>clock</STRONG> vs. if it is attached to the <STRONG>port</STRONG>. When attached to the port, it affects all the clock downstream from that, which means the stuff inside the FPGA. When attached to the clock it is possible that it will apply to <STRONG>all </STRONG>things referenced to that clock, including the set_input_delay commands that use that clock. If so, then this would do what you want - change the latency of the DCO clocks, but not affect the relationship between the data and the DCO clock. This command also has the -clock option, which may also change the behavior - try combinations of this and see if they do what you want. Yours is applied to the port, so it definitely will only affect the inside of the FPGA (and not the set_input_delay commands).</P>
<P>So, try</P>
<PRE>create_clock -period 4.568 -name DSP1_ADC_CLK_P -waveform {0.000 2.284} [get_ports DSP1_ADC_CLK_P]
create_clock -period 4.568 -name RF0_ADC2_DCO_P -waveform {0.000 2.284} [get_ports RF0_ADC2_DCO_P]
set_clock_latency -rise -fall -source -early -0.991 <STRONG>-clock</STRONG> [get_<STRONG>clocks</STRONG> RF0_ADC2_DCO_P]
set_clock_latency -rise -fall -source -late 0.009 <STRONG>-clock</STRONG> [get_<STRONG>clocks</STRONG> RF0_ADC2_DCO_P]
# Edge-Aligned Double Data Rate Source Synchronous Inputs -- FROM TEMPLATE
set input_adcclk_period 4.568; # Period of input clock (full-period)
<STRONG><STRIKE>create_clock -name virt_adcclk_02 -period $input_adcclk_period;</STRIKE></STRONG>
set skew_bre 0.280; # Data invalid before the rising clock edge
set skew_are 0.100; # Data invalid after the rising clock edge
set skew_bfe 0.280; # Data invalid before the falling clock edge
set skew_afe 0.100; # Data invalid after the falling clock edge
# Input Delay Constraint (Proto)
set_input_delay -clock <STRONG>RF0_ADC2_DCO_P</STRONG> -max [expr $input_adcclk_period/2 + $skew_afe] [get_ports {RFDC0_ADC2_D_P[*]}];
set_input_delay -clock <STRONG>RF0_ADC2_DCO_P</STRONG> -min [expr $input_adcclk_period/2 - $skew_bfe] [get_ports {RFDC0_ADC2_D_P[*]}];
set_input_delay -clock <STRONG>RF0_ADC2_DCO_P</STRONG> -max [expr $input_adcclk_period/2 + $skew_are] [get_ports {RFDC0_ADC2_D_P[*]}] -clock_fall -add_delay;
set_input_delay -clock <STRONG>RF0_ADC2_DCO_P</STRONG> -min [expr $input_adcclk_period/2 - $skew_bre] [get_ports {RFDC0_ADC2_D_P[*]}] -clock_fall -add_delay;</PRE>
<P>Second, it is a poorer solution, but you may be able to do something with the set_clock_uncertainty command. When applied to a single clock it manifests as jitter on the clock. However, you can use the -from and -to options to specify an "inter-clock" uncertainty. This isn't the same as specifying a skew (min and max0, but you may be able to make that work.</P>
<P>Next, if all else fails, you can specify the timing requirements on the paths between the domains directly using the set_max_delay command and the set_min_delay command. Without the -datapath_only flag, the tools will use the requirement while still taking into account the clock insertion delays (so it will take into account the diffferent paths through the clocking resources). So, lets say the ADC (and routing imbalance) have the DCO clock coming 0.5 to 1.0ns later than the clock directly to the FPGA. You could use this information for set_max_delay commands between the clocks. The set_max_delay from REF clock to DCO clock would be (period-1ns) max, and 0.5ns min (I think - you would need to check the sign on this, it could be -0.5). In the other direction (from DCO clock to REF clock) it would be the opposite.</P>
<P>Finally, this is UltraScale+. In UltraScale+, the PHASESHIFT_MODE of the MMCM defaults to LATENCY (not WAVEFORM, which is what it did for all previous families). For this example, where you are crossing between clocks that do and don't go through the MMCM (and are trying to let the tools account for the skew between the clocks), I am pretty sure you want the MMCM to be in WAVEFORM mode - take a look at <A href="https://forums.xilinx.com/t5/Timing-Analysis/Timing-Constraint-for-phase-shifted-mmcm-output/m-p/1042854#M18131" target="_self">this post on PHASESHIFT_MODE</A>. To change it, you need to set the property on the MMCM through the XDC file.</P>
<P>set_property PHASESHIFT_MODE WAVEFORM [get_cells &lt;instance_name_of_mmcm&gt;]</P>
<P>Let me know what you try and what results you get!</P>
<P>Avrum</P>Wed, 12 Feb 2020 04:37:16 GMThttps://forums.xilinx.com/t5/Timing-Analysis/Constraining-Clock-Domain-Crossing-for-Related-Phase-Shifted/m-p/1074100#M18800avrumw2020-02-12T04:37:16ZRe: Constraining Clock Domain Crossing for Related Phase Shifted Clockshttps://forums.xilinx.com/t5/Timing-Analysis/Constraining-Clock-Domain-Crossing-for-Related-Phase-Shifted/m-p/1074431#M18801
<P>Thanks Avrum -</P><P>Firstly: no, we are not sure this is even possible.&nbsp; Hopefully the tool will be able to tell us.</P><P>Secondly: one point of clarification with respect to the -set_clock_latency; should we be using -early/-late or -min/-max?&nbsp; In previous answers, it seemed -min/-max was used.&nbsp; I do not fully understand the implications of one method versus the other.</P><P>Once we are straight on that, we will start running some builds with your other suggestions.</P><P>Thanks again,</P><P>Brian</P>Wed, 12 Feb 2020 19:55:34 GMThttps://forums.xilinx.com/t5/Timing-Analysis/Constraining-Clock-Domain-Crossing-for-Related-Phase-Shifted/m-p/1074431#M18801bgiesing2020-02-12T19:55:34ZRe: Constraining Clock Domain Crossing for Related Phase Shifted Clockshttps://forums.xilinx.com/t5/Timing-Analysis/Constraining-Clock-Domain-Crossing-for-Related-Phase-Shifted/m-p/1074550#M18802
<P>First build finished.&nbsp; Some progress, but still not quite there.&nbsp; Here are the relevant constraints used:</P><P>&nbsp;</P><PRE>create_clock -period 4.568 -name DSP1_ADC_CLK_P [get_ports DSP1_ADC_CLK_P]
create_clock -period 4.568 -name RF0_ADC0_DCO_P [get_ports RF0_ADC0_DCO_P]
set_clock_latency -rise -fall -source -early -1.061 -clock [get_clocks RF0_ADC0_DCO_P] [get_clocks RF0_ADC0_DCO_P]
set_clock_latency -rise -fall -source -late -0.061 -clock [get_clocks RF0_ADC0_DCO_P] [get_clocks RF0_ADC0_DCO_P]
# Edge-Aligned Double Data Rate Source Synchronous Inputs -- FROM TEMPLATE
set input_adcclk_period 4.568; # Period of input clock (full-period)
set skew_bre 0.280; # Data invalid before the rising clock edge
set skew_are 0.100; # Data invalid after the rising clock edge
set skew_bfe 0.280; # Data invalid before the falling clock edge
set skew_afe 0.100; # Data invalid after the falling clock edge
# Input Delay Constraint
set_input_delay -clock RF0_ADC0_DCO_P -max [expr $input_adcclk_period/2 + $skew_afe] [get_ports {RF0_ADC0_D_P[*]}];
set_input_delay -clock RF0_ADC0_DCO_P -min [expr $input_adcclk_period/2 - $skew_bfe] [get_ports {RF0_ADC0_D_P[*]}];
set_input_delay -clock RF0_ADC0_DCO_P -max [expr $input_adcclk_period/2 + $skew_are] [get_ports {RF0_ADC0_D_P[*]}] -clock_fall -add_delay;
set_input_delay -clock RF0_ADC0_DCO_P -min [expr $input_adcclk_period/2 - $skew_bre] [get_ports {RF0_ADC0_D_P[*]}] -clock_fall -add_delay;
</PRE><P>With those constraints, we failed the data capture at the IO.&nbsp; It appears the tool applied the "late" clock source latency to the data path, but the "early" clock souce latency to the clock path.&nbsp; Again, in our system these should be linked:</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="image (31).png" style="width: 999px;"><img src="https://xlnx.i.lithium.com/t5/image/serverpage/image-id/70897i43298B250FF0203C/image-size/large?v=1.0&amp;px=999" title="image (31).png" alt="image (31).png" /></span></P><P>However, what's encouraging is that it does appear the tool properly applied the "late" latency at the clock domain crossing (I need to find the "early" corner too):</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="image (32).png" style="width: 999px;"><img src="https://xlnx.i.lithium.com/t5/image/serverpage/image-id/70899i36BBAEAEA991C290/image-size/large?v=1.0&amp;px=999" title="image (32).png" alt="image (32).png" /></span></P><P>&nbsp;</P><P>&nbsp;</P>Thu, 13 Feb 2020 02:28:48 GMThttps://forums.xilinx.com/t5/Timing-Analysis/Constraining-Clock-Domain-Crossing-for-Related-Phase-Shifted/m-p/1074550#M18802bgiesing2020-02-13T02:28:48ZRe: Constraining Clock Domain Crossing for Related Phase Shifted Clockshttps://forums.xilinx.com/t5/Timing-Analysis/Constraining-Clock-Domain-Crossing-for-Related-Phase-Shifted/m-p/1074852#M18805
<P>We replaced the -early/-late constraints in the -set_clock_latency with -min/-max... we got the same results, and as far as we can tell there is no difference.&nbsp; The data capture at the I/O fails because of the added skew between clock and data; but the clock-domain crossings are being analyzed and passing.</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="image (34).png" style="width: 999px;"><img src="https://xlnx.i.lithium.com/t5/image/serverpage/image-id/70971i5850122856842F79/image-size/large?v=1.0&amp;px=999" title="image (34).png" alt="image (34).png" /></span><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="image (33).png" style="width: 999px;"><img src="https://xlnx.i.lithium.com/t5/image/serverpage/image-id/70972i1F57B2DA933C4D9E/image-size/large?v=1.0&amp;px=999" title="image (33).png" alt="image (33).png" /></span></P><P>So, we are still trying to figure out how to properly constrain the data catpure at the I/O in such a manner that the data follows the clock.</P>Thu, 13 Feb 2020 15:13:15 GMThttps://forums.xilinx.com/t5/Timing-Analysis/Constraining-Clock-Domain-Crossing-for-Related-Phase-Shifted/m-p/1074852#M18805bgiesing2020-02-13T15:13:15ZRe: Constraining Clock Domain Crossing for Related Phase Shifted Clockshttps://forums.xilinx.com/t5/Timing-Analysis/Constraining-Clock-Domain-Crossing-for-Related-Phase-Shifted/m-p/1074875#M18806
<P>Quick note: we are adding the&nbsp;<SPAN>-source_latency_included switch to the -set_input_delay constraint... will post results in a few hours, once the build completes.</SPAN></P>Thu, 13 Feb 2020 16:10:58 GMThttps://forums.xilinx.com/t5/Timing-Analysis/Constraining-Clock-Domain-Crossing-for-Related-Phase-Shifted/m-p/1074875#M18806bgiesing2020-02-13T16:10:58ZRe: Constraining Clock Domain Crossing for Related Phase Shifted Clockshttps://forums.xilinx.com/t5/Timing-Analysis/Constraining-Clock-Domain-Crossing-for-Related-Phase-Shifted/m-p/1075165#M18809
<P>Adding the "-source_latency_included" switch to the "-set_input_delay" switch only did half of what we wanted... it no longer skews the data to one extreme, but still skews clock to the other extreme.&nbsp; Thus, we still fail timing at the I/O data capture:</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="image (35).png" style="width: 999px;"><img src="https://xlnx.i.lithium.com/t5/image/serverpage/image-id/71008iD1562E6A9C70CE5F/image-size/large?v=1.0&amp;px=999" title="image (35).png" alt="image (35).png" /></span></P>Fri, 14 Feb 2020 11:58:27 GMThttps://forums.xilinx.com/t5/Timing-Analysis/Constraining-Clock-Domain-Crossing-for-Related-Phase-Shifted/m-p/1075165#M18809bgiesing2020-02-14T11:58:27ZRe: Constraining Clock Domain Crossing for Related Phase Shifted Clockshttps://forums.xilinx.com/t5/Timing-Analysis/Constraining-Clock-Domain-Crossing-for-Related-Phase-Shifted/m-p/1075218#M18810
<P>Still no luck...</P><P>This time, we tried to add the -set_clock_latency to the common clock, encompassing the skews arcross all 18 of the incoming DCOs.&nbsp; The tool says it passed timing, and that the latency constraint was accepted, but there is no evidence of the skew at the domain crossing.&nbsp; Perhaps the MMCM is hiding it?</P><P><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="image (36).png" style="width: 980px;"><img src="https://xlnx.i.lithium.com/t5/image/serverpage/image-id/71017i83961F9234B66C24/image-size/large?v=1.0&amp;px=999" title="image (36).png" alt="image (36).png" /></span><span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="image (37).png" style="width: 999px;"><img src="https://xlnx.i.lithium.com/t5/image/serverpage/image-id/71018iABA54D7E3E59870D/image-size/large?v=1.0&amp;px=999" title="image (37).png" alt="image (37).png" /></span></P>Fri, 14 Feb 2020 15:02:09 GMThttps://forums.xilinx.com/t5/Timing-Analysis/Constraining-Clock-Domain-Crossing-for-Related-Phase-Shifted/m-p/1075218#M18810bgiesing2020-02-14T15:02:09Z