Data Plane Packet Processing Embedded Intel® Architecture: Paper

Data Plane Packet Processing Embedded Intel® Architecture: Paper

Executive SummaryData plane packet processing involves moving data from an I/O device to system memory, classifying the data, then moving the data to a destination I/O device as quickly as possible. At the high speeds of modern communication, this puts pressure on the system bus as data is moved between I/O devices, system memory, and the processors classifying the data. This application is made even more challenging under a distributed memory architecture, where minimal and deterministic I/O latency must be ensured. This paper describes techniques that can be used to overcome these technical challenges and achieve high-performance data plane packet processing on embedded Intel® architecture platforms.

Executive SummaryData plane packet processing involves moving data from an I/O device to system memory, classifying the data, then moving the data to a destination I/O device as quickly as possible. At the high speeds of modern communication, this puts pressure on the system bus as data is moved between I/O devices, system memory, and the processors classifying the data. This application is made even more challenging under a distributed memory architecture, where minimal and deterministic I/O latency must be ensured. This paper describes techniques that can be used to overcome these technical challenges and achieve high-performance data plane packet processing on embedded Intel® architecture platforms.