(Cat? OR feline) AND NOT dog?
Cat? W/5 behavior
(Cat? OR feline) AND traits
Cat AND charact*

This guide provides a more detailed description of the syntax that is supported along with examples.

This search box also supports the look-up of an IP.com Digital Signature (also referred to as Fingerprint); enter the 72-, 48-, or 32-character code to retrieve details of the associated file or submission.

Concept Search - What can I type?

For a concept search, you can enter phrases, sentences, or full paragraphs in English. For example, copy and paste the abstract of a patent application or paragraphs from an article.

Concept search eliminates the need for complex Boolean syntax to inform retrieval. Our Semantic Gist engine uses advanced cognitive semantic analysis to extract the meaning of data. This reduces the chances of missing valuable information, that may result from traditional keyword searching.

Redundancy Compare Latch

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

In the high-density, high-end arrays, redundancy must be used to enhance the yield, and address inputs must be latched to relax the timing constraints. However, when the spare array is accessed, a delay penalty of one compare circuit stage is always incurred. This is illustrated in Fig. 1.

Country

United States

Language

English (United States)

This text was extracted from an ASCII text file.

This is the abbreviated version, containing approximately
69% of the total text.

Redundancy Compare Latch

In the
high-density, high-end arrays, redundancy must be
used to enhance the yield, and address inputs must be latched to
relax the timing constraints. However,
when the spare array is
accessed, a delay penalty of one compare circuit stage is always
incurred. This is illustrated in Fig. 1.

Since the
compare circuit must drive large fan-outs and operate
in large voltage swings, the nominal delay penalty is about 200-300
ps, which amounts to over 10% of a typical array access time. Since
the array circuits are already optimized for performance, not much
delay can be reduced by brute force power increase.

A new
redundancy compare circuit is proposed to eliminate this
delay penalty. The revised redundancy
path is shown in Fig. 2 with
the new compare circuit in Fig. 3.

Essentially
the latching function is duplicated in the compare
circuit so that the regular external address can be directly used for
compare purpose. The Fig. 3 circuit is
derived from the regular
address receiver latch, with identical resistors and current sources.
Thus voltage levels and timings in the redundancy path will be
totally compatible with those in the regular address path.

The signal
levels from the DC redundancy address are like the
regular lower cascode signal levels except for the higher up level.
The RT and RC signals uniquely determine which of the two current
switches are to be used to realize the compare...