1. Summary

Instead of using Modelsim's builtin GUI for compilation and simulation you can use a simulation script called wsrun.pl to simulate your verilog design. This script can be used only if your verification is done using a verilog test bench.

Add the following to your path variable: /u/k/a/karu/public/html/courses/cs552/spring2017/handouts/bins

Identify the verilog files that you want to test, lets call them foo0.v, foo1.v, and foo2.v.

Call your testbench foo_bench.v

Your testbench must be written so that it will stop automatically after running for some cycles by calling $finish .

The script will simulate your testbench and track the waveform output in a file called dump.vcd and dump.wlf. The text output of your testbench will be written to a file called transcript.

You must instantiate the clkrst.v module in your design if you want to use this script. If you are testing pure combinational logic, simply instantiate the clkrst module in your testbench as a dummy module.

If you use this script, you can simply edit your verilog using your favorite editor, and compile and simulate using the script, using Modelsim only as a waveform viewer.

You can now view a waveform of the simulation by issuing the following on the command-line:

prompt% vsim -view dataset=dump.wlf

You can now view all waveforms of all the signals in your design. The waveforms are saved to a file called dump.vcd and dump.wlf. In Model-sim, you will see a tab showing dataset. Click on the Edit menu and choose Wave. You can drag and drop modules into the waveform window to look at different signals as before.

If you make any changes to any of the verilog files, simply reissue the wsrun.pl command again:

prompt% wsrun.pl foo_bench foo_bench.v foo0.v foo1.v foo2.v

And re-open vsim.

You can specify wildcards like *.v to compile all the .v files.

wsrun.pl module_name *.v

3. Additional flags

3.1 -wave

wsrun.pl -wave

Will automatically start vsim with the waveform viewer after simulating your design.

Run the programs one after another on the processor. Results written to a file called summary.log.

3.4 -pipe

This option should be used for simulating a pipelined processor (For demo2 onwards).

3.5 -addr

wsrun.pl -addr <address trace filename> mem_system_perfbench *.v

This option is similar to -prog. It is used to specify an address trace to be used for HW5's mem_system_perfbench testbench. This option does not make sense for any other testbench.

3.6 -brief

Show less output on screen, record to wsrun.log

4. Simulating full programs on your processor

The script has a -prog switch using which you can specify a program to simulate on your processor. The script will automatically assemble it, copy over the loadfile and compile and simulate your processor and run that program by loading into memory.

5. Testing different sub-units of your design

Use the script to simulate and verify individual units rapidly, each with its own testbench as you build up your processor. This script gets rid of the need to create project files and using the GUI to compile and run the simulation. The script takes care of everything and we use ModelSim only as a waveform viewer for debugging.

You will find this script to be useful as we transition to more complex designs.