METHOD FOR FORMING A POLYSILICON THIN FILM LAYER - This invention provides a method for fabricating a polysilicon thin film layer, which performs a gas plasma treatment on channel regions defined in the polysilicon thin film layer after the polysilicon thin film layer is formed on a substrate. Threshold voltages for polysilicon thin film transistors formed subsequently are thus adjusted by the gas plasma treatment. A gate insulating layer is formed on the polysilicon thin film layer after the gas plasma treatment.

2009-05-21

20090127558

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device, and method for making the same, comprising a thin film transistor formed on a first insulating substrate, a pixel electrode electrically connected to the thin film transistor, an organic layer formed on the pixel electrode, a common electrode formed on the organic layer, a conductive layer formed on the common electrode, a transparent electrode layer formed on the conductive layer, the transparent electrode being applied with a common voltage, and a second insulating substrate located on the transparent electrode layer. Thus, the present invention provides a display device to which common voltage is applied effectively.

2009-05-21

20090127559

ORGANIC LUMINESCENT DISPLAY DEVICE HAVING A SEMICONDUCTOR WITH AN AMORPHOUS SILICON LAYER - A display device includes a plurality of light emitting elements arranged in a matrix. A scan signal is made to flow into a gate signal line and a data signal is made to flow into a source signal line so that the data signal is applied to a source electrode and the scan signal is supplied to a gate electrode of a control TFT arranged at a portion where the both signal lines intersect when viewed from above. Thus, when the control TFT is turned ON, a drive TFT having a gate electrode connected to the drain electrode is turned ON, so that current is supplied from a power supply line via the source electrode and the drain electrode of the drive TFT to an organic EL element and the organic EL element emits light. A holding capacity is present between the control TFT and the drive TFT. Even when the scan signal becomes LOW level and the control TFT turns OFF, the gate potential of the drive TFT is held for a predetermined period of time by the holding capacity and the organic EL element continues to emit light.

SEMICONDUCTOR DEVICE, DISPLAY DEVICE AND MOBILE DEVICE - A semiconductor device of the present invention includes an insulating substrate, a nonvolatile memory formed above the insulating substrate and having a memory holding portion, and at least one light-shielding body covering an upper side, an under side, or both sides of the memory holding portion, wherein at least one of the light-shielding bodies is installed in such a way that a protrusion degree of the light-shielding body, which is defined by (a length of the light-shielding body protruded from the memory holding portion)/(a distance between the light-shielding body and the memory holding portion), is 0.1 or more.

2009-05-21

20090127562

Semiconductor Device - To realize a semiconductor device including a capacitor element capable of obtaining a sufficient capacitor without reducing an opening ratio, in which a pixel electrode is flattened in order to control a defect in orientation of liquid crystal. A semiconductor device of the present invention includes a light-shielding film formed on the thin film transistor, a capacitor insulating film formed on the light-shielding film, a conductive layer formed on the capacitor insulating film, and a pixel electrode that is formed so as to be electrically connected to the conductive layer, in which a storage capacitor element comprises the light-shielding film, the capacitor insulating film, and the conductive layer, whereby an area of a region serving as the capacitor element can be increased.

2009-05-21

20090127563

THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF - According to an embodiment, the method of manufacturing a thin film transistor array panel includes forming a gate wire, a data wire, and a thin film transistor on a substrate and depositing an organic material layer on the gate wire, the data wire, and the thin film transistor. The method further includes forming an optical pattern on the upper surface of the organic material layer, depositing a reflecting electrode layer on the organic material layer, etching the reflecting electrode layer, etching the organic material layer after etching the reflecting electrode layer, and forming a pixel electrode on the reflecting electrode layer. Accordingly, the optical pattern on the upper surface of organic material may be transcribed to the reflecting electrode layer without damage and with clarity.

2009-05-21

20090127564

GaN Substrate Manufacturing Method, GaN Substrate, and Semiconductor Device - A GaN substrate manufacturing method characterized in including a step of processing the surface of a substrate composed of a GaN single crystal into a concavely spherical form, based on differences in orientation of the crystallographic axis across the substrate surface. Processing the GaN substrate surface into a concavely spherical form reduces, in the post-process GaN substrate surface, differences in orientation of the crystallographic axis with respect to a normal. Furthermore, employing to manufacture semiconductor devices a GaN substrate in which differences in orientation of the crystallographic axis have been reduced makes it possible to uniformize in device characteristics a plurality of semiconductor devices fabricated from a single GaN substrate, which contributes to improving yields in manufacturing the semiconductor devices.

2009-05-21

20090127565

P-n junctions on mosaic diamond substrates - The present invention provides methods of making and using semiconductive single crystal diamond bodies, including semiconductive diamond bodies made by such methods. In one aspect, a method of making a semiconductive single crystal diamond layer may include placing a plurality of diamond segments in close proximity under high pressure in association with a molten catalyst and a carbon source, where the diamond segments are arranged in a single crystal orientation. The plurality of diamond segments are then maintained under high pressure in the molten catalyst until the plurality of diamond segments have joined together with diamond to diamond bonds to form a substantially single crystal diamond body. Following creation of the single crystal diamond body, a homoepitaxial single crystal diamond layer may be deposited on the single crystal diamond body. A dopant may be introduced into the homoepitaxial single crystal diamond layer to form a semiconductive single crystal diamond layer.

LED CHIP THERMAL MANAGEMENT AND FABRICATION METHODS - The present invention relates to a method of fabricating a high power light-emitting device using an electrolessly or electrolytically plated metal composite heat dissipation substrate having a high thermal conductivity and a thermal expansion coefficient matching with the device.

SEMICONDUCTOR LIGHT EMITTING MODULE AND IMAGE READER USING THE SAME - A semiconductor light emitting module is provided with a supporting conductor including a die bonding pad, and with a plurality of semiconductor light emitting elements bonded to the die bonding pad. The semiconductor light emitting elements are arranged in series along an arrangement line extending in a first direction. The die bonding pad includes a portion overlapping alternative die-bonding positions which are symmetrical to positions of the bonded semiconductor light emitting elements with respect to a line of symmetry extending in a second direction different from the first direction.

2009-05-21

20090127570

Double Wavelength Semiconductor Light Emitting Device and Method of Manufacturing the Same - Provided are a double wavelength semiconductor light emitting device, having an n electrode and p electrode disposed on the same surface side, in which the area of a chip is reduced to increase the number of chips taken from one single wafer, in which light focusing performance of double wavelength optical beams are improved, and in which an active layer of a light emitting element having a longer wavelength can be prevented from deteriorating in a process of manufacturing; and a method of manufacturing the same.

2009-05-21

20090127571

METHOD FOR FABRICATING SEMICONDUCTOR LAYER AND LIGHT-EMITTING DIODE - A semiconductor layer containing defects only in a small density, possessing good quality and exhibiting a large ionic bonding property as to GaN, for example, is formed on a semiconductor layer, such as a silicon carbide layer, which is made of a material possessing a small ionicity and exhibiting a strong covalent bonding property. A method for forming a semiconductor layer includes forming on the surface of a first semiconductor layer

2009-05-21

20090127572

Nitride Semiconductor Light Emitting Device - There is provided a nitride semiconductor light emitting device capable of inhibiting output deterioration of light emission caused by quality deterioration of a nitride semiconductor layer due to lattice-mismatching between a substrate and the nitride semiconductor layer, and utilizing light traveling to the substrate efficiently, while forming a light emitting device of a vertical type which has one electrode on a back surface of the substrate by using the substrate made of SiC. A light reflecting layer (

Semiconductor Structure and Method of Manufacturing a Semiconductor Structure - A semiconductor structure is formed of nitrides of group III metals having wurtzite crystal structure and grown in vapor phase on a (0001) oriented semiconductor substrate. The structure comprises a bottom cladding layer, a top cladding layer, and a diffusion region positioned between the cladding layers for diffusing light propagating within the semiconductor structure. The diffuse region has refractive index different from those of the cladding layers and non-flat surfaces for providing light diffusing interfaces between the diffusion region and the cladding layers. According to the invention, the diffusion region comprises a plurality of diffusion layers, compositions and thicknesses of said diffusion layers having been chosen to avoid formation of strain-induced dislocations in the diffusion region, and adjacent diffusion layers having different refractive indices in order to further enhance the diffusion efficiency.

2009-05-21

20090127575

Light-Emitting Diode Chip With High Light Extraction And Method For Manufacturing The Same - This invention provides a light-emitting diode chip with high light extraction, which includes a substrate, an epitaxial-layer structure for generating light by electric-optical effect, a transparent reflective layer sandwiched between the substrate and the epitaxial-layer structure, and a pair of electrodes for providing power supply to the epitaxial-layer structure. A bottom surface and top surface of the epitaxial-layer structure are roughened to have a roughness not less than 100 nm root mean square (rms). The light generated by the epitaxial-layer structure is hence effectively extracted out. A transparent reflective layer not more than 5 μm rms is formed as an interface between the substrate and the epitaxial-layer structure. The light toward the substrate is more effectively reflected upward. The light extraction and brightness are thus enhanced. Methods for manufacturing the light-emitting diode chip of the present invention are also provided.

2009-05-21

20090127576

NANOCRYSTAL LIGHT-EMITTING DIODE - A nanocrystal light-emitting diode with improved structural stability is disclosed. Specifically, the nanocrystal light-emitting diode comprises an excitation source, a nanocrystal-containing light conversion layer and an air layer formed therebetween to be exposed to the outside.

Optoelectronic device - An optoelectronic device includes a base, a first and a second stands mounted on the base, a chip mounted on the first stand, a copper wire for bonding the chip to the second stand, and a molding compound mounted on the base. The molding compound encapsulates the first and the second stands, the chip, and the copper wire. The molding compound is made of epoxy resin.

2009-05-21

20090127580

LUMINESCENCE DIODE CHIP WITH CURRENT SPREADING LAYER AND METHOD FOR PRODUCING THE SAME - An LED chip is specified that comprises at least one current barrier. The current barrier is suitable for selectively preventing or reducing, by means of a reduced current density, the generation of radiation in a region laterally covered by the electrical connector body. The current spreading layer contains at least one TCO (Transparent Conductive Oxide). In a particularly preferred embodiment, at least one current barrier is contained which comprises material of the epitaxial semiconductor layer sequence, material of the current spreading layer and/or an interface between the semiconductor layer sequence and the current spreading layer. A method for producing an LED chip is also specified.

2009-05-21

20090127581

NITRIDE-BASED LIGHT-EMITTING DEVICE - A nitride-based light-emitting device includes a substrate and a plurality of layers formed over the substrate in the following sequence: a nitride-based buffer layer formed by nitrogen, a first group III element, and optionally, a second group III element, a first nitride-based semiconductor layer, a light-emitting layer, and a second nitride-based semiconductor layer.

2009-05-21

20090127582

Semiconductor apparatus including a radiator for diffusing the heat generated therein - A semiconductor apparatus is provided that includes a radiator for efficiently radiating heat generated in a wiring layer used in a surge current path of an electrostatic discharge protection circuit, and also for protecting the wiring layer itself used as the surge current path. The semiconductor apparatus includes an input protection circuit coupled to a wiring provided between an external terminal and an internal circuit, the input protection circuit includes a protection element for protecting the internal circuit from an excessive electrostatic surge input supplied to the external terminal. The semiconductor apparatus further includes a first metal wiring layer coupled to the input protection circuit and included in a current path for the surge electrostatic surge input, and a radiator including a sufficient thermal conductivity material coupled to the first metal wiring layer.

Transistor with a germanium-based channel encased by a gate electrode and method for producing one such transistor - Source and drain electrodes are each formed by an alternation of first and second layers made from a germanium and silicon compound. The first layers have a germanium concentration comprised between 0% and 10% and the second layers have a germanium concentration comprised between 10% and 50%. At least one channel connects two second layers respectively of the source electrode and drain electrode. The method comprises etching of source and drain zones, connected by a narrow zone, in a stack of layers. Then superficial thermal oxidation of said stack is performed so a to oxidize the silicon of the germanium and silicon compound having a germanium concentration comprised between 10% and 50% and to condense the germanium Ge. The oxidized silicon of the narrow zone is removed and a gate dielectric and a gate are deposited on the condensed germanium of the narrow zone.

2009-05-21

20090127585

Integration of an NPN device with phosphorus emitter and controlled emitter-base junction depth in a BiCMOS process - According to one exemplary embodiment, a heterojunction bipolar transistor includes a base situated on a substrate. The heterojunction bipolar transistor can be an NPN silicon-germanium heterojunction bipolar transistor, for example. The heterojunction bipolar transistor further includes a cap layer situated on the base, where the cap layer includes a barrier region. The barrier region can comprises carbon and has a thickness, where the thickness of the barrier region determines a depth of an emitter-junction of the heterojunction bipolar transistor. An increase in the thickness of the barrier region can cause a decrease in the depth of the emitter-base junction. According to this exemplary embodiment, the heterojunction bipolar transistor further includes an emitter situated over the cap layer, where the emitter comprises an emitter dopant, which can be phosphorus. A diffusion retardant in the barrier region of the cap layer impedes diffusion of the emitter dopant.

2009-05-21

20090127586

INTEGRATED CIRCUIT HAVING MEMORY CELLS AND METHOD OF MANUFACTURE - An integrated circuit having memory cells and a method of manufacture is disclosed. One embodiment provides a switching active volume and a selection transistor coupled in series between a first electrode and a second electrode. The selection transistor is a vertical transistor for at least partially guiding a substantially vertical current flow. The second electrode includes a buried diffused ground plate formed in a substrate. A metal-containing region at least partially contacting the buried diffused ground plate is provided, the metal-containing region at least extending below the selection transistor.

PATTERNING TECHNIQUES - A method of forming a patterned layer, including the steps of: (i) depositing via a liquid medium a first material onto a substrate to form a first body on said substrate; (ii) depositing via a liquid medium a second material onto said substrate to form a second body, wherein said first body is used to control said deposition of said second material so as to form a patterned structure including said first and second bodies; and (iii) using said patterned structure to control the removal of selected portions of a layer of material in a dry etching process or in a wet etching process using a bath of etchant.

2009-05-21

20090127589

Methods and apparatus for measuring analytes using large scale FET arrays - Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.

2009-05-21

20090127590

MICRO ELECTRO MECHANICAL DEVICE, METHOD FOR MANUFACTURING THE SAME, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SAME - A micro electro mechanical device includes: a semiconductor layer; a source/drain region formed on both sides of a channel region within the semiconductor layer; a gate insulating film formed on the semiconductor layer; a cavity formed on the gate insulating film; and a gate electrode formed on the cavity, the gate electrode being movable so as to contact with the gate insulating film. In the device, a pressure applied on the gate electrode is detected by a contact area of the gate electrode and the gate insulating film.

2009-05-21

20090127591

SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF - Manufacturing a semiconductor device with higher operating characteristics and achieve low power consumption of a semiconductor integrated circuit. A single crystal semiconductor layer is formed so that crystal plane directions of single crystal semiconductor layers which are used for channel regions of an n-channel TFT and a p-channel TFT and which are formed over the same plane of the substrate are the most appropriate crystal plane directions for each TFT. In accordance with such a structure, mobility of carrier flowing through a channel is increased and the semiconductor device with higher operating characteristics can be provided. Low voltage driving can be performed, and low power consumption can be achieved.

2009-05-21

20090127592

FIN-JFET - Methods, devices, and systems integrating Fin-JFETs and Fin-MOSFETs are provided. One method embodiment includes forming at least on Fin-MOSFET on a substrate and forming at least on Fin-JFET on the substrate.

2009-05-21

20090127593

MOS device - A semiconductor device includes a drain, an epitaxial layer overlaying the drain, a body disposed in the epitaxial layer, a source embedded in the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source, the active region contact trench having a varying contact trench depth, and an active region contact electrode disposed within the active region contact trench.

2009-05-21

20090127594

MOS TRANSISTORS HAVING NiPtSi CONTACT LAYERS AND METHODS FOR FABRICATING THE SAME - MOS transistors and methods for fabricating MOS transistors are provided. One exemplary method comprises providing a silicon substrate having an impurity-doped region disposed at a surface of the silicon substrate. A first layer is sputter-deposited onto the impurity-doped region using a first sputtering target comprising nickel and a first concentration of platinum. A second layer is sputter-deposited onto the first layer using a second sputtering target comprising nickel and a second concentration of platinum, wherein the second concentration of platinum is less than the first.

2009-05-21

20090127595

SEMICONDUCTOR STRUCTURE WITH FIELD SHIELD AND METHOD OF FORMING THE STRUCTURE - Disclosed is semiconductor structure that incorporates a field shield below a semiconductor device (e.g., a field effect transistor (FET) or a diode). The field shield is sandwiched between upper and lower isolation layers on a wafer. A local interconnect extends through the upper isolation layer and connects the field shield to a selected doped semiconductor region of the device (e.g., a source/drain region of a FET or a cathode or anode of a diode). Current that passes into the device, for example, during back-end of the line charging, is shunted by the local interconnect away from the upper isolation layer and down into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds from the field shield into the lower isolation layer and into the substrate below. This field shield further provides a protective barrier against any electric charge that becomes trapped within the lower isolation layer or substrate

Photodiode Structure - A photodiode structure including a semiconductor of a first conductivity type, the semiconductor having a main surface, a first well formed in the semiconductor at the main surface thereof, the first well being of a second conductivity type opposite to the first conductivity type. A second well formed in the semiconductor at the main surface thereof laterally outside the first well, the second well being of the second conductivity type, and a first terminal electrically connecting the first well and the second well, and a second terminal connecting the semiconductor such that a depletion region of laterally varying distance to the main surface results from applying a reverse voltage to the first and second terminals.

2009-05-21

20090127598

IMAGE SENSOR AND METHOD OF FABRICATING THE SAME - An image sensor includes a semiconductor substrate, a photodiode formed in the semiconductor substrate, a first impurity region formed in the semiconductor substrate spaced from the photodiode, a second impurity region formed in the semiconductor substrate spaced from the first impurity region, a first gate formed over the semiconductor substrate between the photodiode and the first impurity region, a second gate formed over the semiconductor substrate between the first impurity region and the second impurity region, a spacer formed over the fourth impurity region and a first sidewall of the second gate, and an insulating film formed over the photodiode, the first gate, the first impurity region and a second sidewall and a portion of the uppermost surface of the second gate.

2009-05-21

20090127599

Image Sensor and Method of Manufacturing the Same - Provided is an image sensor. The image sensor includes a semiconductor substrate, an interlayer dielectric, metal interconnections, a first electrode, a lower electrode, a second electrode, and a photodiode. The semiconductor substrate has at least one transistor thereon. The interlayer dielectric is on the semiconductor substrate. The metal interconnections pass through the interlayer dielectric. The first electrode is in the interlayer dielectric between the metal interconnections. The lower electrode is on the interlayer dielectric to connect to the metal interconnection. The second electrode is on the interlayer dielectric at a position corresponding to the first electrode, and a gap region is between the second electrode and the lower electrode. The photodiode is on the interlayer dielectric with the lower electrode and the second electrode.

2009-05-21

20090127600

IMAGE SENSOR AND FABRICATING METHOD THEREOF - An image sensor and fabricating method thereof are disclosed by which damage to a protective layer can be prevented in a manner of reducing thermal stress of an uppermost metal line in performing thermal treatment for enhancing the dark characteristic. Such damage can be prevented by forming a poly layer pattern in an insulating interlayer on at least one side of the uppermost layer metal line.

2009-05-21

20090127601

Image Sensor and Method for Manufacturing the Same - An image sensor may include a device isolating layer and a photodiode on a substrate; a first dielectric layer on the photodiode; a first micro lens on the first dielectric layer; a second dielectric layer on the first micro lens; a color filter on the second dielectric layer; and a second micro lens on the color filter.

2009-05-21

20090127602

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - This disclosure concerns a memory including transistors provided on a substrate; ferroelectric capacitors provided on the transistors, the ferroelectric capacitors respectively including a ferroelectric film provided between a lower electrode and an upper electrode; and a barrier film covering a first side surface of the ferroelectric capacitor, and blocking passing of hydrogen, wherein adjacent two of the ferroelectric capacitors connected in the lower electrode form one capacitor unit, a plurality of the capacitor units connected in the upper electrode form one capacitor chain, the capacitor units are arranged with a deviation of a half pitch of the capacitor unit in adjacent plurality of capacitor chains, and when D

2009-05-21

20090127603

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device according to an embodiment comprises: a field-effect transistor formed on a substrate; an interlayer insulation film formed on the substrate on which the field-effect transistor is formed; and a ferroelectric capacitor including a lower electrode connected via a plug to one of source/drain regions of the field-effect transistor, and formed on the interlayer insulation film, a ferroelectric film having a perovskite crystal structure used as a basic structure, and an upper electrode, wherein a lattice matching region in which a lattice of the ferroelectric film is matched with a lattice of the lower electrode is formed in a range of a predetermined thickness of the ferroelectric film from the lower electrode.

2009-05-21

20090127604

FERROELECTRIC MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - A ferroelectric memory device includes: a substrate; a ferroelectric capacitor forming above the substrate, and having a lower electrode layer, a ferroelectric layer and an upper electrode layer; a first hydrogen barrier layer that covers the ferroelectric capacitor; an interlayer dielectric layer formed above the first hydrogen barrier layer; and a contact section that penetrates the interlayer dielectric layer and the first hydrogen barrier layer and connects to the upper electrode layer, wherein the contact section includes a first barrier layer in contact with the upper electrode layer, a second hydrogen barrier layer formed above the first barrier layer and a plug layer formed above the second hydrogen barrier layer.

2009-05-21

20090127605

Semiconductor device and method for manufacturing the same - A semiconductor device includes: n transistor elements; n resistive elements; and n capacitive elements, each kind of elements coupled in series between the first and second terminals. The gate of each transistor element has a gate pad, and each transistor element includes transistor pads disposed on both sides. Each resistive element includes resistive pads disposed on both sides. Each capacitive element includes capacitive pads disposed on both sides. The gate pad other than the first stage transistor element, a corresponding resistive pad, and a corresponding capacitive pad are electrically coupled. One transistor pad, one resistive pad, and one capacitive pad in the first stage are electrically coupled. One transistor pad, one resistive pad, and one capacitive pad in the n-th stage are electrically coupled.

2009-05-21

20090127606

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A driving circuit and a bus to transmit an output signal from the driving circuit are provided. The driving circuit includes a first P-channel transistor, a second P-channel transistor, an N-channel transistor and a capacitor. The first P-channel transistor includes a drain, a source to connect with a higher potential and a gate to receive a first input signal. The second P-channel transistor includes a drain connected to the bus, a source connected to the drain of the first P-channel transistor and a gate to receive a second input signal. The N-channel transistor includes a drain connected to the drain of the second P-channel transistor, a source to connect with a lower potential and a gate to receive the second input signal. The capacitor includes one end connected to the drain of the first P-channel transistor and another end to connect with the lower potential.

2009-05-21

20090127607

SEMICONDUCTOR DEVICE INCLUDING A TCAM HAVING A STORAGE ELEMENT FORMED WITH A DRAM - In order to improve the discharging speed of potential from a match line, a semiconductor device includes a capacitor, a memory transistor having a source/drain region connected to a storage node of the capacitor, a search transistor having a gate electrode connected to the storage node, and a stacked contact connecting a match line and the source/drain region of the search transistor. The storage node has a configuration in which a sidewall of the storage node facing the match line partially recedes away from the stacked contact such that a portion of the sidewall in front of the stacked contact in plan view along the direction of the match line is located farther away from the stacked contact than the remaining portion of the sidewall.

2009-05-21

20090127608

INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT - An integrated circuit including a memory cell array is shown. The memory cell array comprises word lines extending in a first direction and bit lines extending in a second direction intersecting the first direction and memory cells. The memory cells may include storage elements, bit line contacts for coupling a corresponding memory cell to a corresponding bit line. The bit line contacts are arranged in a checkerboard pattern with respect to the first direction, and the storage elements are arranged in a regular grid along the first and second directions, respectively.

2009-05-21

20090127609

Method of fabricating recess channel transistor having locally thick dielectrics and related devices - Provided are a method of fabricating a recess channel transistor and a related semiconductor device. The method may include forming a first gate trench on a substrate, forming a dielectric spacer on a sidewall of the first gate trench, forming a second gate trench on the substrate under the first gate trench, and forming a gate electrode to fill the trenches. The dielectric spacer may remain between the gate electrode and the substrate.

2009-05-21

20090127610

NON-VOLATILE MEMORY AND THE MANUFACTURING METHOD THEREOF - A non-volatile memory disposed on a substrate includes active regions, a memory array, and contacts. The active regions defined by isolation structures disposed in the substrate are extended in a first direction. The memory array is disposed on the substrate and includes memory cell columns, control gate lines and select gate lines. Each of the memory cell columns includes memory cells connected to one another in series and a source/drain region disposed in the substrate outside the memory cells. The contacts are disposed on the substrate at a side of the memory array and arranged along a second direction. The second direction crosses over the first direction. Each of the contacts extends across the isolation structures and connects the source/drain regions in the substrate at every two of the adjacent active regions.

2009-05-21

20090127611

NON-VOLATILE MEMORY DEVICE AND MEMORY CARD AND SYSTEM INCLUDING THE SAME - A non-volatile memory device includes a semiconductor layer including source and drain regions and a channel region between the source and drain regions; a tunneling insulating layer on the channel region of the semiconductor layer; a charge storage layer on the tunneling insulating layer; a blocking insulating layer on the charge storage layer and including a first oxide layer with a first thickness, a high-k dielectric layer, and a second oxide layer with a second thickness different from the first thickness that are stacked sequentially on the charge storage layer; and a control gate on the blocking insulating layer.

2009-05-21

20090127612

SEMICONDUCTOR DEVICE HAVING A GATE STRUCTURE - A gate structure in a semiconductor device includes a dielectric layer pattern on a substrate, a floating gate on the dielectric layer pattern, a gate mask on the floating gate, a tunnel insulation layer on the substrate, and a word line on the tunnel insulation layer. The dielectric layer pattern includes a first portion and a second portion having a thickness different from a thickness of the first portion. The floating gate includes a step and tips. The tunnel insulation layer makes contact with a sidewall of the floating gate. The word line extends on a portion of the gate mask.

2009-05-21

20090127613

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device comprises a memory cell array of plural memory cells arranged in matrix. Each memory cell includes a first gate insulator layer formed on a semiconductor substrate, a floating gate formed on the semiconductor substrate with the first gate insulator layer interposed therebetween, a second gate insulator layer formed on the floating gate, and a control gate formed on the floating gate with the second gate insulator layer interposed therebetween. The first gate insulator layer is a first cavity layer.

POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A vertical power semiconductor device includes a first semiconductor layer of a first conductivity type formed in both a cell section and a termination section, the termination section surrounding the cell section, a second semiconductor layer of a second conductivity type formed on the first semiconductor layer in the cell section, a third semiconductor layer of the first conductivity type formed in part on the second semiconductor layer, and a guard ring layer of the second conductivity type formed on the first semiconductor layer in the termination section. Net impurity concentration in the guard ring layer is generally sloped so as to be relatively high on its lower side and relatively low on its upper side. Alternatively, the net impurity concentration in the guard ring layer is constant.

2009-05-21

20090127617

Trench mosfet and manufacturing method thereof - This invention relates to a trench MOSFET, which can lower parasitic capacitance, thereby increasing a switching speed, and to a method of manufacturing the trench MOSFET. The trench MOSFET includes a substrate having an epi layer and a body layer sequentially formed thereon, a trench formed vertically in the central portion of the epi layer and the body layer, a first gate oxide film formed on the inner wall of the trench, a diffusion oxide film formed in the epi layer between the lower surface of the trench and the upper surface of the substrate to have a thickness greater than a thickness of the first gate oxide film and a width greater than a width of the trench, a gate formed in the trench having the first gate oxide film, a second gate oxide film formed on the gate, and a source region formed at both sides of the upper portion may be of the gate, thus reducing the generation of parasitic capacitance between the epi layer corresponding to a drain region and the gate, thereby improving a switching speed.

2009-05-21

20090127618

MULTI-FIN FIELD EFFECT TRANSISTOR - A multi-fin field effect transistor includes a substrate, an oxide layer, a conductive layer, a gate oxide layer, and a doped region. The substrate is surrounded by a trench, and there are at least two fin-type silicon layers formed in the substrate in a region prepared to form a gate thereon. The oxide layer is disposed in the trench and the top surface of the oxide layer is lower than that of the fin-type silicon layers. The conductive layer is disposed in the region prepared to form a gate. The top surface of the conductive layer is higher than that of the fin-type silicon layers. The gate oxide layer is disposed between the conductive layer and the fin-type silicon layers and disposed between the conductive layer and the substrate. The doped region is disposed in the substrate on both sides of the conductive layer.

2009-05-21

20090127619

DEEP TRENCH SEMICONDUCTOR STRUCTURE AND METHOD - An electrical structure and method of forming. The electrical structure includes a semiconductor substrate comprising a deep trench, an oxide liner layer is formed over an exterior surface of the deep trench, and a field effect transistor (FET) formed within the semiconductor substrate. The first FET includes a source structure, a drain structure, and a gate structure. The gate structure includes a gate contact connected to a polysilicon fill structure. The polysilicon fill structure is formed over the oxide liner layer and within the deep trench. The polysilicon fill structure is configured to flow current laterally across the polysilicon fill structure such that the current will flow parallel to a top surface of the semiconductor substrate.

2009-05-21

20090127620

SEMICONDUCTOR DOPING WITH REDUCED GATE EDGE DIODE LEAKAGE - Semiconductor doping techniques, along with related methods and structures, are disclosed that produce components having a more tightly controlled source and drain extension region dopant profiles without significantly inducing gate edge diode leakage. The technique follows the discovery that carbon, which may be used as a diffusion suppressant for dopants such as boron, may produce a gate edge diode leakage if present in significant quantities in the source and drain extension regions. As an alternative to placing carbon in the source and drain extension regions, carbon may be placed in the source and drain regions, and the thermal anneal used to activate the dopant may be relied upon to diffuse a small concentration of the carbon into the source and drain extension regions, thereby suppressing dopant diffusion in these regions without significantly inducing gate edge diode leakage. The increased concentration of carbon in the source and drain regions may permit heavier doping of the source/drain region, leading to improved gate capacitance.

2009-05-21

20090127621

ZERO CAPACITOR RAM WITH RELIABLE DRAIN VOLTAGE APPLICATION AND METHOD FOR MANUFACTURING THE SAME - The following discloses and describes a zero capacitor RAM as well as a method for manufacturing the same. The zero capacitor RAM includes an SOI substrate. This SOI substrate is composed of a stacked structure of a silicon substrate, an embedded insulation film and a silicon layer. This layer is patterned into line types to constitute active patterns. Moreover, a first insulation layer forms between the active patterns and gates form on the active patterns as well as the first insulation layer to extend perpendicularly to the active patterns. In addition, a source forms in the active pattern on one side of each gate, a drain forms in the active pattern on the other side of each gate which is achieved by filling a metal layer. Continuing, a contact plug forms between the gates on the source and an interlayer dielectric forms on the contact plug in addition to the gates Finally, a bit line forms on the interlayer dielectric to extend perpendicularly to the gates and come into contact with the drain.

2009-05-21

20090127622

TRANSPARENT THIN-FILM TRANSISTOR AND MANUFACTURING METHOD OF THE TRANSISTOR - A transparent thin-film transistor and a method of manufacturing the same includes a substrate composed of a transparent material, and a gate electrode, a gate dielectric layer, an activation layer, and source and drain electrodes, at least one of each being composed of an amorphous oxide material.

2009-05-21

20090127623

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In a semiconductor device, a gate electrode, an impurity diffused region, a body potential fixing region, a first insulator, and a dummy gate electrode are provided on top of an SOI substrate consisting of an underlying silicon substrate, a buried insulator, and a semiconductor layer. The impurity diffused region is a region formed by implanting an impurity of a first conductivity type into the semiconductor layer around the gate electrode. The body potential fixing region is a region provided in the direction of an extension line of the length of the gate electrode and implanted with an impurity of a second conductivity type. The first insulator is formed at least in the portion between the body potential fixing region and the gate electrode. The dummy gate electrode is provided on the first insulator between the body potential fixing region and the gate electrode.

2009-05-21

20090127624

Semiconductor device having soi substrate and method for manufacturing the same - A semiconductor device includes: a SOI substrate including a support layer, a first insulation film and a SOI layer; a first circuit; a second circuit; and a trench separation element. The SOI substrate further includes a first region and a second region. The first region has the support layer, the first insulation film and the SOI layer, which are stacked in this order, and the second region has only the support layer. The trench separation element penetrates the support layer, the first insulation film and the SOI layer. The trench separation element separates the first region and the second region. The first circuit is disposed in the SOI layer of the first region. The second circuit is disposed in the support layer of the second region.

2009-05-21

20090127625

SEMICONDUCTOR DEVICE - A semiconductor device according to one embodiment includes: a substrate; a plurality of fins made of a semiconductor and formed on the substrate; a plurality of via contact regions formed between the fins, the plurality of via contact regions and the plurality of the fins constituting a closed loop structure; a gate contact region on the substrate arranged at a position surrounded by the closed loop structure; a plurality of gate electrodes connected to the gate contact region respectively, each of the plurality of gate electrodes sandwiching both side faces of each of the plurality of fins between its opposite regions via gate insulating film; and source/drain regions formed in regions in the plurality of fins and in the contact region, the regions being formed on both sides of a region sandwiched by the gate electrodes along longitudinal direction of the fin.

2009-05-21

20090127626

STRESS-GENERATING SHALLOW TRENCH ISOLATION STRUCTURE HAVING DUAL COMPOSITION - A shallow trench isolation structure containing a first shallow trench isolation portion comprising the first shallow trench material and a second shallow trench isolation portion comprising the second shallow trench material is provided. A first biaxial stress on at least one first active area and a second bidirectional stress on at least one second active area are manipulated separately to enhance charge carrier mobility in middle portions of the at least one first and second active areas by selection of the first and second shallow trench materials as well as adjusting the type of the shallow trench isolation material that each portion of the at least one first active area and the at least one second active area laterally abut.

2009-05-21

20090127627

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device capable of improving the driving power and a manufacturing method therefor are provided. In a semiconductor device, a gate structure formed by successively stacking a gate oxide film and a silicon layer is arranged over a semiconductor substrate. An oxide film is arranged long the lateral side of the gate structure and another oxide film is arranged along the lateral side of the oxide film and the upper surface of the substrate. In the side wall oxide film comprising these oxide films, the minimum value of the thickness of the first layer along the lateral side of the gate structure is less than the thickness of the second layer along the upper surface of the substrate.

SEMICONDUCTOR DEVICE HAVING ELEMENT ISOLATION REGION AND METHOD FOR MANUFACTURE THEREOF - An n-type buried diffusion layer is formed on the surface layer of the prescribed area of a p-type silicon substrate, and a p-type first high-concentration isolation diffusion layer is formed in the silicon substrate so as to surround the buried diffusion layer. An n-type epitaxial layer is formed on the silicon substrate, the buried diffusion layer, and the first high-concentration isolation diffusion layer. A p-type second high-concentration isolation diffusion layer is formed in the epitaxial layer on the first high-concentration isolation diffusion layer. A p-type low-concentration isolation diffusion layer for isolating the epitaxial layer into a plurality of island regions is formed in the epitaxial layer on the second high-concentration isolation diffusion layer.

2009-05-21

20090127632

Semiconductor Device Manufactured by Removing Sidewalls During Replacement Gate Integration Scheme - One aspect of the invention provides a semiconductor device that includes gate electrodes comprising a metal or metal alloy located over a semiconductor substrate, wherein the gate electrodes are free of spacer sidewalls. The device further includes source/drains having source/drain extensions associated therewith, located in the semiconductor substrate and adjacent each of the gate electrodes. A first pre-metal dielectric layer is located on the sidewalls of the gate electrodes and over the source/drains, and a second pre-metal dielectric layer is located on the first pre-metal dielectric layer. Contact plugs extend through the first and second pre-metal dielectric layers.

2009-05-21

20090127633

NON-VOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME - In one embodiment, a semiconductor memory device includes a substrate having first and second active regions. The first active region includes a first source and drain regions and the second active region includes a second source and drain regions. A first interlayer dielectric is located over the substrate. A first conductive structure extends through the first interlayer dielectric. A first bit line is on the first interlayer dielectric. A second interlayer dielectric is on the first interlayer dielectric. A contact hole extends through the second and first interlayer dielectrics. The device includes a second conductive structure within the contact hole and extending through the first and second interlayer dielectrics. A second bit line is on the second interlayer dielectric. A width of the contact hole at a bottom of the second interlayer dielectric is less than or substantially equal to a width at a top of the second interlayer dielectric.

2009-05-21

20090127634

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate having an active region, a plurality of gate electrodes formed on the active region with a gate insulating film therebetween, and a dummy pattern formed on the active region in at least a part thereof between the gate electrodes. The dummy pattern is formed so that a spacing between gate electrodes adjacent to each other, and a spacing between the dummy pattern and the gate electrodes adjacent to the dummy pattern, are within predetermined ranges.

2009-05-21

20090127635

Transistor including an active region and methods for fabricating the same - A transistor including an active region and methods thereof. The active region may include corners with at least one of a rectangular, curved or rounded shape. The methods may include isotropically etching at least a portion of the active region such that the portion includes a desired shape.

2009-05-21

20090127636

Diffusion Variability Control and Transistor Device Sizing Using Threshold Voltage Implant - A transistor is defined to include a substrate portion and a diffusion region defined in the substrate portion so as to provide an operable transistor threshold voltage. An implant region is defined within a portion of the diffusion region so as to transform the operable transistor threshold voltage of the diffusion region portion into an inoperably high transistor threshold voltage. A gate electrode is defined to extend over both the diffusion region and the implant region. A first portion of the gate electrode defined over the diffusion region forms a first transistor segment having the operable transistor threshold voltage. A second portion of the gate electrode defined over the implant region forms a second transistor segment having the inoperably high transistor threshold voltage. Therefore, a boundary of the implant region defines a boundary of the operable first transistor segment.

2009-05-21

20090127637

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The HVIC includes a dielectric layer and an SOI active layer stacked on a silicon substrate, a transistor formed in the surface of the SOI active layer, and a trench isolation region formed around the transistor. The dielectric layer includes a first buried oxide film formed in the surface of the silicon substrate, a shield layer formed below the first buried oxide film opposite the element area, a second buried oxide film formed around the shield layer, and a third buried oxide film formed below the shield layer and the second buried oxide film. Therefore, the potential distribution curves PC within the dielectric layer are low in density and a high withstand voltage is achieved.

2009-05-21

20090127638

ELECTRICAL DEVICE AND METHOD - An electrical device and method is disclosed. One embodiment provides a substrate, a sensor chip disposed completely above a plane section of a surface of the substrate. A structurally homogeneous material layer is disposed above the substrate and the sensor chip. A cavity is formed between the substrate and the material layer. The sensor chip is disposed inside the cavity.

2009-05-21

20090127639

SEMICONDUCTOR APPARATUS - A semiconductor apparatus includes: a first chip including a MEMS device which has a structure supported in midair therein, and having first pads and a first joining region electrically connected to the MEMS device on a top face thereof; a second chip including a circuit having a semiconductor device electrically connected to the MEMS device therein, and having second pads and a second joining region electrically connected to the semiconductor device on a top face thereof, the second chip being disposed in opposition to the first chip so as to oppose the second pads and the second joining region respectively to the first pads and the first joining region; electrical connection parts which electrically connect the first pads to the second pads, respectively; and joining parts provided between the first joining region and the second joining region opposed to the first joining region to join the first chip and the second chip to each other.

2009-05-21

20090127640

METHOD FOR MANUFACTURING A SEMICONDUCTOR COMPONENT, AS WELL AS A SEMICONDUCTOR COMPONENT, IN PARTICULAR A MEMBRANE SENSOR - A manufacturing method for a micromechanical semiconductor element includes providing on a semiconductor substrate a patterned stabilizing element having at least one opening. The opening is arranged such that it allows access to a first region in the semiconductor substrate, the first region having a first doping. Furthermore, a selective removal of at least a portion of the semiconductor material having the first doping out of the first region of the semiconductor substrate is provided. In addition, a membrane is produced above the first region using a first epitaxy layer applied on the stabilizing element. In a further method step, at least a portion of the first region is used to produce a cavity underneath the stabilizing element. In this manner, the present invention provides for the production of the patterned stabilizing element by means of a second epitaxy layer, which is applied on the semiconductor substrate.

2009-05-21

20090127641

SEMICONDUCTOR DEVICE - The invention provides a semiconductor device that power is stabilized by suppressing power consumption as much as possible. The semiconductor device of the invention includes a logic portion and a memory portion each including a plurality of transistors, a detecting portion for detecting one or both of operation frequencies of the logic portion and the memory portion, a Vth control for supplying a Vth control signal to one or both of the logic portion and the memory portion, and an antenna. Each of the plurality of transistors has a first gate electrode which is input with a logic signal, a second gate electrode which is input with the Vth control signal, and a semiconductor film such that the second gate electrode, the semiconductor film, and the first gate electrode are provided in this order from the bottom.

PHOTODIODE OF AN IMAGE SENSOR AND FABRICATING METHOD THEREOF - A method for fabricating a photodiode of an image sensor includes providing a substrate having a first conductive type and photo sensing regions, respectively forming photodiodes in the photo sensing region, and performing an ion implantation to form an implanted reflective layer having a second conductive type under the plurality of photodiodes for reflecting light and creating depletion regions in the substrate.

2009-05-21

20090127644

Semiconductor device comprising an image sensor, apparatus comprising such a semiconductor device and method of manufacturing such a semiconductor device - The invention relates to a semiconductor device comprising a semiconductor body in which an image sensor is formed and having a semiconductor body surface with an optically active part of the image sensor and a non-optically active part of the image sensor in which electrical connection areas of the image sensor are located, a spacer structure being present on the semiconductor body surface in the non-optically active part of the image sensor and an optical passive component being positioned on top of the spacer structure and above the image sensor and allowing radiation to impinge on the optically active part of the image sensor.

2009-05-21

20090127645

In-line light sensor - The sensor includes an optical waveguide defined in a light-transmitting medium. The waveguide includes a sensing portion and an non-sensing portion. The light-transmitting medium included in the sensing portion has defects that provide the light-transmitting medium with a deep band gap level between a valence band of the light-transmitting medium and a conduction band of the light-transmitting medium. The deep band gap level is configured such that the waveguide guiding light signals through the light-transmitting medium in the sensing portion causes free carriers to be generated in the light-transmitting medium. A detector is configured to detect the free carriers in the sensing region of the waveguide.

2009-05-21

20090127646

IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - An image sensor and a manufacturing method thereof are provided. The image sensor can include a semiconductor substrate having a photodiode, an interlayer dielectric layer on the semiconductor substrate, and an upper insulating layer on the interlayer dielectric layer. A trench can be provided in the upper insulating layer and the interlayer dielectric layer over the photodiode, and the trench can have a curved sidewall. A lens color filter can be disposed in the trench.

2009-05-21

20090127647

SEMICONDUCTOR DEVICE, SOLID-STATE IMAGING DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate; an insulating layer; and a wiring layer that is a high-concentration impurity layer, in this order, wherein the semiconductor device further includes a contact portion that electrically connects the semiconductor substrate with the wiring layer, the contact portion is provided to pass through the wiring layer and the insulating layer to be brought into contact with a surface of the semiconductor substrate, and the contact portion has an impurity concentration lower than that in a connection region of the semiconductor substrate being in contact with the contact portion.

2009-05-21

20090127648

Hybrid Gap-fill Approach for STI Formation - A method of forming a shallow trench isolation region is provided. The method includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; performing a first deposition step to fill a first dielectric material into the opening using a first deposition method. The first deposition method has a bottom deposition rate substantially greater than a sidewall deposition rate. The method further includes isotropically etching the first dielectric material, wherein at least a bottom portion of the first dielectric material remains after the etching; and performing a second deposition step to fill a remaining portion of the opening with a second dielectric material. The first deposition method may be a high-density plasma chemical vapor deposition. The second deposition method may be a high-aspect ratio process.

2009-05-21

20090127649

Semiconductor device and method for fabricating the same - According to the present invention, a semiconductor device includes a semiconductor layer; a device-isolation region formed in the semiconductor layer; an active region surrounded by the device isolation region; and a gap, formed at boundary between the device isolation region and the active region. The gap is not formed under the active region. The gap is formed on a side wall portion of the active region, which extends in a depth direction.

2009-05-21

20090127650

TRENCH ISOLATION STRUCTURE IN A SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A trench isolation structure in a semiconductor device is provided. A semiconductor substrate has cell regions and peripheral circuit regions. First trenches have a predetermined depth and are formed in the semiconductor substrate at the cell regions. A first sidewall oxide film is formed overlying the first trenches. A first liner nitride film is formed overlying the first sidewall oxide film. Second trenches have a predetermined depth and are formed in the semiconductor substrate at the peripheral circuit regions. A second sidewall oxide film is formed overlying the second trenches. An oxide film fills the first overlying second trenches. A second liner nitride film formed on the filling oxide film. The second liner nitride film is separated from the sidewalls of the first and second trenches.

2009-05-21

20090127651

ROBUST SHALLOW TRENCH ISOLATION STRUCTURES AND A METHOD FOR FORMING SHALLOW TRENCH ISOLATION STRUCTURES - In a semiconductor substrate, a shallow trench isolation structure having a dielectric material disposed in voids of a trench-fill material and a method for forming the shallow trench isolation structure. The voids may be formed during a wet clean process after the dielectric material is formed in the trench. A conformal silicon nitride layer is formed over the substrate and in the voids. After removal of the silicon nitride layer, the voids are at least partially filled by the silicon nitride material.

2009-05-21

20090127652

STRUCTURE OF VERY HIGH INSERTION LOSS OF THE SUBSTRATE NOISE DECOUPLING - A structure includes a substrate comprising a region having a circuit or device which is sensitive to electrical noise. Additionally, the structure includes a first isolation structure extending through an entire thickness of the substrate and surrounding the region and a second isolation structure extending through the entire thickness of the substrate and surrounding the region.

2009-05-21

20090127653

PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a phase-change random access memory device includes forming an interlayer insulating film on a semiconductor substrate, on which a bottom structure is formed, and patterning the interlayer insulating film to form a contact hole, forming a spacer on the side wall of the contact hole; forming a dielectric layer in the contact hole, and removing the spacer to form a bottom electrode contact hole. Therefore, the contact area between the bottom electrode contact and the phase-change material layer can be minimized.

2009-05-21

20090127654

Fully Differential, High Q, On-Chip, Impedance Matching Section - An inductor circuit is disclosed. The inductor circuit includes a first in-silicon inductor and a second in-silicon inductor each having multiple turns. A portion of the multiple turns of the second in-silicon inductor is formed between turns of the first in-silicon inductor. The first and second in-silicon inductors are configured such that a differential current flowing through the first in-silicon inductor and the second in-silicon inductor flows in a same direction in corresponding turns of inductors.

2009-05-21

20090127655

CAPACITOR FOR SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A capacitor for the semiconductor device may include a bottom electrode formed over a semiconductor substrate, a dielectric film pattern formed over the bottom electrode, an insulating member formed over a peripheral portion of the top surface of the dielectric film pattern, and a top electrode formed over the insulating member and dielectric film pattern. Capacitor properties are improved and capacitor values are maintained as constant by reducing a parasitic capacitance generated from edges of a capacitor electrode. Therefore, embodiments make it possible to improve semiconductor device properties and yields.

2009-05-21

20090127656

Dielectric relaxation memory - A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the invention to be used as a memory device. A method of forming the trap cites involves an atomic layer deposition of a material at pre-determined areas in the dielectric layer.