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Introduction to System Modeling with Tensilica Processor Cores

Course Description

This 1-day training session teaches the basics of creating, configuring, and debugging a system model using the Xtensa® SystemC library. We describe components in the XTSC example component library, which model key components in a SoC, like cores, memories, interconnects, DMA, and others. We discuss system control, data movement, and synchronization mechanisms, like DMA transfer, GPIO interrupts, and spinlocks. We show how to model a system using those mechanisms. The 4 labs cover the different topics of system modeling using xtsc-run. We show how to build a dual core system model of a control processor controlling a data processor. This is an essential class for an engineer building system simulation models using Tensilica processor cores.

Learning Objectives

After completing this course, you will be able to:

Build a system model using the Xtensa SystemC library

Gain familiarity with the library of example components provided along with your Tensilica core and use them to build your system simulation model

Debug common problems encountered when building a system model

Software Used in This Course

Xtensa Software Tools Release RF-2015.2

Software Release(s)

RF-2015.2

Modules in this Course

Introduction

Overview of XTSC

When System Modeling is required

Single Core Modeling ( Part 1 and Part 2 )

System Setup, Configuration, Debug

Find Tensilica Core Configurations

Lab 1 – Running and Debugging a Single Core System Using XTSC-Run

System Modeling ( Part 1 and Part 2 )

The Memory Map

System Boot-Up

Logging and Debugging

Lab 2 – Adding and Configuring an XTSC Component to a System Model to Drive, Reset, and Boot a System from Reset

Multi-Core System Analysis ( Part 1 and Part 2 )

XTSC Component Library

System Control and Synchronization Mechanisms (Hardware)

System Control and Synchronization Mechanisms (Software)

Lab 3 – Implementing, Simulating, and Debugging a Dual Core System with a Control Processor, a Data Processor, and a DMA Engine

Multi-Core Debugging and Profiling

Lab 4 – Finding a Memory Map Problem in a Dual Core System Using Xplorer and oTransaction Traces

TurboXim

Fast System Simulation Using TurboXim

Audience

Engineers building or working with SystemC based simulation models of Tensilica processor cores