Artisan DDR PHY Solutions

ARM® DDR Interface IP delivers a comprehensive timing solution for a broad range memory sub-systems ranging from high-speed mission critical applications to low-power memory sub-systems. These robust silicon-proven interfaces have been optimized to provide the highest bandwidth at the lowest power and area.

ARM Artisan DDR PHY Key Benefits

Ensures the highest bandwidth, lowest latency and lowest power configuration without sacrificing flexibility in implementation

Provides a Time To Market advantage leveraging mature architecture and silicon proven technology

Lowest risk solutions with a long history of high volume production backed by an experienced support team.

The ARM DDR memory interface IP offers a comprehensive solution for a broad range of application from LPDDR to DDR3. Targeting data rates from 100Mbps up to 1.6 Gb/s data rates, the ARM DDR Interface IP offers the best Power/Performance solution for SoC and ensure robust operation in various packaging and system configurations. The PHY comprises of all analog and digital block required to build the DDR interface. ARM reduces your design risk and ensures seamless integration between blocks and rest of the system.

The DDR interface comes designed to cope with wide range of voltage, temperature, process, package and system variations while ensuring robust signaling between the SoC and off-chip memories. It includes on-die compensation circuitry and supply decoupling to increase power supply noise immunity and reduce jitter.

The ARM DDR interface IP is no stranger to Low Power, deployment of low power operation goes from SoC level all the way down to individual circuit level. Various low power techniques, combined with traffic aware interface, can yield in a significant reduction to the DDR interface power.

Performance

Compliant to JEDEC Standards (DDR, DDR2, LPDDR, DDR3)

Operating speed up to 1.6Gbps

Tight skew specs & Minimum propagation delays

Area optimized to reduce chip size

Robust ESD structures 2000V HBM and 200V MM

Specifications

Multiple Standard support LPDDR, LPDDR2, DDR2 and DDR3

Seamless interoperability between IP

Adjustable slew rates & drive strengths

Low latency with programmable timings

Robust ESD enabling full speed designs

PVT compensation and timing calibration

At speed testability

Low jitter with superior noise rejection

ARM DDR PHY and I/O Interface IP may be used in complex SoC designs which require many types of IP across the design. In addition to DDR PHY and I/O IP, ARM offers a wide variety of compatible Processor to Pads IP including ARM Processor, Multimedia, System and Physical IP, with which to develop your SoC.

You may view ARM DDR and other Physical IP products in DesignStart. Registered users of DesignStart can download Front-End Packages for all products that enable a comprehensive IP evaluation including place and route. DesignStart also includes access to technical documentation, including Datasheets and Application Notes.