SVN Files

- src: containing the verilog sources files {qadd.v,qmult.v,qdiv.v,qtwosComp.v}. These are the parameterized verilog modules implementing the fixed point arithmetic

- testfixtures: containing the three testfixtures for each of the arithmetic operations (add,mult,div). These testfixtures show how data is being entered into the data structure from real life (giving understanding to the user in how to implement in their own projects).

- implementation: containing a sample 'top' module that implements the arithmetic operations in a Q23/32bit scenario