Intel Details 3D XPoint Memory, Future Products

At this year's Intel Developer Forum, the company disclosed additional technical details about its forthcoming 3D XPoint memory, which has the potential to really change PC architecture by filling the gap between traditional main memory and storage.

At this year's Intel Developer Forum, the company disclosed additional technical details about its forthcoming 3D XPoint memory, which has the potential to really change PC architecture by filling the gap between traditional main memory and storage.

Intel and Micron, which together created the new memory and plan to produce it at a joint venture facility in Lehi, Utah, have said that 3D XPoint is 1,000 times faster than NAND flash and 10 times the density of DRAM. As such, it could be a faster alternative to today's NAND flash memory, which has a lot of capacity and is relatively inexpensive, or work as a replacement or adjunct to traditional DRAM, which is faster but has limited capacity. At IDF, we got more details on how it might work in either of those solutions.

During the keynote, Rob Crooke, senior vice president and general manager of Intel's Non-Volatile Memory Solutions Group, announced that Intel plans to sell data center and notebook SSDs as well as DIMMs based on the new memory in 2016 under the Optane brand name. He demonstrated an Optane SSD providing five to seven times the performance of Intel's current fastest SSD running a variety of tasks.

Later on, he and Al Fazio, an Intel senior fellow and director of memory technology development, presented a lot of the technical details—though they are still keeping some important information under wraps, such as the actual material used for writing the data.

In that session, Crooke held up a wafer that he said contained the 3D XPoint memory, which will include 128 Gbits of storage per die. In total, they said the full wafer could hold 5 Terabytes of data.

Fazio stood next to a model of the memory, which he said was 5 million times the actual size. He used this model, which only showed storing 32 bits of memory, to explain how the structure works.

He said it had a pretty simple cross point structure. In this arrangement, the perpendicular wires (sometimes called word lines) connect submicroscopic columns, and an individual memory cell can be addressed by selecting its top and bottom wire. He noted that in other technologies, the ones and zeros are indicated by trapping electrons—in a capacitor for DRAM and in a "floating gate" for NAN. But with the new solution, the memory (indicated in green in the model) is a material that changes its bulk properties—meaning you have hundreds of thousands or millions of atoms moving between high and low resistivity indicating ones and zeros. The issue, he said, has been in creating the materials for memory storage and for the selector (indicated in yellow in the model) which enables the memory cells to be written to or read without requiring a transistor.

He wouldn't say what the materials were, but did say that while it has the basic concept of materials that change between high and low resistance to indicate ones and zeros, it was different from what most in the industry consider resistive RAM, as that often uses filaments and cells of around 10 atoms, while XPoint uses bulk properties so that all the atoms change, which makes it easier to manufacture.

Fazio said this concept is very scalable, in that you could add more layers or scale the manufacturing to smaller dimensions. The current 128 Gbit chips use two layers and are manufactured at 20nm. In a question-and-answer session, he noted that the technology for creating and connecting the layers is not the same as for 3D NAND and requires multiple layers of lithography, so costs may rise proportionally as you add layers after a certain point. But he said it was probably economical to create 4-layer or 8-layer chips, and Crooke joked that in three years, he'll be saying 16 layers. He also said it was technically possible to create multi-level cells—such as the MLCs used in NAND flash—but it took a long time to do that with NAND and isn't likely to happen soon because of manufacturing margins.

In general, Fazio said we could expect the memory capacity to increase on a cadence similar to NAND, doubling every couple of years, approaching Moore's Law-style improvements.

In 2016, Intel will sell Optane SSDs manufactured with the new technology in standard 2.5-inch (U.2) and the mobile M.2 (22mm by 30 mm) form factors, Crooke said. This would be useful in applications such as enabling immersive gaming with large open worlds, which require large data sets.

While the initial demonstration showed an improvement of five to seven times on a standard storage box, Fazio said that was limited by the other things around that storage buss. He said you could "unleash" the potential by taking it off the storage bus and putting it directly on a memory bus, which is why Intel plans to also release next year a version using the NVMe (non-volatile memory express) standard on top of PCIe. Many vendors are now offering NAND flash over the PCI bus, and they said XPoint performance would be significantly better there.

Another use might be to use this memory directly as system memory. Using the next-generation Xeon processor—not yet announced, but mentioned in a number of sessions—you should be able to use XPoint directly as memory allowing four times the current maximum memory of DRAM at a lower cost. 3D XPoint is somewhat slower than DRAM, but they said the latency is measured in double-digit nanoseconds, which is pretty close to DRAM and hundreds of times faster than NAND. (Note that NAND read speeds are much faster than its write speeds, and that NAND addresses memory in pages, while DRAM and XPoint address the memory at an individual bit level.)

Intel will be offering the memory in DDR4-capable DIMM slots next year as well, Crooke said, while a diagram indicated it will be used in conjunction with DRAM, with the traditional memory acting as a write-back cache. They said this can work with no changes to the operating system or application.

Crooke talked about the potential use of this memory in applications such as financial services, fraud detection, online advertising, and scientific research such as computational genomics—as it is particularly good for dealing with large data sets, offering fast random data access. But he said it would also be great for immersive, uninterrupted gaming.

There are still a lot of open questions, as the product hasn't been delivered, so we don't know actual pricing, specifications, or particular models yet. He did make it clear that Intel intends to sell the memory only as part of specific modules, not as raw memory components. (Micron, which will also be selling products based on the material, hasn't yet made any announcements about specific products.)

Assuming the price turns out to be reasonable and that the technology continues to advance, I can see a huge use for a technology that fits in between DRAM and NAND. It's highly unlikely to replace either—DRAM should remain faster and 3D NAND likely will stay cheaper for quite some time  but it could become a very important part of systems architecture going forward.

Michael J. Miller's Forward Thinking Blog: forwardthinking.pcmag.com
Michael J. Miller is chief information officer at Ziff Brothers Investments, a private investment firm. From 1991 to 2005, Miller was editor-in-chief of PC Magazine, responsible for the editorial direction, quality and presentation of the world's largest computer publication.
Until late 2006, Miller was the Chief Content Officer for Ziff Davis Media, responsible for overseeing the editorial positions of Ziff Davis's magazines, websites, and events. As Editorial Director for Ziff Davis Publishing since 1997, Miller took an active role in...
More »