>
> The above code should really look like this:
>
> mfmsr r7
> ori r7,r7,MSR_EE
> oris r7,r7,MSR_POW@h
> sync
> isync
> mtmsr r7
> isync
> label:
> b label
> blr
Ohhh ... we always assumed mtmsr with MSR_POW was
immediate/synchronous ! That explains a lot. The problem with the above
though is that we'll never get out unless we also hack the exception
path to change the return address once an exception happens. It's not
that difficult especially since we already have a special case to handle
returning from NAP there, on ppc32 at least. ppc64 will need a bit more
investigation.
Do you see another way to loop until NAP has gone ? Maybe reading msr in
a loop until POW gets cleared would do the trick ?
> Hope this helps - I don't have hardware to test this on, so I can't
> be sure, but it seems to explain the behavior you're seeing if I'm
> understanding the problem correctly.
It definitely does ! Thanks a lot.
Ben.