An Introduction To Interrupts P2

Describe the problems associated with the timing of interrupts with respect to.

Software Events

The problem with interrupts is that their occurrence cannot be predicted. They could occur at any time. Critical code portions should be protected by disabling
interrupts for their duration. A typical example is accessing shared data.The use of interrupts can affect the timing of existing coded routines. This effect
is unpredictable, due to the nature of interrupts. Code which is heavily timing dependent may not work when interrupts are enabled. These timing critical portions need to be protected also.

The processing of interrupts should be kept as short as possible, with reguard to the duration of the software event in question.

Multiple interrupts from the same source

Because all devices use the same interrupt line, and can assert it at any time, it is possible for a device not to be recognized. Status ports, daisy chaining and the use of PIC chips overcome these problems. Interrupts can be missed, especially if they are edge triggered or non-latched. Level sensitive interrupts need to be kept low till acknowledged by the processor.The interrupts must be arranged in priority. This can be done using either software (polling order) or hardware (use a PIC). It might be that higher priority interrupts keep occurring, preventing a lower level interrupt from being serviced.

Decisions need to be made whether interrupt routines can also be nested. This could mean servicing a high priority interrupt which allows a lower priority interrupt inside it.

Other interrupts

Most processors support two levels of interrupts, maskable and non-maskable. Inherently, the processor assigns each a priority. Separate input lines are used by
the processor for each, eg, NMI and IRQ.The use of a daisy chain or PIC system ensures correct timing with respect to other interrupt sources. It overcomes the problems of multiple interrupts occurring and their associated priorities.

The programmer must decide, for each interrupt in the system, which must be

maskable

its priority level

whether it can be nested

how many interrupts can be active

Some processors with limited stack space could
experience problems with a large number of nested
interrupts.

State the problems of working with multiple interrupts with respect to.

Timing as above

The issues involved are,

response times

priorities

number and frequency

The purpose of interrupt routines are to ensure adequate response times to requests for service. Problems may occur if a lower level interrupt routine will not allow a higher level interrupt to interrupt it. The designer works out worst case scenarios for all interrupts in the system, which will highlight any potential problems. Ensuring that higher priority interrupts can interrupt a lower level routine is important in situations like power-down.

To keep the interrupt routines short, a buffered or message approach might be adopted. This ensures the device is serviced quickly, but that interrupt routines do not consume excessive amounts of processor time.

Priority of interrupts

Where interrupts such as NMI are used for watchdog and powerdown cases, they must have absolute priority.Interrupt priority is determined by

the task to be done

the data transfer rate

expected response times

hardware requirements

This might mean that an interrupt driven printer spooler would have lower priority than an interrupt routine which services a floppy disk unit. Conversely, the highest priority in the system could be refreshing the Dynamic RAM.

Identification of interrupting device and its appropriate service routine

Where more than one interrupt device is connected to the same interrupt line, some method of device determination must be employed.The three main methods are,

status ports

hardware vector

PIC

Status ports are suitable for systems which are not very critical and the priority may need to be changed dynamically. Hardware vector systems are very fast at servicing interrupts, thus are used where response times are critical.

PIC systems combine the features of both the status and hardware vector systems, and are used in complicated systems with a large number of interrupt sources, some of which may need to be periodically disabled/enabled.

TIMING DEVICES

State the different timing devices available, and give examples where each is most appropriately used, eg,

Timing devices and methods are used in computer systems for

timing

event logging

file stamping

task synchronization

implementing controlled delays

measurements

Software methods

These involve the calculation of the time period using software.
The advantage is no/little hardware and easy programming, at the expense of accuracy.

Hardware methods

These involve the use of support chips like a Real Time Clock (RTC), timer/counter chips and interrupts. They have greater accuracy and resolution at the expense of interrupt routines and extra hardware.

Software Loops

These are implemented by loading a register with a value, then decrementing and looping till the register value reaches zero, eg.

DELAY: Mov CX, FFFFh
DELAY1: Dec CX
Jne DELAY1
Ret

It is generally used to implement small delays, examples being

20ms for keyboard debouncing

head settle times for floppy disk controllers

serial communications, eg. RTS to CTS delays

and where variances in iteration speed are not critical (accuracy is not important).

Longer delays are achieved by using another register to provide multiple calls, eg.

Mov BX, 5
Lp1: CALL DELAY
Dec BX
Jne Lp1

The processor is tied up for the duration of the software loop.

Modern processors using high clock rates can buzz through a 16bit timing loop very quickly.

though it will actually perform faster due to the instruction queue cache.

Advantages

no additional hardware required

simple to implement

takes up little memory space

Disadvantages

inaccurate

suitable for small delays only

ties up the processor

RTC in hardware

A peripheral chip, driven by the system clock, is used for timing purposes. It has registers which are programmed with specific time intervals. Each system clock decrements this value at a pre-determined rate (divide by 1,2,4,8,16 etc). When the register count reaches zero, the RTC chip generates an interrupt to the processor.

Most chips provide several channels which can either be used separately, or cascaded together for longer time intervals.

Other chips available are DATE/TIME calendar chips, which are used to implement time of day features for the computer operating system.

Real-time hardware implementations are suitable for

time-slicing in multi-user systems

counting pulses

pulse width or frequency determination

time intervals for A/D and D/A conversions (sample and hold)

accurate delays

watchdog timers

Advantages

the processor can perform other tasks

greater accuracy

several counters available

greater flexibility

wider range available

better resolution

Disadvantages

extra hardware required

software overheads required

requires initialization code

RTC in software

In this system, a periodic interrupt is used to implement timing features, either loop counts or time of day calendar functions.

The frequency of the interrupt determines the resolution and accuracy of the clock. On each interrupt the service routine might be,

In a multi-user system, the operating system controls delays which may be imposed upon tasks for any number of reasons.

task suspension

block/wakeup protocol

task synchronization

Tasks may also voluntarily request suspension. Each suspended task is inserted into a sleep queue, which is driven by a real-time clock. The entry for each task corresponds to the number of timer ticks before the task is to be rewaken.

If the timer tick is every 100microseconds, and taskA requests a sleep period of 400milliseconds, then the queue looks like,

taskA = 4000

If another task, taskB then requests a sleep period of 800 milliseconds, the queue looks like,

taskA = 4000
taskB = 4000

Once the time has expired, the operating system removes the task from the sleep queue.

The following code example illustrates a simple implementation for tasks to sleep under the control of the RTE.

This technique involves using the CPU to detect when the device is ready to present data to it. In our case, it involves continually reading the RBF flag of the Line Status Register for the serial port.

When RBF is asserted, the CPU can then read the character from the receive buffer register of the serial card. The following program shows a C program which performs software polling of the serial port to receive characters from a transmitter station.

This technique involves using the I/O device to tell the CPU when it is ready to present data. This frees the CPU for other tasks during this time, and also guarantees adequate response times. In our case, it involves enabling interrupt driven operation for the receive section of the serial port.

When a character arrives, the serial port will issue an interrupt request to the computers Priority Interrupt Controller chip (PIC). The PIC will interrupt the CPU and place the vector of the receive routine onto the data bus. The CPU uses this vector as an entry into a lookup table which then generates the address of the routine servicing that interrupt.

The receive interrupt routine reads the character stored in the RBR and deposits it into a circular queue buffer. Once the interrupt is serviced, the PIC must be reset to enable further interrupts to take place.

The 8259 Priority Interrupt Controller

This chip is reponsible for prioritizing interrupts from various I/O devices and passing them onto the CPU for servicing. When a device requests service, it asserts its associated interrupt line (IRQ0 to IRQ7), signalling the PIC. The PIC asserts IRQ to the processor which responds with INTA (Interrupt Acknowledge). Upon receiving this, the PIC presents a vector byte on the data bus which the CPU uses to determine the address of the interrupt service routine.

At port 0x21 is the PIC MASK REGISTER. Each bit in the mask register corresponds to an IRQ line. IRQ0 is associated with bit 0 and so on. Writing a ZERO to a selected bit enables the interrupt line for that particular bit.

When the PC is reset or powered on, all interrupt devices are disabled by writing 0x0f to the PIC mask register. The ROM BIOS/DOS routines enable IRQ0, IRQ1, IRQ6 and IRQ7 as part of the system initialisation.

The serial card on the PC uses IRQ4. Enabling bit 4 of the PIC mask register will thus also enable the reception of interrupts from the serial card.

To prevent destroying the current state of the mask register,
it is first read then bit 4 is enabled. The new mask setting is
then written back to the mask register.

Enabling of interrupt operation on the serial card

The Interrupt Enable register (IER) must be programmed for
receive interrupt generation. This is achieved by the statement

outportb( IER, 1 );

The PC serial card also has a little bit which needs to be set
in order to allow interrupts to be passed onto the PIC. This bit
must be set, and is done by the statement

outportb( MCR, 0x0b );
/* bit 0 = DTR, bit 1 = RTS, bit 3 = out2 */

Setting the interrupt vector to the receive interrupt
routine

This must be done before enabling the PIC controller, otherwise
it might cause the system to accept interrupts and branch to a
non-existent service routine.

The code which installs the interrupt service routine is,

setvect( 0x0c, recieve );

This places the segment:offset address of the service routine
into the interrupt vector for interrupt 0x0c. This is the vector
which the PIC chip presents when a device asserts IRQ4.

Enabling of the PIC to recognize the serial card

The PIC controller can provide masking of the various IRQ lines
coming from I/O cards. The PC serial card normally uses IRQ4 for
COM1. This interrupt must be programmed for acceptance by the
PIC.