How to ged rid of the Negative Slack

Hi, I'm Jose and I'm a bit new in the area of Timing Analysis.I have the next situation. I am with a design but I have a problem of timing (Negative Slack) in the circuit I've tried to solve the problem adding D-flip-flop between the modules which the problem was reported with in the Timing Summary. The thing is that I added the registers but the negative slack doesn´t dissapear completely (though it was reduced considerately) instead remain in other places.

The remaining endpoints with problems are 4, as show the Fig.1 and Fig.2

Fig.1. Number of failing endpoints:4.

Fig.2. Paths with timing.

The thing is that when I select the schematic of the first failed endpoint as shown in Fig.3 I notice something strange. First, it is supposed that the module register5 (a D-FlipFlop) and the module intCounterAndConcatADC share a data bus of 4 bits, and I don´t know why appears 30:0. Second, the dataToFIFO[92] and count_reg[4] appear within register5 but really belong to the module intCounterAndConcatADC, why?

last, How can I get rid of that negative slack? I probed to add another register after register5 but the timing negative slack got increased.

Re: How to ged rid of the Negative Slack

@rshekhaw rshekhaw , the method you say implies that I have to do it every time I implement that project? for example if I join it to another bigger project I need to do the same? is there a permanent solution?

@hongh , what are the directives you are saying? in the same way, does it implies that I have to do it every time I implement that project?

Re: How to ged rid of the Negative Slack

@hongh thank you for tell me what the common directives are and to specify the User Guide that is related with these about.

@rshekhaw , your commands worked deleting the timing problem. what more do you recommend to make the solution permanent?

@peterk the frequency is 500 MHz. What is a Register application? to segment the circuit? I don´t know where to see the CLB utilization you are talking about. I searched but I didn't find some ilustrating proccess to do it. How do I see it?

Re: How to ged rid of the Negative Slack

500 MHz is pretty fast. Since using explore directive works, I would just keep using that.

Register replication is duplicating registers when fanout is greater than the set amount (the default maybe 10,000). You can do this manually in your code or set it in the synthesis options. Becareful setting the option since this applies to the whole design. I think the latest Vivado allows synthesis strategy apply to block level.