Does anyone know what the normal fallout rate is for a 12 layer PCB from the board house during testing? We received the inspection data from a recent set of boards. Looking over the report there failure rate looks high to us, but with out knowing what the normal fallout rate is it is hard to tell.

The layer count itself isn't going to be what drives yields. What is the trace/space? How much annular ring for vias did you give them to play with? Class 2 or class 3? What's the worst hole aspect ratio? Controlled impedance? The closer you run to your board House's process limits the worse their yields will be.