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Abstract

Metal lines for VLSI interconnects are generally fabricated by etching metal from unmasked portions of the wafer. For fine lines, reactive ion etching (RIE) is preferred over wet etching because there is better control of the lateral etch rate. However, RIE can damage regions underneath the metal that is removed. This is especially important for local interconnects, where the metal lines are in direct contact with the substrate.

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United States

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English (United States)

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Interconnect Fabrication by Local Metal Oxidation

Metal lines
for VLSI interconnects are generally
fabricated by etching metal from unmasked portions of the wafer. For
fine lines, reactive ion etching (RIE) is preferred over wet etching
because there is better control of the lateral etch rate. However,
RIE can damage regions underneath the metal that is removed. This is
especially important for local interconnects, where the metal lines
are in direct contact with the substrate.

This article
proposes a new method for patterning metal lines.
For metals that form a stable, high resistivity oxide, patterning can
be achieved by oxidizing unmasked regions of the metal to form an
insulator. The masked regions remain
conductive and serve as the
metal lines. A possible local
interconnect process for an FET is
shown in the figures, using Ti as the metal layer and Si3N4 as the
mask. After gate and source/drain
fabrication, layers of Ti (50 nm)
and Si3N4 (100 nm) are deposited. The
Si3N4 is patterned using
lithography and RIE (Fig. 1); then, the Ti in the unmasked regions
over the field oxide is converted to TiO2 by annealing in oxygen at
600~C (Fig. 2). (Note that
stoichiometric TiO2 is a good insulator,
with a resistivity of 108 ohm-cm [1].) The unmasked Ti over the
source, drain, and gate regions is converted to a bilayer of TiO2 and
TiSi2 [2] (Fig. 3).

One advantage
of this patterning method compared to RIE is that
there should be no...