Engineers who are familiar with simulation, but new to formal property verification (FPV), often approach formal with a lot of questions, such as: How do I build a formal testbench? What does a formal property look like? How do I constrain a design for formal analysis? What’s the process of finding a design bug? Does formal verification provide any coverage metrics to measure completeness? Is it even possible to sign-off the verification of a block with formal?

In this webinar, jointly presented by Synopsys and Oski Technology, we will answer these questions and more. Using a multicast crossbar network-on-chip (NOC) design as a case study, we will introduce you to the phases of the FPV flow from planning to implementation to closure. Join us to learn about some of the features of Synopsys VC Formal that enable you to get started with this flow.

Speakers:

Roger Sabbagh, VP of Applications Engineering, Oski Technology

Leveraging over 25 years of semiconductor and EDA industry experience, Roger Sabbagh works with silicon design teams to find opportunities to deploy formal verification solutions that accelerate verification and close gaps. Most recently, he previously served as senior principal engineer at Huawei Technologies, where he led the formal verification team.

Dhruv Gupta, Formal Verification Engineer, Oski Technology

Dhruv Gupta is a formal verification specialist with experience in verifying a wide range of designs including processors such as GPUs and CPUs and peripherals such as USB and cache controllers. Dhruv has a Bachelor of Technology degree from the Indian Institute of Technology, Delhi.

Xiaolin Chen, Corporate Applications Engineer, Synopsys

Xiaolin Chen has been working at Synopsys for 15 years on application of formal technology in verification, working with customers to explore opportunities where formal technology can be best suited to solve verification problems. She provides guidance, training, and assistance to customers as well as Synopsys field and design teams in developing formal verification environment.