Intel® FPGA V-by-One Solution

Overview of V-by-One Solution

Intel® and Design Solutions Network (DSN) member Bitec provide the building blocks and complete reference designs to implement a FPGA-based V-by-One HS solution for displays requiring next-generation high-definition (HD), full HD (F-HD), or 4K2K connectivity. This includes digital television (DTV) flat-panel displays and PC monitors. The solution combines the V-by-One HS IP core and FPGA development hardware to provide design engineers:

Simple and fast V-by-One HS implementation

Reduced design risks

Shortened development times

Selected Intel FPGA families include embedded transceiver I/Os to support the physical layers of the V-by-One HS protocol. The IP core includes all the logic functionality and, when combined with the users' custom design, allows a complete design to be implemented in a single low-cost FPGA. Additional value-added video processing algorithms can easily be added into the remaining FPGA resources. Table 1 gives an overview of the complete V-by-One HS solution for Intel FPGA devices.

Technology Background

The bandwidth requirements of next-generation displays are rapidly out-growing existing internal board-to-board interconnect solutions, such as LVDS. V-by-One HS was developed to enable transmission of large amounts of video and control data. Depending on the bit width required for the color and control, V-by-One HS provides up to 32 lanes, at up to 3.75 Gbps. Panel OEMs also benefit from the following:

Lower cost cables/connectors

Lower energy consumption

Lower EMI

High transmission quality even with noisy conditions

This protocol is being adopted by tier one display manufacturers to replace LVDS-based solutions within their high-end display products. Figure 1 illustrates an example design using low-cost Cyclone IV GX FPGAs.

Figure 1. V-by-One HS IP Implemented in Low-Cost FPGAs

Protocol Standard

The V-by-One HS protocol is an open standard developed by THine Electronics, Inc. to support the higher frame rates and the higher resolutions required by next-generation flat-panel displays. It uses a proprietary encoding scheme along with a clock data recovery- (CDR-) based serializer/deserializer (SERDES) technology.

Protocol transmission includes up to 40-bits video data, up to 24-bit control data, HSYNC, VSYNC, and data enable (DE). The number of data lanes (1 - 32) is determined by the refresh rate (60 Hz --> 240 Hz) and color depth (18/24/30/36 bits). Each data lane is an AC-coupled differential transmission line using the CML I/O standard. The training link monitors signals between the transmitter and receiver to ensure the transceiver I/Os are locked and trained before data transmission begins.