Abstract: Due to the complexity associated with design verification,
testing costs for high performance processors are spinning out of control.
The verification effort grows exponentially as design complexity grows linearly.
It is commonplace for a processor design to contain over 100 million gates today.
Considering that a one million gate design requires 5-8 verification engineers,
the task of verification is dominating project costs. Server farms of thousands of
machines are needed to run design verification tests around the clock.

Five years ago design verification consumed 50% of the total effort expended on
a chip design. Today this percentage has grown to over 80% and is likely to further
dominate costs in the near future. All this opens up new frontiers of challenges
in verifying the complex processor architectures of today with all the practical
constraints that are placed on the verification team. This tutorial will describe
the current state-of-the-art in design verification and suggest some directions
that could lead to reducing this burden.

About the presenter:

Sunil Kakkar has over 20 years of experience in Processor Design, Architecture,
Performance and Functional Verification and has successfully led large design
verification and performance analysis teams that have ended up handing off fully
functional first silicon to the manufacturing and the test teams. Holding a Bachelor's
degree from IIT-Kanpur and two Master's degrees from the University Of Illinois,
Sunil holds a patent for a specialized microprocessor verification flow technique
that he invented at Sony and which led to bug free first silicon. Sunil has also
taught at the University of Berkeley program for industry professionals. Sunil has
also invented a VDL (Verification Design Language) which when used to specify a
digital design at a higher level of abstraction can be used to generate testbenches
automatically in any HDL or high level language. Sunil was invited to chair the
IEEE Computer Society Conference session on Verification. Sunil has worked for
companies like Hewlett Packard and Transmeta and is currently managing the
Processor Architecture, Performance and Verification Groups at IBM Global Services
in Bangalore. He is the chief technologist for the IBM's e-verification technology
initiative in the Asia-Pacific region.

Abstract: The need for power efficiency is becoming a limiting factor in processor design.
Continuing growth in complexity, frequency, and speculative execution outstrip
the benefits of technology scaling and voltage reduction. As static (leakage)
power dissipation becomes one of the major contributors to total power dissipation,
continued innovation in power-aware design only becomes more important.
Energy, thermal, and voltage-stability concerns mean that power-aware design is
needed not only for low-cost and mobile systems but even for high-performance
systems.

This tutorial covers three major topics. First, we differentiate among design for
energy efficiency/battery life, thermal regulation, and voltage stability.
The focus of this tutorial is on energy efficiency. Second, we review the
important mechanisms of dynamic and static power dissipation, how they can be
modeled, and relevant metrics for energy efficiency. Third, we review a broad
set of circuit and architectural techniques for reducing both dynamic and static power.
This tutorial is especially recommended to those who want to update
their knowledge of the major issues in power-aware design and review the
latest techniques from academia and the industry for achievingenergy-efficient
processor designs.

About the presenters:

José (Pepe) González received his Ms.D and PhD. in
Computer Science by the Universitat Politecnica de Catalunya, Spain in 1996 and 2000
respectively. In January 2000 he joined the Computer Engineering
Department of the University of Murcia, Spain, where he became
Associate Professor in June 2001. In March 2002, he moved to the Intel
Barcelona Research Center, at the Intel Labs in Barcelona, where he is a
Staff Research Scientist. His current research interest include high-performance
low-power architectures and clustered simultaneous multithreaded microprocessors.

Kevin Skadron is an Assistant Professor of Computer Science at the
University of Virginia. He received his PhD in Computer Science from Princeton
University, and bachelors' degrees in Electrical and Computer Engineering and
also Economics from Rice University. At U.Va., he directs the Laboratory for
Computer Architecture at Virginia (LAVA), which studies power and thermal issues,
branch prediction, and techniques for fast and accurate microprocessor simulation.
Skadron's research group recently released "HotSpot", a tool for dynamically modeling
localized on-chip temperatures in conjunction with architecture simulations;
"HotLeakage", a tool for dynamically modeling leakage energy in memory-like
structures, and "MRRL"; a tool for calculating the minimum warmup period needed
to avoid cold-start bias in sampled simulation. Skadron will be program
co-chair of the 2006 International Conference on Parallel Architectures and
Compilation Techniques (PACT), is general co-chair for the 2004 International
Symposium on Microarchitecture (MICRO), was general co-chair for PACT-2002,
and helped to launch Computer Architecture Letters, a new short-format,
refereed journal published by the IEEE Computer Society TCCA.

Abstract: This tutorial is intended to provide researchers interested in
embedded computing with a brief introduction to the field and to current research
problems. Embedded computers perform a wide variety of high-performance computing
tasks: control, communications, multimedia, etc. These applications are typically
performed on high-performance heterogeneous multiprocessors executing optimized
software. The applications must generally be performed in real time and often must
consume very small amounts of energy. The combination of high performance and
tight constraints makes for a challenging design environment.

The tutorial will start with a review of the typical requirements on embedded
computing: performance, power, cost, etc. We will then survey several embedded
computing system in different domains: automotive, video, telcom, and printing.
These examples will help to motivate various problems in embedded computing.
We will then move onto a survey of research in embedded computing with emphasis on
problems of interest to computer architects: hardware/software co-design; custom
memory systems; program performance analysis; power analysis and modeling;
and simulation.

About the presenter:

Wayne Wolf is professor of electrical engineering and affiliated faculty
in computer science at Princeton University. Before joining Princeton, he was with
AT&T Bell Laboratories, Murray Hill, New Jersey. He received the B.S., M.S., and
Ph.D. degrees in electrical engineering from Stanford University in 1980, 1981,
and 1984, respectively. He has published over 250 papers on embedded computing,
VLSI systems, computer-aided design, and multimedia information systems. He was
program chair of the first International Conference on Hardware/Software Co-Design,
program/general chair of ICCD, and is a co-chair of the MPSOC Workshop.
He is founding editor-in-chief of ACM Transactions on Embedded Computing Systems.
He is the author of Computers as Components and Modern VLSI Design (for which he
won the ASEE/CSE and HP Frederick E. Terman Award). Wolf has been elected to Phi
Beta Kappa and Tau Beta Pi. He is a Fellow of the IEEE and ACM and a member of
the SPIE and ASEE.