Basicaly you need to run the pwm output thru a diodeand resistor in series
into a parallel RC combination. The voltage on the cap depends on how long
the diode conducts and the value of the series R and the C i.e the pulse
width. Choose the parallel RC time constant to ensure low ripple at PWM
frequency. Note this type of DtoA has an asymetrical slew rate i.e it can
increase the output voltage a lot faster than it can decrease it. Ok for
relatively slow changing output values.

I don't know why you'd want the diode. A precision switch from 0V to
Vref (you can use a CMOS output and Vdd for Vref if accuracy
requirements are slack) and a low-pass DC-accurate filter. Boffins
like using Sallen-Key filters and such like. Personally, I prefer a 2
or 3-pole RC filter and unity-gain buffer. For higher accuracy, a CMOS
gate or buffer powered from Vref can be used (if Vref is different
from Vdd you may need voltage translation).

Best regards,
Spehro Pefhany

--
"it's the network..." "The Journey is the reward"
snipped-for-privacy@interlog.com Info for manufacturers: http://www.trexon.com

No you don't (need such). However the filter characteristics and
gain needed are much different if you don't first stretch the
input pulse, which is best done as a ramp when doing such a sample
and hold. The great advantage of pure impulse inputs is that you
can mix several sources ahead of the single filter. This was the
basis of a telephone system I built 30 years ago, where that
mixing was essential, and took place with no volume or frequency
degradation.

The sample and hold technique has the advantage that you need not
really deal with frequencies above the repetition rate. The
impulse system has much higher frequency components, and is
mathematically tractable.

This AtoD works by varying the the PWM pulse width so stretching it is
definitely not what you want to do. This design is different from the low
pass filter one others have mentioned which assumes a symetric source
impedance which is not the case for 8051 outputs. This design works as a
charge pump so the diode *is* necessary.

That is why the 'ramp', which runs up the value during the PWM
pulse duration, and the result is sampled and held for the next
sample. The problem is to reset it for the next ramp. The
impulse design avoids all this.

The one that you were originally trying to implement with a diode
and resistor, but neglected to reset for the next sample. That is
why a simple system is better implemented by simply low pass
filtering the impulses from the pwm output. Gain is cheap.

OK, I understand. However I do not see how the low pass filter can possibly
work. For a mark space of less than 50% the capacitor must be completely
discharged at the end of each cyle so there cannot be any dc output.

PWM -> DAC is essentially an average process.
Just connect a DC multimeter to the PWM port, and see what its
low pass filter gives.
The CAP is for DC averaging, it does not discharge each cycle.

Using a diode seems a little redundant - it does not improve the
Port impedance in either direction, and only adds more uncertainty.

Impedance is relative, so you can choose a higher R value in the RC,
to minimise the effects in very low cost designs, or you can use
pullups, or resistive dividers, which lower the output swing, and
also lower the output impedance (should that be important), or
a buffer if higher precision is your goal.

We did a 14 bit low speed DAC using two 8 bit PWMs and mixing
resistors, with good CMOS buffers.

Some 80C51 variants have LOW IMPEDANCE modes in PWM operation, so
are designed for lower value R's in the RC LPF, and others use rate
multiplier LSBs for higher freq output, and faster response times, but
still with the simple RC LPF.

The better PWMs allow you to select the bits of resolution, so
a design can trade off settling time / step size, if needed.
Most common 80C51s give you a PWM based on the FX core PCA.

You can also get > 8 bit resolve in a single 8 bit PWM channel,
by carefully timed LSB rate Multiplier modulation, but of course
the corner frequency must reduce. Many applications such as calibration,
self test, offset corrections can tolerate low corner frequencies.

I am sorry but that does not answer my question. The RC time constant of
the low pass filter must be much longer than the repetition rate of the PWM
i order for its pole to be at a fequency a lot less than the PWM fequency.
If the PWM duty cyle is less than 50% the capacitor will charge up to a
small dc voltage when the output is high in the first part of the cycle.
from then on the output is low and the capacitor discharges thru the series
resistor and the port output FET. As the low lasts longer than the high
(duty cycle < 50%) the capacitor must discharge to zero. Please explain
how this is wrong.

The PWM signal is either at +E or 0. The output is whatever V is
present across the capacitor. The voltage across R is E-V, which
is not constant. The rate of change of voltage across the
capacitor is governed by Q = C(E-V), and the only things varying
with time are Q and E and thence V, which is exactly Q/C. The
capacitor never charges up to E nor discharges to zero.

This is the very simplest low pass filter. You want the time
constant RC to be several times the repetition period of the PWM
signal. The whole circuit can be completely analyzed with the
simplest calculus, but the above should give you a feel for what
is happening.

At last, the light finaly dawns on me. Of course the capacitor does not
discharge fully because the voltage on it is very small. So every cycle
the cap will chage up a bit until equilibrium is reached when the small
voltage across R is just enough to restore the charge loss during the off
period.

Many thanks for your patience. I find it is always of benefit to revisit
fundamentals and renew your understanding.

Download a free/demo spice PGM from
http://www.beigebag.com/demo_form_stulite.htm
or wherever, and try it :)
I think you are treating the charge/discharge as linear, and equal,
whilst they are actually relative to the DC filtered output, and
exponential.
-jg

I was not thinking of them as linear but as equal. What I realise now is
that although the charge/discharge time constants are equal, the
charge/discharge voltage are not equal. In the charge case it is the
positive power supply. In the discharge it is the present voltage across
the capacitor, which is clearly different.

This would not convert a pwm into a representative analog voltage. The
capacitor would charge up by some instable amount (diode drops are not
stable with temperature or current) but would not discharge except through
a load, again unpredictable.

Beware, not all good intentions on usenet are accurate. Lose the diode
and re-read Blake & my earlier response.