FloTHERM is powerful 3D computational fluid dynamics (CFD) software that predicts airflow and heat transfer in and around electronic equipment, from components and boards up to complete systems. Learn More →

Clocks will be Clocks..

Clock designers are an enigma. Clock designers in general are die hard star wars fans, own vintage Porsches that leak oil by the gallon, usually have lava lamps in their offices/cubicles, wear fancy leather jackets in peak summer and have likeminded clock designers as best lunch buddies. Clock designers are notorious for making other lesser designers cry with their fancy PLL spice runs, non-negotiable skew numbers and for being resource hogs, especially higher layer metals. Clock designers live and breathe Pico seconds & watts (more recently) while the lesser mortals are perfectly happy to go for beers after two optimization runs. I have never been a clock designer myself but I have worked with clocks & clock designers for the longest time in my career, first as a design engineer, poring over timing reports and then as an application engineer supporting a sign-off timing tool. Building a good well balanced clock tree and effectively managing clock skew has been a challenge since the first transistor was invented and it still is today, especially at 28 & 22nm – The only difference is that now power is in the mix along with timing which complicates things even more. At smaller technology nodes the clock network is responsible for more than half the power consumed on any chip and majority of it is dynamic power due to the toggling clock.

As we are all are aware, clocks are a significant source of dynamic power usage, and clock tree synthesis (CTS) and optimization is a great place to achieve power savings in the physical design flow. The traditional low-power CTS strategies include lowering overall capacitance, specifically leaf caps, minimizing switching activity and minimizing area and buffer count in the clock tree.

While the traditional techniques help optimize clock tree power to a certain extent, Multi-Corner Multi-Mode (MCMM) CTS is an absolute must for achieving optimal QoR for both timing and power. One of the biggest challenges of design variation is clock tree synthesis. In smaller nodes, large variations of resistance seen across various process corners pose additional challenge of balancing the clock skew across multiple corners. With the proliferation of mobile devices, clock trees have become extremely complex circuits with different clock tracing per circuit mode of operation. Further, building robust clock trees that can withstand process variation is a huge challenge for the design teams.

Getting the best power reduction from CTS depends on the ability to synthesize the clocks for multiple corners and modes concurrently in the presence of design and manufacturing variability. Multi-corner CTS can measure early and late clock network delays over all process corners concurrently with both global and local variation accounted for. A multi-corner dynamic tradeoff between either buffering the wire or assigning it to less resistive layers is essential in order to achieve the best delay, area & power tradeoff.In comparison to the 1M1C flow the MCMM CTS solution provides significant reduction in area, buffer count, skew, TNS, and WNS in addition to lower dynamic power.

Now, before I forget let me state what I wanted to in the first place – I have to confess that I can now relate to this unique breed of clock designers and have utmost respect them for solving some of the most difficult chip design challenges thrown at them. A whole new generation is evolving with much cooler iphones and Gore-Tex jackets.

More Blog Posts

About Arvind Narayanan

Arvind Narayanan is the Olympus-SoC product marketing manager for Mentor’s place and route group. Arvind started his career as a microprocessor design engineer for Hal Computer Systems and has been in the semiconductor industry for over 14 years in different capacities, ranging from processor design engineer to application engineer and product marketing. His EDA experience includes working on STA at Synopsys and low power design analysis and implementation at Magma. At Mentor he has a broad view of the latest low power design techniques being used at our most advanced customers. Arvind earned his MS in Electrical and Computer Engineering from Mississippi State University, and MBA from Duke University.
Visit The Power Play