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Friday, 24 August 2012

Supply voltage.

The bipolar TIT, fami-lies require +5 volts, +5%, whereas the CMOS families have a wider range: +2 to +6 volts for HC and AC, +3 to +15 volts for 4000B and 74C. The HCT and ACT CMOS families, designed for compatibility with bipolar TTL (see below), require +5 volts. Input A TTL input held in the LOW state sources current into whatever drives it (0.25mA typ for LS), so to pull it LOW you must sink current. Since the TTL output circuit (a saturated npn transition) is good at sinking current, this presents no problem when TTL logic is wired together, but you must keep it in mind when driving TTL with other circuitry. By contrast, CMOS has no input current. The TTL input logic threshold is about two diode drops above ground (about 1.3V), whereas most CMOS families have their threshold nominally at half the sup-ply voltage (though with considerable spread, typically 1/3 to 2/3 the supply voltage). The HCT and ACT CMOS fami-lies are designed with a low threshold sim-ilar to bipolar TTL for compatibility, since bipolar TTL output does not swing all the way to +5 volts (see below).CMOS inputs are susceptible to damage from static electricity during handling. In both families, unused inputs should be tied HIGH or LOW, as necessary.

Output.

The TTL output stage is a sat-urated transistor to ground in the LOW state, and a (Darlington) follower in the HIGH state (two diode drops below V+). For all CMOS families (including HCT and ACT) the output is a turned-on MOSFET, either to ground or to lc; i.e., rail-to-rail output swings. In general, the faster families (F, AS; AC, ACT) have greater output drive capability than the slower families (LS; 4000B, 74C, HC, HCT).

Speed and power.

The bipolar TTL families consume considerable quiescent current, more for the faster families (AS and F); the corresponding speeds go from about 25MHz (for LS) to about 100MHz (for AS and F). All CMOS families consume zero quiescent current. However, their power consumption rises linearly with increasing frequency (switching capacitive loads re-quires current), and CMOS operated near its upper frequency limit often dissipates as much power as the equivalent bipolar TTL family (Fig. 8.18). The speed range of CMOS goes from about 2MHz (for 4000B/74C at 5V) to about 100MHz (for AC/ACT). In general, the nice characteristics of CMOS (zero quiescent current, rail-to-rail output swings, good noise immunity) make it the logic of choice, and we recommend the HC family for most new designs. However, for greater speed, use AC; for wide supply range where high speed is not needed, use 74C or 4000B; use HCT (or perhaps LS) for compatibility with bipolar TTL outputs, unless you need the speed of ACT (or AS or F). In some high-density applications (memory, micro-processor), NMOS devices are preferred, in spite of their relatively high power dissipation. And for the highest-speed appli-cations (above 100MHz) you are forced to use either ECL, which goes up to about 500MHz, or logic based on GaAs, which is usable to about 40Hz. See Section 14.15 and Table 9.1 for further discussion of CMOS logic families. Within any one logic family, outputs are designed to drive other inputs easily, so you don't often have to worry about thresholds, input current, etc. For instance, with TTL or CMOS, any output can drive at least 10 other inputs (the official term for this is fanout: TTL has a fanout of 10), so you don't have to do anything special to ensure compatibility. In the next chap-ter we will go into the issue of interfacing between logic families and between logic circuits and the outside world.