Senior Design Verification Engineer

Location: Montreal, QC, Canada

Type: Full Time

Min. Experience: Experienced

Verilab is an international professional services team of verification experts. Founded in 2000, we specialize in solving the toughest functional verification problems for ASIC, FPGA and independent IP development. Our work ranges from rescuing projects struggling with verification, through sophisticated verification IP development, to complete methodology engineering. We innovate, implement, manage and coach.

Benefits

Full-time permanent employee with competitive salary

Paid vacation and observed holidays

Medical, dental, and vision insurance

Due to the type of work we do with our clients, flexibility to travel is required.

Minimum Requirements

BS/MS in EE, CPE, or CS with at least 7 years of project proven verification experience.

SystemVerilog and UVM. We are interested in candidates who have developed multiple coverage-driven, self checking SV/UVM verification environments from scratch. They should have implementation experience of register models, config_db, high-level sequence-based stimulus, detailed functional coverage (for protocol and use-model features), on complex protocols such as USB, PCIe, or AXI. Candidates must have developed non-trivial end-to-end checkers. Examples include scoreboards handling data translation, re-ordering, grouping and dropping. Candidates must also have direct experience of implementing protocol level checks for several different protocols. Experience of implementing checks in SVA would be an advantage.

C/C++ experience should include integrating reference models into SV/UVM environments. Experience of embedded C/C++ high and low level test coding for ARM, or GPU processors, is a plus.

Verification Planning. We are looking for candidates proficient in verification planning, who have had to gather high and low level requirements, and followed a methodology to translate them into the elements of the plan. Candidates must be experienced in estimating and prioritizing verification activities, and in the metrics used to determine verification closure. A working knowledge of automated traceability of results back to requirements is a plus.

Scripting is often required when creating a verification environment. Candidates should be comfortable modifying scripts written in a variety of languages, and should be able to demonstrate proficiency in at least one common scripting language (preferably Python or Perl). Experience writing generators for testbench or RTL code is a plus, especially utilising XML, YAML or similar for configuration specification.

Ownership & Leadership. We are only interested in candidates who have had ownership of their work, from specification to implementation, and have had to deal directly with the technical challenges, compromises and deadlines on multiple projects. Where candidates have been in a leadership or project management position, we are interested in a working knowledge of Agile (e.g. SCRUM), budgeting and resource planning, peer technical reviews, audits, root cause analysis, and mentoring.

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Verilab engineers may be required to travel as part of their work for remote clients. Please describe your availability for remote work (percentage, or describe scenarios such as 3 weeks onsite followed by 1 week onsite per month, etc). **