We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Firefox,
Internet Explorer 11,
Safari. Thank you!

AR# 41169

Description

To calculate the overall SDRAM performance, peak bandwidth and efficiency must be taken into account.Near peak bandwidth only occurs during bursts of reads or writes. Overhead always exists on the DRAM data bus which lowers the effective data rate.Examples of overhead on the DRAM data bus are:

Activate time for new banks/rows

Precharge time for changing rows within the same bank

Write recovery time to change to read accesses

Bus turnaround time to change from read to write

Refresh time

ZQ Calibration time (DDR3 only)

The amount of overhead varies greatly based on the traffic pattern. Both the command and address patterns are important to analyze. For the command pattern, grouping reads together and writes together results in the least amount of overhead. Whereas, requesting alternating write and read commands (W-R-W-R) results in high overhead to account for Write Recovery Time and bus turnaround time. Similarly, the address pattern can greatly affect the overhead. Sequentially bursting across a row has little to no overhead. Whereas, a random address pattern results in high overhead due to Activate and Precharge times. Consequently, simulating the target traffic pattern must be completed to calculate efficiency.

To properly include any overhead into the overall SDRAM performance, the following should be used to calculate the efficiency and effective bandwidth:

Efficiency (%) = Number of Clock Cycles Transferring Data / Total Number of Clock Cycles

Effective Bandwidth = Peak Bandwidth * Efficiency

Note: Some users have separate efficiency targets for writes versus reads. Efficiency rates can be calculated separately for reads and writes.

Note:This Answer Record is part of the Xilinx MIG Solution Center(Xilinx Answer 34243)The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

To calculate efficiency, run a simulation with the target traffic pattern driving the user interface of the MIG design and count the number of clock cycles transferring data on the DDR bus and the total number of clock cycles:

Wait for init_calib_complete to assert

Look for the first Activate command associated with the target traffic pattern