JESD204B IP Core and AD9162 Hardware Checkout Report

The JESD204B IP Core has been hardware-tested with a number of selected
JESD204B-compliant DAC (digital-to-analog converter) devices.

This report highlights the interoperability of the JESD204B IP Core with the AD9162
converter evaluation module (EVM) from Analog Devices Inc. (ADI). The following sections
describe the hardware checkout methodology and test results.

Hardware Requirements

The hardware checkout test requires the following hardware and software tools:

Arria 10 GX FPGA Development Kit

ADI AD9162-FMCC-EBZ

Micro-USB cable

SMA cable

Oscilloscope

Hardware Setup

Figure 1. Arria 10 GX FPGA Development Kit Hardware Setup. An Arria 10 GX Development Kit is used with the ADI AD9162 daughter
card module installed to the FMC connector B of the development board.

The AD9162 EVM derives power from FMC pins.

The DAC sampling clock is supplied by the ADF4355 clock
generator on the DAC AD9162 EVM.

The FPGA device clock is supplied by the AD9508 clock fan-out buffer on the
EVM through FMC pins. The link and frame clocks are generated from the
device clock using IOPLL.

For subclass 1, AD9508 clock generator on the EVM generates
SYSREF for JESD204B IP core through FMC pins as well as the DAC AD9162.

The sync_n signal is transmitted from the DAC to FPGA
through FMC.

Figure 2. System Diagram

In this setup, where LMF=821, the data rate of transceiver lanes is 12.5 Gbps. Two clock
generators are available on the EVM – ADF4355 and AD9508. The ADF4355 clock generator
uses 120MHz crystal oscillator as reference clock to generate the DAC sampling clock and
reference clock for AD9508 clock generator. The AD9508 supplies FPGA device clock and
SYSREF for FPGA through FMC pins. In addition to this SYSREF for DAC is also generated.
The DAC AD9162 provides SYNC_N signal through FMC pins. The DAC operates in single JESD
link in all configurations.

The clock generators and DAC are programmed by FPGA through SPI interface. The DAC
provides a 4-wire SPI interface, while the clock generators on the EVM provide a 3-wire
SPI interface for programming. The SPI word size is 24 bits for DAC and AD9508 while the
word size is 32 bits for ADF4355 clock generator. A user logic is written on FPGA to
take care of these differences and allow programming of all 3 SPI slaves.

Hardware Checkout Methodology

The following section describes the test objectives, procedure, and the passing criteria. The test covers the following areas:

Transmitter data link layer

Transmitter transport layer

Scrambling

Deterministic latency (Subclass 1)

Transmitter Data Link Layer

This test area covers the test cases for code group synchronization (CGS) and initial lane
alignment sequence.

Code Group Synchronization (CGS)

Table 1. CGS Test Cases. L in the following table indicates the number of lanes.

Test Case

Objective

Description

Passing Criteria

CGS.1

Check that /K/ characters are transmitted when sync_n is
asserted.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

jesd204_tx_pcs_data[(L*32)-1:0]

jesd204_tx_pcs_kchar_data[(L*4)-1:0]

The following signals in <ip_variant_name>.v are tapped:

sync_n

jesd204_tx_int

The txlink_clk is used as the sampling clock for the SignalTap II.

Each lane is represented by 32-bit data bus in jesd204_tx_pcs_data
signal. The 32-bit data bus is divided into 4 octets.

Check the Code Group Synchronization Status status in the AD9162
Register.

/K/ character or K28.5 (0xBC) is transmitted at each octet of the
jesd204_tx_pcs_data bus when the receiver asserts the sync_n
signal.

The jesd204_tx_pcs_kchar_data signal is asserted when-ever control
characters like /K/ characters are transmitted.

The jesd204_tx_int is deas-serted if there is no error.

The “Code Group Synchronization Status” for all lanes should be
asserted in DAC Register 0x470.

CGS.2

Check that /K/ characters are transmitted after sync_n
is deasserted but before the start of multiframe.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

jesd204_tx_pcs_data[(L*32)-1:0]

jesd204_tx_pcs_kchar_data[(L*4)-1:0]

The following signals in <ip_variant_name>.v are tapped:

sync_n

tx_sysref

jesd204_tx_int

The txlink_clk is used as the sampling clock for the SignalTap II.

Each lane is represented by 32-bit data bus in the jesd204_tx_pcs_data
signal. The 32-bit data bus is divided into 4 octets.

Check the following error in the AD9162 reg-ister:

8b/10b Not-in-Table Error

8b/10b Disparity Error

The /K/ character transmission continues for at least 1 frame plus 9
octets.

The sync_n and jesd204_tx_int signals are deasserted.

The “8b/10b Not-in-Table Error” and “8b/10b Disparity Error” in
AD9162 registers 0x46E and 0x46D respectively should not be
asserted.

Initial Frame and Lane Synchronization

Table 2. Initial Frame and Lane Synchronization Test Cases. L in the following table indicates the number of lanes.

Test Case

Objective

Description

Passing Criteria

ILA.1

Check that the /R/ and /A/ characters are transmitted at the beginning
and end of each multiframe.

Verify that four multiframes are transmitted in ILAS phase and receiver
detects the initial lane alignment sequence correctly.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

jesd204_tx_pcs_data[(L*32)-1:0]

jesd204_tx_pcs_kchar_data[(L*4)-1:0]

The following signals in <ip_variant_name>.v are tapped:

sync_n

jesd204_tx_int

The txlink_clk is used as the sampling clock for the SignalTap II.

Each lane is represented by 32-bit data bus in jesd204_tx_pcs_data. The
32-bit data bus for is divided into 4 octets.

Check the following status in the AD9162 regis-ters:

Frame Synchronization

Initial Lane Synchronization

The /R/ character or K28.0 (0x1C) is transmitted at the
jesd204_tx_pcs_data bus to mark the beginning of multiframe.

The /A/ character or K28.3 (0x7C) is transmitted at the
jesd204_tx_pcs_data bus to mark the end of each multiframe.

The sync_n and jesd204_tx_int signals are deasserted.

The jesd204_tx_pcs_kchar_data signal is asserted when-ever control
characters like /K/, /R/, /Q/ or /A/ characters are transmitted.

The “Frame and Initial Lane Synchronization” status for all lanes
should be asserted in the AD9162 registers 0x471 and 0x473
respec-tively.

ILA.2

Check the JESD204B configuration parameters are
transmitted in the second multiframe.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

jesd204_tx_pcs_data[(L*32)-1:0]

The following signal in <ip_variant_name>.v is tapped:

jesd204_tx_int

The txlink_clk is used as the sampling clock for the SignalTap II.

The system console accesses the following JESD CSR registers:

ilas_data1

ilas_data2

The content of 14 configuration octets in second multiframe is stored in
the above 32-bit registers.

Check the following status and error in the AD9162 register:

Good Checksum

Configuration Mismatch Error

The /R/ character is fol-lowed by /Q/ character or K28.4 (0x9C) in
the jesd204_tx_pcs_data at the beginning of second multiframe.

The jesd204_tx_int is deasserted if there is no error.

The JESD204B parameters read from ilas_data1, ilas_data2 registers
are the same as the parameters set in the JESD204B IP Core Qsys
parameter editor.

The “Link Configuration Mismatch Error” in the AD9162 register 0x4BB
should not be asserted and the “Good Checksum” status for the AD9162
register 0x472 should be asserted.

ILA.3

Check the constant pattern of transmitted user data
after the end of 4th multiframes.

Verify that the receiver successfully
enters user data phase.

The following signals in <ip_variant_name>_inst_phy.v are tapped:

jesd204_tx_pcs_data[(L*32)-1:0]

The following signals in <ip_variant_name>.v are tapped:

jesd204_tx_int

The txlink_clk is used as the sampling clock for the SignalTap II.

The system console accesses the JESD CSR register - tx_err.

Check the following errors in the AD9162 register:

Lane FIFO Full

Lane FIFO Empty

When scrambler is turned off, the first user data is transmitted
after the last /A/ character, which marks the end of the 4th
mul-tiframe transmitted.1

Bits 2 and 3 of the JESD tx_err register are not set to “1”.

The “Lane FIFO Full” and “Lane FIFO Empty” in the AD9162 registers
0x30C and 0x30D should not be asserted.

The jesd204_tx_int is deasserted if there is no error.

1 When scrambler is turned on, the data
pattern cannot be recognized after the 4th multiframe in ILAS
phase.

Transceiver Transport Layer

To verify the data integrity of the payload data stream through the TX JESD204B IP core
and transport layer,the DAC’s JESD core is configured to check short transport layer
test pattern that is transmitted from FPGA’s test pattern generator. The DAC JESD core
checks the transport layer test patterns based on F = 1, 2, 4 or 8 configuration. The
short test pattern has a duration of one frame period and is repeated continu- ously for
the duration of the test.

To verify that data from the FPGA digital domain is successfully sent to the DAC analog
domain, the FPGA is configured to generate a sinewave. Connect an oscilloscope to
observe the waveform at the DAC analog channels.

Check the functionality of the scrambler using short
transport layer test pattern as specified in the parameter
configuration.

Enable descrambler at the DAC JESD core and scrambler at the
TX JESD204B IP core.

The signals that are tapped in this test case are similar to
test case TL.1

Check the following status in the DAC:

STPL test status

Thejesd204_tx_data_ready and jesd204_tx_data_valid
signals are asserted.

The STPL error for all DACs is checked in DAC register
0x32F and jesd204_tx_int signal should be deasserted.

SCR.2

Verify the data transfer from digital to analog
domain

Enable descrambler at the DAC JESD core and scrambler at the
TX JESD204B IP core.

Enable sine wave generator in the FPGA and observe the DAC
analog channel output on the oscilloscope.

A monotone sine wave is observed on the
oscilloscope.

Deterministic Latency (Subclass 1)

Figure below shows a block diagram of the deterministic latency test setup. The
AD9508 clock fan-out buffer provides periodic SYSREF pulses for both the AD9162 and
JESD204B IP Core. The period of SYSREF pulses is configured to 2 Local Multi Frame
Clocks (LMFC). The SYSREF pulse restarts the LMF counter and realigns it to the LMFC
boundary.

Figure 4. Deterministic Latency Test Setup Block Diagram

The FPGA generates a 16-bit digital sample with a value of 8000 hexadecimal
number at the transport layer. The most significant bit of this digital sample has a
logic 1 and this bit is pin out at FPGA. This bit is probed at oscilloscope channel 1.
The DAC analog channel is probed at oscilloscope channel 2. With two's complement value
of 8000h, a pulse with the amplitude of negative full range is expected at DAC analog
channel output. The time difference between the pulses at channel 1 (t0) and channel 2
(t1) is measured. This is the total latency of the JESD204B link, the DAC digital
blocks, and analog channel.

Table 5. Deterministic Latency Test Cases

Test Case

Objective

Description

Passing Criteria

DL.1

Measure the total latency.

Measure the time difference between the rising edge
of pulses at oscilloscope channel 1 and 2.

The latency should be consistent.

DL.2

Re-measure the total latency after DAC power cycle
and FPGA reconfiguration.

Measure the time difference between the rising edge
of pulses at oscilloscope channel 1 and 2.

5 Sine wave pattern is used in TL.2 and
SCR.2 test cases to verify that pattern generated in the FPGA transport
layer is transmitted by DAC analog channel. Single pulse pattern is used
in deterministic latency measurement test cases DL.1 and DL.2 only.
Constant pattern is used to check the STPL test. DAC does not support
STPL test for modes with 3 and 6 lanes.

Test Results

The following table contains the possible results and their
definition.

Table 7. Results Definition

Result

Definition

PASS

TheDevice Under Test (DUT) was observed to
exhibit conformant behavior.

PASS with comments

TheDUT was observed to exhibit conformant
behavior. However, an additional explanation of the situation is
included, such as due to time limitations only a portion of the
testing was performed.

FAIL

The DUT was observed to exhibit non-conformant
behavior.

Warning

TheDUT was observed to exhibit behavior that is
not recommended.

Refer to comments

From the observations, a valid pass or fail
could not be determined. An additional explanation of the situation
is included.

Test Result Comments

In each test case, the TX JESD204B IP core successfully initializes from CGS phase, ILA
phase, and until user data phase. The behavior of the TX JESD204B IP core meets the
passing criteria.

No data integrity issue is observed from the short transport layer (STPL) test pattern
checkers at DAC JESD core for all modes except with 3 and 6 lanes. In these modes, the
DAC does not support the STPL test. Sine wave at transmitted frequency is observed at
analog channel when sine wave generators in FPGA are enabled for all supported JESD
modes.

In the deterministic latency measurement, consistent total latency is observed across
the JESD204B link and DAC analog channels.