The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.

A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.

Silicon advances have no doubt created new opportunities for product differentiation, but not without some unpredictability and uncertainty. Often, schematic creation (electrical), layout (physical), and verification steps are performed sequentially, with little or no visibility into the consequences of each physical design decision.

Using our flow, you can assess physical and electrical consequences of design decisions while these decisions are being made. Based on what you’ve observed, you can rerun simulation at any time with the layout parasitics, perform checks against performance-related constraints, and graphically evaluate pre- and post-layout waveforms. You can apply what-if analysis and in-design optimization across corners, which eliminates uncertainty that contributes to conservative overdesign.

You won’t have to worry about lag or interruptions because analysis and checking results are updated to your screen right away. As your design progresses, parasitic and current-related constraints are easily enabled and checked within your layout environment.

A key component of our electrically aware design flow is the Cadence Virtuoso® Layout Suite for Electrically Aware Design (EAD). The tool lets design teams monitor electrical issues while a layout is created, rather than waiting until the layout is completed before verifying that it meets the original design intent. You can electrically analyze, simulate, and verify interconnect decisions in real time to generate a layout that is electrically correct by construction.

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