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Description

BeagleLogic realizes a logic analyzer on the BeagleBone Black using the Programmable Real-Time units and matching firmware and Linux kernel modules on the BeagleBone Black. Supports capturing into up to 300+ MB of memory (out of the 512 MB) of the BeagleBone Black.

With the sigrok project, BeagleLogic gets support for software triggering and decoding a large variety of digital communication protocols. There's also a small web interface that allows plug-and-play debugging if you are not capturing tons of data once everything is up and running.

I recently designed a cape to help interface BeagleLogic with external circuits and protect the BeagleBone from 5V circuits. You are seeing the photos of the cape.

The possibilities with BeagleLogic are great, and this page should follow future development of BeagleLogic as it gradually evolves with more cool features.

Details

BeagleLogic is a part of a vision of inexpensive Single Board Computers being repurposed as a useful debugging tool, a logic analyzer. It should be the first in a series of tools to make high quality, feature-rich and well-connected instruments accessible to more people over a familiar Linux environment. I see BeagleLogic as an educational tool that can help in understanding digital protocols as well, as one can use the same BeagleBone to send SPI and I2C signals which can be looped back into the inputs to BeagleLogic.

BeagleLogic is delivered as a combination of a ready-to-run BeagleLogic System Image (Software) that can be flashed onto a SD card and which is preloaded with the kernel modules, firmware and software necessary to run BeagleLogic right after the system boots up and a BeagleLogic Cape (Hardware) that logic level translates 5V signals so you can debug 5V logic circuits with the BeagleBone Black.

This infographic compares BeagleLogic to other leading Logic Analyzers:

BeagleLogic makes use of the powerful sigrok library that provides a standardized interface to DMMs, scopes and logic analyzers. For logic analyzers, sigrok tools support decoding over 50different digital protocols (see complete list here) for supported protocols. Since BeagleBone runs Linux, it can run the whole sigrok tool set by itself, but it is usually better to process data on a PC as it's faster.

There's a series of technical explanation walkthorughs on my blog that detail how BeagleLogic works:

You are invited to join and participate in the discussion on how to make BeagleLogic better, or share your experience with BeagleLogic, any issues you faced, how you want to see this going in the future.

These instructions are for the BeagleLogic system image, and are now verified on a BeagleBone Black.

Open up a SSH to the BeagleBone and edit "/boot/uEnv.txt" in nano/vi. Scroll down a bit until you see these lines and make sure they appear the same as in this screenshot by removing a '#' from the red circled area and adding a '#' at the white circled area. Then save it and reboot.

This disables the eMMC. Now solder two 0R resistors on the bottom of the BeagleLogic cape (R8 & R9) to connect them to the logic inputs.

The device tree file also needs to be recompiled to multiplex the 13&14 pins into the BeagleLogic inputs. Download the precompiled version from here - note that this file is called BB-BEAGLELOGIC14-00A0.dtbo to differentiate it from the existing dtbo file which enables only 12 channels. Copy it into /lib/firmware.

Next, we need to edit the startup script to load our new device tree overlay to use all 14 pins. For this, edit /etc/rc.local , go to the line that says 'config-pin overlay BB-BEAGLELOGIC' and edit it to 'config-pin overlay BB-BEAGLELOGIC14'. It should now look like this:

Save it and reboot. After rebooting your system it disables the eMMC and then multiplexes the eMMC pins onto the PRU inputs. Thus you can use all 14 inputs on BeagleLogic.

IMPORTANT NOTE: Do not apply signals on these channels until the BeagleBone has finished booting. It is also a general precaution not to apply signal at any pin of the BeagleBone until it is fully powered up.

[ P.S. Thanks to @David Bacungan for reporting issues in the previous version of these instructions. These have now been addressed with this version of the guide. ]

Removed the cape EEPROM as it wasn't being utilized. All the configuration is handled in the BeagleLogic system Image.

Added a DS1307 RTC to keep time so that logic captures can be correctly timestamped. This will be reflected in the software as well.

Add a LDO with 3.3V / 1.8V select on Input side for configurable logic level thresholds. BeagleLogic should also be able to tolerate +/-12V logic signals, will be working out the best way to make it happen.

At the heart of the schematic is a 74LVCH16T245 logic level translator IC. This translator inputs are 5V tolerant so it shields (and up to a limited level in case of overvoltage transients) the BeagleBone Black from external circuit logic levels. Therefore with the cape you can debug TTL circuits and Arduino circuits without fear of harming the BeagleBone Black in normal usage.

The inputs of BeagleLogic are also the boot pins for the AM335x and hence must not be changed by external circuitry during the boot phase of the SoC. How do we ensure that external pin disturbances do not cause the BeagleBone to lock up at boot?

The answer is - through the little BSS138 MOSFET connected to the SYS_RESETn pin of the AM335x SoC. This pin is pulled low during the SoC boot and goes high after the SoC has booted up. When the pin is pulled low, the MOSFET is off, hence the OE pin of the 74LVCH16T245 buffer is pulled high by the 100K resistor causing all the outputs of the 74lVCH16T245 (the B rail in this case) to go high-impedance thus not disturbing the logic levels on those pins. Once SYS_RESETn is high, the MOSFET turns on and pulls OE low so that the outputs are enabled and follow the BeagleLogic inputs.

Thus using a cape not only provides a layer of logic translation but also a layer of isolation so that if connected to an external circuit with the BeagleBone powered down, the inputs do not accidentally parasitically power the AM335x SoC.

The EEPROM is there for cape configuration, however may be removed from the next iteration of capes as the BeagleLogic system image handles the configuration automatically.

Judges: Please take a few minutes to read this note that I had enclosed along with the BeagleLogic prototypes. Thanks!

Just in time, the semifinal video!

SFTP mapping is created using the File explorer by clicking on "Connect to server" button and adding the address - sftp://192.168.7.2/root ( or change to your IP ) . Then enter "root" as username and leave the password blank.

Channel "x" is bit "x - 1" in the channel binary data (which is stored little endian) Right to left is channel 14 to Channel 1 ( ie bit 13 to bit 0)

Default data captured is in 8 bits, but can be set to capture 16 bits. See sysfs attributes reference for a complete list of parameters that can be changed.

The label alongside each channel pin is the name to be used while using the "sigrok-cli" app. So if you wanted to capture channels 1, 2 and 3 you would use the names P8_45, P8_46 and P8_43 respectively and not refer to them as 1,3 and 5.

However if you process raw binary data, you must use the bit numbers ( channel number - 1) with sigrok to receive correctly.

Build Instructions

Assemble the BeagleLogic cape using the required components in the BOM posted above. SMT components are best reflowed and the pin headers soldered manually.

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Step 2

Download the BeagleLogic system image (*.img) from here . There should only be one image in this folder in the .img.xz format.

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Step 3

(i) Unzip the .img.xz using 7zip on Windows and then use a tool such as Win32 Disk Imager to write to the SD card(ii) In case you are running Ubuntu, Double-clicking the downloaded .img.xz would automatically start a tool such as "Disks" to write the image into a blank SD card. Alternatively something like `xzcat <image>.img.xz | dd of=/dev/sdX` where X = ID of your SD card (b, c, d, ...)

Discussions

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I'm looking into building a BeagleLogic myselffrom what I understand the one thing holding back the V2 schematic is the HV clamping for 12V / -12V inputsany news on where this might be up to. If it's still in progress do you know which IC your planning on using for the HV clamping?

Edit, it looks like the Saleae Logic Pro uses a series of individual Fet's to buffer the input for a max range of 10V to -10V, then feeds the inputs via a series of ADA4891-4 comparators

The 3.8.13 is as of now the only version of the Linux kernel on the BeagleBone Black which allows dynamically loadable/unloadable capes using "device tree overlays" as of now. However the overlay thing was hacky and couldn't make it to the mainline then.

The BeagleBone Black should technically be able to load the latest kernel and boot from it, but the drivers for PRU for the remoteproc subsystem (which is used by BeagleLogic) aren't there yet. It is planned to port the drivers and establish a framework which would make it to upstream (which is the reason I put it in the form in the first place), but there is no definite timeframe for this. Once the framework is in place upstream, BeagleLogic should follow soon.

On your interest form, I voted for support for kernels beyond 3.8.13. I'm curious as to why it doesn't currently support any kernel version that came out in the past two years (according to Wikipedia), especially when that version is not a long-term release. I'm not an embedded Linux expert, so maybe newer versions of Linux just aren't available for ARM yet…?