What’s New at 20 nm

by Bryon Moyer

We talked in a separate piece today about Synopsys’s multi-source clock synthesis technology, but that was only one of several pieces of new technology in their new package. Among other parts of the release were the following non-trivial items:

Double patterning: it’s real now. It’s not used for every layer, just the bottom few layers. But it’s no longer something that will come someday: it’s here.

In the past, metal was metal. When routing, each layer was useful, and all layers were considered to be the same. That’s not the case anymore: lower layers have skinny, resistive lines; upper layers have broader, less-resistive lines. So now it matters which layer gets used. If the router is going to pick a layer, it has to consider the performance implications.

IP blocks are standard today. The problem is, they don’t usually fit together particularly well, leaving narrow routing channels that tend to get congested. They’ve improved their router so that it restricts that area only to signals that really need to be there; everything else is routed a different way to make the best use of that limited space.

You can find a brief discussion about what’s new for 20 nm in IC Compiler can be found in their release announcing their work with Renesas; and what’s new in their other tools is outlined briefly in their release announcing their work with Samsung.

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