DALLAS -- Texas Instruments Inc. figures it can beat industry estimates for cost savings from 300-mm wafers with chip-layout tricks and by aggressively pushing device shrinks after the company completes qualification of its new 0.13-micron (130-nm) process technology in a 300-mm fab here next month.

TI's DMOS 6 fab is now completing qualification runs with the 0.13-micron copper CMOS process, and wafer starts are ramping from about 4,000 per month today to a target of 5,700 wafers per month by July. The 300-mm fab is now expected to have the capacity for 10,000 wafer starts per month by Jan. 1, 2003.

In addition, TI plans to qualify its recently disclosed 0.09-micron (90-nm) process on 300-mm wafers during the second half of 2003. In briefings with analysts this week, TI executives said the company is also installing factory-wide automation systems, which will move 300-mm wafer lots directly to each process tool, starting in the first quarter of 2003.

"The available silicon, on an area basis, increases 2.25 times when moving to 300-mm from 200-mm wafers, but because of layout advantages that we have with 300-mm, we have seen specific DSP chips that can deliver an effective area increase of about 2.4 times," said Bill Aylesworth, senior vice president and chief financial officer at TI.

"That gives us a chip cost savings--based just on the diameter increase--of about 40%, and the combination of the diameter increase and the shrink to 0.13-micron from 0.18-micron gives us about a 60% cost advantage for advanced logic with 300-mm," said the CFO, while briefing analysts and the press on Thursday.

Aylesworth said TI expects to beat International Seamtech's estimates for potential cost savings from 300-mm (12-inch) wafers by a combination of process shrinks and die layout techniques. He said Sematech is currently estimating that 300-mm fab costs will be 1.5-to-1.8 times higher than today's 200-mm fabs, because of higher price tags for tools and larger-diameter silicon substrates. But TI now believes it can push the cost of 300-mm below the current industry target.

"So far, all of our experience would say that Sematech's estimate is conservative," Aylesworth said. "We can do better than that, and we have the capability to have a lower production cost increase as the larger wafers ramp in production."

When the huge 300-mm DMOS 6 fab is fully equipped, TI expects the entire price tag to be about $2.4 billion, said Kevin Ritchie, senior vice president and manager of worldwide manufacturing operations at the Dallas-based company. TI is expanding and filling out the 150,000-square-feet of manufacturing space in DMOS 6 in phases.

Recently, the company decided to move up its next-phase of tool installations and is aiming to have the facility's capacity at 10,000 wafer starts per month by year's end. When fully equipped, the DMOS 6 fab will have the capacity for 35,000 twelve-inch wafer per month, said Ritchie, while briefing analysts this week.

Mixing 300-mm with foundries

While TI is ramping up its 300-mm fab, the company is also moving to a new foundry strategy, which will tap outside capacity for advanced logic ICs during the peak production cycles at each technology node. The target is to outsource as much as 50% of TI's most advanced logic ICs, splitting the leading-edge capacity between its own fabs and plants operated by Taiwan Semiconductor Manufacturing Co. Ltd. and United Microelectronics Corp. A third foundry for advanced logic could also be soon added to help protect against shortages in a sharp market upturn, it was disclosed this week (see May 16 story).

TI's new fab manufacturing strategy will "utilize foundries as well during the early peak periods of each technology node," explained Aylesworth, during Thursday's executive briefings for analysts and the press.

"The benefit for the foundries is that this pulls in early wafer demand for them at the leading-edge technologies. We have shared learning in that regard for TI and foundries," he said.

"TI lowers its capital investment and improves our return on invested capital--presumably for both TI and the foundries," said Aylesworth, in explaining the benefits to all parties from the new manufacturing strategy. TI expects to outsource fewer products in analog ICs, mixed-signal chip, and other segments. For example, all of TI's standard logic wafers will continue to be produced in Sherman, Tex.--north of Dallas--using mature technologies and older 6-inch (150-mm) wafer tools that are being transferred from other facilities.

"We believe over time TI's foundry usage on average will move from about 10%--where it has been historically--to about 20% over time with this augmentation," Aylesworth said, referring to the new leading-edge process outsourcing strategy.