Delay minimization and power minimization are two important objectives in the
design of the high-performance, portable, and wireless computing and
communication systems. Retiming is a very effective way for delay optimization
for sequential circuits. In this paper we propose a unified framework for
multi-level partitioning and floorplanning with retiming, targeting simultaneous
delay and power optimization. We first discuss the importance of retiming delay
and visible power as opposed to the conventional static delay and total power
for sequential circuits. Then we propose GEO-PD algorithm for simultaneous delay
and power optimization and provide smooth cutsize, wirelength, power and delay
tradeoff. In GEO-PD, we use retiming based timing analysis and visible power
analysis to identify timing and power critical nets and assign proper weights to
them to guide the multi-level optimization process. In general, timing and power
analysis are done at the original netlist while a recursive multi-level
approach performs partitioning and floorplanning on the sub-netlist as well as
its coarsened representations. We show an effective way to translate the timing
and power analysis results from the original netlist to a coarsened sub-netlist
for effective multi-level delay and power optimization. To the best of our
knowledge, this is the first paper addressing simultaneous delay and power
optimization in multi-level partitioning and floorplanning.