Data Path Design Considerations for a High Performance VLSI Multiprocessor

Daebum Lee

A VLSI data path implementation for the SPUR (Symbolic Processing Using RISC's) processor is presented. There are many tradeoffs to be considered in the design of a microprocessor data path. Often, these tradeoffs are interrelated and thus increase the complexity of the design. This report focuses on the design of the CMOS data path with the tradeoffs considered throughout the implementation of the data path for the SPUR CPU.

BibTeX citation:

@techreport{Lee:CSD-87-318,
Author = {Lee, Daebum},
Title = {Data Path Design Considerations for a High Performance VLSI Multiprocessor},
Institution = {EECS Department, University of California, Berkeley},
Year = {1986},
Month = {Nov},
URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/1986/5987.html},
Number = {UCB/CSD-87-318},
Abstract = {A VLSI data path implementation for the SPUR (Symbolic Processing Using RISC's) processor is presented. There are many tradeoffs to be considered in the design of a microprocessor data path. Often, these tradeoffs are interrelated and thus increase the complexity of the design. This report focuses on the design of the CMOS data path with the tradeoffs considered throughout the implementation of the data path for the SPUR CPU.}
}