Abstract

Gaussian Mixture Models (GMM)-based classifiers have shown increased attention in many pattern recognition applications. Improved performances have been demonstrated in many applications but using such classifiers can require large storage and complex processing units due to exponential calculations and large number of coefficients involved. This poses a serious problem for portable real-time pattern recognition applications. In this paper, first the performance of GMM and its hardware complexity are analyzed and compared with a number of benchmark algorithms. Next, an efficient digital hardware implementation based on Distributed Arithmetic (DA) is proposed. A novel exponential calculation circuit based on linear piecewise approximation is also developed to reduce hardware complexity. Implementation is carried out on the Celoxica-RC1000 board equipped with the Virtex-E FPGA. Maximum optimization has been achieved by means of manual placement and routing in order to achieve a compact core footprint. A detailed evaluation of the performance metrics of the GMM core is also presented.

abstract = "Gaussian Mixture Models (GMM)-based classifiers have shown increased attention in many pattern recognition applications. Improved performances have been demonstrated in many applications but using such classifiers can require large storage and complex processing units due to exponential calculations and large number of coefficients involved. This poses a serious problem for portable real-time pattern recognition applications. In this paper, first the performance of GMM and its hardware complexity are analyzed and compared with a number of benchmark algorithms. Next, an efficient digital hardware implementation based on Distributed Arithmetic (DA) is proposed. A novel exponential calculation circuit based on linear piecewise approximation is also developed to reduce hardware complexity. Implementation is carried out on the Celoxica-RC1000 board equipped with the Virtex-E FPGA. Maximum optimization has been achieved by means of manual placement and routing in order to achieve a compact core footprint. A detailed evaluation of the performance metrics of the GMM core is also presented.",

N2 - Gaussian Mixture Models (GMM)-based classifiers have shown increased attention in many pattern recognition applications. Improved performances have been demonstrated in many applications but using such classifiers can require large storage and complex processing units due to exponential calculations and large number of coefficients involved. This poses a serious problem for portable real-time pattern recognition applications. In this paper, first the performance of GMM and its hardware complexity are analyzed and compared with a number of benchmark algorithms. Next, an efficient digital hardware implementation based on Distributed Arithmetic (DA) is proposed. A novel exponential calculation circuit based on linear piecewise approximation is also developed to reduce hardware complexity. Implementation is carried out on the Celoxica-RC1000 board equipped with the Virtex-E FPGA. Maximum optimization has been achieved by means of manual placement and routing in order to achieve a compact core footprint. A detailed evaluation of the performance metrics of the GMM core is also presented.

AB - Gaussian Mixture Models (GMM)-based classifiers have shown increased attention in many pattern recognition applications. Improved performances have been demonstrated in many applications but using such classifiers can require large storage and complex processing units due to exponential calculations and large number of coefficients involved. This poses a serious problem for portable real-time pattern recognition applications. In this paper, first the performance of GMM and its hardware complexity are analyzed and compared with a number of benchmark algorithms. Next, an efficient digital hardware implementation based on Distributed Arithmetic (DA) is proposed. A novel exponential calculation circuit based on linear piecewise approximation is also developed to reduce hardware complexity. Implementation is carried out on the Celoxica-RC1000 board equipped with the Virtex-E FPGA. Maximum optimization has been achieved by means of manual placement and routing in order to achieve a compact core footprint. A detailed evaluation of the performance metrics of the GMM core is also presented.