topic Re: convert AXI Stream to AXI memory mapped in Processor System Design and AXIhttps://forums.xilinx.com/t5/Processor-System-Design-and-AXI/convert-AXI-Stream-to-AXI-memory-mapped/m-p/863265#M48972
<P>Thanks!</P><P>To be honest I am new in AXI, can you please provide some help, reference documents please</P>Fri, 08 Jun 2018 03:54:44 GMTp.hayk2018-06-08T03:54:44Zconvert AXI Stream to AXI memory mappedhttps://forums.xilinx.com/t5/Processor-System-Design-and-AXI/convert-AXI-Stream-to-AXI-memory-mapped/m-p/860686#M48965
<P>Hi,</P><P>I need to convert AXI stream data to AXI4 . Which IP is suitable for this?</P><P>I tried using AXI memory to stream mapper IP but later got to know that it must be used in pairs.</P><P>Which IP can I use?</P><P>&nbsp;</P><P>&nbsp;</P><P>&nbsp;</P><P>Thanks and regards,</P><P>Akshay M</P>Wed, 30 May 2018 11:10:28 GMThttps://forums.xilinx.com/t5/Processor-System-Design-and-AXI/convert-AXI-Stream-to-AXI-memory-mapped/m-p/860686#M48965akshay_iyngr952018-05-30T11:10:28ZRe: convert AXI Stream to AXI memory mappedhttps://forums.xilinx.com/t5/Processor-System-Design-and-AXI/convert-AXI-Stream-to-AXI-memory-mapped/m-p/860714#M48966
<P>This is exactly what the DMA block is for (or the VDMA, if you're working with images).</P>Wed, 30 May 2018 13:08:32 GMThttps://forums.xilinx.com/t5/Processor-System-Design-and-AXI/convert-AXI-Stream-to-AXI-memory-mapped/m-p/860714#M48966u42233742018-05-30T13:08:32ZRe: convert AXI Stream to AXI memory mappedhttps://forums.xilinx.com/t5/Processor-System-Design-and-AXI/convert-AXI-Stream-to-AXI-memory-mapped/m-p/860976#M48967
<P>Hi,&nbsp;<LI-USER uid="74556"></LI-USER></P><P>I'm sending stream data and it has to be converted to axi4 .</P><P>How can I get address for data in axi4? will it take automatically or should I provide some address manually through any other block?&nbsp;</P><P>and should I compulsorily use the axi_lite in my design?</P><P>&nbsp;</P><P>&nbsp;</P><P>Thanks and regards,</P><P>Akshay M</P>Thu, 31 May 2018 04:33:22 GMThttps://forums.xilinx.com/t5/Processor-System-Design-and-AXI/convert-AXI-Stream-to-AXI-memory-mapped/m-p/860976#M48967akshay_iyngr952018-05-31T04:33:22ZRe: convert AXI Stream to AXI memory mappedhttps://forums.xilinx.com/t5/Processor-System-Design-and-AXI/convert-AXI-Stream-to-AXI-memory-mapped/m-p/861089#M48968
<P><LI-USER uid="94892"></LI-USER> You're going to have to figure out some way of assigning addresses; doing automatic memory management is a vastly more complex task and requires a full CPU and operating system. For a simple project, just using fixed addresses (assigned during synthesis) is likely to be acceptable.</P>
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<P>I'd normally use AXI Lite and a MicroBlaze or Zynq controlling all the DMA blocks. However, if you don't want to use AXI Lite, there's the AXI DataMover IP core which does much the same task using an AXI Stream for control.</P>
<P>&nbsp;</P>Thu, 31 May 2018 10:34:08 GMThttps://forums.xilinx.com/t5/Processor-System-Design-and-AXI/convert-AXI-Stream-to-AXI-memory-mapped/m-p/861089#M48968u42233742018-05-31T10:34:08ZRe: convert AXI Stream to AXI memory mappedhttps://forums.xilinx.com/t5/Processor-System-Design-and-AXI/convert-AXI-Stream-to-AXI-memory-mapped/m-p/861092#M48969
<P>Hi,&nbsp;<LI-USER uid="74556"></LI-USER></P><P>&nbsp;</P><P>Thank you</P>Thu, 31 May 2018 10:38:04 GMThttps://forums.xilinx.com/t5/Processor-System-Design-and-AXI/convert-AXI-Stream-to-AXI-memory-mapped/m-p/861092#M48969akshay_iyngr952018-05-31T10:38:04ZRe: convert AXI Stream to AXI memory mappedhttps://forums.xilinx.com/t5/Processor-System-Design-and-AXI/convert-AXI-Stream-to-AXI-memory-mapped/m-p/862634#M48970
<P>Hello,</P><P>&nbsp;</P><P>Is it possible to use AXI DMA IP for this purpose?</P><P>&nbsp;</P><P>Thanks</P><P>&nbsp;</P>Wed, 06 Jun 2018 07:27:12 GMThttps://forums.xilinx.com/t5/Processor-System-Design-and-AXI/convert-AXI-Stream-to-AXI-memory-mapped/m-p/862634#M48970p.hayk2018-06-06T07:27:12ZRe: convert AXI Stream to AXI memory mappedhttps://forums.xilinx.com/t5/Processor-System-Design-and-AXI/convert-AXI-Stream-to-AXI-memory-mapped/m-p/862721#M48971
I guess it can be used. You might use the read channel only, to save some area.Wed, 06 Jun 2018 09:39:09 GMThttps://forums.xilinx.com/t5/Processor-System-Design-and-AXI/convert-AXI-Stream-to-AXI-memory-mapped/m-p/862721#M48971satguy2018-06-06T09:39:09ZRe: convert AXI Stream to AXI memory mappedhttps://forums.xilinx.com/t5/Processor-System-Design-and-AXI/convert-AXI-Stream-to-AXI-memory-mapped/m-p/863265#M48972
<P>Thanks!</P><P>To be honest I am new in AXI, can you please provide some help, reference documents please</P>Fri, 08 Jun 2018 03:54:44 GMThttps://forums.xilinx.com/t5/Processor-System-Design-and-AXI/convert-AXI-Stream-to-AXI-memory-mapped/m-p/863265#M48972p.hayk2018-06-08T03:54:44ZRe: convert AXI Stream to AXI memory mappedhttps://forums.xilinx.com/t5/Processor-System-Design-and-AXI/convert-AXI-Stream-to-AXI-memory-mapped/m-p/863285#M48973
Hello p.hayk,<BR /><BR />I'm also new to AXI, but hope this will be little help.<BR /><BR />To convert stream data into memory mapped data you can use, AXI DMA. And the dma can transfer the streamed data to DDR, or to a block ram as you wish.<BR /><BR />What you have to do is connect your stream master into AXI_DMA, S_AXIS_S2MM interface and the other end connect the M_AXI_S2MM to your memory side (Like for DDR you have to connect ZYNQ HP port or for block ram you can directly connect to block ram slave interface. you may have to use AXI_Interconnect to connect AXI Master and Slave interfaces)<BR /><BR />There are examples for AXI_DMA &lt;Install location&gt;\SDK\2016.4\data\embeddedsw\XilinxProcessorIPLib folder. You can use simple_poll example.<BR /><BR />This will be a good start point for you, I hope.<BR /><BR />Thank you.Fri, 08 Jun 2018 05:48:45 GMThttps://forums.xilinx.com/t5/Processor-System-Design-and-AXI/convert-AXI-Stream-to-AXI-memory-mapped/m-p/863285#M48973chathuranga19312018-06-08T05:48:45ZRe: convert AXI Stream to AXI memory mappedhttps://forums.xilinx.com/t5/Processor-System-Design-and-AXI/convert-AXI-Stream-to-AXI-memory-mapped/m-p/1103910#M52591
<P>Hello</P><P><SPAN>I am trying to read an image bare metal from SDK/Vitis (later on PetaLinux) to process this through a custom IP-core created in HLS. The HLS IP-core exists of blur &amp; threshold:</SPAN></P><P>#pragma HLS dataflow<BR />hls::AXIvideo2Mat(video_in, img_1);</P><P>hls::GaussianBlur&lt;5,5&gt;(img_1, img_2, 0, 0);<BR />hls::Threshold(img_2 ,img_3 , 200,255,HLS_THRESH_BINARY);</P><P>hls::Mat2AXIvideo(img_3, video_out);</P><P><SPAN>Transforming an Image into an Mat2AxiStream through the testBench is fairly easy and everything works as intended when simulating. My only question is how to do this with a VDMA (or is DMA enough ?) and with/without OpenCV libs, is there any good examples with a full workflow from HLS-Vivado-Vitis on this ? I have searched most of the forums already.</SPAN></P><P>&nbsp;</P><P><SPAN>Thank you</SPAN></P><P><SPAN>Gilles</SPAN></P>Thu, 07 May 2020 13:57:47 GMThttps://forums.xilinx.com/t5/Processor-System-Design-and-AXI/convert-AXI-Stream-to-AXI-memory-mapped/m-p/1103910#M52591gilles0072020-05-07T13:57:47ZRe: convert AXI Stream to AXI memory mappedhttps://forums.xilinx.com/t5/Processor-System-Design-and-AXI/convert-AXI-Stream-to-AXI-memory-mapped/m-p/1104003#M52592
<P><LI-USER uid="161441"></LI-USER>,</P><P>This is really off topic for the question currently at hand.&nbsp; Let me recommend you consider reposting under the HLS forum to get the most attention to your issue.</P><P>Dan</P>Thu, 07 May 2020 16:30:11 GMThttps://forums.xilinx.com/t5/Processor-System-Design-and-AXI/convert-AXI-Stream-to-AXI-memory-mapped/m-p/1104003#M52592dgisselq2020-05-07T16:30:11Z