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Posts Tagged ‘Coby Zelnik’

We asked three EDA figures to comment on how the Synopsys purchase of Virage would impact the EDA and IP industries. Here’s what they said.

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This acquisition puts Synopsys squarely in the front of the pack as far as IP suppliers go. This trend could be quite significant. Successful IP reuse is a combination of the right EDA tools, best practices methodology and well-designed IP. The EDA vendor is a pretty good place for all that to come together. ARM remains the exception to this rule, and several other rules for that matter.

Mike Gianfagna
Vice President, Marketing
Atrenta, Inc.

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I don’t see how this doesn’t make Synopsys a competitor with ARM on physical IP and ARC processor. ARM should start feeling like it is getting surrounded by Synopsys.

Jim Hogan
EDA investor

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With EDA trying to expand its scope and grow beyond its traditional boundaries (see EDA360), and with small and medium size IP vendors struggling to grow, basic economy forces are pushing this trend.

Synopsys has already been a formidable IP player and Cadence now entered it with its recent acquisition of Denali.

There are still plenty of smaller IP players so we’ll see further consolidation playing out. The IP segment has been trying to define and position itself between EDA and semiconductors. We all wondered if IP would become an intrinsic part of the semiconductor industry, the EDA industry, or stand on its own. These days we clearly see that the IP pendulum has shifted toward EDA.

The outlier is of course ARM which is a different beast, in some ways closer to semiconductors: i.e., look at how ARM competes with Intel. With a market cap equivalent to Synopsys and Cadence put together, ARM is simply too big for that.

The big trend in EDA for 2010 will be the acceptance of social media as an additional means for communicating with customers, partners, and competitors.

Now that blogging is settling in as a viable source of information from media people, company experts, and independent publishers, more new media tools will come into play. Not all tools are right for everyone or every situation, so the EDA industry will explore the options and experiment with a variety of community-development activities.

LinkedIn and Facebook will offer special interest groups a place to congregate. Twitter will be tested by more people – who today are curious or skeptical – as a means of immediate, brief interaction. EDA suppliers will offer new communication channels and those that are truly value-add will thrive.

The EDA world won’t change overnight, but the trends in social media will be noticeable.

In 2010, we’ll see an accelerated move to doing more design at higher levels of abstraction.

Chip complexity and the skyrocketing cost of physical design, along with the advent of 3D stacks is forcing this. Designers just won’t be able to iterate in the back end in 2010 and beyond. It’ll take too long and cost too much.

Power management, design verification, design for test and timing closure will all be “close to done” before handoff to synthesis and place & route. The traditional backend flow of IC design will become a more predictable, routine process, which will accelerate its trend toward commoditization and consolidation.

This move to higher levels of abstraction will also have implications for IP selection and chip assembly. This will compel a new genre of tools to emerge. Standards like IP-XACT will help this process to take hold. Perhaps this is what ESL will become.

There will be a renewed focus on the challenges of integrating existing IP, providing breakthrough technology for design teams to quickly and reliably
assemble complex SoCs from integration-ready IP blocks, and then run
full-chip verification including both analog and digital components.

ESL is part of this story because there’s a need to move to
transaction-level IP creation, verification and integration. Hardware/ software integration and verification and will also become part of
the drive towards SoC integration.

As for the EDA trend in 2010, I think that EDA companies, when they recover, will choose not to hire more sales and marketing people but will invest more in other marketing tools on the Web or using social networking strategies.

A good example is a company like Xuropa, which is actually a client of mine, under full disclosure. They help EDA companies put their tools on the Web in order to help them reduce their costs for demos, product evaluations, etc.

I think that will see a lot of interest in the upcoming year as companies look for ways to do “more with less”. User group events may also move online, just like this year’s CDNLive was a virtual event rather than a real live event. Xilinx and Avnet sponsored an X-Fest this year that was also an online event. Things are moving online fast and economics will drive that.

The areas of greatest real ESL use are the high level synthesis of data crunching blocks used in various DSP-type applications (signal and media processing), the increasing adoption of processor/SW-centric design methods, and the increased creation and use of virtual prototype models.

(Brian Bailey and I have a new book from Springer coming out in the new year on practical ESL use methods: “ESL Models and their Application: Electronic System Level Design and Verification in Practice”. See for a summary. )

For EDA, 2010 will be the year of the foundry. Foundries will drive new EDA flows and business models.

The TSMC Open Initiative Platform
is but the tip of the iceberg. If EDA and IP companies do NOT join forces with the foundries and take arms against the sea of semiconductor troubles – they will continue to suffer the slings and arrows of outrageous economic misfortune.

In an effort to minimize risk, cost and time to market, design reuse will be
maximized; many of them will be migrations of existing 90nm and 65nm products or derivative products with minor updates and tweaks.