Posts Tagged ‘manufacturing’

In-the-know attendees at SEMICON West at a Thursday morning working breakfast heard from executives representing the world’s leading memory fabs discuss manufacturing challenges at the 4th annual Entegris Yield Forum. Among the excellent presenters was Norm Armour, managing director worldwide facilities and corporate EHSS of Micron. Armour has been responsible for some of the most famous fabs in the world, including the Malta, New York logic fab of GlobalFoundries, and AMD’s Fab25 in Austin, Texas. He discussed how facilities systems effect yield and parametric control in the fab.

Just recently, his organization within Micron broke records working with M&W on the new flagship Fab 10X in Singapore—now running 3D-NAND—by going from ground-breaking to first-tool-in in less than 12 months, followed by over 400 tools installed in 3 months. “The devil is in the details across the board, especially for 20nm and below,” declared Armour. “Fabs are delicate ecosystems. I’ll give a few examples from a high-volume fab of things that you would never expect to see, of component-level failures that caused major yield crashes.”

Ultra-Pure Water (UPW)

Ultra-Pure Water (UPW) is critical for IC fab processes including cleaning, etching, CMP, and immersion lithography, and contamination specs are now at the part-per-billion (ppb) or part-per-trillion (ppt) levels. Use of online monitoring is mandatory to mitigate risk of contamination. International Technology Roadmap for Semiconductors (ITRS) guidelines for UPW quality (minimum acceptable standard) include the following critical parameters:

Resistivity @ 25C >18.0 Mohm-cm,

TOC <1.0 ppb,

Particles/ml < 0.3 @ 0.05 um, and

Bacteria by culture 1000 ml <1.

In one case associated with a gate cleaning tool, elevated levels of zinc were detected with lots that had passed through one particular tool for a variation on a classic SC1 wet clean. High-purity chemistries were eliminated as sources based on analytical testing, so the root-cause analysis shifted to to the UPW system as a possible source. Then statistical analysis could show a positive correlation between UPW supply lines equipped with pressure regulators and the zinc exposure. The pressure regulator vendor confirmed use of zinc-oxide and zinc-stearate as part of the assembly process of the pressure regulator. “It was really a curing agent for an elastomer diaphragm that caused the contamination of multiple lots,” confided Armour.

UPW pressure regulators are just one of many components used in facilities builds that can significantly degrade fab yield. It is critical to implement a rigorous component testing and qualification process prior to component installation and widespread use. “Don’t take anything for granted,” advised Armour. “Things like UPW regulators have a first-order impact upon yield and they need to be characterized carefully, especially during new fab construction and fit up.”

Photoresist filtration

Photoresist filtration has always been important to ensure high yield in manufacturing, but it has become ultra-critical for lithography at the 20nm node and below. Dependable filtration is particularly important because industry lacks in-line monitoring technology capable of detecting particles in the range below ~40nm.

Micron tried using filters with 50nm pore diameters for a 20nm node process…and saw excessive yield losses along with extreme yield variability. “We characterized pressure-drop as a function of flow-rate, and looked at various filter performances for both 20nm and 40nm particles,” explained Armour. “We implemented a new filter, and lo and behold saw a step function increase in our yields. Defect densities dropped dramatically.” Tracking the yields over time showed that the variability was significantly reduced around the higher yield-entitlement level.

Airborne Molecular Contamination (AMC)

Airborne Molecular Contamination (AMC) is ‘public enemy number one’ in 20nm-node and below fabs around the world. “In one case there were forrest fires in Sumatra and the smoke was going into the atmosphere and actually went into our air intakes in a high volume fab in Taiwan thousands of miles away, and we saw a spike in hydrogen-sulfide,” confided Armour. “It increased our copper CMP defects, due to copper migration. After we installed higher-quality AMC filters for the make-up air units we saw dramatic improvement in copper defects. So what is most important is that you have real-time on-line monitoring of AMC levels.”

Building collaborative relationships with vendors is critical for troubleshooting component issues and improving component quality. “Partnering with suppliers like Entegris is absolutely essential,” continued Armour. “On AMCs for example, we have had a very close partnership that developed out of a team working together at our Inotera fab in Taiwan. There are thousands of important technologies that we need to leverage now to guarantee high yields in leading-node fabs.” The Figure shows just some of the AMCs that must be monitored in real-time.

Big Data

The only way to manage all of this complexity is with “Big Data” and in addition to primary process parameter that must be tracked there are many essential facilities inputs to analytics:

“Conventional wisdom is that process tools create 90% of your defect density loss, but that’s changing toward facilities now,” said Armour. “So why not apply the same methodologies within facilities that we do in the fab?” SPC is after-the-fact reactive, while APC is real-time fault detection on input variables, including such parameters as vibration or flow-rate of a pump.

“Never enough data,” enthused Armour. “In terms of monitoring input variables, we do this through the PLCs and basically use SCADA to do the fault-detection interdiction on the critical input variables. This has been proven to be highly effective, providing a lot of protection, and letting me sleep better at night.”

Micron also uses these data to provide site-to-site comparisons. “We basically drive our laggard sites to meet our world-class sites in terms of reducing variation on facility input variables,” explained Armour. “We’re improving our forecasting as a result of this capability, and ultimately protecting our fab yields. Again, the last thing a fab manager wants to see is facilities causing yield loss and variation.”

Applied Materials has disclosed commercial availability of new Selectra(TM) selective etch twin-chamber hardware for the company’s high-volume manufacturing (HVM) Producer® platform. Using standard fluorine and chlorine gases already used in traditional Reactive Ion Etch (RIE) chambers, this new tool provides atomic-level precision in the selective removal of materials in 3D devices structures increasingly used for the most advanced silicon ICs. The tool is already in use at three customer fabs for finFET logic HVM, and at two memory fab customers, with a total of >350 chambers planned to have been shipped to many customers by the end of 2016.

Figure 1 shows a simplified cross-sectional schematic of the Selectra chamber, where the dashed white line indicates some manner of screening functionality so that “Ions are blocked, chemistry passes through” according to the company. In an exclusive interview with Solid State Technology, company representative refused to disclose any hardware details. “We are using typical chemistries that are used in the industry,” explained Ajay Bhatnagar, managing director of Selective Removal Products for Applied Materials. “If there are specific new applications needed than we can use new chemistry. We have a lot of IP on how we filter ions and how we allow radicals to combine on the wafer to create selectivity.”

FIG 1: Simplified cross-sectional schematic of a silicon wafer being etched by the neutral radicals downstream of the plasma in the Selectra chamber. (Source: Applied Materials)

From first principles we can assume that the ion filtering is accomplished with some manner of electrically-grounded metal screen. This etch technology accomplishes similar process results to Atomic Layer Etch (ALE) systems sold by Lam, while avoiding the need for specialized self-limiting chemistries and the accompanying chamber throughput reductions associated with pulse-purge process recipes.

“What we are doing is being able to control the amount of radicals coming to the wafer surface and controlling the removal rates very uniformly across the wafer surface,” asserted Bhatnagar. “If you have this level of atomic control then you don’t need the self-limiting capability. Most of our customers are controlling process with time, so we don’t need to use self-limiting chemistry.” Applied Materials claims that this allows the Selectra tool to have higher relative productivity compared to an ALE tool.

Due to the intrinsic 2D resolutions limits of optical lithography, leading IC fabs now use multi-patterning (MP) litho flows where sacrificial thin-films must be removed to create the final desired layout. Due to litho limits and CMOS device scaling limits, 2D logic transistors are being replaced by 3D finFETs and eventually Gate-All-Around (GAA) horizontal nanowires (NW). Due to dielectric leakage at the atomic scale, 2D NAND memory is being replaced by 3D-NAND stacks. All of these advanced IC fab processes require the removal of atomic-scale materials with extreme selectivity to remaining materials, so the Selectra chamber is expected to be a future work-horse for the industry.

When the industry moves to GAA-NW transistors, alternating layers of Si and SiGe will be grown on the wafer surface, 2D patterned into fins, and then the sacrificial SiGe must be selectively etched to form 3D arrays of NW. Figure 2 shows the SiGe etched from alternating Si/SiGe stacks using a Selectra tool, with sharp Si corners after etch indicating excellent selectivity.

“One of the fundamental differences between this system and old downstream plasma ashers, is that it was designed to provide extreme selectivity to different materials,” said Matt Cogorno, global product manager of Selective Removal Products for Applied Materials. “With this system we can provide silicon to titanium-nitride selectivity at 5000:1, or silicon to silicon-nitride selectivity at 2000:1. This is accomplished with the unique hardware architecture in the chamber combined with how we mix the chemistries. Also, there is no polymer formation in the etch process, so after etching there are no additional processing issues with the need for ashing and/or a wet-etch step to remove polymers.”

Systems can also be used to provide dry cleaning and surface-preparation due to the extreme selectivity and damage-free material removal. “You can control the removal rates,” explained Cogorno. “You don’t have ions on the wafer, but you can modulate the number of radicals coming down.” For HVM of ICs with atomic-scale device structures, this new tool can widen process windows and reduce costs compared to both dry RIE and wet etching.

As previously covered by Solid State Technology CEA-Leti in France has been developing monolithic transistor stacking based on laser re-crystallization of active silicon in upper layers called “CoolCube” (TM). Leading mobile chip supplier Qualcomm has been working with Leti on CoolCube R&D since late 2013, and based on preliminary results have opted to continue collaborating with the goal of building a complete ecosystem that takes the technology from design to fabrication.

“The Qualcomm Technologies and Leti teams have demonstrated the potential of this technology for designing and fabricating high-density and high-performance chips for mobile devices,” said Karim Arabi, vice president of engineering, Qualcomm Technologies, Inc. “We are optimistic that this technology could address some of the technology scaling issues and this is why we are extending our collaboration with Leti.” As part of the collaboration, Qualcomm Technologies and Leti are sharing the technology through flexible, multi-party collaboration programs to accelerate adoption.

Olivier Faynot, micro-electronic component section manager of CEA-Leti, in an exclusive interview with Solid State Technology and SemiMD explained, “Today we have a strong focus on CMOS over CMOS integration, and this is the primary integration that we are pushing. What we see today is the integration of NMOS over PMOS is interesting and suitable for new material incorporation such as III-V and germanium.”

The Table shows that CMOS over CMOS integration has met transistor performance goals with low-temperature processes, such that the top transistors have at least 90% of the performance compared to the bottom. Faynot says that recent results for transistors are meeting specification, while there is still work to be done on inter-tier metal connections. For advanced ICs there is a lot of interconnect routing congestion around the contacts and the metal-1 level, so inter-tier connection (formerly termed the more generic “local interconnect”) levels are needed to route some gates at the bottom level for connection to the top level.

“The main focus now is on the thermal budget for the integration of the inter-tier level,” explained Faynot. “To do this, we are not just working on the processing but also working closely with the designers. For example, depending on the material chosen for the metal inter-tier there will be different limits on the metal link lengths.” Tungsten is relatively more stable than copper, but with higher electrical resistance for inherently lower limits on line lengths. Additional details on such process-design co-dependencies will be disclosed during the 2016 VLSI Technology Symposium, chaired by Raj Jammy.

When the industry decides to integrate III-V and Ge alternate-channel materials in CMOS, the different processing conditions for each should make NMOS over PMOS CoolCube a relatively easy performance extension. “Three-fives and germanium are basically materials with low thermal budgets, so they would be most compatible with CoolCube processing,” reminded Faynot. “To me, this kind of technology would be very interesting for mobile applications, because it would achieve a circuit where the length of the wires would be shortened. We would expect to save in area, and have less of a trade-off between power-consumption and speed.”

“This is a new wave that CoolCube is creating and it has been possible thanks to the interest and support of Qualcomm Technologies, which is pushing the technological development in a good direction and sending a strong signal to the microelectronics community,” said Leti CEO Marie Semeria. “Together, we aim to build a complete ecosystem with foundries, equipment suppliers, and EDA and design houses to assemble all the pieces of the puzzle and move the technology into the product-qualification phase.”

Editor’s Note: In Solid State Technology’s November 1995 Asia/Pacific Supplement this editor wrote of the PRC’s status and plans for IC fabs titled “Progress creeps forward”. SEMICON/China 1995 was held in a small hall in Shanghai with 125 exhibitors and 5000 attendees discussing production of just 245M ICs units having happened in the entire country in 1994. Motorola’s Fab17 in Tianjin was planned to be able to yield 360M IC from 200mm wafers.

China has been successfully investing in technology to reach global competitiveness for many decades. Integrated circuit (IC) manufacturing technology is highly strategic for countries, enabling both economically-valuable commercial fabs as well as military power. The Wassenaar Arrangement (WA) between 40-some states has restricted exports to China of “leading” technology with potential “dual-use” by industry and military. Using the terminology of IC fab nodes/generations, WA has typically restricted exports to fab tools capable of processing ICs three nodes behind (n-3) the leading edge of commercial capability (https://en.wikipedia.org/wiki/14_nanometer). In 1995 the leading edge was 0.35 microns, so 1 micron and above was the WA limit. In 2015 the leading edge is 14nm, so 45nm and above is the WA limit, but local capability has already effectively bypassed this restriction.

On February 9, 2015, trade-organization SEMI announced (http://www.semi.org/en/node/54596) the successful lobbying of the U.S. Department of Commerce to declare the export controls on certain etch equipment and technology ineffective, thereby allowing US equipment companies to sell high-volume manufacturing (HVM) tools with capabilities closer to the leading-edge into China. Following years of discussion and negotiations, SEMI had submitted a formal petition for the Commerce Department’s Bureau of Industry and Security (BIS) to examine the foreign availably of anisotropic plasma dry etching equipment, having identified AMEC (amec-inc.com) as providing an indigenous Chinese manufacturing capability. AMEC has announced that it’s tool is being used by Samsung for V-NAND HVM (https://finance.yahoo.com/news/amec-ships-advanced-etch-tool-150000063.html), which is certainly a “leading-edge” product that happens to be made using 45nm node (n-3) design rules.

“The Future is in the Past: Projecting and Plotting the Potential Rate of Growth and Trajectory of the Structural Change of the Chinese Economy for the Next 20 Years” by Jun Zhang et al. from the Institute of World Economics and Politics, Chinese Academy of Social Sciences was first published online in 2015 (DOI: 10.1111/cwe.12098). Thanks to economic growth at an average speed of more than 9.7% annually in China over the past 35 years, it is estimated that today’s China per capital GDP has already reached approximately 23% of the USA. Because of the significant rise in per-capita income over the past 30 years, China has started to see a rapid demographic transition and a gradual rise in labor costs as seen in other high-performing East Asian economies. Benchmarking to the experiences of East Asian high-performing economies from 1950 to 2010, this paper projects potential growth rate of per-capita GDP (adjusted by purchasing power parity) for China at ~6.02% from 2015 to 2035.

The PRC still works with 5-year-plans. Figure 1 shows Deng Xiaoping touring a government-run fab during the 8th 5-year-plan (1991-1995) when central planning of local resources dominated Chinese IC industry. Paramount leader Deng had famously proclaimed, “Poverty is not socialism. To be rich is glorious,” which allowed for private enterprise and different economic classes. As reported by Robert Lawrence Kuhn in 2007’s “What Will China Look Like in 2035” in Bloomberg Business (http://www.bloomberg.com/bw/stories/2007-10-16/what-will-china-look-like-in-2035-businessweek-business-news-stock-market-and-financial-advice), researchers at the Institute of Quantitative & Technical Economics of the Chinese Academy of Social Sciences—the official government think tank housing more than 3,000 scholars and researchers—in 2007 predict that by 2030 China’s economic reform will have been basically completed, such that the major issue will be the “adjustment of interests” among different classes.

Figure 1: Deng Xiaoping is shown Shanghai Belling’s fab by General Manager Lu Dechun during the 8th 5-year-plan (1991-1995). Such small fabs are not globally competitive. (Source: Ed Korczynski)

In 2014, McKinsey&Company published proprietary research (http://www.mckinsey.com/insights/high_tech_telecoms_internet/semiconductors_in_china_brave_new_world_or_same_old_story) that >50% of PCs, and 30-40% of embedded systems contain content designed in China, either directly by mainland companies or emerging from the Chinese labs of global players. Since fewer chip designs will be moving to technologies that are 22nm node and below, low-cost Chinese technology companies will soon be able to address a larger part of the global market. Chinese companies will become more aggressive in pursuing international mergers and acquisitions, to acquire global intellectual property and expertise to be transferred back home.

Figure 2 shows that ICs represent the single greatest import cost for China, so there is great incentive to develop competitive internal fab capacity. The government, recognizing the failure of earlier centrally-planned investment initiatives, now takes a market-based investment approach. The target is a compound annual growth rate (CAGR) for the industry of 20%, with potential financial support from the government of up to 1 trillion renminbi ($170 billion) over the next five to ten years. To avoid the fragmentation issues of the past, the government will focus on creating national champions—a small set of leaders in each critical segment of the semiconductor market (including design, manufacturing, tools, and assembly and test) and a few provinces in which there is the potential to develop industry clusters.

Figure 2: The leading imports to China in 2014, showing that integrated circuits (IC) cost the country more than oil. (Source: China’s customs)

Global Cooperation and Competition

The remaining leading IC manufacturers in the world—Intel, Samsung, and TSMC—are all involved in mainland Chinese fabs. Intel’s Fab68 in Dalian began production of logic chips in 2010. Samsung’s Fab in Xian began production of V-NAND chips in 2014. TSMC has announced it is seeking approval to build a wholly-owned 300mm foundry in Nanjing (http://www.wsj.com/articles/taiwan-semiconductor-plans-to-build-chip-plant-in-china-1449503714), after rival UMC’s has invested in a jointly-owned foundry now being built in Xiamen.

“We do see significant growth, and a big part of that is due to investment by the Chinese government,” said Handel Jones of IC Insights during SEMICON Europa 2015. “Up to US$20B of government subsidy has been earmarked for IC manufacturing investment in China.” Jones forecasts that by 2025 up to 30% of global design starts will be in China, many to be designed by the ~500 fabless companies in China today. Jones estimates the total R&D investment in China today for 5G wireless technology is about US$2B per year, with about one-half of that just by Huawei Technologies Co. Ltd.

Due to the inevitable atomic-limits of Moore’s Law scaling, it is likely that the industry will have reached the end of new nodes in the next 20 years. By then, “trailing-edge” will include everything that is in R&D today, from quantum-devices to CMOS-photonic chips, of which it is highly likely that China will have globally competitive design and manufacturing capability. While today a net importer of ICs, by the year 2035 it seems likely China will be a net exporter of ICs.

Lei Zhang, et al. from Pennsylvania State University—with collaborators from Rutgers University and University of Toledo—have found two new families of transparent conductive oxides (TCO) based on “correlated” electrons in ternary oxides of vanadium. From reported first principles, the co-authors are confident they will find many other correlated materials that behave like strontium vanadate (SrVO3) and calcium vanadate (CaVO3), which could make flat panel displays (FPD) and photovoltaic (PV) modules more affordable.

The correlation relies on strong electron–electron interactions resulting in an enhancement in the carrier effective mass. Both SrVO3 and CaVO3 demonstrate high carrier concentration (>2.2 ×1022 cm−3), and have low screened plasma energies (<1.33 eV). The Figure shows that there is a transparency trade-off in using these new TCOs, since at nominal 10nm thickness they are more than twice as opaque as Indium tin oxide (ITO).

Optical transmission of free standing conductive oxide films at 550nm wavelength, accounting for reflection and interference, and averaged over the range of the visible spectra. (Source: Nature Materials)

ITO has been the dominant TCO used in FPD manufacturing, but the price of indium metal has varied over the range of $100-1000/kg in the last 15 years. Consequently, industry has long searched for a TCO made of less expensive and less variable direct materials. Currently vanadium sells for ~$25/Kg, while strontium is even cheaper. Lei Zhang, lead author of the Nature Materials article (http://dx.doi.org/10.1038/nmat4493) and a graduate student in assistant professor Roman Engel-Herbert’s group, was the first to recognize the application.

“I came from Silicon Valley where I worked for two years as an engineer before I joined the group,” says Zhang. “I was aware that there were many companies trying hard to optimize those ITO materials and looking for other possible replacements, but they had been studied for many decades and there just wasn’t much room for improvement.” Engel-Herbert and Zhang have applied for a patent on this technology.

The U.S. Office of Naval Research, the National Science Foundation, and the Department of Energy funded this R&D. “Now, the question is how to implement these new materials into a large-scale manufacturing process,” said Engel-Herbert. “From what we understand right now, there is no reason that strontium vanadate could not replace ITO in the same equipment currently used in industry.”

Electrons flow like a liquid

Correlated oxides are defined as metals in which the electrons flow like a liquid, unlike conventional metals such as copper and gold in which electrons flow like a gas. “We are trying to make metals transparent by changing the effective mass of their electrons,” Engel-Herbert says. “We are doing this by choosing materials in which the electrostatic interaction between negatively charged electrons is very large compared to their kinetic energy. As a result of this strong electron correlation effect, electrons ‘feel’ each other and behave like a liquid rather than a gas of non-interacting particles. This electron liquid is still highly conductive, but when you shine light on it, it becomes less reflective, thus much more transparent.”

In the November 2007 issue of the prestigious Physical Review B (DOI: 10.1103/PhysRevB.76.205110), F. Rivadulla et al. reported on “VO: A strongly correlated metal close to a Mott-Hubbard transition.” Vanadium oxide (VO) has a rocksalt cubic crystal structure, and displays strongly correlated metallic properties with non-Fermi-liquid thermodynamics and an unusually strong spin-lattice coupling. The structural and electronic simplicity of 3D monoxides provides a basic understanding of highly correlated electron systems, while this new work with 2D ternary oxides is inherently more complex.

One positive aspect of the more complex perovskite structure of SrVO3 and CaVO3 is that it provides for intriguing device integration possibilities with other functional perovskite materials. PV devices based on thin-films of complex perovskites have demonstrated excellent photon-electron conversion efficiencies in labs, but commercial manufacturing has so far been limited by the lack of an inexpensive TCO that can be integrated into a moisture barrier. The templating effect of underlayers could allow for faster deposition of more ideal SrVO3.

Industrial Technology Research Institute (ITRI) (https://www.itri.org.tw/) worked with TSMC (http://www.tsmc.com) in Taiwan on a clever in-line monitor technology that transforms liquids and automatically-diluted-slurries into aerosols for subsequent airborn measurements. They call this “SuperSizer” technology, and claim that tests have shown resolution over the astounding range of 5nm to 1 micron, and with ability to accurately represent size distributions over that range. Any dissolved gas bubbles in the liquid are lost in the aerosol process, which allows the tool to unambiguously count solid impurities. The Figure shows the compact components within the tool that produce the aerosol.

Semiconductor fabrication (fab) lines require in-line measurement and control of particles in critical liquids and slurries. With the exception of those carefully added to chemical-mechanical planarization (CMP) slurries, most particles in fabs are accidental yield-killers that must be kept to an absolute minimum to ensure proper yield in IC fabs, and ever decreasing IC device feature sizes result in ever smaller particles that can kill a chip. Standard in-line tools to monitor particles rely on laser scattering through the liquid, and such technology allows for resolution of particle sizes as small as 40nm. Since we cannot control what we cannot measure, the IC fab industry needs this new ability to measure particles as small as 5nm for next-generation manufacturing.

There are two actual measurement technologies used downstream of the SuperSizer aerosol module: a differential mobility analyzer (DMA), and a condensation particle counter (CPC). The aerosol first moves through the DMA column, where particle sizes are measured based on the force balance between air flow speed in the axial direction and an electric field in the radial direction. The subsequent CPC then provides particle concentration data.

Combining both data streams properly allows for automated output of information on particle sizes down to 5nm, size distributions, and impurity concentrations in liquids. Since the tool is intended for monitoring semiconductor high-volume manufacturing (HVM), the measurement data is automatically categorized, analyzed, and reported according to the needs of the fab’s automated yield management system. Users can edit the measurement sequences or recipes to monitor different chemicals or slurries under different conditions and schedules.

When used to control a CMP process, the SuperSizer can be configured to measure not just impurities but also the essential slurry particles themselves. During dilution and homogeneous mixing of the slurry prior to aerosolization, mechanical agitation needs to be avoided so as to prevent particle agglomeration which causes scratch defects. This new tool uses pressured gas as the driving force for solution transporting and mixing, so that any measured agglomeration in the slurry can be assigned to a source somewhere else in the fab.

TSMC has been using this tool since 2014 to measure particles in solutions including slurries, chemicals, and ultra-pure water. ITRI, which owns the technology and related patents, can now take orders to manufacture the product, but the research organization plans to license the technology to a company in Taiwan for volume manufacturing. EETimes reports (http://www.eetimes.com/document.asp?doc_id=1328283) that the current list price for a tool capable of monitoring ultra-pure water is ~US$450k, while a fully-configured tool for CMP monitoring would cost over US$700k.

In general, there is an accelerating trend toward System-in-Package (SiP) chip designs including Package-On-Package (POP) and 3D/2.5D-stacks where complex mechanical forces—primarily driven by the many Coefficient of Thermal Expansion (CTE) mismatches within and between chips and packages—influence the electrical properties of ICs. In this era, the industry needs to be able to model and control the mechanical and thermal properties of the combined chip-package, and so we need ways to feed data back and forth between designers, chip fabs, and Out-Sourced Assembly and Test (OSAT) companies. With accelerated yield ramps needed for High Volume Manufacturing (HVM) of consumer mobile products, to minimize risk of expensive Work In Progress (WIP) moving through the supply chain a lot of data needs to feed-forward and feedback.

Calvin Cheung, ASE Group Vice President of Business Development & Engineering, discussed these trends in the “Scaling the Walls of Sub-14nm Manufacturing” keynote panel discussion during the recent SEMICON West 2015. “In the old days it used to take 12-18 months to ramp yield, but the product lifetime for mobile chips today can be only 9 months,” reminded Cheung. “In the old days we used to talk about ramping a few thousand chips, while today working with Qualcomm they want to ramp millions of chips quickly. From an OSAT point of view, we pride ourselves on being a virtual arm of the manufacturers and designers,” said Cheung, “but as technology gets more complex and ‘knowledge-base-centric” we see less release of information from foundries. We used to have larger teams in foundries.” Dick James of ChipWorks details the complexity of the SiP used in the Apple Watch in his recent blog post at SemiMD, and documents the details behind the assumption that ASE is the OSAT.

With single-chip System-on-Chip (SoC) designs the ‘final test’ can be at the wafer-level, but with SiP based on chips from multiple vendors the ‘final test’ now must happen at the package-level, and this changes the Design For Test (DFT) work flows. DRAM in a 3D stack (Figure 1) will have an interconnect test and memory Built-In Self-Test (BIST) applied from BIST resident on the logic die connected to the memory stack using Through-Silicon Vias (TSV).

“The test of dice in a package can mostly be just re-used die-level tests based on hierarchical pattern re-targeting which is used in many very large designs today,” said Ron Press, technical marketing director of Silicon Test Solutions, Mentor Graphics, in discussion with SemiMD. “Additional interconnect tests between die would be added using boundary scans at die inputs and outputs, or an equivalent method. We put together 2.5D and 3D methodologies that are in some of the foundry reference flows. It still isn’t certain if specialized tests will be required to monitor for TSV partial failures.”

“Many fabless semiconductor companies today use solutions like scan test diagnosis to identify product-specific yield problems, and these solutions require a combination of test fail data and design data,” explained Geir Edie, Mentor Graphics’ product marketing manager of Silicon Test Solutions. “Getting data from one part of the fabless organization to another can often be more challenging than what one should expect. So, what’s often needed is a set of ‘best practices’ that covers the entire yield learning flow across organizations.”

“We do need a standard for structuring and transmitting test and operations meta-data in a timely fashion between companies in this relatively new dis-aggregated semiconductor world across Fabless, Foundry, OSAT, and OEM,” asserted John Carulli, GLOBALFOUNDRIES’ deputy director of Test Development & Diagnosis, in an exclusive discussion with SemiMD. “Presently the databases are still proprietary – either internal to the company or as part of third-party vendors’ applications.” Most of the test-related vendors and users are supporting development of the new Rich Interactive Test Database (RITdb) data format to replace the Standard Test Data Format (STDF) originally developed by Teradyne.

“The collaboration across the semiconductor ecosystem placed features in RITdb that understand the end-to-end data needs including security/provenance,” explained Carulli. Figure 2 shows that since RITdb is a structured data construct, any data from anywhere in the supply chain could be easily communicated, supported, and scaled regardless of OSAT or Fabless customer test program infrastructure. “If RITdb is truly adopted and some certification system can be placed around it to keep it from diverging, then it provides a standard core to transmit data with known meaning across our dis-aggregated semiconductor world. Another key part is the Test Cell Communication Standard Working Group; when integrated with RITdb, the improved automation and control path would greatly reduce manually communicated understanding of operational practices/issues across companies that impact yield and quality.”

Phil Nigh, GLOBALFOUNDRIES Senior Technical Staff, explained to SemiMD that for heterogeneous integration of different chip types the industry has on-chip temperature measurement circuits which can monitor temperature at a given time, but not necessarily identify issues cause by thermal/mechanical stresses. “During production testing, we should detect mechanical/thermal stress ‘failures’ using product testing methods such as IO leakage, chip leakage, and other chip performance measurements such as FMAX,” reminded Nigh.

Model but verify

Metrology tool supplier Nanometrics has unique perspective on the data needs of 3D packages since the company has delivered dozens of tools for TSV metrology to the world. The company’s UniFire 7900 Wafer-Scale Packaging (WSP) Metrology System uses white-light interferometry to measure critical dimensions (CD), overlay, and film thicknesses of TSV, micro-bumps, Re-Distribution Layer (RDL) structures, as well as the co-planarity of Cu bumps/pillars. Robert Fiordalice, Nanometrics’ Vice President of UniFire business group, mentioned to SemiMD in an exclusive interview that new TSV structures certainly bring about new yield loss mechanisms, even if electrical tests show standard results such as ‘partial open.’ Fiordalice said that, “we’ve had a lot of pull to take our TSV metrology tool, and develop a TSV inspection tool to check every via on every wafer.” TSV inspection tools are now in beta-tests at customers.

As reported at 3Dincites, Mentor Graphics showed results at DAC2015 of the use of Calibre 3DSTACK by an OSAT to create a rule file for their Fan-Out Wafer-Level Package (FOWLP) process. This rule file can be used by any designer targeting this package technology at this assembly house, and checks the manufacturing constraints of the package RDL and the connectivity through the package from die-to-die and die-to-BGA. Based on package information including die order, x/y position, rotation and orientation, Calibre 3DSTACK performs checks on the interface geometries between chips connected using bumps, pillars, and TSVs. An assembly design kit provides a standardized process both chip design companies and assembly houses can use to ensure the manufacturability and performance of 3D SiP.

SEMICON West includes many business and technology workshops and forums for attendees. On Wednesday morning July 15, attendees packed the TechXPOT in the South Hall of Moscone Center to hear updates on the status of flexible hybrid electronics manufacturing.

M-H. Huang of Corning showed the surprising properties of “Corning Willow Glass: Substrates for flexible electronic devices.” Willow Glass is created in a fusion-forming process similar to that used to create Gorilla Glass, though with thickness <=200 microns to allow for flexibility. “A key advantage is hermeticity compared to plastic substrates,” reminded Huang. Thin bare glass without any edge or surface coatings can be repeatably bent and twisted without cracking. The minimum bending radius for roll-to-roll (R2R) processing is limited by coating layer delamination: 12.5mm for bare glass, 25mm for AZO-coated glass, and 50mm radius for CZTS cells on glass all passing 500 bending cycles at 60 cycles per minute. Working with the State University of New York at Binghamton Center for Advanced Microelectronic Manufacturing (CAMM), Corning has demonstrated R2R sputtering of Al, Cr/Cu, ITO, SiO2, and IGZO films. Collaborating with ITRI in Taiwan using tools designed specifically for processing flexible glass, Corning demonstrated R2R gravure-offset printing of metal mesh structures silver ink that can be used for 7” touch-panels. Working with both CAMM and ITRI has led to R&D fabrication of a touch sensor with 90% device yield.

Thomas Lantzer, of DuPont Electronic Materials, discussed the “Materials Supplier Perspective on Flexible Hybrid Electronics.” Since the overarching goal of flexible electronics is not just mass and volume reduction but a huge reduction in manufacturing cost, it is axiomatic that fabrication must evolving toward the use of traditional printing methods and flexible substrates.

“There are many printing techniques,” explained Lantzer, “So there are building blocks out there today that we feel will lead to an explosion of fabrication capabilities in the future.” DuPont has been actively involve in flexible materials and electronics for decades, supplying screen printed conductive pastes, resistor pastes for automotive defoggers, flexible films, and flexible materials for copper circuitry.

Mark Poliks, Professor at the State University of New York at Binghamton and Director of the Center for Advanced Microelectronic Manufacturing (CAMM), provided a comprehensive overview of “Materials, Processes & Tools for Fabrication of Flexible Hybrid Electronics.” Working with partners in the Nano-Bio Manufacturing Consortium since 2013, CAMM researchers are developing a wearable disposable sensor system with a target price of $2 to measure human performance parameters. The device including sensors, processor, battery, and wireless communications blocks will be built with copper (Cu) connections on flexible substrates such as polyimide. Initial functionalities will include biometric parameters such as electro-cardio-gram (ECG) signals and skin temperature. First prototypes of ECG sensors on 12.5 micron thin polyimide have been completed, which demonstrate output wave forms with equal or better signal extraction compared to industry standard silver/silver-chloride (Ag/AgCl) electrodes. This new printed sensor and breadboard electronics can be flexed over 200 times and retain the same signal quality and heart-beat extraction. The flexible substrate can accommodate assembly processes for flip-chip (FC) ASIC dice having micro-bumps on a 70 micron pitch, using die-placement accuracy of 9 microns (3 sigma). For flexible hybrid applications, dual-sided placement of components along with printed circuitry reduces the real estate of the final packaged device.

After 15 years of targeted R&D, through-silicon via (TSV) formation technology has been established for various applications. Figure 1 shows that there are now detailed roadmaps for different types of 3-dimensional (3D) ICs well established in industry—first-order segmentation based on the wiring-level/partitioning—with all of the unit-processes and integration needed for reliable functionality shown. Using block-to-block integration with 5 micron lines at leading international IC foundries such as GlobalFoundries, systems stacking logic and memory such as the Hybrid Memory Cube (HMC) are now in production.

“There are interposers for high-end complex SOC design with good yield,” informed Eric Beyne, Scientific Director Advanced Packaging & Interconnect for imec in an exclusive interview with Solid State Technology. ““For a systems company, once you’ve made the decision to go 3D there’s no way back,” said Beyne. “If you need high-bandwidth memory, for example, then you’re committed to some sort of 3D. The process is happening today.” Beyne is scheduled to talk about 3D technology driven by 3D application requirements in the imec Technology Forum to be held July 13 in San Francisco.

Adaptation of TSV for stacking of components into a complete functional system is key to high-volume demand. Phil Garrou, packaging technologist and SemiMD blogger, reported from the recent ConFab that Hynix is readying a second generation of high-bandwidth memory (HBM 2) for use in high performance computing (HPC) such as graphics, with products already announced like Pascal from Nvidia and Greenland from AMD.

For a normalized 1 cm2 of silicon area, wide-IO memory needs 1600 signal pins (not counting additional power and ground pins) so several thousand TSV are needed for high-performance stacked DRAM today, while in more advanced memory architectures it could go up by another factor of 10. For wide-IO HVM-2 (or Wide-IO2) the silicon consumed by IO circuitry is maybe 6 cm2 today, such that a 3D stack with shorter vertical connections would eliminate many of the drivers on the chip and would allow scaling of the micro-bumps to perhaps save a total of 4 cm2 in silicon area. 3D stacks provide such trade-offs between design and performance, so the best results are predicted for 3DICs where the partitioning can be re-done at the gate or transistor level. For example, a modern 8-core microprocessor could have over 50% of the silicon area consumed by L3-cache-memory and IO circuitry, and moving from 2D to 3D would reduce total wire-lengths and interconnect power consumptions by >50%.

There are inherent thresholds based on the High:Width ratio (H:W) that determine costs and challenges in process integration of TSV:

- 10:1 ratio is the limit for the use of relatively inexpensive physical vapor deposition (PVD) for the Cu barrier/seed (B/S),

- 20:1 ratio is the limit for the use of atomic-layer deposition (ALD) for B/S and electroless deposition (ELD) for Cu fill with 1.5 x 30 micron vias on the roadmap for the far future,

- 30:1 ratio and greater is unproven as manufacturable, though novel deposition technologies continue to be explored.

TSV Processing Results

The researchers at imec have evaluated different ways of connecting TSV to underlying silicon, and have determined that direct connections to micro-bumps are inherently superior to use of any re-distribution layer (RDL) metal. Consequently, there is renewed effort on scaling of micro-bump pitches to be able to match up with TSV. The standard minimum micro-bump pitch today of 40 micron has been shrunk to 20, and imec is now working on 10 micron with plans to go to 5 micron. While it may not help with TSV connections, an RDL layer may still be needed in the final stack and the Cu metal over-burden from TSV filling has been shown by imec to be sufficiently reproducible to be used as the RDL metal. The silicon surface area covered by TSV today is a few percents not 10s of percents, since the wiring level is global or semi-global.

Regarding the trade-offs between die-to-wafer (D2W) and wafer-to-wafer (W2W) stacking, D2W seems advantageous for most near-term solutions because of easier design and superior yield. D2W design is easier because the top die can be arbitrarily smaller silicon, instead of the identically sized chips needed in W2W stacks. Assuming the same defectivity levels in stacking, D2W yield will almost always be superior to W2W because of the ability to use strictly known-good-die. Still, there are high-density integration concepts out on the horizon that call for W2W stacking. Monolithic 3D (M3D) integration using re-grown active silicon instead of TSV may still be used in the future, but design and yield issues will be at least comparable to those of W2W stacking.

Beyne mentioned that during the recent ECTC 2015, EV Group showed impressive 250nm overlay accuracy on 450mm wafers, proving that W2W alignment at the next wafer size will be sufficient for 3D stacking. Beyne is also excited by the fact the at this year’s ECTC there was, “strong interest in thermo-compression bonding, with 18 papers from leading companies. It’s something that we’ve been working on for many years for die-to-wafer stacking, while people had mistakenly thought that it might be too slow or too expensive.”

Thermal issues for high-performance circuitry remain a potential issue for 3D stacking, particularly when working with finFETs. In 2D transistors the excellent thermal conductivity of the underlying silicon crystal acts like a built-in heat-sink to diffuse heat away from active regions. However, when 3D finFETs protrude from the silicon surface the main path for thermal dissipation is through the metal lines of the local interconnect stack, and so finFETs in general and stacks of finFETs in particular tend to induce more electro-migration (EM) failures in copper interconnects compared to 2D devices built on bulk silicon.

3D Designs and Cost Modeling

At a recent North California Chapter of the American Vacuum Society (NCCAVS) PAG-CMPUG-TFUG Joint Users Group Meeting discussing 3D chip technology held at Semi Global Headquarters in San Jose, Jun-Ho Choy of Mentor Graphics Corp. presented on “Electromigration Simulation Flow For Chip-Scale Parametric Failure Analysis.” Figure 2 shows the results from use of a physics-based model for temperature- and residual-stress-aware void nucleation and growth. Mentor has identified new failure mechanisms in TSV that are based on coefficient of thermal expansion (CTE) mismatch stresses. Large stresses can develop in lines near TSV during subsequent thermal processing, and the stress levels are layout dependent. In the worst cases the combined total stress can exceed the critical level required for void nucleation before any electrical stressing is applied. During electrical stress, EM voids were observed to initially nucleate under the TSV centers at the landing-pad interfaces even though these are the locations of minimal current-crowding, which requires proper modeling of CTE-mismatch induced stresses to explain.

Planned for July 16, 2015 at SEMICON West in San Francisco, a presentation on “3DIC Technology Past, Present and Future” will be part of one of the side Semiconductor Technology Sessions (STS). Ramakanth Alapati, Director of Packaging Strategy and Marketing, GLOBALFOUNDRIES, will discuss the underlying economic, supply chain and technology factors that will drive productization of 3DIC technology as we know it today. Key to understanding the dynamic of technology adaptation is using performance/$ as a metric.

It is nearly certain that alternate channel materials with higher mobilities will be needed to replace silicon (Si) in future CMOS ICs. The best PMOS channels are made with germanium (Ge), while there are many possible elements and compounds in R&D competition to form the NMOS channel, in part because of difficulties in forming stable n-junctions in Ge. If the industry can do NMOS with Ge then the integration with Ge PMOS would be much simpler than having to try to integrate a compound semiconductor such as gallium-arsenide or indium-phosphide.

In considering Ge channels in future devices, we must anticipate that they will be part of finFET structures. Both bulk-silicon and silicon-on-insulator (SOI) wafers will be used to build 3D finFET device structures for future CMOS ICs. Ultra-Shallow Junctions (USJ) will be needed to make contacts to channels that are nanoscale.

John Borland is a renowned expert in junction-formation technology, and now a principle with Advanced Integrated Photonics. In a Junction Formation side-conference at SEMICON West 2014, Borland presented a summary of data that had first been shown by co-author Paul Konkola at the 2014 International Conference on Ion Implant Technology. Their work on “Implant Dopant Activation Comparison Between Silicon and Germanium” provides valuable insights into the intrinsic differences between the two semiconducting materials.

P-type implants into Ge showed an interesting self-activation (seen as a decrease in of p-type dopant after implant, especially for monomer B as the dose increases. Using 4-Point-Probe (4PP) to measure sheet-resistance (Rs), the 5E14/cm2 B-implant Rs was 190Ω/□ and at higher implant dose of 5E15/cm2 Rs was 120Ω/□. B requires temperatures >600°C for full activation in PMOS Ge channels, and generally results in minimal dopant diffusion for USJ.

Figure 1 shows a comparison between P, As, and Sb implanted dopants at 1E16/cm2 into both a Si wafer and 1µm Ge-epilayer on Si after various anneals. The sheet-resistance values for all three n-type dopants were always lower in Ge than in Si over the 625-900°C RTA range by about 5x for P and 10x for As and Sb. Another experiment to study the results for co-implants of P+Sb, P+C, and P+F using a Si-cap layer did not show any enhanced n-type dopant activation.

Prof. Saraswat of Stanford University showed in 2005—at the spring Materials Research Society meeting— that n-type activation in Ge is inherently difficult. In that same year, Borland was the lead author of an article in Solid State Technology (July 2005, p.45) entited, “Meeting challenges for engineering the gate stack”, in which the authors advocated for using a Si-cap for P implant to enable high temperature n-type dopant activation with minimal diffusion for shallow n+ Ge junctions that can be used for Ge nMOS. Now, almost 10 year later, Borland is able to show that it can be done.

Ge Channel Integration and Metrology

Nano-scale Ge channels wrapped around 3D fin structures will be difficult to form before they can be implanted. However, whether formed in a Replacement Metal Gate (RMG) or epitaxial-etchback process, one commonality is that Ge channels will need abrupt junctions to fit into shrunk device structures. Also, as device structures have continued to shrink, the junction formation challenges between “planar” devices and 3D finFET have converged since the “2D” structures now have nano-scale 3D topography.

Adam Brand, senior director of transistor technology in the Advanced Product Technology Development group of Applied Materials, explained that, “Heated beamline implants are best when the priority is precise dose and energy control without lattice damage. Plasma doping (PLAD) is best when the priority is to deliver a high dose and conformal implant.”

Ehud Tzuri, director strategic marketing in the Process Diagnostic and Metrology group at Applied Materials reminds us that control of the Ge material quality, as specified by data on the count and lengths of stacking-faults and other crystalline dislocations, could be done by X-Ray Diffraction (XRD) or by some new disruptive technology. Cross-section Transmission Electron Microscopy (X-TEM) is the definitive technology for looking at nanoscale material quality, but since it is expensive and the sample must be destroyed it cannot be used for process control.

Figure 2 shows X-TEM results for 1 µm thick Ge epi-layers after 625°C and 900°C RTA. Due to the intrinsic lattice mis-match between Ge and Si there will always be some defects at the surface, as indicated by arrows in the figure. However, stacking faults are clearly seen in the lower RTA sample, while the 900°C anneal shows no stacking-faults and so should result in superior integrated device performance.

Borland explains that the stacking-faults in Ge channels on finFETs would protrude to the surface, and so could not be mitigated by the use of the “Aspect-Ratio Trapping” (ART) integration trick that has been investigated by imec. However, the use of a silicon-oxide cap allows for the use of 900°C RTA which is hot enough to anneal out the defects in the crystal.

Brand provides an example of why integration challenges of Ge channels include subtle considerations, “The most important consideration for USJ in the FinFET era is to scale down the channel body width to improve electrostatics. Germanium has a higher semiconductor dielectric constant than silicon so a slightly lower body width will be needed to reach the same gate length due to the capacitive coupling.”

Junction formation in Ge channels will be one of the nanoscale materials engineering challenges for future CMOS finFETs. Either XRD or some other metrology technology will be needed for control. Integration will include the need to control the materials on the top and the bottom surfaces of channels to ensure that dopant atoms activate without diffusing away. The remaining challenge is to develop the shortest RTA process possible to minimize all diffusions.

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Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.

In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.

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