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AR# 51837

Design Assistant for Vivado Synthesis - Help with SystemVerilog Support - Connecting Modules and Interfaces

Description

This answer record describes SystemVerilog Connecting Module feature and Interface structures supported by Vivado Synthesis and also provides some coding examples for them. These coding examples are attached to this answer record. The answer record also contains information related to known issues and good coding practices.

Note: Each coding example can be used to directly create a Vivado project. Please refer to the header in each source file for the SystemVerilog constructs covered in each example

Solution

SystemVerilog Connecting Modules and Interfaces structures that are supported by Vivado Synthesis

Please refer to Table 1-1 at the end of this AR for the coding examples for the related coding examples.

1. Connecting Modules. Vivado Synthesis supports the following four ways to instantiate and connect modules.

by ordered list

by name

by named ports

by wildcard ports

2. Interfaces.Interfaces are a way of specifying communication between blocks. An interface is a group of nets and variables that are grouped together for the purpose of making connections between modules. Vivado Synthesis supports the following interfaces structures: