Verilog Programming part 23

Verilog Programming part 23

Examples In order to illustrate the use of behavioral constructs discussed earlier in this chapter, we consider three examples in this section. The first two, 4-to-1 multiplexer and 4-bit counter, are taken from Section

Nội dung Text: Verilog Programming part 23

7.9 Examples
In order to illustrate the use of behavioral constructs discussed earlier in this
chapter, we consider three examples in this section. The first two, 4-to-1
multiplexer and 4-bit counter, are taken from Section 6.5, Examples. Earlier, these
circuits were designed by using dataflow statements. We will model these circuits
with behavioral statements. The third example is a new example. We will design a
traffic signal controller, using behavioral constructs, and simulate it.
7.9.1 4-to-1 Multiplexer
We can define a 4-to-1 multiplexer with the behavioral case statement. This
multiplexer was defined, in Section 6.5.1, 4-to-1 Multiplexer, by dataflow
statements. It is described in Example 7-35 by behavioral constructs. The
behavioral multiplexer can be substituted for the dataflow multiplexer; the
simulation results will be identical.
Example 7-35 Behavioral 4-to-1 Multiplexer
// 4-to-1 multiplexer. Port list is taken exactly from
// the I/O diagram.
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
// Port declarations from the I/O diagram
output out;
input i0, i1, i2, i3;
input s1, s0;
//output declared as register
reg out;
//recompute the signal out if any input signal changes.
//All input signals that cause a recomputation of out to
//occur must go into the always @(...) sensitivity list.
always @(s1 or s0 or i0 or i1 or i2 or i3)
begin
case ({s1, s0})
2'b00: out = i0;
2'b01: out = i1;
2'b10: out = i2;

2'b11: out = i3;
default: out = 1'bx;
endcase
end
endmodule
7.9.2 4-bit Counter
In Section 6.5.3, Ripple Counter, we designed a 4-bit ripple carry counter. We will
now design the 4-bit counter by using behavioral statements. At dataflow or gate
level, the counter might be designed in hardware as ripple carry, synchronous
counter, etc. But, at a behavioral level, we work at a very high level of abstraction
and do not care about the underlying hardware implementation. We will design
only functionality. The counter can be designed by using behavioral constructs, as
shown in Example 7-36. Notice how concise the behavioral counter description is
compared to its dataflow counterpart. If we substitute the counter in place of the
dataflow counter, the simulation results will be exactly the same, assuming that
there are no x and z values on the inputs.
Example 7-36 Behavioral 4-bit Counter Description
//4-bit Binary counter
module counter(Q , clock, clear);
// I/O ports
output [3:0] Q;
input clock, clear;
//output defined as register
reg [3:0] Q;
always @( posedge clear or negedge clock)
begin
if (clear)
Q

endmodule
7.9.3 Traffic Signal Controller
This example is fresh and has not been discussed before in the book. We will
design a traffic signal controller, using a finite state machine approach.
Specification
Consider a controller for traffic at the intersection of a main highway and a country
road.
The following specifications must be considered:
• The traffic signal for the main highway gets highest priority because cars are
continuously present on the main highway. Thus, the main highway signal
remains green by default.
• Occasionally, cars from the country road arrive at the traffic signal. The
traffic signal for the country road must turn green only long enough to let the
cars on the country road go.
• As soon as there are no cars on the country road, the country road traffic
signal turns yellow and then red and the traffic signal on the main highway
turns green again.
• There is a sensor to detect cars waiting on the country road. The sensor
sends a signal X as input to the controller. X = 1 if there are cars on the
country road; otherwise, X= 0.
• There are delays on transitions from S1 to S2, from S2 to S3, and from S4 to
S0. The delays must be controllable.
The state machine diagram and the state definitions for the traffic signal controller
are shown in Figure 7-1.
Figure 7-1. FSM for Traffic Signal Controller
Verilog description
The traffic signal controller module can be designed with behavioral Verilog
constructs, as shown in Example 7-37.