Altera Offers First C-code-based DSP Design Flow for FPGAs

SAN JOSE, Calif., Sept. 4 /PRNewswire-FirstCall/ --
Altera Corporation (Nasdaq: ALTR) today announced the availability of the FPGA
industry's first C-code-based design flow for digital signal processing (DSP)
systems. This flow allows DSP software engineers to target programmable logic
devices (PLDs), without having to learn hardware description language (HDL),
thereby reducing the overall system cost and number of devices on their board.
"By offering the programmable logic industry's first C-code-based design
flow for DSP development, Altera opens the doors to a broad range of DSP
designers who wouldn't otherwise use FPGAs," said Ahmed Shihab, technical
director at Alcahest, a design consultancy active in the development of DSP
systems. "The combined capabilities of Altera's DSP Builder and SOPC Builder
tools offer significant benefits to the entire DSP development community,
allowing designers to use programmable logic for a wider range of DSP
applications."
Altera provides users with industry-standard software development tools
such as the GNUPro compiler and debugger, an open-source C/C++ development
tool suite optimized for the Altera(R) Nios(R) embedded processor. A key
feature of this new flow is the support of 'C' function calls for DSP hardware
accelerators, designed at the system level using The MathWorks' Simulink and
Altera's DSP Builder tools. Altera's comprehensive portfolio of more than
60 DSP intellectual property (IP) cores can be used as function calls for the
Nios processor. This complete system-on-a-programmable-chip (SOPC) design
flow is handled seamlessly by Altera's SOPC Builder tool, including the
integration of memory, communications peripherals, and processor busses.
"For software engineers who have traditionally used 'C' code to implement
their DSP designs with processors, using a familiar C-code-based design flow
to target FPGAs is a big advantage," said Justin Cowling, Altera's director of
intellectual property marketing. "Altera is providing customers with the
broadest and most cost-effective solutions based on Stratix(TM) devices, the
highly successful Nios processor, and parameterizable DSP IP cores."
Using IP cores as hardware accelerators instead of generic
multiply-accumulators (MACs) allows algorithms to be executed up to 20 times
faster. For example, a FIR filter that executes in one cycle on an FPGA can
take up to 20 cycles on a digital signal processor.
More information on the new C-code-based DSP design flow can be found on
the Altera web site at
http://www.altera.com/solutions/dsp/software/dsp-sof_index.html .
Pricing and Availability
Altera's complete C-code-based DSP design flow is supported now in DSP
Builder version 2.0 and SOPC Builder version 2.6. Subscription pricing for
Altera's DSP Builder version 2.0 is $1,995 and includes 12 months of software
upgrades. The DSP Builder tool is available for download for a free 30-day
evaluation from Altera's DSP Solutions Center at http://www.altera.com/dsp .
SOPC Builder version 2.6 is now integrated with Altera's Quartus(R) II version
2.1 design software, with subscription pricing of $1,995, including 12 months
of software upgrades. Simulink and MATLAB are available today from The
MathWorks at http://www.mathworks.com .
About the DSP Builder software
DSP Builder interfaces the industry-leading system-level design software
Simulink from The MathWorks with Altera's Quartus II design software. DSP
Builder provides a seamless design flow, allowing DSP engineers to design
algorithms in MATLAB, enabling system integration in Simulink and porting to
HDL for design in the Quartus II design software. Designers can automatically
generate an RTL design and RTL testbench from Simulink for quick timing and
simulation. Further easing the DSP engineer's transition to programmable
logic, DSP Builder also enables floating-point to fixed-point analysis. More
details about DSP Builder can be found on the Altera web site at
http://www.altera.com/products/software/system/sys-dspbuilder.html .
About the SOPC Builder software
SOPC Builder streamlines the process of integrating large blocks of IP and
accelerates development of complex SOPC designs. Designers can use the tool
to quickly combine system-level components such as embedded processors,
memories, peripherals, and user-created IP blocks to build their own custom
SOPC. For processor-based designs, SOPC Builder automatically generates
custom software development environments for each ARM(R) or Nios processor
included in the system. SOPC Builder is now integrated with Altera's Quartus
II design software, and ships automatically to all current registered Quartus
II software and Niosembedded processor subscribers. For more information on
SOPC Builder, visit http://www.altera.com/sopcbuilder .
About Altera
Altera Corporation is the world's pioneer in system-on-a-programmable-chip
(SOPC) solutions. Combining programmable logic technology with software
tools, intellectual property, and technical services, Altera provides
high-value programmable solutions to approximately 14,000 customers worldwide.
More information is available at http://www.altera.com .
NOTE: Altera, The Programmable Solutions Company, the stylized Altera
logo, specific device designations and all other words that are identified as
trademarks and/or service marks are, unless noted otherwise, the trademarks
and service marks of Altera Corporation in the U.S. and other countries.
Simulink is a registered trademark of The MathWorks. MATLAB is a trademark of
The MathWorks. ARM is a registered trademark of ARM Limited. All other
product or service names are the property of their respective holders.
CONTACT: Ami Dorrell of Altera Corporation, +1-408-544-6397, or
newsroom@altera.com.

SOURCE Altera Corporation

SAN JOSE, Calif., Sept. 4 /PRNewswire-FirstCall/ --
Altera Corporation (Nasdaq: ALTR) today announced the availability of the FPGA
industry's first C-code-based design flow for digital signal processing (DSP)
systems. This flow allows DSP software engineers to target programmable logic
devices (PLDs), without having to learn hardware description language (HDL),
thereby reducing the overall system cost and number of devices on their board.
"By offering the programmable logic industry's first C-code-based design
flow for DSP development, Altera opens the doors to a broad range of DSP
designers who wouldn't otherwise use FPGAs," said Ahmed Shihab, technical
director at Alcahest, a design consultancy active in the development of DSP
systems. "The combined capabilities of Altera's DSP Builder and SOPC Builder
tools offer significant benefits to the entire DSP development community,
allowing designers to use programmable logic for a wider range of DSP
applications."
Altera provides users with industry-standard software development tools
such as the GNUPro compiler and debugger, an open-source C/C++ development
tool suite optimized for the Altera(R) Nios(R) embedded processor. A key
feature of this new flow is the support of 'C' function calls for DSP hardware
accelerators, designed at the system level using The MathWorks' Simulink and
Altera's DSP Builder tools. Altera's comprehensive portfolio of more than
60 DSP intellectual property (IP) cores can be used as function calls for the
Nios processor. This complete system-on-a-programmable-chip (SOPC) design
flow is handled seamlessly by Altera's SOPC Builder tool, including the
integration of memory, communications peripherals, and processor busses.
"For software engineers who have traditionally used 'C' code to implement
their DSP designs with processors, using a familiar C-code-based design flow
to target FPGAs is a big advantage," said Justin Cowling, Altera's director of
intellectual property marketing. "Altera is providing customers with the
broadest and most cost-effective solutions based on Stratix(TM) devices, the
highly successful Nios processor, and parameterizable DSP IP cores."
Using IP cores as hardware accelerators instead of generic
multiply-accumulators (MACs) allows algorithms to be executed up to 20 times
faster. For example, a FIR filter that executes in one cycle on an FPGA can
take up to 20 cycles on a digital signal processor.
More information on the new C-code-based DSP design flow can be found on
the Altera web site at
http://www.altera.com/solutions/dsp/software/dsp-sof_index.html .
Pricing and Availability
Altera's complete C-code-based DSP design flow is supported now in DSP
Builder version 2.0 and SOPC Builder version 2.6. Subscription pricing for
Altera's DSP Builder version 2.0 is $1,995 and includes 12 months of software
upgrades. The DSP Builder tool is available for download for a free 30-day
evaluation from Altera's DSP Solutions Center at http://www.altera.com/dsp .
SOPC Builder version 2.6 is now integrated with Altera's Quartus(R) II version
2.1 design software, with subscription pricing of $1,995, including 12 months
of software upgrades. Simulink and MATLAB are available today from The
MathWorks at http://www.mathworks.com .
About the DSP Builder software
DSP Builder interfaces the industry-leading system-level design software
Simulink from The MathWorks with Altera's Quartus II design software. DSP
Builder provides a seamless design flow, allowing DSP engineers to design
algorithms in MATLAB, enabling system integration in Simulink and porting to
HDL for design in the Quartus II design software. Designers can automatically
generate an RTL design and RTL testbench from Simulink for quick timing and
simulation. Further easing the DSP engineer's transition to programmable
logic, DSP Builder also enables floating-point to fixed-point analysis. More
details about DSP Builder can be found on the Altera web site at
http://www.altera.com/products/software/system/sys-dspbuilder.html .
About the SOPC Builder software
SOPC Builder streamlines the process of integrating large blocks of IP and
accelerates development of complex SOPC designs. Designers can use the tool
to quickly combine system-level components such as embedded processors,
memories, peripherals, and user-created IP blocks to build their own custom
SOPC. For processor-based designs, SOPC Builder automatically generates
custom software development environments for each ARM(R) or Nios processor
included in the system. SOPC Builder is now integrated with Altera's Quartus
II design software, and ships automatically to all current registered Quartus
II software and Niosembedded processor subscribers. For more information on
SOPC Builder, visit http://www.altera.com/sopcbuilder .
About Altera
Altera Corporation is the world's pioneer in system-on-a-programmable-chip
(SOPC) solutions. Combining programmable logic technology with software
tools, intellectual property, and technical services, Altera provides
high-value programmable solutions to approximately 14,000 customers worldwide.
More information is available at http://www.altera.com .
NOTE: Altera, The Programmable Solutions Company, the stylized Altera
logo, specific device designations and all other words that are identified as
trademarks and/or service marks are, unless noted otherwise, the trademarks
and service marks of Altera Corporation in the U.S. and other countries.
Simulink is a registered trademark of The MathWorks. MATLAB is a trademark of
The MathWorks. ARM is a registered trademark of ARM Limited. All other
product or service names are the property of their respective holders.
CONTACT: Ami Dorrell of Altera Corporation, +1-408-544-6397, or
newsroom@altera.com.
SOURCE Altera Corporation