TAPE_OUT_4_FREE
(just add time and skill)
The following is mainly a visual cheat sheet on how to use
"iceditor'. The another Template file found else where on this
site
shows some other how-to details A bandgap with a CMOS inverter is used
here as an example to go from a Spice netlist, on
to a layout, then on to design rule checking (drc), then onto geometry
extraction, then on to layout vs schematic (LVS),
and lastly on to generating a GDSII stream file. Every file used
for all stages in this example is included in this one web page.

A lot of critical steps and details are required to convert a schematic
to a finished GDSII file. But hyperlinking can also capture
all the interrelationships. This web page organizes the big picture of
a full IC layout process in the order at which each stage
is performed . Hyperlinking allows quick navigation from any stage in
the big picture down to any critical detail at the smallest level.
The smallest details are usually what make the difference between
something working or not. But the big picture always needs to
be watched in order for all critical details to be completely
compatible with all the other critical details.

The ability to easily navigate between a macro view and micro view in a
web page has great potential. The following are
the manuals that come with "iceditor".

Navigating to critical details can become time consuming and
frustrating when using just these manuals. The problems usually
are simple, but finding out what to do about them is much more straight
forwardwhen
using a cheat sheet.

...Don Sauer 10/17/09
dsauersanjose@aol.com

=========DOWNLOAD_AND_INSTALL_ICED=======ClassicICEDInstall.exe=========Goto the following site

Any Process has if own set of layer definitions and ways to
recognize
the various geometry's.
A new LAYER
file defined the layer names,numbers, colors and calma numbers.
A new Design
Rule Check file
defines minimum and maximum spacing between all the layers.
A new EXTraction
file defines how to recognize all the geometry's from the layout.
The new LVS
file is a control file that sets the options on how to run the Layout Versus Schematic
checking program.
Working examples of these files are linked below.

The layout window is opened by calling out the StartUp_batch_File
and then a name of a "Cell".
If the Cell of that name does not exist in the directory, a new Cell
with that name is created.

ICBICMOSALL_GEOS

The easiest way to do a layout is to have Mimimum_Geometry_Cells for
all the transistors or resistors or capacitors
already laid out such the all the cells can be manually placed next to
each other and be DRC clean.
For example the cells for a NPN and a PNP are shown separately
below. These cell file mainly consist of
data points corresponding to rectangles. The file contents are shownhere and here.

These cells are designed so when the external isolation rings over lap,
the spacings are automatically DRC clean.

Variable Geometry's like resistors will need to be stepped in first as
a template cell.

Then the Resistor can be ungrouped and resized as needed. The
program will resize some
of the resistor's geometries which can be viewed here.

CMOS geometries often need to be resized too. It is common
practice to make geometries
such as NMOS
and PMOS
use the Poly defines the transistor size. A fast way
to start layout is to first layout all geometries to their intended
size. Knowing what size
things are helps in showing how things want to group together.

Layout of an IC is very much like drawing a schematic, except layout
cells replace schematic symbols.
In fact, layout is much like making a breadboard. First you collect all
the components. Then you
see how things want to be arranged. Make all all the geometries such
that when they butt up against each
other, the spacing is all correct. Label all the components to match
the schematic. Now just hook up
same as before, but use the metal layers in the layout.

Common Documentation in both the layout
and the schematic/netlist can be a real time saver.
To Label a Metal1 Node "GND" , select the layer and then add text.