San Francisco-based Methodics has been addressing both the enterprise data management and IP reuse/lifecycle management markets for over 10 years.

The company’s strategy of integrating their lifecycle management tools with products like Perforce version control software and Subversion from Apache, means they dovetail with industry standard solutions. As a natural outgrowth from that, Methodics’ IP-related offerings also work at the enterprise level, helping the customer’s distributed team coordinate and catalog IP use, and keeping track of third-party IP use as well.

In my recent phone call with Methodics CEO Simon Butler, it was clear the company is seeing the fruits of their many years of hard labor come to fruition.

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Q: How are things going with the company?

Simon Butler: We are doing very well, doubling our revenue and expecting to double that number again.

We are offering design data enterprise management and IP reuse capability to our customers. It’s taken a few iterations to perfect the system, but all along we’ve had the right concept and vision and have never wavered from that optimism.

The enterprise environment is a tough one, with a lot of infrastructure issues that are unique to each of our customers, compared to working with individual design teams. Yet at the same time, these customers have many problems in common.

Our new products really dial into each customer’s enterprise infrastructure and provide the solutions they need.

Q: In the past, it’s seemed the enterprise customer was under-served by the EDA and IP vendors. How did you decide to target this market?

Simon Butler: Yes, enterprise customers have unique needs. These are the types of customers who require a high-performance data base, and that connects them with our Percipient product.

To meet their needs, we have re-written the client’s infrastructure, and are providing a new infrastructure technology and appliances.

As a result, what we offer is an enterprise, a strong enterprise optimization product that reduces the amount of data needed [to find a solution].

Our other product addresses the IP quality management space. We’ve been basically executing massively parallel jobs, particularly for customers who are dealing with large blocks of IP.

Most importantly, in the last few months we are definitely taking customers away from our competition. So, of course, we feel that things are going great!

Q: Who is your competition?

Simon Butler: Rather than answer that, let me just say there will be a press release coming out in the near future that will be a joint marketing opportunity between Methodics and an important new customer, who previously was engaged with our competition.

Q: Yours seems like a unique type of technology from the point of view of IC design, and one that requires developments skills from someone other than a hardware engineer. Where do you find new employees? From the IT industry, from the IP industry?

Simon Butler: We’ve been hiring systems engineers folks, not just people with an EDA background.

We need people who know how to scale our tools over busy networks in often hostile conditions. Enterprise software development is very different to EDA tools development and bring a new set of problems.

Q: Do they need to understand the complexities of chip design or IP development?

Simon Butler: Certainly that helps but it’s more important that they understand how to manage complex libraries of data, version control, design iterations, traceability, etc.

Interfacing with other design tools and databases is also important. That’s what our platform enables so understanding how each piece of data is designed is not necessarily as critical as knowing how to keep it all organized, up to date and accessible

Q: Data management and design have moved to the Cloud in what some might call a mad-cap manner – trusting the Cloud to not mess things up and have perfect security. Are your tools in the Cloud, and how do you guarantee secure access to your customer’s nascent designs and IP blocks?

Simon Butler: We do have a Cloud “strategy”, but frankly most of our customers prefer to host the kind of data that we manage locally to minimize the possibility of theft. For our customers, the better solution is to take the Cloud to them and install on their network, and data centers.

Q: Speaking of security, it must take a great deal of trust for a customer to allow your software to integrate with their tools. How do you reassure customers that your software is secure enough?

Simon Butler: Our tools are as secure as the environments in which they are being used, which in the case of world-class semiconductor companies is pretty secure. We don’t expose their data or IP to any additional risks.

Q: As the huge semiconductor companies further consolidate, does it create opportunities or difficult challenges for Methodics. Are those customer more likely to resort to in-house solutions for version control and/or IP reuse management?

Simon Butler: Actually, it probably helps us as we address one of the biggest problems companies or organizations have when they combine. They need to standardize on a common platform and methodology to manage design data, and also deal with distributed design teams.

When a merger or acquisition happens, there’s always a lot of legacy IP and design data to deal with, so we can help bring some structure and organization to what often is a very complex situation.

We actually get a lot of traction with companies that have been through a recent merger or acquisition and are looking expedite the transition. Discovering design assets across the corporate entities and making it easy for the two teams to collaborate helps maximize the value of the M&A

Q: Are all of your customers IC design houses? Could your tools also be used by industries completely unrelated to IC design and IP reuse?

Simon Butler: At the moment, all of our customers are involved in electronic design of some sort, and our core value is in the area of IC design.

But our core competency is in managing design data, which could be applied to other areas where there are a lot of moving parts, like design reuse and exchange, design iterations, and disparate engineering teams.

Software development, for example, or games design. The nuances are slightly different, but the general concepts are similar from a design management point of view.

Q: How did you decide to locate the company in San Francisco?

Simon Butler: We hire a mix of experienced software developers and interns/new-grads. San Francisco is a center of excellence for these kinds of folks and fosters innovation.

Q: Do you have to travel a lot to interface with customers?

Simon Butler: Our customers are in the typical locations where most EDA customers are, and its important to have relationship with the key decision makers and influencers. So yes, travel is part and parcel with building a company like ours.

Q: You’ve been in business for over 10 years. What’s the exit strategy?

Simon Butler: We don’t think about that much, to be honest. We’re proud of our longevity and think it demonstrates the importance of what we are providing to the IC design market.

Being in the EDA space, there are some pretty well proven ways we could go in terms of an exit or new business direction – acquisition or merger with another EDA company, acquisition by large customer, combine with another like-minded but possibly tangential company, or even an IPO.

We are certainly aware of all those options, but for now we are focused on the business at hand of developing great products and meeting our customers’ needs

Q: Why belong to the ESD Alliance?

Simon Butler: We believe electronics design at all levels is all about the ecosystem, and the ESD Alliance is a good forum for the range players involved in the EDA and IP sector to interact.

I don’t know of any EDA customer that uses a single vendor, so we have to be collaborative as result of market requirements. The ESD Alliance makes that a bit easier, and also provides a platform for discussion of important issues, trends and standards that impact all suppliers in this value chain.

It gives everyone a voice, regardless of their size or focus area.

Q: It seems like many, if not all, of the companies in the ESD Alliance are potential customers. Is that additional motivation for belonging to the Alliance?

Simon Butler: Actually, a lot of them are partners. As a provider of a data and IP management platform, we have to work with all the major tool suppliers to ensure compatibility for our mutual customers.

We have to be a Switzerland in terms of being agnostic about design environments and working with everyone.

Q: What conferences are important to Methodics?

Simon Butler: The major IC design shows are important – DAC, of course – and we tend to work with the major suppliers like Cadence and Mentor around their big user events.

We are also looking at more focused shows in certain market segments, like automotive, and are also looking at PLM types of events.

Q: What is the best part of your job?

Simon Butler: Building something valuable and being part of a great team. That’s what gets me up in the mornings.

Butler has held various technical lead and engineering management positions at High Level Design Systems (acquired by Cadence), Sandcraft, Cadence, Sabio Labs (acquired by Magma). He is a graduate of the University of Manchester.
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Hangzhou C-SKY Microsystems, a 32-bit CPU vendor, became a member of the ESD Alliance in 2016 and was described at the time as “the first IP company from China to join.”

Founded in 2001, C-Sky has “developed 7 types of embedded CPUs covering a wide range of embedded applications including smart devices in IoT, digital audio and video, information security, network and communications, industrial control and automotive electronics. It is the only embedded CPU volume provider in China with its own instruction set architecture, the Yun-on-Chip architecture developed in conjunction with Alibaba.”

C-Sky is a growing IP company serving an enormous market. I spoke recently by phone with Dr. Xiaoning Qi, CEO at C-Sky, who was in California attending meetings. No stranger to Silicon Valley, he previously served at Intel, Rambus, Synopsys, and Sun, after completing his Ph.D. under Prof. Robert Dutton at Stanford.

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WWJD: How has your trip gone so far?

Xiaoning Qi: Very well. We presented our technology for IoT security at the IoT Device Security Summit [co-located with 2017 IoT DevCon]. I also attended the GSA Executive Summit on Tuesday in Menlo Park.

WWJD: What have you learned from these meetings?

Xiaoning Qi: From comments at the GSA meeting, where there were talks about AI, I learned that 5G is very exciting. And the keynote at the summit talked about opportunities in the future in China. It’s a particularly interesting world right now.

WWJD: How is C-Sky doing?

Xiaoning Qi: Very well. We received investment from Alibaba early last year, although we’ve been working on our R&D for a long time, our fundamental technology.

Right now, we continue to work on R&D, but at the same time we are going out and letting the company be known to the world. We are also ramping up sales and marketing, helping our customers realize their goals in the IoT market.

Additionally, yesterday in Beijing, we released the first secure NB-IoT [Narrow Band Internet of Things] chip, designed by ZTE and manufactured in China by SMIC.

WWJD: Has there been good response to that news?

Xiaoning Qi: Yes, and there was a release ceremony in Beijing. My CTO was there. If I hadn’t had a meetings previously scheduled here in California, I would have been there as well.

WWJD: Any announcements at DAC in Austin?

Xiaoning Qi: At DAC, I was on a panel where we talked about future of the IoT and semiconductor markets in the US, China, and in the world. It was very informative.

WWJD: What is the future of the semiconductor market in China?

Xiaoning Qi: China consumes currently at least one-half of all semiconductor products in the world. In the future, that percentage will go up and markets there will continue to grow. The IoT market in China is booming, because the population is there to support it.

WWJD: Do you think IoT will continue to depend on the older nodes?

Xiaoning Qi: Yes, most IoT will stay in the older technologies because of the cost. If you look at sensors, for instance, they are selling at a very cheap price. The [people who use them] can’t afford to use advanced technology which is much more expensive.

[Having said that], a customer just developed a chip for a surveillance camera using our CPU with a vision processor and manufactured at 28 nanometers. But for most IoT devices, the older nodes are [sufficient].

WWJD: Would edge devices be better at smaller technology nodes?

Xiaoning Qi: When those nodes become cheaper, it will be more cost-effective and that’s when people will move into those areas. If Moore’s Law goes forward, the density of transistor doubles and then why not?

WWJD: Is the IoT market just one market, or is it harder to describe than that?

Xiaoning Qi: [laughing] Yes, it is hard to describe. It actually [consists of] lots of future markets, although we are not quite sure about the profit part.

For our company, there are two things of interest. We’ve been involved in the traditional embedded market: smart cars, surveillance, printers. We are [addressing] surveillance with our CPUs, vision and video, and how to enhance edge devices for AR.

We are also working with Alibab on IoT for the future: How to connect the Cloud and edge devices, how to get analytics safely and efficiently from a powerful Cloud to the edge devices. All of these things are in the early stages for us, and we are working hard.

WWJD: Why is there any doubt about the profitability of the IoT market?

Xiaoning Qi: I believe there are two things that may [cause concern].

The IoT market spans everything from industrial to medical and consumers – all sorts of areas – but these areas are very much fragmented. They ‘inherited’ that situation from the embedded market.

The profitability of each market is actually very low, and the lifetime of the products is very short, so the chip designers are not quite sure they want to get into this market.

Typically for chips, you need high volumes [to succeed], but IoT chips are only [being produced] in the tens of thousands, which is quite small.

So the IoT market is fragmented, small volume, and short life cycle. Chip designers are not happy there.

WWJD: Will the IoT market be slow to develop as a result?

Xiaoning Qi: Yes, it will be slow. But from the technology perspective, it will move quickly.

First, we are trying to build an ecosystem, thinking about hardware and software together. As hardware providers, CPU providers, we cannot work on hardware alone. We need to work on the two together, we would like to build an ecosystem with our CPUs and our OS.

In the Wintel world, it is Intel and Microsoft. In the embedded world, it is ARM plus iOs, or ARM plus Android.

In our world, we [are working towards] Alibaba and our embedded OS, coupled with our CPUs. We would like to build such an ecosystem, at least for the Chinese market. From our perspective, we would then be able to build a good IoT market.

Second, from a technical perspective, we are building a unified architecture for the IoT market. We have the basic hardware and have built an abstract level for this hardware. Above that, there’s an operating system. We then build another layer of abstraction above the OS, and then the applications for the [various] domains.

The engineers or developers for a specific domain don’t need to understand the basics of the embedded OS. They just see the unified hardware and software platform. This is how we are trying to solve this ‘fragmented market’ problem.

WWJD: Hardware/software co-design has been a challenge for a long time.

Xiaoning Qi: Yes, but in EDA when we talk about hardware/software co-design, it’s different from what I’m talking about in the context of embedded IoT. Here it’s the more fundamental basics of operating system and computer architecture.

WWJD: I would argue they are the same, an attempt to develop the hardware in conjunction with the software to create a seamless end product.

Xiaoning Qi: Yes, that’s a good point.

And it’s from that perspective that we have worked closely with the Alibaba team. We own the architecture and know how to fit this into the operating system. They understand how to change the OS part to fit into a particular architecture. People working together like this can make a very seamless integration.

For us as a CPU IP company, half of our engineers are on the software side, developing design tools and a design environment – all of these to build the expertise for our hardware development.

WWJD: It seems very exciting.

Xiaoning Qi: Yes, it is.

And on the business side, we also would like to think like a software company, something we are learning how to do.

WWJD: How does a software company think?

Xiaoning Qi: The software guys can make a change very fast, and then try different solutions. If one doesn’t work, they fix it and go forward until it is released.

For hardware, [the process] is different. We have to keep up a fast pace as well, but the silicon takes a longer design cycle. We would like to [be able] to adjust the hardware and then tune the software at the same time.

When we do silicon design for the IoT market, for example, we need to provide value beyond the silicon. We need to provide the software stack, and ultimately for the IoT market, provide a solution and a service.

This is how it works for us when we collaborate with Alibaba, an online company with huge amounts of data. When we have the good IoT devices [we are developing], we can work on software integration through the Cloud. The Cloud will then be much richer, and will enable us to bring more customers to our products.

WWJD: What is the goal of a Cloud-based system connected to a billion edge devices?

Xiaoning Qi: To be able to send all that data into the Cloud, and to have access to huge analytics, to have the analysis done in the Cloud.

For example, for the Smart City, we need lots of sensors, lots of traffic information, sent to the Cloud. Then we need to process that data and make a proposal as to which road is best, which traffic lights to adjust, and eventually which roads to build or make wider.

WWJD: These billion edge devices will allow us to optimize the Smart City?

Xiaoning Qi: If the edge device is strong enough, the response will be that much faster. Strong edge devices process data without much latency, and react much faster that way.

For drones, for cars, for all these applications, using strong edge devices is the solution.

Xiaoning Qi: Yes, but embedded CPUs in printers, for example – versus those in Smart Cars – do not need to be so intelligent.

They don’t need vision processors or facial recognition. They [represent] traditional embedded processors, which is also true for industrial controllers. Manufacturing machines can be controlled using traditional embedded processors.

WWJD: Which edge devices need to be very intelligent, to be very strong?

Xiaoning Qi: The vision processors in autonomous driving systems.

WWJD: So strong that the car can make its own decision without consulting with the Cloud?

Xiaoning Qi: That’s right.

Last year at a GSA meeting, there was a talk from a company that can collect data from the car to the Cloud, and back again. They claimed they had the latency under control. I thought it was good technology, but sometimes you have to make a decision in a tenth of a second, whether to hit another car or hit a pedestrian that is suddenly in front of you.

WWJD: Historically, we have relied on intelligent human reflexes to make that decision.

Xiaoning Qi: Yes, but the machine will soon be smarter than that.

WWJD: On the business side, where are the bulk of your customers?

Xiaoning Qi: They are mostly in China.

WWJD: Why belong to the ESD Alliance?

Xiaoning Qi: It is very helpful for us to know the world.

And we enjoy it because the organization used to be for EDA only. I worked with Synopsys for a number of years, and my adviser was Bob Dutton, so I was there when it was EDAC. I was always amazed at an organization where I could meet visionaries and many interesting people.

Recently, they added IP into the vision of [what EDAC was] and ARM joined. So for us as an IP company, it was also important to learn. We would like to learn from the big guys in the group.

WWJD: Are there topics you would like to see the ESD Alliance address?

Xiaoning Qi: Yes, we would like sessions with more information about IP.

I did attend an IP industry event, which was good, with good speakers. The exhibition was good and the vendors, we all had a chance to talk with each other.

Also, I have been able to meet some people in China working in IP. Bob Smith [Executive Director] has asked me to broadcast to these people the value of belonging to the ESD Alliance, and I said I would be happy to help.

WWJD: How many IP companies are there currently in China?

Xiaoning Qi: There are four.

WWJD: Isn’t it interesting to see Synopsys and TSMC emerge as major players in the IP market, companies that are not just IP companies.

Xiaoning Qi: In EDA, the profit margin in high. But when you compare EDA companies to the semiconductor industry, EDA is only $5 billion in total.

That is so small, companies like Synopsys, and TSMC, made a good move to go into the IP world, because there is more value there than just in tools. Chi-Foon Chan and Aart de Geus made the right decision there, because currently IP is half of Synopsys’ revenue.

For the foundries to go into the IP business also makes sense. In manufacturing, they need to have standard cells and libraries, so they can provide IP to their customers.

This puts the foundry in a better position to help their customers, because the IP would already be proven, for instance, in a TSMC process technology. I think now SMIC is doing the same thing.

WWJD: Also a business issue, how do you find new employees?

Xiaoning Qi: That’s actually an interesting and touchy question. We are a small company and have to compete with large companies for employees, competing in salary and life-work balance.

Typically in small companies that don’t have a lot of people, employees have to wear a lot of hats, but we have big dreams. We have to compete with Huawei and Alibaba for employees. But people come to work for us not just for the salaries, but to pursue the big dream. Yes, it’s a challenge to recruit.

WWJD: Do you ever recruit out of Stanford or Berkeley?

Xiaoning Qi: Right now, no. But some people studying here would like to work in China, would like to move back to work there.

WWJD: After your long years working here, have you moved back to China?

Xiaoning Qi: Yeah, I spend most of my time there now, although I’m also traveling a lot.

WWJD: Do you recall something funny that has happened to you in your career?

Xiaoning Qi: Not so much funny as interesting, perhaps. When I was an EE student at Stanford, electrical engineering jobs were very high profile and interesting.

But the semiconductor industry peaked in 2000, and although it was still very exciting to work in the hardware area, people found out that the industry peaked and they graduated started talking about it as a sunset business, one that was [in decline].

But I was always kind of optimistic, so I was thinking something must come along to rescue us. So then there was the IoT market, and now here we are.

WWJD: Your optimism seems to be an important part of your business model.

Xiaoning Qi: [laughing]. It think that’s right.

Since I was Chairman of the Chinese American Semiconductor Professional Association, Chenming Hu of Berkeley has been our honorable adviser. He told me that there are at least 100 years left for the semiconductor industry, and when I asked him if he was serious, he said yes.

In a similar way, when I was at Stanford some people thought the semiconductor industry would become the next steel industry. There is no more need for the technology itself to develop further, because we know that as a lot of industries becomes mature, we can still use the technology to build things. Applications are very important.

Right now, semiconductors are everywhere, in your home, in your pocket. The semiconductor industry is mature, but with a long future.

Subhasish Mitra is a professor at Stanford. We graduated the same year and are very good friends. He recently published a paper in Nature that looked at the whole [ecosystem] in semiconductors. He said there, we don’t need to have 7 nanometers, or 5 or 4, because memory is the problem.

He said CMOS [for logic] and nanotubes will solve the memory problem, so he is working on the more fundamental technologies. It’s very exciting. When I saw him recently, I said I would like to be one of his graduate students and be doing this work.

WWJD: Given your background, why do an IP company, and not an EDA company?

Xiaoning Qi: I know EDA, because I worked for some time on that side, and I know why people want to develop a tool that is more interesting. If you do EDA and make a tool, design is easier.

But the fact is, we really need a visionary in the EDA industry to come out with a new business model that will change the situation in EDA, moneywise.

I once asked Wally Rhines why EDA revenues are so small compared to the semiconductor industry. He said it’s because anyone with a computer and a brain can start an EDA company, but you need much more to do a semiconductor company.

So again, while I was looking at EDA and the people who design the tools, I was thinking to create something in terms of design itself. My thought was that working on the design would be more exciting.

Also, to do an EDA tool you can be a computer science guy, but I studied electrical engineering. An EE understands which devices you want to optimize, and although people with CS backgrounds may be very good at algorithms – speeding up calculations and simulations – to solve the right problems in design, you need an EE background.

Designers get my utmost respect, which is why I decided to work in IP.

****************Bio …

Xiaoning Qi is CEO of C-Sky Microsystem Corp. Previously he held senior management and technical positions in Intel, Rambus, Synopsys and Sun Microsystems in California, working on IC devices, micro-processor design, and platform electrical design for semiconductor systems.

Xiaoning Qi is a member of Asia-Pacific Leadership Council, Global Semiconductor Alliance (GSA), and was chairman and president of Chinese American Semiconductor Professional Association. He has published more than 50 technical papers, one book, one book chapter and eighteen invited talks, and holds two US patents. He is also a reviewer for numerous IEEE journals and international conferences, and a senior member of IEEE.

Xiaoning Qi received his Ph.D. degree in Electrical Engineering from Stanford University in 2001.

But this is not about Sage, it’s about how Sage fits into an evolving industry from the point of view of Raul Camposano, EDA veteran, former CTO at Synopsys, and currently CEO at Sage. Like so many serving in leadership roles in the industry, Dr. Camposano is a man of good cheer and an optimistic observer.

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WWJD: How are things going?

Raul Camposano: Well, I have just stepped out from the events today at the TSMC ecosystem event. This is a fine show, well attended, with both EDA and IP tracks. It is always very interesting. TSMC, of course, is the gorilla in the industry, so it is attended by a lot of people. A mini-DAC, if you will.

WWJD: How is Sage doing?

Raul Camposano: Quite well. We have tools that do QA on decks from design rule checks. And we’re getting good traction in the market. QA is important because the decks today are so complicated. And we must have good decks. They can include from a few thousand to several thousand rules today.

Remember that even a good programmer will [introduce] 3-to-10 bugs per 1000 lines of code, so if the deck has 50,000 lines of code, that’s 50-to-100 bugs, unless you do QA on the code.

And as the nodes increases, there are even more design rules, and the value of those rules increases, which is why we are getting traction.

WWJD: Why don’t the people who produce the DRC decks do their own QA, the foundries, etc.?

Raul Camposano: They do have internal test patterns to check the design rule deck, but that is often done by hand, not with scripts. When you have just a few rules [that process] is adequate, but it becomes very error prone with many rules. We are automating something that has [traditionally] been done by hand.

Yes, the people who write the rules do their own QA, and that’s okay, but with very complex software you need more. You need tools that look for the bugs.

WWJD: Why the name Sage for the company?

Raul Camposano: Because, like in most disciplines in EDA, you want knowledge. The question we address is who checks the checker?

If the person who creates the DRC decks also does the checks, they’ll make the same mistake twice.

Back when I was at Synopsys, if you wanted to check the outcome of synthesis, you had to ask: How do you know we’re not using the same algorithm as synthesis to do the check?

People like it when there are two different approaches. It’s like having an auditor AND an external auditor, to check the books.

WWJD: Who are your customers?

Raul Camposano: We have 10 customers, although some of them don’t like to be named.

We have some major foundries, some memory companies, which are very good applications for what we do, and we have some smaller foundries where our tools can actually can be run in older nodes.

Raul Camposano: Yes, that’s true to a large extent, but as you do newer chips with them, you have newer devices and possibly new problems.

And the rules come in several different flavors: There’s one set of rules for the process itself, and a different set of rules for the devices that need to have a certain capacity. For instance, this particular transistor needs to be a minimum size. If it’s smaller, it will fail.

So even if they are older nodes, the number of variations in these processes are pretty big. Particularly if you’re a larger customer, there something that’s likely to be tweaked.

That’s the funny thing with the slowing down of Moore’s Law, and the slower adoption of the newer nodes: Where before everybody automatically went for the new node for the [benefits of] power, cost and speed, now there are lot more variations [in needs], so there are many more design rules.

WWJD: It seems like there should be a different set of design rules for every single design.

Raul Camposano: [laughing] Actually, I have heard this is the case, particularly if you’re a big customer.

And I’ve also heard that is true for memory, because you’re pushing the technology to the limits and, because there’s such a big return, you’re going to replicate this billions of times and need to be confident.

WWJD: Is Moore’s Law dead?

Raul Camposano: Not dead, but just much more complicated.

Academia says it’s Denard scaling. Now every time you want to scale below 64 nanometers, there’s a lot of innovation needed. So you have to choose a different type of transistor, a finFET, or a high-k dielectric. In that sense, Moore’s Law is dead. But we will still go to 5 and 3 nanometers, so it will go on for a little bit longer.

The most exciting things, the thing most talked about, is 3D IC. We’ve learned how to stack things.

And Flash is key. There’s a whole slew of new memories, magnetic memory, and the new 3D XPoint memory from Intel. There’s a lot of innovation going on right now.

WWJD: And a lot of opportunities for young engineers?

Raul Camposano: Yes, the opportunities are alive and well.

My hobby is Silicon Catalyst. This is a bunch of people who are industry veterans, who got together to do an incubator for startups to do chips. We are seeing many, many companies – over 150 in that space.

Our group is asking: Why is so difficult to do a chip?

The problem is you have to spend $50 million to see a chip. Although, if you’re trying to do software, it’s only $50,000 to $100,000.

Part of the cost of the chip is the complexity, but the IoT means a lot less complexity at the edge, so those costs should be lower and there are more opportunities [for startups in that space].

Silicon Catalyst partners with TSMC and Synopsys, who give their tools for free to startups for a certain period of time. The startups don’t have to pay for expensive tools [at the beginning], which lowers the cost of entry.

WWJD: Are you saying EDA tools are too expensive?

Raul Camposano: [laughing] You get what you pay for.

WWJD: Is there more interest in IoT because it utilizes the older nodes?

Raul Camposano: I’m a believer in the market. All the push in the semiconductor industry would actually do something IF there’s real need for it. You reach a certain technical threshold, and then things happen.

Look at speech recognition: AI that is deployed for many, many things – fraud detection, to determine what movie you like, shopping patterns, face recognition. All of that is working because there’s enough computer power that’s cheap enough.

But if you say IoT, you need communication, the stack for WiFi or cellular network. And that’s so cheap and commoditized, along with a micro-controller, you can actually do something useful with it.

One of my favorite examples: Consider the billions of engines that power everything. If they break, they need repair. But if each engine had a little sensor that would make a noise before the engine broke, you would know exactly when it would fail.

So if an IoT device could have a cheap, long-term battery, each engineer would have a little expert system embedded in the big, expensive engine, so they would know from the IoT device when it was about to break.

These are the types of things that are enabled by technology. We can produce small systems to monitor bigger systems.

WWJD: Small, cheap devices to monitor big, expensive ones?

Raul Camposano: [laughing] Yes!

WWJD: Given your background helping to document the history of EDA, what should somebody read if they were going to sit down and read for a month to understand it all.

And there are a bunch of text books, one by Kurt Keutzer and one by Nani De Macheli. And I actually wrote one, but it’s in German, that gives a good overview of how things are done. In terms of history, there are two books by Dan Nenni. They’re not technical, but they’re entertaining to read.

All of these books would cover about a month’s worth of reading.

WWJD: You wrote a textbook in German?

Raul Camposano: [laughing] It was a long, long time ago.

WWJD: Speaking internationally, what happens to the industry if the US closes its borders?

Raul Camposano: When I was at Synopsys, we had some export technology that was close to the fabs, so in a sense, the problem itself is not new. But the ESD Alliance has brokered this conversation. They have had [an eye] on export control for a very long time.

It’s always been tough, particularly when the supply chain is so integrated. It’s actually hard to imagine it would survive any real closing of the borders. I think what’s more likely is that things will be more expensive, but nobody really wins if you close the whole thing down.

WWJD: What is the value of belonging to the ESD Alliance?

Raul Camposano: In principal, it’s good to have an industry association that looks out for your interests, and those of the industry. The ESD Alliance happens to be that for EDA.

Speaking of international issues, we benefit very concretely from the export control discussions. At Sage, we have not had any problems like that, but still somebody needs to be on the lookout for those issues. So that is the number one value [of the ESD Alliance].

And the market information they provide is the only reliable information for our industry.

WWJD: But Synopsys doesn’t give its numbers.

Raul Camposano: Yeah, but it gives an indication of which sectors in EDA are growing. Every startup should use that information to understand the market.

And last, but not least, they have this series of talks that brings everyone together. It’s a great way to see the CEOs of the large companies when they do the EDA outlook, to see what they are thinking.

It’s also great to talk with the startups, and to attend the series that Jim Hogan has been running for a while. The little companies, the investors, the entrepreneurs can all get together to see what they are doing.

The ESD Alliance is a great way of taking care of the industry that we all love, or otherwise we wouldn’t be in it.

WWJD: What’s the funniest thing that’s happened to you in your career?

Raul Camposano: The most funny one is from the 90s, when industry was still growing.

I was at Synopsys, and in our incredible optimism for success we ordered a bottle of 1946 wine to celebrate. Obviously we were doing very well, and although it was a few thousand dollars, we thought we could expense it – theoretically.

[laughing] Unfortunately somebody was watching. So as we passed the wine around, we also passed the hat around, because we discovered we had to pay for it ourselves.

**************The Bio …

Dr. Raúl Camposano is the CEO of Sage. He was previously the CEO of Nimbic, a startup that was acquired by Mentor Graphics in 2014. From 1994 to 2007 he was with Synopsys, where he served as Chief Technology Officer, Senior Vice President, and General Manager.

Prior to joining Synopsys, Camposano was a Director for the German National Research Center for Computer Science, Professor of Computer Science at the University of Paderborn, and a Research Staff Member at the IBM T.J. Watson Research Center. Raúl holds a B.S and M.S. in Electrical Engineering from the University of Chile, and a Ph.D. in Computer Science from the University of Karlsruhe.

Camposano has published over 70 technical papers and written and/or edited three books on electronic design automation. He has contributed significantly to building the design community as a whole serving on numerous editorial, advisory and company boards.

Camposano was also an Advisory Professor at Fudan University and the Chinese Academy of Sciences. He was elected a Fellow of the IEEE in 1999 and to the board of directors of EDA Consortium (now the ESD Alliance) in 2012.

As national and international news crashes over the shore, wave after wave, it’s easy to lose track of any particular item amidst the churning foam. The story discussed here, however, floats more visibly atop the flotsam and jetsam because it’s relevant to the IP and EDA industries.

Several weeks ago, Siemens AG – a German company – was caught-up in a violation of a part of the current EU sanctions against Russia. Siemens’s power turbines, having been sold to Russia – which was not a violation – were then allegedly modified and shipped off to Crimea for installation there – which was a violation.

You remember Crimea. It was part of Ukraine until 2014, and then it was not.

Anyway when the turbine situation was uncovered, the EU was not happy with Siemens; Siemens was not happy with Russia; if Russia or Crimea were unhappy with anyone, they kept it to themselves.

As a result of these revelations, Siemens AG now faces a fine from the EU, and has canceled several high-profile, lucrative business deals with Russian firms. Siemens is mad – slightly less rich, and mad.

Which brings us to Mentor Graphics. Such experts we are, who have had the chance to learn about Export Controls from the likes of Cadence’s Larry Disenhof or SmartFlow’s Ted Miracco, and it’s that knowledge which seems relevant to Mentor.

[See article excerpts below]

If Mentor is a German company – post-acquisition in March – then whatever liability the parent company Siemens AG must absorb, will certainly have an impact on Mentor. At least that seems the proper conclusion, although perhaps it’s only the turbine-producing part of Siemens that’s on the hot seat.

If, however, Mentor is an American company – if Siemens USA, of which Mentor is now a part, has no reporting obligations to Siemens AG – then Mentor is off the hook?

That seems right, unless perhaps it can be proven that Mentor’s system design software was somehow used by Siemens AG to create a product that is now illegally poised to begin operation in Crimea.

Internet research interlude …

Well, there you go: A little online exploration seems to indicate that Siemens USA isnota separate business. It’s a ‘subsidiary’ of Siemens AG, per the company’s own website.

Which brings us back to this query: In the eyes of the EU or the United States, do export-compliance obligations only apply to the business unit associated with a particular product line, or does that obligation extend across the entire corporate entity?

Does Mentor Graphics of Wilsonville have any liability with respect to EU export restrictions given that its parent company, Siemens AG of Munich, is under review by the EU for having violated those restrictions?

And an even more fascinating query: Does Siemens AG have any obligation to adhere to American export-compliance regulations, or American sanctions?

The answers to these questions do not seem obvious. More importantly, it’s possible that no one really cares.

After all, the American government did not seem to put up any resistance whatsoever to the sale of Mentor to a foreign-based enterprise. Mentor’s design software and IP were not of enough significance to American national security or corporate well-being to have warranted putting a stop to the acquisition.

That lack of interest may extend to any problems Mentor’s new parent company is currently navigating.

Then there are the Commerce Control List Categories, numbered 0 to 9, and A to E. For instance, Category 3D991 includes most EDA software, while various types of IP fall into categories such as 3E991 or EAR99. Meanwhile, no matter that most EDA and IP categories are not restricted, all categories on the Commerce Control List are controlled. Stated otherwise, “unrestricted does not mean uncontrolled.”

And what does controlled versus restricted mean? It means that you need to keep track of which non-US Person will have access to your products, even if that person is working in your offices within the U.S., and you need to keep track of the destination country for your exports.

Controlled products cannot be sold at any time to any of the Group E1 countries – Cuba, Iran, North Korea, Sudan, or Syria – while restricted products cannot be sold to any Group D1 countries, which include PRC and Russia, without special permissions.

You’re not only responsible for knowing who you’re selling your products to, and where they’re located, you’re also responsible for making sure that your customers don’t sell products that include your products to entities on the Group E1 list, or possibly the Group D1 list, or any other government-declared restricted/controlled export lists … ever.

U.S. government sanctions are administered by two agencies, the Office of Foreign Assets Control (OFAC), which handles licensing and oversight of economic sanctions and the Bureau of Industry and Security (BIS), which handles licensing of certain exports and re-exports of technology and goods originating in the U.S., or foreign manufactured goods using U.S. technology.

The consequences for being found guilty of breaching sanctions are serious. Several major companies have been subject to multi-million dollar fines and settlements with U.S. regulators for sanctions breaches.

It’s good to know another EDA startup has emerged, they’ve been in such short supply of late.

Austin-based Austemper Design Systems is an EDA startup focused on functional safety that had the good luck to find the Design Automation Conference in their own front yard this year – making it easy for the company to exhibit in Austin and showcase their newly announced suite of tools.

Speaking by phone in a recent call, Austemper Founder & CEO Sanjay Pillay said, “We offer four different tools in our suite, one that analyzes quantitative metrics, two for design automation that go in and add diagnostic conversions and can be used for a single block of IP or for the entire design, and a fourth tool that runs fault-injection analysis.”

Given that the company has only been underway since March 2015, I suggested that tool portfolio represents a lot of productivity over a short amount of time.

Pillay agreed: “Although we are young, we are already working with the largest semiconductor companies in the world, and in the process of negotiating licenses with others.

“DAC was a great place to announce our products. We had more than 30 meetings and demonstrations with potential customers and partners during DAC. It was also an opportunity for us to meet in person with people we have interacted with over e-mails and conference calls, to make that human connection.”

Asked about the origin of the company, Pillay said, “Before starting here at Austemper, I was at HGST/STEC running their Enterprise SSD controller development, and before that was at Maxim and Cirrus Logic, both consumer-product companies.

“My move from companies with a consumer focus,” he continued, “to one with an enterprise focus at HGST was where I first saw an emphasis on functional safety. Where I learned a network interface like PCIe can work with any layout format, but still need a fall-back or safe-state when unexpected thing happen.”

Pillay recalled that designers at HGST went looking for third-party IP blocks that could fill their requirements, but the search proved almost fruitless: “I found not a lot of IP companies addressing functional safety in their products, even though it’s a big issues.

“In fact, I only found one company that would actually support our efforts, but the IP from that vendor were not always Best in Class.”

In response to the dearth of appropriate IP, Pillay said his team at HGST had to innovate: “We added functional safety around the IP we were using, and added that feature set to our custom-built design program.

“We basically licensed IP that we knew to be functionally correct, with correct performance, and then put in the functional safety feature ourselves – things like parity across buses, ECC for memories, etc.”

“Unfortunately,” he continued, “we ran into problems. As everyone knows, if you touch or modify the IP you’ve purchased, the warranties are voided. And typically, the IP vendor will nor redo the verification effort [to confirm functionality within your design]

“This errata within the IP market required us to redo the whole verification effort, effectively pushing out the delivery schedule for our designs by 2-to-3 months.

“When I left HGST, as a result we went looking for a better way to do things.”

“While still at HGST,” Pillay said, “we had a very senior architect who manned the spread sheet, and we had very senior people running that program based on feedback from the designers.

“The process was error prone, however, particularly when the floor plan would not have the correct aspect ratio for memories – which caused us to ask: Is there an automated way to measure these diagnostics?

“And that was the genesis of our SafetyScope tool at Austemper, which starts off with the RTL or netlist. The idea is to cut down on the whole manual process in design analysis, and redo it so nothing can slip through.”

While working with an automotive customer, Pillay saw another un-met need: “We got involved by necessity with some of our customers in the automotive space, the certification space in particular.

“We looked for tools and IP that would help us out – especially for the automotive – but we didn’t see any good solutions out in the market to address our needs.

“The way I looked at it, there must be other/better ways. And that’s why we came up with KaleidoScope at Austemper.

“As I come from the user side – I’ve done design, verification, and some architecture work – and I’ve known the pain points. Kaleidoscope was our first EDA tool development meant to address that pain.”

I asked Pillay to comment on the explosive growth in Automotive semiconductors, as well as Machine Learning edge-node devices.

He responded, “It’s absolutely true, there is a huge initial pull coming from Automotive for functional safety. The complexity required in ADAS silicon [Advanced Driver Assistance Systems] is at least 2 orders of magnitude higher than what we’ve previously seen in automotive, for instance, they are more like an SoC controller or a set-top box.

“Obviously there are tools for 8-bit or 16-bit microcontrollers, but when you try to scale those tools to ADAS, they do not scale well.”

“Our tools, however,” Pillay enthused, “are being built from the ground up to meet the needs of the Automotive space.”

Facebook and Google are building their own chips, I noted, so why aren’t the automobile manufacturers building their own chips to meet their ADAS needs.

Pillay responded, “I’m sure there are some auto vendors – especially the new players from the Valley, which are more like Google and Facebook – who would prefer a vertical integration, but most vendors are more traditional.”

“Which translates to a great market opportunity for you,” I suggested.

“Absolutely,” Pillay said. “With automotive complexity going through the roof, all of the functional and functional safety aspects need to be there in the chips the auto vendors are going to use in their systems.

“The amount of hardware-assisted algorithms in those automotive chips, and the amount of data they’re pumping through, and the amount of decisions being made – the complexity is just huge. I’ve seen some automotive customers with chips in their cars that are actually just as complex as an enterprise SSD controller.”

I asked if Austemper has someone internal who keeps track of the plethora of standards associated with automotive hardware and software.

“Yes we do,” Pillay replied. “And our customers do.

“The big one, of course – the standard around which everyone is consolidating – is ISO 26262. That’s the gold standard for automotive today.

“There are also standards for aero, medical, industrial – but at the end of the day, the process across these various industries is very similar. For some standards, the numbers are qualitative, while for other standards they are more specific.”

“As your tools insert functional safety into design blocks, are you also assuring customers that the modifications will result in silicon that meets current safety standards? What about the liability issues?” I asked.

“That’s a great question,” Pillay replied. “Obviously what we are doing is very related to safety standards, and we are in the process of getting our tools certified relative to those standards.

“At the end of the day, however, if we have done everything using the industry’s most established processes – whether from our tool perspective or our IP enhancement perspective – and we can show that we are following all of the established rules, going above and beyond what we need to do, that should answer all issues around liability.”

“Why have four tools,” I asked, “why not consolidate them all into one larger tool?”

“As we see it,” Pillay said, “each company – especially the established ones – have their own mechanisms for design. They don’t want to change anything. For those customers – especially those who already have an internal flow set up – our tools can improve the productivity and they may not need all of the features in all of our tools.

“For less-established customers, however, they may choose to use all four tools. We can help them do that as well.”

“Implying that your customers also rely on your for some design services?” I asked.

“We have tried to stay tool-flow independent,” Pillay said. “Our tools have taken very large SystemVerilog and Verilog designs and [made the modifications] required for functional safety.

“And we support all of the major EDA vendors – Synopsys, Cadence, Mentor, etc. – and their tool flows. Our goal is to help our customers produce an SoC that will meet all of the safety standards, whether standard or emerging.

“So we have done some design services, but that is not our preferred model of engagement.”

“Where did you get the name for the company?” I asked.

Pillay chuckled, and said very few people have actually asked that question: “Austempering is a metallurgical process that changes the characteristic of metal.

“At Austemper, we take a design which was built for consumer devices, and by putting it through our flow, make it useful in the automotive or medical industry.”

“Isn’t that alchemy, a sort of Dark Art?” I asked.

Again Pillay chuckled: “That’s exactly what we are going for in the name, but it gets even better. The word Austemper has Austin embedded in it, and some of our founding team were based in Austin.”

“Most importantly, however, the name conveys what we are trying to do – to create enhanced IP. That’s our focus and that’s what we are able to do.”

***********************The Austemper Suite of Tools …

SafetyScope implements the estimation of the functional safety (FS) metrics based on a given mission profile and set of diagnostic coverage mechanisms. Where applicable, the tool automatically applies default values from ISO26262 and/or IEC61508 for FIT rates and other DC metrics.

This conversation with Hal Barbour, Chairman at CAST IP, is the second of four dialogs about Grand Challenges in IP.

The first installment in the series, published last week, was a conversation with Sonics co-Founder and CEO Grant Pierce.

Pierce argues that today’s Grand Challenges in IP center around the complexities of delivering sub-systems and related technical expertise to customers, helping develop edge-node devices targeted at Machine Learning, and providing IP for myriad automotive systems – all while meeting demands for greater bandwidth and throughput, and astonishingly low power.

In this week’s installment in the series, Hal Barbour talks about a completely different set of Grand Challenges in IP – those related to the business issues surrounding the industry.

Grand Challenge No. 1: Do not put all of your customers in one basket.

Barbour has some very specific ideas about maximizing the circumstances for both the IP vendor and the customer, but he started the conversation with good news: “We’ve had a fantastic year, with 2-to-3x increase in business over previous years. And more importantly, no single customer represents more than 5 percent of our business.”

Does that fact take on particular meaning in light of recent news that Imagination Technologies has been upended by the threat of losing Apple as its principal customer?

Barbour said, “Absolutely. You’re screwed in the IP business if you depend on just one customer, and Imagination is not the only one. There are others as well tied to the super-smart phone business [who would be compromised] to lose a key customer.”

“It’s true,” he clarified, “we do have a lot of business in the smart phone market, but unlike other people we have a royalty-free business model. We make money through an up-front license fee and not royalties.

“And we do not have a top-heavy customer base. You have much great immunity to the changes that occur in the industry, the down cycles and up cycles, if you do not rely on one or two customers.

“We have always felt that the broad range of our customer base is our great strength.”

“We have been in business now for 23 years,” Barbour noted. “We have a good name and reputation out there, and our products are really competitive.

“We’re also different because we don’t do elaborate marketing or put on lavish seminars. It’s not that we couldn’t do these things, but we keep our costs very low and for that reason can provide a better value proposition to our customers.

“And CAST has really, really good people, many located in less costly areas within the US [than Silicon Valley]. Compared with other vendors who have outsourced a lot of their work to India, we also have remote teams in the Czech Republic, in Poland and Greece. These are very focused groups, tightly coupled to everything we do.”

Barbour acknowledged that it’s not always easy to coordinate across remote teams, but said the company successfully “worked through” those issues a long time ago and is now reaping the benefits.

I asked Barbour if CAST’s success has been due in part to luck, or even dumb luck.

“That’s a good question,” he said, laughing. “It’s been luck and dumb luck, because everyone knows the correct way to start a business is to plan your way, write a business model, and get outside financing.

“But that traditional route has not been us. We don’t see out more than a year, or a year and a half, and we have far more flexibility because we are bootstrapped. We’ve never had a loan and never taken a dime from outside investors.

“And we have no internal financial people whatsoever, and I’ll tell you why.

“When you get money from the outside, the investors demand that you have a vice president of finance. That’s who they’re always closest to in the organization.

“From the investors’ standpoint that may make sense, but from a business point of view, those internal financial guys bring no added value to the company.

“At CAST, we keep our expenses in line,” Barbour emphasized. “We’re not stupid, and it’s not that complicated. It’s about controlling the costs.”

“It’s also about focusing your sales, engineering, and energy towards your customers, and doing it in a fashion that’s good for your customers and good for you.”

“Almost every other company has commissioned sales people. Why? Because they say that’s how you get people to work hard for you.

“In the case of highly leveraged sales commissions, it’s done primarily because it’s easy to measure and because you can put a whip on people’s back. But I never believed in putting a whip to people’s back to get high performance.

“When I first started in sales many years ago, I always appreciated the engineers behind the products I was selling. They contributed as much to any deal as I did.

“It’s just a different way to look at the world,” Barbour said.

Grand Challenge No. 5: Keep the costs of IP low for the customer.

These ideals seem appropriate in small companies, I said, but what about the large IP vendors in the industry?

Barbour responded: “Over the 30-year history of the industry, clearly there have been lots of acquisitions by Cadence, Synopsys and others, which have had some effect.

“Then there are the large acquisitions by financial institutions, as we’ve just seen with ARM. Our 2-to-3x growth over this last year indicates to us that some customers are going away from ARM because of this SoftBank acquisition.”

Have the costs for ARM products increased due to the acquisition, I asked.

“Trying to find out what you’re competing against is actually difficult,” Barbour replied. “In our case, we’re competing against a much, much lower business model.

“With ARM, for instance, their IoT entry-level model is called Zero and [costs] approximately $40,000. But once you’ve shipped your product based on that core, you’re still looking at another $300,000 or more in royalties.

“Our comparable product has an overall cost to the customer of closer to $100,000 to $125,000 – including [assistance] in customizing blocks – and no royalties, so the cost is far lower.

“And our development engineers are tightly coupled to the sales process, so we can respond to customers’ customization needs.

“The big IP companies charge $3000 to $4000 a day for help with customization. But with us, the cost is much, much less than that. We can provide customized block at less than half the cost of the big IP providers.

“Many times what customers need is not something complex that’s running an OS, or something that’s very expensive. What they need is a deeply embedded processor or an engine that doesn’t require, or justify, a royalty type of engagement. They just want to lower their NRE costs.

“We don’t have a royalty model, so our customers will not be heard saying, ‘This damn royalty is killing us, so let’s go elsewhere – or do it ourselves.’

“This the most important goal,” Barbour said, “to keep the costs of IP low for the customer.”

Grand Challenge No. 6:Going public is rarely a recipe for success.

Asked about an exit for CAST, perhaps an IPO, Barbour was adamant: There are no advantages.

He cited several examples of companies that lost their way after going public, including View Logic: “The CEO of View Logic was Will Herman, a really nice guy and a brilliant engineer.

“We were a partner of his when CAST first got started and every time I went to see them, Will would call me into his office to bounce off some ideas for yet another presentation to Wall Street.

“After the second or third time [we went through that exercise], Will acknowledged he was spending at least 50 percent of his mental capital towards something that had no real bearing on his customers’ well-being or his employees. All of that effort was strictly for the Street.

“For Will, going public was all about feeding the Beast and after a while, the company got so pressured [by the Street], it was sold off – part went to Synopsys and part went to Mentor Graphics.

“We have never had to go down that path, which has continued to give us a lot of independence.

“I can’t tell you we had a long-term vision for CAST when we first started, we just wanted to do logic simulation for models. But it was too late [in the industry] to do a simulator, so we decided to do models instead.

“Had we had outside financing, or were answering to share holders, the financial folks would have asked what the hell we were doing and never allowed us to change our focus.

“I’ve seen some really, really good engineering organizations torn asunder by unrealistic expectations from the financial people. We have not had to [endure that difficulty].

Grand Challenge No. 7: Hire great people and partner with great companies.

Most importantly, Barbour stressed, hire and/or work with excellent people.

“Our business model is not just about developing CAST owned IP,” he said. “It’s also about working with long-term partners in a tightly coupled business relationship, or serving as exclusive world-wide distributor for people who are experts in their field.

“We work with companies like Ocean Logic, Beyond Semiconductor, Fraunhofer Institute, Sandgate, Silesia Devices, and SoC Solutions. And we have partners in Poland, Slovenia and Greece – they’re all fantastic.

“In effect, we behave like one company, but with each unit operating somewhat like we do – relatively small and managing their costs very carefully. And by operating in geographic areas that are less costly, we can scale much more easily with six or seven development centers beyond our own engineering centers.”

It’s not just great partners but great people who make things a success, according to Barbour.

For instance, he said, “When it was time for me to move from CEO to Chairman, we hired Nikos Zervas, who’s been a great fit. He’s more technically astute than I am, younger, and in all regards better than I am. Everybody respects him as I do. It was a very smooth transition.

“And Paul Lindemann. He’s just fantastic at marketing and has been with us since the very beginning.

“I feel very lucky to have been around these types of really, really good people. Believe me, it’s not me who has made CAST a success. It’s our great people have done that. I’m only one link in the chain.”

Grand Challenge No. 8: Love your work.

Hal Barbour so clearly enjoys his work, I noted he would be working well into his 90’s.

Laughing, he said, “I very much like staying involved in a company I had a major part in building. And I like talking to the customers.

“Why would I want to do anything else?”

*******************Bio …

Hal Barbour is Chairman of the Board of CAST, Inc. He earned a BSEE and worked several years as a circuit designer before moving on to technical sales and marketing positions with GenRad, Intergraph, and HHB Systems (later acquired by Racal-Redac).

Witnessing both stunning successes and colossal managerial failures, he has applied those lessons to semiconductor IP provider CAST. Pioneering a successful virtual and distributed organization model and using a lean, customer-oriented operations philosophy, Barbour has helped CAST succeed and thrive in a volatile and challenging market.

Something eerie and inexplicable happened on Thursday evening, April 6th. Out of nowhere, an intense storm swept through the Bay Area, unannounced and without warning. The skies darkened, the winds howled, severe rain pelted the crowded, suddenly dangerous freeways, and hundreds of thousands lost power.

Meanwhile, exactly in the midst of the most violent part of this mysterious storm, the CEOs of the four most important companies within the ESD Alliance sat on stools in front of an audience assembled at Synopsys and chatted about this, that, and the other. Seemingly oblivious to the profound violence unleashing itself just outside the windows, they acted as if nothing was amiss.

Everything in the industry – and the world – was in order: Wonderful, with the data pointing continuously up and to the right, and everywhere ample evidence for a bullish, optimistic, and excited outlook on the future of EDA and IP.

No matter that Nature was having its way out there in the darkness, that the U.S. had bombed Syria the hour before their discussion began, that the drumbeat for answers about entanglements with Russia was quickening, or difficult conversations with the President of the PRC were underway that very day in Florida – the CEOs of Synopsys, Cadence, Siemens/Mentor Graphics and SoftBank/ARM sat relaxed and easy, basking in the evident vitality of the EDA and IP industries, and allowing themselves to be shepherded through a congenial confab of confident chit-chat by Ed Sperling of Semiconductor Engineering fame.

That fact that the vagaries of Nature never came into the conversation was not surprising; the fact the Mr. Sperling refused all opportunities to bring what he termed as “politics” into the conversation was quite the opposite. Surprising, that is.

Would EDA companies continue to operate on a business-as-usual manner in Russia? Would ARM be changed by Brexit, Article 50 having been invoked by Prime Minister May that very week? Would SoftBank investors, Saudi Arabia, Japan, China or Abu Dhabi, change ARM in any way? Would Mentor be influenced by its new German owners? Would Synopsys continue to operate as if free trade and globalization were still the order of the day? Would Cadence be influenced by the rising power of the PRC?

None of this was on the table at that April 6th CEO Confab of Collegiality and Good Will. And why was that?

Is it possible that the CEOs of publicly traded companies get paid to be positive-outlook kinds of guys? Is it possible that the CEOs of all companies, publicly traded or not, need to maintain a veneer of steady optimism and aura of control over the arc of history of their organizations?

Is it possible that the world will continue to turn, and commerce will continue to operate, no matter the vagaries of political firestorms or howling nor’easters that should be kicking the shit out of Gnarly New England, not Sacred Silicon Valley?

Is it possible that “if we ignore it, it will just go away” is the best way to conduct business in industries as completely/totally global as EDA and IP?

Who knows? These questions were never asked on April 6th.

What was discussed generated two categories of responses: the Good and the Difficult. But other than a stirring endorsement of China as a market and mentor, nobody discussed the geopolitical situation or the weather outside.

Until the very end, that is, when suddenly the panelists turned brutally candid – either in preparation for forging out into the raging storm to reach their cars in the dark, wind-whipped parking lot, or because representatives of the U.S. Military seated at the back of the room began to ask questions.

******************The Good …

In the category of happy talk – trains, planes, cars, IoT, complexity, global markets, and investment opportunities – all of the responses supported the thesis that everything’s up and to the right for the EDA and IP industries.

Synopsys’ Aart de Geus: The industry is going through a phase shift and rejuvenation. Also, the only thing better than something smart, is something even smarter, so let’s praise the advent of the IoT.

SoftBank/ARM’s Simon Segars: There’s been an uptick in optimism about the next 10 years in the semiconductor industry. And just as the automotive industry eventually benefited from regulation after 60 years, the Internet will, after only 25 years, quickly be regulated, making it more safe and secure.

Siemens/Mentor’s Walden C. Rhines: This is a really good time for the industry. People who never did design before – Google, Facebook and Amazon – are becoming big customers for EDA, along with all sorts of companies who find they need to design to differentiate. And although we’ve pretty much automated the whole process of IC design, the design of trains, planes and cars is still largely un-automated. This market will be enormous compared to the semiconductor market.

Cadence’s Lip-Bu Tan: There are waves coming, and you should ride the wave even if you don’t create the wave. There is a lot of new opportunity, and new technology that needs innovation – things that are more data-centric, with more storage, less latency. And there’s the IoT. I’m putting my bets on intelligence at the edge for manufacturing. Overall, EDA is tremendously undervalued, which is good news from an investor’s point of view.

Simon Segars: For over 30 years, we’ve aggregated the industry – EDA and IP – so you don’t have to reinvent the wheel with every design. Although in some ways it’s business as usual today, complexity is going up and up. This creates opportunities.

Aart de Geus: Complexity is our middle name in this industry.

******************The Difficult …

Although unwilling to introduce politics into the conversation, Sperling did ask his panelists to address the difficult topics:

* Security as a hardware/software issue.* Stubborn designers resistant to change, even in the face of growing design complexity.* The steady migration of EDA customers from West to East.

Simon Segars: We are not making progress fast enough. People are building things which are unsafe and dangerous. And, there will be more incidences of large-scale hacks while the supply chain catches up with what needs to be done in the hardware so the software is safe. It doesn’t requires rocket science to see that people are designing things today and pushing them out to the market without thinking about security. The state of the art is pretty grim.

Wally Rhines: There are all sorts of technologies available today for designing chips that are more secure. The problem is that people who design those chips really don’t want to pay a lot for that additional security. But eventually, there will be a trojan in a chip that causes harm. So now there will be an additional line added to the purchase agreement: ‘If we’re buying this chip from you, you’re guaranteeing there are no trojans.’ Only when the customers begin to say that, will security be a critical part of how people design chips.

Aart de Geus: It’s a very complex problem. You could argue that only the smartest people design chips, but the smartest people are working to hack those chips – people so smart that they would be Fellows in conventional companies. Also, there are a deep-rooted set of issues around security that are not well understood – and different issues between hardware and security. Meanwhile, the intersection between these two is very vulnerable. We need to systematically build security into a design that meets regulations, and we need a design to be secure by construction. Gradually we will have to regulate security.

Lip-Bu Tan: Cyber-security is important, and companies must be aware of the problem and know how to prevent it. Look at our key customers – the verticals – they each have different requirements for security, and how much they are willing to pay for solutions. We’re all working on it, but not until some really big companies make it happen … even now, people know they have to be aware of it, but may not yet know how to prevent it.

Wally Rhines: The truth is, we have lots of new capabilities in our tools and IP, but the designers will continue to use older tools and methods as long as they can get the job down – tools and methods that are slow and obsolete, but reliable. Only if the designers absolutely cannot solve a problem, will they move to new tools.

Lip-Bu Tan: The growth opportunities are exciting, but on the EDA side some of the tools are very old and need a complete rewrite. Now there are chips with 100-to-200 CPUs, and every vertical market has different requirements for the tools, so there’s a steep learning curve and we’re all having to move up that curve.

Aart de Geus: As system complexity is changing dramatically, we continue to be on just as fast a wave of evolution forward as at any other time in the 40 years of our industry. But with the speed of change in system complexity, partitioning the project has become just that much more important.

Wally Rhines: China is investing at least $20 billion per year to stimulate their industry – initially investing in fabs, but now investing in the fabless infrastructure, reporting 1300 fabless IC companies in the country. That’s why China and the Pacific Rim are creating new growth that overshadows the old areas.

Lip-Bu Tan: Clearly IP is very important, and we’re seeing IP is starting to have a trend of more outsourcing, but trying to catch up with the protocols involved in using IP is creating a nightmare to support it all. Nonetheless, I’m excited about growth – even though Moore’s Law is clearly slowing down.

******************The Downright Bad …

Only when pressed for answers from representatives of the U.S. military at the back of the room, did Sperling allow the conversation to get prickly. When asked what the Government could do to help keep the EDA and IP industries alive and vital, the responses were sharp and immediate.

Aart de Geus: Work on the H1-B visa issue! Since 9/11, the U.S. has shut its doors indiscriminately. Although we rely on having the best people from around the world to grow our industry, it’s becoming impossible for the best people in the world to work in our industry because of these visa restrictions. This is the singular biggest detriment to our making progress. This is state-of-the-art technology that has nothing to do with borders. The whole situation around the H1-B visas today is a tragedy.

Wally Rhines: Be very careful about implementing export controls. If the global markets for our products are restricted, we simply won’t develop the new technologies. We’re not like the big companies who can monitor and control things. When you put those kinds of export restrictions on our products, our industry is made less viable.

Simon Segars: You need to help get people more interested in science and technology. Now there are more lawyers than engineers – the supply/demand here has gotten out of kilter.

Lip-Bu Tan: The Chinese Government is putting their money behind real innovation. If you and the U.S. Government don’t change at the top, you will no longer be competitive! I know a lot of universities where the professors are telling the students to go into software or social media. But hardware needs the best talent out of the universities. Do more to encourage that to happen.

******************
And the Wind howled on …

Will the wind ever remember
The names it has blown in the past
And with this, crush its old age and its wisdom
It whispers, no this will be the last

And the wind cries Mary.
******************

]]>https://www10.edacafe.com/blogs/ipshowcase/?feed=rss2&p=223522235Oski Technology: new VIP supports Formal Sign-offhttps://www10.edacafe.com/blogs/ipshowcase/?p=2212
https://www10.edacafe.com/blogs/ipshowcase/?p=2212#respondFri, 24 Feb 2017 03:12:03 +0000https://www10.edacafe.com/blogs/ipshowcase/?p=2212
Oski Technology has added a new page to its playbook. Now it’s not just a services company, it’s an IP company as well. This week, the company announced it’s Formal Verification IP Library targeted at those companies using ARM’s AMBA interface protocols.

When we spoke on the phone about the announcement, I asked Oski VP of Applications Engineering Roger Sabbagh why now for this product release. He said: “I personally have been working in Formal since the year 2000, back when I joined 0-In, and over the years I’ve learned that formal adoption grows slowly.

“Yet although there has never been a knee in the curve, we have seen some important developments in the industry. Synopsys developed PC Formal and Cadence bought Jasper, both indicating that Formal is catching on slowly but surely.”

Meanwhile, per Sabbagh, the industry began to accept that design could be made easier, and productivity improved, through the reuse of standard interfaces – a trend that dovetailed well with Oski’s core competence.

“Oski has been doing Formal for over a decade,” Sabbagh said, “and over that time we had developed an in-house capability, reusable verification IPs specifically tuned for Formal.”

So why now for this week’s announcement?

Sabbagh said it combines trends in reuse and Formal: “We decided to make this verification IP available to the rest of the industry, so they could benefit as well from our work.”

[To help understand the work, a bit from the February 22nd Press Release: “Oski’s VIP library components currently are available for both interface protocol rules and coherency properties for all revisions of the ARM Coherent Hub Interface (CHI) and AXI Coherency Extension (ACE) standards. The Oski Formal VIP Library includes AMBA 5, AMBA 4 and AMBA 3 ARM protocols and are designed for both RTL block verification and architectural verification applications.”]

I asked Sabbagh if Oski worked closely with ARM in developing this VIP.

He answered first in general terms: “We’ve worked with a lot of semiconductor companies in developing our VIP, among them Arteris, the leading NOC company. As well, in many of our consulting service assignments we have been using our VIP.”

Sabbagh then answered specifically: “And yes, we have worked with ARM as well, as a VIP customer.”

Given the number of companies providing verification IP these days, I asked Roger Sabbagh who Oski sees as the competition.

He responded emphatically: “Oski is so unique, because there’s nobody out there focused 100-percent on Formal like we are – Formal tools and services. There’s nobody out there who does exactly what we do.

“I just joined Oski last November, previously working at Huawei Technologies where I was leading the Formal team. But I’ve known about Oski for a long time. When I was at Mentor Graphics where we had joint customers; Mentor provided Formal tools and Oski did the consulting.

“And even before that when I was at 0-In Design Automation, I looked to Oski as one of the thought leaders in Formal.”

“But yes,” Sabbagh offered, “all the Formal tool providers have tried to fill this need, because there is a definite need for reusable verification IP designed specifically for Formal. But that VIP is not portable.

“So what I would say about our solution is, not only do you get the benefit of our VIP being proven by Oski engineers, but it’s also not tool specific. It’s portable across all tools and all flows, a library of verification components that enables Formal sign-off for compliance for ARM protocols.

“In today’s SoC design, there’s a lot of use of ARM protocols – processors that can communicate with other devices like shared memories use ARM ACE protocols to communicate and make sure there are coherent caches.

“There are ARM protocols everyone, and all these IP blocks talk to each other through this protocol. Our announcement allows people to say, I’m Formally proven and complaint.”

With additional enthusiasm, Sabbagh said, “This whole concept of Formal sign-off is something that Oski actually came up with. We are one of the pioneers in this area. Now anyone can run Formal sign-off.”

Excellent, I said, and just in time for DVCon 2017 next week in San Jose.

“Yes,” Sabbagh agreed, “At DVCon, we have a booth and will be talking all about our VIP. But we will also be participating in one of the tutorials – Thursday afternoon during the Synopsys tutorial.”

Do you favor Synopsys over other vendors, I asked.

“Absolutely not,” Sabbagh said. “We’ve done joint marketing with many of the other vendors in the past.”

“Actually,” he added with a chuckle, “we are the Switzerland of Formal, vendor neutral because we’re all about the methodology. Our VIP is completely portable across the tools. We work with whatever tools our customers have decided to use.

“It’s the vendor’s job to sell the tools to the customer. It’s our job to sell our services and our methodologies – and now our VIP. We think this will open many doors for us!”

This week, the ESD Alliance announced that Sonics CEO Grant Pierce has been elected chair of the organization’s Board of Directors. His election is unique in several ways: Pierce is the first CEO of an IP company to lead the Alliance; he replaces two co-chairs, Cadence CEO Lip-Bu Tan and PDF Solutions, John Kibarian; and he is only the second CEO of a non-publicly traded company to serve as Board Chair, the other being Jasper CEO Kathryn Kranen who took the reins in 2012.

When Pierce and I spoke by phone on Tuesday about his election, he noted the unique circumstances of his new leadership role: “When I joined the board several years ago, it was with the intention to add a new point of view to what was then the EDA Consortium, to help the organization reflect the emerging reality of what was happening in the marketplace with respect to IP companies.

“In some ways, the IP companies consider themselves to be a necessary evil. Every chip developed today involves some sort of third-party IP, so having a place on the Board of the ESD Alliance is essential.”

Pierce also referenced early input from Kathryn Kranen: “When I joined the Board, I spoke at length with Kathryn, who was Board Chair at the time. She believed this job to be well placed when in the hands of one of the smaller companies in the organization, the CEOs of the larger companies being almost too busy to find the time needed to effectively lead.

“Of course, I don’t have a lot of time either, but when I joined the Board it was with the express intention of playing an active role in the process of re-defining EDAC. And it was my efforts, along with those of many others in the group, that lead directly to the creation of the ESD Alliance early last year.

“The EDA Consortium looked at chip design as a matter for the EDA world alone, but that missed the point of what is needed today in the complex ecosystem that surrounds design.

“Now, not only does the ESD Alliance include the IP perspective, it also looks at the overall systems perspective, including embedded software. Something I feel very strongly about, as does Bob Smith [ESD Alliance Executive Director] and the entire Board of Directors.

“So having served on the board these several years, and knowing what a wonderful guy Bob Smith is to work with – that he is local, so it’s convenient for the two us to connect and work together on various projects for the organization – I concluded that I should put my hat in the ring for a term as Board Chair and the Board agreed with my decision.”

I asked Pierce if he was fully apprised as to what all will be expected of him going forward. Is he sure he really has time to continue to lead Sonics, a company he co-founded 20 years ago, and also lead the ESD Alliance?

He laughed, and said, “Well, the past chairs who are still on the board said they would read me into the Chairman’s Book of Secrets, and I look forward to that.

“But seriously, this organization has had to take some action in order to continue to be relevant to the industry, to continue to lead.

“We all know that it requires a more diverse groups of companies, as I mentioned – system companies, embedded software, IP, EDA, and the like – if we want to continue to be a vital part of the culture of exchanging new ideas and, importantly, encouraging new startups.

“The Board knows I would like to continue to grow the ranks of smaller companies as members of the ESD Alliance, and now I’ve got the opportunity to make some of this happen.”

I asked Pierce to articulate the argument for membership for small companies, particularly those on fixed budgets for which the ESD Alliance membership fees might be a challenge.

He recounted his own company’s journey with respect to membership: “I recognized that Sonics had been in business for a long time, since 1996, yet we were not members of EDAC until we joined the Board. And the reason for that shift in our thinking was very straightforward – the membership of Simon Segars and ARM.

“As a leader in the IP industry, ARM had a very large customer constituency – arguably an even more robust constituency that of the EDA world – and they wanted to learn more and understand better the ecosystem within which their processors were being used.

“That thinking [dovetailed] with our own efforts to understand the environment, so following Simon’s lead we joined the EDAC Board.”

“And now,” Pierce reiterated, “we’re all involved in the continuing process of changing EDAC into the ESD Alliance.”

“I look forward to working with Bob Smith,” he added, “in reviewing the programs the group is investing in – some need to be updated, and some haven’t been looked at in a long time – so when we talk to companies about joining, those organizations that touch every part of chip design can see the value of being part of the Alliance.”

“Of course, for chip design,” Pierce continued, “power, performance and area are still paramount concerns in the day-to-day life of everyone in the ecosystem. Which is why I’ve started to work on promoting the theme that this is what brings the software and the IP and the design flow together.

“Certainly EDA has been thinking along these lines for a long, long time – looking at the physical side of the chips – but the process libraries in the IP world and the process technologies for the foundries are also now part of the equation, and the software that sits on top of the systems.

“The path the ESD Alliance is headed down now will drive things that can’t be done by one company, or one class of companies, things for which the whole ecosystem must function together.

“And although the ESD Alliance is not a standards body, we are in a position to identify where emerging standards might take the industry and to provide the leadership to push for the economic benefits that such standards can provide.

“In particular, consider the importance of power: The California Energy Commission has just come out with power standards that should apply to monitors and desktop PCs. The ESD Alliance has an opportunity to provide leadership in this area.

“Helping to accelerate good design would make all of us more sensitive to the energy demands of the products we create – a definite win for everybody involved. We don’t need any more regulation, at least here in California, but we could work as an organization to coordinate efforts across our industries to help achieve this end.”

“This is the type of conversation,” Pierce said, “that Bob Smith and I are having right now: How can we put the strength of the ESD Alliance to even better use for all?”

Grant Pierce’s admirable sentiments aside – those aimed at fostering a holistic framework within which the ESD Alliance could contribute a defining role – I asked if he could also work on issuing an Executive Order with regards to one of my own favorite agenda items.

Could we get past the formalities, I asked, and start calling the organization ESDA? It’s so much more sleek than The ESD Alliance, so much more in the spirit of the old, succinct EDAC days.

Pierce again laughed, but declined to commit: “Well, I haven’t issued any Executive Orders yet, but if that one seems important, I’ll see what I can do.

“Meanwhile, I think I’ll be busy building relationships with the rest of the Board, to make sure the membership is thriving and that the organization is in a good financial position.

“I also hope we’ll be able to do some experimentation – and in my case, some quick learning – to create a compelling argument for an even larger, even more diverse membership.

“The ESD Alliance offers great opportunities for collaboration that every member company can benefit from. We want to continue to drive home this message across the entire ecosystem.”

********************About Grant Pierce …

Pierce is a co-founder of Sonics, Inc., was elected to the ESD Alliance (formerly the EDA Consortium) Board of Directors in 2014 and will serve as chairman until the next board elections in 2018.

He has served as Sonics’ CEO and President, and as Chairman of the Board of Directors since 1997.

Over the earlier part of his more than 30-year career in high technology, Pierce served in senior management roles in a wide range of companies that built digital media and communications devices, object-oriented software development environments, fabless semiconductors, mini-computer systems, and peripherals.

Pierce is a former CPA, and began his career with Arthur Andersen and Co.

Raise your hand if you think innovation comes out of small, nimble, edgy startups. Keep your hand up if you think consolidation is antithetical to the inventive culture closely associated with small, nimble edgy startups where everybody works outside of their job description and above their grade. Now put your hand down and tell us what you think about yet another merger in the semiconductor industry.

Yes, happy for investors that Qualcomm is buying NXP, but the end result will be a nasty one for technical innovators in EDA. Yet another reduction in the number of customers for EDA tools. Not necessarily a reduction in the number of seats, but a reduction in the number of actual separate corporate entities looking for tools for chip design.

Of course, for those who love large, lumbering organizations with almost as many people in the typing pool as in the engineering pool – more consolidation is great news for the semiconductor business and for the electronic design automation business, as well.

However, for those who still remember when EDA was a Wild West full of crazy startups, wacky business ideas, and loads of shifting sands between a constantly morphing/re-morphing population of EDA startups and an also-always morphing/re-morphing population of chip-design customers – take note: Those days are gone. Forever.

Now it’s just going to be one mega EDA giant versus one of the other two mega EDA giants – which if Cadence buys Mentor will only be one mega giant – as they rumble and lurch through big deals with BIG customers, over golf games, special offsite selling junkets, and enough all-you-can-eat tool packaging deals to sink an aircraft carrier full of bland, tasteless Happy Meals.

Not to mention increasingly ponderous layers of EDA political influence peddling, and enough overt efforts to control the standards conversation in favor of their particular technology to make even Microsoft blush.

After all, the mega-semiconductor customers are only going to allow themselves to be serviced by mega-EDA companies. They will be otherwise impenetrable from an EDA sales point of view, especially if you’re a startup peddling new, untested technologies.

Also an EDA startup buzz killer in the Era of Consolidation? From IT to Purchasing, the fewer EDA tool vendors the better. The customers know it and the Big Three in EDA are rubbing their hands together in ecstasy over the situation.

And so the EDA industry is on the threshold of becoming nothing more than three calcified mega-cities of employees laboring away in huge, behemoth mother ships [read Death Stars] equipped with unlimited fire power. Each one of them more than capable of shooting down even the smallest inkling of out-of-the-box, freewheeling thinking. Able to extinguish with a single cease-and-desist the kind of zany zeitgeist that lead Mad dogs and Englishmen to actually contemplate starting a startup in EDA back in the day.

Yeah, it’s over. EDA as it was is over. Dead. The coffin shut. The lights gone out. The party ended. The bubbles burst. Taps have played out their mournful tune. The sun has set. It’s over.

Now only one question remains.

If you want to do a startup – crazy you. If you want to sorta feel like you are your own boss – crazy you. If you want to do something new, different, with possibly some grand upside potential. What can you do?

It’s simple. Do a startup that provides IP.

Forget about doing tools – although some sort of CAD assist to help integrate your product into the larger design would be helpful – but really, forget the tools.

Do IP.

There’s still a whole universe of opportunities out there in IP. And the needs are so pressing, the opportunities as big as the untamed prairie, the uncharted spaces at yet unmapped.

It won’t be easy, of course. It will require deep subject knowledge, a steady business sense, and nerves of steel to go up against existing IP behemoths such as ARM and Synopsys. But really, life is short. Live on the edge. Do a startup

Do IP.

***************October 27th Press Release …

Qualcomm Inc. and NXP Semiconductors N.V. today announced a definitive agreement, unanimously approved by the boards of directors of both companies, under which Qualcomm will acquire NXP. Pursuant to the agreement, a subsidiary of Qualcomm will commence a tender offer to acquire all of the issued and outstanding common shares of NXP for $110.00 per share in cash, representing a total enterprise value of approximately $47 billion.