Programmable Logic has become more and more common as a core technology used to build electronic systems. By integrating soft-core or hardcore processors, these devices have become complete systems on a chip, steadily displacing general purpose processors and ASICs. In particular, high performance systems are now almost always implemented with FPGAs.
This course will give you the foundation for FPGA design in Embedded Systems along with practical design skills. You will learn what an FPGA is and how this technology was developed, how to select the best FPGA architecture for a given application, how to use state of the art software tools for FPGA development, and solve critical digital design problems using FPGAs. You use FPGA development tools to complete several example designs, including a custom processor. If you are thinking of a career in Electronics Design or an engineer looking at a career change, this is a great course to enhance your career opportunities.
Hardware Requirements:
You must have access to computer resources to run the development tools, a PC running either Windows 7, 8, or 10 or a recent Linux OS which must be RHEL 6.5 or CentOS Linux 6.5 or later. Either Linux OS could be run as a virtual machine under Windows 8 or 10. The tools do not run on Apple Mac computers. Whatever the OS, the computer must have at least 8 GB of RAM. Most new laptops will have this, or it may be possible to upgrade the memory.

GF

I really enjoyed this course. The instructor is by far the best I have encountered on any on-line (or classroom) course. I'm now waiting for the rest of the specialisation.

SD

Apr 24, 2019

Filled StarFilled StarFilled StarFilled StarFilled Star

Simply awsesome, i was unaware of what actually is fpga designing or what days an fpga designer do, now I know the basics of it and am happy to learn, Thanks coursera

From the lesson

Programmable logic design using schematic entry design tools

In module 4 you will extend and enhance your design from module 2, completing the design by adding IP blocks, implementing pin assignments and creating a programming file for the FPGA. One outcome will be improved design productivity, by use of design techniques like pipelining, and by the use of system design tools like Qsys, the system design tool in Quartus Prime. You will complete a Qsys system design by creating a NIOS II softcore processor design, which quickly gives you the powerful ability to customize a processor to meet your specific needs.

Taught By

Timothy Scherr

Senior Instructor and Professor of Engineering Practice

Transcript

Now that you have had some basic training in FPGA design, next you will likely want to develop some design capabilities. In the long term, I tell my students I want them to become dangerous, so expert at their craft that competitors will fear them. This module will help you become much more effective at FPGA design. In module 1, we introduce programmable logic devices and the FPGA. In module 2, we use Quartus Prime to work through a sample FPGA design. In module 3, we learn more about FPGA architectures and capabilities, adding a number of weapons to our arsenal. In this module, we will practice using those weapons, and extend our knowledge of FPGA design by using additional design tools. In the next video, you will further your knowledge of schematic entry for FPGAs by adding an adder circuit to the pipelined multiplier design. You will learn how to add input and output ports to a schematic, how to use the basic symbol library to create low level circuits, and how to create hierarchy in a schematic design. Next, we will improve design entry productivity by the use of IP blocks. We will contrast your previous design entry experience with schematics, to the use of IP blocks to more quickly create your design. You add IP blocks to your design to add some functionality akin to a basic ALU. We will learn to improve timing with pipelining, large combinatorial delays between the input and output can dramatically lower the design maximum frequency. In some cases, combinatorial delays can be broken into pieces by insertion of flip-flops known as retiming, or pipelining. We will learn how pipelining in principle can be applied to improve timing in FPGA designs, and how to use pipelining in IP blocks to improve timing. Next, we'll look at FPGA IO: Getting in and getting out. FPGAs have extensive IO capabilities, including many IO standards and controllable circuit characteristics, but keeping track of the wealth of options can lead to errors. We can reduce IO pin assignment errors, by the use of methods that help document and track IO usage. Differential logic standards like LVDS and LVPECL are increasingly popular in FPGAs as they allow increased speed, and better noise immunity at the same time. We will learn how to handle these interfaces. We'll also learn about making pin assignments spot on. To do this, you'll learn how to do pin assignments using the Pin Planner and the Assignment Editor, how to meet IO standards and control IO properties using the Assignment Editor, and how to check IO assignments using the IO Assignment Analyzer. Essentially, we will learn about programming the FPGA. The Quartus Prime software contains an assembler, which creates the programming file, and a programmer, which downloads the file using a download cable like a USB Blaster II, Byte Blaster II, or Ethernet Blaster II. You will learn how to create the right type of programming file for a given situation, how to set up your hardware chain for programming and which programming mode to use, and how to download a program into the target device. Finally, we will become one with Q. We'll do a Qsys system design. Your training continues with an introduction to Qsys, a system design tool. You will learn how to create a Qsys system, how to build a NIOS II soft-core processor, and how to add memory and peripherals to the NIOS II Qsys design. You will learn how to build a bridge between the processor and the FPGA fabric, and how to bring the Qsys design into the top level to be compiled. In summary, we will learn about the FPGA design flow by working through more example designs in detail using Quartus Prime. Videos in this module will cover FPGA design expertise, advanced schematic entry for FPGA design, including both drawing and hierarchy, improving productivity with IP blocks, improving timing with pipelining, FPGA IO: Getting in and getting out, pin assignments making them spot on, programming the FPGA, becoming one with Q the Qsys system design, and becoming one with Q part II Qsys system design with finishing touches. I hope you're ready to prepare for your mission and make good use of this arsenal of tools, and becoming an expert in FPGA design.

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