Don't forget you'll also need an N-channel FET to turn that top P-channel FET on. And if you do it that way you'd be better off using lower value resistors like 10k:20k and maybe a 10nF cap rather than 100nF to give a low RC constant for charging that cap.Mark.

perky, thanks for feedback. I understand lowering the value of the resistors and using a smaller cap so that the charging time is reduced. I didn't know I would need another N-channel FET to turn the P-channel FET on, not sure how I would hook that up. I found the following article that explains how to use a P-FET to measure voltage: http://fettricks.blogspot.com/2014/01/reducing-voltage-divider-load-to-extend.htmlGoing the transistor route seems more straight forward to me although I understand the drawback is that the transistor leaks current.

The NPN is only needed if you want to drive your load from an active HIGH logic. Otherwise you can directly do it from a digital pin with inverted logic (p-fet is active low). It's a bit less intuitive and the pin has to be left HIGH-z (arduino pin set to INPUT, and write HIGH to it to turn the pfet switch OFF).But yeah otherwise use a NPN to drive it just as any other active high load.

The NPN is only needed if you want to drive your load from an active HIGH logic. Otherwise you can directly do it from a digital pin with inverted logic (p-fet is active low). It's a bit less intuitive and the pin has to be left HIGH-z (arduino pin set to INPUT, and write HIGH to it to turn the pfet switch OFF).But yeah otherwise use a NPN to drive it just as any other active high load.

Remember that the I/O pin cannot go above Vdd+0.3V of the processor, otherwise the substrate diode will conduct and your P-FET will be permanently on (assuming you're switching a voltage that is above Vdd). You either need a capacitor in series with the I/O pin to create a pulse or limit the voltage on that pin by driving an NPN or N-FET to turn the P-FET on.Mark.

@ssmall BTW the NDP6020P you quoted has a Vgs max of +/- 8V, you'll violate that spec if you're swiching voltages above 8V unless you use an additional resistor to create a voltage divider. I'd choose one with +/- 20V spec. Also very low RDSon is not really needed if you're switching into a 10k load, even 10 ohms RDSon would only represent a 0.1% error. What you need is a P-FET with a low enough gate threshold to ensure it is hard on under lowest voltage switching conditions and with a max Vgs that is above your maximum swiching voltage.Mark.

@perky The input voltage will be a max of 6V. I found this P-FET that has a Vgs of +/- 20, an RDSon of 10 ohms a Vgs(th) min -1 to max -2. http://www.mouser.com/ds/2/268/TP2104%20C081313-846395.pdf I am not confident I am looking at the correct values on the data sheet. I also want to make sure I get an Enhancement type P-FET, correct? I have also been reading up how FETs work. Thanks again

I wanted to report back on my progress. I was able to implement both circuits successfully. I do have a few more questions.

1) Why is a resistor needed between the Gate and Source of the FET(s)?2) I had to put a 200ms delay after pin A3 is set to LOW and the analog measurements are taken. Is that because the capacitor needs to charge? I am using a .1uf cap in parallel with a 470k resistor, just like the picture.

Can you post the schematic of the circuit you're using? Setting A3 low implies you're driving the gate of the PET directly from the MCU. If the voltage your trying to measure is above the MCU's Vcc the FET might be on permanently. The resistor is because the gate is usually driven by an open drain or open collector signal, or at least one with capacitor in series from an MCU pin.

Firstly the MCU has things called substrate diodes, basically these are diodes at an I/O pin that stop the voltage on it going above Vcc+0.3V or below GND-0.3V. If the input to A3 goes above the MCU's Vcc by 0.3V the diode will conduct, and the voltage at A3 will be clamped to Vcc + 0.3V. Let's ay your Vin is 6V and Vcc is 3.3V, this means the A3, and hence the gate, will be at 3.6V and current will flow through the resistor (in this case with a 10k resistor it will be about 240uA). It also means the FET will be permanently on.

There are two solutions to this, either place a capacitor in series at the A3 pin which will create a negative going pulse on the gate due to the RC constant it creates with the resistor, or use an open drain or open collector driver such as the N-channel FET to drive the gate. In either case you prevent voltages at the A3 pin going above Vcc+0.3V.

Also as you saw the capacitor will need to charge up, and the RC constant for that depends on the values of your potential divider resistors and the capacitor value. This constant is quite long in your diagram. If you are going to switch the supply you don't need high value resistors for this (and 100nF is probably excessive), it would be better to use maybe 10k and 4k7 resistors and a 10nF capacitor, that means you'll only need to wait about 3ms to get a stable voltage.