The main processing elements of the system are Xilinx
XC2VP20 FPGAs. Although they do contain embedded PowerPC cores, those are not used - instead,
a fully custom processing pipeline is implemented.

The pipeline starts with the pattern generator. This block supplies
inputs to the hash computation core, iterating through the code space.

Bulk of the chip is taken up by the hash core, which is a fully
unrolled implementation of a hash function. This way, results are produced at a rate of one
per cycle.

The resulting hashes are passed to the lookup block, which takes the
first 32-bit section of the hash and checks whether it matches one of the few hundred selected
ones. This operation is also executed at a single-cycle repeat rate. Since the rate of matches
can exceed the rate of PC readback, and no hashes can be allowed to get lost, successive hashes
are merged into min/max ranges that have to be later traversed by the PC.

Matching hashes (or hash ranges) are sent through a switch infrastructure as packets to the
supervising PC. The PC recreates and compares the rest of the hash (not just the first 32-bits)
and saves results for later retrieval.

The complete SHA-1 chip Verilog source can be found here.
The MD5 chip uses most of the files from the SHA-1 one, and the new hash & toplevel is
here.