Records of the 1999 IEEE International Workshop on Memory Technology, Design and Testing

This paper presents characterization methods for an SDRAM in a manufacturing environment. Contact tests, dc tests, basic functional tests, signal margin tests and retention characterization are shown. Measurement of the cell signal is used as an example for pico probing. Special test modes for SDRAMs which can be used to aid characterization and failure analysis (FA) are discussed.
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This paper describes a method to determine threshold voltage (V th) distribution as a multi-colored bitmap of the die. That is, a visual indication of relative threshold voltages on different areas of the die is provided. The spatial distribution of threshold voltage is felt to be more informative than conventional techniques which provide results as a bell-curve Gauss distribution plot...
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The use of special purpose complex embedded memories is becoming increasingly common. Their complex functionality, large sizes, decreasing feature sizes, and limited controllability/observability combine to make testing ever more difficult. In this paper, we describe a built in self test (BIST) method for testing ring addressed first in first out memories (FIFOs) that use transparent input latches...
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The new concept of an unbalanced, hierarchically-divided cache memory system is introduced and analyzed. This approach generalizes existing cache structures by allowing different memory references (e.g. as possibly unevenly divided within an address-space) to be subject to various levels of caching as well as varied amounts of cache at each level. Under the assumption that the total cache size at ...
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This paper presents a novel approach for detection and diagnosis (with no confounding or aliasing) of interconnect faults (short and stuck-at) in a system consisting of multiple RAM chips connected through busses. These systems (referred to as a bus-connected multi RAM systems, or BCMRS) are characterized by multiple types of lines (bus and driver lines), disjoint busses (address and data) as well...
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Continuing improvements in semiconductor fabrication density are enabling new classes of system-on-a-chip architectures that combine extensive processing logic and high-density memory. Many of the capabilities of these new architectures can be custom tailored to the demands of real-time digital image processing. This paper evaluates several candidate designs, using the criteria of image processing...
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A behavioral analysis of transistor faults and cell-stuck-at faults in a n-word by l-bit static CMOS CAM array is presented. First, a CAM cell is analyzed at the transistor-network, event-sequence and finite-state machine level. Then, a transistor stuck-(on/open) and cell-stuck-at fault model for a CAM is defined. We show that two out of eighteen possible CAM cell's transistor faults cannot be tes...
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Dynamic Associative Access Memory (DAAM) chips are processor-in-memory chips wherein a large number of small processing elements are put in a DRAM's sense amps. Thousands of these chips will be mounted on “memory boards” in “TONY” full-text database servers. This paper shows that multibank memory eliminates DRAM latency, and a one-bit ALU that can be made into an associativ...
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Using in-line defect data, critical area analysis of cell layout, and a rule-based algorithm to associate critical areas with electrical faults, we can determine the optimum redundancy configuration for any memory circuit. The technique predicts the yield for a range of redundancy configurations and finds the optimum number of redundant rows and columns for any memory design based on yield and die...
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In the manufacturing process of memory modules (such as SIMMs and DIMMs), first memories are tested at the die level, then at the chip level, and finally at the module level. For the latter special module testers are available. This paper gives an analysis of commercially available module testers and shows their restrictions. Then it lists the requirements for a more advanced module tester, after ...
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Construction analysis is a useful tool to determine microcircuit structure and identify potential failure mechanisms. Cross sectioning procedures used in construction analysis have revealed two possible failure mechanisms. One mechanism involving the use of SOG results in poor adhesion and delamination. The other mechanism permits the corrosion of internal conductors through a combination of disco...
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Multilevel DRAM (MLDRAM) attempts to increase storage density by recording more than one bit per cell. Several different two-bit-per-cell schemes have been described in the literature; however it is difficult to compare them directly because the original papers use different technologies and operating conditions. This paper presents a detailed simulation study that compares three published MLDRAM ...
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It seems likely that density concerns will force the DRAM community to consider using radically different schemes for the implementation of memory devices. We propose using nano-scale carbon structures as the basis for a memory device. A single-wall carbon nanotube would contain a charged buckyball. That buckyball will stick tightly to one end of the tube or the other. We assign the bit value of t...
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This paper presents an extensive summary of the latest developments in low-power circuit techniques and methods for Static Random Access Memories. The key techniques in power reduction in both active and standby modes are: capacitance reduction by using divided word-line structure or single-bitline cross-point cell activation, pulse operation by using ATD generator and reduced signal swings on hig...
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High speed graphics subsystems used some of the earliest application specific DRAMs. Knowledge gained from working with these specialized parts has provided a background for many of the innovations seen today in high speed DRAMs, fast core DRAMs, and high bandwidth embedded DRAMs. Years before synchronous DRAMs become common, clocked DRAM field memories for television frame buffers were in product...
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