Semiconductors are racing toward the 1-V operating voltage mark to achieve higher speeds and use less power. But as they do, a significant hurdle is created for the dc-to-dc converter. Also, since 1-V operating voltage is anticipated first in portable systems, the added pressures on the power supply efficiency and power density present an even bigger challenge.

Besides the demand for extra functionality there is also the requirement for extra battery life and reduced system form factor. This presents an enormous challenge to the design engineers responsible for making the user's requirements a reality. As functionality is added inside the portable system with extra memory capability, faster processing speeds, Internet access with higher bandwidth capability and more, the power required also increases.

The result is an almost exponential rise in current requirements in next-generation portable systems. This alarming rate of increased current required to power the loads and resulting power consumption at the loads have combined to make staying within system thermal limits a huge problem. And, the problem is only accentuated with shrinking system size, thus reducing the ability of the system to deal with the heat efficiently and creating overheating conditions. That is why the trend is toward 1-V operating voltages.

This trend in portable system architecture is demanding improvements in the power electronics within the system so that better electrical and thermal efficiency is achieved, thus creating less heat. It is extremely difficult to achieve 1-VOUT operation while keeping electrical efficiency high. As the differential between input voltage and output voltage increases, the more difficult it is to attain good performance. So as the world moves toward 1 VOUT for the load, there are several concerns when it comes to finding suitable solutions to the problem of higher performance, smaller form factor and longer running portable systems.

One of today's portable systems requiring low operating voltages is the notebook PC, which operate up to 21 VIN and 1.3 VOUT for the core CPU dc-dc application. These systems tend to operate at high output currents-15 Apk-and 1-VOUT operating voltage is on the horizon. As portable systems are moving toward 1 VOUT, the adoption of this system architecture is most likely to appear in the lower-power portable systems first. The class of handhelds like personal digital assistants (PDA) are extremely sensitive to increased power dissipation. They must be extremely small; as functionality increases, there are obvious concerns that thermal capabilities will be exceeded.

Many types of portable systems use the synchronous buck dc-dc topology and system dynamics dictate that it is increasingly difficult to design an efficient converter as output voltage decreases with respect to the input voltage. This is because the ratio of output voltage to input voltage is directly proportional to the duty cycle of the power MOSFETs in the dc-dc converter. The more the output voltage decreases, the longer the synchronous FET, Q2, has to conduct and the more the switching losses are critical for the control FET, Q1. In some systems the duty cycle is already at 95 percent for the synchronous FET and 5 percent for the control FET. If the duty cycle for the control FET reduces even further it makes the control of the dc-dc converter very difficult. Also, the synchronous FET conduction time increases, and in some cases the on-state resistance required for the synchronous FET is so low that the designer can no longer use just one device; instead, two devices have to be used in parallel. With aggressive power density targets the solution footprint needs to be kept to a minimum to make it possible to reduce system size.

So as the application becomes more and more challenging to design for, the improved optimization of power semiconductor components is required to enable system trends for performance. The intent of power semiconductor optimization is to improve power density, increase efficiency, reduce component count, reduce board space and board layout complexity and reduce design effort. These factors will help speed the trend toward 1-VOUT operating voltages in portable systems, and increased system functionality, increased battery life and reduced size.

With increased demands on the power semiconductors for 1-VOUT applications, further optimization for the critical parameters is necessary. As already explained, the critical parameter of the control MOSFET is the switching characteristic since it has very low duty cycle, depending on the VOUT-to-VIN ratio. The device characteristic that requires optimization is the switching charge, or Qsw. This is the charge during the switching period that actually creates power dissipation, otherwise known as the post-gate threshold-related charge. We want to reduce Qsw as much as possible to reduce the switching loss on the device and hence help reduce overall loss on the device. There are other contributors to power loss on the control MOSFET, but the main one besides Qsw is on-state resistance, or RDS(on), in cases where peak current is also high.

The product of Qsw and RDS(on) is known as the figure of merit, for the control FET. The objective is to reduce Qsw and RDS(on) in order to reduce that overall figure. This is an overwhelming challenge to silicon designers, since reducing one of these parameters usually means increasing the other parameter. There is a range of silicon platform technologies to choose from and the right one has to be selected in order to optimize for the figure of merit as described.

The synchronous MOSFET has another set of optimization criteria required for such aggressive applications. Since the duty cycle is extremely long for this device and since peak load currents can be high, it is very important to reduce the RDS(on) as much as possible. This is the primary figure of merit for the synchronous FET. Considerations for switching loss for the synchronous FET are not as important, since the device operates under a zero-voltage switching condition. However, it is also important to look at secondary optimization criteria for the synchronous FET.

High-frequency switching dc-dc converters can have problems with unintended turn-on of the synchronous FET if it is not optimized correctly. When the control FET turns on, the voltage on the switch node (source of the control FET and drain of the synchronous FET) rises with a certain rate of voltage vs. time, dv/dt. The dv/dt can be fast enough that it can couple with the parasitic capacitance of the synchronous FET, CGD, so that it produces a voltage spike on the gate of the synchronous FET. If that spike is greater than the threshold voltage, the FET will turn on. Since under this condition both the control and synchronous FETs are on, a short-circuit is produced across the input power supply, and a huge shoot-through current occurs. That severely derates the performance of the circuit and can cause excessive heat or failures or both. The designer can prevent unintended turn-on, otherwise known as Cdv/dt-induced turn-on, by optimizing the charge ratio on the synchronous FET. If QGD/QGS1 = 1, immunity to the effect is achieved. QGS1 is the pregate threshold charge.

The synchronous buck topology also uses a Schottky diode in parallel with the synchronous FET for improved efficiency during dead time, which is the built-in delay between switching signals provided to the FETs to prevent cross-conduction. During dead time conduction, the current flows through the Schottky instead of the body diode of the synchronous FET. That is the intent, since the forward voltage, or VF, of the Schottky is lower than that of the body diode of the FET. The VF is the parameter of the diode that contributes to dead time power loss; the lower the VF, the more efficient the dead time will be. It is also critical that the inductance associated with the parallel connection of the Schottky is low, since that may contribute to increased VF of the Schottky and can even eliminate the Schottky advantage over the body diode VF. It is therefore important to optimize the pc board layout to reduce or eliminate the stray inductance as much as possible.

It is critical that the solutions for 1-VOUT applications address all of these key optimization parameters for improved electrical efficiency. In addition, since the market demands improved power density it is critical to offer solutions with smaller footprints and performance that at least equals the preceding larger solutions. The requirement for increased levels of power density is driving the trend toward higher levels of integration for power semiconductor solutions. These new trends help trim component count and board space, and also help reduce stray inductance in the circuit.

One such solution, the Dual FETKY IRF7901D1, offers all of these benefits. Moreover, its extremely high efficiency at 1-VOUT operating conditions-more than 85 percent-has been demonstrated. This solution saves up to 60 percent of board space with vastly increased power density over industry-standard discrete solutions that may use three devices: two SO-8-style MOSFETs and an SMA- or SMB-style Schottky diode. The Dual FETKY integrates all power semiconductors into a single SO-8 package. This device has fully optimized MOSFET and Schottky semiconductors ideal for use in portable-system synchronous buck dc/dc converters requiring up to 5-A peak output current.

Taming complexity

In addition, the Dual FETKY helps reduce circuit-board layout complexity, since there are interconnects inside the package linking the control FET, synchronous FET and Schottky diode in the configuration of the synchronous buck dc/dc converter. This actually helps reduce the stray inductance of these interconnects as it helps reduce the external pc-board area that would be used for traces. The Dual FETKY provides an easy-to-use "functional block" for the power semiconductor portion of the dc/dc converter.

In-circuit efficiency of the Dual FETKY for negative-voltage operation is high-about 87 percent peak. It also achieves extremely high efficiency of up to 94 percent and 96 percent, respectively, in 3.3-VOUT and 5-VOUT applications commonly found in notebook PCs for peripheral load applications.

Solutions like the Dual FETKY will help provide the improved performance levels required to meet the industry trend toward adoption of lower operating voltages in portable systems, down toward 1 VOUT.