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H.-G. Moser July 25, 2012 SOI: Shin Etsu 5 Shin Etsu agreed to produce 5 test wafers First two wafers show good quality: Very good polishing Extremly low metal contaminations However some roughness of the top wafer edge and (very few) etch pits were found Recently we got the remaining wafers, Shin Etsu ‘fine tuned’ their process Quality improved and is now very good We gave Shin Etsu green light to produce 30 SOI wafers Thanks to Laci Andricek who worked on the SOI for years!

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H.-G. Moser July 25, 2012 Production Schedule 8 Total production time of a batch: 2 years First wafers leave clean room (before thinning): End 2013: yield test! First sensors available (thinned and cut): July 2014

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H.-G. Moser July 25, 2012 Gated Mode: Measurements 10 Gated mode successfully tested in the lab (laser) and test beam TB: Signal distribution of pixels which have been hit by a track when gated was on (from track extrapolation) MC: normal noise distribution A real signal should be here Protection: the signal of a real hit is still present after gating: Signal before gate (not cleared) Signal after gate Gate on

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H.-G. Moser July 25, 2012 Gated Mode: System Aspects 11 Problem: the clear gates of all pixels have to be pulsed within 1µs => Large capacitance (16nF), large peak currents, instable control signals Decoupling 10nF Decoupling 100nF More simulations needed Have to optimize circuit and place additional decoupling capacitors (where?) Switcher modified for gating has already been submitted (back in September) Exact timing and synchronization still needs to be fixed Gating w/ or w/o readout?

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H.-G. Moser July 25, 2012 Conclusions Good news: SOI problems resolved (ICEMOS & Shin Etsu). PXD9 production has started Injection Noise: Gated operation demonstrated in test beam Working on system implementation Modified switcher submitted Background occupancy and radiation damage under control We have working prototypes of all ASICs (Milestone!) Not covered in this talk: Good progress for: DHH/DAQ, Power Supplies, Services, Cooling … 16