The Crossbar, shown in Figure 1, is a multiplexer
that maps the Port I/O pins to internal hardware
peripherals on the device. For example, it
determines to which port pins RXD and TXD of the
UART get mapped.

The Crossbar governs the pin mapping of the
SMBus, the SPI, the UART, the Timer Capture
Modules, the External PCA Input, the comparator
outputs, the Timer external inputs, /SYSCLK, and
the A/D conversion start input. The Crossbar must
be configured and enabled before the I/O of any
of these peripherals can be accessed.

Unassigned port pins operate as normal GPIO.

The Crossbar provides two key system benefits:
• All unassigned GPIO port pins on Port 0,
Port 1, and Port 2 are grouped contiguously.
• It provides flexibility in peripheral selection
for reduced pin-count devices where some
I/O ports may not be available. Peripheral
selection is limited only by the number of
port pins available, not by which port pins
are available. This allows the system
designer to choose which digital peripherals
are available at the digital I/O pins on a pin-
limited device.

Figure 1. Crossbar Decoder Block Diagram
Application Note 01
Cygnal Integrated Products Inc. AN01-1.1
2
Key Points
• The Crossbar MUST be enabled in order to
use any Port 0, Port 1, or Port 2 port pins as
outputs.
• The Crossbar registers should be configured
before any of the digital peripherals are
enabled.
• The Crossbar registers are typically
configured once at reset, near the top of the
Reset handler, and then left alone.
• The Crossbar settings change the pinout of
the device.
• Each Crossbar setting results in a device
pinout that is unique. If you enable or
disable peripherals in the Crossbar, the
pinout WILL change.
• The output mode of the port pins (open-
drain or push-pull) must be explicitly set for
the output port pins, even those assigned by
the Crossbar. Exceptions to this are the
SDA and SCL pins on the SMBus and the
RX pin on the UART, which are
automatically configured as open-drain.
• The open-drain or push-pull mode of
Crossbar-assigned input pins (like NSS or
/INT0, for example) is not important. These
pins are configured as inputs regardless of
the corresponding Port Configuration
Register setting.
• To configure a GPIO pin as an input, the
Port Configuration Register bit associated
with that pin must be cleared, which selects
that pin to have an open-drain output.
Additionally, the Port bit associated with that
pin must be set to a ‘1’ which tri-states the
pin or loosely pulls it high if WEAKPUD in
XBR2 is set to ‘0’. This is the reset
configuration of the port pins.
• The value at the port pins can be read at
any time by reading the associated port
SFR, regardless of the Crossbar register
setting or whether the pin is configured as
an input or an output.
• The Enable bits in the Crossbar registers
are unique and distinct from the enable bits
in the digital peripherals themselves.
o Peripherals do not need to be
enabled in the Crossbar in order to
be used (for example, a PCA
module can generate interrupts
even if its output is not routed to a
pin).
o Peripherals that are enabled in the
Crossbar, but disabled in their own
SFRs still control the port pins. That
is, the port pins can be read at any
time, but the outputs are controlled
exclusively by the owning peripheral
and cannot be accessed as general-
purpose outputs.
• The four external interrupts on Port 1
(P1.[4..7]) are triggered by a falling edge at
the pin, regardless of the source of the
falling edge, the Crossbar setting, or the
output mode of the port pin.
• Unlike the standard 8051, true push-pull
outputs are provided. If the ‘strong-then-
weak’ pull-up function of the 8051 is
required, it can be emulated in software by
configuring the associated port output as
‘push-pull’ followed by a configuration to
‘open-drain’.
Determining Device Pinout
This section describes how to use the Priority
Crossbar Decode Table, Table 4, to determine the
device pinout based on peripheral selection in the
Crossbar registers, which are listed in Figures 2
through 4.

To determine the pinout, first configure the Crossbar
registers based on the peripherals needed. Then
starting at the top of the Priority Crossbar Decode
table, scan down until you reach the first enabled
device. This device will use P0.0, and if more pins
are required, they will be assigned in order from
P0.1 up. For example, if the SPI is the first
peripheral enabled, then SCK MISO MOSI and NSS
will be mapped to P0.0, P0.1, P0.2, and P0.3
respectively. The next enabled device will be
assigned P0.4. All unassigned pins behave as
GPIO.
Example 1
Assume that the application calls for:
• SPI
• UART
• 2 capture modules
• /INT0
• T2
Referencing the Port I/O Crossbar Register
descriptions, which are listed in Figures 2 through 4
for convenience, the Crossbar registers are
configured as follows:
XBR0 = 00010110b ; enable UART, 2 capture
; modules, and SPI
XBR1 = 00100100b ; enable T2 and /INT0
XBR2 = 01000000b ; enable Crossbar
Application Note 01
Cygnal Integrated Products Inc. AN01-1.1
3

Example Usage of XBR0, XBR1, XBR2:
When selected, the digital resources fill the Port I/O pins in order (top to bottom as
shown in the Priority Crossbar Decode Table) starting with P0.0 through P0.7, and then
P1.0 through P1.7, and finally P2.0 through P2.7. If the digital resources are not
mapped to the Port I/O pins, they default to their matching internal Port Register bits.