Summary: The Development of High Performance FFT IP Cores through
Hybrid Low Power Algorithmic Methodology
Wei Han, A. T. Erdogan, T. Arslan, and M. Hasan
School of Engineering and Electronics
University of Edinburgh, Edinburgh EH9 3JL, Scotland, UK
w.han@ed.ac.uk
Abstract - This paper presents a solution based on
parallel-pipelined architectures for high throughput and power
efficient FFT IP cores. Low power consumption can be gained
through the combination of hybrid low power algorithms and
architectures. A number of IP cores have been implemented for
the comparison of the impact of parameterization on
power/area/speed performance. The results show that up to
55% and 52% power saving can be achieved by the
combination of the above techniques for 64-point
4-parallel-pipelined FFT and 16-point 2-parallel-pipelined FFT
respectively, as compared to R4SDC pipelined FFTs.
I. Introduction
The FFT processor is used in a wide range of DSP and
communication applications, such as radar signal processing