True Televisions have the CRT Tube !!
Welcome to the Obsolete Technology Tellye Web Museum. Here you will see a TV Museum showing many Old Tube Television sets
all with the CRT Tube, B/W ,color, Digital, and 100HZ Scan rate, Tubes technology. This is the opportunity on the WEB to see, one more time, what real technology WAS ! In the mean time watch some crappy lcd picture around shop centers (but don't buy them, or money lost, they're already broken when new) !!!

Richtige Fernseher haben Röhren!

Richtige Fernseher haben Röhren!

In Brief: On this site you will find pictures and information about some of the electronic, electrical and electrotechnical technology relics that the Frank Sharp Private museum has accumulated over the years .

Premise: There are lots of vintage electrical and electronic items that have not survived well or even completely disappeared and forgotten.

Or are not being collected nowadays in proportion to their significance or prevalence in their heyday, this is bad and the main part of the death land. The heavy, ugly sarcophagus; models with few endearing qualities, devices that have some over-riding disadvantage to ownership such as heavy weight,toxicity or inflated value when dismantled, tend to be under-represented by all but the most comprehensive collections and museums. They get relegated to the bottom of the wants list, derided as 'more trouble than they are worth', or just forgotten entirely. As a result, I started to notice gaps in the current representation of the history of electronic and electrical technology to the interested member of the public.

Following this idea around a bit, convinced me that a collection of the peculiar alone could not hope to survive on its own merits, but a museum that gave equal display space to the popular and the unpopular, would bring things to the attention of the average person that he has previously passed by or been shielded from. It's a matter of culture. From this, the Obsolete Technology Tellye Web Museum concept developed and all my other things too. It's an open platform for all electrical Electronic TV technology to have its few, but NOT last, moments of fame in a working, hand-on environment. We'll never own Colossus or Faraday's first transformer, but I can show things that you can't see at the Science Museum, and let you play with things that the Smithsonian can't allow people to touch, because my remit is different.

There was a society once that was the polar opposite of our disposable, junk society. A whole nation was built on the idea of placing quality before quantity in all things. The goal was not “more and newer,” but “better and higher" .This attitude was reflected not only in the manufacturing of material goods, but also in the realms of art and architecture, as well as in the social fabric of everyday life. The goal was for each new cohort of children to stand on a higher level than the preceding cohort: they were to be healthier, stronger, more intelligent, and more vibrant in every way.

The society that prioritized human, social and material quality is a Winner. Truly, it is the high point of all Western civilization. Consequently, its defeat meant the defeat of civilization itself.

Today, the West is headed for the abyss. For the ultimate fate of our disposable society is for that society itself to be disposed of. And this will happen sooner, rather than later.

OLD, but ORIGINAL, Well made, Funny, Not remotely controlled............. and not Made in CHINA.

How to use the site:

- If you landed here via any Search Engine, you will get what you searched for and you can search more using the search this blog feature provided by Google. You can visit more posts scrolling the left blog archive of all posts of the month/year,or you can click on the main photo-page to start from the main page. Doing so it starts from the most recent post to the older post simple clicking on the Older Post button on the bottom of each page after reading , post after post.

You can even visit all posts, time to time, when reaching the bottom end of each page and click on the Older Post button.

- If you arrived here at the main page via bookmark you can visit all the site scrolling the left blog archive of all posts of the month/year pointing were you want , or more simple You can even visit all blog posts, from newer to older, clicking at the end of each bottom page on the Older Post button.So you can see all the blog/site content surfing all pages in it.

- The search this blog feature provided by Google is a real search engine. If you're pointing particular things it will search IT for you; or you can place a brand name in the search query at your choice and visit all results page by page. It's useful since the content of the site is very large.

Note that if you don't find what you searched for, try it after a period of time; the site is a never ending job !

Every CRT Television saved let revive knowledge, thoughts, moments of the past life which will never return again.........

Many contemporary "televisions" (more correctly named as displays) would not have this level of staying power, many would ware out or require major services within just five years or less and of course, there is that perennial bug bear of planned obsolescence where components are deliberately designed to fail and, or manufactured with limited edition specificities..... and without considering........picture......sound........quality........

The idea of digitization of TV functions is not new. The time some companies have started to work on it, silicon technology was not really adequate for the needed computing power so that the most effective solutions were full custom designs. This forced the block-oriented architecture where the digital functions introduced were the one to one replacement of an existing analog function. In Figure 2 there is a simplified representation of the general concept.

Fig.2: Block Diagram of first generation digital TV set

The natural separation of video and audio resulted in some incompatibilities and duplication of primary functions. The emitting principle is not changed, redundancy is a big handicap, for example the time a SECAM channel is running, the PAL functions are not in operation. New generations of digital TV systems should re-think the whole concept top down before VLSI system partitioning.

In today’s state-of-the-art solution one can recognize all the basic functions of the analog TV set with, however, a modularity in the concept, permitting additional features becomes possible, some special digital possibilities are exploited, e.g. storage and filtering techniques to improve signal reproduction (adaptive filtering, 100 Hz technology), to integrate special functions (picture-in-picture, zoom, still picture) or to receive digital broadcasting standards (MAC, NICAM). The Figure 3 shows the ITT Semiconductors solution which was the first on the market in 1983 !! !!

Fig.3: The DIGIT2000 TV receiver block diagram

Description:This invention relates generally to digital television receivers and, particularly, to digital television receivers arranged for economical interfacing with a plurality of auxiliary devices.

With the proliferation of low cost microprocessors and microprocessor controlled devices, television (TV) receivers are being designed to utilize digitized signals and controls. There are many advantages associated with digital TV receivers, including uniformity of product, precise control of signal parameters and operating conditions, elimination of mechanical switches and a potential for reliability that has been heretofore unknown. Digital television receivers include a high speed communication bus for interconnecting a central control unit microprocessor (CCU) with various TV function modules for processing a TV signal. These modules include a deflection processing unit (DPU), a video processing unit (VPU), an automatic phase control (APC), a video codec unit (VCU), an audio analog to digital converter (ADC) and an audio processing unit (APU). The CCU has associated with it a non-volatile memory, a hardware-generated clock signal source and a suitable interface circuit for enabling the CCU to control processing of the TV signal throughout the various TV function modules. The received TV signal is in analog form and suitable analog to digital (A/D) converters and digital to analog (D/A) converters are provided for converting the digital and analog signals for signal processing and for reconverting them after processing for driving a cathode ray tube (CRT) and suitable speakers. The CCU microprocessor is heavily burdened because of the high speed timing required to control the various TV function modules.
To further complicate matters, modern TV receivers are increasingly being used with auxiliary devices for other than simple processing of TV signals. For example, the video cassette recorder (VCR) has enabled so-called "time-shifting" of program material by recording TV signals for later, more convenient viewing. The VCR is also extensively used with prerecorded material and with programs produced by users having access to a video camera. Other auxiliary devices providing features such as "Space Phone" whereby the user is enabled to make and receive telephone calls through his TV receiver, are desirable options. Additionally, a source selector auxiliary device enables a host of different signal sources, such as cable, over-the-air antenna, video disk, video games, etc. to be connected for use with the signal processing circuitry of the TV. In addition, all of these many auxiliary devices are preferably controllable from a remote position. A great deal of flexibility is available since each of the above auxiliary devices includes a microprocessor for internally controlling functioning of the device.
In the digital TV system described, the CCU microprocessor and the microprocessors in the auxiliary devices may be conventionally arranged to communicate over the main communication bus. Such a system would entail a specialized microprocessor with a hardware-generated clock signal in each auxiliary device in order to communicate at the high speeds used on the main communication bus. A specialized microprocessor, that is, one that is hardware configured, is significantly more expensive than an off-the-shelf microprocessor. Also, the auxiliary devices may not be required, or even desired, by all users and their low volume production cost becomes very important. It would therefore be desirable to provide a digital TV in which such auxiliary devices utilized off-the-shelf microprocessors for their control.

A digital TV system includes a CCU that is interconnected by a three-wire, high speed bus to a plurality of TV signal function modules for controlling operation thereof by means of a high speed hardware generated clock signal. A software generated clock signal in the CCU is supplied on a low speed two-wire auxiliary device bus which is connected to microprocessors in a plurality of auxiliary devices for performing functions ancillary to TV signal processing. The microprocessor in each auxiliary device is an off-the-shelf type that does not require any special hardware because the timing on the auxiliary device bus is sufficiently slow to enable software monitoring of the line and data transfer.
As mentioned, the three-wire IM bus 21 is a high speed bidirectional bus in which CCU 20 functions as the master and all of the interconnected TV signal processing function modules are slaves that communicate with the CCU in accordance with the protocol established for the system. CCU 20 is also indicated as including a software generated clock which supplies a two-wire auxiliary device bus 50. Two-wire bus 50 includes a clock lead 51 and a data lead 52 coupled to a plurality of auxiliary devices. A VCR 54, including an off-the-shelf microprocessor 55, is coupled to bus 50. A Source Selector 56, including an off-the-shelf microprocessor 57, is also coupled to bus 50. Source Selector 56 has access to four RF inputs, two baseband video and audio inputs and one separate baseband audio input. It will be appreciated that Source Selector 56 may have a greater or lesser number of signal sources to which it has access. Source Selector 56 outputs are coupled to VCR 54 and also to tuner 10 and supply, under control of CCU 20 and keyboard 44, the signal from the signal source selected by keyboard 44 or IR transmitter 46 for use with the digital TV. Auxiliary device bus 50 is also coupled to a Space Phone 58 which includes an off-the-shelf microprocessor 59 and a modem 60 that is connectable to a conventional telephone terminal.
Two-wire auxiliary device bus 50 is a relatively low speed bus and there is no need for separate hardware generated clock signals to be developed by the auxiliary device microprocessors. As mentioned above, this feature involves a significant savings in the cost and complexity of the auxiliary devices.
The protocol used on the two-wire auxiliary device bus consists of a 16 bit sequence, the first eight bits of which are used for bus address commands for the auxiliary devices. Each auxiliary device may respond to 16 addresses which allows the CCU to write into or read from various storage registers in the devices which are used for control or data storage. Thus, with this low cost system, as many as 16 auxiliary devices may be connected to the auxiliary device bus. The second eight bits of the 16 bit sequence contain data which is either transferred from the CCU to the auxiliary device addressed, or transferred from the auxiliary device to the CCU, based upon the bus address used. Thus, the various bus addresses to which a given auxiliary device will respond determine whether the auxiliary device will receive data from the CCU or send data to the CCU. The clock line timing, generated by software in CCU 20, is slow enough to permit software monitoring of the line and data reception by simple auxiliary device microprocessors that are not equipped with an external interrupt feature. The timing on the auxiliary device bus is made sufficiently fast to avoid too many instruction steps or the need for special registers in CCU 20. In the system described, data is clocked every 82.5 microseconds, thus permitting a 16 bit word to be clocked in 1.32 milliseconds. A pause of 277.5 microseconds between the first 8 bits and the second 8 bits permits the slave auxiliary device to process the bus address data contained in the first 8 bits. This timing fits into the 2 millisecond timing block structure used for the CCU in controlling the DIGIT 2000 digital TV. Two-2 millisecond timing blocks have been established in the CCU, which has a 20 millisecond timing loop divided into ten-2 millisecond timing blocks. Thus, two control words may be sent to an auxiliary device every 20 milliseconds, or a request by the CCU to receive data and the actual receipt of that data may take place in that time period.

Referring to the drawing, a digital TV includes a tuner 10 coupled to an IF/Detector 12 which has a pair of outputs 13 and 14 supplying video and audio signals, respectively. Control signals for tuner 10 are supplied through an interface circuit 16 from a CCU microprocessor 20 which functions as a single master control unit for the system. Microprocessor 20 is interconnected by means of a bidirectional three-wire IM (Intermetal) bus 21 to a DPU 22, a VPU 26, an APC 30, a TTX (teletext processor) 38, an APU 36, an ADC 32 and a non-volatile memory 24. A serial control line 29 interconnects a hardware generated clock 28, VPU 26 and VCU 34. VPU 26 and VCU 34 are also interconnected by a seven wire cable and TTX 38 is interconnected with a DRAM 42. DRAM 42 is a dynamic RAM in which TTX information is stored for display. VCU 34 is supplied with video signal and supplies a digitized 7 bit grey coded video signal to VPU 24 for processing and RGB color signals to a Video Drive 40 which, in turn, supplies a cathode ray tube (not shown). A keyboard 44 is coupled to CCU 20 and includes an IR detector that is responsive to coded IR signals supplied from an IR transmitter (IRX) 46. A resident microprocessor in keyboard 44 decodes the received IR signals and generated control commands and supplies appropriate outputs to CCU 20. The diagram, as described, is substantially identical to that for a "DIGIT" 2000 VLSI Digital TV System developed by ITT Intermetal and published in Edition 1984/85 Order No. 6250-11-2E

.POSITIVE AND NEGATIVE OUTPUT CURRENT
UP TO 1.2AAND – 1.7A .A TWO LEVEL COLLECTOR CURRENT LIMITATION
.COMPLETE TURN OFF AFTER LONG DURATION
OVERLOADS .UNDER AND OVER VOLTAGELOCK-OUT .SOFT START BY PROGRESSIVE CURRENT
LIMITATION .DOUBLE PULSE SUPPRESSION .BURST MODE OPERATION UNDER STANDBY
CONDITIONS
DESCRIPTION
In amaster slave architecture, the TEA2164control
IC achieves the slave function. Primarily designed
for TV receivers and monitors applications, this
circuit provides an easy synchronizationand smart
solution for low power stand by operation.
Located at the primary side the TEA2164 Control
IC ensures :
- the power supply start-up
- the power supply control under stand-by conditions
- the process of the regulation signals sent by the
master circuit located at the secondary side
- directbasedrive of the bipolarswitching transistor
- the protection of the transistor and the power
supply under abnormal conditions.

II. GENERAL DESCRIPTION
In a master slave architecture, the TEA2164 Control
IC, located at the primary side of an off line
power supply achievesthe slave function ;whereas
the master circuit is located at the secondary side.
The link between both circuits is realized by a small
pulse transformer

In the operation of the master-slave architecture,
four majors cases must be considered :
- normal operating
- stand-bymode
- power supply start-up
- abnormal conditions : off load, short circuit, ...
II.1. Normal Operating (master slave mode)
In this configuration, the master circuit generatesa
pulse widthmodulatedsignal issued from themonitoring
of the output voltage which needs the best
accuracy (in TV applications : the horizontal deflection
stagesupplyvoltage).Themaster circuit power
supply can be supplied by another output.
The PWM signal are sent towards the primary side
through small differentiating transformer. For the
TEA2164 positive pulses are transistor switchingon
commands ; and negative pulses are transistor
switching-offcommands (Figure 4). In this configuration,
only by synchronizing the master oscillator,
the switching transistor may be synchronized with
an external signal.
II.2. Stand-by Mode
In this configuration the master circuit no longer
sends PWM signals, the structure is not synchronized
; and the TEA2164 operates in burst mode.
The average power consumption at the secondary
side may be very low 1W 3 P 3 6W (as it is
consumed in TV set during stand by).
By action on the maximum duty cycle control, a
primary loop maintains a semi-regulation of the
output voltages.Voltage on feed-back is applied on
Pin 9.
Burst period is externally programmedby capacitor
C1.
II.3. Power Supply Start-up
After the mains have been switched-on, the VCC
storage capacitor of the TEA2164 is charged
through a high value resistor connected to the
rectified high voltage.When Vcc reaches VCC start
threshold (9V typ), the TEA2164 starts operatingin
burst mode. Since available output power is low in
burst mode the output power consumption must
remain low before complete setting-up of output
voltage. In TV application it can be achieved by
maintaining the TV in stand-by mode during startup.

Overvoltage Protection
When VCC exceeds VCC max, an internal flip-flop
stops output conduction signals. The circuit will
start again after the capacitor C1 discharge ; it
means : after loss of synchronization or after Vcc
stop crossing (Figure 7).
In flyback converters, this function protects the
power supply against output voltage runaway.

SCHNEIDER DTV5535 DIGITAL PROFI CONCEPT 55 CHASSIS DTV1Synchronized switch-mode power supply:
In a switch mode power supply, a first switching transistor is coupled to a primary winding of an isolation transformer. A second switching transistor periodically applies a low impedance across a second winding of the transformer that is coupled to an oscillator for synchronizing the oscillator to the horizontal frequency. A third winding of the transformer is coupled via a switching diode to a capacitor of a control circuit for developing a DC control voltage in the capacitor that varies in accordance with a supply voltage B+. The control voltage is applied via the transformer to a pulse width modulator that is responsive to the oscillator output signal for producing a pulse-width modulated control signal. The control signal is applied to a mains coupled chopper transistor for generating and regulating the supply voltage B+ in accordance with the pulse width modulation of the control signal.

Description:

The invention relates to switch-mode power supplies.

Some television receivers have signal terminals for receiving, for example, external video input signals such as R, G and B input signals, that are to be developed relative to the common conductor of the receiver. Such signal terminals and the receiver common conductor may be coupled to corresponding signal terminals and common conductors of external devices, such as, for example, a VCR or a teletext decoder.

To simplify the coupling of signals between the external devices and the television receiver, the common conductors of the receiver and of the external devices are connected together so that all are at the same potential. The signal lines of each external device are coupled to the corresponding signal terminals of the receiver. In such an arrangement, the common conductor of each device, such as of the television receiver, may be held "floating", or conductively isolated, relative to the corresponding AC mains supply source that energizes the device. When the common conductor is held floating, a user touching a terminal that is at the potential of the common conductor will not suffer an electrical shock.

Therefore, it may be desirable to isolate the common conductor, or ground, of, for example, the television receiver from the potentials of the terminals of the AC mains supply source that provide power to the television receiver. Such isolation is typically achieved by a transformer. The isolated common conductor is sometimes referred to as a "cold" ground conductor.

In a typical switch mode power supply (SMPS) of a television receiver the AC mains supply voltage is coupled, for example, directly, and without using transformer coupling, to a bridge rectifier. An unregulated direct current (DC) input supply voltage is produced that is, for example, referenced to a common conductor, referred to as "hot" ground, and that is conductively isolated from the cold ground conductor. A pulse width modulator controls the duty cycle of a chopper transistor switch that applies the unregulated supply voltage across a primary winding of an isolating flyback transformer. A flyback voltage at a frequency that is determined by the modulator is developed at a secondary winding of the transformer and is rectified to produce a DC output supply voltage such as a voltage B+ that energizes a horizontal deflection circuit of the television receiver. The primary winding of the flyback transformer is, for example, conductively coupled to the hot ground conductor. The secondary winding of the flyback transformer and voltage B+ may be conductively isolated from the hot ground conductor by the hot-cold barrier formed by the transformer.

It may be desirable to synchronize the operation of the chopper transistor to horizontal scanning frequency for preventing the occurrence of an objectionable visual pattern in an image displayed in a display of the television receiver.

It may be further desirable to couple a horizontal synchronizing signal that is referenced to the cold ground to the pulse-width modulator that is referenced to the hot ground such that isolation is maintained.

A synchronized switch mode power supply, embodying an aspect of the invention, includes a transfromer having first and second windings. A first switching arrangement is coupled to the first winding for generating a first switching current in the first winding to periodically energize the second winding. A source of a synchronizing input signal at a frequency that is related to a deflection frequency is provided. A second switching arrangement responsive to the input signal and coupled to the second winding periodically applies a low impedance across the energized second winding that by transformer action produces a substantial increase in the first switching current. A periodic first control signal is generated. The increase in the first switching current is sensed to synchronize the first control signal to the input signal. An output supply voltage is generated from an input supply voltage in accordance with the first control signal.

In a switch mode power supply, a first switching transistor is coupled to a primary winding of a transformer for generating pulses of a switching current. A secondary winding of the transformer is coupled via a switching diode to a capacitor of a control circuit for developing a control signal in the capacitor. The control signal is applied to a mains coupled chopper second transistor for generating and regulating supply voltages in accordance with pulse width modulation of the control signal. During standby operation, the first and second transistors operate in a burst mode that is repetitive at a frequency of the AC mains supply voltage such as 50 Hz. In the burst mode operation, during intervals in which pulses of the switching current occur, the pulse width and peak amplitude of the switching current pulses progressively increase in accordance with the waveform of the mains supply voltage to provide a soft start operation in the standby mode of operation within each burst group.

Description:

The invention relates to switch-mode power supplies.

In a typical switch mode power supply (SMPS) of a television receiver the AC mains supply voltage is coupled to a bridge rectifier. An unregulated direct current (DC) input supply voltage is produced. A pulse width modulator controls the duty cycle of a chopper transistor switch that applies the unregulated supply voltage across a primary winding of a flyback transformer. A flyback voltage at a frequency that is determined by the modulator is developed at a secondary winding of the transformer and is rectified to produce DC output supply voltages such as a voltage B+ that energizes a horizontal deflection circuit of the television receiver and a voltage that energizes a remote control unit.

During normal operation, the DC output supply voltages are regulated by the pulse width modulator in a negative feedback manner. During standby operation, the SMPS is required to generate the DC output supply voltage that energizes the remote control unit. However, most other stages of the television receiver are inoperative and do not draw supply currents. Consequently, the average value of the duty cycle of the chopper transistor may have to be substantially lower during standby than during normal operation.

Because of, for example, storage time limitation in the chopper transistor, it may not be possible to reduce the length of the conduction interval in a given cycle below a minimum level. Thus, in order to maintain the average value of the duty cycle low, it may be desirable to operate the chopper transistor in an intermittent or burst mode, during standby. During standby, a long dead time interval occurs between consecutively occurring burst mode operation intervals. Only during the burst mode operation interval switching operation occurs in the chopper transistor. The result is that each of the conduction intervals is of a sufficient length.

In accordance with an aspect of the invention, burst mode operation intervals are initiated and occur at a rate that is determined by a repetitive signal at the frequency of the AC mains supply voltage. For example, when the mains supply voltage is at 50 Hz, each burst mode operation interval, when switching cycles occur, may last 5 milliseconds and the dead time interval when no switching cycles occur, may last during the remainder portion or 15 milliseconds. Such arrangement that is triggered by a signal at the frequency of the mains supply voltage simplifies the design of the SMPS.

The burst mode operation intervals that occur in standby operation are synchronized to the 50 Hz signal. During each such interval, pulses of current are produced in transformers and inductances of the SMPS. The pulses of current occur in clusters that are repetitive at 50 Hz. The pulses of current occur at a frequency that is equal to the switching frequency of the chopper transistor within each burst mode operation interval. Such qurrent pulses might produce an objectionable sound during power-off or standby operation. The objectionable sound might be produced due to possible parasitic mechanical vibrations as a result of the pulse currents in, for example, the inductances and transformers of the SMPS.

In accordance with another aspect of the invention, the change in the AC mains supply voltage during each period causes the length of the conduction interval in consecutively occurring switching cycle during the burst mode operation interval to increase progressively. Such operation that occurs during each burst mode operation interval may be referred to as soft start operation. The soft start operation causes, for example, gradual charging of capacitors in the SMPS. Consequently, the parasitic mechanical vibrations are substantially reduced. Also, the frequency of the switching cycles within each burst mode operation interval is maintained above the audible range for further reducing the level of such audible noise during standby operation.

A switch mode power supply, embodying an aspect of the invention, for generating an output supply voltage during both a standby-mode of operation and during a run-mode of operation includes a source of AC mains input supply voltage. A control signal at a given frequency is generated. A switching arrangement energized by the input supply voltage and responsive to the first control signal produces a switching current during both the standby-mode of operation and the run-mode operation. The output supply voltage is generated from the switching current. An arrangement coupled to the switching arrangement and responsive to a standby-mode/run-mode control signal and to a signal at a frequency that is determined by a frequency of the AC mains input supply voltage controls the switching arrangement in a burst mode manner during the standby-mode of operation. During a burst interval, a plurality of switching cycles are performed and during an alternating dead time interval no switching cycles are performed. The two intervals alternate at a frequency that is determined by the frequency of the AC mains input supply voltage.

SCHNEIDER DTV5535 DIGITAL PROFI CONCEPT 55 CHASSIS DTV1 Switched vertical deflection circuit with bidirectional power supply SCHNEIDER CHASSIS DTV1 :A switched vertical deflection circuit derives vertical deflection current from horizontal deflection energy. A single switching element operates during both horizontal trace and retrace intervals. Conduction of the switching element is controlled by a vertical control circuit to provide the desired vertical deflection current. Feedback to the control circuit is referenced to ground potential to eliminate nonlinearity caused by voltage supply variations. The vertical circuit voltage supply is adapted to sink as well as supply current, thereby stabilizing the supply.

1. A field deflection circuit for a video display apparatus, comprising:
a source of voltage;
a field deflection winding coupled to said source of voltage;

energy storage means coupled to said field deflection winding for providing field deflection current in said field deflection winding;
a source of line deflection rate energy incorporating a switching transistor;
means for applying a predetermined amount of said line deflection rate energy from said line deflection rate energy source to said energy storage means during a first portion of each line deflection interval and for removing a predetermined amount of energy from said energy storage means during a second portion of each line deflection interval; and
unidirectional current control means for completing a current path from said field deflection winding to a source of reference potential during a portion of a field deflection interval in response to switching of said transistor, said current path including said switching transistor.

2. The arrangement defined in claim 1 wherein said means for applying and removing line rate energy comprises a field effect transistor and an antiparallel diode.

3. The arrangement defined in claim 1, wherein said unidirectional current control means comprises a diode.

4. The arrangement defined in claim 1, wherein said source of voltage comprises a transformer winding and a capacitor and wherein said source of line deflection rate energy comprises a diode for providing damper action for said source of line deflection rate energy.

5. A field deflection circuit for a video display apparatus, comprising:
a source of direct voltage;
a field deflection winding coupled to said source of direct voltage;
energy storage means coupled to said field deflection winding for providing field deflection current in said field deflection winding;
a source of line deflection rate energy;
means for applying a predetermined amount of said line deflection rate energy from said line deflection rate energy source to said energy storage means during a first portion of each line deflection interval and for removing a predetermined amount of energy from said energy storage means during a second portion of each line deflection interval; and
first and second unidirectional current control means coupled to said source of direct voltage for clamping the level of said direct voltage within a predetermined range independent of said field deflection current.

6. A field deflection circuit for a video display apparatus, comprising:
a source of voltage;
a field deflection winding coupled to said source of voltage;
energy storage means coupled to said field deflection winding for providing field deflection current in said field deflection winding;
a source of line deflection rate energy;
means for applying a predetermined amount of said line deflection rate energy from said line deflection rate energy source to said energy storage means during a first portion of each line deflection interval and for removing a predetermined amount of energy from said energy storage means during a second portion of each line deflection interval; and
first unidirectional current control means for completing a current path from said source of voltage to said field deflection winding for supplying current to said field deflection winding and second unidirectional current control means for completing a current path from said field deflection winding to said source of voltage for sinking current from said field deflection winding.

7. A field deflection circuit for a video display apparatus, comprising:
a source of direct voltage;
a capacitor;
a field deflection winding coupled to said source of direct voltage and to said capacitor;
energy storage means coupled to said field deflection winding for providing field deflection current in said field deflection winding, said deflection current generating an ac ripple component on said capacitor;
a source of line deflection rate energy;
means for applying a predetermined amount of said line deflection rate energy from said line deflection rate energy source to said energy storage means during a first portion of each line deflection interval and for removing a predetermined amount of energy from said energy storage means during a second portion of each line deflection interval; and
unidirectional current control means coupled to said source of direct voltage for reducing the magnitude of said ac ripple component.

Description:

This invention relates to deflection circuits for television receivers and, in particular, to vertical deflection circuits which derive power from horizontal deflection energy.
Synchronous switched vertical deflection circuits operate by storing a portion of the horizontal trace or retrace energy each horizontal deflection cycle. This energy is applied to the vertical deflection winding in order to provide the desired vertical deflection current in the deflection windings. The amount of horizontal rate energy that is stored each horizontal interval is carefully controlled in order to provide the correct amount of vertical deflection current.
U.S. Pat. No. 4,048,544 discloses a switched vertical deflection circuit in which a pair of SCRs are selectively rendered conductive in order to permit portions of positive and negative polarity horizontal retrace pulses to charge a capacitor. The capacitor is connected to the vertical deflection windings and discharges through the winding to provide the desired vertical deflection current. The gating signals for the SCRs are provided by pulse width modulating circuits. FIG. 1 illustrates a prior art circuit which utilizes a single switch comprising a thyristor and diode combination, such as an ITR, and a single storage coil L s to effect horizontal-rate charge and discharge of a storage capacitor C y which supplies vertical deflection current. In the circuit shown in FIG. 1, the supply capacitor 15 charges through the vertical deflection winding V y . This causes a large amount of vertical parabola voltage to be superimposed on the 23 volt supply. This may disrupt the operation of other receiver circuits operating from the 23 volt supply. Also, if a circuit malfunction should cause the thyristor to fail to turn on, capacitor 15 will charge via the ITR diode to a level greater than the 23 volt power supply, which may damage the vertical control circuit or other receiver circuits. This requires the use of a protection circuit 16 to disable the receiver if the level of the 23 volt supply increases.
The present invention is directed to a switched vertical deflection circuit that advantageously incorporates only one switching element yet provides more economy and greater reliability as compared to the single element switched vertical deflection circuit of FIG. 1.
In accordance with an aspect of the present invention, a vertical deflection circuit for a video display apparatus comprises a vertical deflection winding and a capacitor connected to the vertical deflection winding for providing vertical deflection current to the winding. A source of horizontal deflection rate energy incorporates a switching transistor. A switch applies a predetermined amount of horizontal rate energy to the capacitor during a first portion of each horizontal deflection interval and removes a predetermined amount of energy from the capacitor during a second portion of each horizontal deflection interval. Unidirectional current control means completes a current path from the vertical deflection winding to a source of reference potential by way of the transistor in response to switching of the transistor.
In the accompanying drawing, FIG. 1 is a schematic and block diagram of a switched vertical deflection circuit of the prior art;
FIG. 2 is a schematic and block diagram of a switched vertical deflection circuit in accordance with an aspect of the present invention;
FIGS. 3 and 4 illustrate waveforms associated with the circuit of FIG. 2; and
FIG. 5 is a schematic diagram of a practical embodiment of the switched vertical deflection circuit of the present invention.
The prior art switched vertical deflection circuit shown in FIG. 1 incorporates a single switching element, such as an ITR, which has its conduction controlled by a vertical control circuit 10. During the horizontal retrace interval, current flows from ground, through the diode of the ITR, winding 11 of a high voltage transformer 12, storage coil L s and charges capacitor C y . The charge on capacitor C y then causes a deflection current to flow from C y through the vertical deflection winding V Y and the sampling resistor R s . The voltage developed across sampling resistor R s is sensed by vertical control circuit 10 which in turn controls the conduction of the SCR element of the ITR.
The SCR is conductive during a portion of the horizontal trace interval. During conduction of the SCR, current flows from the +23 volt supply through deflection winding V y , coil L s , winding 11 and the SCR to ground. Controlling the conduction of the SCR by shifting the occurrence of the SCR trigger pulses during the horizontal trace interval provides the desired sawtooth vertical deflection current in deflection winding V y .
In the prior art circuit of FIG. 1 the voltage across sampling resistor R s is determined by the deflection winding voltage and the level of the +23 volt supply. The +23 volt supply is generated via a winding 17 of a high voltage transformer 12. Load variations of other receiver circuits may cause variations or modulation of the +23 volt supply via the flyback transformer 12. This may in turn alter the voltage developed across sampling resistor R s , causing nonlinearity distortion in the vertical deflection current. A possible solution would require a common mode rejection input circuit for the feedback input 13 and power input 14 of the vertical control circuit 10, which would compensate for variations in the +23 volt supply level.
Vertical parabola voltage (ripple) developed across the storage capacitor 15 may be superimposed on the +23 volt supply, thereby disrupting the operation of other circuits connected to this supply. Also, in the prior art circuit of FIG. 1, failure of the SCR to trigger causes capacitor 15 to charge to a level much higher than the +23 volt supply via the diode of the SCR. This increased voltage may damage the vertical control circuit or other receiver circuits, thereby necessitating protection circuit 16, which illustratively disables the receiver if the voltage across capacitor 15 increases beyond a predetermined level. FIG. 2 illustrates a power supply and vertical or field deflection circuit in accordance with an aspect of the present invention. A vertical control circuit 20 provides width modulated horizontal or line rate switching signals to a switching element 21, illustratively shown as comprising a Darlington transistor 18 and an integrated antiparallel diode 19. Transistor 18 may comprise a power field effect transistor which is advantageous when multiple horizontal rate deflection circuits are provided, such as are used with computer monitor or video display terminals. Switching element 21 is coupled via a winding 23 of high voltage transformer 24 and storage coil 25 to a capacitor 26. Capacitor 26 is coupled to one terminal of a vertical deflection winding 27. The other terminal of vertical deflection winding 27 is coupled to a voltage supply designated +V 1 . The +V 1 supply is generated via a winding 30 of transformer 24, rectifying diode 31 and filter capacitor 32. The +V 1 supply may also be used to power other receiver circuits.
A horizontal output transistor 33 is switched at the horizontal deflection rate by signals applied to its base from horizontal oscillator and driver circuits 34. The collector of transistor 33 is coupled to a voltage supply designated +V 2 via a winding 35 of transformer 24. Transistor 33 is also coupled to a horizontal deflection winding 36, an S-shaping capacitor 38, and a resonant retrace capacitor 37. A diode 40 is coupled in series with diode 31 between winding 30 and the collector of transistor 33.
During the horizontal retrace interval, transistor 33 is cut off by horizontal oscillator and driver circuit 34, causing a resonant retrace pulse to be formed across winding 35, as shown in FIG. 3A. This in turn causes a similar pulse to be formed across windings 30 and 23. With transistor 18 of switching element 21 turned off by vertical control circuit 20, a horizontal rate current will circulate from winding 23 through energy storage coil 25, capacitor 26 and diode 19 back to winding 23. As a result, capacitor 26 charges to a level greater than the +V 1 level, causing a negative deflection current component of i 27 to flow through winding 27 and resistor 22. When transistor 18 is rendered conductive by signals from vertical control circuit 20, shown in FIG. 3B, a horizontal rate current component circulates from winding 23 through transistor 18, capacitor 26 and energy storage coil 25. As a result, a positive current component of i 27 flows from the +V 1 source through winding 27 and resistor 22 to ground. The deflection current i 27 is shown in FIG. 4C. The current through winding 23 and switching element 21 is shown in FIG. 3C at the horizontal deflection rate and in FIG. 4A at the vertical deflection rate. The positive current represents current flow through transistor 18, while the negative current represents current flow through diode 19. Conductor 28, carrying drive signals for transistor 18, and feedback conductor 29 are of high impedance, as is deflection winding 27, so that horizontal rate current circulates only through winding 23, coil 25, capacitor 26 and switching element 21. Deflection winding 27 represents too high an impedance for horizontal rate currents. The horizontal rate current loop is controlled by vertical control circuit 20 and forms a variable voltage battery having terminals across capacitor 26. The horizontal rate voltage across capacitor 26 is such that the desired vertical deflection current i 27 passes through capacitor 32, deflection winding 27, the circulating horizontal rate current loop and sampling resistor 22. The horizontal rate components are integrated by the large inductance of winding 27. It can be further seen that the current through resistor 22 is equal to the deflection current i 27 . The voltage developed across resistor 22 is proportional to i 27 , the vertical deflection current. FIGS. 3A, 3B and 3C illustrate the dynamic operation of the circuit. The switching of Darlington transistor 18 is controlled by width modulated base drive current pulses shown in FIG. 3B. The turn-on time is modulated between times t 1 and t 3 . The turn-off time is common at time t 4 , the end of the horizontal trace interval. Turn-off of transistor 18 is not only provided by the base drive signal but also by the inverting retrace voltage across winding 23. At the beginning of the vertical trace interval at the top of the screen, transistor 18 is rendered conductive between times t 3 and t 4 . The positive portion of current i 23 is much smaller than the negative one resulting in a positive voltage across capacitor 26, as shown in FIG. 3D and in a negative deflection current i 27 , as shown in FIG. 4C. Vertical control circuit 20 advances the turn-on time of transistor 18. At time t 2 , the center of the vertical trace interval, the positive and negative portions of i 23 are equal, the voltage across capacitor 26 equals +V 1 , and the deflection current i 27 is zero. A further advance of the turn-on time of transistor 18 toward t 1 , near the bottom of the screen, results in increasing positive portions and decreasing negative portions of current i 23 . The voltage across capacitor 26 decreases and deflection current i 27 increases in a positive direction. During the vertical retrace interval, transistor 18 is cut off. Deflection winding 27 and capacitor 26 resonate for one half cycle via resistor 22 and capacitor 32. This produces a large vertical retrace voltage pulse, as shown in FIG. 4B, and reverses the deflection current i 27 . At the beginning of the vertical trace interval, the voltage across capacitor 26 and the deflection current i 27 are of the proper magnitude and polarity and must only be maintained by current i 23 . The amplitude of the positive current component of i 23 through transistor 18 also modulates the negative current component of i 23 through diode 19. This occurs because the di/dt of current i 23 during the interval t 4 - t 5 is determined by the storage coil 25. Therefore, a high transistor current causes a low diode current (bottom) and conversely a low transistor current permits a high diode current (top). At the beginning of the vertical trace interval, transistor 18 is conductive for only a short period of time, so that the voltage across capacitor 26, shown at the horizontal deflection rate in FIG. 3D and at the vertical deflection rate in FIG. 4B, will be of such a polarity that deflection current, shown in FIG. 4C, flows from capacitor 26 through deflection winding 27 in the +V 1 supply. The vertical rate current path is completed through capacitor 32. The additional charge on capacitor 32 from deflection current i 27 is fed back to the high voltage transformer 24 via winding 30 and diode 40. Diode 40 is rendered conductive by horizontal output transistor 33. Diodes 31 and 40 act also as damper diodes for the horizontal deflection output circuit. The presence of diode 40 therefore allows the +V 1 supply to sink current, thereby eliminating the need for a protection circuit as shown in the prior art arrangement illustrated in FIG. 1. The level of the +V 1 supply is clamped bidirectionally by diodes 40 and 31 to the horizontal trace voltage across winding 30, thereby stabilizing the +V 1 supply. This arrangement also reduces the amount of voltage ripple that appears across capacitor 32, as shown in FIG. 4D. The current flow in winding 30 is shown at the horizontal and vertical deflection rates in FIGS. 3E and 4E, respectively. The positive current represents current flow in diode 31 while the negative current represents current flow in diode 40. The unequal current amplitudes occur because of other load circuits coupled to the +V 1 supply. The presence of these load circuits increases current through diode 31 and decreases current through diode 40.
As previously described and as shown in FIG. 3B, at the beginning of the vertical trace interval transistor 18 is conductive for only a short time. This results in capacitor 26 being charged above the level of the +V 1 supply, as shown in FIG. 4B, causing deflection current to flow from capacitor 26 through vertical deflection winding 27 to the +V 1 supply. During the vertical trace interval, vertical control circuit 20 progressively advances the conduction of transistor 18 each horizontal trace interval, as shown in FIG. 3B, so that transistor 18 conducts for a progressively greater length of time. This causes the net charge on capacitor 26 to progressively decrease through the vertical trace interval, thereby resulting in the desired vertical deflection current through winding 27, as shown in FIG. 4C. The voltage developed across deflection current sampling resistor 22, as shown in FIG. 4F, is produced by deflection current i 27 and provides feedback to vertical control circuit 20. This feedback provides information to vertical control circuit 20 to enable the driving of transistor 18 into conduction at the appropriate time each horizontal interval to generate the desired vertical deflection current. The feedback resistor 22 is referenced to ground potential so that supply loading variations by other receiver circuits will not adversely affect the feedback voltage. A common mode rejection circuit in vertical control circuit 20 is therefore not required. This reduces the cost and simplifies the construction of vertical control circuit 20.

FIG. 5 illustrates a particular embodiment of a power supply and switched vertical deflection circuit in accordance with the present invention, illustratively for use with a kinescope having a 110° deflection angle. Components corresponding to those in FIG. 2 are designated with the same reference numerals. Representative component values are also given. A CA339 quad comparator is used as the basis for the vertical control circuit, which operates in the following manner. Resistor 50, along with capacitors 51 and 52, and emitter follower transistor 53 form a conventional vertical sawtooth generator. Comparators 54 and 55, incorporated within integrated circuit 56, combine with the sawtooth generator to form a vertical rate oscillator. During the vertical trace interval, capacitors 51 and 52 are charged positively via resistor 50 until the emitter voltage of transistor 53 applied to pin 8 of integrated circuit 56 reaches the voltage present at pin 9. When this occurs, comparator 54 switches low and causes the voltage levels at pin 9 and pin 11 to go low. Comparator 55 then switches low and discharges capacitors 51 and 52 to the low voltage level at pin 9. The output collectors of comparators 54 and 55 then open and a new charge (trace) cycle begins. Hold control resistor 60 determines the high voltage level at pin 9 and therefore determines the length of the charge cycle. Vertical sync pulses are integrated by capacitor 61 and differentiated by capacitor 62. The positive transient of the processed vertical sync pulse sits on the vertical ramp and switches comparators 54 and 55 prior to switching by the emitter voltage of transistor 53.
Comparator 63 serves as a vertical blanking pulse generator. During the vertical trace interval the voltage across capacitor 64 at pin 4 is higher than the voltage at pin 5 because of the voltage drop across resistor 65. Switching of comparator 54 discharges capacitor 64, causing comparator 63 to open. Comparator 63 remains open until capacitor 64 becomes charged to a voltage level higher than the voltage at pin 5. Blanking time is adjustable by varying the value of capacitor 64. Comparator 66 serves as a pulse width modulator. The vertical sawtooth ramp is fed via the height control resistor 67, coupling capacitor 70 and resistor 71 to pin 7 of comparator 66. Resistors 72 and 73 determine the dc bias on pin 7. Resistor 71 determines the amplitude of the vertical ramp voltage applied to pin 7. Capacitor 70 provides the deflection current S-shaping at the beginning of vertical trace. Horizontal retrace pulses via resistor 74 charge capacitor 75 to obtain a horizontal ramp which is compared with the vertical sawtooth. The output of comparator 66 at pin 1 short circuits to ground the voltage at the junctions of resistors 76 and 77 to provide base drive to transistor 21. Capacitor 80 is required to switch the base voltage below ground because the emitter of transistor 21 is floating on the sampling resistor 22 and swings between ±1 volt. Centering control resistor 81 adjusts the dc bias on pin 6. Illustratively, vertical deflection winding 27 has an inductance of 25 mH, and a resistance of 9.5 ohms.
The previously described switched vertical deflection circuit is desirably utilized at vertical deflection rates of 100 Hz or greater, such as could be provided by progressive scan systems or in digital deflection circuits.

ITT DIGIVISION CHIPSET FUNCTIONS SCHNEIDER CHASSIS DTV1.

DIGITAL CRT TUBE Cathode RAY CURRENT CONTROL / Cut OFF / Drive and processing.In this IC set, the dark currents and the white levels of the three electron guns, the leakage currents of the cathodes, and a light-detector current are measured during four successive vertical blanking intervals. The cathode leakage currents and the dark currents are measured in the first half of the vertical blanking interval, and the light-detector current and the white level currents are measured at the end of this interval. From these measured data and alignment data stored in a reprogrammable memory (ps), a microprocessor (mp) contained together with the memory (ps) in an integrated circuit (ic2) derives operating data for the picture tube (b) as well as further data. These operating data are transferred over a wire of a chroma bus (cb), over which chroma signals are transferred during the vertical sweep, into a shift register (sr) of a further integrated circuit (ic3) at the beginning of each vertical blanking interval, from where they are passed on to the picture tube (b) in groups via digital-to-analog converters and analog amplifiers. By the use of the chroma bus for a dual purpose, and the successive measurements of the above-mentioned picture-tube data, a saving of external terminals of the integrated circuits (ic1, ic2, ic3) is achieved.

1. Set of three integrated circuits(ic1, ic2, ic3) for digital video-signal processing in color-television receivers,
wherein the first integrated circuit (ic1) contains an analog-to-digital converter (ad) followed by a first bus interface circuit (if1) for a serial data bus (sb), and a first multiplexer (mx1) following the first bus interface circuit (if1), the analog-to-digital converter (ad) being fed with measured data corresponding to the cathode currents of the picture tube (b) flowing at "black" (="dark current") and "white" (="white level") in each of the three electron guns, and with the signal of an ambient-light detector (ls) via a second multiplexer (mx) in the vertical blanking interval, and the first multiplexer (mx1) being fed with the processed digital chrominance signals (cs), wherein the second integrated circuit (ic2) contains a microprocessor (mp), an electrically reprogrammable memory (ps), and a second serial-data-bus interface circuit (if2) corresponding to the first bus interface circuit (if1), the memory (ps) holding alignment data and nominal dark-current/white-level data of the picture tube used (b) which were entered by the manufacturer of the color-television receiver and, together with the measured data, are used by the microprocessor (mp) to generate video-signal-independent operating data for the picture tube (b), and
wherein the third integrated circuit (ic3) contains a demultiplexer (dx), an analog RGB matrix (m), and three analog amplifiers (vr, vg, vb) each designed to drive one of the electron guns via an external video output stage (ve), the dark current of the picture tube (b) being adjusted via the operating point of the respective analog amplifier, and the white level of the picture tube (b) being adjusted by adjusting the gain of the respective amplifier after digital-to-analog conversion, and with the demultiplexer (dx) connected to the first multiplexer (mx1)of the first integrated circuit (ic1) via a chroma bus (cb),
Characterized by the Following Features:
The first multiplexer (mx1) consists of three electronic switches (s1, s2, s3),
the first of which (s1) has its input grounded through a first resistor (r1) and connected to the collectors of external transistors (tr, tg, tb) which are each associated with one of the electron guns and the base of each of which is driven by the associated video output stage, while the emitter is connected to the associated electron gun system, and the output of the first switch (s1) is connected to the input of the analog-to-digital converter (ad);
the second of which (s2) has its input connected to the light detector (ls), while its output is coupled with the input of the analog-to-digital converter (ad), and
the third of which (s3) has its input connected to the input of the first electronic switch (s1) via a second resistor (r2), and its output is grounded, the value of the second resistor (r2) being about one order of magnitude smaller than that of the first resistor (r1);
the three electronic switches (s1, s2, s3) have the following positions:

______________________________________

s1 s2 s3

______________________________________

during vertical

closed open closed

sweep

during vertical

closed/open

open/closed

open/closed

retrace: for

leakage/light-

det. current meas.

for white level

closed open closed

measurement

for dark current

closed open open

measurement

______________________________________

the measurements of the dark current together with the white level of each electron gun and the measurements of the light-detector current together with the cathode leakage currents are performed in four successive vertical blanking intervals;
to this end, the cathodes are connected at one end to a voltage for blacker than black (us), and at the other end to a voltage for black (ud) and then to a voltage for white (uw) in accordance with the following table:

______________________________________

Measurement in the first at about the Vertical half of the end of the blanking vertical vertical interval blanking blanking Cathode No. interval interval red green blue

______________________________________

1 Leakage cur-

Light-detect-

us us us

rents of the

or current

cathodes

2 Dark current

White level

ud/uw us us

red red

3 Dark current

White level

us ud/uw us

green green

4 Dark current

White level

us us ud/uw

blue blue

______________________________________

the measured data are transferred from the analog-to-digital converter (ad) to the microprocessor (mp) of the second integrated circuit (ic2) via the two interface circuits (if1, if2) and the data bus (sb) at an appropriate instant, and
the video-signal-independent operating data for the picture tube (b), which are generated by the microprocessor (mp), are transferred from the second integrated circuit (ic2) via the two interface circuits (if1, if2) and a line (db) to the first multiplexer (mx1) of the first integrated circuit (ic1) at an appropriate instant, and from there over a wire of the chroma bus (cb) into a shift register (sr) of the third integrated circuit (ic3) shortly after the beginning of the next vertical blanking interval, the parallel outputs of which shift register (sr) are combined in groups each assigned to one type of operating value, and each of the groups is connected to one digital-to-analog converter (dh, ddr, ddg, ddd, dwr, dwg, dwb) which drives the RGB matrix (m) or the respective analog amplifier (vr, vg, vb).
. 2. An integrated-circuit set as claimed in claim 1, characterized in that the voltage for blacker than black (us) is applied to the cathodes of the picture tube (b) during the data transfer to the shift register (sr). 3. An integrated-circuit set as claimed in claim 2, characterized in that the microprocessor (mp) determines the appropriate instant for the measured-data transfer, and that, if a measurement has not yet been finished at that instant, the measured data of the corresponding earlier measurement are transferred. 4. An integrated-circuit set as claimed in claim 3, characterized in that the measurement performed in a vertical blanking interval is not enabled until the data of the preceding measurement have been transferred to the microprocessor (mp). 5. An integrated-circuit set as claimed in claim 2, characterized in that the measurement performed in a vertical blanking interval is not enabled until the data of the preceding measurement have been transferred to the microprocessor (mp). 6. An integrated-circuit set as claimed in claim 1, characterized in that the microprocessor (mp) determines the appropriate instant for the measured-data transfer, and that, if a measurement has not yet been finished at that instant, the measured data of the corresponding earlier measurement are transferred. 7. An integrated-circuit set as claimed in claim 6, characterized in that the measurement performed in a vertical blanking interval is not enabled until the data of the preceding measurement have been transferred to the microprocessor (mp). 8. An integrated-circuit set as claimed in claim 1, characterized in that the measurement performed in a vertical blanking interval is not enabled until the data of the preceding measurement have been transferred to the microprocessor (mp).

Description:

The present invention relates to a set of three integrated circuits for digital video signal processing in color-television receivers as is set forth in the preamble of claim 1. An IC set of this kind is described in a publication by INTERMETALL entitled "Eine neue Dimension-VLSI-Digital-TV-System", Freiburg im Breisgau, September 1981, on pages 6 to 11 (see also the corresponding English edition entitled "A new dimension-VLSI Digital TV System", also dated September 1981). The first integrated circuit, designated in the above-mentioned publications by "MAA 2200" and called "Video Processor Unit" (VPU), includes an analog-to-digital converter followed by a first serial-data-bus interface circuit which, in turn, is followed by a first multiplexer. During the vertical blanking interval, the analog-to-digital converter is fed, via a second multiplexer, with measured data corresponding to the cathode currents of the picture tube flowing at "black" (="dark current") and "white" ("white level") in each of the three electron guns, and with the signal of an ambient-light detector. The processed digital chrominance signals are applied to the first multiplexer.
The second integrated circuit, designated by "MAA 2000" and called "central control unit" (CCU) in the above publications, contains a microprocessor, an electrically reprogrammable memory, and a second serial-data-bus interface circuit. The memory holds alignment data and nominal dark-current/white-level data entered by the manufacturer of the color-television receiver. From these data and the measured data, the microprocessor derives video-signal-independent operating data for the picture tube.
The third integrated circuit, designated by "MAA 2100" and called "video-codec unit" (VCU) in the above publications, includes a demultiplexer, an analog RGB matrix, and three analog amplifiers each designed to drive one of the electron guns via an external video output stage. After digital-to-analog conversion, the dark current of the picture tube is adjusted via the operating point of the respective analog amplifier, and the white level of the picture tube is adjusted by adjusting the gain of the respective analog amplifier. The demultiplexer is connected to the first multiplexer of the first integrated circuit via a chroma bus.
As to the prior art concerning such digital color-television receiver systems, reference is also made to the journal "Elektronik", Aug. 14, 1981 (No. 16), pages 27 to 35, and the journal "Electronics", Aug. 11, 1981, pages 97 to 103.
During the further development of the prior art system following the above-mentioned publication dates, the developers were faced with the problem of how to accomplish the dark-current/white-level control of the picture tube within the existing system, particularly with respect to measured-data acquisition and transfer and to the transfer of the operating data to the picture tube.
Another requirement imposed during the further development of the prior art system was that the leakage currents of the electron guns of the picture tube be measured and processed within the existing system. The solution of these problems is to take into account the requirement that the number of external terminals of the individual integrated circuits be kept to a minimum.
The object of the invention as claimed is to solve the problems pointed out. The essential principles of the solution, which directly give the advantages of the invention, are, on the one hand, the division of the measurement to four successive vertical blanking intervals and, on the other hand, the utilization of one wire of the chroma bus at the beginning of the next vertical blanking interval as well as the measurement of the ambient light by means of the light detector and the measurement of the leakage currents during a single vertical blanking interval.
The invention will now be explained in more detail with reference to the accompanying drawing, which is a block diagram of one embodiment of the IC set in accordance with the invention. It shows the first, second, and third integrated circuits ic1, ic2, and ic3, which are drawn as rectangles bordered by heavy lines. The first integrated circuit ic1 includes the analog-to-digital converter ad, which converts the measured dark-current, white-level, ambient-light, and leakage-current data into digital signals, which are fed to the first bus interface circuit if1. The latter is connected via the line db to the first multiplexer mx1, which interleaves data from the first bus interface circuit if1 with digital chrominance signals cs produced in the first integrated circuit ic1, and places the interleaved signals on the chroma bus cb. The generation of the digital chrominance signals cs is outside the scope of the present invention and is disclosed in the references cited above.
The first integrated circuit ic1 further includes the second multiplexer mx2, which consists of the three electronic switches s1, s2, s3, and represents a subcircuit which is essential for the invention. The input of the first switch s1 is grounded through the first resistor r1, and connected to the collectors of the external transistors tr, tg, tb, each of which is associated with one of the electron guns. Via the base-emitter paths of these transistors, the cathodes of the three electron guns are driven by the video output stages ve. The final letters r, g, and b in the reference characters tr, tg, and tb and in the reference characters explained later indicate the assignment to the electron gun for RED (r), GREEN (g), and BLUE (b), respectively. The output of the first switch s1 is connected to the input of the analog-to-digital converter ad.
The input of the second switch s2 is connected to the light detector ls, which has its other terminal connected to a fixed voltage u and combines with the grounded resistor r3 to form a voltage divider. The input of the second switch s2 is thus connected to the tap of this voltage divider, while the output of this switch, too, is coupled to the input of the analog-to-digital converter ad.
The input of the third switch s3 is connected to the input of the first switch s1 via the second resistor r2, while the output of the third switch s3 is grounded. The value of the resistor r1 is about one order of magnitude greater than that of the resistor r2. For the whole duration of the picture shown on the screen of the picture tube b, and throughout the vertical sweep, the first switch s1 and the third switch s3 are closed, and the second switch s2 is open. During the vertical retrace interval, for the white-level measurement, the switches s1, s3 are closed, and the switch s2 is open; for the dark-current measurement and the leakage-current measurement, the switch s1 is closed, and the switches s2, s3 are open, and for the light-detector-current measurement, the switches s2, s3 are closed, and the switch s1 is open.
The measurements of the dark current and the white level of each electron gun and the measurements of the light-detector current and the leakage currents are made in four successive vertical blanking intervals. One end of the respective cathode is connected to a voltage us for blacker-than-black, and the other end is connected to a voltage ud for black and then to a voltage uw for white, in accordance with the following table:

______________________________________

Measurement in the first at about the Vertical half of the end of the blanking vertical vertical interval blanking blanking Cathode No. interval interval red green blue

______________________________________

1 Leakage cur-

Light-detect-

us us us

rents of the

or current

cathodes

2 Dark current

White level

ud/uw us us

red red

3 Dark current

White level

us ud/uw us

green green

4 Dark current

White level

us us ud/uw

blue blue

______________________________________

The voltage ud for black is, as usual, a voltage which just causes no brightness on the screen of the picture tube b, i.e., a voltage just below the dark threshold of the picture tube. The voltage us for blacker-than-block is then a cathode voltage lying further in the black direction than the voltage for black. The voltage for white is the voltage for the screen brightness to be measured; the brightness of the screen is generally below the maximum permissible value.
Thus, two measurements are made during each vertical blanking interval, namely one in the first half, preferably at one-third of the pulse duration of the vertical blanking interval, and the other at about the end of the first half. During the four successive vertical blanking intervals, the first measurement determines the leakage currents of the cathodes and the dark currents for red, green, and blue. The second measurements determine the light-detector current and the white levels for red, green, and blue. During the measurement of the cathode leakage currents and the light-detector current, all three cathodes are at the voltage us. During the measurements of the dark current and the white level of the respective cathode, the latter is connected to the respective dark-current cathode voltage ud and white-level cathode voltage uw, respectively, while the cathodes of the two other electron guns, which are not being measured, are at the voltage us.
The second integrated circuit circuit ic2 contains the microprocessor mp, the electrically reprogrammable memory ps, and the second bus interface circuit if2, which is associated with the serial data bus sb in this integrated circuit and also connects the microprocessor mp and the memory ps with one another and with itself. The memory ps holds alignment data and nominal dark-current/white-value data of the picture tube used, which were entered by the manufacturer. From this alignment and nominal data and from the measured data obtained via the second multiplexer mx2 and the analog-to-digital converter ad of the first integrated circuit ic1, the microprocessor mp derives video-signal-independent operating data for the picture tube.
The derivation of these operating data is also outside the scope of the invention; it should only be mentioned that with respect to the operating data of the picture tube, the microprocessor performs a control function in accordance with a predetermined control characteristic.
The third integrated circuit ic3 includes the demultiplexer dx, which is connected to the first multiplexer mx1 of the first integrated circuit ic1 via the chroma bus cb and separates the chrominance signals cs and the operating data of the picture tube from the interleaved signals transferred over the chroma bus. While the transfer of measured data from the analog-to-digital converter ad to the microprocessor mp of the second integrated circuit ic2 takes place via the two interface circuits if1, if2 and the data bus sb at an appropriate instant, the video-signal-independent operating data for the picture tube b, which are derived by the microprocessor mp, are transferred from the second integrated circuit ic2 via the two interface circuits if1, if2 and the line db to the first multiplexer mx1 at an appropriate instant, and from the first multiplexer mx1 over a wire of the chroma bus cb into the shift register sr of the third integrated circuit ic3 shortly after the beginning of the next vertical blanking interval. To accomplish this, the first interface circuit if1 also includes a shift register from which the operating data are read serially.
During this data transfer into the shift register sr, the cathodes of the picture tube b are preferably at the voltage us in order that this data transfer does not become visible on the screen.
The appropriate instant for the transfer of measured data to the microprocessor mp is determined by the latter itself, i.e., depending on the program being executed in the microprocessor, and on the time needed therefor, the measured data are called for from the interface circuits not at the time of measurement but at a selectable instant within the working program of the microprocessor mp. If the measurement currently being performed should not yet be finished at the instant at which the measured data are called for, in a preferred embodiment of the invention, the stored data of the previous measurement will be transferred to the microprocessor mp.
As mentioned previously, the operating data for the picture tube b are transferred into the shift register sr at the beginning of a vertical blanking interval. The parallel outputs of this shift register are combined in groups each assigned to one operating value, and each group has one of the digital-to-analog converters dh, ddr, ddg, ddb, dwr, dwg, dwb associated with it. In the figure, the division of the shift register into groups is indicated by broken lines. The shift register sr performs a serial-to-parallel conversion in the usual manner, and the operating data are entered by the demultiplexer dx into the shift register in serial form and are then available at the parallel outputs of the shift register.
The digital-to-analog converter dh provides the analog brightness control signal, which is applied to the RGB matrix m in the integrated circuit ic3. Also applied to the RGB matrix m are the analog color-difference signals r-y, b-y and the luminance signal y. The formation of these signals is outside the scope of the invention and is known per se from the publications cited at the beginning.
The three analog-to-digital converters ddr, ddg, ddb provide the dark-current-adjusting signals for the three cathodes, which are currents and are applied to the inverting inputs--of the analog amplifiers vr, vg, vb. Also connected to these inputs is a resistor network which is adjustable in steps in response to the digital white-level-adjusting signals at the respective group outputs of the shift register sr. The resistors serve as digital-to-analog converters dwr, dwg, dwb and establish the connection between the inverting inputs--and the outputs of the analog amplifiers vr, vg, vb.
In an arrangement according to the invention which has proved good in practice, each of the three dark-current-adjusting signals is a seven-digit signal, and each of the three white-level-adjusting signals and the brightness control signal are five-digit signals. The voltages us and ud/uw of the three cathodes are assigned a three-digit identification signal in accordance with the above table, which signal is also fed into the shift register sr in the implemented circuit. Finally, a three-digit contrast control signal is provided in the implemented circuit for the Teletext mode of the color-television receiver. These nine data blocks are transferred in the implemented circuit from the demultiplexer dx to the shift register sr in the following order, with the least significant bit transmitted first, and with the specified number of blanks: identification signal, white-level signal blue, three blanks, white-level signal green, three blanks, white-level signal red, one blank, dark-current signal blue, one blank, dark-current signal green, one blank, dark-current signal red, contrast signal Teletext, and brightness control signal. These are seven eight-digit data blocks which are assigned to 56 pulses of a 4.4-MHz clock frequency, which is the frequency of the shift clock signal of the shift register sr.
It should be noted that the data sequence just described does not correspond to the order of the groups of the shift register sr in the figure. The order in the figure was chosen only for the sake of clarity.
The outputs of the three analog amplifiers vr, vg, vb are coupled to the inputs of the video output stage ve, whose outputs, as explained previously, are connected to the bases of the transistors pr, tg, td, so that the cathodes of the picture tube b are driven via the base-emitter paths of these transistors.
In another preferred embodiment of the invention, the measurement performed during a vertical blanking interval is not enabled until the data of the previous measurement has been transferred into the microprocessor mp. In this manner, no measurement will be left out.
It is also possible to omit the digital-to-analog converter dh if the analog RGB matrix m is replaced with a digital one.
One advantage of the invention is that the use of the chroma bus for the transfer of operating data facilitates the implementation of the third integrated circuit ic3 using bipolar technology, because an additional bus interface circuit, which could be used there, would occupy too much chip area.

The invention permits an n bit resolution to be achieved with an n-1 bit converter. In a color television receiver the analog-to-digital converter is a parallel analog-to-digital converter with p=2r -1 differential amplifiers as comparators, where r is the number of binary digits of the output signal of the analog-to-digital converter minus one. The composite color signal is then applied as the input signal to the noninverting (or inverting) inputs of all p differential amplifiers and the inverting (noninverting) inputs of the differential amplifiers being connected successively to the taps of a resistive voltage divider which contains equal-value resistors and is fed with a reference voltage (Ur).
For the duration of every second line, either the reference voltage or the input signal is shifted by ΔU=0.5 Ur/2r. 1. A color-television receiver comprising at least one integrated circuit for separating and conditioning the luminance signal and the chrominance signals from the composite color signal, said integrated circuit containing:
a chrominance-subcarrier oscillator,
a chrominance-subcarrier band-pass filter,
a synchronous demodulator,
a PAL switch,
a color matrix, and, if necessary,
an R--G--B matrix, and being characterized by the following subcircuits for conditioning digital signals:
the chrominance-subcarrier oscillator is a squarewave clock generator providing four clock signals the first of which has four times the chrominance-subcarrier frequency and the second to fourth of which have the chrominance-subcarrier frequency, with the first and second clock signals having a pulse duty factor of 0.5, and the third and fourth clock signals each consisting of two consecutive, T/2-long pulses separated by T/2 within each 4T-long period (T=period of the first clock signal);
an analog-to-digital converter clocked by the first clock signal, whose analog input is presented with the composite color signal, and which forms as its output signal a parallel binary word from the amplitude of the composite color signal (F) at the instants the respective amplitudes of the undemodulated chrominance signal are equal to the amplitudes of the respective color-difference signal;
a first binary arithmetic stage which multiplies the output signal of the analog-to-digital converter by a binary overall-contrast control signal;
a two-stage delay line which delays the output signal of the first binary arithmetic stage by T/2;
a second binary arithmetic stage which forms the arithmetic mean of the delayed and undelayed output signals of the first binary arithmetic stage;
a third binary arithmetic stage which subtracts the output signal of the second binary arithmetic stage from the output signal of the first delay stage;
a buffer-memory arrangement which temporarily stores the output signal of the third binary arithmetic stage, and whose enable input is fed with the third clock signal;
a shift-register arrangement consisting of n parallel shift registers (n=number of bits at the output of the third binary arithmetic stage) each of which provides a delay of one line period and whose serial inputs are connected to the parallel outputs of the buffer-memory arrangement, while their clock inputs are fed with the fourth clock signal;
a fourth binary arithmetic stage which forms the arithmetic mean of the input and output signals of the shift-register arrangement;
a fifth binary arithmetic stage which subtracts the input signal of the shift-register arrangement from the output signal of this arrangement and then divides the difference by two;
a sixth binary arithmetic stage which, controlled by the PAL switch, either leaves the output signal of the fifth binary arithmetic stage unchanged or forms its absolute value;
a seventh binary arithmetic stage which forms the green color-difference signal from the output signals of the fourth and sixth binary arithmetic stages;
the outputs of the second, fourth, sixth and seventh binary arithmetic stages are connected to the binary R-G-B matrix each of whose outputs is coupled to one of three digital-to-analog converters for deriving the analog signals for controlling the R-G-B values of the picture tube, or
the outputs of the second, fourth, sixth and seventh binary arithmetic stages are each connected to one of four digital-to-analog converters for deriving the analog signals for controlling the color-difference value of the picture tube;
the improvement wherein
the analog-to-digital converter is a parallel analog-to-digital converter with p=2r -1 differential amplifiers as comparators, where r is the number of binary digits of the output signal of the analog-to-digital converter minus one, the composite color signal being applied as the input signal to one of the noninverting or inverting inputs of all p differential amplifiers and the other of the inverting or noninverting inputs of the differential amplifiers being connected successively to the taps of a resistive voltage divider which contains equal-value resistors and is fed with a reference voltage (Ur), and
for the duration of every second line, either the reference voltage (Ur) or the input signal (F) is shifted by ΔU=0.5 Ur/2r.

Description:

FIELD OF THE INVENTION Color-television receivers comprising at least one integrated circuit for separating and conditioning the luminance signal and the chrominance signals from the composite color signal are known in the art. The particular color-television receiver of such a known type comprises at least one integrated circuit for separating and conditioning the luminance signal and the chrominance signals from the composite color signal. This integrated circuit contains a chrominance-subcarrier oscillator, a chrominance-subcarrier band-pass filter, a synchronous demodulator, a PAL switch, a color matrix, and, if necessary, an R-G-B matrix. Additionally, such a color-television receiver contains the following subcircuits for conditioning digital signals; (1) the chrominance-subcarrier oscillator is a square-wave clock generator providing four clock signals the first of which has four times the chrominance-subcarrier frequency and the second to fourth of which have the chrominance-subcarrier frequency, with the first and second clock signals having a pulse duty factor of 0.5, and the third and fourth clock signals each consisting of two consecutive, T/2-long pulses separated by T/2 within each 4T-long period (T=period of the first clock signal); (2) an analog-to-digital converter clocked by the first clock signal, whose analog input is presented with the composite color signal, and which forms as its output signal a parallel binary word from the amplitude of the composite color signal (F) at the instants the respective amplitudes of the undemodulated chrominance signal are equal to the amplitudes of the respective color-difference signal; (3) a first binary arithmetic stage which multiplies the output signal of the analog-to-digital converter by a binary overall-contrast control signal; (4) a two stage delay line which delays the output signal of the first binary arithmetic stage by T/2; (5) a second binary arithmetic stage which forms the arithmetic means of the delayed and undelayed output signals of the first binary arithmetic stage; (6) a third binary arithmetic stage, which subtracts the output signal of the second binary arithmetic stage from the output signal of the first delay stage; (7) a buffer-memory arrangement which temporarily stores the output signal of the third binary arithmetic stage, and whose enable input is fed with the third clock signal; (8) a shift-register arrangement consisting of n parallel shift registers (n=number of bits at the output of the third binary arithmetic stage) each of which provides a delay of one line period and whose serial inputs are connected to the parallel outputs of the buffer-memory arrangement, while their clock inputs are fed with the fourth clock signal; (9) a fourth binary arithmetic stage which forms the arithmetic mean of the input and output signals of the shift-register arrangement; (10) a fifth binary arithmetic stage which subtracts the input signal of the shift-register arrangement from the output signal of this arrangement and then divides the difference by two; (11) a sixth binary arithmetic stage which, controlled by the PAL switch, either leaves the output signal of the fifth binary arithmetic stage unchanged or forms its absolute value; (12) a seventh binary arithmetic stage which forms the green color-difference signal from the output signals of the fourth and sixth binary arithmetic stages; (13) the outputs of the second, fourth, sixth and seventh binary arithmetic stages are connected to the binary R-G-B matrix each of whose outputs is coupled to one of three digital-to-analog converters for deriving the analog signals for controlling the R-G-B values of the picture tube, or (14) the outputs of the second, fourth, sixth and seventh binary arithmetic stages are each connected to one of four digital-to-analog converters for deriving the analog signals for controlling the color-difference values of the picture tube. An essential feature of such a receiver is the use of an analog-to-digital converter whose analog input is presented with the composite color signal and which is clocked by a clock signal at four times the chrominance-subcarrier frequency, so that a parallel binary word is obtained from the amplitudes of the composite color signal at the instants the respective amplitudes of the undemodulated chrominance signal are equal to the amplitudes of the respective color-difference signal. Thus, because of the high frequencies to be be processed, a parallel analog-to-digital converter is needed. Such fast parallel analog-to-digital converters are well known (cf. D. F. Hoeschele, "Analog-to-Digital/Digital-to-Analog Conversion Techniques", New York, 1968, p. 10) and contain 2 s -1 differential amplifiers as comparators, where s is the number of binary digits of the digital converter output signal. The noninverting (or inverting) inputs of all differential amplifiers are presented with the composite color signal, while the inverting (or noninverting) inputs are connected successively to the taps of a resistive voltage divider inserted between a constant reference voltage and ground and consisting of 2 s or 2 s -1 equal-value resistors.
A 6-bit parallel analog-to-digital converter thus has 63 comparators and 63 resistors. A 7-bit converter has 127 comparators and resistors, and an 8-bit converter even has 255 comparators and resistors. It is readily apparent that as the number of digits increases, the implementation of such converters using integrated circuit techniques quickly becomes uneconomical. In particular, a reduction by one digit would result in the component count being halved. SUMMARY OF THE INVENTION
Accordingly, the object of the invention is to reduce the number of comparators and resistors in an arrangement as set forth hereinbefore to one half without adversely affecting the digital resolution. In other words, the invention is to permit a 6-bit resolution, for example, to be achieved with a 5-bit converter. This is done by using the means set forth above recourse being had to the principle described in the above-cited book on pp. 413 to 415 as follows: In color-television receiver described above, the analog-to-digital converter is a parallel analog-to-digital converter with p=2 r -1 differential amplifiers as comparators, where r is the number of binary digits of the output signal of the analog-to-digital converter minus one. The composite color signal is then applied as the input signal to the noninverting (or inverting) inputs of all p differential amplifiers and the inverting (noninverting) inputs of the differential amplifiers being connected successively to the taps of a resistive voltage divider which contains equal-value resistors and is fed with a reference voltage (Ur). For the duration of every second line, either the reference voltage or the input signal is shifted by ΔU=0.5 Ur/2 r . BRIEF DESCRIPTION OF THE DRAWINGS
The invention will now be explained in more detail with reference to the accompanying drawings, in which:
FIG. 1 shows the block diagram of a color-television receiver of a known type.
FIGS. 2a-h, k, l, and p-t show various waveforms occurring in the arrangement of FIG. 1, and, in tabular form, signals occurring at given points of the circuit at given times, and
FIG. 3 is a block diagram of a preferred embodiment of the invention. DESCRIPTION OF THE BEST MODE
At the outset, FIG. 1, will be explained to permit a better understanding of the invention. In the block diagrams shown in FIGS. 1 to 3, like parts are designated by like reference characters. In addition to interconnections indicated by solid lines as is usual in circuit diagrams, these figures contain interconnections indicated by stripes. These stripes mark connections between digital parallel outputs of the delivering portion of the circuit and digital parallel inputs of the receiving portion. The interconnections indicated by stripes, therefore, consist of at least as many wires as there are bits in the binary word to be transferred. Thus, the signals transferred over the lines indicated by stripes in FIGS. 1 to 3 are all binary signals whose instantaneous binary value corresponds to the instantaneous analog value of the composite color signal and of other signals. Like in conventional color-television receivers, the composite color signal F, derived in the usual manner controls the chrominance-subcarrier oscillator, which, according to the invention, is designed as a squarewave clock generator 1. By means of the so-called burst contained in the composite color signal F, the clock generator 1 is synchronized to the transmitted chrominance-subcarrier frequency. The clock generator 1 generates the clock signal F1, whose frequency is four times the chrominance-subcarrier frequency, i.e. about 17.73 MHz (precisely 17.734475 MHz) in the case of the CCIR standard.
The clock generator 1 also generates the square-wave clock signal F2 having the frequency of the chrominance subcarrier. The first and second clock signals F1, F2 have a pulse duty factor of 0.5 (cf. FIGS. 2a and 2b). In addition, the clock generator 1 generates the third clock signal F3 and the fourth clock signal F4, each of which consists of two consecutive, T/2-long pulses separated by T/2 within each 4T-long period, where T is the period of the first clock signal F1. The third and fourth clock signals F3, F4 are shown in FIGS. 2b and 2g.
The individual clock signals are generated within the clock generator 1 in the usual manner using conventional digital techniques. The clock signal F1, for instance, may be generated by means of a suitable 17.73--MHz crystal, and the clock signals F2, F3, F4 may be derived therefrom by frequency division and suitable elimination of pulses. Like in conventional color-television receivers, the clock generator 1 is also fed with a pulse Z from the horizontal output stage during which the clock generator 1 is sychronized by the burst. The composite color signal F is also applied to the analog input of the analog-to-digital converter 2, which is clocked by the first clock signal F1 and, (at the beginning of each pulse of the first clock signal F1) forms from the amplitude of this pulse a parallel binary word and delivers it as an output signal. These leading edges of the pulses of the first clock signal F1 thus occur at the instants the respective amplitudes of the undemodulated chrominance signal contained in the composite color signal are equal to the amplitudes of the respective color-difference signal.
These parallel binary words then remain unchanged for the respective period T of the first clock signal F1, i.e., they are held like in a sample-and-hold circuit. The signals appearing at the output of the analog-to-digital converter 2 are given in tabular form in FIG. 2c, where the vertical lines symbolize the respective clock periods of the first clock signal F1. The letter c of FIG. 2 is also shown in FIG. 1 (encircled).
According to FIG. 2c, successive signals Y+V, Y-U, Y-V, and Y+U are obtained in a line m during one period of the second clock signal F2, where U, V and Y have the formal meanings given in the above-mentioned book, namely U=B-Y, V=R-Y, B=blue chrominance signal, R=red chrominance signal, and Y=luminance signal, but designate here the corresponding digitized signals, i.e., the corresponding binary words. The second line in the Table of FIG. 2c gives the corresponding binary signals in the line m+1, namely the signals Y-V, Y-U and Y+U, occurring during that period of the clock signal F2 which is under consideration.
This output signal of the analog-to-digital converter 2 is applied to one of the two inputs of the first binary arithmetic stage 10, which multiplies this output signal by a binary overall-contrast control signal GK. This overall contrast control signal thus corresponds to the analog overall-contrast control signal present in conventional color-television receivers. In present day color-television receivers, the binary overall contrast control signal GK, just as the binary color-saturation control signal FK and the binary brightness control signal H to be explained below, is available in digital form, because remote-control units and digital controls are usually present which provide these signals.
An advantage of the present application is, therefore, seen in the fact that these signals need no longer be conditioned in analog form in their place of action.
The output signal of the first binary arithmetic stage 10 is fed to the second binary arithmetic stage 20 and to the two-stage delay line 3, which delays this output signal by T/2. The second binary arithmetic stage 20 forms the arithmetic mean of the delayed and undelayed signals. The underlying idea is that if a sinusoidal signal, namely the chrominance subcarrier, is sampled at double frequency, the mean of two successive sample values will always be zero. Thus, by forming the arithmetic means in the second binary arithmetic stage 20, the chrominance subcarrier is suppressed and the luminance signal Y is obtained in digital form.
The output signal of the first binary arithmetic stage 10, delayed in the first stage 31 of the delay line 3 by half the delay provided by this stage, i.e., by T/4, and the output signal of the second binary arithmetic stage 20 are then fed to the third binary arithmetic stage 30, which subtracts the latter signal, i.e., the Y signal, from the former signal. As a result, the output of the third binary arithmetic stage 30 provides the color-difference signal, made up of the successive components B-Y, R-Y, -(B-Y) and -(R-Y), as shown in FIG. 2d in tabular form for the lines m and m+1.
These signals are fed to the buffer-memory arrangement 4, whose enable input is fed with the third clock signal F3, which is shown in FIG. 2e. This buffer memory operates in such a manner that the binary word fed to the input at the beginning of each pulse of the third clock signal F3 appears at the output when the next clock pulse occurs. Thus, the instantaneous output signals given in FIG. 2f in tabular form for the lines m and m+1 are obtained. The individual stages of the buffer-memory arrangement may be so-called D flip-flops, for example.
The output signal of the buffer-memory arrangement 4 is applied to the shift-register arrangement 5, which consists of n parallel shift registers, where n is the number of bits at the ouput of the third binary arithmetic stage 30. The delay provided by the n parallel shift registers is equal to the duration of one line, i.e., 64 μs in the case of PAL television sets. The clock inputs of the n parallel shift registers are fed with the fourth clock signal F4, which is shown in FIG. 2g. The output signal of the shift-register arrangement is given in tabular form in FIG. 2h for the lines m and m+1.
This output signal, together with the input signal of the shift-register arrangement 5 is fed to the fourth binary arithmetic stage 40, which forms the arithmetic means of the two signals, so that its output provides the signal B-Y in digital form, which is given in tabular form in FIG. 2k. The input and output signals of the shift-register arrangement 5 are also fed to the fifth binary arithmetic stage 50, which subtracts the input signal from the output signal and divides the difference by two. By the division, a sort of averaging is performed as well.
The output signal of the fifth binary arithmetic stage 50 is given in tabular form in FIG. 21, again for the lines m and m+1. This output signal is fed to the sixth binary arithmetic stage 60, which, in response to the output signal of the PAL switch 12, leaves it unchanged in one line and forms its absolute value in the other. "To form the absolute value" is used here first of all in the mathematical sense i.e., the negative sign of a negative number is suppressed and only the positive value of this negative number is taken into account. Within the scope of the present invention, however, "absolute value" also means "value with respect to a constant number". By this it is meant that for a number A below the constant X, the "absolute value with respect to X" is 2X-A. Thus, for the number 30, the "absolute value with respect to 50" is 70. The output of the sixth binary arithmetic stage 60 thus provides the PAL compensated signal R-Y in digital form, i.e., the red color-difference signal, which is given in tabular form in FIG. 2p for the lines m and m+1.
The output signals of the fourth binary arithmetic stage 40 and of the sixth binary arithmetic stage 60 are fed to the seventh binary arithmetic stage 70, which forms the green color-difference signal G-Y by the well-known formula Y=0.3R+0.59G+0.11B.
The subcircuits 5, 40, 50, 60 and 70, together with the PAL switch 12, represent the portion for correcting the phase of the received signal by the PAL method.
The output signals of the second, fourth, sixth and seventh binary arithmetic stages 20, 40, 60, 70, i.e., the luminance signal Y and the color-difference signals B-Y, R-Y, and G-Y, are then fed to the binary R-G-B matrix 6, which forms therefrom the binary chrominance signals R, G, B by the above formula. Each of these binary chrominance signals is then fed to one of the three digital-to-analog converters 7, 8, 9, which convert the binary chrominance signals to the analog chrominance signals R', G', B' necessary for R-G-B control of the picture tube.
In the embodiment of FIG. 1, each of thes digital-to-analog converters is also fed with the color-saturation control signal FK and the brightness control signal H, both in binary form. The PAL switch 12 is fed with the second clock signal F2, i.e., a signal having the chrominance-subcarrier frequency locked to the burst, with the composite color signal F, and with the reference pulse Z from the horizontal output stage.
FIG. 3 shows the block diagram of an embodiment of the invention. The analog-to-digital converter 2 is designed as a parallel analog-to-digital converter 2' and contains the differential amplifiers D1, D2, D3, Dp-1, Dp which are used as comparators, the resistors R1, R2, R3, Rp-1, Rp, RO, connected in series to form a voltage divider, and the decoder 21, which changes the output signals of the comparators into corresponding binary words. That portion of FIG. 3 located on the right-hand side of the decoder 21 is a greatly simplified representation of the units designated by like reference characters in FIG. 1.
The parallel analog-to-digital converter 2' contains p=2 r -1 differential amplifiers and a corresponding number of resistors, where r is the number of binary digits of the output signal of the analog-to-digital converter 2 of FIG. 1 minus one. If the analog-to-digital converter is to provide 8 bits, for example, then r is 7. The resistors R2 to Rp are alike and have a value of R, while the resistors RO, R1 have a value of 0.5 R.
According to the invention, the reference voltage applied to the comparators, in the embodiment of FIG. 3 to all inverting inputs, is shifted by ΔU=0.5 Ur/2 r during every second line as electronic switches S1 and S2 in parallel with resistors R1 and RO, respectively, are opened and closed alternately. Their control signal comes from one of the outputs Q, Q of the binary divider BT, which is fed with the horizontal synchronizing or horizontal flyback pulses Z.
Instead of shifting the reference voltage Ur as described, the amount of change ΔU may be added to the composite color signal in an analog adding stage during every second line. The reference voltage UR then remains constant.
By influencing the reference voltage Ur during every second line, and with the fourth or fifth binary arithmetic stage 40, 50 and the shift-register arrangement 5, which acts as a delay stage providing a delay of exactly one line period, the intended effect is produced, i.e., the number of comparators required is reduced to one half, while the resolution corresponds to that achieved with an additional binary digit since the average of the signals of two successive lines is taken at the output of the fourth or fifth binary arithmetic stage 40,50.
The principle explained with the aid of FIG. 3 can also be applied to the luminance channel if a comb filter and a delay arrangement providing a delay of one line period are provided in this channel.

Digital integrated chrominance-channel circuit with gain control:

(Pal) Video Processing Unit (VPU - PVPU)

An improved digital integrated chrominance-channel circuit having gain control for color-television receivers includes at least one integrated circuit for digitally processing the composite color signal. The circuit includes a first limiter inserted between a parallel multiplier and a burst-amplitude-measuring stage, and a control stage including a parallel subtracter whose minuend input is fed with a reference signal, and whose subtrahend input is connected to the output of the burst-amplitude-measuring stage. A digital accumulator whose enable input is presented with a signal derived from the trailing edge of a burst gating signal is used as an integrator.
1. A digital integrated chrominance-channel circuit with gain control for color-television receivers, comprising:
at least one integrated circuit for digitally processing the composite color signal, wherein a digital chrominance signal appearing at an output of a digital chroma filter is applied to a first input of a parallel multiplier, and a digital gain control signal is applied to a second input of the parallel multiplier, the output of the parallel multiplier is connected to an input of a digital chroma demodulator with a color killer stage and to an input of a burst-amplitude-measuring stage whose output signal is compared with a reference signal in a control stage, the output signal of the control stage passes through an integrator whose output signal is the gain control signal;
a square-wave clock generator used as a chrominance subcarrier oscillator generates at least a first clock signal, whose frequency is four times that of the chrominance subcarrier, and a second clock signal, whose frequency is equal to that of the chrominance subcarrier; and
a first limiter is inserted between the parallel multiplier and the burst-amplitude-measuring stage, the control stage is a parallel subtracter whose minuend input is presented with the reference signal, and whose subtrahend input is connected to the output of the burst-amplitude-measuring stage and the integrator is a digital accumulator whose enable input is fed with a signal derived from the trailing edge of a burst gating signal.
2. A chrominance-channel circuit as claimed in claim 1, wherein the output signal from the first limiter is applied to the input of a first buffer memory and, through a delay element which provides a delay equal to the period of the first clock signal, to the input of a second buffer memory, the second clock signal being applied to the enable inputs of the first and second buffer memories during the burst gating signal, the output signals from the first buffer memory and the second buffer memory are fed, respectively, to a first absolute-value former and a second absolute-value former which have their outputs connected to the first and the second input, respectively, of a first parallel adder, the output of the first parallel adder is connected via a second limiter to the input of a third buffer memory and to the minuend input of a parallel comparator whose minuend-greater-than-subtrahend output is coupled to the enable input of the third buffer memory through the first input-output path of an AND gate whose second input is fed with the second clock signal, and the output of the third buffer memory is coupled to the subtrahend input of the parallel comparator, the output of the third buffer memory is connected to the input of a fourth buffer memory whose output is coupled to the subtrahend input of the parallel subtracter, and whose enable input is fed with a signal derived from the leading edges of horizontal-frequency pulses not coinciding with the burst gating signal, and the clear input of the third buffer memory is fed with a signal derived from the trailing edges of the pulses not coinciding with the burst gating signal. 3. A chrominance-channel circuit as claimed in claim 1, wherein the output signal from the parallel subtracter is applied to the first input of a second parallel adder having its output connected via a third limiter to the input of a fifth buffer memory whose output is coupled to the second input of the second parallel adder, and which has normalizing-data inputs and the enable input of the accumulator. 4. A chrominance-channel circuit as claimed in claim 2, wherein the output signal from the parallel subtracter is applied to the first input of a second parallel adder having its output connected via a third limiter to the input of a fifth buffer memory whose output is coupled to the second input of the second parallel adder, and which has normalizing-data inputs and the enable input of the accumulator. 5. A chrominance-channel circuit as claimed in claim 1, additionally comprising:
a first bus switch having its path from the break-contact input to the output inserted between the output of the chroma filter and the associated input of the parallel multiplier and its make-contact input connected to the input of the chroma filter;
a second bus switch having its path from the break-contact input to the output inserted between the output of the first limiter and the input of the chroma demodulator and its make-contact input connected to the input of the chroma filter;
a first test enable signal and a second test enable signal, which does not overlap the first test enable signal, being applied to the control input of the first bus switch and to the control input of the second bus switch, respectively;
an actuating signal being applied to the input of the color killer stage during the second test enable signal;
a normalizing signal being applied to the enable input of the fifth buffer memory during a third test enable signal; and
in addition to the usual contact pads, there is a contact pad via which the test-result signals of the individual subcircuits are accessible.
6. A chrominance-channel circuit as claimed in claim 2, additionally comprising:
a first bus switch having its path from the break-contact input to the output inserted between the output of the chroma filter and the associated input of the parallel multiplier and its make-contact input connected to the input of the chroma filter;
a second bus switch having its path from the break-contact input to the output inserted between the output of the first limiter and the input of the chroma demodulator and its make-contact input connected to the input of the chroma filter;
a first test enable signal and a second test enable signal, which does not overlap the first test enable signal, being applied to the control input of the first bus switch and to the control input of the second bus switch, respectively;
an actuating signal being applied to the input of the color killer stage during the second test enable signal;
a normalizing signal being applied to the enable input of the fifth buffer memory during a third test enable signal; and
in addition to the usual contact pads, there is a contact pad via which the test-result signals of the individual subcircuits are accessible.
7. A chrominance-channel circuit as claimed in claim 3, additionally comprising:
a first bus switch having its path from the break-contact input to the output inserted between the output of the chroma filter and the associated input of the parallel multiplier and its make-contact input connected to the input of the chroma filter;
a second bus switch having its path from the break-contact input to the output inserted between the output of the first limiter and the input of the chroma demodulator and its make-contact input connected to the input of the chroma filter;
a first test enable signal and a second test enable signal, which does not overlap the first test enable signal, being applied to the control input of the first bus switch and to the control input of the second bus switch, respectively;
an actuating signal being applied to the input of the color killer stage during the second test enable signal;
a normalizing signal being applied to the enable input of the fifth buffer memory during a third test enable signal; and
in addition to the usual contact pads, there is a contact pad via which the test-result signals of the individual subcircuits are accessible.
8. A chrominance-channel circuit as claimed in claim 4, additionally comprising:
a first bus switch having its path from the break-contact input to the output inserted between the output of the chroma filter and the associated input of the parallel multiplier and its make-contact input connected to the input of the chroma filter;
a second bus switch having its path from the break-contact input to the output inserted between the output of the first limiter and the input of the chroma demodulator and its make-contact input connected to the input of the chroma filter;
a first test enable signal and a second test enable signal, which does not overlap the first test enable signal, being applied to the control input of the first bus switch, respectively;
an actuating signal being applied to the input of the color killer stage during the second test enable signal;
a normalizing signal being applied to the enable input of the fifth buffer memory during a third test enable signal; and
in addition to the usual contact pads, there is a contact pad via which the test-result signals of the individual subcircuits are accessible.
9. A method of testing a chrominance-channel circuit as claimed in claim 5, characterized by the following features:
in a first step, the chroma demodulator is tested by applying the second test enable signal to the control input of the second bus switch, the actuating signal to the input of the color killer stage, and a known data sequence to the input of the chroma filter;
in a second step, the parallel multiplier is tested by applying the first test enable signal to the control input of the first bus switch, the third test enable signal and the normalizing signal to the enable input of the accumulator, the normalizing data to the normalizing-data input of the accumulator, and a known data sequence to the input of the chroma filter;
in further steps, the absolute-value formers the first adder, and the parallel comparator are tested by applying the first test enable signal to the control input of the first bus switch, and known data sequences to the input of the chroma filter, and
in the last step, the accumulator is tested by applying the first test enable signal to the control input of the first bus switch, the third test enable signal and the normalizing signal to the enable input of the accumulator, the normalizing data to the normalizing data to the normalizing-data input of the accumulator, a trigger signal to the second limiter, and known data sequences to the minuend input of the parallel sub- tracter.
10. A method of testing a chrominance-channel circuit as claimed in claim 6, characterized by the following features:
in a first step, the chroma demodulator is tested by applying the second test enable signal to the control input of the second bus switch, the actuating signal to the input of the color killer stage, and a known data sequence to the input of the chroma filter;
in a second step, the parallel multiplier is tested by applying the first test enable signal to the control input of the first bus switch, the third test enable signal and the normalizing signal to the enable input of the accumulator, the normalizing data to the normalizing-data input of the accumulator, and a known data sequence to the input of the chroma filter;
in further steps, the absolute-value formers the first adder, and the parallel comparator are tested by applying the first test enable signal to the control input of the first bus switch, and known data sequences to the input of the chroma filter, and
in the last step, the accumulator is tested by applying the first test enable signal to the control input of the first bus switch, the third test enable signal and the normalizing signal to the enable input of the accumulator, the normalizing data to the normalizing-data input of the accumulator, a trigger signal to the second limiter, and known data sequences to the minuend input of the parallel subtracter.
11. A method of testing a chrominance-channel circuit as claimed in claim 7, characterized by the following features:
in a first step, the chroma demodulator is tested by applying the second test enable signal to the control input of the second bus switch, the actuating signal to the input of the color killer stage, and a known data sequence to the input of the chroma filter;
in a second step, the parallel multiplier is tested by applying the first test enable signal to the control input of the first bus switch, the third test enable signal and the normalizing signal to the enable input of the accumulator, the normalizing data to the normalizing-data input of the accumulator, and a known data sequence to the input of the chroma filter;
in further steps, the absolute-value formers the first adder, and the parallel comparator are tested by applying the first test enable signal to the control input of the first bus switch, and known data sequences to the input of the chroma filter, and
in the last step, the accumulator is tested by applying the first test enable signal to the control input of the first bus switch, the third test enable signal and the normalizing signal to the enable input of the accumulator, the normalizing data to the normalizing-data input of the accumulator, a trigger signal to the second limiter, and known data sequences to the minuend input of the parallel subtracter.
12. A method of testing a chrominance-channel circuit as claimed in claim 8, characterized by the following features:
in a first step, the chroma demodulator is tested by applying the second test enable signal to the control input of the second bus switch, the actuating signal to the input of the color killer stage, and a known data sequence to the input of the chroma filter;
in a second step, the parallel multiplier is tested by applying the first test enable signal to the control input of the first bus switch, the third test enable signal and the normalizing signal to the enable input of the accumulator, the normalizing data to the normalizing-data input of the accumulator, and a known data sequence to the input of the chroma filter;
in further steps, the absolute-value formers the first adder, and the parallel comparator are tested by applying the first test enable signal to the control input of the first bus switch, and known data sequences to the input of the chroma filter, and
in the last step, the accumulator is tested by applying the first test enable signal to the control input of the first bus switch, the third test enable signal and the normalizing signal to the enable input of the accumulator, the normalizing data to the normalizing-data input of the accumulator, a trigger signal to the second limiter, and known data sequences to the minuend input of the parallel subtracter.

Description:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a digital integrated chrominance-channel circuit with gain control for color-television receivers containing at least one integrated circuit for digitally processing the composite color signal.
2. Description of the Prior Art
A chrominance-channel circuit is disclosed in the published patent application EP 51075 Al. (U.S. application Ser. No. 311,218, Oct. 11, 1981).
Practical tests of color-television receivers with digital signal processing circuitry have shown that the prior art chrominance-channel circuit still has a few disadvantages. For example, the burst-amplitude-measuring circuit is not yet optimal because it is possible in the prior art arrangement that the burst signals are sampled, i.e., measured, near or at the zero crossing. As these measured values are small, so that the digitized values formed therefrom are small numbers, the measurement error is large.
Another disadvantage of the prior art arrangement is that it has two set points for the gain control, namely a lower and an upper threshold level in the form of corresponding numbers entered into two read-only memories. Finally, the integration of the control signal is implemented with two counters, so that the time constant of this "integrator" is determined only by the clock signals for the counters and by the count lengths of these counters. As to the prior art, reference is also made to the journal "Fernseh- und Kino-Technik", 1981, pages 317 to 323, particularly FIG. 9 on page 321. However, the digital chrominance-channel circuit shown there works on the principle of feed-forward control, while both the invention and the above-mentioned prior art use a feedback control system, so that the arrangement disclosed in that journal lies further away from the present invention, the more so since in that prior art arrangement, the set point is implemented only with the concrete circuit (hardware). SUMMARY OF THE INVENTION
The invention as claimed eliminates the above disadvantages and, thus, has for its object to improve the prior art digital integrated chrominance-channel circuit with gain control in such a way that error-free burst amplitude measurement is ensured, that a single set point can be generated, and that the integration of the control signal is implemented in optimum fashion. Another object of the invention is to modify the chrominance-channel circuit so that the automatic control system can be opened for measuring purposes. DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of the chrominance channel in accordance with the invention.
FIG. 2 is a block diagram of a preferred embodiment of the burst-amplitude-measuring stage and the digital accumulator.
FIG. 3 is a block diagram of another embodiment of the invention with the aforementioned measuring facility. DESCRIPTION OF THE INVENTION The block diagram of FIG. 1 includes a digital chroma filter cf, which derives a digital chrominance signal cs from a digitized composite color signal. The digital chrominance signal cs is applied to a first input of a parallel multiplier m, whose second input is fed with a digital gain control signal st. The output of the parallel multiplier m is connected to an input of a first limiter b1, which limits the output signals from the parallel multiplier m to a predetermined value. This can be done by arranging, for example, that at least one of the high-order digits of the output signal from the parallel multiplier is indicated by the interconnecting lead between these two subcircuits in FIG. 1.
In the figures of the accompanying drawing, the lines interconnecting the signal inputs and outputs of the individual subcircuits are shown as stripelike connections (buses), while the solid lines commonly used to indicate interconnections in discrete-component circuits are used for interconnections over which only individual bits or clock and/or noise signals are transferred. The stripelike lines thus interconnect parallel inputs and parallel outputs, i.e., inputs to which complete binary words are applied, which are transferred in parallel into the subcircuit at a given time, and outputs which provide complete binary words.
An output signal bs of the first limiter b1 is applied to the input of a burst-amplitude-measuring stage bm, which has its output coupled to a subtrahend input (-) of a parallel subtracter sb, while its minuend input (+) is fed with the reference signal rs, i.e., the set point. The output of the parallel subtracter sb is connected to the input of a digital accumulator ak, which provides the digital gain control signal st, which is applied to the second input of the parallel multiplier m, as mentioned above. A signal rb derived from the trailing edge of the burst gating signal (keying pulse) is applied to an enable input eu of the accumulator ak.
It is also indicated in FIG. 1 that a square-wave clock generator os, used as a chrominance-subcarrier oscillator, forms part of the invention. It provides at least the first clock signal f1, whose frequency is four times that of the chrominance subcarrier, and a second clock signal f2, having the same frequency as the chrominance subcarrier. FIG. 2 is a block diagram of a preferred embodiment of the burst-amplitude-measuring stage bm and the digital accumulator ak of FIG. 1. The burst-amplitude-measuring stage in FIG. 2 comprises all subcircuits ahead of the subtrahend input (-) of the parallel subtracter sb, while the accumulator consists of the subcircuits following the output of the parallel subtracter sb.
The output signal bs from the first limiter b1 of FIG. 1 is applied in FIG. 2 to the input of a first buffer memory p1 and, through a delay element v, which provides a delay equal to the period of the first clock signal f1, i.e., to one quarter or 90° of the chrominance-subcarrier frequency, to an input of a second buffer memory p2.
The second clock signal f2 is applied to the enable inputs eu of these two buffer memories p1, p2 during the burst gating signal ki, which is indicated in FIG. 2 by the logical term f2.ki. During the keying pulse ki, whose duration usually equals about 10 periods of the chrominance-subcarrier frequency, a corresponding number of digital values are thus transferred successively from the first limiter b1 into the two buffer memories p1, p2, the values transferred into the second buffer memory p2 differing in phase from those transferred into the first buffer memory p1 by the aforementioned 90°; thus, two zero-crossing values are never evaluated at the same time.
The outputs of the two buffer memories p1, p2 are connected to the inputs of a first absolute-value former bb1 and a second absolute-value former bb2, respectively, whose outputs are coupled to a first and a second input, respectively, of a first adder a1. The absolute-value formers bb1, bb2 provide digital values without the sign of the input value, i.e., without the sign bit, for example. They thus contain a subcircuit which converts negative numbers in one's or two's complement notation into the corresponding positive number, i.e., they include complement reconverters.
The first adder a1 is followed by the second limiter b2, whose limiting action is controlled by at least one of the high-order digits of the first adder a1.
The output signal from the second limiter b2 is applied to the input of a third buffer memory p3 and to a minuend input a of a parallel comparator k, which has its subtrahend input b connected to the output of the third buffer memory p3.
In the present description, the two inputs of the parallel comparator k, too, are referred to as "minuend input" and "subtrahend input", respectively, which is considered justifiable in view of the fact that, purely formally, the arithmetic operation performed by comparators is more closely related to subtraction than to addition by means of an adder, even though the internal circuit of a comparator resembles that of an adder more than that of a subtracter, cf. the corresponding mathematical operations a-b and a b as opposed to a+b.
The minuend-greater-than-subtrahend output a>b of the parallel comparator k is connected to the enable input eu of the third buffer memory p3 via the first input-output path of the AND gate u, while the second clock signal f2 is applied to the second input of the AND gate u. The output of the third buffer memory p3 is also connected to an input of a fourth buffer memory p4, which has its output coupled to the subtrahend input (-) of the parallel subtracter sb. The enable input eu of the fourth buffer memory p4 is presented with a signal vz derived from the trailing edges of horizontal-frequency pulses zf, which, however, do not coincide with the burst gating signal ki, while a signal rz derived from the trailing edges of the horizontal-frequency pulses zf not coinciding with the burst gating signal ki is applied to the clear input el of the third buffer memory p3.
The derivation of the two signals rz, vz from the horizontal-frequency pulses zf is indicated in FIG. 2 by a pulse-shaper stage if. The section consisting of the two buffer memories p3, p4, the parallel comparator k, the AND gate u, and the pulse shaper if determines, for each line of the television picture, the maximum value of the burst amplitude from the--possibly limited--output signal of the first adder a1, and feeds this maximum value to the subtrahend input (-) of the parallel subtracter sb. This is achieved essentially by transferring only those words of the output signal of the second limiter b2 into the third buffer memory p3 which are greater than any word already stored in the third buffer memory p3. This is done line by line during the keying pulse ki.
As mentioned, a preferred embodiment of the accumulator ak of FIG. 1 is shown in the lower portion of FIG. 2. The output signal from the parallel subtracter sb is applied to a first input of a second parallel adder a2, which has its output connected to an input of a fifth buffer memory p5 through the third limiter b3. To realize the adding function, the output of the fifth buffer memory p5 is connected to the second input of the second adder a2. The buffer memory p5 has, in addition to the enable input eu, which is the enable input of the accumulator ak of FIG. 1, the normalizing-data inputs ne, through which normalizing data nd, i.e., known data, can be entered if necessary. The enable input eu is presented with the signal rb derived from the trailing edge of the burst gating signal ki. With the trailing edge of the keying pulse, the output signal from the third limiter b3 is thus transferred into the fifth buffer memory p5 and simultaneously transferred to the output. With the trailing edge of each keying pulse, the sum of the value from the preceding line and the set-point deviation calculated in the measured line by the parallel subtracter sb is thus produced line by line as the control signal st.
Thus, the essential advantages of the invention follow directly from the solution of the problem, namely particularly the line-by-line subtraction of the maximum burst amplitude, which is integrated in the accumulator ak to form the control signal st for the automatic control system, from the reference signal rs. FIG. 3, a block diagram like FIGS. 1 and 2, shows a preferred embodiment of the invention which makes it possible to test the digital automatic control system after the fabrication of the integrated circuit, and to make the test-result signals accessible. The testing is necessary because the automatic control system contains several subcircuits each of which may be faulty. The test procedure and the design of the overall circuit must therefore be adapted to one another in such a way that all subcircuits of the automatic control system can be tested with little additional circuitry.
To this end, the path from a break-contact input to an output of a first bus switch bu1, whose make-contact input is connected to the input of the chroma filter cf, is interposed between the output of this chroma filter and the associated input of the parallel multiplier m, as shown in the block diagram of FIG. 3. For the graphic representation of the bus switch bu1, the symbol of a mechanical transfer switch has been chosen, with the above mentioned stripelike interconnecting lines, i.e., buses, connected to the signal inputs and the output of the switch. It is thus clear that the bus switch consists of as many individual electronic switches as there are wires in the buses.
Inserted between the output of the first limiter b1 and the input of the chroma demodulator cd, which is also present in FIG. 1, where it "demodulates" the output signal bs of the first limiter b1 into the chroma signal cs, is a path from a break-contact input to an output of a second bus switch bu2, which has its make-contact input am connected to the input of the chroma filter cf. Viewed in the direction of signal flow, the second bus switch bu2 lies behind the junction point where the signal bs for the burst-amplitude-measuring circuit is taken off. What was said on the circuit design and the graphic representation of the first bus switch bu1 applies analogously to the second bus switch bu2.
The first test enable signal t1 and the second test enable signal t2, which does not overlap the first test enable signal t1, are applied to the control input of the first bus switch bu1 and to the control input of the second bus switch bu2, respectively. Thus, when the second bus switch bu2 is in its "make" position, the first bus switch bu2 is in its "break" position, and vice versa.
During the first test enable signal t1, an actuating signal db is applied to the input ec of the color killer stage ck of the chroma demodulator cd, so that the latter is active during the testing of the automatic control system although the circuit is not in its normal mode of operation but only in a test mode.
The enable input eu of the accumulator ak, i.e., the enable input eu of the fifth buffer memory p5 in FIG. 3, may be fed with a normalizing signal ns during the third test enable signal t3. During testing and measurement, instead of the signal rb, derived from the trailing edge of the keying pulse and applied in the normal mode of operation, the normalizing signal ns is applied to the enable input eu of the fifth buffer memory p5 and causes the normalizing data nd to be transferred into this buffer.
In addition to the usual contact pads of the integrated circuit, through part of which the output signal cs of the chroma demodulator cd is coupled out, a contact pad is provided via which test-result signals of individual subcircuits are accessible, i.e., transferred out of the integrated circuit. These test-result signals are advantageously coupled to this additional contact pad through transfer transistors which, in turn, are driven by the above-mentioned test enable signals or corresponding additional signals of this kind or by signals derived by performing simple logic operations on the signals just mentioned. In this manner, only the respective subcircuit to be tested is connected to the additional contact pad.
An advantageous method of testing the chrominance-channel circuit according to the invention consists in the following time sequence of test steps. In the first step, the chroma demodulator cd is tested. This is necessary because, throughout the testing of the chrominance-channel circuit, signals are transferred out through the chroma demodulator cd and must not be falsified by the latter.
This first test step is performed by applying the second test enable signal t2 to the control input of the second bus switch bu2, the actuating signal db to the input ec of the color killer stage ck, and a known data sequence, i.e., a test-data sequence, to the input of the chroma filter cf. The application of the actuating signal db to the input ec of the color killer stage ck is necessary because an actual actuating signal coming from other stages of the chrominance-channel circuit is applied to the color killer only during normal operation of the chrominance-channel circuit, cf. the above-mentioned printed publication EP 0 051 075 Al.
In response to the application of the second test enable signal t2 to the second bus switch bu2, the input signals of the chroma filter cf are transferred directly to the input of the chroma demodulator cd, so that, if a known test-data sequence is used, the performance of the chroma demodulator cd can be checked by means of the output signals.
In the second step, the parallel multiplier m is tested. This is done by applying the first test enable signal t1 to the control input of the first bus switch bu1, the third test enable signal t3 and the normalizing signal ns to the enable input of the accumulator ak, i.e., to the enable input of the fifth buffer memory p5, for example; the normalizing data nd are applied to the normalizing-data input ne of the fifth buffer memory p5, and a known data sequence, i.e., a test-data sequence, is applied to the input of the chroma filter cf.
As in the first test, the first test enable signal t1 causes the test-data sequence to bypass the chroma filter cf, so that the test data are applied directly to one input of the parallel multiplier m. This bypassing of the chroma filter cf is necessary because the chroma filter is generally a dynamic subcircuit, which is not suitable for being included in the individual tests for this reason alone.
As a result of the entry of normalizing data into the accumulator ak or into the fifth buffer memory p5 as a subcircuit of the accumulator, known data are also applied to the second input of the parallel multiplier m, so that the output signal of the latter is predeterminable, which makes it possible to check the correct functioning of the multiplier. Since the chroma demodulator cd was tested already in the first test step, the data appearing at its output during the second test step are the unchanged output data of the parallel multiplier m if the chroma demodulator cd was found to operate correctly.
Further tests may now be performed on the absolute-value formers bb1, bb2, the first adder a1, and the parallel comparator k. To do this, the first test enable signal t1 is applied to the control input of the first bus switch bu1, and known data sequences are applied to the input of the chroma filter cf, the individual test results being accessible via the above-mentioned additional contact pad and being generally present in the form of a go/no-go decision.
The last test to be performed is that of the accumulator ak. To this end, the first test enable signal t1 is applied to the control input of the first bus switch bu1; the third test enable signal t3 and the normalizing signal ns are applied to the enable input of the accumulator ak, i.e., to the corresponding input of the fifth buffer memory p5, for example; a trigger signal is applied to the second limiter b2, and known data sequences are fed to the minuend input (+) of the parallel subtracter sb. With the second limiter sb2 triggered, one of the input signals of the accumulator is predetermined and, thus, known because the output data of the subtracter sb are known as well. The accumulator ak can thus be tested by varying the reference data rs.
The reference data rs, the above-mentioned various test-data sequences, and the normalizing data nd may come from a microprocessor.

Digital deflection Processor (DPU)Instead of fine-controlling the horizontal deflection signal in a digital television receiver by means of two phase-locked loops and gate-delay stages as is done in prior art arrangements, in the horizontal-deflection circuit according to the invention, a first digital word delivered by a first phase-locked loop and representative of the horizontal frequency is added in an adder to a suitably amplified third digital word delivered by a phase comparator of a second phase-locked loop. The output of the adder is fed to the control input of a digital sine-wave generator which drives a frequency divider. The latter delivers the horizontal deflection signal, which drives the horizontal output stage. The phase comparator is fed with the horizontal flyback signal, which is derived from the horizontal deflection signal, and a second digital word generated by the first phase-locked loop and representative of the desired phase position of the flyback signal.

What is claimed is: 1. A digital horizontal-deflection circuit for generating an analog horizontal deflection signal driving the horizontal output stage of a digital television receiver clocked with a system clock, comprising:
a first digital phase-locked loop which synchronizes the horizontal deflection signal with the horizontal synchronizing signal separated from the composite color signal and delivers for each line of video signal a first digital word representative of the horizontal frequency and a second digital word representative of the desired phase position of the horizontal flyback signal;
a second phase-locked loop which uses a digital phase comparator to generate a third digital word representative of the phase deviation of the horizontal flyback signal from the desired position and shifts the horizontal deflection signal in time so that the horizontal flyback signal takes up the desired phase position;
an adder having a first input to which said first digital word is fed and a second input to which said third digital word is fed via a multiplier serving as an amplifier;
a digital sine-wave generator having a control input to which the output of said adder is fed; and
a frequency divider to which the output of said digital sine-wave generator is supplied, the output of said frequency divider providing the horizontal deflection signal.
2. A horizontal-deflection circuit as defined in claim wherein said first digital word is representative of the period of the horizontal deflection signal, and additionally comprising a digital period-to-frequency converter connected between said first phase-locked loop and said first input of said adder. 3. A horizontal-deflection circuit as defined in claims 1 or 2, additionally comprising a protection circuit coupled between the output of said digital sine-wave generator and the input of said frequency divider, said protection circuit providing a sine-wave signal of a desired frequency if the frequency of said sine-wave generator departs from a desired-value range. 4. A horizontal-deflection circuit as defined in claim 3, wherein said protection circuit is an analog phase-locked loop.

Description:

BACKGROUND OF THE INVENTION
The present invention relates to a digital horizontal-deflection circuit for generating an analog horizontal deflection signal driving the horizontal output stage of a digital television receiver clocked with a system clock. A digital horizontal-deflection circuit of this kind is described in a data book of Intermetall, "DIGIT 2000 VLSI Digital TV System," 1984/5, pages 112 to 114, which deal with the integrated circuit DPU 2500.
In the prior art arrangement, the phase variation which is necessary for the digital generation of the horizontal deflection signal and must be stepped in fractions of the period of the system clock is achieved essentially by the use of gate-delay stages or chains as are described, for example, in the European Patent Applications EP-A Nos. 0,059,802; 0,080,970; and 0,116,669, which essentially utilize the inherent delay of inverters. It turned out, however, that with these arrangements, it is not possible to completely control all operating conditions which may occur. SUMMARY OF THE INVENTION
It is, therefore, the object of the invention to modify and improve the digital horizontal-deflection circuit described in the above prior art in such a way that the gate-delay stages can be dispensed with. DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT The invention will now be explained in more detail with reference to the single FIGURE of the accompanying drawing, which is a block diagram of an embodiment of the invention. The block diagram shows that portion of a digital television receiver, i.e., of a television receiver in which the analog signal received via the antenna is processed digitally, which is of interest in connection with the invention. Thus, all subcircuits for digital-to-analog conversion, sync separation, chrominance-signal and luminance-signal processing or sound-signal processing have been omitted; the overall circuit concept of digital television receivers has been well known for some time.
The first digital phase-locked loop (PLL) p1 is supplied with the (digital) horizontal synchronizing signal hs, which was separated from the composite color signal, and the system clock st, and derives therefrom, in the manner described in the prior art, the first digital word d1, which is representative of the horizontal frequency, and the second digital word d2, which is representative of the desired phase position of the horizontal flyback signal fy. The signal fy comes from the receiver's horizontal output stage ps, which supplies the necessary sawtooth current to the deflection coil 1. The phase position of the flyback signal fy relative to the horizontal deflection signal ps is dependent on the switching properties of the horizontal output stage ps and is also influenced by the video signal applied to the picture tube.
By means of the second PLL p2, indicated in the FIGURE by the large rectangle bounded by a broken line, these dependences are compensated in the manner described in the prior art. The phase comparator pv generates the third digital word d3, which is representative of the phase deviation of the flyback signal fy from its desired position, and the second PLL p2 shifts the horizontal deflection signal ds in time so that the flyback signal fy takes up the desired phase position.
The first digital word d1 is fed to the first input of the adder ad, and the third digital word d3 is fed to the second input of this adder via the multiplier m, which serves as an amplifier. The second input of the multiplier m is fed with the signal k determining the gain of the second PLL p2, so that the transient response of the latter can be optimally adjusted by the manufacturer of the television receiver.
The output of the adder ad is fed to the control input of the digital sine-wave generator s, which may be designed as an accumulator followed by a sine looker table (ROM). If an n-bit word d4 is applied to its control input, this arrangement, which is known in principle, delivers a sine-wave of frequency (d4)fs/2 n , where fs is the frequency of the system clock st.
The output of the digital sine-wave generator sg is fed to the frequency divider ft, which provides the horizontal deflection signal ds, a square-wave signal as usual. The frequency divider ft thus not only divides the frequency of the signal delivered by the sine-wave generator sg, but also converts the sine-wave signal into the above-mentioned square-wave signal; this can be done in a suitable sine-to-square wave converter stage at the input of the frequency divider ft.
Two stages which can be added to the arrangement singly or in combination are indicated in the FIGURE by rectangles bounded by broken lines. The period-to-frequency converter fw between the output of the first PLL pl for the first digital word d1 and the corresponding input of the adder ad is necessary if the first digital word d1, generated by the first PLL p1, represents the period of the horizontal deflection signal ds (if this word represents the frequency of the horizontal deflection signal, the stage fw is not necessary).
Between the output of the digital sine-wave generator sg and the input of the frequency divider ft, the protection circuit sc may be inserted. It is preferably an analog phase-locked loop which provides a sine-wave signal of the desired frequency if the frequency of the sine-wave generator sg departs from a predetermined desired-value range. This may be to advantage during the start-up phase after the turning on of the television receiver or may serve to afford protection in the event of a failure of one or both of the PLL's p1, p2. In the FIGURE, the stripe-like connecting leads represent signal paths over which digital signals are transferred in parallel, i.e., on these buses, the individual (parallel) digital words follow one after the other at the pulse repetition rate of the system clock st. The fact that the individual stages of the second PLL p2--where necessary and appropriate--and the period-to-frequency converter fw are clocked with the system clock st, too, is indicated by the respective clock input lines.
The digital horizontal-deflection circuit in accordance with the invention is preferably realized using monolithic integrated circuit techniques, particularly MOS technology. It may form part of a larger integrated circuit but can also be implemented as a separate integrated circuit.

This circuit arrangement is designed for use in digital color-television receivers or the like and contains for each of the two digital color-difference signals a slope detector to which both a digital signal defining an amplitude threshold value and a digital signal defining a time threshold value are applied. At least one intermediate value occurring during an edge to be steepened is stored, and at the same time value of the steepened edge, it is "inserted" into the latter. This is done by means of memories switches, output registers, and a sequence controller.

What is claimed is: 1. A circuit arrangement for steepening color-signal transitions, comprising:
first and second circuit branches, said first branch receiving a first color difference digital signal from a first color difference channel and said second branch receiving a second color difference digital signal from a second color difference channel, each of said branches comprising:
a digital slope detector for generating a control signal at an output when the respective one of said first or second color difference digital signals has a predetermined relationship to predetermined amplitude and time thresholds;
a first delay element receiving and delaying said respective one color difference digital signal by a time equal to the delay of said digital slope detector;
at least one memory having its input connected to the output of said first delay element;
a switch having first and second inputs connected to the outputs of said delay element and said at least one memory, respectively; and
an output register having its input connected to the output of said switch;
and
a sequence controller coupled to the outputs of said digital slope detectors in said first and second circuit branches, and receiving a clock signal having a predetermined frequency relationship to a chrominance subcarrier frequency, and receiving a digital signal determining the hold time equal to the known system rise time of said first and second color difference channels, said sequence controller providing sequence control signals for controlling said at least one memory, said switch and said output register in both of said first and second circuit branches such that:
a color difference signal value occurring at an intermediate value of said hold time is read into said memory, said color difference signal value stored in said memory is read via said switch into said output rergister at the corresponding intermediate value of the steepened leading edge of said color-signal, the input of said output register being connected to the output of said delay element at all times except at said intermediate value of said steepened leading edge.
2. A circuit arrangement in accordance with claim 1, wherein each said slope detector comprises:
a first digital differentiator receiving the respective color difference digital signal;
a digital absolute value stage coupled to said first digital differentiator output;
a first digital comparator having a minuend input coupled to said digital absolute value stage output, a subtrahend input supplied with a digital signal corresponding to said amplitude threshold value, and an output;
a second digital differentiator having an input coupled to said comparator output;
a counter for counting pulses of said clock signal, said counter having an enable input coupled to said comparator output, and having a reset input coupled to the output of said second digital differentiator;
a fifth memory having its inputs coupled to the count outputs of said counter and an enable input coupled to said second digital differentiator output;
a second digital comparator having a minuend input coupled to the output of said fifth memory, a subtrahend input supplied with a digital signal corresponding to said time threshold value; and
gate means for combining the output of said comparator and the output of said second digital differentiator to provide said control signal when the output of said comparator and the output of said second digital differentiator are both active.
3. A circuit arrangement in accordance with claim 2,
wherein each of said first and second circuit branches further comprises a second memory having its input connected to said first delay element output, said switch having a third input coupled to said second memory output; and
wherein said sequence controller comprises:
a counter for counting pulses of said clock signal; and
a decoder for decoding the count output of said counter to provide said sequence control signals, said sequence control signals also controlling each said second memory,
said sequence controller operating such that color difference signal values occurring at the end of the first third of said hold time are written into said at least one memory, and color difference signal values occurring at the end of the second third of said hold time are written into said second memory; and
wherein:
in said first circuit branch the contents of said at least one memory and said second memory are written via said switch into said output register at the end of the first third and at the end of the second third, respectively, of said steepened leading edge;
in said second circuit branch the contents of said at least one memory and said second memory are written via said switch into said output register at the end of the first third and the second third, respectively, of said steepened leading edge; and
the input of the respective output register of each of said first and second circuit branches is connected to the output of the respective first delay element at all times except at the end of said first third and said second third or said steepened leading edge.
4. A circuit arrangement in accordance with claim 1,
wherein each of said first and second circuit branches further comprises a second memory having its input connected to said first delay element output, said switch having a third input coupled to said second memory output;
wherein said sequence controller comprises:
a counter for counting pulses of said clock signal; and
a decoder for decoding the count output of said counter to provide said sequence control signals, said sequence control signals also controlling each said second memory,
said sequence controller operating such that color difference signal values occurring at the end of the first third of said hold time are written into said at least one memory, and color difference signal values occurring at the end of the second third of said hold time are written into said second memory; and
wherein:
in said first circuit branch the contents of said at least one memory and said second memory are written via said switch into said output register at the end of the first third and at the end of said second third, respectively, of said steepened leading edge;
in said second circuit branch the contents of said at least one memory and said second memory are written via said switch into said output register at the end of the first third and the second third, respectively, of said steepened leading edge; and
the input of the respective output register of each of said first and second circuit branches is connected to the output of the respective first delay element at all times except at the end of said first third and said second third of said steepened leading edge.

Description:

BACKGROUND OF THE INVENTION
The invention pertains to a circuit for steepening color-signal transitions in color television receivers or the like.
A circuit arrangement of this kind includes a slope detector which, when a predetermined amplitude threshold value is exceeded, delivers a switching signal which causes a substitute signal to appear at the respective output of the two color-difference channels for the duration of the system rise time of said channels. One circuit arrangement of this kind, which provides a chroma transient improvement, is described in a publication by VALVO entitled "Technische Information 840228 (Feb. 28, 1984): Versteilerung von Farbsignalsprungen and Leuchtdichtesignal-Verzogerung mit der Schaltung TDA 4560".
The bandwidth of the color-difference channel is very small compared with the bandwidth of the luminance channel, namely only about 1/5 that of the luminance channel in the television standards now in use. This narrow bandwidth leads to blurred color transitions ("color edging") in case of sudden color-signal changes, e.g., at the edges of the usual color-bar test signal, because, compared with the associated luminance-signal transition, an approximately fivefold duration of the color-signal transition results from the narrow transmission bandwidth.
In the prior circuit arrangement, the relatively slowly rising color-signal edges are steepened by suitably delaying the color-difference signals and the luminance signal and steepening the edges of the color-difference signals at the end of the delay by suitable analog circuits. The color-difference signals and the luminance signal are present and processed in analog form as usual.
The problem to be solved by the invention is to modify the principle of the prior art analog circuits in such a way that it can be used in known color-television receivers with digital signal-processing circuitry (cf. "Electronics", Aug. 11, 1981, pages 97 to 103), with the slope detector responding not only to one criterion, namely a predeterminable amplitude threshold value as in the prior art arrangement, but to an additional criterion. SUMMARY OF THE INVENTION
In accordance with the invention a circuit arrangement provides a fully digital solution for chroma transient improvement. The circuit arrangement contains a slope detector, a memory, a switch-over switch and a timing control stage for the processing of each color difference signal. A time period threshold signal and an amplitude threshold signal are fed to the slope detector. If the amplitude threshold is exceeded and the time threshold is not being reached, the slope is improved.
This circuit arrangement is designed for use in digital color-television receivers or the like and contains for each of the two digital color-difference signals a slope detector to which both a digital signal defining an amplitude threshold value and a digital signal defining a time threshold value are applied. At least one intermediate value occurring during an edge to be steepened is stored, and at the same time value of the steepened edge, it is "inserted" into the latter. This is done by means of memories, switches, output registers, and a sequence controller. BRIEF DESCRIPTION OF THE DRAWING
The invention will be better understood from a reading of the following detailed description in conjunction with the drawing in which:
FIG. 1 is a block diagram of a first embodiment of the invention;
FIG. 2 is a block diagram of a second form of the arrangement of FIG. 1;
FIG. 3 is a block diagram of an embodiment of the slope detectors of FIGS. 1 and 2;
FIGS. 4a-c shows various waveforms to explain the basic operation of the invention; and
FIGS. 5a and 5b shows waveforms to explain the operation of the improved arrangement of FIG. 2. DETAILED DESCRIPTION In the block diagram of FIG. 1, the digital color-difference signals yr, yb are present in the baseband at the frequency of the clock signal f, which is four times the chrominance-subcarrier frequency, i.e., the individual data words appear one after the other at this frequency. If a subharmonic of the clock signal f, i.e., the chrominance-subcarrier frequency itself, for example, is chosen for the color-difference-signal demodulation as may be the case in known digital color-television receivers, these digital signals must be brought to the aforementioned repetition frequency of the clock signal f by digital interpolation.
In FIG. 1, there are two branches for the two color-difference signal yr and yb, respectively. They are of the same design, with the branch z1 assigned to the red-minus-luminance channel, and the branch z2 to the blue-minus-luminance channel. In the branch z1, the red-minus-luminance signal yr is applied to the inputs of the first delay element v1 and the first digital slope detector fs1. The output of the first delay element v1 is fed to the input of the first memory s1 and to one of the inputs of the first switch us1, whereas the output of the first memory s1 is connected to the other input of the first switch us1, whose output is coupled to the input of the first output register r1.
The second branch z2, to which the blue-minus-luminance signals yb are applied, is of the same design as the first branch z1 as far as the individual circuits and their interconnections are concerned, and contains the second digital slope detector fs2, the second delay element v2, the second memory s2, the second switch us2, and the second output register r2.
The output signals of the two slope detectors fs1, fs2 are applied, respectively, to the first and second inputs of the OR gate og, whose output is connected to the first input of the sequence controller ab. The second input of the latter is presented with the clock signal f, and the third input with the digital signal hz, by which the hold time equal to the system rise time of the color-difference channels can be preset. The outputs of the sequence controller ab are connected to the enable inputs en of the first and second memories s1, s2 and of the first and second output registers r1, r2 and to the control inputs of the two switches us1, us2.
The sequence controller ab controls these subcircuits as follows. A red-minus-luminance signal value yr1 and a blue-minus-luminance signal value yb1 occurring at an intermediate value of the hold time are read into the memories s1 and s2, respectively. This intermediate value of the hold time lies preferably in the middle of the hold time. Furthermore, the sequence controller causes the contents of the memories s1 and s2 to be transferred via the associated switches us1 and us2 into the associated output registers r1 and r2, respectively, at the corresponding intermediate value, preferably one-half, of the steepened leading edge, while at all times other than the instant of the intermediate value of the steepened leading edge, the inputs of the associated output registers are connected to the outputs of the delay elements v1 and v2, respectively. The block diagram of FIG. 2 shows an improved version of the arrangement of FIG. 1. The improvement is that the first and second memories s1 and s2 of FIG. 1 have been supplemented with the third and fourth memories s3 and s4, respectively, each of which is connected in parallel with the associated memory, and that the two switches us1 and us2 of FIG. 1 have been expanded into multiposition switches us1' and us2' each having one additional input connected to the output of the third memory s3 and the output of the fourth memory s4, respectively.
This improved portion of FIG. 2 concerns the sequence controller ab of FIG. 1. In FIG. 2, the latter consists of the counter c2, which counts the pulses of the clock signal s, the decoder dc, and the AND gate u2. The start input st of the counter c2 is connected to the output of the OR gate og, whereas the stop input sp is controlled by the decoder dc. The digital signal hz is fed to the decoder dc, cf. FIG. 1.
The counts of the counter c2 are decoded by reading the red- and blue-minus-luminance signal values occurring at the end of the first third of the hold time, i.e., the values yr1' and yb1', into the first memory s1 and the second memory s2, respectively, and the red- and blue-minus-luminance signal values occurring at the end of the second third of the hold time, i.e., the values yr2 and yb2, into the third memory s3 and the fourth memory s4, respectively. At the end of the first third and second third, respectively, of the steepened leading edge, the contents of the memories s1 and s3, respectively, are transferred through the switch us1' into the output register r1, and at the end of the first third and second third, respectively of that edge, the contents of the memories s2 and s4, respectively, are transferred through the switch us2' into the output register r2. The inputs of the two outputs registers are connected to the outputs of the first and second delay elements v1 and v2, respectively, except at the end of the first and second thirds, respectively, of the steepened leading edge.
The clock signal f is applied to one of the inputs of the AND gate u2, whose other input is connected to one of the outputs of the decoder dc, and whose output is coupled to the enable inputs en of the first and second output registers r1, r2. The block diagram of FIG. 3 shows a preferred embodiment of the circuit of the slope detectors fs1, fs2. The input for the color-difference signal yr, yb is followed by the series combination of the first digital differentiator d1, the digital absolute-value stage bb, and the minuend input m of the first digital comparator k1. The subtrahend input s of the latter is presented with the digital signal corresponding to the amplitude threshold value, the signal ta.
The absolute-value stage bb delivers digital values which are unsigned, i.e., which have no sign bit, for example.
Accordingly, the absolute-value stage bb contains a subcircuit which changes negative binary numbers in, e.g., one's or two's complement representation into the corresponding positive binary number, i.e., a recomplementer.
The term "comparator" as used herein means a digital circuit which compares the two digital signals appearing at the two inputs to determine which of the two signals is greater. Since, purely formally, such a comparison is closer to the arithmetic operation of subtraction than to that of addition although the concrete internal circuitry of such comparators is more similar to that of adders than to that of subtracters, the two inputs of the comparator are called "minuend input" and "subtrahend input" as in the case of a subtracter. The three logic output signals are "minuend greater than subtrahend", "subtrahend greater than minuend", and "minuend equal to subtrahend". Thus, in positive logic, the more positive logic level will appear at the minuend-greater-than-subtrahend output of a comparator if and as long as the minuend is greater than the subtrahend. If needed, the more negative logic level appearing at this output may serve to signal the "minuend-smaller-than-subtrahend" function, i.e., it is also possible to use negative logic.
In the slope detector of FIG. 3, the enable input eb of the first clock-pulse counter c1 and one of the inputs of the second digital differentiator d2 are connected to the minuend-greater-than-subtrahend output ms of the first comparator k1. The count outputs of the first counter c1 are coupled to the input of the fifth memory s5, which has its output connected to the minuend input m of the second digital comparator k2. The subtrahend input s of the latter is presented with a digital signal corresponding to the time threshold value, the signal tt.
The reset input re of the first counter c1, the enable input en of the fifth memory s5, and the first input of the first AND gate u1 are connected to the output of the second differentiator d2. The subtrahend-greater-than-minuend output sm of the second comparator k2 is connected to the second input of the second AND gate u2, whose output is fed to the OR gate of FIGS. 1 or 2. The subcircuits d1, bb, k1, d2, and, as mentioned above, c1 are clocked by the clock signal f. FIGS. 4a-c and 5a and b serve to illustrate the operation of the circuit arrangement in accordance with the invention. FIG. 4a shows the assumed shape of one of the two color-difference signals yr, yb; it should be noted that, in those figures, the representation commonly used for analog signals has been chosen for simplicity.
FIG. 4b shows the output signal of the absolute-value stage bb and the amplitude threshold value corresponding to the digital signal ta. Also shown is the time threshold value corresponding to the digital signal tt. FIG. 4c shows the shape of the assumed color-difference signal of FIG. 4a as it appears at the output of the output register r1, r2 of FIG. 1 or FIG. 2. A comparison between FIGS. 4a and 4c shows that the last edge on the right has been steepened since, during this edge, both the amplitude threshold value is exceeded and the time threshold value is not reached (cf. the use of the subtrahend-greater-than-minuend output sm of the second comparator k2), the steepening function becomes effective. The first comparator k1 provides a signal at the minuend-greater-than-subtrahend output ms as long as the output signal of the absolute-value stage bb is greater than the amplitude threshold value. During that time, the first counter c1 can count the clock pulses until it is reset by a signal derived by the second differentiator d2 from the trailing edge of the output signal of the first comparator k1. The previous count of the counter c1 is transferred into the fifth memory s5 and compared with the time threshold value by the second comparator k2. If the time threshold value is greater than the period measured by the counter c1, the above-mentioned function will be initiated.
FIGS. 5a and 5b serve to explain how the steepened edge is formed. Curve a of FIG. 5a shows a slowly rising edge used for the explanation. The distances between the points in curves a and b of FIG. 5a are to illustrate the period of the clock signal f. FIG. 5b shows the waveform at the enable inputs en of the output registers r1, r2. At the arrow shown on the left between curves a and b of FIG. 5a, the signal periodically applied to these inputs at the repetition rate of the clock signal f is stopped, so to speak, so that no signals are transferred to the output registers r1, r2 over several clock periods, but the signal read in at the "clocking" of the enable inputs en is retained in those registers. After the "clocking" of the enable inputs of the output registers r1, r2 has resumed at the beginning of the edge to be steepened, the signal values yr1', yb1' and yr2, yb2 read into the memories s1, s2 and s3, s4 at the end of the first third and the second third, respectively, of the slowly rising edge of curve a of FIG. 5a are transferred into the output registers r1, r2 at the end of the first third and the second third, respectively, of this edge. The arrow shown on the right between curves a and b of FIG. 5a is to indicate that, at the end of the slowly rising edge of curve a, the steepened edge of curve b has reached the desired signal value.
The period for which the "clocking" of the enable inputs en of the output registers r1, r2 is "interrupted" is equal to the duration of the digital signal hz fed to the sequence controller ab of FIG. 1 or to the decoder dc of FIG. 2.
The circuit arrangement in accordance with the invention can be readily implemented in monolithic integrated form. As it uses exclusively digital circuits, it is especially suited for integration using insulated-gate field-effect transistors, i.e., MOS technology.

SCHNEIDER DTV5535 DIGITAL PROFI CONCEPT 55 CHASSIS DTV1 VCU 2133 Video Codec UNITHigh-speed coder/decoder IC for analog-to-digital and di-gital-to-analog conversion of the video signal in digital TVreceivers based on the DIGIT 2000 concept. The VCU2133is a VLSI circuit in Cl technology, housed in a 40-pin Dilplastic package. One single silicon chip combines the fol-lowing functions and circuit details (Fig. 1):- two input video amplifiers- one A/D converter for the composite video signal- the noise inverter- one D/A converter for the luminance signal- two D/A converters for the color difference signals- one RGB matrix for converting the color difference sig-nals and the luminance signal into RGB signals- three RGB output amplifiers- programmable auxiliary circuits for blanking, brightnessadjustment and picture tube alignment- additional clamped RGB inputs for text and other analogRGB signals- programmable beam current limiting1. Functional DescriptionThe VCU 2133 Video Codec is intended for converting theanalog composite video signal from the video demodulatorinto a digital signal. The latter is further processed

digitallyin the VPU 2203 Video Processor and in the DPU2553 De-flection Processor. After processing in the VPU2203 (colordemodulation, PAL compensation, etc.), the VPU‘s digitaloutput signals (luminance and color difference) are recon-verted into analog signals in the VCU 2133. From these an-alog signals are derived the RGB signals by means of theRGB matrix, and, after amplification in the integrated RGBamplifiers, the RGB signals drive the RGB output amplifiersof the color T\/ set.For TV receivers using the NTSC standard the VPU2203may be replaced by the CVPU 2233 Comb Filter Video Pro-cessor which is pin-compatible with the VPU 2203, but of-fers better video performance. In the case of SECAM, theSPU 2220 SECAM Chroma Processor must be connectedin parallel to the VPU 2203 for chroma processing, whilethe luma processing remains inthe VPU 2203.In a more sophisticated CTV receiver according to the Dl-GIT 2000 concept, after the VPU Video Processor may beplaced the DTI 2223 Digital Transient Improvement Proces-sor which serves for sharpening color transients on thescreen. The output signals of the DTI are fed to the VCU’sluma and chroma inputs. To achieve the desired transientimprovement, the R-Y and B-Y D/A converters of the VCUmust be stopped for a certain time which is done by thehold pulse supplied by the DTI and fed to the Reset pin 23of the VCU. The pulse detector following this pin seperatesthe (capacitively-coupled) hold pulse from the reset signal.In addition, the VCU 2133 carries out the functions:- brightness adjustment- automatic CRT spot-cutoff control (black level)- white balance control and beam current limitingFurther, the VCU 2133 offers direct inputs for text or otheranalog RGB signals including adjustment of brightness andcontrast for these signals.The RGB matrix and RGB amplifier circuits integrated inthe VCU 2133 are analog. The CRT spot-cutoff control iscarried out via the RGB amplifiers’ bias, and the white bal-ance control is accomplished by varying the gain of theseamplifiers. The VCU 2133 is clocked by a 17.7 or 14.3 MHzclock signal supplied by the MCU 2632 Clock Generator IC.1.1. The A/D Converter with Input Amplifiers and BitEnlargementThe video signal is input to the VCU 2133 via pins 35 and 37which are intended for normal TV video signal (pin 35) andfor VCR or SCART video signal (pin 37) respectively. Thevideo amplifier whose action is required, is activated by theCCU 2030, CCU 2050 or CCU 2070 via the IM bus by soft-ware. The amplification of both video amplifiers is doubledduring the undelayed horizontal blanking pulse (at pin 36)in order to obtain a higher digital resolution of the colorsynchronization signal (burst). At D 2-MAC reception, thedoubled gain is switched off by means of bit p = 1 (Fig. 8).

The A/D converter is of the flash type, a circuit of 2" com-parators connected in parallel. This means that the numberof comparators must be doubled if one additional bit isneeded. Thus it is important to have as few bits as possi-ble. For a slowly varying video signal, 8 bits are required.

lnorder to achieve an 8-bit picture resolution using a 7-bitconverter, a trick is used: during every other line the refer-ence voltage of the A/D converter is changed by anamount corresponding to one half of the least significantbit. ln this procedure, a grey value located between two 7-bit steps is converted to the next lower value during oneline and to the next higher value during the next line. Thetwo grey values on the screen are averaged by the viewer’seye, thus producing the impression of grey values with8-bit resolution. Synchronously to the changing referencevoltage of the A/D converter, to the output signal of the YD/A converter is added a half-bit step every second line.The bit enlargement just described must be switched off inthe case of using the D2-MAC standard (q = 1 and r = 1in Fig. 8). ln the case of using the comb filter CVPU insteadof the VPU, the half-bit adding in the Y D/A converter mustbe switched off (r = 1 in Fig. 8).The A/D converter’s sampling frequency is 17.7 MHZ forPAL and 14.3 MHz for NTSC, the clock being supplied bythe MCU 2632 Clock Generator IC which is common to allcircuits for the digital T\/ system. The converter’s resolu-tion is 1/2 LSB of 8 bits. Its output signal is Gray-coded toeliminate spikes and glitches resulting from different com-parator speeds or from the coder itself. The output is fed tothe VPU 2203 and to the DPU 2553 in parallel form.1.2. The Noise InverterThe digitized composite video signal passes the noise in-verter circuit before it is put out to the VPU 2203 and to theDPU 2553. The noise inverter serves for suppressing brightspots on the screen which can be generated by noiseVCU 2133pulses, p. ex. produced by ignition sparks of cars etc. Thefunction of the noise inverter can be seen in Fig. 2. Themaximum white level corresponds with step 126 of the A/Dconverter’s output signal (that means a voltage of 7 V atpin 35). lf, due to an unwanted pulse on the compositevideo signal, the voltage reaches 7.5 V (what means step127 in digital) or more, the signal level is reduced by suchan amount, that a medium grey is obtained on the screen(about 40 lFiE). The noise inverter circuit can be switchedoff by software (address 16 in the VPU 2203, see there).1.3. The Luminance D/A Converter (Y)After having been processed in the VPU 2203 (color de-modulation, PAL compensation, etc.), the different parts ofthe digitized video signal are fed back to the VCU 2133 forfurther processing to drive the RGB output amplifiers. Theluminance signal (Y) is routed from the VPU’s contrast mul-tiplier to the Y D/A converter in the VCU 2133 in the form ofa parallel 8-bit signal with a resolution of 1/2 LSB of 9

The luminance D/A converter is designed as an R-2R lad-der network. lt is clocked with the 17.7 or the 14.3 MHzclock signal applied to pin 22. The cutoff frequency of theluminance signal is determined by the clock frequency.1.4. The D/A Converters for the Color Difference SignalsR-Y and B-Yln order to save output pins at the VPU 2203 and input pinsat the VCU 2133 as well as connection lines, the two digitalcolor difference signals R-Y and B-Y are transferred in timemultiplex operation. This is possible because these signals’bandwidth is only 1 MHZ and the clock is a 17.7 or 14.3MHz signal.The two 8-bit D/A converters R-Y and B-Y are also built asR-2R ladder networks. They are clocked with ‘A clock fre-quency, but the clock for the multiplex data transfer is 17.7or 14.3 MHz. Four times 4 bits are transferred sequentially,giving a total of 16 bits. A sync signal coordinates the

multi-plex operations in both the VCU 2133 and the VPU 2203.Thus, only four lines are needed for 16 bits. Fig. 4 showsthe timing diagram of the data transfer described.ln a CTV receiver with digital transient improvement (DTI2223), the R-Y and B-Y D/A converters are stopped by thehold pulse supplied by the DTI, and their output signal iskept constant for the duration of the hold pulse. Thereafter,the output signal jumps to the new value, as described inthe DTl’s data sheet.Fig. 4:Timing diagram of the multiplex data transfer of the chromachannel between VPU 2203, VCU 2133 and SPU 2220a) main clock signal QSMb) valid data out of the VCU 2133’s video A/D converter.AIAD is the delay time of this converter, about 40 ns.c) valid data out of the VPU 2203.d) MUX data transfer of the chroma signals from VPU 2203to VCU 2133, upper line: sync pulse from pin 27 VPU topin 21 VCU during sync time in vertical blanking time,see Fig. 8; lower line: valid data from pins 27 to 30(VPU) to pins 18 to 21 (VCU)1.5. The RGB Matrix and the RGB Output Amplifiersln the RGB matrix, the signals Y, R-Y and B-Y are dema-trixed, the reduction coefficients of 0.88 and 0.49 being tak-en into account. In addition, the matrix is supplied with asignal produced by an 8-bit D/A converter for setting thebrightness of the picture. The brightness adjustment rangecorresponds to 1/2 of the luminance signal range (see Fig.3). It can be covered in 255 steps. The brightness is set bycommands fed from the CCU 2030, CCU 2050 or CCU 2070Central Control Unit to the VPU 2203 via the IM bus.There are available four different matrices: standard PAL,matrix 2, 3 and 4, the latter for foreign markets. 'The re-quired matrix must be mask-programmed during produc-tion. The matrices are shown in Table 1, based on the for-mulas:R = r1~(R-Y)+ l'2~(B-Y) +YG = Q1-(Ft-Y)+ Q2 - (B-Y) +YB = b1-(Ft-Y)+ bg - (B-Y) +YThe three RGB output amplifiers are impedance convertershaving a low output impedance, an output voltage swing of6 V (p-p), thereof 3 V for the video part and 3 V for bright-ness and dark signal. The output current is 4 mA. Fig. 5shows the recommended video output stage configuration.

For the purpose of white-balance control, the amplificationfactor of each output amplifier can be varied stepwise in127 steps (7 bits) by a factor of 1 to 2. Further, the CRTspot-cutoff control is accomplished via these amplifiers’ bi-as by adding the output signal of an 8-bit D/A converter tothe intelligence signal. The amplitude of the output signalcorresponds to one half of the luminance range. The eightbits make it possible to adjust the dark voltage in 0.5 %steps. By means of this circuit, the factory-set values forthe dark currents can be maintained and aging of the pic-ture tube compensated.1.6. The Beam Current and Peak Beam Current LimiterThe principle of this circuitry may be explained by means ofFig. 6. Both facilities are carried out via pin 34 of the VCU2133. For beam current limiting and peak beam current li-miting, contrast and brightness are reduced by reducingthe reference voltages for the D/A converters Y, Ft-Y andB-Y. At a voltage of more than +4 V at pin 34, contrast andbrightness are not affected. In the range of +4 V to +3 V,the contrast is continuously reduced. At +3 V, the originalcontrast is reduced to a programmable level, which is setby the bits of address 16 of the VPU as shown in Table 2. Afurther decrease of the voltage merely reduces brightness,the contrast remains unchanged. At 2 V, the brightness isreduced to zero. At voltages lower than 2 V, the outputgoes to ultra black. This is provided for security purposes.The beam current limiting is sensed at the ground end ofthe EHT circuit, where the average value of the beam cur-rent produces a certain voltage drop across a resistor in-serted between EHT circuit and ground. The peak beamcurrent limiting can be provided additionally to avoid“blooming” of white spots or letters on the screen. Forthis, a fast peak current limitation is needed which issensed by three sensing transistors inserted between theRGB amplifiers and the cathodes of the picture tube. Oneof these three transistors is shown in Fig. 6. The sum of thepicture tube’s three cathode currents produces a voltagedrop across resistor R1. If this voltage exceeds that gen-erated by the divider R2, B3 plus the base emitter voltageof T2, this transistor will be turned on and the voltage at

pin34 of the VCU 2133 sharply reduced. Time constants forboth beam current limiting and peak beam current limitingcan be set by the capacitors C1 and C2.1.7. The Blanking CircuitThe blanking circuit coordinates blanking during verticaland horizontal flyback. During the latter, the VCU 2133'soutput amplifiers are switched to “ultra black”. Suchswitching is different during vertical flyback, however, be-cause at this time the measurements for picture tube align-ment are Carried out. During vertical flyback, only the ca-thode to be measured is switched to “black” during mea-suring time, the other two are at ultra black so that only thedark current of one cathode is measured at the same time.For measuring the leakage current, all three cathodes areswitched to ultra black.The sequence described is controlled by three code bitscontained in a train of 72 bits which is transferred from theVPU 2203 to the VCU 2133 during each vertical blanking in-terval. This transfer starts with the vertical blanking pulse.During the transfer all three cathodes of the picture tubeare biased to ultra black. In the same manner, the white-balance control is done.The blanking circuit is controlled by two pulse combina-tions supplied by the DPU 2553 Deflection Processor(“sandcastle pulses"). Pin 39 of the VCU 2133 receives thecombined vertical blanking and delayed horizontal blanking

pulse from pin 22 of the DPU (Fig. 7 b), and pin 36 of theVCU gets the combined undelayed horizontal blanking andcolor key pulse from pin 19 of the DPU (Fig. 7 a). The twooutputs of the DPU are tristate-controlled, supplying theoutput levels max. 0.4 V (low), min. 4.0 V (high), or high-im-pedance, whereby the signal level in the high-impedancemode is determined by the VCU’s input configuration, avoltage divider of 3.6 KS! and 5 KQ between the +5 V sup-ply and ground, to 2_8 V. The VCU’s input amplifier has twothresholds of 2.0 V and 3.4 V for detecting the three levelsof the combined pulses. ln this way, two times two pulsesare transferred via only two lines.1.8. The Circuitry for Picture Tube AlignmentDuring vertical flyback, a number of measurements are tak-en and data is exchanged between the VCU 2133, the VPU2203 and the CCU 2030 or CCU 2050. These measure-ments deal with picture tube alignment, as white level anddark current adjustment, and with the photo current sup-plied by a photo resistor (Fig. 5) which serves for adaptingFig. 8:Data sequence during the transfer of test results from theVPU 2203 to the VCU 2133. Nine Bytes are transferred, ineach case the LSB first. These 9 Bytes, 8 bits each, coin-cide with the 72 pulses of 4.4 MHz that are transferred dur-ing vertical flyback from pin 27 of the VPU 2203 to pin 21 ofthe VCU 2133 (see Fig. 9).l and mi beam current limiter rangel<: noise inverter on/offn: video input switching bitS: SECAM chroma sync bit; S = 1 means that the chromademultiplexer is synchronized every line. The switch-overtime from C0 to demux counter begins with the end of theundelayed horizontal blanking pulse and remains valid for atime of 12 Q M clock periods.6the contrast of the picture to the light in the room wherethe TV set is operated. The circuitry for transferring the

pic-ture tube alignment data, the sensed beam currents andthe photo current is clocked in compliance with the VPU2203 by the vertical blanking pulse and the color key pulse.To carry out the measurements, a quadruple cycle is pro-vided (see Table 3). The timing of the data transfer duringthe vertical flyback is shown in Fig. 9, and Fig. 8 shows thedata sequence during that data transfer.Ft, G, B: code bitsp=1; no doubled gain in the input amplifier during horizon-tal blanking (see section 1.1.)q=1: no changing of the A/D converter’s reference vol-tage during every other line (see section 1.1.)r=1: when operating with the DMA D2-MAC decoder orthe CVPU comb filter video processor, the adding ofa step of ‘/2 LSB to the output signal of the Y D/Aconverter is switched off (see section 1.1.).s=1; the blankirig pulse in the analog video output signalat pins 26 to 28 is switched off, as is required instand-alone applications.

1.9. The Additional RGB InputsThe three additional analog RGB inputs are provided forinputting text or other analog RGB signals. They are con-nected to fast voltage-to-current converters whose outputcurrent can be altered in 64 steps (6 bits) for contrast set-ting between 100 % and 30 %. The three inputs areclamped to a DC black level which corresponds to the levelof 31 steps in the luminance channel, by means of the colorkey pulse. So, the same brightness level is achieved fornormal and for external RGB signals. The output currentsofthe converters are then fed to the three RGB output am-plifiers. Switchover to the external video signal is also

fast.1.10. The Reset Circuit and Pulse DetectorThe reset pulse produced by the external reset RC networkin common for the whole DIGIT 2000 system, switches theRGB outputs to ultra black during the power-on routine ofthe TV set. At other times, high level must be applied to thereset input pin 23.There is an additional facility with pin 23 which is used onlyin conjunction with the DTl 2223 Digital Transient Improve-ment Processor. The hold pulse produced by the latterwhich serves for stopping the R-Y and B-Y D/A converters,is also fed to pin 23, capacitively-coupled. The pulse detec-tor responds on positive pulses which exceed the 5 V sup-ply by about 1 V. The two DACs are stopped as long as thehold pulse lasts, and supply a constant output signal of theamplitude at the begin of the hold pulse.

5. Description of the Connections and the SignalsPins 1, 9, and 25 - Supply Voltage, +5 VThe supply voltage is +5 V. Pins 1 and 25 supply the ana-log part and must be filtered separately.Pins 2 to 8 - Outputs V0 to V6Via these pins the VCU 2133 supplies the digitized videosignal in a parallel 7-bit Gray code to the VPU 2203 and theDPU 2553. The output configuration is shown in Fig. 16.Pins 10 to 17 - Inputs L7 to L0Fig. 17 shows these inputs’ configuration. Via these pins,the VCU 2133 receives the digital luminance signal from theVPU 2203 in a paraliel 8-bit code.Pins 18 to 21 - Inputs C0 to C3Via these inputs, whose circuitry and data correspond tothose of pins 10 to 17, the VCU 2133 is fed with the digi-tized color difference signals R-Y and B-Y and with thecontrol and alignment signals described in section 1.8., inmultiplex operation. Pin 21 is additionally used for the

multi-plex sync signal.Pin 22 - QSM Main Clock InputVia this pin, whose circuitry is shown in Fig. 18, the VCU2133 is supplied with the clock signal QSM produced by theMCU 2600 or MCU 2632 Clock Generator IC. The clock fre-quency is 17.7 MHz for PAL and SECAM and 14.3 MHz forNTSC. The clock signal must be DC-coupled.Pin 23 - Reset and Hold Pulse Input (Fig. 19)Via this pin, the VCU 2133 is supplied with the reset andhold signals which are supplied by pin 21 of the DTI 2223Digital Transient Improvement Processor for stopping theR-Y and B-Y D/A converters, and for Reset.Pins 24 and 29 - Analog Ground, 0These pins serve as ground connections for the supply andfor the analog signals (GND pin 24 for RGB).Pins 26 to 28 - RGB OutputsThese three analog outputs deliver an analog signal suit-able for driving the RGB output transistors. Their diagramis shown in Fig. 20. The output voltage swing is 6 V total,3 V for the black-to-white signal and 3 V for adjustingthe brightness and the black level.Pins 30 to 32 - Additional Analog Inputs R, G and BFig. 21 shows the configuration of these inputs. They serveto feed analog RGB signals, for example for Teletext or si-milar applications, and they are clamped during the colorkey pulse. At a 1 V input, full brightness is reached. Thebandwidth extends from 0 to 8 MHz.Pin 33 - Fast Switching InputThis input is connected as shown in Fig. 22. It ser\/es forfast switchover of the video channel between an internally-produced video signal and an externally-applied video sig-nal via pins 30 to 32. With 0 V at pin 33, the RGB outputswill supply the internal video signal, and at a 1 V input

level,the RGB outputs are switched to the external video signal.Bandwidth is 0 to 4 MHz, and input impedance 1 KQ mini-mum.Pin 34 - Beam Current Limiter InputThe diagram of pin 34 is shown in Fig. 25. The input voltagemay be between +5 V and 0 V. The input impedance is 100kQ. The function of pin 34 is described in section 1.6.Pin 35 - Composite Video Signal Input 1To fully drive the video A/D converter the following ampli-tudes are required at pin 35: +5 V = sync pulse top level,all bits low; +7 V = peak white, all bits high. Fig. 24 showsthe configuration of pin 35.Pin 36 - Undelayed Horizontal Blanking and Color KeyPulse InputThe circuitry of this pin is shown in Fig. 23. Pin 36 receivesthe combined undelayed horizontal blanking and color keypulse which are “sandcastled” and are supplied by pin 19of the DPU 2553 Deflection Processor. During the undelay-ed horizontal blanking pulse, the input amplifiers’ gain isdoubled, and the bit enlargement circuit is also switchedby this pulse, and the counter for the data transmissiongap started. The color key pulse is used for clamping theRGB inputs pins 30 to 32.Pin 37 - Composite Video Signal Input 2This pin has the same function and properties as pin 35,except the gain of the input amplifier which is twice thegain as that of the amplifier at pin 35. This means an inputvoltage range of +5 V to +6 V.Pin 38 - Supply Voltage, +12 V »The 12 V supply is needed for certain circuit parts to obtainthe required input or output voltage range, as the video in-put and the RGB outputs (see Figs. 20 and 24).Pin 39 - Vertical Blanking and Delayed Horizontal BlankingInputThis pin receives the combined vertical blanking and delay-ed horizontal blanking. pulse from pin 22 of the DPU 2553Deflection Processor. Both pulses are “sandcastled” sothat only one connection is needed for the transfer of twopulses. These two pulses are separated in the input circui-try of the VCU 2133, and are used for blanking the pictureduring vertical and horizontal flyback. Fig. 23 shows the cir-cuitry of pin 39.Pin 40 - Digital Ground, OThis pin is used as GND connection in conjunction with thepins 2 to 8 and 10 to 21 which carry digital signals.

1. IntroductionThese programmable VLSI circuits in n-channel mOStechnology carry out the deflection functions in digitalcolorTV receivers based onthe DiGiT 2000 system andare also suitable for text and D2~mAC application. Thethree types are basically identical, but are modified ac-cording to the intended application:

The functional diagram of the DPU is shovvn in Fig. 3-1.3.2. The Video Clamping Circuit and the Sync PulseSeparation Circuit

The digitized composite video signal delivered as a 7»bitparallel signal by the VCU 2133, VCU 2134 or VCU 2136Video Codec is first noise-filtered by a 1 mHz digital lovv-pass filter and, to improve the noise immunity oftheclamping circuit, is additionally filtered by a 0.2 mHz low-pass filter before being routed to the minimum and backporch level detectors (Fig. 3-3).The DPU has tvvo different clamping outputs, no. 1 andNo. 2, one of vvhich supplies the required clampingpulses to the video input of the VCU as shovvn in Fig.3-1. The following values forthe clamping circuit applyfor Video Amp. l. since the gain of Video Amp. ll istwiceth at of Video Amp l, all clamping and signal levels of Vid-eo Amp ll are halt those of Video Amp l referred to +5 V.Afterthe TV set is switched on,thevideo clamping circuitfirst of all ensures by means of horizontal-frequencycurrent pulses from the clamping output of the DPU tothe coupling capacitor of the analog composite videosignal, that the video signal atthe VCU’s input is optimal-ly biased for the operation range of the A/D converter of5 to 7 V. For this, the sync top level is digitally measuredand set to a constant level of 5.125 V by these currentpulses. The horizontal and vertical sync pulses are novvseparated by a fixed separation level of 5.250 V so thatthe horizontal synchronization can lock to the correctphase (see section 3.3. and Figs. 3-2 and 3-3).vvith the color key pulse which is now present in syn-chronism with the composite video signal, the videoclamping circuit measures the DC voltage level of theporch and by means of the pulses from pin 21 (or pin4),sets the DC level ofthe porch at a constant 5.5 V (5.25 Vfor Video Amp ll). This level is also the reference blackto Video Processorffeletext Processor, D2-MAC Processor tc.

level for the PVPU 2204 or CvPU 2270 Video Proces-sors.When horizontal synchronization is achieved, the slicelevel for the sync pulses is set to 50 % of the sync pulseamplitude by averaging sync top and black level. Thisensures optimum pulse separation, even with smallsync pulse amplitudes (see application notes, section4).

3.3. Horizontal SynchronizationTwo operating modes are provided for in horizontal syn-chronization. The choice of mode depends on whetheror not the Tv station is transmitting a standard PAL orNTSC signal, in which there is a fixed ratio between colorsubcarrier frequency and horizontal frequency. ln thefirst case we speak of “color-locked” operation and inthe second case of “non-color-locked” operation (e.g.black-and-white programs). Switching between thetwomodes is performed automatically by the standard sig-nal detector.

3.3.1. Non-Color-Locked Operationln the non»locked mode,which is needed in the situationwhere there is no standard fixed ratio between the colorsubcarrier frequency and the horizontal frequency ofthetransmitter, the horizontal frequency is produced by subdemding the clock frequency (1 7.7 mHz for PAL and SECAM, 14.3mHz for NTSC) in the programmable fre-quency dmder (Fig. 3-4) until the correct horizontalfrequency is obtained. The correct adjustment of fre-quency and phase is ensured by phase comparator l.This determines the frequency and phase deviation bymeans of a digital phase comparison between the sepa-rated horizontal sync pulses and the output signal of theprogrammable dmder and corrects the dmder accordingly. Foroptimum adjustment of phase iitter, capturebehavior and transient response of the horizontal PLLcircuit, the measured phase deviation is filtered in a digi-lowpass filter (PLL phase filter). ln the case of non-OZMH synchronized horizontal PLL, this filter is set towideband PLL response with a pull-in range of 1800 Hz. if the- sync sync PLL circuit is locked, the PLL filter isautomatically switched to narrow-band response by an internalsynchronism detector in order to limit the phase jitter to aminimum, even in the case of weak and noisy signals.

The various key and gating pulses such as the color keypulse (tKe(,), the normal-scan (1 H) and double-scan(2H) horizontal blanking pulse (tAZ(/) and the 1 H hori-zontal undelayed gating pulse (t/(Z) are derived from theoutput signals ofthe programmable dmder and an addi-tional counter forthe2H signals and the 1 H and 2H skewdata output. These pulses retain a fixed phase positionwith respect to the 1 H inputvideo signal andthe double-scan output video signal from the CvPU 2270 Video Pro-cessorForthe purpose of equalizing phase changes in the hori-zontal output stage due to switching response toler-ances or video influence, a second phase control loopis used which generates the horizontal output pulse atpin 31 to drivethe horizontal output stage. ln phase com-parator li (Fig. 3~4), the phase difference between theoutput signal of the programmable dmder and the lead-ing edge (or the center) of the horizontal flyback pulse(pin 23) is measured by means of a balanced gate delayline. The deviation from the desired phase difference isused as an input to an adder. ln this, the information onthe horizontal frequency derived from phase com-parator l is added to the phase deviation originating formphase comparator ll. The result of this addition controlsa digital on-chip sinewave generator (about 1 mHz)which acts as a phase shifter with a phase resolution of1/128 of one main clock period m_By means of control loop ll the horizontal output pulse(pin 31) is shifted such that the horizontal flyback pulse(pin 23) acquiresthe desired phase position with respectto the output signal of the programmable dmder which,in turn, due to phase comparator l, retains a fixed phaseposition with respect to the video signal. The horizontaloutput pulse itself is generated by dmding the frequencyofthe 1 mHz sinewave oscillator by a fixed ratio of 64 inthe case of norm al scan and of 32 in the case of double-scan operation.

3.3.2. Color-Locked OperationWhen in the color~locked operating mode, after thephase position has been set in the non-color-lockedmode, the programmable dmder is set to the standarddmsion ratio (1135:1 for PAL, 91O:1 for NTSC) andphase comparator is disconnected so that interferingpulses and noise cannot influence the horizontal deflec-tion. Because phase comparator ll is still connected,phase errors ofthe horizontal output stage are also cor-rected in the color»locKed operating mode. The stan-dard signal detector is so designed that it only switchesto color-locked operation when the ratio between colorsubcarrier frequency and horizontal frequency deviatesno more than 1O'7 from the standard dmsion ratio. Toascertain this requires about 8 s (NTSC). Switching offcolor-locked operation takes place automatically, in the_ case of a change of program for example, within approx-imately 67 ms (e.g. two NTSC fields, 60 Hz).

3.3.3. Skew Data Output and Field Number Informa-tionwith non-standard input signals, the TPU 2735 or TPU2740 Teletext Processor produce a phase error vvith re-spect to the deflection phase.The DPU generates a digital data stream (skevv data,pin 7 ofthe DPU), which informs the PSP and TPU onthe amount of phase delay (given in 2.2 ns increments)used in the DPU for the 1H and 2h output pulse com-pared With the Fm main clock signal of 17.7 mHz (PALor SECAm) or 14.3 mhz (NTSC), see also Figs. 3-6 to3-8. The skew data is used by the PSP and by the TPUto adjust the double-scan video signal to the 1 H and 2Hphase of the horizontal deflection to correct these phaseerrors.For the vmC processor the skew data contains three additional

bits for information about frame number, 1 Vsync and 2 V sync start.

3.3.4. Synchronism Detector for PLL and MutingSignalTo evaluate locking ofthe horizontal PLL and conditionof the signal, the DPU’s HSP high-speed processor(Fig. 3~1) receives two items of information from the hor-izontal PLL circuit (see Fig. 3-11).a) the overall pulsevvidth of the separated sync pulsesduring a 6.7 us phase window centered to the horizontalsync pulse (value A in Fig. 3-11).b) the overall pulsevvidth of the separated sync pulseduring one horizontal line but outside the phase window(value B in Fig. 3-11).Based on a) and b) and using the selectable coefficientsKS1 and KS2 and a digital lovi/pass filter, the HSP pro-cessor evaluates an 8-bit item of information “SD” (seeFig. 3-12). By means of a comparator and a selectablelevel SLP, the switching threshold for the PLL signal“UN” is generated. UN indicates Whether the PLL is inthe synchronous or in the asynchronous state.To produce a muting signal in the CCU, the data SD canbe read by the CCU. The range ot SD extends from O(asynchronous) to +127 (synchronous). Typical valuestorthe comparator levels and their hysteresis B1 = 30/20and for muting 40/30 (see also HSP Bam address Table5-6).

DPU 2553, DPU 2554

3.4. Start Oscillator and Protection CircuitTo protect the horizontal output stage of the TV set dur-ing changing the standard and for using the DPU as alow power start oscillator, an additional oscillator is pro-vided on-chip (Fig. 3-4), with the output connected topin 31. This oscillator is controlled by a 4 mHz signalin-dependent trom the Fm main clock produced by theMCU 2600 or mCU 2632 Clock Generator IC and is pow-ered by a separate supply connected to pin 35. Thefunc-tion ofthis circuitry depends on the external standard se-lection input pin 33 and on the start oscillator select inputpin 36, as described in Table 3-3. Using the protectioncircuit as a start oscillator, the following operation modesare available (see Table 3-3).With pin 33 open-circuit, pin 36 at high potential (con-nected to pin 35) and a 4 mHz clock applied to pin 34,the protection circuit acts as a start oscillator. This pro-duces a constant-frequency horizontal output pulse of15.5 kHz in the case of DPU 2553, and of 31 khz in thecase of DPU 2554 while the Beset input pin 5 is at lowpotential. The pulsewidth is 30 us with DPU 2553, and16 us with DPU 2554. main clock at pin 2 or main powersupplies at pins 8, 32 and 40 are not required for this startoscillator After the main power supply is stabilized andthe main clock generator has started, the reset input pin5 must be switched to the high state. As long as the startvalues from the CCU are invalid, the start oscillator willcontinuously supply the output pulses of constant fre-quency to pin 31 _ By means of the start values given bythe CCU via the lm bus, the register FL must be set tozero to enable the stan oscillator to be triggered by thehorizontal PLL circuit. After that, the output frequencyand phase are controlled by the horizontal PLL only.It the external standard selection input pin 33 is con-nected to ground or to +5 V, the start oscillator isswitched off as soon as it ls in phase with PLL circuit. Pin33to ground selects PAL or SECAm standard (17.7 mHzmain clock), and pin 33 to +5 V selects NTSC standard(14.3 MHz main clock). After the main power supplies topins 8, 32 and 40 are stabilized, the start oscillator canbe used as a separate horizontal oscillator with a con-stant frequency of 15.525 khz. For this option, pin 33must be unconnected. By means ofthe lm bus registerSC the start oscillator can be switched on (SC = 0) or oft(SC = 1). Setting SC =1 is recommended.By means of pin 29 (horizontal output polarity selectin-put and start oscillator pulsewidth select input), the out-put pulsewidth and polarity ofthe start oscillator and pro-tection circuit can be hardware-selected. Pin 29 at lowpotential gives 30 us for DPU 2553 and 16 us for DPU2554,with positive output pulses. Pin 29 at high potentialgives 36 us for DPU 2553 and 18 its for DPU 2554, withnegative output pulses. Both apply forthetime period inwhich no start values are valid from the CCU. If pin 29is intended to be in the high state, it must be connectedto pin 35 (standby power). Pin 29 must be connected toground or to +5 V in both cases.Table 3-3: Operation modes ofthe start oscillator andprotection circuit

Pin 19 supplies a combination ofthe color key pulse andthe undelayed horizontal blanking pulse in the form of athree-level pulse as shown in Fig. 3-13. The high level(4 V min.) and the low level (0.4 V max.) are controlledby the DPU. During the low time of the undelayed hori-zontal blanking pulse, pin 19 of the DPU i sin the high--impedance mode and the output level at pin 19 is set to2.8 V by the VCU.At pin 22, the delayed horizontal blanking pulse in com-bination with the vertical blanking pulse is available asathree-level pulse as shown in Fig. 3-13. Output pin 22is in high-impedance mode during the delayed horizon-tal blanking pulse.ln double-scan operation mode (DPU 2554), pin 22 sup-plies the double-scan (2H) horizontal blanking pulse in-stead ofthe 1H blanking pulse (DPU 2553). ln text dis-play mode with increased deflection frequencies (seesection 1.), pin 22 ofthe respective DPU (DPU 2553, asdefined by register ZN) delivers the horizontal blankingpulse with 18.7 kHz and the vertical blanking pulse with60 Hz according to the display. At pin 24 the undelayedhorizontal blanking pulse is output.normally,pin3suppliesthe samevertical blanking pulseas pin 22. However, with“DVS” = 1, pin 3 will be in thesingle-scan mode also with double-scan operation ofthe system. The pulsewidth of the single-scan verticalblanking pulse at pin 3 will be the same as.that of thedouble-scan vertical blanking pulse at pin 22. The out-put pulse of pin 3 is only valid if the COU register “VBE”is set to 1 . The default value is set to 0 (high-impedancestate of pin 3).

Fig. 3-13: Shape of the output pulses at pins 19 and 22*) The output level is externally defined3.6. Output for Switching the Horizontal PowerStage Between 15.6 kHz (PAL/NTSC) and 18 kHz(Text Display)This output (pin 37) is designed as a tristate output. Highlevels (4 V mln.) and low levels (0.4 V max.) are con-trolled bythe DPU. During high-impedance state an ex-ternal resistor network defines the output level,For changing the horizontal frequency from 15 kHz to18 kHz, the following sequence of output levels isderived at pin 37 (see Fig. 3-14).After register ZN is set from ZN = 2 (15 kHz) to ZN = 0(18 kHz) by the CCU, pin 37 is switched from High levelto high-impedance state synchronously with the fre-quency change at pin 31. Following a delay of 20ms, pin37 is set to Low level and remains in this state forthetimethe horizontal frequency remains 18 kHz (with ZN == 0).This 20 ms delay is required for switching-over the hori-zontal power stage.To change the horizontal frequency in the opposite di-rection, from 18 kHz to 15.6 kHz, the sequence de-scribed is reversed.

3.7. Text Display Mode with Increased DeflectionFrequenciesAs already mentioned, the DPU 2553 provides the fea-ture of increased deflection frequencies for text displayfor improved picture quality in this mode of operation. Toachieve this, the processor acting as deflection proces-sor has its register Zn set to 0. The horizontal output fre-quency at pin 31 is then switched to a frequency of18746.802 Hz which is generated by dmding the Fmmain clock frequency by 946 i 46. The horizontal PLL isthen able to synchronize to an external composite syncsignal offH = 18.746 kHzi 46. The horizontal PLL isthenable to synchronizeto an external composite sync signalof fH = 18.746 kHzi 5 % and f\, = 60 Hz i 10 % and canbe set to an independent horizontal and vertical syncgenerator by setting register VE = 1 and register VB = 0.That means a constant dmder of 946 for horizontal fre-quency and constant 312 lines per frame.

The DPU working in this mode supplies the TPU 2740Teletext Processor or the respective Viewdata Proces-sor with the 18.7 kHz horizontal blanking pulses form pin24 and the 60 Hz vertical blanking pulses form pin 22(see Fig. 3-8).To be able to receive and store data from an IF video sig-nal at the same time, the Teletext or Viewdata Processorrequires horizontal and vertical sync pulses from this IFsignal. Therefore, the second DPU provides videoclamping and sync separation forthe external signal andsupplies the horizontal sync pulses (pin 24) and the ver-tical sync pulses (pin 22) to the Teletext or viewdata Pro-cessor. For this, the second DPU is set to the PAL stan-dard by register ZN = 2, and the clamping pulses of theother DPU are disabled by CLD = 1.To change the output frequency ofthe DPU acting as de-flection processor from 18.7 kHz to 15.6 kHz, the controlswitch output pin 37 prepares the horizontal outputstage for 15.6 khz operation (pin 37 is in the high-impe-dance state) beforethe DPU changesthe horizontal out-put frequencyto 15.6 kHz, after a minimum delay of onevertical period. Switching the horizontal deflection fre-quency from 15.6 kHzto 18.7 kHz is done in the reversesequence. Firstly, the horizontaloutput frequency of pin31 is switched to 1 8.7 khz, and after a delay of one verti-cal period, pin 37 is set low.3.8. D2-MAC Operation ModeWhen receiving Tv signals having the D2-mAC stan-dard (direct satellite reception), register ZN is set to 3.The programmable dmder is set to a dmsion ratio of1296 i48 to generate a horizontal frequency of 15.625khz with the clock rate of 20.25 mHz used in theD2-mAC standard. ln this operation mode, pin 6 acts asinput forthe composite sync signal supplied by the DmA2271 D2-mAC Decoder. The DPU is synchronized tothis sync signal, and after locking-in (status registerUN = 0), the CCU switches the DPU to a clock-lockedmode between clock signal and horizontal frequency(fm mainclock by 1024, during the vertical sync signal separatedfrom the received video signal. To use an 8-bit register,the result of the count is dmded by 2 and given to theDPU status register. ln the CCU, the vertical frequencycan be evaluated using the following equation:

The interlace control output pin 39 supplies a 25 Hz (forPAL and SECAm) or 80 Hz (for NTSC) signal for control-ling an external interlace-off switch, which is requiredwith A.C.-coupled vertical output stages, becausetheseare not able to handle the internal interlace-off proce-dure using register “ZS”.For operation with the vmC Processor the DPU 2554hasthree interlace control modes in double vertical scanmode (DVS = 1). These options can be selected with theregister “IOP” and can be used together with the controloutput pin 39 only. This output has to be connected to thevertical output stage, so that the vertical phase can beshifted by 16 us (or 32 us with DPU 2553).

SCHNEIDER DTV5535 DIGITAL PROFI CONCEPT 55 CHASSIS DTV1 ITT DIGIT2000 CATHODE RAY TUBE (Kinescope) driver with kinescope current sensing circuit:
A television receiver includes a kinescope and a current sensing transistor for conveying amplified video signals to the kinescope, and for providing at a sensing output terminal an output signal related to the magnitude of kinescope current conducted during given sensing intervals. A clamping circuit clamps the sensing output terminal during normal image intervals, and unclamps the sensing output terminal during the sensing intervals. The clamping circuit facilitates interfacing the sensing transistor with utilization circuits which process the sensed output signal, and assists to maintain a proper operating condition for the sensing transistor.

1. In a video signal processing system including an image reproducing device for displaying video information in response to a video signal applied thereto, apparatus comprising:
a video output driver stage with a video signal input and a video signal output for providing an amplified video signal;
means for conveying said amplified video signal to said image reproducing display device, said conveying means having a sensing output for providing thereat a sensed signal representative of the current conducted by said image reproducing display device;
utilization means responsive to said sensed signal; and
clamping means for selectively clamping said sensing output during normal image intervals, and for unclamping said sensing output during intervals when said sensed signal representative of current conducted by said image reproducing display device is subject to processing by said utilization means; wherein
said clamping means comprises clamping transistor means with an output first electrode coupled to said sensing output, a second electrode coupled to an operating potential, and an input third electrode coupled to said sensing output, the conduction of said clamping transistor means being controlled in accordance with the magnitude of said sensed signal as received by said third electrode; and
said clamping transistor means is self-keyed to exhibit clamping and non-clamping states in response to said sensed representative signal.
2. Apparatus according to claim 1, wherein:
said video output stage comprises a video amplifier with a video signal input and a video signal output for providing said amplified video signal; and
said conveying means comprises an active current conducting device with an input first terminal for receiving said amplified video signal, an output second terminal for conveying said amplified video signal to said image reproducing display device, and a third terminal for providing said sensed signal.
3. Apparatus according to claim 2, wherein
said active current conducting device is a transistor with a base input for receiving said amplified video signal, an emitter output for providing said amplified video signal to said image reproducing display device, and a collector output for providing said sensed signal.
4. Apparatus according to claim 1, wherein
said first and second electrodes define a main current conduction path of said clamping transistor means.
5. Apparatus according to claim 4, wherein
said clamping means includes resistive means coupled to said sensing output for providing a voltage in accordance with the magnitude of said sensed signal; and
said third electrode of said clamping transistor means is coupled to said resistive means.
6. Apparatus according to claim 1, and further comprising
filter means for bypassing high frequency signal components at said sensing output.
7. In a video signal processing system including an image reproducing device for displaying video information in response to a video signal applied thereto, apparatus comprising:
a video output driver stage coupled to said image reproducing display device for providing an amplified video signal thereto, and having a sensing output for providing thereat a sensed signal representative of the current conducted by said image reproducing display device;
control means responsive to said sensed signal for developing a control signal;
means for coupling said control signal to said image reproducing display device to maintain a desired conduction characteristic of said image reproducing display device; and
clamping means for selectively clamping said sensing output during normal image intervals, and for unclamping said sensing output during intervals when said control means operates to monitor said sensed signal; wherein
said clamping means comprises clamping transistor means with an output first electrode coupled to said sensing output, a second electrode coupled to an operating potential, and an input third electrode coupled to said sensing output, the conduction of said clamping transistor means being controlled in accordance with the magnitude of said sensed signal as received by said third electrode; and
said clamping transistor means is self-keyed to exhibit clamping and non-clamping states in response to said sensed signal.
8. Apparatus according to claim 7, wherein
said control means includes digital signal processing circuits; and
said control means includes an input analog-to-digital signal converter network.
9. In a video signal processing system including an image reproducing device for displaying video information in response to a video signal applied thereto, apparatus comprising:
a video amplifier with a video signal input for receiving video signals, and a video signal output for providing an amplified video signal;
a signal coupling transistor with an input first electrode for receiving said amplified video signal from said video amplifier, an output second electrode for providing a further amplified video signal to said image reproducing display device, and a third electrode for providing a sensed signal representative of the magnitude of the current conducted by said image reproducing display device;
utilization means responsive to said sensed signal; and
clamping means for selectively clamping said third electrode of said coupling transistor during normal image intervals, and for unclamping said third electrode during interval when said sensed representative signal is subject to processing by said utilization means, said clamping means comprising clamping transistor means with an output first electrode coupled to said third electrode of said signal coupling transistor, a second electrode coupled to an operating potential, and an input third electrode coupled to said third electrode of said signal coupling transistor, the conduction of said clamping transistor means being controlled in accordance with the magnitude of said sensed signal as received by said input third electrode of said clamping transistor means.
10. Apparatus according to claim 9, wherein
said coupling transistor is an emitter follower transistor with a base input electrode, an emitter output electrode, and a collector output electrode corresponding to said third electrode.

Description:

This invention concerns a video output display driver amplifier for supplying high level video output signals to an image display device such as a kinescope in a television receiver. In particular, this invention concerns a display driver stage associated with a sensing circuit for providing a signal representative of the magnitude of current conducted by the kinescope during prescribed intervals.
Video signal processing and display systems such as television receivers commonly include a video output display driver stage for supplying a high level video signal to an intensity control electrode, e.g., a cathode electrode, of an image display device such as a kinescope. Television receivers sometimes employ an automatic black current (bias) control system or an automatic white current (drive) control system for maintaining desired kinescope operating current levels. Such control systems typically operate during image blanking intervals, at which time the kinescope is caused to conduct a black image or a white image representative current. Such current is sensed by the control system, which generates a correction signal representing the difference between the magnitude of the sensed representative current and a desired current level. The correction signal is applied to video signal processing circuits for reducing the difference.
Various techniques are known for sensing the magnitude of the black or white kinescope current. One often used approach employs a PNP emitter follower current sensing transistor connected to the kinescope cathode signal coupling path. Such sensing transistor couples video signals to the kinescope via its base-to-emitter junction, and provides at a collector electrode a sensed current representative of the magnitude of the kinescope cathode current. The representative current from the collector electrode of the sensing transistor is conveyed to the control system and processed to develop a suitable correction signal.
In accordance with the principles of the present invention, there is disclosed a kinescope current sensing arrangement wherein a current sensing device is coupled to a kinescope for providing at an output terminal a signal representative of the magnitude of the kinescope current. A clamping circuit clamps the output terminal to a given voltage during normal image trace intervals. During prescribed kinescope current sensing intervals, however, the clamping circuit is inoperative and the sensed signal representative of the kinescope current is developed at the output terminal. The clamping circuit advantageously facilitates interfacing the current sensing device with control circuits for processing the sensed signal, and assists to maintain a proper operating condition for the current sensing device which, in a disclosed embodiment, also conveys video signals to the display device. In accordance with a feature of the invention, the clamping circuit is self-keyed between clamping and non-clamping states in response to the representative signal at the output terminal.
In the drawing:
FIG. 1 shows a circuit diagram of a kinescope driver stage with associated kinescope current sensing and clamping apparatus in accordance with the present invention; and
FIG. 2 depicts, in block diagram form, a portion of a color television receiver incorporating the current sensing and clamping apparatus of FIG. 1.
In FIG. 1, low level color image representative video signals r, g, b are provided by a source 10. The r, g and b color signals are coupled to similar kinescope driver stages. Only the red (r) color signal video driver stage is shown in schematic circuit diagram form.
Red kinescope driver stage 15 comprises a driver amplifier including an input common emitter amplifier transistor 20 arranged in a cascode amplifier configuration with a common base amplifier transistor 21. Red color signal r is coupled to the base input of transistor 20 via a current determining resistor 22. Base bias for transistor 20 is provided by a resistor 24 in association with a source of negative DC voltage (-V). Base bias for transistor 21 is provided from a source of positive DC voltage (+V) through a resistor 25. Resistor 25 in the base circuit of transistor 21 assists to stabilize transistor 21 against oscillation.
The output circuit of driver stage 15 includes a load resistor 27 in the collector output circuit of transistor 21 and across which a high level amplified video signal is developed, and opposite conductivity type emitter follower transistors 30 and 31 with base inputs coupled to the collector of transistor 21. A high level amplified video signal R is developed at the emitter output of follower transistor 30 and is coupled to a cathode electrode of an image reproducing kinescope via a kinescope arc current limiting resistor 33. A resistor 34 in the collector circuit of transistor 31 also serves as a kinescope arc current limiting resistor. Degenerative feedback for driver stage 15 is provided by series resistors 36 and 38, coupled from the emitter of transistor 31 to the base of transistor 20.
A diode 39 connected between the emitters of transistors 30 and 31 as shown is normally reverse biased and therefore nonconductive by the voltage difference across it equalling the sum of the two base-emitter voltage drops of transistors 30 and 31, but is forward biased and therefore rendered conductive under certain conditions in response to positive-going transients at the emitter of transistor 30, corresponding to the output terminal of driver stage 15. The arrangement of transistor 31 prevents the amplifier feedback loop including transistors 20, 21 and 31 and resistors 36 and 38 from being disrupted, thereby preventing feedback transients and signal ringing from occurring. Additional details of the arrangement including transistors 30 and 31 and diode 39 are found in my copending U.S. patent application Ser. No. 758,954 titled "FEEDBACK DISPLAY DRIVER STAGE". The emitter voltage of transistor 30 follows the voltage developed across load resistor 27, and transistor 30 conducts the kinescope cathode current. Substantially all of the kinescope cathode current flows as collector current of transistor 30, through a kinescope arc current limiting protection resistor 37a, to a clamping network 40. Transistor 30 acts as a current sensing device in conjunction with network 40 as will be explained. Clamping network 40 in this example is self-keyed to exhibit clamping and non-clamping states in response to the magnitude of the current conducted by transistor 30.
Clamping network 40 is common to all three driver stages of the receiver, as will be seen subsequently in connection with FIG. 2, and is coupled to the green and blue signal driver stages via protection resistors 37b and 37c. Network 40 includes clamping transistors 41 and 42 arranged in a Darlington configuration, and series voltage divider resistors 43 and 44 which bias clamp transistors 41 and 42. A high frequency bypass capacitor 46 filters signals in the collector circuit of transistor 30 in a manner to be described below. The series combination of a mode control switch 49 and a scaling resistor 48 is coupled across resistors 43 and 44. A voltage related to the magnitude of kinescope current is developed at a terminal A and, as will be explained with reference to FIG. 2, the voltage at terminal A can be used in conjunction with a feedback control loop to maintain a desired kinescope operating current condition which is otherwise subject to deterioration due to kinescope aging and temperature effects, for example.
Assuming switch 49, the function of which will be explained below, is open, the kinescope cathode current flowing in the collector of transistor 30 is conducted to ground via resistors 43 and 44. When this current causes a voltage drop across resistor 44 to sufficiently forward bias the base-emitter junctions of transistors 41 and 42, transistor 42 will conduct in a linear region, and will clamp terminal A to a voltage VA according to the following expression, where V BE41 and V BE42 are the base-emitter junction voltage drops of transistors 41 and 42: VA=(V BE41 +V BE42 ) (R43+R44)/R44
During normal image intervals typically there are greater than approximately 25 microamperes of current conducted by transistor 30, which is sufficient to render transistors 41 and 42 conductive for developing clamping voltage VA at terminal A. At other times, as will be discussed, transistors 41 and 42 are rendered nonconductive whereby clamping action is inhibited and a (variable) voltage is developed at node A as a function of the magnitude of the kinescope cathode current, for processing by succeeding control circuits.
Illustratively, the arrangement of FIG. 1 can be used in connection with digital signal processing and control circuits in a color television receiver employing digital signal processing techniques, as will be seen in FIG. 2. Such control circuits include an input analog-to-digital converter (ADC) for converting analog voltages developed at terminal A to digital form for processing.
When the control circuits are to operate in an automatic kinescope black current (bias) control mode, wherein during image blanking intervals the kinescope conducts very small cathode currents on the order of a few microamperes, approximating a kinescope black image condition, clamp transistors 41 and 42 are rendered nonconductive because such small currents flowing through resistors 43 and 44 from the collector of transistor 30 are unable to produce a large enough voltage drop across resistor 44 to forward bias transistors 41 and 42. Consequently terminal A exhibits voltage variations, as developed across resistors 43 and 44, related to the magnitude of kinescope black current. The voltage variations are processed by the control circuits coupled to terminal A to develop a correction signal, if necessary, to maintain a desired level of kinescope black current conduction by feedback action. In this operating mode switch 49, e.g., a controlled electronic switch, is maintained in an open position as shown in response to a timing signal VT developed by the control circuits.
When the control circuits are to operate in an automatic kinescope white current (drive) control mode wherein during image blanking intervals the kinescope conducts much larger currents representing a white image condition, switch 49 closes in response to timing signal VT, thereby shunting resistor 48 across resistors 43 and 44. The value of resistor 48 is chosen relative to the combined values of resistors 43 and 44 so that the larger current conducted via the collector of transistor 30 divides between series resistors 43, 44 and resistor 48 such that the magnitude of current conducted by resistors 43 and 44 is insufficient to produce a large enough voltage drop across resistor 44 to render clamping transistors 43 and 44 conductive. Unclamped terminal A therefore exhibits voltage variations related to the magnitude of kinescope white current, which voltage variations are processed by the control circuits to develop a correction signal as required. As used herein, the expression "white current" refers to a high level of individual red, green or blue color image current, or to combined high level red, green and blue currents associated with a white image.
With the illustrated configuration of transistors 41 and 42 clamping voltage VA is relatively low, approximately +2.0 volts. The clamping voltage could be provided by a Zener diode rather than the disclosed arrangement of Darlington-connected transistors 41 and 42, but the disclosed clamping arrangement is preferred because Zener diodes with a voltage rating less than about 4 volts usually do not exhibit a predictable Zener threshold voltage characteristic, i.e., the "knee" transition region of the Zener voltage-vs-current characteristic is usually not very well defined. In addition, the disclosed transistor clamp operates with better linearity than a Zener diode clamp and radiates less radio frequency interference (RFI).
The relatively low clamping voltage is compatible with the analog input voltage requirements of the analog-to-digital converter (ADC) at the input of the control circuits which receive the sensed voltage at terminal A as will be explained in greater detail with respect to FIG. 2. In this example the ADC is intended to process analog voltages of from 0 volts to approximately +2.5 volts, and the clamping voltage assures that excessively high analog voltages are not presented to the ADC during normal video signal intervals.
The relatively low clamping voltage also assists to prevent transistor 30 from saturating, which is necessary since transistor 30 is intended to operate in a linear region. To achieve this result and to maximize the cathode current conduction capability of transistor 30, the clamping voltage should be as low as possible to maintain a suitably low bias voltage at the collector of transistor 30. On the other hand, the value of arc current limiting resistor 37a should be large enough to provide adequate arc protection without compromising the objective of maintaining the collector bias voltage of transistor 30 as low as possible. Operation of transistor 30 in a saturated state renders transistor 30 ineffective for its intended purpose of properly conveying video drive signals to the kinescope cathode, and for conveying accurate representations of cathode current to clamping network 40 particularly in the white current control mode when relatively high cathode current levels are sensed. In addition, undesirable radio frequency interference (RFI) can be generated by transistor 30 switching into and out of saturation. Also, when saturation occurs transistor base storage effects can result in video image streaking due to the time required for a transistor to come out of a saturated state.
Thus clamping network 40 advantageously limits the voltage at terminal A to a level tolerable by the analog-to-digital converter at the input of the control circuits coupled to terminal A, and protects the analog-to-digital converter input from damage due to signal overdrive. Network 40 also provides a collector reference bias for transistor 30 to prevent transistor 30 from saturating on large negative-going signal amplitude transitions at its emitter electrode. The clamping voltage level is readily adjusted simply by tailoring the values of resistors 43 and 44.
Capacitor 46 bypasses high frequency video signals to ground to prevent transistor 30 from saturating in response to such signals. Capacitor 46 also serves to smooth out undesirable high frequency variations at terminal A to prevent potentially troublesome signal components such as noise from interfering with the signal processing function of the input analog-to-digital converter of the control circuits, e.g., by smoothing the current sensed during the settling time of the analog-to-digital converter.
The latter noise reducing effect is particularly desirable, for example, when the input ADC of the control circuits coupled to terminal A is of the relatively inexpensive and uncomplicated "iterative approximation" type ADC, compared to a "flash" type ADC. The operation of an iterative ADC, wherein successive approximations are made from the most significant bit to the least significant bit, requires a relatively constant or slowly varying analog signal to be sampled during sampling intervals, uncontaminated by noise and similar effects.
The value of capacitor 46 should not be excessively large because a certain rate of current variation should be permitted at terminal A with respect to kinescope cathode currents being sensed. If the value of capacitor 46 is too small, excessive voltage variations, particularly high frequency video signal variations, will appear at terminal A, increasing the likelihood of transistor 30 saturating. The speed of operation of the clamp circuit itself is restricted by an RC low pass filter effect produced by the base capacitance of transistor 41 and the equivalent resistance of resistors 43 and 44.
FIG. 2 shows a portion of a color television receiver system employing digital video signal processing techniques. The FIG. 2 system utilizes kinescope driver amplifiers and a clamping network as disclosed in FIG. 1, wherein similar elements are identified by the same reference number. By way of example, the system of FIG. 2 includes a MAA 2100 VCU (Video Codec Unit) corresponding to video signal source 10 of FIG. 1, a MAA 2200 VPU (Video Processor Unit) 50, and a MAAA 2000 CCU (Central Control Unit) 60. The latter three units are associated with a digital television signal processing system offered by ITT Corporation as described in a technical bulletin titled "DIGIT 2000 VLSI DIGITAL TV SYSTEM" published by the Intermetall Semiconductors subsidiary of ITT Corporation.
In unit 10, a luminance signal and color difference signals in digital form are respectively converted to analog form by means of digital-to-analog converters (DACs) 70 and 71. The analog luminance signal (Y) and analog color difference signals r-y and b-y are combined in a matrix amplifier 73 to produce r, g and b color image representative signals which are processed by preamplifiers 75, 76 and 77, respectively, before being coupled to kinescope driver stages 15, 16 and 17 of the type shown in FIG. 1. A network 78 in unit 10 includes circuits associated with the automatic white current and black current control functions.
The high level R, G and B color signals from driver stages 15, 16 and 17 are coupled via respective current limiting resistors (i.e., resistor 33) to cathode intensity control electrodes of a color kinescope 80. Currents conducted by the red, green and blue kinescope cathodes are conveyed to network 40 via resistors 37a-37c, for producing at terminal A a voltage representative of kinescope cathode current conducted during measuring intervals, as discussed previously.
VPU unit 50 includes input terminals 15 and 16 coupled to terminal A. Through terminal 15 the VPU receives the analog signal from terminal A and, via an internal multiplex switching network 51, the analog signal is supplied to an analog-to-digital-converter (ADC) 52. Terminal 16 is connected to an internal switching device (corresponding to switch 49 in FIG. 1) which, in conjunction with scaling resistor 48, controls the impedance and therefore the sensitivity at input terminal 15. High sensitivity for black current measurement is obtained with resistor 48 ungrounded by internal switch 49, and low sensitivity for white current measurement is obtained with resistor 48 grounded by internal switch 49.
The digital signal from ADC 52 is coupled to an IM BUS INTERFACE unit 53 which coacts with CCU unit 60 and provides signals to an output data multiplex (MPX) unit 55. Multiplexed output signal data from unit 55 is conveyed to VCU unit 10, and particularly to control network 78. Control network 78 provides output signals for controlling the signal gain of preamplifiers 75, 76 and 77 to achieve a correct white current condition, and also provides output signals for controlling the DC bias of the preamplifiers to achieve a correct black current condition.
More specifically, during vertical image blanking intervals the three (red, green, blue) kinescope black currents subject to measurement and the three white currents subject to measurement are developed sequentially, sensed, and coupled to VPU 50 via terminal 15. The sensed values are sequenced, digitized and coupled to IM Bus Interface 53 which organizes the data communication with CCU 60. After being processed by CCU 60, control signals are routed back to interface 53 and from there to data multiplexer 55 which forwards the control signals to VCU 10.

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IMPORTANT NOTE: - FRANK SHARP obsoletetellyemuseum.blogspot.comwas founded as a public free WEB Museum to all kind of people and amateur and professional CRT TELEVISION Lovers who enjoy using and/or preserving - restoring vintage CRT Televisions sets, or only curious public who was unaware of that kind of technolgy of the past. The purpose is to provide information about vintage Television Receivers Publicy on the WEB that is generally difficult to locate; all this as a important milestone general worldwide reference for the future, globally in the public interest.obsoletetellyemuseum.blogspot.com does not provide support or parts for any apparatus on this site nor do we represent any manufacturer listed on this site in any way. Catalogs, manuals and any other literature that is available on this site is made available for a historical record only. Please remember that safety standards have changed over the years and information in old manuals as well as the old Television receivers themselves may not meet modern standards. It is up to the individual user to use good judgment and to safely operate old machinery. The obsoletetellyemuseum.blogspot.com web site will assume NO responsibilities for damages or injuries resulting from information obtained from this site. No offer to sell or license — Nothing in this site/Blog may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

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Safety Hazards:

------------------------------------------------------Safety Hazards in Radio and TV Repair,------------------------------------------------------

People who believe they can conquer nature are clueless that the laws of nature are a precondition of their existence. Their weapon is a miserable idea.When man attempts to rebel against the iron logic of Nature, he comes into struggle with the principles to which he himself owes his existence as a man. And this attack must lead to his own doom.

Anyone attempting to repair any electronic equipment who does not fully understand the shock hazards, as well as the fire hazards associated with working with electronic equipment, should not attempt such procedures! Improperly attempted repair can kill you and burn down your house.Devices that plug into the wall can produce a very lethal electric shock as well cause a fire from incorrect or careless repairs both during servicing or later on.Improper repair of battery operated devices can also result in bad consequences for you, the device, and any equipment attached to it.

Why some people do repairs themselved then? If you can do the repairs yourself, the equation changes dramatically asyour parts costs will be 1/2 to 1/4 of what a professional will chargeand of course your time is free. The educational aspects may also beappealing. You also will learn a lot in the process.

Consumer electronic equipment like TVs, computer monitors, microwave ovens, and electronic flash units, use voltages at power levels that are potentially lethal. Even more so for industrial equipment like lasers and anything else that is either connected to the power line, or uses or generates high voltage.

Normally, these devices are safely enclosed to prevent accidental contact. However, when troubleshooting, testing, making adjustments, and during repair procedures, the cabinet will likely be open and/or safety interlocks may be defeated. Home-built or modified equipment, despite all warnings and recommendations to the contrary - could exist in this state for extended periods of time - or indefinitely.

Depending on overall conditions and your general state of health, there is a wide variation of voltage, current, and total energy levels that can kill.

Microwave ovens in particular are probably THE most dangerous household appliance to service. There is high voltage - up to 5,000 V or more - at high current - more than an amp may be available momentarily. This is an instantly lethal combination.

TVs and monitors may have up to 35 kV on the CRTbut the current isn't low - like a wrong legend saying a "couple of milliamps" but relatively high because of the boost circuit technology and transformer design. However, the CRT capacitance can hold a painful charge for a long time. In addition, portions of the circuitry of TVs and monitors as well as all other devices that plug into the wall socket are line connected.This is actually even more dangerous than the high voltage due to the greater current available - and a few hundred volts can make you just as dead as 35 kV!

Electronic flash units and strobe lights, and pulsed lasers have large energy storage capacitors which alone can deliver a lethal charge - long after the power has been removed. This applies to some extent even to those little disposable pocket cameras with flash which look so innocent being powered from a single 1.5 V AA battery. Don't be fooled - they are designed without any bleeder so the flash can be ready for use without draining the battery!

Even some portions of apparently harmless devices like VCRs and CD players - or vacuum cleaners and toasters - can be hazardous (though the live parts may be insulated or protected - but don't count on it!

This information also applies when working on other high voltage or line connected devices like Tesla Coils, Jacobs Ladders, plasma spheres, gigawatt lasers, hot and cold fusion generators, cyclotrons and other particle accelerators, as well as other popular hobby type projects. :-)

In addition, read the relevant sections of the document for your particular equipment for additional electrical safety considerations as well as non-electrical hazards like microwave radiation or laser light. Only the most common types of equipment are discussed in the safety guidelines, below.

SAFETY guidelines:

These guidelines are to protect you from potentially deadly electrical shock hazards as well as the equipment from accidental damage.

Note that the danger to you is not only in your body providing a conducting path, particularly through your heart. Any involuntary muscle contractions caused by a shock, while perhaps harmless in themselves, may cause collateral damage. There are likely to be many sharp edges and points inside from various things like stamped sheet metal shields and and the cut ends of component leads on the solder side of printed wiring boards in this type of equipment. In addition, the reflex may result in contact with other electrically live parts and further unfortunate consequences.

The purpose of this set of guidelines is not to frighten you but rather to make you aware of the appropriate precautions. Repair of TVs, monitors, microwave ovens, and other consumer and industrial equipment can be both rewarding and economical. Just be sure that it is also safe!

Don't work alone - in the event of an emergency another person's presence may be essential.

Always keep one hand in your pocket when anywhere around a powered line-connected or high voltage system.

Wear rubber bottom shoes or sneakers. An insulated floor is better than metal or bare concrete but this may be outside of your control. A rubber mat should be an acceptable substitute but a carpet, not matter how thick, may not be a particularly good insulator.

Don't wear any jewelry or other articles that could accidentally contact circuitry and conduct current, or get caught in moving parts.

Set up your work area away from possible grounds that you may accidentally contact.

Have a fire extinguisher rated for electrical fires readily accessible in a location that won't get blocked should something burst into flames.

Use a dust mask when cleaning inside electronic equipment and appliances, particularly TVs, monitors, vacuum cleaners, and other dust collectors.

Know your equipment: TVs and monitors may use parts of the metal chassis as ground return yet the chassis may be electrically live with respect to the earth ground of the AC line. Microwave ovens use the chassis as ground return for the high voltage. In addition, do not assume that the chassis is a suitable ground for your test equipment!

If circuit boards need to be removed from their mountings, put insulating material between the boards and anything they may short to. Hold them in place with string or electrical tape. Prop them up with insulation sticks - plastic or wood.

If you need to probe, solder, or otherwise touch circuits with power off, discharge (across) large power supply filter capacitors with a 2 W or greater resistor of 100 to 500 ohms/V approximate value (e.g., for a 200 V capacitor, use a 20K to 100K ohm resistor). Monitor while discharging and/or verify that there is no residual charge with a suitable voltmeter. In a TV or monitor, if you are removing the high voltage connection to the CRT (to replace the flyback transformer for example) first discharge the CRT contact (under the insulating cup at the end of the fat red wire). Use a 1M to 10M ohm 1W or greater wattage resistor on the end of an insulating stick or the probe of a high voltage meter. Discharge to the metal frame which is connected to the outside of the CRT.

For TVs and monitors in particular, there is the additional danger of CRT implosion - take care not to bang the CRT envelope with your tools. An implosion will scatter shards of glass at high velocity in every direction. There is several tons of force attempting to crush the typical CRT. Always wear eye protection. While the actual chance of a violent implosion is relatively small, why take chances? (However, breaking the relatively fragile neck off the CRT WILL be embarrassing at the very least.)

Connect/disconnect any test leads with the equipment unpowered and unplugged. Use clip leads or solder temporary wires to reach cramped locations or difficult to access locations.

If you must probe live, put electrical tape over all but the last 1/16" of the test probes to avoid the possibility of an accidental short which could cause damage to various components. Clip the reference end of the meter or scope to the appropriate ground return so that you need to only probe with one hand.

Perform as many tests as possible with power off and the equipment unplugged. For example, the semiconductors in the power supply section of a TV or monitor can be tested for short circuits with an ohmmeter.

Provide a reliable means of warning that power is applied and that high voltage filter capacitor(s) still hold a charge during servicing. For example, solder a neon indicator lamp (e.g., an NE2 in series with a 100K ohm resistor) across the line input and a super high brightness LEDs in series with 100K, 1 W resistors across the main filter capacitor(s).

Use an isolation transformer if there is any chance of contacting line connected circuits. A Variac(tm) (variable autotransformer) is not an isolation transformer! However, the combination of a Variac and isolation transformer maintains the safety benefits and is a very versatile device. See the document "Repair Briefs, An Introduction", available at this site, for more details.

The use of a GFCI (Ground Fault Circuit Interrupter) protected outlet is a good idea but may not protect you from shock from many points in a line connected TV or monitor, or the high voltage side of a microwave oven, for example. (Note however, that, a GFCI may nuisance trip at power-on or at other random times due to leakage paths (like your scope probe ground) or the highly capacitive or inductive input characteristics of line powered equipment.) A GFCI is also a relatively complex active device which may not be designed for repeated tripping - you are depending on some action to be taken (and bad things happen if it doesn't!) - unlike the passive nature of an isolation transformer. A fuse or circuit breaker is too slow and insensitive to provide any protection for you or in many cases, your equipment. However, these devices may save your scope probe ground wire should you accidentally connect it to a live chassis.

When handling static sensitive components, an anti-static wrist strap is recommended. However, it should be constructed of high resistance materials with a high resistance path between you and the chassis (greater than 100K ohms). Never use metallic conductors as you would then become an excellent path to ground for line current or risk amputating your hand at the wrist when you accidentally contacted that 1000 A welder supply!

Don't attempt repair work when you are tired. Not only will you be more careless, but your primary diagnostic tool - deductive reasoning - will not be operating at full capacity.

Finally, never assume anything without checking it out for yourself! Don't take shortcuts!

Many people who mistakenly feel that ‘old technology’ is somehow more user-friendly, in some strange way automatically good - merely because it is old. Don’t be fooled! Approach old equipment with an open and alert mind and realise that a hot chassis, or a resistor line cord, or asbestos insulation, or selenium rectifiers require much more thought and consideration for safety.

Live chassis are indiscriminate in whom they kill and even if you are a thoughtful, careful kind of person, that doesn’t mean the last person who handled the set was.

Vintage radio and television receivers use 'live chassis' techniques, in which the chassis is connected directly to one side of the incoming mains supply. This means they can be lethal to carry out repair or servicing work on, unless the appropriate safety measures are in place.

Another thing about live-chassis sets - live spindles. We’ve touched on this already but it’s worth making the point once more. The shafts of switches and potentiometers fixed to the chassis may well be at chassis potential and thus live. The bakelite or wood cabinet is insulated but these shafts are not, and if someone lost the proper grub screw and replaced a knob using a cheesehead screw, the next person to grip that knob may get a dose of 250 volts. Originally these grub screws were sealed and embedded in wax but you cannot rely on subsequent tinkerers having the same high standards.

Even in more orthodox apparatus standards of insulation were not always as high as they are now. Soldered connections to HT and mains wiring should always have rubber or plastic sleeving but in times gone by this was often omitted (or it may since have perished). Beware too of kinked and frayed braiding on cloth-covered mains cords, particularly when the cord has a dropper conductor.

If you are not satisfied that you fully understand the risks involved in this sort of work, do not proceed any further. Instead seek advice and assistance from a competent technician or engineer.

Whenever you acquire a new treasure there's always a terrific temptation to try it out. With mains-driven equipment that means plugging it in and seeing if it works. Well don't, not until you have made some quick checks.

Before contemplating connecting any unknown receiver to the mains supply, spend a little time inspecting it for signs of missing or loose parts, blown fuses, overheating or even fire damage. Use a meter to check obvious points to ensure no short circuit exists (e.g. across the mains input). If you then decide to apply power keep clear but be observant since an elderly electrolytic might explode! This can be avoided if you can apply power gradually through a variac. Auto-transformers are handy for supplying reduced power to sets being repaired but they are not a substitute for a proper isolation transformer!

If you are working with electricity and your work area has a concrete floor, a rubber mat is essential, particularly during damp weather! Where possible try to arrange a neat working area away from water or central heating pipes. For safety try to arrange that this area is separate from the area occupied by your family. This is emphasised because inadvertently rushing to answer a telephone you might just leave a TV chassis connected to a supply and curious little fingers know nothing of the dangers of electricity - or, for that matter - the lethal vacuum encased within every picture tube!

Many younger enthusiasts may not be aware of the dangers of mishandling tubes, in particular the old round types found in early TVs. When handling these tubes eye protection should be worn and tubes must not be left lying around, they must be stored in boxes. The glass is surprising fragile and can implode without any provocation or warning. Bits of glass flying around at high speed can be deadly. The notes following are inspired by Malcolm Burrell again.

Picture tubes are perhaps one of the most hazardous items in any TV receiver. This is because most are of glass construction and contain a very high vacuum. If you measured the total area of glass in any picture tube then estimated the pressure of air upon it at 14.7lb. per square inch, you would discover that the total pressure upon the device could amount to several tons! Fracturing the glass suddenly would result in an extremely rapid implosion such that fragments of glass, metal and toxic chemicals would be scattered over a wide area, probably causing injury to anyone in close proximity. In modern workshops it is now a rule that protective goggles are worn when handling picture tubes.

The weakest point in most picture tubes is where the thin glass neck containing the electron gun is joined to the bowl. It is therefore essential that you refrain from handling the tube by its neck alone. Once a tube is removed from the receiver hold it vertically with the neck uppermost and one hand beneath the screen with the other steadying the device by the neck.With larger devices it is sometimes easier to grip the peripheral of the screen with both hands.

Until the advent of reinforced picture tubes, most were mounted in the cabinet or on the TV chassis by some form of metal band clamped around the face.Never support the weight of the tube by this band since it has been known for the tube to slide out! Some of the larger tubes are extremely heavy. It may, therefore, be easier to enlist assistance.

Before starting to remove a tube, first discharge the final anode connection to the chassis metalwork and preferably connect a shorting lead to this connection whilst you are working. It might be convenient to keep a spare piece of EHT cable with a crocodile clip at one end and a final anode connector at the other.

Exercise care when removing picture tubes from elderly equipment. You may find that the deflection coils have become stuck to the neck. It is extremely dangerous to use a screwdriver prise them away. Gently heating with a hairdryer or soaking in methylated spirit is safer.

Disposal of picture tubes also requires care. Unless rendered safe they should never be placed in dustbins or skips. Many engineers swipe the necks off tubes in cavalier fashion using a broom handle but this is not recommended. A safer method is to make a hole in the side of a stout carton, preferably one designed to hold a picture tube. The tube is placed in the carton and the neck broken using a broom handle. The carton should then be clearly labelled that it contains chemicals and broken glass!

Therefore people who believe they can conquer nature are clueless that the laws of nature are a precondition of their existence. Their weapon is a miserable idea.When man attempts to rebel against the iron logic of Nature, he comes into struggle with the principles to which he himself owes his existence as a man. And this attack must lead to his own doom.

Think for yourself. Otherwise you have to believe what other people tell you.

For most people thinking is a matter of fortune.A society based on individualism is an oxymoron.Freedom is at first the freedom to starve.A wise fool speaks, because he has something to say.A fool speaks, because he has to say something.A wise fool is silent, because there is nothing to say.A fool is silent, because he has nothing to say.

Resist or regretWork for what's good for our people

Help stem the dark tideStand tall or be beat downFight back or die

The man who does not exercise the first law of nature—that of self preservation — is not worthy of living and breathing the breath of life.

We now live in a nation where doctors destroy health, lawyers destroy justice, universities destroy knowledge, governments destroy freedom, the press destroys information, religion destroys morals and our banks destroy the economy.The globalist argument is that if only we erase distinctions, obliterate identities, put everyone on a level playing field, etc.. we can eliminate war and everyone can be so prosperous and efficient, such great cogs in a well-oiled global machine.There will be no more historical grievances because people will no longer even care, they'll have no connection to the past, no foolish pride in past accomplishments of people totally unrelated to them.A globalized culture, no borders, everyone a citizen of the world.Know this: I will never acquiesce to this corrupt, inhuman, Borg-like vision. The dangerous lunatics who push us towards their globalized "utopia" are my enemy. How exactly all this will play out, whether through wars, or whether we can thwart the globalist agenda peacefully (this is my hope of course) I don't know. But I do know that unless people are willing to fight and die, globalism will win out in the end.The actual crimes committed by the EU against the European peoples are directly in violation of the 1948 UN genocide convention, Article II: (c) Deliberately inflicting on the group conditions of life calculated to bring about its physical destruction in whole or in part; (d) Imposing measures intended to prevent births within the group; (e) Forcibly transferring children of the group to another group.* The man who does not exercise the first law of nature—that of self preservation — is not worthy of living and breathing the breath of life.

TELEVISION HISTORY IN BRIEF

Television history

At 1928 Baird transmits from London to New York, using his mechanical system.with 30 vertical lines. By 1930 it was clear that mechanical television systems could never produce the picture quality required for commercial success. For this reason mechanical system was rapidly succeeded by the electronic TV systems. The first all-electronic American systems in 1932 used only 120 scanning lines at 24 frames per second Since the mid-1930s picture repetition frequency (field rate or frame rate) has been the same as the mains frequency, either 50 or 60Hz according to the frequency used in each country. This is for two very good reasons. Studio lighting generally uses alternating current lamps and if these were not synchronised with the field frequency, an unwelcome strobe effect could appear on TV pictures. Secondly, in days gone by, the smoothing of power supply circuits in TV receivers was not as good as it is today and ripple superimposed on the DC could cause visual interference. If the picture was locked to the mains frequency, this interference would at least be static on the screen and thus less obtrusive.To determine what electronic system to use, the BBC sponsored trial broadcasts by two systems, one by Baird, with 240 lines, and one by EMI with 405 lines. Scheduled electronic television broadcasting began in England in 1936 using 405-line system (lasted until the 1980s in the UK). Germany made their forst TV broadcasts at 1936 olympics using 180-line TV system. Germany also made their TV broadcasts by the fall of 1937 using a 441-line system. Also fFrance tested TV (455 line system). RCA introduced electronic television to the U. S. at the 1939 World's Fair,and began regularly scheduled broadcasting at the same time (525 line system).In 1940 the USA established its 525-line standard. At year 1941 the 525-line standard, still in use today in USA, was adopted.Russia also produced TV sets before the war (240 and 343 line systems).World War Two interrupted the development of television. Immediately after World War Two production of TV sets started in the U.S-In USA there was TV broadcasts and few throusand receivers at 1945. In the early 1950s, two competing color TV systems emerged: CBS sequential color (used color wheel) and RCA dot sequential system. At 1953 color broadcasting officially arrives in the U.S. on Dec. 17, when FCC approves modified version of an RCA system.It calls this new RCA color system "NTSC" color. The first NTSC color TVs were on the marker at 1954.In Europe the TV broadcasts started to use experiment using 625 line system 1950s. This standard is used nowadays throughout Europe. France also tried 819 line system at the same time (this system was in use to 1980s). The rest of Europe opted for 625 lines, a system devised in 1946 by two German engineers, M??ller and Urtel (it appears that the Russians came up independently with a very similar system). The use of PAL color standard started at around 1967 and is still in use. The SECAM color system (used in France) testing started also at 1967. The TV broadcasting history has not ended. The newst thign is digital television. It is expected that terrestrial television will open up billion-dollar opportunities for those companies and organisations best prepared to embrace this new broadcasting era. At 1996 small digital satellite dishes hit the market. They become the biggest selling electronic item in history next to the VCR.

Using TV 24H

TV has something for everyone. Idiots, intellectuals, fans of all sorts. Some people are couch potatoes, watch anything just to sit there and be mindless. That's their problem. Children have always needed to be monitored by their parents. If people gotta a mind for it they could figure out the real news even without the internet and there has always been a library.

Is TV bad in and of itself? The researchers aren’t saying that. But we all know that watching television is a solitary, isolating occupation that keeps you sedentary. Sitting in front of the boob tube reduces the time you have available to exercise, interact with your family, read books, and be outdoors. This new research dovetails with other studies, which have linked excessive TV time to obesity and higher rates of cardiovascular disease.

watching too much television can jeopardize your whole family’s health.

This should be a wake-up call to all adults. Stay active. Go outside. Spend time with your spouse and your children with the television off. Read a book and do crossword puzzles to stimulate your imagination and your brain. Reduce your screen time as much as you can.

The National Cancer Institute researchers suggest that watching TV is a public health issue. The price we are paying for our technology-driven lives may be much higher than we previously realized !

DON'T WATCH TV AT ALL !!

The Propaganda TV Machine a.k.a. The Ministry of Truth delivers The Truth from The Government to the people.

At least, that's what they say. In fact, a Propaganda Machine is only employed by The Empire and used to brainwash people into Gullible Lemmings who believe that everything is all right when in fact, it isn't, and that the very people who could help them are their enemies.

Girl Looking TV.

Happy Times:

Do you remember when a telly looked like a real telly? When it was a piece of furniture that you lavished love on, even polished from time to time ?When it was a piece of somewhat at looking in to ?When it was a piece of Highest tech looking inside ? First, this site is a Digital free, HD free, flat panel, HDMI, China, Turks, Afrika free zone. All in all a wealth of vintage information at your finger tips, a one stop unique experience. So step on in, leave the modern throw-away world behind, travel back in time to a vintage world of repair and enjoy.This site has stirred memories about the watching TV's days on a CRT TUBE television......Childhood memories, your parents getting their first colour tv, a b/w or color portable, perhaps memories of renting or buying your first set remote featured, perhaps your days working in the trade, selling or repairing them....... If you enjoyed this site, found its content left you all misty eyed then just talk about it as it would be very welcome............like the time to recover and restore a set ................and happy reminiscing.

Digital TV in Brief.

Digital TV:

Digital television is a hot topic now.If you have looked at television sets at any of the big electronics retailers lately, you know that Digital TV, or DTV, is a BIG deal right now in the U.S. In Europe Digital TV is also a hot topic, because many countries have started terrestrial digital TV broadcasts and plan to end analogue broadcasts after some years (will take 5-10 years). Satellite TV broadcasts have also shifted very much to digital broadcasts.The main advantage if digital broadcasts are that it does not havethe picture quality problems of analogue TVs (it had it's own videoproblems caused by video compression), it allowes putting more TV channels to same medium (TV channel frequencies and satellites) and it allows new services (like HDTV and interactive multimedia). The digital brodcasts are generally designed to use such modulation that the digital data stream (typically around 20-30 Mbit/s) is modulated to the same bandwidth (around 6 MHz) as the analogue TV broadcasts. The used modulation vary between different media, which means thatdifferent modulation techniques are used in terrestrial transmissions, cable TV and satellite. Different modulations are used because of the different characteristics of those transmission medias. There is not on "digital TV", but several different variations of it in use.The basic technology of digital TV, known as MPEG 2 video compressionand MPEG 2 transmission stream format, is same around the world, butis is used somewhat differently in different standards used in differentcountries.

USA uses ACTS Digital Televisio Standard, which standardizes NTSC format transmissions, HDTV transmission, sound formats and data signal modulation in use. The ATSC MPEG-2 formats for DTV, including HDTV, uses 4:2:0 samling for video signal. The US system uses a fixed power and a fixed maximum bitrate, at which some bits are always transmitted. That rate is typically 19.3 Mb/sec.

Europe uses DVB (Digital Video Broadcasting) standard. This standardallows basically normal PAL resolution transmisssion (vasically HDTVcould be added later but is not yet standardized) with several audio formats, digital data rates and digital signal modulation. There are several different variations fo DVB standard for different media:

DVB-T for terrestrial broadcastsDVB-S for satelliteDVB-C for cable TV

Those different DVB versions varyon the data signal modulation methods, error correction and frequency bands used. DVB and option for some interactive extra services, but thestandardization of this is not ready here yet(there are fire different incompatible interactive servicessystems in use in different countries and by different broadcasters).

The process of transmitting digital TV signal is the following: Analog video/audio - digitisation - MPEG compression - Multiplexing ( youcan now call it digital) - Preparation for transmisson - modulation toanalog carrier.Reception process is the following: Demodulation of analogue carrier - Error correction - Demultiplexing - MPEG decompression - DA conversion to get analogue signal (unless you use digital display). The analoguie video signal that gets digitized can be practically from any video source, for example produced with old analogue video production equipment and distributed with a video tape. In high-end system the information is analogue only in the image sensor on the video camera, and from this on the signal gets digitally processed. In many real-life TV production systems the reality is something between those two extremes.

At least in Europe, the signal level requirements for DVB-T are well below the analog requirements, so the transmitter power is much less than on the analog side. In the NorDig recommendation the minimum received signal level for 64QAM, 7/8 code rate with a Rayleigh fading path and 8 dB receiver noise figure would be -64 dBm. With other code rates, modulations and fading mechanisms, the requirement is lower. Many receivers can perform much better at conditions where there is no fading (a quasi error free less than one uncorrected error/hour signal even at 27 dBuV (-82 dBm) with 64QAM and 8 MHz channel width). For analog signals, the recommended level is more than 1 mV (+60 dBuV, -49 dBm). While the ERP can be at least 10 dB lower than analog, the question of power consumption is more complicated, since COFDM with 64QAM carriers require a quite good linearity, which may affect the efficiency and hence power consumption.

Digital TV system in use in USA

The FCC mandate to change our broadcast standards from NTSC analog to ATSC digital broadcasting (DTV) is big bold move, requiring changes in everything from the way the studios shoot video, the format that's transmitted, to the equipment we use to receive and watch broadcastsDTV (digital TV) applies to digital broadcasts in general and to the U.S. ATSC standard in specific. The ATSC standard includes both standard-definition (SD) and high-definition (HD) digital formats. The notation H/DTV is often used to specifically refer to high-definition digital TV. The federal mandate grants the public airwaves to the broadcasters to transmit digital TV in exchange for return of the current analog NTSC spectrum, allowing for a transition period in the interim. At the end of this period scheduled for 2006, broadcasters must be fully converted to the 8VSB broadcast standard. Digital Television ("DTV") is a new broadcast technology that will transform television. The technology of DTV will allows TV broadcasts with movie-quality picture and CD- quality sound and a variety of other enhancements (for example data delivery). With digital television, broadcasters will be able to offer free television of higher resolution and better picture quality than now exists under the current mode of TV transmission. If broadcasters so choose, they can offer what has been called "high definition television" or HDTV, television with theater-quality pictures and CD-quality sound. . Alternatively, a broadcaster can offer several different TV programs at the same time, with pictures and sound quality better than is generally available today. HDTV (high-definition TV) encompasses both analog and digital televisions that have a 16:9 aspect ratio and approximately 5 times the resolution of standard TV (double vertical, double horizontal, wider aspect). High definition is generally defined as any video signal that is at least twice the quality of the current 480i (interlaced) analog broadcast signal. There are 18 approved formats for digital TV broadcasts, but only two (720p/1080i) are proper definition of the term HDTV. The advent of high definition has allowed monitors to read images differently, either in standard interlaced format or progressively. Sets that do not have any decoding capabilities but can display the high-resolution image is often labeled as "HD-Ready" a term that describes 80% or more of the Digital TVs on the market. HDTV displays support digital connections such as HDMI (DVI) and IEEE 1394/FireWire, although standardization is not finished. HDTV in the US is part of the ATSC DTV format. The resolution and frame rates of DTV in the US generally correspond to the ATSC recommendations for SD (640x480 and 704x480 at 24p, 30p, 60p, 60i) and HD (1280x720 at 24p, 20p, and 60p; 1920x1080 at 24p, 30p and 60i). In addition, a broadcaster will be able to simultaneously transmit a variety of other information through a data bitstream to both enhance its TV programs and to provide entirely new services. The technical specifications of USA DTV system is defined in ACTS Digital Television Standards.

Digital TV in Europe

Digital TV brodacasting in Europe is done according to DVB standards. DVB technology has become an integral part of global broadcasting, setting the global standard for satellite, cable and terrestrial transmissions and equipment. There are three versions of DVB in use: DVB-S, DVB-C and DVB-T.DVB-T is a flexible system allowing terrestrial broadcastersto choose from a variety of options to suit their various service environments. This allows the choice between fixed roof-top antenna, portableand even mobile reception of DVB-T services. Broadly speaking the trade-off in one of service bit-rate versus signal robustness.

DVB-T network is very flexible. Having many transmitters all on the same frequency is not a problem for the used COFDM based system. COFDM has been chosen and designed to minimise the effects of multipath in obstructed reception areas. In fact multipath signals can significantly improve the overall received signal with no adverse effects. These properties are particularly valuable for radio cameras and mobile links. DVB-T because of its unique design which allows single frequency networks (SFN). This means that many transmitters along the planned routes can transmit on the same frequency. It is also possible to use simple gap fillers that amplify and retransmit the signal. In-air digital TV broadcasts in Europe use DVB-T. 8 MHz of bandwidth may be used to provide a 24 Mbps digital transmission path using Coded Orthogonal Frequency Division Multiplexing (COFDM) modulation (theoretical maximum 31.67 Mbits for 8 MHz bandwidth). In cases where less bandwidth is available (6 or 7 MHz), the data rate is somewhat lower (around 20 Mbit/s).

DVB-C does the same function as DVB-T, but the modulation used in this system is optimized to operate well in cable TV networks. The modulation used in DVB-C is QAM. Systems from 16-QAM up to 256-QAM can be used, but the system centres on 64-QAM, in which an 8MHz channel can accommodate a physical payload of about 38 Mbit/s. Digital cable TV in Europe uses DVB-C. The DVB standard for the cable return path has been developed jointly with DAVIC, the Digital Audio Visual Council. The specification uses Quadrature Phase Shift Keying (QPSK) modulation in a 200kHz, 1MHz or 2MHz channel to provide a return path for interactive services (from the user to the service provider) of up to about 3Mbit/s. The path to the user may be either in-band (embedded in the MPEG-2 Transport Stream in the DVB-C channel) or out-of-band (on a separate 1 or 2MHz frequency band).

DVB-S is the satellite version of DVB. Satellite transmission has lead the way in delivering digital TV to viewers. Established in 1995, the satellite standard DVB-S is the oldest DVB standard, used on all six major continents. QPSK modulation system is used, with channel coding optimised to the error characteristics of the channel. A typical satellite channel has 36 MHz bandwidth, which may support transmission at up to 38 Mbps (assuming delivery to a 0.5m receiving antenna) using Quadrature Phase Shift Keying (QPSK) modulation. 16 bytes of Reed Solomon (RS) coding are added to each 188 byte transport packet to provide Forward Error Correction (FEC) using a RS(204,188,8) code. For the satellite transmission, the resultant bit stream is then interleaved and convolutional coding is applied.

The core of the DVB digital data stream isthe standard MPEG-2 "data container",which holds the broadcast and service information.This flexible "carry-all" can containanything that can be digitised, includingmultimedia data. The MPEG-2 standards define how to format the various component parts of a multimedia programme (which may consist of: MPEG-2 compressed video, compressed audio, control data and/or user data). It also defines how these components are combined into a single synchronous transmission bit stream. The process of combining the steams is known as multiplexing. The multiplexed stream may be transmitted over a variety of links, standards / products.Each MPEG-2 MPTS multiplex carries a number of streams which in combination deliver the required services. A typical data rate of such multiplex is around 24 Mbps for terrestrial brodcasts.

European DVB systems currently transmit only standard definition TV signals and set top boxes also handle only normal TV resolution. It would be possible to transmit HDTV signals on DVB data stream, but those broadcasts have not yet started in any wide scale. There is one satellite broadcater that broadcasts HDTV DVB signals in Europe (some cable TV operators carry that signal on their cable).

Many DVB-T integrated TV sets, and some set top boxes, in the Europe come with a Common Interface slot - which is pretty much the same form-factor as a PC Card (aka PCMCIA) used in PC laptops. This CI slot accepts a Conditional Access Module, in the same way that DVB-S receivers do, which implements at least one (some can do more than one) decryption algorithm. This CAM may also, itself, have a smart card slot to accept a consumer subscription card to authorise decryption - you plug your smartcard into your CAM and your CAM into the CI slot in your receiver/IDTV. Some DVB receivers have an integrated CAM (in the case of some receivers this is implemented purely in software, with no extra hardware required) rather than a CI slot to plug in a 3rd party device. With these type of receivers you just plug in the smart card and don't have to worry about CI slots and buying CAMs. So there is an interface standard for DVB - but different broadcasters can chose different encryption schemes, requiring different CAMs for decryption.

DVB Standards and related documents are published by the European Telecommunications Standards Institute (ETSI). These include a large number of standards and technical notes to complement the MPEG-2 standards defined by the ISO.

There are few different standard how interactive TV functionaly is implemented in DVB-systems in use in differenct countries. DVB-MHP is one gaining some acceptance. Multimedia Home Platform (MHP) is the open middleware system designed by the DVB Project (www.dvb.org).

Obsolete Technology Tellye ! Visitors From 15/May/2012:

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