As the 50th Design Automation Conference opens, attendees rushing through the doors early Monday may have their heads in a Cloud. Cloud computing that is, and heading straight toward Booth #846.

That’s because OneSpin Solutions in Booth #846 figured out the gnarly security problem that’s prevented more widespread adoption of the Cloud in EDA and the semiconductor industry. The need for proprietary design code to leave the office has been eliminated.

Briefly, OneSpin’s technology analyzes the design code locally and only transmits an encrypted mathematical abstraction of the verification problem with all the descriptive details stripped away. After processing, results are returned to the local machine and the descriptive details are reapplied. No data is retained in the Cloud. Functionality is provided by OneSpin’s formal verification tools, 360 DV-Inspect and 360 DV-Verify, and is meant to be simple to use and easy to adopt in a flow.

Let’s not focus too heavily on the OneSpin Cloud Strategy, though it’s an important breakthrough. Instead, I invite you to stop by its DAC Booth #846 to see for yourself and, if you’re interested, sign up to become a Beta user. Approved project teams will be able to access cloud servers at no charge, less a minimal charge to OneSpin Cloud System host Amazon Web Services (AWS) Marketplace, until August 30.

A Spin Around OneSpin Solutions

Jim Cantele is OneSpin’s vice president of worldwide sales.

With a nifty Cloud Strategy and so much more, OneSpin Solutions is executing on its lofty goal: A commitment to produce software that verifies the chip works as intended and is ready for tapeout in just one spin.

While 2012 is only a distant memory, it’s worth noting that OneSpin had double-digit growth that year, remarkable given the complete change in direction implemented mid-year. Readers who follow OneSpin may have lost sight of this entrepreneurial company’s progress last year. That’s because it took a lower profile to reassess the verification space.

Since then, OneSpin’s CEO Dr. Raik Brinkmann notes that adoption of its formal ABV tools for both ASIC and FPGA designs is way, way up. The tools are used to verify designs in markets that range from telecommunications and automotive to consumer electronics and embedded systems. In fact, OneSpin signed a large deal with a major semiconductor company in mid-May. Kudos all around!

Raik claims that design teams need formal verification more than ever because of chip complexity, smaller teams, faster turnaround time required to meet market conditions and on and on it goes. Finding the opportunities requires a senior executive to build a solid, worldwide sales and support team. And, that’s just what OneSpin did with the recent appointment of Jim Cantele to the position of vice president of worldwide sales. Jim’s a popular and seasoned sales executive with technical knowledge and a skill for relationship building. “He has an impressive track record and the essential skills we’re looking for as we gain momentum and grow our business,” remarks Raik.

OneSpin’s management team includes (from left to right) Dominik Strasser, vice president of engineering, Raik Brinkmann, CEO, and Oliver Habeck, chief financial officer.

Raik and another co-founder Dominik Strasser assumed management positions as part of the transition last July. Dominik is now vice president of engineering. Oliver Habeck is chief financial officer. Dave Kelf, another well-known and popular EDA executive, is serving as director of marketing and rounds out the executive team with Raik, Dominik, Oliver and Jim.

Part of the transformation of OneSpin was developing a new business strategy and a focused approach to providing enduring solutions that enable the most thorough and easiest-to-use commercial logic verification software. Formal verification technology combined with simulation significantly reduces the effort required to verify designs, while having a dramatic effect on bug discovery in complex operational scenarios. These tools are considered hard to use and require significant compute resources and runtime, raising barriers to mainstream adoption. According to Raik, OneSpin already offers the best ROI for formal verification and the easiest tools to learn to use. Now, it’s a matter of letting verification engineers and design teams in on this.

Dave Kelf is OneSpin’s director of marketing.

The reconstituted team produced a roadmap that streamlined the existing product lines to focus on tool solutions and devised a plan for additional verification products that’s being unveiled throughout 2013.

Ah, readers are wondering about capitalization, for software development doesn’t come free. OneSpin secured a round of funding from Azini Capital to grow the business and implement the new strategy. Azini Capital is a believer –– it likes the new strategy and the professionalism of the team.

This funding allowed OneSpin to put a foot on the gas. It was able to increase the size of its engineering team and hire additional sales managers and application engineers in North America and Europe, including new distributors in Eastern Europe and Israel. Corporate headquarters was moved to another, larger location in Germany and a new office was opened in Santa Clara, Calif.

And, here’s everyone enjoying the meal.

In April, it rolled out Spinnaker Certified Service Partners Program, a service partners program to ensure a broad range of service expertise to meet a variety of verification needs. Inaugural members are Methods2Business, Oski Technology, Syosil, Terastatic and Test and Verification Solutions (TVS), all certified to offer services using either the OneSpin 360 EC or the 360 DV Product Families. Each is trained and certified to offer services using OneSpin’s design verification or equivalence checking software. Member partners are then able to use its formal verification solutions in their customer engagements with the full support of OneSpin’s technical staff.

To all those EDACafe readers at this year’s DAC: Keep your heads in the Cloud and proceed to the OneSpin Booth #846. This is one company with its head in the Cloud and feet firmly planted in formal verification.

It’s fitting that Breker Verification Systems will celebrate its 10th anniversary during the 50th Design Automation Conference (DAC) in Austin, Texas. That’s because 10 years ago Breker was founded in Austin. And, while the corporate headquarters moved to Silicon Valley two years ago, its roots are firmly planted in Austin. Rick Nordin, vice president of business development, remains in the cultural epicenter of Texas taking care of business there. After all, Austin chip development teams have loads of verification issues.

Breker’s new corporate headquarters now sits firmly in the epicenter of Silicon Valley, San Jose, Calif., also a hot spot for verification and perfect for the kind of EDA software Breker produces –– SoC verification. That is, software to rigorously test the entire chip design, not just its individual pieces stitched together. In fact, Breker is defining and building SoC verification as a new verification category.

While some skeptics may question the necessity of this extra verification step, companies such as NVIDIA wouldn’t consider a verification strategy without it. After all, a stitch and ship strategy will sink a chip. We’ll get to more of that later in our profile.

Co-founders Adnan Hamid and Maheen Hamid are a husband and wife team. Adnan is chief executive officer, visionary and chief technologist, while Maheen is chief financial officer, who is serving as chief operating officer as well.

Adnan Hamid is a Breker co-founder and serves as CEO, visionary and chief technologist.

Maheen is a Breker co-founder and serves as CFO. She’s also a blogger and writes opinion pieces on a variety of business topics.

Adnan is often asked about the name Breker. His usual response starts with a hearty laugh. He was given the nickname Breaker in the MBA program at The University of Texas’ McCombs School of Business once his classmates found out he broke things for a living. His expertise is hardware verification and it was Adnan, while working for AMD, who designed an automated test generator to make sure that the AMD microprocessor K7 was fully compatible with Intel’s.

When he and Maheen struck out on their own in 2003, Breaker was the obvious choice for a name, but soon morphed into Breker and the name stuck. Initially, Breker took on verification consulting projects while the software was under development. TrekSoC was launched in 2008 to remove functional verification as the bottleneck for technological innovation and project schedules. It’s an innovative solution that automatically generates self-verifying C test cases to solve complex verification challenges for SoCs containing embedded processors. And, since 2008, Breker’s can point to many successes with project teams as varied as Broadcom and STMicroelectronics, and NVIDIA.

A lot has happened in the two years Breker relocated from Austin to San Jose. For example, it raised $5 million in Series A funding from Astor Capital Group, a private equity firm from Far East Asia. Previously, Breker bootstrapped the company with a small, initial round of angel investment.

Tom Anderson assumed the role of vice president of marketing, joining Adnan, Maheen and Rick on the management team that also includes Dave Johnson, vice president of sales. Special mention should be made that Michel Courtoy, an EDA entrepreneur and verification expert, is an active member of its board of directors and an almost ex-officio company executive.

Tom Anderson is Breker’s vice president of marketing.

Rick Nordin is Breker’s vice president of business development and man in Austin.

Breker’s vice president of sales is Dave Johnson.

EDA entrepreneur and verification expert Michel Courtoy is an active member of its board of directors and an almost ex-officio company executive.

Stitch and Ship

“Stitch and ship will sink a chip design” is almost a mantra within Breker and well worth exploring a bit more. Being verification experts, the Breker team has seen design teams mistakenly assume that an SoC full of multiple heterogeneous embedded processors will work as intended if individual IP blocks have been verified on their own.

Yikes! They should be thinking like systems integrators. While the IP may have been rigorously tested, cross interactions between the IP can create scenarios where the sum of the parts is greater than the whole. That leads to system failure in a real-world situation.

Instead, design teams should develop a SoC verification methodology to exercise a variety of functional scenarios, including cross-interactions and ways to cover all points of convergence. Graph-based scenario models capture intended behavior of the IP blocks. They can be combined to create scenario models for major subsystems or the complete SoC. TrekSoC can “read” these scenario models intelligently and then automatically generate self-verifying C test cases to run on multiple heterogeneous embedded processors within the SoC. These multi-processor, multi-threaded test cases thoroughly exercise the system-level chip functionality, running end-to-end user scenarios with randomized variations, harnessing the power of the embedded processors to verify the SoC from the inside out.

Breker at DAC

You got it! The Breker Booth (#2015) theme is “Stitch and Ship will Sink Your Chip.” As proof, Breker will demonstrate TrekSoC daily from 9 a.m. until 6 p.m. Monday, June 3, through Wednesday, June 5, at the Austin Convention Center. The booth will feature a skit and a variety of presentations from Breker and its partners. Special musical entertainment from Rudy Roberson is planned also. Rudy has an extensive background in acting, singing and storytelling, including two years touring as a cast member of The Lion King and appearances on multiple original-cast recordings.

In another nod to its hometown, Breker will host a dinner cruise around Austin’s Lady Bird Lake June 4 for lucky attendees whose names are drawn at the end of each booth presentation Monday and Tuesday. The cruise will feature the exodus of the bats living under the Congress Avenue Bridge as they head out for their nightly feeding.

Breker will host a dinner cruise around Austin’s Lady Bird Lake. Stop by the Breker Booth (#2015) at DAC to enter the drawing.

Breker is all over the DAC program. Engineers from IBM will present “Graph-Based Verification Patterns,” a look at how they apply Breker’s TrekSoC to a real-world verification project, during the Designer Track June 4 from noon until 1:30 p.m.

Adnan will participate in a DAC technical panel moderated by Brian Bailey of Brian Bailey Consulting titled, “Disruptive Verification Technologies: Can They Really Make a Difference?” June 5 from 9 a.m. until 10:30 a.m. Additionally, Tom Anderson organized “Organizational and Management Solutions to the Verification Crisis,” a DAC pavilion panel June 4 from 1:30 p.m. until 2:30 p.m.

EDACafe readers who will be at DAC next week should plan to take in the Breker experience in Booth #2015. It will be a great learning experience about the risky stitch and ship strategy. It will be a chance to meet Adnan and Maheen and enter to win a ticket for the dinner cruise around Austin’s Lady Bird Lake. Don’t forget to wish the Breker team a happy 10th anniversary.

Last summer, Russ Henke, EDACafe’s then contributor, called Uniquify a uniquely Silicon Valley company in a profile called, “A Visit to Uniquify,” (found here: http://tiny.cc/4jjlxw). Having had a chance to work with the Uniquify team and get to know many of them, I can attest to the uniqueness that you’ll only find in Silicon Valley.

Since the original EDACafe profile, Uniquify relocated its corporate headquarters from a cramped space in Santa Clara, Calif., to a handsome and large building in San Jose, close to Highway 880, tripling the office space.

The office may have moved, but the goal to create chips easier and faster with better results remains. A comprehensive design services platform called ideas2silicon introduced last year offers project teams faster turnaround, lower costs and a transparent business model to provide rapid assembly of IP blocks into a base system. Uniquify’s successfully completed various design services, manufacturing services and IP projects through ideas2silicon that range from leading-edge designs at 28nm, but also 40, 65 and 90nm. Satisfied customers include Tehuti Networks, Ikanos, LG and Pixelworks. Many of the projects had low power as a goal, and end products are everything from networking, consumer electronics, image and media processing to digital TV.

In the new office, everyone’s able to spread out and there are enough conference rooms to handle all the daily meetings and then some. This office includes a dedicated on-site engineering working space for Uniquify’s customers and a lab area that everyone’s proud of. Visitors waiting in the lobby sometimes can hear the thwack of table tennis balls hitting the rackets.

When I finally have a chance to catch up with Bob Smith, Uniquify’s senior vice president of marketing and business development, he had just returned from a whirlwind week in Asia. On this day, he and his team were wrapping up the results of the “DDR with Confidence” Technology Symposium held in Korea and Taiwan. Bob and Gabe Iniguez, Uniquify’s marketing communications manager, took the original DDR Technology Symposium held in February in Santa Clara, Calif., on the road and met with great interest.

Bob Smith is Uniquify’s senior vice president of marketing and business development,

According to Bob, a good many project teams have huge challenges when trying to implement and deploy DDR-based designs and are looking for ways to improve or solve these challenges, especially at 28nm. They are finding that process variation effects and dynamic variations due to fluctuating operating conditions degrade system performance and can cause system instability. The system becomes inoperative.

Josh Lee, Uniquify’s co-founder, president and CEO, is a clever engineer who figured out a way to address this by measuring relevant parameters critical for performance and reliability, and automatically making adjustments to ensure they are optimized. Uniquify calls this Adaptive IP. Its unique (there’s that word again) adaptive and patented DDR memory subsystem IP that has captured the attention of these project teams.

Josh Lee is Uniquify’s co-founder, president and CEO.

Hence, the big crowds at all three symposium events and huge interest in Uniquify’s Adaptive DDR memory subsystem IP.

Uniquify has been conducting a series of “DDR with Confidence” Technology Symposium events in 2013.

Now, Bob is turning his attention to the 50th Design Automation Conference, where Uniquify will showcase its Adaptive DDR IP, along with its SoC design and manufacturing solutions in its two exhibit spaces. Yes, two booths. More on that later.

But first, Uniquify is a proud sponsor of the Heart of Technology’s HOT Zone, part of DAC’s Kickin’ It Up in Austin party to celebrate its 50th year, Monday, June 3, at Austin City Limits Live. The Heart of Technology (HOT), founded by Jim Hogan, supports non-profits where all funds raised go directly back into the communities they visit. The recipient is CASA (Court Appointed Special Advocates) of Travis County, Texas. It speaks up for children who have been abused or neglected by empowering the community to volunteer as advocates for them in the court system.

Uniquify is a proud sponsor of the Heart of Technology’s HOT Zone, part of DAC’s Kickin’ It Up in Austin party to celebrate its 50th year, Monday, June 3, at Austin City Limits Live.

When asked what Uniquify will have to demonstrate to DAC attendees, he handed me a mailer that he came up with on the Top 10 Reasons why DAC attendees should stop by and visit with Uniquify.

In descending order, they are:

10. A project team has a great product idea, but needs help turning it into an ASIC or SoC … Talk to Uniquify!

9. Attendees can find out about Uniquify’s complete SoC manufacturing and design services and more than 300 successful projects.

8. They can learn about Perseus, Uniquify’s automated design management system that delivers predictable, consistent high quality designs in the shortest amount of time.

7. If an attendee is looking for DDR IP, Uniquify’s got it.

6. Or if he or she needs 28nm or beyond, Uniquify is silicon proven with many designs in production.

5. DAC attendees need a definition of Adaptive IP should see Uniquify in Booth 1941 to learn what it is and why it’s important.

1. Perhaps the best reason of all … DAC attendees can relax and play IPong in the “Chill Zone” in Booth 615.

Obviously, Josh Lee isn’t the only clever person at Uniquify. And, this Top 10 List should explain why Uniquify has two booths at DAC this year. One for business, one for fun and relaxation, which makes perfect sense at Uniquify and a perfect balance for DAC.

Uniquify will be in two DAC booths — #1941 and #615. Here’s a look at the booth graphic.

We barely scratched the surface on what makes Uniquify unique. Perhaps this profile will encourage EDACafe readers to stop by Booths 1941 and 615 during DAC to see Uniquify for themselves.

When EDACafe last looked in on Forte Design Systems in September 2012, writer Russ Henke learned from its founder and technical visionary John Sanguinetti, “Patience and fortitude really do characterize Forte. We’ve kept at it and appreciate our success.”

So it does. As the industry heads into DAC, the news from Forte, exhibiting in Booth #1547 June 3-5, is great. Really great, in fact.

First, Gary Smith EDA conferred the ranking of #1 provider of electronic system-level (ESL) synthesis software at the end of last year. No small feat and no matter that Forte prefers to call its software category high-level synthesis (HLS), it bested a market segment that included three other vendors. This is a huge win and a validation of everything the company’s done since it launched itself at Forte in 2001. (EDACafe readers will remember that Forte is the merger of CynApps and Chronology.)

Next, Forte’s on Gary Smith EDA’s What to See at DAC 2013 List and for good reason. EDACafe readers who stop by the Forte booth will be offered demonstrations of the newly launched Cynthesizer 5 SystemC high-level synthesis, perhaps the most important Forte announcement in years.

For those readers unfamiliar with Forte’s Cynthesizer, it automatically creates high-quality RTL design implementations for ASIC, SoC, and FPGA targets from a high- level SystemC/C++ description. Cynthesizer’s proven successes in hundreds of production designs around the world are testament to its consistently high quality of results, mature feature set, and complete design coverage. The latest version has low power synthesis capabilities, increased performance and capacity across the entire tool and includes core synthesis algorithms, and a new SystemC IDE. Brett Cline, Forte’s vice president of marketing and sales, can’t help but be proud of the new tool and the team that built it: “Cynthesizer 5 defines the next generation of high-level synthesis technologies. We leveraged more than a decade of production design experience to allow design teams to get to better results more quickly. Cynthesizer continues to lead the way for quality of results and now includes several advanced optimizations for low power design.”

From the news release dated May 14: Cynthesizer 5 includes Forte’s new “C5” synthesis core, introducing a new architecture that combines the scheduling and allocation phases of the tool, improving predictability and quality of results. New scheduling algorithms allow Cynthesizer to quickly test multiple design microarchitectures and schedules to find the best possible area, performance, and power based on the designers constraints. For existing users, the new C5 core improves area results 9% on average compared to previous Cynthesizer releases. The full news release can be found at: http://www.forteds.com/news/pr20130514.asp

Back at the Forte booth, CellMath Floating Point IP will be demonstrated, too. Design teams from all over the world are standardizing on Forte’s CellMath IP for GPUs, FPUs, and SIMDs due to better performance, area, and customizability. Beer will be served Tuesday from 3 until 6 p.m. If you haven’t made it to the Forte booth before then, stop by to greet John, Brett, Sean Dart, Forte’s president and chief executive officer, Matt Marshall, Mike Meredith, Dave Pursley and the rest of the Forte crew.

Here’s the Forte team from last DAC. Sean Dart is third from right, John Sanguinetti is sixth from right. Brett Cline is third from left.

To see all the great new features and benefits of Cynthesizer 5 or the latest CellMath Floating Point IP capabilities, schedule a personalized demo during DAC through: www.ForteDS.com/dac2013. Also, Forte will highlight the work of high-level SystemC IP provider Adapt-IP as well as a joint flow with Ansys’ Apache on low power.

Forte’s in the DAC technical program as well. Cynthesizer users from NTT in Japan will offer a look at how they deployed the tool during a presentation titled, “Parallel Design Methodology for Video Codec LSI with High-Level Synthesis and FPGA-Based Platform,” during Designer Track Session #8. It will be held Wednesday, June 5, from 1:30 p.m. until 3 p.m. in Room 18C.

While it’s too late to take advantage of “I Love DAC”, a way for DAC attendees to get free three-day exhibit floor passes, it’s worth noting that Forte’s a sponsor this year of the popular program. Thanks, Forte!

Forte’s a sponsor this year of the popular I Love DAC program.

Let’s backtrack a bit to January when Forte impressively reported that 2012 was its seventh consecutive year of revenue growth. Sean Dart noted in a prepared statement, “Our commitment to high-value software and top-notch support was validated in 2012 as we moved into the #1 slot for ESL synthesis. We’re looking forward to building upon this success with continued growth forecast for high-level synthesis and our intellectual property offerings for 2013.”

This success translated into a remarkable 22% growth in 2012 and the addition of new HLS users in Europe, Japan, Korea, Taiwan and the United States, many of whom were using competitive C-synthesis products. Cynthesizer was deployed more widely in several large semiconductor companies throughout the U.S., Korea, and Japan. Forte’s IP businesses has been expanding as well as design teams implemented the IP into GPUs and custom processors.

One of the new customers is LG Electronics from Seoul, Korea, who is using Cynthesizer for its next-generation DTV design project. After evaluating several HLS software tools, LG selected Cynthesizer for its notable productivity improvements, including faster turnaround time and better QoR over handwritten code, and its ability to reduce power consumption. View the news release at: http://www.forteds.com/news/pr20130515.asp

Forte will host DAC’s closing with a bagpiper’s performance Wednesday, June 5, at 5:50 p.m., a tradition Forte’s kept alive and a fitting end to our profile. EDACafe readers need patience and fortitude to make it through three days of DAC, but will want to stick around to the end and head over to the Forte Booth #1547 for the return of the bagpipers.

How is it that an EDA tool is old enough to celebrate its 20 birthday and still be popular and well used? The tool is advanced device modeling software and part of the unusual story of ProPlus Design Solutions.

ProPlus is a company with deep roots that go back to its founding as BTA Technology in 1993, a merger with Ultima in 2001 to what became Celestry and an acquisition by Cadence in 2003.

Come along with me as we take a circuitous journey to the company with loads of talent and loads of accomplishments that became ProPlus.

A Long and Storied History
Any tale about ProPlus must start with Dr. Zhihong Liu who holds Ph.D. degree in electrical engineering from the University of Hong Kong. In the early 90s, he came to the U.S. to study with Professor Chenming Hu at the University of California at Berkeley as a research fellow. (Professor Hu is an active member of the ProPlus board of directors and is this year’s recipient of the Phil Kaufman Award.)

Zhihong Liu is Executive Chairman of ProPlus Design Solutions.

Professor Chenming Hu is an active member of the ProPlus board of directors and is this year’s recipient of the Phil Kaufman Award.

At Berkeley, Zhihong co-developed BSIM3v3 that became the industry standard model for IC designs in 1995 and still widely adopted today. As a co-founder of BTA, he served as vice president of engineering, assuming the role of president and CEO in 1995. He led the development of the industry’s golden device modeling platform, the BSIMPro product family, employed by all the leading foundries and semiconductor companies even today.

As an EDA player growing in stature, BTA Technology merged with Ultima and formed Celestry in 2001. Celestry was noted for its UltraSim fast circuit simulator and the Nautilus full-chip verification suite with signal integrity, delay calculation, and RC extraction. DAC attendees may remember the Celestry booth crew dressed one year in white lab coats with stethoscopes around their necks.

Then came the Cadence acquisition in 2003. As the Celestry team assimilated into Cadence, it became clear that the companies’ products, visions and, perhaps, philosophies didn’t gel as well as expected. Cadence wanted a fast simulator, which it got. Celestry’s goal was to make device technology more accessible to designers, bridging the gap between device physics and design.

After a few years with Cadence, the core engineering team bought out what had been Celestry, including a majority of its products and customers, in 2006 with Cadence’s blessing to create ProPlus. Zhihong, who was corporate vice president for CSV R&D at Cadence, served as the board chairman since its founding and joined in 2010.

ProPlus Today
Device modeling has served as the foundation of ProPlus’ expanding tool suite and continues to do so. As Zhihong explains, ProPlus saw an opportunity to expand its business by building a seamlessly integrated design for yield (DFY) solution. In addition to device modeling, it includes hardware-validated statistical variation analysis and the parallel SPICE circuit simulator known at NanoSpice introduced in early April.
Dr. Bruce McGaughy, ProPlus’ talented chief technology officer and senior vice president of engineering, managed the team responsible for this next-generation high-capacity, high-performance parallel SPICE simulator for giga-scale circuit simulation. Bruce is another member of the original core BTA Technology team and most recently served as the chief architect of Cadence’s Simulation Division.

Bruce McGaughy is chief technology officer and senior vice president of engineering, and manages the team responsible for NanoSpice.

ProPlus now employs about 150 people, 100 of whom are part of the R&D team in China, while 30 work from its U.S. headquarters in San Jose, Calif. The others work in various regions throughout Asia. Of those 150 employees, about 30 are long-time veterans of BTA, Celestry, Cadence and now ProPlus, an unusual feat in any industry and just about unheard of in EDA.

Here’s part of the ProPlus team that works in San Jose, Calif.

Here’s a photo of the ProPlus team in Beijing, China.

Not all 150 employees of ProPlus will be at DAC this year in Austin, Texas, but many of them will be, ready to take attendees on a journey “From Nano-Scale Modeling to Giga-Scale Simulations.” The entire DFY product portfolio will be demonstrated in Booth #1525 and there might be a birthday cake for BSIMProPlus, the 20-year old modeling platform for nanometer devices. Over the three days of DAC, attendees will learn about:

Newly introduced NanoSpice and its ability to handle 100-million+ element designs. It is the core engine of BSIMProPlus

ProPlus will celebrate BSIMProPlus’ 20th anniversary, its new products and DAC’s 50 years of innovation as a contributing sponsor of Kickin’ it Up in Austin and host a daily drawing in its booth for an iPad mini and Samsung Galaxy Tab 2.

The accomplishments continue. Zhihong led a development team that produced the 9812D noise measurement system, delivering high accuracy, 10-megahertz (MHz) measurement bandwidth and increased measurement throughput over the decades old 9812B, another ProPlus industry golden standard for 1/f noise characterization.

Savvy EDACafe readers may wonder how 9812B is obsolete while BSIMProPlus modeling platform is useable and quite widely deployed. According to Zhihong, BSIMProPlus is being constantly enhanced and improved upon.

ProPlus hosted two other webinars within the last six months, including, “Giga-Scale Parallel SPICE Simulator taking Pure SPICE Capacity to the 100M+ Element Level.” The other addressed “Advanced Yield Analysis and Optimization with 3-6 Sigma Statistical Simulations for Memory, Logic, Digital and Analog Designs.” Both can be found at: http://tiny.cc/ijg1ww.

The goal to bridge device manufacturing and IC design is being met by the ProPlus team and we likely can expect another 20 years of accomplishments. Don’t just take my word on ProPlus. Stop by the ProPlus Booth (#1525) to see for yourself how its developed a complete suite of DFY tools all integrated together.

During a team-building day in China last year, a banner is unfurled to celebrate pursuing excellence, achieving another success.

P.S.: Zhihong worked with the DAC Pavilion Panel Committee to organize a pavilion panel titled, “Learn the Secrets of Design for Yield,” moderated by Pete Singer, editor in chief of Solid State Technology. It will be held Wednesday, June 5, from 1:30-2:15 p.m. on the exhibit floor in Booth #509. Panelists are: Dr. Min-Chie Jeng of TSMC, Dr. Luigi Capodieci with GLOBALFOUNDRIES, and Dr. Shaofeng Yu from SMIC.

]]>0Nanette Collinshttp://www10.edacafe.com/blogs/dispatchesfromboston/?p=192013-05-10T15:09:17Z2013-05-10T02:00:05ZCarbon Design Systems was founded in 2002 and will be at this year’s DAC exhibitor in the ARM Booth (#921). The story picks up from here with Bill Neifert, Carbon’s co-founder who serves as chief technology officer and vice president of business development, and CEO Rick Lucier, who’s been at Carbon since 2006.

Carbon, Bill and Rick explain, recorded the sixth consecutive year of growth at the close of 2012. They attribute this to 14 new customers, all of whom recognize the need for fast virtual prototypes with a path to 100%, the solution Carbon is known for.

Rick Lucier is Carbon’s CEO.

Bill racked up 125,000 United Airlines frequent flier miles getting that business closed and claims to have seen “The Bourne Legacy” eight times traveling between continents. He’s wised up since then and loads his iPad with TiVo downloads for the numerous flights he taken already this year.

Bill Neifert is a Carbon co-founder. He’s now CTO and vp of business development.

Virtual prototyping is a trend moving through the design community. For those of you who don’t know what a virtual prototype is, here’s the Wikipedia description: Virtual prototyping is a technique in the process of product development. It involves using CAD and CAE software to validate a design before committing to making a physical prototype.

Bill and Rick explained that companies are adopting Carbon Performance Analysis Kits (CPAKs) introduced last year, pre-built, easily extensible virtual prototypes. While CPAKs sound like a political action committee, they are actually packaged with bare-metal and O/S software to enable rapid user productivity and cut the time needed to be productive with virtual prototypes. More than 30 CPAKs are available from Carbon’s IP Exchange web portal (www.carbonipexchange.com) and feature cores from partners ARM, Arteris, MIPS and Cadence.

Another highlight from 2012 is a $4 million strategic investment from Samsung that’s now in use as working capital and supports Carbon’s ongoing development of ESL tools, another indication of the trending toward virtual prototypes.

Rick says: “We’ve seen a strong uptick in demand from design teams seeking virtual prototypes with a connection to accuracy. Our 100% accurate models give us the unique capability to solve this growing demand, while also offering the capability to execute that same virtual prototype at the speeds needed by software developers.”

Joe Tatham, vice president of engineering, at left and engineering director Matt Grasse hold an informal discussion in Joe’s office.

Bill interjects here to explain that design teams have been led to believe they need to choose either performance or cycle accuracy when employing virtual prototypes. That, he says, is what sets Carbon apart because it has removed the tradeoff for designs. They can have it all!

It’s interesting to note that Carbon is bucking the EDA trend by being located in Massachusetts but then, these are hearty New Englanders. Acton, where it’s located, is a suburb of Boston 21 miles away. Its closest neighbor in Concord, a town that’s the home of Walden Pond, the American Revolution and authors Henry David Thoreau, Louisa May Alcott and Ralph Waldo Emerson.

A few of Carbon’s engineering team grabbed a conference room for a meeting.

To get to Carbon, visitors coming from Boston need to circle a rotary right beyond Concord State Penitentiary, an inauspicious route, to be sure. But once there, it’s an oasis for Carbon is tucked into a picturesque office park just off Rte. 2 in Acton, the busy main drag.

Carbon’s corporate headquarters is in Nagog Park in Acton, Mass.

I’d be remiss if I didn’t mention Carbon’s vice president of marketing and sales is EDA long timer Hal Conklin.

Hal Conklin, vice president of sales and marketing, responds to email.

As our conversation draws to a close, Bill and Rick confirm that Carbon will have more announcements focused on accuracy, speed and system-level design. It seems fitting to quote Thoreau, who wrote, “This world is but a canvas for our imagination,” in A Week on the Concord and Merrimack Rivers (1849).

]]>0Nanette Collinshttp://www10.edacafe.com/blogs/dispatchesfromboston/?p=62013-05-04T20:32:21Z2013-05-03T21:48:41ZThe design and EDA communities have been preping since last June for DAC’s 50th anniversary to be celebrated in one notable high-tech city, Austin. The program’s been posted, keynotes announced and everything’s coming together nicely. The exhibit floor will be filled once again with a mix of new companies, long timers and emerging companies.

Over the next several weeks this blog will be dedicated to a few of this year’s DAC exhibitors, all of whom are emerging companies reporting growth, new customers and products and momentum. We’ll start with an impressive story about Verific Design Automation, a company that hails from a small town across the Bay from San Francisco called Alameda.

DAC attendees who wander the exhibit floor must have passed by the Verific booth –– this year, in Booth #2141 –– a time or two and noticed that a giraffe serves as its mascot. You may have walked away with one of its plush giraffe giveaways, or entered your name into a drawing to win the large, stuffed giraffe on display. Attendees who look more closely will see a tagline that reads, “Head and Shoulders above the Rest.”

The Verific Team at DAC in June 2012 included, from left to right: Rob Dekker, Rick Carlson, Hoa Dinh, Michiel Ligthart, James Johnston, Abhijit Chakrabarty and Rajat Mukherjee.

Well, ask anyone at Verific about this and you’ll soon discover that its founder and several of its employees are well over 6’tall in stature. Crane your neck a bit and discover that “Head and Shoulders above the Rest” also refers to a well-regarded, well-respected company providing SystemVerilog and VHDL parsers to well over 50 companies and counting in the semiconductor ecosystem … EDA, FPGA, IDMs. In 2012 alone, Verific signed six new licensed customers, while several existing customers added further software to their existing product mix. What’s more, Verific reported a 2012 revenue increase of 20% over 2011.

Verific unveiled a Perl interface to SystemVerilog and VHDL parsers and elaborators at last year’s DAC.

As we talk over coffee one afternoon, Michiel Ligthart, Verific’s president and chief operating officer, chuckles about using a giraffe as the company mascot. He gets serious when describing Verific’s success: “Much of our business comes as a result of our reputation for quality, reliable software and excellent customer service, the hallmarks of our corporate culture. EDA developers continue to select our parsers so that they can focus on their core competencies and get their products to market more efficiently.”

Rob Dekker is Verific’s founder who stands tall in HDL circles and his vision has made Verific the go-to company for SystemVerilog and VHDL parsers since 1999. The software is found in more than 40,000 copies of analysis, simulation, verification, synthesis, emulation and test tools for RTL design. Today, Rob continues as principal developer of Verific’s HDL source code software. Prior to founding Verific, he was at Exemplar Logic, now Mentor Graphics, serving as the architect and a primary developer of Leonardo, a synthesis product that has sold more than 10,000 copies.

No article about Verific would be complete without a mention of industry giant Rick Carlson who ably serves as vice president of sales, and seemingly knows everyone, even from an outpost in Colorado. What you may not know about this well-liked executive is that he founded the EDA Consortium in 1987. Don’t miss an opportunity to hear the full story from him when you stop by the Verific booth.

Michiel Ligthart (left) and Rick Carlson huddle at last year’s DAC.

Speaking of this year’s DAC, Michiel said that the Verific theme again this year will be “Build Your Own RTL Tools.” It’s a nod to CAD managers and SoC designers who have a hankering to build one-of-a-kind EDA applications they cannot get from mainstream EDA companies. The tool came as a result of designers who need to solve a specific problem in their RTL code or netlist. “They aren’t C++ programmers and they would prefer to put a solution together using a scripting language so we extended our regular parsers with a Perl API.”

The connections to giraffes continue. In early 2012, a baby giraffe named Maggie was born in the Oakland Zoo in Oakland, Calif., the next town over from Alameda. Being close in proximity, Verific donated $1,000 to the zoo’s Adopt-an-Animal program.

James Johnston and friends share a DAC moment.

As I closed my notebook on our conversation, I think that it’s quite impressive how a sizable part of EDA came to rely on a small company. Michiel interrupted my train of thought to mention that a Verific user once said: “Verific is Giraffic!” That just about sizes up Verific, doesn’t it?