Better modeling is the need of the hour. Each interconnect need to be modeled as transmission line, but too many such things to handle!

Every CAD tool vendor now is talking about noise analysis, IR drop calculation. Design flows need to address this, if possible prevent or at least fix once the problem surface.

2. Power

With Oxide thickness decreasing 10 nm in 90 nm technology and expected to touch one molecular layer of oxide (0.2 nm approx.) leakage power is going to play an important role, if not playing already. Gate leakage current density is increasing beyond 1A/cm 2 at 3.0V in 22A 0 thickness. In addition to rapid increase in leakage power, dynamic power is also increasing with the increase in frequency of the device. With this kind of increase in power dissipation, packaging the device is a real challenge, in spite of all measures to control the power.

Some of the well discussed measures to control power:

Creating voltage islands.

Optimizing the designs using dual Vt.

Back bias technique.

Power management.

SOI

Strained Semiconductor

Note: As the contribution of leakage power to the total power is increasing, Dual Vt (or even tri-Vt) can be very effectively used. We can restrict the low Vt cells only for the critical paths and use high Vt cells for the remaining. (If 100,000 gates consumes 25 mW as leakage power using low Vt, it can be reduced to 1.5 mW using high Vt.)

3. Complexity of the design

Chip complexity is increasing with decreasing individual device dimensions. If usable gates in 12mmX12mm silicon area with 130 nm technology were 10 million gates, it is 90 million gates in the same silicon area with 65 nm technology. Imagine its impact on data base size! With more issues to handle in 90nm and beyond, data base can get only get complicated! This is a big challenge to EDA tools and the design managers:

Make the data base effective to handle the complexities.

Use the estimation and prevention based design flow rather than iteration based flows.

Standardized IP interfaces and less dependence on in-chip verification.

Address the validation and interface issues at architectural level.

4. Packaging and Testing

Most of the designs using DSM technology are SOCs with multiple IPs. Testing them can be a time consuming affair. DFT is a must and go beyond scan chains. We can add logic BIST and this will add to the complexity.

5. NRE Cost

Technology cost because of increased complexities in mask making and fabrication. This increases each spin. This makes the programmability of the IPs to bypass the soft bugs and make the chip testable as mandatory.

Man hour cost: With the design and validation task is increasing exponentially, each iteration of Search- fix-Validate cycle can become expensive and prohibitory. This issue needs to be addressed at “design flow” level.

Cost of the CAD tools: As issues like power distribution, signal integrity, cross-talk are becoming main stream problems cost of Design Automation tools and computing requirements can increase the total cost.