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AR# 52124

MIG 7 Series DDR3/DDR2 - Synplify fails due to DQS parameters

Description

The MIG 7 Series DDR3/DDR2 designs will fail in Synplify with errors similar to the following:

@E: CG596 :"/user_design/rtl/phy/mig_7series_v1_7_ddr_mc_phy_wrapper.v":1185:14:1185:21|Parameter DQS_BIAS cannot be found in module IOBUFDS_DCIEN.

or

@E: CG596 :"/user_design/rtl/ddr3_sdram/phy/mig_7series_v1_8_ddr_byte_lane.v":435:3:435:18|Parameter DQS_FIND_PATTERN cannot be found in module PHASER_IN_PHY.

Solution

These errors occur because between ISE design tools 14.2 and 14.3, the DQS_BIAS I/O feature changed from an attribute on an I/O primitive to a parameter on an I/O primitive. This change is nowreflected in the Synplify FPGA 2012.09 overlay patch and will be included into the official release of Synplify FPGA G-2012.09-SP1.

The overlay update can be downloaded at the bottom of this answer record.

Note: When this overlay is applied, critical warnings may be seen in Vivado implementation similar to the following:[Netlist 29-73] Incorrect value 'UNDECLARED' specified for property 'OSERDES_DATA_WIDTH'. The system will either use the default value or the property value will be dropped. Verify your source files. ["/proj/ipmig/mig_7series_v1_8//test10_ddr3_ver_synp/example_design/par_vivado/project_1/project_1.srcs/sources_1/imports/rev_1/example_top.edf":44124]

These critical warnings can safely be ignored.

If the overlay file cannot be used, then the following workaround can be used to bypass the error message.

Synplify Flow Work-around:

1. Open the user_design/rtl/phy/mig_7series_v1_7_ddr_mc_phy_wrapper.v module.2. Make the following edits:

Note:These updates cannot be made for simulation because the Xilinx models require the DQS_BIAS I/O parameter. The file originally generated by MIG 7 Series v1.7 must be used for simulation.

In the ISE 14.4 release, the same situation occurs with the DQS_AUTO_RECALL and DQS_FIND_PATTERN attributes in the ddr_byte_lane module. Between 14.3 and 14.4 these changed from attributes to parameters. A similar workaround can be made to the mig_7series_v1_8_ddr_byte_lane.v module: