By "we", please tell me if it has anything to do with the chipset and
mainboard code.
Zheng
-----Original Message-----
From: Myles Watson [mailto:mylesgw at gmail.com]
Sent: Tuesday, November 10, 2009 11:31 AM
To: Bao, Zheng; coreboot at coreboot.org
Cc: 'Carl-Daniel Hailfinger'; 'Stefan Reinauer'; 'Marc Jones'
Subject: RE: [coreboot] [v2] r4925 makes my linux hang
> Log from r4924.
The problem is that the video card gets treated as if it were part of
the
RS780. In many chipsets, there's a check to see if the device is really
part of the chipset before it is initialized using the chipset
functions.
rs780_enable: dev=000231dc, VID_DID=0x96151002
Bus-0, Dev-4,5,6,7, Fun-0. enable=1
gpp_sb_init nb_dev=0x000202f0, dev=0x000231dc, port=0x00000005
PcieLinkTraining port=5:lc current state=0
PcieTrainPort port=0x5 result=0
PCI: 01:05.0 [1002/9615] ops
Maybe we need some way to say "use the default" still? chip default_ops
or
something?
Thanks,
Myles