[WHOOSH] Hello. My name is Denislav Petkov, and I'm the Applications Engineering Manager in the Power Modules team at Texas Instruments. Today, we'll talk about understanding, measuring, and reducing output noise in DC-to-DC switching regulators. Here's the agenda for the presentation.
The first part of the presentation will focus on understanding the noise origin and how to properly measure it. We will look at the relevant parasitic elements, high-frequency and low-frequency components of the noise. Then, we'll look at some measurement techniques, along with examples from the bench. And we'll discuss some noise reduction techniques with board layout and component placement.
We will also look at having parallel capacitors of different types and their effect on low-frequency noise reduction. And we'll follow with taking a look at filtering techniques using two different approaches. We'll look at second-stage LC filters and LDOs. Both of these will include examples, and we'll look at the trade-offs of each of these methods.
Let's get started. And with this, let's start with the ideal world. This, as you know, is the buck regulator. It is fairly simple. And here, we have an input source, an input bypass capacitor, two switches-- high side and low side-- an inductor, an output capacitive, and a load.
The two switches chop the input voltage with a particular duty cycle. And the inductor and the output capacitor average out this chopped waveform to result in an output voltage equal to Vin times this duty cycle.
In reality, there are a few more components that come with the buck regulator in the form of parasitic elements. Those are free. But most of the time, these free components are not wanted. There are parasitic inductances associated with the package. The input capacitor and its placement also result in additional parasitic elements.
There's parasitic inductance in series with the high side and low side switches. And there is a high di/dt loop on the input side of the converter. There are parasitic elements associated with the inductor, as well, and also with the output capacitor. So most of the noise problems customers and engineers experience with switching power supplies are related to those components shown in red here, the ones that show up in the design as parasitic elements.
Let's take a look at the output of a buck converter. If we zoom in on the voltage with our oscilloscope and have sufficient bandwidth, we will notice two distinct shapes. There is voltage spikes with relatively high frequency and also a low-frequency ripple at the converter switching frequency. The low-frequency output voltage ripple of the converter is a result of the ripple current in the inductor going through the output capacitor impedance.
And as we know already, the output capacitor is not just a capacitor. It comes with parasitic inductance in equivalent series resistance. So the total low-frequency peak-to-peak voltage ripple on the output is a function of the total output capacitor impedance, which, again, has ESR capacitance and ESL. We will take a look at this in a little bit more detail. But let's first take a look at the high-frequency spikes and where these spikes come from.
So here's the output of the buck converter again. In this case, we're focusing on the high-frequency spikes at the edges of each switching period. So where is this noise coming from? This noise is generated by the high di/dt current and any inductance in its path.
And for a buck converter, the high di/dt loop is on the input side of the regulator. For a boost converter, the high di/dt loop would be on the output. So any parasitic inductance in series with this high di/dt current will result in voltage. And these voltage spikes will appear on the switch node as high-frequency ringing.
Now, the switch node gets polluted with these high-frequency spikes. But how do they show up on the output? Again, we have an inductor there, so that should be able to block some high frequency. Well, it turns out that there are parasitic capacitances from switch node to the output, mainly through the inductor, and also through our board layout.
So the capacitance across the inductor could be a few picofarads to a few tens of picofarads, depending on the inductor we're using. And also, the switch node copper in the board layout may be overlapping with another layer, resulting in some parasitic capacitance there.
So for example, some layouts will have dedicated power planes for the output voltage. And if there is a switch node copper overlap with sufficiently large area, that could be a parallel plate capacitor, which could be ready to couple this high-frequency noise to the output.
Before we explore ways for reducing the output noise, let's make sure we're measuring it properly. Why do we care about the measurement so much? Well, improper measurement techniques can result in exaggerated output noise. And exaggerated output noise measurement can result in overly aggressive methods for fixing it. So it's important to know the real amount of noise that we're dealing with before we start to see how we can reduce it.
Here's a good example of a bad measurement technique. Here, we're trying to measure the output of a buck converter with our typical scope probe. And you can see that the ground wire of the scope probe can form a nice loop antenna. And this would definitely pick up additional noise from the inductor here. And it would pollute our measurement with huge spikes.
A better way to take the same measurement is to improve the ground wiring of the scope probe. And one way to do it is to wrap around a ground wire around the barrel of the probe. And this will result in much smaller loop area of the ground connection here. And this will also result in much cleaner measurement. Here's an example.
In the top wave form, from this scope shot, we're measuring the output noise using a large ground loop of the oscilloscope probe. And in this case, we're picking up 200 millivolts, peak-to-peak, of high-frequency noise. With improved grounding of our scope probe, the measurement is actually 100 millivolts peak-to-peak. Now, this is 2x difference in measured noise. And we know that the circuit is exactly the same, and the difference is only how we measure it.
So let's assume that the application in this case required 75 millivolts of ripple or high-frequency noise. If we used the first measurement, we would think that we're way off from the target, and we'll need a lot of filtering to achieve the target. And in the second case, or second measurement, we'll see that we're actually much closer to, let's say, the 75 millivolt target, and we don't need as much filtering to get there.
Now, some engineers may want to improve this measurement further. And one way to do this is to get yourself a 1x probe. Here is one way to make a 1x scope probe. A short piece of coax cable can be soldered directly to the measurement point.
There is an AC coupling capacitor and an external 50-ohm termination resistor at the oscilloscope channel. The capacitor, a 0.1 microfarad, in this case, and the 50-ohm termination form a cutoff frequency at 31.8 kilohertz. And this cutoff frequency for this high-pass filter, basically, is suitable for the full switching frequency for most modern regulators.
And from the frequency response of the probe, we see that it's pretty flat up to 200 megahertz. So this would be useful for, or suitable for, measurements for up to let's say, 200, 250 megahertz bandwidth on the oscilloscope.
Now, because the cutoff frequency is around, let's say, 32 kilohertz, it's important to know the switching frequency of the converter. If you're operating at light load and the converter goes into some sort of power savings mode, the switching frequency may reduce. And we want to make sure that it's not below this cutoff frequency. Otherwise, our measurement will be, essentially, attenuating some of this noise. And we will not get the correct results.
Also, if we're trying to measure load transient peak-to-peak ripple, again, this probe may not be suitable for this case. Because the load transient may be at a lower frequency, where it would start attenuating. But for most modern switchers with a loaded output that operate in this frequency range here, this probe should be very good.
Here is an example measurement taken with a 1x probe. We have the 1x probe on top and a 10x probe on the bottom. We can see that with a 1x probe, we can get a much cleaner reading, and we can actually zoom in to one millivolt per division if we want to take some sub-1 millivolt measurements. So this may be a really good approach of measuring output noise.
Let's look at ways of reducing the low-frequency ripple component of our output noise. Just to remind ourselves what we're trying to reduce, here's the output of the buck converter again. And this low-frequency ripple is what we're trying to reduce in this case.
As we know now, the low-frequency ripple is a function of the inductor ripple current and the output capacitor impedance. So based on the capacitor type, the ripple on the output can look quite different. Here's an example on the left, where we have different output ripple wave forms using the same 47 microfarad capacitance, but we're using capacitors of different type.
On the top, we have a ceramic capacitor, which usually comes with very low ESR and ESL. In red here, we have a tantalum capacitor of the same value-- 47 microfarad-- but it has a little bit more ESR and some ESL, and the ripple is larger.
Further down, in light blue here, we have all OSCON capacitor-- again, a 47 microfarad cap. And that capacitor has, let's say, medium levels of ESR and some more ESL. And you see that the ripple is slightly more. And on the bottom, we have an example with a aluminum electrolytic capacitor, which has a lot of ESR. And you see that the ripple is quite a bit higher in this case.
So the type of capacitor can definitely affect our low-frequency ripple on the output. And it's really important to focus on the parasitic components of the capacitor to understand how much ripple we're going to get.
Some noise-sensitive application requires this ripple to be very low, and such examples like test and measurement applications, where you'd need a really, really clean output. So for those applications, engineers can choose to have a additional LC filter on the output. And in this example here on the right, we're using the LMZM23601 DC-to-DC module, which already has an inductor inside.
And we're pairing this up with a additional LC filter on the output. So C1 here is the output capacitor for the module-- normal output capacity that usually has to be placed on the output. L2 is the inductor for our second-stage filter. C2, C3, and C4, and the damping resistor here, form the entire filter.
So with this filter implementation, we're able to get 0.7 millivolts of peak-to-peak for this 5 volt supply, which is extremely low ripple on the output. And included in this slide, there is a spreadsheet calculator that will help you design an LC filter if you need to achieve really low ripple for the application.
We saw that the low-frequency ripple really depends on the output capacitor impedance. And different capacitor types will have different parasitic characteristics. So some designers may choose to mix capacitor of different types on the output of the converter.
Ceramic capacitors are great, as we saw here. But sometimes they're difficult to get, difficult to buy. And they may also run out of the capacitance at a particular application voltage. So it may make sense to parallel a ceramic capacitor with a bulk cap of some different chemistry so that you get, let's say, the best of both worlds. You get enough capacitance, and then you have low enough impedance to achieve low ripple.
But how much ripple will we end up when you have a parallel capacitance of, let's say, ceramic and aluminum electrolytic? If we know each capacitor's ESR, we can actually do some math and calculate the resulting effective capacitance and effective series resistance for our parallel combination. There's some equations here, and this slide also includes a calculator, which will take these equations into account and will show the effective capacitance and resistance for a parallel combination.
Here is what a calculator looks like when you open it. You can enter up to two capacitors here-- capacitor 1 and capacitor 2 specifications-- capacitance and ESR of the first capacitor and capacitance and ESR of the second capacitor. Then, you can enter the input voltage of the buck converter, the output voltage, the inductance in the switching frequency.
This portion here would basically calculate the ripple current for the particular condition. And considering the effective parallel combination of ESR and capacitance, the calculator will show you what low frequency ripple is, here on the bottom.
Here's an example of the low-frequency output ripple assuming 1 amp of ripple current and 100 microfarad out of electrolytic in parallel with different values of ceramic capacitance. Let's assume that the regulator switches at 500 kilohertz. Depending on the electrolytic ESR and if we have 2.2 microfarad of parallel ceramic, the low-frequency ripple will be about 85 millivolts, in this case, with this switching frequency.
With a 22 microfarad parallel ceramic, the ripple will be a little over 10 millivolts. And if we add more ceramic capacitor, up to 100 microfarad of parallel ceramic, we can see that the low-frequency ripple will go down in a few millivolts of total peak-to-peak. So this can give you an idea of how much ripple we can expect for a particular output capacitor parallel combination.
Let's look at ways of reducing high-frequency noise on the output of the buck converter. As a first line of attack, let's see what we can do with the component placement. One thing we can do is to try to minimize the area of the high di/dt current loop. A smaller area will result in smaller inductance.
And for a buck converter, we know that the high di/dt loop is formed on the input side of the regulator. So placing the input capacitor as close as possible to the IC will result in smaller loop and loop area. And that would result in lower inductance.
Smaller loop area will result in lower ringing on the switch node. And lower ringing on the switch node means lower output noise on the output of the buck converter. So a first step to minimize a high-frequency noise is to really optimize the input capacitor placement of a buck converter.
Many people don't realize this right away, but for a buck converter, the input capacitor positioning affects the output noise. This is something we always emphasize when we do layout reviews for buck converters. And the placement of the input capacitor is one of the most important things to look at for when we lay out a buck converter.
Here's an example. Here, we have a synchronous buck converter IC with the input cap placed a little bit farther away from the IC. And the high di/dt loop area here is highlighted in red. The input voltage for this converter is 12 volts. And we see that the switch node spike goes up to 18 volts with this particular capacitor placement. And the alpha voltage high-frequency noise peak-to-peak is 75 millivolts.
And on the right, here, we have a radiated EMI measurement. And we see that we're failing Class B specifications for this design. If we place the input capacitor a little bit better and reduce the loop area of the input capacitor near the high di/dt loop-- roughly two times smaller area in this case-- we see that for the same input voltage, now, the spike is at 14 and a half volts.
And our output noise-- so this is down from 18 to 14 and a half-- and our output high-frequency noise went from 75 millivolts to 47 millivolts peak-to-peak. And also, the EMI scan improved a little bit, compared to what we had before.
And note that, in this case, we did not spend any additional money to get this substantial improvement in output noise. We just placed the input capacitor of the buck converter differently than before and directly against the IC. And we got much better results. So this improvement was absolutely free. And it was only due to the proper placement of the input capacitor.
Now, power modules can really help with simplifying the board layout and keeping the engineers out of trouble. Now, how does this work? Well, for example, power modules that integrate some of the input capacitance can help you greatly reduce the high di/dt loop area. Some of this capacitance will be inside the module. And that would make the layout as optimal as possible.
Now, also, since the switch node is inside the module and is as small as possible, the potential parasitic capacitance from switch node to any other node in the circuit due to a board layout is quite limited. So as a result, you get less ringing and lower noise coupling to the output when you use power modules for design.
Here's an example on the bottom where one of the newer models that we've released is the LMZM33603. You can see that there is a input capacitor placed right against the internal IC in this case, and the high di/dt loop is very small. And we have a shielded inductor, and we have a minimal switch node that connects the IC just outside to connect to the inductor terminal and nothing excessive on the switch node area.
The IC package construction can also offer some advantages in reducing high-frequency noise. Some ICs are available in hot rod packages, which tend to reduce the package parasitics, which are usually in series with our high di/dt loop, and, therefore, can reduce the ringing on the switch node. Here's an example with our LMR33630.
This device is available in a standard QFN wire bond package. And it's also available in a hot rod package, where we flip the chip, and we have copper interconnects between the die and lead frame. As you can imagine, this results in a lot lower parasitic inductance. And if we compare the switch node for a wire bond version of the device and the hot rod version of the device package, we get a lot less ringing on the switch node and, therefore, lower output noise.
So the package construction can definitely help if noise is an issue. A hot rod-style package can be used in this case. The trade-off for a hot rod package is that getting the heat out of the die may be a little bit more challenging, and careful attention to layout is necessary, as with everything else.
Another way of reducing noise is to use a proper stackup on the board. In this particular example, we used a shooting technique, where we put the Vin-- the noisy Vin line-- and Vout on an inner layer-- mid-layer 2, in this case-- and we had a nice ground plane on top. Mid-layer, we didn't change.
The routing of Vin and Vout we moved to layer 3, or mid-layer 2, in this case. And the bottom layer was all ground. So you can see that we're basically sandwiching this noisy line and Vout between ground planes in our stackup. So the build materials is exactly the same. The difference is the stackup and the routing.
And we went from having this bump at high frequency and failing this EMI spec here to removing this bump with the improved stackup and now passing this Class B specification for a radiated EMI. So again, no change in the build materials. It's just the stackup of the PCB layers. And that led to passing EMI, as opposed to failing here at the high frequency.
Adding an input filter to the buck converter can also help a lot with radiated noise. Here is one example of how an input filter for a conducted EMI actually reduced the radiated EMI, as well. The input filter is usually a pi filter, where this would be the input of the buck converter. You have a capacitor for damping with some ESR and you have a L and a C that will clean up any generated noise and not allow it to go back on the input line.
So you see without the filter, we're getting a failure here. And with a filter, cleaning up the Vin-- the noisy Vin-- line, we're passing very easily this EMI spec. There's a quick calculator embedded in this slide that will help you design an input filter if you need to do that in your application.
So after careful layout, careful capacitor placement, looking at a stackup of the PCB, and doing all the best practices, at the end of the day, we're going to end up with some output noise, which would have a high-frequency component in it. We'll get some spiking, no matter what, because we cannot completely eliminate parasitic inductances and high di/dt loop and parasitic capacitance to couple noise to the output. So what can we do to further reduce this high frequency noise?
Well, one thing we can try to do is perhaps choose a high-frequency capacitor that would improve our output capacitor impedance at this high frequency. So in terms of high frequency, what do you think is better? Is it better to parallel our main capacitor with one microfarad-- let's say in 0.1 and 0.01-- or use the same value of high-frequency capacitance several times?
I've seen both approaches applied to designs. And the answer is it really depends. It depends on the frequency of the signal we're trying to filter and the overall frequency response, or impedance, of the capacitor combination. Let's look at some examples here.
Here's why I say it really depends. Here's an impedance curve of the three configurations we just looked at. We see that at high frequency, the additional parallel capacitors-- high-frequency capacitors-- can add valleys of impedance, which is great. That means low impedance, and we can filter the noise in this frequency. But they also, unfortunately, add peaks at different frequencies here.
So these resonant peaks can really affect the performance of this output capacitance combination. You see that if the noise that we're trying to filter fell into this range, the addition of this high-frequency capacitance is actually going to make things worse than what we would have had if we just stuck with one 10 microfarad capacitor.
So it really depends on the frequency of the noise we're trying to filter. And this plot was generated through simulation of different capacitor parasitic values. And there's a quick simulation file that you can use, again, embedded here in this presentation if you want to do a similar analysis.
Here's an example. In the first wave form, we had a 22 microfarad ceramic capacitor. And we measured on the board 76.2 millivolts of peak-to-peak high-frequency noise. We said, OK, well, let's filter this high-frequency noise. We'll put 220 pF ceramic capacitor in parallel with a 22.
And that actually made things worse. Why? Because the overall impedance at this ringing frequency was actually worse with this capacitor combination. We got a peak in impedance instead of a valley. Changing this capacitor to 470, in our case, moved that resonant peak, and it ended up with better overall impedance at the ringing frequency than one capacitor here.
So you see that if you pick the wrong capacitance value for the high-frequency cap, you can actually make things worse. So it's important to actually know what noise we're trying to filter and what kind of overall impedance we're going to get with the parallel combination.
Many power engineers may choose to use some sort of a second-stage filter, or an LDO, at the output of the switcher to clean up the voltage rail. Second-stage filter is a low-pass filter, and it's designed to attenuate really high frequencies. And with the LDO approach, we're basically aiming to utilize the power supply rejection characteristics of the LDO to basically reject the noise here and produce a really clean output.
Let's look at both of these approaches in a little bit more detail and see what we have in terms of benefits and trade-offs for each approach. Let's look at the second-stage LC filter approach of reducing output noise. Here is an example of a second-stage LC filter.
On top here, we have ideal LC filter. And as you've probably guessed already, in real life, we don't have an ideal LC filter, so we do get some parasitic components around the inductor, namely DCR of the inductor and parasitic capacitance across. And then, we also get ESL and ESR of the output cap. And we also have a damping resistor, which also will have some parasitic inductance in series and some capacitance.
So these parasitic components will result in, actually, worse attenuation of a LC filter at high frequency. In blue here, we have the ideal LC filter response. In red, we have LC filter with some parasitic components. And in green, we have LC filter with a ideal damping resistor. So as we can see, depending on the frequency we're trying to filter, these parasitic components can affect our attenuation at the high frequencies.
Here is some more detail on the LC filter parasitics. The inductor comes, actually, with a parallel capacitor. And this parasitic component can be calculated from the self-resonant frequency spec of the inductor. The output capacitor, as we already know, comes with small ESL, or parasitic conductance. So these parasitic components-- the parasitic capacitance and parasitic conductance-- actually start to have a negative effect on our filtering performance at a high frequency.
And you can see that in the plot to the right, where we're showing ideal LC attenuation and attenuation of a more real LC filter, where the capacitor's self-resonant frequency starts to kick in here. This is the inductor self-resonant frequency, and this is the capacitor ESL and the parasitic capacitance across the inductor.
So depending on the frequency we're trying to filter, you can see that at high frequencies, we may be losing quite a bit of attenuation. And we may even be making things worse here with these peaks. So if high-frequency attenuation is of interest, it may make sense to pick an inductor with better SRF spec. And by better, I mean higher SRF frequency.
This would mean that the inductor has lower capacitance across it. And the attenuation in high frequency would be slightly better than, comparing it to an inductor with lower SRF. In this case, we're comparing inductors from the same inductor family. But 10 times smaller value here would give us a better high frequency attenuation.
Again, this comes at a trade-off, where your LC filter product, if we're trying to keep that the same-- which is this corner here-- if we're using 10 times smaller inductance, we will need to use 10 times bigger capacitance. So there's a trade-off. But if high frequency attenuation is of interest, that might be a good trade-off to make.
Also, using a smaller inductance value results in lower DCR value, which means DC losses across our inductor would be smaller, would have smaller inductance value. So that's also another trade-off.
Here's another filtering example and a trade-off of self-resonant frequency. We tested two filters with the same LC product. But one has lower inductance than the other. The green curve here shows the noise spectrum of a switcher without an additional LC filter. And this noise spectrum was measured from 100 megahertz up to 1,000 megahertz.
The red curve shows the output of the second-stage filter where the second-stage filter was a 2.2 microhenry together would have a 44 microfarad capacitor. The blue curve is the output of a second-stage filter where the filter values were 1 microhenry instead of 2.2 and 94 microfarad instead of 44.
So you can see that at high frequency, with a smaller inductor and higher-value capacitor, we have a slightly better attenuation, and the high-frequency attenuation is improved by the better SRF spec of the filter inductor. So in this case, it would be better, if we wanted to really attenuate these frequencies, it would probably be better to use a 1 microhenry together with a 94 microfarad capacitor.
Let's look at an example that we tested in the lab. We started out with an unmodified LMZM23601 evaluation board, which comes with 47 microfarad and 22 microfarad output capacitance for a total of 69 microfarads of Cout. Here is the output noise of the board with 12 volt input, 3.3 volt output, and at 500 milliamps of load. And this was measured within our 1x probe with bandwidth set to 250 megahertz, so we can capture some of these high-frequency spikes.
So the high-frequency noise, peak-to-peak, in this case, was 12.6 millivolts. Here's a diagram of the filter setup. We actually chose to include the filter inside the feedback loop of the regulator. But we made sure that the regulator is still stable, and it's operating properly.
The output capacitance of the module was actually reduced slightly-- actually, not slightly. It was reduced almost 10 times, down to 6.8 microfarad capacitance so that we can use more output capacitance here on the output of the LC filter. And with this setup here, we tried two different LC values.
Here's the initial filter design. We used a 2.2 microhenry inductor and a 44 microfarad capacitor combination, which helped to reduce the high-frequency output noise down to 5.8 millivolts peak-to-peak, which is about 6.7 dB of attenuation at the high frequency.
The blue trace here shows the input of the LC filter. And you can see that there's a low-frequency ripple component and a high-frequency spike component to this overall output noise. And you can see that the filter does a good job in filtering the low-frequency ripple.
So here's that component here, and it's filtered out. And it also helps to reduce the high-frequency noise. Now, here's the switching spike before the filter. And here's what we have after. So you can see that the filter attenuation is not that great at a very high frequency. But still, it helps to cut down this high-frequency noise.
The second filter we tried was about one half of the inductance, so it went down to one microhenry. And we doubled the output capacitance to 94 microfarad, in this case. So this resulted in slightly lower-- although pretty comparable-- noise with 5.4 millivolts of high-frequency noise, which is about 7.7 overall dB of attenuation at that high frequency.
Now, a second-stage filter, we saw that it helps a lot to actually reduce noise, both at low frequency and high frequency. But what are some of the trade-offs with this addition of a LC filter? So one of the trade-offs is power dissipation penalty because of the DCR of the inductor that we're adding.
And in our case, the inductor had low enough DCR and the current was low enough so that we didn't see any significant change in efficiency, in power dissipation. But with higher current levels and higher DCR, this would definitely be something to consider, this additional power dissipation that's dissipated across the inductor.
Another trade-off is load regulation. Because the filter adds additional resistance in series with our output, depending on whether the filter is inside the feedback loop or outside of the feedback loop, we can see some load reg differences. So in this plot here, we're plotting the load regulation with no additional filtering, the load regulation with a filter inside the feedback loop, and load regulation with the filter outside of the loop.
And you see that if the filter is outside of the regulator feedback loop, there will be some penalty on low regulation. And we expect this penalty to be worse with heavier loads and worse with higher DCR.
Another trade-off to consider is the operation of the DC-to-DC converter at no load or at light load. Many modern regulators utilize some sort of power savings mode where the switching frequency gets scaled down considerably at light load or at no load conditions. So usually, the LC filter corner frequency is chosen so that we can get sufficient attenuation at the regulator switching frequency.
Let's assume that the full switching frequency of the regulator is, let's say, 1 megahertz. If the frequency of the regulator falls below the cutoff frequency of the filter-- at, let's say, light load-- the LC filter will just pass through all the noise, and there will be no attenuation at that frequency.
So if attenuation is needed at light load, the LC filter corner frequency may have to be optimized, which means that the LC filter physical size will go up. And that will result in a larger solution size. But if we need to capture that frequency of operation, that is the only way we can do that with an LC filter.
So what are the key takeaways for a second-stage LC filter approach filtering output noise? Well, we see that the filter can be quite effective for both low-frequency ripple reduction and high-frequency noise reduction. If the switcher has power savings mode, as we just discussed, with a lower switching frequency operation at light load, the LC filter may need to be adjusted for the appropriate switching frequency at the light load.
High-frequency switching noise reduction highly depends on the filter parasitics, as we demonstrated. There may be a need to optimize and simulate the filter design at the high-frequency ringing and look at how the SRF of the inductor is going to affect the filter performance.
If the LC filter is inside the loop, some of the regulation penalty can be avoided. The regulator loop would take care of that. But we may need to damp the LC filter to avoid regulator stability issues. And damping will definitely also affect the high-frequency attenuation. So in order to avoid some of these penalties, we may be sacrificing high-frequency noise reduction.
Let's now take a look at using LDOs as the supply cleaner circuit after the switching regulator. There is actually an excellent presentation on LDOs on the TI training site. It goes into more detail on LDOs, and the link to that presentation is provided here in this slide.
Here's a diagram of the buck converter again. And the idea here is to place an LDO after the switcher and utilize the LDO power supply rejection ratio characteristics to clean up the rail. Let's take a look at the power supply rejection ratio curve of the LDO.
Now, the PSRR characteristics of the LDO can be divided into several different regions. The first region depends on the LDO internal reference and internal filtering. And the second region of the PSRR curve depends on the open-loop gain of the LDO error amplifier.
And the third region here-- the high-frequency portion of the PSRR curve-- really depends on the parasitic elements, as you might have guessed already, of the output capacitance of the LDO. Remember, the LDO circuit has an input bypass capacitor and an output capacitor. So those would play a role here at the high frequency.
We did an experiment again using the same switcher as in a earlier example, the LMZM23601 power module with an integrated inductor. And this time, we paired it together with a TPS7A4701, which is a 36 volt, 1 amp ultra-low LDO. So both devices are capable of delivering 1 amp of current. And we thought that this would be a good match to pair these two together.
Here's some results of the pairing of the switcher with the LDO. The upper trace shows the output of the switcher. The vertical scale is 5 millivolts per division, actually, for both measurements. And the bandwidth here is 250 megahertz. So the lower trace, here in blue, shows the output of the LDO. And again, the vertical scale and the bandwidth are the same for these two measurements.
So in this measurement, we're showing attenuation of the high-frequency noise of about 7.6 dB, which is not bad. We see that some of this high-frequency noise is really getting attenuated. And in terms of the setup, we have a power supply. We have a switcher with a short enough connection to the LDO and with a short connection to our load.
We hooked up our board setup to a spectrum analyzer to see a little bit more detail in the frequency domain. And here, in blue, we're showing the output of the switcher, as is. And then, in green, we're actually showing the input of the LDO measured close to the LDO device. Remember, the LDO circuit has input bypass capacitance, whose purpose in life is to filter noise going into the LDO.
So you can see that the input capacitor of the LDO is already working to filter some of this noise. Also, since the LDO is closer to the load, there's some parasitic inductance between the switch and the LDO. So that parasitic L, along with the LDO input capacitance, will form a small LC filter already. So it would help with filtering some of this high-frequency noise.
The red trace shows the output of the LDO. And you can see that's very clean. And as we know, and as we saw in earlier slides, at that frequency, the noise on the output of the LDO is really a function of the parasitic capacitance across the LDO pass device and the LDO output capacitance impedance.
So the LDO, in this case, is the combination of input capacitance, LDO, and output capacitance. It really helps to filter the output noise. And in this case, we used LDO standard evaluation board with--
So great. The LDO can help clean up the output noise of the DC-to-DC converter. But what are some of the trade-offs? One clear trade-off is power dissipation, or overall efficiency. The LDO needs some headroom to regulate the output voltage. And the additional power dissipation associated with the LDO, when compared to just the switcher-only solution, is the headroom voltage times the load current.
So in our case, the switcher was programmed to 3.8 volts output, and the LDO was programmed to 3.3 volts output. With 600 milliamps of load, the additional dissipation is about 300 milliwatts. So definitely, there's some additional loss that we have to take into account when we have the LDO attached to the output of the switcher.
Now, in some applications, we may require dynamic adjustment of the power supply voltage, and we may require low noise at the same time. A example of that would be some test and measurement applications where you want a dynamic output voltage scaling.
So if we have a DAC that changes the voltage dynamically, the difference between the switcher output voltage and the LDO output voltage can be quite large and that can result in high power dissipation. So here's a design idea that avoids the excessive heat by configuring the switcher as a tracking pre-regulator.
And so basically, the idea is that we have an LDO. We control the LDO output with a deck, and a switcher tracks this output of the LDO and produces output voltage just enough to support the headroom for the LDO here. And we avoid a big delta between the output of the switcher and the output of the LDO. And there's a nice blog about this design idea in this link highlighted on the bottom.
Another obvious trade-off for using an LDO is board space. The LDO is, at minimum, three additional BOM components-- for example, an input capacitor, LDO, and an output capacitor. So fitting this on the board, in addition to a switcher, may be a board space issue.
So one way to save on board space for the switcher is to use a power module, which integrates the inductor and, in most cases, results in space savings. And this can open up, actually, room to fit the LDO circuit following the DC-to-DC converter.
We mentioned power savings mode and the fact that LC filters may not be able to attenuate the really low switching frequency. This is assuming that, again, that an LC filter was not grossly oversized, and it was designed to filter the full switching frequency of the converter. So the LDO will inherently do a better job at filtering the low-frequency ripple. And here's an example.
The plot on the left has a switcher running with no load, but the switcher is put in a forced PWM mode of operation. So the switching frequency of the switcher is a full 1 megahertz switching frequency. You can see that both a switcher with a LC filter and a switcher with a LDO produce a pretty clean output at the full switching frequency of the converter.
However, on the right, we have a comparison of what happens to the output noise when we put the regulator in PFM mode. And again, there is no load, so the switching frequency of the regulator is now down to 300 hertz instead of 1 megahertz. So you can see that the LC filter on the top here is not adequate in filtering this low-frequency noise because it's way lower than the cutoff frequency of the LC design.
Also, it wouldn't be practical to design an LC filter, to size the LC filter for 300 hertz of operation. It would be, really, a large filter, and it would be difficult to fit that on the board. At the same time, the LDO has no problem dealing with this low-frequency noise. That's well taken care of by the LDO PSRR characteristic.
So let's look at the key takeaways for using LDO as a filter at the output of a switching converter. We saw that the LDO can help reduce both the low-frequency ripple and the high-frequency switching noise. And if the switcher has some sort of power savings mode where the switching frequency is reduced at light load, the LDO would still work very well in filtering the low-frequency ripple.
The high-frequency switching noise reduction depends on the LDO PSRR curve at high frequency, which is really dependent on the impedance of the output capacitor of the LDO. We see that the low regulation issues are mitigated by the LDO because it has its own loop to regulate the output voltage. And there is a trade-off with additional power loss, additional BOM count, and additional board space associated with the LDO design.
So what should we use-- LDO or a second-stage filter? Well, we saw that the LC filters can get really tricky at high frequency. The designer would need to consider the parasitic elements of the output capacitor and inductor, and filter damping may be needed so that the overall regulator is stable.
The LC filter may require a lower BOM count than the LDO, but it really depends on how many output capacitors are used in the LDO and the LC filter design. If power savings mode is employed for the DC-to-DC switcher, then the LDO would definitely provide better filtering in that low frequency.
And in terms of design, the LDO is really straightforward. So in my mind, the LDO approach could be easier and more beneficial. And keep in mind that the LDO can always be followed by a high-frequency capacitor to clean up the remaining switching noise.
In summary, we saw that understanding the noise origin is important for noise mitigation. We saw that parasitic elements are usually the ones that cause trouble in terms of noise. And measuring noise properly can save us a lot of effort in trying to design filtering solutions.
We saw that there are many noise reduction techniques. We discussed layout, component placement, stackup, some high-frequency filtering with capacitors, and different package options and regulator options, such as power modules. We saw that second-stage LC filters and LDOs can be used effectively to clean up output noise, both low-frequency ripple and high-frequency switching noise.
And considering all the trade-offs that we went over, we concluded that LDOs may be the preferred option to come up with a cleaner output voltage. This concludes this presentation. And I would like to thank you for watching. [嗖] 你好。 我的名字是Denislav Petkov， 我是德州仪器电力模块团队的 应用工程经理。 今天，我们将讨论 如何理解、测量 和降低直流-直流 开关稳压器的输出噪声。 这是演讲的议程。
演示的第一部分 将着重于理解噪声的来源 以及如何正确地测量它。 我们将研究相关寄生元件， 高频和低频元件的噪声。 然后，我们将查看一些测量技术， 以及来自工作台的示例。 我们还将讨论一些 关于电路板布局 和元件布置的降噪技术。
我们还将研究不同类型的 并联电容器及其 对低频降噪的影响。 接下来我们将看看使用 两种不同方法的过滤技术。 我们将研究第二阶段的 LC过滤器和LDO。 这两种方法都将包含示例， 我们将研究这两种方法的优缺点。
让我们开始吧。 从理想世界开始。 你们知道，这是巴克调节器。 这相当简单。 这里，我们有一个输入源， 一个输入旁路电容，两个开关-- 高侧和低侧-- 一个电感，一个输出电容， 和一个负载。
这两个开关以特定的占空比 切断输入电压。 电感器和输出电容 将这个斩波平均， 得到输出电压等于Vin 乘以占空比。
实际上，巴克调节器 还附带了 一些寄生元件。 这些都是免费的。 但大多数时候， 这些免费组件是不需要的。 有寄生电感与封装有关。 输入电容及其位置 也会产生额外的寄生元件。
高侧开关和低侧开关 串联有寄生电感。 在变换器的输入端 有一个高的di/dt回路。 有寄生元件与电感器， 以及与输出电容。 因此，客户和工程师 在开关电源方面 遇到的大多数噪音问题 都与这里红色显示的 那些元件有关， 那些在设计中作为寄生元件 出现的元件。
让我们看一下巴克转换器的输出。 如果我们用示波器放大电压， 并有足够的带宽， 我们会注意到两个不同的形状。 在变换器的开关频率上， 存在频率较高的电压尖峰 和频率较低的纹波。 变换器的低频输出电压纹波 是电感中的纹波电流 通过输出电容阻抗的结果。
我们已经知道，输出电容 不仅仅是一个电容。 它具有等效串联电阻的 寄生电感。 因此，输出端总的 低频峰间电压纹波 是总输出电容阻抗的函数， 它同样具有ESR电容和ESL。 我们会更详细地看一下。 但我们先来看看高频尖峰 以及这些尖峰从何而来。
这是巴克转换器的输出。 在这种情况下，我们关注的是 每个开关周期边缘的高频尖峰。 那么这些噪音来自哪里呢？ 这种噪声是由高的di/dt电流 和其路径中的任何电感所产生的。
对于巴克变换器，高di/dt回路 在调节器的输入端。 对于升压变换器，高di/dt回路 将在输出端。 所以任何寄生电感 与这个高di/dt电流串联 都会产生电压。 这些电压尖峰会以 高频振铃的形式 出现在开关节点上。
现在，开关节点被这些 高频尖峰污染了。 但是它们如何在输出中表现? 再一次，我们有一个电感， 所以应该能够阻挡一些高频。 结果是有寄生电容 从开关节点到输出端， 主要通过电感， 也通过我们的电路板。
所以电感之间的电容 可以是几皮拉德到几十皮拉德， 这取决于我们使用的电感。 此外，电路板布局中的 开关节点铜 可能与另一层重叠， 导致那里有寄生电容。
例如，一些布局会有 专门的电源平面用于输出电压。 如果有一个开关节点铜 与足够大的面积重叠， 那可能是一个平行板电容器， 它可以准备耦合 这个高频噪声到输出。
在我们探索降低 输出噪声的方法之前， 让我们确保我们正确地 测量了它。 为什么我们如此在意测量？ 不正确的测量技术会 导致输出噪声的放大。 夸大的输出噪声测量可能导致 过于激进的方法来修复它。 所以在我们开始研究 如何减少噪音之前， 知道我们所处理的噪音的真实数量 是很重要的。
这是一个不好测量技术的好例子。 在这里，我们试图用我们的 典型范围探头测量 巴克转换器的输出。 你可以看到范围探头的地线 可以形成一个很好的环形天线。 这肯定会从这里的电感 接收额外的噪声。 它会用巨大的尖刺 污染我们的测量。
进行相同测量的较好方法是 改进示波器探头的接地接线。 其中一种方法是绕一根地线 在探测筒上。 这将导致这里的接地回路 面积更小。 这也将导致更清洁的测量。 这里有一个例子。
在上面的波形图中， 我们用示波器探头的 一个大的接地回路 来测量输出噪声。 在这种情况下，我们接收到 200毫伏的高频噪声， 从峰值到峰值。 随着我们的示波器探头 接地的改进， 测量实际上是 100毫伏的峰值到峰值。 这是测量到的噪音差的2倍 我们知道电路是完全一样的， 不同之处在于我们如何测量它。
所以我们假设在这种情况下 应用需要75毫伏的波纹 或高频噪声。 如果我们使用第一个度量， 我们会认为我们离目标很远， 我们需要大量的过滤 来达到目标。 在第二种情况下， 或者说第二次测量中， 我们会发现我们实际上更接近， 比如说，75毫伏目标， 我们不需要太多的滤波 就能到达那里。
现在，一些工程师可能想要 进一步改进这种测量方法。 一种方法是给自己一个1x探头。 下面是制作1x范围探测器的 一种方法。 短段同轴电缆可直接 焊接到测量点。
示波器通道上有交流耦合电容 和外置50欧姆 终止电阻。 电容，这里是0.1微法拉， 在这种情况下， 50欧姆的终止形成了 31.8千赫兹的截止频率。 这个高通滤波器的截止频率， 基本上，适用于大多数 现代调节器的全开关频率。
从探测器的频率响应， 我们可以看到它非常平坦， 高达200兆赫。 这对于测量，比如说， 在示波器上的200，250兆赫带宽 是很有用的。
因为截止频率在，比如说， 32千赫兹左右，所以知道 转换器的开关频率很重要。 如果你在轻负荷下工作， 转换器进入某种节能模式， 开关频率可能会降低。 我们要确保它不低于 截止频率。 否则，我们的测量，本质上， 会减弱一些噪音。 我们不会得到正确的结果。
此外，如果我们试图测量 负载瞬态峰间纹波，同样， 这个探头 可能不适合这种情况。 因为负载瞬态可能是 在一个较低的频率， 在那里它将开始衰减。 但是对于大多数现代开关， 负载输出 在这个频率范围内工作， 这个探头应该是非常好的。
下面是一个用1x探头测量的例子。 我们在上面有一个1x的探针， 在下面有一个10x的探针。 我们可以看到，用1x探头， 我们可以得到一个更清晰的读数， 我们可以放大到每单位1毫伏， 如果我们想做一些 低于1毫伏的测量。 所以这可能是一个很好的 测量输出噪声的方法。
让我们看看如何减少输出噪声的 低频纹波分量。 提醒一下我们要减少什么， 这是巴克转换器的输出。 在这种情况下，我们试图 减少低频波纹。
我们现在知道，低频纹波 是电感纹波电流 和输出电容阻抗的函数。 因此，根据电容的类型， 纹波对输出可能会有很大的不同。 这里有一个左边的例子， 我们有不同的 输出纹波形式 使用相同的47微法拉电容， 但我们使用不同类型的电容。
在顶部，我们有一个陶瓷电容器， 通常配备非常低的ESR和ESL。 红色的部分，我们有一个 同样值的钽电容-- 47微法拉--但是它有更多的 ESR和ESL，纹波更大。
再往下，这里是浅蓝色， 我们都有OSCON电容-- 同样，一个47微法拉帽。 这个电容，比方说， 有中等水平的ESR和更多的ESL。 你可以看到涟漪更大。 在底部，我们有一个 铝电解电容器的例子， 它有很多ESR。 你可以看到这里的波纹 要高一些。
所以电容的类型肯定会 影响我们输出的低频纹波。 重点放在电容器的 寄生元件上是非常重要的， 这样我们才能知道 我们会得到多少波纹。
一些对噪声敏感的应用程序 需要非常低的纹波， 像测试和测量应用程序 这样的例子， 需要非常非常干净的输出。 因此，对于这些应用程序， 工程师可以选择在输出上 附加一个LC过滤器。 在右边这个例子中， 我们使用的是LMZM23601 直流对直流模块， 它里面已经有一个电感。
我们将它与输出上的 额外LC过滤器配对。 所以C1是模块的输出电容-- 正常的输出电容通常 要放在输出上。 L2是二阶滤波器的电感。 C2，C3和C4，以及 这里的阻尼电阻， 构成整个滤波器。
通过这个过滤器实现， 我们能够得到一个 0.7毫伏的峰值到峰值， 对于这个5伏的电源， 这是极低的纹波输出。 在这张幻灯片中， 有一个电子表格计算器， 它将帮助您设计一个LC过滤器， 如果您需要为应用程序实现 真正低纹波。
我们看到低频纹波实际上 取决于输出电容阻抗。 而不同的电容类型会有 不同的寄生特性。 因此，一些设计人员可能会选择 在变换器的输出端 混合不同类型的电容器。
陶瓷电容器很棒，就像 我们在这里看到的。 但有时很难买到。 它们也可能在特定的 应用电压下耗尽电容。 因此，将陶瓷电容器与一些 不同化学成分的 大容量电容并联是有意义的， 这样你就得到了，我们说， 两个世界中最好的。 你得到足够的电容，然后 你有足够低的阻抗 来实现低纹波。
但是当你有一个平行电容， 比如说陶瓷和铝的电解电容， 会产生多少波纹？ 如果我们知道每个电容的ESR， 我们实际上可以做一些计算， 计算出并联组合的有效电容 和有效串联电阻。 这里有一些方程，这张幻灯片 还包括一个计算器， 它会把这些方程考虑进去 并显示并联组合的 有效电容和电阻。
这是你打开计算器时的样子。 您可以在这里输入最多两个电容-- 电容1和电容2规格-- 第一个电容的电容和ESR， 第二个电容的电容和ESR。 然后，你可以输入降压转换器的 输入电压，输出电压， 电感在开关频率。
这部分基本上会计算 特定条件下的纹波电流。 考虑到ESR和电容的有效并行组合， 计算器会告诉你 什么是低频纹波，在底部这里。
这是一个低频输出纹波的例子， 假设有1安培的纹波电流 和100微法拉的电解电流， 同时有不同的陶瓷电容值。 假设调节器的开关频率 是500千赫兹。 根据电解ESR， 如果我们有2.2微法拉的并联陶瓷， 低频纹波将会是85毫伏， 在这种情况下， 这个开关频率。
使用22微法拉平行陶瓷， 波纹将略超过10毫伏。 如果我们添加更多的陶瓷电容器， 多达100微法拉的并联陶瓷， 我们可以看到低频纹波 会在几毫伏的 峰值到峰值之间下降。 因此，这可以给你一个想法， 我们可以期待多少波纹， 为一个特定的输出电容 并联组合。
让我们来看看降低降压变换器输出 高频噪声的方法。 作为第一线攻击，让我们看看 如何处理组件放置。 我们可以做的一件事是尽量减小 高di/dt电流回路的面积。 面积越小，电感越小。
对于巴克变换器，我们知道 高di/dt回路是在调节器的 输入端形成的。 因此，将输入电容尽可能 靠近集成电路 将导致更小的环路和环路面积。 这将导致更低的电感。
环路面积越小，开关节点的 振铃越低。 开关节点上振铃越低， 则降压变换器输出噪声越低。 所以减小高频噪声的第一步是 优化降压变换器的 输入电容位置。
很多人没有马上意识到这一点， 但对于降压变换器， 输入电容的定位 会影响输出噪声。 当我们为巴克转换器做布局检查时， 我们总是强调这一点。 输入电容的位置 是我们设计巴克变换器时 最重要的考虑因素之一。
这是一个例子。 这里，我们有一个 同步降压转换器IC， 它的输入端离IC 稍远一点， 这里的高di/dt回路区域 用红色标出。 这个转换器的输入电压是12伏。 我们看到开关节点的尖峰 随着这个特殊的电容位置 上升到18伏特。 和阿尔法电压高频噪声 峰值至峰值是75毫伏。
在右边，这里，我们有一个 辐射电磁干扰测量。 我们发现我们的设计 不符合B类规范。 如果我们把输入电容 放置的好一点， 减少高di/dt回路附近的 输入电容的环路面积-- 在这种情况下，环路面积 大约是原来的两倍-- 我们看到，对于相同的输入电压， 峰值是14.5伏特。
而我们的输出噪音-- 从18降到14.5-- 我们的输出高频噪声从75毫伏 到47毫伏的峰值到峰值。 同时，电磁干扰扫描 也比之前有所改善。
注意，在这种情况下，我们并没有 花费额外的钱来获得 输出噪音的显著改善。 我们只是把降压变换器的输入电容 放在不同的地方， 直接对着集成电路。 我们得到了更好的结果。 所以这个改进是完全免费的。 这仅仅是由于输入电容的 正确放置。
现在，电源模块真的可以帮助 简化电路板布局， 让工程师远离麻烦。 现在，这是如何工作的? 例如，集成了一些输入电容的 电源模块可以帮助您大大减少 高di/dt环路面积。 一些电容会在模块内部。 这将使布局尽可能的优化。
另外，由于开关节点在模块内部， 且尽可能小，因此由于电路板布局， 开关节点到电路中任何其他节点的 寄生电容都是有限的。 因此，当你使用电源模块 进行设计时， 你会得到更少的振铃 和更低的输出噪声耦合。
下面是一个例子， 我们发布的一个新型号 是LMZM33603。 你可以看到，在这种情况下， 有一个输入电容正好放在 内部IC上， 而高的di/dt回路是非常小的。 我们有一个屏蔽电感， 我们有一个最小的开关节点 连接IC就在外面连接到 电感终端在开关节点区域 没有多余的。
集成电路封装结构 在降低高频噪声方面 也有一定的优势。 一些集成电路可以在 热棒封装中使用， 这可以减少封装寄生， 通常与我们的高di/dt环路串联， 因此可以减少开关节点上的振铃。 下面是我们的LMR33630的 一个例子。
该设备采用标准的 QFN线键合封装。 它也可以在一个热棒封装中使用， 我们翻转芯片，我们在模具 和引线框架之间有铜互连。 可以想象，这大大降低了 寄生电感。 如果我们将开关节点 与设备的线键版本 和设备包的热棒版本进行比较， 我们会在开关节点上 得到更少的振铃， 因此，输出噪音更低。
因此，如果噪音是个问题， 这种包装结构肯定会有所帮助。 在这种情况下，可以使用 热杆样式的包。 对于热棒组件的权衡是， 将热从模具中取出 可能更具挑战性， 与其他所有事情一样， 仔细注意布局是必要的。
另一种减少噪音的方法是 在木板上使用适当的叠层。 在这个特殊的例子中， 我们使用了一种拍摄技术， 我们把Vin-- 嘈杂的Vin线-- 和Vout放在一个内层-- 在这个例子中是中间层2-- 我们在上面有一个很好的地面。 中层，我们没有改变。
Vin和Vout的路由我们移到了第3层， 在本例中是中间层2。 底层都是地面。 所以你可以看到，我们基本上 是把这条嘈杂的线和Vout 夹在了我们堆叠的地面平面之间。 所以建筑材料是完全一样的。 区别在于堆叠和路由。
我们从在高频时出现这个碰撞， 并没有达到电磁干扰的标准， 到通过改进的叠加消除了这个碰撞， 现在通过了辐射电磁干扰的 B类标准。 同样，建筑材料没有变化。 它只是PCB层的堆叠。 这导致了通过EMI，而不是 在这里的高频失败。
增加一个输入滤波器到降压转换器 对辐射噪声也有很大的帮助。 这是一个例子，一个输入滤波器 如何为传导的电磁干扰， 实际上减少辐射电磁干扰。 输入滤波器通常是pi滤波器， 这里是巴克转换器的输入。 你有一个电容，用来阻尼一些ESR， 你有一个L和一个C，可以清除 任何产生的噪音， 不让它回到输入线上。
所以你看，如果没有过滤器， 我们就会失败。 用一个过滤器，清理Vin-- 嘈杂的Vin线-- 我们很容易通过这个EMI规范。 这张幻灯片中嵌入了 一个快速计算器，如果需要 在应用程序中 设计输入过滤器，它将帮助您 设计一个输入过滤器。
经过精心的布局， 精心的电容配置， 观察PCB的堆叠， 并做所有的最佳实践， 一天结束时， 我们会得到一些输出噪声， 其中会有高频成分。 我们会遇到一些尖峰，无论如何， 因为我们不能完全消除寄生电感 和高di/dt回路寄生电容 耦合噪声到输出。 那么我们能做什么来进一步 降低这个高频呢?
我们能做的一件事是， 也许我们可以选择一个高频电容， 来提高我们在这个高频下的 输出电容阻抗。 就高频而言，你觉得哪个更好? 主电容和一个微法拉平行比较好吗? 比方说0.1和0.01-- 或多次使用相同值的 高频电容?
我看到这两种方法都应用于设计。 答案是，这要视情况而定。 它取决于我们试图过滤的 信号的频率 和电容组合的 整体频率响应，或阻抗。 我们来看一些例子。
这就是为什么我说 这要视情况而定。 这是我们刚刚看到的 三种构型的阻抗曲线。 我们看到，在高频时，附加的 并联电容器--高频电容器-- 可以增加阻抗谷，这很好。 这意味着低阻抗，我们可以过滤 这个频率的噪声。 但不幸的是，它们也会在 不同的频率上增加峰值。
所以这些共振峰会影响 输出电容组合的性能。 你看，如果我们试图过滤的噪音 落在这个范围内， 高频电容的增加 实际上会使事情变得更糟， 如果我们只使用一个 10微法拉电容的话。
所以这取决于我们要过滤的 噪音的频率。 通过对不同电容寄生值的仿真， 得到了该图。 如果你想做一个类似的分析， 这里有一个快速的模拟文件， 你可以在这个演示中使用。
这是一个例子。 在第一波中，我们有一个22微法拉 陶瓷电容器。 我们在板上测量出 峰值到峰值的76.2毫伏高频噪声。 我们说，好吧， 让我们过滤这个高频噪声。 我们将220 pF陶瓷电容器 与22并联。
这让事情变得更糟。 为什么？ 因为这个振铃频率下的 总阻抗实际上在这个电容组合中 更差。 我们得到的是阻抗的峰值 而不是谷值。 把这个电容改成470， 在我们的例子中， 移动了共振峰， 它在振铃频率上的总阻抗 比这里的一个电容要好。
所以你可以看到，如果你选错 高频电容值，你实际上 会使事情变得更糟。 所以很重要的是要知道 我们要过滤的 是什么样的噪声 以及通过并联组合得到的总阻抗 是什么样的。
许多电力工程师可能会选择 在开关的输出端使用 某种二级滤波器或LDO 来清理电压轨。 二阶滤波器是一种低通滤波器， 它的设计目的是衰减非常高的频率。 使用LDO方法， 我们的主要目标是，利用LDO的 电源抑制特性， 基本上抑制这里的噪音， 产生一个真正干净的输出。
让我们更详细地看看这两种方法， 看看每种方法的好处 和权衡。 让我们来看看降低输出噪声的 第二阶段LC滤波方法。 下面是一个第二阶段 LC过滤器的例子。
在上面，我们有理想的LC滤波器。 你们可能已经猜到了， 在现实生活中， 我们没有一个理想的LC滤波器， 所以我们在电感周围 有一些寄生元件， 也就是电感的DCR和寄生电容。 然后，我们还得到了输出帽的 ESL和ESR。 我们还有一个阻尼电阻， 它也有串联的 寄生电感和电容。
所以这些寄生元件会导致 LC滤波器在高频下衰减更差。 用蓝色表示，我们得到了 理想的LC滤波器响应。 红色的是带有寄生元件的 LC滤波器。 绿色的是LC滤波器，它有一个 理想的阻尼电阻。 所以我们可以看到， 根据我们要过滤的频率， 这些寄生成分 会影响我们在高频下的衰减。
下面是关于LC滤波器寄生的 一些细节。 实际上，电感器带有一个并联电容。 该寄生分量可由电感器的 自谐振频率谱 计算得到。 我们已经知道，输出电容 具有较小的ESL或寄生电导。 所以这些寄生元件-- 寄生电容和寄生电导-- 实际上开始在高频下 对我们的滤波性能产生负面影响。
你可以看到在右边的图中， 我们展示了理想的LC衰减 和更真实的LC滤波器的衰减， 电容的自共振频率开始出现在这里。 这是电感的自共振频率， 这是电容ESL和寄生电容 穿过电感。
所以根据我们要过滤的频率， 你可以看到在高频率下， 我们可能会失去一些衰减。 我们甚至可能让这里的高峰 变得更糟。 因此，如果对高频衰减感兴趣， 选择一个SRF规格更好的电感 可能是有意义的。 我说的更好是指更高的SRF频率。
这将意味着电感的 电容较低。 与SRF较低的电感相比， 高频时的衰减效果 略好。 在这种情况下，我们正在比较 来自相同电感系列的电感器。 但是这里的值小10倍 就能得到更好的高频衰减。
同样，这是一个权衡， 当你的LC滤波器产品， 如果我们想保持它不变-- 就是这个角-- 如果我们用小10倍的电感， 我们需要用大10倍的电容。 所以这是有代价的。 但如果对高频衰减感兴趣， 这可能是一个很好的权衡。
此外，使用更小的电感值 会导致更低的DCR值，这意味着 我们的电感器的直流损耗 会更小，会有更小的电感值。 这也是另一种权衡。
这是另一个滤波例子 和自共振频率的权衡。 我们用同样的LC产品 测试了两个过滤器。 但是一个比另一个电感小。 这里的绿色曲线显示了 没有附加LC滤波器的 切换器的噪声频谱。 这个噪声频谱是从100兆赫 到1000兆赫测量的。
红色曲线显示的是 二级滤波器的输出， 二级滤波器为2.2微亨利， 两级滤波器加起来 有44微法拉电容。 蓝色曲线是二级滤波器的输出， 其中滤波器值为1微亨利 而不是2.2， 是94微法拉而不是44。
所以你可以看到在高频下， 用一个更小的电感 和更高值的电容， 我们有一个稍微更好的衰减， 高频衰减被更好的 滤波器电感的SRF规格改善。 所以在这种情况下，它会更好， 如果我们想真正衰减这些频率， 它可能会更好地使用一个1微亨利 与一个94微法拉电容器。
让我们看一个我们在 实验室中测试的例子。 我们从一个未经修改的 LMZM23601评估板开始， 它具有47微法拉 和22微法拉输出电容， 共69微法拉的Cout。 这是带有12伏输入，3.3伏输出， 500毫安负载的电路板的输出噪声。 这是在我们的1x探头内测量的 带宽设置为250兆赫， 所以我们可以捕捉到 一些高频尖峰。
所以高频噪声，从峰值到峰值， 在这种情况下，是12.6毫伏。 下面是过滤器设置的图表。 我们实际上选择将滤波器 包含在调节器的反馈回路中。 但我们确保了监管机构仍然稳定， 运转正常。
模块的输出电容 实际上稍微减小了-- 实际上，不是很小。 它被降低了近10倍， 降到6.8微法拉电容， 所以我们可以 在LC滤波器的输出上 使用更多的输出电容。 通过这个设置，我们尝试了 两个不同的LC值。
这是最初的过滤器设计。 我们使用2.2 microhenry电感 和44 microfarad电容组合， 将高频输出噪声降低到 5.8毫伏峰值至峰值， 在高频时衰减约6.7 dB。
这里的蓝色跟踪显示了 LC过滤器的输入。 你可以看到在整个输出噪声中 有一个低频纹波分量 和一个高频尖峰分量。 你可以看到滤波器 在过滤低频波纹方面 做得很好。
这是这个组件，它被过滤掉了。 它还有助于降低高频噪声。 这是滤波器之前的开关峰。 这是我们得到的。 所以你可以看到滤波器的衰减 在很高的频率下不是很大。 但它仍然有助于 减少这种高频噪音。
我们尝试的第二个滤波器 大约是电感的一半， 所以它降到一个微亨利。 在这种情况下，我们把输出电容 加倍到94微法拉。 这导致了稍微低一点的-- 尽管相当相似--具有5.4毫伏 高频噪声的噪声， 在该高频下 衰减约为7.7 dB。
现在，第二个阶段的滤波器， 我们看到它在很大程度上 降低了噪音， 无论是在低频还是高频。 但是添加LC过滤器 有哪些权衡？ 其中一个权衡就是功耗损失 因为我们要加上电感的DCR。
在我们的例子中， 电感有足够低的DCR， 电流足够低， 所以我们没有看到效率 和功耗的显著变化。 但是随着更高的电流水平 和更高的DCR， 这肯定是需要考虑的， 额外的功率损耗， 是通过电感损耗的。
另一个权衡是负载调节。 因为过滤器在输出中 增加了额外的电阻， 这取决于过滤器是在反馈回路内部 还是在反馈回路外部， 我们可以看到一些负载reg差异。 在这个图中，我们画的 是没有额外过滤的负载调节， 反馈回路中有一个 过滤器的负载调节， 回路外有一个过滤器的 负载调节。
你可以看到，如果过滤器 在调节器反馈回路之外， 低调节会受到一些惩罚。 我们预计这种惩罚会随着 负载的增加而加重， 随着DCR的增加而加重。
另一个需要考虑的权衡是 直流对直流变换器在空载 或轻载时的运行。 许多现代的调节器 利用某种节能模式，在轻负荷 或无负荷的情况下， 开关频率会大幅降低。 因此，通常选择LC滤波器的角频率， 使我们能够在稳压器的开关频率上 获得足够的衰减。
假设调节器的全开关频率是， 假设是1兆赫。 如果调节器的频率 低于滤波器的截止频率-- 比方说，在轻负载时-- LC滤波器就会通过所有的噪声， 在那个频率上没有衰减。
因此，如果需要在轻载下衰减， 可能需要优化LC滤波器的 转角频率， 这意味着LC滤波器的物理尺寸 会增大。 这将导致更大的解决方案尺寸。 但是如果我们需要捕捉 操作的频率， 这是我们用LC滤波器 能做到的唯一方法。
那么，第二阶段 LC滤波器滤波输出噪声的 关键是什么呢？ 我们可以看到滤波器 在降低低频纹波和高频噪声方面 都是非常有效的。 如果开关器具有节电模式， 正如我们刚才讨论的， 在轻负载下开关频率较低， 那么LC滤波器 可能需要调整为在轻负载下 合适的开关频率。
正如我们所证明的， 高频开关噪声的降低高度 依赖于滤波器寄生。 可能需要对高频振铃的滤波器设计 进行优化和仿真， 并研究电感的SRF 对滤波器性能的影响。
如果LC滤波器在环路内， 则可以避免一些调节损失。 调节器回路会处理这个问题。 但我们可能需要抑制LC滤波器， 以避免稳压器的稳定性问题。 阻尼必然也会影响 高频衰减。 因此，为了避免这些惩罚， 我们可能牺牲高频降噪。
现在让我们来看看使用LDO 作为开关稳压器之后的 电源清洁电路。 实际上有一个很好的演示。 在TI培训站点的LDO上。 它将更详细地介绍LDO， 以及到该演示文稿的链接， 在这张幻灯片中提供。
这是降压转换器的图表。 这里的想法是在开关后 放置一个LDO利用LDO的 电源抑制比特性来清理轨道。 让我们来看看LDO的 电源抑制比曲线。
现在，LDO的PSRR特性 可以划分为几个不同的区域。 第一个区域依赖于LDO内部引用 和内部过滤。 而PSRR曲线的第二区域 依赖于LDO误差放大器的 开环增益。
这里的第三个区域-- PSRR曲线的高频部分-- 实际上取决于寄生元件， 你们可能已经猜到了， LDO的输出电容。 记住，LDO电路有一个 输入旁路电容 和一个输出电容。 所以它们会在高频下发挥作用。
我们再次做了一个实验， 使用与前面例子相同的开关， 集成电感的LMZM23601电源模块。 这次，我们把它和TPS7A4701配对， 这是一个36伏，1安培超低LDO。 所以这两种设备都能提供 1安培的电流。 我们认为这这两个在一起 将是一个很好的配对。
下面是切换器与LDO配对的 一些结果。 上面的跟踪显示了切换器的输出。 垂直比例尺是5毫伏每单位， 实际上，为两次测量。 这里的带宽是250兆赫。 下面的蓝色跟踪显示了 LDO的输出。 同样，垂直比例尺和带宽 对于这两个测量是一样的。
所以在这个测量中，我们展示了 约7.6 dB的高频噪声的衰减。 这并不坏。 我们看到一些高频噪声 正在减弱。 就设置而言，我们有一个电源。 我们有一个切换器， 它与LDO的连接足够短， 与负载的连接也足够短。
我们把电路板安装在频谱分析仪上， 以便在频域中看到更多的细节。 这里，用蓝色表示的是 切换器的输出。 然后，用绿色表示的是 LDO设备附近测量到的 LDO输入。 记住，LDO电路有输入旁路电容， 其目的是滤除进入LDO的 噪声。
所以你可以看到LDO的输入电容 已经开始过滤这些噪音了。 此外，由于LDO更接近负载， 开关和LDO之间 存在寄生电感。 所以寄生的L， 连同LDO的输入电容， 将会形成一个小的LC滤波器。 所以这将有助于过滤 一些高频噪音。
红色的跟踪显示了LDO的输出。 你可以看到它很干净。 正如我们所知，正如我们 在之前的幻灯片中看到的， 在那个频率下，LDO输出的噪声 实际上是LDO通过器件寄生电容 和LDO输出电容阻抗的 函数。
在这种情况下，LDO是输入电容， LDO和输出电容的组合。 它确实有助于过滤输出噪声。 在这个例子中，我们使用了 LDO标准评估板--
很好。 LDO可以有效地消除直流 对直流变换器的输出噪声。 但是为什么有一些权衡？ 一个明显的权衡是功耗， 或整体效率。 LDO需要一些空间来调节输出电压。 与只有开关的解决方案相比， 与LDO相关的额外功耗是 净空电压乘以 负载电流。
在我们的例子中，切换器 被编程为3.8伏电压输出， LDO被编程为3.3伏电压输出。 在600毫安的负载下， 额外的损耗大约是300毫瓦。 显然，当LDO附加到 切换器的输出时， 我们还需要考虑 一些额外的损失。
现在，在一些应用中， 我们可能需要 动态调整电源电压， 同时我们可能需要低噪声。 这方面的一个例子是一些测试 和测量应用程序，其中需要 动态输出电压缩放。
所以如果我们有一个 动态改变电压的DAC， 开关输出电压 和LDO输出电压之间的差异 可能会很大， 这可能导致高功耗。 因此，这里有一个设计思想， 通过配置开关作为跟踪预调节器， 以避免过多的热量。
基本上，我们有一个LDO。 我们用一个甲板来控制LDO的输出， 一个开关跟踪LDO的输出 并产生足够的输出电压 来支持这里的LDO。 我们避免了切换器的输出 和LDO的输出之间的大增量。 在底部突出显示的这个链接中 有一个关于这个 设计理念很好的博客。
使用LDO的另一个明显的权衡 是电路板空间。 LDO至少是另外三个BOM组件-- 例如，输入电容、LDO和输出电容。 因此，除了切换器之外， 将其安装在板上 可能是板空间的问题。
因此，为开关器节省船上空间的 一种方法是 使用一个电源模块，它集成了 电感器，在大多数情况下， 节省了空间。 实际上，这就为LDO电路 在直流对直流变换器之后的应用 提供了空间。
我们提到了节电模式和LC滤波器 可能无法衰减非常低的 开关频率的事实。 这是假设，再一次， 一个LC滤波器 不是很大的尺寸，它的设计是 过滤全开关频率的转换器。 因此，LDO在过滤低频纹波方面 天生就能做得更好。 这里有一个例子。
左边的图中有一个空载开关， 但开关处于强制PWM工作模式。 所以开关器的开关频率是 一个全1兆赫的开关频率。 您可以看到，无论是带有 LC过滤器的切换器， 还是带有LDO的切换器， 在转换器的全开关频率下 都会产生非常干净的输出。
然而，在右边， 我们比较了将调节器 置于PFM模式时 输出噪声的变化。 同样，没有负载，所以 调节器的开关频率现在降到了 300赫兹而不是1兆赫。 所以你可以看到顶部的LC滤波器 不能很好地滤除低频噪声 因为它比LC设计的截止频率 低得多。
此外，设计一个LC滤波器， 将LC滤波器的大小设置为 300赫兹是不现实的。 这将是一个很大的过滤器， 很难把它放在板上。 同时，LDO在处理这种 低频噪声方面没有问题。 LDO PSRR特性很好地 解决了这个问题。
因此，让我们看看使用LDO 作为开关转换器输出的过滤器的 关键要点。 我们看到LDO可以帮助降低 低频纹波 和高频开关噪声。 如果开关器有某种节能模式， 在轻负荷下开关频率降低， LDO仍然可以很好地 滤除低频纹波。
高频开关噪声的降低依赖于 LDO在高频时的PSRR曲线， 这实际上依赖于 LDO输出电容的阻抗。 我们看到低调节问题 被LDO减轻了， 因为它有自己的回路 来调节输出电压。 与LDO设计相关的额外功耗、 额外的BOM计数 和额外的电路板空间 也需要权衡。
我们应该用什么-- LDO还是二级过滤器？ 我们看到LC滤波器在高频时 会变得很棘手。 设计者需要考虑输出电容 和电感的寄生元件， 可能需要滤波器阻尼， 使整体稳压器稳定。
LC滤波器可能需要比LDO 更低的BOM数， 但这实际上取决于在LDO 和LC滤波器设计中 使用了多少输出电容。 如果直流对直流开关采用节电模式， 那么LDO在这种低频下 一定可以提供更好的滤波效果。
在设计方面，LDO非常简单。 所以在我看来，LDO方法 可能更简单，更有益。 请记住，LDO之后总是可以 有一个高频电容来清除 剩余的开关噪声。
综上所述，我们发现了解噪声源 对于降低噪音非常重要。 我们看到寄生元素通常 会引起噪音方面的问题。 适当地测量噪声可以为我们 在设计滤波方案时 节省大量的精力。
我们看到有很多降噪技术。 我们讨论了布局， 组件的放置，堆叠， 一些高频电容滤波， 以及不同的封装选项 和调节器选项， 如电源模块。 我们看到，二阶LC滤波器和LDO 可以有效地清除输出噪声， 包括低频纹波 和高频开关噪声。
考虑到我们所做的所有权衡， 我们得出结论，LDO可能是 提供更清洁输出电压的首选方案。 这就结束了这次演讲。 感谢大家的收看。