Understanding Power Integrity as a System-Wide Challenge

By definition, power integrity in ICs is the practice of verifying that all the transistors on a chip have proper voltage to operate at their intended performance levels. A power-delivery network (PDN) is a complex chain of interconnects that delivers electrons from a voltage regulator through the printed-circuit board (PCB), across the package, and through the on-die routing to the transistors themselves. While each aspect of the system’s design can contribute to power-delivery noise, to accurately determine the power integrity of a design one must consider the electronic interactions between chip, package, and system (CPS).

This tutorial will decompose the problem of CPS power integrity. It will offer chip-level explanations of the analyses of static IR drops and time-domain dynamic voltage drops. Subsequently, it will demonstrate these analyses in the context of the complete system, as it adds package and PCB models to the analysis framework. And, it will examine the value of CPS frequency-domain simulation for its application toward minimizing frequency-dependent impedance and avoiding resonance frequencies.

Table Of Contents

Power Delivery Network Modeling and Time-domain Voltage Drop Analysis

A full understanding of the entire picture of CPS power integrity demands a look at the individual power-noise contributions from chip, package, and PCB. Starting at the receiving end of the PDN, on-die power is delivered through the IC’s power connections (wire bond pads or C4 redistribution layer (RDL) bumps), through the multi-layer power grid. The power grid inherently has non-ideal impedance, which will ultimately result in voltage drops at the transistors. In past technology nodes, we performed voltage drop analysis using a static IR-drop methodology (Fig. 1).

1. In this illustration of static IR-drop analysis modeling, we have connected a DC voltage source modeling the power supply to a chip model. Here, we model transistors as DC average current sources and model the PDN solely by its resistive properties.

A static approach models the transistors as time-domain average dc current sources, while extracting the power grid as a resistance network. Such a static, dc-average simulation ignores all time-dependent passive components. The full-chip PDN is stitched together as a mesh of current sources and resistors that subsequently solve Ohm’s Law (V = IR) to determine the voltage level at the transistors.

Since we have migrated into the deep-submicron technology nodes, analysis methodologies have shifted from an average IR-drop paradigm to a dynamic, time-dependent solution that more accurately represents the chip during its operation. In the time domain, power grid capacitance and inductance are included in the mesh. We now model the transistors themselves as time-varying current sources, which depend on the voltage, load, and input slew for each logic gate (Fig. 2).

2. In dynamic voltage-drop analysis modeling, we connect the power supply to a chip model where we model the transistors as time-domain current profiles that are a function of load, VDD level, and input slew. We completely model the PDN with its R, L, and C components, necessary for dynamic simulation. All capacitive coupling components are included.

The timing of an IC cell’s switching is a critical factor in correctly analyzing the impact of the PDN. A large number of locally placed transistors firing at the same time will have a cumulative effect on the peak current demand in a particular region. Standard-cell capacitance comes into play as charge accumulates both on intentional decoupling-capacitor (decap) cells, as well as non-switching standard cells.

The current demanded by the dynamically switching transistors must be supplied by the charge accumulated on these nearby cells, or from the off-chip regulator, resulting in dynamic voltage drop. In addition, the extracted power-grid mesh must now consider capacitive and inductive coupling where these passive elements become a factor due to their time-dependent behavior. Traditional static IR analyses ignore the time-dependent inductance and capacitance. Therefore, the PDN’s resistance plays the only analytic role during static analysis.

In summary, a dynamic transient power analysis involves the resistance, capacitance, and inductance parasitics of the chip and the switching current demand () of each cell during its operation. Solving for voltage becomes a function of the following equations: V = IR, V = L(di/dt), and I = C(dv/dt). Once the complete mesh is stitched together, a transient circuit solver is used to determine the time-varying voltage v(t) at each transistor. After that, sign-off criteria can be weighed against the results.

System-Wide PDN

As mentioned above, a system’s PDN reaches the chip through the package and PCB network. To ensure the chip receives adequate stable voltage, the package and PCB design must reduce impedances at all frequency ranges. As technology scales, the drive for reduced cost and lower power is contributing to package and PCB design complexity.

For example, to reduce package cost, designers seek to minimize the numbers of layers allowed for package implementation. Low-power design methodologies now routinely create multiple power domains so non-critical on-chip blocks can receive a reduced voltage, reducing power consumption compared with high-performance blocks.

Because of this trend toward lower costs and power consumption, we are seeing power-domain counts in the hundreds. Lack of routing real estate and increased numbers of power domains force designers to move away from the implementation of large planes dedicated to the power and ground domains. Instead, they resort to “Swiss-cheese” type structures, which significantly add to package and PCB design complexity, where the amount of routing layers is growing inversely to the power-domain count in modern electronic design.1

Ultimately, these trends are contributing to increased package and PCB impedance (Fig. 3). Before the power even reaches the die, the system experiences a voltage drop at the chip-package interface. This applies to static IR drop, but more significantly to dynamic voltage drop where time-dependent passive elements (especially inductance) play a critical factor.

3. Shown is an example of a modern 12-layer package layout. IC complexity and multiple power domains drive designs to take on complex geometries; increasing package impedances.

In comparison to the chip, package design typically is highly inductive in nature. The largest component of power-delivery voltage drop in a package results from the inductive voltage drop across the package as governed by V = L(di/dt) Package voltage drop itself can constitute 2% to 3% of the overall voltage drop seen at the transistors from the nominal supply voltage.1 As can be seen from the last equation, package voltage drop is indeed a function of the package’s extracted inductance, but it’s also scaled by the current demand di/dt of the chip.

The package’s voltage-drop contribution depends not only on the package itself, but also on the chip and PCB. This reinforces the importance of power analysis of the complete system. As seen in time-domain dynamic voltage drop analysis, a large amount of simultaneously switching instances can cause a cumulative spike in current demand from the chip, which in turn stresses the package, PCB, and ultimately the voltage regulator model (VRM). These spikes in current are a major cause of design failure, especially in high-current modes such as automatic test pattern-generation (ATPG) test mode, where simultaneous switching is encouraged to ultimately save time and money on automated test equipment (ATE) machines.

Minimizing Frequency-Domain Impedance

It is also important to solve system-wide power integrity in the frequency domain. Because impedance is a complex metric, Z(, the impedance of the system varies as a function of frequency. Designers must ensure the PDN impedance is under the specification limits at the design’s operating frequencies. Typically, engineers look at the impedance at the chip-package interface where the package connects to the RDL’s C4 bumps.

In general, chips and PCBs are more capacitive with respect to their package counterparts. Likewise, packages are largely inductive compared to the on-die and PCB PDN’s inductance. With this assumption, the frequency of the impedance peaks (or resonant peaks) of the system are largely determined by the LC resonance between chip-package and package-PCB as determined by .2

There are two main resonant peaks in a chip-package-PCB system. Because of the large size and capacitance of the PCB, the coupling between package and PCB determines the lower frequency peak that typically resides in the range of 10 MHz to 500 MHz, depending on the size of the PCB and amount of placed capacitance. The package-chip coupling determines the higher-frequency peak (1 GHz to 5 GHz), which depends largely on package inductance, the more variable metric in the equation, where L refers to Lpackage and C refers to Cdie.

Avoiding the resonant peaks is critical for the power integrity of a system. Package and PCB designers will use techniques such as adding decoupling capacitance to not only lower the frequency of the peaks, but also to suppress their magnitude. In addition, chip designers will insert decoupling-capacitance cells to lower the frequency of impedance peaks, but will also avoid switching the on-die transistors at the frequencies around the resonant frequency that is associated with their power domains (Fig. 4).

Simply determining resonant peaks based on one component of the system (whether chip, package, or PCB) provides an incomplete solution, as each component uniquely determines the frequency and magnitude of the peak it corresponds to. The best solution for PDNs is to solve for a CPS solution that includes an IC chip power model, package model, and PCB model simultaneously with electromagnetic field solvers. Impedance peak determination is a must-have step in the power integrity sign-off of IC design, as these peaks coincide with the maximum impedance values of the system.

Maximum impedance is scaled by a parameter known as the quality factor (or Q), which can be related proportionately to Q ~ , where Z is the impedance of the system. In oscillator theory, a higher Q indicates a lower rate of energy loss relative to the stored energy of the oscillator; the oscillations die out more slowly. Physically speaking, Q is 2π times the ratio of the total energy stored divided by the energy lost in a single cycle, or equivalently the ratio of the stored energy to the energy dissipated over one radian of the oscillation.3

For an ideal series RLC circuit, which can be used to represent a chip-package-PCB PDN, Q is defined as , an equation that refers to the parasitics of each component of the system. In a PDN system, the architecture largely determines the resistance and inductance. In turn, that architecture is bound to the main goal of PDN routing—getting power from the voltage regulator to the transistors, in multiple power domains, without congestion or shorting.

In other words, there is a lack of freedom to adjust PDN routing significantly enough to reduce L or increase R. As with resonance frequency adjustment, designers will add capacitance on the chip, package, or PCB with a sub-linear effect on the peak impedance. Minimization of peak impedance contributions from CPS resonance is critical, as it directly influences the power noise seen at the chip-package interface. Hybrid electromagnetic field solvers provide the Q of the entire system, including decoupling capacitors from the IC to the PCB.

Avoiding Resonant Frequencies

When the current flow of a power domain happens to coincide with its resonance frequency, an undesired ringing effect occurs due to exaggeration and temporal extension of power-domain noise. The voltage potential at the C4 bumps of the design takes on a diminishing sinusoidal form, whose magnitude and time to dampen are determined by the quality factor of the system (Fig. 5).

5. Shown is an example of a time-domain simulation of a chip, package, PCB analysis that operates around resonant frequency. The top waveform shows the current demand of the switching instances of the chip versus time. The center waveform is the current flow from battery to the chip versus time. At bottom is the voltage noise seen at the bumps. Note the exaggerated noise ringing effect at the bumps.

Avoiding resonant frequencies is critical in ensuring power integrity. A design might be under the voltage-noise limits for normal conditions, but operating at resonant frequency will usually result in failure due to the exaggeration of power noise. Studies have shown that out of all possible switching scenarios for a chip’s operation, we see the highest drop when the switching noise profile has the most frequency content around the resonance frequency of the system.4

In the above example, voltage noise seen at the bumps degrades to 94% of ideal voltage in a chip-only dynamic voltage-drop analysis. However, once we add package and PCB models to the analysis and see resonance, voltage drop exceeds 12% of ideal voltage. As can also be observed, voltage and current overshoots occur, which is an effect of resonant ringing.

Summary

Numerous factors contribute to the power noise of a system. The chip, package, and PCB each contribute to power noise individually, but the mutual interaction of the three affects numerous power-integrity issues. This is borne out by time-domain voltage drop analysis, minimizing of frequency-domain impedances, and avoiding resonant frequencies. Thus, it is preferable to analyze power integrity in the context of the complete system to solve the complex interactions.