Verification alive and well at SoC virtual conference

MANHASSET, N.Y.  During the first EE Times System-on-Chip Virtual Conference, a panel on verification challenges raised pressing issues in the areas of cost, startups, impact of electronic sytem level (ESL) design, virtual plattforms and functional verification as a methodology.

"Verification is the single biggest challenge in the design of SoC devices and reusable IP blocks," said panel moderator Clive (Max) Maxfield, Vice President, TechBites Interactive.

Synopsys' Janick Bergeron said that ever increasing complexity of chip designs is increasing verification costs: "We can't buy more servers to throw more computer time at verification, that's not the answer." Rather the design community needs to work toward a continuum that takes designs all the way fom the highest abstraction level to RTL implementation with verification in mind thorughout the process, said Bergeron.

This continuum needs to be closed loop, said Nick Heaton, Senior Architect, Cadence Design Systems: "Too much of the verification methodology is in an open loop and we need to reign it into the design methodology."

Start-up verification companies are part of the solution in filling the gaps in the verification methodology flow. "A lot of niche verification problems to be solved can be by new point tools from start-ups," said Heaton. "Their contributions will pave the way for a full verification methodology flow within a design flow."

"Calypto saw the niche need to reduce power in RTL designs using our sequential analysis technology," said Tom Sandoval, chief executive officer of Calypto Design Systems at the panel discussion.

On the impact of ESL on verification, Sandoval predicted that ESL methodology is bound to be become part and parcel of chip designs. "I see that we do not have many representatives from Japan at this panel discussion. If there were, this kind of question would be superfluous. Japanese designers are fully engaged using ESL methodologies in the their consumer devices designs. They have seen the system design benefits of using ESL in designing and verifying their chips for the past two years."

"We are at a tipping point of getting designers to use ESL methodologies," said Cadence's Heaton.

"I think we had a tipping point for using ESL at last year's Design Automation Conference when the TLM 2.0 standard was released," said independent consultant Brian Bailey. "It allowed for interoperability of models. Since then the industry has made tremendous progress. But we need metrics to know when and what kinfd of verification has been performed on our designs."

There is room for using virtual platforms to verify designs as well. Bailey inferred that Synopsys has hinted at a hybrid prototype that they are working on, which pulls in all the required data from an FPGA into the virtual platform just like with emulators today. "This way first chips out the door will be able to be tested using a model from the virtual platform."

Synopsys' Bergeron would not comment on the company's future offerings. Earlier this year the company formed a verification IP (VIP) alliance program to provide designers access to a broader range of Verification Methodology Manual (VMM)-enabled verification IP. "We need verification metrics we can rely on, and the VIP program was our contribution," said Bergeron.