Peter Stuge wrote:
>> I see the correctness of our CPU model being compromised here..
>>>> Please write a little about sockets vs. CPUs?
>> Why is there a socket?
>> What are sockets used for?
> (Grouping CPUs is not the answer I'm hoping for.)
>
When you describe a mainboard (think devicetree.lb), you usually don't
have a CPU on there, but a socket.
There is a certain choice of CPUs you can put into that socket. The
socket decides which CPU drivers to
include in the coreboot image. These drivers include
- MSR setup
- microcode updates
- power management setup
- cache setup
Especially due to microcode it's not possible to make this completely
generic: All microcode for all Intel CPUs alone is more than 500kb
It's less about grouping CPUs but more about a clean device model. If we
want coreboot to be easily understandable, we need to make it reflect
what hardware looks like, logically. I think Ron has brought up some
pretty good reasons for moving the CPU capabilities into the sockets
(Which is a hack we need because of romcc - Enabling MMX and SSE per
socket is only needed because romcc needs to work without cache or
memory. We might want to add that as a comment to the socket Kconfig)
Stefan
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