The CY7C341 is an Erasable Programmable Logic Device(EPLD) in which CMOS EPROM cells are used to configurelogic functions within the device. The MAX

®

architecture is

100% user-configurable, allowing the devices to accom-modate a variety of independent logic functions.

The 192 macrocells in the CY7C341 are divided into 12 LABs,16 per LAB. There are 384 expander product terms, 32 perLAB, to be used and shared by the macrocells within eachLAB. Each LAB is interconnected with a programmable inter-connect array, allowing all signals to be routed throughout thechip.

The speed and density of the CY7C341 allows them to beused in a wide range of applications, from replacement of largeamounts of 7400-series TTL logic, to complex controllers andmultifunction chips. With greater than 37 times the function-ality of 20-pin PLDs, the CY7C341 allows the replacement ofover 75 TTL devices. By replacing large amounts of logic, theCY7C341 reduces board space and part count, and increasessystem reliability.

Each LAB contains 16 macrocells. In LABs A, F, G, and L, eightmacrocells are connected to I/O pins and eight are buried,while for LABs B, C, D, E, H, I, J, and K, four macrocells areconnected to I/O pins and 12 are buried. Moreover, in additionto the I/O and buried macrocells, there are 32 single productterm logic expanders in each LAB. Their use greatly enhancesthe capability of the macrocells without increasing the numberof product terms in each macrocell.

Logic Array Blocks

There are 12 logic array blocks in the CY7C341. Each LABconsists of a macrocell array containing 16 macrocells, anexpander product term array containing 32 expanders, and anI/O block. The LAB is fed by the programmable interconnectarray and the dedicated input bus. All macrocell feedbacks goto the macrocell array, the expander array, and the program-mable interconnect array. Expanders feed themselves and themacrocell array. All I/O feedbacks go to the programmableinterconnect array so that they may be accessed by macro-cells in other LABs as well as the macrocells in the LAB inwhich they are situated.

Externally, the CY7C341 provides eight dedicated inputs, oneof which may be used as a system clock. There are 64 I/O pinsthat may be individually configured for input, output, or bidirec-tional data flow.

Programmable Interconnect Array

The Programmable Interconnect Array (PIA) solves inter-connect limitations by routing only the signals needed by eachlogic array block. The inputs to the PIA are the outputs of everymacrocell within the device and the I/O pin feedback of everypin on the device.

Unlike masked or programmable gate arrays, which inducevariable delay dependent on routing, the PIA has a fixed delay.This eliminates undesired skews among logic signals, whichmay cause glitches in internal or external logic. The fixeddelay, regardless of programmable interconnect array config-uration, simplifies design by assuring that internal signalskews or races are avoided. The result is ease of design imple-mentation, often in a single pass, without the multiple internallogic placement and routing iterations required for a program-mable gate array to achieve design timing objectives.

Timing Delays

Timing delays within the CY7C341 may be easily determinedusing WarpTM, Warp ProfessionalTM, or Warp EnterpriseTMsoftware. The CY7C341 has fixed internal delays, allowing theuser to determine the worst case timing delays for any design.

Design Recommendations

For proper operation, input and output pins must beconstrained to the range GND < (V

IN

or V

OUT

) < V

CC

. Unused

inputs must always be tied to an appropriate logic level (eitherV

CC

or GND). Each set of V

CC

and GND pins must be

connected together directly at the device. Power supplydecoupling capacitors of at least 0.2

µ

F must be connected

between V

CC

and GND. For the most effective decoupling,

each V

CC

pin should be separately decoupled to GND, directly

at the device. Decoupling capacitors should have goodfrequency response, such as monolithic ceramic types.

Design Security

The CY7C341 contains a programmable design securityfeature that controls the access to the data programmed intothe device. If this programmable feature is used, a proprietarydesign implemented in the device cannot be copied orretrieved. This enables a high level of design control to beobtained since programmed data within EPROM cells isinvisible. The bit that controls this function, along with all otherprogram data, may be reset simply by erasing the device. TheCY7C341 is fully functionally tested and guaranteed throughcomplete testing of each programmable EPROM bit and all internallogic elements thus ensuring 100% programming yield.

The erasable nature of these devices allows test programs tobe used and erased during early stages of the production flow.The devices also contain on-board logic test circuitry to allowverification of function and AC specification once encapsu-lated in non-windowed packages.

This specification is a measure of the delay from input signal applied to a dedicated input to combinatorial output on any output pin. This delay assumes that no expander terms are used to form the logic function. When this note is applied to any parameter specification it indicates that the signal (data, asynchronous clock, asynchronous clear, and/or asynchronous preset) is applied to a dedicated input only and no signal path (either clock or data) employs expander logic. If an input signal is applied to an I/O pin an additional delay equal to t

PIA

should be added to the comparable delay for a dedicated input. If expanders are used, add the

maximum expander delay t

EXP

to the overall delay for the comparable delay without expanders.

8.

This specification is a measure of the delay from input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used to form the logic function.

9.

This specification is a measure of the delay from an input signal applied to a dedicated input to combinatorial output on any output pin. This delay assumes expander terms are used to form the logic functions and includes the worst-case expander logic delay for one pass through the expander logic.

10. This specification is a measure of the delay from an input signal applied to an I/O macrocell pin to any output. This delay assumes expander terms are used

to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by sampling production material.

11. This specification is a measure of the delay from synchronous register clock to internal feedback of the register output signal to the input of the LAB logic array

and then to a combinatorial output. This delay assumes no expanders are used, register is synchronously clocked and all feedback is within the same LAB. This parameter is tested periodically by sampling production material.

12. If data is applied to an I/O input for capture by a macrocell register, the I/O pin set-up time minimums should be observed. These parameters are t