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At the recently ended International Electron Devices Meeting 2002 (IEDM) Intel and IBM presented their 90-nm process technologies and reported about the benefits of the proprietary logic production technologies and the excellent results. However, each company used different techniques: IBM used the partially depleted SOI and Intel – the concept of the strained silicon in its "1262 process technology". Besides, each company used its own measuring system. IBM announced that its 90-nm CMOS process enabled the maximum self-excitation, and Intel, not using the auto-oscillation generation results, offered the fastest current transfer for the 90-nm silicon. According to Intel, the strained silicon enabled to improve the results by at least 20%.

Intel´s new 90-nm 1262 process technology will be launched on 300-mm wafer fabs next year for making the next-generation P4s codenamed "Prescott". To create the strained lattice Intel plans to use the epitaxial germanium dopant on the upper silicon layer with the moderate 17% germanium atom concentration. According to Intel, the change in the germanium atom quantities will enable the company to easily move to the 65-nm process technology without transition to SOI.

Besides, Intel will use the basis of 90-nm process technology to develop the new technology of making comm chips, combining the bipolar SiGe transistors, passive and other elements. The first chips, made using the Intel’s new 90-nm SiGe process are expected in about the late 2003 – early 2004.

By a twist of fate, for the last five year IBM has remained one of the most active adepts of the strained silicon, offering IEDM numerous research docs. However, it seems that Intel will launch this technology earlier than IBM and others. IBM plans to launch the strained- lattice silicon on SOI while moving to the 65-nm process technology.

The presented IBM´s 90-nm SOI process technology enables to speak of the auto-oscillation circuits with about 4.5-5 picoseconds latency.