UltraScale devices support many of the same features supported in 7 series devices. However, there are some useful new features, along with changes to severalexisting features. These new features and changes include:

Each I/O bank contains 52 SelectIO interface pins. In some devices, there are some HR I/O mini-bankscontaining 26 SelectIO pins, each with their own independent power supply andVREF pin.（HR bank支持只有26个IO的mini-bank）

Receiver offset cancellation is available for some I/O standards to compensate for processvariations (HP I/O banks only).

Digitally controlled impedance (DCI) is only available in HP I/O banks. DCI uses only one reference resistor per bank, 240Ω to GND on the VRP pin. The values of the driver orinput termination are determined by the OUTPUT_IMPEDANCE and on-die termination(ODT) attributes, respectively.

VCCAUX_IO only supports a nominal voltage level of 1.8V.

A SLEW value of MEDIUM is supported in HP I/O banks.

The DCITERMDISABLE port can control both DCI and non-DCI on-die input termination features in HP I/Obanks.

Where applicable, asserting IBUFDISABLE causes the input to the interconnect logic to be a 0.This is different from the resulting 1 after asserting IBUFDISABLE in 7 series devices.

The bit slice is effectively a physical layer (PHY) block that replaces and enhances thefunctionality of the Component mode primitives. This PHY block gives tightercontrol over timing and provides new features enabling higher data rate reception in UltraScale devices.

2、HD
High-density (HD) I/O banks are SelectIO resources designed to support a wide range of I/O standards with voltages ranging from 1.2V to 3.3V. HD I/Os are optimized for single-ended, voltage-referenced, and pseudo-differential I/O standards operating at data rates of up to 250 Mb/s. Limited support for true differential inputs (with external termination) is also available to support LVDS and LVPECL clock inputs. HD I/Os also contain interface logic including registers and static delay lines to support asynchronous, system synchronous, and clock-based source synchronous interfaces.

Every HD I/O bank contains 24 I/O pins. When defined as single-ended standards, HD I/O pins support input, output, and bidirectional operating modes. Paired I/O pins can be used to support differential standard functionality. For pseudo-differential standards, like DIFF_SSTL15, input, output, and bidirectional support is available. True differential standards, like LVDS_25, can only function as an input buffer.