The minimum feature size of integrated circuit continues to shrink. At 32 nm and smaller nodes, mask linearity
errors caused by short range proximity effects less than around 3um during the manufacturing of photomasks
become more significant in the overall lithography error budget. To address this, we have carried out a study that:
(1). models the short range mask error; (2). implements mask process correction (MPC) based on these mask error
models; and (3). verifies the mask process corrections. In this paper we will demonstrate that application of MPC
can significantly reduce mask errors with minimal increase in writing overhead.