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Dec. 18, 1962
3,069,659
H. A. SKOVMAND ETAL
DATA PROCESSING SYSTEM
Filed April 11, 1960
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INVENTORS.
BY
HARRY A. SKCNMAND
KENNETH R. SI‘DVMAND
FRASER and BOGUGY/
ATTORNEYS
Dec. 18, 1962
3,069,659
H. A. SKOVMAND ETAL
DATA PROCESSING SYSTEM
Filed April 11, 1960
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Dec. 18, 1962
H. A. SKOVMAND ETAL
3,069,659
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Filed April 11, 1960
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INVENTORS
HARRY A. SKOVMAND
BY KENNETH R. SKOVMAND
FRASER and 8060670
ATTORNEYS
Dec. 18, 1962
H. A. SKOVMAND ETAL
3,069,659
DATA PROCESSING SYSTEM
Filed April 11, 1960
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INVENTORS
HARRY A. SKOVMAND
KENNETH R, SKOVMAND
BY
FRASER and BOGUCK/
ATTORNEYS
Dec. 18, 1962
H. A. SKOVMAND ETAL
3,069,659
DATA PROCESSING SYSTEM
Filed April 11, 1960
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INVENTURS
HARRY A. SKOVMAND
KENNETH R. SKOVMAND
FRASER and BOGUCK/
ATTORNEYS
Dec. 18, 1962
H. A. SKOVMAND ETAL
3,069,659
DATA PROCESSING SYSTEM
Filed April 11, 1960
9 Sheets-Sheet 6
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BY
FRASER and BOG‘UCK/
ATTORNEYS
Dec- 13, 1962
H- A. SKOVMAND ETAL
3,059,659
DATA PROCESSING SYSTEM
Filed April 11, 1960
PROGRAM STEP N0. Q
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BY
INVENTORJI
HARRY A. SKOVMAND
KENNETH R. SKCNMAND
FRASER and BOGUCK/
ATTORNEYS
Dec. 18, 1962
H. A . SKOVMAND ETAL
3,069,659
DATA PROCESSING SYSTEM
Filed April 11, 1960
9 Sheets-Sheet 9
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INVENTORS
HARRY A SKOVMAND
KENNETH R. SKOVMAND
FIG.10
FRASER and BOGUCK/
ATTORNEYS
United States Patent 0
3,069,659
Patented Dec. 18, 1962
1
2
3,069,659
under the control of the stored program and de
cisions are made by wir d program. These and other
Jose, Calif., assiguors to International Business Ma
features, for full understanding of which reference should
be made to the above identi?ed application, permit in»
DATA PROCESSING SYSTEM
Harry A. Skovmaud and Kenneth R. Skovmand, San
line processIng of a continuous ?ow of a large amount
of data, and a great deal of ?exibility in processing, re
chines Corporation, New York, N.Y., a corporation of
New York
arranging and maintaining data. A cyclic recording de
Filed Apr. 11, 1960, Ser. No. 33,875
17 Claims. (Cl. 340—172.5)
vice, speci?cally a magnetic drum, is employed as a
“proress” drum to store and transfer data and instructions
This invention relates to systems for storing, process
used in the arithmetric and other processing operations.
ing and transferring data, and more particularly to sys
The process drum requires, as described therein, at least
tems which utilize a cyclic recording device in perform
three cycles or revolutions for completion of the normal
ing data processing functions.
transfer operation, in which an instruction calls for the
The principal functional units which are used in the
transfer of data from one track to another. Other parts
operation of modern data processing systems and com 15 of the system may therefore have to “wait” during trans~
puters include, as is well recognized, input, output, stor
fer operations, until the transfer operations are com
age, arithmetic and control units. While the control
ple-ted.
functions performed in different machines can vary
It is therefore an object of the present invention to.
widely, the control functions are usually considered to
provide a novel data processing system.
be directed to the internal activities by which operating 20
Another object of the preient invention is to provide
sequences and sub-sequences are selected and carried
an improved system for transferring data on a cyclic
out in orderly fashion. Thus the selection of instruc
tions, and the manipulation of internally stored data in
accordance with the instructions, are important parts of
recording device.
the control function.
A number of data processing systems wh'ch are cur
rently in widespread use employ multi-track cyclic record
ing devices as principal operative elements for perform~
Yet another object of the present invention is to pro;
vide an improved systems for addressing a cyclic record
25 ing de\ice with a counter which is cycled in different
count relationships with the recording device.
A further object of the present invention is to provide
an improved system for performing control functions in‘
ing the control function.
Instructions and data may be
an in-line data processing system at a higher speed thanv
stored on the recording device, and reproduced and re 30 has heretofore been feasible.
arranged in accordance with the needs of a program.
In accordance with the present invention, increased
These systems are required to select track locations on
speed may be given to systems which use cyclic record
the cyclic recording devices by choosing particular re
ing devices which are addressed by counters set in differ
cording tracks as well as speci?c unit or character posi
ent count re‘ationships to the cyclic recording device. In
tions along the tracks. A particularly advantageous form 35 stead of waiting to commence each subsequence in a
of system for selecting character positions on a cyclic
program w th the start of a cycle of the recording device,
recording device employs counters which are set in differ
two or more subsequences may be carried out in succes
ent count relationships and advanced with successive
sion during the same cycle of the recording device.
character positions. The counters may be set in such a
One speci?c system, given by way of example, em
manner as to have zero counts at the point at which an p'oys a magnetic drum on which instructions and data are
recording or reproducing is started, and a predetermined
recorded for use in and control of an in-line data process
?nal count when the needed number of character posi
ing system. In operations in which data is transferred
tions have been passed. With such systems relatively
from one track to another on the drum, the addresses
little equipment is needed for the selection of a sequence
from which the data is taken and to which it is trans
of character positions. Heretofore, however, the coun 45 ferred are established by counters which are advanced
ters have had to be advanced with respect to a ?xed
controllab'y as the drum rotates. The counters are set‘
reference point on the cyclic recording device. Each
with a given initial count, but are to provide a carry at
time access is sought to the recording device in such
the beginning of an address location, and to thereafter
arrangements, it is necessary to use a separate cycle of
provide counts corresponding to the number of char
the recording device, in order to begin with the ?xed 50 acters being transferred. In accordance with the inven
reference point. In consequence, where the steps of a
tion, however, the counters are not advanced beginning
program call for repeated access to the cyclic recording
with the reference marks on the drum but instead are
device, as for the transfer of data between different
advanced with variable times which are initiated with
tracks, the operation of the system as a whole may have
the start of the subsequences in which the counters are
to be delayed until a number of successive revolutions
to be used. After the counters are initially set the counts
of the recording device are completed. It is evident that
which they present are corrected to compensate for the
an increase in the speed of these data transfer operations
time relationship of the setting to the cycling of the
contributes directly to system capability and is highly
desirable.
magnetic drum. Due allowance is made for the time
needed for the correction. Thus several program sub
An example of a system which uses a cyclic recording 60 sequences may follow each other within the time interval
device for performing internal control functions is pro
of one drum revolution if the data to be used in the
vided in a copending application for patent entitled “Data
transfer is stored in successive positions on the drum.
Transfer Apparatus,” ?led by John H. Haanstra et 21].,
A better understanding of the invention may be had
Serial No. 565,293, on January 24, 1956. The system de
by reference to the following description, taken in con
scribed therein provides “in-line” data processing by
junction with the accompanying drawings, in which:
handling technical business transactions sequentially as 65
FIG. 1 is a simpli?ed block diagram of the principal
they occur and re?ecting each transaction concurrently
units of a system in which the present invention may be
in all accounts which it affects. A large capacity ran
employed;
domly addressed memory is utilized in a manner such
FIG. 2 is a block diagram of circuits for performing
that entered data is processed along with selected data
70 control functions in accordance with the present invention
A combination of a stored program and
in a manner to increase the processing speed of the ar
wired program is used whereby data transfer is
from storage.
rangement of FIG. 1, which circuits include a cyclic re
3,069,659
4
3
cording system, core buffer storage circuits, gating cir
drum 21 during various subsequences is applied along with
cuits and count correction circuits;
FIG. 3 is a block diagram of the cyclic recording system
of FIG. 2 utilizing a process drum and other elements;
FIG. 4 is a simpli?ed representation of the disposition Ct
and nomenclature of patterns recorded on the drum of
FIG. 3;
FIGS. SA, 53 and 5C are timing diagrams showing vari
ations with time of various signals arising in the operation
10
of the system of FIG. 3;
FIG. 6 is a block diagram of core buffer storage circuit
arrangements which may be employed in the circuits of
FIG. 2;
FIG. 7 is a block diagram of gating circuits employed
in the arrangement of FIG. 2;
instructions from the register 26 to comparator and core
buffer storage circuits 30 which, for present purposes, are
used to establish the number of character positions to be
transferred and also are used to buffer the flow of data
FIG. 8 is a block diagram of count correction circuits
employed in the arangement of FIG. 2;
FIG. 9 is a simpli?ed representation of data transfer
which is being transferred. Gating circuits 32 for the
control of subsequences and count correction circuits 34
for performing certain adjustments in order to assist in
the achievement of high processing speeds are coupled in
an integrated fashion to the cyclic recording system 20
and the comparator and core buffer storage circuits 30.
For simplicity of representation, the numerous couplings
between the different units, including many lines in par
allel, have been shown symbolically by only a few lines.
Each of the blocks is identi?ed as to the more detailed
?gure in the drawings to which it is equivalent.
The processing unit of FIG. 2 performs some subse
quences which are known as data transfers. In these sub
sequences a given amount of data is transferred from one
track on the drum to another, from one speci?ed address
to another speci?ed address. The individual steps of the
subsequences are known as, and hereafter referred to as,
operations on the process drum of FIG. 3, showing rela
tionships useful in explaining the system; and
FIG. 10 is a timing diagram, showing the variations
with time of various signals occurring during a typical
sequence of operations of the circuits of FIG. 2.
Referring now to FIG. 1, there is provided a diagram
of the principal parts of an in-line data transfer system
of the type described in the above identi?ed application
the Instruction Cycle, The Read (or From) Cycle and the
Write (or To) Cycle. As used in this sense, the term
“Cycle” should not be confused with the full rotational
cycle or revolution of the process drum 21, because a
for patent ?led by Haanstra et a1. Data pertaining to a
great many different accounts is maintained in a random
principal purpose of this invention is to make possible the
access, high capacity memory 10, which is preferably of
Write Cycles in a single revolution of the drum 21. In
the Instruction Cycle, the program counter 25 sets the
switching circuits 23 to derive an instruction in a given
completion of more than one of the Instruction, Read and
the type using a number of magnetic surfaced discs ro
tating on a common shaft and employing movable trans
format from a program track on the drum 21.
ducers which are positioned selectively at desired tracks
on individual discs. Input information for the system may
be derived from punched cards by an input card reader 11
containing card feeding and sensing equipment and associ
ated circuitry. The major control functions necessary to
the manipulation and storage of data are provided prin
cipally by a processing unit 12, the term “processing” here
being used to conform to the like designation of a part
of the system in the above identi?ed application.
The
processing unit 12 provides the necessary synchroniza
tion and rearrangement of data, as well as the arithmetic
and program control operations for the system.
Subsequent to the accomplishment of desired routines,
data signals from the memory 10 and the processing unit
12 may be used to actuate an output punch 14 or an output
printer 15.
Data pertinent to the current state of any
of the stored entries and other signi?cant relationships
may also be provided on command at a supervisory con
sole 16. All of the units are coupled to and derive power
from a power supply 17.
The many operative features of an in-line data transfer
system thus generally arranged cannot adequately be sum
marized in a satisfactory brief form, and reference should
be made to the copending application for an appreciation
of such features. The present invention, however, is con
cerned with the processing unit 12, and with like units in
different systems. A more detailed, but still general block
diagram of parts of the processing unit 12 is provided in
FIG. 2, to which reference now may be made. It must
be stated that those portions which are not pertinent or
necessary to a description of the present invention have
40
The in
struction is placed in the instruction register 26, which was
cleared at the completion of the previous instruction. The
instruction then controls reading of the desired data and
placement of the data in the core buffer storage circuits
30 during the Read Cycle, and transfer of the data to a
selected drum 21 location during the Write Cycle. Such
data transfers may have to be accomplished repetitively
many times, and may appreciably slow down the system in
some instances if each data transfer requires three drum
revolutions to complete.
Some details of the arrangement of the various tracks
on the drum 21 may be discussed with reference to the
The drum 21 contains a clock
45 drum 21 alone in FIG. 3.
track having a regular pattern of reference marks which
provide timing pulses suitable for the generation of a
number of timing signals in a manner to be discussed be
low. The transducers which are operatively associated
with the clock track, and the various other tracks, are
indicated only symbolically by arrows. The drum 21
also contains a group of instruction tracks and another
group of storage tracks, as illustrated in FIG. 3. For
simplicity, accumulator tracks for arithmetic and other
steps, and a number of tracks which are employed for
miscellaneous operations but which do not concern the
present description, have been omitted.
The manner in which instructions are coded in the pres
ent system is depicted in the designations used for the
various elements employed in the instruction register 26
of FIG. 3. Each unit of the instruction register 26 is des
ignated so as to correspond to a different character in
the instruction, and these designations provide convenient
been omitted for clarity and simplicity. Thus, the arith
reference terms for following the operation of the system.
metic units, the circuits by which the ?ow of input and
output data is controlled and the decision elements by 65 Each instruction consists of a series of ten binary coded
which program steps are chosen have not been shown.
decimal characters which are recorded on the process
drum 21 in sequence and entered into the instruction reg
The cyclic recording system 20 includes a rotating mag
ister 26 in sequence. The ?rst three units of the register
netic surfaced process drum 21 with which is operatively
26 are devoted to the characters which determine the
associated a timing pulse generator circuit 22 and magnetic
heads and switching circuits 23. A program counter 25 70 address from which data is to be transferred, with a
T1 control circuit 40 being used for the character which
and an instruction register 26 are coupled to provide con
designates the address of the storage track on the drum 21
trol of the operation of the magnetic heads and switch
from which data is to be taken. The address of the
ing circuits 23. The detailed arrangement of these ele
character position on the track is denoted in binary coded
ments and the gating circuits which couple them is shown
in FIG. 3, described below. Data derived from the process 75 decimal form by an A, counter 41 and a B1 counter 42,
3,069,659
5
6
Each track has one hundred character positions, so that
two decimal stages, such as the A1 and B1 counters 41
therefore denotes the Q character of the instruction, C8
the P character, and so on to CI] for the T1 character.
The program counter 25 operates, as is described in de
and 42, can present any count up to one hundred and can
tail in the above identi?ed application, to successively
choose any of the character positions. The B1 counter
42 presents the units value and the A1 counter 41 pre
sents the tens value for a given character position along
the recording track.
The next three elements of the instruction register 26
consist of a T2 control 43, for the character which desig
choose the stored instructions for data transfer as they
are needed.
The manner in which data is maintained and disposed
in the storage tracks is of signi?cance throughout the
entire operation of the system, and will not be explained
nates the track at which data is to be inserted during a 10 in detail. A representative storage track of the process
drum is shown at the right hand end of FIG. 4. In the
storage track, the ?eld separation used in the instruction
tracks is not employed. Instead, the storage track is
divided into one hundred character positions, numbered
from 00 to 99. Because of the direction of rotation of
the drum, however, the character positions pass a ?xed
data transfer operation, an A2 counter 44 and a B2
counter 45. The A2, B2 counters 44 and 45 present the
tens and units values, respectively, of the character posi
tion at which recording is to begin. Only the initial char
acter positions of the data locations are speci?ed by the
A1, B1 and A2, B2 counters, with the total number of
characters which are to be transferred being speci?ed by
magnetic head in the order 99, 98, 97 . . . 00.
Each of
the character positions, on both the storage and clock
an M register 46 and an N register 47. The various
counters 41, 42, 44 and 45 have inputs to which counter
tracks, is further divided into eight separate binary digit
(bit) positions as shown in the enlarged fragmentary
advance pulses may be applied. The carry outputs of the
B, and B2 counters 42 and 45 are coupled to the ad
vance inputs of the A1 and A2 counters 41 and 44 re
portion.
These bit positions pass a ?xed magnetic head
in the following sequence: BS, BX, B0, B1, B2, B4, B8
spectively.
and BR. The BS digit, for data characters, may be con
sidered to be a start digit, and the BX and B0 digits to
provide ?eld designations in a punched card code, or the
The N register 47 represents the units position of the
M-N counter, while the M register 4-6 represents the tens
like. The B1 and B8 digits provide the binary values
which constitute a decimal number, and the BR digit may
be considered to be a parity bit. With data characters,
these digits may or may not be present, in accordance
decimal stages are sufficient. Additional instructions may
be recorded in a P register 48 and a Q register 49 which 30 with the code employed for a particular character, but
a signal is provided for each bit on the clock track.
provide the remaining elements of the instruction regis
These clock track bits are then employed for the control
ter 26. The P and Q registers 48 and 49 are not em
position.
There being no more than one hundred char
acters in a track, no more than one hundred characters
can be transferred from one track to another and two
of timing and gating throughout the system described
herein, and are the bits referred to by the corresponding
ployed during data transfer operations, and have been
shown solely to complete the instruction register 6. In
practice, the instructions are derived from ‘the drum in a
designations in the drawings.
sequence which begins with the Q character and pro
ceeds through to the T1 character.
The cyclic recording system of FIGS. 2 and 3 also
includes a T1 register 50 and a T2 register 51 which are
Each bit position is further subdivided into three differ
ent phases, as shown in the ?nal enlarged fragmentary
view of FIG. 4. The three phases, termed successively
governed by the T1 control 40 and the T2 control 43,
¢A, ¢B and ¢C, occupy the major portion of the bit
40 space, but a slight ‘gap between ¢>C and the succeeding
plicity, that there are only ten storage tracks on the
bit space is provided for operative reasons. For like
reasons, a character position should be considered to
start after the ?rst phase of a BS bit, and to stop after
Instructions are distributed on the process drum 21
character late (CL), reference mark (RM) and character
respectively, so as to present the T1 and T2 characters to
the switching circuits 23.
Here it is assumed, for sim
the first phase of the next succeeding BS bit, instead of
process drum 21. Each of the T1 and T2 registers 50
and 51 therefore need only have a single decimal stage, as 45 precisely with the start of a BS bit and the end of the
next succeeding BR bit.
shown in the present example. It should be understood,
As is also shown in FIG. 4, on the left hand portion
however, that although only single lines are shown, the
thereof, the clock track which is employed on the drum
binary digits of the characters are presented from the
21 is divided into ten ?elds each having ten characters
various elements of the instruction register 26 and the
T1 and T2 registers 50 and 51 in parallel. Likewise 60 like those on the instruction tracks. In addition, how
ever, the clock track includes special spaces which are
suitable means are provided for clearing the instruction
devoted to added characters which may be termed the
register upon completion of the instruction.
early (CE) spaces. These positions are utilized to pro
in ten separate “?elds” for each instruction track. Ref
erence may also be made, at this point, to the represen 55 vide cyclical references for the operation of the system.
by which separate rotations may be distinguished and
tation of the drum 21 which is given in FIG. 4. The
operations may be synchronized to the successive revolu
ten ?elds, numbered from 0 to 9, are disposed sequentially
tions of the drum. The character positions on the drum,
around each instruction track. The direction of ro
including the special characters, may be spatially located
tation of the drum 21, however, is such that a given
by a permanently recorded pattern on the drum surface,
?xed magnetic head is passed ?rst by ?eld 9, then by 60
or by embedded magnetic segments. The actual position
?eld 8, then by ?eld 7, and so on. Individual ones of the
of
the reference mark may be assumed to be in the precise
instruction tracks are selected under control of the tens
center of the reference mark space.
stage of the program counter 25, while the ?eld de
As the drum 21 rotates at a substantially ?xed rate of
sired Within a track is selected under control of the
speed,
the pulses derived by a magnetic head associated
units stage of the program counter 25. As with the 65
with the clock track are applied to a timing pulse gener
storage tracks, there are assumed to be only ten instruc
ator 22 (FIG. 3) which includes circuitry for providing
tion tracks, so that no further stages of the program
timing signals to de?ne the different ?elds, characters, bits
counter 25 need be employed, for purposes of the pres
and phases. The timing pulse ‘generator 22 is described
ent description. The switching circuits 23 are controlled
in
the above identi?ed application, to which reference
in accordance with the characters which are provided to 70
should be made for a fuller understanding. Basically, the
select the instruction tracks or storage tracks for the re
timing pulse generator 22 includes a number of pulse
production or recording of data.
Each of the ten ?elds in an instruction track in
cludes ten character positions, identi?ed from C0 to C9,
but passing the heads in the order from C9 to C0. C9 75
generators, each of which is synchronized with and con
trolled by the clock track on the magnetic drum. A
number of ring counters may be employed, each controlled
by the clock track signals so as to cycle in synchronism
8,069,659
7
dressed by two buffer counters 56, S7 and a single char
acter register 58. Data inputs to the characier register
with one of the characteristic divisions of the magnetic
drum. Due allowance is made for the gap provided in
the successive ?elds because of the presence of the refer
ence mark and the CL and CE characters. As shown in
FIG. 3, one group of output signals is provided on ten
different lines and represents gating signals for the differ
ent ?elds on the process drum 21.
58 are provided sequentially during the R Cycle from the
magnetic head selection matrix 23 (not shown in FIG. 6)
which is coupled to the track from which data is to be
taken. These data inputs are applied through an input
AND gate 59 which is fully energized by coincident ap
plication of an R Cycle signal, and an R/W Cycle Gate
signal, generated in a fashion described in more detail
below. The buffer storage 55 has a single read wind
These successive ?eld
signals, F9 to F0, are gated out in synchronism with the
passage of the successive ?elds past the magnetic head
for the clock track on the process drum 21, as is shown in
FIG. 5. As also shown in FIG. 5, gate signals C9 to C0
for the successive character positions are provided on
successive ones of ten different character lines during
ing coupled through the single character register 58 and
an output AND gate 60 to the magnetic head section
matrix of the process drum. The output AND gate
60 is condilioned to pass the data signals to the track
the interval in which a ?eld gate is provided. Like rela
tionships hold true for the bit gates which are provided
at which data is to be recorded by the coincident applica
during the individual character gates, and the phase gates
provided during the bit gates. The relationship of the
tion of a W Cycle signal and an R/W Cvcle Gate signal.
Details of the operation of the core buffer circuits need
seen in FIG. 5C.
are stepped and by which reset and readout are accom
plished, have not been shown in detail. Brie?y, as suc
only be summarized here, because reference may be made
CE, the CL and the RM gates to the various ?eld gates,
to the above identi?ed copending application and because
and speci?cally to the F9 gate signal is shown in FIG.
5A. The manner in which a character interval is de 20 the operation of such devices may in any event follow
conventional techniques. For simplicity also the as
?ned between like intermediate points on the BS bit gate,
sociated circuits by which the buffer counters 56 and 57
instead of from the start of the BS bit gate, may best be
FIGS. 4 and 5 also illustrate various speed and timing
cessive characters are taken from one track on the process
relationships which may be observed in a practical ex
drum and passed through the selection matrix and the
input AND gate 59, they are applied to the single char
acter register 58. From the single character register 58,
empli?cation of a system in accordance with the invention.
The process drum 21 may be rotated at a speed such
that one revolution takes 10 milliseconds (rns.). With
one hundred character positions, plus a reference mark
position and a CE and CL position, each of the character
they may be writ‘len, a line at a time, into the buffer
storage 55 under the coincident control of the buffer count
er 56 which is disposed in the opposite coordinate from
positions, including the CL and CE positions, may be
the single character register 58. When a comparison
effected by the comparator circuit 54 indicates that the
desired number of characters have been transferred into
bit position thus requires 12 microseconds to pass a ?xed
point, and the three phase zones require approximately 35 the buffer slorage 55, the characters may be then trans
ferred out, onto a different track on the process drum.
31/2 microseconds each, with the gap between adjacent
The counters 56, 57 are reset to a starting condition by
phase zones being approximately 11/: microseconds.
the Buffer Reset signal.
When these relationships are observed and the system
During the W Cycle, the buffer counters 56, 57 are
is operated as described below, high speed operation is
maintained but adequate switching and control times are 40 concurrently operated in a sequence which causes the
characters to be read out in the same order in which they
assured.
were written into the buffer storage 55. This readout
A number of other signals are also used in the oper
con.inues at a rate synchronized with the process drum
ation of the system. These signals are externally gener’
to cause proper entry into the successive character posi
ated and conventionally found in such systems. Thus,
Start and Stop signals may be applied to generate a Master 45 tions of the process drum. When a comparison again
indicates that the desired total number of characters
Gate signal to govern the system. A Shared Drum Cycles
have been transferred, the Buffer Reset signal is again ap
signal (SDC) may also be externally provided, as by the
allotted a total time interval of 96 microseconds, with
the RM position being allotted 208 microseconds.
Each
plied to reset the buffer counters 56 and 57.
The other circuits which are shown in the comparator
generated by the system when the various pulses from the 50 and core buffer circuits 30 of FIG. 6 are described below
use of a manual switch, in order to operate the system
in the mode here described.
A Not Clock Error signal,
in conjunction with the generation of the various cycle
and gate signals.
The general organization and operation of the cyclic
recording system of FIG. 2, including also the coopera
timing pulse generator are properly cycled with relation
to each other, is provided by the system as an added
measure of safety. The Buffer Reset signal is provided
to reset the counters which address the core buffer storage
at the end of the ?eld from which an instruction is taken 55 tion with the comparator and core buffer circuits 30
during the Instruction Cycle, and upon detection of a
selected count by the comparator circuits, as will be evi
dent when the system is described in more detail below.
of FIG. 6, may now be discussed. The circuits by which
used for both the R and W Cycles.
For data transfer operations, comparator and core
buffer circuits 30, shown in detail in FIG. 6, are also em
ployed with the cyclic recording system 20 of FIGS. 2 70
together at their outputs through an OR gate 63 and ap
plied along with an I Cycle signal to another AND gate
and 3. In the comparator and core buffer circuits of
FIG. 6, as the principal units are a comparator circuit 54,
referred to the AB=MN comparator, and a one hundred
the data derived from the magnetic heads and switching
circuits 23, to another AND gate 66, which therefore
instructions are transferred from the process drum 21
include a group of ten ?eld ring AND gates 62 coupled
to the different outputs of the units stage of the program
For brevity hereafter, the Instruction Cycle will be
referred to as the I Cycle, the Read Cycle Will be referred 60 counter 25. The ?eld gate signals F9 to F0 are in
dividually applied from the ?eld ring of the timing pulse
to as the R Cycle, and the Write Cycle will be referred
generator 22 to the different ones of the ?eld AND
to as the W Cycle. In addition, Cycle Gate signals are
gates 62, so that a gate signal for the selected ?eld on the
also employed to denote intervals within the Cycle
instruction track is provided during only the one ?eld
signals during which an actual transfer of data is oc
curring. These Cycle Gate signals include an I Cycle 65 interval which is selected by the units stage of the pro’
gram counter 25. The ?eld AND gates 62 are coupled
Gate for the I Cycle, and an R/W Cycle Gate which is
character magnetic core bu?’er storage 55 shown only
in block diagram form. The buffer storage 55 is ad
65, output signals from which represent the I Cycle Gate
signal. The I Cycle Gate signal is applied, along with
passes the characters of the selected ?eld on the instruc
tion tracks. The individual bits of these characters are
r gated out by yet another AND gate 66, which therefore
3,069,659
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passes the characters of the selected ?eld on the instruc
tion tracks. The individual bits of these characters are
gated out by yet another AND gate 67, by concurrent
application of the bit gates BS to BR.
The gated data from the selected ?eld on the instruc
tion tracks is therefore provided sequentially to a group
of AND gates 70 to 79 which individually control the
counter 41 corresponds in value at this time to the number
of the character position from which the taking of data on
a storage track is to begin. If data transfer is to begin
from character position 61, for example, the A131 counter
41, 42 is set to 61.
The AlBl counter 41, 42 is then
advanced by counter advance pulses provided during the
R Cycle. The ?rst counter advance pulse is derived for
different elements 40 to 49 of the instruction register 26.
this mode of operation from the CE character position
Each of the AND gates 70 to 79 is conditioned to pass
(FIG. 4) and the succeeding pulses come from the BR
data by a different one of the character gates C9 to C0 10 bit signals for each of the following character positions.
as these gate signals are provided in sequence. Thus
As the process ‘drum 21 rotates, however, the number of
during the ?rst C9 character gate which is provided dur
the character position scanning past the magnetic heads
ing a ?eld the Q instruction is entered through the C9
becomes successively lower while the value presented by
AND gate 79 into the Q register 49. The sequence is
the A181 counter 41, 42 approaches 100. Because the
continued until the T1 instruction is entered through the 15 counter 41, 42 is advanced just before each character
Cl] AND gate 70 during the C0 character gate signal
position passes the magnetic heads, the counter reaches
into the T1 control 40.
the count of 100 and provides a carry pulse in the bit
time just preceding the arrival of the selected character
The selection of the desired track on the instruction
position at the magnetic heads for reading. This initiates
track portion of the process drum 21 is, as previously de
scribed, determined by the tens stages of the program 20 transfer of data from the selected storage track by starting
the R/W Cycle Gate signal. Referring speci?cally to
counter 25. The count presented thereby, during a par
ticular part of the program, is applied through OR gates
FIG. 6, the concurrent presence of the R/W Cycle Gate
signal and the R Cycle signal at the input AND gate 59
80 to the magnetic heads and switching circuits 23. Al
permits the successive characters from the magnetic beads
though data is read out from the entire track, data passes
through the AND gate 66 only during the interval in 25 to be entered into the buffer storage 55' in the manner
which the I Cycle Gate signal is provided.
previously described. This entry of the successive charac
The couplings and circuits which are employed with
ters thereafter continues until a full transfer has been
the drum 21 during the R and W Cycles are principally
effected, as determined by the generation of the MN Com
pare signal.
concerned with the remaining elements shown in the de
tailed views of FIGS. 3 and 6. The storage tracks on the 30
Because the A181 counter 41, 42 is set to a zero count
process drum 21 ‘are addressed fro-m the T1 register 50
at the start of the data transfer, it effectively counts the
and the T2 register 51 separately during these cycles. The
number of characters being transferred. Therefore, the
count presented by the T1 register 50 activates one set
comparator circuit 54 may make a relatively simple com
parison between the count presented by the AIBI counter
of inputs of a group of AND gates 82 which are fully
activated only during the R Cycle signal, while the T2
register 51 presents a count through other AND gates 83
which are fully activated only during the presence of the
W Cycle Gate. The signals appearing on the output
terminals of the AND gates 82 and 83 (which have been
35
41, 42 and that presented by the MN register 46, 47 to
establish when the transfer should stop. With equal
counts on the A13, counters 41, 42 and the MN register
46, 47' the MN Compare signal is provided, and the
grouped together for simplicity of representation) there
R/ W Cycle Liate signal is terminated, so that entry into
the buffer storage 5: is completed.
fore are provided at separate points in time and are com
On the next passage of the reference mark on the
bined into a single set of outputs through a group of OR
process drum 21 past the reading heads, for the mode of
gates 84. The signals are ultimately applied to the mag
operation in which drum cycles are not shared, the sys
netic heads and switching circuits 23 through the OR
tem then begins the W Cycle. The relationship of the
gates 80 ‘to which the program counter 25 is also coupled. 45 count set into the A282 counter 44, 45, and the manner in
In summary, therefore, the T1 register 50 controls the
which the count is advanced, is the same in principle as
selection of a storage track on the process drum 21 during
has previously been described in conjunction with the
the R Cycle, While the T2 register 51 controls the selection
A181 counter 41, 42. 1 he advance pulses are applied 10
of a storage track on the process drum 21 during the W
the B2 counter 45 of the A282 counter 44, 45 starting with
Cycle.
50 the RM position on the drum 21. Again, the R/W Cycle
The comparator circuit 54, the A181 counters 41, 42
Gate signal is initiated when the A232 counter 44, 45
reaches the count of I00 and provides the A2 carry. The
and the A282 counters 44, 45, however, determine the
characters to be transferred from and to the selected
characters stored in the buffer storage 55 (FIG. 6) are
storage tracks. Each of the counter stages 41, 42, 44 and
then read out in the order in which they were written in,
45 are coupled to ‘the coparator circuit 54, along with the 55 and directed back to the magnetic heads and switching
R Cycle signals and the W Cycle signals and the ?xed
circuits 23 for entry on the selected storage track of the
counts presented by the M register 46 and the N register
process drum 21 at the desired character position. This
47. The comparator circuit 54 has not been shown in
data transfer is completed when the A282 counter 44, 45
presents the same count as that presented by the MN
detail, but operates in conventional fashion to make a
comparison between the A18; counts and the MN counts 60 register 46, 47. This then completes the simplified ex~
during the presence of the R Cycle signal, and between
ample of the transfer of data from and to different storage
tracks on the process drum 21 in the mode in which the
the AzBz counts and the MN counts during the presence
of the W Cycle signal. An MN Compare signal is pro
l, R and W Cycles each use a single drum revolution.
vided whenever the input counts are equal during a given
Having thus described the general organization and 0p
cycle.
65 eratiohal sequence of such a data processing system, the
Taking the R Cycle ?rst, the discussion at this point
individual steps by which the various Cycle signals ‘are
may center about the manner in which a sequence of
provided may now be reviewed. Referring speci?cally to
characters is selected from a given track on the process
the gating circuits of FIG. 7, which correspond to the
drum when Shared Drum Cycles are not employed. In
gating circuits 32 of FIG. 2, and referring also to a por
this situation, each of the I, R and W Cycles is ‘allotted 70 tion of the arrangement of FIG. 6, there are shown a
a full revolution of the process drum 21 and each is
number of individual intercoupled gate circuits. For
initiated at the reference mark (RM).
During the R
simplicity and clarity, all coupling lines have not been
Cycle the A1131 counter 41, 42 is set to have a desired
shown, but the input signals provided to the various gating
count when the reference mark on the process drum 21
elements have been enumerated. The basic circuit ele
passes the magnetic heads. The count set into the AIBI 75 ments which ‘are employed include AND, OR and trigger
3,069,659
12
11
denote the time interval in which an instruction is to be
transferred from the process drum. At the completion
circuits of any of the types well known in the art. The
trigger circuits, which are here assumed to be bistable
multivibra-tors, are turned “on” by the application of
pulses to a selected one of the ‘two inputs, and accordingly
the input and output terminals which are used in ‘the “on”
of this transfer, the Cycle Complete signal is generated,
to initiate a sequence for turning off the various signals
arising during the I Cycle. Coincident application of the
Cycle Complete signal, a B1 pulse and the I Cycle sig
condition have been given like designations.
The different signals which are generated by the gat
no! to an AND gate 109 results in the provision of an I
Cycle End signal to turn off the I Cycle Ready trigger
ing circuits of FIG. 7 in the course of the performance
of a full data transfer operation include Cycle signals
101.
The I Cycle End signal also turns on the R Cycle
(the I, R and W Cycle signals), Cycle Ready signals 10 Ready trigger 110 to prepare for R Cycle operation. The
following BR Reset signal is then applied to an AND gate
(which may be considered to be transitional or prepara
tory signals for the different individual cycles) and
112 which is conditioned by the R Cycle Ready signal
“Cycle Gate” signals (I and R/W Cycle Gate signals),
to apply a reset signal to the I Cycle trigger 108 so as
to turn that trigger off.
which are signals which denote the intervals in which
instructions or data are transferred to or from the proc
15
The R Cycle Ready signal from the trigger 110 pre
In addition, various cycle control and reset
pares the gate circuits for the R Cycle, in which data is
signals are provided in obtaining and maintaining an
transferred from storage track on the drum to the buffer
ess drum.
storage. The R Cycle Ready signal conditions one in
put of an AND gate 113, which in turn provides a start
of the arrangement of FIG. 6 may thus be understood 20 signal for the R Cycle upon coincident application of an
SDC signal, a Start BO pulse and a C6 character gate
by following through the initiation and termination of
through a coupled AND gate 114. The Start R Cycle
the various individual signals which are generated in the
signal turns on the R Cycle trigger 116, providing the R
course of a complete data transfer operation.
Cycle signal. Character gate C6 is used to initiate this
Operations are initiated at a master stop trigger 90,
to one input of which start signals are applied to turn 25 cycle because of the time relationship which this char
acter gate establishes. It is known, because of the fact
the trigger 90 “on” so as to generate a Master Gate sig
that instructions are contained in different ?elds on the
nal. The master stop trigger 90 is turned off by stop
drum, that the previous instruction transfer will have
signals, applied to its remaining input. The Master
orderly sequence in the gating operations. The operation
of the arrangement of FIG. 7 and the pertinent portions
Gate signal is coupled to various control elements (not
shown) throughout the system so as to insure inactiva
been completed during character gate CO. It is further
30 known that a predetermined amount of time must be
utilized for accomplishing various switching and count
tion of the system when the master stop trigger 90 is
automatically or selectively turned off.
An important control function is also provided by a
Cycle Complete trigger 92 which is turned on by termina
correction operations to be described in more detail be
low. Four added character positions are allotted for this
the “on” input of the Cycle Complete trigger 92 so that
the termination of the various Cycle Gate signals turns
6), and data is transferred from the process drum to the
interval, these being de?ned by the C9, C8. C7 and C6
tion of any of the I Cycle Gate or R/W Cycle Gate 35 gates of the ?eld following the ?eld in which the ins-truc
tion was taken off the drum.
signals. The I and R/W Cycle Gate signals are applied
During the R Cycle, the R/W Cycle Gate signal is
through an OR circuit 94 and an inverter circuit 95 to
generated (as discussed below in conjunction with FIG.
buffer storage. On completion of this data transfer, the
termination of the R/W Cycle Gate signal causes gen
eration of the Cycle Complete signal to initiate a se
layed pulse generator responsive to the termination of the
quence in which the R Cycle Ready trigger 110 is turned
I Cycle Gate and R/W Cycle Gate to provide a signal
off by the R Cycle End signal from an AND gate 117
approximately equal to a character gate in duration.
Upon application of the next succeeding BR signal along 45 and the R Cycle trigger 116 is then turned off by the R
Cycle trigger Reset signal from the AND gate 119. The
with the Buffer Reset to an AND gate 93, 21 BR Reset
R Cycle End signal also turns on the W Cycle Ready
signal is provided which turns off the Cycle Complete
trigger 118, preparing the system for the final, W Cycle
trigger 92. Each actual data transfer operation there‘
in the data transfer operation.
fore terminates in generation of a Cycle Complete sig
In the W Cycle, data is transferred from the buffer
nal, followed by the BR Reset signal.
on the Cycle Complete trigger 92.
Shortly thereafter,
the Buffer Reset signal is provided as by the use of a de
To prepare the gating circuits for the 1 Cycle opera
tion, the start signal is applied through an OR circuit
100 to turn on an I Cycle Ready trigger 101.
The I
storage back to a selected address on a selected storage
track on the process drum. As with the commencement
of the R Cycle, the coincidence of an SDC signal and
Cycle Ready trigger 101 is also turned on by W Cycle
a Start BO signal at an AND gate 120 are detected to
end signals from the previous data transfer. so a sequence
activate a second AND gate 122 which is conditioned
by the W Cycle Ready signal so as to provide a Start W
Cycle signal. The Start W Cycle signal turns on the W
may be intiated at some intermediate point in a drum
cycle. The circuits then effectively check for various
system conditions of operation. An AND circuit 102
detects the coincident presence of a “No Clock Error"
signal and the Master Gate, and primes an AND gate
104 to which are also applied the B0 signals. Output
signals from the AND gate 104 are applied along with
the SDC signals to an AND gate 105 to generate what
may be considered to be Start BO signals. Finally, the
signals for the start of the I Cycle are generated by an
AND gate 106 which is conditioned by the I Cycle
Ready signals and which receives the Start BO signals.
Cycle trigger 124, with the R/W Cycle Gate signal being
generated within this cycle time to control the actual
transfer of data from the buffer storage back to the
process drum. In terminating the W Cycle, the Cycle
Complete signal, along with the coincident B1 pulse and
the W Cycle signal, together activate an AND gate 125
to provide the W Cycle End signals to turn off the W
Cycle Ready trigger 118. The following BR Reset signal
and the I Cycle Ready signal from the trigger 101 which
is activated by the W Cycle End signals, then operate
The Start I Cycle signals turn on the I Cycle trigger
108, with the signals from the “on" output terminal of
an AND gate 126 which resets the W Cycle trigger 124.
the I Cycle trigger 108 providing the I Cycle signals
trigger 124 are both turned off and the system is again
in its initial state of operation, with the W Cycle End
for the system. As was discussed above in conjunction
with FIG. 3, to which brief reference may now be
made, the I Cycle signals condition an AND gate 65 of
FIG. 3 to which the various ?eld gates are also applied,
Thus, the W Cycle Ready trigger 118 and the W Cycle
signal being passed through the OR gate 100 to turn
on the I Cycle Ready trigger 101. An instruction regis
ter reset signal is obtained from AND gate 127 by com
and the I. Cycle Gate signal is generated thereby. to 75 bining the I Cycle Ready signal with the not I Cycle Gate
3,069,659
13
14
signal. The instruction register 26 is therefore cleared.
counter and A, counter 42 and 41 respectively, are shown,
Consequently, the same sequence may be repeated on
successive steps to provide further data transfer opera
tions.
although it will be understood that the coupled gating
The R/W Cycle Gate signal is generated by the ele
ments shown in FIG. 6. An R/W Cycle Gate trigger
128 is arranged to be turned off by MN Compare signals
from the comparator circuit 54. The trigger 128 is
turned on, however, by a combination of gates which
insure proper timing. A1 carry signals applied through
an OR circuit 130 to the on input terminal of the R/W
Cycle Gate trigger 128 indicate that the transfer from
elements are also connected in like fashion to the various
stages of the B2 and A2 counters 45 and 44 respectively.
The B, counter 42 is a binary coded decimal counter
consisting of four stages, separately identi?ed as the
B=l, 8:2, 3:4 and 3:8 stages. The output termi
nals of the various stages 140 through 143 are coupled,
as shown in simpli?ed form, to the comparator circuits.
The intercouplings between the various stages 140 through
143 have been omitted for clarity, the only input cou
plings which are shown being the advance signal input
- to the B:l stage 140, this being the input terminal to
which counter advance signals are applied. In like man
Inasmuch as the generation of the R Cycle signal is
delayed suf?ciently to insure proper count correction, 15 ner, the A, counter 41 consists of four intercoupled
the A1 carry may be used virtually instantaneously there
binary coded decimal stages A=l, A=2, A=4 and
A=8 numbered 145 through 148 respectively. Again,
after in the generation of the R/W Cycle Gate.
the output terminals of the various stages 145 through
With the W Cycle signals, however, a different arrange
ment is employed. W Cycle Ready signals are applied
148 are coupled to the comparator circuits and the inter
to a single shot multivibrator 132, the output terminal 20 couplings between successive stages are not shown. The
A=l stage 145 is advanced by “one count correction”
of which is coupled through an inverter 133 to an AND
pulses and by B1 carry pulses from the B1 counter 42
gate 134- to which the A2 carry signals are also applied.
the storage track of the process drum may commence.
The pulse introduced by the single shot multivibrator
which are applied through an OR circuit 150 to the
advance input. The A=2 stage is independently ad
the switching delays which are necessary following the 25 vanced by “two count correction" pulses applied to its
advance input from circuitry which is to be described
R Cycle End signal. On the cessation of this pulse, the
132 is selected to be of su?icient duration to encompass
output of the inverter circuit 132 conditions the AND
gate 134 and the A2 carry signal is passed through the
AND gate 134 and the OR circuit 130 to turn on the
below.
As was previously described, the B1 counter 42 is ad
vanced during the R Cycle. Because the R Cycle can
R/W Cycle Gate trigger 128. Data may then be trans 30 not begin until the C6 B0 time following the completion
ferred back from the buffer storage 55 to the process
of the I Cycle Gate signal, however, it is necessary for
drum. If an A2 carry signal is received prior to the
the B1 counter 42 to be corrected for this interval, so
completion of this delay interval, the system must wait
as to have a proper units count relationship to the posi
until the next cycle. In both instances of data transfer,
tion of the process drum. Five counts are needed, be
the MN Compare signal is used to turn oh‘. the R/W 35 cause of the fact that the counter is to be advanced prior
Cycle Gate trigger 128.
to each character position, and because counts are ar
The problems involved in increasing processing speed
ranged to begin relative to the CE position on the drum.
may therefore be visualized in terms of the states of the
Accordingly, the ?ve character positions which are used
various counters 41, 42, 44 and 45 of FIG. 3. The
are the C0 position of the 1 Cycle Gate, and the C9, C8,
counts which determine the addresses from which stored
C7 and C6 positions of the next succeeding ?eld. The
data is to be taken and to which it is to be transferred
C0 gate signal which is applied coincidently with the I
are not set into the instruction register 26 of FIG. 3
Cycle Gate signal to an AND gate 152 turns on a 3;
until the Instruction Cycle. Following the entry of the
counter advance control trigger 153 through an OR gate
instruction, the counts presented by the various counters
154. The BR gate of the C0 character gate and the next
41, 42, 44 and 45 are those intended to be presented at 45 four succeeding character gates are then applied through
the reference mark on the process drum, and not those
an AND gate 155 to the advance input of the 8:1 stage
at the position which the drum then occupies (at the
140 of the B1 counter 42, the AND gate 155 being con
completion of entry of the instruction). Because the
ditioned by the “on” output signal from the B, counter
ten character instruction may be entered in any of the
advance control trigger 153. This correction of the B1
ten different ?elds on the drum, the counts presented by 50 counter 42 is therefore uniform for each operation, be
the various counters stages will dilfer from the counts
cause the I Cycle terminates coincidently with a ?eld on
which they should have by correspondingly varying
the drum, and because the R Cycle begins in each in—
amounts.
stance a speci?ed number of characters later.
In providing a Shared Drum Cycle mode of operation,
Both the A1 B1 counter 41, 42 shown in FIG. 8, and
systems in accordance with the invention correct the 55 the A2 B2 counter 44, 45, which is not shown in FIG. 8,
counters for the actual position of the instruction as
are corrected in the units stage in the same manner.
rapidly as possible during and following the I Cycle. It
Each then counts BR pulses in a continuous cycle until
will be recalled that, as discussed above in conjunction
the instruction is completed, at which time the instruc
with FIG. 7, the R Cycle trigger 116 is turned on by
tion register 26 is reset by the instruction register reset
coincident application of the C6 and B0 gates to the 60 signals and the B1 Counter Advance Control trigger 153
AND gate 114. Accordingly, there is an interval from
is turned off by the same signals applied through an OR
some point in the I Cycle to the C6 B0 time of the
gate 156. Where more than one drum cycle is required
following ?eld in which the correction may be accom
to complete the instruction, the F0, C0 and B1 gates
plished. Because the entire instruction is entered previ
activate an AND gate 157 which turns off the B1 Counter
ous to the C0 character of the I Cyc'e Gate, ?ve charac 65 Advance Control trigger momentarily through the OR
ter times are available for this count correction. These
gate 156. The count is again initiated by the application
character times are, speci?cally, C0 of the I Cycle Gate,
of the reference mark pulse to the on input of the B1
and C9, C8, C7 and C6 of the next succeeding ?eld.
Counter Advance Control trigger 153 through the OR
To accomplish these count corrections, the I Cycle
gate 154 and an AND gate 158, which is conditioned by
Gate signal is used along with the Count Correction cir 70 the not I Cycle signal.
cuits in FIG. 8, to change speci?c stages of the A181
The correction of the A1 counter 41 proceeds in ac
counters 41, 42 and the A232 counters 44, 45 of FIG.
cordance with a de?nite program which is determined by
3 so as to place these counters in proper count relation
the address of the instruction presented by the program
ship to the cycling of the drum as quickly as possible
counter 25 of FIGS. 2 and 4. The counts presented by
after the I Cycle. Referring now to FIG. 8, only the B, 75 both the A=1 stage 145 and the A=2 stage 146 are
3,069,659
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15
applied through an AND gate 168, which is conditioned
corrected in the ?ve character times which are available
between C0 of the I Cycle Gate and the C6 character
by the “on" output terminal of a two count correction
gate of the next succeeding ?eld. If the ?eld occupied by
control trigger 170.
the instruction is odd numbered, a one count correction
pending upon the ?eld at which the instruction is located,
The B1 signals are applied, de
pulse is ?rst provided. Then a number of two count cor
during selected ones of the C9, C8, C7 and C6 character
rection pulses are provided during successive character
positions, as determined by the actual ?eld location of
the instruction. Referring to the count presented by the
times following the I Cycle Gate signal.
unit stage of the program counter as a program step,
the various correction counts which are needed, from 1
to 9, may be shown as successively generated during the
character gates C0 through C6 for the different odd and
even program steps as follows:
In general
terms, the operation may be considered to consist of
turning the two count correction control trigger 170 on
for a desired number of character times, to let the B1
pulse pass through the AND gate 168 to advance the A1
counter 41 by steps of two.
The two count correction control trigger 170 is turned
on upon cessation of the I Cycle Gate signal through
application of the I Cycle Gate signal to an inverter 171
which is coupled to one input of an AND gate 173. The
Odd Program Step __________________ -_
1
Even Program Step _________________ __
5
4
7
6
9
8
This table signi?es that depending upon the program
step, as presented by the units stage of the program
counter, a count correction is made which proceeds with
the successive character positions available until the de
sired ?nal correction count is reached. If the instruction
is contained in the ?fth ?eld, for example, so that 50
must be introduced in the count presented by the A1 B1
counter 41, 42, then a one count correction is provided
during the C0 gate, and two successive two count cor
remaining input of this AND gate 173 is responsive to the
X9 signals from the program counter, and the output
terminal of the gate 173 is coupled to the "on” input ter
minal of the two count correction control trigger 170. If
the ?eld in which the instruction is located is the number
9 ?eld, the two count correction control trigger 170 need
not be turned on, because only a one count correction is
needed. Otherwise, the two count correction control trig
ger 170 is turned on in each instance upon cessation of
the I Cycle Gate signal.
The AND gate 168 which passes the two count cor
rection pulses is closed by turning otf the two count cor
rection control trigger 170 at a proper time, as deter
rection pulses are provided during the following C9 and
mined by the actual ?eld position of the instruction on
C8 gates respectively. The one count correction is the 39 the instruction track. The remaining gating elements
same, wherever used, so that the operation of these por
control the turn-off time. A review of these elements will
tions of the count correction circuits may be conveniently
also provide a review of the various operating conditions.
separated into the one count correction part and the two
Where the instruction is contained in ?eld 9, as dis
count correction part.
cussed above, the two count correction is not used.
The one count correction operation centers about a
Otherwise, two count correction pulses are generated for
one count correction AND gate 160 which is conditioned
each successive pair of ?eld positions, starting with the
during the B1 C0 time of the I Cycle Gate signal by three
pair de?ned by the eighth and seventh ?elds. The X8
corresponding input signals. Odd program step signals
are provided to the remaining input terminal of the one
count correction AND gate 160 from individual ones of
a group of AND gates 162 through 166, each of which
detects the use in the program counter of a different one
of the odd ?elds in an instruction track.
All of this
group of AND gates 162—166 are coupled to the same
input of the one count correction AND gate 160 through
an OR gate 167. Taking a ?rst of the AND gates 162
as an example, the two input signals provided thereto
are the X9 terminal from the program counter 25 of
FIG. 3 and the F9 ?eld gate line from the timing pulse
generator 22 of FIG. 3, the designation “X9” is used to
identify the tens and units stage counts presented by the
program counter. Because the value of the tens digit
is determinative only of the instruction track which is to
be used and it is therefore not signi?cant to the count cor
rection process, it ‘is indicated only by an “X.” The rela
tionship established by the coincidence of the X9 and
F9 signals is that the program counter is addressing ?eld
number 9 of a selected track, and that the ?eld is at that
time under the magnetic head, so that the I Cycle Gate
and X7 signals from the program counter are coupled to
gether through an OR gate 175 and applied to an AND
gate 176, the remaining input of which is responsive to
the C8 character gates. The output terminal of the AND
gate 176 is coupled through a four input OR gate 177 to
the turn-off input of the two count correction control
trigger. During the 131 time of C9 character gate, there
fore, a two count correction pulse is passed through the
AND gate 168 to advance the A=2 stage 146 of the A1
counter 41, while the C8 character gate is used to shut oif
the two count correction control trigger 170 before fur
ther B1 pulses can generate two count correction pulses.
When the units stage of the program counter provides
50
counts which select the sixth or ?fth ?elds according to
the numbering system, the X6 and X5 signals are used in
conjunction with the C7 character gate in a series con
nccted OR gate 178 and an AND gate 179 which pass
55 signals through the OR gate 177 to turn off the two count
correction control trigger 170. Thus, the B1 puises pro
vide two count correction pulses through the AND gate
168 during the C9 and C8 times but are blocked off com
mencing with the C7 character gate. A similar combina
signal is being provided.
tion is used for the X4 and X3 signals from the program
Similarly, the coincidence of the X7 signal from the
counter, which are applied through an OR gate 181 and
program. drum and the F7 ?eld gate signal activates the
along with C6 character gates to an AND gate 182 for
next AND gate 163, and so on to the X1 and F1 signals
application through the OR circuit 177 to the off input of
which activate the ?nal AND gate 166 in this group.
the two count correction control trigger 170. Here three
The signals provided through the OR gate 167 from each 65 two count correction pulses are applied to the A=2 stage
of the AND gates 162 through 166 constitute “odd pro
146, as is need to set the A, counter 41 in the proper
gram step” signals which complete the activation of the
count relationship.
one count correction AND gate 160, so that the one
The remaining ?elds which are available for use on the
count correction pulse is provided through the OR gate
instruction track are those numbered 2, 1 and I}.
on an instruction track.
through C6 character gates, and stopped by application
The two count correction pulses applied to the A=2
stage 146 of the A1 counter 41 are de?ned by El pulses
of the C5 character pulse through the remaining OR gate
184 which is coupled to the OR gate 177. Where the
The
150 to advance the A=1 stage 145 of the A1 counter 41. 70 use of the number 2 or number 1 ?eld on the instruction
No one count correction pulse is provided in the remain
track requires four correction pulses, and these four pulses
ing instances, in which an even numbered ?eld is used
are provided during the B1 time of the successive C9
3,069,659
17
18
program counter selects ?eld number 0, the X0 signal
pleted in a single revolution with the I Cycle having re
quired a full previous revolution. Likewise, a W Cycle
of one instruction may be shared with the I Cycle of
applied to the OR gate 184 turns off the two count correc
tion control trigger 170 immediately, because then the R
and W Cycles must necessarily use the succeeding cycle
of rotation of the process drum.
The above completes the description of the operation
the next instruction.
Some further understanding of the coherent and or
derly progression of these subsequences in a Shared Drum
of the principal functional units of the system, as illus
Cycle mode of operation may be understood by reference
trated in the block diagram of FIG. 2. While this ar
to the timing waveforms and representative waveforms
rangement is complete, and will function as indicated in
illustrated in FIG. 10. The timing diagrams which are
all contingencies, an additional example may be given to 10 there included show the waveform variations which oc
illustrate a complete data transfer operation. The ex
cur at the designated points within the system. The ex
ample chosen is one in which, referring to FIGS. 9 and
ample chosen is the same as that used above with respect
10, the length and placement of the data on the data
to FIG. 9. Waveforms A, B and C represent the rela
storage tracks is so related to the instruction that the I,
tive placement and duration of the instruction ?eld, the
R and W Cycles may be completed in a single revolution 15 data in the FROM location and the data in the TO loca
of the drum.
tion for the example. Waveform D shows these com
bined waveforms relative to the ?elds of the drum in the
Referring speci?cally to FIG. 9, in the example given,
seven characters are to be transferred in accordance with
Shared Drum Cycle mode, and illustrates in linear form
the relative placements previously discussed with respect
program step 07 from an address beginning with character
position 61 on track W (an arbitrary designation) to an 20 to FIG. 9. Waveforms E, F and G represent the I Cycle,
R Cycle and W Cycle signals respectively, generated as
address beginning with character position 42 on data
storage track X (also an arbitrary designation).
The
control characters P and Q are not of pertinence to this
data transfer, and have merely been indicated for com
described in conjunction with FIG. 7.
The remaining waveforms and numerical designations
on lines H through U, are taken on an expanded scale
The numbering of the peripheral character 25 relative to waveform D, speci?cally the part ‘between the
beginning of character position 80 and the end of char
positions on the process drum 21 is merely intended to
acter position 54. On line H, the successive character
show the relative placement of the character positions,
positions have ‘been numerically designated. The I Cycle
between the different tracks including the instruction and
Gate signal, generated as described above in conjunc
storage tracks, with relation to each other and to the
pleteness.
record gap. FIG. 9 therefore provides a graphic illus 30 tion with FIGS. 7 and 3, is shown on waveform J as
being coextensive with ?eld No. 7, that is, beginning with
tration of the manner in which the subsequences of the
the start of character position 79 and ?nishing with the
data transfer operation are carried out.
The subsequence following the record gap selects the
end of character position 70. The R Cycle Ready sig
proper ?eld and track for the location of an instruction.
Here the program step 07 (track 0 and ?eld 7) is to be
nal shown in waveform K is commenced with the B1
gate which next follows the termination of the I Cycle
used. Therefore, during the 1 Cycle running from char
Gate signal. The R Cycle signal, however, commences
acter positions 79 to 7t) inclusive, the instructions con
tained at these character positions on the selected instruc
tion track are read out and entered into the instruction
at a later time beginning with the C6 character, here
character position 66, and the B0 bit gate which next
follows the end of the I Cycle Gate signal. Both the R
which is more than four characters behind the instruc
ce Gate time. The time interval during which the T1
character of the instruction is transferred is used to turn
on the counter advance control trigger (153 in FIG. 8)
at Ci! time of the I Cycle (iate signal. The advance
register. Subsequent to the entry of this instruction, what 40 Cycle Ready signal and the R Cycle signal terminate,
along with the R/W Cycle Gate signal, when the infor
may be called a “Cycle Gap" is provided which includes
mation has vbeen transferred from the desired storage
at least the C6 character position of the next succeeding
track on the magnetic drum, as indicated by the appli
?eld. Where at least this amount of spacing is not avail
cation of the MN Compare signal at the end of character
able, the system bcgins its next cycle of operation subse
position 55.
quent to the passage of the record gap at the read/write
As shown on line M, the entry into the instruction
heads, so that another full drum 21 cycle is emplo ed.
register begins in reverse order, starting with the Q char
Where, as in the present example however, the FRC‘M
acter and ending with the T1 character during the I Cy
location begins on a data track at a character position
tion location, relative to the magnetic heads, the data
transfer from the process drum 2.1 to the core bu?‘er
storage is accomplished during the same revolution of
the process drum 21. There then follows another Cycle
Gap, which need not conform to a speci?c number of
pulses which are applied to the B=l stage of the B1
counter 42 or the B2 counter 45 are supplied by the BR
character positions but should take a ?nite time so as to 55
pulses which immediately precede each successive charac
if any two of the placements and spacings are proper.
Thus both the I and R Cycles may be completed within
a single revolution and the W Cycle completed in the
next revolution, or the R and W Cycles may be com 75
B1 gate in the T1 character time. The two count correc
tion control trigger 170 (FIG. 8) is turned on at the ‘be
ginning of character position 69 and off at the end of
the same character position to pass through a single B1
ter position, as illustrated in waveform O. The counters
allow switching to be effected. Because, in the present
effectively continue the count until the remainder of the
example the PROM location begins at character position
revolution of the process drum.
61 and ?nishes at the end of character position 55, while
The counters must, however, ?rst be adjusted to counts
the TO location begins at character position ~52 and ?n
ishes after the end of the character position 36, there is 60 which place them in the proper relationship to the r0<
rational position of the process dru’n. These adjustments
more than adequate spacing and the W Cycle can be
must account for the position of the instruction relative
undertaken and completed in the same revolution of the
to the process drum. The remaining waveforms and rep
process drum 21. The remainder of the W Cycle, subse
resentations,
shown on lines P through U, graphically
quent to the end of character position 36 is a Cycle Gap
65 illustrate the count correction which is speci?cally de
and is not here employed.
scribed with relation to FIG. 8.
Where the relative positions of the instruction, the
Because. in the selected example, the instruction is
FROM location and the TO location are not in order,
located in ?eld No. 7, a correction of 3 in the tens stage
or overlap, a single revolution of the process drum 21
of each of the A1 B1 and A2 B2 counters is required.
is not su?icient to complete the I, R and W Cycles. Less 70 Accordingly, as shown on waveform P, the one count
than three full revolutions may, however, be suf?cient
correction pulse is generated during the provision of the
3,069,669
19
20
pulse so as to eifect the desired two count correction
a cyclic recording device in which data to be trans
which completes the correction of the tens stages. In
the meantime, the BR pulses which are passed through
beginning with character position 70 place the unit stages
ferred is maintained,
settab‘le counting means coupled to said recording de
vice for supervising data transfer operations,
of these counters in the proper count relationship to the
rotational position of the process drum.
The exact transition of the counts in the A; B1 and
A3 B2 counters may be seen by references to lines R and
means connected to said counting means to set a se
S in FIG. 1.
lected count therein in a given time interval related
to a cycle of operation of the recording device, and
means coupled to said counting means to establish a
new count in the counting means dependent upon
During character position 75, the units
count of "2" is set into the B2 counter, while during 10
character position 74 the tens count of "4" is set into the
A2 counter. Similarly, the units stage of the A1 B1 count
er is set to a “1” value during character position 72 and
the tens stage is set to a “6" during the succeeding char
acter position. These counts remain the same until the 15
beginning of the counter advance control trigger signal
provided when that trigger is on. Then, the units stage
of each counter is advanced by l by the advance pulses
(waveform O), and the tens stages are advanced by 10
is entered into said counting means.
4. A data transfer system including the combination of
‘a cyclic recording device in which data to be transferred
is maintained,
settable counting means coupled to said device for ad
dressing the cyclic recording device,
means connected to said counting means to set a count
therein selected in accordance with an instruction
and at a known time interval relative to the cyclic
by the various count correction pulses. Here, the one 20
count correction advances each counter by 10, and the
succeeding two count corrections advance each counter
by 20, while two successive advances are concurrently
made of the units stages. At character position 68, there
fore, the correction has been completed and the counts 25
are in the proper count relationship. The value presented
by the A1 B1 counter, illustrated on line R, which deter
mines the transfer frorn. a given location on the process
drum, provides a carry signal from the A1 B1 counter
when the 00 count has been set in, and this carry ini
the time during said interval that said selected count
30
tiates the R/W Cycle Gate signal for the R Cycle. When
the A1 B1 counter indicates the transfer of the desired
number of characters, here seven characters, the MN
Compare signal (also indicated in waveform U) is pro
vided to terminate the R/W Cycle Gate signal, as shown 35
on waveform T.
The above constitutes a complete description, there
operation of the recording device,
and means coupled to said counting means to change
the count thereof by an amount determined by the
relationship of the known time interval to the cyclic
operation of the recording device, in a time interval
immediately following the known time interval.
5. A data transfer system comprising
a cyclic recording device in which data to be trans‘
ferred is maintained,
settable counting means coupled to said device and ad
vanceable with the cyclic recording device for ad
dressing selected locations in the cyclic recording
device,
means connected to said counting means for setting
selected counts therein during selected time intervals
relative to the cycles of operation of the recording
device, and
means coupled to the scttable counting means for cor
fore, of the timing relationships of the different pulses
recting the counts therein depending upon the time
in atypical sequence involved in the Shared Drum Cycle
mode of operation. The W Cycle, which follows after 40
of occurrence of the selected time intervals to estab
lish a selected counting relationship to the cycles
the R Cycle, operates in a similar manner and need not
be described. No further count correction is necessary.
of operation of the cyclic recording device.
6. A data transfer system comprising
a cyclic recording device containing instruction data
and stored data,
settable counting means coupled to said device and ad
vanceable with the cyclic recording device for add
At the end of W Cycle, the instruction register reset
signal clears the instruction register and turns off the B1
counter advance control trigger 153. When a single drum
revolution cannot be shared by more than one of the I,
R and W Cycles, the system operation proceeds automati
dressing selected locations in the cyclic recording
cally, with the A1, B1 and A2, B2 counters in proper count
device,
relationship to the rotational position of the drum.
means coupled to said device for setting selected counts
While there have been described above and illustrated
into the settable counting means at known time in
in the drawings various forms of signal processing sys
tervals relative to the cycling of the recording de
tems for operating with a cyclic recording medium to
vice, and
effect data transfer operations in a minimum time, it will
means coupled to the settable counting means for cor
be appreciated that the invention is not limited thereto.
recting the counts set therein by amounts deter
Accordingly, the invention should be understood to in 55
mined by the relation of the known time interval to
clude all modi?cations, variations and alternative forms
the cycling of the recording device.
falling Within the scope of the appended claims.
7. A data transfer system including a cyclic recording
What is claimed is:
device,
1. A data processing system comprising
counters coupled to said device and synchronized there
a cyclic recording device ‘in Which the data to be
with for addressing the recording device,
transferred is maintained,
means coupled to said counters for setting the counters
a settab‘le counter means coupled to said recording
at variable time intervals related to the cycles of
device for supervising data transfer operations,
means controlling said settable counter means and
operatively coupled thereto to establish desired count 65
relationships to the cyclic recording device, and
means coupled to said settable counter means for
changing the desired count relationship of the setta
ble counter means relative to the cyclic recording
device depending upon the time of operation of said 70
controlling means.
2. A data processing system in accordance with claim
1 in which said settable counter changing means operates
in synchronism with the cycling of the recording device.
3. A data transfer system comprising
operation of the cyclic recording device, and
means connected to the counters for advancing the
counters in synchronisrn with the cyclic recording
device and for correcting the count therein by a value
determined by the time interval, relative to the cycling
of the device, in which the counters are set.
8. A data transfer system including
a cyclic recording device for storing data at successive
character positions and for storing instructions at
successive ?eld positions,
counters for addressing the recording device, said coun
ters being coupled to said device to be advanced
3,069,669
21
22
with the successive character positions on the record
during the count correction cycle to a seletced rela
ing device,
tionship relative to the cycling of the recording
device.
12. A data processing system including the combina
means coupled to said device responsive to individual
ones of the stored instructions for setting the coun
ters during time intervals determined by the ?eld 5 tion of
position from which the instruction was taken,
a magnetic drum having instruction tracks and storage
means connected to said counters responsive to the
tracks, the instruction tracks being divided into ?elds,
completion of setting the counters for de?ning a
count correction interval of selected duration, and
a counter coupled to said device for addressing the
storage tracks on the magnetic drum,
means connected to said counter for changing the set
means connected to the counter responsive to a selected
10
ting of the counters during the count correction in
terval by amounts corresponding to the ?eld posi
?eld on the instruction track for entering selected
counts into the counter, and
means connected to said counter for advancing the
counter by counts selected in accordance with the
position of the ?eld from which the instruction was
taken.
tion from which the instruction was taken.
9. In a data processing system utilizing a cyclic record
ing device and in which counter means for addressing
the cyclic recording device are set by instruction signals
at a selected time interval relative to the operative cycle
of the recording device, the combination including
13. A data processing system for accomplishing data
transfer operations including the combination of
a magnetic drum having instruction tracks and data
gating means connected to said counter means for
establishing a count correction cycle for the counter 20
means in response to the time relationship of the
storage tracks, the instruction tracks being divided
into ?elds and each of the instruction and storage
tracks including regularly spaced character and digit
positions,
setting of the counter means to the cyclic operation
of the recording device, and
binary counter means coupled to said data tracks for
controlling data transfer operations to and from
said data storage tracks on the magnetic drum,
means coupled to the gating means for applying a
series of correction pulses to the counter means to
advance the counter means during said correcting
cycle to a selected count relationship relative to the
means coupled to said drum to select an instruction
cycle of operation of the recording device.
?eld,
10. ‘In combination with a data processing system utiliz
ing a cyclic recording device for the retention of instruc
means coupled to said drum and said counter means
for setting the binary counter means to a selected
count in accordance with a selected instruction, and
means for applying count correction pulses to the
counter means in accordance with the position of the
30
tions and data, in which the instructions are recorded at
selected positions relative to the cycling of the recording
device, and in which timing signals are provided to de?ne
the cycling relationship,
?eld from which the instruction was selected and
the termination of the setting of the binary counter
transfer operations,
means whereby the counter means is placed in a
selected count relationship to the cycling of the mag
means coupled to said counter means for initiating a
netic drum.
count correction cycle in response to the position on
14. In a data processing system in which data transfer
the recording device at which a selected instruction
ll) operations are to be carried out and in which data is
is located, and
transferred from one track on a cyclic recording device
means coupled to said counter means for supplying a
selected number of timing pulses to the counter
to another track under control of an instruction posi
counter means coupled to said device supervising data
tioned at a given cycling relationship to the recording
device, the combination of
means to correct the count thereof during the count
correction cycle. said selected number of pulses being
dependent on the position of the instruction relative
to the cycling of the recording device.
binary counter means coupled to said device having a
plurality of stages for addressing the data tracks on
the recording device,
11. In a data transfer system utilizing a cyclic record
ing device in which instructions are maintained in different
means coupled to said counter means for setting the
counter means in response to selected instructions
count relationships to the cycling of the recording device,
and in which timing gate signals are derived to de?ne
successive ?eld, character and digit positions, the com
bination of
on the recording device,
means connected to said setting means for initiating a
count correction cycle in response to the setting of
settable counter means coupled to said device for ad
the counter means,
means connected to said counter means for terminating
dressing the cyclic recording device,
the count correction cycle in response to the rela
tionship of the instruction to the cycling of the
means coupled between said device and said counter 55
for selecting an instruction,
means coupled to said counter means responsive to
selected instructions on the cyclic recording device
for setting the counter means to values speci?ed by
said selected instruction,
recording device, and
means coupled to said counter means for applying cor
rection pulses to the stages of the counter means in
a regular sequence during the count correction cycle
in response to the cycling of the recording device.
60
means connected to said setting means for detecting the
completion of the setting of the counter means,
means coupled to said instruction selecting means for
manifesting the relationship of the position of the
instruction to the cycling of the recording device, and 85
15. The invention as set forth in claim 14 above,
wherein the means for applying count correction pulses
in a regular sequence includes
means coupled to said counter for de?ning a count cor
rection cycle initiating subsequent to the setting of
the counter means and terminating at a time deter
mined by the means for manifesting the relationship 70 of
of the position of the instruction to the cycling of the
recording,
said count correction cycle de?ning means including
gating means coupled to the counter means to enable
selected timing pulses to advance the counter means 75
means applying a one count correction pulse to the
?rst binary stage of the counter means and there
after two count correction pulses to the second binary
stage of the counter means.
16. A data transfer system including the combination
a magnetic drum in which instructions are recorded in
?elds and instruction tracks thereon, and in which
data is stored in data storage trucks thereon begin
ning with a reference mark on the drum,
program counter means coupled to said drum for ad