Designed and verified new ASIC block for real-time hardware decompression of proprietary run-length-encoded image format. Block was verified using directed test and SystemVerilog constrained-random test-bench. The block was integrated into an existing high-performance imaging pipeline.

Developed FPGA prototypes for other engineering teams, including: a quadrature-encoder resolution divider for interfacing high-resolution sensors to existing hardware systems; and an LVDS data stream demultiplexer for driving multiple serialized LVDS channels from a single ASIC channel.

Reflow oven controllerConverted a toaster-oven into a reflow soldering oven, using an AVR microcontroller, thermocouples, and solid-state relays; developed graphical control interface for oven in Python and QT; designed and tuned PID control loop using simulated system in Python.