DebuggingTechniquesUsingtheVivadoLogicAnalyzer

As FPGA designs become increasingly more complex, designers continue look to reduce design and debug time. The powerful, yet easy-to-use Vivado® logic analyzer debug solution helps minimize the amount of time required for verification and debug.

This one-day course will not only introduce you to the cores and tools and illustrate how to use the triggers effectively, but also show you effective ways to debug designs—thereby decreasing your overall design development time. This training will provide hands-on labs that demonstrate how the Vivado debug tool can address advanced verification and debugging challenges.

Release Date

June 2015

Level

FPGA 2

Training Duration

1 day

Who Should Attend

System and logic designers who want to minimize verification and debug time.