Intel Shows 2.5D FPGA at ISSCC

SAN FRANCISCO – Intel gave the most detailed look at its lower cost alternative to 2.5D packaging in a paper on its Stratix X FPGA at the International Solid State Circuits Conference (ISSCC) here. In the same session, AMD showed its Zen x86 processor sports a 10 percent smaller die than Intel’s latest 14nm CPUs.

The Stratix X uses Intel’s Embedded Multi-die Interconnect Bridge (EMIB) to link the FPGA with four external transceivers. The bridge is made using silicon die mounted in a BGA substrate which is significantly smaller than the silicon substrates used in the CoWoS process developed by TSMC and used by rival FPGA vendor Xilinx and GPU designer Nvidia.

EMIB uses a combination of 55 micron micro-bumps and 100+ micron flip-chip bumps to support up to 24 transceiver channels with 96 I/Os each. They deliver 2 Gbits/second/pin at 1.2 pJ/bit/die using a proprietary protocol.