SystemVerilog versus SystemC

Guruprasad PV, Prabu M (Global Edge Software)

Abstract

SystemVerilog and SystemC are the languages used for verification and hardware modelling. Both have features which are unique to each of them while some features are inherited from C++ language. Verilog concepts which are inherited in system verilog is not compared, but features with respect to C++ and hardware description is used for comparison. Objective of this paper is to help hardware engineer when switching between these two languages and to help new users to get familiarized with both the languages and reduce the ramp up time.

Introduction

This paper compares widely used features which is common between System Verilog and SystemC. Specific features which are unique in both have not used for comparison. For e.g package in system verilog is not taken for reference similarly in systemC threads and process is not taken for reference.

1. Data types

Feature

SystemC

Systemverilog

comments

Two state data type

short int, long int, sc_bit, char

variable vector size

sc_int<width>, sc_uint<width>, sc_bigint<width>

They can have different sizes

int, short int, long int, bit, byte

In systemC, some are inherited form c++ while others are part of SystemC package

Four state data type

sc_logic

Varable vector size sc_lv<width>

reg, integer, logic

------

Default value of wire

Signal depends on template argument

e.g.

sc_signal <sc_logic>abc

sc_logic is the template argument. This template can be any of systemC data types

Wire and variable types defaults to logic which is four state

e.g.

Wire abc is same as wire logic abc in system verilog

var i is same as

var logic i

In system verilog net defaults to logic which is 4 state whereas in systemC it can be either 2 state or 4 state based on template argument

Scope of variables

All local variables are default Automatic

All variables within function and tasks and module are default static.

All variable within automatic tasks and automatic functions are automatic

In system Verilog variables have to prefixed with the word automatic whereas in SystemC it has to be prefixed with static as default scope is different

Enumeration literals and declarations

Same as in C++

Few additional declarations and features are available

1. Enum{flag[2:0], host[2]}

is same as enum{flag2, flag1, flag0, host0, host1, host2}

2. enum {flag[5]} is same as enum {flag0, flag1, flag2, flag3, flag4}

3. literals can be other data types

enum bit[2:0]{a, b, c, d}

4. you can assign x and Z value to literals, if it is a 4 state type

e.g :

enum logic[2:0] {a, b=11x, c=001}xyz

4. Built in methods are available

Most of the other features like forward type declaration are available in both the languages

2. structures

Feature

SystemC

Systemverilog

comments

Structure types

Same as C++

There are two types of structure

a. variable structure

b. wire structure

e.g for wire structure

Typedef struct

{

logic clk;

logic [31:0] address;

}ctrl

wire ctrl signals;

-----------

Structure member initialization

It cannot be initialized during declaration

Members can be initialized during declaration

Typedef struct{

logic [3:0] a = 'b1011;

bit [2:0]b ='b110;

}bit_var;

--------------

Vector access

Vector addressing is possible using range(start, end) built in method

struct tag {

sc_bv<8> var;

sc_bv<8>var2;

}obj;

obj.var.range(5, 0) = 4

Vector access is possible for packed structure

Struct packed

{

short int shr;

int adr;

short int dhr;

}test1;

test1[15:0] coressponds to shr.

In system Verilog entire structure can be accessed using vectors but in systemC individual members can be accessed(systemC data type only)

system verilog

test1[16:0] = 17'h10001

would result in adr =1 and dhr =1

but in systemC you cannot access var and var2 simultaneously using vector

Structure memory struct abc

{

short int a;

short int b;

int c;

}xyz;

Variable a will be assigned the lowest address

variable a will be stored at highest address

If structure is occupying the space from 0x2000 to 0x2007 , a would be located at 2000 in systemC and variable C would be located at 2000 in system Verilog

3. Arrays and queues

Feature

SystemC

SystemVerilog

comments

Associative array

Same as C++ .

STL(Standard Template Library)

Supported

Built in methods are different for systemC and systemVerilog

Array access

Bit[4]ctr[20]

Bit [3:0]ctr[19:0]

or

bit[3:0]ctr[20]

In systemC range cannot be specified during declaration but range can be used for array access

Queue and built in methods

Available

Same as C++ .

STL(Standard Template Library)

They refer it as list and it as standard keyword

Available

Built in methods are same but syntax are different

4. Function and tasks

Features

System C

System Verilog

Comments/Differences

Tasks definition

There is no concepts of tasks

Task definition can exist inside the class or outside the class

Task is a verilog concept , it cannot be compared with SystemC

Functions

Supported

Supported

Implementation is similar

Variables and functions inside the class

They are referred as Data members

member functions

They are referred as

Class Property Class method

Properties of variables and functions are same

5. Class

Features

System C

System Verilog

Comments/Differences

Constants

instance constant

There are two types

1. Global constant

2. instance constant

// global constant can be assigned

Const int j =20;

//instance constant

const int j;

// j can be assigned later(run time)

Accessing common name variables

Scope resolution operator is used in derived class to access the variable with same name in base class

In derived class word super is used

---------------

Parameterized class

Available

Available

Syntax is different

Some of other features of c++ are more or less same in both with slight difference in syntax

e.g local keyword in system verilog is represeted as private in systemC

6. Module

Features

System C

System Verilog

Comments/Differences

Declaration

SC_MODULE (abc)

{

sc_in <bool/int/sc_logic>a,

sc_out <bool/int/sc_logic>b;

};

Module abc(a, b)

or

Module abc(input a, output reg b)

In systemC input and output declarations is done in body of the module while in system verilog it can be in port list or in body of module

In system verilog class and Modules are different but in systemC SC_MODULE will be treated as class internally. SC_MODULE is a macro which replaces class abc: public sc_module. sc_module is a predefined class

Assigning value to wires

In systemC write built in method is used to assign a value to signal

Assign statement is used

Assignment to wire can be done anywhere within scope of the signal

In system verilog it is outside always block

7. Interprocess communication and Synchronization

Features

System C

System Verilog

Comments/Differences

semaphores

Available

Available

Built in methods have different names but functionality is same

Mailboxes

NA

Available. It has built in methods

-----

Mutex

Available

it has built in methods

Not Available

-------

Event

Available

Available

In system verilog event hastriggered property and assigning of events is possible.

SystemC does not have triggered property and assigning of events is not possible

8. miscallaneous

Features

System C

System Verilog

Comments/Differences

Wait statement

Available

Available

System verilog has an additional wait _order statement

Constaint Random values to variables

Not Available

Available

In systemC verification library constraint random is available

If statements

Same as C++

Different types if statement

1. if

2. unique if

3. unique0 if

4. priority if

-------

Case statement

Same as C++

1. case

2. unique case

3. unique0 case

4. priority case

------------

Interface

Available

Available

Interface functionality is same in both but syntax is different

Conclusion

System verilog and SystemC cannot be compared for effectiveness as end target of both are different. System Verilog is predominantly for ensuring best silicon comes out (verification) , while SystemC is used for accelerating the software development by modelling a SOC which is identical to actual Hardware. System verilog is already evolved while systemC is in progress. Accellera is taking up lot of iniitiatives to take systemC to higher level. The use of SystemC can be found in another paper