Hi again,
On Mo, 2013-12-30 at 13:12 +0200, M.Emrah OZKAYA wrote:
> That's fantastic news, guess Santa came early this year :) Thank you
> very much.
I'm making good progress on the LWLA1034 driver, and hope to have it
ready for testing soon. However, I do not own an LWLA1016 myself. If
you want to help, it would be greatly appreciated if you could capture
logs of the USB traffic generated by the vendor software when
communicating with the LWLA1016.
How to do that in a nutshell:
Setup:
- get a VM (such as VirtualBox) running with USB 2.0 support
- forward the LWLA1016 USB device to the Windows guest in the VM
- install and run the LWLA1016 software
Monitoring:
- install Wireshark
- modprobe usbmon
- chmod a+r /dev/usbmon?
- run wireshark
- start capture on the usbmon<bus number> where your device is on
- make sure you have no other noisy devices talking on that bus
- start vendor software inside Windows VM
- change some settings, capture samples, etc
- quit the vendor software
- stop the capture in Wireshark
- save file with pcapng format (the default) and gzip compression
If you don't have the necessary resources at hand, no big deal, we will
get to support the device at some point. But perhaps you could help to
speed up the process. :)
Cheers,
--Daniel

Hi,
as already mentioned in my earlier mail we have implemented the API and
protocol for having a driver for our own open hardware and open software
device "hsa-tple".
Can you give help me how to use the session bus correctly as I haven't
found further documentation.
We use sigrok-cli with the time parameter:
> $ sudo sigrok-cli -l 5 -O vcd -o outfile.txt -d
> hsa-tple:conn=/dev/ttyACM0:serialcomm=9600/8n1 --time=10000 --probes='0-7'
Or this way using samples counter (baudrate can furthermore be changed):
> $ sudo sigrok-cli -l 5 -O vcd -o outfile.txt -d
> hsa-tple:conn=/dev/ttyACM0:serialcomm=9600/8n1 --samples=10000
> --probes='0-7'
Everything seems to work as excepted until we open and read the output
file. We always get "0" as timestamp.
How can this value be increased? What kind of meta data or usage is needed?
> $date Fri Jan 10 16:54:02 2014 $end
> $version libsigrok 0.2.2 $end
> $timescale 1 ms $end
> $scope module libsigrok $end
> $var wire 1 ! 0 $end
> $var wire 1 " 1 $end
> $var wire 1 # 2 $end
> $var wire 1 $ 3 $end
> $var wire 1 % 4 $end
> $var wire 1 & 5 $end
> $var wire 1 ' 6 $end
> $var wire 1 ( 7 $end
> $upscope $end
> $enddefinitions $end
> $dumpvars
> #0
> 1!
> #0
> 1$
> #0
> 0!
> #0
> 1!
> #0
> 0!
> #0
> 1!
> #0
> 0!
> #0
> ...
We send a SR_DF_HEADER and a SR_DF_END packet. Inbetween there are a lot
of SR_DF_LOGIC packets.
Is the last one the problem? Are we only allowed to send one packet with
all samples at once? At the moment we start a measurement, stop it, dump
the samples. During the receiption of samples we already give them to
the session bus.
What are the SR_DF_FRAME_BEGIN and SR_DF_FRAME_END used for? Should they
be used instead/ additionally?
Finally another question: we only save samples when input levels have
changed to save memory. This is a kind of internal VCD. Instead of
creating a whole lot of samples between two sample timestamps that are
the same (what is currently not implemented yet) -- is there a way
around? Can this be ported to be RLE or something?
Help is very appreciated! Thanks in advance.
Bye,
Matthias

Hi all,
as I already told you about we have been developing an open source and
open hardware logic analyzer at Hochschule Augsburg during this winter
semester. We have implemented the API and the protocol on the PC side.
It finally became a serial protocol (virtual serial via USB, sorry guys)
due to a lack of time. But as (almost) everything seems to work now feel
free to contribute and help implement another USB protocol.
A short abstract:
* 8 channels
(24 channels planned, but had not enough logic elements of the CPLD)
* [currently fixed] sample rate of 6.25 MSamples/s
(this correspons to a resolution of 160 ns)
* memory for up to 262'144 samples
the sample storage format is 4 bytes / 32 bit:
- 16 bit timestamp
(we only store new samples and therefore have kind of internal VCD)
- 8 bit data
- 8 bit status
* controllable via USB
- includes meausurement as well as
- microcontroller firmware update and
- CPLD firmware update via uC JTAG bridge
* open hardware and open software
* fully homebrew at Hochschule Augsburg
* low-cost, standard components
* no external power supply required (USB-powered)
Hardware components:
* CPLD: Altera Max II with 240 logic elements
(programmed in VHDL)
* microcontroller: Atmel ATmega32u4
(programmed in C)
* 2x RAM organised as 256K*16
* I/O drivers supporting 5V and 3V as input voltage
If you agree I'll put this information in the wiki also. Also with
further hyperlinks (our internal wiki is not yet publically available,
but hopefully will be soon) and pictures.
Unfortnately it isn't running 100% yet, please help us getting it done.
We're facing some problems with the session bus. For the sake of clarity
I'll let you know in another mail.
Enjoy your weekend,
Matthias

Hi,
I build home-brew packages for libserialport, libsigrok, libsigrokdecode, sigrok-cli and pulseview.
firmware is still missing.
can anyone on OS X test them? http://sigrok.org/wiki/Mac_OS_X#Building_using_Homebrew
I do not like the way pulse view works with this, but it is a good start for new OS X users.
it works, but it is not very pretty.
I am still working on a pulse view bundle with all the libs. There are still issues with the firmware. in the bundle.
How can I tell libsigrok where to look for firmware?
Rene