Testing large analog subsystems within even larger digital SoCs requires an
integrated Design for Test and Test Engineering approach from day one. This
presentation will identify how to align the overall test strategy to various
expectations of test across multiple disciplines. These expectations include
testing for manufacturing anomalies, validating against industry specifications,
reducing test costs and the ability to debug issues in Silicon. Once the various
test expectations are defined, the analog sub-system is analyzed to expose
critical components needed for test access and in-application observation.
Lastly, a method that allows for quick turn test development targeting several
different environments including simulation, production test and bench top
testing will be discussed.