ABSTRACT
Whether you design with discrete logic, base all of your designs on microcontrollers, or simply want to learn how to use the latest and most advanced programmable logic software, you will find this book an interesting insight into a different way to design. Programmable logic devices were invented in the late 1970s and have since proved to be very popular, now one of the largest growing sectors in the semiconductor industry. Why are programmable logic devices so widely used? Besides offering designers ultimate flexibility, programmable logic devices also provide a time-to-market advantage and design integration. Plus, they’re easy to design with and can be reprogrammed time and time again – even in the field – to upgrade system functionality. This book was written to complement the popular Xilinx Campus Seminar series, but you can also use it as a stand-alone tutorial and information source for the first of many programmable logic designs. After you have finished your first design, this book will prove useful as a reference guide or quick start handbook. The book details the history of programmable logic devices; where and how to use them; how to install the free, fully functioning design software (Xilinx WebPACK ISE software is included with this book); and then guides you through your first designs. There are also sections on VHDL and schematic capture design entry, as well as a data bank of useful applications examples. We hope you find this book practical, informative, and above all easy to use.

Karen Parnell and Nick Mehta

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P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK •

Navigating This Book
This book was written for both the professional engineer who has never designed using programmable logic devices and for the new engineer embarking on an exciting career in electronics design. To accommodate these two audiences, we offer the following navigation section, to help you decide in advance which sections would be most useful.

C H A P T E R 1: I N T RO D U C T I O N
Chapter 1 is an overview of how and where PLDs are used. It gives a brief history of programmable logic devices and goes on to describe the different ways of designing with PLDs.

These two planes provided any combination of “AND” and “OR” gates. Then someone asked.CHAPTER 1
Introduction
The History of Programmable Logic
By the late 1970s. To offer the ultimate in design flexibility.
. as well as sharing of AND terms across multiple ORs. “What if we gave designers the ability to implement different interconnections in a bigger device?” This would allow designers to integrate many standard logic devices into one part. Ron Cline from Signetics™ (which was later purchased by Philips and then eventually Xilinx) came up with the idea of two programmable planes. standard logic devices were all the rage. and printed circuit boards were loaded with them.

FIGURE 1-1: WHAT IS A CPLD? MMI (later purchased by AMD™) was enlisted as a second source for the PLA array. but at the time wafer geometries of 10 µm made the input-to-output delay (or propagation delay) high. but without the flexibility of the PLA structure.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 1 This architecture was very flexible. PAL architecture also had the added benefit of faster Tpd and less complex software. which made the devices relatively slow. it was modified to become the programmable array logic (PAL) architecture by fixing one of the programmable planes. This new architecture differed from that of the PLA in that one of the programmable planes was fixed – the OR array.
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. After fabrication issues.

INTRODUCTION Other architectures followed, such as the PLD. This category of devices is often called Simple PLD.

FIGURE 1-2:

SPLD ARCHITECTURES

The architecture had a mesh of horizontal and vertical interconnect tracks. At each junction was a fuse. With the aid of software tools, designers could select which junctions would not be connected by “blowing” all unwanted fuses. (This was done by a device programmer, but more commonly these days is achieved with ISP). Input pins were connected to the vertical interconnect. The horizontal tracks were connected to AND-OR gates, also called “product terms”. These in turn connected to dedicated flip-flops, whose outputs were connected to output pins. PLDs provided as much as 50 times more gates in a single package than discrete logic devices! This was a huge improvement, not to mention fewer devices needed in inventory and a higher reliability over standard logic. PLD technology has moved on from the early days with companies such as Xilinx producing ultra-low-power CMOS devices based on flash memory technology. Flash PLDs provide the ability to program the devices time and time again, electrically programming and erasing the device. Gone are the days of erasing for more than 20 minutes under an UV eraser.

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P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 1

Complex Programmable Logic Devices (CPLDs)
Complex programmable logic devices (CPLDs) extend the density of SPLDs. The concept is to have a few PLD blocks or macrocells on a single device with a general-purpose interconnect in-between. Simple logic paths can be implemented within a single block. More sophisticated logic requires multiple blocks and uses the general-purpose interconnect in-between to make these connections.

FIGURE 1-3:

CPLD ARCHITECTURE

CPLDs are great at handling wide and complex gating at blistering speeds – 5 nanoseconds, for example, which is equivalent to 200 MHz. The timing model for CPLDs is easy to calculate so before starting your design you can calculate your input-to-output speeds.

A CPLD? CPLDs enable ease of design, lower development costs, more product revenue for your money, and the opportunity to speed your products to market. Ease of Design: CPLDs offer the simplest way to implement a design. Once a design has been described, by schematic and/or HDL entry, you simply use CPLD development tools to optimize, fit, and simulate the design. The development tools create a file that is used to customize (that is, program) a standard off-the-shelf CPLD with the desired functionality. This proXilinx • 4

W HY USE

INTRODUCTION vides an instant hardware prototype and allows the debugging process to begin. If modifications are needed, you can enter design changes into the CPLD development tool, and re-implement and test the design immediately. Lower Development Costs: CPLDs offer very low development costs. Because CPLDs are re-programmable, you can easily and very inexpensively change your designs. This allows you to optimize your designs and continue to add new features to enhance your products. CPLD development tools are relatively inexpensive (or in the case of Xilinx, free). Traditionally, designers have had to face large cost penalties such as rework, scrap, and development time. With CPLDs, you have flexible solutions, thus avoiding many traditional design pitfalls. More Product Revenue: CPLDs offer very short development cycles, which means your products get to market quicker and begin generating revenue sooner. Because CPLDs are re-programmable, products can be easily modified using ISP over the Internet. This in turn allows you to easily introduce additional features and quickly generate new revenue. (This also results in an expanded time for revenue). Thousands of designers are already using CPLDs to get to market quicker and stay in the market longer by continuing to enhance their products even after they have been introduced into the field. CPLDs decrease TTM and extend TIM. Reduced Board Area: CPLDs offer a high level of integration (that is, a large number of system gates per area) and are available in very small form factor packages. This provides the perfect solution for designers whose products which must fit into small enclosures or who have a limited amount of circuit board space to implement the logic design. Xilinx CoolRunner CPLDs are available in the latest chip scale packages. For example, the CP56 CPLD has a pin pitch of 0.5 mm and is a mere 6 mm x 6 mm in size, making it ideal for small, low-power end products. Cost of Ownership: Cost of Ownership can be defined as the amount it costs to maintain, fix, or warranty a product. For instance, if a design change requiring hardware rework must be made to a few prototypes, the cost might be relatively small. However, as the number of units that must be changed increases, the cost can become enormous. Because CPLDs are re-programmable, requiring no hardware rework, it costs much less to make changes to designs implemented using them. Therefore cost of ownership is dramatically reduced. Don't forget that the ease or difficulty of design changes can also affect opportunity costs. Engineers who spend time fixing old designs could be working on introducing new products and features ahead of the competition. Xilinx • 5

P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 1 There are also costs associated with inventory and reliability. PLDs can reduce inventory costs by replacing standard discrete logic devices. Standard logic has a predefined function. In a typical design, lots of different types have to be purchased and stocked. If the design is changed, there may be excess stock of superfluous devices. This issue can be alleviated by using PLDs. You only need to stock one device; if your design changes, you simply reprogram. By utilizing one device instead of many, your board reliability will increase by only picking and placing one device instead of many. Reliability can also be increased by using ultra-low-power CoolRunner CPLDs. Their lower heat dissipation and lower power operation leads to decreased FIT.

Field Programmable Gate Arrays (FPGAs)
In 1985, a company called Xilinx introduced a completely new idea: combine the user control and time to market of PLDs with the densities and cost benefits of gate arrays. Customers liked it – and the FPGA was born. Today Xilinx is still the number-one FPGA vendor in the world. An FPGA is a regular structure of logic cells (or modules) and interconnect, which is under your complete control. This means that you can design, program, and make changes to your circuit whenever you wish. With FPGAs now exceeding the 10 million gate limit (the Xilinx Virtex™-II FPGA is the current record holder), you can really dream big.

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These two types of FPGAs differ in the implementation of the logic cell and the mechanism used to make connections in the device.INTRODUCTION
FIGURE 1-4:
FPGA ARCHITECTURE
With the introduction of the Spartan series of FPGAs.95. In fact. For example.
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. an SRAM FPGA is reprogrammed every time it’s powered up. a Reed Solomon IP core implemented in a Spartan-II XC2S100 FPGA has an effective cost of $9. and I/O count. The Spartan-IIE FPGA provides as many as 300.000 gates at a price point that enables application specific standard product (ASSP) replacement. Xilinx can now compete with gate arrays on all aspects – price. There are two basic types of FPGAs: SRAM-based reprogrammable and OTP. whereas the equivalent ASSP would cost around $20. The dominant type of FPGA is SRAM-based and can be reprogrammed as often as you choose. That’s why you need a serial PROM or system memory with every SRAM FPGA. as well as performance and cost. gate. because the FPGA is really a fancy memory chip.

(In the “SRAM logic cell” diagram above. six different combinations of the four inputs determine the values of the output. you must throw away the chip! The OTP logic cell is very similar to PLDs. the pick and place machine only has to place one part.” during programming) to make permanent connections in the chip. instead of conventional gates. However. connections are made.
D ESIGN INTEGRATION
The integration of 74 series standard logic into a low-cost CPLD is a very attractive proposition. Less parts means higher quality and better FIT factor.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 1
FIGURE 1-5:
DIGITAL LOGIC HISTORY
In the SRAM logic cell. OTP FPGAs use anti-fuses (contrary to fuses. an LUT determines the output based on the values of the inputs. with dedicated gates and flipflops. Thus. every time you make a design change.) SRAM bits are also used to make connections. In production. Xilinx • 8
. therefore speeding up production. OTP FPGAs do not require SPROM or other means to download the program to the FPGA. not “blown. Not only do you save PCB area and board layers – thus reducing your total system cost – but you only have to purchase and stock one generic part instead of as many as 20 pre-defined logic devices.

VHDL. Verilog™. you can benefit from low power consumption and reduced thermal emissions. or with a schematic capture package. This in turn leads to the reduction of the use of heat sinks (another cost savings) and a higher reliability end product. but you don’t yet have to know what device within that family you will ultimately use with respect to package and speed. There are four basic steps to using schematic capture: 1. You must choose a specific vendor and device family library at this time. You have complete control of connecting the gates in whatever configuration is required for your application. It is a graphical tool that allows you to specify the exact gates required and how you want them connected. Xilinx • 9
2. begin building the circuit by loading the desired gates from the selected library.INTRODUCTION By using Xilinx CoolRunner devices.
FIGURE 1-6:
BASIC LOGIC D EFINITIONS
The Basic Design Process
The availability of products such as WebPACK ISE software has made it much easier to design with programmable logic. Schematic capture is the traditional method that designers have used to specify gate arrays and programmable logic devices. Designs can be described easily and quickly using a description language such as ABEL. After selecting a specific schematic capture tool and device library.
. You can use any combination of gates that you need. Connect the gates together using nets or wires.

Generate a netlist. and D. The netlist is a compact way for other programs to understand what gates are in the circuit. In the example below. 4. These will define the I/O package pins for the device. Add and label the input and output buffers.
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. There is one line for each of the components and one line for each of the nets. C. EDIF is the industry-wide standard for netlists. and the names of the I/O pins. it will have input package pins A.
FIGURE 1-7:
PLD D ESIGN FLOW
A netlist is a text equivalent of the circuit. Once you have the design netlist. When implementing this design.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 1 3. B. It is generated by design tools such as a schematic capture program. how they are connected. many others exist. including vendor-specific ones such as the Xilinx Netlist Format (XNF). R. and S. and output pins Q. Note that the computer assigns names to components (G1 to G4) and to the nets (N1 to N8). the netlist reflects the actual syntax of the circuit in the schematic. you have all you need to determine what the circuit does.

or even larger design..000. and generating a netlist. especially if you want to have a 20. If you initially create your 10. contained with soft macros. This is rather time-consuming. there is. The term behavioral is used because in this powerful language. behavioral. you would have to modify every one of those 50 pages using the gate array vendor’s component library. For our purposes.INTRODUCTION
FIGURE 1-8:
DESIGN SPECIFICATION – NETLIST
The example on the previous pages is obviously very simplistic. The typical schematic page contains about 200 gates.000gate design with FPGA vendor X and then want to migrate to a gate array. Another inherent problem with using schematic capture is the difficulty in migrating between vendors and technologies. There has to be a better way . There are two major flavors of HDL: VHDL and Verilog. 50. and of course. It’s called high-level design (HLD). or hardware description language (HDL).000-gate design! Each page needs to go through all the steps mentioned previously: adding components. The idea is to use a high-level language to describe the circuit in a text file rather than a graphical low-level gate description. Xilinx • 11
. Therefore. you describe the function or behavior of the circuit in words rather than figuring out the appropriate gates needed to create the application.000.. interconnecting the gates. Let’s describe a more realistic design of 10. these three terms are essentially the same thing.000 equivalent gates. it would require 50 schematic pages to create a 10. adding I/Os.

the HDL method is completely vendor-independent. This file contains all the information necessary to define our 16 x 16 multiplier. with I/O buffers added.
FIGURE 1-9:
DESIGN SPECIFICATION – MULTIPLIER
To create a 32 x 32 multiplier.
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. For the schematic approach. positioned on the page. That’s about three days’ worth of work. then figuring out where to edit the 90 pages so that they addressed the larger bus widths. let’s design a 16 x 16 multiplier specified with a schematic capture and an HDL file. this would entail making three copies of the 30 pages. which method would you choose? In addition to the tremendous time savings. A multiplier is a regular but complex arrangement of adders and registers that requires quite a few gates. and interconnected. requires eight lines of text and can be done in three minutes. the required gates would have to be loaded. This circuit requires approximately 6. as a designer.000 equivalent gates.000 gates. Our example has two 16-bit inputs (A and B) and a 32-bit product output (Y = A x B) – that’s a total of 64 I/Os. In the schematic implementation. So. you could simply modify the work you’d already done for the smaller multiplier. This would probably require four hours of graphical editing. The HDL implementation. which is also 6.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 1 As an example. This opens up tremendous design possibilities for engineers.

) Because the resulting netlist is vendor and device family-specific. You can share your “library” of parts with other designers at your company. now that we have specified the design in a behavioral description. you would have to do this manually. Y:out std_logic(31 downto 0)). (Using schematic capture. FPGA. Y:out std_logic(63 downto 0)). This would probably require about four seconds. In addition.
AFTER (32
X
32
MULTIPLIER ):
entity MULT is port(A. you must use the appropriate vendor library. architecture BEHAVE of MULT is begin Y <= A * B. Xilinx • 13
. end BEHAVE. also called mapping.INTRODUCTION For the HDL specification. and CPLD device vendors. it would be a matter of changing the bus references from 15 to 31 in line 2 and 31 to 63 in line 3. you can specify optimization criteria that the synthesis tool will take into account when selecting the gate-level selection. which is what all logic devices are made of? The answer is synthesis. therefore saving and avoiding duplication of effort. how do we convert this into gates. end BEHAVE. architecture BEHAVE of MULT is begin Y <= A * B. The synthesis tool does the intensive work of figuring out what gates to use based on the high-level description file you provide.
HDL is also ideal for design re-use. end MULT. So.
HDL File Change Example
BEFORE (16
X
16
MULTIPLIER ):
entity MULT is port(A. Some of these options include: optimizing the complete design for the least number of gates. optimizing a certain section of the design for fastest speed.B:in std_logic(15 downto 0). Most synthesis tools support a large range of gate array. end MULT.B:in std_logic(31 downto 0).

In fact. device families. or using the FPGAfriendly. only a synthesis recompile is necessary. such as a PCI bus interface. They are extensively tested (and hence rarely free of charge) to prevent designers from having to verify the IP core functions themselves.000 gates. Merely select the library and optimization criteria (e.
Intellectual Property (IP) Cores
IP cores are very complex pre-tested system-level functions that are used in logic designs to dramatically shorten development time. IP cores differ from soft macros in that they are generally much larger system-level functions. register-rich configuration for state machines.
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. If a vendors changes its libraries. thus exploring many different solutions instead of just one with the schematic approach. or PCMCIA interface.g. DSP filter. To recap. You are relieved from the tedium of selecting and interconnecting at the gate level.. the advantages of high level design and synthesis are many. and much easier to make changes to the design because of the self-documenting nature of the language. The industry-standard formats used ensure that designs can be reused. speed. there is no real practical alternative for designs exceeding 10. You can easily experiment with different vendors. The benefits of using an IP core include: • Faster time to market • A simplified development process • Minimal design risk • Reduced software compile time • Reduced verification time • Predictable performance/functionality.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 1 using the best gate configuration to minimize power. which is a software program that confirms the functionality or timing of a circuit. You can also try different design alternatives and select the best one for the application. IP cores are similar to vendor-provided soft macros in that they simplify the design specification step by removing designers from gate-level details of commonly used functions. It is much simpler and faster to specify your design using HLD.
Design Verification
Programmable logic designs are verified by using a simulator. and optimization constraints. area) and the synthesis tool will determine the results.

A simulator simulates the circuit. since that makes them easier to modify and use with different device vendors. You’ll need to provide the design information (via the netlist after schematic capture or synthesis) and the specific input pattern.
FIGURE 1-10:
THE PLD DESIGN FLOW
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. you’re just a compile away after selecting the new library. After completing the design specification. that you want checked. you’ll need to know if the circuit actually works as it’s supposed to. That is the purpose of design verification. so you can try synthesis tools from different vendors and pick the best results. The simulator takes this information and determines the outputs of the circuit. It’s even design-tool independent. IP cores are more commonly available in HDL format. or test vectors.INTRODUCTION Even if you decide to move to a different vendor and/or technology.

the design step is called fitting. you will be asked to select the target device. which helps you to determine if you’ve selected the best device. a section of the design is fit to the CPLD. referred to as device implementation. Using HDL offers an additional advantage when verifying the design: You can simulate directly from the HDL source file.
Device Implementation
A design netlist completely describes the design using the gates for a specific vendor/device family. The translate step usually ends with a comprehensive report of the results of all the programs executed. In the diagram above. you can go back to the schematic or HDL file. speed grade. The biggest potential problem is if you had previously assigned the exact locations of the I/O pins. CPLDs are a fixed architecture.. and device-specific design rule checking (e. Most often. meaning to “fit” the design to the target device. Once the circuit works correctly. Once it’s fully verified. The programs will vary among vendors. If there are any problems. This is usually a fast process. This bypasses the time-consuming synthesis process that would normally be required for every design change iteration. this occurs when using a legacy design iteration that has been committed to the printed circuit board layout.g. running the synthesis tool generates the netlist for the next step in the design flow – device implementation. Designers typically spend 50% of their development time going through this loop until the design works as required. it’s time to put this in a chip. In addition to warnings and errors is usually a listing of device and I/O utilization. commonly referred to as pin locking. package. translation to the physical device elements. You would conduct a timing simulation a little later in the design flow. They allow you to keep the Xilinx • 16
.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 1
Functional Simulation
At this point in the design flow. re-generate the netlist. Some of the more common programs during translate include: optimization. and then rerun the simulation. does the design exceed the number of clock buffers available in this device?). Translate comprises various programs used to import the design netlist and prepare it for layout. make changes. so the software needs to pick the gates and interconnect paths that match the circuit. Architectures that support I/O pin locking (such as the Xilinx XC9500 and CoolRunner CPLDs) have a very big advantage.
Fitting
For CPLDs. and any other device-specific options. a functional simulation only checks that the circuits give the right combinations of ones and zeros. During the stage of the design flow.

“Place” is the process of selecting specific modules. especially if there are not enough routing tracks. the timing reflects delays of the logic blocks as well as the interconnect. It provides timing information about paths in the design. the most common solution would be to use a larger device. Some vendors offer tools that allow expert users to manually place and/or route the most critical parts of their designs to achieve better performance than with the automatic tools.
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. place and route programs are run after compile. Floorplanner is a type of manual tool. “Route. you can re-program confident that you pin out will stay the same. in the FPGAs where design gates will reside. or required performance. at this point you can use the detailed layout information after reformatting and go back to your chosen simulator with detailed timing information. In addition. A related program is called timing-driven place and route (TDPR).” as the name implies. In both cases. This allows you to specify timing criteria that will be used during device layout. If you layout your PCB to accept a specific pin out. Place and route programs require the longest time to complete successfully because it’s a complex task to determine the location of large designs. A static timing analyzer is usually part of the vendor’s implementation software.
Place and Route
For FPGAs. and meet the desired performance. utilization. This information is very accurate and can be viewed in many different ways. Pin locking is very important when using ISP. Most vendors provide automatic place and route tools so that you don’t have to worry about the intricate details of the device architecture. and then change the design. And you would likely remember the experience the next time you selected a vendor. No amount of fancy coding can compensate for an ill-conceived architecture. This process is called back-annotation and has the advantage of providing the accurate timing as well as the zeros and ones operation of your design. such as displaying all paths in the design and ranking them from longest to shortest delay.INTRODUCTION original I/O pin placements regardless of the number of design changes. ensure that they all get connected correctly. is the physical routing of the interconnect between the logic blocks. can only work well if the target architecture has sufficient routing for the design. or logic blocks. The final implementation step is the download or program. These programs however. If you were to encounter this problem.

For antifuse devices. JTAG Boundary Scan – formally known as IEEE/ANSI standard 1149. board.
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. Program is used to program all non-volatile programmable logic devices.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 1
Downloading or Programming
Download generally refers to volatile devices such as SRAM FPGAs. the bitstream must be stored somewhere for a production solution. the devices do not need to be removed from the board but simply re-programmed in-system. As the name implies.1_1190 – is a set of design rules that facilitate testing. In-system programming has an added advantage in that devices can be soldered directly to the PCB (such as TQFP surface-mount-type devices). you download the device configuration information into the device memory. There is an associated piece of hardware that connects from the computer to a board containing the target device. and system levels. A common such place is a serial PROM. device programming. and debugging at the chip. Because SRAM devices lose their configuration when the power is turned off. Programming performs the same function as download. Programming of Xilinx CPLDs can be done in-system via JTAG or with a conventional device programmer such as Data I/O. except that the configuration information is retained after the power is removed from the device. programming can only be done once per device – hence the term one-time programmable. If the design changes. including serial PROMs. The bitstream that is transferred contains all the information to define the logic and interconnect of the design and is different for every design.

but you still need to verify that the device works in the actual board. If so. Xilinx has the world’s first WebPOWERED programmable logic devices. ChipViewer. This means we have the first WebFITTER CPLD design fitting tool. so you can decide which parts you need. design files. You can download your personal copy in modules. which includes full fitter results. Then press “fit. If you like the results. Simply take your existing design to our WebFITTER web page – these files can be HDL source code or netlists – and specify your target device or your key design criteria. a process called system debug. XST (Xilinx Synthesis Tool). ModelSim™ Xilinx Edition Starter (a thirdparty simulator). such as speed or low power. enabling you to fit your design in real time at our website. Any major problems here mean that you have made an assumption on the device specification that is incorrect. you can then obtain an online price. Xilinx • 19
.INTRODUCTION
FIGURE 1-11:
DEVICE IMPLEMENTATION – DOWNLOAD/PROGRAM
System Debug
The device is now working. and eventually ECS schematic capture and VSS.” You will receive your results moments later via e-mail. or have not considered some aspect of the signal required to/from the programmable logic device. and a programming file (JEDEC file). you can collect data on the problem and go back to the drawing (or behavioral) board. Modules include the design environment (Project Navigator).

fixed logic gate arrays. state-of-the-art software solutions. Moreover.CHAPTER 2
Xilinx Solutions
Introduction
Xilinx programmable logic solutions help minimize risks for electronic equipment manufacturers by shortening the time required to develop products and take them to market. Xilinx Software Solutions provide powerful tools that make designing with programmable logic simple. and high-performance automatic and auto-interactive tools help you achieve optimum results. instrumentation. because Xilinx devices are standard parts that need only to be programmed. Customers incorporate Xilinx programmable logic into products for a wide range of markets. integrated online help. Push-button design flows.
. networking. telecommunications. Those include data processing. consumer electronics. Leading-edge silicon products. and world-class technical support make up the total solution that Xilinx delivers. automotive. and aerospace markets. multimedia tutorials. In addition. The software component of this solution is critical to the success of every design project. the industry's broadest array of programmable logic technology and EDA integration options deliver unparalleled design flexibility. you are not required to wait for prototypes or pay large nonrecurring engineering (NRE) costs. industrial control. You can design and verify the unique circuits in Xilinx programmable devices much faster than by choosing traditional methods such as mask-programmed. defense.

strengthened by our strategic alliances with IBM. RocketChips™. Xilinx “Online Upgradeable Systems” would allow equipment manufacturers to remotely add new features and capabilities to installed systems. Conexant. or repair problems without having to physically exchange hardware. The MathWorks.
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.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2 Xilinx is also actively developing breakthrough technology that will enable the hardware in Xilinx-based systems to be upgraded remotely over any kind of network – including the Internet – even after the equipment has been shipped to a customer. and other technology leaders. once again setting a new benchmark in performance and offering a feature set that is unparalleled. It's an era where Xilinx leads the way.
Xilinx Devices
FIGURE 2-1:
XILINX D EVICES AT A GLANCE
Platform FPGAs
V IRTEX FPGAS
The Virtex-II product is the first embodiment of the Platform FPGA. Wind River Systems.

supported by IBM CoreConnect™ bus technology. Xilinx/Conexant's flawless high-speed serial I/O technology.000 to 10 million system gates. the XtremeDSP tool is the industry's premier programmable solution for enabling TeraMAC/s applications. Empower! processor technology for flexible highperformance system processing needs. and Wind River Systems's cutting-edge embedded design tools.
VIRTEX-II P RO FPGAS
“The Platform for Programmable Systems'” With as many as four IBM PowerPC™ 405 processors immersed into the industry's leading FPGA fabric. powerful synthesis. Xilinx • 23
. With as many as 556 embedded 18 x 18 multipliers. and an extensive library of DSP algorithms and tools including System Generator for DSP. Not only does the fabric provide the ability to integrate a variety of soft IP. significant new capabilities address system-level design issues. smart implementation algorithms. and Cadence™ Design Systems SPW. DCI). and efficient verification capabilities.XILINX SOLUTIONS The Platform FPGA delivers: • SystemIO interfaces to bridge emerging standards • XtremeDSP™ FPGA-based DSP solution for unprecedented DSP performance (as much as 100 times faster than the leading DSP processor) • Coming soon. 10 Mb of embedded block RAM.
The Power of Xtreme Processing
Each PowerPC runs at 300+ MHz delivering 420 Dhrystone MIPS. Additionally. ISE. complex system clock management (Digital Clock Manager). the Virtex-II solution delivers enhanced system memory and lightning-fast DSP through a flexible IP-immersion fabric. into the industry's highest performance programmable logic. you can now harness the power of high-performance processors. including flexible system interfaces with signal integrity (SystemIO. With densities ranging from 40. and onboard EMI management (EMIControl). With the unique Xilinx IP immersion architecture. along with easy integration of soft IP.
XtremeDSP – The World's Fastest Programmable DSP Solution
The Xilinx XtremeDSP solution is the world's fastest programmable DSP solution. Xilinx delivers a complete development platform of infinite possibilities. but it also has the capability of embedding hard IP cores such as processors and gigabit serial I/Os in future Virtex-II families. Virtex-II solutions are empowered by advanced design tools that drive time-to-market advantages through fast design.

guaranteeing your performance target in the most cost-efficient manner.
Virtex FPGAs
The Xilinx Virtex series was the first line of FPGAs to offer one million system gates. introduced in 2000 and the first FPGAs to be manufactured using an advanced copper process. offer additional on-chip memory for network switch applications
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. You can also debug hardware and software simultaneously at speed.
Industry-Leading Tools
Optimized for the PowerPC. you can take advantage of microprocessors. and more. offer more than three million system gates. 3GIO. easy-to-use development system available. the Virtex-II Pro™ series of FPGAs addresses all existing connectivity requirements as well as the emerging high-speed interface standards. The result is a dramatic simplification of board layout. Our SelectIO™-Ultra technology supports 840 Mbps LVDS and high-speed single-ended standards such as XSBI and SFI-4. digital clock managers. Virtex-EM devices. unveiled in 1999. The latest devices in the Virtex-E series. the highest density of on-chip memory. Wind River Systems's industry-proven embedded tools are the premier support for real-time microprocessor and logic designs. and unbeatable time to market. Introduced in 1998.125 Gbps transceivers. you can partition and repartition your systems between hardware and software at any time during the development cycle – even after the product has shipped.
The Power of Integration
In a single off-the-shelf programmable device. a reduced bill of materials. supporting 10 Gigabit Ethernet with XAUI.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2
The Ultimate Connectivity Platform
The first programmable device to combine embedded processors along with 3. Driving the Virtex-II Pro FPGA is the Xilinx lightning-fast ISE software. among others. multi-gigabit serial transceivers. the most comprehensive. on-chip termination. Xilinx RocketIO™ transceivers offer a complete serial interface solution. and SerialATA. This means you can optimize the overall system. the Virtex product line fundamentally redefined programmable logic by expanding the traditional capabilities of FPGAs to include a powerful set of features that address board level problems for high performance system designs.
Enabling a New Development Paradigm
For the first time.

This combination of low cost and features makes it an ideal replacement for ASICs (gate arrays) and many ASSP devices. and logic.5V). Spartan XL (3. The diagram below shows such a system:
Xilinx • 25
.8V). Spartan-IIE (1.
SPARTAN-3 FPGAS
The Spartan-3 (1. a Spartan-3 FPGA in a car multimedia system could absorb many system functions. but it integrates many architectural features associated with high-end programmable logic. For example. Spartan-II (2. including embedded IP cores. The five members of the family are the Spartan-3 (1.2V). 90 nm) FPGA is not only available for a very low cost.3V).2V. and Spartan (5V) devices. high-volume applications and are targeted as replacements for fixed-logic gate arrays and ASSP products such as bus interface chip sets. DSP.
FIGURE 2-2:
PLATFORM FPGAS
Spartan FPGAs
Xilinx Spartan FPGAs are ideal for low-cost.XILINX SOLUTIONS
. custom system interfaces.

the PCI bridge takes the form of a pre-verified drop in IP core. memory. and the device-level and board-level clocking functions are implemented in the Spartan-3 on-chip DCMs. On-chip 18 x 18 multipliers can be used in DSP-type activities such as filtering and formatting. A smaller die size and 300 mm wafers improve device densities and yields. Xylon. less expensive product that takes up less board space when designed into an end product. and Intelliga. thereby reducing overall production costs. eightlayer metal process technology. the Spartan-3 XCITE digitally controlled impedance technology can reduce EMI and component count by providing on-chip tuneable impedances to provide line matching without the need for external resistors. These cores are provided by Xilinx AllianceCORE™ partners such as Bosch. Additionally. CAST. CAN core IP can connect to the body electronics modules. Inc. Xilinx uses 90 nm technology to drive pricing down to under $20 for a one-million-gate FPGA (approximately 17. Xilinx • 26
. which represents a cost savings as high as 80 percent compared to competitive offerings. This in turn leads to a more highly integrated.000 logic cells).P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2
FIGURE 2-3:
CAR MULTIMEDIA SYSTEM
In the car multimedia system shown in Figure 2-3. The Spartan-3 family is based on IBM and UMC advanced 90 nm. Memec Design. and LCD. audio. an IDE interface to the drive unit of a DVD player.. Other custom-designed interfaces can be implemented to off-chip processors.

FIFOs.
FIGURE 2-7:
SPARTAN-IIE SYSTEM INTEGRATION
Xilinx • 31
. and system bus drivers that in the past have been necessary to complete a system design.XILINX SOLUTIONS
SPARTAN-IIE FPGAS
The Spartan-IIE (1. I/O translators. LVPECL. In addition. Spartan-IIE devices provide superior value by eliminating the need for many simple ASSPs such as phase lock loops.8V core) family of FPGAs offers some of the most advanced FPGA technologies available today. on-chip block RAM. including programmable support for multiple I/O standards (including LVDS. and digital delay lock loops for both chip-level and board-level clock management. and HSTL).

The SelectIO feature allows many different I/O standards to be implemented in the areas of chip-to-chip. chip-to-memory.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2
FIGURE 2-8:
SPARTAN-IIE ARCHITECTURE
S PARTAN -IIE ARCHITECTURAL FEATURES
Spartan-IIE devices leverage the basic feature set of the Virtex-E architecture to offer outstanding value. clock multiplication. Each of the two independent ports can be configured independently for width. Clock de-skew can be done on an external (board level) or internal (chip level) basis. Four DLLs are used for clock management and can perform clock de-skew. and chip-to-backplane interfaces.
Xilinx • 32
. The block memory blocks are 4 Kb each and can be configured from 1 to 16 bits wide. and clock division. The basic CLB structure contains distributed RAM and performs basic logic functions.

The architecture also provides advanced functions such as block RAM and clock control blocks.XILINX SOLUTIONS
FIGURE 2-9:
SPARTAN-IIE BLOCK DIAGRAM
The Spartan-IIE family of FPGAs is implemented with a regular. flexible. interconnected by a powerful hierarchy of versatile routing resources. programmable architecture of CLBs.
Xilinx • 33
. surrounded by a perimeter of programmable IOBs.

and GTL. the three registers share a set/reset. SSTL. In addition to the CLK and CE control signals. Three IOB registers function either as edge-triggered D-type flip-flops or as level-sensitive latches. a synchronous reset. an asynchronous preset.
Xilinx • 34
. These high-speed inputs and outputs are capable of supporting various state-of-the-art memory and bus interfaces. BLVDS. LVPECL. HSTL. LVCMOS. you can independently configure this signal as a synchronous set. Each IOB has a CLK shared by the three registers and independent CE signals for each register. For each register. including LVDS.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2
FIGURE 2-10:
SPARTAN-IIE INPUT/OUTPUT BLOCK
The Spartan-IIE IOB features inputs and outputs that support 19 I/O signalling standards. or an asynchronous clear.

Eight I/O banks result from separating each edge of the FPGA into two banks. The output from the function generator in each logic cell drives both the CLB output and the D input of the flip-flop. all of which must be connected to the same voltage. and a storage element. the Spartan-IIE CLB contains logic that combines function generators to provide functions of five or six inputs. when estimating the number of system gates provided by a given device. Consequently. In addition to the four basic logic cells. A logic cell includes a four-input function generator. These voltages are connected externally to device pins that serve groups of IOBs.XILINX SOLUTIONS
FIGURE 2-11:
SPARTAN-IIE BANKING OF I/O STANDARDS
Some of the I/O standards require VCCO and/or VREF voltages.5 logic cells. Xilinx • 35
. Each Spartan-IIE CLB contains four logic cells. restrictions exist about which I/O standards can be combined within a given bank. each CLB counts as 4.
Logic Cells
The basic building block of the Spartan-IIE CLB is the logic cell. carry logic. organized in two similar slices. Each bank has multiple VCCO pins. This voltage is determined by the output standards in use. Consequently. called banks.

P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2
FIGURE 2-12:
SPARTAN-IIE LOGIC CELL
Spartan-IIE function generators are implemented as 4-input LUTs.
Xilinx • 36
. The Spartan-IIE LUT can also provide a 16-bit shift register that is ideal for capturing high-speed or burst-mode data. or a 16 x 1-bit dual-port synchronous RAM. each LUT can provide a 16 x 1-bit synchronous RAM. which is ideal for DSP applications. Furthermore. two LUTs within a slice can be combined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM. In addition to operating as a function generator. The storage elements in the Spartan-IIE slice can be configured either as edge-triggered D-type flip-flops or as level-sensitive latches. This SRL16 mode can increase the effective number of flip-flops by a factor of 16. Adding flip-flops enables fast pipelining.

a Spartan-IIE device eight CLBs high will contain two memory blocks per column. and consequently. Each memory block is four CLBs high. These complement the distributed SelectRAM+ resources that provide shallow RAM structures implemented in CLBs. All Spartan-II devices contain two such columns.
FIGURE 2-13:
SPARTAN-IIE O N-CHIP MEMORY
FIGURE 2-14:
BLOCK RAM APPLICATIONS Xilinx • 37
. These columns extend the full height of the chip. one along each vertical edge.XILINX SOLUTIONS
Block RAM
Spartan-IIE FPGAs incorporate several large block SelectRAM+™ memories. and a total of four blocks. Block SelectRAM+ memory blocks are organized in columns.

P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2
Delay-Locked Loop
Associated with each global clock input buffer is a fully digital DLL that can eliminate skew between the clock input pad and internal clock input pins throughout the device. The DLL monitors the input clock and the distributed clock. This closed-loop system effectively eliminates clock-distribution delay by ensuring that clock edges arrive at internal flip-flops in synch with clock edges arriving at the input. and automatically adjusts a clock delay element. Additional delay is introduced such that clock edges reach internal flip-flops exactly one clock period after they arrive at the input. Each DLL drives two global clock networks.
FIGURE 2-15:
SPARTAN-IIE CLOCK MANAGEMENT
Xilinx • 38
.

Spartan-IIE devices support both serial configuration. using the master/slave serial and JTAG modes.XILINX SOLUTIONS
FIGURE 2-16:
SPARTAN FAMILY COMPARISON
Configuration
Configuration is the process by which the FPGA is programmed with a configuration file generated by the Xilinx development system.
Xilinx • 39
. as well as byte-wide configuration employing the slave parallel mode.

The CoolRunner-II CPLD extends usage as it offers system-level features such as LVTTL and SSTL. You should also review the selection considerations to choose the device that best meets your design criteria. state machines. features. such as a PLCC package? Xilinx • 41
. and flexibility. With standby current in the low micro amps and minimal operational power consumption. What is the fastest sequential circuit in your design? This will tell you what fMax you need. and input hysteresis. or can you use a more ordinary QFP? Or are you prototyping and need to use a socketed device.” or estimate of the logic density of the part. go to a specific product family page to get more detailed information about the device you need. Density – Each part gives an equivalent “gate count. such as battery-powered or portable applications. clocking modes. along with extensive IEEE Std.1 JTAG Boundary Scan support. Xilinx offers CPLD products in two categories: XC9500 and CoolRunner devices. Number of I/O Pins – How many inputs and outputs does your design need? Speed Requirements – What is the fastest combinatorial path in your design? This will determine the Tpd (in nanoseconds) of the device. take a minute to jot down your design specs (using the list below as a criteria reference). review the product features below to identify the product family that fits your application.
Product Features:
XC9500 Device – The XC9500 ISP CPLD families take complex programmable logic devices to new heights of performance. Next.
Selection Considerations:
To decide which device best meets your design criteria. This CPLD family is ideal for high-speed. Number of Registers – Count up the number of registers you need for your counters. and latches. making them the leaders in an all-new market segment: portable electronics. CoolRunner Device – The CoolRunner CPLD families offer extreme low power. Package – What electromechanical constraints are you under? Do you need the smallest ball grid array package possible. these parts are ideal for any application is that is especially power sensitive.1149. registers.XILINX SOLUTIONS
Xilinx CPLDs
Currently. low-cost designs. These families deliver industry-leading speeds while providing the flexibility of enhanced customer-proven pin-locking architecture. To choose a CPLD that's right for you. The number of macrocells in the device must be at least this large.

extensive system in-board debugging. including individual product term (p-term) output enables. and field upgrades. in conjunction with our fitter software. guaranteed timing. It features the standard support including BYPASS. and more p-terms per output than any other CPLD. These devices support ISP. and a full JTAG-compliant interface. longer system life.
Full IEEE 1149. with a wide variety of package combinations that both minimize board space and maintain package footprints as designs grow or shrink. 3.5-volt (XC9500XV). easy-to-use CSP and BGA packaging gives you access to as many as 192 signals. The proven ability of the architecture to adapt to design changes while maintaining pin assignments has been demonstrated in countless real-world customer designs since the introduction of the XC9500 family. three global clocks.
Flexible Pin-Locking Architecture
XC9500 devices. Xilinx • 42
. the XC9500 families provide fast. program and test during manufacturing. low-cost XC9500 families of Xilinx CPLDs are targeted for leading-edge systems that require rapid design development.3-volt (XC9500XL) and 5-volt (XC9500) versions. give you the maximum in routeability and flexibility while maintaining high performance. and robust field upgrade capability. The I/O pins allow direct interfacing to both 3. while the latest in compact. SAMPLE/PRELOAD.or solar-powered? Does your design require the lowest power devices possible? Do you have heat dissipation concerns? System-Level Functions – Does your board have multi-voltage devices? Do you need to level shift between these devices? Do you need to square up clock edges? Do you need to interface to memories and microprocessors?
XC9500 ISP CPLD OVERVIEW
The high-performance. The architecture is feature-rich. which allows manufacturers to perform unlimited design iterations during the prototyping phase.1 JTAG Development and Debugging Support
The JTAG capability of the XC9500 family is the most comprehensive of any CPLD on the market. and EXTEST.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2 Low Power – Is your end product battery.000 program/erase cycle endurance rating and 20-year data retention.and 5-volt systems. Based on advanced process technologies.
XC9500 5V Family
The XC9500 ISP CPLD family features six devices ranging from 36 to 288 macrocells. All XC9500 devices have excellent quality and reliability characteristics with a 10. superior pin locking. The XC9500 families range in density from 36 to 288 macrocells and are available in 2.

The family is also supported on all major ATE platforms. The Xilinx • 43
. and debug system failures. with the lowest cost in the industry. test. JTAG Technologies.3V FAMILY
The XC9500XL CPLD family is targeted for leading-edge systems that require rapid design development. This 3. longer system life. HIGHZ (for bypass). The XC9500 family is supported by a wide variety of industry-standard third-party development and debugging tools including Corelis.3V ISP family provides unparalleled performance and the highest programming reliability. and Asset Intertech. Hewlett Packard. and Genrad. and robust field upgrade capability. These tools allow you to develop Boundary Scan test vectors to interactively analyze. include INTEST (for device functional test). not found in any other CPLD. within a unified development environment.XILINX SOLUTIONS Additional Boundary Scan instructions.
XC9500 Product Overview Table
TABLE 2-2: XC9500 PRODUCT OVERVIEW
XC9500XL 3. for maximum debugging capability. and USERCODE (for program tracking). XC9500XL CPLDs also complement the higher-density Xilinx FPGAs to provide a total logic solution. including Teradyne.

Designed to operate with an internal core voltage of 2. and local and global clock control to provide maximum flexibility. 144.
High Performance Through Advanced Technology
Manufactured on the latest generation 0.1 (JTAG) ISP and Boundary Scan testing • Free WebPOWERED software
XC9500XV 2.5V CPLD FAMILY
The Xilinx XC9500XV 2. Xilinx • 45
.25 µm process. with device offerings of 36.1 JTAG and IEEE 1532 programming capability.5V CPLD family is based on an advanced architecture that combines system flexibility and low cost to allow for faster time to market and lower manufacturing and support costs. which contributes to the device's superior pin-locking capability. resulting in lower heat dissipation and increased long-term device reliability.XILINX SOLUTIONS • Mainstream. bus-hold circuitry for better I/O control. which helps to streamline the manufacturing. 72.5 ns and system frequencies as fast as 275 MHz will be available later this year.3V CPLDs. the new XC9500XV CPLDs provide the same advanced architectural features and densities of the 3. scalable. A high-performance version offering pin-to-pin delays as low as 3. The XC9500XV silicon plus the powerful WebPOWERED software offers a valuable logic solution that can't be beat when it comes to cost and ease of use. thus empowering you to fully concentrate on your system design and not so much on chip-level details. built-in input hysteresis for improved noise margin.
The System Designer’s CPLD
The advanced architecture employed in the XC9500XV CPLD allows for easy design integration.3V XC9500XL family. high-reliability processing • Fast ISP and erase times
Outperforms All Other 3. The 2.5V XC9500XV devices also include optimized support for ISP through the industry's most extensive IEEE1149. The unique features offered in the XC9500XV include a 54-input block fanin.5V. including remote field upgrades. hot-plugging capability to eliminate the need for power sequencing.3V CPLDs
• Extended data retention supports longer system operating life • Virtually eliminates ISP failures • Superior pin-locking for lower design risk • Glitch-free I/O pins during power-up • Full IEEE 1149. and programming of CPLD-based electronic products. the XC9500XV silicon offers 30% lower power consumption than 3. and 288 macrocells. testing.

With this design technique. and power-sensitive applications. simulators. heatsensitive equipment such as telecom switches. the XPLA3 family offers true pin-to-pin speeds of 5. video conferencing systems. handheld. while simultaneously delivering power that is <100 µA (standby) without the need for special "power down bits" that can negatively affect device performance. By replacing conventional amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a casXilinx • 47
. CoolRunner XPLA3 device (3. an important feature for high-performance. These CPLDs also use far less dynamic power during actual operation compared to conventional CPLDs. Let’s look at the CoolRunner XPLA3 devices.XILINX SOLUTIONS
COOLRUNNER LOW -POWER CPLDS
There are two members to the CoolRunner series.8V) device. and emulators. such as: • Laptop PCs • Telephone handsets • Personal digital assistants • Electronic games • Web tablets.3V) and the CoolRunner-II (1.3V family ranges in density from 32 to 512 macrocells.0 ns. and high I/O counts in a single device. The CoolRunner 3. Each member of the XPLA3 family includes Fast Zero Power design technology that combines low power and high speed. CoolRunner CPLDs feature Fast Zero Power technology. CoolRunner CPLDs combine very low power with high speed. high-end testers.
FIGURE 2-21:
SENSE AMPLIFIER VS. allowing the devices to draw virtually no power in standby mode. This makes them ideal for the fast-growing market of battery-operated portable electronic equipment. high density. CMOS CPLDS
The CoolRunner XPLA3 eXtended family of CPLDs is targeted for lowpower applications that include portable.

The XPLA3 CPLD is electrically reprogrammable using industry-standard device programmers from vendors such as Data I/O. through which (ISP) and reprogramming of the device can occur. In addition. and SMS. These enhancements deliver high speed coupled with flexible logic allocation. This combination allows logic to be allocated efficiently throughout the logic block and support as many product terms as needed per macrocell.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2 caded chain of pure CMOS gates. CoolRunner devices are the only total CMOS PLDs.1 JTAG interface. BP Microsystems. which results in the ability to make design changes without changing pin-outs.
FIGURE 2-22:
CPLD APPLICATION TRENDS
XPLA3 Architecture
The XPLA3 architecture features a direct input register path. the dynamic power is also substantially lower than any competing CPLD. using a variable number of product terms per macrocell incurs no speed penalty. and a full PLA structure. JTAG programming. 5V-tolerant I/Os.
Xilinx • 48
. The XPLA3 architecture includes a pool of 48 product terms that can be allocated to any macrocell in the logic block. multiple clocks. The XPLA3 family features industry-standard IEE 1149. as they use both a CMOS process technology and the patented full CMOS Fast Zero Power design technique.

There are eight FoldBack NAND p-terms that are available for ease of fitting and pin locking. What makes the XPLA3 family unique is logic allocation inside each logic block and the design technique used to implement these logic blocks. The XPLA3 architecture comprises logic blocks inter-connected by ZIA. and output enables. presets. From this point of view. The VFM increases logic optimization by implementing any two input logic functions before entering the macrocell.XILINX SOLUTIONS Figure 2-23 shows a high-level block diagram of the XPLA3 architecture. this architecture looks like many other CPLD architectures. Each logic block contains a PLA array that generates control terms and macrocells for use as asynchronous clocks.
FIGURE 2-23:
COOLRUNNER XPLA3 ARCHITECTURE OVERVIEW
Logic Block Architecture
Figure 2-24 illustrates the logic block architecture of CoolRunner XPLA CPLDs. Sixteen product terms are coupled with the associated programmable OR gate into the VFM. The ZIA is a virtual cross point switch. The other p-terms serve as additional single inputs into each macrocell.
Xilinx • 49
. Each logic block has 36 inputs from the ZIA and 16 macrocells. resets.

FoldBack NANDs
XPLA3 utilizes FoldBack NANDs to increase the effective product term width of a programmable logic device. These structures effectively provide an inverted product term to be used as a logic input by all of the local product terms.
Xilinx • 50
. If a macrocell needs more product terms. it simply gets the additional product terms from the PLA array. preset and reset. or latch functions. configurable D. T.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2
FIGURE 2-24: COOLRUNNER XPLA3 LOGIC BLOCK Each macrocell supports combinatorial or registered inputs.

There is one universal clock signal. Using the I/O pin as an output enables the output buffer. When an I/O pin is used as an input. and the macrocell feedback path can be used to feed back the logic implemented in the macrocell. You can individually configure the clock input signals CT[4:7] (local control terms) as either a PRODUCT term or SUM term equation created from the 36 signals available inside the logic block. or combinatorial logic function. the output buffer will be tri-stated and the input signal fed into the ZIA via the I/O feedback path. a path to the register provides a fast input setup time. Any macrocell can be reset or pre-set on power-up. Each of these flip-flops can be clocked from any one of eight sources. There are two feedback paths to the ZIA: one from the macrocell and one from the I/O pin. or latch-type flip-flop. If the macrocell is configured as an input.
Xilinx • 51
. T-.
FIGURE 2-25:
COOLRUNNER XPLA3 MACROCELL DIAGRAM
Each macrocell register can be configured as a D-.XILINX SOLUTIONS
Macrocell Architecture
Figure 2-25 shows the architecture of a macrocell used in the CoolRunner XPLA3 CPLD. The logic implemented in the buried macrocell can be fed back to the ZIA via the macrocell feedback path. Two global synchronous clocks are derived from the four external clock pins.

P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2
I/O Cell
The output-enable multiplexer has eight possible modes. The I/O cell is 5V tolerant and has a single-bit slew-rate control for reducing EMI generation. Outputs are 3. but you may not be sure whether system timing requirements can be met until after the design has been fit into the device. which has three main timing parameters: T PD .3V PCI electrical specification compatible (no internal clamp diode). you may be able to fit the design into the CPLD. This is because of the simplicity of the timing model.
FIGURE 2-26:
COOLRUNNER XPLA3 SIMPLE TIMING MODEL
Xilinx • 52
. In the XPLA3 architecture. including a programmable WPU eliminating the need for external termination on unused I/Os.
Simple Timing Model
Figure 2-26 shows the XPLA3 timing model. This is because the timing models of other architectures are very complex including such things as timing dependencies on the number of parallel expanders borrowed. and varying numbers of X and Y routing channels. In other architectures. and T CO . T SU . you know up-front whether the design will meet system timing requirements. sharable expanders.

XPLA3 Software Tools
Software support for XPLA3 devices is provided by Xilinx WebPOWERED software products. and less heat dissipation Suits full range of designs and applications. Exemplar. EDIF input is supported for all major third-party software flows. able to migrate up and down densities if design grows or shrinks Simplifies multi-voltage design and level shifting Optimizes sharing and resource utilization (all product terms available) Pull-up resistor for I/O termination Design flexibility Supports direct high-speed interface
32 to 512 macrocell device selections
5V tolerant I/Os and multi I/O standards PLA array
Bus-friendly I/O Multiple clocking options Fast input registers
Xilinx • 53
. The nominal delay for using this option is 2. which include the WebFITTER CPLD design fitting tool and WebPACK ISE software. therefore longer battery life. such as Cadence Design Systems. In addition. Mentor Graphics. and Synopsys. TABLE 2-4: COOLRUNNER SUMMARY OF FEATURES AND BENEFITS Features Total CMOS architecture with FZP design technology Benefits Lowest stand-by current and total current consumption of any CPLD. increased reliability. You have the option to enable the slew rate control to reduce EMI.0 ns. Both tools are free. Viewlogic.XILINX SOLUTIONS
Slew Rate Control
XPLA3 devices have slew rate control for each macrocell output pin.

the WebFITTER CPLD design tool.XILINX SOLUTIONS
FIGURE 2-28:
COOLRUNNER XPLA3 PART NUMBER SYSTEM
COOLRUNNER-II CPLD S
Xilinx CoolRunner-II CPLDs deliver the high speed and ease of use associated with the XC9500/XL/XV CPLD family and the extremely low power versatility of the XPLA3. and leading-edge portable products. Xilinx • 55
. Figure 2-29 shows the CoolRunner-II CPLD package offering with corresponding I/O count. 1. This means that the exact same parts can be used for high-speed data communications. The FT256 is particularly suited for slim-dimensioned portable products with mid. allowing the use of tiny packages during high-speed operation. with three in the VQ100 (100-pin. These design features are supported from Xilinx ISE 4. and in the FT256 (256ball. At least two densities are present in each package.to high-density logic requirements.4 mm QFP). with the added benefit of ISP. All packages are surface mount.0 mm-spacing FLBGA). Xilinx-patented Fast Zero Power architecture inherently delivers extremely low power performance without the need for special design measures. Clocking techniques and other power-saving features extend your power budget.1i. Low power consumption and high-speed operation are combined into a single family that is easy to use and cost effective. and WebPACK ISE software onwards. The ultra-tiny packages permit maximum functional capacity in the smallest possible area. The CMOS technology used in CoolRunner-II CPLDs generates minimal heat. with more than half of them ball-grid technologies. 1.0 mm QFP) and TQ144 (144-pin. 1. computing systems.

and 64-macrocell parts. but brings marginal benefit to small parts. with advanced features included in densities where they are most useful. an ability to block and latch inputs to save power. The I/O banks are groupings of I/O pins using any one of a subset of compatible voltage standards that share the same V CCIO level. the Xilinx Advanced Interconnect Matrix (AIM). For example. it is unlikely that you would need four I/O banks on 32. DataGATE™ technology. The function blocks use a PLA configuration that allows all product terms to be routed and shared among any of the macrocells of the function block. low-power devices.
FIGURE 2-29:
COOLRUNNER-II FAMILY OVERVIEW
CoolRunner-II Architecture Description
The CoolRunner-II CPLD is a highly uniform family of fast.
Xilinx • 56
. The family has uniform basic features.and 512-macrocell parts. The underlying architecture is a traditional CPLD architecture. is valuable in larger parts. combining macrocells into function blocks interconnected with a global routing matrix. but very likely for 384. but more useful and likely to be used on larger ones.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2 Figure 2-29 also details the distribution of advanced features across the CoolRunner-II CPLD family. The clock division capability is less efficient on small parts.

regardless of the number contained in the device. Figure 2-30 shows the high-level architecture whereby function blocks attach to pins and interconnect to each other within the internal interconnect matrix. The internal logic engine is a 56-product term PLA. without needing to know the architectural details. you can take advantage of these details to more thoroughly understand the software’s choices and direct its results. The software easily and automatically manages design changes. Each function block contains 16 macrocells. exploiting the 100% routeability of the PLA within each function block. Xilinx • 57
. with 40 entry sites for signals to arrive for logic creation and connection. The design software automatically manages device resources so that you can express your designs using completely generic constructs.XILINX SOLUTIONS Design software can efficiently synthesize and optimize logic that is subsequently fit to the function blocks and connected with the ability to utilize a very high percentage of device resources. All function blocks. If you’re more experienced. are identical.
FIGURE 2-30:
COOLRUNNER-II HIGH-LEVEL ARCHITECTURE
CoolRunner-II Function Block
The CoolRunner-II CPLD function blocks contain 16 macrocells. This extremely robust building block delivers the industry’s highest pin-out retention under very broad design conditions.

the p-terms reside in a PLA. Third.
FIGURE 2-31:
LOGIC ALLOCATION – TYPICAL PAL VS. The PLA is different – and better. to an upper limit of 56.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2 At the high level. you can reuse product terms at multiple macrocell OR functions so that within a function block. you need only create a particular logical product once. any p-term can be attached to any OR gate inside the function block macrocell(s). Naturally. Second. any logic function can have as many p-terms as needed attached to it within the function block. Classic CPLDs typically have a few p-terms available for a high-speed path to a given macrocell. This structure is extremely flexible and very robust when compared to fixed or cascaded p-term function blocks. The result of this architecture is a variable timing model and the possibility of stranding unusable logic within the function block. this works well with the fitting software. PLA
Xilinx • 58
. First. which identifies product terms that can be shared. but you can reuse it as many as 16 times within the function block. They rely on capturing unused p-terms from neighboring macrocells to expand their product term tally when needed.

There are no cascade time adders for putting more product terms in the function block. a small interconnect timing penalty routes signals to another function block to continue creating logic. resets.
Xilinx • 59
. Xilinx design software handles all this automatically. The macrocell can further combine the SOP expression into an XOR gate with another single p-term expression. When the function block p-term budget is reached. and output enables. Functions need not share a common clock. or local p-term-derived clocks. providing either double data rate capability or the ability to distribute a slower clock (thereby saving power). For single-edge clocking or latching. The resulting logic expression’s polarity is also selectable. Xilinx application note XAPP376 gives a detailed explanation of how logic is created in the CoolRunner-II CPLD family. every p-term arrives with the same time delay incurred. In addition. or transparent latch. Standard logic symbols are used in the in figure. Each macrocell flip-flop is configurable for either single edge or DualEDGE clocking. common set/reset. You can develop SOP logic expressions comprising as many as 40 inputs and span 56 product terms within a single function block. or common output enable to take full advantage of the PLA. which is handled by the software. There is no need to force macrocell functions to be adjacent or have any other restriction except for residing in the same function block. with the storage element operating selectively as a D or T flip-flop. Available at each macrocell are independent selections of global. except the trapezoidal multiplexers have input selection from statically programmed configuration select lines (not shown).
CoolRunner-II Macrocell
The CoolRunner-II CPLD macrocell is extremely efficient and streamlined for logic creation. The logic function can be pure combinatorial or registered.XILINX SOLUTIONS The software places as many functions as it can into function blocks. CoolRunner-II macrocell details are shown in Figure 2-32. sets. functionblock level. either clock polarity may be selected per macrocell.

The AIM minimizes both propagation delay and power as it makes attachments to the various function blocks. circulate back through the AIM for additional connection available to all other function blocks. The control term product terms are available for function block clocking (CTC). Results from all function block macrocells. function block asynchronous set (CTS). each macrocell has an optional clock enable signal permitting state hold while a clock runs freely.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2
FIGURE 2-32:
COOLRUNNER-II MACROCELL
When configured as a D-type flip-flop. Note that control terms are available to be shared for key functions within the function block. The macrocell combinatorial functionality is retained for use as a buried logic node if needed.
Xilinx • 60
. which takes in the signal from the macrocell’s I/O pin and directly drives the AIM. as dictated by the design software. function block asynchronous reset (CTR). and function block output enable (CTE). and are generally used whenever the exact same logic function would be repeatedly created at multiple macrocells. as well as all pin inputs.
Advanced Interconnect Matrix (AIM)
AIM is a highly connected low-power rapid switch directed by the software to deliver a set of as many as 40 signals to each function block for the creation of logic. You can configure any macrocell flip-flop as an input register or latch.

tri-stated. Hysteresis also allows easy generation of external clock circuits. A choice of slow or fast slew rate output signal is also available. The medium parts (128 and 256 macrocell) support two output banks. Outputs can be directly driven. unless both banks are set to the same voltage. but substantially reduces noise on that input pin. or open-drain configured. the output pins are grouped in large banks. In addition to voltage levels. The smallest parts are not banked. each I/O is either automatically compliant with standard voltage ranges or can be programmed to become compliant.
FIGURE 2-33: COOLRUNNER-II I/O BLOCK
Output Banking
CPLDs are widely used as voltage interface translators. thus.and 64-macrocell parts. each input can selectively arrive through Schmitt-trigger inputs. Xilinx • 61
. so all signals will have the same output swing for 32. With two. the outputs will switch to one of two selected output voltage levels. This adds a small time delay.XILINX SOLUTIONS
I/O Blocks
I/O blocks are primarily transceivers. However. The Schmitt-trigger path is best illustrated in Figure 2-33.

without any special tricks. three. and 1. making these CPLDs unusable in portable systems. two. This kind of flexibility permits easy interfacing to 3. split evenly. Disabling these switches enables you to complete your design and choose which sections will participate in the DataGATE function. However. CoolRunner-II CPLDs use standard CMOS methods to create the CPLD architecture and deliver the corresponding low current consumption. 1.
DataGATE
Low power is the hallmark of CMOS technology. or four separate output voltage levels.3V.5V. Other CPLD families use a sense amplifier approach to create p-terms. Each I/O pin has a series switch that can block the arrival of unused freerunning signals that may increase power consumption. sometimes you might want to reduce the system current even more by selectively disabling unused circuitry. This residual current can be several hundred milliamps. 2. The patented DataGATE technology permits a straightforward approach to additional power reduction.5V in a single part.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2 The larger parts (384 and 512 macrocell) support four output banks.
FIGURE 2-34:
D ATAGATE FUNCTION IN COOLRUNNER-II CPLDS
The DataGATE logic function drives an assertion rail threaded through medium. They can support groupings of one.8V.and high-density CoolRunner-II CPLD parts. Xilinx • 62
. which always has a residual current component.

One macrocell is singled out to drive the rail. 4. 6. this pin is an ordinary I/O. and CoolCLOCK
Division Circuitry has been included in the CoolRunner-II CPLD architecture to divide one externally supplied global clock by standard values.XILINX SOLUTIONS You can select which inputs to block under the control of the DataGATE function. This capability is supplied on the GCK2 pin. so each can participate if chosen. and 16 (see Figure 2-35). Output signals that do not switch are held by the bus hold feature. The resulting clock produced will be 50% duty cycle for all possible divisions. A latch automatically captures the state of the pin when it becomes blocked. any pass transistor switch attached to it is blocked. One I/O pin drives the DataGATE assertion rail. Figure 2-34 shows how DataGATE function works. and that macrocell is exposed to the outside world (through a pin) for inspection.
Additional Clock Options: Division. 14. 8. 10. It can have any desired logic function on it – something as simple as mapping an input pin to the DataGATE function or as complex as a counter or state machine output driving the DataGATE I/O pin through a macrocell. The DataGATE assertion rail threads throughout all possible I/Os. effectively blocking controlled switching signals so that they do not drive internal chip capacitances.
Xilinx • 63
. When the DataGATE rail is asserted low. Each pin has the ability to attach to the AIM through a DataGATE pass transistor. with options for division by 2. DualEDGE. 12. You can choose any set of input pins can be chosen to participate in the DataGATE function. If the DataGATE function is not needed. and be blocked.

P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2 Note that a synchronous reset is included to guarantee that no runt clocks can get through to the global clock nets.
FIGURE 2-35: COOLRUNNER-II CLOCK D IVISION DualEDGE Each macrocell has the ability to double its input clock switching frequency. CoolCLOCK In addition to the DualEDGE flip-flop. The ability to switch on both clock edges is vital for a number of synchronous memory interface applications as well as certain double data rate I/O applications. Figure 2-32 shows the macrocell flip-flop with the DualEDGE option (doubled clock) at each macrocell. This capability is called CoolCLOCK and is designed to reduce clocking power within the CPLD. The signal is buffered and driven to multiple traces with minimal loading and skew. and then doubling the clock rate using DualEDGE triggering at the macrocells. Xilinx • 64
. you can reduce the clock power by driving the net at half frequency. a product term clock. you can gain additional power savings by combining the clock division circuitry with the DualEDGE circuitry. The source to double can be a control term clock. Because the clock net can be a significant power drain. or one of the available global clocks.

with the divider and DualEDGE flip-flop working together. CoolRunner-II CPLDs have four independent levels of security provided on-chip.
FIGURE 2-36: COOLCLOCK
Design Security
You can secure your designs during programming to prevent either accidental overwriting or pattern theft via readback.XILINX SOLUTIONS Figure 2-36 illustrates how CoolCLOCK is created by internal clock cascading. eliminating any electrical or visual detection of configuration patterns.
Xilinx • 65
.

They are built around application notes and have been tested in WebPACK software. You can find CoolRunner reference designs in the Xilinx IP Center (http://www.com/ipcenter/) by searching on the keyword “CoolRunner.” This will bring up a page that details all of the reference designs available for selection. which can be used as is. select “Products and Services” from the top bar and then select “Silicon Solutions. Click on the application note that of interest and download the PDF file. Unlike purchased IP.com website. These reference designs take the form of not-for-pay IP.” Select “CoolRunner-II CPLDs” from the left-hand side bar and then select “CoolRunner Reference Designs.xilinx. They are available free of charge.
FIGURE 2-41:
APPLICATION NOTE REFERENCE DESIGN LINK
Xilinx • 68
. Open the application and go to the last page of the document. They are fully functional through the WebPACK simulator and testbench. these reference designs do not come with direct support.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2
C OOLRUNNER REFERENCE DESIGNS
CoolRunner reference designs are HDL code-based designs that can help reduce the time of CPLD designs.”
Accessing the Reference Designs
From the Xilinx.

If you are already a Xilinx registered user.
FIGURE 2-44:
LOG IN PAGE
The page above will appear.” You will then be sent an e-mail listing all of the HDL files. you will need to create an account. You can then download and start to use any of the HDL design examples in conjunction with your WebPACK software. with links to each file. If you are new to the Xilinx web site. please enter your user name and password. you will see a page saying “You will receive an e-mail with links to the downloadable files. Once successful.
Xilinx • 70
.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2
.

missile guidance and targeting. signal processing. These devices are used in a wide range of applications such as electronic warfare. These are continually updated. Our quality management system is fully compliant with all ISO9001 requirements. and satellites.
Automotive and Industrial
XILINX IQ SOLUTIONS – ARCHITECTING AUTOMOTIVE INTELLIGENCE
In-car electronic content is increasing at a phenomenal rate. avionics. The Xilinx QPro family of ceramic and plastic QML products provides you with advanced programmable logic solutions for next-generation designs. Xilinx became fully qualified as a QML supplier by meeting all of the requirements for MIL Standard 38535. Xilinx • 71
. advanced driver information systems. The QPro family also includes select products that are radiation hardened for use in satellite and other space applications. so check regularly for new listings. and communications devices. It includes such applications as navigation systems. entertainment systems. TABLE 2-5: CURRENT REFERENCE DESIGNS
Military and Aerospace
Xilinx is the leading supplier of high-reliability PLDs to the aerospace and defense markets. instrument clusters. SONAR communications.XILINX SOLUTIONS Table 2-5 details the current reference designs. In 1997. RADAR.

The wide range of device density and package combinations enables you to deliver highperformance. in the field.
FIGURE 2-45:
IQ DEVICES ORDERING INFORMATION
Xilinx • 72
.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2 To address the needs of automotive electronics designers. Because many new standards continue to evolve (such as the LIN.xilinx. you need the flexibility to quickly modify your designs at any time. visit www. you can develop advanced. Xilinx has created a new family of devices with an extended industrial temperature range option.
Design-In Flexibility
With Xilinx IQ devices. and FlexRay in-car busing standards). after your product has left the factory. The new IQ product grade (-40°C to +125°C ambient for CPLDs and junction for FPGAs) is ideal for automotive and industrial applications. you can remotely and automatically modify your designs. IP cores. By combining our latest IQ PLDs with our solutions infrastructure of highproductivity software. This new “IQ” family consists of existing Xilinx industrial grade (I) FPGAs and CPLDs. with the addition of a new extended temperature grade (Q) for selected devices.com/automotive. design services. you can design-in flexibility and get your product to market faster than ever before. MOST. and customer education. With our unique Internet Reconfigurable Logic (IRL) capability. flexible solutions that meet your application needs. For more information. highly flexible products faster than ever before. cost-effective.

3V) CoolRunner XPLA3 (3. Xilinx • 73
. and system performance is measured in hundreds of megahertz. Given these system complexities. the critical success factor in the creation of a design is your productivity. and robust support for reuse of your own IP.8V) Spartan-IIE (1. ISE tools support today’s most popular methods for design capture. integration of IP cores.3V) XC9500XL (3. easy-to-use graphical interface to help you achieve the best possible designs within your project schedule – regardless of your experience level. Xilinx offers complete electronic design tools that enable the implementation of designs in Xilinx PLDs. including HDL and schematic entry.5V) CoolRunner-II (1.3V) Spartan-II (2. It is arranged by the following topics:
DESIGN E NTRY
ISE software greatly improves your time to market and productivity by accelerating the design entry process. These development solutions combine powerful technology with a flexible.XILINX SOLUTIONS TABLE 2-6: Product Group FPGA CPLD TABLE 2-7: IQ TEMPERATURE RANGE Temperature Grade/Range (ºC) C Tj = 0 to +85 Ta = 0 to +70 I Tj = -40 to +100 Ta = -40 to +85 Q Tj = -40 to +125 Ta = -40 to +125
AVAILABLE IQ D EVICES IN EXTENDED TEMPERATURE Densities 15k gates to 40k gates 36 and 72 macrocells 32 to 512 macrocells 15k gates to 200k gates 32 to 512 macrocells 50k gates to 600k gates 36 and 72 macrocells
IQ Device Family Spartan XL (3. The “Design Tools Center” web pages cover both the Xilinx ISE tools suite as well as design tools from our software partners.8V) XC9500 (5V)
Design Tools
Programmable logic design has entered an era in which device densities are measured in the millions of gates.

AND CONFIGURATION Programmable logic design implementation assigns the logic created during design entry and synthesis into specific physical resources. To ensure that you get your product to market quickly. Synopsys. where a bitstream is generated from the physical place and route information and downloaded into the target PLD.
Xilinx • 74
. The term "place and route" has historically been used to describe the implementation process for FPGA devices. one of the most essential steps in your design methodology.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2 This rich mixture of design entry capabilities provides the easiest-to-use design environment available today for all logic design. Exemplar. The ISE product also includes Xilinx proprietary synthesis technology. A state-of-the-art synthesis engine is required to produce highly optimized results with a fast compile and turnaround time. In addition. cross probing between the physical design report and the HDL design code further enhances the turnaround time. With just the push of a button. while "fitting" has been used for CPLDs. Implementation is followed by device configuration.
S YNTHESIS
ISE advanced HDL synthesis engines produce optimized results for PLD synthesis. or XST. You can even use multiple synthesis engines to obtain the most optimized result of your programmable logic design. To meet this requirement. and Synplicity. you can start any leading synthesis engine within ISE. Xilinx ISE software provides seamless integration with leading synthesis engines from Mentor Graphics. It takes your conceptual HDL design definition and generates a logical or physical representation for the targeted silicon device. Xilinx ISE software provides several key technologies required for design implementation.
I MPLEMENTATION
B OARD -LEVEL I NTEGRATION
ISE software provides intensive support to help you ensure your programmable logic design works within the context of the entire system. the synthesis engine must be tightly integrated with the physical implementation tool and proactively meet design timing requirements by driving the placement in the physical device. including: • Ultra-fast runtimes enable multiple "turns" per day • ProActive Timing Closure drives high-performance results • Timing-driven place and route combined with push-button ease.

Board-Level Verification
Using board-level verification tools ensures that your design performs as intended once integrated with the rest of the system. High-density design environments mean multiple teams working through distributed nodes on the same project. your design problems can change. Xilinx • 76
. The following dynamic verification tools are supported: • HDL Bencher™ • ModelSim XE • StateBench • HDL Simulation Libraries. The Xilinx ISE environment supports the following board-level verification tools: • IBIS Models • Tau • BLAST • Stamp Models • Impact. By exposing a design to realistic and extensive stimuli. across the aisle or in different parts of the world. identifying.
Debug Verification
Debug verification tools speed up the process of viewing.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2
Dynamic Verification
You can save time by using dynamic verification to intercept logical or HDL-based errors early in the design cycle. “live. and correcting design problems at different stages of the design cycle. ISE software’s advanced design options are targeted at making high-density designs as easy to realize as the smallest glue logic.
ADVANCED DESIGN TECHNIQUES
As your FPGA requirements grow. you can find many functional problems at this stage. Debug verification includes the ability to view. These tools can also assist in HDL-based designs by checking coding style for optimum performance.” all internal signals and nodes within an FPGA. The following debug verification tools are supported: • LEDA • FPGA Editor Probe • ChipScope ILA • ChipScope Pro.

Xilinx supports the Virtex-II Pro Platform FPGA embedded processors with "Xilinx versions" of established tools for both low-cost and high-performance markets. High-Level Languages – As design densities increase. Xilinx is driving and supporting industry standards and their respective support tools. Alternatively. and debug high-level language code. Floorplanning can efficiently drive your high-density design process. Each module can then be floorplanned. running on process engines like the embedded PowerPC hard core. When it comes to embedded software development. Partial Reconfigurability – Useful for applications requiring the loading of different designs into the same area of the device. You will be able to port existing legacy designs more easily to the Virtex-II Pro Platform FPGA. compile.
EMBEDDED SW D ESIGN TOOLS CENTER
Embedded Software Tools for Virtex-II Pro Platform FPGAs
The term "embedded software tools" most often applies to the tools required to create. Xilinx provides a simple and low-cost solution. Internet Team Design – This allows managers to drive each team and its design module from a standard Internet browser using the corporate intranet structure. Xilinx offers multiple levels of support. implemented. for execution on a processor engine.XILINX SOLUTIONS Floorplanner – The Xilinx high-level floorplanner is a graphic planning tool that lets you map your design onto the target chip. Modular Design – This gives you the ability to partition a large design into individual modules. link. if software-centric engineers want a feature-rich environment in which to develop more complex applications. designed. Xilinx supplies access to specialized best-of-class tools from the embedded industry leader. and locked until the remaining modules are finished. With the Virtex-II Pro Platform FPGA. load. the need for a higher level of abstraction becomes more important. usually C or C++. This prevents you from having to embrace completely new development methodologies. partial reconfiguration allows you to flexibly change portions of a design without having to reset or completely reconfigure the entire device.
Xilinx • 77
. you will be able to target design modules for either silicon hardware (FPGA gates) or as software applications. edit. For hardware-centric engineers who want to move design modules into software running on the Virtex-II Pro Platform FPGA PowerPC core.

The CORE Generator tool is provided as part of Xilinx Foundation ISE software.
Xilinx • 78
. The CORE Generator tool from Xilinx delivers highly optimized cores compatible with standard design methodologies for Xilinx FPGAs.
Web-Based Information Guide
The “Products and Services” and “End Markets” sections on the Xilinx website give you information about where and how Xilinx devices can be used in end applications and markets. and industry information to reference designs and example code. The data ranges from application notes. This easy-to-use tool generates flexible. visit the Xilinx IP Center at www. You can also download future core offerings from the Xilinx website. These pages are updated regularly.xilinx. making them ideal to bookmark for research purposes or for downloading code or design solutions to shorten your design time to market. To find them.com/ipcenter. high-performance cores with a high degree of predictability. white papers.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2
Xilinx IP Cores
The Xilinx website has a comprehensive database of Xilinx LogiCORE and third-party AllianceCORE verified and tested cores.

” choose from: • Metro Access Networks • Automotive • Broadband • Industrial • Medical and Scientific Xilinx • 79
. You can select a specific market solution or a broad-reaching technology from two drop-down menus: “Network Solutions” or “Technologies.XILINX SOLUTIONS The sections within the “Products and Services” page on the Xilinx website are:
FIGURE 2-46:
PRODUCTS AND SERVICES WEBSITE
Let’s look at each of these web-based sections.” In “Market Solutions. It is the industry's first web portal dedicated to providing comprehensive solutions that accelerate product development. we've provided a choice for locating material.
END MARKETS
The eSP web portal is located within the “End Markets” section on the Xilinx website. To make it as easy as possible.

white papers.
S ILICON PRODUCTS
AND
S OLUTIONS
These web pages allow you to gain in-depth details on Xilinx silicon products. The site was designed to decrease the time spent in the pre-design phase. and application notes are also available. impartial information about which one is best for your application. Data sheets. The eSP web portal (www. and more. you can also go to the IP Center for details about development boards and platforms. choose from: • Wired Networks • Consumer • Additional Topics (such as digital video imaging and capture and editing). FAQs.xilinx. This phase. including FPGAs (Virtex and Spartan).com/esp) includes: • White Papers • System Diagrams • Ask the Experts • Glossary of Terms • System Solutions Boards/reference design boards • eSP News • Industry Events • Tutorials on the latest standards and protocols. and pre-tested reference designs that can be purchased and used. In the “Technologies” section. learning new standards. CPLDs (CoolRunner and XC9500) and RocketPHY™ transceivers. how and where they are used.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2 • Test and Measurement • Digital Video Technologies (DVT) • Home Networking • Wireless Networks. From here. which increasingly has become the designers’ Achilles’ heel.
Xilinx • 80
. involves visiting seminars. The eSP web portal saves time by proving up-to-date information about emerging standards and protocols. analyzing market trends. user guides. assimilating the data.
D ESIGN RESOURCES
This section details the selection of Xilinx and third-party design software.

along with the most comprehensive technical support. high-performance DSP systems. the recognized leader in programmable logic solutions. and third-party programs in the industry. the demand for digital signal processing featuring extreme performance and great flexibility is growing faster than what conventional DSP can deliver. high-bandwidth networking. identify.” Xilinx. and high-performance computing systems – is producing what analysts call ”The beginning of a new information technology era. you can search for algorithms by type: • DSP Cores • Communication and Networking • Video/Image Processing • IP Updates. This section provides details and design information in the following areas:
Algorithms/Cores
In this comprehensive listing of intellectual property. The mission of the Xilinx Online program is to enable. easy-to-use tools.
XILINX ONLINE (IRL)
You can access and upgrade hardware from your desktop anywhere in the world with the Xilinx IRL capability. is well established in these technology segments and uniquely positioned to address this new DSP paradigm now. real-time video broadcasting. Using our comprehensive line of industry-leading FPGAs. The rapid convergence of different technology segments – 3G and 4G wireless communication systems. The XtremeDSP solution can give you computing capabilities approaching 1 Tera MAC/s – more than 100 times faster than conventional DSP solutions. DSP Central provides information that will enable you to achieve the maximum benefit from Xilinx DSP solutions.XILINX SOLUTIONS
SYSTEM RESOURCES
DSP Central
These web pages detail the XtremeDSP solutions that deliver the performance and flexibility needed to quickly build complex. you’ll have the confidence to tackle even the most challenging applications using the Xilinx XtremeDSP tool. services. and optimized algorithms. and promote any Xilinx programmable system that is connected to a network that can
Xilinx • 81
. Driven by the broadband revolution and explosive growth in wireless products.

C ONFIGURATION S OLUTIONS
Located under the “Products and Services” section of the Xilinx website. your network connectivity. and configuration storage devices. You can access details through the “Systems Resources” main web page or visit www. Processor Central also includes more than 40 soft processor peripherals and the necessary embedded software tools to easily complete your design. embedded software solutions.com/irl. this section provides easy-to-use. whether from a PROM for FPGAs or via ISP for CPLDs. IRL design technology comprises robust PLD technology. The section also includes third-party Boundary Scan tools. Spartan-II.xilinx. ATE and programmer support. Virtex-E. or IRL. and Spartan-IIE FPGAs). Put these individual pieces together and network-based hardware upgradeability becomes a reality. upgraded. easy-to-use Virtex-II Pro FPGA PowerPC-based microcontroller solution ideal for embedded hardware and software applications.
P ROCESSOR C ENTRAL
This section provides information that will enable you to reap maximum benefits from Xilinx FPGA processing solutions. ISP cables. and software design tools. It offers the freedom to design a custom solution with a choice of hard processors (as many as four embedded PowerPC processors in Virtex-II Pro devices) or soft processors (with the MicroBlaze™ soft processor core and PicoBlaze™ microprocessor core in Virtex-II.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2 be fixed.
PowerPC Embedded Processor Solution
Embedding IBM's PowerPC processor core into the Virtex-II Pro FPGA provides the ultimate platform FPGA solution.
The UltraController Solution
Xilinx offers a powerful. All aspects of configuration are explained. or otherwise modified after the system has been deployed in the field. pre-engineered solutions to configure all Xilinx FPGAs and CPLDs. Xilinx • 82
. The design technology for creating Xilinx Online applications is called Internet Reconfigurable Logic. The Processor Central section has the following detailed web pages:
The Embedded Development Kit (EDK)
EDK is an all-encompassing solution for designing embedded programmable systems using the IBM PowerPC hard processor core and the Xilinx MicroBlaze soft processor core in Xilinx FPGAs.

Key features of the UltraController include: • A completely self-contained PowerPC system • The ability to implement applications using "C" code • As many as 32 general-purpose inputs and outputs • Ultra low power – 0. This combination of high performance and miniscule size. for use across all applications. yet occupies a tiny footprint of just 154 logic cells. when coupled with the Xilinx MicroBlaze product. at sizes ranging from one-half to one-fifth the size.
Xilinx • 83
. offers you a broad range of "right-sized" solutions from 8 to 32 bits. It offers a single hardware HDL module with two memory versions. the PicoBlaze processor runs at speeds of 116 MHz.
MicroBlaze and PicoBlaze Soft Processor Solutions
Xilinx introduces the industry's fastest 32-bit soft processor core running at 100 D-MIPS on a Virtex-II Pro FPGA. while minimizing the time and effort of building a full CPU-based system. Based on the PowerPC and internal block RAMs. pre-engineered Virtex-II Pro device microcontroller. UltraController uses a simplified software design flow for faster development time. It is optimized for embedding software/hardware applications in Virtex-II Pro devices.XILINX SOLUTIONS The UltraController Solution is an easy-to-use. UltraController delivers performance exceeding many commercial microcontrollers. yet occupies less than 50 logic cells of fabric. Formerly known as KCPSM. All of Xilinx soft CPUs offer performance that is two to four times faster than competitive offerings. The PicoBlaze 8-bit microprocessor core is the clear leader in FPGA-based soft processors.9 mW/MHz • Full debug support via JTAG • Integration with simplified ISE/EDK design flows.

and noise immunity. Cardbus. including PCI Express. The documents and links in this area are designed to give you everything you need to achieve reliable PCB designs on the first try. Xilinx provides a variety of system tools. and LANs. lower EMI. The documents and links in this area will help you design a reliable PC board quickly. In addition. optical cross connects. Let’s list the areas accessible from this web page: Xilinx • 86
.
PARTNERSHIPS
Xilinx works with other networking industry leaders to provide you with a complete connectivity solution. and RapidIO. serial I/O simplifies your system design and provides scalable bandwidth. WANs.
Control Plane and Backplane Products
Building on our PCI IP leadership. and application notes for help with your high-speed designs.
S IGNAL INTEGRITY
Building a working system today requires you to know more than just Boolean logic and HDL code. we are also providing IP cores for more system interconnectivity standards. Terabit networks (among other applications) require high-bandwidth system interconnect technology.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2
C ONNECTIVITY CENTRAL
The industry is moving from parallel to serial I/O. In addition. cheaper PCBs. By using serial I/O. smaller connectors.
Networking and Datapath Products
By using the Xilinx SystemIO networking IP cores and reference designs.
S IGNAL INTEGRITY TOOLS
Building a working system today requires knowing a great deal more than just logic design. compliant IP cores. utilizing a combination of the FPGA physical interface. you can reduce system cost through fewer pins. PCI-X. The Xilinx SystemIO solution provides complete connectivity for high-performance applications. reference designs. and design services. you can quickly build your edge and core routers. Our dedicated Serial Tsunami Solutions web portal is a one-stop shop for the latest design resources to enable serial design success. including device interoperability testing. and partnerships. and MANs.
H IGH-SPEED DESIGN RESOURCES
Xilinx Virtex-II series Platform FPGAs are the ideal solution for building high-performance designs. layer2/3+ switches. design tools. better signal integrity. thirdparty IP.

L IVE E-LEARNING ENVIRONMENT
You can choose from more than 70 online classes or modules covering a broad range of topics and skills involving Xilinx products and services. driver development. but test engineers. During each session. The one-hour modules are taught weekly at different times throughout the day to support worldwide access. please visit the XDS home page or e-mail designservices@xilinx. and engineering managers may want to participate in the training to understand Xilinx products. XDS offers: • Professional project management • System-level experience around the world • Faster project ramp-up • Experienced FPGA design engineers • FPGA hardware and software experts • Accelerated knowledge of FPGA systems • Access to ready-made intellectual property cores. including processors and gates • Expertise in hardware/software co-design techniques • Fixed bid/fixed price contracts Overall. Live instructors present the modules in real time. with more effective use of the devices. and integration with hardware • Experience with FPGA platform design.
Education Services
Participation in a Xilinx training course is one of the fastest and most efficient ways to learn how to design with Xilinx FPGA devices.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2 design • Broad applications experience and immense depth of experience with Xilinx embedded processing tools and products • Fixed bid/fixed price contracts
Embedded Software Design
• Complex embedded software designs with real-time constraints. To find out more. Xilinx • 88
. CAD engineers. technicians. Not only design engineers. Our learning services provide a number of courses in a variety of delivery methods. Hands-on experience with the latest information and software allows you to implement your own design in less time. component engineers.com. you can interact with the instructor or collaborate with online subject experts.

com/support/searchtd. This serves to make training available when you need it and for the products you need. e-mail eurotraining@xilinx.
Xilinx Answers Database
The Xilinx Answers Database is located at www.com/support/education-home. You can save vast amounts of time and energy by using the resources contained within these pages. our new courses reflect current product releases.htm. Working with various Xilinx product development groups. For more information.htm. you’ll find references and resources regarding everything from hardware data sheets to tutorials on using the Xilinx search engine effectively. although specific onsite instruction is also available. which allows you to learn the Verilog language at your own pace without ever leaving your office.com. For more information.
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.support.”
COMPUTER-BASED TRAINING (CBT)
Xilinx introduced computer-based training with Verilog CBT. discounted products.xilinx.msu. and services to universities since 1985. the Xilinx University Resource Center website (xup. XUP has provided donations. The resources available to universities include:
Xilinx University Resource Center
Developed and maintained by the Department of Electrical and Computer Engineering at Michigan State University.600 universities using Xilinx in class labs. Classes are held in centers around the world. or visit www. converted into a computerized self-study program. or about 18% of all engineering universities worldwide. telephone +44 (0)870 7350 548.
UNIVERSITY PROGRAM
The mission of the Xilinx University Program (XUP) is to promote Xilinx as the technology of choice in the academic community. Here.edu/) is designed specifically to support and encourage universities using Xilinx products in the classroom.XILINX SOLUTIONS
DAY SEGMENT C OURSES
Xilinx continues to develop and offer traditional day-length courses. visit www.xilinx.xilinx.com and click on “Courses” under “Education. Verilog CBT is based on the traditional three-day course. Today there are more than 1.

and teambased design techniques. Lastly. A listing of partners in the Xilinx XPERTS program is located at www.xil-
DESIGN CONSULTANTS
The Xilinx XPERTS Program qualifies.support. For more information on Xilinx products and services. you can access Xilinx engineers over the Web by opening a case against a specific issue. Edition FAQ is located at university. For technical support.
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.com.xilinx.htm. software tools. The Xilinx search utility scans through thousands of answer records to return solutions for the given issue. visit www. XPERTS partners also offer consulting in the areas of HDL synthesis and verification. ensuring that they have superior design skills and the ability to work successfully with customers. Several problem-solver tools are also available for assistance in specific areas.com/ipecenter. XPERTS is a worldwide program that allows easy access to certified experts in Xilinx device architectures.xilinx.xilinx. system-level designs.com. A complete suite of one-hour modules is also available at the desktop via live or recorded e-learning. please consult the Xilinx Data Source CDROM in the back of this book. customization and integration.com/univ/xsefaq1.
TECHNICAL SUPPORT
Xilinx provides 24-hour access to a set of sophisticated tools for resolving technical issues via the Web. develops.P ROGRAMMABLE LOGIC D ESIGN: QUICK START HANDBOOK • CHAPTER 2
Xilinx Student Edition Frequently Asked Questions
The Xilinx Student inx. and cores. and supports design consultants. if you have a valid service contract. or visit www. like configuration or install.

WebPACK ISE software offers an easy-to-use GUI to visually create a test pattern.CHAPTER 3
WebPACK ISE Design Software
WebPACK ISE design software offers a complete design suite based on the Xilinx ISE series software. such as VHDL. along with the design under test. The design can also comprise of a mixture of schematic diagrams and embedded HDL symbols. A testbench is then generated and compiled into MXE. or simulating after the implementation process for timing verification.
Module Descriptions
Individual WebPACK ISE modules give you the ability to tailor the design environment to your chosen PLDs as well as the preferred design flow. WebPACK ISE software incorporates a Xilinx version of the ModelSim simulator from Model Technology (a Mentor Graphics company). This chapter describes how to install the software and what each module does. You can choose whether to enter the design in schematic form or in HDL. In general. referred to as MXE (ModelSim Xilinx Edition). Verilog. the design flow for FPGAs and CPLDs is identical. This powerful simulator is capable of simulating functional VHDL before synthesis.
. There is also a facility to create state machines in a diagrammatic form and let the software tools generate optimized code from a state diagram. or ABEL.

1. the implementation process includes four key steps.” Map – Calculates and allocates resources in the targeted device.QUICK START HANDBOOK • CHAPTER 3 The flow diagram below shows the similarities and differences between CPLD and FPGA software flows. Although we’ll discuss details of the software flow in Chapters 5 and 6.
FIGURE 3-1:
WEBPACK SOFTWARE D ESIGN FLOW
When your design is complete and you’re happy with the simulation results.
. here’s a basic overview. Place and Route – Places the CLBs in a logical position and utilizes the routing resources.P ROGRAMMABLE LOGIC D ESIGN -. 2. For FPGAs. Xilinx • 92 Translate – Interprets the design and runs a “design rule check. you can then download the design to the required device. 3.

Generate Programming File – Creates a JED file for programming. and StateCAD gives a visual test facility. 3.
WEBPACK STATECAD
StateCAD is a tool for graphically entering state machines in “bubble diagram” form.
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.WEBPACK ISE D ESIGN SOFTWARE 4. and outputs. which are then synthesized by XST in the same way. State machines are generated in HDL and then added to the WebPACK ISE project. or ABEL into a netlist. The XST synthesis tool synthesizes HDL code in VHDL. the implementation process includes:
WebPACK Design Suite
TABLE 3-1: WEBPACK D EVICE SUPPORT Support Up to XC2VP2 Up to XC2V250 Up to XCV300E Up to XC2S300E Up to XC2S200 Up to XC3S400 All All All
Device Virtex-II Pro Virtex-II Virtex-E Spartan-IIE Spartan-II Spartan-3 CoolRunner-II CoolRunner XC9500 Families
WEBPACK DESIGN E NTRY
The WebPACK tool suite supports several different design entries. You simply draw the states.” Fit – Allocates resource usage and connections. transitions. Generate Programming File – Creates a programming bitstream. Translate – Interprets the design and runs a “design rule check. 1. Schematic designs are converted into VHDL or Verilog. 2.
For CPLDs. Verilog.

the programmer module allows you to configure a device via the JTAG cable. you can simulate the design using the same original testbench as a test fixture. allowing you to simulate the design under test. You simply enter signal transitions in a graphical timing diagram GUI.
WEBPACK FPGA IMPLEMENTATION TOOLS
As we discussed. Prewritten scripts seamlessly compile the design to be tested. but with logic and routing delays added. the written code is simulated before synthesis. The programmer module also includes a PROM file formatter. as well as its testbench. CPLDs. there are several steps to implementing an FPGA design.
WEBPACK HDL BENCHER TOOL
The HDL Bencher tool generates the testbenches. Xilinx FPGAs are based on a volatile SRAM technology. they will retain their program until it’s erased or reprogrammed. this configuration method is normally only used for test purposes. For functional simulation. so the device will not retain configuration data when you remove the power. The necessary libraries are already pre-compiled into MXE. The use of an external PROM is a popular method of storing FPGA configuration data. You can also enter your expected simulation results. After fitting (CPLDs) or place and route (FPGAs). Therefore. allowing the simulator to flag a warning if the simulation did not yield the expected results. The HDL Bencher tool reads the design under test.
WEBPACK IMPACT PROGRAMMER
The iMPACT programmer module allows you to program a device in-system for all devices available in the WebPACK software.QUICK START HANDBOOK • CHAPTER 3
WEBPACK MXE SIMULATOR
The WebPACK MXE Simulator can be used for both functional and timing simulation. (You must connect a JTAG cable to the PC’s parallel port. Once programmed. Xilinx FPGA implementation tools perform all of these steps. The PROM file formatter takes in the bitstream generated during the implementation phase and provides an MCS.) For FPGAs. Xilinx • 94
.P ROGRAMMABLE LOGIC D ESIGN -.
WEBPACK CPLD IMPLEMENTATION TOOLS
Similarly. CPLD implementation tools perform all of the steps in the CPLD implementation flow outlined previously. are non-volatile devices.or HEX-formatted file used by PROM programmers. however.

As the installation process starts up.
WebPACK CD-ROM Installation
First. Xilinx • 95
.
FIGURE 3-2:
REGISTRATION KEY WINDOW
Once at the registration web page. as well as the configuration of the internal logical resources. enter the product ID in the appropriate field. insert the CD. enter the product ID on the CD sleeve at the website given in the window. (The installation process may have already started automatically). follow the online registration process by selecting “new customer please register” from the first online screen. You’ll need to create and enter a memorable user name and password. you’ll see a window asking for a registration key. A CD registration key number will then be sent to you via e-mail. Double-click on the setup. When requested.exe file to start the installation process. It shows the connections between pins of the device. Enter the data requested at each stage.
XPOWER
As power consumption becomes increasingly important in modern digital designs. navigate to the CD drive using Microsoft Windows Explorer software. If the installation does not start automatically. the XPower tool is available to calculate the power consumption of a design running inside a device. To get the registration key.WEBPACK ISE D ESIGN SOFTWARE
WEBPACK CHIPV IEWER
The ChipViewer tool can be used to examine the design after implementation.

If you have enough disk space, we recommend that you install the complete ISE WebPACK software, although it’s also possible to upgrade later.

Getting Started
L ICENSES
The MXE Simlulator is the only tool that requires a license. MXE Simulator is licensed via the FlexlM product from Macrovision. It requires you to situate a starter license file on your hard drive, pointed to by a set lm_license_file environment setting. The license is free and is applied for online after installation, after which you’ll receive a license.dat file via e-mail. From the Start menu, go to Programs > ModelSimXE 5.xx > Submit License Request.

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WEBPACK ISE D ESIGN SOFTWARE

PROJECTS
When starting a project the default location of the project will be: c:\Xilinx_WebPACK\bin\nt You can create a unique directory on your hard drive for working on projects, e.g. c:\my_projects. Should you need to uninstall and reinstall WebPACK ISE software due to problems on your system, we recommend that you delete the entire WebPACK ISE directory structure.

Summary
In this chapter, we explained the functions of all WebPACK ISE modules, along with installation instructions of the modules you require. You can decide which modules are necessary for your intended design and install only relevant modules. In the next section, we’ll take you through your first PLD design using the powerful features of WebPACK ISE software. Our example design is a simple traffic light controller that uses a VHDL counter and a state machine. The design entry process is identical for FPGAs and CPLDs.

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P ROGRAMMABLE LOGIC D ESIGN -- QUICK START HANDBOOK • CHAPTER 3

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CHAPTER 4

WebPACK ISE Design Entry

Introduction
This chapter describes a step-by-step approach to a simple design. The following pages are intended to demonstrate the basic PLD design entry and implementation process. In this example tutorial, you’ll design a simple traffic light controller in VHDL. Our design is initially targeted at a CoolRunner-II CPLD, and we also show how you can convert the project to target a Spartan-3 FPGA. We’ll also discuss some of the advanced features of the architecture.

QUICK START HANDBOOK • CHAPTER 4 Click the Next> button.” and “count.” The clock and reset ports should both be of direction “in. This has automatically generated the entity in the counter VHDL module.
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.P ROGRAMMABLE LOGIC D ESIGN -. Click the Next> button.” “reset. Review the contents of the final window and click the Finish button. Create a 4-Bit Counter Module
FIGURE 4-4:
DEFINE VHDL SOURCE WINDOW
Declare three ports: “clock.” Count should be direction “inout” and should be a 4-bit vector with MSB 3. LSB 0.

WEBPACK ISE D ESIGN ENTRY Notice that a file called “counter.
FIGURE 4-5:
SOURCE IN PROJECT W INDOW
Double-click on this source to open it in the WebPACK ISE Editor window.vhd” has been added to the project in the Sources in Project window of the Project Navigator.
FIGURE 4-6:
COUNTER WINDOW
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.

The port definitions are required if this counter was used in its entirety. They can be copied and pasted into the design. Open the language templates by clicking the button located on the far right side of the toolbar.vhd” architecture between the begin and end statements.
T HE LANGUAGE TEMPLATE
The language template is an excellent tool to assist you in creating HDL code. Language templates are used as a reference. It also has templates for creating common operators (such as “IF/THEN” and “FOR” loops) often associated with software languages. so some sections are deleted. then customized for their intended purpose. you will notice how the WebPACK ISE tool manages hierarchy and associated files in the Sources window. and sometimes modify the functionality.
As the project builds. decoders. Click and drag the counter template from the VHDL > Synthesis > Templates folder and drop it into the “counter. It has a range of popular functions such as counters. An alternate method is to highlight the code in the language template that you want to use in your code and right-click your mouse button. and shift registers. In this tutorial. Usually. Double-clicking on any file name in the Sources window allows that file to be edited in the main Text Editor. The green text indicates a comment.
You can also access the language template from the Edit > Language Template menu.vhd.” The design requires the signal to be called “clock.” The counter in the template is too complex for this particular requirement. the template uses the signal name “clk.QUICK START HANDBOOK • CHAPTER 4 You can remove the source files from the WebPACK ISE GUI by clicking on the add/remove arrow.
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C LOSE
. multiplexers. you must change the bus width or signal names.P ROGRAMMABLE LOGIC D ESIGN -. The commented text in this template shows which libraries are required in the VHDL header. Then select use in “counter.”
THE LANGUAGE TEMPLATES Notice the color-coding used in the HDL Editor.

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. else if DIR='1' then
Delete this section:
else COUNT <= COUNT . The counter from the template shows a loadable bidirectional counter. You can delete the green comments if you wish. A right-click in the gray bar on the left side of the Source Editor window will bring up a menu of these features. For the purposes of debugging code. this information is not required.WEBPACK ISE D ESIGN ENTRY As you have already created the entity. For this design. end if. several new features are available in the Source Editor window. end if. only a 4-bit up counter is required.1.
The counter module should now look like Figure 4-7.
EDIT
THE C OUNTER MODULE Replace “clk” with the word “clock” by using the Edit > Replace function. end if. Delete this section:
if CE='1' then if LOAD='1' then COUNT <= DIN.

FIGURE 4-7:
COUNTER IN VHDL WINDOW
A typical VHDL module consists of library declarations. This is resolved into a positive edge. and an architecture. Xilinx • 106
.” The actual functional description of the design appears after the begin statement in the architecture. The library declarations are needed to tell the compiler which packages are required. The entity declares all ports associated with the design. The reset is asynchronous as is evaluated before the clock action.QUICK START HANDBOOK • CHAPTER 4 You can toggle the line numbers in the side bar on or off and place bookmarks to mark lines of interest in the source file. an entity. This design has two inputs – clock and reset – and one output. The function of this design is to increment a signal “count” when clock = 1 and there is an event on the clock. a 4-bit bus called “count.P ROGRAMMABLE LOGIC D ESIGN -. Count (3 down to 0) means that count is a 4-bit logic vector.

select “New Source” as before.
SAVE
Functional Simulation
To simulate a VHDL file. With “counter. Select “Test Bench Waveform” as the source type and give it the name “counter_tb.”
FIGURE 4-8:
NEW SOURCE W INDOW Xilinx • 107
. a design consists of several lower-level modules wired together by a top-level file. From the Project menu.vhd” highlighted in the Source window. the Process window will give all the available operations for that particular module.
THE C OUNTER MODULE You can now simulate the counter module of the design. We’ll give some examples of component and signal declarations later in this chapter. you must first create a testbench. A VHDL file can be synthesized and then implemented through to a bitstream. Normally.WEBPACK ISE D ESIGN ENTRY The area still within the architecture – but before the begin statement – is where declarations reside. This design currently only has one module that can be simulated.

so when asked which source you want to associate the source with. Review the information and click the Finish button. you can enter a value in the text field or click on the Pattern button to open a Pattern Wizard. clicking the left mouse button on the cell will cycle through the available values for that cell. and output delays. When entering a stimulus. setup requirements. From this Pattern window.” Enter the expected response as follows: Click the yellow COUNT[3:0] cell under CLK cycle 1 and click the Pattern button to launch the Pattern Wizard.P ROGRAMMABLE LOGIC D ESIGN -. The HDL Bencher tool now reads in the design. select “Counter” and click the Next> button. Set the Pattern Wizard parameters to count up from 0 to 1111 (see Figure 4-10). The “Initialize Timing” box sets the frequency of the system clock. Open a pattern text field and button by double-clicking on a signal’s cell or single-clicking on a bus cell. The testbench is going to simulate the counter module. Xilinx • 108
. Enter the input stimulus as follows: Set the RESET cell below CLK cycle 1 to a value of “1.” Set the RESET cell below CLK cycle 2 to a value of “0. Set initialize timing as follows and click OK: Clock high time: Clock low time: Input setup time: Output valid delay: 50 ns 50 ns 10 ns 10 ns
FIGURE 4-9:
HDL BENCHER WINDOW
Note that the blue cells are for entering input stimulus and the yellow cells are for entering expected response.QUICK START HANDBOOK • CHAPTER 4 Click the Next> button.

type “–all” and hit OK.fdo” file). The –all property runs MXE until the end of the testbench. then right-click on “Simulate Behavioral VHDL Model.udo. By default. and calls a user-editable “.” Now that the testbench is created. compiles the design and testbench source files. MXE will only run for 1us.” This will bring up the Model Technology MXE dialog box. In the Process window. double-click on “Simulate Behavioral VHDL Model.” It also invokes the simulator. and runs the simulation for the time specified by the simulation run time property. Xilinx • 110
.tbw.do” file. Select “counter_tb. In the Process window. or in this case an “. you can simulate the design.” Selelect Properties. expand the ModelSim simulator by clicking. Close the HDL Bencher tool. In the Simulation Run Time field. adds all the signals to the List window. The ISE Sources in Project window should look like Figure 4-12. adds all the signals to the Wave window. opens all the viewing windows.tbw” in the ISE Source window. WebPACK ISE software automates the simulation process by creating and launching a simulation macro file (a “.P ROGRAMMABLE LOGIC D ESIGN -. double-click on “counter_tb.
FIGURE 4-12:
NEW SOURCES IN PROJECT WINDOW
To make changes to the waveform used to create the testbench. This creates the design library.QUICK START HANDBOOK • CHAPTER 4 Click File > Save to save the waveform.do file” called “counter_tb.

select Zoom Full. You can view project snapshots by selecting the Sources window snapshot tab in the Project Navigator.
FIGURE 4-13:
WAVE WINDOW
Use File > Exit to close the ModelSim simulator.WEBPACK ISE D ESIGN ENTRY Maximize the Wave window. Alternatively. closing the main ModelSim window using the usual close window button will close down the ModelSim program.
FIGURE 4-14:
PROJECT SNAPSHOT WINDOW
Taking a snapshot of your project saves the current state of your project in a subdirectory (with the same name as the snapshot) so that you can go back to it in the future.
Take a snapshot of your design by selecting Project > Take Snapshot. From the Zoom menu.
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.

Highlight State Diagram and give it the name “stat_mac.dia. State 1: Red Light State 2: Red and Amber Light State 3: Green Light State 4: Amber Light To invoke the state machine editor. select New Source from the project menu. the counter acts as a timer that determines the transitions of a state machine.” Click the Next> button.P ROGRAMMABLE LOGIC D ESIGN -.QUICK START HANDBOOK • CHAPTER 4 If the design had only one module (one level of hierarchy). each state controlling a combination of the three lights. however. then the Finish button. has a further module to represent a more typical VHDL design. The state machine will run through four states. This design. the implementation phase would be the next step.
FIGURE 4-15:
NEW SOURCE WINDOW
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.
State Machine Editor
For our traffic light design.

FIGURE 4-16:
STATE MACHINE WIZARD WINDOW
Set the number of states to “4” and hit the Next> button. Click the Next> button to build a synchronous state machine.WEBPACK ISE D ESIGN ENTRY Open the State Machine Wizard by clicking on the button in the main toolbar.
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.

and GRN.P ROGRAMMABLE LOGIC D ESIGN -.
FIGURE 4-17:
SETUP TRANSITIONS WINDOW
Click on the Finish button and drop the state machine on the page. AMB. Double-click on the Reset State 0 colored yellow. In the DOUT field. Rename the state name “RED. This design will have three outputs named RD. type “RD” to declare an output.
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.QUICK START HANDBOOK • CHAPTER 4 In the Setup Transitions box. type “TIMER” in the Next field (shown in Figure 4-17).” Hit the Output Wizard button.

edit the other states: Rename State 1 to “REDAMB” and use the output wizard to set RD = 1.WEBPACK ISE D ESIGN ENTRY Set RD to a constant “1” with a registered output. Rename State 3 to “AMBER” and use the output wizard to set AMB = 1. and a new output AMB equal to “1” with a registered output. as shown in Figure 4-18. The state machine should look like Figure 4-19.
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.
FIGURE 4-18:
LOGIC W IZARD W INDOW
Click on OK and then OK the Edit State box. In a similar fashion. Rename State 2 to “GREEN” and use the output wizard to set a new output GRN equal to “1” with a registered output.

it is no longer ticked as registered.”
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.)
FIGURE 4-19: STATE D IAGRAM Double-click on the transition line between state “RED” and state “REDAMB.QUICK START HANDBOOK • CHAPTER 4 (If you set a signal as registered in the Output Wizard and then select Signal and re-open the wizard.P ROGRAMMABLE LOGIC D ESIGN -.

set a transition to occur when timer is 1111 by editing the Condition field to TIMER = “1111.” (Don’t forget the double quotes (“). as these are part of VHDL syntax. TIMER = “0100” Transition GREEN to AMBER.). TIMER = “0000” Hence. AMBER once every three cycles of the counter. declare the vector TIMER by clicking on the button on the left-hand side of the toolbar. TIMER = “0011” Transition AMBER to RED.WEBPACK ISE D ESIGN ENTRY In the edit condition window.
FIGURE 4-20: EDIT CONDITIONS WINDOW Repeat for the other transitions: Transition REDAMB to GREEN. Finally. the traffic light completes a RED. REDAMB.
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. GREEN.

go to the Project menu and select Add Source. go to the Project menu and select Add Source. In the Add Existing Sources box.WEBPACK ISE D ESIGN ENTRY Click on the Generate HDL button on the top toolbar.” Click on Open and declare it as a VHDL Module. Save and close StateCAD. In the Add Existing Sources box.dia. In the Project Navigator. In the Project Navigator. find “STAT_MAC.
The Results window should read “Compiled Perfectly. Doubleclicking on this file will open up the state diagram in StateCAD. The state machine can now be added to the WebPACK ISE project.vhd.
FIGURE 4-23:
SOURCE IN PROJECT W INDOW SHOWING MODEL VIEW
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.” The state diagram will be added to the top of the Sources window. find “stat_mac.” Close the dialog box and the generated HDL Browser window.

vhd file.P ROGRAMMABLE LOGIC D ESIGN -.
FIGURE 4-24:
PROJECT SNAPSHOT
From the Project menu. If you prefer the former. the counter and state machine will be connected using a top. jump directly to the next section Top-Level Schematic Designs. Take a snapshot of the project from Project > Take Snapshot. select New Source and create a VHDL module called “top. two modules in the design are connected together by a top-level file. Because this section discusses the latter. Some designers like to create a top-level schematic diagram. page 125.QUICK START HANDBOOK • CHAPTER 4
Top-Level VHDL Designs
At this point in the flow. while others like to keep the design entirely text-based. You will have the opportunity to do both by continuing through this tutorial.”
FIGURE 4-25:
NEW SOURCE WINDOW SHOWING VHDL MODULE
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.

FIGURE 4-28:
INSTANTIATION TEMPLATE
Close the instantiation template. highlight “counter.” In the Process window.vhd. Repeat the copy-and-paste procedure previously described. Highlight “stat_mac.
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. Highlight and copy the component declaration and instantiation.” Rearrange the component declaration so that it lies before the begin statement in the architecture. Paste the component declaration and instantiation into “top. double-click View VHDL Instantiation Template from the Design Entry Utilities section. Declare a signal called “timer” by adding the following line above the component declarations inside the architecture: signal timer : std_logic_vector(3 downto 0).P ROGRAMMABLE LOGIC D ESIGN -.vhd.vhd” in the Sources window and double-click View VHDL Instantiation Template from the Design Utilities section. as shown in Figure 4-28.QUICK START HANDBOOK • CHAPTER 4 In the Sources window. Rearrange the instantiation so that it lies between the begin and end statement (see Figure 4-29 for reference).

vhd.vhd” becoming sub-modules of “top.vhd. but this time. In the waveform diagram.” You can now simulate the entire design.” Xilinx • 123
.
FIGURE 4-29:
TOP. Add a new testbench waveform source as before.vhd” and “stat_mac. with “counter.WEBPACK ISE D ESIGN ENTRY Connect the counter and state machine instantiated modules so that your “top.” Accept the timing in the Initialize Timing dialog box and click OK.VHD
FILE
When you save “top.vhd” file looks like Figure 4-29. associate it with the module “top. enter the input stimulus as follows: Set the RESET cell below CLK cycle 1 to a value of “1.” notice how the Sources window automatically manages the hierarchy of the whole design.

followed by the object on which the action will be performed. WebPACK ISE software will ask if you would like to take another snapshot of the design in its current state.
Top-Level Schematic Designs
Sometimes.” The Sources window module view should look like Figure 4-32.WEBPACK ISE D ESIGN ENTRY You are now ready to go to the implementation stage.vhd” files.vhd” and the “stat_mac. In the Project menu. it’s easier to visualize designs when they have a schematic top level that instantiates the individual blocks of HDL. the entire project can be schematicbased.
FIGURE 4-32:
SOURCES IN PROJECT WINDOW
ECS H INTS
The ECS schematic capture program is designed around you selecting the action you wish to perform. Highlight Snap2 (two modules). select Make Snapshot Current. This section discusses the method of connecting VHDL modules via the ECS schematic tool. select the Snapshot View tab. The blocks can then be wired together in the traditional method. For designs in the WebPACK ISE tool. Xilinx • 125
. you will first need to revert to the screen shown in Figure 4-32 (two modules with no top-level file). Select Yes and create a third snapshot called “vhdl_top. This action will take you back to the stage in the flow with only the “counter. At the bottom of the Sources window. If you have worked through the previous session.

P ROGRAMMABLE LOGIC D ESIGN -- QUICK START HANDBOOK • CHAPTER 4 In general, most Windows applications currently operate by selecting the object and then the action to be performed on that object. Understanding this fundamental philosophy of operation makes learning ECS a much more enjoyable experience. From the Project menu, select New Source > Schematic and give it the name “top_sch.”

FIGURE 4-33: NEW SOURCE WINDOW SHOWING TOP_SCH Click the Next> button, then the Finish button. The ECS Schematic Editor window will now appear. Back in the Project Navigator, highlight “counter.vhd” in the Sources window. In the Process window, double-click on Create Schematic Symbol from the Design Entry Utilities section. This will create a schematic symbol and add it to the library in the Schematic Editor. Create another symbol – this time for the state machine – by highlighting “stat_mac.vhd” and double-clicking on Create Schematic Symbol. Returning to the Schematic editor, the symbol libraries can be found under the Symbol tab on the left-hand side of the page. Add the counter and state machine by clicking on the new library in the Categories window at the top right of the ECS page and then selecting Counter. Move the cursor over the sheet and drop the counter symbol by clicking where it should be placed. Xilinx • 126

WEBPACK ISE D ESIGN ENTRY Move the cursor back into the Categories window and place the “stat_mac” symbol on the sheet. Zoom in using the button so your zoom button and the window looks like Figure 4-34.

FIGURE 4-34:

CLOSE-UP OF COUNTER AND STATE MACHINE SYMBOLS

Select the Add Wire tool from the Drawing toolbar.

To add a wire between two pins, click once on the symbol pin, once at each vertex, and once on the destination pin. ECS will let you decide whether to use the Autorouter or manually place the signals on the page. To add a hanging wire, click on the symbol pin to start the wire once at each vertex. Then double-click at the location where you want the wire to terminate. Wire up the counter and state machine as shown in Figure 4-35:

Type “clock” (notice that the text appears in the window in the top lefthand side of the ECS page) and then place the net name on the end of the clock wire. To add net names to wires that will be connected to your FPGA/CPLD I/Os, place the net name on the end of the hanging wire. Finish adding net names so that your schematic looks similar to Figure 4-36.

FIGURE 4-36:

MORE NET NAMES

ECS recognizes that count(3:0) and TIMER(3:0) are buses, and so connects them together with a bus rather than a single net.

I/O MARKERS
Select the Add I/O Marker tool from the Drawing toolbar.

With the Input type selected, click and drag around all the inputs to which you want to add input markers. Repeat for the outputs but select Output type.

FIGURE 4-37: ADDING I/O MARKERS Save the design and exit the Schematic editor. (In the Design Entry utilities, you can view the VHDL created from the schematic when “top_sch” is selected in the Sources window. The synthesis tool actually works from this file.) You can now simulate the entire design. Highlight “top_sch.sch” in the Sources window. Add a new testbench waveform source by right-clicking on “top_sch.sch” and selecting New Source. Call this source “top_sch_tb” and associate it with “top.” Accept the timing in the Initialize Timing dialog box and click OK. In the waveform diagram, enter the input stimulus as follows: Set the RESET cell below CLK cycle 1 to a value of “1.” Click the RESET cell below CLK cycle 2 to reset it low.

The first step is translate. the synthesis stage converts the text-based design into an NGC netlist file. this stage prepares the synthesized design for use within a CPLD. It all depends on how well the design converts into product terms. As all the logic delays added by the macrocells. The netlist is a non-readable file that describes the actual circuit to be implemented at a very low level. switch matrix. Translate also checks the UCF for any inconsistencies. it is good practice to re-simulate. MXE can use information for timing simulation. the fit process will not be able to complete its job. The fitter also uses the UCF file to understand timing and may sometimes decide to change the actual design. Obviously.
. In effect. if the design is too big for the chosen device. This step checks the design and ensures that the netlist is consistent with the chosen architecture. For example. The implementation phase uses the netlist and a constraints file to recreate the design using the available resources within the CPLD. and flip-flops are known. The fit stage distributes the design to the resources in the CPLD and places those resources according to the constraints specified. Once the fitter has completed. sometimes the fitter will change the D-Type flip-flops in the design to Toggle Type or T-Type registers. Constraints may be physical or timing and are commonly used for setting the required frequency of the design or declaring the required pinout.CHAPTER 5
Implementing CPLDs
Introduction
After you have successfully simulated your design.

In the Process window. a tick will appear. the software will automatically synthesize. ensure that “top. Ensure that any errors in your code are corrected before you continue. The steps of implementation must be carried out in this order. If the syntax check is OK.P ROGRAMMABLE LOGIC D ESIGN -. In our traffic light design. expand the Synthesis subsection by clicking on the “+” next to Synthesize.vhd” (or “top_sch” for schematic flows) is highlighted. It will then generate the timing information before it opens MXE and gives the timing simulation results. You can now check your design by double-clicking on Check Syntax. WebPACK ISE software will automatically perform the steps required if a particular step is selected.vhd” (for VHDL designs) or “top_sch” (for schematic designs) instantiates two lower level blocks.
Synthesis
The XST synthesis tool will only attempt to synthesize the file highlighted in the Sources window.
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. which is used to program the device either on the board via a parallel cable or using programming equipment. and tit the design. In the Sources window. The rest of this chapter demonstrates the steps required to successfully implement our traffic light design.” The synthesis tool recognizes all the lower level blocks used in the top-level code and synthesizes them together to create a single bitstream.QUICK START HANDBOOK • CHAPTER 5 The fitter creates a JEDEC file. “top. if the design has only just been functionally simulated and you decide to do a timing simulation. translate. For example. “stat_mac” and “counter.

when writing code.IMPLEMENTING CPLDS The design should be okay because both the HDL Bencher tool and MXE simulator have already checked for syntax errors. you must tell the implementation tools what and where performance is required. Click OK in the Process Properties window and double-click on Synthesize. to periodically check your design for any mistakes using this feature. pin locking is a physical constraint. (It is useful. This design is particularly slow and timing constraints are unnecessary. Double-click on View Synthesis Report. The Help feature will explain each of the options in each tab. In the Xilinx Specific Options tab.)
FIGURE 5-1:
PROCESS WINDOW SHOWING CHECK SYNTAX
Right-click on Synthesize and select Properties. A window appears allowing you to influence the way in which your design is interpreted. Constraints can also be physical. The synthesis tool will never alter the function of the design. When the synthesis is complete. Clicking on Help in each tab demonstrates the complex issue of synthesis and how the final result could change. Xilinx • 133
.
Constraints Editor
To get the ultimate performance from the device. but it has a huge influence on how the design will perform in the targeted device. Click on the HDL Options tab. The I/O buffers will be attached to all the port names in the top-level entity of the design. ensure that the Add IO Buffers box is ticked. a green tick will appear next to Synthesize.

add a New Source of type Implementation Constraints File. In the Source window.QUICK START HANDBOOK • CHAPTER 5 For this design. expand the User Constraints section and doubleclick on Assign Package Pins.P ROGRAMMABLE LOGIC D ESIGN -.”
FIGURE 5-2:
CONSTRAINTS FILE AS A SOURCE
In the Process window.
FIGURE 5-3:
ASSIGN PACKAGE PINS IN PACE TOOL
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. assume that the specification for clock frequency is 100 MHz and that the pin-out has been pre-determined to that of a CoolRunner-II pre-designed board. Call this file “top_constraints “and associate it with the module “top.

In the Design Object List. The UCF file will open in the main window of the ISE Project Navigator. PACE recognizes the five pins in the design and displays them in the list.IMPLEMENTING CPLDS Notice that the translate step in the Implement Design section runs automatically. double-click Edit Constraints (Text) in the Process window. Click in the Loc area next to each signal and enter the following location constraints: clock reset red_light green_light amber_light p38 p143 p11 p13 p12
FIGURE 5-4: ENTER LOCATION CONSTRAINTS When a pin is highlighted in the Design Object List. It is now possible to see the constraints in the UCF file. If there are already constraints in the UCF file. With “top_constraints. When translate has completed. This is because the implementation stage must see the netlist before it can offer you the chance to constrain sections of the design. these will be imported by PACE and displayed. As we have an empty UCF file. the pin to which it is “Loc'ed” is highlighted in the Package Pins view. the Xilinx PACE (Pinout Area and Constraints Editor) tool opens. Save the PACE session and exit the PACE tool.
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. you can enter a variety of constraints on the I/O pins used in the design. nothing exists for PACE to import.ucf” highlighted in the Source window.

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. The Constraints Editor recognizes the one global signal in the design. Save and close the text file. The next step is to create timing constraints.QUICK START HANDBOOK • CHAPTER 5 The constraints entered into PACE can be seen in Figure 5-5. Enter the following syntax in the text file: NET "clock" BUFG=CLK. With the UCF highlighted in the Source window.
FIGURE 5-5:
TEXT CONSTRAINTS IMPORTED FROM PACE
To force a signal onto a global resource.P ROGRAMMABLE LOGIC D ESIGN -. you can apply the BUFG constraint. double-click on Create Timing Constraints in the Process window. we will apply the BUFG constraint to the clock signal. This tool can be used to set location constraints. but for this tutorial it will only be used to create timing constraints. In this case. The Constraints Editor will open.

change the Time value to 10 ns. The duty cycle should stay at 50% high. they have been imported. A period constraint ensures that the internal paths starting and ending at synchronous points (flip-flop.IMPLEMENTING CPLDS DoubLe-click in the Period window of the global clock signal. latch) have a logic delay less than 10 ns. Click the Ports tab in the Constraints Editor.
FIGURE 5-6:
CLOCK PERIOD EDITOR W INDOW
In the Clock Period definition window. 50% low. As there were already constraints in the UCF.
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. The period constraint is now written into the UCF file and can be seen in the constraints list at the bottom of the Constraints Editor.

In the Select Group box.P ROGRAMMABLE LOGIC D ESIGN -.QUICK START HANDBOOK • CHAPTER 5 Highlight the three outputs “red_light. select “lights” and click the Clock to Pad button.” “green_light.
FIGURE 5-7: CONSTRAINTS EDITOR – CREATE GROUP In the Group Name field.” and “amber_light” using ctrl select.
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. type “lights” and then click the Create Group button.

FIGURE 5-8: Click OK. set the Time Requirement to 15 ns relative to the clock. The UCF file should look similar to Figure 5-9. but in some designs there may be more). (There is only one clock.
FIGURE 5-9:
COMPLETE CONSTRAINTS LIST Xilinx • 139
.
CLOCK TO PAD D IALOG BOX
Notice that the Clock to Pad fields have been filled in automatically and that the UCF generated has appeared in the UCF constraints tab at the bottom of the screen.IMPLEMENTING CPLDS In the Clock to Pad dialog box.

The CoolRunner-II CPLD also supports different I/O standards.xilinx.P ROGRAMMABLE LOGIC D ESIGN -.
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. if the clock used in this design is an RC oscillator. On larger devices (128 macrocell and larger). the input hysteresis can be used to clean up the clock using the following constraint syntax: NET “clock” schmitt_trigger. SSTL2_I. which will reduce the power consumption of that net without compromising the performance of the design.com/apps/epld. All of the registers clocked by this clock are then automatically configured as dual-edge triggered flip-flops. LVCMOS15. For more information on the use of CoolRunner-II CPLDs. visit www. The highest toggling net in the design will now be toggling at half the frequency. However. and their advanced features. LVCMOS33. you can use only one I/O standard per bank. One of these features is known as CoolClock. For example.htm for a number of application notes. LVCMOS18. You must re-run translate so the new constraints can be read. This can be selected on a pin-by-pin basis. The permissible standards are LVTTL. If the three light signals had to go to a downstream device that required the signals to conform to a certain I/O standard. The CoolClock attribute can be applied by right-clicking on GCK2 in ChipViewer or by adding the following line in the UCF: NET “clock” COOL_CLK. the permissible standards are HSTL_I.QUICK START HANDBOOK • CHAPTER 5 Save the Constraints Editor session and exit the Constraints Editor. However. CoolRunner-II architecture supports the use of non 50:50 duty cycle clocks by implementing input hysteresis. we will not use these features in this tutorial. and SSTL3_I. often including free code examples. LVCMOS25. you could use the following constraint syntax: NET “red_light” IOSTANDARD=LVTTL. The clock signal on Global Clock Input 2 (GCK2) is divided by 2 as soon as it enters the device. so take care when assigning different I/O standards in a design. The CoolRunner-II family has several features that are aimed at reducing power consumption in the device.

You can set the default I/O standard under the Fitting tab of the Process Properties window.
FIGURE 5-11:
PROCESS PROPERTIES – IMPLEMENT DESIGN
The Help button will explain the operation of each field. A right-click on Implement Design allows you to edit the properties for each particular step. as shown in Figure 5-11. Xilinx • 141
. An orange question mark indicates that translate is now out of date and should be re-run.IMPLEMENTING CPLDS Click on the “+” next to Implement Design in the Process window.
FIGURE 5-10:
DESIGN PROCESS WINDOW
The implementation steps are now visible.

The CPLD Fitter Report can be opened in two ways.8V standard.
FIGURE 5-12:
ISE PREFERENCES
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. When there is a green tick next to Implement Design.QUICK START HANDBOOK • CHAPTER 5 In this case.
CPLD Reports
Two reports are available that detail the fitting results and associated timing of the design. we will set the Output Voltage Standard to LVCMOS18 so that all of our pins are configured to be compliant with the LVCMOS 1. go to Edit > Preferences > General > CPLD Fitter Report. You can implement your design by double-clicking on Implement Design. These are: The Translation Report shows any errors in the design or the UCF.P ROGRAMMABLE LOGIC D ESIGN -. expand the Optional Implementation Tools branch in the Process window. Then expand the Generate Timing branch and double-click on Timing Report. the design has completed the implementation stage. The timing analysis is performed by default on the design. To look at the Timing Report. To select which format to open. either in a standard text window within the ISE GUI or in a browser window.

The Mapped Inputs and Mapped Logic sections give information about signals. and pins in the fitted design. macrocells. but the HTML report has been designed to make the information more readable and easier to find. The Summary section of the report gives a summary of the total resources available in the device (256 macrocells.IMPLEMENTING CPLDS To open the CPLD Fitter Report. By clicking on a specific function block (e.g.
FIGURE 5-13:
CPLD HTML FITTER REPORT
The same information is contained in both the HTML and text reports. Xilinx • 143
.
The Function Block Summary looks into each function block and shows which macrocell is used to generate the signals on the external pins. etc. FB1) in the Function Blocks section. expand the Fit branch and double-click on the Fitter Report Process. The key to the meaning of the abbreviations is available by pressing the legend button. and how much is used by the design. all of the macrocells in that function block will be shown. 118 I/O pins.. The errors and warnings generated during fitting can be seen in the Errors and Warnings section.). You can browse through several sections of the HTML Fitter Report by using the menu on the left-hand side of the page.

vhd” for schematic flow) selected in the Sources window. and clock-to-out time. The next section shows all the inputs and outputs of the design and their timing relationship with the system clock. With “top_tb. The next section lists the longest setup time. The report shows that this design has a minimum cycle time of 7. or 140 MHz. A great feature of CPLDs is the deterministic timing. Xilinx • 144
.
Timing Simulation
The process of timing simulation is very similar to the functional method. as a fixed delay exists per macrocell. In the Simulation Run Time field. expand the ModelSim simulator section in the Process window and right-click on Simulate Post Fit VHDL Model. explaining the difference between the types mentioned previously in the report.vhd” (or “top_sch_tb.P ROGRAMMABLE LOGIC D ESIGN -. The maximum delay in this section dictates the maximum system frequency. These values are displayed in the first section of the report you will have created. “amber_light”. but the chosen I/O pins dictate which macrocells (and hence which function blocks) are used.0 ns delay with respect to the clock input. Three lights will have a 6. Select Properties. The Timing Report is able to give the exact propagation delays and setup times and clock-to-out times. The design could be packed into a single function block. These parameter limitations are dependent on the upstream and downstream devices on the board. The setup and clock-to-out times don’t strictly affect the design’s performance. cycle time (logic delay between synchronous points as constrained by the period constraint). of which only two have been used for logic functions in this design. The last section details all the path type definitions. “red_light” and “green_light” are the D-Type flip-flops used to register the outputs. then double-click on Simulate Post Fit VHDL Model. To generate a detailed timing report. The cycle time is the maximum period of the internal system clock.QUICK START HANDBOOK • CHAPTER 5 Clicking on a specific macrocell will bring up a diagram of how that macrocell is configured. right-click on Generate Timing in the Process window and select Properties > Timing Report Format > Detail. type “all. The clock to setup section details the internal nets to and from a synchronous point.” Click OK. An XC2C256 device has 16 function blocks.1 ns.

vhd is a very low-level VHDL file generated by the implementation tools. but this time implementing a different script file and compiling a post-route VHDL file (time_sim.
FIGURE 5-14:
SIMULATION WAVEFORM
Configuration
A DLC7 Parallel-IV JTAG cable is required to configure the device from the iMPACT programmer.IMPLEMENTING CPLDS MXE will open.
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. Use the zoom features and cursors to measure the added timing delays. Ensure that the cable is plugged in to the computer and that the ribbon cable/flying leads are connected properly to the board. You must also connect the power jack of the Parallel-IV cable to either the mouse or keyboard PS2 port of the PC. Time_sim. It references the resources within the CPLD and takes timing information from a separate file.vhd) is compiled.

FIGURE 5-15:
IMPACT
PROGRAMMER MAIN W INDOW
Right-click on the Xilinx XC2C256 icon that appears in the iMPACT window and select Program.P ROGRAMMABLE LOGIC D ESIGN -.vhd” highlighted in the Source window.QUICK START HANDBOOK • CHAPTER 5 With “top. double-click on Configure Device (iMPACT) in the Process window. You have now successfully programmed your first CoolRunner-II CPLD. The design will now download into the device.
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.

The implementation phase uses the netlist and a constraints file to recreate the design using the available resources within the FPGA. Obviously. The routing resources are then allocated to each connection. The whole process is automatic and requires little user input. The map stage distributes the design to the resources available in the FPGA. Map has the ability to “shuffle’ the design around LUTs to create the best possible implementation for the design.CHAPTER 6
Implementing FPGAs
Introduction
After you have successfully simulated your design. if the design is too big for the specified device. mapping will be incomplete. The map stage also uses the UCF file to understand timing and may sometimes decide to add further logic (replication) to meet the given timing requirements. the synthesis stage converts the text-based HDL design into an NGC netlist file. Constraints may be physical or timing and are commonly used for setting the required frequency of the design or declaring the required pin-out. it makes sense to place relevant CLBs next to each other simply to minimize the path length. again using a careful selection of the best possible routing types.
. The place and route stage works with the allocated CLBs and chooses the best location for each block. For a fast logic path. The netlist is a non-readable file that describes the actual circuit to be implemented at a very low level.

the software will automatically synthesize and fit. It will then generate the timing information before it opening MXE and giving timing simulation results.
WebPACK ISE software will automatically perform the steps required if a particular step is selected. we’ll demonstrate the steps required to successfully implement our traffic light design into a Spartan-3 FPGA.P ROGRAMMABLE LOGIC D ESIGN -. it is good practice to re-simulate. As all of the logic delays added by the LUTs and flip-flops are now known (as well as the routing delays). In this chapter. if you need a signal for many areas of the design. it may not be necessary to create a bit file on every implementation. The steps of implementation must be carried out in this order: 1. Finally. For example.
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. as you may only need to ensure that a particular portion of your design passes timing verification. the place and route tool would use a “longline” to span the chip with minimal delay or skew. At this point. a program called “bitgen” takes the output of place and route and creates a programming bitstream. 3. if the design has only just been functionally simulated and you decide to do a timing simulation. Synthesize Fit Timing Simulate Program. 4. When developing a design.QUICK START HANDBOOK • CHAPTER 6 For example. MXE can use this information for timing simulation. 2.

is now targeting a Xilinx Spartan-3 FPGA. originally targeted at a CoolRunner-II CPLD. The green ticks in the Process window should have disappeared and been replaced by orange question marks. select xc3s50 Change the Package field to tq144 Enter the Speed Grade as -4 Top Level Module HDL Synthesis Tool XST (VHDL/Verilog) Simulator ModelSim Generated Simulation Language VHDL Click on OK.
FIGURE 6-1:
SOURCES IN PROJECT W INDOW
Enter the following characteristics:
Change the Device Family to Spartan3 In the Device field.
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.
The project. shown inFigure 6-1. indicating that the design must be re-synthesized and re-implemented.IMPLEMENTING FPGAS Double-click on “xc2c256-7tq144 – XST VHDL” in the Sources window.

P ROGRAMMABLE LOGIC D ESIGN -.QUICK START HANDBOOK • CHAPTER 6
Synthesis
The XST synthesis tool will only attempt to synthesize the file highlighted in the Source window. The design should be okay because both the Bencher and MXE have already checked for syntax errors. You can now check your design by double-clicking on Check Syntax. Click on the HDL Options tab. In the Process window. a tick will appear (as shown in Figure 6-2). In the Sources window. Ensure that any errors in your code are corrected before you continue. “top. If the syntax check is OK.)
FIGURE 6-2:
PROCESSES W INDOW SHOWING CHECK SYNTAX HAS COMPLETED SUCCESSFULLY
Right-click on Synthesize and select Properties.” The synthesis tool recognizes all the lower level blocks used in the top-level code and synthesizes them together to create a single netlist. “stat_mac” and “counter. The Help feature explains each of the options in each tab. to periodically check your design for any mistakes using this feature. (It is useful. ensure that “top. A window will appear allowing you to influence the way in which your design is interpreted.vhd” (or “top_sch” for schematic flows) is highlighted.vhd” (for VHDL designs) or “top_sch” (for schematic designs) instantiates two lower level blocks. when writing code. In our traffic light design. Xilinx • 150
. expand the Synthesis subsection by clicking on the “+” next to Synthesize.

This is because of the abundance of flip-flops in FPGA architectures. Although this may seem wasteful. amber. and the design is likely to run much faster. and green) has been assigned its own 1-bit register. The I/O buffers will be attached to all of the port names in the top-level entity of the design. In the Xilinx Specific Options tab. Note that the state machine is one hot encoded.IMPLEMENTING FPGAS The FSM encoding algorithm option looks for state machines and determines the best method of optimizing. The first section of the report summarizes just the synthesis settings. Each entity in the design is then compiled and analyzed. Leave the setting on “auto” to achieve this fast one hot encoding. but it has a huge influence on how the design will perform in the targeted device.
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. as each state name (red. redamb. ensure that the Add I/O Buffers box is ticked. state machines are usually “one hot” encoded. For FPGAs. Clicking on Help in each tab demonstrates the complex issue of synthesis and how the final result could change. A one hot encoded state machine will use one flip-flop per state. The next section in the report gives synthesis details and documents how the design was interpreted. The synthesis tool will never alter the function of the design. Click OK in the Process Properties window and double-click on Synthesize. the next state logic is reduced.

FIGURE 6-4:
RESOURCE REPORT
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.
FIGURE 6-3:
EXTRACT OF SYNTHESIS REPORT
The Final Report section shows the resources used within the FPGA.” As registered outputs were selected in the state machine. three further registers were inferred.P ROGRAMMABLE LOGIC D ESIGN -.QUICK START HANDBOOK • CHAPTER 6 When synthesis chooses to use primitive macros it is known as “inference.

It will be necessary to delete these constraints. you must tell the implementation tools what and where performance is required. There are already some constraints in the UCF from the previous project implementation.ucf” in the Source window. Expand the “+” next to User Constraints and double-click Edit Constraints (Text). Double-click on Assign Package Pins. reset red_light green_light clock amber_light p36 p44 p52 p55 p46 Xilinx • 153
. assume that the specification for clock frequency is 100 MHz and that the pin-out has been pre-determined to that of a Spartan-3 device.
FIGURE 6-5:
PROCESS W INDOW SHOWING ASSIGN PACKAGE PINS
The PACE tool will be launched. Save the UCF and close it. This design is particularly slow and timing constraints are unnecessary. Highlight “top_constraints. Alternatively. pin locking is a physical constraint. you can highlight the top level (“top. Highlight all of the constraints and delete them. Constraints can also be physical.vhd”) and expand the User Constraints branch. Assign all I/O pins in the Design Object List as follows. For this design.IMPLEMENTING FPGAS
The Constraints File
To get the ultimate performance from the device.

QUICK START HANDBOOK • CHAPTER 6 Save and Exit the PACE session.
FIGURE 6-6: Click OK. as seen above Assign Package Pins in Figure 6-5. Double-click on Create Timing Constraints in the Process window.
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.P ROGRAMMABLE LOGIC D ESIGN -.
SPECIFY PERIOD CONSTRAINT
Click on the Ports tab in the Constraints Editor. As there were already constraints in the UCF. Double-click in the Period window of the global signal clock and enter a period of 10 ns. they have been imported. These can be edited by double-clicking on them in the read-write window or under the Ports tab in the Main window. Notice that the Constraints Editor is invoked and picks up the LOC constraints entered in PACE.

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.IMPLEMENTING FPGAS Highlight the three outputs “red_light.” and “amber_light” using ctrl select. In the Select Group box.
FIGURE 6-7:
CONSTRAINTS EDITOR – CREATE GROUP
In the Group Name field. select lights and hit the Clock to Pad button. type “lights” and then hit Create Group.” “green_light.

P ROGRAMMABLE LOGIC D ESIGN -.
FIGURE 6-8: Click OK. Also notice that the UCF generated has appeared in the UCF Constraints tab at the bottom of the screen. The UCF file should look similar to Figure 6-9. There is only one clock.QUICK START HANDBOOK • CHAPTER 6 In the Clock to Pad dialog box.
FIGURE 6-9:
COMPLETE CONSTRAINTS FILE
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. set the time requirement to 15 ns relative to the clock. but in some designs there may be more.
CLOCK TO PAD D IALOG BOX
Notice that the Clock to Pad fields have been filled in automatically.

FIGURE 6-11:
COMPLETED IMPLEMENTATION
A green tick means that the design ran through without any warnings. Click on the “+” next to Implement Design in the Process window. (You could run each stage separately if required. your design has completed the implementation stage.
FIGURE 6-10: PROCESS WINDOW SHOWING IMPLEMENT DESIGN Implement the design by double-clicking on Implement Design.IMPLEMENTING FPGAS Save and close the Constraints Editor session. Xilinx • 157
. and Place and Route. Map.) When there is a green tick next to Translate.

there should be no errors or warnings.
FPGA Reports
Each stage has its own report. The Guide Report shows how well a guide file has been met (if one was specified).
The Post Place and Route Static Timing Report adds the routing delays. It will also describe exactly where each portion of the design is located in the actual device. WebPACK ISE software has additional tools for complex timing analysis and floor planning. Notice that the max frequency of the clock has dropped.
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. The Map Report confirms the resources used within the device and describes trimmed and merged logic. The Place and Route Report gives a step-by-step progress report. is that an “fpga_don’t_touch” attribute has been applied to an instance.QUICK START HANDBOOK • CHAPTER 6 A yellow exclamation point may mean that there is a warning in one of the reports. which are beyond the scope of this introductory book. which can be safely ignored in CPLD designs. The Asynchronous Delay Report is concerned with the worst path delays in the design – both logic and routing. The Post-Map Static Timing Report shows the logic delays only (no routing) covered by the timing constraints. these traffic lights would run at 216 MHz! 4.
A detailed Map Report can be chosen in the Properties for map. The place and route tool must be aware of timing requirements.
If the logic-only delays don’t meet timing constraints. the clock period and the clock-to-out time of the three lights. The Translate Report shows any errors in the design or the UCF. 6. It will list the given constraints and report how comfortably the design fell within – or how much it failed – the constraints. 2. the additional delay added by routing will only add to the problem. A common warning. This design has two timing constraints. Without a routing delay. 5. 7. If you’ve followed the design procedure outlined in this example. 3. with information regarding the drive strength and signalling standard. Clicking on the “+” next to each stage lists the reports available: 1.P ROGRAMMABLE LOGIC D ESIGN -. The Pad Report displays the final pin-out of the design.

Open “top.
Summary
This chapter has taken the VHDL or Schematic design through to a working physical device. Ensure that the cable is plugged in to the computer and that the ribbon cable/flying leads are connected properly to the board. Double-click on Configure Device (iMPACT). The steps discussed were: • Synthesis and Synthesis report • Timing and Physical Constraints using the Constraints Editor • The Reports Generated throughout the Implementation flow • Timing Simulation • Creating and Downloading a bitstream. Expand the Generate Programming File tools subsection. From the Operations Menu.bit file that can be used by the iMPACT programmer to configure a device. Click on the picture of the device.
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.IMPLEMENTING FPGAS
Programming
Right-click on Generate Programming file and click on Properties. You must also connect the power jack of the Parallel-IV cable to either the mouse or keyboard port of the PC. A DLC7 Parallel-IV JTAG cable is required to configure the device from the iMPACT Programmer.bit” for schematic designs). right-click in the top half of the iMPACT window and select Add Xilinx Device. This operation creates a . Under the Start-Up Options tab. If the chain specified in the design is not automatically picked up from the ISE tool. ensure that the startup clock is set to JTAG Clock by selecting JTAG Clock from the drop-down menu. Browse to the location of the project (c:\designs\traffic) and change the file type to .bit” (“top_sch.bit. select Program. The iMPACT Programmer has drawn a picture of the programming chain. Double-click on Generate Programming File.

You can find microcontrollers in automobiles. We selected the application examples from a comprehensive list of application notes available from the Xilinx website.CHAPTER 7
Design Reference Bank
Introduction
Our final chapter contains a useful list of design examples and applications that will give you a good jump start into your future programmable logic designs. Microcontrollers are naturally good at sequential processes and computationally intensive tasks. microwave ovens. automatic teller machines.
. robotic devices. better. and cheaper products. the Xcell Journal (To subscribe. VCRs. but they most certainly help us get around in the world.xilinx. click on “Subscribe to Xcell Journal” at www. This section will also give you pointers on where to look for and download code and search for IP from the Xilinx website. In the never-ending quest for faster. advanced designers are now pairing CPLDs with microcontrollers to take advantage of the strengths of each. home security systems.com/publications/xcellonline/). to name just a few applications. and satellites.
Get the Most out of Microcontroller-Based Designs
Microcontrollers don’t make the world go round. as well as extracts from the Xilinx quarterly magazine. as well as a host of non-time-critical tasks. wireless telephones. point-of-sale terminals.

The typical operational speed is around 20 MHz. high-speed operations. This works out to an operational speed of only 3. you can quickly learn how to partition your designs across a CPLD and microcontroller to maximum advantage. they can perform those tasks with ultralow power consumption. which equates to impressive system speeds as fast as 285 MHz.
C ONVENTIONAL STEPPER MOTOR CONTROL
A frequent use of microcontrollers is to run stepper motors.33 MHz. The four windings have a common connection to the motor supply voltage (Vss). Thus. because they not only can perform high-speed tasks.5 ns.
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. Although faster and more powerful microcontrollers do exist. CoolRunner CPLDs are much. Xilinx offers free software and low-cost hardware design tools to support CPLD integration with microcontrollers. The Xilinx CPLD design process is quite similar to that used on microcontrollers. Today. CoolRunner CPLDs make ideal partners for microcontrollers. we are even seeing CoolRunner devices with input-to-output delays as short as 3. and applications where lots of inputs and outputs are required. 8-bit microcontrollers own much of the market because of their low cost and low power characteristics. a design partition over a microcontroller and a CPLD sounds good in theory. Figure 7-1 depicts a typical four-phase stepper motor driving circuit. much faster than microcontrollers and can easily reach system speeds in excess of 100 MHz. but some microcontroller cores divide clock frequency internally and use multiple clock cycles per instruction (operations often include fetch-and-execute instruction cycles). which typically ranges from 5V to 30V. but will it work in the field? We will devote the rest of this chapter to design examples that show how you can enhance a typical microcontroller design by utilizing the computational strengths of the microcontroller and the speed of a CoolRunner CPLD. So far.P ROGRAMMABLE LOGIC D ESIGN -.QUICK START HANDBOOK • CPLDs such as Xilinx CoolRunner devices are ideal for parallel processing. with a clock division of 2 – with each instruction taking as long as three cycles – the actual speed of a 20 MHz microcontroller is divided by 6.

The transistor selection depends on the drive current. The series resistors should be selected to limit the current to 8 mA per output to suit either the microcontroller or CPLD outputs. MOSFETs can also be used to drive stepper motors. and gain. (Incidentally.5 degrees per step. higher cost versions have a basic resolution of 1. the motor rotor rotates through 7.9 degrees per step.
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. The basic control sequence of a four-phase motor is achieved by activating one phase at a time. or 48 steps per revolution. More accurate. At the low-cost end. which is advantageous in precise positional control. Stepper motors tend to have a much lower torque than other motors.)
FIGURE 7-1:
STEPPER MOTOR CONTROLLER
Each motor phase current may range from 100 mA to as much as 10A. Furthermore.8 degrees per step. power dissipation.D ESIGN REFERENCE BANK A high-powered NPN transistor drives each of the four phases. it is possible to half-step these motors to achieve a resolution of 0.

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. the ABEL hardware description language targets PLDs. Using a JTAG Boundary Scan. Assembly language targets microcontrollers.
FIGURE 7-2:
D ESIGN FLOW COMPARISON
Both flows start with text entry. the PLD can then be programmed with the final code in-system via the JTAG port. We can then program the devices in-system using an inexpensive ISP cable.” the design is either compiled (microcontroller) or synthesized (PLD). The PLD can also be used as a “gateway” to test the rest of the board’s functionality. As Figure 7-2 illustrates. Microcontrollers can include monitor debug code internal to the device for limited code testing and debugging. With the advent of flash-based microcontrollers. One of the advantages of a PLD over a microcontroller occurs during board-level testing. these can now also be programmed in-system. the design flow for both is quite similar. Next. After entering the text “description.QUICK START HANDBOOK • The examples that follow show how either a microcontroller or a CPLD can control stepper motor tasks to varying degrees of accuracy. the design is verified by some form of simulation or test.P ROGRAMMABLE LOGIC D ESIGN -. the PLD can be fully tested on the board. the design is downloaded to the target device – either a microcontroller or PLD. Once verified. After the board-level test is completed.

The steps are: 1010 5V 0V 5V 0V 1001 5V 0V 0V 5V 0101 0V 5V 0V 5V 0110 0V 5V 5V 0V If you send this pattern repeatedly. A very common stepping code is given by the following hexadecimal numbers: A 9 5 6 Each hex digit is equal to four binary bits: 1010 1001 0101 0110 These binary bits represent voltage levels applied to each of the coil driver circuits. The manufacturer’s motor specification data sheet provides the stepping motor code. When logic level patterns are applied to each set of coils. The stepper motor that the microcontroller will control has four sets of coils. then the motor shaft rotates.
USING
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. the motor steps through its angles. The speed of the stepper motor shaft depends on how fast the logic level patterns are applied to the four sets of coils.D ESIGN REFERENCE BANK
A MICROCONTROLLER TO C ONTROL A STEPPER MOTOR Figure 7-3 shows assembly language targeting a Philips 80C552 microcontroller.

QUICK START HANDBOOK • The assembly language program in Figure 7-3 continually rotates the stepper motor shaft. The angle of rotation of the shaft will depend on the specific motor used. altering the value of R1 will give coarse variations in speed.P ROGRAMMABLE LOGIC D ESIGN -. this will give fine control over speed. entity step1 is
S TEPPER MOTOR CONTROL USING
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.all.Stepper Motor Controller library IEEE. use IEEE. The CLK input synchronizes the logic and determines the speed of rotation. The motor advances one step per clock period.
FIGURE 7-3:
ASSEMBLY LANGUAGE PROGRAM TO ROTATE THE STEPPER MOTOR SHAFT
A CPLD Figure 7-4 shows a design written in ABEL hardware description language. four inputs are required to fully control the stepper motor. Within the Xilinx CPLD. The enable input (EN) determines whether the motor is rotating or holding. By altering the value of R0 in the delay loop.
-.std_logic_1164. The active low reset input (RST) initializes the circuit to ensure that the correct starting sequence is provided to the outputs. The direction (DIR) control input changes the sequence at the outputs (PH1 to PH4) to reverse the motor direction.

PC-BASED MOTOR CONTROL
Our next example (Figure 7-5 and Figure 7-6) is more complex. it cannot be affected by extraneous system interrupts or other unconnected system state changes. This means that if the emergency stop is acti-
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. The ABEL hardware description motor control module can be embedded within a macro function and saved as a reusable standard logic block. and direction. which has the highest level of system interrupt. Extraneous system interrupts in a purely software-based system could cause indeterminate states that are hard to test or simulate. ph1. Therefore. The value of the direction input (DIR) determines which product term is used to sequence clockwise or counterclockwise. because now the motor is connected to a PC-based system via an RS-232 serial connection. or disabled (!EN).P ROGRAMMABLE LOGIC D ESIGN -. This “hardware” macro function is independent of any other function or event not related to its operation. The asynchronous equations (for example.AR=!rst) initialize the circuit. Such independence is critical in safety systems. There is also the addition of a safety-critical emergency stop. Each phase equation is either enabled (EN). which can be shared by many designers within the same organization – this is the beauty of design reuse. indicating that the current active phase remains on and the motor is locked. indicating that the motor is rotating.QUICK START HANDBOOK •
FIGURE 7-4:
CPLD ABEL PROGRAM TO CONTROL A STEPPER MOTOR
The phase equations (PH1 to PH4) are written with a colon and equal sign (:=) to indicate a registered implementation of the combinatorial equation. speed. This implementation has a closed loop system controlling rotation.

This configuration would also need a built-in UART. In a safety-critical system.P ROGRAMMABLE LOGIC D ESIGN -. The main functions it performs are: • Interrupt control • Status feedback to the PC • Accurate motor control.
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. the interrupt handling must be thoroughly mapped out. These extra functions usually add extra cost to the overall microcontroller device.QUICK START HANDBOOK • This design solution purely uses a microcontroller. The output from the motor rotation sensor is very fast. because interrupts could affect the speed of the motor.
D ESIGN PARTITIONING
As we noted before. and CPLDs are excellent in high-speed systems. Due to the nature of the microcontroller. emergency stops implemented in software require exhaustive testing and verification before they can be used in the final system to ensure that they operate properly under all software related conditions. This configuration would probably be implemented in a single microcontroller device with specific motor control peripherals. including software bugs and potential software states. microcontrollers are very good at computational tasks. so control of the speed of the motor could cause problems if system interrupts occurred. such as a capture-compare unit. with their abundance of I/Os.

• Decides direction of rotation of the motor. because it is very fast and has abundant inputs and outputs. Meanwhile. Additionally. • Recovers from emergency stops. Although the microcontroller performs recovery from emergency stops. • Monitors progress (control loop) and adapts speed. or imple• 171
. • Converts required speed into control vectors (small mathematical algorithm). • Reports status of the motor to the PC. • Computes stop point and sets a value into the pulse count comparison register. Because the CPLD is considered independent hardware.
FIGURE 7-7:
PARTITIONED DESIGN: MICROCONTROLLER AND CPLD
The microcontroller: • Interprets ASCII commands from the PC. all of the high-speed interface functions are also implemented in the CPLD. the UART and FIFO sections of the design can be implemented in the microcontroller in the form of a microcontroller peripheral. because this is the safetycritical part of the design. the actual emergency stop is implemented by the CPLD. safety-critical proving and sign-off are more straightforward than software safety systems.D ESIGN REFERENCE BANK Figure 7-7 shows how we can use a microcontroller and a CPLD in a partitioned design to achieve the greatest control over a stepper motor.

a capture-compare unit for accurate motor control. The CoolRunner family of ultra-low power CPLDs are an ideal fit in this arena and may be used to complement your low-power microcontroller to integrate designs in battery-powered. This solution uses low-cost devices to implement the functions they do best – computational functions in the microcontroller and high-speed. In low-power applications. a Xilinx Spartan device. and potentially absorb all of the other discrete logic functions in a Design – thus presenting a truly reconfigurable system. we can consider the CPLD as offering hardware-based subroutines or as a mini co-processor. reduce costs. Using a PLD in this design has the added benefit of gaining the ability to absorb any other discrete logic elements on the PCB or in the total design into the CPLD. Under this new configuration. more granular PLD such as an FPGA – for example. Low-cost microcontrollers are now in the region of US $1. In safety-critical systems. microcontrollers are universally accepted as low-power devices and have been the automatic choice of designers. or UARTs). high I/O tasks in the CPLD. ADCs.QUICK START HANDBOOK • mented in a larger. Partitioning your design across the two devices can increase overall system speeds. but it now has more time to perform these operations – without interruption. The motor control is now independently stable and safe. portable designs (<100 µA current consumption at standby).00. why not put the safety-critical functions in “hardware” (CPLDs) to cut down on safety system approval time scales? System testing can also be made easier by implementing the difficult-tosimulate interrupt handling into programmable logic. A low cost microcontroller coupled with a low cost CPLD from Xilinx can deliver the same performance at approximately half the cost. The design process for a microcontroller is very similar to that of a programmable logic device.
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. but if your design requires extra peripherals (for example. this can quadruple the cost of your microcontroller. Microcontroller/CPLD design partitioning can reduce overall system costs.
C ONCLUSION
Microcontrollers are ideally suited to computational tasks. This permits a shorter learning and designing cycle.P ROGRAMMABLE LOGIC D ESIGN -. The microcontroller still performs ASCII string manipulation and mathematical functions. I/O-intensive operations. whereas CPLDs are suited to very fast.

com/apps/appsweb.)
Documentation and Example Code
The following is a list of selected application notes.htm. Spring 2001. Thus. tutorials. white papers. your first project using CPLDs can be not only quick and painless. and example code that can be downloaded from the Xilinx website. For the latest list. (Excerpted from the Xilinx Xcell Journal. This list grows longer as more applications are developed. but very cost-effective as well. Issue 39.xilinx. TABLE 7-1: DOCUMENTATION LIST Title Embedded Instrumentation Using XC9500 CPLDs Configuring Xilinx FPGAs Using an XC9500 CPLD and Parallel PROM Xilinx FPGAs: A Technical Overview for the First-Time User Choosing a Xilinx Product Family XC9500 Remote Field Upgrade A Quick JTAG ISP Checklist A CPLD VHDL Introduction Adapting ASIC Designs for Use with Spartan FPGAs 170 MHz FIFOs using the Virtex Block SelectRAM+ Feature Synthesizable HighPerformance SDRAM Controllers Number XAPP076 XAPP079 Family XC9500 XC9500 Design Code
XAPP097
FPGA
XAPP100 XAPP102 XAPP104 XAPP105 XAPP119 XAPP131
All XC9500 XC9500 XC9500 Spartan Virtex
XAPP134
Virtex
FREE VHDL and Verilog
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.D ESIGN REFERENCE BANK Full-functioning software design tools for Xilinx CPLDs are free of charge and may be downloaded from the Xilinx website. please visit www.

Type of high-integration chip or chipset ASIC that is designed for a common yet specific application. CMOS offers lower power consumption and smaller chip sizes compared to bipolar and now meets or even beats TTL speed. using computers to design products. but are more sensitive to parametric changes and are thus less robust. CAD – Computer Aided Design. ASIC – Application Specific Integrated Circuit. Asynchronous designs can be faster than synchronous ones. low-level language for design entry. also called a gate array. CMOS – Complementary Metal-Oxide-Silicon. Anti-fuse-based FPGAs are thus non-volatile and can be programmed only once (see OTP).GLOSSARY OF TERMS
GLOSSARY OF TERMS
ABEL – Advanced Boolean Expression Language. that might not meet specification or be defective. AQL – Acceptable Quality Level. A very high-speed (megahertz to gigahertz) connection-oriented bit-serial protocol for transmitting data and realtime voice and video in fixed-length packets (48-byte payload. CAE – Computer Aided Engineering. A CLB contains two or four LUTs (function generators) plus two or four flip-flops. Behavioral Language – Top-down description from an even higher level than VHDL. Asynchronous logic that is not synchronized by a clock. The relative number of devices. ATM – Asynchronous Transfer Mode. AIM – Advanced Interconnect Matrix in the CoolRunner-II CPLD that provides the flexible interconnection between the PLA function blocks. Dual-port and synchronous operation are desirable. ASSP – Application-Specific Standard Product. expressed in parts-per-million (ppm). CLB – Configurable Logic Block. 5-byte header). Block RAM – A block of 2k to 4k bits of RAM inside an FPGA.
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. from Data I/O. analyses designs created on a computer. Back Annotation – Automatically attaching timing values to the entered design format after the design has been placed and routed in an FPGA. Xilinx-specific name for a block of logic surrounded by routing resources. Antifuse – A small circuit element that can be irreversibly changed from being non-conducting to being conducting with ~100 Ohm. Has replaced the older bipolar TTL technology in most applications (except very fast ones). Typical values are around 10 ppm. Dominant technology for logic and memory.

CPLD development tool available from Logical Devices. Input Hysteresis – Input hysteresis provides designers with a tool to minimize external components. DRAM – Dynamic Random Access Memory. and can accept wide inputs. DLL – Delay Locked Loop. Usually measured in gates.QUICK START HANDBOOK • Compiler – software that converts a higher language description into a lower-level representation. Provides zero-delay clock buffering. DCM – Digital Clock Manager. CoolCLOCK – Combination of the clock divider and clock doubler functions in CoolRunner-II CPLDs to further reduce power consumption associated with high-speed clocked-in internal device networks. Constraints – Performance requirements imposed on the design. often used to mean capacity. the act of loading an FPGA with that file. Function found in CoolRunner-II CPLDs (may also be referred to as Schmitt Trigger inputs in the text). place and route process. Configuration – The internally stored file that controls the FPGA so that it performs the desired logic function. DCI uses two external high-precision resistors to incorporate equivalent input and output impedance internally for hundreds of I/O pins. PAL-derived programmable logic devices that implement logic as sum-of-products driving macrocells. CUPL – Compiler Universal for Programmable Logic. A digital circuit used to perform clock management functions on. or required operating frequency. CPLD – Complex Programmable Logic Device. and precise frequency generation on Xilinx Virtex-II FPGAs. precise phase control. whether using the inputs to create a simple clock source or reducing the need for external buffers to sharpen a slow or noisy input signal. DCI – Digitally Controlled Impedance in the Virtex-II solution dynamically eliminates drive strength variation due to process. usually in the form of max allowable delay. For FPGAs: the complete partition. synonymous with EPLD. each consisting of a 4-input LUT and a flip-flop. but for FPGAs. temperature. Can be selected on all inputs. Xilinx • 184
. CPLDs are known to have short pin-to-pin delays. but have relatively high power consumption and fewer flip-flops compared to FPGAs. DataGATE – A function within CoolRunner-II devices to block free-running input signals. Also. better expressed in logic cells.P ROGRAMMABLE LOGIC D ESIGN -. Density – Amount of logic in a device. effectively blocking controlled switching signals so they do not drive internal chip capacitances to further reduce power consumption. and voltage fluctuation. Debugging – The process of finding and eliminating functional errors in software and hardware. A low-cost/read-write memory where data is stored on capacitors and must be refreshed periodically.and off-chip.

Device temperature must be specified. PAL-derived programmable logic devices that implement logic as sum-of-products driving macrocells. better utilization. High-voltage discharge can rupture the input transistor gate oxide. an alternative to Electrically-Erasable Programmable Read-Only Memory (EEPROM) technology. Describes the number of device failures statistically expected for a certain number of device-hours. Expressed as failures per one billion device hours. EPLDs are known to have short pin-to-pin delays. EDIF – Electronic Data Interchange Format. A FIFO needs no external addresses. 5-Volt Tolerant – Characteristic of the input or I/O pin of a 3. and higher performance. and Fast Fourier Transform EAB – Embedded Array Block. MTBF can be calculated from FIT. ESD – Electro-Static Discharge. EPLD – Erasable Programmable Logic Devices. although all modern FIFOs are implemented internally with RAMs driven by circular read and write counters. where data is stored in the incoming sequence and is read out in the same sequence. Input and output can be asynchronous to each other.3V device that allows this pin to be driven to 5V without any excessive input current or device breakdown. Can achieve faster compilation. Flip-Flop – Single-bit storage cell that samples its Data input at the active (rising or falling) clock edge. Altera™ name for block RAM in FLEX10K. Avoids the delay and additional connections of an external RAM. holding it there until after the next active clock edge. DSP – Digital Signal Processing. The memory content can be erased by an electrical signal. convolution. Industry-standard for specifying a logic design in text (ASCII) form. and then presents the new state on its Q output after that clock edge. This allows in-system programmability and eliminates the need for ultraviolet light and quartz windows in the package. The manipulation of analog data that has been sampled and converted into a digital representation.GLOSSARY OF TERMS DRAMs are usually addressed by a sequence of two addresses – row address and column address – which makes them slower and more difficult to use than SRAMs. Xilinx • 185
. and can accept wide inputs. but have relatively high power consumption and fewer flip-flops than FPGAs. Very desirable feature. ESD-protection diodes divert the current to the supply leads. FIFO – First-In-First-Out memory. FIT – Failure In Time. Examples are filtering. Embedded RAM – Read-write memory stored inside a logic device. Floorplanning – Method of manually assigning specific parts of the design to specific chip locations. synonymous with CPLDs. Flash – Non-volatile programmable technology.

Although all SRAM-based FPGAs are naturally ISP.P ROGRAMMABLE LOGIC D ESIGN -. and windows. Footprint-compatible devices can be interchanged without modifying the PC board. N is between 2 and 6. IQ – Extended temperature devices for automotive and industrial applications.QUICK START HANDBOOK • Footprint – The printed circuit pattern that accepts a device and connects its pins appropriately. and trade secrets. Logic block with features specialized for interfacing with the PC board. ISP – In-System Programmable device. A 2-input NAND gate is used as the measurement unit for gate array complexity. Smallest logic element with several inputs and one output. In integrated circuits: pre-defined large functions. 4-input function generators are most popular. HDL – Hardware Description Language. IP – Intellectual Property. Incremental design making small design changes while maintaining most of the layout and routing. called cores. Alternative: flat design. Can implement any logic function of its N-inputs.. this term is only used with certain CPLDs. icons. where everything is described at the same level of detail. to distinguish them from the older CPLDs that must be programmed in programming equipment. GAL – Generic Array Logic. Interconnect – Metal lines and programmable switches that connect signals between logic blocks and between logic blocks and the I/O. Hierarchical Design – Design description in multiple layers. Function Generator – Also called look-up-table. OR gate output is high when at least one input is high. that help you complete large designs faster. A high-speed. Lattice name for a variation on PALs Gate. Pioneered by Xerox and the Macintosh. AND gate output is high when all inputs are high. now universally adopted (e. A programmable logic device that can be programmed after it has been connected to (soldered into) the system PC board. Xilinx is certified to ISO9001 and ISO9002. An integrated circuit that contains configurable (programmable) logic blocks and configurable (programmable) interconnect between those blocks. In the legal sense: patents. Gate Array – ASIC where transistors are pre-defined. by Windows 95). low-power back-plane standard. pictures. with N-inputs and one output. IOB or I/O – Input/Output block. GUI – Graphic User Interface. A way of representing the computer output on the screen as graphics. from the highest (overview) to the lowest (circuit details). copyrights. Xilinx • 186
. and only the interconnect pattern is customized for the individual application.g. GTL – Gunning Transceiver Logic. FPGA – Field Programmable Gate Array. ISO9000 – An internationally recognized quality standard.

LUT – Look-Up Table. Very similar to LPM. With FPGAs. gate array. Fuses and anti-fuses are inherently OTP. like data width. LPM – Library of Parameterized Modules. Partitioning – In FPGAs. A 33 MHz PCI can support data byte transfers of up to 132 megabytes per second on 36 parallel data lines (including parity) and a common clock. One logic cell is one 4-input look-up table plus one flip-flop.1 Boundary Scan. NRE – Non-Recurring Engineering charges. light loading. See also XNF and EDIF. LogiBLOX – Formerly called X-Blox. Library of logic modules. Library of logic modules.
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. PAL – Programmable Array Logic. N is between 2 and 6. (Also: People Can’t Memorize Computer Industry Acronyms). Mapping – Process of assigning portions of the logic design to the physical chip resources (CLBs). Pays for layout. Also called function generator with N inputs and one output. low cost. and high performance. Physical and electrical standard for small plug-in boards for portable computers. There is also a new 66 MHz standard. Irreversible method of programming logic or memory. Logic Cell – Metric for FPGA density. Can implement any logic function of its N inputs. MTBF – Mean Time Between Failure. a method to test PC boards and ICs. Older name for IEEE 1149. 4-input LUTs are most popular. Very similar to LogiBlox. See also FIT. PCI – Peripheral Component Interface. PCMCIA – Personal Computer Memory Card Interface Association.GLOSSARY OF TERMS JTAG – Joint Test Action Group. FPGAs and CPLDs do not require NRE. The statistically relevant up-time between equipment failure. Netlist – Textual description of logic and interconnects. the process of dividing the logic into sub-functions that can later be placed into individual CLBs. OTP – One-Time Programmable. Partitioning precedes placement. mapping is a more demanding and more important process than with gate arrays. Startup cost for the creation of an ASIC. or HardWire. Oldest practical form of programmable logic. implemented a sum-of-products plus optional output flip-flops. Macrocell – The logic cell in a sum-of-products CPLD or PAL/GAL. and test development. Optimization – Design change to improve performance. See also Synthesis. often with user-definable parameters. masks. Synchronous bus standard characterized by short range. EPROMs and EPROM-based CPLDs are OTP if their plastic package blocks the ultraviolet light needed to erase the stored data or configuration. often with user-definable parameters. like data width.

or thousandth of a millimeter) The state of the art is moving Xilinx • 188
. In Xilinx FPGAs.P ROGRAMMABLE LOGIC D ESIGN -. and FPGAs. SPROM – Serial Programmable Read-Only Memory. or the process of creating the desired interconnection. Placement – In FPGAs. Schematic – Graphic representation of a logic design in the form of interconnected gates. receives a clock. Simulation – Computer modeling of logic and (sometimes) timing behavior of logic driven by simulation inputs (stimuli or vectors). Routing follows partitioning and placement. Non-volatile memory device that can store the FPGA configuration bitstream. The first and most flexible programmable logic configuration with two programmable planes providing any combination of “AND” and “OR” gates and sharing of AND terms across multiple ORs. Older and more visually intuitive alternative to the increasingly more popular equation-based or high-level language text description of a logic design. and outputs a serial bitstream. Usually done automatically. an alternative mode of operation for every function generator (LUT) that are part of every CLB in Virtex and Spartan FPGAs. CPLDs. Sub-Micron – The smallest feature size is usually expressed in micron (µ = millionth of a meter. implemented in a LUT. QML – Qualified Manufacturing Line. This architecture is implemented in CoolRunner and CoolRunner-II devices. a point where two signal lines can be connected. PLA – Programmable Logic Array. SelectRAM – Xilinx-specific name for a small RAM (usually 16 bits). Static Timing – Detailed description of on-chip logic and interconnect delays. Routing – The interconnection. The SPROM has a built-in address counter. the process of assigning specific parts of the design to specific locations (CLBs) on the chip. Most generic name for all programmable logic: PALs. as determined by the device configuration. of logic cells to make them perform the desired function. Faster than DRAM and with simpler timing requirements. Pin-locking has become important. PIP – Programmable Interconnect Point. since circuit-board fabrication times are longer than PLD design implementation times. SRAM – Static Random Access Memory. ISO9000. This mode increases the number of flip-flops by 16.QUICK START HANDBOOK • Pin-Locking – Rigidly defining and maintaining the functionality and timing requirements of device pins while the internal logic is still being designed or modified. and larger blocks. Adding flip-flops enables fast pipelining – ideal in DSP applications. SRL16 – Shift Register LUT. Read-write memory with data stored in latches. PLD – Programmable Logic Device. flip-flops. but smaller in size and about four times as expensive than DRAM of the same capacity. For example.

8µ.4µ. Each I/O pin is individually programmable for any of the 19 singleended I/O standards or six differential I/O standards. self-clocking bitserial bus (1. VME – Older bus standard. as opposed to asynchronous circuitry that responds to a multitude of derived signals. longline.18µ. and GTL+. Used for multiplexing different data sources onto a common bus. performance. ground. differential data) to daisy-chain as many as 128 devices. Timing – Relating to delays. TBUFs – Buffers with a tri-state option. Synchronous – Circuitry that changes state only in response to a common clock.4 to 0. or speed. where the output can be made inactive. including LVDS. debug. popular with MC68000-based industrial computers. An 8-bit-parallelto-serial and serial-to-8-bit-parallel converter. combined with parity and startdetect circuitry and sometimes even FIFO buffers. low-cost. SSTL. The pulldown-only option can use the bus as a wired AND function. HSTL II. UART – Universal Asynchronous Receiver/Transmitter.25µ. SelectIO-Ultra technology delivers 840 Mbps LVDS performance using dedicated DDR registers.
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. XNF File – Xilinx proprietary description format for a logic design Alternative: EDIF.GLOSSARY OF TERMS from 0.5 MHz and 12 MHz) using four wires (Vcc. SystemI/O – Technology incorporated in Virtex-II FPGAs that uses the SelectIO-Ultra blocks to provide the fastest and most flexible electrical interfaces available. USB – Universal Serial Bus. and dedicated carry. 1 mil = 25. and may soon reach 0.35µ to 0. Timing Driven – A design or layout method that takes performance requirements into consideration. Synthesis precedes mapping. low-speed. like LUTs. A new. Synchronous circuits are easier to design. and tolerate parameter changes and speed upgrades better than asynchronous circuits. The wavelength of visible light is 0. Synthesis – Optimization process of adapting a logic design to the logic resources available on the chip. Used widely in asynchronous serial communications interfaces such as modems. and modify.