Monolithic 3D IC Technologies

In this installment of our 3D IC mini-series, we ponder the use of esoteric materials and monolithic 3D IC technologies.

In my previous columns on 3D ICs, we considered the way things used to be, along with the current state of play. Everything we've discussed thus far might fall under the umbrella of conventional technologies. They are simply evolutionary enhancements (and adaptations) of proven and accepted silicon-based materials and techniques. Other materials, if they came into play, could significantly change the 3D IC landscape.

Take graphene, an allotrope of carbon. It has a structure of one-atom-thick planar sheets formed from carbon atoms packed densely in a honeycomb crystal lattice. In addition to being incredibly strong (measurements have shown a breaking strength 200 times higher than steel), this material is an excellent conductor of electricity. It also has fantastic thermal conductivity -- better than even nanotubes and diamond. Suppose we could lay graphene sheets down layer by layer, patterning each layer with the equivalent of transistors and separating adjacent layers with a few atoms of insulating material. The results could be mind boggling.

Graphene is an atomic-scale honeycomb lattice made of carbon atoms.

Of course, graphene won't be used in this way in the near future, unless something completely unexpected happens. Also, we should recognize the billions of dollars that have been invested in the silicon-based infrastructure. Fortunately, there are other options closer to home.

Monolithic 3D ICs
Here's a 30,000-foot description of a relatively new approach that seems very promising: the Monolithic 3D IC technology. All the following numbers are approximations and/or rounded values. They are intended only to provide a sense of scale.

We start with a regular wafer ~700 μm (0.7 mm) thick. The active/device layer (the doped region containing the transistors) is ~20 nm thick -- 1/50th of 1 μm, which is infinitesimal when compared to the thickness of the wafer as a whole.

We then add the metallization layers as usual. These layers may have different thicknesses, depending on what we want them to do (signal or power, for example). Between each pair of adjacent metal layers, we will need an isolation layer (silicon dioxide or a low-k dielectric layer). We end with a final layer of silicon dioxide, and we polish the surface of the wafer to be as flat as possible. In fact, the wafer is polished multiple times as the metal/dielectric layer combos are added.

Cross section of a standard wafer with metallization.

To provide something to visualize (and to round things furiously), let's say that we have eight or nine metal layers. Adding everything together, the stack of metal and insulating layers is ~1 μm thick. This is where things start to get very interesting.

There seems to be some usual confusion going on here between 3-d stacking of dice ea. first processed separately on separate wafers to build device ( the original question by Lasheras ) and devices built one on top of another on the same wafer ( in the response by Zvi ).

in the first case the thermally conductive Cu used to fill the through vias can aid vertical heat dispersal but not completely since they also introduce stress if placed too close to the transistors. the TSVs do nothing to directly aid lateral heat dispersal. IBM / 3M and a few others are working on this part as local heat build up impacts memory refresh times.

For the second config. of 3-d, which Zvi has been championing for a while, what are the vias between transistors built one on top of another made of ? Copper or still much less conductive Tungsten ? Samsung's 3-d NAND sticks to usual CVD W. But as Zvi says, the heat transfer distances are within microns and so the fluxes could be acceptable even with vias filled with CVD W which has a k just a quarter of Cu.

Yes, copper is a good heat conductor and there is a general need to have a good power delivery which imply use of thick copper wires across the device with many vias to spread the power across the device.

In monolithic 3D we can have many vias which provides good heat transfer from the inner transistors layers to the device heat-sink. And the very thin layers of monolithic 3D means that the distance from where the heat is being generated to where it could dissipate is only few microns. Accordingly the power-distribution-network could be used to effectively removed the inner heat.

It should be noted that monolithic 3D is most effective way to reduce the overall heat generated in IC device as it significantly reduce the average interconnect length.

Or_Bach: "the heat could be very effectively be removed using the power distribution network (PDN)"

Thank you very much for this valious update. The blog you are pointing out is really interesting. So, you reuse the Power Distribution Network in the same way some heat sinks use heat pipes -- but immersed into the "dice". Is this right?

Heat removal is a known issue and important one. The advantage of the monolithic 3D stacked device is that all upper layers are thin and not too far from the base wafer bulk or from the upper surface of the device. In IEDM 2012 we had published joint work with Stanford University showing that the heat could be very effectively be removed using the power distribution network (PDN). The work was also covered by a follow on blog: http://www.monolithic3d.com/2/post/2012/12/can-heat-be-removed-from-3d-ic-stacks.html

@Garcia: One of the main issues with 3D ICs is how to get rid of the extra heat that is produced inside the "dice". I've heard that a very promising alternative is embedding active cooling devices into the IC -- e.g. Peltier towers. Do you have any clue about this?

Sadly not -- but I'm sure the folks at MonolithicIC3D do. I will "ping" them and ask them to comment here.

This is a very interesting column, Max. Your explanation about the physical processes involved in building this kind of 3D ICs is very clear and enlightening.

But I've a question for you. One of the main issues with 3D ICs is how to get rid of the extra heat that is produced inside the "dice". I've heard that a very promising alternative is embedding active cooling devices into the IC -- e.g. Peltier towers. Do you have any clue about this?