Rules for multiple SPI write cycles in succession

What are the timing limits to send multiple configuration commands to the ADIS16364? Can I send some arbitrary number of SPI command cycles within the same frame of 1 cycle of SS* HIGH to LOW to HIGH or does each transmission require an independent SS* cycle? If multiple cycles are allowed I would assume a reasonable time of 1 uSec minimum between the last clock rising edge of SCLK of a SPI cycle and the first clock falling edge of SCLK of the next SPI cycle. Is this a valid assumption or is a longer wait necessary?