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Configuration

This register has no effect if EL2 is not enabled in the current Security state.

Some or all RW fields of this register have defined reset values.
These apply
only if the PE resets into an Exception level that is using AArch64.
Otherwise,
RW fields in this register reset to architecturally UNKNOWN values.

Bits [63:32]

EOIcount, bits [31:27]

This field is incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation. That is either:

A virtual write to EOIR with a valid interrupt identifier that is not in the LPI range (that is < 8192) when EOI mode is zero and no List Register was found.

A virtual write to DIR with a valid interrupt identifier that is not in the LPI range (that is < 8192) when EOI mode is one and no List Register was found.

This allows software to manage more active interrupts than there are implemented List Registers.

It is CONSTRAINED UNPREDICTABLE whether a virtual write to EOIR that does not clear a bit in the Active Priorities registers (ICH_AP0R<n>_EL2/ICH_AP1R<n>_EL2) increments EOIcount. Permitted behaviors are:

NPIE, bit [3]

No Pending Interrupt Enable. Enables the signaling of a maintenance interrupt when there are no List registers with the State field set to 0b01 (pending):

NPIE

Meaning

0b0

Maintenance interrupt disabled.

0b1

Maintenance interrupt signaled while the List registers contain no interrupts in the pending state.

This field resets to 0.

LRENPIE, bit [2]

List Register Entry Not Present Interrupt Enable. Enables the signaling of a maintenance interrupt while the virtual CPU interface does not have a corresponding valid List register entry for an EOI request:

LRENPIE

Meaning

0b0

Maintenance interrupt disabled.

0b1

Maintenance interrupt is asserted while the EOIcount field is not 0.

This field resets to 0.

UIE, bit [1]

Underflow Interrupt Enable. Enables the signaling of a maintenance interrupt when the List registers are empty, or hold only one valid entry:

UIE

Meaning

0b0

Maintenance interrupt disabled.

0b1

Maintenance interrupt is asserted if none, or only one, of the List register entries is marked as a valid interrupt.

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