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Key Features Of PCIe

Compatible with the current PCI software model: There are no changes required to the current Operating Systems while maintaining platform configuration and device driver interfaces. Enables smooth integration within future system allowing for broad industry adoption.

Serial architecture; Low-pin-count point-to-point connection (link): Does away with some of the limitations of parallel bus architectures by using embedded clock timing and differential signaling. The embedded clock lowers pin count (no separate control and clock pins are required) and makes data synchronization easier than in a parallel-based technology. Data can traverse a connector and cable scheme allowing flexible system partitioning. Serial technology enables unique and small form factors, reduces cost, simplifies board design and routing and reduces signal integrity issues. Point-to-point interconnect means no multiple hosts on same bus creating a bottleneck.

Packetized protocol: Time multiplexing versus circuit switching. This allows more than two-way communication at one time unlike circuit switching where only a two-way communications can occur. With packet based protocol there is no wasted bandwidth.