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Automating the Creation of Your UVM Register Model

On-demand Web Seminar

This webinar will introduce the Register Assistant feature of the Questa Verification Platform and show how it can be used to quickly generate correct-by-construction register models and tests from a register specification.

Details

Overview

The UVM Register Layer is a great way to abstract the interaction between your testbench and your DUT from the pin-level, or even protocol-specific transactions to a generic register-based view of communication. This abstraction provides many benefits, not the least of which is isolating your stimulus generation and coverage modeling from low-level changes in your design (i.e. separating the what from the how). Unfortunately, the benefits of using the register layer come at the cost of having to specify the register models in your testbench to reflect the registers in your hardware. With thousands or even tens of thousands of registers in a typical design, this can be a laborious and error-prone process when done from scratch. This webinar will introduce the Register Assistant feature of the Questa Verification Platform and show how it can be used to quickly generate correct-by-construction register models and tests from a register specification.

What You Will Learn

Brief review of the UVM Register Layer data model

Creating a spreadsheet-based Register Specification

Generating the register model code

Modifying your Register Specification

Adding Coverage and other advanced capabilities to your register model

About the Presenter

Tom Fitzpatrick

Verification Technologist

Tom Fitzpatrick is currently a Verification Technologist at Mentor Graphics Corp. where he brings over two decades of design and verification experience to bear on developing advanced verification methodologies, particularly using SystemVerilog, and educating users on how to adopt them. He has been actively involved in the standardization of SystemVerilog, starting with his days as a member of the Superlog language design team at Co-Design Automation through its standardization via Accellera and then the IEEE, where he has served as chair of the 1364 Verilog Working Group, as well as a Technical Champion on the SystemVerilog P1800 Working Group. At Mentor Graphics, Tom was one of the original designers of the Advanced Verification Methodology (AVM), and later the Open Verification Methodology (OVM), and is the editor of Verification Horizons, a quarterly newsletter with approximately 40,000 subscribers. He is a charter member and key contributor to the Accellera Verification IP Technical Subcomittee. He has published multiple articles and technical papers about SystemVerilog, verification methodologies, assertion-based verification, functional coverage, formal verification and other functional verification topics.

Verification Horizons

We have created the Verification Horizons newsletter to provide concepts, values, methodologies and examples to assist with the understanding of what advanced functional verification technologies can do and how to most effectively apply them. Verification Horizons