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Abstract:

A register circuit is provided which can hold data even after being
powered off and which does not require a save operation and a return
operation. In a register circuit including a plurality of register
component circuits, a first transistor with small off-state current, and
a second transistor with small off-state current, a data holding portion
is connected to one of a source and a drain of the first transistor and
one of a source and a drain of the second transistor. Since the first
transistor and the second transistor have a small off-state current,
electric charge does not leak from the data holding portion, and data is
held by the data holding portion even after the register circuit is
powered off. Thus, a save operation and a return operation are not
required.

Claims:

1. A semiconductor device comprising: a register circuit comprising: a
register component circuit comprising: a buffer circuit; a logic circuit;
and a first transistor; and a second transistor, wherein a first terminal
of the register component circuit is electrically connected to an input
terminal of the buffer circuit, a first terminal of the first transistor,
and a first terminal of the second transistor, wherein a second terminal
of the register component circuit is electrically connected to a second
terminal of the first transistor, wherein a third terminal of the
register component circuit is electrically connected to an output
terminal of the buffer circuit, wherein a fourth terminal of the register
component circuit is electrically connected to a first input terminal of
the logic circuit, and wherein an output terminal of the logic circuit is
electrically connected to a gate of the first transistor.

2. The semiconductor device according to claim 1, wherein the register
component circuit comprises a capacitor, and wherein a first terminal of
the capacitor is electrically connected to the first terminal of the
register component circuit.

3. The semiconductor device according to claim 1, further comprising an
inverter circuit, wherein an input terminal of the inverter circuit is
electrically connected to the fourth terminal of the register component
circuit, and wherein an output terminal of the inverter circuit is
electrically connected to a gate of the second transistor.

4. The semiconductor device according to claim 1, wherein the logic
circuit is a NOR circuit, and wherein a fifth terminal of the register
component circuit is electrically connected to a second input terminal of
the logic circuit.

5. The semiconductor device according to claim 1, wherein the first
transistor comprises an oxide semiconductor layer comprising a channel
formation region, and wherein the second transistor comprises an oxide
semiconductor layer comprising a channel formation region.

6. A semiconductor device comprising: a register circuit comprising: a
first register component circuit comprising: a first buffer circuit; a
first logic circuit; and a first transistor; a second register component
circuit comprising: a second buffer circuit; a second logic circuit; and
a second transistor; and a third transistor, wherein a first terminal of
the first register component circuit is electrically connected to an
input terminal of the first buffer circuit, a first terminal of the first
transistor, and a first terminal of the third transistor, wherein a
second terminal of the first register component circuit is electrically
connected to a second terminal of the first transistor, wherein a third
terminal of the first register component circuit is electrically
connected to an output terminal of the first buffer circuit, wherein a
fourth terminal of the first register component circuit is electrically
connected to a first input terminal of the first logic circuit, wherein
an output terminal of the first logic circuit is electrically connected
to a gate of the first transistor, wherein a first terminal of the second
register component circuit is electrically connected to an input terminal
of the second buffer circuit, a first terminal of the second transistor,
and the second terminal of the first register component circuit, wherein
a second terminal of the second register component circuit is
electrically connected to a second terminal of the second transistor,
wherein a third terminal of the second register component circuit is
electrically connected to an output terminal of the second buffer
circuit, wherein a fourth terminal of the second register component
circuit is electrically connected to a first input terminal of the second
logic circuit, and wherein an output terminal of the second logic circuit
is electrically connected to a gate of the second transistor.

7. The semiconductor device according to claim 6, wherein the first
register component circuit comprises a first capacitor, wherein the
second register component circuit comprises a second capacitor, wherein a
first terminal of the first capacitor is electrically connected to the
first terminal of the first register component circuit, and wherein a
first terminal of the second capacitor is electrically connected to the
first terminal of the second register component circuit.

8. The semiconductor device according to claim 6, further comprising an
inverter circuit, wherein an input terminal of the inverter circuit is
electrically connected to the fourth terminal of the first register
component circuit and the fourth terminal of the second register
component circuit, and wherein an output terminal of the inverter circuit
is electrically connected to a gate of the third transistor.

9. The semiconductor device according to claim 6, wherein the first logic
circuit is a NOR circuit, wherein the second logic circuit is a NOR
circuit, wherein a fifth terminal of the first register component circuit
is electrically connected to a second input terminal of the first logic
circuit, and wherein a fifth terminal of the second register component
circuit is electrically connected to a second input terminal of the
second logic circuit.

10. The semiconductor device according to claim 6, wherein the first
transistor comprises an oxide semiconductor layer comprising a channel
formation region, wherein the second transistor comprises an oxide
semiconductor layer comprising a channel formation region, and wherein
the third transistor comprises an oxide semiconductor layer comprising a
channel formation region.

11. A method for driving the semiconductor device according to claim 6,
the method comprising the steps of: supplying a first voltage to the gate
of the first transistor and a gate of the third transistor in a first
period; supplying a second voltage to the gate of the second transistor
in the first period; supplying a third voltage to a second terminal of
the third transistor in the first period; holding a voltage of the gate
of the first transistor to the third voltage after the first period;
holding a voltage of the gate of the second transistor to the third
voltage after the first period; supplying the first voltage to the gate
of the second transistor and the gate of the third transistor in a second
period; supplying the second voltage to the gate of the first transistor
in the second period; supplying the third voltage to the second terminal
of the third transistor in the second period; supplying a fourth voltage
to the second terminal of the second register component circuit in the
second period; holding the voltage of the gate of the first transistor to
the third voltage after the second period; and holding the voltage of the
gate of the second transistor to the fourth voltage after the second
period.

12. A semiconductor device comprising: a register circuit comprising: a
first register component circuit comprising: a first buffer circuit; a
first logic circuit; and a first transistor; a second register component
circuit comprising: a second buffer circuit; a second logic circuit; and
a second transistor; a third transistor; a fourth transistor; and a fifth
transistor, wherein a first terminal of the first register component
circuit is electrically connected to an input terminal of the first
buffer circuit, a first terminal of the first transistor, and a first
terminal of the third transistor, wherein a second terminal of the first
register component circuit is electrically connected to a second terminal
of the first transistor, wherein a third terminal of the first register
component circuit is electrically connected to an output terminal of the
first buffer circuit, wherein a fourth terminal of the first register
component circuit is electrically connected to a first input terminal of
the first logic circuit, wherein an output terminal of the first logic
circuit is electrically connected to a gate of the first transistor,
wherein a first terminal of the second register component circuit is
electrically connected to an input terminal of the second buffer circuit,
a first terminal of the second transistor, and the second terminal of the
first register component circuit, wherein a second terminal of the second
register component circuit is electrically connected to a second terminal
of the second transistor, wherein a third terminal of the second register
component circuit is electrically connected to an output terminal of the
second buffer circuit, wherein a fourth terminal of the second register
component circuit is electrically connected to a first input terminal of
the second logic circuit, wherein an output terminal of the second logic
circuit is electrically connected to a gate of the second transistor,
wherein a first terminal of the fourth transistor is electrically
connected to the first terminal of the first register component circuit,
wherein a second terminal of the fourth transistor is electrically
connected to a power source line, wherein a gate of the fourth transistor
is electrically connected to a reset line, wherein a first terminal of
the fifth transistor is electrically connected to the first terminal of
the second register component circuit, wherein a second terminal of the
fifth transistor is electrically connected to the power source line, and
wherein a gate of the fifth transistor is electrically connected to a
reset line.

13. The semiconductor device according to claim 12, wherein the first
register component circuit comprises a first capacitor, wherein the
second register component circuit comprises a second capacitor, wherein a
first terminal of the first capacitor is electrically connected to the
first terminal of the first register component circuit, and wherein a
first terminal of the second capacitor is electrically connected to the
first terminal of the second register component circuit.

14. The semiconductor device according to claim 12, further comprising an
inverter circuit, wherein an input terminal of the inverter circuit is
electrically connected to the fourth terminal of the first register
component circuit and the fourth terminal of the second register
component circuit, and wherein an output terminal of the inverter circuit
is electrically connected to a gate of the third transistor.

15. The semiconductor device according to claim 12, wherein the first
logic circuit is a NOR circuit, wherein the second logic circuit is a NOR
circuit, wherein a fifth terminal of the first register component circuit
is electrically connected to a second input terminal of the first logic
circuit, and wherein a fifth terminal of the second register component
circuit is electrically connected to a second input terminal of the
second logic circuit.

17. A method for driving the semiconductor device according to claim 12,
the method comprising the steps of: supplying a first voltage to the gate
of the first transistor and a gate of the third transistor in a first
period; supplying a second voltage to the gate of the second transistor
in the first period; supplying a third voltage to a second terminal of
the third transistor in the first period; holding a voltage of the gate
of the first transistor to the third voltage after the first period;
holding a voltage of the gate of the second transistor to the third
voltage after the first period; supplying the first voltage to the gate
of the second transistor and the gate of the third transistor in a second
period; supplying the second voltage to the gate of the first transistor
in the second period; supplying the third voltage to the second terminal
of the third transistor in the second period; supplying a fourth voltage
to the second terminal of the second register component circuit in the
second period; holding the voltage of the gate of the first transistor to
the third voltage after the second period; and holding the voltage of the
gate of the second transistor to the fourth voltage after the second
period.

Description:

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a semiconductor device. In this
specification, a semiconductor device refers to a semiconductor element
itself or a device including a semiconductor element. As an example of
such a semiconductor element, for example, a thin film transistor can be
given. Therefore, the semiconductor device includes a liquid crystal
display device, a memory device, and the like.

[0003] 2. Description of the Related Art

[0004] In recent years, metal oxides having semiconductor characteristics
(hereinafter referred to as oxide semiconductors) have attracted
attention. Oxide semiconductors may be applied to transistors (see Patent
Documents 1 and 2).

[0007] In a display device, a memory device, and the like, semiconductor
elements are arranged in a matrix. The semiconductor elements arranged in
a matrix are controlled by a peripheral driver circuit. One example of
circuits included in the peripheral driver circuit is a register circuit.

[0008] A register circuit stores data. In the case where data is stored at
a node or the like, the data stored is lost when the power is turned off.
Thus, there has been a problem in that the power cannot be turned off
even when the register circuit is idle, which prevents a reduction in
power consumption of the register circuit.

[0009] Therefore, in the case where the power of the register circuit is
turned off depending on the operation, it is necessary to write the data
to a nonvolatile memory element before turning off the power (a save
operation) and to read the data from a nonvolatile memory element shortly
after turning on the power (a return operation).

[0010] Thus, the register circuit requiring the save operation and the
return operation additionally requires a circuit for controlling the save
operation and the return operation, and also a nonvolatile memory element
used for the save operation and the return operation. Therefore, there
has been a problem in that the save operation and the return operation of
the register circuit prevent reductions in size and power consumption of
a semiconductor device.

[0011] It is an object of one embodiment of the present invention to
provide a register circuit which is capable of holding data even after
being powered off and which does not require a save operation and a
return operation.

[0012] One embodiment of the present invention is a semiconductor device
which includes a register circuit including first to n-th (n: a natural
number) register component circuits and a first transistor with small
off-state current. Each of the register component circuits includes a
first terminal, a second terminal, a NOR circuit, a second transistor
with small off-state current, and a buffer circuit. The NOR circuit
includes a first NOR input terminal, a second NOR input terminal, and a
NOR output terminal Through the first NOR input terminal, the same signal
is input to each of the register component circuits. The NOR output
terminal is electrically connected to a gate of the second transistor
with small off-state current. One of a source and a drain of the second
transistor with small off-state current is electrically connected to an
input terminal of the buffer circuit and the first terminal. The other of
the source and the drain of the second transistor with small off-state
current is electrically connected to the second terminal. An inverted
signal of the signal for the first NOR input terminal is input to the
gate of the first transistor with small off-state current. A first
terminal of the first register component circuit is electrically
connected to one of a source and a drain of the first transistor with
small off-state current. A second terminal of the first register
component circuit is electrically connected to a first terminal of a
second register component circuit. A first terminal of a k-th (k: a
natural number, k<n) register component circuit is electrically
connected to a second terminal of a (k-1)-th register component circuit.
A second terminal of the k-th (k: a natural number, k<n) register
component circuit is electrically connected to a first terminal of a
(k+1)-th register component circuit. A data signal is input to the other
of the source and the drain of the first transistor with small off-state
current.

[0013] One embodiment of the present invention is a semiconductor device
which includes a register circuit including first to n-th (n: a natural
number) register component circuits and a first transistor with small
off-state current. Each of the register component circuits includes a
first terminal, a second terminal, a NOR circuit, a second transistor
with small off-state current, and a buffer circuit. The NOR circuit
includes a first NOR input terminal, a second NOR input terminal, and a
NOR output terminal. Through the first NOR input terminal, the same
signal is input to each of the register component circuits. The NOR
output terminal is electrically connected to a gate of the second
transistor with small off-state current. One of a source and a drain of
the second transistor with small off-state current is electrically
connected to an input terminal of the buffer circuit and the first
terminal. The other of the source and the drain of the second transistor
with small off-state current is electrically connected to the second
terminal. An inverted signal of the signal for the first NOR input
terminal is input to the gate of the first transistor with small
off-state current. A first terminal of the first register component
circuit is electrically connected to one of a source and a drain of the
first transistor with small off-state current. A second terminal of the
first register component circuit is electrically connected to a first
terminal of a second register component circuit. A first terminal of a
k-th (k: a natural number, k<n) register component circuit is
electrically connected to a second terminal of a (k-1)-th register
component circuit. A second terminal of the k-th (k: a natural number,
k<n) register component circuit is electrically connected to a first
terminal of a (k+1)-th register component circuit. A first terminal of
the n-th register component circuit is electrically connected to a second
terminal of an (n-1)-th register component circuit. A first data signal
is input to a second terminal of the n-th register component circuit. A
second data signal is input to the other of the source and the drain of
the first transistor with small off-state current.

[0014] In each of the above configurations, it is preferable that a data
holding portion be formed between the one of the source and the drain of
the first transistor with small off-state current and the one of the
source and the drain of the second transistor with small off-state
current.

[0015] In each of the above configurations, it is preferable that the data
holding portion be electrically connected to one of a source and a drain
of a third transistor with small off-state current, the other of the
source and the drain of the third transistor with small off-state current
be electrically connected to a fixed potential power supply line, and a
reset signal be input to a gate of the third transistor with small
off-state current.

[0016] According to one embodiment of the present invention, data can be
held even after the register circuit is powered off, and a save operation
and a return operation can be eliminated.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017]FIG. 1 illustrates a register component circuit included in a
semiconductor device according to one embodiment of the present
invention.

[0018]FIG. 2 illustrates a register circuit included in a semiconductor
device according to one embodiment of the present invention.

[0019]FIG. 3 illustrates an operation of the register circuit in FIG. 2.

[0020]FIG. 4 illustrates an operation of the register circuit in FIG. 2.

[0021]FIG. 5 illustrates an operation of the register circuit in FIG. 2.

[0022]FIG. 6 illustrates a modified example of a register circuit
included in a semiconductor device according to one embodiment of the
present invention.

[0023]FIG. 7 illustrates a modified example of a register component
circuit included in a semiconductor device according to one embodiment of
the present invention.

[0024]FIG. 8 is a schematic cross-sectional view of a transistor which
can be applied to one embodiment of the present invention.

[0025] FIGS. 9A to 9D illustrate a method for manufacturing the transistor
illustrated in FIG. 8.

[0026] FIGS. 10A to 10E illustrate structures of oxide semiconductors
which can be applied to a transistor.

[0027] FIGS. 11A to 11C illustrate a structure of an oxide semiconductor
which can be applied to a transistor.

[0028] FIGS. 12A to 12C illustrate a structure of an oxide semiconductor
which can be applied to a transistor.

[0040]FIG. 24 shows a relation between off-state current of a transistor
and substrate temperature in measurement.

DETAILED DESCRIPTION OF THE INVENTION

[0041] Embodiments of the present invention will be described in detail
below with reference to drawings. Note that the present invention is not
limited to the following description, and it will be easily understood by
those skilled in the art that various changes and modifications can be
made without departing from the spirit and scope of the present
invention. Therefore, the present invention should not be construed as
being limited to the description in the following embodiments.

[0042] A configuration example of a register circuit according to one
embodiment of the present invention will be described; first, a basic
circuit included in the register circuit (referred to as a register
component circuit) will be described.

[0043]FIG. 1 illustrates a register component circuit 100 included in a
register circuit according to one embodiment of the present invention and
a peripheral portion thereof. The register component circuit 100 includes
a NOR circuit 102, a buffer circuit 104, a transistor 106 with small
off-state current, and a capacitor 108. As terminals through which
signals are input to or output from the register component circuit 100,
there are a first terminal 110, a second terminal 112, a third terminal
114, a fourth terminal 116, and a fifth terminal 118.

[0044] The NOR circuit 102 is a well-known NOR circuit (also referred to
as a NOR gate), and the third terminal 114 and the fourth terminal 116
are input terminals of the NOR circuit 102. Accordingly, the NOR circuit
102 outputs an H signal (or "1") through an output terminal only when
both a signal input through the third terminal 114 and a signal input
through the fourth terminal 116 are L signals (or "0").

[0045] The buffer circuit 104 is used for data reading.

[0046] The transistor 106 with small off-state current and a transistor
120 with small off-state current may each be an n-type transistor with an
off-state current of 1×10-13 A or less assuming the channel
width is 10 mm and the gate voltage Vg is from -5 V to -20 V. The
transistor 106 and the transistor 120 may each preferably be an n-type
transistor with an off-state current per unit channel width (1 μm) of
100 zA or less, more preferably 10 zA or less, at room temperature
(25° C.).

[0047] Such a transistor with small off-state current includes a channel
formation region formed using a wide bandgap semiconductor material (2.0
eV to 3.5 eV), and can be regarded as having substantially no minority
carriers therein. Examples of semiconductor materials which can be used
for such a transistor include compound semiconductors such as silicon
carbide and gallium nitride, oxide semiconductors such as zinc oxide, and
the like, each of which has a lower intrinsic carrier density than
silicon. For example, a transistor including a channel formation region
formed using an oxide semiconductor has a low minority carrier density,
which does not allow minority carries to be easily induced. Thus, in a
transistor including a channel formation region formed using an oxide
semiconductor, tunneling current is unlikely to be generated, and
off-state current is small.

[0048] The capacitor 108 may have a dielectric layer sandwiched between
two conductive layers; for example, the capacitor 108 may have a gate
insulating layer sandwiched between a conductive layer formed using the
same layer as electrodes serving as gates of the transistor 106 with
small off-state current and the transistor 120 with small off-state
current and a conductive layer formed using the same layer as electrodes
serving as sources and drains thereof.

[0049] The first terminal 110 is an output terminal of the buffer circuit
104.

[0050] The second terminal 112 is electrically connected to one of the
source and the drain of the transistor 106 with small off-state current.

[0051] The third terminal 114 and the fourth terminal 116 are the input
terminals of the NOR circuit 102. Note that the output terminal of the
NOR circuit 102 is electrically connected to the gate of the transistor
106 with small off-state current.

[0052] The fifth terminal 118 is electrically connected to the other of
the source and the drain of the transistor 106 with small off-state
current, an input terminal of the buffer circuit 104, and one electrode
of the capacitor 108. Note that the other electrode of the capacitor 108
is electrically connected to a low-potential power supply line Vss.

[0053] Note that the fifth terminal 118 is electrically connected to one
of the source and the drain of the transistor 120 with small off-state
current. The gate of the transistor 120 with small off-state current is
electrically connected to a sixth terminal 122. The other of the source
and the drain of the transistor 120 with small off-state current is
electrically connected to a seventh terminal 124.

[0054] A data holding portion 126 is constituted by a node between the
fifth terminal 118 and the other of the source and the drain of the
transistor 106 with small off-state current. The transistor 106 with
small off-state current and the transistor 120 with small off-state
current can minimize the leakage of electric charge held by the data
holding portion 126.

[0055]FIG. 2 illustrates a register circuit including a combination of a
plurality of register component circuits 100 each illustrated in FIG. 1.
Note that an n-th register component circuit is referred to as a register
component circuit 100(n). Here, n is equal to 1, 2, 3, or 4. Similarly,
terminals of the register component circuit 100(n) are referred to as a
first terminal 110(n), a second terminal 112(n), a third terminal 114(n),
a fourth terminal 116(n), and a fifth terminal 118(n).

[0056] The first terminal 110(n) is an output terminal.

[0057] A second terminal 112(1) is electrically connected to a fifth
terminal 118(2), a second terminal 112(2) is electrically connected to a
fifth terminal 118(3), and a second terminal 112(3) is electrically
connected to a fifth terminal 118(4).

[0058] A signal EN(n) is input to the third terminal 114(n).

[0059] A signal G is input to the fourth terminal 116(n). Note that the
signal G is also input to an inverter circuit 130, and an output terminal
of the inverter circuit 130 is electrically connected to the sixth
terminal 122.

[0060] A fifth terminal 118(1) is electrically connected to one of the
source and the drain of the transistor 120 with small off-state current.

[0061] The sixth terminal 122 is electrically connected to the gate of the
transistor 120 with small off-state current.

[0062] The seventh terminal 124 is electrically connected to the other of
the source and the drain of the transistor 120 with small off-state
current, and a signal D1 is input to the seventh terminal 124. A signal
D2 is input to a second terminal 112(4).

[0063] The register circuit illustrated in FIG. 2 includes a combination
of four register component circuits 100 and therefore can be used as a
4-bit register.

[0064] Next, an operation of the register circuit illustrated in FIG. 2
will be described.

[0065]FIG. 3 is a timing chart for the case where power is not turned off
and where only the signal D1 is input as a data signal and the signal D2
is not input. FIG. 3 illustrates periods t1 to t9.

[0066] Although two-level signals each having an H level and an L level
are used, driving voltages for the NOR circuit 102 and the inverter
circuit 130 and potentials of the signal G and the signal EN(n) are each
set higher than the potential of the signal D1 by the threshold voltage
of the transistor 106 with small off-state current and the transistor 120
with small off-state current.

[0067] Note that FN represents a potential of the data holding portion 126
(either at the H level or at the L level). FN(n) denotes a potential of
the data holding portion 126 of the register component circuit 100(n).

[0068] In the period t1, first, all of FN(1) to FN(4) are set to the L
levels, D1 is set to the L level, G is set to the H level, EN(1) to EN(3)
are set to the L levels, and EN(4) is set to the H level.

[0069] In the period t2, D1 is set to the H level, and G is set to the L
level; thus, all of FN(1) to FN(4) are set to the H levels.

[0070] In the period t3, EN(3) is set to the H level, and G is set to the
H level. All of FN(1) to FN(4) are kept at the H levels.

[0071] In the period t4, D1 is set to the L level, and G is set to the L
level. FN(1) to FN(3) are set to the L levels, and FN(4) is kept at the H
level.

[0072] In the period t5, D1 is kept at the L level, G is set to the H
level, and EN(2) is set to the H level. FN(1) to FN(3) are kept at the L
levels, and FN(4) is kept at the H level.

[0073] In the period t6, D1 is set to the H level, and G is set to the L
level. FN(1) and FN(2) are set to the H levels, FN(3) is kept at the L
level, and FN(4) is kept at the H level.

[0074] In the period t7, D1 is kept at the H level, G is set to the H
level, and EN(1) is set to the H level. FN(1), FN(2), and FN(4) are kept
at the H levels, and FN(3) is kept at the L level.

[0075] In the period t8, D1 is set to the L level, and G is set to the L
level. FN(1) is set to the L level, FN(2) and FN(4) are kept at the H
levels, and FN(3) is kept at the L level.

[0076] In the period t9, D1 is kept at the L level, and G is set to the H
level. FN(1) and FN(3) are kept at the L levels, and FN(2) and FN(4) are
kept at the H levels.

[0077]FIG. 4 is a timing chart for the case where power is not turned off
and where both of the signals D1 and D2 are input as data signals. FIG. 4
illustrates periods t1 to t5. In addition, two-level signals each having
an H level and an L level are used.

[0078] In the period t1, first, all of FN(1) to FN(4) are set to the L
levels, D1 and D2 are set to the L levels, G is set to the H level,
EN(1), EN(3), and EN(4) are set to the L levels, and EN(2) is set to the
H level.

[0079] In the period t2, D1 is set to the H level, D2 is kept at the L
level, and G is set to the L level; thus, FN(1) and FN(2) are set to the
H levels.

[0080] In the period t3, D1 is kept at the H level, D2 is kept at the L
level, EN(1) and EN(3) are set to the H levels, and G is set to the H
level. FN(1) and FN(2) are kept at the H levels, and FN(3) and FN(4) are
kept at the L levels.

[0081] In the period t4, D1 is set to the L level, D2 is set to the H
level, and G is set to the L level. FN(1) is set to the L level, FN(2) is
kept at the H level, FN(3) is kept at the L level, and FN(4) is set to
the H level.

[0082] In the period t5, D1 is kept at the L level, D2 is kept at the H
level, and G is set to the H level. FN(1) and FN(3) are kept at the L
levels, and FN(2) and FN(4) are kept at the H levels.

[0083] In the case where the signal D2 is also input as a data signal as
illustrated in FIG. 4, data can be written at a higher speed than in the
case where only the signal D1 is input as a data signal as illustrated in
FIG. 3.

[0084]FIG. 5 is a timing chart for the case where power is turned off and
only the signal D1 is input as a data signal. FIG. 5 illustrates periods
T1 to T3. In addition, two-level signals each having an H level and an L
level are used.

[0085] First, in the period T1, before power is turned off, the operation
is similar to the operation until the start of the period t7 in FIG. 3.

[0086] In the period T2, when power is turned off, all of EN(1) to EN(4)
are set to the L levels. In addition, D1 and G are also set to the L
levels. On the other hand, FN(1) to FN(4) are kept at the same levels as
before the power is turned off. This is because the data holding portion
126 is constituted by a node between the fifth terminal 118 and the other
of the source and the drain of the transistor 106 with small off-state
current and because the transistor 106 with small off-state current and
the transistor 120 with small off-state current can minimize the leakage
of electric charge held by the data holding portion 126.

[0087] Then, in the period T3, the power is turned on, so that D1, G, and
EN(1) to EN(4) which are at the H levels before the power is turned off
are set to the H levels. That is, in the state in the period t7 of FIG.
3, the operation is similar to the operation before turning off the
power. After that, the operation is similar to that in the periods t8 and
t9 of FIG. 3.

[0088] Therefore, as illustrated in FIG. 5, even when the power is turned
off during the operation, the operation is similar to the operation
before turning off the power, and the operation is similar to that in
FIG. 3 except for the period during which the power is turned off.

[0089] Although not illustrated here, in the case where the power is
turned off and both of the signals D1 and D2 are input as data signals,
even when the power is turned off during the operation, the operation is
similar to that before turning off the power, and the operation is
similar to that in FIG. 4 except for the period during which the power is
turned off.

[0090] Note that the register component circuit and the register circuit
according to one embodiment of the present invention are not limited to
the configurations illustrated in FIGS. 1 and 2.

[0091] For example, a configuration (FIG. 6) may be employed which
includes reset transistors each having one of a source and a drain
electrically connected to the corresponding data holding portion 126
where an FN signal is held, the other of the source and the drain
electrically connected to a low-potential power supply line Vss, and a
gate to which a reset signal R is input.

[0092]FIG. 6 illustrates reset transistors 130A to 130D. The reset
transistor 130A is electrically connected between the source or the drain
of the transistor 120 with small off-state current and the register
component circuit 100(1). The reset transistor 130B is electrically
connected between the register component circuit 100(1) and the register
component circuit 100(2). The reset transistor 130C is electrically
connected between the register component circuit 100(2) and the register
component circuit 100(3). The reset transistor 130D is electrically
connected between the register component circuit 100(3) and the register
component circuit 100(4). That is, the number of reset transistors may be
equal to the number of register component circuits.

[0093] Alternatively, a configuration (not illustrated) may be employed
which includes only one reset transistor having one of a source and a
drain electrically connected to a node electrically connected to each of
the data holding portions 126 where an FN signal is held, the other of
the source and the drain electrically connected to a low-potential power
supply line Vss, and a gate to which a reset signal R is input.

[0094] Such a configuration including a reset transistor enables the
signal in the data holding portion to be set to the L level (here, a
potential of the low-potential power supply line Vss) at the start of the
operation of the register circuit and thus can prevent malfunction of the
register circuit due to the initial potential of the data holding
portion.

[0095] Alternatively, a configuration (FIG. 7) may be employed in which
the capacitor 108 of the register component circuit 100 is not provided.
Note that the register component circuit 100 illustrated in FIG. 7 may be
combined with the register circuit illustrated in FIG. 6.

[0096] The above-described register circuit can hold data even after the
power is turned off and does not require a save operation and a return
operation.

[0097] In the above-described register circuit, oxide semiconductor
transistors are preferably used as the transistor 106 with small
off-state current and the transistor 120 with small off-state current.

[0098] Note that in the present invention, the transistors are not limited
to those having specific structures and may have various structures.
Thus, the transistors may be formed using polycrystalline silicon or may
be formed using a silicon-on-insulator (SOI) substrate.

[0099] Although the transistors in the above description are n-channel
transistors, the present invention is not limited thereto and p-channel
transistors may be used as appropriate.

[0100] Next, a transistor with small off-state current which can be used
in the present invention will be described. As an example of the
transistor with small off-state current, there is a transistor formed
using a metal oxide which has semiconductor characteristics. As an
example of a transistor other than the transistor with small off-state
current, there is a transistor formed using a semiconductor substrate.

[0101]FIG. 8 illustrates examples of schematic cross-sectional structures
of transistors which can be used in the present invention. In FIG. 8, a
transistor with small off-state current is formed over a transistor
formed using a semiconductor substrate. As the transistor formed using
the semiconductor substrate, both a p-channel transistor and an n-channel
transistor may be provided, or only either one may be provided.

[0102] The p-channel transistor and the n-channel transistor may be formed
using the semiconductor substrate by a known method. After the p-channel
transistor and the n-channel transistor are formed using the
semiconductor substrate, the transistor with small off-state current is
formed thereover. In other words, the transistor with small off-state
current is formed over a semiconductor substrate 200 provided with the
p-channel transistor and the n-channel transistor. As an example of the
transistor with small off-state current, there is a transistor having a
channel formation region in an oxide semiconductor layer.

[0103] Note that the semiconductor substrate 200 provided with the
p-channel transistor and the n-channel transistor includes
high-concentration impurity regions 201 serving as a source region and a
drain region, low-concentration impurity regions 202, a gate insulating
film 203, a gate electrode 204, and an interlayer insulating film 205
(FIG. 8).

[0104] A transistor 210 having a channel formation region in an oxide
semiconductor layer includes an oxide semiconductor layer 211 over the
semiconductor substrate 200 provided with the p-channel transistor and
the n-channel transistor, a source electrode 212a and a drain electrode
212b which are apart from each other and in contact with the oxide
semiconductor layer 211, a gate insulating film 213 over at least a
channel formation region of the oxide semiconductor layer 211, and a gate
electrode 214b over the gate insulating film 213 so as to overlap with
the oxide semiconductor layer 211 (FIG. 9D). Although not illustrated, an
electrode 214a and the gate electrode 214b are electrically connected to
each other, and the gate electrode 204 and the electrode 214a are
electrically connected to each other.

[0105] The interlayer insulating film 205 also functions as a base
insulating film for the oxide semiconductor layer 211.

[0106] The interlayer insulating film 205 contains oxygen at least on its
surface and may be formed using an insulating oxide from which part of
oxygen is released by heat treatment. As the insulating oxide from which
part of oxygen is released by heat treatment, an insulating oxide
containing a large amount of oxygen exceeding the stoichiometry is
preferably used. This is because oxygen can be supplied to an oxide
semiconductor film in contact with the interlayer insulating film 205 by
the heat treatment.

[0107] As an example of the insulating oxide containing a large amount of
oxygen exceeding the stoichiometry, silicon oxide represented by
SiOx where x>2 can be given. However, one embodiment of the
present invention is not limited thereto, and the interlayer insulating
film 205 may be formed using silicon oxide, silicon oxynitride, silicon
nitride oxide, aluminum oxynitride, gallium oxide, hafnium oxide, yttrium
oxide, or the like.

[0108] Note that the interlayer insulating film 205 may be formed by
stacking a plurality of films. The interlayer insulating film 205 may
have a stacked structure in which a silicon oxide film is formed over a
silicon nitride film, for example.

[0109] From the insulating oxide containing a large amount of oxygen
exceeding the stoichiometry, part of oxygen is easily released by heat
treatment. The amount of released oxygen (the value converted into the
number of oxygen atoms) obtained by TDS analysis when part of oxygen is
easily released by heat treatment is greater than or equal to
1.0×1018 atoms/cm3, preferably greater than or equal to
1.0×1020 atoms/cm3, more preferably greater than or equal
to 3.0×1020 atoms/cm3.

[0110] Here, a method for the TDS analysis is described. The amount of a
gas released in the TDS analysis is proportional to a time integral value
of ion intensity. Thus, the amount of a released gas can be calculated
from the time integral value of the ion intensity of an oxide and a
reference value of a standard sample. The reference value of a standard
sample refers to the ratio of the density of atoms of a predetermined
element contained in the sample to the integral value of its spectrum.

[0111] For example, the number of oxygen molecules (O2) released from
an oxide (NO2) can be found according to the formula,
NO2=NH2/SH2×SO2×α, from the ion
intensity of a silicon wafer containing hydrogen at a predetermined
density (standard sample) and the ion intensity of the oxide.

[0112] NH2 is the value obtained by conversion of the number of
hydrogen molecules (H2) released from the standard sample into
density. SH2 is the time integral value of the ion intensity of
hydrogen molecules (H2) of the standard sample. In other words, the
reference value of the standard sample is NH2/SH2. SO2 is
the time integral value of the ion intensity of oxygen molecules
(O2) of the insulating oxide. α is a coefficient which
influences the ion intensity. Refer to Japanese Published Patent
Application No. H06-275697 for details of the above equation.

[0113] Note that the amount of oxygen released in the TDS analysis (the
value converted into the number of oxygen atoms) is measured with a
thermal desorption spectroscopy apparatus produced by ESCO Ltd.,
EMD-WA1000S/W, using a silicon wafer containing hydrogen atoms at
1×1016 atoms/cm3 as the standard sample.

[0114] Note that, in the TDS analysis, oxygen is partly detected as oxygen
atoms. The ratio between oxygen molecules and oxygen atoms can be
calculated from the ionization rate of the oxygen molecules. Note that,
since the above coefficient a includes the ionization rate of oxygen
molecules, the number of the released oxygen atoms can also be calculated
through the evaluation of the number of the released oxygen molecules.

[0115] Note that NO2 is the number of released oxygen molecules
(O2). Therefore, the amount of released oxygen converted into the
number of oxygen atoms is twice the number of the released oxygen
molecules (O2).

[0116] The interlayer insulating film 205 may be formed by a sputtering
method, a CVD method, or the like and is preferably formed by a
sputtering method. In the case where a silicon oxide film is formed as
the interlayer insulating film 205, a quartz (preferably synthetic
quartz) target may be used as a target, and an argon gas may be used as a
sputtering gas. Alternatively, a silicon target may be used as a target,
and a gas containing oxygen may be used as a sputtering gas. Note that
the gas containing oxygen may be a mixed gas of an argon gas and an
oxygen gas or may be an oxygen gas alone.

[0117] Between the formation of the interlayer insulating film 205 and the
formation of an oxide semiconductor film to be the oxide semiconductor
layer 211, first heat treatment is performed. The first heat treatment is
performed to remove water and hydrogen contained in the interlayer
insulating film 205. The temperature of the first heat treatment may be
set higher than or equal to a temperature at which water and hydrogen
contained in the interlayer insulating film 205 are released (a
temperature at which the release amount peaks) and lower than a
temperature at which the semiconductor substrate 200 provided with the
p-channel transistor and the n-channel transistor alters or deforms, and
is preferably set higher than or equal to 400° C. and lower than
or equal to 750° C., and lower than a temperature of second heat
treatment performed in a later step.

[0118] Then, the second heat treatment is performed after the oxide
semiconductor film is formed. The second heat treatment is performed to
supply oxygen to the oxide semiconductor film from the interlayer
insulating film 205 which serves as a source of oxygen. Note that the
timing of the second heat treatment is not limited thereto, and the
second heat treatment may be performed after the oxide semiconductor film
is processed into the oxide semiconductor layer 211.

[0119] Note that it is preferable that the second heat treatment be
performed in a nitrogen gas atmosphere or a rare gas atmosphere including
helium, neon, argon, or the like and the atmosphere do not contain
hydrogen, water, a hydroxyl group, hydride, and the like. Alternatively,
the purity of a nitrogen gas or a rare gas such as helium, neon, or argon
introduced into a heat treatment apparatus is preferably set to 6N
(99.9999%) or more, more preferably 7N (99.99999%) or more (i.e., the
impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0120] In some cases, the oxide semiconductor film or the oxide
semiconductor layer 211 may be crystallized into a microcrystalline oxide
semiconductor layer or a polycrystalline oxide semiconductor layer,
depending on the conditions of the second heat treatment or the material
of the oxide semiconductor film or the oxide semiconductor layer 211. For
example, the oxide semiconductor film or the oxide semiconductor layer
211 may be crystallized into a microcrystalline oxide semiconductor layer
having a degree of crystallization of greater than or equal to 90%, or
greater than or equal to 80%. Further, the oxide semiconductor film or
the oxide semiconductor layer 211 may be an amorphous oxide semiconductor
layer without containing a crystalline component, depending on the
conditions of the second heat treatment or the material of the oxide
semiconductor film or the oxide semiconductor layer 211. Furthermore, the
oxide semiconductor film or the oxide semiconductor layer 211 may be an
amorphous oxide semiconductor layer containing microcrystals (having a
crystal grain size of 1 nm to 20 nm).

[0121] Note that in the second heat treatment, the interlayer insulating
film 205 serves as a source of oxygen.

[0122] Note that the interlayer insulating film 205 over which the oxide
semiconductor film is formed preferably has an average surface roughness
(Ra) of greater than or equal to 0.1 nm and less than 0.5 nm. This
is because crystal orientations can be aligned when the oxide
semiconductor film is a crystalline oxide semiconductor film.

[0123] Note that the average surface roughness (Ra) is obtained by
expanding the center line average roughness (Ra) that is defined by
JIS B 0601:2001 (ISO 4287:1997) into three dimensions so as to be able to
be applied to a measurement surface. The average surface roughness
(Ra) is expressed as an average value of the absolute values of
deviations from a reference surface to a specific surface.

[0124] Here, the center line average roughness (Ra) is shown by the
following formula (1) assuming that a portion having a measurement length
L is picked up from a roughness curve in the direction of the center line
of the roughness curve, the direction of the center line of the roughness
curve of the picked portion is represented by an X-axis, the direction of
longitudinal magnification (direction perpendicular to the X-axis) is
represented by a Y-axis, and the roughness curve is expressed as Y=F(X).

[ Formula 1 ] R a = 1 L ∫ 0
L F ( X ) X ( 1 ) ##EQU00001##

[0125] When the measurement surface which is a surface represented by
measurement data is expressed as Z=F(X,Y), the average surface roughness
(Ra) is an average value of the absolute values of deviations from
the reference surface to the specific surface and is shown by the
following formula (2).

[0126] Here, the specific surface is a surface which is an object of
roughness measurement, and is a rectangular region which is surrounded by
four points represented by the coordinates (X1, Y1), (X1,
Y2), (X2, Y1), and (X2, Y2). S0 represents
the area of the specific surface when the specific surface is flat
ideally.

[0127] In addition, the reference surface is a surface parallel to an X-Y
plane at the average height of the specific surface. That is, when the
average value of the height of the specific surface is expressed as
Z0, the height of the reference surface is also expressed as
Z0.

[0128] Chemical mechanical polishing (CMP) treatment may be performed so
that the average surface roughness of the interlayer insulating film 205
can be greater than or equal to 0.1 nm and less than 0.5 nm. The CMP
treatment may be performed before formation of the oxide semiconductor
film, preferably before the first heat treatment.

[0129] The CMP treatment may be performed at least once. When the CMP
treatment is performed plural times, it is preferable that first
polishing be performed at a high polishing rate and final polishing be
performed at a low polishing rate.

[0130] Instead of the CMP treatment, dry etching or the like may be
performed in order to planarize the interlayer insulating film 205. As
the etching gas, a chlorine-based gas such as a chlorine gas, a boron
chloride gas, a silicon chloride gas, or a carbon tetrachloride gas, a
fluorine-based gas such as a carbon tetrafluoride gas, a sulfur fluoride
gas, or a nitrogen fluoride gas, or the like may be used.

[0131] Instead of the CMP treatment, plasma treatment or the like may be
performed in order to planarize the interlayer insulating film 205. The
plasma treatment may be performed here using a rare gas. In the plasma
treatment, the surface to be processed is irradiated with ions of an
inert gas and is planarized by a sputtering effect through removal of
minute projections and depressions on the surface. Such plasma treatment
is also referred to as "reverse sputtering".

[0132] Note that any of the above treatments may be employed in order to
planarize the interlayer insulating film 205. For example, only reverse
sputtering may be performed, or dry etching may be performed after CMP
treatment is performed. Note that dry etching or reverse sputtering is
preferably used so that water and the like can be prevented from entering
the interlayer insulating film 205 over which the oxide semiconductor
film is to be formed. In particular, in the case where the planarization
treatment is performed after the first heat treatment, dry etching or
reverse sputtering is preferably used.

[0133] The oxide semiconductor layer 211 may be selectively formed in such
a manner that an oxide semiconductor film is formed, an etching mask is
formed over the oxide semiconductor film, and etching is performed.
Alternatively, an ink-jet method or the like may be used.

[0134] The oxide semiconductor film preferably contains at least indium
(In) or zinc (Zn). In particular, both In and Zn are preferably
contained. In addition, gallium (Ga) is preferably contained. When
gallium (Ga) is contained, variation in the transistor characteristics
can be reduced. Such an element capable of reducing variation in the
transistor characteristics is referred to as a stabilizer. As a
stabilizer, tin (Sn), hafnium (Hf), or aluminum (Al) can be given.

[0135] As another stabilizer, a lanthanoid such as lanthanum (La), cerium
(Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu),
gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium
(Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu) can be given. One
or a plurality of these elements can be used.

[0136] As the oxide semiconductor, for example, an indium oxide, a tin
oxide, a zinc oxide, a two-component metal oxide such as an In--Zn-based
oxide, a Sn--Zn-based oxide, an Al--Zn-based oxide, a Zn--Mg-based oxide,
a Sn--Mg-based oxide, an In--Mg-based oxide, or an In--Ga-based oxide, a
three-component metal oxide such as an In--Ga--Zn-based oxide (also
referred to as IGZO), an In--Al--Zn-based oxide, an In--Sn--Zn-based
oxide, a Sn--Ga--Zn-based oxide, an Al--Ga--Zn-based oxide, a
Sn--Al--Zn-based oxide, an In--Hf--Zn-based oxide, an In--La--Zn-based
oxide, an In--Ce--Zn-based oxide, an In--Pr--Zn-based oxide, an
In--Nd--Zn-based oxide, an In--Sm--Zn-based oxide, an In--Eu--Zn-based
oxide, an In--Gd--Zn-based oxide, an In--Tb--Zn-based oxide, an
In--Dy--Zn-based oxide, an In--Ho--Zn-based oxide, an In--Er--Zn-based
oxide, an In--Tm--Zn-based oxide, an In--Yb--Zn-based oxide, or an
In--Lu--Zn-based oxide, a four-component metal oxide such as an
In--Sn--Ga--Zn-based oxide, an In--Hf--Ga--Zn-based oxide, an
In--Al--Ga--Zn-based oxide, an In--Sn--Al--Zn-based oxide, an
In--Sn--Hf--Zn-based oxide, or an In--Hf--Al--Zn-based oxide can be used.

[0137] Note that here, for example, an "In--Ga--Zn-based oxide" means an
oxide containing In, Ga, and Zn as its main components and there is no
limitation on the ratio of In:Ga:Zn. Further, a metal element in addition
to In, Ga, and Zn may be contained.

[0138] For example, an In--Ga--Zn-based oxide with an atomic ratio of
In:Ga:Zn=1:1:1 (=1/3:1/3:1/3) or In:Ga:Zn=2:2:1 (=2/5:2/5:1/5), or an
oxide with an atomic ratio close to the above atomic ratios can be used.
Alternatively, an In--Sn--Zn-based oxide with an atomic ratio of
In:Sn:Zn=1:1:1 (=1/3:1/3:1/3), In:Sn:Zn=2:1:3 (=1/3:1/6:1/2), or
In:Sn:Zn=2:1:5 (=1/4:1/8:5/8), or an oxide with an atomic ratio close to
the above atomic ratios may be used.

[0139] However, the oxide semiconductor film which can be used in one
embodiment of the present invention is not limited to those described
above, and an oxide semiconductor film having an appropriate composition
may be used depending on needed semiconductor characteristics (mobility,
threshold voltage, variation, and the like). In accordance with needed
transistor characteristics (semiconductor characteristics), the carrier
density, the impurity concentration, the defect density, the atomic ratio
between a metal element and oxygen, the interatomic distance, the
density, and the like may be appropriately adjusted.

[0140] For example, with the In--Sn--Zn-based oxide, a relatively high
mobility can be obtained. However, mobility can be increased by reducing
the defect density in the bulk also in the case of using the
In--Ga--Zn-based oxide.

[0141] The oxide semiconductor may be either single crystal or
non-single-crystal. In the case where the oxide semiconductor is
non-single-crystal, the oxide semiconductor may be either amorphous or
polycrystalline. Further, the oxide semiconductor may have a structure
including a crystalline portion in an amorphous portion. Moreover, the
oxide semiconductor may be non-amorphous.

[0142] Note that the metal oxide preferably contains oxygen in excess of
the stoichiometry. When excess oxygen is contained, generation of
carriers due to oxygen deficiency in the oxide semiconductor film to be
formed can be prevented.

[0143] Note that for example, in the case where the oxide semiconductor
film is formed using an In--Zn-based metal oxide, a target has a
composition ratio where In/Zn is 1 to 100, preferably 1 to 20, more
preferably 1 to 10 in atomic ratio. When the atomic ratio of Zn is in the
above preferred range, field-effect mobility can be improved. Here, when
the atomic ratio of the metal oxide is In:Zn:O=X:Y:Z, it is preferable to
satisfy the relation of Z>1.5X+Y so that excess oxygen is contained.

[0144] Note that the filling factor of the target is greater than or equal
to 90% and less than or equal to 100%, preferably greater than or equal
to 95% and less than or equal to 99.9%. With a high filling factor, a
dense oxide semiconductor film can be formed.

[0145] Note that the energy gap of a metal oxide which can be applied to
the oxide semiconductor film is preferably 2 eV or more, more preferably
2.5 eV or more, still more preferably 3 eV or more. In this manner, the
off-state current of a transistor can be reduced by using a metal oxide
having a wide band gap.

[0146] Note that the oxide semiconductor film contains hydrogen. As
hydrogen, a hydrogen atom, a hydrogen molecule, water, a hydroxyl group,
or hydride may be contained in the oxide semiconductor film. It is
preferable that hydrogen contained in the oxide semiconductor film be as
little as possible.

[0147] Note that the concentrations of an alkali metal and an alkaline
earth metal in the oxide semiconductor film are preferably low, and these
concentrations are preferably 1×1018 atoms/cm3 or lower,
more preferably 2×1016 atoms/cm3 or lower. This is
because an alkali metal and an alkaline earth metal may be bonded to an
oxide semiconductor to generate carriers, in which case the off-state
current of the transistor is increased.

[0148] Note that there is no particular limitation on the formation method
and the thickness of the oxide semiconductor film, which can be
determined in consideration of the size or the like of a transistor to be
manufactured. As an example of a method for forming the oxide
semiconductor film, a sputtering method, a molecular beam epitaxy method,
a coating method, a printing method, a pulsed laser deposition method, or
the like can be given. The thickness of the oxide semiconductor film may
be greater than or equal to 3 nm and less than or equal to 50 nm. This is
because the transistor might be normally on when the oxide semiconductor
film has a large thickness of 50 nm or more. In a transistor having a
channel length of 30 μm, when the oxide semiconductor film has a
thickness of 5 nm or less, a short-channel effect can be suppressed.

[0149] Here, as a preferable example, the oxide semiconductor film is
formed by a sputtering method using an In--Ga--Zn-based metal oxide
target. A rare gas (for example, an argon gas), an oxygen gas, or a mixed
gas of a rare gas and an oxygen gas may be used as a sputtering gas.

[0150] It is preferable that a high-purity gas in which hydrogen, water, a
hydroxyl group, or hydride is reduced be used as the sputtering gas for
the formation of the oxide semiconductor film. In order to keep the high
purity of a sputtering gas, a gas attached to the inner wall of a
treatment chamber or the like is removed, and the semiconductor substrate
200 provided with the p-channel transistor and the n-channel transistor
may be subjected to heat treatment before the oxide semiconductor film is
formed. In addition, a high-purity sputtering gas may be introduced into
the treatment chamber, which may be an argon gas having a purity of 9N
(99.9999999%) or more, a dew point of -121° C. or less, a water
content of 0.1 ppb or less, and a hydrogen content of 0.5 ppb or less or
may be an oxygen gas having a purity of 8N (99.999999%) or less, a dew
point of -112° C. or less, a water content of 1 ppb or less, and a
hydrogen content of 1 ppb or less. When the oxide semiconductor film is
formed while the semiconductor substrate 200 provided with the p-channel
transistor and the n-channel transistor is being heated and kept at a
high temperature, the concentration of impurities such as water contained
in the oxide semiconductor film can be reduced. Furthermore, damage to
the oxide semiconductor film by use of a sputtering method can be
reduced. Here, the semiconductor substrate 200 provided with the
p-channel transistor and the n-channel transistor may be kept at a
temperature of higher than or equal to 100° C. and lower than or
equal to 600° C., preferably higher than or equal to 200°
C. and lower than or equal to 400° C.

[0151] In addition, oxygen may be supplied by ion implantation so that the
oxide semiconductor film contains excess oxygen.

[0152] Note that the oxide semiconductor film may have an amorphous
structure or a crystalline structure. In one embodiment in the case of
having a crystalline structure, the oxide semiconductor film is
preferably a c-axis aligned crystalline (CAAC) oxide semiconductor film.
When the oxide semiconductor film is a CAAC oxide semiconductor film, the
reliability of the transistor can be increased.

[0153] Note that the CAAC oxide semiconductor film means an oxide
semiconductor film including a crystal which has c-axis alignment and a
triangular or hexagonal atomic arrangement when seen from the direction
of an a-b plane, a surface, or an interface. In the crystal, metal atoms
are arranged in a layered manner, or metal atoms and oxygen atoms are
arranged in a layered manner along the c-axis, and the direction of the
a-axis or the b-axis is varied in the a-b plane (or the surface, or at
the interface) (the crystal rotates around the c-axis).

[0154] Note that the CAAC oxide semiconductor film means, in a broad
sense, a non-single-crystal oxide semiconductor film including a phase
which has a triangular, hexagonal, regular triangular, or regular
hexagonal atomic arrangement when seen from the direction perpendicular
to the a-b plane and in which metal atoms are arranged in a layered
manner or metal atoms and oxygen atoms are arranged in a layered manner
when seen from the direction perpendicular to the c-axis direction.

[0155] Note that the CAAC oxide semiconductor film is not single crystal,
but this does not mean that the CAAC oxide semiconductor film is composed
of only an amorphous component. Although the CAAC oxide semiconductor
film includes a crystallized portion (crystalline portion), a boundary
between one crystalline portion and another crystalline portion is not
clear in some cases.

[0156] Part of oxygen included in the CAAC oxide semiconductor film may be
substituted with nitrogen. The c-axes of individual crystalline portions
included in the CAAC oxide semiconductor film may be aligned in one
direction (e.g., a direction perpendicular to a surface of a substrate
over which the CAAC oxide semiconductor film is formed, a surface of the
CAAC oxide semiconductor film, or an interface of the CAAC oxide
semiconductor film). Alternatively, normals of the a-b planes of
individual crystalline portions included in the CAAC oxide semiconductor
film may be aligned in one direction (e.g., a direction perpendicular to
the surface of the substrate over which the CAAC oxide semiconductor film
is formed, the surface of the CAAC oxide semiconductor film, or the
interface of the CAAC oxide semiconductor film).

[0157] Note that the CAAC oxide semiconductor film may be a conductor, a
semiconductor, or an insulator depending on its composition or the like.
The CAAC oxide semiconductor film transmits or does not transmit visible
light depending on its composition or the like.

[0158] An example of such a CAAC oxide semiconductor film is a film formed
using a material which has a triangular or hexagonal atomic arrangement
when observed from the direction perpendicular to a surface of the film,
a surface of a substrate, or an interface and in which metal atoms are
arranged in a layered manner or metal atoms and oxygen atoms (or nitrogen
atoms) are arranged in a layered manner when a cross section of the film
is observed.

[0159] Examples of crystal structures included in such a CAAC oxide
semiconductor film will be described in detail with reference to FIGS.
10A to 10E, FIGS. 11A to 11C, and FIGS. 12A to 12C. In FIGS. 10A to 10E,
FIGS. 11A to 11C, and FIGS. 12A to 12C, the vertical direction basically
corresponds to the c-axis direction and a plane perpendicular to the
c-axis direction basically corresponds to the a-b plane. When the
expression "an upper half" or "a lower half' is simply used, the boundary
is the a-b plane. Furthermore, in FIGS. 10A to 10E, O surrounded by a
circle represents a tetracoordinate O atom and O surrounded by a double
circle represents a tricoordinate O atom.

[0160]FIG. 10A illustrates a structure including one hexacoordinate
indium (hereinafter referred to as In) atom and six tetracoordinate
oxygen (hereinafter referred to as tetracoordinate O) atoms proximate to
the In atom. A structure in which one In atom and oxygen atoms proximate
to the In atom are only illustrated is called a subunit here. The
structure in FIG. 10A is actually an octahedral structure, but is
illustrated as a planar structure for simplicity. Note that three
tetracoordinate O atoms exist in each of an upper half and a lower half
in FIG. 10A. In the subunit illustrated in FIG. 10A, electric charge is
0.

[0161]FIG. 10B illustrates a structure including one pentacoordinate
gallium (hereinafter referred to as Ga) atom, three tricoordinate oxygen
(hereinafter referred to as tricoordinate O) atoms proximate to the Ga
atom, and two tetracoordinate O atoms proximate to the Ga atom. All the
tricoordinate O atoms exist on the a-b plane. One tetracoordinate O atom
exists in each of an upper half and a lower half in FIG. 10B. An In atom
can also have the structure illustrated in FIG. 10B because an In atom
can have five ligands. In the subunit illustrated in FIG. 10B, electric
charge is 0.

[0162]FIG. 10c illustrates a structure including one tetracoordinate zinc
(hereinafter referred to as Zn) atom and four tetracoordinate O atoms
proximate to the Zn atom. In FIG. 10c, one tetracoordinate O atom exists
in an upper half and three tetracoordinate O atoms exist in a lower half
Alternatively, three tetracoordinate O atoms may exist in the upper half
and one tetracoordinate O atom may exist in the lower half in FIG. 10c.
In the subunit illustrated in FIG. 10c, electric charge is 0.

[0163]FIG. 10D illustrates a structure including one hexacoordinate tin
(hereinafter referred to as Sn) atom and six tetracoordinate O atoms
proximate to the Sn atom. In FIG. 10D, three tetracoordinate O atoms
exist in each of an upper half and a lower half In the subunit
illustrated in FIG. 10D, electric charge is +1.

[0164]FIG. 10E illustrates a subunit including two Zn atoms. In FIG. 10E,
one tetracoordinate O atom exists in each of an upper half and a lower
half In the subunit illustrated in FIG. 10E, electric charge is -1.

[0165] Here, a plurality of subunits forms one group, and a plurality of
groups forms one cycle which is called a unit.

[0166] Now, a rule of bonding between the subunits will be described. The
three O atoms in the upper half with respect to the hexacoordinate In
atom in FIG. 10A each have three proximate In atoms in the downward
direction, and the three O atoms in the lower half each have three
proximate In atoms in the upward direction. The one O atom in the upper
half with respect to the pentacoordinate Ga atom in FIG. 10B has one
proximate Ga atom in the downward direction, and the one O atom in the
lower half has one proximate Ga atom in the upward direction. The one O
atom in the upper half with respect to the tetracoordinate Zn atom in
FIG. 10c has one proximate Zn atom in the downward direction, and the
three O atoms in the lower half each have three proximate Zn atoms in the
upward direction. In this manner, the number of the tetracoordinate O
atoms above the metal atom is equal to the number of the metal atoms
proximate to and below each of the tetracoordinate O atoms. Similarly,
the number of the tetracoordinate O atoms below the metal atom is equal
to the number of the metal atoms proximate to and above each of the
tetracoordinate O atoms. Since the coordination number of the
tetracoordinate O atom is 4, the sum of the number of the metal atoms
proximate to and below the O atom and the number of the metal atoms
proximate to and above the O atom is 4. Accordingly, when the sum of the
number of tetracoordinate O atoms above a metal atom and the number of
tetracoordinate O atoms below another metal atom is 4, the two kinds of
subunits including the metal atoms can be bonded. For example, in the
case where the hexacoordinate metal (In or Sn) atom is bonded through
three tetracoordinate O atoms in the lower half, it is bonded to the
pentacoordinate metal (Ga or In) atom or the tetracoordinate metal (Zn)
atom.

[0167] A metal atom whose coordination number is 4,5, or 6 is bonded to
another metal atom through a tetracoordinate O atom in the c-axis
direction. In addition to the above, one group can be formed in a
different manner by combining a plurality of subunits so that the total
electric charge of the layered structure is 0.

[0168]FIG. 11A illustrates a model of one group included in a layered
structure of an In--Sn--Zn-based material. FIG. 11B illustrates a unit
including three groups. Note that FIG. 11 C illustrates an atomic
arrangement in the case where the layered structure in FIG. 11B is
observed from the c-axis direction.

[0169] In FIG. 11A, a tricoordinate O atom is omitted for simplicity, and
a tetracoordinate O atom is illustrated by a circle; the number in the
circle shows the number of tetracoordinate O atoms. For example, three
tetracoordinate O atoms existing in each of an upper half and a lower
half with respect to a Sn atom are denoted by circled 3. Similarly, in
FIG. 11A, one tetracoordinate O atom existing in each of an upper half
and a lower half with respect to an In atom is denoted by circled 1.
Similarly, FIG. 11A also illustrates a Zn atom proximate to one
tetracoordinate O atom in a lower half and three tetracoordinate O atoms
in an upper half, and a Zn atom proximate to one tetracoordinate O atom
in an upper half and three tetracoordinate O atoms in a lower half.

[0170] In the group included in the layered structure of the
In--Sn--Zn-based material in FIG. 11A, in the order starting from the
top, a Sn atom proximate to three tetracoordinate O atoms in each of an
upper half and a lower half is bonded to an In atom proximate to one
tetracoordinate O atom in each of an upper half and a lower half, the In
atom is bonded to a Zn atom proximate to three tetracoordinate O atoms in
an upper half, the Zn atom is bonded to an In atom proximate to three
tetracoordinate O atoms in each of an upper half and a lower half through
one tetracoordinate O atom in a lower half with respect to the Zn atom,
the In atom is bonded to a subunit that includes two Zn atoms and is
proximate to one tetracoordinate O atom in an upper half, and the subunit
is bonded to a Sn atom proximate to three tetracoordinate O atoms in each
of an upper half and a lower half through one tetracoordinate O atom in a
lower half with respect to the subunit. A plurality of such groups is
bonded to form one unit that corresponds to one cycle.

[0171] Here, electric charge for one bond of a tricoordinate O atom and
electric charge for one bond of a tetracoordinate O atom can be assumed
to be -0.667 and -0.5, respectively. For example, electric charge of a
(hexacoordinate or pentacoordinate) In atom, electric charge of a
(tetracoordinate) Zn atom, and electric charge of a (pentacoordinate or
hexacoordinate) Sn atom are +3, +2, and +4, respectively. Thus, electric
charge of a subunit including a Sn atom is +1. Accordingly, electric
charge of -1, which cancels +1, is needed to form a layered structure
including a Sn atom. As a structure having electric charge of -1, the
subunit including two Zn atoms as illustrated in FIG. 10E can be given.
For example, with one subunit including two Zn atoms, electric charge of
one subunit including a Sn atom can be cancelled, so that the total
electric charge of the layered structure can be 0.

[0172] An In atom can have either five ligands or six ligands.
Specifically, using the unit illustrated in FIG. 11B, In--Sn--Zn-based
crystal (In2SnZn3O.sub.8) can be obtained. Note that a layered
structure of the obtained In--Sn--Zn-based crystal can be expressed by a
composition formula, In2SnZn2O7(ZnO)m (m is 0 or a
natural number).

[0173] The above-described rule also applies to other metal oxides. As an
example, FIG. 12A illustrates a model of a group included in a layered
structure of In--Ga--Zn-based crystal.

[0174] In the group included in the layered structure of the
In--Ga--Zn-based crystal in FIG. 12A, in the order starting from the top,
an In atom proximate to three tetracoordinate O atoms in each of an upper
half and a lower half is bonded to a Zn atom proximate to one
tetracoordinate O atom in an upper half, the Zn atom is bonded to a Ga
atom proximate to one tetracoordinate O atom in each of an upper half and
a lower half through three tetracoordinate O atoms in a lower half with
respect to the Zn atom, and the Ga atom is bonded to an In atom proximate
to three tetracoordinate O atoms in each of an upper half and a lower
half through one tetracoordinate O atom in a lower half with respect to
the Ga atom. A plurality of such groups is bonded to form a unit that
corresponds to one cycle.

[0175]FIG. 12B illustrates a unit including three groups. Note that FIG.
12C illustrates an arrangement in the case where the layered structure in
FIG. 12B is observed from the c-axis direction.

[0176] Here, since electric charge of a (hexacoordinate or
pentacoordinate) In atom, electric charge of a (tetracoordinate) Zn atom,
and electric charge of a (pentacoordinate) Ga atom are +3, +2, and +3,
respectively, electric charge of a subunit including any of an In atom, a
Zn atom, and a Ga atom is 0. As a result, the total electric charge of a
group having a combination of such subunits is always 0.

[0177] Note that the group included in the layered structure of the
In--Ga--Zn-based crystal is not limited to the group illustrated in FIG.
12A.

[0178] Here, a method for forming the CAAC oxide semiconductor film is
described.

[0179] First, an oxide semiconductor film is formed by a sputtering method
or the like. Note that by forming the oxide semiconductor film while
keeping the semiconductor substrate 200 provided with the p-channel
transistor and the n-channel transistor at high temperature, the ratio of
a crystalline portion to an amorphous portion can be high. At this time,
the temperature of the semiconductor substrate 200 provided with the
p-channel transistor and the n-channel transistor may be, for example,
higher than or equal to 150° C. and lower than or equal to
450° C., preferably higher than or equal to 200° C. and
lower than or equal to 350° C.

[0180] Here, the formed oxide semiconductor film may be subjected to a
heat treatment. By the heat treatment, the ratio of a crystalline portion
to an amorphous portion can be high. In the heat treatment, the
temperature of the semiconductor substrate 200 provided with the
p-channel transistor and the n-channel transistor is, for example, higher
than or equal to 200° C. and lower than a temperature at which the
semiconductor substrate 200 provided with the p-channel transistor and
the n-channel transistor alters or deforms, preferably higher than or
equal to 250° C. and lower than or equal to 450° C. The
heat treatment may be performed for 3 minutes or longer, and preferably
24 hours or shorter. This is because the productivity is decreased when
the heat treatment is performed for a long time, although the ratio of a
crystalline portion to an amorphous portion can be high. Note that the
heat treatment may be performed in an oxidizing atmosphere or an inert
atmosphere; however, there is no limitation thereto. This heat treatment
may be performed under a reduced pressure.

[0181] The oxidizing atmosphere is an atmosphere containing an oxidizing
gas. As examples of the oxidizing gas, oxygen, ozone, nitrous oxide, and
the like can be given. It is preferable that components (e.g., water and
hydrogen) which are not preferably contained in the oxide semiconductor
film be removed from the oxidizing atmosphere as much as possible. For
example, the purity of oxygen, ozone, or nitrous oxide may be higher than
or equal to 8N (99.999999%), more preferably higher than or equal to 9N
(99.9999999%).

[0182] The oxidizing atmosphere may contain an inert gas such as a rare
gas. Note that the oxidizing atmosphere contains an oxidizing gas at a
concentration of higher than or equal to 10 ppm. An inert atmosphere
contains an inert gas (a nitrogen gas, a rare gas, or the like) and
contains a reactive gas such as an oxidizing gas at a concentration of
lower than 10 ppm.

[0183] Note that a rapid thermal annealing (RTA) apparatus may be used for
all the heat treatments. With the use of the RTA apparatus, the heat
treatment can be performed at high temperature if the heating time is
short. Thus, the oxide semiconductor film having a high ratio of a
crystalline portion to an amorphous portion can be formed, and a decrease
in productivity can be suppressed.

[0184] However, the apparatus used for all the heat treatments is not
limited to an RTA apparatus; for example, an apparatus provided with a
unit that heats an object to be processed by thermal conduction or
thermal radiation from a resistance heater or the like may be used. For
example, an electric furnace or a rapid thermal annealing (RTA) apparatus
such as a gas rapid thermal annealing (GRTA) apparatus or a lamp rapid
thermal annealing (LRTA) apparatus can be given as the heat treatment
apparatus used for all the heat treatments. Note that an LRTA apparatus
is an apparatus for heating an object to be processed by radiation of
light (an electromagnetic wave) emitted from a lamp such as a halogen
lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high
pressure sodium lamp, or a high pressure mercury lamp. A GRTA apparatus
is an apparatus for heating an object to be processed using a
high-temperature gas as a heat medium. Here, the temperature of the
high-temperature gas is preferably higher than the heat temperature of
the object to be processed.

[0185] With the use of an In--Ga--Zn-based metal oxide in which the
nitrogen concentration is higher than or equal to 1×1017
atoms/cm3 and lower than or equal to 5×1019
atoms/cm3, a metal oxide film having a c-axis-aligned hexagonal
crystal structure is formed and one or more layers containing Ga and Zn
are provided between two layers of the In--O crystal planes (crystal
planes containing indium and oxygen).

[0186] In order to form an In--Sn--Zn-based metal oxide, a target of
In:Sn:Zn=1:2:2, 2:1:3, 1:1:1, or 20:45:35 in atomic ratio may be used,
for example.

[0187] As described above, the CAAC oxide semiconductor film can be
formed.

[0188] The CAAC oxide semiconductor film has high orderliness of a bond
between metal and oxygen as compared to an oxide semiconductor film
having an amorphous structure. In other words, in the case of an oxide
semiconductor film having an amorphous structure, the number of oxygen
atoms coordinated around an adjacent metal atom varies according to the
kind of the adjacent metal. In contrast, in the case of the CAAC oxide
semiconductor film, the number of oxygen atoms coordinated around an
adjacent metal atom is substantially the same. Therefore, oxygen
deficiency is hardly observed even at a microscopic level, and charge
transfer and instability of electric conductivity due to hydrogen atoms
(including hydrogen ions), alkali metal atoms, or the like can be
suppressed.

[0189] Therefore, when a transistor has a channel formation region formed
using a CAAC oxide semiconductor film, it is possible to suppress the
shift of the threshold voltage of the transistor which occurs through
light irradiation or a bias-temperature stress (BT) test on the
transistor, so that the transistor can have stable electrical
characteristics.

[0190] Next, an etching mask is formed over the oxide semiconductor film
and etching is performed, whereby the oxide semiconductor layer 211 is
formed (FIG. 9A).

[0191] Then, the source electrode 212a and the drain electrode 212b which
are apart from each other are formed in contact with the oxide
semiconductor layer 211 (FIG. 9B).

[0192] The source electrode 212a and the drain electrode 212b may be
selectively formed in such a manner that, for example, a conductive film
(e.g., a metal film or a silicon film to which an impurity element
imparting one conductivity type is added) is formed by a sputtering
method, an etching mask is formed over the conductive film, and etching
is performed. Alternatively, an ink-jet method may be used. Note that the
conductive film to be the source electrode 212a and the drain electrode
212b may be formed by using a single layer or by stacking a plurality of
layers. For example, the conductive film may be formed to have a
three-layer structure in which an Al layer is sandwiched between Ti
layers. Note that the source electrode 212a and the drain electrode 212b
also serve as signal lines.

[0193] Next, the gate insulating film 213 is formed over at least the
channel formation region of the oxide semiconductor layer 211, and after
the gate insulating film 213 is formed, an opening is formed (FIG. 9C).
The opening is formed so as to overlap with the gate electrode 204.

[0194] As the gate insulating film 213, for example, a film of an
insulating material (for example, silicon nitride, silicon nitride oxide,
silicon oxynitride, silicon oxide, or the like) may be formed using a
sputtering method. Note that the gate insulating film 213 may be formed
by using a single layer or by stacking a plurality of layers. Here, the
gate insulating film 213 is formed to have a two-layer structure in which
a silicon oxynitride layer is stacked over a silicon nitride layer, for
example. Note that in the case where the gate insulating film 213 is
formed by a sputtering method, hydrogen and moisture can be prevented
from entering the oxide semiconductor layer 211. In addition, the gate
insulating film 213 is preferably an insulating oxide film because oxygen
can be supplied to fill oxygen vacancies.

[0196] Here, the oxide semiconductor film may be processed by dry etching.
For example, a chlorine gas or a mixed gas of a boron trichloride gas and
a chlorine gas may be used as an etching gas used for the dry etching.
However, there is no limitation thereto; wet etching may be used or
another method capable of processing the oxide semiconductor film may be
used.

[0197] The gate insulating film 213 contains oxygen at least in a portion
in contact with the oxide semiconductor layer 211 and is preferably
formed using an insulating oxide from which part of oxygen is released by
heating. In other words, the materials given as examples of the material
of the interlayer insulating film 205 are preferably used. When the
portion of the gate insulating film 213 which is in contact with the
oxide semiconductor layer 211 is formed using silicon oxide, oxygen can
be diffused into the oxide semiconductor layer 211 and a reduction in the
resistance of the transistor can be prevented.

[0198] Note that the gate insulating film 213 may be formed using a high-k
material such as hafnium silicate (HfSiOx), hafnium silicate to
which nitrogen is added (HfSixOyN.sub.z), hafnium aluminate to
which nitrogen is added (HfAlxOyN.sub.z), hafnium oxide,
yttrium oxide, or lanthanum oxide so that gate leakage current can be
reduced. Here, gate leakage current refers to leakage current which flows
between a gate electrode and a source or drain electrode. Further, a
layer formed using the high-k material and a layer formed using silicon
oxide, silicon oxynitride, silicon nitride, silicon nitride oxide,
aluminum oxide, aluminum oxynitride, or gallium oxide may be stacked.
Note that even in the case where the gate insulating film 213 has a
stacked structure, the portion in contact with the oxide semiconductor
layer 211 is preferably formed using an insulating oxide.

[0199] The gate insulating film 213 may be formed by a sputtering method.
The thickness of the gate insulating film 213 may be greater than or
equal to 1 nm and less than or equal to 300 nm, preferably greater than
or equal to 5 nm and less than or equal to 50 nm When the thickness of
the gate insulating film 213 is greater than or equal to 5 nm, gate
leakage current can be particularly reduced.

[0200] In addition, third heat treatment (preferably at a temperature of
higher than or equal to 200° C. and lower than or equal to
400° C., for example, at a temperature of higher than or equal to
250° C. and lower than or equal to 350° C.) may be
performed in an inert gas atmosphere or an oxygen gas atmosphere. By the
third heat treatment, hydrogen or moisture remaining in the oxide
semiconductor layer 211 can be diffused into the gate insulating film.
Furthermore, by the third heat treatment, oxygen can be supplied to the
oxide semiconductor layer 211 from the gate insulating film 213 which
serves as a source of oxygen.

[0201] The third heat treatment may be performed not only after the gate
insulating film 213 is formed over the oxide semiconductor layer 211 but
also after the electrode 214a and the gate electrode 214b are formed or
the conductive film to be the electrode 214a and the gate electrode 214b
is formed.

[0202] Note that the concentration of hydrogen in the oxide semiconductor
layer 211 is preferably 5.0×1019 atoms/cm3 or lower, more
preferably 5.0×1018 atoms/cm3 or lower. When the
concentration of hydrogen is low as mentioned above, the threshold
voltage of the transistor can be prevented from shifting in the negative
direction.

[0203] Note that the oxide semiconductor layer 211 preferably has a low
carrier concentration of lower than 1.0×1014/cm3. When
the carrier concentration is low, off-state current can be low.

[0204] Next, a conductive film is formed over the gate insulating film
213, an etching mask is formed over the conductive film, and etching is
performed, whereby the electrode 214a and the gate electrode 214b are
formed (FIG. 9D). Note that a conductive layer partly serving as the gate
electrode 214b serves also as at least a scan line.

[0205] The electrode 214a and the gate electrode 214b may be formed using
a material and a method which are similar to those for the source
electrode 212a and the drain electrode 212b.

[0206] Although not illustrated, it is preferable that a dopant be added
to the oxide semiconductor layer 211 using the gate electrode 214b as a
mask to form a source region and a drain region in the oxide
semiconductor layer 211.

[0207] Note that here, the dopant may be added by an ion implantation
method or an ion doping method. Alternatively, the dopant may be added by
performing plasma treatment in an atmosphere of a gas containing the
dopant. As the dopant, nitrogen, phosphorus, boron, or the like may be
added.

[0208] In the above-described manner, an oxide semiconductor transistor
can be manufactured over a transistor formed using a semiconductor
substrate as illustrated in FIG. 8.

[0209] As described above, an oxide semiconductor is preferably used for
the oxide semiconductor transistor. A transistor including an oxide
semiconductor can have high field-effect mobility.

[0210] Note that the actual field-effect mobility of the transistor
including an oxide semiconductor can be lower than its original mobility.
One of the causes for the lower mobility is a defect inside a
semiconductor or a defect at an interface between the semiconductor and
an insulating film. When a Levinson model is used, the field-effect
mobility on the assumption that no defect exists inside the semiconductor
can be calculated theoretically.

[0211] Assuming that the original mobility and the measured field-effect
mobility of a semiconductor are μ0 and μ, respectively, and a
potential barrier (such as a grain boundary) exists in the semiconductor,
the measured field-effect mobility can be expressed by the following
formula (3).

[ Formula 3 ] μ = μ 0 exp (
- E kT ) ( 3 ) ##EQU00003##

[0212] Here, E represents the height of the potential barrier, k
represents the Boltzmann constant, and T represents the absolute
temperature. When the potential barrier is assumed to be attributed to a
defect, the height of the potential barrier can be expressed by the
following formula (4) according to the Levinson model.

[0213] Here, e represents the elementary charge, N represents the average
defect density per unit area in a channel, ε represents the
dielectric constant of the semiconductor, n represents the number of
carriers per unit area in the channel, Cox represents the
capacitance per unit area, Vg represents the gate voltage, and t
represents the thickness of the channel. In the case where the thickness
of the semiconductor layer is less than or equal to 30 nm, the thickness
of the channel may be regarded as being the same as the thickness of the
semiconductor layer.

[0214] The drain current Id in a linear region can be expressed by
the following formula (5).

[0215] Here, L represents the channel length and W represents the channel
width, and L and W are each 10 μm. In addition, Vd represents the
drain voltage. When dividing both sides of the formula (5) by Vg and
then taking logarithms of both sides, the following formula (6) can be
obtained.

[0216] The right side of the formula (6) is a function of Vg. From
the formula (6), it is found that the defect density N can be obtained
from the slope of a line in a graph which is obtained by plotting actual
measured values with ln(Id/Vg) as the ordinate and 1/Vg as
the abscissa. That is, the defect density can be evaluated from the
Id-Vg characteristics of the transistor. The defect density N
of an oxide semiconductor in which the ratio of indium (In) to tin (Sn)
and zinc (Zn) is 1:1:1 is approximately 1×1012/cm2.

[0217] On the basis of the defect density obtained in this manner, or the
like, μ0 can be calculated to be 120 cm2/Vs from the formula
(3) and the formula (4). The measured mobility of an In--Sn--Zn oxide
including a defect is approximately 40 cm2/Vs. However, assuming
that no defect exists inside the semiconductor and at the interface
between the semiconductor and an insulating film, it is found from the
above results that the mobility μ0 of the oxide semiconductor is
120 cm2/Vs.

[0218] Note that even when no defect exists inside a semiconductor,
scattering at an interface between a channel and a gate insulating film
affects the transport property of the transistor. In other words, the
mobility μ1 at a position that is distance x away from the
interface between the channel and the gate insulating film can be
expressed by the following formula (7).

[ Formula 7 ] 1 μ 1 = 1 μ 0
+ D B exp ( - x l ) ( 7 ) ##EQU00007##

[0219] Here, D represents the electric field in the gate direction, and B
and l are constants. B and l can be obtained from actual measurement
results; according to the above measurement results, B is
4.75×107 cm/s and l is 10 nm (the depth to which the influence
of interface scattering reaches). When D is increased (i.e., when the
gate voltage is increased), the second term of the formula (7) is
increased and accordingly the mobility μ1 is decreased.

[0220] Calculation results of the mobility μ2 of a transistor
whose channel includes an ideal oxide semiconductor without a defect
inside the semiconductor are shown in FIG. 13. For the calculation,
device simulation software Sentaurus Device (manufactured by Synopsys,
Inc.) was used, and the bandgap, the electron affinity, the relative
permittivity, and the thickness of the oxide semiconductor were assumed
to be 2.8 eV, 4.7 eV, 15, and 15 nm, respectively. Further, the work
functions of a gate, a source, and a drain were assumed to be 5.5 eV, 4.6
eV, and 4.6 eV, respectively. The thickness of a gate insulating film was
assumed to be 100 nm, and the relative permittivity thereof was assumed
to be 4.1. The channel length and the channel width were each assumed to
be 10 μm, and the drain voltage Vd was assumed to be 0.1 V.

[0221] As shown in FIG. 13, the mobility has a peak of more than or equal
to 100 cm2/Vs at a gate voltage that is a little over 1 V and is
decreased as the gate voltage becomes higher because the influence of
interface scattering is increased. Note that in order to reduce interface
scattering, it is preferable that a surface of the semiconductor layer be
flat at the atomic level (atomic layer flatness), as described with the
above formula (1) and the like.

[0222] Calculation results of characteristics of minute transistors which
are manufactured using an oxide semiconductor having such a mobility are
shown in FIGS. 14A to 14C, FIGS. 15A to 15C, and FIGS. 16A to 16C. FIGS.
17A and 17B illustrate cross-sectional structures of the transistors used
for the calculation. The transistors illustrated in FIGS. 17A and 17B
each include a semiconductor region 303a and a semiconductor region 303c
which have n+-type conductivity in an oxide semiconductor layer. In
the calculation, the resistivity of the semiconductor region 303a and the
semiconductor region 303c was assumed to be 2×10-3 Ωcm.

[0223] The transistor illustrated in FIG. 17A is formed over a base
insulating film 301 and an embedded insulating film 302 which is embedded
in the base insulating film 301 and formed of aluminum oxide. The
transistor includes the semiconductor region 303a, the semiconductor
region 303c, an intrinsic semiconductor region 303b serving as a channel
formation region therebetween, and a gate 305. In the calculation, the
width of the gate 305 was assumed to be 33 nm.

[0224] A gate insulating film 304 is formed between the gate 305 and the
semiconductor region 303b. In addition, a sidewall insulator 306a and a
sidewall insulator 306b are formed on both side surfaces of the gate 305,
and an insulating film 307 is formed over the gate 305 so as to prevent a
short circuit between the gate 305 and another wiring. The width of the
sidewall insulator was assumed to be 5 nm. A source 308a and a drain 308b
are provided in contact with the semiconductor region 303a and the
semiconductor region 303c, respectively. Note that the channel width of
this transistor is 40 nm.

[0225] The transistor illustrated in FIG. 17B is formed over the base
insulating film 301 and the embedded insulating film 302 formed of
aluminum oxide. The transistor includes the semiconductor region 303a,
the semiconductor region 303c, the intrinsic semiconductor region 303b
serving as a channel formation region therebetween, the gate insulating
film 304, the gate 305, the sidewall insulator 306a and the sidewall
insulator 306b, the insulating film 307, the source 308a, and the drain
308b.

[0226] The transistor illustrated in FIG. 17A is different from the
transistor illustrated in FIG. 17B in the conductivity type of
semiconductor regions directly below the sidewall insulator 306a and the
sidewall insulator 306b. The semiconductor regions directly below the
sidewall insulator 306a and the sidewall insulator 306b are regions
having n+-type conductivity in the transistor illustrated in FIG.
17A, and are intrinsic semiconductor regions in the transistor
illustrated in FIG. 17B. In other words, in the semiconductor layer of
FIG. 17B, a region having a width of Loff which overlaps with
neither the semiconductor region 303a (the semiconductor region 303c) nor
the gate 305 is provided. This region is called an offset region, and the
width Loff is called an offset length. The offset length is equal to
the width of the sidewall insulator 306a (the sidewall insulator 306b).

[0227] The other parameters used in calculation are as described above.
For the calculation, device simulation software Sentaurus Device
manufactured by Synopsys, Inc. was used. FIGS. 14A to 14C show the gate
voltage (Vg: a potential difference obtained by subtracting the
potential of the source from that of the gate) dependence of the drain
current (Id, a solid line) and the mobility (μ, a dotted line) of
the transistor having the structure illustrated in FIG. 17A. The drain
current Id is obtained by calculation under the assumption that the
drain voltage (Vd: a potential difference obtained by subtracting
the potential of the source from that of the drain) is +1 V and the
mobility μ is obtained by calculation under the assumption that the
drain voltage is +0.1 V.

[0228] The thickness of the gate insulating film is 15 nm in FIG. 14A, 10
nm in FIG. 14B, and 5 nm in FIG. 14c. As the gate insulating film is
thinner, the drain current Id (off-state current) particularly in an
off state is significantly decreased. In contrast, there is no noticeable
change in the peak value of the mobility μ and the drain current
Id (on-state current) in an on state.

[0229] FIGS. 15A to 15C show the gate voltage Vg dependence of the
drain current Id (a solid line) and the mobility μ (a dotted
line) of the transistor illustrated in FIG. 17B where the offset length
Loff is 5 nm. The drain current Id is obtained by calculation
under the assumption that the drain voltage is +1 V and the mobility μ
is obtained by calculation under the assumption that the drain voltage is
+0.1 V. The thickness of the gate insulating film is 15 nm in FIG. 15A,
10 nm in FIG. 15B, and 5 nm in FIG. 15c.

[0230] FIGS. 16A to 16C show the gate voltage Vg dependence of the
drain current Id (a solid line) and the mobility μ (a dotted
line) of the transistor illustrated in FIG. 17B where the offset length
Loff is 15 nm. The drain current Id is obtained by calculation
under the assumption that the drain voltage is +1 V and the mobility μ
is obtained by calculation under the assumption that the drain voltage is
+0.1 V. The thickness of the gate insulating film is 15 nm in FIG. 16A,
10 nm in FIG. 16B, and 5 nm in FIG. 16c.

[0231] In either of the structures, as the gate insulating film is
thinner, the off-state current is significantly decreased, whereas no
noticeable change arises in the peak value of the mobility μ and the
on-state current.

[0232] Note that the peak of the mobility μ is approximately 80
cm2/Vs in FIGS. 14A to 14C, approximately 60 cm2/Vs in FIGS.
15A to 15C, and approximately 40 cm2/Vs in FIGS. 16A to 16C; thus,
the peak of the mobility μ is decreased as the offset length Loff
is increased. Further, the same applies to the off-state current. The
on-state current is also decreased as the offset length Loff is
increased; however, the decrease in the on-state current is much more
gradual than the decrease in the off-state current.

[0233] As described above, the oxide semiconductor transistor including an
oxide semiconductor can have significantly high mobility.

[0234] Note that at least one of conductive layers serving as a scan line
and a signal line is preferably formed using copper because the wiring
has low resistance.

[0235] Note that the transistor described in this embodiment as an oxide
semiconductor transistor is a mere example, and without limitation
thereto, various modes can be employed for the oxide semiconductor
transistor.

[0236] A transistor in which an oxide semiconductor containing In, Sn, and
Zn as main components is used as a channel formation region can have
favorable characteristics by depositing the oxide semiconductor while
heating a substrate or by performing heat treatment after forming an
oxide semiconductor film. Note that a main component refers to an element
included in a composition at 5 atomic % or more.

[0237] By intentionally heating the substrate after formation of the oxide
semiconductor film containing In, Sn, and Zn as main components, the
field-effect mobility of the transistor can be improved. Further, the
threshold voltage of the transistor can be positively shifted to make the
transistor normally off.

[0238] As an example, FIGS. 18A to 18C are graphs each showing
characteristics of a transistor in which an oxide semiconductor film
containing In, Sn, and Zn as main components and having a channel length
L of 3 μm and a channel width W of 10 μm, and a gate insulating
film with a thickness of 100 nm are used. Note that Vd was set to 10
V.

[0239]FIG. 18A shows characteristics of a transistor whose oxide
semiconductor film containing In, Sn, and Zn as main components was
formed by a sputtering method without heating a substrate intentionally.
The field-effect mobility of the transistor is 18.8 cm2/Vsec. On the
other hand, when the oxide semiconductor film containing In, Sn, and Zn
as main components is formed while heating the substrate intentionally,
the field-effect mobility can be improved. FIG. 18B shows characteristics
of a transistor whose oxide semiconductor film containing In, Sn, and Zn
as main components was formed while heating a substrate at 200° C.
The field-effect mobility of the transistor is 32.2 cm2/Vsec.

[0240] The field-effect mobility can be further improved by performing
heat treatment after formation of the oxide semiconductor film containing
In, Sn, and Zn as main components. FIG. 18c shows characteristics of a
transistor whose oxide semiconductor film containing In, Sn, and Zn as
main components was formed by sputtering at 200° C. and then
subjected to heat treatment at 650° C. The field-effect mobility
of the transistor is 34.5 cm2/Vsec.

[0241] The intentional heating of the substrate is expected to have an
effect of reducing moisture taken into the oxide semiconductor film
during the formation by sputtering. Further, the heat treatment after
film formation enables hydrogen, a hydroxyl group, or moisture to be
released and removed from the oxide semiconductor film. In this manner,
the field-effect mobility can be improved. Such an improvement in
field-effect mobility is presumed to be achieved not only by removal of
impurities by dehydration or dehydrogenation but also by a reduction in
interatomic distance due to an increase in density. In addition, the
oxide semiconductor can be crystallized by being highly purified by
removal of impurities from the oxide semiconductor. In the case of using
such a purified non-single-crystal oxide semiconductor, ideally, a
field-effect mobility exceeding 100 cm2/Vsec is expected to be
achieved.

[0242] The oxide semiconductor containing In, Sn, and Zn as main
components may be crystallized in the following manner: oxygen ions are
implanted into the oxide semiconductor, hydrogen, a hydroxyl group, or
moisture included in the oxide semiconductor is released by heat
treatment, and the oxide semiconductor is crystallized through the heat
treatment or by another heat treatment performed later. By such
crystallization treatment or recrystallization treatment, a
non-single-crystal oxide semiconductor having favorable crystallinity can
be obtained.

[0243] The intentional heating of the substrate during film formation
and/or the heat treatment after the film formation contributes not only
to improving field-effect mobility but also to making the transistor
normally off. In a transistor in which an oxide semiconductor film that
contains In, Sn, and Zn as main components and is formed without heating
a substrate intentionally is used as a channel formation region, the
threshold voltage tends to be shifted negatively. In contrast, when the
oxide semiconductor film formed while heating the substrate intentionally
is used, the problem of the negative shift of the threshold voltage can
be solved. That is, the threshold voltage is shifted so that the
transistor becomes normally off; this tendency can be confirmed by
comparison between FIGS. 18A and 18B.

[0244] Note that the threshold voltage can also be controlled by changing
the ratio of In to Sn and Zn; when the composition ratio of In to Sn and
Zn is 2:1:3, a normally-off transistor is expected to be formed. In
addition, an oxide semiconductor film having high crystallinity can be
obtained by setting the composition ratio of a target as follows:
In:Sn:Zn=2:1:3.

[0245] The temperature of the intentional heating of the substrate or the
temperature of the heat treatment is 150° C. or higher, preferably
200° C. or higher, further preferably 400° C. or higher.
When film formation or heat treatment is performed at high temperature,
the transistor can be normally off.

[0246] By intentionally heating the substrate during film formation and/or
by performing heat treatment after the film formation, the stability
against a gate-bias stress can be increased. For example, when a gate
bias is applied with an intensity of 2 MV/cm at 150° C. for one
hour, drift of the threshold voltage can be less than ±1.5 V,
preferably less than ±1.0 V.

[0247] A BT test was performed on the following two transistors: Sample 1
on which heat treatment was not performed after formation of an oxide
semiconductor film, and Sample 2 on which heat treatment at 650°
C. was performed after formation of an oxide semiconductor film.

[0248] First, Vg-Id characteristics of the transistors were
measured at a substrate temperature of 25° C. and Vd of 10 V.
Then, the substrate temperature was set to 150° C. and Vd was
set to 0.1 V. After that, Vg of 20 V was applied so that the
intensity of an electric field applied to gate insulating films was 2
MV/cm, and the condition was kept for one hour. Next, Vg was set to
0 V. Then, Vg-Id characteristics of the transistors were
measured at a substrate temperature of 25° C. and Vd of 10 V.
This process is called a positive BT test.

[0249] In a similar manner, first, Vg-Id characteristics of the
transistors were measured at a substrate temperature of 25° C. and
Vd of 10 V. Then, the substrate temperature was set at 150°
C. and Vd was set to 0.1 V. After that, Vg of -20 V was applied
so that the intensity of an electric field applied to the gate insulating
films was -2 MV/cm, and the condition was kept for one hour. Next,
Vg was set to 0 V. Then, Vg-Id characteristics of the
transistors were measured at a substrate temperature of 25° C. and
Vd of 10 V. This process is called a negative BT test.

[0250] FIGS. 19A and 19B show results of the positive BT test and the
negative BT test, respectively, of Sample 1. FIGS. 20A and 20B show
results of the positive BT test and the negative BT test, respectively,
of Sample 2.

[0251] The amount of shift in the threshold voltage of Sample 1 due to the
positive BT test and that due to the negative BT test were 1.80 V and
-0.42 V, respectively. The amount of shift in the threshold voltage of
Sample 2 due to the positive BT test and that due to the negative BT test
were 0.79 V and 0.76 V, respectively. It is found that, in each of Sample
1 and Sample 2, the amount of shift in the threshold voltage between
before and after the BT tests is small and the reliability is high.

[0252] The heat treatment can be performed in an oxygen atmosphere;
alternatively, the heat treatment may be performed first in an atmosphere
of nitrogen or an inert gas or under reduced pressure, and then in an
atmosphere including oxygen. Oxygen is supplied to the oxide
semiconductor after dehydration or dehydrogenation, whereby the effect of
the heat treatment can be further increased. As a method for supplying
oxygen after dehydration or dehydrogenation, a method in which oxygen
ions are accelerated by an electric field and implanted into the oxide
semiconductor film may be employed.

[0253] A defect due to oxygen vacancy is easily caused in the oxide
semiconductor or at an interface between the oxide semiconductor and a
film stacked over the oxide semiconductor; when excess oxygen is included
in the oxide semiconductor by the heat treatment, oxygen vacancy caused
constantly can be compensated for with excess oxygen. The excess oxygen
is mainly oxygen existing between lattices. When the concentration of
oxygen is set in the range of 1×1016/cm3 to
2×1020/cm3, excess oxygen can be included in the oxide
semiconductor without causing crystal distortion or the like.

[0254] When heat treatment is performed so that at least part of the oxide
semiconductor includes crystal, a more stable oxide semiconductor film
can be obtained. For example, when an oxide semiconductor film that is
formed by sputtering using a target having a composition ratio of
In:Sn:Zn=1:1:1 without heating a substrate intentionally is analyzed by
X-ray diffraction (XRD), a halo pattern is observed. The formed oxide
semiconductor film can be crystallized by being subjected to heat
treatment. The temperature of the heat treatment can be set as
appropriate; when the heat treatment is performed at 650° C., for
example, a clear diffraction peak can be observed with X-ray diffraction.

[0255] An XRD analysis of an In--Sn--Zn--O film was conducted. The XRD
analysis was conducted using an X-ray diffractometer D8 ADVANCE
manufactured by Bruker AXS, and measurement was performed by an
out-of-plane method.

[0256] Sample A and Sample B were prepared and the XRD analysis was
performed thereon. A method for forming Sample A and Sample B will be
described below.

[0257] An In--Sn--Zn--O film with a thickness of 100 nm was formed over a
quartz substrate that had been subjected to dehydrogenation treatment.

[0258] The In--Sn--Zn--O film was formed with a sputtering apparatus with
a power of 100 W (DC) in an oxygen atmosphere. An In--Sn--Zn--O target
having an atomic ratio of In:Sn:Zn=1:1:1 was used as a target. Note that
the substrate heating temperature in film formation was set at
200° C. A sample formed in this manner was used as Sample A.

[0259] Next, a sample formed by a method similar to that of Sample A was
subjected to heat treatment at 650° C. As the heat treatment, heat
treatment in a nitrogen atmosphere was performed first for one hour and
heat treatment in an oxygen atmosphere was further performed for one hour
without lowering the temperature. A sample formed in this manner was used
as Sample B.

[0260]FIG. 23 shows XRD spectra of Sample A and Sample B. No peak derived
from crystal was observed in Sample A, whereas peaks derived from crystal
were observed when 2θ was around 35 deg. and at 37 deg. to 38 deg.
in Sample B.

[0261] As described above, by intentionally heating a substrate during
deposition of an oxide semiconductor containing In, Sn, and Zn as main
components and/or by performing heat treatment after the deposition,
characteristics of a transistor can be improved.

[0262] These substrate heating and heat treatment have an effect of
preventing hydrogen and a hydroxyl group, which are unfavorable
impurities for an oxide semiconductor, from being contained in the film
or an effect of removing hydrogen and a hydroxyl group from the film.
That is, an oxide semiconductor can be purified by removing hydrogen
serving as a donor impurity from the oxide semiconductor, whereby a
normally-off transistor can be obtained. The purification of an oxide
semiconductor enables the off-state current of the transistor to be 1
aA/μm or lower. Here, the unit of the off-state current represents
current per micrometer of a channel width.

[0263]FIG. 24 shows a relation between the off-state current of a
transistor and the inverse of substrate temperature (absolute
temperature) at measurement. Here, for simplicity, the horizontal axis
represents a value (1000/T) obtained by multiplying an inverse of
substrate temperature at measurement by 1000.

[0265] Note that in order to prevent hydrogen and moisture from being
contained in the oxide semiconductor film during formation of the film,
it is preferable to increase the purity of a sputtering gas by
sufficiently suppressing leakage from the outside of a deposition chamber
and degasification through an inner wall of the deposition chamber. For
example, a gas with a dew point of -70° C. or lower is preferably
used as the sputtering gas in order to prevent moisture from being
contained in the film. In addition, it is preferable to use a target that
is purified so as not to contain impurities such as hydrogen and
moisture. Although it is possible to remove moisture from a film of an
oxide semiconductor containing In, Sn, and Zn as main components by heat
treatment, a film that does not contain moisture originally is preferably
formed because moisture is released from the oxide semiconductor
containing In, Sn, and Zn as main components at a higher temperature than
from an oxide semiconductor containing In, Ga, and Zn as main components.

[0266] The relation between the substrate temperature and electrical
characteristics of the transistor of the sample, on which heat treatment
at 650° C. was performed after formation of the oxide
semiconductor film, was evaluated.

[0267] The transistor used for the measurement has a channel length L of 3
μm, a channel width W of 10 μm, Lov of 0 μm, and dW of 0
μm. Note that Vd was set to 10 V. Note that the substrate
temperatures were -40° C., -25° C., 25° C.,
75° C., 125° C., and 150° C. Here, in the
transistor, the width of a portion where a gate electrode overlaps with
one of a pair of electrodes is referred to as Lov, and the width of
a portion of the pair of electrodes, which does not overlap with an oxide
semiconductor film, is referred to as dW.

[0268]FIG. 21 shows the Vg dependence of Id (a solid line) and
field-effect mobility (a dotted line). FIG. 22A shows a relation between
the substrate temperature and the threshold voltage, and FIG. 22B shows a
relation between the substrate temperature and the field-effect mobility.

[0269] From FIG. 22A, it is found that the threshold voltage gets lower as
the substrate temperature increases. Note that the threshold voltage is
decreased from 1.09 V to -0.23 V in the range from -40° C. to
150° C.

[0270] From FIG. 22B, it is found that the field-effect mobility gets
lower as the substrate temperature increases. Note that the field-effect
mobility is decreased from 36 cm2/Vs to 32 cm2/Vs in the range
from -40° C. to 150° C. Thus, it is found that variation in
electrical characteristics is small in the above temperature range.

[0271] In a transistor in which such an oxide semiconductor containing In,
Sn, and Zn as main components is used as a channel formation region, a
field-effect mobility of 30 cm2/Vsec or higher, preferably 40
cm2/Vsec or higher, further preferably 60 cm2/Vsec or higher
can be obtained with the off-state current maintained at 1 aA/μm or
lower, which can achieve on-state current needed for an LSI. For example,
in an FET where L/W is 33 nm/40 nm, an on-state current of 12 μA or
higher can flow when the gate voltage is 2.7 V and the drain voltage is
1.0 V. In addition, sufficient electrical characteristics can be ensured
in a temperature range needed for operation of a transistor.

[0272] This application is based on Japanese Patent Application serial no.
2011-108340 filed with Japan Patent Office on May 13, 2011, the entire
contents of which are hereby incorporated by reference.

Patent applications by Seiichi Yoneda, Atsugi JP

Patent applications by SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Patent applications in class With specific source of supply or bias voltage

Patent applications in all subclasses With specific source of supply or bias voltage