BitGen accepts text strings of 1's, 0's and hex
digits and converts them to equivalent "pwl"
voltage sources for inclusion in netlists for
circuit simulation (with SPICE or Spectre, for
example). Periodic waveforms (eg, clocks) can be
exported as "pulse" voltage sources. Parameters
such as rise time, fall time, pulse width and duty
cycle can be set on a waveform-by-waveform basis.
BitGen is written in Perl with the Perl/Tk toolkit
and has an easy-to-use graphical interface.

DiaCanvas is a generalized version of the drawing canvas used by DIA. It extends some features used by DIA and adds new ones, while preserving as many of the original features as possible. This project is no longer actively maintained. It is suggested that you try DiaCanvas2 instead.

Dinotrace is a graphical viewer for Signal Wave
files. It supports the output from Verilog, VCS,
and other simulators in addition to simple ASCII.
It includes a mode for GNU Emacs allowing signal
values to be backannotated into Verilog or C
source code.

The Eagle EDA software is composed of tightly integrated modules for PCB design, including Schematic Capture, Board Layout, and Autorouter. There is a free full-function (only board size limited) non-commercial license available for hobby and educational use as well. Windows, DOS, and of course, Linux versions are available.

Electric is a complete EDA system that can handle
many forms of circuit design, including Schematic
Capture (digital and analog), Custom IC layout,
Logic Simulation, Electro-mechanical hybrid
layout, Programmable logic (FPGAs) and much more.

HDLmaker generates hierarchical Verilog and VHDL code, PCB netlists, simulation and synthesis scripts/projects/make files, and schematics. It can translate Verilog/VHDL and HDLmaker projects into HTML, including extensive hyperlinking between the modules. It can also translate PADS PCB netlists into Verilog and VHDL and can do some simple VHDL to Verilog translations. HDLMaker synplifies the development of complex FPGAs and ASICs, and has extensive support for most Xilinx FPGAs.