We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Firefox,
Internet Explorer 11,
Safari. Thank you!

AR# 51835

Design Assistant for Vivado Synthesis - Help with SystemVerilog Processes Support

描述

This answer record describes SystemVerilog Processes supported by Vivado Synthesis, and also provides coding examples for them. These coding examples are attached to this answer record. The answer record also contains information related to known issues and good coding practices.

Note: Each coding example can be used to directly create a Vivado project. Please refer to the header in each source file for the SystemVerilog constructs demonstrated in each example.

解决方案

SystemVerilog Processes that are Supported by Vivado Synthesis

Please refer to Table 1-1 at the end of this answer record for the coding examples related to Processes.

1. Always Procedure

Verilog-2001 has an always statement which defines static processes. System Verilog adds specialized blocks for combinational, latch and sequential logic.

Vivado Synthesis supports the following four always process statements:

1.1. always This block has a syntax and usage which is same as the one defined in Verilog-2001 standard without any separate exception for Vivado Synthesis.

1.2. always_comb This block is defined only in System Verilog and is a procedure for modeling combinational logic behavior. For example: always_comb a = b & c;

The always_comb procedure provides functionality that is different than a normal always procedure: There is an inferred sensitivity list that includes the expressions. The variables written on the left-hand side of assignments shall not be written to by any other process. The procedure is automatically triggered once at time zero, after all initial and always blocks have been started, so that the outputs of the procedure are consistent with the inputs.

1.3. always_latch This block is defined only in System Verilog and is a procedure for modeling latch logic behavior. For example: always_latch if(ck) q <= d; The always_latch procedure determines its sensitivity and executes identically to the always_comb procedure.

1.4. always_ff This block is defined only in System Verilog and is a procedure which can be used to model synthesizable sequential logic behavior. For example: always_ff @(posedge clock or posedge reset) begin r1 <= reset ? 0 : r2 + 1; ... end

2. Block Statements

System Verilog Block statements provide a mechanism to group sets of statements together. A named block is used to identify the entire statement block. A named block creates a new hierarchy scope. The block can declare its own variables, and those variables are specific to that block. SystemVerilog allows a matching block name to be specified after the block's end statement preceded by a colon. This can help document the "end" associated with the corresponding begin or fork when there are nested blocks.Vivado Synthesis supports usage of Block Statements.

Note: The block name after the end statement is not mandatory but it improves code readability.Vivado Synthesis Unsupported: System Verilog Parallel Blocks (or Fork..Join blocks) are not supported in Vivado Synthesis.

This construct specifies the amount of time between the statement and its execution. This is not useful for synthesis, and Vivado synthesis ignores the time statement while still creating logic for the assignment.

This construct makes the assignment occur with a specific event. This is same as Verilog and Vivado Synthesis supports the System Verilog @* event control which eliminates simulation mismatch due to incorrect sensitivity list.

Example: Logic always@* begin

Also, the usage of logical "or" operator or a comma to separate the sensitivity list is supported in Vivado Synthesis.