Message from Accellera Systems Initiative Chair

This year, the Design Automation Conference will celebrate "50 Years of Innovation" signifying the start of the first conference to support and advance electronic design automation. The industry has come a long way since then, with the development of HDLs, RTL2GDS2, DFX and the introduction of intellectual property and other groundbreaking technical advancements to maintain high designer productivity. Along the way, dedicated members of the engineering community have come together to design, develop and formalize standards that keep technology moving forward in pace with growing development complexity and higher productivity demands.

Accellera Systems Initiative is proud to have played a key role in the standardization movement. For the past 25 years, we have developed 20 design and verification standards. Nine of these standards have been formalized within the IEEE. IEEE 1666 (SystemC language), IEEE 1685 (IP-XACT) and IEEE 1800 (SystemVerilog) are available for free download through Accellera's partnership with IEEE's GET program which grants public access to view and download select IEEE standards at no charge. We also sponsor and support the Design and Verification Conference (DVCon), which had record exhibitors and attendees this year.

Our work continues through the dedicated efforts of our 15 working groups, including the newly formed Multi-Language Working Group. As we move forward into the next 50 years, our mission remains unchanged: to collaborate with the systems, semiconductor, IP and electronic design community to deliver standards that enhance the IC and systems design and verification process and lower the cost of development. We invite you to join us and get involved!

Accellera Systems Initiative at DAC

Accellera Breakfast and Town Hall Meeting

Topic: "The Standard for Low Power Design and Verification is here! What's next?"

Monday, June 3 7:00-8:45 am Ballroom G

Register >Pre-registration is required for this free event. Seating is limited, so register early!

Moderated by: Ed Sperling, System-level Design

Panelists:

John Biggs, Consultant Engineer, ARM

Jeffrey Lee, Staff Corporate Application Engineer, Synopsys

Erich Marschner, Verification Architect, Mentor Graphics

Qi Wang, Solutions Group Director, Cadence

Sushma Honnavara-Prasad, Sr Staff Engineer, Broadcom

At our breakfast this year, we will host a town hall discussion about the emerging IEEE 1801-2013 standard. We'll have a panel of experts fresh from the IEEE 1801-2013 tutorial available to answer your questions about this pending standard. With so many of our projects needing power-aware structures, this is sure to be an exciting and informative discussion about the future of low-power design and verification.

A practical guide to packaging IP and assembling SoCs using the IP-XACT- IEEE1685 Standard. This all-day tutorial will appeal to those new to the IP-XACT- IEEE1685 standard as well providing additional insight into more advanced IP-XACT topics. The tutorial will be presented by IP-XACT experts and will begin with a brief introduction to IP-XACT, followed by a deeper dive of the core IP packaging and design/assembly metadata concepts of IP-XACT and concludes with an examination of the typical flows that can utilize this metadata. Read more on the DAC website >

Attendees will initially be through typical IP Packaging metadata e.g. components, bus definitions, bus interfaces and HW/SW interface representation. The focus will then move to integration-oriented topics and explore how hierarchical designs are represented and connected. Some advanced integration topics are introduced that explore how system-memory mapping are represented as well as how configurability is addressed. The final section then explores how this component and design metadata can be processed and presents several different example flows.

The presentation technique will focus more on visually presenting the IP-XACT concepts rather than walking through XML snippets.

Multi-Language Birds-of-a-Feather Meeting

Roughly 18 months ago, the Accellera Board tasked representatives from six electronics companies to define a standard for multi-language verification. Warren Stapleton, chair of the Multi-Language Working Group (MLWG), will review the progress of the group in an open forum. Please join us to learn more about this exciting topic.

The audience for this session is IP stakeholders — the authors, users, and EDA tool vendors. The intent is to provide enough detail for a high-level overview suitable for members of the 1800 and P1076 working groups and balance that with enough introductory material to explain the concepts to anyone interested.

IP Protection / P1735 Birds-of-a-Feather Meeting

P1735 has developed recommendations for IP Protection that soon will become a standard. This contains both recommendations and extensions to the IEEE protection pragmas in the SystemVerilog and VHDL LRMs. Its overall goal is to enable IP authors to evaluate and use IP protection to more effectively deliver their IP for use in an interoperable tool flow for a wider IP user community. This session will explain the use models for this protection and how it can work effectively in an interoperable tool flow. It will explain the extensions to support or improve key management, licensing, rights management, and visibility

Technical Tutorials from DVCon 2013 Now Available

Two tutorials from Accellera Systems Initiative Day at DVCon 2013 are now available:

In the News

Soft IP Tagging 1.0 Now Available

The Soft IP Tagging 1.0 standard provides a mechanism to track critical soft IP data throughout the entire chip design and development process such that it can be readily identified, tagged, and used again for future designs.

New Multi-language Working Group Formed

The mission of the Multi-language working group is to create a standard and functional reference for interoperability of multi-language verification environments and components. Accellera is calling for participation in the newly formed group. Accellera members and the industry at large are invited to join the standardization initiative.

Setting the Standard Blog

Smooth and efficient design and verification of electronic systems is what Accellera Systems Initiative standards are all about. This blog will provide insights into the standards we set to make your work more efficient.

Community Brings Standards to Life

We can choose to see standards as static tomes in three-ring binders or as living documents that integrate the electronics community. There is no doubt about the origin — a team of interested parties forms a working group and creates a document after months or years of work. That work represents the collective technical knowledge of the team and can serve as a blueprint for engineering work. The question is... will it ever be taken off the shelf?

Applications cause us to reach for the binder. We combine the reference examples provided with some of the standards with our own knowledge to get our implementation work started. Inevitably we reach a point where the standard specifies choice, is ambiguous, or simply represents technology that is new. That's just reality. It’s also the point when we need to reach out to the community. Has anyone implemented the standard yet? Have they done so with an application like ours? Has anyone seen this specific problem?

When we find a vibrant community that has the experts ready to answer our questions, then know that the standard is alive. We can see the bugs being reported and closed. We can see new features being suggested. And we get our answers.

A great example of this is the UVM community now hosted on the Accellera site at www.accellera.org/community/uvm. In the Accellera Promotions Committee we recognized the value of the UVM community, so we created a new community space. As we migrated the previous UVM site, UVMWorld, we maintained the forum histories that capture the community knowledge, the contributions that add value around the standard, and — perhaps the most important part — the ecosystem of companies that help engineers apply UVM. This model will be applied to SystemC, IP-XACT, and other communities in the future.

Of course, some other examples of great communities are technical events like DVCon, DAC, and user group meetings. As we look to June we have some exciting events coming. The birds-of-a-feather meetings regarding the new Accellera Multi-Language Working Group and the new IP Protection / IEEE P1735 will bring together engineers to discuss requirements and recommendations for each. We will have a town-hall style discussion about the emerging IEEE 1801 low-power update during our Accellera breakfast. And the North American SystemC User Group will also meet at DAC.

Some of you reading this have helped and continue to help develop the standards, and many more of you apply them. Regardless of where you participate, the Accellera standards are brought to life by dynamic communities ready to help you apply them in your projects. When you need us, we’ll be there!

Upcoming Events

SystemC Japan

FDL

During FDL, Martin Barnasconi, chair of the SystemC AMS working group, will present a half-day tutorial on Accellera work. Stay tuned for details.

2013 Global Sponsors

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EDITORIAL CONTACT

If you have questions or need assistance, please contact:

Jill JacobsThis email address is being protected from spambots. You need JavaScript enabled to view it.