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This issue does not exist for any VHDL designs, single controller Verilog designs, or multi-controller Verilog designs that do not target a UDIMM.

Solution

Thisoccurs becausethe parameter DQ_WIDTH is not being mapped properly to the memory model in the sim_tb_top (testbench) module.

For example, if the design is generated for 2 controllers ("Number of Controllers" option in GUI set to 2) and x16 UDIMM is selected for the second controller, port mapping to the memory model of UDIMM is as follows in the sim_tb_top module.

The above example properly port maps the DQ_WIDTH parameter when a UDIMM is selected as the second controller. This fix needs to be applied to properly map the DQ_WIDTH parameter for all x16 UDIMM controllers.