Coupled process and device simulation has been applied to investigate the physical processes which determine
the performance and scaling properties of fully depleted thin-silicon-body SOI based (FD-SOI) NMOS transistors
at gate lengths of 40 nm and below. A comparison of simulation results with measurements of electrical
characteristics of the FD-SOI NMOS transistors showed that the electrical performance of such transistors can
only be reproduced by simulation, if contact resistances, ballistic electron transport, quantum mechanical depletion
of the electrons near the gate dielectric, and mechanical stress are accounted for. The mechanical stress in
thin-silicon-body SOI transistors is simulated as a result of two silicidation processes: the source/drain contact
CoSi2 silicidation and NiSi gate silicidation. The resulting stress in the silicon channel at the end of processing
is tensile along the gate length, non-uniform and reaches maximum values in excess of 1GPa. The simulations
show that mechanical stress as well as the contact resistances increase for scaled FD-SOI transistors, therefore
a careful optimization of mechanical stress and an engineering of contact resistances are mandatory for scaled
FD-SOI devices.