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Apple IIc Plus MIG Chip

The MIG is a custom chip in the Apple IIc Plus that provides signals for accessing 3.5" disk drives and access to a 2K static RAM chip mainly used to buffer 3.5" sector data for reading and writing. The RAM is also used for the accelerator.

2018-08-01 update: Based on the work Léon and I have done, R. Belmont has implemented MIG emulation in MAME and the Apple IIc Plus emulation is now working (also see here).

Functional Description

The MIG is an interface chip that allows a 1 MHz 6502-based system to utilize Apple's “dumb” 800K 3.5" disk drives (1.44 MB drives also work, but only at 800K). It does so by providing the additional signals required to control the drives (HDSEL and 3.5DRIVE) and mediating access to a 2K SRAM that can be used to buffer data coming from the IWM at the fast (2 us) bit-cell rate that the 800K drives use.

In addition to allowing four (two each 3.5" and 5.25") “dumb” external drives to be connected, the MIG allows for one “internal” disk drive by accepting a drive enable line input on ENB2X (drive 2 in the IIc Plus) and switching it between two output pins, ENB2 and INTEN, of which the former goes to the external disk port, and the latter to the internal drive.

When the MIG is held in RESET and immediately after it is released, its state is such that the 3.5“ control signals are not enabled and the switched drive select is routed to the external disk. The end result in the IIc Plus is that when the IWM is accessed in this state, any 5.25" drives connected to the external disk port are addressed.

In the IIc Plus, the internal 3.5" drive does not need the 3.5DRIVE signal asserted in order to operate.

MIG Chip

Pins/Signals

According to the Apple IIc Technical Reference 2nd Ed., the MIG has the following signals. Note that the descriptions in the manual are not entirely accurate. For example, the description of EN2X is “input that indicates an access to address $C0nx is occuring…” In fact, this pin is connected to the drive 2 enable line of the IWM.

“Input that indicates an accesses to lower ROM bank space $C100-$DFFF is occurring”

14

RESET*

“System reset or ROM address 14”
Léon realized that this literally means that ROM address 14 is tied to the RESET line on the MIG (can be seen in the schematic). This means the MIG is held reset whenever the ROM is in the main bank, and why my prior oscilloscope testing only revealed short pulses on the MIG outputs: because I switched back to the main bank immediately in order to exit the code.

Analysis

It doesn't decode the lower 5 bits of the address bus. Thus the MIG address space must be broken down into 32-byte chunks.

RAMA5-RAMA10 combined with the lower 5 bits of the address bus are used to address the 2K SRAM.

It doesn't decode A12-A15, so on a 16-bit bus its address space must repeat every $1000 bytes without other selection logic. This logic is the ROMEN1* signal. This explains why the MIG appears at both $CE00 and $DE00.

It doesn't have pins for the data bus at all. Therefore it cannot possibly directly provide state information. However it could provide it indirectly by selectively not enabling the RAM chip select during a read or write.

Since the MIG RAM window appears at $xE00-$xFFF, the MIG considers itself selected when A11-A5 = 111xxxx, in this case it does not pass ROMEN1* to ROMEN2*. It cannot drive the data bus (no data lines) therefore it can only perform an action or assert RAMEN* to select the 2K SRAM.

It also responds in the $CC00-$CCFF range.

The MIG is held in reset when the main ROM is active.

MIG Address Space

Access/control of the MIG is via a $800-byte window starting at $C800 when the aux firmware bank is selected. The window is repeated at $D800 (I/O select is mediated by the lower half ROM select), but is not usable unless the accelerator is disabled. The lower $600 bytes of this space is shared with the ROM, and the upper $200 bytes is used for the MIG RAM window and other control functions.

MIG Control

Almost all of these addresses accessed in the ROM are via writes (except for an LDA $CCC0 in routine at $E9C5), implying that R/*W is must be low.

Address(s)

Use

$C840

routine at $EF02

$C880

routine at $EF02

$C8C0

routine at $EF02

$CC40

(probably) /IWMRES

$CC80

Assert /INTEN (drive 2 select goes to internal disk)

$CCC0

De-assert /INTEN (drive 2 select goes to external disks)

The docs say /IWMRES is latched, so would expect a $CC00/$CC40 combo, but no evidence for that.

MIG RAM / Control

These lines respond to read or write, sometimes with different behavior.

The address space for the MIG is repeated at $DE00-$DFFF but this is unusable because the Apple IIc Plus accelerator treats this space as ROM, whereas the $CE00-$CFFF window is treated as the I/O space and not cached.