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Description

When I target a Virtex-6 FPGAin the LogiCOREEthernet 1000BASE-X PCS/PMA or SGMII version 10.3 and earlier, block RAM instances do not comply with all asynchronous clocking conflict avoidance requirements as described in the Virtex-6 FPGA Memory Resources User Guide (UG363):http://www.xilinx.com/support/documentation/user_guides/ug363.pdf.

Thisproblem only existswhen the core is generated with theoptional fabricelastic buffer for SGMII mode for Virtex-6 devicesandcould result in memory collisions and erroneous behavior.

Solution

This issue has been corrected in theLogiCOREEthernet 1000BASE-X PCS/PMA or SGMII version 10.3 rev1 and later,available starting in ISE Design Suite 11.5.