One
may argue, what is the need of OVM/UVM? why OVM/UVM Exists?
Traditionally, test benches were written using VHDL or Verilog.
The concept was simple, drive inputs to DUT,
Observe Outputs, check if Outputs are as expected. However, this
model could not keep pace with the

growing
complexity of systems and growing complexity of SoC integration.

1.The
key question is: How and when would an engineer may declare that
verification is complete?

2.The
other problem is Re-use? How do we re-use testbenches?

3.And
last and certainly not the least BUGS? Is your Verification Env
good enough to catch bugs?

4.
Has all the possible combination of inputs been created by the
verification?

Tutorial Organization:
The tutorial starts with concise theory, followed by some
practicals. If you are smart enough with the
theory part, keep on clicking 'Next' at bottom, till you see
practicals.
The tutorial makes references to AHB protocol. Its important for
the reader to understand AHB protocol.
A copy of the AHB protocol spec can be found here
. It is recommended that the user makes himself familiar
with the AHB protocol, to be able to make most out of this tutorial.Tutorial Objective:
The objective of this tutorial is to let the user be able to write
his/her UVM compliant test-benches
as soon as possible. The tutorial wont deal with what Object
Oriented programming is, it wont
deal with the theory of UVM. It will just let the user understand
the structure of UVM compliant
test-benches (or test environments) and what all is needed to be
able to write compile and simulate
a UVM compliant test bench.

Introduction:

OVM/UVM is a systematic and standardized way to
write Test Bench or Test Environments for IPs, Subsystems etc.
The VLSI Industry has 2 principal languages to write advanced test
benches and test environments.
One is Specman ‘e’ and the other is SystemVerilog.
Though Specman ‘e’ was the first language invented specifically
for verification,
SystemVerilog arrived late, and it did take concepts from Specman
‘e’.

To be able to understand OVM/UVM concepts, its
important to understand the following