The Impact of Jitter on Signal to Noise Ratio (SNR) for High-Speed Analog-to-Digital Converters (ADCs)

Hello and welcome to the TI Precision Lab, discussing clock jitter considerations for high speed data converters. In this video, we'll discuss what jitter is, where it comes from, and how it impacts the noise performance of a high speed data converter. We'll also look at how to calculate jitter and steps to minimize the noise degradation.
In the sampling theory, the high speed ADC samples the input signal using an external clock signal. The clock edges have timing uncertainty, typically called jitter, which degrades the noise performance of the ADC. During the sampling process, the timing uncertainty of the sampling clock edge causes an amplitude error. For a given amount of jitter, the error gets larger as the input frequency increases. Hence, the noise, or the SNR degradation off the ADC, is sensitive to both the amount of jitter and the frequency of the input signal.
The sampling clock jitter consists of two components, the external jitter from the non-ideal clock source, and the internal ADC aperture jitter. The ADC aperture jitter originates primarily from the thermal noise of the internal clock buffers, and the aperture jitter is typically dependent on the clock signal amplitude provided to the ADC. Both the external jitter and the internal ADC aperture jitter need to be combined in order to determine the ADC SNR degradation.
There is a well known formula that system designers use to estimate the noise degradation due to clock jitter. The SNR jitter degradation can be calculated as minus 20 times log of 2 pi times the input frequency times the jitter. As mentioned earlier, this formula also confirms that the SNR degradation due to jitter depends primarily on the input frequency and the amount of the jitter.
The example figure below shows a 14-bit ADC with a thermal noise of about 73 dB. This is the pink horizontal line. Additionally, we can see four traces that showed SNR due to jitter plotted for 50, 100, 200, and 400 femtoseconds. With a sampling clock jitter of 400 femtoseconds, for example, the SNR due to jitter degrades by 20 dB when the input frequency changes from 10 to 100 megahertz.
The noise floor of the ADC is determined by three different contributors. First is the ADC quantization noise. Typically, the output resolution of the ADC is chosen such that the quantization noise does not degrade the ADC SNR significantly. In high speed ADCs, the effective number of bits, or ENOB, is typically quite a bit lower than the actual resolution of the ADC.
Second is the ADC thermal noise. The thermal noise is the inherent noise floor of the ADC.
Third is the jitter degradation. This is the noise contribution due to clock edge timing uncertainty.
Coming back to the previous example with the 14-bit ADC, our 14-bit ADC has a thermal noise of about 73 dB and a quantization noise of 86 dB. The total sampling clock jitter is 400 femtoseconds.
As the plot below shows, at input frequencies up to about 30 megahertz, the resulting SNR is limited by the thermal noise to about 73 dB. The quantization size of 86 dB is not impacting the result at all. As the input frequency increases, the jitter degradation takes over and ultimately completely limits it. If the clock is improved from 400 femtoseconds to 100 femtoseconds, then even at an input frequency of 200 megahertz, the jitter impact is not significant at all.
For more on RF sampling converters, clock jitter degradation is a very big care about.
The jitter of the external clock signal can be calculated by integrating its phase noise. For that calculation, one has to set the upper and the lower integration limits. The lower integration limit is typically set by the application. If the application uses FFT processing, for example, then the lower limit is set by the FFT bin size, as shown in the figure on the left. If it's a telecom application, the lower limit is set by the channel spacing. In GSM communications, for example, the channel spacing is 200 kilohertz. Any phase noise closer in than that is not relevant.
The right figure shows that the lower integration limit can have a significant impact on the overall jitter number, so getting the limit set correctly is important.
The upper integration limit depends on a few different variables. If a bandpass filter is used on a clock input, the upper limit is set by the filter bandwidth. If the clock input is not filtered, then theoretically, the phase noise needs to be integrated to an offset frequency of twice the clock rate. But the internal clock input has a limited bandwidth, and so integrating to twice the clock rate is a worst case scenario.
As seen in the upper picture, the foreign noise floor contributes significantly to the total clock jitter number. Here at TI, we use a bandpass filter on the ADC clock input whenever we can, to limit the noise flow degradation. As a simple experiment, I added white noise to the clock input off the ADS 5463, then I used different low pass filters to illustrate the impact to the broad noise floor of the ADC.
The results are illustrated in the bottom figure. As expected, the worst noise floor degradation is obtained when no filter is used. As I reduced the corner frequency of the low pass filter on the clock input from 300 megahertz to 1 megahertz, the resulting overall noise floor degradation got better and better.
Perhaps a better way to grasp the noise floor degradation due to clock jitter is to look at it in the frequency domain. During the sampling process, the clock signal phase noise gets added to the input signal, but the clock phase noise amplitude also gets scaled by a factor of 20 log input frequency to clock frequency.
Similar as in the time domain analysis, if the input frequency increases by a factor of 10, the clock phase noise amplitude increases by 20 dB prior to adding it to the thermal noise of the ADC. And obviously, the larger the inherent clock noise amplitude, which directly translates to higher jitter, the worse the ADC noise floor degradation.
So why is clock jitter or phase noise so critical to the receiver performance? A typical receiver use case is a blocking condition, where the receiver needs to detect a small wanted signal in the presence of a high power in-band interferer. This interferer is inside the desired passband, and therefore won't be filtered out. Since we can't overdrive or saturate the ADC input, the high power interferer limits how much front end gain can be applied to the small wanted signal. Therefore, the noise floor of the ADC itself needs to be as low as possible.
As can be seen in the picture below, the clock phase noise gets modulated onto the full power interferer, and that clock phase noise starts to directly limit how small a wanted signal can be detected. As the input frequency or the clock phase noise increases, so does the combined noise floor of the ADC. This makes it harder and harder to detect small wanted signals.
So what can be done to minimize the clock noise impact to the SNR of the ADC? There are a few different options that are available to the system designer. First, select the clock source with low enough jitter or phase noise. Second, use a bandpass filter with low insertion loss to limit the broadband noise degradation. And third, ensure that the clock amplitude at the ADC clock input pins is sufficient to not degrade the ADC aperture jitter.
And that concludes this video. Thank you for watching. 大家好，欢迎观看 TI 高精度实验室视频， 其中讨论高速 数据转换器的 时钟抖动注意事项。 在本视频中，我们 将讨论什么是抖动， 它的来源，以及它 如何影响高速数据 转换器的噪声性能。 我们还将探究 如何计算抖动， 以及执行怎样的步骤以最大 程度地减小噪声性能下降。 在采样理论中， 高速 ADC 使用 外部时钟信号对 输入信号进行采样。 时钟边沿具有通常 称为抖动的时序 不确定性，这会降低 ADC 的噪声性能。 在采样过程中， 采样时钟边沿的 时序不确定性会 导致振幅误差。 对于给定量的 抖动，误差会 随着输入频率的 增大而变大。 因此，ADC 的 噪声或 SNR 性能下降对 抖动量和输入 信号的频率 都很敏感。 采样时钟抖动 包含两个分量， 即来自非理想 时钟源的外部 抖动和内部 ADC 孔径抖动。 ADC 孔径抖动 主要源自内部 时钟缓冲器的 热噪声，而孔径 抖动通常 取决于向 ADC 提供的时钟 信号振幅。 需要将外部抖动 和内部 ADC 孔径 抖动结合在 一起才能确定 ADC SNR 降低量。 系统设计人员 使用一个著名的 公式来估算时钟 抖动导致的噪声 性能下降。 SNR 抖动下降的 计算表达式为： -20*log10[2π*输入频率*抖动] 。 正如先前 提到的，该 公式还证明 抖动导致的 SNR 下降主要 取决于输入 频率和抖动量。 下面的示例图 显示了一个 具有大约 73dB 热 噪声的 14 位 ADC。 这是粉色的 水平线。 此外，我们可以 看到四条显示抖动 导致的 SNR 降低的迹线， 抖动时长分别为 50、 100、200 和 400 飞秒。 例如，对于 400 飞秒的 采样时钟抖动， 当输入频率从 10 兆赫兹更改为 100 兆赫兹时， 抖动导致的 SNR 会降低 20dB。 ADC 的本底噪声 由三个不同的 因素决定。 第一个因素是 ADC 量化噪声。 通常，选择 ADC 的 输出分辨率时 应满足以下 条件：量化噪声 不会使 ADC SNR 显著降低。 在高速 ADC 中， 有效位数 或 ENOB 通常 远低于 实际的 ADC 分辨率。 第二个因素是 ADC 热噪声。 热噪声是 ADC 的固有 本底噪声。 第三个因素是抖动降级。 这是时钟边沿时序 不确定性导致的噪声 增加。 返回到前面有关 14 位 ADC 的示例， 我们的 14 位 ADC 具有大约 73dB 的热噪声和 86dB 的量化噪声。 总采样时钟 抖动为 400 飞秒。 如下图所示， 在高达约 30 兆赫兹的输入 频率下，产生的 SNR 受约 73dB 的 热噪声限制。 86dB 的量化 大小完全 不会影响结果。 随着输入频率 不断增加， 抖动降级将占据 主导地位，并最终 完全限制它。 如果时钟从 400 飞秒提高 至 100 飞秒，那么 即使在 200 兆 赫兹的输入 频率下，抖动 影响一点儿也不明显。 对于射频采样 转换器，时钟 抖动降级是一个非常 重要的考虑因素。 外部时钟 信号的抖动 可以通过对其相位 噪声进行积分来计算。 要进行该计算， 必须设置积分 上限和积分下限。 积分下限通常 由应用程序 设置。 例如，如果应用 使用 FFT 处理， 那么下限由 FFT bin 大小 设置，如左侧的 图所示。 如果是电信 应用，那么下限 由频道间隔设置。 例如，在 GSM 通信中，频道 间隔是 200 千赫兹。 任何比这更接近的 相位噪声都是不相关的。 右侧的图 显示了积分 下限可能对总抖动 数有显著的影响，因此 正确设置积分 下限非常重要。 积分上限 取决于一些 不同的变量。 如果在时钟输入端 使用带通滤波器， 那么上限由滤波器 带宽进行设置。 如果未对时钟输入进行 滤波，那么从理论上而言， 需要将相位 噪声积分至 时钟速率两倍的 偏移频率。 但内部时钟输入 具有有限的带宽， 因此积分至时钟 速率的两倍是 最糟糕的情形。 正如在上面的 图中看到的， 外部本底噪声会显著 增加总时钟抖动数。 在 TI，只要可以，我们 就在 ADC 时钟输入端 使用带通滤波器，以 限制本底噪声降级。 作为一个简单的 实验，我向 ADS 5463 的 时钟输入添加了白噪声， 然后我使用不同的低通 滤波器来演示对 DC 宽本底噪声的影响。 底部的图展示了 相关结果。 不出所料，在不 使用滤波器时， 发生了最糟糕的 本底噪声降级。 随着我将时钟 输入端的低通 滤波器转角频率 从 300 兆赫兹 降低至 1 兆赫兹， 产生的总本底噪声 降级变得越来越好。 或许控制时钟 抖动导致的 本底噪声 降级的更佳 方法是在 频域中查看它。 在采样过程中， 会向输入信号 添加时钟信号相位 噪声，但时钟相位噪声 振幅也会以 20*log (输入频率/时钟频率) 的 因数进行缩放。 与时域分析中的 情况类似，如果 输入频率 增加 10 倍， 那么在添加到 ADC 的热噪声 之前，时钟相位噪声 振幅会增加 20dB。 很显然，固有时钟 噪声振幅越大， 这会直接导致 更高的抖动， ADC 本底噪声 降级就越糟糕。 那么，为何时钟 抖动或相位噪声 对于接收器性能 而言如此重要？ 典型的接收器 用例是阻断情况， 其中接收器需要 在存在高功率带内 干扰信号的情况下 检测微小的目标信号。 该干扰信号位于 所需的通带内， 因此无法 将其滤除。 由于我们无法对 ADC 输入进行过驱 或使其饱和，因此 高功率干扰信号会 限制可应用至微小 目标信号的前端增益量。 因此，ADC 本身的 本底噪声需要 尽可能低。 正如可以在 下面的图中 看到的，时钟相位 噪声被调制到 全功率干扰信号上， 然后该时钟相位 噪声开始直接限制 能够检测到多小的 目标信号。 随着输入频率 或时钟相位噪声 不断增大，ADC 的组合 本底噪声也会不断增大。 这样就使检测微小的 目标信号变得越来越难。 那么，可以采取什么措施 来最大程度地减小时钟 噪声对 ADC SNR 的影响呢？ 系统设计 人员可以 在一些不同的 选项中进行选择。 首选，选择具有足够低的 抖动或相位噪声的 时钟源。 然后，使用具有 低插入损耗的 带通滤波器，从而 限制宽带噪声降级。 第三，确保 ADC 时钟 输入引脚上的时钟 振幅足够高，从而 不会降低 ADC 孔径 抖动。 本视频到此结束。 谢谢观看。

Description

July 31, 2017

This video is part of the TI Precision Labs – ADCs curriculum. This video covers what is jitter, where it comes from and how it impacts the noise performance of a high-speed data converter. We’ll also look at how to calculate it and steps to minimize noise degradation.