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INTRODUCTION Power Optimization has always been a major goal in designing digital circuits. All of the circuit determines power dissipation but only a small fraction of the gates determine circuit performance. We should use high performance devices on critical path. Circuit Design Techniques: 1) Multiple Vdd. 2) Multiple Threshold voltages. 3) Gate Resizing.

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Level Converter Low Vdd gates cannot drive High Vdd gates:  PMOS does not turn off  Results in flow of static current Insertion of Level converters required:  Similar to amplifiers in memories

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Problem with Level Converters Level converters introduce a new source of power dissipation. They take more silicon area. They add delay to the circuit. Approach: We need a strategy to limit the number of Level Converters !

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Clustered Voltage Scaling “Usami and Horowitz” proposed Clustered Voltage Scaling Structure to limit the number of Level converters. CVS results in the clustering of gates in two sets: A set of gates at high Vdd and a set of gates at low Vdd. CVS structure: Primary I/p -> High Vdd cells -> Low Vdd cells -> Level Converters -> Primary O/p. CVS Algorithm is a search algorithm which tries to substitute as many cells as possible with low Vdd cells while maintaining the required performance.

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CVS Algorithm 1. Pick a new cell C connected to a primary output. 2. Substitute it with a VDD L analogous cell. 3. Perform a new static timing analysis. 4. If the new timing worsen the original one, go back to step 1. 5. Pick a cell feeding the last substituted. 6. Verify it’s viability for substitution through a DFS. 7. If the new timing worsen the original one, go back to step 5. 8. If there are unanalyzed PO cells, go back to step 1. Reference: Monica Donno et al.

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Application of Original CVS Algorithm Reference: Monica Donno et al. This is the algorithm which was used in the CVS structure proposed by Usami and Horowitz. 2 1 3 4 5 7 6 8 10 9

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Partial DFS Algorithm Forward DFS -> Checks whether substitution is feasible for all the transitive fanouts of a node or not -> Might take a long time! Donno et al. proposed alternative implementation to improve results and/or execution time without changing the basic CVS. They Proposed “Partial DFS Algorithm”. Partial DFS Algorithm -> Stops the search whenever a node is declared unfeasible -> Skips to the following PO -> Search space is reduced by cutting substitutions which are not likely to affect the results substantially -> Saves Computation time!

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Results for two Algorithms The following result for c6288 is the biggest benchmark circuit the authors have considered. (Monica et al.) AlgorithmCircuitPower Red.CPU Time DFSC62880.35%20 Min. Partial DFS C62880.35%8 Min.

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How to Determine Vdd R Subthreshold effect makes the prediction of Vdd R imprecise. Solution : Determine Vdd R by a circuit simulator, such as HSPICE, when the acceptable value of static current is given.

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CFMV Structure A combinational circuit can be represented as a directed acyclic graph G = ( V,E ). Proper Directed Cut: [ V 1, V 2 ] is a proper directed cut of G if V 2 contains all the sinks of G, all the boundary vertices of G and all the vertices in their reachable set. C1 is a proper directed cut but not C2

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Summary According to Yeh et al., on average, 9 – 18% power reduction can be obtained using the CFMV technique. We can observe that the CPU time in this case is more than CVS. I wonder, if we can we improve the CPU time by using partial DFS algorithm here too, without substantially affecting the results. ? ? ? This is indeed a very challenging research topic !