Arup Bhattacharyya, Essex Junction US

Arup Bhattacharyya, Essex Junction, VT US

Patent application number

Description

Published

20080220577

SCALABLE HIGH DENSITY NON-VOLATILE MEMORY CELLS IN A CONTACTLESS MEMORY ARRAY - A plurality of mesas are formed in the substrate. Each pair of mesas forms a trench. A plurality of diffusion areas are formed in the substrate. A mesa diffusion area is formed in each mesa top and a trench diffusion area is formed under each trench. A vertical, non-volatile memory cell is formed on each sidewall of the trench. Each memory cell is comprised of a fixed threshold element located vertically between a pair of non-volatile gate insulator stacks. In one embodiment, each gate insulator stack is comprised of a tunnel insulator formed over the sidewall, a deep trapping layer, and a charge blocking layer. In another embodiment, an injector silicon rich nitride layer is formed between the deep trapping layer and the charge blocking layer.

09-11-2008

20080230827

SCALABLE FLASH/NV STRUCTURES AND DEVICES WITH EXTENDED ENDURANCE - Devices and methods are provided with respect to a gate stack for a nonvolatile structure. According to one aspect, a gate stack is provided. One embodiment of the gate stack includes a tunnel medium, a high K charge blocking and charge storing medium, and an injector medium. The high K charge blocking and charge storing medium is disposed on the tunnel medium. The injector medium is operably disposed with respect to the tunnel medium and the high K charge blocking and charge storing medium to provide charge transport by enhanced tunneling. According to one embodiment, the injector medium is disposed on the high K charge blocking and charge storing medium. According to one embodiment, the tunnel medium is disposed on the injector medium. Other aspects and embodiments are provided herein.

09-25-2008

20080268605

Capacitors and methods with praseodymium oxide insulators - Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. Monolayers that contain titanium or other metals are deposited onto a substrate and subsequently processed to form metal electrodes. Resulting capacitor structures includes properties such as improved dimensional control. One improved dimensional control includes thickness. Some resulting capacitor structures also include properties such as an amorphous or nanocrystalline microstructure. Selected components of capacitors formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.

10-30-2008

20080303080

BACK-SIDED TRAPPED NON-VOLATILE MEMORY DEVICE - Non-volatile memory devices and arrays are described that utilize back-side trapped floating node memory cells with band-gap engineered gate stacks with asymmetric tunnel barriers. Embodiments of the present invention allow for direct tunneling programming and efficient erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention and reduces the possibility of damage to the channel/insulator interface. The direct tunneling program and efficient erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and leakage issues and enhancing device lifespan. Memory device embodiments of the present invention are presented that are arranged in NOR or NAND memory architecture arrays. Memory cell embodiments of the present invention also allow multiple levels of bit storage in a single memory cell, and allow for programming and erase with reduced voltages.

12-11-2008

20090014780

DISCRETE TRAP NON-VOLATILE MULTI-FUNCTIONAL MEMORY DEVICE - A multiple layer tunnel insulator is fabricated between a substrate and a discrete trap layer. The properties of the multiple layers determines the volatility of the memory device. The composition of each layer and/or the quantity of layers is adjusted to fabricate either a DRAM device, a non-volatile memory device, or both simultaneously.

01-15-2009

20090027963

HIGH PERFORMANCE MULTI-LEVEL NON-VOLATILE MEMORY DEVICE - Non-volatile memory devices and arrays are described that utilize band engineered gate-stacks and multiple charge trapping layers allowing a multiple trapping site gate-insulator stack memory cell that utilizes a band engineered direct tunneling or crested barrier tunnel layer and charge blocking layer for high speed programming/erasure. Charge retention is enhanced by utilization of nano-crystals and/or bulk trapping materials in a composite non-conductive trapping layer and a high K dielectric insulating layers. The band-gap engineered gate-stack with asymmetric direct tunneling or crested barrier tunnel layers of the non-volatile memory cells of embodiments of the present invention allow for low voltage high speed tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. Memory cell embodiments of the present invention allow multiple levels of bit storage in a memory cell through multiple charge centroids and/or multiple threshold voltage levels.

01-29-2009

20090035904

METHODS OF FORMING NON-VOLATILE MEMORY HAVING TUNNEL INSULATOR OF INCREASING CONDUCTION BAND OFFSET - Methods of forming non-volatile memory cell structures are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and normal mode floating node memory cells that allow for direct tunnel programming and erase, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The low voltage direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and enhancing device lifespan. The low voltage direct tunnel program and erase capability also enables size reduction through low voltage design and further device feature scaling. Such memory cells also allow multiple bit storage. These characteristics allow such memory cells to operate within the definition of a universal memory, capable of replacing both DRAM and ROM in a system.

02-05-2009

20090067256

Thin gate stack structure for non-volatile memory cells and methods for forming the same - Embodiments are described for reducing the programming voltage of a memory cell in a memory device. The memory cell includes a channel region extending between first and second diffusion regions formed in a substrate. A tunnel dielectric material is formed over the channel region. A storage medium is formed over the tunnel dielectric material to store electrical charge. The storage medium is disposed between a first interface material and a second interface material, each interface material provides a smoother interface between the storage medium and surrounding dielectric materials. A charge blocking material is formed over the storage medium, followed by a control gate material.

03-12-2009

20090079015

Lanthanide dielectric with controlled interfaces - Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on the lanthanide dielectric film.

03-26-2009

20090090950

SEMICONDUCTOR DEVICES - Methods, devices, modules, and systems providing semiconductor devices in a stacked wafer system are described herein. One embodiment includes a first wafer for NMOS transistors in a CMOS architecture and a second wafer for PMOS transistors in the CMOS architecture, with the first wafer being bonded and electrically coupled to the second wafer to form at least one CMOS device. Another embodiment includes a number of DRAM capacitors formed on a first wafer and support circuitry associated with the DRAM capacitors formed on a second wafer, with the first wafer being bonded and electrically coupled to the second wafer to form a number of DRAM cells. Another embodiment includes a first wafer having a number of vertical transistors coupled to a data line and a second wafer having amplifier circuitry associated with the number of vertical transistors, with the first wafer being bonded and electrically coupled to the second wafer.

04-09-2009

20090097320

Memory Cells, Electronic Systems, Methods Of Forming Memory Cells, And Methods of Programming Memory Cells - Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.

EMBEDDED TRAP DIRECT TUNNEL NON-VOLATILE MEMORY - The cell comprises a substrate having a drain region and a source region. An oxynitride layer is formed over the substrate. An embedded trap layer is formed over the oxynitride layer. An injector layer is formed over the embedded trap layer. A high dielectric constant layer is formed over the injector layer. A polysilicon control gate formed over the high dielectric constant layer. The cell can be formed in a planar architecture or a two element, split channel, three-dimensional device. The planar cell is formed with the high dielectric constant layer and the control gate being formed over and substantially around three sides of the embedded trap layer. The split channel device has a source line in the substrate under each trench and a bit line on either side of the trench.

08-13-2009

20090200602

COMBINED VOLATILE AND NON-VOLATILE MEMORY DEVICE WITH GRADED COMPOSITION INSULATOR STACK - A memory device is fabricated with a graded composition tunnel insulator layer. This layer is formed over a substrate with a drain and a source region. The tunnel insulator is comprised of a graded SiC—GeC—SiC composition. A charge blocking layer is formed over the tunnel insulator. A trapping layer of nano-crystals is formed in the charge blocking layer. In one embodiment, the charge blocking layer is comprised of germanium carbide and the nano-crystals are germanium. The thickness and/or composition of the tunnel insulator determines the functionality of the memory cell such as the volatility level and speed. A gate is formed over the charge blocking layer.

08-13-2009

20090236650

TANTALUM LANTHANIDE OXYNITRIDE FILMS - Electronic apparatus and methods of forming the electronic apparatus include a tantalum lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The tantalum lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a tantalum lanthanide oxynitride film.

09-24-2009

20090256243

LOW K INTERCONNECT DIELECTRIC USING SURFACE TRANSFORMATION - Systems, devices and methods are provided to improve performance of integrated circuits by providing a low-k insulator. One aspect is an integrated circuit insulator structure. One embodiment includes a solid structure of an insulator material, and a precisely determined arrangement of at least one void formed within the solid structure which lowers an effective dielectric constant of the insulator structure. One aspect is a method of forming a low-k insulator structure. In one embodiment, an insulator material is deposited, and a predetermined arrangement of at least one hole is formed in a surface of the insulator material. The insulator material is annealed such that the low-k dielectric material undergoes a surface transformation to transform the arrangement of at least one hole into predetermined arrangement of at least one empty space below the surface of the insulator material. Other aspects are provided herein.

10-15-2009

20090294924

HAFNIUM LANTHANIDE OXYNITRIDE FILMS - Electronic apparatus and methods of forming the electronic apparatus include a hafnium lanthanide oxynitride film on a substrate for use in a variety of electronic systems. The hafnium lanthanide oxynitride film may be structured as one or more monolayers. Metal electrodes may be disposed on a dielectric containing a hafnium lanthanide oxynitride film.

12-03-2009

20090302365

Nanocrystal Based Universal Memory Cells, And Memory Cells - Some embodiments include memory cells that contain a dynamic random access memory (DRAM) element and a nonvolatile memory (NVM) element. The DRAM element contains two types of DRAM nanoparticles that differ in work function. The NVM contains two types of NVM nanoparticles that differ in trapping depth. The NVM nanoparticles may be in vertically displaced charge-trapping planes. The memory cell contains a tunnel dielectric, and one of the charge-trapping planes of the NVM may be further from the tunnel dielectric than the other. The NVM charge-trapping plane that is further from the tunnel dielectric may contain larger NVM nanoparticles than the other NVM charge-trapping plane. The DRAM element may contain a single charge-trapping plane that has both types of DRAM nanoparticles therein. The memory cells may be incorporated into electronic systems.

12-10-2009

20090316480

METHODS OF STORING MULTIPLE DATA-BITS IN A NON-VOLATILE MEMORY CELL - Methods of storing multiple data-bits in a non-volatile memory cell are carried out by trapping carriers in a composite trapping layer formed over a tunnel insulator layer. The composite trapping layer contains a plurality of band engineered sub-layers providing a plurality of charge trapping layers.

12-24-2009

20100038701

INTEGRATED TWO DEVICE NON-VOLATILE MEMORY - The non-volatile memory cell is comprised of the series integration of a fixed threshold element and a bistable element. The fixed threshold element is formed over a substrate with a gate insulator layer and an access gate having a nitride layer. The bistable element is formed adjacent to the fixed threshold element by a tunnel insulator over the substrate, a charge trapping layer over the tunnel insulator, a charge blocking layer over the trapping layer, and a control gate, having a nitride layer, over the charge blocking layer. In one embodiment, the gate insulator, tunnel insulator and charge trapping layers are all SiON with thicknesses that depend on the designed programming voltage. The control gate can be formed overlapping the access gate or the access gate can be formed overlapping the control gate.

02-18-2010

20100041244

HAFNIUM TANTALUM OXYNITRIDE DIELECTRIC - Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum oxynitride film may be structured as one or more monolayers. The hafnium tantalum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a hafnium tantalum oxynitride film.

02-18-2010

20100065902

SCALABLE HIGH DENSITY NON-VOLATILE MEMORY CELLS IN A CONTACTLESS MEMORY ARRAY - A plurality of mesas are formed in the substrate. Each pair of mesas forms a trench. A plurality of diffusion areas are formed in the substrate. A mesa diffusion area is formed in each mesa top and a trench diffusion area is formed under each trench. A vertical, non-volatile memory cell is formed on each sidewall of the trench. Each memory cell is comprised of a fixed threshold element located vertically between a pair of non-volatile gate insulator stacks. In one embodiment, each gate insulator stack is comprised of a tunnel insulator formed over the sidewall, a deep trapping layer, and a charge blocking layer. In another embodiment, an injector silicon rich nitride layer is formed between the deep trapping layer and the charge blocking layer.

03-18-2010

20100072537

BAND ENGINEERED NANO-CRYSTAL NON-VOLATILE MEMORY DEVICE UTILIZING ENHANCED GATE INJECTION - Non-volatile memory devices and arrays are described that utilize reverse mode non-volatile memory cells that have band engineered gate-stacks and nano-crystal charge trapping in EEPROM and block erasable memory devices, such as Flash memory devices. Embodiments of the present invention allow a reverse mode gate-insulator stack memory cell that utilizes the control gate for programming and erasure through a band engineered crested tunnel barrier. Charge retention is enhanced by utilization of high work function nano-crystals in a non-conductive trapping layer and a high K dielectric charge blocking layer. The band-gap engineered gate-stack with symmetric or asymmetric crested barrier tunnel layers of the non-volatile memory cells of embodiments of the present invention allow for low voltage tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention.

03-25-2010

20100090265

High density nanodot nonvolatile memory - A nanodot nonvolatile memory element comprises a substrate having a source and a drain region formed therein, and an insulating layer formed on the substrate. The insulating layer contains a nanocrystalline floating gate of approximately three to six nanometers in diameter formed at a distance of approximately two to five nanometers from the substrate, and a carbon nanotube control gate having a diameter of approximately six nanometers or less is formed at a distance of approximately 10-15 nanometers from the substrate.

04-15-2010

20100109068

Lanthanide dielectric with controlled interfaces - Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on the lanthanide dielectric film.

05-06-2010

20100167479

EMBEDDED TRAP DIRECT TUNNEL NON-VOLATILE MEMORY - The cell comprises a substrate having a drain region and a source region. An oxynitride layer is formed over the substrate. An embedded trap layer is formed over the oxynitride layer. An injector layer is formed over the embedded trap layer. A high dielectric constant layer is formed over the injector layer. A polysilicon control gate formed over the high dielectric constant layer. The cell can be formed in a planar architecture or a two element, split channel, three-dimensional device. The planar cell is formed with the high dielectric constant layer and the control gate being formed over and substantially around three sides of the embedded trap layer. The split channel device has a source line in the substrate under each trench and a bit line on either side of the trench.

07-01-2010

20100193032

Solar Cell Systems - The invention includes optoelectronic devices containing one or more layers of semiconductor-enriched insulator (with exemplary semiconductor-enriched insulator being silicon-enriched silicon oxide and silicon-enriched silicon nitride), and includes solar cells containing one or more layers of semiconductor-enriched insulator. The invention also includes methods of forming optoelectronic devices and solar cells.

TANTALUM ALUMINUM OXYNITRIDE HIGH-K DIELECTRIC - Electronic apparatus and methods of forming the electronic apparatus may include a tantalum aluminum oxynitride film for use in a variety of electronic systems and devices. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film.

11-11-2010

20100295118

Nanocrystal Based Universal Memory Cells, and Memory Cells - Some embodiments include memory cells that contain a dynamic random access memory (DRAM) element and a nonvolatile memory (NVM) element. The DRAM element contains two types of DRAM nanoparticles that differ in work function. The NVM contains two types of NVM nanoparticles that differ in trapping depth. The NVM nanoparticles may be in vertically displaced charge-trapping planes. The memory cell contains a tunnel dielectric, and one of the charge-trapping planes of the NVM may be further from the tunnel dielectric than the other. The NVM charge-trapping plane that is further from the tunnel dielectric may contain larger NVM nanoparticles than the other NVM charge-trapping plane. The DRAM element may contain a single charge-trapping plane that has both types of DRAM nanoparticles therein. The memory cells may be incorporated into electronic systems.

11-25-2010

20100301428

TANTALUM SILICON OXYNITRIDE HIGH-K DIELECTRICS AND METAL GATES - Electronic apparatus and methods of forming the electronic apparatus include a tantalum silicon oxynitride film on a substrate for use in a variety of electronic systems. The tantalum silicon oxynitride film may be structured as one or more monolayers. The tantalum silicon oxynitride film may be formed using a monolayer or partial monolayer sequencing process. Metal electrodes may be disposed on a dielectric containing a tantalum silicon oxynitride film.

12-02-2010

20100308389

DISCRETE TRAP NON-VOLATILE MULTI-FUNCTIONAL MEMORY DEVICE - A multiple layer tunnel insulator is fabricated between a substrate and a discrete trap layer. The properties of the multiple layers determines the volatility of the memory device. The composition of each layer and/or the quantity of layers is adjusted to fabricate either a DRAM device, a non-volatile memory device, or both simultaneously.

12-09-2010

20110070717

CAPACITORS AND METHODS WITH PRASEODYMIUM OXIDE INSULATORS - Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. Monolayers that contain titanium or other metals are deposited onto a substrate and subsequently processed to form metal electrodes. Resulting capacitor structures includes properties such as improved dimensional control. One improved dimensional control includes thickness. Some resulting capacitor structures also include properties such as an amorphous or nanocrystalline microstructure. Selected components of capacitors formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.

03-24-2011

20110086481

METHODS OF FORMING NON-VOLATILE MEMORY STRUCTURE WITH CRESTED BARRIER TUNNEL LAYER - Embodiments of methods of forming non-volatile memory structures are provided. In one such embodiment, first and second source/drain regions are formed on a substrate so that the first and second source/drain regions define an intervening channel region. A charge blocking layer is formed over the channel region. A trapping layer is formed over the charge blocking layer. A tunnel layer of two or more sub-layers is formed over the trapping layer, where the two or more sub-layers form a crested barrier tunnel layer. A control gate is formed over the tunnel layer.

04-14-2011

20110133268

Memory Cells - Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.

06-09-2011

20110248353

METHODS OF FORMING STRAINED SEMICONDUCTOR CHANNELS - In various method embodiments, a device region in a semiconductor substrate and isolation regions adjacent to the device region are defined. The device region has a channel region and the isolation regions have strain-inducing regions laterally adjacent to the channel regions. The channel region is strained with a desired strain for carrier mobility enhancement, where at least one ion type is implanted with an energy resulting in a peak implant in the strain-inducing regions of the isolation regions. Other aspects and embodiments are provided herein.

LANTHANIDE DIELECTRIC WITH CONTROLLED INTERFACES - Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on the lanthanide dielectric film.

12-01-2011

20120094477

HAFNIUM TANTALUM OXYNITRIDE DIELECTRIC - Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum oxynitride film may be structured as one or more monolayers. The hafnium tantalum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a hafnium tantalum oxynitride film.

04-19-2012

20120133428

DIELECTRICS CONTAINING AT LEAST ONE OF A REFRACTORY METAL OR A NON-REFRACTORY METAL - Electronic apparatus and methods of forming the electronic apparatus may include one or more insulator layers having a refractory metal and a non-refractory metal for use in a variety of electronic systems and devices. Embodiments can include electronic apparatus and methods of forming the electronic apparatus having a tantalum aluminum oxynitride film. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film.

05-31-2012

20120139004

HIGH-PERFORMANCE ONE-TRANSISTOR MEMORY CELL - One aspect of this disclosure relates to a memory cell. In various embodiments, the memory cell includes an access transistor having a floating node, and a diode connected between the floating node and a diode reference potential line. The diode includes an anode, a cathode, and an intrinsic region between the anode and the cathode. A charge representative of a memory state of the memory cell is held across the intrinsic region of the diode. In various embodiments, the memory cell is implemented in bulk semiconductor technology. In various embodiments, the memory cell is implemented in semiconductor-on-insulator technology. In various embodiments, the diode is gate-controlled. In various embodiments, the diode is charge enhanced by an intentionally generated charge in a floating body of an SOI access transistor. Various embodiments include laterally-oriented diodes (stacked and planar configurations), and various embodiments include vertically-oriented diodes. Other aspects and embodiments are provided herein.

06-07-2012

20120161223

DISCRETE TRAP NON-VOLATILE MULTI-FUNCTIONAL MEMORY DEVICE - A multiple layer tunnel insulator is fabricated between a substrate and a discrete trap layer. The properties of the multiple layers determines the volatility of the memory device. The composition of each layer and/or the quantity of layers is adjusted to fabricate either a DRAM device, a non-volatile memory device, or both simultaneously.

06-28-2012

20120164804

METHODS OF FORMING REVERSE MODE NON-VOLATILE MEMORY CELL STRUCTURES - Methods of forming non-volatile memory cell structures are described that facilitate the use of band-gap engineered gate stacks with asymmetric tunnel barriers in reverse and normal mode floating node memory cells that allow for direct tunnel programming and erase, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention. The low voltage direct tunneling program and erase capability reduces damage to the gate stack and the crystal lattice from high energy carriers, reducing write fatigue and enhancing device lifespan. The low voltage direct tunnel program and erase capability also enables size reduction through low voltage design and further device feature scaling. Such memory cells also allow multiple bit storage. These characteristics allow such memory cells to operate within the definition of a universal memory, capable of replacing both DRAM and ROM in a system.

06-28-2012

20120181662

LANTHANIDE DIELECTRIC WITH CONTROLLED INTERFACES - Methods and devices for a dielectric are provided. One method embodiment includes forming a passivation layer on a substrate, wherein the passivation layer contains a composition of silicon, oxygen, and nitrogen. The method also includes forming a lanthanide dielectric film on the passivation layer, and forming an encapsulation layer on the lanthanide dielectric film.

07-19-2012

20120205720

TANTALUM SILICON OXYNITRIDE HIGH-K DIELECTRICS AND METAL GATES - Electronic apparatus and methods of forming the electronic apparatus include a tantalum silicon oxynitride film on a substrate for use in a variety of electronic systems. The tantalum silicon oxynitride film may be structured as one or more monolayers. The tantalum silicon oxynitride film may be formed using a monolayer or partial monolayer sequencing process. Metal electrodes may be disposed on a dielectric containing a tantalum silicon oxynitride film.

DEVICES AND METHODS TO IMPROVE CARRIER MOBILITY - Electronic apparatus and methods of forming the electronic apparatus include a silicon oxynitride layer on a semiconductor device for use in a variety of electronic systems. The silicon oxynitride layer may be structured to control strain in a silicon channel of the semiconductor device to modify carrier mobility in the silicon channel, where the silicon channel is configured to conduct current under appropriate operating conditions of the semiconductor device.

02-21-2013

20130279259

HAFNIUM TANTALUM OXYNITRIDE DIELECTRIC - Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum oxynitride film may be structured as one or more monolayers. The hafnium tantalum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a hafnium tantalum oxynitride film.

10-24-2013

20140035101

DIELECTRICS CONTAINING AT LEAST ONE OF A REFRACTORY METAL OR A NON-REFRACTORY METAL - Electronic apparatus and methods of forming the electronic apparatus may include one or more insulator layers having a refractory metal and a non-refractory metal for use in a variety of electronic systems and devices. Embodiments can include electronic apparatus and methods of forming the electronic apparatus having a tantalum aluminum oxynitride film. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film.

02-06-2014

20140138795

CAPACITORS AND METHODS WITH PRASEODYMIUM OXIDE INSULATORS - Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. Monolayers that contain titanium or other metals are deposited onto a substrate and subsequently processed to form metal electrodes. Resulting capacitor structures includes properties such as improved dimensional control. One improved dimensional control includes thickness. Some resulting capacitor structures also include properties such as an amorphous or nanocrystalline microstructure. Selected components of capacitors formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.

05-22-2014

20140322923

DIELECTRICS CONTAINING AT LEAST ONE OF A REFRACTORY METAL OR A NON-REFRACTORY METAL - Electronic apparatus and methods of forming the electronic apparatus may include one or more insulator layers having a refractory metal and a non-refractory metal for use in a variety of electronic systems and devices. Embodiments can include electronic apparatus and methods of forming the electronic apparatus having a tantalum aluminum oxynitride film. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film.

10-30-2014

20150035119

CAPACITORS AND METHODS WITH PRASEODYMIUM OXIDE INSULATORS - Methods of forming and the resulting capacitors formed by these methods are shown. Monolayers that contain praseodymium are deposited onto a substrate and subsequently processed to form praseodymium oxide dielectrics. Monolayers that contain titanium or other metals are deposited onto a substrate and subsequently processed to form metal electrodes. Resulting capacitor structures includes properties such as improved dimensional control. One improved dimensional control includes thickness. Some resulting capacitor structures also include properties such as an amorphous or nanocrystalline microstructure. Selected components of capacitors formed with these methods have better step coverage over substrate topography and more robust film mechanical properties.