We are trying to use Physical compiler(PC) in our mult imillion gates IP development.

Almost all our sub-designs are too big for the RTL2placedgates flow in PC.
Hence, we are using DEsign Compiler (DC) for the initial synthesis and then continue with the gates2placedgates.

I'm sure many of you would have done or facing a similar situation.
What kind of changes have you done to the traditional DC synthesis flow to give a basic technology mapping of the RTL description without too much bufferings...