Programming the auxiliary boards

Situation

In normal operation, the CPLD receives configuration data from the backplane (originating from the mainboard through the SCSI port) and distributes it to the FPGAs. The CPLD uses JTAG to send data to the FPGAs. The 64 FPGAs on each auxiliary board are arranged to form one big JTAG chain driven by the CPLD.

Because this mode of operation uses a proprietary protocol which is especially hard to reverse engineer since we do not have the original software and SCSI device driver, we are trying to program the boards with a JTAG probe.

CPLD access

The CPLD's JTAG port is accessible on each board with a HE10 connector following the MultiLINX pinout.

Vref

GND

NC

NC

NC

NC

NC

NC

NC

NC

TDO

NC

X

TDI

TCK

TMS

NC

NC

Legend: X = missing pin (key), NC = No Connect

We can use urJTAG to access the CPLD, with the BSDL files released by Xilinx to enable boundary scan. For an unknown reason, the Xilinx iMPACT tool fails to recognize the CPLD.