1149.4 working group meeting
Oct 28, 2001
Meeting came to order at about 8:40am, and attendees identified themselves
Attendees:
Adam Cron Synopsys
a.cron@ieee.org
Ken Parker Agilent
kenneth_parker@agilent.com
Steve Sunter LogicVision
sunter@logicvision.com
Adam Ley ASSET InterTech
aley@asset-intertech.com
Frans de Jong Philips
frans.de.jong@philips.com
Bill Aronson National Semiconductor
bill.aronson@nsc.com
Jeff Butler National Semiconductor
jeff.butler@nsc.com
Bob Russell EMC
russell_rj@cmc.com
Ted Eaton Cisco
teaton@cisco.com
Bill Eklow Cisco
beklow@cisco.com
Jim Monzel IBM
jmonzel@us.ibm.com
Ad van de Goor Delft University of Technology
a.j.vandegoor@its.tudelft.nl
John Braden Sun Microsystems
j.braden@ieee.org
Minutes from ITC’00 WG meeting accepted unanimously – they are on the dot4
web-site.
Steve Sunter – Status of the National Semiconductor (NSC) chip
* A checklist for designers would be useful
* 500 ohm switches were used; each is about the size of a NAND gate
* ABM is about half the size of a bond pad (100x100um), but much of the
logic is in the core of the IC (synthesized from RTL)
* The large arrows in the graphic representation of the chip are ABMs
* The more practical method (used for this chip) of measuring Rcom
should be put in the standard, i.e. use 0 or 10 ohms instead of 1000
ohms as the CUT
* Steve clarified that he wrote “I think” in his slide 2 because he
wasn’t absolutely sure if every recommendation was implemented on the
chip
* It was suggested that an IC designer’s checklist should be created
with all rules and recommendations concisely listed
* The NSC demo board will only be made available publicly on a very
limited basis (e.g., for software developers or selected customers of
NSC)
Adam Cron – Tutorial development
A 2-day class was proposed by Adam Osseiran prior to the meeting, as
follows
Intro to Bscan (1149.1)
Adam Cron
Mixed-signal Bscan (1149.4)
Mani Soma
System Test Methodologies
Steve Sunter
Structural Test and Implementation Examples John
McDermid/Steve Sunter
* Bill Aronson said that the NSC demo board might be a suitable board
for the tutorial
* Adam Ley said ASSET software might be made available for the tutorial
* Adam Osseiran is driving the tutorial development
* VTS appears to be the earliest practical time and place, in Monterrey,
California
* Ken asked at whom is the tutorial aimed
* VTS seems to be too IC-oriented, ITC would be better
* The ITC tutorial submission deadline is the end of November
* 1 day is likely sufficient, especially if 1149.1 stuff is only briefly
summarized
* A hands-on portion would be preferable, however that is impractical
for ITC
* Bill pointed out that demos tend to cost a lot of class time even for
simple cases
* In any case, we need to decide the dates very soon
* IMSTW would be suitable – we could at least have a demo during the
poster session, to show 1149.4’s advanced capabilities
* Steve said that we should in any case submit an ITC tutorial proposal
Review of Draft – Adam Cron
* Does anyone know of any changes needed to 1149.4 standard?
* What is the status of the analog extension to BSDL?
* Adam Ley - “Is it dead?” Adam Cron - “No, but there is no life in it”
* Steve said that nothing will happen beyond John’s straw dog proposal
until there is market pull, which won’t happen until people use
1149.4, which won’t happen until they get chips in their hands
* What about CTL? – nothing happening for analog
* There was some discussion about if/when CTL could be used – not soon
was the conclusion
* Ken said there is no economic justification to drive ABSDL development
* What is holding up ABDSL? – no parts, no applications
* Bill Eklow said that if 1149.4 could be used for AC-EXTEST
applications, then there would be a market pull almost immediately
* What is stopping designers from using 1149.4 for AC-EXTEST
applications now?
* Bill E. asked how would we handle 30 chips for gigabit SERDES
applications coming out with 1149.4 in the next year
* Bill Aronson noted that a greater issue is that 1149.4 is not
technically ready for many applications – it needs to be proven
suitable
* Bill E. said RF is a perfect application – embedded testing
* A suitable VTS slant might be to talk about solving RF test problems
* The lack of ABSDL may not be holding back 1149.4 adoption, but it
doesn’t help
* Pad macro designers are an extremely rare breed, who are very busy,
and they won’t change pad design unless there is a compelling reason
* Adam – dot4 adoption will be worse than dot1; Bill E. said that until
designers see a real need for any DFT standard, they won’t implement
it
* Adam Ley – Designers presently have no incentive to put in dot4
* Frans – dot4 won’t go in until it is mandated as a functional
requirement
* Steve said dot 4 needs to pay off at the chip level before it will be
adopted – using it to do DC parametrics can allow reduced pin-count
testing (RPCT)
* Steve said that dot4 discussions have only been around 10 kHz, so are
ignored by RF designers – we need to show that testing RF can be done
by mixing signals down to LF
* Need also to show how dot4 can test the structure of RF circuits,
instead of their function
* Dot4 needs ABSDL for board testing
* Dot4 is only an access mechanism, whereas AC-EXTEST is access plus a
test method, and AC-EXTEST is needed “yesterday”
* Bill E. said that if we can convince the board guys that dot4 will
provide big benefits, then they will convince the chip guys to
implement it on chip
* For VTS, the chip-level benefits need to be stressed, such as RPCT
* Panel 10 (ITC 2001) will debate AC-EXTEST, and whether dot4 is
applicable
* Adam noted that the 1149.4 PAR is still open (it was recently
officially re-opened)
* Adam Ley asked, “do we let the sleeping straw dog lie” or what
* Steve – the analog nature of dot4 said that we need more proof of
concept for accuracy and frequency before software will be the
bottleneck
* Ken said he would help, but he’s too busy and he’s not suitably analog
literate
* Steve said he himself was more interested in the hardware side and
solving specific technical problems
* Adam L. asked if PLD companies would be interested in the RPCT aspect
(like any IC company), and PLDs would be a good first application
because virtually every board designed today has a PLD, and many of
the chips have unused pins
Adjourned, unanimously at 11:00am
In unofficial discussion after the adjournment:
* Adam C. will look into getting dot4 errata onto the dot4 web site, and
included with future purchased copies of the standard