Apparently Knights Landing will use a derivative of the Silvermont (Atom) core. The above report speaks about "two 512b vector units per core", but it is still unclear if that means two floating point multiply-add pipelines, or a combination of one FP and one fixed point unit.

The issue width is still two instructions per clock. That implies it will be very difficult to fully saturate both vector FPUs for any significant amount of time. (Memory accesses and integer instructions compete with floating point instructions.)

Clock speed is expected to be similar to current Xeon Phi: somewhere near 1.3GHz.