We need to find a solution for the bitfile name scrambling

As shown here, the actual bitfile name is retained unchanged, but the expected bitfile name (in the FPGA buils spec) gets mangled with the project name that the user choses, requiring a lenghty FPGA recompile. The current solution is to open the FPGA build spec and point it to the bitfile that is already there, but that should not be necessary, and impacts the user experience.

Is there an xml setting to fix that or is there a bug in the project scripter?

Re: We need to find a solution for the bitfile name scrambling

We are not including the FPGA source code, just the bitfile, that is why I was not seeing the same bitfile name change that you see.

What we are seeing is that the FPGA reference points to the bitfile in the Project Template folder and not the one in the project. Not a big deal if the user stays in the same computer, but if they decide to move the project to another computer they might not realize that the bitfile is not connected to the right bitfile. We added for now the #Configuration-Needed comment.

Re: We need to find a solution for the bitfile name scrambling

I am working on a post-copy scripting VI that should resolve these issues. In your XML document, you should have a field for <CustomVIPath>. The current myRIO PostCopyScriping.vi is linked here. This VI sets the target address of the myRIO if it was provided. I will add code to update the Open FPGA Reference VI, which should resolve your issues. You'll have to include the VI with your installer, place on disk it in LabVIEW 2013\ProjectTemplates\Source\myRIO\scripting\myRIOMetaDataObj, and link to it from the XML.

Altenbach, I believe the problem you are seeing only relates to the Build Spec for the FPGA Main bitfile. That is, if the user were to recompile their FPGA VI, the new bitfile would have the name spacing shown. Is your screenshot showing the FPGA Main Properties for configuring the build spec, or a different property window? In the screen shot below, you can see that the FPGA Bitfile in my project, generated from the Create Project view, has the original name. The FPGA Main Properties window for the Build Spec shows the updated name. As such, the same PostCopyScripting VI provided for Fabiola should fix your issues as well - linking the Open FPGA reference to the newly copied bitfile.

I will be contacting each of you individually to provide the PostCopyScripting VI. Anyone else who needs to call this VI should send me a direct message requesting the VI.

Re: We need to find a solution for the bitfile name scrambling

Altenbach, I believe the problem you are seeing only relates to the Build Spec for the FPGA Main bitfile. That is, if the user were to recompile their FPGA VI, the new bitfile would have the name spacing shown. Is your screenshot showing the FPGA Main Properties for configuring the build spec, or a different property window?

Yes, the screenshot shows the FPGA build spec right after demo project generation. Hopefully your solution will work around this issue.

In any case, if I try to run the project out-of-the-box, it wants to recompile because it is looking for the wrong bitfile.

Re: We need to find a solution for the bitfile name scrambling

Thanks. Yes I figured it out and actually built a new version that uses a short and concise bitfile name. Works fine.

(I think having these ultra-long automatic names is a bit of a general problem, especially with these deep hierachies present. I was actually running into path lenght issues until I rooted the project in a shallower path. How many extra characters do we really need to avoid collisions????)