The Z80 CPU is an 8-bit based microprocessor. It was introduced by Zilog in 1976 as the startup company's first product. The Z80 was conceived by Federico Faggin in late 1974 and developed by him and his then-11 employees at Zilog from early 1975 until March 1976, when the first fully working samples were delivered. With the revenue from the Z80, the company built its own chip factories and grew to over a thousand employees over the following two years.[2]

In the early 1980s, the Z80 was the one of the most commonly used CPU in the home computer market from the late 1970s to the mid 1980s.[4][5] Zilog licensed the Z80 to the US-based Synertek and Mostek, that had helped them with initial production, as well as to a European second source manufacturer, SGS. The design was copied also by several Japanese, East European and Russian manufacturers.[6] This enabled the Z80 to gain acceptance in the world market since large companies like NEC, Toshiba, Sharp, and Hitachi, started to manufacture the device (or their own Z80 compatible designs). In recent decades Zilog has refocused on the ever-growing market for embedded systems (for which the original Z80 and the Z180 were designed) and the most recent Z80-compatible microcontroller family, the fully pipelined24-biteZ80 with a linear 16 MBaddress range, has been successfully introduced alongside the simpler Z180 and Z80 products.

By March 1976, Zilog had developed the Z80 as well as an accompanying assembler based development system for its customers, and by July 1976, this was formally launched onto the market.[7] (Some of the Z80 support and peripheral ICs were under development at this point, and many of them were launched during the following year.)

Early Z80s were manufactured by Synertek and Mostek, before Zilog had its own manufacturing factory ready, in late 1976. These companies were chosen because they could do the ion implantation needed to create the depletion-mode MOSFETs that the Z80 design used as load transistors in order to cope with a single 5 Volt power supply.[8]

Faggin designed the instruction set to be binary compatible with the Intel 8080[9][10] so that most 8080 code, notably the CP/Moperating system and Intel's PL/M compiler for 8080 (as well as its generated code), would run unmodified on the new Z80 CPU. Masatoshi Shima designed most of the microarchitecture as well as the gate and transistor levels of the Z80 CPU, assisted by a small number of engineers and layout people.[11][12] CEO Federico Faggin was actually heavily involved in the chip layout work, together with two dedicated layout people. Faggin worked 80 hours a week in order to meet the tight schedule given by the financial investors, according to himself.[13]

A more automatic and general vectorized interrupt system, mode 2, primarily intended for Zilog's line of counter/timers, DMA and communications controllers, as well as a fixed vector interrupt system, mode 1, for simple systems with minimal hardware (with mode 0 being the 8080-compatible mode).[17]

A non maskable interrupt (NMI) which can be used to respond to power down situations and/or other high priority events (and allowing a minimalistic Z80 system to easily implement a two-level interrupt scheme in mode 1).

Two separate register files, which could be quickly switched, to speed up response to interrupts such as fast asynchronous event handlers or a multitaskingdispatcher. Although they were not intended as extra registers for general code, they were nevertheless used that way in some applications.[18]

Less hardware required for power supply, clock generation and interface to memory and I/O

A special reset function which clears only the program counter so that a single Z80 CPU could be used in a development system such as an in-circuit emulator.[20]

The Z80 took over from the 8080 and its offspring, the 8085, in the processor market,[21] and became one of the most popular 8-bit CPUs.[4][5] Perhaps a key to the initial success of the Z80 was the built-in DRAM refresh, and other features which allowed systems to be built with fewer support chips (Z80 embedded systems typically use static RAM and hence do not need this refresh).

For the original NMOS design, the specified upper clock frequency limit increased successively from the introductory 2.5 MHz, via the well known 4 MHz (Z80A), up to 6 (Z80B) and 8 MHz (Z80H).[22][23]CMOS versions were also developed with specified upper frequency limits ranging from 4 MHz up to 20 MHz for the version sold today. The CMOS versions also allowed low-power sleep with internal state retained, having no lower frequency limit.[24] The fully compatible derivatives HD64180/Z180[25][26] and eZ80 are currently specified for up to 33 and 50 MHz respectively.

An approximate block diagram of the Z80. There is no dedicated adder for offsets or separate incrementer for R, and no need for more than a single 16-bit temporary register WZ (although the incrementer latches are also used as a 16-bit temporary register, in other contexts). It is the PC and IR registers that are placed in a separate group, with a detachable bus segment, to allow updates of these registers in parallel with the main register bank.[27]

The programming model and register set are fairly conventional, ultimately based on the register structure of the Datapoint 2200 (which the related 8086 family also inherited). The Z80 was designed as an extension of the 8080, created by the same engineers, which in turn was an extension of the 8008 and the Datapoint 2200. These early designs allowed register H and L to be paired into a 16-bit address register HL. In the 8080 this pairing was generalized into BC and DE, while HL also became usable as a 16-bit accumulator. The Z80 orthogonalized this a bit further by making all 16-bit register pairs (including IX and IY) more general purpose, with 16-bit copying directly to and from memory. The new 16-bit IX and IY registers are primarily intended as base address-registers, where a particular instruction supplies a constant offset, but they are also usable as 16-bit accumulators, among other things. The Z80 also introduces a new signed overflow flag and complements the fairly simple 16-bit arithmetics of the 8080 with dedicated instructions for signed 16-bit arithmetics.

The 8080 compatible registers AF, BC, DE, HL are duplicated as two separate banks in the Z80,[28] where the processor can quickly switch from one bank to the other;[29] a feature useful for speeding up responses to single-level, high-priority interrupts. A similar feature was present in the Datapoint 2200 but was never implemented at Intel. The dual register-set makes sense as the Z80 (like most microprocessors at the time) was really intended for embedded use, not for personal computers, or the yet-to-be invented home computers. According to one of the designers, Masatoshi Shima, the market focus was on high performance printers, high-end cash registers, and intelligent terminals, although Ralph Ungermann also saw other opportunities, such as computers.[30] The two register sets also turned out to be quite useful for heavily optimized manual assembly-language coding, such as for floating point arithmetics or home computer games.

AF': alternate (or shadow) accumulator and flags (toggled in and out with EX AF,AF' )

BC', DE' and HL': alternate (or shadow) registers (toggled in and out with EXX)

Four bits of interrupt status and interrupt mode status

There is no direct access to the alternate registers; instead, two special instructions, EX AF,AF' and EXX,[31] each toggles one of two multiplexer flip-flops. This enables fast context switches for interrupt service routines: EX AF, AF' may be used alone, for really simple and fast interrupt routines, or together with EXX to swap the whole BC, DE, HL set. This is still several times as fast as pushing the same registers on the stack. Slower, lower priority, or multi level interrupts normally use the stack to store registers, however.

The refresh register, R, increments each time the CPU fetches an opcode (or opcode prefix) and has no simple relationship with program execution. This has sometimes been used to generate pseudorandom numbers in games, and also in software protection schemes.[citation needed] It has also been employed as a "hardware" counter in some designs; an example of this is the ZX81, which lets it keep track of character positions on the TV screen by triggering an interrupt at wrap around (by connecting INT to A6).

The interrupt vector register, I, is used for the Z80 specific mode 2 interrupts (selected by the IM 2 instruction). It supplies the high byte of the base address for a 128-entry table of service routine addresses which are selected via an index sent to the CPU during an interrupt acknowledge cycle; this index is simply the low byte part of the pointer to the tabulated indirect address pointing to the service routine.[17] The pointer identifies a particular peripheral chip and/or peripheral function or event, where the chips are normally connected in a so-called daisy chain for priority resolution. Like the refresh register, this register has also sometimes been used creatively; in interrupt modes 0 and 1 (or in a system not using interrupts) it can be used as simply another 8-bit data register.

The instructions LD A,R and LD A,I affect the Z80 flags register, unlike all the other LD (load) instructions. The Sign (bit 7) and Zero (bit 6) flags are set according to the data loaded from the Refresh or Interrupt source registers. For both instructions, the Parity/Overflow flag (bit 2) is set according to the current state of the IFF2 flip-flop.[32]

The first Intel 8008assembly language was based on a very simple (but systematic) syntax inherited from the Datapoint 2200 design. This original syntax was later transformed into a new, somewhat more traditional, assembly language form for this same original 8008 chip. At about the same time, the new assembly language was also extended to accommodate the added addressing possibilities in the more advanced Intel 8080 chip (the 8008 and 8080 shared a language subset without being binary compatible; however, the 8008 was binary compatible with the Datapoint 2200).

In this process, the mnemonic L, for LOAD, was replaced by various abbreviations of the words LOAD, STORE and MOVE, intermixed with other symbolic letters. The mnemonic letter M, for memory (referenced by HL), was lifted out from within the instruction mnemonic to become a syntactically freestanding operand, while registers and combinations of registers became very inconsistently denoted; either by abbreviated operands (MVI D, LXI H and so on), within the instruction mnemonic itself (LDA, LHLD and so on), or both at the same time (LDAX B, STAX D and so on).

Illustration of four syntaxes, using samples of equivalent, or (for 8086) very similar, load and store instructions.[34] The Z80 syntax uses parentheses around an expression to indicate that the value should be used as a memory address (as mentioned below), while the 8086 syntax uses brackets instead of ordinary parentheses for this purpose. Both Z80 and 8086 use the + sign to indicate that a constant is added to a base register to form an address

Because Intel had a copyright on their assembly mnemonics,[35] a new assembly syntax had to be developed for the Z80. This time a more systematic approach was used:

All registers and register pairs are explicitly denoted by their full names

Parentheses are consistently used to indicate "memory contents at" (constant address or variable pointer dereferencing) with the exception of some jump instructions.[36]

All load and store instructions use the same mnemonic name, LD, for LOAD (a return to the simplistic Datapoint 2200 vocabulary); other common instructions, such as ADD and INC, use the same mnemonic regardless of addressing mode or operand size. This is possible because the operands themselves carry enough information.

These principles made it straightforward to find names and forms for all new Z80 instructions, as well as orthogonalizations of old ones, such as LD BC,(1234).

Apart from naming differences, and despite a certain discrepancy in basic register structure, the Z80 and 8086 syntax are virtually isomorphic for a large portion of instructions. Only quite superficial similarities (such as the word MOV, or the letter X, for extended register) exist between the 8080 and 8086 assembly languages, although 8080 programs can be assembled into 8086 object code using a special assembler or translated to 8086 assembly language by a translator program.[37][38]

The Z80 uses 252 out of the available 256 codes as single byte opcodes ("root instruction"); the four remaining codes are used extensively as opcode prefixes:[39] CB and ED enable extra instructions and DD or FD selects IX+d or IY+d respectively (in some cases without displacement d) in place of HL. This scheme gives the Z80 a large number of permutations of instructions and registers; Zilog categorizes these into 158 different "instruction types", 78 of which are the same as those of the Intel 8080[39] (allowing operation of most 8080 programs on a Z80). The Zilog documentation further groups instructions into the following categories:

8-bit arithmetic and logic operations

16-bit arithmetic

8-bit load

16-bit load

Bit set, reset, and test

Call, return, and restart

Exchange, block transfer, and search

General purpose arithmetic and CPU control

Input and output

Jump

Rotate and shift

No multiply instruction is available in the original Z80.[40] Different sizes and variants of additions, shifts, and rotates have somewhat differing effects on flags because most[41] of the flag-changing properties of the 8080 were copied.

The Z80 has six new LD instructions that can load the DE, BC, and SP register pairs from memory, and load memory from these three register pairs -- unlike the 8080.[42] As on the 8080, load instructions do not affect the flags (except for the special purpose I and R register loads). A quirk (common with the 8080) of the register-to-register load instructions is that each of the 8-bit registers can be loaded from themselves (e.g. LD A,A). This is effectively a NOP.

Unlike the 8080, the Z80 can jump to a relative address using a signed 8-bit displacement. Only the Zero and Carry flags can be tested for these new two-byte JR instructions.

A two-byte instruction specialized for program looping is new to the Z80. DJNZ (Decrement Jump if Non-Zero) takes a signed 8-bit displacement as an immediate operand. The B register is decremented. If the result is nonzero then program execution jumps relative to the address of the PC plus the displacement. The flags remain unaltered. To perform an equivalent loop on an 8080 would require separate decrement and jump (to a two-byte absolute address) instructions, and the flag register would be altered.

The index register (IX/IY) instructions can be useful for accessing data organised in fixed heterogenous structures (such as records) or at fixed offsets relative a variable base address (as in recursivestack frames) and can also reduce code size by removing the need for multiple short instructions using non-indexed registers. However, although they may save speed in some contexts when compared to long/complex "equivalent" sequences of simpler operations, they incur a lot of additional CPU time (e.g. 19 T-states to access one indexed memory location vs. as little as 11 to access the same memory using HL and INCrement it to point to the next). Thus, for simple or linear accesses of data, IX and IY tend to be slower. Still, they may be useful in cases where the 'main' registers are all occupied, by removing the need to save/restore registers. Their officially undocumented 8-bit halves (see below) can be especially useful in this context, for they incur less slowdown than their 16-bit parents. Similarly, instructions for 16-bit additions are not particularly fast (11 clocks) in the original Z80; nonetheless, they are about twice as fast as performing the same calculations using 8-bit operations, and equally important, they reduce register usage.

The 10-year-newer microcoded Z180 design could initially afford more "chip area", permitting a slightly more efficient implementation (using a wider ALU, among other things); similar things can be said for the Z800, Z280, and Z380. However, it was not until the fully pipelined eZ80 was launched in 2001 that those instructions finally became approximately as cycle-efficient as it is technically possible to make them, i.e. given the Z80 encodings combined with the capability to do an 8-bit read or write every clock cycle.[citation needed]

The index registers, IX and IY, were intended as flexible 16 bit pointers, enhancing the ability to manipulate memory, stack frames and data structures. Officially, they were treated as 16-bit only. In reality, they were implemented as a pair of 8-bit registers,[43] in the same fashion as the HL register, which is accessible either as 16 bits or separately as the High and Low registers. Even the binary opcodes (machine language) were identical, but preceded by a new opcode prefix.[44] Zilog published the opcodes and related mnemonics for the intended functions, but did not document the fact that every opcode that allowed manipulation of the H and L registers was equally valid for the 8 bit portions of the IX and IY registers. As an example, the opcode 26h followed by an immediate byte value (LD H,n) will load that value into the H register. Preceding this two-byte instruction with the IX register's opcode prefix, DD, would instead result in the most significant 8 bits of the IX register being loaded with that same value. A notable exception to this would be instructions similar to LD H,(IX+d) which make use of both the HL and IX or IY registers in the same instruction;[44] in this case the DD prefix is only applied to the (IX+d) portion of the instruction.

There are several other undocumented instructions as well.[45] Undocumented or illegal opcodes are not detected by the Z80 and have various effects, some of which are useful. However, as they are not part of the formal definition of the instruction set, different implementations of the Z80 are not guaranteed to work the same way for every undocumented opcode.

The OTDR instruction doesn't conform to the Z80 documentation. Both OTDR and OTIR are supposed to leave the carry C unaffected. OTIR functions correctly; however, during the execution of the OTDR instruction, the carry takes the results of a spurious compare between the accumulator and what has last been output by the OTDR instruction.

The following Z80 assembly source code is for a subroutine named memcpy that copies a block of data bytes of a given size from one location to another. Important: The example code does not handle a certain case where the destination block overlaps the source; a fatal bug. The sample code is extremely inefficient, intended to illustrate various instruction types, rather than best practices for speed. In particular, the Z80 has a single instruction that will execute the entire loop (LDIR). The data block is copied one byte at a time, and the data movement and looping logic utilizes 16-bit operations. Note that the assembled code is binary-compatible with the Intel 8080 and 8085 CPUs.

Each instruction is executed in steps that are usually termed machine cycles (M-cycles), each of which can take between three and six clock periods (T-cycles).[46] Each M-cycle corresponds roughly to one memory access and/or internal operation. Many instructions actually end during the M1 of the next instruction which is known as a fetch/execute overlap.

The Z80 machine cycles are sequenced by an internal state machine which builds each M-cycle out of 3, 4, 5 or 6 T-cycles depending on context. This avoids cumbersome asynchronous logic and makes the control signals behave consistently at a wide range of clock frequencies. It also means that a higher frequency crystal must be used than without this subdivision of machine cycles (approximately 2–3 times higher). It does not imply tighter requirements on memory access times, since a high resolution clock allows more precise control of memory timings and so memory can be active in parallel with the CPU to a greater extent, allowing more efficient use of available memory bandwidth.[citation needed]

One central example of this is that, for opcode fetch, the Z80 combines two full clock cycles into a memory access period (the M1-signal). In the Z80 this signal lasts for a relatively larger part of the typical instruction execution time than in a design such as the 6800, 6502, or similar, where this period would typically last typically 30-40% of a clock cycle.[citation needed] With memory chip affordability (i.e. access times around 450-250 ns in the 1980s[citation needed]) typically determining the fastest possible access time, this meant that such designs were locked to a significantly longer clock cycle (i.e. lower internal clock speed) than the Z80.

Memory was generally slow compared to the state machine sub-cycles (clock cycles) used in contemporary microprocessors. The shortest machine cycle that could safely be used in embedded designs has therefore often been limited by memory access times, not by the maximum CPU frequency (especially so during the home computer era). However, this relation has slowly changed during the last decades, particularly regarding SRAM; cacheless, single-cycle designs such as the eZ80 have therefore become much more meaningful recently.

The content of the refresh register R is sent out on the lower half of the address bus along with a refresh control signal while the CPU is decoding and executing the fetched instruction. During refresh the contents of the Interrupt register I are sent out on the upper half of the address bus.[53]

Zilog introduced a number of peripheral parts for the Z80, which all supported the Z80's interrupt handling system and I/O address space. These included the Counter/Timer Channel (CTC),[54] the SIO (Serial Input Output), the DMA (Direct Memory Access), the PIO (Parallel Input-Output) and the DART (Dual Asynchronous Receiver Transmitter). As the product line developed, low-power, high-speed and CMOS versions of these chips were produced.

PIO Z84C2008PEC

CTC Z84C3008PEC

SIO Z84C4008PEC

Like the 8080, 8085 and 8086 processors, but unlike processors such as the Motorola 6800 and MOS Technology 6502, the Z80 and 8080 had a separate control line and address space for I/O instructions. While some Z80-based computers such as the Osborne 1 used "Motorola-style" memory mapped input/output devices, usually the I/O space was used to address one of the many Zilog peripheral chips compatible with the Z80. Zilog I/O chips supported the Z80's new mode 2 interrupts which simplified interrupt handling for large numbers of peripherals.

The Z80 was officially described as supporting 16-bit (64 KB) memory addressing, and 8-bit (256 ports) I/O-addressing. All I/O instructions actually assert the entire 16-bit address bus. OUT (C),reg and IN reg,(C) places the contents of the entire 16 bit BC register on the address bus;[55] OUT (n),A and IN A,(n) places the contents of the A register on b8-b15 of the address bus and n on b0-b7 of the address bus. A designer could choose to decode the entire 16 bit address bus on I/O operations in order to take advantage of this feature, or use the high half of the address bus to select subfeatures of the I/O device. This feature has also been used to minimise decoding hardware requirements, such as in the Amstrad CPC/PCW and ZX81.

Mostek, who produced the first Z80 for Zilog, offered it as second-source as MK3880. SGS-Thomson (now STMicroelectronics) was a second-source, too, with their Z8400. Sharp and NEC developed second sources for the NMOS Z80, the LH0080 and µPD780C respectively. The µPD780C was used in the Sinclair ZX80 and ZX81, original versions of the ZX Spectrum, and several MSX computers, and in musical synthesizers such as Oberheim OB-8 and others. The LH0080 was used in various home computers and personal computers made by Sharp and other Japanese manufacturers, including Sony MSX computers, and a number of computers in the Sharp MZ series.[56]

Toshiba made a CMOS-version, the TMPZ84C00, which is believed[by whom?] (but not verified) to be the same design also used by Zilog for its own CMOS Z84C00. There were also Z80-chips made by GoldStar (alias LG) and the BU18400 series of Z80-clones (including DMA, PIO, CTC, DART and SIO) in NMOS and CMOS made by ROHM Electronics.

In East Germany, an unlicensed clone of the Z80, known as the U880, was manufactured. It was very popular and was used in Robotron's and VEB Mikroelektronik Mühlhausen's computer systems (such as the KC85-series) and also in many self-made computer systems. In Romania another unlicensed clone could be found, named MMN80CPU and produced by Microelectronica, used in home computers like TIM-S, HC, COBRA.

Also, several clones of Z80 were created in the Soviet Union, notable ones being the T34BM1, also called КР1858ВМ1 (parallelling the Russian 8080-clone KR580VM80A). The first marking was used in pre-production series, while the second had to be used for a larger production. Though, due to the collapse of Soviet microelectronics in the late 1980s, there are many more T34BM1s than КР1858ВМ1s.[citation needed]

Hitachi developed the HD64180, a microcoded and partially dynamic Z80 in CMOS, with on chip peripherals and a simple MMU giving a 1 MB address space. It was later second sourced by Zilog, initially as the Z64180, and then in the form of the slightly modified Z180[57] which has bus protocol and timings better adapted to Z80 peripheral chips. Z180 has been maintained and further developed under Zilog's name, the newest versions being based on the fully static S180/L180 core with very low power draw and EMI (noise).

Toshiba developed the 84 pin Z84013 / Z84C13 and the 100 pin Z84015 / Z84C15 series of "intelligent peripheral controllers", basically ordinary NMOS and CMOS Z80 cores with Z80 peripherals, watch dog timer, power on reset, and wait state generator on the same chip. Manufactured by Sharp as well as Toshiba. These products are today second sourced by Zilog.[58]

Zilog's fully pipelined Z80 compatible eZ80[59] with an 8/16/24-bit word length and a linear 16 MB address space was introduced in 2001. It exists in versions with on chip SRAM and/or flash memory, as well as with integrated peripherals. One variant has on chip MAC (media access controller), and available software include a TCP/IP stack. In contrast with the Z800 and Z280, there are only a few added instructions (primarily LEAs, PEAs, and variable-address 16/24-bit loads), but instructions are instead executed between 2 and 11 times as clock cycle efficient as on the original Z80 (with a mean value around 3-5 times). It is currently specified for clock frequencies up to 50 MHz.

Kawasaki developed the binary compatible KL5C8400 which is approximately 1.2-1.3 times as clock cycle efficient as the original Z80 and can be clocked at up to 33 MHz. Kawasaki also produces the KL5C80A1x family, which has peripherals as well as a small RAM on chip; it is approximately as clock cycle efficient as the eZ80 and can be clocked at up to 10 MHz (2006).[60]

The NEC uPD9002 was an hybrid CPU compatible with both Z80 and x86 families.

The Chinese Actions Semiconductor's audio processor family of chips (ATJ2085 and others) contains a Z80-compatible MCU together with a 24-bit dedicated DSP processor.[61] These chips are used in many MP3 and media player products.

The T80 (VHDL) and TV80 (Verilog) synthesizable soft cores are available from OpenCores.org.[62]

Non-compatible

The Toshiba TLCS 900 series of high volume (mostly OTP) microcontrollers are based on the Z80; they share the same basic BC,DE,HL,IX,IY register structure, and largely the same instructions, but are not binary compatible, while the previous TLCS 90 is Z80-compatible.[63]

The NEC 78K series microcontrollers are based on the Z80; they share the same basic BC,DE,HL register structure, and has similar (but differently named) instructions; not binary compatible.

The ASCII CorporationR800 was a fast 16-bit processor used in MSX TurboR computers; it was software, but not hardware compatible with the Z80 (signal timing, pinout & function of pins differ from the Z80).

Zilog's NMOS Z800 and CMOS Z280 were 16-bit Z80-implementations (before the HD64180 / Z180) with a 16 MB paged MMU address space; they added many orthogonalizations and addressing modes to the Z80 instruction set. Minicomputer features — such as user and system modes, multiprocessor support, on chip MMU, on chip instruction and data cache and so on — were seen rather as more complexity than as functionality and support for the (usually electronics-oriented) embedded systems designer, it also made it very hard to predict instruction execution times.[citation needed]

The Z80A was used as the CPU in a number of gaming consoles, such as this ColecoVision.

During the late 1970s and early 1980s, the Z80 was used in a great number of fairly anonymous business-oriented machines with the CP/M operating system, a combination that dominated the market at the time.[67][68] Four well-known examples of Z80+CP/M business computers are the portable Osborne 1, the Kaypro series, the Epson QX-10 and the Heathkit H89. Research Machines manufactured the 380Z and 480Z microcomputers which were networked with a thin Ethernet type LAN and CP/NET in 1981. Other manufacturers of such systems included Televideo, Xerox (820 range) and a number of more obscure firms. Some systems used multi-tasking operating system software (like MP/M) to share the one processor between several concurrent users.

In the U.S., the Radio ShackTRS-80, introduced in 1977, as well as the Models II, III, 4, and the proposed Model V, used the Z80. A number of TRS-80 clones were produced by companies like Lobo (Max-80), LNW (LNW-80), and Hong Kong-based EACA (Video Genie and derivatives TRZ-80, PMC-80, and Dick Smith System 80). In the Netherlands a TRS-80 Model III clone was produced that had CP/M capability; this was the Aster CT-80. In the United Kingdom, Sinclair Research used the Z80 and Z80A in its ZX80, ZX81, and ZX Spectrum home computers. These were marketed in the USA by Timex as the Timex/Sinclair series. Amstrad used the Z80 in their Amstrad CPC and PCW ranges and an early UK computer, the Nascom 1 and 2 also used it. The Z80 powered a great many home computers adhering to the MSX standard in Japan, Asia, and to a lesser extent, Europe and South America (some 5 million in Japan alone). Also in Japan Sharp used the Z80 in its MZ and X1 series. In Germany an Apple-CP/M hybrid called the Base 108 paired a Z80 with a 6502. Similarly the Commodore 128 featured a Z80 processor alongside its MOS Technology 8502 processor for CP/M compatibility.[69] Other 6502 architecture computers on the market at the time, such as the BBC Micro, Apple II,[70] and the 6510 based Commodore 64,[71] could make use of the Z80 with an external unit, a plug-in card, or an expansion ROM cartridge. The MicrosoftZ-80 SoftCard for the Apple II was a particularly successful add-on card and one of Microsoft's few hardware products of the era.

In 1981, Multitech (later to become Acer) introduced the Microprofessor I, a simple and inexpensive training system for the Z80 microprocessor. Currently, it is still manufactured and sold by Flite Electronics International Limited in Southampton, England.

Nintendo's Game Boy and Game Boy Color handheld game systems used an 8080-derived processor with some Z80 instructions added (CB prefix) as well as unique auto-increment/decrement addressing modes. The CPU was a Sharp Corporation LR35902[82] running at 4.19 MHz in the original and Pocket models, and 8.39 MHz in the Color model. This processor was later included in the Game Boy Advance / SP / Micro taking up a new role as a co-processor for backwards compatibility with Game Boy / Color games (except Micro) and to add legacy 8-bit sounds to supplement the digital samples in Game Boy Advance games.

In Russia, Z80 and its clones were widely used in multi-functional land line phones with Caller ID.

Several polyphonicanalog synthesizers used it for keyboard-scanning (also wheels, knobs, displays...) and D/A or PWM control of analog levels; in newer designs, sometimes sequencing and/or MIDI-communication. The Z80 was also often involved in the sound generation itself, implementing LFOs, envelope generators and so on. Known examples include:

^ abThe Seybold report on professional computing. Seybold Publications. 1983. In the 8-bit world, the two most popular microcomputers are the Z80 and 6502 computer chips.

^Zilog actually included several "traps" in the layout of the chip to try to delay this copying. According to Faggin, a NEC engineer later told him it had cost them several months of work, before they were able to get their μPD780 to function.

^Although the 8080 had 16-bit addition and 16-bit increment and decrement instructions, it had no explicit 16-bit subtraction, and no overflow flag for 16-bit operations. The Z80 complemented this with the ADC HL,rr and SBC HL,rr instructions which sets the overflow flag accordingly.

^ abWai-Kai Chen (2002). The circuits and filters handbook. CRC Press. p. 1943. ISBN978-0-8493-0912-0. interrupt processing commences according to the interrupt method stipulated by the IM i, i=0, 1, or 2, instruction. If i=1, for direct method, the PC is loaded with 0038H. If i=0, for vectored method, the interrupting device has the opportunity to place the op-code for one byte . If i=2, for indirect vector method, the interrupting device must then place a byte . The Z80 then uses this byte where one of 128 interrupt vectors can be selected by the byte .

^Notably to simultaneously handle the 32-bit mantissas of two operands in the 40-bit floating point format used in the Sinclair home computers. They were also used in a similar fashion in some earlier but lesser known Z80 based computers, such as the Swedish ABC 80 and ABC 800.

^As this refresh does not need to transfer any data, just output sequential row-adresses, it occupies less than 1.5 T-states. The dedicated M1-signal (machine cycle one) in the Z80 can be used to allow memory chips the same amount of access time for instruction fetches as for data access, i.e almost two full T-states out of the 4T fetch cycle (as well as out of the 3T data read cycle). The Z80 could use memory with the same range of access times as the 8080 (or the 8086) at the same clock frequency. This long M1-signal (relative to the clock) also meant that the Z80 could employ about 4-5 times the internal frequency of a 6800, 6502 or similar using the same type of memory.

^Jump (JP) instructions, which load the program counter with a new instruction address, do not themselves access memory. Absolute and relative forms of the jump reflect this by omitting the round brackets from their operands. Register based jump instructions such as "JP (HL)" include round brackets in an apparent deviation from this convention."Z80 Relocating Macro Assembler User's Guide"(PDF). p. B–2.

^ ab"Z80 CPU Introduction". Zilog. 1995. It has a language of 252 root instructions and with the reserved 4 bytes as prefixes, accesses an additional 308 instructions.

^Sanchez, Julio; Canton, Maria P. (2008). Software Solutions for Engineers And Scientists. Taylor & Francis. p. 65. ISBN978-1-4200-4302-0. The 8-bit microprocessors that preceded the 80x86 family (such as the Intel 8080, the Zilog Z80, and the Motorola) did not include multiplication.

^The Z80 redefines the P (parity) flag of the 8080 as P/V (parity/overflow), and arithmetic instructions on the Z80 set it to indicate overflow rather than parity. Also, bit 1 of the F (flags) register, unused on the 8080, is defined on the Z80 as N, a flag that indicates whether the last arithmetic instruction executed was a subtraction or addition, and the Z80 DAA instruction checks the N flag and behaves differently in the latter case, so a subtraction followed later by DAA will yield a different result on a Z80 than on an 8080.

^ abBot, Jacco J. T. "Z80 Undocumented Instructions". Home of the Z80 CPU. If an opcode works with the registers HL, H or L then if that opcode is preceded by #DD (or #FD) it works on IX, IXH or IXL (or IY, IYH, IYL), with some exceptions. The exceptions are instructions like LD H,IXH and LD L,IYH

^Young, Sean (1998). "Z80 Undocumented Features (in software behaviour)". The I/O instructions use the whole of the address bus, not just the lower 8 bits. So in fact, you can have 65536 I/O ports in a Z80 system (the Spectrum uses this). IN r,(C), OUT (C),r and all the I/O block instructions put the whole of BC on the address bus. IN A,(n) and OUT (n),A put A*256+n on the address bus.

^Electronic Business Asia. Cahners Asia Limited. 1997. p. 5. Kawasaki's KL5C80A12, KL5C80A16 and KL5C8400 are high speed 8-bit MCUs and CPU. Their CPU code, KC80 is compatible with Zilog's Z80 at binary level. KC80 executes instructions about four times faster than Z80 at the same clock rate

^Hyder, Kamal; Perrin, Bob (2004). Embedded systems design using the Rabbit 3000 microprocessor. Newnes. p. 32. ISBN978-0-7506-7872-8. The Rabbit parts are based closely on the Zilog Z180 architecture, although they are not binary compatible with the Zilog parts.

^Holtz, Herman (1985). Computer work stations. Chapman and Hall. p. 223. ISBN978-0-412-00491-9. and CP/M continued to dominate the 8-bit world of microcomputers.

^Dvorak, John C. (10 May 1982). "After CP/M, object oriented operating systems may lead the field". InfoWorld. Vol. 4 no. 18. InfoWorld Media Group. p. 20. ISSN0199-6649. The idea of a generic operating system is still in its infancy. In many ways it begins with CP/M and the mishmash of early 8080 and Z80 computers.

^Byte. McGraw-Hill. 1986. p. 274. C-128 CP/M uses both the Z80 and 8502 processors. The Z80 executes most of the CP/M BIOS functions.

^Daniel Sanchez-Crespo Dalmau (2004). Core techniques and algorithms in game programming. Indianapolis, Ind.: New Riders. p. 14. ISBN978-0-13-102009-2. Internally, both the NES and Master System were equipped with 8-bit processors (a 6502 and a Zilog Z80, respectively)