PHYSICAL VERIFICATION

DURATION - 10 weeks

STARTS FROM - 23rd June 2019

Course Overview:

Physical Verification (PV) is an essential process in the Chip Design cycle both in Analog, and Digital design flows, wherein IC Layout or Routed Design is checked for manufacturing rules criteria as specified by the foundry.

Physical Verification includes Design Rule Checks (DRC), Layout Versus Schematic (LVS), Electrical Rule Checks (ERC), Antenna Checks, DFM, ESD, Latch-up and various integration flows at SOC level. EDA tools are used to check these complex rules and fix the violations using the layout editor tools. Physical Verification is a critical part of the sign-off checks for IC design before tapeout, to be manufactured in the foundry.

Typically PV checks are done by Physical Design (PD) engineers in digital designs and by Layout engineers in Analog designs. However, some many companies have dedicated PV engineers as part of their work methodologies.

In latest technology nodes, particularly 7nm and below with FINFET technology being used, PV has become more involved with more number of rules to verify, and this has opened up a good amount of job opportunities for PV engineers in the VLSI industry.

ChipEdge is the first training institute to offer a dedicated PV course, designed as per the latest industry requirements and delivered by a senior engineer, who has substantial experience in Physical Verification. It gives full exposure to an engineer over layout concepts and flows, accepted by the industry.

The course will have 70% hands-on labs and 30% lecture sessions.

Training Delivery Model:

Weekends (Saturdays): Instructor Lead classroom training

Each Lecture session will be followed by Labs on that module.

Weekdays: Lab support through Email and WhatsApp

Flexible learning with 24/7 Lab Access from home through VPN

Training Material & Certification:

Handouts of training material will be provided.

Course completion certificate from ChipEdge.

Who Can Attend This Course:

Diploma Engineers working in Embedded / Electronics (PCB designing, assembling, testing..) and interested to Change Career into VLSI industry for work satisfaction & Career growth.

B.Sc or M.Sc graduates looking to start a career in VLSI.

Interns / Entry level PV Engineers, who have started working on Physical Verification, but not received any formal training.

Engineers working in different domains of VLSI, but interested in pursuing a career in Physical Verification.

Pre-requisites:

Good Knowledge on below topics is required. One needs to refresh his/her knowledge thoroughly, before the course as these fundamentals are essential to the Course.

Working knowledge of Linux.

Knowledge of Digital Electronics Fundamentals.

Knowledge of CMOS fundamentals

Educational Qualification:

Diploma in Electronics / Electrical / Instrumentation

B.Sc / M.Sc in Electronics

B.E / B.Tech in Electronics / Electrical / Instrumentation / Telecom

Course Content outline:

1) UNIX Fundamentals

2) Layout Basics

Fabrication Process

CMOS Basics

ESD

Latchup

Antenna/Gnac

3) TCL Basic Concepts

4) SOC Basic

DFM

Cell Structures

Density

5) Introduction to PD Flow

6) PV Introduction

DRC

LVS Other essential Industry flows

ERC

7) ICC Introduction

8) Physical Verification Project -1

9) Physical Verification Project -2

10) Soft Skill: Work Management & Daily Tracker/Task Planning

Tools to be used:

Synopsys IC Compiler (ICC), IC Validator (ICV)

Additional Lab Hours through VPN, to enable you to spend more time on labs from home. This is on top of Trainer led lab sessions during Sundays.

Assessment & Certification:

Course completion certificate from ChipEdge.

At the end of the course, Course learning will be assessed as per Bloom’s Taxonomy.

Trainer:

The trainer is a working professional with 7+ years of experience in Analog Layout Design, SOC Physical Verification & Circuit Design. He has worked on memories, standard cells, Analog & Mixed signal Layouts, IO Circuit & Layout Design, Test Chips and SOCs with experience on technology nodes varying from 10nm to 180nm.