Experts At The Table: How To Improve IP Quality

Semiconductor Engineering sat down to discuss the best ways to improve the quality of design IP with Piyush Sancheti, vice president of product marketing at Atrenta; Chris Rowen, Cadence Fellow and former CTO at Tensilica; Gene Matter, senior applications manager at Docea Power; Warren Savage, president and CEO of IPextreme; and Dan Kochpatcharin, deputy director of IP portfolio marketing at TSMC. What follows are excerpts of that conversation. For Part One, click here. For Part Two, click here.

SE: If we have an IP quality standard driven by the foundries, are there concerns on the customer side that it should be a more independent determination? Savage: I’m seeing a lot of customers that pick the foundries towards the end. They are looking at what IP is needed for their application – soft IP, processors, things like that – that will port to any process. But maybe there is some specialized IP that meets a particular automotive standard, it has some right certifications and that might be only available from special foundries or might be in volume at TSMC or someplace like that. At the end, the IP is actually kind of driving the technology of choice just because it’s available there, it has silicon heritage that the customer can trust the quality of it.Sancheti: Having talked to a lot of our customers, IP availability is a key part of the foundry selection and there are established scenarios within the industry where the reason to go to a vendor was the rich, high quality IP portfolio. From that standpoint, as far as concerns by engineers, I think there is more the awareness and the desire that we need to fix this problem. Problem sounds too harsh, maybe, but there are up and coming IP vendors who don’t necessarily have that same level of rigor in their development and sign-off process. From that standpoint, there is always some concern about, ‘I’m introducing a new piece of IP into what is otherwise a fairly stable, fairly mature portfolio.’ It only takes one bad apple to make the thing fall apart.Matter: Experienced engineers and design folks are highly concerned about taking on too much risk. If I’m going to be in the middle of vendor process selection for a new fab or process node and a new microarchitecture, I’m going to view that as a Richter Scale 10 risk level. If indeed I have an existing design which I’m going to add some new intellectual property and it’s hard IP that’s circuit level and it’s a new technology, I will focus my attention, my paranoia, my energy on the things that are new and that allows me to reduce my level of risk and therefore my level of comfort to innovate or take risks or whatever. And indeed, I’m going to focus most of this stuff on the new IP selection.

SE: I’ve heard that the definition of ‘reuse’ is possibly a misnomer – that with so much changing all the time, nothing stays the same. Kochpatcharin: From an objective standpoint, because we track all of the partners IP, and just from a reusability perspective, we see some of the IPs being reused 10 or 20 different times with no changes. So we do see the IP being reused caused by the different product lines. With the hard IP we do see it being reused across multiple customers and multiple different product lines. Rowen: I think that there are some fundamental changes taking place in the nature of the SoC design companies and the semiconductor guys which is driving a fundamental redefinition of IP and IP reuse. That fundamental change is that they are moving up inevitably that the system companies have been hollowed out but are relying on more and more sophisticated system solutions – hardware and software – coming from their supplier, the chip guy. And for the chip guy, more and more of the innovation is in how they put it together – what subsystems they use, what software they put on it, what’s the whole experience beyond the pins of the chip they are creating. And that is creating a bigger and bigger opportunities for IP suppliers because if the semiconductor companies are moving up and dealing with these system-level issues, it is economically attractive for them to be able to outsource, if you will, more of the gory details on some of the bits inside. So rather than buying little blocks of 10 to 100 k gates in digital terms, they are buying rather complete subsystems that may be 1,000,000 gates or 10,000,000 gates. When you think about this in the context of system-on-chip, when it was small blocks driven by industry-official standard interfaces of course those things had to remain constant, at least on the outbound side and so reuse was quite natural because all that block did was talk that particular industry-standard interface. As you integrate more and more into a subsystem, then it reflects more and more of the function of this end product – it has to do more and it’s not just driven by an external standard. It’s, how does it fit in with the other subsystems? It’s, how does it contribute to the differentiation of this platform? So there’s a new challenge for the IP business which is not just how do we do reuse, but how do we do something that delivers what the customer wants and needs, which has the same quality and economic characteristics as pure, simple reuse. Pumped it out of mass production, but which allows for that configuration or extension or re-adaptation to what that customer needs. I think all of us have dealt a long time with configurability of different kinds of IP blocks, particularly on the inbound side of IP but it’s clearly taken on a whole new character. Matter: I think there are certain benchmarks for reuse. You could say within the design flows that I’m dealing with, we look at some reuse relatively to say, copy exact, do not touch this block. In other words, I’m going to give to you a complete IP solution that you implement that has the same socket interfaces and so forth and you can reuse this across a variety of products – it’s great for proliferation. So, on a given process node in a family of SoCs, the designer can spit out 20 or 50 variations of that part: one for the low cost market segment, maybe one for embedded, one for the consumer segment, etc., etc., etc. of which there is a large collection of intellectual property within the company there that is reused. And it is reusable and it’s a mandate because there’s no way you can possibly generate that many proliferation products without doing derivatives with exact reuse. However when you talk about reuse at another spectrum, building multilingual PHYs on each process node, and these multilingual PHYs talk everything: SATA, USB, USB 3, PCI-Express, etc., etc., and each one of these must conform to an electrical standard on the outside and must conform to a set of interfaces to the logic arrays that are driving it – the host controllers, etc., that are driving this. There’s a high degree of reuse that’s mandated by that because there’s no way you can use this hard macro unless you do that.

SE: As the sophistication of customers is increasing, what does this mean for the IP provider? Rowen: That’s good news. The ability to go satisfy the expectations of a customer is just enhanced enormously if those expectations are detailed, appropriate and well communicated to us. The biggest challenge in terms of satisfying customer expectations is if their expectations are variable or unclear about what they’re looking for and we love nothing better than to have a discussion about requirements and quality with someone who has considerable clarity about what they’re trying to accomplish and what that means in terms of what the functionality is that they’re looking for. There’s no question that that’s good news. Matter: I like nothing better than to be grilled and actually go through the accountability because at that point, I do believe I have a higher likelihood of satisfying those requirements with fewer surprises than just going out and promising the moon. I would like to under-commit and over-deliver than the other way around and ideally what you want. If you have a very sophisticated customer, your commitment and your delivery will match well within expectations or reason. I think that’s a huge metric to really look at: what is the level of commitment that is being asked of you. What is your level of confidence in terms of fulfillment on that? Given that there are surprises and given you’d like to innovate and actually deliver a little bit more – because that’s what raises the bar. That’s what actually gets your customer coming back to you is when you delight them; when you provide something above and beyond the commitment and their expectation that gives them something more. And with respect to IP, that’s a big deal. Most of the engineers I know don’t want to sit there and view themselves as an assembly block of Legos. It’s somewhat demeaning because where’s their value-add to that process? Kochpatcharin: It’s good for us as well in terms of the chip being ramped quickly, less issues and problems. We also do see certain types of customers that are more sophisticated but there are new fabless semiconductor companies coming up quickly as well, especially in China. Those may not be as sophisticated as the U.S. customer. I think those guys expect an IP ecosystem and a foundry to provide them enough information so that they can understand how the IP will work.

SE: It seems that we are at a pretty good point today in terms of the industry striving for IP quality. What needs to happen to take it to the next level? Savage: I think the bar is moving. It’s moving at different rates in different regions and emerging countries of high tech have a different level of sophistication but the other regions are driving the level of sophistication of IP providers up to a level that used to be at the systems companies. Those chip companies are now becoming big systems companies, almost software companies. Software is driving content in semiconductors. It shifts the value chain around a bit over time, and it shifts the level of expertise required within IP companies to be increasingly software oriented as part of the IP offering. Rowen: I agree strongly that software content, software expectations, software quality is the new dimension of the semiconductor IP business. As we’re doing more processor-based, certainly more subsystem IP, the software content is clearly a lot of the total intellectual content of it and it requires this intimate knowledge of the architecture of the IP and of the end application. Very often for many of these customers – not perhaps so much Tier One, but Tier Two and Tier Three – they are relying on the semiconductor IP company for their software content. Those customers expect the IP supplier to know more about the end application and the software standards than even they do, in a given domain. That means we have to go figure out the software quality side, which is a bit different because the nature of what’s a bug, what are the mechanisms of interoperability, how does it tie into operating systems, how does it track what Google is doing – all of these things are completely new dimensions for many semiconductor IP companies. It’s opening up a whole new vista with its own set of landmines.