Comments

Hello all,
Attached patch adds support for secondary SMBus of AMD SB800 and new AMD FCH
chipsets. The base address of secondary SMBus is different from SB700 and it is
stored on similar place as SB800 primary SMBus.
More verbose info:
Probing function was just modified to read the SMBus base from address 0x28 or
from original 0x2c. The secondary bus does not provide IRQ information.
I think the SB700 has same secondary controller, so revision/IRQ information
should not be printed too. This can be fixed in some other patch.
Chipset datasheet can be found here:
http://support.amd.com/us/Embedded_TechDocs/45482.pdf
Tested on SB800 and FCH boards.
Tested-by: Paul Menzel <paulepanter@users.sourceforge.net>
ASRock E350M1 with SB800
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Thanks
Rudolf

> Do you know if there should be something connected?
In Paul case, most likely not. In my case there is a voltage controller for the
DDR3 voltage regulator. I asked Paul test it on his SB800 system, I have the
Hudson successor..
>> Rudolf, it looks like your patch could also update the i2c files under>> `Documentation`. At least there are some patches doing that.>> Do you mean 'busses/i2c-piix4'?
Yes he means that. I will add documentation to the patch.
Thanks
Rudolf
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On Tue, Jun 11, 2013 at 09:47:12PM +0200, Rudolf Marek wrote:
> >Do you know if there should be something connected?> > In Paul case, most likely not. In my case there is a voltage> controller for the DDR3 voltage regulator. I asked Paul test it on> his SB800 system, I have the Hudson successor..> > >>Rudolf, it looks like your patch could also update the i2c files under> >>`Documentation`. At least there are some patches doing that.> >> >Do you mean 'busses/i2c-piix4'?> > Yes he means that. I will add documentation to the patch.
OK, so I will wait for V2. Thanks!