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Description

General Description:I0 pins driven by GND in a Virtex design may initialize incorrectly to1 instead of 0.

This may be due to a problem in the 3.1i Mapper which results in an incorrectNGM file. When the NGM file is subsequently read in as an input to NGDANNOduring the process of generating a backannotated timing simulation netlist, the resultingsimulation netlist may contain instances where inputs that are supposed to bedriven by 0 are driven by a 1 instead.

The problem is associated with an Virtex or Virtex-II LUT that is configured as a buffer,with the least significant LUT input pin, I0, driven by GND. The GND connection mayhave been specified by the user, or it may be preconfigured in a CORE Generator core'sEDIF netlist in response to some user-specified INIT value.

The problem has been observed in the Virtex Accumulator, Adder/Subtracter,and FD-based Register).

Solution

The workaround is to omit the NGM file when running NGDANNO to work around this bug.

If you are processing the design through Design Manager, de-select the switch for "Correlate Simulation Data to Inpur Design".