Sunday, December 16, 2012

I am doing work on a KC705 evaluation board from Xilinx. This chip (Kintex 7) uses the 7 Series Integrated Block for PCI Express. I am running this on a Gigabyte GA-Z77X-UP5 TH board. I have run into a brick wall trying to get this Xilinx board to work on this Gigabyte motherboard. Luckily, there is a note from Xilinx about this:http://www.xilinx.com/support/answers/51135.htmIn short, there is a workaround. Check out this page, which tells you to set the TX_RXDETECT_REF signal to 3'b011 instead of the default. The Answer Record also explains that this is due to an errata on Ivy Bridge cores. It points to a web page by Intel and indicates that it is errata BV56.http://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/3rd-gen-core-desktop-specification-update.pdfI don't understand the errata, but I can attest to the fact that this fixes the problem. The KC705 is now successfully detected on this motherboard.
UPDATE: If you take a look at
http://www.xilinx.com/support/documentation/boards_and_kits/kc705_PCIe_pdf_xtp197_14.2.pdf
you can see that by setting the Bitstream Configuration, and by adding an emcclk you can accomplish a PCIe compliant FPGA load-time. This method doesn't need a soft-reboot to properly enumerate the bus.

See note above, kept for accuracy:
Even with this success, there are still some failures... For example, the load time for the FPGA configuration is too long. This means that I have to do a soft-reboot after a hard reboot to get the PCIe link to work. Xilinx has created a method to solve this, but I have yet to figure it out. It is called Tandem PROM and Tandem PCIe. It is supposed to quickly load the PCIe portion, negotiate the link, and then load the rest.