In order to overcome disadvantages of existing centralized network management systems that use simple objects, dynamic object platforms are proposed as alternative systems. So the distributed network management systems are implemented using various distributed platform such as CORBA and Java-RMI. Subsequently mobile agent-based platforms are proposed. The mobile agent-based platform can additionally provide flexibility and scalability to network management system that CORBA or Java-RMI based platforms do not support. In this paper, we address an architecture to solve the problem of the occurrence of additional traffic by using mobile agent and to save resources of network element. Our proposal in this paper is an efficient network management architecture using motile agents. And we make use of mobile agents for minimizing of traffic that can happen when mobile agents moves. Also we design agents using information architecture of TMN for efficient resource management of network element and improvement of operation performance.

In this paper, we propose a new hybrid type of the routing protocol (Virtual Cluster-based Routing Protocol: VCRP) for mobile ad-hoc networks, based on a virtual cluster, which is defined as a narrow-sense network to exchange the basic information related to the routing among the adjacent nodes. This particular approach combines advantage of proactive routing protocol (PRP), which immediately provides the route collecting the network-wide topological and metric information, with that of reactive routing protocol, which relies on the route query packet to collect the route information on its way to the destination without exchanging any information between nodes. Furthermore, it also provides the back-up route as a byproduct, along with the optimal route, which leads to the VCBRP (Virtual Cluster-based Routing Protocol with Backup Route) establishing the alternative route immediately after a network topology is changed due to degradation of link quality and terminal mobility, Our simulation studies have shown that the proposed routing protocols are robust against dynamics of network topology while improving the performances of packet transfer delay, link failure ratio, and throughput over those of the existing routing protocols without much compromising the control overhead efficiency.

The network-wide performance management is crucial for maintaining the quality of network services, which requires the collection and monitoring the performance data at individual network nodes. Most of the public networks, however, are composed of diverse, heterogeneous network nodes that are managed by various types of proprietary management systems with a conventional operator console and embedded management functions, which makes it difficult to implement the integrated performance management systems. Even though the developments of TMN (Telecommunication Management Network) based management systems are being attempted, the little work has been done in performance management area. In this paper, we propose the performance monitoring architecture for ATM switches using the 0₃ object model and describe how to implement the TMN-based performance prosy agent for ATM switching systems. The proposed performance proxy agent provides the TMN standard performance management interfaces by translating the proprietary performance management functions, which eventually leads to network-wide integrated performance management.

In this paper, we relatively differentiate maximum delay for each Assured Service subclass in Differentiated Services by allocating bandwidth to each subclass differently. To maximize the throughput for the In-profile traffic and the link utilization, we propose a Cofiguration method of RIO and the admission control criterion based on the buffer size determined by the network topology and the ratio of bandwidth allocated to each subclass. Simulation results show that the proposed method can calculate the capacity to guarantee the QoS for the Assured Service and maximize the throughput for the In-profile traffic and the link utilization by applying the RIO parameter values set through the proposed configuration method.

In this paper, we proposed an Adaptive RIO scheme to solve the problem of RIO scheme that occurs when admission control is performed for QoS guarantee of Assured Service in Differentiated Services. To prevent an early random drop of the admitted In-profile packet, proposed Adaptive RIO scheme updates parameters of RIO scheme every time interval according to the estimated numbers of maximum packet arrivals of In-profile traffic and total traffic during the next time interval. The numbers of maximum packet arrivals during the next time interval are estimated based on the buffer size determined by the network topology and the ratio of bandwidth allocated to each subclass. We found from simulation results that, compared with RIO scheme, proposed Adaptive RIO scheme can improve performance of the throughput for In-profile traffic when admission control is performed or congestion occurs.

A data manipulation unit capable of bit partitioned shift and various multimedia data type conversions in addition to conventional shift, is presented. Utilizing the similarity between the data type conversion and the shift, the addition of small amount of interconnections to conventional barrel shifter enables data type conversion as well as shift operations with minimal hardware overhead. The presented data manipulation unit is composed of the shifter block for conventional shift and a pack and a unpack block. It has been designed with verilog HDL and the VLSI implementation results using compass 0.6 um standard cell are discussed.

The efficient Viterbi decoder that supports full data-rate output of DAB system was proposed. Viterbi decoder consumes lots of computational load and should be designed to be fast specific hardware. In this paper, SST scheme was adopted for Viterbi decoder with puncturing to reduced the power consumption. Puncturing vector tables are modified and re-arranged to be designed by a hardwired logic to save the system area. New re-scaling scheme which uses the fact that the difference of the maximum and minimum of the path metric values is bounded is proposed. The proposed re-scaling scheme optimizes the wordlength of path metric memory and greatly reduces the computational load for re-scaling by controlling MSB of path metric memory. Another saving of computation is done by proposed algorithm for branch metric calculation, which makes use of pre-calculated metric values. The designed Viterbi decoder was synthesized using SAMSUNG 0.35 standard cell library and occupied small area and showed lower power consumption.

This paper presents a new image retrieval method that is based on color space and block region information. The color space information of images can be obtained by color binary set, and the block region information can be obtained by regional segmentation and feature. The candidate images are decided by comparing with color features and its binary set of query image and image feature database for retrieval. Particularly, it is possible that the retrieval using similarity-measurements has the weights of color spatial distribution arid its objective block region features. This retrieval method using color spatial and block region features is shown with the effectiveness on the result of implementation on image database with 6,000 images.

In this paper, a novel architecture of programmable divider with fifty percent duty cycle output and programmable dividing number has been proposed. Through HSPICE simulation, a 900MHz frequency synthesizer with proposed (sequency divider has designed in a standard 0.25㎛ CMOS technology To verify the operation of proposed frequency divider, a chip had been fabricated using 0.65㎛ 2-poly, 3-metal standard CMOS processing and experimental result shows that the proposed frequency divider works well. The designed voltage controlled oscillator(VCO) has a center frequency of 900MHz a tuning range of 10%, and a gain of 154HHz/V. The simulated frequency synthesizer performance has a settling time of 1.5s, a frequency range from 820MHz to IGHz and power consumption of 70mW at 2.5V power supply voltage.

This paper presents a MSB-first digit-serial systolic array for computing modular multiplication of A(x)B(x) mod G(x) in finite fields . From the MSB-first multiplication algorithm in , we obtain a new data dependence graph and design an efficient digit-serial systolic multiplier. For circuit synthesis, we obtain VHDL code for multiplier, If input data come in continuously, the implemented multiplier can produce multiplication results at a rate of one every [m/L] clock cycles, where L is the selected digit size. The analysis results show that the proposed architecture leads to a reduction of computational delay time and it has much more simple structure than existing digit-serial systolic multiplier. Furthermore, since the propose architecture has the features of unidirectional data flow and regularity, it shows good extension characteristics with respect to m and L.

To reduce the area and power consumption in constant coefficient multiplications, the constant coefficient can be encoded using canonic signed digit(CSD) representation. When the partial product terms are added depending on the nonzero bit(1 or -1) positions in the CSD-encoded multiplier, all sign bits are properly extended before the addition takes place. In this paper, to reduce the overhead due to sign extension, a new method is proposed based on the fact that carry propagation in the sign extension part can be controlled such that a desired input bit can be propagated as a carry. Also, a fixed-width multiplier design method suitable for CSD multiplication is proposed. As an application, 43-tap filbert transformer for SSB/BPSK-DS/CDMA is implemented. It is shown that, about 16∼28% adders can be saved by the proposed method compared with the conventional methods.