Consumer demand for greater functional integration in wireless and Internet-enabled products drives an increased adoption of CMOS and SiGe technologies for high-performance circuit design. This leads to a beneficial reduction in device footprint, cost, and power consumption but dramatically increases devices counts (10x to 100x). These larger, more complex circuits require detailed circuit simulation including transistor (SPICE) level accuracy to properly capture the analog/RF behavior at the higher operating frequencies. In addition, time-domain (transient) and frequency-domain (harmonic balance) simulations must be performed from the identical circuit netlist using the identical device models to guarantee consistent results.

Nexxim from Ansoft represents the "next state-of-the-art" for detailed circuit simulation and verification for a new generation of complex high-performance ICs. Nexxim delivers orders of magnitude improvement in simulation speed, accuracy, and capacity. Nexxim combines with Ansoft Designer and HFSS to provide a total solution for circuit design, circuit/system co-design, and post-layout verification including on-chip/embedded passives.

The table illustrates the performance advantage of Nexxim relative to current tools. As shown in Fig. 1, the software is designed for large, complex circuits: Nexxim's simulation speed advantage increases as the number of harmonics and number of transistors in the circuit increase; in other words, the larger the problem, the greater Nexxim's performance advantage. Likewise, Nexxim demonstrates a much steeper "accuracy versus simulation time" curve than existing tools; its speed advantage increases as the required solution accuracy increases.

Nexxim is easily incorporated in the typical IC design flow to perform circuit analysis (Fig. 2). A netlist describing a circuit of interest at its pre-layout verification phase can be exported from within a design environment and imported into Nexxim for solution. The same applies for the post-layout verification phase; the extraction of local parasitics, crosstalk, interconnect delays, and substrate noise add significantly more elements to the design and augments the netlist size. This netlist can be also exported from within the design environment and imported into Nexxim for solution.

An example of the different designs tackled by Nexxim is an analog-to-digital converter (ADC), where the effects of layout parasitics, substrate coupling and packaging result in a large circuit that includes tens of thousands of transistors and passive elements to be accurately analyzed (Fig. 3). Even for a circuit of this complexity, Nexxim's large capacity and fast speed provide transient solutions within minutes, allowing large parametric simulation runs to be performed within a reasonable time frame. As a result, thermal effects and process variations can be taken into account to ensure that the most optimal design architecture is used during an IC process run.

Even a small design such as a 100-MHz frequency divider with 14 active devices provides a challenge for frequency-domain simulations using current CAE tools. The output of the divider approximates a square wave, requiring the use of many harmonics for accurate characterization. By performing single-tone and multi-tone harmonic balance analyses that incorporate Krylov subspace methods, Nexxim can simulate the performance of the frequency divider quickly and accurately. Proprietary preconditioning algorithms help achieve fast convergence, and a multi-tone harmonic-balance simulation can be run with an option that uses minimal memory (often a cause for concern in circuits with many variables and harmonics).

The speed of Nexxim is apparent in the simulation of a phase-locked loop (PLL). Using current tools, about two days are needed to simulate the performance of a 430-MHz PLL circuit on a 0.15-µm CMOS process, even if the lock voltage and frequency are set very close to their final values during simulation. Nexxim uses a new variable-time-step integration formula combined with advanced error estimation and control to decrease the solution time five times to provide greater accuracy while requiring fewer time points over the simulation time interval. A new sparse matrix solver specifically optimized for circuit simulation applications speeds solutions for all time points.

For high-level designs, the combination of Nexxim and Ansoft Designer allows operators to literally "toggle" between aspects of a circuit. Ansoft Designer's system simulator can be used to size the various system components and Nexxim can be applied to "fine-tune" the design, by performing detailed and accurate circuit-level analysis of each of the components at high simulation speed. The combination was applied to the co-design of an integer-N PLL based on a 0.25-µm CMOS process (for GSM 1800). Ansoft Designer simplifies the sizing of the prescaler residing in the PLL's counter, while Nexxim handles the analysis of the prescaler at the circuit level. The overall circuit contains 182 BSIM3v3.2 transistors, readily available from Nexxim's extensive device model library. Nexxim is compatible with the golden standards in device models and netlist formats. It also provides designers with the capability of rapidly incorporating their own proprietary models; their run-time efficiency matches that of already existing, built-in models so as to not compromise simulator performance. Simulation of the prescaler using Nexxim takes a few seconds and quickly exposes the need for a preamplifier to be added in the design so that the output signal is sufficient to drive the divider core (the red solid line in Fig. 4). This design complication was not apparent from the system-level simulation results.

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At the circuit level, Nexxim can be also used for the VCO used with the PLL (Fig. 5). It performs time-domain (transient) and frequency-domain (harmonic balance, AC) simulations using the same circuit schematic/netlist and the same device models across analysis domains. This guarantees that results in the different domains are consistent so that the steady-state transient response is in agreement with the harmonic balance solution. Consequently, designers do not have to spend countless hours reconciling circuit responses from different simulators, running from different netlists, using different versions of device models.

After verifying the performance of the individual PLL functional blocks, the whole system is brought together into one circuit and Nexxim is used to verify the overall PLL response. Nexxim takes approximately 19 h to run a transient simulation within 20-µs of the whole system. This is faster, more accurate and without the large waveform discontinuities present in the results of current simulations tools, which take over a week to produce a result.

Given continuing expansion of wireless applications, and with technology scaling down towards 90- and 65-nm feature sizes, accurate simulations must include noise and electromagnetic (EM) effects. Nexxim dynamically links with Ansoft's HFSS full-wave three-dimensional (3D) EM solver to obtain accurate S-parameter or equivalent-circuit models of IC packages, passive elements, and other complicated layout geometries. Through a simple interface window, user-defined primitives of on-chip passive components allow the automatic definition of fully parameterized, on-chip passive configurations. Parameters such as diameter, number of turns, trace-width, and the spacing between traces can be edited via a property window and the passive components can be quickly analyzed and incorporated into the circuit (through S-parameter or W-element representation) for subsequent simulation by Nexxim. In turn, Nexxim incorporates proprietary S-parameter and W-element implementations that allow for accurate frequency- and time-domain simulations of these frequency-domain specified elements. Nexxim provides the correct solution to problems that are simple, such as reflections from transmission lines, yet cannot be handled accurately by current tools.

Nexxim represents a new approach to simulation, built from the ground up. It can be invoked from Ansoft Designer to form a complete design capture, simulation and post-processing environment, providing simulation accuracy and transistor-level detail without the use of model approximations. Dynamic parameterized links to HFSS and system co-simulation with Ansoft Designer allow for circuit design, circuit/system co-design and post-layout verification for complex, mixed signal ICs.