That's one of only a few major new microprocessor disclosures at the semiconductor industry's premier conference where Intel’s Haswell and Nvidia’s Project Denver parts are noticeably absent. However, both Intel and Nvidia will deliver papers on new chip-to-chip links that may provide an oblique view on their future processor plans.

Samsung will detail a 28-nm SoC with two quad-core clusters. One cluster runs at 1. 8 GHz, has a 2 MByte L2 cache and is geared for high performance apps; the other runs at 1.2 GHz and is tuned for energy efficiency.

The chip clearly parallel’s ARM’s description of a big.little architecture using its 32-bit A15 and A7 cores. In October, ARM said the approach is delivering greater than expected benefits and expects it will become widely used in smartphones.

“We expect the Samsung part is the first big.little processor,” said Kevin Krewell, senior analyst with market watcher Linley Group (Mountain View, Calif.). “The A7 cores should be capable of handling most [smartphone] tasks, with the A15 cores only required for maximum performance needs, like video games,” he said.

The chip and ones like it from Qualcomm, Nvidia and others will roll out in 2013, competing for sockets in tablets with Intel’s 22-nm Haswell, which will not be described at ISSCC. In a departure from past years, Intel will present no processor papers at the event.

However, the x86 giant will describe a scalable 64-lane chip-to-chip interconnect with 1 Tbit/s aggregate bandwidth. The link uses multiple 2-16 Gbit/s channels running at power efficiencies of 0.8 to 2.6 pJ/bit in 32nm CMOS with a total bus-level power consumption of 2.6 W.

The paper describes research at Intel Labs that is not necessarily related to a clustering interconnect the company announced in September for future x86 and Atom server processors. It describes research using so-called micro-twinax wiring from Samtec, and connectors from Ardent Concepts to link chips at Tbit/s rates that otherwise might draw up to 20 W, according to co-author Bryan Casper, a senior principal engineer overseeing I/O research at Intel Labs.

The 1 to 2 millimeter diameter wire bundles will be “a very important technology for us going forward for some segments” spanning mobile and server apps, said Casper. “Sub picojoule per bit I/O is really important, as are fast on and off I/O links."

Separately, NVidia will describe a 20 Gbit/s serial die-to-die link made in 28-nm CMOS. It runs on a 0.9 V supply and has power efficiency of 0.54pJ/b. The interconnect might be part of Nvidia’s Project Denver, a still secretive family of processors merging ARM and graphics cores for everything from notebooks to supercomputers.