DATASHEET

ISL6217A
®
Data Sheet
June 30, 2005
FN9107.3
Precision Multi-Phase Buck PWM
Controller for Intel, Mobile Voltage
Positioning IMVP-IV™ and IMVP-IV+™
Features
The ISL6217A Multi-Phase Buck PWM controller IC, with
integrated half bridge gate drivers, provides a precision
voltage regulation system for advanced Pentium IV
microprocessors in notebook computers. Two-phase
operation eases the thermal management issues and load
demand of Intel’s latest high performance processors. This
control IC also features both input voltage feed-forward and
average current mode control for excellent dynamic
response, “Loss-less” current sensing using MOSFET
rDS(ON) and user-selectable switching frequencies from
250kHz to 1MHz per phase.
• IMVP-IV™ and IMVP-IV+™ Compliant CORE Regulator
The ISL6217A includes a 6-bit digital-to-analog converter
(DAC) that dynamically adjusts the CORE PWM output
voltage from 0.700V to 1.708V in 16mV steps and conforms
to the Intel IMVP-IV™ and IMVP-IV+™ mobile VID
specification. The ISL6217A also has logic inputs to select
Active, Deep Sleep and Deeper Sleep modes of operation. A
precision reference, remote sensing and proprietary
architecture, with integrated, processor-mode, compensated
“Droop”, provide excellent static and dynamic CORE voltage
regulation.
• Programmable “Droop” and CORE Voltage Slew Rate to
comply with IMVP-IV™ and IMVP-IV+™ specification
To improve efficiency at light loading, the ISL6217A can be
configured to run in single phase PWM in ACTIVE, DEEP or
DEEPER SLEEP modes of operation. Also, in deep and
deeper sleep modes the ISL6217A will operate in diode
emulation.
Another feature of this IC controller is the PGOOD monitor
circuit that is held low until CORE voltage increases, during
its soft-start sequence, to within 12% of the “Boot” voltage.
This PGOOD signal is masked during VID changes. Output
overcurrent, overvoltage and undervoltage are monitored
and result in the converter latching off and PGOOD signal
being held low.
• Diode Emulation Functionality in deep and deeper sleep
modes for improved light load efficiency
• Single and/or Two-phase Power Conversion
• “Loss-less” Current sensing for improved efficiency and
reduced board area
- Optional Discrete Precision Current Sense Resistor
• Internal Gate-Drive and Boot-Strap Diodes
• Precision CORE Voltage Regulation
- 0.8% system accuracy over temperature
• 6-Bit Microprocessor Voltage Identification Input
• Direct Interface with System Logic (STP_CPU# and
DPRSLPVR) for Deep and Deeper Sleep modes of
operation
• Easily Programmable voltage setpoints for Initial “Boot”,
Deep Sleep and Deeper Sleep Modes
• Excellent Dynamic Response
- Combined Voltage Feed-Forward and Average Current
Mode Control
• Overvoltage, Undervoltage and Overcurrent Protection
• Power-Good Output with internal blanking during VID and
mode changes
• User programmable Switching Frequency of 250kHz 1MHz per phase
• Pb-Free Plus Anneal Available (RoHS Compliant)
The overvoltage and undervoltage thresholds are 112% and
84% of the VID, Deep or Deeper Sleep setpoint,
respectively. Overcurrent protection features a 32 cycle
overcurrent shutdown. PGOOD, overvoltage, undervoltage
and overcurrent provide monitoring and protection for the
microprocessor and power system. The ISL6217A IC is
available in a 38 lead TSSOP.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6217A
Pinout
Ordering Information
PART NUMBER
ISL6217ACV
ISL6217ACV-T
ISL6217ACVZ
(Note 1)
ISL6217ACVZ-T
(Note 1)
ISL6217ACVZA
TEMP (°C)
-10 to 85
PACKAGE
PKG.
DWG. #
38 Ld TSSOP
M38.173
38 Ld TSSOP Tape and Reel
-10 to 85
M38.173
38 Ld TSSOP
(Pb-free)
M38.173
38 Ld TSSOP Tape and Reel
(Pb-free)
M38.173
-10 to 85
38 Ld TSSOP
(Pb-free)
ISL6217ACVZA-T 38 Ld TSSOP Tape and Reel
(Pb-free)
M38.173
ISL6217A (38 LD TSSOP)
TOP VIEW
VDD 1
38 VBAT
DACOUT 2
37 ISEN1
FSET 4
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100%
matte tin plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations. Intersil
Pb-free products are MSL classified at Pb-free peak reflow
temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
34 BOOT1
EN 6
33 VSSP1
DRSEN 7
32 LG1
DSEN# 8
31 VDDP
VID1 10
VID2 11
VID3 12
ISL6217A
TSSOP
30 LG2
29 VSSP2
28 BOOT2
27 UG2
VID4 13
26 PHASE2
VID5 14
25 ISEN2
PGOOD 15
24 VSEN
EA+ 16
23 DRSV
COMP 17
FB 18
SOFT 19
2
35 UG1
PWRCH 5
VID0 9
M38.173
36 PHASE1
DSV 3
22 STV
21 OCSET
20 VSS
FN9107.3
June 30, 2005
ISL6217A
Absolute Voltage Ratings
Thermal Information
Supply Voltage, VDD, VDDP . . . . . . . . . . . . . . . . . . . . . . . . -0.3-+7V
Battery Voltage, VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+25V
Boot1,2 and UGATE1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+35V
Phase1,2 and ISEN1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+30V
Boot1,2 with respect to Phase1,2 . . . . . . . . . . . . . . . . . . . . . . +6.5V
UGATE1,2 . . . . . . . . . . . . . . . (Phase1,2 - 0.3V) to (Boot1,2 + 0.3V)
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V)
Thermal Resistance (Typical, Note 1)
θJA (°C/W)
TSSOP Package (Note 1) . . . . . . . . . . . . . . . . . . . .
72°
Maximum Operating Junction Temperature. . . . . . . . . . . . . . . 125°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
Recommended Operating Conditions
Supply Voltage, VDD, VDDP . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Ambient Temperature. . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to 85°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . .-10°C to 125°C
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air.
Electrical Specifications
Operating Conditions: VDD = 5V, TA = -10°C to 85°C, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
EN = 3.3V, DSEN# = 0, DRSEN = 0, PWRCH = 0
-
1.4
-
mA
EN = 0V
-
1
-
µA
VDD Rising
4.35
4.45
4.5
V
VDD Falling
4.05
4.20
4.40
V
Percent system deviation from programmed VID Codes @ 1.356
-0.8
-
0.8
%
-
-
0.3
V
0.7
-
-
V
Maximum Output Voltage
-
1.708
-
V
Minimum Output Voltage
-
0.70
-
V
INPUT POWER SUPPLY
Input Supply Current, I(VDD)
POR (Power-On Reset) Threshold
REFERENCE AND DAC
System Accuracy
DAC (VID0 - VID5) Input Low Voltage DAC Programming Input Low Threshold Voltage
DAC (VID0 - VID5) Input High
Voltage
DAC Programming Input High Threshold Voltage
CHANNEL GENERATOR
Frequency, FSW
RFset = 243K, ±1%
225
250
275
kHz
Adjustment Range
Guaranteed by Design
0.25
-
1.0
MHz
-
100
-
dB
ERROR AMPLIFIER
DC Gain
Gain-Bandwidth Product
CL = 20pF
-
18
-
MHz
Slew Rate
CL = 20pF
-
4.0
-
V/µs
-
32
-
µA
-
64
-
µA
-
31
-
µA
27
28
30
µA
ISEN
Full Scale Input Current
Overcurrent Threshold
ROCSET = 124K
Soft-Start Current
Droop Current
GATE DRIVER
UGATE Source Resistance
500mA Source Current
-
1
1.5
Ω
UGATE Source Current
VUGATE-PHASE = 2.5V
-
2
-
A
3
FN9107.3
June 30, 2005
ISL6217A
Electrical Specifications
Operating Conditions: VDD = 5V, TA = -10°C to 85°C, Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
UGATE Sink Resistance
500mA Sink Current
-
1
1.5
Ω
UGATE Sink Current
VUGATE-PHASE = 2.5V
-
2
-
A
LGATE Source Resistance
500mA Source Current
-
1
1.5
Ω
LGATE Source Current
VLGATE = 2.5V
-
2
-
A
LGATE Sink Resistance
500mA Sink Current
-
0.5
0.8
Ω
LGATE Sink Current
VLGATE = 2.5V
-
4
-
A
0.58
0.68
0.76
V
2.43
-
-
mA
56
63
82
Ω
BOOTSTRAP DIODE
Forward Voltage
VDDP = 5V, Forward Bias Current = 10mA
POWER GOOD MONITOR
PGOOD Sense Current
PGOOD pull down MOSFET rDS(ON) (See Figure 10)
Undervoltage Threshold (Vsen/Vref)
VSEN Rising
-
85.0
-
%
Undervoltage Threshold (Vsen/Vref)
VSEN Falling
-
84.0
-
%
PGOOD Low Output Voltage
IPGOOD = 4mA
-
0.26
0.4
V
EN, DSEN#, DRSEN Low
-
-
1
V
EN, DSEN#, DRSEN High
2
-
-
V
-
112.0
-
%
LOGIC THRESHOLD
PROTECTION
Overvoltage Threshold (Vsen/Vref)
VSEN Rising
Delay Time
Delay Time from LGATE Falling to
UGATE Rising
VDDP = 5V, BOOT to PHASE = 5V, UGATE - PHASE = 2.5V,
LGATE = 2.5V
10
18
30
ns
Delay Time from UGATE Falling to
LGATE Rising
VDDP = 5V, BOOT to PHASE = 5V, UGATE - PHASE = 2.5V,
LGATE = 2.5V
10
18
30
ns
4
FN9107.3
June 30, 2005
ISL6217A
Functional Pin Description
VDD - This pin is used to connect +5V to the IC to supply all
power necessary to operate the chip. The IC starts to
operate when the voltage on this pin exceeds the rising POR
threshold and shuts down when the voltage on this pin drops
below the falling POR threshold.
FB - This pin is connected to the inverting input of the error
amplifier.
SOFT - This pin programs the slew rate of VID changes,
Deep Sleep and Deeper Sleep transitions and Soft-Start
after initializing. This pin is connected to ground via a
capacitor, and to EA+ through an external “Droop” resistor.
DACOUT - This pin provides access to the output of the
Digital-to-Analog Converter.
VBAT - Voltage on this pin provides feed-forward battery
information which adjusts the oscillator ramp amplitude.
DSV - The voltage on this pin provides the set point for
output voltage during Deep Sleep Mode of operation.
ISEN1, ISEN2 - These pins are used as current sense inputs
from the individual converter channel phase nodes.
FSET - A resistor from this pin to ground programs the
switching frequency.
PHASE1, PHASE2 - These pins are connected to the phase
nodes of channels 1 and 2, respectively.
PWRCH - This pin selects the number of power channels. A
HIGH logic level on this pin enables 2 channel operation,
and a LOW logic signal enables single channel operation.
UG1, UG2 - These pins are the gate-drive outputs to the
high side MOSFETs for channels 1 and 2, respectively.
EN - This pin is connected to the system signal VR_ON and
provides the enable/disable function for the PWM controller.
DRSEN - This pin connects to system logic “DPRSLPVR”
and enables Deeper Sleep mode of operation when a logic
HIGH is detected on this pin.
DSEN# - This pin connects to system logic “STP_CPU#” and
enables Deep Sleep mode of operation. Deep Sleep is
enabled when a logic LOW signal is detected on this pin.
VID0, VID1, VID2, VID3, VID4, VID5 - These pins are used
as inputs to the 6-bit Digital-to-Analog converter (DAC). VID0
is the least significant bit and VID5 is the most significant bit.
PGOOD - This pin is used as an input and an output and is
tied to the Vccp and Vcc_mch PGOOD signals. During startup, this pin is recognized as an input and prevents further
slewing of the output voltage from the “Boot” level until
PGOOD from Vccp and Vcc_mch is enabled High. After
Start-up, this pin has an open drain output used to indicate
the status of the CORE output voltage. This pin is pulled low
when the system output is outside of the regulation limits.
PGOOD includes a timer for power-on delay.
EA+ - This pin is connected to the non-inverting input of the
error amplifier and is used for setting the “Droop” voltage.
BOOT1, BOOT2 - These pins are connected to the
bootstrap capacitors, for upper gate-drive, for channels 1
and 2, respectively.
VSSP1, VSSP2 - These pins are connected to the power
ground of channels 1 and 2, respectively.
LG1, LG2 - These pins are the gate-drive outputs to the low
side MOSFETs for channels 1 and 2, respectively.
VDDP - This pin provides a low-esr bypass connection to the
internal gate drivers for the +5V source.
VSEN - This pin is used for remote sensing of the
microprocessor CORE voltage.
DRSV - The voltage on this pin provides the set point for
output voltage during Deeper Sleep Mode of operation.
OCSET - A resistor from this pin to ground sets the
overcurrent protection threshold. The current from this pin
should be between 10µA and 25µA (70kΩ - 175kΩ
equivalent) pull-down resistance.
STV - The voltage on this pin sets the initial Start-Up or
“Boot” voltage.
VSS - This pin provides connection for signal ground.
COMP - This pin provides connection to the error amplifier
output.
5
FN9107.3
June 30, 2005
ISL6217A
Block Diagram
VSEN
PGOOD
VDD
EN
1.3V
+
POWER-ON
-
RESET(POR)
+
CONTROL
AND
FAULT LOGIC
OVP
-
VBAT
CLOCK AND
SAWTOOTH
GENERATOR
1.75V
FS
HIGH-IMPEDANCE STATE
+
112% RISING
102% FALLING
Σ
+
PWM1
PWM
-
-
88% RISING
84% FALLING
HIGH-IMPEDANCE STATE
-
+
UV
+
Σ
PWM2
PWM
-
32 COUNT
CLOCK
CYCLE
PWRCH
+
-
BOOT1
VDDP
UG1
DACOUT
VSOFT
SOFT
PWM1
SOFT
START
PHASE
LOGIC
PHASE1
VDDP
EA+
LG1
VID0
PWM2
VID1
VDDP
VID2
+
VID
VID3
VSSP1
PHASE
LOGIC
D/A
BOOT2
E/A
-
VID4
UG2
CHANNEL
CURRENT
BALANCE
VID5
PWRCH
PHASE2
COMP
VDDP
FB
1.75V
+
OCSET
IDROOP
OC
MUX
DRSV
VCORE
REF
Σ
-
+
DSV
1
2N
Σ
IOCSET
STV
LG2
0.435
-2µA
VSSP2
Σ
SAMPLE
&
HOLD
8µA
ISEN1
CHANNEL
CURRENT
SENSE
32 COUNT
CLOCK
CYCLE
ISEN2
VSS
DSEN# DRSEN
6
PWRCH
FN9107.3
June 30, 2005
ISL6217A
Typical Application - 2-Phase Converter
Figure 1 shows a 2-Phase Synchronous Buck Converter
circuit used to provide “CORE” voltage regulation for the
Intel Pentium IV mobile processor using IMVP-IV™ and
IMVP-IV+™ voltage positioning.
The ISL6217A PWM controller can be configured for two or
one channel operation, and the ISL6217A can change the
number of power channels in operation, dynamically. The
number of channels of operation can be changed through
+5VDC
+5VDC
the PWRCH pin. The ISL6217A can be configured for two
channel operation in “Active” mode and one channel
operation in “Deep” and “Deeper Sleep” modes through logic
connections to the PWRCH pin. The following configuration
uses two channel operation in “Active” mode and one
channel operation in “Deep” and “Deeper Sleep” modes.
The circuit shows pin connections for the ISL6217A PWM
controller in the 38 lead TSSOP package.
Vbattery
VBAT
VDD
DACOUT
ISEN1
DSV
PHASE1
UG1
FSET
BOOT1
PWRCH
EN
VSSP1
DRSEN
LG1
DSEN#
VDDP
VID0 ISL6217A LG2
VID1
TSSOP VSSP2
VID2
BOOT2
VID3
UG2
VID4
PHASE2
VID5
ISEN2
PGOOD
VSEN
EA+
DRSV
COMP
STV
FB
OCSET
VSS
SOFT
VR_ON
DPRSLPVR
STP_CPU#
VID
PWRGD
+Vcc_core
FIGURE 1. TYPICAL APPLICATION CIRCUIT FOR ISL6217A MULTIPHASE PWM CONTROLLER
7
FN9107.3
June 30, 2005
ISL6217A
VID
Capture VID Code
< 3m s
VR_ON / EN
V BOOT
>10us
-12%
V CC-CORE
V VID
t2
t1
PGOOD Vccp / Vcc_m ch
3m s to 12m s
PGOOD Vcc_core
FIGURE 2. TIMING DIAGRAM SHOWING VR_ON, VCC_CORE AND PGOOD FOR VCC_CORE, VCCP AND VCC_MCH
Operation
Initialization
Soft-Start Interval
Once the +5VDC supply voltage, as connected to the
ISL6217A VDD pin, reaches the Power-On Reset (POR)
rising threshold, the PWM drive signals are held in “highimpedance state” or high impedance mode. This results in
both high and low side MOSFETs being held low. Once the
supply voltage exceeds the POR rising threshold, the
controller will respond to a logic level high on the EN pin and
initiate the soft-start interval. If the supply voltage drops
below the POR falling threshold, POR shutdown is triggered
and the PWM signals are again driven to “high-impedance
state”.
Once VDD rises above the POR rising threshold and the EN
pin voltage is above the threshold of 2.0V, a soft-start
interval is initiated. Refer to Figure 2 and Figure 3.
The system signal, VR_ON is directly connected to the EN
pin of the ISL6217A. Once the voltage on the EN pin rises
above 2.0V, the chip is enabled and soft-start begins. The
EN pin of the ISL6217A is also used to reset the ISL6217A,
for cases when an undervoltage or overcurrent fault
condition has latched the IC off. A toggling of the state of this
pin to a level below 1.0V will re-enable the IC. For the case
of an overvoltage fault, the VDD pin must be reset.
During Start-Up, the ISL6217A regulates to the voltage on
the STV pin. This is referred to as the “Boot” voltage and is
labelled VBOOT in Figure 2. Once power good signals are
received from the Vccp and Vcc_mch regulators, the
ISL6217A will capture the VID code and regulate to this
command voltage within 3ms to 12ms. The PGOOD pin of
the ISL6217A is both an input and an output and is further
described in the “Fault Protection” section of this document.
8
The voltage on the EA+ pin is the reference voltage for the
regulator. The voltage on the EA+ pin is equal to the voltage
on the SOFT pin minus the “Droop” resistor voltage,
VDROOP. During Start-Up, when the voltage on SOFT is
less than the “Boot” voltage VBOOT, a small 30µA current
source, I1, is used to slowly ramp up the voltage on the softstart capacitor CSOFT. This slowly ramps up the reference
voltage for the controller, and therefore, controls the slew
rate of the output voltage. The STV pin is externally
programmable and sets the Start-Up, or “Boot” voltage,
VBOOT. The programming of this voltage level is explained
in the “STV, DSV and DRSV” section of this document.
The ISL6217A PGOOD pin is both an input and an output.
The system signal, IMVP4_PWRGD, is connected to power
good signals from the Vccp and Vcc_mch supplies. The
Intersil ISL6227, Dual Voltage Regulator is an ideal choice
for the Vccp and Vcc_mch supplies.
Once the output voltage is within the “Boot” level regulation
limits and a logic high PGOOD signal from the Vccp and
Vccp_mch regulators is received, the ISL6217A is enabled
to capture the VID code and regulate to that command
voltage. Refer to Figure 2 and Figure 3. A second current
source, I2, is added to I1, after the initial Start-Up transition.
I2 is approximately 100µA, and raises the total SOFT pin
sinking and sourcing current to 130µA. This increased
current is used to increase the slew rate of the reference to
FN9107.3
June 30, 2005
ISL6217A
meet all Active, Deep and Deeper Sleep slew rate
requirements of the Intel IMVP-IV™ and IMVP-IV+™
specification.
FSET RESISTOR VALUE (kΩ)
250
ISL6217A
I1
I2
IDROOP
Error
Amplifier
+
SOFT
R DROOP
EA+
200
150
100
50
0
250
500
750
1000
CHANNEL SWITCHING FREQUENCY, Fsw, (kHz)
+ V DROOP
C SOFT
FIGURE 4. CHANNEL SWITCHING FREQUENCY vs RFSET
FIGURE 3. SOFT-START TRACKING CIRCUITRY SHOWING
INTERNAL CURRENT SOURCES AND "DROOP"
FOR ACTIVE, DEEP AND DEEPER SLEEP
MODES OF OPERATION
The “Droop” current source, IDROOP, is proportional to load
current. This current source is used to reduce the reference
voltage on EA+ by the voltage drop across the “Droop”
resistor. A more in-depth explanation of “Droop”, and the
sizing of this resistor, can be found in the “Droop
Compensation” section of this document.
The choice of value for soft-start capacitor is determined by
the maximum slew rate required for the application. An
example calculation is shown below. Using the combined I1
and I2 current sources on the SOFT pin as 130µA, and the
worst case slew rate of (10mV/µs), the SOFT capacitor is
calculated as follows:
I
1µs
CSOFT = SOURCE = 130µA ×
= 0.013µF ≈ 0.012µF
SlewRate
10mV
(EQ. 1)
Gate-Drive Signals
The ISL6217A provides internal gate-drive for a two channel,
Synchronous Buck, Core Regulator. During two channel
mode of operation, the PWM drive signals are switched 180°
out of phase to reduce ripple current delivered from the DC
rail and to the load.
The ISL6217A was designed with a 4A, low-side gate
current sink ability, and a 2A low-side gate current source
ability, to efficiently drive the latest, high-performance
MOSFETs. This feature will provide the system designer with
flexibility in MOSFET selection, as well as optimum
efficiency during Active mode of operation.
9
PWRCH Pin
A HIGH logic level on this pin enables two channel operation
and a LOW logic signal enables single channel operation. By
tying this pin to the STP_CPU# system signal, (DSEN# pin
on ISL6217A) single channel operation will be invoked
during the light loading of both Deep and Deeper Sleep. If
single channel operation is desired only during Deeper
Sleep, the inversion of system signal DPRSLPVR can be
connected to this pin.
The aggressive gate-drive capability and diode emulation of
ISL6217A, coupled with the single channel operation feature
results in superior efficiency performance over both light and
heavy loads.
Frequency Setting
Both channel switching frequencies are set up by a resistor
from the FSET pin to ground. The choice of FSET resistance
for a desired switching frequency can be approximated using
Figure 4. The switching frequency is designed to operate
between 250kHz and 1MHz per phase.
CORE Voltage Programming
The voltage identification pins (VID0, VID1, VID2, VID3,
VID4 and VID5) set the DAC output voltage. These pins do
not have internal pull-up or pull-down capability. These pins
will recognize 1.0V, 3.3V, or 5.0V CMOS logic. Table 1
shows the command voltage, VDAC for the 6 bit VID codes.
The IC responds to VID code changes as shown in Figure 5.
PGOOD is masked between these transitions.
FN9107.3
June 30, 2005
ISL6217A
TABLE 1. IMPV-IV VID CODES (Continued)
TABLE 1. IMPV-IV VID CODES
VID5
VID4
VID3
VID2
VID1
VID0
VDAC
VID5
VID4
VID3
VID2
VID1
VID0
VDAC
0
0
0
0
0
0
1.708
1
0
0
0
0
0
1.196
0
0
0
0
0
1
1.692
1
0
0
0
0
1
1.180
0
0
0
0
1
0
1.676
1
0
0
0
1
0
1.164
0
0
0
0
1
1
1.660
1
0
0
0
1
1
1.148
0
0
0
1
0
0
1.644
1
0
0
1
0
0
1.132
0
0
0
1
0
1
1.628
1
0
0
1
0
1
1.116
0
0
0
1
1
0
1.612
1
0
0
1
1
0
1.100
0
0
0
1
1
1
1.596
1
0
0
1
1
1
1.084
0
0
1
0
0
0
1.580
1
0
1
0
0
0
1.068
0
0
1
0
0
1
1.564
1
0
1
0
0
1
1.052
0
0
1
0
1
0
1.548
1
0
1
0
1
0
1.036
0
0
1
0
1
1
1.532
1
0
1
0
1
1
1.020
0
0
1
1
0
0
1.516
1
0
1
1
0
0
1.004
0
0
1
1
0
1
1.500
1
0
1
1
0
1
0.988
0
0
1
1
1
0
1.484
1
0
1
1
1
0
0.972
0
0
1
1
1
1
1.468
1
0
1
1
1
1
0.956
0
1
0
0
0
0
1.452
1
1
0
0
0
0
0.940
0
1
0
0
0
1
1.436
1
1
0
0
0
1
0.924
0
1
0
0
1
0
1.420
1
1
0
0
1
0
0.908
0
1
0
0
1
1
1.404
1
1
0
0
1
1
0.892
0
1
0
1
0
0
1.388
1
1
0
1
0
0
0.876
0
1
0
1
0
1
1.372
1
1
0
1
0
1
0.860
0
1
0
1
1
0
1.356
1
1
0
1
1
0
0.844
0
1
0
1
1
1
1.340
1
1
0
1
1
1
0.828
0
1
1
0
0
0
1.324
1
1
1
0
0
0
0.812
0
1
1
0
0
1
1.308
1
1
1
0
0
1
0.796
0
1
1
0
1
0
1.292
1
1
1
0
1
0
0.780
0
1
1
0
1
1
1.276
1
1
1
0
1
1
0.764
0
1
1
1
0
0
1.260
1
1
1
1
0
0
0.748
0
1
1
1
0
1
1.244
1
1
1
1
0
1
0.732
0
1
1
1
1
0
1.228
1
1
1
1
1
0
0.716
0
1
1
1
1
1
1.212
1
1
1
1
1
1
0.700
10
FN9107.3
June 30, 2005
ISL6217A
Active, Deep Sleep and Deeper Sleep Modes
TABLE 2. OUTPUT VOLTAGE AS A FUNCTION OF DSEN#
AND DRSEN LOGIC STATES
The ISL6217A Multi-Phase Controller is designed to control
the CORE output voltage as per the IMVP-IV™ and
IMVP-IV+™ specifications for Active, Deep Sleep, and
Deeper Sleep Modes of Operation.
DSEN# STP_CPU#
DRSEN DPRSLPVR
MODE OF
OPERATION
OUTPUT
VOLTAGE
1
0
Active
VID
0
0
Deep Sleep
DSV
0
1
Deeper Sleep
DRSV
1
1
Deeper Sleep
DRSV
After initial Start-up, a logic high signal on DSEN# and a
logic low signal on DRSEN signals the ISL6217A to operate
in Active mode. Refer to Table 2. This mode will recognize
VID code changes and regulate the output voltage to these
command voltages.
VID[0..5]
Current VID Code
New VID Code
<600ns
VCC_CORE
Current Voltage Level
PGOOD
New Voltage Level
HIGH
FIGURE 5. PLOT SHOWING TIMING OF VID CODE CHANGES AND CORE VOLTAGE SLEWING AS WELL AS PGOOD MASKING
VID[0..5]
VID Code remains the same
STP_CPU#
(DSEN#)
<30us
VID Command Voltage
VCC_CORE
VDeep Sleep
FIGURE 6. VCORE RESPONSE FOR DEEPER SLEEP COMMAND
VID[0..5]
VID Code remains the same
STP_CPU#
(DSEN#)
Deeper Sleep Mode
DPRSLPVR
(DRSEN)
VCC_CORE
Short DPRSLP causes
VCC-CORE to ramp up
VDeep Sleep
VDeeper Sleep
FIGURE 7. VCORE RESPONSE FOR DEEPER SLEEP COMMAND
11
FN9107.3
June 30, 2005
ISL6217A
A logic low signal present on STPCPU# (pin DSEN#), with a
logic low signal on DPRSLPVR (pin DRSEN), signals the
ISL6217A to reduce the CORE output voltage to the Deep
Sleep level, the voltage on the DSV pin, and to operate in
diode emulation.
A logic high on DPRSLPVR, (pin DRSEN) with a logic low
signal on STPCPU# (pin DSEN#), signals the ISL6217A
controller to further reduce the CORE output voltage to the
Deeper Sleep level, which is the voltage on the DRSV pin.
Deep Sleep and Deeper Sleep voltage levels are
programmable and are explained in the “STV, DSV and
DRSV” section of this document.
Deep Sleep Enable-DSEN# and Deeper Sleep
Enable - DRSEN
Table 2 shows logic states controlling modes of operation.
Figure 6 and Figure 7 show the timing for transitions entering
and exiting Deep Sleep Mode and Deeper Sleep Mode. This
is controlled by the system signals STPCPU# and
DPRSLPVR. ISL6217A pins DSEN#, (Deep Sleep Enable #)
and DRSEN, (Deeper Sleep Enable), are connected to these
2 signals, respectively.
When DSEN# is logic high, and DRSEN is logic low, the
controller will operate in Active Mode and regulate the output
voltage to the VID commanded DAC voltage, minus the
voltage “Droop” as determined by the load current. Voltage
“Droop” is the reduction of output voltage proportional to
output current.
When a logic low is detected at the DSEN# and DRSEN
pins, the controller will regulate the output voltage to the
voltage seen on the DSV pin minus “Droop”. If the PWRCH
pin is connected to the DSEN# pin then the controller will
also switch to single channel operation.
When DSEN# is logic low and DRSEN is logic high the
controller will operate in Deeper Sleep mode. The ISL6217A
will then regulate to the voltage at the DRSV pin minus
“Droop”. If the PWRCH pin is connected to the DSEN# pin,
then the controller will also automatically switch to single
channel operation.
If the PWRCH pin is connected to an inverted DPRSLPVR
system signal, then the controller will automatically switch to
single channel operation during Deeper Sleep mode only.
Deep and Deeper Sleep voltage levels are programmable
and explained in the “STV, DSV and DRSV” section of this
document.
STV, DSV and DRSV
Start-up “Boot” Voltage - STV
The Start-up or “Boot” voltage is programmed by an external
resistor divider network from the OCSET pin. Refer to
Figure 8. Internally, a 1.75V reference voltage is output on
the OCSET pin. The start-up voltage is set through a voltage
12
divider from the 1.75V reference at the OCSET pin. The
voltage on the STV pin will be the voltage the controller will
regulate to during the start-up sequence.
Once the PGOOD pin of the ISL6217A controller is
externally enabled high by the Vccp and Vcc_mch
controllers, the ISL6217A will then ramp, after a 10µs delay,
to the voltage commanded by the VID setting minus “Droop”.
BATTERY
VREF = 1.75V
ISL6217A
IOCSET
R1
OCSET
VBAT
36.5K
1.200V
R2
STV
30.1K
DACOUT
VID COMMAND
VOLTAGE
1.21K
0.750V
R3
49.9K
DRSV
SOFT
GND
DSV
98.8%
DACOUT
98.8K
0.012µF
FIGURE 8. CONFIGURATIONS FOR BATTERY INPUT,
OVERCURRENT SETTING AND START, DEEP
SLEEP AND DEEPER SLEEP VOLTAGE
DIVIDERS
Deep Sleep Voltage - DSV
The Deep Sleep voltage is programmed by an external
voltage divider network from the DACOUT pin. Refer to
Figure 8. The DACOUT pin is the output of the VID digital-toanalog converter. By having the Deep Sleep voltage setup
from a resistor divider from DAC, the Deep Sleep voltage will
be a constant percentage of the VID. Through the voltage
divider network, Deep Sleep voltage is set to 98.8% of the
programmed VID voltage, as per the IMVP-IV™ and
IMVP-IV+™ specification.
The IC enters the Deep Sleep mode when the DSEN# is low
and the DRSEN pin is low as shown in Figure 6 and
Figure 7. Once in Deep Sleep Mode, the controller will
regulate to the voltage seen on the DSV pin minus “Droop”.
Deeper Sleep Voltage - DRSV
The Deeper Sleep voltage, DRSV, is programmed by an
external voltage divider network from the 1.75V reference on
the OCSET pin. Refer to Figure 8. In Deeper Sleep mode
the ISL6217A controller will regulate the output voltage to
the voltage present on the DRSV pin minus “Droop”. This
voltage is easily changed by changing the ratio of R1, R2,
and R3.
The IC enters Deeper Sleep mode when DRSEN is high and
DSEN# is low, as shown in Figure 7.
FN9107.3
June 30, 2005
ISL6217A
Overcurrent Setting - OCSET
The ISL6217A overcurrent protection essentially compares a
user-selectable overcurrent Threshold to the scaled and
sampled output current. An overcurrent condition is defined
when the sampled current is equal to or greater than the
threshold current. A step by step process to design for the
user-desired overcurrent set point is detailed next.
RISEN resistor, as described above, is then replaced with a
standard 1% resistor and connected from the ISEN pin of the
ISL6217A controller to the SOURCE of the lower MOSFET.
STEP 1: SETTING THE OVERCURRENT THRESHOLD
The overcurrent threshold is represented by the DC current
flowing out of the OCSET pin (See Figure 8). Since the
OCSET pin is held at a constant 1.75V, the user need only
populate a resistor from this pin to ground to set the desired
overcurrent threshold, IOCSET. The user should pick a value
of IOCSET between 10µA and 25µA. Once this is done, use
Ohm’s Law to determine the necessary resistor to place from
OCSET to ground:
ROCSET =
1.75 V
= R1 + R2 + R3
IOCSET
(EQ. 2)
For example, if the desired overcurrent threshold is 15µA,
the total resistance from OCSET must equal 117kΩ.
STEP 2: SELECTING ISEN RESISTANCE FOR DESIRED
OVERCURRENT LEVEL
After choosing the IOCSET level, the user must then decide
what level of total output current is desired for overcurrent.
Typically, this number is between 150% and 200% of the
maximum operating current of the application. For example,
if the max operating current is 46A, and the user chooses
150% overcurrent, the ISL6217A will shut down if the output
current exceeds 46A*1.5 or 69A. According to the Block
Diagram, the equation below should be used to determine
RISEN once the overcurrent level, IOC, is chosen.
RISEN =
IOC ⋅
r(DSON)
⋅ 0.2175
M
− 130
(IOCSET + 2µA ) ⋅ N − 4µA
(EQ. 3)
In Equation 3, M represents the number of Low-Side
MOSFETs in one channel, and N represents the number of
channels. Using the examples above (IOC = 69A,
IOCSET = 15µA) and substituting the values M = 2, N = 2,
rDS(ON) = 6mΩ, RISEN is calculated to be 1.5kΩ.
STEP 3: THERMAL COMPENSATION FOR rDS(ON) (IF
DESIRED)
If PTCs are used for thermal compensation, then RISEN is
found using the room temperature value of rDS(ON). If
standard resistors are used for RISEN, then the “HOT” value
of rDS(ON) should be used for this calculation.
MOSFET rDS(ON) sensing provides advantages in cost,
efficiency, and board area. However, if more precise current
feedback is desired, a discrete Precision Current Sense
Resistor, RPOWER, may be inserted between the SOURCE
of each channels lower MOSFET and ground. The small
13
FN9107.3
June 30, 2005
ISL6217A
FB
R2
CDCPL
R1
C2
C1
COMP
VIN
ERROR
AMPLIFIER
_
EA+
VDROOP R
DROOP
+
SOFT
CSOFT
Σ
+
+
Q1
UG1
PWM 1
CIRCUIT
BALANCE
-
VERROR1
+
-
IDROOP
IAVERAGE
PHASE
CURRENT
SENSING
-
IMVP-IV_
IMVP-IV+_
REFERENCE
ISEN1
+
+
Σ
RISEN1
CURRENT
AVERAGING
VCORE
Σ
IL1
Q2
COMPARATOR
+
Σ
LG1
L 01
ISEN2
CURRENT
SENSING
COUT
RISEN2
+
Vrdson
RLOAD
VIN
PHASE
VERROR2
BALANCE
+
-
Q3
UG2
PWM 2
CIRCUIT
COMPARATOR
Q4
LG2
L 02
Vrdson IL2
+
ISL6217A
FIGURE 9. SIMPLIFIED BLOCK DIAGRAM OF THE ISL6217A VOLTAGE AND CURRENT CONTROL LOOPS FOR A TWO CHANNEL
REGULATOR
Battery Feed-Forward Compensation - VBAT
The ISL6217A incorporates Battery Voltage Feed-Forward
Compensation, as shown in Figure 8. This compensation
provides a constant Pulse Width Modulator Gain
independent of battery voltage. An understanding of this
gain is required for proper loop compensation. The Battery
Voltage is connected directly to the ISL6217A by way of the
VBAT pin, and the gain of the system ramp modulator is a
constant 6.0.
PGOOD pin toggling low to indicate a problem with the
output voltage.
PGOOD
As previously described, the ISL6217A PGOOD pin
operates as both an input and an output. During start-up, the
PGOOD pin operates as an input. Refer to Figure 10.
ISL6217A
ISL6217
SET
RST#
Fault Protection
EN
The ISL6217A protects the CPU from damaging stress
levels. The overcurrent trip point is integral in preventing
output shorts of varying degrees from causing current spikes
that would damage a CPU. The output overvoltage and
undervoltage detection features insure a safe window of
operation for the CPU.
Output Voltage Monitoring
VSEN is connected to the local CORE Output Voltage and is
used for PGOOD, undervoltage and overvoltage sensing
only. Refer to the “Block Diagram”.
The voltage on VSEN is compared with two voltage levels
which indicate an overvoltage or undervoltage condition of
the output. Violating either of these conditions results in the
14
IPGT
START
SQ
RQ
CLR
t
START
PGOOD
1.2K
3.3V
3.3V
10K
3.3V
ISL6227
PGOOD
Vccp
10K
PGOOD
Vcc_mch
~ 100ns
t
3ms-12ms
CPU-UP# =
UV# and OV#
CLK_ENABLE#
IMVP4_PWRGD
FIGURE 10. INTERNAL PGOOD CIRCUITRY FOR THE
ISL6217A CORE VOLTAGE REGULATOR
As per the IMVP-IV™ and IMVP-IV+™ specification, once
the ISL6217A CORE regulator regulates to the “Boot”
voltage, it waits for the PGOOD logic HIGH signals from the
Vccp and Vcc_mch regulators. The Intersil ISL6227 is a
FN9107.3
June 30, 2005
ISL6217A
perfect choice for these two supplies, as it is a dual regulator
and has independent PGOOD functions for each supply.
Once these two supplies are within regulation, PGOODVccp
and PGOODVcc_mch will be high impedance, and will allow
the PGOOD of the ISL6217A to sink approximately 2.6mA to
ground through the internal MOSFET, shown in Figure 10.
The ISL6217A detects this current and starts an internal
PGOOD timer.
This architecture eliminates the need of a high current,
Schottky diode on the output. If the overvoltage condition
persists, the outputs are cycled between output low and
output “off”, similar to a hysteretic regulator. The OV latch is
reset by cycling the VDD supply voltage to initiate a POR.
Depending on the mode of operation, the overvoltage set
point is 112% of the VID, Deep or Deeper Sleep set point.
The current sourced into the PGOOD pin is critical for proper
start-up operation. The pullup resistor, Rpullup is sized to
give approximately 2.6mA of current sourced into the
PGOOD pin when the system is enabled and the Vccp and
Vcc_mch supplies are in regulation.
The VSEN pin is also compared to an undervoltage (UV)
reference which is set to 84% of the VID, Deep or Deeper
Sleep set point, depending on the mode of operation. If the
VSEN voltage is below the UV reference for more than 32
consecutive phase clock cycles, the power good monitor
triggers the PGOOD pin to go low, and latches the chip off
until power is reset to the chip, or the EN pin is toggled.
As given in the electrical specifications of this document, the
PGOOD MOSFET rDS(ON) is given as 82Ω maximum. If
3.3V is used as the supply, then the pullup resistor is given
by the following equation:
RPullup =
(EQ. 4)
3.3 − 0.05(3.3 )
Vsource
− rDSON (max ) =
− 82 ≈ 1.2kΩ
2.6mA
2.6mA
where Vsource is the supply minus 5% for tolerance. This
will insure that approximately 2.6mA will be sourced into the
PGOOD pin for worst case conditions of low supply and
largest MOSFET rDS(ON).
Once the proper level of PGOOD current is detected, the
ISL6217A then captures the VID and regulates to this value.
The PGOOD timer is a function of the internal clock and
switching frequency. The internal PGOOD delay can be
calculated as follows:
Timer Delay = 3072 / FSW
(EQ. 5)
The ISL6217A controller regulates the CORE output voltage
to the VID command, and once the timer has expired, the
PGOOD output is allowed to go high.
NOTE: the PGOOD functions of the VCC_CORE, Vccp and
Vcc_mch regulators are wire OR’d together to create the system
signal “IMVP4_PWRGD”. If any of the supplies fall outside the
regulation window, their respective PGOOD pins are pulled low,
which forces IMVP4_PWRGD low. PGOOD of the ISL6217A is
internally disabled during all VID and Mode transitions.
Overvoltage
The VSEN voltage is compared with an internal overvoltage
protection (OVP) reference, set to 112% of the VID voltage.
If the VSEN voltage exceeds the OVP reference, a
comparator simultaneously sets the OV latch, and pulls the
PWM signal low. The drivers turn on the lower MOSFETs,
shunting the converter output to ground. Once the output
voltage falls below 102% of the set point, the high side and
low side MOSFETs are held off. This prevents dumping of
the output capacitors back through the output inductors and
lower MOSFETs, which would cause a negative voltage on
the CORE output.
15
Undervoltage
Overcurrent
The RISEN resistor scales the voltage sampled across the
lower MOSFET and provides current feedback proportional
to the output current of each active channel. Refer to
Figure 9. The ISEN currents from all the active channels are
averaged together to form a scaled version of the total
output current, IAVERAGE. IAVERAGE is compared with an
internally generated overcurrent trip threshold, which is
proportional to the current sourced from the OCSET pin,
IOCSET. The overcurrent trip current source is
programmable and described in the “Overcurrent Setting OCSET” section of this document.
If IAVERAGE exceeds the IOCSET level, an up/down
counter is enabled. If IAVERAGE does not fall below
IOCSET within 32 phase cycle counts, the PGOOD pin
transitions low and latches the chip off. If normal operation
resumes within the 32 phase cycle count window, the
controller will continue to operate normally. Refer to the
“Block Diagram”.
NOTE: due to “DROOP” there is inherent current limit, since load
current cannot exceed the amount that would command an output
voltage lower than 84% of the VID voltage. This would result in an
undervoltage shutdown, and would also cause the PGOOD pin to
transition low and latch the chip off.
Control Loops
The “Block Diagram” and Figure 9 shows a simplified
diagram of the voltage regulation and current control loops
for a two-phase converter. Both voltage and current
feedback are used to precisely regulate voltage and tightly
control output currents, IL1 and IL2, of the two power
channels. The voltage loop is comprised of the Error
Amplifier, Comparators, Internal Gate Drivers, and
MOSFETs. The Error Amplifier drives the modulator to force
the FB pin to the IMVP-IV™ and IMVP-IV+™ reference
minus “Droop”.
FN9107.3
June 30, 2005
ISL6217A
Voltage Loop
The output CORE voltage feedback is applied to the Error
Amplifier through the compensation network. The signal
seen on the FB pin will drive the Error Amplifier output either
high or low, depending on the CORE voltage. A CORE
voltage level that is lower than the IMVP-IV™ and
IMVP-IV+™ reference, as output from the 6 bit DAC, makes
the amplifier output move towards a higher output voltage
level. The amplifier output voltage is applied to the positive
inputs of the comparators by the BALANCE summing
networks. Out-of-phase sawtooth signals are applied to the
two comparator inverting inputs. Increasing Error Amplifier
voltage results in increased Comparator output duty cycle.
This increased duty cycle signal is passed through the PWM
circuit to the internal gate-drive circuitry. The output of the
internal gate-drive is directly connected to the gate of the
MOSFETs. Increased duty cycle or ON-time for the high side
MOSFET transistors results in increased output voltage,
VCORE, to compensate for the low output voltage sensed.
Current Loop
The current control loop keeps the channel currents in
balance. During the PWM off-time of each channel, the
voltage VrDS(ON), developed across the lower MOSFET is
sampled. Internally, the ISEN pin is held at virtual ground
during this interval, and VrDS(ON) is impressed across the
RISEN resistor. This provides current feedback proportional
to the output current of each channel. The scaled output
currents from all active channels are combined to create an
average current reference IAVERAGE, proportional to the
converter total output current. This signal is then subtracted
from the individual channel scaled output currents to
produce a current correction signal for each channel. The
current correction signal keeps each channel output current
contribution balanced relative to the other active channels.
Each current correction signal is subtracted from the error
amplifier output and fed to the individual channel PWM
circuits. For example, assume the voltage sampled across
Q4 in Figure 9 is higher than that sampled across Q2. The
ISEN2 current would be higher than ISEN1. When the two
reference currents are averaged, they accurately represent
the total output current of the converter. The reference
current IAVERAGE is then subtracted from the ISEN
currents. This results in a positive offset for Channel 2 and a
negative offset for Channel 1. These offsets are subtracted
from the error amplifier signal and perform phase balance
correction. The VERROR2 signal is reduced, while
VERROR1 would be increased. The PWM circuit would then
reduce the pulse width to lower the output current
contribution by Channel 2, while doing the opposite to
Channel 1, thereby balancing channel currents.
Droop Compensation
Microprocessors and other peripherals tend to change their
load current demands from near no-load to full load often
16
during operation. These same devices require minimal
output voltage deviation during a load step.
A high di/dt load step will cause an output voltage spike. The
amplitude of the spike is dictated by the output capacitor
ESR, multiplied by the load step magnitude, plus the output
capacitor ESL, times the load step di/dt. A positive load step
produces a negative output voltage spike and vice versa. A
large number of low-series-impedance capacitors are often
used to prevent the output voltage deviation from exceeding
the tolerance of some devices. One widely accepted solution
to this problem is output voltage “Droop”, or active voltage
positioning.
As shown in Figure 3 and Figure 9, the average channel
current is used to control the “Droop” current source,
IDROOP. The “Droop” current source is a controlled current
source and is proportional to output current. This current
source is approximately 87% of the averaged ISEN currents.
The Droop current is sourced out of the SOFT pin through
the Droop resistor and returns through the EA+ pin. This
creates a “Droop” voltage VDROOP, which subtracts from
the IMVP- IV™ and IMVP-IV+™ reference voltage on SOFT
to generate the voltage set point for the CORE regulator.
Full load current for the Intel IMVP-IV™ and IMVP-IV+™
specification is 32A. Knowing that the Droop Current,
sourced out of the SOFT pin, will be 87% of the ISEN
averaged currents, a “Droop” resistor RDROOP, can be
selected to provide the amount of voltage “Droop” required
at full load. The selection of this resistor is explained in the
following section.
Selection of RDROOP
Figure 11 shows a static “Droop” load line for the 1.484V
Active Mode. The ISL6217A, as previously mentioned,
allows the programming of the load line slope by the
selection of the RDROOP resistor.
VOUT,HI
VOUT,NOM
VOUT,LO
(0A,1.506V)
(0A,1.484V)
(0A,1.462V)
(25A,1.431V)
(25A,1.409V)
(25A,1.387V)
-3 m_
load line
IOUT,NL
STATIC TOLERANCE BANDS
IOUT,MID
IOUT,MAX
NOMINAL "DROOP" LOAD LINE
FIGURE 11. IMVP-IV ACTIVE MODE STATIC LOAD LINE
As per the Intel IMVP-IV™ and IMVP-IV+™ specification,
Droop = 0.003 (Ω). Therefore, 25A of full load current
equates to a 0.075V Droop output voltage from the VID
setpoint. Refer to Figure 3 and Figure 9, RDROOP can be
FN9107.3
June 30, 2005
ISL6217A
selected based on RISEN which is calculated through
Equation 3, rDS(ON), and Droop as per the Block Diagram or
the following equation:
R DROOP = 2.3 ⋅ (Droop ) ⋅
R ISEN
( Ω)
r(DSON)
M
(EQ. 6)
Diode Emulation
Diode emulation allows for higher converter efficiency under
light-load situations. With diode emulation active, the
ISL6217A will detect the zero current crossing of the output
inductor and turn off LGATE. This ensures that
discontinuous conduction mode (DCM) is achieved. In DCM,
conduction losses are reduced in the Low-Side MOSFET,
consequently boosting efficiency. The ISL6217A operates in
DCM in both deep and deeper sleep mode.
Adaptive Shoot-Through Protection
Both drivers incorporate adaptive shoot-through protection
to prevent upper and lower MOSFETs from conducting
simultaneously and shorting the input supply. This is
accomplished by ensuring the falling gate has turned off one
MOSFET before the other is allowed to turn on.
During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it reaches a 1V threshold, at which time the
UGATE is released to rise. Adaptive shoot-through circuitry
monitors the upper MOSFET gate-to-source voltage during
UGATE turn-off. Once the upper MOSFET gate-to-source
voltage has dropped below a threshold of 1V, the LGATE is
allowed to rise.
Component Selection Guidelines
OUTPUT CAPACITOR SELECTION
Output capacitors are required to filter the output inductor
current ripple and supply the transient load current. The
filtering requirements are a function of the channel switching
frequency and the output ripple current. The load transient
requirements are a function of the slew rate (di/dt) and the
magnitude of the transient load current.
The microprocessor used for IMVP-IV™ and IMVP-IV+™
will produce transient load rates as high as 30A/ns. High
frequency, ceramic capacitors are used to supply the initial
transient current and slow the rate-of-change seen by the
bulk capacitors. Bulk filter capacitor values are generally
determined by the ESR (Effective Series Resistance) and
voltage rating requirements rather than actual capacitance
requirements. To meet the stringent requirements of
IMVP-IV™ and IMVP-IV+™, (15) 2.2µF, 0612 “Flip Chip”
high frequency, ceramic capacitors are placed very close the
Processor power pins, with care being taken not to add
inductance in the circuit board traces that could cancel the
usefulness of these low inductance components.
capacitors. The bulk capacitor ESR and ESL determine the
output ripple voltage and the initial voltage drop following a
high slew-rate transient edge. Recommended are at least (4)
4V, 220µF Sanyo Sp-Cap capacitors in parallel, or (5) 330µF
SP-Cap style capacitors. These capacitors provide an
equivalent ESR of less than 3mΩ. These components
should be laid out very close to the load.
As the sense trace for VSEN may be long and routed close
to switching nodes, a 1.0µF ceramic decoupling capacitor is
located between VSEN and ground at the ISL6217A.
Output Inductor Selection
The output inductor is selected to meet the voltage ripple
requirements and minimize the converter response time to a
load transient. In a multi-phase converter topology, the ripple
current of one active channel partially cancels with the other
active channels to reduce the overall ripple current. The
reduction in total output ripple current results in a lower
overall output voltage ripple.
The inductor selected for the power channels determines the
channel ripple current. Increasing the value of inductance
reduces the total output ripple current and total output
voltage ripple; however, increasing the inductance value will
slow the converter response time to a load transient.
One of the parameters limiting the converter response time
to a load transient is the time required to slew the inductor
current from its initial current level to the transient current
level. During this interval, the difference between the two
levels must be supplied by the output capacitance.
Minimizing the response time can minimize the output
capacitance required.
The channel ripple can be reasonably approximated by the
following equation:
V − VOUT VOUT
∆ICH = IN
•
FSW • L
VIN
(EQ. 7)
The total output ripple current can be approximated from the
curves in Figure 10.
They provide the total ripple current as a function of duty
cycle and number of active channels, normalized to the
parameter KNORM at zero duty cycle,
K NORM =
VOUT
L • FSW
(EQ. 8)
Where L is the channel inductor value.
Specialized low-ESR capacitors, intended for switching
regulator applications, are recommended for the bulk
17
FN9107.3
June 30, 2005
ISL6217A
value, by the current multiplier value found, and the result is
the RMS input current which must be supported by the input
capacitors.
FIGURE 12. OUTPUT RIPPLE CURRENT MULTIPLIER vs
DUTY CYCLE
Find the intersection of the active channel curve and duty
cycle for your particular application. The resulting ripple
current multiplier from the y-axis is then multiplied by the
normalization factor KNORM, to determine the total output
ripple current for the given application. Find the intersection
of the active channel curve and duty cycle for your particular
application. The resulting ripple current multiplier from the yaxis is then multiplied by the normalization factor KNORM, to
determine the total output ripple current for the given
application.
∆I TOTAL = K NORM • K CM
(EQ. 9)
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use ceramic capacitors for
the high frequency decoupling, and bulk capacitors to supply
the RMS current. Small ceramic capacitors must be placed
very close to the upper MOSFET to suppress the voltage
induced in the parasitic circuit impedances.
Two important parameters to consider when selecting the
bulk input capacitor are the voltage rating and the RMS
current rating. For reliable operation, select a bulk capacitor
with voltage, and current ratings above the maximum input
voltage and the largest RMS current required by the circuit.
The capacitor voltage rating should be at least 1.25 times
greater than the maximum input voltage and a voltage rating
of 1.5 times is a conservative guideline. The RMS current
requirement for a converter design can be approximated
with the aid of Figure 13.
Follow the curve for the number of active channels in the
converter design. Next determine the worst case duty cycle
for the converter and find the intersection of this value and
the active channel curve. The worst case duty cycle is
defined as the maximum operating CORE output voltage
divided by the minimum operating battery voltage. Find the
corresponding y-axis value, which is the current multiplier.
Multiply the total full load output current, not the channel
18
FIGURE 13. INPUT RMS RIPPLE CURRENT MULTIPLIER
MOSFET Selection and Considerations
For the Intel IMVP-IV™ and IMVP-IV+™ application, which
requires up to 25A of current, it is suggested that 2 channel
operation with (3) MOSFETs per channel be implemented.
This configuration would be: (1) High Switching Frequency,
Low Gate Charge MOSFET for the Upper, and (2) Low
rDS(ON) MOSFETs for the Lowers.
In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes two
loss components: conduction loss and switching loss. These
losses are distributed between the upper and lower
MOSFETs according to duty cycle of the converter. Refer to
the PUPPER and PLOWER equations below. The
conduction losses are the main component of power
dissipation for the lower MOSFETs. Only the upper
MOSFETs have significant switching losses, since the lower
devices turn on and off into near zero voltage. The following
equations assume linear voltage-current transitions and do
not model power loss due to the reverse-recovery of the
lower MOSFETs body diode. The gate-charge losses are
dissipated in the ISL6217A drivers and do not heat the
MOSFETs; however, large gate-charge increases the
switching time tSW, which increases the upper MOSFET
switching losses. Ensure that both MOSFETs are within their
maximum junction temperature, at high ambient
temperature, by calculating the temperature rise according
to package thermal-resistance specifications.
PLOWER =
IO2 × rDS(ON) × (VIN − VOUT )
VIN
(EQ. 10)
FN9107.3
June 30, 2005
ISL6217A
2
PUPPER =
IO × rDS(ON) × VOUT
VIN
I ×V ×t
×F
+ O IN SW SW
2
regulation for the Intel IMVP-IV™ and IMVP-IV+™
application. The circuit uses 2 channels for delivering up to
25A steady state current, and has a 250kHz channel
switching frequency. This circuit also switches to single
channel operation for Deep and Deeper Sleep modes of
operation. For thermal compensation, PTC resistors are
used as sense resistors. The Output capacitance is less than
3mΩ of ESR, and are (4) 220µF, 4V Sp-Cap parts in parallel
with (35) high frequency, 10µF ceramic capacitors.
(EQ. 11)
Typical Application - 2 Phase Converter
Using ISL6217A PWM Controller - 38 Lead
TSSOP
Figure 14 shows the ISL6217A, Synchronous Buck
Converter circuit used to provide the CORE voltage
Vbattery
+5VDC
+5VDC
4 x 10 µF
1 x IRF7811W
98.8K_1%
1µF
BAT54
0.027µF
243K_1%
VR_ON
DPRSLPVR
DPSLP#
VID
MVP4_PGOOD
3.40K_1%
10_1%
0.8µH
1.5K_1%PTC
VDD
VBAT
1.20K_1%
DACOUT
ISEN1
DSV
PHASE1
UG1
FSET
BOOT1
PWRCH
EN
VSSP1
DRSEN
LG1
DSEN#
VDDP
ISL6217A
VID0
LG2
VID1 TSSOP VSSP2
VID2
BOOT2
VID3
UG2
VID4
PHASE2
VID5
ISEN2
PGOOD
VSEN
EA+
DRSV
COMP
STV
FB
OCSET
SOFT
VSS
ETQ-P3H0R8BA
2 x SI4404DY
0.33µF
1R5_5%
4.7µF
4 x 10 µF
1R5_5%
0.33µF
1 x IRF7811W
2200pF
0.8µH
10_1%
0.012µF
1.5K_1%PTC
13K_1%
36.5K_1%
No-Pop
30.1K_1%
1800pF
BAT54
2 x SI4404DY
+Vcc_core
ETQ-P3H0R8BA
4 x 220µF &
35 x 10µF
49.9K_1%
No-Pop
3.57K_1%
Analog GND
560pF
Power GND
FIGURE 14. TYPICAL APPLICATION CIRCUIT FOR THE IMVP-IV™ AND IMVP-IV+™ CORE VOLTAGE REGULATOR
19
FN9107.3
June 30, 2005
ISL6217A
Thin Shrink Small Outline Plastic Packages (TSSOP)
M38.173
N
INDEX
AREA
E
0.25(0.010) M
E1
2
INCHES
GAUGE
PLANE
-B1
38 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-153-BD-1 ISSUE F)
B M
SYMBOL
A
3
L
0.05(0.002)
-A-
0.25
0.010
SEATING PLANE
A
D
-C-
α
e
A2
A1
b
c
0.10(0.004)
0.10(0.004) M
C A M
B S
MIN
-
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-BD-1, Issue F.
MIN
MAX
NOTES
0.047
-
1.20
-
A1
0.002
0.006
0.05
0.15
-
A2
0.031
0.051
0.80
1.05
-
b
0.0075
0.0106
0.17
0.27
9
c
0.0035
0.0079
0.09
0.20
-
D
0.378
0.386
9.60
9.80
3
E1
0.169
0.177
4.30
4.50
4
e
0.0197 BSC
0.500 BSC
-
E
0.246
0.256
6.25
6.50
-
L
0.0177
0.0295
0.45
0.75
6
8°
0°
N
NOTES:
MILLIMETERS
MAX
α
38
0°
38
7
8°
Rev. 0 1/03
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
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Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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20
FN9107.3
June 30, 2005