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AR# 18780

描述

Keywords: ERROR:Place:17, placer, ICLK, OTCLK

In Virtex-II Pro devices, IOB tiles occasionally do not follow the common pattern in which four IOB sites are divided into pairs for the purpose of sharing clock routing resources. These pairs are normally LVDS pairs as well. In rare cases, the routing pair is not the same as the LVDS pair. (See sites H16, J16, and H17 in the XC2VP50 device for an example.)

In ISE 6.1i, the placer incorrectly assumes that the LVDS pairings can also be used to check the clock pairings. As a result of this incorrect check, the following failures can occur:

2. The placer might reject valid IOB constraints because of a bad clock resource check and fail with the error message:

"Phase 8.24 ERROR:Place:17 - The current designer locked placement of the IOBs dimm1_dq_io<38> and dimm1_dqs_out<13> makes this design unroutable due to a physical routing limitation. This device has a shared routing resource connecting the ICLK and OTCLK pins on pairs of IOBs. This restriction means that these pairs of pins must be driven by the same signal or one of the signals will be unroutable. Before continuing with this design please unlock or move one of these IOBS to a new location."

解决方案

This problem has been fixed in the version 6.2i and 7.1i software under environment variable control. The environment variable must be set to enable the fix. If MAP was run with the timing driven option (-timing), it will be necessary to rerun MAP after setting the variable, before proceeding to PAR.

Windows

SET XIL_PAR_V2P_DDR_PAIR=1

Solaris

setenv XIL_PAR_V2P_DDR_PAIR 1

Linux

setenv XIL_PAR_V2P_DDR_PAIR 1

NOTE: The specific problem described in this Answer Record no longer exists in the 8.1i software. There is no need to set the environment variable. If the Place:17 error is seen in ISE 8.1i or later, the problem is either the more general case described by (Xilinx Answer 11747), or the bug described by (Xilinx Answer 22765).