Two versions of Xeon, code-named “Potomac” and “Cranford,” are scheduled to arrive in systems in the next 90 days. The processors are designed for four-processor servers, with Potomac geared for high-end work and Cranford for lower-priced machines. One major difference will be in the amount of high-speed cache memory; Potomac will include 8MB but Cranford will employ less. The Potomac and Cranford processors are at the heart of a new “platform” at Intel that also includes the new 8500 chipset codename Twin Castle. The 8500-based systems will introduce technology for the crucial 2006 transition to dual-core chips. For the first time, there will be two data pathways called front-side buses that connect the processor to the rest of the system. Also coming with the 8500 will be DDR2 memory, PCI Express input-output systems, demand-based switching to lower processor speed and power consumption during idle moments, memory reliability improvements and technology to correct errors in data transferred within the system. The front-side bus will run at 667MHz compared to the current 400MHz speed. Two versions of Xeon, code-named “Potomac” and “Cranford,” are scheduled to arrive in systems in the next 90 days. The processors are designed for four-processor servers, with Potomac geared for high-end work and Cranford for lower-priced machines. One major difference will be in the amount of high-speed cache memory; Potomac will include 8MB but Cranford will employ less. The Potomac and Cranford processors are at the heart of a new “platform” at Intel that also includes the new 8500 chipset codename Twin Castle. The 8500-based systems will introduce technology for the crucial 2006 transition to dual-core chips. For the first time, there will be two data pathways called front-side buses that connect the processor to the rest of the system. Also coming with the 8500 will be DDR2 memory, PCI Express input-output systems, demand-based switching to lower processor speed and power consumption during idle moments, memory reliability improvements and technology to correct errors in data transferred within the system. The front-side bus will run at 667MHz compared to the current 400MHz speed.