IBM processor hints at Apple's 64-bit future

SAN MATEO, Calif.  IBM Corp. may give a peek into Apple Computer Inc.'s 64-bit future when it details a new version of its Power4 microprocessor next week. Aimed for use in desktops and low-end servers, the 64-bit Power4 could be IBM's first PowerPC-compatible chip to support the Altivec multimedia instruction extensions defined by Apple and Motorola Inc.

The IBM device is one of about 18 new processors that will be described at the Microprocessor Forum 2002, to be held Oct. 14-17. "I expect there will be a fair amount of discussion about this part," said Peter Glaskowsky, editor-in-chief of The Microprocessor Report, which hosts the annual gathering.

Unlike IBM's original Power4, the device to be described next week will use one, not two, internal processor core and will support extensions that make the Power4 compatible with the PowerPC architecture. "Because it supports a full 32-bit environment, this chip should be able to boot the Mac OS just fine," Glaskowsky said.

An IBM spokesman would not say if Apple plans to use the chip to move its desktops to a full 64-bit operating system.

"Apple would have to be crazy not to use this part," said Glaskowsky. "Its performance will be in the upper reaches of any CPU. I can't comment on its speeds, but they are good numbers. Apple would be able to produce for the first time machines that not only have great performance but support full 64-bit addressing."

The chips could be used in Apple's new line of Xserve servers even in a 32-bit mode. However, Apple would have to heavily rework its Mac OS, which has just gone through a major release cycle, to support 64-bit addressing. Therefore the company, which keeps a tight lid on unannounced products, might not be ready to detail its plans for the chip until the end of 2003.

"Apple has a whole lot of work to do to fully make use of this part," said Glaskowsky of the chip, which sports an eight-stage superscalar pipeline and supports symmetric multiprocessing.

Likely reference

The new Power4 also includes "a vector processing unit implementing over 160 specialized vector instructions," according to the conference program. That's likely a reference to the Altivec instruction set defined by Motorola and Apple to boost multimedia performance by providing special vector processing capabilities in the PowerPC instruction set.

IBM had focused for some time on building fast PowerPC parts for Apple, rather than adopting the relatively complex Altivec extensions. The new Power4 seems to mark a change in course.

Among other news at MPF next week, startup MemoryLogix will announce a Pentium II-class synthesizeable X86-compatible core for embedded applications. The part's die size and cost will be comparable to current 486 parts, Glaskowsky said. It will be capable of running at several hundred MHz, and users will be able to customize the chip's cache size and elect whether or not it uses a floating-point processor, he added.

The Cisco T3 is the company's third-generation Toaster network processor designed for internal use on Cisco systems. "Seeing what Cisco has done and how fairly straightforward their device is should be interesting  especially since it means this company will not be a customer for some other vendors," Glaskowsky said.

Among embedded processors, Tensilica Inc. will discuss a new VLIW platform that will become a base architecture for the company. And Motorola will detail version 5 of its ColdFire embedded 32-bit processor.

For its part, ARM Ltd. will discuss the first two ARM 11 processors. The "400-MHz+ cores feature an 8-stage pipeline, a new memory system, a vector floating-point unit, and a quad 64-bit Amba AHB-lite bus interface," according to the conference agenda.

"These processors sort of stretch how much performance you might want to have in a cellphone, but they should find good use in PDAs," Glaskowsky said.

Separately, Samsung Electronics Co. Ltd. will discuss its plans for a 1.2-GHz version of an ARM 10 processor built in a 130-nanometer (0.13-micron) process.