Contents

ARM Clocks

The clocks are controlled by two registers at 0xE3103000 (ScePervasiveBaseClk). Currently, it is unknown how the values are interpreted. However, 0xE3103000 (one word) takes values 0 to 16, and increases clock speed while 0xE3103004 (single byte) takes values 0 to 8 and decreases clock speed. It is likely related to a PLL multiply and divide function. The input clock signal comes from a P1P40167 clock synthesizer (found on the bottom of the board under the main SoC). It takes a 27MHz crystal and generates a 37MHz clock which feeds directly into the SoC's internal PLL.

The following are tests run to determine what the values of each register corresponds to. It appears that the maximum clock speed is 500MHz and the minimum clock speed is 16MHz.

0xE3103000

0xE3103004

Clock Speed (MHz)

0

0

37

0

1

35

0

2

32

0

3

29

0

4

27

0

5

24

0

6

22

0

7

19

0

8

16

1

0

37

1

1

35

1

2

32

1

3

30

1

4

27

1

5

24

1

6

22

1

7

19

1

8

16

2

0

37

2

1

35

2

2

32

2

3

30

2

4

27

2

5

24

2

6

22

2

7

19

2

8

16

3

0

79

3

1

74

3

2

69

3

3

63

3

4

58

3

5

53

3

6

48

3

7

43

3

8

37

4

0

107

4

1

100

4

2

93

4

3

86

4

4

79

4

5

72

4

6

65

4

7

58

4

8

51

5

0

162

5

1

152

5

2

142

5

3

131

5

4

121

5

5

110

5

6

100

5

7

90

5

8

79

6

0

218

6

1

204

6

2

190

6

3

176

6

4

163

6

5

148

6

6

135

6

7

121

6

8

107

7

0

329

7

1

308

7

2

287

7

3

266

7

4

246

7

5

225

7

6

204

7

7

183

7

8

162

8

0

439

8

1

411

8

2

384

8

3

356

8

4

329

8

5

301

8

6

273

8

7

246

8

8

218

9

0

494

9

1

463

9

2

432

9

3

401

9

4

370

9

5

339

9

6

308

9

7

277

9

8

245

10

0

328

10

1

308

10

2

287

10

3

266

10

4

245

10

5

225

10

6

204

10

7

183

10

8

162

11

0

37

11

1

35

11

2

32

11

3

30

11

4

27

11

5

24

11

6

22

11

7

19

11

8

16

12

0

121

12

1

113

12

2

105

12

3

97

12

4

90

12

5

82

12

6

74

12

7

66

12

8

58

13

0

245

13

1

230

13

2

214

13

3

199

13

4

183

13

5

168

13

6

152

13

7

136

13

8

121

14

0

439

14

1

412

14

2

384

14

3

356

14

4

329

14

5

301

14

6

273

14

7

246

14

8

218

15

0

494

15

1

463

15

2

433

15

3

401

15

4

370

15

5

339

15

6

308

15

7

277

15

8

245

16

0

37

16

1

35

16

2

32

16

3

29

16

4

27

16

5

24

16

6

22

16

7

19

16

8

16

Clock Gating

Individual devices can be clock gated to preserve battery. To request the clock for a device to be enabled, do *REG32(0xE3102000 + dev_off) |= mask and to request the clock to be turned off do *REG32(0xE3102000 + dev_off) &= ~mask.

Reset

Devices must be put out of reset before they are first used. To put a device out of reset, do *REG32(0xE3101000 + dev_off) &= ~mask. To put a device in reset, do *REG32(0xE3101000 + dev_off) |= mask.