This paper presents a detailed analysis of the behavior of a novel fault-tolerant 32-bit embedded CPU as compared to a
default (non-fault-tolerant) implementation of the same processor during a fault injection campaign of single and double faults. The
fault-tolerant processor tested is characterized by per-cycle voting of microarchitectural and the flop-based architectural states,
redundancy at the pipeline level, and a distributed voting scheme. Its fault-tolerant behavior is characterized for three different
workloads from the automotive application domain. The study proposes statistical methods for both the single and dual fault injection
campaigns and demonstrates the fault-tolerant capability of both processors in terms of fault latencies, the probability of fault
manifestation, and the behavior of latent faults.