The design of optimal analog and mixed signal
(AMS) very large scale integrated circuits (VLSI) with lesser design cycle time is a challenging task for the integrated circuit (IC) designers. Voltage Controlled Oscillator (VCO) is a radio
frequency integrated circuit (RFIC) having wide range of applications. This paper presents a new approach to design a ring oscillator (RO) with optimum performance with only one design
cycle. The optimal figure of merit performance for a RO with a constraint of achieving a desired centre frequency is observed using a new technique which combines multi-objective
optimization with differential evolution (CMODE). The RO is designed by considering the design parameters extracted from constrained CMODE in Cadence Virtuoso analog design environment (ADE) using gpdk090 library. The simulation results are compared with the CMODE predicted indices and are
observed to be in good agreement with it. In this work RO circuits with 9 stages of inverters are considered to be designed for 2 GHz centre frequency with the limitations imposed by
gpdk090 library. Results of exhaustive simulation and experimental studies for these ROs are presented here to verify the reduced design cycle time and superior performance offered by the proposed design methodology.