Asynchronous VLSI (idea)

As described in clockless computing, asynchronous design involves no global clock signal. This means the chip does not rely on any sort of timing assumptions; the circuits should theoretically work even if you slowed down any given signal by any amount.

Asynchronous circuits are different from clocked, synchronous systems in that they can actually be mathematically characterized. (Thus, computer scientists are happy). One can prove, for example, that the class of truly delay-insensitive circuits is very small. Circuits made out of such elements would not be able to do much at all.

One of the smallest concession to practicality is assuming that signal forks are isochronous. That is, if a given wire travels from A to B and C, a signal sent from A reaches B and C at the same time. With just this assumption, relatively easy to satisfy, the range of available circuits expands to just about anything one would need. Complete microprocessors have been fabricated using this method

In general, asynchronous VLSI can be harder to grasp at first than standard design. The restrictions required to ensure delay insensitivity are sometimes subtle; logic checking tools are essential. However, the benefits are significant: Unconstrained by a clock, the circuits run as fast as they possibly can, making chips fast. And because a part of the chip that is not involved in a calculation is doing nothing (unlike in a normal chip, where the clock signal is always causing transistors to switch in the whole chip), power consumption tends to be far lower.

Commercial asynchronous designs have focused on the low power; research is ongoing to improve design techniques and automate the process further.