Eagle’s popularity is partly due to the sheer number of parts and footprint libraries available for it. Sometimes you can’t find the part you need in an existing library though, and it’s time to make your own. Making a new part in Cadsoft Eagle can be intimidating for new users, but the guide below shows how we make our own Eagle parts step by step. Alternately you can check it out on the Wiki.

A part is composed of 3 sections:

Symbol – the thing you connect to other parts on the schematic

Package – the footprint on the PCB that you attach the part to

Device – a symbol and a package together. Symbol connections are assigned to package pins

Example part

Lets take the LM5022 as an example, a simple 10 pin chip. The datasheet shows the connection list we need to build the symbol.

The datasheet also has packaging dimensions we need to build the footprint.

It’s very important to have the landing pattern and not just the pin dimensions. Some datasheets will only give the pin size, the landing pattern is larger and optimized to help the chip solder easily.

Making the Symbol

Let’s start with the symbol. Symbols are what you connect to other parts in the schematic diagram. We’ll design this one as simple as a block with pins.

Create a new symbol by clicking the symbol icon in the library editor

Hint: If you haven’t created a library yet just go to Panel > File > New > Library in Eagle Control

A window will open and ask for a symbol name. Enter the chip name or part number and click OK, then click Yes when asked to create a new symbol.

In the chip’s datasheet find the pinout or connection diagram, this will be the basis for our symbol

Start making the symbol by using the ‘wire’ command in the 94Symbol layer as an outline, ICs are rectangular so we just make a simple box to represent the chip. Always put the symbol on its center (0 0) as this will be your anchor when moving in the schematic.

Place pins on the chip. Click the pin button, then click on the symbol to drop pins.

Hint: When placing the pins just leave the current settings for the grid (0.1inch), this makes the connection easier to snap when working with the device later.

Name each pin by using the ‘info’ command, and clicking on the pin. Name the pins according to the datasheet to make life easier later. You can tweak other pin attributes in the info window too.

Add a space for the part designation on the 95Names layer. This is where the part number such as IC1, C3, or R2 will appear on the schematic.

You can also place the ‘value’ label for the part on the 96Values layer. We don’t usually assign a value because we usually change it in the schematic design phase.

Hint: The prefix ‘>’ is not necessary for these texts. It’s just a style decision.

Making the Footprint

Footprints, sometimes called landing patterns, define where a chip attaches to a circuit board. The footprints will be the silver shiny pads that you’ll solder parts to later. Eagle calls this a package.

To access the package editor click the ‘package’ icon.

Name the package, this time by the package type which is MSOP-10 for this chip.

The datasheet gives the units in inch and mm. We’ll go for the metric unit, but you could also use inches.

Check the datasheet for the dimensions of the recommended pin pads. We’ll use this to make the optimal pad in our footprint.

Here, the manufacturer recommends 0.3 x 1.02. This area will be slightly larger than the pin itself, and is optimized for the package type.

Important: It’s very important to have the landing pattern and not just the pin dimensions. Some datasheets will only give the pin size, the landing pattern is larger and optimized to help the chip solder easily.

This is a surface mount part, so we click ‘SMD’ to get the right pad. For through-hole parts click the round green via next to the SMD button.

Set the dimension of the pad to the values we pulled from the datasheet.

There are many ways to place the pad in the correct position. You can place it manually if the grid you set (View > Grid) fits the pad pitch. Alternately you can calculate the correct pad coordinates, we’ll use this method.

What we’re going to do is calculate the location of the center of each pad using the values from the datasheet. This seems a little tedious, but we think it’s easier than messing with the grid values constantly.

The formula for the X axis is Px=(n-1)Dpx where:

n is the order of the pad from the center

Dpx is the major pitch distance of each pad

For Pad 1 X (3rd pad from X center)

Pad1X=(3-1)0.5 will be 1. Since pad 1 is located on the 3rd quadrant its X value will be negative hence -1.

The formula for the Y axis is Py=Dpy/2 where:

Dpy is the minor pitch distance of each pads

For Pad 1 Y

Pad1Y=4.8/2 will be 2.4. The lower pads are below the X axis, and should be negative. The Y location of Pad1 is Pad1Y=-2.4. On this chip pins 1-5 will have negative Y axis value (-2.4), and pins 6-10 will have a positive Y axis value (2.4).

Pad2X=(2-1)0.5, and it’s still on the 3rd quadrant so the value is -0.5

Pad2Y=(4.8)/2, still below X, -2.4

Pad3X=(1-1)0.5, yields 0

Pad3Y=(4.8/2), still below X, -2.4

Pad4X=(2-1)0.5, now we’re on the fourth quadrant, which is on the positive side of X axis. This will be positive 0.5

Pad4Y=(4.8/2). still at -2.4

Now we have: Pad1 at (-1 -2.4), Pad2 at (-0.5 -2.4), Pad3 at(0 -2.4), and Pad4(0.5 -2.4). Repeat for each pad. Remember that the Y values only need to be calculated once.

Enter the coordinates into the command box at the top of the library editor as shown

Press enter. All pads are now in place

The order of the coordinates in the command box assigns numbering to the pads. Its not necessary to do it like that. You can always use the ‘info’ command and edit the pad name or fix mistakes.

Now we’ll make the chip package and pin outline, again using the values from the datasheet. This is a 3×3 mm chip with 0.23x.95 sized pins.

Use the ‘wire’ command to draw the outline on the top silk 21tPlace layer.

We used the package dimensions in the datasheet to calculate the coordinates of the chip’s 4 edges.

It’s nice to see where the actual pins will be when you route the PCB. We’ll create a pin reference on the Document layer. We use the Document layer so the reference will not be included on the top silk or overlap the pin pads.

Select the ‘Rectangle’ command and set the layer to top Document 51tDocu layer

Create a single pin centered on the part origin, this makes it easy to copy and snap onto our pads. We use a rectangle that is half of the width of the pad (0.23/2= 0.115).

Use the ‘Copy’ command to copy the first pin. Place a copy on each pad with its base touching the chip outline.

When we’re building the board we need to know how to position parts. Mark pin 1 with a zero width ‘circle’ on the top silk 21 tPlace layer. The zero width circle will fill up.

Finally put a ‘name’ text near the chip, on the top silk name layer 25 tNames, and we’re done.

Making the Device

Device links the symbol and package and makes the whole part.

Create a new device by clicking the ‘Device’ symbol

Import the symbol by clicking the ‘Add’ icon.

A window will pop-up with a list of symbols in the library. Pick the symbol that we made before and click OK.

Now import the package by clicking the ‘New’ button.

Eagle highlights packages that will fit the symbol. Choose the package/footprint we created before.

In the variant name box enter the same name as the package. This can be used to make different sizes of the same device. Click OK.

The footprint appears on the package list with an ‘!’ icon showing that the symbol and the package are not linked or connected yet. Click the ‘connect’ button to link both.

After clicking the connect button, another window will appear showing unpaired pins.

Match each symbol pin with the corresponding pad and click connect. Each pin should only connect to one pad.

Finally, click the ‘Prefix’button and specify a prefix for this chip. Eagle will automatically increment this when you make your schematic, eg IC1, IC2, IC3. It will also identify this part in your bill of materials.

Save the library and you can try your newly created part.

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on Wednesday, March 7th, 2012 at 3:00 pm and is filed under how-to, tutorials.
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Nice tutorial, but why do you bother constructing the device by hand if you can use a ULP provided by cadsoft?
make-symbol-device-package-bsdl.ulp is your friend, the documentation can be found in the ‘doc’ directory of your eagle installation.

you are right when it comes to packages that have some special layout. But I would use the ULP even for packages with as few pins as SOIC-8 or even SOT-23 with because the process of using the ulp is less error-prone than doing it by hand.
Even SOT-23 with 5 pins is easily constructed with the ulp and only needs some finishing touch.

However, I was hoping to see a good explanation of how to keep the VCC and GND pins separate. This tutorial combines them in the same schematic symbol which most designers don’t do because it’s less distracting to put power pins (and decoupling caps) in a corner of the schematic (or on a separate sheet). And it seems that some symbol libraries do this different from others.

Personally, I really *don’t* like separating the VCC/GND pins, and I especially hate when they’re hard-coded to “VCC” and “GND”. There have been too many times when I’ve had multiple power rails on a board and the hidden power connection is stuck on a power rail that I don’t want it on. I also really like the explicitness of knowing which bypass caps go to which packages, which is also obscured when all of the bypass are herded together into one corner of the schematic.

I think that there’s a movement away from implicit power pins, which I’m a big fan of. What can I say, I’m an explicit kind of guy. If there’s a schematic middle ground that answers my concerns, I’m interested in hearing/listening about a better way — but I find the practice really annoying/confusing/unclear.

Name bypass caps after their package: C1 for U1, C2 for U2, etc. Then you can keep track of the pairings more easily. Special cases with parallel caps or large caps for regulation can be special-cased as needed.

I agree entirely. VCC pins are absolutely part of the design and I have seen even fairly experienced PCB layout guys not have a clue where to put anything because half of the circuit doesn’t really exist. On the other hand, separating power pins out to a separate but visible part of the package can be a really neat way of achieving all of the above and I have done that with some intensive analogue circuits in the past where feedback resistances and capacitances are smothering the area around an op amp.

It’s for the same reason that I use actual wires, messy as they may be and avoid net name joins because it’s not really that humanly readable. Obviously, off page connectors are an exception.

The comment from “rsdio” is fairly sensible except for two aspects:
1) it’s common to re-annotate a board so that part idents go numerically from top left to bottom right on the PCB to make finding and debugging easier
2) when you start putting bypass caps on 484 pin BGAs you tend to find you need rather more than one bypass cap per device ;)

When I have more than one bypass cap per chip, I just continue to use the number sequencing before moving to non-bypass caps. So, if I have 20 chips, they’re U1 through U20, and the primary bypass caps are C1 through C20, followed by C21 through whatever for the additional bypass caps. I prefer to keep all caps of a particular value in sequence, otherwise the assembly ship might get confused about the counts for each part – at least that’s been my experience. I don’t spend much time debugging boards; far more time is spent communicating with assemblers.

*make a symbol with all the pins except the VCC and VSS (GND) VDD VEE etc….
*make a separate symbol of a single pin…
*make a device, add the symbol for most of the pins, and add as many single pin symbols as there are in the device…connect the dots :D

Nice tutorial, but what would be even more useful is how to modify/incorporate existing symbols to make new ones. It’s crazy to have to reinvent the pads for an SO-8 a million times. Often symbols just need a little tweaking. Also, as Eagle versions change they no longer match your tutorial -so specify which ver. yours applies to.

Finally, users: Be sure to use the proper reference designations (i.e. Q for transistors, etc.) -see the Wikipedia page “Electronic symbol” for a list.

Reusing packages and symbols is a great suggestion, Steve. The first step is to find out whether what you want exists, and I have even resorted to using Unix grep to scan the Eagle libraries. Once you find a symbol, your aesthetics are the only criterion, but you should double-check packages to make sure they’re accurate. The next step is to copy the symbol and/or package from whatever library you found it in to a library of your own making. As far as I know, devices must be made from symbols and packages that appear in the same library, so if you want to borrow an SO-8 then you just have to copy it to your own library where you can reuse it many times. You also have the benefit of customizing various aspects or even improving the package to match your assembly process.

In v5, you typically create multiple pins with the same name, appending @1, @2, etc. Each pin connects to a single pad, but the similarity of the names makes it obvious by convention. It’s not as convenient as having a single pin, but it does allow you to control distinct connections to each pin.

How can I get rid of the “P$” text on pins in my schematics? For example, I can never get pin 1 of an IC to have the simple text “1” beside it, or pin 2 to have the simple text “2” beside it, etc.. Instead, the pins always have the “P$” prefix.

This is very annoying because it makes a “noisy” and messy schematic. Does the “P$” signify anything specific? If so, I’d like to know what it means. I’m assuming it is something useful. And even if it does signify something useful, I’d still like to be able to shut it off and have plain numeric pin numbers on my schematics.