Abstract

In this paper,we present a low latency finite Field multiplier over GF(2) that is used in Cryptographic applications for secure data encryption and decryption which deals with discrete structure and mathematical arithmetic. Since it uses modular arithmetic operation,It is found that it has the latency of m cycles. To overcome this problem, we proposed an efficient software implementation of high speed montgomery multiplier over GF(2) in FPGA for pentanomial which is based on residue number system and it uses the concept of parallel processing in which multiplication is decomposed into number of independent units and “pre-computed addition” techniques. The proposed design involves significantly less delay and power complexities compared to traditional multipliers.