At 09:31 PM 6/4/2002 -0400, Mitch Berkson wrote:
>I'd like to draw graphical dashed lines in a schematic to indicate guard
>traces which should be placed during PCB layout. Is there a way to do
>this in Protel 99SE SP6?

Advertising

Others have noted how to place a dashed line, and also that such a line has
no incorporated intelligence, it is only a note to the PCB designer.
However, it is possible to go further than that.
I assume that the guard traces are to be grounded, since they would be
positively harmful if they were not. So one would place a jumper at the
ground connection (whether this is at the driving end or the receiving end
depends on the design, but if it is to be grounded at more than one end, it
should be grounded *frequently* along its length to a solid ground,
probably a plane).
this jumper is what we have called a "virtual short." There are two ways to
implement it.
(1) a jumper footprint can be created that has a gap of, say, 4 microinches
between rectangular pads, and a design rule allows that particular
footprint to have a gap of 2 microinches. If boards were always fabricated
according to nominal values and to the limits of the technology (which is
well above the microinch region), this gap would never appear on the
finished boards. However, we have seen cases where round-off error in the
gerber generation, coupled with poor control of the aperture assignment and
other conditions, has resulted in a gap on the order of 1 mil on the
gerber, which has then been opened by an assumption-making fabricator to a
fabricatable dimension.... The technique is still useful, but one would
want to ensure that the aperture assigned is rounded up, and this is enough
of an opportunity for error that I now prefer the second method.
(2) a jumper footprint is created that has a shorting bar placed on a
mechanical layer. One of the copper layers is chosen as appropriate to
which to add the short, and the gerber definition for this layer is
eliminated from the CAM manager gerber control file (most of us only have
one just file for a design). A different file is created by copying the
first, and all other layers are eliminated from that file except for the
copper layer in question; then the mechanical layer dedicated to the short
is merged in photoplot with the copper layer. this additional CAM control
file is given a descriptive name so that future generations do not become
confused. (Note, however, that if the shorting bar is forgotten, it should
be a simple matter to short the jumper footprint manually on the PCB,
assuming that the short lives on an outer layer. I wish all
design/fabrication errors were as easy to fix....)
The mech layer used for the short is also given a descriptive name, such as
Top_Layer_Shorts.
(Note also that if all the CAM files are checked for plotting and left that
way, the copper layer with the short will routinely be plotted with all the
other files; this is pretty much set-and-forget.)
A combination of the two techniques *could* be used, which would leave it
very unlikely that the gap would ever be present.
Both these techniques fool Protel into thinking that the net to be
controlled is isolated from ground; one controls the grounding point by
controlling the placement of the short, which is highly desirable behavior.
Protel does not have, unfortunately, a signal pair routing constraint,
which would make this process even more controllable. But there is
Tools/Outline_Selected_Objects, which would add the guard traces, which
could then be selected with "select connected copper" and globally edited
to the appropriate subground net (i.e., the apparently isolated net created
by placing the virtual short on the schematic, which would likewise be
given a descriptive name, such as "DETECTOR SHIELD" or the like.) After
editing the outline to the appropriate name, the outline would be broken
and the virtual short moved into position. DRC will then correctly check
the routing.
Similar techniques allow the creation and control of other kinds of
subnets, such as star grounds, single-point connected analog/digital
grounds, etc; also the process has been used to create RF components where
copper is physically connected (at DC) but needs to function and be treated
as if it were not.
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* To post a message: mailto:[EMAIL PROTECTED]
*
* To leave this list visit:
* http://www.techservinc.com/protelusers/leave.html
*
* Contact the list manager:
* mailto:[EMAIL PROTECTED]
*
* Forum Guidelines Rules:
* http://www.techservinc.com/protelusers/forumrules.html
*
* Browse or Search previous postings:
* http://www.mail-archive.com/proteledaforum@techservinc.com
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *