Designing can be anyone’s cup of tea … but it is surely not a bed of roses. Developing a good and robust design is what really matters and contributes to the development of design on FGPA and finally on an ASIC. Tips, tricks and ideas presented in this paper are like a small drop in the ocean of efficient designing techniques, but they surely will help designers to take the first step towards developing efficient designs. The scope of this paper is to provide designers with state machine coding styles, efficient ways of writing code, portability from FPGA to ASIC, implementation of internal memories in FPGA, design tips for multiple clock designs, clock gating, clock management, using resets efficiently, synchronous designs and problem with latches.