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All IP blocks, macro libraries, wrapper files and testbench files are compiled and stored in the simulation library. When we ran the program compedklib all Xilinx IPs and Xilinx macro libraries were compiled. See Part 13 (Compiling everything) for information on how to compile the EDK libraries. Here is a view of the simulation database:

Library Name

Directory Path

Description

unisim

../database/macrolib/unisim

Unit delay macro library

simprim

../database/macrolib/simprim

Timing simulation macro library

XilinxCoreLib

../database/macrolib/XilinxCoreLib

Xilinx Core Functions

edklib

../database/edklib/ip_name

Xilinx EDK IPs

userlib

../database/userlib/user_ip_name

User IPs

top

../database/top_design

Top entity, IP wrappers

testbench

../database/testbench/testcase_name

Testbench+testcases

The cds.lib file

The mapping of library names to physical file locations is done in the cds.lib file which must be referenced in the NCsim compile script. When we compiled the simulation libraries using compedklib this cds.libwas generated for us. This file contains all the available IPs and is overkill for us. Let's find out exactly which libraries we need and remove the unused ones. We will open the wrapper files and look for used libraries:

From now on we will use the Mongoose simulation environment for our simulation setup. Here everything is setup to compile the Embedded Test Controller IP block. ETC_block_verilog_v1_00_a.def contains all the Verilog HDL files defining the ETC.

During the HDL generation a bram VHDL model (lmb_bram_elaborate.vhd) has been generated and stored in the directory: ../xps/hdl/elaborate/lmb_bram_elaborate_v1_00_a/hdl/vhdl. We will compile this model and store it in the simulation database: $ETC_VERIFICATION/database/ncsim/userlib/lmb_bram_elaborate_v1_00_a using the library name lmb_bram_elaborate_v1_00_a.

Compiling Verilog wrappers

The ETC_system_verilog_v1_00_a.def contains all the Verilog wrappers. In our case only the ETC wrapper.

When compiling Verilog code you almost every time get a message telling you that some modules are missing timescale directives. The easiest way to fix this problem is to have a separate timescale file only containing a timescale directive. Like this: timescale 1ns/10ps. I call this file timescale.v and put it as the first file in the Verilog compile script.

Compiling VHDL wrappers

The ETC_system_vhdl_v1_00_a.def contains all the VHDL wrappers and the top entity.

This line in the cds.lib file defines the name and the location of the wrapper simulation database:

define top /home/svenand/root/projects/ETC/verification/database/ncsim/top_design

Elaborating the design

We have now compiled the whole design and are ready to elaborate. Here is the elaboration script generated from Mongoose:

To find out more about these warnings we can execute the following commands:

==> nchelp ncelab CUDEFB

nchelp: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems, Inc.ncelab/CUDEFB = No explicit binding mechanism was found for the component instance in the form of a configuration specification or a component declaration. Default binding occurred with an entity having a visible entity declaration which had the same simple name as that of the instantiated component.

I do remember overhearing something about this particular message. Default binding is a perfectly normal thing todo, and is standard VHDL. However, some customer was trying to use a methodology of requiring explicit binding foreverything. To enforce this, they wanted a warning produced whenever default binding was used instead. As a result,everyone else has to put up with a bunch of warnings that they didn't care about.I think we can ignore this warning. We will add this line to the elaboration script: -nowarn CUDEFB

==> nchelp ncelab CUNOTB

nchelp: 05.83-p003: (c) Copyright 1995-2006 Cadence Design Systems, Inc.ncelab/CUNOTB = The (hierarchically) named component instance was not bound to an entity declaration along with a corresponding architecture body [5.2.1.1]. When this occurs, the component instantiation statement designated by the label in the hierarchical name shown has no effect [12.4.3]. This may have been due to a non-successful search through the binding search order. Following is the search order for all default bindings 1) A design unit made visible with a USE clause visible to the architecture instantiating the component. 2) A design unit made visible with a USE clause visible to the entity of the architecture instantiating the component. 3) A design unit available in the library to which the component was compiled. 4) A design unit in the WORK library. One of the above rules must provide for an entity to which the instance can be bound. Using other options to expand the search for default bindings can impact the ncelab performance. The user may first want to try modifying the design so that an entity can be found using the above stated rules. In most cases, it would imply adding appropriate USE clauses or compiling components into the same library to which the corresponding entity has been compiled.

This warning is a more serious one. We have things missing in our design. Here is the elaboration log file. We have to get rid of these warnings before we can continue.I will ask Xilinx for help by creating a WebCase. The answer from Xilinx came the next day and was a reference to the Answer Database #19446. In that example they used the option -lib_binding to ncelab. That was the answer to my problems.

Using the -lib_binding and -relax options

In the NC-VHDL Simulator Help manual we can read the following:

By default, the elaborator adheres to a strict interpretation of the VHDL LRM, which states that you must use LIBRARY statements with corresponding USE clauses in the source code to provide visibility to the declarative region that an unbound instance resides in. To bind component instances to compiled design units in the libraries, the elaborator:

Uses explicit binding indications

If there is no explicit binding indication, the elaborator tries to bind the component to in order:

A design unit made visable with a USE clause given to the architecture instantiating the component.

A design unit made visable with a USE clause given to the entity of the architecture instantiating the component.

A design unit available in the library into whjich the component was compiled.

A design unit in the work library

If a binding cannot be found, the elaborator generates an error (unbound ...).

To extend the binding rules there are two options we can use:-lib_binding-relax

We will use the -relax option which extends the set of binding rules with the following rules:

A design unit made visable with a LIBRARY clause given to the architecture instantiating the component (no corresponding USE clause).

A design unit made visable with a LIBRARY clause given to the entity of the architecture instantiating the component (no corresponding USE clause)

A design unit in a library defined in the cds.lib file. If a binding has not been found the elaborator opens the cds.lib file and searches all of the libraries that are defined.

Specify the timescale precision for VHDL

According to the IEEE 1076-1993 VHDL Language Reference Manual (Section 3.1.3.1), the primary unit of type TIME (1 femtosecond) is, by default, the resolution limit for type TIME. All simulations run in femtoseconds by default. Use the -vhdl_time_precision option to specify a secondary unit of type TIME as the resolution limit. Setting the timing resolution to a coarser value may increase simulation performance, as the simulator will not default to femtoseconds. We will use 1ps as our timing resolution.