From an IT-services (information technology) standpoint, that means transparently supplying analog voice, fax, and Voice-over-IP (VoIP) capabilities simultaneously with basic data services. From a hardware standpoint, it implies autosensing services such as various high-speed versions of Ethernet SONET, Fibre Channel, T1/E1, and older modes. It also suggests a considerable challenge extracting clock and data signals from all those inputs.

Indeed, it is a challenge. Yet none of the base frequencies for the various standards are harmonically related. For Gigabit Ethernet and 10-Gigabit Ethernet (10GE), they are 625.000 and 644.53125 MHz, respectively. For SONET/SDH, the base frequency is 622.08 MHz. For Fibre Channel, it is 657.421875 MHz. Each of these frequencies is further complicated by adding a forward error correction (FEC) factor. While FEC ratios are established as standards, there are several possibilities, such as 255/238, 255/237, 15/14, and 239/237.

How have clocks in multiservice routers been implemented?
Because of the different standards, OEMs initially found it necessary to build families based on separate models with different input configurations. More recently, market pressures have led to a common platform approach.

Historically, the clocking approach provides a separate voltage-controlled crystal oscillator (VCXO) for each clock. The required VCXOs are fairly expensive and tend to be among the least reliable parts in the system. Since all but one of these devices sit idle at any one time, it is a natural place to look when trying to optimize the system design.

This definitely presents a challenge to bringing data in from multiple standards and translating that data to a single format at some point. Consider Fibre Channel, where the lowest common sub-multiple of any of the other frequency options is a very small number. So, existing Integer-N phaselocked loop (PLL) approaches that are readily available cannot translate with precise accuracy.

It recently has become possible to simplify clocking design with chips that accept two reference input signals and generate output signals that aren’t harmonically related to those inputs. This facilitates translation between any two standard network rates.

What does that mean in practical terms?
It makes it reasonably straightforward to achieve the basic functions of switchover when a reference signal changes and of holdover when a reference signal drops.

Switchover is the key to handling multiple services. As the references change, the clock device must switch over seamlessly. It is essential to design the switchover function so no runt pulses or extra-long pulses result from this change and no downstream PLLs will lose lock, even when no predefined relationship exists between the phases of the various reference input signals. It is additionally desirable to have a smooth phase transition during switchover. When a clocking system supports “smooth phase transition,” there is a gradual transitioning of the phase of the output signal as the device adjusts to the phase of the newly active reference. The system designer should be able to choose how fast this transition occurs to prevent a phase change greater than the system can handle while allowing for sufficiently fast settling to the new phase.

Not every system designer subscribes to that philosophy, of course. Some prefer a “no phase transition” policy, where the output phase won’t change even when switching between two references that aren’t phase-aligned. In that case, the output signal should show no sign that anything unusual has occurred to the reference input. The clock device should provide an alarm (sometimes a pin, sometimes a bit in a register map) to indicate to the system that a switchover has occurred if such information is important.

Holdover enables designers to build systems with greater uptime. Furthermore, it lets systems use reference signals that are intermittent or unreliable without fear of that unreliability crashing the system.

These new chips implement holdover by having the input PLL in the digitally controlled crystal oscillator (DCXO) employ an external crystal as its frequency source. That way, it continues to operate in the absence of the input reference signal. Absent that signal, the DCXO holds at the frequency it was operating at just prior to switchover until a reference signal again becomes available.

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The output frequency or frequencies of devices with high stability-holdover would only drift in response to environmental stimuli (primarily temperature and/or supply voltage variations) to the extent that the local reference drifted. For systems that must adhere to the holdover requirements predefined by some standard, it would be a simple matter of providing a local reference source whose stability meets the holdover stability defined in the appropriate standard.

So if the design required SONETlevel stability in holdover, the use of an oscillator that supports SONETlevel stability would provide what was required. If the clock signal were to drift in holdover, the result will eventually manifest as a FIFO error of some kind (overflow or empty) that would result in blank or skipped frames. Holdover can be initiated as directed by controller/processor elements in a system. Or, in many cases, devices with holdover also provide a monitoring function that will automatically switch into holdover mode when the reference input goes quiet. The output frequency or frequencies of devices featuring high stability holdover will only drift in response to environmental stimuli (temperature and/or supply voltage variations primarily) to the extent that this local reference drifts.

For systems that must adhere to the holdover requirements pre-defined by some standard, it is a simple matter of providing a local reference source whose stability meets the holdover stability defined in the appropriate standard. If you need SONET-level stability in holdover, use an oscillator that supports SONET-level stability. If clock signal drifts in holdover, the result will eventually be a FIFO error of some kind (overflow or empty) that results in blank or skipped frames.

Product Q&A

Analog Devices’ Clock Generators Simplify System Design And Reduce Clocking Component CountAnalog Devices’ AD9549 dual-input network clock generator provides networking and data communications systems designers with a new standard of performance to maximize network uptime and increase system stability and reliability. Using a new architecture based on ADI’s proprietary DDS (direct digital synthesis) technology, the AD9549 enables a more stable holdover, allowing designers additional time to restore the clock reference in the event of a failure. If an input reference clock fails, the clock generator IC continues to “hold” the output frequency until the reference failure is recovered. With the AD9549, there is no time limit to holdover—the output will be maintained until the system is powered down or a new reference is provided. Compared to competitive solutions, this holdover functionality improves stability by as much as two orders of magnitude (~0.37 ppm vs. ~30 ppm), resulting in significantly increased system uptime. The AD9549 dual-input network clock generator reduces jitter to 600 fs (femtoseconds), 25% better than competing devices. The AD9549 has a programmable digital loop filter capable of bandwidths down to 1 Hz and below.

The AD9520 and AD9522 multi-output clock generators include a 512-byte embedded EEPROM memory block, affording system engineers a programmable clock solution that can serve as both the source and system clock. By programming their own specific set of output conditions using the on-chip memory, designers can easily configure the AD9520/2 as the source clock to ensure initial processing functions are synchronized when the system is powered on or reset. Competing clock ICs require a separate source clock, which must be independently matched to the system processor or microcontroller in order to program the system clock chip, adding component count, cost, and complexity to clocking designs. In addition to the on-chip EEPROM and PLL, the AD9520/2 integrates dividers, fanout buffers, and a VCO that tunes from 1.4 GHz to 2.95 GHz. The PLL/VCO clock-generation circuitry boasts industry-leading phase noise, while the clock distribution fanout channels feature ultra-low wideband jitter performance of 225 fs. The AD9520 offers 12 differential LVPECL outputs. The AD9522 includes 12 differential LVDS outputs. The outputs are partitioned in four groups, each with a 1 to 32 divider and phase delay. Both devices alternatively offer up to 24 single-ended CMOS output configurations up to 250 MHz.