Can We Thank Aristotle for Heterogeneous Integration?

A couple of years ago we may not have predicted that in 2018 there would be a growing demand for high-end chips specifically for global cryptocurrency mining. Those taking part in this search for hashes have a glimmer in their eye similar to those consumed by the hope and frenzy of a gold rush. The rush of getting to the answer first, and of course the alluring reward paid in Bitcoin, is driving participants to demand more computational power. Why stay with a mere rate of megahashes per second (MH/s) when you could go for terahashes per second (TH/s)? This demand is trickling through the entire semiconductor supply chain and certainly has found its way to the back-end segment.

These demands extend further as the drive for more data, more speed, more connectivity and more portability is increasing more than ever, as we settle into our increasingly connected life with our phones in hand. Transistor scaling faces unique challenges with increasingly complicated solutions like the evolution of multi-patterning techniques (octa-patterning anyone?) and the introduction of EUV lithography into high volume. These are really hard problems to solve, and they are certainly causing delays in the manufacturing cycle. So then what? It makes sense to move some focus to other areas that can advance without an exponential increase in cost. This is driving change in the back-end, with the advancement of wafer-level packaging and 3D integration. It makes sense that the industry would continue to look at smarter ways of combining packages to meet the increasing need for more complex functionality and lower power consumption.

To understand how to combine this functionality, we can look at how devices are evolving into full systems with different building blocks, which may include but are not limited to sensors, actuators, MEMS, RF communication, power electronics, GPUs, CPUs, and memory. These blocks typically have different electrical requirements, and often face limitations from single die integration using System on Chip (SoC) methods, because of cost and/or technology limits. Additionally, thin phone requirements are putting extra pressure on the need for dense integration.

Aristotle was the first to bring the concept of synergy to light. The thought that the whole is greater than the sum of the parts is very relevant here and could be considered the motivation behind heterogeneous integration in packaging. Isn’t it ideal to consider that putting all the pieces together into one package would then have enhanced operating characteristics and more functionality than each building block on its own?

There is a wide variety of approaches to building a system in package (SiP), which will depend on the application, type of building blocks included and the type of packaging technology to be used. Advanced packaging technology has been evolving with new wafer-level packaging (WLP) methods, like fan-in WLP (FI-WLP), fan-out WLP (FO-WLP), 2.5D/interposer and 3D-IC, which can be used as the base for the integration of different dies into a small standalone package.

Overall performance, form factor, power consumption and cost can all provide the motivation for moving towards heterogeneous integration. What does this mean for KLA-Tencor? The method of combining multiple dies into complex systems increases the risk that a single bad die will destroy the package as a whole. If the desired outcome is to maintain tight quality control requirements without sacrificing time to results, process control at the source is key. For the back-end, KLA-Tencor focuses on both wafer-level and component-level inspection and metrology. For critical wafer-level process steps such as the formation of the through silicon vias (TSVs) and the redistribution layer (RDL), it is essential to monitor for killer defects, such as cracks and shorts, early in the process flow. Finding yield-limiting defects at the source allows for efficient feedback loops to fix the process issue quickly. In the case that a killer defect is found, that die could be excluded from the packaging steps down the line. To maintain yield after dicing, inspection of the bare dies and packages is required before integration in the SiP. Depending on the package type, different defect types need to be captured in high-volume production. For bare dies this can be chipping defects, sidewall cracks, and internal die cracks, while for FI-WLP, sidewall crack detection is most critical, as they can lead to yield loss after final assembly. Finally, the finished SiP also needs quality control, especially because specific requirements apply for these packages, e.g. very low tolerance for package height and required detection of tiny exposed copper defects on EMI shielded SiPs.

As innovation enables increasingly specific and complicated packages, KLA-Tencor needs to provide sensitivity for defect types like tiny internal die cracks, but also maintain significant flexibility as the expanding number of applications continues to drive packaging in many directions. This means that we need multiple substrate handling solutions, and inspection capabilities for multiple form factors. Our goal is to keep synergy with our customers to stay aligned with their current and future process control needs as the technology continues to evolve.