We perform both of the operations under an acquired exclusive lock using mtx_. When
the lock is acquired, we can check the current queue state: whether it is empty (and
we cannot pop any new element) or full (and we cannot push a new element).
std::condition_variable::wait() moves the current
thread to the sleep state until
the specified predicate is true. Next, we push or pop an element and notify
the other thread (with the notify_one() call) that we have changed the queue state.
Because we add or delete only one element at a time, only one thread
waiting
for available elements or free slots in the queue can make progress, so we
notify and wake up only one thread.

The problem with the implementation is that only one thread at single point
in
time can modify the queue. Moreover, mutexes and condition variables
are expensive—in Linux, they are implemented by the futex(2) system call.
So each time a thread needs to wait on a mutex or condition variable,
that leads to a call to futex(2), which re-schedules the thread and moves it
to the wait
queue.

Now, let's run a basic test that just pushes and pops addresses to and from the
queue in 16 producers and 16 consumers (there is a link at the end of
article to
the full source code). On a box with 16 Xeon cores, the test took about
seven
minutes:

# time ./a.out
real 6m59.219s
user 6m21.515s
sys 72m34.177s

And, strace with the -c and
-f options shows that the program spends 99.98% of
the time
in the futex system call.

Alexander Krizhanovsky is the software architect and founder of NatSys-Lab. Before NatSys-Lab, he worked as a Senior Software Developer at IBM, Yandex and Parallels. He specializes in high-performance solutions for UNIX environments.

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Aside: I believe I am the registered user rhkramer (at least, I used to be) but this posting thingie wouldn't let me use that name--I think if someone at LJ looks it up, they'll see that my email and the email of registered user rhkramer are the same.

Do you really mean temporal variable or do you just mean a temporary variable.

I had never heard of a temporal variable before I read this article, then I did some googling to find it.

In looking at a page of 10 google hits, I then investigated 3 or 4 of those. At least one of them definitely simply meant temporary variable, and, at the time I looked at the article, it used the phrase temporary variable. I'm guessing that at the time google indexed the article it might have said temporal variable--but there were no remaining instances of temporal in the article. OTOH, maybe google decided that I meant temporary and used temporary instead of temporal in the query.

One hit on the page of hits did give me some hints as to what might be meant by a temporal variable:

'
On the semantics of (Bi)temporal variable databases - Springer
link.springer.com/chapter/10.1007%2F3-540-57818-8_53
Numerous proposals for extending the relational data model to incorporate the
temporal dimension of data have appeared during the past several years.
'

I guess my point is (especially as an old guy trying to keep up with some of this stuff), is that it sure would help if terminology didn't change unnecessarily. If the variable in this article truly is something more or different than a temporary variable, fine (but then please provide a definition or a pointer to a definition), but, if it is no different, then just please use "temporary variable".

I do consider all of the concepts you have presented for your post.
They are really convincing and can definitely work. Nonetheless, the posts are very short for beginners.
Could you please lengthen them a bit from subsequent time?

This is untrue (and is explicitly contradicted by the Intel manuals, which state categorically that “mfence does not serialize the instruction stream”; i.e. the instructions can still execute out of order).

The mfence will cause memory accesses before the fence to complete before memory accesses after the fence (more accurately, it causes memory accesses before the fence to become globally visible — i.e. their effects are apparent to other cores in the system — before those after the fence).

This was just a simplification for gentle introduction to memory ordering and when and why barriers are used. Unfortunately, the article has limited size, so there is no opportunity to carefully and fully describe this and some other interesting points.

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If effects of the instruction A and B are to be visible outside the processor core they must somehow access the memory (or to be precise maybe the cache). The article explains inter core or inter processors relations, so IMHO the explanation in the article is a little simplification but it is not inaccurate.