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Re: Procedure to loop back PL clock

pl_clk0 is not being "looped back" to the PSU in this design; it's simply being fanned out to become the source clock for several things.

I'm not entirely sure why the clock is connected to maxihpm0_lpd_aclk port of the PSU. That port is used to provide the clock to the PSU that would be used to clock data into and out of the M_AXI_HPM0_LPD interface--but that interface is (apparently) unused in the design. It's possible that that connection is shown to remind you that if you do use the interface, you must connect the raw clock output from the PSU to the maxihpm0_lpd_aclk port of the PSU, instead of connecting the gated version that's used for the demonstrated circuitry. That clock connection really has no bearing on the rest of the demonstrated circuitry.

I 'skimmed' the video. This is not an entry-level tutorial. A lot of significant and involved steps were mentioned ony in passing. I hope this isn't your first FPGA tutorial.

-Joe G.

P.S. Input-clock ports on the PSU are enabled automatically when you enable the associated AXI interface. The interfaces themselves are enabled through the PSU Re-customize IP Wizard:

Re: Procedure to loop back PL clock

If you're connecting the SEMI IP to the PS using an AXI port on the PS, when you enabled that port, the clock input associated with that port should have emerged on the left side of the PS block. Assuming you're using pl_clk2 as the AXI clock input for the SEMI IP, you would also connect pl_clk2 to the clock input on the PS block.

That clock would also be used to clock the AXI Interconnect between the PS block and the SEMI IP, as well as the Processor System Reset IP you'll need to finish-off the design.

Re: Procedure to loop back PL clock

pl_clk0 is not being "looped back" to the PSU in this design; it's simply being fanned out to become the source clock for several things.

I'm not entirely sure why the clock is connected to maxihpm0_lpd_aclk port of the PSU. That port is used to provide the clock to the PSU that would be used to clock data into and out of the M_AXI_HPM0_LPD interface--but that interface is (apparently) unused in the design. It's possible that that connection is shown to remind you that if you do use the interface, you must connect the raw clock output from the PSU to the maxihpm0_lpd_aclk port of the PSU, instead of connecting the gated version that's used for the demonstrated circuitry. That clock connection really has no bearing on the rest of the demonstrated circuitry.

I 'skimmed' the video. This is not an entry-level tutorial. A lot of significant and involved steps were mentioned ony in passing. I hope this isn't your first FPGA tutorial.

-Joe G.

P.S. Input-clock ports on the PSU are enabled automatically when you enable the associated AXI interface. The interfaces themselves are enabled through the PSU Re-customize IP Wizard: