Title (fr)

Publication

Application

Priority

DE 19956069 A 19991122

Abstract (en)

The integrated memory has memory cells (MC) arranged at the intersection points of word lines (WL1,..) and bit lines (BL1,..), reference cells (CREF) at the intersection points of at least one reference word line (WLREF) ,/WLREF) and the bit lines for generating a reference potential on the bit lines before access to one of the memory cells, redundant memory cells (RC) at the intersection points of a redundant word line (RWL1,..) and the bit lines and a programmable activation unit (AKT) that determines whether to connect in redundant word lines and memory cells.