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Abstract

Disclosed is a method to reduce the number of memory components required to implement byte parity across multiple bytes of data.

Country

United States

Language

English (United States)

This text was extracted from an ASCII text file.

This is the abbreviated version, containing approximately
63% of the total text.

Memory Device for Efficient Implementation of Byte Parity

Disclosed is
a method to reduce the number of memory
components required to implement byte parity across multiple bytes of
data.

When
implementing byte parity across a multi-byte memory array
with independent byte accessibility, an individual memory component
is required to store the parity bit associated with each byte of
data. For example, suppose byte parity
is implemented on a memory
array with a 32-bit bus interface (four bytes), as shown in Fig. 1.
If independent byte operations are to be supported (i.e., you can
modify one or more bytes), then present memory devices require one
additional memory component for each byte.
This method prevents the
other parity bits from being modified during a byte operation.

Although x9
memory components have been devised to eliminate
the need for an extra memory component when implementing byte parity,
they generally lag behind their x8 counterparts by at least a
generation of memory technology.
Furthermore, in most cases, the x9
memory components are never available.

This
invention reduces the number of memory components required
to implement byte parity across a multi-byte memory array by
providing a memory device with independent chip selects for each bit.
Hence, if the invention is used in the example illustrated in Fig. 1,
only one memory device is needed to implement byte parity rather than
four. This device reduction i...