Via Technologies’ Dual-Core Microprocessors Only Due in 2010

Via Technologies, a struggling developer of x86 central processing units and supporting core-logic sets, on Thursday demonstrated its roadmap at a conference in Tokyo, Japan. According to plans of the company, dual-core Via Nano processors will only emerge commercially in 2010, later than expected.

Dual-core Via Nano microprocessors will be, as expected, produced using “new”, presumably 45nm, process technology and will be compatible with Via C7 and Via Nano mainboards and infrastructure. There are no exact specifications available, but Via claims that the first samples are to emerge in December, 2009, whereas the commercial products are scheduled to become available in June, 2010, according to slides published by PC Watch web-site.

Earlier it was rumoured that Via Technologies intends to release its first dual-core chips sometimes by the end of 2009. Even though the chip was not even supposed to come out in time to compete against low-power dual-core chips from companies like Advanced Micro Devices or Intel Corp., the further delay seems be a disaster for Via.

In fact, the delay of dual-core processor introduction does not seem too surprising: Via Nano processors are still not available, at least widely, despite of the fact that the chips were formally announced back in May, 2008.

Via Nano is the first x86 processor from Via Technologies that features 64-bit instruction set along with a superscalar and out of order execution engine, macro-fusion and micro-fusion functionality, advanced branch prediction mechanism, advanced floating point unit as well as support for virtualization technology and Via PadLock security engine.

The new chips that belong to the Isaiah family also feature Adaptive PowerSaver Technology that further reduces power consumption and improve thermal management, including the unique TwinTurbo dual-PLL implementation, which permits smooth transitions between activity states within one clock cycle, ensuring always-on service and minimize latency, as well as new mechanisms for managing the die temperature.