All the news you're looking for from Tensilica, Inc. Find out how you can use Tensilica's customizable, extensible processors to speed your SOC design. See Tensilica for DSPs and all the processing you need to do in the dataplane (dataplane processors - DPUs).

Follow us on:

Friday, September 30, 2011

TLMCentral aggregates information about free and commercial system-level models of common system-on-chip (SoC) components from leading semiconductor IP vendors, tool providers, service companies and universities. TLMCentral is an open portal that will ease and accelerate the development of virtual prototypes across the industry. It is available at no cost to users and providers of transaction-level models.

Transaction-level models raise designer productivity by increasing the level of abstraction at which they design. TLMs are predominantly used in virtual prototypes which allow engineers to accelerate their software design schedules by up to nine months and significantly improve the productivity of their software development, hardware/software integration, and system validation tasks. Transaction-level modeling has also contributed to significant productivity gains in architecture design and SoC verification, and the models aggregated on TLMCentral can be applied to those use cases as well. See Synopsys news.