ARM announces new Cortex-A35: ultra-low power, 64-bit

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Over the past 18 months, we’ve seen consumer tablets and smartphones mostly jump from 32-bit ARM cores (the Cortex-A9 and A15) to their 64-bit counterparts (Cortex-A53 and A57). At the lower-end of the market, however, 32-bit continued to rule the roost. While ARM billed the Cortex-A53 as a replacement for the Cortex-A7 initially, tests showed that the A53’s power curve was high enough that it wasn’t a drop-in replacement for the 32-bit chip. Now, ARM has announced a new 64-bit processor that does replace the Cortex-A7, while simultaneously improving performance and flexibility.

The new Cortex-A35 is designed as a successor to the Cortex-A5 and A7, but presumably tilts towards the A7’s power efficiency and performance ratio rather than the minimalist Cortex-A5. A5 customers likely don’t have much need for 64-bit in the near future in any case — if you work in environments where the A5’s performance is good enough, it’s probably good enough for the foreseeable future. The exact positioning and replacement cycle is shown below:

Anandtech reports that the A35 is targeting environments where power is below 125mW (ARM claims the A35 can operate at 1GHz while drawing just 90mW — and that’s on a 28nm process. Since ARM intends for the chip to deploy at the 14/16nm node, real power and voltage levels should be even better. This allows for a greater frequency range or even lower power consumption for Internet of Things devices that don’t require much in the way of performance.

Like the A5 and A7, the Cortex-A35 is an in-order core with an eight-stage pipeline and limited dual-issue capabilities. What’s changed compared to those cores is that ARM has improved memory accesses, branch prediction, and instruction fetch to boost both power efficiency and overall performance. ARM borrowed heavily from the A53’s memory architecture to improve the A35’s final design, and boost the cache subsystem’s overall capabilities as well.

Flexible implementation

ARM has always offered flexible core implementations, but the Cortex-A35 takes that approach to new levels. The Cortex-A35 can be configured with 8K-64K L1 caches and an L2 cache between 128KB and 1MB. Customers who wish to do so can implement a Cortex-A35 core with an 8K L1, no FPU, Neon, L2 cache, hardware cryptography, or multi-core capability. Our recent story on an impending lawsuit against AMD over the core counts on Bulldozer processors argued that attempting to legally define a CPU “core” is effectively impossible, and ARM’s implementation offerings on the Cortex-A35 are part of the reason why. Two different vendors can build two different Cortex-A35’s with entirely different hardware capabilities, including functions we think of as essential to a modern processor, like the FPU.

In typical configurations, ARM is telling users to expect a 6% improvement in integer performance, 16% in browsing performance, 36% in floating point, and 40% in a Geekbench-style MPI test. That’s compared to the Cortex-A7 and assumes equivalent process technology and clock speed tests. Overall, the goal is clearly to provide a chip that better suits an evolving IoT ecosystem (assuming IoT developers ever manage to create a smart product worth owning that isn’t riddled with security flaws).

By offering low-power devices that include advanced security capabilities like TrustZone, ARM is giving developers some hardware options to help with that goal. Whether or not designers will use them is another question. Devices based on the Cortex-A35 are expected to be in-market by the end of the year, and ARM has suggested that some companies might choose to use a pair of Cortex-A53 / A35 cores in Big.little configurations to take advantage of the efficiency of its lower-power cores. ARM has previously stated that it expects companies to continue to pair Cortex-A72 cores with Cortex-A53 cores, but it’s possible that we’ll see a few OEMs offer A72 / A35 pairings to maximize both power savings and performance.

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