Alrighty, I'm posting this topic to try and tap the power of the community. Under the mips arch, we're using a patch in gcc-3.4.x that adds optimization support for the R10000 processor family. The original variant of the patch was for gcc-3.0, found here: http://gcc.gnu.org/ml/gcc-patches/2001-07/msg01161.html

What we're looking for is a port of this patch to the gcc-4.x DFA format so that when we finally adopt gcc-4 in portage as mainstream, the mips arch will have available the -march=r10000 and -mtune=r10000 options. I've poked around with it myself, but lacking the deep-level compiler knowledge that the usual gcc hacker has, I haven't been able to discern heads from tails in how things got moved around in the bump from gcc-3.4.x to gcc-4.x, so I haven't had alot of luck porting this. Plus, if this gets ported in time, it can hopefully be submitted back upstream and have a chance of making it into the mainline gcc tree for inclusion in future gcc releases.

Those curious about the performance gains this offers, based on my reading, this patch allows the compiler to schedule the instructions a little differently to take advatange of some of the better parallelization the R10000 offers (such as utilizing the second ALU unit it has). As reported by the original author of the gcc-3.0 patch, he saw performance gains upwards of %15. This doesn't mean the average user of the Octane, IP28, or even IP27 systems will see a blazing increase in speed, but they may notice some things running more efficiently, given various factors ongoing at the time.

If anyone succeeds in making a patch to gcc-4.x, I'll try and give it a test run in a chroot on my Octane (assuming I can get gcc-4 to even bootstrap...), and if it looks to work, tack it onto our gcc-4 beta ebuilds.

Well certainly it would be nice to see -ftree-vectorize work with MIPS SIMD. Right now only SSE/SSE2 and Altivec are supported. (This probably would require a whole lot of code to integrate into MIPS)_________________Inspiron 4100 & Sun UltraAXe
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