The power loss of the controllable switches in modular multilevel converter (MMC) HVDC transmission systems is an important factor, which can determine the design of the operating junction temperatures. Due to the dc current component, the approximate calculation tool provided by the manufacturer of the switches cannot be used for the losses of the switches in the MMC. Based on the enabled probabilities of each SM in an arm, the current analytical models of the switches can be determined. The average and RMS currents can be obtained from the corresponding current analytical model. Then, the conduction losses can be calculated, and the switching losses of the switches can be estimated according to the upper limit of the switching frequency. Finally, the thermal resistance model of the switches can be utilized, and the junction temperatures can be estimated. A comparison between the calculation and PSCAD simulation results shows that the proposed method is effective for estimating the junction temperatures of the switches in the MMC.

In a modular multilevel converter (MMC) HVDC transmission system, it must be guaranteed that the operating junction temperatures Tj of controllable switches do not exceed the temperature limit in the whole operating range [1]. Therefore, the estimation of Tj is a key part of the MMC design procedure. At present, some switch manufacturers use approximate calculation tools for this purpose [2], [3]. The current of the switches in the MMC include dc and ac current components. Since these simulation tools can only calculate the losses and junction temperatures of the switches under sinusoidal currents, these tools can be used for 2-level voltage source converters (VSCs). However, they cannot be used for the MMCs.

Usually, the estimation of the junction temperature in the MMC design is based on datasheet values, conduction losses, switching losses, and the thermal characteristics of the switches. In addition, the analysis of the conduction losses and switching losses of the switches is the first task. Annex B of IEC/TR 62543 [4] gives a general method to evaluate the losses of the converters in VSC systems. However, the International Standard does not provide the details to evaluate the losses of MMCs. Thus, finding a well understood and accepted method to evaluate these losses is very important.

For the losses in a 2-level VSC, the authors of [5]-[7] have studied the switching losses of the converter by fitting the corresponding parameters of the switching and conduction losses. The fitting parameters methods are validated by experiments. As for MMCs, the authors of [8] have provided a mathematical analysis for the average current and RMS current of the switches in a converter based on sinusoidal pulse width modulation (SPWM). However, this may result in excessive switching losses.

Masserant and Stuart [9] utilized the average current and root mean square (RMS) current to calculate the IGBT conduction and switching losses in a boost type power factor controller (PFC). The arm current of the MMC may flow through the upper IGBT or the lower free-wheeling diode (FWD), and then through the lower IGBT or the upper FWD. Therefore, the RMS currents of the IGBT and FWD cannot be determined directly. The authors of [10], [11] proposed mathematical analysis to calculate the conduction and switching losses of the switches in a MMC. The two methods have good precision for loss estimation. However, they are computationally demanding and time consuming.

This paper has proposed using the enabled probabilities of each SM in the upper arm or lower arm considering the path of the arm current. The expression of the average current and RMS current of the upper/lower switches can be determined. Then, it is possible to obtain the conduction losses of the IGBT or FWD, and the switching losses of the IGBT or FWD from the point of the analytical method. This paper provides an estimation method for the junction temperature of the switch in the MMC.

II. MMC IN VSC-HVDC SYSTEMS

- A. Basic Structure

A diagram of a three-phase MMC is shown as Fig. 1. The MMC mainly consists of three phase units. Each phase unit consists of one upper arm and one lower arm connected in series between two dc terminals. Each arm is made up of 2n series-connected half-bridge SMs and one arm inductor. The inductor Ls can be used to control the transmission power, to restrain the circulating current between different phases, and to limit fault currents under dc side faults.

The structure of the SM is shown on top right of Fig. 1. The SM is mainly made up of two IGBT-diode pairs with the IGBT and FWD connected in inverse parallel, one dc capacitor Cs, and one DC grading resistor Rp. The output voltage USM of the SM has two values (USM = Uc or 0), which depend on the switch-statuses of T1 and T2 . The output voltage is Uc when the upper IGBT is switched on and the lower one is switched off. The output voltage is 0 when the upper IGBT is switched off and the lower one is switched on. The voltages of the SM with the output voltage Uc and 0 are enabled and bypassed, respectively. The reference directions of the voltage and current in the MMC are shown in Fig. 1.

- B. Operating Mechanisms

The ac voltage of each phase can be obtained by controling the number of enabled and bypassed SMs in each arm. Under normal operation, the phase to ground voltage va and ac side current ia (take phase a for example) can be defined as:

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where Em is the peak value of va, ωN is the fundamental angular frequency, Im denotes peak value of ia, and φ denotes phase delay.

Since three identical phase units are in parallel connection, the dc current Idc of the dc transmission lines (cables/overhead lines) should equally distribute among the three phase units. In addition, the upper arm and lower arm in the phase unit are connected in parallel for ia, which can equally divide between the upper arm and lower arm while neglecting the circulating current between the different phases. Thus, the currents in the upper and lower arms can be expressed as:

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From (2) and (3), the current in the upper and lower arms can be rewritten as:

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where current ratio k is:

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where iau and ial are the currents of the upper and lower arms, respectively.

III. CAPACITOR VOLTAGE BALANCING OF SMS

The capacitor voltage of each SM is a fluctuation voltage due to the charge or discharge current. In order to achieve voltage balance, the capacitor voltage must be monitored and kept within a small range of voltage deviations among the SMs. In addition, the capacitor voltages are sorted in ascending order. Under the inverter operation of the MMC, the current paths and states of the SMs are shown in Fig. 2. In Fig. 2, the left current path is the positive current, and right current path is the negative current flowing through the enabled and bypassed SMs under the inverter operation. The voltage balancing algorithm has a significant impact on the circulating current, which obviously leads to the average and RMS currents of the switches. Here, the circulating current between the different phases is neglected [12].

From Fig. 2, it can be seen that, when the arm current iarm is a positive current, the arm current flows through the capacitor of the enabled SM, and the capacitor is charged. On the other hand, when the arm current iarm is a negative current, the arm current flows through the capacitor of the enabled SM, and the capacitor discharges. It can also be seen that, when the SM is bypassed, the arm current flows through T2 or D2 rather than the capacitor, and that the voltage of the bypassed SM can be kept constant. In order to keep the voltage balance between the different arms and phase units, the selection of the SMs depends on the state of the SMs and the path of the arm current. To obtain a desired arm voltage, the selection of the SMs can refer the following principles:

- When the arm current is positive or zero, if the arm needs to increase one SM, the chosen SM should be the bypassed SM with the lowest capacitor voltage, and the frequency of the switch action is the necessary switching frequency. When the capacitor voltage of the enabled SM is more than the allowable value, the enabled SM needs to be bypassed, and the bypassed SM with the lowest capacitor voltage should be enabled to maintain the number of enabled SMs. In addition, the frequency of the switch action is an additional switching frequency;

- When the arm current is a negative current, if the arm needs to increase one SM, the chosen SM should be the bypassed SMs with the highest capacitor voltage, and the frequency of the switch action is the necessary switching frequency. When the capacitor voltage of the enabled SM is less than the allowable value, the enabled SM needs to be bypassed, and the bypassed SM with the highest capacitor voltage should be enabled to maintain the number of enabled SMs. In addition, the frequency of the switch action is an additional switching frequency.

In accordance with the above principles, the voltage balance between different arms and phase units and the safe operation of the SMs can be obtained effectively.

IV. SM ENABLED PROBABILITY

Since the terminal voltage Udc from the positive terminal to the negative terminal of the MMC is constant, when one SM is bypassed in the upper arm, one SM should be enabled in the lower arm, and vice versa. With the nearest level control (NLC) modulation technology [13], the voltage of the upper and lower arms are shown in Fig. 3 (take phase a and n=4 for example).

Staircase output voltage on ac side of the MMC with the example of n=4.

According to Fig. 3, the voltages of the upper arm and lower arm satisfy:

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If the number of SMs is large enough, the output voltage of the MMC can be taken as a roughly sinusoidal voltage. Equation (6) can be rewritten as:

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where the modulation index m is:

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The voltages uau and ual are the total voltages of the enabled SMs in the upper and lower arms, respectively. With the assumption that the SM capacitor voltage Uc (t)=Udc/2n, the number of enabled SMs in the upper and lower arms can be expressed as:

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where nau(t) and nal(t) are the numbers of the enabled SMs in the upper and lower arms, respectively.

According to (9), the enabled probabilities of each SM in the upper and lower arms are:

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For each SM, the current path has only two paths. The current may flow through the upper switch T1 or D1, which means that the SM belongs to the enabled SM. It may also flow through the lower switch T2 or D2, which means that the SM belongs to the bypassed SM.

By neglecting the power losses in the MMC and using energy conservation between the ac and dc sides of the MMC, the following is obtained:

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Using (5) and (8), k can be rewritten as:

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Equation (12) shows that k is infinite when the MMC only exchanges reactive power.

V. AVERAGE VALUE AND RMS VALUE OF THE SWITCHES CURRENT

In (8), the modulation index m is a lot greater than zero and less than 1. From (12), k should be greater than 2. Thus, the arm voltage is unipolar, and the arm current is bipolar, which shows that iau has two zero points in one fundamental period. The two points are:

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When the MMC operates the inverter mode, iau and the two zero points are shown in Fig. 4.

From Fig. 4, it can be seen that the forward current time is π + 2 arcsin(k-1) for D1 and T2, and that the reverse current time is π - 2 arcsin(k-1) for T1 and D2 under the inverter operation in a fundamental period. Due to the dc current component in the arm, the conduction times of the switches of the SMs are different, which is neglected in [8].

According to the enabled probability and conduction time, the average and RMS currents can be determined. Here, the schematic diagram of the switch conduction is taken as an example under the inverter operation of the MMC. The arm current iau and switching characteristics of T1, D1, T2, and D2 are shown in Fig. 5, during a fundamental period T.

In Fig. 5, from the instant t1 to t2, iau is a positive current, which flows through D1 during Δt1, Δt3 and Δt5, or through T2 during Δt2 and Δt4. For D1 and T2, the total conduction times of the corresponding conduction sequences are the sum of Δt1, Δt3 and Δt5, and the sum of Δt2 and Δt4, respectively. The conduction time can be expressed as:

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where tD1 and tT2 are respectively the total conduction times of D1 and T2.

From the instant t2 to t1+T, iarm is a negative current, which flows through T1 during Δt7 and Δt9, or through D2 during Δt6, Δt8 and Δt10. With the same method, the total conduction times of T1 and D2 are:

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The procedures for the corresponding total conduction time of the switches in lower arm are the same as the above procedures and can be neglected here.

According to the conduction times of the switches and the characteristics under the non-conduction state (the current of the switch is 0), the average and RMS currents in the SM upper switches (T1 and D1) and lower switches (T2 and D2), referring to the solid arrow shown in Fig. 1, are computed as follows:

From (16) and (18), it can be seen that the sum of the average current of T1 and D1 is zero, which shows that the capacitor voltage of the SMs can maintain its balance.

When the MMC operates in the rectifier mode, the calculation of the average and RMS currents flowing through the switches is similar to the calculation under the inverter operation. According to the current reference direction under the inverter and rectifier operation, the following current relationships can be found: the average and RMS currents of T1, D1, T2 and D2 under the inverter operation are the same as the average and RMS currents of D1, T1, D2 and T2 under the rectifier operation of the MMC.

VI. MMC IN VSC-HVDC SYSTEMS

- A. IGBT and FWD Conduction Losses

The average conduction losses Pcon of an IGBT or a diode are approximated as:

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where Pcon_x represents the average conduction losses of device x; U0_x presents the bias voltage of device x; r0_x indicates the dynamical resistance of device x; and Ix_avg and Ix_rms are the average and RMS currents flowing through device x, respectively.

- B. IGBT and FWD Switching Losses

witching losses consist of essential switching losses and additional switching losses. The essential switching losses are generated due to the enabled probabilities of each SM. The additional switching losses are generated to maintain voltage balancing with additional switching actions. The additional switching frequency is hard to determine analytically. The upper limit of the total switching frequency fp (including the necessary switching frequency and the additional switching frequency) is 3 times the fundamental frequency fN[11], [14].

Brückner and Bernet [15] have found that the turn-on losses Eon and turn-off losses Eoff of the IGBT have an almost linear relation with the average current. The recovery losses Erec of the diodes are less than the switching losses of the IGBT. The IGBT switching losses Psw and the FWD recovery losses Prec can be approximated as:

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where Eon, Eoff, and Erec can obtained from the corresponding device manufacturer; Uref_x and Iref_x are the reference voltage and current of the IGBT or FWD when the turn-on and turn-off losses or recovery losses are measured, respectively.

The turn-on losses of the FWD are rather small, and may be not considered [15]. Using (24) and (25), the total losses of the IGBT and FWD are roughly the sum of the conduction losses and switching losses

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where Pcon_T is conduction loss of the IGBT, and Pcon_D is conduction loss of the FWD.

- C. Equivalent Thermal Circuit Model

In order to calculate the average junction temperature of one IGBT-diode pair with a heat-sink, the equivalent thermal model is shown in Fig. 6[16]. The thermal capacitances are not included here.

In Fig. 6, RthJC,X and RthCS,X are the thermal resistances of the junction-to-case and case-to-heat-sink for device X, respectively, and TS is the temperature of the heat-sink.

The thermal resistance of the junction-to-case (IGBT and FWD) can be taken from the datasheet. By neglecting the coupling between the IGBT and FWD, the values of RthCS_x are usually stated separately for the IGBT and FWD. They can be obtained from newer datasheets.

The junction temperatures of the IGBT and FWD can be obtained by:

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- D. IGBT and FWD Losses Calculation with a Heat Sink

In order to calculate the losses of the temperature-dependent switches, the conduction losses were determined in an iterative calculation procedure. The initial junction temperature T0j,x of device X is 125℃, which is the one case operating point provided by the device manufacturer. According to (26), the losses of device X can be obtained. It is assumed that the temperature of the heat sink is constant. Then, the junction temperature Tj,x can be determined from (27). The junction temperature rise ΔTx is Tj,x minus T0j,x. Thus, the dynamical resistance

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is changed as:

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The iterations are repeated until ΔTx within -0.1 ℃~0.1 ℃.

VII. LOSS ESTIMATION OF AN MMC

- A. Specifications of an MMC

To verify the derived analytical formulas for the estimation of the junction temperature in the MMC IGBTs, a bipolar MMC-HVDC system with 1000 MW/±320 kV is established with the simulation tool PSCAD/EMTDC as shown in Fig. 7. When compared with the symmetrical monopolar HVDC system proposed in [17], the operational reliability of the bipolar MMC-HVDC system can improved.

For the effectiveness of the simulation, each arm was made up of 200 SMs. Each converter station was connected to a 180 kV ac system. The main circuit parameters of the simulated system are listed in Table I. An ABB HiPak IGBT module 5SNA 1500E330305 was applied to the switches of the SMs in this paper. Its related turn-on losses, turn-off losses and recovery losses are listed in the data sheets in [18], [19]. Based on these specifications, the conduction and switching losses of the MMC can be estimated. This IGBT module has a 3300 V collector–emitter voltage VCES and a 1500 A dc collector current IC nom.

To calculate the losses of the IGBT model in the MMC, the semiconductor specifications from the manufacturer can be used to evaluate related losses. These losses consist of the conduction and switching losses. The specifications of the ABB IGBT module (5SNA 1500E330305) can be obtained from references [17], [18]. These specifications include the bias voltage, the dynamical resistance, the switching or recovery losses, and the thermal resistances shown as in Table II.

According to (28)-(30) and Table I, the conduction and switching losses of the IGBT and FWD in the upper arm of phase a are shown in Figs. 8 and 9, respectively, with the transmission power of the MMC under cos(φ)=1. From Figs. 7 and 8, it can be seen that the conduction losses of the switches are more than one order of magnitude of the corresponding switching losses with the MMC technology. It can also be seen that the total losses of T2 and D2 are larger than the total losses of T1 and D1 under the inverter and rectifier operation, respectively. Thus, the junction temperature of T2 or D2 should be taken care of first.

Switching losses of IGBT and FWD changing with the transmission power of MMC under cos(φ)=1.

Figs. 8 and 9 show that the losses distribution of the four switches is rather unequal. When the MMC transmits its rated power, the simulation current waveforms of the arm and the switches (T1, D1, T2, D2 ), under the inverter and rectifier operation, are shown in Figs. 10 and 11, respectively. Due to the dc component of the arm current, the conduction current and time of T2 reach their largest values under the inverter operation, and the conduction current and time of D2 reach their largest values under the rectifier operation. The bias voltage, dynamical resistance of T2, is larger than that of D2 in Table II. This is the main reason that the total loss of the SM under the inverter operation is larger than that of the SM under the rectifier operation.

Simulation current waveforms of the arm, and T1, D1, T2, D2 when P=1000MW (rectifier operation).

When the MMC under the rectifier or inverter operation transmits its rated power, the conduction losses and switching losses obtained from the analytical method are listed in Table III. It is assumed that the temperature of the heat-sink is about 65 ℃ . Using these losses and the resistances for the junction-to-case and case-to-heat-sink of the IGBT or FWD, the respective junction temperatures are also listed in Table III.

From Table III, it can be seen that the junction temperature of T1, D1, T2 and D2 at the maximum transmission capacity under the rectifier and inverter operation, are 76.9 ℃, 79 ℃, 66 ℃, 150.3 ℃, and 75 ℃, 81.9 ℃, 123.4 ℃, 66℃ respectively. In addition, the junction temperatures of the switches are below the maximum junction temperature 150 ℃ under the inverter operation. This shows that the temperature of the heat-sink can be properly increased. However, under the rectifier operation, the junction temperature of D2 is over 150 ℃. The heat-sink temperature of D2 should be kept below 64.7℃.

- D. Losses and Junction Temperature with the Simulation

To verify the analytical formulas for the evaluation losses of the SM, a simulation model of the MMC-HVDC is established in the PSCAD/EMTDC environment. Under the transmission rated power of the MMC, the conduction losses, switching losses and junction temperatures of T1, D1, T2 and D2 from the simulation results are listed in Table IV.

From Tables III and IV, it can be seen that the conduction losses of the switches, except T2 under the rectifier operation and D2 under the inverter operation, are relatively close. The main reasons for the deviation of the conduction losses are (1) neglecting the reactive power consumption of the arm inductor; (2) neglecting the harmonic components of the current in the arm. It is interesting that for different switches with the larger conduction losses, the deviation is smaller. The relative errors ε = (Pcalculation/Psimulation-1)×100% of T2 under the rectifier operation and D2 under the inverter operation are below 5%. Since 3fN is taken as the switching frequency, which is its upper limit, the switching losses obtained from the analytical method are correspondingly larger than ones obtained from simulation. In comparison, the evaluation losses and junction temperature by the analytical formulas are simpler and faster than by the PSCAD simulation, which requires a simulation model and consumes time.

From Tables III and IV, it can also be seen that the junction temperatures of D2 under the rectifier operation are over 150 ℃. This shows that the heat-sink temperature of the rectifier station should be lower than that of the inverter station.

VIII. CONCLUSION

Using the voltage of the upper and lower arms, the enabled probabilities of each of the SMs in the upper and lower arms have been proposed. According to the enabled probabilities, the average and RMS currents of the switches of the SMs can be obtained from the analytical method. Thus, the conduction and switching losses can be calculated or estimated. According to the thermal model of an IGBT-diode pair with a heat-sink, the junction temperatures of the switches can be determined. Based on a 1000 MW ±320 kV MMC–HVDC system, the simulated results show that the analytical method is effective enough to estimate the reliability of a cool system.

Acknowledgements

This work was supported by the National Natural Science Foundation of China (51261130471)

BIO

Haitian Wang was born in Hunan, P.R. China. He received his B.S. degree in Computation Mathematics and his M.S. degree in Electrical Engineering, from Sichuan University, Chengdu, P.R. China, in 1999 and 2003, respectively, and his Ph.D. degree in Electrical Engineering from Shanghai Jiao Tong University, Shanghai, P.R. China, in 2011. From 2011 to 2013, he had a postdoctoral position with the China Electric Power Research Institute (CEPRI), Beijing, P.R. China. He was sponsored by the China Postdoctoral Science Foundation. In 2013, he joined the State Grid Smart Grid Research Institute, Beijing, P.R. China. His current research interests include voltage source converter based high voltage DC (VSC-HVDC) transmission systems, and cross-linked polyethylene cables for VSC-HVDC transmission systems. He is the author or coauthor of more than 20 scientific papers and has 5 papers that have been published in IEEE transactions. He is a paper reviewer for the IEEE Transactions on Industry Applications and the IEEE Industry Applications Magazine.

Guangfu Tang received his B.S. degree in Electrical Engineering from Xi’an Jiao Tong University, Shanxi, P.R. China, in 1990, and his M.S. and Ph.D. degrees in Electrical Engineering from the Institute of Plasma Physics, the Chinese Academy of Sciences (ASIPP), Hefei, China, in 1993 and 1996 respectively. From 1996 to 1998, he had a postdoctoral position with the China Electric Power Research Institute (CEPRI), Beijing, China, and he was the Vice Director of the China Energy Conservation Center, Beijing, China. In 1998, he joined CEPRI, where he led the Thyristor Controlled Series Compensator Group, from 1998 to 1999, and the Static Var Compensator Group, from 2000 to 2001. Since 2002, he has been a Professor-level Senior Engineer of CEPRI. In 2012, he joined the State Grid Smart Grid Research Institute (SGRI), Beijing, China, as a Professor-level Senior Engineer. He is presently the Vice-President of SGRI. Over the past 16 years, his research interests have include flexible AC transmission systems (FACTS), converter valves of high voltage and ultra-high voltage in DC transmission systems, voltage source converter based high voltage DC (VSC-HVDC) transmission systems, and DC grids. Dr. Tang was a Member of the CIGRE SC B4 (HVDC and Power Electronics) committee. He is a Member of CIGRE SC B4 AG4 “HVDC System Performance.” In addition, he was the Convener of the CIGRE SC B4 Working Group B4-48 “Components Testing of VSC System for HVDC Applications. He is also a Member of the IEC SC22F, WG25 and MT22. He is a member of the IEEE PES Narain Hingorani FACTS and the Custom Power Award Committee.

Zhiyuan He received his B.S. degree in Electrical Engineering from Sichuan University, Chengdu, China, in 2000, and his M.S. and Ph.D. degrees in Electrical Engineering from the China Electric Power Research Institute (CEPRI), Beijing, China, in 2003 and 2006, respectively. In 2006, he joined CEPRI, where he led the voltage-source converter based high voltage DC (VSC-HVDC) transmission systems group. From 2008 to 2009, he was the Manager for CEPRI in the areas of HVDC Technology. Since January 2010, he has been the Manager and Chief Engineer for the CLP Power Engineering CO., LTD PURELL of CEPR. In 2012, he joined the State Grid Smart Grid Research Institute (SGRI), Beijing, China, as a Senior Engineer. In 2013, he became a Professor-level Senior Engineer of SGRI. He is presently the Head of the Department of DC Power Transmission Technology of SGRI. Over the past eight years, his research interests have included high power electronics technologies for the reliable operation of large interconnected power grids, re-locatable DC de-ice systems, and VSC-HVDC transmissions, including work on the first VSC-HVDC project in China, in 2011. He has published more than 50 papers, and has obtained 36 patents in his research field. In addition, he has received 2 Provincial Scientific and Technological Progress Awards. Dr. He was as a Member of CIGRE B4 Working Group 48, and a Researcher working on “Components Testing of VSC System for HVDC applications,” from 2006 to 2009. From 2009 to 2010, he was a member of IEC SC22F Working Group 19, where he carried out research on “High-Voltage Direct Current (HVDC) Power Transmission Using Voltage Sourced Converters (VSC).

Junzheng Cao received his B.S. and M.S. degrees from Xi’an Jiaotong University, Xi’an, China, in 1982 and 1985, respectively, and his Ph.D. degree from the London South Bank University, London, England, UK, in 1997. Prior to returning China in 2010, he served as a Principal Engineer and an HVDC expert at AREVA/ALSTOM T&D. He is presently a Professor-level Senior Engineer and Chief Engineer for the HVDC Department of the State Grid Smart Grid Research Institute (SGSGRI), Beijing, China, a sub-organization of the State Grid Corporation of China (SGCC), Beijing, China. He was made a China’s National Distinguished Expert of the "1000-Elite Program," in 2010, and a Guest Professor of Xi’an Jiaotong University, in 2012. He has authored or co-authored over 30 HVDC related technical papers, holds 17 patents and has written a book, China Electric Power Encyclopedia. Dr. Cao is members of IEEE, IET, Cigre and several working groups including the Cigre working group B4-62, IEC TC22/22F/MT10, IEC TC22/22F/WG26, and the National Technical Committee 60 on Power Electronics of the Standardization Administration of China (SAC/TC60/SC2). He is a paper reviewer for the IEEE Transactions on Smart Grid and the IEEE Transactions on Instrumentation and Measurement. His current research interests include the development and engineering of high voltage equipment for FACTS, HVDC and future DC grid applications.