I have an asynchronous non-periodic signal in Spartan 6 and I would like
to have a delayed copy of it (10 ns delay). And I would prefer not to
use iodelay2 element. What are the possible implementations in Verilog
for me?
Regards,
Mo

Mo Z. wrote:> an asynchronous non-periodic signal in Spartan 6 and I would like to> have a delayed copy of it (10 ns delay). And I would prefer not to use> iodelay2 element.
A signal inside the FPGA cannot use an input-output delay...
> What are the possible implementations in Verilog for me?
For the implementation and use of components see the Synthesizers User
Guide. For Xilinx synthesizer this is the "XST User Guide". In there you
can find how to describe components in VHDL/Verilog to get the FPGA
hardware invoked.

Here's the situation:
I need to implement the FIFO buffer of a 16-bit ADC system. Since the
external SRAM data line is 8-bit architecture, I was thinking that I
could divide the 16-bit output into 2 8-bit registers and store them
separately. Here's some part of the code for buffering:
always @(negedge ADC_EOC)
begin
SRAM_A <= {Q1_7, Q1_6, Q1_5, Q1_4, Q1_3, Q1_2, Q1_1, Q1_0};
// SRAM address line for 8-bit MSB
SRAM_WR = 1; //
de-asserting SRAM write command
LBD <= ADC_REGA; // pushing the
8-bit MSB into SRAM data line
delay #
SRAM_A <= {Q2_7, Q2_6, Q2_5, Q2_4, Q2_3, Q2_2, Q2_1, Q2_0};
// SRAM address line for 8-bit LSB
SRAM_WR = 1; //
de-asserting SRAM write command
LBD <= ADC_REGB; // pushing the
8-bit LSB into SRAM data line
end
at the negative edge of ADC_EOC, I have all the 16-bit ADC output ready
to process. I have already sampled the 16 bits in 2 separate registers
(ADC_REGA, ADC_REGB). I would like to place them separately on the SRAM
data line (LBD). I'm also using 2 separate counters (Qi_j keeps track of
the address separately) for SRAM address line (SRAM_A). I was thinking I
could use a delay # command and do the whole process separately.
Regards,
Mo