Lot of hush-hush about memory controller ownership in HMC. Intel of course wants to put all the ownership in its CPU, as would anyone who integrates an on-chip memory controller into the main processing unit. It's a big factor in chip design strategy. Designing with HMC-based controller is actually a big risk.

It would be interesting to know in quantitative terms what "in low volume production" means and even more intriguing what does "it has its place, it's its own thing." actually mean in the light of the following.

By late December 2013 both the 128Mb and the 1Gbit MCP had been quietly removed from the Micron product list on their web site. It was reported elsewhere* that Micron had indicated that their earlier generations of phase change memory were no longer available for new designs or for those wishing to evaluate the technology and the focus for PCM had moved to developing a new PCM process, in order to lower bit costs and power while at the same time improve performance. What then is the PCM device type that is in low volume production, why would low volume production be maintained for devices that are no longer available to potential customers and have the bit cost, power and performance limitations indicated? If PCM is not suitable for NAND or DRAM replacement, for what then is it suited?

Micron also have a paper a paper co-authored with Sony at ISSCC 2014 that reports a 16Gbit ReRAM based on a 27nm process, one wonders why that not get a mention along with STT/MRAM as one of the whittled down list of emerging memory types with future potential on which Micron are working?

Its interesting to look at the status of alternatives to DRAM among memory architectures. up to this point, they weren't getting much attention but now that they have been whittled down to just a few, those alterntives are gaining visibility and credibility as it is hard to deny what has been proven over the course of time.