Authors:
Xingjun Xue;Shujie Yang;Zheyao Wang;
Pages: 1751 - 1758Abstract: This paper presents a method for fabrication of flexible silicon sensor chips using temporary bonding, backside thinning, debonding, and flexible packaging. Flexibility of silicon chips requires ultrathin thickness, which imposes a challenge to debonding of thinned silicon chips from carrier wafers because of the fragility of silicon. To address this problem, temporary bonding using polypropylene carbonate (PPC), a heat-depolymerizable polymer material, as bonding adhesive is developed. PPC allows damage-free detachment of ultrathin silicon chips from carrier wafers by heating after backside thinning. The method is demonstrated and applied to the fabrication of silicon stress sensor chips with thickness down to $30~mu text{m}$ . The measurement results show that the ultrathin silicon chips have good flexibility and function well. The processes are optimized, and the detailed parameters are reported. The preliminary results demonstrate the feasibility of the method, and show its potential application in the fabrication of flexible ultrathin silicon sensors.PubDate:
Nov. 2017
Issue No:Vol. 7, No. 11 (2017)

Authors:
Yan Pan;Lu Song;Shuye Zhang;Xionghui Cai;Kyung-Wook Paik;
Pages: 1759 - 1764Abstract: Anisotropic conductive films (ACFs) composed of an adhesive polymer resin and fine conductive particles such as metal-coated polymer conductive particles are interconnect materials for fine-pitch flex-on-flex (FOF) assembly technologies due to their fine-pitch handling capability, low-temperature bonding, and stable electrical properties due to the compliance of polymer conductive particles. For the ultrafine pitch FOF assembly, the polymer conductive particle content becomes more important due to electrical storage problem between electrodes. To design better quality ACFs materials for 50-μm FOF assemblies, the effects of polymer conductive particle contents on the electrical stability and reliability of FOF ACFs joints were investigated. It was found that the bonding temperature should be less than the deformation temperature of polymer conductive particles, and proper conductive particles content should be applied to obtain the stable joint contact resistance and ACF joint morphology. When the conductive particle contents increased more than 4wt%, the gap width between the top and bottom electrodes increased and the deformation of conductive particles became less, resulting in higher contact resistance. Therefore, 4wt% of conductive particle ACFs bonded at 175 °C, 2 MPa for 10 s showed the lowest contact resistance of 36.2 mQ and excellent thermal cycle (T/C) reliability up to 1000 cycles. As a result, the optimum polymer conductive particles contents and the bonding conditions such as temperature, pressure, and times were achieved to obtain the best performance and T/C reliability of 50-μm pitch FOF assembly using ACFs.PubDate:
Nov. 2017
Issue No:Vol. 7, No. 11 (2017)

Authors:
David Rojas;John Barrett;
Pages: 1765 - 1773Abstract: Measurements of relative displacement between the components of structural steel frameworks such as those used in large buildings, bridges, ships, and offshore platforms can be used to detect overstress or impending failure. However, current approaches used to measure displacement require complex arrays of optical sensors or strain gauges. We instead present a novel low-cost wireless 3-D embedded module that uses inductive eddy-current sensing with planar printed circuit board (PCB) coils to measure relative displacement between two or more metal plates. The module is a 50-mm cube with four faces formed by the planar PCB inductors that are used for measurement of relative displacement. The other faces and the hollow center of the cube are used for a four-channel inductive sensing IC, a microcontroller with integrated 802.15.4-compatible radio, antenna, micro-USB serial connector, battery, and battery charger/monitor. The addition of temperature and humidity sensors and a microelectromechanical system inertial measurement unit makes the module into a full structural health monitoring system that can also sense environmental factors, inclination, vibration, and shock. The module was evaluated in two axes in a custom test system that allowed controlled relative movement to two orthogonal mild steel plates, as well as inclination of the plate in a different test setup. The results show that a resolution of 0.5 mm can be achieved in both axes when measuring displacement from the planar coils to the steel plates, with negligible interference between coils/plates on the adjacent faces. The displacement measurement is immune to the presence of water between the planar inductors and the steel plates, allowing the module to be used in applications exposed to high humidity and rain.PubDate:
Nov. 2017
Issue No:Vol. 7, No. 11 (2017)

Authors:
Muhammad S. Alshahed;Zili Yu;Harald Richter;Christine Harendt;Joachim N. Burghartz;
Pages: 1786 - 1794Abstract: In this paper, a rigorous methodology for extracting the thermal compact model parameters of packaged chips is presented. The methodology is based on using a custom-designed test chip with multiple heating and temperature sensing elements in order to predict the temperature distribution in packaged chips after packaging. The technique involves measurement of various chips with different thicknesses, different packages, and for different power dissipation scenarios through which the thermal model parameters can be extracted. The results show that ultrathin chips with a total thickness below 20 μm experience a dramatically increased temperature for localized heat dissipation. In addition to this, the measurements conducted in time domain and frequency domain show that at high enough frequencies of heat pulsing, the temperature variations become independent of the thermal boundary conditions of the chip. The measurement results are compared to the finite-element method simulation data. The simulations together with the measurement methodology serve as a technique to extract the thermal compact model parameters of packaged chips after being fabricated and packaged in an accurate and efficient way.PubDate:
Nov. 2017
Issue No:Vol. 7, No. 11 (2017)

Authors:
Hamza Salih Erden;Mustafa Koz;Mehmet T. Yildirim;H. Ezzat Khalifa;
Pages: 1795 - 1803Abstract: Aisle containment separates hot and cold aisles in air-cooled data centers to prevent hot air recirculation into cold aisle and decrease temperature nonuniformity among the servers. Uniform server inlet temperatures allow the cooling system to operate more efficiently at a higher evaporator temperature. Lower cooling power consumption can be achieved by optimizing the combined power consumption of the chillers and the computer room air handlers (CRAHs) fans. CRAH bypass (BP) is proposed, in which additional fans at the tiles induce a fraction of tile flow from the room into the plenum through low-resistance ports or leakage paths, thus decreasing the airflow passing through the high pressure resistance of the CRAH heat exchangers and filters and associated fan power usage. A further advantage of the proposed induced CRAH BP is the elimination of leakage as a result of reversing the room-plenum pressure difference. However, in order to keep the enclosed-aisle temperature below acceptable limits (typically ≤27 °C), the chiller needs to operate at a lower, less efficient temperature. This paper presents the experimental verification of a flow network model (FNM) in a data center test cell demonstrating the proposed induced CRAH BP concept. Exercise of the verified FNM in conjunction with a thermodynamic model of the cooling infrastructure (TDM) confirms that there is an optimum BP fraction that minimizes the combined chiller and CRAH fan power consumption.PubDate:
Nov. 2017
Issue No:Vol. 7, No. 11 (2017)

Authors:
Jorge M. Cruz-Duarte;Arturo Garcia-Perez;Ivan M. Amaya-Contreras;C. Rodrigo Correa-Cely;Rene J. Romero-Troncoso;J. Gabriel Avina-Cervantes;
Pages: 1804 - 1812Abstract: This paper proposes a conceptual design strategy for an optimal cooling system, typically used in several microelectronic devices. The methodology was implemented using the entropy generation minimization (EGM) criterion, powered by the cuckoo search (CS) algorithm. EGM-CS methodology was addressed to design rectangular microchannel heat sinks, utilizing high thermal conductive graphite as build material and a water-based colloid as coolant. This strategy was implemented under different hydrodynamic conditions, where it showed strong capability to achieve optimal designs with flowing nanofluids in either laminar or turbulent regimes. In addition, two types of nanoparticles were considered, i.e., Al and TiO2, with several values of volume fraction, as a passive mechanism for enhancing overall system performance. It was corroborated that all considered flowing colloids in laminar regime improve the thermal efficiency of the system. Moreover, an additional enhancement of this performance was observed with smaller nanoparticle concentrations (e.g., 0.01 wt/wt%), which also reduces the side effects due to nanoclustering. Furthermore, fluids with titanium dioxide nanoparticles showed slightly better thermal performance enhancement compared to aluminum particles.PubDate:
Nov. 2017
Issue No:Vol. 7, No. 11 (2017)

Authors:
Cagan Diyaroglu;Selda Oterkus;Erkan Oterkus;Erdogan Madenci;
Pages: 1823 - 1831Abstract: Diffusion modeling is essential in understanding many physical phenomena such as heat transfer, moisture concentration, and electrical conductivity. In the presence of material and geometric discontinuities and nonlocal effects, a nonlocal continuum approach, named peridynamics (PD), can be advantageous over the traditional local approaches. PD is based on integro-differential equations without including any spatial derivatives. In general, these equations are solved numerically by employing meshless discretization techniques. Although fundamentally different, commercial finite-element software can be a suitable platform for PD simulations that may result in several computational benefits. Hence, this paper presents the PD diffusion modeling and implementation procedure in a widely used commercial finite-element analysis software, ANSYS. The accuracy and capability of this approach is demonstrated by considering several benchmark problems.PubDate:
Nov. 2017
Issue No:Vol. 7, No. 11 (2017)

Authors:
Suman Bhowmik;Sambhu Nath Pradhan;Bidyut K. Bhattacharyya;
Pages: 1832 - 1841Abstract: In this paper, a method has been proposed by which one can reduce the clock jitter and achieve almost flat frequency clock output from the phase-locked loop (PLL), independent of the power supply voltage fluctuation. These voltage fluctuations occur when a given chip comes out from the sleep mode to the active mode. This causes the chip to draw a hasty current, which in turn produces LdI/dt noise. That causes the voltage to drop and also to oscillate at the power delivery network's resonance frequency. This power supply noise causes clock jitter. The voltage-controlled oscillator of the proposed PLL is designed at 45-nm technology such that when there is supply voltage variation, it is automatically corrected by a feedback methodology having only 11-ps response time delay, compared to 588-ps clock period. Simulation result shows that, for the proposed new PLL design, the number of places where the clock periods are altered due to this power supply voltage fluctuation is reduced. The performance of the proposed PLL design in terms of reduction of clock jitter, caused by the variation of power supply voltage and the flatness of the frequency versus power supply voltages, is tested by feeding the clock to a circuit (c17 of ISCAS'85) for the conventional methodology and also for our new methodology. It has been shown that, using the proposed method, the clock jitter caused by the power supply noise can be reduced by about 50% compared to the conventional design methodology.PubDate:
Nov. 2017
Issue No:Vol. 7, No. 11 (2017)

Authors:
Torsten Reuschel;Jan B. Preibisch;Katharina Scharff;Renato Rimolo-Donadio;Xiaomin Duan;Young H. Kwark;Christian Schuster;
Pages: 1842 - 1851Abstract: High-speed data links that utilize multilayer printed circuit boards suffer from loss, dispersion, and intersymbol interference. Often, equalization and error correction are required to make these channels functional at gigabit data rates and demand costly analyses. The characterization of loss-dominated links can be generalized and simplified by means of a normalized link length as presented herein. Based on a correlation of this normalized length and observed eye opening, a novel assessment of wired digital links for frequencies up to 50GHz and data rates up to 30 Gb/s is proposed. It allows for an efficient prediction of the amount and type of required equalization for a given link as well as determining maximum tolerable loss for a given equalizer configuration. The proposed method and its applicability are demonstrated by means of practical examples.PubDate:
Nov. 2017
Issue No:Vol. 7, No. 11 (2017)

Authors:
Po-Chun Chen;Kang-Yun Yang;Ying-Hsi Lin;Wen-Shan Wang;Ting-Ying Wu;Ruey-Beei Wu;
Pages: 1852 - 1858Abstract: This paper proposes a novel two-cap wideband filter that suppresses the high-frequency noise in a power trace routing. By combining electromagnetic bandgap (EBG) theory and decoupling capacitors, the EBG propagation characteristics are studied and a systematic design procedure is proposed. Advanced Design System (ADS) and gigahertz transverse electromagnetic (GTEM) cell measurement are used to validate the accuracy of the proposed analysis and the validity of the design. It is found that the filter gives a 67% stopband with 20-dB suppression, using only two capacitors that are spaced one-twentieth of a wavelength apart.PubDate:
Nov. 2017
Issue No:Vol. 7, No. 11 (2017)

Authors:
Ke Wu;Zheyao Wang;
Pages: 1859 - 1868Abstract: This paper presents design, fabrication, and high-frequency characterization of through-silicon-vias (TSVs) with benzocyclobutene (BCB) as the dielectric liner to exploit its low dielectric constant. Fabrication processes for BCB polymer liner TSVs are developed, and BCB-liner TSVs have been successfully fabricated in both low-resistivity silicon and high-resistivity silicon substrates for comparison. A de-embedding method that enables extraction of S-parameters from cascade TSV chains is developed based on the thru-reflect-line calibration algorithm, and the S-parameters of BCB-liner TSVs have been obtained from the measured transmission properties of cascade TSV chains with frequencies up to 25 GHz. Measurement results show that the BCB liner improves transmission properties of TSVs up to 10 GHz compared with SiO2-liner TSVs, and substrate resistivity dominates transmission properties for frequencies higher than 10 GHz.PubDate:
Nov. 2017
Issue No:Vol. 7, No. 11 (2017)

Authors:
Stefano Grivet-Talocia;
Pages: 1869 - 1881Abstract: This paper presents an algorithm for checking and enforcing passivity of behavioral reduced-order macromodels of linear time-invariant systems, whose frequency-domain (scattering) responses depend on external parameters. Such models, which are typically extracted from sampled input-output responses obtained from numerical solution of first-principle physical models, usually expressed as partial differential equations, prove extremely useful in design flows since they allow optimization, what-if or sensitivity analyses, and design centering. Starting from an implicit parameterization of both poles and residues of the model, as resulting from well-known model identification schemes based on the generalized Sanathanan-Koerner iteration, we construct a parameter-dependent skew-Hamiltonian/Hamiltonian matrix pencil. The iterative extraction of purely imaginary eigenvalues of the pencil, combined with an adaptive sampling scheme in the parameter space, is able to identify all regions in the frequency-parameter plane where local passivity violations occur. Then, a singular value perturbation scheme is set up to iteratively correct the model coefficients, until all local passivity violations are eliminated. The final result is a corrected model, which is uniformly passive throughout the parameter range. Several numerical examples demonstrate the effectiveness of the proposed approach.PubDate:
Nov. 2017
Issue No:Vol. 7, No. 11 (2017)

Authors:
Huimin He;Fengman Liu;Haiyun Xue;Peng Wu;Mangu Song;Cheng Chen;Yu Sun;Liqiang Cao;
Pages: 1882 - 1890Abstract: Short-reach optical interconnection mainly focuses on the power consumption, the cost, and the volume. According to these requirements, the design and implementation of a multichannel transceiver are presented in this paper. In this paper, a high-coupling method without the 90° beam deflection is proposed so as to reduce the total power consumption to 0.9 W. Moreover, only the mature and low-cost packaging methods such as wire bonding and flip chip are adopted to satisfy the requirement of the optical coupling, which reduces the cost. Finally, the designed transceiver retains a small size of $28times 16 ,, times $ 3 mm3. To ensure normal function of the transceiver, the organic substrate is carefully designed, and the post-design simulation is conducted to characterize the electrical performance. At last, the test results show that the optical transceiver with this novel packaging structure is able to transmit the data at 10 Gb/s per channel successfully.PubDate:
Nov. 2017
Issue No:Vol. 7, No. 11 (2017)

Authors:
Sung Yun Jun;Benito Sanz-Izquierdo;Edward A. Parker;David Bird;Alan McClelland;
Pages: 1891 - 1898Abstract: The use of additive manufacturing (AM) techniques for the fabrication of 3-D fractal monopole antennas is presented. The 3-D printing (3-D P) of 3-D designs based on the Sierpinski fractal concept is studied, and the performance discussed. The AM allows the fabrication of the complex features of these antennas. The specific structures, on the other hand, provide a reduction of the material used in AM compared with the equivalent nonfractal designs, in which two cases can be described by over 75%. This is the first time that 3-D fractals have been studied in terms of volume reduction and their potential benefits to AM of antennas. The first investigated antenna derives from the Sierspinki tetrahedron fractal shape. From this initial design, two new structures have been developed: the dual Sierpinksi fractal and the dual inverse Sierpinski fractal. The new designs offer improved matching and radiation pattern. All the antennas operate at 2.4 GHz used in Bluetooth and wireless LAN band. Furthermore, the final inverse fractal shape is able to cover both the 2.4- and 5.5-GHz WLAN frequencies with a reflection coefficient (S11) better than -10 dB, together with coverage at bands around 8 GHz. This ratio of resonant frequencies is achieved after a series of described design stages. The radiation patterns of the antennas are monopole-like at both bands. The AM technique employed is metal powder embinder printing where a binding material is jetted on a powder bed containing metal particles. Metal 3-D P is ideal for maintaining the mechanical strength of the structures. The envisaged applications are in the defense and aerospace sectors where high-value, lightweight, and mechanically robust antennas can be integrated with other 3-D printed parts. Transient simulations based on the finite integration technique compare well with measurements.PubDate:
Nov. 2017
Issue No:Vol. 7, No. 11 (2017)

Authors:
Ya-Sheng Tang;Jaber Derakhshandeh;Yi-Tung Kho;Yao-Jen Chang;John Slabbekoorn;Inge De Preter;Kris Vanstreels;Kenneth June Rebibis;Eric Beyne;Kuan-Neng Chen;
Pages: 1899 - 1905Abstract: The demand of small-feature-size, high-performance, and dense I/O density applications promotes the development of fine-pitch vertical interconnects for 3-D integration where microbumps are fabricated with Cu through-silicon via and under-bump metallization. Small dimension Cu/Sn bonding has to be developed to address the needs of increasing I/O density and shrinking pitch and size for future applications. For fine-pitch microbumps, it is important to select right UBM and solder materials to obtain lower UBM consumption, which means lower intermetallic compound (IMC) thickness. To find the best binary system material for fine-pitch microbumps with a different annealing temperature and time, we investigate the interfacial reaction and intermetallic compound morphologies of Co UBM with Sn, SnCu, and SAC solders. A thin, uniform, and single-phase IMC between solder and UBM facilitates finer pitch and more reliable microbumps development; the higher activation energies imply longer solder lifetime. Co, as an ultrathin buffer layer (UBL), is also used in Cu/Sn bonding. A comparison between Cu-Sn bonding with and without UBL is conducted. From this study, Co as UBL and UBM is explored and could be applied in semiconductor applications.PubDate:
Nov. 2017
Issue No:Vol. 7, No. 11 (2017)

Authors:
Chien-Yi Huang;
Pages: 1911 - 1919Abstract: The emergence of environmental awareness, particularly regarding green packaging, has caused SAC305, a tin-silver-copper alloy (Sn 96.5%, Ag 3%, and Cu 0.5%), to become a widely used lead-free solder material. The use of SAC305 increases in temperature requirements for reflow soldering roughly 15 °C-35 °C compared with that of the use of Sn63Pb37, a conventional tin-lead solder. However, component and printed circuit board (PCB) warpage may occur when subject to high temperature, leading to open solder joints and other defects. The ball grid array (BGA), quad flat pack, and dual-flat no-lead (DFN-8) packaging components of server PCBs were tested in this paper. First, the height of the component contacts, printing thickness of the solder paste, and PCB and component warpage were examined, and geometric principles were applied to establish an open solder joint model for nonflat solder joints. Subsequently, the Monte Carlo simulation method was used to sample the aforementioned parameters randomly and calculate the distance between the contacts at the bottom of the electronic component and the surface of the solder paste. A threshold value was used to determine whether the contacts at the bottom of the components were connected to the surface of the solder paste and independently evaluate the occurrence of open solder joints before and during reflow soldering.PubDate:
Nov. 2017
Issue No:Vol. 7, No. 11 (2017)