HMC830 absolute phase sync

In our application we have to sweep two PLLs over multiple frequencies. The absolute phase offset of both PLL-Outputs with respect to the reference should remain constant or at least predictable over all Frequency sweep. Unfortunatelly we are fixed to the HMC830

PLL and it is not possible to use other PLLs with phase sync function. The difference is in Seed value, that can be programmed to 4 init values only. Is it possible to reach the phase sync using this PLL?

According to this thread https://ez.analog.com/message/214063#214063 it will be not possible to zero the random phase offset due to the poor SPI-timing. According to the application I have a couple of opened questions I would like to adress to the forum members

Is there any solution to sync the register writes of both PLLs or is it an intern problem of the PLL-Structure

The first and second requirements are easy - just program both parts with one of the four available seeds and distribute the reference clocks with a zero delay buffer and equal trace lengths. The third requirement is necessary because the DSM is clocked off the divided VCO clock. The phase between two parts will only be aligned when the DSM pseudo random sequence is synchronized.

In theory if the rising SEN edge occurs on both parts at the same time the seed register should update at the same time. In practice since the SPI interface is on a separate clock domain the data transfer timing is not well controlled. This causes an uncertainty on exactly which divided VCO cycle loads the seed. Synchronizing SEN to the reference helps but an adjustment is still necessary since the timing varies with VCO frequency. Phase alignment also varies between parts due to offset current accuracy and temperature dependent phase detector delays. Even in integer mode there is still some miss-alignment due to temperature dependent delays.

The HMC835 was designed for phase adjust applications. Exact mode controls when the seed gets loaded into the DSM instead of relying on SPI timing. Exact mode uses Reg 0x0C as the start value for a count down counter clocked off the reference clock. When the counter reaches zero the seed gets loaded. Now we can align the phase by adjusting the seed in one part. Note the counters in both parts reach zero at different times but it doesn't matter since we're just adjusting the phase of one device relative to the the other.

The HMC830 has exact mode but unfortunately the exact mode counter is clocked off the divided VCO. This means all counters reach zero at different times on every frequency change (the VCOs unlock for a short period of time during the frequency switch). It's a mote point since with only four seed values available you can't align phase. This is why the HMC835 allows full 24 bit resolution on the seed value.

The first and second requirements are easy - just program both parts with one of the four available seeds and distribute the reference clocks with a zero delay buffer and equal trace lengths. The third requirement is necessary because the DSM is clocked off the divided VCO clock. The phase between two parts will only be aligned when the DSM pseudo random sequence is synchronized.

In theory if the rising SEN edge occurs on both parts at the same time the seed register should update at the same time. In practice since the SPI interface is on a separate clock domain the data transfer timing is not well controlled. This causes an uncertainty on exactly which divided VCO cycle loads the seed. Synchronizing SEN to the reference helps but an adjustment is still necessary since the timing varies with VCO frequency. Phase alignment also varies between parts due to offset current accuracy and temperature dependent phase detector delays. Even in integer mode there is still some miss-alignment due to temperature dependent delays.

The HMC835 was designed for phase adjust applications. Exact mode controls when the seed gets loaded into the DSM instead of relying on SPI timing. Exact mode uses Reg 0x0C as the start value for a count down counter clocked off the reference clock. When the counter reaches zero the seed gets loaded. Now we can align the phase by adjusting the seed in one part. Note the counters in both parts reach zero at different times but it doesn't matter since we're just adjusting the phase of one device relative to the the other.

The HMC830 has exact mode but unfortunately the exact mode counter is clocked off the divided VCO. This means all counters reach zero at different times on every frequency change (the VCOs unlock for a short period of time during the frequency switch). It's a mote point since with only four seed values available you can't align phase. This is why the HMC835 allows full 24 bit resolution on the seed value.

Thank you four your response. As I can see, I will leave the idea of syncing the phase in the fractional mode.

What about the integer mode of operation? What is the necessary condition for the phase alignment? I run some tests in the last days but with the results are confusing for me. I have a PCB with two PLLs with a common crystal reference and measure the phase offset between the both output signals. Moreover both PLLs have the same configuration R=K=1, and N1=N2. Unfortunately at some frequencies the phase offset of both PLLs varies by approximately 210°. This means if I am changing the frequency between f1 and f2, the measured phase difference at frequency f1 is (116° or -92°) but phase offset at f2 stays always close to -83°.

Have someone any explanation for this behaviour? From my understanding, if the DSM is off, the output signal phase should be locked to the common reference, what in turn results in the constant phase offset between the two PLL outputs.

Phase alignment in integer mode requires R=1 and output-divide by 1 otherwise the dividers introduce large phase errors. With these dividers bypassed you will still see a small temperature dependent phase error between the reference edge and VCO due to internal delays:

reference clock to Q delays on the reference path into the PFD

phase detector mismatch

VCO clock to Q delay on the feedback path into the PFD

If two parts have exactly the same internal delays there would be no output phase error. In practice we expect part to part variations of around +- 20ps. At 3G this corresponds to a phase error of about +-21 degrees in integer mode.