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Cost modeling and analysis for interposer-based three-dimensional IChttp://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83921
title: Cost modeling and analysis for interposer-based three-dimensional IC abstract: Three-dimensional (3D) integration has recently become a popular technology for integrated circuits (IC). 3D IC with the passive silicon interposer is currently the main trend in the industry, especially for processor-memory integration. Evaluating the economic efficiency of test operations in the interposer-based 3D IC thus is important. We propose a cost model for the Die-to-Wafer (D2W) and Die-to-Die (D2D) stacking, including manufacturing cost and test cost. A tool which is based on the proposed cost model is developed. We use this tool for cost analysis and for finding the most cost effective test flow. The results show that, in some applications, test flows including the iterative known-good stack (KGS) test and the pre-bond interposer test significantly reduce the cost, when the KGS test yield is lower than 98.2% and the pre-bond interposer test yield is lower than 99.38%. A Shmoo plot is depicted to show the lower bound of the yield of the final package level test, given the number of stacked dies and the final yield. For different applications, the proposed model evaluates the critical yield or cost values, which helps the designers to determine the most cost effective test flow and the system architecture.
<br>A memory failure pattern analyzer for memory diagnosis and repairhttp://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83920
title: A memory failure pattern analyzer for memory diagnosis and repair abstract: As VLSI technology advances and memories occupy more and more area in a typical SOC, memory diagnosis has become an important issue. In this paper, we propose the Memory Failure Pattern Analyzer (MFPA), which is developed for different memories and technologies that are currently used in the industry. The MFPA can locate weak regions of the memory array, i.e., those with high failure rate. It can also be used to analyze faulty-cell/defect distributions automatically. We also propose a new defect distribution model which has 1-12 times higher accuracy than other theoretical models. Based on this model, we propose a defect-spectrum-based methodology to identify critical failure patterns from failure bitmaps. These failure patterns can further be translated to corresponding defects by our memory fault simulator (RAMSES) and physical-level failure analysis tool (FAME). In an industrial case, the MFPA fits the defect distribution with the proposed model, which has 12 times higher accuracy than the Poisson distribution. With our model, it further identifies two special failure patterns from 132,488 faulty 4-Mb macros in 1.2 minutes.
<br>Multi-visit TAMs to reduce the post-bond test length of 2.5D-SICs with a passive silicon interposer basehttp://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83919
title: Multi-visit TAMs to reduce the post-bond test length of 2.5D-SICs with a passive silicon interposer base abstract: 2.5D Stacked ICs (2.5D-SICs) consist of multiple active dies (or 3D towers of active dies), which are placed side-by-side on top of and interconnected through a passive silicon interposer base which contains Through-Silicon Vias (TSVs). A previously presented post-bond test and Design-for-Test (DfT) strategy for such 2.5D-SICs implements a serial Test Access Mechanism (TAM) for interposer and micro-bump testing. In addition, it tries to identify an as-wide-as-possible set of functional interposer interconnects that can be reused as parallel TAMs to the various dies. In this paper, we extend that approach with the concept of Multi-Visit TAMs, i.e., parallel TAMs which are allowed to visit the same die more than once. For minimal additional hardware costs, the Multi-Visit TAMs succeed significantly more often in identifying a valid parallel TAM and achieve significantly lower test lengths.
<br>Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer basehttp://nthur.lib.nthu.edu.tw/dspace/handle/987654321/83918
title: Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base abstract: Through-Silicon Vias (TSVs) enable high-density, low-latency, and low-power interconnects for system chips that consist of multiple dies. In &quot;2.5D&quot; Stacked ICs (2.5D-SICs), multiple dies without TSVs are stacked side-by-side on top of a passive silicon interposer base containing TSVs. In true 3D-SICs, multiple dies containing TSVs themselves are vertically stacked; one or multiple of such stacks are possibly placed on a passive silicon interposer. This paper proposes a post-bond test and design-for-test (DfT) strategy for 2.5D- and 3D-SICs containing a passive silicon interposer base. Functional interconnects in the interposer are reused as much as possible in order to keep the interposer cost low.
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