Legend:

The goal of the SIMD project is to allow GHC and Haskell libraries to take advantage of SIMD vector instructions. Please see the proposed [wiki:SIMD/Design design] and he current [wiki:SIMD/Implementation/Status implementation status] for further details.

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= Using SIMD instructions in GHC =

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'''Goal''': improve program running times by taking advantage of CPU's SIMD vector instructions.

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'''How''': by extending GHC to generate code using SIMD vector instructions and by modifying libraries as necessary.

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This page describes the issues involved and a design for implementing SIMD vector support in GHC.

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Related pages:

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* Notes on the [wiki:SIMDPlan current implementation plan]

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== Introduction ==

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We are interested in the SIMD vector instructions on current and future generations of CPUs. This includes SSE and AVX on x86/x86-64 and NEON on ARM chips (targets like GPUs or FPGAs are out of scope for this project). These SIMD vector instruction sets are broadly similar in the sense of having relatively short vector registers and operations for various sizes of integer and/or floating point operation. In the details however they have different capabilities and different vector register sizes.

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We therefore want a design for SIMD support in GHC that will let us efficiently exploit current vector instructions but a design that is not tied too tightly to one CPU architecture or generation. In particular, it should be possible to write portable Haskell programs that use SIMD vectors.

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On the other hand, we want to be able to write programs for maximum efficiency that exploit the native vector sizes, preferably while remaining portable. For example, algorithms on large variable length vectors are in principle agnostic about the size of the primitive vector operations.

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Finally, we want a design that is not too difficult or time consuming to implement.

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=== Use cases ===

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We are mainly interested in scientific / numerical use cases with large arrays / vectors. These are the kinds of use cases that DPH already targets.

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In the interests of limiting implementation difficulty, we are prepared initially to sacrifice performance in use cases with small vectors. Examples with lots of small vectors include 3D work where there are lots of 4-element vectors and 4x4 matrices. These tradeoffs show up in our choices about calling conventions and vector memory alignment which are discussed below.

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Note: we will need to be clear with users that initially this SIMD work is not suitable for small vectors, just big arrays.

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=== Existing SIMD instruction sets ===

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Intel and AMD CPUs use the [http://en.wikipedia.org/wiki/Streaming_SIMD_Extensions SSE family] of extensions and, more recently (since Q1 2011), the [http://en.wikipedia.org/wiki/Advanced_Vector_Extensions AVX] extensions. ARM CPUs (Cortex A series) use the [http://www.arm.com/products/processors/technologies/neon.php NEON] extensions. PowerPC and SPARC have similar vector extensions. Variations between different families of SIMD extensions and between different family members in one family of extensions include the following:

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'''Register width'''::

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SSE registers are 128 bits, whereas AVX registers are 256 bits, but they can also still be used as 128 bit registers with old SSE instructions. NEON registers can be used as 64-bit or 128-bit register.

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'''Register number'''::

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SSE sports 8 SIMD registers in the 32-bit i386 instruction set and 16 SIMD registers in the 64-bit x84_64 instruction set. (AVX still has 16 SIMD registers.) NEON's SIMD registers can be used as 32 64-bit registers or 16 128-bit registers.

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'''Register types'''::

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In the original SSE extension, SIMD registers could only hold 32-bit single-precision floats, whereas SSE2 extend that to include 64-bit double precision floats as well as 8 to 64 bit integral types. The extension from 128 bits to 256 bits in register size only applies to floating-point types in AVX. This is expected to be extended to integer types in AVX2, but in AVX, SIMD operations on integral types can only use the lower 128 bits of the SIMD registers. NEON registers can hold 8 to 64 bit integral types and 32-bit single-precision floats.

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'''Alignment requirements'''::

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SSE requires alignment on 16 byte boundaries. With AVX, it seems that operations on 128 bit SIMD vectors may be unaligned, but operations on 256 bit SIMD vectors needs to be aligned to 32 byte boundaries. NEON suggests to align SIMD vectors with ''n''-bit elements to ''n''-bit boundaries.

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=== SIMD/vector support in other compilers ===

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Both GCC and LLVM provide some low-level yet portable support for SIMD vector types and operations.

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GCC provides [http://gcc.gnu.org/onlinedocs/gcc/Vector-Extensions.html vector extensions] to C where the programmer may define vector types of a fixed size. The standard C `+`, `-`, `*` etc operators then work on these vector types. GCC implements these operations using whatever hardware support is available. Depending on the requested vector size GCC uses native vector registers and instructions, or synthesises large requested vectors using smaller hardware vectors. For example it can generate code for operating on vectors of 4 doubles by using SSE2 registers and operations which only handle vectors of doubles of size 2.

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The LLVM compiler tools targeted by GHC's [wiki:Commentary/Compiler/Backends/LLVM LLVM backend] support a generic [http://llvm.org/docs/LangRef.html#t_vector vector type] of arbitrary, but fixed length whose elements may be any LLVM scalar type. In addition to three [http://llvm.org/docs/LangRef.html#vectorops vector operations], LLVM's operations on scalars are overloaded to work on vector types as well. LLVM compiles operations on vector types to target-specific SIMD instructions, such as those of the SSE, AVX, and NEON instruction set extensions. As the capabilities of the various versions of SSE, AVX, and NEON vary widely, LLVM's code generator maps operations on LLVM's generic vector type to the more limited capabilities of the various hardware targets.

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== General plan ==

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We need to implement support for vectors in several layers of GHC + Libraries, from bottom to top:

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* code generators (NCG, LLVM)

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* Cmm

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* Haskell/Core primops

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* Some strategy for making use of vector primops, e.g. DPH or Vector lib

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=== Vector types ===

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We intend to provide vectors of the following basic types:

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|| Int8 || Int16 || Int32 || Int64 ||

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|| Word8 || Word16 || Word32 || Word64 ||

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|| || || Float || Double ||

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=== Fixed and variable sized vectors ===

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The hardware supports only small fixed sized vectors. High level libraries would like to be able to use arbitrary sized vectors. Similar to the design in GCC and LLVM we will provide primitive Haskell types and operations for fixed-size vectors. The task of implementing variable sized vectors in terms of fixed-size vector types and primops is left to the next layer up (DPH, vector lib).

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That is, in the core primop layer and down, vector support is only for fixed-size vectors. The fixed sizes will be only powers of 2 and only up to some maximum size. The choice of maximum size should reflect the largest vector size supported by the current range of CPUs (256bit with AVX):

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|| types || || || vector sizes ||

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|| Int8 || Word8 || || 2, 4, 8, 16, 32 ||

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|| Int16 || Word16 || || 2, 4, 8, 16 ||

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|| Int32 || Word32 || Float || 2, 4, 8 ||

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|| Int64 || Word64 || Double || 2, 4 ||

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|| Int || Word || || 2, 4 ||

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In addition, we will support vector types with fixed but architecture-dependent sizes (see below).

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We could choose to support larger fixed sizes, or the same maximum size for all types, but there is no strict need to do so.

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=== Portability and fallbacks ===

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To enable portable Haskell code we will provide the same set of vector types and operations on all architectures. Again this follows the approach taken by GCC and LLVM.

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We will rely on fallbacks for the cases where certain types or operations are not supported directly in hardware. In particular we can implement large vectors on machines with only small vector registers. Where there is no vector hardware support at all for a type (e.g. arch with no vectors or 64bit doubles on ARM's NEON) we can implement it using scalar code.

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The obvious approach is a transformation to synthesize larger vector types and operations using smaller vector operations or scalar operations. This synthesisation could plausibly be done at the core, Cmm or code generator layers, however the most natural choice would be as a Cmm -> Cmm transformation. This approach would reduce or eliminate the burden on code generators by allowing them to support only their architecture's native vector sizes and types, or none at all.

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Using fallbacks does pose some challenges for a stable/portable ABI, in particular how vector registers should be used in the GHC calling convention. This is discussed in a later section.

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=== GHC command line flags ===

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We will add machine flags such as `-msse2` and `-mavx`. These tell GHC that it is allowed to make use of the corresponding instruction sets.

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For compatibility, the default will remain targeting the base instruction set of the architecture. This is the behaviour of most other compilers. We may also want to add a `-mnative` / `-mdetect` flag that is equivalent to the `-m` flag corresponding to the host machine.

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== Code generators ==

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We will not extend the portable C backend to emit vector instructions. It will rely on the higher layers transforming vector operations into scalar operations. The portable C backend is not ABI compatible with the other code generators so there is no concern about vector registers in the calling convention.

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The LLVM C library supports vector types and instructions directly. The GHC LLVM backend could be extended to translate vector ops at the Cmm level into LLVM vector ops.

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The NCG (native code generator) may need at least minimal support for vector types if vector registers are to be used in the calling convention (see below). If we choose a common calling convention where vectors are passed in registers rather than on the stack then minimal support in the NCG would be necessary if ABI compatibility is to be preserved with the LLVM backend. It is optional whether vector instructions are used to improve performance.

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== Cmm layer ==

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The Cmm layer will be extended to represent vector types and operations.

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The `CmmType` describes the machine-level type of data. It consists of the "category" of data, along with the `Width` in bits.

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{{{

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data CmmType = CmmType CmmCat Width

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data Width = ...

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data CmmCat -- "Category" (not exported)

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= GcPtrCat -- GC pointer

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| BitsCat -- Non-pointer

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| FloatCat -- Float

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}}}

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The current code distinguishes floats, pointer and non-pointer data. These are distinguished primarily because either they need to be tracked separately (GC pointers) or because they live in special registers on many architectures (floats).

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For vectors we add two new categories

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{{{

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| VBitsCat Multiplicity -- Non-pointer

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| VFloatCat Multiplicity -- Float

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type Multiplicty = Int

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}}}

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We keep vector types separate from scalars, rather than representing scalars as having multiplicty 1. This is to limit disruption to existing code paths and also because it is expected that vectors will often need to be treated differently from scalars. Again we distinguish float from integral types as these may use different classes of registers. There is no need to support vectors of GC pointers.

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Vector operations on these machine vector types will be added to the Cmm `MachOp` type, e.g.

We need Haskell data types and Haskell primitive operations for fixed size vectors. In some ways this is a harder problem than representing the vector types and opertions at the Cmm level. In particular, at the Haskell type level we cannot easily parametrise on the vector length.

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Our design is to provide a family of fixed size vector types and primitive operations, but not to provide any facility to parametrise this family on the vector length.

Internally in GHC we can take advantage of the obvious parametrisation within the families of primitive types and operations. In particular we extend GHC's `primop.txt.pp` machinery to enable us to describe the family as a whole and to generate the members.

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For example, here is some plausible concrete syntax for `primop.txt.pp`:

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{{{

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parameter <w, m> Width Multiplicity

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with <w, m> in <8, 2>,<8, 4>,<8, 8>,<8, 16>,<8, 32>,

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<16,2>,<16,4>,<16,8>,<16,16>,

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<32,2>,<32,4>,<32,8>,

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<64,2>,<64,4>

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}}}

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Note that we allow non-rectangular combinations of values for the parameters. We declare the range of values along with the parameter so that we do not have to repeat it for every primtype and primop.

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{{{

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primtype <w,m> Int<w>Vec<m>#

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primop VIntAddOp <w,m> "addInt<w>Vec<m>#" Dyadic

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Int<w>Vec<m># -> Int<w>Vec<m># -> Int<w>Vec<m>#

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{Vector addition}

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}}}

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This would generate a family of primops, and an internal representation using the type names declared for the parameters:

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{{{

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data PrimOp = ...

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| IntAddOp

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| VIntQuotOp Width Multiplicity

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}}}

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It is not yet clear what syntax to achieve the names of the native sized types `Int` and `Word`. Perhaps we should use "", e.g.

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{{{

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parameter <w, m> Width Multiplicity

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with <w, m> in <8, 2>,<8, 4>,<8, 8>,<8, 16>,<8, 32>,

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<16,2>,<16,4>,<16,8>,<16,16>,

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<32,2>,<32,4>,<32,8>,

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<64,2>,<64,4>

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<"",2>,<"",4>

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}}}

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=== Optional extension: primitive int sizes ===

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The above mechanism could be used to handle parametrisation between Int8#, Int16# etc. Currently these do not exist as primitive types. The types Int8, Int16 etc are implemented as a boxed native-sized Int# plus narrowing.

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Note that while this change is possible and would make things more uniform it is not essential for vector support.

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That is we might have:

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{{{

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parameter <w> Width

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with <w> in <8>, <16>, <32>, <64>, <"">

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primtype Int<w>#

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primop IntAddOp <w> "addInt<w>#" Dyadic

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Int<w># -> Int<w># -> Int<w>#

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with commutable = True

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}}}

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generating

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{{{

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data PrimOp = ...

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| IntAddOp Width

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}}}

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We might want some other solution so we can use `+#` as well as `addInt#` since `+8#` as an infix operator doesn't really work.

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== Native vector sizes ==

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In addition to various portable fixed size vector types, we will have a portable vector type that is tuned for the hardware vector register size. This is analogous to the existing integer types that GHC supports. We have Int8, Int16, Int32 etc and in addition we have Int, the size of which is machine dependent (either 32 or 64bit).

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As with Int, the rationale is efficiency. For algorithms that could work with a variety of primitive vector sizes it will almost always be fastest to use the vector size that matches the hardware vector register size. Clearly it is suboptimal to use a vector size that is smaller than the native size. Using a larger vector is not nearly as bad as using as smaller one, though it does contribute to register pressure.

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Without a native sized vector, libraries would be forced to use CPP to pick a good vector size based on the architecture, or to pick a fixed register size that is always at least as big as the native size on all platforms that are likely to be used. The former is annoying and the latter makes less sense as vector sizes on some architectures increase.

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Note that the actual size of the native vector size will be fixed per architecture and will not vary based on "sub-architecture" features like SSE vs AVX. We will pick the size to be the maximum of all the sub-architectures. That is we would pick the AVX size for x86-64. The rationale for this is ABI compatibility which is discussed below. In this respect, the !IntVec# is like Int#, the size of both is crucial for the ABI and is determined by the target platform/architecture.

To iron out this wrinkle we would need the whole family of primitve types: Int8#, Int16#, Int32# etc whereas currently only the native register sized Int# type is provided, plus a primitive Int64# type is provided on 32bit systems.

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== Data Parallel Haskell layer ==

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In [http://www.haskell.org/haskellwiki/GHC/Data_Parallel_Haskell DPH], we will use the new SIMD instructions by suitably modifying the definition of the lifted versions of arithmetic and other operations that we would like to accelerate. These lifted operations are defined in the `dph-common` package and made accessible to the vectoriser via [wiki:DataParallel/VectPragma VECTORISE pragmas]. Many of them currently use `VECTORISE SCALAR` pragmas, such as

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{{{

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(+) :: Int -> Int -> Int

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(+) = (P.+)

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{-# VECTORISE SCALAR (+) #-}

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}}}

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We could define them more verbosely using a plain `VECTORISE` pragma, but might instead like to extend `VECTORISE SCALAR` or introduce a variant.

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'''NB:''' The use of SIMD instructions interferes with vectorisation avoidance for scalar subcomputations. Code that avoids vectorisation also avoids the use of SIMD instructions. We would like to use SIMD instructions, but still avoid full-scale vectorisation. This should be possible, but it is not immediately clear how to realise it (elegantly).

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== ABIs and calling conventions ==

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For each CPU architecture GHC has a calling convention that it uses for all Haskell function calls. The calling convention specifies where function arguments and results are placed in registers and on the stack. Adhering to the calling convention is necessary for correctness. Code compiled using different calling conventions should not be linked together. Note that currently the LLVM and NCG code generators adhere to the same ABI.

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The calling convention needs to be extended to take into account the primitive vector types. We have to decide if vectors should be passed in registers or on the stack and how to handle vectors that do not match the native vector register size.

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For efficiency it is highly desirable to make use of vector registers in the calling convention. This can be significantly quicker than copying vectors to and from the stack.

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Within the same overall CPU architecture, there are several sub-architectures with different vector capabilities and in particular different vector sizes. The x86-64 architecture supports SSE2 vectors as a baseline which includes pairs of doubles, but the AVX extension doubles the size of the vector registers. Ideally when compiling for AVX we would make use of the larger AVX vectors, including passing the larger vectors in registers.

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This poses a major challenge: we want to make use of large vectors when possible but we would also like to maintain some degree of ABI compatibility.

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=== Alternative design: separate ABIs ===

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It is worth briefly exploring the option of abandoning ABI compatibility. We could declare that we have two ABIs on x86-64, the baseline SSE ABI and the AVX ABI. We would further declare that to generate AVX code you must build all of your libraries using AVX. Essentially this would mean having two complete sets of libraries, or perhaps simply two instances of GHC, each with their own libraries. While this would work and may be satisfactory when speed is all that matters, it would not encourage use of vectors more generally. In practice haskell.org and linux distributions would have to distribute the more compatible SSE build so that in many cases even users with AVX hardware would be using GHC installations that make no use of AVX code. On x86 the situation could be even worse since the baseline x86 sub-architecture used by many linux distributions does not include even SSE2. In addition it is wasteful to have two instances of libraries when most libraries do not use vectors at all.

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=== Selected design: mixed ABIs using worker/wrapper ===

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It it worth exploring options for making use of AVX without having to force all code to be recompiled. Ideally the base package would not need to be recompiled at all and perhaps only have packages like vector recompiled to take advantage of AVX.

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Consider the situation where we have two modules `Lib.hs` and `App.hs` where `App` imports `Lib`. The `Lib` module exports:

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{{{

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f :: DoubleVec4# -> Int

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g :: (DoubleVec4# -> a) -> a

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}}}

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which are used by App. We compile:

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{{{

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ghc -msse2 Lib.hs

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ghc -mavx App.hs.

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}}}

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There are two cases to consider:

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* if the function being called has an unfolding exported from `Lib` then that unfolding can be compiled in the context of App and can make use of AVX instructions

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* alternatively we are dealing with object code for the function which follows a certain ABI

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Notice that not only do we need to be careful to call `f` and `g` using the right calling convention, but in the case of `g`, the function that we pass as its argument must also follow the calling convention that `g` will call it with.

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Our solution is to take a worker/wrapper approach. We will split each function into a wrapper that uses a lowest common denominator calling convention and a worker that uses the best calling convention for the target sub-architecture. The simplest lowest common denominator calling convention is to pass all vectors on the stack, while the fast calling convention will use SSE2 or AVX registers.

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For `App` calling `Lib.f` we start with a call to the wrapper, this can be inlined to a call to the worker at which point we discover that the calling convention will use SSE2 registers. For `App` calling `Lib.g` with a locally defined `h`, we would pass the wrapper for `h` to `g` and since we assume we have no unfolding for `g` then this is how it remains: at runtime `g` will call `h` through the wrapper for `h` and so will use the lowest common denominator calling convention.

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We might be concerned with the reverse situation where we have A and B, with A importing B:

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{{{

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ghc -mavx B.hs.

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ghc -msse2 A.hs

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}}}

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That is, a module compiled with SSE2 that imports a module that was compiled with AVX. How can we call functions using AVX registers if we are only targeting SSE2? There are two design options:

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* One option is to note that since we will be using AVX instructions at runtime when we call the functions in B, and hence it is legitimate to use AVX instructions in A also, at least for the calling convention.

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* The other is to avoid generating AVX instructions at all, even for the calling convention, in which case it is essential to avoid inlining the wrapper function since this exposes the worker that uses the AVX calling convention.

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While the first option is in some ways simpler, it also implies that all ABI-compatible code generators can produce at least some vector instructions. In particular it requires data-movement instructions to be supported. If however we wish to completely avoid implementing any vector support in the NCG backend then we must take the second approach.

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For the second approach we would need to add an extra architecture flag and check to inlining annotations. There are already several conditions that are checked prior to inlining (e.g. phase checks), this would add an additional check.

If we have support for arch-conditional inlining, we in future may want to extend the idea to allow inlining to one of a number of arch-specific implementations.

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Consider a hypothetical function in a core library that uses vectors but that is too large to be a candidate for inlining. We have to ship core libraries compiled for the base architecture. Hence the function from the core lib will not be compiled to use AVX. Another possibility is to generate several copies of the function worker, compiled for different sub-archtectires. Then when the function is called in another module compiled with -mavx we would like to call the AVX worker. This could be achieved by arch-conditional inlining or rules.

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This option should only be considered if we expect to have functions in core libs that are above the inlining threshold. This would probably not be the case for ghc-prim and base. It may however make sense for the vector library should that become part of the standard platform and hence typically shipped to users as a pre-compiled binary.

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=== Types for calling conventions ===

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One of GHC's clever design tricks is that the type of a function in core determines its calling convention. A function in core that accepts an Int is different to one that accepts an Int#. The use of two different types, Int and Int# let us talk about the transformation and lets us write code in core for the wrapper function that converts from Int to Int#.

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If we are to take a worker wrapper approach with calling conventions for vectors then we would do well to use types to distinguish the common and special calling conventions. For example, we could define sub-architecture specific types:

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{{{

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FloatSseVec4#

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DoubleSseVec2#

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FloatAvxVec8#

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DoubleAvxVec4#

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}}}

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We would also need some suitable primitive conversion operations

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{{{

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toSseVec4# :: FloatVec4# -> FloatSseVec4#

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fromSseVec4# :: FloatSseVec4# -> FloatVec4#

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etc

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}}}

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Then we can describe the types for the worker and wrapper for our function

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{{{

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f :: DoubleVec4# -> Int

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}}}

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This remains the type of the wrapper, which also is still called f. If we compile the module with -msse2 or -mavx then we would get workers with the respective types:

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{{{

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f_worker :: (# DoubleSseVec2#, DoubleSseVec2# #) -> Int

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}}}

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or

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{{{

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f_worker :: DoubleAvxVec4# -> Int

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}}}

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Note that in the SSE2 case we have to synthesize a vector of length 4 using native vectors of length 2.

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Now it is clearer what the calling convention of the workers are. What is the calling convention of the wrapper?

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{{{

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f :: DoubleVec4# -> Int

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}}}

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We have said that this is the lowest common denominator calling convention. The simplest is passing vectors on the stack. This has the advantage of not requiring vector support in the NCG.

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=== Calling convention and performance ===

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The mixed ABI approach using worker/wrapper trades off some performance for convenience and compatibility. Why do we think the tradeoff is reasonable?

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In the case of ordinary unboxed types, Int/Int# etc, this approach is very effective. It is only when calling unknown functions, e.g. higher order functions that are not inlined that we would be calling the wrapper and using the slower calling convention. This is unlikely for high performance numeric code.

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=== Optional extension: faster common calling convention ===

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On x86-64 we know we always have SSE2 available, so we might want to use that in our lowest common denominator calling convention. It would of course require support for vector data movement instructions in the NCG.

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=== Alternative design: only machine-specific ABI types ===

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With the above extension to use vectors registers in the common calling convention, it would make sense to say that in fact the wrapper `f` has type:

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{{{

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f :: (# DoubleSseVec2#, DoubleSseVec2# #) -> Int

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}}}

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This is a plausible design, but it is not necessary to go this way. We can simply declare types like `DoubleVec4#` to have a particular calling convention without forcing it to be rewritten in terms of machine-specific types in core.

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But it would be plausible to say that types like `DoubleVec4#` are ephemeral, having no ABI and must be rewritten by a core -> core pass to use machine-specific types with an associated ABI.

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=== Memory alignment for vectors ===

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Many CPUs that support vectors have strict alignment requirements, e.g. that 16 byte vectors must be aligned on 16byte boundaries. On some architectures the requirements are not strict but there may be a performance penalty, or alternative instruction may be required to load unaligned vectors. For example AVX has special instructions for unaligned loads and stores but Intel estimates a [http://software.intel.com/en-us/articles/practical-intel-avx-optimization-on-2nd-generation-intel-core-processors/ 20% performance loss].

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LLVM has primitives that can load and store vectors from unaligned memory locations, which (presumably) compile to either aligned vector instructions if the architecture has them, or non-vector instructions if not. So alignment of vectors in memory is optional, and we can make an independent choice about whether we align stored vectors

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* on the stack

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* in a heap closure

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* in an array

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'''Alignment in arrays.''' Arrays of vectors are clearly the most important case, so we must support allocation of aligned unboxed arrays. Indeed GHC already does support ''pinned'' arrays of unboxed data, and any array larger than about 3k is implicitly pinned. Supporting unpinned arrays would be somewhat more difficult, requiring some GC support to keep the objects aligned when copying them, and requiring that the "slop" be filled in some cases, but it could be done.

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'''Alignment on the stack.''' Aligning the stack could be done either by ensuring that all stack allocation is a multiple of the alignment (thus possibly wasting a lot of stack space), or by adding extra frames to fill the slop when allocating a frame that needs alignment. Neither option is particularly attractive. We propose to use unaligned access to vectors stored on the stack for the time being, and revisit this decision if it is found to be a performance bottleneck later.

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'''Alignment in the heap.''' Again, while we could arrange the correct alignment for vectors stored in heap objects, it would be painful to do so, requiring code generator support and GC support. We propose not to do this, at least for the time being, and to use unaligned loads and stores for vectors in heap objects.

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=== ABI summary ===

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The size of the native-sized vectors `IntVec#`, `DoubleVec#` etc correspond to the maximum size for any sub-architecture, e.g. AVX on x86-64.

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The ordinary `IntVec#`, `Int32Vec4#` etc types correspond to the slow compatible calling convention which passes all vectors on the stack. These vectors must all have their obvious strict alignment. For example `Int32Vec4#` is 16 bytes large and has 16 byte alignment.

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Extra machine-specific types `DoubleSseVec2#`, `FloatAvxVec8#`, `FloatNeonVec4#` etc correspond to the fast calling convention which use the corresponding vector registers. These have the alignment requirements imposed by the hardware. The machine-specific types need not be exposed but it is also plausible to do so.

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We will use worker/wrapper to convert between the common types and the machine-specific types.

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Initially, to avoid implementing vector data-movement instructions in the NCG, we will add arch-conditional inlining of the wrapper functions.

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If later on we add vector data-movement instructions to the NCG, then the arch-conditional inlining of the wrapper functions can be discarded and the compatible calling convention could be changed to make use of any vector registers in the base architecture (e.g. SSE2 on x86-64).

* [wiki:VectorComputing VectorComputing] A previous proposal to make use of x86 SSE in GHC.

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= Current Implementation Status =

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The prototype implementation of the above specification is vailable as the `simd` branch of GHC.

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== General plan ==

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=== Vector types ===

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Vectors of the following types are implemented: `Int32`, `Int64`, `Float`, and `Double`.

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=== Fixed and variable sized vectors ===

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For each type, currently only one vector width is implemented, namely the width that is appropriate for SSE2. This means that vectors are currently all 16 bytes in size.

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== Code generators ==

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Only the LLVM code generator is supported.

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== Cmm layer ==

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Our `CmmType` representation for vectors differs slightly from the proposal. See [source:/compiler/cmm/CmmType.hs?rev=e42746d07239888c74e937046fadf93655b44b65#L42 cmm/CmmType.hs].

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See [source:/compiler/cmm/CmmMachOp.hs?rev=e42746d07239888c74e937046fadf93655b44b65#L106 cmm/CmmMachOp.hs] for the new vector MachOps.

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== Core layer ==

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The implementation differs from the proposal in its naming scheme. We wanted to avoid overloading the term "vector," so, e.g., a 4-wide SIMD vector of `Float#`s is a `FloatX4#`.

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See [source:/compiler/prelude/primops.txt.pp?rev=e42746d07239888c74e937046fadf93655b44b65#L1935 compiler/prelude/primops.txt.pp] for the new primops. Not everything in the proposal is implemented, but we do have a useful subset.

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== Native vector sizes ==

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This is unimplemented. Instead we define a higher-level `Multi` data family whose instance is platform-dependent. For example, a `Multi Int` is represented using an `Int32X4#` on a 32-bit platform, and by a `Int64X2#` on a 64-bit platform.

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== ABIs and calling conventions ==

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Integrating variable-sized vectors with GHC's calling convention is a challenge. How many new registers do we add? Do we add registers for each vector type? The correct approach is unclear, so the current implementation passes all SIMD vectors on the stack.

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=== Memory alignment for vectors ===

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The implementation does not attempt to align memory containing SIMD vectors. SIMD vector loads and stores do not assume alignment.

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Obsolete sub-topics:

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* An [wiki:SIMD/Implementation/Plan implementation plan].

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* Manuel's notes on [wiki:SIMD/Implementation/Llvm implementing SIMD support in GHC using LLVM].

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* An [wiki:SIMD/Implementation/Old old implementation] of the very beginnings of SIMD support in GHC.