Future servers are expected to have huge amount of volatile and nonvolatile main memory that can be directly accessed by the processors.

Managing such a memory hierarchy is a major concern of computer and of hardware security architects.

Thus, while computer architects are aiming at increasing the page and region size, which is being controlled by a single entry at of the TLB (e.g., 1G page size), hardware security architects aims at protecting variable size of regions, starting at few bytes and up to Tera-bytes.

At the first part of my talk, I will focus on software and hardware proposals, starting at segmentation and MPX technologies Intel propose, and up to SW based solutions such as Java and M-system propose.

The second part of my talk will be devoted to capability-based solutions, such as the Cheri project, which was developed by the University of Cambridge, that offers to extend the ISA in order to support variable size memory regions.

I will conclude with an open discussion on the applicability of these technologies to the industry and the open research topics we hope to handle in the near future.