I am assuming that the 24-pin 01-22000-400 IC is functionally identical to the 28-pin JV001 IC except in pin count, and that the difference in pin count is solely due to the JV001 having six input and six output data bits, while the 01-22000-400 has only four input and four output data bits:

The JV001 also has a Mirroring control, using three pins: Input PA10, Input PA11, and Output CIRAM A10. PA10, PA11 are the inputs from the cartridge connector. $4101 D0 selects whether PA10 or PA11 is relayed to the JV001's CIRAM A10 output, effective once $8000-$FFFF is written to:

We know from the Mapper 173 analysis that the 01-22000-400 IC also has a pin that is similarly affected by $4101 D0: Pin 22, so it is most likely the CIRAM A10 equivalent. The question then is which pins are the equivalent input PA10 and PA11 pins. Unfortunately, no known board actually uses that IC for mirroring control, so we cannot observe that directly. But:

On the Mapper 173 board, Pin 22 is connected to CHR A14. To deterministically be a 0 or 1 depending on $4101 D0, the Input PA10 pin must be connected to Vcc, and the Input PA11 pin must be connected to GND (or vice-versa).

On the Mapper 036 board, Pin 22 is not connected to anything, but is reportedly always high but somewhat unstable depending on register values being written. This may be the result of a broken chip, as previously claimed, but I think it's the result of one of the two inputs being connected to Vcc, and the other floating but mostly picking up a high signal.

On Mapper 173, GND is on Pins 8 and 19 and VCC is on Pins 5 and 7. On Mapper 036, VCC is also on Pins 5 and 7, GND is Pin 19, while Pin 8 is not connected. I would suspect then that Pin 7 is Input PA10 and Pin 8 is Input PA11. Which means that if both were connected to GND, then Pin 22 should deterministically go Low after all.

After that, there are still three of the 24 pins with functions to distribute: Pins 4, 6 and 23. Of the JV001's functions, we still have PA13, CHR /OE, and PPU R/W. I'm not sure what the JV001 would need them for, but that's how they are connected on the Mapper 172 board.

Please note that my designations of D0-D5 are from the chip's point of view. Because the Mapper 172 board connects the CPU bits in reverse order, D5 is D0, D4 is D1 and so on, and Mapper 036's CPU D4/D5 are the chip's D0/D1.

The 01-22111-100 PCB has the ASIC wired identically to the 01-22270-000 PCB, the only difference between the two is that the 01-22270-000 PCB has the spot for the 74LS161 while the 01-22111-100 PCB does not.

Comparing the 74LS161 pin functions to the ASIC pin functions as I find them, the 74LS161 at address $8000-$FFFF does exactly the same as the ASIC, only without the $4100-$4103 adder/inverter, which I understand basically as a protection method. I suppose that the 74LS161 configuration is then used for prototypes and development, while the ASIC configuration for production. The 74LS161 configuration would then have its data bits indeed like Mapper 133, but at $8000-$FFFF instead of $4100.

I am assuming that the 24-pin 01-22000-400 IC is functionally identical to the 28-pin JV001 IC except in pin count, and that the difference in pin count is solely due to the JV001 having six input and six output data bits, while the 01-22000-400 has only four input and four output data bits:

But I know that to be untrue?

There are six data bus pins on the 05-00002-010 IC, divided into two functional groups of three.

Pin 24 on the 05-00002-010 is unequivocally carry-out from the bits latched into pins 12-10 and exported on pins 3-1.

Quote:

On the Mapper 036 board, Pin 22 is not connected to anything, but is reportedly always high but somewhat unstable depending on register values being written. This may be the result of a broken chip, as previously claimed, but I think it's the result of one of the two inputs being connected to Vcc, and the other floating but mostly picking up a high signal.

I mean, it unequivocally can switch between two different amounts of current sourced when pulling up. I don't see an obvious way for that to happen short that either being deliberately designed in (but I have no idea why), or damage to the IC.

Pin 24 on the 05-00002-010 is unequivocally carry-out from the bits latched into pins 12-10 and exported on pins 3-1.

That's what I said: Input bit 0 (pin 12), Input bit 1(pin 11) and Input bit 2 (pin 10) relayed to Output bit 0 (3), Output bit 1 (2) and Output bit 2 (1), and Input bit 3 (9) relayed to Output bit 3 (24). But have you checked, or are you just assuming based on what looks like functional groups, that a fifth and sixth bit are indeed directly relayed as well? Right now, the Mapper 036 article says that if Pin 22 weren't defective, you assume it would relay some other pin, but that's just conjecture and directly contradicted by Mapper 173's connection.Edit: No, actually it doesn't say that. It says that Pin 22 is always defective, and Pins 23 and 24 relay something else, although I am note quite sure what.

lidnariq wrote:

I mean, it unequivocally can switch between two different amounts of current sourced when pulling up.

With the inputs that two other pins have, yes. What I am proposing is that if certain other pins (possibly 7 and 8, but I am not sure about that yet) were not connected as they are on the Mapper 36 board, but as they are e.g. on the Mapper 173 board, things would be different, and you would observe normal high and low states.

Last edited by NewRisingSun on Thu Mar 01, 2018 2:07 pm, edited 1 time in total.

I am confident that pin 9 is not relayed to pin 24, even though this contradicts what you've found on other ICs with the same marking.

Quote:

or are you just assuming based on what looks like functional groups, that a fifth and sixth bit are indeed directly relayed as well?

Pin 6 was definitely relayed to pin 23.

Pin 6, 8, and 9 in that order obeyed increment behavior when set to increment mode and reading back from the register inside, separate from pins 12, 11, and 10 in that order.

I'd want a less cranky test system than my current hot-swappable thing if I'm going to do more testing.

Quote:

What I am proposing is that if certain other pins (possibly 7 and 8, but I am not sure yet) were not connected as they are on the Mapper 36 board, but as they are e.g. on the Mapper 173 board, things would be different, and you would observe normal high and low states.

No, don't desolder anything just for me. The original question was what the 74LS161 spot was for, and that was answered thanks to MLX' testing, so let's leave it at that for now.

I think the current pinout should be rewritten though to clearly state which pin is relayed to which, instead of how the pins are connected on that particular board, as the current description is giving me a headache.

Ah, now it's becoming clear that 6, 8 and 9 are connected in reverse order from 10, 11 and 12. Now the increment can work on both triples without breaking the Mapper 173 games. The $4101 part still needs to be added to the Mapper 036 page (or better yet, the IC's page). Was it that Invert is applied to the 10/11/12 tuple when writing to $4100 and Mode=0, and to the 6/8/9 tuple when reading from $4100?

Unfortunately, that will not work with Puzzle, which writes $01 to $4101 yet expects all bits to be inverted. That, and the mystery pin 22 still need to be investigated, and since all Mapper 173 games explicitly vary their $4101 value between 00 and FF to select CHR A14, which is connected to Pin 22, the two must *somehow* be connected, possibly with the help of another pin.

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