Intel has high-volume production of its 22 nm Tri-Gate products, and its feature dimensions do not require double patterning. The second-generation Haswell 22 nm processor is also demonstrating high performance as well as long battery lifetime.

The next logical technology node is 20 nm HKMG, and TSMC is projecting 20 nm will represent 10% of its 2014 revenues ($2.2 billion to $2.3 billion) and 20% of its fourth-quarter revenues ($1.10 billion to $1.15 billion). With the capacity of 60,000 wafers per month (WPM), the average price for 20 nm wafers in the fourth quarter at $1.1 billion will be around $6,000. This is a relatively large increase in pricing compared with 28 nm wafers, which sell at $4,500.00 to $5,000.00. If TSMC achieves its projection for 20 nm, the company will have 95% of the 20 nm foundry market in the fourth quarter 2014.

There are, however, challenges in controlling leakage and gaining high yields of application processors and modems that require low leakage. If 20 nm does not provide low leakage with cost penalties compared to 28 nm, an alternate option is 28 nm FD-SOI. The wafer cost of 28 nm FD-SOI is comparable to 28 nm bulk CMOS, with performance potentially being 15% superior to 20 nm bulk CMOS.

Consequently, Samsung Electronics has a major opportunity with its large wafer capacity to support low-leakage products with its 28 nm FD-SOI process. Cadence Design Systems, Synopsys, and Mentor Graphics are all supporting the FD-SOI ecosystem, and the transition from 28 nm bulk HKMG to FD-SOI should be inexpensive.

16/14 nm 3D technology status
Intel, TSMC, Samsung, and Globalfoundries are trying to ramp their 3D structures. Intel planned to have the initial volume production of its 14 nm Tri-Gate structure in the fourth quarter of 2013, but low yields postponed this ramp-up.

A number of fabless companies will tape out their 16/14 FinFET product designs in the third quarter of 2014 with high-volume production planned for the second or third quarter of 2015.

Tens of billions of dollars are being committed by the semiconductor industry to have volume production of FinFETs in the next 12 to 18 months. What is the probability of this happening? And is the next-generation FD-SOI (called 14 nm by STMicroelectronics) a better option for mobile applications, which are the key driver for high-volume wafers?

The cost to manufacture a 16/14 nm FinFET wafer is approximately $4,000 at the high-volume stage, and with a gross profit margin of 45%, the selling price is around $7,270. The key issue is whether high systemic and parametric yields can be obtained from the initial designs. Based on an assessment of many variables, the probability of this occurring is very low.

FinFETs will happen, but there will be a learning process, and multiple design interactions will need to occur.

With this scenario, Samsung's adoption of FD-SOI and implementation of shrinkages are very astute decisions. If its 14 nm FinFETs ramp up as expected, Samsung's competitive position will be very strong, and if there is a delay in this ramp-up, Samsung has an alternate solution.

1) I do not disagree that the floating body effect affects the transistor characteristics. What I'm saying is that the effect is well known and high performance circuits have been built for over a decade. FYI, IBM's system-z is using SOI and those are bleeding edge performance. The latest was shown at ISSCC 2013, nearly 600mm2 large chip clocking at 5.5GHz. If you think that's not high performance, I have nothing more to say. Floating body effect, self-heat, and whatever "nasty" characteristics you would like to attribute to the PDSOI are there, and yet the whole circuit delivers the performance that is expected.

Scribe line transistors (and other test structures) are characterized to monitor the process. Nobody sells them! So I don't care what type of performance I get in those. As long as I know how they correlate with the overal circuit performance, they serve their purpose.

2) A platform technology is more than a single transistor I-V. It's about all pieces here and there that make it possible to put billions of transistors next to each other. IEDM is about all those pieces not an I-V (that in some cases was not consistnet with the rest of the charts!).

3) Technology name (22nm/28nm etc) is just a label. Look more closely at the papers you read and talks you attend, and you figure they have nothing to do with the gate length. And yes, Intel's gate length was 30nm for lowest Vt and 35nm for higher Vt device.

4) You can have doubts and TSMC has their own reasons. They choose to do FinFET for whatever reason and then ended up postponing it. It's not an easy path and the performance advantage that everyone is claiming is not easy to get. Their plan to do 16FF+ to get more performance is just an indication that 16FF was not competetive, despite what they thought at the beginning.

5) I stand by my earlier comment that at the system level, performnace is not about a single transistor I-V. It's about how many different transistors (SLVT, LVT, RVT, HVT, etc) you have and what kind of Vt range they cover. TSMC rightfully emphasize on this fact in their 28HPM paper. when looking at an Ion-Ioff characteristics this is the information one should be interested to see, the range of Ion and Ioff available and not neccessarily the on current at a given Ioff. A big circuit uses a mixture of transistors withe a range of Vt and it's alway good to have a wider range. Ironically, FinFET has a steeper Ion-Ioff characterstics than a planar device. This means that the abilty to crank up the performance by using a lower Vt device is reduced. Similarily, the ability to increase performance by increasing Vdd when needed is reduced and the ability to drop the leakage by using a longer gate length is reduced.

6) For the record, calling a bulk FinFET is incorrect. Fully depeleted is only meaningful when refering to SOI (as opposed to PDSOI) and does not bear any meaning about the thickness of the device, doped vs undoped channel, etc. Using it to refer to bulk FinFET is a misnomer!

7) In strong inversion, the thickness of the inversion layer is about 3nm in any Si device. That means for anything thicker than this you won't see the effect of the channel thickness. 14nm FDSOI is using 5nm channel thickness with Si for NFET and SiGe channel for PFET. Please read the VLSI'14 paper. The thickness uniformity is not an issue. You start from the same wafer used for 28FDSOI and just oxidize 2nm of Si. If you think thermal oxidation cannot be controlled withing 1A uniformity consult a gate module owner at any company.

8) Enough have said about the performance. NFET PDSOI delivered 1.65mA/um at 100nA/um off current at 1V back in 2012. That's absolute highest performance in any Si NFET. PFET is about 1.4mA/um, again among the highest I've seen.

1) I agree, PDSOI shows floating body effect which results in history effect in circuits, but this is known for almost two decades and circuits designers know how to handle it. Design of multiple generations of IBM servers and AMD/Freescale/Sony, etc is a estimony that circuits with competetive performance can be made. We can sit here and talk about physics as long as we want, but when there is a chip that runs and delivers the performance, all the discussions about a single transistors I-V are moot. Same applies to the self-heating effect. It is known that when a transistor runs a DC current drive current is about 5% lower because of self-heating. But that condition almost never happens in real circuits except for a few analog transistors. Everything else has an activity factor of 1% or less and self-heating is not an issue.

2) FYI, I have attended IEDM, ISSCC, VLSI, etc and presented in all of them. I think I am well aware of what is being presented at these conferences somethimes well before the conference. For a platform technology, 20nm does not mean anything anymore. It's just a name and has nothing to do with the gate length. When Intel submitted their 22nm paper to VLSI'2012, the minimum gate length from TEM was said to be 30nm. At the conference they showed exact same TEM and called it a 26nm gate length. None of them of course have anything to do with the technology node. When I asked the author about the differences (submission vs presentation) he said one is the physical and one is electrical. His manager however said they had multiple versions of the technology and they just made it shorter. Don't take me wrong, I admire Intel's engineering team and know many of them personally. They did a great job putting the technology together, but that doesn't mean I will not speak up if I do not agree technocally with what they claim.

3) 28FDSOI is being manufactured in Crolles and will be in production in Samsung next year. Circuit level perfrmance have already been demonstrated and that's why it's put in Samsung. If it does not deliver higher performance than 28nm bulk or delivers same performance at a reduced cost, why would any foundry in their right mind want to run wafers? Whay would customers want to spend millions of dollars to design? Again, you and me can talk long about 5nm/7nm, 12" wafers, etc, but circuit designers don't care about any of those. A transistor is a 4 terminal device with a certain I-V and C-V charactersitics for them. At system level, even a single transistor I-V is not important. You care about range of Vt that is available, uniformity across chip and from chip to chip, and the circuit tricks you can play. Body biasing is the strength of FDSOI, that allows you to compensate for variations that you inevetibly have in in any process and adjust the performance for the work load. That option is not available in FinFET. So, yes you get a single transistor with probably higher current with FinFET, but what a circuit designer cares about is the whole device menu and not a single I-V.

4) For 28nm FDSOI the final channel thickness is 7nm, with the starting thickness of 12nm from SOITEC/SEH/SunEdison. The spec is +-5A across wafer and from wafer to wafer and as far as I know all three suppliers do better than that. For 14nm FDSOI (I personally don't agree with the naming, but it has the same gate pitch and metal pitch as 14/16nm FinFET) channel thickness is 6nm and same uniformity spec. You tell me that I cannot start with the same wafer and thermally oxidize 1nm of Si with perfect uniformity? FYI, that was the process used to form the gate oxide before high-k and still is one of the best controlled processes.

5) I think I have measured enough transistors in my life to know if 7nm is scary point or not. If you read publications on mobity in very thin Si, peak mobility drops from ~440 cm2/V.s to maybe 420 at 4nm Tsi. In the presence of high-k peak mobility is less than 200 cm2/V.s. Should the whole industry give up on high-k just because it degrades mobility? At the end of the day what matters is that whether a 7nm or 5nm channel thickness delivers a compeptitive drive current or not. And I think there has been enough publications in the past few years to prove it's doable.

I am a device engineer and for me a good device is a good device, no matter who builds it. FinFET has it's strengths and weakness. Same is bulk planar, FDSOI, or PDSOI. But when looking at a given technology I trust Si data (once confirmed and is consistent across many measurements). The industry does not go anywhere with handwaving arguements based on limited inofrmation and incorrect assumptions.

I am afraid you have mixed up many things. PDSOI has been in production at IBM down to 22nm. It has served IBM and other companies (AMD, Freescale, Sony, Nintendo, and Microsoft to name a few) for several generatios. So, unlike what you claim it is actually scalable. Even "the one time thing" long channel devices (180nm node) are being manufactured at a handful of foundries and are powering RF parts of nearly 50% of cell phones!

Samsung reported their 20nm bulk planar at IEDM 2011 (6 months before Intel's 22nm) and at smaller gate length, gate pitch (80nm vs 90nm) and metal pitch (64nm vs 80nm). Contrary to what you say, leakage was ok, down to 1nA/um for nominal gate length. TSMC also developed their 20nm node, and although they did not report device performance in public, customers like Qualcomm have already announced their product shipment plan. So, yes bulk planar is also scalable.

I cannot speak for ST or Samsung, but what I have seen in their announcement is that they are commited in offering 28FDSOI as a foundry service and that is happening even if you are not convinced.

With all respect, I would suggest that you through away anything you have heard about device physics, mobilit, etc and start afresh. There is no mobility degradation due to the prsence of back oxide interface. Quantum effects are not a monster to be afraid of. They are in play in any device and people have been accounting for those for many years. Those publications that reported mobility degradation in thin channel FDSOI only showed a modets 10-15% degradation in peak mobility down to any channel thickness of interest. Still those mobility numbers are almost 3X higher than typical numbers you get in the prsennce of high-k! So, the back interface is not a concern, certainly not at 5-7nm that is used in any FDSOI technology.

The "end of roadmap" and technology scaling has nothing to do with the gate length. A 3nm node does not have a 3nm gate length, the same way that Intel's 22nm has a gate length of 35nm. All you need for the gate length is that it fits the gate pitch. That's why practically it has been not scaled since 65nm node. At some point you need to start scaling the gate length but cerytainly no one in right mind would go less than about 15nm. After that there are several possibilities. One is monolithic stacking of 2 or more transistor layers. The other is to use vertical channel devices to decouple gate length from gate pitch. Both of these have been practiced in NAND flash and there is no reason they cannot be used in logic. Although logic does not enjoy the uniform layout that memory has. So there is no technology limitation that you want to solve with a FinFET that is "scalable to the end of roadmap". It all boils down to whether you can do any of these cost effectively. The major problem in advanced nodes is not the choice of transistor, it's how to make three contacts to each transistor. At 10nm you need 8 mask levels just to get from the transistor to M1 (which is another 3 masks to print). How does the choice of FinFET vs FDSOI affect this esclataing cost?

IBM's 22nm which is used for power8 is PDSOI, which is very similar to bulk planar in terms of scaling and in fact uses a gate length shorter than Intel's 22nm FinFET. Samsung and others made 20nm bulk planar and showed their results. ISDA's 20nm was shown in at VLSI 2012. TSMC is said to ship 20nm parts this year. The problem with 20nm was not scalability, it was cost. For your information foundry's 20nm uses 64nm metal pitch vs Intel's 80nm. Which means foundry is offering a denser technology, which of course comes at the cost of double patterning.
FDSOI products have already made by ST, see for example NovaThor demo in early 2013 that clearly showed SOC benefit. Samsung is now committed to offer 28FDSOI to the public.
I do not understand your repeated comment about 28nm bulk planar being in high volume for several years as a drawback of FDSOI. Yes, 28nm has been in production for several years, but it didn't come with all bells and whistles at the beginning. The first products used poly SiON gate stack and no strain element to keep cost down. Overtime several versions of the technology with different cost-performance trade offs were offered. They are put into volume manufacturing when fabless companies demand a certain performance and are willing to pay for that extra cost. 28FDSOI is no exception to this. Volume manufacturing was put on hold because customers did not demand.
BTW, Intel's 14nm FinFET is not in manufacturing yet and there has been multiple delays. And there is no such thing as "end of roadmap". Technology is scaled as long as it makes financially sense to do so. Whether it's being conventional scaling of the transistor, being stacking in 3D, or a completely new technology the same way BJT was replaced by MOSFET logic.

No, the doping is not uniform in bulk planar! The well is retrograde (although not ideal) and there are halos. The whole point is that the well and halo doping will take care of leakage at the depth and gate takes care of it at the surface. I agree with you that the ideal supersteep retrograde will end up with high drain leakage, but that's not the case in FDSOI because drain is isolated from the substrate by the BOX.

BTW, your point about Vt being higher and more variable in a retrograde well is not correct either. In fact it's the other way around! Please see page 230 of Taur and Ning's text book. With retrograde well design Vt is lower than a uniformly doped well and in the extreme case independent of the well doping. This is in fact what SuVolta is promoting. Of course, with Vt being independent of the well doping you cannot use Vt adjust anymore and need to rely on body bias. What FDSOI does is simply making an ideal retrograde well possible and allowing the well doping to have either n+ or p+ polarity for either NFET or PFET witout fearing about drain leakage.