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AR# 5197

Description

Keywords: RAM, Quicksim, Mentor, simulation

Urgency: Standard

General Description:

Doing a Functional or Timing simulation of a RAM using Mentor Quicksim II,the RAM comes up in a known state, but none of my write operationsappear to be written into the RAM module. Doing a Read on the RAMshows the contents to be the same as what it powered up as.

Solution

Possible solutions:

1) Toggle the //globalsetreset signal at the beginning of the simulation.

2) If it is a timing simulation and the RAM is not coming up in the userdefined initial state (INIT property on RAM), make sure that pld_dve is run after running pld_edif2tim. Doing this will add the INIT property asan INSTANCE property for the RAM initialization in the design viewpoint.