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Disclosed is a method for surface
plane metallization capacitor land design for reduced loop inductance. Benefits include improved performance.

Background

The frequency of
operation of a processor is set by the lower limit of the voltage in the
voltage tolerance window. When the voltage tolerance window around the nominal
operating voltage is smaller, the VCC and the frequency of operation
are higher.

To minimize the
voltage tolerance window, capacitance must be added between the VCC
and VSS power planes in the package. A metal encapsulated capacitor
structure provides a way of reducing the loop inductance (L) of a capacitor by
increasing the interaction between the VCC (Power) and VSS
(Ground) connections.

Capacitor inductance
must be increased when it is mounted to the package.

The conventional substrate design defines exposed surface metal
to establish a local connection between the passive component (capacitor)
terminals and substrate pads. Solder paste is typically placed on substrate
pads and then reflowed to connect to component terminals (see Figure 1).

Conventionally,
terminals are confined to the edge of the capacitor. A plane is located directly below the capacitor with a layer of solder
resist between them. The solder resist material increases the spacing between
the bottom most capacitor internal metal plates and reference planes of the
substrate. This increased spacing leads to a increased effective series
inductance (ESL). The distance, d, includes the z-height of the backing
material and the z-height of the solder mask above the package. The ESL of a
capacitor is a strong function of this distance, which means that the capacitor
can respond faster to a di/dt current transient (see Figure 2).

The increased ESL
makes the conventional solution very unattractive for high-speed designs, where
CPU demands current at a much faster rate. The allowed voltage tolerance window
at the die is also very small.

General description

The disclosed method is a capacitor pad that accommodates
surface plane metallization under the shadow of the capacitor.

The disclosed method
provides an alternative arrangement of connecting a capacitor through a
low-inductance path of the power delivery network of a die through the package
substrate. The method greatly reduces the noise that affects the die,
increasing its maximum frequency capability.

The decoupling
capacitor inductance is dominated by pad layout. Providing a low inductance
power delivery path between the capacitor and the die is imperative to
supporting high-current transients for high-frequency operation.

A uniquely shaped
capacitor terminal increases the interaction between the VCC and VSS
terminal connections, lowering the inductance between the capacitor and the
die. Additionally, the disclosed method
reflects assembly capability requirements to apply required metallizat...