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Lisa Su, senior vice president and general manager at Freescale Semiconductors, needs some help from the EDA community. In a dynamic keynote speech at the Design Automation Conference June 7, she set forth a list of hardware and software design tool requirements for the oncoming generation of multi-core, mobile, connected embedded devices.

Su began her speech by pointing to an ongoing shift from a "compute centric" world to an embedded world. We've already gone from mainframes to PCs to mobile devices. What's coming up next, she said, is an "Internet of everything" that encompasses health care, safety, energy conservation, transportation, cloud computing, and much more. This new trend will "drive more growth in the semiconductor industry during the next five years than we've seen during the last five years," she said.

Here are a few data points. From 2010 to 2015, Su said, mobile Internet traffic will double every year. By 2015, there will be over 7 billion connected devices in the world. There will be an incredible variety of embedded devices, from large to small - Su, in fact, talked about some of the embedded electronics that will become available in automobiles, like collision avoidance. But all of these embedded systems will have similar concerns - performance, cost, and low power.

The Multi-Core Revolution

Multi-core architectures represent the most significant innovation within the past five years in the embedded world, Su said. It's evolving very rapidly but is posing a lot of challenges. "It's very easy to put 100 cores on a chip and very difficult to get the performance capability out of it," she said. "We're trying to balance system needs and get the optimal power and performance. We're spending a substantial amount of time on the software side." (The slide behind her said that 70% of a multi-core project cost is software).

Su identified three "integration options," all of which are used at Freescale. The simplest is a single processor with hardware accelerators. The second is homogeneous multi-core, commonly used today in compute platforms. The most flexible - and most complex to design - is heterogeneous multi-core, with different types of processors. What she sees down the road are systems with "lots of cores, a multi-core fabric, and very application-specific accelerators developed for each market segment."

The number of cores will go up rapidly, she said, increasing transistor count at a rate faster than Moore's Law. At the same time, there are "very high levels of quality expectations out there," especially for safety-critical applications like automotive electronics. It all adds up to a very challenging design environment.

How EDA Can Help

Freescale is doing much of its design today at the 32/28nm nodes, Su said. "There is tremendous improvement in tools, but there are still a number of challenges, particularly where we have very large SoCs." She noted that "stitching it all together is still our job. We'd like it to be somebody else's job to help us stitch it together."

Su identified some specific EDA needs, as follows:

The ability to complete verification runs in less than 12 hours (allowing better information sharing between globally-dispersed teams).

Better power analysis. Present capabilities are "still fairly simplistic relative to the complexity of the design."

Low-power technologies that correlate with silicon.

An "end to end" solution for system integration.

Reliability analysis. This is handled today with margins, but "we need to be a lot smarter."

"The single biggest thing my engineers ask for," Su added, "is more efficiency in how we run simulation cycles. We need a 3-4X improvement. " She also said Freescale is relying more and more on external IP and is looking not just for hardware IP but APIs and drivers "so we can just drop it into the system."

Su noted, however, that "software is the biggest single challenge we have, and the reason is that we're not that good at it." She noted that "our customers expect us to deliver software at the same time we deliver hardware. Gone are the days when we sample the chip and they figure out what to do."

Su identified several areas of challenge around multi-core software development:

System partitioning - challenges include mapping multiple applications to one processor, and migrating single-core code to multi-core without re-writing.

Software programming model - it must be easy to understand, but multi-core requires complex system interactions. A software abstraction layer is needed.

Application consolidation and disparate operating systems. When there are mixed OSes, the application developers want to abstract this complexity

System-level visibility and debugging. Visibility into all aspects of the embedded system is critical.

"Hardware/software codesign? Yes, please help us," Su said. "The key point is that software design starts at the same time as hardware design." She said that today's virtual prototypes are "pretty good" but that there's still a need for "cycle-accurate simulation to debug real-world use cases." Engineers are still finding use-case problems on silicon, she noted.

In conclusion, Su called on the EDA community to "scale up" (faster tools) and "scale out" (more complete solutions). "End to end system development improvements are needed," she said. "There are a lot of opportunities here."

Observation: As the EDA360 vision paper notes, semiconductor companies need help producing systems that include both hardware and embedded software. "End-to-end" system development flows are exactly what's needed. Listening to Lisa Su's talk, I see now that the multi-core revolution is going to put even more pressure on the EDA industry to "scale out" to a more expansive vision.