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Abstract

Multichip packaging is used for high-packing densities of chips that are subject to relatively high-power dissipation. This type of packaging provides for a satisfactory thermal coupling of the chips to the cooling medium.

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United States

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English (United States)

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Multichip Packaging

Multichip packaging is used for high-packing densities of chips that are
subject to relatively high-power dissipation. This type of packaging provides for a
satisfactory thermal coupling of the chips to the cooling medium.

To ensure a good thermal conductivity, chips 1 are connected on their rear
sides, via a eutectic gold silicon alloy 2, to substrate 3. Substrate 3 serves to
discharge the heat produced as a result of the power dissipation and to make the
package mechanically stable. Electrical connecting pins 4 pass through substrate
3 and are secured thereto.

The contact pads 5 on the top side of chips 1 are linked with multilayer
substrate 6. Substrate 6 is designed to meet the requirements of low-capacity
lines, since it is not used to cool the package nor to make it mechanically stable.
Materials have approximately identical thermal expansion coefficients are
employed for substrate 3 and multilayer substrate 6, to prevent the electrical
connections to chips 1 from being unduly loaded.