Dear ralf,
> Most systems define MIPS_CPU_IRQ_BASE as 0 so be careful that your
> set_irq_chip_and_handler loop doesn't overwrite any previous setup by
> mips_cpu_irq_init. If your interrupt controller has 32 interrupts you
> probably want to assign interrupts 0..7 to the CPU interrupts and 8..39
> to the other controller.
thanks for the tips, I take a mistake that it could not be overwrite
Would like your help on my following question, thanks
1, I found that some CPU(e.g. ar7) does not request_irq on TC0_IRQ, do
not deal with the timer interrupt, and do not call function
do_timer(1).
2, But I must request a IRQ to deal with TC0_IRQ and call do_timer(1)
&& update_process_times, (this is porting from vendor released code)
3, How the AR7(or other MIPS SOC) deal with timer interrupt and update
the jiffies ?
thanks
Arrow