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Description

The Virtex-5 DDR/DDR2 SDRAM designs have specific requirements on the user interface signals during initialization and calibration. The testbench module included in the "withtb" design follows these requirements on the user interface signals. However, when the testbench module is removed ("withouttb" design) and the design is connected to the user application, these requirements have to be manually followed.

Solution

The write data FIFO within the MIG-generated design is used for storing either the data pattern used during calibration or the write data used during normal operation. The data pattern for the calibration is written into the FIFO by the initialization state machine during calibration. In order to reduce resources and help with timing, the FIFO input is driven by the logical OR of the user write data and the data patterns.

Consequently, user interface signals need to be held Low to allow the correct calibration pattern to be written into the FIFO. After the calibration, all the signals from the calibration state machine are held Low to allow the user interface values to be written into the FIFO correctly.

The user interface signals that have to be held Low are shown below (shown from the u_ddr/ddr2_top_0.v module level). These signals should all be held Low until the calibration and initialization is complete (assertion of phy_init_done).

input app_af_wren, -- held low until phy_init_done is asserted input app_wdf_wren, -- held low until phy_init_done is asserted input [(2*DQS_WIDTH*DQ_PER_DQS)-1:0] app_wdf_data, -- held low until phy_init_done is asserted input [((2*DQS_WIDTH*DQ_PER_DQS)/8)-1:0] app_wdf_mask_data, -- held low until phy_init_done is asserted

output phy_init_done, -- signal will be asserted once initialization is completed

NOTE: Holding these signals Low is no longer required starting with MIG v2.0