TSMC starts FinFETs in 2013, tries EUV at 10 nm

Much of this year’s growth comes in the 28nm node. Just a year ago, Qualcomm’s chief executive Paul Jacobs was telling his investors the company could sell more of the advanced chips than it could make at TSMC and was searching for capacity elsewhere.

In June 2010, TSMC broke ground on a so-called Gigafab 15 site in Taichung, Taiwan, it planned as its manufacturing center for 28-nm chips. By April 2012, just 22 months later, it started production in half the planned facility -- a record for the Taiwan foundry.

Within eight months it was kicking out 50,000 28-nm wafers a month -- another record -- but it still wasn’t enough. So, next month the second half of the facility is set to produce its first wafers and within five months is expected to beat the old record and add another 50,000 28-nm wafers/month. “The scale is difficult to appreciate,” said Chang.

The “unprecedented ramp of 28-nm chips came with an acceleration in time to good yields and volume production," said J.K Wang who oversees TSMC’s 300-mm fabs. The foundry expects to see even faster ramps at 20 and 16 nm, so it has several thousand engineers preparing for those nodes at its fab 12 and 14 facilities today.

TSMC now starts three new fabs each year.

“In the past, we built one phase of a new fab each a year, now we typically initiate three phases a year,” said Wang.

The foundry estimates it makes 1.3 million logic wafers per month total now, far ahead of Samsung in second place at about 900,000 logic wafers/month. It estimates it will produce a whopping 13.5 million wafers/month in 2017 if it continues its growth.

"Even if EUV hits its targets, the 10nm node also requires use of self-aligning techniques with immersion lithography to minimize the need for EUV to just some critical layers. TSMC also is developing a so-called G-rule that automates the tricky process of handling color conflicts in double patterning."
It would be implied that no EUV layers would be best otherwise why all the trouble with the double patterning.

God also gave electrons mean free paths, so I doubt EUV or E-beam are the intended windows for lithography.
http://www.google.com.tw/imgres?imgurl=http://www.virginia.edu/ep/SurfaceScience/mfp-luth.GIF&imgrefurl=http://www.virginia.edu/ep/SurfaceScience/diffract.html&h=1306&w=1760&sz=44&tbnid=QKsyadnm5B9OOM:&tbnh=92&tbnw=124&prev=/search%3Fq%3Delectron%2Bmean%2Bfree%2Bpath%26tbm%3Disch%26tbo%3Du&zoom=1&q=electron+mean+free+path&usg=__bB9cU--iCG-n29qsTr83sRrdjcg=&docid=jwiPBTm96sPScM&sa=X&ei=RRuFUdKrEM2jkQXxsYH4Cg&ved=0CDsQ9QEwAw&dur=156

Burn Lin should have retired as the Holy Father of Immersion, basically saving an industry which made another obviously foolish bet on X-ray lithography (oh, sorry: EUV lithography) and while saving us from a 157nm black hole. The trouble with such success is it can breed hubris. Lin's E-beam direct write has had a similar history to X-ray. The end of optical seems around the corner, billions are spent on alternatives, all fail; now, the end of optical seems even closer, so the failures are renamed (EUV and maskless), more resources are wasted, but Mother Nature doesn't pay attention to marketing-created name-changes. Refocusing from X-ray to EBDW means instead of the overwhelming challenges of source, resist, and mask/blank, we have the overwhelming challenges of source, resist, throughput, and data path.

Who does direct write?
ASML bought SVG and ASML killed it.
Direct write goes back to Eaton?
SUMMARY OF THE INVENTION
An object of the present invention is to provide an improved electron beam lithography method for creating an exposure pattern having unprecedented resolution in an electron sensitive surface.
This is accomplished in accordance with this invention by patternwise treating an electron sensitive surface to a high resolution pattern of low-energy electrons rather than high-energy electrons.
.......
When the separation between the pointed electrode and the surface being treated is less than about 1 nm, the electron clouds of the atoms at the apex of the pointed electrode and at the surface opposite the apex touch, and a tunnel current path is established between the apex of the pointed electrode and the surface. When the separation is more than about 3 nm, electrons must leave the pointed source via field emission. When the separation is between about 1 and 3 nm, both current effects are experienced. In any case, the area of the surface receiving the electrons has a diameter roughly equal to the distance between the point source of the electrons and the target surface.