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This is a rather unexpected, even apparently self-contradictory, choice. But the expectation is set by the assumptions.

It might be related to the difference of available immersion tools. Some immersion tools have the maximum numerical aperture (NA) of 1.35, while others have a lower NA of 1.2. The 40 nm resolution is achievable with the 1.35 NA, achieving a k1 of (40)*(1.35)/193 = 0.28, which is just above the fundamental limit of k1=0.25. This is what was used for Intel's 22nm. On the other hand, the same 40 nm is not achievable with 1.2 NA, since k1 = (40)*(1.2)/193 < 0.25. If there are not enough 1.35 NA tools to use for Intel's 10nm, they have to reuse the 1.2 NA tools with quadruple patterning (starting from 80 nm half-pitch) instead of double patterning (starting from 40 nm half-pitch).

Restricting to 1.2 NA tools would also increase the number of via or cut or block masks compared to 1.35 NA. Two vias or cuts 80 nm apart must use different masks on 1.2 NA but can be squeezed onto one mask with care on 1.35 NA.

This is a rather unexpected, even apparently self-contradictory, choice. But the expectation is set by the assumptions.

It might be related to the difference of available immersion tools. Some immersion tools have the maximum numerical aperture (NA) of 1.35, while others have a lower NA of 1.2. The 40 nm resolution is achievable with the 1.35 NA, achieving a k1 of (40)*(1.35)/193 = 0.28, which is just above the fundamental limit of k1=0.25. This is what was used for Intel's 22nm. On the other hand, the same 40 nm is not achievable with 1.2 NA, since k1 = (40)*(1.2)/193 < 0.25. If there are not enough 1.35 NA tools to use for Intel's 10nm, they have to reuse the 1.2 NA tools with quadruple patterning (starting from 80 nm half-pitch) instead of double patterning (starting from 40 nm half-pitch).

Restricting to 1.2 NA tools would also increase the number of via or cut or block masks compared to 1.35 NA. Two vias or cuts 80 nm apart must use different masks on 1.2 NA but can be squeezed onto one mask with care on 1.35 NA.

Do you have a paper on Intel 14nm for comparison? It would be interesting to see how Intel stepped from 22nm to 14nm to 10nm?

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Historically, the 1.2NA tool was targeted for 45 nm node. I suppose at the time Intel was more aggressive in purchasing those tools to stay ahead at 45 nm, even though in the end not using them for 45 nm. So they may have a larger share of those tools. Still, they also purchased many 1.35NA tools as well. It's a little hard to believe the 1.35NA capacity ran out. But possibly the other players like TSMC or Samsung could have the advantage to buy relatively more 1.35NA tools, which were available shortly after 45 nm.

Intel's 10nm process has a 36nm M1 pitch done with SAQP. My guess is they also use SAQP for M0 even though the pitch is 40nm to match some design rules, it likely has nothing to do with the pitch when they could clearly do SADP.

Assuming they have enough 1.35NA tools now, would they now move M0 to SADP?

I don't think it has anything to do with availability of 1.35NA tools, M0 and M1 are tightly coupled for routing and I think they need M0 to be SAQP for design rule reasons. I don't for a moment believe Intel doesn't have enough 1.35NA tools available. It is also possible there is something about the way it is laid out or steps heights or whatever that drives the need for SAQP.

I'd be intrigued if there was some new consideration to use SAQP other than pitch resolution. But if the final line pitch after SAQP is 36 or 40 nm, then they could probably be using dry ArF rather than their high-end immersion tools for 144 or 160 nm pitch.

I'd be intrigued if there was some new consideration to use SAQP other than pitch resolution. But if the final line pitch after SAQP is 36 or 40 nm, then they could probably be using dry ArF rather than their high-end immersion tools for 144 or 160 nm pitch.

I just looked over the IITC 2018 paper by Intel (reference below) where they described their BEOL SAQP and process. Though they did not give away all the details, if I understand the hints correctly, the M0 layout required a special process integration sequence for the line cutting arrangement, due to lots of skip-line cuts. SADP would have used thinner photoresist which probably couldn't support this process integration sequence. Just a guess.

I'd be intrigued if there was some new consideration to use SAQP other than pitch resolution. But if the final line pitch after SAQP is 36 or 40 nm, then they could probably be using dry ArF rather than their high-end immersion tools for 144 or 160 nm pitch.