AMD, HP propose extensions for PCI Express 3.0

SAN JOSE, Calif.  Researchers from Advanced Micro Devices and Hewlett-Packard have written two extensions to the PCI Express 3.0 specification which aim to enable lower cost chips that could support multiple protocols and reduce processor overhead. They hope to get the extensions accepted as part of the draft PCIe 3.0 spec slated for publication early next year.

The two extensions are independent of each other and have applications in graphics, high-speed I/O and embedded systems. Both require some changes to silicon and software.

A so-called protocol multiplexing extension would let chips dynamically switch between as many as seven different protocols in addition to PCIe using a shared set of chip pins, buffers and board traces. Resulting chips could use fewer pins, and OEMs would need fewer devices and could make more flexible systems.

Using the technique, for example, chip makers could design a single part that connects processors and accelerators via PCIe, Intel's Quick Path Interconnect or the coherent HyperTransport bus.

"This will enable hybrid computing to take off because a graphics chip could act like a host processor, and you could much more easily offload jobs from a CPU to a GPU or accelerator," said Michael Krause, an I/O specialist at HP.

"In the embedded space, some packets could be for example Ethernet and others PCIe to separate control and data planes in communications systems," he added.

A separate extension—called lightweight notification--would allow co-processors or peripheral chips to talk to each other through system memory using a PCIe transaction without interrupting a host processor. For example, an Ethernet switch could respond to commands to encrypt and decrypt specific data packets while a host processor is inactive.

Both extensions are aimed at addressing the rising need for I/O subsystems and accelerators to support dozens of functions in systems that are increasingly using multicore processors and virtual machines. Both extensions are designed for use with the 2.5, 5 and 8 GHz versions of PCIe.

"We finished everything we thought we would need for a 0.9 version of the extensions," Krause said. "A couple people who co-authored this are very good at spec writing and are widely respected in the PCI SIG, he said.

"We've shared this with the PCI Special Interest Group, and it needs to decide what to do with it," he added.

At its annual conference in mid-July, the PCI SIG said it expects to publish by June 2010 the PCIe 3.0 spec which pushes the technology to data rates up to 8 GHz. It did not disclose any details about the AMD/HP proposal.

Krause said the extensions could still make it into the 3.0 draft which is not yet in a final 0.7 version stage. The extensions mark "a big step forward" for PCIe, said Krause. "I see it as something that could appear in products in 2012-13," he added.