Predictable Coherent Caching with Incoherent Caches

Caches are a well known hardware construct for improving energy consumption and average performance by keeping frequently-used data near processing resources. Yet, at the same time, they form a major hurdle for worst-case execution time analyses, in particular if they are shared between multiple cores. Exploiting that most shared data objects are accessed or at least committed in a mutually exclusive manner, the authors demonstrate, using an ARM MP-Core and an x86 multicore system, an explicit write-back synchronization scheme for shared data.