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As today’s handsets and consumer devices become more sophisticated, manufacturers continue to incorporate more and more functionality into a small and sleek form factor. Today’s range of smartphones incorporate voice and data transceivers, GPS, Bluetooth, Wi-Fi, cameras, music, touchscreen interfaces, compasses, motion sensors, cameras, storage cards, and many other technologies. Free turn-by-turn navigation services, such as offered on Google Android phones and iPhones, have created a compelling reason for many of us to own a GPS-equipped smartphone.

The pressure on manufacturers to integrate so many functions into one small printed circuit board has fueled a race among semiconductor suppliers to offer new solutions combining GPS and wireless connectivity. Phones that are small and comfortable to hold mean less and less space available for the internal electronics. Large screen sizes and the trend to thinner and thinner devices means smaller, less efficient antennas, placing pressure on chip designers to improve integrated circuit (IC) performance to make up for antenna constraints.

Finally, cost competition in these markets is intense, as operators compete to bring more users online.
These forces have shaped several changes in the wireless semiconductors found in new smartphones. Three important enabling technologies are:

reduced-geometry semiconductor technologies,

wafer-scale packaging, and

combo chip integration.

Let’s look at the trends in each area.

Semiconductor transistor sizes have been shrinking for decades. GPS processors in the market today use transistor geometries with gate widths of 0.18 micrometers, 0.13 micrometers, 90 nanometers (nm), and 65 nm, the latter showing up in the newest handsets on the market. 40-nm-based ICs have been announced as well, and will find their way into the market in the next year or two.

Each generation of technology offers a 50–100 percent increase in density for pure digital circuits. This so-called shrink has allowed designers to both reduce the size of chips and to pack in more performance — in GPS chips this usually means more tracking channels and more correlators for faster signal search. The area for non-digital circuits such as the radio receiver in a GPS has not been shrinking as fast as the digital portion. This had led to changes in architecture, with more and more functions going digital. Examples include digital band-shaping filters, digital gain adjustment, and sigma-delta analog- to-digital converters.

Wafer-scale packaging has moved into the mainstream for GPS and other wireless ICs. Traditional ball-grid array (BGA) packaging requires placing a semiconductor die on a substrate. The substrate carries the balls (pins) and some interconnects, and the semiconductor die is connected to the substrate via wire bonds. For small ICs the overall package size may be 50 percent larger than the die itself, because of overhead of the space needed for wire bonds.

By contrast, wafer-level ball grid array (WLBGA) packaging yields a finished packaged part with the same dimensions as the underlying die. Wire bonds are not used; a redistribution layer (RDL) is bonded to the silicon wafers and carries interconnections from the silicon to the balls. This type of packaging yields the smallest possible board footprint. It also places strict limitations on the number of package pins, since the pins must all fit under the chip and cannot be spaced too closely, due to board manufacturing constraints. Often designers struggle to provide the features customers seek while abiding by package pin-count limitations. Pins are shared or multiplexed to preserve flexibility.

Combo-chip integration offers the ultimate solution for small size. A single IC with multiple functions will almost always be considerably smaller than several ICs on a printed board. The last two years have seen the introduction of several combo ICs containing GPS, including the Broadcom’s BCM2075 Bluetooth-FM-GPS combo IC. Combo ICs like this allow manufacturers to build cellular handsets that would be difficult or impossible to create using discrete chip sets. Since GPS, FM, and Bluetooth have become standard features across many product lines, manufacturers not only benefit from small size but also economies of scale, designing a single part into dozens of devices.

The benefits of combo ICs are easy to understand, but making these devices brings unique challenges. First and foremost, these ICs are wireless devices containing multiple sensitive radios, where every fraction of a decibel of performance counts. With few exceptions, handset manufacturers and their wireless operator customers are not willing to sacrifice radio performance in their quest for miniaturization and cost reduction. Each function on the wireless combo IC must perform as well as its counterpart function in a stand-alone IC.

However, in a combo IC the radios are at most a few millimeters apart from each other. Designing for this type of integration requires engineering attention at multiple stages of the design. Up front, during the system engineering phase, component specifications must be set that minimize interference between radio subsystems, considering not just the radios on the combo IC but the influence of other radios in a handset as well. For example, in setting the specification for the second-order intercept point of the GPS receiver, system engineers must consider the fact that transmissions in 825 MHz cellular band can mix with Bluetooth transmissions at 2400 MHz to yield an intermodulation product at 1575 MHz, right in the middle of the GPS receive band. Designers also choose clock frequencies to avoid interference; for example, a GPS baseband processor that clocks at 100 MHz might be changed to 75 MHz to avoid the FM receive band. These are just a couple of examples of the many scenarios and considerations that must be examined early in the design process.

Once the system engineer has done his or her job, the next level of interference mitigation falls on the analog designers. They choose where to place circuits, how to structure the semiconductor layers, how to drive and load interconnects, and how to properly filter supply voltages to avoid undesired interactions. Keeping spurious products off local oscillator signals is a key challenge. GPS receivers have 100 dB or more of gain to amplify very weak GPS signals to a usable level. Due to this high gain, even a tiny spurious product on a local oscillator can have the effect of tuning in an undesired cellular transmitter. For example, a spurious product offset 135 MHz will tune a cellular transmitter at 1710 MHz down to 1575 MHz, again right in the middle of the GPS band. Avoiding these interactions requires experienced designers who can anticipate complex issues. Mistakes can be costly, with each mask for each IC iteration going into seven figures.

As the challenges of combo ICs are overcome, it’s likely the future will bring even more in the way of wireless technology integration. This in turn will provide even more opportunities for GPS to penetrate a broader set of handsets and cellular devices, making this exciting technology available to more consumers every day.

CHARLES ABRAHAM is senior director of engineering for the GPS Business Unit at Broadcom, which he joined via acquisition of Global Locate, a company he co-founded in 2000. Previously, he worked at Ashtech, Magellan, Trimble, and Hughes Electronics.