These are the 240/9240 models Cordell put in his last post. There are other models but this is the new VDMOS model which should do everything well. BUT, only a few people have seen it yet. So please verify it to your satisfaction (Cordell has the test jig and everything in his post) before using it for anything important.

PS. I didn't actually do much work, I just expressed enthusiasm mostly, hesitant to mess with the models because I knew I couldn't do better than Ian or Cordell and didn't see a way to help with the problems that were coming up. Now that the dust is settling a bit, I think I will try out the new model.

These are the 240/9240 models Cordell put in his last post. There are other models but this is the new VDMOS model which should do everything well. BUT, only a few people have seen it yet. So please verify it to your satisfaction (Cordell has the test jig and everything in his post) before using it for anything important.

PS. I didn't actually do much work, I just expressed enthusiasm mostly, hesitant to mess with the models because I knew I couldn't do better than Ian or Cordell and didn't see a way to help with the problems that were coming up. Now that the dust is settling a bit, I think I will try out the new model.

I tried Bobs THD test and added an old model pair for comparison. The VDMOS is really close and shows just how poor the old model was. I can see how the very abrupt transition of the old model could give very low THD simulation if you get the biasing just right

I made a mistake when starting this thread, I said FET and not MOSFET. I changed the references in the post but I wasn't able to edit the thread title. The improvements are to the MOSFET model, so won't work for Jfet models.