The Ultra PLL is designed with a state-of-the-art architecture using
high-speed digital and analog circuits that offers exceptional performance,
features and ease of use. It is highly programmable so one PLL can be used
for all applications on a SoC. It has ultra-low jitter performance (<500fs)
for the most demanding SerDes and ADC reference clocks. It has ultra wide
frequency range with multiplication factors over 250,000 to support
reference clocks from 32KHz to 1GHz. It has precise frequency control with a
least 26 fractional bits (at least 10 precise) for extremely high
fractional-N resolution. It can generate precise and adjustable frequency
spreading with programmable rate and depth to meet tight FCC requirements.
It draws low power in a compact size.