-----------------------------------------------------------ABSTRACT-------------------------------------------------------------------The increasing demand for higher data rate contributes in enhancing overall growth of digital systems.
However, an analog system continues to be a vital part of electronics sensor circuits. Thus every DSP consists
of both analog and digital sections. The need to lower down the power consumption in these systems has led
to a scaling down of most technologies. The Current-mode design techniques in analog circuits results in the
enhancement of bandwidth and linearity. One of the important building blocks in current-mode analog signal
processing is the OTA, which is basically a voltage to current converter. This paper deals with design and
analysis of single output Operational Transconduct ance Amplifier (OTA) in submicron CMOS process
technology (which was earlier done in 350nm technology). Simulations have been carried out in HspiceSynopsys and Awanwaves. This paper also covers effects of scaling on various parameters such as power
dissipation, total harmonic distortion , bandwidth etc. of the single output OTA in various CMOS process
technology.

are important building blocks for various analog
circuits and systems. Depending on system needs, an
OTA must satisfy many design requirements. As
CMOS technologies evolves the supply voltage
decreases and device characteristics deteriorate.
CMOS provides the highest analog-digital on-chip
integration. At present times, a typical Applications
Specific Integrated Circuit (ASIC) contains about 80%
digital and 20% analog circuitry. The digital circuits
are more robust with better performance. However,
digital circuits are inherently power hungry. This has
motivated the continual decrease in the feature size of
silicon technology and the supply voltage. The
operational transconductance amplifier topology
which is a single output OTA was simulated in 350nm
technology .These paper presents the simulation and
results of the single output OTA in 90nm technology.
The main objective of this paper is to study the effects
of the scaling on the operational transconductance
amplifier parameters such as power dissipation, Total
harmonic distortion (THD), bandwidth etc.
Bandwidth (or settling time), accuracy (offset,
noise, and gain), and power consumption are three of
the most important properties of the analog design.
However, they cannot be satisfied simultaneously. In

www.theijes.com

more power consumed. It is the analog designer’s task
to make the tradeoffs between bandwidth and
accuracy at minimum power consumption. Less power
is especially important in this “portable” era.

II. LV OTA DES IGN
A widely used approach in design of low voltage
circuits is to reduce the number of transistors between
the supply voltage and ground. This approach led to
the design of an OTA topology depicted in [1] known
as basic transconductor stage, which is not only very
simple in design but also works at really low voltages.
The output current is given by:

I 0  g m .Vin

(1)

Although it possesses good frequency response, the
topology carries the disadvantage of lack of tunability
& limited linearity.
Fig. 1 shows the circuit diagram for single output
OTA. This topology utilizes a variant of cross -coupled
cell to build the transconductor. In order to realize a
low voltage circuit just two MOSFETs have been used
between the power supply and ground. The circuit is
also tunable. The differential input is fed at the gates

The IJES

Page 191

Effect of Scaling On Operation of Low Voltage OTA
of M0 and M8. Vb is the control voltage, which adds
the proper tunability to the circuit. The output current
Io is given by:

I 0  2kn 2 (V1  V2 )(2Vtn  Vb )

(2)

and the transconductance gm is given by:

gm  2kn 2 (2Vtn  Vb )

(3)

Where Kn and Vtn have their usual meaning , V1-V2 is
the differential input, α is a scaling factor for the series
connected transistors and Vb is a bias voltage that
controls the transconductance gm .
The trasconductance g m of an OTA is a function of
OTA operating point, input voltage, output current,
and temperature and process parameters. The output
current in OTA is expanded in terms of Taylor series
which has dc component, a fundamental frequency
and other higher order harmonics which can cause
significant distortion. The distortion can be reduced
using various linearization techniques.

TABLE I
A SPECT RAT IOS OF T HE T RANSIST ORS IN OTA
Transistor
W/L ratio (180nm) W/L ratio (90nm)
M3, M4
4u/180n
2u/90n
M0-M2,
2u/180n
1u/90n
M5-M14
Table-I presents the aspect ratios of the
transistors used in the Dual input single output OTA.
Simulation results of the OTA were obtained using a
HSPICE Level 49 model. The aspect ratios of the
transistors have been selected so as to ensure
optimum performance.
Fig. 2 shows the ac analysis of the OTA , an ac sweep
was conducted for the frequency response of this
OTA topology. The current bandwidth was found to
be 123MHz , 5.46 GHz and 15.4 GHz approximately for
350nm , 180nm and 90nm respectively.
The transconductance gain was found to be 80.43 dB for 350nm and it increases when the
technology is nanotechnology. Table –II gives the
transconductance values of the OTA in dB.

III. SCALING AND EFFECT OF SCALING
Reducing the channel length of a MOSFET
can be described in terms of scaling theory. A scaling
parameter S (S < 1) is used to scale the dimensions of a
MOSFET. The value of S is typically in the
neighbourhood of 0.7 from one CMOS technology
generation to the next. For example, if a process uses a
Vdd of 2V, a next generation process would us e a Vdd
of 1.4V.
The main benefits of scaling are smaller
device sizes and thus reduced chip size (increased
yield and more parts per wafer), lower delays, allowing
higher frequency operation, reduction in power
dissipation. Associated with these benefits are some
unwanted side effects referred to as short channel
effects such as Hot carriers, Oxide breakdown, Drain
Induced Barrier lowering (DIBL), Substrate CurrentInduced Body Effect (SCBE), Gate tunnel current.

Fig. 2 A.C. analysis of OTA in 180nm &90nm
Fig. 3 and Fig. 4 shows the transient analysis of the
OTA, when conducting the transient analysis the
circuit was found to be stable. For a input of 100mV at
a frequency of 1MHz, the distortion produced by the
circuit is reduces to 0.0566 for 90nm technology.

I. FIGURES AND TABLES

Fig. 1 Single output Operational Transconductance
Amplifier

www.theijes.com

Fig. 3 Transient Analysis of OTA in 180nm

The IJES

Page 192

Effect of Scaling On Operation of Low Voltage OTA
are shrinking the process technology.
Fig. 3 is the transient simulation in 180nm which
shows the applied input voltage, output current and
power consumption during transient simulation
maximum value is 850uWatts and minimum is
700uWatts.
Fig. 4 is the transient simulation in 90nm which
shows the applied input voltage , output current and
power consumption during transient simulation
maximum value is 770uWatts and minimum is
670uWatts.

Fig. 4 Transient Analysis of OTA in 90nm
TABLE II
PERFORMANCE SPECIFICAT IONS OF SINGLE OUT PUT
OT A

CMOS
process
(nm)

Power

Iopp

T.H.D

F3dB

Gain

(mW)

(uA)

(%)

(GHz)

(dB)

350

3.369

20

0.2786

0.123

-80.43

180

0.7669

28.8

0.0966

5.46

-70.12

90

0.7214

38

0.0566

15.4

-68.31

IV. CONCLUS ION

Output current, Current Bandwidth and
Transconductance gain obtained is enhanced in 90nm.
Power consumption is reduced (LV/LP) and total
harmonic distortion is also reduced. Hence the circuit
performance is enhanced as we are shrinking the
technology and Low voltage /Low power circuits are
preferred for the enhanced performance it provides.

The single output OTA topology is scaled
down in 180nm and 90nm with supply voltage 1.5V
and 1.3V (LV) respectively. The Aspect ratios of the
corresponding transistors is given in Table-I. The
power dissipation at 180nm is found to be 0.7669mW
and in 90nm it is found to be 0.7214mw. The output
current swing obtained in 180nm (124μ -136μ) is less
than the 90nm (215μ -250μ) technology. Thus it can be
concluded that in 90nm the output current obtained is
more with less power dissipation as compared to two
other technology. From Table-II the power dissipation
in 350nm is 3.369mW which gradually decreases as we