A Closer Look

The PCB’s microstrip width (0.58 mm) is nominally dimensioned for an impedance of 50 Ω. However, the traces next to the input coupler’s mounting pads are necked down to compensate for the pads’ parasitic capacitances (Fig. 3). Computer simulations show that the 2.5-GHz input match can be improved by narrowing the trace width to 60% of its nominal value.

For circuit simulation, the design is modelled using a two-level nested hierarchy (Fig. 4). The upper level consists of blocks representing the MMIC, the signal dividing/combining, and the impedance-matching functions. Each of the dual amplifiers, Q1 and Q2, is represented by an identical set of scattering (S) parameters (.s2p). The device .s2p was previously extracted from a MMIC sample mounted on a test fixture of similar PCB material and thickness, using a thru-reflect-line (TRL) technique to compensate for the fixture.

The device’s noise and linearity [third-order intercept point (IP3)] parameters were also extracted on the same test fixture using automated source and load-pull tuners. The minimum noise figure, NFMIN, of about 0.4 dB is particularly challenging to extract because it is very close to the combined loss of the tuner, cables, and connector adapters. The inductors and couplers are modelled with their manufacturers’ .s2p data. Other passive components are modelled using their equivalent-circuit values, including first-order parasitic values.