Folding Levels • Logic folding can be performed at different levels of granularity, providing flexibility to perform area-performance trade-offs • A level-p folding implies reconfiguration of the LE after the execution of p LUT computations (a) level-1 folding (b) level-2 folding

Choosing the Folding Level • Advantages of logic folding • Significant flexibility for performing area-performance trade-offs • Ability to map much larger circuits using the same number of LEs • Significant improvement in the area/circuit delay product • Reduction in the need for global routing Clock period increases: Routing delay increases Number of clock cycles decreases Reconfiguration time decreases Total delay typically decreases Folding level Area increases Number of LEs increases

Experimental Setup • Instance of architecture: 4 MBs in an SMB, 4 LEs in an MB, and LEs contain a 4-input LUT • Number of reconfiguration copies k varied in order to compare implementations corresponding to selected folding levels: level-1, level-2, level-4 and no logic folding • Results based on 100nm CMOS technology parameters

Experimental Results (Contd.) • Flexibility in performing area-performance trade-off • For area-time (AT) product, larger the circuit depth, more the advantages of level-1 folding relative to no folding • For the 64-bit ripple-carry adder, this advantage is about 35X • LE utilization and logic density very high, with a reduced need for a deep interconnect hierarchy