Key Benefits

Methodology and tool support for DO-254 verification requirements traceability

Due to the ever-increasing costs of development and manufacturing of custom IC devices as well as the flexibility that FPGAs provide, many system houses use FPGA devices not just for prototype or early availability runs, but for the entire life of the product. The result is the number of designs that are implemented in FPGAs is growing, and the complexity of those designs is increasing, requiring more powerful EDA tools for design, up-front verification, debug, and implementation.

Cadence offers a variety of tools and methodologies that enable users to develop their FPGA designs quickly and effectively to improve quality and time to FPGA signoff. Our tools and our FPGA vendor relationships help users avoid long programming and field testing cycles.

Let us help you:

Track and sign off top-level requirements through all transformations for safety

Use techniques and methodologies to improve design productivity

Improve design creation and reuse of code

Implement system synthesis that feeds FPGA synthesis tools

Integrate coverage between formal and simulation increase coverage

Our portfolio includes:

Ability to track requirements through signoff for high-reliability, safety-critical, or any complex FPGA design projects with the vManager™ Metric-Driven Signoff Platform