VCC and VBAT can be sourced from the main board, any stackable daughter board, either communications areas or the rear connector.

Provision for in-system programming of any co-processor (AVR at least, maybe others depending on the requirements) via the backplane using the SPI signals and a PGM control signal.

Provision for simple debugging of any processor via four debug signals on the backplane.

Low(ish) power options, for example stackables daughter boards can have provision to cut power from IO circuitry and enter sleep mode or th ecore processor can cut power from individual stackable boards.

A fairly complete description of the system with schematics for most boards can be found at

How will you retain shield compatibility and also have 16-board addressability?

As the stackables can be used with only 5 IO lines the rest are free, they are of course subject to the usual clashing issues but there are probably enough free to allow coexistance with many shields.

The current adapter design just routes the signals and therefore doesn't help in this regard, however I do have plans to make the adapter itself addressable so Arduino shields appear at a single address. Just how practical this is I'm not sure as all 19 Arduino IO lines would have to be isolated and possibly pulled high/low when not selected.

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If you are talking over SPI as you say then won't you need at least 4 I/O lines "stolen" for chip select decoding?

The "chip select" (called BRDEN) comes from the decoder chip on the daughter board, therefore only 3 SPI lines are needed. On a smart board this would go to the SS input of the processor, when using an IO expander to the EN pin, and on a dumb board it is used to enable tri-state buffers.

So the worst case is that stackables use a heap of pins and the same clashing issues apply as with Arduino. Best case is only 5 pins are used (still allows up to 16 daughter boards on those 5 pins) and there's a good chance Arduino shields can be used as well.

It may be worth analysing a heap of shields to see if there's any grouping of pins used and ensuring that the 5 I need are on other pins to decrease the odds of a clash. The 3 SPI pins of course cannot be moved but software SPI could be used at the expense of speed.