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STARC Adopts Atrenta SpyGlass-Power for RTL Power Estimation and Verification

STARC Adopts Atrenta SpyGlass-Power for RTL Power Estimation and Verification

Tokyo, Japan January 27, 2010 -- Atrenta Inc., the leading provider of Early Design Closure solutions to radically improve design efficiency throughout the IC design flow, today announced the integration of the SpyGlass-Power solution into version 3.5 of the STARCAD-CEL reference flow for RTL estimation and verification. The STARCAD-CEL reference flow is provided by the Semiconductor Technology Academic Research Center (STARC).

Atrenta’s SpyGlass-Power solution provides early information about power consumption at RTL, and provides guidance for power reduction with respect to clock gating, memory and data path designs. The solution not only detects, but can also automatically fix key power management issues. The SpyGlass-Power solution supports UPF and CPF power formats, and verifies designs with voltage and power domain management structures so that voltage level shifters and isolation logic are correct.

SpyGlass-Power RTL estimation and verification capabilities have been incorporated into the version 3.5 of the STARCAD-CEL reference flow. STARC evaluated SpyGlass-Power using both vector-based and vector-less analysis for estimation of leakage power, data path, clock and memory power. STARC engineers also conducted an exhaustive evaluation of the CPF 1.0e & UPF 1.0 power formats.

“We are very impressed with the capabilities of SpyGlass-Power for RTL power estimation and verification - both with and without simulation vectors. The RTL power estimation results with simulation vectors for clock, data-path and memory were within 20% of final silicon numbers,” said Nobuyuki Nishiguchi, vice president and general manager at STARC. \"The integration of the SpyGlass-Power solution into the STARC production flow will save our customers from multiple iterations of synthesis and tens of hours of power simulations at the gate level.\"

“Atrenta is the only vendor to provide RTL power estimation, reduction and verification support for both CPF and UPF power formats at both the RTL and gate level,” said Mike Gianfagna, vice president of marketing at Atrenta. “STARC’s rigorous evaluation and adoption of SpyGlass-Power into the STARCAD-CEL flow has once again validated the importance of using early analysis solutions at RTL on low power designs.”

About Atrenta
Atrenta is the leading provider of Early Design Closure solutions to radically improve design efficiency throughout the IC design flow. Customers benefit from Atrenta tools and methodologies to capture design intent, explore implementation alternatives, validate RTL and optimize designs early, before expensive and time-consuming detailed implementation. With over 150 customers, including the world’s top 10 semiconductor companies, Atrenta provides the most comprehensive solution in the industry for Early Design Closure. For more information, visit www.atrenta.com. Atrenta, Right from the Start!

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Atrenta, the Atrenta logo, SpyGlass, and Early Design Closure are registered trademarks of Atrenta Inc. All others are the property of their respective holders.

This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this press release.