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Archive for April 5th, 2010

Add me to a growing list of EDA globetrotters because I spent five weeks of the first two months of 2010 traveling around the world, visiting India, Japan, Taiwan, Korea, China and France. It was an eye-opening experience and showed me that, while the world economy has not completely recovered, there is plenty of optimism and design activity in our semiconductor market segment.
During my travels, I found that chip design and verification seem to be on everyone’s mind. For example, many of the design teams I met with are starting new projects in the hot, hot, hot multimedia area to support high-definition TV. I talked with teams designing Blu-Ray and other high-definition disc players. Other consumer electronics areas are booming as well, as is the fast-paced networking and communications market.

In Asia, electronic system level (ESL) is in widespread use and, in Europe, STMicroelectronics still serves as the ESL early adopter and role model. It is also a leader in the move to transaction-level modeling through its efforts on the Open SystemC Initiative (OSCI) Transaction-Level Modeling Working Group. This standard is meant to enable interoperability between system models, intellectual property (IP) models and ESL design tools, and promote widespread acceptance of ESL.
Back in the United States and in meetings around Silicon Valley, I don’t see ESL adoption as yet, though that may change as full designs in all market segments around the world are now at least 10-million gates. Moreover, individual blocks are topping out at between two- and four-million.

My travelogue continues with the worldwide challenges of verification. In the verification niche shared by Real Intent, pioneer of automating formal technology for design verification, and EVE, developer of emulation and hardware-assisted verification, 10-million gate designs results in boundless opportunities.

In my roam around the world, I discovered that many “nice to have” technologies have become “must have” verification tools in the design flow, in particular, formal technology and emulation. That’s because design complexity is only increasing due to new features, added capabilities of existing products and need to get products to market faster. The added complexity brings forth isolated failure modes which demand specific technologies for the most efficient and effective verification, such as asynchronous clock domain crossing verification and timing exception verification using automated formal technologies. Equally attractive is emulation’s ability to be used across the entire development cycle, from hardware verification, hardware/software integration to embedded software validation. A new generation of emulators is capable of handling up to one-billion or more ASIC gates at high speeds in a short period of time, making them a great choice for such huge designs. Pricing is more competitive, too.

As a member of the EDA Globetrotter Travel Club, I’ve recently had the chance to meet with semiconductor companies worldwide embarking on all sorts of new and exciting development projects. In almost all cases, their verification needs are real and, almost always, verification solutions are available for almost every need. I didn’t need to globetrot the world to learn that.