Reveals the operation of and interaction between the design, assertions, and testbench

Figure 1: The unique behavior analysis technology of the Verdi3 system automatesmany time-consuming aspects of debug

Complete Debug SystemThe Verdi3 automated debug system incorporates all of the technology and capabilities you would expect in a debug system. In addition, the Verdi3 system combines advanced debugging features with support for a broad range of languages and methodologies.

Core FeaturesThe Verdi3 system provides the following fundamental debug features:

Full-featured waveform viewer enables you to display and analyze activity over time

Transaction-level debug views are based on extended FSDB and support new transaction and relation data recording

Figure 2: UVM-aware debug with built-in UVM intelligent viewers

Languages and MethodologiesThe Verdi3 system supports the following languages and methodologies:

Design components described in Verilog, VHDL, and SystemVerilog

Automated testbench environments using SVTB, as well as UVM, OVM and VMM

Assertions using SystemVerilog Assertions (SVA)

Optimized Open Architecture and Unified MethodologyThe Verdi3 automated debug system is designed so that you can take full advantage of your verification and debug methodology. The Verdi3 system is built on the open Design Knowledge Architecture, which consists of compilers that extract relevant information into databases that are optimized for efficient debug. The Verdi3 system also unifies your debug process by providing a single solution that operates seamlessly and consistently across multiple domains: verification tools, design/verification languages, and abstractions. This consistency reduces your learning curve and saves time as you move to new projects using different tools and languages, and allows you to further leverage your investment in the Verdi3 system even as your other tools and methodology evolve.

Application programming interfaces (APIs) provide open access to both databases and command-and-control mechanisms, enabling you to easily integrate the Verdi3 system with other verification tools and design environments

Third-Generation Debug PlatformThe Verdi3 platform builds on these core values with unprecedented personalization, customization and interoperability to maximize your debug productivity. You can speed debug of your large, complex designs, tailor the debug environment for the way you work, and directly integrate custom and third-party programs into your flows. Faster, smaller and more efficient infrastructure:

Interoperability and CustomizationThe open architecture and interoperability of the Verdi3 platform also enables you to leverage your investment with integration of other commercial and proprietary verification tools. Its continuously expanding ecosystem provides out-of-the-box support for a wide range of commonly used tools, including:

Simulators

Emulators and accelerators

Model checkers and other formal analysis engines

You can further maximize the effectiveness of your Verdi3 deployment with custom automation programs that leverage the power of its underlying design knowledge infrastructure for data mining and manipulation applications. Seamless integration with the VC Apps platform provides everything you need to quickly create and integrate Open Source scripts/ utilities with the Verdi3 software that are designed to work reliably in your flow.

Debug and Analysis Across Multiple Abstraction LevelsThe Verdi3 platform allows you to seamlessly debug throughout your system-level to gate-level methodology flow. It provides additional support for verification and analysis at the implementation level with the nAnalyzer Design Implementation Analysis Module, a single environment for analyzing troublesome design errors related to clocks, clock trees, and timing.

Power-Aware Debug ModuleThe Verdi3 Power-aware Debug Module accelerates the comprehension of power intent and automates the process of visualizing, tracing, and analyzing the source of power-related errors. It simplifies the verification of low-power SoC designs with unique automation technologies that help you visualize power intent with UPF/CPF, comprehend the impact of power intent on HDL design, and automate debug to determine whether unexpected design behavior is caused by functional logic or power-related issues.

Debug of Power-Aware Design IntentThe Verdi3 Power-aware Debug Module accelerates comprehension of power intent and automates the process of visualizing, tracing, and analyzing the source of power-related errors. It simplifies the verification of low-power SoC designs with automation technologies that help you:

Figure 5: Users can personalize the layout and debug modes of the Verdi3 environment

Figure 6: Complete power design intent aware debug views

Low-Power Debug ChallengesLow-power design requirements add more complexity to an already burdened verification process. RTL design can represent function and timing, but not power states. Gate-level design includes all information but the verification is too tedious. IP reuse is not possible when power requirements change. The need for a consistent format for describing power intent across the entire design and verification methodology creates new challenges that:

Introduce the new PDML language into the verification flow (UPF/CPF)

Require power-aware design environments to understand the power specification in the HDL design

Create gaps between HDL debugging and power-aware debug tools

Power Intent ComprehensionThe Verdi3 Power-aware Debug Module provides a high-level overview of power intent that can be correlated with RTL design data for a complete power-aware understanding of designs. Core features include:

Full UPF and CPF source code support allows you to import and compile power design data into FSDB

Easy-to-use Power Manager browser enables you to:

Visualize power domains, power networks and power states/modes

Annotate power intent on all design views (nTrace, nSchema and nWave

Locate power-related constraints for each power domain (power switch rules and retention, isolation and level-shifter rules)

Drag-and-drop cross-probing between PDML and all design views to identify the origin of power-related problems

Power-Aware Debug AutomationUsing the automated HDL debug capabilities of the Verdi3 system, you can track down the root cause of power-related design behavior across HDL design and power domains. Core features include:

Automatic unrolling of signal paths driven by power intent across different power domains back to the source code origin

Automatic tracing to locate drivers/ loads across the power manager and all design views

Active annotation of dynamic power modes in both the Power Manager and all design views for seamless tracing between HDL and CPF/UPF code

Temporal Flow View of power circuits that shows retention registers with save/restore signals and enables you to automatically trace control signals

Power state monitors that automatically identify the current power status of any signal at any simulation time

Special visualization for the values caused by power intent rules, such as isolation rules and power on/off

Reporting of signals impacted by power intent and related from/to instance (driver/load) with power domain

Automatic list X of selected signals with its driver and related power status

Bridging the Power Verification GapThe Verdi3 Power-aware Debug Module bridges the power verification gap with a universal platform for integrating power formats and innovations with HDL debug automation. By making it easier to visualize, trace and analyze complex power behaviors in both HDL design and UPF/CPF code, power issues can be resolved earlier in the process while also saving valuable verification cycles.

nAnalyzer Design Implementation Analysis ModuleThe nAnalyzer™ Design Implementation Analysis Module provides a single system for understanding and debugging critical design implementation issues that typically arise during synthesis and related activities that transform an RTL description into a gate-level netlist that is ready for tapeout. Throughout the flow, these transformations impact timing closure, power consumption, and clocking schemes. To detect and resolve detrimental effects in these areas, you must analyze your designs using specialized tools and techniques outside of the traditional simulation flow. The nAnalyzer solution both augments and enables these analysis steps through the following capabilities:

Clock Tree and Clock Domain AnalysisToday’s complex designs require special and often sophisticated clock schemes. Multiple clock domains introduce the need to synchronize data passed between the different domains. Low-power stipulations require special clock gating techniques. The integration of third-party IP presents unexpected clock-related challenges at the IP interface. All of these factors increase the complexity of the clock circuitry and introduce more opportunities for implementation errors and thus incorrect operation. The nAnalyzer solution provides powerful built-in analysis engines that enable comprehensive exploration and debug of common clock-related issues.

Timing and Power AnalysisAlthough dedicated tools exist that provide comprehensive analysis and verification in the timing and power analysis domains, it is often useful to interactively explore timing and power issues outside of these tools. In some cases, the data required for a comprehensive analysis may not be available. In other cases, the dedicated tool may take a long time to complete its analysis, but only a quick approximation is needed. The nAnalyzer solution provides built-in analysis capability in both the timing and power domains to meet these needs.

Timing Analysis Features

Import reports from common static timing analysis (STA) tools

Browse critical path details in text form or display and explore them in intuitive Verdi3 schematics

Interoperability with Third-Party ToolsComplete analysis and resolution of timing, power and clock scheme related issues often require the application of best-in-class tools dedicated to one of these domains. The nAnalyzer solution enhances your usability of these dedicated tools by importing, displaying, and enabling the exploration of the analysis results in the familiar Verdi3 environment.

Embedded Software DebugThe Verdi3 HW SW Debug works together with the Verdi3 Debug Automation System to provide a comprehensive multi-window hardware and software debug view of a SoC design. When operating Verdi3’s unified debug environment, both hardware and software engineers can simultaneously view their design at both hardware debug views and software debug views, including both C/C++ and assembly code as well as memory, register and breakpoint windows. Please refer to Verdi3 HW SW Debug datasheet for more details.

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