I have been playing around with the AMD fam10 codebase as of late.It is quite different from Intel hardware is that AMD hardware starts upother AP cores whereas on Intel hardware typically only the BSP runs code.

As far as I can tell the AP's are started early on. They then startrunning from the reset vector. The code then updates their microcodeand sets a 'reasonable' TOP_MEM MTRR such that when starting the APslater on during the ramstage, it won't result in any problems given that thestack will be in that 'reasonable' range (below CONFIG_RAMTOP). After that,they are put to rest and the BSP will be doing the rest of the thingsduring the romstage (raminit for instance).

Now the cbmem_top depends on the value the BSP set's in TOP_MEM, butunless the AP's have their own TOP_MEM (not shared MTRR) synced with theBSP. This syncing only happens during the AP init.

To implement relocatable ramstage this syncing needs to happen earlier,preferable during the romstage...

At the moment with relocatable ramstage enabled it hangs when startingthe APs as it puts their stack somewhere in CBMEM well above the'reasonable' default value of TOP_MEM which is CONFIG_RAMTOP.

Now my questions:

- Is this analysis correct?- If so, how to sync TOP_MEM in romstage (is there already an example ofan implementation somewhere?), is there an easy way to run code onall AP's during the romstage?- Are workarounds possible/better? like figuring out TOP_MEM saving itnvram and resetting and programming that value on AP's