Overview

Small is beautiful...
The DUART is one of the tiniest UART IP Cores available on the market.
It is a soft core of a Universal Asynchronous Receiver/Transmitter (UART). It performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (overrun, framing). The DUART includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (216-1), and producing a 16 clock for driving the internal transmitter logic.

Features

Majority Voting Logic; Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data

In UART mode receiver and transmitter are double buffered to eliminate the need for precise synchronization between the CPU and serial data

IP Quality Metrics

IP has been successfully implemented in production with at least one customer

Y

Deliverables

Customer deliverables include the following:

Design file (encrypted source code or post-synthesis netlist)

Simulation model for ModelSim Altera edition

Timing and/or layout constraints

Testbench or design example

Documentation with revision control

Readme file

Y

Parameterization GUI allowing end user to configure IP

Y

IP core is enabled for OpenCore Plus Support

Y

Source language

Verilog; VHDL

Testbench language

Verilog; VHDL

Software drivers provided

Y

Driver OS support

N/A

Implementation

User Interface

AXI; Avalon-MM

IP-XACT Metadata included

N

Verification

Simulators supported

ModelSim

Hardware validated

Y. Altera Board Name DE1, DE2

Industry standard compliance testing performed

N

If No, is it planned?

Y

Interoperability

IP has undergone interoperability testing

N

Interoperability reports available

N

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