vhdl high z

In I2C the Hi-Z state correspond to the '1' state because in the SDA line there must be a pull-up in the circuit. Check the I2C norm and you'll find it.
So, instead of do "IF (bus ='z')" you do "IF(bus='1')".
To test a Hi-Z state your device should measure the current that is drained in that line.

vhdl pullup

If use a buffer macro, Would anyone give a buffer name for any vendor product?

The construction if ( bus = 'z' ) data <= 1; can't be implemented in hardvare. But I think that your main problem is in understanding of I2C bus. It doesn't require to control "z" state. Please, study I2C standard carefully.

verilog high impedance

Originally Posted by BuBEE

IN FPGA io port before Read signal on SDA pin you must set port to 'H'
SDA <= 'H'

What are you talking about? We don't have to issue a high level to SDA. We even can't do that physically, because SDA is "open collector (or drain)". This pin may be only "0" or "z".
Let's separate the problem of simulatiom from real working circuits. I have faced the same situation. As soon as SDA pin is bidirectional, we can set SDA to "1" in simulator all the time, excluding moments of reading from device (for example, acknolledge on 9th clock) and moments of writing "0" into device, of course.
The project's code mustn't contain any analysis of levels, it must analyse transitions of SDA and SCL lines, for example START, STOP conditions, etc.
Talking in general, it should be a state machine.
I would like to advice you to visit http://www.opencores.org/ and find appropriate free examples there. A long ago I did that. And though I was forced to rewrite a piece of that code, I found it very useful.

Regards, YUV.

PS. Sorry, if I misunderstood you. I don't know VHDL. And Verilog doesn't have "H" syntax. I understood it as "1".

verilog compare hi-z

If use a buffer macro, Would anyone give a buffer name for any vendor product?

if (bus ='z ') // This express is not verilog !
if (bus =='z') // however the result of ( but =='z ') will be 'X'
if (bus ==='z ')//but case equality is not supported for synthesis
who can solve this problem? thank you

verilog highz

Hi

why do want to detect the high impedance state ?

Let me share my experience of this issue. It may help you.

I have designed FPGA core for parallel port in ECP mode. A normal parallel port supports up to 200 KHz. But the same in ECP mode, it supports 25 MHz (depends on design) or more. In this protocol, i had to design the bidirectional data bus between PC parallel port and FPGA. Whenever the FPGA wants to write some data on the bus, it can write data directly. Only problem is reading the data sent by PC. This time at FPGA side, the data bus should 'Z'. First we tried to check high impedance state on bus before reading. In fact, it was not possible. Then i used to make it high impedance before reading. then it was working perfectly.

My suggestion is it is better to make it high impedance before reading data in bidirectional signal (even in I2C) rather than checking for high impedance.

But only thing you should do is, you should make it high impedance before (atleast one clock before) you read. If you make this side (FPGA side) high impedance, then the otherside (Some other device) of the signal can be written by the data. So that you can read it.

If use a buffer macro, Would anyone give a buffer name for any vendor product?

if (bus ='z ') // This express is not verilog !
if (bus =='z') // however the result of ( but =='z ') will be 'X'
if (bus ==='z ')//but case equality is not supported for synthesis
who can solve this problem? thank you

For synthesis, you don't solve it with VHDL or Verilog. You solve it electrically with a pull up resistor. Effectively, a 'Z' state is logically a "disconnect" state. The pull up resistor connects the signal to '1' when all outputs (to the same signal) are in the Hi-Z or "disconnected" state.

z vhdl

For synthesis, the solution is circuitry. I'm going to assume you can read a circuit diagram.

When you put the FPGA output buffer (triangle on left) into the high impedance (Z) state with sig_out <= 'Z'; the "pullup" resistor R will raise sig_out towards the Power voltage, which is interpreted as the high or '1' state. This is basic digital electronics.

Note that it is the output circuit (buffer) that is in the hi-Z state, not the wire or signal.