Intel and Micron are jointly announcing new 3D NAND technology that will radically increase solid-storage capacity going forward. The companies have indicated that moving to this technology will allow for the type of rapid increases in capacity that are consistent with Moore’s Law.

The way Intel and Micron are approaching 3D NAND is very different from existing 3D technologies from Samsung and now Toshiba. The implementation of floating-gate technology and “unique design choices” has produced startling densities of 256 Gb MLC, and a whopping 384 Gb with TLC. The choice to base this new 3D NAND on floating-gate technology allows development with a well-known entity, and benefits from the knowledge base that Intel and Micron have working with this technology on planar NAND over their long partnership.

What does this mean for consumers? This new 3D NAND enables greater than 10TB capacity on a standard 2.5” SSD, and 3.5TB on M.2 form-factor drives. These capacities are possible with the industry’s highest density 3D NAND, as the >3.5TB M.2 capacity can be achieved with just 5 packages of 16 stacked dies with 384 Gb TLC.

While such high density might suggest reliance on ever-shrinking process technology (and the inherent loss of durability thus associated) Intel is likely using a larger process for this NAND. Though they would not comment on this, Intel could be using something roughly equivalent to 50nm flash with this new 3D NAND. In the past die shrinks have been used to increase capacity per die (and yields) such as IMFT's move to 20nm back in 2011, but with the ability to achieve greater capacity vertically using 3D cell technology a smaller process is not necessary to achieve greater density. Additionally, working with a larger process would allow for better endurance as, for example, 50nm MLC was on the order of 10,000 program/erase cycles. Samsung similarly moved to a larger process with with their initial 3D NAND, moving from their existing 20nm technology back to 30nm with 3D production.

This announcement is also interesting considering Toshiba has just entered this space as well having announced 48-layer 128 Gb density 3D NAND, and like Samsung, they are moving away from floating-gate and using their own charge-trap implementation they are calling BiCS (Bit Cost Scaling). However with this Intel/Micron announcement the emphasis is on the ability to offer a 3x increase in capacity using the venerable floating-gate technology from planar NAND, which gives Intel / Micron an attractive position in the market - depending on price/performance of course. And while these very large capacity drives seem destined to be expensive at first, the cost structure is likely to be similar to current NAND. All of this remains to be seen, but this is indeed promising news for the future of flash storage as it will now scale up to (and beyond) spinning media capacity - unless 3D tech is implemented in hard drive production, that is.

So when will Intel and Micron’s new technology enter the consumer market? It could be later this year as Intel and Micron have already begun sampling the new NAND to manufacturers. Manufacturing has started in Singapore, plus ground has also been broken at the IMFT fab in Utah to support production here in the United States.

Taking a Fresh Look at GLOBALFOUNDRIES

It has been a while since we last talked about GLOBALFOUNDRIES, and it is high time to do so. So why the long wait between updates? Well, I think the long and short of it is a lack of execution from their stated roadmaps from around 2009 on. When GF first came on the scene they had a very aggressive roadmap about where their process technology will be and how it will be implemented. I believe that GF first mentioned a working 28 nm process in a early 2011 timeframe. There was a lot of excitement in some corners as people expected next generation GPUs to be available around then using that process node.

Fab 1 is the facility where all 32 nm SOI and most 28 nm HKMG are produced.

Obviously GF did not get that particular process up and running as expected. In fact, they had some real issues getting 32 nm SOI running in a timely manner. Llano was the first product GF produced on that particular node, as well as plenty of test wafers of Bulldozer parts. Both were delayed from when they were initially expected to hit, and both had fabrication issues. Time and money can fix most things when it comes to process technology, and eventually GF was able to solve what issues they had on their end. 32 nm SOI/HKMG is producing like gangbusters. AMD has improved their designs on their end to make things a bit easier as well at GF.

While shoring up the 32 nm process was of extreme importance to GF, it seemingly took resources away from further developing 28 nm and below processes. While work was still being done on these products, the roadmap was far too aggressive for what they were able to accomplish. The hits just kept coming though. AMD cut back on 32nm orders, which had a financial impact on both companies. It was cheaper for AMD to renegotiate the contract and take a penalty rather than order chips that it simply could not sell. GF then had lots of line space open on 32 nm SOI (Dresden) that could not be filled. AMD then voided another contract in which they suffered a larger penalty by opting to potentially utilize a second source for 28 nm HKMG production of their CPUs and APUs. AMD obviously was very uncomfortable about where GF was with their 28 nm process.

During all of this time GF was working to get their Luther Forest FAB 8 up and running. Building a new FAB is no small task. This is a multi-billion dollar endeavor and any new FAB design will have complications. Happily for GF, the development of this FAB has gone along seemingly according to plan. The FAB has achieved every major milestone in construction and deployment. Still, the risks involved with a FAB that could reach around $8 billion+ are immense.

2012 was not exactly the year that GF expected, or hoped for. It was tough on them and their partners. They also had more expenses such as acquiring Chartered back in 2009 and then acquiring the rather significant stake that AMD had in the company in the first place. During this time ATIC has been pumping money into GF to keep it afloat as well as its aspirations at being a major player in the fabrication industry.

SOI has been around for some time now, but in partially depleted form (PD-SOI). Quite a few manufacturers have utilized PD-SOI for their products, such as AMD and IBM (probably the two largest producers of SOI based parts). Oddly enough, Intel has shunned SOI wafers altogether. One would expect Intel to spare no expense to have the fastest semiconductor based chips on the market, but SOI did not provide enough advantages for the chip behemoth to outweigh the nearly 10% increase in wafer and production costs. There were certainly quite a few interesting properties to PD-SOI, but Intel was able to find ways around bulk silicon’s limitations. These non-SOI improvements include stress and strain, low-K dialectrics, high-K metal gates, and now 3D FinFET Technology. Intel simply did not need SOI to achieve the performance they were looking for while still using bulk silicon wafers.

Things started looking a bit grim for SOI as a technology a few years back. AMD was starting to back out of utilizing SOI for sub-32 nm products, and IBM was slowly shifting away from producing chips based on their Power technology. PD-SOI’s days seemed numbered. And they are. That is ok though, as the technology will see a massive uptake with the introduction of Fully Depleted SOI wafers. I will not go into the technology in full right now, but expect another article further into the future. I mentioned in a tweet some days ago that in manufacturing, materials are still king. This looks to hold true with FD-SOI.

Intel had to utilize 3D FinFETs on 22 nm because they simply could not get the performance out of bulk silicon and planar structures. There are advantages and disadvantages to these structures. The advantage is that better power characteristics can be attained without using exotic materials all the while keeping bins high, but the disadvantage is the increased complexity of wafer production with such structures. It is arguable that the increase in complexity completely offsets the price premium of a SOI based solution. We have also seen with the Intel process that while power consumption is decreased as compared to the previous 32 nm process, the switching performance vs. power consumption is certainly not optimal. Hence the reason why we have not seen Intel release Ivy Bridge parts that are clocked significantly faster than last generation Sandy Bridge chips.

FD-SOI and planar structures at 22 nm and 20 nm promise the improve power characteristics as compared to bulk/FinFET. It also looks to improve overall power vs. clockspeed as compared to bulk/FinFET. In a nutshell this means better power consumption as well as a jump in clockspeed as compared to previous generations. Gate first designs using FD-SOI could be very good, but industry analysts say that gate last designs could be “spectacular”.

So what does this have to do with ST Ericsson? They are one of the first companies to show a products based on 28 nm FD-SOI technology. The ARM based NovaThore L8580 is a dual Cortex A9 design with the graphics portion being the IMG SGX544. At first glance we would think that ST is behind the ball, as other manufacturers are releasing Cortex A15 parts which improve IPC by a significant amount. Then we start digging into the details.

The fastest Cortex A9 designs that we have seen so far have been clocked around 1.5 GHz. The L8580 can be clocked up to 2.5 GHz. Whatever IPC improvements we see with A15 are soon washed away by the sheer clockspeed advantage that the L8580 has. While it has been rumored that the Tegra 4 will be clocked up to 2 GHz in tablet form, ST is able to get the L8580 to 2.5 GHz in a smartphone. NVIDIA utilizes a 5th core to improve low power performance, but ST was able to get their chip to run at 0.6v in low power mode. This decrease in complexity combined with what appears to be outstanding electrical and thermal characteristics makes this a very interesting device.

The Cortex A9 cores are not the only ones to see an improvement in clockspeed and power consumption. The well known and extensively used SGX544 graphics portion runs at 600 MHz in a handheld device, and is around 20% faster clocked than other comparable parts.

When we add all these things together we have a product that appears to be head and shoulders above current parts from Qualcomm and Samsung. It also appears that these parts are comparable, if not slightly ahead, of the announced next generation of parts from the Cortex A15 crowd. It stands to reason that ST Ericsson will run away with the market and be included in every new handheld sold from now until the first 22/20 nm parts are released? Unfortunately for ST Ericsson, this is not the case. If there was an Achilles Heel to the L8580 it is that of production capabilities. ST Ericsson started production on FD-SOI wafers this past spring, but it was processing hundreds of wafers a month vs. the thousands that are required for full scale production. We can assume that ST Ericsson has improved this situation, but they are not exactly a powerhouse when it comes to manufacturing prowess. They simply do not seem to have the FD-SOI production capabilities to handle orders from more than a handful of cellphone and table manufacturers.

ST Ericsson has a very interesting part, and it certainly looks to prove the capabilities of FD-SOI when compared to competing products being produced on bulk silicon. The Nova Thor L8580 will gain some new customers with its combination of performance and power characteristics, even though it is using the “older” Cortex A9 design. FD-SOI has certainly caught the industrys’ attention. There are more FD-SOI factoids floating around that I want to cover soon, but these will have to wait. For the time being ST Ericsson is on the cutting edge when it comes to SOI and their proof of concept L8580 seems to have exceeded expectations.