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System architecture

This paragraph describes the architecture of the MIPS system that currently is being emulated by Qemu. As Qemu is still very much work in progress this is expected to change.

Firmware

There currently is no firmware for Qemu. This is only a minor problem as unlike on a real system Qemu's virtual hardware is mostly initialized after a reset.

Processor

Qemu is simulating a 4KcMIPS32 processor with a 16 entry TLB. Both I-cache and D-cache are 4kB each, 2-way set-associative with 16 bytes per cacheline however the cache effects are not simulated and cacheops are treated as noops. This is a design decission to iprove performance over accuracy. No benchmarking has been done however it is expected that the performance of the virtual MIPS system will be comparable to emulation of the other processors.

Qemu's source code can also be configured to be built with support for a 4Km processor. However being TLB-less this processor is not of interest for Linux, so does not currently receive any sort of attention.