DesignCon 2019 Presentation Viewer

Welcome to the DesignCon Presentation Store. Here you can view and download conference and/or show floor theater presentations before, during, and after the event. If you’re looking for a presentation from a specific session that you’re unable to find here, note that it’s likely because the presenter has not provided permission for external use or has not yet shared their presentation with us. Please check back after the event for a more complete catalogue of available presentations.

Power integrity effects on signal integrity in FPGA DDR4 memory interfaces are analyzed in pre-layout, post-layout, and system validation data patterns created based on the resonance peaks of the power distribution network (PDN). The PDN impedance profile is measured with an FPGA configured vector network analyzer (VNA). Multiple test data patterns are created to superimpose the power supply current frequency spectral components with the PDN resonance peaks and to exercise transmission line multiple reflections build-up effect. These data patterns are then used to identify the dominant contributors to signal integrity degradation.

Takeaway

Attendants will learn a technique for identifying the dominant contributors of signal integrity degradation in high-speed interfaces, such as DDR4, using a statistical analysis approach for model extraction and worst case specific data patterns that exercise PDN resonant peaks and transmission line multiple reflections for simulation and validation.