1/ Does the circuit receive adc_data and transmit dac_data in a same frame or

in separated frames?

The part does send and receive data continuously and simultaneously. There is a delay from when the analog voltage appears at the input pins to when the data appears at the serial output or the analog output. This depends on configuration and how much processing the DSP core is doing. Look in the Typical Performance Characteristics section for multiple graphs of group delay details.

2/ in TDM mode why having 8 channels while only 2 dac channels or 4 adc

channels exist?

The part is designed to work with other parts in a system. It is capable of receiving serial data from another 4 ADCs and combining them into one TDM -8 steam to then send to a DSP or other system controller. It is also capable of tri-stating unused slots of a TDM stream so that there is a TDM bus and this part would insert its data onto the bus at the correct time. The TDM SOUT_CONTROL0 register sets this behavior.

3/ What is the tolerance about the 48/96/192khz sampling frequency?

This is dependent on the clock source for the MCLK input. The more accurate and stable the clock the closer the tolerance will be.

4/ In a TDM emission or reception, which channel is affected to each slot?

Figure 77 shows the signal routing. There are several registers that select what data will show up on which slot or which slot it will pick off the data. SigmaStudio is the best way to see where to set this. To set the Serial Output use the SOUT Source pull-down boxes to select which signal appears in which TDM slot. SOUT0 is the first slot and the pull down box selects which signal will be in that slot.

For the serial input to be sent to the DACs or the PDM output, you select the channel pair in the Input ASRC source select register. See the next screenshot to see where this is located in SigmaStudio:

Both of these diagrams and selections can be found by selecting the Hardware Configuration tab located in the upper part of the main window. Then on the lower part of the window you select the ADAU1772 Register Control tab. This will bring up a number of additional tab on the upper part of the window. Then select Signal Routing and you will see these selection boxes.

5/ for a TDM emission/reception, what is the slot length : always 32 BCLK

periods even for a 16 bits data or can it be 16 periods?

The BCLK Slot size can be either 32 BCLK periods or 16. You will find this setting in the Serial Port Control 1 Register, bit 2, BCLKRATE. You can also find it in the SigmaStudio register interface on the Output/Serial Port tab.

See the picture below: BCLK Cycles per Channel

I hope this helps. Please feel free to ask more questions and we will do our best to answer quickly.

1/ Does the circuit receive adc_data and transmit dac_data in a same frame or

in separated frames?

The part does send and receive data continuously and simultaneously. There is a delay from when the analog voltage appears at the input pins to when the data appears at the serial output or the analog output. This depends on configuration and how much processing the DSP core is doing. Look in the Typical Performance Characteristics section for multiple graphs of group delay details.

2/ in TDM mode why having 8 channels while only 2 dac channels or 4 adc

channels exist?

The part is designed to work with other parts in a system. It is capable of receiving serial data from another 4 ADCs and combining them into one TDM -8 steam to then send to a DSP or other system controller. It is also capable of tri-stating unused slots of a TDM stream so that there is a TDM bus and this part would insert its data onto the bus at the correct time. The TDM SOUT_CONTROL0 register sets this behavior.

3/ What is the tolerance about the 48/96/192khz sampling frequency?

This is dependent on the clock source for the MCLK input. The more accurate and stable the clock the closer the tolerance will be.

4/ In a TDM emission or reception, which channel is affected to each slot?

Figure 77 shows the signal routing. There are several registers that select what data will show up on which slot or which slot it will pick off the data. SigmaStudio is the best way to see where to set this. To set the Serial Output use the SOUT Source pull-down boxes to select which signal appears in which TDM slot. SOUT0 is the first slot and the pull down box selects which signal will be in that slot.

For the serial input to be sent to the DACs or the PDM output, you select the channel pair in the Input ASRC source select register. See the next screenshot to see where this is located in SigmaStudio:

Both of these diagrams and selections can be found by selecting the Hardware Configuration tab located in the upper part of the main window. Then on the lower part of the window you select the ADAU1772 Register Control tab. This will bring up a number of additional tab on the upper part of the window. Then select Signal Routing and you will see these selection boxes.

5/ for a TDM emission/reception, what is the slot length : always 32 BCLK

periods even for a 16 bits data or can it be 16 periods?

The BCLK Slot size can be either 32 BCLK periods or 16. You will find this setting in the Serial Port Control 1 Register, bit 2, BCLKRATE. You can also find it in the SigmaStudio register interface on the Output/Serial Port tab.

See the picture below: BCLK Cycles per Channel

I hope this helps. Please feel free to ask more questions and we will do our best to answer quickly.

If you setup the serial port in TDM4 mode, then the two serial output ports 0 and 1 will each take four channels. So the first four go to serial port 0 and the second 4, SOUT4,5,6 &7, will go to serial port 1.

If you choose a stereo format then the first two go to port 0 and the second 2 outputs go to port 1. The remaining four outputs will go nowhere.

Likewise, if you choose TDM8 then all 8 channels will be on serial port 0 and I don't think there will be anything on serial port 1.

One other little note I did not mention in my earlier post. If you use the tri-state unused slots register setting. Then there will be a problem with the CLKOUT pin. It is a bug in the silicon. So if you need to tri-state the TDM bus AND you need to supply a clock to another part using the CLKOUT pin then you will run into trouble. This is not really common and the workaround will be to run the other channels into the serial input port and route the four channels coming in over to the serial output port along with the internal four channels and then do not tri-state the TDM bus.

I am working with ADAU1772 codec device (Master mode) interfaced with Microcontroller, The codec is configured as Master mode and capturing audio data through serial audio interface (TDM4 mode,16bit data size,16k bit sampling). I can able to capture 4 channel data . But how can I separate 4 audio channel data.

The serial port will separate the data but only the first two channels go to the ASRC. The other two appear at the multiplexers to directly feed the output serial port. This is to daisy-chain two parts where each part only takes two of the channels and passes on the other two.

Also I have another question:- Actually in our design Self boot pin is connected to VDD so that codec will auto boot through EEPROM connected to it. Now if I need to change some codec register settings on runtime through the same I2C interface, Is it possible to do like this .

In our design Codec I2C pins are connected to both Microcontroller as well as EEPROM.

Yes, you can. You simply have to make sure the Microcontroller will not attempt to transmit anything on the bus while the 1772 is booting. The 1772 does not support a multi-master protocol where it will check to see if the bus is busy and detect collisions. So you have to wait until it has completed booting then you can change the registers.