How power-aware test improves reliability and yield

While many techniques have evolved to address power minimization during the functional mode of operation, it is also necessary to manage power during the test mode. Circuit activity is substantially higher during test than during functional mode, and the resulting excessive power consumption can increase chip reliability failures due to higher junction temperature and increased peak power.

Today, scan technology is used for integrated circuit (IC) test, which increases the switching activity well beyond that of the normal operation of the IC. This switching activity increases the energy, peak power and average power consumption of the device.

While energy is more important to monitor for situations where battery life comes into play, in manufacturing test the peak power and average power need to be controlled. If peak power exceeds a certain limit, the correct operation of the circuitry cannot be guaranteed. Excessive peak power over multiple cycles will elevate the temperature of the chip, causing instant damage or severe decrease in reliability of the IC.

Similarly, elevated average power causes structural damage due to hot spots on the silicon. Test tools attempt to address this problem by back-filling the "don't care X's" in the test patterns with values to reduce the switching activity during scan and, thereby, achieve power reduction.

While this is a step in the right direction, it does not holistically address all test requirements. As a case in point, recent advancements in test compression technology use these same X's, making them unavailable for back-filling to achieve power-reduction.

Over the years, numerous techniques for power reduction within the context of "back-end" test have been proposed, focusing on improvements to ATPG algorithms, pattern ordering methods, and scan chain modifications, as well as clocking changes. However, while these techniques have yet to come into mainstream use, the design flow has since adapted to create better power management within the context "front-end" design. These significant advancements in power management have created the need for new power-aware test technology that works throughout the flow.

In this article, we will look at the necessity of having a design flow that incorporates power-aware test. This includes the ability to design for testability and to create test programs for a device within its power limits.

Power-aware DFT in the design flow

In design for test (DFT), testability structures such as full-scan and test compression logic are typically added into the design during logic or physical synthesis.

DFT processes have traditionally focused on scan chain balancing for test time reduction and on scan chain ordering/routing for timing closure, often at the expense of power management or power closure. To correct this problem, DFT processes must become truly power-aware, capable of considering these three things:

Maximum power consumption during scan test mode(s).

Scan chain configurations in a multi-voltage or a multi-supply design.

The truly power-aware DFT flow will enable DFT structures to be rapidly implemented in concert with timing, area and power structures, enabling rapid closure of testable designs.

There are a myriad of challenges the designer must address to reduce power consumption during scan test, to configure scan chains in the multi-voltage/multi-supply design, and to deal with the test coverage issues caused by clock and power-gating techniques.

The total power consumption for any given design includes dynamic (active-mode) and leakage (standby-mode) power. Dynamic power is the energy consumed to accomplish useful work, whereas leakage power is the energy that is largely wasted while the device is waiting in standby.

Dynamic power reduction

Reducing dynamic power consumption in the design commonly involves the use of clock-gating techniques and/or the use of chip-level multi-voltage design architectures.

Figure 1 shows one such design transformation where dynamic power reduction is obtained in the design by gating the clock. Clock-gating techniques reduce power by inserting a disabling logic in the clock path when no state transition occurs on the state element(s).

Figure 1  Dynamic power reduction with clock gating

However, in scan test mode, all state elements must be fully controlled by test clocks. This is achieved by forcing clock-gating logic into an enabled state. Inserting any extra test control signals into the clock-gating logic will prohibit the ATPG tool from fully testing the clock control logic in the functional path. DFT is, therefore, required to improve test coverage, as shown in Figure 2.

Figure 2  DFT with clock-gating structure

In the case of multi-voltage (multi-Vdd) designs, the physical design is divided into multiple voltage islands, which may or may not share the same power supply voltage. Sharing signals across voltage islands may require the implementation of level shifters.

The insertion of scan chains across voltage islands, therefore, has to consider the impact these level shifters will have on the design. Scan chain routing within the bound of the voltage islands is preferred over random stitching of scan flip-flops across the voltage islands.

Leakage power reduction

Managing leakage power effectively is now critical to the success of wireless and portable applications. With respect to total power consumption, leakage power has increased from an almost negligible level to nearly 20 percent in 130-nanometer (nm) designs, 40 percent in 90-nm designs, and over 50 percent in 65-nm designs. The most common techniques for reducing leakage power are the use of power-gating state retention cells and the use of multi-threshold voltage libraries.

The use of power-gating state retention cells allows a system to shut down power to certain block(s) in a design, and recover the prior states after a power-up sequence. To implement power-gating, special state retention cells are required to store prior state(s) of the blocks before power down.

Both scan insertion and ATPG tools must take these special cells into account and provide full test coverage for these cells. The insertion of isolation cells for any signals output from the blocks in power-down is also required.

The use of multi-threshold (multi-Vt) libraries reduces leakage power by maximizing the use of high-Vt cells in a design, while achieving timing closure. High-Vt cells consume lower leakage power than low-Vt cells with the same function.

Some synthesis tools automatically select appropriate cells to achieve area, timing and power closure. On the other hand, maximizing the use of high-Vt cells to achieve lowest leakage can potentially make most of the signal paths' timing critical. Margin sensitivity could lead to yield concerns due to process variation, as well as the increasing need for timing-related delay fault testing.

Because of the optimizations in synthesis, too many critical paths are created for manufacturing test, leading to long test times if critical paths are to be tested. If solutions that lengthen the non-critical paths target optimizations of timing that build in a margin off the critical timing, the problem will not get unmanageable in test.

Figure 3 shows the optimizations made in synthesis, which has the effect of lengthening the non-critical paths. Here, a timing margin is "built in."

Historically, in full-scan designs, the average power consumption for scan ATPG vectors is roughly about 3X of mission (normal, functional) mode. However, in the arena of low-power designs, this approach now needs to be reconsidered.

Recent design evaluations have revealed that scan patterns in some designs may consume almost 30X of peak power over its mission mode. Without caution, such a magnitude of difference in power consumption can easily lead to permanent damage to the device under test, or, at the very least, result in reliability failures due to electromigration.

Low-power designs adopt the approach of "just-enough" energy to keep the system working to deliver the required functions. (As explained earlier, the techniques of clock-gating, power-gating and multi-voltage help to accomplish this low-power design goal.) However, scan-based ATPG, in principle, operates on the entire design at the same time. The ATPG process, therefore, can significantly increase the total power consumption in the design.

Recent studies and improvements made to ATPG tools have led to power-sensitive ATPG options, to create relatively low-power patterns for scan shift. For example, wherever possible, ATPG can minimize internal state transitions during scan shift by filling adjacent flip-flops with the same state, instead of using random fill. Evaluations have shown up to 50 percent power reduction is achieved with this approach alone.

As a recommended flow, it is always important to do power analysis for ATPG mode(s). For example, it is best to perform a dynamic power analysis with a small sample of ATPG patterns, or to run vector-free power analysis for the given test modes. Excessive power consumption can then be assessed and corrected through a change in design and test strategies. (For example, a design may be partitioned into smaller blocks and test may be run serially.)

Power-aware test planning

At design nodes of 65-nm and below, these additional design planning capabilities become essential in the flow to ensure rapid closure of testable designs:

DFT-aware power grid planning. Design planning tools may need to preview power grid requirements for various test modes prior to "committing" the plan.

Power-aware test method and architecture planning. Predicting potential power consumptions will become very important to address the tradeoffs of designing for economical test methods or intelligent scheduling to remain in the target power budget. This is particularly significant for on-chip BIST applications or compression techniques to reduce test data volume.

Protecting power integrity and increasing shippable yield during test. Predicting potential voltage-drop during scan or BIST mode and creating a sufficient power network are becoming critical for shippable yield. Abnormally high levels of state transitions and voltage-drop during scan or BIST mode can lead to severe degradation of system performance. Numerous reports from a variety of companies reveal that, while doing at-speed transition delay testing, fully functional devices have been falsely discounted as "bad". This has resulted in lowered yield (see Figure 4).

Power management is important for both the functional and test modes. Synthesis and implementation flows must address testability within the context of low-power design, and the two must work together to ensure real quality of results.

A comprehensive platform solution for power-aware test is now necessary to achieve testability, quality, reliability and yield goals.

Dr. Cheng Shi is Director of Corporate Application Engineering (CAE) for Low Power and Automatic Test-Pattern Generation (ATPG) products within Synopsys' Implementation Group. Dr. Shi joined Synopsys in 1996, and previously held positions as Director of Test Consulting Services at Synopsys, and a Design for Test (DFT) Consultant at Viewlogic/Sunrise Test Systems before the company was acquired by Synopsys in 1997.

Dr. Rohit Kapur is a Synopsys Scientist who guides the development of Synopsys design-for-test (DFT) solutions based on Core Test Language (CTL) and other open standards. He is chair of the Core Test Language, IEEE P1450.6, standard committee, and was named IEEE Fellow in January, 2003 for his outstanding contributions to the field of IC test technology.