A Timing-Driven RTL-Based Design Flow for Multi-FPGA Rapid Prototyping SystemsWithin this work existing rapid prototyping design flows for FPGA-based functional verification have been analyzed and a new timing-driven design flow starting at register transfer level has been proposed, which addresses the insufficiencies of the analyzed approaches. The efficiency of the proposed design flow has been proven by experimental results obtained by a prototype implementation called PuMA, which is a generic fully automatic LPM-based partitioning and technology mapping environment targeting LUT-based FPGAs. Multi-FPGA partitioning, direct generator-based technology mapping and signal-flow-driven floorplanning as well as placement is performed by interacting processes implementing the first available RTL-based EDA tool targeting direct implementation of RT-level netlists into heterogeneous multi-FPGA rapid prototyping systems.