Job Description: Responsible for ensuring the testability and manufacturability of integrated circuits from the component feasibility stage through production ramp. Make significant contributions to design, development and validation of testability circuits. Evaluation, development and debug of complex test methods. Develops and debugs complex software programs to convert design validation vectors and drive complex test equipment. Creates and tests validation and production test hardware solutions. Tests, validates, modifies and re-designs circuits to guarantee component margin to specification. Analyzes and evaluates component specification versus performance to ensure optimal match of component requirements with production equipment capability with specific emphasis on yield analysis and bin split capability. Analyzes early customer returns with emphasis on driving test hole closure activities. Creates and applies concepts for optimizing component production relative to both quality and cost constraints. Autonomously plans and schedules own daily tasks, develops solutions to problems utilizing formal education and judgment.Qualifications: Detailed Position Summary: -Deliver test solutions and module to the manufacturing test program to: -Screen PLL related defects -Tune the PLL to its optimized performance and stability -Enable data collection critical to PLL characterization that is needed for debug, performance monitoring, and learning for future product/process

HVM day-to-day: Pre-Silicon: - Definition of how-to-test a certain PLL parameter May involved meeting with design or test engineers from other products/sites - Writing and launching test in RTL ,system Verilog or Intel-based test writing language -Test results verification and debug May involve review with peers and design -Conversion of test to test pattern -Development of test program module flow Needs tester knowledge and scripting (Python, xml) Scripting skills need file parsing, string manipulation, search algorithms and calculation -Integration, validation and release of test module and patterns into test program Will require coordination with test program team Need to attend regular meetings for test program team pass down and schedule -Post-Silicon: -Pre-Silicon activities will usually overlap with post-Si work -Characterization or DV of PLL on Silicon in the context of high volume -Perform statistical analysis and conclusions regarding PLL health and performance based on high volume Requires skills in data mining, data manipulation, and use of statistical tools: SQL, Proficiency in scripting and Unix (Perl/Python), Medium to advance level Excel, JMP -Unit level debug on anomalous or outlier units Requires debug skills May require coordination with design and bench DV team Will require enough knowledge of PLL architecture and operation to be able to design experiments DOE -Optimization of test module performance May require creative solutions to achieve cost-saving and high quality solutions on test implementations -Desired candidates: -Self-driven and strong team player -Makes initiative in working with or helping peers -Strong background on analog circuits (LDO, regulators, basic feedback and filter circuits, PLL, A2D, DAC) -Hands-on Verilog experience -Strong scripting background (Python or Perl) -Proficient on Unix and Excel -Basic test method background (e.g., how to test open/short, leakage) -Knowledge of how a ATE (e.g. timing/levels/patterns) -Data mining and manipulation background (SQL) -Understands statistics and how to statistically present high volume data