This patchs adds a new access driver for the existing
USB-Blaster interface driver.

This interface (as it is build-in on the sockit development
board) is composed of a Cypress EZ-USB plus a CPLD.

The Cypress chip as an embedded 8051 microcontroller.
When it's powered up, the firmware is downloaded to the
chip then the device is disconnected and reconnected with
the new firmware.

The USB-Blaster II protocol is almost identicial to
the old one. The only difference is that you need to
send a 0x5F before read TDO back. This command
seems to copy TDO buffer datas to the endpoint buffer.

This is used for the emulated DCC channel which is only maintained as long
as target->dbg_msg_enabled is set. Skip the saving and restoring if not
enabled to save one dap_run() per core register access.

Note that we could've probably queued all core register accesses in the
same transaction if the armv7 register framework hadn't required
synchronous register accesses.

IAP commands fail on programming LPC810 because it has only 1kByte of SRAM.
This patch is fixing cmd51_max_buffer suitable size for LPC810,LPC811 and
other LPC1000 series.
Tested on a LPC810,LPC812,LPC11u14,and LPC1114(DIP28).

This adds a new NOR Flash driver, "at91samd", which supports the
built-in Flash on Atmel's D-series Cortex M MCUs, starting with the D20.
Parts and their geometry are detected automatically using the DSU and
lookup schemes described in the D20 document, 42129F–SAM–10/2013.
Future D-series variants and families should presumably use this
controller as well (possibly with minor changes and improvements).

Tested on the SAMD20 Xplained Pro board, for which we also add the
corresponding Flash configuration.

This adds a new NOR Flash driver, "at91sam4l", which supports the
built-in Flash on Atmel's low-power SAM4L family of Cortex M4 MCUs.
Parts and their geometry are detected automatically using the Chip ID
and lookup schemes described in document 42023E–SAM–07/2013.

These kits feature a CMSIS-DAP compliant debugger and so have been added
as part of the pending support.

Currently the flash drivers for the L8 and D20 are wip.

One issue this implementation of CMSIS-DAP raised is that it supports
512byte HID reports, however using the current HIDAPI we have no cross platform
way of querying this info. Long term we plan to add this support to HIDAPI.

This is based on work from:
https://github.com/TheShed/OpenOCD-CMSIS-DAP/tree/cmsis-dap

Main changes include moving over to using HIDAPI rather than libusb-1.0
and cleaning up to merge into master. Support for reset using srst has
also been added.

It has been tested on all the mbed boards as well as the Freedom board
from Freescale. These boards only implement SWD mode, however JTAG mode
has been tested with a Keil ULINK2 and a stm32 target - but requires a lot
more work.

This adds a set of helper functions with the aim to make it possible
to flash mass-market devices without RTFMing altogether (i.e. to
obsolete GPL-violating proprietary tjtag and other similar software).

This adds the bcm47xx config with the special undocumented trick to
put it into standard EJTAG mode from the mystic "LV mode".

The RAM setup is not done as it would require considerable efforts
without much practical gain.

The only issue I noticed so far is that "reset" doesn't actually reset
the chip.

Unfortunately, it's unclear how to make it work properly with SRST as
OpenOCD asserts it in MIPS-specific code so the device will enter LV
mode again but the LV tap is already disabled by that time, so it's
not possible to send the magic command again.

Anyway, this config is more than enough to "recover" any RT-N16
provided the hardware is not damaged.

On all platforms, search for scripts in
$HOME/.openocd
${run_prefix}${pkgdatadir}/site
${run_prefix}${pkgdatadir}/scripts

On Windows, set run_prefix to the runtime path of the executable, minus
${bindir}. This is to enable the install dir to be moved anywhere, as long
as the structure of the install dir is kept intact. On all other platforms,
run_prefix is empty.

The script paths can now be adjusted on Windows builds the normal way; by
overriding pkgdatadir at build time. For example, to create a Windows
package layout of

bin/openocd.exe
scripts/interface/...
scripts/target/...

you can do
configure --prefix= --enable-... and then
make pkgdatadir= DESTDIR=/some/path clean all install

at91sam7sx.cfg: fix use $_TARGETNAME as target identifier, not '0' warning

all other at91 cfg files already has this fix.
It also fix "No flash at address 0x...." error when JTAG chain consist of
more than one at91sam7sx cores during attempt to flash other than first mcu
in chain.

STM32F42xxx & STM32F43xxx series boudary scan TAP-ID are differ from
STM32F405xx/07xx & STM32F415xx/17xx.
And Section number was also fixed for RM0090 rev5.
Tested on a STM32F427IIT6 and STM32F429ZIT6.

get_flash_bank_by_addr() iterates through all flash banks
trying to auto_probe() every bank, even if bank can belongs to
target other than requested, and this other target can be
in non-halted state, which leads to error message and
operation abort.
Same situation in gdb_new_connection() and gdb_memory_map():
get_flash_bank_by_num() tries to auto_probe() requested bank,
so first get bank by get_flash_bank_by_num_noprobe(), check
if it belongs to current connection's target and skip
get_flash_bank_by_num() (actually autoprobing) if not.

Add a command to specify the serial string and pass it to the find helper.
Actual matching was already supported for both serial and product but was
using hard coded string indices. Instead use the indices from the device
descriptor.

This add support to the Xilinx BSCAN_* virtual JTAG interface.
This is the Xilinx equivalent of the Altera sld_virtual_jtag interface,
it allows a user to connect to the debug unit through the main
FPGA JTAG connection.

The current way of detecting the sector size of the internal
flash does not work for all Kinetis MCUs. Add support for the
K21 flash by detecting the specific model from the SDID register
and picking the correct sector size based on that.

If the flash is not ready (MDM_STAT_FREADY is 0) then
dap_syssec_kinetis_mdmap() would act as if the MDM_STAT_SYSSEC bit was
set and erase the flash. Wait until MDM_STAT_FREADY is set before
checking the MDM_STAT_SYSSEC bit.

When programming large FPGAs the generated SVF files might contain really
long SDR scans. They won't fit in the 1MiB jtag scan page at all, so in
this case the allocated page needs to be bigger. The current code was
silently corrupting memory.

One particular example was sent by Volter targetting XC3S4000. It has an
SDR 11316992 bits long, that is 1414624 bytes.

Some MB9Ax (especially few internal SRAM model) fails programming
because of wrong SRAM basic-address on running algorithm.
Default SRAM basic-address must be 0x20000000.
This patch is fixing default SRAM basic-address and ramcode offset.
Tested on a MB9BF618T and MB9AF112K.

Re-order the "trace" parameters to allow the raw capture (log) file to
be an optional feature. The clock frequency for calculating the "Async
Clock Prescalar" is always required when enabling trace processing and
is now the first "required" parameter.

The ST-Link driver is updated to use the (required parameter)
"trace_source_hz" non-zero value as the indicator of trace being
required, rather than the now optional output file descriptor being
non-NULL.

Background: This patch is groundwork for extending the OpenOCD SWO
capture to implement other (OpenOCD built-in) ITM/DWT processing where
the core trace support is required, but there is no requirement to
store raw trace data to a configured host file. By itself this patch
is almost a functional NOP, since without the other processing in
place there is no reason NOT to specify a capture file.

This is a tcl implementation of public domain tests by Michael Barr,
http://www.barrgroup.com/Embedded-Systems/How-To/Memory-Test-Suite-C

The initial porting is done by Shane Volpe and posted to the mailing
list:
http://www.mail-archive.com/openocd-development@lists.berlios.de/msg16676.html

This patch includes some cosmetic amendments plus hardcodes 32bit word
size (as the code depends on memread32/memwrite32 anyway) which fixes
original code's issue of testing only the first quarter of the
specified nBytes.

There is an remark in jtag_srst and jtag_trst variables declaration:
/*
* JTAG adapters must initialize with TRST and SRST de-asserted
* (they're negative logic, so that means *high*). But some
* hardware doesn't necessarily work that way ... so set things
* up so that jtag_init() always forces that state.
*/

but in hla_target such forsing is missed and both variables remains
uninitialized until "reset" command issued, It prevents target polling
when connecting to running target.