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Disclosed is a method for hardware stack based architecture for
processor pipelines in multi-threaded systems. Benefits include improved
functionality, improved performance, and improved reliability.

Background

Conventionally, software
programs (processes) use two kinds of memory types, global heap memory and
local stack memory. They are specific to each thread.

Local variables that
use the software stack are limited in number and size. This software stack is
not as big as the stack of most structured programming languages. Bigger chunks
of memory are allocated in heaps and not in a stack.

Light weight, low
power processing cores with support for multiple threads are gaining
popularity. The reduction in power and size is primarily achieved by reduction
in complexity. The trend is to use in-order execution engines with multiple
thread support and avoid all the complexities associated with an out-of-order
execution approach. The assumption is that the multi-thread scheduler, which
executes before the processing pipeline, pushes a new thread if the current
thread is stalled by a load operation. However, if frequent load/store
instructions exist in all threads, the pipeline stalls even with multiple
threads. To achieve optimal performance, there is a need to reduce the access
time for frequent memory accesses.

General description

The disclosed method
is load-store pipeline architecture based on an on-chip hardware implementation
of a process (task) specific software stack. The method includes a processing
pipeline with thread-specific stack memory that is an on-chip hardware stack.
Access to the stack memory is provided through a special port called stack load
store port (SLSP) in addition to typical load store ports (LSPs). The
hardware-based on-chip memory stack stores process/thread-specific information,
such as the process control block (PCB) for faster context switches.