Intel has announced the commercial introduction of a game-changing new …

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At an event today in San Francisco, Intel announced one of the most important pieces of semiconductor news in many years: the company's upcoming 22nm processors will feature a fundamental change to the design of the most basic building block of every computer chip, the transistor.

Intel has been exploring the new transistor for over a decade, and the company first announced a significant breakthrough with the design in 2002. A trickle of announcements followed over the years, as the new transistor progressed from being one possible direction among many to its newly crowned status as the official future of Intel's entire product line.

In this short article, I'll give my best stab at explaining what Intel has announced—the so-called tri-gate transistor. Semiconductor physics are not my strong suit, so corrections/clarifications/comments are welcome. Also, this explanation focuses solely on the "3D" part of today's announcements. Other features of the 22nm process, like high-K dielectrics and such, are ignored. (So if you see a funny term on a slide and you don't know what it means, either ignore it or hit one of the Related Links for more info.)

But before we dive into what's new about Intel's transistor design, we first have to review how traditional transistors work.

Planar transistors and leakage current

A planar transistor

Intel

In the diagram above, you can see that a traditional "planar" transistor—the kind that was first invented at the dawn of the microchip era, and which has been the norm up until today's announcement—consists of three main parts: source, drain, and gate. (This is actually one specific kind of transistor, a MOSFET, but let's not get too deep into the weeds.)

The device may look odd, but it's really just an electrical switch. Think of the source and the drain as the two slots in a standard electrical socket; if you stuck a conducting wire (like a coat-hanger ) into both of the slots, you'd close the circuit and current would flow (and sparks would fly, flesh would burn, etc... so don't try that at home.) The transistor's substrate is sort of like a magic wire that can either conduct electricity or not, and the gate is the switch that controls whether the wire will conduct or not.

So when a voltage is applied to the metal plate that forms the transistor's gate, a tiny strip of semiconductor material between the source and the drain (our magic wire) changes from an insulator into a conductor, thereby turning the switch "on" and allowing current to flow from the source to the drain. When the voltage is removed, current stops flowing... or, at least, current is supposed to stop flowing when the switch is off. In reality, trace amounts of current will constantly flow between the source and the drain. This so-called "leakage current" wastes precious power and becomes even more of a problem as transistors get smaller and more numerous.

So to recap, the basic idea is that the transistor is a switch that works because a tiny bit of insulating material between two "electrodes" magically morphs into a conductor when a voltage is applied to it, thereby closing the circuit.

Let's take a look at a different diagram of the same thing:

A planar transistor

Intel

That little strip of blue, the inversion layer, is the region of material near the gate that turns into an electrical conductor when exposed to a voltage. Again, the gate is a small metal plate, and when that plate has a voltage applied to it the layer of semiconductor material that's sandwiched right up against it turns into a conductor.

Now, as transistor gates get smaller, that little strip of blue conducting material naturally gets smaller, and as that little strip of blue gets smaller, less current is able to squeeze through it. When the gate and inversion layer get really small, as they are at the 22nm feature size, that layer can only let a tiny trickle of electrons flow through when the switch is on. But there's already a tiny trickle of (leakage) current flowing through when the switch is off, so the end result is a switch that looks almost the same when it's off as it does when it's on. That's not good, because flipping the switch "on" and "off" is how the chip transmits the 1's and 0's of binary.

There are two main was to fix this problem: 1) reduce the leakage current, and/or 2) force more electrons through that blue conductive strip. Intel's new design does a bit of both, but I'll focus on option 2, because that explains the majority of what's new and important about this advance.

There are two ways to get more electrons through that tiny blue strip. The first and most obvious approach is to crank up the amount of voltage that you apply to the gate, so that the inversion layer will become even more electrically conductive. That's not ideal, though, because more voltage means more power consumption.

The other approach, which is better, is to find a way to make that blue strip even bigger. A bigger blue strip could accommodate more electrical current, and it would do it with less voltage—i.e., you don't need to crank the voltage on the gate up quite so high in order to squeeze more conductivity out of that tiny strip of material, because the strip itself is larger and can transmit more current.

Intel took this second approach, and the chipmaker accomplished this by stretching the gate out into the third dimension.

155 Reader Comments

Maybe this can have a less obvious answer. Is it called "tri-gate" due to the "3 sides" to the gate on top versus "1 side" in the planar design? But it's still one electrical gate wrapped around the new "fin", isn't it?

Now, as transistor gates get smaller, that little strip of blue conducting material naturally gets smaller, and as that little strip of blue gets smaller, less current is able to squeeze through it. When gate and inversion layer get really small, as they are at the 22nm feature size, that layer can only let a tiny trickle of electrons flow through when the switch is on. But there's already a tiny trickle of (leakage) current flowing through when the switch is off, so the end result is a switch that looks almost the same when it's off as it does when it's on. That's not good, because flipping the switch "on" and "off" is how the chip transmits the 1's and 0's of binary.

@ JonWhen you state that "as the little strip of blue gets smaller, less current is able to squeeze through it" ... actually this is not truly accurate in the direction your image refers to (along the channel from Source to Drain).

As gate length shrinks, the On current also increases, however its the Off current that increases much more strongly. This is because the gate loses control on the inversion layer (due to fringing fields and depletion region encroachment) and thus, is unable to truly turn the device Off. This is the Short Channel Effect. Consequently, you are correct that the On to Off ratio is degraded, but this is due to increases in the Off current as opposed to a reduction of the On current.

Having a "tri-gate" device allows strong improvements in the gate control as it wraps around on 3 sides - thereby reducing the Off current even at very short dimensions. This should help standy power significantly.

An interesting consequence of "tri-gate" is ... having "compressed" a larger inversion layer into a smaller space in plan view helps Intel boost their device packing density also.

I'm curious if Intel has patented this technology. If so, will they be licensing it to other companies? If not, how long will it take other companies to start using the same method? It seems like this will be a huge advantage for Intel over all other manufacturers if they are the only people that can use it. Of course, they did work on it for over 10 years, so if anything is patentable, this should be.

Maybe this can have a less obvious answer. Is it called "tri-gate" due to the "3 sides" to the gate on top versus "1 side" in the planar design? But it's still one electrical gate wrapped around the new "fin", isn't it?

Yes, it is called "tri-gate" in most semiconductor literature due to the gate wrapping around 3 surfaces of the channel region. It usually still is 1 gate electrically, but that too is not absolutely necessary. More exotic devices with multiple electrical gates do exist in the literature.

I'm curious if Intel has patented this technology. If so, will they be licensing it to other companies? If not, how long will it take other companies to start using the same method? It seems like this will be a huge advantage for Intel over all other manufacturers if they are the only people that can use it. Of course, they did work on it for over 10 years, so if anything is patentable, this should be.

The general idea of a FinFET is older than 20 years so that is not patented. I wouldn't be surprised if most of the technology is kept as a trade secret as not to give ideas to anyone else on how to manufacture them.

Nice to know someone's figured out how to actually manufacture finFETs on a large scale - I remember reading a bunch of papers on the technology back in 2002 (including a piece in spectrum), and it's nice to know that someone's actually figured out how to make them on a large scale.

I think it's more interesting that Intel says they have a roadmap to 10nm. I thought CMOS becomes physically useless at that scale.

Without this exact advancement in technology, you would be correct. Shrinking the size of transistors decreases the size of the inversion layer leading to the issues discussed in the article. This article directly addresses the physics behind the existing limitations, and how they're being addressed (adding a third dimension to grow the inversion layer).

I'm curious if Intel has patented this technology. If so, will they be licensing it to other companies? If not, how long will it take other companies to start using the same method? It seems like this will be a huge advantage for Intel over all other manufacturers if they are the only people that can use it. Of course, they did work on it for over 10 years, so if anything is patentable, this should be.

The general idea of a FinFET is older than 20 years so that is not patented. I wouldn't be surprised if most of the technology is kept as a trade secret as not to give ideas to anyone else on how to manufacture them.

However, Intel may patent all or part of the manufacturing process that allows them to do this at scale with reliability and so on. Their approach to creating the structures may be novel. I would be very surprised if a good chunk of all the manufacturing IP was not protected.

Are ARM processors also planar transistor devices? If so, how are they able to reduce power draw so drastically yet achieve similar or better performance as Intel chips?

ARM processors have a different architecture and are actually lower performance. In particular, I think that Intel's x86 to micro-op translator is a big part of the power difference since it is still a large part of the die.

Jon, I'm not sure that the schematic you have of the Trigate structure is fully accurate. My impression was that the gate does wrap around each channel (as the picture shows) but that each transistor also has multiple channels. This is useful because one consequence of thinning down the 'wire' or inversion channel is that electrical resistance goes up as the channel shrinks (just as in a regular wire). By having multiple channels, the total channel area goes up. Therefore the total electrical resistance and thus waste heat is reduced for the same current flow (ON or OFF) which means cooler parts.

Can you clarify this? The waffle-like structure in the SEM image from Intel in this article is somewhat confusing - it as it appears to show multiple channels as I described but also multiple gates. I'm wondering if Intel PR gave out conflicting/confusing pictures.

Very interesting. Great article. I understand microprocessors much better now.

Im sure Intel has this whole thing patented up the arse, so that is unfortunate. Not that I dont want Intel to profit from the decade of research put into this, but as an AMD fan, Id love to see some more variation with this new technology.

Oh, now I get it. I was looking at the left side of the second picture, trying to figure out how the transistor would let current flow horizontally (as in the piccy on page 1). The 3D version on the right showing the source in front and the drain in the back hadn't even registered in my thick skull, and I was baffled as to what the hell they were up to.

Now, as transistor gates get smaller, that little strip of blue conducting material naturally gets smaller, and as that little strip of blue gets smaller, less current is able to squeeze through it. When gate and inversion layer get really small, as they are at the 22nm feature size, that layer can only let a tiny trickle of electrons flow through when the switch is on. But there's already a tiny trickle of (leakage) current flowing through when the switch is off, so the end result is a switch that looks almost the same when it's off as it does when it's on. That's not good, because flipping the switch "on" and "off" is how the chip transmits the 1's and 0's of binary.

@ JonWhen you state that "as the little strip of blue gets smaller, less current is able to squeeze through it" ... actually this is not truly accurate in the direction your image refers to (along the channel from Source to Drain).

As gate length shrinks, the On current also increases, however its the Off current that increases much more strongly. This is because the gate loses control on the inversion layer (due to fringing fields and depletion region encroachment) and thus, is unable to truly turn the device Off. This is the Short Channel Effect. Consequently, you are correct that the On to Off ratio is degraded, but this is due to increases in the Off current as opposed to a reduction of the On current.

Having a "tri-gate" device allows strong improvements in the gate control as it wraps around on 3 sides - thereby reducing the Off current even at very short dimensions. This should help standy power significantly.

An interesting consequence of "tri-gate" is ... having "compressed" a larger inversion layer into a smaller space in plan view helps Intel boost their device packing density also.

He's partially right in that due to the excessive increases in leakage from having a shorter channel, keeping power and the IV-curve in a reasonable level means one would have to either dope the body less, thus resulting in lower mobility in the channel, or decrease the width of the channel which decreases Ion.

However, the very act of making the channel shorter doesn't decrease carrier mobility nor Ion, as you said. In fact, it increases it.

One interesting thing is that, in theory, with an effectively wider channel (only the width isn't planar anymore), both leakage and on-current should be increased. However, this provides the benefit of greater density (as the transistor now provides the same on-current as one 2-3x as wide) and also allows an increase in the thickness or dielectric constant of the insulator between the gate and the channel without overly increasing the gate capacitance, which has been the traditional trade-off between speed (thin insulator, more leakage) and power (thick insulator, less leakage).