Sigasi 2.29

Better Verilog support

We significantly improved our internal Verilog parser. Our parser is now able to give type-time syntax errors for Verilog (2005) code. This gives you instant feedback about Verilog syntax errors. So no more waiting for the compiler to find syntax issues.
Note that this feature is disabled by default. You can enable/disable it with the Ctrl-3 keyboard shortcut, and next typing Toggle Verilog problem markers.

SystemVerilog for synthesis

We added support for the synthesisable subset of SystemVerilog. This means that Sigasi can now cope with:
Packages
Typedefs
Structs
Unions
Arrays of arrays
Enums
For loops
...

The New Verilog file wizard now allows you to create SystemVerilog files too (.sv, .svh).

Cadence Incisive (NCSim)

[Sigasi Premium Desktop and Sigasi Premium Doc]

You can now configure Cadence Incisive (NCSim) as save-time-compilation for your HDL code. Once configured, Sigasi will automatically run ncvhdl and ncvlog to compile your code. All issues will get a problem marker in the editor and will appear in the problems view.

Other new and noteworthy improvements

The Sigasi Premium Desktop formatter now converts keywords to lower case when the Upper case keywords formatting option is disabled. (Note that the Sigasi Pro formatter will not change the keyword casing).

Expose BlockConfiguration context in VHDL autocomplete templates

We added a filter to project explorer to filter all non-Verilog files

Bugfixes

ticket 2840 : Autocomplete for entity instantiations does not work well with upper case setting