Pain Points At 7nm

Early work has begun on 7nm. Process technology has progressed to the point where IP and tools are being qualified.

There is still a long way to go. But as companies begin engaging with foundries on this process node—TSMC is talking publicly about it, but Intel, GlobalFoundries and Samsung reportedly are all working on this node, as well. This has provided some glimmers of what designing at this new process will entail.

To begin with, process node numbers are ill-defined and confusing. In the past, a node was defined by line widths. The numbers being used now are more arbitrary. Back end of line (BEOL) no longer matches front end of line for all foundries. While Intel uses 14nm finFETs with a 14nm BEOL, TSMC’s 16nm uses a 20nm BEOL process. Samsung’s 14nm BEOL uses a different min pitch (64nm) than its 20nm BEOL (80nm), so it defines that node as 14nm FEOL and BEOL design rules.

What exactly constitutes a 7nm design is rather fuzzy. But it’s clear that foundries no longer see 10nm as a major process node from a demand perspective, according to numerous industry sources. They are pushing to 7nm finFETs, regardless of what that actually means for each foundry’s BEOL process and marketing definition.

More data
The amount of data that chipmakers have been wrestling with at each new node has been rising due to concerns about power, leakage current, process variation, electromigration calculations, multi-patterning and exceptions to rules caused by integration of IP. But at 7nm the volume of data that needs to be processed is expected to grow non-linearly compared with previous nodes.

“With process variation, corners become more of a problem,” said Mike Gianfagna, vice president of marketing at eSilicon. “You need to manage more sets of data. In the past, min-max was typical. Extra corners kick up correlations, so the amount explodes. Real ASICs will be a legitimate Big Data problem at 7nm.”

For tools companies, this isn’t all bad. It means significantly more resources will be required to build these advanced chips, including more hardware acceleration and more tools for DFM/DFY/DFT.

“The big change is triple coloring,” said Michael Buehler-Garcia, director of Calibre Design Solutions marketing at Mentor Graphics. “Getting this right can mean the difference between good performance and standard performance, and you have to control that through the design flow.”

He noted that the amount of data consumed by coloring and fill is roughly double what it was at 16/14nm. “For post fill, there is so much data that we’re recommending our customers keep the database in Calibre and stream the results to the router.”

Part of that data explosion also comes in the form of new design rules, which are increasingly at a non-linear rate compared with previous nodes.

“The theme of these rules is still line and cut,” said Vasilios Gerousis, distinguished engineer and technologist at Cadence. “But we need to understand the termination rules surrounding IP. You cannot put two IP blocks together and assume they will line up. There will be some violations with the cut, which is for the mask layer. And there must be a termination rule with each block.”

The line/cut process been around for many years in the photomask world, but it has become much more complicated at advanced nodes because of problems with line-edge roughness. This is one of the key reasons the semiconductor industry has been so focused on next-generation lithography such as EUV and multi-beam e-beam, as well as chemically and non-chemically amplified resists.

“We will need to worry about how to constrain blocks so that other blocks are lined up or so there is a larger space or termination set of rules,” said Gerousis. “This is a major thing that has not existed before. Everything is closer together, so coupling has a big impact.”

He noted that even with EUV, the line/cut issues will be a problem. “EUV does give you better yield. And if someone is in charge of the whole SoC, they can line up the blocks and it isn’t as much of a problem. But if they get IP from different groups, or they mix up IP in a design, that can create issues.”

How much will it cost?
What’s also coming into focus is just how hard it will be to design and manufacture chips at 7nm. So far, it appears that finFETs developed at 16/14nm will scale to 7nm, although there still could be changes as test chips begin rolling out of foundries. It is assumed that gate-all-around FETs will be the next finFET technology, but when that happens is unknown at this point, at least partly because naming conventions for process nodes is increasingly inconsistent. Also on the drawing board are vertical and horizontal nanowire FETs and carbon nanotube FETs.

At this point, it appears that most of the IP developed at 14nm will be scalable, as well. “We have access to the PDKs and will be delivering IP to customers this year,” said Navraj Nandra, senior director of marketing at Synopsys. “But there are a lot more people looking at the cost equation. Some have a two-chip solution, where the VLSI is in 7nm, while they still use the same IP and memories. But they cannot move DDR to the latest node, so they’re coming at it from an HBM (high-bandwidth memory) standpoint. With HBM-2 you can have tens of terabytes. The trick with HBM, though, is you need to build an ecosystem with a foundry or packaging house. Right now, they are doing that without any special tools.”

And this is one of the themes emerging out of 7nm so far. While some tools work, notably emulation/simulation/verification, more needs to be automated for costs to come down. “It’s more IP, more verification complexity, more verification at the SoC level with the larger SoCs,” said Dave Kelf, vice president of marketing at OneSpin Solutions.

Ever since 28nm, cost per gate has been increasing. At 16/14nm that was largely due to the introduction of finFETs and double patterning. At 7nm, if EUV is not ready for prime time—that depends on advances in sustained uptime, advances in EUV resists and higher-wattage power supplies—some sort of multi-patterning will be required. Even if EUV is introduced, at 7nm that will require double patterning, but line-edge roughness issues will be sharply reduced.

In addition, while finFETs essentially make leakage current a non-issue at 16/14nm due to three-sided control of the gate, most experts believe the leakage problem will grow worse at each successive process node after that. As a result, chipmakers will have to deal with both increased dynamic power density in addition to leakage current, which will add steps for power estimation and analysis, thermal management, verification and debug, and increasing unknowns involving reliability and yield.

That has other effects, as well. “While gates are shrinking, wires are not, so more and more the communication is becoming a dominant design decision,” said Joe Rowlands, chief architect at NetSpeed Systems. “How do you get information from one side of the chip to the other, or between the various agents? There’s all the typical tricks of trying to send it faster with larger metal, thicker wires, higher metal layers, but that only works if you can keep the wire count minimal. So the trend is that the interconnect is becoming much more important, and we’re going to see more people focused on wire counts — how many wires are crossing the chip.”

So how much extra will this cost? It’s difficult to assess at this point. It will certainly be more expensive to produce initial chips than at the previous node. How much more depends on what companies are trying to design. Companies that push to the leading edge of design are veteran chipmakers with a deep understanding of IP, physical effects, and manufacturing possibilities. The question is whether they can get enough scale, most likely over time through multiple derivative chips, to recoup their investment at 7nm. The answer so far isn’t clear.

Even less clear is whether chipmakers will be able to do the same kind of tweaks to processes and IP that were possible at previous nodes, and what the cost will be in terms of power, performance and yield. Those tweaks were a way of differentiating designs, but it gets harder at 7nm, where everything is a system-level decision.

“It used to be that interconnect was a very physical design activity, meaning, it was after you figured out the architecture, after you did the design, then you worried about buses or crossbars,” said Anush Mohandass, vice president of marketing at NetSpeed. “As we went from 40 to 28, we realized we need to pay attention to these things that communicate with each other. As a result, it was pushed into the design phase. At 7nm, interconnects become an integral part of your chip.”

Ed Sperling

3 comments

Solid summary of the challenges they face. It is interesting to get some history back through 28. Are the design constraints that we built up by going to line and cut still really nessecary with EUV? What if a chip with a higher “width”.. (node? What does this even mean? Why not go to N6 but actually be 10nm wide just for comedic value)… actually performed better because of the unconstrained design? What about pitch with EUV?

Sang Kim
First, lets look at the uniqueness of 7nm FinFET. In my opinion 7nm FinFET will be the last FinFET technology node that no longer has the periphery regions any more unlike 22nm, 14nm and 10nm FinFETs. Instead, 7nm at the bottom and 4nm at the topmost is so narrow that the entire channel becomes fully inverted just like a double gate transistor resulting in large transistor derive currents. How can these be called as pain points at 7nm as claimed?

Furthermore, FinW(width) equal to 5nm or less is not manufacturable because depositing such an ultra thin 5nm filum uniformly and reliably over 12″ wafers at the manufacturing line is extremely difficult or may not be manufacturable. If not manufacturable, the debate is over. Therefore, 7nm FinFET is the end of ITRS(International Roadmap for Semiconductors).