Yingda Dong, San Jose US

Yingda Dong, San Jose, CA US

Patent application number

Description

Published

20100034022

COMPENSATING FOR COUPLING DURING READ OPERATIONS IN NON-VOLATILE STORAGE - Capacitive coupling from storage elements on adjacent bit lines is compensated by adjusting voltages applied to the adjacent bit lines. An initial rough read is performed to ascertain the data states of the bit line-adjacent storage elements, and during a subsequent fine read, bit line voltages are set based on the ascertained states and the current control gate read voltage which is applied to a selected word line. When the current control gate read voltage corresponds to a lower data state than the ascertained state of an adjacent storage element, a compensating bit line voltage is used. Compensation of coupling from a storage element on an adjacent word line can also be provided by applying different read pass voltages to the adjacent word line, and obtaining read data using a particular read pass voltage which is identified based on a data state of the word line-adjacent storage element.

02-11-2010

20100322005

REDUCED PROGRAMMING PULSE WIDTH FOR ENHANCED CHANNEL BOOSTING IN NON-VOLATILE STORAGE - Program disturb is reduced in a non-volatile storage system during a programming operation by switching from using programming pulses of a longer duration to programming pulses of a shorter duration, partway through the programming operation. A switchover point can be based on temperature, selected word line position and/or tracking of storage elements to a trigger state. The switchover point occurs sooner for higher temperatures, and for drain side word lines. The trigger state can be selected based on temperature. A portion of storage elements which are required to reach the trigger state to trigger a switchover can also be set a function of temperature. Programming pulses of a shorter duration improve channel boosting for inhibited storage elements, thereby reducing program disturb for these storage elements.

12-23-2010

20100329002

FORECASTING PROGRAM DISTURB IN MEMORY BY DETECTING NATURAL THRESHOLD VOLTAGE DISTRIBUTION - Program disturb is reduced in a non-volatile storage system during a programming operation by determining a susceptibility of a set of storage elements to program disturb and taking a corresponding precautionary measure, if needed, to reduce the likelihood of program disturb occurring. During programming of a lower page of data, a natural threshold voltage distribution of the set of storage elements is determined by tracking storage elements which are programmed to a particular state, and determining how many program pulses are need for a number N

12-30-2010

20100329010

READ OPERATION FOR MEMORY WITH COMPENSATION FOR COUPLING BASED ON WRITE-ERASE CYCLES - A read operation for non-storage elements compensates for floating gate-to-floating gate coupling and effects of program-erase cycles. During programming of a word line WLn+1, the threshold voltages of previously-programmed storage elements on WLn are increased due to coupling. To compensate for the increase, during a subsequent read operation of WLn, different sets of pass voltages are applied to WLn+1 for each control gate read voltage which is applied to WLn. The pass voltages vary in each different set so that they are a function of the control gate read voltage which is applied to WLn. The pass voltages may also be a function of a number of program-erase cycles. A higher amount of compensation is provided by increasing the pass voltages as the number of program-erase cycles increases.

12-30-2010

20110013460

DYNAMICALLY ADJUSTABLE ERASE AND PROGRAM LEVELS FOR NON-VOLATILE MEMORY - Degradation of non-volatile storage elements is reduced by adaptively adjusting erase-verify levels and program-verify levels. The number of erase pulses, or the highest erase pulse amplitude, needed to complete an erase operation is determined. When the number, or amplitude, reaches a limit, the erase-verify level is increased. As the erase-verify level is increased, the number of required erase pulses decreases since the erase operation can be completed more easily. An accelerating increase in the degradation is thus avoided. One or more program-verify levels can also be increased in concert with changes in the erase-verify level. The one or more program-verify levels can increase by the same increment as the erase-verify level to maintain a constant threshold voltage window between the erased state and a programmed state, or by a different increment. Implementations with binary or multi-level storage elements are provided.

01-20-2011

20110026331

PROGRAM VOLTAGE COMPENSATION WITH WORD LINE BIAS CHANGE TO SUPPRESS CHARGE TRAPPING IN MEMORY - Program disturb is reduced in a non-volatile storage system during a program operation for a selected word line by initially using a pass voltage with a lower amplitude on word lines which are adjacent to the selected word line. This helps reduce charge trapping at floating gate edges, which can widen threshold voltage distributions with increasing program-erase cycles. When program pulses of higher amplitude are applied to the selected word line, the pass voltage switches to a higher level to provide a sufficient amount of channel boosting. The switch to a higher pass voltage can be triggered by a specified program pulse being applied or by tracking lower state storage elements until they reach a target verify level. The amplitude of the program voltage steps down when the pass voltage steps up, to cancel out capacitive coupling to the selected storage elements from the change in the pass voltage.

02-03-2011

20110044102

SELECTIVE MEMORY CELL PROGRAM AND ERASE - Techniques are disclosed herein for programming memory arrays to achieve high program/erase cycle endurance. In some aspects, only selected word lines (WL) are programmed with other WLs remaining unprogrammed. As an example, only the even word lines are programmed with the odd WLs left unprogrammed. After all of the even word lines are programmed and the data block is to be programmed with new data, the block is erased. Later, only the odd word lines are programmed. The data may be transferred to a block that stores multiple bit per memory cell prior to the erase. In one aspect, the data is programmed in a checkerboard pattern with some memory cells programmed and others left unprogrammed. Later, after erasing the data, the previously unprogrammed part of the checkerboard pattern is programmed with remaining cells unprogrammed.

02-24-2011

20110051517

PARTIAL SPEED AND FULL SPEED PROGRAMMING FOR NON-VOLATILE MEMORY USING FLOATING BIT LINES - Partial speed and full speed programming are achieved for a non-volatile memory system. During a program operation, in a first time period, bit lines of storage elements to be inhibited are pre-charged, while bit line of storage elements to be programmed at a partial speed and bit lines of storage elements to be programmed at a full speed are fixed. In a second time period, the bit lines of storage elements to be programmed at the partial speed are driven higher, while the bit lines of storage elements to be inhibited are floated and the bit line of storage elements to be programmed remain fixed. In a third time period, the bit lines of storage elements to be inhibited are driven higher while the bit lines of the storage elements to be programmed at the partial speed or the full speed are floated so that they couple higher.

03-03-2011

20110170358

PROGRAMMING NON-VOLATILE STORAGE WITH FAST BIT DETECTION AND VERIFY SKIP - A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one or more targets are verified to determine whether they have reached their target and are locked out of further programming if it is determined that they have reached their target. Non-volatile storage elements being programmed to the second set of one or more targets are tested to determine the number of fast programming bits. When the number of fast bits for a particular target is greater than a threshold, then programming stops for the non-volatile storage elements being programmed to the particular target.

07-14-2011

20110242899

EXTRA DUMMY ERASE PULSES AFTER SHALLOW ERASE-VERIFY TO AVOID SENSING DEEP ERASED THRESHOLD VOLTAGE - An erase operation for non-volatile memory includes first and second phases. The first phase applies a series of voltage pulses to a substrate, where each erase pulse is followed by a verify operation. The verify operation uses a verify level which is offset higher from a final desired threshold voltage level. The erase pulses step up in amplitude until a maximum level is reached, at which point additional erase pulses at the maximum level are applied. The first phase ends when the verify operation passes. The second phase applies one or more extra erase pulses which are higher in amplitude than the last erase pulse in the first phase and which are not followed by a verify operation. This avoids the need to perform a verify operation at deep, negative threshold voltages levels, which can cause charge trapping which reduces write-erase endurance, while still achieving the desired deep erase.

10-06-2011

20110249504

SAW-SHAPED MULTI-PULSE PROGRAMMING FOR PROGRAM NOISE REDUCTION IN MEMORY - In a memory system, a programming waveform reduces program noise by using sets of multiple adjacent sub-pulses which have a saw-tooth shape. In a set, an initial sub-pulse steps up from an initial level such as 0 V to a peak level, then steps down to an intermediate level, which is above the initial level. One or more subsequent sub-pulses of the set can step up from an intermediate level to a peak level, and then step back down to an intermediate level. A last sub-pulse of the set can step up from an intermediate level to a peak level, and then step back down to the initial level. A verify operation is performed after the set of sub-pulses. The number of sub-pulses per set can decrease in successive sets until a solitary pulse is applied toward the end of a programming operation.

10-13-2011

20110255345

PROGRAMMING NON-VOLATILE STORAGE INCLUDNG REDUCING IMPACT FROM OTHER MEMORY CELLS - A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells using a programming signal that increases over time. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells using a programming signal that has been lowered in magnitude in response to the first trigger. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells with the programming signal being raised in response to the second trigger. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.

10-20-2011

20110273935

MITIGATING CHANNEL COUPLING EFFECTS DURING SENSING OF NON-VOLATILE STORAGE ELEMENTS - Channel coupling effects during verify and read of non-volatile storage are mitigated by matching the amount of channel coupling that occurs during read with channel coupling that occurred during verify. All bit lines may be read together during both verify and read. In one embodiment, first bias conditions are established on bit lines when verifying each of a plurality of programmed states. A separate set of first bias conditions may be established when verifying each state. Biasing a bit line may be based on the state to which a non-volatile storage elements on the bit line is being programmed. A separate set of second bias conditions are established for each state being read. The second bias conditions for a given state substantially match the first bias conditions for the given state.

11-10-2011

20120140559

SELECTIVE MEMORY CELL PROGRAM AND ERASE - Techniques are disclosed herein for programming memory arrays to achieve high program/erase cycle endurance. In some aspects, only selected word lines (WL) are programmed with other WLs remaining unprogrammed. As an example, only the even word lines are programmed with the odd WLs left unprogrammed. After all of the even word lines are programmed and the data block is to be programmed with new data, the block is erased. Later, only the odd word lines are programmed. The data may be transferred to a block that stores multiple bit per memory cell prior to the erase. In one aspect, the data is programmed in a checkerboard pattern with some memory cells programmed and others left unprogrammed. Later, after erasing the data, the previously unprogrammed part of the checkerboard pattern is programmed with remaining cells unprogrammed.

06-07-2012

20120188824

PROGRAMMING NON-VOLATILE STORAGE WITH FAST BIT DETECTION AND VERIFY SKIP - A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one or more targets are verified to determine whether they have reached their target and are locked out of further programming if it is determined that they have reached their target. Non-volatile storage elements being programmed to the second set of one or more targets are tested to determine the number of fast programming bits. When the number of fast bits for a particular target is greater than a threshold, then programming stops for the non-volatile storage elements being programmed to the particular target.

INTELLIGENT SHIFTING OF READ PASS VOLTAGES FOR NON-VOLATILE STORAGE - A first read pass voltage is determined and optimized for cycled memory. One or more starting read pass voltages are determined for one or more dies. The system dynamically calculates a current read pass voltage based on the number of program/erase erase cycles, the first read pass voltage and the respective starting read pass voltage. Data is read from one or more non-volatile storage elements using the calculated current read pass voltage.

Reducing Weak-Erase Type Read Disturb In 3D Non-Volatile Memory - A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel is boosted by controlling of voltages of bit lines (Vbl), drain-side select gates (Vsgd_unsel), source-side select gates (Vsgs_unsel), a selected level (word line layer) of the memory device (Vcg_sel), and unselected levels of the memory device (Vcg_unsel). A channel can be boosted by initially making the drain-side and source-side select gates non-conductive, to allow capacitive coupling from an increasing Vcg_unsel. The drain-side and/or source-side select gates are then made non-conductive by raising Vsgd_unsel and/or Vsgs_unsel, interrupting the boosting. Additionally boosting can occur by making the drain-side and/or source-side select gates conductive again while Vcg_unsel is still increasing. Or, the channel can be driven at Vbl. Two-step boosting drives the channel at Vbl, then provides boosting by capacitive coupling.

08-08-2013

20130223155

TEMPERATURE BASED COMPENSATION DURING VERIFY OPERATIONS FOR NON-VOLATILE STORAGE - A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.

TEMPERATURE BASED COMPENSATION DURING VERIFY OPERATIONS FOR NON-VOLATILE STORAGE - A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.

02-06-2014

20140056065

Reducing Weak-Erase Type Read Disturb In 3D Non-Volatile Memory - A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel is boosted by controlling of voltages of bit lines (Vb1), drain-side select gates (Vsgd_unsel), source-side select gates (Vsgs_unsel), a selected level (word line layer) of the memory device (Vcg_sel), and unselected levels of the memory device (Vcg_unsel). A channel can be boosted by initially making the drain-side and source-side select gates non-conductive, to allow capacitive coupling from an increasing Vcg_unsel. The drain-side and/or source-side select gates are then made conductive by raising Vsgd_unsel and/or Vsgs_unsel, interrupting the boosting. Additionally boosting can occur by making the drain-side and/or source-side select gates non-conductive again while Vcg_unsel is still increasing. Or, the channel can be driven at Vb1. Two-step boosting drives the channel at Vb1, then provides boosting by capacitive coupling.

02-27-2014

20140112075

Pre-Charge During Programming For 3D Memory Using Gate-Induced Drain Leakage - In a programming operation of a 3D stacked non-volatile memory device, the channel of an inhibited NAND string is pre-charged by gate-induced drain leakage (GIDL) to achieve a high level of boosting which prevents program disturb in inhibited storage elements. In a program-verify iteration, prior to applying a program pulse, the drain-side select gate transistor is reverse biased to generate GIDL, causing the channel to be boosted to a pre-charge level such as 1.5V. Subsequently, when the program pulse is applied to a selected word line and pass voltages are applied to unselected word lines, the channel is boosted higher from the pre-charge level due to capacitive coupling. The pre-charge is effective even for a NAND string that is partially programmed because it does not rely on directly driving the channel from the bit line end.

04-24-2014

20140133232

Compensation for Sub-Block Erase - A non-volatile memory system that has two or more sub-blocks in a block performs a check before accessing memory cells to see if the condition of a sub-block that is not being accessed could affect the memory cells being accessed. If such a sub-block is found then parameters used to access the cells may be modified according to a predetermined scheme.

05-15-2014

20140146609

Weighted Read Scrub For Nonvolatile Memory - In a nonvolatile memory array, such as a three-dimensional array of charge-storage memory cells, data is scrubbed according to a scheme which weights particular data that is exposed to potentially damaging voltages. Data that may cause damage to other data is moved to a location where such potential damage is reduced.

05-29-2014

20140149641

Optimized Configurable NAND Parameters - Configurable parameters may be used to access NAND flash memory according to schemes that optimize such parameters according to predicted characteristics of memory cells, for example, as a function of certain memory cell device geometry, which may be predicted based on the location of a particular device within a memory array.

05-29-2014

20140153333

Systems and Methods to Avoid False Verify and False Read - In a nonvolatile NAND memory array, a NAND block may be falsely determined to be in an erased condition because of the effect of unwritten cells prior to the erase operation. Such cells may be programmed with dummy data prior to erase, or parameters used for a verify operation may be modified to compensate for such cells. Read operations may be similarly modified to compensate for unwritten cells.

06-05-2014

20140169095

Select Transistor Tuning - In a nonvolatile memory array in which a select transistor includes a charge storage element, the threshold voltage of the select transistor is monitored, and if the threshold voltage deviates from a desired threshold voltage range, charge is added to, or removed from the charge storage element to return the threshold voltage to the desired threshold voltage range.

06-19-2014

20140211568

BIT LINE CURRENT TRIP POINT MODULATION FOR READING NONVOLATILE STORAGE ELEMENTS - Upon selecting non-volatile storage elements to be sensed, the system obtains information about the position of these non-volatile storage elements, determines sensing parameters based at least in part on this information, pre-charges a charge storage device and, while maintaining the voltage level of the bit lines of these memory cells at a constant value, applies a reference signal to these non-volatile storage elements for a certain duration of time, afterwards determining whether, for the certain duration of time, the current conducted by these non-volatile storage elements exceeds a predetermined value.

07-31-2014

20140219027

Programming Select Gate Transistors And Memory Cells Using Dynamic Verify Level - Programming accuracy is increased for select gate transistors and memory cells by using a dynamic verify voltage which increases from an initial level to a final level during a programming operation. Faster-programming transistors are locked out from programming before slower-programming transistors, but experience program disturb which increases their threshold voltage to a common level with the slower-programming transistors at the conclusion of the programming operation. For programming of memory cells to different target data states, an offset between the initial and final verify levels can be different for each data state. In one approach, the offset is greater for lower target data states. The increases in the dynamic verify voltage can be progressively smaller with each subsequent program-verify iteration of the programming operation. The start of the increase can be adapted to the programming progress or can be at a predetermined program-verify iteration.

08-07-2014

20140247659

REDUCING WEAK-ERASE TYPE READ DISTURB IN 3D NON-VOLATILE MEMORY - A read process for a 3D stacked memory device provides an optimum level of channel boosting for unselected memory strings, to repress both normal and weak-erase types of read disturbs. The channel is boosted by controlling of voltages of bit lines (Vbl), drain-side select gates (Vsgd_unsel), source-side select gates (Vsgs_unsel), a selected level (word line layer) of the memory device (Vcg_sel), and unselected levels of the memory device (Vcg_unsel). A channel can be boosted by initially making the drain-side and source-side select gates non-conductive, to allow capacitive coupling from an increasing Vcg_unsel. The drain-side and/or source-side select gates are then made conductive by raising Vsgd_unsel and/or Vsgs_unsel, interrupting the boosting. Additionally boosting can occur by making the drain-side and/or source-side select gates non-conductive again while Vcg_unsel is still increasing. Or, the channel can be driven at Vbl. Two-step boosting drives the channel at Vbl, then provides boosting by capacitive coupling.

09-04-2014

20140247660

Compensation for Sub-Block Erase - A non-volatile memory system that has two or more sub-blocks in a block performs a check before accessing memory cells to see if the condition of a sub-block that is not being accessed could affect the memory cells being accessed. If such a sub-block is found then parameters used to access the cells may be modified according to a predetermined scheme.

09-04-2014

20140247662

Efficient Smart Verify Method For Programming 3D Non-Volatile Memory - In a programming operation of a 3D stacked non-volatile memory device, an initial set of memory cells on a selected word line layer, involving fewer than all memory cells on a selected word line layer, are programmed first as a test case to determine optimal conditions for programming the remaining memory cells on the selected word line layer. For example, a number of program-verify iterations or loops which are needed to program the initial set of memory cells an initial amount is determined. This loop count is then stored, e.g., within the initial set of memory cells, within the remaining memory cells, within memory cells on a remaining word line layer, or in a data register, and programming of the initial set of memory cells continues to completion. Subsequently, the loop count is retrieved and used to determine an optimal starting program voltage for programming the remaining memory cells.

09-04-2014

20140247665

Select Transistor Tuning - In a nonvolatile memory array in which a select transistor includes a charge storage element, the threshold voltage of the select transistor is monitored, and if the threshold voltage deviates from a desired threshold voltage range, charge is added to, or removed from the charge storage element to return the threshold voltage to the desired threshold voltage range.

09-04-2014

20140247670

Pre-Charge During Programming For 3D Memory Using Gate-Induced Drain Leakage - In a programming operation of a 3D stacked non-volatile memory device, the channel of an inhibited NAND string is pre-charged by gate-induced drain leakage (GIDL) to achieve a high level of boosting which prevents program disturb in inhibited storage elements. In a program-verify iteration, prior to applying a program pulse, the drain-side select gate transistor is reverse biased to generate GIDL, causing the channel to be boosted to a pre-charge level such as 1.5V. Subsequently, when the program pulse is applied to a selected word line and pass voltages are applied to unselected word lines, the channel is boosted higher from the pre-charge level due to capacitive coupling. The pre-charge is effective even for a NAND string that is partially programmed because it does not rely on directly driving the channel from the bit line end.

09-04-2014

20140250266

Data Randomization in 3-D Memory - In a nonvolatile memory array, such as a three-dimensional array of charge-storage memory cells, data is randomized so that data of different strings along the same bit line are randomized using different keys and portions of data along neighboring word lines are randomized using different keys. Keys may be rotated so that data of a particular word line is randomized according to different keys in different strings.

09-04-2014

20140254283

Programming Select Gate Transistors And Memory Cells Using Dynamic Verify Level - Programming accuracy is increased for select gate transistors and memory cells by using a dynamic verify voltage which increases from an initial level to a final level during a programming operation. Faster-programming transistors are locked out from programming before slower-programming transistors, but experience program disturb which increases their threshold voltage to a common level with the slower-programming transistors at the conclusion of the programming operation. For programming of memory cells to different target data states, an offset between the initial and final verify levels can be different for each data state. In one approach, the offset is greater for lower target data states. The increases in the dynamic verify voltage can be progressively smaller with each subsequent program-verify iteration of the programming operation. The start of the increase can be adapted to the programming progress or can be at a predetermined program-verify iteration.

09-11-2014

20140269083

BIT LINE CURRENT TRIP POINT MODULATION FOR READING NONVOLATILE STORAGE ELEMENTS - Upon selecting non-volatile storage elements to be sensed, the system obtains information about the position of these non-volatile storage elements, determines sensing parameters based at least in part on this information, pre-charges a charge storage device and, while maintaining the voltage level of the bit lines of these memory cells at a constant value, applies a reference signal to these non-volatile storage elements for a certain duration of time, afterwards determining whether, for the certain duration of time, the current conducted by these non-volatile storage elements exceeds a predetermined value.

09-18-2014

20140293701

Adjusting Control Gate Overdrive Of Select Gate Transistors During Programming Of Non-Volatile Memory - In a 3D stacked non-volatile memory device, multiple smaller drain-end selected gate (SGD) transistors replace one larger SGD transistor. The SGD transistors have different control gate overdrive voltages so that, during a programming operation, a discontinuous channel potential is created in an inhibited NAND string. The SGD transistor closest to the bit line has a lower control gate overdrive voltage so that the channel potential under it is lower, and the next SGD transistor has a higher control gate overdrive voltage so that the channel potential under it is higher. The different control gate overdrive voltages can be provided by programming different threshold voltages, or by providing different control gates voltages, for the SGD transistors. Undesirable reductions in a Vsgd window due to drain-induced barrier lowering can be avoided.

10-02-2014

20140293702

Select Gate Materials Having Different Work Functions In Non-Volatile Memory - In a 3D stacked non-volatile memory device, multiple smaller drain-end selected gate (SGD) transistors replace one larger SGD transistor. The SGD transistors have different work functions in their control gates so that, during a programming operation, a discontinuous channel potential is created in an inhibited NAND string. The SGD transistor closest to the bit line has a higher work function so that the channel potential under it is lower, and the next SGD transistor has a lower work function so that the channel potential under it is higher. The different work functions can be provided by using different control gate materials for the SGD transistors. One option uses p+ polysilicon and n+ polysilicon to provide higher and lower work functions, respectively. Metal or metal silicide can also be used. A single SGD transistor with different control gate materials could also be used.

10-02-2014

20140351496

Optimized Configurable NAND Parameters - Configurable parameters may be used to access NAND flash memory according to schemes that optimize such parameters according to predicted characteristics of memory cells, for example, as a function of certain memory cell device geometry, which may be predicted based on the location of a particular device within a memory array.

11-27-2014

20140355344

Adaptive Operation of Three Dimensional Memory - When data from a portion of a three dimensional NAND memory array is determined to be uncorrectable by Error Correction Code (ECC), a determination is made as to whether data is uncorrectable by ECC throughout some unit that is larger than the portion. If modified read conditions provide ECC correctable data, the modified read conditions are recorded for subsequent reads of the larger unit.

12-04-2014

20140355345

Adaptive Operation of Three Dimensional Memory - When data from a portion of a three dimensional NAND memory array is determined to be uncorrectable by Error Correction Code (ECC), a determination is made as to whether data is uncorrectable by ECC throughout some unit that is larger than the portion. If modified read conditions provide ECC correctable data, the modified read conditions are recorded for subsequent reads of the larger unit.

12-04-2014

20140359398

Selection of Data for Redundancy Calculation in Three Dimensional Nonvolatile Memory - Portions of data stored in a three dimensional memory array are selected based on their locations for calculation of redundancy data. Locations are selected so that no two portions in a set of portions for a given calculation are likely to become uncorrectable at the same time. Selected portions may be separated by at least one word line and separated by at least one string in a block.

12-04-2014

20140359400

Selection of Data for Redundancy Calculation in Three Dimensional Nonvolatile Memory - Portions of data stored in a three dimensional memory array are selected based on their locations for calculation of redundancy data. Locations are selected so that no two portions in a set of portions for a given calculation are likely to become uncorrectable at the same time. Selected portions may be separated by at least one word line and separated by at least one string in a block.

12-04-2014

20140362641

Program And Read Operations For 3D Non-Volatile Memory Based On Memory Hole Diameter - Techniques are provided for programming and reading memory cells in a 3D stacked non-volatile memory device by compensating for variations in a memory hole diameter. The memory hole diameter is smaller at the bottom of the stack, resulting in more severe read disturb. To compensate, programming of memory cells at the lower word line layers is modified. In one approach, threshold voltage (Vth) distributions of one or more data states are narrowed during programming so that a lower read pass voltage can be used in a subsequent sensing operation. A sufficient spacing is maintained between the read pass voltage and the upper tail of the highest data state. The Vth distributions can be downshifted as well. In another approach, the read pass voltage is not lowered, but the lowest programmed state is upshifted to provide spacing from the upper tail of the erased state.

12-11-2014

20140362642

3D Non-Volatile Memory With Control Gate Length Based On Memory Hole Diameter - A structure and fabrication process are provided for a 3D stacked non-volatile memory device which compensates for variations in a memory hole diameter. The memory hole diameter is smaller at the bottom of the stack, resulting in more severe read disturb. To compensate, the word line layers are thicker at the bottom of the stack and can increase gradually from the bottom to the top of the stack. As a result, the length of the control gates of the memory cells is greater at the bottom of the stack. The capacitance between the control gate and a charge trapping layer increased in proportion to the length of the control gates. During programming, a narrower threshold voltage (Vth) distribution is achieved for these memory cells. The Vth distributions can be placed closer together and downshifted to allow lowering of a read pass voltage in a subsequent sensing operation, reducing read disturb.

12-11-2014

20140362645

3D Non-Volatile Memory With Control Gate Length Based On Memory Hole Diameter - A structure and fabrication process are provided for a 3D stacked non-volatile memory device which compensates for variations in a memory hole diameter. The memory hole diameter is smaller at the bottom of the stack, resulting in more severe read disturb. To compensate, the word line layers are thicker at the bottom of the stack and can increase gradually from the bottom to the top of the stack. As a result, the length of the control gates of the memory cells is greater at the bottom of the stack. The capacitance between the control gate and a charge trapping layer increased in proportion to the length of the control gates. During programming, a narrower threshold voltage (Vth) distribution is achieved for these memory cells. The Vth distributions can be placed closer together and downshifted to allow lowering of a read pass voltage in a subsequent sensing operation, reducing read disturb.

12-11-2014

20150063028

Bad Block Reconfiguration in Nonvolatile Memory - When a bad block is found in a nonvolatile memory array, the block is marked as a bad block so that it is not subsequently used. The block is also reconfigured as a bad block by increasing resistance of vertical NAND strings in the block by increasing threshold voltage of at least some transistors along vertical NAND strings, for example, select transistors or memory cell transistors.

03-05-2015

20150063033

Selective Word Line Erase In 3D Non-Volatile Memory - An erase process for a 3D stacked memory device allows a portion of a block of memory cells to be erased. In one approach, in a U-shaped NAND string configuration, memory cells in the drain- or source-side columns are erased. In another approach, such as in a U-shaped or a straight NAND string configuration, memory cells in a portion of a column of memory cells are erased, and a dummy memory cell is provided between the erased and non-erased memory cells. A dummy memory cell can be on either side (e.g., above and below) of an erase memory cell, or on either side of a non-erased memory cell. A dummy memory cell is ineligible to store user data, but prevents a downshift in the threshold voltage of an erased memory cell from changing the threshold voltage of a non-erased memory cell, due to capacitive coupling.

03-05-2015

20150067419

Bad Block Reconfiguration in Nonvolatile Memory - When a bad block is found in a nonvolatile memory array, the block is marked as a bad block so that it is not subsequently used. The block is also reconfigured as a bad block by increasing resistance of vertical NAND strings in the block by increasing threshold voltage of at least some transistors along vertical NAND strings, for example, select transistors or memory cell transistors.

03-05-2015

20150070998

VREAD BIAS ALLOCATION ON WORD LINES FOR READ DISTURB REDUCTION IN 3D NON-VOLATILE MEMORY - Techniques are provided for sensing memory cells in a 3D stacked non-volatile memory device in a way which reduces read disturb, by using read pass voltages which are adjusted based on variations in a memory hole diameter. The memory cells are in NAND strings which extend in the memory holes. A larger read pass voltage is used for memory cells which are adjacent to wider portions of the memory holes, and a smaller read pass voltage is used for memory cells which are adjacent to narrower portions of the memory holes. This approach reduces the worst-case read disturb. Further, an overall resistance in the NAND string channel may be substantially unchanged so that a reference current used during sensing may be unchanged. The read pass voltage may be set based on a program voltage trim value, which is indicative of programming speed and memory hole diameter.

03-12-2015

20150085574

Back Gate Operation with Elevated Threshold Voltage - In a three dimensional NAND memory, increased threshold voltages in back gate transistors may cause program failures, particularly along word lines near back gates. When back gate transistor threshold voltages cannot be returned to a desired threshold voltage range then modified program conditions, including increased back gate voltage, may be used to allow programming.