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Partial-Parallel Decoders A subset of check and variable nodes are implemented in hardware Processing of the whole matrix done by changing interconnection between implemented nodes A network of muxes is utilized This interconnection network results in: Hardware overhead 1344 x 4:1 muxes for a (672,588) LDPC code High power dissipation All muxes toggle over every cycle Decline in throughput In critical path of the signals 3

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Contribution A new decoding scheme is proposed Based on matrix structure of codes in IEEE 802.15.3c and 802.11ad Results in almost complete elimination of logic gates on routing network of the decoder Improvement in area, power and throughput No degradation in BER performance Class of matrices the method can be utilized for is defined Results for (672,588) LDPC code adopted in IEEE 802.15.3c are presented 4

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Valid Mapping Assume a partitioning on columns along layers on rows A mapping from column groups of layer L1 to column groups of layer L2 is called valid if: 1) It is one-to-one, 2) It maps every non-zero submatrix in layer L1 to an equal or an all-zero submatrix in layer L2, 8 Column groupSubmatrix - MP valid from Layer 1 to Layer 2

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Permutational Matrix We call a parity-check matrix permutational if there exists a mapping and a sequence of all its layers such that the mapping is valid: Between consecutive layers in the sequence. From last layer to the first layer of the sequence. 9 Sequence = 1,2,3,4

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Characteristics of the architecture Number of implemented CN’s: number of row in a layer (M l ) Number of implemented VN’s: number of columns (U x N c ) Almost no gates are needed in the routing network, only a constant wiring network is used. No need for shifting outputs or check node messages Outputs can be registered at the end of last cycle in each iteration R i,j values are registered internally The complexity of overall routing network is not dramatically changed. The shifting network and the connection network based on L max are in series, and can be assumed as one overall routing network, comparable to any other v-to-c routing network in regular partial-parallel decoders, but with no gates. No effect on BER 16

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Conclusion A new LDPC decoding technique is presented and the class of codes the method can be utilized for is defined. The technique is implemented for (672,588) code adopted for IEEE 802.15.3c. The new architecture reduces the gates on the routing network of the decoder from 1344 4:1 muxes to 126 2:1 muxes. The decoding technique results in 30% improvement in throughput and 24% decrease in area, with no effect on BER performance. 20