I immediately jumped to the easy answer, i.e. how more bandwidth is desired across many segments of the market today, ergo JESD204B. The tougher answer to that question revolves, I believe, around interleaved ADC converters. When ADC converters are interleaved, two or more ADC converters with a defined clocking relationship are used to simultaneously sample an input signal and produce a combined output signal that results in a sampling bandwidth at some multiple of the individual ADC converters.

Interleaved ADC converters are definitely part of the push to a more efficient interface. Interleaved ADC converters offer several advantages to system designers. However, with the extra converter bandwidth comes a large amount of data that needs to be processed in an FPGA or ASIC. There has to be some efficient way to get all that data from the converter processed. It becomes impractical to continue using an LVDS interface in converters with sample rates in the gigasample range. So JESD204B is a nice, efficient way to get the large amount of data from the converter to an FPGA or ASIC.

Let's take a moment to step away from the interface though and look at interleaving for a moment. In communications infrastructure there is constantly a push for higher sample rate ADCs to allow for multi-band, multi-carrier radios in addition to wider bandwidth requirements for linearization techniques like DPD (digital predistortion). In military and aerospace, higher sample rate ADCs allow for multi-purpose systems that can be used for communications, electronic surveillance, and radar just to name a few. In industrial instrumentation, the need is always increasing for higher sample rate ADCs so that higher speed signals can be measured accurately. Let's begin this discussion by taking a look at the basics of interleaved ADCs.

Utilizing m number of ADCs allows for the effective sample rate to be increased by a factor of m. For the sake of simplicity and ease of understanding, let's just focus on the case of two ADCs. In this case, if two ADCs with each having a sample rate of fS are interleaved, the resultant sample rate is simply 2fS. These two ADCs must have a clock phase relationship in order to interleave them properly. The clock phase relationship is governed by equation 1, where n is the specific ADC and m is the total number of ADCs.

As an example, two ADCs each with a sample rate of 250MSPS are interleaved to achieve a sample rate of 500MSPS. In this case, equation 1 can be used to derive the clock phase relationship of the two ADCs and is given by equations 2 and 3.

Now that we know the clock phase relationship, the construction of samples can be examined. Figure 1 gives a visual representation of the clock phase relationship and the sample construction of two 250MSPS interleaved ADCs.

Figure 1

Two Interleaved 250MSPS ADCs – Basic Diagram

Notice the 180° clock phase relationship and how the samples are interleaved. The input waveform is alternatively sampled by the two ADCs. In this case, the interleaving is implemented by using a 500MHz clock input that is divided by a factor of two. The divider takes care of sending the required phases of the clock to each ADC.

Another representation of this concept is illustrated in Figure 2.

Figure 2

Two Interleaved ADCs – Clocking and Samples

By interleaving these two 250MSPS ADCs, the sample rate is increased to 500MSPS. This extends width of the converter's Nyquist zone from 125MHz to 250MHz, doubling the available bandwidth in which to operate. The increased operational bandwidth brings many advantages. Radio systems can increase the number of supported bands; radar systems can improve spatial resolution, and measurement equipment can achieve greater analog input bandwidth.

Hi Sunita, these are good questions. The upper limit is bounded by several factors. For ease of understanding the most basic limit is the accuracy of your phase created for each of the n clocks used to interleave n converters. As n goes higher the phase delta between converters becomes smaller and the impact of any error becomes larger. As Brad alluded too there are many (proprietary) techniques that can be use to account for errors. Stay tuned for more on interleaved converters and the gotchas to be aware of...

I think that problems such as error and gain matching would be minimized when placing two or more ADCs into same die. I do not know if ADI Blackfin or SHARC feature interleaved ADCs internally. Some DSCs (Digital Signal Controllers) have multiple ADC / Sample & Hold in MSa/s range. The first idea that comes to mind is to use them to acquire different signals simultaneously - for example, in order to calculate the Power is necessary to measure the Current and Voltage with no delay between. Conversely, we can join two such independent converters to create an interleaved converter; so that a single signal would be sampled at a higher rate with an appropriate software. Ex., most ADCs in microcontrollers can be triggered directly by a timer that, ultimately, is the generation of those 2*pi*(n-1)/m phase shifts.

ADC by itself have issues like DC offset, quantization error. Along with these issues, interleaved ADC's gain and phase needs to be matched. Is it possible to match the behaviour of interleaved ADC's using feedback system ? Can we use digital assisted analog where digital processor analyse the data from interleaved ADC's and provide the feedback.

As Jonathan noted, there are other details to deal with. He will probably discuss the importance of getting the interleaving timing just right so that the conversion is accurate. Timing skew and jitter are your enemies here. And there are propriatary (in fact, highly propriatary) techniques that different companies promote to address this issue.

Hi Derek, that is correct. In order to get larger bandwidths for measurement equipment such as oscilloscopes ADCs can be interleaved together. There are things to watch out for though...(look for future blog posts to find out more).

Is this not how most digital oscilloscopes operate? It would make intuitive sense that if there is a limit on the speed of the ADC, interleaving multiple ADCs would increase the effective sampling? Thus, it comes down to how fast one can pull data from the multitude of ADCs to process, and to store / display the waveform - the digital side of the system.

A device going into space must be much more rigorously evaluated than a device going into a commercial product. Hence the need to do a good deal more characterization and ‘proving out’ of the device to make sure that it will endure the harsh environment in space as well as the long lifetimes required.

Now that we’ve had a chance to learn a bit about the tool we will take a look at using Virtual Eval to predict the performance of the AD9680-500 which has integrated digital downconverters (DDCs) and will compare simulated data to measured data.