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On Mar 10, 2:51 pm, Benjamin Couillard <>
wrote:
> Hi everyone,
>
> I was wondering if I can do the following in VHDL :
>
> my_process : process(CLK)
> begin
> if rising_edge(CLK) then
> if (load_reg = '1') then
> assert unsigned(DATA) > 10
> report "error, DATA must be greater than 10"
> severity error;
> end if;
> end if;
> end process;
>
> I've tried the following code in Active-HDL, and no assertions were
> triggered in simulation even though there should have. Is it supposed
> to trigger? Is there another way to write that assertion?
>
> Best regards

Theres nothing wrong with the code. I can only assume that DATA is
greater than 10 whenever the process triggers. Or load_reg = '0'.

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On 10 mar, 10:17, Tricky <> wrote:
> On Mar 10, 2:51 pm, Benjamin Couillard <>
> wrote:
>
>
>
>
>
>
>
>
>
> > Hi everyone,
>
> > I was wondering if I can do the following in VHDL :
>
> > my_process : process(CLK)
> > begin
> > if rising_edge(CLK) then
> > if (load_reg = '1') then
> > assert unsigned(DATA) > 10
> > report "error, DATA must be greater than 10"
> > severity error;
> > end if;
> > end if;
> > end process;
>
> > I've tried the following code in Active-HDL, and no assertions were
> > triggered in simulation even though there should have. Is it supposed
> > to trigger? Is there another way to write that assertion?
>
> > Best regards
>
> Theres nothing wrong with the code. I can only assume that DATA is
> greater than 10 whenever the process triggers. Or load_reg = '0'.

Ok, I found out what the problem was. I was using variables instead of
signals in the assert statement (I simplified my statement a bit to
make it easier to understand) and I didn't realize that it would solve
the problem.

On Mar 10, 7:20 am, Benjamin Couillard <>
wrote:
> On 10 mar, 10:17, Tricky <> wrote:
>
>
>
>
>
>
>
>
>
> > On Mar 10, 2:51 pm, Benjamin Couillard <>
> > wrote:
>
> > > Hi everyone,
>
> > > I was wondering if I can do the following in VHDL :
>
> > > my_process : process(CLK)
> > > begin
> > > if rising_edge(CLK) then
> > > if (load_reg = '1') then
> > > assert unsigned(DATA) > 10
> > > report "error, DATA must be greater than 10"
> > > severity error;
> > > end if;
> > > end if;
> > > end process;
>
> > > I've tried the following code in Active-HDL, and no assertions were
> > > triggered in simulation even though there should have. Is it supposed
> > > to trigger? Is there another way to write that assertion?
>
> > > Best regards
>
> > Theres nothing wrong with the code. I can only assume that DATA is
> > greater than 10 whenever the process triggers. Or load_reg = '0'.
>
> Ok, I found out what the problem was. I was using variables instead of
> signals in the assert statement (I simplified my statement a bit to
> make it easier to understand) and I didn't realize that it would solve
> the problem.

I thought variables can only be declared in processes and thus their
scope
only extends to the process they're declared in? So then by your
example
my_process should not have been able to see DATA or load_reg,
whichever was
declared as a variable. Could you post the non-simplified code? I'm
curious.

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