Maybe you can use the "LPC5410x PLL setup example" that comes with the LPC54102 LPCOpen package as reference, this example shows how to setup and use the clock driver to generate different PLL rates at run-time. Will switch the main system clock to the safe (IRC) clock, set a new PLL frequency, and then the main system clock to the PLL.

When the reference frequency of the PLL is 32 kHz (i.e. <= 500 kHz) you cannot rely on the lock bit anymore. Instead you should simply wait for a minimum time after enabling the PLL before using its output clock.

The user manual gives a formula in chapter 4.6.4.5.1 for the minimum time to wait when a 32 kHz reference is used (> 6.1 ms). However, I recommend to wait much longer (100 ms at least). The reason is that the 6.1 ms assumes the settings for SELI/SELP/SELR in the PLL control registers are calculated as per the formulas given for the SYSPLLSSCTRL0 register. A remark for 32 kHz operation has been added to the user manual at a later date, recommending fixed values for the SELx fields. These fixed values set a much narrower loop bandwidth, leading to noticeably increased settling time.

P.S.: You define the board clock frequency as "32768000". This is 32.768MHz. Doesn't seem right to me.

P.S.2: Note that the fixed settings for SELx assume you are using the built-in RTC oscillator. This oscillator has significant jitter, which leads to the PLL becoming unstable and losing lock if the calculated SELx filter coefficients are used.

In the unlikely case of applying an external low-jitter reference via CLKIN, using the calculated SELx values is allowed, and a settling time of 6.1 ms may be assumed. I guess this is not your application setup though...