OverviewIn this hands-on workshop, you will learn to use IC Compiler to perform placement, clock tree synthesis (CTS), routing, and design-for-manufacturability (DFM) on non-UPF block-level designs with an existing floorplan. The covered flows are aimed at achieving design closure for designs with moderate congestion, and multi-corner multi-mode (MCMM) timing and power challenges.

Day 1: Introduces the GUI, then covers data setup for concurrent MCMM optimization, including on-chip variation (OCV) effects, followed by a high-level overview of floorplanning.

Day 3: The Routing Unit covers; control setup, clock and signal routing, post-route optimization, DRC fixing, and functional ECOs. The workshop concludes with DFM and data generation for final validation.

The workshop is based on Synopsys'Reference Methodology (RM) flow. Every lecture is accompanied by a comprehensive hands-on lab.

Objectives

At the end of this workshop you should be able to use IC Compiler to:

Use the GUI to analyze the layout during the various design phases

Perform and debug data setup to create an initial design cell which is ready for design planning and placement; This includes loading required files and libraries, creating a Milkyway design library, and applying common timing and optimization controls

Audience Profile
ASIC, back-end, or layout designers who will be using IC Compiler to perform placement, CTS, and routing on block-level designs

Prerequisites
While prior knowledge of IC Compiler is not needed, knowledge of general (non-tool specific) standard cell-based placement, CTS, and routing concepts and terms is helpful.
An understanding of basic digital ASIC design concepts is assumed, including:

Combinational and sequential logic functionality

Setup and hold timing

Must be able to use a text editor (vi, vim, emacs) in a UNIX environment.