Friday, January 4, 2013

So I've read up a bit on the newest SystemVerilog standard, SV 2012. There are a few simple things I like:
You can now call new from another object.
In SV 2009:
class cl_base;
...
endclass
class cl_ext extends cl_base;
...
endclass

So now I want to instantiate a cl_ext and point to it with a cl_base pointer.
Some people will code this verbosely:
cl_base cl_b_inst;
cl_ext cl_e_inst = new();
cl_b_inst = cl_e_inst;

Now onto the next improvement that I am excited about: Multiple Inheritance! The new SV 2012 now supports multiple inheritance by using an interface class. Don't know how that works as I haven't used it yet.

or something like that... This might work with a function, but I do believe that SystemVerilog still doesn't support unconstrained types for a function.

Generate statements in a class:
SV supports parameters in a class, but it won't allow for generate statements in a class. This is both unexpected, and annoying. If parameters are allowed appear identical to parameters for a module or interface, then they should behave more or less the same!

Wildcard connections of parameters. It would've helped me today.

I know there is something I want having to do with clocking blocks... One second, I have to find it...
So I want some indication of when a clocking block updates a signal. See forum post for more information.