What next for IC materials?

By Chris Edwards

Published Monday, October 22, 2012

For 50 years, silicon has been the material of choice for making integrated circuits; but some say that it's been living on borrowed time - and chipmakers are developing innovative new material bases for future processors.

By itself silicon is actually not all that great a semiconductor. To do anything useful it has to be mixed with other elements to change its properties; but by adding other elements to the crystal lattice it is possible to improve silicon's performance, not just making it more conductive to pass electrons much more easily, but to actively block them as well.

For the past 10 years, chipmakers like Intel have been adding materials such as germanium under the silicon in the channel of each transistor - the heart of each of the billions of logic devices inside today's processors. The larger germanium atoms stretch the silicon lattice to let electrons move more easily.

"The majority of performance gains are now coming from materials and materials engineering," said Mike Mayberry, Intel's director of components research, at the VLSI Technology and Circuits Symposium in Honolulu last June. The use of more materials is not all good news. 'Doping' silicon with elements such as boron - to make the material electron-light - or phosphorus - for the opposite effect, sounds quite a gentle process. In practice, however, it is far from being the case. Implantation means firing high-energy ions into the silicon substrate, breaking the crystal lattice. Rapid heating and cooling helps mend the lattice - and as it does so the ions settle into place, but not necessarily the right place.

You wind up with dopant ions that roughly follow a statistical distribution, so that their concentration falls away rapidly from where the hard mask let them through during implantation. The dopants are placed randomly, however.

Under a transistor gate that is 100nm long, there are thousands of dopant ions that collectively tune the device to switch at the right voltage. The drawback here is that as the gate and the other dimensions shrink to where they are today, that number drops rapidly to the point where the number of dopants is counted in tens rather than thousands.

Trigate and SOI structures

Researchers such as Professor Asen Asenov of the University of Glasgow have long-warned how the fall in dopant numbers increases the variability of transistors. Just a few poorly-placed ions can cause the transistor's threshold voltage - the point at which it switches from off to on - to move so far that the device simply fails.

The manufacturers cannot easily move away from doping because it is a critical component in making ultra-small transistors work. The gate on top of the channel uses changes in voltage to either stop electrons passing through the channel or allow them through. The dopants not only alter conductivity, they also help focus the carriers into a thin band in the channel, which otherwise would reach deep into the silicon substrate and out of the gate's influence.

Instead of a switch, you would simply have a valve that moves between fully open and slightly less open. The response has been to begin to change the structure of the transistor to make undoped channels feasible. The reason chipmakers have been so reluctant to make this move is that the transistors are much more difficult to make than conventional devices.

Some companies favour ultra-thin body silicon-on-insulator (SOI) structures. As the name suggests, a sliver of silicon is laid on top of a thick insulating oxide, which cuts-off the transistor from the rest of the wafer. STMicroelectronics aims to use this technology in forthcoming mobile phones because it consumes less power than comparable 'bulk silicon' designs, at the cost of some performance.

Intel is, to date, alone in making chips based on the trigate or finFET structure, which turns the transistor on its side so that the gate can be wrapped around three sides of the channel. Silicon foundries such as GlobalFoundries and TSMC are working on their own finFET processes that should arrive within the next three or four years, possibly earlier.

"The ultimate scaling at least from the electrostatics point of view would be to make a very narrow diameter channel and then surround it with the gate," says Mayberry.

The trigate and SOI structures provide an improvement but there are limits to how far they can go before silicon needs another helping hand. Simply doping the channel is not going to help as this brings back the variability.

One answer is to give silicon the heave-ho and use something else in its place. When transistors first appeared, they were made using germanium, a material through which electrons move much more easily than through silicon. Similarly, the Group III and V elements such as gallium and arsenic used in the power amplifiers of mobile phones offer similar advantages.

"The main advantage of III-V channel materials is their high mobilitya 30-fold improvement over silicon," says Intel engineer Gilbert Dewey. The world's biggest chipmaker first started work on CMOS transistors based on III-V materials more than 10 years ago, teaming up with UK-based Qinetiq. Not only do electrons move more easily through the materials, they travel more quickly"A five-times increase in effective velocity over silicon," Dewey claims.

The trouble with III-V devices as a number of research teams have found so far is that the core transistor works well but the source and drain interfaces are not so good. High resistance slows them down. "[As things stand] silicon CMOS still wins," adds Mayberry. "We expect to surpass this."

There is another way to obtain the advantages promised by III-V materials, and to improve not just speed but energy consumption. Professor Tsu-Jae King Liu of the University of California at Berkeley, who worked on early generations of the finFET architecture, says: "With Moore's Law we have been able to improve the speed of computing and have lower power - but a large part of the market is going to grow in very, very low-power devices that could be embedded in our environment and within us. Energy efficiency is going to be very important."

The leakage that plagues today's transistors is a result of the way they work. Electrons need to have enough energy to easily break free of their bonds and move through the channel once the right voltage is applied to shove them on their way. Much of this required energy comes from heat. Unfortunately, some are energetic enough to make it through with very little help - the result is unwanted subthreshold leakage current. Ideally, when the voltage is below the threshold, there should be no current flow at all.

FET feats

One way around this is to not rely on thermally excited electrons at all and use a different kind of device. One candidate is the tunnel FET. This design uses changes in voltage to move around the energy bands in different layers of semiconductor - using a so-called 'heterojunction' design. When they are close enough together, electrons can tunnel from one layer to another. Electrons do not have to be in conduction bands to move. "They can tunnel from the valence to the conduction band," explains Dewey.

The concept underlying the tunnel FET was discovered in the late 1950s, but even now working devices prove elusive. Dewey says the promised lower leakage has yet to become a reality, largely because it is hard to make small but reliable transistors. And they do not pass much current when switched on, which reduces their effective speed.

Katsuhiro Tomioka of Hokkaido University is confident that tunnel FETs can be made to work reliably and that one direction in manufacturing - which will see the finFET mutate into a nanowire in which the gate is wrapped around the entire silicon channel - will help. "Once we are able to grow nanowires on silicon without dislocation we can use that for heterojunctions," says Tomioka. "We will be able to fit them into the CMOS process."

There is another way to get around the leakage problem: it is to move away from the idea of a solid-state switch. According to University of California's Prof King Liu: "A mechanical switch has zero current when it is switched off."

In an environment where solid-state technology has delivered incredible gains in density and performance, making a computer out of mechanical switches seems fanciful; but it is feasible thanks to an extension of the microetching technology used to build solid-state transistors. Microelectromechanical machine systems (MEMS) technology makes it possible to put billions of tiny moving bars into a chip. These bars work in the same way as a much larger relay: the bar is pulled shut by electrostatic forces generated by the gate.

Conceptually, you would expect the bar to snap after millions of up-down movements over its life, but "the displacement is usually very small. So fatigue is not an issue", says King Liu. "Endurance is limited by diffusion at the contact. The relay contact heats up and, eventually, the atoms move so much that the device fails: it welds shut."

Cycle upper limits

The Berkeley researchers have pushed endurance to a quadrillion cycles. This is not enough for a computer to run round the clock for more than a few weeks, but does fit the very low-power processors that go into energy meters and wireless sensors. These sensors have circuits that spend 99 per cent of their time doing nothing. A quadrillion cycles lets one wake up periodically, crunch out computations at 100MHz before going to sleep, over a period of 10 years or more.

Because of the time it takes to switch on and off, a clock speed of more than a few hundred megahertz looks unlikely. The switches are also much bigger than 2012's transistors although changes in design could improve density. As a result, the nanorelays are unlikely to make it into the core processors in devices such as tablet PCs and mobile telephones.

Spun not charged

Instead, the next step from silicon, if tunnel FETs do not work, will be to go to devices based on materials such as graphene that use other quantum-mechanical effects or the spin of electrons, rather than their charge. The problem for the spin-based devices versus current charge-based transistors is how fast they can deliver information.

"Ballistic spin transport is a lot slower than for charge. But for some distances, it will beat diffusion for electrons and phonons," says Intel's Mayberry. "We need to consider how to change our circuits to achieve the maximum potential of our devices."

Before this happens, Mayberry warns, other things need to change to make sure traditional transistor structures based on electron charge can deliver information to other parts of the chip quickly.

All future devices are all limited by the wiring that connects them, Mayberry explains. "As you go to more vertical devices it becomes hard to make connections. It's also a challenge for creating precise materials, especially as the materials in interconnect aren't always crystallisedit's hard to predict precise properties.

Scaling is not just a problem in the core transistors: "You get more resistance because you have less space for copper. So, the resistance goes up dramatically as you get to smaller and smaller dimensions," Mayberry adds.

A lot of the resistance is caused by electrons bouncing-off the surfaces between the many metal crystals that make-up a typical wire - they are lost through the scattering. Known materials, such as carbon nanotubes for instance, offer the prospect of ballistic interconnect in which electrons travel unimpeded by this scattering, but unfortunately, we do not yet know how to build this.