Prop2 FPGA files!!! - Updated 2 June 2018 - Final Version 32i

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Okay, I'll eat my words on that point. It would appear I wasn't careful enough on the reader comparison. I'm getting an easy sustained 65+ MB/s using the other good reader.

Thanks for the nudge. Saves me making a fool of myself tomorrow!

I'm guessing there is a power problem. I do have trouble getting cards to even register sometimes. The third reader I mentioned only detects some SD cards. It's fine for CF cards, they have a sturdy connector.

Here's the graphs using the second card reader. Left most blob is the Kingston SD card writing six files totalling almost 12 GB. Middle blob is the Sandisk SD card writing the same six files. And finally the second piccy has the 10 GB block write to the Sandisk card.

Yeah, looks like the USB controllers/bridges are partly to blame here. After a power cycle of the whole PC, things are more alive. It's no faster but I've got that third card reader, the 5.25" bay, back in action and more all round seems to work. So there was some bugginess along the device chain getting in the way before. I'm slightly suspicious of the first card reader, the Kingston, on top of the PC, reader being the cause. See photo below.

The USB cables are quite chunky. I feel they're okay. The 5.25" bay power is from a 5.25" FDD/HDD power plug.

It's becoming notable that some readers are marked as USB3 SuperSpeed but cap out at a flat 40 MB/s. Which is better than what USB2 devices ever achieved in practice but that's before it got a performance bump late in the piece. This applies to the Silverstone 5.25" bay card reader and also the Mbeat reader - another card reader I just found.

The only card reader that provides full speed sustained is the small Transend reader in the left most USB socket of the bay.

Yeah, looks like the USB controllers/bridges are partly to blame here...

Hi evanh

I'm seeing that you're using the front-panel accessible USB ports of your pc.

Despite the convenient reaching of front-panel accessible USB connectors, at least in my home pc setup, there is some evidence of bad transfer rates, just at those connectors, e.g., when I use a external hd (USB-2 and USB-3). Also, sometimes, either external hd fails to be properly recognized, when connected to any of the front-panel USB ports.

Most of the times, changing the USB port where the drive was initialy connected, at the front-panel, is enough to resolve the recognization issue, though that procedure does not solve the poor transfer rate issues, never.

By attaching the external drives (I have two, so I was able to test them, independently) to any of the rear-panel accessible USB ports (at my systerm, the ones that are directly soldered to the motherboard, without intervening cables or connectors, inside the hood) they ever displayed better sustained transfer rates and never fail to be recognized, at first try.

Sure, I know that external HDs would consume a lot more power than any USB-enabled SD card reader, an that fact could explain the difficulty of recognizing it, but, perhaps, it helps trying your system's back-panel USB ports, at least to check for any difference in the transfer rates, as I have noticed on my system's operation.

Henrique,
Ah, these ones are a little different to what you have. Note it fills a 5.25" bay. There is a 5.25" power plug powering that bay unit. Inside, the two USB3 ports of the internal plug from the motherboard will be used independently:
- One will be just for the low grade card reader slots. Would have been nice if these were faster.
- The other will be feeding a USB3 hub controller chip which splits out to the three blue USB sockets. The fourth red socket is just a charging port.

So, strong power and USB controller is direct PCB to those blue USB sockets.

The two blue USB sockets in the case above the DVD drive are not plugged in internally. Mainly because the motherboard only has one USB3 internal socket. If they had a USB2 internal plug then I would have used them.

"There's no huge amount of massive material
hidden in the rings that we can't see,
the rings are almost pure ice."

Many thanks by having it explained to me. Truly different from the ones under my possession.

As I only had the photo you've posted as an input, I'd almost immediately tryed to relate it to my younger system (the better one, if it can be called in such way; Prince Retard, The Sequel). I also have another one, a trully ancient (fourteen y. o.) Asus/Amd; (King Retard, The First).

The simple fact they are yet able to power-on and boot is a daily surprise, as a double yolk egg, extra bacon, for the breakfast.

I haven't noticed Chip online for several days now and he hasn't come back with any reports which probably means he's still buried in sims with On Semi and they haven't proceeded to tapeout yet. I hope it's not like the P2HOT scenario though although I doubt it since the full FPGA version runs from a USB port and dedicated silicon will fare far better. However it is probably wise not to jump to or discuss possible conclusions, just wait as I'm sure we will hear back this week.

I've kind of been on summer vacation while On Semi finishes up the simulations.

As of today, we checked the waveforms from the final simulations and everything looks perfect.

They're going to have some paperwork for me to sign on Friday and tape-in in will proceed on Monday. After DRC checks on the mask data, tape-out will happen and we will be on the way to getting chips built. I think it will take 15 weeks before we see chips.

We did some worst-case power checks. These were under fastest process conditions, highest voltage, and lowest temperature. The results are probably 50% in excess of what anybody will ever see. I wrote a program which enabled all smart pins in PWM mode, all cogs, and all hub FIFO's. Also, each cog issues a CORDIC command every 16 clocks. The power came in at 2.05 Watts. Leakage was only 134ua. These numbers are way better than what the tool was estimating, based on 20% toggling.

I've kind of been on summer vacation while On Semi finishes up the simulations.

As of today, we checked the waveforms from the final simulations and everything looks perfect.

They're going to have some paperwork for me to sign on Friday and tape-in in will proceed on Monday. After DRC checks on the mask data, tape-out will happen and we will be on the way to getting chips built. I think it will take 15 weeks before we see chips.

We did some worst-case power checks. These were under fastest process conditions, highest voltage, and lowest temperature. The results are probably 50% in excess of what anybody will ever see. I wrote a program which enabled all smart pins in PWM mode, all cogs, and all hub FIFO's. Also, each cog issues a CORDIC command every 16 clocks. The power came in at 2.05 Watts. Leakage was only 134ua. These numbers are way better than what the tool was estimating, based on 20% toggling.

We did some worst-case power checks. These were under fastest process conditions, highest voltage, and lowest temperature. The results are probably 50% in excess of what anybody will ever see. I wrote a program which enabled all smart pins in PWM mode, all cogs, and all hub FIFO's. Also, each cog issues a CORDIC command every 16 clocks. The power came in at 2.05 Watts. Leakage was only 134ua. These numbers are way better than what the tool was estimating, based on 20% toggling.

Great news - do you have exact applied voltages, and MHz used for this test, and the mA from each rail ?
What was the 3v3 Pin toggle rate in this test ? is that 62 ? 60 ? pins in PWM ? ( 60! PWMs is certainly going to get people's attention !)

'Lowest temp' is not going to stay lowest for very long at 2W - how much does Icc vary with temperature ?

Was that 134uA leakage the worst case value, or the one at lowest temp ?

Leakage is lower than expected, we can easily battery back that for security, and that xcl220 regulator jmg found to looks possible

Yes, very good news.

Those numbers also mean the 1A+ Linear regulators can be looked at, knowing they will handle the peak numbers. It's then up to users to mostly sleep, to keep average thermal envelope still ok for linear regulators.'
This makes the ST LDL1117 I've suggested a particularly good fit for linear regulator choices, not pushing the envelope. Series diodes can be added to spread the power footprint. eg SMB 2A are low cost
SMPS would be used for very top end, or someone wanting to stay inside the 500mA USB limit.