Next week, DVCon is once again in Europe, October 19-20 in Munich. A marvelous agenda has been laid out for this year’s 2-day conference, including three keynoters that pretty much sum up the state of things in the industry here in 2016. If you want to know where to apply your resources – both human and material – over the next decade, look no farther than these three talks.

It’s a tiring trip from Silicon Valley to Bavaria, but the quality of these presentations, combined with the rest of the content at DVCon Europe, will make the trip well worth the effort. Hope you’re going.

* ARM’s Hobson Bullman will be speaking about the focus on design and verification in ARM’s Technology Services Group.

“As the world leader in semiconductor IP, ARM supplies technology that’s at the heart of billions of new devices manufactured every year.

“In order to make that possible, ARM has enabled an engineering infrastructure and workflow group to support the compute and tooling needs of ARM, called Technology Services Group, which enables and develops best practice and promotes effectiveness, understanding and continuous improvement.

“TSG tools and services are used by ARM engineers across all regions and functions, across software, process and system design, and physical implementation.

“In this Keynote, Hobson will address some of the methodology and infrastructure challenges faced, and solutions delivered by TSG, for delivering IP into a demanding partner base, across a wide variety of markets.”

* NXP Semiconductors’ Juergen Weyer will be speaking about the securely connected, self-driving car. Today’s absolute favorite topic at every semiconductor technology conference, it’s hard not to catch the enthusiasm.

“Few industries are as primed for radical change in the years ahead as the worldwide automotive market. Advanced driver assistance system (ADAS) features are increasingly common in entry-level new car models, and today’s high-end vehicles commonly receive over-the-air software updates and feature semi-autonomous driving functionality.

“Meanwhile, Silicon Valley start-ups and established auto OEMs alike are rushing to deliver the first true ‘self-driving’ cars, thereby ushering a new era in transportation based on some of the most profound technical advancements this mature industry has seen since its inception more than 100 years ago.

“The U.S. is taking bold steps towards implementing V2X technologies with a planned mandate and a Smart City Challenge that fosters the rapid introduction of latest mobility innovations.

* ESD Alliance’s Bob Smith will be speaking about Moore’s Law and the transition from chip-centric design to system-level design.

“The semiconductor design ecosystem is evolving from a chip-centric focus to a system-centric worldview. While SoCs and other complex semiconductor devices remain as critical building blocks, the design emphasis is shifting to system
design.

“Moore’s Law remains a key driver, although there are roadblocks in the path and it is clear that the industry is beginning a transition from integration at the transistor level to integration at the functional (block) level.

“The Electronic System Design Alliance (formerly EDAC) recognizes these major changes and has acknowledged them by upgrading its mission to recognize the breadth of activity across the entire design ecosystem.”

********************DVCon Europe Sponsors …

It is refreshing to see the sponsors this year include the Big Three – Synopsys, Cadence, and Mentor Graphics – as well as AMIQ.

Synopsys has a problem. Per Norm Kelly, speaking at the ESD Alliance panel on September 14th in Silicon Valley, Synopsys loses fully a third of the revenue they’re owed each year for their vast catalog of IP because it’s stolen by Cheaters and used without paying any licensing or royalty fees.

Kelly said Synopsys earns about $200 million per year selling IP, and loses another $100 million to theft. Cheaters are a real problem, he lamented, and as Director of License Compliance for Synopsys he should know. Kelly did not have the floor to share these laments, however, until Warren Savage, GM of IP at Silvaco, opened the meeting.

Speaking from the podium as moderator of the evening’s discussion, Savage said the real problem is the bumblers, those designers and companies who lose track of licensing obligations for IP that was either purchased some time ago, or was brought into the design effort on a data stick fished out of the pocket of someone who’s joined the organization through a poorly managed M&A.

In other words, when Chuckles the Clown uses IP, often as not he doesn’t realize some monies are owed to the third-party IP vendor who created it in the first place. Savage offered this statistic: On an average SoC today, there are 150 to 200 blocks of IP, but only a small percentage of those blocks are actually paid for.

Chuckles the Clown is indeed alive and well in the IP user community and to blame for most of the lost revenue owed to an increasingly agitated IP vendor community, per Savage. He drove home the point with the proverbial foot-on-banana-peel graphic.

Savage and Kelly weren’t the only two at the front of the room on Wednesday night, however.

Also perched on speaker stools were KPMG’s Rob Ballow and Pricewaterhouse-Cooper’s Eric Stein. These two guys are accountants-turned-IP-sleuths, who handle audits of IP use in semiconductor companies on behalf of the IP vendors who sell the stuff.

How is IP usage audited? Ballow and Stein were not quite clear on the process, but basically it’s an issue of body language, is what we were told.

If somebody in a user company starts to hem, haw, look away, or fidget in their chair when they’re asked by outside auditors if IP is being used on projects without adequate licensing or fees being paid, the auditors know they’ve got a live one, a cheater.

Despite the tell in their body language, however, cheaters are often reluctant to confess to their crimes. Ballow amused his audience with one particularly momentous story.

An IP vendor in Europe sent out a notice to all of their customers worldwide announcing that an audit team was going to call on each and every customer to determine if any of the vendor’s IP was being used without proper licensing.

One of the vendor’s customers – a large company in Asia, according to Ballow – responded to the letter with a $10 million check sent by return post. The company said they were sending the money as a courtesy, but would not be submitting to an audit of any of their people or projects. The $10 million was a just-in-case payment for violations in case there were any, which there weren’t.

Larger lesson here? Audits are only optional, and must be submitted to voluntarily by the companies that use IP.

So much for Cheaters and Chuckles, now for the Chalk and Cheese.

There are several methods for tagging and tracking IP usage. These methods were discussed throughout the 2-hour session on Wednesday night, by Savage, Kelly, Ballow and Stein, and also by many in the audience who participated in the lively back-and-forth.

For instance there’s a long-standing IP tagging standard, promoted by Accellera. Per several speakers in the audience, however, that standard is rarely used, it’s not robust enough and therefore of little value.

More recently, Warren Savage – while still CEO at IPextreme, before his company was acquired by Silvaco – oversaw the development of a fingerprinting scheme that puts identifying markers on a block of IP that can be used to track the block throughout its integration into a design and subsequent manufacturing into a chip.

“Nobody in the semiconductor companies really wants to cheat,” Savage said, “which is why they need these tracking tools to help monitor all of the IP floating around out there.”

The fingerprinting strategy was announced late last year [see blog here], and is now a project that Silvaco continues to promote, with Savage leading the effort via his involvement with ESD Alliance.

[Hence this Wednesday’s panel was held on the Silvaco campus in Santa Clara and all in attendance were gifted with a nifty Silvaco-branded wireless mouse upon exiting the meeting.]

The value of this fingerprinting strategy notwithstanding, some in the audience still expressed profound skepticism over any kind of IP tagging, fingerprinting, or tracking tools and strategies. All of them can be circumvented, was the consensus.

Norm Kelly acknowledged the optimism of Warren Savage and also agreed with the pessimism he heard from the audience: “Yeah, most don’t want to cheat, but many companies do want to cheat. Soft IP is configurable and hard to fingerprint, but even hard IP can have the tagging layer removed.”

In other words, all of these protocols, tags, tools, and so forth, are no better than the meter maid’s Chalk on your tire. If you’ve exceeded the time limit in that parking spot, just move your car forward so the chalk mark is in a different location relative to the street, or smudge it out completely with the heel of your hand.

As one audience member put it on Wednesday night, “Cheaters who steal IP are truly nefarious. They steal the IP, they change it, and then they sell it. What can fingerprinting do to stop that?”

The chalk mark on IP is simply not powerful enough to stop the cheaters. So what strategy remains to those IP vendors who continue to insist they should be paid for the products they provide to an IP-hungry industry?

That’s where the Cheese comes in.

After the panel discussion was ended and the crowd began mingling, a very knowledgeable CEO approached me and offered the most defensive, and seemingly robust strategy to counter both Cheaters and Chuckles.

Issue a new version of your IP every 90 days, the new version is not backwards compatible, and ergo anybody looking for support for a piece of IP that’s older than 90 days is simply out of luck. The vendor company will know instantly that IP is being used without proper licensing and fees.

Old cheese is stinky cheese, and will not sit well if consumed. Eat it and suffer the consequences.

And there’s one more part to this very defensive stance, about which the knowledgeable CEO was absolutely blunt: “We don’t do business with people we do not trust.

“If we don’t trust them, it’s simply not worth our time. Period.”

*****************Addendum …

* You will be able to access the entirety of this extremely informative panel discussion very soon. It was taped and will be viewable shortly on the ESD Alliance website.

* The Core Store is an online repository, developed at IPextreme and now supported by Silvaco, where companies who chose to participate in the IP fingerprinting scheme can register their IP.

* The world of IP will be gathering for a debut conference in December 2016. Supported by the ESD Alliance, CAST, True Circuits, SoC Solutions, Certus, Silicon Creations and Silvaco, this one-day meeting will be held in Silicon Valley.

Over the last several weeks, the ESD Alliance has announced two more members, news of particular interest because both companies are IP vendors. C-Sky Microsystems provides 32-bit embedded CPU cores, and Silvaco provides EDA tools for development of analog/mixed-signal devices, power IC and memory design.

True, Silvaco doesn’t sound like an IP vendor until you remember that it just acquired IPextreme, a well-known player in the IP market headed up by Warren Savage. And Savage, now GM of Silvaco’s IP Division, has recently been named chair of the ESD Alliance Semiconductor IP Working Group, tasked with developing a common methodology, best practices for fingerprinting, and solutions for tracking and auditing IP.

Meanwhile, C-Sky Microsystems brings its own unique value proposition to ESD Alliance. Described in the Press Release as “the first IP company from China to join the ESD Alliance,” C-Sky says it intends to actively participate in Savages’ SIP Working Group. This second bit is admirable, but the first could prove complicated.

For many semiconductor design houses, China presents problems when it comes to manufacturing, a long-standing concern about IP protection during the manufacturing process. Relying on the vast semiconductor manufacturing infrastructure in Taiwan, instead, is for some the solution. A geographically beneficial location in Asia that is not associated with a country frequently accused of less-than-stringent IP protection protocols.

So herein lies the concerns. People who use IP, and the vendors who sell it, need processes for securing the pipeline, audits for tracking IP usage and the associated liabilities, costs, royalties. If an IP vendor is associated with a location or country that continues to generate concerns about IP protection, how can that vendor participate in the development of the aforementioned processes for tracking and auditing IP usage?

In 2009, I published a blog suggesting that the Common Platform was launched, subliminally, as the not-China option. Here isa link to that blog.

The messaging in that blog notwithstanding – to think we’ve come so far as to include a China-based IP company in the membership of the ESD Alliance is a great step forward in international understanding and/or faith in good global business practices.

Don’t be surprised, however, if this newest member of the ESD Alliance also generates some concerns. It may not be politically correct to air those concerns, but when has the business of making money ever been politically correct?

This is a touchy subject, no doubt about it. But failing to address these concerns could potentially undermine any good that’s been done so far by the ESD Alliance in enlarging its scope to include IP vendors in its ranks.

It’s fantastic to see that the ESD Alliance is following through with its new-found commitment to promote discussion about the IP industry. On Wednesday, September 14th, the Alliance is hosting an evening panel at their headquarters in Santa Clara to discuss semiconductor IP issues that “Keep You Awake at Night”.

As background, consider that the massive amounts of IP involved in building a modern SoC may translate into IP vendors losing millions of dollars if their IP is used therein without proper licensing. At the same time, semiconductor companies also wrestle with troubling issues if their engineers accidentally reuse a core without proper licensing, possibly exposing their employers to huge liabilities. The ESD Alliance event in September promises to address these thorny problems.

Moderated by industry leader Warren Savage – formerly CEO of IPextreme, but now GM of IP at Silvaco with the acquisition announced just prior to DAC – the evening’s two panelists come from interesting backgrounds.

Rob Ballow is Director of KPMG’s U.S. Risk Consulting Advisory Services, a role to which he brings 20+ years working in semiconductors and consumer electronics. Specifically, he’s worked in semiconductor IP and “has been involved in over 350 royalty audits”. Definitely someone who would understand the things that keep IP folks awake at night.

Equally qualified to contribute to the conversation, Eric Stein is Director of PwC’s Forensic Practice and specializes in IP, royalty, contract and channel compliance matters. Stein “has led over 100 compliance and investigative engagements throughout the Americas, Asia and Europe.” Prior to his 13+ years at PricewaterhouseCoopers, he led license compliance programs at NAVTEQ and Wind River/Intel.

Just reading the CVs of Ballow and Stein should be enough to inspire industry observers and IP vendors alike to want to attend the September 14th event. But knowing that Warren Savage will be coordinating the panel makes the evening an absolute must.

Here are some questions I hope the group will address over the course of the evening:

1) How can an IP vendor be sure their products are not being pirated by unscrupulous foundries?

2) How can an IP customer use an IP block with complete certainty that the associated licensing agreement will hold up in court if at a future point, the vendor comes after the user for extraordinary and/or unlicensed IP utilization?

3) How can IP Vendor A be totally sure that rival IP Vendor B will not come after A for perceived IP piracy, if A’s block looks very similar to B’s?

4) What does an IP audit consist of, and who are the responsible parties who open their project files for examination?

5) How can we verify that the auditors themselves are above reproach? Organizations like KPMG and PwC follow nationally established guidelines for financial auditing, but what governing body sets standards for IP auditing? Who audits the auditors?

Whether these questions are specifically addressed on September 14th, it’s still great to see that the ESD Alliance is providing a venue for crucial discourse about issues that frame the IP industry. Kudos to all involved.

]]>http://www10.edacafe.com/blogs/ipshowcase/?feed=rss2&p=20350Kapow Wham Boom: Holy Acquisition, Sir Robin!http://www10.edacafe.com/blogs/ipshowcase/?p=1983
http://www10.edacafe.com/blogs/ipshowcase/?p=1983#commentsMon, 18 Jul 2016 10:06:38 +0000http://www10.edacafe.com/blogs/ipshowcase/?p=1983
Yep, it’s happened. More astonishing than Brexit. Faster than a skyrocketing market cap. Stronger than any ties to Merry Old England, Apple, or ESDA. Able to leap over continents in a single bound.

Holy All-Cash-Deal, Sir Robin, ARM’s been bought by SoftBank!

For a mere 24.3 billion pounds.

[Or somewhere in the neighborhood of US$32 billion, depending on the moment or the hour or the day you’re calculating the exchange rate.]

It appears to be a done possible offer deal, and so the world wobbles a bit on its axis. Again.

And the questions are flying.

Will the UK allow this Crown Jewel of its tech ecosystem to be purchased outright by some folks 6000 miles away?

If it’s only a “possible offer” are there other suitors holding nosegays in the parlor?

Will other IP providers see this as an opportunity to compete more effectively with the Vendor Previously Known as ARM?

Will every EDA partner in the ARM Connected Community willingly go along for the ride?

Most importantly of all …

Will Simon Segars continue to sit on the ESD Alliance Board?

Holy Consolidation, Sir Robin. If you couldn’t afford one before, surely you can afford a Batmobile now.

It’s a poorly kept secret that Bob Smith was brought in as Executive Director of EDAC last year to shake things up, to breathe new life into the sails of a somewhat becalmed organization. Well, in the category of be careful what you ask for, here’s how things have gone so far:

New companies have joined the consortium, the newest member of the Board of Directors is not a CEO, a plethora of monthly panels have engaged the industry in thought-provoking discussions about innovation vis-à-vis commercial enterprise, a marketing deal has been struck with Semico, and the whole friggin’ organization has been re-branded as the ESD Alliance to reflect an intent to get more IP guys, more Embedded guys, and more Yet-to-be-identified guys into the alliance than just the traditional anchor tenants from EDA.

But none of this comes close to the potential impact of the latest disruptive idea that ESDA is proposing: The founding of a brand new working group that could very well redefine the whole semiconductor supply chain: The ESD Alliance System Scaling Working Group.

Astonishing.

That’s the only word to describe my impressions, after sitting for 90 minutes at the back of the room on Wednesday evening at ESDA headquarters in Silicon Valley, of the discussion that unfolded under the leadership of the ever-energetic President of eda 2 asic, Herb Reiter, who was standing at the front of the room.

The group in attendance at this ESDA meeting engaged in a dynamic back-and-forth in their attempts to nail down a proposed charter for the aforementioned Working Group.

Per Herb’s slides, the broad objectives for the group would include: Moving focus in the industry from transistor to system scaling, bringing design and manufacturing together through a combination of news, education, and collaboration, and focusing on those methodologies and best practices that would dovetail with the various standards efforts that perpetually percolate out of IEEE, Accellera, Si2, and Semi.

Wow.

Of course, Herb Reiter is hardly a novice when it comes to establishing and growing Working Groups. He’s had a great track record of doing this kind of thing over X number of years, once for Si2, once for GSA, and once for Sematech. He really knows how to do this – how to create focus and generate participation – so if anybody can get the ESDA_SSWG off the ground, Herb is the one to do it.

Nonetheless, even acknowledging Herb’s abilities, there were still huge questions being thrown about, some more politely than others, during the discussion/debate on Wednesday evening.

Principally, what is the intent of this System Scaling Working Group?

1) To be a Standards Body2) To create a Road Map3) To create a new Data Exchange Format4) To create a Reference Board5) To write a White Paper6) To be a Talking Shop

Not for a moment did Herb pretend to have an answer to these questions. He just wanted to get the idea for the Working Group out there, for the attendees to go out, discuss the thing with their colleagues, and get back to him with a) more questions and b) some answers.

Change is in the air, and ESDA’s evolution is just the tip of the iceberg.

Per one attendee on Wednesday night, referencing the latest hotness in the industry: “Yes, the IoT means the end of the SoC, but a billion IoT devices are only going to fill 10 wafers. Where’s the money in that?”

Exactly.

But that’s just one of the questions that emerged on Wednesday. There was also …

1) If packaging of heterogeneous die is the solution to the end of Moore’s Law, the end of scaling, why does the industry need a Working Group to point that out? Don’t they already know?

2) And why don’t the chip guys know that it’s all about the packaging? Why are they so stuck in their silo, they’re unable to see over the wall to the brutal realities of manufacturing whole systems?

Okay, so 90 minutes on a Wednesday night wasn’t enough time to sort out these cosmic questions.

And in fairness to ESDA, neither Herb Reiter nor Bob Smith were suggesting the Alliance could solve everything for everyone with the establishment of this Working Group. But what they did suggest was a way of inserting ESDA into a critical conversation about closing the yawning gap between design and manufacturing.

And all of this in the face of the most profound critique of the evening, lobbed at them from someone else who was sitting at the back of the room …

“All of this is very admirable, these ideas for this Working Group, but it’s not going to go anywhere unless we crispify what we are doing here. Crispify the value of this Working Group to the industry.”

Warren Savage, CEO at IPextreme, is willing to address questions regarding IP content at DAC 2016, enthusiastic in fact. That’s not surprising, given that he serves on the IP Track Committee that reviews the content.

“I think the content’s very good this year,” Savage said in a recent phone call. “We’ve been working on the IP content at the DAC for 3 years, and continue to make progress. I would say the biggest thing [we struggle with] is insufficient time allocated for IP.

“In comparison to previous years, however, the IP and Design tracks have been merged and all put under the same track – something we recommended against, because design-related submissions generally are different from IP-related submissions.”

“But as an IP consumer,” I asked, “isn’t the biggest problem knowing if the IP I’m about to buy is any good? Isn’t that the thing that should be addressed at DAC?”

Savage responded, “Over the past 20 years, there’s been considerable evolution in how people think about IP and I’ve been the megaphone for that change: IP is a product business and not a services business. It’s an idea that we felt was important back when I worked at Synopsys.

“In the early days of IP, people would try to sell some code labeled as IP. The customers tweaked and customized it for their own use, but it had no silicon provenance. What’s really changed over the last 20 years, people now have the product idea of IP. Customers have to have used it, so there’s certification.

“These are the kinds of things that potential customers look at. They need to be able to say: I trust this supplier and how this IP has been developed, and how it’s been verified. It’s this attitude that has raised confidence levels about using IP.”

“Even if IP has been certified by previous users,” I asked, “how do I know the block will perform well in my design, an environment that differs from that of previous users?”

Savage said, “There are two categories of IP, digital soft IP and hard IP. The latter does not change. Customers can be assured, for instance, that a microprocessor [verified] at 28 nanometers will not change.

“Soft IP, however, is somewhat more variable, and can change depending on the underlying libraries. A synthesizable processor core may run at certain speeds with certain libraries from ARM, but will behave different with Synopsys libraries at a different geometry.”

“I’m hearing great confidence today in third-party IP,” I commented.

“Yes, it’s quite stable right now,” Savage replied. “Over the last several decades, there was a first round of shake-ups in the industry and [the demise of] questionable IP companies after the dot.com crash.

“But the industry rebuilt itself in a structurally sound way after that. As a result, most IP companies even survived the 2008-2009 downturn.”

“If that’s the case,” I asked, “why is there so much angst about the IP industry, and the quality of IP, in the descriptions of panels that will be presented at DAC in June?”

“I don’t know,” Savage replied. “If you actually attend those panels, you’ll hear a far more optimistic attitude from the speakers. From my point of view, there’s nothing but optimism to think about in the IP industry.

“It’s by far the Gold Star market segment in the semiconductor industry. It’s growing faster than everything else, has a lot of longevity, and unlike EDA and some of the other market segments, it’s not mature and is still changing.

“That’s definitely different from the business of EDA today, where the design flows and tools used to make semiconductors are moving at a decelerating pace. We’re now working around the edges of [current design challenges], increasing tool capacity and cleaning up insufficiencies in parts of the flow for the smaller geometries.

“Also unlike EDA, IP is a content business driven by the consumer. Where EDA is driven by the requirement to manufacture the device, the IP industry is completely application-driven. In addition, IP is being driven by emerging standards, those for the auto industry and other new applications.”

“Are rumors of consolidation in the IP industry true or false?” I asked.

“That’s a myth,” Savage replied. “I know one of the great initiatives at large companies [is based on the idea] that there’s so much consolidation, including in the semiconductor industry, that the customers are saying, We just want to buy our IP from one or two companies. But that’s just the dream of purchasing agents, because that [strategy] doesn’t work in IP.

“The big IP companies work on collecting IP [for their portfolios] with the most revenue. But if you’re a semiconductor company and will be using IP for 90 percent of your design, the big companies can only supply your engineers with 80-percent of the chip. You will still need 10-percent from the smaller companies, the kind of IP the big guys haven’t yet seen the value of adding to their portfolios.”

“Seems like good news for the small IP companies,” I said.

Savage agreed: “Yes, as long as you have some differentiation, you’ll always be one step ahead of the big guys. That’s the unique thing about IP, it still offers market advantages to smaller companies.

“And there’s one other pitchy thing: The semiconductor industry has changed quite a bit over the last 10 years, VC money has slowed to a trickle. I have a lot of friends who [in a different time] would have left Intel, for instance, and tried to raise some money to start a semiconductor company.

“But it’s so expensive today, instead they change themselves into an IP company. That’s where all the great intellectual power of the semiconductor industry is going.”

“How about the changes at EDAC,” I asked “How’s the morphing of the organization into ESDA, the ESD Alliance, being received in the IP industry?”

Savage endorsed the change: “Historically, most of these organizations have been targeted at the semiconductor industry, GSA for instance, or EDAC for the EDA players.

“However, the ESD Alliance is [emerging] as an organization willing to put some of its energy towards helping the smaller IP guys, which is most of the IP community. There are 4 or 5 big companies in IP, but 400 or 500 smaller companies, where the innovation actually happens.

“In my view, getting the smaller IP companies into an industry-wide organization is something that’s been missing. And these small guys do need help. I’m working closely with [ESDA Executive Director] Bob Smith, because we both know there are a lot of things that can be done.”

The ESD Alliance has announced two additional updates on its remarkable road to renaissance. The Alliance formerly known as the EDA Consortium says Dr. Lucio Lanza, long-time EDA investor and 2014 Kaufman Award winner, is joining the organization’s board of directors, effective immediately.

That news is unique for 4 reasons: a) Lanza is the first new board member since EDAC was relaunched as ESDA; b) Lanza is the only member of the board who is not currently serving as the CEO of a company, the first such circumstance in recent memory; c) Lanza serves on the board of PDF Solutions, triggering another first in that one company is now represented twice on the EDAC/ESDA board with PDF’s John Kibarian also serving therein; and d) Lanza was not elected, but appointed.

Certainly for all of these reasons and more, Dr. Lucio Lanza will serve as a refreshing change agent as the EDA Consortium morphs into the ESD Alliance.

The second major update from the ESD Alliance is the announcement of a “cooperative marketing” partnership with Semico.

In case you’ve forgotten: “Semico Research, founded in 1994 by semiconductor industry experts, is a semiconductor marketing and consulting research company, [that offers] custom consulting, portfolio packages, individual market research studies and premier industry conferences, improving the validity of semiconductor product forecasts via technology roadmaps in end-use markets. Semico is also noted for its coverage of the IP market.”

Per the press release, the new partnership “will enable the ESD Alliance and Semico to promote their common business goals. Semico will assist the ESD Alliance in broadening its reach into the IP community by promoting it at Semico events, on its website and through promotional emails, and will provide a discount to ESD Alliance members for purchase of individual research reports, will offer enterprise-wide access to its IPI Monthly Report and extend admission discounts to Semico conference events.

“In exchange, Semico has become an associate member of the ESD Alliance, which will post availability of new Semico research reports and provide a link to its website for Semico blogs and articles.”

Bob Smith, ESD Alliance Executive Director, is quoted in the press release: “Our new mission is focused on representing the design ecosystem, and IP is a key component [therein]. We will rely on Semico’s expertise as we expand our presence and showcase our benefits to IP vendors and suppliers.”

Jim Feldham, President of Semico, returns the compliment in the same press release: “The ESD Alliance recognizes that the IP community is an important element of the semiconductor design ecosystem, and one that will benefit from its newly expanded charter and ongoing initiatives. We look forward to working with the ESD Alliance to raise the visibility of the importance of the IP market.”

**************An observation …

It would be good news to hear that ESDA has also struck up a “cooperative marketing” partnership with Gary Smith EDA. Although that organization does not host conferences, it certainly provides important market research and custom consulting to a significant portion of the ESD Alliance. Hopefully, when Gary Smith EDA is presenting on Sunday evening, June 5th, at the Design Automation Conference in Austin, we will hear of such a partnership.

IP now dominates design automation, evidenced in no small measure by ARM’s seat at the head of the table for the ESD Alliance, ESDA being an important sponsor of the Design Automation Conference. Everyone seems to agree that IP reuse is the only way complex mega-systems of the 21st century can be designed, so not surprisingly the DAC program now reflects that reality. There are sessions every day categorized as being IP-related, but are those designations accurate?

I would argue that a lot of the content that’s sitting in the IP Track at DAC is really just about design, and not specifically about IP-based design. To prove that point, below is a complete listing of the sessions in the IP Track that’s set to air between June 6th and 9th at DAC in Austin. Those that are legitimately about IP are bolded, sessions that actually talk about using IP. Those not bolded are ‘just’ about design, or are merely high-level nattering about superficial issues associated with IP reuse.

Conclusion: the number of IP-related sessions are far fewer than one would hope. If IP is this important, why aren’t there more sessions that are really about IP? Is there a conspiracy here?

Fortunately, this next week I’m talking at length with Warren Savage. As CEO of IPextreme, his knowledge about the technology and business of IP is pretty encyclopedic. I will run my conspiracy theory past him: DAC wants you to believe they believe in IP, but in fact the conference is still more about design automation, not about using silicon IP to enhance the process. EDA vendors still rule the roost at DAC.

******************

* IP TRENDS AND REQUIREMENTS [Monday, 10:30 am to Noon]
Sessions include presentations that demonstrate leading-edge trends and requirements covering the IoE, emerging as the next frontier of connectivity to conquer, as well as functional safety as an emerging requirement for SoC Designers and vendors of silicon IP.Chair: ARM’s Simon RanceSpeakers: Synopsys’ Jamil Kawa, Cadence’s Nick Heaton, ARM’s Andrew Hopkins and Lauri OraSponsor: ChipEstimate.com

* FISH FOOD FOR THOUGHT: CONSOLIDATION TREND IN THE IP ECOSYSTEM GOOD FOR THE INDUSTRY? [Tuesday, 11 am to Noon]
The Commercial IP Ecosystem is growing and projected to sustain growth, yet the pool seems smaller, year over year. Is current trend a hindrance or catalyst for innovation? What challenges would IP companies expect when swimming in these waters? What conditions may re-populate the pool? Who ultimately prospers: investors or end customers?Moderator: IEEE’s John BlylerPanelists: Sankalp Semi’s Samir Patel, Leyden Technologies’ Dennis Segers, Design Rivers’ Camille Kokozaki, Lattice Semi’s Laxman VemuryOrganizer: Intel’s Heather MoniganSponsor: ChipEstimate.com

* RISC-V: INSTRUCTION SETS WANT TO BE FREE [Tuesday, 1 pm to 1:30 pm]
A free ISA is a necessary precursor to future hardware innovation. There’s no technical reason not to have free, open ISAs just as we have free, open networking standards and free, open operating systems.Speaker: UCB’s Krste Asanovic

* HOW DO WE MAKE IP REUSE WORK? [Wednesday, 3:30 pm to 4:30 pm]
Various factors have made IP reuse an arduous journey. Representatives from the design, provider and semiconductor communities will discuss what ails the IP industry and what can be done to improve IP reuse for analog and digital design.Moderator: ARM’s Brian FullerPanelists: eSilicon’s Mike Gianfagna, Samsung’s Rwik Sengupta, ClioSoft’s Ranit Adhikary, Synopsys’ John Koeter

*DESIGN/IP TRACK POSTER SESSION [Monday and Tuesday, 5 pm to 6 pm]
Per organizers: “The limited time available in the Design/IP Track session program was exceeded by the quantity of great submitted content, posters based on these papers will be presented in the Design/IP Track.”

By my estimation, however, only 6 of the 58 posters offered over the 2-day poster session can be considered relevant to IP. Those posters include …