The ambition of PLASMIC is to address the bottleneck caused by electrical interconnects and develop on-chip optical interconnect solutions based on plasmonically-enhanced nanoscale emitters.Nanoscale photonic components are desirable for on-chip communications because of density, speed and because reducing the size of the cavity might reduce the lasing threshold. Conventional photonics are limited in scale by the diffraction-limit to dimensions of half of the wavelength of light in the material. This limit does not apply to plasmonics, an optical mode that exists at the interface between a metal and a dielectric. Thus, they have a great potential for applications where down-scaling and confinement are primordial.One of the barriers for applying plasmonics is the large losses associated with the metals. Thus in PLASMIC alternative plasmonic metals will be investigated based on their potential for tuning, VLSI compatibility, deposition methods and achieving lower optical losses in the near-IR. I will focus on highly doped semiconductors, metal nitrides, as well as multi-layers and compounds to form new plasmonic materials. Specifically, I will evaluate the use of the field-effect to achieve the semiconductor-metal transition to tune the plasma frequency.New pioneering device concepts for plasmonic-photonic emitters on a silicon platform integrated with passive silicon photonic waveguides will be developed. To implement the gain medium for the lasers, I will exploit a novel nanowire (NW) integration approach: Template-Assisted Epitaxy. The unique advantages make it possible to grow III-V NWs on any orientation of silicon and aligned to lithographic features.The devices will be based on a hybrid cavity formed between the NW and a Si waveguide with gratings to provide feedback. My team and I will explore dimensional scaling potential as well as the energy efficiency of plasmonic and photonic devices operating both in a lasing as well as in a subthreshold operation mode.