The SCANSTA112 device is a 7-port multidrop IEEE 1149.1 (JTAG) multiplexer design to connect boundary scan chains into a single chain as well as the ability to remove a board from the system and retain test access to the remaining chains.

Non-boundary scan devices such as DDR or flash memories need to hold one or more nodes (chip select/enable) to fixed states during boundary scan testing, so that the device is disabled during boundary scan testing and its output pins (i.e. data) are not activated, as otherwise, it will cause unstable tests or damage to the circuitry. Boundary scan “hold states” are node/device pins on a board that are held to a logic of 1 or 0 by a boundary scan driver on the node, when the boundary scan device driver/output pin is in EXTEST.

When the device is operating under the normal mode, the boundary register is transparent. Signals can pass through the boundary scan cells freely and the device operates as it would without test cells. In this mode, test data is captured in the boundary register cells, then shifted through the boundary register out to TDO.

The IEEE Standard (Std) 1581 is the standard for Static Component Interconnection Test Protocol and Architecture. The IEEE Std 1581 targets testing for low-cost, complex DDR memory devices, which would be able to communicate through another semiconductor device with an IEEE Std 1149.1 boundary scan capability.