Intel details Sandy Bridge at ISSCC

SAN FRANCISCO—Intel Corp. disclosed more technical details of its 32-nm Sandy Bridge processor at the International Solid-State Circuits Conference here Tuesday (Feb. 22), including further description of its modular ring interconnect, design techniques used to minimize the cache's operational voltage and the inclusion of debug bus for monitoring traffic on the interconnect.

The 32-nm Sandy Bridge processor integrates up to four x86 cores, a power/performance optimized graphic processing unit (GPU) and DDR3 memory and PCI Express controllers on the same die, according to the paper presented at ISSCC Tuesday by Ernest Knoll, a designer at Intel's design center in Haifa, Israel. Sandy Bridge features 1.16 billion transistors and a die size of 216 square millimeters, Knoll said.

The Sandy Bridge IA core implements several improvements that boost performance without increasing power consumption, including an improved branch prediction algorithm, a micro-operation cache and a floating point advanced vector extension, according to the paper. Also, the devices' CPUs and GPU share the same 8MB level-3 cache memory, according to the paper.

Although the L3 cache units are organized in four slices along with the x86 cores, 2MB per core, they are fully shared with the GPU, Knoll said.

Sandy Bridge's ring interconnect fabric connects all the elements of the chip, including the CPUs, the GPU, the L3 cache and the system agent. Because the ring interconnect is modular, the four-core die can easily be converted into a two-core die by "chopping" out two cores and two L3 cache modules, according to Knoll's presentation. The initial version of Sandy Bridge are available in two- or four-core variations.

"By simply 'chopping' two slices, we get to another level of die," Knoll said.

Intel provided the first details about the Sandy Bridge family of heterogeneous processors at the Intel Developer Forum here last September. Intel introduced the first Sandy Bridge products, the second generation of the company's Core processor family, at the Consumer Electronics Show in January. Some of the devices have been shipping since early January and Intel expects them to be incorporated into more than 500 laptop and desktop PC designs this year.

I dont think Intel Integrated graphics can beat AMD's in near future. AMD graphics is way ahead of Intels. Response from Intel's Graphics is too slow compared to AMD/ATI. I have Wii also, amaging quality. Also see latest HP product dm1z with AMD latest processor which has integrated graphics processor, what an amaging product.

This is a highly awaited information about the Architecture from Intel and it is good that Intel has started providing some technical information. By the time Haswell Architecture comes in usage the might get complete information about Sandy Bridge.

Interesting. It is likely a large, distributed PFET to modulate VDD into every bitcell. It throttles the power to every cell in a row when a write op is performed. That's the easy part.
The interesting part is this pfet is "shared", so it could also affect the neighboring row of bitcells, which may lose their data when VDD is dropped. Or not, depending on leakage and noise. Another ISSCC paper should reveal more details.
I originally thought it switched VDD, but reading closely, it implies VDD modulation, rather than on/off. The technique has significant layout impact -- the 6T cell becomes 8T equivalent and layout symmetry is very much compromised.