ICQ

Yahoo

Jabber

Skype

Location

Interests

Biography

Location

Interests

Occupation

Company

Hello,
I need a help, Its a huge implementation like having A, B, C systemC Modules and instantiated in the Top and sc_main have the Top hierarchy sc_module_name. In the systemC Module A, i have lot of pure C++ classes and instantiated so many times like some algorithm to do some computation. While debugging difficult to get the hierarchy which one is printing or tracing.
I am looking for a solution, without changing the pure C++ classes to derive from sc_module, how do i make it a hierarchy to Top. Changing every where to have a constructor with sc_module_name will be little difficult as the code is huge. Is there any suggestion?
Regards
Aarthi

Hi,
I have a simple project it's goal is to create a 32 bit ripple adder from an array of Full adders (FA).
I have successfully implemented the FA (implementation attached) , but I have a simple problem now.
Unlike the FA , the Ripple adder has many more inputs, and I cant find an efficient way to model these inputs , for instance in VHDL I would have an input port with the number of bits that I needed and I can access them easily in the architecture of the module, Unfortunatly this isn't the case for me in systemC.
Approaches that I tried include:
Using ( sc_in<sc_lv<32>> ) , which seems logical , but I cant deconstruct the vector into sc_logic inputs that I can then pass to my FA sub-modules to process.
using ( sc_lv::read() ), doesn't seems to output the right data type (sc_logic) , I even tried type casting, but the constructor for the FA failed.
Using array of sc_in<sc_logic> *A[32],*B[32]; , this approach is probably the closest I have got, It compiles correctly , but it doesn't run as there is always some kind of port that isn't connected correctly.
Basically , I need to know how to model a 32 bit module and pass each individual bit to their respective sub-module.
I know that there is the approach of declaring 32 inputs individually, but this seems tedious and the language must have some better approach.
I realize this might seems easy, but I'm still new to systemC , and would love for someone to give me their feedback on how to implement this Ripple Adder as it would help me immensely in my project.
FA.cpp
FA.h
HA.cpp
HA.h

Hi,
I have a simple project it's goal is to create a 32 bit ripple adder from an array of Full adders (FA).
I have successfully implemented the FA (implementation attached) , but I have a simple problem now.
Unlike the FA , the Ripple adder has many more inputs, and I cant find an efficient way to model these inputs , for instance in VHDL I would have an input port with the number of bits that I needed and I can access them easily in the architecture of the module, Unfortunatly this isn't the case for me in systemC.
Approaches that I tried include:
Using ( sc_in<sc_lv<32>> ) , which seems logical , but I cant deconstruct the vector into sc_logic inputs that I can then pass to my FA sub-modules to process.
using ( sc_lv::read() ), doesn't seems to output the right data type (sc_logic) , I even tried type casting, but the constructor for the FA failed.
Using array of sc_in<sc_logic> *A[32],*B[32]; , this approach is probably the closest I have got, It compiles correctly , but it doesn't run as there is always some kind of port that isn't connected correctly.
Basically , I need to know how to model a 32 bit module and pass each individual bit to their respective sub-module.
I know that there is the approach of declaring 32 inputs individually, but this seems tedious and the language must have some better approach.
I realize this might seems easy, but I'm still new to systemC , and would love for someone to give me their feedback on how to implement this Ripple Adder as it would help me immensely in my project.
FA.cpp
FA.h
HA.cpp
HA.h

Hello,
I am trying to create several nodes that are represented as SC_MODULE. I see that once I reach 10000 nodes the compile throws the following error:
SG_m_n: ../../../../src/sysc/kernel/sc_cor_qt.cpp:107: virtual void sc_core::sc_cor_qt::stack_protect(bool): Assertion `ret == 0' failed.
Aborted (core dumped)
I think it might be related to memory protection (mprotect()) but I don't know if someone has some ideas about this limitation or how to overcome it?
thank you :),
Emad