An FPGA is made up of a combination of Logic Blocks, IO Blocks and interconnections wiring everything up.

Each logic block is made up of a variety of different primitive components interconnected, usually this consists of a Look Up Table, Multiplexer and some combinational logic. Below is a very simple CLB from an early Xilinx FPGA.

Now the important thing for me are the primitive components, which I have to model individually. Which in the case of the Xilinx XC2000, a very early FPGA is over 400 different components! Below is the same CLB but with the primitives highlighted.Using an Event-Driven Discrete Modelling Simulation, these primitives were modelled and their interconnections simulated. Thus creating a working model. And whats more, it only took around 35,000 lines of code!

About Me

I'm currently employed as a Software Engineer specializing in Embedded Solutions after finishing my Software Engineering degree at York. I was an Academic Developer Evanglist at Microsoft and a world-wide finalist in the Imagine Cup developer competition in both 2010 and 2011.