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Abstract

This article describes a method of testing global wiring used in "wafer scale" integration (i.e., an entire wafer forms one "chip"), or in very large-scale integration (i.e., one wafer contains only 2-4 "chips"). Global wiring" refers to the wiring which interconnects the input/output (I/O) pads of each "domain" (i.e., functional block) and connects these domain I/O pads to wafer I/O pads. Testing the continuity of this global wiring is facilitated by creating an additional level of temporary wiring (i.e., a layer of insulation with via holes to all pads and a patterned layer of metal on the insulation layer) which interconnects a selected large set of the global wires in series by interconnecting selected domain I/O pads.

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United States

Language

English (United States)

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Method of Testing Global Wires Used in Wafer Scale Integration

This article describes a method of testing global wiring used in "wafer scale"
integration (i.e., an entire wafer forms one "chip"), or in very large-scale
integration (i.e., one wafer contains only 2-4 "chips"). Global wiring" refers to the
wiring which interconnects the input/output (I/O) pads of each "domain" (i.e.,
functional block) and connects these domain I/O pads to wafer I/O pads. Testing
the continuity of this global wiring is facilitated by creating an additional level of
temporary wiring (i.e., a layer of insulation with via holes to all pads and a
patterned layer of metal on the insulation layer) which interconnects a selected
large set of the global wires in series by interconnecting selected domain I/O
pads. By applying test signals at two wafer I/O pads, the continuity of the series-
connected global wires is determined. Once testing is complete, the temporary
wiring is removed by any of several means, e.g., chemical etching. The figure
shows a small portion of an edge of a semiconductor wafer 2. Wafer I/O pads 4
are disposed along the edge of wafer 2. The dashed rectangular regions
represent the various circuit domains. A few of the domain I/O pads 6 are shown
in two of these circuit domains. Global wiring 8 (finer lines) passes between
circuit domains to connect domains to one another and to the wafer I/O pads.
The heavier lines 10 represent the temporary test wiring layer. The test...