CoreLink CCN-504 Cache Coherent Network

The ARM® CoreLink™ CCN-504 Cache Coherent Network is optimised for mid-range systems with up to 16 processor cores. This give system architects an optimal solution for enterprise applications including servers and network infrastructure.

CoreLink CCN-504 includes an integrated Level 3 Cache from 1 to 16MB, which places it in the middle of the range of the ARM CCN series. The CoreLink CCN-504 offers high bandwidth interconnect supporting AMBA 5 CHI protocol and bandwidth approaching 1 terabits per second.

CoreLink CCN-504 is optimised for the latest ARMv8 64-bit processors including Cortex-A57 and Cortex-A53. CoreLink CCN-504 is part of a family of products offering designers a scalable, cache coherent interconnect for 'many core' networking infrastructure and sever solutions.

Optimized for ARM Cortex Processors

The CoreLink CCN-504 supports the high efficiency Cortex-A15 processor and the latest Cortex-A53 and Cortex-A57 processors, and is in the family of ARM CoreLink CCN that support the AMBA® 5 CHI. This new coherent hub interface has been developed to support high frequency, non-blocking data transfers between multiple fully coherent processors.

Integrated Low Latency Level 3 Cache

The CoreLink CCN-504 Cache Coherent Network includes integrated level 3 (L3) cache and snoop filter functions. The L3 cache, which is configurable up to 16MB, extends on-chip caching for demanding workloads and offers low latency on-chip memory for allocation and sharing of data between processors, high-speed IO interfaces and accelerators. The snoop filter removes the need for broadcast coherency messaging, further reducing latency and power.

High Performance DDR3 and DDR4 Memory Interfaces

The CoreLink CCN-504 is optimized to work with the CoreLink DMC-520 Dynamic Memory Controller providing high-bandwidth interface for off-chip memory, such as DDR3, DDR3L and DDR4 DRAM. CoreLink DMC-520 offers enterprise class RAS (Reliability, Availability and Serviceability) features such as ECC for x72 DRAM, TrustZone security and end-to-end QoS.

Bandwidth and Latency

CoreLink CCN-504 Cache Coherent Network can deliver up to one Terabit per second of usable system bandwidth. It will enable designers to provide high-performance, hardware managed cache coherency between processor clusters and IO interfaces and accelerators. Bandwidth to the dual channel DDR4 memory approaches 50GB/s.

Frequency

CoreLink CCN-504 is designed to work closely with the latest ARM applications processors and can be imlemented at clock speeds approaching that of the Cortex-A15 or Cortex-A57 processor. Interfaces to memory and processors can be configured for asynchronous interfaces to allow power management including dynamic voltage and frequency scaling.

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LSI, a leading designer of intelligent semiconductors that accelerate storage, mobile networking and client computing, and Calxeda, an innovative supplier of disruptive SoC technology for the server market, are lead licensees for the CoreLink CCN-504 launch.

“Calxeda and ARM have been working closely to meet the demands of the datacenter since ARM's initial investment in our company in 2008, and we are beginning to see the fruits that relationship,” said Barry Evans, co-founder and CEO, Calxeda. “We are already building our next generation datacenter-class solutions using this new ARM CoreLink technology, and think we will once again send shockwaves across the industry when they are announced.”

“To meet the demands of rapidly growing mobile network traffic, LSI and ARM have worked closely to drive a feature-rich on-chip interconnect that can serve as the backbone for industry-leading many-core system-on-chip devices,” said Gene Scuteri, vice president of engineering, LSI. “ARM expertise in processor and interconnect technology, guided by LSI's deep understanding of networking and compute workloads, has delivered a robust, carrier-grade interconnect that will deliver scalable, deterministic performance and quality of service for today’s most advanced networks.”

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