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by Ann Steffora - Contributing EditorPosted anew every four weeks or so, the EDA WEEKLY delivers to its readers information concerning the latest happenings in the EDA industry, covering vendors, products, finances and new developments. Frequently, feature articles on selected public or private EDA companies are presented. Brought to you by EDACafe.com. If we miss a story or subject that you feel deserves to be included, or you just want to suggest a future topic, please contact us! Questions? Feedback? Click here. Thank you!

Mentor Graphics Assists Out of Work Design Engineers

At a dismal time in the employment landscape, Mentor Graphics Corp. is admirably helping design engineers that are out of work. The company said it would provide EDA training to recently displaced electronic design professionals at no charge. Through the new Displaced Worker Program, the company said it would offer free course placements to unemployed engineering staff, on a “space available” basis, in its public enrollment training classes. The program enables engineers to enhance technical skills and gain experience in the use of leading-edge technologies for programmable logic design, PCB design and integrated circuit design and verification. The courses will first be

offered to qualified candidates in all North American Mentor Graphics training locations, including Austin, Boston, Chicago, Dallas, Denver, Minneapolis, Portland and San Jose. A complete list of course descriptions, schedules and training locations is available at

Mentor also announced that the U.S. District Court for the Northern District of California granted the company's motion for summary judgment of infringement against Cadence Design Systems. In a 19-page opinion entered in Case No. C 00-1030 SI, the Court found that Cadence's Mercury and MercuryPlus emulator products infringe a claim of Mentor's U.S. Patent No. 5,999,725 (the '725 patent). This order follows the same Court's summary judgment finding that Cadence's MercuryPlus infringed another Mentor patent on April 9, 2002. Hearings on additional summary judgment motions for infringement and invalidity are scheduled for October and November of this year. A trial of the

remaining issues in this case, including Mentor's claim of trade secrets theft, is set for January 6, 2003. Prior to the present summary judgment ruling on the '725 patent, the court invalidated another single claim in the patent.

Speaking of Cadence Design Systems, Inc., the company and Datang Mobile Communications Equipment Co. Ltd. announced a collaborative effort to develop standards-based solutions that is aimed at helping 3G developers in China and the rest of the world accelerate time to market for mobile communications products. The first solution resulting from this collaboration is a base-band library, which fuses Datang's uplink and downlink simulation models with the Cadence Signal Processing Worksystem (SPW). For details, see

Cadence also unveiled a joint initiative meant to help customers facilitate the smooth transition to fabrication through physical design verification using Cadence's nanometer design technology. Under this initiative, Cadence Assura physical verification solution DRC decks for 0.25-, 0.18- and 0.13-micron CMOS logic technologies are now available for download free-of-charge on UMC's “My UMC” customer website. This easy access to high-quality, foundry-level, silicon-proven rule decks should save customer time and resources, thus enabling them to remain focused on their nanometer chip designs.

Synopsys, Inc. reported that the waiting period under the Hart-Scott-Rodino Antitrust Improvements Act of 1976 with respect to Synopsys' pending tender offer for all outstanding shares of inSilicon Corp. expired without a formal request from the Federal Trade Commission for additional information or documentary material. The parties have previously received clearance from the German Federal Cartel Office to complete the acquisition and plan to file a pre-merger notification in Taiwan. Synopsys' completion of its tender offer for inSilicon shares remains subject to certain conditions, including the tender of a majority of the outstanding shares of inSilicon.

Mentor Graphics also announced DMS2002, the latest version of its design data management infrastructure solution that consolidates and manages work-in-progress design data and provides a tight integration between the design engineer and the extended enterprise. According to the company, DMS2002 expands the accessibility of component information from the corporate library to the wealth of data available on the Internet through specialized content providers, giving users a broader portfolio of decision and selection criteria in a very early phase of the design process.

DMS2002 now includes DMS-Xchange, a new communication and interchange platform that provides a dedicated eXtensible Markup Language (XML) link to third-party content providers. The first of several DMS-Xchange offerings is DMS-Xchange for PartMiner, which is the result of an agreement between Mentor Graphics and PartMiner, Inc., a supplier of electronic component information services to the electronics industry. DMS-Xchange for PartMiner allows DMS2002 users with PartMiner subscriptions to incorporate PartMiner component data into their company's library as Computer-Aided Engineering (CAE) symbols and component information.

In other news from Mentor Graphics, special editions of its ModelSim simulator and LeonardoSpectrum synthesis tools will be included with other leading PLD design tools in a new self-study program for learning PLD design and Verilog, a hardware description language (HDL), the company said. This program is aimed at allowing tomorrow's PLD engineers to familiarize themselves with leading-edge simulation and synthesis tools they will use in the future to create complex, multi-million gate designs. Verilog Computer-Based Training Course (Verilog CBT), published by McGraw-Hill, is a CD-ROM that can be used by engineering students and entry-level designers to learn how

to create textual representations of digital designs. The training software provides a unique learning environment, designed to provide value to each individual user's needs and skill levels. The Verilog CBT includes training software, quizzes, projects, language reference manuals, software manuals, and language and software tutorials. In addition to ModelSim and LeonardoSpectrum, also included in Verilog CBT is the web edition of Altera's Quartus II design software, used for advanced PLD and SoC designs.

Verilog CBT was created by Dr. Zainalabedin Navabi, expert and author of several publications related to Verilog, including, Verilog Digital System Design, and VHDL: Analysis and Modeling of Digital Systems. Dr. Zainalabedin Navabi is an associate professor of electrical and computer engineering at Northeastern University. He holds doctorate and master's degrees in electrical engineering from the University of Arizona and a bachelor's degree in electrical engineering from the University of Texas at Austin. Navabi has authored several books and technical papers on Verilog and VHDL, including VHDL: Analysis and Modeling of Digital Systems, currently in its second edition.

Verilog CBT is available now and carries a list price of $199.95 and is available from McGraw-Hill at www.books.mcgraw-hill.com, amazon.com and other online retailers.

The Open SystemC Initiative (OSCI), an independent non-profit organization dedicated to supporting and advancing SystemC as an open source industry standard for system-level design, today announced the election of its new officers including Dr. Guido Arnout, Chairman of CoWare, Inc., as the newly appointed Chief Strategy Officer (CSO). The Chief Strategy Officer's primary responsibility will be to ensure that OSCI strategy is created, coordinated, communicated and executed. As such, the CSO will play an integral role in the identification and implementation of all OSCI technical activities, providing clear direction and strategic guidance to the working groups currently focused on

key design issues such as verification and Intellectual Property (IP) modeling and integration. The addition of the Chief Strategy Officer comes as the momentum grows towards designing at higher levels of abstraction to meet chip complexity requirements and as the need grows for standardization of a system level-modeling platform that benefits the entire electronics industry.

PDF Solutions, Inc. announced that it is working with Tower Semiconductor Ltd. in a program to achieve best-in-class yield and performance of 0.18-micron CMOS process technology at Tower's Fab 2. The Tower project calls for PDF's technologies to be implemented on a broad scale, preparing Tower's new Fab 2 process technology to achieve maximum yield from all of its process-modules and to speed yield ramp for a wide range of semiconductor products from multiple customers. By proactively using PDF Solutions' technologies, Tower said it seeks to avoid typical product-specific yield loss mechanisms that are characteristic of fabrication facilities manufacturing many different

products. Tower's new Fab 2 facility, currently prototyping 0.18 um micron products, is expected to begin volume production by year-end 2002. The facility will produce up to 33,000 200 mm wafers per month, the companies reported.