Intel FinFETs vary, may need SOI for shrink, says GSS

LONDON – Intel's 22-nm FinFETs show physical variability according to cross-sectional photographs from engineering consultancy Chipworks Inc. (Ottawa, Ontario) and EDA company Gold Standard Simulations Ltd. (GSS) has attempted to model electrical characteristics of various examples.

One conclusion drawn by Professor Asen Asenov, CEO of GSS (Glasgow, Scotland), is that Intel may need to turn to silicon-on-insulator wafers to scale its FinFETs below 22-nm. This may also have implications for foundries which are yet to introduce FinFET technology into their chip manufacturing processes.

GSS has already done some TCAD simulation of FinFETs and posted findings in a blog that discussed the fact that at 22-nm Intel's FinFETs are trapezoidal rather than rectangular in cross-section (see Intel's FinFETs are less fin and more triangle).

The latest GSS blog seeks to compare the on-current of differently-shaped FinFETs. It points out that in logic applications multiple fins are connected in parallel, resulting in an averaging of their characteristics, but in SRAM circuits the variability of a single fin is a key characteristic and performance limiter.

The characteristic dimensions of three FinFETs were fed into the GSS Garand simulator and it revealed that at 22-nm, nature appears to have worked to Intel's advantage. "Despite significant differences in the shape of the three fins, the difference in the on-current is within a 4 percent range," the blog states.

"Compared with process variation across the chip or across the wafer 4 percent is small. But it is additional variation," Professor Asenov told EE Times. He added that the simulation revealed that the FinFET process technology is complex and difficult to implement, partly because of the lack of a planarization process that can level-up shallow trench isolation oxides between transistors. One result of this is that bulk FinFET heights can vary, he said.

Professor Asenov admitted that a number of assumptions have to be made to allow the simulations to run. It is assumed that the fin itself is virtually undoped but there is a punch-through stopper dopant region beneath the fin. "We don't know about dopant profiles and strain, but we have tried to make favorable assumptions," said Professor Asenov.

Click on image to enlarge.

Dependence of on-current, ION, on gate length. Source: GSS

GSS has included results for simulations of rectangular cross-section FinFETs with 10-nm and 8-nm widths hinting at where the company thinks Intel must go next. "If you can make them [FinFETs] rectangular you will gain significantly in terms of performance, about a 20 percent gain."

Professor Asenov said that moving from bulk FinFETs to FinFETs constructed on SOI wafers could solve a number of problems. "The buried oxide layer means you don't have the problem of filling trenches. The height of the fin is determined by the depth of the silicon above the oxide."

Professor Asenov added: "I think Intel just survived at 22-nm. I think bulk FinFETs will be difficult to scale to 16-nm or 14-nm. I think that SOI will help the task of scaling FinFETs to 16-nm and 11-nm. Of course, the wafers are more expensive, but you save money with less processing."

Researchers from GSS and the University of Glasgow published a paper at the International Electron Devices Meeting of 2011 that dealt with FinFETs implemented in SOI wafers and how they could meet the low statistical variability requirements of 11-nm CMOS.

First, Professor Asenov doesn’t address the floating body (Kink effect) and self-heating effects that are intrinsic to the FinFETs on SOI. Second, please see the three different fin shapes as shown in Fin 1, Fin 2 and Fin 3. Their shapes are quite different even seen by naked eyes. Despite such differences the on-current, I-ON is not significantly different or only within 4 percent range according to Prof. Asenov. This is indeed negligibly small compared with process variation across the chip or across the wafer. How this can be? Such small difference in the I-ON may be due to the differences in the volume inversion for the different fin shapes. Each fin has different volume inversion at the upper part and full depletion at the lower part because of the trapezoidal fin shape. The volume inversion contributes higher I-ON than the fully depleted case. The narrowest at the top fin (Fin 3) has the largest volume inversion, Fin 1 is next, and Fin 2 is the least or may be no volume inversion. As a result, the I-ON of each fin ends up in being almost equal, although significant differences in the shapes of three fins. It shows the fin shape is not a big concern for FinFETs on BULK. S. kim

No disrespect, but; I am always amazed how arrogantly Intel outsiders always "believe" they know better; when, as Chipguy1 correctly noted, "Intel is a ... data driven company" and the_floating_ gate posted M. Bohr's "one on one" discussion of balanced mix of concerns and factors that Intel weights when choosing a technology.
I guess we will see who has the last word
"Finfets need to be on SOI". I think both you and he will be proven right."

Man. I agree with GSS. I am designer now with past process training. We dont bin our parts so this variation woulld be a big issues. Do I really want to make each transistor on a random plane versus standard 100 surface?
At least if fin was vertical I would have consistent 110 plane. When I look at the 3 fins it's a crap shoot what plane of silicon transistor is fabricated on.

For the first time, at the 2012 Symposium on VLSI Technology (June 12 - 15), Intel will be reporting technical details of its state-of-the-art
Tri-gate 22-nm CMOS technology on bulk silicon which has entered volume production.
Program information about the two VLSI Symposia can be viewed here (Technology): http://www.vlsisymposium.org/technology/technical.html
and (Circuits): http://www.vlsisymposium.org/circuits/technical.html

While Intel has undoubtedly developed it's own proprietary approach to deal with the channel height definition and short channel leakage problems alluded to by Professor Asenov regarding
"bulk" devices, these problems were actually anticipated some time ago by HiperSem through the incorporation of a dual-polarity source/drain
architecture.
http://www.hipersem.com/technology.htm
The use of a dual-polarity source/drain device
architecture solves a number of problems and creates additional opportunities simultaneously by defining the active channel height according to the "depth" of the source drain junction, as opposed to the height of the "fin" itself.