Z80 32KB address space is mapped to A0xxxx on 68K. Can Z80 access to its own space using A0 page in upper 32KB? Will it stop 68K while access itself address space because it uses outer loop through 68K?

The same opposite question: Z80 has special map of VDP+PSG to 7Fxx address. Can 68K access VDP/PSG on A07Fxx address? Does it need to request Z80 bus access for this address?

I guess it uses the Z80 BUS as you have to request Z80 BUS to access YM at $A04000 from the 68k. Also the YM chip cannot be connected on both BUS at the same time, as it's a 8 bit device it makes sense to connect it to the Z80 BUS.

Having a consistent mapping is not the same thing as using the same mapping circuitry. Since the only thing the 68000 can access in "z80 space" is the ram and FM, I'd be more inclined to believe it's not using the same mapping. They simply made the ram and FM map in a similar place to make it easier on programmers to remember. Now if someone can make a demo showing the 68000 controlling the z80 rom bank register or the VDP through the z80 mapping, then I'd be inclined to believe it's accessing the actual z80 mapper.

I recall that trying to access the bank window from the 68000 side results in a hang up so huh, I do believe it indeed maps to the Z80 bus. Besides making it not be the case would probably make the whole thing more complex as it'd be working on exceptions to the rule instead.

What kind of test ROM would work here? :/

(and again… we also should just see what the bus arbitrer does anyway, which was the whole point of the thread)

I believe that if both buses were interconnected a death lock could take place when both processors try to connect to the other processor bus.
I have found other reasons to not do that, but that one seems definitive.

I also don't recall that paradigm in multiprocessor word, I suppose that's the reason.

Z80 32KB address space is mapped to A0xxxx on 68K. Can Z80 access to its own space using A0 page in upper 32KB? Will it stop 68K while access itself address space because it uses outer loop through 68K?

The same opposite question: Z80 has special map of VDP+PSG to 7Fxx address. Can 68K access VDP/PSG on A07Fxx address? Does it need to request Z80 bus access for this address?

3. Addresses A08000-A0FFFFh mirror A00000-A07FFFh, so the 68000 cannot access it's own banked memory. All addresses are valid except for the VDP which is at A07F00-A07FFFh and A0FF00-A0FFFFh, writing or reading those addresses will lock up the machine.

In my own tests, I've been unable to do the following:
- Read banked 68000 RAM. (returns FFh)
- Find result of partial writes to the bank address register.
- Have the Z80 read A00000-A0FFFF through the banked memory area.
(locks up the machine)

3. Addresses A08000-A0FFFFh mirror A00000-A07FFFh, so the 68000 cannot access it's own banked memory. All addresses are valid except for the VDP which is at A07F00-A07FFFh and A0FF00-A0FFFFh, writing or reading those addresses will lock up the machine.

In my own tests, I've been unable to do the following:
- Read banked 68000 RAM. (returns FFh)
- Find result of partial writes to the bank address register.
- Have the Z80 read A00000-A0FFFF through the banked memory area.
(locks up the machine)

Taken both quotes together, it sounds more like the 68000 map decodes mirrors of A00000 for z80 ram, and mirrors of A04000 for FM, and nothing else. He's not sure it does anything at all for the bank address, and freezing for VDP space could just be the mapper not asserting DTACK for an unmapped location, which we know it does (like at 800000 and 900000).

Taken both quotes together, it sounds more like the 68000 map decodes mirrors of A00000 for z80 ram, and mirrors of A04000 for FM, and nothing else. He's not sure it does anything at all for the bank address, and freezing for VDP space could just be the mapper not asserting DTACK for an unmapped location, which we know it does (like at 800000 and 900000).

Apparently, that is not the case.

gen-hw.txt wrote: The 68000 can write to A06000h to set up the bank address.

I am pretty sure the Bus Arbiter decodes 68k and z80 bus access as usual in case of 68k access to z80 bus or z80 access to 68k bus (there are likely two decoding logic running in parallel and this looks more complicated to have one decoding logic disabled when the other decodes specific memory range). Address and Data buses are connected through the I/O chip (315-5309 in model 1 VA0-VA4) which is controlled by Bus Arbiter through VTOZ and ZTOV signals when access is made to $a00000-$a0ffff on one side or $7f00-$ffff on the other side.

The reason access to VDP from 68k through Z80 address locks the system is likely due to the fact Bus Arbiter requests 68k bus in case of access to 68k bus from Z80 bus master but since 68k is the initiator of the access and is waiting for !DTACK to complete the bus cycle, 68k bus access is never granted.

Similarly, the reason access to Z80 area from 68k bank locks the system is probably that Bus Abitrer waits for z80 bus to be released before doing an access to z80 bus from 68k bus but this never happens since z80 is master of the bus. This one might be a little more complicated since we know that accessing z80 memory are from 68k without having requested z80 bus first does not lock the system.

gen-hw.txt wrote: The Z80 bus can only be accessed by the 68000 when the Z80 is running
and the 68000 has the bus. (as opposed to the Z80 being reset, and/or
having the bus itself)
Otherwise, reading $A00000-A0FFFF will return the MSB of the next
instruction to be fetched, and the LSB will be set to zero. Writes
are ignored. This even applies to the VDP area that would normally
lock up the machine.

Well, it does sound like A0xxxx does just address the z80 decoder then. Mostly. As said earlier, the z80 rom bank is apparently not part of that. I wonder if that's because it's handled separately on the z80 side, or if one less address line from the 68000 feeds the decoder. That would prevent recursive mapping while needing one less needed pin on the chip.

Well, I/O chip only connects VA1-VA7 and ZA1-ZA7, the rest of address lines are managed by the Bus Arbiter so the most logical is that it sets ZA0 according to !LDS, ZA8-ZA14 with VA8-VA14 and simply forces ZA15 low to prevent access to Z80 bank area, just like it sets VA15-VA23 with bank register settings when ZA15 is High.