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The MMU-500 applies the following logical processing steps
to every transaction:

Determines
the security state of the device that originates the transaction.
The security attribute presented on AWPROT[1] and ARPROT[1] signals is different from
the security state of the device. Identifying the security state
of the device is called security state determination.

Maps an incoming transaction to one of the contexts
using an incoming StreamID.

Caches frequently used address ranges using the
TLB. The best-case hit latency of this caching is two clocks when
the TBU address slave register slices are not implemented. The best-case
latency is three clocks when the TBU address slave register slices
are specified.

Performs the main memory PTW automatically on an
address miss.

The MMU-500 shares the page
table formats with the processor as specified in the Large
Physical Address Extension (LPAE) for maximum efficiency.