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Abstract:

In at least one embodiment, a controller allows triac-based dimmer to
properly function and dim a load whose voltage is regulated by a
switching power converter. In at least one embodiment, the switching
power converter includes a switch to control voltage conversion of an
input voltage to the switching power converter, wherein phase delays are
introduced in the input voltage by a triac-based dimmer during a dimming
period. In at least one embodiment, the controller is configured to
control the switch of the switching power converter to establish an input
resistance of the switching power converter during a dimming portion of
the input voltage, wherein the input resistance allows the triac-based
dimmer to phase modulate a supply voltage to the dimmer so that an output
voltage of the dimmer has a substantially uninterrupted phase delay
during each half-cycle of the supply voltage during the dimming period.

Claims:

1. A controller to control a switching power converter and provide
compatibility between the switching power converter and a triac-based
dimmer, wherein the switching power converter includes a switch to
control voltage conversion of an input voltage to the switching power
converter, the controller comprising: one or more components to control
the switch of the switching power converter to establish an input
resistance of the switching power converter during a dimming portion of
the input voltage, wherein the input resistance allows the triac-based
dimmer to generate a phase modulated input voltage to the switching power
converter having a substantially uninterrupted phase delay during each
half-cycle of the input voltage during a dimming period.

2-25. (canceled)

Description:

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation of co-pending application Ser.
No. 12/347,138, filed Dec. 31, 2008, which claims priority under 35
U.S.C. § 119(e) to U.S. Provisional Application No. 61/083,717,
filed Jul. 25, 2008, both of which are incorporated herein by reference
in their entirety.

[0002] U.S. patent application Ser. No. 11/967,269, entitled "Power
Control System Using a Nonlinear Delta-Sigma Modulator with Nonlinear
Power Conversion Process Modeling," inventor John L. Melanson, Attorney
Docket No. 1745-CA, and filed on Dec. 31, 2007 describes exemplary
methods and systems and is incorporated by reference in its entirety.
Referred to herein as Melanson I.

[0008] The present invention relates in general to the field of signal
processing, and more specifically to a system and method that includes
switching power converter control with triac-based leading edge dimmer
compatibility.

[0009] 2. Description of The Related Art

[0010] Power control systems often utilize a switching power converter to
convert alternating current (AC) voltages to direct current (DC) voltages
or DC-to-DC. Power control systems often provide power factor corrected
and regulated output voltages to many devices that utilize a regulated
output voltage. Switching power converters have been used as interfaces
between triac-based dimmers and loads. The load can be virtually any load
that utilizes converted power, such as one or more light emitting diodes
(LEDs).

[0011] LEDs are becoming particularly attractive as main stream light
sources in part because of energy savings through high efficiency light
output and environmental incentives such as the reduction of mercury.
LEDs are semiconductor devices and are driven by direct current. The
lumen output intensity (i.e. brightness) of the LED approximately varies
in direct proportion to the current flowing through the LED. Thus,
increasing current supplied to an LED increases the intensity of the LED
and decreasing current supplied to the LED dims the LED. Current can be
modified by either directly reducing the direct current level to the
white LEDs or by reducing the average current through duty cycle
modulation.

[0012] Dimming a light source saves energy when operating a light source
and also allows a user to adjust the intensity of the light source to a
desired level. Many facilities, such as homes and buildings, include
light source dimming circuits (referred to herein as "dimmers"). Power
control systems with switching power converters are used to control
constant current light sources. However, conventional dimmers, such as a
triac-based dimmer, that are designed for use with resistive loads, such
as incandescent light bulbs, often do not perform well when supplying a
raw, phase modulated signal to a reactive load such as a switching power
converter.

[0013] FIG. 1 depicts a power control system 100, which includes a
switching power converter 102. Voltage source 101 supplies an AC supply
voltage VIN to a triac-based dimmer 104. The voltage source 101 is,
for example, a public utility, and the supply voltage VIN is, for
example, a 60 Hz/110 V line voltage in the United States of America or a
50 Hz/220 V line voltage in Europe. Dimmer 104 receives the supply
voltage VIN and generates a dimmer voltage
V.sub.Φ--DIM. During a dimming period, dimmer 104 phase
modulates the supply voltage VIN by introducing phase delays a into
the beginning of each half cycle of dimmer voltage
V.sub.Φ--DIM. "α" represents an amount of time
between the beginning and leading edge of each half cycle of dimmer
voltage V.sub.Φ--DIM. ("Introducing phase delays" is also
referred to as "chopping"). The portion of the dimmer voltage
V.sub.Φ--DIM having a phase delay a is referred to as the
"dimming portion". As subsequently described in more detail, the amount
of phase delay a depends upon the amount of selected dimming When dimmer
104 is not in a dimming period, i.e. dimmer 104 is not set to phase
modulate the supply voltage VIN, the phase delay a is zero, and
dimmer 104 simply passes the supply voltage VIN to full bridge diode
rectifier 103. Rectifier 103 rectifies the dimmer voltage
V.sub.Φ--DIM and supplies a rectified, time-varying, line
input voltage V.sub.Φ--RECT to the switching power
converter 102.

[0014] The power control system 100 includes a PFC and output voltage
controller 114 to control power factor correction and regulate an output
voltage VLINK of switching power converter 102. The PFC and output
voltage controller 114 controls an ON (i.e. conductive) and OFF (i.e.
nonconductive) state of switch 108 by varying a state of pulse width
modulated control signal CS0. Switching between states of switch 108
regulates the transfer of energy from the rectified line input voltage
V.sub.Φ--RECT through inductor 110 to capacitor 106. The
inductor current iL ramps `up` when the switch 108 is ON. The
inductor current iL ramps down when switch 108 is OFF and supplies
current iL to recharge capacitor 106. The time period during which
inductor current iL ramps down is commonly referred to as the
"inductor flyback time". During the inductor flyback time, diode 111 is
forward biased. Diode 111 prevents reverse current flow into inductor 110
when switch 108 is OFF. In at least one embodiment, the switching power
converter 102 operates in discontinuous current mode, i.e. the inductor
current iL ramp up time plus the inductor flyback time is less than
the period of the control signal CS0. When operating in continuous
conduction mode, the inductor current iL ramp-up time plus the
inductor flyback time equals the period of control signal CS0.

[0015] The switch 108 is a field effect transistor (FET), such as an
n-channel FET. Control signal CS0 is a gate voltage of switch 108,
and switch 108 conducts when the pulse width of CS0 is high. Thus,
the `ON time` of switch 108 is determined by the pulse width of control
signal CS0.

[0016] Capacitor 106 supplies stored energy to load 112. The capacitor 106
is sufficiently large so as to maintain a substantially constant output
voltage VLINK, as established by PFC and output voltage controller
114. As load conditions change, the output voltage VLINK changes.
The PFC and output voltage controller 114 responds to the changes in
output voltage VLINK and adjusts the control signal CS0 to
restore a substantially constant output voltage VLINK as quickly as
possible. Power control system 100 includes a small, filter capacitor 115
in parallel with switching power converter 102 to filter any high
frequency signals from the input voltage V.sub.Φ--RECT.

[0017] The goal of power factor correction technology is to make the
switching power converter 102 appear resistive to the voltage source 101.
Thus, PFC and output voltage controller 114 attempts to control the
inductor current iL so that the average inductor current iL is
linearly and directly related to the line input voltage
V.sub.Φ--RECT. Prodi , Compensator Design and Stability
Assessment for Fast Voltage Loops of Power Factor Correction Rectifiers,
IEEE Transactions on Power Electronics, Vol. 22, No. 5, September 2007,
pp. 1719-1729 (referred to herein as "Prodi "), describes an example of
PFC and output voltage controller 114.

[0018] In at least one embodiment, the values of the pulse width and duty
cycle of control signal CS0 depend on sensing two signals, namely,
the input voltage V.sub.Φ--RECT and the capacitor
voltage/output voltage VLINK. PFC and output voltage controller 114
receives the input voltage V.sub.Φ--RECT and the output
voltage VLINK respectively via a wide bandwidth current loop 116 and
a slower voltage loop 118. The input voltage V.sub.Φ--RECT
is sensed from node 120 between the diode rectifier 103 and inductor 110.
The output voltage VLINK is sensed from node 122 between diode 111
and load 112. The current loop 116 operates at a frequency fc that
is sufficient to allow the PFC and output voltage controller 114 to
respond to changes in the line input voltage V.sub.Φ--RECT
and cause the inductor current iL to track the input voltage
V.sub.Φ--RECT to provide power factor correction. The
current loop frequency is generally set to a value between 20 kHz and 130
kHz. The voltage loop 118 operates at a much slower frequency fv,
typically 10-20 Hz. By operating at 10-20 Hz, the voltage loop 118
regulates slow variations in the output voltage VLINK due to AC line
voltage fluctuations in amplitude.

[0019] FIG. 2 (labeled prior art) depicts a triac-based power and dimming
system 200 that includes a triac-based dimmer 202. Potentiometer 204
conducts current Ito charge capacitor 206. During a dimming period, diac
208 blocks current to triac 210 until capacitor 206 reaches a breakover
voltage of diac 208. When capacitor 206 reaches the breakover voltage,
diac 208 conducts, and capacitor 206 discharges through diac 208. When
capacitor 206 discharges, capacitor 206 supplies a current to triac 210,
and triac 210 conducts. The time between when the supply voltage VIN
crosses zero and when the triac 210 conducts represents the phase delay a
of dimmer voltage V.sub.Φ--DIM. The resistance of
potentiometer 204 sets the value of phase delay a. The resistance R of
potentiometer 204 and capacitance C of capacitor 206 form an RC time
constant that determines a phase delay a (FIG. 3) of dimmer voltage
VDIM. Increasing R increases the phase delay α, and decreasing
R decreases the phase delay α. When R is decreased sufficiently,
the phase delay α is essentially zero, and, thus,
V.sub.Φ--DIM=VIN. The value of R is set by
potentiometer 204. The value of C and the range of R are matters of
design choice.

[0020] When the phase delay a is zero, dimmer 202 stops dimming In at
least one embodiment, when dimmer 202 is dimming and the supply voltage
VIN reaches 0, diac 208 and triac 210 stop conducting. When dimming,
the alternating conduction/nonconduction of triac 210 modulates the phase
of the supply voltage VIN. Resistor 214, capacitor 216, and inductor
218 provide high frequency rejection for dimmer 202.

[0021] Referring to FIGS. 1 and 2, controller 114 operates switch 108 to
provide power factor correction so that input current iL tracks
changes in input voltage V.sub.Φ--RECT. In at least one
embodiment, when the input voltage V.sub.Φ--RECT approaches
a zero crossing, a very low input resistance is presented. Presenting a
very low input resistance to a triac-based dimmer 104 can cause the triac
210 to turn ON and OFF multiple times during a single half cycle of input
voltage V.sub.Φ--RECT. As discussed in more detail below,
oscillations in the conduction of triac 210 during a single half cycle of
input voltage V.sub.Φ--RECT can cause problems, such as
flicker in a lamp when load 112 includes a lamp.

[0022]FIG. 3 depicts a series of ideal voltage waveforms 300 that
represent two respective cycles of waveforms present in an ideal power
and dimming system 200 during two dimming periods. Referring to FIGS. 1,
2, and 3, supply voltage VIN is a sine wave depicted with two
exemplary cycles 302 and 304. Dimmer 104 generates the phase modulated
voltage V.sub.Φ--DIM by chopping each half cycle of supply
voltage VIN to ideally generate one, leading edge phase delay
α1 for each respective half cycle of cycle 306. The phase delays a
of the phase modulated signal V.sub.Φ--DIM increase as the
dimming level increases, i.e. as phase delays a increase, less power is
delivered to load 112. If load 112 is a lamp, dimming level increases
correspond to decreases in brightness of the lamp. Half cycle 308
indicates a longer phase delay α2 corresponding to a decrease in
dimming level. The exemplary leading edge phase delays α1 and
α2 represent the elapsed time between a beginning of a half cycle
and a leading edge of dimmer voltage V.sub.Φ--DIM. The
cycles 310 and 312 of rectified input voltage V.sub.Φ--RECT
have the same respective phase delays α1 and α2 as the phase
modulated signal V.sub.Φ--DIM. The phase delayed portions
of voltages V.sub.Φ--DIM and V.sub.Φ--RECT
represented by α1 and α2 are also referred to as the "dimming
portion" of voltages V.sub.Φ--DIM and
V.sub.Φ--RECT.

[0023] As previously mentioned, conventional dimmers, such as triac-based
dimmer 202, that are designed for use with resistive loads, such as
incandescent light bulbs, often do not perform well when supplying a
phase modulated signal V.sub.Φ--DIM to a reactive load such
as switching power converter 102. For example, when supplying a reactive
load, the dimmer 202 can miss generating phase delays in some cycles of
phase modulated signal V.sub.Φ--DIM and can generate ripple
during the phase delays. Exemplary problems with at least one
conventional triac-based dimmer when used with a reactive load are
described in Rand et al., "Issues, Models and Solutions for Triac
Modulated Phase Dimming of LED Lamps", June, 2007, pages 1398-1404 of
Power Electronics Specialists Conference, 2007. PESC 2007, published by
the Institute of Electrical and Electronic Engineers, ISBN
978-1-4244-0655-5. Thus, although the rectified input voltage
V.sub.Φ--RECT ideally has one phase delay per cycle during
dimming, when driving a reactive load, such as a switching power
converter 102, problems such as missing phase delays and multiple phase
delays a in a single half cycle of the rectified input voltage
V.sub.Φ--RECT exist.

[0024] Although minor ripple may be present during the dimming portion of
the input voltage V.sub.Φ--RECT, the multiple phase delays
a during a single half cycle of input voltage V.sub.Φ--RECT
cause significant interruptions in the initial phase delay a of the input
voltage V.sub.Φ--RECT. In at least one embodiment, triac
210 (FIG. 2) turning ON and OFF multiple times during a single half cycle
of input voltage V.sub.Φ--RECT causes the significant
interruptions in the initial phase delay a of the input voltage
V.sub.Φ--RECT. When triac 210 (FIG. 2) turns ON and OFF
multiple times during a dimming portion of a half cycle of input voltage
V.sub.Φ--RECT, the input voltage
V.sub.Φ--RECT increases and decreases multiple times during
the dimming portion of the half cycle of input voltage
V.sub.Φ--RECT. Multiple oscillations of the input voltage
V.sub.Φ--RECT during a half cycle of the input voltage
V.sub.Φ--RECT can cause problems such as flicker of a lamp
load.

[0025] Conventional solutions to the problem of interfacing a triac-based
dimmer with a reactive switching power converter 102 involve adding
additional components to, for example, discharge the filter capacitor 115
during the dimming portion of dimmer voltage V.sub.Φ--DIM.

[0026] FIGS. 4A and 4B (collectively referred to as FIG. 4) depict an LED
driver circuit 400 available from Supertex, Inc. of Sunnyvale, Calif.,
USA. LED driver circuit 400 represents one embodiment of light source
driver circuit 106. The LED driver circuit 400 is described in more
detail in Supertex design note DN-H05 available from Supertex, Inc. The
LED driver circuit 400 includes two extra circuits, damper circuit 402
and bleeder circuit 404 to provide compatibility with a dimmer, such as
dimmer 104. According to DN-H05, the damper circuit 402 provides damped
charging of the driver's input filter circuit at P16. The damper circuit
402 provides resistive damping to prevent AC line input current
oscillations due to a sudden rise of an AC line voltage, such as the
edges of dimmer voltage V.sub.Φ--DIM. The bleeder circuit
404 provides a nominal 1 kohm load to a rectified AC line at P21 to
suppress a voltage rise at the input capacitors C21-C23 due to leakage
current of diac 208 and triac 210 (FIG. 2) during dimming portions of
dimmer voltage V.sub.Φ--DIM which could otherwise cause
flicker of a lamp driven by LED driver circuit 400.

[0027] FIG. 5 depicts a unity power factor LED lamp driver 500, which
represents one embodiment of light source driver circuit 106. The LED
lamp driver 500 is described in more detail in Supertex application note
AN-H52 available from Supertex, Inc. LED lamp driver 500 includes damping
circuitry 502 to add a load to dimmer 104 during dimming portions of the
dimmer voltage V.sub.Φ--DIM. The damping circuitry 502
includes a bleeder resistor RBL that is connected by transistor M2
during the dimming portions of dimmer voltage V.sub.Φ--DIM
to lamp driver 500. When transistor M2 conducts, the bleeder resistor
RBL provides an added load to the AC line at VIN to dampen the
dimmer voltage V.sub.Φ--DIM during dimming portions. Adding
an extra transistor M2 and resistor RBL increases the system cost of
lamp driver 500.

[0028] It would be desirable to reduce or eliminate the extra components
of LED driver circuit 400 and LED lamp driver 500 that provide a load to
dimmer 104 during the dimming portion of dimmer voltage
V.sub.Φ--DIM. It would also be desirable to reduce or
eliminate the power consumption of resistive loads added by LED driver
circuit 400 and LED lamp driver 500 that provide a load to dimmer 104
during the dimming portion of dimmer voltage V.sub.Φ--DIM.

SUMMARY OF THE INVENTION

[0029] In one embodiment of the present invention, a controller is
configured to control a switching power converter and provide
compatibility between the switching power converter and a triac-based
dimmer. The switching power converter includes a switch to control
voltage conversion of an input voltage to the switching power converter.
The controller includes one or more components to control the switch of
the switching power converter to establish an input resistance of the
switching power converter during a dimming portion of the input voltage.
The input resistance allows the triac-based dimmer to generate a phase
modulated input voltage to the switching power converter having a
substantially uninterrupted phase delay during each half-cycle of the
input voltage during a dimming period.

[0030] In another embodiment of the present invention, a method to control
a switching power converter and provide compatibility between the
switching power converter and a triac-based dimmer, wherein the switching
power converter includes a switch to control voltage conversion of an
input voltage to the switching power converter, includes controlling the
switch of the switching power converter to establish an input resistance
of the switching power converter during a dimming portion of the input
voltage. The input resistance allows the triac-based dimmer to generate a
phase modulated input voltage to the switching power converter having a
substantially uninterrupted phase delay during each half-cycle of the
input voltage during a dimming period.

[0031] In a further embodiment of the present invention, an electronic
system includes a switching power converter to convert an input voltage
to the switching power converter. The switching power converter includes
a switch to control voltage conversion of the input voltage to the
switching power converter into the output voltage. The input voltage to
the switching power converter is phase modulated during dimming periods
by a triac-based dimmer. The electronic system also includes a
controller, coupled to the switching power converter, to control the
switch of the switching power converter to establish an input resistance
of the switching power converter during a dimming portion of the input
voltage. The input resistance allows the triac-based dimmer to generate a
phase modulated input voltage to the switching power converter having a
substantially uninterrupted phase delay during each half-cycle of the
input voltage during a dimming period.

BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The present invention may be better understood, and its numerous
objects, features and advantages made apparent to those skilled in the
art by referencing the accompanying drawings. The use of the same
reference number throughout the several figures designates a like or
similar element.

[0033] FIG. 1 (labeled prior art) depicts a power control system having a
switching power converter.

[0044] In at least one embodiment, a controller allows triac-based dimmer
to properly function and dim a load whose voltage is regulated by a
switching power converter. In at least one embodiment, the switching
power converter includes a switch to control voltage conversion of an
input voltage to the switching power converter, wherein phase delays are
introduced in the input voltage by a triac-based dimmer during a dimming
period. In at least one embodiment, the controller is configured to
control the switch of the switching power converter to establish an input
resistance of the switching power converter during a dimming portion of
the input voltage, wherein the input resistance allows the triac-based
dimmer to phase modulate a supply voltage to the dimmer to generate a
dimmer output voltage having a substantially uninterrupted phase delay
during each half-cycle of the supply voltage during the dimming period.
In at least one embodiment, the input resistance allows the triac-based
dimmer to phase modulate the supply voltage so that the output voltage of
the dimmer has a single, uninterrupted phase delay during each half cycle
of the input voltage. In at least one embodiment, phase modulating the
supply voltage introduces a leading edge phase delay in each cycle of the
input voltage, and each phase delay has a duration of less than one-half
of the period of each cycle of the input voltage.

[0045] In at least one embodiment, the controller has two modes of
operation, a power factor correction (PFC) mode and a maintenance mode.
In at least one embodiment, the maintenance mode has an active
maintenance mode, and, in at least one embodiment, the maintenance mode
has both the active maintenance mode and a quiet maintenance mode. In the
PFC mode, the controller controls the switching power converter to
provide power factor correction and voltage regulation. When the input
voltage to the switching power converter is below a first threshold
voltage, the controller enters the active maintenance mode. In at least
one embodiment, when the input voltage further drops below a second
threshold voltage, the controller enters a quiet maintenance mode.

[0046] In the maintenance mode, the controller sets an operational
frequency and pulse width of a control signal that respectively controls
a switching frequency and ON time of the switching power converter switch
so that an input resistance to the triac-based dimmer allows the dimmer
to phase modulate the supply voltage during each half-cycle of the supply
voltage during the dimming period. In at least one embodiment, the
switching power converter includes a filter capacitor across input
terminals of the switching power converter. In the maintenance mode, the
controller controls the input resistance of the switching power converter
to allow the filter capacitor to discharge sufficiently to allow the
triac-based dimmer to phase modulate the supply voltage during each
half-cycle of the input voltage during the dimming period with a
substantially uninterrupted phase delay. In at least one embodiment, the
dimming period is substantially uninterrupted when the triac of the
triac-based dimmer does not include multiple oscillations between
conduction and nonconduction during each half cycle of the input voltage.
In at least one embodiment, when the input voltage to the switching power
converter further decreases below a second predetermined threshold, the
controller ceases operating the switch until the input voltage increases
above the first predetermined threshold.

[0047] FIG. 6 depicts power system 600, which includes a switching power
converter 602 controlled by controller 604 with dimmer compatibility.
Voltage source 101 and triac-based dimmer 603 generate the phase
modulated dimmer voltage V.sub.Φ--DIM as previously
described. Dimmer 603 includes triac 605, and, in at least one
embodiment, dimmer 603 and triac 605 are respectively configured
identically to dimmer 202 and triac 210. Full bridge diode rectifier 103
rectifies dimmer voltage V.sub.Φ--DIM to generate the
rectified input voltage V.sub.Φ--RECT to the switching
power converter 602. Filter capacitor 115 provides, for example, high
frequency filtering of the rectified input voltage
V.sub.Φ--RECT. Switching power converter 602 converts the
input voltage V.sub.Φ--RECT into a regulated output voltage
VLINK to supply a voltage to load 112. Load 112 can be any type of
load including a load having one or more LEDs. The particular
configuration of input section 608 and output section 610 is a matter of
design choice. The switching power converter 602 can be any kind of
switching power converter 602, such as a buck converter, boost converter,
boost-buck converter, and a Ca converter.

[0048] Controller 604 generates switch control signal CS1 to control
conductivity of switch 606. In at least one embodiment, switch 606 is
identical to switch 108 (FIG. 1). Controller 604 monitors the input
voltage V.sub.Φ--RECT and the link voltage VLINK.
Controller 604 controls switch 606 to provide power factor correction and
regulate link voltage VLINK. During PFC mode, controller 604
provides power factor correction for switching power converter 602 after
any phase delay a of input voltage V.sub.Φ--RECT. (A phase
delay α of 0 indicates an absence of dimming). Control of power
factor correction and the output voltage VOUT of switching power
converter 102 is, for example, described in the exemplary embodiments of
Melanson I, II, III, IV, and V.

[0049] During a dimming portion of input voltage
V.sub.Φ--RECT, controller 604 controls switch 606 so that
switching power converter 602 has an input resistance that allows
sufficient current to flow through triac 605. Allowing sufficient current
to flow through triac 605 allows the triac 605 to properly operate. In at
least one embodiment, proper operation of dimmer 603 occurs when dimmer
603 is set to provide a phase delay in input voltage
V.sub.Φ--RECT and dimmer 603 phase supply voltage VIN
to generate an input voltage V.sub.Φ--RECT with a
substantially uninterrupted phase delay during each half cycle of input
voltage V.sub.Φ--RECT during a dimming period. Exemplary
waveforms of voltages V.sub.Φ--DIM and
V.sub.Φ--RECT indicating proper operation of dimmer 603 are
set forth in FIG. 3. In at least one embodiment, proper operation of
triac 605 includes preventing the triac 605 from oscillating during
subsequent dimming periods.

[0050] In at least one embodiment, controller 604 has two modes of
operation, PFC mode and maintenance mode. In at least one embodiment, the
maintenance mode has two modes of operation, the active maintenance mode
and the quiet maintenance mode. During any phase delay a of input voltage
V.sub.Φ--RECT, controller 604 operates in maintenance mode.
During maintenance mode, controller 604 causes switching power converter
602 to have an input resistance that allows dimmer 603 to generate a
phase modulated input voltage V.sub.Φ--RECT with a
substantially uninterrupted phase delay a during each half-cycle of the
input voltage V.sub.Φ--RECT during the dimming period. In
at least one embodiment, controller 604 establishes an input resistance
REFF during the maintenance mode that allows the triac-based dimmer
603 to phase modulate the supply voltage VIN so that input voltage
V.sub.Φ--RECT has a single, uninterrupted phase delay
during each half cycle of the input voltage V.sub.Φ--RECT.
In at least one embodiment, phase modulating the supply voltage VIN
introduces a leading edge phase delay a in each cycle of the input
voltage V.sub.Φ--RECT, and each phase delay a has a
duration of less than one-half of the period of each cycle of the input
voltage V.sub.φ--RECT.

[0051] During PFC mode, the switching frequency of switch 606 is nominally
40 kHz-120 kHz. However, switching at such high frequencies during a
phase delay of input voltage V.sub.Φ--RECT is inefficient
because very little voltage is presented to the load 112 during the phase
delay of input voltage V.sub.Φ--RECT. Thus, power is
consumed by switch 606 with very little power delivered to load 112.

[0052] FIG. 7 depicts a circuit model 700 of power system 600 when
controller 604 operates in maintenance mode. Referring to FIGS. 6 and 7,
in maintenance mode, controller 604 generates control signal CS1 so
that the input impedance of switching power converter 602 appears as a
resistive load 602E having an effective resistance REFF. The
effective resistance REFF of load 602E is a matter of design choice.
In at least one embodiment, the effective resistance REFF, as
established by controller 604, provides a sufficient discharge path for
capacitor 115 to allow current to keep the triac 605 conducting during
the dimming portion of voltage V.sub.Φ--DIM. In at least
one embodiment, controller 604 causes switch 606 to switch as slowly as
possible to establish an effective resistance REFF that allows the
triac of dimmer 603 to properly operate. In at least one embodiment,
controller 604 establishes the effective resistance REFF to be
between 2 kohms and 5 kohms.

[0053] Although the effective resistance REFF appears as an actual
resistance to dimmer 603, effective resistance REFF does not
dissipate energy as a physical resistor does. Instead, charge from the
input current I is eventually transferred to load 112.

[0054]FIG. 8 represents power system 800, and power system 800 represents
one embodiment of power system 600. Power system 800 includes a switching
power converter 802, and, in one embodiment is identical to switching
power converter 102. Power system 800 also includes controller 804 with
dimmer compatibility. Controller 804 operates in maintenance mode in the
dimming portion of input voltage V.sub.Φ--RECT and
otherwise operates in PFC mode.

[0055] Signal plot 806 depicts input current iL during one period tt
of control signal CS1 with switching power converter 802 operating
in discontinuous conduction mode. During a dimming portion of input
voltage V.sub.Φ--RECT, controller 804 operates in
maintenance mode. In at least one embodiment, when operating in
maintenance mode, controller 804 operates in the active maintenance mode.
In at least one embodiment, when operating in maintenance mode,
controller 804 operates in the active maintenance mode or the quiet
maintenance mode during the dimming portion of input voltage
V.sub.Φ--RECT depending upon a value of the input voltage
V.sub.Φ--RECT.

[0056] In at least one embodiment, when operating in the active
maintenance mode, controller 804 establishes a switching frequency
fsw and amount of conduction time t1 of switch 606 to present
an effective resistance REFF to dimmer 603. Switching frequency
fsw=1/tt. In at least one embodiment, controller 804 determines an
average of input current iL (IL--avg) for a given
value of input voltage V.sub.Φ--RECT to determine the value
of effective resistance REFF. The effective resistance REFF is
related to the average input current IL--avg and the value
of input voltage V.sub.Φ--RECT by Ohm's law in Equation
[1]:

REFF=V.sub.Φ--RECT/IL--avg [1]

[0057] When switch 606 conducts for t1 seconds, the input current
iL increases. After t1 seconds, input current iL decreases
for t2 seconds. This pattern repeats for each period of tt seconds.
In at least one embodiment, for a given pulse width t1 and period u
of control signal CS1, the average input current iL is derived
and set forth in Equation [2]:

IL--avg represents the average input current iL,
V.sub.Φ--RECT represents the rectified input voltage to
switching power converter 802, VLINK represents the output voltage
of switching power converter 802, t1 represents the pulse width of
control signal CS1 and, thus, the conduction time of switch 606, tt
represents the period of control signal CS1, and L represents the
inductance of inductor 110.

[0058] From Equations [1] and [2], the effective resistance REFF is
set forth in Equation [4]:

If V.sub.Φ--RECT<<VLINK, the effective
resistance REFF is approximated by Equation [5]:

R EFF = 2 * tt * L t 1 2 [ 5 ] ##EQU00003##

[0059] Rearranging Equation [5] yields Equation [6], which solves for the
pulse width t1 of control signal CS1 in terms of the period of
control signal CS1, the inductance value L of inductor 110, and the
effective resistance REFF of switching power converter 802:

t 1 = 2 * tt * L R EFF [ 6 ] ##EQU00004##

[0060] Thus, in at least one embodiment, when operating in the active
maintenance mode, controller 804 sets a value for the period of control
signal CS1 and utilizes Equation [6] to calculate a pulse width
t1 of control signal CS1, i.e. an amount of conduction time
t1 of switch 606, to present an effective resistance REFF to
dimmer 603. Equation [5] can also be rearranged to determine a period tt
of control signal CS1 based upon a pulse width t1. The
particular inductance value L of inductor 110 is a matter of design
choice. In one embodiment, an effective resistance value REFF of 5
kohms is sufficient to discharge capacitor 115 and allow the triac of
dimmer 603 to operate properly. For a period tt of 0.5 msec and a 1 mH
value for inductor L, to achieve an effective resistance REFF of 5
kohms, controller 804 determines t1 to be approximately 14 μsec.

[0061] In at least one embodiment, the inductance value of inductor L, the
period tt of control signal CS1, and the pulse width t1 of
control signal CS1 are preset in a memory (not shown) of controller
804 in accordance with the relationship in Equation [5]. Presetting the
values of L, tt, and t1 eliminates a need for controller 804 to
determine the values and/or actually calculate the pulse width

[0062] Thus, in at least one embodiment, controller 804 can set the period
tt and pulse width t1 of control signal CS1 using, for example,
preset determinations of period tt and pulse width t1. In at least
one embodiment, controller 804 can calculate values of period tt and
pulse width

[0063] In at least one embodiment, controller 804 dithers the value of
period tt and pulse width t1 to mitigate electromagnetic
interference. In at least one embodiment, when dithering, controller 804
stores multiple values of period tt and values of pulse width t1 in
accordance with Equation [5] and utilizes the values of period tt and
pulse width t1 in accordance with a dithering algorithm. The
dithering algorithm is a matter of design choice and is, for example, a
pseudo-random selection algorithm. The exact manner of storing and/or
determining the values of variables and results in Equation [4] and/or
Equation [5] are a matter of design choice.

[0064] The particular implementation of controller 804 is a matter of
design choice. Controller 804 can be implemented using analog, digital,
or analog and digital components.

[0066] In operation 1002, processor 902 monitors the input voltage
V.sub.Φ--RECT. In operation 1003, if input voltage
V.sub.Φ--RECT is greater than or equal to active mode
threshold voltage VTH0, controller 900 operates in PFC mode 1004
until operation 1002 determines that input voltage
V.sub.Φ--RECT is less than the active mode threshold
voltage VTH0. If V.sub.Φ--RECT is less than active
mode threshold voltage VTH0, then controller 900 operates in active
maintenance mode 1006. Controller 900 can be implemented in any of a
variety of ways. In at least one embodiment, controller 900 includes an
analog-to-digital converter (ADC) to convert the input voltage
V.sub.Φ--RECT into a digital value and compares the digital
value to the active mode threshold voltage VTH0. The ADC can also be
a separate component exterior to the processor. In at least one
embodiment, the controller 900 includes analog comparators to compare the
value of input voltage V.sub.Φ--RECT to the active mode
threshold VTH0 and generate a comparison signal. In at least one
embodiment, the comparison signal is used as a basis for determining
whether controller 900 operates in PFC mode 1004 or active maintenance
mode 1006. The processor 902 can be any type of processor including a
digital signal processor. Memory 904 can be any type of memory including
a read only memory or a read-write type memory.

[0067] In at least one embodiment, the active mode threshold voltage
VTH0 is set so that the active maintenance mode 1006 is not entered
until the input voltage V.sub.Φ--RECT is close to a zero
crossing and below a breakover voltage of the diac in dimmer 603. In at
least one embodiment, the breakover voltage of the diac is 30V, and the
active mode threshold voltage VTH0 is set to 20V. Once the active
threshold voltage VTH0 is reached, controller 900 will operate
switch 606 to generate an effective input resistance REFF of
switching power converter 802 to allow the triac 605 to properly operate.
When the input voltage V.sub.φ--RECT rises above the active
threshold voltage VTH0, in at least one embodiment, the dimming
portion of input V.sub.Φ--RECT is over, i.e. dimmer 603 has
ceased chopping the supply voltage VIN, and the controller 900
operates to provide power factor correction for switching power converter
802. The particular execution frequency of triac compatibility algorithm
1000 is a matter of design choice and is preferably sufficient to allow
triac compatibility algorithm 1000 to accurately respond to changes in
the input voltage V.sub.Φ--RECT to allow triac 605 to
function properly.

[0068] When controller 900 enters active maintenance mode 1006, controller
900 generates control signal CS1 with a switch period tt of 0.5 msec
(i.e. fsw=2 kHz) and a pulse period of 14 μsec. In at least one
embodiment, the period tt is dithered to the spread the spectrum of the
control signal CS1 and mitigate electromagnetic radiation at the
switching frequency fsw. After entering active maintenance mode
1006, triac compatibility algorithm 1000 continues to monitor the input
voltage V.sub.Φ--RECT and compare the input voltage
V.sub.Φ--RECT to active mode threshold voltage VTH0.

[0069] FIG. 11 depicts a triac compatibility algorithm 1100, which, in at
least one embodiment, is represented by code stored in memory 904 and
executable by processor 902. Referring to FIGS. 8, 9, 10, and 11, in
general, triac compatibility algorithm 1000 effectively removes charge
from capacitor 115 and, thus, lowers the input voltage
V.sub.Φ--RECT to allow sufficient current to flow into
switching power converter 802 so that the triac of dimmer 603 operates
properly during a dimming portion of the input voltage
V.sub.Φ--RECT. If the input voltage
V.sub.Φ--RECT remains below a second threshold value
VTH1, triac compatibility algorithm 1100 causes controller 900 to
enter quiet maintenance mode 1104 to increase the period tt of control
signal CS1 and, thus, further reduce the amount of switching of
switch 606. Thus, by monitoring a comparison between input voltage
V.sub.Φ--RECT and thresholds VTH0 and a lower
threshold VTH1 and having active and quiet maintenance modes,
controller 900 operates switching power converter more efficiently using
triac compatibility algorithm 1100 relative to triac compatibility
algorithm 1000. If the input voltage V.sub.Φ--RECT rises
above the active threshold voltage VTH0, in at least one embodiment,
the dimming portion is over, i e dimmer 603 has ceased chopping the
supply voltage VIN, and the controller 900 operates to provide power
factor correction for switching power converter 802.

[0071] If operation 1106 determines that the input voltage
V.sub.Φ--RECT is greater than or equal to the quiet
threshold voltage VTH1, triac compatibility algorithm 1100 causes
controller 900 to enter active maintenance mode 1006. If the input
voltage V.sub.Φ--RECT is less than the quiet threshold
voltage VTH1, triac compatibility algorithm 1100 causes controller
900 to enter the quiet maintenance mode 1104. The quiet maintenance mode
1104 further reduces switching of switch 606. In at least one embodiment,
the quiet threshold voltage VTH1 is 15V. When the input voltage
V.sub.Φ--RECT decreases below the quiet threshold voltage
VTH1, in at least one embodiment, it is assumed that controller 900
does not need to pulse switch 606 to remove charge from capacitor 115.
Thus, in the quiet maintenance mode 1104, controller 900 generates
control signal CS1 so that switch 606 does not conduct.

[0072] The particular execution frequency of triac compatibility algorithm
1100 is a matter of design choice and is preferably sufficient to allow
triac compatibility algorithm 1100 to accurately respond to changes in
the input voltage V.sub.Φ--RECT to allow triac 605 to
function properly.

[0073] Accordingly, a controller controls a switching power converter to
allow the switching power converter to allow a triac-based dimmer to dim
a load, such as a lighting fixture having LEDs as light sources.

[0074] Although the present invention has been described in detail, it
should be understood that various changes, substitutions and alterations
can be made hereto without departing from the spirit and scope of the
invention as defined by the appended claims.

Patent applications by John L. Melanson, Austin, TX US

Patent applications by Mauro L. Gaetano, Austin, TX US

Patent applications by Michael A. Kost, Cedar Park, TX US

Patent applications in class Impedance or current regulator in the supply circuit

Patent applications in all subclasses Impedance or current regulator in the supply circuit