Computing in 3-D

Chips could gain depth to keep delivering on Moore’s Law

Moore’s Law, which basically states that the number of transistors that can be placed on an integrated circuit will double every 18 months, has been in effect for more than 50 years. But some are predicting that that law may be hitting a wall, perhaps as early as 2020. Two reasons stand out: increased communication times between transistors and the growing amount of energy required to run the current chip architecture.

In response, a collaboration called CMOSAIC devotes itself to building 3-D stacks of interconnected cores that will reduce information latency and energy consumption. In the end, the institutions involved—including IBM Research, the Ecole Polytechnique Federale de Lausanne (EPFL) and the Swiss Federal Institute of Technology Zurich (ETH)—hope to keep Moore’s Law essentially intact.

To learn more, IBM Systems Magazine recently spoke with Bruno Michel, manager of advanced thermal packaging, IBM Research–Zurich, and John Thome, professor of heat and mass transfer at EPFL and the CMOSAIC project coordinator. According to them, this new 3-D chip architecture will advance computing for decades to come.

IBM Systems Magazine:Would you define Moore’s Law for us?

Michel:The initial observation by Gordon Moore was that the number of transistors on a silicon chip doubles every year in a very initial state of silicon integration. That was his first paper and then five or six years later he corrected that to a long-term trend of doubling not every year but every 18 months. So that was the observation by Gordon Moore and everybody now tries to adhere to it. But to call it a law is kind of a misnomer; it’s not a law but kind of an observation or target.

“Instead of laying out chips horizontally, one after another, ... all the communication is not only lateral, but also vertical and local.” —John Thome, professor of heat and mass transfer, EPFL

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