Security Options for ARC Processors

With the vast amount of personal data stored in the cloud and transferred between smart devices, it is increasingly important to have effective security measures in place to avoid the threat of data breaches and malicious attacks.

Enhanced Security Package Option for ARC EM Cores

The Enhanced Security Package option available for DesignWare® ARC® EM Processors enables designers to create a tamper-resistant, secure environment that protects their systems and software from vulnerabilities using a single ultra-low power processor.

The option includes SecureShield™ technology to enable development of a trusted execution environment, reducing the area and power that an additional security core and associated memories would require. SecureShield technology protects critical processor registers like stack and instruction pointer registers as well as secure bus accesses, and includes a secure memory protection unit (MPU) to protect traditional instruction and data memory. The secure MPU has up to 16 configurable memory regions with the option for per region scrambling and encryption.

The Enhanced Security Package also consists of an encrypted, tamper-resistant pipeline and additional protection features such as data and instruction path integrity checks and watchdog timer to help prevent IP theft and system attacks.

Designers can also add user-defined instructions and co-processors through the ARC Processor EXtension (APEX) technology and restrict their operations to a secure mode, enabling IP protection throughout the value chain.

Enhanced Security Package Option for ARC HS Cores

The Enhanced Security Package option for ARC HS Processors enables designers to create a secure environment that protects their systems and software from evolving security threats such as IP theft and intentional remote attacks. The package includes the capability to protect critical processor registers like stack and instruction pointer registers as well as secure bus accesses and includes a memory protection unit (MPU) with up to 16 configurable memory regions to protect traditional instruction and data memory. Also included is data and instruction path integrity checks to prevent fault injection attacks, error detection codes (EDC) on memories and key registers, stack bounds checking and a watchdog timer.

As with the ARC EM processors, designers can add user-defined instructions and co-processors through the ARC Processor EXtension (APEX) technology for cryptographic or encryption purposes.