Intel Developer Zone Blogshttps://software.intel.com/en-us/blogs/all
Blog posts from the Intel Developer Zone community.enRunning “Large” Software on Wind River® Simics® Virtual Platforms, Then and Nowhttps://software.intel.com/en-us/blogs/2018/03/15/software-on-wind-river-simics-virtual-platforms-then-and-now
<div><span class="floatRight"><img alt="Simics 20 Years rounded corners smaller" title="Simics 20 Years rounded corners smaller" class="floatRight" src="https://software.intel.com/sites/default/files/managed/51/c5/Simics20Years_375px_v2.png" /></span>This is the first of a series of posts that will look at the past, present, and future of Wind River® Simics® virtual platforms. In 2018, it is 20 years since its commercial launch as a product. At the time <a href="https://petersmagnusson.org/2010/02/05/wind-river-intel-acquires-virtutech/" target="_blank" rel="nofollow">back in 1998</a>, Simics was marketed by a startup called Virtutech, which was acquired by Wind River, an Intel company, in 2010. </div>
<div>To run real-world software on the virtual platform, the Simics team has always strived for target scalability and simulation speed. Real server workloads already ran on Simics 20 years ago. But what counted as “large” software then and what that means today are two different things. Let’s take a look back and then make a comparison to what Simics runs today. </div>
<h3>Then…</h3>
<div><a href="https://www.usenix.org/legacy/publications/library/proceedings/usenix98/full_papers/magnusson/magnusson_html/magnusson.html" target="_blank" rel="nofollow">A seminal paper</a> published 20 years ago described how Simics would boot unmodified Sun* Solaris* 2.6 and Linux* 2.0.30 operating systems (OSs) on a quad-processor virtual <a href="https://en.wikipedia.org/wiki/SPARCstation" target="_blank" rel="nofollow">sun4m-architecture</a>-based SPARCstation* using disk images from a real machine. The setup was used to run the Mozilla* 5.0 web browser, as well as the Transaction Processing Council’s TPC-D database benchmark software, using a PostgreSQL* database. It was remarkable at the time: full-system simulation and virtual platforms were still new. Just taking a software stack from a real machine and running it inside a simulator quickly enough for interactive usage was practically unheard of. </div>
<div>The simulated sun4m architecture was used in workstations and servers that employed a variety of 32-bit SPARC V8 RISC processors. These platforms supported up to 512 MB of RAM, up to four processors at up to 200 MHz clock frequency. </div>
<div>Most actual hardware systems were more pedestrian, featuring sub-100 MHz clocks and sub-100 MB memories. A large software setup would have used a few hundred megabytes of RAM—today Microsoft* Word is using that much RAM on my laptop as I write this blog. </div>
<div>Simics back then used a pure interpreter in the core simulation instruction set processing engine. That made it between 25-100 times slower than actual hardware. Still, it was fast enough to get through the billion target instructions needed to boot Solaris in a reasonable amount of time. At the time, this was state-of-the-art. </div>
<h3>…and now</h3>
<div>Today, a high-end system can have 512 GB of RAM (1000x the SPARCstation above), 40+ cores (10x), and processor core clock frequencies of two to five GHz (25x). Thanks to micro-architectural improvements, new instructions, and other innovations, we probably run code about 100x faster on today’s systems compared to 20 years ago. </div>
<div>Simics has also improved to keep up with the times. The interpreter mode that was used in 1998 is rarely used these days. Instead, Simics relies on VMP (using Intel® Virtualization Technology for IA-32, Intel® 64 and Intel® Architecture (VT-x) to run Intel® architecture-based target code directly on the host) and <a href="https://en.wikipedia.org/wiki/Just-in-time_compilation" target="_blank" rel="nofollow">just-in-time (JIT) compiler technology</a> to convert target code to host code. These techniques make the slowdown of the virtual machine as low as 1x when running code. Thus, Simics run large workloads on models of contemporary hardware. </div>
<div>To see how workloads and the scope of virtual platforms have changed, let’s look at some examples of software we have seen running on Simics over the years. We start with some Java examples—in 1998, most server software was native, compiled for a particular processor architecture and OS. But Java was getting started on the client side, and a few years later, it jumped over to the server side. That provided a mostly host-independent environment for building business applications, thanks to the use of a Java Virtual Machine (JVM) to run byte code rather than native code. Thus, running JVMs on Simics is pretty common today. </div>
<h3>Just-in-Time running just in time</h3>
<div>Java*-based benchmarks running on Simics provide an interesting example of stacked computing layers. On the top level, Java code runs on top of a Java Virtual Machine (JVM). The JVM uses a JIT compiler to translate the JVM byte code to target system code for execution. Next, that target code runs on a Simics virtual platform that contains its own JIT. The Simics JIT converts target system code to host system code. The host system code runs on the Simics host—see the diagram below:</div>
<div>
<table align="center" style="width:100%"><tbody><tr><td style="text-align:center"><span><img alt="Simics host diagram 1" title="Simics host diagram 1" style="text-align:center" src="https://software.intel.com/sites/default/files/managed/5d/9e/diagram_01.png" /></span></td>
</tr></tbody></table></div>
<div>The stacking of virtual platforms and virtual machines works just fine! <span> </span></div>
<div>Note that in addition to the JIT, Simics “VMP” technology runs Intel architecture (IA) target code directly on the host by using Intel® Virtualization Technology (Intel® VT) for IA. This makes Simics performance similar to that of a typical virtual machine (VM) or hypervisor running on actual hardware. </div>
<h3>SpecJEnterprise on Simics</h3>
<div>Our first Java example is <a href="https://www.spec.org/jEnterprise2010/docs/UsersGuide.html#Section_1_Introduction" target="_blank" rel="nofollow">SpecJEnterprise 2010</a>, a benchmark from the <a href="https://www.spec.org/consortium/" target="_blank" rel="nofollow">Standard Performance Evaluation Corporation (SPEC) </a>consortium that mimics a business workload with an application server written in Java*, talking to a back-end database. The setup contains a driver utility that sends stimuli to the application server, which in turn uses the database. SpecJEnterprise measures system performance, including the hardware, JVM, database engine, networking, and other components. We run SpecJEnterprise on Simics as a platform test case because it is a good stimulus to test the integration of the OS, <a href="http://www.uefi.org/" target="_blank" rel="nofollow">Unified Extensible Firmware Interface (UEFI)</a>, and the hardware platform.</div>
<div>SpecJEnterprise requires at least two machines to run: one for the database and one for the application server. The driver utility can run on the same machine as the application server. The Simics setup is illustrated below, with two target systems inside a single Simics process. This provides neat encapsulation that does not depend on running external software or coordinating multiple simulation programs. In practice, the two Linux distributions used are slightly different, since each software stack comes with its own recommended Linux OS. </div>
<div><span><img alt="Wind River Simics Diagram 2" title="Wind River Simics Diagram 2" src="https://software.intel.com/sites/default/files/managed/11/cd/diagram_02.png" /></span></div>
<div>The two target machines have the same hardware configuration, and they are connected using 10Gbps Ethernet. Each target has four processor cores split over two sockets, and 192 GB of simulated RAM (96 GB attached to each socket). As a whole, the Simics setup simulates 384 GB of target RAM. Four processor cores per target system is a small configuration that is sufficient to run the benchmark setup; the Simics platform can support many more cores than that. As in 1998, Simics supports configurations all the way to the limits of the physical platform, <a href="https://software.intel.com/en-us/blogs/2016/09/02/simulating-six-terabytes-of-serious-ram" target="_blank">and beyond</a>. </div>
<div>When run, this configuration uses between 300 and 400 GB of host machine physical RAM—most of the simulated target RAM ends up being used and thus represented in Simics. As noted in a <a href="https://software.intel.com/en-us/blogs/2016/09/02/simulating-six-terabytes-of-serious-ram" target="_blank">previous blog post</a>, Simics can simulate very large target memories without using host RAM if the memory is not used for active data.</div>
<div>The two systems have their own simulated disks, and each disk has its own image. This image is a full bootable disk, basically the same as you would use on a physical system. Doing full-stack software development and execution <a href="http://blogs.windriver.com/wind_river_blog/2014/10/enabling-automatic-testing-of-anything-with-simics.html" target="_blank" rel="nofollow">independent of hardware</a> and <a href="http://blogs.windriver.com/wind_river_blog/2016/01/intel-co-design-shift-left-for-new-hardware-using-simics-an-interview-with-karthik-kumar-thomas-willhalm.html" target="_blank" rel="nofollow">before the hardware appears</a> are key benefits of the virtual platform. </div>
<div>Depending on the server load, the virtual platform slowdown is about 4x. Each benchmark test runs for about 3.5 hours in on the target machine, and between 12 and 14 hours to run in real-world time (wall-clock), depending on the load on the server which works out to a slowdown of around 4. It is good for this kind of workload – and—an order of magnitude better than in 1998!</div>
<h3>SpecJBB on Simics</h3>
<div><a href="https://www.spec.org/jbb2015/" target="_blank" rel="nofollow">SpecJBB 2015 </a>is called a “Java server business benchmark.” It measures the performance of Java virtual machines and consists of a three-tier “business application.” SpecJBB 2015 can use a varying number of JVM instances. In our setup, we use a single JVM. The benchmark runs on a single target machine, both in the real world and on Simics.</div>
<div>
<table align="center" style="width:100%"><tbody><tr><td style="text-align:center"><span><img alt="Wind River Simics Diagram 3" title="Wind River Simics Diagram 3" src="https://software.intel.com/sites/default/files/managed/99/39/diagram_03.png" /></span></td>
</tr></tbody></table></div>
<div>The setup in Simics is shown above. It contains a single server target system with 384 GB of simulated RAM and four processor cores split across two sockets. The software stack runs on Linux, just like SpecJEnterprise. The target system server boots using a real UEFI from the real platform being modeled, and the server model is a full model of a server platform with all the details and peculiarities of a particular hardware platform, including the processor cores, <a href="https://en.wikipedia.org/wiki/Uncore" target="_blank" rel="nofollow">uncore</a>, and <a href="https://en.wikipedia.org/wiki/Platform_Controller_Hub" target="_blank" rel="nofollow">Platform Controller Hub (PCH)</a>. It is not a “generic system” but a rather specific model. </div>
<div>Each run of SpecJBB on Simics currently takes about 3.5 hours to run on the virtual platform, and about 12 real-world hours to complete (depending on other loads running on the same server running Simics). This is a slowdown less than 4x, similar to SpecJEnterprise. </div>
<h3>HammerDB on Simics</h3>
<div><a href="http://www.hammerdb.com/" target="_blank" rel="nofollow">HammerDB</a> is an open-source database load testing and benchmarking tool. It is not a database in its own right, but a tool to “hammer” databases with transactions to test their performance under load. To run HammerDB, you use two separate machines, one with the database and one running the HammerDB tool. This setup is replicated in Simics by putting two server machines into a single Simics instance, just as we did with SpecJEnterprise.</div>
<div><span><img alt="Wind River Simics Diagram 4" title="Wind River Simics Diagram 4" src="https://software.intel.com/sites/default/files/managed/71/68/diagram_04.png" /></span></div>
<div>HammerDB requires “only” 128 GB of RAM in each simulated target machine, with 64GB attached to each processor socket. Depending on the load from other software running on the server at the same time, HammerDB needs up to 20 hours of host time to run through 1.5 to 2 hours of virtual time—still within a factor of 10. I consider that quite reasonable for virtual platforms, especially considering the scale of the system. It is quite a bit better than the slowdowns observed in 1998. </div>
<div>HammerDB features a graphical user interface (GUI) to execute tests and check results. The GUI displays on a console attached to the Simics model. Most of the other tests run with serial consoles, as the server workloads are designed to be headless. Simics scripting is used to automate test execution and ensure <a href="https://software.intel.com/en-us/blogs/2016/05/30/finding-kernel-1-2-3-bug-running-wind-river-simics-simics" target="_blank">run-by-run reproducibility</a>. </div>
<h3>HHVM oss-performance</h3>
<div>Our final example is a web-focused workload that uses another virtual machine system, one that targets the PHP and Hack languages, not Java. <a href="https://hhvm.com/" target="_blank" rel="nofollow">HHVM (“HipHop Virtual Machine”)</a> is an open-source virtual machine for PHP and Hack, offering a high-performance way to run many web applications and frameworks. The HHVM <a href="https://github.com/hhvm/oss-performance" target="_blank" rel="nofollow">oss-performance</a> benchmark uses <a href="https://nginx.org/en/" target="_blank" rel="nofollow">nginx </a>as the web server, underneath HHVM. To generate traffic to the web server and the application running on it, oss-performance uses the <a href="https://www.joedog.org/siege-home/" target="_blank" rel="nofollow">siege </a>benchmark tool, which “besieges” web servers to test their traffic handling ability. </div>
<div>This entire set of software is run on a single Simics target machine, inside a single Linux OS instance: </div>
<div>
<table align="center" style="width:100%"><tbody><tr><td style="text-align:center"><span><img alt="Wind River Simics Diagram 5" title="Wind River Simics Diagram 5" style="text-align:center" src="https://software.intel.com/sites/default/files/managed/a2/12/diagram_05.png" /></span></td>
</tr></tbody></table><p style="text-align:left">The hardware resources needed to run the oss-performance benchmark are more modest than the software stacks discussed above. 24 GB of target RAM is sufficient. That illustrates the variation in scale that different software stacks exhibit. For instance, SpecJBB requires an order of magnitude more memory to run, and thus stresses the target system software and hardware in a very different way. </p>
</div>
<div>The oss-performance benchmark is a suite of web application tests which operate in sequence during a single run. Each component benchmark starts by launching nginx and HHVM, and then starts the web application to test on top of HHVM. Once the web application is up and running, the siege benchmarking engine starts, and an application-specific benchmark program runs. Siege connects to nginx using network sockets within the same target machine. Each component benchmark starts from a Simics script. It watches the serial port of the target system for output strings and issues commands to the serial port—a good example of how Simics can automate a long sequence of operations on the target system from the outside, and work through complex operation sequences on the target system. </div>
<div>Depending on the host and the other loads, each run of the oss-performance benchmark takes about one hour of virtual time, taking six to eight real-world hours to complete. Thus, the slowdown is less than a factor of ten. </div>
<h3>Twenty years of virtual platforms</h3>
<div>What we see from current use cases is that Simics does the same thing it did when the technology was new, 20 years ago: it runs software from the real world on virtual platforms modeling the latest hardware, and it runs fast enough that you can use full-size standard software on the virtual platform for software validation, integration testing, and development. </div>
<div>Workloads now use a few orders of magnitude more memory and processor clock cycles on the virtual platform than on a physical systems. Depending on the simulated processor frequency, a workload that takes an hour to run in virtual time will churn through some 40 to 60 petacycles of target time and tens of trillions of instructions. An OS boot in 1998 required one billion instructions, but today’s OSs require <a href="https://en.wikipedia.org/wiki/Peta-" target="_blank" rel="nofollow">quadrillions</a>. </div>
<div>Thankfully, host machines and Simics have scaled up along with the workloads. Just as Simics could run a contemporary server workload in 1998, it can run a contemporary server workload in 2018. In practice, the gap between the simulated machines and the host machines has actually shrunk with the advent of JIT compilers, VMP technology, and <a href="http://blogs.windriver.com/wind_river_blog/2015/07/simics-5-multicore-accelerator-boosting-performance-adding-parallelism.html" target="_blank" rel="nofollow">multithreading</a>. </div>
<div>For more information, visit the <a href="https://www.windriver.com/products/simics/" target="_blank" rel="nofollow">Wind River Simics</a> page.</div>
Thu, 15 Mar 18 16:45:16 -0700Engblom, Jakob (Intel)759484Use an Advanced Development Environment for OpenCL™ Applications https://software.intel.com/en-us/blogs/2017/07/28/2017-opencl-whats-new
<h1><span><img alt="innovate hetergeneous compute solutions" title="innovate hetergeneous compute solutions" height="200" width="745" style="color:rgb(85, 85, 85)" src="https://software.intel.com/sites/default/files/managed/3e/c0/innovate-hetergenous-compute-solutions.jpg" /></span></h1>
<h1>Just Released! Intel® SDK for OpenCL™ Applications 2017</h1>
<p>Accelerate heterogeneous compute application performance and customize your solutions with the new <strong><a href="https://software.intel.com/intel-opencl">Intel® SDK for OpenCL™ Applications 2017</a></strong>. The 2017 update (August 2017) adds support for additional operating systems and platforms, and compatible integration into more recent IDEs for flexibility and to stay up to date. It also provides new tool features that help you speed your development and improve performance for create high-performance image and video processing pipelines.</p>
<ul><li><strong>2017 R2 Update</strong> (December 2017) - The Intel® SDK for OpenCL™ Applications 2017 R2 update<strong> </strong>adds support and fixes small issues working with key IDEs: Microsoft Visual Studio* 2017 and Eclipse* Oxygen 4.7. Review the latest release notes for more details. Developers should also ensure that they have the latest updates for other software components and drivers that work with this SDK: <a href="https://software.intel.com/en-us/articles/opencl-drivers">software.intel.com/opencl-drivers</a></li>
</ul><p><strong><a class="button-white" href="https://software.intel.com/en-us/intel-opencl">Download Now</a></strong></p>
<h3>2017 Update Summary</h3>
<p><strong>New IDE Support</strong></p>
<ul><li>Microsoft Visual Studio* 2017</li>
<li>Eclipse Oxygen* 4.7 and Neon* 4.6</li>
</ul><p><strong>New Operating System Support</strong></p>
<ul><li>Windows 10 Creator* including full compatibility with the latest Intel® Graphics driver (15.46)</li>
<li>Ubuntu* 16.04 including full compatibility with latest OpenCL™ 2.0 CPU/GPU driver package for Linux* OS (SRB5)</li>
<li>CentOS 7.3 </li>
</ul><p><strong>New Platform Support</strong></p>
<p>Enhanced tools support platforms with 6th and 7th Generation Intel® Core™ Processors on Microsoft Windows* and Linux* operating systems.</p>
<h3>New Features that Streamline Development and Improve Solutions Customization</h3>
<h3><a href="https://software.intel.com/en-us/intel-opencl"><img alt="Intel SDK for OpenCL Applications" class="one-quarter-float-left" src="https://software.intel.com/sites/default/files/managed/fe/41/Intel-OpenCL-200.png" style="width:215px" title="Intel SDK for OpenCL Applications" /></a></h3>
<ul><li>Improved OpenCL™ 2.1 and SPIR-V* support on Linux* OS</li>
<li>OpenCL 2.1 development environment with the experimental CPU-only runtime for OpenCL 2.1</li>
<li>SPIR-V generation support with Intel® Code Builder for OpenCL™ offline compiler and Kernel Development Framework including textual representation of SPIR-V binaries - </li>
<li>Workflow support allowing build, execution and analysis of applications with several kernels</li>
<li>Build from binary to reduce compilation time for complex kernels</li>
<li>Latency analysis on 6th and 7th Generation Intel® Core™ Processors</li>
</ul><p>Learn more at the <a href="https://software.intel.com/en-us/intel-opencl">product site</a>.</p>
<p>Access <a href="https://software.intel.com/en-us/intel-opencl-support/documentation">developer guides</a> and a complete list of new features and changes in this release, read the <a href="https://software.intel.com/en-us/intel-opencl-support/documentation">release notes</a></p>
<div>
<div>
<p> </p>
<p class="footnote">OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos</p>
</div>
</div>
<p> </p>
Thu, 15 Mar 18 16:00:03 -0700Michael C.740093MeshCentral2 - Windows Installer, Server Aliasing &amp; Wide Mode Supporthttps://software.intel.com/en-us/blogs/2018/03/14/meshcentral2-windows-installer-server-aliasing-wide-mode-support
<p><a href="http://www.meshcommander.com/meshcentral2" rel="nofollow"><img alt="" src="https://software.intel.com/sites/default/files/managed/10/d5/MeshCentralBlogBanner2.png" /></a></p>
<p><a href="http://www.meshcommander.com/meshcentral2" rel="nofollow">MeshCentral</a> is an open source web based remote computer management web site. We release new versions many times a week and this week we added a bunch of more interesting features &amp; improvements:</p>
<ul><li><strong>New MeshCentral installer for Windows</strong>. MeshCentral2 is pretty amazing in that you can install and run a new server easily and within minutes on both Windows and Linux. However, for Windows users we just made the process of getting your own MeshCentral2 server up and running even simpler with the all new <a href="http://info.meshcentral.com/downloads/meshcentral2/MeshCentralInstaller.exe" rel="nofollow">MeshCentral2 installer for Windows</a>. This installer will automatically detect, download and install NodeJS if needed along with installing the very latest version of MeshCentral. It can also be used for limited configuration of the server to get you started and to perform server updates. The new installer is fast, interactive and super simple. Anyone can launch a remote management service in minutes.</li>
<li><strong>Wide screen toggle</strong>. You can now toggle the web page to use the full width of your browser window. This is really useful as increasingly there are really wide monitors. As the number of computers you manage increases, being able to use the entire browser window is a big plus. All of the MeshCentral2 screens has been modified to support the new mode toggle. Since this is a new feature, the toggle button will be somewhat hidden for now.</li>
<li><strong>Server name and port aliasing</strong>. In some cases, you need to install the server in such a way that the internal private ports are not the same as the external ports. This is important where you are co-locating many services on a single server behind a firewall or have odd port mappings you have to deal with. When using port aliasing, the server will bind to ports on the local computer but assume that externally, the server is accessible on a different set of ports, so when getting a URL from the server, the external alias port is used. The server can also alias the name of the Intel® AMT MPS, making it possible to get HTTPS and CIRA connections on the same port using two different IP addresses.</li>
</ul><p>In addition to these features, MeshCentral2 and the latest MeshAgent have gotten a lot more bug fixes and upgrades. A updated <a href="http://info.meshcentral.com/downloads/meshcentral2/MeshCentral2UserGuide.pdf" rel="nofollow">MeshCentral2 User’s Guide 0.1.5</a> was put online reflecting the latest changes and updates.</p>
<p>Enjoy!<br />
Ylian<br />
Blog: <a href="http://www.intel.com/software/ylian">http://www.intel.com/software/ylian</a><br />
MeshCentral2: <a href="http://www.meshcommander.com/meshcentral2" rel="nofollow">http://www.meshcommander.com/meshcentral2</a></p>
<p align="center"> </p>
<p align="center">The all new <a href="http://info.meshcentral.com/downloads/meshcentral2/MeshCentralInstaller.exe" rel="nofollow">Windows installer for MeshCentral</a> allow you to quickly get it up and running.<br />
NodeJS is automatically installed if needed, just a few steps and the server is setup.</p>
<p align="center"><span><img height="688" width="946" alt="" title="" src="https://software.intel.com/sites/default/files/managed/86/c0/MeshCentral-Installer3.png" /></span></p>
<p align="center">MeshCentral2’s latest web page are not only all real time, you can<br />
now toggle to use the full width of the browser window.<br />
(During testing, the button is not highly visible)</p>
<p align="center"><span><img height="499" width="669" alt="" title="" src="https://software.intel.com/sites/default/files/managed/ef/0d/MeshCentral-WideMode.png" /></span></p>
<p align="center">MeshCentral2 now supports MPS server aliasing and port aliasing.<br />
You can setup MeshCentral2 with different internal and external ports.</p>
<p align="center"><span><img height="527" width="641" alt="" title="" src="https://software.intel.com/sites/default/files/managed/43/4e/MeshCentral-Aliasing.png" /></span></p>
<p align="center"> </p>
Wed, 14 Mar 18 17:17:04 -0700Ylian S. (Intel)759437Trending on IoT: Our Most Popular Developer Stories for Marchhttps://software.intel.com/en-us/blogs/2018/03/14/trending-on-iot-our-most-popular-developer-stories-for-march
<p style="text-align:center"><a href="/en-us/iot/devfest/2?VideoID=5729370064001" rel="nofollow"><span><img alt="Industrial IoT Workers " title="Industrial IoT Workers " src="https://software.intel.com/sites/default/files/managed/d8/54/800px_COLOURBOX5320353.png" /></span></a></p>
<h4 style="text-align:center"><a href="https://software.intel.com/en-us/iot/devfest/2?VideoID=5729370064001">Workers in the Wild: Discover the Problems That Matter to Today's Industrial Workers</a></h4>
<p style="text-align:center"><span style="color:rgb(56, 64, 71)">Industrial workers discuss the problems they face and the opportunities they see for smart technologies to help solve those problems, as well as roadblocks to adopting new technologies.</span></p>
<hr /><p style="text-align:center"><a href="/en-us/iot/devfest/2?VideoID=5729201482001" rel="nofollow"><span><img alt="Autonomous Driving" title="Autonomous Driving" src="https://software.intel.com/sites/default/files/managed/76/61/Autonomous-5G2-e1482965847508-720x360.png" /></span></a></p>
<h4 style="text-align:center"><a href="https://software.intel.com/en-us/iot/devfest/2?VideoID=5729201482001">Automobile Sense and Control</a></h4>
<p style="text-align:center"><span style="color:rgb(56, 64, 71)">Learn how to develop an IoT solution that collects data and sensor metrics from smart vehicles, displays the data locally, and then transmits it to a cloud platform to create a fully remote control platform for vehicles.</span></p>
<hr /><p style="text-align:center"><a href="/en-us/articles/increasing-efficiency-and-uptime-with-predictive-maintenance" rel="nofollow"><span><img alt="Manufacturing " title="Manufacturing " src="https://software.intel.com/sites/default/files/managed/d2/bd/manufacturers.png" /></span></a></p>
<h4 style="text-align:center"><a href="https://software.intel.com/en-us/articles/increasing-efficiency-and-uptime-with-predictive-maintenance">Increase Efficiency and Uptime with Predictive Maintenance</a></h4>
<p style="text-align:center"><span style="color:rgb(56, 64, 71)">Use the 4.1 Industrial Internet of Things Platform (4.1 IIoTP) to enable prompt responses to emergencies, power outages, or technical faults, and to decrease downtime.</span></p>
<hr /><p style="text-align:center"><a href="/en-us/articles/cut-energy-costs-with-a-smart-real-time-occupancy-solution-from-feedback-solutions-and?cid=em-elq-34628&amp;utm_source=elq&amp;utm_medium=email&amp;utm_campaign=34628&amp;elq_cid=1198870" rel="nofollow"><span><img alt="Cut Energy Costs " title="Cut Energy Costs " src="https://software.intel.com/sites/default/files/managed/ae/37/feedback-solutions-real-time-occupancy-banner.png" /></span></a></p>
<h4 style="text-align:center"><a href="/en-us/articles/cut-energy-costs-with-a-smart-real-time-occupancy-solution-from-feedback-solutions-and?cid=em-elq-34628&amp;utm_source=elq&amp;utm_medium=email&amp;utm_campaign=34628&amp;elq_cid=1198870" rel="nofollow">Cut Energy Costs with a Smart Real-Time Occupancy Solution from Feedback Solutions and Intel</a></h4>
<p style="text-align:center">Feedback Solutions offers a unique, cloud-based solution using Intel<sup>®</sup> IoT Gateway for controlling heating and cooling systems based on real-time occupancy.</p>
<hr /><p style="text-align:center"><a href="/en-us/iot/devfest/2?VideoID=5729444813001" rel="nofollow"><span><img alt="Secure Platforms " title="Secure Platforms " src="https://software.intel.com/sites/default/files/managed/73/df/encryption_security_lock-100052900-orig.png" /></span></a></p>
<h4 style="text-align:center"><a href="https://software.intel.com/en-us/iot/devfest/2?VideoID=5729444813001">Providing Secure IoT Platforms at the Edge</a></h4>
<p style="text-align:center"><span style="color:rgb(56, 64, 71)">Create a secure foundation for your embedded device with these best practices for providing platform integrity and security, as well as considerations to limit exposure to vulnerability.</span></p>
<hr /><p style="text-align:center"><a href="/en-us/articles/whats-new-in-intel-system-studio" rel="nofollow"><span><img alt="Application Development " title="Application Development " src="https://software.intel.com/sites/default/files/managed/cd/45/IoT%20copy_0.png" /></span></a></p>
<h4 style="text-align:center"><a href="https://software.intel.com/en-us/articles/whats-new-in-intel-system-studio">Speed Up System &amp; IoT Device Application Development with the New Intel® System Studio</a></h4>
<p style="text-align:center"><span style="color:rgb(56, 64, 71)">Discover how this all-in-one, cross-platform system and IoT development tool suite can help shorten the development cycle, improve performance and power efficiency, and provide easy access to over 400 sensors.</span></p>
<hr /><p style="text-align:center"><a href="/en-us/iot/devfest/2?VideoID=5729378262001" rel="nofollow"><span><img alt="Smart Trans*" title="Smart Trans*" src="https://software.intel.com/sites/default/files/managed/1c/89/Smart%20Trans.png" /></span></a></p>
<h4 style="text-align:center"><a href="https://software.intel.com/en-us/iot/devfest/2?VideoID=5729378262001">IoT Goes into the Real World</a></h4>
<p style="text-align:center"><span style="color:rgb(56, 64, 71)">In transportation, accuracy and dependability are key. SmartTrans* gives a real-world account of problems they experienced when bringing their IoT application to life.</span></p>
<hr /><p style="text-align:center"><a href="https://www.intel.com/content/www/us/en/embedded/retail/vending/iot-gateway-for-intelligent-vending/overview.html"><span><img alt="IoT Retail Gateway " title="IoT Retail Gateway " src="https://software.intel.com/sites/default/files/managed/f4/d9/Big%20Digital%20sign.png" /></span></a></p>
<h4 style="text-align:center"><a href="https://www.intel.com/content/www/us/en/embedded/retail/vending/iot-gateway-for-intelligent-vending/overview.html">Intel® IoT Retail Gateway Reference Design for Intelligent Vending</a></h4>
<p style="text-align:center"><span style="color:rgb(56, 64, 71)">The Reference Design for Intelligent Vending using the Intel® IoT Retail Gateway provides a solution for rearchitecting traditional vending machines into highly capable, internet-connected machines by concentrating all vending machine functions onto a single board.</span></p>
<hr /><p style="text-align:center"><a href="/en-us/iot/devfest/2?VideoID=5728410859001" rel="nofollow"><span><img alt="Smart Factory " title="Smart Factory " src="https://software.intel.com/sites/default/files/managed/33/d6/Intel%20factory.png" /></span></a></p>
<h4 style="text-align:center"><a href="https://software.intel.com/en-us/iot/devfest/2?VideoID=5728410859001">The Smart Factory Journey</a></h4>
<p style="text-align:center"><span style="color:rgb(56, 64, 71)">Using IoT, technical process challenges are often solved with new end-to-end methods (from sourcing data to decision-making) that can be automated. Learn about future opportunities and challenges with IoT deployments including automated instrumentation of industrial equipment.</span></p>
<hr /><p style="text-align:center"><a href="/en-us/articles/updates-to-the-intel-high-definition-audio-specification" rel="nofollow"><span><img alt="Audio Specification " title="Audio Specification " src="https://software.intel.com/sites/default/files/managed/45/32/face.png" /></span></a></p>
<h4 style="text-align:center"><a href="https://software.intel.com/en-us/articles/updates-to-the-intel-high-definition-audio-specification">Updates to the Specification Document for Intel® High Definition Audio</a></h4>
<p style="text-align:center"><span style="color:rgb(56, 64, 71)">The specification document for Intel® High Definition Audio has been updated to include a simplified capabilities linked list, support for static switching to lower frequencies, and added support for a new variant of the codec.</span></p>
<hr /><p style="text-align:center"><span style="color:rgb(56, 64, 71)">Intel® Developer Zone experts, Intel® Software Innovators, and Intel® Black Belt Software Developers contribute hundreds of helpful articles and blog posts every month. From code samples to how-to guides, we gather the most popular software developer stories in one place each month so you don’t miss a thing.</span></p>
<p style="text-align:center"><span><img alt="Intel IoT" title="Intel IoT" src="https://software.intel.com/sites/default/files/managed/73/ff/Top10-IoT-Icon.jpg" /></span></p>
Wed, 14 Mar 18 16:33:40 -0700Amelia N. (Intel)759433The Best of Modern Code Marchhttps://software.intel.com/en-us/blogs/2018/03/13/the-best-of-modern-code-march
<h4 style="text-align:center"><a href="/en-us/articles/building-freefem-with-intel-software-tools-for-developers" rel="nofollow"><span><img alt="FreeFEM++" title="FreeFEM++" src="https://software.intel.com/sites/default/files/managed/26/c6/chesapeake-2.png" /></span></a></h4>
<h4 style="text-align:center"><a href="https://software.intel.com/en-us/articles/building-freefem-with-intel-software-tools-for-developers">Building FreeFEM++ with Intel Software Tools for Developers</a></h4>
<p style="text-align:center"><span style="color:rgb(56, 64, 71)">Use Intel® Parallel Studio XE to optimize the performance of FreeFEM++—a powerful tool that can help solve partial differential equations.</span></p>
<hr /><p style="text-align:center"><a href="/en-us/articles/isd-windbg-extension" rel="nofollow"><span><img alt="Intel Debugger " title="Intel Debugger " src="https://software.intel.com/sites/default/files/managed/02/a6/Kf2pfVQP.png" /></span></a></p>
<h4 style="text-align:center"><a href="https://software.intel.com/en-us/articles/isd-windbg-extension">How to Use Intel® Debugger Extension for WinDbg*</a></h4>
<p style="text-align:center"><span style="color:rgb(56, 64, 71)">Learn how to use this extension tool for operating system delay issues.</span></p>
<hr /><p style="text-align:center"><a href="/en-us/articles/intel-accelerates-hardware-and-software-performance-for-server-side-java-applications" rel="nofollow"><span><img alt="Java" title="Java" src="https://software.intel.com/sites/default/files/managed/70/dc/Java.png" /></span></a></p>
<h4 style="text-align:center"><a href="https://software.intel.com/en-us/articles/intel-accelerates-hardware-and-software-performance-for-server-side-java-applications">Intel Accelerates Hardware and Software Performance for Server-Side Java* Applications</a></h4>
<p style="text-align:center"><span style="color:rgb(56, 64, 71)">Get tips and techniques on hardware and software optimizations that benefit Java* applications running on the latest Intel® Xeon and Intel® Xeon Phi™ processors.</span></p>
<hr /><p style="text-align:center"><a href="/en-us/videos/python-scalability-in-production-environments" rel="nofollow"><span><img alt="Python* Language " title="Python* Language " src="https://software.intel.com/sites/default/files/managed/67/cd/Python%20language.png" /></span></a></p>
<h4 style="text-align:center"><a href="https://software.intel.com/en-us/videos/python-scalability-in-production-environments">Python* Scalability in Production Environments</a></h4>
<p style="text-align:center"><span style="color:rgb(56, 64, 71)">Get specific Intel tools, optimizations, and instructions to expand your expertise with the Python* language.</span></p>
<hr /><p style="text-align:center"><a href="https://colfaxresearch.com/how-series/" rel="nofollow"><span><img alt="Deep Dive into Modern Code " title="Deep Dive into Modern Code " src="https://software.intel.com/sites/default/files/managed/7c/db/deep%20dive%202.png" /></span></a></p>
<h4 style="text-align:center"><a href="https://colfaxresearch.com/how-series/" rel="nofollow">Take a Deep Dive Into Modern Code</a></h4>
<p style="text-align:center"><span style="color:rgb(56, 64, 71)">Learn new skills or brush up on old skills with this in-depth online training. Topics include parallel programming and performance optimization in computational applications for Intel® architecture.</span></p>
Tue, 13 Mar 18 17:05:14 -0700Russ Beutler (Intel)759404Announcing Intel® Graphics Performance Analyzers Version 2018 R1https://software.intel.com/en-us/blogs/2018/03/12/intel-gpa-product-announcement
<p class="intro-paragraph">Say hello! to some of the latest features for the Intel® Graphics Performance Analyzers (Intel® GPA) tool suite.</p>
<h2>Experience Ease of Use and Cross-platform Compatibility</h2>
<p style="text-align:center"><img alt="" src="https://software.intel.com/sites/default/files/managed/8c/96/graphicsMonitor.png" title="" /></p>
<p>Experience identical, intuitive workflows across all platforms with the new Graphics Monitor. Easily identify which API will be profiled with the API tab selection, modify settings from within the tool, and access valuable information about your target or remote host.</p>
<h2>Target a Specific GPU on Multi-GPU Systems</h2>
<p style="text-align:center"><span><img alt="" title="" src="https://software.intel.com/sites/default/files/managed/1b/8a/selectGPUHighligh.png" /></span></p>
<p>It's now easier to target a specific graphics card on multi-GPU systems. Capture a frame on one GPU and use another one for analysis. Use the information button to see which GPU is currently being targeted, as well as additional information about your machine.</p>
<h2>Quickly Switch Between Informational Views</h2>
<p style="text-align:center"><img alt="" src="https://software.intel.com/sites/default/files/managed/57/a5/frameAnalzyerTabsLightHighlight.png" title="" /></p>
<p>The API log now features tabs for resource history, pixel history, and frame statistics. Quickly switch between these informational views without fuss and never lose track of the draw call at hand. Figure out resource dependencies and experiment with draw calls later in the scene while maintaining the same resource history list.</p>
<p>Download for free on the <a href="/en-us/gpa" rel="nofollow">Intel® GPA site</a>.</p>
Mon, 12 Mar 18 11:02:18 -0700Giselle G. (Intel)759314Doctor Fortran in &quot;And They&#039;re Off!&quot;https://software.intel.com/en-us/blogs/2018/03/10/doctor-fortran-in-and-theyre-off
<p>Two significant events happened recently in the Fortran world. As I wrote in <a href="https://software.intel.com/en-us/blogs/2018/01/09/doctor-fortran-in-dis-dat-and-doze" target="_blank">Doctor Fortran in "DIS, Dat and Doze"</a>, the Draft International Standard for Fortran 2018 was submitted for country ballot back in January. There was an eight-week period for possible translations, though I don't know that any occurred, and the ballot officially opened on March 9. Each ISO National Body (country standards committee) gets to vote and can Approve, Approve with Comments or Disapprove. The DIS is available for view at the new J3 web site, <a href="https://j3-fortran.org" rel="nofollow">https://j3-fortran.org</a> - go to Documents &gt; By Year &gt; 2018 &gt; 18-007. </p>
<p>The US National Body (formally INCITS PL22.3, but we all call it J3) voted at its February meeting to approve the DIS with comments (paper <a href="https://j3-fortran.org/doc/year/18/18-155.pdf" rel="nofollow">18-155</a>). Voting runs through June 2, just in time for the next WG5 (international committee) meeting mid-June in Berkeley, California. There, WG5 will consider any comments received and decide which to accept and whether any of the accepted comments constitute technical changes that warrant creating a separate FDIS (Final Draft International Standard), which would require another country ballot (and push the publication date into 2019.) If WG5 decides that any changes are minor, a 30-day ballot is then done to see if countries agree, and if they do, then the FDIS step is skipped and the standard (with minor edits as needed) is published. Yay!</p>
<p>Ok, that's the F2018 news, now on to F202X! As I have written earlier, WG5 ran a survey for many months to solicit user requests for new features in the next Fortran standard revision. The survey received 137 responses, which were collected and organized into WG5 document <a href="https://isotc.iso.org/livelink/livelink?func=ll&amp;objId=19530634&amp;objAction=Open&amp;viewType=1" rel="nofollow">N2147</a> (pdf). In my new role as WG5 Convenor I asked each J3 member to send me a list of their top five requests, drawing from N2147 or their own experiences. These were collated into J3 document <a href="https://j3-fortran.org/doc/year/18/18-122r1.txt" rel="nofollow">18-122r1</a> and then distributed to the various J3 subgroups for discussion. Each subgroup then offered their recommendation as to whether or not to do further work on a topic. Some of the requests, upon further analysis, were deemed unworkable, others changed in scope during discussions. Then all J3 members present discussed the proposals and took straw votes as to whether to recommend the features to WG5 - the recommendations paper is <a href="https://j3-fortran.org/doc/year/18/18-156.txt" rel="nofollow">18-156</a>.</p>
<p>This is the very early start at F202X. Other National Bodies will have their own lists of requests, and WG5 members will undoubtedly offer some of their own. My stated goal is to have the feature list nailed down by the end of the August 2019 WG5 meeting in Tokyo, Japan. By keeping the feature list to a manageable size, I hope to keep the process moving forward and have something we can publish by 2022 or 2023 at the latest. Wish us luck!</p>
Sat, 10 Mar 18 07:50:19 -0800Steve Lionel (Ret.)759291Showcasing the Shift to 5G at MWC-2018https://software.intel.com/en-us/blogs/2018/03/09/showcasing-the-shift-to-5g-at-mwc-2018
<div><span><img alt="Mobile World Congress 2018 Booth aerial view" title="Mobile World Congress 2018 Booth aerial view" src="https://software.intel.com/sites/default/files/managed/0c/69/MWC-2018-1_sm.jpg" /></span></div>
<div>During their Olympics keynote ahead of Mobile World Congress (MWC) in Barcelona, Intel senior VPs Sandra Rivera and Aicha Evans laid-out Intel’s 5G strategy. They were joined on-stage by execs from Korea Telecom, NTT DOCOMO and Toyota to share the compelling business value they see from the shift to 5G. </div>
<div>Those and other 5G partners around the globe are working with Intel today, conducting real-world commercial tests. In addition, just days before MWC, <a href="https://www.intel.com/content/www/us/en/sports/olympic-games/5g.html" target="_blank">Intel 5G gear proved what it could do</a> at the Winter Olympics in PyeongChang, South Korea. Using PyeongChang as the largest broad scale deployment of 5G in the world, Intel, along with its partners, showcased 22 5G links across 10 Olympic venues that spanned the country, letting tens of thousands of spectators see, test and experience the power of 5G connectivity.</div>
<h3>5G for a smart, connected world</h3>
<div>We caught up with Intel MWC booth staffer Farid Adrangi, an Intel senior architect for next-generation networking. We asked him to share his impressions of MWC-2018.</div>
<div>“The show’s focus was on 5G everywhere and the goodness it will bring to users in different segments. In that context, self-driving cars were the biggest story for Intel and many other vendors: 5G modems and powerful processing platforms for vehicle-to-vehicle and vehicle-to-infrastructure (V2X) were especially prominent on the exhibit floor,” Farid observed.</div>
<div>“We highlighted Intel end-to-end platform security for connected cars and virtualized network usages with our partners,” he added. “For example, we showcased a trusted payment solution concept for connected cars—both self-driving and human-operated. It combined the <a href="https://software.intel.com/en-us/sgx-sdk" target="_blank">Intel® Software Guard Extensions (Intel® SGX)</a> trusted enclave with Worldpay’s in-car payment services for smart/electric car charging, smart parking, smart tolls, smart keys, and more.“ </div>
<div><span class="full-content-width"><img alt="Mobile World Congress 2018 EV Charging Model" title="Mobile World Congress 2018 EV Charging Model" style="width:862.4px" class="full-content-width" src="https://software.intel.com/sites/default/files/managed/6a/0a/MWC-2018-2.jpg" /></span><br /><em>This Intel mock-up showcased 5G-enabled secure payments for EV-charging.</em></div>
<div>“One of our other big demos was the 5G-connected van. It was the actual van that was used as the first successful multi-vendor 5G connected-car trial in late 2017 with the <a href="https://www.intel.com/content/www/us/en/automotive/go-automated-driving.html" target="_blank">Intel® GO™ 5G Automotive Platform</a>, in partnership with NTT DOCOMO, Ericsson, Toyota and Denusu,” Farid explained. “The demo showed how connected cars will benefit from ultra-high bandwidth, ultra-low latency, and massive capacity helping to transform vehicles and transportation.”</div>
<div>Connected cars were a big part of the story, but not the only part. “We also showcased a solution concept that combined the Intel SGX trusted enclave with Gemalto’s advanced <a href="https://safenet.gemalto.com/data-protection-on-demand/" target="_blank" rel="nofollow">Data Protection On-demand</a> software services, to protect the new generation of cloud-based 5G virtualized networks against cyber-attack,” Farid said.</div>
<div>He added, “Another big thing at MWC was 5G for virtual reality and augmented reality (VR/AR. For example, if you want to learn how to ski, you put the VR goggles on, and it seems so real, like you’re jumping off the cliff—you can feel it in your stomach.” </div>
<div><span><img alt="Mobile World Congress 2018 Booth demo" title="Mobile World Congress 2018 Booth demo" src="https://software.intel.com/sites/default/files/managed/79/31/MWC-2018-3_sm.jpg" /></span><br /><em>Wireless 5G makes PC-based VR experiences more real than ever before.</em></div>
<div>“In addition, massive Internet of Things (IoT) use cases were shown by multiple vendors, to enable a connected world, like Smart Cities with sensors everywhere, as well as factory-automation and robotics.”</div>
<div><span class="full-content-width"><img alt="Mobile World Congress 2018 Booth top view big cities 5g" title="Mobile World Congress 2018 Booth top view big cities 5g" class="full-content-width" src="https://software.intel.com/sites/default/files/managed/85/e0/MWC-2018-4_sm.jpg" /></span><br /><em>Intel’s “Smart Cities” MWC exhibit showcased the value of 5G everywhere.</em></div>
<div>According to Farid, the highlights at the Intel booth included the connected car demos, the VR experience area, a huge Smart Cities exhibit, and most of all, the prototype 5G-connected PC, which was the number-one voted demo by Intel booth attendees. </div>
<div><span class="full-content-width"><img alt="Mobile World Congress 2018 5G-Enabled demo" title="Mobile World Congress 2018 5G-Enabled demo" class="full-content-width" src="https://software.intel.com/sites/default/files/managed/16/6b/MWC-2018-5_sm.jpg" /></span><br /><em>The 5G-connected 2-in-1 PC was a big hit at Intel’s MWC-2018 booth.</em></div>
<div>Farid added, “We had big crowds, like last year, and we got a lot of compliments on our in-car payment demo from the media, including its recognition in more than one ‘Top 10 Demos’ list.”</div>
<h3>Six highlights from this year’s event</h3>
<div>For Intel and our ecosystem partners, these announcements and demos stood-out at MWC-2018:</div>
<ol><li><strong>5G at the 2020 Summer Olympics in Tokyo</strong>—5G technology from Intel’s labs played a key role at Winter Olympics in PyeongChang. Intel and Korea Telecom deployed the world’s largest 5G array at 10 sites around the Olympics, enabling unique new camera angles of athletes in action, and live 360-degree video feeds beamed to spectators. What’s next, you ask?<a href="https://newsroom.intel.com/editorials/intel-5g-technology-olympic-games-tokyo-2020-play-role-transforming-everything-sports-transportation" target="_blank"> Intel and NTT DOCOMO revealed</a> 5G will power new experiences at the 2020 Summer Olympics in Tokyo.</li>
<li><strong><span>T</span>he world’s first demo of a live 5G connection</strong>—At the Intel’s MWC booth, people could see and operate the world’s first 5G-connected “concept PC.” What’s more, they could interact with it on the world’s first 5G wireless feed. That 5G New Radio (NR) Wi-Fi spec was finalized by the wireless consortium at the beginning of this year. Although Intel tested 5G NR in the lab and in limited field trials, we showed the live capabilities of 5G to a large audience for the first time at MWC-2018.</li>
<li><strong>5G-enabled PCs coming in late 2019</strong>—Leading up to MWC, Intel announced agreements with four of the biggest players in the PC industry: Dell, HP, Lenovo and Microsoft. They will merge Intel’s 5G multi-mode modems into a new class of 2-in-1 PCs to support 5G while remaining backward-compatible all the way back to 2G connections. At our booth, Intel showed off a 5G PC prototype running on 8th Generation Intel® Core® processors. The first wave of these devices is expected to arrive in time for the 2019 holiday buying season.</li>
<li><strong>New Intel® Xeon® system-on-a-chip brings 5G to the edg</strong>e—Communications OEMs and telcos around the world face growing needs for compute power at the edge. To meet that need, Intel introduced the Intel® Xeon® D-2100 system-on-a-chip (SoC) for mobile edge computing (MEC). Rather than streaming high-intensity workloads to a faraway data center for processing, the new SoC is designed to move the computing much closer to edge-devices, minimizing latency.</li>
<li><strong>Intel and Spreadtrum to drive 5G phones in China</strong>—5G phones will be available in China late next year using Intel® XMM 8000-series modems and Spreadtrum application processors. At MWC, <a href="https://newsroom.intel.com/articles/intel-unigroup-spreadtrum-rda-announce-5g-collaboration" target="_blank">Intel and Spreadtrum jointly revealed plans</a> to collaborate for several years.</li>
<li><strong>5G NR Interoperability with Huawei</strong>—Intel and Huawei showed interoperability of the 5G New Radio (5G NR) specification between Intel Mobile Trial Platform (MTP) and a Huawei 5G base station based on 3GPP Release 15 specs. Intel and Huawei, along with Deutsche Telekom announced in late January that they had achieved the world’s first multi-vendor 5G NR interoperability, moving the industry an important step closer to full 5G commercialization. </li>
</ol><h3>Spotlight on software</h3>
<div>Hardware innovations launched at MWC-2018 included Intel® Silicon Photonics 100G transceivers for 5G, as well as 5G-based PCs, mobile platforms, and MEC servers from multiple vendors. But for many, software took the spotlight. Here are some examples that highlight 5G’s rapid advance:</div>
<ul><li><a href="https://qct.io/Press-Releases/index/PR/Solution/MWC-2018-QCT-Presents-Solutions-for-Cloud-based-5G-Infrastructures/1/0" target="_blank" rel="nofollow">Quanta Cloud Technology</a> announced its QuantaGrid* D52BQ-2U Intel® Select Solution for Network Function Virtualization infrastructure (NFVi), verified to build an optimized NFVi with Intel® Xeon® Scalable processors, Intel® QuickAssist Technology (Intel® QAT) and the <a href="https://software.intel.com/en-us/articles/data-plane-development-kit-dpdk-getting-started" target="_blank">Data Plane Development Kit (DPDK)</a>.</li>
<li><a href="http://www.nec.com/en/press/201802/global_20180223_03.html" target="_blank" rel="nofollow">NEC Corp</a> joined with NTT DOCOMO to showcase its use of FlexRAN, Intel’s 5G reference architecture which includes a reference-ready software development kit based on the DPDK.</li>
<li><a href="https://www.newswire.ca/news-releases/pivot-technology-solutions-inc-introduces-smart-edge-675260063.html" target="_blank" rel="nofollow">Pivot </a>launched its Smart Edge* advanced developer platform designed to support enterprise MEC solutions, and built to operate on Intel technology.</li>
<li><a href="https://blogs.vmware.com/telco/accelerating-reality-nfv-can-achieved-integrate-best-breed-technologies-vmware-intel-collaborating-deliver-high-performance-open-tested-network-functions-ope/" target="_blank" rel="nofollow">VMware </a>announced it will provide customers with DPDK network acceleration on Intel® Xeon® processors, Intel poll mode drivers for VMware* vSphere*, improved memory throughput on Intel Xeon Scalable processors, and more.</li>
<li><a href="https://blog.gemalto.com/mobile/2018/02/26/how-to-protect-5g-and-virtualized-networks-from-cyber-attacks-at-the-very-heart-of-the-core-and-multi-access-edge-clouds/" target="_blank" rel="nofollow">Gemalto </a>and Intel demonstrated SafeNet Data Protection On-Demand*, a cloud-based, security-as-a-service platform that offers developers a single gateway to implement software solutions direct to Intel SGX. </li>
<li><a href="https://www.worldpay.com/us" target="_blank" rel="nofollow">Worldpay </a>and Intel demonstrated Worldpay Within* using Intel SGX secure enclaves to enable and protect payments between connected cars and other IoT devices—examples include electric vehicle (EV) charging, bridge tolls, and more.</li>
</ul><h3>5G possibilities are 'beyond exciting'</h3>
<div>Intel is helping create global standards, sparking new business models, and partnering with telcos and network operators around the world. </div>
<div>“5G will not just enable smart cities and fleets of autonomous vehicles,” says Intel Sr. VP Aicha Evans. “It’ll change the way athletes and spectators experience the Olympic Games.” </div>
<div><span class="full-content-width"><img alt="Intel Sr. VP Aicha Evans speaking at MWC-2018" title="Intel Sr. VP Aicha Evans speaking at MWC-2018" class="full-content-width" src="https://software.intel.com/sites/default/files/managed/be/07/MWC-2018-6_sm%20.jpg" /></span><br /><em>Intel Sr. VP Aicha Evans speaking at MWC-2018</em></div>
<div>She added, “We’re beyond excited to make these possibilities a reality, as well as new ones that were previously unimaginable!”</div>
<div>For more information on Intel Software Development Tools and resources for network transformation, visit the <a href="https://software.intel.com/en-us/networking" target="_blank">Intel Developer Zone/networkin</a>g. </div>
Fri, 09 Mar 18 13:17:57 -0800Dan Fineberg (Intel)759273Top Ten Intel Software Developer Stories Marchhttps://software.intel.com/en-us/blogs/2018/03/08/top-ten-intel-software-developer-stories-march
<p style="text-align:center"><a href="/en-us/videos/vr-ux-an-introduction" rel="nofollow"><span><img alt="VR UX " title="VR UX " height="150" width="200" src="https://software.intel.com/sites/default/files/managed/f6/01/VR%20DJJa48_WAAEq72e.png" /></span></a></p>
<h4 style="text-align:center"><a href="https://software.intel.com/en-us/videos/vr-ux-an-introduction">VR UX: An Introduction</a></h4>
<p style="text-align:center"><span style="color:rgb(56, 64, 71)">Gain insight and learn new practices for creating VR games and applications with our new </span><em>VR UX</em><span style="color:rgb(56, 64, 71)"> weekly video miniseries.</span></p>
<hr /><p style="text-align:center"><a href="/en-us/blogs/2018/03/07/intel-two-day-deep-learning-training-april-29-30" rel="nofollow"><span><img alt="Deep Learning Training " title="Deep Learning Training " src="https://software.intel.com/sites/default/files/managed/59/4f/tutorial.png" /></span></a></p>
<h4 style="text-align:center"><a href="/en-us/blogs/2018/03/07/intel-two-day-deep-learning-training-april-29-30" rel="nofollow">Two Day Hands-On Deep Learning Training</a></h4>
<p style="text-align:center"><span style="color:rgb(56, 64, 71)">Join us in New York for our deep learning 2-day training at the O’Reilly Conference on April 29-30! From training to inference, create an end to end deep learning project using optimized hardware and software from Intel.</span></p>
<p style="text-align:center"> </p>
<hr /><p style="text-align:center"><a href="/en-us/videos/introduction-to-iot-in-industry-4-0" rel="nofollow"><span><img alt="Industrial IoT " title="Industrial IoT" src="https://software.intel.com/sites/default/files/managed/a4/6c/DRD_16_99-Q4-Machine-Learning-Mixed-Media-Campaign_Final_FB_1200x628_A.png" /></span></a></p>
<h4 style="text-align:center"><a href="https://software.intel.com/en-us/videos/introduction-to-iot-in-industry-4-0">Introduction to IoT in Industry 4.0</a></h4>
<p style="text-align:center"><span style="color:rgb(56, 64, 71)">In this webinar, see how IoT influences Industry 4.0 with the use of sensors and actuators.</span></p>
<hr /><p style="text-align:center"><a href="/en-us/videos/best-practices-and-performance-studies-for-high-performance-computing-clusters" rel="nofollow"><span><img alt="High Performance Clusters " title="High Performance Clusters " src="https://software.intel.com/sites/default/files/managed/bf/b1/CERN_0.png" /></span></a></p>
<h4 style="text-align:center"><a href="https://software.intel.com/en-us/videos/best-practices-and-performance-studies-for-high-performance-computing-clusters">Best Practices and Performance Studies for High-Performance Computing Clusters</a></h4>
<p style="text-align:center"><span style="color:rgb(56, 64, 71)">Watch this video to gain practical tips and techniques for building and running applications on multicore processors.</span></p>
<hr /><p style="text-align:center"><a href="/en-us/articles/detect-persistent-memory-programming-errors-with-intel-inspector-persistence-inspector" rel="nofollow"><span><img alt="Detect Persistent Memory" title="Detect Persistent Memory" src="https://software.intel.com/sites/default/files/managed/d3/e4/detect-persistent-mem-errors-fig2-flowchart.png" /></span></a></p>
<h4 style="text-align:center"><a href="https://software.intel.com/en-us/articles/detect-persistent-memory-programming-errors-with-intel-inspector-persistence-inspector">How to Detect Persistent Memory Programming Errors Using Intel® Inspector - Persistence Inspector</a></h4>
<p style="text-align:center"><span style="color:rgb(56, 64, 71)">Learn to mitigate persistent memory programming challenges with this tool that allows you to discover problem caching and other issues.</span></p>
<hr /><p style="text-align:center"><a href="/en-us/videos/vr-ux-social-safety" rel="nofollow"><span><img alt="UX Security " title="UX Security " src="https://software.intel.com/sites/default/files/managed/b8/22/Untitled.png" /></span></a></p>
<h4 style="text-align:center"><a href="https://software.intel.com/en-us/videos/vr-ux-social-safety">VR UX: Social Safety</a></h4>
<p style="text-align:center"><span style="color:rgb(56, 64, 71)">Learn how you can create a safe environment and experience for your users in a social or multiplayer environment.</span></p>
<hr /><p style="text-align:center"><a href="/en-us/node/754929" rel="nofollow"><span><img alt="Visual Retail Solutions " title="Visual Retail Solutions " src="https://software.intel.com/sites/default/files/managed/0d/b3/retail-apparel-woman-shopping-digital-sign-0Z0A4491-1-3x2.zip.renditions.cq5dam.web_.1280.1280.png" /></span></a></p>
<h4 style="text-align:center"><a href="https://software.intel.com/en-us/node/754929">Develop Visual Retail Solutions Using Intel® Hardware and Software</a></h4>
<p style="text-align:center"><span style="color:rgb(56, 64, 71)">Download labs and learn to create advanced retail solutions, such as building a sample video decoder.</span></p>
<hr /><p style="text-align:center"><a href="https://en-us/articles/lower-numerical-precision-deep-learning-inference-and-training" rel="nofollow"><span><img alt="Deep Learning Inference" title="Deep Learning Inference" src="https://software.intel.com/sites/default/files/managed/4f/69/MachineLearning-Category.png" /></span></a></p>
<h4 style="text-align:center"><a href="https://software.intel.com/en-us/articles/lower-numerical-precision-deep-learning-inference-and-training">Lower Numerical Precision in Deep Learning Inference and Training</a></h4>
<p style="text-align:center"><span style="color:rgb(56, 64, 71)">Review the history of lower numerical precision in training and inference and understand how Intel is enabling it for deep learning.</span></p>
<hr /><p style="text-align:center"><a href="/en-us/articles/intel-xeon-scalable-processors-deliver-performance-boosts-for-it-and-developers" rel="nofollow"><span><img alt="Performance Boosts" title="Performance Boosts" src="https://software.intel.com/sites/default/files/managed/0a/cf/4xpng_0.png" /></span></a></p>
<h4 style="text-align:center"><a href="https://software.intel.com/en-us/articles/intel-xeon-scalable-processors-deliver-performance-boosts-for-it-and-developers">Intel® Xeon® Scalable Processors Deliver Performance Boosts for IT and Developers</a></h4>
<p style="text-align:center"><span style="color:rgb(56, 64, 71)">Learn how Aerospike* (a hybrid memory architecture database ) increased their performance up to four times by enhancing their software with capabilities such as auto-tuning and more.</span></p>
<hr /><p style="text-align:center"><span style="color:rgb(56, 64, 71)">Intel® Developer Zone experts, Intel® Software Innovators, and Intel® Black Belt Software Developers contribute hundreds of helpful articles and blog posts every month. From code samples to how-to guides, we gather the most popular software developer stories in one place each month so you don’t miss a thing. Missed last month? <a href="/en-us/blogs/2018/02/08/top-ten-intel-software-developer-stories-february" rel="nofollow">Read it here. </a></span></p>
<p style="text-align:center"><span><img alt="Top 10-icon" title="Top Ten Intel Software Developer Stories" src="https://software.intel.com/sites/default/files/managed/de/0f/Top10-Icon.jpg" /></span></p>
Thu, 08 Mar 18 15:44:34 -0800Karissa Pagliero (Intel)759233Implementing MicroPython as a UEFI Test Frameworkhttps://software.intel.com/en-us/blogs/2018/03/08/implementing-micropython-as-a-uefi-test-framework
<p>Since its introduction in 2005, the Unified Extensible Firmware Interface (<a href="http://uefi.org/" rel="nofollow">UEFI</a>) has become the primary standard for firmware development. As the industry continues to develop Embedded Development Kit II (<a href="https://github.com/tianocore/edk2/" rel="nofollow">EDK II</a>) as a core UEFI component, we are also supporting test frameworks to accelerate firmware validation.</p>
<hr /><p><a href="https://www.python.org/" rel="nofollow">Python</a> is a popular high-level interpreted language, common in automated testing environments. While C is still the language of choice for developing UEFI firmware components, Python support allows validation engineers to apply existing skills from operating system (OS) level scripting to UEFI unit tests and manufacturing line applications.</p>
<p>Python already is used for a number of UEFI platform tests. <a href="https://tianocore.org/" rel="nofollow">TianoCore</a> currently includes a <a href="https://github.com/tianocore/edk2/tree/master/AppPkg/Applications/Python" rel="nofollow">CPython 2.7.10 implementation as part of EDK II</a>. The <a href="https://github.com/chipsec/chipsec" rel="nofollow">CHIPSEC</a> platform security assessment framework uses Python to execute the same scripts across Microsoft* Windows, Linux*, Mac OS X*, and <a href="https://github.com/tianocore/tianocore.github.io/wiki/ShellPkg" rel="nofollow">UEFI Shell</a> environments. However, the existing EDK II port of <a href="https://en.wikipedia.org/wiki/CPython" rel="nofollow">CPython</a> has several limitations:</p>
<ul><li>Large footprint &amp; poor performance (compared to native C code)</li>
<li>Scripts to not have direct access to EDK II or hardware resources</li>
<li>Limited usage with UEFI Shell dependencies</li>
<li><a href="https://pythonclock.org/" rel="nofollow">Python 2.7.x tree scheduled for end-of-life in 2020</a></li>
</ul><p>Because of Python’s flexibility and wide adoption, my team investigated several options to support Python 3.x in UEFI boot services. Because firmware is a constrained environment compared to OS runtime, we evaluated porting <a href="https://micropython.org/" rel="nofollow">MicroPython</a> to UEFI. MicroPython is a Python 3 variant designed for microcontrollers, with memory and size optimizations that make it ideal for pre-OS applications.</p>
<p><a href="https://micropython.org" target="_blank" rel="nofollow"><span class="one-quarter-float-right"><img alt="MicroPython" title="MicroPython" height="334" width="334" style="width:215.6px" class="one-quarter-float-right" src="https://software.intel.com/sites/default/files/managed/74/34/micropython.png" /></span></a></p>
<div>
<p>My colleagues will present an overview of a MicroPython-based UEFI test framework at the <a href="http://uefi.org/SpringPlugfest2018" rel="nofollow">Spring 2018 UEFI </a><a href="http://uefi.org/SpringPlugfest2018" rel="nofollow">Plugfest</a> (March 26-30 in Bellevue, WA). This framework provides scripts with access to UEFI and EDK II interfaces, along with access to hardware resources. We also see this as an ideal environment for rapid prototyping of UEFI applications, and replacing legacy applications still used in manufacturing environments. MicroPython also extends support for existing UEFI CPython scripts, since the <a href="https://pythonclock.org/" rel="nofollow">Python 2.7 tree is scheduled for end-of-life in 2020</a>.</p>
<div>
<p>Using MicroPython for a firmware test framework leverages Python experience from validation engineers and a Python interpreted optimized for execution in constrained environments. There aren’t many unified EDK II testing frameworks optimized for both development and validation engineers. Extending the Python model adopted by <a href="https://github.com/chipsec/chipsec" rel="nofollow">CHIPSEC</a> to a common framework expands validation capabilities for <a href="https://tianocore.org/" rel="nofollow">open source UEFI firmware</a>.</p>
<p>Firmware is a critical platform component, with a limited number of developers who understand its development and validation. Supporting Python 3.x &amp; MicroPython in open source creates new opportunities for the TianoCore community to validate robust firmware solutions.</p>
<p><span class="full-page-width"><img alt="MicroPython for UEFI - Stack Overview" title="MicroPython for UEFI - Stack Overview" class="full-page-width" src="https://software.intel.com/sites/default/files/managed/a0/5e/Spring%202018%20UEFI_Plugfest_MicroPythonUEFI%202018%20CHM.png" /></span></p>
<p>The upcoming presentation at the <a href="http://uefi.org/SpringPlugfest2018" rel="nofollow">Spring 2018 UEFI Plugfest</a> will introduce plans for developing and releasing this test framework. If you’re interested in following this project, check out the <a href="http://www.tianocore.org/contrib/" rel="nofollow">“How to Contribute” page on tianocore.org</a>.</p>
</div>
</div>
Thu, 08 Mar 18 13:15:06 -0800Brian Richardson (Intel)759228