8 to 1 MUX w/ two 4 to 1 MUX and one 2 to 4 BIN/DEC decoder

Draw a diagram to show how to implement a 8 to 1 multiplexer with two 4 to 1 multiplexers and a 2 to 4 binary to decimal decoder.

2. Relevant equations

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3. The attempt at a solution

I know that I'm going to need another select line (S2) since an 8 to 3 multiplexer has 3 select lines but I've been struggling with the decoder. I have no idea what purpose the decoder should serve. Any help would be appreciated :).

Staff: Mentor

Draw a diagram to show how to implement a 8 to 1 multiplexer with two 4 to 1 multiplexers and a 2 to 4 binary to decimal decoder.

2. Relevant equations

/

3. The attempt at a solution

I know that I'm going to need another select line (S2) since an 8 to 3 multiplexer has 3 select lines but I've been struggling with the decoder. I have no idea what purpose the decoder should serve. Any help would be appreciated :).

What is a "2 to 4 binary to decimal decoder"? Is that a typo? 2 binary bits to a 4-bit decimal representation? Can you post a schematic of the logic arrangement of this decoder?

Like this, except with 2 inputs and 4 outputs, and I guess we could also assume positive logic (so no inverters on the output side). The decoder could also have a chip select / enable line but I'm still not seeing how to implement it.

Staff: Mentor

Umm, no. A demultiplexer is the opposite of a multiplexer. A decoder is just like the picture I attached above. For example, if all the inputs are high except A2 then in binary thats 11 so pin 11 on the output side would be high (ie. without those inverters on the chip in the picture above.) This decoder has no select lines, but a demxer would.

Staff: Mentor

Umm, no. A demultiplexer is the opposite of a multiplexer. A decoder is just like the picture I attached above. For example, if all the inputs are high except A2 then in binary thats 11 so pin 11 on the output side would be high (ie. without those inverters on the chip in the picture above.) This decoder has no select lines, but a demxer would.

Staff: Mentor

They could, yeah. So the decoder would control whether or not the multiplexer is enabled? I tried thinking about that but then the decoder has 4 outputs but there are only be 2 enables (1 for each multiplexer) ...

Staff: Mentor

They could, yeah. So the decoder would control whether or not the multiplexer is enabled? I tried thinking about that but then the decoder has 4 outputs but there are only be 2 enables (1 for each multiplexer) ...

Think about using only one input to the 2:4 decoder and tie off the other input. Use the one input as a High/Low MUX select line, which generates two OE~ signals at the output of the 2:4 decoder...