The phrases "adaptive writes", "DSP
IP in flash SSD" and "adaptive flash cell care" have appeared
at various times in
past SSD
news stories, interviews and comments.

And while I sketched out as much
explanation as was needed for each story at the time - I did promise I would
eventually publish a list of SSD companies who use what I loosely called back
then "adaptive DSP technologies in SSD IP" in their new designs along
with a technology and market guide.

This article is it.

A
year ago there were only 4 or 5 companies doing this kind of thing - but I
could see this technology trend was creeping into double digits of companies
and when that happens in the SSD market you know that something significant is
going on.

Why are these new adaptive technologies important?

They
change the rules about what SSD designers can do with cheap consumer grade MLC
and TLC (x3) flash.

As I said in an
earlier article -
they reset the commonly held assumptions about the limitations of
endurance -
but that's just a small part of the new effect.

Here's a summary of
what the new technologies enable in different segments of the SSD market

enterprise SSDs
- changes the economics in fast-enough SSDs - because consumer grade MLC in the
new SSDs can last as long as more expensive eMLC.

But another
byproduct of the new technologies is that SSDs which use it can also have
significantly faster write cycles (greater
IOPS) - and
operate at lower power

Each of these bullet points represents a
potential competitive advantage for the early adopters of these new technologies
in whichever SSD segment they are applied. But the bag of magic tricks can be
used to provide different characteristics for the different markets.

Currently
only a small percentage of SSD makers deploy these technologies. In fact each of
the many companies I spoke to about this in recent months believed they were
just one of a handful of companies doing anything similar.

I told
them how wrong they were and that they might be surprised when I published this
article.

Driving the need to develop these extraordinarily complex SSD
technologies is the certain knowledge and fear that traditional SSD controller
IP will fail to deliver working SSDs with future shrinks of flash geometry.

That means a successful SSD company in generation X flash may wake up
to be told by its designers that its SSDs using generation Z flash - can't be
made to operate at all - let alone last for 1, 2 or 5 years. (Time for the
company's VPs to create / update their bios on Linkedin.)

On the one
hand - companies which have already got the new SSD magic wands - such as
STEC - told me over a
year ago they are confident that they may see an upturn in their businesses when
their competitors (without adaptive designs) start to fall off the new flash
technology cliff.

On the other hand - with the
SSD market share
prizes getting bigger - it's more likely that enterprising SSD IP companies
will step in to sell their own maps of safe ways around the cliff - and that's
the business plan of DensBits.

But
I'm running ahead of myself now by mentioning companies.

Before I get
onto that - it's worth asking - What's at the core of the new SSD adaptive
technologies?

The simple answer has 3 parts

adapting the write pulse energy in the flash memory to be as low as can be
- while at the same time providing usable
data integrity
with the attached ECC / DSP technology

designing a set of ECC / DSP technology which can provide usable data
integrity.

Unlike traditional SSD designs - the ECC/ DSP strength and
actual choice of algorithms can be adapted to suit the flash memory according
the circumstances.

That means the same memory block may have different
ECC codes wrapped around it at different times in its operating life - depending
how healthy it looks. And different ECC codes may be used within the same memory
chip at the same time.

Other techniques include adapting the spatial distribution of data - and
making the data striping plans more flexible than traditional designs.

None
of these individual design philosophies is entirely new.

Systems designers like me working with the first generation of flash chips
in the early 1980s could see clearly that some locations were harder to program
than others - because the write pulses were an external user designed circuit
and software algorithm.

In later generations of flash - the
chipmakers embedded the write pulse circuits inside the memory chips to make it
easier for digital designers to use flash - and to reduce the risk of systems
designers over cooking the flash. So the awareness of this parameter may have
gone away for systems designers - but it was always an important part of the
memory chip design.

Adapting to the reliability population curve of flash memory too - with
different controller technologies like wear-leveling and bad block management
goes back to the early 1990s and a company called
M-Systems.

Spatial scattering of data across multiple memory chips in SSDs with
RAID goes back to the
1990s too and a company called
Solid Data Systems.

Variability in this parameter (variable size stripes) has been used in 2
generations of SSD designs already by
Texas Memory Systems.

What
is new about the new adaptive SSD flash care management IP is that instead
of each of these parameters and design rules being fixed at the time of
manufacturing the SSD according to an idea of what works best for the
population of flash chips in this current generation - as with traditional
controller designs - the new adaptive SSDs have smarter technologies which
can each dynamically interact and learn from the chips they're connected to.

You don't have to understand the internal details of how these
individual techniques work.

And with hundreds of patents already
pending in this topic there's a high probability that the SSD vendor won't give
you the details anyway (not even under NDA) and even if you are yourself among
the rare set of people on the planet with the
educational
background to understand them.

It's enough to get the general idea.

Now
as we're talking about the SSD market here - you don't really expect that
anything - will stay clear cut for long. And so you won't be surprised to know
that it isn't.

Earlier this year for example -
Smart Storage
launched SSDs which used the knowledge learned from tweaking its adaptive SSD
controllers and then reapplied this back as a set of fixed paramters to
precondition flash chips so they would run better with traditional unmodified
controllers from LSI/SandForce.
You can think of this as presetting the write pulse parameters in the memory
chips with a better set of magic numbers than even the memory chip makers or
SandForce themselves would have come up with on their own.

When that product was launched in
April 2012 - I
said ""SMART's trick with the SandForce controllers is like using
Dolby correction with a 1980s cassette tape. Whereas SMART's trick with its
Optimus controller is like having a built-in dynamic sound equalizer."

I
doubt if that's the last we'll hear about
hybridizing
some of the IP knowledge acquired from developing these newer technologies and
then reapplying them back into earlier designs to stretch their market life.

I
promised you some kind of list of companies who are using these new adaptive
technologies inside their SSD designs - so here goes.

The list below
is my first draft - except that the first draft excluded LSI - which didn't
have this technology at that time.

In the years following publication
most of these DSP ECC pioneers were
acquired by
other companies.

My
preliminary list above and the expanded list later is only going to include
companies which have developed their own SSD controllers which use these new
adaptive techniques - and not companies which
simply license IP
from a DSP IP controller company.

NAND statistics collection constructs the history
of the NAND flash memory cell characteristics and facilitates the estimation of
the reliability of each bit. To obtain soft information from the memory cell,
extra read commands or test mode sequences are required. These commands are
proprietary to the NAND flash manufacturer and a vendor implementing DSP would
require the NAND flash manufacturer to provide these commands.

Needless
to say, not all controller/SSD vendors will obtain this support.

Advanced decoding schemes employing soft decoding use the NAND
statistics and soft information to determine the most probable read signal
that corresponds to the actual stored data.

This allows you to
obtain readable data even when the memory cell is severely degraded or there is
a lot of 'noise' in cell data.

That is why you see companies like
Anobit and Densbits claiming a 10x improvement in endurance. STEC and Smart
Storage also claim to have similar technology.

This article will
help you understand why some SSDs which (work perfectly well in one type of
application) might fail in others... even when the changes in the operational
environment appear to be negligible.

As every SSDmouse knows -
measuring stuff and adapting to what you know gives you safer operating speed,
better reliability and lower TCO.

.....

summary

In
the future - all nand flash SSDs will have to use adaptive R/W and DSP ECC IP
technologies in their
controller schemes in
order to be able to use newer generations of denser flash memory. Among other
things these adaptive R/W techniques can magnify
reliability and
performance while
improving SSD design
efficiency and reducing
cost.

As
we go through the transition
years - all the safe assumptions which you thought you knew about flash SSDs
and suppliers will change (again).

.....

The interesting thing about
NVMdurance's IP is that it delivers endurance amplifying results using a
lightweight runtime controller.

But this doesn't stop you getting
even better results by adding DSP correction as an additive process.

Editor:- January 23, 2015 - Even if you already
thought that adaptive
R/W and DSP was an essential way for getting usable SSDs out of smaller 2D
nand flash - then there are even more reasons for using this technology on the
journey in 3D.

Among other
things in this paper:- DensBits says that the scope for inter-cell interference
grows from 8 identifiable routes in 2D to 26 for each cell in 3D.

But
memory modem technology (DensBits's branding for their collection of adaptive
R/W DSP IPs) will (over and above everything it already does for 2D)
intelligently decouple read operations according to the severity of read
operations expected in the new 3D architectures - and even supports the notion
of TLC (x3) within 3D. (Which "needs state of art decoder and signal
processing".)

Editor:- June 15, 2010 - Anobitannounced
it is sampling SSDs based on its patented Memory Signal Processing technology
which provide
20x improvement in operational life for MLC SSDs in high IOPS server
environments.

Based on proprietary algorithms that compensate for the
physical limitations of NAND flash, Anobit's technology (a variation of
adaptive R/W
and DSP ECC) extends standard MLC endurance from approximately 3K
read/write cycles to over 50K cycles - to make MLC technology suitable for
high-duty cycle applications.

All SSDs rely on processing data
about the quality of the memory as part of their normal data integrity
operations.

They wouldn't work without it.

But some companies have SSD IP sets in which knowledge about different
parts of the SSD can be optimized and fed back to control and enhance SSD
functionality over and beyond the standard accepted SSD function block
boundaries.

The degree to which this passing of the intelligence
(regarding the state of past and future anticipatable data flows, priorities
of the application and the flash array's own readiness and healthiness
condition) can impact behavior in other parts of the SSD - is what I call
adaptive intelligence flow symmetry.

And
instead of applying different strengths of
ECC for fixed
physical block sizes - the company says another approach is to have variable
sized virtual blocks - which effectively means that better cells carry lower ECC
overhead.