Let’s Build a Rocket Chip

I’ve been looking at various open-source RISC-V cores to hook up to the 2D sprite renderer I’ve been working on, and it looks like Rocket Chip is the way to go, since it’s so highly-configurable. That’s perfect for me, because game system cores have always been highly custom.

Let’s see what it takes to build some RTL on a stock Ubuntu 18.04 LTS install:

Okay, if all goes well, in generated-src you should have the conveniently-named “freechips.rocketchip.system.DefaultFPGAConfig.v”

At this point I think I’ve added enough value to this post to publish it.

Next steps:

Delete the TestHarness module from the file (“freechips.rocketchip.system.DefaultFPGAConfig.v”, which I’ve renamed “freechips.rocketchip.system.DefaultFPGAConfig_TestHarness_removed.v”)

Add my own SystemVerilog testbench file, which will instantiate “ExampleRocketSystem” from the file (“Rocket” is the actual top-level module, but that only exposes a TileLink interface, and might be missing some default configuration).

Copy some necessary verilog files into the generated-src directory (just because it seems more convenient to me, you can leave them where they are.

When I run this, it doesn’t actually do anything, and by that I mean, not a single signal changes state after reset, presumably it’s waiting for some AXI handshaking to take place, or maybe I’m holding it in some reset state somehow. I’ll have to look at TestHarness more closely…