Re: How to snyc one 7 Series Transceiver to anothe

I have not worked with such video streams, but in general a receiving transceiver locks to the incoming data.
If you want the same data to be "forwarded" out an another transceiver, the data will be clocked out locked to a local oscillator.
If the units are not locked to each other, there will always be a small difference in clock frequencies.
To handle this, the transport protocol must have some slack. This is normally done by inserting some redundant K symbols in the lowest layer.
If the incoming data has no slack, you must make sure that your transmit data rate is slightly higher than the incoming data rate.

Re: How to snyc one 7 Series Transceiver to anothe

Transceivers use clock recovery as the clock information is embedded in the data.

I would say this is probably has nothing to do with the data rates or slight frequency differences between the transmit and local clocks, I suspect this is an SI problem. Especially as you make it sound like the failures are somewhat random. Rate mismatches tend to result in discernible patterns of errors.

Have you hooked up a high speed scope and verified the eye opening is large enough to meet the 3G-SDI spec?

Have you played around with the Serial IO debug tools? You might want to use that to test the hardware and try to find optimal settings for the emphasis and equalization in your particular application.

Re: How to snyc one 7 Series Transceiver to anothe

Have you played around with the Serial IO debug tools?

I second this. The debug tools should have already been used if this is a prototype. If this is not a prototype, you can easily get these set up.

I also suggest adding connections between config/diag ports on the tiles and any software control interface. The ability to determine link margin and configure the interfaces has value. I'm not sure if Xilinx has gone full-crazy with encrypted IP though.

Other random suggestions:
1.) 8b10b is mostly symmetric but not entirely. It is possible to get an inverted polarity that almost works and looks like a fairly high bit-error rate. (but repeatable and less than a fully corrupted link)
2.) DFE is probably not useful at these rates if you don't have a long backplane or connectors.
3.) Avoid over-EQ and excessively high/low drivers.
4.) You can also use something other than 12G SDI if you control both ends of this interface.
5.) In the worst case, you can add ECC. (or retransmit)