4 1. Product Description 1.1 Introduction pacer s SFD18S4-M is a solid-state disk (SSD) drive that contains a controller, embedded firmware, and flash media along with a male connector. Using NND flash memory devices, the SFD drive interfaces with the host allowing data to be seamlessly transferred between the host and the flash devices. SFD18S4-M drive is designed with a single-chip controller, offering capacities of up to 128 gigabytes and providing full support for the STⅡ high-speed interface standard. It can operate at sustained access rates of up to 100 megabytes per second, which is much faster than any other solid-state or traditional ST drive currently available on the market. Though built with MLC, this SSD can work in highly demanding environment as it can withstand ambient temperature from -40 C to +85 C (for certain capacities only). In addition to buffer management through dynamical allocation, SFD18S4-M adopts the pacer-specific global wear-leveling scheme to allow uniform use of all storage blocks, ensuring that the lifetime of a flash media can be significantly increased and the disk performance is optimized as well. SFD18S4-M provides the S.M..R.T. feature that follows the ST Rev. 2.6, T/TPI-7 specifications and uses the standard SMRT command 0h to read data from the drive. This feature protects the user from unscheduled downtime by monitoring and storing critical drive performance. 1.2 Functional lock Diagram SFD18S4-M drive includes a single-chip STⅡ Controller and the flash media, as well as the ST standard interface. The controller integrates the flash management unit with the controller itself to support multi-channel, multi-bank flash arrays. Figure 1-1 shows the functional block diagram. Figure 1-1 pacer SFD18S4-M block diagram 3

7 Figure 1-3 ST Cable/Connector Connection Diagram The connector on the left represents the Host with TX/RX differential pairs connected to a cable. The connector on the right shows the Device with TX/RX differential pairs also connected to the cable. Notice also the ground path connecting the shielding of the cable to the Cable Receptacle. 6

9 2.2 S.M..R.T. S.M..R.T. is an acronym for Self-Monitoring, nalysis and Reporting Technology, an open standard allowing disk drives to automatically monitor their own health and report potential problems. It protects the user from unscheduled downtime by monitoring and storing critical drive performance and calibration parameters. Ideally, this should allow taking proactive actions to prevent impending drive failure. pacer devices use the standard SMRT command 0h to read data out from the drive to activate our SMRT feature that complies with the T/TPI-7 specifications. ased on the SFF-8035i Rev. 2.0 specifications, pacer SMRT defines vendor-specified SMRT ttribute IDs (0 ~ 5, and 0C). They represent Initial bad block count, ad block count, Spare block count, Maximum erase count, verage erase count and Power cycle. When the pacer SMRT Utility running on the host, it analyzes and reports the disk status to the host before the device reaches in critical condition. 8

10 3. Flash Management 3.1 Error Correction/Detection SFD18S4-M implements a hardware ECC scheme, based on the CH algorithm. It can detect and correct up to 16 bits or 24 bits error in 1K bytes. 3.2 ad lock Management lthough bad blocks on the flash media are already identified by the flash manufacturer, they can also be accumulated over time during operation. SFD18S4-M s controller maintains a table that lists those normal blocks with disk data, the free blocks for wear leveling, and bad blocks with errors. When a normal block is detected broken, it is replaced with a free block and listed as a bad block. When a free block is detected broken, it is then removed from the free block list and marked as a bad block. During device operation, this ensures that newly accumulated bad blocks are transparent to the host. The device will stop file write service once there are only two free blocks left such that the read function is still available for copying the files from the disk into another. 3.3 Wear Leveling The NND flash devices are limited by a certain number of write cycles. When using a FT-based file system, frequent FT table updates are required. If some area on the flash wears out faster than others, it would significantly reduce the lifetime of the whole SSD, even if the erase counts of others are far from the write cycle limit. Thus, if the write cycles can be distributed evenly across the media, the lifetime of the media can be prolonged significantly. This scheme is called wear leveling. pacer s wear-leveling scheme is achieved both via buffer management and pacer-specific static wear leveling. They both ensure that the lifetime of the flash media can be increased, and the disk access performance is optimized as well. 3.4 Power Failure Management Power Failure Recovery ensures data transmission when experiencing unstable power supply. When power disruption takes places, NND Flash will have to cache multiple write-to-flash cycles to securely store data. This urgent operation requires about several milliseconds to get it done. When the supplied voltage is below a certain percentage of the required, the flash controller will be signaled by a detector IC component with low power detection signal and then the firmware will communicate the controller to flush all the data into the cache of Flash storage area. This can prevent incomplete data transmission. The crucial part lies in the strength of the capacitor of the SSD. The capacitor must be able to hold up some milliseconds of remaining time before the power is totally out, for the urgent write-back-into-flash operations to complete. 3.5 T Secure Erase ccomplished by the Secure Erase (SE) command, which added to the open NSI standards that control disk drives, T Secure Erase is built into the disk drive itself and thus far less susceptible to malicious software attacks than external software utilities. It is a positive easy-to-use data destroy command, amounting to electronic data shredding. Executing the command causes a drive to internally completely erase all possible user data. This command is carried out within disk drives, so no additional software is required. Once executed, neither data nor the erase counter on the device would be recoverable, which blurs the accuracy of device 9

11 lifespan. The process to erase will not be stopped until finished while encountering power failure, and will be continued when power is back on. 3.6 TRIM Made of millions of NND flash cells, SSD can be written into groups called pages in 4K size generally, but can only be erased in larger groups called blocks of 128 pages or 512K. These stipulations are partially the source of many performance issues. Until an address gets used again, the SSD has to keep track of every last bit of data that s written on it. The T-TRIM instruction tilts the balance in favor of the SSD. TRIM addresses a major part of the performance degradation issue over time that plagues all SSDs. TRIM enabled drive running an OS with TRIM support will stay closer to its peak performance over time. 10

14 (VCP Right) 25-4kV 5.4 Electrical Fast Transient/urst Electrical Fast Transient/urst Inject Line Polarity Voltage kv Inject Time (Second) Inject Method Required Criteria Complied to Criteria L-N-PE ± 1kV 60 Direct Notes about 5.3 Electrostatic Discharge & 5.4 Electrical Fast Transient/urst The tests performed are from lowest level up to the highest level as required by standard, but only highest level is shown on the report. Meet criteria : Operate as intended during and after the test Meet criteria : Operate as intended after the test Meet criteria C: Loss/Error of function dditional Information: EUT stopped operation and could / could not be reset by operator at kv. No false alarms or other malfunctions were observed during or after the test. The Contact discharges were applied at least total 200 discharges at a minimum of four test points. 13

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