The X1 uses a 1.2 ns (800 MHz) clock cycle, and 8-wide vector pipes in MSP mode, offering a peak speed of 12.8 gigaflops per processor. Air-cooled models are available with up to 64 processors. Liquid-cooled systems scale to a theoretical maximum of 4096 processors, comprising 1024 shared-memory nodes connected in a two-dimensional torus network, in 32 frames. Such a system would supply a peak speed of 50 teraflops. The largest unclassified X1 system was the 512 processor system at Oak Ridge National Laboratory, though this has since been upgraded to an X1E system.

In 2005, Cray released the X1E upgrade, which uses dual-core processors, allowing two quad-processor nodes to fit on a node board. The processors are also upgraded to 1150 MHz. This upgrade almost triples the peak performance per board, but reduces the per-processor memory and interconnect bandwidth. X1 and X1E boards can be combined within the same system.

The X1 is notable for its development being partly funded by United States Government's National Security Agency (under the code name SV2).[1] The X1 was not a financially successful product[2] and it seems doubtful that it or its successors would have been produced without this support.