Mode 0 (CPOL=0, CPHA=0) sets the bit on the falling edge, and then samples on the next rising edge.Mode 1 (CPOL=0, CPHA=1) set the bit on the rising edge, and then samples on the next falling edge.Mode 2 (CPOL=1, CPHA=0) sets the bit on the rising edge, and then samples on the next falling edge.Mode 3 (CPOL=1, CPHA=1) sets the bit on the falling edge, and then samples on the next rising edge.

I'm looking for clarification as to how to properly use SPI_CK_I_EDGE and SPI_CK_OUT_EDGE to control the behavior of when MISO is sampled.

Setting SPI_CK_OUT_EDGE to 1=rising edge and 0=falling edge per the above description correctly transitions the MOSI bit at the right time.

However, my guess that SPI_CK_I_EDGE controlled MISO was not accurate - the value here does not seem to have any effect of when the ESP8266 reads the MISO bit. In fact, testing shows that the ESP8266 is reading the MISO bit on the same clock edge that it uses to set MOSI.

Mode 0 (CPOL=0, CPHA=0) sets the bit on the falling edge, and then samples on the next rising edge.Mode 1 (CPOL=0, CPHA=1) set the bit on the rising edge, and then samples on the next falling edge.Mode 2 (CPOL=1, CPHA=0) sets the bit on the rising edge, and then samples on the next falling edge.Mode 3 (CPOL=1, CPHA=1) sets the bit on the falling edge, and then samples on the next rising edge.

I'm looking for clarification as to how to properly use SPI_CK_I_EDGE and SPI_CK_OUT_EDGE to control the behavior of when MISO is sampled.

Setting SPI_CK_OUT_EDGE to 1=rising edge and 0=falling edge per the above description correctly transitions the MOSI bit at the right time.

However, my guess that SPI_CK_I_EDGE controlled MISO was not accurate - the value here does not seem to have any effect of when the ESP8266 reads the MISO bit. In fact, testing shows that the ESP8266 is reading the MISO bit on the same clock edge that it uses to set MOSI.

Is there an undocumented bit that I am missing?

hi

in which mode you work, master or slave?what you need, when do you read valid data?

you wrote MoSi, that is Master Out, Serial in, in the past that was SDI named too.so you akt as Master to a Slave, right?

SPI_CK_I_EDGE (rising edge) and SPI_CK_OUT_EDGE (falling edge) are for your sampling the time position.example put Data on MOSI pin if CK low, the slave read at in next comming CK high wave then ( this is a half wave after CK was low.

For the purpose of this post, I was referring to using the ESP as a master.

In a recent enhancement to the NodeMCU firmware, we added support for Mode 2 and Mode 3. The MOSI edge (master out, or when the ESP sets the bit from the master) is successfully set using the SPI_CK_OUT_EDGE. However, the MISO (master in, or when the ESP reads the bit from the slave) does not occur on the next clock edge as it is supposed to - instead, it seems to be happening at the same time/same edge as MOSI.

The test to illustrate the behavior had the slave set 0xAA on the SPI so that the data was valid for the MOSI clock edge, but cleared for the MISO clock edge. The ESP should have read in 0x00 based on the defined behavior for SPI (since the bit was 0 for MISO's edge), but instead, it read in 0xAA (because it was sampling on MOSI's edge).

jfollas wrote:For the purpose of this post, I was referring to using the ESP as a master.

In a recent enhancement to the NodeMCU firmware, we added support for Mode 2 and Mode 3. The MOSI edge (master out, or when the ESP sets the bit from the master) is successfully set using the SPI_CK_OUT_EDGE. However, the MISO (master in, or when the ESP reads the bit from the slave) does not occur on the next clock edge as it is supposed to - instead, it seems to be happening at the same time/same edge as MOSI.

The test to illustrate the behavior had the slave set 0xAA on the SPI so that the data was valid for the MOSI clock edge, but cleared for the MISO clock edge. The ESP should have read in 0x00 based on the defined behavior for SPI (since the bit was 0 for MISO's edge), but instead, it read in 0xAA (because it was sampling on MOSI's edge).

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