"D. C. Sessions" <dc.sessions@vlsi.com> writes:> > I agree the best capacitance is on-die. It is expensive in die area, but> > becoming more and more essential as edge rates and speeds increase.> > However, there exist devices already without such provisions and I was still> > wondering whether capacitors can be placed under BGA packages to help> > existing power decoupling problems. Is it cost effective and> > manufacturable?> > On-chip decoupling isn't so much expensive in die area (because die> area is generally interconnect-dominated) but it does impact on yield> because of the increase in gate-oxide area where a gate failure can> cause a supply short.

This reminds me of an article I saw once about a fast IBM CMOS
processor that had on-chip decoupling capacitors (I don't remember any
specifics). If I recall correctly, the capacitors were made from large
square poly-diffusion thinox areas with diffusion contacts around the
edges, and with a minimum-with poly connection from each thinox poly
square to Vdd. If there was a short in the oxide, the narrow poly
connection would blow like a fuse and deconnect that decoupling
capacitor.

I think the series resistance with this layout means that the
decoupling capacitor is almost useless above maybe some hundred MHz.
If I am correct, on-chip decoupling is mostly useful at very high
frequencies (above the clock frequency) in order to reduce di/dt of
the supply wiring/pads. My idea of on-chip decoupling capacitor looks
like some kind of Scottish pattern:

The capacitance per area is of course lower than for a large thinox
area, but the series resistance is also much lower. I assume that both
structures use poly over N+ in N-well. Do you think this technique is
worthwhile, or is the series resistance not that critical?

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