In the timer control register CNTP_CTL, CNTHP_CTL, or CNTV_CTL:
— The timer is enabled.
— The timer output signal is not masked.
This means that, to deassert the timer output signal, software must do one of the following:
• Reprogram the timer registers so that neither of the timer conditions is met.
• Mask the timer output signal, in the timer control register.
• Disable the timer, in the timer control register.

So if i program CNTP_CTL & CNTP_TVAL , and lets say i program one of the core 0 timer registers for interrupts, at address 0x4000_0000, i am able to get the interrupts, but i am not able to clear the pending interrupts. Does anyone know how to clear the interrupt pending status for this timer?

Isnt the architected timer supposed to be one-shot (with automatic clearing of the status bit) ?

As mentioned in the original post, linux seems to be doing that (plus modifiying imask & istatus bits), i was curious if the other options as mentioned in the armv7 arm, would equally work (or probably my reading is wrong) or if there exists other means of clearing the pending interrupt. My previous experiments too showed what you have mentioned (setting the cntp_tval).