I have no clue how to implement an adder using two xor gates and a minimal number of 2 input Nand and Nor Gates. All we have learned about adders is that it has 3 inputs and produces 2 outputs (carry out and sum). I get that and how to make the truth table for it but idk what my professor is trying to get me to do. If anyone can explain that would be great.

I am not sure how to with two, I got the sum right by using one xor gate

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Do you REALLY need 1.5 MB files?

The description implies two 2-input XOR gates. If 3-input XOR gates are fair game, then what you did is fine as far as it goes, but by using two 2-input XOR gates you can reduce the number of 2-input NAND/NOR gates you need for the carry output.

The description implies two 2-input XOR gates. If 3-input XOR gates are fair game, then what you did is fine as far as it goes, but by using two 2-input XOR gates you can reduce the number of 2-input NAND/NOR gates you need for the carry output.

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Does this look right using two input gates? could I simplify them any further?

The 2 NOR gates are equivalent to an OR gate. Look up the equivalent of an OR gate using NAND gates. Redraw the circuit, and several simplifications will be apparent.

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what would be the most simplified way to do it using nor and nand gates? would I use them both? I'm not sure if my professor wants me to use both or just one. Im not good at simplifying them. Thats the only issue I have had in this class.

what would be the most simplified way to do it using nor and nand gates? would I use them both? I'm not sure if my professor wants me to use both or just one. Im not good at simplifying them. Thats the only issue I have had in this class.

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In this case, have you done what I suggested? It should be quite obvious how to simplify from the schematic that results.

Oh -- I thought you were thinking along the lines of reducing the NAND followed by the NAND with tied inputs down to an AND. But I see what you are focusing on -- the rightmost four gates and reducing that to a NAND.

Is this right? I really just used trial and error. I don't know how you guys can figure that stuff out so quickly

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Yes.

With experience and practice you learn how to spot things. One very useful technique is known as "bubble logic" where you basically apply DeMorgan's theorem graphically to the logic symbols by adding/moving inversion bubbles around and swapping OR with AND (or vice-versa) while adding bubbles to all inputs/outputs. If you do that to the left NOR gate, it becomes and AND gate with bubbles at the two inputs and no bubble at the output (the new bubble cancels the bubble that was already there). The final NOR gate is just an inverter and so it becomes a bubble at the output of the NOR gate. The bubbles at the inputs cancel the two NAND gates that are to the left of them, since each of those is just an invertor. You thereby replace the four right-most gates with a single NAND gate.

With experience and practice you learn how to spot things. One very useful technique is known as "bubble logic" where you basically apply DeMorgan's theorem graphically to the logic simples by adding/moving inversion bubbles around and swapping OR with AND (or vice-versa) while adding bubbles to all inputs/outputs. If you do that to the left NOR gate, it becomes and AND gate with bubbles at the two inputs and no bubble at the output (the new bubble cancels the bubble that was already there). The final NOR gate is just an inverter and so it becomes a bubble at the output of the NOR gate. The bubbles at the inputs cancel the two NAND gates that are to the left of them, since each of those is just an invertor. You thereby replace the four right-most gates with a single NAND gate.