JPEG-LS-D Core — XILINX FPGA Results

The JPEG-LS-D can be mapped to any Xilinx device, provided enough silicon resources are available. The size of a core depends on its configuration. The following table provides sample area and performance data for the JPEG-LS-D core mapped on a Kintex UltraScale device with -1 speed grade and excludes the image line buffer.

Core Version

Max. Bits per Sample

Max. NEAR Value

FPGA Resources

MSamples per sec

LUTs

BRAM Tiles

JPEG-LS-DS

8

0

7,076

2

100

4

7,442

2

100

8

7,858

2

95

10

0

7,414

2

100

4

8,067

2

92

8

8,301

2

85

16

0

9,782

2.5

98

4

10,823

2.5

78

8

11,021

2.5

57

JPEG-LS-DF with 3 cores

8

0

16,330

6

300

10

17,820

6

300

16

25.384

7.5

285

Note that the list of core configurations is not exhaustive, and that these sample implementation figures do not represent the highest speed or smallest area possible for the core. Please consult with CAST to get accurate characterization data for your target technology and required core configuration.