From README:

This is a Verilog-AMS 2.3 Parser Frontend. Publicly available Verilog-A and Verilog-AMS files are preprocessed and parsed correctly. The Parse tree is internally stored in a VPI-object-tree representation, but no elaboration, compilation or synthesis is performed. In addition to the parser you find a simple arbitrary-precision 4-state-Verilog-vector arithmetic implementation.

I started working on this some while ago as proof-of-concept. Unfortunately I will probably not find the required time to continue this project anytime soon.

In the hope that this work may be useful or inspiring to others I nevertheless release this fragment on SourceForge. Please contact me if you need repository access, want to take over maintenance and administrator rights for the project page. Visit the Sourceforge project page to access the repository (Click on logo below). 3rd-party dependencies and external testbench repositories are fetched automatically by make. To check out code, dependencies, build the code and run test bench samples, type: