NAND, PCM vie for ISSCC attention

LONDON – Multiple non-volatile memory technologies will be represented at next year's International Solid-State Circuits Conference, due to take place in San Francisco, California, Feb. 20 to 24, 2011.

This makes the point that progress is getting increasingly tough and that none of the competing technologies – neither flash, MRAM, ferroelectric, phase-change nor other forms of resistive memory, has achieved the overwhelming fundamental or applied engineering dominance to quash the others. Each non-volatile memory type has its proponents and applications where they think it might succeed.

Developments in NAND flash memory over the past few years are resulting in high-density, low-power, and low-cost storage solutions that are enabling the replacement of hard-disk storage in computers with solid-state disks (SSDs). At ISSCC 2011, engineers from Toshiba and SanDisk are due to present a 64-Gbit NAND flash memory in 24-nm CMOS with two-bits per cell. At 151 square millimeters this is the smallest die size for such a device yet reported and Toshiba and Sandisk are also set to describe programming algorithms that improve the data-write throughput of the device by 5 percent.

Later in the same session there is a paper from Samsung engineers that discusses a 64-Gbit triple layer cell NAND flash memory in what the abstract calls a 20nm-node technology but which elsewhere is referenced as 28-nm. The focus of the Samsung device is on improving the data transmission rate and the device is reported to implement a 7-Mbyte per second write rate and a 200-Mbit/s asynchronous DDR interface.

The fast pace of miniaturization of flash memory minimum dimensions has done much to keep other non-volatile memory technologies away from commercialization, but many are now predicting that flash may struggle to get below 22-nm.

Phase-change memory which is being offered commercially with lower capacity memories implemented at 128-Mbit at 90-nm and 512-Mbit at 65-nm is represented by a single paper at ISSCC 2011. Samsung engineers are due to report on a 1-Gbit phase-change memory implemented in a 58-nm process with a specialized low-power double-data-rate nonvolatile-memory (LPDDR2-N) interface. To enhance the core-write performance of 6.4-Mbyte per second the engineers have included a timing controller and mid-array pre-charge scheme, which helps speed up writes, is also due to be presented.

Meanwhile researchers from ITRI and the National Tsing Hua University and the National Central University all in Taiwan are set to present a 4-Mbit embedded SLC resistive RAM with 7.2-ns random-access time and Sony engineers are at the same density with a conductive-bridge resistive memory with 2.3-Gbyte pr second read-throughput and 216-Mbyte per second program-throughput. The 4-Mbit chip, and it has long been a condition of acceptance at ISSCC that the circuit have been made, is implemented in 180-nm CMOS.

Well, Samsung engineers have some guts to present "a paper." After all, Samsung lied that they would have a cell phone with phase-change memory by the end of June 2010 ( http://www.samsung.com/global/business/semiconductor/newsView.do?news_id=1148 ). The "rumor" is that "as of July ... Samsung had yet to deliver engineering samples, largely because phase-change power consumption remains too high for handsets." ( http://spectrum.ieee.org/semiconductors/memory/resistive-ram-gains-ground )
Can't wait for "PCM Scalability:The Myth (Part 3)."
It appears we are getting very close to the final end of the longest-running techno-Ponzi, the phase-change memory.