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Offers : 94

Strategy of crosspoint non-volatile memory integration in cache hierarchy of a multicore architecture

Start date :
1 October 2017

offer n° SL-DRT-17-0689

Non volatile memory presents a real opportunity to improve caches performance in a multicore architecture. The goal of this PhD thesis is to propose an innovative approach to integrate and handle this kind of memory in cache’s hierarchy to improve both performance and energy efficiency of computing multicore circuits.

As the bandwidth to external memory increases slower than computational power of multicore processors, the size of embedded memory caches keeps growing. In present circuits, caches can take up to 75 percent of silicon area. Moreover, the last level cache, which is the bigger, has a low access rate and so has a high static power consumption. We can solve both problems thanks to non volatile memories (NVM) because they have a null static power consumption and provide a higher storage density than SRAM memory usually found in caches. More recently, the emergence of crosspoint NVM promises to deliver even higher storage densities.

This PhD thesis aims at exploring new system-level and microarchitectural-level strategies of crosspoint NVM integration in the cache hierarchy of an existing multicore. This kind of memory has a high write cost which must be taken into account while optimizing performance, power and endurance of the circuit. The student will provide a RTL model of a cache integrating crosspoint NVM in an innovative manner.

So, the student must be knowledgeable in processor architectures, RTL design and verification, and have minimal knowledge in low level software (C, operating system). The work will consist firstly in a bibliography of existing proposals to embed NVM in caches, then a research of specific constraints of crosspoint NVM, a proposal of innovative ideas to answer these problematics, an implementation of these ideas and an evaluation. The thesis will end by the writing of a manuscript and the PhD defense.

Build auto-optimizing libraries for High Performance Computing

Start date :
1 October 2017

offer n° SL-DRT-17-0668

The PhD objective will be to invent a methodology allow to build compute intensive library able to adapt statically to new architectures and dynamically to usage conditions. The context thesis will be between compilation, computer architecture and applied mathematics.

Research activities are mainly based on big numerical simulations. These simulation codes are based on compute intensive libraries which abstract the underlying computing architectures. The increasing complication of the computing architecture make difficult to build efficient libraries.

This topic falls in the context of the development of autonomous vehicles, drones, and robotics.

The environment of the vehicle is described in an occupation grid, each cell of the grid containing the probability of occupation by an object. This grid is updated over time with sensors data.

Higher-level algorithms, like path planning or collision avoidance, think in terms of objects described by their path, speed, and nature. It is thus mandatory to get these objects from individual grid cells, with clustering, classification, and tracking.

Most of the previous publications on this topic comes from the context of vision processing, many of them using deep learning. They show a big computational complexity, and do not benefit from occupation grids specific characteristics (lack of textures, a priori knowledge of areas of interest…). In this PhD, we want to explore new techniques, tailored to occupation grids, and more compatible with embedded and low cost implementation.

The purpose of this thesis is, starting from a fusion-based occupation grid, to get the contained objects, including their position, speed vector, and nature, by using attention-based artificial neuron networks.

Optical brursts integrated switchs

Start date :
1 October 2017

offer n° SL-DRT-17-0866

The increase in the data rate of intra or inter processor transmissions, linked to stringent constraints in terms of latency, seem to lead to the requirement for very high speed (50-100Gbps) point to point optical links integrated into the electronics. However, these links appear to be underused (10-15% of the time only) and due to their simple point to point architecture imply the use of numerous transceivers. In order to reduce the energy consumed by the overall data transmission links it is envisaged to design a multipoint to multipoint optical architecture with packet switching granularity. This innovative architecture shall provide energy savings while meeting the availability and latency requirements of intra-chip data transmission networks. It will be designed and fabricated with silicon photonics technology then tested and demonstrated on both the transmission performance and control planes.

From fault detection to Telecommunications

Start date :
1 October 2017

offer n° SL-DRT-17-0720

The Reliability and Sensor Integration Laboratory (LFIC) has been interested for many years in the detection of broadband (non-perceptible in low frequency) and low signature (in noisy environment) defects for wired networks.

In our detection systems based on the principle of reflectometry, several families of embedded and communicating devices have been manufactured in partnership with industrial players in the field of automotive and aeronautics.

To date, reflectometry systems have limitations related to their sensitivity (10dBm emitted against -10dBm received) while some telecommunication systems can go beyond -90dBm, as for example the DVB-T standard.

The aim of this thesis is to transpose the most relevant telecommunication paradigms (such as multi-band frequency transposition architectures, correction codes, analogue front-end imperfections compensation and equalization techniques) in order to exacerbate defects with low spatial sub-wavelength extension.

The student will have to propose new algorithms and innovative architectures for signal processing in reflectometry or transférométrie.