Striving to Create More Design Efficiency

There are many things to be learned at the upcoming Design and Verification™ Conference (DVCon) in San Jose, CA next month. One item I’d like to touch on is how Accellera is working to help tackle the ever increasing need for more efficiency in the design process. IP providers and SoC integrators are constantly striving to increase design reuse and designer productivity.

In 2014, Accellera working groups advanced industry standards to address challenges with design efficiency including updates to IP-XACT (now IEEE 1685) and Verilog AMS 2.4. IP-XACT provides a formal way to capture IP metadata to enable design automation, integration and reuse of IP. Verilog AMS 2.4 provides additional modeling features that help designers address the challenges in designing and verifying complex mixed-signal integrated circuits. The use of behavioral models enables designers to perform more efficient design trade-offs in the design process, resulting in an improved overall quality of these mixed-signal products.

If you’re looking for ways to create efficiencies in your design process, I encourage you to come to DVCon and learn more about the ongoing standards development at Accellera as well as the products in the industry that can help you. Joining Accellera will also give you a voice in standards development in the areas that are of most interest to you.

I look forward to seeing you at DVCon in San Jose!

Sincerely,

Shishpal Rawat, Accellera Systems Initiative Chair February 2015

Bringing the Design Back to DVCon

by Adam Sherer, Accellera Promotions Committee Chair

The San Jose location of the Design and Verification Conference is just around the corner. Yes, it’s "Design and Verification," not "Design Verification" or "Digital Verification" as some may think. And with projects growing in complexity while rising in abstraction and integrating analog, digital, and software, design is again a challenge for engineering teams.

For that reason, Accellera Day 2015 at DVCon will emphasize design. The morning tutorials will have parallel tracks with SystemVerilog for design and meta-modeling for the overall system. The afternoon will feature parallel tracks on focusing on SystemC for design and exploring the frontier of design. These sessions come together at lunch where we will have a panel discussing the future of efficient design and recognize an individual with Accellera’s annual Technical Excellence award.

Design is certainly a challenge for all of us as we scale up to billion gate designs and scale down to ultra-low power IoT devices. Attend the tutorials to get your engineering ideas flowing! Then join an Accellera community or working group to contribute and you may be the next Technical Excellence Award recipient.

Accellera Day at DVCon

Monday, March 2 8:00am-5:00pm DoubleTree Hotel, San Jose, CA

Accellera invites you to join us for a day filled with information-packed technical tutorials focused on design challenges and the future of efficient design. Meet with experts, colleagues and users to share ideas and get the latest information on what’s developing in the industry.

Accellera in the News

Accellera Forms Portable Stimulus Working Group

Accellera announced last week that it has established the Portable Stimulus Working Group with the charter to develop the electronic industry’s first standard for portable test and stimulus. When completed and adopted, this standard will enable a single specification that will be portable from IP to full system and across multiple target implementations.

SystemC Synthesizable Subset Public Review Now Open

The SystemC Synthesizable Subset Version 1.4 is now open for public review and comment until May 15, 2015. The document can be downloaded here. Feedback is welcome and should be submitted via the public forum.