Single Event Upset has become an increasingly important issue for SRAM-based Field Programmable Gate Arrays. To mitigate these soft errors, most of existing works focused on utilizing logic-level flexibilities to improve circuit reliability. However, we notice that from an application's perspective, there exist higher-level flexibilities. This kind of application-level fault tolerance can be useful from two aspects: one is by directly modifying algorithms (algorithm-based fault tolerance), and the other is by mapping algorithm properties into logic level (algorithm-mapping fault tolerance).
In this thesis, we perform two case studies to analyze the impact of both categories of application-level fault tolerance on circuit reliability, and explore their linkages to the logic-level fault tolerance. With an enhanced algorithm considering algorithm-based fault tolerance, the error rate for the matrix multiplication can be reduced by 18x. Moreover, by mapping algorithm properties into logic level, we achieve 3x improvement in circuit reliability for the discrete convolution.

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