UWB impulse radio signals have a very short duration, extremely wide bandwidth and share the same frequency spectrum with other existing systems. It was determined by the Federal Communications Commission (FCC) that UWB systems could cause interference with other systems, such as Global Positioning System (GPS) for example. Therefore, at present, the FCC has restricted the use of UWB systems to frequencies above 3.1 GHz. In this paper, we evaluated performance of UWB system using proposed pulses that are strictly limited in time to remove interference while, at the same time, contain their power distribution to a frequency band from 3.1 GHz to 10.6 GHz. In particular, we evaluated the BER Performance in relation to system parameters such as pulse duration, δ, the number of users, Nu, and the number of symbols, M. We found the optimal pulse duration δ through computer simulation using developed UWB pulses. It is shown that performance evaluation between the UWB communication system using these UWB pulses and the Gaussian monocycle pulse in M-ary PPM and BPSK schemes. These results can be contributed to construct M-ary PPM UWB communication system in terms of multiuser parameters and pulse duration.

This paper describes the use of an FPGA based prototype to enable the rapid prototyping of IEEE 802.11 modems. Prototyping ASICs on a reconfigurable platform enabled concurrent development by the hardware and software teams, and provided a high degree of confidence in the designs. The capabilities of modern FPGAs and their development tools allowed easy and quick retargetting of the complex ASICs into FPGAs, enabling the integration of the prototyping effort into the design flow from the start of the project. The effect was to accelerate the development cycle and generate an ASIC which had been through one pass of beta testing before tape-out.

This paper presents the design of a 1 GHz continuous-time second order Lowpass Sigma Delta Modulator (LPSDM). The design is intended to meet the future requirements of wideband wireless receivers. The continuous-time Noise Transfer Function (NTF) for the modulator is realized using two Gm-C integrators with negative transconductance feedback and three linearized Gm elements. A three-stage delayed comparator is employed for designing the one bit quantizer, therefore a delayed NTF had to be synthesized. The presented target design is 0.18μm CMOS process. The designed chip uses both 3.3V and 1.8V MOSFETs and consumes 80mW including the clock driver and the output buffer. The performance of the modulator based on post layout simulation is 11 bits for a 5 MHz bandwidth and 8.6 bits for an 11MHz bandwidth.

The performance of low noise amplifiers (LNAs) is limited by the quality factors of the inductors used. Realizing fully integrated LNAs and other radio frequency (RF) circuits requires the development of techniques to improve the quality factors of on-chip inductors. It was found that the maximum attainable tank-Q of on-chip square spiral inductors for a given technology remained fairly constant and independent of the number of turns and the width of the tracks. Based on this on-chip spiral inductors were designed for applications in resonant tank circuits. A 433 MHz Industrial, Scientific and Medical (ISM) band tank circuit was designed based on a single spiral structure with a self-resonant frequency of 433 MHz, resulting in a decrease of 3.6% in the tank-Q compared to a circuit designed for maximum tank-Q. An LNA for a wireless receiver utilising a similar structure for the tuned load has been designed with a gain of 43 dB and a bandwidth of 1.74 MHz occupying an area of 0.48 mm2.

The leakage power consumption in deep sub-100nm CMOS systems is projected to become a significant part of the total power dissipation. Although the dual Vt CMOS process helps reduce the subthreshold leakage current, the gate leakage problem poses a significant design challenge. We introduce gate leakage tolerant circuits. We describe two new circuit techniques to suppress gate leakage currents in dual Vt Domino circuits. In standby mode, proposed circuits generate low inputs and low outputs for all Domino stages to suppress gate leakage currents in the NMOS logic tree. Simulation results using 45nm BSIM4 SPICE models for 32-bit adders show that adders using the two proposed circuits can reduce the standby gate leakage by 66% and 90%, respectively. Proposed adders have 7% active power overhead to achieve the same speed as single Vt domino adder and the area penalty is minimal with careful layout.

The domino circuit failure is due to competing requirements of the keeper and the NMOS logic transistors that cannot be satisfied simultaneously in order to achieve the noise margin and performance objectives. Domino keeper transistor has to be upsized to compensate for the subthreshold leakage and gate leakage currents that discharge the dynamic node in deep sub-100nm technologies. Domino multiplexer can fail when the fan-in number is greater than 14 for the noise margin of 0.1 Vdd, where the noise margin is defined as the input voltage that causes 10% voltage drop at the dynamic node of Domino. In simulation, 45nm BSIM4 models were used with the power supply voltage of 0.8V. To solve this problem, we propose a dual gate oxide thickness (Tox) implementation for high fan-in Domino. With proper dual gate oxide thickness assignment, subthreshold leakage and gate leakage that discharge the dynamic node are suppressed with the keeper size reduced. Proposed circuit not only prevents the possible failure in high fan-in Domino, but also reduces the delay and power consumption due to decreased contention between the keeper and NMOS logic tree. For 14-bit domino multiplexer, proposed circuit is 56% faster with 66% less power consumption and without area penalty, compared to single Tox domino.

A design and analysis of symmetric on-chip planar inductors are
presented based in 0.5 μm silicon-on-sapphire CMOS process of Peregrine Semiconductor. Compared to conventional CMOS processes, an insulating thick sapphire (Al2O3) substrate enables higher quality factor inductors due to low energy loss in the substrate. In addition, symmetric cross-coupled configuration of identical asymmetric inductors of thick top metalization minimizes the insertion loss. Such differentially connected inductors are
simulated on 2.5D electromagnetic field environment and a modeling method of quasi-3D structures is introduced for the metal strips. Maximum quality factor of 53.6 with 2.34 nH at 8.9 GHz is achieved by optimizing the symmetric circular inductors. This inductor is used in the design of a low power (0.42 mW) LC VCO operating at 5.8 GHz and exhibits a phase noise of -120.6 dBc/Hz at 3 MHz offset frequency.

Microstrip patch antenna arrangements offer several well known advantages over other sensors including their low profile (and hence conformal nature), light weight, low-cost in production and compatibility with packaged miniaturised monolithic integrated and optoelectronic integrated circuitry. The major drawback of microstrip patch sensing solutions remains its inherently narrow bandwidth of ~ 2%. Although there has been intensive research to enhance bandwidth based on different strategies e.g., implementing stacked planar parasitic patches and thick substrate configurations and adopting low inductive techniques for feeding microstrip antennas, best approaches for broadening bandwidth for high frequency miniaturised sensor operation (>10 GHz) remain unclear. This paper discusses the development of broadband microstrip sensors for high frequency radiometric sensing operations. It considers the design and fabrication of frequency scanning sensors for Ku (~17 GHz) band operation comprising a microstrip transmission line network of series linked junctions feeding pairs of rectangular patches.

Although electronically scanned antenna arrays can provide effective mm-wave search radar sensors, their high cost and complexity are leading to the consideration of alternative beam-forming arrangements. Rotman lenses offer a compact, rugged, reliable, alternative solution. This paper considers the design of a microstrip based Rotman lens for high-resolution, frequency-controlled scanning applications. Its implementation in microstrip is attractive because this technology is low-cost, conformal, and lightweight. A sensor designed for operation at 77 GHz is presented and an ~80° azimuthal scan over a 30 GHz bandwidth is demonstrated.

A reconfigurable digital filter for a mobile terminal receiver has been analyzed in a simulated dynamic UTRA-TDD environment. By monitoring in-band and out-of-band power ratios, the filter architecture automatically scales its length to meet the signal to noise ratio of the system, This results in optimal battery power efficiency. Analysis reveals a 60 percent power saving for the receiver filter is available for the UTRA-TDD environment. This is compared to a static length filter that meets the 3GPP specifications. The savings in power will extend talk time and stand by time of the mobile terminal.

A critical review of contemporary papers on modulation recognition, signal separation, and Single Station Location (SSL) is described in the context of High-Frequency (HF) radio-communications. High-frequency communications is undergoing resurgence despite advances in long-range satellite communication systems. Defense agencies are using the HF spectrum for backup communications as well as for spectrum surveillance applications. Spectrum management organizations are monitoring the HF spectrum to control and enforce licensing. This type of activity usually requires a system that is able to determine the location of a source of transmissions, separate valid signals from interferers and noise, and characterize signals-of-interest (SOI). The immediate aim is to show that commercial-off-the-shelf (COTS) equipment can be used to locate HF transmission sources, enhance SOIs and reject interference, and recognize signal types. The described work on single-station-location (SSL), signal separation, and modulation recognition is contributing to these goals. This paper describes the overall objectives and some of the disadvantages and benefits of various schemes for single-station-location (SSL), signal separation, and modulation recognition. It also proposes new approaches that may relieve shortcomings of existing methods -- including selection of benchmarks or modulations for various transmission scenarios and propagation modes, and use of multiple digital receivers or compression techniques to improve modulation recognition, signal separation, and location of HF emitters.

Wireless networks are growing rapidly. Their applications include cellular phone, satellite communication and wireless local area networks. In order to avoid interference between all these applications, high selectivity RF filters are essential. The stacked crystal filter (SCF) is a useful configuration when low insertion loss is desired and the near-in skirt selectivity requirement is not as high as that produced by ladder filters. A SCF is an acoustically coupled resonator filter which includes a pair of thickness mode piezoelectric plates attached to each other. Mounted between adjacent sides of the two plates is a shared electrode. The common ways to model the SCF are mason model and lumped element equivalent circuit method. To accommodate complicated geometries, we need to use the other kinds of numerical analysis techniques. Finite element methods have been applied to the modeling of thin film bulk acoustic wave resonator in recent years. Advanced FEM software has the capability to do a coupled piezoelectric-circuit analysis that can connect electrical circuits directly to the piezoelectric finite element models. In this work, we integrate the SCF two-dimensional piezoelectric finite element models and electrical circuits together to simulate the performance of SCF. The influences of electrode property and acoustic loss to the performance of filter are also investigated. The results of simulation are verified by mason model. This methodology can be applied to more complicated geometry models and other types of filters simulation such as coupled resonator filters (CRF) and ladder filters.

In this paper we suggest a new near ideal memory technology to replace existing FLASH and DRAM, the new technology being based on the semiconducting material Silicon Carbide (SiC). The technology will not only be a replacement for FLASH and DRAM but will open up new and novel applications because of its unique capabilities. We provide the reasons why SiC will become the next generation memory material and suggest new structures that will be exploited by a new company QsRAM that will lead the market push for these new memories.

The endurance of a FRAM is 1014 cycles with better retention times (>10 years). FRAM's have fast read/write access, low standby current, scalable and capable of ultra-low voltage operation. FRAM's share architectural features such as addressing schemes and I/O circuitry with other types of random access memories (DRAMs), but they have distinct features with respect to accessing the stored data, sensing, and overall circuit topology. The FRAM is a great advantage for SoC and wireless and mobile products, since it supports non-volatility but also delivers a fast memory access. Today's 1T/1C FRAM have an access time of 30 nS, a cycle time of 35 nS at 1.2 V power supply in a standard CMOS process with 2 mask adders. The cell size of a FRAM is comparable to that of a planar DRAM and is 3 - 4x denser than SRAM. This paper outlines the circuit innovations in embedded ferroelectric memories, and will cover the architecture, reference circuits, sense amplifiers, reliability issues and references to other memory technologies.

This paper describes a 64 x 64 digital pixel array employing a pulse width analogue to digital conversion scheme. Each pixel contains a photodiode sensor, comparator and memory, and in conjuction with a central control circuit performs the analogue to digital conversion, by timing a pulse generated by the photodiode/comparator circuit. The control circuit produces data which compensates for this nonlinear relationship, resulting in a pixel parallel ADC operation. The digital image data can be read from the array non-destructively, with random access. The array is constructed in a standard 0.35 μm, 3.3 V digital CMOS process.

This article introduces newly developed multicomponent oxide host materials for electroluminescent phosphors. These are composed of Y2O3 and another binary compound such as Al2O3, Ga2O3, Gd2O3, In2O3, B2O3 or GeO2. The various Mn-activated (Y2O3)1-x-(oxide)x phosphor thin films were deposited while varying the composition by r.f. magnetron sputtering and postannealed. The obtained electroluminescent and photoluminescent emissions from the [(Y2O3)1-x-(oxide)x]:Mn phosphor thin-film emitting layers were strongly dependent on the preparation and postannealing conditions as well as on the composition. The highest luminance and photoluminescent intensity were obtained by using a (Y2O3)1-x-(oxide)x:Mn thin-film emitting layer prepared with an optimized composition. Both the obtained electroluminescent and photoluminescent characteristics were correlated to the crystallinity of the thin-film emitting layers. High luminances above 7000 cd/m2 were obtained in [(Y2O3)0.6-(GeO2)0.4]:Mn and [(Y2O3)0.5-(Ga2O3)0.5]:Mn thin-film electroluminescent devices fabricated under optimal condition and driven by an ac sinusoidal wave voltage at 1 kHz.

In this paper, a theoretical and experimental study is carried out of crosstalk between neighboring devices within a back-side illuminated two dimensional HgCdTe photovoltaic infrared sensing array. Theoretical calculations are performed utilizing Dhar's model, a 2D simulated current approximation to crosstalk. Experimental results stem from spatial photo-response (SPR) measurements, which have been performed on HgCdTe MWIR photodiode arrays. The characterized devices are part of an 8x8 array fabricated using LPE grown p-type HgCdTe, with photodiodes fabricated in-house at The University of Western Australia. A scanning laser microscope is used to measure the spatial photo-response as a function of temperature. The theoretical model uses finite analysis techniques of probabilistic equations describing photogenerated carrier diffusion within the array. The Dhar model is a two dimensional model of simulated currents generated within the array. The basis of this model is the Kammins Fong (KF) model, a simplistic one dimensional representation of similar simulated currents. Inclusion of diffusion characteristics in the Dhar model is shown to result in greater levels of accuracy.

In this paper, a current-mode VLSI architecture enabling on read-out skin detection without the need for any on-chip memory elements is proposed. An important feature of the proposed architecture is that it removes the need for demosaicing. Color separation is achieved using the strong wavelength dependence of the absorption coefficient in silicon. This wavelength dependence causes a very shallow absorption of blue light and enables red light to penetrate deeply in silicon. A triple-well process, allowing a P-well to be placed inside an N-well, is chosen to fabricate three vertically integrated photodiodes acting as the RGB color detector for each pixel. Pixels of an input RGB image are classified as skin or non-skin pixels using a statistical skin color model, chosen to offer an acceptable trade-off between skin detection performance and implementation complexity. A single processing unit is used to classify all pixels of the input RGB image. This results in reduced mismatch and also in an increased pixel fill-factor. Furthermore, the proposed current-mode architecture is programmable, allowing external control of all classifier parameters to compensate for mismatch and changing lighting conditions.

Heterostructured Hg(1-x)Cd(x)Te photodetectors are important for the next generation of high performance Infra-Red (IR) sensing applications. The measurement of the composition and thickness of each layer in double layer HgCdTe heterostructures is examined in this paper, in particular, the use of infrared transmission and Secondary Ion Mass Spectroscopy techniques. Several authors have published models of the optical absorption coefficient and refractive index in HgCdTe, and these models have been assessed on their suitability for use in modelling the infrared transmission characteristics of multilayer HgCdTe films. No data is available for the refractive index of HgCdTe for photon energies around the bandgap energy, so a modified Sellmeier equation has been used to approximate the refractive index in this range. A versatile
mathematical model of the infrared transmission of multilayer HgCdTe
films is presented, based on the characteristic matrix of each layer.
The model is then fit to experimental data, where the composition and thickness of each of the HgCdTe layers are fitting parameters. While some film parameters may be determined with high accuracy from infrared transmission, Secondary Ion Mass Spectroscopy (SIMS)
is useful as a complimentary technique which enables the measurement of the composition of the wider bandgap HgCdTe layer in double layer HgCdTe films, as well as measurement of the interface abruptness and layer uniformity. A method of calibrating SIMS data is presented, which gives results consistent with those obtained from infrared transmission fitting. Room temperature infrared transmission spectra and SIMS depth profiles of HgCdTe layers grown by Molecular Beam Epitaxy at the University of Western Australia are presented, and are compared with theoretical composition vs. depth profiles which have been determined using elements of each measurement technique.

During the past decade there has been a major change, often described as a paradigm shift, in passive infrared (IR) detection, due to the rapid development of microbolometer IR detectors fabricated by MEMS/MST technology. Microbolometers are now replacing the elegant but costly cryogenically cooled photon detector technology for all but specialised or very high performance applications. Silicon resistance microbolometers were first developed at the Defence Science and Technology Organisation (DSTO), Edinburgh, South Australia, more than two decades ago. In this paper the author introduces a new concept, whereby the microbolometer functions as a transistor. The semiconductor material is silicon or a silicon alloy. The subject matter covers an overview of active bolometer theory, device design and applications. Active operation offers a number of possibilities, including tuning of resistance and activation energy for optimum performance, self-bias correction for fixed pattern noise, and direct addressing. Whilst at an early stage of development, this technology has the potential to significantly impact on the next generation of IR detectors.

The operation of a thin film hot wire directional anemometer is demonstrated using three modes of operation; constant voltage, constant current, constant resistance, and the heating response and characteristics for the different excitation modes observed. Evaluation is primarily by experimental approach. The anemometer fabricated is a four element 2mm x 2mm thermoresistive sensor array mounted on a 1.5 μm silicon nitride membrane formed by bulk reverse etching. Reverse etching is used for thermal isolation of the sensor elements and allows element temperatures in excess of 500°C to be reached with an input power of 250mW and accurate lower temperature operation with element temperatures and heating powers of 65°C and 25mW respectively. Current sources are commonly used for excitation of such devices and resistance feedback often not required due to low resistance variations during operation, however high power modes of operation can lead to instability and self-destruction of positive temperature coefficient of resistance (PTCR) devices. Voltage or resistance feedback provides stable operation due its self-limiting nature in a PTCR device. Resistance monitoring provides a means to achieve stable temperatures of the heating elements and provides reduced sensitivity to fluctuations in ambient air temperatures and a more acceptable response to the incident airflow velocity.

In 1959, the physicist Richard Feynman advised his colleagues that "there's plenty of room at the bottom." He envisioned a discipline devoted to manipulating smaller and smaller units of matter. "I am not afraid," he wrote, "to consider the final question as to whether, ultimately -- in the great future -- we can arrange the atoms the way we want, the way very atoms, all the way down." However, in early 1980's the doom and gloom of silicon MOS transistors was foreshadowed and scaling of the humble MOS transistors beyond 140 nm appeared as the impossible dream. Manipulation of material science, the emergence of low-K material and copper technology together with new techniques in lithography and processing have paved the way for revised predication that has foreshadowed the feature sizes in the order of 20 nm - 30 nm will occur somewhere between 2012 and 2016. Coupled with these developments, nanochemists have began to probe into matter and now Nanochemistry is beginning to shape the future of new materials and better understand the unique properties of assemblies of atoms and molecules on a scale that range between that of individual building blocks and the bulk material, thus confirming Feynman's vision. At this level quantum effects can be significant and innovative ways of carrying out chemical reactions become possible.

As the demand for analog-to-digital (A/D) conversion with greater bandwidths increase, it is necessary to look at other alternatives to electronics for integrated circuit design. One such approach to utilize is a combination of optics and electronics, or opto-electronics, at all levels of the system hierarchy. A device that has these properties is the Self Electro-optic Effect Device (SEED), and combining this with oversampling techniques for data conversion can meet the demands for direct digitization of radio frequency (RF) signals. One form of A/D oversampling conversion method is Sigma-Delta modulation. A key element of this technique is the subtractor and in this paper we will discuss the implementation of a differential subtractor using SEEDs as part of a Sigma-Delta Modulator. This paper will detail simulation results based on experimental data to predict the behavior of two types of differential subtractors, one of which will be compared with experimental results.

A low-voltage low-power CMOS switched-current analog-to-digital converter is presented. The influences of a hysteretic comparator on the performance of the ADC are studied with the help of SPICE simulations. SPICE BSIM4 models are used to study the behavior of the overall circuit. The hysteretic comparator is devised to minimize the errors caused by current spikes at the input to the comparator. The current-mode A/D converter implements a multiply-by-2 scheme. The A/D converter starts converting for the most significant bit (MSB) of an input current. The input is multiplied by two using MOS transistors. The comparator then senses the current imbalance and then determines if the signal 2Iin is greater than Iref. The remaining bits are converted in the same manner. The aim of this study is to use such an ADC in the CMOS imagers to be realized in a low-cost standard digital process technology. Another aim of this study is to utilize a hysteretic comparator to quantize the full-scale range of signals (MSB to LSB) independent of the resolution. The proposed design allows users to easily set the hysteresis width of the comparator for a predetermined resolution without causing any performance degradation.

This paper presents the performance analysis of different high-accuracy sample-and-hold circuit (SHC) techniques using CMOS technology. The paper begins with a detailed analysis of the major factors that limit the accuracy of a fundamental SHC. Then different techniques to implement high-accuracy SHCs are described. SHC employing transmission gate and SHC using feedback loop with compensation capacitor, as well as the fundamental SHC, were all implemented and tested and performance results demonstrate the superiority of each SHC schemes. For comparison reasons, the three SHCs were operated at a speed of 330 MHz. Results indicate that an increase of accuracy of 95% is achieved and the maximum sampling speed is increased by 15% when the SHC using feedback loop is used instead of the fundamental SHC. These characteristics make this device better candidate for many applications where speed and accuracy are the major factors.

In this paper we review two motion detection models based on
insect's visual system. The two motion detection models are the
Horridge template model and the Reichardt correlator model, both have
been implemented in analog VLSI. We briefly review the VLSI
implementation of the two motion detection models and identify the difficulties in designing the required large RC time constants in
VLSI. Possible circuit designs to obtain RC time constants in the order of 10-100 ms are presented.

A control unit has been proposed, which is used to reconfigure a pipeline ADC for a mobile terminal receiver that can drastically reduce the power dissipation dependent on adjacent channel interference. The proposed design automatically scales the word length by monitoring the quantization noise along the in-band and out-of-bands powers in the UTRA-TDD spectrum. The new ADC performance was evaluated in a simulation UTRA-TDD environment because of the large near far problem caused by adjacent channel interference from adjacent mobiles and base stations. Results show that by using the control unit to reconfigure the ADC, up to 88% power dissipation could be saved, when compared to a fixed 16 bits ADC without the use of the control unit. This will prolong talk and standby time in a moble terminal.

Reconfigurable System-on-Chip (rSoC) design is inherently a complex task with enormous freedom in design parameters such as processor, operating system, and backplane buses. Design efficiency can be improved by the use of an rSoC platform which constrains these choices, and allows new designs to leverage much of the expertise of previous designs. Egret is an rSoC prototyping platform being developed at the University of Queensland, Australia, and this paper explains and justifies the design decisions for the first version of Egret.

Through use of a delay impulse function the theory of signal propagation in a lossless medium subject to delay control is detailed. A quasi-static delay modulation approximation is introduced to establish a simple analytical expression for the delay harmonic distortion. Experimental results for a two stage delay cascade provide good experimental justification for the presented theory.

Taking into account the tendency towards higher integration based on sophisticated technologies in microelectronics or the use of specific process steps for the realization of MEMS it becomes evident that the impact of properties and parameters from fabrication processes are getting more and more important. For long the interface between the design domain and the process domain was simply expressed in design rules sets. With the use of high resolution and new IC technology steps the interface gets more complex. As far as MEMS are concerned the technology issues are too dominating for fixed interfaces to the design. Novel approaches are necessary to support future design tasks in the area covered by process development on the one hand and application/structure design on the other hand, considering structural design specifications as well as process flow requirements. This paper describes the development of a process design and management environment that supports process engineers and designers to determine valid process step sequences for specific applications and to derive all characterization data from process flows that are relevant for design stages. This environment (acronym PRINCE) is developed in cooperation with a major European MEMS foundry. It is based on a common data base where all process steps and their characterizations as well as derived rules are stored. Users are able to compose process flows on a graphical editor. Consistency violations such as missing or wrong placed process steps within a complete process flow will automatically be detected. Future work will integrate algorithms to optimize process flows.

The characterization of photodiode junction depth using laser beam induced current (LBIC) has long been ambiguous, due in part to the limited understanding behind the relevant physics governing this phenomena, and more importantly, the signal behavior for the various device geometries. In this work, the induced current behavior arising from the individual junction components that form the device for different geometric conditions is examined in detail. In particular, at low temperatures, the overall LBIC signal dependence to junction depth could be attributed to current crowding through the dominance of two competing current mechanisms which include a lateral current flow, Ilbic, and a transverse current flow, Iph. This study represents another step in the development towards a fully quantitative procedure for extracting junction depth and alternatively interpreting the current contributions arising from the individual junction components using LBIC.

This paper presents the test and validation of FPGA based IP using the concept of remote testing. It demonstrates how a virtual tester environment based on a powerful, networked Integrated Circuit testing facility, aimed to complement the emerging Australian microelectronics based research and development, can be employed to perform the tasks beyond the standard IC test. IC testing in production consists in verifying the tested products and eliminating defective parts. Defects could have a number of different causes, including process defects, process migration and IP design and implementation errors. One of the challenges in semiconductor testing is that while current fault models are used to represent likely faults (stuck-at, delay, etc.) in a global context, they do not account for all possible defects. Research in this field keeps growing but the high cost of ATE is preventing a large community from accessing test and verification equipment to validate innovative IP designs. For these reasons a world class networked IC teletest facility has been established in Australia under the support of the Commonwealth government. The facility is based on a state-of-the-art semiconductor tester operating as a virtual centre spanning Australia and accessible internationally. Through a novel approach the teletest network provides virtual access to the tester on which the DUT has previously been placed. The tester software is then accessible as if the designer is sitting next to the tester. This paper presents the approach used to test and validate FPGA based IPs using this remote test approach.

Residual stresses can significantly affect the performances of silicon micro-structures. The understanding of the residual stress growth during their processing is of great importance. However, the experimental tracing of the stress at the various stages of the machining is still almost impossible. Quantitative modelling of these problems is the alternative to provide guidelines for the minimization of the residual stresses. In this paper, we describe a technology computer aided design homemade tool, IMPACT. The mechanical models and the numerical implementation are presented. We give details about our methodology to calibrate and validate our implementation. The originality of this study lies in (1) the capability to simulate almost all the sources of stress taking into account of the complex rheological behaviors of the materials, (2) the experimental determination of the mechanical properties of various thin film materials and (3) the validation of the calculations by direct comparisons with measured deformations in the micro-structures.

Triaxial accelerometers have been used to measure human movement parameters in swimming. Interpretation of data is difficult due to interference sources including interaction of external bodies. In this investigation the authors developed a model to simulate the physical movement of the lower back. Theoretical accelerometery outputs were derived thus giving an ideal, or noiseless dataset.
An experimental data collection apparatus was developed by adapting a system to the aquatic environment for investigation of swimming. Model data was compared against recorded data and showed strong correlation. Comparison of recorded and modeled data can be used to identify changes in body movement, this is especially useful when cyclic patterns are present in the activity. Strong correlations between data sets allowed development of signal processing algorithms for swimming stroke analysis using first the pure noiseless data set which were then applied to performance data. Video analysis was also used to validate study results and has shown potential to provide acceptable results.

A modular self-contained modular platform is described, for easy integration with micro sensors and other sensor elements. The platform is designed to be physically robust and suitable for harsh environments. The platform features switch able power modes, signal processing capabilities and extensive I/O for sensor and external device communications, data download and transmission. The modular design allows flexible implementation of required functionality depending on the particular application and also provides flexibility for packaging solutions. Two practical applications of the platform are presented to demonstrate its use. Firstly a variety of human exercise activities are investigated using accelerometers. Secondly a weather station made up of environmental sensors using off the shelf and prototype sensors is described. Both of these applications differ greatly in their operational requirements. These implementations demonstrate the adaptability of the platform for different applications.

This paper presents the design of a CMOS 64-bit adder using threshold logic gates based on Logical Effort (LE) transistor level
delay estimation. The adder is a hybrid design, consisting of domino
logic and the recently proposed Charge Recycling Threshold Logic
(CRTL). The delay evaluation is based LE modeling of the delay of
the domino and CRTL gates. From the initial estimations, the 8-bit
sparse carry look-ahead/carry-select scheme has a delay of less than
5.5 FO4 (fan-out-of-four inverter delay), which is more than 1 FO4
delay faster than any previously published domino design.

This paper explores the energy-delay space of eight widely referred flip-flops in a 0.13µm CMOS technology. The main goal has been to find the smallest set of flip-flop topologies to be included in a “high performance” flip-flop cell library covering a wide range of power-performance targets. Based on our comparison results, transmission gate-based flip-flops show the best power-performance trade-off with a total delay (clock-to-output + setup time) down to 105ps. For higher performance, the pulse-triggered flip-flops are the fastest (80ps) alternatives suitable to be included in a flip-flop cell library. However, pulse-triggered flip-flops consume significantly larger power (about 2.5x) compared to other fast but fully dynamic flip-flops such as TSPC and dynamic TG-based flip-flops.

A comparison between the performance of conductometric and layered surface acoustic wave (SAW) hydrogen sensors is presented. Both sensor structures employ an R.F. magnetron sputtered tungsten trioxide (WO3) thin film as a selective layer for hydrogen (H2) sensing applications. The conductometric device is based on an alumina substrate, while the layered SAW device structure is fabricated on a 36° Y-cut, X-propagating LiTaO3 substrate with a zinc oxide (ZnO) guiding layer. The sensors were investigated for different operational temperatures and various concentrations of H2 in synthetic air.

The DC performances of a novel InP/InGaAs tunneling emitter bipolar transistor (TEBT) are studied and demonstrated. The studied device can be operated under an extremely wide collector current regime larger than 11 decades in magnitude (10-12 to 10-1A). A current gain of 3 is obtained even operated at an ultra-low collector current of 3.9x10-12A (1.56x10-7 A/cm2). The common-emitter and common-base breakdown voltages of the studied device are higher than 2 and 5V, respectively. Furthermore, a very low collector-emitter offset voltage of 40 mV is found. The temperature-dependent DC characteristics of the TEBT are measured and studied. Consequentially, based on experimental results, the studied device provides the promise for low-power electronics applications.

Vacuum bake-out for out-gassing is a required process in packaging of devices which are designed to operate at cryogenic temperatures. This process may be problematic for HgCdTe devices, even at relatively low temperatures, since the material is sensitive to heat induced changes. The effect of vacuum baking on HgCdTe photodiode characteristics and performance is investigated through I-V and spectral responsivity measurements. The photodiodes were fabricated on LPE grown HgCdTe on lattice matched CdZnTe substrates. The surface was passivated with thermally evaporated CdTe and the p-n junction was formed by plasma induced p-to-n type conversion. The I-V characteristics of the devices were then measured and the devices were baked under vacuum for varying times at 80°C. This simulates the vacuum bakeout required in vacuum packaging of the devices in cryogenic dewars. The results indicate that the vacuum baking process can significantly modify the I-V characteristics of the photodiodes. There is an initial improvement in device characteristics after a 6 hour bake at 80°C, with a five times increase in the zero-bias dynamic resistance. Further baking sees the dynamic resistance decrease slightly. An insight into the mechanisms and parameters that are affected by the vacuum baking process is also gained by studying the I-V characterisics of the fabricated photodiodes before and after baking. It is observed that tunneling dark currents are significantly reduced after baking.

On-chip communication architectures can have a great influence on the speed and area of System-on-Chip designs, and this influence is expected to be even more pronounced on reconfigurable System-on-Chip (rSoC) designs. To date, little research has been conducted on the performance implications of different on-chip communication architectures for rSoC designs. This paper motivates the need for such research and analyses current and proposed interconnect technologies for rSoC design. The paper also describes work in progress on implementation of a simple serial bus and a packet-switched network, as well as a methodology for quantitatively evaluating the performance of these interconnection structures in comparison to conventional buses.

Initially, IP cores in Systems-on-Chip were interconnected through custom interface logic. The more recent use of standard on-chip buses has eased integration and eliminated inefficient glue logic, and hence boosted the production of IP functional cores. However, once an IP block is designed to target a particular on-chip bus standard, retargeting to a different bus is time-consuming and tedious. As new bus standards are introduced and different interconnection methods are proposed, this problem increases. Many solutions have been proposed, however these solutions either limit the IP block performance or are restricted to a particular platform. A new methodology is presented that can automate the connection of an IP block to a wide variety of interface architectures with low overhead through the use a special Interface Adaptor Logic layer.

This paper introduces a computer architecture suitable for embedded real-time applications where low power consumption is a requirement. This is achieved through the use of a hybrid hardware-software system. A system architecture is proposed which allows for modules of a system to be implemented at run-time in either hardware or software. Implementation choices may be made dynamically based on the loading of the host microprocessor, in a multi-tasking environment. An approach to inter-module communication is described, along with how this is affected by dynamic configuration. Some research goals are identified, including investigating the effects on
real-time performance, power consumption and the design process involved in reconfigurable systems.

The effect of 60Co gamma-irradiation on the device characteristics of Al0.35Ga0.65N-GaN heterojunction field effect transistors (HFET) has been investigated using DC and geometrical magnetoresistance measurements. Cumulative gamma-ray doses up to 20 Mrad(Si) are shown to induce drain current degradation, negative threshold voltage shifts and reverse gate leakage current degradation. Analysis of drain magneto-conductance characteristics measured at 80 K indicated an increase in two-dimensional electron gas (2DEG) sheet concentration with accumulated radiation dose. More importantly, the 2DEG mobility-concentration characteristics are noted to remain aproximately constant for total gamma-radiation doses up to 20 Mrad(Si), indicating that the areal density of radiation-induced defects at the heterointerface is likely to be negligible. The threshold voltage shifts are therefore attributable to the introduction of relatively shallow radiation-induced defects in the AlGaN barrier region and/or to defects introduced at the gate-barrier interface. Although the drain conductance characteristics manifested similar degradation trends at 80 and 300 K, the 2DEG parameters obtained at 300 K exhibited significant scatter with increasing dose, possibly a manifestation of device instabilities induced by radiation-induced surface defects in the ungated access region near the edge of the gate. Device failure due to severe gate leakage and loss of gate control over the 2DEG charge, occurred after a total dose of 30 Mrad(Si).

This paper presents a semi-automatic segmentation method which can be used to generate video object plane (VOP) for object based coding scheme and multimedia authoring environment. Semi-automatic segmentation can be considered as a user-assisted segmentation technique. A user can initially mark objects of interest around the object boundaries and then the user-guided and selected objects are continuously separated from the unselected areas through time evolution in the image sequences. The proposed segmentation method consists of two processing steps: partially manual intra-frame segmentation and fully automatic inter-frame segmentation. The intra-frame segmentation incorporates user-assistance to define the meaningful complete visual object of interest to be segmentation and decides precise object boundary. The inter-frame segmentation involves boundary and region tracking to obtain temporal coherence of moving object based on the object boundary information of previous frame. The proposed method shows stable efficient results that could be suitable for many digital video applications such as multimedia contents authoring, content based coding and indexing. Based on these results, we have developed objects based video editing system with several convenient editing functions.

In this paper, we propose the architecture of the MPLS switch supporting Differentiated Services in the MPLS-based network. The traffic conditioner consists of a classifier, a meter, and a marker. The VOQ-PHB module which combines input queue with each PHB queue is implemented to utilize the resources more efficiently, employing the Priority-iSLIP scheduling algorithm to support high-speed switching. The proposed MPLS switch architecture is modeled and synthesized by Very High Speed Integrated Circuits Hardware Description Language (VHDL), verified and then implemented by commercialized CAD tools to justify the validity of the proposed hardware architecture.

Herein we are offering a concept of matrix FE devices construction based on alumina technology opportunities combined with nanocarbon diamondlike materials and classical microdisplay construction. FE matrix cathode contains a massive of spikes with the emitting part in the form of NCT grown with the help of CVD method. The function of centers is fulfilled by ends of nanospikes formed by the metallization of periodical transparent nanoporous passing in substrates from one of anodic alumina (AA) surface. Spikes are grouped in separate plaits forming periodical grid. On the backside of the grid there is a resistive layer made of thin diamondlike nanomaterial and above it there is a conductive layer on each of the spikes. Control grid is formed in the way of monolith with controlling electrode 3D substrate. Dielectrical lugs on the substrate fulfill the function of spacers 1 and with high precision they keep the distance between cathode and grid while assembling microtriode. To provide precise distance between grid and anode as spacers 2 a frame made of AA and of a certain thickness is used. Modeling of triode systems with FE and separate controlling structures made of AA showed high efficiency of such a classical construction.

In many device modeling and simulations, it is commonly assumed that the barrier height and the effective electron mass are constant regardless of the oxide thickness and the interfacial nitrogen concentration for nitrided oxides. In this work, we have examined the dependence of barrier height and effective electron mass on gate oxide thickness and nitrogen concentration at SiOxNy/Si interface. From the measurement of the direct tunneling and Fowler-Nordheim (FN) tunneling currents we have been able to determine both the barrier height and the effective electron mass without assuming a value for either the effective electron mass or the barrier height. It is observed that with the interfacial nitrogen concentration increased, the barrier height decreases, and the effective electron mass increases. On the other hand, it is also observed that the reduction in the gate oxide thickness leads to a decrease of the barrier height but an increase in the effective electron mass. These results are explained using the electronic structures of SiO2 and SiOxNy.

This paper presents a new pseudo-exhaustive testing algorithm that is composed of the path sensitization and sub-circuit partitioning using t-distribution. In the proposed testing algorithm, the paths, for the path sensitization the, between PIs and POs based on the high TMY (test-mainstay) nodes of CUT are sensitized and the boundary nodes, for the partitioned sub-circuits, are defined on the level of significance α on t-distribution respectively. As a consequence, when (1-α) is 0.2368, the most suitable of the performance to operate the singular cover and consistency operation in the path sensitization. And when the α is 0.5217, the most suitable of the performance to partition the sub-circuit in sub-circuit partitioning.

Introduction of digital communication network such as Integrated Services Digital Networks (ISDN) and digital storage media have rapidly developed. Due to a large amount of image data, compression is the key techniques in still image and video using digital signal processing for transmitting and storing. Digital image compression provides solutions for various image applications that represent digital image requiring a large amount of data. In this paper, the proposed DWT (Discrete Wavelet Transform) filter bank is consisted of simple architecture, but it is efficiently designed that a user obtains a wanted compression rate as only input parameter. If it is implemented by FPGA chip, the designed encoder operates in 12 MHz.