On Fri, Oct 23, 2009 at 11:16 AM, Konstantin Lazarev <klazarev at sbcglobal.net
> wrote:
> Hi Myles,
>> Thank you for hint. I found this place too. Apparently it is not correct
> for vx800 platform.
> I tried to modify this output in src/boot/hardwaremain.c to have different
> POST code. And I still have the same sequence "00"->''10"->"80" after
> complete rebuild of the image.
> Ok. It looks that I need more understanding about what is the sequence of
> execution of coreboot.
> Here is the quote from documentation/POSTCODES
> ----------------------------------------
> 0x10 Entry into protected mode
> 0x01 Entry into 'crt0.s' reset code jumps to here
> 0x11 Start copying LinuxBIOS to RAM with decompression if compressed
> 0x12 Copy/decompression finished jumping to RAM
> 0x80 Entry into LinuxBIOS in RAM
>>Post codes are poorly maintained. Because debugging with the serial port is
_so_ much easier, they aren't used much except to get the serial console
working.
Do you see anything on the serial console? There should be a lot of output
before LinuxBIOS is in RAM.
----------------------------------------
>> From this quote I see that boot sequence for vx800 lacks decompression/copy
> stages and goes directly to entry in RAM.
>Yeah. That sounds bogus.
> So my question is:
> What is the sequence of coreboot start-up for 32-bits x86 after entry32.inc
> (post code 0x10). What code is executed next before hardwaremain.
>I would look at
src/cpu/via/car/cache_as_ram.inc
which calls amd64_main() in
src/mainboard/via/epia-m700/cache_as_ram_auto.c
I'm not exactly sure the path it takes, but cache_as_ram.inc is very early.
Hopefully you'll be able to insert some post codes there and see them.
Thanks,
Myles
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