Intel was surprisingly quiet about the remaining details of Haswell at IDF this year. We know the rough CPU architecture details, some info at a high level about the GPU and of course the platform power improvements. There is a lot more however.

The improved graphics performance comes both from an updated architecture and more EUs, but also an optional on-package cache of up to 128MB in size. It's too early to talk about SKUs and DRAM configurations, but 128MB is the upper bound. Expect to see tons of bandwidth available to this cache as well.

On the CPU side you can expect a ~10% increase in performance on average over Ivy Bridge. As always we'll see a range of performance gains, some benchmarks will show less and others will show more.

Rumors from a year ago were that Intel was going to use a large number of cellphone/tablet/etc type ram chips and implement a silicon interconnect (much denser traces than with a PCB) inside the package to create an ultrawide data bus to compensate for the low clockrates of each individual chip.

With Haswell topping out at only 128Mb vs the 512mb-1gb being speculated about at the time it seems likely they've either scrapped the ultrawide bus, or are using a custom ram chip design with a much wider than normal databus instead of a commodity part.Reply

The idea is the same as the eDRAM in the Xbox 360: store the frequently used buffers in the eDRAM to free up bandwidth to main memory while simultaneously giving access to those buffers a massive increase in performance. The performance benefits can be massive depending on how frequently those buffers are accessed and if they can contain the full buffer.

With 128 MB, that's enough for two full 32 bit buffers at 1920 x 1080 resolution.Reply

Being on-package allows the bus to be much wider. If rumors of the silicon interposer are true, there could potentially be a 512 bit (or wider) bus. Also, without wires travelling off the package, latency and power consumption are hugely cut down.Reply