During the AMD Technology Analyst Day, AMD’s CTO Phil Hester rehashed the majority of the K8L
information we discussed on DailyTech several days ago, but disclosed further
details on specifics. Hester was very
specific to refer to these new technologies as simply “new architecture,” and
never using the K8L core name.

Internally, AMD engineers use the codename Greyhound to describe the "new architecture."

A major push for AMD’s K8L design is in “modular” component
design – meaning everything from L3 cache to memory controllers are developed
as individual components and linked together with reusable, robust
designs. To some extent, processor
design is already modular with libraries and designs that are developed
individually. However, Hester insists
this new modular approach takes this modular approach even further, claiming
that the company is developing “better define the interfaces for each of these
building blocks.”

Additionally, Hester revealed some more information about
the cache specifics on K8L. Each K8L
core will have 64KB of dedicated L1 cache, followed by 512KB of dedicated L2
cache. The base models of K8L will have
2MB of shared L3 cache, but Hester also went on to claim that adding more L3
cache was in the company’s roadmap. One thing AMD representatives have not particularly touched on is the cache reduction from 64+64KB (data+instruction) to 32+32KB. AMD employees have assured us this move is logical with the addition of L3 cache.

A major feature of K8L is DICE, or Dynamic Independent Core
Engagement. Essentially, the ACPI layer
will have the ability to dynamically adjust individual cores and crossbars on
the processor. Each processor core will have the ability to
enter its own power-state, or p-state, allowing a K8L processor the ability to
conserve power when the system does not have enough threads to utilize the other
processor cores. Intel’s Core processors
have the ability to enter c-states on a per-core basis, but the AMD
demonstration showed a quad-core K8L processor dip individual cores into full
halt.

Opteron servers right now are, for the most part, limited to
PCs with eight sockets or less. Part of
this is due to the fact that each processor has only three HyperTransport
links. Hester announced that the next
generation Opteron core will have four 16-bit HyperTransport-3 links running at
2.6GHz each. These four links can
reconfigure into eight 8-bit HyperTransport links in a process called “un-ganging,”
which is a fundamental feature of HyperTransport-3. Essentially, one could have an eight-socket
server with thirty-two fully connected cores. Each processor will be able to take advantage of any of the eight memory
banks within one memory hop. The
HyperTransport-3 specification claims un-ganging mode can work on the fly,
meaning that even a fully connected eight-socket server could dynamically
change two 8-bit links into a single 16-bit link during operation to increase
I/O at critical moments.

K8L is designed as a native quad-core design, although slides
from the Technology Analyst Day also revealed that a dual-core desktop SKU will
appear in mid-2007. So far, DailyTech
has touched a little bit on the 65nm quad-core code names announced in AMD roadmaps,
but to our knowledge the code names for dual-core K8L processors have not been
disclosed. Update 07/06/2006: Please read the update to this article about the K8L L1 cache sizes.

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This article is over a month old, voting and posting comments is disabled

quote:The changes from K7 to K8 were bigger. IMC, AMD64, HTT to name a few.

Bigger yes, but IPC was just not there. Hopefully the K8L will solve this with lower latency in it's L2 cache and a smarter, more accurate prefetch. I have no idea what they did to the core itself yet as it's not as easy to assume and squeeze information about the registry units.

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