Typical Clock Generation Scenario：The oscillator is external to the chip and produces a low frequency (10-50 MHz typical) clock which is used as a reference clock by the on-chip PLL to generate a high-frequency low-jitter clock (200-800 MHz typical). This PLL clock is then fed to a clock divider log...

Hi Vikram, May be you know as sequential depth is related to capture ( Launc on capture if atspeed), when we want to capture value related to input of non-scannable flop we need extra clock pulse so by increasing seuential depth as 2 you can capture response of that non-scan flop via scanable flop h...

You are right IDDQ fault testing is for faults which are not detected by stuckat fault type. It is like top-up patterns. Also, Bridging faults and punch trough faults can be detected by these patterns.So, we use IDDQ patterns for additional fault coverage.

Hi Vikaram, Test Procedure file will be mostly same for EDT(Decompressor-Compression) Insertion and for ATPG (Pattern generation) except for additional EDT constraints. For example : EDT_UPDATE,EDT_CLOCK and other EDT related constraints. Dofile will also have additional constraints with compression...

IDDQ testing is based on the principle that complimentary CMOS does not draw any current from the power supply when it's inputs are static (i.e. not switching). In reality, however, there exists a small leakage current which typically is orders of magnitude smaller than the switching current. By thi...