Now back to the original question, I have to construct an SR flip-flop using D flip-flops and other logic gates. How do I work my way towards the solution?

I thought I had decent understanding of how SR and D flip-flops work but I don't know how to work my way towards a solution in a situation like this.

Thinking about the differences between and SR FF and D FF:

- An SR FF doesn't depend on any sort of clock, so somehow using D flip-flops and logic, I have to "eliminate" the clock in such a way that when values for S and R are applied, the clock will have a positive edge.

- An SR FF (If we think about the SR NOR FF) is invalid for S = R = 1, so somehow I have to incorporate an "invalid state" using D flip-flops.

- An SR FF will hold its state when S = R = 0, while the D flip flop will hold its state while the clock is low (or on a negative edge). If I can guarentee that the when S = R = 0 that the clock is low(or on a negative edge) I should be able to manage the case S = R = 0.

I can't get any solid progress down on actually designing this thing. Am I attacking the problem in the wrong way? What should I be thinking about and what should I be asking myself?

- An SR FF (If we think about the SR NOR FF) is invalid for S = R = 1, so somehow I have to incorporate an "invalid state" using D flip-flops.

Rethink this portion first of all. Your instructions mentioned using 'other' logic gates as well to implement the S-R type of operation. How could you use AND and OR gates to set up a S=1 and R=1 exception?

- An SR FF (If we think about the SR NOR FF) is invalid for S = R = 1, so somehow I have to incorporate an "invalid state" using D flip-flops.

Rethink this portion first of all. Your instructions mentioned using 'other' logic gates as well to implement the S-R type of operation. How could you use AND and OR gates to set up a S=1 and R=1 exception?

Click to expand...

Well if I ran S and R into a NAND gate, the output would be 1 expect for the case when S=R=1, then the output would be 0.

So the output of this NAND gate tell's us whether or not the SR input is valid. (i.e. it will output a 1 if the SR input is valid)

This is another assignment in which I don't find any point in it. The D-FF is an evolution of the SR-FF. What is the point in using the D-FF to construct its predececor? Unspeakable words come to my mind.

First let's admit that you do want your circuit to operate with a clock. After all, you want to build an SR-FF, not an SR-latch. Note that wikipedia has a latch picture on the FF section. Look here, I think it's more illuminating. http://www.electronics-tutorials.ws/sequential/seq_1.html. It describes the NOR SR-FF, but basically you just invert the input, nothing too hard.

You want a logic circuit that will have as inputs S, R and Q (the output of the FF) and as an output the D (input of the FF). You want it to:

Output D=0 when S=0 and R=1; (Q=both 1 and 0).

D=1 when S=1 and R=0; (Q=both 1 and 0).

D=Q when S=R=0.

Since the inuts S=R=1 are invalid, I don't think anyone should ask for a specific behaviour in this case. So set D=X for S=R=1 and Q=both 1 and 0.

Make a Karnaugh table with 3 inputs S,R,Q and its ouput will be D. Seems pretty straightforward to me.
The clock will be drived the the D-FF clock.

This is another assignment in which I don't find any point in it. The D-FF is an evolution of the SR-FF. What is the point in using the D-FF to construct its predececor? Unspeakable words come to my mind.

First let's admit that you do want your circuit to operate with a clock. After all, you want to build an SR-FF, not an SR-latch. Note that wikipedia has a latch picture on the FF section. Look here, I think it's more illuminating. http://www.electronics-tutorials.ws/sequential/seq_1.html. It describes the NOR SR-FF, but basically you just invert the input, nothing too hard.

You want a logic circuit that will have as inputs S, R and Q (the output of the FF) and as an output the D (input of the FF). You want it to:

Output D=0 when S=0 and R=1; (Q=both 1 and 0).

D=1 when S=1 and R=0; (Q=both 1 and 0).

D=Q when S=R=0.

Since the inuts S=R=1 are invalid, I don't think anyone should ask for a specific behaviour in this case. So set D=X for S=R=1 and Q=both 1 and 0.

Make a Karnaugh table with 3 inputs S,R,Q and its ouput will be D. Seems pretty straightforward to me.
The clock will be drived the the D-FF clock.

Click to expand...

Thank you very much Georacer. What you stated worked perfectly.

Understanding what my inputs are and what my outputs are was a big help.

From here I could make myself a truth table as you mentioned. From the truth table I was able to generate minterms, and from there I could use a karnuagh map to simplify.

This is the "procedure" that I couldn't find anywhere. Atleast now for next I have a rough idea of what I should try and what I should be doing.

If I were to be your professor, I would be a professional.
If I ware a professional, I would be paid for my hobby.
If I were being paid for my hobby, it would be work by then and propably a boring one to keep it up...