Within EDE cstart.asm can be automatically added to your project. Select the "EDE | Configure Selected CPU" menu item and open the "Cstart" tab. Select the "Automatically add cstart.asm to your project" option.
The "Build Options" dialog has an extra edit field "Output directory". All files that are generated during a build will appear here, instead of in the project directory.

The type modifiers _sfrbit16 and _sfrbit32 control the access of
(SFR) bit fields. Bit fields qualified with the type modifiers _srfbit16 are only accessed as word or halfword. Bit fields qualified with the type modifiers _srfbit32 are only accessed as word.
To support SFR bit field access, SFR data structures are defined containing SFR bit field members. For example the ctri/include/regCPU_name.sfr files contain SFR structure definitions that contain SFR bit field members.

With the _far function storage qualifier you can qualify a function to be called indirectly instead of PC relative or absolute. The _far function storage qualifier only affects non C function pointer calls; C function pointer calls always use the indirect call operation of the TriCore.
Use the -indirect option to enable code generation for indirect function calling.

Trap Function Qualifiers

With the _trap and _trap_fast function qualifier you can declare a
function to serve as a trap service routine. Trap functions cannot return
anything and must have a void argument type list, except for class 6 SYS trap handlers.

Enable Interrupt/Trap Function Qualifier

The _enable_ function qualifier let you declare an interrupt or trap service routine and enables the interrupts immediately at function entry.

Bisr Interrupt/Trap Function Qualifier

By means of the _bisr_ interrupt/trap function qualifier you can set the current CPU priority number (ICR.CCPN) to a value in the range from 0 to 511 and enable the interrupts for an interrupt or trap service routine.

With the _imaskldmst() intrinsic function you can perform atomic Load-Modify-Store of a bit-field from an integer value with the IMASK
and LDMST instruction.
The intrinsic macro _putbit() enables you to store a single bit atomically in memory at a specified bit offset.
The intrinsic macro _getbit() provides the reverse functionality. You can load a single bit from memory at a specified bit offset.

Infineon Technologies regularly publishes micro controller errata sheets reporting functional problems and deviations from the electrical and timing specifications. The TASKING TriCore Software Development tools provide workaround support for a number of these functional problems in the TriCore architecture.
This release has been extended to support a bypass for CPU functional problem TC113_CPU16.
The workaround for CPU functional problem TC113_CPU9 has been updated; The C compiler now generates two NOPs after a DSYNC instruction instead of one.
See appendix C of the C Cross-Compiler User's Guide for details on CPU functional problem bypasses.

To minimize space consumed by alignment padding with unions and structures, elements follow the minimum alignment requirements imposed
by the architecture. The TriCore architecture supports access to 32-bit integer variables on halfword boundaries.
By applying '#pragma pack 2' a structure or union type is qualified for halfword packing. The structure or union to be packed cannot have members that require an alignment larger than 2 bytes.
The halfword packing for structures and unions can be turned off by applying '#pragma pack 0'.

Pragma section code_init

With the '#pragma section code_init', the code section is copied from ROM to RAM when the program is started. The advantage is that code from RAM can be executed much faster.

Pragma section data_overlay

The '#pragma section data_overlay' allows the noclear and farnoclear section to be overlayed with other sections with the same name.

The tools now support the option -C<cpu>, which causes an
SFR-definition file to be included automatically before the source
file. The tools which support this feature are the C compiler (ctri), assembler (astri), debugger (xfwtri), C++ compiler (cptri) and control program (cctri). This option will cause ctri and cptri to include the file regCPU_name.sfr (so ctri no longer uses regCPU_name.h files). Astri and xfwtri will include the file regCPU_name.def. Cctri just passes this option to those tools that support it.
The old option "-C " for astri to include an SFR-register file has become obsolete, but it is still supported for compatibility reasons. A generic include option "-H" has been added to astri, which supports the inclusion of any include file before the source to be assembled.
For all supported CPU types regCPU_name.sfr and
regCPU_name.def files are provided in the ctri/include
directory. For user defined CPU types the user may define his own files. In
the EDE the basename for these user-defined SFR-files can be set on the CPU
tab in the TriCore Project Configuration dialog. If this field is set for a
user-defined CPU type, both the .sfr and the .def file must be present. The old provisions in the EDE to include SFR-files into assembly files have been replaced by this new mechanism.
Since xfwtri now reads the assembly .def files for register definitions, the use of the register manager (rmtri) has become obsolete. Therefore, rmtri has been removed from the toolchain.
The currently supported derivatives are: TC10GP, TC11IB, TC1765, TC1775, TC1920, PXB4225, PXB4260 and Raptor.

By using the -WAE option warning messages are treated as errors. This also affects the return value of the application when only warnings occur. A build process will now stop when warnings occur. This feature is handy in those cases where no warnings are tolerated (for QA/QC purposes).
The option is available for the compiler, assembler, linker and locator.

Enable MMU Instructions

The -MMU option allows the use of memory management instructions in the assembly source.
The assembler used to generate MMU instructions by default, but in some derivatives the MMU-unit is not present.

HW_Only Option

Normally the assembler may replace instructions by other, smaller or faster instructions. For example, the instruction jeq d0,#0,label1 is replaced by jz d0,label1.
With the option -hw_only you instruct the assembler to encode all instruction as they are. The assembler does not substitute instructions with other, faster or smaller instructions.

In this version a start is made with supporting the TriCore 2. At this
moment the assembler supports the TriCore 2 chip; the option '-Ctc2' needs to be
specified. Other parts of the toolchain are prepared, such as the
disassembler in CrossView Pro.
The standard library path for TriCore has been changed from tooldir/lib into tooldir/lib/tc1, analogous to this there will be a tooldir/lib/tc2 directory containing the TriCore 2 libraries.
In a consecutive release the C compiler will support the TriCore 2 features
as well and a TriCore 2 simulator will be included.

The GUI of CrossView has been improved, resulting in a more intuitive and user-friendly interface.
Furthermore, the breakpoint interface has been redesigned and functionality was added. Besides setting up code- and data-breakpoints, you now can set up breakpoints on instruction counts, cycle counts and timer counts as well.
Also Probe Points were introduced, with this mechanism you can interrupt the execution of the program to perform a user-specified action.
When a breakpoint is hit, CrossView Pro will generate an ISYNC and a DSYNC instruction, to make sure that Memory windows and Register windows are synchronized.
CrossView Pro for the TriCore now supports I/O Simulation for all types of I/O support which were formerly known as FSS, VIO and SIO. I/O simulation consists of File I/O (FIO), File System Simulation (FSS) and Debug Instrument I/O (DIO).
Finally, the TriCore CrossView Pro debugger has been enhanced with generic kernel aware debugging for OSEK ORTI compliant real-time operating systems. With the information stored in your application's ORTI file, the OSEK kernel aware debugging module is able to offer dedicated kernel awareness.