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User View: A 20nm Custom IC Constraint-Driven Flow

If the semiconductor industry is going to ramp up for 20nm design, a custom IC flow that can handle this process node is essential. This flow will require more automation than previous nodes. In a recorded audio presentation at the Cadence web site Francois Lemery, member of the Technology R&D group at STMicroelectronics, shows how his company is working with Cadence to develop a 20nm constraint-driven flow based on Modgens (Module Generators).

Lemery gave one of 30-plus customer and partner presentations at the EDA360 Theater in the Cadence booth at the Design Automation Conference (DAC 2012). These hands-on, interactive, 10-30 minute presentations covered a variety of IC and system design topics. Audio recordings and slides from most of the presentations are located here, and a previous blog post lists the titles of available presentations.

In the presentation, Lemery cited two objectives for a 20nm custom design flow. One objective is to predict layout-dependent effects (LDE) as early as possible in the design cycle. This requires an ability for schematic designers to easily generate a floorplan. The second objective is to have an automatic "redo" capability to accommodate design kit changes and SPICE model changes. "To accommodate these changes we need to use parameterized cells, because they are regenerated each time there is something new."

To meet these two objectives, STMicroelectronics and Cadence set up a constraint-driven flow flow based on the Modgens provided by the Cadence Virtuoso platform. As Lemery explained, Modgens let designers group PCells (parameterized cells) together and find the relationship between the PCells. They also let designers define the distance between PCells, the abutment, and the alignment, making it easy to regenerate structures when design kits change. "It is much easier for a person or a tool to manipulate groups of devices rather than just individual ones," Lemery said.

The most accurate way to compute LDE parameters is to create a fully extracted layout view. Unfortunately, this requires an LVS (layout-versus-schematic) clean layout, which can take an entire day for a block. "So we propose to break that loop and do the extraction of the LDEs from a partial layout or from a floorplan where the designer has just placed the devices," he said. "However, we must establish the correspondence between instances in the layout and instances in the schematic."

The rest of the 20-minute presentation goes into considerable detail showing how this flow is accomplished. Lemery explained how his team uses a customized version of the Virtuoso Circuit Prospector tool to find topologies in the circuit and generate the associated constraints. Designers can also select devices in the schematic and call up the generator they need. STMicroelectronics has developed its own tool for layout generation, allowing designers to select instances in a hierarchical schematic and generate a flat Modgen layout.

The work goes on. Lemery noted that there are still more 20nm rules to support, new structures that could be added to generators, and new constraints to manage. But it certainly sounds like there's been considerable progress, and that STMicroelectronics and Cadence are blazing a path that many others will follow. You can view the audio recording and presentation slides here.