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4 Mbit DRAM: square root of bits per RAS/CAS DRAM Logical Organization Refreshing prevent access to the DRAM (typically 1- 5% of the time) Reading one byte refreshes the entire row Read is destructive and thus data need to be re- written after reading – Cycle time is significantly larger than access time

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Virtual Addressing Page faults are costly and take millions of cycles to process (disks are slow) Optimization Strategies: –Pages should be large enough to amortize the access time –Fully associative placement of pages reduces page fault rate –Software-based so can use clever page placement –Write-through can make writing very time consuming (use copy back)

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Hardware supported Page Table Page table: –Resides in main memory –One entry per virtual page –No tag is requires since it covers all virtual pages –Point directly to physical page –Table can be very large –Operating sys. may maintain one page table per process –A dirty bit is used to track modified pages for copy back

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Page Faults A page fault happens when the valid bit of a virtual page is off A page fault generates an exception to be handled by the operating system to bring the page to main memory from a disk The operating system creates space for all pages on disk and keeps track of the location of pages in main memory and disk Page location on disk can be stored in page table or in an auxiliary structure LRU page replacement strategy is the most common Simplest LRU implementation uses a reference bit per page and periodically reset reference bits

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With a 32-bit virtual address, 4-KB pages, and 4 bytes per page table entry: Optimizing Page Table Size Optimization techniques: –Keep bound registers to limit the size of page table for given process in order to avoid empty slots –Store only physical pages and apply hashing function of the virtual address (inverted page table) –Use multi-level page table to limit size of the table residing in main memory –Allow paging of the page table –Cache the most used pages  Translation Look-aside Buffer

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Avoiding Address Translation Send virtual address to cache? –Called Virtually Addressed Cache or just Virtual Cache vs. Physical Cache –Every time process is switched logically must flush the cache; otherwise get false hits Cost is time to flush + “compulsory” misses from empty cache –Dealing with aliases (sometimes called synonyms) Two different virtual addresses map to same physical address causing unnecessary read misses or even RAW –I/O must interact with cache, so need virtual address

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Solutions Solution to aliases –HW guarantees that every cache block has unique physical address (simply check all cache entries) –SW guarantee: lower n bits must have same address so that it overlaps with index; as long as covers index field & direct mapped, they must be unique; called page coloring Solution to cache flush –Add process identifier tag that identifies process as well as address within process: cannot get a hit if wrong process

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Indexing via Physical Addresses If index is physical part of address, can start tag access in parallel with translation To get the best of the physical and virtual caches, use the page offset (not affected by the address translation) to index the cache The drawback is that direct-mapped caches cannot be bigger than the page size (typically 4-KB) To support bigger caches and use same technique: –Use higher associativity since the tag size gets smaller –OS implements page coloring since it will fix a few least significant bits in the address (move part of the index to the tag)

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Possible exceptions: Cache miss: referenced block not in cache and needs to be fetched from main memory TLB miss: referenced page of virtual address needs to be checked in the page table Page fault: referenced page is not in main memory and needs to be copied from disk Memory Related Exceptions

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Memory Protection Want to prevent a process from corrupting memory space of other processes –Privileged and non-privileged execution Implementation can map independent virtual pages to separate physical pages Write protection bits in the page table for authentication Sharing pages through mapping virtual pages of different processes to same physical pages

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Memory Protection To enable the operating system to implement protection, the hardware must provide at least the following capabilities: –Support at least two mode of operations, one of them is a user mode –Provide a portion of CPU state that a user process can read but not write, e.g. page pointer and TLB –Enable change of operation modes through special instructions