IBM announces ASIC timing flow, Cisco chips

SAN DIEGO  IBM Corp. introduced a "variation-aware" IC timing flow targeted at ASICs in 130-, 90- and 65-nm design nodes at the Design Automation Conference here Wednesday (July 9). The flow maximizes performance and minimizes power consumption and is expected to reduce custom chip design turnaround time by as much as a factor of four.

IBM also announced a custom chip deal with Cisco Systems.

Variation-aware timing enables chip designers to account for variables in custom chip design by closely analyzing the time it takes signals to pass between circuits. Designers are then able to correct errors that might previously have gone undetected.

IBM's flow is able to account for process and environmental variations in real time and engineer the chip accordingly throughout the design flow, from development through the manufacturing process, according to Richard Busch, director of the ASIC business unit within the IBM Systems and Technology Group.

Variation-aware timing is available now as part of the IBM Cu-11 (130 nm) and Cu-08 (90 nm) ASIC design kits.

The most sophisticated IC is the silicon packet processor, operating at 40Gbits/s. The chip has 38 million gates, more than 185 million transistors and 188 high-performance programmable 32-bit RISC processors executing 47 billion instructions per second.

The 18.3-millimeter chip, along with nine additional ASICs designed by Cisco and built by IBM, is the result of a strategic multi-year chip technology development effort between the partners. During the past three years, IBM and Cisco engineers worked closely to develop the 10 new custom chips, which are being produced in IBM's 300-mm fab in East Fishkill, N.Y., and at the 200-mm facility in Burlington, Vt.

"By coupling Cisco's expertise in networking and chip design with IBM's expertise in deep sub-micron silicon manufacturing and packaging, we have delivered the world's most sophisticated 40 gigabit per second network processor," said Dan Lenoski, Cisco's vice president of engineering.