3 Central Idea of a Memory Hierarchy3Central Idea of a Memory HierarchyProvide memories of various speed and size at different points in the system.Use a memory management scheme which will move data between levels.Those items most often used should be stored in faster levels.Those items seldom used should be stored in lower levels.

4 4TerminologyCache: a small, fast “buffer” that lies between the CPU and the Main Memory which holds the most recently accessed data.Virtual Memory: Program and data are assigned addresses independent of the amount of physical main memory storage actually available and the location from which the program will actually be executed.Hit ratio: Probability that next memory access is found in the cache.Miss rate: (1.0 – Hit rate)

13 Set Associative Mapping13Set Associative MappingIntermediate compromise solution between Fully Associative and Direct MappingNot as expensive and complex as a fully associative approach.Not as much contention as in a direct mapping approach.

14 Set Associative Mapping14Set Associative MappingCostDegree AssociativityMiss RateDelta$1-way6.6%$$2-way5.4%1.2$$$$4-way4.9%.5$$$$$$$$8-way4.8%.1Performs close to theoretical optimum of a fully associative approach – notice it tops off.Cost is only slightly more than a direct mapped approach.Thus, Set-Associative cache offers best compromise between speed and performance.

15 Cache Replacement Algorithms15Cache Replacement AlgorithmsReplacement algorithm determines which block in cache is removed to make room.2 main policies used todayLeast Recently Used (LRU)The block replaced is the one unused for the longest time.RandomThe block replaced is completely random – a counter-intuitive approach.

16 16LRU vs RandomBelow is a sample table comparing miss rates for both LRU and Random.CacheSizeMiss Rate:LRURandom16KB4.4%5.0%64KB1.4%1.5%256KB1.1%As the cache size increases there are more blocks to choose from, therefore the choice is less critical  probability of replacing the block that’s needed next is relatively low.

18 18OptimalReplace the page which will not be used for the longest (future) period of time.Faults are shown in boxes; hits are not shown.7 page faults occur

19 19OptimalA theoretically “best” page replacement algorithm for a given fixed size of VM.Produces the lowest possible page fault rate.Impossible to implement since it requires future knowledge of reference string.Just used to gauge the performance of real algorithms against best theoretical.

20 FIFO 20 Faults are shown in boxes; hits are not shown.When a page fault occurs, replace the one that was brought in first.Faults are shown in boxes; hits are not shown.9 page faults occur

21 FIFO Simplest page replacement algorithm.21FIFOSimplest page replacement algorithm.Problem: can exhibit inconsistent behavior known as Belady’s anomaly.Number of faults can increase if job is given more physical memoryi.e., not predictable

22 Example of FIFO Inconsistency22Example of FIFO InconsistencySame reference string as before only with 4 frames instead of 3.Faults are shown in boxes; hits are not shown.10 page faults occur

23 23LRUReplace the page which has not been used for the longest period of time.Faults are shown in boxes; hits only rearrange stack1255122519 page faults occur

24 LRU More expensive to implement than FIFO, but it is more consistent.24LRUMore expensive to implement than FIFO, but it is more consistent.Does not exhibit Belady’s anomalyMore overhead needed since stack must be updated on each access.

25 Example of LRU Consistency25Example of LRU ConsistencySame reference string as before only with 4 frames instead of 3.Faults are shown in boxes; hits only rearrange stack121254151234251234447 page faults occur