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Technical Info
Chrome project was developed starting from Speccybob design (Thanks Mike) but while speccybob was made only with TTL chips, Chrome features 2 CPLD from Xilinx that emulates not only 48K spectrum but a more powerful 128K, 7 MHz Z80 clock and floppy disk interface. This means also a very small number of chips and a compact board too.
Every logic devices are fully reprogrammable on board enabling changes to original design in real time.

I recently reworked the entire cpld's design to match the best timing compatibility with the original 128K, some demos still runs not perfectly, but if speccybob was 99% compatible, I reached 99,9% ;)

Memory Map
Chrome memory map is similar to original 128K Speccy, but add to this other two 16K pages of ram and two of rom. Memory paging is controlled by port 7FFDh and 1FFDh, you can read these ports. Notice that only Bank 2 and 5 are contended with video CPLD.

Port 7FFDh (read/write)

Bit 0-2 RAM page (0-7) to map into memory at C000h
Bit 3 Select normal (0) or shadow (1) screen to be displayed. The normal screen is in bank 5, whilst the shadow screen is in bank 7. Note that this does not affect the memory between 0x4000 and 0x7fff, which is always bank 5.
Bit 4 Low bit of ROM selection.
Bit 5 If set, memory paging will be disabled and further output to this port will be ignored until the computer is reset.
Bit 6-7 not used

If you need further information about Ay registers and usage, please look at the datasheet in Download section.

Floppy Interface
The floppy disk interface is compatible with +D, originally made by Miles Gordon Technology in the late 1980s.
It controls two floppy drive double density with 800K capacity. Other +D features are a parallel printer interface and a shapshot button to transfer games snap to floppy or to make screen hardcopy.
+D contains its own memory (8K ram + 8K rom) that are paged in when the CPU fetchs an instruction at addresses 08h,66h,028Eh.
Further information on Ramsoft site