USB

USB3.0 PCIe3 SATA3 Combo PHY IP

Description

The MiPHYA c4.0 macrocell is extracted from production chips, it implements the lower (physical) layer protocols of the following standards:

USB 3.0 SuperSpeed

PCI-e 3.0

SATA gen1/2/3

Data transmission and reception are provided over a dual differential pair CABLE. The TX (transmit) and RX (receive) serial channels operate plesiochronously (NRZ). The macro-cell can be used in Host or Device applications.

USB 2.0 Super Speed host Controller IP

Description

USB 2.0 Host controller is a highly configurable core and implements the USB 2.0 Host functionality that can be interfaced with third party USB 2.0 PHY’s. USB2.0 Host controller core is part of USB3.0 family of cores.

Host Controller core is architected with an high performance DMA engine based on xHCI specification. The core can be configured to support full-fledged USB 2.0 host controller based higher performance xHCI specification for use in standard PCIe-USB bus adaptors/chip sets or be configured with a subset of features for embedded applications requiring limited host functionality.

The controller has a very simple application interface which can be easily adapted to standard on-chip-bus interfaces such as AXI,AHB, OCP as well as other standard off-chip interconnects making it easy to be integrated in a wide range of applications.

USB 2.0 Audio Design Platform IP

Description

The USB 2.0 Audio Design platform is a complete ,integrated solution,designed to be used in USB based Audio Devices such as speaker and microphones. You can use it in various applications,like portable flash memories, digital audio players, card readers and digital cameras.

This includes :

DUSB2 peripheral controller designed to support 12 Mb/S full speed and 480 Mb/S high speed serial data transmission rates.

USB 3.0 Host controller IP

Description

The USB 3.0 Host controller is a highly configurable core and implements the USB 3.0 Host functionality that can be interfaced with third party USB 3.0 PHY's. The Host Controller core is architected with an optional high performance DMA engine based on xHCI specification. The core can be configured to support full fledged xHCI implementations for use in standard PCIe-USB bus adaptors/chip sets or be configured with a subset of features for embedded applications requiring limited host functionality.
The Host Controller core is carefully partitioned to support standard power management schemes which include extensive clock gating and multiple power wells for aggressive power savings required for mobile and handheld applications. The controller has a very simple application interface which can be easily adapted to standard on-chip-bus interfaces such as AXI, AHB, OCP as well as other standard off-chip interconnects making it easy to be integrated in a wide range of applications.
The controller's simple, configurable and modular architecture is independent of application logic, PHY designs, implementation tools and most importantly, the target technology.

Features

Compliant with xHCI Rev1.0

Compliant with USB3.0 Specification Rev1.0

Implements Phy Logical/ Link / Protocol Layers.

Asynchronous clocking between Host Controller and Application logic

Supports Aggressive Low Power Management

Configurable core frequency: 125, 250, 500 Mhz.

Configurable PIPE Interface: 8, 16, 32 bit.

Flexible User Application Logic

Can be adapted by any SoC / OCB interface / offchip interconnects – such as AHB, AXI, PCIe

Configurable Datawidth: 32, 64, 128 bit.

Simple Register Interface for internal Register Access.

Support for various Hardware and Software Configurability regarding Core characteristics.