The combination of 16nm technology and Cadence's innovative architecture helps customers realize the maximum performance of the DDR4 standard, which is specified to scale up to 3200Mbps, as compared to today's maximum of 2133Mbps for both DDR3 and DDR4 technologies. This technology enables server, network switching, storage fabric and other systems on chip (SoCs) requiring high-memory bandwidth to design-in Cadence® DDR4 PHY IP now and to exploit higher speed DRAMs when they become available.

"The demand for 16nm FinFET-based designs continues to grow and is driving the market need for a complementary DDR4 IP offering," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "Because we have worked very early and closely with Cadence on this technology, our customers can review the design's silicon results to feel confident about turning to Cadence for comprehensive 16nm support from tools to IP."

"Many of our customers are concerned that their next-generation designs might not reach their performance goals because of the bottleneck in memory systems," stated Martin Lund, Cadence's senior vice president and general manager of the IP Group. "By using Cadence DDR4 IP, we believe our customers can have more confidence that their products will work with future DRAMs designed for higher speeds."