Hi,
in the realworld, who is still coding at the gate level and for what
purposes?
-> http://www.asic-world.com/verilog/gate1.html
Are not the manufacturer's tools able to generate more efficient code
with higher level description because some hardware details may not be
documented?
I need realworld examples.
Thanks,

Hi!
I am working on my master diploma and I am designing a mixed signal
ASIC.
So from my (very limited) experience:
-) For normal RTL designs you trust in the synthesis and PnR tools. You
are still working with the standard cells you have to know if something
is faulty.
-) Sometimes you want to design something that is not synthesizable or
you want to do some analog simulation because you want to know the exact
timing.
For the degree of documentation: we got everything from the factory
regarding the std cells. By that I mean the layout (together with the
techfiles I can do post layout simulation) and the digital libaries used
for synthesis and STA. I don't know what else is needed (you could make
the digital libs yourself if you have way to much time). So the hardware
is fully documented. I don't know if this is normal or if other fabs
only give away abstract views of their cells.
But in most uses you should trust in your synthesis and PnR tools. Doing
timing analysis by hand is nearly impossible (especially when you start
talking about setup and hold violation with different corners). I think
creating an 8 bit counter would take some days :D

In our ASIC designs at work, the only thing we write at gate level is
our clocking infrastructure, since glitch-free operation is vital here
(and since you need to use balanced-output clock gates rather than
standard logic cells)
For everything else, synthesis will do a better job than you of
fine-grained optimisation. However, you can help synthesis out a lot by
specifying a more efficient structure at the high level, and this
requires you to think about what you expect your synthesis output to
look like.