IMX233 reset loop during boot, PDN unstable (especially 2v5)

We have created a design using i.mx233, and have great difficulties getting it stable and booting.

Our original reference was Olinuxino Maxi, but we do not support battery, and power the board directly from 5V. We use imx to generate all other power lines needed - or we would like it to. So far we are failing miserably.

Sometimes the board might boot (usually the board behaves better when it has been without power for a while), but still 95% of the time it just stays in a reset loop during power on.

We are using mainline u-boot as our loader, and the same uboot will boot our reference board just fine.

Our PDN schematic looks like this:

And in the scope the power lines look like this:

As you can see from the image, our 2v5 never manages to climb to acceptable levels, and we are suspecting it to cause the crash. 4v2 seems to rise very well, but it drops slightly when 2v5 line is started, but it seems to recover before the reset..

We have also tried to change our caps closer to the Freescale reference design, but there is no real difference. 2v5 looks somewhat different, but actually we still have same stability problems and a reboot.

Could some load (ie. 100k resistor) on the VDDD and VDDA lines help the PDN internally ?

Is there some rule regarding 2v5 capacitor placement we should have followed, or are our values too large ? What kind of values have other projects used ?

We have been trying to get this board to wake up for few weeks now, and we are ready to try almost anything at this point...

In our first production run we decided to try Olimex configuration but it seems difficult to get this configuration working now.. It's strange why they have such a differing configuration to Freescale..

I took a look at the patch set for 5V only configuration - unfortunately it's for Freescale bootlets (we use uboot), but there is some errata workaround for false brownout detection on VDDD, VDDA, VDDIO and VBUSVALID comparators, I will need to study u-boot code more to see if this is implemented there or not.

- Depending of the ddr memory chip, has to work at 2.6V, not 2.5V as in u-boot standard source.

- In one board, we needed to change sd signals strength from 8mA to 4mA (overshoot problems) in uboot and dts.

- A repetitive on/off, without allowing v4.2V discharge, leads to a problem in power supply not initialized correctly. Resolved with a power supervisor: TL77xxA family from TI, and setting CT capacitor to at least 200ms of reset time.

This 800kHz was giving noise to the 4V2 which leads to our instabillity issues.

Now we have added 3 x 22µ capacitors to the DCDC_BATT & BATT pins and memtester currently runs the 29th loop wihtout an error!! Also the voltage on DCDC_BATT, BATT & 4V2 pins does'nt pulse or has spikes, its an nice DC voltage without spikes.

I will let it run a few days to see if its now really stable.

It seem the adding those capacitors to the DCDC_BATT & BATT has solved our issue.