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Abstract

Disclosed is an error detection and isolation technique which utilizes "copy" chips or "bit sliced" chips with common controls. Fault detection is increased, while chip IO and cells are decreased.

Country

United States

Language

English (United States)

This text was extracted from an ASCII text file.

This is the abbreviated version, containing approximately
94% of the total text.

Synchronization Check for Copy Chips

Disclosed is
an error detection and isolation technique
which utilizes "copy" chips or "bit sliced" chips with
common
controls. Fault detection is increased,
while chip IO and cells are
decreased.

First, all
internal parity predicting and parity checking of
control latches are deleted. Second, all
input control parity bits
are deleted, provided each control is sent to the copy chips via
multiple drivers.

Instead of
parity, all the input controls and control latches
are combined (XORed) into one signal.
This signal is then sent to
its neighbor in a ring of copy chips.
See Fig. 1. The chips then
compare their incoming and outgoing signals.
If they are different,
then an error was detected. Fig. 2 illustrates the internal circuitry
required on each chip.

Since the
chips are connected in a ring, the actual chip with
the error may be determined. If two
neighboring chips in the ring
flag errors, then the error was on the previous one. If only one
chip flags an error, then the error is in the synchronization checker
logic.

Error
isolation is achieved by combining the controls into
functional groups and then combining these functional groups into the
signal that is passed to a copy and compared.
If an error is
detected, the functional group signal is latched into a hold register
and scanned out during recovery. The
error can be isolated to the
functional group by compari...