I2C Bus Analyzer and Exerciser Products

CAS-1000-I2C/E™ Bus Analyzer, Exerciser, Emulator, and
Programmer

The CAS-1000-I2C/E™ has all the
power, flexibility, and features needed to debug, validate, and
test the I2C bus circuitry on a printed circuit board. It is an
advanced instrument used in the monitoring and testing of boards
and systems incorporating one or more I2C communication busses.
The CAS-1000-I2C/E can be used to monitor and log I2C bus
traffic in real-time, generate I2C transactions to exercise the
bus and communicate to its components, in-system programming of
I2C EEPROMs, validate bus specification compliance, confirm I2C
protocol of bus traffic, and emulate I2C-compatible devices that
are not yet physically connected to the bus. It further complies
with the SMbus (System Management Bus) standard variant. The
CAS-1000-I2C/E also includes a JTAG controller that, when used
with the optional Corelis ScanExpress™ software, can perform
structural boundary-scan testing and in-system programming of
flash memories and CPLDs.

Because of its rich feature set,
reliability, portability and ease-of-use, the CAS-1000-I2C/E can
be used in a wide variety of applications, such as product
development, troubleshooting, validation, system integration,
production, and field testing. Windows® XP/Vista/7 host software
included with the CAS-1000-I2C/E provides a user-friendly GUI
control and visibility of the CAS-1000-I2C/E, including set-up,
options, traffic visibility screens, and test actions. For
integrating the CAS-1000-I2C/E into a new or existing test
environment, the API included with the CAS-1000-I2C/E can be
used to operate the CAS-1000-I2C/E from third party software
applications such as National Instruments' LabWindows/CVI and
LabView software.

CAS-1000-I2C/E Features

Supports I2C and SMBus

Easily connects to PCs and workstations via USB 2.0
interface

Supports Standard-mode, Fast-mode, and Fast-mode Plus (Fm+)
with I2C bit rates of up to 5 Mbit/sec

I2C Emulator: Enables concurrent virtual devices
programmed to interact with the bus in addition to those
of the target. These can include a Master (capable of
multi-master arbitration), and up to 10 slaves. The
above monitor includes and tags this emulated traffic.

I2C Tester:
Interprets a script program file to control a go-no-go
test sequence, including bus electrical/timing
parametric measurements. This enables automatic target
bus specification compliance and functionality
validation. It is suitable for design/development as
well as factory acceptance testing. The test script
window is shown below.

I2C Parameters Scope: Using the Parameters Scope
tool, the CAS-1000-I2C/E can be utilized to quickly
measure and return the basic electrical and I2C timing
parameters of the target bus without setting up the
advanced scripting functions of the Test tool. It can
gather master specific and slave-specific parameters,
such as signal timing characteristics, and also
system-wide parameters, such as bus voltage, pull-up
resistance, and capacitance. Each measurement is
compared to maximum and minimum values loaded from a
specification file and the resulting pass or fail status
is shown with the measurement. The Parameters Scope
provides the additional ability to display a graph of
captured signal edge transition data and a trigger can
be set to capture a particular I2C bus signal's rising
or falling edge.

CAS-1000-I2C/E Parameters Scope Window
(click for a full size view)

One application of the CAS-1000-I2C/E is to rapidly
validate compliance of a target bus with the
specification. This is supported at the electrical,
timing, as well as the signaling level. Another
application is to passively monitor any I/O activity
transpiring on a target bus. This includes the detection
of errant protocol. All such logged information is time
stamped for history reconstruction. A third application
is the programmed interchange of messages with the
target bus system, also recorded by the monitoring
function. This method can serve to generally exercise
the target bus. It also supports target code development
with debug stand-ins for non-existent bus devices.
Finally, a general user PC to I2C communications link
provides quick and direct visibility/control of target
devices. This is extended to user applications via the
provided API.

SMBus Support

The System Management Bus,
or SMBus, was defined by Intel® Corporation in 1995 and
is based on the I2C bus architecture. It is used in
personal computers and servers for low-speed system
management communications.

SMBus is a two-wire interface through which simple
system and power management related chips can
communicate with the rest of the system. A system using
SMBus as a control bus for these system and power
management related tasks passes messages to and from
devices by addressed transfers, enabling moderate
transfer rates using minimal board resources. With
System Management Bus, for example, a device can provide
manufacturer information, tell the system what its
model/part number is, save its state for a suspend
event, report different types of errors, accept control
parameters, and return its status. The SMBus may share
the same host device and physical bus with standard I2C
components. Intel originally conceived the SMBus as the
communication bus to accommodate Smart Batteries and
other system and power management components.

The CAS-1000-I2C/E software features SMBus decoding for
common SMBus devices. Ordinarily, the raw data of the
I2C transactions between SMBus devices must be manually
decoded into meaningful information. With the SMBus
decoding feature, a specific device address can be
associated with a text file containing decoding
information which allows the I2C Exerciser software to
do the interpretation automatically.

Hardware

At the core of the
CAS-1000-I2C/E is an on-board engine whose logic
performs the low level interaction with the I2C bus.
This element receives set-up, direction and drive data
from the host via a USB 2.0 port. Conversely, as bus
activity is detected and characterized, its transitional
information is conveyed up to the host for further
processing.

In addition there is an array of onboard physical
interface elements to facilitate the required
measurement, capture, and operating capabilities. This
includes a number of DACs to develop the various
programmable voltages.

The
CAS-1000-I2C/E clock rate is programmable under software for use
when emulating a master. It is capable of supporting standard
mode and fast mode transfers of up to 5 Mbits/sec as well as
intermediate values. For emulated slaves, clocking comes from
the target, whose rate is automatically accommodated up to 5 MHz
since the clock rate automatically tracks the target bus master.

Test Discrete I/O Signals

Two programmable lines can be operated under PC host software
control. They are available to stimulate the target system or
sense target conditions in coordination with the testing. Each
line is programmable as input, output, or output open-drain. One
of these outputs can be a dedicated trigger and programmably
linked to the SMB output trigger connector for test
synchronization with external laboratory equipment. The other
discrete I/O can be tied to the other SMB connector as an input
trigger.

Adjustable Voltage Levels

The signal
level of the set of discrete I/O and trigger lines is
programmable from 1.25V to 3.3V in increments of 50mV. The I2C
bus reference voltage can be programmed as target driven through
its bus pull-ups or driven from the CAS-1000-I2C/E I2C analyzer.
This target reference voltage can also be measured. When the
CAS-1000-I2C/E is programmed to source this reference level
(both SCL and SDA signals), the voltage can be set with 100mV
resolution over the range of 0.8V to 5V. When the CAS-1000-I2C/E
reference voltage drives the bus, one of a set of pull-up
resistors can be selected. The resistor values span the range
from 250 to 50K ohms. Additionally, sensed bus signal high and
low individual threshold levels can be adjusted. This supports
the bus hysteresis requirements. Default software-determined
values are available.

CAS-1000-I2C/E Hardware Configuration Window

Auxiliary TAP Port

The CAS-1000-I2C/E includes an IEEE-1149.1 JTAG Test Access Port
(TAP). This port can be used to perform boundary-scan testing
and in-system programming of flash, EEPROMs and PLDs on the
target system and is both hardware and software compatible with
the complete ScanExpress™ family of IEEE-1149.1 test and
in-system programming products offered by Corelis. This feature
is mutually exclusive to the I2C functionality and requires it
to be put into the JTAG mode.

This
CAS-1000-I2C-E Whitepaper provides an overview of
how to expedite the development of I2C bus enabled products for
bus compliance and interoperability.

BusPro-I

While the CAS-1000-I2C/E is
aimed at chip design and verification, the low cost
BusPro-I is intended primarily for engineers who
design and verify printed circuit boards that
incorporate I2C buses. It has many of the same features
and capabilities of the CAS-1000-I2C/E and is available
at a substantially lower price.
Click here
for more information on the
BusPro-I.
Visit our
I2C Bus Analyzer page for a
summary of the BusPro-I and CAS-1000-I2C/E
products.