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Abstract

Integrated circuits have become increasingly dense; the number of circuit I/O pins has not increased accordingly. This has increased the difficulty of 'debugging' new designs. One of the most difficult problems is tracing what internal states an internal finite-state- machine (also called sequencer or counter) has traversed. A technique is described for tracing hardware states by writing them to successive RAM locations. Writes may be triggered at regular intervals or whenever state-changes occur. Timing information may be stored with the data.

Country

United States

Language

English (United States)

This text was extracted from a PDF file.

This is the abbreviated version, containing approximately
54% of the total text.

Integrated circuits have become increasingly dense; the number of circuit I/O
pins has not increased accordingly. This has increased the difficulty of
'debugging' new designs. One of the most difficult problems is tracing what
internal states an internal finite-state- machine (also called sequencer or counter)
has traversed. A technique is described for tracing hardware states by writing
them to successive RAM locations. Writes may be triggered at regular intervals
or whenever state-changes occur. Timing information may be stored with the
data.

This disclosure uses a small amount of extra circuitry added to an integrated
circuit, which regularly copies the state of a sequencer to successive locations in
Random-Access Memory (RAM). The copies can be caused to occur at constant
intervals, or whenever a state transition occurs.

The prior practice of connecting sequencers to test points is no longer a
realistic approach. Other approaches have been used. One is multiplexing a
series of state machines to a single set of pins. Another, applicable to
peripherals attached to a microprocessor bus, involves making each state
machine appear as a readable register.

The former approach lessens the requirement for scarce I/O pins, but does
not completely relieve the problem. The latter is only applicable to static
situations, and is difficult to use for tracing a series of dynamic states, particularly
when the microprocessor is involved in the problem, and cannot be used to trace
machine states.

Several other prior techniques for determining internal states
are:
1 Making each sequencer in a microprocessor peripheral
readable as a register. The problem with this approach

is that software involvement distorts machine timings

and masks problems.
2 Using LSSD techniques. The problem with this approach
is that the peripheral must be halted while external

hardware serially unloads and reloads the chips.
3 Sharing a set of I/O pins multiplexed among a group of
sequencers. The problem here is that a set of I/O pins

is required and expensive logic-analysis test equipment

is necessary to monitor the

I/O pins to provide the same trace functions (clocked, on change, time-
stamped). The new present approach uses RAM and a Direct-Memory Access
(DMA) channel, both of which are already present in microprocessor-based
systems.