The company is also looking at 3D NAND as a way of getting out of a NAND scaling trap. Sub-16nm cell geometries will increasingly ramp up bit error rates and decrease endurance, meaning it will becoming progressively harder - and then impossible - for a next-generation geometry shrink to produce flash chips better than the current cell geometry.

The use of 3D layering is a way to increase flash die footprint capacity without having to go to a post-flash technology, such as Resistive RAM or Phase Change Memory. No post-flash candidate technology is ready for the commercial big time yet.

Micron has licensed Avago’s 28nm Low Power 30Gbps Serializer/Deserializer (SerDes) IP. SerDes blocks serialise and deserialise sequential IO data into/out of parallel data – and in either direction. This is precisely how SerDes will be used in Micron's DRAM Memory cubes. ®