ATM Chip Database

CDR

The CDR VLSI device is a monolithic clock and data recovery component
that receives NRZ data, extracts the high-speed clock, and presents the
separated data and clock as its outputs. This device is designed
specifically for SONET OC12 and SDH STM4 applications at 622 Mbit/s.
The device contains a phase-locked loop (PLL) that generates a stable
622.08 Mbit/s reference clock output based upon an external 38.88 MHz
TTL reference clock input. The PLL is based on a VCO constructed from
integrated reactive components, which form a low-jitter/high-Q
differential tank circuit. Both frequency- and phase-detect circuitsreliably
acquire and hold lock in worst-case input jitter conditions
and scrambling patterns. The lock-detect circuitry signals when the CDR
acquires frequency lock.