As the temperature increases, the atoms that make up the lattice structure of conductors start to vibrate more vigorously [over greater distances]. As a result of this, mobile electrons in the conductor may collide more often with vibrating ions. Hence an increase in electrical resistance. Picture this, it is easier to walk in a street where people are only standing around, but if its busy [like rush hour in Manhattan], you'll find it harder to make your way through the crowd.

The reason people actively cool processors is not to reduce the resistance of the wires inside the chip (the resistance of the wires is somewhat inconsequential). They do it because running a chip at a higher frequency means it produces more heat, and that heat has to be removed somehow.

The reason people actively cool processors is not to reduce the resistance of the wires inside the chip (the resistance of the wires is somewhat inconsequential). They do it because running a chip at a higher frequency means it produces more heat, and that heat has to be removed somehow.

- Warren

OK, but why is resistance of the wires inconsequential? I thought less resistance meant faster data flow? Isn't this the very reason superconductors are preferred?

chroot, in devices like FETs and HBTs, the speed of the device is largely determined by electron mobility (and the related saturation velocity) in conjunction with the local band structure. It was primarily the recognition of higher mobilities that lead to the interest in making GaAs/AlGaAs based hi-speed devices.

As for resistance of metallic traces - that is irrelevant for the reason provided by chroot. The speed of the device is largely limited by things like tunneling rates, charging time constants, and transport rates through semiconductor channels. Of course, a chunk of semiconductor at low temperatures has a much higher resistivity than at higher temperatures, but that is an effect that does not play a role in the speed of the device.

Resistance does change with temperature, but the velocity of signal propagation does not. Remember, most circuits use voltage signals, not current signals.

- Warren

well, actually Warren, in a transmission line, if the per length resistance increases and all other per length electrical parameters remain constant (capacitance, inductance), the signal velocity through the line will decrease. that's in the math. need me to look it up?

well, actually Warren, in a transmission line, if the per length resistance increases and all other per length electrical parameters remain constant (capacitance, inductance), the signal velocity through the line will decrease. that's in the math. need me to look it up?

Its becuase of this increase in resistance that it was stressed that I design circuits to rely on voltage signals rather than current signals. But I'm curious as to how what you stated will affect this situation.

well, actually Warren, in a transmission line, if the per length resistance increases and all other per length electrical parameters remain constant (capacitance, inductance), the signal velocity through the line will decrease. that's in the math. need me to look it up?

Yeah, perhaps you do need to look it up. The signal propagation velocity in a transmission line depends only on the dielectric constant of the material around it, not on its series resistance.

Besides, I don't really know why you'd want to model a wire on an IC as a transmission line.

Yeah, perhaps you do need to look it up. The signal propagation velocity in a transmission line depends only on the dielectric constant of the material around it, not on its series resistance.

no, that is not true. in the Wikipedia example, at http://en.wikipedia.org/wiki/Telegrapher's_equations , they start with the general non-zero series resistance, but then they solve it with the assumption that R=0 and G=0 (i know i just added the text that qualified that, but i know that, technically, the previous authors/editors did that). do you need me to go through the general solution of the telegrapher's equations to prove this?

try to imagine a chain of cascaded RC low-pass filters. the time-constant for each cascaded section is RC. as either R or C increase, the response time of each section increases and the speed of propagation through this cascade of RC sections will decrease. it's pretty obvious, i don't have my old Transmission Lines text here at the office, but the telegrapher's equations at the Wikipedia site are correct and general. but the solution is not general and is correct only for the lossless case. do you want me to give you the general solution? i can solve those in terms of a general R, L, G, C, but it's a little laborious and i haven't found a quick little website with the general solution.

Besides, I don't really know why you'd want to model a wire on an IC as a transmission line.

it's called "microstrip" and they do it both for layout on a PC board and on IC chips. http://en.wikipedia.org/wiki/Microstrip Warren, this is how the hardcore chip designers deal with signal propagation, delays, and reflections in a system. admittedly, they almost always use the lossless model (R=0 and G=0). it's how we deal with reflections and "ringing" when the signal is not perfectly terminated.

I understand the telegrapher's equations. I don't know why you keep harping on this, because you already understand that the resistance of a channel in a MOSFET is much more significant than the resistance of an interconnect wire in calculating the delays through digital logic -- right? And thus that my conclusion (the effect on temperature on interconnect wire resistance is insignificant) is still as true at this moment as it was when I first wrote it.

It's silly to model a digital interconnect wire as a transmission line, unless you're being compulsively pedantic, because we both know that essentially the only characteristic of the interconnect that matters materially is its capacitance.

You can go on and on with your presentation of negligible effects, if you'd like. I won't stop you. It's just a little silly and out of place. The original poster was asking about how temperature affects the speed of his microprocessor.

Warren, this is how the hardcore chip designers deal with signal propagation, delays, and reflections in a system. admittedly, they almost always use the lossless model (R=0 and G=0). it's how we deal with reflections and "ringing" when the signal is not perfectly terminated.

Perhaps you're not aware, but I'm an integrated circuit designer. Are you just name-dropping microstrip construction to inflate your argument? We're talking about digital logic running at, maximally, a few gigahertz. There's no reason to muddy the waters and bring microwave frequency effects into this discussion. It just isn't relevant, at all.

Are you just name-dropping microstrip construction to inflate your argument?

no, just to answer the implied question in "Besides, I don't really know why you'd want to model a wire on an IC as a transmission line."

I don't model wires on ICs as a transmission line, but i've certainly have read, in both texts (Bracewell) and in IEEE stuff, that "they" (some of your fellow IC designers) do use transmission line modeling for traces on PC boards and in high speed ICs.

We're talking about digital logic running at, maximally, a few gigahertz. There's no reason to muddy the waters and bring microwave frequency effects into this discussion. It just isn't relevant, at all.

i guess not. you tell me, but the clock speeds of modern ICs (Ghz) is in the microwave region of the spectrum, why does bringing microwave frequency effects muddy the waters?

i am pedantic (i'm a DSP alg guy and i'll leave the hardcore IC design to the hardcore IC designers) but i do read about stuff that is not DSP. i also remember my analog circuit theory pretty well and knew that the series resistance contributes to the expression of phase velocity or group velocity of a transmission line. i also knew, and said as much, that in the use of transmission line modeling done on either the PC or IC context that they assume lossless with R=0 and G=0. if R is already treated as zero, sure, increasing temperature is not going to increase it, but i thought this statement was still relevant and accurate, at least theorectically: "in a transmission line, if the per length resistance increases and all other per length electrical parameters remain constant (capacitance, inductance), the signal velocity through the line will decrease." i didn't say the effect was measurable, only that it's in the math (and i think i can still show this "pedantically"). but i thought that it was in the context of the question that the OP was asking. do supercooled devices run faster than they would at room temp (or warmer)?

"they" (some of your fellow IC designers) do use transmission line modeling for traces on PC boards and in high speed ICs.

Of course, transmission line modelling makes sense for PCB traces at gigahertz frequencies.

For a first approximation of the delay through a CMOS gate, you only need two numbers: the resistance of the conducting paths that connect the gate's output to ground or VDD, and the capacitance seen at the gate output. That RC delay totally, completely swamps any RC delay seen on reasonable pieces of interconnect metal. The typical on-resistance of a transistor is in the range of kilohms, and the typical gate and diffusion capacitances are of the order of tens of femtofarads. These are very, very large numbers compared to those of the metal.

Temperature does affect the carrier mobility in the silicon -- and thus the on-resistance of transistors, as Gokul pointed out -- and this is a much larger effect than that of the changing resistance of interconnect.

The truth is, digital logic design tools do use a "wire load model" which attempts to include R, C, and L, and R is certainly non-zero. (I should note that in all the technologies I'm familiar with, R is considered fixed, unchanging with temperature, by the EDA tools.) Unfortunately, wire load models are notoriously inaccurate, and, generally, the only way to really verify a very high-speed design is to do post-layout extraction. We're in an age where EDA companies are trying to model second-order effects from the very beginning of the design workflow, but are currently doing a pretty lousy job at it.

i guess not. you tell me, but the clock speeds of modern ICs (Ghz) is in the microwave region of the spectrum, why does bringing microwave frequency effects muddy the waters?

It's a little debatable that 1 GHz is really "microwave," or that you truly need microwave design techniques to accomplish such a design. Many people design (small) 1 GHz logic with standard EDA tools, which have no knowledge of microwave circuit behavior. Current technology nodes (like 0.18u CMOS) have toggle frequencies of tens of GHz.

i am pedantic (i'm a DSP alg guy and i'll leave the hardcore IC design to the hardcore IC designers) but i do read about stuff that is not DSP. i also remember my analog circuit theory pretty well and knew that the series resistance contributes to the expression of phase velocity or group velocity of a transmission line.

It does, and you're correct. It's just a negligible effect, so I left it out.

i didn't say the effect was measurable, only that it's in the math (and i think i can still show this "pedantically").

It's in the math. We both know that. I left it out, and you called me on it as if I didn't know what I was talking about. I took offense to that (my apologies) and just wanted to explain that the reason I left it out is because it's negligible.

but i thought that it was in the context of the question that the OP was asking. do supercooled devices run faster than they would at room temp (or warmer)?

Well, people who cool their processors actively then go on to overclock them. The resulting junction temperatures deep inside the die are probably not much different than they were to start with, so the chip is not operating with any less resistance, or propagating signals any more quickly. Cooling the chip actively just enables higher clock frequencies by removing the waste heat more effectively.

It's silly to model a digital interconnect wire as a transmission line, unless you're being compulsively pedantic, because we both know that essentially the only characteristic of the interconnect that matters materially is its capacitance.

Chroot, just a question : why does the interconnect need to be a low k (ie low capacitance) material ? Is that because the interconnecting wires are shorter for the same capacitance , just like a high k dielectric is thicker for the same capacitance ? What are the considerations for these interconnects ? Why a low k (for example : you wanna have a high k dielectric in a MOSFET to undo the charge loss in the channel due to charge tunneling, hopping toward the gate). Any "similar" considerations for interconnects ?

Low-k interlayer dielectric material just reduces the parasitic capacitances seen by the gate outputs.

- Warren

Ok, and how do these parasetic capacitances lower the quality of the interconnect or the gate at the interconnect side (i know how such capacitances disturbe the MOSFET functionality at the gate/high k dielectric interface)? Do they delay the processing or something ?

Parasitic capacitances affect the speed of gates (it takes more time to charge and discharge large capacitances).

Basically, you can model a gate as a resistance connecting its output to VDD or ground, and a capacitance being charged or discharged whenever the gate output changes. The capacitance seen by the output is the sum of diffusion capacitances of the driving transistors, interconnect capacitance (which can be substantial for long lines), and gate capacitance of the inputs of other gates.

Parasitic capacitances affect the speed of gates (it takes more time to charge and discharge large capacitances).

Basically, you can model a gate as a resistance connecting its output to VDD or ground, and a capacitance being charged or discharged whenever the gate output changes. The capacitance seen by the output is the sum of diffusion capacitances of the driving transistors, interconnect capacitance (which can be substantial for long lines), and gate capacitance of the inputs of other gates.

I should also mention that digital designs are becoming more and more dominated by the interconnect as geometries shrink. In other words, the die area consumed by routing is almost always larger than the area consumed by transistors. The end result is that "transistors are free," in the sense that interconnect is what ends up filling up a die's area.

Because of this, a lot of research is going into making the interconnect more "transparent."