GCC vs Clang vs ICC for 32-bit register manipulation

Today godbolt released a new compiler comparison feature and I decided to quickly try to compare C++ vs C style register manipulation and see what kind of optimizations will be applied across the different compilers.

Source code

So I wrote a naive C++ class that would represent a 32-bit register.

Note that I am trying here to test compilers’ optimization on class member manipulation, rather than making the case for embedded C++ (where bits in registers would be volatile, since the order of bit setting is significant most of the time).

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structRegister

{

unsignedintb0:1;

unsignedintb1:1;

unsignedintb2:1;

unsignedintb3:1;

unsignedintb4:1;

unsignedintb5:1;

unsignedintb6:1;

unsignedintb7:1;

unsignedintb8:1;

unsignedintb9:1;

unsignedintb10:1;

unsignedintb11:1;

unsignedintb12:1;

unsignedintb13:1;

unsignedintb14:1;

unsignedintb15:1;

unsignedintb16:1;

unsignedintb17:1;

unsignedintb18:1;

unsignedintb19:1;

unsignedintb20:1;

unsignedintb21:1;

unsignedintb22:1;

unsignedintb23:1;

unsignedintb24:1;

unsignedintb25:1;

unsignedintb26:1;

unsignedintb27:1;

unsignedintb28:1;

unsignedintb29:1;

unsignedintb30:1;

unsignedintb31:1;

inlinevoidSet(unsignedcharbitNumber,boolvalue)

{

switch(bitNumber)

{

case0:b0=value;break;

case1:b1=value;break;

case2:b2=value;break;

case3:b3=value;break;

case4:b4=value;break;

case5:b5=value;break;

case6:b6=value;break;

case7:b7=value;break;

case8:b8=value;break;

case9:b9=value;break;

case10:b10=value;break;

case11:b11=value;break;

case12:b12=value;break;

case13:b13=value;break;

case14:b14=value;break;

case15:b15=value;break;

case16:b16=value;break;

case17:b17=value;break;

case18:b18=value;break;

case19:b19=value;break;

case20:b20=value;break;

case21:b21=value;break;

case22:b22=value;break;

case23:b23=value;break;

case24:b24=value;break;

case25:b25=value;break;

case26:b26=value;break;

case27:b27=value;break;

case28:b28=value;break;

case29:b29=value;break;

case30:b30=value;break;

case31:b31=value;break;

}

}

};

After that you can see I am using it to set the 0, 1, 3, 5, 13 and 30th bits of the register:

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voidcppFunction(Register&reg)

{

reg.Set(0,true);

reg.Set(1,true);

reg.Set(3,true);

reg.Set(5,true);

reg.Set(13,true);

reg.Set(30,true);

}

the corresponding C implementation is:

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voidcFunction(int*reg)

{

*reg|=(1<<0)|(1<<1)|(1<<3)|(1<<5)|(1<<13)|(1<<30);

}

I am also calling the above functions from a third one to see if the compilers will inline it:

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voidCaller(Register&reg1,int*reg2)

{

cppFunction(reg1);

cFunction(reg2);

}

The compilers

I am comparing three compilers:

gcc 6.2

clang 3.9.0

icc 17

All are using the following options: -O3 -mtune=native -march=native

I would expect that the compilers “see trough” the C++ code and optimize it completely with a simple instruction.

Let’s see the assembly of GCC:

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cppFunction(Register&):

orBYTEPTR[rdi],43

orBYTEPTR[rdi+1],32

orBYTEPTR[rdi+3],64

ret

cFunction(int*):

orDWORDPTR[rdi],1073750059

ret

Caller(Register&,int*):

orBYTEPTR[rdi],43

orBYTEPTR[rdi+1],32

orBYTEPTR[rdi+3],64

orDWORDPTR[rsi],1073750059

ret

We see that the cFunction() was correctly optimized and the rdi register representing the register is set correctly with one ‘or‘ instruction.

The cppFunction() on the other is less than ideal – it uses BYTE_PTR addressing three times instead of one DWORD.

The above functions has been correctly inlined in the Caller() function, which does nothing but function calls.

Now lets see Clang:

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cppFunction(Register&):#@cppFunction(Register&)

ordwordptr[rdi],1073750059

ret

cFunction(int*):#@cFunction(int*)

ordwordptr[rdi],1073750059

ret

Caller(Register&,int*):#@Caller(Register&,int*)

ordwordptr[rdi],1073750059

ordwordptr[rsi],1073750059

ret

Wow, we see correct optimization on all three points there… nothing could be done better.

What about the Intel Compiler:

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cppFunction(Register&):

pushrbp#80.1

xoresi,esi#81.7

movedx,1#81.7

movrbp,rdi#80.1

callRegister::Set(unsignedchar,bool)#81.7

movesi,1#82.7

movrdi,rbp#82.7

movedx,esi#82.7

callRegister::Set(unsignedchar,bool)#82.7

movrdi,rbp#83.7

movesi,3#83.7

movedx,1#83.7

callRegister::Set(unsignedchar,bool)#83.7

orBYTEPTR[rbp],32#48.15

orBYTEPTR[1+rbp],32#56.16

orBYTEPTR[3+rbp],64#73.16

poprbp#87.1

ret#87.1

Register::Set(unsignedchar,bool):

movzxesi,sil#40.3

cmpesi,31#41.5

ja..B2.67#Prob50%#41.5

jmpQWORDPTR[.2.10_2.switchtab.3+rsi*8]#41.5

..1.1_0.TAG.31.0.1:

movzxeax,BYTEPTR[3+rdi]#74.16

shledx,7#74.16

andeax,127#74.16

oreax,edx#74.16

movBYTEPTR[3+rdi],al#74.16

jmp..B2.67#Prob100%#74.16

..1.1_0.TAG.30.0.1:

andedx,1#73.16

movzxeax,BYTEPTR[3+rdi]#73.16

shledx,6#73.16

andeax,-65#73.16

oreax,edx#73.16

movBYTEPTR[3+rdi],al#73.16

jmp..B2.67#Prob100%#73.16

..1.1_0.TAG.29.0.1:

andedx,1#72.16

movzxeax,BYTEPTR[3+rdi]#72.16

shledx,5#72.16

andeax,-33#72.16

oreax,edx#72.16

movBYTEPTR[3+rdi],al#72.16

jmp..B2.67#Prob100%#72.16

..1.1_0.TAG.28.0.1:

andedx,1#71.16

movzxeax,BYTEPTR[3+rdi]#71.16

shledx,4#71.16

andeax,-17#71.16

oreax,edx#71.16

movBYTEPTR[3+rdi],al#71.16

jmp..B2.67#Prob100%#71.16

..1.1_0.TAG.27.0.1:

..B2.12:#Preds..B2.2

andedx,1#70.16

movzxeax,BYTEPTR[3+rdi]#70.16

shledx,3#70.16

andeax,-9#70.16

oreax,edx#70.16

movBYTEPTR[3+rdi],al#70.16

jmp..B2.67#Prob100%#70.16

..1.1_0.TAG.26.0.1:

..B2.14:#Preds..B2.2

andedx,1#69.16

movzxeax,BYTEPTR[3+rdi]#69.16

shledx,2#69.16

andeax,-5#69.16

oreax,edx#69.16

movBYTEPTR[3+rdi],al#69.16

jmp..B2.67#Prob100%#69.16

..1.1_0.TAG.25.0.1:

..B2.16:#Preds..B2.2

andedx,1#68.16

movzxeax,BYTEPTR[3+rdi]#68.16

addedx,edx#68.16

andeax,-3#68.16

oreax,edx#68.16

movBYTEPTR[3+rdi],al#68.16

jmp..B2.67#Prob100%#68.16

..1.1_0.TAG.24.0.1:

..B2.18:#Preds..B2.2

movzxeax,BYTEPTR[3+rdi]#67.16

andedx,1#67.16

andeax,-2#67.16

oreax,edx#67.16

movBYTEPTR[3+rdi],al#67.16

jmp..B2.67#Prob100%#67.16

..1.1_0.TAG.23.0.1:

..B2.20:#Preds..B2.2

movzxeax,BYTEPTR[2+rdi]#66.16

shledx,7#66.16

andeax,127#66.16

oreax,edx#66.16

movBYTEPTR[2+rdi],al#66.16

jmp..B2.67#Prob100%#66.16

..1.1_0.TAG.22.0.1:

..B2.22:#Preds..B2.2

andedx,1#65.16

movzxeax,BYTEPTR[2+rdi]#65.16

shledx,6#65.16

andeax,-65#65.16

oreax,edx#65.16

movBYTEPTR[2+rdi],al#65.16

jmp..B2.67#Prob100%#65.16

..1.1_0.TAG.21.0.1:

..B2.24:#Preds..B2.2

andedx,1#64.16

movzxeax,BYTEPTR[2+rdi]#64.16

shledx,5#64.16

andeax,-33#64.16

oreax,edx#64.16

movBYTEPTR[2+rdi],al#64.16

jmp..B2.67#Prob100%#64.16

..1.1_0.TAG.20.0.1:

..B2.26:#Preds..B2.2

andedx,1#63.16

movzxeax,BYTEPTR[2+rdi]#63.16

shledx,4#63.16

andeax,-17#63.16

oreax,edx#63.16

movBYTEPTR[2+rdi],al#63.16

jmp..B2.67#Prob100%#63.16

..1.1_0.TAG.19.0.1:

..B2.28:#Preds..B2.2

andedx,1#62.16

movzxeax,BYTEPTR[2+rdi]#62.16

shledx,3#62.16

andeax,-9#62.16

oreax,edx#62.16

movBYTEPTR[2+rdi],al#62.16

jmp..B2.67#Prob100%#62.16

..1.1_0.TAG.18.0.1:

..B2.30:#Preds..B2.2

andedx,1#61.16

movzxeax,BYTEPTR[2+rdi]#61.16

shledx,2#61.16

andeax,-5#61.16

oreax,edx#61.16

movBYTEPTR[2+rdi],al#61.16

jmp..B2.67#Prob100%#61.16

..1.1_0.TAG.17.0.1:

..B2.32:#Preds..B2.2

andedx,1#60.16

movzxeax,BYTEPTR[2+rdi]#60.16

addedx,edx#60.16

andeax,-3#60.16

oreax,edx#60.16

movBYTEPTR[2+rdi],al#60.16

jmp..B2.67#Prob100%#60.16

..1.1_0.TAG.16.0.1:

..B2.34:#Preds..B2.2

movzxeax,BYTEPTR[2+rdi]#59.16

andedx,1#59.16

andeax,-2#59.16

oreax,edx#59.16

movBYTEPTR[2+rdi],al#59.16

jmp..B2.67#Prob100%#59.16

..1.1_0.TAG.15.0.1:

..B2.36:#Preds..B2.2

movzxeax,BYTEPTR[1+rdi]#58.16

shledx,7#58.16

andeax,127#58.16

oreax,edx#58.16

movBYTEPTR[1+rdi],al#58.16

jmp..B2.67#Prob100%#58.16

..1.1_0.TAG.14.0.1:

..B2.38:#Preds..B2.2

andedx,1#57.16

movzxeax,BYTEPTR[1+rdi]#57.16

shledx,6#57.16

andeax,-65#57.16

oreax,edx#57.16

movBYTEPTR[1+rdi],al#57.16

jmp..B2.67#Prob100%#57.16

..1.1_0.TAG.13.0.1:

..B2.40:#Preds..B2.2

andedx,1#56.16

movzxeax,BYTEPTR[1+rdi]#56.16

shledx,5#56.16

andeax,-33#56.16

oreax,edx#56.16

movBYTEPTR[1+rdi],al#56.16

jmp..B2.67#Prob100%#56.16

..1.1_0.TAG.12.0.1:

..B2.42:#Preds..B2.2

andedx,1#55.16

movzxeax,BYTEPTR[1+rdi]#55.16

shledx,4#55.16

andeax,-17#55.16

oreax,edx#55.16

movBYTEPTR[1+rdi],al#55.16

jmp..B2.67#Prob100%#55.16

..1.1_0.TAG.11.0.1:

..B2.44:#Preds..B2.2

andedx,1#54.16

movzxeax,BYTEPTR[1+rdi]#54.16

shledx,3#54.16

andeax,-9#54.16

oreax,edx#54.16

movBYTEPTR[1+rdi],al#54.16

jmp..B2.67#Prob100%#54.16

..1.1_0.TAG.10.0.1:

..B2.46:#Preds..B2.2

andedx,1#53.16

movzxeax,BYTEPTR[1+rdi]#53.16

shledx,2#53.16

andeax,-5#53.16

oreax,edx#53.16

movBYTEPTR[1+rdi],al#53.16

jmp..B2.67#Prob100%#53.16

..1.1_0.TAG.9.0.1:

..B2.48:#Preds..B2.2

andedx,1#52.15

movzxeax,BYTEPTR[1+rdi]#52.15

addedx,edx#52.15

andeax,-3#52.15

oreax,edx#52.15

movBYTEPTR[1+rdi],al#52.15

jmp..B2.67#Prob100%#52.15

..1.1_0.TAG.8.0.1:

..B2.50:#Preds..B2.2

movzxeax,BYTEPTR[1+rdi]#51.15

andedx,1#51.15

andeax,-2#51.15

oreax,edx#51.15

movBYTEPTR[1+rdi],al#51.15

jmp..B2.67#Prob100%#51.15

..1.1_0.TAG.7.0.1:

..B2.52:#Preds..B2.2

movzxeax,BYTEPTR[rdi]#50.15

shledx,7#50.15

andeax,127#50.15

oreax,edx#50.15

movBYTEPTR[rdi],al#50.15

jmp..B2.67#Prob100%#50.15

..1.1_0.TAG.6.0.1:

..B2.54:#Preds..B2.2

andedx,1#49.15

movzxeax,BYTEPTR[rdi]#49.15

shledx,6#49.15

andeax,-65#49.15

oreax,edx#49.15

movBYTEPTR[rdi],al#49.15

jmp..B2.67#Prob100%#49.15

..1.1_0.TAG.5.0.1:

..B2.56:#Preds..B2.2

andedx,1#48.15

movzxeax,BYTEPTR[rdi]#48.15

shledx,5#48.15

andeax,-33#48.15

oreax,edx#48.15

movBYTEPTR[rdi],al#48.15

jmp..B2.67#Prob100%#48.15

..1.1_0.TAG.4.0.1:

..B2.58:#Preds..B2.2

andedx,1#47.15

movzxeax,BYTEPTR[rdi]#47.15

shledx,4#47.15

andeax,-17#47.15

oreax,edx#47.15

movBYTEPTR[rdi],al#47.15

jmp..B2.67#Prob100%#47.15

..1.1_0.TAG.3.0.1:

..B2.60:#Preds..B2.2

andedx,1#46.15

movzxeax,BYTEPTR[rdi]#46.15

shledx,3#46.15

andeax,-9#46.15

oreax,edx#46.15

movBYTEPTR[rdi],al#46.15

jmp..B2.67#Prob100%#46.15

..1.1_0.TAG.2.0.1:

..B2.62:#Preds..B2.2

andedx,1#45.15

movzxeax,BYTEPTR[rdi]#45.15

shledx,2#45.15

andeax,-5#45.15

oreax,edx#45.15

movBYTEPTR[rdi],al#45.15

jmp..B2.67#Prob100%#45.15

..1.1_0.TAG.1.0.1:

..B2.64:#Preds..B2.2

andedx,1#44.15

movzxeax,BYTEPTR[rdi]#44.15

addedx,edx#44.15

andeax,-3#44.15

oreax,edx#44.15

movBYTEPTR[rdi],al#44.15

jmp..B2.67#Prob100%#44.15

..1.1_0.TAG.0.0.1:

..B2.66:#Preds..B2.2

movzxeax,BYTEPTR[rdi]#43.15

andedx,1#43.15

andeax,-2#43.15

oreax,edx#43.15

movBYTEPTR[rdi],al#43.15

..B2.67:#Preds..B2.1..B2.4..B2.6..B2.8..B2.10

ret#76.3

.2.10_2.switchtab.3:

.quad..1.1_0.TAG.0.0.1

.quad..1.1_0.TAG.1.0.1

.quad..1.1_0.TAG.2.0.1

.quad..1.1_0.TAG.3.0.1

.quad..1.1_0.TAG.4.0.1

.quad..1.1_0.TAG.5.0.1

.quad..1.1_0.TAG.6.0.1

.quad..1.1_0.TAG.7.0.1

.quad..1.1_0.TAG.8.0.1

.quad..1.1_0.TAG.9.0.1

.quad..1.1_0.TAG.10.0.1

.quad..1.1_0.TAG.11.0.1

.quad..1.1_0.TAG.12.0.1

.quad..1.1_0.TAG.13.0.1

.quad..1.1_0.TAG.14.0.1

.quad..1.1_0.TAG.15.0.1

.quad..1.1_0.TAG.16.0.1

.quad..1.1_0.TAG.17.0.1

.quad..1.1_0.TAG.18.0.1

.quad..1.1_0.TAG.19.0.1

.quad..1.1_0.TAG.20.0.1

.quad..1.1_0.TAG.21.0.1

.quad..1.1_0.TAG.22.0.1

.quad..1.1_0.TAG.23.0.1

.quad..1.1_0.TAG.24.0.1

.quad..1.1_0.TAG.25.0.1

.quad..1.1_0.TAG.26.0.1

.quad..1.1_0.TAG.27.0.1

.quad..1.1_0.TAG.28.0.1

.quad..1.1_0.TAG.29.0.1

.quad..1.1_0.TAG.30.0.1

.quad..1.1_0.TAG.31.0.1

cFunction(int*):

orDWORDPTR[rdi],1073750059#92.4

ret#93.1

Caller(Register&,int*):

pushr13#97.1

pushr14#97.1

pushrsi#97.1

movr14,rsi#97.1

xoresi,esi#81.7

movedx,1#81.7

movr13,rdi#97.1

callRegister::Set(unsignedchar,bool)#81.7

movesi,1#82.7

movrdi,r13#82.7

movedx,esi#82.7

callRegister::Set(unsignedchar,bool)#82.7

movrdi,r13#83.7

movesi,3#83.7

movedx,1#83.7

callRegister::Set(unsignedchar,bool)#83.7

orBYTEPTR[r13],32#48.15

orBYTEPTR[1+r13],32#56.16

orBYTEPTR[3+r13],64#73.16

orDWORDPTR[r14],1073750059#92.4

poprcx#100.1

popr14#100.1

popr13#100.1

ret#100.1

The conclusion

So it seems that GCC does a good job on the C code, but not so much on the C++ one.