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Since 1987 - Covering the Fastest Computers in the World and the People Who Run ThemFri, 09 Dec 2016 13:18:37 +0000en-UShourly1https://wordpress.org/?v=4.760365857The Week in HPC Researchhttps://www.hpcwire.com/2013/03/14/the_week_in_hpc_research-7/?utm_source=rss&utm_medium=rss&utm_campaign=the_week_in_hpc_research-7
https://www.hpcwire.com/2013/03/14/the_week_in_hpc_research-7/#respondThu, 14 Mar 2013 07:00:00 +0000http://www.hpcwire.com/?p=4161<img src="http://media2.hpcwire.com/hpcwire/test_tube_image_200x.jpg" alt="" width="93" height="61" />The top research stories of the week include the 2012 Turing Prize winners; an examination of MIC acceleration in short-range molecular dynamics simulations; a new computer model to help predict the best HIV treatment; the role of atmospheric clouds in climate change models; and more reliable HPC cloud computing.

]]>The top research stories of the week have been hand-selected from leading scientific centers, prominent journals and relevant conference proceedings. Here’s another diverse set of items, including the just-announced 2012 Turing Prize winners; an examination of MIC acceleration in short-range molecular dynamics simulations; a new computer model to help predict the best HIV treatment; the role of atmospheric clouds in climate change models; and more reliable cloud computing.

Security Researchers Win Turing Prize

The Association for Computing Machinery (ACM) has named the 2012 Turning Prize winners. The esteemed award goes to Shafi Goldwasser of the Massachusetts Institute of Technology (MIT) and the Weizmann Institute of Science and Silvio Micali of MIT for their ground-breaking work in cryptography and complexity theory.

Goldwasser and Micali carried out pioneering research in field of provable security. Their work laid the mathematical foundations that made modern cryptography possible. The ACM observes that “by formalizing the concept that cryptographic security had to be computational rather than absolute, they created mathematical structures that turned cryptography from an art into a science.”

ACM President Vint Cerf provided additional details in a prepared statement. “The encryption schemes running in today’s browsers meet their notions of security,” he said of the duo. “The method of encrypting credit card numbers when shopping on the Internet also meets their test. We are indebted to these recipients for their innovative approaches to ensuring security in the digital age.”

So many of our daily activities are possible because of their research. According to Alfred Spector, vice president of Research and Special Initiatives at Google Inc., these achievements have changed how we work and live. Applications extend to ATM cards, computer passwords, electronic commerce and even electronic voting.

The Turing Prize has been called the “Nobel Prize in Computing.” It carries a $250,000 prize, funded by Intel Corporation and Google Inc.

A team of researchers from the National University of Defense Technology in Changsha, China, is investigating the use of MIC acceleration in short-range molecular dynamics simulations.

Their paper in the Proceedings of the First International Workshop on Code OptimiSation for MultI and many Cores (COSMIC’13) begins with the observation that heterogeneous systems built with accelerators (like GPUs) or coprocessors (like Intel MIC) are increasing in popularity. Such architectures are used for their ability to exploit large-scale parallelism.

The team reports optimum performance on the hybrid CPU-MIC system. They write: “by employing a hierarchy of parallelism with several optimization methods such as memory latency hiding and data pre-fetching, our MD code running on a CPU-MIC heterogeneous system…achieves (1) multi-thread parallel efficiency of 72.4% for 57 threads on the co-processor with up to 7.62 times SIMD speedup on each core for the force computation task, and (2) up to 2.25 times speedup on the CPU-MIC system over the pure CPU system, which outperforms our previous work on a CPU-GPU (one NVIDIA Tesla M2050) platform.”

According to the study, the models can predict how HIV patients whose drug therapy is failing will respond to combination antiretroviral therapy (ART). Most notably for resource-constrained regions, the models do not require the expensive genotyping tests that are normally used to predict drug resistance. In effect, the researchers were able to create a model that predicted response to ART without a genotype with comparable accuracy to a genotyping-based assessment.

Julio Montaner, former President of the International AIDS Society, commented: “This is the first time this approach has been tried with real cases of treatment failure from resource-limited settings.”

Director of the BC Centre for Excellence in HIV & AIDS, based in Vancouver, Canada, and an author on the paper, said, “the results show that using sophisticated computer based algorithms we can effectively put the experience of treating thousands of patients into the hands of the under-resourced physician with potentially huge benefits.”

Climate models continue to improve, and scientist are producing realistic representations of the oceans, ice, land surfaces and atmospheric conditions. However, a model will always have some degree of uncertainty, and when it comes to climate models, clouds pose the greatest challenge to accuracy.

As an article at Berkeley Lab News Center explains, “clouds can both cool the planet, by acting as a shield against the sun, and warm the planet, by trapping heat.”

Lawrence Berkeley National Laboratory scientist David Romps is investigating the behavior of clouds. He hopes to address why they act like they do and how their cover affects the temperatures of a planet.

“We don’t understand many basic things about clouds,” he says. “We don’t know why clouds rise at the speeds they do. We don’t know why they are the sizes they are. We lack a fundamental theory for what is a very peculiar case of fluid flow. There’s a lot of theory that remains to be done.”

The earth’s response to atmospheric levels of CO2 is studied using global climate models (GCMs) on lab supercomputers. At current computational limits, GCMs are restricted to modeling atmospheric samples less than 100 kilometers in size. However, convective clouds have sizes closer to 1 km, placing them outside the boundaries of GCMs. In response to this dilemma, climate scientists use submodels to resolve cloud behavior. It gets the job done, but comes with its own set of limitations, which Romp is chipping away at.

He’s already had some early successes. His theory that climate change, or rising temperatures, will result in fewer clouds was confirmed with a high-resolution model.

A team of computer scientists from Louisiana Tech University has contributed to the growing body of HPC cloud research, specifically as it relates to the reliability of cloud computing resources. Their paper, A Reliability Model for Cloud Computing for High Performance Computing Applications, was published in the book, Euro-Par 2012: Parallel Processing Workshops.

Cloud computing and virtualization allow resources to be used more efficiently. Public cloud resources are available on-demand and don’t require an expensive capital expenditure. But with an increase in both software and hardware components, comes a corresponding rise in server failure. The researchers assert that it’s important for service providers to understand the failure behavior of a cloud system, so they can better manage the resources. Much of their research applies specifically to the running of HPC applications on the cloud.

In the paper, the researchers “propose a reliability model for a cloud computing system that considers software, application, virtual machine, hypervisor, and hardware failures as well as correlation of failures within the software and hardware.”

They conclude failures caused by dependencies create a less reliable system, and as the failure rate of the system increases, the mean time to failure decreases. Not surprisingly, they also find that an increase in the number of nodes decreases the reliability of the system.

]]>https://www.hpcwire.com/2013/03/14/the_week_in_hpc_research-7/feed/04161Heterogeneous Computing and HPC Accelerators, Disruptive Technologies in the Makinghttps://www.hpcwire.com/2011/06/18/heterogeneous_computing_and_hpc_accelerators_disruptive_technologies_in_the_making/?utm_source=rss&utm_medium=rss&utm_campaign=heterogeneous_computing_and_hpc_accelerators_disruptive_technologies_in_the_making
https://www.hpcwire.com/2011/06/18/heterogeneous_computing_and_hpc_accelerators_disruptive_technologies_in_the_making/#respondSat, 18 Jun 2011 07:00:00 +0000http://www.hpcwire.com/?p=4808At this week's International Supercomputing Conference in Hamburg, Germany, two of the biggest topics on the agenda are heterogeneous architectures and GPU/accelerator computing. Those emerging trends are joined at the hip, thanks mostly to the efforts of NVIDIA and their industry partners. Intel's ongoing plans for its Many Integrated Core (MIC) co-processor and AMD's introduction of its CPU-GPU "Fusion" processors are yet additional indications that the industry is moving to an architecture where CPUs married to accelerators will provide the next big seismic shift in high performance computing.

]]>At this week’s International Supercomputing Conference in Hamburg, Germany, two of the biggest topics on the agenda are heterogeneous architectures and GPU/accelerator computing. Those emerging trends are joined at the hip, thanks mostly to the efforts of NVIDIA and their industry partners. Intel’s ongoing plans for its Many Integrated Core (MIC) co-processor and AMD’s introduction of its CPU-GPU “Fusion” processors are yet additional indications that the industry is moving to an architecture where CPUs married to accelerators will provide the next big seismic shift in high performance computing.

And just in time. The HPC community has known for awhile that conventional CPUs, at least in their x86 form, will not be a practical path to exascale computing. That’s not just academic theory. HPC vendors and users have come to realize that commodity CPU-based computing, even with multicore parallelism, can only go so far, performance-wise.

But is the emerging HPC heterogeneous architecture with discrete GPUs or Intel MIC co-processors just another dead end as well? That’s what we set to find out in a recent conversations with John Shalf, who heads up the Advanced Technologies Group at the National Energy Research Scientific Computing Center (NERSC) in Berkeley, California. Shalf has given a lot of thought to this new computing paradigm, and at ISC’11 he’ll be moderating a panel entitled Heterogeneous Systems & Their Challenges to HPC Systems.

Like all HPC researchers, Shalf is well aware of the impact of general-purpose GPUs and other accelerators in the supercomputing realm. And while he believes heterogeneous architectures will be the future of HPC, he is skeptical of the current implementations. Shalf has two main objections to the today’s model: 1) the awkwardness of the accelerator as an external processor and 2) what he sees as significant shortcomings in the available programming models.

Like many in the industry, Shalf thinks relegating the accelerator to an external PCI device negates a lot of the performance advantages inherent in vector-like processors. The problem is that the time taken to transfer data between main CPU memory and local memory on the accelerator card via a relatively slow PCI Express (PCIe) connection can nullify any performance advantages gained by offloading the CPU. In essence, this has cast the co-processor as an I/O device.

But it’s not just a performance issue. The external accelerator setup also drives Shalf’s larger criticism — that of the programming model. Having separate memory spaces for the CPU and accelerator means the application has to account for moving data back and forth between processors. And in Shalf’s estimation, performing this data shuffle across the PCIe bus is tedious, error-prone, and complicates algorithm design.

On that last point, because data management is so critical to accelerator performance, the associated code often must be intermingled with the algorithm itself. In fact from Shalf’s perspective, the lack of a unified memory space is a much larger issue than the difficulties entailed in porting codes to CUDA, OpenCL, OpenMP, or any other kind of parallel programming framework. “My concern with accelerators hanging off of PCI Express is that they distract us from the core issue of expressing parallelism.”

Then there are the programming models themselves. Although Shalf recognizes that NVIDIA’s CUDA programming environment is the most established and the most performance-friendly software environment for GPU computing, it is by definition, proprietary. “Anybody who has any history in computing has very little stomach for single-vendor solutions,” he says.

OpenCL, on the other hand, is a hardware-independent, but not as mature as CUDA, and is unproven for performance-critical applications. Compiler directives offer a higher level framework, but as we’ll see in a moment, it has its own challenges.

Despite those reservations, there have been GPU computing success stories at Shalf’s NERSC. In particular, scientists with quantum chromodynamics (QCD) and quantum chemistry applications have hand-coded the underlying algorithms in CUDA and are enjoying some nice application speedups. In these cases, the codes are reasonably compact and amenable to GPU porting, so the programming effort is within the reach of small teams of developers.

For larger more complex legacy codes, the compiler directives approach offers a higher level alternative for programming accelerators. In this case, special directives are inserted into C or Fortran source to instruct the compiler to generate low-level instructions for the accelerator. The nice feature here is that such directives are ignored by compilers that don’t support them. So as long as the original source code around the directives can be left alone, the application can be transferred from target to target, with just a recompilation.

PGI and CAPS enterprise have commercial compiler products for GPUs based on their own directive schemes, and the OpenMP group is developing an open-standards version for accelerators. All have the advantage of allowing developers to build on top of existing high-level source code, while maintaining some semblance of hardware independence.

But according to Shalf, the performance results on GPUs for existing directives implementations have not been promising thus far. Some of this has to do with the fact the directives don’t address on-chip data stores (non-cache coherent shared memory and registers), which need to be explicitly managed for optimal performance. That management is level up to the intelligence of compilers, and Shalf is skeptical that they can deliver this level of sophistication.

Furthermore, the directives only partially hide the data management problem, so the application programmer will still be saddled with this distraction. OpenMP-supported compilers for the Intel MIC platform may yield better results, but that work is in its preliminary stages.

As far as maintaining target independence, from what Shalf has seen, the application of these directives tends to mangle the application source. As a result, in many cases it won’t be possible maintain separate code bases for CPU-only and various accelerator versions, negating one of the main advantages of this approach. Shalf says the current joke going around the community is that the total amount of text in the accelerator directives exceeds the amount of source code that you’re applying those directives to. “The environment is just not ready for the average user to hop onboard,” he says.

Fortunately, the accelerator chip vendors seem headed toward integrated CPU-accelerator processors, doing away with the PCIe bus performance limitations and the associated memory management. AMD is furthest along in this regard with its Fusion processors, although the first iterations announced this year are all aimed at client-side computing. NVIDIA’s “Project Denver” aims to marry ARM CPUs with future GPU cores in the 2013-2014 timeframe and will address server and HPC platforms. Intel has not publicly stated its intentions to have its MIC co-processor sharing silicon with Xeons, but given NVIDIA’s and AMD’s plans, Intel is almost certainly considering a future heterogeneous x86 chip.

Heterogeneous processors are nothing new to HPC. For example, in classic vector-based supercomputers like the Cray 1, the processor was a heterogeneous mix of distinct scalar and vector units. The reason nobody talked about the vector component as an accelerator was because both units shared the same memory space. But unlike the custom design of the Cray 1 processor, the new breed of heterogeneous chips will be based on commodity architectures — x86, ARM, and NVIDIA or AMD GPUs.

When fat cores (the CPU) and thin cores (the accelerator) are integrated, their roles could become reversed in some sense. According to Shalf, the accelerator cores should be devoted to the application, since they are much more efficient at pure computation, sequential or parallel. He thinks the fat cores should be used primarily for operation system functions; these are infrequent occurrences, but ones that require a lot of energy and time. “It completely breaks the old paradigm,” says Shalf.

As these specialized units become integrated into the processor, the notion of accelerators could fade away entirely. Just as floating point units and memory management units were swallowed on-chip, the accelerator would just become another processor component. At that point, compilers would have a much easier time of making the accelerator invisible to the application developer. And for them, that’s the Holy Grail.