Abstract

Several image coding and compression schemes based on Mathematical Morphology have been documented in the literature including: morphological skeleton coding [1], multiresolution analysis [2], morphological pyramid coding [3,4], morphological subband coding [5,6], and segmenta­tion-based coding using the watershed transform [7,8]. The advantages of the morphological approach over more traditional linear methods are: low computational com­plexity, inherent parallelism, and elimination of the ring­ing and blurring associated with linear techniques such as linear subband coding and transform coding using the dis­crete cosine transform (the latter is used in JPEG and MPEG). Morphological compression algorithms rely on two basic transformations: the dilation and the erosion. Hardware implementation of these operations is needed to realise the computational speed required for the real time processing of video. This paper proffers specifications for a video rate VLSI processor and examines the throughput and organisation for an implementation in 0.5 um GaAs technology.

Abstract

Several image coding and compression schemes based on Mathematical Morphology have been documented in the literature including: morphological skeleton coding [1], multiresolution analysis [2], morphological pyramid coding [3,4], morphological subband coding [5,6], and segmenta­tion-based coding using the watershed transform [7,8]. The advantages of the morphological approach over more traditional linear methods are: low computational com­plexity, inherent parallelism, and elimination of the ring­ing and blurring associated with linear techniques such as linear subband coding and transform coding using the dis­crete cosine transform (the latter is used in JPEG and MPEG). Morphological compression algorithms rely on two basic transformations: the dilation and the erosion. Hardware implementation of these operations is needed to realise the computational speed required for the real time processing of video. This paper proffers specifications for a video rate VLSI processor and examines the throughput and organisation for an implementation in 0.5 um GaAs technology.