SP8695 Counter

SP8695 200 MHz Divide by 10/11 Counter

Features

Quick Reference Data

Supply Voltage: +5.0V

Power Consumption: 80mW

Maximum Input Frequency: 200MHz

Description

The SP8695 is a low power ECL counter with both ECL 10K and TTL-compatible outputs. They divide by 10 when either control input in the high state and by 11 when both are low (or open circuit). The inputs are ECL II compatible but can also be AC coupled. An open collector output is provided for interfacing to TTL or CMOS.

Operating Notes

The clock inputs can be driven by ECL II, III and 10K. The input reference voltage (-3.8V at 25°C) is also compatible with ECL II, III and 10K over the specified temperature range. The inputs can also be capacitively coupled by the addition of external bias as shown in figure 6. Each input has an internal pull-down resistor of 10k, and unused inputs can, therefore, be left open circuit. They should be bypassed to RF where maximum noise immunity is required.

The PE control inputs are similarly ECL III/10K compatible and also have an internal 10k pull-down resistor, allowing unused inputs to be left open circuit if required.

The two Q4 ECL outputs have internal circuitry equivalent to a 14k pull-down resistor on each output and are ECL II compatible: they can, however, be interfaced to ECL III/10K as shown in figure 8.

The circuit operates down to DC, but slew rate must be better than 5V/µs.

The input impedance of SP8695 varies as a function of frequency.

The TTL/CMOS output has a free collector, and the high state output voltage will depend on the supply that the collector load is taken to. This should not exceed 12V. The rise and fall time of the open collector output waveform is directly proportional to load capacitance and load resistance value. Therefore load capacitance should be kept to a minimum, and the load resistor kept to a minimum compatible with system power requirement.