The Week In Review: Design

Synopsysdebuted a tool to replay RTL simulation data on a gate-level netlist for power analysis the company says is accurate within 5% of signoff. The tool, PowerReplay, is design to be used in combination with PrimeTime PX gate-level power analysis for earlier and faster generation of gate-level switching data.

IP

ClioSoftlaunched a design reuse ecosystem for searching and comparison of IP throughout a company, as well as related information such as SoC sub-systems, documents, scripts, and flows. The designHUB ecosystem, hosted within the company, also provides a platform for designers to communicate with IP/SoC developers.

Imaginationuncorked the first GPU IP core based on its new PowerVR Furian architecture. The Series8XT GT8525 is a two cluster GPU that shows 50%-80% improvement in various benchmarks over the previous series’ equivalent. The new architecture includes a number of completely changed blocks, changes for shorter path lengths with less congestion, and a move from an x16 to x32 ALU pipeline. The GPU is targeted at smartphones, AR/VR headsets and automotive.

The latest generation of Andes’ AndeStar architecture supports 64-bits as well as the RISC-V ISA as its subset. The company says the V5 NX25 core in a typical configuration will deliver over 1GHz (in “worst case” conditions) with area of 67K gates and power consumption as little as 17 µW/MHz in a TSMC 28nm process.

SiFiveunveiled two commercial RISC-V cores. The 32-bit E31 Coreplex IP is targeted at IoT, wearables, and embedded microcontrollers. The 64-bit E51 embedded processor is targeted as a host control core within a larger 64-bit SoC and has an extended memory map of 40 physical address bits. Both deliver up to 1.5 GHz in 28nm and have royalty-free licensing.

Embedded FPGA IP company Flex Logixsecured $5 million in Series B equity financing, led by existing investors Lux Capital and Eclipse Ventures, with participation from the Tate Family Trust. The company plans to use the funds to expand its sales, applications and engineering teams.

SiFiveraised $8.5 million in a Series B round led by Spark Capital with participation from Osage University Partners and existing investor Sutter Hill Ventures. The company offers RISC-V SoCs, development boards, and IP.