Vertical 3D NAND Possible by 2013-2014

Vertical 3D NAND Possible by 2013-2014

By David Lammers, SemiMD

The advent of 3D NAND memories may be only two or three years away, speakers said recently at SEMICON West 2011 (July 12-14) in San Francisco. By 2013 the major memory companies developing 3D NAND, including Hynix, Samsung, and Toshiba, may be ready with pilot lines, moving to volume production a year or so later. Taiwan-based Macronix International also has been developing a 3D NAND solution.

The increasing emphasis on 3D NAND comes as the cost of advancing planar 2D NAND to the next technology node — lithography in particular — may be prohibitive. 3D NAND could come in with a 55nm half pitch, possible using a dry lithography toolset. And the basic steps are fairly straightforward. With Samsung’s TCAT process flow, for example, multiple oxide and nitride deposition layers are stacked. Then the silicon nitride is removed by a wet etch process, followed by a tungsten fill for the bit and word lines and contacts.

Fusen Chen, executive vice president at Novellus Systems Inc., said the 2D planar NAND architectures are at the 20nm node this year, moving to 1X technologies by 2013. That will require either self-aligned quad patterning with 193nm immersion scanners, or EUV lithography – in his view both “very expensive solutions.”

There also are materials challenges to scaling today’s planar NAND. A 1X planar NAND technology requires floating gate shaping and air gap engineering to deal with the parasitic capacitance coupling challenge, said Gil Lee, a senior director at Applied Materials who has worked for several memory manufacturers. Also, 2D NAND faces inter-poly dielectric scaling issues, requiring decoupled plasma nitridation to form the NONON dielectric.

“When 3D goes into production depends on how far they can push 2D planar technology,” Lee said, adding that the “migration to 3D NAND revives the scaling roadmap again.”

To avoid the high lithography costs, Chen said 3D NAND “will start in earnest in 2013.”

Bart van Schravendijk, a senior fellow at Novellus, said that by 2013 the NAND makers will need double or quad patterning, either with or without EUV. “The concern is that EUV plus SADP will be very costly. 3D NAND does not depend on lithography scaling. And TSVs are coming to NAND,” he said during a presentation at a TechXPOT session on emerging memory architectures.

While the NAND vendors are “very serious about 3D, there are a lot of challenges leading up to commercialization,” van Schravendijk said.

Each of the major memory companies has a different approach to a vertical channel NAND. Toshiba and Samsung prefer a charge-trapped flash technology, while Hynix is developing a vertical floating-gate structure. The various vertical NAND approaches employ either a gate-first or gate-last process flow.

At the TechXPOT session both Lee and van Schravendijk outlined the major challenges facing vertical NAND.

Lee said multi-layer stack deposition requires low-cycle-time PECVD deposition, while the high aspect ratio etch requires high mask selectivity. Also, slimming of the control gate requires good control of the anisotropic slimming etch step. The high aspect ratio gap fill requires a highly flowable CVD film.

Lee said Applied’s technologists believe single-wafer processing in one station to be the most-effective solution for deposition, where very smooth films with an RMS of less than one nanometer are required. Etching the 16-layer staircase contact structure, with a sufficient landing area for the contacts, requires an 80:1 aspect ratio contact area. The critical dimension control required is better than the lithographic CDs, and calls for very high throughput rates.

Van Schravendijk said 3D multi-layered structures require excellent etch profile control, deposition of atomically smooth films, and improved tungsten fill. Wafer bow control, particles, and cost also are among the issues. “3D can be low cost if we can quickly switch between oxynitride — without particles — and silicon nitride deposition. We must have good oxide selectivity,” he said. Unlike the move to EUV for 1X 2D NAND, the good news is that “with 3D they don’t have to change the toolset. 3D is “no longer linked by litho.”

Enticed by a shift from a lithography capital intensive 2D flow to a deposition and etch intensive approach, the major equipment vendors are paying close attention to 3D NAND equipment development.

Girish Dixit, a Novellus vice president of process applications, said 3D NAND was one of the central themes at this year’s VLSI Symposium on Technology, held in Kyoto, Japan in early June. A panel discussion on memory technology, Dixit said, concluded that 3D NAND would emerge in pilot lines in 2013.

“There is a lot of activity in this area, partly because companies are facing limits on scaling today’s floating gate NAND. Companies are looking at how difficult it is to get the reliability and endurance their customers need at the 1X node with floating gate planar memory cells. And to scale planar memories, they will need to go to quad patterning or EUV,” he said.

In a recent Toshiba press release announcing readiness of a new line at its Yokkaichi fab complex, Toshiba said the new fab would be used for leading edge planar NAND as well as 3D flash memories, which the company referred to as “post-NAND flash memory.”

Chen said the 2D planar architecture may run out of steam at the 128 gigabit or 256 gigabit densities. With a 3D approach, the design rules are relaxed to 55 nm and “there is not an added layer of lithography – you can pattern all the bits in one shot.”

The challenge shifts to the deposition and etch steps. “Memory companies have to be able to etch the nitride selectively back to the oxide layer. To do that, they must engineer the material properties so they get the right interface, 64 times, with less than one defect.”

Chen said 3D NAND technology, looked at from a high level, involves stacks of oxide and nitride films. The nitride film is etched away and replaced with tungsten, leaving an oxide layer to separate the two bits.

“The 32 layers need to be very smooth, with better than 1 percent uniformity while eliminating all air bubbles,” Chen said.

Dixit said 3D NAND is “definitely not five years away. Before the VLSI conference, some people thought it was five or six years away. Now, the expectation is that it is only two to three years out,” he said.

Tim Archer, the chief operating officer at Novellus, said NAND costs dropped rapidly from 2000 to 2008. Since then, bit cost reductions have become more difficult to accomplish. By moving to 3D NAND, memory companies will avoid high lithography costs and be able to move to a smaller die size, albeit one with multiple vertical layers of memory cells.

Rather than adopt 16nm technology with multi-level-cell (MLC) NAND, memory vendors could turn to 55nm technology with 32 pairs of bit cells. “That will give the 3D NAND vendors a huge cost advantage. With that we will start to see a massive conversion to solid-state disk drives,” Archer said at SEMICON West.

This article was originally published in Semiconductor Manufacturing and Design (SemiMD), which deals with the complex technology and business issues in manufacturing and designing semiconductors. David Lammers is the editor-in-chief of SemiMD, which is a joint venture of Sperling Media Group LLC and Extension Media LLC.