This class provides, within an electrical computer or digital
data processing system, for the following subject matter:

A. Processes and apparatus for addressing memory wherein the processes and apparatus
involve significant address manipulating (e.g., combining, translating, or mapping
and other techniques for formatting and modifying address
data) and are combined with specific memory configurations or memory systems;

(1)Note. In the instance where a peripheral is a memory, classification herein
is proper.

(2)Note. Classification herein requires more than nominal
recitation of addressing techniques or of memory accessing
or controlling in combination with digital data processing
systems or data processing. A nominal
combination refers to a combination wherein one or more of the means
or steps thereof are recited so broadly, and without details, as
to constitute a mere identification rather than a description of each
means or step.

(4)Note. Processes and apparatus for transferring data between memories of
different computers directly (i.e., with
minimum or no intervention from main processors of
the computers) are classified
elsewhere. See the SEARCH CLASS notes below.

(5)Note. Processes and apparatus for direct memory
access (DMA) (i.e., the
transferring of data between peripherals and memories of
a computer or digital data processing system with minimal or
no intervention from the main processor of
the computer or digital data processing system) are classified
elsewhere. See the SEARCH CLASS notes below.

(6)Note. Processes and apparatus for accessing and
retrieving instruction data of a
fixed or variable length from a memory or
buffer and for shifting such instruction data to align
it with a physical memory or buffer boundary
are classified elsewhere. See the SEARCH CLASS notes below.

Registers, various subclasses for basic machines and associated
indicating mechanisms for ascertaining the number of movements of
various devices and machines; machines made from these
basic machines alone (e.g., cash
registers, voting machines) and in combination
with various perfecting features such as printers and recording
means; and various systems controlled by data bearing records (e.g., smart
cards).

Communications: Electrical,
subclasses 1.1 through 16.1for controlling one or more devices to obtain a
plurality of results by transmission of a designated one of plural
distinctive control signals over a smaller number of communication
lines or channels, particularly subclasses 2.1-2.8
for path selection, subclass 2.81 for tree or
cascade selective communication, subclasses 3.1-3.9
for communication systems where status of a controlled device is communicated, subclasses
4.1-4.14 for synchronizing selective
communication systems, subclasses 9.1-9.17
for selective communication addressing, subclasses 12.1-12.55
for pulse responsive actuation, and subclasses 14.1-14.69
for selective decoder matrix.

Coded Data Generation or Conversion, various subclasses for electrical pulse and digit code
converters (e.g., systems for
originating or emitting a coded set of discrete signals or translating
one code into another code wherein the meaning of the data remains the same but formats may
differ).

Facsimile and Static Presentation Processing,
subclasses 1.16and 1.17 for process and apparatus (e.g., printer) that
includes memory for processing data for static presentation (i.e., for viewing
on a fixed medium such as paper).

Dynamic Magnetic Information Storage or Retrieval, (which is an integral part of Class 369 following
subclass 18), for record carriers and systems
wherein data are stored and retrieved
by interaction with a medium and there is relative motion between
a medium and a transducer (e.g., magnetic
disk drives, tapes, and drums and control thereof, per
se), particularly subclasses 72.1+ for
locating a specific area in storage.

Static Information Storage and Retrieval, various subclasses for static memory devices including
internal elements of the memory, particularly
subclass 189.011for read/write circuits and subclasses
230.01+ for addressing of addressable, static
single storage elements or plural elements; subclass
189.05 for buffering or latching data being
read from or written to memory; subclass
189.08 for logic devices in combination with memory systems; subclasses 200
and 201 for testing of memory systems; and
subclass 230.08 for buffering and latching address data being employed to access memory.

Dynamic Information Storage or Retrieval, various subclasses for record carriers and systems wherein
data are stored and retrieved by interaction with a medium and there
is relative motion between a medium and a transducer (e.g., optical
disks, CD-ROMs, jukeboxes), particularly
subclasses 30.01 through 41.01,69, and 176-271 for designating
or selecting storage media to be used for storage and retrieval.

Multiplex Communications, appropriate subclasses for multiplex switching techniques
similar to addressing and the handling of memory information signals
and for the simultaneous transmission of two or more signals over
a common medium, particularly 351 for time division multiplex (TDM) switching,
subclass 395.7for an ATM network with detail of storage access
and control, subclasses 475+ for asynchronous
TDM communications including addressing, and subclasses
498+ for time division bus transmission.

Electrical Computers And Digital Data Processing
Systems: Input/Output,
subclasses 1+ for transferring data from one or more peripherals
to one or more computers for the latter to process, store, or
further transfer or for transferring data from the computers to
the peripherals, particularly subclasses 22+ for
direct memory access (DMA) (i.e., the
transferring of data between peripherals and memories of a computer
or digital data processing system with minimal or no intervention
from the main processor of the computer or digital data processing
system).

The terms below have been defined for purposes of
classification in this class and are shown in underlined
type when used in the class and subclass definitions. When these
terms are not underlined in the definitions, the meaning
is not restricted to the glossary definitions below.

This subclass is indented under the class definition. Subject matter comprising means or steps for determining
one or more values (i.e., address data) that specify one
or more locations in a storage medium wherein the means or steps
are claimed in combination with a particular configuration or system
for storing data.

(1)Note. Classification herein requires significant
address manipulating (i.e., more than
nominal recitation of an addressing technique). Significant
address manipulating is exemplified by address
dataprocessing functions
such as combining, translating, mapping, and
other techniques associated with forming or modifying address data.

(2)Note. Means or steps for determining a value that
specifies a memory location (i.e., address data) must include more than
nominal recitation of processing functions
and memory components for classification
herein.

(3)Note. This subclass and those indented below provide
for combinations of data processing, particular memory systems, and significant address data manipulating. Generalized
addressing in a digital data processing system is
classified elsewhere in this class. See the SEARCH THIS
CLASS, SUBCLASS notes below.

(4)Note. This subclass and those indented below may
include means (e.g., processor, controller, etc.) or
steps for control of a memory of
a digital data processing system in
combination with memory accessing (e.g., reading, writing). Memory accessing and control for specific memory compositions, hierarchical memory configurations, and shared memory, however, is
classified elsewhere. See the SEARCH THIS CLASS, SUBCLASS
notes below.

(5)Note. Means or steps for accessing and controlling
plural memory configurations (e.g., data farms, "library" systems) that
include significant data processing are
classified herein. Control systems for delivering storage
media (e.g., delivery of robotics
or automated tapes or cartridges, selection and delivery
of platters), however, are properly classified elsewhere
under automated control or another appropriate subclass in the respective
device, robotics, and generic control classes. In
instances involving significant data processing and
significant details of media delivery systems, classification
herein is proper.

Static Information Storage and Retrieval,
subclasses 189.011for read/write circuits, and
subclasses 230.01+ for addressing of addressable, static
single storage elements or plural elements of the same type.

Dynamic Information Storage or Retrieval,
subclasses 30.01 through 41.01,69, and 176-271, as appropriate, for
subject matter related to designation or selection of storage medium to
be used for storage and retrieval.

Data Processing: Database, Data
Mining, and File Management or Data Structures,
subclasses 781 through 789for access control to a database or file in a
computer environment and subclasses 790 through 812 for database
design including data structures and data structure management, subclasses
813 through 820 for garbage collection in database environments and
subclasses 821 through 831 for file management, file systems
and file directory structures.

This subclass is indented under subclass 1. Subject matter wherein addresses are determined for memory not normally accessible by a base
operating system, computer, or digital data processing system components.

(1)Note. Classification here may include virtual addressing
techniques; however, virtual memory addressing
art which deals with logical addressing techniques as opposed to
addressing for physical enhancements, such as extended
and expanded memory, is
classified elsewhere in this class.

This subclass is indented under subclass 1. Subject matter wherein addresses are generated for memory nearest a processor in
a hierarchical memory arrangement (i.e., a
cache memory arrangement).

(1)Note. This subclass accommodates particular addressing
techniques for cache memory systems. Cache memory accessing and control (i.e., reading
and writing) are classified elsewhere in this class. See
the SEARCH THIS CLASS, SUBCLASS notes below.

This subclass is indented under subclass 1. Subject matter wherein address schemes are particular to
a data storage device requiring
relative motion between a data holding
medium and a recording mechanism such as disk, tape, or
drum memory.

Dynamic Magnetic Information Storage or Retrieval, which is an integral part of Class 369, following
subclass 18, for record carriers and systems wherein information is stored and retrieved by
interaction with a medium and there is relative motion between a
medium and a transducer (e.g., magnetic
disk drive devices and control thereof, per se). See
Class 360, subclass 72.2 for addressing and control
of recording mechanism to locate the selected area.

Dynamic Information Storage or Retrieval, various subclasses for record carriers and systems wherein information
is stored and retrieved by interaction with a medium and there is relative
motion between a medium and a transducer. Particularly, see
subclasses 30.01 through 41.01for selective addressing of dynamic storage medium.

This subclass is indented under subclass 1. Subject matter wherein addresses are determined in a memory
system accommodating addressing requirements for software emulation
of a target computer or digital data processing system on a base
computer or digital data processing system.

This subclass is indented under the class definition. Subject matter comprising means (e.g., a processor, a controller, etc.) or
steps for governing memory in a computer or digital
data processing system or the passage (e.g., reading, writing) of data thereto.

(1)Note. The subject matter of this subclass and the
subclasses thereunder provides for details of how memory is
accessed and controlled. Classification herein requires
more than nominal recitation of accessing or controlling memory in the context of digital
data processing systems or data
processing. Examples of significant memory accessing and control data processing include transferring and
modifying memoryaddress
data, selecting memory devices
or memory locations, and
scheduling memory accesses.

(3)Note. Subject matter classified herein may include
nominal recitations of address data generation, manipulation, and
modification. Combinations of a particular memory construct (e.g., cache) with
accessing and control and significant addressing as exemplified
by data processing functions such
as combining, translating, mapping, and
other techniques associated with forming and modifying addresses, however, are
classified in superior subclasses directed to such combinations.
See the SEARCH THIS CLASS, SUBCLASS notes below.

(4)Note. Classification herein requires more than nominal
recitation of means or steps for controlling memory.

(5)Note. This subclass and the subclasses thereunder
also provide for subject matter wherein static or dynamic storage forms
part of a digital data processing system.

(6)Note. Subject matter classified herein may include
nominal recitations of reliability and availability in combination with memory accessing and control. The species
of reliability and availability related to data archiving, backup, and device
access limiting and security combined
with memory accessing and controlling
is classified herein. Other species of reliability and
availability combined with memory accessing
and controlling are classified elsewhere. See the SEARCH
THIS CLASS, SUBCLASS notes below.

(7)Note. Memories known
as display memory, display
buffers, frame buffers, VRAMs, etc., functioning
in combination to store image data for
image processing are properly classified elsewhere. Subject
matter for interfacing between a graphics processor and
a memory is classified elsewhere.
See the SEARCH THIS CLASS, SUBCLASS notes and SEARCH CLASS
notes below for the information handling
subclasses relevant to memories acting on display data.

(8)Note. Means or steps for accessing and controlling
plural memory configurations (e.g., data farms, "library" systems, etc.) including
significant data processing are
classified here. Details of control systems for medium
delivery such as robotics or automated tape, cartridge, and
platter selection and delivery, however, are properly
classified elsewhere under automated control or another appropriate
subclass in the respective device, robotics, and
generic control classes. In instances where there is significant data processing and significant details
of medium delivery systems, classification should be based
on the hierarchy of classes and classified here.

(9)Note. This subclass is directed to generic memory
accessing and control. Database accessing and retrieval
is classified elsewhere. See the SEARCH THIS CLASS, SUBCLASS
notes below.

Communications: Electrical,
subclasses 1.1 through 16.1for controlling one or more devices to obtain a plurality
of results by transmission of a designated one of plural distinctive control
signals over a smaller number of communication lines or channels, particularly
subclasses 2.1-2.8 for path selection, subclass
2.81 for tree or cascade selective communication, subclasses
3.1-3.9 for communication systems where
status of a controlled device is communicated, subclasses 4.1-4.14
for synchronizing selective communication systems, subclasses 9.1-9.17
for selective communication addressing, subclasses 12.1-12.55
for pulse responsive actuation, and subclasses 14.1-14.69
for selective decoder matrix.

Computer Graphics Processing and Selective Visual
Display Systems,
subclasses 530 through 574for memory organization and structure for storing
images to be displayed and subclasses 531-574 for interfacing between
a graphics processor and a memory.

Dynamic Information Storage or Retrieval,
subclasses 30.01 through 41.01,69, and 176-271, as appropriate, for
subject matter related to designation or selection of storage medium to
be used for storage and retrieval.

Multiplex Communications, for the simultaneous transmission of two or more signals
over a common medium, particularly
subclasses 351+ for time division multiplex (TDM) switching, subclasses
475+ for asynchronous TDM communications including addressing, and
subclasses 498+ for time division bus transmission.

Electrical Computers and Digital Data Processing
Systems: Input/Output,
subclasses 1+ for combinations of data transfers performed by
a peripheral (e.g., I/O
processors, DMA, I/O controllers, I/O
adapters, etc.) between digital data
processing systems or computers and peripherals; subclasses
22+ for Direct Memory Access (DMA) or
direct data transfers to or from memory or to or from other peripherals
and for data transfers performed by a peripheral between external
components such as disk drives, peripheral devices, etc., which involves
I/O processing; and subclasses 100+ for
connections within a single computer or digital data processing
system arrangement such as interfacing, bus arbitration, bus expansion.

Electrical Computers and Digital Processing Systems: Processing
Architectures and Instruction Processing (e.g., Processors),
subclasses 220+ for processing control and instruction processing, per
se, which often includes access to registers surrounding
functional units of a processor.

This subclass is indented under subclass 100. Subject matter wherein control of the memory or
the accessing thereof is adapted to the type of memory being
accessed.

(1)Note. Structures and particulars of the memory device itself are classified in
the relevant device class.

(2)Note. Subject matter included herein is directed
to the specifics of accessing technique employed to access and control
the memory by computers, digital data processing systems, processors, or other users.

(3)Note. The nature of data stored
in a memory (i.e., the information) does not make the memory "specific" within
the context of this and its indented subclasses (e.g., video
or image data, printer buffer, control datamemory, etc.).

(4)Note. Accessing and controlling of a multiport memory, per se, are
classified elsewhere in this class. See the SEARCH THIS
CLASS, SUBCLASS notes below.

Dynamic Information Storage or Retrieval,
subclasses 30.01 through 41.01,69, and 176-271, as appropriate, for
subject matter related to designation or selection of storage medium to
be used for storage and retrieval.

This subclass is indented under subclass 105. Subject matter including specifics of coordinating refreshing
operations with other system operations.

(1)Note. This subclass is proper for subject matter
directed to coordinating refresh scheduling with other system events, accesses, requirements, etc., external
to the memory cells. However, coordinating
the timing requirements within a memory cell
or composite thereof is classified elsewhere. See the
SEARCH CLASS notes below.

This subclass is indented under subclass 101. Subject matter comprising arrays of magnetizable rings as
the individual storage elements.

(1)Note. In the 1960"s the term "core memory" referred exclusively
to memory with ferrite cores. Also
at that time, the main memory of
large systems were exclusively of this type. As the art
progressed, the term core memory became
a holdover to refer to the system"s main memory, regardless
of the actual type of memory being
used. Therefore, if core memory is
claimed, the specification should be checked to see if
the memory is indeed core memory (i.e., ferrite memory) for classification here; otherwise, it should
be treated as solid-state memory and
classified elsewhere.

This subclass is indented under subclass 101. Subject matter including memory of
the type where elements are arranged to serially pass the stored
contents from one location to an adjacent location, or
for use in data format conversion
within a digital data processing system.

(1)Note. Employing shift registers as part of the system memory for transferring data within
a digital data processing system is
classified here; however, the specifics of the
interconnections and control of shift register memories is
classified elsewhere. See the SEARCH CLASS notes below.

(2)Note. Although data format
conversion may form part of the overall combination in this subclass, data format conversion, per se, is
classified elsewhere. See the SEARCH CLASS notes below.

This subclass is indented under subclass 109. Subject matter wherein the contents of a register may be
passed in a recirculating fashion among a group of adjacent registers (e.g., ring buffers, barrel
shifters, etc.).

This subclass is indented under subclass 101. Subject matter including accessing memory of the
type where a storage medium is moved relative to a transducer (e.g., magnetic
or paper tape, punched cards, etc.).

(1)Note. This and indented subclasses provide for dynamic
storage combined with significant digital data
processing system elements and functions.

This subclass is indented under subclass 112. Subject matter where a plurality of direct access devices
are arranged in an array and files or portions thereof are stored
on more than one of the direct access storage devices.

(1)Note. This subclass is appropriate for redundant
arrays of inexpensive disks (RAID).

(2)Note. See the (6) Note to subclass
100 for systems directed to reliability and availability of DASDs. See
the SEARCH CLASS notes below.

This subclass is indented under subclass 101. Subject matter wherein the memory is
of the solid-state type and can be readily physically connected
and disconnected manually, without the aid of any tools, for
temporary or transient purposes (e.g., replaceable memory cartridges, smart cards, etc.).

This subclass is indented under subclass 101. Subject matter wherein the memory is
of the solid-state type comprising one or more series of
persistent microscopically small magnetized bubbles on a thin film
substrate.

This subclass is indented under subclass 119. Subject matter further comprising means or steps for employing
plural cache memories arranged at
the same ordinal level between at least one processor and
at least one main memory.

This subclass is indented under subclass 119. Subject matter further comprising means or steps for employing
plural cache memories where at least one of the caches is exclusively associated
with a respective one of a plurality of processors.

This subclass is indented under subclass 119. Subject matter further comprising means or steps for caching
at a plurality of different hierarchical levels (e.g., main
cache coupled to an on-chip cache).

This subclass is indented under subclass 119. Subject matter further comprising means or steps for employing
separate or partitioned cache(s) for separately
storing portions of instruction data and user data, respectively.

(1)Note. This physical separation of instruction
data and user data is
often referred to as Harvard architecture in the art and associated
literature.

This subclass is indented under subclass 119. Subject matter wherein an individual cache system must announce
to other cache systems or check with other cache systems which may possibly
contain a copy of a given cached location prior to or upon modification
or appropriation of data at a given
cached location.

This subclass is indented under subclass 118. Subject matter further comprising organizing a cache system
where any block in main memory can
be mapped to any block in the cache (fully associative) or
where the cache is divided into sets of blocks and individual blocks
of main memory are mapped to any
of the blocks of a particular corresponding set (that is, for
example, set associative).

This subclass is indented under subclass 118. Subject matter further comprising means or steps not specifically
covered above for assuring that the data stored
in the cache memory and those of
the main memory are either identical
or controlled so that stale and current data are
not confused with each other.

(1)Note. The subject matter in this subclass is also
called cache consistency or cache currency in the art.

Data Processing: Presentation Processing
of Document, Operator Interface Processing, and
Screen Saver Display Processing,
subclasses 255 through 272for developing or changing a document wherein one
or more elements of document are added, deleted, or
modified, or including means or steps for storing the resultant
altered document or the alterations.

This subclass is indented under subclass 141. Subject matter where, as contents of the cache are
changed, the changes are not posted to main memory immediately, but rather
changes to a block are posted upon the occurrence of a predetermined
event.

This subclass is indented under subclass 141. Subject matter wherein coherency for each unit or block
of data includes associated identifier bit(s) to
indicate the validity status of an associated cached location.

This subclass is indented under subclass 141. Subject matter wherein each unit or block of memory or cache includes associated identifier bit(s) to
indicate ownership of or restricted access to the unit or block.

This subclass is indented under subclass 141. Subject matter further comprising cache memory monitoring
an associated address bus to determine
if access to a cached location occurs by another cache memory or other user (e.g., DMA, peripherals, etc.).

This subclass is indented under subclass 100. Subject matter wherein at least a portion of the memory being accessed or controlled is
solid-state memory that
iscommon to a plurality of users (e.g., a
CPU and a DMA controller, multiple CPUs, etc.) or
a plurality of tasks (e.g., in a
multitasking system) or both.

Electrical Computers and Digital Processing Systems: Multicomputer
Data Transferring or Plural Processor Synchronization,
subclasses 213 through 216for a plurality of computers transferring data
through one or more memories accessible by the plurality of computers.

Electrical Computers and Digital Processing Systems: Virtual
Machine Task or Process Management or Task Management/Control,
subclass 103for priority scheduling of process (e.g., deciding
which resources to use, deciding which jobs to do first
and what order to do them; scheduling constraints may include
resource characteristics such as performance, availability, data
coherency, etc.).

This subclass is indented under subclass 154. Subject matter including provisions for performing an access
operation where the contents of a given memory location
are read and then overwritten in a single access operation.

Error Detection/Correction and Fault Detection/Recovery,
subclass 1for diagnostic testing or monitoring of a digital
data processing system for reliability purposes comprising power fail-safe
functions, fault detection, or anticipation of
a failure; more specifically, subclasses 5.1
through 6.32 for memory or peripheral subsystem affected
recovery, subclass 42 for memory component fault, and
subclass 54 for storage content error detection or notification, subclasses 718-723
for reliability and availability in memory accessing and control
such as isolating failed memory and storing redundant data with
recitation of the recovery, fault, or failure.

Error Detection/Correction and Fault Detection/Recovery,
subclasses 5.1 through 6.32and subclasses 718-723 for reliability
and availability in memory accessing and control such as isolating
failed memory and storing redundant data with recitation of the recovery, fault, or
failure.

Electrical Computers and Digital Processing Systems: Support,
subclasses 182 through 186for system access control based on cryptographic
identification, and subclasses 187 and 188 for software
program protection or computer virus detection in combination with
data encryption.

This subclass is indented under subclass 154. Subject matter including provisions for moving or copying data from one location in a given memory to another location in the given memory or another memory at
the same hierarchical level.

Electrical Computers and Digital Processing Systems: Support,
subclasses 400+ for details relating to the timing control or timing
regulation of any one or combination of digital data processing
system components according to a periodic sequence of clock/ timing
pulses (e.g., synchronous time
control, time delay, cycle control, cycle
steal, etc.).

Electrical Computers and Digital Data Processing
Systems: Input/Output,
subclasses 8+ for assigning operating characteristics to peripherals
or peripheral configuring and subclass 104 for utilizing a hardware
structure for providing to a digital data processing system component
the arrangement of the digital data processing system including
characteristics of the digital data processing system"s components.

Electrical Computers and Digital Processing Systems: Virtual
Machine Task or Process Management or Task Management/Control, appropriate subclasses for task management, in particular
subclass 104for resource allocation (e.g., deciding
how best to use the available resources to get the job done) and
also subclasses 107 and 108 for multitasking and context switching.

(2)Note. The subject matter also includes deriving
new address data from existing address data.

(3)Note. The location in memory may include data for forming further an address (e.g., address
mapping is classified herein).

(4)Note. Means or steps for addressing or for storing data in one or more memory cells
of a storage medium having one or more specific, internal
cell elements is classified elsewhere. See the SEARCH CLASS
notes below.

Communications: Electrical,
subclasses 9.1 through 9.17for selective communication addressing and subclasses
14.1-14.69 for selective decoder matrix
which may be used for control or as a switching means.

Static Information Storage and Retrieval,
subclass 189.011for read/write circuits and subclasses
230.01+ for addressing of addressable, static single
storage elements or plural elements of the same type.

Dynamic Information Storage or Retrieval, various subclasses for record carriers and systems wherein information
is stored and retrieved by interaction with a medium and there is relative
motion between a medium and a transducer. Particularly, see
subclasses 30.01 through 41.01for selective addressing of dynamic storage medium.

This subclass is indented under subclass 200. Subject matter wherein the value determination takes into
account a memory size constraint.

(1)Note. This subclass will accept range or limit checking, boundary
crossing, and related memory boundary
issues (e.g., (a) handling
a boundary fixed length field to accommodate data size
or position and boundary checking and (b) incrementing
addresses within a page).

This subclass is indented under subclass 200. Subject matter including translating (i.e., converting) processormemoryaddress data to physical memoryaddress data through a mechanism which
defines a correspondence between the addresses.

(1)Note. The subject matter in this and the indented
subclasses is aimed at determining a physical address using a mapping
technique.

(2)Note. Classification here is proper for direct mapping
for a segmented memory not being
used in a virtual memory system.

This subclass is indented under subclass 203. Subject matter wherein means or steps are utilized for optimizing
address determination by, for example, anticipating
a next address or prefetching addresses.

This subclass is indented under subclass 204. Subject matter wherein a memory space
is employed for registering indexes and the like to real or physical
address spaces in a predicting or look-ahead arrangement.

(1)Note. A directory table is a mechanism for storing
virtual (i.e., logical) to
physical (i.e., real, absolute) address
translation entries that are used in combination with methods of
predicting or prefetching.

(2)Note. DLAT is a term of art referring to Directory
Look-Aside Table; TLB is a term of art referring
to Translation Look-Aside Buffer.

This subclass is indented under subclass 203. Subject matter wherein directories (e.g., maps) are
employed for converting address data in
a first form (e.g., virtual, logical) to address data in a second form (e.g., physical, absolute).

(1)Note. This subclass and its indented subclasses
are intended for generalized applications of tables not classifiable
in the combinations above.

(2)Note. This area also provides for mechanisms for
storing virtual (i.e., logical) to physical (i.e., real, absolute) address translation
entries that are of general use in virtual memory.

(3)Note. This subclass will accept table walking which
generally requires accesses to main memory.

This subclass is indented under subclass 206. Subject matter wherein a memory space
is employed for registering indexes and the like to real or physical
address spaces.

(1)Note. These mechanisms convert address
data from a virtual address to a physical address without
the need for accessing translation tables in main memory (e.g., utilizing
cache for virtual to physical translation).

(2)Note. DLAT is a term of art referring to Directory
Look-Aside Table; TLB is a term of art referring
to Translation Look-Aside Buffer.

This subclass is indented under subclass 200. Subject matter having a memory space
of general utility for registering indexes and like data related
to address generation (e.g., fixed
offsets, conditions, or status).

NOTE—E-subclasses in USPC Class 711/E12.001-E12.103
were created as duplicates of EPO groups in G06F 12/00
and its indents. With the implementation of CPC, these
E-subclasses should no longer be used. Instead, use
CPC groups in G06F 12/00 and its indents.

The E-subclasses in U.S. Class
711 provide for methods and apparatus for addressing or allocating
computer memory space including space management and address translation.
They also provide for methods and means for protecting against unauthorized
use of memory and protection against loss of memory contents.

ACCESSING, ADDRESSING, OR ALLOCATING
WITHIN MEMORY SYSTEMS OR ARCHITECTURES:

This main group provides for methods and apparatus for addressing
or allocating computer memory space including space management and
address translation. It also provides for methods and
means for protecting against unauthorized use of memory and protection against
loss of memory contents. This subclass is substantially
the same in scope as ECLA classification G06F12/00.

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