Tirupattur skillfully pulled both humorous and discriminating observations from the foundry perspective, the EDA perspective and both a large and small IP vendor.
The topic of the panel was the high cost and risk of integrating IP in today’s semiconductor product development. There’s a massive risk of product failure from choosing the wrong IP, the wrong supplier, the wrong fab, or the wrong process. A misstep means jobs could be on the line. Today, complex SoCs are not comprised of just one or two IP blocks, it’s a battalion of IP coming from a variety of sources. Dan Kochpatcharin of TSMC noted that at the 20nm node an average design has 12 unique IP blocks. That compares to an average of only eight at the 28nm node.

The IP selection process is complex and involves a lot of cost and risk. Types of IP include foundation IP from the fabs, standard-based IP, different custom IP and some internal customer-owned IP. Mixing it all together is where a lot of challenges begin. Every IP vendor says their IP is the best, it works, it’s been verified, and there is a team of engineers to back it up. But in reality the integration can be a nightmare. Customers not only have to spend a lot on the infrastructure and software just to make sure each IP is individually verified but they also have to make sure it works with other IP. This work involves huge cost and risk. Add to that the issue of time. As Chris Rowen, Cadence Fellow, pointed out, the industry is always racing against time.

There were two topics that the panel spent most of the time talking about: IP quality and raising the level of IP support to the application level. All players in the ecosystem are being forced to work more closely together and at an earlier point in the development cycle. Foundries are a key part of that development cycle. Kochpatcharin from TSMC pointed out that every time a new technology is launched, the foundry must look at what is happening in the ecosystem and what is happening to the IP needed to support the new technologies. The foundry must keep up with all the IP that is needed by each customer. Proving the IP could take a year or two before a customer can expect any tapeout results. Product development and process technologies are becoming so expensive, most companies only have one shot to get the tapeout working. It is not just the IP customer that is interested in the IP, but it’s also the IP customers’ customer who is interested. The foundries are concerned about the IP because they want quality IP so they can fill their fabs.

Although many skeptics predicted the decline of design starts, the number of tapeouts at the foundries continues to grow. In fact, TSMC sees the number of tapeouts rising by the thousands. Tapeouts are rising and so is the number of unique IP blocks in each design. So how does the industry keep up with the growing number of tapeouts, while accommodating a larger number of unique IP blocks per design? One of the ways that tapeouts can continue to increase at such a rate is through the reuse of proven IP.

Most IP is being used multiple times. TSMC has over 3700 IP blocks that have been catalogued and tagged. Approximately 2500 have been reused two or more times. So customers are reusing the IP that they are licensing.

Of course, reuse doesn’t eliminate all the headaches. The foundries are not only involved in physical verification, they must now get involved in the quality of the IP and the quality of their IP partners. TSMC’s job is not just physical verification. At the pre-silicon level, TSMC gets involved in physical review, DFM compliance, and pre-silicon assessment of a new design.

The new IP ecosystem is evolving and expanding. IP vendors must consider more information relating to the specifications at the system level and are getting more involved with the end application. Now companies have to deal with the IP customer’s customer.

It’s natural for EDA and IP to grow closer together because EDA companies have to have process know-how. In that sense, EDA companies have to be very close to the foundries. EDA companies also have to have a lot of automation know-how, but automation to an IP vendor is not exactly the same know-how because it’s often about manipulating IP.

The tricky one is application know-how. It’s increasingly evident with the advent of subsystems and advanced processor technology, in order to deliver quality IP solutions, more application knowledge is necessary. That opens the door for specialty or application-oriented IP players. Some of the specialty IP vendors have expertise in key segments whether it’s automotive or imaging or wireless. Rowen believes the more software content in specialty IP, the more application focus there tends to be. So the structural trend is that EDA companies will play bigger roles, but the challenge is whether they can step up their game to have the application know-how as an integral part of their offerings, to create a much richer system.

The panel concluded that IP integration is becoming more and more complicated. The idea of software and IP reuse is going to be an integral part of the industry going forward and everyone needs to do their part to guarantee quality. Tirupattur made two additional closing observations. The first one, IP reuse is like a human organ transplant, they don’t always work perfectly. Second, based on the panel bios, the real secret to a successful IP company is the executives need to start running marathons because the value of your company is directly related to the number of miles run.
And finally, one more shout out to Analog Bits. One very happy conference attendee walked away with an AR.Drone2.0 that Analog Bits gave away in a drawing right after the panel. Thank you Mahesh and Analog Bits! Congratulations on being designed into something your kids can now appreciate.