High Bandwidth Memory

High Bandwidth Memory (HBM) is a high-performance RAM interface for 3D-stackedDRAM from Samsung, AMD, and Hynix. It is to be used in conjunction with high-performance graphics accelerators and network devices.[1] The first devices to use HBM are the AMD Fiji GPUs.[2][3]

High Bandwidth Memory has been adopted by JEDEC as an industry standard in October 2013.[4] The second generation, HBM2, was accepted by JEDEC in January 2016.[5]

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HBM achieves higher bandwidth while using less power in a substantially smaller form factor than DDR4 or GDDR5.[6] This is achieved by stacking up to eight DRAM dies, including an optional base die with a memory controller, which are interconnected by through-silicon vias (TSVs) and microbumps. The HBM technology is similar in principle but incompatible with the Hybrid Memory Cube interface developed by Micron Technology.[7]

HBM memory bus is very wide in comparison to other DRAM memories such as DDR4 or GDDR5. An HBM stack of four DRAM dies (4‑Hi) has two 128‑bit channels per die for a total of 8 channels and a width of 1024 bits in total. A graphics card/GPU with four 4‑Hi HBM stacks would therefore have a memory bus with a width of 4096 bits. In comparison, the bus width of GDDR memories is 32 bits, with 16 channels for a graphics card with a 512‑bit memory interface.[8] HBM supports up to 4 GB per package.

The larger number of connections to the memory, relative to DDR4 or GDDR5, required a new method of connecting the HBM memory to the GPU (or other processor).[9] AMD and Nvidia have both used purpose-built silicon chips, called interposers, to connect the memory and GPU. This interposer has the added advantage of requiring the memory and processor to be physically close, decreasing memory paths. However, as semiconductor device fabrication is significantly more expensive than printed circuit board manufacture, this adds cost to the final product.

The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. The channels are completely independent of one another and are not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve high-speed, low-power operation. The HBM DRAM uses a 500 MHz differential clock CK_t / CK_c (where the suffix "_t" denotes the "true", or "positive", component of the differential pair, and "_c" stands for the "complementary" one). Commands are registered at the rising edge of CK_t, CK_c. Each channel interface maintains a 128‑bit data bus operating at double data rate (DDR). HBM supports transfer rates of 1 GT/s per pin (transferring 1 bit), yielding an overall package bandwidth of 128 GB/s.[10]

The second generation of High Bandwidth Memory, HBM2, also specifies up to eight dies per stack and doubles pin transfer rates up to 2 GT/s. Retaining 1024‑bit wide access, HBM2 is able to reach 256 GB/s memory bandwidth per package. The HBM2 spec allows up to 8 GB per package. HBM2 is predicted to be especially useful for performance-sensitive consumer applications such as virtual reality.[11]

On January 19, 2016, Samsung announced early mass production of HBM2, at up to 8 GB per stack.[12][13] SK Hynix also announced availability of 4 GB stacks in August 2016.[14]

In late 2018, JEDEC announced an update to the HBM2 specification, providing for increased bandwidth and capacities.[15] Up to 307 GB/s per stack (2.4 Tbps effective data rate) is now supported in the official specification, though products operating at this speed had already been available. Additionally, the update added support for 12‑Hi stacks (12 dies) making capacities of up to 24 GB per stack possible.

A third generation of High Bandwidth Memory, HBM3, was announced in 2016.[16][17] HBM3 is expected to offer increased memory capacity, greater bandwidth, lower voltage, and lower costs. The increased density is expected to come from greater density per die and more die stacks per chip. Bandwidth is expected to be 512 GB/s or greater. No release date has been announced, though Samsung expects volume production by 2020.

For the future of exascale high-performance computers, Hewlett Packard Enterprise predicts OPGHC HBM3+ and HBM4 to be released between 2022 and 2024. More stacking and higher capacity should bring more addressable memory per socket and higher speed. HBM3+ is planned with 4 TB/s and 1024 GB addressable memory per socket. (For comparison, high-end AMD EPYC chips have 150 GB/s and 2048 GB addressable DDR4 DRAM per CPU socket.)[18]. With 32 Gb DRAM die and 16 dies per HBM3+ stack, each HBM3+ component would provide a capacity of 64 GB.

The development of High Bandwidth Memory began at AMD in 2008 to solve the problem of ever-increasing power usage and form factor of computer memory. Amongst other things, AMD developed procedures to solve the die stacking problems with a team led by Senior AMD Fellow Bryan Black. Partners from the memory industry (SK Hynix), interposer industry (UMC) and packaging industry (Amkor Technology and ASE) were obtained to help AMD realize their vision of HBM.[19] High volume manufacturing began at a Hynix facility in Icheon, Korea in 2015.

HBM has been adopted as industry standard JESD235 by JEDEC as of October 2013 following a proposal by AMD and SK Hynix in 2010.[4] The first GPU utilizing HBM is AMD Fiji which was released in June 2015 powering the AMD Radeon R9 Fury X.[20][2][21]

HBM2 was accepted by JEDEC as standard JESD235a in January 2016.[5] The first GPU chip utilizing HBM2 is the Nvidia Tesla P100 which was officially announced in April 2016.[22][23]

At Hot Chips in August 2016 both Samsung and Hynix announced the next generation HBM memory technologies.[24][25] Both companies announced high performance products expected to have increased density, increased bandwidth, and lower power. Samsung also announced a lower-cost version of HBM under development targeting mass markets. Removing the buffer die and decreasing the number of TSVs lowers cost, though at the expense of a decreased overall bandwidth (200 GB/s).