Architectures of digital circuits are usually composed of repetitive
elements in form of computation units or memory blocks. These elements
are usuallt organized to n-dimensional arrays or tree structures. The
process of automated mapping of such architectures into the chips with
limited amount of resources is complicated by several factors. To the
most important ones belong: computation of architecture dimensions,
selection of type of resources for element individual parts. This paper
describes the basic framework of such method for automated mapping of
architectures composed of variable number of processing elements.
Proposed method is evaluated on example of circuit for approximate
string matching using Smith-Waterman algorithm and achieved results are
compared with others approaches in this area.