14.
Image Enhancement :
image can be enhanced by adding a constant to each pixel values.
Image filtering can also be done using model based design different filtering architecture can be defined and
Xilinx block can be created.
Grayscale Image Enhancement

19.
HARDWARE CO-SIMULATION:
The FPGA part to be used (virtex5 xupv5-lx110t).
Hardware co-simulation block
Synthesis tool: Specifies the tool to be used to synthesize the design.
Hardware Description Language: Specifies the HDL language to be used for compilation i. e Verilog.
Create test bench: This instructs System Generator to create a HDL test bench.
Design is synthesized and implemented.

20.
Clocking Tab
FPGA clock period(ns): Defines the period in nanoseconds of the system clock
Clock pin location: Defines the pin location for the hardware clock.
Invoking the Code Generator
The code generator is invoked by pressing the Generate button
in the System Generator token dialog box.

21.
CONCLUSION:
 A real-time image processing algorithms are implemented on FPGA.
 Modeling, simulation and synthesis have made FPGA a highly useful platform.
The Xilinx System Generator tool is a new application in image processing
because processing units are designed by blocks.