ArchLab

UC Santa Barbara

CS Prof. Tim Sherwood works with Engineering students to rebuild IV waterwheel

Prof. Tim Sherwood and several students from the UC Santa Barbara College of Engineering took some time to leave their mark, in the form of the new waterwheel at Anisq ‘Oyo Park in Isla Vista. “The waterwheel had been broken for years — decades,” said UCSB professor Tim Sherwood, who oversaw the group of mostly mechanical engineering students who
tackled the project over the winter and spring quarters. To read the full article by Sonia Fernandez, go here.

December 7, 2014

Tim Sherwood selected as ACM Distinguished Scientist

Congratulations to UCSB CS Professor Tim Sherwood, who was recently named an Association for Computing Machinery (ACM) Distinguished Member. This year the ACM selected 49 scientists, engineers, and
educators from universities, corporations, and research institutions for their significant contributions to the field of computing. ACM President Alexander Wolf hailed these ACM members as “drivers
of the advances and inventions that are propelling the information revolution in new directions. Their creativity and commitment to their craft ensures that we will benefit as a society in the
digital age.”

January 25, 2014

Hassan Wassel and Ying Gao win IEEE Micro Top Pick

As multicore processors find increasing adoption in domains such as aerospace and medical devices where failures have the potential to be catastrophic, strong performance isolation and security
become first-class design constraints. When cores are used to run separate pieces of the system, strong time and space partitioning can help provide such guarantees. However, as the number of
partitions or the asymmetry in partition bandwidth allocations grows, the additional latency incurred by time multiplexing the network can significantly impact performance.
In this paper, we introduce SurfNoC, an on-chip network that significantly reduces the latency incurred by temporal partitioning. By carefully scheduling the network into waves that flow across the
interconnect, data from different domains carried by these waves are strictly non-interfering while avoiding the significant overheads associated with cycle-by-cycle time multiplexing. We describe
the scheduling policy and router microarchitecture changes required, and evaluate the information-flow security of a synthesizable implementation through gate-level information flow analysis. When
comparing our approach for varying numbers of domains and network sizes, we find that in many cases SurfNoC can reduce the latency overhead of implementing cycle-level non-interference by up to 85%

January 29, 2013

Valamehr and Sherwood win IEEE Micro Top Pick Award for technique to make it harder to steal keys from hardware

Each year a committee of industry experts and faculty chooses 10
papers from the top computer architecture conferences to highlight in the annual “Top Picks” issue of IEEE Micro. This year UCSB Computer Engineering student Jonathan Valamehr, Computer Science and
Engineering Professor Tim Sherwood, and their collaborators from Microsoft, had their work “Inspection Resistant Memory Architectures” selected for this prestigious publication.
The ability to safely keep a secret in memory is central to the vast majority of security schemes, but storing and erasing these secrets is a difficult problem in the face of an attacker who can
obtain unrestricted physical access to the underlying hardware. Depending on the memory technology, the very act of storing a 1 instead of a 0 can have physical side effects measurable even after
the power has been cut. These effects cannot be hidden easily, and if the secret stored on chip is of sufficient value, an attacker may go to extraordinary means to learn even a few bits of that
information. Solving this problem requires a new class of architectures that measurably increase the difficulty of physical analysis. Jonathan and his collaborators take a first step towards this
goal by focusing on one of the backbones of any hardware system: on-chip memory. They examine the relationship between security, area, and efficiency in these architectures, and quantitatively
examine the resulting systems through cryptographic analysis and microarchitectural impact. In the end, they are able to find an efficient scheme in which, even if an adversary is able to inspect
the value of a stored bit with a probabilistic error of only 5%, the system will be able to prevent that adversary from learning any information about the original un-coded bits with 99.9999999999%
probability.
The paper will appear in the May-June 2013 award edition of IEEE Micro.

April 23, 2012

Prof. Tim Sherwood received UCSB Distinguished Teaching Award

Professor Timothy Sherwood, an associate professor in the Department of Computer Science at UCSB, was recently awarded the Distinguished Teaching Award by the Academic Senate. The award is given in recognition of the efforts of faculty members who have successfully united teaching and research. Nominees are judged by their fellow professors on their excellence in teaching and their contributions to the teaching mission of the University.
In their official announcement, the Academic Senate stated that Professor Sherwood was awarded a Distinguished Teaching Award for “his dedication to teaching excellence.” Many congratulations to Professor Sherwood!

December 1, 2006

Virtual Pipelines by Agrawal and Sherwood is nominated for best paper at Micro

In their paper, an architectural technique that efficiently supports high-bandwidth, uniform latency memory accesses, and high-confidence throughput even under adversarial conditions is proposed. The technique, Virtual pipelining. provides a simple to analyze programing model of a deep pipeline (deterministic latencies) with a completely different physical implementation (a memory system with banks and probabilistic mapping). This allows designers to effectively decouple the analysis of their algorithms and data structures from the analysis of the memory buses and banks. Unlike specialized hardware customized for a specific data-plane algorithm, the system makes no assumption about the memory access patterns. In their paper, the authors present a mathematical argument for the system's ability to provably provide bandwidth with high confidence and demonstrate its functionality and area overhead through a synthesizable design. Even though the scheme is general purpose to support new applications such as packet reassembly, it outperforms the state of the art in specialized packet buffering architectures.

Each year, a panel of 30 senior computer architects chooses 10 of the years most significant research publications for publication in a special issue of IEEE Micro. For the 3rd Year in a row, a paper from UCSB Computer Science is present: Introspective 3D Chips by Shashi Mysore, Banit Agrawal, and Sheng-Chih Lin, Navin Srivastava, Kaustav Banerjee, and Timothy Sherwood from ASPLOS 2006. To deal with the complexity of modern systems, software developers are increasingly dependent on specialized development tools such as security profilers, memory leak identifiers, data flight recorders, and dynamic type analysis. In their paper, the authors argue that a new way to attack this problem is with the addition of specialized analysis hardware, literally stacked on top of the processor die using 3D-integration technology. This provides a modular snap-on functionality that could be included with developer systems, while keeping the cost impact on consumer systems to minimum.

The paper titled Profiling over Adaptive Ranges received the best paper award at CGO 06 (4th Annual ACM International Symposium on Code Generation and Optimization), which was held in New York during March 26-29. The paper describes a new geometry-based scheme to summarize the huge number of events processed by a modern computer system. The compact summary, called RAP, adaptively and dynamically zooms onto event ranges of interest, thus creating a profile of the program behavior which can then be used for processor optimization.

June 30, 2005

Tim Sherwood receives early Career award from the National Science Foundation

Tim Sherwood, an Assistant Professor in Computer Science, received the early Career award from the National Science Foundation to fund his research on high speed architectures for online security analysis. The research focus is in building specialized computer processors that are engineered to sort through suspicious packets, and developing new algorithms for hardware string matching.

November 10, 2005

BitSplit Architecture for Intrusion Detection is IEEE Micro Top Pick

Each year, a panel of 30 senior computer architects chooses 10 of the years most significant research publications for publication in a special issue of IEEE Micro. In this work, a novel high-speed tile-based packet scan technique is described that can search for strings and perform restricted pattern matching. To build an efficient system, the technique converts the large database of search strings into a language, and then rips the language into a set of sub-languages each of which describes a bit-slice of the original language. A recognizer for each of these sub-languages can then be loaded into a simple memory tile and run in parallel. While this sounds somewhat theoretical, a prototype has been implemented, demonstrated it's usefulness through the development of a custom rule compiler, and formally proved both the correctness and efficiency of our approach.