VIA Isaiah Processor Architecture Preview - Low Power CPU

Isaiah Architecture (cont'd)

The Isaiah is a truly competitive part when compared to current
offerings from AMD and Intel. It is a out-of-order, superscalar design
which utilizes multiple decode and execution units that take it a big
step above the previous C7 processor. In fact, many of its design
aspects do remind us of Intel’s Core 2 Duo, but with a mind towards
overall power consumption.

VIA Isaiah Wafer from Mystery Fab - Photo courtesy Russell Johnson

Isaiah is being produced on a bulk 65 nm process, though VIA is not
releasing who is doing the fabrication. The previous C7 was produced
by IBM on their 90 nm SOI process. This time Centaur decided to forgo
SOI and work with a cheaper bulk process (though nearly any 65 nm
process has plenty of power and speed optimizations over previous 90 nm
nodes). When considering die size, the people at VIA are not talking
official numbers as of yet, but most likely Isaiah uses around the same
amount of space as the older C7 cores.

The core does not utilize an integrated memory controller, but
still uses the VIA V4 front side bus to a memory controller on the
chipset. Centaur did a lot of work to mitigate any latency penalties
for using an off-chip controller. The first is the use of large L1 and
L2 caches. The L1 data and instruction caches each feature 64 KB,
while the L2 cache expands from 128 KB in the C7 to 1 MB with Isaiah.
The CPU also uses a memory prefetch function which actually stores data
from main memory in L2 cache.

Centaur did a lot of work on the caches. Both the L1 and L2 caches
feature 16 way set associativity, and they are exclusive caches.
Exclusivity means that the data in the L1 caches is not replicated in
the L2. Intel’s C2D caches are non-exclusive, but because of the large
2 MB/core L2 cache it is not that big of a deal. The L1 caches have 16
byte accesses, while L2 cache is doubled to 32 bytes. They were
unwilling to give overall MB/sec throughput for the caches, but their
performance should be adequate for what the design requires.

The core utilizes three complex decoders which can take a full X86
instruction and break it down into micro or macro-ops, depending on the
instruction/s. It also features 7 execute units which can take these
ops, as well as handle fused ops. The floating point unit does look to
be quite impressive, as they are saying it is one of the fastest and
lowest latency units around. It can do 2 adds and 2 muls in 1 cycle,
which makes its potential throughput pretty tremendous. It also
features a 128 bit wide SSE unit which supports SSE-3. This is
something that AMD implemented in Phenom, and Intel had in their
original Core 2 Duo chips. The FP unit may not kick around the
competition when put in real-world situations, but it is surely a huge
improvement over the previous C7.

The C7 had a very basic branch predictor, and it seemingly relied
more upon other front end optimizations such as the caches to improve
its efficiency. Centaur has taken a different approach with Isaiah.
It now features a much more robust and complex branch predictor unit
which should improve overall efficiency. Their predictor looks quite
unique, and a step away from what Intel and AMD have been doing with
their products. More research is needed on my part to better
understand the functionality of this branch predictor. Needless to
say, it is a major improvement from the previous C7.

Perhaps the most impressive feature of this architecture is the
transistor count. Each chip is approximately 94 million transistors,
and quite a bit of that is taken up by the 1 MB L2 cache. Compare this
with the AMD Phenom which features 450 million transistors. Though
that is a four core part with 2 MB of L3 cache, we see that the Isaiah
is still less than 1/4th the size.

Current Isaiah Die Shot

VIA will not pursue dual core products at this time, but the Isaiah
architecture can handle more than one core. Supposedly much of the
internal infrastructure needed to create a dual core product is
present, and just waiting for the right economic and processing
conditions to design a product around.

The overall performance of the chip has not been discussed, as it
is still undergoing a lot of testing and tuning. VIA does expect it to
be 2 to 4 times faster than the C7 at the same clockspeed, and be able
to pull about the same power. This will be a tremendous boost for
those working with the lower power/small form factor designs.

We will start seeing the first Isaiah products near the end of 1H
2008. Already there are some 40 design wins based on Isaiah with
manufacturers around the world. If the product performs as advertised,
it will be a viable competitor to AMD and Intel’s low power offerings.
For the integrated market, the only real competition on the horizon is
Intel’s Silverthorne line. VIA will still have a lot of time to
capture as much marketshare as possible before Intel rolls out their
product, and if this product is as good as VIA is hoping, then they
have a chance at being a major supplier of X86 parts.