The obvious design tradeoff is that while any desired degree of ripple attenuation can be achieved by choosing a large enough RC product, settling time will correspondingly suffer. For example, if we (fairly logically) choose a definition for the settling band as equal to ripple amplitude, then…

Tsettle = RC·ln(Vfullscale / Vripple)

= TPWM·Vfullscale·ln(Vfullscale / Vripple) / (4·Vripple)

The consequences of this relationship can be illustrated by the 8-bit case:

But not every application that can’t tolerate molasses-in-January 355·TPWM settling times need or can justify such a complex filtering solution. The Design Idea presented here addresses these middle-of-the-road applications. As shown in Figure 1, it augments the basic R1/C1 low-pass with an inverter, R2, and C2, which combine to negate and subtract (most of) the undesired AC component from the wanted DC signal, leaving a relatively clean analog output with settling time much less than a simple RC filter.

Figure 1 Waveforms & schematic of PWM DAC ripple canceller

But how pure is “relatively clean”, and how fast is “much less”? Setting R2=R1 and C2=C1, the ripple and settling time figures for the new circuit are:

Vripple / Vfullscale = (TPWM / 4·RC)2

Tsettle = TPWM·ln(Vfullscale / Vripple)·(Vfullscale / 16·Vripple)1/2

Referring again to the 8-bit case (illustrated graphically in Figure 1):

Given: RC = 4·TPWM

Tsettle = 22·TPWM = 0.69 ms

with a 32 kHz cycle, it’s 16times faster, with a squared ripple-amplitude ratio!

For many applications, this represents a very worthwhile tradeoff between a modest increase in circuit complexity and a significant increase in PWM DAC performance.

—W. Stephen Woodward is one of EDN's most prolific and innovative Design Ideas authors, with dozens of contributions to his credit.