'''Advanced Programmable Interrupt Controller'''. An advanced version of a [[Glossary#PIC|PIC]] that can handle interrupts from and for multiple CPUs. Modern systems usually have several APICs: Local APICs are CPU-bound, IO-APICs are bridge-bound.

+

'''Advanced Programmable Interrupt Controller'''. An advanced version of a [[Glossary#PIC|PIC]] that can handle interrupts from and for multiple CPUs. Modern systems usually have several APICs: '''Local APICs''' (LAPIC) are CPU-bound, '''IO-APICs''' are bridge-bound.

The '''Built-In Self Test''', a selftest run by the processor when it is first started. Usually, any nonzero value indicates that the selftest failed.

== C ==

== C ==

=== CAR ===

=== CAR ===

−

Cache as RAM.

+

'''Cache as RAM'''.

=== CMOS ===

=== CMOS ===

−

Complementary metal oxyde semiconductor.

+

'''Complementary metal oxyde semiconductor''', a [http://en.wikipedia.org/wiki/CMOS class of semiconductors]. In the coreboot context CMOS (which is a bit of a misnomer here) usually refers to a chunk of non-volatile memory (NVRAM) in the PC, though.

+

* http://en.wikipedia.org/wiki/Nonvolatile_BIOS_memory

=== CPU ===

=== CPU ===

−

Central processing unit (e.g. an Athlon64)

+

'''Central processing unit''' (e.g. an Athlon64).

+

* http://en.wikipedia.org/wiki/Central_processing_unit

=== crt0 ===

=== crt0 ===

−

C Run Time 0 - This is now called the romstage.

+

'''C Run Time 0''' - This is now called the romstage in coreboot.

+

* http://en.wikipedia.org/wiki/Crt0

=== crt0s ===

=== crt0s ===

−

Sources that make up the romstage.

+

Sources that make up the romstage in coreboot, see [[#crt0|crt0]].

== D ==

== D ==

=== DCR ===

=== DCR ===

−

Decode Control Register.

+

'''Decode Control Register'''.

=== DID ===

=== DID ===

−

Device ID, a way of identifying the hardware in question. See [[Glossary#VID|VID]] for more info.

+

'''Device ID''', a way of identifying the hardware in question. See [[Glossary#VID|VID]] for more info.

DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load.

DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load.

* http://en.wikipedia.org/wiki/Direct_memory_access

* http://en.wikipedia.org/wiki/Direct_memory_access

=== DSDT ===

=== DSDT ===

−

Differentiated System Descriptor Table, generated by BIOS and necessary for ACPI, see mailing list also. Implementation of ACPI needs to be done in a "cleanroom" development process to avoid legal issues.

+

'''Differentiated System Descriptor Table''', generated by BIOS and necessary for [[#ACPI|ACPI]]. Implementation of [[ACPI|ACPI in coreboot]] needs to be done in a "cleanroom" development process to avoid legal issues.

APIC

Advanced Programmable Interrupt Controller. An advanced version of a PIC that can handle interrupts from and for multiple CPUs. Modern systems usually have several APICs: Local APICs (LAPIC) are CPU-bound, IO-APICs are bridge-bound.

BIOS

BIST

The Built-In Self Test, a selftest run by the processor when it is first started. Usually, any nonzero value indicates that the selftest failed.

C

CAR

Cache as RAM.

CMOS

Complementary metal oxyde semiconductor, a class of semiconductors. In the coreboot context CMOS (which is a bit of a misnomer here) usually refers to a chunk of non-volatile memory (NVRAM) in the PC, though.

crt0

crt0s

D

DCR

Decode Control Register.

DID

Device ID, a way of identifying the hardware in question. See VID for more info.

DMA

Direct Memory Access. Allows certain hardware subsystems within a computer to access system memory for reading and/or writing independently of the main CPU. Examples of systems that use DMA: Hard Disk Controller, Disk Drive Controller, Graphics Card, Sound Card.
DMA is an essential feature of all modern computers, as it allows devices of different speeds to communicate without subjecting the CPU to a massive interrupt load.

E

EEPROM

EHCI

F

Flashing

Flashing means writing of flash memory. The BIOS on modern mainboards is stored in a flash memory chip, which can be 128 Kilobytes to 4 Megabytes big.

Framebuffer

The Framebuffer is a part of RAM in a computer allocated to hold the graphics information for one frame or picture. This information typically consists of color values for every pixel on the screen.
A framebuffer is either:

Off-screen, meaning that writes to the framebuffer don't appear on the visible screen

On-screen, meaning that the framebuffer is directly coupled to the visible display

LPC

LRU

Least Recently Used, a rule used in operating systems that utilises a paging system. LRU selects a page to be paged out if it has been used less recently than any other page. This may be applied to a cache system as well.

P

PAM

Programmable Attribute Map. Hardware registers that describe how certain memory areas are accessed. The BIOS areas have a flash chip mapped on top of a piece of memory. By changing the PAM registers, accesses to these memory areas can be mapped to either the RAM or the flash device. Shadowing is implemented by setting read accesses to the flash device and write accesses to the same address space are mapped to RAM. Walking over the address space, each byte is read and immediately written from/to each address. Afterwards write accesses are ignored and read accesses are mapped to RAM. Usually the PAM registers are part of the southbridge of a system.

PAT

Page Attribute Table. Can be used independently or in combination with MTRR to setup memory type access ranges. Allows more finely-grained control than MTRR.

UHCI

V

VGAcon

The purpose of the VGAcon (VGA controller) is to isolate the details of VGA signal generation from all the other modules in a (hardware) design. It allows the pixel information to be written into its video memory using a very simple interface, while it is alone responsible for generating the required signals for displaying the pixel information on a VGA monitor. (Note: This is mostly relevant to a hardware design - the text is copied from a students FPGA project).