TSVs can be used to reduce chip-to-chip wire lengths, or to reduce on-chip global wire lengths. For on-chip global wire length reduction, small TSV area is important due to the high TSV densities. If, instead of 5um TSVs with 7um keep-out zones, you have 5um TSVs with <1um keep-out zone, each TSV moves from taking a ~20um region to taking a ~7um region, which represents a 8-9x area reduction.

" Separately, Terrazon has shown a design using tungsten TSVs that have a high CTE and thus can eliminate the keep-out zone, Reiter notes. "

this statement is absolutely WRONG.

Tungsten has been used instead of Copper to fill TSV vias because it has a LOWER CTE than Cu, almost similar to Silicon hence unlike Cu almost no mismatch stresses during temperature cycling or any effect on device performance ( therefore very small KOZs and the freedom to disperse TSVs throughout the chip and not just at a central location ).

The company that uses W to fill vias is not Terrazon but TEZZARON

The stress field around a filled TSV depends on the square of the Via Dia, the thermal mismatch strain and the modulus of the fill material. Hence the effort now at LETI and elsewhere to try smaller dia TSVs and fill them with lower Mod materials.

Tungsten filling of vias were chosen to satisfy theory and are already in production for Memory chips. The limitation of W is that can't be too long, hence Cu filled vias are preferred for TSVs in interposers ( 2.5-d ).

BTW did this IITC paper from GloFo report any reliability test results ( e,g. temp. cycling effects on the compressive layer in the vias and ultimately surrounding transistors ) ?

The offer of writing a comprehensive article on 3-d TSV technology for EE Times still stands.