Antenna effect is an important issue that critically impacts the reliability and yield of integrated circuits. The dynamic-programming-based (DP-based) layer assignment method has been adopted to minimize antenna violation by enumerating all possible solutions and pruning inferior solutions. However, the complexities of modern circuits have significantly increased, likely causing the DP-based meth...
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As technology node advances, Extreme Ultraviolet Lithography (EUVL) is regarded as the most promising technology for improving the lithographic printability. However, there are still several challenges in EUVL like the most critical flare effect that causes patterning distortions. As a result, dummy fills are added to a layout (i.e., dummification) to compensate the flare effect. Although dummy fi...
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As compared to two-dimensional (2D) ICs, 3D integration is a breakthrough technology of growing importance that has the potential to offer significant performance and functional benefits. This emerging technology allows stacking multiple layers of dies and resolves the vertical connection issue by through-silicon vias (TSVs). However, though a TSV is considered a promising solution for vertical co...
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One of main challenges of 3D-integration is the area overhead which has two main causes: first the huge TSV diameter which is usually in the range of microns, and the second reason is the Keep-Out-Zone (KOZ) overhead due to the high induced thermal stresses during fabrication. The area overhead besides the fabrication process itself inversely affects the overall yield and fabrication cost, so the ...
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In this paper, a low-complexity video stitching algorithm and its system prototype are proposed. With the novel design, users can obtain a high-resolution, high quality and seamless 360-degree panoramic video immediately by stitching the images with overlapped regions. Most of the present works are focused on image stitching instead of video stitching. In the proposed design, we develop some novel...
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This paper presents a novel abstraction-guided simulation approach for multiple target states which uses posterior probabilities of the states from the abstract model, instead of abstract distances used by former abstraction-guided approaches, as the guidance of simulation. The posterior probabilities carry more precise information of the abstract model, being able to offer more effective guidance...
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Recently a novel test response compaction method called output selection is proposed to achieve high compaction ratio and high diagnosibility by observing only a subset of output response bits. In addition, this method also ensures zero aliasing and no unknown-value problem. Previously, a single counter and a multiplexer are employed as selection logic for output selection on scan-based designs. T...
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With the advance of semiconductor manufacturing technology, low yield issue of a circuit/system has received much attention. Error-tolerance is an innovative concept that can significantly improve yield of integrated circuits (IC's) by identifying defective yet acceptable chips. In this paper we first employ an Inverse Discrete Wavelet Transform (IDWT) circuit to illustrate the potential of yield ...
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The Oscillation-Based Test (OBT) method converts the circuits under test (CUTs) into self-oscillating mode by changing CUT's typology or adding feedback path(s). In traditional OBT, the frequencies and amplitudes of sinusoidal oscillation are used as fault features to build up the fault dictionary, which is capable of test but not diagnosis. This paper designs harmonic feedback path to enlarge the...
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This paper presents an efficient implementation of key-value store using Bloom filters on FPGA. Bloom filters are used to reduce the number of unnecessary accesses to the hash tables, thereby improving the performance. Additionally, for better hash table utilization, we use a modified cuckoo hashing algorithm for the implementation. They are implemented in FPGA to further improve the performance. ...
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Logic implication that finds necessary assignments for a given set of value assignments in a Boolean circuit has a wide set of applications in the computer-aided design field, such as logic optimization, design verification, and test pattern generation. Due to the high computational complexity, earlier methods either cannot or do not find all necessary assignments, limiting their qualities in the ...
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Due to its low power, small ripple and low noise properties, low-dropout regulators (LDO) are often used in on-chip applications. However, there are few design automation works focusing on this important circuit. In this paper, an automatic optimization process is proposed to generate the optimal sizing of low dropout regulators. The devices in the LDO circuit and its error amplifier are both cons...
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The integrated CPU/GPU architecture brings performance advantage since the communication cost between the CPU and GPU is reduced, and also imposes new challenges in processor architecture design, especially in the management of shared memory resources, e.g, the last-level cache and memory bandwidth. Therefore, a micro-architecture level simulator is essential to facilitate researches in this direc...
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This paper presents a switch-routing framework which can generate a feasible Hamiltonian-path switch routing while minimizing the dynamic IR drop of a targeted fragile active domain with an analytical model. The accuracy of the analytical model and the effectiveness of the proposed framework are validated through an advanced multi-domain mobile-phone MTCMOS design.
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PDN evaluation/synthesis techniques have been used to facilitate the planning/construction of PDNs in integrated circuits at early physical implementation stages. They are rarely relevant after the routing stage when few routing resources are left and hence call for a repair strategy. The reason is that the traditional methods often apply wire widening or wire density increment directly without ta...
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Switching activity in digital circuits produce current peaks which result in voltage fluctuation on the power network, and the accompanying digital power noise may cause WIFI desense. To address this issue, this paper proposes a novel simulation method for application to WLCSP (Wafer Level Chip Scale Packaging), in which RDL (Redistribution Layer) routing is only partially occupied by power mesh. ...
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This paper provides a step-by-step guideline for the assessment of an automotive safety microprocessor with ISO 26262 hardware requirements. ISO 26262 part 5 - Product development at the hardware level - specifies the safety activities during the phase of the automotive hardware development. In this phase, hardware safety design is derived (from the results of ISO 26262 part 3 and 4), implemented,...
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One notable difference between 3D test flow and 2D test flow mainly lies in the mid-bond test, in which the stacking yield can be further enhanced through optimized bonding arrangement. In contrast to the existing sequential stacking, this paper proposes a novel rearranged stacking scheme which estimates the probability and cost of failed bonding in each stacking step and optimizes the mid-bond or...
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Three-dimensional integration is considered a promising solution to cure the challenges of performance, power consumption, quality, and reliability issues. The feature of 2.5D ICs is that the dies are stacked on a passive silicon interposer and the dies communicate with each other by means of TSV-based interconnects and re-Distribution layers (RDL) within the silicon interposer. This paper aims to...
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Three-dimension ICs (3D-ICs) are the current trend due to their improvement in heterogeneous integration, performance, power consumption, silicon area, and form factors. However, the consequent new challenges are interconnects between dies, i.e., Through-Silicon-Vias (TSVs) and micro-bumps (μ-bumps). Therefore, many interconnect test, diagnosis, and repair schemes were proposed, such as dou...
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A 3X-oversampling hybrid clock and data recovery (CDR) circuit with programmable bandwidth has been fabricated in a 55-nm CMOS technology. The jitter tolerance analysis and the design of the proposed architecture are presented. The proposed hybrid CDR consists of a conventional phase-tracking CDR and a oversampling CDR for jitter tolerance improvement. Based on the input jitter magnitude and jitte...
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This paper proposes a low-area digitalized band-pass filter (BPF) for the DSRC Receiver. The resonance of active inductor and MOS varactor are utilized to generate band-pass filtering characteristics. To apply for different passband, both the inductance of the inductor and the capacitance of the varctor are designed to be adjusted via digital controls. Band selectivity is raised by cascading stage...
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