About Me

I’m an analytical person, skilled at distilling problems to their essence. This helps me manage complex projects by being able to break them down into workable steps, while still maintaining the overall picture. Once brokendown, with dependencies analyzed, it becomes easier to delegate amongst a team and increases the chances of on-time delivery

With many years of working in the field, I’ve become a technical expert in multiple related areas of Digital Design and Verification, for both FPGAs and ASICs. This includes such things as working in VHDL, Verilog, and SystemVerilog, using the UVM and OVM Frameworks, as well as developing in C and occasionally Assembly (usually ARM) to support design and verification. Additionally I have built several ASICs where my role was backend Synthesis and Static Timing Analysis.

I spend a lot of time learning new ways of doing things, usually with the goal of improving the way things get done in whatever organization I am working in. Often, however, it is just for satisfying my own curiosity and edification. As a hobby, I spend a lot of time learning new (to me) programming languages, as well as working to become a better digital photographer.

Hand in hand with my desires for continual learning, I like to share what I learn to help others along their path. In the past I have mentored highschool students in algebra, and now I am more than happy to work with willing colleagues to mentor them in areas that I have learned.

I tend to find great satisfaction in finding solutions to problems that are not necessarily orthodox, but get the job done in a logical and timely manner. When a team is in a rut, I feel I am well suited to bring some alternative perspectives to the table.