MyHDL: a Python-Based Hardware Description Language

Hardware design finally enters the 21st century. This new tool brings the readable code of Python and the test discipline of extreme programming to hardware projects.

Digital hardware design typically is done using a specialized
language, called a hardware description language (HDL). This approach
is based on the idea that hardware design has unique requirements. The
mainstream HDLs are Verilog and VHDL.

The MyHDL Project challenges conventional wisdom by making it possible
to use Python, a high-level, general-purpose language, for
hardware design. This approach lets hardware designers benefit from
a well-designed, widely used language and the
open-source model behind it.

Concepts

An HDL contains certain concepts that reflect the nature of
hardware. The most characteristic concept is a model for massive
concurrency. An HDL description consists of a large amount of tiny
threads that communicate closely with one another. This design calls for an
approach to threading that is as lightweight as possible.
HDL descriptions are executed on a dedicated runtime
environment called a simulator.

When designing MyHDL, I took a minimalistic approach, which is in line
with the Python spirit and a good idea in general. Therefore, an
important part of MyHDL is a usage model for
Python. The other part consists of a Python package, called myhdl,
that contains objects that implement HDL concepts. The following
Python code imports some MyHDL objects that we are going to use shortly:

from myhdl import Signal, Simulation, delay, now

MyHDL models concurrency with generator functions, recently
introduced in Python (see the on-line Resources). They are similar to classic functions,
except they have a nonfatal return capability. When a generator
function is called, it returns a generator, which is the object of
interest. Generators are resumable and keep state between
invocations, making them usable as ultra-lightweight threads.

The following example is a generator function that models
a clock generator:

This function looks similar to a classic function in Python. Notice that the
functional code starts with a while 1 loop; this is the idiomatic way
to keep a generator alive forever. The essential difference between
a classic and a generator function is the yield statement. It
behaves similarly to a return statement, except the generator
remains alive after yielding and can be resumed from that
point. Moreover, the yield statement returns a delay
object. In MyHDL, this mechanism is used to pass control information
to the simulator. In this case, the simulator is informed that it
should resume the generator after a delay of ten time units.

The parameter clk represents a clock signal. In MyHDL, signals are
used for communication among generators. The concept of a signal is
inherited from VHDL. A signal is an object with two values: a
read-only current value and a next value that can be modified by assigning
it to the .next attribute. In the example, the clock signal is
toggled by setting its next value to the inverse of its current value.

To simulate the clock generator, we first create a clock signal:

clk = Signal(bool(0))

The signal clk has a Boolean zero as its initial value. Now, we
can create a clock generator by calling the generator function:

clkgen_inst = clkgen(clk)

To have a minimally useful simulation, let's create another generator
that monitors and prints the changes of the clock signal over time:

The yield clk statement shows how a generator can wait on a
change of the signal value.

In MyHDL, a simulator is created with the Simulation object
constructor, which takes an arbitrary number of generators as
parameters:

sim = Simulation(clkGen_inst, monitor())

To run the simulator, we call its run method:

sim.run(50)

This runs the simulation for 50 time units. The output is as follows:

$ python clkgen.py
time: clk
0: 0
10: 1
20: 0
30: 1
40: 0
50: 1

At this point, we can describe how the simulator works. The simulation
algorithm is inspired by VHDL, an HDL slightly less popular
than Verilog but a better example to follow. The simulator
coordinates the parallel execution of all generators using an
event-driven algorithm. The object that a generator yields specifies
the event for which it wants to wait before its next invocation.

Suppose that at a given simulation step, some generators become active
because the event they were waiting on has occurred. In a first
simulation phase, all active generators are run, using current signal
values and assigning to next values. In a second phase, the current
signal values are updated with the next values. As a result of signal
value changes, some generators become active again, and the simulation
cycle repeats. This mechanism guarantees determinism, because the
order in which the active generators are run is irrelevant for the
behavior of the model.