I have been working on the test ROM, but I can only do so much while away from the house with my desktop PC that has NESICIDE on it, other than perhaps loading NESICIDE on someone else's PC, based on INL's revised Verilog or kevtris's untested Verilog. Hopefully thefox can get the PowerPak version working soon. I did manage to get the automated test to start running in FCEUX and display an error message.

I have a few questions about using NESICIDE as an IDE, which I'll bring up in the other topic.

Additionally thefox should be able to take my verilog and dump it into mapper #28 of power pak mappers to allow for additional testing. The one thing to keep in mind when he does that though is default/startup values my code doesn't actually cover that, it's a setting in the fitting properties of Xilinx webpack.

Can't you do this in Verilog? At least for my FPGA projects, it picks up the initialization values from Verilog automagically, i.e.

Perhaps so. I haven't gone back to look at the verilog since I got it working.

tepples wrote:

I have been working on the test ROM, but I can only do so much while away from the house with my desktop PC that has NESICIDE on it, other than perhaps loading NESICIDE on someone else's PC, based on INL's revised Verilog or kevtris's untested Verilog. Hopefully thefox can get the PowerPak version working soon. I did manage to get the automated test to start running in FCEUX and display an error message.

Did you catch my note about unchecking the "bug icon" in the toolbar to disable some of the more intensive debuggers. Unfortunately it currently disables the breakpoint engine too but I'm thinking about leaving that in. If performance of the IDE is your main issue it'd be something to try.

tepples wrote:

I have a few questions about using NESICIDE as an IDE, which I'll bring up in the other topic.

Great! In my experience [both professional and private], user feedback always leads to a better end product.

Can't you do this in Verilog? At least for my FPGA projects, it picks up the initialization values from Verilog automagically, i.e.

Code:

reg [5:0] prg_outer_bank = 6'hFF; //sets PRG ROM A15-20

Perhaps you can with the FPGA, From what I understand it won't work for me on the CPLD. If it's worked for you in the past I say go for it. I found online where it said you had use the flag 'defparam' to initialize in the code. This is all dependent on the compiler/synthesizer not necessarily verilog 'rules' as far as I know.

_________________If you're gonna play the Game Boy, you gotta learn to play it right. -Kenny Rogers

I noticed that the nametable visualizer in NESICIDE reacts instantly when I press F8 to step to the next instruction. This is convenient; FCEUX's doesn't.

Doesnt this conflict conceptually with the idea of tying the nametable viewer update to a specific scanline? There would need to be a way to change the nametable viewer to refresh every time the debugger snaps, instead of at the specified scanline.

I noticed that the nametable visualizer in NESICIDE reacts instantly when I press F8 to step to the next instruction. This is convenient; FCEUX's doesn't.

Doesnt this conflict conceptually with the idea of tying the nametable viewer update to a specific scanline?

True, both behaviors can't be enabled at once, but each behavior has its own uses.

Quote:

There would need to be a way to change the nametable viewer to refresh every time the debugger snaps, instead of at the specified scanline.

For that, I'd recommend a radio button with options "Current" and "Scanline #".

Anyway, I'm working on adding tests for CHR RAM size (8K, 16K, or 32K) and tests to rule out a bunch of obscure misunderstandings of nametable mirroring that arose from an IRC discussion with kevtris. I had someone make me PowerPak mappers for both 8K and 32K versions based on kev's Verilog code.

thefox has given me the go-ahead through an IRC conversation to distribute PowerPak mapper files (MAP1C.MAP) based on the Verilog implementation by kevtris, which pass test version 0.03. The two versions differ in their CHR RAM size:

The 32K version of the mapper provides four 8192-byte pages of CHR RAM.

The 8K version of the mapper provides one 8192-byte page of CHR RAM.

To clarify (January 2017):Well-behaved games should run fine with the 32K. A few games may require the 8K version due to having been tested only on the 8K or on emulators that behave the same way. If you're testing a game that you're developing, use the one that matches how your board connects CHR A14-13.

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