Triad attempts to make mixed-signal design for the masses

Automation has been the name of the game for digital designers for a long time. It enables them to create more in the same amount of time and at complexity levels not possible in the past. But not all chips are 100% digital and in fact the analog part of many chips is growing again due to the amount of interfaces being integrated on chip. Analog has never had the same advantages. Abstractions for analog have not existed and design times seem to exponentially increase with complexity. To make matters worse, the latest manufacturing nodes and not very friendly to analog circuitry. Decreasing voltages have made signal to noise ratio small, and in turn requiring analog to be even more independent of process variations. What is a design team to do?

Well, Triad Semiconductor and Mentor Graphics recently announced a new approach to low cost, mixed-signal IC design. It is called ViaDesigner and it is a tool that enables system-level engineers, who have no previous IC design experience, to design their own mixed-signal configurable ASICs. Can that be possible – I hear you ask? According to Triad, this new approach to IC design is built on system-level design technology from Mentor Graphics and Triad’s intelligent ViaASIC™ library wizards and results in IC development in two to six months, allows respins in less than four weeks, and can radically reduce the cost and risk typically associated with custom mixed-signal IC design.

ViaDesigner is built upon SystemVision® a tool from Mentor Graphics, which merges design capture, SPICE simulation, digital simulation, and high-level VHDL-AMS behavioral modeling into a unified design flow. Triad’s ViaDesigner tunes and extends the SystemVision environment by adding an easy-to-use set of ViaASIC library wizards that help the user design sophisticated mixed-signal circuits while freeing the designer from the tedium and expertise required of full-custom IC layout. ViaDesigner output is mapped to a ViaASIC utilizing Triad’s mixed-signal aware place & route software, ViaPath™.

I had a few questions for Triad, and Reid Wender, VP Marketing & Technical Sales, stepped up to the plate to provide me with answers. His answers were very in-depth and so I have included them very much as he provided. First I asked if anyone has used this yet to tapeout a mixed-signal chip and if so what kind of design? Reid replied:

There are two parts to Triad’s technology: via-configurable array (VCA) hardware and the new EDA software -- ViaDesigner.

VCA technology was initially deployed around 2003 for use in strategic radiation-hard applications.

We introduced our first commercial VCA (VCA-1) in 2006.

Customers have been in volume product with VCAs since 2008 with production volumes ranging from 300 devices/year to 10-million devices/year.

Unique to Triad, we also developed a proprietary mixed-signal aware place and route tool called ViaPath. ViaPath places vias in the global routing fabric of a VCA to configure and interconnect the analog and digital resources without the need for full custom layout. For many years now, we’ve been using this design flow to release low, medium and high volume designs to production.

With the announcement of ViaDesigner we are empowering the system-level design engineer to do their own “front-end” design. It is currently available in a “closed beta” format for select customers in 2012. These customers will be the first users to tapeout designs on ViaDesigner but they will be utilizing a flow very similar to the flow Triad has used for over six years with models that have been developed, characterized and refined through years of prototyping and production.

As for what kind of designs customers are using VCAs for a wide range of applications.

Power management sweep up chips (some in industrial, some in consumer) – volumes from 50K to 1-million/year

50V mixed-signal industrial design with 5 different power domains – volumes of 400K/year

I then asked about the compromises that a design must make using this kind of technology. I said I understand that it may enable people to create analog when they couldn’t before, that it will be faster, but what do they leave on the table? It took 20 years for RTL synthesis to be as good as hand crafted, but that was an OK tradeoff.

I hate to start out with “your mileage will vary” but when it comes to trade-offs of VCAs versus full-custom or standard-cell ASIC solutions “your mileage will vary.”

First of all, we are not field programmable on purpose.

Field programmable devices use active switches as connection resources. This is okay for digital because an active switch simply consumes power, makes the chip bigger, introduces noise and makes things run more slowly (sounds pretty bad when you say it that way). Digital-only FPGAs overcame these negatives by relentlessly following a “Moore’s Law” path to smaller and smaller geometries. Eventually, FPGAs got to process nodes where they could deliver SYSTEM-PERFORMANCE that was acceptable to a large percentage of all designs needing ASIC integration with reasonable total cost of ownership.

Triad uses a single mask configuration step at the foundry and our configuration element is a standard metal via. Compared to the FPGA’s active transistor, a via is: infinitesimally small, very fast (low resistance), and does not introduce noise. Therefore, we think via-configurablility and not transistor field programmability is what makes since for mixed-signal configurable ASICs.

On the digital sideThe configurable digital logic of a VCA is built out of via-configurable complex logic gates and flip-flops. We do not use RAM-based look-up tables. The power, speed and area profile of our digital section looks more like a standard-cell implementation than an FPGA. Unlike, a standard-cell design we do place fabric over the entire digital section and, in theory, that introduces an increase in area compared to a standard cell implementation. With minimum metal and via pitches we have to put the metal somewhere. Our logic cells are alternated with RAM cells to create logic tiles. These RAM cells are porous in the metal layers where we run the global routing fabric. Therefore, the digital area is increased by the size of these RAM blocks when compared to a standard-cell implementation.

If you do not use any of the RAM in one of our VCAs your design would be a good bit larger than a standard-cell design. The reality is that most of the designs we see today contain a good amount of distributed RAM. Since many people prototype on FPGAs we see designers taking advantage of the FPGA’s distributed and block RAMs. When they port such a design to a standard-cell ASIC they are often surprised at how much area is consumed by the combined RAM/Std-cell logic design due to the inefficiency of combining a bunch of RAMs into the standard-cell routing. For most real designs we see our digital section 10-30% slower and larger than a hand-optimized digital section and this tends to be an excellent trade-off for all but the highest volume designs.

We are not typically trying to solve the 40-million gate digital-only design problem. Most of our customers are looking for 10K to 300K gates worth of digital integration.

For things like ARM Cortex-M0 processors we do harden them into arrays for minimized size and optimized performance.

On the analog sideDigital is a lot of little objects with a whole bunch of interconnect. For example, a digital design could have tens of thousands of flip-flops and combinatorial logic that need to be interconnected. Analog tends be larger objects (think op-amps) with far fewer interconnects. Triad’s VCA technology really shines in analog and mixed-signal.

Triad’s focus, patents and trade secrets revolve around mixed-signal: fabric, via-configurability, mixed-signal place & route and the art required to make these things work together in a precision analog environment – we’ve been refining this solution since 2002.

If you found this article to be of interest, visit EDA Designline where you will find the latest and greatest design, technology, product, and news articles with regard to all aspects of Electronic Design Automation (EDA).

Also, you can obtain a highlights update delivered directly to your inbox by signing up for the EDA Designline weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).

Once the FPGA guys get their analog act in gear just the high volume applications will be left for Triad. Like other markets look for the FPGAs to follow right behind by adding the popular analog components that Triad 'tests out' in the low end and mid-range spaces.