A full wave bridge drops voltage across 2 diodes, so it will lose ~1.4V, a bit less with Schottky diodes.

Regulators vary and can be low drop-out LDO. You have to read the datasheets.

Calculating ripple after the filter capacitor can be complex and you have to know the load characteristics. At the very least you need the DC resistance of a resistive load. A big capacitor with little or no load will have a tiny ripple. A small capacitor with a big load can be 100% ripple.

I'm not an old hand here, but I would think that most bridges (silicon based) would have a characteristic ~0.7 V drop as they are basically four rectifier diodes configured in a package. In the configuration used, a pair at a time can be conducting so about ~1.4 V would be my guess.

I'll add that the voltage drop across a diode depends on the current passing through it and its temperature, hence "~" 0.7V. If you need an accurate value, it depends on the specific diode and situation.

This is of no concern in most simple DC supplies, but it matters if you're trying to rectify low voltage wind power, for instance.

i want to know that what is the formula for smoothing a dc supply through capacitor and how much voltage drops by passing a bridge and also a regulator

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The main thing that you will need to be able to calculate is the minimum value of the reservoir capacitance that will be required.

Start with the ideal capacitor equation:

i = C ∙ dv/dt

but use an approximate form of that, solved for C:

C ≥ i ∙ Δt / Δv

Or, with capacitor ESR (Equivalent Series Resistance) included:

C ≥ (i ∙ Δt) / (Δv - (i ∙ ESR))

Remember that C is in Farads. If you want the answer in microFarads, multiply the right side by 1000000.

For the ESR, it is often convenient to initially use an approximate value of

ESR = 0.02 / (C ∙ Voltage_Rating_of_Cap)

where C is in Farads. You will want to use capacitors with extra-low ESR. (It should also be better to use multiple smaller-value capacitors in parallel instead of one large capacitor, for several reasons, including the lower combined ESR.)

Above, i is the maximum expected peak load current (in Amperes), Δt is the maximum time interval for which the capacitance might be required to supply that current (in seconds), and Δv is the maximum tolerable dip in the rail voltage (in Volts), due to the current i being drawn from the capacitance for Δt seconds.

Some prefer to use the maximum expected average or RMS load current, for i, instead of the peak current. Sometimes that might be sufficient.

The designer must determine or choose Δv. Δv is also known as "the peak-to-peak ripple voltage".

(However, note that except for the pathologically-boring case of a constant DC load current, the ripple voltage will typically not be periodic, and you can then mostly forget about the textbook examples that show a sawtooth-like ripple voltage.)

For a mains-powered supply with a full-wave bridge rectifier and a sufficiently-rated transformer, we can assume that

Δt = 1 / (2 ∙ fmains)

since the leading edge of another charging pulse will arrive from the rectifiers in less than that interval of time. Here, fmains is the frequency of the AC Mains voltage, usually either 60 Hz or 50 Hz.

With a Voltage Regulator:

If a voltage regulator follows the reservoir capacitance, its input voltage must never drop below its desired output voltage plus its specified dropout voltage. That means

Vreg_in ≥ Vreg_out + Vreg_dropout + safety margin

In that case, the bottom of the ripple voltage waveform must never dip down to the level of Vreg_in. Otherwise, the regulator will drop out of regulation and its output voltage will become very ugly, probably with ripple-shaped chunks gouged out of it.

That means that the ripple voltage amplitude must be less than the rail voltage minus the regulator's input voltage:

Δv ≤ Vrail - Vreg_in

or

Δv ≤ Vrail - Vreg_out - Vreg_dropout - safety margin

Note that the dropout voltage of a regulator will change with the current that it is supplying. So look in the datasheet and find the plot of dropout voltage versus load current and select the dropout voltage that corresponds to the maximum expected peak load current.

Note that even if a voltage regulator is not used, all other active loads (i.e. with transistors, or transistors within ICs) will have a "minimum voltage" spec that is very similar to a dropout voltage, and that is often in the range of 2 to 5 volts. For an amplifier circuit, for example, it would be the minimum voltage between the power supply input and the signal output, often called Vclip, and would typically be 3 to 4 Volts, e.g. the minimum Vce of an output transistor plus the voltage across its small emitter resistor.

Aside: Many people forget that both Vclip and Vripple must be subtracted from Vrail, when calculating the maximum peak signal output and the rated max output power of an amplifier.

For an audio power amplifier:

With an un-regulated power supply:

Δv = Vrail - Vclip - Vpk

where Vpk is the maximum peak output voltage for a sine wave output at the RATED maximum output power, and Vclip is the minimum voltage across the amplifier itself, i.e. between the power rail and the output, and is typically around 3 Volts or more for output stages without "stacked" transistors such as Darlingtons. Many chip amp datasheets, such as LM3886 and LM3875, provide plots of Vclip versus rail voltage.

Note that this equation for the minimum reservoir capacitance assumes the true worst-case load current, which would be a constant DC output signal at the PEAK sine level that corresponds to running at the rated maximum output power. Typically, it seems, the minimum capacitance calculation is performed assuming constant DC at the RMS level rather than the PEAK level. But that assumes a single sine wave output at max rated power and is not the worst-case load condition.

It can also be useful and enlightening to express Vpk in terms of the rated maximum output power, P_rms:

Vpk = √(2(P_rms)(Rload))

and substitute that for Vpk in the equation for C and then solve for P_rms, to see how the RATED (i.e. sinusoidal RMS) maximum output power varies with the value of the reservoir capacitance.

All of the above assumes that the transformer output voltage doesn't sag under load, and that the mains voltage never falls below its nominal value. It would be wise to also perform the design calculations for the worst-case conditions that might occur.

For high-current loads, especially, it might be necessary to consider the transformer winding resistance's voltage drop, and also the actual diode voltage drops at the expected peak diode current, but assuming the peak diode current is three to five times the average load current, since the diodes must supply all of the ampere-seconds used by the load, on average, but only conduct for one-third to one-fifth of the time. (On the other hand, if the transformer winding's leakage inductance were considered, we might find that the peaks of the rectifier output voltage are somewhat higher than the expected transformer output voltage would provide.)

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After all of that, I will say that it seems like most people have a view of power supplies that is far too voltage-centric. The current is the signal and is the interesting part! The power supply needs to be able to supply current, and changes in current, accurately, in both amplitude and time.

The inductance (and resistance) of the power rail conductors can make it very difficult to supply fast transient currents and high-frequency current to a load, accurately. Therefore it will often be necessary to use decoupling capacitances, right at the point of load, if there is to be any hope of accurately supplying the transient currents that the load demands. And note that active loads and feedback loops will often need to use slew rates and frequencies that are 10X to 20x faster than those in their input or output signals.

Having decoupling capacitors at the point of load will also mostly prevent voltage spikes from being induced across the parasitic inductances of the power and ground rail conductors. They also help to contain highly-dynamic current flows in small loops, helping to prevent both conducted and radiated interference.

Calculation of the required values of decoupling capacitance is similar to what was given above, except i is replaced with Δi/2, and Δt may be based on worst-case slew rate, or the edge time (rise time) of a digital IC, for example.

Δv/Δi can also be thought of as a maximum target impedance

Z_target = Δv/Δi

that the decoupling network must provide, as seen by the power/gnd pin RIGHT AT the active load (NOT at the PSU output), which should not be exceeded at least up to a frequency given by

f = 1 / (π ∙ t_rise)

For very high-speed circuits (high slew rates, not necessarily high repetition rates), you would also need to use a form of v = L di/dt to calculate the maximum tolerable inductance, which would give the maximum LENGTH of the connections plus lead spacing of the smaller decoupling capacitors, and would also be likely to point out that it would be impossible to attain unless multiple decoupling capacitors were placed in parallel, with minimal mutual inductance. (But at that point you should be using a multi-layer PCB with power and ground planes.)

Note that if the Δv/Δi type of idea is applied to the main reservoir caps, then looking at the denominator of

C ≥ (i ∙ Δt) / (Δv - (i ∙ ESR))

from farther above, it becomes clear that if the ESR of the reservoir capacitance is close to the desired Δv/Δi (or Δv/i), then the denominator gets close to zero and the required capacitance will become "excessive", which is yet-another reason to use low-ESR reservoir capacitors.

The grounding configuration should also be a concern, especially for high-current loads, and for low-noise requirements, because ground-return currents will induce voltages across the inductance and resistance of the ground conductors, which will cause various "ground" points throughout the circuit to have varying voltages, compared to the power supply ground. This is also known as "bouncing ground". It can be particularly troublesome at the ground reference point for the input signal of a high-gain amplifier, for example.

Therefore, separate ground-return conductors should be used for each type of ground return, such as the load ground, signal ground, and feedback ground, which can be achieved with a "star ground" PCB-trace or wiring topology or with the use of a ground plane. ("Star power" topologies can also be useful.)

The single common or "star" grounding point might typically be at or very near the output ground of the power supply, e.g. very near to the ground connection of the last reservoir capacitor. But it should never be further "upstream" than that; i.e. never closer to the rectifiers or transformer than any reservoir capacitor's ground pin. Otherwise, all of the various separate "star" ground-return conductors would share some length of conductor with the charging pulses from the rectifier, and the voltage induced by the charging pulses, across that length of conductor, would cause voltage disturbances at the far end of every one of the separate ground conductors.

It might sometimes also be a good idea to use more than one parallel stage of reservoir capacitance, so that the first stage can confine a significant portion of the charging pulse ground currents in a smaller local loop, with its own separate ground conductor to the rectifier ground (and/or center tap, if one is used). The rest of the reservoir caps could then have another separate ground conductor, to the rectifier or transformer.