This page provides information on the Next Generation Microprocessor (NGMP) development based on LEON4-FT

GR740: The ESA Next Generation Microprocessor (NGMP)

After the preliminary GINA study based on LEON3, completed in 2006, Aeroflex Gaisler has started the first development phase of the Next Generation Microprocessor (NGMP) under a TRP contract. This first phase was kicked off in summer 2009, and it comprises the architectural (VHDL) design, verification by simulation and on FPGA. FPGA boards have been made available in 2010. The design is a quad-core LEON4 based microprocessor with L2 cache and numerous peripherals.

The development of Functional Prototypes of the NGMP, called NGFP, has been started in April 2011. These prototypes have been manufactured in 45 nm commercial structured ASIC technology eASIC Nextreme2. While the FPGA prototypes include only a subset of the NGMP features, and their clock frequency is limited to 45 - 70 MHz, the goal of NGFP is to allow functional validation and evaluation by end users of an almost fully fledged NGMP implementation. NGFP contains most of the features of NGMP (except the high speed serial links), and runs at a clock frequency of 150 MHz, which is a good step towards the final space ASIC implementation. Development boards have been made available in 2013 under the product name GR-CPCI-LEON4-N2X.

News

During Final Presentation Days at ESTEC on 01. June 2015, the following NGMP related activities have been presented:

Sept. 2014: After some delay due to unavailability of a suitable chip technology, the development was resumed in Q2/2014, and currently the first layout iterations are in progress, using the C65SPACE platform from ST Microelectronics. Due to technology constraints, compared to the full NGMP baseline design, a somewhat modified version will be implemented. Most prominent changes are the removal of DDR2 and HSSL interfaces due to missing IP and packaging solutions, but there are also some enhancements, namely the increased L2 cache size of now 2 MByte. As design optimisation is currently in progress, the final specification is still subject to changes. The intention is to freeze the design by the end of this year (2014) and to publish an updated datasheet at this webpage. Rad-hard EM prototypes should become available in 2015, followed by qualification to FM level. This chip will be commercialised under the product number GR740.