A FIELD-PROGRAMMABLE GATE ARRAY (FPGA) is an integrated circuit
designed to be configured by a customer or a designer after
manufacturing – hence "field-programmable ". The FPGA configuration
is generally specified using a hardware description language (HDL),
similar to that used for an application-specific integrated circuit
(ASIC). (Circuit diagrams were previously used to specify the
configuration, as they were for ASICs, but this is increasingly rare.)
A Spartan FPGA from
XilinxXilinx

FPGAs contain an array of programmable logic blocks , and a hierarchy
of reconfigurable interconnects that allow the blocks to be "wired
together", like many logic gates that can be inter-wired in different
configurations. Logic blocks can be configured to perform complex
combinational functions , or merely simple logic gates like AND and
XOR . In most FPGAs, logic blocks also include memory elements, which
may be simple flip-flops or more complete blocks of memory.

Contemporary field-programmable gate arrays (FPGAs) have large
resources of logic gates and RAM blocks to implement complex digital
computations. As FPGA designs employ very fast I/Os and bidirectional
data buses, it becomes a challenge to verify correct timing of valid
data within setup time and hold time.
Floor planning enables resources
allocation within FPGAs to meet these time constraints. FPGAs can be
used to implement any logical function that an
ASIC could perform. The
ability to update the functionality after shipping, partial
re-configuration of a portion of the design and the low non-recurring
engineering costs relative to an
ASIC design (notwithstanding the
generally higher unit cost), offer advantages for many applications.

Some FPGAs have analog features in addition to digital functions. The
most common analog feature is programmable slew rate on each output
pin, allowing the engineer to set low rates on lightly loaded pins
that would otherwise ring or couple unacceptably, and to set higher
rates on heavily loaded pins on high-speed channels that would
otherwise run too slowly. Also common are quartz-crystal
oscillators, on-chip resistance-capacitance oscillators, and
phase-locked loops with embedded voltage-controlled oscillators used
for clock generation and management and for high-speed
serializer-deserializer (SERDES) transmit clocks and receiver clock
recovery. Fairly common are differential comparators on input pins
designed to be connected to differential signaling channels. A few
"mixed signal FPGAs" have integrated peripheral analog-to-digital
converters (ADCs) and digital-to-analog converters (DACs) with analog
signal conditioning blocks allowing them to operate as a
system-on-a-chip . Such devices blur the line between an FPGA, which
carries digital ones and zeros on its internal programmable
interconnect fabric, and field-programmable analog array (FPAA), which
carries analog values on its internal programmable interconnect
fabric.

HISTORY

The FPGA industry sprouted from programmable read-only memory (PROM)
and programmable logic devices (PLDs). PROMs and PLDs both had the
option of being programmed in batches in a factory or in the field
(field-programmable). However, programmable logic was hard-wired
between logic gates.

In the late 1980s, the
Naval Surface Warfare Center funded an
experiment proposed by Steve Casselman to develop a computer that
would implement 600,000 reprogrammable gates. Casselman was successful
and a patent related to the system was issued in 1992.

Some of the industry's foundational concepts and technologies for
programmable logic arrays , gates, and logic blocks are founded in
patents awarded to David W. Page and LuVerne R. Peterson in 1985.

AlteraAltera was founded in 1983 and delivered the industry's first
reprogrammable logic device in 1984 – the EP300 – which featured a
quartz window in the package that allowed users to shine an
ultra-violet lamp on the die to erase the
EPROM cells that held the
device configuration.

XilinxXilinx co-founders
Ross Freeman and
Bernard Vonderschmitt invented
the first commercially viable field-programmable gate array in 1985
– the XC2064. The XC2064 had programmable gates and programmable
interconnects between gates, the beginnings of a new technology and
market. The XC2064 had 64 configurable logic blocks (CLBs), with two
three-input lookup tables (LUTs). More than 20 years later, Freeman
was entered into the
National Inventors Hall of Fame for his
invention.

AlteraAltera and
XilinxXilinx continued unchallenged and quickly grew from 1985
to the mid-1990s, when competitors sprouted up, eroding significant
market share. By 1993,
ActelActel (now
Microsemi ) was serving about 18
percent of the market. By 2010,
AlteraAltera (31 percent),
ActelActel (10
percent) and
XilinxXilinx (36 percent) together represented approximately 77
percent of the FPGA market.

The 1990s were an explosive period of time for FPGAs, both in
sophistication and the volume of production. In the early 1990s, FPGAs
were primarily used in telecommunications and networking. By the end
of the decade, FPGAs found their way into consumer, automotive, and
industrial applications.

21ST CENTURY DEVELOPMENTS

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A recent trend has been to take the coarse-grained architectural
approach a step further by combining the logic blocks and
interconnects of traditional FPGAs with embedded microprocessors and
related peripherals to form a complete "system on a programmable
chip". This work mirrors the architecture created by Ron Perlof and
Hana Potash of Burroughs Advanced Systems Group in 1982 which combined
a reconfigurable CPU architecture on a single chip called the SB24.
Examples of such hybrid technologies can be found in the Xilinx
Zynq-7000 All Programmable SoC, which includes a 1.0 GHz dual-core ARM
Cortex-A9 MPCore processor embedded within the FPGA's logic fabric or
in the
AlteraAltera Arria V FPGA, which includes an 800 MHz dual-core ARM
Cortex-A9 MPCore. The
Atmel FPSLIC is another such device, which uses
an AVR processor in combination with Atmel's programmable logic
architecture. The
MicrosemiSmartFusion devices incorporate an ARM
Cortex-M3 hard processor core (with up to 512 kB of flash and 64 kB of
RAM) and analog peripherals such as a multi-channel ADC and DACs to
their flash-based FPGA fabric. A
XilinxXilinx Zynq-7000 All
Programmable System on a Chip.

An alternate approach to using hard-macro processors is to make use
of soft processor cores that are implemented within the FPGA logic.
Nios II ,
MicroBlaze and
Mico32 are examples of popular softcore
processors. Many modern FPGAs are programmed at "run time", and this
is leading to the idea of reconfigurable computing or reconfigurable
systems – CPUs that reconfigure themselves to suit the task at hand.
Additionally, new, non-FPGA architectures are beginning to emerge.
Software-configurable microprocessors such as the Stretch S5000 adopt
a hybrid approach by providing an array of processor cores and
FPGA-like programmable cores on the same chip.

Companies like Microsoft have started to use FPGA to accelerate
high-performance, computationally intensive systems (like the data
centers that operate their Bing search engine), due to the performance
per Watt advantage FPGAs deliver.

Historically, FPGAs have been slower, less energy efficient and
generally achieved less functionality than their fixed ASIC
counterparts. An older study had shown that designs implemented on
FPGAs need on average 40 times as much area, draw 12 times as much
dynamic power, and run at one third the speed of corresponding ASIC
implementations. More recently, FPGAs such as the
XilinxXilinx Virtex-7 or
the
AlteraAlteraStratix 5 have come to rival corresponding
ASIC and ASSP
solutions by providing significantly reduced power usage, increased
speed, lower materials cost, minimal implementation real-estate, and
increased possibilities for re-configuration 'on-the-fly'. Where
previously a design may have included 6 to 10 ASICs, the same design
can now be achieved using only one FPGA.

Advantages of FPGAs include the ability to re-program in the field to
fix bugs, and may include a shorter time to market and lower
non-recurring engineering costs. Vendors can also take a middle road
by developing their hardware on ordinary FPGAs, but manufacture their
final version as an
ASIC so that it can no longer be modified after
the design has been committed.

XilinxXilinx claims that several market and technology dynamics are
changing the ASIC/FPGA paradigm:

*
Integrated circuit development costs are rising aggressively
*
ASIC complexity has lengthened development time
* R white-space:nowrap;">. Customers wanting a higher guarantee of
tamper resistance can use write-once,
Antifuse FPGAs from vendors such
as
Microsemi .

With its
Stratix 10 FPGAs and SoCs,
AlteraAltera introduced a Secure Device
Manager and physically uncloneable functions to provide high levels of
protection against physical attacks.

In 2012, researchers, Sergei Skorobogatov and Christopher Woods,
demonstrated that FPGA's can be vulnerable to hostile intent. They
discovered a critical backdoor vulnerability had been manufactured in
silicon as part of the Actel/
Microsemi ProAsic 3 making it vulnerable
on many levels such as reprogramming crypto and access keys, accessing
unencrypted bitstream, modifying low-level silicon features, and
extracting configuration data.

APPLICATIONS

An FPGA can be used to solve any problem which is computable . This
is trivially proven by the fact FPGA can be used to implement a soft
microprocessor , such as the
XilinxXilinxMicroBlaze or
AlteraAlteraNios II .
Their advantage lies in that they are sometimes significantly faster
for some applications because of their parallel nature and optimality
in terms of the number of gates used for a certain process.

FPGAs originally began as competitors to CPLDs and competed in a
similar space, that of glue logic for PCBs . As their size,
capabilities, and speed increased, they began to take over larger and
larger functions to the point where some are now marketed as full
systems on chips (SoC ). Particularly with the introduction of
dedicated multipliers into FPGA architectures in the late 1990s,
applications which had traditionally been the sole reserve of DSPs
began to incorporate FPGAs instead.

Another trend on the usage of FPGAs is hardware acceleration, where
one can use the FPGA to accelerate certain parts of an algorithm and
share part of the computation between the FPGA and a generic
processor.

Traditionally, FPGAs have been reserved for specific vertical
applications where the volume of production is small. For these
low-volume applications, the premium that companies pay in hardware
costs per unit for a programmable chip is more affordable than the
development resources spent on creating an
ASIC for a low-volume
application. Today, new cost and performance dynamics have broadened
the range of viable applications.

The most common FPGA architecture consists of an array of logic
blocks (called configurable logic block, CLB, or logic array block,
LAB, depending on vendor), I/O pads, and routing channels. Generally,
all the routing channels have the same width (number of wires).
Multiple I/O pads may fit into the height of one row or the width of
one column in the array.

An application circuit must be mapped into an FPGA with adequate
resources. While the number of CLBs/LABs and I/Os required is easily
determined from the design, the number of routing tracks needed may
vary considerably even among designs with the same amount of logic.
For example, a crossbar switch requires much more routing than a
systolic array with the same gate count. Since unused routing tracks
increase the cost (and decrease the performance) of the part without
providing any benefit, FPGA manufacturers try to provide just enough
tracks so that most designs that will fit in terms of lookup tables
(LUTs) and I/Os can be routed. This is determined by estimates such as
those derived from Rent\'s rule or by experiments with existing
designs.

In general, a logic block (CLB or LAB) consists of a few logical
cells (called ALM, LE, slice etc.). A typical cell consists of a
4-input LUT, a full adder (FA) and a D-type flip-flop , as shown
below. The LUTs are in this figure split into two 3-input LUTs. In
_normal mode_ those are combined into a 4-input LUT through the left
mux . In _arithmetic_ mode, their outputs are fed to the FA. The
selection of mode is programmed into the middle multiplexer. The
output can be either synchronous or asynchronous, depending on the
programming of the mux to the right, in the figure example. In
practice, entire or parts of the FA are put as functions into the LUTs
in order to save space.

HARD BLOCKS

Modern FPGA families expand upon the above capabilities to include
higher level functionality fixed into the silicon. Having these common
functions embedded into the silicon reduces the area required and
gives those functions increased speed compared to building them from
primitives. Examples of these include multipliers, generic DSP blocks,
embedded processors, high speed I/O logic and embedded memories.

Higher-end FPGAs can contain high speed multi-gigabit transceivers
and _hard IP cores_ such as processor cores,
EthernetEthernet MACs , PCI /PCI
Express controllers, and external memory controllers. These cores
exist alongside the programmable fabric, but they are built out of
transistors instead of LUTs so they have
ASIC level performance and
power consumption while not consuming a significant amount of fabric
resources, leaving more of the fabric free for the
application-specific logic. The multi-gigabit transceivers also
contain high performance analog input and output circuitry along with
high-speed serializers and deserializers, components which cannot be
built out of LUTs. Higher-level PHY layer functionality such as line
coding may or may not be implemented alongside the serializers and
deserializers in hard logic, depending on the FPGA.

CLOCKING

Most of the circuitry built inside of an FPGA is synchronous
circuitry that requires a clock signal. FPGAs contain dedicated global
and regional routing networks for clock and reset so they can be
delivered with minimal skew . Also, FPGAs generally contain analog PLL
and/or DLL components to synthesize new clock frequencies as well as
attenuate jitter . Complex designs can use multiple clocks with
different frequency and phase relationships, each forming separate
clock domains. These clock signals can be generated locally by an
oscillator or they can be recovered from a high speed serial data
stream. Care must be taken when building clock domain crossing
circuitry to avoid metastability. FPGAs generally contain block RAMs
that are capable of working as dual port RAMs with different clocks,
aiding in the construction of building FIFOs and dual port buffers
that connect differing clock domains.

3D ARCHITECTURES

To shrink the size and power consumption of FPGAs, vendors such as
Tabula and
XilinxXilinx have introduced new 3D or stacked architectures.
Following the introduction of its 28 nm 7-series FPGAs, Xilinx
revealed that several of the highest-density parts in those FPGA
product lines will be constructed using multiple dies in one package,
employing technology developed for 3D construction and stacked-die
assemblies.

Xilinx's approach stacks several (three or four) active FPGA die
side-by-side on a silicon interposer – a single piece of silicon
that carries passive interconnect. The multi-die construction also
allows different parts of the FPGA to be created with different
process technologies, as the process requirements are different
between the FPGA fabric itself and the very high speed 28 Gbit/s
serial transceivers. An FPGA built in this way is called a
_heterogeneous FPGA_.

Altera's heterogeneous approach involves using a single monolithic
FPGA die and connecting other die/technologies to the FPGA using
Intel's embedded multi-die interconnect bridge (EMIB) technology.

DESIGN AND PROGRAMMING

To define the behavior of the FPGA, the user provides a design in a
hardware description language (HDL) or as a schematic design. The HDL
form is more suited to work with large structures because it's
possible to just specify them numerically rather than having to draw
every piece by hand. However, schematic entry can allow for easier
visualisation of a design.

Then, using an electronic design automation tool, a technology-mapped
netlist is generated. The netlist can then be fit to the actual FPGA
architecture using a process called place-and-route , usually
performed by the FPGA company's proprietary place-and-route software.
The user will validate the map, place and route results via timing
analysis , simulation , and other verification methodologies. Once the
design and validation process is complete, the binary file generated
(also using the FPGA company's proprietary software) is used to
(re)configure the FPGA. This file is transferred to the FPGA/
CPLD via
a serial interface (JTAG ) or to an external memory device like an
E
EPROM .

The most common HDLs are
VHDL and
Verilog , although in an attempt to
reduce the complexity of designing in HDLs, which have been compared
to the equivalent of assembly languages , there are moves to raise the
abstraction level through the introduction of alternative languages .
National InstrumentsNational Instruments '
LabVIEW graphical programming language
(sometimes referred to as "G") has an FPGA add-in module available to
target and program FPGA hardware.

To simplify the design of complex systems in FPGAs, there exist
libraries of predefined complex functions and circuits that have been
tested and optimized to speed up the design process. These predefined
circuits are commonly called _IP cores _, and are available from FPGA
vendors and third-party IP suppliers (rarely free, and typically
released under proprietary licenses). Other predefined circuits are
available from developer communities such as
OpenCores (typically
released under free and open source licenses such as the GPL , BSD or
similar license), and other sources.

In a typical design flow, an FPGA application developer will simulate
the design at multiple stages throughout the design process. Initially
the RTL description in
VHDL or
Verilog is simulated by creating test
benches to simulate the system and observe results. Then, after the
synthesis engine has mapped the design to a netlist, the netlist is
translated to a gate level description where simulation is repeated to
confirm the synthesis proceeded without errors. Finally the design is
laid out in the FPGA at which point propagation delays can be added
and the simulation run again with these values back-annotated onto the
netlist.

More recently, OpenCL is being used by programmers to take advantage
of the performance and power efficiencies that FPGAs provide. OpenCL
allows programmers to develop code in the C programming language and
target FPGA functions as OpenCL kernels using OpenCL constructs.

* SRAM – based on static memory technology. In-system programmable
and re-programmable. Requires external boot devices.
CMOSCMOS . Currently
in use. It is worth noting that flash or E
EPROM devices may often load
contents into internal SRAM that controls routing and logic.
* Fuse – One-time programmable. Bipolar. Obsolete.
*
Antifuse – One-time programmable. CMOS.
* PROM – Programmable Read-Only Memory technology. One-time
programmable because of plastic packaging. Obsolete.
*
EPROM – Erasable Programmable Read-Only Memory technology.
One-time programmable but with window, can be erased with ultraviolet
(UV) light. CMOS. Obsolete.
* E
EPROM – Electrically Erasable Programmable Read-Only Memory
technology. Can be erased, even in plastic packages. Some but not all
E
EPROM devices can be in-system programmed. CMOS.
* Flash – Flash-erase
EPROM technology. Can be erased, even in
plastic packages. Some but not all flash devices can be in-system
programmed. Usually, a flash cell is smaller than an equivalent EEPROM
cell and is therefore less expensive to manufacture. CMOS.

MAJOR MANUFACTURERS

By 2006, long-time industry rivals
XilinxXilinx and
AlteraAltera were the FPGA
market leaders. At that time, they controlled over 80 percent of the
market. Both
XilinxXilinx and
AlteraAltera provide proprietary Windows and Linux
design software (ISE /Vivado and Quartus ) which enables engineers to
design, analyse, simulate, and synthesize (compile) their designs.

In March 2010, Tabula announced their FPGA technology that uses
time-multiplexed logic and interconnect that claims potential cost
savings for high-density applications. On March 24, 2015, Tabula
officially shut down.

On June 1, 2015,
IntelIntel announced it would acquire
AlteraAltera for
approximately $16.7 billion and completed the acquisition on December
30, 2015.