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DSP Processors

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DSP processors

DSP systems are able to accomplish tasks inexpensively that would be difficult or even impossible using analog electronics. (Examples of such applications include speech synthesis and speech recognition).

Architecture (cont.)

Single instruction, multiple data describes computers with multiple processing elements that perform the same operation on multiple data simultaneously.

Architecture (cont.)

Instruction-level parallelism (ILP)

Instruction-level parallelism (ILP) is a measure of how many of the operations in a computer program can be performed simultaneously.

Ex:

1. e = a + b

2. f = c + d  independent

3. g = e * f

ILP allows the compiler and the processor to overlap the execution of multiple instructions or even to change the order in instructions

Architecture of the Digital Signal Processor

Transferring information to and from memory includes data, such as samples from the input signal and the filter coefficients, as well as program instructions, the binary codes that go into the program sequencer.

Ex.

a  b×a

Architecture of the DSP(cont.)

There are mainly three types of architectures employed for the processors:

Von Neumann architecture

Harvard architecture

Super Harvard Architecture

1-Von Neumann architecture

contains a single memory and a single bus for transferring data into and out of the central processing unit (CPU).

For example,

Memory

(instruction and data)

CPU

add. bus

data bus

a  b×a

1-Von Neumann architecture(cont.)

Advantages:

This type of architecture is cheap, and

Simple to use because the programmer can place instructions or data anywhere throughout the available memory.

Disadvantages:

Von Neumann computers spend a lot of time moving data to and from the memory, and his slows the computer.

2- Harvard architecture

Separate memories for data and program instructions, with separate buses for each.

For example,

Program Memory

(instruction only)

CPU

Data Memory

(data only)

PM add. bus

DM add. bus

PM data bus

DM data bus

a  b×a

2- Harvard architecture(cont.)

Advantages:

Since the buses operate independently, program instructions and data can be fetched at the same time, improving the speed over the single bus design.

Disadvantages:

data memory bus is busier than the program memory bus.

3- Super Harvard Architecture

Improves upon the Harvard design by adding an instruction cache and dedicated I/O controller.

For example,

Program Memory

(instruction and secondary data)

CPU

Data Memory

(data only)

PM add. bus

DM add. bus

PM data bus

Instruction Cache

DM data bus

I/O

Controller

a  b×a

Data

3- Super Harvard Architecture (cont.)

Advantages:

the instruction cache improves the performance of the Harvard architecture.

I/O controller connected to data memory this dedicated hardware allows the data streams to be transferred directly into memory without having to pass through the CPU's registers.

Disadvantages:

If we were executing random instructions, this situation would be no better at all.

Architecture of the DSP(Cont.)

Now let's look inside the CPU

Architecture of the DSP(Cont.)

At the top of the diagram are two blocks labeled Data Address Generator (DAG), one for each of the two memories.

These control the addresses sent to the program and data memories, specifying where the information is to be read from or written to.