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Silvaco’s TCAD-to-Signoff flow is visualized in the picture below. It encompasses a flow that initiates from TCAD process simulation (driven via a layout if desired). TCAD device simulation enables device characterization I-V/C-V data to be created that can be used as an input into a SPICE model characterization tool where a scalable compact or macro model is generated for utilization in a SPICE circuit simulator. This part of the flow encompasses the process development/integration side.

On the design side the flow can initiate with a schematic or netlist and lead to a schematic/netlist driven layout. The layout can be extracted via a rule based extractor or where detailed parasitics are required a 3D RC extractor. Extracted netlists in combination with model files are used to simulate and verify the circuit. The design can also be made more robust in order to handle process variation. In order to achieve a faster simulation runtime, an optimized extracted netlist can be used with control over accuracy & reduction tradeoffs. In the final stage the design is verified and signed-off physically for DRC and LVS violations and for power integrity via EM/IR/thermal analysis. The entire flow enables a “paper technology & design” cycle well before manufacturing cycles are possible or available. As actual measured data is available during the evolution of a process technology development cycle, the various steps in this flow can be augmented with a combination of simulated and measured data. For example measured data can be used to calibrate the TCAD simulation and can be used for SPICE model extraction. The complete TCAD-to-Signoff flow can be integrated with Silvaco’s statistical analysis or design-of-experiments tools to enable path finding analysis, what-if scenarios, and optimization.