Return of the Son of Pentium in 2008? Intel’s new ultramobile processors

Okay, so the original Pentium isn't really coming back in 2008, but what is coming looks enough like the Pentium to give some of us Pentium-era CPU buffs déjà vu. I'm talking, of course, about Intel's forthcoming attempts at an embedded processor core that will compete with the likes of ARM and MIPS, a "core" that may actually be a family of cores aimed at different applications. One application is low-cost, low-power mobile devices, and it turns out that the Diamondville/Silverthorne processor that will power these devices is a lot leaner than I thought. And contrary to expectations, it also will lag Core Solo significantly in clock-for-clock performance.

The new details on Diamondville/Silverthorne are buried in the program for the 2008 International Solid State Circuits Conference (ISSCC). As always, the program contains a number of tantalizing nuggets of information that will be further fleshed out in the conference presentations, some of which were dug out by David Kanter over at RWT in a recent article. But I want to zoom in on the following entry:

A 47M transistor, 25mm2, sub-2W IA processor designed for mobile internet devices is presented. It features a 2-issue, in-order pipeline with 32KB iL1 and 24KB dL1 caches, integer and floating point execution units, x86 front end, a 512KB L2 cache and a 533MT/s front-side bus. The design is manufactured in 9M 45nm High-? metal-gate CMOS and housed in a 441-ball μFCBGA package.

Unless the "two-issue, in-order pipeline" in question is some kind of derivative of the original Pentium, then my previous skepticism about Intel's "new architecture from the ground up" claims was unwarranted. Even if it isn't really a Pentium derivative, and it probably isn't in any meaningful sense, the fact that it issues two instructions per clock and has an in-order pipeline makes it the spiritual heir to the original Pentium, which was Intel's original x86 two-issue, in-order design.

This also makes it a direct competitor to ARM's embedded processors, which are also two-issue, in-order designs that focus on low power. But in this particular low-transistor-count, sub-2W competition, the x86 ISA does put Intel at a real disadvantage.

Because a huge chunk of Silverthorne's die area is cache, the percentage of total die area that the new processor spends on x86 instruction decoding won't be as high as the original Pentium's 40 percent, but may well be in the double digits. Like the original Pentium, this relatively large number of transistors spent on x86 decode hardware will put Silverthorne at a performance and performance/watt disadvantage compared to a leaner RISC design like ARM, which can spend more die area on performance-enhancing cache. And Silverthorne's lower-cost Diamondville derivative, which will probably be underclocked and/or have less cache than its big brother, will look even worse next to a comparable ARM part.

Given these factors, I think we can safely assume at this point that Silverthorne will be clock-for-clock slower and less efficient than a comparable ARM part, especially on integer-intensive Web and productivity apps. But if the 45nm Silverthorne launches in the 1-2 GHz clockspeed range that Intel claims for it, then it may still be competitive in terms of performance/watt with ARM's 65nm, slower-clocked Cortex A8 (600MHz to 1.1GHz), its closest competitor. In other words, Intel is planning to do to RISC in the embedded space what it has done to RISC everywhere else: steamroll the competition with sheer process muscle.

The revelation that Silverthorne is in-order and two-issue also raises questions about its performance relative to Intel's regular laptop processors. Obviously, Silverthorne won't be anywhere near even a first-generation Pentium M in terms of clock-for-clock performance, though a (more appropriate) performance/watt comparison may put it within striking distance of even a Core Solo. Nonetheless, don't expect Windows to be anything but slow on Silverthorne—you're going want to run a mobile Linux flavor on a Silverthorne-based MID.