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The fourth Industrial Revolution is upon us, driven by digitally connected factories, machines, and devices that are fast enough to process data in real time, and “smart” enough to make good decisions.

Today we announced a solution for an intrinsic DDR3 timing constraint that has been impacting our customers’ system performance. This is great news for networking apps, where tRRD and tFAW timing specifications can restrict much-needed data throughput.

Here’s a little background on the issue.

Activation delay or tRRD is the amount of time that must elapse between two ACTIVATE commands being issued to different banks. Four-bank activation window or tFAW is the amount of time in which ACTIVATE commands to four different banks can be issued. Stated another way, after four banks have been activated, tFAW is the amount of time that must elapse before an ACTIVATE command can be issued to another bank. The bottom line is, tRRD and tFAW limit the number of ACTIVATE commands that can be issued during specified time periods.

The actual tRRD and tFAW timing specifications used are based on page size. For DDR3, a x16 device has a page size of 2KB. In most cases, tFAW is greater than the product of tRRD x 4, which means that tFAW will cause additional delay on top of the delay caused by tRRD.

Here’s an example of how this can impact a system—
DDR3-2133 x 16 tRRD(2KB) = The greater of 4CK or 6ns (7 CLKs at a 0.9375ns tCK); andtFAW (2KB) = 35ns (38 CLKs at a 0.9375ns tCK)

As the figure shows, B[3:0] can be activated in 21 clock cycles. If tRRD was the only constraint, B4 could be activated on the 28th clock cycle. However, tFAW requires an additional 10-clock-cycle delay before the fifth bank can be activated, which reduces system bandwidth by about 30%.

By successfully solving this issue for DDR3, we’re able to provide an 18% increase in bandwidth—something we’re pretty proud of.