Low Power Aging-Aware Register File Design by Duty Cycle Balancing

The degradation of CMOS devices over the lifetime can cause the severe threat to the system performance and reliability at deep sub-micron semiconductor technologies. The Negative Bias Temperature Instability (NBTI) is among the most important sources of the aging mechanisms. Applying the traditional guard banding technique to address the decreased speed of devices is too costly. Due to presence of the narrow-width values, integer register files in high-performance microprocessors suffer a very high NBTI stress.