Integrated Computer-Aided Engineering - Volume 5, issue 2

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ISSN 1069-2509 (P)
ISSN 1875-8835 (E)

Impact Factor 2018: 3.667

The focus of ICAE is the integration of leading edge and emerging computer and information technologies for innovative solution of engineering problems. The journal fosters interdisciplinary research and presents a unique forum for innovative computer-aided engineering. It also publishes novel industrial applications of CAE, thus helping to bring new computational paradigms from research labs and classrooms to reality.

Abstract: Behavioral power estimation is required to help the designer in making important architectural choices. In this work we propose an accurate and general behavioral power modeling approach especially suited for synthesis-based design ows making use of a library of hard macros implementing behavioral operators. Power dissipation models are pre-characterized and back-annotated in a preliminary step. Accurate information on the power dissipation of the used macros can then be collected during behavioral simulation of the synthesized circuit. Our characterization and modeling methodology is based on the theory of linear regression. Optimal linear power models are obtained with methods of least squares…fitting and their generalization to a recursive procedure called tree regression. The regression models can be used for pattern-based dynamic power simulation and for probabilistic static power estimation as well. Our behavioral simulator is integrated within PPP, a multilevel simulation engine for power estimation fully compatible with Verilog XL.
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Abstract: While estimating glitches or spurious transitions is a challenge due to signal correlations, the random behavior of logic gate delays makes the estimation problem even more difficult. In this paper, we present statistical estimation of signal activity at the internal and output nodes of combinational Complementary Metal-Oxide-Semiconductor (CMOS) logic circuits considering uncertainty of gate delays. The methodology is based on the stochastic models of logic signals and the probabilistic behavior of gate delays due to process variations, interconnect parasitics, etc. We propose a statistical technique of estimating average-case activity, which is exible in adopting different delay models and variations and…can be integrated with worst-case analysis into statistical logic design process. Experimental results show that the uncertainty of gate delays has a great impact on activity at individual nodes (more than 100%) and total power dissipation (can be overestimated up to 65%) as well.
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Abstract: Optimizing energy during the synthesis of VLSI embedded systems for real-time-constrained applications is an important new problem. Memory has been shown to be a crucial component of the total system energy dissipation. This paper presents for the first time a network ow approach to minimizing the energy dissipation of memory components during systems synthesis. In particular, this new approach determines the optimal number of external and internal memory accesses and the number of extra computations (or data regeneration) for each task such that the total estimated energy dissipation of a task is minimized. This is unlike previous research which has…only discussed ad-hoc suggestions for this problem. The network ow approach can be solved by a globally optimal solution in polynomial time using very fast and efficient algorithms. A large complex real industrial application, audio compression, donated by Motorola, is used to study the energy savings using different single and multichip system implementations along with voltage scaling. Results of synthesizing this complex application show that for some tasks, estimated energy savings range from 2 to 10 times. This contributes to 2.7 times improvement in the overall estimated energy dissipation of the embedded audio compression system, with no significant increase in cost or decrease in performance. This research is important for industry since consideration of energy dissipation at the early stages of design is crucial for mapping high performance applications into cost-efficient and reliable systems.
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Abstract: A significant part of the power dissipation in CMOS digital circuits is due to the short-circuit currents. In this paper an accurate analytical model for the evaluation of the CMOS short-circuit power dissipation, on the basis of a CMOS inverter, is presented. The innovation of the proposed approach against previous works is due to the accurate, analytical expressions of the inverter output waveform which include for the first time the effects of both transistor currents and the gate-to-drain coupling capacitance. The α-power law MOS model which considers the carriers' velocity saturation effects of short-channel devices is used. The results produced…by the suggested model show very good agreement with SPICE simulations.
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Abstract: In this paper an efficient technique for estimating the average number of signal transitions in CMOS logic circuits is presented. A logic signal is modeled as a two state, discrete-time Markov chain, that is characterized by two parameters. The steady-state average number of transitions on a signal is expressed as a function of the Markov chain parameters. Formulas for the two parameters associated with the gate output as a function of the corresponding parameters associated with the gate input are derived. This allows estimation of signal transitions at all gates by local propagation of the parameters. For circuits without reconvergent,…the local propagation provides very accurate estimates and the time to obtain the estimates is a negligible fraction of the time required to perform logic simulation. For circuits with reconvergent fanout, the estimation procedure is based on the (local) use of OBBDs. This scheme has the exibility of trading off between speed and accuracy by allowing the user to specify the number of levels of reconvergent fanout that are to considered. Results of experiments carried out on a large number of benchmark circuits are given. The theoretical estimates of switching activity are compared with those obtained via simulation. The experiments also examine the number of levels of logic that need to be examined in the presence of reconvergent fanout.
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Abstract: Increasing demand for portable electronics for computing and communication, as well as other applications, has necessitated longer battery life, lower weight, and lower power consumption. In order to satisfy these requirements, research activities focusing on low power/low voltage design techniques are underway. Since 'power' is now one of the design decision variables, the expanded design space required for low power has further increased the complexity of an already non-trivial task. Low power design basically involves two concomitant tasks: power estimation and analysis and power minimization. These tasks need to be carried out at each of the levels in the design…hierarchy, namely, the behavioral, architectural, logic, circuit and physical levels. In this survey of the current state of the field, many of the salient power estimation and minimization techniques proposed for low power VLSI design are reviewed. For each of the design levels, we provide an overview of several power estimation and minimization approaches and the CAD tools that support them. Finally, future research issues are discussed that will be necessary in order to make the low power design endeavor a successful one.
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Abstract: We describe an approach to estimate the average power dissipation in sequential logic circuits under user-specified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the estimation of the power dissipated when the controller or processor is running specific application programs. Current approaches to sequential circuit power estimation are limited by the fact that the input sequences to the sequential circuit are assumed to be uncorrelated. In reality, the inputs come from other sequential circuits, or are application programs. In this paper we show how user-specified sequences and programs can be modeled…using a finite state machine, termed an input-modeling finite state machines or IMFSM. Power estimation can be carried out using existing sequential circuit power estimation methods on a cascade circuit consisting of the IMFSM and the original sequential circuit.
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