G_ANYEXT produces a register of the specified width, with bits 0 to sizeof(Ty) * 8 set to Op. The remaining bits are unspecified (i.e. this is neither zero nor sign-extension). For a vector register, each element is extended individually.

Tst must be a generic virtual register with scalar type. At the beginning of legalization, this will be a single bit (s1). Targets with interesting flags registers may change this. For a wider type, whether the branch is taken must only depend on bit 0 (for now).

opcode for the instruction. Either LLT/TargetRegisterClass/unsigned types for Dst Variadic list of uses of types(unsigned/MachineInstrBuilder) Uses of type MachineInstrBuilder will perform getOperand(0).getReg() to convert to register.