News Flash: NAND is transitioning to 3-D

An industry-wide transition for the nonvolatile NAND flash memory technology from memory cells in a 2-D array to strings of NAND transistors integrated monolithically in the vertical direction is now anticipated. These 3-D memories are expected to be arranged as a 2-D array of vertical semiconductor channels with many levels of gate-all-around (GAA) structures forming the multiple voltage level memory cell transistors.

His focus was primarily on a presentation that had been given by Keyvan Esfarjani at the IMEC Technology Forum, which was held in Brussels in late May. Esfarjani is Intel’s VP of technology and manufacturing. He’s also the co-CEO of IM Flash Technologies (IMFT), a joint venture between Intel and Micron Technologies. For IMFT, 3-D NAND is going to come by way of scaling 2-D NAND.
…Esfarjani, while acknowledging there is a scaling limit for 2-D NAND flash, indicated in one of his slides that 2-D NAND flash can scale to two more nodes at about 15- and 10-nm. The slide showed that the first 3-D NAND generation is likely to be brought up alongside that 15-nm 2-D node. Esfarjani added that 16 layer NAND flash ICs will not be enough to provide an economic benefit. “You need 64 or at least 32 layers,” he said.

While IMFT works on its approach, Toshiba appears to be ahead of the curve. This isn’t surprising, given that NAND (and NOR) flash memory were first developed at Toshiba over thirty years ago. No date on when IMFT’s 3-D NAND will go commercial, but it’s anticipated that Toshiba will be in volume production mode sometime in 2015.

What’s Critical Link’s interest here?

For starters, most of our SoMs include an option for NAND flash memory, and customers who take this option do so primarily to hold the file system that embedded Linux relies on. As embedded Linux permeates further into scientific and medical instrumentation, and even some industrial automation applications, so will the need for NAND. Sure, there are other technologies out there – like SD, MMC, and eMMC (which is now becoming popular). Will eMMC continue to grow its adoption into embedded devices, or will the capacities of 3-D NAND compel embedded designers go this route?