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Abstract

For high speed applications of the 630 microprocessor, it is a requirement that off chip drivers must maintain a specified slew rate to ensure proper packaging electrical noise levels for signal integrity. The slew rate determines the amount of circuit electrical noise created in the package.

Country

United States

Language

English (United States)

This text was extracted from an ASCII text file.

This is the abbreviated version, containing approximately
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CMOS Delay Controlled Circuit

For high
speed applications of the 630 microprocessor, it is a
requirement that off chip drivers must maintain a specified slew rate
to ensure proper packaging electrical noise levels for signal
integrity. The slew rate determines the
amount of circuit electrical
noise created in the package.

This
disclosure proposes a method where circuit RISE/FALL times
of the driver can be controlled with the use of pass gates in CMOS
technology.

The pass
gates in CMOS technology act like a near perfect
switch and are characterized by low ON state impedance, high OFF
state impedance. Fig. 1 shows a block
diagram of a circuit path
where a delay controlled circuit can be used for as part of a Off
chip driver stage. The delay circuit can
be controlled by the
signals CO,C1,..., CN etc., to produce a desired RISE and FALL time
of the driver output.

The circuit
schematic of Fig. 2 shows how this is accomplished.
The predrive stage is basically an inverter stage consisting of P and
N type devices. The predrive stage
drives the large output
transistors. Since the off chip driver
must drive a large capacitive
load, the RISE and FALL time of the output is critical to the
switching noise level produced in the package.
As shown in Fig. 2
the delay controlled circuit consists of pass devices NQO,NQ1,...NQN
and their corresponding input signals are C0,C1,...CN. The
capacitance devices are N0,N1,...NN, and are basica...