Because someone might look at it and say "Oh, that's a good idea - I can use that trick in my project", or "Oh, I see how you could solve that problem - here, try this."

Open source projects aren't museum pieces. People aren't supposed to look at your beautiful code artifact and gasp in awe - they're supposed to use your code, imperfect as it may be, as a springboard for their own projects, or to try something experimental, and if it works, contribute the result back to you.

For example, because the source code is available, I'm able to experiment with the Chameleon port of the Minimig core. I've already implemented a simple Akiko-style chunky-to-planar converter. The source for my changes is already public even though it's far from perfect. Is it compatible with a "real" Akiko? No. Is it useful? No - it's slower than a CPU-based C2P. Is it interesting? Hell yes - it demonstrates how to add new custom chip registers to the chipset, so someone might find it useful, and that's all that matters!

I'm currently reading, annotating and trying to make sense of the TG68K bridge, so I can have my Akiko running at ZorroII speeds instead of chipram speeds. That work will be released, too, as soon as I have it compiling cleanly and doing something.

Quote:

The 68k is done (somebody on this forum already has it)

That's great (Is that the core known as J68?)

Quote:

Agnus is almost done. Then, I have to change Gary and maybe add a cache to the 68k.Things take time, especially when you want to simulate the whole system.

Indeed - but in many ways a project like this is never "finished" - so release early, and release often

frenchshark: yes I have your J68 sources. Unfortunately, I haven't had the time to look at it much (busy busy )

Otherwise I agree with gaula92 and MMrobinsonb5 - I know it is not the "Amiga style", but it is the "opensource style" - it is best to release early, as both you and other interested people could benefit from it. You know, the cathedral and the bazaar

I know that this is not much but TG68 core is started somehow. Clock is from external Cristal at 50Mhz. Statement for reset signal and core is started. Next stage is to use clk from Amiga board but there are some problems with overheating with ALVT devices, so I need to investigate this.

Code:

sys_rst <= '1';

This is complete code so maybe someone can point me about problems. There are no statements for other signals and don't know do I need to add them for example for as or some other signals. Like I said it is not much but for me it is huge progress. Code is dirty and some of the parts are not used for now but you can get the picture

-- not used for now there is some error that I dont understand -- Register input reset signal-- reset_sync: process(sys_clk)-- begin-- if iSYS_CLK'event and iSYS_CLK = '1' then-- reset1 <= iSYS_RESETn; -- Sync through 2 registers-- sys_rst <= not reset1; -- Synchronized active high reset-- end if;-- end process;

@FrenchShark,So you did most of the MCC216 ?I'm 'happy' owner of one. I use the C64(your flagship product) mostly but the ps2key 'right shift problem' always gets to me. I've to re-type what I've typed just to get out of that situation.when typing in basic (when R-shift is pressed too fast with another key). It's a known problem. All my PS2 keyboards (x3) have this problem including the Microsoft keyboard. I'm not buying the Genius KB120 as recommended by some people. Pls have a look see on this. TKU

In 3 wire bus arbitration on MC68K key signals are BR, BG, BGACK but those signals have some dependency of signals present on real MC68K so if we need to use them to start arbitration with FPGA some signals needs to be threaded like input and output one in the same time.

3 wire bus arbitration works this way.FPGA sends BR(active low) to real CPU and he confirms that by sending BG(active low) to FPGA, then FPGA waits for MC68K to finish current cycle and then sends BGACK to MC68K to confirm that FPGA now have control of the bus. After that FPGA negates BR and MC68K confirms that by negating BG and waiting for BGACK to be negated. In that time FPGA performs read and write cycles and after finishing negates BGACK and next arbitration begins.So in this case to send BR we need to separate it into inputBR and outputBR signal, also need to be done with AS, BGACK and some more signals.Also direction control of ALVC devices needs to change direction in cases when we need to read or write signal.

So in the process inputBR is checked and if he is negated inputoutputBR connected to outputBR signal who goes low sending Bus Request. After that ioBGACKn is over obgack_s checking signals on real CPU to find out that he finished his bus cycle and then he sends active low signal to the real CPU, the same time ALVC devices changes their direction, so new states could be sent to real CPU.

So all of this should be separated into different processes and it could be done for day or two but only question I may ask here is all of this necessary, is there any simpler way to disable CPU or he must stay active in some bus cycles. Thank you

After so much questions here some results. TG68 code integrated and I must say that all of previous codes that I have published here was unusable. I just had to find another way to integrate all of this. Most important thing for now that I was trying to run core at 14 Mhz but without any luck because it could be hard to keep original 7.09Mhz bus cycles and in the same time increase performance. http://youtu.be/JkkKMrUkJtE

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