Category

Published on

11 Dec 2012

Abstract

"Thermoelectrics of Roughened Silicon Nanowire Arrays"
The possibility of using silicon as a thermoelectric material for waste heat recovery is technologically significant due to silicon's economy of scale and vast processing knowhow. Patterning silicon as nanowires with roughened sidewalls is shown to enhance the thermoelectric figure-of-merit ZT by order of magnitude compared to the bulk at 300 K. This enhancement is primarily achieved by reduction of thermal conductivity of silicon below 5 W/mK due tophonon scattering from the rough boundaries. We developed an electroless etching technique to generate nanowire arrays (NWAs) with controlled surface roughness, morphology, porosity and doping. The device-level measurements of the thermoelectric properties of the NWAs reveal reduction in the thermal conductivity of NWAs below the Casimir limit due to sidewall roughness. We also observe a reduction in the Seebeck coefficient of NWAs in comparison to the bulk silicon due to the quenching of phonon drag.

Bio

Jyothi Sadhu, Grad Student with Prof. Sanjiv Sinha, Dept. of Material Science and Engineering
Jyothi received his bachelors in Mechanical Engineering from Indian Institute of Technology, Madras in 2008. He received his Masters degree in Mechanical Engineering at UIUC in 2010 and is pursuing his doctoral work. His research interests include modeling electron and phonon transport in thermoelectrics and characterization techniques of nanostructures.
-Taken from Professor Sinha's Lab Group page.