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Patent #

Description

US-7,232,713

Methods of forming interconnect linesIn one aspect, the invention provides a method of forming an electrical
connection in an integrated circuitry device. According to one preferred
implementation,...

US-7,232,198

Printer and print control methodIn a printer, an MPU makes a flash ROM store a temperature read by a
temperature sensor at the time of setting of a correction value and a
misalignment...

Method for erasing an NROM cellAn operation to erase a nitride read only memory (NROM) memory block
starts by erasing the memory block. An erase verify operation can then be
performed to...

US-7,227,777

Mode selection in a flash memory deviceA single flash memory device has selectable read modes for either a
segment mode or a page mode. The desired mode is selected by writing a
control word to a mode...

On-chip substrate regulator test modeAn on-chip circuit for defect testing with the ability to maintain a
substrate voltage at a level more positive or more negative than a normal
negative operating...

Wire bonders and methods of wire-bondingWire bonders and methods of wire-bonding are disclosed herein. In one
embodiment, a method includes attaching a wire to a terminal of a
microelectronic component...

US-7,226,872

Lightly doped drain MOS transistorA method of forming a MOS transistor in an upper surface of a
semiconductor substrate. A gate oxide layer covers the upper surface of
the substrate. A gate stack...