Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY ...

DS557 (v4.1) April 1, 2011 Spartan-3AN FPGA Design Documentation The functionality of the Spartan®-3AN FPGA family is described in the following documents. The topics covered in each guide are listed below: • DS706: Extended Spartan-3A Family Overview • UG331: Spartan-3 ...

Related Product Families The Spartan-3AN FPGA family is generally compatible with the Spartan-3A FPGA family. • DS529: Spartan-3A FPGA Family Data Sheet Revision History The following table shows the revision history for this document. Date Version 02/26/07 1.0 Initial release. ...

DS557 (v4.1) April 1, 2011 DC Electrical Characteristics In this section, specifications can be designated as Advance, Preliminary, or Production. These terms are defined as follows: Advance: Initial estimates are based on simulation, early characterization, and/or extrapolation from the characteristics ...

... DCM XC3S400AN XC3S700AN XC3S1400AN (3) LVCMOS25 , XC3S50AN IFD_DELAY_VALUE = 5, XC3S200AN without DCM XC3S400AN XC3S700AN XC3S1400AN Table 30 and are based on the operating conditions set forth in Table 26. If this is true of the data Input, add the Table 26. If this is true of the data Input, subtract the www ...

Table 23: Setup and Hold Times for the IOB Input Path (Cont’d) Symbol Description T Time from the active transition at the IOICKPD ICLK input of the Input Flip-Flop (IFF) to the point where data must be held at the ...

Table 25: Propagation Times for the IOB Input Path (Cont’d) Symbol Description T The time it takes for data to travel IOPLID from the Input pin through the IFF latch to the I output with the input delay programmed Notes: ...

Output Propagation Times Table 27: Timing for the IOB Output Path Symbol Description Clock-to-Output Times T When reading from the Output IOCKP Flip-Flop (OFF), the time from the active transition at the OCLK input to data appearing at the Output ...

Three-State Output Propagation Times Table 28: Timing for the IOB Three-State Path Symbol Description Synchronous Output Enable/Disable Times T Time from the active transition at the OTCLK IOCKHZ input of the Three-state Flip-Flop (TFF) to when the Output pin enters ...

Timing Measurement Methodology When measuring timing parameters at the programmable I/Os, different signal standards call for different test conditions. Table 30 lists the conditions to use for each standard. The method for measuring Input timing is as follows: A signal ...

Table 34: CLB Distributed RAM Switching Characteristics Symbol Clock-to-Output Times T Time from the active edge at the CLK input to data appearing on SHCKO the distributed RAM output Setup Times T Setup time of data at the BX or ...

Digital Clock Manager (DCM) Timing For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), and the Phase Shifter (PS). Aspects of DLL operation play a role in all DCM applications. ...

Table 40: Switching Characteristics for the DLL (Cont’d) Symbol Delay Lines (5) DCM_DELAY_STEP Finest delay resolution, average over all taps Notes: 1. The numbers in this table are based on the operating conditions set forth in 2. Indicates the maximum ...

DNA Port Timing Table 46: DNA_PORT Interface Timing Symbol T Setup time on SHIFT before the rising edge of CLK DNASSU T Hold time on SHIFT after the rising edge of CLK DNASH T Setup time on DIN before the ...

... All functions except those shown below Configuration commands (CFG_IN, ISC_PROGRAM) All functions except ISC_DNA command During ISC_DNA command All operations on XC3S50AN, XC3S200AN, and XC3S400AN FPGAs and for BYPASS or HIGHZ instructions on all FPGAs All operations on XC3S700AN and XC3S1400AN FPGAs, except for BYPASS or HIGHZ instructions Table www ...

Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY ...

DS557 (v4.1) April 1, 2011 Introduction This section describes how the various pins on a Spartan®-3AN FPGA connect within the supported component packages, and provides device-specific thermal characteristics. For general information on the pin functions and the package characteristics, see ...

Table 62: Types of Pins on Spartan-3AN FPGAs (Cont’d) Type with Color Code Dedicated configuration pin, two per device. Not available as a user-I/O pin. Every package has two dedicated configuration pins. These pins are powered by VCCAUX. See UG332: ...

TQG144: 144-lead Thin Quad Flat Package The XC3S50AN is available in the 144-lead thin quad flat package, TQG144. Table 68 lists all the package pins. They are sorted by bank number and then by pin name. Pins that form a ...

User I/Os by Bank Table 69 indicates how the 108 available user-I/O pins are distributed between the four I/O banks on the TQG144 package. The AWAKE pin is counted as a dual-purpose I/O. Table 69: User I/Os Per Bank for ...

... They are sorted by bank number and then by the pin name of the largest device. Pins that form a differential I/O pair appear together in the table. The differential I/O pairs that have different assignments between the XC3S50AN and the XC3S200AN or XC3S400AN are highlighted in light blue in See ...

... XC3S50AN and the XC3S200AN or XC3S400AN devices for migration between these devices in the FTG256 package. The XC3S200AN and XC3S400AN have identical pinouts. The XC3S50AN pinout is compatible with the XC3S200AN and XC3S400AN, however, there are 51 unconnected balls and one functionally different ball ...

FGG484: 484-Ball Fine-Pitch Ball Grid Array The 484-ball fine-pitch ball grid array, FGG484, supports both the XC3S700AN and the XC3S1400AN FPGAs. There are three pinout differences, as described in Table 78 lists all the FGG484 package pins. They are sorted ...

User I/Os by Bank Table 79 and Table 80 indicate how the user-I/O pins are distributed between the four I/O banks on the FGG484 package. The AWAKE pin is counted as a dual-purpose I/O. Table 79: User I/Os Per Bank ...

FGG676: 676-Ball Fine-Pitch Ball Grid Array The 676-ball fine-pitch ball grid array, FGG676, supports the XC3S1400AN FPGA. Table 82 lists all the FGG676 package pins. They are sorted by bank number and then by pin name. Pins that form a ...

User I/Os by Bank Table 83 indicates how the 502 available user-I/O pins are distributed between the four I/O banks on the FGG676 package. The AWAKE pin is counted as a dual-purpose I/O. Table 83: User I/Os Per Bank for ...

Revision History The following table shows the revision history for this document. Date Version 02/26/07 1.0 Initial release. 08/16/07 2.0 Updated for Production release of initial device. Noted that family is available in Pb-free packages only. 09/12/07 2.0.1 Minor updates ...

Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY ...