Message from the Chair

Much has been happening within Accellera this year and we have much to look forward to in the coming months. The Accellera Board of Directors recently approved the SystemC Synthesis Subset Standard version 1.4.7. The standard is based on the IEEE Std 1666™-2011 SystemC language standard and the ISO/IEC 14882:2003 C++ standard. The working group has spent a great deal of time and much effort to get this standard ready, and we appreciate all of their efforts.

After years of active development and adoption, we are pleased to announce that the SystemC AMS standard has just been released by the IEEE Standards Association as IEEE Std 1666.1™-2016. With the recent extension of our relationship with the IEEE-SA, we are able to offer IEEE Std 1666.1-2016 as part of the IEEE Get Program where the standard can be downloaded at no cost.

We also held the first SystemC Evolution Day in Munich earlier this month. Organized by Accellera members from Infineon, Intel and NXP, the full-day workshop focused on the evolution and progression of SystemC standards. This day resulted in quite a number of relevant standardization proposals which are being further discussed in the Accellera working groups.

At the Design Automation Conference (DAC) next month we have a couple of exciting events for you to attend. Members of our Portable Stimulus Working Group will present a tutorial addressing how portable stimulus addresses key verification, test reuse and portability challenges. We will also have our annual breakfast meeting where we will be presenting our Accellera Leadership Award, and we'll have a panel discussing the Universal Verification Methodology, the challenges the industry is still facing and what's in store for UVM over the next 5 years. We invite you to join us as I'm sure this will be an informative, lively discussion.

I look forward to seeing you in Austin at the Design Automation Conference.

Sincerely, Shishpal Rawat, Accellera Systems Initiative Chair

Accellera at the Design Automation Conference

Accellera Breakfast and Town Hall DiscussionUVM: The Next 5 Years

Tuesday, June 7th 7:30am-9:00am Austin Convention Center, Room 9C

UVM, the Universal Verification Methodology, has experienced enormous success in its first 5 years. It's used by thousands of engineers worldwide in nearly all digital verification flows. The IEEE P1800.2 committee is diligently working to standardize UVM. But what's next for UVM? Future possibilities include of UVM multi-language, UVM for mixed-signal, and UVM for acceleration. Accellera is also in the late stages of bringing a native SystemC implementation of UVM to the community. Join us to discuss what more should be considered for UVM.

At the Accellera DAC breakfast this year, we will assemble a presentation and panel to discuss the next 5 years for UVM. We’ll provide an update on the IEEE P1800.2 UVM standard efforts and then discuss the future with a panel of verification experts. They will shed light on the technical challenges the industry is still facing and how UVM could further evolve to address the needs in areas like SoC verification and software-driven verification.

So come join us and start your day at DAC with an Accellera update by Accellera Chair Shishpal Rawat, the presentation of the Accellera Leadership Award, and a view to the future of UVM. The breakfast is free, but registration is required.

The upcoming Accellera portable test and stimulus standard specification will permit the creation of a reusable model for a variety of users across different levels of integration under different configurations. This tutorial will outline a set of common usage examples that emphasize specific verification, reuse, and portability challenges. Verification challenges include randomization of both data and control flow. Reuse challenges include migrating tests from IP level to SoC. Portability challenges include growing test to improve coverage when running on faster platforms and executing at the full platform speed. Finally, the tutorial will show how portable stimulus can address the usage examples.

This panel is organized by Tom Anderson of Breker Verification Systems, Inc. and Larry Melling of Cadence Design Systems, Inc. Registration with the Design Automation Conference is required to attend the tutorial. Find out more >

Working Group Member Highlight

Since the first SystemC Synthesizable Subset 1.3 was introduced for public review in August of 2009, Andres Takach, Chair of the working group and Michael Meredith, Vice-chair, have worked tirelessly on its evolution. Draft 1.4 was updated and open for public review until May of 2015 after which Andres and Mike worked closely with the working group members to evaluate the public review results and make the valuable changes to move the standard forward. After many years of hard work and dedication, they have introduced SystemC Synthesis Subset Standard version 1.4.7, which has been approved by the Accellera Board of Directors. The standard is based on the IEEE 1666-2011 SystemC language standard and the ISO/IEC 14882:2003 C++ standard.

"Andres and Mike are to be applauded for all of their hard work and leadership in guiding the SystemC Synthesis Working Group through the development of the standard," stated Karen Pieper, Accellera Technical Committee Chair. "Andres and Mike are exceptional leaders, and we'd like to thank them for all of their efforts in bringing SystemC Synthesis to where it is today."

DVCon U.S. 2016 Tutorial Videos

Two video tutorials from DVCon U.S. 2016 are now available.

Cut Your Design Time in Half with Higher Abstraction

This tutorial explains how to use the SystemC language subset to write synthesizable models at a higher level of abstraction than RTL. It provides real code examples comparing algorithms written at RTL and those written using the synthesizable subset, explaining the reasons behind the coding choices and the downstream implications for RTL and gates. It also discusses how a synthesis standard is the foundation for a full design and verification ecosystem at a higher level of abstraction and the value that can bring to the designer. View tutorial >

Preparing for IEEE UVM Plus UVM Tips and Tricks

Debugging UVM testbenches can be extremely difficult because errors often appear in lines of SystemVerilog code that make up the UVM package, as opposed to the user written code. There are also a number of common errors that are hard to recognize because the compiler gets off on the wrong track early and never recovers. Most of these errors can easily be eliminated by following a structured approach to debugging that targets these common errors first. This tutorial delivers a plethora of tips and tricks to alleviate the struggle. It walks you through an introduction of UVM testbench features, includes real-world examples including common errors and fixes, and details how to use the built in debugging features in UVM.

This tutorial also includes changes to the UVM standard as it makes the great leap to the IEEE. View tutorial >

DVCon Around the Globe

DVCon is the industry’s premier set of conferences for discussion of the functional design and verification of electronic systems.

The 28th annual DVCon U.S., held in March, concluded with an overall attendance of almost 1,200 attendees including full conference, exhibit-only and exhibit personnel. With the addition of Europe and India, DVCon now serves more than 2,000 attendees each year worldwide. "At Accellera, because of the demand for the information worldwide, we have decided to expand the global reach of DVCon beyond the U.S., India and Europe to also include China in 2017. We want to make sure that the global design and verification engineering community has access to the outstanding technical programs offered by DVCon," stated DVCon U.S. 2016 Chair Yatin Trivedi.

DVCon India will be held on September 15-16, 2016 at the Leela Palace in Bangalore. The conference continues to grow since its launch in India in 2014. Similar to last year, it will have two parallel tracks: ESL and Design & Verification (DV). The ESL track aims to accelerate the adoption of SystemC in the Semiconductor Industry. It provides a platform for the SystemC beginners, SystemC/TLM experts, ESL managers and ESL vendors to share their knowledge, experiences & best practices about SystemC usage. The DV track provides the design and verification community, including beginners, architects/experts, managers and EDA vendors an opportunity to share their knowledge, experiences and best practices.

DVCon Europe will be held October 19-20, 2016 at the Holiday Inn Munich City Centre in Munich. In its third year, the conference will offer a similar format to previous years, but with an expanded program. The program committee is still in the process of developing the program and will add a second keynote, panels, additional tutorials and other events. The exhibition layout has been improved to allow for more exhibits and an easier traffic flow. Please continue to check back for more information as we finalize the program. We look forward to seeing you in Munich in October!

Two tutorial videos from DVCon Europe 2015 are currently available: "Accellera Standards Technical Update," gives an update on recent standardization activities in the UVM, Portable Stimulus, IP-XACT, and SystemC working groups. The second video, "System-Level Modeling for Today and Tomorrow with SystemC" provides an overview about recent standardization activities from the SystemC-related Accellera and IEEE Working Groups, as well as a segment that addresses, "What is Needed Beyond SystemC and TLM-2.0 for Bigger Systems?"

DVCon China is coming in 2017. Stay tuned for more information coming soon.

SystemC Evolution Day Wrap-up

As a result of the high level of interest in the SystemC birds-of-a-feather session at DVCon Europe 2015, the SystemC user community met again earlier this month for a full day to discuss the evolution of the various SystemC standards. With more than 50 participants, the new Accellera-sponsored technical workshop was sold out, with representatives from more than 20 companies and seven universities in attendance.

The main objective of the SystemC Evolution Day was to identify the areas to align and accelerate the different SystemC standardization initiatives within Accellera and propose solutions for standards inclusion. The workshop started with presentations covering user experiences and standardization proposals in the fields of high-level synthesis, parallel SystemC simulation, transaction-level modeling (TLM) and interactive tracing and debug. In the afternoon, various technical sessions focused on the interaction between multiple SystemC working groups addressing C++11/14 standard adoption, multi-threaded SystemC, TLM for serial interfaces and UVM-SystemC combined with Configuration Control and Inspection (CCI). In a wrap-up session, the main conclusions were shared, including proposals for further standardization. The material and presentations are available for Accellera members active in any of the SystemC working groups.

The participants were all very excited to actively contribute to the success of this workshop. After the positive feedback from the attendees, the organization committee is exploring the best and most effective way to continue the workshop on a regular basis.

Save the Date!

SystemC Japan June 17, 2016 Shin-Yokohama Kokusai Hotel Japan

In its seventh year, SystemC Japan provides a full day of in-depth technical sessions as well as a keynote address and social event in the evening. For more information, visit systemcjapan.com.