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MIG 007 rel 6 - DDR SDRAM controller reads a first value of 'XXXX' from the Read FIFO during behavioral simulation but works correctly in hardware

Description

When doing a behavioral simulation of a MIG 007 DDR SDRAM interface, it appears that data is being written into the read FIFOs one cycle too early during a read operation by the controller. This causes "XXXX" values to be written into the read FIFOs. When looking at the user_output_data signal of the FIFO, the invalid "XXXX" values appear on the output of the data read FIFO during a read operation. This happens during behavioral simulation, but the design works perfectly in hardware.

Why does this happen and is there a way to work around the problem?

Solution

The reason this happens is because the rst_dqs_div, dqs0_delayed_col0(n), and dqs0_delayed_col1(n) signals must be delayed by the user during behavioral simulation to match the delays on these signals in hardware.

Firstly, rst_dqs_div must be delayed to account for the external PCB loop back. In hardware, rst_dqs_div_out is output from the FPGA, loops back on the PCB, and is then input to the FPGA as rst_dqs_div_in. In behavioral simulation, the user should add this delay during behavioral simulation.

Secondly, the dqs0_delayed_col0(n) and dqs0_delayed_col1(n) signals should be delayed to account for the LUT delays placed on the DQS bits in the design's data capture technique. In hardware, the LUT delays properly delay these signals, however, these delays are not included in a behavioral simulation, so the user must manually add the delay. NOTE:This causes issues in some versions of simulators but it might also work in many simulators.

To delay these signals manually to account for both PCB loopback and LUT delay, the following modifications are needed within the data_read_controller_16bit_rl.vhd file: