3. Responsible for power integrity technology research, application analysis, time/frequency domain simulation and test verification methods, research on power integrity analysis and design methods. Responsible for the company's high-end product power design evaluation and power integrity design constraints customization.

Qualifications:

1. Have a good understanding of SerDes, PLL design, LVDS, SSTL, HSTL, CML and other high performance IO technologies. Proficient in system link analysis methods and tools, such as HSPICE, Matlab, ADS, etc., proficient in a 3D modeling tool, such as Ansoft HFSS, CST Microwave studio. Ability to use signal integrity simulation tools such as Heperlynx, SigXplorer, etc. PCB design experience with complex circuits is better.

2. Skilled in using PI analysis and optimization tools for power integrity design, such as Sigrity PowerSI/OPT, Ansoft SIWave, Cadence Allegro PCB PI, etc. Have a good understanding of the test schemes of instruments such as High speed Oscilloscopes, VNA, PNA, TDR, Bit Error rate testers, and Spectrum analyzer.

3. Has a good digital / analog circuit basis, signal integrity and microwave theory basis. Excellent analytical, communication and documentation skills, including English listening, speaking, reading and writing skills. Experience with relevant technical standards in the field of interconnect technology research is preferred, such as IBIS, OIF25G, etc.