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2 Legal Lines and Disclaimers Intel technologies features and benefits depend on system configuration and may require enabled hardware, software or service activation. Learn more at Intel.com, or from the OEM or retailer. No computer system can be absolutely secure. Intel does not assume any liability for lost or stolen data or systems or any damages resulting from such losses. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See for details. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling or by visiting Intel s website at Intel, Xeon, Pentium, Pentium Pro, Pentium 4, Intel Core, Enhanced Intel SpeedStep Technology and the Intel logo are trademarks of Intel Corporation in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright 2015 Intel Corporation. All rights reserved. 2 Intel Xeon Processor E7 v2 Product Family Specification Update, June 2015

5 Preface Preface Nomenclature This document is an update to the specifications contained in the Nomenclature table below. This document is a compilation of device and documentation errata, specification clarifications and changes. It is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. Information types defined in Nomenclature are consolidated into the specification update and are no longer published in other documents. This document may also contain information that was not previously published. S-Spec Number is a five-digit code used to identify products. Products are differentiated by their unique characteristics (for example, core speed, L3 cache size, package type, and so forth) as described in the processor identification information table. Read all notes associated with each S-Spec number. Errata are design defects or errors. These may cause the Intel Xeon Processor E7 v2 Product Family s behavior to deviate from published specifications. Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices. Specification Changes are modifications to the current published specifications. These changes will be incorporated in any new release of the specification. Specification Clarifications describe a specification in greater detail or further highlight a specification s impact to a complex design situation. These clarifications will be incorporated in any new release of the specification. Documentation Changes are modifications to the current published specifications and may include typographical errors, omissions, or incorrect information from the current published specifications. These will be incorporated in the next release of the specification. Documentation changes are removed from the sightings report and/or specification update when the appropriate changes are made to the appropriate product specification or user documentation. Intel Xeon Processor E7 v2 Product Family 5

7 Summary Table of Changes Summary Table of Changes The table included in this section indicates the sightings that apply to the Ivy Bridge-EX Processor. If a sighting becomes a Known Sample Issue, Intel may fix some of the Known Sample Issues in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. Definitions are listed below for terminology used in Table 8 and Table 3. Affected stepping column: Status column: Change bar X: This sighting applies to this stepping. Blank: This sighting is fixed, or does not exist, in the listed stepping. No Fix: Root caused to a silicon issue that will not be fixed. Plan Fix: Root caused to a silicon issue and will be fixed in a future stepping. Fixed: Root caused to a silicon issue and has been fixed in a subsequent stepping. Spec Change: Root caused to a specification error that will be updated. Under Investigation: A root cause has not been determined. Not Reproducible: The sighting could not be reproduced after it was reported. Third Party: Root caused to a board, software, driver, BIOS, or third-party silicon issue. A change bar in the margin indicates a new Known Sample Issue or Sighting for the Ivy Bridge-EX Processor. Intel Xeon Processor E7 v2 Product Family 7

8 Summary Table of Changes Table 1. Summary Table of Changes (Sheet 1 of 6) No. Stepping D1 Status Errata CF1 X No Fix Core Frequencies at or Below the DRAM DDR Frequency May Result in Unpredictable System Behavior. CF2 X No Fix DWORD Aligned XOR DMA Sources May Prevent Further DMA XOR Progress. CF3 X No Fix Rank Sparing May Cause an Extended System Stall. CF4 X No Fix Intel QuickData Technology DMA Lock Quiescent Flow Causes DMA State Machine to Hang. CF5 X No Fix Suspending/Resetting a DMA XOR Channel May Cause an Incorrect Data Transfer on Other Active Channels. CF6 X No Fix Quad Rank DIMMs May Not be Properly Refreshed During IBT_OFF Mode. CF7 X No Fix Intel QuickData Technology Continues to Issue Requests After Detecting 64-bit Addressing Errors. CF8 X No Fix PCIe* TPH Attributes May Result in Unpredictable System Behavior. CF9 X No Fix PCIe* Rx Common Mode Return Loss is Not Meeting the Specification. CF10 X No Fix Intel QuickPath Interconnect (Intel QPI) Tx AC Common Mode Fails Specification. CF11 X No Fix PCIe* Rx DC Common Mode Impedance is Not Meeting the Specification. CF12 X No Fix QPILS Reports the VNA/VN0 Credits Available for the Processor Rx Rather Than Tx. CF13 X No Fix A PECI RdPciConfigLocal Command Referencing a Non-Existent Device May Return an Unexpected Value. CF14 X No Fix The Vswing of the PCIe* Transmitter Exceeds the Specification. CF15 X No Fix PECI Write Requests That Require a Retry Will Always Time Out. CF16 X No Fix The Intel QPI Link Status Register link_init_status Field Incorrectly Reports Internal Stall Link Initialization for Certain Stall Conditions. CF17 X No Fix The Processor Does Not Detect Intel QPI RSVD_CHK Field Violations. CF18 X No Fix CF19 X No Fix Intel QuickData Technology DMA Non-Page-Aligned Next Source/ Destination Addresses May Result in Unpredictable System Behavior. Intel QPI May Report a Reserved Value in The Link Initialization Status Field During Link Training. CF20 X No Fix Enabling Opportunistic Self-Refresh and Pkg C2 State Can Severely Degrade PCIe* Bandwidth. CF21 X No Fix Functionally Benign PCIe* Electrical Specification Violation Compendium. CF22 X No Fix CF23 X No Fix CF24 X No Fix CF25 X No Fix CF26 X No Fix CF27 X No Fix CF28 X No Fix Patrol Scrubbing During Memory Mirroring May Improperly Signal Uncorrectable Machine Checks. A Modification To The Multiple Message Enable Field Does Not Affect The AER Interrupt Message Number Field. Long latency Transactions Can Cause I/O Devices On The Same Link to Time Out. Coherent Interface Write Cache May Report False Correctable ECC Errors During Cold Reset. Combining ROL Transactions With Non-ROL Transactions or Marker Skipping Operations May Result in a System Hang. Excessive DRAM RAPL Power Throttling May Lead to a System Hang or USB Device Offlining. TSOD-Related SMBus Transactions may not Complete When Package C- States are Enabled. 8 Intel Xeon Processor E7 v2 Product Family

9 Summary Table of Changes Table 1. Summary Table of Changes (Sheet 2 of 6) No. Stepping D1 Status Errata CF29 X No Fix CF30 X No Fix The Integrated Memory Controller does not Enforce CKE High For txsdll DCLKs After Self-Refresh. Intel QuickData Technology DMA Suspend does not Transition From ARMED to HALT State. CF31 X No Fix Routing Intel High Definition Audio Traffic Through VC1 May Result in System Hang. CF32 X No Fix Patrol Scrubbing does not Skip Ranks Disabled After DDR Training. CF33 X No Fix CF34 X No Fix DR6.B0-B3 May Not Report All Breakpoints Matched When a MOV/POP SS is Followed by a REP MOVSB or STOSB 64-bit REP MOVSB/STOSB May Clear The Upper 32-bits of RCX, RDI And RSI Before Any Data is Transferred CF35 X No Fix An Interrupt Recognized Prior to First Iteration of REP MOVSB/STOSB May Result EFLAGS.RF Being Incorrectly Set CF36 X No Fix Instructions Retired Event May Over Count Execution of IRET Instructions CF37 X No Fix CF38 X No Fix An Event May Intervene Before a System Management Interrupt That Results from IN or INS Execution of VAESIMC or VAESKEYGENASSIST With An Illegal Value for VEX.vvvv May Produce a #NM Exception CF39 X No Fix An Event May Intervene Before a System Management Interrupt That Results from IN or INS CF40 X No Fix Successive Fixed Counter Overflows May be Discarded CF41 X No Fix CF42 X No Fix Execution of FXSAVE or FXRSTOR With the VEX Prefix May Produce a #NM Exception VM Exits Due to NMI-Window Exiting May Not Occur Following a VM Entry to the Shutdown State CF43 X No Fix Execution of INVVPID Outside 64-Bit Mode Cannot Invalidate Translations For 64-Bit Linear Addresses CF44 X No Fix REP MOVSB May Incorrectly Update ECX, ESI, and EDI CF45 X No Fix Performance-Counter Overflow Indication May Cause Undesired Behavior CF46 X No Fix VEX.L is not Ignored with VCVT*2SI Instructions CF47 X No Fix Concurrently Changing the Memory Type and Page Size May Lead to a System Hang CF48 X No Fix MCI_ADDR May be Incorrect For Cache Parity Errors CF49 X No Fix CF50 X No Fix CF51 X No Fix Instruction Fetches Page-Table Walks May be Made Speculatively to Uncacheable Memory REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory-Ordering Violations The Processor May Not Properly Execute Code Modified Using a Floating- Point Store CF52 X No Fix VM Exits Due to GETSEC May Save an Incorrect Value for Blocking by STI in the Context of Probe-Mode Redirection CF53 X No Fix IA32_MC5_CTL2 is Not Cleared by a Warm Reset CF54 X No Fix The Processor May Report a #TS Instead of a #GP Fault CF55 X No Fix IO_SMI Indication in SMRAM State Save Area May be Set Incorrectly CF56 X No Fix Performance Monitor SSE Retired Instructions May Return Incorrect Values Intel Xeon Processor E7 v2 Product Family 9

10 Summary Table of Changes Table 1. Summary Table of Changes (Sheet 3 of 6) No. Stepping D1 Status Errata CF57 X No Fix CF58 X No Fix CF59 X No Fix CF60 X No Fix IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count Some Transitions General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be Preempted LBR, BTS, BTM May Report a Wrong Address When an Exception/Interrupt Occurs in 64-bit Mode CF61 X No Fix Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR or XSAVE/ XRSTOR Image Leads to Partial Memory Update CF62 X No Fix Values for LBR/BTS/BTM Will be Incorrect after an Exit from SMM CF63 X No Fix EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a Translation Change CF64 X No Fix B0-B3 Bits in DR6 For Non-Enabled Breakpoints May be Incorrectly Set CF65 X No Fix MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error CF66 X No Fix Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled Breakpoints CF67 X No Fix LER MSRs May be Unreliable CF68 X No Fix Storage of PEBS Record Delayed Following Execution of MOV SS or STI CF69 X No Fix PEBS Record Not Updated When in Probe Mode CF70 X No Fix Faulting MMX Instruction May Incorrectly Update x87 FPU Tag Word CF71 X No Fix #GP on Segment Selector Descriptor That Straddles Canonical Boundary May Not Provide Correct Exception Error Code CF72 X No Fix APIC Error Received Illegal Vector May Be Lost CF73 X No Fix CF74 X No Fix CF75 X No Fix CF76 X No Fix CF77 X No Fix CF78 X No Fix CF79 X No Fix CF80 X No Fix CF81 X No Fix CF82 X No Fix CF83 X No Fix Changing the Memory Type for an In-Use Page Translation May Lead to Memory-Ordering Violations Reported Memory Type May Not be Used to Access the VMCS and Referenced Data Structures LBR, BTM or BTS Records May have Incorrect Branch From Information After an Enhanced Intel SpeedStep Technology/T-state/S-state/C1E Transition or Adaptive Thermal Throttling FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64-bit Mode VMREAD/VMWRITE Instruction May Not Fail When Accessing an Unsupported Field in VMCS An Unexpected PMI May Occur After Writing a Large Value to IA32_FIXED_CTR2 A Write to the IA32_FIXED_CTR1 MSR May Result in Incorrect Value in Certain Conditions #GP May be Signaled When Invalid VEX Prefix Precedes Conditional Branch Instructions Interrupt From Local APIC Timer May Not be Detectable While Being Delivered PCMPESTRI, PCMPESTRM, VPCMPESTRI and VPCMPESTRM Always Operate with 32-bit Length Registers During Package Power States Repeated PCIe* and/or DMI L1 Transitions May Cause a System Hang 10 Intel Xeon Processor E7 v2 Product Family

11 Summary Table of Changes Table 1. Summary Table of Changes (Sheet 4 of 6) No. Stepping D1 Status Errata CF84 X No Fix RDMSR of IA32_PERFEVTSEL4-7 May Return an Incorrect Result CF85 X No Fix MONITOR or CLFLUSH on the Local XAPIC's Address Space Results in Hang CF86 X No Fix PCMPESTRI, PCMPESTRM, VPCMPESTRI and VPCMPESTRM Always Operate With 32-bit Length Registers CF87 X No Fix Clock Modulation Duty Cycle Cannot Be Programmed to 6.25% CF88 X No Fix Processor May Livelock During On Demand Clock Modulation CF89 X No Fix Performance Monitor Counters May Produce Incorrect Results CF90 X No Fix Virtual-APIC Page Accesses with 32-Bit PAE Paging May Cause a System Crash CF91 X No Fix IA32_FEATURE_CONTROL MSR May be Un-Initialized on a Cold Reset CF92 X No Fix PEBS May Unexpectedly Signal a PMI After the PEBS Buffer is Full CF93 X No Fix Execution of GETSEC[SEXIT] May Cause a Debug Exception to Be Lost CF94 X No Fix CF95 X No Fix An Uncorrectable Error Logged in IA32_MC2_STATUS May also Result in a System Hang The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is Not Updated When the UC Bit is Set CF96 X No Fix IA32_VMX_VMCS_ENUM MSR (48AH) Does Not Properly Report the Highest Index Value Used for VMCS Encoding CF97 X No Fix The Upper 32 Bits of CR3 May be Incorrectly Used With 32-Bit Paging CF98 X No Fix EPT Violations May Report Bits 11:0 of Guest Linear Address Incorrectly CF99 X No Fix Intel QuickData Technology DMA Access to Invalid Memory Address May Cause System Hang CF100 X No Fix CPUID Faulting is Not Enumerated Properly CF101 X No Fix TSC is Not Affected by Warm Reset CF102 X No Fix PECI_WAKE_MODE is Always Reported as Disabled CF103 X No Fix Poisoned PCIe* AtomicOp Completions May Return an Incorrect Byte Count CF104 X No Fix Incorrect Speed and De-emphasis Level Selection During DMI Compliance Testing CF105 X No Fix PCIe* Device 3 Does Not Log an Error in UNCERRSTS When an Invalid Sequence Number in an Ack DLLP is Received CF106 X No Fix Programmable Ratio Limits For Turbo Mode is Reported as Disabled CF107 X No Fix PCIe* TLPs in Disabled VC Are Not Reported as Malformed CF108 X No Fix PCIe* Link May Fail to Train to 8.0 GT/s CF109 X No Fix PCIe* Header of a Malformed TLP is Logged Incorrectly CF110 X No Fix PCIe* May Associate Lanes That Are Not Part of Initial Link Training to L0 During Upconfiguration CF111 X No Fix Single PCIe* ACS Violation or UR Response May Result in Multiple Correctable Errors Logged CF112 X No Fix PCIe* Extended Tag Field May be Improperly Set CF113 X No Fix Power Meter May Under-Estimate Package Power CF114 X No Fix DTS2.0 May Report Inaccurate Temperature Margin CF115 X No Fix A DMI UR May Unexpectedly Cause a CATERR# After a Warm Reset CF116 X No Fix PECI May Not be Able to Access IIO CSRs Intel Xeon Processor E7 v2 Product Family 11

16 Identification Information Identification Information Component identification The Ivy Bridge-EX Processor stepping can be identified by the following register contents. Table 7. Intel Xeon Processor E7 v2 Product Family signature/version Reserved Extended family 1 Extended model 2 Reserved Processor type 3 Family code 4 Model number 5 Stepping ID 6 31:28 27:20 19:16 15:14 13:12 11:8 7:4 3: b 0011b 00b 0110b 1110b D1=0111b Notes: 1. The Extended Family, bits [27:20] are used in conjunction with the Family Code, specified in bits [11:8], to indicate whether the processor belongs to the Intel386, Intel486, Pentium, Pentium Pro, Pentium 4, Intel Core processor family, or Intel Core i7 family. 2. The Extended Model, bits [19:16] in conjunction with the Model Number, specified in bits [7:4], are used to identify the model of the processor within the processor s family. 3. The Processor Type, specified in bits [13:12] indicates whether the processor is an original OEM processor, an OverDrive processor, or a dual processor (capable of being used in a dual processor system). 4. The Family Code corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan. 5. The Model Number corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID register accessible through Boundary Scan. 6. The Stepping ID in bits [3:0] indicates the revision number of that model. See Table 8 for the processor stepping ID number in the CPUID information. When EAX is initialized to a value of 1, the CPUID instruction returns the Extended Family, Extended Model, Processor Type, Family Code, Model Number, and Stepping ID in the EAX register. Note that the EDX processor signature value after reset is equivalent to the processor signature output value in the EAX register. Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX, and EDX registers after the CPUID instruction is executed with a 2 in the EAX register. 16 Intel Xeon Processor E7 v2 Product Family

19 Errata CF1 Core Frequencies at or Below the DRAM DDR Frequency May Result in Unpredictable System Behavior. The Enhanced Intel SpeedStep Technology can dynamically adjust the core operating frequency to as low as 1200 MHz. Due to this erratum, under complex conditions and when the cores are operating at or below the DRAM DDR frequency, unpredictable system behavior may result. Implication: Systems using Enhanced Intel SpeedStep Technology with DDR or DDR memory devices are subject to unpredictable system behavior. Workaround: It is possible for the BIOS to contain a workaround for this erratum. CF2 DWORD Aligned XOR DMA Sources May Prevent Further DMA XOR Progress. XOR DMA channels may stop further progress in the presence of Locks/PHOLDs if the source pointed to by a DMA XOR descriptor is not cacheline aligned. Implication: Non-cacheline aligned DMA XOR sources may hang both channels 0 and 1. A reset is required in order to recover from the hang. Legacy DMA descriptors on any channel have no source alignment restrictions. Workaround: Software must either: Ensure XOR DMA descriptors only point to cacheline aligned sources (best performance) OR A legacy DMA copy must be used prior to non-cacheline aligned DMA operations to guarantee that the source misalignment is on DWORD15 of the cacheline. The required source that must be misaligned to DWORD15, depends on the following desired subsequent DMA XOR operations: DMA XOR Validate (RAID5/ P-Only): The P-source must be misaligned to DWORD15 (last DWORD). DMA XOR Validate (RAID6/P+Q): The Q-source must be misaligned to DWORD15 (last DWORD). DMA XOR Generate or Update: The last source (which will be different based on numblk) must be misaligned to DWORD15 (last DWORD). CF3 Rank Sparing May Cause an Extended System Stall. The Integrated Memory Controller sequencing during a rank sparing copy operation blocks all writes to the memory region associated with the rank being taken out of service. Due to this erratum, this block can result in a system stall that persists until the sparing copy operation completes. Implication: The system can stall at unpredictable times which may be observed as one time instance of system unavailability. Workaround: A BIOS workaround has been identified. Refer to Intel Xeon Processor E7 v2 Product Family-based Platform CPU/Intel QPI/Memory Reference Code version or later and release notes. Intel Xeon Processor E7 v2 Product Family 19

20 CF4 Intel QuickData Technology DMA Lock Quiescent Flow Causes DMA State Machine to Hang. The lock quiescent flow is a means for an agent to gain sole ownership of another agent's resources by preventing other devices from sending transactions. Due to this erratum, during the lock quiescent flow, the Intel QuickData Technology DMA read and write queues are throttled simultaneously. This prevents subsequent read completions from draining into the write queue, hanging the DMA lock state machine. Implication: The DMA lock state machine may hang during a lock quiescent flow. Workaround: Fix was provided in Reference Code version or later. CF5 Suspending/Resetting a DMA XOR Channel May Cause an Incorrect Data Transfer on Other Active Channels. Suspending an active DMA XOR channel by setting CHANCMD.Suspend DMA bit (Offset 84; Bit 2) while XOR type DMA channels are active may cause incorrect data transfer on the other active legacy channels. This erratum may also occur while resetting an active DMA XOR channel CHANCMD.Reset DMA bit (Offset 84; Bit 5). CHANCMD is in the region described by CB_BAR (Bus 0; Device 4; function 0-7; Offset 10H). Implication: Due to this erratum, an incorrect data transfer may occur on the active legacy DMA channels. Workaround: Software must suspend all legacy DMA channels before suspending an active DMA XOR channel (channel 0 or 1). CF6 Quad Rank DIMMs May Not be Properly Refreshed During IBT_OFF Mode. The Integrated Memory Controller incorporates a power savings mode known as IBT_OFF (Input Buffer Termination disabled). Due to this erratum, Quad Rank DIMMs may not be properly refreshed during IBT_OFF mode. Implication: Use of IBT_OFF mode with Quad Rank DIMMs may result in unpredictable system behavior. Workaround: A BIOS workaround has been identified. Refer to Intel Xeon Processor E7 v2 Product Family-based Platform CPU/Intel QPI/Memory Reference Code version or later and release notes. CF7 Intel QuickData Technology Continues to Issue Requests After Detecting 64-bit Addressing Errors. Intel QuickData Technology uses the lower 48 address bits of a 64-bit address field. Detection of accesses to source address, destination address, descriptor address, chain address, or completion address outside of this 48-bit range are flagged as 64-bit addressing errors and should halt DMA processing. Due to this erratum, the Intel QuickData Technology DMA continues to issue requests after detecting certain 64-bit addressing errors involving RAID operations. The failing condition occurs for 64-bit addressing errors in either a Channel Completion Upper Address Register (CHANCMP_0, CHANCMP_1) (Bus 0; MMIO BAR CB_BAR [0:7]; Offset 98H, 9CH), or in the source or destination addresses of a RAID descriptor. Implication: Programming out of range DMA address values may result in unpredictable system behavior. Workaround: Ensure all RAID descriptors, CHANCMP_0, and CHANCMP_1 addresses are within the 48-bit range before starting the DMA engine. 20 Intel Xeon Processor E7 v2 Product Family

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