Hi,
We have a motherboard with the Intel 6700PXH 64-bit PCI Hub chip. As I understand the chip automatically selects between 33/66/100/133MHz bus rates based on the slowest PCI card installed. Is there a way to monitor/read-out what the selected bus speed is?
Thanks!
Chris

I'm trying to run the Intel Power Gadget on a Win 8.1 x64 system with a Core i7-720QM. The program and the MS Visual C++ 2010 redistributable library appear to install OK, but the tool will not start. I try launching it, and nothing happens. I attached windbg to the executable, but did not learn anything. I also investigated it with Process Monitor and Dependency Walker, but couldn't get to the bottom of it.
The same utility runs fine on a different computer. Curiously, I might have not installed the MSVC 2012 redistributable on that PC. I don't see it listed in Programs and Features. The power gadget runs just fine though.
Any ideas?

Hello,
the documentation of the Intel Memory Latency Checker states that with the option -bXXX you can specify the buffer size. For example to measure caches instead of DRAM. But this option will not considered for execution. The print message "Using buffer size of" as well as the measures values indicate that it not works. For example mlc --idle_latency –b3000 –c0 –t3 out of the documentation will not work. Is there a workaround?
Kind regards,
Steffen

Hello,
I see the Linux kernel didn't go the hardware route for process switching in ring 0 (kernel).
Could one gain a lot by using it ? It is said to be slower than software context switch.
Seems strange to me.
Any performance pointer ?
Thanks

Hello,
In 64-ia-32-architectures-optimization-manual, chapter B.3.7.2 Understanding the Sources of the Micro-op Queue it is said that UOPs come from DSB, MITE and MS, and a 'typical distribution' is given. It happens so that in the app I'm profiling quite a lot more UOPs are dispatched from MS than suggested as desirable by Intel in the manual while the execution is clearly front-end bound.
The problem is, I don't understand why that happens. The manual reads:
A large portion of micro-ops coming from the microcode sequencer may be benign, such as complex instructions, or string operations, but can also be due to code assists handling undesired situations like Intel SSE to Intel AVX code transitions.
But I am pretty sure there aren't any SSE/AVX instructions employed at all, nor could 'denormals' or string operations occur often enough to produce any notable amount of stirring (the code mainly works with integer values).
Is there a complete list of instructions that actually cause M...

Hello all,
I'm novice on using PEBS facility and I am trying to use "long latency loads" facility and want to dump "raw PEBS records" for further analysis.
For writing a simple example, I referenced SDM v3, especially on 18.8.4.1 through 18.8.4.3 (for Sandy Bridge).
When testing, counting long latency loads counter normally works, but PEBS recording does not correctly works.
In the test, I fount that PMCx reset value for adjusting sampling rate does not correctly working, specifically it does not overflow at all for too low counts.
According to SDM v3, it needs to trigger overflow to "arm PEBS facility" and to set "PEBS Counter X Reset" for triggering PEBS counters repeatedly.
However, even with set of "PEBS Counter X Reset" in high value (0xFFFFFFFFFF00 in my case), PMCx does not appear to correctly set as preset value in Debug Store Area (0x40H ~ 0x58H), even after first overflow of PMCx.
I was trying to find simple examples on this, but it is hard to find the example that in...