Abstract

The principles of an automated cross-talk extractor from the mask-level description of a CMOS integrated circuit are detailed. The physical extraction principles, the techniques for parasitic coupling evaluation and modeling, the technique for back-annotating the schematic diagram of the integrated circuit are presented. A model for mixed-level simulation is proposed, covering various parasitic effects of the cross-talk phenomenon. The efficiency of the cross-talk extractor is demonstrated through the analysis of mixed digital/analog CMOS integrated circuits where critical couplings are predicted and eliminated