Kickstarter

The initial run of Parallella computers is being funded via a Kickstarter campaign, which on 27th October 2012 had succeeded in raising $898,921 via 4,965 backers, and with those pledging $99 or more receiving at least one board.

Thanks to generous support from Xilinx the Kickstarter boards will be upgraded to use a Zynq-7020 SoC instead of a Zynq-7010.

General availability

Work is being done to put distribution in place, however, a date for post-Kickstarter orders has not been confirmed yet and in the meantime interest can be registered using a form on the project website.

Revisions

A 66-Core Parallella Prototype

Prototypes

The first Parallella prototypes shipped in late December 2012 and comprise of a ZedBoard plus a 16 or 64-core Epiphany FMC.

From a software perspective the prototypes are virtually identical to the final form factor boards.

Beta boards

The first 10 Parallella beta boards came back from assembly on 11th April 2013 and were unveiled four days later at the Linux Foundation Collaboration Summit.

Specifications

Please note that these are preliminary specifications and subject to change.

includes 48 bidirectional signals that can be configured within the Zynq device to support a number of different signal standards. When configured as LVDS signals, each differential signal pair provides a maximum bandwidth of 950Mbps. In aggregate, the PEC_FPGA connections can provide 22Gbps of total I/O bandwidth.

PEC_NORTH/PEC_SOUTH expansion:

3.2GB/s total I/O bandwidth via 2.5V LVDS

2.8GB/s total I/O bandwidth via 1.8V subLVDS

Real-time clock:

None

Power source:

5 V (DC) at 1A

Size:

3.4" x 2.15"

Documentation

Comprehensive documentation is being made available without the need for any special access or NDAs.