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AR# 43775

13.2 EDK - Does the AXI user logic master support a length width greater than 12?

Description

The AXI user logic master only supports a master length width of 12. Even if I change the C_MST_LENGTH_WIDTH parameter, I still see some errors while trying to configure them.

Solution

Any other value selected while configuring the master interface of the user logic peripheral is not reflected in the user_logic.vhd signal description. For example, the signal 'mst_xfer_length' and 'mst_xfer_length' array lenghts are fixed (11 down to 0). Instead, the lengths should be (C_MST_LENGTH_WIDTH-1 downto 0). The C_MST_LENGTH_WIDTH parameter is a generic one and it gets the value from its top module.

This is planned to be fixed in EDK 13.3 to allow values greater than 12.