We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Firefox,
Internet Explorer 11,
Safari. Thank you!

Description

General Description:If the Project Navigator synthesis flow is set to Synplify_Pro (VHDL) and a package is used, the synthesis could fail if the "compiling" Library is different from the default work Library.

Solution

The work-around for this problem is to compile the package in the default work Library. This can be done in the Project Navigator under Synthesize -> Process Properties -> VHDL Specific Options -> Set Library -> work, or delete this field, because the default Library is the work Library.