10.17 Summary

Table 10.27 shows
the essential elements of the VHDL language. Table 10.28 shows the
most important BNF definitions and their locations in this chapter. The
key points covered in this chapter are as follows:

The use of an entity and an architecture

The use of a configuration to bind entities and their
architectures

The compile, elaboration, initialization, and simulation steps

Types, subtypes, and their use in expressions

The logic systems based on BIT and Std_Logic_1164
types

The use of the IEEE synthesis packages for BIT arithmetic

Ports and port modes

Initial values and the difference between simulation and hardware

The difference between a signal and a variable

The different assignment statements and the timing of updates

The process and wait statements

VHDL is a "wordy"
language. The examples in this chapter are complete rather than code fragments.
To write VHDL "nicely," with indentation and nesting of constructs,
requires a large amount of space. Some of the VHDL code examples in this
chapter are deliberately dense (with reduced indentation and nesting), but
the bold keywords help you to see the code structure. Most of the time,
of course, we do not have the luxury of bold fonts (or color) to highlight
code. In this case, you should add additional space, indentation, nesting,
and comments.