SIMULATION BASED LOW POWER TEST GENERATION FOR CROSSTALK DELAY FAULTS

Keywords

Abstract

Crosstalk faults in deep submicron cause severe design validation and test problems. Further power consumption during testing is becoming a critical factor. The proposed Weighted Sum Genetic Algorithm (WSGA) based Automatic Test Pattern Generation (ATPG) for crosstalk induced delay faults generates test sequences that has high-fault coverage with reduced power consumption. The eﬀectiveness of various crossover operators was analysed. Experimental
results with ISCAS 85 and scan version of ISCAS 89 benchmark circuits demonstrate that the proposed WSGA based ATPG with Weight based Crossover Operator (WCO) provides compact test vectors that have higher fault coverage with minimum number of transitions for most of the benchmark circuits when compared with those generated by Genetic Algorithm (GA) based ATPG.