MEMS may still be largely a one product, one process business, but customers across diverse applications share a common set of demands for smaller devices with better performance at lower cost.

And that will drive the industry towards new assembly solutions for tighter integration and more standard process modules over the next decade. Yole Développement see most common applications shrinking to 1mm2 or 2mm2 die or smaller by 2020, and price points continuing on a sharp downward path, driving demand for 3D TSV, active capping, thin film capping, and CMOS MEMS technologies going forward. Cost and time-to-market pressures will also favor increased reliance on standard process modules….

The biggest change coming down the pipeline is chip stacking with through-silicon vias This 3D TSV technology is now starting production for those few applications where users are willing to pay the higher cost to get the better performance and smaller size from the shorter connections. Yole projects demand for MEMS with 3D TSV will reach several hundred thousand wafers a year by 2015.

Early uses of the TSV technology are as varied as microphones from Sonion and fingerprint readers from IDTECK/ STMicroelectronics. MEMS foundries Dalsa, Silex and Xintec are running the 3D process for various applications that include gyros, microphones and oscillators for customers like InvenSense, VTI, Epcos, and SiTime. Yole has indentified at least 20 companies developing TSV for MEMS, spread across the value chain from MEMS foundries, packaging houses, and IDMS.

But another technology also starting to change the integration game is wafer-level bonding or active capping, bonding the ASIC wafer to directly to the MEMS wafer as a functional cap. InvenSense has led the way with its unique metal-to-metal bonding of the ASIC to the MEMS with AlGe, which efficiently and compactly makes both the connection and the hermetic seal for its consumer gyroscopes. But other sensor makers are expecte to develop wafer level bonding approaches as well.

Also coming into wider use to shrink device size and cost is thin film capping, where the wafer with released MEMS devices is sealed under an encapsulation layer. Though the high temperature encapsulation process developed by Bosch with Stanford University was originally seen by some as a step towards building CMOS on top of MEMS, —the process has turned out to be most useful for wafer-level encapsulation to shrink die size. The

thin film cap layer eliminates the need to devote wafer surface area to all the framing frit lines usually used for bonding on the glass or silicon cap wafers, making it particularly useful for ultra small devices like oscillators and RF MEMS. SiTime is using the thin film capping for its oscillators, and Bosch is now using the technology in a least one of its accelerometer products. MEMtronics uses a different thin film capping process on its RF MEMS devices, while RFMD, WiSpry, ASE and CEA Leti are all also developing capping films.

More CMOS-MEMS and standard process modules coming too

These alternative TSV and capping technologies get some of the gains of shorter electrical connections between the MEMS and ASIC of the CMOS MEMS approach without having to deal with the many complexities of monolithic integration. But real onechip solutions –with the MEMS layers made before, during or after the CMOS layers—may further improve performance and reduce size and cost, in part by using the existing CMOS infrastructure and avoiding the cost of separate assembly of the MEMS with the ASIC. Though of course wire- bonded, twochip system-in-a-package solutions offer lower costs in other cases, especially for small volumes, as well as greater design flexibility in using different chips.

Going forward, all MEMS array devices that need to control each pixel individually will require CMOS MEMS, as do micromirror digital light processors or microbolometerswhich build the MEMS directly above the CMOS. The very small geometries in nano MEMS chemical sensors will also likely require monolithic integration. A lineup of startups has also turned to some flavor of CMOS MEMS in recent years in hopes of disruptive advantage in lower costs and faster volume ramps, from Akustica and MEMSiC to Silicon Clocks and now Baolab.

The growing use of MEMS’ own standard process modules may, however, also start to challenge CMOS-MEMS’ purported advantage in established processes and faster ramp to volume. As the industry has matured, both the IDMs and the MEMS foundries have built up repertoires of wellcharacterized process blocks that can be used again in other devices. Back end processes modules for things like wafer-level packaging and TSVs were the easiest and first to be applied across products, but the approach is also now being extended to things like silicon membranes. CEA-Leti and Silex are most vocal about the advantages of standard modules, but we hear a similar story from most of the other leading MEMS foundries, and from IDMs like STMicroelectronics, who forces almost all its MEMS devices into one of two established process flows.