Long design cycles due to the inability to predict
silicon realities are a well-known problem that plagues analog/RF
integrated circuit product development. As this problem worsens
for nanoscale IC technologies, the high cost of design and multiple
manufacturing spins causes fewer products to have the volume
required to support full-custom implementation. Design reuse
and analog synthesis make analog/RF design more affordable;
however, the increasing process variability and lack of modeling
accuracy remain extremely challenging for nanoscale analog/RF
design. We propose a regular analog/RF IC using metal-mask
configurability design methodology Optimization with Recourse of
Analog Circuits including Layout Extraction (ORACLE), which
is a combination of reuse and shared-use by formulating the
synthesis problem as an optimization with recourse problem. Using a
two-stage geometric programming with recourse approach,
ORACLE solves for both the globally optimal shared and
application-specfic variables. Furthermore, robust optimization is
proposed to treat the design with variability problem, further enhancing
the ORACLE methodology by providing yield bound for
each configuration of regular designs. The statistical variations of
the process parameters are captured by a confidence ellipsoid. We
demonstrate ORACLE for regular Low Noise Amplifier designs
using metal-mask configurability, where a range of applications
share common underlying structure and application-specific
customization is performed using the metal-mask layers. Two RF
oscillator design examples are shown to achieve robust designs
with guaranteed yield bound.