Thanks to this the input files $(OBJDIR)/%$(OBJEXT) will be created from $(SRCDIR)/%$(SRCEXT). The % sign symbolizes currently processed file name, so all it does is replaces ./src/<file>.c to ./bin/<file>.o.

I’ve added the all, run and clean rules and new variables: $(LD)/$(LDFLAGS) and $(CC)/$(CCFLAGS) for linker/flags and compiler/flags and a new rule for creating $(OBJDIR) if it doesn’t exist yet ($(OBJDIR) is often removed by the clean rule).

There’s also a $(OBJDIR) for specifying output directory and $(OBJEXT) for object file extension. The @ sign mutes printing of currently executed command (we only want the output).

This makefile is pretty much done but it still won’t work because these variables are never defined. We can change that with some shell commands.