Mesgarzadeh, Behzad

Abstract [en]

Today’s microprocessors with millions of transistors perform high-complexitycomputing at multi-gigahertz clock frequencies. Clock generation and clockdistribution are crucial tasks which determine the overall performance of amicroprocessor. The ever-increasing power density and speed call for newmethodologies in clocking circuitry, as the conventional techniques exhibit manydrawbacks in the advanced VLSI chips. A significant percentage of the total dynamicpower consumption in a microprocessor is dissipated in the clock distributionnetwork. Also since the chip dimensions increase, clock jitter and skew managementbecome very challenging in the framework of conventional methodologies. In such asituation, new alternative techniques to overcome these limitations are demanded.

The main focus in this thesis is on new circuit techniques, which treat thedrawbacks of the conventional clocking methodologies. The presented research in thisthesis can be divided into two main parts. In the first part, challenges in design ofclock generators have been investigated. Research on oscillators as central elements inclock generation is the starting point to enter into this part. A thorough analysis andmodeling of the injection-locking phenomenon for on-chip applications show greatpotential of this phenomenon in noise reduction and jitter suppression. In thepresented analysis, phase noise of an injection-locked oscillator has been formulated.The first part also includes a discussion on DLL-based clock generators. DLLs haverecently become popular in design of clock generators due to ensured stability,superior jitter performance, multiphase clock generation capability and simple designprocedure. In the presented discussion, an open-loop DLL structure has beenproposed to overcome the limitations introduced by DLL dithering around the averagelock point. Experimental results reveals that significant jitter reduction can beachieved by eliminating the DLL dithering. Furthermore, the proposed structuredissipates less power compared to the traditional DLL-based clock generators.Measurement results on two different clock generators implemented in 90-nm CMOSshow more than 10% power savings at frequencies up to 2.5 GHz.

In the second part of this thesis, resonant clock distribution networks have beendiscussed as low-power alternatives for the conventional clocking schemes. In amicroprocessor, as clock frequency increases, clock power is going to be thedominant contributor to the total power dissipation. Since the power-hungry bufferstages are the main source of the clock power dissipation in the conventional clock distribution networks, it has been shown that the bufferless solution is the mosteffective resonant clocking method. Although resonant clock distribution shows greatpotential in significant clock power savings, several challenging issues have to besolved in order to make such a clocking strategy a sufficiently feasible alternative tothe power-hungry, but well-understood, conventional clocking schemes. In this part,some of these issues such as jitter characteristics and impact of tank quality factor onoverall performance have been discussed. In addition, the effectiveness of theinjection-locking phenomenon in jitter suppression has been utilized to solve the jitterpeaking problem. The presented discussion in this part is supported by experimentalresults on a test chip implemented in 130-nm CMOS at clock frequencies up to 1.8GHz.

Abstract [en]

The paper presents an analysis of the injection locking phenomenon in CMOS ring oscillators. Adler's equation in injection locking is proved for a three-stage ring oscillator and the behavior of this kind of oscillator in the locked condition with respect to phase noise and jitter reduction has been analyzed.

Abstract [en]

This paper presents an analysis of first-harmonic injection locking in CMOS ring oscillators. In this analysis, Adler's equation is proved by using a new analytical approach based on the propagation delay of an inverter stage. Also the behavior of the injection-locked ring oscillators from phase noise point of view is discussed and a closed-form equation for the phase noise of such oscillators is derived. According to the measurement results on a DLL-based frequency multiplier implemented in 0.13-mum CMOS process, good agreement between theoretical prediction and measurements is observed

Abstract [en]

This paper presents a detailed clock jitter characteristic analysis of a fully integrated 1.5-GHz resonant clocking fabricated in 130-nm CMOS, with 57% total clock power saving, compared to the conventional clocking implemented in the same test-chip. The jitter measurement result is in good agreement with the jitter analysis. Furthermore, a jitter-suppression technique based on injection locking phenomenon has been utilized to reduce the clock jitter and to solve the jitter peaking problem. Measurements show about 50% peak-to-peak clock jitter reduction from 28.4 ps to 14.5 ps after the activation of the injection locking.

Abstract [en]

This paper is focused on analysis and suppression of clock jitter in charge recovery resonant clock distribution networks. In the presented analysis, by considering the data-dependent nature of the generated jitter, the reason for the undesired jitter-peaking phenomenon is investigated. The analysis has been verified by measurements on a test chip fabricated in 0.13-mum standard CMOS process. The chip includes a fully integrated 1.5-GHz LC clock resonator with a passive (bufferless) clock distribution network, which directly drives the clocked devices in pipelined data path circuits. Furthermore, a jitter suppression technique based on injection locking is presented. Measurement results show about 50% peak-to-peak clock jitter reduction from 28.4 ps down to 14.5 ps after injection locking.

Abstract [en]

The major design challenges toward a highly power- efficient bufferless resonant clock distribution network is discussed. The presented discussion is supported by measurements on three different clock distribution networks implemented in a test chip fabricated in 0.13-mum standard CMOS process. In addition to presenting a detailed power comparison between these networks and the conventional buffer-driven scheme, the clock jitter characteristic in bufferless clock distribution is discussed. Furthermore, injection-locking phenomenon is utilized to suppress data- dependent jitter and to achieve a low-jitter clock distribution.