We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Firefox,
Internet Explorer 11,
Safari. Thank you!

Solution

In the example above, the subb_0014 sub block has 2 ports of type bit_vector. The component subb_0014 declared in the ex_0014 has 2 ports of a different type: std_logic_vector. This is not a VHDL LRM compliant code.