Sign up to receive free email alerts when patent applications with chosen keywords are publishedSIGN UP

Abstract:

Three-dimensional (3D) semiconductor memory devices are provided.
According to the 3D semiconductor memory device, a gate structure
includes gate patterns and insulating patterns alternately stacked on a
semiconductor substrate. A vertical active pattern penetrates the gate
structure. A gate dielectric layer is disposed between a sidewall of the
vertical active pattern and each of the gate patterns. A semiconductor
pattern is disposed on the gate structure and is connected to the
vertical active pattern. A string drain region is formed in a portion of
the semiconductor pattern and is spaced apart from the vertical active
pattern.

Claims:

1. A three-dimensional (3D) semiconductor memory device comprising: a
gate structure including gate patterns and insulating patterns
alternately stacked on a semiconductor substrate; a vertical active
pattern penetrating the gate structure; a gate dielectric layer disposed
between a sidewall of the vertical active pattern and each of the gate
patterns; a semiconductor pattern disposed on the gate structure, the
semiconductor pattern connected to the vertical active pattern; and a
string drain region formed in a portion of the semiconductor pattern, the
string drain region spaced apart from the vertical active pattern.

2. The 3D semiconductor memory device of claim 1, wherein an uppermost
gate pattern of the gate patterns is configured to control a vertical
channel region defined in the vertical active pattern and a horizontal
channel region defined in the semiconductor pattern; wherein the vertical
channel region is connected to one end of the horizontal channel region;
and wherein the string drain region is connected to another end of the
horizontal channel region.

4. The 3D semiconductor memory device of claim 1, wherein an uppermost
gate pattern of the gate patterns extends in a first direction when
viewed from a plan view; and wherein the semiconductor pattern extends in
a second direction different from the first direction when viewed from
the plan view.

5. The 3D semiconductor memory device of claim 4, further comprising: a
bit line electrically connected to the string drain region, the bit line
extending in the second direction.

6. The 3D semiconductor memory device of claim 1, further comprising: a
common source region formed in the semiconductor substrate at a side of
the gate structure, wherein a lowermost gate pattern of the gate patterns
is configured to control a vertical channel region defined in the
vertical active pattern and a horizontal channel region defined in the
semiconductor substrate; and wherein an end of the horizontal channel
region is connected to the common source region, and another end of the
horizontal channel region is connected to the vertical channel region.

7. The 3D semiconductor memory device of claim 1, further comprising: a
body pickup region disposed in the semiconductor pattern, the body pickup
region spaced apart from the string drain region, wherein the body pickup
region is doped with dopants of a first conductivity type, and the string
drain region is doped with dopants of a second conductivity type.

8. The 3D semiconductor memory device of claim 7, further comprising: a
bit line electrically connected to the string drain region; and a body
pickup line electrically connected to the body pickup region, wherein the
bit line is disposed at a level different from the body pickup line with
respect to a top surface of the semiconductor substrate.

9. The 3D semiconductor memory device of claim 7, further comprising: a
common source region formed in the semiconductor substrate, the common
source region doped with dopants of the second conductivity type, wherein
the vertical active pattern contacts the common source region.

10. A three-dimensional (3D) semiconductor memory device comprising: a
first gate structure including first gate patterns and first insulating
patterns alternately stacked on a semiconductor substrate; a first
vertical active pattern penetrating the first gate structure; a second
gate structure including second gate patterns and second insulating
patterns alternately stacked on the semiconductor substrate, the second
gate structure laterally spaced apart from the first gate structure; a
second vertical active pattern penetrating the second gate structure; a
gate dielectric layer disposed between a sidewall of each of the first
and second vertical active patterns and each of the first and second gate
patterns; a semiconductor pattern disposed on the first and second gate
structures, the semiconductor pattern connected to the first and second
vertical active patterns; and a string drain region disposed in the
semiconductor pattern, the string drain region spaced apart from the
first and second vertical active patterns.

11. The 3D semiconductor memory device of claim 10, further comprising: a
string source region disposed in the semiconductor pattern, the string
source region spaced apart from the string drain region and the first and
second vertical active patterns, wherein bottom ends of the first and
second vertical active patterns are connected to each other and
constitute a U-shape active part; wherein an uppermost gate pattern of
the first gate patterns corresponds to a string selection gate pattern,
and an uppermost gate pattern of the second gate patterns corresponds to
a ground selection gate pattern; and wherein an lowermost gate pattern of
the first gate patterns and an lowermost gate pattern of the second gate
patterns correspond to cell gate patterns.

12. The 3D semiconductor memory device of claim 11, wherein the string
selection gate pattern is configured to control a first vertical channel
region defined in the first vertical active pattern and a first
horizontal channel region defined in the semiconductor pattern; wherein
one end of the first horizontal channel region is connected to the first
vertical channel region, and another end of the first horizontal channel
region is connected to the string drain region; wherein the ground
selection gate pattern is configured to control a second vertical channel
region defined in the second vertical active pattern and a second
horizontal channel region defined in the semiconductor pattern; and
wherein one end of the second horizontal channel region is connected to
the second vertical channel region, and another end of the second
horizontal channel region is connected to the string source region.

13. The 3D semiconductor memory device of claim 11, further comprising: a
body pickup region formed in the semiconductor pattern, the body pickup
region spaced apart from the string drain region and the string source
region, wherein the body pickup region is doped with dopants of a first
conductivity type; wherein the string drain region and the string source
region are doped with dopants of a second conductivity type; and wherein
the body pickup region is disposed between the string drain region and
the string source region.

14. The 3D semiconductor memory device of claim 13, further comprising: a
bit line electrically connected to the string drain region; a common
source line electrically connected to the string source region; and a
body pickup line electrically connected to the body pickup region,
wherein the bit line is disposed at a level different from the common
source line with respect to a top surface of the semiconductor substrate;
and wherein the bit line, the common source line, and the body pickup
line are spaced apart from each other.

15. The 3D semiconductor memory device of claim 11, further comprising:
an active connection portion disposed in a recess region formed in the
semiconductor substrate under the first and second gate structures,
wherein the active connection portion is formed of the same semiconductor
material as the first and second vertical active patterns; wherein the
bottom end of the first vertical active pattern is connected to the
bottom end of the second vertical active pattern through the active
connection portion; and wherein the gate dielectric layer extends to be
disposed between the active connection portion and the semiconductor
substrate.

16. A semiconductor memory device comprising: a gate structure including
an insulating pattern and a gate pattern stacked on a substrate; a
vertical active pattern penetrating the gate structure in a direction
substantially perpendicular to a top surface of the substrate; and a
semiconductor pattern disposed on top surfaces of the gate structure and
the vertical active pattern, the semiconductor pattern including a string
drain region, wherein the string drain region does not contact the
vertical active pattern.

17. The semiconductor memory device of claim 16, wherein the vertical
active pattern includes a first vertical channel region, and the
semiconductor pattern includes a horizontal channel region, wherein the
horizontal channel region connects the first vertical channel region with
the string drain region.

18. The semiconductor memory device of claim 16, further comprising a
common source region in the substrate, wherein the common source region
does not contact the vertical active pattern.

19. The semiconductor memory device of claim 18, wherein the vertical
active pattern includes a second vertical channel region, and the
substrate includes a horizontal channel region, wherein the horizontal
channel region of the substrate connects the second vertical channel
region with the common source region.

20. The semiconductor memory device of claim 16, further comprising a
device isolation pattern at a side of the vertical active pattern.

Description:

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This U.S. non-provisional patent application claims priority under
35 U.S.C. §119 to Korean Patent Application No. 10-2011-0106016,
filed on Oct. 17, 2011, the entirety of which is incorporated by
reference herein.

BACKGROUND

[0002] Embodiments of the inventive concept relate to semiconductor
devices and more particularly to three-dimensional semiconductor memory
devices.

[0003] High integration density of semiconductor memory devices, which may
contribute to cost savings, may be limited by their available planar
area.

[0006] In an embodiment, a three-dimensional (3D) semiconductor memory
device may include a gate structure including gate patterns and
insulating patterns alternately stacked on a semiconductor substrate, a
vertical active pattern penetrating the gate structure, a gate dielectric
layer disposed between a sidewall of the vertical active pattern and each
of the gate patterns, a semiconductor pattern disposed on the gate
structure, the semiconductor pattern connected to the vertical active
pattern, and a string drain region formed in a portion of the
semiconductor pattern, the string drain region spaced apart from the
vertical active pattern.

[0007] In an embodiment, an uppermost gate pattern of the gate patterns
may control a vertical channel region defined in the vertical active
pattern and a horizontal channel region defined in the semiconductor
pattern. The vertical channel region may be connected to one end of the
horizontal channel region, and the string drain region may be connected
to another end of the horizontal channel region.

[0008] In an embodiment, the semiconductor pattern may contact the
vertical active pattern.

[0009] In an embodiment, an uppermost gate pattern of the gate patterns
may extend in a first direction when viewed from a plan view, and the
semiconductor pattern may extend in a second direction different from the
first direction when viewed from a plan view.

[0010] In an embodiment, the 3D semiconductor memory device may further
include: a bit line electrically connected to the string drain region and
extending in the second direction.

[0011] In an embodiment, the 3D semiconductor memory device may further
include a common source region formed in the semiconductor substrate at a
side of the gate structure. A lowermost gate pattern of the gate patterns
may control a vertical channel region defined in the vertical active
pattern and a horizontal channel region defined in the semiconductor
substrate. An end of the horizontal channel region may be connected to
the common source region, and another end of the horizontal channel
region may be connected to the vertical channel region.

[0012] In an embodiment, the 3D semiconductor memory device may further
include: a body pickup region disposed in the semiconductor pattern, the
body pickup region spaced apart from the string drain region. The body
pickup region may be doped with dopants of a first conductivity type and
the string drain region may be doped with dopants of a second
conductivity type.

[0013] In an embodiment, the 3D semiconductor memory device may further
include a bit line electrically connected to the string drain region and
a body pickup line electrically connected to the body pickup region. The
bit line may be disposed at a level different from the body pickup line
with respect to a top surface of the semiconductor substrate.

[0014] In an embodiment, the 3D semiconductor memory device may further
include a common source region formed in the semiconductor substrate and
doped with dopants of the second conductivity type. The vertical active
pattern may contact the common source region.

[0015] In an embodiment, a 3D semiconductor memory device may include a
first gate structure including first gate patterns and first insulating
patterns alternately stacked on a semiconductor substrate, a first
vertical active pattern penetrating the first gate structure, a second
gate structure including second gate patterns and second insulating
patterns alternately stacked on the semiconductor substrate, the second
gate structure laterally spaced apart from the first gate structure, a
second vertical active pattern penetrating the second gate structure, a
gate dielectric layer disposed between a sidewall of each of the first
and second vertical active patterns and each of the first and second gate
patterns, a semiconductor pattern disposed on the first and second gate
structures, the semiconductor pattern connected to the first and second
vertical active patterns, and a string drain region disposed in the
semiconductor pattern, the string drain region spaced apart from the
first and second vertical active patterns.

[0016] In an embodiment, the 3D semiconductor memory device may further
include a string source region disposed in the semiconductor pattern. The
string source region may be spaced apart from the string drain region and
the first and second vertical active patterns. Bottom ends of the first
and second vertical active patterns may be connected to each other and
constitute a U-shape active part. An uppeimost gate pattern of the first
gate patterns may correspond to a string selection gate pattern, and an
uppermost gate pattern of the second gate patterns may correspond to a
ground selection gate pattern. A lowermost gate pattern of the first gate
patterns and an lowermost gate pattern of the second gate patterns may
correspond to cell gate patterns.

[0017] In an embodiment, the string selection gate pattern may control a
first vertical channel region defined in the first vertical active
pattern and a first horizontal channel region defined in the
semiconductor pattern. One end of the first horizontal channel region may
be connected to the first vertical channel region, and another end of the
first horizontal channel region may be connected to the string drain
region. The ground selection gate pattern may control a second vertical
channel region defined in the second vertical active pattern and a second
horizontal channel region defined in the semiconductor pattern. One end
of the second horizontal channel region may be connected to the second
vertical channel region, and another end of the second horizontal channel
region may be connected to the string source region.

[0018] In an embodiment, the 3D semiconductor memory device may further
include a body pickup region formed in the semiconductor pattern. The
body pickup region may be spaced apart from the string drain region and
the string source region. The body pickup region may be doped with
dopants of a first conductivity type, and the string drain region and the
string source region may be doped with dopants of a second conductivity
type. The body pickup region may be disposed between the string drain
region and the string source region.

[0019] In an embodiment, the 3D semiconductor memory device may further
include a bit line electrically connected to the string drain region, a
common source line electrically connected to the string source region,
and a body pickup line electrically connected to the body pickup region.
The bit line may be disposed at a level different from the common source
line with respect to a top surface of the semiconductor substrate. The
bit line, the common source line, and the body pickup line may be spaced
apart from each other.

[0020] In an embodiment, the 3D semiconductor memory device may further
include an active connection portion disposed in a recess region formed
in the semiconductor substrate under the first and second gate
structures. The active connection portion may be formed of the same
semiconductor material as the first and second vertical active patterns.
The bottom end of the first vertical active pattern may be connected to
the bottom end of the second vertical active pattern through the active
connection portion. The gate dielectric layer may extend to be disposed
between the active connection portion and the semiconductor substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The embodiments of the inventive concept will become more apparent
in view of the attached drawings and accompanying detailed description.

[0022] FIG. 1 is a perspective view illustrating a three-dimensional (3D)
semiconductor memory device according to an embodiment of the inventive
concept;

[0047]FIG. 32 is a schematic block diagram illustrating an example of an
electronic system including 3D semiconductor memory devices according to
an embodiment of the inventive concept; and

[0048]FIG. 33 is a schematic block diagram illustrating an example of
memory cards including 3D semiconductor memory devices according to
embodiments of the inventive concept.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0049] The embodiments of the inventive concept will now be described more
fully hereinafter with reference to the accompanying drawings. It should
be noted, however, that the inventive concept is not limited to the
following exemplary embodiments, and may be implemented in various forms.
Accordingly, the exemplary embodiments are provided only to disclose the
inventive concept and let those skilled in the art know the category of
the inventive concept. In the drawings, embodiments of the inventive
concept are not limited to the specific examples provided herein and are
exaggerated for clarity.

[0050] The terminology used herein is for the purpose of describing
particular embodiments only and is not intended to limit the invention.
As used herein, the singular terms "a," "an" and "the" are intended to
include the plural forms as well, unless the context clearly indicates
otherwise. It will be understood that when an element is referred to as
being "connected" or "coupled" to another element, it may be directly
connected or coupled to the other element or intervening elements may be
present.

[0051] Similarly, it will be understood that when an element such as a
layer, region or substrate is referred to as being "on" another element,
it can be directly on the other element or intervening elements may be
present. The same reference numerals or the same reference designators
may denote the same or substantially the same elements throughout the
specification and the drawings.

[0052] FIG. 1 is a perspective view illustrating a three-dimensional (3D)
semiconductor memory device according to an embodiment of the inventive
concept, FIG. 2 is a plan view illustrating the 3D semiconductor memory
device of FIG. 1, and FIG. 3 is a cross-sectional view taken along a line
I-I' of FIG. 2. FIG. 4A is an enlarged view of a portion `A1` of FIG. 3,
FIG. 4B is an enlarged view of a portion `A2` of FIG. 3, and FIG. 4c is
an enlarged view of a portion `A3` of FIG. 3.

[0053] Referring to FIGS. 1, 2, and 3, a gate structure is disposed on a
semiconductor substrate 100. The gate structure includes gate patterns
GSG, CG, and SSG and insulating patterns 110a and 110ua which are
alternately and repeatedly stacked on the semiconductor substrate 100.
The uppermost gate pattern SSG and the lowermost gate pattern GSG of the
gate patterns GSG, CG, and SSG in the gate structure correspond to a
string selection gate pattern SSG and a ground selection gate pattern
GSG, respectively. The gate patterns GSG, CG, and SSG in the gate
structure include a plurality of stacked cell gate patterns CG. The
stacked cell gate patterns CG are disposed between the ground selection
gate pattern GSG and the string selection gate pattern SSG. A buffer
dielectric pattern 103a is disposed between the gate structure and the
semiconductor substrate 100. According to an embodiment, a plurality of
gate structures are provided on the semiconductor substrate 100. The
plurality of gate structures are laterally spaced apart from each other.

[0054] The semiconductor substrate 100 includes a semiconductor material.
For example, according to an embodiment, the semiconductor substrate 100
includes a silicon substrate, a germanium substrate, or a
silicon-germanium substrate. The semiconductor substrate 100 is doped
with dopants of a first conductivity type. For example, according to an
embodiment, the semiconductor substrate 100 includes a well region doped
with the dopants of the first conductivity type. The gate structure is
disposed on the well region. The uppermost insulating pattern 110ua of
the insulating patterns 110a and 110ua is disposed on the string
selection gate pattern SSG. The insulating patterns 110a under the
uppermost insulating pattern 110ua include oxide. The uppermost
insulating pattern 110ua includes the same insulating material as the
insulating patterns 110a. Alternatively, the uppermost insulating pattern
110ua includes an insulating material different from the insulating
patterns 110a. This will be described below in more detail. The gate
patterns GSG, CG, and SSG are formed of a conductive material. For
example, according to an embodiment, the gate patterns GSG, CG, and SSG
include at least one of a semiconductor material doped with dopants
(e.g., doped silicon, etc.), a conductive metal nitride (e.g., titanium
nitride (TiN), tantalum nitride (TaN), and/or tungsten nitride (WN),
etc.), metal (e.g., tungsten, titanium, and/or tantalum, etc.), and a
metal-semiconductor compound (e.g., metal silicide, etc.). The buffer
dielectric pattern 103a includes the same material as the insulating
patterns 110a. For example, according to an embodiment, the buffer
dielectric pattern 103a includes oxide.

[0055] In an embodiment, the gate structure includes a plurality of string
selection gate patterns SSG which are disposed at the same level from a
top surface of the semiconductor substrate 100. The string selection gate
patterns SSG in the gate structure are laterally spaced apart from each
other and disposed on a single uppermost cell gate pattern CG. According
to an embodiment, a single ground selection gate pattern GSG is included
as the lowermost gate pattern in the gate structure. A separation
insulating pattern 135 is disposed between the string selection gate
patterns SSG. The separation insulating pattern 135 extends upward and is
disposed between the uppermost insulating patterns 110ua which are
disposed on the plurality of string selection gate patterns SSG,
respectively.

[0056] As illustrated in FIG. 2, the gate structure extends in a first
direction D1 in a plan view. Thus, the string selection, cell, and ground
selection gate patterns SSG, CG, and GSG extend in the first direction
D1. In a plan view, the plurality of string selection gate patterns SSG
are spaced apart from each other in a second direction D2 perpendicular
to the first direction D1.

[0057] A plurality of vertical active patterns VAP penetrate the gate
structure. In an embodiment, the vertical active patterns VAP contact the
semiconductor substrate 100. As illustrated in FIG. 2, the plurality of
vertical active patterns VAP are two-dimensionally arranged in rows and
columns in a plan view. The columns are parallel to the first direction
D1, and the rows are parallel to the second direction D2. In an
embodiment, the vertical active patterns VAP constituting each of the
columns penetrate a corresponding string selection gate pattern of the
string selection gate patterns SSG and the cell and ground selection gate
patterns CG and SSG under the corresponding string selection gate pattern
SSG. For example, the vertical active patterns VAP penetrating each of
the string selection gate pattern SSG are linearly arranged in the first
direction D1.

[0058] According to an embodiment, the vertical active patterns VAP are
formed of the same semiconductor material (e.g., silicon) as the
semiconductor substrate 100. According to an embodiment, the vertical
active patterns VAP have a poly-crystalline state or a single-crystalline
state. According to an embodiment, the vertical active patterns VAP have
an undoped state or be doped with dopants of the first conductivity type.
Alternatively, the vertical active patterns VAP are lightly doped with
dopants of a second conductivity type different from the first
conductivity type.

[0059] In an embodiment, as illustrated in FIG. 3, each of the vertical
active patterns VAP has a pipe shape or a macaroni shape. According to an
embodiment, a filling dielectric pattern 125 fills an inner space
surrounded by each of the vertical active patterns VAP. According to an
embodiment, the filling dielectric pattern 125 includes oxide, nitride,
and/or oxynitride.

[0060] A gate dielectric layer GEL is disposed between a sidewall of each
of the vertical active patterns VAP and each of the gate patterns GSG,
CG, and SSG. The gate dielectric layer GEL will be described below in
more detail.

[0061] A plurality of semiconductor patterns 140b are disposed on the gate
structure. The semiconductor patterns 140b extend in the second direction
D2 when viewed from a plan view. The semiconductor patterns 140b are
spaced apart from each other in the first direction D1 and electrically
insulated from each other. Each of the semiconductor patterns 140b is
connected to top ends of the vertical active patterns VAP constituting
each of the rows in the gate structure. Each of the semiconductor
patterns 140b contacts the vertical active patterns VAP in each of the
rows. Each of the semiconductor patterns 140b covers top surfaces of the
filling dielectric patterns 125 filling the inner spaces of the vertical
active patterns VAP in each of the rows. In an embodiment, as illustrated
in FIG. 3, each of the semiconductor patterns 140b includes two opposite
sidewalls respectively aligned with two opposite sidewalls of the gate
structure.

[0062] According to an embodiment, the semiconductor patterns 140b are
formed of the same semiconductor material as the vertical active patterns
VAP. For example, according to an embodiment, when the vertical active
patterns VAP are formed of silicon, the semiconductor patterns 140b are
formed of silicon. According to an embodiment, the semiconductor patterns
140b have the same doped state as the vertical active patterns VAP. For
example, according to an embodiment, the semiconductor patterns 140b have
an undoped state or are doped with dopants of the first conductivity
type. Alternatively, the semiconductor patterns 140b are lightly doped
with dopants of the second conductivity type.

[0063] A string drain region 150 is formed in a portion of each of the
semiconductor patterns 140b. The string drain region 150 corresponds to a
region doped with dopants of the second conductivity type. The string
drain region 150 has a high concentration. The string drain region 150 is
spaced apart from the vertical active patterns VAP. For example, the
string drain region 150 is spaced apart from a hole defined by the
vertical active pattern VAP in the gate structure. Thus, the dopants in
the string drain region 150 do not substantially influence the vertical
active patterns VAP. As a result, it is possible to prevent a
deterioration of characteristics of vertical channel regions defined in
the vertical active pattern VAP. According to an embodiment, one of the
first conductivity type and the second conductivity type is a P type and
the other is an N type.

[0064] Since the string drain region 150 is spaced apart from the vertical
active patterns VAP, at least a portion of the string selection gate
pattern SSG overlaps a portion of the semiconductor pattern 140b in which
the string drain region 150 is not formed. For example, the string
selection gate pattern SSG overlaps a portion of the semiconductor
pattern 140b between the string drain region 150 and each of the vertical
active patterns VAP.

[0065] As illustrated in FIG. 3, common source regions CSR are disposed in
the semiconductor substrate 100 at two opposite sides, respectively, of
the gate structure. The common source regions CSR are doped with dopants
of the second conductivity type. A capping dielectric pattern 153 is
disposed on the semiconductor patterns 140b and fills spaces between the
semiconductor patterns 140b. The capping dielectric pattern 153 has two
opposite sidewalls respectively aligned with the two opposite sidewalls
of the gate structure. The capping dielectric pattern 153 includes oxide.
Device isolation patterns 160 are disposed on the common source regions
CSR, respectively. The gate structure, the semiconductor patterns 140b,
and the capping dielectric pattern 153 are disposed between two device
isolation patterns 160 adjacent to each other. Top surfaces of the device
isolation patterns 160 are substantially coplanar with a top surface of
the capping dielectric pattern 153. According to an embodiment, the
device isolation patterns 160 include oxide, nitride, and/or oxynitride.

[0066] Hereinafter, the string selection gate pattern SSG, the
semiconductor pattern 140b, and the string drain region 150 are described
in more detail with reference to FIG. 4A.

[0067] Referring to FIGS. 1, 2, 3, and 4A, the string selection gate
pattern SSG controls a string horizontal channel region HCR1 defined in
the semiconductor pattern 140b located over the string selection gate
pattern SSG and a string vertical channel region VCR1 defined in the
vertical active pattern VAP located beside the string selection gate
pattern SSG. An end of the string horizontal channel region HCR1 is
connected to the string drain region 150 and another end of the string
horizontal channel region HCR1 is connected to the string vertical
channel region VCR1. For example, a string selection transistor including
the string selection gate pattern SSG has the string horizontal channel
region HCR1 and the string vertical channel region VCR1. Thus, even
though the string drain region 150 is spaced apart from the vertical
active pattern VAP, a channel generated in the string vertical channel
region VCR1 is electrically connected to the string drain region 150
through a channel generated in the string horizontal channel region HCR1
during an operation of the 3D semiconductor memory device.

[0068] A string selection gate dielectric layer of the string selection
transistor includes the gate insulating layer GEL disposed between the
vertical active pattern VAP and the string selection gate pattern SSG,
and the uppermost insulating pattern 110ua and a portion 157 of the gate
dielectric layer GEL disposed between the semiconductor pattern 140b and
the string selection gate pattern SSG. According to an embodiment, the
uppermost insulating pattern 110ua includes oxide, nitride, oxynitride,
and/or a high-k dielectric material.

[0069] According to an embodiment, the common source region CSR is
disposed in the semiconductor substrate 100 at a side of the gate
structure. According to an embodiment, a ground selection transistor
including the ground selection gate pattern GSG includes also a
horizontal channel region and a vertical channel region.

[0070] Referring to FIGS. 1, 2, 3, and 4B, the ground selection gate
pattern GSG controls a ground horizontal channel region HCR2 defined in
the semiconductor substrate 100 under the ground selection gate pattern
GSG and a ground vertical channel region VCR2 defined in the vertical
active pattern VAP beside the ground selection gate pattern GSG. An end
of the ground horizontal channel region HCR2 is connected to the common
source region CSR, and another end of the ground horizontal channel
region HCR2 is connected to the ground vertical channel region VCR2. A
ground selection gate dielectric layer of the ground selection transistor
includes the gate dielectric layer GEL disposed between the vertical
active pattern VAP and the ground selection gate pattern GSG, and a
portion 157 of the gate dielectric layer GEL and the buffer dielectric
pattern 103a disposed between the ground selection gate pattern GSG and
the semiconductor substrate 100. In an embodiment, the buffer dielectric
pattern 103a is omitted.

[0071] The gate dielectric layer GEL is described in more detail with
reference to FIG. 4c. Referring to FIGS. 1, 2, 3, and 4C, the gate
dielectric layer GEL between each of the gate patterns GSG, CG, and SSG
and each of the vertical active patterns VAP includes a tunnel dielectric
layer, a charge storing layer, and a blocking dielectric layer. The
tunnel dielectric layer is adjacent to the vertical active pattern VAP,
and the blocking dielectric layer is adjacent to each of the gate
patterns GSG, CG, and SSG. The charge storing layer is disposed between
the tunnel dielectric layer and the blocking dielectric layer.

[0072] According to an embodiment, the tunnel dielectric layer includes
oxide, oxynitride, and/or metal oxide (e.g., hafnium oxide, etc.). The
charge storing layer includes a dielectric material having traps capable
of storing charges. For example, according to an embodiment, the charge
storing layer includes nitride and/or metal oxide (e.g., hafnium oxide,
etc.). The blocking dielectric layer includes a high-dielectric layer
having a dielectric constant higher than a dielectric constant of the
tunnel dielectric layer. For example, according to an embodiment, the
high-dielectric layer includes a metal oxide layer, such as an aluminum
oxide layer or a hafnium oxide layer. According to an embodiment, the
blocking dielectric layer further includes a barrier dielectric layer
having an energy band gap greater than an energy band gap of the high-k
dielectric layer. In an embodiment, the barrier dielectric layer is
disposed between the charge storing layer and the high-k dielectric
layer.

[0073] As illustrated in FIG. 4c, the gate dielectric layer GEL includes a
first sub-layer 120 and a second sub-layer 157. The first sub-layer 120
includes at least a portion of the tunnel dielectric layer, and the
second sub-layer 157 includes at least a portion of the blocking
dielectric layer. One of the first and second sub-layers 120 and 157
includes the charge storing layer. For example, according to an
embodiment, the first sub-layer 120 includes the tunnel dielectric layer,
the charge storing layer, and the barrier dielectric layer, and the
second sub-layer 157 includes the high-k dielectric layer. However, the
embodiments of the inventive concept are not limited thereto. According
to an embodiment, the first sub-layer 120 and the second sub-layer 157
include any combination.

[0074] As illustrated in FIG. 4c, the first sub-layer 120 vertically
extends between the vertical active pattern VAP and the insulating
patterns 110a and 110ua. The second sub-layer 157 horizontally extends
and covers a bottom surface and a top surface of each of the gate pattern
GSG, CG, and SSG. The extending portion of the second sub-layer 157 is
disposed between the bottom or top surface of each of the gate patterns
GSG, CG, and SSG and the insulating pattern 110 or 110ua.

[0075] A cell transistor includes each of the cell gate patterns CG and
the gate dielectric layer GEL between the vertical active pattern VAP and
each of the cell gate patterns CG. The cell transistor includes a cell
vertical channel region defined in the vertical active pattern VAP.

[0076] Referring to FIGS. 1 to 3 and 4A to 4C, a vertical cell string
includes a corresponding vertical active pattern of the vertical active
patterns VAP, and the ground selection transistor, the cell transistors,
and the string selection transistor defined at the corresponding vertical
active pattern VAP. The ground selection, cell, and string selection
transistors in the vertical cell string include vertical channel regions.
Thus, a plurality of vertical cell strings are formed in the gate
structure. The vertical cell strings in the gate structure are arranged
along the rows and the columns when viewed from a plan view. The vertical
cell strings in each of the rows share the string drain region 150 in
each of the semiconductor patterns 140b. The ground selection transistor,
the cell transistors, and the string selection transistor in each of the
vertical cell strings are connected in series to each other. In an
embodiment, each of the vertical cell strings includes a plurality of
ground selection transistors connected in series to each other and/or a
plurality of string selection transistors connected in series to each
other. According to an embodiment, the uppermost transistor in each of
the vertical cell strings also corresponds to the string selection
transistor.

[0077] An interlayer dielectric layer 165 is disposed on the capping
dielectric layer 153 and the device isolation patterns 160. The
interlayer dielectric layer 165 includes oxide. Contact plugs 170
successively penetrate the interlayer dielectric layer 165 and the
capping dielectric layer 153 and connect to the string drain regions 150,
respectively. Bit lines BL are disposed on the interlayer dielectric
layer 165 and connect to the contact plugs 170, respectively. The bit
lines BL are electrically connected to the string drain regions 150
through the contact plugs 170, respectively. The bit lines BL extend in
the second direction D2 to be parallel to the semiconductor patterns
140b. Each of the bit lines BL is connected to the string drain region
150 in the semiconductor pattern 140b connected to the vertical active
patterns VAP in each of the rows of the vertical active patterns VAP.

[0079] According to the 3D semiconductor memory device described above,
the string drain region 150 is disposed in the semiconductor pattern 140b
on the gate structure. Thus, the string drain region 150 is spaced apart
from the vertical active pattern VAP, such that the string selection
transistor has the string vertical channel region VCR1 with stable
characteristics. As a result, it is possible to realize the 3D
semiconductor memory device with improved reliability and higher
integration.

[0080] When the string drain region 150 contacts the vertical active
pattern VAP, the dopants in the string drain region 150 may be diffused
into the string vertical channel region. Thus, a doping concentration of
the string vertical channel region may be non-uniform. Therefore, the
characteristics of the string selection transistor may be deteriorated,
such that reliability of a 3D semiconductor memory device may decrease.
However, according to an embodiment of the inventive concept, the string
drain region 150 is disposed in a portion of the semiconductor pattern
150 to be separated from the vertical active pattern VAP. As a result, it
is possible to realize the 3D semiconductor memory device with improved
reliability.

[0081] Even though the string drain region 150 is spaced apart from the
vertical active pattern VAP, the string selection gate pattern SSG, which
is an uppermost gate pattern, controls the string horizontal channel
region HCR1. Thus, the string drain region 150 can be electrically
connected to the channel generated in the string vertical channel region
VCR1 through the channel generated in the string horizontal channel
region HCR1.

[0082] Hereinafter, modified examples of the present embodiment will be
described with reference to drawings.

[0083]FIG. 5 is a cross-sectional view illustrating a 3D semiconductor
memory device according to an embodiment of the inventive concept.

[0084] According to an embodiment, the filling dielectric pattern 125
described with reference to FIGS. 1 to 3 is omitted. According to an
embodiment, as illustrated in FIG. 5, a vertical active pattern VAP' has
a pillar shape. The semiconductor pattern 140b contacts a top surface of
the vertical active pattern VAP' having the pillar shape.

[0085]FIG. 6 is a cross-sectional view illustrating a 3D semiconductor
memory device according to an embodiment of the inventive concept.

[0086] Referring to FIG. 6, a semiconductor pattern 140b' does not cover a
top surface of the filling dielectric pattern 125 filling the inner space
of the vertical active pattern VAP. According to an embodiment, the
semiconductor pattern 140b' contacts the vertical active pattern VAP so
that the semiconductor pattern 140b' and the vertical active pattern VAP
constitute one body. According to an embodiment, the top surface of the
filling dielectric pattern 125 is substantially coplanar with a top
surface of the semiconductor pattern 140b'.

[0087]FIG. 7 is a cross-sectional view illustrating a 3D semiconductor
memory device according to an embodiment of the inventive concept.

[0088] Referring to FIG. 7, a semiconductor pattern 140k laterally extends
to cross the device isolation patterns 160 according to an embodiment.
According to an embodiment, the capping dielectric pattern 153 is
omitted, and top surfaces of the device isolation patterns 160 are
substantially coplanar with top surfaces of the uppermost insulating
patterns 110ua.

[0089] FIG. 8 is a cross-sectional view illustrating a 3D semiconductor
memory device according to an embodiment of the inventive concept.

[0090] Referring to FIG. 8, according to an embodiment, a plurality of
vertical active patterns VAP penetrating each of string selection gate
patterns SSG are arranged in a zigzag shape along the first direction D1
when viewed from a plan view. For example, a column of odd-numbered
vertical active patterns VAP, which is referred to as a first column, may
be offset from a column of even-numbered vertical active patterns VAP,
which is referred to as a second column. The vertical active patterns VAP
constituting the first and second columns penetrate each of the string
selection gate patterns SSG. According to an embodiment, string drain
regions 150 formed in the semiconductor patterns 140b are arranged in a
zigzag shape along the first direction D1. A width of the gate structure
in the first direction D1 is reduced by the arrangement of the vertical
active patterns VAP according to an embodiment. As a result, the 3D
semiconductor memory device can have higher integration.

[0091] FIG. 9 is a cross-sectional view illustrating a 3D semiconductor
memory device according to an embodiment of the inventive concept.

[0092] Referring to FIG. 9, a gate dielectric layer GEL' between the
sidewall of the vertical active pattern VAP and each of the gate patterns
GSG, CG, and SSG horizontally extends to cover the bottom surface and the
top surface of each of the gate patterns GSG, CG, and SSG. For example,
all the tunnel dielectric layer, the charge storing layer, and blocking
dielectric layer in the gate dielectric layer GEL' horizontally extend to
cover the bottom surface and the top surface of each of the gate patterns
GSG, CG, and SSG. According to an embodiment, the insulating patterns
110a and 110ua contact the sidewalls of the vertical active patterns VAP.

[0093] The embodiments described with reference to FIGS. 5 to 9 may be
combined in various forms under a non-contradictable condition.

[0095] Referring to FIGS. 10A and 10B, sacrificial layers 105 and 105u and
insulating layers 110 and 110u are alternately and repeatedly formed on a
semiconductor substrate 100 doped with dopants of a first conductivity
type. According to an embodiment, a buffer dielectric layer 103 is formed
on the semiconductor substrate 100. According to an embodiment, the
buffer dielectric layer 103 is formed on the semiconductor substrate 100
before the sacrificial layers 105 and 105u and the insulating layers 110
and 110u are formed. Alternately, the buffer dielectric layer 103 is
omitted. The sacrificial layers 105 and 105u are formed of a material
having an etch selectivity with respect to the insulating layers 110 and
110u and the buffer dielectric layer 103. For example, according to an
embodiment, the insulating layers 110 and 110u and the buffer dielectric
layer 103 incude oxide layers, and the sacrificial layers 105 and 105u
include nitride layers. According to an embodiment, the dopants of the
first conductivity type are provided into the semiconductor substrate 100
to form a well region. According to an embodiment, the dopants of the
first conductivity type are provided in the semiconductor substrate 100
before the formation of the sacrificial layers 105 and 105u and the
insulating layers 110 and 110u.

[0096] Holes 115 are formed to penetrate the insulating layers 110 and
110u, the sacrificial layers 105 and 105u, and the buffer dielectric
layer 103. The holes 115 expose the semiconductor substrate 100. As
illustrated in FIG. 10A, the holes 115 are two-dimensionally arranged to
constitute rows and columns when viewed from a plan view. The columns are
parallel to a first direction D1, and the rows are parallel to a second
direction D2.

[0097] A first sub-layer 120 is conformally formed on the semiconductor
substrate 100 having the holes 115. The first sub-layer 120 disposed on
bottom surfaces of the holes 115 are removed to expose the semiconductor
substrate 100. The first sub-layer 120 disposed on the uppermost
insulating layer 110u of the insulating layers 110 and 110u is removed. A
vertical active pattern VAP and a filling dielectric pattern 125 are
formed in each of the holes 115. In an embodiment, the vertical active
pattern VAP and the filling dielectric pattern 125 are formed by
deposition processes and a planarization process. In an embodiment, the
vertical active pattern VAP is formed by an epitaxial process, and the
filling dielectric pattern 125 is omitted. In an embodiment, the vertical
active pattern VAP is fanned by a solid phase epitaxial (SPE) process and
a planarization process.

[0098] The uppermost insulating layer 110u and the uppermost sacrificial
layer 105u of the sacrificial layers 105 and 105u are patterned to form a
cutting trench 130. The cutting trench 130 is formed between the columns
of vertical active patterns VAP in a plan view. A separation insulating
pattern 135 is formed in the cutting trench 130. The cutting trench 130
and the separation insulating pattern 135 may be formed to separating
string selection gate patterns which are formed by subsequent processes.

[0099] According to an embodiment, after the holes 115 and the vertical
active patterns VAP are formed, the cutting trench 130 and the separation
insulating pattern 135 are formed. Alternatively, after the cutting
trench 130 and the separation insulating pattern 135 are formed, the
holes 115 and the vertical active patterns VAP are formed.

[0100] A thickness of the uppermost insulating layer 110u is controlled by
a planarization process for the formation of the vertical active patterns
VAP.

[0101] Referring to FIGS. 11A and 11B, a semiconductor layer 140 is foamed
on the semiconductor substrate 100. The semiconductor layer 140 is
disposed on the uppermost insulating layer 110u, the separation
insulating pattern 130, and the vertical active patterns VAP. The
semiconductor layer 140 contacts the vertical active patterns VAP.
According to an embodiment, a surface treatment process is performed on
the uppermost insulating layer 110u. According to an embodiment, the
surface treatment process is performed before the semiconductor layer 140
is formed.

[0102] Referring to FIGS. 12A and 12B, the semiconductor layer 140 is
patterned to form preliminary semiconductor patterns 140a. As illustrated
in FIG. 12A, the preliminary semiconductor patterns 140a have line shapes
extending in the second direction D2 in a plan view. Each of the
preliminary semiconductor patterns 140a contacts the vertical active
patterns VAP constituting each of the rows of vertical active patterns
VAP. The preliminary semiconductor patterns 140a are separated from each
other.

[0103] Referring to FIGS. 13A and 13B, dopants of a second conductivity
type are provided into the preliminary semiconductor patterns 140a to
foim string drain regions 150. According to an embodiment, after the
preliminary semiconductor patterns 140a are formed, the string drain
regions 150 may be formed.

[0104] Alternatively, the dopants of the second conductivity type are
provided into the semiconductor layer 140 illustrated in FIGS. 11A and
11B to form a doped region extending in the first direction D1.
Subsequently, the semiconductor layer 140 and the doped region are
patterned to form the preliminary semiconductor patterns 140a and the
string drain regions 150 in the preliminary semiconductor patterns 140a.
According to an embodiment, the doped region is divided into the string
drain regions 150.

[0105] Referring to FIGS. 14A and 14B, a capping dielectric layer is
formed on the semiconductor substrate 100 having the preliminary
semiconductor patterns 140a and the string drain regions 150. The capping
dielectric layer, the preliminary semiconductor patterns 140a, the
insulating layers 110u and 110, and the sacrificial layers 105u and 105
are successively patterned to form device isolation trenches 155.
Sacrificial patterns 105a and 105ua, insulating patterns 110a and 110ua,
semiconductor patterns 140b, and a capping dielectric pattern 153 are
formed between two device isolation trenches 155 adjacent to each other.
The sacrificial patterns 105a and 105ua and the insulating patterns 110a
and 110ua are alternately and repeatedly stacked. The cutting trench 130
and the separation insulating pattern 135 are disposed between the
adjacent device isolation trenches 155. Thus, a plurality of the
uppermost sacrificial patterns 105ua are formed between the adjacent
device isolation trenches 155. The plurality of the uppermost sacrificial
patterns 105ua are disposed at substantially the same level from a top
surface of the semiconductor substrate 100.

[0106] When the device isolation trenches 155 are formed, the buffer
dielectric layer 103 is also patterned to form a buffer dielectric
pattern 103a.

[0107] Referring to FIGS. 15A and 15B, the sacrificial patterns 105a and
105ua exposed by the device isolation trenches 155 are removed to form
empty regions ER and ERu. First sides of the uppermost empty regions ERu
adjacent to the separation insulating pattern 135 are closed by the
separation insulating pattern 135. Second sides of the uppermost empty
regions ERu adjacent to the device isolation trenches are opened. Two
opposite sides of each of the empty regions ER under the uppermost empty
region ERu are opened.

[0108] Referring to FIGS. 16A and 16B, a second sub-layer 157 may be
conformally formed on the semiconductor substrate 100 having the empty
regions ER and ERu. A conductive layer may be formed on the semiconductor
substrate 100 having the second sub-layer 157 to fill the empty regions
ER and ERu.

[0109] A conductive layer outside the empty regions ER and ERu is removed
to faun gate patterns GSG, CG, and SSG in the empty regions ER and ERu,
respectively. According to an embodiment, the second sub-layer 157
outside the empty regions ER and ERu are removed or remain. Forming the
gate patterns GSG, CG, and SSG by using the sacrificial patterns 105a and
105ua and the empty regions ER and ERu is defined as `a replacement
process`.

[0110] Dopants of the second conductivity type are provided into the
semiconductor substrate 100 under the device isolation trenches 155 to
form common source regions CSR. According to an embodiment, the common
source regions CSR is formed after the gate patterns GSG, CG, and SSG are
formed or before the empty regions ER and ERu are formed.

[0111] Subsequently, the device isolation patterns 155 of FIGS. 1 to 3 are
formed in the device isolation trenches 155, respectively. Subsequently,
the interlayer dielectric layer 165, the contact plugs 170, and bit lines
BL of FIGS. 1 to 3 are formed. Thus, it is possible to realize the 3D
semiconductor memory device illustrated in FIGS. 1 to 3 and 4A to 4C.

[0112] According to an embodiment, the filling dielectric pattern 125 is
omitted. Thus, it is possible to realize the 3D semiconductor memory
device illustrated in FIG. 5.

[0113] Next, a method of manufacturing the 3D semiconductor memory device
illustrated in FIG. 6 will be described with reference to drawings.

[0114] FIGS. 17A and 18A are plan views illustrating a method of
manufacturing a 3D semiconductor memory device as shown in FIG. 6, and
FIGS. 17B and 18B are cross-sectional views taken along lines I-I' of
FIGS. 17A and 18A, respectively.

[0115] Referring to FIGS. 17A and 17B, a semiconductor layer 140' is
conformally formed on the semiconductor substrate 100 having the holes
115 and the first sub-layer 120. Thus, vertical active patterns VAP are
defined in the holes 115. A filling dielectric layer is formed on the
semiconductor layer 140' to fill the holes 115. Subsequently, the filling
dielectric layer is planarized until the semiconductor layer 140' is
exposed, thereby forming filling dielectric patterns 125 in the holes
115, respectively.

[0116] Referring to FIGS. 18A and 18B, the semiconductor layer 140'
disposed on the uppermost insulating layer 110u is patterned to form
preliminary semiconductor patterns 140a'. Dopants of the second
conductivity type are provided into the preliminary semiconductor
patterns 140a' to form string drain regions 150. Alternatively, before
the semiconductor layer 140' is patterned, a doped region of the second
conductivity type is formed in the semiconductor layer 140'. The
semiconductor layer 140' and the doped region are then patterned to form
the preliminary semiconductor patterns 140a' and the string drain regions
150.

[0117] Subsequently, the processes described with reference to FIGS. 14A,
15A, and 16A and 14B, 15B, and 16B are performed. Thus, it is possible to
realize the 3D semiconductor memory device illustrated in FIG. 6.

[0118] According to an embodiment, the vertical active patterns VAP and
the semiconductor patterns 140b' are formed using a single semiconductor
layer 140'.

[0119] According to the manufacturing method described with reference to
FIGS. 10A to 16A and 10B to 16B, after the semiconductor patterns 140b
are formed, the gate patterns GSG, CG, and SSG are formed. Alternatively,
after the gate patterns GSG, CG, and SSG are formed, the semiconductor
patterns are formed. This are described with reference to the drawings.

[0120] FIGS. 19A and 20A are plan views illustrating a method of
manufacturing a 3D semiconductor memory device as shown in FIG. 7, and
FIGS. 19B and 20B are cross-sectional views taken along lines I-I' of
FIGS. 19A and 20A, respectively.

[0121] The manufacturing method illustrated in FIGS. 10A to 16A and 10B to
16B except the formation processes of the semiconductor layer 140, the
preliminary semiconductor patterns 140a, the string drain regions 150,
and the semiconductor patterns 140b is performed to form the vertical
active patterns VAP, the gate structure, the common source regions CSR,
and the device isolation patterns 160 illustrated in FIGS. 19A and 19B.
The gate structure includes the gate patterns GSG, CG, and SSG and the
insulating patterns 110a and 110ua which are alternately and repeatedly
stacked.

[0122] Referring to FIGS. 20A and 20B, a semiconductor layer is
sequentially formed on an entire surface of the semiconductor substrate
100. The semiconductor layer contacts top ends of the vertical active
patterns VAP. The semiconductor layer is patterned to form semiconductor
patterns 140k extending in the first direction D1. String drain regions
150 doped with dopants of the second conductivity type are formed in the
semiconductor patterns 140k. Alternatively, after a doped region of the
second conductivity type is formed in the semiconductor layer, the
semiconductor layer and the doped region are patterned to the
semiconductor patterns 140k and the string drain regions 150.

[0123] Subsequently, the interlayer dielectric layer 165, the contact
plugs 170, and the bit lines BL of FIG. 7 are formed. Thus, it is
possible to realize the 3D semiconductor memory device of FIG. 7.

[0124] Positions of the holes 116 are determined as positions of the
vertical active patterns VAP illustrated in FIG. 8. Thus, it is possible
to realize the 3D semiconductor memory device of FIG. 8.

[0125] In the manufacturing method illustrated in FIGS. 10A, 11A, 12A,
13A, 14A, 15A, and 16A and 10B, 11B, 12B, 13B, 14B, 15B, and 16B, the
formation of the first sub-layer 120 is omitted. According to an
embodiment, the formation process of the second sub-layer 157 is replaced
with a formation process of the gate dielectric layer GEL' of FIG. 9.
Thus, it is possible to realize the 3D semiconductor memory device
illustrated in FIG. 9.

[0126] FIG. 21 is a plan view illustrating a 3D semiconductor memory
device according to an embodiment of the inventive concept, and FIG. 22
is a cross-sectional view taken along a line II-II' of FIG. 21.

[0127] Referring to FIGS. 21 and 22, a common source region CSR is
disposed in a semiconductor substrate 200. The semiconductor substrate
200 is doped with dopants of a first conductivity type, and the common
source region CSR is doped with dopants of a second conductivity type. A
gate structure is disposed on the common source region CSR. The gate
structure includes insulating patterns 202, 210, and 210ua and gate
patterns GSG, CG, and SSG which are alternately and repeatedly stacked.

[0128] The lowermost insulating pattern 202 is disposed between the
lowermost gate pattern GSG and the common source region CSR, and the
uppermost insulating pattern 210ua is disposed on the uppermost gate
pattern SSG.

[0129] The lowermost gate pattern GSG corresponds to a ground selection
gate pattern GSG, and the uppermost gate pattern SSG corresponds to a
string selection gate pattern SSG. A plurality of cell gate patterns CG
are sequentially stacked between the ground selection gate pattern GSG
and the string selection gate pattern SSG. A plurality of the string
selection gate patterns SSG are disposed on the uppermost cell gate
pattern CG. The plurality of the string selection gate patterns SSG are
disposed at substantially the same level from a top surface of the
semiconductor substrate 200.

[0130] As illustrated in FIG. 21, the string selection gate patterns SSG
extend in a first direction D1 and be spaced apart from each other in a
second direction D2 perpendicular to the first direction D1 when viewed
from a plan view. A separation insulating pattern 235 is disposed between
the string selection gate patterns SSG adjacent to each other. The
separation insulating pattern 235 upward extend to be disposed between
the uppermost insulating patterns 210ua on the string selection gate
patterns SSG. As illustrated in FIG. 21, the cell gate patterns CG and
the ground selection gate pattern GSG have plate shapes when viewed from
a plan view.

[0131] A plurality of vertical active patterns VAP are disposed in a
plurality of holes 215, respectively, penetrating the gate structure. A
gate dielectric layer GEL is disposed between a sidewall of each of the
vertical active patterns VAP and each of the gate patterns GSG, CG, and
SSG. In an embodiment, the gate dielectric layer GEL is disposed between
the entire inner sidewall of each of the holes 215 and the entire
sidewall of each of the vertical active patterns VAP. For example, the
gate dielectric layer GEL covers the entire sidewall of the vertical
active pattern VAP. The vertical active pattern VAP has a pipe shape or a
macaroni shape. According to an embodiment, an inner space surrounded by
the vertical active pattern VAP is filled with a filling dielectric
pattern 225. The vertical active pattern VAP contacts the common source
region CSR.

[0132] As illustrated in FIG. 21, the vertical active patterns VAP are
two-dimensionally arranged to constitute rows and columns when viewed
from a plan view. The columns are parallel to the first direction D1, and
the rows are parallel to the second direction D2. The vertical active
patterns VAP in each of the columns penetrate each of the string
selection gate pattern SSG.

[0133] Semiconductor patterns 240 are disposed on the gate structure and
extend in the second direction D2. The semiconductor patterns 240 are
separated from each other. Each of the semiconductor patterns 240 is
connected to the vertical active patterns VAP constituting each of the
rows. In more detail, each of the semiconductor patterns 240 contacts the
vertical active patterns VAP constituting each of the rows. A string
drain region 250 doped with dopants of the second conductivity type is
disposed in each of the semiconductor patterns 240. The string drain
region 250 is spaced apart from the vertical active patterns VAP. The
string selection gate pattern SSG controls a vertical channel region
defined in the vertical active pattern VAP beside the string selection
gate pattern SSG and a horizontal channel region defined in the
semiconductor pattern 240 over the string selection gate pattern SSG. Due
to the horizontal channel region of the string selection gate pattern
SSG, vertical channel regions defined in the vertical active pattern VAP
of a string selection transistor, cell transistors, and a ground
selection transistor can be electrically connected to the string drain
region 250.

[0134] A body pickup region 255 doped with dopants of the first
conductivity type is disposed in each of the semiconductor pattern 240.
The body pickup region 255 is spaced apart from the string drain region
250. A voltage is provided to bodies of the ground selection, cell, and
string selection transistors defined in the vertical active pattern VAP
through the body pickup region 255. For example, according to an
embodiment, an erasing voltage is provided to the bodies of the
transistors through the body pickup region 255 during an erasing
operation of the 3D semiconductor memory device. Thus, even though the
vertical active patterns VAP are not in contact with the well region in
the semiconductor substrate 200 due to the common source region CSR, the
erasing voltage can be provided to the bodies of the transistors through
the body pickup region 255 to perform the erasing operation. As a result,
a speed of the erasing operation can be improved.

[0135] When the erasing voltage is not provided to the bodies in the
vertical active pattern VAP, the erasing operation may be performed using
a gate-induced drain leakage (GIDL) phenomenon, but a speed of the
erasing operation using the GIDL phenomenon may be reduced. However,
according to an embodiment of the inventive concept, due to the body
pickup region 255 disposed in the semiconductor pattern 240 on the gate
structure, the easing voltage can be provided to the bodies in the
vertical active pattern VAP. As a result, it is possible to improve the
speed of the erasing operation of the 3D semiconductor memory device.

[0136] A body pickup line 270 is electrically connected to the body pickup
region 255, and a bit line BL is electrically connected to the string
drain region 250. The bit line BL is disposed at a level different from
the body pickup line 270 with respect to the top surface of the
semiconductor substrate 200.

[0137] For example, a first interlayer dielectric layer 260 is disposed on
the gate structure and the semiconductor patterns 240, and the body
pickup line 270 is disposed on the first interlayer dielectric layer 260.
The body pickup line 270 is electrically connected to the body pickup
region 255 through a first contact plug 265 penetrating the first
interlayer dielectric layer 260. The body pickup line 270 extends in the
first direction D1. A second interlayer dielectric layer 275 is disposed
on the first interlayer dielectric layer 260 and the body pickup line
270. The bit line BL is disposed on the second interlayer dielectric
layer 275. The bit line BL is electrically connected to the string drain
region 240 through a second contact plug 280 successively penetrating the
second and first interlayer dielectric layers 275 and 260. The bit line
BL extends in the second direction D2. For example, the bit line BL
crosses the body pickup line 270.

[0138] FIGS. 23A, 24A, and 25A are plan views illustrating a method of
manufacturing a 3D semiconductor memory device according to an embodiment
of the inventive concept, and FIGS. 23B, 24B, and 25B are cross-sectional
views taken along lines II-II' of FIGS. 23A, 24A, and 25A, respectively.

[0139] Referring to FIGS. 23A and 23B, a common source region CSR is
formed in a semiconductor substrate 200. Subsequently, a preliminary gate
structure is formed on the semiconductor substrate 200. The preliminary
gate structure is disposed on the common source region CSR. The
preliminary gate structure includes insulating patterns 202, 210, and
210u and gate patterns GSG, CG, and UG which are alternately and
repeatedly stacked. The preliminary gate structure includes a ground
selection gate pattern having a plate shape and cell gate patterns CG
having plate shapes. The uppermost gate pattern UG and the uppermost
insulating pattern 210u of the preliminary gate structure have plate
shapes.

[0140] Referring to FIGS. 24A and 24B, the uppermost insulating pattern
210u and the uppermost gate pattern UG of the preliminary gate structure
are patterned to form a plurality of string selection gate patterns SSG
extending in a first direction D1.

[0141] An uppermost insulating pattern 210ua extending in the first
direction D1 is formed on each of the string selection gate patterns SSG.
Thus, it is possible to form the gate structure described with reference
to FIGS. 21 and 22. A separation insulating pattern 235 is formed between
the string gate patterns SSG.

[0142] Holes 215 are formed to penetrate the gate structure. A gate
dielectric layer GEL is formed on inner sidewalls of the holes 215. A
vertical active pattern VAP and a filling dielectric pattern 225 are
formed in each of the holes 215.

[0143] After the gate structure is formed, the holes 215 and the vertical
active patterns VAP are formed. Alternatively, after the holes 215 and
the vertical active patterns VAP are formed in the preliminary gate
structure, the uppermost insulating pattern 210u and the uppermost gate
pattern UG of the preliminary gate structure are patterned to form the
gate structure.

[0144] Referring to FIGS. 25A and 25B, a semiconductor layer is
subsequently formed on the semiconductor substrate 200 having the gate
structure. The semiconductor layer is patterned to form semiconductor
patterns 240 extending in the second direction D2. Dopants of a first
conductivity type are injected into first regions of the semiconductor
patterns 240 to form body pickup regions 255. Dopants of a second
conductivity type are injected into second regions of the semiconductor
patterns 240 to form string drain regions. After the body pickup regions
255 are formed, the string drain regions 250 are formed. Alternatively,
after the string drain regions 250 are formed, the body pickup regions
255 are formed.

[0145] Alternatively, a first doped region of the first conductivity type
and a second doped region of the second conductivity type are formed in
the semiconductor layer. The first doped region is separated from the
second doped region. The semiconductor layer, the first doped region, and
the second doped region are patterned to form the semiconductor patterns
240, the string drain regions 250, and the body pickup regions 255.

[0146] Subsequently, the first interlayer dielectric layer 260, the first
contact plug 265, and the body pickup line 270 illustrated in FIGS. 21
and 22 are sequentially formed. Subsequently, the second interlayer
dielectric layer 275, the second contact plug 280 and the bit line BL
illustrated in FIGS. 21 and 22 are sequentially formed. Thus, it is
possible to realize the 3D semiconductor memory device illustrated in
FIGS. 21 and 22.

[0147] According to an embodiment, the components described in connection
with FIGS. 21 to 25 are formed of the same materials as the respective
corresponding components described in FIGS. 1 to 20. According to an
embodiment, the body pickup region 255 and the body pickup line 270 are
applied to the embodiment described in connection with FIGS. 1 to 20.
According to an embodiment, the embodiment described with reference to
FIGS. 5 to 9 is applied to the embodiment described in connection with
FIGS. 21 to 25 under a non-contradictable condition.

[0148] FIG. 26 is a plan view illustrating a 3D semiconductor memory
device according to an embodiment of the inventive concept, and FIG. 27
is a cross-sectional view taken along a line of III-III' FIG. 26.

[0149] Referring to FIGS. 26 and 27, an electrode-doped region 301 doped
with dopants of a first or a second conductivity type is disposed in a
semiconductor substrate 300. A first gate structure GS1 and a second gate
structure GS2 are disposed on the semiconductor substrate 300. The first
and second gate structures GS1 and GS2 are disposed on the
electrode-doped region 301. The first and second gate structures GS1 and
GS2 extend in parallel in a first direction D1 when viewed from a plan
view. The first and second gate structures GS1 and GS2 are spaced apart
from each other in a second direction D2.

[0150] The first gate structure GS1 includes first insulating patterns
305a, 310a, 310ua and first gate patterns CG1 and SSG which are
alternately and repeatedly stacked. The first gate patterns CG1 and SSG
include a plurality of first cell gate patterns CG1 sequentially stacked,
and a string selection gate pattern SSG on the uppermost first cell gate
pattern of the first cell gate patterns CG1. The lowermost gate pattern
of the first gate patterns CG1 and SSG corresponds to the lowermost first
cell gate pattern of the first cell gate patterns CG1. For example, the
first gate structure GS1 does not include a ground selection gate
pattern. The second gate structure GS2 includes second insulating
patterns 305b, 310b, 310ub and second gate patterns CG2 and GSG which are
alternately and repeatedly stacked. The second gate patterns CG2 and GSG
include a plurality of second cell gate patterns CG2 sequentially stacked
and a ground selection gate pattern GSG on the uppermost second cell gate
pattern of the second cell gate patterns CG2. The lowermost gate pattern
of the second gate patterns CG2 and GSG corresponds to the lowermost
second cell gate pattern of the second cell gate patterns CG2.

[0151] The lowermost first insulating pattern 305a of the first insulating
patterns 305a, 310a, and 310ua is disposed between the lowermost first
cell gate pattern CG1 and the semiconductor substrate 300, and the
lowermost second insulating pattern 305b of the second insulating
patterns 305b, 310b, and 310ub is disposed between the lowermost second
cell gate pattern CG1 and the semiconductor substrate 300. The uppermost
first insulating pattern 310ua of the first insulating patterns 305a,
310a, and 310ua is disposed on the string selection gate pattern SSG, and
the uppermost second insulating pattern 310ub of the second insulating
patterns 305b, 310b, and 310ub is disposed on the ground selection gate
pattern GSG.

[0152] First vertical active patterns VAP1 are disposed in first holes
315a, respectively, penetrating the first gate structure GS1. Second
vertical active patterns VAP2 are disposed in second holes 315b,
respectively, penetrating the second gate structure GS2. As illustrated
in FIG. 26, the first vertical active patterns VAP1 and the second
vertical active patterns VAP2 constitute a plurality of rows parallel to
the second direction D2 when viewed from a plan view. Each of the rows
includes each of the first vertical active patterns VAP1 and each of the
second vertical active patterns VAP2. The first vertical active patterns
VAP1 are arranged in a column shape or in a zigzag shape along the first
direction D1. Likewise, the second vertical active patterns VAP2 are
arranged in a column shape or in a zigzag shape along the first direction
D1.

[0153] As illustrated in FIG. 27, bottom ends of the first vertical active
pattern VAP1 and the second vertical active pattern VAP2 in each of the
rows are connected to each other to constitute a U-shape active part. The
first and second vertical active patterns VAP1 and VAP2 in each of the
rows are connected to each other by an active connection portion ACP in a
recess region 302 which is formed in the semiconductor substrate 300. The
active connection portion ACP is formed of the same semiconductor
material as the first and second vertical active patterns VAP1 and VAP2.
The first vertical active pattern VAP1, the active connection portion
ACP, and the second vertical active pattern VAP 2 of the U-shape active
part are connected to each other without boundaries to constitute one
body. In an embodiment, the first vertical active pattern VAP1, the
active connection portion ACP, and the second vertical active pattern VAP
2 of the U-shape active part have a pipe shape or a macaroni shape. In an
embodiment, a filling dielectric pattern 325 fills an inner space
surrounded by the first vertical active pattern VAP1, the active
connection portion ACP, and the second vertical active pattern VAP2. In
an embodiment, the filling dielectric pattern 325 is omitted. The first
vertical active pattern VAP1, the active connection portion ACP, and the
second vertical active pattern VAP2 have pillar shapes.

[0154] A gate dielectric layer GEL is disposed between a sidewall of each
of the first and second vertical active patterns VAP1 and VAP2 and each
of the first and second gate patterns CG1, SSG, CG2, and GSG. The gate
dielectric layer GEL covers an entire sidewall of the first vertical
active pattern VAP1 and an entire sidewall of the second vertical active
pattern VAP 2. The gate dielectric layer GEL extends to be disposed
between an inner surface of the recess region 302 and the active
connection portion ACP. Thus, the active connection portion ACP is
insulated from the electrode-doped region 301. A predetermined voltage is
applied to the electrode-doped region 301 to generate a connection
channel in the active connection portion ACP during an operation of the
3D semiconductor memory device according to an embodiment. Vertical
channels in the first vertical active pattern VAP1 are electrically
connected to vertical channels in the second vertical active pattern VAP2
through the connection channel.

[0155] Device isolation patterns 330 are disposed at two opposite sides of
each of the first and second gate structures GS1 and GS2. In an
embodiment, top surfaces of the device isolation patterns 330 are
substantially coplanar with top surfaces of the uppermost first and
second insulating patterns 310ua and 310ub.

[0156] The U-shape active part and portions of the first and second gate
structures GS1 and GS2 surrounding the U-shape active part constitute one
U-shape cell string. The string selection gate pattern SSG and the ground
selection gate pattern GSG of the U-shape cell string correspond to the
uppermost gate pattern of the first gate structure GS1 and the uppermost
gate pattern of the second gate structure GS2, respectively.

[0157] Semiconductor patterns 340 are disposed on the first gate structure
GS1, the second gate structure GS2, and the device isolation patterns
330. The semiconductor patterns 340 extend in parallel with the second
direction D2 when viewed from a plan view. The semiconductor patterns 340
are laterally separated from each other. Each of the semiconductor
patterns 340 is connected to top ends of the first and second vertical
active patterns VAP1 and VAP2 in each of the rows. In more detail, each
of the semiconductor patterns 340 contacts the top ends of the first and
second vertical active patterns VAP1 and VAP2 in each of the rows.

[0158] A string drain region 350D is disposed in each of the semiconductor
pattern 340 and is spaced apart from the first and second vertical active
patterns VAP1 and VAP2. A portion of the string drain region 350D
overlaps the string selection gate pattern SSG. The string selection gate
pattern SSG controls a first horizontal channel region defined in the
semiconductor pattern 340 over the string selection gate pattern SSG and
a first vertical channel region defined in the first vertical active
pattern VAP beside the string selection gate pattern SSG. Two opposite
ends of the first horizontal channel region are connected to the string
drain region 350D and the first vertical channel region, respectively.

[0159] A string source region 350S is disposed in each of the
semiconductor patterns 340 and is spaced apart from the vertical active
patterns VAP1 and VAP2 and the string drain region 350D. A portion of the
string source region 350S overlaps the ground selection gate pattern GSG.
The ground selection gate pattern GSG controls a second horizontal
channel region defined in the semiconductor pattern 340 over the ground
selection gate pattern GSG and a second vertical channel region defined
in the second vertical active pattern VAP2 beside the ground selection
gate pattern GSG. Two opposite ends of the second horizontal channel
region are connected to the string source region 350S and the second
vertical channel region, respectively.

[0160] A body pickup region 355 is disposed in each of the semiconductor
patterns 340. The body pickup region 355 is spaced apart from the string
drain region 350D and the string source region 350S. The body pickup
region 355 is disposed between the string drain region 350D and the
string source region 350S.

[0161] In an embodiment, in a plan view, a top surface of the first
vertical active pattern VAP1 is disposed between the string drain region
350D and the body pickup region 355, and a top surface of the second
vertical active pattern VAP2 is disposed between the body pickup region
355 and the string source region 350S.

[0162] The body pickup region 355 is doped with dopants of the first
conductivity type, and the string drain and source regions 350D and 350S
are doped with dopants of the second conductivity type.

[0163] A body pickup line 370B is electrically connected to the body
pickup region 355, and a common source line 370S is electrically
connected to the string source region 350S. A bit line BL is electrically
connected to the string drain region 350D. The bit line BL is disposed at
a level different from at least the common source line 370S with respect
to a top surface of the semiconductor substrate 300. The body pickup line
370B is disposed at a level different from the bit line BL.

[0164] For example, a first interlayer dielectric layer 360 is disposed on
the semiconductor patterns 340. The body pickup line 370B and the common
source line 370S are disposed on the first interlayer dielectric layer
360. The body pickup line 370B and the common source line 370S extend in
parallel in the first direction D1. The body pickup line 370B is
electrically connected to the body pickup region 355 through a first
contact plug 365B penetrating the first interlayer dielectric layer 360.
The common source line 370S is electrically connected to the string
source region 350S through a second contact plug 365S penetrating the
first interlayer dielectric layer 360.

[0165] A second interlayer dielectric layer 375 is disposed on the first
interlayer dielectric layer 360, the body pickup line 370B, and the
common source line 370S. The bit lines BL are disposed on the second
interlayer dielectric layer 375 and extend in the second direction D2.
Each of the bit lines BL is electrically connected to the string drain
region 350D in each of the semiconductor patterns 340 through a third
contact plug 380 successively penetrating the second and first interlayer
dielectric layers 375 and 360.

[0166] FIGS. 28A, 29A, 30A, and 31A are plan views illustrating a method
of manufacturing a 3D semiconductor memory device according to an
embodiment of the inventive concept, and FIGS. 28B, 29B, 30B, and 31B are
cross-sectional views taken along lines of III-III' FIGS. 28A, 29A, 30A,
and 31A, respectively.

[0167] Referring to FIGS. 28A and 28B, dopants of a first or a second
conductivity type are provided into the semiconductor substrate 300 to
form an electrode-doped region 301. Recess regions 302 are formed in the
semiconductor substrate 300. The recess regions 302 are arranged in a
first direction D1 in a plan view. The recess regions 302 are spaced
apart from each other. The recess regions 302 are formed in the
electrode-doped region 301. A bottom sacrificial pattern 303 is formed in
each of the recess region 302.

[0168] Insulating layers 305, 310, and 310u and conductive layers 307 are
alternately and repeatedly stacked on the semiconductor substrate 300.
The lowermost insulating layer 305 of the insulating layers 305, 310, and
310u is disposed between the semiconductor substrate 300 and the
lowermost conductive layer of the conductive layers 307. The uppermost
insulating layers 310u of the insulating layers 305, 310, and 310u is
disposed on the uppermost conductive layer of the conductive layers 307.

[0169] Referring to FIGS. 29A and 29B, the insulating layers 305, 310, and
310u and the conductive layers 307 are patterned to form first holes 315a
and second holes 315b. The first holes 315a and the second holes 315b
constitute a plurality of rows parallel to a second direction D2 when
viewed from a plan view. The first hole 315a and the second hole 315b in
each of the rows expose each of the bottom sacrificial pattern 303. The
bottom sacrificial pattern 303 is formed of a material having an etch
selectivity with respect to the insulating layers 305, 310, and 310u, the
conductive layers 307, and the semiconductor substrate 300. The bottom
sacrificial patterns 303 exposed by the first and second holes 315a and
315b are removed to expose inner surfaces of the recess regions 302.

[0170] Referring to FIGS. 30A and 30B, a gate dielectric layer GEL is
conformally formed on the semiconductor substrate 300 having the holes
315a and 315b and the exposed recess regions 302. The gate dielectric
layer GEL is conformally formed on inner surfaces of the holes 315a and
315b and the exposed inner surfaces of the recess regions 302. An active
layer is conformally formed on the semiconductor substrate 300 having the
gate dielectric layer GEL, and then a filling dielectric layer is formed
to fill the holes 315a and 315b and the recess regions 302. The active
layer is formed of a semiconductor material for vertical active patterns
VAP1 and VAP2. The filling dielectric layer and the active layer are
planarized to form a first vertical active pattern VAP1 in each of the
first holes 315a, a second vertical active pattern VAP2 in each of the
second holes 315b, and an active connection portion ACP in each of the
recess region 302. Filling dielectric patterns 325 are formed. The
uppermost insulating layer 310u is recessed during the planarization of
the filling dielectric layer and the active layer. The recessed uppermost
insulating layer is denoted by reference numeral 310u'. A surface
treatment process is performed on the recessed uppermost insulating layer
310u'.

[0171] Referring to FIGS. 31A and 31B, the insulating layers 305, 310, and
310u and the conductive layers 307 are successively patterned to form a
first gate structure GS1 and a second gate structure GS2. A structural
description of the first and second gate structures GS1 and GS2 is
described above with reference to FIGS. 26 and 27. Device isolation
patterns 330 are formed at two opposite sides of the first and second
gate structures GS1 and GS2.

[0172] Subsequently, a semiconductor layer is formed on the semiconductor
substrate 300. The semiconductor layer contacts the vertical active
patterns VAP1 and VAP2. The semiconductor layer is patterned to form
semiconductor patterns 340. Dopants of the first conductivity type are
provided into the semiconductor patterns 340 to form body pickup regions
355. Dopants of the second conductivity type are provided into the
semiconductor patterns 340 to form string drain regions 350D and string
source regions 350S. Alternatively, after a first doped region doped with
dopants of the first conductivity type, and second and third doped
regions doped with dopants of the second conductivity type are formed in
the semiconductor layer, the semiconductor layer and the first, second
and third doped regions are patterned to form the semiconductor patterns
340, the body pickup regions 355, the string drain regions 350D, and the
string source regions 350S.

[0173] Subsequently, the interlayer dielectric layers 260 and 275, the
contact plugs 365B, 365S, and 380, and the lines 370B, 370S, and BL of
FIGS. 26 and 27 are formed. Thus, it is possible to realize the 3D
semiconductor memory device illustrated in FIGS. 26 and 27.

[0174] According to an embodiment, the components described in connection
with FIGS. 26 to 31 are formed of the same materials as the respective
corresponding components described above in connection with FIGS. 1 to
20. According to an embodiment, the embodiment described with reference
to FIGS. 5 to 9 is applied to the embodiment described in connection with
FIGS. 26 to 31 under a non-contradictable condition.

[0176]FIG. 32 is a schematic block diagram illustrating an example of an
electronic system including 3D semiconductor memory devices according to
an embodiment of the inventive concept.

[0177] Referring to FIG. 32, an electronic system 1100 according to an
embodiment of the inventive concept includes a controller 1110, an
input/output (I/O) unit 1120, a memory device 1130, an interface unit
1140 and a data bus 1150. At least two of the controller 1110, the I/O
unit 1120, the memory device 1130 and the interface unit 1140 communicate
with each other through the data bus 1150. The data bus 1150 corresponds
to a path through which electrical signals are transmitted.

[0178] The controller 1110 includes at least one of a microprocessor, a
digital signal processor, a microcontroller or another logic device. The
other logic device has a similar function to any one of the
microprocessor, the digital signal processor and the microcontroller. The
I/O unit 1120 includes a keypad, a keyboard and/or a display unit. The
memory device 1130 stores data and/or commands. The memory device 1130
includes at least one of the 3D semiconductor memory devices according to
the embodiments described above. The memory device 1130 further includes
another type of semiconductor memory devices which are different from the
3D semiconductor memory devices described above. For example, according
to an embodiment, the memory device 1130 further includes a magnetic
memory device, a static random access memory (SRAM) device, a dynamic
random access memory (DRAM) device, a resistive random access memory
(RRAM) device, and/or a phase change memory device. The interface unit
1140 transmits electrical data to a communication network or receives
electrical data from a communication network. The interface unit 1140
operates by wireless or cable. For example, the interface unit 1140
includes an antenna for wireless communication or a transceiver for cable
communication. According to an embodiment, the electronic system 1100
further includes a fast DRAM device and/or a fast SRAM device which acts
as a cache memory for improving an operation of the controller 1110.

[0179] The electronic system 1100 is applied to a personal digital
assistant (PDA), a portable computer, a web tablet, a wireless phone, a
mobile phone, a digital music player, a memory card or other electronic
products. The other electronic products receive or transmit information
data by wireless.

[0180]FIG. 33 is a schematic block diagram illustrating an example of
memory cards including 3D semiconductor memory devices according to
embodiments of the inventive concept.

[0181] Referring to FIG. 33, a memory card 1200 according to an embodiment
of the inventive concept includes a memory device 1210. The memory device
1210 includes at least one of the 3D semiconductor memory devices
according to the embodiments mentioned above. In an embodiment, the
memory device 1210 further includes another type of semiconductor memory
devices which are different from the 3D semiconductor memory devices
according to the embodiments described above. For example, according to
an embodiment, the memory device 1210 further includes a magnetic memory
device, a SRAM device, a DRAM device, a RRAM device, and/or a phase
change memory device. The memory card 1200 includes a memory controller
1220 that controls data communication between a host and the memory
device 1210.

[0182] The memory controller 1220 includes a central processing unit (CPU)
1222 that controls overall operations of the memory card 1200. The memory
controller 1220 includes an SRAM device 1221 used as an operation memory
of the CPU 1222. According to an embodiment, the memory controller 1220
further includes a host interface unit 1223 and a memory interface unit
1225. The host interface unit 1223 is configured to include a data
communication protocol between the memory card 1200 and the host. The
memory interface unit 1225 connects the memory controller 1220 to the
memory device 1210. The memory controller 1220 further includes an error
check and correction (ECC) block 1224. The ECC block 1224 detects and
corrects errors of data which are read out from the memory device 1210.
According to an embodiment, the memory card 1200 further includes a read
only memory (ROM) device that stores code data to interface with the
host. The memory card 1200 is used as a portable data storage card.
Alternatively, the memory card 1200 is realized as solid state disks
(SSD) which are used as hard disks of computer systems.

[0183] As described above, the string drain region is disposed in the
semiconductor pattern on the gate structure and is spaced apart from the
vertical active pattern. Thus, dopants in the string drain region may not
influence a dopant concentration of the vertical channel region in the
vertical active pattern. As a result, it is possible to realize the 3D
semiconductor memory device with improved reliability and higher
integration.

[0184] While the embodiments of the inventive concept have been described,
it will be apparent to those skilled in the art that various changes and
modifications may be made without departing from the spirit and scope of
the inventive concept. Therefore, it should be understood that the above
embodiments are not limiting, but illustrative. Thus, the scope of the
inventive concept is to be determined by the broadest permissible
interpretation of the following claims and their equivalents, and shall
not be restricted or limited by the foregoing description.