Design007 Magazine

PCBD-May2015

Contents of this Issue

Navigation

Page 31 of 66

32 The PCB Design Magazine • May 2015
In the GB/s regime, accurate modeling of
conductor losses is a precursor to successful
high-speed serial link designs. Failure to model
roughness effects can ruin you day. For exam-
ple, Figure 1 shows the simulated total loss of a
40-inch PCB trace without roughness compared
to measured data. Total loss is the sum of dielec-
tric and conductor losses. As can be seen, with
just -3dB delta in insertion loss between simu-
lated and measured data at 12.5 GHz, there is
half the eye height opening with rough copper
at 25GB/s.
According to Wikipedia, close-packing of
equal spheres is defined as "a dense arrange-
ment of congruent spheres in an infinite, regu-
lar arrangement (or lattice)"
[8]
. The cubic close-
packed and hexagonal close-packed are ex-
amples of two regular lattices. The cannonball
by Bert Simonovich
laMsIM enTerPrIses
Cannonball Stack for Conductor
Roughness Modeling
stack is an example of a cubic close-packing of
equal spheres, and is the basis of modeling the
surface roughness of a conductor in this article.
So what do cannonballs have to do with
modeling copper roughness anyway? Well, oth-
er than sharing the principle of close packing
of equal spheres, and having a cool name, not
very much.
Background
In PCB construction, there is no such thing
as a perfectly smooth conductor surface. There
is always some degree of roughness that pro-
motes adhesion to the dielectric material. Un-
fortunately this roughness also contributes to
additional conductor loss.
Electro-deposited (ED) copper is widely used
in the PCB industry. The manufacturing process
sees a large rotating drum, made of polished
stainless steel or titanium, which is partially
submerged in a bath of copper sulfate solution.
The cathode terminal is attached to the drum,
article