The TMS320DM8127 DaVinci Digital Media processors also include a
high-definition video and imaging coprocessor 2 (HDVICP2) to off-load many video
and imaging processing tasks from the DSP core, making more DSP MIPS available
for common video and imaging algorithms. Additionally, the TMS320DM8127 DaVinci
Digital Media processors have a complete set of development tools for both the
ARM and DSP which include C compilers, a DSP assembly optimizer to simplify
programming and scheduling, and a Microsoft® Windows™ debugger interface for
visibility into source code execution.

The C674x DSP core is the high-performance floating-point DSP generation in
the TMS320C6000 DSP platform and is code-compatible with previous generation
C64x Fixed-Point and C67x Floating-Point DSP generation. The C674x
Floating-Point DSP processor uses 32KB of L1 program memory with EDC and 32KB of
L1 data memory. Up to 32KB of L1P can be configured as program cache. The
remaining memory is noncacheable no-wait-state program memory. Up to 32KB of L1D
can be configured as data cache. The remaining memory is noncacheable
no-wait-state data memory. The DSP has 256KB of L2 RAM with ECC, which can be
defined as SRAM, L2 cache, or a combination of both. All C674x L3 and off-chip
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