I2C (Inter-Integrated Circuit) is one of the most commonly used serial bus for interfacing sensors and other chips, and use two signals (Clock and Data) to control up to 128 chips thanks to its 7-bi address scheme. After announcing it was working of a new I3C standard in 2014, the MIPI Alliance has now formally introduced the MIPI I3C (Improved Inter Integrated Circuit) Standardized Sensor Interface, a backward compatible update to I2C with lower power consumption, and higher bitrate allowing it to be used for applications typically relying on SPI too.

I3C offers four data transfer modes that, on maximum base clock of 12.5MHz, provide a raw bitrate of 12.5 Mbps in the baseline SDR default mode, and 25, 27.5 and 39.5 Mbps, respectively in the HDR modes. After excluding transaction control bytes, the effective data bitrates achieved are 11.1,20, 23.5 and 33.3 Mbps.

MIPI I3C vs I2C Energy Consumption and Bitrate – Click to Enlarge

The MIPI Alliance has also provided a tablet comparing I3C, I2C, and SPI features, advantages and disadvantages.

Only full members can have full access to the spec? So much for hoping for wide adoption.

If the spec isn’t readily available, then individual manufacturers will tweak it for their products–said another way, they’ll violate the spec in ways that suit their needs. Their users won’t know and will build products and invest in using standard breaking parts. This will reduce their ability to use other conforming (or non-conforming in different ways) parts. And then we’ll end up with another mess of a standard. Why does this start to sound like an xkcd comic? 🙁

Something a little bit confusing. In the comparison section at the bottom it says that one limitation of I3C is it still has 7 bit addressing like I2C. It then goes on to say that a single I3C bus could only support “to around a dozen devices”.

If you can only support a dozen devices then it doesn’t really matter if you still have 7 bit addressing. You certainly won’t need any more than that.

@Dennis
Assuming the 7 bit addressing limitation is the same as with I2C, the problem that manufacturers of I3C chips only have 7 bits of addressing to choose from. What this means is that consumers of these chips will still run the possibility of having conflicting addresses on their bus. i.e. a Flash chip and accelerometer that have the same address cannot exist on the same bus together.

PCB designers will still have to ensure their devices are unique and with only 128 possible addresses for the entire world, there is a high likely hood that 2 devices you choose might conflict for your PCB.

@Sean
I understand what you are saying but my experience is that many devices have the ability to change addresses (either through addressing pins or writing to a register a new address). The worst case is to put the conflicting devices behind a mux.