Abstract:

An antifuse contains a first silicide layer, a grown silicon oxide
antifuse layer on a first surface of the first silicide layer, and a
first semiconductor layer having a first surface in contact with the
antifuse layer.

Claims:

1-15. (canceled)

16. A method of making an antifuse comprising:forming a first silicide
layer over a substrate;growing an insulating antifuse layer on a first
surface of the first silicide layer by converting a portion of the first
silicide layer to the insulating antifuse layer; andforming a first
semiconductor layer on the insulating antifuse layer.

17. The method of claim 16, wherein the first silicide layer is selected
from a group consisting of platinum silicide, nickel silicide, chromium
silicide and niobium silicide.

18. The method of claim 16, wherein:growing the insulating antifuse layer
comprises thermally growing a silicon oxide layer; andthe first
semiconductor layer comprises an intrinsic or lightly doped polysilicon
or single crystalline silicon layer of a first conductivity type.

19. The method of claim 16, further comprising:forming a heavily doped
third semiconductor layer over the substrate;forming the first silicide
layer on the third semiconductor layer; andforming a heavily doped second
semiconductor layer of a first conductivity type on the first
semiconductor layer.

20. The method of claim 19, wherein the first, the heavily doped second
and the heavily doped third semiconductor layers comprise n-type
polysilicon layers.

21. The method of claim 19, wherein the first and the heavily doped second
semiconductor layers comprise n-type polysilicon layers and the heavily
doped third semiconductor layer comprises a p-type polysilicon layer.

22. The method of claim 19, further comprising forming a second silicide
layer on the heavily doped second semiconductor layer.

23. The method of claim 22, wherein:The insulating antifuse layer is 2 to
15 nm thick;the first and the second silicide layers are 30 to 100 nm
thick;the first semiconductor layer is 30 to 800 nm thick;the heavily
doped second semiconductor layer is 30 to 500 nm thick; andthe heavily
doped third semiconductor layer is 30 to 500 nm thick.

24. The method of claim 22, further comprising:patterning the heavily
doped third semiconductor layer to form first rails extending in a first
direction;then forming the first silicide layer on the heavily doped
third semiconductor layer; andthen growing the antifuse layer on the
first silicide layer.

25. The method of claim 24, further comprising:forming an insulating fill
layer over and between the first rails; andplanarizing the insulating
fill layer using chemical mechanical polishing to form insulating fill
regions between adjacent first rails.

26. The method of claim 25, further comprising patterning the first
semiconductor layer, the heavily doped second semiconductor layer and the
second silicide layer to form a second rail stack disposed in a second
direction different than the first direction.

27. The method of claim 26, further comprising:forming a second antifuse
layer on the second silicide layer;forming an intrinsic or lightly doped
fourth semiconductor layer of the first conductivity type on the first
antifuse layer;forming a heavily doped fifth semiconductor layer of the
first conductivity type on the intrinsic or lightly doped fourth
semiconductor layer;forming a third silicide layer on the heavily doped
fifth semiconductor layer; andforming a third rail stack disposed in the
first direction.

28. The method of claim 19, further comprising:forming an interlayer
insulating layer over the substrate;forming the heavily doped third
semiconductor layer comprising a polysilicon layer on the interlayer
insulating layer;patterning the heavily doped third semiconductor layer
to form a plurality of first rails disposed in a first direction;forming
an insulating fill layer over and between the first rails;planarizing the
insulating fill layer using chemical mechanical polishing to form first
insulating fill regions between adjacent first rails, such that at least
top surfaces of the first rails are exposed;depositing a first metal
layer on the first rails and the insulating fill regions;forming a first
capping layer on the first metal layer;annealing the first metal layer at
a first temperature to react portions of the first metal layer with the
first rails to form the first silicide layer on the first
rails;selectively etching the capping layer and unreacted portions of the
first layer;annealing the first silicide layer at a second temperature
higher than the first temperature;growing the insulating antifuse layer
on the first silicide layer by exposing the first silicide layer to an
oxygen containing ambient at a temperature above room temperature;
andpatterning the first semiconductor layer and the heavily doped second
semiconductor layer to form second rail stacks extending in a second
direction different from the first direction.

29. The method of claim 28, wherein:growing the insulating antifuse layer
comprises exposing the first silicide layer to oxygen gas in a rapid
thermal annealing system at 600.degree. C. to 850.degree. C. for 20 to 60
seconds;forming the first semiconductor layer comprises depositing a
first polysilicon layer; andforming the second semiconductor layer
comprises depositing a second polysilicon layer on the first polysilicon
layer or doping an upper portion of the first polysilicon layer with
dopant of the first conductivity type.

30. The method of claim 16, further comprising passing a programming
current between the first silicide layer and the first semiconductor
layer to form a conductive link through the insulating antifuse layer
between first silicide layer and the first semiconductor layer.

31. The method of claim 16, wherein the step of growing the insulating
antifuse layer on the first surface of the first silicide layer comprises
converting an upper portion of the first silicide layer to silicon oxide
by exposing the first silicide layer to an oxygen containing ambient to
form a silicon oxide insulating antifuse layer.

32. A method of making an antifuse comprising:forming a first silicide
layer over a substrate;growing a silicon oxide antifuse layer on a first
surface of the first silicide layer by oxidizing a surface of the first
silicide layer; andforming a first semiconductor layer on the silicon
oxide antifuse layer.

35. The method of claim 32, further comprising programming the antifuse
such that a diode is formed in the programmed device.

Description:

FIELD OF THE INVENTION

[0001]The present invention is directed generally to semiconductor devices
and methods of fabrication and more particularly to an antifuse device
and method of fabrication.

BACKGROUND OF THE INVENTION

[0002]Antifuse devices are used in write once non-volatile memories. An
antifuse device usually contains an insulating antifuse layer between two
metal or semiconductor layers. When a programming voltage is applied
across the antifuse layer, a conductive link is formed between the metal
or semiconductor layers to provide a conductive path between these
layers. It is desirable to form antifuse devices with high quality
antifuse layers to improve device reliability. Furthermore, it is
desirable to form memories with antifuse devices with the smallest
possible dimensions in order to increase the device density and decrease
the cost of the memory.

BRIEF SUMMARY OF THE INVENTION

[0003]A preferred embodiment of the present invention provides an antifuse
comprising a first cobalt silicide layer, a grown silicon oxide antifuse
layer on a first surface of the first cobalt silicide layer, and a first
semiconductor layer having a first surface in contact with the antifuse
layer.

[0004]Another preferred embodiment of the present invention provides an
antifuse array disposed above a substrate. The array comprises a first
plurality of first spaced apart rail stacks disposed at a first height in
a first direction above the substrate. Each first rail stack comprises a
first cobalt silicide layer and a first thermally grown silicon oxide
antifuse layer on the first cobalt silicide layer. The array also
comprises a second plurality of spaced apart rail stacks disposed at a
second height above the first height and in a second direction different
from the first direction. Each second rail stack comprises a first
intrinsic or lightly doped semiconductor layer of a first conductivity
type in contact with the first antifuse layer, and a second heavily doped
second semiconductor layer of a first conductivity type above the first
semiconductor layer.

[0005]Another preferred embodiment of the present invention provides a
three dimensional antifuse array disposed above a substrate, comprising a
substrate and at least two sets of a plurality of first, laterally spaced
apart rail stacks disposed substantially in a first direction. Each set
of first rail stacks is disposed at a different height above the
substrate. Each first rail stack comprises a first intrinsic or lightly
doped semiconductor layer of a first conductivity type, a second heavily
doped semiconductor layer of a first conductivity type located over the
first semiconductor layer, a first metal or metal silicide layer located
over the second semiconductor layer, and a first antifuse layer located
on the first metal or metal silicide layer.

[0006]The array in this embodiment also comprises at least one set of a
plurality of second, laterally spaced apart rail stacks disposed
substantially in a second direction different from the first direction.
Each set of the second rail stacks is disposed at a height between
successive sets of first rail stacks. Each second rail stack comprises a
third intrinsic or lightly doped semiconductor layer of a first
conductivity type located on the first antifuse layer, a fourth heavily
doped semiconductor layer of a first conductivity type located over the
third semiconductor layer, a second metal or metal silicide layer located
over the fourth semiconductor layer, and a second antifuse layer located
on the second metal or metal silicide layer.

[0007]Another preferred embodiment of the present invention provides a
method of making an antifuse comprising forming a first silicide layer
over the substrate, growing an insulating antifuse layer on a first
surface of the first silicide layer, and forming a first semiconductor
layer on the antifuse layer.

[0008]Another preferred embodiment of the present invention provides a
method of making a three dimensional antifuse array disposed above a
substrate, comprising forming a first set of a plurality of first,
laterally spaced apart rail stacks disposed substantially in a first
direction above the substrate. Each first rail stack comprises a first
intrinsic or lightly doped semiconductor layer of a first conductivity
type, a second heavily doped semiconductor layer of a first conductivity
type located over the first semiconductor layer, a first metal or metal
silicide layer located over the second semiconductor layer, and a first
antifuse layer located on the first metal or metal silicide layer.

[0009]The method further comprises forming a second set of a plurality of
second, laterally spaced apart rail stacks disposed substantially in a
second direction different from the first direction, on the first set of
first rail stacks. Each second rail stack comprises a third intrinsic or
lightly doped semiconductor layer of a first conductivity type located on
the first antifuse layer, a fourth heavily doped semiconductor layer of a
first conductivity type located over the third semiconductor layer, a
second metal or metal silicide layer located over the fourth
semiconductor layer, and a second antifuse layer located on the second
metal or metal silicide layer.

[0010]The method further comprises forming a third set of a plurality of
first, laterally spaced apart rail stacks disposed substantially in a
first direction, on the second set of second rail stacks. Each first rail
stack comprises a first intrinsic or lightly doped semiconductor layer of
a first conductivity type located on the second antifuse layer, a second
heavily doped semiconductor layer of a first conductivity type located
over the first semiconductor layer, a first metal or metal silicide layer
located over the second semiconductor layer, and a first antifuse layer
located on the first metal or metal silicide layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011]FIG. 1 illustrates a side cross sectional view of a three
dimensional memory array.

[0012]FIG. 2 illustrates a side cross sectional view of an antifuse device
according to the first preferred embodiment of the present invention.

[0013]FIGS. 3A-I illustrate side cross sectional views of a preferred
method of making the antifuse device of FIG. 2.

[0014]FIG. 4 illustrates a side cross sectional view of a three
dimensional memory array according to the second preferred embodiment of
the present invention.

[0015]FIGS. 5A and 5B are transmission electron microscopy images of
antifuse devices according to the preferred embodiments of the present
invention.

[0016]FIGS. 6 and 7 are current-voltage plots of electrical test results
on antifuse devices according to the first preferred embodiment of the
present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

I. Introduction

[0017]PCT Published Application number WO 01/84553 published on Nov. 8,
2001, incorporated herein by reference in its entirety, discloses a
multi-level memory employing rail stacks. The rail stacks include
conductor and semiconductor layers separated by insulating antifuse
layers.

[0018]FIG. 1 illustrates one embodiment of a memory device described in WO
01/84553, where the insulating antifuse layers 106, 112 are located
between conductor layers 105, 113 and N- polysilicon layers 107, 111. The
memory device also contains N+ polysilicon layers 108 and 110. The memory
device shown in FIG. 1 contains four device levels 100, 101, 102 and 103
and two rail stacks 113, 114.

[0019]In the embodiment of the memory device of WO 01/84553 shown in FIG.
1, the insulating antifuse layer 106 is deposited on the conductor layer
105. For example, the antifuse silicon dioxide layer 106 may be deposited
by a deposition method such as chemical vapor deposition (CVD). However,
while CVD silicon dioxide forms an antifuse layer of sufficient quality,
a higher quality antifuse layer is desirable.

[0020]Furthermore, the rail stacks 113, 114 of WO 01/84553 contain six
layers each. Therefore, the rail stacks have a relatively large height.
The spaces between adjacent rail stacks in the same device level are
filled in with an insulating fill layer. Therefore, adjacent six layer
rail stacks in the same level should be spaced relatively far apart in
order to avoid high aspect spaces or vias between rail stacks and to
ensure proper filling of the spaces between the rail stacks by the
insulating fill layer. However, by spacing the adjacent rail stacks
further apart, the device density is decreased, which increases the
device cost.

[0021]The present inventor realized that in one preferred embodiment of
the present invention, the quality of the antifuse device is improved if
the insulating antifuse layer is grown, preferably thermally grown,
rather than deposited on a conductive layer. Furthermore, the present
inventor realized that in another preferred embodiment of the invention,
reducing the height of the rail stacks allows the spacing between
adjacent rail stacks to be reduced and the device density to be
increased.

II. The First Preferred Embodiment

[0022]An antifuse device of the first preferred embodiment contains a
grown antifuse layer on a conductive layer. Preferably, a silicon oxide
antifuse layer is thermally grown on a cobalt silicide conductive layer.
However, silicide layers other than cobalt silicide, such as platinum
silicide, nickel silicide (i.e., NiSi and NiSi2), chromium silicide
and niobium silicide, on which silicon oxide may be grown may be used
instead. Antifuse layers other than silicon oxide may be also be grown or
deposited on the silicide layer. By forming a grown antifuse layer on a
silicide layer instead of on a polysilicon layer, more power is delivered
to the antifuse layer. Silicon oxide layers grown on silicide layers,
such as cobalt silicide layers, can be formed with a greater range of
thicknesses without significantly affecting the antifuse breakdown
voltage compared to grown silicon oxide layers on silicon.

[0023]Silicon oxide antifuse layer preferably comprises the stoichiometric
silicon dioxide, but also may include a non-stoichiometric silicon oxide
layer (i.e., a layer having a silicon to oxygen ratio of other than 1:2)
and silicon oxide containing layers, such as silicon oxynitride (i.e.,
nitrogen containing silicon oxide). The silicide preferably comprises a
stoichiometric silicide, such as CoSi2, PtSi, NiSi, NiSi2,
CrSi2 and NbSi2, but also may include a non-stoichiometric
silicide layer (i.e., a cobalt silicide layer having a cobalt to silicon
ratio of other than 1:2) and a silicide layer containing additive
elements other than the primary metal (i.e., cobalt for CoSi2) and
silicon.

[0024]The term "grown" silicon oxide includes converting a portion of the
underlying silicide/silicon film stack to silicon oxide by exposing the
silicide layer to an oxygen containing ambient. Without wishing to be
bound by any particular theory, it is believed that silicon from the
underlying silicon layer in the stack diffuses through the cobalt
silicide layer to react with the oxygen containing ambient to form a
layer which substantially comprises silicon oxide. For example, the grown
oxide may be formed by dry oxidation (i.e., exposing the silicide to an
O2 containing gas), wet oxidation (i.e., exposing the silicide to
hot steam), plasma enhanced oxidation (i.e., exposing the silicide to an
oxygen plasma), chemical oxidation (i.e., exposing the silicide to an
oxidizing liquid) and electrochemical oxidation (such as anodic
oxidation). In contrast to a "grown" silicon oxide layer, a "deposited"
silicon oxide layer is formed on a surface by providing silicon and
oxygen atoms to the surface. For example, a silicon oxide layer is
deposited by CVD or sputtering.

[0025]Preferably, the silicon oxide layer is thermally grown at a
temperature above room temperature by dry, wet or plasma oxidation. Most
preferably, the silicon oxide layer is grown by exposing the silicide
layer to an oxygen atmosphere in a rapid thermal annealing system.

[0026]The silicide layer preferably comprises a silicide material on which
a silicon oxide layer may be grown. CoSi2, PtSi, NiSi, NiSi2,
CrSi2 and NbSi2 are preferred materials for the silicide layer,
because they form a mostly silicon oxide layer when exposed to an
oxidizing ambient. In contrast, other silicides (such as titanium
silicide) can form significant amounts of metal oxide layers (i.e.,
TiO2) rather than silicon oxide layers when they are exposed to an
oxidizing ambient. Metal oxide antifuse layers have an inferior quality
to silicon oxide antifuse layers, namely higher leakage currents compared
to silicon oxide. Cobalt silicide is most preferred because a good
quality oxide layer can be grown on it and because it has the lowest
resistivity out of the listed silicides. Low resistivity allows current
to be conducted with a thinner layer relative to a layer with higher
resistivity. Thinner layers result in smaller devices and require less
deposition time. However, the antifuse devices with thicker silicide
layers of higher resistivity can also be formed. Cobalt silicide is also
preferred because it is stable (i.e., resists agglomeration) up to about
850° C. High temperature stability is desirable because it allows
a high quality, high temperature oxide layer to be grown on the silicide
and because it allows a wider latitude when integrating the antifuse
device with other devices on the chip. NiSi is the second most preferred
silicide layer because it has a low resistivity that is comparable
CoSi2. However, NiSi is only stable up to about 600° C., and
transforms to a higher resistivity NiSi2 above about 600° C.
NiSi2 is stable up to about 700° C. Reference is made to a
cobalt silicide layer in the description of the preferred antifuse
devices below. However, it should be noted that the cobalt silicide layer
may be replaced with any of PtSi, NiSi, NiSi2, CrSi2 and
NbSi2 in these antifuse devices.

[0027]FIG. 2 illustrates an antifuse device 1 according to a preferred
aspect of the first embodiment. The antifuse device contains a conductive
layer, such as a first cobalt silicide layer 3, a grown silicon oxide
antifuse layer 5 on a first surface of the first cobalt silicide layer 3,
and a first semiconductor layer 7, having a first surface in contact with
the antifuse layer 5. Preferably, the layers 3, 5 and 7 are stacked in a
vertical direction, such that the first semiconductor layer 7 is formed
on the antifuse layer 5 and the antifuse layer 5 is formed on the
silicide layer 3, as shown in FIG. 2. However, the layers 3, 5 and 7 may
be stacked in a direction other than vertical, such as a horizontal
direction (i.e., sideways in FIG. 2), if desired.

[0028]The antifuse layer 5 is capable of being selectively breached by
passing a programming current between the first cobalt silicide layer 3
and the first semiconductor layer 7 to form a conductive link through
layer 5 between layers 3 and 7. Preferably, layer 7 is an intrinsic or
lightly doped semiconductor layer (i.e., N- or P-layer having a charge
carrier concentration of less than about 1018 cm-3, such as
1017 cm-3).

[0029]Preferably, the antifuse device 1 also contains a heavily doped
second semiconductor layer 9 of first conductivity type (i.e., N+ or P+
layer having a charge carrier concentration of more than about 1018
cm-3, such as 1020 cm-3). Layer 9 has a first surface in
contact with a second surface of the first semiconductor layer 7.
Preferably, layer 9 is formed on layer 7, as shown in FIG. 2.

[0030]The first semiconductor layer 7 may comprise an intrinsic or lightly
doped polysilicon layer or single crystalline silicon layer of a first
conductivity type. Layer 7 may also comprise amorphous silicon or other
semiconductor layers, such as SiGe or GaAs, if desired. The second
semiconductor layer 9 may comprise a heavily doped polysilicon layer or
single crystalline silicon layer of a first conductivity type.
Preferably, the first and second semiconductor layers comprise
polysilicon layers.

[0031]The antifuse device 1 also contains an optional heavily doped third
semiconductor layer 11, having a first surface in contact with a second
surface of the first cobalt silicide layer 3. Preferably, the cobalt
silicide layer 3 is formed on the third semiconductor layer 11. The third
semiconductor layer 11 comprises a heavily doped polysilicon layer or
single crystalline silicon layer. Preferably layer 11 is a polysilicon
layer.

[0032]The third semiconductor layer 11 may be of the same or opposite
conductivity type as the first 7 and second 9 semiconductor layers.
Preferably, the first 7, second 9 and third 11 semiconductor layers
comprise n-type polysilicon layers. Alternatively, the first 7 and second
9 semiconductor layers comprise n-type polysilicon layers and the third
semiconductor layer 11 comprises a p-type polysilicon layer. Of course,
the first 7 and second 9 semiconductor layers may comprise p-type
polysilicon layers, while the third semiconductor layer 11 may comprise a
p-type or n-type polysilicon layer. N-type polysilicon is preferred as
the material for layers 7, 9 and 11 because it provides an antifuse
device 1 with a lower leakage current than an antifuse device with p-type
polysilicon layers.

[0033]The antifuse device 1 may also contain a conductive layer, such as a
metal or metal silicide layer 13, having a first surface in contact with
a second surface of the second semiconductor layer 9. Layer 13 enhances
the conductivity of layer 9. Layer 13 may also comprise a cobalt silicide
layer. Alternatively, layer 13 may comprise other silicide layers, such
as titanium, tungsten or nickel silicide.

[0034]The layers 3 to 13 may have any suitable thickness. Preferably, the
antifuse layer 5 is 2 to 15 nm thick, such as 4 to 10 nm thick.
Preferably, the first 3 and the second 13 cobalt silicide layers may be
30 to 100 nm thick, such as 50 to 70 nm thick. Preferably, the first 7
semiconductor layer is 30 to 800 nm thick, such as 100 to 250 nm, most
preferably 100 to 200 nm thick. Preferably, the second 9 semiconductor
layer is 30 to 500 nm thick, such as 30 to 250 nm, most preferably 30 to
50 nm thick and the third 11 semiconductor layer is 30 to 800 nm thick,
such as 100 to 250 nm, most preferably 150 to 200 nm thick.

[0035]The antifuse device 1 may have any desired configuration.
Preferably, device 1 is laid out in a rail stack configuration. The first
metal silicide layer 3, the antifuse layer 5 and the third semiconductor
layer 11 are located in a first rail stack 15. The first semiconductor
layer 7, the second semiconductor layer 9 and the second cobalt silicide
layer 13 are located in a second rail stack 17. The layers in a rail
stack preferably have at least one and more preferably two common side
surfaces, and have a significantly larger length than width or thickness.
The rail stack may be straight (i.e., have a length extending in only one
direction) or not straight (i.e., have bends or turns).

[0036]While not shown in FIG. 2, other antifuse devices containing first
and second rail stacks are located adjacent to the antifuse device 1. A
planarized insulating fill layer 19 is located between adjacent first and
adjacent second rail stacks of adjacent antifuse devices. The fill layer
may comprise any one or more insulating layers, such as silicon oxide,
silicon nitride, silicon oxynitride, PSG, BPSG, spin-on glass or a
polymer based dielectric, such as polyimide.

[0037]The first rail stack 15 is located below the second rail stack 17.
Preferably, the first rail stack 15 extends perpendicular to the second
rail stack 17. However, the first and the second rail stacks may be
disposed at an angle other than 90 degrees with respect to each other.

[0038]The antifuse device 1 may be made by any desired method. A method of
making the antifuse device 1 according to a preferred aspect of the
present invention is shown in FIGS. 3A-3I.

[0039]The third semiconductor layer 11 is formed on or over a substrate
21, as shown in FIG. 3A. Preferably, layer 11 comprises a heavily doped
polysilicon layer formed on one or more interlayer insulating layer(s)
23, such as silicon oxide or silicon nitride, disposed over the substrate
21. However, if desired, layer 23 may comprise a portion of a silicon
substrate 21.

[0040]A first masking layer 25, such as a photoresist layer, is formed
over layer 11. The third semiconductor layer 11 is patterned (i.e., dry
or wet etched) using masking layer 25 to form a plurality of first
semiconductor rails 15 disposed in a first direction, as shown in FIG. 3B
(the first direction extends into the plane of the page of FIG. 3B). The
first masking layer 25 is then removed by conventional removal
techniques, such as ashing.

[0041]The first insulating fill layer 19 is deposited over and between the
first rails 15. Preferably, layer 19 is a silicon oxide layer deposited
by a high density plasma (HDP) process or another CVD deposition process.
The first insulating fill layer 19 is planarized using chemical
mechanical polishing or etchback to form first insulating fill regions
19A between adjacent first rails 15 (only one first rail 15 is shown for
clarity in FIG. 3C), such that at least top surfaces of the first rails
15 are exposed, as shown in FIG. 3C.

[0042]A first cobalt layer 27 is deposited on the first rails 15 and the
insulating fill regions 19A, as shown in FIG. 3D. It should be noted that
a platinum, nickel, chromium or niobium layer may be deposited instead of
the cobalt layer if it is desired to form a silicide of these metals
instead. The cobalt layer 27 may be deposited by any suitable deposition
method, such as sputtering, to an exemplary thickness of 20 to 50 nm,
such as 30 nm. An optional capping layer 29 is deposited on the first
cobalt layer 27, as shown in FIG. 3D. The capping layer may be sputter
deposited titanium, titanium nitride or any other suitable material. The
capping layer assists in the subsequent conversion of the cobalt layer to
cobalt silicide. If desired, the capping layer may be omitted.

[0043]The first cobalt layer 27 is annealed at a suitable temperature to
react portions of the first cobalt layer with the polysilicon of the
first rails 15 to form a first cobalt silicide layer 3 on the first rails
15, as shown in FIG. 3E. For example, the annealing may be carried out in
a rapid thermal annealing system at 400 to 700° C. for 20 to 100
seconds, preferably at 440° C. for 60 seconds. A portion of layer
3 extends above the top surface of regions 19A, while a portion of rail
15 is consumed by the silicide formation. The formation of cobalt
silicide on narrow polysilicon rails is also advantageous compared to
titanium silicide because cobalt silicide does not suffer from the fine
line effect (i.e., the inability to transform the high resistivity C49
phase to the low resistivity C54 phase on narrow linewidths. However,
titanium silicide suffers from the fine line effect when it is formed on
narrow polysilicon features.

[0044]The capping layer 29 and unreacted portions of the first cobalt
layer 27 are selectively removed by a selective etch, as shown in FIG.
3F. Any etching medium which selectively etches the capping layer and the
cobalt layer over the cobalt silicide layer may be used. Preferably,
selective wet etching is used.

[0045]The first cobalt silicide layer 3 is then annealed at a second
temperature higher than the first temperature to homogenize the cobalt
silicide layer. For example, the annealing may be carried out in a rapid
thermal annealing system at 550° C. to 800° C. for 30 to 60
seconds, preferably at 740° C. for 40 seconds. Furthermore, the
second annealing step may be omitted if the first annealing step is
carried out at a temperature above 700° C. Higher temperatures may
also be used for the first anneal, such as 1000 to 1200° C., if
the second anneal is omitted.

[0046]An antifuse layer 5 is selectively thermally grown on the first
cobalt silicide layer by exposing the first cobalt silicide layer 3 to an
oxygen containing ambient at a temperature above room temperature, as
shown in FIG. 3G. Preferably, the first cobalt silicide 3 layer is
exposed to oxygen gas in a rapid thermal annealing system at 600°
C. to 850° C. for 20 to 60 seconds, preferably at 700° C.
to 800° C. for 20 to 30 seconds. Alternatively, a steam ambient
(wet oxidation) may be used instead with a temperature of 800 to
1000° C. The growth of thin silicon oxide layers on a cobalt
silicide layer by annealing the cobalt silicide layer in an oxygen
ambient is described, for example, in R. Tung, Appl. Phys. Lett., 72 (20)
(1998) 2358-60; S, Mantl, et al., Appl. Phys. Lett., 67 (23) (1995) 3459-
and I. Kaendler, et al., J. Appl. Phys., 87 (1) (2000) 133-39,
incorporated herein by reference in their entirety. The antifuse layer 5
is formed on the top surface of layer 3 and on portions of side surfaces
of layer 3 that extend above insulating fill regions 19A. Silicon oxide
layers may be grown on platinum, nickel, chromium and niobium silicide
layers by a similar method.

[0047]The first semiconductor layer 7 is deposited on the antifuse layer
5. The second semiconductor layer 9 is then deposited on the first
semiconductor layer 7, as shown in FIG. 3H. Preferably, both layers
comprise in-situ doped n-type polysilicon layers. However, if desired,
the second semiconductor layer 9 may be formed by doping the upper
portion of the first semiconductor layer 7 with a higher concentration of
dopant ions than the lower portion. For example, the doping may be
carried out by ion implantation or diffusion after the layer 7 is formed,
or by increasing the doping concentration during the deposition of the
upper portion of layer 7 compared to the deposition of the lower portion
of layer 7.

[0048]The first 7 and second 9 semiconductor layers are pattered to form
second rail stacks 17 extending in a second direction different from the
first direction, as shown in FIG. 3I. FIG. 3I is a cross sectional view
across line A-A' in FIG. 3H. The rail stacks 17 are formed by forming a
second masking layer (not shown) on layer 9 and etching layers 7 and 9 to
form the rail stacks 17. A second insulating fill layer is deposited over
and between the second rail stacks 17. The second insulating fill layer
is planarized using chemical mechanical polishing or etchback to form
second insulating fill regions 19B between adjacent the second rail
stacks 17, such that at least top surfaces of the second rail stacks are
exposed, as shown in FIG. 3I. If desired, the conductive layer, such as a
metal or metal silicide layer 13, is formed over layer 9 and regions 19B.

[0049]In an alternative method of making the antifuse device 1, the first
cobalt silicide layer 3 is formed on the third semiconductor layer 11
before the third semiconductor layer 11 is patterned. For example, the
first cobalt silicide layer may be formed by reacting layer 11 with a
cobalt layer or by sputter depositing a cobalt silicide layer over layer
11. The first masking layer 25 is then formed on the first cobalt
silicide layer 3, and layers 11 and 3 are patterned together to form the
first rail stacks 15. Alternatively, the first masking layer 25 is formed
on the cobalt layer, the cobalt layer is patterned together with layer
11, and then the patterned cobalt layer is reacted with patterned layer
11 to form the cobalt silicide layer 3 on the first rail stacks 15. The
insulating fill layer 19 is then formed and planarized to expose the top
surface of the first cobalt silicide layer 3. In this case, the top of
the first cobalt silicide layer 3 is planar with the top of the
insulating fill regions 19A. This alternative method increases the
planarity of the device 1.

[0050]A programming voltage is applied such that current is passed between
the first cobalt silicide layer 3 and the first semiconductor layer 7 in
selected antifuse devices to form a conductive link through the antifuse
layer 5 between first cobalt silicide layer and the first semiconductor
layer. The programming may be accomplished either in the factory or in
the field. A Schottky diode is formed in the programmed antifuse (i.e., a
silicide to silicon connection). To sense the data programmed into the
antifuse, a voltage lower than the programming voltage is used.

III. The Second Preferred Embodiment

[0051]In a second preferred embodiment of the present invention, an array
201 of nonvolatile memory devices comprising a three dimensional array of
antifuse devices is provided as illustrated in FIG. 4. The array 201
contains at least two sets of a plurality of first, laterally spaced
apart rail stacks 215 disposed substantially in a first direction. Each
set of first rail stacks 215 is disposed at a different height above a
substrate 221.

[0052]The array 201 also contains at least one set of a plurality of
second, laterally spaced apart rail stacks 217 disposed substantially in
a second direction different from the first direction. Each set of the
second rail stacks 217 is disposed between successive sets of first rail
stacks 215.

[0053]The present inventor has realized that reducing the height of the
rail stacks allows the spacing between adjacent rail stacks to be reduced
and the device density to be increased. Thus, each rail stack 215, 217
may contain four layers rather than six, as shown in FIG. 1. For example,
for 0.15 micron wide rail stacks, the aspect ratio may be reduced to
about 2:1 from about 3.5:1 by reducing the height of the rail stacks.

[0054]The first 215 and second 217 rail stacks are oriented in different
directions from each other, but preferably contain the same following
four layers. A first intrinsic or lightly doped semiconductor layer of a
first conductivity type 207 is provided at the bottom of the stacks. A
second heavily doped second semiconductor layer of a first conductivity
type 209 is located on or over the first semiconductor layer 207. A metal
or metal silicide layer 203 is located on or over the second
semiconductor layer 209. An antifuse layer 205 is located on or over the
metal or metal silicide layer 203. The first semiconductor layer 207 of
each rail stack is located on the antifuse layer of the underlying rail
stack. While the rail stacks 215, 217 are described as containing the
same layers, the rail stacks 215 and 217 may contain a different number
of layers, layers of different composition or thickness, and/or layers
arranged in a different order.

[0055]Layers 203, 205, 207 and 209 may comprise the same layers having the
same thickness ranges as in the first embodiment of FIG. 2. Thus, the
metal or metal silicide layer 203 may comprise a cobalt silicide layer,
the antifuse layer 205 may comprise a thermally grown silicon oxide layer
and the semiconductor layers 207, 209 may comprise undoped or N- and N+
polysilicon layers. However, other materials may be used. For example,
tungsten, tantalum, aluminum, copper or metal alloys such as MoW and
metal silicides, such as TiSi2, CoSi2, or conductive compounds
such as TiN may be used as layer 203. Thermally grown or deposited
dielectric such as silicon dioxide, silicon nitride, silicon oxynitride,
amorphous carbon, other insulating materials or combinations of materials
or undoped amorphous silicon may be used for the antifuse layer 205.
Single crystal silicon, polysilicon, amorphous silicon or other compounds
semiconductors may be used for layers 207 and 209. The array 201 further
comprises a planarized insulating fill layer or regions 219A located
between adjacent first rail stacks 215 and adjacent second rail stacks
217 (not shown in FIG. 4).

[0056]The array 201 may have any number of rail stacks 215, 217. For
example, there may be two to eight rail stacks 215 and one to seven rail
stacks 217. Preferably, there are at least three sets of first rail
stacks 215 and at least two sets of second rail stacks 217.

[0057]Preferably, the first 215 and the second 217 rail stacks are
disposed perpendicular to each other. However, the first rail stacks may
deviate from a first direction by 1-30 degrees, such that they are
disposed "substantially" in the first direction. The second rail stacks
may deviate from the second direction by 1-30 degrees, such that they are
disposed "substantially" in the second direction. Thus, the first and
second rail stacks are not necessarily perpendicular to each other.

[0058]If desired, the array 201 may also contain a first partial rail
stack 235 disposed below a lower most first or second rail stack, as
shown in FIG. 4. The first partial rail stack 235 comprises a cobalt
silicide layer 203 and an antifuse layer 205 on the cobalt silicide
layer. If desired, layer 203 may be disposed on a heavily doped
semiconductor layer 209.

[0059]If desired, the array 201 may also contain a second partial rail
stack 237 disposed above an upper most first or second rail stack, as
shown in FIG. 4. The second partial rail stack 237 comprises an intrinsic
or lightly doped semiconductor layer 207 of a first conductivity type, a
heavily doped second semiconductor layer 209 of a first conductivity type
located over the fifth semiconductor layer, and a metal or metal silicide
layer 203 located over the layer 209.

[0060]A bit can be stored at each of the intersections of the first and
the second rail stacks. However, there are no physically discrete
individual memory cells at the intersections. Rather, memory cells are
defined by the rail stack intersections. This makes it easier to
fabricate the memory array. The term "memory cell" is intended broadly to
encompass physically discrete elements or elements that are defined by
the rail stacks, or any other localized region where a bit can be stored.
When the array is fabricated all the bits are in the zero (or one) state
and after programming, the programmed bits are in the one (or zero)
state.

[0061]The metal or metal silicide layers 203 at each level are either
bitlines or wordlines, depending on the programming voltage applied. This
simplifies the decoding and sensing and more importantly reduces
processing. Thus, antifuse devices vertically overlap each other. It
should be noted that the Schottky diodes in array 201 of FIG. 4 are
arranged in a "totem pole" configuration. In other words, the Schottky
diodes are stacked in the same direction, with the silicide layers 203
located between the N+ polysilicon layer 209 and the antifuse layer 205.
In contrast, the Schottky diodes of the array of FIG. 1 are arranged back
to back, where the alternating Schottky diodes are stacked in opposite
directions (i.e., the Schottky diode containing antifuse layer 106 is
upside down compared to the Schottky diode containing antifuse layer
112). In other words, in FIG. 1, the first conductor 109 is located
between two N+ polysilicon layers 108, 110, while the second conductor
113 is located between two antifuse layers 112.

[0062]For example, one antifuse device 1A is shown by dashed lines in FIG.
4. The device 1A is formed in the heavily doped semiconductor layer 209,
the metal or metal silicide layer 203 and the antifuse layer 205 of one
first rail stack 215 and in the intrinsic or lightly doped semiconductor
layer 207, the heavily doped semiconductor layer 209, and the metal or
metal silicide layer 203 of an adjacent second rail stack 217 overlying
said first rail stack 215. Another antifuse device 1B shown by dashed and
dotted lines in FIG. 4 is formed in the heavily doped semiconductor layer
209, the metal or metal silicide layer 203 and the antifuse layer 205 of
one second rail stack 217 and in the intrinsic or lightly doped
semiconductor layer 207, the heavily doped semiconductor layer 209, and
the metal or metal silicide layer 203 of an adjacent first rail stack 215
overlying said second rail stack 215.

[0063]The array 201 is fabricated on a substrate 221 which may be an
ordinary monocrystalline silicon substrate. Decoding circuitry, sensing
circuits, and programming circuits are fabricated in one embodiment
within the substrate 221 under the memory array 201 using, for instance,
ordinary MOS fabrication techniques. However, these circuits may also be
fabricated above the substrate. An insulating layer 223 is used to
separate the rail stacks 215, 217 from the substrate 221. This layer may
be planarized with, for instance, chemical-mechanical polishing (CMP) to
provide a flat surface upon which the array 201 may be fabricated. Vias
are used to connect conductors within the rail stacks to the substrate to
allow access to each rail stack in order to program data into the array
and to read data from the array. For instance, the circuitry within the
substrate 221 may select two particular rail stacks in order to either
program or read a bit associated with the intersection of these rail
stacks.

[0064]The array 201 may be made by any desired method. For example, if the
array contains cobalt silicide and thermally grown antifuse silicon oxide
layer, then the array may be made by the method shown in FIGS. 3A-I.

[0065]Thus, the first partial rail stack 235 is formed prior to the first
rail stack on the insulating layer 223 over the substrate 221. Then, the
intrinsic or lightly doped and heavily doped semiconductor layers 207,
209 are deposited on the first partial rail stack 235. The semiconductor
layers 207, 209 are patterned using a mask to form a plurality of the
first rail stacks 215 disposed in the first direction. An insulating fill
layer is formed over and between the first rail stacks 215. The
insulating fill layer is planarized using chemical mechanical polishing
to form first insulating fill regions 219A between adjacent first rail
stacks 215, such that at least top surfaces of the first rail stacks are
exposed. During the CMP, a portion of the layer 209 is removed.

[0066]A cobalt layer is deposited on the first rail stacks 215 and the
first insulating fill regions 219A. An optional capping layer is
deposited on the cobalt layer. The cobalt layer is annealed at a first
temperature to react portions of the first cobalt layer with the first
rails to form the cobalt silicide layer 203 on the first rail stacks 215.
The capping layer and unreacted portions of the first cobalt layer are
selectively etched away. The cobalt silicide layer 203 is annealed at a
second temperature higher than the first temperature. Then the antifuse
layer 205 is selectively grown on the cobalt silicide layer 203 by
exposing the cobalt silicide layer to an oxygen containing ambient at a
temperature above room temperature.

[0067]The steps are then repeated for a second rail stack 217 and other
subsequent first and second rail stacks. The second partial rail stack
237 is formed over the last full rail stack. Thus, a three dimensional
monolithic array is formed (i.e., where all the layers are deposited over
the same substrate). Alternatively, one or more rail stacks may be formed
over one substrate and then joined to one or more rail stacks formed over
a second substrate by any suitable bonding technique to form a
non-monolithic three dimensional array.

IV. Specific Examples

[0068]A plurality of antifuse devices shown in FIG. 5A were fabricated. A
roughly 50 nm thick cobalt silicide layer was formed on a plurality of N+
polysilicon rails doped 1×1020 cm-3. A roughly 10 nm
silicon dioxide antifuse layer was thermally grown on the cobalt silicide
layer, a 200 nm N-polysilicon layer doped 1×1017 cm-3 was
deposited on the antifuse layer, and a 250 nm N+ polysilicon layer doped
1×1020 cm-3 was deposited on the N-layer. The thickness
of the N+ layer was reduced to about 50 nm during the CMP of the
insulating fill layer. A transmission electron microscopy (TEM) image of
one antifuse device 1 is shown in FIG. 5B. In the middle of FIG. 5B, the
thickness of the cobalt silicide layer is 52 nm, and the thickness of the
antifuse layer is 10 nm. The thickness of the layers varies somewhat
along the length of the device.

[0069]To form the cobalt silicide layer, a sputtered cobalt layer and a
titanium capping layer were deposited on about 200 nm thick N+
polysilicon rails and annealed in a rapid thermal annealing system at
440° C. for 60 seconds. Portions of the polysilicon rails and the
cobalt layer were converted to cobalt silicide. After the unreacted
portions of the cobalt layer and the capping layer were selectively
etched, the cobalt silicide layer was annealed in the a rapid thermal
annealing system at 740° C. for 40 seconds. An antifuse layer was
formed on the cobalt silicide layer in a rapid thermal annealing system
by exposing the cobalt silicide layer to oxygen at 700° C. for 20
seconds or at 800° C. for 30 seconds.

[0070]The antifuse devices were electrically tested to determine their
breakdown voltage. The current-voltage plots of the electrical tests are
shown in FIGS. 6 and 7. When the silicon dioxide antifuse layers were
thermally grown in oxygen at 700° C. for 20 seconds, the antifuse
devices exhibited a breakdown voltage of about 5.5 volts, as shown in
FIG. 6. When the silicon dioxide antifuse layers were thermally grown in
oxygen at 800° C. for 30 seconds, the antifuse devices exhibited a
breakdown voltage of about 8.5 volts, as shown in FIG. 7.

[0071]The foregoing description of the invention has been presented for
purposes of illustration and description. It is not intended to be
exhaustive or to limit the invention to the precise form disclosed, and
modifications and variations are possible in light of the above teachings
or may be acquired from practice of the invention. The drawings are not
necessarily to scale and illustrate the device in schematic block format.
The drawings and description of the preferred embodiments were chosen in
order to explain the principles of the invention and its practical
application, and are not meant to be limiting on the scope of the claims.
It is intended that the scope of the invention be defined by the claims
appended hereto, and their equivalents.