(Cat? OR feline) AND NOT dog?
Cat? W/5 behavior
(Cat? OR feline) AND traits
Cat AND charact*

This guide provides a more detailed description of the syntax that is supported along with examples.

This search box also supports the look-up of an IP.com Digital Signature (also referred to as Fingerprint); enter the 72-, 48-, or 32-character code to retrieve details of the associated file or submission.

Concept Search - What can I type?

For a concept search, you can enter phrases, sentences, or full paragraphs in English. For example, copy and paste the abstract of a patent application or paragraphs from an article.

Concept search eliminates the need for complex Boolean syntax to inform retrieval. Our Semantic Gist engine uses advanced cognitive semantic analysis to extract the meaning of data. This reduces the chances of missing valuable information, that may result from traditional keyword searching.

Publishing Venue

Related People

Abstract

In this system for communication, in a processor, writing is prevented unless a lock and a key match. A read may occur, but it can be inhibited from loading into the memory output register 18 in Fig. 1, so that the read is blocked unless the lock and key match. Locks and keys are stored in memory. Keys can be rewritten during program execution if the proper interrupt level is invoked. Locks are changed by initial program load (IPL).

Country

United States

Language

English (United States)

This text was extracted from a PDF file.

At least one non-text object (such as an image or picture) has been suppressed.

This is the abbreviated version, containing approximately
36% of the total text.

In this system for communication, in a processor, writing is prevented unless
a lock and a key match. A read may occur, but it can be inhibited from loading
into the memory output register 18 in Fig. 1, so that the read is blocked unless
the lock and key match. Locks and keys are stored in memory. Keys can be
rewritten during program execution if the proper interrupt level is invoked. Locks
are changed by initial program load (IPL).

There is means provided in the system generating a unique interrupt signal
representing a unique interrupt level for each I/O device, and for predetermined
conditions internal to the processor. Key-bit storage is associated with each of
the interrupt levels. Other key-bits storage is associated with the address of each
I/O device. Initializing means selectively loads the lock-bits storage and key-bits
storage to specify allowable accesses. Comparing of key bits identifies a
requesting device or an interrupt level with stored lock bits, and inhibits access to
memory or I/O space when the key bits do not match the stored lock bits.

A two-data bus and address bus processor organization and design permit
implementation of a protection mechanism, based upon a protection adaptor
accessed from processor software via I/O commands through a program I/O
interface. In addition, this adapter has access to the address bus of the
processor. Moreover, control lines required for the implementation of this
adapter are available from a controller. The protection mechanism described is a
special type of an I/O adapter.

For its operation a protection adapter requires; (1) the identity of the current
interrupt levels; (2) a signal that a change in interrupt level is taking place; (3) the
address of the protected space being accessed; (4) a means to notify the
processor in case of protected space violation; (5) a mechanism for changing
keys to the protected space; (6) a mechanism for storing the lock bits for the
protected space; and (7) a mechanism for changing the lock bits and the key bits.

Memory Protection is accomplished by the memory protection adapter 9
shown in Fig. 1. The adapter 9 contains a storage table 10 for the lock bits.
Lock bits are assigned per block of memory space, as indicated by the memory
block address in table 10.

A two-bit lock protection is provided per two (2) K bytes protection of main
storage, and a two-bit lock protection is provided for each of the Register Space
Pages. The adapter 9 also contains the keys associated with each level of
interrupt in table 11.

During a "PSW (Program Status Word) SWAP", the processor goes through
a two-phase operation of, storing the current PSW and loading the new PSW.
Bus 12 carries the respective addresses of the current and new PSW during the
associated memory operations. Special tag lines 13 and 14, called "PSW 1" and
"PSW 2", identify the precise timing when the bu...