generic_events

- generic performance counter events

Description

The Solaris cpc(3CPC) subsystem implements a number of predefined, generic performance counter
events. Each generic event maps onto a single platform specific event and
one or more optional attributes. Each hardware platform only need support a
subset of the total set of generic events.

The defined generic events are:

PAPI_br_cn

Conditional branch instructions

PAPI_br_ins

Branch instructions

PAPI_br_msp

Conditional branch instructions mispredicted

PAPI_br_ntk

Conditional branch instructions not taken

PAPI_br_prc

Conditional branch instructions correctly predicted

PAPI_br_tkn

Conditional branch instructions taken

PAPI_br_ucn

Unconditional branch instructions

PAPI_bru_idl

Cycles branch units are idle

PAPI_btac_m

Branch target address cache misses

PAPI_ca_cln

Requests for exclusive access to clean cache line

PAPI_ca_inv

Requests for cache invalidation

PAPI_ca_itv

Requests for cache line intervention

PAPI_ca_shr

Request for exclusive access to shared cache line

PAPI_ca_snp

Request for cache snoop

PAPI_csr_fal

Failed conditional store instructions

PAPI_csr_suc

Successful conditional store instructions

PAPI_csr_tot

Total conditional store instructions

PAPI_fad_ins

Floating point add instructions

PAPI_fdv_ins

Floating point divide instructions

PAPI_fma_ins

Floating point multiply and add instructions

PAPI_fml_ins

Floating point multiply instructions

PAPI_fnv_ins

Floating point inverse instructions

PAPI_fp_ins

Floating point instructions

PAPI_fp_ops

Floating point operations

PAPI_fp_stal

Cycles the floating point unit stalled

PAPI_fpu_idl

Cycles the floating point units are idle

PAPI_fsq_ins

Floating point sqrt instructions

PAPI_ful_ccy

Cycles with maximum instructions completed

PAPI_ful_icy

Cycles with maximum instruction issue

PAPI_fxu_idl

Cycles when units are idle

PAPI_hw_int

Hardware interrupts

PAPI_int_ins

Integer instructions

PAPI_tot_cyc

Total cycles

PAPI_tot_iis

Instructions issued

PAPI_tot_ins

Instructions completed

PAPI_vec_ins

VectorSIMD instructions

PAPI_l1_dca

Level 1 data cache accesses

PAPI_l1_dch

Level 1 data cache hits

PAPI_l1_dcm

Level 1 data cache misses

PAPI_l1_dcr

Level 1 data cache reads

PAPI_l1_dcw

Level 1 data cache writes

PAPI_l1_ica

Level 1 instruction cache accesses

PAPI_l1_ich

Level 1 instruction cache hits

PAPI_l1_icm

Level 1 instruction cache misses

PAPI_l1_icr

Level 1 instruction cache reads

PAPI_l1_icw

Level 1 instruction cache writes

PAPI_l1_ldm

Level 1 cache load misses

PAPI_l1_stm

Level 1 cache store misses

PAPI_l1_tca

Level 1 cache accesses

PAPI_l1_tch

Level 1 cache hits

PAPI_l1_tcm

Level 1 cache misses

PAPI_l1_tcr

Level 1 cache reads

PAPI_l1_tcw

Level 1 cache writes

PAPI_l2_dca

Level 2 data cache accesses

PAPI_l2_dch

Level 2 data cache hits

PAPI_l2_dcm

Level 2 data cache misses

PAPI_l2_dcr

Level 2 data cache reads

PAPI_l2_dcw

Level 2 data cache writes

PAPI_l2_ica

Level 2 instruction cache accesses

PAPI_l2_ich

Level 2 instruction cache hits

PAPI_l2_icm

Level 2 instruction cache misses

PAPI_l2_icr

Level 2 instruction cache reads

PAPI_l2_icw

Level 2 instruction cache writes

PAPI_l2_ldm

Level 2 cache load misses

PAPI_l2_stm

Level 2 cache store misses

PAPI_l2_tca

Level 2 cache accesses

PAPI_l2_tch

Level 2 cache hits

PAPI_l2_tcm

Level 2 cache misses

PAPI_l2_tcr

Level 2 cache reads

PAPI_l2_tcw

Level 2 cache writes

PAPI_l3_dca

Level 3 data cache accesses

PAPI_l3_dch

Level 3 data cache hits

PAPI_l3_dcm

Level 3 data cache misses

PAPI_l3_dcr

Level 3 data cache reads

PAPI_l3_dcw

Level 3 data cache writes

PAPI_l3_ica

Level 3 instruction cache accesses

PAPI_l3_ich

Level 3 instruction cache hits

PAPI_l3_icm

Level 3 instruction cache misses

PAPI_l3_icr

Level 3 instruction cache reads

PAPI_l3_icw

Level 3 instruction cache writes

PAPI_l3_ldm

Level 3 cache load misses

PAPI_l3_stm

Level 3 cache store misses

PAPI_l3_tca

Level 3 cache accesses

PAPI_l3_tch

Level 3 cache hits

PAPI_l3_tcm

Level 3 cache misses

PAPI_l3_tcr

Level 3 cache reads

PAPI_l3_tcw

Level 3 cache writes

PAPI_ld_ins

Load Instructions

PAPI_lst_ins

Loadstore Instructions

PAPI_lsu_idl

Cycles load store units are idle

PAPI_mem_rcy

Cycles stalled waiting for memory reads

PAPI_mem_scy

Cycles stalled waiting for memory accesses

PAPI_mem_wcy

Cycles stalled waiting for memory writes

PAPI_prf_dm

Data prefetch cache misses

PAPI_res_stl

Cycles stalled on any resource

PAPI_sr_ins

Store Instructions

PAPI_stl_ccy

Cycles with no instructions completed

PAPI_syc_ins

Synchronization instructions completed

PAPI_tlb_dm

Data TLB misses

PAPI_tlb_im

Instruction TLB misses

PAPI_tlb_sd

TLB shootdowns

PAPI_tlb_tl

Total TLB misses

The tables below define mappings of generic events to platform events and
any associated attribute for all supported platforms.

Intel Core2 Processors

Generic Event

Event Code/Unit Mask

Platform Event

PAPI_tot_cyc

0x3c/0x00

cpu_clk_unhalted.thread_p/core

PAPI_tot_ins

0xc0/0x00

inst_retired.any_p

PAPI_br_ins

0xc4/0x0c

br_inst_retired.taken

PAPI_br_msp

0xc5/0x00

br_inst_retired.mispred

PAPI_br_ntk

0xc4/0x03

br_inst_retired.pred_not_taken |
pred_taken

PAPI_br_prc

0xc4/0x05

br_inst_retired.pred_not_taken | pred_taken

PAPI_hw_int

0xc8/0x00

hw_int_rvc

PAPI_tot_iis

0xaa/0x01

macro_insts.decoded

PAPI_l1_dca

0x43/0x01

l1d_all_ref

PAPI_l1_icm

0x81/0x00

l1i_misses

PAPI_l1_icr

0x80/0x00

l1i_reads

PAPI_l1_tcw

0x41/0x0f

l1d_cache_st.mesi

PAPI_l2_stm

0x2a/0x41

l2_st.self.i_state

PAPI_l2_tca

0x2e/0x4f

l2_rqsts.self.demand.mesi

PAPI_l2_tch

0x2e/0x4e

l2_rqsts.mes

PAPI_l2_tcm

0x2e/0x41

l2_rqsts.self.demand.i_state

PAPI_l2_tcw

0x2a/0x4f

l2_st.self.mesi

PAPI_ld_ins

0xc0/0x01

inst_retired.loads

PAPI_lst_ins

0xc0/0x03

inst_retired.loads | stores

PAPI_sr_ins

0xc0/0x02

inst_retired.stores

PAPI_tlb_dm

0x08/0x01

dtlb_misses.any

PAPI_tlb_im

0x82/0x12

itlb.small_miss | large_miss

PAPI_tlb_tl

0x0c/0x03

page_walks

PAPI_l1_dcm

0xcb/0x01

mem_load_retired.l1d_miss

Fixed-function counters do not require Event Code and Unit Mask. The generic
event to fixed-function counter event mappings available are: