SAN JOSE, CA –(Marketwired – July 22, 2016) – BaySand, the leader in application configurable ASICs, announces the availability of the ASIC UltraShuttle-65, first of its class silicon MPW program that will support multiple designs customizable by 4 metal layers. With the support of a proven design flow and methodology, the ASIC UltraShuttle-65 MPW delivers high quality verified and fully tested ASICs. The methodology is based on BaySand’s standard cell library, including logic cells, IOs, Memories and IP blocks, which are fully characterized and silicon proven, combined with BaySand’s RTL signoff design methodology that includes Design for Testability (DFT), Automatic Test Pattern Generation (ATPG), full scan, JTAG, BIST and physical implementation. BaySand is committed to deliver fully tested and verified engineering samples.

“We are excited to introduce this innovative program that will provide access to deep submicron affordable and risk free ASIC,” said Salah Werfelli, BaySand’s president and CEO. “The ASIC UltraShuttle-65 methodology delivers high quality production ready devices that shorten the Time to Market (TTM) significantly and will be changing the market dynamics.”

Compared to the traditional shuttle offered by foundries today, BaySand will customizing the logic and IOs with 4 metal layers while the bottom layers are pre-defined. BaySand will be providing the following advantages compared to traditional shuttle services:

BaySand ASIC UltraShuttle-65

Traditional foundry shuttle service

RTL hand off and sign off

GDS hand off

Customer does not need special tools, licenses, or EDA tools expertise

EDA tools and EDA tools expertise required

BaySand ASIC proven methodology

Customer own methodology

Available IP: PLL, Memory, IOs and logic cells

Basic cell library

Production ready tape out

NA

DFT, ATPG and BIST included

NA

Deliver fully tested packaged parts

Deliver none tested dies

Schedule 6-8 weeks from tape out

Schedule about 9-12 weeks from tape out

High volume support

NA

The ASIC UltraShuttle-65 can also be used for FPGA to ASIC conversion and by that reducing the risk and shortening the TTM. The new program which will enable system designers to have a full ASIC implementation at low NRE cost rather than having to ship a low performance, high power implementation which cost up to 10 times higher.

Orders for the October 2016 UltraShuttle-65 can be placed today. The Shuttle is for the FG65L-5 device, which is a 65nm technology up to 600,000 usable gates, up to 900kbit of memory, 4 PLLs/DCMs with maximum of 242 user IOs. The shuttle deliver is planned for December 2017. The NRE cost, which include 100 fully tested units, is $70k, where it will cost $50k for the first 100 customers who sign up and make the commitment until the end of August. For more shuttle information, or to reserve your spot contact us at info@baysand.com.