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About Michael J. Miller

Miller, who was editor-in-chief of PC Magazine from 1991 to 2005, authors this blog for PC Magazine to share his thoughts on PC-related products. No investment advice is offered in this blog. All duties are disclaimed. Miller works separately for a private investment firm which may at any time invest in companies whose products are discussed in this blog, and no disclosure of securities transactions will be made.

IDF: 14nm Production on Track for Late 2013; Paths to 10nm and Below

There was one thing missing from the Intel Developer Forum this week: an executive holding up a wafer of 14nm SRAM and crowing about how the company is well on the way to the next big advancement in process technology. After all, it was three years ago that the company held up its first 22nm SRAM wafer (albeit without any information on what turned out to be the Tri-Gate or FinFet transistors). But Intel Senior Fellow Mark Bohr gave an update on the company's technology process. He said that the 14nm process is in full development and on track for "production readiness" at the end of next year.

Bohr said the company is currently manufacturing 22nm chips in three factories: D1D in Oregon, Fab 32 in Arizona, and Fab 32 in Israel. D1C in Oregon and Fab 12 in Arizona are on track to start 22nm production by the end of the year. One interesting thing he mentioned is that the company has approximately the same defect density at all of its fabs thanks to its "copy exactly" methodology.

All of the 22nm production to date has been Intel's CPU technology, but the company is prepping a variation on the process for its SoCs designs, presumably including the 22nd Atom SoC mobile architecture known as Silvermont, promised for next year. Many things are the same in the CPU and SoC designs, including the Tri-Gate transistors, which Bohr said work well on analog devices despite skepticism from some in the industry.

Among the big differences with the SoC process is that it needs to focus on low-leakage transistors for better battery life; support dense upper-level interconnects; and support high-voltage connections to legacy I/O devices at 1.2, 1.8, and 3.3 Volts. Bohr explained that Intel is able to do this through thicker oxide layers within the transistor. He noted that in practice, different circuits on the same die may use different transistors, combining high-voltage and low-voltage transistors (with thick and standard oxide layers).

Bohr said the company is still working on new process technologies on a two-year cadence, using a components research team to identify promising new technology, as well as development and manufacturing teams. As he's done before, he shared a slide that listed many of the items in research, but cautioned against reading too much into it, saying these are just a sample of research directions.

When asked about extreme ultraviolet (EUV) lithography, which the industry has been awaiting for many years, he said it is unlikely to be ready for Intel's 10nm production. He would like to have EUV then, but can't bet on it. He knows he has an immersion lithography solution that works at 10nm, using multiple layers of patterning. Still, this might be ready for 7nm production for Intel, which seems to be around the same time as Intel is hoping to move to 450mm wafers. EUV is very important to Intel's future, which is why the company recently invested in lithography maker ASML.

Where will this end? In another presentation, Bohr said classical silicon chip scaling hit its physical limits ten year ago, but the industry has always found ways around that. Thirty years ago, people were forecasting that chip scaling would end at 1 micron, but we've gone well below that. He said he can see a clear path for scaling to continue for at least the next ten years, through the 10, 7, and 5nm generations.

He noted that over time, the cost per wafer has gone up, but as transistor density continues to double following Moore's Law, the cost per transistor continues to go down each generation at a steady trend.

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