@chipmonk0: yes you covered a lot more. A current thinking was 2.5 D (which is really 2D w/TSV interposer) can avoid the thermals initially. But even this may not work with SOI chips, though that's another story entirely.

Several thermal solutions using very different aproaches are under development / being implemented at Micron and IBM / 3M. The real barrier is very involved process, low yield & high cost. Simplifications / modifications to the current industry process flow along the lines of my original post are sorely needed.

FYI it is not possible to bond ( / "weld" ) one Tungsten filled via directly to another in the next die stacked on top. At least not at any acceptable temperature anyway. So another layer of metal has to be deposited first to cap the W vias. Then these cap layers are CMPed, and whats really great, instead of using traditional metallurgical bonding that require high temperature ( 250 C ) and pressure, are bonded at quite low temperatures in which electrons are actually shared between atoms across the interface. Co-valent bonds develop and Van der Waals forces contribute to bond strength. There are a lot of tricks in the CMP step but its Good Science overall and reduces residual stress in the stack !

As to your "wield" getting misinterpreted by another poster as "weld", in this case two wrongs ( his typo & my responding to his post ) certainly made one right. Because as explained above "weld" is relevant in the case of die stacking.

@Chipmonk0: I should have put "Tungsten wielding" in quotes -was meant to be a pun on Peter's comment! And there was a typo! Tezzaron does use Tungsten TSV's in the "FaStack Stacking Technology." Tungsten acts as a good stress-relieving conduit for thermo-mechanical forces.

@Peter, I think you can fearlessly say the word Tezzaron for Tungsten welding expertise! But in all fairness, we need to give small companies credit for taking the risk to advance 3D technologies that were hitherto the domains of big ones like Intel, Micron & IBM etc.