Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS) is refer- enced to the crossings of CK and CK#.

72

CKE0

Input

Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers, and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all device banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any device bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied and until CKE is first brought HIGH. After CKE is brought HIGH, it becomes an SSTL_2 input only.

95

S0#

Input

Chip Select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code.

88, 91

BA0, BA1

Input

Bank Address: BA0 and BA1 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied.

73 (128MB, 256MB), 75, 77,

A0–A11

Input

Address Inputs: A0-A11/A12 provide the row address for

81, 83, 85, 87, 74, 76, 78, 82,

(64MB)

ACTIVE commands, and the column address and auto

84, 86

A0–A12

precharge bit (A10) for READ/WRITE commands, to select

(128MB, 256MB)

one location out of the memory array in the respective

device bank. A10 sampled during a PRECHARGE command

determines whether the PRECHARGE applies to one device

bank (A10 LOW, device bank selected by BA0, BA1) or all

device banks (A10 HIGH). The address inputs also provide the

op-code during a MODE REGISTER SET command. BA0 and

BA1 define which mode register (mode register or extended

mode register) is loaded during the LOAD MODE REGISTER

command.

12, 26, 48, 62, 108, 122, 144,
158

DM0–DM7

Input

Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins.

1, 2

VREF

Input

SSTL_2 reference voltage.

167

SDA

Input/ Output

Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presence- detect portion of the module.

169

SCL

Input

Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module.

168, 170, 172

SA0–SA2

Input

Presence-Detect Address Inputs: These pins are used to configure the presence-detect device.