SystemVerilog for ASIC and FPGA Design

System-level languages like SystemVerilog are replacing traditional Verilog as the industry standard. Far more than Verilog with a ++ operator, SystemVerilog describes complex logic and bus fabric using concise, yet high-level, constructs. This course prepares hardware engineers, ASIC and FPGA designers, and other engineering staff to use the syntax of this hardware description language to design, debug, and synthesize digital logic for ASICs, FPGAs, and IP cores.

The course introduces SystemVerilog's basic design building blocks and language constructs, including synthesizable data types and operators, structures and unions, 2-D arrays and loops, and the bus interface unit. Design examples progress in complexity from an easy-to-grasp split counter to a video acquisition subsystem. Students will write their own code, and then synthesize it into 90-nm digital logic for ASICs and FPGAs in the lab. All synthesizable aspects of the IEEE 1800 syntax, especially the versatile bus interface unit, are covered. Eight step-by-step labs highlight proven coding techniques for low-power and high-speed design. The focus of this course is how to write efficient code for logic synthesis. Both ASIC and FPGA tools are provided in our lab but they are not the focus of the course.