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AR# 15388

HyperLynx - Frequently Asked Questions

Description

Keywords: HyperLynx, Hyper, Lynx, Linx, questions, FAQ, FAQs

This Answer Record presents frequently asked questions for the Innoveda HyperLynx solution.

Solution

Q: What is Signal Integrity (SI)?A: Signal Integrity (SI) describes the environment in which the signals must exist. It covers the various techniques and design issues that ensure signals are undistorted and do not cause problems for themselves, to other components in the system, or to other systems nearby. As system performance increases, electrical effects that could previously be ignored must now be accounted for. Having control over crosstalk, ground bounce, ringing, noise margins, impedance matching, and decoupling is now critical to a successful design.

Q: What is the added value of using SI analysis tools?A: The value of these tools is that they flag signal integrity, electromagnetic compliance (EMC), or crosstalk problems very early in the product development flow, which saves time and money.

Q: What is HyperLynx?A: Since the HyperLynx acquisition, Innoveda's signal integrity analysis tool is HyperSuite. HyperSuite is made up of two components: - LineSim for pre-layout analysis- BoardSim for post-layout analysis

Q: What is LineSim?A: LineSim is part of the HyperSuite signal integrity tool suite and is a pre-layout analysis tool. The current version (6.0) is available for PC and UNIX (Solaris). LineSim comes with three options: - Crosstalk analysis (included in the Xilinx version) - EMI/EMC analysis (included in the Xilinx version) - SPICE writer: writes SPICE compatible circuit for the PCB topology under test

Q: What can I do with LineSim?A: LineSim allows for transient and spectrum analysis that will help define board stackup and material properties, as well as topologies, trace characteristics, terminations, and connectors to get a reliable estimates of SI effects like reflections, propagation delays, crosstalk, EMC, etc.

Q: What are LineSim limitations?A: Limited integration with board layout tools (topologies can be imported from most board layout tools, but parameters extracted from simulation results cannot be exported back to the board layout tool). No eye diagram measurements. No support for SPICE simulations. The IBIS standard (read-in by LineSim) does not allow for ground bounce, power supply droop, or simultaneous switching output (SSO) noise simulations. For other SI phenomenon, IBIS models may generally be used for simulations up to the GHz range (simplification slightly arbitrary).

Q: What models are supported by LineSim?A: LineSim supports IBIS models, but does not support SPICE models.

Q: Can I get models for all Xilinx devices?A: Xilinx provides IBIS models for all Select I/O and Select I/O-Ultra standards. Xilinx can provide (upon SPICE Model License Agreement) HSPICE models for all Select I/O, Select I/O-Ultra, and Rocket I/Os.

Q: What is the LineSim flow?A: During the board pre-layout phase or to verify critical net SI after board layout:

Q: Can ISE generate IBIS models?A: Yes. The tool is called IBISWriter: just click "Run" on the "Generate IBIS Model" item of the Project Navigator process view. If designers do not need design-specific pinout models for simulations, they may download the latest models from the web.

Q: What do I need to know about IBISWriter?A: A design-specific file is generated wherein all input/output pins are associated with an IBIS model. For now, however, IBIS models are asynchronously released with ISE service packs, so you may want to check for the latest IBIS models at:http://www.xilinx.com/support/mysupport.htm

Q: How do I get the latest IBIS models? To obtain Xilinx IBIS models, go to:http://www.xilinx.com/support/mysupport.htm (updates are currently asynchronous to software releases). Other IBIS models are available from IC and connector vendor respective web sites.

Q: Why is Xilinx only providing HSPICE models for Rocket I/O?A: First, IBIS models and simulators were not meant for 1+GHz simulations and therefore do not allow for reliable Rocket I/O data rate simulations. Second, the various SPICE simulators are not fully compatible with each other. Therefore, it does not make sense for Xilinx to create and support the different SPICE model flavors. Rocket I/O HSPICE models can be simulated using only Avant! HSPICE.

Q: What is a SPICE model?A: A SPICE model is an IC circuit description at the transistor level. It contains detailed information about the circuit and process parameters that are usually regarded as proprietary information by the IC vendor; therefore, vendors are very reluctant to distribute SPICE models. Xilinx can provide encrypted HSPICE models for board-level simulations upon the acceptance of a SPICE Model License Agreement.

Q: What is an IBIS model?A: IBIS (I/O Buffer Information Specification) is a standard for electronic behavioral specifications of integrated circuit input/output analog characteristics. The core of an IBIS model is a table of current versus voltage and I/O switching timing information. Xilinx IBIS models contain tables for typical, slow/MIN (weak transistors, high temperature, low voltage) and fast/MAX (strong transistors, low temperature, high voltage) process corners. IBIS models are derived from SPICE simulation results and/or lab measurements. The benefit for IC vendors is that no information about circuit and process details are revealed.

Q: What are the main differences between HSPICE and IBIS?A: The user benefits of IBIS over HSPICE models are faster simulations, elimination of non-convergence issues, ease of use, and availability. Accuracy is only slightly decreased. The IBIS standard does not allow for ground bounce, power supply droop, and simultaneous switching output (SSO) noise simulations. For other SI phenomenon, IBIS models may generally be used for simulations up to the GHz range (simplification slightly arbitrary).