clock tree synthesis & clock mesh synthesis

Started by gops on 20 Nov 2008 12:17 AM. Topic has 2 replies and 5177 views.
Last post on 20 Nov 2008 8:30 PM by gops.

what is the difference between clock tree synthesis and clock mesh synthesis? How will i select one for the design ( i think only one of these is necessary for a single design). Please give me some guidelines regarding these. Thanks gops

2 Replies

This is a valid question. Clock Tree Synthesis is a long-standing technique widely available in place and route tools whereby the tool is tasked with automatically matching the arrival time of the clock signal at each target in the clock network by building a tree of buffers and inverters distributed across the design. I would estimate that 90+% of designs implemented in SoC-Encounter use this approach.

Clock Mesh is an approach to consider when very tight control of arrival times of clock signals is mandatory. There are a few different approaches that fall into the Clock Mesh category, but essentially we seek to build a mesh-like strucutre across the chip with very regular drivers in the clock network. This regularity leads to very similar arrival times at each target (ie "low skew"). The tradeoffs associated with Clock Mesh are typically:

Hi Bob;Thanks for the reply.I think it will be helpful if you give some more idea about the clock mesh about how the tight control of arrival times is met better than clock tree and also about how clock buffers are inserted in the mesh such things. Also it will be better understood if you can give a snapshot of the clock mesh .