A friend of mine phoned me its appreciation for the performance of the unit and the possibility to use it as high performance receiver. Other than the powerful Spike application Signal Hound provides the ExtIO_BB60.dll for use with HDSDR.

I decided to dig into the BB60c API manual and ExtIO_BB60.dll source code looking for higher sampling rate. A real time signal demodulation in a wider I/Q bandwidth.My ExtIO_BB60c.dll version runs up to 40Msps sampling rate and shows 27 MHz bandwidth. I named it ExtIO_BB60c.dll. It allows the selection of sampling rate, up to 40Msps.

Input sampling rate selection under Bandwidth button

HDSDR + ExtIO_BB60c running in real time at 40Msps.

HDSDR (version 275 or 270) can record the RF spectrum as a filename.wav.The recording at 10Msps is fine. Nevertheless at 20Msps or 40Msps the recording shows some discontinuities every second.Hereafter a 10Msps playback loop video example.

I used a 31 stages long LFSR with 2 taps: [31, 28] in Fibonacci configuration. The generator output bits are computed in 8 bit burst and sent to the SPI serializer at a clock rate that can be selected between 2, 1, 0.5, 0.25, 0.125 Mbps. Some clock phase skewing is caused by the USB routine interrupts but it seems not affecting the resulting randomness. In the following the clock was set at 1 MHz.

31 bit LFSR fits into a 32 bit integer and output period is long enough to easily cover the latency delay in between the tre RTL-SDR USB receivers.

The uP output signal is as follows:

The signal frequency shape (sinx/x)^2 depends on the rectangular bit shape with clk 1uS that has a spectrum with minimums at 1MHz division.

The measure shown in 3radio project - part 4 are repeated with different receiver frequency. It computes the cross correlation between sequences of 100000 samples.

Center frequency 69 MHz sampling 2.048 Msps

The pseudo randomness of the sequence improves the cross correlation results versus the previous test. Side lobes are low and the time latency between different RTL-SDR is within the 100000 bit analysis span used.

Center frequency 101.800 MHz sampling 2.048 Msps

Center frequency 144.000 MHz sampling 2.048 Msps

This measure shows the presence of a constant pattern that generates the triangular shape on the image on the left while on the right one it causes the minimum value offset.

I think the reason can be the presence of the 28.800 MHz x 5 = 144 MHz harmonic spur that it's synchronous and quite strong.

The following measure shows the results at 142000 MHz where there are lower spurs.

Center frequency 142.000 MHz sampling 2.048 Msps

Center frequency 500.000 MHz sampling 2.048 Msps

The correlation measure at 500 MHz shows that this frequency without a pulse shaping is the limit of the usable range and the peak value is 40 dB lower (100 times) than in VHF tests.

Possibly the use of a shape pulse circuit flattens the spectrum and increases the energy at higher frequency.

Here some test results to evaluate the hardware performance and the use of a pseudo random binary sequence as reference to cross correlate the streams received from the 3radio, a radio composed by multiple RTL-SDR hardware.

The 3radio has been tuned to 69 MHz center frequency and a sampling rate of 2048000 Hz has been chosen. 3 streams of 100000 IQ sample have been recorded using librtlsdr . The real time length is half a second.

The same signal was routed via separated switching diodes to all the RTL-SDR receivers.

Sequences of about 3 ms or 6000 bits have been generated. A delay of some hundred of ms separates the different bursts. The reason was to be able to recognize some sync reference just looking to signals in time.

The previous figure shows the IQ streams in time, a chunk of about 6200 samples at 2048000 sampling is selected.

A script in python was written to compute the cross correlation. Here after the script:

# The raw, captured IQ data is 8 bit unsigned data.# Each I and Q value varies from 0 to 255.# To get from the unsigned (0 to 255) range we need to subtract 127.5# from each I and Q value, which results in a new range from -127.5 to +127.5.# The complex data is y = I + jQ and we subtract 127.5 +127.5j

The results look quite good nevertheless the reference signal was far from perfect as you can notice from the cross correlation side lobes.

The time differences of the max positions define the time skewing between the streams. This time depends on the USB latency, on the different starting time of the software application trigger. I hope that the hardware clock skewing is solved with the synchronization.

TI ClockPro(TM) application is used to made the configuration file of CDCE925 while an I2C programmer (an Arduino board) is required to program it.

Other than the 12 MHz and 16 MHz clocks used for the HUB FE1.1s IC and the AT90USB162 uP a 10 MHz synchronous clock is generated for comparison to lab frequency standard.

The 28.8 MHz buffered output goes to a two xtal filter made with the 28.8 MHz xtals de-soldered from the RTL-SDR. This filter is used to obtain the sinusoidal output signal that synchronizes the RTL-SDR dongles.

The FFT analysis shows a 40 dB attenuation of high harmonics.

The CDCE925 has been mounted with dead-bug style and the cable used for the rtl-sdr 28.8MHz is RG174. The cables have the same length, while for 12 MHz and 16 MHz a twisted wire pair has been used.

The 28.8 MHz TCXO and the 28.8 MHz xtal filter are on the top while the cdce925 is on the bottom side of the PCB. The black cables feed the clock to the RTL-SDR dongles. The grey twin wires on the left are the 12 and 16 MHz clocks.

The software uses rtl-sdr library. It runs 3 instances using synchronous transfer. Each stream is recorded in a file as raw bytes. A first graphical analysis and comparison is made using Audacity application.

The application programs all the units to the same frequency. The central frequency is 60.0 MHz because the energy of Pseudo Random Noise Generator (PRNG) sequence is higher at low frequency. The 3radio PRNG prototype has not jet a pulse sharpening circuit.

The PRNG has been programmed to generate at pseudo-random time intervals a sequence of 64 bits at 1Mbps with a good auto-correlation peak. Nevertheless the first measure has been made without any correlation processing, just looking at signal in time with Audacity app.

The picture shows the records made with a sampling rate of 2048 ksps and the gain set to 10dB. All the units are feed by the same PRNG signal. The signals are down-converted and recorded as complex base-band signal I&Q, here shown as stereo audio signals. The time scale is in 10 ms units as Audacity does not accept 2048 kHz sampling and 20.48 kHz is selected instead. The time span is about 500 ms.

The 3 streams are correlated and shown different latency time. I think latency is due to the different recording starting time and serialization over the USB link other than the pll phasing of RTL2832 and R820T.

Lucky the sampling synchronization is kept constant during the measure. So an head synchronization could be maintained for a long time.

Manually phasing the signals and zooming into the 64 bit sequence shows the strong correlation in between the 3 I&Q streams.

A phase rotation in the signals is expected as the PRNG signal is generated by a microprocessor running at 16.0 MHz with a xtal not synchronous to the 28.8MHz clock.

Note: an hardware improvement could be made synchronizing the 16.0 MHz clock of PRNG and the 12.0 MHz clock of HUB with the advantage of decreasing the eterodine signals.

This pages describe my own project of a SDR coherent receiver named 3radio

The first goal is a setup for coherence measure without sophisticate instruments.

Block diagram rev 1.0

It is a compact device that uses a single USB cable to acquire 3 SDR sample streams.

Thermal cooling is important to reach reliable performance.

The unit is housed into an aluminum box with the rtl-sdr screwed to the box wall.

Temperature range from 25°C to 85°C

The original MCX connector, the IR receiver and the led have been removed. Please keep the solder dots as flat as possible on the solder side.

Solder side

The rtl-sdr PCB has a 2.0 mm hole that can be used to fix the unit near the led position. A second 2.0 mm diameter hole is drilled in the position indicated in the picture.Two 2.0 mm screws will rest the board against the aluminum wall. An electrical insulated thermal pad is placed in between the board and the aluminum.90° SMA Female connectors has been used in the prototype.

Preliminary test wiring with a xtal oscillator feeding the other units.

As the TCXO 28.8MHz is not jet arrived in the mail, one of the original xtal oscillators has been used to drive the other two ones using a 14 pF capacitors (2*6.8pF in parallel).

The USB connectors has been replaced by wires to place the boards against the aluminum near the HUB PCB.

The red wire that goes to the antenna diode is carrying the pseudo random noise PRNG signal to the antenna inputs via a BAV99 diode gate.

The HUB is a FE1.1s chip while the PRNG is a AT90USB162 wired to the 4th port of the HUB.

The plan is to use the PRNG sequence to synchronize the received streams during an initial calibration phase or every time the USB samples streams are stopped.

At the beginning the generator stream is used to measure some coherence figure...