WHAT:Cadence is demonstrating design and verification IP that enable the successful integration of flash memory technology into ASICs and SOCs. Combining technology from both Cadence and the Denali acquisition, the company’s comprehensive offering enables the rapid deployment of systems for storage, enterprise and networking applications.

Session 307: “PCIe Storage 2.” Ashwin Matta, engineering director, SoC Realization, at Cadence, will present on an implementation of the PCIe Gen3 specification, with features targeted at maximizing flexibility and performance of data access within a storage subsystem.

WHERE:The Flash Memory Summit is being held at the Santa Clara Convention Center in Santa Clara, CA. Demonstrations will take place in the Cadence Booth #206. Sessions will take place in the convention center conference rooms.

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.