This patch updates the PMCs for AMD Zen1 core based processors (Family17h; Models 0 through 2F) to be in accordance with PMCs asdocumented in the latest versions of the AMD Processor ProgrammingReference [1], [2] and [3]. Note that some events, such as FPU pipeassignment are missing in [1], and therefore [3] is included for fullcoverage of events.

---Changes in v2: - Correct the UMasks for fpu_pipe_assignment.dual* by left shifting all by 4 bits. - Correct UMask for ls_mab_alloc.loads - add bp_dyn_ind_pred (PMC0x08E) - add bp_de_redirect (PMC0x091)Changes in v3: - Correct the pipe numbers for fpu_pipe_assignment counters - Correct ls_mab_alloc.* public descriptionsChanges in v4: - PMC 0x46 add missing subcounters for types 0 and 1 of tablewalker allocation - PMC 0x60 and 0x61: add missing detail on brief descriptions - change descriptions of many of the events to bring them in-line with improvements made in patch 2/3. These were for counters that did not change between zen1 to zen2. Patch reviews for zen2 lead these descriptions to be changed and improved, and many of these have been carried here in this version of patch 3.