TECHNICAL LIBRARY

Simulation of PMOS Device Characterization

ATLAS is typically used to generate electrical
characteristics from a device generated in process simulation. In
CMOS type applications, users typically require electrical characteristics
that are suitable for subsequent SPICE model extraction.

In this example a 0.35 micron channel length LDD
- PMOS device has been created in ATHENA as shown in Figure
1. For characterization of this type of device an Id / Vd family
at several Vg are required as well as an Id / Vg family at several
Vb.

Figure 1. PMOS device
structure, showing the doping profiles.

Typically, mesh structures generated during process
simulation are not adequate for device simulation as their respective
requirements are quite different (for example process simulation
grids must accurately portray the doping profiles, and their change
with subsequent thermal cycles, where as device simulation requires
areas of high field and current flow to be more densely meshed).
It is possible to use DEVEDIT(a graphical and batch mode meshing
tool) to automatically remesh the structure between process and
device simulation.

Figure 2 shows
the Id / Vd family and Figure 3 shows the Id / Vg family. Additionally,
once the device has been characterized in terms of I/V curves, it
is possible to use a parameter extraction tool, such as UTMOST to
produce a SPICE model (for example BSIM3 or PHILIPS9) from this
data. This makes the data produced by process and device simulation
much more valuable, as a designer can now evaluate and optimize
the overall circuit performance of a design based upon the simulated
device. This also gives advanced information about new processes
to the circuit and system level engineers.

Figure 2. Id/Vd family of curves
at several gate biases.

Figure 3. Id/Vg family
of curves at several back biases.

Using ATLAS it is also possible to carry out any
type of electrical test on the simulated device, including transient
and AC analysis. Additionally, breakdown calculations (including
snapback analysis) are also possible for this type of device.

This simulation has a reasonably dense mesh as
illustrated in Figure 4. Typically it
can take around 30 - 40 minutes to produce a set of characteristics
for this type of device. Using the parallel version of ATLAS, this
time can be reduced to a few minutes as illustrated in Figure
5. This can be very useful when performing device optimization
or tuning of simulation as multiple sets of results can be generated
very quickly.

Figure 4. Mesh structure used
in these simulations.

Figure 5. Execution time
improvement with
number of processors for PMOS characterization.