Application Defined Processors

By rebuilding a system's logic on the fly, this project can make one FPGA do the work of tens or hundreds of ordinary processors.

Programming Model for Reconfigurable Computing

Traditionally, the programming model for RC has been
one of hardware design. Given that the tools required
for the underlying FPGA technology of RC are all logic
design tools from the Electronic Design Automation
industry, there really has not been a programming
environment recognizable to a software developer.
The tools have supported Hardware Definition Languages
(HDLs) such as Verilog, VHDL and Schematic Capture.

With the introduction of system-on-a-chip (SOC)
technology and the complexity associated with hardware
definition of such complexity, high-level languages
have begun to be available. Java and C-like languages
are becoming more common for use in programming
RC chips. This is a significant step forward but
continues to require quite a leap by application
programmers.

The SRC programming model is the traditional software
development model where C and Fortran are used to
program the MAP processor, and any language capable
of linking with the runtime libraries (written in C)
can be compiled and run on the microprocessor portion
of the system.

The SRC Carte programming environment was created with
the design assumption that application programmers
would be writing and porting applications to the
RC platform. Therefore, the standard development
strategies of design, code in high-level languages
(HLLs), compile, debug via standard debugger,
edit code, recompile and so on, until correct,
are used to develop for the SRC-6 system. Only when
the application runs correctly in a microprocessor
environment is the application recompiled and
targeted for the DEL processor, MAP.

Compiling to hardware in an RC system requires
two compilation steps that are quite foreign to
programming for an instruction processor. The output
of the HLL compiler must be a hardware definition
language. In Carte, the output either is Verilog or
Electronic Design Interchange Format (EDIF). EDIF
files are the hardware definition object files that
define the circuits that will be implemented in the
RC chips. If Verilog is generated, then that HDL must
be synthesized to EDIF using a Verilog compiler such
as Synplify from Synplicity.

A final step, place and route, takes the collection
of EDIF files and creates the physical layout of
the circuits on the RC chip. The output files for
this process are a configuration bitstream, which
can be loaded into an FPGA to create the hardware
representation of the algorithm being programming
into the RC processor.

The Carte programming environment performs the
compilation from C or Fortran to bitstream for the
FPGA without programmer involvement. It further
compiles the codes targeted to microprocessors into
objects modules. The final step for Carte is the
creation of a unified executable that incorporates
the microprocessor object modules, the MAP bitstreams,
and all of the required runtime libraries into a
single Linux executable file.
Figures 6 and 7 present the Carte compilation process.

Figure 6. Carte Programming Environment

Figure 7. Carte Compilation

Open-Source Hardware Opportunity

Linux has led the way and benefited greatly from
the Open Source movement where a large and dedicated
group of software developers has created, modified
and improved the Linux kernel and OS at a rate,
quality and level of innovation that could not
be matched by the work of a single commercial
organization. Reconfigurable computing has the
potential of enabling such innovation and technical
advances in hardware design. Much of this article
is spent explaining the concept of application
programmers writing code and using standard
programming methods to create application-specific
hardware without requiring knowledge of hardware
design. However, in RC the building blocks of the
generated hardware created by application programmers
is the functional unit. Functional units are basic
computational units such as adders, floating-point
multipliers or trigonometric functions. Functional
units also can be specialty high-performance units,
like triple DES functions, or nonstandard precision
arithmetic units, such as 24-bit IEEE floating-point
operators.

Functional units are created by logic designers.
RC compilers, such as SRC's Carte MAP compiler, are
capable of allowing customer-supplied functional
units to be added to the standard set of operations
supported by the compiler. When new and novel
functional units are made available to application
programmers, an even higher level of performance can
be achieved.

It is in the creation and sharing of innovative
hardware designs for functional units where an
Open Hardware movement could bring substantial
advances to computational science. The innovation
and productivity seen in the open-source arena could
be replicated as Open Hardware.

RC provides a vehicle for many more creative designers
to create new and novel hardware that can be used
by application developers. Through groups like
Opencores.org, functional unit design can be shared
and improved upon. The significant advances seen
in the computational sciences, due to open-source
software, easily could be seen through a movement
focused on open hardware as well.

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