TEMPERATURE MONITORING OF A LIGHT GUIDE IN AN ILLUMINATION APPARATUS - An illumination apparatus having a radiation source and a light guide coupled thereto. The temperature of the light guide is monitored along its complete length. If a threshold temperature is exceeded, a switching mechanism will be triggered. The switching mechanism switches off the radiation source or triggers a warning signal.

2011-11-24

20110286234

METHOD OF MANUFACTURING A LIGHT EMITTING DEVICE - A method of manufacturing a light emitting device includes separating a plurality of regions in a film with a thickness not greater than 0.5 millimeters to form a plurality of legs continuous with a body of film, folding the plurality of legs such that each leg terminates in a stack of bounding edges, disposing the stack of bounding edges proximate at least one light source such that light from the at least one light source propagates through the legs and the body by total internal reflection, and treating the film to form a plurality of light scattering features therein such that frustrated totally internally reflected light exits the light emitting device at a visible light emitting area and the light emitting area is at most barely visible when not illuminated by the at least one light source.

2011-11-24

20110286235

BACKLIGHT MODULE - A backlight module includes a back plate, a light guide plate, a heat insulation layer, a heat dissipation member, and a light source device. The back plate has a first surface, a second surface opposite to the first surface, and an opening passing through the back plate. The light guide plate is disposed on the first surface, the heat insulation layer is disposed on the second surface, and the heat dissipation member is disposed on the heat insulation layer. The light source device is connected to the heat dissipation member and protrudes from the first surface to face the light guide plate through the opening.

2011-11-24

20110286236

Light Source with Light Recovery Mechanism - A light source with a light recovery mechanism is disclosed. In one embodiment, the system comprises a light source placed within a mirrored enclosure. The light source is used to illuminate a light guide. All of the light entering the light N guide might not be utilized. Some of the light might get reflected back in the direction of the light source, or may travel to the other end of the light guide. The mirrored enclosure of the light source reflects this light back into the light guide. Thus the light source placed within a mirrored enclosure acts as a light source emitting light into a light guide and also redirects light coming out of the light guide back into the light guide.

2011-11-24

20110286237

SURFACE LIGHT SOURCE DEVICE - A light guide plate is formed of a light introducing part positioned to face a point light source for confining light and a light guide plate body having a thickness smaller than the thickness of an end of the light introducing part on a point light source side and causing the confined light to be output from a light exit surface to outside. The light introducing part has an inclined surface, and a directivity conversion pattern formed on the inclined surface. The directivity conversion pattern is configured by arranging V grooves in parallel to each other, each having a vertical angle of 120°, and each extends in a direction approximately perpendicular to a light incidence end face of the light guide plate. The length of the inclined surface in a inclination direction where part of light incident to the light introducing part enters the inclined surface at least twice.

2011-11-24

20110286238

SURFACE LIGHT SOURCE DEVICE - A light guide plate includes a light introducing portion which is positioned facing a point light source and which confines light, and a light guide plate body which is thinner than a maximum thickness of the light introducing portion and which causes a light exit means to emit the confined light outward. The light introducing portion has an inclined face which is inclined from a portion having the maximum thickness to a surface of the light guide plate body. The inclined face includes a directivity converting pattern for converting a directional characteristic of the light that has entered the light introducing portion. The directivity converting pattern's structure includes a plurality of V-shaped grooves. An inscribed circle of the directivity converting pattern passes through both ends of a light exit window of the point light source.

2011-11-24

20110286239

LIGHT MODULE - A light module includes a light guide plate, a light bar, and a first reflector. The light guide plate has a first edge surface, a second edge surface, and a top surface serving as a light-outgoing surface. The light bar is disposed on the first edge surface for providing an edge light source into the light guide plate. The light bar has a plurality of light-emitting devices. The first reflector is disposed on the second edge surface to reflect light back to a region above the light bar.

2011-11-24

20110286240

ILLUMINATING APPARATUS - An illuminating apparatus includes a plurality of light source units and a light guide plate. The light guide plate has a flat part and a protruding part, wherein the light source units provide a side light beam into the light guide plate at an edge surface, the side light beam is guided in the light guide plate and exits at the protruding part.

2011-11-24

20110286241

LIGHT SOURCE MODULE - A light source module including a back frame, a light guide plate (LGP), and at least one light emitting device is provided. The back frame has a baseboard. The LGP is disposed on the back frame, and has a first surface, a second surface opposite to the first surface, and a light incident surface, wherein the second surface faces toward the baseboard. The light emitting device is disposed beside the light incident surface. The light source module further includes a thermal insulating element, which is disposed between the baseboard and the second surface, and is located adjacent to the light incident surface.

2011-11-24

20110286242

LIGHT GUIDE PANEL, FRONT-LIGHT MODULE AND REFLECTIVE DISPLAY APPARATUS - A light guide panel (LGP) has a light incident surface for receiving light. The LGP is configured at a side of a display surface of a reflective display panel. Besides, the LGP includes a main body, a first film, and a plurality of circular light guide patterns. The first film is configured on one side surface of the main body away from the display surface. The circular light guide patterns are configured on the first film, so that the light transmitted in the LGP exits and substantially moves toward the display surface. Each of the circular light guide patterns has a center and a circumference. An included angle is between two lines that respectively connect the center to the circumference located at two sides of the center, and the included angle is 140°˜179°.

2011-11-24

20110286243

ISOLATED FEEDBACK SYSTEM FOR POWER CONVERTERS - An isolated feedback system for power converters includes an error amplifier for receiving an input voltage to output an error signal; a modulator circuit to modulate the error signal with a carrier signal; an acoustic transformer unit, one end of the acoustic transformer connected to the modulator circuit, where a frequency of the carrier signal is away from resonant frequencies of the acoustic transformer; and a demodulation circuit connected to the other end of the acoustic transformer and receiving the modulated signal.

2011-11-24

20110286244

ADJUSTABLE SPEED DRIVE LIFETIME IMPROVEMENT METHOD - The present techniques include methods and systems for operating an inverter to maintain a lifespan of the inverter. In some embodiments, the switching frequency and/or the output current of the inverter may be changed such that stress may be reduced on the inverter bond wires of the inverter. More specifically, embodiments involve calculating the aging parameters for certain operating conditions of the inverter and determining whether the operating conditions result in aging the inverter to a point which reduces the inverter lifespan below a desired lifespan. If the operating conditions reduce the inverter lifespan below the desired lifespan, the switching frequency may be reduced to a lower or minimum switching frequency of the inverter and/or the output current of the inverter may be reduced to a maximum output current at the minimum switching frequency.

2011-11-24

20110286245

DC/DC POWER CONVERTER HAVING ACTIVE SELF DRIVING SYNCHRONOUS RECTIFICATION - A DC/DC voltage converter includes a transformer having a primary side and a secondary side. Primary side circuitry is connected to the primary side and includes a first pair of switching transistors controlled responsive to first control signals from the primary side of the transformer and receiving an input voltage. Secondary side circuitry is connected to the secondary side and includes a second pair of switching transistors controlled responsive to second control signals from the secondary side of the transformer and providing an output voltage. Driver circuitry generates the second control signals responsive to drain and source voltages at each of the second pair of switching transistors and a first and second PWM control signals. Signal shaping circuitry provides the first and second PWM control signals responsive to a drain voltage of each of the second pair of switching transistors.

2011-11-24

20110286246

Electric power converter - An electric power converter facilitates performing soft switching in the two-way electric-power-conversion operation thereof, and reducing the manufacturing costs thereof and the losses caused therein, The electric power converter includes a first switching device; a second switching device; a first series circuit including capacitor, a diode, the primary winding of transformer, and a third switching device; a second series circuit including a capacitor, a fourth switching device, the primary winding of transformer, and a diode; a third series circuit including a diode and the secondary winding of transformer; and a voltage clamping element connected in parallel to the primary winding of transformer. The first series circuit is connected in parallel to the first switching device, and the second series circuit is connected in parallel to second switching device. The third series circuit is connected between the DC output terminals.

2011-11-24

20110286247

SENSING ARRANGEMENTS - A sensing arrangement and method a sense winding is used to provide a voltage which represents the voltage appearing across an in-circuit magnetic component. In a flyback phase, when the component is supplying the output, that voltage represents an output voltage and in a supply phase, the supply voltage. This arrangement provides a solution to the problem of the disparity in magnitude of sense winding output during the two phases by proving a pull-up resistor arranged to apply bias to the voltage measured, the pull-up being to a first level during the supply period and to a second value during the flyback period, the first and second levels being selected such that the voltage across the sense winding is scaled differently during the supply period and the flyback period. The invention is suitable for use in a transformer based flyback power converter in which the magnitude disparity problem may be exacerbated by a turns ratio.

2011-11-24

20110286248

Adaptive Control for Transition Between Multiple Modulation Modes in a Switching Power Converter - In a switching power converter, PWM mode and PFM mode are separated into two independent control sections with the control voltage range in each control section determined independently. Each of the PWM and PFM modulation modes cannot operate continuously beyond its boundaries, thereby forming a control gap between the two control sections within which no continuous operation is allowed. In order to supply a load condition within the control gap, the power supply operates at the two boundaries of the control gap. Transition between PWM and PFM modes occurs fast, with low output voltage ripple. No limitation needs to be imposed on the control voltage range in each of the PWM and PFM control sections, because the control parameters in the PWM and PFM control sections need not be matched to one another, due to separation of the PWM and PFM modes by the control gap.

2011-11-24

20110286249

METHOD AND DEVICE OF ELECTRICAL POWER - A power factor correction of three-phase boost-type conversion is disclosed. Embodiments comprising multi-leg autotransformers are disclosed, e.g. comprising 3-phase low-pass filtering impedances such as capacitors between an input of a converter and a midpoint of the output.

2011-11-24

20110286250

POWER ADAPTATION DEVICE AND POWER SUPPLY MANAGEMENT METHOD - A power adaptation device and a power supply management method thereof are provided. The power adaptation device includes a terminal seat, a detection structure, a detection unit, an electric power modulation unit, an electric power modulation unit, and a control unit. The power supply management method includes the following steps. A detection result of the detection structure is read by the detection unit to judge whether the power terminal is electrically connected to the electronic device. The detection unit notifies the control unit that the power terminal is not connected to the electronic device when judging that the power terminal is not connected to the electronic device. The control unit controls the electric power modulation unit to stop supplying power to the electric power modulation unit to reduce a total power consumption of the electric power modulation unit.

2011-11-24

20110286251

POWER SUPPLY DEVICE - A power supply device includes: a magneto generator with a rotor having a magnet; a torque supplying device supplying torque to the rotor; a rectifier circuit supplying electric power to a electrical load device by rectifying an output of the magneto generator; a short circuit electrically shorting an output end of the magneto generator; a voltage detection circuit detecting a terminal voltage of the electrical load device; and a control circuit controlling a voltage of the electrical load device to be a first set value by controlling the short circuit to switch ON (short operating mode) and OFF (rectification operating mode) according to the voltage detected by the voltage detection circuit and allowing the short circuit to operate while making a switching between the two operating modes according to a operating state relating to a rotation of the rotor of the magneto generator.

2011-11-24

20110286252

T-TYPE THREE-LEVEL INVERTER CIRCUIT - This invention relates to a T-type three-level inverter circuit. The circuit includes an absorption unit. In the absorption unit, a first terminal of the first resistor is connected to a positive bus terminal, and a second terminal of the first resistor is connected to a first terminal of the first capacitor and a negative electrode of the first diode; a second terminal of the first capacitor and an positive electrode of the first diode are respectively connected to an emitter and a collector of the first controllable switch tube; a first terminal of the second resistor is connected to a negative bus terminal, and a second terminal of the second resistor is connected to a positive electrode of a third diode; a negative electrode of the third diode is connected to both a first terminal of the second capacitor and a positive electrode of a second diode; and a second terminal of the second capacitor and a negative electrode of the second diode are respectively connected to a collector and a emitter of the second controllable switch tube. As the T-type three-level inverter circuit according to the invention is implemented, a voltage stress on the bidirectional switch tube is effectively reduced due to strong absorption capacity of the absorption unit, and thus the bidirectional switch tube can adopt a tube having a relatively low breakdown voltage value. Moreover, the absorption unit has a low cost and a small loss.

2011-11-24

20110286253

Three-phase inverter circuit and method for operating a three-phase inverter circuit - A three-phase inverter circuit includes an inverter comprising a plurality of controllable power switches, and an electronic control device adapted to control the power switches. The control device in the event of a measured voltage drop on one phase is adapted to supply a reactive current on the phase with voltage drop and to supply and/or draw an active current on at least one phase without voltage drop.

2011-11-24

20110286254

Semiconductor Devices Having a Three-Dimensional Stacked Structure and Methods of De-Skewing Data Therein - A semiconductor memory device having a 3D stacked structure includes: a first semiconductor area with a stacked structure of a first layer having first data and a second layer having second data; a first line for delivering an access signal for accessing the first semiconductor area; and a second line for outputting the first and/or second data from the first semiconductor area, wherein access timings of accessing the first and second layers are controlled so that a first time delay from the delivery of the access signal to the first layer to the output of the first data is substantially identical to a second time delay from the delivery of the access signal to the second layer to the output of the second data, thereby compensating for skew according to an inter-layer timing delay and thus performing a normal operation. Accordingly, the advantage of high-integration according to a stacked structure can be maximized by satisfying data input/output within a predetermined standard.

2011-11-24

20110286255

Magnetic Logic Circuits Formed with Tapered Magnetic Wires - A magnetic circuit in one aspect comprises a plurality of tapered magnetic wires each having a relatively wide input end and a relatively narrow output end, with the output end of a first one of the tapered magnetic wires being coupled to the input end of a second one of the tapered magnetic wires. Each of the tapered magnetic wires is configured to propagate a magnetic domain wall along a length of the wire in a direction of decreasing width from its input end to its output end. In an illustrative embodiment, the magnetic circuit comprises a logic buffer that includes at least one heating element. The heating element may be controlled to facilitate transfer of a magnetic moment from the output end of the first tapered magnetic wire to the input end of the second tapered magnetic wire.

2011-11-24

20110286256

SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR DEVICE - A semiconductor device with a reduced area and capable of higher integration and larger storage capacity is provided. A multi-valued memory cell including a reading transistor which includes a back gate electrode and a writing transistor is used. Data is written by turning on the writing transistor so that a potential according to the data is supplied to a node where one of a source electrode and a drain electrode of the writing transistor and a gate electrode of the reading transistor are electrically connected to each other, and then turning off the writing transistor and holding a predetermined potential in the node. Data is read by supplying a reading control potential to a control signal line connected to one of a source electrode and a drain electrode of the reading transistor, and then detecting potential change of a reading signal line.

2011-11-24

20110286257

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix; a plurality of word lines commonly coupling the control gates of the plural memory cell transistors present in a identical first direction; a plurality of source lines commonly coupling the sources of the plural memory cell transistors present in the identical first direction; a plurality of bit lines commonly coupling the drains of the plural memory cell transistors present in a identical second direction intersecting the first direction; a first transistor having a drain coupled to the source line; a second transistor having a drain coupled to a source of the first transistor, a gate coupled to the word line and a source grounded; and a control line commonly coupling the gates of the plural first transistors.

2011-11-24

20110286258

NONVOLATILE MEMORY DEVICE HAVING A TRANSISTOR CONNECTED IN PARALLEL WITH A RESISTANCE SWITCHING DEVICE - A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in parallel with a resistance switching device. The transistor is switchable between a plurality of different threshold voltages associated with respective memory states. The resistance switching device is configured to be switchable between a plurality of different resistances associated with respective memory states.

2011-11-24

20110286259

Reading Memory Elements Within a Crossbar Array - A method for reading the state of a memory element within a crossbar memory array includes storing a first electric current sensed from a half-selected target memory element within the crossbar memory array; and outputting a final electric current based on the stored first electric current and a second electric current sensed from the target memory element when the target memory element is fully selected.

2011-11-24

20110286260

NONVOLATILE MEMORY DEVICE AND METHOD FOR DRIVING SAME - According to one embodiment, a nonvolatile memory device includes a memory unit and a control unit. The memory unit includes first and second interconnects, and a memory cell. The second interconnect is non-parallel to the first interconnect. The memory cell includes a resistance change layer provided at an intersection between the first and second interconnects. The control unit is connected to the first and second interconnects to supply voltage and current to the resistance change layer. The control unit increases an upper limit of a current supplied to the first interconnect based on a change of a potential of the first interconnect when applying a set operation voltage to the first interconnect in a set operation of changing the resistance change layer from a first state with a first resistance value to a second state with a second resistance value being less than the first resistance value.

2011-11-24

20110286261

RESISTANCE CHANGE MEMORY - According to one embodiment, a resistance change memory includes a memory cell array area and a resistive element area on a substrate. A first memory cell array in the memory cell array area includes a first control line, a second control line above first control line, and a first cell unit between the first and second control lines. A second memory cell array on the first memory cell array includes the second control line, a third control line above the second control line, and a second cell unit between the second and the third control lines. And a resistive element in the resistive element area includes resistance lines, and a resistor connected to the resistance lines. The resistor includes the same member as one of a member of the cell unit and a member of a contact plug.

2011-11-24

20110286262

Semiconductor memory device - A semiconductor memory device includes a plurality of word lines wired in a first direction, a plurality of bit lines wired in a direction crossing the first direction, a memory cell array including a plurality of DRAM cells provided corresponding to intersections between the word lines and the bit lines, a word line driver which drives the word lines, and a plurality of word line potential stabilization transistors connected to the respective word lines and disposed on an opposite side of the word line driver with the memory cell array sandwiched between the word line potential stabilization transistors and the word line driver, each word line potential stabilization transistor turning on when the word line adjacent to a relevant one of the word lines is selected, thereby connecting the relevant word line to a non-selected potential, and turning off when the relevant word line is selected.

2011-11-24

20110286263

MEMORY DEVICE - Memory device, comprising a storage material, a first electrode connected to the storage material; and a second electrode associated to the storage material.

2011-11-24

20110286264

MAGNETIC RANDOM ACCESS MEMORY AND INITIALIZING METHOD - A magnetic random access memory which includes a magnetic record layer which is ferromagnetic; a ferromagnetic magnetization fixed layer whose magnetization is fixed; and a non-magnetic spacer layer provided between the magnetic record layer and the magnetization fixed layer. The magnetic record layer includes a magnetization invertible region whose magnetization is invertible and which is connected to the magnetization fixed layer through the spacer layer; a first magnetization region which has a magnetization in a first direction and which is provided in parallel to the magnetization invertible region; a second magnetization region which has a magnetization in a second direction and which is provided in parallel to the magnetization invertible region; a first inclined region connected to the magnetization invertible region and the first magnetization region at a predetermined inclination angle; and a second inclined region connected to the magnetization invertible region and the second magnetization region at the inclination angle.

2011-11-24

20110286265

PROGRAMMING NON-VOLATILE STORAGE WITH SYNCHONIZED COUPLING - A process for programming non-volatile storage is able to achieve faster programming speeds and/or more accurate programming through synchronized coupling of neighboring word lines. The process for programming includes raising voltages for a set of word lines connected a group of connected non-volatile storage elements. The set of word lines include a selected word line, unselected word lines that are adjacent to the selected word line and other unselected word lines. After raising voltages for the set of word lines, the process includes raising the selected word line to a program voltage and raising the unselected word lines that are adjacent to the selected word line to one or more voltage levels concurrently with the raising the selected word line to the program voltage. The program voltage causes at least one of the non-volatile storage elements to experience programming.

2011-11-24

20110286266

MEMORY SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME - In a read step or a program (write) verification step of a semiconductor memory device, read voltages different from one another are applied to a pair of word lines respectively disposed on both sides of a selected word line to suppress the enlargement of program distribution.

2011-11-24

20110286267

Pattern-Sensitive Coding of Data for Storage in Multi-Level Memory Cells - A method of operating a memory device includes receiving first and second sets of bits to be stored in multi-level cells in the device. A multi-level encoding is selected from among a plurality of multi-level encodings for storing the first and second sets of bits in the multi-level cells. Each multi-level encoding includes at least four encoding levels for a respective multi-level cell. Respective multi-level encodings have respective costs associated with programming the first and second sets of bits into the multi-level cells in accordance with the respective multi-level encodings. The multi-level encoding is selected based on the respective costs of the respective encodings. The first and second sets of bits are encoded in accordance with the selected multi-level encoding to produce encoded data for storage in the device such that a respective multi-level cell stores respective bits from both the first and second sets of bits.

2011-11-24

20110286268

NONVOLATILE SEMICONDUCTOR MEMORY - A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.

2011-11-24

20110286269

Non-Volatile Electronic Memory Device With NAND Structure Being Monolithically Integrated On Semiconductor - A non-volatile electronic memory device is integrated on a semiconductor and is of the Flash EEPROM type with a NAND architecture including at least one memory matrix divided into physical sectors, intended as smallest erasable units, and organized in rows or word lines and columns or bit lines of memory cells. At least one row or word line of a given physical sector is electrically connected to at least one row or word line of an adjacent physical sector to form a single logic sector being erasable, with the source terminals of the corresponding cells of the pair of connected rows referring to a same selection line of a source line.

2011-11-24

20110286270

SEMICONDUCTOR MEMORY DEVICE AND AN OPERATING METHOD THEREOF - A semiconductor memory device including a flash memory that includes a page, wherein the page includes a plurality of memory cells connected to even bitlines and odd bitlines of the flash memory, and the memory cells are disposed in a plurality of sectors. The semiconductor memory device also includes a memory controller configured to provide the flash memory with a read address that identifies sectors to be read. The flash memory is configured to determine a sequence of even sensing and odd sensing based on the read address and perform the even sensing and the odd sensing according to the determined sequence. In addition, the flash memory is configured to sense data of at least one identified sector that includes memory cells connected to the even bitlines during the even sensing and sense data of at least one identified sector that includes memory cells connected to the odd bitlines during the odd sensing.

2011-11-24

20110286271

MEMORY SYSTEMS AND METHODS FOR READING DATA STORED IN A MEMORY CELL OF A MEMORY DEVICE - A memory system is provided. A memory device includes multiple memory cells for storing data. A controller is coupled to the memory device for accessing the memory device. When reading the data stored in a memory cell, the controller receives a digital signal representing content of the data stored in the memory cell, and detects a level of a voltage or conducted current of the memory cell according to the digital signal to obtain the content of the data.

2011-11-24

20110286272

MEMORY DEVICES AND THEIR OPERATION WITH DIFFERENT SETS OF LOGICAL ERASE BLOCKS - Methods of operating memory devices include storing data of a first type in a first set of logical erase blocks and storing data of a second type in a second set of logical erase blocks. The logical erase blocks of the first set of logical erase blocks each have a first size the logical erase blocks of the second set of logical erase blocks each have a second size different than the first size.

2011-11-24

20110286273

SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME - An embodiment of the invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. One embodiment of the invention also provides a method of controlling the semiconductor device.

2011-11-24

20110286274

NONVOLATILE MEMORY DEVICE, PROGRAMMING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME - A nonvolatile memory device preventing a program disturb, a program method thereof and a memory system including the nonvolatile memory device and the program method. The nonvolatile memory device includes a memory cell array; first and second word lines connected to a NAND string in the memory cell array; a third word line connected to the NAND string, the third word line being disposed between the first and second word lines; a temperature sensor configured to measure the temperature of the nonvolatile memory device; and a voltage generator configured to generate first and second pass voltages and a program voltage, and the voltage level of at least one of the first and second pass voltages is controlled according to the measured temperature. When a program operation is performed, the program voltage is applied to the third word line, the first pass voltage is applied to the first word line, the second pass voltage is applied to the second word line.

2011-11-24

20110286275

Stacked Memory Devices And Method Of Manufacturing The Same - A stacked memory device may include at least one memory unit and at least one peripheral circuit unit arranged either above or below the at least one memory unit. The at least one memory unit may include a memory string array, a plurality of bit lines, and a plurality of string selection pads. The memory string may include a plurality of memory strings arranged in a matrix and each of the memory strings may include a plurality of memory cells and a string selection device arranged perpendicular to a substrate. The plurality of bit lines may extend in a first direction and may be connected to ends of the plurality of memory strings. The plurality of string selection pads may be arrayed in a single line along the first direction and may be connected to the string selection devices included in the plurality of memory strings.

2011-11-24

20110286276

PARTIAL LOCAL SELF BOOSTING FOR NAND - A memory system is programmed with minimal program disturb and reduced junction and channel leakage during self-boosting. Pre-charging bias signals are applied to word lines adjacent to a selected word line before a program signal is applied to the selected word line and a pass signal is applied to the remaining word lines. The pre-charging bias signals apply a pre-charge to the memory cells. The pre-charging bias signals are chosen to improve the isolation of the memory cells on word lines adjacent to the selected word line, improve self boost efficiency and reduce current leakage to prevent or reduce program disturb and/or programming errors especially in the inhibited memory cells on the selected word line.

2011-11-24

20110286277

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix; a plurality of word lines commonly coupling the control gates of the plural memory cell transistors present in a identical first direction; a plurality of source lines commonly coupling the sources of the plural memory cell transistors present in the identical first direction; a plurality of bit lines commonly coupling the drains of the plural memory cell transistors present in a identical second direction intersecting the first direction; a first transistor having a drain coupled to the source line; a second transistor having a drain coupled to a source of the first transistor, a gate coupled to the word line and a source grounded; and a control line commonly coupling the gates of the plural first transistors.

2011-11-24

20110286278

METHOD OF STORING E-FUSE DATA IN FLASH MEMORY DEVICE - Provided is a method of storing configuration data regarding an operating environment of a flash memory device, which includes a memory cell array having an electrical fuse (E-Fuse) block for storing the configuration data. The method includes storing the configuration data in multiple strings of the E-Fuse block, each string including multiple memory cells configured to store one bit.

2011-11-24

20110286279

Erase and Programming Techniques to Reduce the Widening of State Distributions in Non-Volatile Memories - Techniques are presented for use in memory devices to improve reliability and endurance by reducing the widening in state distributions, that occurs after multiple write/erase cycles. One set of techniques uses a pre-conditioning operation where a pulse series, which may include program and gentle erase, are applied to one or more wordlines while a voltage differential is applied in the wordline direction, bitline direction, or both. Another set of techniques uses a dual or multi-pulse program process, where an increased wordline-to-wordline differential used in the first pulse of a pair.

2011-11-24

20110286280

Pulse Control For NonVolatile Memory - This disclosure provides a nonvolatile memory device that uses pulsed control and rest periods to mitigate the formation of defect precursors. A first embodiment uses pulsed bitline control, where the coupling between a memory cell channel and a reference voltage (selected in response to the bitline) is pulsed when it is desired to change state in the associated memory cell. Each pulse may be chosen to be less than about (20) nanoseconds, while a “rest period” between pulses typically is chosen to be on the order of about a hundred nanoseconds or greater (e.g., one microsecond). Because bitline control is used, very short rise times can be enabled, enabling generation of pulse durations of (50) nanoseconds or less. In other embodiments, these methods may also be more generally applied to other conductors (e.g., wordline or substrate well, for program or erase operations); if desired, segmented wordlines or bitlines may also be used, to minimize RC loading and enable sufficiently short rise times to make pulses robust.

2011-11-24

20110286281

REFERENCE CURRENT GENERATOR USED FOR PROGRAMMING AND ERASING OF NON-VOLATILE MEMORY - A reference current generator used for programming and erasing of the non-volatile memory. Wherein, a self-biasing reference generator is used to generate a first reference voltage of a negative temperature coefficient and a second reference voltage of a positive temperature coefficient. A voltage converter receives said first reference voltage and generate a third reference voltage having its temperature coefficient less than that of said first reference voltage, and said second reference voltage and said third reference voltage are input to a reference current source, such that said reference current source generates a reference current of low temperature sensitivity. Through said reference current source, said second reference voltage and said third reference voltage are used to compensate said negative temperature coefficient of a threshold voltage of a transistor, thus reducing difference of times required for programming and erasure under various operation temperatures.

2011-11-24

20110286282

SEMICONDUCTOR MEMORY COLUMN DECODER DEVICE AND METHOD - Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data register buffer unit, a row decoder, an erase control unit, and an input/output buffer unit. In one or more embodiments, the erase control unit applies voltages to the well to erase the memory cells in a manner that avoids breaking down p-n junctions formed by transistors fabricated in the well. In another embodiment, high voltage transistors are used to selectively isolate the bit lines from and couple the bit lines to a peripheral circuit in pairs so that each high voltage transistor is shared by two bit lines.

2011-11-24

20110286283

3D TWO-BIT-PER-CELL NAND FLASH MEMORY - A 3D memory device is described which includes bottom and top memory cubes having respective arrays of vertical NAND string structures. A common source plane comprising a layer of conductive material is between the top and bottom memory cubes. The source plane is supplied a bias voltage such as ground, and is selectively coupled to an end of the vertical NAND string structures of the bottom and top memory cubes. Memory cells in a particular memory cube are read using current through the particular vertical NAND string between the source plane and a corresponding bit line coupled to another end of the particular vertical NAND string.

2011-11-24

20110286284

MULTI-TRANSISTOR NON-VOLATILE MEMORY ELEMENT - The present disclosure provides a multi-transistor element including a substrate, a first floating gate disposed on the substrate, a second floating gate disposed on the substrate and coupled to the first floating gate, and a first active region disposed in the substrate and coupled to the first and second floating gates.

2011-11-24

20110286285

SEMICONDUCTOR INTEGRATED CIRCUIT FOR GENERATING CLOCK SIGNALS - A semiconductor integrated circuit device includes a write-read clock control signal generating unit that activates a read clock control signal and a write clock control signal in response to one of a write operational mode and a read operational mode after maintaining the read clock control signal and the write clock control signal at a deactivation state in response to one of an idle mode and a refresh operational mode, and a clock buffer that generates a read clock signal and a write clock signal in response to a clock signal, the read clock control signal, and the write clock control signal.

2011-11-24

20110286286

SEMICONDUCTOR INTEGRATED CIRCUIT FOR GENERATING CLOCK SIGNALS - A semiconductor integrated circuit device includes a write-read clock control signal generating unit that activates a read clock control signal and a write clock control signal in response to one of a write operational mode and a read operational mode after maintaining the read clock control signal and the write clock control signal at a deactivation state in response to one of an idle mode and a refresh operational mode, and a clock buffer that generates a read clock signal and a write clock signal in response to a clock signal, the read clock control signal, and the write clock control signal.

2011-11-24

20110286287

SEMICONDUCTOR MEMORY DEVICE WITH OPTIMUM REFRESH CYCLE ACCORDING TO TEMPERATURE VARIATION - Methods for generating a refresh signal in a semiconductor device and methods for performing a refresh operation in a semiconductor memory device are disclosed. A method for generating a refresh signal includes measuring a temperature of the semiconductor memory device, generating a temperature controlled voltage based on the measured temperature, generating an N-bit digital signal based on the temperature controlled voltage, and generating a refresh signal whose frequency is determined by the N-bit digital signal. The generation of the temperature controlled voltage includes generating a first current that is increased when the measured temperature is decreased and is decreased with the measured temperature is increased, and generating the temperature controlled voltage.

2011-11-24

20110286288

DYNAMIC ADJUSTMENT OF REFERENCE VOLTAGE IN A COMPUTER MEMORY SYSTEM - A method provides improved signal quality in a computer memory system. In one embodiment, a digital signal is generated having a voltage interpreted with respect to a reference voltage. The reference voltage is dynamically adjusted as a function of the traffic intensity at which the digital signal is directed to a particular receiver. A training phase may be performed for each DIMM of the memory system, to construct a lookup table correlating suitable reference voltages with different traffic intensities. The lookup table may be referenced during a subsequent execution phase, to dynamically select a reference voltage according to changing traffic intensity. The dynamically selected reference voltage value may be enforced by using transistors to selectively recruit resistors of a resistor network.

2011-11-24

20110286289

SYSTEM AND METHOD OF SELECTIVELY VARYING SUPPLY VOLTAGE WITHOUT LEVEL SHIFTING DATA SIGNALS - An electronic system implements a plurality of voltage domains, at least one of which has a selectively variable supply voltage, without requiring the use of a large number of level shifters (e.g., for each data and/or address line). The supply voltage for a first domain is set equal or nearly equal to that of a second domain for a first duration, when the two domains are connected for data transfer across a system bus. When the first domain is isolated from the bus, its supply voltage is set differently from that of the second domain for a second duration. In the second duration, the first domain may have a higher supply voltage, e.g., to perform high-performance computational tasks. Alternatively, it may have a lower supply voltage, to conserve power, if its computational task is less demanding.

2011-11-24

20110286290

DRIVING METHOD OF SEMICONDUCTOR DEVICE - A period (inverted period) in which a high negative potential is applied to a gate of the transistor is provided between a writing period and a retention period. In the inverted period, supply of positive electric charge from the drain of the transistor to the oxide semiconductor layer is promoted. Thus, accumulation of positive electric charge in the oxide semiconductor layer or at the interface between the oxide semiconductor layer and a gate insulating film can converge in a short time. Therefore, it is possible to suppress a decrease in the positive electric charge in the node electrically connected to the drain of the transistor in the retention period after the inverted period. That is, the temporal change of data stored in the semiconductor device can be suppressed.

2011-11-24

20110286291

SEMICONDUCTOR MEMORY DEVICE COMPRISING A PLURALITY OF STATIC MEMORY CELLS - A driver power supply circuit stepping down a power supply voltage is arranged at a power supply node of a word line driver. The driver power supply circuit includes a non-silicide resistance element of N+ doped polycrystalline silicon, and a pull-down circuit lowering a voltage level of the driver power supply node. The pull-down circuit includes a pull-down transistor having the same threshold voltage characteristics as a memory cell transistor pulling down a voltage level of the driver power supply node, and a gate control circuit adjusting at least a gate voltage of the pull-down transistor. The gate control circuit corrects the gate potential of the pull-down transistor in a manner linked to variations in threshold voltage of the memory cell transistor.

2011-11-24

20110286292

METHOD OF FORMING A UNIQUE NUMBER - A unique number is formed with logic states from a static random access memory (SRAM), which is laid out to be balanced so that memory cells within the SRAM assume a non-random logic state when power is applied to the SRAM. The unique number is formed by grounding the word lines and bit lines before power is applied to the memory cells, applying power to the memory cells to assume the non-random logic state, reading the non-random logic states held by the memory cells, and forming the unique number from the logic states read from the memory cells.

2011-11-24

20110286293

METHOD OF FORMING A UNIQUE NUMBER - A unique number is formed with logic states from a static random access memory (SRAM), which is laid out to be balanced so that memory cells within the SRAM assume a non-random logic state when power is applied to the SRAM. The unique number is formed by grounding the word lines and bit lines before power is applied to the memory cells, applying power to the memory cells to assume the non-random logic state, reading the non-random logic states held by the memory cells, and forming the unique number from the logic states read from the memory cells.

2011-11-24

20110286294

METHOD OF FORMING A UNIQUE NUMBER - A unique number is formed with logic states from a static random access memory (SRAM), which is laid out to be balanced so that memory cells within the SRAM assume a non-random logic state when power is applied to the SRAM. The unique number is formed by grounding the word lines and bit lines before power is applied to the memory cells, applying power to the memory cells to assume the non-random logic state, reading the non-random logic states held by the memory cells, and forming the unique number from the logic states read from the memory cells.

2011-11-24

20110286295

Methods of Arranging L-Shaped Cell Blocks In Semiconductor Devices - Semiconductor devices are provided including a plurality of L-shaped cell blocks each including a cell array and a plurality of decoders disposed in horizontal and vertical directions of the cell array. The plurality of L-shaped cell blocks is oriented in a diagonal direction intersecting the horizontal and vertical directions. Related methods are also provided herein.

2011-11-24

20110286296

SCREW EXTRUDER FOR CONTINUOUS AND SOLVENT-FREE RESIN EMULSIFICATION - A screw extruder is presented including a feed hopper for receiving materials and a body member having at least one supply port and at least one outlet port. The screw extruder also includes a screw positioned within the body member and movable along a channel defining a longitudinal axis. The screw extruder further includes a drive shaft for rotatably driving the screw along the channel. The screw extruder may be configured to mix the materials received via the feed hopper with a series of one or more forward, neutral, and reverse kneading elements.

2011-11-24

20110286297

INFUSER FOR SUPERSATURATING A LIQUID WITH A GAS - A gas infuser facilitates dissolving a gas into a liquid to produce a supersaturated liquid. A liquid in the infuser is spread over the surfaces of infuser structures in the infuser chamber such that the liquid forms a film on the surfaces in the presence of a pressurized gas. Preferably the liquid flows by gravity over the surfaces of the infuser structures as it flows in a cascade from an input at the top of the infuser. The infuser described herein may be used with a variety of infuser structures to provide increased surface area for the cascading flow of liquid. The liquid leaves the infuser supersaturated with the gas. The supersaturated liquid can then be used in any one of a variety of industrial type processes. The infuser is preferably a continuous flow process but may also be operated as a batch process. The gas and liquid are preferably introduced together into the infuser under pressure in a non-dissolved state or semi-dissolved state.

2011-11-24

20110286298

ADJUSTABLE ORBIT IMBALANCE COMPENSATING ORBITAL SHAKER - An orbital shaker apparatus is provided, including a first shaft connected to a first bearing assembly at a first end and a mounting portion at the other. The first shaft is rotatable about a first shaft axis, and is connected to a motor. The second shaft has a bearing assembly on the mounting portion at one end and a platform at the other, and is aligned parallel to and offset from the first shaft by a distance. A counterweight rotor assembly is coupled to the mounting portion, and rotated by a belt driven by a pulley connected to the rotating shaft of a counterweight motor. The counterweight assembly includes two counterweight bearings, each having a counterweight wedge. The platform also includes supports for objects to be secured thereto. In use, as the counterweight rotor rotates, the second shaft, second bearing assembly, and platform describes a circular orbit with diameter 2R.

2011-11-24

20110286299

Variable Height Blender System - A variable height blender system is disclosed that includes an industrial blender carried by a first lift and a second lift for moving the blender up and down into any of various vertical positions. The variable height blender system includes drive controls for independently controlling movement of the first and second lifts, and a synchronizer in communication with at least one of the first and second drive controls for synchronizing the movement of the first and second lifts to maintain the batch blender substantially level. The synchronizer includes a level sensor that senses a tilt of the batch blender with respect to a local gravity vector and sends level reading signals to the synchronizer for use in independently adjusting the speeds of the first and/or second lift.

Seismic Streamer Shape Estimation - A seismic streamer system and associated methods for estimating the shape of a laterally steered seismic streamer. The streamer is divided into a series of contiguous streamer segments by lateral-steering devices. Heading sensors positioned in forward and aft portions of each segment produce heading readings. Each segment is modeled as having a linear shape in the forward portion and a curved shape in the aft portion. The shape of the segment is estimated according to the model from the heading readings on the segment.

2011-11-24

20110286302

Marine Seismic Survey Method and System - An inventive method provides for control of a seismic survey spread while conducting a seismic survey, the spread having a vessel, a plurality of spread control elements, a plurality of navigation nodes, and a plurality of sources and receivers. The method includes the step of collecting input data, including navigation data for the navigation nodes, operating states from sensors associated with the spread control elements, environmental data for the survey, and survey design data. The positions of the sources and receivers are estimated using the navigation data, the operating states, and the environmental data. Optimum tracks for the sources and receivers are determined using the position estimates and a portion of the input data that includes at least the survey design data. Drive commands are calculated for at least two of the spread control elements using the determined optimum tracks. The inventive method is complemented by an inventive system.

2011-11-24

20110286303

Coaxial support structure for towed marine seismic source arrays - A seismic source array includes at least one float. A plurality of rigid conduit sections each includes a bracket for suspension from the float at a selected depth in a body of water and configured to suspend a seismic energy source therefrom. At least one bend strain relief is coupled between adjacent rigid conduit sections. Each bend strain relief includes a coupling at each longitudinal end. Each bend strain relief includes woven fiber molded into flexible plastic for transmitting axial loading while absorbing bending and torsional stress. A seismic energy source is suspended from each bracket. Lines for operating the seismic energy sources pass through the rigid conduit sections and the at least one bending strain relief.

2011-11-24

20110286304

Downhole Acoustic Emission Formation Sampling - A method, system and apparatus for testing properties of a rock formation surrounding a wellbore in situ. The apparatus includes a tool body, one or more indenters, and one or more acoustic sensors. The body includes an outer surface that defines one or more cavities therein. Each cavity extends into the body. Each indenter is positioned within a corresponding cavity and is positionable into an operating position and a non-operating position. The acoustic sensor is positioned within the cavity and adjacent to the indenter. The indenter is positioned at least partially beyond the outer surface when in the operating position. The acoustic sensor senses one or more acoustic events occurring when the indenter is in the operating position. The apparatus is inserted into the wellbore. Once inserted, the indenter applies a load onto the rock formation causing cracking and the sensor receives the generated acoustic transmissions. The transmissions are analyzed.

2011-11-24

20110286305

TIME REVERSE IMAGING OPERATORS FOR SOURCE LOCATION - A method and system for processing synchronous array seismic data includes acquiring synchronous passive seismic data from a plurality of sensors to obtain synchronized array measurements. A reverse-time data propagation process is applied to the synchronized array measurements to obtain a plurality of dynamic particle parameters associated with subsurface locations. Imaging conditions are applied to the dynamic particle parameters to obtain image values associated with subsurface energy source locations.

2011-11-24

20110286306

DETERMINING ORIGIN AND MECHANISM OF MICROSEISMIC EVENTS IN THE EARTH'S SUBSURFACE BY DEVIATORIC MOMENT INVERSION - A method for locating origin time, origin location and source mechanism of seismic events occurring in a selected volume of subsurface formations includes calculating a travel time from each possible origin location to each of a plurality of seismic receivers disposed above the volume in a selected pattern. A signal amplitude is measured by each receiver for each possible origin time at each possible origin location. The signal amplitude is determined from the continuously recorded data by calculating travel time delays for each possible origin location and origin time. The deviatoric moment tensors are determined from the signal amplitudes by moment tensor inversion restricted to deviatoric moment tensors. A norm for each deviatoric moment tensor is generated. An origin time, origin position and source mechanism of a seismic event is determined wherein any norm exceeds a selected threshold.

2011-11-24

20110286307

ACOUSTIC LOGGING WHILE DRILLING TOOL HAVING RAISED TRANSDUCERS - An acoustic logging while drilling tool includes an acoustic transmitter and a linear array of acoustic receivers. At least one of the transmitter and the linear array of receivers is deployed on a blade having an outer diameter greater than that of the tool body. In preferred embodiments the transmitter and linear array are each deployed on a distinct blade. Deployment of the transmitter and/or the receivers on a blade reduces the standoff distance to the borehole wall which tends to improve the signal strength of received guided waves without an increase in transmitter power or receiver sensitivity.

2011-11-24

20110286308

Downlinking Communication System and Method - A downlinking signal is transmitted downhole from the surface using drilling fluid as the communications medium. The downlinking signal includes at least a synchronization phase and a command phase. Attributes of the synchronization phase are used upon reception of the signal to determine corresponding attributes of the command phase. Commands may be transmitted downhole while drilling and simultaneously while using mud-pulse telemetry uplinking techniques.

2011-11-24

20110286309

Downlinking Communication System and Method Using Signal Transition Detection - A downlinking signal is transmitted downhole from the surface using drilling fluid as the communications medium. The downlinking signal includes at least a synchronization phase and a command phase. The downlinking signal is differentiated upon reception such that attributes of the synchronization phase may be used to determine corresponding attributes of the command phase. Commands may be transmitted downhole while drilling and simultaneously while using mud-pulse telemetry uplinking techniques.

2011-11-24

20110286310

Hour notification - A position information acquisition section acquires position information about a mobile terminal, and a storage section stores hour information and position condition information inputted to an interface section in association with each other. When the hour shown by a clock becomes the hour indicated by the hour information stored in the storage section, a comparison section compares the position condition information stored in association with the hour information, with the position information acquired by the position information acquisition section. If the position information corresponds to the position condition information as a result of the comparison, a notification section gives a notification.

2011-11-24

20110286311

Calendar mechanism and timepiece equipped with the same - A calendar mechanism includes: a calendar driving wheel equipped with a calendar finger portion rotating a calendar cogwheel portion and a cam portion equipped with a torque reduction shape portion; a lever main body portion rotatably supported on a substrate, a jumper support lever equipped with a cam follower portion following the cam portion, and a jumper operating spring shoe portion provided in an intermediate portion in the longitudinal direction of the lever main body portion and formed on the same side as the cam follower portion with respect to the rotating direction thereof; and a jumper arranged so as to be rotatable with respect to the jumper support lever while overlapping the lever main body portion of the jumper support lever, the jumper being equipped with a jump control finger portion which is directed in a direction opposite to the cam follower portion of the jumper support lever and whose distal end side end portion is pressed against the calendar cogwheel portion by a jumper spring portion locked to the jumper operating spring shoe portion.

LED ANALOG CLOCK OR WATCH DISPLAY - The Clock Face or Watch Face contains two physically separate and non-concentric circles of Light representing Hours and Minutes and an Arc representing Seconds. The Hours fill in 12 smaller circles with Light as the Hours pass and the Minutes fill in 12 smaller circles with Light as 60 minutes pass.

2011-11-24

20110286314

ENVIRONMENT DEPENDENT - TEMPERATURE INDEPENDENT COLOR CHANGING LABEL - A timing device comprises a sensing material and/or a component which is sensitive to the presence of an environmental attribute. The environmental attribute drives and speeds up or slows the timing device as the concentration of the attribute increases or decreases, respectively. Alternatively, the timing device is activated upon sensing the presence of the environmental attribute and indicates a total passage of time from exposure/activation of the timing device. Particularly, sensing materials of varying types are able to be used to indicate exposure to a variety of substances. For example, in some embodiments, the timing device comprises a sensing material which is sensitive to the presence of ultraviolet radiation. Alternatively, the sensing material is sensitive to other variables such as x-ray radiation and nuclear radiation. In further embodiments, the sensing material is sensitive to biological or physical contamination.

ADAPTIVE WRITING METHOD FOR HIGH-DENSITY OPTICAL RECORDING APPARATUS AND CIRCUIT THEREOF - An apparatus configured to write input data on an optical recording medium using a write pulse waveform, the write pulse waveform including a first pulse, a last pulse and a multi-pulse train, is provided. The apparatus includes a discriminator configured to discriminate a magnitude of a present mark and a magnitude of a leading space from the input data, a write waveform controller configured to control the write pulse waveform to generate an adaptive write pulse waveform by varying a position of a rising edge of a first pulse of the present mark to be written according to the magnitude of the present mark and the magnitude of the leading space, and use a grouping table to control the write pulse waveform to generate the adaptive write pulse waveform, the grouping table being configured to store rising edge data of the first pulse of the write pulse waveform varying according to corresponding stored values of magnitudes of present marks and magnitudes of leading spaces, and a processor configured to process the input data on the optical recording medium using the adaptive write pulse waveform. The discriminator is further configured to apply the magnitude of the present mark and the magnitude of the leading space to the write waveform controller. The adaptive write pulse waveform is generated without regard for a trailing space of the present mark being written using the adaptive write pulse waveform. A width of the first pulse is varied by varying the position of the rising edge.

2011-11-24

20110286317

ADAPTIVE WRITING METHOD FOR HIGH-DENSITY OPTICAL RECORDING APPARATUS AND CIRCUIT THEREOF - An apparatus configured to write input data on an optical recording medium using a write pulse waveform including a first pulse, a last pulse and a multi-pulse train is provided. The apparatus includes a discriminator configured to discriminate a magnitude of a present mark, a magnitude of a leading space, and a magnitude of a trailing space from the input data, a write waveform controller configured to control the write pulse waveform based on a grouping table, the grouping table being configured to store rising edge data of the first pulse of the write pulse waveform grouped in corresponding pulse groups according to magnitudes of a plurality of present marks and magnitudes of a plurality of spaces adjacent to the plurality of present marks, the write pulse waveform being controlled to generate an adaptive write pulse waveform by varying a position of a rising edge of a first pulse of the mark to be written according to at least the magnitudes of the present mark and the leading space, and a processor configured to process the input data on the optical recording medium using the adaptive write pulse waveform. The discriminator is further configured to apply the magnitude of the present mark, the magnitude of the leading space, and the magnitude of the trailing space to the write waveform controller. The width of the first pulse is varied by varying the position of the rising edge.

2011-11-24

20110286318

ADAPTIVE WRITING METHOD FOR HIGH-DENSITY OPTICAL RECORDING APPARATUS AND CIRCUIT THEREOF - An optical recording medium is provided, the optical recording medium including a plurality of zones respectively corresponding to width data of first and/or last pulses of an adaptive write pulse waveform stored in a grouping table, the grouping table being configured to group a magnitude of a present mark of input data and magnitudes of leading and/or trailing spaces of the present mark into a short pulse group, a middle pulse group, and a long pulse group using grouping pointers, store data configured to calculate a width of a write pulse, an adaptive write pulse being generated in response to the calculated width, generate the adaptive write pulse waveform by varying a position of a rising edge of a first pulse of a mark to be written according to the magnitudes of the present mark and the leading space, the adaptive write pulse waveform being generated without regard for the trailing space of the present mark being written using the adaptive write pulse waveform, the adaptive write pulse being configured to correspond to the adaptive write pulse waveform, and store rising edge data of the first pulse of the adaptive write pulse waveform varying according to corresponding stored values of lengths of marks to be written. A width of the first pulse is varied by varying the position of the rising edge.

2011-11-24

20110286319

CHARGED PARTICLE BEAM WRITING APPARATUS, WRITE DATA CREATION METHOD AND CHARGED PARTICLE BEAM WRITING METHOD - A charged particle beam writing apparatus according to an embodiment, includes a storage device configured to store write data which is to be written by using a charged particle beam and in which a plurality of patterns with different writing precision is defined; a cutout unit configured to read data of each pattern from the storage device and to cut out a partial pattern, among a pattern, in the plurality of patterns, whose writing precision is on a low-precision side, positioned within a range of influence of a proximity effect from a region edge of a pattern, in the plurality of patterns, whose writing precision is on a high-precision side; a merge processing unit configured to perform merge processing of a cut-out partial pattern on the low-precision side and the pattern on the high-precision side; and a pattern writing unit configured to write a pattern obtained by the merge processing and a remaining partial pattern on the low-precision side remaining without being merged with the pattern on the high-precision side to a target object by using the charged particle beam under different writing conditions based on data of the pattern obtained by the merge processing and data of the remaining partial pattern.

2011-11-24

20110286320

ADAPTIVE WRITING METHOD FOR HIGH-DENSITY OPTICAL RECORDING APPARATUS AND CIRCUIT THEREOF - An optical recording medium is provided, the optical recording medium including a plurality of zones configured to store data corresponding to an adaptive write pulse, the adaptive write pulse including a first pulse, a last pulse, and a multi-pulse train, the adaptive write pulse being different for each of the plurality of zones, the plurality of zones being reflected by a grouping table, the grouping table being configured to generate an adaptive write pulse waveform by varying a position of a rising edge of a first pulse of a mark to be written according to a length of the mark to be written and a leading space, the adaptive write pulse waveform being generated without regard for a trailing space of a present mark being written using the adaptive write pulse waveform, the adaptive write pulse being configured to correspond to the adaptive write pulse waveform, and store rising edge data of the first pulse of the adaptive write pulse waveform varying according to corresponding stored values of lengths of marks to be written. A width of the first pulse is varied by varying the position of the rising edge.

2011-11-24

20110286321

TIME-SLICED SEARCH OF RADIO ACCESS TECHNOLOGIES DURING CONNECTED-MODE RADIO LINK FAILURE - Systems and methodologies are described that facilitate apportioning a radio link failure (RLF) recovery timer among a plurality of radio access technologies (RAT). Once RLF is determined, a RLF recovery timer can be obtained and split according to a timer allocation. The timer allocation can include equal or weighted percentages related to the plurality of RATs, and a timer can be split according to the percentages to attempt connection using a RAT during a corresponding portion of the timer. In addition, the timer allocation can be defined according to a type of communication. In this regard, for voice calls, the timer can be split among circuit-switched networks regardless of a network from which connection is lost, and/or the like. Moreover, the timer allocation can be defined based on RAT deployment characteristics.

2011-11-24

20110286322

METHOD AND APPARATUS FOR SEAMLESS TRANSITIONS OF DATA TRANSMISSION TRANSFER BETWEEN RADIO LINKS - A method for wireless communications is provided that includes generating an index for a plurality of packets for use in a first radio link for transmission to an apparatus; transmitting the plurality of packets using a second radio link to the apparatus; determining transmission state information indicating whether each packet in the plurality of packets have been received by the apparatus; and transmitting additional packets based on the index and the transmission state information. Apparatuses for performing the methods are also disclosed.

2011-11-24

20110286323

DEVICE AND SYSTEM FOR PROTECTION SWITCHING - A unit and a system for protection switching of line cards in a telecommunication system are described. A protection unit is connectable between communication lines and a line interface unit. The protection unit can be interconnected with other protection units to form a protection switching system. One protection unit in the protection switching system is connectable to a stand-by line card. The protection switching system is configured so that when protection switching is needed, the line signal is re-directed between the communication line for a failed line card and the stand-by line card via electrical connection elements.

2011-11-24

20110286324

Link Failure Detection and Traffic Redirection in an Openflow Network - Failure detection and traffic redirection are implemented in an OpenFlow switch. Link failure detection packets, such as Bidirectional Forwarding Detection (BFD) packets, are periodically sent out on links to peer OpenFlow switches, such as via the Multi-protocol Label Switching (MPLS) Transport Profile (MPLS-TP). Link failure detection packets are received from the peer OpenFlow switches on the links, and monitored. A link failure is detected if no incoming link failure detection packets are received on a link for a predetermined interval. In the event of a link failure, traffic is redirected from the failed link to a backup link by altering entries on a flow table of the OpenFlow switch.

2011-11-24

20110286325

HYBRID SATELLITE AND MESH NETWORK SYSTEM FOR AIRCRAFT AND SHIP INTERNET SERVICE - A hybrid satellite-mesh network including a ground segment, a mobile segment and a satellite segment provides high bandwidth communication between mobile platforms and the Internet. The satellite segment is used only when mesh network communication links between mobile segment nodes and ground segment nodes are unavailable. Mobile segment nodes can function in either an access terminal mode or an access point mode to communicate with other mobile segment nodes according to a routing algorithm in a mesh portion of the network. Mobile segment nodes employ adaptive frequency reuse, link level date rate adaptation, link level power control and adaptive beam forming antennas.

2011-11-24

20110286326

Communication system, forwarding node, path management server, and communication method - A communication system comprises: a path management server that generates a plurality of forwarding path information items each includes a sequence of identifiers, each of which identifies a communication interface provided in each of a plurality of forwarding nodes on a forwarding path in a data forwarding network or a link established between the forwarding node and a neighboring node thereof; and a forwarding node that, in accordance with at least one of the plurality of forwarding path information items, executes a packet forwarding processing of a packet with a header including the plurality of forwarding path information items.

2011-11-24

20110286327

Method, Apparatus, and System for Processing Radio Link Failure - A method for processing radio link failure (RLF) is disclosed. When a user equipment (UE) communicates with a network through two or more carriers, if a downlink RLF occurs on at least one of the two or more carriers, the UE determines whether there is a carrier among the two or more carriers on which no downlink RLF occurs. The UE stops sending information on an uplink dedicated physical control channel (DPCCH) of the carrier on which the downlink RLF occurs if there is a carrier on which no downlink RLF occurs.

2011-11-24

20110286328

SYSTEM MANAGEMENT METHOD AND SYSTEM MANAGEMENT APPARATUS - Provided is an IT system to minimize occurrence of a bottleneck on a network while effectively making use of the bandwidth of the network. A system management apparatus collects performance information from a network device, and calculates the average value, the peak hour, and the variance from the collected performance information. In response to a request for addition of a business system, the system management apparatus builds configuration patterns of a group of virtual servers configuring the business system and monitors traffic states of the paths on the network, identifies the part of the network where the traffic quality is most degraded, and determines the pattern that includes the path which has the smallest variance in the traffic based on traffic information on the part where the communication quality is degraded identified in each pattern as the requested system configuration of the business system.

2011-11-24

20110286329

ACCESS POINT, TERMINAL, AND METHOD FOR PROCESSING ACCESS CONTROL BASED ON CONGESTION LEVEL OF TRANSMISSION CHANNEL - An access point (AP) measures a congestion level of a transmission channel representing a collision probability between frames at a channel busy duration and transmits the congestion level to a terminal. Therefore, the terminal extracts a congestion level that is included in a frame that is received from the AP through a scan process for searching for an AP to which the terminal is to connect. The terminal selects an AP to connect from at least one AP based on the extracted congestion level of the transmission channel.

2011-11-24

20110286330

Hardware Filtering of Unsolicited Grant Service Extended Headers - A system and method is presented that uses hardware at a central node to determine if bandwidth being provided to a remote node in accordance with an unsolicited grant service (UGS) flow requires adjustment. In one embodiment, the hardware performs this function by comparing information in two consecutively-received UGS extended headers from the same remote device. If the information in the current and previous UGS extended headers differ, then an indication is provided to software of the central node that the bandwidth being provided to the remote node requires adjustment.

2011-11-24

20110286331

Differentiated Services Code Point Mirroring For Wireless Communications - The DSCP Mirroring System enables the automatic reuse of the Differentiated Services Code Point header by the user devices that are served by a network to enable delivery of wireless services to the individually identified user wireless devices and manage the various data traffic and classes of data to optimize or guarantee performance, low latency, and/or bandwidth without the overhead of the management of the Differentiated Services Code Point header.

2011-11-24

20110286332

Flow control apparatus, network system, network control method, and program - A flow control apparatus that sends control information to one or more switching node apparatuses, where the control information is assigned to each series of communications performed between terminal devices via the switching node apparatuses. The flow control apparatus includes an effective time setting unit that sets an effective time of the control information based on an elapsed time measured from when the terminal devices which perform the series of communications start a communication via a specific one of the switching node apparatuses, in a manner such that the longer the elapsed time, the longer the effective time; and a sending unit that sends the control information every time when the effective time has elapsed.