The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.

A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.

Having the right tools to design and verify your chips has never been more important. After all, you're trying to stay on top of Moore's Law and meet the design challenges that come with this. However, with electronic circuits being an integral component of so many products, design and verification also extends to packages, boards, and the whole system.

To help you create high-quality, differentiated electronic products, Cadence offers a broad portfolio of tools to address an array of challenges related to custom IC, digital, IC package, and PCB design and system-level verification. Find the tools and methodologies you need to meet your power, performance, and area targets; overcome mixed-signal design constraints; achieve faster design closure; and much more.

Our next system-on-chip (SoC) projects will be on a 16nm process, and the Innovus Implementation System can enable much larger blocks than previously possible, decreasing area and top-level complexity.

Electrically aware design can enable us to save several iterations on the design of each block sensitive to parasitic effects. Depending on block complexity, design time savings can range from half a day to several days per block.