From envy at ee.ucla.edu Fri Feb 19 08:56:07 2010
From: envy at ee.ucla.edu (Girish)
Date: Fri, 19 Feb 2010 08:56:07 -0800 (PST)
Subject: P5000 free from 10am-noon
Message-ID:
From mtang at stanford.edu Sun Feb 21 05:20:15 2010
From: mtang at stanford.edu (Mary Tang)
Date: Sun, 21 Feb 2010 05:20:15 -0800
Subject: Warning: No CF4 gas
Message-ID: <4B81330F.8080509@stanford.edu>
Apologies everyone, but it looks like the CF4 cylinder has run dry.
This affects drytek1/2, mrc, p5000etch, pquest, sts (dep) and lampoly.
We will address this as soon as possible.
Your SNF Staff
--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang at stanford.edu
http://snf.stanford.edu
From mtang at stanford.edu Mon Feb 22 13:21:47 2010
From: mtang at stanford.edu (Mary Tang)
Date: Mon, 22 Feb 2010 13:21:47 -0800
Subject: Warning: No CF4 gas
In-Reply-To: <4B81330F.8080509@stanford.edu>
References: <4B81330F.8080509@stanford.edu>
Message-ID: <4B82F56B.1020204@stanford.edu>
Hi all --
The CF4 cylinder has been replaced. Although the cylinder change is
routine and no problems are anticipated, staff have not yet run etch
rates. Please check before running your critical material and let us
know if you observe problems.
Your SNF Staff
Mary Tang wrote:
> Apologies everyone, but it looks like the CF4 cylinder has run dry.
> This affects drytek1/2, mrc, p5000etch, pquest, sts (dep) and
> lampoly. We will address this as soon as possible.
>
> Your SNF Staff
>
>
--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang at stanford.edu
http://snf.stanford.edu
From mtang at stanford.edu Mon Feb 22 14:04:59 2010
From: mtang at stanford.edu (Mary Tang)
Date: Mon, 22 Feb 2010 14:04:59 -0800
Subject: Wafers in ChB MUST have 5 mm EBR
Message-ID: <4B82FF8B.3090502@stanford.edu>
Dear p5000etch users --
Several of you have suffered wafer handling problems, particularly in
ChB. Please be reminded that wafers to be processed in ChB using
photoresist masks should have all resist removed from the outer 5 mm of
the wafer. This can be most easily accomplished using the EBR program
on the SVG Coat: make sure to use a program that specifies 5 mm of EBR
(some are set at 2 mm, others may have backside rinse only.)
It has been suspected here and Applied Materials has confirmed that resist
can contaminate the clamp fingers which press down on the wafer edges onto
the helium backside seal on the chuck. The tiny fingers exert a lot of
pressure to ensure a good seal; they can easily pick up resist in contact
and become contaminated. This is probably especially true on ChB where
the temperatures run higher, especially during long etches. When the
fingers become contaminated, they can become sticky, which can interfere
with wafer handling.
There are many possible reasons for wafer handling problems. But this
one is preventable. If everyone is diligent, we will have one less
reason to worry about.
Thanks for your attention --
Your SNF staff
--
Mary X. Tang, Ph.D.
Stanford Nanofabrication Facility
CIS Room 136, Mail Code 4070
Stanford, CA 94305
(650)723-9980
mtang at stanford.edu
http://snf.stanford.edu