Testing a given circuit is a very important issue in todayOs situation due to high test cost. Tester
mainly focuses on power dissipation and test data volume. Compression technique is implemented to reduce
test power which causes the chip failure and is also used to reduce test data size. This study discusses reduction
of test data and scan chain shift-in power. Proposed method on compressing test data is done by threshold
method for unspecified test patterns. Appropriate indexing and encoding is done in this method. An analysis
of shift in power is carried out for encoded compressed pattern by considering its switching activity.
Experimental results prove that the proposed method can produce rapid reduction in test data volume and shiftin
power.