This course is an
introduction to Computer-Aided Logic Design. This is a highly active research
area, enabling the design of increasingly complex digital systems. In this
course we will mainly focus on three areas - specification, synthesis, and
optimization. We will look at how to specify functionality at a variety of
abstractions, use industry-standard tools to simulate these designs,
investigate some of the underlying optimization techniques utilized, as well as
develop your own tools. Topics include, but are not limited to (1) Register-Transfer
Level (RTL) Design, (2) Behavioral Synthesis, (3) Optimization and Tradeoffs of
Combinational and Sequential Circuits, (4) Exact and Heuristic Minimization of
Two-Level Circuits.

Students will be
expected to implement a variety of Verilog and C/C++ projects throughout the
semester. While specific programming assignments may change with the course
offering, projects typically focus on the implementation of optimization and
synthesis methods discussed in class, as well as the RTL design.

Prerequisite(s):

ECE 275

Textbook(s):

No textbook is required. The class notes/slides are
sourced from the following materials:

Understand the difference between heuristic and exact optimization methods, and be able to classify a variety of algorithms into these categories.

Use the Quine-McCluskey tabular minimization technique for identifying all the prime implicants, and solve the covering problem using Petrick’s method to find an optimal two-level implementation, for both completely specified and incompletely specified logic functions.

Use Quine-McCluskey with iterative and recursive consensus methods for identifying all the prime implicants (complete sum), and solve the covering problem using row/column dominance to find a minimal gate, two-level implementation, for both completely specified and incompletely specified logic functions.

Understand how generalized optimization algorithms can be adapted to the logic minimization problem.