Addressing the Challenges with SoC Integration and Verification

As a society entrenched in connectivity, we put a great deal of pressure on our portable electronic devices to provide us with more and more computing power and capabilities. Take this blog for example. As I’m traveling, I’m actually writing this blog post on my smart phone. To write this effectively, I need to be able to easily flip back and forth between PowerPoint, Word, and the Internet while still answering emails and the occasional phone call. The fact that my mobile device is able to handle all of these requests with no errors is astonishing given that just a few short years ago, this idea was just “pie in the sky”. The computation complexities that make this possible are staggering. But what is also staggering, is that even more complex designs are being created in ever shrinking time-to-market windows. How do system and SOC companies remain competitive with these seemingly unrealistic expectations?

There are, of course, a myriad of answers to that question, but a critical facet is the use of third-party IP. More and more companies must adopt third-party IP so that they can focus their design on their companies’ core competence. Outsourcing other, proven, capabilities to IP providers saves a great deal of time, energy, and money. However, the use of this third-party IP also introduces new challenges for interface specification, integration, and verification of SoCs on a large scale. These challenges, if not addressed properly, can eliminate any of the productivity gains thought to be realized with the use of third-party IP.

Designers must be able to easily integrate third-party IP (often from multiple sources) into their designs with minimal or no errors. The reality is that this type of integration is very time-consuming and error-prone. What’s needed is a flow that enables design teams to quickly and accurately detect issues, inconsistencies and omissions when assembling their complex Semiconductor IP (SIP)-based systems. A flow that allows designer to work form black-box IP specification, through architectural capture and SoC assembly, to verification is critical. Development teams must be able to verify the correctness of both the specification and the implementation, while also detecting inconsistencies in the specification.

Jasper Design Automation and Duolog Technologies have linked their tools and methodologies to create a flow that addresses these requirements and that has been utilized successfully by ARM, Ltd.

ARM uses Duolog’s Socrates Weaver to rapidly assemble highly sophisticated and configurable sub-systems and systems. In addition to Duolog’s Weaver, ARM also uses Jasper’s Connectivity Verification App to verify interconnectivity of these systems. Weaver, using a rules-based methodology, offers an extremely efficient and quick method of assembling and connecting sub-systems and top-level SoC. The result is compressing IP integration activities into days compared to weeks. It also enables a high degree of configurability and the ability to create a chip netlist, from one of thousands of options, in just a few minutes. Jasper’s Connectivity App, leverages Jasper’s formal technologies to verify RTL connectivity at the block, or chip level. Duolog, Jasper and ARM are collaborating closely, leveraging the IEEE1685 IP-XACT standard to integrate these tools and flows together seamlessly. The resulting collaboration provides unified high-level specifications that capture design intent to drive both these design implementation and verification flows.

Jasper and Duolog have initially introduced two flows:

Capturing and verifying register metadata that will enable SIP designers to verify the executable specifications against the RTL for consistency and completeness.

Enabling SoC design teams to assemble, construct and exhaustively verify a complete SoC integration, including temporal and conditional connections, as well as multiplexed IO connections.