Press Releases

AMD supports industry-standards like UVM that improve interoperability while reducing cost and effort. Industry UVM tools and methodologies are now widely used across AMD to drive consistency across IP test benches, reuse from IP to SoCs, affordable third-party VIP (Verification Intellectual Property), and improved documentation while also increasing our ability to readily hire experienced methodology engineers. The contributions of key industry domain experts have resulted in a high-quality UVM standard with broad industry adoption. Moving the UVM standard to the IEEE will stabilize and mature the standard for even broader implementation.-- Warren Stapleton, Sr. Fellow Design Engineer, AMD

Cadence Design Systems

“The rapid growth of UVM is a result of strong collaboration among the working group members and the electronics community. Cadence was honored to serve a leading technology role in the working group during the UVM standard development in Accellera. We will continue to actively participate in this user driven activity as it transitions to the IEEE P1800.2 working group.”-- Stan Krolikoski, Distinguished Engineer Cadence Design Systems

Mentor Graphics Corporation

Congratulations to Accellera and the UVM Working Group for reaching this pinnacle. UVM’s global adoption has truly unified verification to become the dominant method to advance verification productivity. We are pleased to see ongoing maintenance and standardization move to the IEEE as a natural part of UVM’s evolution by Accellera. The move to the IEEE will boost its global adoption and support. Further, it will drive stability to promote greater interoperability. -- Dennis Brophy, Director of Strategic Business Development, Mentor Graphics Corporation

NVIDIA

NVIDIA is pleased that UVM will become an IEEE standard. UVM is already an important part of the verification landscape. Bringing it under the IEEE umbrella will ensure its stability and longevity, and provide the global visibility needed to take its place as the de facto platform for simulation-based verification.-- Mark Glasser, Verification Architect, NVIDIA Corporation

Synopsys

Synopsys applauds Accellera’s continued efforts to standardize verification methodology on System Verilog. Accellera’s interest in contributing its UVM standard to IEEE 1800.2 is a clear indication of the maturity of the standard and the global collaboration by the verification community. Synopsys will continue to support these efforts through the participation of its verification methodology experts just as we have been the founding member and the leading contributors to Accellera’s UVM efforts for the past six years.-- Yatin Trivedi, Director of Standards and Interoperability Programs, Synopsys, Inc.