Intel has a major ’06-’07 weak spot, and AMD is aiming right at it

There's no doubt that Intel's Yonah and its successors will scream--scream …

Anyone who reads our Ars System Guides, or the front page for that matter, knows that AMD has had the price/performance edge over Intel for quite some time. And ever since Intel's Pentium 4 architecture ran smack into the power wall and stopped scaling, the Hammer architecture has had an outright performance edge in the x86 desktop and server spaces. So the fact that Intel has been trying to play catch-up to AMD technology-wise in the x86 market is widely known.

This past year was especially hard on Intel, but the company has been touting 2006 as the year they get their act together. The CES launch of Yonah, the corporate rebranding, the new platform initiative, the high-profile Apple deal, and the launch of the Merom/Conroe architecture later this year are all supposed to put Intel back on top in terms of performance, marketing, mind-share, and core technology.

So by the second half of 2006, Intel will have all plugged all of the chinks in its armor and the company's x86 flagship processor line will be once again ready to go forward and retake any ground that has been lost to AMD... or will it?

In spite of the fact that Yonah and its successors are going to be great CPUs that will deliver industry-leading performance/watt numbers, Intel has one giant hole in its '06-'07 lineup: interconnect technology. Intel has failed to deliver on a next-generation multiprocessor FSB spec, and that's why AMD's plans to license coherent HyperTransport to other chip vendors could spell trouble for Intel in the coming year.

CSI goes AWOL

One of the worst pieces of news to come out of Intel's October roadmap reorganization was the fact that the introduction of the company's long-planned Common System Interconnect technology would be postponed. CSI is the "HyperTransport killer" that's supposed to let Xeon and Itanium processors share the same system hardware. So CSI-based motherboards will be able to accept either a Xeon or an Itanium chip in their CPU socket with only a BIOS tweak.

CSI isn't here, though, and it won't be here this year either. Intel's next-generation x86 processors are therefore stuck with an antiquated, shared-bus interconnect topology that's bandwidth-starved, expensive, not scalable, and inferior to coherent HT in every respect.

This is bad news for those of us who're pumped about Merom/Conroe, because—as any Apple fan who uses a G4 can tell you—you can have the baddest processor on the market, but if you're starving it by sticking it on an outdated FSB then a lot of potential performance is going to waste. (Oh yes indeed my fellow Mac users; Apple is poised to have a repeat of the G4's infamous FSB bottleneck shortly after the switch to Intel. Look on the bright side, though: the situation won't be quite as dire... at first.) Furthermore, this problem gets worse rapidly as you increase the number of cores per socket.

That's why AMD's plans to license coherent HT are a big deal. In 2006, AMD will no longer be sitting on a processor architecture that's superior to Intel, but they will be sitting on a processor interconnect technology that's miles ahead of what Intel is offering.

AMD's coherent HyperTransport protocol

In a recent interview, AMD CTO Phil Hester discusses AMD's plans to license their multiprocessor interconnect technology, coherent HyperTransport (HT). Before we talk more about that, though, it's important to note that Coherent HT is different from regular HT. Coherent HT is a special, enhanced flavor of HT that AMD uses to connect its Opteron processors to each other in SMP systems. Coherent HT lets the Opteron do "glueless SMP," which means that two or four Opterons can all talk to each other via HT links without the need for a northbridge to route the data between them. On of the things that the coherent HT protocol enables is cache coherency among the processors, hence the name.

The take-home point here is that coherent HyperTransport is an SMP-specific flavor of HT that AMD uses for gluelessly ganging together multiple Opterons in SMP systems.

AMD plans to license this technology, so that third-party chipmakers can create specialized coprocessors that could be dropped into a coherent HT socket and begin working gluelessly with the other Opterons in the system. The example that Hester gives is a Java + XML accelerator chip that's dropped into one socket of a multi-chip Opteron system. So you could build a datacenter web server with, say, an Opteron in one socket and a Java + XML coprocessor in another.

AMD would love to see coherent HT become widespread enough and generate enough momentum that Intel would be forced either to switch to HT or risk losing even more server market share. AMD will press their interconnect-based performance and scalability advantage just as hard as they've pressed their architecture-based performance advantage this past year. Whether or not they can leverage coherent HT to the same extent that they've leveraged Hammer remains to be seen. But there's no denying that there's a gaping, HyperTransport-sized hole in Intel's upcoming processor lineup, and AMD is hoping to party like it's 2003.