DAC Day Two: Down To Business

DAC day two started with a breakfast presentation put on by Synopsys which included guests from ARM, TSMC and HiSilicon. It was titled Collaborating to Enable Design with the latest processors and finFET processes. Collaboration is a word that we hear increasingly when talking about the advanced nodes and today we are truly at the point where one company cannot do it all.

Ron Moore, VP of marketing at ARM, talked about development of the Cortex A73 processor and what collaboration means. He mentioned the need to keep improving the performance of the memory and the need to focus on power and thermal characteristics of the core. Moore said that collaboration gives the EDA vendor a two-year head start to make sure their customer can get the best PPA when the core is used within an end user design.

Chris Schreppel, staff design consultant within the Synopsys professional services group outlined several things they had learned which could result in users gaining better productivity or avoiding problems. One area in which new development was required was to be able to effectively utilize the multi-bit cells. This results in power reduction and simplification in areas such as reset and routability.

Willy Chen, deputy director of design technology with TSMC talked about the status of 10nm and 7nm. The biggest difference is that 10nm requires full coloring and he provided examples of how this works in practice. While mobile has been the biggest driver for the advanced nodes, high performance computing is a new driver for 7nm. “7nm is a further extension of 10nm technology,” said Chen. “We have 20 customers in design engagement and 15 tapeouts expected in the first half 2017. They can expect to see 60% area shrink and 40% power reduction. One area that will require different techniques are in clock tree design. Another area is the need to remove excessive margins.”

Ron Preston, senior principle engineer at ARM talked about optimization in the face of increasing problems. He said that this requires a bidirectional flow from process upwards and from system design downwards. He talked about one example of bottom up communications from a finFET attribute that enables foundries to make taller finFETs and in order to optimize the design, the fins may need to be depopulated. These are defined in the library cells and different cells have to be considered but there are implications of these choices in various parts of the flow.

This was followed by the first of the DAC keynotes. Lars Reger is the CTO of the automotive division of NXP and you can expect a full report on the keynote shortly. Connectivity, automation and energy efficiency are the three things that are driving automotive semiconductors these days and there are many disruptions happening that are making cars a robot on wheels. Reger says it is all about saving lives and saving the planet.

The two blocking issues for self-driving cars today are functional security and functional safety. ISO 26262 is being developed to address the functional safety issues and requires zero failures caused by system failures. “We are no longer driven by Moore’s Law but by being able to think about car systems in different ways,” says Reger. “What would happen if you could have a complete CMOS radar chip? Then when you can put enough of them together a complete radar cocoon becomes possible.”

The keynote was well received and the room was standing room only. Another opportunity for food and learning was provided by Synopsys. This time, the subject was Robust AMS Design Verification at Advanced Nodes and Samsung, Oracle, STM and Qualcomm participated.

Zach Coombes, a CAD engineer for Samsung talked about the increasing challenges that have been put on memory simulation and power grid support since the 90s and the transitions that have been required in the tools including overcoming some of the early challenges with finFET simulation. Sam Lo, hardware development manager from Oracle talked about dealing with end-to-end security with always on memory. His presentation covered a lot of detail about how to do this and the simulation options required. Atul Bhargava, senior staff engineer at STM talked about IP development challenges and the need for Monte Carlo simulation. He talked about the tradeoffs between accuracy and simulation performance and how to make the best tradeoffs. Bramha Marathe, director of engineering in the central verification and validation team within Qualcomm, talked about the advances they are making by extending coverage-driven constrained random verification methodologies into the analog and mixed-signal domain.

At the same time Cadence was talking about connecting verification engines together and some of the problems associated with this. The lunch session concentrated on software-driven verification, one of the most important verification technologies under development today.

The afternoon was spent talking to many vendors about a bunch of new product announcements, standards groups, such as the MIPI Alliance, and running roundtables that will appear here in the weeks to come.

The late afternoon reception was coupled with DAC’s first ever art show, which contained plots, thermal heat maps and other imagery created during construction of systems and chips. Semiconductor Engineering’s Ed Sperling was one of the judges and the winners will be announced on Wednesday. The day was completed with a raucous evening with Mentor Graphics who chose to provide a set of drum sticks for everyone on their tables for the entertainment after dinner and copious amounts of wine. Let’s just say that a lot of fun was had.

Related StoriesDAC Day One
Is the glass half full or half empty? The same can be said of opportunities within EDA, but it depends which glasses you have on.DAC Day Three
An action packed day at DAC where all extremes of the EDA problem space can be covered under one roof.DAC Day Four
Art, a fire in the exhibit hall, risk management and team advice, car races and notions of open-source hardware.