We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Firefox,
Internet Explorer 11,
Safari. Thank you!

AR# 58025

Description

When I run Vivado Synthesis on my design, I receive the following message:

INFO: [Synth 8-3967] The signal mem_reg was recognized as a RAM template but could not be mapped onto a dedicated block RAM for the following reason(s): The *asynchronous read* does not match a dedicated block HDL RAM template.

The read address is actually registered, so it is synchronous read but it has a sync reset on it.

What is the root cause of the issue? Is the feature supported?

Solution

The synchronous reset on the read address register is the root cause of the block RAM inference failure.

Vivado Synthesis does not currently support this feature.

The INFO message is misleading here as the read address is actually synchronous but Vivado Synthesis fails to extract it due to the reset.