Ronen Stilkol

Power grid verification is considered as a challenge since no industry standard that if the design team is following will result in a proof power grid for power and signal integrity issues, in other areas there is a verification plan with many checks need to be performed and when all are done successfully the design is considered verified and can continue to TapeOut.

Having a high coverage in power grid power and signal integrity means that the design after TapeOut is not exposed to a logic failure due to a critical timing path that was violated, or an analog design that became not functional because it got a noise level which is way beyond it's specifications, another failure aspect is a jitter violation which can cause a logic failure, but before that is can cause a violation of jitter target on the DDR chip clock pin.In this paper a verification flow to get a high power grid verification coverage will be presented, while keeping low effort and catching the design weak point early in the design cycle.

Given the complexity of present day’s System-on-chip (SoC) designs, higher resistance of the power and ground meshes, increased device density, and the greater sensitivity of the metal structures to breakdown in the sub micron technology nodes, the proper design and placement of ESD protection circuitry has become quite critical.