Repeater insertion is one of the most widely used techniques to reduce the signal propagationdelay on global interconnects. The number of repeaters inserted into interconnects is expectedto be enormous due to the ever-increasing chip dimension. The huge number of repeaters cantake up signicant silicon area and consume a lot of power. Consequently, minimization of powerconsumption of repeaters with timing closure constraints is a very important problem in future lowpowerVLSI design.In this dissertation, we investigate efcient schemes for low-power repeater insertion on globalinterconnects. We rst analyze key issues on repeater library design by introducing an analyticallow-power repeater insertion algorithm for uniform two-pin interconnects. Our study leads to.