AMD is expected to release its 65nm products soon. Moving
beyond the 65nm Brisbane
die shrink and Windsor FX,
AMD has a couple of other tricks up its sleeves. AMD plans to transition from
its Cities core products to new Stars cores. This transition uses
AMD’s new core naming scheme. While AMD has typically named its processor cores
after cities, the new naming scheme uses star names.

The Stars family includes the upcoming Agena FX, Agena, Kuma, Rana and Spica cores. AMD
will be introducing plenty of architectural changes with the upcoming Stars
family. Stars family processors will switch over to AMD’s previously announced
HyperTransport 3.0 architecture. Previously, Star processors have been referred to as Revision H or K8L -- if that's not confusing enough, AMD calls the architecture of the Stars family Greyhound. While Stars family processors use the
HyperTransport 3.0 protocol, it will be backwards compatible with
HyperTransport 1.0 systems.

HyperTransport 3.0 is expected to provide twice the amount of bandwidth between
the processor and chipset. It will also allow the processor and internal north
bridge to operate at different frequencies as well. With HyperTransport 3.0,
the north bridge can operate at 75% of the maximum clock frequency of the
processor. AMD roadmaps claim the greater bandwidth of HyperTransport 3.0 is
important for PCIe 2.0 and upcoming multi-GPU, integrated graphics and
multiprocessor performance.

In addition to HyperTransport 3.0, Stars family processors feature a
128-bit floating point unit for each CPU core, DDR2-1066 support, SSE4A instructions
and a split power
plane. Split power planes allow the processor and internal north bridge to
operate at different voltages and speeds. The advantages of split power planes
are it allows the north bridge speed and voltage to never change during
Cool’n’Quiet power saving measures. With split power planes the Stars
processors require separate PLLs for the processor and internal north bridge.

Stars family processors will use socket AM2+, with the exception of the Agena
FX. Nevertheless, Stars family processors will be backwards
compatible on socket AM2 motherboards, though performance is sacrificed by
falling back to HyperTransport 1.0. AMD's documentation no longer refers to AM3; it appears AM2+ is the expected socket AM3.

Beginning in Q3’2007 AMD is expected to release its first Stars
quad-core processors. The new quad-core processors are based on AMD’s Agena
and Agena FX cores. Targeting AMD’s 4x4 platform is the Agena FX
core. Agena FX will only be available on Socket 1207+ and offer dual
processor functionality. The vanilla Agena core will be available on
single processor socket AM2+ platforms.

Agena FX and Agena based processors offer identical features. New
to the Agena FX and Agena cores is a shared L3 cache. 2MB of L3
cache will be shared between all four processor cores. The L2 cache will be 2MB
as well. Clock frequencies of 2.7 GHz to 2.9 GHz are initially expected. The
HyperTransport 3.0 frequency for Agena FX and Agena cores is
expected to be clocked at 4000 MHz. Agena FX and Agena core
processors will be manufacturing using a 65nm process and carry 125W TDPs. The
first Agena FX and Agena based processors are expected to arrive
in Q3’2007.

AMD will be releasing new Kuma core dual-core processors in Q3’07 as
well. The new Kuma core processors feature HyperTransport 3.0 clocked at
4000 MHz, 1MB of L2 cache and 2MB of shared L3 cache. Kuma processors
are expected to arrive in 2.0 GHz to 2.9 GHz frequencies for socket AM2+. TDP
for Kuma core processors is expected at 89W and 65W.

Single-core products won’t be left out of the Stars family either. AMD
will release single-core Rana and Spica cores towards the end of
2007. Rana core processors will be replacing Orleans and Lima
Athlon 64 single-core processors while Spica will be replacing
single-core Venice Athlon 64 and Manilla Sempron processors.
AMD’s roadmap doesn’t reveal too much on Rana and Spica.
Nevertheless, Rana and Spica will feature HyperTransport 3.0 and
socket AM2+ compatibility.

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