I have been studying for a final exam and one of the exam style questions include designing a sequential circuit. I am only stuck on the very beginning when I have to design the state diagram and state table. The question that is asked is as follows:

Design a sequential logic circuit whose output Z is 1 except when the input X = 1 for at least four clock periods. Then the output Z is 0. Use J-K flip-flops.

I don't understand how I am to go from this question to the state diagram that is given below where later on he describes:
A = 00
B = 01
C = 10
D = 11

There are four states {A,B,C,D} that are encoded with two JK flip-flops. These two JK flip-flops can be in any one of four states {00,01,10,11}. Now it should be fairly obvious that you can map the letters from the set {A,B,C,D} onto the the set of binary numbers {00,01,10,11}

From the present state and the present input you need to compute a next state and an output according to the diagram. the paper part of this design is easy. Realizing it in hardware is just a bit more challenging.

There are four states {A,B,C,D} that are encoded with two JK flip-flops. These two JK flip-flops can be in any one of four states {00,01,10,11}. Now it should be fairly obvious that you can map the letters from the set {A,B,C,D} onto the the set of binary numbers {00,01,10,11}

From the present state and the present input you need to compute a next state and an output according to the diagram. the paper part of this design is easy. Realizing it in hardware is just a bit more challenging.

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Hi I just realized I made a mistake in my original post by not saying that the state diagram is not given in the exam. The state diagram is what I have to compute from the question alone and that is where I'm stuck. The attached state diagram is one that has already been worked out, but is not given in the question. What I don't understand is how to compute the next state and output without the state diagram/table.

The state diagram and the state transition table are two representations of exactly the same thing. You have a behavioral description of what the state machine is supposed to do. Can you imagine a machine that is in some state after a very long string of inputs which are 1's. As long as the input is a 1 it stays in that state. As soon as there is an input of a 0, it goes to a state which stays in that state as long as there is a zero on the input. When the input returns to a 1 it takes four clock cycles to get back to the original state so you can output a 1. Any 0 input takes you back to the state where it takes 4 inputs equal to 1 to get you back to the initial state. That is how I interpret the verbal description