Dates:
October 5, 2006
Venue: SEMI Headquarters, Click on each presentation to viewLow Power Workshop
Abstract:Low
power design has been identified as a critical area for design flow
improvement in the 65nm regime and beyond. This workshop, lasting a
day, is intended to serve as an open forum for key contributors from
EDA and end-user companies to identify the critical needs in the area
of low power design, verification and analysis of integrated
circuit chips. The goal is to first assimilate requirements from a
varied group of presenters from end-user design companies representing
requirements to satisfy the needs of microprocessor, SoC and AMS chip
designs. Subsequent discussions will be held among the participants at
the workshop to enlist the work content and responsibilities, and to
identify the specific areas (language extensions, library standards,
design constraints, flow interfaces, etc) where standards need to be
created or extended to enable an open environment for more advanced low
power design flows and capabilities. Agenda:09:00am - 09:10am: Introduction,John Ellis,
SEMI and Steve Schulz, Si2