HI all,I have to read the file inputs,outputs,regs,always..of verilog file in the perl and print all the read things ie(inputs,outputs...)into differant corresponding files named correspondingly.I had a code for this one.But what the problem here is my always file is showing empty.I attached my Perl code here,and also you can see the file that i have to read down the perl code.If u help me out i would be very glad to u.thanks

Code

#!usr/bin/perl

use strict; use warnings;

open (my $ip_fileh, '<', "pras.v") || die ("unable to open the file pras.v\n"); #open the file

always @ ( bmu_id or bmu_version or bmu_revision or csr_bmu_en or csr_bmu_sw_rst or csr_bmu_max_buf_cnt or csr_bmu_base_addr or csr_bmu_buf_size or bmu_active_buf_cnt or bmu_active_mcast_cnt or csr_bmu_ucast_thres or csr_bmu_mcast_thres or bmu_int or bmu_empty_int or bmu_full_int or bmu_thres_int or bmu_free_err_int or bmu_mcast_empty_int or bmu_mcast_full_int or bmu_mcast_thres_int or bmu_mcast_free_err_int or bmu_int_en or bmu_empty_int_en or bmu_full_int_en or bmu_thres_int_en or bmu_free_int_en or bmu_mcast_empty_int_en or bmu_mcast_full_int_en or bmu_mcast_thres_int_en or bmu_mcast_free_int_en or ucast_alloc_addr or ucast_free_addr or bmu_free_err_addr or bmu_curr_buf_cnt or paddr ) begin prdata = 32 'h0; if ((paddr [8 :7] == 2'b10 )&& data_ready) begin prdata [31:0] ={ csr_ucast_mem_rdata}; end else begin case (paddr[10:0])

Re: [per'l'over] Failed to read the particular block in the given file
[In reply to]

Can't Post

When I use your Perl code to parse your Verilog file, the 'always.txt' file is not empty, but it is incomplete. Your regular expression does not account for consecutive blank lines within an always block. One improvement might be to change your '\n\n' to '\n\n\n'. However, this will not account for 3 consecutive blank lines with your always block.

Verilog code is extremely difficult to parse. The best Perl tool I have found is the CPAN Verilog::Parser suite. It does a great job of finding module ports, but I have never tried to parse always blocks with it.

Obviously, if you could guarantee that your Verilog code were formatted more consistently, you would have an easier time parsing it.

PS. I realize I am replying to a question which is 1 year old (I just joined this forum). But, perhaps my answer will be of use to someone searching this forum.