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Abstract

Disclosed is a mechanism allowing a hardware Direct Memory Access (DMA) to transfer data and control block information for P1394 Isochronous Channels between Peripheral Component Interconnect (PCI) addressable memory space or transmit ping pong buffers and either a receive First In, First Out (FIFO) buffer or a register bank. The transmit ping pong buffers are for Transmit Isochronous Data, the receive FIFO is for Receive Isochronous Data, and the register bank is for Transmit or Receive Buffer Control Blocks. This mechanism is configured within a module performing a Link function, providing an interface between the physical layer chip for this serial bus and the PCI bus.

Country

United States

Language

English (United States)

This text was extracted from an ASCII text file.

This is the abbreviated version, containing approximately
32% of the total text.

Hardware Control of Isochronous Data Transfer between
P1394 and PCI
Busses

Disclosed is
a mechanism allowing a hardware Direct Memory
Access (DMA) to transfer data and control block information for P1394
Isochronous Channels between Peripheral Component Interconnect (PCI)
addressable memory space or transmit ping pong buffers and either a
receive First In, First Out (FIFO) buffer or a register bank. The
transmit ping pong buffers are for Transmit Isochronous Data, the
receive FIFO is for Receive Isochronous Data, and the register bank
is for Transmit or Receive Buffer Control Blocks. This mechanism is
configured within a module performing a Link function, providing an
interface between the physical layer chip for this serial bus and the
PCI bus.

This mechanism uses the Arithmetic Logic
Unit (ALU) and
dataflow to determine how to increment the addresses pointing to the
remaining data buffer available and to calculate a residual byte
count for use when data in an isochronous packet spans between two
data buffers. These calculations are
used to program the DMA
controller with the address and byte count of each sequential block
of isochronous data to be fetched from, or stored into, the PCI
-addressable memory. The mechanism is
also responsible for
programming the DMA controller with the appropriate address and byte
count for fetching control blocks for isochronous data buffers as
required. On receive operations, the
mechanism is responsible for
"backing up" to the state of the previous packet if an error is
detected in a packet for which data has already been transmitted to
PCI-addressable memory.

This
mechanism consists of several state machines.
Fig. 1
describes the state machine for fetching the initial control block
from PCI-addressable memory to bus to the register bank (receive or
transmit). Fig. 2 describes the state
machine for initiating a
receive packet data store from FIFO to PCI-addressable memory. Fig.
3 describes the state machine for fetching transmit packet data from
PCI-addressable memory to the ping-pong buffer.
Fig. 4 describes the
state machine for fetching the next control block in a chain. This
subroutine is used by other state machines.
Fig. 5 describes the
state machine for terminating receive packet operation and for
restoring the state prior to the start of a packet. This subroutine
is used if a packet error is detected after part of a packet is
stored in PCI-addressable memory. Fig. 6
describes the state machine
for completing the receive packet operation.
All of these state
machines can be made serially reusable, so that they can process
receive and transmit data for multiple channels. Yet another state
machine can be implemented to ensure that only one state machine
attempts to use the dataflow at one time, and to prioritize among
state machines contending for use of the ALU and dataflow resources.