The G-1 core stepping will not only be compliant with European Reduction of Hazardous Substances (RoHS) regulations, courtesy of a "lead-free second level interconnect", but add two new instructions to Intel's AMD64-like EM64T 64-bit addressing system.

Intel is adding the LAHF and SAHF AMD64 instructions to its own 64-bit instruction set architecture. It has been alleged that they were missing from the original EM64T specification because the AMD documents used by Intel's engineers pre-dated AMD's addition of the two mnemonics.

LAHF and SAHF two instructions copy content back and forth between a 64-bit x86 processor's status flags and its AH register.

Intel has already told customers it is adding LAHF and SAHF to certain Pentium 4 and Xeon DP processors. The P4s arrive on 14 November, the Xeons on 28 November.

The new-core chips are pin-compatible with old-core Celeron Ds, Intel said, but the new processors will require host systems to have their BIOS code updated. ®