Processor Architecture and Assembly Programming Training

Course Name
Processor Architecture and Assembly Programming Training

Course Overview
This course on Processor Architecture and Assembly Programming training focuses on the basic architecture, programming environment and instruction set of the processor and the opcode structure of Intel 64 and IA-32 processors.These training target operating-system and BIOS designers and addresses the programming environment for classes of software that host operating systems.

Target Audience

Application Programmers and Programmers who write operating systems or executives

Developers, Testers/QA and Verification Engineers who are working on or keen to know Processor Architecture and Assembly Programming

MANAGING STATE USING THE XSAVE FEATURE SET
XSAVE-MANAGED FEATURES AND STATE-COMPONENT BITMAPS
ENUMERATION OF CPU SUPPORT FOR XSAVE INSTRUCTIONS AND XSAVE-SUPPORTED FEATURES
ENABLING THE XSAVE FEATURE SET AND XSAVE-SUPPORTED FEATURES
XSAVE AREA
XSAVE-MANAGED STATE
OPERATION OF XSAVE
OPERATION OF XRSTOR
OPERATION OF XSAVEOPT
OPERATION OF XSAVEC
OPERATION OF XSAVES
OPERATION OF XRSTORS