Western Digital, Toshiba announce first 512Gbit 64-layer TLC 3D-NAND

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Western Digital and Toshiba have jointly announced that they have begun initial production on 64-layer 3D NAND in 512Gb capacities. This new pilot production at the company’s fab in Yokkaichi, Japan, is expected to ramp up to commercial volumes within the first half of 2017, with hardware arriving on store shelves not too long thereafter.

“The launch of the industry’s first 512Gb 64-layer 3D NAND chip is another important stride forward in the advancement of our 3D NAND technology, doubling the density from when we introduced the world’s first 64-layer architecture in July 2016,” said Dr. Siva Sivaram, executive vice president, memory technology, Western Digital. “This is a great addition to our rapidly broadening 3D NAND technology portfolio. It positions us well to continue addressing the increasing demand for storage due to rapid data growth across a wide range of customer retail, mobile and data center applications.”

Whether Samsung or Toshiba/WD are “first” to 64-layer NAND depends on whether you care to measure in technology press releases or shipping products. Neither company has, as of yet, actually shipped 64-layer NAND. Toshiba and Western Digital use what they refer to as Bit Cost Scaling (BiCS) technology, though the actual variations between this approach and the V-NAND manufactured by Samsung are unclear. Both Samsung and WD/Toshiba use charge-trap flash as opposed to a floating-gate — Micron is the only 3D NAND manufacturer using a floating-gate structure at this point in time.

The only other clue about BiCS is that it uses different materials in cell construction. Samsung’s V-NAND is built on SONOS — Silicon-Oxide-Nitride-Oxygen-Silicon, as opposed to using polysilicon. TANOS uses TaN, AL2O3, Si3N4, SiO2, and Si — which is probably why we call it TANOS in the first place. The benefits of this construction method have not been well explained; all of the firms working on 3D NAND have been quiet about what the specific benefits are of their particular approaches and technologies and have generally described them in only very general terms.

Reaching full commercialization of BiCS would be a significant step for Western Digital. The first BiCS, which Toshiba announced back in 2015, was a 48-layer pilot production product that never made it into shipping products. BiCS2 has supposedly been shipped to OEMs and customers, though I’m not aware of any SSDs that use it (this doesn’t mean nobody uses it; but low-cost OEMs or parts sold for system integration might not advertise the fact).

It’ll also be interesting to see how the reliability and performance metrics shape up for these new triple-layer cell products. Manufacturers like Samsung and WD are trying to get away from TLC, probably because the NAND type is known to have much lower performance and reliability compared with MLC. It’ll be interesting to see how many of these characteristics carry over to 3D NAND. Samsung uses its 40nm process for all of its current 3D NAND products, at least as far as we know, which means these 40nm TLC drives have, in some cases, reliability metrics that compare well against 20nm planar MLC NAND.

For now, we’re sticking with the TLC acronym to discuss both 2D and 3D NAND, since the term refers to the amount of data stored within each NAND cell, not any associated metrics related to reliability. Western Digital’s new 512Gb capacities also put it on par with Samsung, which announced similar capacities for its upcoming 64-layer 3D NAND, which is also expected to ship in 2017.

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