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Abstract

This is a shift register of n positions for use on each chip in large-scale integrated (LSI) chip technologies, with n number of signal I/O pads. The shift register stages are connected in such a way that the logic functions of the chip are performed independently of the shift register. The shift register is personalized on a part number basis to drive input pads and receive from output pads.

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United States

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English (United States)

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Shift Register Tester on a Chip

This is a shift register of n positions for use on each chip in large-scale
integrated (LSI) chip technologies, with n number of signal I/O pads. The shift
register stages are connected in such a way that the logic functions of the chip
are performed independently of the shift register. The shift register is
personalized on a part number basis to drive input pads and receive from output
pads.

The shiit register stage configuration used to drive input pads is shown in Fig. 1. The shift register stage configuration used to receive from output pads is
shown in Fig. 2. Seven additional I/O's per chip are required to operate the shift
register two shift controls, an input gate, an output gate, a data in, a data out, and
a power supply to disable the shift registers during normal chip operation. Fig. 3
contains a schematic of the shift register.

To perform a DC functional test, requires that the shift register stages that
feed input pads be loaded with the logical value to be applied at each pad. The
input gate pad is then activated, gating the input stimuli to the chip input pads.
After waiting for the logic under test to reach a steady-state condition, the output
gate pad is activated, gating the output responses into the appropriate shift
register stages. These values are then shifted out, recorded and then compared
to the predicted results.

An AC functional test is performed in the same fashion, except that the output
gate pad is act...