Elphel camera

10353 - processor board (computer part of the camera) uses ETRAX FS processor running GNU/Linux (currently kernel 2.6.19) that has support for multiple hardware interfaces with the following of them used/connected in the Model 353:

10/100 Ethernet

USB 1.1 (host)

IDE (ATA-6)

RS-232

Teridian 78Q2123 is used as Ethernet PHY in the camera - it has Auto-MDI/X, so no more crossover cables are needed when connecting camera directly to a PC.

64MB of 32-bit white system SDRAM provide memory to run multiple applications in the camera. It is also used as a buffer for video/images and as a RAM-disk.

128MB of system flash memory work a solid-state disk to boot the camera and provide it with the software. The JFFS2 file system allows writing to this "disk" data and updating the applications without the need to replace the whole flash memory image. As in the other Elphel products marked with /*source inside*/ logo, Model 353 holds all the source code (including FPGA and circuit diagrams) designed by Elphel. Combined with the other free software used in the camera (automatically downloaded when Elphel software is being installed) this code is completely sufficient to regenerate the camera flash image. Axis ETRAX FS provides built-in code to boot from the network and restore the contents of flash memory if it is lost/corrupted so re-flashing the camera is a completely safe procedure.

Xilinx (R) Spartan 3e 1200K gates FPGA is the highest density device available in the small FT256 package (that fits in the camera) and it carries most of the video processing/compression in the camera. All the FPGA code is provided under GNU GPL and with free for download development tools from Xilinx you may modify this part of the camera code similar to the software. FPGA registers are accessible by the software through a system bus, FPGA can also transfer data to the system memory using DMA access. In addition to the pseudo-DMA (the only method available in the earlier ETRAX 100LX) the 10353 board has circuitry to allow the FPGA to gain full control of the system bus and transfer data to the system memory up to 5 times faster.

Another 64MB of DDR SDRAM memory chip is connected directly to the FPGA and provides temporary buffering of the images needed for compression or processing. With the dedicated controllers and fine-tuned data structures this memory can provide an average data rate of 95% of the memory bandwidth of 0.5GB/sec.

Cypress programmable CY22393 3-PLL clock generator provides clock for the CPU and FPGA, all the frequencies can be adjusted when needed.