vlog-mode --- The verilog code maker

What and Why

vlog-mode is a powerful major mode for editing verilog sources in GNU
Emacs. (Yes, up to now for GNU Emacs only, because no XEmacs compatibility
test is made, though I'm hoping to have it made). It is designed to be a
free, open, powerful and fully customizable working environment for those
who deal with verilog a lot.

Then why Emacs? Emacs is a powerfull editor available under nearly all
OS on all hardwares, esp. on those EDA platforms such as GNU/Linux on x86
or Solaris on Sparc. So the answer is: Emacs is powerful (not "powerful
enough" but "cannot be more powerful") and cross-platform (or in geeks'
words, Emacs is a platform itself).

Well, then why anothor major mode?
verilog-mode is a
long-history major mode for verilog, but it's not very open and not good
enough for me. So I decided to write a brand-new, more open, more
customizable and more powerful one, and then open it to the users'
community. Everyone is welcom to make suggestions, send bug reports or
feature requests, etc. No single person or organization controls the
codes. We will have OUR vlog-mode, not "crazycool's vlog-mode". It belongs
to the community, everyone in this community is welcom to make
contributions.

Featurs

Verilog 2000 support (optional).

Colorful syntax highlight (screenshot), keywords customization.

Fully configurable code indentation and alignment.

Convenient typing assistants.

Module instantiation assistants. (In progress...)

Automatic sensitive lists generation.

Signal width detection.

Configurable signal list in imenu and speedbar (screenshot).

Error message capture for various simulators, linters and other tools under compilation mode.

Codes folding.

Smart skeletons.

Jump between block beginning and end (begin/end, fork/join, case/endcase...), also from else to if

And many more...

Changelog

From 1.6 till now

More powerful (yet quite configurable) code alignment support through the use of align.el. (align.el has been included in GNU Emacs since 21.4 release.)

Various minor bug fixes.

From 1.4 to 1.6

Verilog 2000 support.

ANSI C style port declaration support.

Signal list (imenu and speedbar) support.

Jumping between block beginning and block end, also from `else' to correspoding `if'.