Author Bio

Bert Simonovich was born in Hamilton, ON, Canada. He received his Electronic Engineering Technology diploma from Mohawk College of Applied Arts and Technology, Hamilton, ON, Canada in 1976. Over a 32-year career, working as an Electronic Engineering Technologist at Bell Northern Research and later Nortel, in Ottawa, Canada, Bert helped pioneer several advanced technology solutions into products. He has held a variety of engineering, research and development positions, eventually specializing in signal integrity and backplane architecture for the last 10 years. He is the founder of Lamsim Enterprises, Inc., where he continues to provide innovative signal integrity and backplane solutions to clients as a consultant. With three patent applications and two patent grants to his name, Bert has also (co)authored several publications, including an award-winning DesignCon2009 paper related to PCB via modeling. His current research interests include signal integrity, high-speed characterization, and modeling of high-speed serial links associated with backplane interconnects

Practical Modeling of High-Speed Backplane Channels

As Dave Dunham of Molex Corp. likes to say, "When designing high-speed serial links beyond 10 GB/s, everything matters." And part of that everything is accurate modeling of transmission line losses.

Failure to account for conductor roughness can ruin your day, especially if you are trying to push 28 GBaud/s (56 GB/s) PAM-4 signaling down your channel. To ensure first-time success at these speeds, using the right parameters for dielectric and conductor roughness to feed into modern EDA tools is a prerequisite. This is especially true for long backplane channels.

Many EDA tools include the latest and greatest models for conductor surface roughness and wide-band dielectric properties. But obtaining the right parameters to feed the models is always a challenge. So how do we get these parameters?

One way is to follow the design feedback method which involves designing, building and measuring a test coupon. After modeling and tuning various parameters to best fit measured data, Dk, Df and roughness parameters can be extracted. They are then used in channel modeling software to design the final product.

The benefits of this method are that it is practical and accurate—if you use the exact same material, glass style and copper foil in your final board stack-up. On the down side, a significant amount of expertise and equipment is required to design, build and measure the test coupon, which takes significant amount of time and money.

To read this entire article, which appeared in the October 2017 issue of The PCB Design Magazine, click here.

2017

As Dave Dunham of Molex Corp. likes to say, "When designing high-speed serial links beyond 10 GB/s, everything matters." And part of that everything is accurate modeling of transmission line losses. Many EDA tools include the latest and greatest models for conductor surface roughness and wide-band dielectric properties. But obtaining the right parameters to feed the models is always a challenge. So how do we get these parameters?

You know you have an obsession when you are flying six miles over Colorado and you look out the window at the beautiful scenery, and all you can think about is how the rocky mountain topology reminds you of conductor surface roughness! Well, call me obsessed, because that’s exactly what I thought on my way to DesignCon 2017. This year at DesignCon, I presented a paper titled "A Practical Method to Model Effective Permittivity and Phase Delay Due to Conductor Surface Roughness."

2016

Originally, Bandini Mountain referred to a mound of fertilizer built by the Bandini Fertilizer Company in California prior to the 1984 Los Angeles Olympics. When the company went bankrupt, this mound of fertilizer was left behind. Steve Weir coined this term to describe the large resonant frequency peak formed by the parallel combination of the on-die capacitance and the package lead inductance, as seen from the die looking into the PDN.

2014

Columnist Bert Simonovich writes, "Last year, Dr. Eric Bogatin, the 'Signal Integrity Evangelist,' announced the end of his famous signal integrity classes. At the time I remember thinking to myself, 'What's next for Eric?' If you know Eric, like I do, you realize that the end of one phase of his career usually means the start of the next one. And now we know what that is."

Columnist Bert Simonovich writes, "Last year, Dr. Eric Bogatin, the 'Signal Integrity Evangelist,' announced the end of his famous signal integrity classes. At the time I remember thinking to myself, 'What's next for Eric?' If you know Eric, like I do, you realize that the end of one phase of his career usually means the start of the next one. And now we know what that is."

2013

Some claim that a guard trace should be shorted to ground at regular intervals along its length using stitching vias spaced at 1/10th of a wavelength of the highest frequency component of the aggressor's signal. But others believe separating the victim trace to at least three times the line width from the aggressor is good enough. Bert Simonovich addresses both arguments.

Some claim that a guard trace should be shorted to ground at regular intervals along its length using stitching vias spaced at 1/10th of a wavelength of the highest frequency component of the aggressor's signal. But others believe separating the victim trace to at least three times the line width from the aggressor is good enough. Bert Simonovich addresses both arguments.

2012

Popular opinion has held that PCB vias were mainly capacitive in nature, and therefore could be modeled with lumped capacitors. Although this might be true when the rise time of the signal is greater than or equal to 3x the delay of the via discontinuity, I'll show you why it is no longer appropriate to think this way.

I was intrigued by a DesignCon 2010 paper presented by Dr. Nicholas Biunno on a new matched terminated stub technology developed by Sanmina-SCI Corporation. The company calls this technology MTSvia, and it allows the embedding of metal thin-film or polymer thick-film resistors within a PCB stackup during fabrication. Personally, I like to call this technology the "Stubinator."

In my previous column, I touched briefly on the concept of backplane high-level design (HLD). For any new backplane design, I always recommend starting with a HLD. It helps you capture your thoughts in an organized manner, and later provides the roadmap to follow for detailed design of the backplane. This week, I will touch on key aspects that go into this process.

2011

I am often asked what I do for a living. When I say high-speed signal integrity and backplane architect, the next question is usually, "What is a backplane architect?" By my definition, a backplane architect is any person who plans, devises or contrives the achievement of a backplane design. And the earlier you consider the backplane's physical architecture, the more successful the project will be.

A couple of times this year, fiber weave effect timing skew came up for discussion on the SI-List that many of us subscribe to. This is becoming more of an issue for many designers as bit rates continue to soar upwards. For signaling rates of 5GB/s and beyond, it can actually ruin your day. So what is fiber weave effect anyway, and why should we be concerned about it?

So, why do we need to study PCB cross-sectional geometries? Because they describe the details of the dielectric substrates, traces and reference planes in a PCB stackup. Their relationship to each other is used to predict the characteristic impedance and interaction of the respective traces. Understanding these geometries can help you determine odd-mode and even-mode impedance, average and differential impedance, crosstalk and more.

In my last column, I discussed the twin-rod model. Now I'll explain how a twin-rod transmission line model can be the basis for a practical differential via circuit modeling technique and a simple alternative to a 3D field solver. This method can yield an approximation much faster than a field solver, and when you need a rough estimate, this via modeling method may be just what you need!

In almost all cases, equations used to calculate the loop inductance and capacitance of transmission lines are approximations. However, there are three unique cross-sectional geometries that have exact equations: Twin-rod, rod-over-plane and coaxial. I've dubbed them "The Three Amigos." Get to know them -- they can be your friends.

I subscribe to the SI-List forum on signal integrity. People often pose the question, "How do you find the driver impedance information from the IBIS file?" Most of the time we want this information so that we can explore mitigation techniques to control reflections caused by impedance discontinuities of the transmission path. Let's look into IBIS output impedance.

Over the years, I have held a variety of hardware design engineering positions and pioneered several advanced technologies into products. After all this time as an engineer, I still have the passion I had as kid to learn and understand new things. This column is about sharing some of that passion.