Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents. 2. 100pF through MIL-STD-883C, 3015.7

Mode Standby Output Disable Write Disable Read Write

PIN DESCRIPTION Addresses (A0-A10). The address inputs select an 8-bit memory location during a read or write operation. Chip Enable (E). The chip enable input must be low to enable all read/write operations. When Chip Enable is high, power consumption is reduced. Output Enable (G). The Output Enable input controls the data output buffers and is used to initiate read operations. Data In/ Out - DQ7). Data is written to or read from the M28C16 through the I/O pins. Write Enable (W). The Write Enable input controls the writing of data to the M28C16. Ready/Busy (RB). Ready/Busy is an open drain output that can be used to detect the end of the internal write cycle. It is offered only with the TSOP28 package. The reader should refer to the M28C17 datasheet for more information about the Ready/Busy function.

OPERATION In order to prevent data corruption and inadvertent write operations an internal VCC comparator inhibits Write operation if VCC is below VWI (see Table 7). Access to the memory in write mode is allowed after a power-up as specified in Table 7. Read The M28C16 is accessed like a static RAM. When E and G are low with W high, the data addressed is presented on the I/O pins. The I/O pins are high impedance when either E is high. Write operations are initiated when both W and E are low and G is high.The M28C16 supports both E and W controlled write cycles. The Address is latched by the falling edge or W which ever occurs last and the Data on the rising edge or W which ever occurs first. Once initiated the write operation is internally timed until completion.