2014 Accellera Standards Are Built on Powerful Shoulders

Looking out at the fresh snow coating the landscape here in Buffalo, it’s tempting to look toward 2014 and focus only on the fresh and new. However, if I’ve learned anything about this city from the day I arrived here as a freshman EE in 1984, it’s that you don’t bury your foundation. Instead, you recognize it as your greatest strength, the powerful shoulders upon which you build your future. That’s akin to what I see as I look at the activity and trends in the industry for 2014—strengthening the standards core as we inexorably move up to higher abstraction.

Standards Proliferation Builds Foundation for the Future
The UVM standard is deep in the proliferation phase. There are more than 4,100 members in the UVM LinkedIn group. Every day there are new job openings for verification engineers with UVM skills. This translates into shorter ramp-up for new projects, more reusable VIP available, and easier communication among teams, reducing the development costs for new chips.

In 2014, the UVM Working Group (WG) will release UVM 1.2. The new release will add new features for runtime phasing and messaging as well as close a few bugs, further solidifying this pervasive standard. Following the release, the WG will present the standard to the IEEE. But what comes next? Accellera may consider how this verification foundation built for RTL will apply to SoC integration, power-aware designs, mixed-signal designs, and other aspects of system development.

Working in parallel with the UVM WG is the Multi-Language WG. This group is also building on the UVM foundation to connect multiple verification languages and verification frameworks into cohesive verification environments for mixed RTL and SystemC designs. Like UVM, the multi-language effort is aimed at reducing costs through reuse. In 2014, this WG will have an exciting transition from requirements collection to standard development.

Another key foundation standard is IP-XACT. IP integration and the reuse of legacy IP is critical for every project team across the design. Packaging IP and enabling faster integration is key to big SoC projects. Not only can digital design IP be described in IP-XACT metadata, but the recently announced Accellera vendor extensions now also support capturing analog/mixed-signal, physical design, and power intent. Accellera also acquired the OCP 3.0 standard last year; OCP facilitates reuse of IP blocks and continues to bolster Accellera’s IP standards initiatives. In 2014, the IP-XACT WG will take the IP-XACT standard to the IEEE P1685 Working Group, but will also continue development in Accellera because IP remains a big challenge.

Accellera also sees continued industry adoption of SystemC-based electronic system-level (ESL) methodologies. In 2014, we will further enrich the ESL ecosystem with new standards to grow virtual prototyping and embedded design practices. Work is going on in the SystemC Language, Verification, CCI (Configuration, Control & Inspection), Synthesis, and AMS (Analog/Mixed-Signal) WGs to develop extensions or introduce new features in each standard. The SystemC CCI and Verification WGs expect to provide standards updates in 2014. In addition, Accellera has contributed its SystemC AMS 2.0 standard to the newly formed IEEE SystemC AMS Working Group (P1666.1), which will formalize the standard.

Be the Future
The future efficiency derived from Accellera standards comes from the hard work of engineers in Accellera member companies. In this short space, I highlighted a few of the standards, but there is also development happening in UCIS, OVL, OCP, and others in Accellera. Our members, and many others in the electronics world, also provide their knowledge and experience through Accellera communities. Please join us there as we all work together to use the standards more efficiently.

As I look forward to 2014, I do so with the confidence that fresh and new standards are building on the shoulders of a powerful foundation. Good luck and good engineering in 2014!