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Abstract:

A semiconductor package includes a body having a first surface and a
second surface facing away from the first surface, and formed with a
groove in the first surface. First connection parts may electrically
connect a portion of the first surface to a portion of the second surface
of the body. Second connection parts may electrically connect a portion
of a bottom portion of the groove to a portion of the second surface of
the body. A lower device may be disposed in the groove of the body, and
have third connection parts that are electrically connected with the
second connection parts. An upper device may be disposed on the body and
the lower device, and have fourth connection parts that are electrically
connected with the first connection parts and the third connection parts.

Claims:

1. A semiconductor package comprising: a body having a first surface and
a second surface facing away from the first surface, and formed with a
groove in the first surface; first connection parts that are configured
to electrically connect a portion of the first surface to a portion of
the second surface of the body; second connection parts that are
configured to electrically connect a portion of a bottom portion of the
groove to a portion of the second surface of the body; a lower device
disposed in the groove and having third connection parts that are
configured to be electrically connected with the second connection parts;
and an upper device disposed on the body and the lower device and having
fourth connection parts that are configured to be electrically connected
with the first connection parts and the third connection parts.

2. The semiconductor package according to claim 1, wherein the body is
any one of a printed circuit board, a semiconductor chip, a wafer, a
silicon interposer, an interposer including a passive device, an
interposer including an active device, a printed circuit board including
a passive device, and a printed circuit board including an active device.

4. The semiconductor package according to claim 1, further comprising:
connection members formed between the first connection parts and the
fourth connection parts, between the second connection parts and the
third connection parts, and between the third connection parts and the
fourth connection parts.

5. The semiconductor package according to claim 4, wherein the connection
members comprise any one of a solder bump, a solder paste, a solder ball,
a metal bump, a metal paste, a carbon nanotube, an ACI (anisotropic
conductive ink), an ACF (anisotropic conductive film), and a conductive
paste.

6. The semiconductor package according to claim 1, wherein an upper
surface of the lower device is flush with the first surface of the body.

7. The semiconductor package according to claim 1, wherein the first and
second connection parts have different sizes.

8. The semiconductor package according to claim 7, wherein the first
connection parts are longer than the second connection parts.

9. The semiconductor package according to claim 1, wherein the first,
second, third, and fourth connection parts are through vias.

10. The semiconductor package according to claim 1, wherein the upper
device has a size larger than the lower device.

11. The semiconductor package according to claim 1, wherein a plurality
of upper devices is stacked over at least one of the body and the lower
device.

12. The semiconductor package according to claim 1, further comprising: a
molding member formed on the body to encase the lower and upper devices.

Description:

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims priority to Korean patent
application number 10-2011-0013240 filed on Feb. 15, 2011, which is
incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to a semiconductor package, and more
particularly, to a semiconductor package that can improve electrical
connection between a substrate and an upper semiconductor chip in a stack
package structure.

[0003] Packaging technologies for a semiconductor device have been
developed to satisfy demands for miniaturization and high capacity. One
such technology is a stack package capable of satisfying requirements for
miniaturization, high capacity, and mounting efficiency.

[0004] An example of the stack package includes a COC (chip-on-chip)
package in which an upper semiconductor chip is stacked on a lower
semiconductor chip.

[0005] In the COC package, in order to electrically connect the lower
semiconductor chip with the upper semiconductor chip, circuit wiring
lines such as redistribution lines or connection members such as bumps
are formed.

[0006] In some cases a plurality of semiconductor chips with different
sizes are stacked and electrically connected with one another on a
substrate. For example, a lower semiconductor chip may be attached to a
substrate and a plurality of upper semiconductor chips larger than the
lower semiconductor chip may be stacked on and electrically connected
with the lower semiconductor chip. However, since there is space under
the periphery of the upper semiconductor chips due to overhang over the
smaller lower semiconductor chip, the upper semiconductor chips are not
likely to be appropriately connected with the substrate.

[0007] This may lead to degradation of the electrical characteristics and
reliability of the package.

BRIEF SUMMARY OF THE INVENTION

[0008] An embodiment of the present invention is directed to a
semiconductor package that can improve electrical connection between a
substrate and an upper semiconductor chip in a stack package structure.

[0009] In one embodiment of the present invention, a semiconductor package
includes a body having a first surface and a second surface facing away
from the first surface, and formed with a groove in the first surface.
First connection parts may electrically connect a portion of the first
surface to a portion of the second surface of the body. Second connection
parts may electrically connect a portion of a bottom portion of the
groove to a portion of the second surface. A lower device may be disposed
in the groove of the body, and may have third connection parts that may
electrically connect with the second connection parts. An upper device
larger than the lower device may be disposed on the body and the lower
device, and may have fourth connection parts that may be electrically
connected with the first connection parts of the body and the third
connection parts of the lower device.

[0010] The body may be any one of a printed circuit board, a semiconductor
chip, a wafer, a silicon interposer, an interposer including a passive
device, an interposer including an active device, a printed circuit board
including a passive device, and a printed circuit board including an
active device.

[0011] The lower and upper devices may include semiconductor chips.

[0012] The semiconductor package may further include connection members
formed between the first connection parts and the fourth connection
parts, between the second connection parts and the third connection
parts, and between the third connection parts and the fourth connection
parts.

[0013] The connection members may include any one of a solder bump, a
solder paste, a solder ball, a metal bump, a metal paste, a carbon
nanotube, an ACI (anisotropic conductive ink), an ACF (anisotropic
conductive film) and a conductive paste.

[0014] An upper surface of the lower device may be flush with the first
surface of the body.

[0015] The first and second connection parts may have different sizes.

[0016] The first connection parts may be longer than the second connection
parts.

[0017] The first, second, third, and fourth connection parts may be
through vias.

[0018] A plurality of upper devices may be stacked over at least one of
the body and the lower device.

[0019] The semiconductor package may further include a molding member
formed on the body to encase the lower and upper devices.

BRIEF DESCRIPTION OF THE DRAWINGS

[0020] FIG. 1 is a cross-sectional view illustrating a semiconductor
package in accordance with an embodiment of the present invention.

[0021] FIG. 2 is a cross-sectional view illustrating a semiconductor
package in accordance with another embodiment of the present invention.

DESCRIPTION OF SPECIFIC EMBODIMENTS

[0022] Specific embodiments of the present invention will be described in
detail with reference to the accompanying drawings.

[0023] It is to be understood that the drawings are not necessarily to
scale and in some instances proportions may have been exaggerated in
order to more clearly depict certain features of the invention.

[0024] FIG. 1 is a cross-sectional view illustrating a semiconductor
package in accordance with an embodiment of the present invention.

[0025] Referring to FIG. 1, the semiconductor package in accordance with
the embodiment of the present invention includes a body 100 with a groove
H, a lower device A disposed in the groove H, and an upper device B
disposed on the lower device A in the groove H of the body 100.

[0026] The body 100 has an upper surface a and a lower surface b. The
groove H is defined on the upper surface a of the body 100, and ball
lands 101 are formed on the lower surface b of the body 100.

[0027] For example, the body 100 may comprise any one of a printed circuit
board, a semiconductor chip, a wafer, a silicon interposer, an interposer
including a passive device, an interposer including an active device, a
printed circuit board including a passive device, and a printed circuit
board including an active device.

[0028] First connection parts 102a and second connection parts 102b are
formed through the body 100. The first connection parts 102a electrically
connect the upper surface a and the lower surface b with each other. The
second connection parts 102b may electrically connect the bottom of the
groove H and the lower surface b of the body 100. The first and second
connection parts 102a and 102b may be, for example, through vias. The
first and second connection parts 102a and 102b may have different sizes,
where the first connection parts 102a may be shorter than the second
connection parts 102b.

[0029] The lower device A is disposed in the groove H of the body 100, and
may, for example, be a first semiconductor chip 104. The first
semiconductor chip 104 includes first bonding pads 109 of a face-down
type and first bumps 108 which are formed under the first bonding pads
109 as connection members. The first semiconductor chip 104 further
includes third connection parts 106 electrically connected with the
second connection parts 102b. The third connection parts 106 may be, for
example, through vias. Since the lower device A may be inserted into the
groove H of the body 100 such that the upper surface of the lower device
A is flush with the upper surface of the body 100, a subsequent underfill
process may be easily performed.

[0030] In succession, the upper device B is disposed on the body 100
including the lower device A. Similarly to the case of the lower device
A, the upper device B may, for example, be a second semiconductor chip
110. The second semiconductor chip 110 may include second bonding pads
112 of a face-down type and second bumps 111 formed under the second
bonding pads 112 as connection members. At least one such upper device B
may be stacked. The reference symbols C, D, and E may denote a plurality
of upper devices stacked upon the upper device B. The upper device B is
larger than the lower device A. The upper device B includes fourth
connection parts 114 electrically connected with the first connection
parts 102a of the body 100 and the third connection parts 106 of the
lower device A. The fourth connection parts 114 may be, for example,
through vias. The plurality of upper devices B, C, D and E may be stacked
over at least one of the body 100 and the lower device A.

[0031] In an embodiment of the present invention, the first and second
bumps 108 and 111 may be exemplified as connection members for
electrically connecting the first, second, third and fourth connection
parts 102a, 102b, 106, and 114. That is, for electrically connecting the
first connection parts 102a with the fourth connection parts 114, the
second connection parts 102b with the third connection parts 106, and the
third connection parts 106 with the fourth connection parts 114. However,
the invention need not be so limited. For example, any one of, for
example, a solder bump, a solder paste, a solder ball, a metal bump, a
metal paste, a carbon nanotube, an ACI (anisotropic conductive ink), an
ACF (anisotropic conductive film) and a conductive paste may be formed
between the first connection parts 102a and the fourth connection parts
114, between the second connection parts 102b and the third connection
parts 106 and between the third connection parts 106 and the fourth
connection parts 114, as a connection member.

[0032] External connection terminals 130 such as, for example, solder
balls may be attached to the ball lands 101. Accordingly, an embedded COC
(chip-on-chip) package structure may be formed in which the upper device
B is disposed on the body 100, where the lower device A is in the body
100.

[0033] FIG. 2 is a cross-sectional view illustrating a semiconductor
package in accordance with another embodiment of the present invention.
Detailed descriptions of the same or like component elements as those
shown in FIG. 1 will be omitted, and only different features will be
described.

[0034] Referring to FIG. 2, there is further shown, compared to FIG. 1, a
molding member 120 formed on the body 100 that encases the lower device A
and the upper devices B, C, D and E.

[0035] The semiconductor package shown in FIG. 2 is, for example, one
molded at a wafer level and individualized through a sawing process.

[0036] As is apparent from the above description, in various embodiments
of the present invention, a groove is defined in a substrate in a general
stack package structure, for example, in a COC (chip-on-chip) package
structure. A lower device is inserted into the groove, and an upper
device larger than the lower device is stacked on the substrate where the
lower device is inserted. This may provide a stable platform such that
the upper device is electrically connected with the substrate and the
lower device. As a consequence, electrical connection between the
substrate and the upper device may be improved. Moreover, in various
embodiments of the present invention, because the lower device is
inserted into the groove, an underfill process may be easily performed.

[0037] Although specific embodiments of the present invention have been
described for illustrative purposes, those skilled in the art will
appreciate that various modifications, additions and substitutions are
possible, without departing from the scope and the spirit of the
invention as disclosed in the accompanying claims.