No support for parameterized interface in module "signal" list.

In SystemVerilog there is, I believe - I admit to being very new to SystemVerilog - no syntax to be able to pass parameters to an interface type when it is used in the signal list of a module.

Instead in the signal list the keyword 'interface' should be used.

See the example code, attached, which essentially lifted directly from Section 25.8 "Parameterized interfaces" of IEEE 1800-1012. (I've deleted the tasks which are not relevant to this issue, and changed a 'ref' on 'data' to 'input'/'output' in the modports so this should be supported by Verilator.)

History

This unfortunately cannot be supported soon, as Verilator needs to resolve all types during a first pass (before parameters are known) and this cannot be done with generic interfaces. A major restructuring would have to happen first.