512k SRAM extension for Atari XL/XE
v1.3 (c) 2006-2010 by Matthias Reichl
1. Introduction
The main goals when designing this SRAM extension was that it
should be cheap (less than 10-15 EUR), easy to build (I can be
quite lazy when it comes to soldering) and compatible with as many
programs as possible.
Several users asked for battery backup support (so that the
contents are preserved when you switch off your Atari), so I added
this, too. But this is an optional feature, you don't need to
add it if you don't need it.
Concerning compatibility with software: This RAM extension is able
to operate in 4 modes, depending on the switch settings.
If both switches are open, the RAM extension is completely disabled.
If the EN5 switch is closed, and EN7 is open, the RAM extension
is in 256k mode and uses PB2,3,5,6 for selecting one out of
16 banks. PB4 is used to enable/disable the RAM extension.
This mode is compatible with the "Atari Magazin Ramdisk"
If EN5 is open and EN7 is closed, the RAM extension is in 256k
mode and uses PB2,3,6,7 for bank selection. PB4 enables CPU
access to the ram extension, PB5 enables ANTIC access to the
RAM extension. If both CPU and ANTIC access is disabled,
PB7 enables/disables the builtin selftest ROM. If the RAM
extension is enabled, the selftest is switched off.
This mode is compatible with the "Rambo" or "Compy Shop"
RAM extension
If both EN5 and EN7 are closed, the RAM extension is in 512k
mode and uses PB2,3,5,6,7 for bank selection. PB4 enables/disables
the RAM extension. Like in the previous mode, PB7 controls
the selftest ROM unless the RAM extension is active.
2. Component list
These are all components required for the RAM extension:
512k SRAM (eg Alliance AS6C4008-55PCN or BSI BS62LV4006PC)
GAL 22V10-15
24pin narrow DIP socket (for GAL)
8 pcs 4k7 resistors
100nF capacitor
2 pcs SPST switch (or jumpers, if you like)
Of course you'll also need a GAL programmer to program the logic
(SRAM13.JED) into the GAL.
Note: the JEDEC file also contains test vectors to verify correct
operation of the programmed GAL (for example to sort out defective
GALs). If your GAL programmer supports vector tests it's a good
idea to run them after programming.
If you want to add the optional battery backup feature, you need
a few other components:
another 100nF capacitor
DS1210 (the successor MXD1210 should work, too)
3V battery (for example a CR2032 plus battery holder)
Important note: Please make sure that the SRAM is able to operate
at 3V! Most current 5V SRAMs support a 3V "data retention mode",
if in doubt have a look at the datasheet.
3. How to build
You can find the schematics to this upgrade in the SRAM13.PNG
and SRAM13.SCH (Eagle format) files.
Most of the connections are the address and data lines to the SRAM.
If you don't want to build a PCB, the easiest way is to solder
the SRAM on top of either the OS ROM or the BASIC ROM. I'd recommend
soldering it on top of the BASIC ROM, so you can install a
replacement OS later (if you want).
The pinout of the SRAM is very similar to the pinout of the ROMs.
You just have to bend up a few pins of the SRAM and can get most
signals (address and data lines, GND) directly from the ROM.
If you want to build a PCB, just take these signals from somewhere
in your Atari (ROMs, CPU or ANTIC).
3.1 Installing the SRAM on top of the OS ROM
Bend up the following pins of the SRAM: 3, 22, 24, 29, 30
Now align the SRAM on top of the OS ROM so that SRAM pin
16 (GND) connects to OS ROM pin 14 (GND). The SRAM is a little
bit larger than the OS ROM, pins 1,2,31,32 of the SRAM aren't
connected to anything (yet). Solder all pins that aren't bent
up to the OS ROM.
If you don't want to build the optional battery backup, use
a short insulated wire and connect
SRAM pin 32 to OS ROM pin 28 (VCC)
3.2 Installing the SRAM on top of the BASIC ROM
Bend up the following pins of the SRAM: 22, 24, 28
Now align the SRAM on top of the BASIC ROM so that SRAM pin
16 (GND) connects to BASIC ROM pin 12 (GND). SRAM Pins 1-4
and 29-32 aren't connected, yet. Solder all pins that aren't bent
up to the BASIC ROM.
Now you need to solder 2 wires to connect A11 and A13 from the
Atari to the SRAM:
SRAM pin 4 (A12) to CPU pin 20 (A11)
SRAM pin 28 to CPU pin 23 (A13).
Note: no, I didn't mix up A11 and A12 :-) The pinout of the BASIC
ROM differs a little bit from the pinout of the SRAM:
A11 and A12 "swapped" and A11 of the BASIC ROM (pin 18) would connect
to /CE of the SRAM (pin 22) if we soldered these pins together.
If you don't want to build the optional battery backup, use
a short insulated wire and connect
SRAM pin 32 to BASIC ROM pin 24 (VCC)
3.3 Getting signals from the PIA
Bend up pins 12-17 (PB2-PB7) of the pia, take 6 4k7 resistors
and solder one end of each resistor to each of the PIA pins.
Connect all other ends of the resistors and make a connection
to PIA pin 20 (VCC). These resistors are used as pull-ups so
that the default signal is high (which means RAM extension
disabled) in case the PIA is programmed for input.
If the PIA is socketed, you may also just clip off pins
12-17 directly at the PCB and carefully bend them up a little
bit so that there's no more connection to the PCB. In the
Atari 600/800XL, only pin 17 is really connected to the board,
so you only need to clip this pin and you can leave all other
pins soldered to the PCB. On the XE series computers this might
be different, if in doubt, carefully check the traces from the
PIA or just clip off all pins.
Now take 3 wires and connect pins 12,13,16 (PB2,3,6) of the
PIA to SRAM pins 1,2,3 (A18, A16, A14). The other PIA pins
will later be connected to the GAL.
3.4 Getting signals from the MMU
This RAM extension intercepts the /CI (CAS-inhibit) signal to
disable the builtin RAM. This mode works with all XL/XE computers
but it also requires that you bend up one pin of the MMU
(or cut it off in case it's soldered in).
So, bend up pin 16 of the MMU (this is /CI).
3.5 Connecting the GAL
I'd recommend you use a DIP socket for the GAL, but you may also
connect all wires directly to the GAL if you like. Just be sure
you programmed the GAL right before soldering it in :-)
First, solder the 100nF bypass capacitors to pin 12 (GND) and
pin 24 (VCC) of the GAL.
Next, install two 4k7 pullup resistors for the mode select switches.
Solder one 4k7 resistor between pin 10 (EN5) and pin 24 (VCC), another
resistor between pin 11 (EN7) and pin 24 (VCC).
Take some wires and connect the switches to the mode select pins.
Install the first switch between pin 10 (EN5) and pin 12 (GND),
the second switch between pin 11 (EN7) and pin 12 (GND).
Note: If you don't need the modeswitch feature you can simply
connect GAL pins 10, 11 and 12 together (you also don't need the
4k7 pullups in this case). The RAM upgrade will then permanently
operate in 512k mode.
Use a short, insulated wire and connect GAL pin 1 (NPHI2 / CLK) to
GAL pin 23 (NPHI2_OUT).
Now connect the PIA pins 14,15,17 (PB4,5,7) to the GAL pins
7,8,9 (in this order!).
Now its time to connect several pins of the CPU to the GAL:
GAL pin 2 to CPU pin 24 (A14)
GAL pin 3 to CPU pin 25 (A15)
GAL pin 4 to CPU pin 35 (/HALT)
GAL pin 5 to CPU pin 36 (RW)
GAL pin 6 to CPU pin 39 (PHI2)
GAL pin 12 to CPU pin 1 (GND)
GAL pin 13 to CPU pin 37 (PHI0)
GAL pin 24 to CPU pin 8 (VCC)
And some connections from the GAL to the SRAM:
GAL pin 17 to SRAM pin 24 (/OE)
GAL pin 19 to SRAM pin 29 (/WE)
GAL pin 20 to SRAM pin 30 (A17)
GAL pin 21 to SRAM pin 31 (A15)
If you don't want to build the optional battery backup, connect
GAL pin 18 to SRAM pin 22 (/CE)
And now some pins at the MMU:
GAL pin 15 to MMU pin 6 (/MAP)
GAL pin 16 to MMU pin 16 (/CI)
For the last connection (GAL pin 14), the new /CI signal going into
the Atari, you've got several options. One possibility, that works
identically with all Atari, is to connect this signal directly
to the PCB where you bent up (or cut off) pin 16 of the MMU.
Unless you make the connection on the back side of the PCB it's
quite hard to get there and there's also the risk that you create
a short circuit between the bent-up pin 16 of the MMU and the PCB
by accident.
So, it's better to connect this pin to the IC where the /CI signal
is going to.
For all Atari computers with a Freddie, connect pin 14 of the
GAL to Freddie pin 4.
In an 800XL, without the Freddie, connect pin 14 of the GAL to
pin 10 of the 74LS08
In an 600XL connect pin 14 of the GAL to pin 9 of the 74LS08.
If unsure, check the connection from MMU pin 16 and verify the
exact location where this trace is running to. Or just connect
to the former MMU pin 16 on the PCB :-)
3.6 Building the optional battery back-up
First solder a 100nF capacitor between SRAM pin 16 (GND) and
SRAM pin 32 (VCC).
Then connect the DS1210 to the SRAM:
DS1210 pins 3, 4 and 7 to SRAM pin 16 (GND)
DS1210 pin 1 to SRAM pin 32 (VCC)
DS1210 pin 6 to SRAM pin 22 (/CE)
And connect the DS1210 to the GAL:
DS1210 pin 5 to GAL pin 18 (/CE)
Finally, connect the power supply and 3V battery
DS1210 pin 8 to BASIC ROM pin 24 or OS ROM pin 28 (+5V)
SRAM pin 16 to the "-" connector of the 3V battery (GND)
DS1210 pin 2 to the "+" connector of the 3V battery (+3V)
4. Check if it works
First, set both switches into the "open" position and turn on your
Atari. Check that everything works before, including the selftest etc.
Next, close both switches and check if your Atari still works.
If everything's fine so far, it's time to use some ramdisk test
programs to verify proper operation of the RAM extension. I'd
recommend using the XRAM test program (XRAM021.COM). It is able
to detect all ram extension that use PortB and also has the nice
feature that you can re-run the ram detection any time.
This is very useful to test the various modes of this ram
extension. Just set the switches and press the "DEL" key.
XRAM should then immediately display the available RAM banks.
5. How it all works
The design of this RAM extension is really straight forward. There's
nothing too complicated in the design. Just have a look at the
PALASM logic source (SRAM13.PDS).
There are only maybe one or two small parts that might look
interesting at first glance:
- Write Enable (/WE) is set using "PHI2 AND PHI0". This part is
necessary with some broken Ataris that don't meet the official
timing specification. PHI0 is almost identical to PHI2, except
that this signal is set a little bit earlier. Using "PHI2 & PHI0"
will shorten the write cycle a little bit. This doesn't hurt the
SRAM at all (it's quite fast, anyway) but will cure all problems
with those broken Ataris. Usually the address and data lines
should be valid for some time after the trailing edge (high to
low transition) of PHI2. But Atari really built quite some crap
and this isn't true for all Atari computers (especially later
XL/XE models seem to be affected). Since the actual write operation
to the SRAM occurs at the rising edge of /WE, this all is really
bad: if address and/or data lines aren't valid at this time,
the write operation fails and wrong data will be written to
the RAM (eventually also right data to the wrong address or
even random data to a random location). Older RAMs weren't
that fast (back in the 80s), but newer RAMs notice the difference.
- Chip Enable (/CE) is set using "PHI0 OR PHI2" (new in V1.13 logic).
This solves problems with newer BSI RAM chips which didn't like
it when /CE and /OE or /WE were pulled at the same time.
- Separate ANTIC access: There are quite some rumors and tales
going on about separate ANTIC access. Some people believe it's
only possible with this "magic" U35 IC of the 130XE, some
people also believe you need a special MMU for that. But this
is all just plain wrong. This U35, an 74LS95, is just used
as a flip flop (a register) that is clocked by the falling edge
of PHI2. That's nothing unusual, only in this way that most other
74xx flip flops/registers are clocked at the rising edge. If
you like, you can just run the PHI2 signal through an inverter
and substitute the LS95 with an LS74.
Why is this "strange" register needed? The answer is quite simple:
If the ANTIC wants access to the RAM, it signals it by setting
the /HALT line of the CPU to low. ANTIC asserts this signal
approximately 100ns after the falling edge of PHI2 (this is in
the first phase of a clock cycle) and this means that the
_next_ clock cycle will be used by ANTIC (and the CPU will be
halted). ANTIC will then set the /HALT signal to high again
some 100ns after the falling edge of PHI2. Since the signal
is valid for quite some time at the beginning of the clock
cycle, but then is de-asserted during the clock cycle where
ANTIC accesses the RAM, it has to be stored in a register.
The time, when we store it in a register, is just the time
when the ANTIC access clock cycle starts. So it really isn't
magic at all, one has just to understand the docs correctly :-)
- (optional) battery backup: This is handeled by the NVRAM controller
DS1210. Basically this chip intercepts the VCC and /CE pins of the
SRAM so that the SRAM is powered by the battery and
chip enable is disabled when your Atari is powered off.
Using an NVRAM controller has several advantages over the
"poor man's" battery backup solution using diodes and a pull-up
resistor that I've seen in some other RAM upgrades:
It consumes less power (meaning the battery will last longer)
and, most important of all, it's a lot safer: The NVRAM controller
disables RAM access (holds /CE high) unless the +5V supply from
the Atari is stable. When you power up your Atari the +5V line rises
from 0V to 5V. During this time the chips in the Atari aren't properly
initialized yet (this takes some time) and their pins may output
random signals. This may lead to "fake" SRAM write accesses that
corrupt SRAM data. A similar thing can happen when you power off the
Atari, in this case the +5V line drops from +5V down to 0V. The DS1210
takes care of this, it enables /CE only after +5V has reached a stable
state (usually 4.25..4.75V) and disables it immediately when the
+5V line has dropped below 4.25..4.75V.