"With Simulink and HDL Verifier, simulation and verification are performed in one environment. As a result, we can test the design from end to end, improving quality and ensuring design accuracy and validity."

Bradford Watson, Lockheed Martin Space Systems

Artist's rendition of one of the satellites that will carry Lockheed Martin's digital channelizer.

Many commercial communications satellites are limited to fixed band plans that assign a bandwidth to users even if they are not actively employing it, an inefficient use of communications capacity.

Lockheed Martin Space Systems developed a dual-stage, satellite-based channelizer (also known as a bent pipe transponder) that can move bandwidth on demand between users and locations. Lockheed engineers designed and tested the channelizer using MathWorks tools for Model-Based Design.

“Simulink and Model-Based Design enabled us to visualize the operation of the system as it was running, and the model served as a golden reference for the hardware,” says Bradford Watson, Staff Engineer, Advanced Algorithm Development Group at Lockheed Martin Space Systems Company. “Additionally, HDL Verifier proved invaluable for continuously verifying the accuracy and validity of the design and for troubleshooting any anomalous behavior observed in the hardware.”

Challenge

Lockheed Martin needed to design a system that could be updated after launch, making FPGAs an obvious choice for implementation. Designing a space-qualified system based on FPGAs was a challenge, however, because the system would be exposed to radiation in orbit, and FPGAs are highly susceptible to radiation upset.

Frequently changing requirements compounded the design challenge. "Early in the project, the band plans and the requirements for the system changed almost every day," says Watson. "We needed a process and software tools that would enable us to implement a complex design and rapidly make changes as requirements evolved. We also needed to replace an inefficient and error-prone verification process that required importing and exporting text files and many other manual steps."

Solution

Lockheed Martin engineers used MATLAB® and Simulink to design, model, and simulate the digital channelizer. They then used HDL Verifier™ and Mentor Graphics® ModelSim® to verify, analyze, and visualize the VHDL® implementation in Simulink.

Watson used MATLAB to develop algorithms for the channelizer. As band plans changed, Watson parameterized the algorithms, enabling him to tailor variables to implement a new band plan in a matter of minutes. The ability to perform fast, iterative design changes helped to keep the project on track even in the face of ever-changing requirements.

A second Lockheed Martin engineer used Simulink to develop a hardware-like, full- system model of the digital channelizer based on the MATLAB algorithms. He used delay lines, interleavers, deinterleavers, and other blocks from DSP System Toolbox™ and Communications Toolbox™ to implement two stages of channelization and two stages of reconstruction, and to manage all the signals between them.

The team also used Simulink to build test-bench wrappers that included signal sources, such as simulated radio frequency/intermediate frequency (RF/IF) signals, and output analysis tools, such as buffered fast Fourier transform displays and spectrogram analyzers.

"The Simulink models documented the design, provided traceability, and enabled us to visualize the outputs of the system as it was operating," Watson notes.

After implementing the design in VHDL, the engineers used HDL Verifier and Mentor Graphics ModelSim to perform a final functional verification of the VHDL implementation at the bit level.

To minimize the effects of radiation upset, the system uses three identical channelizers and then "votes" on the results. Lockheed Martin engineers used HDL Verifier to resolve complex reset condition and clocking issues in the voting system.

Watson used MATLAB to generate test vectors and post-process test results for hardware tests of the system running on Xilinx® Virtex-II 2v6000 FPGAs.

The digital channelizer has been successfully demonstrated in hardware, and is currently undergoing formal tests for flight certification.

Results

Verification time reduced by 90%. "Our system required precise timing. Troubleshooting our system without HDL Verifier would have taken 10 times longer," explains Watson. "Being able to compare the implemented VHDL against the golden reference in Simulink is a real advantage."

Development time reduced by eight months. "With MathWorks tools and Model-Based Design I was able to focus on the algorithm work and higher- level system issues while another engineer focused on the VHDL implementation and verification," says Watson. "We had working code in four months, from start to finish, for a system requiring 5 million gates. Without MathWorks products, it would have taken us at least a year."

Key algorithms reused, saving 50% of design effort on subsequent projects. "While the original band plan took four months to implement, we implemented two more in fewer than six weeks by reusing the existing design," explains Watson. "The channelization and reconstruction algorithms developed in MATLAB and Simulink are so flexible that I can use them anywhere. On a recent project, reusing those two functions saved 50% of the algorithm design effort."