San Diego, Sept. 6, 2011 -- A University of California, San Diego technology that significantly reduces the amount of energy wasted by chips in computers, mobile phones and other electronic devices has recently passed the trillion watt-hour milestone in energy savings, according to the technology’s current licensee, Tela Innovations. With residential energy costs at just over 11 cents per kilowatt hour, according to the latest figures from the U.S. Energy Information Administration, the savings are significant and growing, so far totaling well over $100 million that consumers haven’t been charged on their electricity bills.

Depiction of process for identifying transistors that can be slowed down in order to reduce wasted energy while maintaining performance. Courtesy: Tela Innovations.

Electronics are constantly leaking power, and that energy is wasted without having contributed anything to performance. This is especially true of devices that consumers tend to leave turned on even when they aren’t being used, such as personal computers, cell phones, and cable and Internet connections.

The technology, co-invented in 2003 by UC San Diego Jacobs School of Engineering Professor Andrew B. Kahng and his then-student Puneet Gupta, subtly modifies the dimensions of transistors, the tiny switches that control the flow of electricity in an integrated circuit. This approach, known as “gate-length biasing,” exploits the fact that slower transistors leak less power. The invention essentially ensures that transistors on a chip are as slow as possible without affecting performance.

Some of the fundamental concepts of the invention are now part of a broad, multi-university coalition funded by the National Science Foundation through a $10 million Expeditions in Computing grant awarded in 2010. UCLA's Puneet Gupta is a co-PI on the Variability-Aware Software for Efficient Computing with Nanoscale Devices project, and Kahng sits on the Advisory Board of the Variability Expedition, which is based in the California Institute for Telecommunications and Information Technology (Calit2).

The technology is now widely used in numerous applications such as network processors, Internet routers and the graphics processing units (GPUs) that are found in personal computers, tablets and game consoles.

Andrew B. Kahng is a professor in the Jacobs School's CSE and ECE departments, and sits on the Advisory Board of the Calit2-base Variability Expedition project.

Meanwhile, this milestone underscores the significant benefit university-based research brings to the market and society at large. “Consumers today save over a million dollars a week in energy costs with this invention, and both the rate and the total amount of savings are growing with every design and every manufactured chip that uses the technology,” said Sandra Brown, vice chancellor for research at UC San Diego. “Over 40 jobs were created, our faculty member gained two years of entrepreneurial experience, and our Ph.D. alumnus is now on the faculty of another UC campus. We hope he will one day repeat the cycle of innovation, commercialization, and real-world impact. This is what UC San Diego technology transfer is all about.”

Kahng and Gupta solved a complex optimization problem to identify which transistors can be slowed down. And they had to do this without changing the way chip designs are handed off from design teams to the silicon foundries that manufacture the chips.

“The key is figuring out which of the hundreds of millions of transistors on the chip to modify,” said Kahng. “Many, but not all, of the transistors can be made slower without affecting the clock frequency. We developed a tool to maximize leakage power savings without affecting product performance, and we created a flow to make this transparent and easy for both designers and manufacturers.

“As transistor dimensions continue to shrink in advanced manufacturing technologies, the potential for wasted energy only increases,” Gupta added “By adding even a few nanometers to the channel length of a transistor – using gate-length biasing – the invention substantially reduces leakage power while only slightly slowing down the transistor’s switching speed.”

Now a UCLA professor and co-PI on the NSF-funded Variability Expedition project, Puneet Gupta was a UCSD graduate student when he and Kahng set up Blaze DFM to market the power-saving technology (before Tela Innovations purchased Blaze DFM in 2009).

UC San Diego first licensed the then-patent-pending invention in 2004 to a startup company, Blaze DFM, which Kahng and Gupta co-founded. The patent was subsequently awarded in 2006 to UC San Diego and the University of Michigan. Kahng returned to the Jacobs School of Engineering in 2006 after developing the technology into a commercial design tool during a two-year leave of absence. Kahng is a professor in the departments of Computer Science and Engineering and Electrical and Computer Engineering. Gupta returned to the Jacobs School in 2007 to finish his Ph.D., and is now on the faculty of UCLA’s Henry Samueli School of Engineering and Applied Science. Blaze DFM was acquired by Tela Innovations in 2009.

As the technology is more widely deployed, the energy and cost savings continue to accelerate.

The gate-length biasing approach exemplifies the increasingly close coupling between design and manufacturing that is needed to keep Moore’s Law on track in today’s advanced technologies. Indeed, Kahng and his UC San Diego research lab, as well as Gupta and his UCLA research group, are widely recognized for pioneering work in the field known as “design for manufacturability,” meaning a device is designed to be easily manufacturable in order to maintain efficiency and reduce costs.

“Power has long been one of the key constraints for advanced chips, especially for mobile applications,” said Riko Radojcic, director at Qualcomm CDMA Technologies. “Qualcomm has been one of the early evaluation partners with Blaze technology, and demonstrated the leakage power reductions achieved by the Blaze optimization tool and gate-length biasing methodology on a baseband processor chip, starting at the 90nm technology node. It is gratifying to see such success for a technology that originated just a few miles away on the UC San Diego campus. I always look forward to the next ideas from Professors Kahng and Gupta.”