DAC: IP and Power. Then and now

DAC left issues in Intellectual Property quality and Power Format standardization unresolved.

Two of the most visible topics at the just concluded Design Automation Conference were Intellectual Property (IP) and Power Aware Design (PAD). I do not know that anyone has used the PAD moniker for Power Aware Design, but it is time we give it one.

Is IP quality really such a problem?
I knew that the Intellectual Property segment of EDA (yes Peggy, IP is EDA) was in trouble when it was shorten to IP thus forever generating much confusion with the other, older IP that stands for Internet Protocol. From the very beginning of the IP business, now almost twenty years ago, the quality question haunted vendors and disturbed customers. In all these years we have tried in many ways, including consortia such as VSIA and SPIRIT, to produce guidelines and specifications to help users of third party cores get a quantifiable measure of a core quality without having to read its source code. We have not succeeded yet. Some companies, like ARM for processors, True Circuits for analog cores, and The Mathworks for blocks that are automatically built by its software products, have achieved customers acceptance through the robustness displayed by their products through a large number of design uses. Other, like CAST are trusted by their longevity in the market place. Obviously by naming only these four companies I am not saying that all the other IP vendors are not to be trusted. Many provide good quality cores, but the subject of IP quality continues to be debated, and designers representatives do not express any more satisfaction with the sector today than they did three years ago.
In the mean time, lots and lots of successful designs have been concluded using third party IP cores. So, do we really have a problem? Are customers just being lazy or too demanding? Do companies really have to depend from untried core vendors for their most critical products?

I think we do have reliable suppliers of cores, including large EDA companies like Synopsys and Mentor, and I think both the VSIA Quality Metrics and the SPIRIT IP-XACT specifications provide much needed help. Designers must remember that, just as in all other market segments, you get what you pay for. Saving on royalties or one time license cost by using an untried group of designers that think they can build the next ARM, comes with risk. If you win, the rewards may be worth the gamble, but in this segment "CAVE EMPTOR" as those pioneering Roman capitalists used to say.

The Power or Dueling to the Death
The duel between the two power formats: CPF and UPF continued at DAC. In my opinion it was unfortunate that attendees to the Sunday Workshop had to pay $100 to listen to advertorials about the two formats. All of the panelists at the CPF workshop with the exception of ArchPro were affiliated with companies members of the Low Power Coalition (LPC) of Si2. In the end the choice of ArchPro did not work out as expected, since the Synopsys purchased the company the week after DAC and their choice of format they will support is now in the hands of Synopsys' Richard Goldman.

The UPF workshop, not to be outdone, featured all speakers with firm ties to the Accellera development work of UPF. So if you wanted an unbiased opinion, you certainly did not get it on Sunday. yet if I have to say who scored the most points in the week following DAC, I must say that UPF got the upper hand. By purchasing S8ierra Design, Mentor assured one more physical implementation company in the UPF fold, while ArchPro will provide additional implementations of UPF in the front end of the design flow. Unfortunately the advantage scored by UPF is not decisive for those who are looking for a clear sign to help them pick which format to support first. Cadence has significant resources, good relations with the foundries, and money to spend to safeguard its reputation. So the duel goes on: I just hope we can minimize the collateral damage.