As the complexity of power and ground networks increases, methods for efficient analysis and aggressive optimization of these networks become essential. Here, the authors describe efficient hierarchical methods for analyzing distribution networks. To optimize the networks, the authors call for techniques that reduce noise on the power grid, including topology selection, wire widening, and decoupli...
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Although it is tempting to think of the power grid as an independent medium of the transfer of energy from the package to the devices in the IC, some second-order technology-related effects can sometimes cause unforeseen problems. This article focuses especially on the relationship of the power delivery system to the silicon substrate properties, and shows how a low-impendance substrate can make a...
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Assuming that delay is linearly dependent on local power supply voltage, the authors show how to set up an analysis to determine the effect of power supply variations on delay. This analysis can drive the introduction of clock gating, an increasingly popular technique for reducing dynamic power dissipation.
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This article takes a high level of the power-grid noise problem as it relates to the microarchitectural definition of an IC. Through a set of simulations, the authors relate the noise problem to the details of the circuit and clocking implementation giving insight into the possible method to reduce such noise.
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Chip-level failure detection has been a target of research for some time, but today's very deep-submicron technology is forcing such research to move beyond detection. Repair, especially self-repair, has become very important for containing the susceptibility of today's chips. This article introduces a self-repair-solution for the digital FIR filter, one of the key blocks used in DSPs.
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Today's complex SoCs need sophisticated infrastructure IP, not only to test and diagnose embedded memories but also to repair them and improve fabrication yield. The authors solution integrates memory IP with test and repair IP in a composite infrastructure IP that ensures manufacturing and field repair efficiency and optimizes SoC yield.
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The tradeoff between IP protection and SoC-level test optimization has been an issue for some time. The more IP providers protect their IP, the less flexibility system developers have to control test costs and fault coverage. In this paper, a new approach dynamically extracts IP-related test information or optimizing SoC testing without jeopardizing IP protection.
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Embedding infrastructure IP to optimize chip-level manufacturing test and debugging has recently become common practice. However, adopting the same approach for boards and systems requires a different family of infrastructure IP. This article introduces such a family and discusses how it can optimize manufacturing test and debugging, as well as support configurability, especially in today's reconf...
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