While the notion of self-awareness has a long history in biology, psychology, medicine, engineering and (more recently) computing, we are seeing the emerging need for self-awareness in the context of complex many-core Systems-on-Chip that must address the often conflicting requirements of performance, resiliency, energy, heat, cost, security, etc. in the face of highly dynamic operational behaviors coupled with process, environment, and workload variabilities. Unlike traditional MultiProcessor Systems-on-Chip (MPSoCs), self-aware SoCs must deploy an intelligent co-design of the control, communication, and computing infrastructure that interacts with the physical environment in real-time in order to modify the system’s behavior so as to adaptively achieve desired objectives and Quality-of-Service (QoS). Self-aware SoCs require a combination of ubiquitous sensing and actuation, health-monitoring, and statistical model-building to enable the SoC’s adaptation over time and space. Accordingly, this special session first outlines the notions of self-awareness in computing and then features three different dimensions of self-aware Systems-on-Chip. The first talk by Prof. Nikil Dutt defines the notion of self-aware computing and presents the Cyber-Physical System-on-Chip (CPSoC) concept as an exemplar of a self-aware SoC that intrinsically couples on-chip and cross-layer sensing and actuation using a sensor-actuator rich fabric to enable self-awareness. The second talk by Prof. Mehdi Tahoori discusses data-driven learning based chip health monitoring infrastructure to ensure system resilience. The third talk by Prof. Abhijit Chatterjee presents self-aware self-learning real-time systems with applications to wireless communication, signal processing and control.