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Classifications

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof

H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer

H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials

H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268

H01L21/28008—Making conductor-insulator-semiconductor electrodes

H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon

H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor

H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects

H—ELECTRICITY

H01—BASIC ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials

H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices

In einigen Vorgehensweisen können gewisse strukturelle Aspekte in einer Transistorarchitektur verwirklicht werden, um eine deutliche Verbesserung eines oder mehrerer der obigen Aspekte zu erreichen. In some approaches certain structural aspects can be implemented in a transistor architecture to achieve a significant improvement in one or more of the above aspects.Beispielsweise wird in modernen Halbleiterbauelementen häufig die SOI-Architektur eingesetzt auf Grund gewisser dieser Architektur innewohnender Vorteile eines SOI-Transistors in Bezug auf ein Vollsubstratbauelement, etwa die geringere Übergangskapazität, das erhöhte Ausmaß an Isolation zwischen benachbarten Bauelementen, und dergleichen. For example, the SOI architecture is used on the basis of certain of this architecture like inherent advantages of SOI transistor with respect to a bulk substrate device, such as the lower junction capacitance, the increased degree of insulation between adjacent devices, and in advanced semiconductor devices frequently.Ferner werden in SOI-Bauelementen typischerweise Isolationsgräben vorgesehen, die in einigen Lösungen nicht mit einem isolierenden Material wieder gefüllt werden, bevor die Gatestrukturierung beendet ist, um damit zusätzlich zu einem Prozessablauf mit geringerer Komplexität deutliche Vorteile im Hinblick auf ein verbessertes Durchlassstromvermögen zu erreichen. Further, the isolation trenches are provided in SOI devices typically are not filled in some solutions with an insulating material again before the gate patterning is completed, in order to achieve in addition to a process flow with less complexity significant advantages in terms of an improved current capability.Beispielsweise können auf Grund des fehlenden Füllmaterials in den Isolationsgräben während des Gatestrukturierungsprozesses das Gateisolationsmaterial und das Gateelektrodenmaterial auch an den Endbereichen der Gateelektrode in Bezug auf die Transistorbreitenrichtung vorgesehen werden, wodurch das Erzeugen eines leitenden Kanals mit hoher Effizienz über die gesamte Breitenabmessung des Transistors hinweg ermöglicht wird. For example, the gate insulator and the gate electrode material may due to the lack of filling material in the isolation trenches during the gate patterning process are also provided at the end portions of the gate electrode with respect to the transistor width direction, thereby enabling the generation of a conductive channel with a high efficiency over the entire width dimension of the transistor of time is ,Somit kann ein effizienter Ladungsträgertransport auch an den Endbereichen erfolgen, wobei dieser Ladungsträgertransport in Bauelementen mit einem gefüllten Isolationsgraben an diesen Kanalbereichen auf Grund der geringeren kapazitiven Ankopplung an die Gateelektrode deutlich geringer sein kann. Thus can also take place at the end portions, an efficient charge carrier transport, said charge carrier transport can be considerably lower in devices with a filled isolation trench in these channel regions due to the lower capacitive coupling to the gate electrode.In ähnlicher Weise kann in einer entsprechenden Konfiguration mit einem fehlenden Isoliermaterial in dieser Fertigungsphase, was auch als „Mesa-Isolation” bezeichnet wird, die Herstellung der Metallsilizide, die die Leitfähigkeit des Halbleitermaterials verbessern, an diesen Endbereichen des Kanals verbessert werden, wodurch ebenso der Gesamtreihenwiderstand des Transistors reduziert wird. Similarly, the preparation of the metal silicides that improve the conductivity of the semiconductor material may in a corresponding configuration with a lack of insulating material in this manufacturing stage, which is also referred to as "mesa isolation" can be improved at these end regions of the channel, whereby also the total series resistance of the transistor is reduced.

Angesichts der zuvor beschriebenen Situation ist es Aufgabe, ein verbessertes Verfahren, wobei eines oder mehrere der oben erkannten Probleme vermieden oder zumindest dessen Auswirkungen reduziert werden, bereitzustellen. In view of the situation described above, it is an object to provide an improved method in which one or avoided to provide more of the problems identified above or at least its effect can be reduced.

Lacquer contamination reducing method, involves forming lacquer mask, which unseals area of deformation induced layer, over layer to cover one transistor, and removing unsealed area of layer from area over another transistor