Contents

Hardware

The brain of the device sits in the FX2. It does the USB communication, programs two DACs and the waveform generator, uploads the firmware into the FPGA, forwards some settings to the FPGA, and controls the seven relays, the input channel crossbar, and the power nets enable signals. The FPGA fetches samples from the ADCs, stores them in the SRAM and waits for the trigger signal. When done, it fetches the samples from the SRAM and gives them to the FX2.

I2C

An ST24C02 EEPROM is directly connected to the FX2. It stores the USB ID and probably some calibration data. All other chips are behind an I2C gate (74VHC4052). The other I2C chips are

PCA9554A - 8 bit GPIO controller

IO0 controls the relay for the 20:1 attenuator on channel B

IO1 controls the relay for the AC high-pass filter on channel B

IO2 controls the relay for the 20:1 attenuator on channel A

IO3 controls the relay for the AC high-pass filter on channel A

IO4 drives the LED

IO5 decides which channel is routed to the AD8132+AD9215 behind the channel A connector

IO6 decides which channel is routed to the AD8132+AD9215 behind the channel B connector and the LT1715 for triggering

IO7 drives the relay to route the waveform generator to the EXT connector

MAX5822 - 2 channel DAC

Sets the trigger levels

AD5315 - 4 channel DAC

One output to each AD8132

One output to the VREF pin of each AD9215

SPI

There is no SPI controller in the FX2. You have to do bit banging.

AD9833 - waveform generator

SDATA/SCLK/FSYNC is PD4/PD3/PD2 on the FX2

XC2S30 - FPGA

DIN/CCLK/PROGRAM is PA1/PA7/PA0 on the FX2

Power Nets

The voltage from the optional power supply is converted to 4.9V by an LM3578. This is combined with the nominal 5V from USB. This power rail sources the SP6650 for 3.3V and the secondary 5V power rail.

The 3.3V power rail is for the FX2, the EEPROM, the I2C gate, the MAX6424UK29, and the 555 timer. It also sources the secondary 3.3V power rail. It is always on.

The secondary 3.3V power rail is for the AD9833, the 25MHz oscillator, both AD9215s, and the LT1715. It is enabled while FX2 PD7 is low.

The secondary 5V power rail sources the LM2611 for -4.9V, the SP6650 for 2.5V, the MAX1896 for 6V, and both LP2981AIM5 for 4V. It is limited to about 7mA unless FX2 PD7 is low.

The 6V power rail is for the two SST5912s. It is enabled while FX2 PD5 is high.

The 2.5V power rail is for the FPGA and the SRAM. It is enabled while FX2 PD6 is high.

The -4.9V power rail is for the input channel and trigger signal conditioning, the waveform generator, and FPGA pin 102/103. It is enabled while FX2 PD5 is high.

One 4V power rail is for the input channel and trigger signal conditioning, the waveform generator. It is enabled while FX2 PD5 is high.

The other 4V power rail is for the AD5315, the MAX5822, the PCA9554, the LED and the relays. This one is always on.

FX2 PD5 also controls the I2C gate.

PD5/PD6/PD7 can be overridden by dip switches.

FPGA

Thankfully this is only a two layer design without BGA components. On the top layer the 2.5V are distributed below the FPGA to all VCCINT and VCCO pins. Ground is fetched from the other side with vias.

FPGA IOs

Pin

Connected to

Pin

Connected to

Pin

Connected to

3

LT1715 out A (Trigger A or B)

49

SRAM /WE

94

SRAM D

4

LT1715 out B (Trigger EXT)

50

SRAM A19

95

SRAM D

6

25MHz oscillator

51

SRAM A

96

SRAM D

7

FX2 PD1

54

SRAM A

99

SRAM D

10

FX2 PD0

56

SRAM A

100

Test point

11

FX2 RDY1

57

SRAM A

102

RC network @ -4.9V

12

FX2 WAKEUP

58

SRAM D

103

RC network @ -4.9V

13

FX2 PKTEND

59

SRAM D

112

AD9215-1 D9

18

FX2 FLAGA

60

SRAM D

113

AD9215-1 D8

19

FX2 FD4

62

SRAM D

114

AD9215-1 D7

20

FX2 FD5

63

SRAM D

115

AD9215-1 D6

21

FX2 FD6

65

SRAM D

117

AD9215-1 D5

22

FX2 FD7

66

SRAM D

118

AD9215-1 D4

23

FX2 FD0

67

SRAM D

120

AD9215-1 D3

26

FX2 FD1

68

SRAM A

121

AD9215-1 D2

27

FX2 FD2

69

FX2 PA0

122

AD9215-1 D1

28

FX2 FD3

72

Test point (DONE)

123

AD9215-1 D0

29

FX2 IFCLK

74

SRAM A

126

AD9215-1 CLK

31

555 out

75

SRAM A

129

AD9215-2 D9

37

FX2 PA7

76

SRAM A

130

AD9215-2 D8

38

10kOhm to CCLK?

77

SRAM A

131

AD9215-2 D7

39

FX2 PA1

79

SRAM A

132

AD9215-2 D6

40

SRAM D

80

SRAM A

133

AD9215-2 D5

41

SRAM D

83

SRAM A

134

AD9215-2 D4

43

SRAM D

84

SRAM A

136

AD9215-2 D3

44

SRAM D

85

SRAM A

137

AD9215-2 D2

46

SRAM A

86

SRAM A

139

AD9215-2 D1

47

SRAM A

87

SRAM A

140

AD9215-2 D0

48

SRAM CLK

93

SRAM A

141

AD9215-2 CLK

As you can see only 16 data lines of the SRAM are connected. Two data pins are unused. This probably also means that the FPGA discards two of the data bits from the ADCs depending on the selected voltage range.

Pin 50 is an address pin only if the board is equipped with a bigger SRAM (K7N161831B).

I don't know what the 555 is used for. It looks like it in an astable configuration.

Have a good look at pin 102 and 103. They are connected to caps via 110 Ohm resistors. These caps are supplied by the -4.9V power rail via 100kOhm if both pins are inputs. Contrary to what was said here before, this will not kill the FPGA. According to the IBIS data the internal protection diodes will limit the voltage to a safe value and the negative voltage is in fact applied while the FPGA bitstream is uploaded. Anyone knows if these pins serve any purpose?

EEPROM

The I2C EEPROM is used mainly to hold calibration data. Multi-byte values are little endian. There is a checksum, but is very weak and overly complicated. The last two bytes contain the number of iterations that have to be done to a 14 bit LFSR to get a value that equals the sum of the preceding data when interpreted as signed bytes. The weakness comes from their method of reducing the sum to 14 bits: During summing they reset the intermediate value to zero as soon as it uses more than 14 bits. As the bytes added are signed, this happens very often.

Allocation of EEPROM bytes

00-07

see FX2 docs

08

unknown (0x01)

09-0A

Hardware version

0B-0C

Flags?, bit 0 makes FW disable USB high speed

0D-12

unknown (all 0x00)

13-1C

Batch and serial as ASCIIZ string

1D-24

Calibration date as ASCIIZ string

25-26

AD5315 channel 2 value for 0.5V and 1V ranges, trigger not on channel A

27-28

AD5315 channel 2 value for 0.2V range, trigger not on channel A

29-2A

AD5315 channel 2 value for 0.1V range, trigger not on channel A

2B-2C

AD5315 channel 2 value for 5V, 10V, and 20V ranges, trigger not on channel A