Build Xyce from Source for ADMS Verilog-A Model Integration

Xyce is a new (relative to the original SPICE) circuit simulator from Sandia National Laboratories that is SPICE-compatible but operates in a fundamentally different way under the hood. Xyce boasts a modern code base, an active forum, supports large-scale parallel computing architectures to accelerate simulations and it’s open source too! We have recently adopted Xyce in order to further develop several memristor models including our own The Generalized Metastable Switch Memristor Model, as Xyce is able to integrate Verilog-A models into Xyce-compatible C++ code using the ADMS model compiler with the Xyce/ADMS back-end. In this blog post I demonstrate how to build Xyce from source so that it is able to do the Verilog-A model integration via the plug-in mechanism. I am using Xyce 6.6, MacOS Sierra, Trilinos-12.6.4, Homebrew and gcc6. Other systems such as Linux and Windows would need to slightly modify these instructions, but the basic idea should be very similar.

Install Xyce the Easy Way

It is possible to install a Xyce binary forgoing the process of building it yourself. You won’t be able to integrate Verilog-A models into Xyce though. Compiled binaries of Xyce for most platforms can be found at https://xyce.sandia.gov/downloads/Binaries.html.

Extract the folders

Setup an out of source build directory

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cd~/workspaces/workspace_eda/Xyce-6.6

mkdirbuild

cdbuild

mkdirserial

cdserial

Create a config script

Here we take the script given on the Xyce building guide and modify it to our system and preferences. We add ADMS_CXXFLAGS="-O1" to reduce the optimization of the ADMS components which will vastly improve compile times. We also add --disable-adms_sensitivities to turn off analytic sensitivity derivative calculation for Verilog-A-derived devices. These and more optimization tips can be found on the build guide in section Special note for building on small-memory computer systems. You must configure Xyce using the --enable-shared and --enable-xyce-shareable option in order to integrate your own Verilog-A/ADMS models.

Xyce ( Parallel ) Build Instructions

Building Trilinos for use in Parallel Xyce requires enabling some additional Trilinos packages (Zoltan and ShyLU) and enabling ParMETIS library support. It also requires using the compiler wrappers provided by your system’s MPI package (ex. Open MPI) instead of the compilers (gcc, g++, gfortran) directly. These wrappers are typically called “mpicc,” “mpic++”, and “mpif77”, but your system may install them with different names or special paths.

To build for parallel, follow the instructions here, making slight modifications to the above instructions. You can use a diff tools to see the differences that need to be applied.

Additional Xyce Dependencies with Parallel support

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brew install open-mpi

brew install parmetis--build-from-source

Example Circuit for Testing

This is taken from the user manual linked to above.

Diode clipper

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Diode clipper circuit with transient analysis statement

*

*Voltage Sources

VCC105V

VIN30SIN(0V10V1kHz)

*Analysis Command

.TRAN2ns2ms

*Output

.PRINTTRANV(3)V(2)V(4)

*Diodes

D121D1N3940

D202D1N3940

*Resistors

R1231K

R2123.3K

R3203.3K

R4405.6K

*Capacitor

C1240.47u

*

*GENERIC FUNCTIONAL EQUIVALENT=1N3940

*TYPE:DIODE

*SUBTYPE:RECTIFIER

.MODELD1N3940D(

+IS=4E-10

+RS=.105

+N=1.48

+TT=8E-7

+CJO=1.95E-11

+VJ=.4

+M=.38

+EG=1.36

+XTI=-8

+KF=0

+AF=1

+FC=.9

+BV=600

+IBV=1E-4)

*

.END

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Xyce/path/to/.../clipper.cir

Xyce will run the simulation and create a .prn file. Xyce does not have it’s own graphical system for displaying results and a third party tool is necessary. They recommend gnuplot and Tecplot. To get a quick and dirty plot with the software I already had installed, I changed the .prn file to a .csv file and imported it into Libreoffice.

Note that we added the option FORMAT=CSV to directly get a CSV file as output so we don’t have to manually change the file extension before importing it into LibreOffice. Following is the familiar pinched hysteresis loop response of the memristor in response to a sinusoidal input.

Xyce Memristor I-V

Plotting with GNUPlot

The official Xyce manual states that GNUPlot is a popular choice for plotting the results of a simulation. As using LibreOffice is quite slow and cumbersome and GNUPlot could be wrapped into a script, we show how to do that next. Since I’m using a Mac, gnuplot is installed easily with homebrew:

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brew install gnuplot--with-x11

To make the plot, run the following code making sure you removed the FORMAT=CSV from the original simulation file and running it again to create the .prn file.

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gnuplot

plot'/path/to/data/memristor.cir.prn'using3:4with lines title"I-V"

Xyce GNUPlot Memristor

Schematic Capture

According to the Xyce Reference Guide page 484, Xyce has the Yakopcic and TEAM models integrated natively. The source code for these files is in .../workspaces/workspace_eda/Xyce-6.6/src/DeviceModelPKG/OpenModels/src/N_DEV_MemristorYakopcic.C and .../workspaces/workspace_eda/Xyce-6.6/src/DeviceModelPKG/OpenModels/src/N_DEV_MemristorTEAM.C

Custom Verilog-A Device models for Xyce

The rest of this blog covers the steps in integrating a simple test Verilog-A model, which comes with the Xyce source code, into a Xyce simulation. Xyce does not at this time have any capability for direct import of Verilog-A models through a netlist. Before a model written in Verilog-A can be used, it must be converted to C++ using Xyce/ADMS, compiled, and linked into Xyce. The plugin method requires that Xyce be built specially to support shared library loads — the standard binary distributions of Xyce do not support this feature yet. A script is provided with Xyce that simplifies the generation and installation of such plugins, and a command-line option is available to load the plugin at run time.

Because we previously used the compiler flags --enable-shared and --enable-xyce-shareable in order to integrate your own Verilog-A/ADMS models, we should have a utility in usr/local/bin called buildxyceplugin. What this utility will do is compile your Verilog-A model files and simulation circuits using these models into a system library file with a *.so extension in usr/local/lib. Then when you run Xyce, you just need to tell it about this library with the -plugin option and then use Xyce like normal. Let’s build the Verilog-A examples that came with Xyce to make sure everything is working before building our own models.

First, we copy the toys directory form the Xyce source code to a different place. This way we won’t accidentally change anything important in Xyce’s source tree and mess up a future compile. We can do whatever we want with it. In this case, I copied Xyce-6.6/utils/ADMS/examples/toys to ~/Desktop.