Coreboot Options

The wiki is being retired!

Documentation is now handled by the same processes we use for code: Add something to the Documentation/ directory in the coreboot repo, and it will be rendered to https://doc.coreboot.org/. Contributions welcome!

This is an automatically generated list of coreboot compile-time options.

Last update: 4.8-142-g9129f1aae9

Option

Source

Format

Short Description

Description

Menu: General setup

LOCALVERSION

toplevel

string

Local version string

Append an extra string to the end of the coreboot version.

This can be useful if, for instance, you want to append the
respective board's hostname or some other identifying string to
the coreboot version number, so that you can easily distinguish
boot logs of different boards from each other.

CBFS_PREFIX

toplevel

string

CBFS prefix to use

Select the prefix to all files put into the image. It's "fallback"
by default, "normal" is a common alternative.

CBFS_PREFIX

toplevel

string

Compiler to use

This option allows you to select the compiler used for building
coreboot.
You must build the coreboot crosscompiler for the board that you
have selected.

To build all the GCC crosscompilers (takes a LONG time), run:
make crossgcc

For help on individual architectures, run the command:
make help_toolchain

Use LLVM/clang to build coreboot. To use this, you must build the
coreboot version of the clang compiler. Run the command
make clang
Note that this option is not currently working correctly and should
really only be selected if you're trying to work on getting clang
operational.

Many toolchains break when building coreboot since it uses quite
unusual linker features. Unless developers explicitely request it,
we'll have to assume that they use their distro compiler by mistake.
Make sure that using patched compilers is a conscious decision.

Enable this option if you are working on the flashmap descriptor
parser and made changes to fmd_scanner.l or fmd_parser.y.

Otherwise, say N to use the provided pregenerated scanner/parser.

UTIL_GENPARSER

toplevel

bool

Generate SCONFIG & BINCFG parser using flex and bison

Enable this option if you are working on the sconfig device tree
parser or bincfg and made changes to the .l or .y files.

Otherwise, say N to use the provided pregenerated scanner/parser.

USE_OPTION_TABLE

toplevel

bool

Use CMOS for configuration values

Enable this option if coreboot shall read options from the "CMOS"
NVRAM instead of using hard-coded values.

STATIC_OPTION_TABLE

toplevel

bool

Load default configuration values into CMOS on each boot

Enable this option to reset "CMOS" NVRAM values to default on
every boot. Use this if you want the NVRAM configuration to
never be modified from its default values.

COMPRESS_RAMSTAGE

toplevel

bool

Compress ramstage with LZMA

Compress ramstage to save memory in the flash image. Note
that decompression might slow down booting if the boot flash
is connected through a slow link (i.e. SPI).

COMPRESS_PRERAM_STAGES

toplevel

bool

Compress romstage and verstage with LZ4

Compress romstage and (if it exists) verstage with LZ4 to save flash
space and speed up boot, since the time for reading the image from SPI
(and in the vboot case verifying it) is usually much greater than the
time spent decompressing. Doesn't work for XIP stages (assume all
ARCH_X86 for now) for obvious reasons.

COMPRESS_BOOTBLOCK

toplevel

bool

This option can be used to compress the bootblock with LZ4 and attach
a small self-decompression stub to its front. This can drastically
reduce boot time on platforms where the bootblock is loaded over a
very slow connection and bootblock size trumps all other factors for
speed. Since this using this option usually requires changes to the
SoC memlayout and possibly extra support code, it should not be
user-selectable. (There's no real point in offering this to the user
anyway... if it works and saves boot time, you would always want it.)

INCLUDE_CONFIG_FILE

toplevel

bool

Include the coreboot .config file into the ROM image

Include the .config file that was used to compile coreboot
in the (CBFS) ROM image. This is useful if you want to know which
options were used to build a specific coreboot.rom image.

Saying Y here will increase the image size by 2-3KB.

You can use the following command to easily list the options:

grep -a CONFIG_ coreboot.rom

Alternatively, you can also use cbfstool to print the image
contents (including the raw 'config' item we're looking for).

Make coreboot create a table of timer-ID/timer-value pairs to
allow measuring time spent at different phases of the boot process.

TIMESTAMPS_ON_CONSOLE

toplevel

bool

Print the timestamp values on the console

Print the timestamps to the debug console if enabled at level spew.

USE_BLOBS

toplevel

bool

Allow use of binary-only repository

This draws in the blobs repository, which contains binary files that
might be required for some chipsets or boards.
This flag ensures that a "Free" option remains available for users.

COVERAGE

toplevel

bool

Code coverage support

Add code coverage support for coreboot. This will store code
coverage information in CBMEM for extraction from user space.
If unsure, say N.

UBSAN

toplevel

bool

Undefined behavior sanitizer support

Instrument the code with checks for undefined behavior. If unsure,
say N because it adds a small performance penalty and may abort
on code that happens to work in spite of the UB.

RELOCATABLE_RAMSTAGE

toplevel

bool

Build the ramstage to be relocatable in 32-bit address space.

The reloctable ramstage support allows for the ramstage to be built
as a relocatable module. The stage loader can identify a place
out of the OS way so that copying memory is unnecessary during an S3
wake. When selecting this option the romstage is responsible for
determing a stack location to use for loading the ramstage.

CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM

toplevel

bool

The relocated ramstage is saved in an area specified by the
by the board and/or chipset.

UPDATE_IMAGE

toplevel

bool

Update existing coreboot.rom image

If this option is enabled, no new coreboot.rom file
is created. Instead it is expected that there already
is a suitable file for further processing.
The bootblock will not be modified.

If unsure, select 'N'

BOOTSPLASH_IMAGE

toplevel

bool

Add a bootsplash image

Select this option if you have a bootsplash image that you would
like to add to your ROM.

This will only add the image to the ROM. To actually run it check
options under 'Display' section.

BOOTSPLASH_FILE

toplevel

string

Bootsplash path and filename

The path and filename of the file to use as graphical bootsplash
screen. The file format has to be jpg.

Menu: Mainboard

(comment)

Important: Run 'make distclean' before switching boards

VENDOR_WINNET

mainboard/winnet.name

bool

WinNET

WinNET boards. Used in various thin client appliances.

UART_FOR_CONSOLE

mainboard/intel/mohonpeak

int

The Mohon Peak board uses COM2 (2f8) for the serial console.

PAYLOAD_CONFIGFILE

mainboard/intel/mohonpeak

string

The Avoton/Rangeley chip does not allow devices to write into the 0xe000
segment. This means that USB/SATA devices will not work in SeaBIOS unless
we put the SeaBIOS buffer area down in the 0x9000 segment.

ENABLE_FSP_MEMORY_DOWN

mainboard/intel/harcuvar

bool

Enable Memory Down

Select this option to enable Memory Down function.

SPD_LOC

mainboard/intel/harcuvar

hex

SPD binary location in cbfs

Location of SPD binary for memory down function.

VBOOT

mainboard/intel/kblrvp

None

TPM to USE

This option allows you to select the TPM to use.
Select whether the board does not have TPM, TPM 1.1 or TPM 2.0

UART_FOR_CONSOLE

mainboard/intel/littleplains

int

The Little Plains board uses COM2 (2f8) for the serial console.

PAYLOAD_CONFIGFILE

mainboard/intel/littleplains

string

The Avoton/Rangeley chip does not allow devices to write into the 0xe000
segment. This means that USB/SATA devices will not work in SeaBIOS unless
we put the SeaBIOS buffer area down in the 0x9000 segment.

GALILEO_GEN2

mainboard/intel/galileo

bool

Board generation: GEN1 (n) or GEN2 (y)

The coreboot binary will configure only one generation of the Galileo
board since coreboot can not determine the board generation at
runtime. Select which generation of the Galileo that coreboot
should initialize.

FSP_VERSION_1_1

mainboard/intel/galileo

bool

FSP 1.1

Use FSP 1_1 binary

FSP_VERSION_2_0

mainboard/intel/galileo

bool

FSP 2.0

Use FSP 2.0 binary

FSP_BUILD_TYPE_DEBUG

mainboard/intel/galileo

bool

Debug

Use the debug version of FSP

FSP_BUILD_TYPE_RELEASE

mainboard/intel/galileo

bool

Release

Use the release version of FSP

FSP_TYPE_1_1

mainboard/intel/galileo

bool

MemInit subroutine

FSP 1.1 implemented as subroutines, no EDK-II cores

FSP_TYPE_1_1_PEI

mainboard/intel/galileo

bool

SEC + PEI Core + MemInit PEIM

FSP 1.1 implemented using SEC and PEI core

FSP_TYPE_2_0

mainboard/intel/galileo

bool

MemInit subroutine

FSP 2.0 implemented as subroutines, no EDK-II cores

FSP_TYPE_2_0_PEI

mainboard/intel/galileo

bool

SEC + PEI Core + MemInit PEIM

FSP 2.0 implemented using SEC and PEI core

FSP_DEBUG_ALL

mainboard/intel/galileo

bool

Enable all FSP debug support

Turn on debug support to display HOBS, MTRRS, SMM_MEMORY_MAP, UPD_DATA
also turn on FSP 2.0 debug support for ESRAM_LAYOUT,
FSP_CALLS_AND_STATUS, FSP_HEADER, POSTCAR_CONSOLE and VERIFY_HOBS
or FSP 1.1 DISPLAY_FSP_ENTRY_POINTS

VBOOT_WITH_CRYPTO_SHIELD

mainboard/intel/galileo

bool

Verified boot using the Crypto Shield board

Perform a verified boot using the TPM on the Crypto Shield board.

DRIVER_TPM_I2C_ADDR

mainboard/intel/galileo

hex

Address of the I2C TPM chip

I2C address of the TPM chip on the Crypto Shield board.

FMDFILE

mainboard/intel/galileo

string

FMAP description file in fmd format

The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
but in some cases more complex setups are required.

When an FMD descriptionn file is specified, the build system uses it
instead of creating a default FMAP file.

BASEBOARD_GLKRVP_LAPTOP

mainboard/intel/glkrvp

None

ON BOARD EC

This option allows you to select the on board EC to use.
Select whether the board has Intel EC or Chrome EC

Menu: Debugging

DISABLE_UART_ON_TESTPADS

mainboard/intel/dcp847ske

bool

Disable UART on testpads

Serial output requires soldering to the testpad next to
NCT5577D pin 18 (txd) and gnd.

VGA_BIOS_FILE

mainboard/intel/strago

string

The C0 version of the video bios gets computed from this name
so that they can both be added. Only the correct one for the
system will be run.

VGA_BIOS_ID

mainboard/intel/strago

string

The VGA_BIOS_ID for the C0 version of the video bios is hardcoded
in soc/intel/braswell/Makefile.inc as 8086,22b1

BOARD_EMULATION_SPIKE_UCB_RISCV

mainboard/emulation/spike-riscv.name

bool

SPIKE ucb riscv

To run coreboot in spike:

run "make" as usual

util/riscv/make-spike-elf.sh build/coreboot.{rom,elf}

spike -m1024 build/coreboot.elf

HUDSON_LEGACY_FREE

mainboard/bap/ode_e21XX

bool

Select DDR3 clock

Select your preferenced DDR3 clock setting.

Note: This option changes the total power consumption.

If unsure, use DDR3-1333.

HUDSON_LEGACY_FREE

mainboard/bap/ode_e20XX

bool

Select DDR3 clock

Select your preferred DDR3 clock setting.

Note: This option changes the total power consumption.

If unsure, use DDR3-1066.

ENABLE_DP3_DAUGHTER_CARD_IN_J120

mainboard/amd/lamar

bool

Use J120 as an additional graphics port

The PCI Express slot at J120 can be configured as an additional
DisplayPort connector using an adapter card from AMD or as a normal
PCI Express (x4) slot.

By default, the connector is configured as a PCI Express (x4) slot.

Select this option to enable the slot for use with one of AMD's
passive graphics port expander cards (only available from AMD).

(comment)

Slippy

(comment)

Octopus

(comment)

Auron

(comment)

Gru

(comment)

Cyan

(comment)

Reef

(comment)

Jecht

(comment)

Beltino

(comment)

Rambi

(comment)

Kahlee

(comment)

Poppy

(comment)

Zoombini

(comment)

Veyron

(comment)

Oak

MAINBOARD_PART_NUMBER

mainboard/google/nyan_blaze

string

BCT boot media

Which boot media to configure the BCT for.

NYAN_BLAZE_BCT_CFG_SPI

mainboard/google/nyan_blaze

bool

SPI

Configure the BCT for booting from SPI.

NYAN_BLAZE_BCT_CFG_EMMC

mainboard/google/nyan_blaze

bool

eMMC

Configure the BCT for booting from eMMC.

BOOT_DEVICE_SPI_FLASH_BUS

mainboard/google/nyan_blaze

int

SPI bus with boot media ROM

Which SPI bus the boot media is connected to.

DISPLAY_SPD_DATA

mainboard/google/cyan

bool

Display Memory Serial Presence Detect Data

When enabled displays the memory configuration data.

VGA_BIOS_FILE

mainboard/google/cyan

string

The C0 version of the video bios gets computed from this name
so that they can both be added. Only the correct one for the
system will be run.

VGA_BIOS_ID

mainboard/google/cyan

string

The VGA_BIOS_ID for the C0 version of the video bios is hardcoded
in soc/intel/braswell/Makefile.inc as 8086,22b1

FMDFILE

mainboard/google/kahlee

string

The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
but in some cases more complex setups are required.
When an fmd is specified, it overrides the default format.

DRAM_SIZE_MB

mainboard/google/smaug

int

BCT boot media

Which boot media to configure the BCT for.

SMAUG_BCT_CFG_SPI

mainboard/google/smaug

bool

SPI

Configure the BCT for booting from SPI.

SMAUG_BCT_CFG_EMMC

mainboard/google/smaug

bool

eMMC

Configure the BCT for booting from eMMC.

BOOT_DEVICE_SPI_FLASH_BUS

mainboard/google/smaug

int

SPI bus with boot media ROM

Which SPI bus the boot media is connected to.

MAINBOARD_PART_NUMBER

mainboard/google/nyan_big

string

BCT boot media

Which boot media to configure the BCT for.

NYAN_BIG_BCT_CFG_SPI

mainboard/google/nyan_big

bool

SPI

Configure the BCT for booting from SPI.

NYAN_BIG_BCT_CFG_EMMC

mainboard/google/nyan_big

bool

eMMC

Configure the BCT for booting from eMMC.

BOOT_DEVICE_SPI_FLASH_BUS

mainboard/google/nyan_big

int

SPI bus with boot media ROM

Which SPI bus the boot media is connected to.

DRAM_SIZE_MB

mainboard/google/foster

int

BCT boot media

Which boot media to configure the BCT for.

FOSTER_BCT_CFG_SPI

mainboard/google/foster

bool

SPI

Configure the BCT for booting from SPI.

FOSTER_BCT_CFG_EMMC

mainboard/google/foster

bool

eMMC

Configure the BCT for booting from eMMC.

BOOT_DEVICE_SPI_FLASH_BUS

mainboard/google/foster

int

SPI bus with boot media ROM

Which SPI bus the boot media is connected to.

MAINBOARD_PART_NUMBER

mainboard/google/nyan

string

BCT boot media

Which boot media to configure the BCT for.

NYAN_BCT_CFG_SPI

mainboard/google/nyan

bool

SPI

Configure the BCT for booting from SPI.

NYAN_BCT_CFG_EMMC

mainboard/google/nyan

bool

eMMC

Configure the BCT for booting from eMMC.

BOOT_DEVICE_SPI_FLASH_BUS

mainboard/google/nyan

int

SPI bus with boot media ROM

Which SPI bus the boot media is connected to.

UART_FOR_CONSOLE

mainboard/adi/rcc-dff

int

The Mohon Peak board uses COM2 (2f8) for the serial console.

PAYLOAD_CONFIGFILE

mainboard/adi/rcc-dff

string

The Avoton/Rangeley chip does not allow devices to write into the 0xe000
segment. This means that USB/SATA devices will not work in SeaBIOS unless
we put the SeaBIOS buffer area down in the 0x9000 segment.

BOARD_ASUS_F2A85_M_DDR3_VOLT_135

mainboard/asus/f2a85-m

bool

1.35V

Set DRR3 memory voltage to 1.35V

BOARD_ASUS_F2A85_M_DDR3_VOLT_150

mainboard/asus/f2a85-m

bool

1.50V

Set DRR3 memory voltage to 1.50V

BOARD_ASUS_F2A85_M_DDR3_VOLT_165

mainboard/asus/f2a85-m

bool

1.65V

Set DRR3 memory voltage to 1.65V

BOARD_WINNET_G170

mainboard/winnet/g170.name

bool

WinNET G170 (Neoware CA19, IGEL 2110)

G170 is a board manufactured by WinNET, used in thin clients including
HP Neoware CA19 and IGEL 2110.

BMC_INFO_LOC

mainboard/scaleway/tagada

hex

BMC information location in flash

Location of BMC SERIAL information.

NO_POST

mainboard/purism/librem_skl

int

This platform does not have any way to see POST codes
so disable them by default.

DRIVERS_PS2_KEYBOARD

mainboard/purism/librem_bdw

string

Default PS/2 Keyboard to enabled on this board.

DRIVERS_UART_8250IO

mainboard/purism/librem_bdw

string

This platform does not have any way to get standard
serial output so disable it by default.

NO_POST

mainboard/purism/librem_bdw

int

This platform does not have any way to see POST codes
so disable them by default.

(comment)

was acquired by ADLINK

ONBOARD_UARTS_RS485

mainboard/lippert/spacerunner-lx

bool

Switch on-board serial ports to RS485

If selected, both on-board serial ports will operate in RS485 mode
instead of RS232.

ONBOARD_IDE_SLAVE

mainboard/lippert/spacerunner-lx

bool

Make on-board SSD act as Slave

If selected, the on-board SSD will act as IDE Slave instead of Master.

BOARD_OLD_REVISION

mainboard/lippert/hurricane-lx

bool

Board is old pre-3.0 revision

Look on the bottom side for a number like 406-0001-30. The last 2
digits state the PCB revision (3.0 in this example). For 2.0 or older
boards choose Y, for 3.0 and newer say N.

Old revision boards need a jumper shorting the power button to
power on automatically. You may enable the button only after this
jumper has been removed. New revision boards are not restricted
in this way, and always have the power button enabled.

ONBOARD_UARTS_RS485

mainboard/lippert/hurricane-lx

bool

Switch on-board serial ports to RS485

If selected, both on-board serial ports will operate in RS485 mode
instead of RS232.

ONBOARD_UARTS_RS485

mainboard/lippert/literunner-lx

bool

Switch on-board serial ports 1 & 2 to RS485

If selected, the first two on-board serial ports will operate in RS485
mode instead of RS232.

ONBOARD_IDE_SLAVE

mainboard/lippert/literunner-lx

bool

Make on-board CF socket act as Slave

If selected, the on-board Compact Flash card socket will act as IDE
Slave instead of Master.

ONBOARD_UARTS_RS485

mainboard/lippert/roadrunner-lx

bool

Switch on-board serial ports to RS485

If selected, both on-board serial ports will operate in RS485 mode
instead of RS232.

(comment)

see under vendor LiPPERT

(comment)

WARNING: This mainboard uses LATE_CBMEM_INIT, which is deprecated

BOARD_ROMSIZE_KB_65536

mainboard

bool

ROM chip size

Select the size of the ROM chip you intend to flash coreboot on.

The build system will take care of creating a coreboot.rom file
of the matching size.

COREBOOT_ROMSIZE_KB_64

mainboard

bool

64 KB

Choose this option if you have a 64 KB ROM chip.

COREBOOT_ROMSIZE_KB_128

mainboard

bool

128 KB

Choose this option if you have a 128 KB ROM chip.

COREBOOT_ROMSIZE_KB_256

mainboard

bool

256 KB

Choose this option if you have a 256 KB ROM chip.

COREBOOT_ROMSIZE_KB_512

mainboard

bool

512 KB

Choose this option if you have a 512 KB ROM chip.

COREBOOT_ROMSIZE_KB_1024

mainboard

bool

1024 KB (1 MB)

Choose this option if you have a 1024 KB (1 MB) ROM chip.

COREBOOT_ROMSIZE_KB_2048

mainboard

bool

2048 KB (2 MB)

Choose this option if you have a 2048 KB (2 MB) ROM chip.

COREBOOT_ROMSIZE_KB_4096

mainboard

bool

4096 KB (4 MB)

Choose this option if you have a 4096 KB (4 MB) ROM chip.

COREBOOT_ROMSIZE_KB_8192

mainboard

bool

8192 KB (8 MB)

Choose this option if you have a 8192 KB (8 MB) ROM chip.

COREBOOT_ROMSIZE_KB_10240

mainboard

bool

10240 KB (10 MB)

Choose this option if you have a 10240 KB (10 MB) ROM chip.

COREBOOT_ROMSIZE_KB_12288

mainboard

bool

12288 KB (12 MB)

Choose this option if you have a 12288 KB (12 MB) ROM chip.

COREBOOT_ROMSIZE_KB_16384

mainboard

bool

16384 KB (16 MB)

Choose this option if you have a 16384 KB (16 MB) ROM chip.

COREBOOT_ROMSIZE_KB_32768

mainboard

bool

32768 KB (32 MB)

Choose this option if you have a 32768 KB (32 MB) ROM chip.

COREBOOT_ROMSIZE_KB_65536

mainboard

bool

65536 KB (64 MB)

Choose this option if you have a 65536 KB (64 MB) ROM chip.

ENABLE_POWER_BUTTON

mainboard

bool

Enable the power button

The selected mainboard can optionally have the power button tied
to ground with a jumper so that the button appears to be
constantly depressed. If this option is enabled and the jumper is
installed then the board will turn on, but turn off again after a
short timeout, usually 4 seconds.

Select Y here if you have removed the jumper and want to use an
actual power button. Select N if you have the jumper installed.

DEVICETREE

toplevel

string

This symbol allows mainboards to select a different file under their
mainboard directory for the devicetree.cb file. This allows the board
variants that need different devicetrees to be in the same directory.

Examples: "devicetree.variant.cb"
"variant/devicetree.cb"

CBFS_SIZE

toplevel

hex

Size of CBFS filesystem in ROM

This is the part of the ROM actually managed by CBFS, located at the
end of the ROM (passed through cbfstool -o) on x86 and at at the start
of the ROM (passed through cbfstool -s) everywhere else. It defaults
to span the whole ROM on all but Intel systems that use an Intel Firmware
Descriptor. It can be overridden to make coreboot live alongside other
components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
binaries.

FMDFILE

toplevel

string

fmap description file in fmd format

The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE,
but in some cases more complex setups are required.
When an fmd is specified, it overrides the default format.

CBFS_AUTOGEN_ATTRIBUTES

toplevel

bool

If this option is selected, every file in cbfs which has a constraint
regarding position or alignment will get an additional file attribute
which describes this constraint.

Menu: Chipset

(comment)

SoC

MAINBOARD_DO_DSI_INIT

soc/nvidia/tegra210

bool

Use dsi graphics interface

Initialize dsi display

MAINBOARD_DO_SOR_INIT

soc/nvidia/tegra210

bool

Use dp graphics interface

Initialize dp display

CONSOLE_SERIAL_TEGRA210_UARTA

soc/nvidia/tegra210

bool

UARTA

Serial console on UART A.

CONSOLE_SERIAL_TEGRA210_UARTB

soc/nvidia/tegra210

bool

UARTB

Serial console on UART B.

CONSOLE_SERIAL_TEGRA210_UARTC

soc/nvidia/tegra210

bool

UARTC

Serial console on UART C.

CONSOLE_SERIAL_TEGRA210_UARTD

soc/nvidia/tegra210

bool

UARTD

Serial console on UART D.

CONSOLE_SERIAL_TEGRA210_UARTE

soc/nvidia/tegra210

bool

UARTE

Serial console on UART E.

CONSOLE_SERIAL_TEGRA210_UART_ADDRESS

soc/nvidia/tegra210

hex

Map the UART names to the respective MMIO addres.

BOOTROM_SDRAM_INIT

soc/nvidia/tegra210

bool

SoC BootROM does SDRAM init with full BCT

Use during Foster LPDDR4 bringup.

TRUSTZONE_CARVEOUT_SIZE_MB

soc/nvidia/tegra210

hex

Size of Trust Zone region

Size of Trust Zone area in MiB to reserve in memory map.

TTB_SIZE_MB

soc/nvidia/tegra210

hex

Size of TTB

Maximum size of Translation Table Buffer in MiB.

SEC_COMPONENT_SIZE_MB

soc/nvidia/tegra210

hex

Size of resident EL3 components

Maximum size of resident EL3 components in MiB including BL31 and
Secure OS.

HAVE_MTC

soc/nvidia/tegra210

bool

Add external Memory controller Training Code binary

Select this option to add emc training firmware

MTC_FILE

soc/nvidia/tegra210

string

tegra mtc firmware filename

The filename of the mtc firmware

MTC_DIRECTORY

soc/nvidia/tegra210

string

Directory where MTC firmware file is located

Path to directory where MTC firmware file is located.

MTC_ADDRESS

soc/nvidia/tegra210

hex

The DRAM location where MTC firmware to be loaded in. This location
needs to be consistent with the location defined in tegra_mtc.ld

SOC_INTEL_APOLLOLAKE

soc/intel/apollolake

bool

Intel Apollolake support

SOC_INTEL_GLK

soc/intel/apollolake

bool

Intel GLK support

TPM_ON_FAST_SPI

soc/intel/apollolake

bool

TPM part is conntected on Fast SPI interface, but the LPC MMIO
TPM transactions are decoded and serialized over the SPI interface.

PCR_BASE_ADDRESS

soc/intel/apollolake

hex

This option allows you to select MMIO Base Address of sideband bus.

DCACHE_RAM_SIZE

soc/intel/apollolake

hex

The size of the cache-as-ram region required during bootblock
and/or romstage.

DCACHE_BSP_STACK_SIZE

soc/intel/apollolake

hex

The amount of anticipated stack usage in CAR by bootblock and
other stages.

ROMSTAGE_ADDR

soc/intel/apollolake

hex

The base address (in CAR) where romstage should be linked

VERSTAGE_ADDR

soc/intel/apollolake

hex

The base address (in CAR) where verstage should be linked

FSP_M_ADDR

soc/intel/apollolake

hex

The address FSP-M will be relocated to during build time

NEED_LBP2

soc/intel/apollolake

bool

Write contents for logical boot partition 2.

Write the contents from a file into the logical boot partition 2
region defined by LBP2_FMAP_NAME.

LBP2_FMAP_NAME

soc/intel/apollolake

string

Name of FMAP region to put logical boot partition 2

Name of FMAP region to write logical boot partition 2 data.

LBP2_FILE_NAME

soc/intel/apollolake

string

Path of file to write to logical boot partition 2 region

Name of file to store in the logical boot partition 2 region.

NEED_IFWI

soc/intel/apollolake

bool

Write content into IFWI region

Write the content from a file into IFWI region defined by
IFWI_FMAP_NAME.

IFWI_FMAP_NAME

soc/intel/apollolake

string

Name of FMAP region to pull IFWI into

Name of FMAP region to write IFWI.

IFWI_FILE_NAME

soc/intel/apollolake

string

Path of file to write to IFWI region

Name of file to store in the IFWI region.

NHLT_DMIC_1CH_16B

soc/intel/apollolake

bool

Include DSP firmware settings for 1 channel 16B DMIC array.

NHLT_DMIC_2CH_16B

soc/intel/apollolake

bool

Include DSP firmware settings for 2 channel 16B DMIC array.

NHLT_DMIC_4CH_16B

soc/intel/apollolake

bool

Include DSP firmware settings for 4 channel 16B DMIC array.

NHLT_MAX98357

soc/intel/apollolake

bool

Include DSP firmware settings for headset codec.

NHLT_DA7219

soc/intel/apollolake

bool

Include DSP firmware settings for headset codec.

NHLT_RT5682

soc/intel/apollolake

bool

Include DSP firmware settings for headset codec.

NHLT_RT5682

soc/intel/apollolake

bool

Cache-as-ram implementation

This option allows you to select how cache-as-ram (CAR) is set up.

CAR_NEM

soc/intel/apollolake

bool

Non-evict mode

Traditionally, CAR is set up by using Non-Evict mode. This method
does not allow CAR and cache to co-exist, because cache fills are
block in NEM mode.

CAR_CQOS

soc/intel/apollolake

bool

Cache Quality of Service

Cache Quality of Service allows more fine-grained control of cache
usage. As result, it is possible to set up portion of L2 cache for
CAR and use remainder for actual caching.

USE_APOLLOLAKE_FSP_CAR

soc/intel/apollolake

bool

Use FSP CAR

Use FSP APIs to initialize & tear down the Cache-As-Ram.

APL_SKIP_SET_POWER_LIMITS

soc/intel/apollolake

bool

Some Apollo Lake mainboards do not need the Running Average Power
Limits (RAPL) algorithm for a constant power management.
Set this config option to skip the RAPL configuration.

SOC_ESPI

soc/intel/apollolake

bool

Use eSPI bus instead of LPC

SOC_INTEL_BAYTRAIL

soc/intel/baytrail

bool

Bay Trail M/D part support.

HAVE_MRC

soc/intel/baytrail

bool

Add a Memory Reference Code binary

Select this option to add a blob containing
memory reference code.
Note: Without this binary coreboot will not work

MRC_FILE

soc/intel/baytrail

string

Intel memory refeference code path and filename

The path and filename of the file to use as System Agent
binary. Note that this points to the sandybridge binary file
which is will not work, but it serves its purpose to do builds.

DCACHE_RAM_SIZE

soc/intel/baytrail

hex

The size of the cache-as-ram region required during bootblock
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
must add up to a power of 2.

DCACHE_RAM_MRC_VAR_SIZE

soc/intel/baytrail

hex

The amount of cache-as-ram region required by the reference code.

RESET_ON_INVALID_RAMSTAGE_CACHE

soc/intel/baytrail

bool

Reset the system on S3 wake when ramstage cache invalid.

The baytrail romstage code caches the loaded ramstage program
in SMM space. On S3 wake the romstage will copy over a fresh
ramstage that was cached in the SMM space. This option determines
the action to take when the ramstage cache is invalid. If selected
the system will reset otherwise the ramstage will be reloaded from
cbfs.

ENABLE_BUILTIN_COM1

soc/intel/baytrail

bool

Enable builtin COM1 Serial Port

The PMC has a legacy COM1 serial port. Choose this option to
configure the pads and enable it. This serial port can be used for
the debug console.

HAVE_REFCODE_BLOB

soc/intel/baytrail

bool

An external reference code blob should be put into cbfs.

The reference code blob will be placed into cbfs.

REFCODE_BLOB_FILE

soc/intel/baytrail

string

Path and filename to reference code blob.

The path and filename to the file to be added to cbfs.

SOC_INTEL_BRASWELL

soc/intel/braswell

bool

Braswell M/D part support.

DCACHE_RAM_SIZE

soc/intel/braswell

hex

The size of the cache-as-ram region required during bootblock
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
must add up to a power of 2.

RESET_ON_INVALID_RAMSTAGE_CACHE

soc/intel/braswell

bool

Reset the system on S3 wake when ramstage cache invalid.

The haswell romstage code caches the loaded ramstage program
in SMM space. On S3 wake the romstage will copy over a fresh
ramstage that was cached in the SMM space. This option determines
the action to take when the ramstage cache is invalid. If selected
the system will reset otherwise the ramstage will be reloaded from
cbfs.

ENABLE_BUILTIN_COM1

soc/intel/braswell

bool

Enable builtin COM1 Serial Port

The PMC has a legacy COM1 serial port. Choose this option to
configure the pads and enable it. This serial port can be used for
the debug console.

SOC_INTEL_BROADWELL

soc/intel/broadwell

bool

Intel Broadwell and Haswell ULT support.

DCACHE_RAM_SIZE

soc/intel/broadwell

hex

The size of the cache-as-ram region required during bootblock
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
must add up to a power of 2.

DCACHE_RAM_MRC_VAR_SIZE

soc/intel/broadwell

hex

The amount of cache-as-ram region required by the reference code.

HAVE_MRC

soc/intel/broadwell

bool

Add a Memory Reference Code binary

Select this option to add a Memory Reference Code binary to
the resulting coreboot image.

Note: Without this binary coreboot will not work

MRC_FILE

soc/intel/broadwell

string

Intel Memory Reference Code path and filename

The filename of the file to use as Memory Reference Code binary.

PRE_GRAPHICS_DELAY

soc/intel/broadwell

int

Graphics initialization delay in ms

On some systems, coreboot boots so fast that connected monitors
(mostly TVs) won't be able to wake up fast enough to talk to the
VBIOS. On those systems we need to wait for a bit before executing
the VBIOS.

RESET_ON_INVALID_RAMSTAGE_CACHE

soc/intel/broadwell

bool

Reset the system on S3 wake when ramstage cache invalid.

The romstage code caches the loaded ramstage program in SMM space.
On S3 wake the romstage will copy over a fresh ramstage that was
cached in the SMM space. This option determines the action to take
when the ramstage cache is invalid. If selected the system will
reset otherwise the ramstage will be reloaded from cbfs.

SERIRQ_CONTINUOUS_MODE

soc/intel/broadwell

bool

If you set this option to y, the serial IRQ machine will be
operated in continuous mode.

The size of the cache-as-ram region required during bootblock
and/or romstage.

DCACHE_BSP_STACK_SIZE

soc/intel/cannonlake

hex

The amount of anticipated stack usage in CAR by bootblock and
other stages.

NHLT_DMIC_1CH_16B

soc/intel/cannonlake

bool

Include DSP firmware settings for 1 channel 16B DMIC array.

NHLT_DMIC_2CH_16B

soc/intel/cannonlake

bool

Include DSP firmware settings for 2 channel 16B DMIC array.

NHLT_DMIC_4CH_16B

soc/intel/cannonlake

bool

Include DSP firmware settings for 4 channel 16B DMIC array.

NHLT_MAX98357

soc/intel/cannonlake

bool

Include DSP firmware settings for headset codec.

NHLT_MAX98373

soc/intel/cannonlake

bool

Include DSP firmware settings for headset codec.

NHLT_DA7219

soc/intel/cannonlake

bool

Include DSP firmware settings for headset codec.

PCR_BASE_ADDRESS

soc/intel/cannonlake

hex

This option allows you to select MMIO Base Address of sideband bus.

STACK_SIZE

soc/intel/cannonlake

hex

Cache-as-ram implementation

This option allows you to select how cache-as-ram (CAR) is set up.

USE_CANNONLAKE_CAR_NEM_ENHANCED

soc/intel/cannonlake

bool

Enhanced Non-evict mode

A current limitation of NEM (Non-Evict mode) is that code and data
sizes are derived from the requirement to not write out any modified
cache line. With NEM, if there is no physical memory behind the
cached area, the modified data will be lost and NEM results will be
inconsistent. ENHANCED NEM guarantees that modified data is always
kept in cache while clean data is replaced.

USE_CANNONLAKE_FSP_CAR

soc/intel/cannonlake

bool

Use FSP CAR

Use FSP APIs to initialize and tear down the Cache-As-Ram.

SOC_INTEL_DENVERTON_NS

soc/intel/denverton_ns

bool

Intel Denverton-NS SoC support

FSP_T_ADDR

soc/intel/denverton_ns

hex

Intel FSP-T (temp ram init) binary location

The memory location of the Intel FSP-T binary for this platform.

FSP_M_ADDR

soc/intel/denverton_ns

hex

Intel FSP-M (memory init) binary location

The memory location of the Intel FSP-M binary for this platform.

FSP_S_ADDR

soc/intel/denverton_ns

hex

Intel FSP-S (silicon init) binary location

The memory location of the Intel FSP-S binary for this platform.

PCR_BASE_ADDRESS

soc/intel/denverton_ns

hex

This option allows you to select MMIO Base Address of sideband bus.

IQAT_MEMORY_REGION_SIZE

soc/intel/denverton_ns

hex

Do not change this value

NON_LEGACY_UART_MODE

soc/intel/denverton_ns

bool

Non Legacy Mode

Disable legacy UART mode

LEGACY_UART_MODE

soc/intel/denverton_ns

bool

Legacy Mode

Enable legacy UART mode

DENVERTON_NS_CAR_NEM_ENHANCED

soc/intel/denverton_ns

bool

Enhanced Non-evict mode

A current limitation of NEM (Non-Evict mode) is that code and data sizes
are derived from the requirement to not write out any modified cache line.
With NEM, if there is no physical memory behind the cached area,
the modified data will be lost and NEM results will be inconsistent.
ENHANCED NEM guarantees that modified data is always
kept in cache while clean data is replaced.

SOC_INTEL_FSP_BAYTRAIL

soc/intel/fsp_baytrail

bool

Bay Trail I part support using the Intel FSP.

SMM_TSEG_SIZE

soc/intel/fsp_baytrail

hex

This is set by the FSP

VGA_BIOS_ID

soc/intel/fsp_baytrail

string

This is the default PCI ID for the Bay Trail graphics
devices. This string names the vbios ROM in cbfs.

ENABLE_BUILTIN_COM1

soc/intel/fsp_baytrail

bool

Enable built-in legacy Serial Port

The Baytrail SOC has one legacy serial port. Choose this option to
configure the pads and enable it. This serial port can be used for
the debug console.

FSP_FILE

soc/intel/fsp_baytrail/fsp

string

The path and filename of the Intel FSP binary for this platform.

FSP_LOC

soc/intel/fsp_baytrail/fsp

hex

The location in CBFS that the FSP is located. This must match the
value that is set in the FSP binary. If the FSP needs to be moved,
rebase the FSP with Intel's BCT (tool).

The Bay Trail FSP is built with a preferred base address of
0xFFFC0000.

SOC_INTEL_FSP_BROADWELL_DE

soc/intel/fsp_broadwell_de

bool

Broadwell-DE support using the Intel FSP.

INTEGRATED_UART

soc/intel/fsp_broadwell_de

bool

Integrated UART ports

Use Broadwell-DE Integrated UART ports @3F8h and 2F8h.

SERIRQ_CONTINUOUS_MODE

soc/intel/fsp_broadwell_de

bool

If you set this option to y, the serial IRQ machine will be
operated in continuous mode.

FSP_FILE

soc/intel/fsp_broadwell_de/fsp

string

The path and filename of the Intel FSP binary for this platform.

FSP_LOC

soc/intel/fsp_broadwell_de/fsp

hex

The location in CBFS that the FSP is located. This must match the
value that is set in the FSP binary. If the FSP needs to be moved,
rebase the FSP with Intel's BCT (tool).

The Broadwell-DE FSP is built with a preferred base address of
0xffeb0000.

DCACHE_RAM_BASE

soc/intel/fsp_broadwell_de/fsp

hex

This address needs to match the setup performed inside FSP.
On Broadwell-DE the FSP allocates temporary RAM starting at 0xfe100000.

DCACHE_RAM_SIZE

soc/intel/fsp_broadwell_de/fsp

hex

The DCACHE is shared between FSP itself and the rest of the coreboot
stages. A size of 0x8000 works fine while providing enough space for
features like VBOOT in verstage. Further increase to a power of two
aligned value leads to errors in FSP.

FSP_MEMORY_DOWN

soc/intel/fsp_broadwell_de/fsp

bool

Enable Memory Down

Load SPD data from ROM instead of trying to read from SMBus.

If the platform has DIMM sockets, say N. If memory is down, say Y and
supply the appropriate SPD data for each Channel/DIMM.

FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT

soc/intel/fsp_broadwell_de/fsp

bool

Channel 0, DIMM 0 Present

Select Y if Channel 0, DIMM 0 is present.

FSP_MEMORY_DOWN_CH0DIMM0_SPD_FILE

soc/intel/fsp_broadwell_de/fsp

string

Channel 0, DIMM 0 SPD File

Path to the file which contains the SPD data for Channel 0, DIMM 0.

FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT

soc/intel/fsp_broadwell_de/fsp

bool

Channel 0, DIMM 1 Present

Select Y if Channel 0, DIMM 1 is present.

FSP_MEMORY_DOWN_CH0DIMM1_SPD_FILE

soc/intel/fsp_broadwell_de/fsp

string

Channel 0, DIMM 1 SPD File

Path to the file which contains the SPD data for Channel 0, DIMM 1.

FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT

soc/intel/fsp_broadwell_de/fsp

bool

Channel 1, DIMM 0 Present

Select Y if Channel 1, DIMM 0 is present.

FSP_MEMORY_DOWN_CH1DIMM0_SPD_FILE

soc/intel/fsp_broadwell_de/fsp

string

Channel 1, DIMM 0 SPD File

Path to the file which contains the SPD data for Channel 1, DIMM 0.

FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT

soc/intel/fsp_broadwell_de/fsp

bool

Channel 1, DIMM 1 Present

Select Y if Channel 1, DIMM 1 is present.

FSP_MEMORY_DOWN_CH1DIMM1_SPD_FILE

soc/intel/fsp_broadwell_de/fsp

string

Channel 1, DIMM 1 SPD File

Path to the file which contains the SPD data for Channel 1, DIMM 1.

FSP_HYPERTHREADING

soc/intel/fsp_broadwell_de/fsp

bool

Enable Hyper-Threading

Enable Intel(r) Hyper-Threading Technology for the Broadwell-DE SoC.

FSP_EHCI1_ENABLE

soc/intel/fsp_broadwell_de/fsp

bool

EHCI1 Enable

Enable EHCI controller 1

FSP_EHCI2_ENABLE

soc/intel/fsp_broadwell_de/fsp

bool

EHCI2 Enable

Enable EHCI controller 2

SOC_INTEL_QUARK

soc/intel/quark

bool

Intel Quark support

ENABLE_BUILTIN_HSUART0

soc/intel/quark

bool

Enable built-in HSUART0

The Quark SoC has two HSUART. Choose this option to configure the pads
and enable HSUART0, which can be used for the debug console.

ENABLE_BUILTIN_HSUART1

soc/intel/quark

bool

Enable built-in HSUART1

The Quark SoC has two HSUART. Choose this option to configure the pads
and enable HSUART1, which can be used for the debug console.

TTYS0_BASE

soc/intel/quark

hex

HSUART Base Address

Memory mapped MMIO of HSUART.

ENABLE_DEBUG_LED

soc/intel/quark

bool

Enable the use of the SD LED for early debugging before serial output
is available. Setting this LED indicates that control has reached the
desired check point.

ENABLE_DEBUG_LED_ESRAM

soc/intel/quark

bool

SD LED indicates ESRAM initialized

Indicate that ESRAM has been successfully initialized. If the SD LED
does not light then the ESRAM initialization needs to be debugged.

ENABLE_DEBUG_LED_FINDFSP

soc/intel/quark

bool

SD LED indicates fsp.bin file was found

Indicate that fsp.bin was found. If the SD LED does not light then
the code between ESRAM initialization through find_fsp needs to
debugged. Start by verifying that the correct fsp.bin is in the
image.

ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY

soc/intel/quark

bool

SD LED indicates bootblock.c successfully entered

Indicate that bootblock_c_entry was entered. If the SD LED does not
light then debug the code between ESRAM and bootblock_c_entry. For
FSP 1.1, use ENABLE_DEBUG_LED_FINDFSP to split this code.

ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY

soc/intel/quark

bool

SD LED indicates bootblock_soc_early_init successfully entered

Indicate that bootblock_soc_early_init was entered. If the SD LED
does not light then debug the code in bootblock_main_with_timestamp.

ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT

soc/intel/quark

bool

SD LED indicates bootblock_soc_early_init successfully exited

Indicate that bootblock_soc_early_init exited. If the SD LED does not
light then debug the scripts in bootblock_soc_early_init.

ENABLE_DEBUG_LED_SOC_INIT_ENTRY

soc/intel/quark

bool

SD LED indicates bootblock_soc_init successfully entered

Indicate that bootblock_soc_init was entered. If the SD LED does not
light then debug the code in bootblock_mainboard_early_init and
console_init. If the SD LED does light but there is no serial then
debug the serial port configuration and initialization.

DISPLAY_ESRAM_LAYOUT

soc/intel/quark

bool

Display ESRAM layout

Select this option to display coreboot's use of ESRAM.

CBFS_SIZE

soc/intel/quark

hex

Specify the size of the coreboot file system in the read-only (recovery)
portion of the flash part. On Quark systems the firmware image stores
more than just coreboot, including:
- The chipset microcode (RMU) binary file located at 0xFFF00000
- Intel Trusted Execution Engine firmware

ADD_FSP_RAW_BIN

soc/intel/quark

bool

Add the Intel FSP binary to the flash image without relocation

Select this option to add an Intel FSP binary to
the resulting coreboot image.

Note: Without this binary, coreboot builds relying on the FSP
will not boot

FSP_FILE

soc/intel/quark

string

Intel FSP binary path and filename

The path and filename of the Intel FSP binary for this platform.

FSP_LOC

soc/intel/quark

hex

The location in CBFS that the FSP is located. This must match the
value that is set in the FSP binary. If the FSP needs to be moved,
rebase the FSP with Intel's BCT (tool).

FSP_ESRAM_LOC

soc/intel/quark

hex

The location in ESRAM where a copy of the FSP binary is placed.

RELOCATE_FSP_INTO_DRAM

soc/intel/quark

bool

Relocate FSP into DRAM

Relocate the FSP binary into DRAM before the call to SiliconInit.

ADD_RMU_FILE

soc/intel/quark

bool

Should the RMU binary be added to the flash image?

The RMU file is required to get the chip out of reset.

RMU_FILE

soc/intel/quark

string

The path and filename of the Intel Quark RMU binary.

RMU_LOC

soc/intel/quark

hex

The location in CBFS that the RMU is located. It must match the
strap-determined base address.

STORAGE_TEST

soc/intel/quark

bool

Test SD/MMC/eMMC card or device access

Read block 0 from each parition of the storage device. User
must also enable one or both of COMMONLIB_STORAGE_SD or
COMMONLIB_STORAGE_MMC.

I2C_DEBUG

soc/intel/quark

bool

Enable I2C debugging

Display the I2C segments and controller errors

SOC_INTEL_SKYLAKE

soc/intel/skylake

bool

Intel Skylake support

SOC_INTEL_KABYLAKE

soc/intel/skylake

bool

Intel Kabylake support

DCACHE_RAM_SIZE

soc/intel/skylake

hex

The size of the cache-as-ram region required during bootblock
and/or romstage.

DCACHE_BSP_STACK_SIZE

soc/intel/skylake

hex

The amount of anticipated stack usage in CAR by bootblock and
other stages.

EXCLUDE_NATIVE_SD_INTERFACE

soc/intel/skylake

bool

If you set this option to n, will not use native SD controller.

PCR_BASE_ADDRESS

soc/intel/skylake

hex

This option allows you to select MMIO Base Address of sideband bus.

SERIRQ_CONTINUOUS_MODE

soc/intel/skylake

bool

If you set this option to y, the serial IRQ machine will be
operated in continuous mode.

A current limitation of NEM (Non-Evict mode) is that code and data
sizes are derived from the requirement to not write out any modified
cache line. With NEM, if there is no physical memory behind the
cached area, the modified data will be lost and NEM results will be
inconsistent. ENHANCED NEM guarantees that modified data is always
kept in cache while clean data is replaced.

The mapping of addresses via the SBREG_BAR assumes the IOSF-SB
agents are using 32-bit aligned accesses for their configuration
registers. For IOSF versions greater than 1_0, IOSF-SB
agents can use any access (8/16/32 bit aligned) for their
configuration registers

SOC_INTEL_COMMON_BLOCK_ACPI

soc/intel/common/block/acpi

bool

Intel Processor common code for ACPI

SOC_INTEL_COMMON_BLOCK_RTC

soc/intel/common/block/rtc

bool

Intel Processor common RTC support

SOC_INTEL_COMMON_BLOCK_CPU

soc/intel/common/block/cpu

bool

This option selects Intel Common CPU Model support code
which provides various CPU related APIs which are common
between all Intel Processor families. Common CPU code is supported
for SOCs starting from SKL,KBL,APL, and future.

SOC_INTEL_COMMON_BLOCK_CPU_MPINIT

soc/intel/common/block/cpu

bool

This option selects Intel Common CPU MP Init code. In
this common MP Init mechanism, the MP Init is occurring before
calling FSP Silicon Init. Hence, MP Init will be pulled to
BS_DEV_INIT_CHIPS Entry. And on Exit of BS_DEV_INIT, it is
ensured that all MTRRs are re-programmed based on the DRAM
resource settings.

SOC_INTEL_COMMON_BLOCK_CAR

soc/intel/common/block/cpu

bool

This option allows you to select how cache-as-ram (CAR) is set up.

INTEL_CAR_NEM

soc/intel/common/block/cpu

bool

Traditionally, CAR is set up by using Non-Evict mode. This method
does not allow CAR and cache to co-exist, because cache fills are
blocked in NEM.

INTEL_CAR_CQOS

soc/intel/common/block/cpu

bool

Cache Quality of Service allows more fine-grained control of cache
usage. As result, it is possible to set up a portion of L2 cache for
CAR and use the remainder for actual caching.

INTEL_CAR_NEM_ENHANCED

soc/intel/common/block/cpu

bool

A current limitation of NEM (Non-Evict mode) is that code and data sizes
are derived from the requirement to not write out any modified cache line.
With NEM, if there is no physical memory behind the cached area,
the modified data will be lost and NEM results will be inconsistent.
ENHANCED NEM guarantees that modified data is always
kept in cache while clean data is replaced.

Intel Processor common code for Power Management controller(PMC)
subsystem

POWER_STATE_OFF_AFTER_FAILURE

soc/intel/common/block/pmc

bool

S5 Soft Off

Choose this option if you want to keep system into
S5 after reapplying power after failure

POWER_STATE_ON_AFTER_FAILURE

soc/intel/common/block/pmc

bool

S0 Full On

Choose this option if you want to keep system into
S0 after reapplying power after failure

POWER_STATE_PREVIOUS_AFTER_FAILURE

soc/intel/common/block/pmc

bool

Keep Previous State

Choose this option if you want to keep system into
same power state as before failure even after reapplying
power

PMC_INVALID_READ_AFTER_WRITE

soc/intel/common/block/pmc

bool

Enable this for PMC devices where a read back of ACPI BAR and
IO access bit does not return the previously written value.

SOC_INTEL_COMMON_BLOCK_SMBUS

soc/intel/common/block/smbus

bool

Intel Processor common SMBus support

SOC_INTEL_COMMON_BLOCK_GPIO

soc/intel/common/block/gpio

bool

Intel Processor common GPIO support

DEBUG_SOC_COMMON_BLOCK_GPIO

soc/intel/common/block/gpio

bool

Output verbose GPIO debug messages

This option enables GPIO debug messages

SOC_INTEL_COMMON_BLOCK_SGX

soc/intel/common/block/sgx

bool

Software Guard eXtension(SGX) Feature. Intel SGX is a set of new CPU
instructions that can be used by applications to set aside private
regions of code and data.

SOC_INTEL_COMMON_BLOCK_DSP

soc/intel/common/block/dsp

bool

Intel Processor common DSP support

SOC_INTEL_COMMON_BLOCK_I2C

soc/intel/common/block/i2c

bool

Intel Processor Common I2C support

SOC_INTEL_COMMON_BLOCK_I2C_DEBUG

soc/intel/common/block/i2c

bool

Enable debug output for LPSS I2C transactions

Enable debug output for I2C transactions. This can be useful
when debugging I2C drivers.

SOC_INTEL_COMMON_BLOCK_SRAM

soc/intel/common/block/sram

bool

Intel Processor common SRAM support

SOC_INTEL_COMMON_BLOCK_ITSS

soc/intel/common/block/itss

bool

Intel Processor common interrupt timer subsystem support

SOC_INTEL_COMMON_BLOCK_GRAPHICS

soc/intel/common/block/graphics

bool

Intel Processor common Graphics support

ACPI_CONSOLE

soc/intel/common

bool

Provide a mechanism for serial console based ACPI debug.

MMA

soc/intel/common

bool

Enable MMA (Memory Margin Analysis) support for Intel Core

Set this option to y to enable MMA (Memory Margin Analysis) support

TPM_TIS_ACPI_INTERRUPT

soc/intel/common

int

acpi_get_gpe() is used to provide interrupt status to TPM layer.
This option specifies the GPE number.

SOC_AMD_STONEYRIDGE_FP4

soc/amd/stoneyridge

bool

AMD Stoney Ridge FP4 support

SOC_AMD_STONEYRIDGE_FT4

soc/amd/stoneyridge

bool

AMD Stoney Ridge FT4 support

DCACHE_BSP_STACK_SIZE

soc/amd/stoneyridge

hex

The amount of anticipated stack usage in CAR by bootblock and
other stages.

PRERAM_CBMEM_CONSOLE_SIZE

soc/amd/stoneyridge

hex

Increase this value if preram cbmem console is getting truncated

BOTTOMIO_POSITION

soc/amd/stoneyridge

hex

Bottom of 32-bit IO space

If PCI peripherals with big BARs are connected to the system
the bottom of the IO must be decreased to allocate such
devices.

Declare the beginning of the 128MB-aligned MMIO region. This
option is useful when PCI peripherals requesting large address
ranges are present.

VGA_BIOS_ID

soc/amd/stoneyridge

string

The default VGA BIOS PCI vendor/device ID should be set to the
result of the map_oprom_vendev() function in northbridge.c.

STONEYRIDGE_XHCI_ENABLE

soc/amd/stoneyridge

bool

Enable Stoney Ridge XHCI Controller

The XHCI controller must be enabled and the XHCI firmware
must be added in order to have USB 3.0 support configured
by coreboot. The OS will be responsible for enabling the XHCI
controller if the the XHCI firmware is available but the
XHCI controller is not enabled by coreboot.

STONEYRIDGE_XHCI_FWM

soc/amd/stoneyridge

bool

Add xhci firmware

Add Stoney Ridge XHCI Firmware to support the onboard USB 3.0

STONEYRIDGE_IMC_FWM

soc/amd/stoneyridge

bool

Add IMC firmware

Add Stoney Ridge IMC Firmware to support the onboard fan control

STONEYRIDGE_GEC_FWM

soc/amd/stoneyridge

bool

Add Stoney Ridge GEC Firmware to support the onboard gigabit Ethernet MAC.
Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.

STONEYRIDGE_SATA_MODE

soc/amd/stoneyridge

int

SATA Mode

Select the mode in which SATA should be driven.
The default is NATIVE.
0: NATIVE mode does not require a ROM.
2: AHCI may work with or without AHCI ROM. It depends on the payload support.
For example, seabios does not require the AHCI ROM.
3: LEGACY IDE
4: IDE to AHCI
5: AHCI7804: ROM Required, and AMD driver required in the OS.
6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.

(comment)

NATIVE

(comment)

AHCI

(comment)

LEGACY IDE

(comment)

IDE to AHCI

(comment)

AHCI7804

(comment)

IDE to AHCI7804

STONEYRIDGE_LEGACY_FREE

soc/amd/stoneyridge

bool

System is legacy free

Select y if there is no keyboard controller in the system.
This sets variables in AGESA and ACPI.

SERIRQ_CONTINUOUS_MODE

soc/amd/stoneyridge

bool

Set this option to y for serial IRQ in continuous mode.
Otherwise it is in quiet mode.

STONEYRIDGE_ACPI_IO_BASE

soc/amd/stoneyridge

hex

Base address for the ACPI registers.
This value must match the hardcoded value of AGESA.

STONEYRIDGE_UART

soc/amd/stoneyridge

bool

UART controller on Stoney Ridge

There are two UART controllers in Stoney Ridge.
The UART registers are memory-mapped. UART
controller 0 registers range from FEDC_6000h
to FEDC_6FFFh. UART controller 1 registers
range from FEDC_8000h to FEDC_8FFFh.

USE_PSPSCUREOS

soc/amd/stoneyridge

bool

Include PSP SecureOS blobs in AMD firmware

Include the PspSecureOs, PspTrustlet and TrustletKey binaries
in the amdfw section.

If unsure, answer 'y'

AMDFW_OUTSIDE_CBFS

soc/amd/stoneyridge

bool

The AMD firmware is outside CBFS

The AMDFW (PSP) is typically locatable in cbfs. Select this
option to manually attach the generated amdfw.rom outside of
cbfs. The location is selected by the FWM position.

This option determines what state to go to once power is restored
after having been lost in S0. Select this option to automatically
return to S0. Otherwise the system will remain in S5 once power
is restored.

VENDORCODE_FULL_SUPPORT

soc/amd/stoneyridge

int

This option determines if all files under
vendorcode/amd/pi/00670F00/ will be compiled or only
selected procedures of source files (minimum required).

SOC_AMD_COMMON

soc/amd/common

bool

common code for AMD SOCs

SOC_AMD_COMMON_BLOCK

soc/amd/common/block

bool

SoC driver for AMD common IP code

(comment)

AMD SoC Common IP Code

SOC_AMD_COMMON_BLOCK_S3

soc/amd/common/block/s3

bool

Select this option to add S3 related functions to the build.

SOC_AMD_COMMON_BLOCK_PI

soc/amd/common/block/pi

bool

This option builds functions that interface AMD's AGESA.

SOC_AMD_COMMON_BLOCK_PCI

soc/amd/common/block/pci

bool

This option builds functions used to program PCI interrupt
routing, both PIC and APIC modes.

SOC_AMD_COMMON_BLOCK_CAR

soc/amd/common/block/cpu

bool

This option allows the SOC to use a standard AMD cache-as-ram (CAR)
implementation. CAR setup is built into bootblock and teardown is
in postcar. The teardown procedure does not preserve the stack so
it may not be appropriate for a romstage implementation without
additional consideration. If this option is not used, the SOC must
implement these functions separately.

SOC_AMD_COMMON_BLOCK_PSP

soc/amd/common/block/psp

bool

This option builds in the Platform Security Processor initialization
functions.

SOC_AMD_PSP_SELECTABLE_SMU_FW

soc/amd/common/block/psp

bool

Some PSP implementations allow storing SMU firmware into cbfs and
calling the PSP to load the blobs at the proper time.

The soc/<codename> should select this if its PSP supports the feature
and each mainboard can choose to select an appropriate fanless or
fanned set of blobs. Ask your AMD representative whether your APU
is considered fanless.

The path and filename of the binary blob containing
ipq40xx early initialization code, as supplied by the
vendor.

SBL_UTIL_PATH

soc/qualcomm/ipq40xx

string

Path for utils to combine SBL_ELF and bootblock

Path for utils to combine SBL_ELF and bootblock

SBL_BLOB

soc/qualcomm/ipq806x

string

file name of the Qualcomm SBL blob

The path and filename of the binary blob containing
ipq806x early initialization code, as supplied by the
vendor.

RK3399_SPREAD_SPECTRUM_DDR

soc/rockchip/rk3399

bool

Spread-spectrum DDR clock

Select Spread Spectrum Modulator (SSMOD) is a fully-digital circuit
used to modulate the frequency of the Silicon Creations' Fractional
PLL in order to reduce EMI.

(comment)

CPU

RESET_ON_INVALID_RAMSTAGE_CACHE

cpu/intel/haswell

bool

Reset the system on S3 wake when ramstage cache invalid.

The haswell romstage code caches the loaded ramstage program
in SMM space. On S3 wake the romstage will copy over a fresh
ramstage that was cached in the SMM space. This option determines
the action to take when the ramstage cache is invalid. If selected
the system will reset otherwise the ramstage will be reloaded from
cbfs.

CPU_INTEL_FIRMWARE_INTERFACE_TABLE

cpu/intel/fit

None

This option selects building a Firmware Interface Table (FIT).

CPU_INTEL_NUM_FIT_ENTRIES

cpu/intel/fit

int

This option selects the number of empty entries in the FIT table.

CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED

cpu/intel/turbo

None

This option indicates that the turbo mode setting is not package
scoped. i.e. enable_turbo() needs to be called on not just the bsp

SET_VMX_LOCK_BIT

cpu/intel/common

bool

Set lock bit after configuring VMX

Although the Intel manual says you must set the lock bit in addition
to the VMX bit in order for VMX to work, this isn't strictly true, so
we have the option to leave it unlocked and allow the OS (e.g. Linux)
to manage things itself. This is beneficial for testing purposes as
there is no need to reflash the firmware just to toggle the lock bit.
However, leaving the lock bit unset will break Windows' detection of
VMX support and built-in virtualization features like Hyper-V.

GEODE_VSA_FILE

cpu/amd/geode_lx

bool

Add a VSA image

Select this option if you have an AMD Geode LX vsa that you would
like to add to your ROM.

You will be able to specify the location and file name of the
image later.

VSA_FILENAME

cpu/amd/geode_lx

string

AMD Geode LX VSA path and filename

The path and filename of the file to use as VSA.

XIP_ROM_SIZE

cpu/amd/agesa

hex

Overwride the default write through caching size as 1M Bytes.
On some AMD platforms, one socket supports 2 or more kinds of
processor family, compiling several CPU families agesa code
will increase the romstage size.
In order to execute romstage in place on the flash ROM,
more space is required to be set as write through caching.

ENABLE_MRC_CACHE

cpu/amd/agesa

bool

Use cached memory configuration

Try to restore memory training results
from non-volatile memory.

FORCE_AM1_SOCKET_SUPPORT

cpu/amd/agesa/family16kb

bool

Force AGESA to ignore package type mismatch between CPU and northbridge
in memory code. This enables Socket AM1 support with current AGESA
version for Kabini platform.
Enable this option only if you have Socket AM1 board.
Note that the AGESA release shipped with coreboot does not officially
support the AM1 socket. Selecting this option might damage your hardware.

XIP_ROM_SIZE

cpu/amd/pi

hex

Overwride the default write through caching size as 1M Bytes.
On some AMD platforms, one socket supports 2 or more kinds of
processor family, compiling several CPU families agesa code
will increase the romstage size.
In order to execute romstage in place on the flash ROM,
more space is required to be set as write through caching.

PARALLEL_MP

cpu/x86

bool

This option uses common MP infrastructure for bringing up APs
in parallel. It additionally provides a more flexible mechanism
for sequencing the steps of bringing up the APs.

PARALLEL_MP_AP_WORK

cpu/x86

bool

Allow APs to do other work after initialization instead of going
to sleep.

LAPIC_MONOTONIC_TIMER

cpu/x86

bool

Expose monotonic time using the local APIC.

TSC_CONSTANT_RATE

cpu/x86

bool

This option asserts that the TSC ticks at a known constant rate.
Therefore, no TSC calibration is required.

TSC_MONOTONIC_TIMER

cpu/x86

bool

Expose monotonic time using the TSC.

TSC_SYNC_LFENCE

cpu/x86

bool

The CPU driver should select this if the CPU needs
to execute an lfence instruction in order to synchronize
rdtsc. This is true for all modern AMD CPUs.

TSC_SYNC_MFENCE

cpu/x86

bool

The CPU driver should select this if the CPU needs
to execute an mfence instruction in order to synchronize
rdtsc. This is true for all modern Intel CPUs.

NO_FIXED_XIP_ROM_SIZE

cpu/x86

bool

The XIP_ROM_SIZE Kconfig variable is used globally on x86
with the assumption that all chipsets utilize this value.
For the chipsets which do not use the variable it can lead
to unnecessary alignment constraints in cbfs for romstage.
Therefore, allow those chipsets a path to not be burdened.

SMM_MODULE_HEAP_SIZE

cpu/x86

hex

This option determines the size of the heap within the SMM handler
modules.

SERIALIZED_SMM_INITIALIZATION

cpu/x86

bool

On some CPUs, there is a race condition in SMM.
This can occur when both hyperthreads change SMM state
variables in parallel without coordination.
Setting this option serializes the SMM initialization
to avoid an ugly hang in the boot process at the cost
of a slightly longer boot time.

X86_AMD_FIXED_MTRRS

cpu/x86

bool

This option informs the MTRR code to use the RdMem and WrMem fields
in the fixed MTRR MSRs.

PLATFORM_USES_FSP1_0

cpu/x86

bool

Selected for Intel processors/platform combinations that use the
Intel Firmware Support Package (FSP) 1.0 for initialization.

MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING

cpu/x86

bool

On certain platforms a boot speed gain can be realized if mirroring
the payload data stored in non-volatile storage. On x86 systems the
payload would typically live in a memory-mapped SPI part. Copying
the SPI contents to RAM before performing the load can speed up
the boot process.

SOC_SETS_MSRS

cpu/x86

bool

The SoC requires different access methods for reading and writing
the MSRs. Use SoC specific routines to handle the MSR access.

NO_CAR_GLOBAL_MIGRATION

cpu

bool

This option is selected if there is no need to migrate CAR globals.
All stages which use CAR globals can directly access the variables
from their linked addresses.

SMP

cpu

bool

This option is used to enable certain functions to make coreboot
work correctly on symmetric multi processor (SMP) systems.

AP_SIPI_VECTOR

cpu

hex

This must equal address of ap_sipi_vector from bootblock build.

MMX

cpu

bool

Select MMX in your socket or model Kconfig if your CPU has MMX
streaming SIMD instructions. ROMCC can build more efficient
code if it can spill to MMX registers.

SSE

cpu

bool

Select SSE in your socket or model Kconfig if your CPU has SSE
streaming SIMD instructions. ROMCC can build more efficient
code if it can spill to SSE (aka XMM) registers.

SSE2

cpu

bool

Select SSE2 in your socket or model Kconfig if your CPU has SSE2
streaming SIMD instructions. Some parts of coreboot can be built
with more efficient code if SSE2 instructions are available.

USES_MICROCODE_HEADER_FILES

cpu

bool

This is selected by a board or chipset to set the default for the
microcode source choice to a list of external microcode headers

CPU_MICROCODE_CBFS_GENERATE

cpu

bool

Generate from tree

Select this option if you want microcode updates to be assembled when
building coreboot and included in the final image as a separate CBFS
file. Microcode will not be hard-coded into ramstage.

The microcode file may be removed from the ROM image at a later
time with cbfstool, if desired.

If unsure, select this option.

CPU_MICROCODE_CBFS_EXTERNAL_HEADER

cpu

bool

Include external microcode header files

Select this option if you want to include external c header files
containing the CPU microcode. This will be included as a separate
file in CBFS.

A word of caution: only select this option if you are sure the
microcode that you have is newer than the microcode shipping with
coreboot.

The microcode file may be removed from the ROM image at a later
time with cbfstool, if desired.

If unsure, select "Generate from tree"

CPU_MICROCODE_CBFS_NONE

cpu

bool

Do not include microcode updates

Select this option if you do not want CPU microcode included in CBFS.
Note that for some CPUs, the microcode is hard-coded into the source
tree and is not loaded from CBFS. In this case, microcode will still
be updated. There is a push to move all microcode to CBFS, but this
change is not implemented for all CPUs.

Microcode may be added to the ROM image at a later time with cbfstool,
if desired.

If unsure, select "Generate from tree"

The GOOD:
Microcode updates intend to solve issues that have been discovered
after CPU production. The expected effect is that systems work as
intended with the updated microcode, but we have also seen cases where
issues were solved by not applying microcode updates.

The BAD:
Note that some operating system include these same microcode patches,
so you may need to also disable microcode updates in your operating
system for this option to have an effect.

The UGLY:
A word of CAUTION: some CPUs depend on microcode updates to function
correctly. Not updating the microcode may leave the CPU operating at
less than optimal performance, or may cause outright hangups.
There are CPUs where coreboot cannot properly initialize the CPU
without microcode updates
For example, if running with the factory microcode, some Intel
SandyBridge CPUs may hang when enabling CAR, or some VIA Nano CPUs
will hang when changing the frequency.

Make sure you have a way of flashing the ROM externally before
selecting this option.

CPU_MICROCODE_MULTIPLE_FILES

cpu

bool

Select this option to install separate microcode container files into
CBFS instead of using the traditional monolithic microcode file format.

CPU_MICROCODE_HEADER_FILES

cpu

string

List of space separated microcode header files with the path

A list of one or more microcode header files with path from the
coreboot directory. These should be separated by spaces.

CPU_UCODE_BINARIES

cpu

string

Microcode binary path and filename

Some platforms have microcode in the blobs directory, and these can
be hardcoded in the makefiles. For platforms with microcode
binaries that aren't in the makefile, set this option to pull
in the microcode.

This should contain the full path of the file for one or more
microcode binary files to include, separated by spaces.

If unsure, leave this blank.

(comment)

Northbridge

I945_LVDS

northbridge/intel/i945

string

Selected by mainboards that use native graphics initialization
for the LVDS port. A linear framebuffer is only supported for
LVDS.

OVERRIDE_CLOCK_DISABLE

northbridge/intel/i945

bool

Usually system firmware turns off system memory clock
signals to unused SO-DIMM slots to reduce EMI and power
consumption.
However, some boards do not like unused clock signals to
be disabled.

MAXIMUM_SUPPORTED_FREQUENCY

northbridge/intel/i945

int

If non-zero, this designates the maximum DDR frequency
the board supports, despite what the chipset should be
capable of.

CHECK_SLFRCS_ON_RESUME

northbridge/intel/i945

int

On some boards it may be neccessary to hard reset early
during resume from S3 if the SLFRCS register indicates that
a memory channel is not guaranteed to be in self-refresh.
On other boards the check always creates a false positive,
effectively making it impossible to resume.

USE_NATIVE_RAMINIT

northbridge/intel/sandybridge

bool

Use native raminit

Select if you want to use coreboot implementation of raminit rather than
System Agent/MRC.bin. You should answer Y.

NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES

northbridge/intel/sandybridge

bool

Ignore vendor programmed fuses that limit max. DRAM frequency

Ignore the mainboard's vendor programmed fuses that might limit the
maximum DRAM frequency. By selecting this option the fuses will be
ignored and the only limits on DRAM frequency are set by RAM's SPD and
hard fuses in southbridge's clockgen.
Disabled by default as it might causes system instability.
Handle with care!

NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS

northbridge/intel/sandybridge

bool

Ignore XMP profile max DIMMs per channel

Ignore the max DIMMs per channel restriciton defined in XMP profiles.
Disabled by default as it might cause system instability.
Handle with care!

MMCONF_BASE_ADDRESS

northbridge/intel/sandybridge

hex

The MRC blob requires it to be at 0xf0000000.

MRC_FILE

northbridge/intel/sandybridge

string

Intel System Agent path and filename

The path and filename of the file to use as System Agent
binary.

DCACHE_RAM_SIZE

northbridge/intel/haswell

hex

The size of the cache-as-ram region required during bootblock
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
must add up to a power of 2.

DCACHE_RAM_MRC_VAR_SIZE

northbridge/intel/haswell

hex

The amount of cache-as-ram region required by the reference code.

DCACHE_RAM_ROMSTAGE_STACK_SIZE

northbridge/intel/haswell

hex

The amount of anticipated stack usage from the data cache
during pre-ram ROM stage execution.

HAVE_MRC

northbridge/intel/haswell

bool

Add a System Agent binary

Select this option to add a System Agent binary to
the resulting coreboot image.

Note: Without this binary coreboot will not work

MRC_FILE

northbridge/intel/haswell

string

Intel System Agent path and filename

The path and filename of the file to use as System Agent
binary.

PRE_GRAPHICS_DELAY

northbridge/intel/haswell

int

Graphics initialization delay in ms

On some systems, coreboot boots so fast that connected monitors
(mostly TVs) won't be able to wake up fast enough to talk to the
VBIOS. On those systems we need to wait for a bit before executing
the VBIOS.

VGA_BIOS_ID

northbridge/intel/fsp_sandybridge

string

This is the default PCI ID for the sandybridge/ivybridge graphics
devices. This string names the vbios ROM in cbfs. The following
PCI IDs will be remapped to load this ROM:
0x80860102, 0x8086010a, 0x80860112, 0x80860116
0x80860122, 0x80860126, 0x80860166

FSP_FILE

northbridge/intel/fsp_sandybridge/fsp

string

The path and filename of the Intel FSP binary for this platform.

FSP_LOC

northbridge/intel/fsp_sandybridge/fsp

hex

Intel FSP Binary location in CBFS

The location in CBFS that the FSP is located. This must match the
value that is set in the FSP binary. If the FSP needs to be moved,
rebase the FSP with the Intel's BCT (tool).

The Ivy Bridge Processor/Panther Point FSP is built with a preferred
base address of 0xFFF80000

SDRAMPWR_4DIMM

northbridge/intel/i440bx

bool

This option affects how the SDRAMC register is programmed.
Memory clock signals will not be routed properly if this option
is set wrong.

If your board has 4 DIMM slots, you must use select this option, in
your Kconfig file of the board. On boards with 3 DIMM slots,
do _not_ select this option.

SET_TSEG_1MB

northbridge/intel/fsp_rangeley

bool

1 MB

Set the TSEG area to 1 MB.

SET_TSEG_2MB

northbridge/intel/fsp_rangeley

bool

2 MB

Set the TSEG area to 2 MB.

SET_TSEG_4MB

northbridge/intel/fsp_rangeley

bool

4 MB

Set the TSEG area to 4 MB.

SET_TSEG_8MB

northbridge/intel/fsp_rangeley

bool

8 MB

Set the TSEG area to 8 MB.

FSP_FILE

northbridge/intel/fsp_rangeley/fsp

string

The path and filename of the Intel FSP binary for this platform.

FSP_LOC

northbridge/intel/fsp_rangeley/fsp

hex

The location in CBFS that the FSP is located. This must match the
value that is set in the FSP binary. If the FSP needs to be moved,
rebase the FSP with Intel's BCT (tool).

The Rangeley FSP is built with a preferred base address of 0xFFF80000

BOTTOMIO_POSITION

northbridge/amd/pi

hex

Bottom of 32-bit IO space

If PCI peripherals with big BARs are connected to the system
the bottom of the IO must be decreased to allocate such
devices.

Declare the beginning of the 128MB-aligned MMIO region. This
option is useful when PCI peripherals requesting large address
ranges are present.

VGA_BIOS_ID

northbridge/amd/pi/00630F01

string

The default VGA BIOS PCI vendor/device ID should be set to the
result of the map_oprom_vendev() function in northbridge.c.

VGA_BIOS_ID

northbridge/amd/pi/00730F01

string

The default VGA BIOS PCI vendor/device ID should be set to the
result of the map_oprom_vendev() function in northbridge.c.

VGA_BIOS_ID

northbridge/amd/pi/00660F01

string

The default VGA BIOS PCI vendor/device ID should be set to the
result of the map_oprom_vendev() function in northbridge.c.

REDIRECT_NBCIMX_TRACE_TO_SERIAL

northbridge/amd/cimx/rd890

bool

Redirect AMD Northbridge CIMX Trace to serial console

This Option allows you to redirect the AMD Northbridge CIMX
Trace debug information to the serial console.

Warning: Only enable this option when debuging or tracing AMD CIMX code.

NO_MMCONF_SUPPORT

northbridge/amd/amdk8

bool

If you want to remove this, you need to make sure any access to CPU
nodes 0:18.0, 0:19.0, ... continue to use PCI IO config access.

VGA_BIOS_ID

northbridge/amd/agesa/family16kb

string

The default VGA BIOS PCI vendor/device ID should be set to the
result of the map_oprom_vendev() function in northbridge.c.

SVI_HIGH_FREQ

northbridge/amd/amdfam10

bool

Select this for boards with a Voltage Regulator able to operate
at 3.4 MHz in SVI mode. Ignored unless the AMD CPU is rev C3.

Use of this option will only limit the autodetected HT width.
It will not (and cannot) increase the width beyond the autodetected
limits.

This is primarily used to work around poorly designed or laid out HT
traces on certain motherboards.

LIMIT_HT_DOWN_WIDTH_16

northbridge/amd/amdfam10

bool

HyperTransport uplink width

This option sets the maximum permissible HyperTransport
uplink width.

Use of this option will only limit the autodetected HT width.
It will not (and cannot) increase the width beyond the autodetected
limits.

This is primarily used to work around poorly designed or laid out HT
traces on certain motherboards.

(comment)

Southbridge

SERIRQ_CONTINUOUS_MODE

southbridge/intel/ibexpeak

bool

If you set this option to y, the serial IRQ machine will be
operated in continuous mode.

INTEL_LYNXPOINT_LP

southbridge/intel/lynxpoint

bool

Set this option to y for Lynxpont LP (Haswell ULT).

SERIRQ_CONTINUOUS_MODE

southbridge/intel/lynxpoint

bool

If you set this option to y, the serial IRQ machine will be
operated in continuous mode.

ME_MBP_CLEAR_LATE

southbridge/intel/lynxpoint

bool

Defer wait for ME MBP Cleared

If you set this option to y, the Management Engine driver
will defer waiting for the MBP Cleared indicator until the
finalize step. This can speed up boot time if the ME takes
a long time to indicate this status.

FINALIZE_USB_ROUTE_XHCI

southbridge/intel/lynxpoint

bool

Route all ports to XHCI controller in finalize step

If you set this option to y, the USB ports will be routed
to the XHCI controller during the finalize SMM callback.

SERIRQ_CONTINUOUS_MODE

southbridge/intel/bd82x6x

bool

If you set this option to y, the serial IRQ machine will be
operated in continuous mode.

LOCK_SPI_FLASH_RO

southbridge/intel/bd82x6x

bool

Write-protect all flash sections

Select this if you want to write-protect the whole firmware flash
chip. The locking will take place during the chipset lockdown, which
is either triggered by coreboot (when INTEL_CHIPSET_LOCKDOWN is set)
or has to be triggered later (e.g. by the payload or the OS).

NOTE: If you trigger the chipset lockdown unconditionally,
you won't be able to write to the flash chip using the
internal programmer any more.

LOCK_SPI_FLASH_NO_ACCESS

southbridge/intel/bd82x6x

bool

Write-protect all flash sections and read-protect non-BIOS sections

Select this if you want to protect the firmware flash against all
further accesses (with the exception of the memory mapped BIOS re-
gion which is always readable). The locking will take place during
the chipset lockdown, which is either triggered by coreboot (when
INTEL_CHIPSET_LOCKDOWN is set) or has to be triggered later (e.g.
by the payload or the OS).

NOTE: If you trigger the chipset lockdown unconditionally,
you won't be able to write to the flash chip using the
internal programmer any more.

SERIRQ_CONTINUOUS_MODE

southbridge/intel/fsp_bd82x6x

bool

If you set this option to y, the serial IRQ machine will be
operated in continuous mode.

INTEL_CHIPSET_LOCKDOWN

southbridge/intel/common

bool

Lock down chipset in coreboot

Some registers within host bridge on particular chipsets should be
locked down on each normal boot path (done by either coreboot or payload)
and S3 resume (always done by coreboot). Select this to let coreboot
to do this on normal boot path.

SERIRQ_CONTINUOUS_MODE

southbridge/intel/fsp_rangeley

bool

If you set this option to y, the serial IRQ machine will be
operated in continuous mode.

IFD_BIN_PATH

southbridge/intel/fsp_rangeley

string

The path and filename to the descriptor.bin file.

SERIRQ_CONTINUOUS_MODE

southbridge/intel/fsp_i89xx

bool

If you set this option to y, the serial IRQ machine will be
operated in continuous mode.

HUDSON_XHCI_ENABLE

southbridge/amd/pi/hudson

bool

Enable Hudson XHCI Controller

The XHCI controller must be enabled and the XHCI firmware
must be added in order to have USB 3.0 support configured
by coreboot. The OS will be responsible for enabling the XHCI
controller if the the XHCI firmware is available but the
XHCI controller is not enabled by coreboot.

HUDSON_XHCI_FWM

southbridge/amd/pi/hudson

bool

Add xhci firmware

Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0

HUDSON_IMC_FWM

southbridge/amd/pi/hudson

bool

Add IMC firmware

Add Hudson 2/3/4 IMC Firmware to support the onboard fan control

HUDSON_GEC_FWM

southbridge/amd/pi/hudson

bool

Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC.
Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.

HUDSON_SATA_MODE

southbridge/amd/pi/hudson

int

SATA Mode

Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
The default is NATIVE.
0: NATIVE mode does not require a ROM.
1: RAID mode must have the two ROM files.
2: AHCI may work with or without AHCI ROM. It depends on the payload support.
For example, seabios does not require the AHCI ROM.
3: LEGACY IDE
4: IDE to AHCI
5: AHCI7804: ROM Required, and AMD driver required in the OS.
6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.

(comment)

NATIVE

(comment)

RAID

(comment)

AHCI

(comment)

LEGACY IDE

(comment)

IDE to AHCI

(comment)

AHCI7804

(comment)

IDE to AHCI7804

RAID_ROM_ID

southbridge/amd/pi/hudson

string

RAID device PCI IDs

1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode

RAID_MISC_ROM_POSITION

southbridge/amd/pi/hudson

hex

RAID Misc ROM Position

The RAID ROM requires that the MISC ROM is located between the range
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
The CONFIG_ROM_SIZE must be larger than 0x100000.

HUDSON_LEGACY_FREE

southbridge/amd/pi/hudson

bool

System is legacy free

Select y if there is no keyboard controller in the system.
This sets variables in AGESA and ACPI.

AZ_PIN

southbridge/amd/pi/hudson

hex

bit 1,0 - pin 0
bit 3,2 - pin 1
bit 5,4 - pin 2
bit 7,6 - pin 3

AMDFW_OUTSIDE_CBFS

southbridge/amd/pi/hudson

hex

The AMDFW (PSP) is typically locatable in cbfs. Select this
option to manually attach the generated amdfw.rom at an
offset of 0x20000 from the bottom of the coreboot ROM image.

SERIRQ_CONTINUOUS_MODE

southbridge/amd/pi/hudson

bool

Set this option to y for serial IRQ in continuous mode.
Otherwise it is in quiet mode.

HUDSON_ACPI_IO_BASE

southbridge/amd/pi/hudson

hex

Base address for the ACPI registers.
This value must match the hardcoded value of AGESA.

HUDSON_UART

southbridge/amd/pi/hudson

bool

UART controller on Kern

There are two UART controllers in Kern.
The UART registers are memory-mapped. UART
controller 0 registers range from FEDC_6000h
to FEDC_6FFFh. UART controller 1 registers
range from FEDC_8000h to FEDC_8FFFh.

ENABLE_IDE_COMBINED_MODE

southbridge/amd/cimx/sb800

bool

Enable SATA IDE combined mode

If Combined Mode is enabled. IDE controller is exposed and
SATA controller has control over Port0 through Port3,
IDE controller has control over Port4 and Port5.

If Combined Mode is disabled, IDE controller is hidden and
SATA controller has full control of all 6 Ports when operating in non-IDE mode.

IDE_COMBINED_MODE

southbridge/amd/cimx/sb800

hex

SATA Mode

Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
The default is AHCI.

SB800_SATA_IDE

southbridge/amd/cimx/sb800

bool

NATIVE

NATIVE does not require a ROM.

SB800_SATA_AHCI

southbridge/amd/cimx/sb800

bool

AHCI

AHCI is the default and may work with or without AHCI ROM. It depends on the payload support.
For example, seabios does not require the AHCI ROM.

SB800_SATA_RAID

southbridge/amd/cimx/sb800

bool

RAID

sb800 RAID mode must have the two required ROM files.

RAID_ROM_ID

southbridge/amd/cimx/sb800

string

RAID device PCI IDs

1002,4392 for SATA NON-RAID5 module, 1002,4393 for SATA RAID5 mode

RAID_MISC_ROM_POSITION

southbridge/amd/cimx/sb800

hex

RAID Misc ROM Position

The RAID ROM requires that the MISC ROM is located between the range
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
The CONFIG_ROM_SIZE must larger than 0x100000.

SB800_IMC_FWM

southbridge/amd/cimx/sb800

bool

Add IMC firmware

Add SB800 / Hudson 1 IMC Firmware to support the onboard fan control.

SB800_FWM_AT_FFFA0000

southbridge/amd/cimx/sb800

bool

0xFFFA0000

The IMC and GEC ROMs requires a 'signature' located at one of several
fixed locations in memory. The location used shouldn't matter, just
select an area that doesn't conflict with anything else.

SB800_FWM_AT_FFF20000

southbridge/amd/cimx/sb800

bool

0xFFF20000

The IMC and GEC ROMs requires a 'signature' located at one of several
fixed locations in memory. The location used shouldn't matter, just
select an area that doesn't conflict with anything else.

SB800_FWM_AT_FFE20000

southbridge/amd/cimx/sb800

bool

0xFFE20000

The IMC and GEC ROMs requires a 'signature' located at one of several
fixed locations in memory. The location used shouldn't matter, just
select an area that doesn't conflict with anything else.

SB800_FWM_AT_FFC20000

southbridge/amd/cimx/sb800

bool

0xFFC20000

The IMC and GEC ROMs requires a 'signature' located at one of several
fixed locations in memory. The location used shouldn't matter, just
select an area that doesn't conflict with anything else.

SB800_FWM_AT_FF820000

southbridge/amd/cimx/sb800

bool

0xFF820000

The IMC and GEC ROMs requires a 'signature' located at one of several
fixed locations in memory. The location used shouldn't matter, just
select an area that doesn't conflict with anything else.

EHCI_BAR

southbridge/amd/cimx/sb800

hex

Fan Control

Select the method of SB800 fan control to be used. None would be
for either fixed maximum speed fans connected to the SB800 or for
an external chip controlling the fan speeds. Manual control sets
up the SB800 fan control registers. IMC fan control uses the SB800
IMC to actively control the fan speeds.

SB800_NO_FAN_CONTROL

southbridge/amd/cimx/sb800

bool

None

No SB800 Fan control - Do not set up the SB800 fan control registers.

SB800_MANUAL_FAN_CONTROL

southbridge/amd/cimx/sb800

bool

Manual

Configure the SB800 fan control registers in devicetree.cb.

SB800_IMC_FAN_CONTROL

southbridge/amd/cimx/sb800

bool

IMC Based

Set up the SB800 to use the IMC based Fan controller. This requires
the IMC ROM from AMD. Configure the registers in devicetree.cb.

The XHCI controller must be enabled and the XHCI firmware
must be added in order to have USB 3.0 support configured
by coreboot. The OS will be responsible for enabling the XHCI
controller if the the XHCI firmware is available but the
XHCI controller is not enabled by coreboot.

HUDSON_XHCI_FWM

southbridge/amd/agesa/hudson

bool

Add xhci firmware

Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0

HUDSON_IMC_FWM

southbridge/amd/agesa/hudson

bool

Add imc firmware

Add Hudson 2/3/4 IMC Firmware to support the onboard fan control

HUDSON_GEC_FWM

southbridge/amd/agesa/hudson

bool

Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC.
Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard.

HUDSON_SATA_MODE

southbridge/amd/agesa/hudson

int

SATA Mode

Select the mode in which SATA should be driven. NATIVE AHCI, or RAID.
The default is NATIVE.
0: NATIVE mode does not require a ROM.
1: RAID mode must have the two ROM files.
2: AHCI may work with or without AHCI ROM. It depends on the payload support.
For example, seabios does not require the AHCI ROM.
3: LEGACY IDE
4: IDE to AHCI
5: AHCI7804: ROM Required, and AMD driver required in the OS.
6: IDE to AHCI7804: ROM Required, and AMD driver required in the OS.

(comment)

NATIVE

(comment)

RAID

(comment)

AHCI

(comment)

LEGACY IDE

(comment)

IDE to AHCI

(comment)

AHCI7804

(comment)

IDE to AHCI7804

RAID_ROM_ID

southbridge/amd/agesa/hudson

string

RAID device PCI IDs

1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode

RAID_MISC_ROM_POSITION

southbridge/amd/agesa/hudson

hex

RAID Misc ROM Position

The RAID ROM requires that the MISC ROM is located between the range
0xFFF0_0000 to 0xFFF0_FFFF. Also, it must 1K bytes aligned.
The CONFIG_ROM_SIZE must be larger than 0x100000.

HUDSON_LEGACY_FREE

southbridge/amd/agesa/hudson

bool

System is legacy free

Select y if there is no keyboard controller in the system.
This sets variables in AGESA and ACPI.

AZ_PIN

southbridge/amd/agesa/hudson

hex

bit 1,0 - pin 0
bit 3,2 - pin 1
bit 5,4 - pin 2
bit 7,6 - pin 3

SOUTHBRIDGE_AMD_SB700_33MHZ_SPI

southbridge/amd/sb700

bool

Enable high speed SPI clock

When set, the SPI clock will run at 33MHz instead
of the compatibility mode 16.5MHz. Note that not
all ROMs are capable of 33MHz operation, so you
will need to verify this option is appropriate for
the ROM you are using.

NO_EARLY_SMBUS

southbridge/amd/cs5536

bool

Skip the CS5536 early SMBUS initialization.

EHCI_BAR

southbridge/amd/sb600

hex

SATA Mode

Select the mode in which SATA should be driven. IDE or AHCI.
The default is IDE.

config SATA_MODE_IDE
bool "IDE"

config SATA_MODE_AHCI
bool "AHCI"

(comment)

Super I/O

SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG

superio/ite/common

bool

Enable extended, 16-bit wide tacho counters.

SUPERIO_ITE_ENV_CTRL_8BIT_PWM

superio/ite/common

bool

PWM duty cycles are set in 8-bit registers (instead of 7 bit).

SUPERIO_ITE_ENV_CTRL_PWM_FREQ2

superio/ite/common

bool

The second FAN controller has a separate frequency setting.

(comment)

Embedded Controllers

EC_ACPI

ec/acpi

bool

ACPI Embedded Controller interface. Mostly found in laptops.

EC_GOOGLE_CHROMEEC

ec/google/chromeec

bool

Google's Chrome EC

EC_GOOGLE_CHROMEEC_ACPI_MEMMAP

ec/google/chromeec

bool

When defined, ACPI accesses EC memmap data on ports 66h/62h. When
not defined, the memmap data is instead accessed on 900h-9ffh via
the LPC bus.

EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER

ec/google/chromeec

bool

Expose methods for enabling and disabling port power on individual USB
ports through the EC.

EC_GOOGLE_CHROMEEC_BOARDID

ec/google/chromeec

bool

Provides common routine for reading boardid from Chrome EC.

EC_GOOGLE_CHROMEEC_I2C

ec/google/chromeec

bool

Google's Chrome EC via I2C bus.

EC_GOOGLE_CHROMEEC_I2C_PROTO3

ec/google/chromeec

bool

Use only proto3 for i2c EC communication.

EC_GOOGLE_CHROMEEC_LPC

ec/google/chromeec

bool

Google Chrome EC via LPC bus.

EC_GOOGLE_CHROMEEC_MEC

ec/google/chromeec

bool

Microchip EC variant for LPC register access.

EC_GOOGLE_CHROMEEC_PD

ec/google/chromeec

bool

Indicates that Google's Chrome USB PD chip is present.

EC_GOOGLE_CHROMEEC_SPI

ec/google/chromeec

bool

Google's Chrome EC via SPI bus.

EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US

ec/google/chromeec

int

Force delay after asserting /CS to allow EC to wakeup.

EC_GOOGLE_CHROMEEC_BOARDNAME

ec/google/chromeec

string

Chrome EC board name for EC

The board name used in the Chrome EC code base to build
the EC firmware. If set, the coreboot build with also
build the EC firmware and add it to the image.

EC_GOOGLE_CHROMEEC_PD_BOARDNAME

ec/google/chromeec

string

Chrome EC board name for PD

The board name used in the Chrome EC code base to build
the PD firmware. If set, the coreboot build with also
build the EC firmware and add it to the image.

EC_GOOGLE_CHROMEEC_RTC

ec/google/chromeec

bool

Enable Chrome OS EC RTC

Enable support for the real-time clock on the Chrome OS EC. This
uses the EC_CMD_RTC_GET_VALUE command to read the current time.

EC_GOOGLE_CHROMEEC_FIRMWARE_NONE

ec/google/chromeec

bool

No EC firmware is included

Disable building and including any EC firmware in the image.

config EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL
bool "External EC firmware is included"
help
Include EC firmware binary in the image from an external source.
It is expected to be built externally.

config EC_GOOGLE_CHROMEEC_FIRMWARE_BUILTIN
bool "Builtin EC firmware is included"
help
Build and include EC firmware binary in the image.

EC_GOOGLE_CHROMEEC_FIRMWARE_FILE

ec/google/chromeec

string

Chrome EC firmware path and filename

The path and filename of the EC firmware file to use.

EC_GOOGLE_CHROMEEC_PD_FIRMWARE_NONE

ec/google/chromeec

bool

No PD firmware is included

Disable building and including any PD firmware in the image.

config EC_GOOGLE_CHROMEEC_PD_FIRMWARE_EXTERNAL
bool "External PD firmware is included"
help
Include PD firmware binary in the image from an external source.
It is expected to be built externally.

config EC_GOOGLE_CHROMEEC_PD_FIRMWARE_BUILTIN
bool "Builtin PD firmware is included"
help
Build and include PD firmware binary in the image.

EC_GOOGLE_CHROMEEC_PD_FIRMWARE_FILE

ec/google/chromeec

string

Chrome EC firmware path and filename for PD

The path and filename of the PD firmware file to use.

EC_GOOGLE_CHROMEEC_SWITCHES

ec/google/chromeec

bool

Enable support for Chrome OS mode switches provided by the Chrome OS
EC.

Select this option to add the two firmware blobs for KBC1126.
You need these two blobs to power on your machine.

KBC1126_FW1

ec/hp/kbc1126

string

KBC1126 firmware #1 path and filename

The path and filename of the file to use as KBC1126 firmware #1.
You can use util/kbc1126/kbc1126_ec_dump to dump it from the
vendor firmware.

KBC1126_FW2

ec/hp/kbc1126

string

KBC1126 filename #2 path and filename

The path and filename of the file to use as KBC1126 firmware #2.
You can use util/kbc1126/kbc1126_ec_dump to dump it from the
vendor firmware.

H8_BEEP_ON_DEATH

ec/lenovo/h8

bool

Beep on fatal error

Beep when encountered a fatal error.

H8_FLASH_LEDS_ON_DEATH

ec/lenovo/h8

bool

Flash LEDs on fatal error

Flash all LEDs when encountered a fatal error.

H8_SUPPORT_BT_ON_WIFI

ec/lenovo/h8

bool

Support bluetooth on wifi cards

Disable BDC detection and assume bluetooth is installed. Required for
bluetooth on wifi cards, as it's not possible to detect it in coreboot.

EC_RODA_IT8518

ec/roda/it8518

bool

Interface to IT8518 embedded controller in Roda notebooks.

EC_SMSC_MEC1308

ec/smsc/mec1308

bool

Shared memory mailbox interface to SMSC MEC1308 Embedded Controller.

EC_PURISM_LIBREM

ec/purism/librem

bool

Purism Librem EC

EC_COMPAL_ENE932

ec/compal/ene932

bool

Interface to COMPAL ENE932 Embedded Controller.

EC_KONTRON_IT8516E

ec/kontron/it8516e

bool

Kontron uses an ITE IT8516E on the KTQM77. Its firmware might
come from Fintek (mentioned as Finte*c* somewhere in their Linux
driver).
The KTQM77 is an embedded board and the IT8516E seems to be
only used for fan control and GPIO.

(comment)

Intel FSP

HAVE_FSP_BIN

drivers/intel/fsp1_0

bool

Use Intel Firmware Support Package

Select this option to add an Intel FSP binary to
the resulting coreboot image.

Note: Without this binary, coreboot builds relying on the FSP
will not boot

FSP_FILE

drivers/intel/fsp1_0

string

Intel FSP binary path and filename

The path and filename of the Intel FSP binary for this platform.

FSP_LOC

drivers/intel/fsp1_0

hex

Intel FSP Binary location in CBFS

The location in CBFS that the FSP is located. This must match the
value that is set in the FSP binary. If the FSP needs to be moved,
rebase the FSP with Intel's BCT (tool).

ENABLE_FSP_FAST_BOOT

drivers/intel/fsp1_0

bool

Enable Fast Boot

Enabling this feature will force the MRC data to be cached in NV
storage to be used for speeding up boot time on future reboots
and/or power cycles.

ENABLE_MRC_CACHE

drivers/intel/fsp1_0

bool

Enabling this feature will cause MRC data to be cached in NV storage.
This can either be used for fast boot, or just because the FSP wants
it to be saved.

MRC_CACHE_FMAP

drivers/intel/fsp1_0

bool

Use MRC Cache in FMAP

Use the region "RW_MRC_CACHE" in FMAP instead of "mrc.cache" in CBFS.
You must define a region in your FMAP named "RW_MRC_CACHE".

MRC_CACHE_SIZE

drivers/intel/fsp1_0

hex

Fast Boot Data Cache Size

This is the amount of space in NV storage that is reserved for the
fast boot data cache storage.

WARNING: Because this area will be erased and re-written, the size
should be a full sector of the flash ROM chip and nothing else should
be included in CBFS in any sector that the fast boot cache data is in.

VIRTUAL_ROM_SIZE

drivers/intel/fsp1_0

hex

Virtual ROM Size

This is used to calculate the offset of the MRC data cache in NV
Storage for fast boot. If in doubt, leave this set to the default
which sets the virtual size equal to the ROM size.

Example: Cougar Canyon 2 has two 8 MB SPI ROMs. When the SPI ROMs are
loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB. When
the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM
size is 16 MB.

CACHE_ROM_SIZE_OVERRIDE

drivers/intel/fsp1_0

hex

Cache ROM Size

This is the size of the cachable area that is passed into the FSP in
the early initialization. Typically this should be the size of the CBFS
area, but the size must be a power of 2 whereas the CBFS size does not
have this limitation.

USE_GENERIC_FSP_CAR_INC

drivers/intel/fsp1_0

bool

The chipset can select this to use a generic cache_as_ram.inc file
that should be good for all FSP based platforms.

FSP_USES_UPD

drivers/intel/fsp1_0

bool

If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig.

HAVE_INTEL_FIRMWARE

southbridge/intel/common/firmware

bool

Chipset uses the Intel Firmware Descriptor to describe the
layout of the SPI ROM chip.

(comment)

Intel Firmware

HAVE_IFD_BIN

southbridge/intel/common/firmware

bool

Add Intel descriptor.bin file

The descriptor binary

EM100

southbridge/intel/common/firmware

bool

Configure IFD for EM100 usage

Set SPI frequency to 20MHz and disable Dual Output Fast Read Support

HAVE_ME_BIN

southbridge/intel/common/firmware

bool

Add Intel ME/TXE firmware

The Intel processor in the selected system requires a special firmware
for an integrated controller. This might be called the Management
Engine (ME), the Trusted Execution Engine (TXE) or something else
depending on the chip. This firmware might or might not be available
in coreboot's 3rdparty/blobs repository. If it is not and if you don't
have access to the firmware from elsewhere, you can still build
coreboot without it. In this case however, you'll have to make sure
that you don't overwrite your ME/TXE firmware on your flash ROM.

CHECK_ME

southbridge/intel/common/firmware

bool

Verify the integrity of the supplied ME/TXE firmware

Verify the integrity of the supplied Intel ME/TXE firmware before
proceeding with the build, in order to prevent an accidental loading
of a corrupted ME/TXE image.

USE_ME_CLEANER

southbridge/intel/common/firmware

bool

Strip down the Intel ME/TXE firmware

Use me_cleaner to remove all the non-fundamental code from the Intel
ME/TXE firmware.
The resulting Intel ME/TXE firmware will have only the code
responsible for the very basic hardware initialization, leaving the
ME/TXE subsystem essentially in a disabled state.

Don't flash a modified ME/TXE firmware and a new coreboot image at the
same time, test them in two different steps.

WARNING: this tool isn't based on any official Intel documentation but
only on reverse engineering and trial & error.

The integrated gigabit ethernet controller needs a firmware file.
Select this if you are going to use the PCH integrated controller
and have the firmware.

HAVE_EC_BIN

southbridge/intel/common/firmware

bool

Add EC firmware

The embedded controller needs a firmware file.

Select this if you are going to use the PCH integrated controller
and have the EC firmware. EC firmware will be added to final image
through ifdtool.

BUILD_WITH_FAKE_IFD

southbridge/intel/common/firmware

bool

Build with a fake IFD

If you don't have an Intel Firmware Descriptor (descriptor.bin) for your
board, you can select this option and coreboot will build without it.
The resulting coreboot.rom will not contain all parts required
to get coreboot running on your board. You can however write only the
BIOS section to your board's flash ROM and keep the other sections
untouched. Unfortunately the current version of flashrom doesn't
support this yet. But there is a patch pending [1].

WARNING: Never write a complete coreboot.rom to your flash ROM if it
was built with a fake IFD. It just won't work.

The BIOS region is typically the size of the CBFS area, and is located
at the end of the ROM space.

For an 8MB ROM with a 3MB CBFS area, this would look like:
0x00500000:0x007fffff

IFD_ME_SECTION

southbridge/intel/common/firmware

string

ME/TXE Region Starting:Ending addresses within the ROM

The ME/TXE region typically starts at around 0x1000 and often fills the
ROM space not used by CBFS.

For an 8MB ROM with a 3MB CBFS area, this might look like:
0x00001000:0x004fffff

IFD_GBE_SECTION

southbridge/intel/common/firmware

string

GBE Region Starting:Ending addresses within the ROM

The Gigabit Ethernet ROM region is used when an Intel NIC is built into
the Southbridge/SOC and the platform uses this device instead of an external
PCIe NIC. It will be located between the ME/TXE and the BIOS region.

Leave this empty if you're unsure.

IFD_PLATFORM_SECTION

southbridge/intel/common/firmware

string

Platform Region Starting:Ending addresses within the Rom

The Platform region is used for platform specific data.
It will be located between the ME/TXE and the BIOS region.

Leave this empty if you're unsure.

LOCK_MANAGEMENT_ENGINE

southbridge/intel/common/firmware

bool

Lock ME/TXE section

The Intel Firmware Descriptor supports preventing write accesses
from the host to the ME or TXE section in the firmware
descriptor. If the section is locked, it can only be overwritten
with an external SPI flash programmer. You will want this if you
want to increase security of your ROM image once you are sure
that the ME/TXE firmware is no longer going to change.

If unsure, say N.

CBFS_SIZE

southbridge/intel/common/firmware

hex

Reduce CBFS size to give room to the IFD blobs.

UDK_VERSION

vendorcode/intel

int

UEFI Development Kit version for Platform

Menu: AMD Platform Initialization

None

vendorcode/amd

None

AGESA source

Select the method for including the AMD Platform Initialization
code into coreboot. Platform Initialization code is required for
all AMD processors.

CPU_AMD_AGESA_BINARY_PI

vendorcode/amd

bool

binary PI

Use a binary PI package. Generally, these will be stored in the
"3rdparty/blobs" directory. For some processors, these must be obtained
directly from AMD Embedded Processors Group
(http://www.amdcom/embedded).

CPU_AMD_AGESA_OPENSOURCE

vendorcode/amd

bool

open-source AGESA

Build the PI package ("AGESA") from source code in the "vendorcode"
directory.

AGESA_BINARY_PI_VENDORCODE_PATH

vendorcode/amd/pi

string

AGESA PI directory path

Specify where to find the AGESA header files
for AMD platform initialization.

AGESA_BINARY_PI_FILE

vendorcode/amd/pi

string

AGESA PI binary file name

Specify the binary file to use for AMD platform initialization.

AGESA_BINARY_PI_AS_STAGE

vendorcode/amd/pi

bool

AGESA Binary PI is added as stage to CBFS.

AGESA will be added as a stage utilizing --xip cbfstool options
as needed relocating the image to the proper location in memory-mapped
cpu address space. It's required that the file be in ELF format
containing the relocations necessary for relocating at runtime.

AGESA_SPLIT_MEMORY_FILES

vendorcode/amd/pi

bool

Split AGESA Binary PI into pre- and post-memory files.

Specifies that AGESA is split into two binaries for pre- and
post-memory.

AGESA_PRE_MEMORY_BINARY_PI_FILE

vendorcode/amd/pi

string

Specify the binary file to use for pre-memory AMD platform
initialization.

AGESA_POST_MEMORY_BINARY_PI_FILE

vendorcode/amd/pi

string

Specify the binary file to use for post-memory AMD platform
initialization.

AGESA_BINARY_PI_LOCATION

vendorcode/amd/pi

hex

AGESA PI binary address in ROM

Specify the ROM address at which to store the binary Platform
Initialization code.

Menu: ChromeOS

CHROMEOS

vendorcode/google/chromeos

bool

Build for ChromeOS

Enable ChromeOS specific features like the GPIO sub table in
the coreboot table. NOTE: Enabling this option on an unsupported
board will most likely break your build.

NO_TPM_RESUME

vendorcode/google/chromeos

bool

On some boards the TPM stays powered up in S3. On those
boards, booting Windows will break if the TPM resume command
is sent during an S3 resume.

HAVE_REGULATORY_DOMAIN

vendorcode/google/chromeos

bool

Add regulatory domain methods

This option is needed to add ACPI regulatory domain methods

CHROMEOS_DISABLE_PLATFORM_HIERARCHY_ON_RESUME

vendorcode/google/chromeos

bool

Disable the platform heirarchy on resume path if the firmware
is involved in resume. The hierarchy is disabled prior to jumping
to the OS. Note that this option is sepcific to TPM2 boards.
This option is auto selected if CHROMEOS because it matches with
vboot_reference model which disables the platform hierarchy in
the boot loader. However, those operations need to be symmetric
on normal boot as well as resume and coreboot is only involved
in the resume piece w.r.t. the platform hierarchy.

GOOGLE_SMBIOS_MAINBOARD_VERSION

vendorcode/google

bool

Provide a common implementation for mainboard version,
which returns a formatted 'rev%d' board_id() string.

Specify ARMv8 extension, for example '1' for ARMv8.1, to control the
'-march' option passed into the compiler. Defaults to 0 for vanilla
ARMv8 but may be overridden in the SoC's Kconfig.

All ARMv8 implementations are downwards-compatible, so this does not
need to be changed unless specific features (e.g. new instructions)
are used by the SoC's coreboot code.

ARM64_SECURE_OS_FILE

arch/arm64

string

Secure OS binary file

Secure OS binary file.

ARM64_A53_ERRATUM_843419

arch/arm64

bool

Some early Cortex-A53 revisions had a hardware bug that results in
incorrect address calculations in rare cases. This option enables a
linker workaround to avoid those cases if your toolchain supports it.
Should be selected automatically by SoCs that are affected.

USE_MARCH_586

arch/x86

bool

Allow a platform or processor to select to be compiled using
the '-march=i586' option instead of the typical '-march=i686'

CBMEM_TOP_BACKUP

arch/x86

bool

Platform implements non-volatile storage to cache cbmem_top()
over stage transitions and optionally also over S3 suspend.

LATE_CBMEM_INIT

arch/x86

bool

Enable this in chipset's Kconfig if northbridge does not implement
early cbmem_top() call for romstage. CBMEM tables will be allocated
late in ramstage, after PCI devices resources are known.

WARNING: Late CBMEM initialization is deprecated. Platforms that
don't support early CBMEM initialization will be removed after
the release of coreboot 4.7.

PRERAM_CBMEM_CONSOLE_SIZE

arch/x86

hex

Increase this value if preram cbmem console is getting truncated

EARLY_EBDA_INIT

arch/x86

bool

Initialize BIOS EBDA area early in romstage to allow bootloader to
use this region for storing data which can be available across
various stages. If user is selecting this option then its users
responsibility to perform EBDA initialization call during romstage.

BOOTBLOCK_DEBUG_SPINLOOP

arch/x86

bool

Add a spin (JMP .) in bootblock_crt0.S during early bootblock to wait
for a JTAG debugger to break into the execution sequence.

BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP

arch/x86

bool

Select this value to provide a routine to save the BIST and timestamp
values. The default code places the BIST value in MM0 and the
timestamp value in MM2:MM1. Another file is necessary when the CPU
does not support the MMx register set.

VERSTAGE_DEBUG_SPINLOOP

arch/x86

bool

Add a spin (JMP .) in assembly_entry.S during early verstage to wait
for a JTAG debugger to break into the execution sequence.

ROMSTAGE_DEBUG_SPINLOOP

arch/x86

bool

Add a spin (JMP .) in assembly_entry.S during early romstage to wait
for a JTAG debugger to break into the execution sequence.

SKIP_MAX_REBOOT_CNT_CLEAR

arch/x86

bool

Do not clear reboot count after successful boot

Do not clear the reboot count immediately after successful boot.
Set to allow the payload to control normal/fallback image recovery.
Note that it is the responsibility of the payload to reset the
normal boot bit to 1 after each successsful boot.

ACPI_CPU_STRING

arch/x86

string

Sets the ACPI name string in the processor scope as written by
the acpigen function. Default is \_PR.CPxx. Note that you need
the \ escape character in the string.

COLLECT_TIMESTAMPS_NO_TSC

arch/x86

bool

Use a non-TSC platform-dependent source for timestamps.

COLLECT_TIMESTAMPS_TSC

arch/x86

bool

Use the TSC as the timestamp source.

PAGING_IN_CACHE_AS_RAM

arch/x86

bool

Chipsets scan select this option to preallocate area in cache-as-ram
for storing paging data structures. PAE paging is currently the
only thing being supported.

NUM_CAR_PAGE_TABLE_PAGES

arch/x86

int

The number of 4KiB pages that should be pre-allocated for page tables.

Menu: Devices

HAVE_VGA_TEXT_FRAMEBUFFER

device

bool

Selected by graphics drivers that support legacy VGA text mode.

HAVE_VBE_LINEAR_FRAMEBUFFER

device

bool

Selected by graphics drivers that can set up a VBE linear-framebuffer
mode.

HAVE_LINEAR_FRAMEBUFFER

device

bool

Selected by graphics drivers that can set up a generic linear
framebuffer.

HAVE_FSP_GOP

device

bool

Selected by drivers that support to run a blob that implements
the Graphics Output Protocol (GOP).

Selected by mainboards that implement support for `libgfxinit`.
Usually this requires a list of ports to be probed for displays.

MAINBOARD_DO_NATIVE_VGA_INIT

device

bool

Use native graphics init

Some mainboards, such as the Google Link, allow initializing the
display without the need of a binary only VGA OPROM. Enabling this
option may be faster, but also lacks flexibility in setting modes.

MAINBOARD_USE_LIBGFXINIT

device

bool

Use libgfxinit

Use the SPARK library `libgfxinit` for the native graphics
initialization. This requires an Ada toolchain.

VGA_ROM_RUN

device

bool

Run VGA Option ROMs

Execute VGA Option ROMs in coreboot if found. This can be used
to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS
payload.

When using a SeaBIOS payload it runs all option ROMs with much
more complete BIOS interrupt services available than coreboot,
which some option ROMs require in order to function correctly.

RUN_FSP_GOP

device

bool

Run a GOP driver

Some platforms (e.g. Intel Braswell and Skylake/Kaby Lake) support
to run a GOP blob. This option enables graphics initialization with
such a blob.

NO_GFX_INIT

device

bool

None

Select this to not perform any graphics initialization in
coreboot. This is useful if the payload (e.g. SeaBIOS) can
initialize graphics or if pre-boot graphics are not required.

S3_VGA_ROM_RUN

device

bool

Re-run VGA Option ROMs on S3 resume

Execute VGA Option ROMs in coreboot when resuming from S3 suspend.

When using a SeaBIOS payload it runs all option ROMs with much
more complete BIOS interrupt services available than coreboot,
which some option ROMs require in order to function correctly.

If unsure, say N when using SeaBIOS as payload, Y otherwise.

ALWAYS_LOAD_OPROM

device

bool

Always load option ROMs if any are found. The decision to run
the ROM is still determined at runtime, but the distinction
between loading and not running comes into play for CHROMEOS.

An example where this is required is that VBT (Video BIOS Tables)
are needed for the kernel's display driver to know how a piece of
hardware is configured to be used.

ALWAYS_RUN_OPROM

device

bool

Always uncondtionally run the option regardless of other
policies.

ON_DEVICE_ROM_LOAD

device

bool

Load Option ROMs on PCI devices

Load Option ROMs stored on PCI/PCIe/AGP VGA devices in coreboot.

If disabled, only Option ROMs stored in CBFS will be executed by
coreboot. If you are concerned about security, you might want to
disable this option, but it might leave your system in a state of
degraded functionality.

When using a SeaBIOS payload it runs all option ROMs with much
more complete BIOS interrupt services available than coreboot,
which some option ROMs require in order to function correctly.

If unsure, say N when using SeaBIOS as payload, Y otherwise.

PCI_OPTION_ROM_RUN_REALMODE

device

bool

Native mode

If you select this option, PCI Option ROMs will be executed
natively on the CPU in real mode. No CPU emulation is involved,
so this is the fastest, but also the least secure option.
(only works on x86/x64 systems)

PCI_OPTION_ROM_RUN_YABEL

device

bool

Secure mode

If you select this option, the x86emu CPU emulator will be used to
execute PCI Option ROMs.

This option prevents Option ROMs from doing dirty tricks with the
system (such as installing SMM modules or hypervisors), but it is
also significantly slower than the native Option ROM initialization
method.

This is the default choice for non-x86 systems.

YABEL_PCI_ACCESS_OTHER_DEVICES

device

bool

Allow Option ROMs to access other devices

Per default, YABEL only allows Option ROMs to access the PCI device
that they are associated with. However, this causes trouble for some
onboard graphics chips whose Option ROM needs to reconfigure the
north bridge.

YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG

device

bool

Fake success on writing other device's config space

By default, YABEL aborts when the Option ROM tries to write to other
devices' config spaces. With this option enabled, the write doesn't
follow through, but the Option ROM is allowed to go on.
This can create issues such as hanging Option ROMs (if it depends on
that other register changing to the written value), so test for
impact before using this option.

YABEL_VIRTMEM_LOCATION

device

hex

Location of YABEL's virtual memory

YABEL requires 1MB memory for its CPU emulation. This memory is
normally located at 16MB.

YABEL_DIRECTHW

device

bool

Direct hardware access

YABEL consists of two parts: It uses x86emu for the CPU emulation and
additionally provides a PC system emulation that filters bad device
and memory access (such as PCI config space access to other devices
than the initialized one).

When choosing this option, x86emu will pass through all hardware
accesses to memory and I/O devices to the underlying memory and I/O
addresses. While this option prevents Option ROMs from doing dirty
tricks with the CPU (such as installing SMM modules or hypervisors),
they can still access all devices in the system.
Enable this option for a good compromise between security and speed.

This option sets the resolution used for the coreboot framebuffer (and
bootsplash screen).

BOOTSPLASH

device

bool

Show graphical bootsplash

This option shows a graphical bootsplash screen. The graphics are
loaded from the CBFS file bootsplash.jpg.

You can either specify the location and file name of the
image in the 'General' section or add it manually to CBFS, using,
for example, cbfstool.

VGA_TEXT_FRAMEBUFFER

device

bool

Legacy VGA text mode

If this option is enabled, coreboot will initialize graphics in
legacy VGA text mode or, if a VGA BIOS is used and a VESA mode set,
switch to text mode before handing control to a payload.

VBE_LINEAR_FRAMEBUFFER

device

bool

VESA framebuffer

This option keeps the framebuffer mode set after coreboot finishes
execution. If this option is enabled, coreboot will pass a
framebuffer entry in its coreboot table and the payload will need a
compatible driver.

GENERIC_LINEAR_FRAMEBUFFER

device

bool

Linear \"high-resolution\" framebuffer

This option enables a high-resolution, linear framebuffer. If this
option is enabled, coreboot will pass a framebuffer entry in its
coreboot table and the payload will need a compatible driver.

PCIEXP_COMMON_CLOCK

device

bool

Enable PCIe Common Clock

Detect and enable Common Clock on PCIe links.

PCIEXP_ASPM

device

bool

Enable PCIe ASPM

Detect and enable ASPM (Active State Power Management) on PCIe links.

PCIEXP_CLK_PM

device

bool

Enable PCIe Clock Power Management

Detect and enable Clock Power Management on PCIe.

PCIEXP_L1_SUB_STATE

device

bool

Enable PCIe ASPM L1 SubState

Detect and enable ASPM on PCIe links.

EARLY_PCI_BRIDGE

device

bool

Early PCI bridge

While coreboot is executing code from ROM, the coreboot resource
allocator has not been running yet. Hence PCI devices living behind
a bridge are not yet visible to the system.

This option enables static configuration for a single pre-defined
PCI bridge function on bus 0.

SUBSYSTEM_VENDOR_ID

device

hex

Override PCI Subsystem Vendor ID

This config option will override the devicetree settings for
PCI Subsystem Vendor ID.

SUBSYSTEM_DEVICE_ID

device

hex

Override PCI Subsystem Device ID

This config option will override the devicetree settings for
PCI Subsystem Device ID.

VGA_BIOS

device

bool

Add a VGA BIOS image

Select this option if you have a VGA BIOS image that you would
like to add to your ROM.

You will be able to specify the location and file name of the
image later.

In the above example 1106 is the PCI vendor ID (in hex, but without
the "0x" prefix) and 3230 specifies the PCI device ID of the
video card (also in hex, without "0x" prefix).

Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.

INTEL_GMA_ADD_VBT_DATA_FILE

device

bool

Add a Video Bios Table (VBT) binary to CBFS

Add a VBT data file to CBFS. The VBT describes the integrated
GPU and connections, and is needed by the GOP driver integrated into
FSP and the OS driver in order to initialize the display.

INTEL_GMA_VBT_FILE

device

string

VBT binary path and filename

The path and filename of the VBT binary.

SOFTWARE_I2C

device

bool

Enable I2C controller emulation in software

This config option will enable code to override the i2c_transfer
routine with a (simple) software emulation of the protocol. This may
be useful for debugging or on platforms where a driver for the real
I2C controller is not (yet) available. The platform code needs to
provide bindings to manually toggle I2C lines.

Menu: Generic Drivers

ELOG

drivers/elog

bool

Support for flash based event log

Enable support for flash based event logging.

ELOG_CBMEM

drivers/elog

bool

Store a copy of ELOG in CBMEM

This option will have ELOG store a copy of the flash event log
in a CBMEM region and export that address in SMBIOS to the OS.
This is useful if the ELOG location is not in memory mapped flash,
but it means that events added at runtime via the SMI handler
will not be reflected in the CBMEM copy of the log.

ELOG_GSMI

drivers/elog

bool

SMI interface to write and clear event log

This interface is compatible with the linux kernel driver
available with CONFIG_GOOGLE_GSMI and can be used to write
kernel reset/shutdown messages to the event log.

ELOG_BOOT_COUNT

drivers/elog

bool

Maintain a monotonic boot number in CMOS

Store a monotonic boot number in CMOS and provide an interface
to read the current value and increment the counter. This boot
counter will be logged as part of the System Boot event.

ELOG_BOOT_COUNT_CMOS_OFFSET

drivers/elog

int

Offset in CMOS to store the boot count

This value must be greater than 16 bytes so as not to interfere
with the standard RTC region. Requires 8 bytes.

USBDEBUG

drivers/usb

bool

USB 2.0 EHCI debug dongle support

This option allows you to use a so-called USB EHCI Debug device
(such as the Ajays NET20DC, AMIDebug RX, or a system using the
Linux "EHCI Debug Device gadget" driver found in recent kernel)
to retrieve the coreboot debug messages (instead, or in addition
to, a serial port).

This feature is NOT supported on all chipsets in coreboot!

It also requires a USB2 controller which supports the EHCI
Debug Port capability.

Intel platforms have hardwired the debug port location and this
setting makes no difference there.

Hence, if you select the correct port here, you can speed up
your boot time. Which USB port number refers to which actual
port on your mainboard (potentially also USB pin headers on
your mainboard) is highly board-specific, and you'll likely
have to find out by trial-and-error.

USBDEBUG_DONGLE_STD

drivers/usb

bool

USB gadget driver or Net20DC

Net20DC, BeagleBone Black, Raspberry Pi Zero W

USBDEBUG_DONGLE_BEAGLEBONE

drivers/usb

bool

BeagleBone

Use this to configure the USB hub on BeagleBone board.
Do NOT select this for the BeagleBone Black.

USBDEBUG_DONGLE_FTDI_FT232H

drivers/usb

bool

FTDI FT232H UART

Use this with FT232H usb-to-uart. Configuration is hard-coded
to use 8n1, no flow control.

USBDEBUG_DONGLE_FTDI_FT232H_BAUD

drivers/usb

int

FTDI FT232H baud rate

Select baud rate for FT232H in the range 733..12,000,000. Make
sure that your receiving side supports the same setting and your
connection works with it. Multiples of 115,200 seem to be a good
choice, and EHCI debug usually can't saturate more than 576,000.

COMMON_CBFS_SPI_WRAPPER

drivers/spi

bool

Use common wrapper to interface CBFS to SPI bootrom.

SPI_FLASH

drivers/spi

bool

Select this option if your chipset driver needs to store certain
data in the SPI flash.

BOOT_DEVICE_SPI_FLASH_BUS

drivers/spi

int

Which SPI bus the boot device is connected to.

BOOT_DEVICE_SPI_FLASH_RW_NOMMAP

drivers/spi

bool

Provide common implementation of the RW boot device that
doesn't provide mmap() operations.

BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY

drivers/spi

bool

Include the common implementation in all stages, including the
early ones.

SPI_FLASH_SMM

drivers/spi

bool

SPI flash driver support in SMM

Select this option if you want SPI flash support in SMM.

SPI_FLASH_NO_FAST_READ

drivers/spi

bool

Disable Fast Read command

Select this option if your setup requires to avoid "fast read"s
from the SPI flash parts.

SPI_FLASH_ADESTO

drivers/spi

bool

Select this option if your chipset driver needs to store certain
data in the SPI flash and your SPI flash is made by Adesto Technologies.

SPI_FLASH_AMIC

drivers/spi

bool

Select this option if your chipset driver needs to store certain
data in the SPI flash and your SPI flash is made by AMIC.

SPI_FLASH_ATMEL

drivers/spi

bool

Select this option if your chipset driver needs to store certain
data in the SPI flash and your SPI flash is made by Atmel.

SPI_FLASH_EON

drivers/spi

bool

Select this option if your chipset driver needs to store certain
data in the SPI flash and your SPI flash is made by EON.

SPI_FLASH_GIGADEVICE

drivers/spi

bool

Select this option if your chipset driver needs to store certain
data in the SPI flash and your SPI flash is made by Gigadevice.

SPI_FLASH_MACRONIX

drivers/spi

bool

Select this option if your chipset driver needs to store certain
data in the SPI flash and your SPI flash is made by Macronix.

SPI_FLASH_SPANSION

drivers/spi

bool

Select this option if your chipset driver needs to store certain
data in the SPI flash and your SPI flash is made by Spansion.

SPI_FLASH_SST

drivers/spi

bool

Select this option if your chipset driver needs to store certain
data in the SPI flash and your SPI flash is made by SST.

SPI_FLASH_STMICRO

drivers/spi

bool

Select this option if your chipset driver needs to store certain
data in the SPI flash and your SPI flash is made by ST MICRO.

SPI_FLASH_WINBOND

drivers/spi

bool

Select this option if your chipset driver needs to store certain
data in the SPI flash and your SPI flash is made by Winbond.

SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B

drivers/spi

bool

Select this option if your SPI flash supports the fast read dual-
output command (opcode 0x3b) where the opcode and address are sent
to the chip on MOSI and data is received on both MOSI and MISO.

SPI_FLASH_HAS_VOLATILE_GROUP

drivers/spi

bool

Allows chipset to group write/erase operations under a single volatile
group.

CACHE_MRC_SETTINGS

drivers/mrc_cache

bool

Save cached MRC settings

MRC_WRITE_NV_LATE

drivers/mrc_cache

bool

MRC settings are normally written to NVRAM at BS_DEV_ENUMERATE-EXIT.
If a platform requires MRC settings written to NVRAM later than
normal, select this item. This will cause the write to occur at
BS_OS_RESUME_CHECK-ENTRY.

DIGITIZER_AUTODETECT

drivers/lenovo

bool

Autodetect

The presence of digitizer is inferred from model number stored in
AT24RF chip.

DIGITIZER_PRESENT

drivers/lenovo

bool

Present

The digitizer is assumed to be present.

DIGITIZER_ABSENT

drivers/lenovo

bool

Absent

The digitizer is assumed to be absent.

UART_OVERRIDE_INPUT_CLOCK_DIVIDER

drivers/uart

boolean

Set to "y" when the platform overrides the uart_input_clock_divider
routine.

UART_OVERRIDE_REFCLK

drivers/uart

boolean

Set to "y" when the platform overrides the uart_platform_refclk
routine.

DRIVERS_UART_OXPCIE

drivers/uart

bool

Oxford OXPCIe952

Support for Oxford OXPCIe952 serial port PCIe cards.
Currently only devices with the vendor ID 0x1415 and device ID
0xc158 or 0xc11b will work.

UART_USE_REFCLK_AS_INPUT_CLOCK

drivers/uart

bool

Use uart_platform_refclk to specify the input clock value.

UART_PCI_ADDR

drivers/uart

hex

UART's PCI bus, device, function address

Specify zero if the UART is connected to another bus type.
For PCI based UARTs, build the value as:

This forces a realtek 10ec:8168 card to reset to ensure power state
is correct at boot.

REALTEK_8168_MACADDRESS

drivers/net

string

Realtek rt8168 mac address

This is a string to set the mac address on a Realtek rt8168 card.
It must be in the form of "xx:xx:xx:xx:xx:xx", where x is a
hexadecimal number for it to be valid. Failing to do so will
result in the default macaddress being used.

RT8168_SET_LED_MODE

drivers/net

bool

This is to set a customized LED mode to distinguish 10/100/1000
link and speed status with limited LEDs avaiable on a board.
Please refer to RTL811x datasheet section 7.2 Customizable LED
Configuration for details. With this flag enabled, the
customized_leds variable will be read from devicetree setting.

DRIVERS_PS2_KEYBOARD

drivers/pc80/pc

bool

PS/2 keyboard init

Enable this option to initialize PS/2 keyboards found connected
to the PS/2 port.

Some payloads (eg, filo) require this option. Other payloads
(eg, GRUB 2, SeaBIOS, Linux) do not require it.
Initializing a PS/2 keyboard can take several hundred milliseconds.

If you know you will only use a payload which does not require
this option, then you can say N here to speed up boot time.
Otherwise say Y.

VGA

drivers/pc80/vga

bool

Include legacy VGA support code.

LPC_TPM

drivers/pc80/tpm

bool

Enable TPM support

Enable this option to enable LPC TPM support in coreboot.

If unsure, say N.

TPM_TIS_BASE_ADDRESS

drivers/pc80/tpm

hex

This can be used to adjust the TPM memory base address.
The default is specified by the TCG PC Client Specific TPM
Interface Specification 1.2 and should not be changed unless
the TPM being used does not conform to TPM TIS 1.2.

TPM_PIRQ

drivers/pc80/tpm

hex

This can be used to specify a PIRQ to use instead of SERIRQ,
which is needed for SPI TPM interrupt support on x86.

TPM_INIT_FAILURE_IS_FATAL

drivers/pc80/tpm

bool

What to do if TPM init failed. If true, force a hard reset,
otherwise just log error message to console.

SKIP_TPM_STARTUP_ON_NORMAL_BOOT

drivers/pc80/tpm

bool

Skip TPM init on normal boot. Useful if payload does TPM init.

TPM_DEACTIVATE

drivers/pc80/tpm

bool

Deactivate TPM

Deactivate TPM by issuing deactivate command.

TPM_RDRESP_NEED_DELAY

drivers/pc80/tpm

bool

Enable Delay Workaround for TPM

Certain TPMs seem to need some delay when reading response
to work around a race-condition-related issue, possibly
caused by ill-programmed TPM firmware.

PLATFORM_USES_FSP1_1

drivers/intel/fsp1_1

bool

Does the code require the Intel Firmware Support Package?

(comment)

Intel FSP 1.1

HAVE_FSP_BIN

drivers/intel/fsp1_1

bool

Should the Intel FSP binary be added to the flash image

Select this option to add an Intel FSP binary to
the resulting coreboot image.

Note: Without this binary, coreboot builds relying on the FSP
will not boot

CPU_MICROCODE_CBFS_LEN

drivers/intel/fsp1_1

hex

Microcode update region length in bytes

The length in bytes of the microcode update region.

CPU_MICROCODE_CBFS_LOC

drivers/intel/fsp1_1

hex

Microcode update base address in CBFS

The location (base address) in CBFS that contains the microcode update
binary.

FSP_FILE

drivers/intel/fsp1_1

string

Intel FSP binary path and filename

The path and filename of the Intel FSP binary for this platform.

FSP_LOC

drivers/intel/fsp1_1

hex

Intel FSP Binary location in CBFS

The location in CBFS that the FSP is located. This must match the
value that is set in the FSP binary. If the FSP needs to be moved,
rebase the FSP with Intel's BCT (tool).

If this FSP uses UPD/VPD data regions, select this in the chipset
Kconfig.

USE_GENERIC_FSP_CAR_INC

drivers/intel/fsp1_1

bool

The chipset can select this to use a generic cache_as_ram.inc file
that should be good for all FSP based platforms.

INTEL_DDI

drivers/intel/gma

bool

helper functions for intel DDI operations

INTEL_GMA_SSC_ALTERNATE_REF

drivers/intel/gma

bool

Set when the SSC reference clock for LVDS runs at a different fre-
quency than the general display reference clock.

To be set by northbridge or mainboard Kconfig. For most platforms,
there is no choice, i.e. for i945 and gm45 the SSC reference always
differs from the display reference clock (i945: 66Mhz SSC vs. 48MHz
DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Nehalem and newer, it's
the same frequency for SSC/non-SSC (120MHz). The only, currently
supported platform with a choice seems to be Pineview, where the
alternative is 100MHz vs. the default 96MHz.

INTEL_GMA_SWSMISCI

drivers/intel/gma

bool

Select this option for Atom-based platforms which use the SWSMISCI
register (0xe0) rather than the SWSCI register (0xe8).

GFX_GMA_ANALOG_I2C_PORT

drivers/intel/gma

string

Boards with a DVI-I connector share the I2C pins for both analog and
digital displays. In that case, the EDID for a VGA display has to be
read over the I2C interface of the coupled digital port.

DRIVERS_INTEL_MIPI_CAMERA

drivers/intel/mipi_camera

bool

MIPI CSI I2C camera SSDT generator. Generates SSDB and PWDB
structures which are used by the Intel kernel drivers.

(comment)

Intel FSP

HAVE_FSP_BIN

drivers/intel/fsp1_0

bool

Use Intel Firmware Support Package

Select this option to add an Intel FSP binary to
the resulting coreboot image.

Note: Without this binary, coreboot builds relying on the FSP
will not boot

FSP_FILE

drivers/intel/fsp1_0

string

Intel FSP binary path and filename

The path and filename of the Intel FSP binary for this platform.

FSP_LOC

drivers/intel/fsp1_0

hex

Intel FSP Binary location in CBFS

The location in CBFS that the FSP is located. This must match the
value that is set in the FSP binary. If the FSP needs to be moved,
rebase the FSP with Intel's BCT (tool).

ENABLE_FSP_FAST_BOOT

drivers/intel/fsp1_0

bool

Enable Fast Boot

Enabling this feature will force the MRC data to be cached in NV
storage to be used for speeding up boot time on future reboots
and/or power cycles.

ENABLE_MRC_CACHE

drivers/intel/fsp1_0

bool

Enabling this feature will cause MRC data to be cached in NV storage.
This can either be used for fast boot, or just because the FSP wants
it to be saved.

MRC_CACHE_FMAP

drivers/intel/fsp1_0

bool

Use MRC Cache in FMAP

Use the region "RW_MRC_CACHE" in FMAP instead of "mrc.cache" in CBFS.
You must define a region in your FMAP named "RW_MRC_CACHE".

MRC_CACHE_SIZE

drivers/intel/fsp1_0

hex

Fast Boot Data Cache Size

This is the amount of space in NV storage that is reserved for the
fast boot data cache storage.

WARNING: Because this area will be erased and re-written, the size
should be a full sector of the flash ROM chip and nothing else should
be included in CBFS in any sector that the fast boot cache data is in.

VIRTUAL_ROM_SIZE

drivers/intel/fsp1_0

hex

Virtual ROM Size

This is used to calculate the offset of the MRC data cache in NV
Storage for fast boot. If in doubt, leave this set to the default
which sets the virtual size equal to the ROM size.

Example: Cougar Canyon 2 has two 8 MB SPI ROMs. When the SPI ROMs are
loaded with a 4 MB coreboot image, the virtual ROM size is 8 MB. When
the SPI ROMs are loaded with an 8 MB coreboot image, the virtual ROM
size is 16 MB.

CACHE_ROM_SIZE_OVERRIDE

drivers/intel/fsp1_0

hex

Cache ROM Size

This is the size of the cachable area that is passed into the FSP in
the early initialization. Typically this should be the size of the CBFS
area, but the size must be a power of 2 whereas the CBFS size does not
have this limitation.

USE_GENERIC_FSP_CAR_INC

drivers/intel/fsp1_0

bool

The chipset can select this to use a generic cache_as_ram.inc file
that should be good for all FSP based platforms.

FSP_USES_UPD

drivers/intel/fsp1_0

bool

If this FSP uses UPD/VPD data regions, select this in the chipset Kconfig.

DRIVERS_INTEL_WIFI

drivers/intel/wifi

bool

Support Intel PCI-e WiFi adapters

When enabled, add identifiers in ACPI and SMBIOS tables to
make OS drivers work with certain Intel PCI-e WiFi chipsets.

Verify that the HOBs required by coreboot are returned by FSP and
that the resource HOBs are in the correct order and position.

DISPLAY_FSP_VERSION_INFO

drivers/intel/fsp2_0

bool

Display Firmware Ingredient Version Information

Select this option to display Firmware version information.

FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS

drivers/intel/fsp2_0

bool

This is selected by SoC or mainboard to supply their own
concept of a version for the memory settings respectively.
This allows deployed systems to bump their version number
with the same FSP which will trigger a retrain of the memory.

VGA driver for qemu emulated vga cards supporting
the bochs dispi interface. This includes
standard vga, vmware svga and qxl. The default
vga (cirrus) is *not* supported, so you have to
pick another one explicitly via 'qemu -vga $card'.

DRIVER_XPOWERS_AXP209

drivers/xpowers/axp209

bool

X-Powers AXP902 Power Management Unit

DRIVER_XPOWERS_AXP209_BOOTBLOCK

drivers/xpowers/axp209

bool

Make AXP209 functionality available in he bootblock.

DRIVER_PARADE_PS8640

drivers/parade/ps8640

bool

Parade PS8640 MIPI DSI to eDP Converter

DRIVER_PARADE_PS8625

drivers/parade/ps8625

bool

Parade ps8625 display port to lvds bridge

DRIVER_MAXIM_MAX77686

drivers/maxim/max77686

bool

Maxim MAX77686 power regulator

DRIVERS_I2C_PCA9538

drivers/i2c/pca9538

bool

Enable support for I2C I/O expander PCA9538.

DRIVERS_I2C_RX6110SA

drivers/i2c/rx6110sa

bool

Enable support for external RTC chip RX6110 SA.

DRIVERS_I2C_DESIGNWARE

drivers/i2c/designware

bool

Designware I2C support

DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ

drivers/i2c/designware

int

The i2c ip block's clock.

DRIVERS_I2C_RTD2132

drivers/i2c/rtd2132

bool

Enable support for Realtek RTD2132 DisplayPort to LVDS bridge chip.

STORAGE_ERASE

commonlib/storage

bool

Support SD/MMC erase operations

Select to enable SD/MMC erase oprations

STORAGE_WRITE

commonlib/storage

bool

Support SD/MMC write operations

Select to enable SD/MMC write oprations

SD_MMC_DEBUG

commonlib/storage

bool

Debug SD/MMC card/devices operations

Display overview of SD/MMC card/device operations

SD_MMC_TRACE

commonlib/storage

bool

Trace SD/MMC card/device operations

Display details of SD/MMC card/device operations

SDHC_DEBUG

commonlib/storage

bool

Debug SD/MMC controller settings

Display clock speed and bus width settings

SDHC_TRACE

commonlib/storage

bool

Trace SD/MMC controller operations

Display the operations performed by the SD/MMC controller

SDHCI_ADMA_IN_BOOTBLOCK

commonlib/storage

bool

Determine if bootblock is able to use ADMA2 or ADMA64

SDHCI_ADMA_IN_ROMSTAGE

commonlib/storage

bool

Determine if romstage is able to use ADMA2 or ADMA64

SDHCI_ADMA_IN_VERSTAGE

commonlib/storage

bool

Determine if verstage is able to use ADMA2 or ADMA64

Menu: Security

Menu: Verified Boot (vboot)

VBOOT

security/vboot

bool

Verify firmware with vboot.

Enabling VBOOT will use vboot to verify the components of the firmware
(stages, payload, etc).

VBOOT_VBNV_CMOS

security/vboot

bool

VBNV is stored in CMOS

VBOOT_VBNV_OFFSET

security/vboot

hex

CMOS offset for VbNv data. This value must match cmos.layout
in the mainboard directory, minus 14 bytes for the RTC.

VBOOT_VBNV_CMOS_BACKUP_TO_FLASH

security/vboot

bool

Vboot non-volatile storage data will be backed up from CMOS to flash
and restored from flash if the CMOS is invalid due to power loss.

VBOOT_VBNV_EC

security/vboot

bool

VBNV is stored in EC

VBOOT_VBNV_FLASH

security/vboot

bool

VBNV is stored in flash storage

VBOOT_STARTS_IN_BOOTBLOCK

security/vboot

bool

Firmware verification happens during the end of or right after the
bootblock. This implies that a static VBOOT2_WORK() buffer must be
allocated in memlayout.

VBOOT_STARTS_IN_ROMSTAGE

security/vboot

bool

Firmware verification happens during the end of romstage (after
memory initialization). This implies that vboot working data is
allocated in CBMEM.

VBOOT_MOCK_SECDATA

security/vboot

bool

Mock secdata for firmware verification

Enabling VBOOT_MOCK_SECDATA will mock secdata for the firmware
verification to avoid access to a secdata storage (typically TPM).
All operations for a secdata storage will be successful. This option
can be used during development when a TPM is not present or broken.
THIS SHOULD NOT BE LEFT ON FOR PRODUCTION DEVICES.

VBOOT_DISABLE_DEV_ON_RECOVERY

security/vboot

bool

When this option is enabled, the Chrome OS device leaves the
developer mode as soon as recovery request is detected. This is
handy on embedded devices with limited input capabilities.

VBOOT_SEPARATE_VERSTAGE

security/vboot

bool

If this option is set, vboot verification runs in a standalone stage
that is loaded from the bootblock and exits into romstage. If it is
not set, the verification code is linked directly into the bootblock
or the romstage and runs as part of that stage (cf. related options
VBOOT_STARTS_IN_BOOTBLOCK/_ROMSTAGE and VBOOT_RETURN_FROM_VERSTAGE).

VBOOT_RETURN_FROM_VERSTAGE

security/vboot

bool

If this is set, the verstage returns back to the calling stage instead
of exiting to the succeeding stage so that the verstage space can be
reused by the succeeding stage. This is useful if a RAM space is too
small to fit both the verstage and the succeeding stage.

VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT

security/vboot

bool

This option ensures that the recovery request is not lost because of
reboots caused after vboot verification is run. e.g. reboots caused by
FSP components on Intel platforms.

VBOOT_OPROM_MATTERS

security/vboot

bool

Set this option to indicate to vboot that this platform will skip its
display initialization on a normal (non-recovery, non-developer) boot.
Vboot calls this "oprom matters" because on x86 devices this
traditionally meant that the video option ROM will not be loaded, but
it works functionally the same for other platforms that can skip their
native display initialization code instead.

VBOOT_HAS_REC_HASH_SPACE

security/vboot

bool

Set this option to indicate to vboot that recovery data hash space
is present in TPM.

VBOOT_EC_SOFTWARE_SYNC

security/vboot

bool

Enable EC software sync

EC software sync is a mechanism where the AP helps the EC verify its
firmware similar to how vboot verifies the main system firmware. This
option selects whether vboot should support EC software sync.

VBOOT_EC_SLOW_UPDATE

security/vboot

bool

Whether the EC (or PD) is slow to update and needs to display a
screen that informs the user the update is happening.

VBOOT_EC_EFS

security/vboot

bool

CrosEC can support EFS: Early Firmware Selection. If it's enabled,
software sync need to also support it. This setting tells vboot to
perform EFS software sync.

VBOOT_PHYSICAL_DEV_SWITCH

security/vboot

bool

Whether this platform has a physical developer switch. Note that this
disables virtual dev switch functionality (through secdata). Operation
where both a physical pin and the virtual switch get sampled is not
supported by coreboot.

VBOOT_PHYSICAL_REC_SWITCH

security/vboot

bool

Whether this platform has a physical recovery switch.

VBOOT_LID_SWITCH

security/vboot

bool

Whether this platform has a lid switch. If it does, vboot will not
decrement try counters for boot failures if the lid is closed.

VBOOT_WIPEOUT_SUPPORTED

security/vboot

bool

When this option is enabled, the firmware provides the ability to
signal the application the need for factory reset (a.k.a. wipe
out) of the device

VBOOT_FWID_MODEL

security/vboot

string

Firmware ID model

This is the first part of the FWID written to various regions of a
vboot firmware image to identify its version.

VBOOT_FWID_VERSION

security/vboot

string

Firmware ID version

This is the second part of the FWID written to various regions of a
vboot firmware image to identify its version.

VBOOT_NO_BOARD_SUPPORT

security/vboot

bool

Allow the use of vboot without board support

Enable weak functions for get_write_protect_state and
get_recovery_mode_switch in order to proceed with refactoring
of the vboot2 code base. Later on this code is removed and replaced
by interfaces.

RO_REGION_ONLY

security/vboot

string

Additional files that should not be copied to RW

Add a space delimited list of filenames that should only be in the
RO section.

Menu: GBB configuration

Menu: Vboot Keys

Menu: Trusted Platform Module

TPM

security/tpm

bool

Enable this option to enable TPM support in coreboot.

If unsure, say N.

TPM2

security/tpm

bool

Enable this option to enable TPM2 support in coreboot.

If unsure, say N.

DEBUG_TPM

security/tpm

bool

Output verbose TPM debug messages

This option enables additional TPM related debug messages.

POWER_OFF_ON_CR50_UPDATE

security/tpm

bool

Power off machine while waiting for CR50 update to take effect.

MAINBOARD_HAS_LPC_TPM

security/tpm

bool

Board has TPM support

MAINBOARD_HAS_TPM2

security/tpm

bool

There is a TPM device installed on the mainboard, and it is
compliant with version 2 TCG TPM specification. Could be connected
over LPC, SPI or I2C.

Set to "y" when the platform overrides the baudrate by providing
a get_uart_baudrate routine.

CONSOLE_SERIAL_921600

console

bool

921600

Set serial port Baud rate to 921600.

CONSOLE_SERIAL_460800

console

bool

460800

Set serial port Baud rate to 460800.

CONSOLE_SERIAL_230400

console

bool

230400

Set serial port Baud rate to 230400.

CONSOLE_SERIAL_115200

console

bool

115200

Set serial port Baud rate to 115200.

CONSOLE_SERIAL_57600

console

bool

57600

Set serial port Baud rate to 57600.

CONSOLE_SERIAL_38400

console

bool

38400

Set serial port Baud rate to 38400.

CONSOLE_SERIAL_19200

console

bool

19200

Set serial port Baud rate to 19200.

CONSOLE_SERIAL_9600

console

bool

9600

Set serial port Baud rate to 9600.

TTYS0_BAUD

console

int

Map the Baud rates to an integer.

SPKMODEM

console

bool

spkmodem (console on speaker) console output

Send coreboot debug output through speaker

CONSOLE_USB

console

bool

USB dongle console output

Send coreboot debug output to USB.

Configuration for USB hardware is under menu Generic Drivers.

ONBOARD_VGA_IS_PRIMARY

console

bool

Use onboard VGA as primary video device

If not selected, the last adapter found will be used.

CONSOLE_NE2K

console

bool

Network console over NE2000 compatible Ethernet adapter

Send coreboot debug output to a Ethernet console, it works
same way as Linux netconsole, packets are received to UDP
port 6666 on IP/MAC specified with options bellow.
Use following netcat command: nc -u -l -p 6666

CONSOLE_NE2K_DST_MAC

console

string

Destination MAC address of remote system

Type in either MAC address of logging system or MAC address
of the router.

CONSOLE_NE2K_DST_IP

console

string

Destination IP of logging system

This is IP address of the system running for example
netcat command to dump the packets.

CONSOLE_NE2K_SRC_IP

console

string

IP address of coreboot system

This is the IP of the coreboot system

CONSOLE_NE2K_IO_PORT

console

hex

NE2000 adapter fixed IO port address

This is the IO port address for the IO port
on the card, please select some non-conflicting region,
32 bytes of IO spaces will be used (and align on 32 bytes
boundary, qemu needs broader align)

CONSOLE_CBMEM

console

bool

Send console output to a CBMEM buffer

Enable this to save the console output in a CBMEM buffer. This would
allow to see coreboot console output from Linux space.

CONSOLE_CBMEM_BUFFER_SIZE

console

hex

Room allocated for console output in CBMEM

Space allocated for console output storage in CBMEM. The default
value (128K or 0x20000 bytes) is large enough to accommodate
even the BIOS_SPEW level.

CONSOLE_CBMEM_DUMP_TO_UART

console

bool

Dump CBMEM console on resets

Enable this to have CBMEM console buffer contents dumped on the
serial output in case serial console is disabled and the device
resets itself while trying to boot the payload.

CONSOLE_SPI_FLASH

console

bool

SPI Flash console output

Send coreboot debug output to the SPI Flash in the FMAP CONSOLE area

This option can cause premature wear on the SPI flash and should not
be used as a normal means of debugging. It is only to be enabled and
used when porting a new motherboard which has no other console
available (no UART, no POST, no cbmem access(non bootable)). Since
a non bootable machine will require the use of an external SPI Flash
programmer, the developer can grab the console log at the same time.

The flash console will not be erased on reboot, so once it is full,
the flashconsole driver will stop writing to it. This is to avoid
wear on the flash, and to avoid erasing sectors (which may freeze
the SPI controller on skylake).

The 'CONSOLE' area can be extracted from the FMAP with :
cbfstool rom.bin read -r CONSOLE -f console.log

CONSOLE_SPI_FLASH_BUFFER_SIZE

console

hex

Room allocated for console output in FMAP

Space allocated for console output storage in FMAP. The default
value (128K or 0x20000 bytes) is large enough to accommodate
even the BIOS_SPEW level.

Enable support for the debug console on the Dediprog EM100Pro.
This is currently working only in ramstage due to how the spi
drivers are written.

CONSOLE_OVERRIDE_LOGLEVEL

console

boolean

Set to "y" when the platform overrides the loglevel by providing
a get_console_loglevel routine.

DEFAULT_CONSOLE_LOGLEVEL_8

console

bool

8: SPEW

Way too many details.

DEFAULT_CONSOLE_LOGLEVEL_7

console

bool

7: DEBUG

Debug-level messages.

DEFAULT_CONSOLE_LOGLEVEL_6

console

bool

6: INFO

Informational messages.

DEFAULT_CONSOLE_LOGLEVEL_5

console

bool

5: NOTICE

Normal but significant conditions.

DEFAULT_CONSOLE_LOGLEVEL_4

console

bool

4: WARNING

Warning conditions.

DEFAULT_CONSOLE_LOGLEVEL_3

console

bool

3: ERR

Error conditions.

DEFAULT_CONSOLE_LOGLEVEL_2

console

bool

2: CRIT

Critical conditions.

DEFAULT_CONSOLE_LOGLEVEL_1

console

bool

1: ALERT

Action must be taken immediately.

DEFAULT_CONSOLE_LOGLEVEL_0

console

bool

0: EMERG

System is unusable.

DEFAULT_CONSOLE_LOGLEVEL

console

int

Map the log level config names to an integer.

CMOS_POST

console

bool

Store post codes in CMOS for debugging

If enabled, coreboot will store post codes in CMOS and switch between
two offsets on each boot so the last post code in the previous boot
can be retrieved. This uses 3 bytes of CMOS.

CMOS_POST_OFFSET

console

hex

Offset into CMOS to store POST codes

If CMOS_POST is enabled then an offset into CMOS must be provided.
If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value
defined in the mainboard option table.

CMOS_POST_EXTRA

console

bool

Store extra logging info into CMOS

This will enable extra logging of work that happens between post
codes into CMOS for debug. This uses an additional 8 bytes of CMOS.

CONSOLE_POST

console

bool

Show POST codes on the debug console

If enabled, coreboot will additionally print POST codes (which are
usually displayed using a so-called "POST card" ISA/PCI/PCI-E
device) on the debug console.

POST_IO

console

bool

Send POST codes to an IO port

If enabled, POST codes will be written to an IO port.

POST_IO_PORT

console

hex

IO port for POST codes

POST codes on x86 are typically written to the LPC bus on port
0x80. However, it may be desirable to change the port number
depending on the presence of coprocessors/microcontrollers or if the
platform does not support IO in the conventional x86 manner.

NO_EARLY_BOOTBLOCK_POSTCODES

console

hex

Some chipsets require that the routing for the port 80h POST
code be configured before any POST codes are sent out.
This can be done in the boot block, but there are a couple of
POST codes that go out before the chipset's bootblock initialization
can happen. This option suppresses those POST codes.

ACPI_HUGE_LOWMEM_BACKUP

toplevel

bool

On S3 resume path, backup low memory from RAMBASE..RAMTOP in CBMEM.

RESUME_PATH_SAME_AS_BOOT

toplevel

bool

This option indicates that when a system resumes it takes the
same path as a regular boot. e.g. an x86 system runs from the
reset vector at 0xfffffff0 on both resume and warm/cold boot.

HAVE_HARD_RESET

toplevel

bool

This variable specifies whether a given board has a hard_reset
function, no matter if it's provided by board code or chipset code.

HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK

toplevel

bool

This should be enabled on certain plaforms, such as the AMD
SR565x, that cannot handle concurrent CBFS accesses from
multiple APs during early startup.

Cooperative multitasking allows callbacks to be multiplexed on the
main thread of ramstage. With this enabled it allows for multiple
execution paths to take place when they have udelay() calls within
their code.

NUM_THREADS

toplevel

int

How many execution threads to cooperatively multitask with.

HAVE_OPTION_TABLE

toplevel

bool

This variable specifies whether a given board has a cmos.layout
file containing NVRAM/CMOS bit definitions.
It defaults to 'n' but can be selected in mainboard/*/Kconfig.

GFXUMA

toplevel

bool

Enable Unified Memory Architecture for graphics.

HAVE_ACPI_TABLES

toplevel

bool

This variable specifies whether a given board has ACPI table support.
It is usually set in mainboard/*/Kconfig.

HAVE_MP_TABLE

toplevel

bool

This variable specifies whether a given board has MP table support.
It is usually set in mainboard/*/Kconfig.
Whether or not the MP table is actually generated by coreboot
is configurable by the user via GENERATE_MP_TABLE.

HAVE_PIRQ_TABLE

toplevel

bool

This variable specifies whether a given board has PIRQ table support.
It is usually set in mainboard/*/Kconfig.
Whether or not the PIRQ table is actually generated by coreboot
is configurable by the user via GENERATE_PIRQ_TABLE.

MAX_PIRQ_LINKS

toplevel

int

This variable specifies the number of PIRQ interrupt links which are
routable. On most chipsets, this is 4, INTA through INTD. Some
chipsets offer more than four links, commonly up to INTH. They may
also have a separate link for ATA or IOAPIC interrupts. When the PIRQ
table specifies links greater than 4, pirq_route_irqs will not
function properly, unless this variable is correctly set.

ACPI_NHLT

toplevel

bool

Build support for NHLT (non HD Audio) ACPI table generation.

Menu: System tables

GENERATE_MP_TABLE

toplevel

bool

Generate an MP table

Generate an MP table (conforming to the Intel MultiProcessor
specification 1.4) for this board.

If unsure, say Y.

GENERATE_PIRQ_TABLE

toplevel

bool

Generate a PIRQ table

Generate a PIRQ table for this board.

If unsure, say Y.

GENERATE_SMBIOS_TABLES

toplevel

bool

Generate SMBIOS tables

Generate SMBIOS tables for this board.

If unsure, say Y.

MAINBOARD_SERIAL_NUMBER

toplevel

string

SMBIOS Serial Number

The Serial Number to store in SMBIOS structures.

MAINBOARD_VERSION

toplevel

string

SMBIOS Version Number

The Version Number to store in SMBIOS structures.

MAINBOARD_SMBIOS_MANUFACTURER

toplevel

string

SMBIOS Manufacturer

Override the default Manufacturer stored in SMBIOS structures.

MAINBOARD_SMBIOS_PRODUCT_NAME

toplevel

string

SMBIOS Product name

Override the default Product name stored in SMBIOS structures.

SMBIOS_ENCLOSURE_TYPE

toplevel

hex

System Enclosure or Chassis Types as defined in SMBIOS specification.
The default value is SMBIOS_ENCLOSURE_DESKTOP (0x03) or
SMBIOS_ENCLOSURE_LAPTOP (0x09) if SYSTEM_TYPE_LAPTOP is set.

Menu: Payload

PAYLOAD_NONE

payloads

bool

None

Select this option if you want to create an "empty" coreboot
ROM image for a certain mainboard, i.e. a coreboot ROM image
which does not yet contain a payload.

For such an image to be useful, you have to use 'cbfstool'
to add a payload to the ROM image later.

PAYLOAD_ELF

payloads

bool

An ELF executable payload

Select this option if you have a payload image (an ELF file)
which coreboot should run as soon as the basic hardware
initialization is completed.

You will be able to specify the location and file name of the
payload image later.

PAYLOAD_BAYOU

payloads

bool

Bayou

Select this option if you want to set bayou as your primary
payload.

PAYLOAD_UBOOT

payloads/external/U-Boot.name

bool

U-Boot (Experimental)

Select this option if you want to build a coreboot image
with a U-Boot payload.

This option allows a platform to set Kconfig options for a basic
U-Boot payload. In general, if the option is used, the default
would be "$(top)/src/mainboard/$(MAINBOARDDIR)/config_uboot"
for a config stored in the coreboot mainboard directory, or
"$(project_dir)/configs/coreboot-x86_defconfig" to use a config
from the U-Boot config directory

SEABIOS_STABLE

payloads/external/SeaBIOS

bool

1.11.1

Stable SeaBIOS version

SEABIOS_MASTER

payloads/external/SeaBIOS

bool

master

Newest SeaBIOS version

SEABIOS_REVISION

payloads/external/SeaBIOS

bool

git revision

Select this option if you have a specific commit or branch
that you want to use as the revision from which to
build SeaBIOS.

You will be able to specify the name of a branch or a commit id
later.

SEABIOS_REVISION_ID

payloads/external/SeaBIOS

string

Insert a commit's SHA-1 or a branch name

The commit's SHA-1 or branch name of the revision to use.

SEABIOS_PS2_TIMEOUT

payloads/external/SeaBIOS

int

PS/2 keyboard controller initialization timeout (milliseconds)

Some PS/2 keyboard controllers don't respond to commands immediately
after powering on. This specifies how long SeaBIOS will wait for the
keyboard controller to become ready before giving up.

SEABIOS_THREAD_OPTIONROMS

payloads/external/SeaBIOS

bool

Hardware init during option ROM execution

Allow hardware init to run in parallel with optionrom execution.

This can reduce boot time, but can cause some timing
variations during option ROM code execution. It is not
known if all option ROMs will behave properly with this option.

After initializing the GPU, the information about it can be passed to the payload.
Provide an option rom that implements this legacy VGA BIOS compatibility requirement.

PAYLOAD_CONFIGFILE

payloads/external/SeaBIOS

string

SeaBIOS config file

This option allows a platform to set Kconfig options for a basic
SeaBIOS payload. In general, if the option is used, the default
would be "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios"

SEABIOS_BOOTORDER_FILE

payloads/external/SeaBIOS

string

SeaBIOS bootorder file

Add a SeaBIOS bootorder file. From the wiki:
"The bootorder file may be used to configure the boot up order. The file
should be ASCII text and contain one line per boot method. The description
of each boot method follows an Open Firmware device path format. SeaBIOS
will attempt to boot from each item in the file - first line of the file
first."

If used, a typical value would be:
$(top)/src/mainboard/$(MAINBOARDDIR)/bootorder

SEABIOS_DEBUG_LEVEL

payloads/external/SeaBIOS

int

SeaBIOS debug level (verbosity)

The higher the number, the more verbose SeaBIOS will be. See the table
below for the current values corresponding to various items as of SeaBIOS
version 1.10.1. Set this value to -1 to use SeaBIOS' default.

In the above example 10ec is the PCI vendor ID (in hex, but without
the "0x" prefix) and 8168 specifies the PCI device ID of the
network card (also in hex, without "0x" prefix).

Under GNU/Linux you can run `lspci -nn` to list the IDs of your PCI devices.

FILO_STABLE

payloads/external/FILO

bool

0.6.0

Stable FILO version

FILO_MASTER

payloads/external/FILO

bool

HEAD

Newest FILO version

PAYLOAD_FILE

payloads/external/linux

string

Linux path and filename

The path and filename of the bzImage kernel to use as payload.

LINUX_COMMAND_LINE

payloads/external/linux

string

Linux command line

A command line to add to the Linux kernel.

LINUX_INITRD

payloads/external/linux

string

Linux initrd

An initrd image to add to the Linux kernel.

PAYLOAD_FILE

payloads/external/tianocore

string

Tianocore binary

The result of a corebootPkg build

PAYLOAD_FILE

payloads/external/tianocore

string

Tianocore version

Select which version of Tianocore to build (default is to build stable)
stable: a version of Tianocore that builds without any errors
master: most recent version from upstream Tianocore repository
revision: use specific commit or branch to build Tianocore (specified by user)

TIANOCORE_STABLE

payloads/external/tianocore

bool

stable

Select this option to build the stable tianocore version
i.e. a version of Tianocore that builds without any errors

TIANOCORE_MASTER

payloads/external/tianocore

bool

master

Select this option to build the master tianocore version
i.e. most recent version from upstream Tianocore repository

TIANOCORE_REVISION

payloads/external/tianocore

bool

git revision

Select this option if you have a specific commit or branch
that you want to use as the revision from which to
build Tianocore.

You will be able to specify the name of a branch or a commit id
later.

TIANOCORE_REVISION_ID

payloads/external/tianocore

string

Insert a commit's SHA-1 or a branch name

The commit's SHA-1 or branch name of the revision to use.

TIANOCORE_REVISION_ID

payloads/external/tianocore

string

Target architecture

The Tianocore coreboot Payload Package binary can be
built for either only IA32 or both X64 and IA32 architectures.
Select which architecture(s) to build for; default is to build
for both X64 and IA32.

TIANOCORE_TARGET_IA32

payloads/external/tianocore

bool

IA32

By selecting this option, the target architecture will be built
for only IA32.

TIANOCORE_TARGET_X64

payloads/external/tianocore

bool

X64

By selecting this option, the target architecture will be built
for X64 and IA32.

TIANOCORE_TARGET_X64

payloads/external/tianocore

bool

Tianocore build

Select whether to generate a debug or release build for
Tianocore; default is to generate a release build.

TIANOCORE_DEBUG

payloads/external/tianocore

bool

Generate Tianocore debug build

Generate a debug build.

TIANOCORE_RELEASE

payloads/external/tianocore

bool

Generate Tianocore release build

Generate a release build.

GRUB2_STABLE

payloads/external/GRUB2

bool

2.02

Stable GRUB2 version

GRUB2_MASTER

payloads/external/GRUB2

bool

HEAD

Newest GRUB2 version

GRUB2_REVISION

payloads/external/GRUB2

bool

git revision

Select this option if you have a specific commit or branch
that you want to use as the revision from which to
build GRUB2.

You will be able to specify the name of a branch or a commit id
later.

GRUB2_REVISION_ID

payloads/external/GRUB2

string

Insert a commit's SHA-1 or a branch name

The commit's SHA-1 or branch name of the revision to use.

GRUB2_EXTRA_MODULES

payloads/external/GRUB2

string

Extra modules to include in GRUB image

Space-separated list of additional modules to include. Few common
ones:

bsd for *BSD

png/jpg for PNG/JPG images

gfxmenu for graphical menus (you'll need a theme as well)

gfxterm_background for setting background

GRUB2_INCLUDE_RUNTIME_CONFIG_FILE

payloads/external/GRUB2

bool

Include GRUB2 runtime config file into ROM image

The GRUB2 payload reads its runtime configuration file from etc/grub.cfg
stored in the CBFS on the flash ROM chip. Without that, it’ll just drop
into a rescue shell.

This configuration may need to be coreboot specific.

Select this option, if you want to include the GRUB2 runtime
configuration file into CBFS as `etc/grub.cfg` automatically.

You will be able to specify the path of the configuration file later.

Without this option you would need to add this file manually with
build/cbfstool build/coreboot.rom add -f grub.cfg -n etc/grub.cfg -t raw

GRUB2_RUNTIME_CONFIG_FILE

payloads/external/GRUB2

string

Path of grub.cfg

The path of the GRUB2 runtime configuration file to be added to CBFS.

DEPTHCHARGE_STABLE

payloads/external/depthcharge

bool

stable

Latest stable version.

DEPTHCHARGE_MASTER

payloads/external/depthcharge

bool

master

Newest Depthcharge version.

DEPTHCHARGE_REVISION

payloads/external/depthcharge

bool

git revision

Select this option if you have a specific commit or branch that
you want to use as the revision from which to build Depthcharge.

You will be able to specify the name of a branch or a commit SHA
later.

DEPTHCHARGE_REVISION_ID

payloads/external/depthcharge

string

Insert a commit's SHA-1 or a branch name

The commit's SHA-1 or branch name of the revision to use.

LP_DEFCONFIG_OVERRIDE

payloads/external/depthcharge

bool

Use default libpayload config

The Depthcharge makefile looks for a file config.<boardname> in the
libpayload/configs directory. Say Y here to use the file defconfig
instead. This is can be a convenience for development purposes, or
if the defaults in defconfig are sufficient for your system.

PAYLOAD_FILE

payloads

string

Payload path and filename

The path and filename of the ELF executable file to use as payload.

PAYLOAD_FILE

payloads

string

Payload compression algorithm

Choose the compression algorithm for the chosen payloads.
You can choose between LZMA and LZ4.

COMPRESSED_PAYLOAD_LZMA

payloads

bool

Use LZMA compression for payloads

In order to reduce the size payloads take up in the ROM chip
coreboot can compress them using the LZMA algorithm.

COMPRESSED_PAYLOAD_LZ4

payloads

bool

Use LZ4 compression for payloads

In order to reduce the size payloads take up in the ROM chip
coreboot can compress them using the LZ4 algorithm.

PAYLOAD_OPTIONS

payloads

string

Additional cbfstool options for the payload

PAYLOAD_IS_FLAT_BINARY

payloads

string

Add the payload to cbfs as a flat binary type instead of as an
elf payload

COMPRESS_SECONDARY_PAYLOAD

payloads

bool

Use LZMA compression for secondary payloads

In order to reduce the size secondary payloads take up in the
ROM chip they can be compressed using the LZMA algorithm.

Menu: Secondary Payloads

COREINFO_SECONDARY_PAYLOAD

payloads

bool

Load coreinfo as a secondary payload

coreinfo can be loaded as a secondary payload under SeaBIOS, GRUB,
or any other payload that can load additional payloads.

MEMTEST_SECONDARY_PAYLOAD

payloads

bool

Load Memtest86+ as a secondary payload

Memtest86+ can be loaded as a secondary payload under SeaBIOS, GRUB,
or any other payload that can load additional payloads.

MEMTEST_STABLE

payloads

bool

Stable

Stable Memtest86+ version.

For reproducible builds, this option must be selected.

MEMTEST_MASTER

payloads

bool

Master

Newest Memtest86+ version.

This option will fetch the newest version of the Memtest86+ code,
updating as new changes are committed. This makes the build
non-reproducible, as it can fetch different code each time.

NVRAMCUI_SECONDARY_PAYLOAD

payloads

bool

Load nvramcui as a secondary payload

nvramcui can be loaded as a secondary payload under SeaBIOS, GRUB,
or any other payload that can load additional payloads.

TINT_SECONDARY_PAYLOAD

payloads

bool

Load tint as a secondary payload

tint can be loaded as a secondary payload under SeaBIOS, GRUB,
or any other payload that can load additional payloads.

Menu: Debugging

GDB_STUB

toplevel

bool

GDB debugging support

If enabled, you will be able to set breakpoints for gdb debugging.
See src/arch/x86/lib/c_start.S for details.

GDB_WAIT

toplevel

bool

Wait for a GDB connection in the ramstage

If enabled, coreboot will wait for a GDB connection in the ramstage.

FATAL_ASSERTS

toplevel

bool

Halt when hitting a BUG() or assertion error

If enabled, coreboot will call hlt() on a BUG() or failed ASSERT().

DEBUG_CBFS

toplevel

bool

Output verbose CBFS debug messages

This option enables additional CBFS related debug messages.

DEBUG_RAM_SETUP

toplevel

bool

Output verbose RAM init debug messages

This option enables additional RAM init related debug messages.
It is recommended to enable this when debugging issues on your
board which might be RAM init related.

If enabled, every function will print information to console once
the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
of calling function. Please note some printk related functions
are omitted from trace to have good looking console dumps.

DEBUG_COVERAGE

toplevel

bool

Debug code coverage

If enabled, the code coverage hooks in coreboot will output some
information about the coverage data that is dumped.

DEBUG_BOOT_STATE

toplevel

bool

Debug boot state machine

Control debugging of the boot state machine. When selected displays
the state boundaries in ramstage.

Don't include default fill_lb_framebuffer() implementation. Select
this if your drivers uses MAINBOARD_DO_NATIVE_VGA_INIT but provides
its own fill_lb_framebuffer() implementation.

RAMSTAGE_ADA

lib

bool

Selected by features that use Ada code in ramstage.

RAMSTAGE_LIBHWBASE

lib

bool

Selected by features that require `libhwbase` in ramstage.

FLATTENED_DEVICE_TREE

lib

bool

Selected by features that require to parse and manipulate a flattened
devicetree in ramstage.

POWER_BUTTON_DEFAULT_ENABLE

toplevel

bool

Select when the board has a power button which can optionally be
disabled by the user.

POWER_BUTTON_DEFAULT_DISABLE

toplevel

bool

Select when the board has a power button which can optionally be
enabled by the user, e.g. when the board ships with a jumper over
the power switch contacts.

POWER_BUTTON_FORCE_ENABLE

toplevel

bool

Select when the board requires that the power button is always
enabled.

POWER_BUTTON_FORCE_DISABLE

toplevel

bool

Select when the board requires that the power button is always
disabled, e.g. when it has been hardwired to ground.

POWER_BUTTON_IS_OPTIONAL

toplevel

bool

Internal option that controls ENABLE_POWER_BUTTON visibility.

REG_SCRIPT

toplevel

bool

Internal option that controls whether we compile in register scripts.

MAX_REBOOT_CNT

toplevel

int

Internal option that sets the maximum number of bootblock executions allowed
with the normal image enabled before assuming the normal image is defective
and switching to the fallback image.

CREATE_BOARD_CHECKLIST

toplevel

bool

When selected, creates a webpage showing the implementation status for
the board. Routines highlighted in green are complete, yellow are
optional and red are required and must be implemented. A table is
produced for each stage of the boot process except the bootblock. The
red items may be used as an implementation checklist for the board.

MAKE_CHECKLIST_PUBLIC

toplevel

bool

When selected, build/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html
is copied into the Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board
directory.

CHECKLIST_DATA_FILE_LOCATION

toplevel

string

Location of the <stage>_complete.dat and <stage>_optional.dat files
that are consumed during checklist processing. <stage>_complete.dat
contains the symbols that are expected to be in the resulting image.
<stage>_optional.dat is a subset of <stage>_complete.dat and contains
a list of weak symbols which the resulting image may consume. Other
symbols contained only in <stage>_complete.dat will be flagged as
required and not implemented if a weak implementation is found in the
resulting image.

NO_XIP_EARLY_STAGES

toplevel

bool

Identify if early stages are eXecute-In-Place(XIP).

EARLY_CBMEM_LIST

toplevel

bool

Enable display of CBMEM during romstage and postcar.

RELOCATABLE_MODULES

toplevel

bool

If RELOCATABLE_MODULES is selected then support is enabled for
building relocatable modules in the RAM stage. Those modules can be
loaded anywhere and all the relocations are handled automatically.

NO_STAGE_CACHE

toplevel

bool

Do not save any component in stage cache for resume path. On resume,
all components would be read back from CBFS again.

GENERIC_GPIO_LIB

toplevel

bool

If enabled, compile the generic GPIO library. A "generic" GPIO
implies configurability usually found on SoCs, particularly the
ability to control internal pull resistors.

GENERIC_SPD_BIN

toplevel

bool

If enabled, add support for adding spd.hex files in cbfs as spd.bin
and locating it runtime to load SPD. Additionally provide provision to
fetch SPD over SMBus.

DIMM_MAX

toplevel

int

Total number of memory DIMM slots available on motherboard.
It is multiplication of number of channel to number of DIMMs per
channel