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Abstract:

A method for producing a MEMS device comprises forming a semiconductor
layer stack, the semiconductor layer stack comprising at least a first
monocrystalline semiconductor layer, a second monocrystalline
semiconductor layer and a third monocrystalline semiconductor layer, the
second monocrystalline semiconductor layer formed between the first and
third monocrystalline semiconductor layers. A semiconductor material of
the second monocrystalline semiconductor layer is different from
semiconductor materials of the first and third monocrystalline
semiconductor layers. After forming the semiconductor layer stack, at
least a portion of each of the first and third monocrystalline
semiconductor layers is concurrently etched.

Claims:

1. A method for producing a MEMS device comprising: forming a
semiconductor layer stack, the semiconductor layer stack comprising at
least a first monocrystalline semiconductor layer, a second
monocrystalline semiconductor layer and a third monocrystalline
semiconductor layer, the second monocrystalline semiconductor layer
formed between the first and third monocrystalline semiconductor layers,
wherein a semiconductor material of the second monocrystalline
semiconductor layer is different from semiconductor materials of the
first and third monocrystalline semiconductor layers; and after forming
the semiconductor layer stack, concurrently etching at least a portion of
each of the first and third monocrystalline semiconductor layers.

2. The method according to claim 1, wherein the first, second and third
monocrystalline semiconductor layers are epitaxial grown monocrystalline
semiconductor layers.

3. The method according to claim 1, wherein a movable MEMS element is
formed by a portion of the second monocrystalline layer, the portion of
the second monocrystalline layer being released by the etching of at
least a portion of each of the first and third monocrystalline
semiconductor layers.

4. The method according to claim 3, wherein the semiconductor layer stack
further comprises fourth and fifth semiconductor layers, wherein the
first monocrystalline semiconductor layer is formed above the fourth
semiconductor layer and wherein the fifth semiconductor layer is formed
above the third monocrystalline semiconductor layer, wherein a first gap
between the fourth semiconductor layer and the second monocrystalline
semiconductor layer and a second gap between the second monocrystalline
semiconductor layer and the fifth semiconductor layer is formed by the
etching of at least a portion of the first and third monocrystalline
semiconductor layers.

5. The method according to claim 4, wherein the second monocrystalline
semiconductor layer and the fourth and fifth semiconductor layers
comprise a same semiconductor material.

6. The method according to claim 5, wherein the first and third
monocrystalline semiconductor layers comprise a semiconductor material
different from a semiconductor material of the second monocrystalline
semiconductor layer and the fourth and fifth semiconductor layers.

7. The method according to claim 1, wherein a semiconductor crystal
structure of the first and third monocrystalline semiconductor layers
have a first lattice constant which is different to a second lattice
constant of a semiconductor crystal structure of the second
monocrystalline semiconductor layer, wherein a difference of the first
and second lattice constants is not greater than 10%.

8. The method according to claim 7, wherein the first and third
monocrystalline semiconductor layers comprise a compound semiconductor.

9. The method according to claim 8, wherein a crystal structure of the
second monocrystalline semiconductor layer is formed by a lattice
arrangement of first atoms and a crystal structure of the compound
semiconductor is formed by a lattice arrangement of the first atoms and
second atoms.

10. The method according to claim 9 wherein the first and second atoms
are chemical elements of a same group within a periodic table of chemical
element.

11. The method according to claim 1, wherein the etching of at least a
portion of each of the first and third monocrystalline semiconductor
layer removes at least a portion of the first and third monocrystalline
semiconductor layers above and below of a first portion of the second
monocrystalline semiconductor layer while the first and third
monocrystalline semiconductor layer remains above and below a second
portion of the second monocrystalline semiconductor layer.

12. The method according to claim 11, wherein no etch stop is provided
lateral to the first and third monocrystalline semiconductor layers to
stop the etching of at least a portion of the first and third
monocrystalline semiconductor layers.

13. The method according to claim 1, wherein a lateral etch stop is
provided lateral to at least one of the first and third monocrystalline
semiconductor layers to stop the etching of at least a portion of the
first and third monocrystalline semiconductor layers.

14. The method according to claim 1, wherein an etchant is provided via
channels which vertically extend at least between the first and third
monocrystalline semiconductor layers.

15. The method according to claim 14, wherein the channels are at least
partially filled with monocrystalline semiconductor material prior to the
etching of at least a portion of the first and third monocrystalline
semiconductor layers.

16. The method according to claim 15, wherein the monocrystalline
semiconductor material in the channels comprises a same material as the
material of at least one of the first and third monocrystalline
semiconductor layers.

17. The method according to claim 1, wherein a portion of the second
monocrystalline layer provides a movable element of the MEMS device,
wherein the second monocrystalline semiconductor layer is structured
prior to the etching of at least a portion of the first and third
monocrystalline semiconductor layers such that gap portions at least
partially surrounding the portion of the second monocrystalline layer are
formed in the second monocrystalline semiconductor layer.

18. The method according to claim 17, wherein forming the semiconductor
stack comprises: epitaxial growing the second monocrystalline
semiconductor layer on the first monocrystalline semiconductor layer;
structuring the second monocrystalline semiconductor layer such that gap
portions are formed by removing at least a portion of the second
monocrystalline semiconductor layer; providing an epitaxial grow process
to form the third monocrystalline semiconductor layer above the second
monocrystalline semiconductor layer and to fill the gap portions with
epitaxial grown semiconductor material; etching at least a portion of
each of the first and third monocrystalline semiconductor layers and at
least a portion of the epitaxial grown semiconductor material in the gap
portions.

19. The method according to claim 14, wherein a portion of the second
monocrystalline semiconductor layer forms a movable element of the MEMS
device, wherein the channels at least partially surround the portion of
the second monocrystalline semiconductor layer.

20. The method according to claim 4, wherein the fifth semiconductor
layer forms a cover of the MEMS device.

21. The method according to claim 20, wherein the method further
comprises a forming of channels extending at least from the fifth
semiconductor layer to the first monocrystalline semiconductor layer, and
wherein the method further comprises a process to seal the channels in
the fifth layer.

22. The method according to claim 4, further comprising forming a sixth
monocrystalline semiconductor layer, a seventh monocrystalline
semiconductor layer and an eighth monocrystalline semiconductor layer,
wherein the sixth monocrystalline semiconductor layer is formed above the
fifth semiconductor layer and wherein the seventh monocrystalline
semiconductor layer is formed between the sixth monocrystalline
semiconductor layer and the eighth monocrystalline semiconductor layer,
and wherein at least a portion of the sixth and eighth monocrystalline
semiconductor layers is etched to release a further movable MEMS element.

23. A MEMS device comprising: a movable MEMS element comprising a
monocrystalline semiconductor material; a non-movable semiconductor layer
stack lateral to the movable MEMS element, the semiconductor layer stack
comprising at least a first monocrystalline semiconductor layer, a second
monocrystalline semiconductor layer and a third monocrystalline
semiconductor layer, the second monocrystalline semiconductor layer
formed between the first and third monocrystalline semiconductor layers;
and a gap structure surrounding the movable MEMS element and separating
the movable MEMS element in lateral directions from the layer stack.

24. The MEMS device according to claim 23, wherein a vertical extension
of the movable MEMS element is equal to a vertical extension of the
second monocrystalline semiconductor layer, wherein a vertical extension
of a first gap below the movable MEMS element is equal to a vertical
extension of the first monocrystalline semiconductor layer and a vertical
extension of a second gap above the movable MEMS element is equal to a
vertical extension of the third monocrystalline semiconductor layer.

25. A method of producing vertically stacked MEMS devices, the method
comprising: forming a first plurality of monocrystalline semiconductor
layers of a semiconductor material such that a first monocrystalline
semiconductor layer is formed between a first pair of monocrystalline
semiconductor layers; etching at least a portion of each layer of the
first pair of monocrystalline semiconductor layers; forming a second
plurality of monocrystalline semiconductor layers of a semiconductor
material such that a second monocrystalline semiconductor layer is formed
between a second pair of monocrystalline semiconductor layers; etching at
least a portion of each layer of the second pair of monocrystalline
semiconductor layers.

26. The method according to claim 25, wherein etching at least a portion
of each layer of the first pair of monocrystalline semiconductor layers
releases a first movable element of a first MEMS device and etching at
least a portion of each layer of the second pair of monocrystalline
semiconductor layers releases a second movable element of a second MEMS
device.

Description:

CROSS REFERENCE TO RELATED APPLICATION

[0001] This application is a Non Provisional of U.S. Provisional Patent
Application Ser. No. 62/045,289, which was filed September. This
application is incorporated herein by reference in its entirety.

[0003] MEMS is a technology of very small mechanical structures on a
microscale or nanoscale. A movement of the mechanical structures of MEMS
devices is typically sensed or actuated by electrical signals. MEMS
devices are typically manufactured on or within semiconductor substrates
or other materials. MEMS devices can be used in a variety of applications
such as pressure sensors, accelerometers and gyroscopes. Typically, MEMS
devices made from silicon are fabricated by polysilicon processes which
results in a movable element having a polycrystalline structure. In view
of this, there is a need for an improved MEMS technology which allows
improved manufacturing of MEMS devices with a monocrystalline movable
element.

SUMMARY

[0004] According to an embodiment, a method for producing a MEMS device
comprises forming a semiconductor layer stack, the semiconductor layer
stack comprising at least a first monocrystalline semiconductor layer, a
second monocrystalline semiconductor layer and a third monocrystalline
semiconductor layer, the second monocrystalline semiconductor layer
formed between the first and third monocrystalline semiconductor layers.
A semiconductor material of the second monocrystalline semiconductor
layer is different from semiconductor materials of the first and third
monocrystalline semiconductor layers. After forming the semiconductor
layer stack, at least a portion of each of the first and third
monocrystalline semiconductor layers is concurrently etched.

[0005] According to a further embodiment, a MEMS device comprises a
movable MEMS element comprising a monocrystalline semiconductor material
and a non-movable semiconductor layer stack lateral to the movable MEMS
element. The semiconductor layer stack comprises at least a first
monocrystalline semiconductor layer, a second monocrystalline
semiconductor layer and a third monocrystalline semiconductor layer, the
second monocrystalline semiconductor layer formed between the first and
third monocrystalline semiconductor layers. A gap structure surrounds the
movable MEMS element and separates the movable MEMS element in lateral
directions from the layer stack.

[0006] According to a further embodiment, a method of producing vertically
stacked MEMS devices comprises forming a semiconductor layer stack, the
semiconductor layer stack comprising a first plurality of monocrystalline
semiconductor layers of a first semiconductor material and a second
plurality of monocrystalline semiconductor layers of a second
semiconductor material, such that a first one of the first plurality of
monocrystalline semiconductor layers is formed between a first pair of
the second plurality of monocrystalline semiconductor layers and a second
one of the first plurality of monocrystalline semiconductor layers is
formed between a second pair of the second plurality of semiconductor
layers. Thereafter, a portion of each layer of the second plurality of
monocrystalline semiconductor layers is concurrently etched.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0007] FIGS. 1A to 1D show cross-sectional views of an embodiment for
manufacturing a MEMS device at various stages;

[0008] FIG. 2 shows a schematic top view of a layer according to an
embodiment;

[0009] FIGS. 3A to 3H show cross-sectional views of an embodiment for
manufacturing a MEMS device at various stages;

[0010] FIGS. 4A to 4H show cross-sectional views of an embodiment for
manufacturing a MEMS device at various stages;

[0011] FIG. 5 shows a flow chart diagram according to an embodiment;

[0012] FIG. 6 shows a flow chart diagram according to an embodiment; and

[0013] FIGS. 7A to 7E show cross-sectional views of an embodiment for
manufacturing a MEMS device at various stages.

DETAILED DESCRIPTION

[0014] The following detailed description explains exemplary embodiments
of the present invention. The description is not to be taken in a
limiting sense, but is made only for the purpose of illustrating the
general principles of embodiments of the invention while the scope of
protection is only determined by the appended claims.

[0015] It is to be understood that the features of the various exemplary
embodiments described herein may be combined with each other, unless
specifically noted otherwise.

[0016] In the various figures, identical or similar entities, modules,
devices etc. may have assigned the same reference number. Example
embodiments will now be described more fully with reference to the
accompanying drawings. Embodiments, however, may be embodied in many
different forms and should not be construed as being limited to the
embodiments set forth herein. Rather, these example embodiments are
provided so that this disclosure will be thorough and complete, and will
fully convey the scope to those skilled in the art. In the drawings, the
thicknesses of layers and regions are exaggerated for clarity.

[0017] In the described embodiments, various specific views or schematic
views of elements, devices, features, etc. are shown and described for a
better understanding of embodiments. It is to be understood that such
views may not be drawn to scale. Furthermore, such embodiments may not
show all features, elements etc. contained in one or more figures with a
same scale, i.e. some features, elements etc. may be shown oversized such
that in a same figure some features, elements, etc. are shown with an
increased or decreased scale compared to other features, elements etc.

[0018] It will be understood that when an element is referred to as being
"on," "between", "connected to," "electrically connected to," or "coupled
to" to another component, it may be directly on, between, connected to,
electrically connected to, or coupled to the other component or
intervening components may be present. In contrast, when a component is
referred to as being "directly on," "directly connected to," "directly
electrically connected to," or "directly coupled to" another component,
there are no intervening components present. As used herein, the term
"and/or" includes any and all combinations of one or more of the
associated listed items.

[0019] Spatially relative terms, such as "vertical", "lateral" "beneath,"
"below," "lower," "above," "upper," and the like may be used herein for
ease of description to describe the relationship of one component and/or
feature to another component and/or feature, or other component(s) and/or
feature(s), as illustrated in the drawings. It will be understood that
the spatially relative terms are intended to encompass different
orientations of the device in use or operation in addition to the
orientation depicted in the figures.

[0020] Embodiments described below are directed to a new concept to
manufacture a MEMS device. The described embodiments allow manufacturing
of a MEMS device having a movable MEMS element of moncrystalline
structure.

[0021] Referring to FIGS. 1A-1D, a first embodiment showing various stages
of the manufacturing process of a MEMS device will be described. FIGS.
1A-1D show cross sectional views along a x-z plane which is perpendicular
to a main surface of the MEMS device. Starting at FIG. 1A, a vertical
layer stack of monocrystalline layers comprising semiconductor layers
102, 104 and 106 of monocrystalline structure is provided. The layer
stack shown in FIG. 1A may in a lateral direction continuously extend
from one wafer edge to another edge or may be provided in predefined or
preselected areas of a wafer. In the stack, the layer 104 is provided
above the layer 102 and the layer 106 is provided above the layer 104.
The semiconductor layers 102, 104 and 106 may each have a thickness
between X and Y μm. In some embodiments, the layers 102 and 106 may be
thinner than the layer 104.

[0022] It is to be noted that in embodiments, the layer stack can be
formed on regular silicon or other semiconductor wafers without requiring
the use of SOI substrates. Thus, the embodiments described below allow
the forming of monocrystalline MEMS devices without using SOI (silicon on
insulator) wafers which are typically more expensive than regular
semiconductor wafers.

[0023] The semiconductor layers 102, 104 and 106 may be epitaxial grown
layers. The layer 102 may be epitaxial grown on a layer 108 below layer
102. Layer 108 may be a bulk semiconductor layer such as a bulk
semiconductor wafer. Furthermore, the layer 104 may be epitaxial grown on
the layer 102 and the layer 106 may be epitaxial grown on the layer 104.

[0024] A further layer 110 is provided above layer 106 such that the
layers 102, 104 and 106 are sandwiched between the layer 108 and the
layer 110. The layer 110 may in some embodiments have a monocrystalline
structure. The layer 110 may in some embodiments have a
non-monocrystalline structure such as a polycrystalline or amorphous
structure. The layers 102, 104 and 106 may be formed such that the
crystalline structures of adjacent layers are formed of different
materials. For example, according to an embodiment, the layer 102 and 106
may be formed of a same semiconductor material while the layer 104 may be
formed of a semiconductor material different to the layers 102 and 106.
In other embodiments, each of the layer 102, 104 and 106 may be formed of
mutual different semiconductor material. The materials of the layers 102
and 106 may be selected to have a good etching selectivity against the
material of the layer 104. In other words, the material of the layers 102
and 106 may be selected such that the layers 102 and 106 can be etched
selective to the layer 104 such that the layer 104 is not or barely
etched when the material of the layers 102 and 106 is etched. In some
embodiments, a semiconductor crystal structure of the layers 102 and 106
may have a lattice constant (dimension of the repeating element of the
crystal structure) which is different to a lattice constant of the
semiconductor crystal structure of the layer 104.

[0025] In some embodiments, the layers 102 and 106 may be formed of a
compound semiconductor material while the layer 104 is formed of a
non-compound semiconductor material. Compound semiconductor materials are
semiconductor materials which have a lattice structure comprising two or
more different chemical elements such as silicon germanium (SiGe),
gallium arsenide (GaAs) etc. In some embodiments, the crystal structure
of the layer 104 may be a non-compound material formed by a lattice
arrangement of first atoms (e.g. silicon) and a crystal structure of the
compound semiconductor material of the layers 102 and 106 is formed by a
lattice arrangement of the first atoms and second atoms (e.g. silicon and
germanium). Thus, the layers 102 and 106 may be formed in some
embodiments of silicon germanium and the layer 104 may be may be formed
of silicon. In some embodiments, it may be vice versa, i.e. the layers
102 and 106 may be formed of a non-compound semiconductor material and
the layer 104 may be formed of a compound semiconductor material. It is
to be understood that in some embodiments, the layers 102, 104 and 106
may be intentionally or unintentionally doped with a dopant (doping
agent), e.g. during the growing of the layer or after the growing of the
layer. In some embodiments, adjacent layers of the layers 102, 104 and
106 may be doped with a mutual different doping type, e.g. the layers 102
and 106 may be p-doped and layer 104 may be n-doped, or vice versa.

[0026] In some embodiments, the layer 108 may be a semiconductor bulk
substrate which is significantly thicker (e.g. 10 times) than the layers
102, 104 and 106. In some embodiments, the layer 108 may be a
semiconductor layer provided on a substrate. In embodiments, the layers
102, 104 and 106 extend parallel to a main surface of the substrate. The
layer 108 is in some embodiments formed from the same material as the
layer 104. Furthermore the layer 110 may be formed from the same material
as layer 104 such that layers 102 and 106 can be etched selective to the
layers 104, 108 and 110.

[0027] Referring now to FIG. 1B, after the forming of layers 102 to 110,
channel structures 112 are etched in the layer stack. As can be seen from
FIG. 1B, the channel structures 112 extend in a vertical direction from
the top of the layer 110 through the layers 106 and 104. In some
embodiments, the channel structures 112 may extend at least partially
into the layer 102 or may extend fully throughout the layer 102. A ratio
of a channel width of the channel structures 112 to a thickness of the
layer 102 or the layer 106 may be may in some embodiments within a range
between 1 and 5. Such ratios may for example provide sufficient etching
rates for the layers 102 and 106 while good control of the etching is
obtained when no etch stops are used lateral of the layers 102 and 106.
Furthermore, such ratios allow sufficient lateral gap distances for the
movable element as will be explained later.

[0028] Etching of the channel structures 112 is performed such that a
layer stack portion 114 of the layer 104 extends between channel
structures 112. It is to be understood that predefined mask structures
may be deposited and structured prior to the etching of the channel
structures 112 in order to etch the channel structures 112 into the layer
stack. The mask structures may be removed after the channels structures
112 have been etched.

[0029] In a next step shown in FIG. 1C, a selective etching of the layers
102 and 106 is performed to remove at least a portion of the layer 102
and a portion of the layer 106. The etchant for etching the layers 102
and 106 is provided via the channel structures 112. Since the etchant is
provided from the top of the layer stack, i.e. from the top surface of
the layer 110, and in view of the layer 106 being closer to the top than
the layer 102, a greater portion is etched in the layer 106 than in the
layer 102. In the embodiment shown, no etch stops are provided in a
direction lateral of the layers 102 and 106 to stop the etching of the
layers 102 and 106 in lateral directions. Therefore, the extension of the
portions removed in the layers 102 and 106 in a lateral direction are
defined only by the etching time and the etch rate.

[0030] In the embodiment, the layers 102 and 106 are completely removed in
the portion 114 of the layer stack between the channel structures 112. In
the portion 114 of the layer stack, a first gap 116 is generated between
the layer 108 and the layer 104 by the removing of the layer 102 in the
layer stack portion 114. Furthermore, a second gap 118 is generated
between the layer 104 and the layer 110 by the removing of the layer 106
in the layer stack portion 114. As a result of the selective etching, a
portion 104A of the layer 104 forming a movable element of the MEMS
device is released and the portion 104A is thereafter a movable element
104A. Furthermore, portions 104B lateral to the movable element 104A and
separated by the channel structures 112 remain after the selective
etching and form non-movable portions 104B of the layer 104.

[0031] FIG. 1D shows the MEMS device after a sealing process is applied
for sealing holes generated by the channel structures 112 in the layer
110. In the embodiment shown in FIG. 1D, the layer 110 is sealed with
monocrystalline material, e.g. by epitaxial deposition of monocrystalline
semiconductor material. This allows the manufacturing of a further
vertically stacked MEMS device as will be described with respect to FIGS.
7A to 7E. It is to be noted, however, that the sealing process can
include other sealing processes such as the deposition of
poly-crystalline material or other material. In some embodiments, an
etching process may be applied after the sealing process to obtain a
plain surface. In some embodiments, the sealing provides a hermetically
sealed cavity including the movable element. A hermetically sealed cavity
allows the movable element to move at low pressures thereby reducing
damping and other effects caused by ambient air.

[0032] As can be seen from FIG. 1D, the channel structures 112 define a
lateral gap between the movable element 104A and the non-movable portions
104B of the layer 104. The channel structures 112 thus are not only used
for providing the etchant for the selective etching to the layers 102 and
106 but also define the lateral gap between the movable element 104A and
the non-movable portions of the layer 104 which allows the movable
element 104A to move in lateral directions and for example to sense a
variation of the distance between the movable element 104A and the
non-movable portions 104B of the layer 104.

[0033] The movable element 104A can have a variety of forms and structures
depending on the type of MEMS device and the application. The movable
element 104A may include any element which is capable of a mechanical
movement of the entire element or portions of the element relative to
non-movable portions of the MEMS device such as the non-movable portions
104B or a substrate. The mechanical movement may include movements
resulting from mechanical forces acting on the MEMS device such as an
acceleration or rotation. In such application the movement of the movable
element 104A can be sensed and a quantity representing the physical act
can be determined based on the sensed movement. The mechanical movement
may also include movements which are induced by the MEMS device itself
for example by applying electric drive signals to induce such movements.
The MEMS device may be a sensor, an actuator or an oscillator for example
to provide timing applications. The mechanical movement may be a
rotational movement, a linear movement, a flexure movement, a strain
movement, a stress movement, a compression movement or other types of
mechanical movements. The movable element 104A may be a beam or
cantilever which is anchored at one or more anchor portions to allow a
rotational movement around the anchor portions or a movement between two
anchor portions or a flexure of the beam. The movable element 104A may
include specific structures such as a finger structure to allow
capacitive sensing of the movement with high signal strength. The finger
structure may be arranged interdigital with a finger structure of the
non-movable portions. The movable element 104A may in some embodiments
include membrane-like elements capable to bend or deform in response to
mechanical forces or applied electric signals.

[0034] In some embodiments, the movable element 104A may be capable of
moving only in one dimension. In some embodiments the movable element may
be capable to move in two dimensions. In some embodiments, the movable
element 104A may be capable to move in three dimensions. In some
embodiments, the movable element 104A may be capable of rotation
movements. In some embodiments, the movable element 104A may be capable
of linear movements. In some embodiments, the movable element 104A may be
capable of rotation movements and linear movements.

[0035] In some embodiments, the movable element 104A may be movable in
lateral directions such that a gap distance between the movable element
104A and the remaining portions of the layer 104 changes in view of the
movement. Physical quantities such as an acceleration or a rotation rate
may be detected by such movements of the movable element 104A. The
variation of the gap distance between the movable element 104A and the
non-movable portions 104B of the layer 104 can be measured for example by
detecting a change of the electric capacitance between the movable
element 104A and the non-movable portions 104B of the layer 104. The
physical quantity can be detected by further evaluation and processing of
an electric capacitance signal in electronic circuitry. The electronic
circuitry may be monolithically integrated in the MEMS device or may be
provided within a separate integrated circuit device. In other
embodiments, the movable element 104A may be capable to move in a
vertical direction. In some embodiments, the movable element 104A may be
capable to move in vertical and lateral directions.

[0036] For detection purposes, a doping process can be applied when
forming the layer 104 or at a later stage of the process. The doping of
the layer 104 increases the electric conductivity of the movable element
104A and the non-movable portions 104B of the layer 104 and may therefore
enhance a detection of the electric capacitance between them. Electrical
isolation between the movable element 104A and the non-movable portions
104B can be achieved for example by a doping process of different doping
types in order to form an electrical isolating p-n junction.

[0037] It is further to be mentioned that in some embodiments transistors
may be formed in transistor regions to provide an integrated circuitry
for the MEMS. In particular since the described embodiments use
monocrystalline layers for forming the MEMS element, transistor
structures provided in processes such as bipolar, MOS, CMOS or BiCMOS
processes can be formed in a transistor region lateral to the MEMS region
after the MEMS element has been formed.

[0038] FIG. 2 shows now a schematic top view of the layer 104 in a x-y
plane according to an example embodiment. FIG. 2 shows an accelerometer
MEMS device that can be formed with the processes described in
embodiments herein. FIG. 2 shows the movable element 104A as a beam with
a plurality of fingers arranged interdigital with fingers of the
non-movable portions of the layer 104 and separated by a gap defined by
the channel structures 112. The movable element 104A is mechanically
connected at an anchor portion to the non-movable portion 104B. It is to
be noted that FIG. 2 shows only a schematic MEMS device for illustrative
purpose and a variety of other types, structures sizes or forms of MEMS
devices can be provided in other embodiments. For example, amongst other
variations and modifications, the electrode fingers shown in FIG. 2 may
in other embodiments have different size, shape and the number of fingers
may be smaller or higher, the gap provided between the movable element
104A and the non-movable portion may have different sizes and the like.

[0039] In FIG. 5, a flow diagram 500 for manufacturing a MEMS device in
accordance with embodiments described herein is explained.

[0040] The flow diagram 500 starts at 502 with a forming of a stack
comprising first, second and third monocrystalline layers (for example
semiconductor layers 102, 104, 106). As described earlier, the second
monocrystalline semiconductor layer is formed between the first and third
monocrystalline semiconductor layers and a semiconductor material of the
second monocrystalline semiconductor layer is different from
semiconductor materials of the first and third monocrystalline
semiconductor layers. At 504, a movable element is released by
concurrently etching portions of the first and third monocrystalline
layers.

[0041] In some embodiments, the first, second and third monocrystalline
semiconductor layers are formed by an epitaxial growth process. In
embodiments, the movable element is formed by a portion of the second
monocrystalline layer. In some embodiments, the semiconductor layer stack
further comprises fourth and fifth semiconductor layers (e.g. layers 108
and 110), wherein the first monocrystalline semiconductor layer is formed
above the fourth semiconductor layer and wherein the fifth semiconductor
layer is formed above the third monocrystalline semiconductor layer. The
fourth semiconductor layer may be a semiconductor wafer substrate such as
a non-SOI wafer substrate. In a vertical direction, a first gap between
the fourth semiconductor layer and the second monocrystalline
semiconductor layer and a second gap between the second monocrystalline
semiconductor layer and the fifth semiconductor layer is formed by the
etching of at least a portion of the first and third monocrystalline
semiconductor layers.

[0042] In some embodiments, the second monocrystalline semiconductor layer
and the fourth and fifth semiconductor layers comprise a same
semiconductor material.

[0043] In some embodiments, the first and third monocrystalline
semiconductor layers comprise a semiconductor material different from the
second monocrystalline semiconductor layer and the fourth and fifth
semiconductor layers.

[0044] In some embodiments the semiconductor crystal structure of the
first and third monocrystalline semiconductor layer have a first lattice
constant which is different to a second lattice constant of the
semiconductor crystal structure of the second monocrystalline
semiconductor layer, wherein a difference of the first and second lattice
constants is not greater than X %

[0045] In some embodiments, the first and third monocrystalline
semiconductor layers comprise a compound semiconductor. According to some
embodiments, a crystal structure of the second monocrystalline
semiconductor layer is a non-compound semiconductor formed by a lattice
arrangement of first atoms and a crystal structure of the compound
semiconductor is formed by a lattice arrangement of the first atoms and
second atoms. The first and second atoms may be chemical elements of a
same group in the periodic table of chemical element.

[0046] As outlined above, the etching of at least a portion of each of the
first and third monocrystalline semiconductor layers removes at least a
portion of the first and third monocrystalline semiconductor layers above
and below of a first portion of the second monocrystalline semiconductor
layer while the first and third monocrystalline semiconductor layer
remains above and below a second portion of the second monocrystalline
semiconductor layer. It is to be noted that the etching to release the
movable element can be provided from a front side (top side) avoiding
backside etching and manufacturing processes.

[0047] In some embodiments, the etching is provided with no etch stop
lateral to the first and third monocrystalline semiconductor layers to
stop the etching of at least a portion of the first and third
monocrystalline semiconductor layers.

[0048] In some embodiments, a lateral etch stop is provided lateral to at
least one of the first and third monocrystalline semiconductor layers to
stop the etching of at least a portion of the first and third
monocrystalline semiconductor layers. An embodiment in which etch stops
are used will be described further below with respect to FIGS. 4A to 4H.

[0049] In some embodiments, the etchant for etching the portions of the
first and third layers and releasing the movable element is provided via
channels which vertically extend at least between the first and third
monocrystalline semiconductor layers. The channels may for example be
formed by vertical trenches etched into the layer stack. Thus, a vertical
extension of the movable MEMS element is equal to a vertical extension of
the second monocrystalline semiconductor layer, wherein a vertical
extension of a first gap below the movable MEMS element is equal to a
vertical extension of the first monocrystalline semiconductor layer and a
vertical extension of a second gap above the movable MEMS element is
equal to a vertical extension of the third monocrystalline semiconductor
layer.

[0050] FIG. 6. shows a process 600 which starts at 602 with the forming of
a stack comprising first, second and third monocrystalline layers. At
604, channels extending in a vertical direction at least throughout the
second monocrystalline layer are etched into the stack. At 606, the
movable element is released by concurrently etching portions of the first
and third monocrystalline layers via the channel structures.

[0051] In some embodiments, the channels may be at least partially filled
with monocrystalline semiconductor material prior to the etching of at
least a portion of the first and third monocrystalline semiconductor
layers as will be described below with respect to FIGS. 3A to 3H. The
monocrystalline semiconductor material in the channels may be the same
material as the material of at least one of the first and third
monocrystalline semiconductor layers or may be of different material.

[0052] In some embodiments, a portion of the second monocrystalline layer
which forms a movable element of the MEMS device may be structured prior
to the etching of at least a portion of the first and third
monocrystalline semiconductor layers such that gap portions at least
partially surrounding the portion of the second monocrystalline layer are
formed in the second monocrystalline semiconductor layer. In embodiments,
the structuring of the portion of the second monocrystalline layer is
provided by the etching of the channels which at least partially surround
the portion forming the movable element.

[0053] In some embodiments, the releasing of the movable element is
provided such that the portion of the second monocrystalline layer which
forms the movable element is structured in a first etching. The first
etching may be the etching of the channels as described above. After the
first etching, the portion forming the movable element is mechanically
connected in vertical directions to the first layer below and the third
layer above the second monocrystalline layer. The movable element is then
released by the removing the first and third layers.

[0054] In some embodiments, the stack comprises a fifth layer above the
third layer which forms a cover for the MEMS device. Holes formed by the
channels in the fifth layers may be sealed to provide a closed cavity for
the movable element.

[0055] In some embodiments, the fifth layer may be sealed with
monocrystalline material which allows providing an additional stack of
monocrystalline layers above the fifth layer. The additional stack can be
processed in a similar manner as described to form vertically above the
MEMS device an additional MEMS device. Thus, a sixth monocrystalline
semiconductor layer, a seventh monocrystalline semiconductor layer and a
eighth monocrystalline semiconductor layer may be formed, wherein the
sixth monocrystalline semiconductor layer is formed above the fifth
semiconductor layer and wherein the seventh monocrystalline semiconductor
layer is formed between the sixth monocrystalline semiconductor layer and
the seventh monocrystalline semiconductor layer, and wherein at least a
portion of the sixth and seventh monocrystalline semiconductor layers is
etched to release a further movable MEMS element. It is to be understood,
that the above described process allows an easily integrated process for
providing vertically stacked monocrystalline MEMS devices.

[0056] In some embodiments, the channels may be at least partially filled
with monocrystalline semiconductor material prior to the etching of at
least a portion of the first and third monocrystalline semiconductor
layers. An embodiment including such a process step will be described
below with respect to FIGS. 3A to 3H.

[0057] FIG. 3A starts with a layer arrangement in which the layers 102,
104 are provided on the layer 108. As already described with respect to
FIG. 1A, layers 102, 104 and 108 may be monocrystalline layers formed for
example by an epitaxial growth process. With reference to FIG. 3B, a
channel structure 112A extending from a top surface of the layer 104 to
the layer 102 is etched. In a further step, material is deposited which
fills the channel structure 112A and forms a layer 106' on the layer 104
as can be seen from FIG. 3C. The layer 106' is planarized by applying
techniques such as chemical mechanical polishing resulting in a planar
layer 106 as shown in FIG. 3D. The layer 110 is thereafter deposited on
the layer 106 as shown in FIG. 3E. Thereafter, channel structures 112B
extending from a top surface of the layer 110 to the layer 106 are
etched, see FIG. 3F. FIG. 3F shows the channel structures 112B lateral to
the channel structures 112A. The separate forming of the channel
structures 112A and 112B at different stages of the process allows the
forming of the channel structures 112B extending from the layer 110 to
the layer 106 at different locations than the channel structures 112A
extending from the layer 106 to the layer 102. This may bring more
flexibility for the MEMS manufacturing process. Such separation may for
example allow tailoring the selective etching of the layers 102 and 106
according to the needs of the manufacturing process or the MEMS device
since the etchant for etching the layer 102 is introduced via the channel
structure 112A and for etching the layer 106 is introduced via the
channel structure 112B. However, in other embodiments, the channel
structures 112A and 112B may be arranged one below the other similar to
the embodiment described in FIGS. 1A-1D.

[0058] FIG. 3G shows the layers 102 and 106 after portions have been
etched selective to the layer 104. In the selective etching process, the
etchant for etching the layer 106 is introduced via the channel structure
112B. Furthermore, the material of the channel structure 112A is removed
in the selective etching process allowing thereafter the introducing of
the etchant to the layer 106 via the channel structures 112A.

[0059] As shown in FIG. 3H, the holes of the layer 110 provided by the
channel structures 112B are sealed in a similar manner as already
described above with respect to FIGS. 1A-D.

[0060] Referring now to FIGS. 4A to 4H, a further example embodiment is
described. The embodiment of FIGS. 4A to 4H distinguishes from previously
described embodiment in that etch stops are provided lateral to the
layers 102 and 106.

[0061] FIG. 4A starts with a layer arrangement in which the layer 102 is
provided on the layer 108. Next as shown in FIG. 4B, portions of the
layer 102 corresponding to first etch stop regions 102A are etched
selective to the layer 108. A mask to define the first etch stop regions
102A may be provided prior to the selective etching and removed after the
selective etching.

[0062] In a next step, monocrystalline material is deposited for example
by epitaxial growth to fill the first etch stop regions 102A and to form
the layer 104 on the layer 102. The material may be epitaxial grown in
the etch stop regions 102A starting on the layer 108, and otherwise
starting on the layer 102. In some embodiments, the layer 104 may have
the same material as the layer 108, e.g. silicon. Since the material
deposited has a lower etch rate compared to the material of the layer
102, the later applied selective etching of the layer 102 stops in
vertical directions at the layers 104 and 108 and in lateral directions
at the first etch stop regions 102A. A planarization process such as
chemical mechanical polishing (CMP) may be applied to obtain a planar
surface of the layer 104 as shown in FIG. 4C.

[0063] In a further step, the layer 106 is deposited on the layer 104, see
FIG. 4D. Portions of the layer 106 are etched selective to the layer 104
to define second etch stop regions 106A as shown in FIG. 4E.

[0064] In a next step, monocrystalline material is deposited (for example
by epitaxial growth) to fill the second etch stop regions 106A and to
form the layer 110 on the layer 106. During deposition, the material may
epitaxial grow in the second etch stop regions 106A on the layer 104 and
otherwise on the layer 106. In some embodiments, the layer 110 may have
the same material as the layers 104 and 108, e.g. silicon. Since the
material deposited has a lower etch rate compared to the material of the
layer 106, the later applied selective etching of the layer 106 stops in
vertical directions at the layers 104 and 110 and in lateral directions
at the second etch stop regions 106A. A planarization process such as
chemical mechanical polishing (CMP) may be applied to obtain a planar
surface of the layer 110 as shown in FIG. 4F. It is to be noted that the
embodiment shown in FIG. 4F shows the etch stop regions 102A and 106A one
below the other. However it is to be understood that in other embodiments
the etch stop regions 106A may be provided lateral displaced to the etch
stop regions 102A.

[0065] In a next step, the channel structures 112 are etched from a top
side of the layer 110 to the layer 102 in the region between the etch
stop regions 102A and 106A, respectively.

[0066] The selective etching is provided in a next step by applying the
etchant via the channel structures 112 to the layers 102 and 106. The
etching of the layers 102 and 106 is selective to the materials of the
layers 104, 108, 110 and the etch stop regions 102A and 106A. The
selective etching of the layer 102 stops in vertical directions at the
layers 108 and 104 and in lateral directions at the etch stop regions
102A. Furthermore, the selective etching of the layer 106 stops in
vertical directions at the layers 104 and 110 and in lateral directions
at the etch stop regions 106A.

[0067] While the forming of etch stop regions 102A and 106A requires
additional manufacturing steps it may be beneficial for some applications
in which a precise stopping of the selective etching is desired.

[0068] Referring now to FIGS. 7A to 7E, an embodiment of manufacturing
vertically stacked MEMS devices will be described. While the embodiment
described in FIGS. 7A to 7E uses the process of FIGS. 1A to 1D for
manufacturing stacked MEMS devices, it is to be noted that vertically
stacked MEMS devices can be manufactured in accordance with any other
embodiment described herein.

[0069] FIG. 7A shows a cross-sectional view after a MEMS device has been
manufactured in accordance with FIGS. 1A to 1D. In a next step shown in
FIG. 7B, a stack including the monocrystalline layers 702, 704 and 706 is
grown on the monocrystalline layer 110. Furthermore, on top of layer 706,
a layer 710 is provided.

[0070] Next, channel structures 712 extending in a vertical direction are
etched in the layer stack as shown in FIG. 7C in a similar manner as
described above with respect to FIGS. 1A to 1D. Furthermore, similar to
the embodiment of FIGS. 1A to 1D, etching of the layers 702 and 706 is
performed to remove at least a portion of the layer 702 and a portion of
the layer 706. The etching of the layers 702 and 706 is provided
selective to the layers 110, 706 and 710, i.e. the etching rate for
layers 702 and 706 is significantly higher than the etching rate for the
layers 110, 706 and 710. The etchant for etching the layers 702 and 706
is provided via the channel structures 712.

[0071] The layers 702 and 706 are completely removed in a portion 714 of
the layer stack between the channel structures 112. In the portion 714 of
the layer stack, a first gap 716 in vertical direction is generated
between the layer 110 and the layer 704 by the removing of the layer 702
in the layer stack portion 714. Furthermore, a second gap 718 is
generated in a vertical direction between the layer 704 and the layer 710
by the removing of the layer 702 in the layer stack portion 714. As a
result of the selective etching, a portion 704A of the layer 704 forming
a movable element portion of a second MEMS device is released and the
portion 704A is thereafter movable. Furthermore, portions 704B lateral to
the movable element portion 704A and separated by the channel structures
712 remain after the selective etching and form non-movable portions 704B
of the layer 704.

[0072] Referring to FIG. 7E, the holes provided by the channel structures
712 in the layer 710 are sealed. Sealing of the holes may include a
monocrystalline grow of material, deposition of polycrystalline material
or deposition of materials other than semiconductor material.

[0073] It can be seen from FIG. 7E that two vertically stacked MEMS
devices comprising movable monocrystalline elements are formed with the
above described process. It is to be understood that further MEMS devices
can be stacked in the same manner as described. Furthermore, it is to be
understood that stacked MEMS devices can be manufactured by any other
embodiment described herein, for example by manufacturing in accordance
with embodiments utilizing lateral etch stops as described in FIGS. 4A-4H
or embodiments providing channel structures as described with respect to
FIGS. 3A to 3H or any combination thereof.

[0074] In the above description, embodiments have been shown and described
herein enabling those skilled in the art in sufficient detail to practice
the teachings disclosed herein. Other embodiments may be utilized and
derived there from, such that structural and logical substitutions and
changes may be made without departing from the scope of this disclosure.

[0075] This Detailed Description, therefore, is not to be taken in a
limiting sense, and the scope of various embodiments is defined only by
the appended claims, along with the full range of equivalents to which
such claims are entitled.

[0076] Such embodiments of the inventive subject matter may be referred to
herein, individually and/or collectively, by the term "invention" merely
for convenience and without intending to voluntarily limit the scope of
this application to any single invention or inventive concept if more
than one is in fact disclosed. Thus, although specific embodiments have
been illustrated and described herein, it should be appreciated that any
arrangement calculated to achieve the same purpose may be substituted for
the specific embodiments shown. This disclosure is intended to cover any
and all adaptations or variations of various embodiments. Combinations of
the above embodiments, and other embodiments not specifically described
herein, will be apparent to those of skill in the art upon reviewing the
above description.

[0077] It is further to be noted that embodiments described in combination
with specific entities may in addition to an implementation in these
entity also include one or more implementations in one or more
sub-entities or sub-divisions of said described entity. For example,
specific embodiments described herein describe the forming of a feature
or a process step not shown in another embodiment. It is to be understood
that such a feature may be formed also in other embodiments or such a
process step may be applied also in other embodiments, unless it is
explicitly excluded herein or technically not possible.

[0078] The accompanying drawings that form a part hereof show by way of
illustration, and not of limitation, specific embodiments in which the
subject matter may be practiced.

[0079] In the foregoing Detailed Description, it can be seen that various
features are grouped together in a single embodiment for the purpose of
streamlining the disclosure. This method of disclosure is not to be
interpreted as reflecting an intention that the claimed embodiments
require more features than are expressly recited in each claim. Rather,
as the following claims reflect, inventive subject matter lies in less
than all features of a single disclosed embodiment. Thus the following
claims are hereby incorporated into the Detailed Description, where each
claim may stand on its own as a separate embodiment. While each claim may
stand on its own as a separate embodiment, it is to be noted
that--although a dependent claim may refer in the claims to a specific
combination with one or more other claims--other embodiments may also
include a combination of the dependent claim with the subject matter of
each other dependent claim. Such combinations are proposed herein unless
it is stated that a specific combination is not intended. Furthermore, it
is intended to include also features of a claim to any other independent
claim even if this claim is not directly made dependent to the
independent claim.

[0080] Furthermore, it is intended to include in this detailed description
also one or more of described features, elements etc. in a reversed or
interchanged manner unless otherwise noted.

[0081] It is further to be noted that methods disclosed in the
specification or in the claims may be implemented by a device having
means for performing each of the respective steps of these methods.

[0082] Further, it is to be understood that the disclosure of multiple
steps or functions disclosed in the specification or claims may not be
construed as to be within the specific order. Therefore, the disclosure
of multiple steps or functions will not limit these to a particular order
unless such steps or functions are not interchangeable for technical
reasons.

Furthermore, in some embodiments a single step may include or may be
broken into multiple substeps. Such substeps may be included and part of
the disclosure of this single step unless explicitly excluded.