Product Briefing Outline: Applied Materials has launched a trio of new systems designed to boost performance in the next generations of DRAM chips. These systems are claimed to overcome key challenges in fabricating the transistor and contact areas of memory chips, include: the ‘Applied Centura DPN HD’ system to improve the gate insulator scaling; the ‘Applied Endura HAR Cobalt PVD’ system for high aspect ratio contact structures; and the ‘Applied Endura Versa XLR W PVD’ system for reduced gate stack resistance.

Problem: While microprocessor speed has increased significantly over the years, DRAM chips have not kept pace - resulting in a critical performance gap. To overcome this "memory wall," the speed of the control circuitry that transfers data between the memory cell array and external data bus must be increased. DRAM chipmakers are addressing this challenge by adapting key transistor technologies from advanced logic devices to increase transistor density and make room for faster, more sophisticated, control circuitry.

Solution: The Applied Centura DPN HD system is designed to boost transistor performance by incorporating nitrogen atoms into the gate insulator to improve its electrical characteristics. The new high-dose (HD) technique builds on Applied's pioneering decoupled plasma nitridation (DPN) technology, which enables the shrink of transistor dimensions while maintaining optimum transistor performance. By replacing traditional titanium with lower-resistivity cobalt for transistor contact metallization, the new Applied Endura Cobalt PVD system offers a production-proven method to boost switching speed and lower power consumption. The system leverages Applied's decade of experience in cobalt physical vapor deposition (PVD) to deposit uniform films in high-aspect-ratio contact structures with 50% lower contact resistance than titanium. The Applied Endura Versa XLR W PVD system extends Applied's tungsten PVD technology to deliver up to a claimed 20% reduction in gate stack resistivity, enabling a significant improvement in switching speed, a key requirement for gate scaling. In addition, the new system's optimized reactor design is claimed to significantly improve the lifetime of critical consumable components, enabling a claimed 10% lower cost-per-wafer.