Annual Design jobs growth 3.7 % Verification jobs growth : 12.8% – So good to be in demand you the Verification engineers!

Respin Trends: Smaller designs <5M gates have more respins than the large designs of > 80M gates. Sounds odd? Here is Harry’s rationale:

Smaller designs are NOT necessarily less complex. Larger designs are predominantly assembly of pre-verified IPs

Mark then talked about “Accelerating Coverage Closure with Formal Verification”. With some impressive results from customer case studies such as Micron he drove home the point that Formal apps are very useful even for simulation folks with coverage unreachability and other applications.

Doug Smith then followed with his “Power Tips & Tricks to Get the Most Out of Formal” topic:

Then followed one of the key attractions of this event: Ram Narayan, Consulting Member of Technical Staff in Oracle Labs presented on his DAC-2015 popular topic: “Formal Model Checking: From Oblivion to a Pillar of Success”

Detailed agenda (close to final) for upcoming DVTalk event is below. It is a free of cost event, but advance registration is a must. The venue has limited seating so it is first-come-first-serve basi...

Riding on the success of initial few editions of VerifNews' DVTalk event, we are glad to expand it to Hyderabad, Telangana, India this time. As usual with our start-up mode, finer details are still em...