CCIX Project to link ARM Processors and FPGAs for HPC

Today ARM, Xilinx, Cadence, and Taiwan Semiconductor announced plans to produce the first test chip for the Cache Coherent Interconnect for Accelerators (CCIX) project. CCIX (pronounced “C6”) aims to prove that many-core ARM processors linked to FPGAs have a home in HPC.

With the surge in artificial intelligence and big data, we’re seeing increasing demand for more heterogeneous compute across more applications,” said Noel Hurley, vice president and general manager, Infrastructure Group, Arm. “The test chip will not only demonstrate how the latest Arm technology with coherent multichip accelerators can scale across the data center, but reinforces our commitment to solving the challenge of accessing data quickly and easily. This innovative and collaborative approach to coherent memory is a significant step forward in delivering high-performance, efficient data center platforms.”

Accelerating applications in the data center is a growing requirement due to power and space constraints. Applications such as big data analytics, search, machine learning, wireless 4G/5G, in-memory database processing, video analytics, and network processing benefit from acceleration engines that move data seamlessly among the various system components. CCIX will allow components to access and process data irrespective of where it resides, without the need for complex programming environments.

CCIX will leverage existing server interconnect infrastructure and deliver higher bandwidth, lower latency and cache coherent access to shared memory. This will result in a significant improvement in the usability of accelerators and overall performance and efficiency of data center platforms, lowering the barrier to entry into existing server systems and improving the total cost of ownership (TCO) of acceleration systems.

The test chip, implemented on TSMC’s 7nm process, will be based on the latest Arm DynamIQ technology, CMN-600 coherent on-chip bus and foundation IP. To validate the complete subsystem, Cadence provided key I/O and memory subsystems, which include the CCIX IP solution (controller and PHY), PCI Express 4.0/3.0 (PCIe-4/3) IP solution (controller and PHY), the DDR4 PHY, peripheral IPs such as I2C, SPI and QSPI, as well as associated IP drivers. Cadence verification and implementation tools are being used to build the test chip. The test chip provides connectivity to Xilinx’s 16nm Virtex UltraScale+ FPGAs over CCIX chip-to-chip coherent interconnect protocol.

The test chip will tape-out in early Q1 2018 with silicon availability expected in 2nd half 2018.

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