AUTOMATED FILLING OF FLEXIBLE CRYOGENIC STORAGE BAGS WITH THERAPEUTIC CELLS - An apparatus and processes for aseptically dispensing live mammalian cells into sterile, flexible bags in a non-sterile atmosphere. The method includes the steps of: providing the cells suspended in a liquid; providing a plurality of sterile flexible bags fluidly connected to a main line by a plurality of branch lines of sterile flexible tubing; evacuating air from the flexible bags by applying a vacuum to the open end of the main line; preventing fluid flow through all branch lines except that of one bag to be filled; dispensing a desired volume of cell suspension into the open end of the main line; and introducing sufficient sterile purging gas under pressure into open end of the main line to drive into the bag any of the dispensed volume remaining in the main line or branch line of filled bag. Cells can be cryogenically preserved in the filled bags.

2011-11-24

20110287535

Histone Deacetylase Inhibitors - Histone deacetylase is a metallo-enzyme with zinc at the active site. Compounds having a zinc-binding moiety, such as, for example, a hydroxamic acid group or a carboxylic acid group, can inhibit histone deacetylase. Histone deacetylase can repress gene expression, including expression of genes related to tumor suppression. Accordingly, inhibition of histone deacetylase can provide an alternate route for treating cancer, hematological disorders, e.g., hemoglobinopathies, and genetic related metabolic disorders, e.g., cystic fibrosis and adrenoleukodystrophy.

2011-11-24

20110287536

SIMPLIFIED METHOD FOR PARTIAL GENETIC AND EPIGENETIC REPROGRAMMING OF CELLS - A method of partial, rapid and direct genetic and epigenetic reprogramming of biological cells without returning to the embryonic state can partially reprogram a cell to be treated to specifically modify the biological age of said cell to be treated without causing functional de-differentiation of said cell to be treated, said cell to be treated always remaining as a specialized functional cell that is immunologically autologous to the donor tissue from which said cell to be treated is derived, and for which the phenotype is preserved and/or rejuvenated.

METHOD FOR PRODUCTION OF REPROGRAMMED CELL USING CHROMOSOMALLY UNINTEGRATED VIRUS VECTOR - An objective of the present invention is to provide vectors for conveniently and efficiently producing ES-like cells in which foreign genes are not integrated into the chromosome. The present inventors discovered methods for producing ES-like cells from somatic cells using chromosomally non-integrating viral vectors. Since no foreign gene is integrated into the chromosome of the produced ES-like cells, they are advantageous in tests and research, and immunological rejection and ethical problems can be avoided in disease treatments.

METHOD FOR CONTROLLING PROLIFERATION OF CORD BLOOD HEMATOPOIETIC STEM CELLS AND USE THEREOF - The present invention provides a method for controlling the proliferation and differentiation of cord blood-derived hematopoietic stem cells with excellent safety when proliferating them by culturing. The hematopoietic stem cells are inoculated into a medium containing a sonicated liquid component of cord blood. The proliferation and differentiation of the cord blood hematopoietic stem cells can be inhibited in the presence of the sonicated liquid component of cord blood. On the contrary, the proliferation of cord blood hematopoietic stem cells can be accelerated by inoculating the hematopoietic stem cells into a medium containing a non-sonicated liquid component of cord blood. Thus, according to the present invention, by using serum derived from cord blood, it is possible to regulate the inhibition of the proliferation and differentiation of cord blood hematopoietic stem cells and the acceleration of the proliferation of the same as desired.

2011-11-24

20110287541

ACCORDION BIOREACTOR - Disclosed herein are bioreactors including a first sheet and a second sheet (one or both of which is substantially transparent to light), wherein the second sheet is disposed adjacent to the first sheet, and the first and second sheets are sealed along a first longitudinal edge, a second longitudinal edge, a first horizontal edge, a second horizontal edge, and at least one intermediate horizontal seal between the first horizontal edge and the second horizontal edge, thereby forming at least two chambers for holding fluid in series along a vertical axis, wherein each of the two or more chambers is oriented at an angle relative to the vertical axis, wherein the angle is about 0° to about 90° and at least one of the chambers is oriented at an angle greater than 0°, and wherein there is at least one opening in each of the first horizontal edge, the second horizontal edge, and intermediate horizontal seal(s); a support structure comprising at least one horizontal support, wherein the horizontal support is located at or near the position of the intermediate horizontal seal; a reservoir below the second horizontal edge of the first and second sheets; and a means for pumping fluid from the reservoir to the first horizontal edge of the first and second sheets. Also disclosed are methods of culturing cells including circulating a suspension of cells in a disclosed bioreactor. In some examples, the cells include microalgae, macroalgae, bacteria, fungi, insect cells, plant cells, animal cells (such as mammalian cells), or plant or animals tissue or organs. In particular examples, the method includes exposing the culture in the bioreactor to a light source (such as sunlight or an artificial light source).

Photobioreactor Systems Positioned on Bodies of Water - Certain embodiments and aspects of the present invention relate to a photobioreactor including photobioreactor units through which a liquid medium stream and a gas stream flow. The photobioreactor units are floated on a body of water such as a pond or a lake. The liquid medium comprises at least one species of phototrophic organism therein. Certain methods of using the photobioreactor system as part of fuel generation system and/or a gas-treatment process or system at least partially remove certain undesirable pollutants from a gas stream. In certain embodiments, the photobioreactor units are formed of flexible, deformable material and are configured to provide a substantially constant thickness of liquid medium. In certain embodiments, a barrier between the photobioreactor unit and the body of water upon which the unit is floated facilitates thermal communication between the liquid medium and the body of water.

2011-11-24

20110287545

Targeted genomic modification with partially single-stranded donor molecules - Disclosed herein are donor molecules comprising single-stranded complementary regions flanking one or more sequences of interest. The donor molecules and/or compositions comprising these molecules can be used in methods for targeted integration of an exogenous sequence into a specified region of interest in the genome of a cell.

2011-11-24

20110287546

Automated intracellular manipulation and transfection - A method and apparatus whereby prokaryotic, eukaryotic and/or mammalian cells may have genetic agents inserted or removed or transferred in an automated and semi-quantitative fashion. The functional unit of the invention is composed of two rectangular plates: a contact plate with circular holes and a carefully aligned base plate with a pleurality of rods, which protrude through the center of the holes of the contact plate. The edges of the two plates are sealed lengthwise to create a space whereby fluid may flow through the proximal and distal openings to induce a negative pressure, vacuum suction, venturi effect at each hole of the contact plate. The rods and base plate may be coated with an electronically magnetizable surface which may attract and hold or repulse and release any magnetically responsive genetic agents.

2011-11-24

20110287547

NUCLEIC ACID DELIVERY COMPOSITIONS AND METHODS - Complexes comprising a cationic polymer, a nucleic acid and a metal ion are provided. In some embodiments, a complex may be used as a means for delivering nucleic acid to a cell. In some embodiments, a complex may be used as part of a gene therapy. Methods of making a complex comprising a cationic polymer, a nucleic acid, and a metal ion are also described. Methods of condensing a polyplex comprising a cationic polymer and a nucleic acid are also provided.

2011-11-24

20110287548

THERMAL DISTRIBUTION DISPLAY AND METHOD FOR CONFIRMING THERMAL DISTRIBUTION - Provided is a thermal distribution display including, on a support, a thermal distribution display layer which includes an organic polymer composite containing an electron-donating dye precursor and a polymer; at least an electron-accepting compound A represented by the following formula (1) and an electron-accepting compound B represented by the following formula (2); and a binder, wherein the content ratio (A:B) is from 95:5 to 50:50 on a mass basis, and the content of the electron-accepting compound A in the total amount of electron-accepting compounds is 40% by mass or greater:

METAL SALT HYDROGEN SULFIDE SENSOR - A sensor made from a metal salt film, formed on a set of monitoring electrodes, by evaporation of a metal salt aqueous solution disposed on the electrodes, is used for detecting a weak acid. Low concentrations of the weak acid, such as ten ppm, are indicated as the conductivity of the film changes by several orders of magnitude, as a result of reaction of the weak acid with the metal salt, as the metal salt converts to a metal reaction product upon exposure to the weak acid.

BREACH OR CONTAMINATION INDICATING ARTICLE HAVING MICROCAPSULES - Provided among other things are breach or contamination indicating elastomeric articles for indicating a breach or contamination by a selected chemical or group of chemicals, the article having an exterior and interior and comprising: (1) an indicating layer that comprises (a) a carrier polymer, and (b) a plurality of microcapsules wherein each microcapsule comprises a dye and a shell, wherein the plurality of microcapsules is dispersed in the carrier polymer and the polymer shell releases the dye in the presence of the selected chemical(s); and (2) an elastomeric layer selected to resist permeation by the selected chemical(s), which resistant layer is to the interior or exterior side of the indicating layer.

2011-11-24

20110287554

ATMOSPHERIC PRESSURE ION SOURCE PERFORMANCE ENHANCEMENT - Electrospray ionization sources interfaced to mass spectrometers have become widely used tools in analytical applications. Processes occurring in Electrospray (ES) ionization generally include the addition or removal of a charged species such as H+ or other cation to effect ionization of a sample species Electrospray includes ionization processes that occur in the liquid and gas phase and in both phases ionization processes require a source or sink for such charged species. Electrolyte species, that aid in oxidation or reduction reactions occurring in Electrospray ionization, are added to sample solutions in many analytical applications to increase the ion signal amplitude generated in Electrospray and detected by a mass spectrometer (MS). Electrolyte species that may be required to enhance an upstream sample preparation or separation process may be less compatible with the downstream ES processes and cause reduction in MS signal. New Electrolytes have been found that increase positive and negative polarity analyte ion signal measured in ESMS analysis when compared with analyte ESMS signal achieved using more conventional electrolytes. The new electrolyte species increase ES MS signal when added directly to a sample solution or when added to a second solution flow in an Electrospray membrane probe. It has also been found that running the ES membrane probe with specific Electrolytes in the second solution of the ES membrane probe have been found to enhance ESMS signal compared to using the same electrolytes directly in the sample solution being Electrosprayed. The new electrolytes can be added to a reagent ion source configured in a combination Atmospheric pressure ion source to improve ionization efficiency.

2011-11-24

20110287555

REUSABLE SHEATHS FOR SEPARATING MAGNETIC PARTICLES - An assembly that utilizes reusable sheaths for covering magnetic rods for collecting particles in an inverse magnetic particle process. The magnetic rod is removed from the reusable sheath to release particles at the same or a different location. The reusable sheaths can be assembled in a cylindrical plate, which can be rotated to position a clean sheath for each step of the inverse magnetic particle process. When not being used for particle separation, the sheaths can be washed of potentially contaminating solution in wash receptacles.

SINGLE QUANTUM-DOT BASED APTAMERIC NANOSENSORS - A signal-off-quantum-dot-based sensor for detecting the presence of a target molecule comprising: an aptamer probe having a nucleotide sequence which specifically interacts with the target molecule by sequence-dependent interaction, wherein the aptamer probe is sandwiched between (a) an oligonucleotide which is immobilized on the surface of a quantum dot (QD), and (b) a fluorophore-labeled oligonucleotide, wherein when the sensor is excited by an energy source: (i) in the absence of specific interaction between the target molecule and the aptamer probe, a baseline signal is emitted, and (ii) in the presence of specific interaction between the target molecule and the aptamer probe, a detection signal is emitted, wherein the baseline signal is greater than the detection signal, whereby the presence of the target molecule is detected.

METHOD OF CHARACTERIZING GLYCANS ATTACHED TO GLYCOPROTEINS - A method of characterizing glycans attached to glycoproteins is disclosed herein. The method comprises a first step of immobilizing the glycoproteins on colloidal particles forming glycoprotein/colloidal particles. The glycans on the glycoproteins may then be characterized, for example the composition and/or structure of glycans may be characterized or the glycans attached to proteins may be identified. Characterization may be accomplished by either binding the glycoprotein/colloidal particles with one or more binding agents and assessing the aggregation of the glycoprotein/colloidal particles or by cleaving glycans from the glycoprotein/colloidal particles with a cleaving agent and analyzing the glycans.

2011-11-24

20110287560

IN-SITU MELT AND REFLOW PROCESS FOR FORMING FLIP-CHIP INTERCONNECTIONS AND SYSTEMS THEREOF - A method for fabricating a flip-chip semiconductor package. The method comprises processing a semiconductor device, for example a semiconductor chip and processing a device carrier, for example a substrate. The semiconductor device comprises bump structures formed on a surface thereof. The substrate comprises bond pads formed on a surface thereof. Processing of the semiconductor chip results in heating of the semiconductor chip to a chip process temperature. The chip process temperature melts solder portions on the bump structures Processing of the substrate results in heating of the substrate to a substrate process temperature. The method comprises spatially aligning the semiconductor chip in relation to the substrate to correspondingly align the bump structures in relation to the bump pads. The semiconductor chip is then displaced towards the substrate for abutting the bump structures of the semiconductor chip with the bond pads of the substrate to thereby form bonds therebetween. A system for performing the above method is also disclosed.

2011-11-24

20110287561

THIN FILM TRANSISTOR ARRAY SUBSTRATE WITH IMPROVED TEST TERMINALS - A thin film transistor array substrate comprises thin film transistors and pixel electrodes formed at respective pixels that are defined by gate lines and data lines that orthogonally intersect each other. The thin film transistor array substrate further comprises a plurality of gate pad units that group a plurality of gate pads extended from the gate lines, and a plurality of data pad units that groups a plurality of data pads extended from the data lines. The thin film transistor array substrate further includes a plurality of gate test terminals connected to the gate pad units and beside at least one side of the respective gate pad units, and a plurality of data test terminals connected to the data pad units and located beside at least one side of the respective data pad units.

METHOD OF MAKING A SEMICONDUCTOR CHIP ASSEMBLY WITH A POST/DIELECTRIC/POST HEAT SPREADER - A method of making a semiconductor chip assembly includes providing first and second posts, first and second adhesives, first and second conductive layers and a dielectric base, wherein the first post extends from the dielectric base in a first vertical direction into a first opening in the first adhesive and is aligned with a first aperture in the first conductive layer, the second post extends from the dielectric base in a second vertical direction into a second opening in the second adhesive and is aligned with a second aperture in the second conductive layer and the dielectric base is sandwiched between and extends laterally from the posts, then flowing the first adhesive in the first vertical direction and the second adhesive in the second vertical direction, solidifying the adhesives, then providing a conductive trace that includes a pad, a terminal and selected portions of the conductive layers, wherein the pad extends beyond the dielectric base in the first vertical direction and the terminal extends beyond the dielectric base in the second vertical direction, providing a heat spreader that includes the posts and the dielectric base, then mounting a semiconductor device on the first post, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.

2011-11-24

20110287564

LIGHT EMITTING DEVICE HAVING LIGHT EXTRACTION STRUCTURE - A light emitting device having a light extraction structure, which is capable of achieving an enhancement in light extraction efficiency and reliability, and a method for manufacturing the same. The light emitting device includes a semiconductor layer having a multi-layered structure including a light emission layer; and a light extraction structure formed on the semiconductor layer in a pattern having unit structures. Further, the wall of each of the unit structures is sloped at an angle of −45° to +45° from a virtual vertical line being parallel to a main light emitting direction of the light emitting device.

METHOD FOR FABRICATING AN ELECTROLUMINESCENCE DEVICE - A nanocrystal electroluminescence device comprising a polymer hole transport layer, a nanocrystal light-emitting layer and an organic electron transport layer wherein the nanocrystal light-emitting layer is independently and separately formed between the polymer hole transport layer and the organic electron transport layer. According to the nanocrystal electroluminescence device, since the hole transport layer, the nanocrystal light-emitting layer and the electron transport layer are completely separated from one another, the electroluminescence device provides a pure nanocrystal luminescence spectrum having limited luminescence from other organic layers and substantially no influence by operational conditions, such as voltage. Further included is a method for fabricating the nanocrystal electroluminescence device.

METHOD OF MANUFACTURING THIN FILM SOLAR CELL - A method of manufacturing a thin film solar cell includes a bonding step of bonding a bus bar on a back face electrode layer of a solar cell string including a transparent conductive film, a photoelectric conversion layer and the back face electrode layer formed on a light-transmitting insulating substrate. The bonding step includes a first step of bonding conductive tape on the bonding surface of the bus bar that is to be bonded to the back face electrode layer, and a second step of bonding the bus bar to which the conductive tape has been bonded to the back face electrode layer of the solar cell string.

2011-11-24

20110287569

Solid-state imaging device, method of producing the same, and camera - To provide a solid-state imaging device able to improve light transmittance of a transparent insulation film in a light incident side of a substrate, suppress the dark current, and prevent a quantum efficiently loss, wherein a pixel circuit is formed in a first surface of the substrate and light is received from a second surface, and having: a light receiving unit formed in the substrate and for generating a signal charge corresponding to an amount of incidence light and storing it; a transparent first insulation film formed on the second surface; and a transparent second insulation film formed on the first insulation film and for retaining a charge having the same polarity as the signal charge in an interface of the first insulation film or in inside, thicknesses of the first and second insulation film being determined to obtain a transmittance higher than when using only the first insulation film.

2011-11-24

20110287570

LASER PROCESSING APPARATUS, LASER PROCESSING METHOD, AND MANUFACTURING METHOD OF PHOTOVOLTAIC DEVICE - To provide a conveying unit that holds a workpiece and conveys the workpiece at a constant rate in one direction, a laser oscillator that emits a pulsed laser beam, a splitter that splits a pulsed laser beam into a pattern having a predetermined geometric pitch, a first deflector that scans the split pulsed laser beam in the other direction substantially orthogonal to the one direction, a second deflector that adjusts and deflects the split pulsed laser beam deflected by the first deflector on the surface to be processed in the one direction so as to scan the resultant pulsed laser beam onto the surface to be processed at a constant rate equal to a rate at which the workpiece is conveyed, and a condenser that condenses the split pulsed laser beam deflected by the second deflector onto the surface to be processed.

2011-11-24

20110287571

METHOD OF FABRICATING A BACK-ILLUMINATED IMAGE SENSOR - A method of fabricating a back-illuminated image sensor that includes the steps of providing a first substrate of a semiconductor layer, in particular a silicon layer, forming electronic device structures over the semiconductor layer and, only then, doping the semiconductor layer. By doing so, improved dopant profiles and electrical properties of photodiodes can be achieved such that the final product, namely an image sensor, has a better quality.

2011-11-24

20110287572

SEMICONDUCTOR DEVICE FABRICATION METHODS - Methods for fabricating semiconductor devices, such as complementary metal-oxide-semiconductor (CMOS) imagers, include fabricating transistors and other low-elevation features on an active surface of a fabrication substrate, and fabricating contact plugs, conductive lines, external contacts, and other higher-elevation features on the back side of the fabrication substrate. Semiconductor devices with transistors on the active surface and contact plugs that extend through the substrate are also disclosed, as are electronic devices including such semiconductor devices.

2011-11-24

20110287573

ATYPICAL KESTERITE COMPOSITIONS - This invention relates to processes for making kesterite compositions with atypical Cu:Zn:Sn:S ratios and/or kesterite compositions with unusually small coherent domain sizes. This invention also relates to these kesterite compositions and their use in preparing CZTS films.

2011-11-24

20110287574

BULK SODIUM SPECIES TREATMENT OF THIN FILM PHOTOVOLTAIC CELL AND MANUFACTURING METHOD - A method for forming a thin film photovoltaic device is provided. The method includes providing a transparent substrate comprising a surface region. A first electrode layer is formed overlying the surface region. A chalcopyrite material is formed overlying the first electrode layer. In a specific embodiment, the chalcopyrite material comprises a copper poor copper indium disulfide region. The copper poor copper indium disulfide region having an atomic ratio of Cu:In of about 0.95 and less. The method includes compensating the copper poor copper indium disulfide region using a sodium species to cause the chalcopyrite material to change from an n-type characteristic to a p-type characteristic. The method includes forming a window layer overlying the chalcopyrite material and forming a second electrode layer overlying the window layer.

2011-11-24

20110287575

SULFIDE SPECIES TREATMENT OF THIN FILM PHOTOVOLTAIC CELL AND MANUFACTURING METHOD - A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region, forming a first electrode layer overlying the surface region, forming a copper layer overlying the first electrode layer and forming an indium layer overlying the copper layer to form a multi-layered structure. The multi-layered structure is subjected to a thermal treatment process in an environment containing a sulfur bearing species to forming a copper indium disulfide material. The copper indium disulfide material comprising a copper-to-indium atomic ratio ranging from about 1.2:1 to about 2:1 and a thickness of substantially copper sulfide material having a copper sulfide surface region. The thickness of the copper sulfide material is selectively removed to expose a surface region having a copper poor surface comprising a copper to indium atomic ratio of less than about 0.95:1. The method subjects the copper poor surface to a sulfide species to convert the copper poor surface from an n-type semiconductor characteristic to a p-type semiconductor characteristic. A window layer is formed overlying the copper indium disulfide material.

2011-11-24

20110287576

BULK COPPER SPECIES TREATMENT OF THIN FILM PHOTOVOLTAIC CELL AND MANUFACTURING METHOD - A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region. A first electrode layer is formed overlying the surface region. A copper layer is formed overlying the first electrode layer and an indium layer is formed overlying the copper layer to form a multi-layered structure. The method subject at least the multi-layered structure to a thermal treatment process in an environment containing a sulfur bearing species to form a bulk copper indium disulfide material. The bulk copper indium disulfide material includes one or more portions of copper indium disulfide material characterized by a copper-to-indium atomic ratio of less than about 0.95:1 and a copper poor surface comprising a copper to indium atomic ratio of less than about 0.95:1. The method subjects the copper poor surface and one or more portions of the bulk copper indium disulfide material to copper species to convert the copper poor surface from an n-type characteristic to a p-type characteristic and to convert any of the one or more portions of the bulk copper indium disulfide material having the copper-to-indium atomic ratio of less than about 0.95:1 from a p-type characteristic to an n-type characteristic. A window layer is formed overlying the copper indium disulfide material.

2011-11-24

20110287577

METHOD OF CLEANING AND FORMING A NEGATIVELY CHARGED PASSIVATION LAYER OVER A DOPED REGION - The present invention generally provides a method of forming a high efficiency solar cell device by preparing a surface and/or forming at least a part of a high quality passivation layer on a silicon containing substrate. Embodiments of the present invention may be especially useful for preparing a surface of a p-type doped region formed on a silicon substrate so that a high quality passivation layer can be formed thereon. In one embodiment, the methods include exposing a surface of the solar cell substrate to a plasma to clean and modify the physical, chemical and/or electrical characteristics of the surface.

2011-11-24

20110287578

Method of fabricating bifacial tandem solar cells - A method of fabricating on a semiconductor substrate bifacial tandem solar cells with semiconductor subcells having a lower bandgap than the substrate bandgap on one side of the substrate and with subcells having a higher bandgap than the substrate on the other including, first, growing a lower bandgap subcell on one substrate side that uses only the same periodic table group V material in the dislocation-reducing grading layers and bottom subcells as is present in the substrate and after the initial growth is complete and then flipping the substrate and growing the higher bandgap subcells on the opposite substrate side which can be of different group V material.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object of an embodiment of the present invention is to provide a semiconductor device including a normally-off oxide semiconductor element whose characteristic variation is small in the long term. A cation containing one or more elements selected from oxygen and halogen is added to an oxide semiconductor layer, thereby suppressing elimination of oxygen, reducing hydrogen, or suppressing movement of hydrogen. Accordingly, carriers in the oxide semiconductor can be reduced and the number of the carriers can be kept constant in the long term. As a result, the semiconductor device including the normally-off oxide semiconductor element whose characteristic variation is small in the long term can be provided.

2011-11-24

20110287581

SEMICONDUCTOR WORKPIECE CARRIERS AND METHODS FOR PROCESSING SEMICONDUCTOR WORKPIECES - Semiconductor workpiece carriers and methods for processing semiconductor workpieces are disclosed herein. In one embodiment, a semiconductor workpiece carrier assembly includes (a) a support structure having an opening sized to receive at least a portion of a semiconductor workpiece, and (b) a replaceable carrier positioned at the opening. The replaceable carrier includes a base and an adhesive layer on the base. The base has a surface, and the adhesive layer covers only a section of the surface of the base. The adhesive layer releasably attaches the replaceable carrier to the support structure.

2011-11-24

20110287582

METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method of funning a semiconductor device includes filling a gap of a semiconductor chip stack while carrying out a first heating process which heats the semiconductor chip stack from upper and lower portions of the semiconductor chip stack.

2011-11-24

20110287583

CONVEX DIE ATTACHMENT METHOD - A method for assembling a microelectronic device is provided comprising the step of adhering a die to a substrate using a convex die attachment process. The convex die attachment process generally comprises a) providing a die having an underfill material thereon, b) picking up and inverting the die, c) heating the underfill until it liquefies at least slightly and forms a convex surface, and d) placing the die on a substrate.

2011-11-24

20110287584

SEMICONDUCTOR PACKAGE HAVING SIDE WALLS AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes a semiconductor chip having an upper surface, side surfaces connected with the upper surface, and bonding pads formed on the upper surface. A first insulation layer pattern is formed to cover the upper surface and the side surfaces of the semiconductor chip and expose the bonding pads. Re-distribution lines are placed on the first insulation layer pattern and include first re-distribution line parts and second re-distribution line parts. The first re-distribution line parts have an end connected with the bonding pads and correspond to the upper surface of the semiconductor chip and the second re-distribution line parts extend from the first re-distribution line parts beyond the side surfaces of the semiconductor chip. A second insulation layer pattern is formed over the semiconductor chip and exposes portions of the first re-distribution line parts and the second re-distribution line parts.

2011-11-24

20110287585

SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR ELEMENTS MOUNTED ON BASE PLATE - A method of manufacturing a semiconductor device and a semiconductor device including a first semiconductor element mounted on a first surface of a base plate, wherein solder balls are formed on a second opposite surface of the base plate—such that the second opposite surface includes an area without solder balls. At least one second semiconductor element is mounted to the base plate at the area of the second surface without solder balls. The at least one semiconductor element may be mounted to the base plate using low molecular adhesive, or in the alternative, high temperature solder.

2011-11-24

20110287586

MEMS Switch Capping and Passivation Method - A MEMS switch with a platinum-series contact is capped through a process that also passivates the contact by controlling, over time, the amount of oxygen in the environment, pressures and temperatures. Some embodiments passivate a contact in an oxygenated atmosphere at a first temperature and pressure, before hermetically sealing the cap at a higher temperature and pressure. Some embodiments hermetically seal the cap at a temperature below which passivating dioxides will form, thus trapping oxygen within the volume defined by the cap, and later passivate the contact with the trapped oxygen at a higher temperature.

2011-11-24

20110287587

METHOD FOR FABRICATING HEAT DISSIPATION PACKAGE STRUCTURE - A heat dissipation package structure and method for fabricating the same are disclosed, which includes mounting and electrically connecting a semiconductor chip to a chip carrier through its active surface; mounting a heat dissipation member having a heat dissipation section and a supporting section on the chip carrier such that the semiconductor chip can be received in the space formed by the heat dissipation section and the supporting section, wherein the heat dissipation section has an opening formed corresponding to the semiconductor chip; forming an encapsulant to encapsulate the semiconductor chip, and the heat dissipation member; and thinning the encapsulant to remove the encapsulant formed on the semiconductor chip to expose inactive surface of the semiconductor chip and the top surface of the heat dissipation section from the encapsulant. Therefore, the heat dissipation package structure is fabricated through simplified fabrication steps at low cost, and also the problem that the chip is easily damaged in a package molding process of the prior art is overcome.

2011-11-24

20110287588

METHOD FOR MANUFACTURING HEAT-DISSIPATING SEMICONDUCTOR PACKAGE STRUCTURE - A heat-dissipating semiconductor package structure and a method for manufacturing the same is disclosed. The method includes: disposing on and electrically connecting to a chip carrier at least a semiconductor chip and a package unit; disposing on the top surface of the package unit a heat-dissipating element having a flat portion and a supporting portion via the flat portion; receiving the package unit and semiconductor chip in a receiving space formed by the flat portion and supporting portion of the heat-dissipating element; and forming on the chip carrier encapsulant for encapsulating the package unit, semiconductor chip, and heat-dissipating element. The heat-dissipating element dissipates heat generated by the package unit, provides EMI shielding, prevents delamination between the package unit and the encapsulant, decreases thermal resistance, and prevents cracking.

2011-11-24

20110287589

METHOD FOR MANUFACTURING ANTENNA AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present invention provides an antenna with low resistance and a semiconductor device having an antenna whose communication distance is improved. A fluid containing conductive particles is applied over an object. After curing the fluid containing the conductive particles, the fluid is irradiated with a laser to form an antenna. As a method for applying the fluid containing the conductive particles, screen printing, spin coating, dipping, or a droplet discharging method is used. Further, a solid laser having a wavelength of 1 nm or more and 380 nm or less is used as the laser.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device including an oxide semiconductor, which has stable electrical characteristics and high reliability. In a manufacturing process of a bottom-gate transistor including an oxide semiconductor layer, heat treatment in an atmosphere containing oxygen and heat treatment in vacuum are sequentially performed for dehydration or dehydrogenation of the oxide semiconductor layer. In addition, irradiation with light having a short wavelength is performed concurrently with the heat treatment, whereby elimination of hydrogen, OH, or the like is promoted. A transistor including an oxide semiconductor layer on which dehydration or dehydrogenation treatment is performed through such heat treatment has improved stability, so that variation in electrical characteristics of the transistor due to light irradiation or a bias-temperature stress (BT) test is suppressed.

2011-11-24

20110287592

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is provided, which comprises at least a steps of forming a gate insulating film over a substrate, a step of forming a microcrystalline semiconductor film over the gate insulating film, and a step of forming an amorphous semiconductor film over the microcrystalline semiconductor film. The microcrystalline semiconductor film is formed by introducing a silicon hydride gas or a silicon halide gas when a surface of the gate insulating film is subjected to hydrogen plasma to generate a crystalline nucleus over the surface of the gate insulating film, and by increasing a flow rate of the silicon hydride gas or the silicon halide gas.

2011-11-24

20110287593

METHOD FOR FORMING SEMICONDUCTOR FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to provide a method for forming an oxide semiconductor film with little variation in electrical characteristics. Another object is to provide a method for manufacturing a semiconductor device including an oxide semiconductor film with little variation in electrical characteristics. To reduce the amount of light scattered by a substrate stage or the amount of the scattered light which travels to enter a light-transmitting oxide semiconductor layer when the light-transmitting oxide semiconductor layer is patterned, a layer having a function of preventing light transmission may be provided in a lower layer than a photoresist layer so that light does not reach the substrate stage. In addition, a semiconductor device may be manufactured using the oxide semiconductor layer formed by the above patterning method.

2011-11-24

20110287594

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A polysilicon film to be a resistor element is formed on a resistor element formation region of a semiconductor substrate while a polysilicon gate and high concentration impurity regions are formed on a transistor formation region. Thereafter, an insulating film is formed on the entire surface of the semiconductor substrate. Then, a photoresist film is formed to cover the transistor formation region, and a conductive impurity is ion-implanted into the polysilicon film. Next, the photoresist film is removed by asking.

2011-11-24

20110287595

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

2011-11-24

20110287596

SYSTEM AND METHOD FOR PROVIDING LOW VOLTAGE HIGH DENSITY MULTI-BIT STORAGE FLASH MEMORY - A system and method is disclosed for providing a low voltage high density multi-bit storage flash memory. A dual bit memory cell of the invention comprises a substrate having a common source, a first drain and first channel, and a second drain and a second channel. A common control gate is located above the source. A first floating gate and a second floating gate are located on opposite sides of the control gate. Each floating gate is formed with a sharp tip adjacent to the control gate and an upper curved surface that follows a contour of the surface of the control gate. The sharp tips of the floating gates efficiently discharge electrons into the control gate when the memory cell is erased. The curved surfaces increase capacitor coupling between the control gate and the floating gates.

2011-11-24

20110287597

Nonvolatile semicondutor memory device and manufacturing method thereof - A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

2011-11-24

20110287598

METHOD OF MANUFACTURING SUPER-JUNCTION SEMICONDUCTOR DEVICE - A method of manufacturing a super-junction semiconductor device prevents mutual positional deviation between the region of the first conductivity type in the alternating conductivity type layer and the second trench for forming a trench gate from resulting. The method includes growing an alternating conductivity type layer epitaxially on a heavily doped n-type semiconductor substrate, the alternating conductivity type layer including n-type and p-type semiconductor regions arranged alternately and repeated such that n-type and p-type regions are adjoining each other, and arranged to extend perpendicular to the substrate's major surface. The method includes forming a first trench having a predetermined depth in the surface portion of n-type semiconductor region; forming an n-type thin layer on the inner surface of the first trench; and burying gate electrode in the space surrounded by the n-type thin layer with a gate insulator film interposed between a gate electrode and the n-type thin layer

2011-11-24

20110287599

Method of Fabricating a Transistor - A method of fabricating a saddle-fin transistor may include: forming a buffer oxide film and a hard mask oxide film over a semiconductor substrate; etching the buffer oxide film, the hard mask oxide film and the semiconductor substrate corresponding to a mask pattern to form a trench corresponding to a gate electrode and a fin region; oxidizing the exposed semiconductor substrate in the trench to form a gate oxide film; depositing a gate lower electrode in the trench; and depositing a gate upper electrode over the gate lower electrode to fill the trench.

2011-11-24

20110287600

Selective Etching in the Formation of Epitaxy Regions in MOS Devices - A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. After the step of performing the selective epitaxial growth, a selective etch-back is performed to the epitaxy region. The selective etch-back is performed using process gases comprising a first gas for growing the semiconductor material, and a second gas for etching the epitaxy region.

2011-11-24

20110287601

METHODS OF FORMING A DIELECTRIC CONTAINING DYSPROSIUM DOPED HAFNIUM OXIDE - The use of a monolayer or partial monolayer sequencing process, such as atomic layer deposition, to form a dielectric layer of hafnium oxide doped with dysprosium and a method of fabricating such a combination produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure can include depositing hafnium oxide onto a substrate surface using precursor chemicals, followed by depositing dysprosium oxide onto the substrate using precursor chemicals, and repeating to form a thin laminate structure. A dielectric layer of dysprosium doped hafnium oxide may be used as the gate insulator of a MOSFET, as a capacitor dielectric in a DRAM, as a tunnel gate insulator in flash memories, or as a dielectric in NROM devices, because the high dielectric constant (high-k) of the film provides the functionality of a thinner silicon dioxide film, and because the reduced leakage current of the dielectric layer when the percentage of dysprosium doping is optimized improves memory function.

2011-11-24

20110287602

PHASE CHANGE MEMORY DEVICE HAVING A BENT HEATER AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device includes heaters which are formed in their respective memory cells and vertically positioned stack patterns having phase change layers and top electrodes which are formed to come into contact with the heaters. The heaters have horizontal cross-sectional bent shapes which can have any number of shapes such as a shape similar to that of a boomerang. The horizontal cross-sectional bent shapes of the to heaters are for minimizing the contact area between the heaters and the phase change layer so that programming currents can be reduced or minimized.

2011-11-24

20110287603

METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE - First and second supported portions each made of silicon carbide and a supporting portion made of silicon carbide are arranged such that the first and second supported portions and the supporting portion face each other and a gap is provided between the first and second supported portions. By sublimating and recrystallizing silicon carbide of the supporting portion, the supporting portion is connected to each of the first and second single-crystal substrates. On this occasion, a through hole is formed in the supporting portion so as to be connected to the gap. Accordingly, a path is formed which allows a fluid to pass through the gap and the through hole. By closing this path, the fluid can be prevented from being leaked through the silicon carbide substrate.

2011-11-24

20110287604

METHODS OF FORMING SEMICONDUCTOR STRUCTURES COMPRISING DIRECT BONDING OF SUBSTRATES - The invention relates to a method of initiating molecular bonding, comprising bringing one face of a first wafer to face one face of a second wafer and initiating a point of contact between the two facing faces. The point of contact is initiated by application to one of the two wafers, for example using a bearing element of a tool, of a mechanical pressure in the range 0,1 MPa to 33.3 MPa.

2011-11-24

20110287605

METHOD FOR MANUFACTURING SOI SUBSTRATE - Forming an insulating film on a surface of the single crystal semiconductor substrate, forming a fragile region in the single crystal semiconductor substrate by irradiating the single crystal semiconductor substrate with an ion beam through the insulating film, forming a bonding layer over the insulating film, bonding a supporting substrate to the single crystal semiconductor substrate by interposing the bonding layer between the supporting substrate and the single crystal semiconductor substrate, dividing the single crystal semiconductor substrate at the fragile region to separate the single crystal semiconductor substrate into a single crystal semiconductor layer attached to the supporting substrate, performing first dry etching treatment on a part of the fragile region remaining on the single crystal semiconductor layer, performing second dry etching treatment on a surface of the single crystal semiconductor layer subjected to the first etching treatment, and irradiating the single crystal semiconductor layer with laser light.

2011-11-24

20110287606

METHOD FOR FABRICATING CHIP ELEMENTS PROVIDED WITH WIRE INSERTION GROOVES - The invention relates to a method for fabricating chip elements provided with a groove from devices formed on a wafer. The method comprises the steps consisting in, depositing a sacrificial film on the wafer so as to leave a central part of each device exposed and to cover an edge of the device at the level of which the groove is to be formed; applying a mold on the sacrificial film; injecting a hardenable material into the mold; hardening the hardenable material; dicing the wafer between the devices; and eliminating the sacrificial film.

2011-11-24

20110287607

METHOD AND APPARATUS FOR IMPROVED WAFER SINGULATION - Laser singulation of electronic devices from semiconductor substrates including wafers is performed using up to 3 lasers from 2 wavelength ranges. Using up to 3 lasers from 2 wavelength ranges permits laser singulation of wafers held by die attach film while avoiding problems caused by single-wavelength dicing. In particular, using up to 3 lasers from 2 wavelength ranges permits efficient dicing of semiconductor wafers while avoiding debris and thermal problems associated with laser processing die attach tape.

WAFER PROCESSING METHOD - A processing method for a wafer having a device area where a plurality of devices are formed on the front side of the wafer and a peripheral marginal area surrounding the device area. The processing method includes a reinforcing plate forming step of applying a heat-resistant bond to the front side of the wafer and solidifying the heat-resistant bond to thereby form a reinforcing plate from only the heat-resistant bond, a back grinding step of holding the reinforcing plate on a chuck table and grinding the back side of the wafer in the device area to thereby form a circular recess in the device area and leave an annular reinforcing portion in the peripheral marginal area, a through electrode forming step of forming a through electrode connected to an electrode of each device formed on the front side of the wafer, from the back side of the wafer fixed to the reinforcing plate, and a reinforcing plate removing step of supplying a solvent for dissolving the heat-resistant bond to the reinforcing plate, thereby removing the reinforcing plate.

2011-11-24

20110287610

Selenium/Group 3A ink and methods of making and using same - A selenium/Group 3a ink, comprising (a) a selenium/Group 3a complex which comprises a combination of, as initial components: a selenium component comprising selenium; a carboxylic acid component having a formula R—COOH, wherein R is selected from a C

2011-11-24

20110287611

Reducing Variation by Using Combination Epitaxy Growth - A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate in a wafer; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. The step of performing the selective epitaxial growth includes performing a first growth stage with a first growth-to-etching (E/G) ratio of process gases used in the first growth stage; and performing a second growth stage with a second E/G ratio of process gases used in the second growth stage different from the first E/G ratio.

MANUFACTURING METHOD OF SUPERJUNCTION STRUCTURE - A manufacturing method of superjunction structure is disclosed. After the growth of an epitaxial layer on a substrate, deep trenches are etched in the epitaxial layer. A mixture of silicon source gas, hydrogen gas, halide gas and doping gas is used for trench tilling by means of epitaxial growth. The epitaxial growth rate on trench sidewalls near the bottom of the trench is set to be higher than that near the top of the trench by adjusting the flow rates of the silicon source gas and the halide gas and other parameters. By changing the flow rate of the doping gas at different stages of the epitaxial filling process, the trenches can be filled with epitaxial layers of different doping concentrations, with higher doping concentration near the bottom and lower doping concentration near the top.

2011-11-24

20110287614

Group 6a/Group 3a ink and methods of making and using same - A selenium/Group 3a ink, comprising (a) a selenium/Group 3a complex which comprises a combination of, as initial components: a selenium component comprising selenium; an organic chalcogenide component having a formula selected from RZ—Z′R′ and R

2011-11-24

20110287615

HIGH-DENSITY NONVOLATILE MEMORY AND METHODS OF MAKING THE SAME - Nonvolatile memory cells and methods of forming the same are provided, the methods including forming a first conductor at a first height above a substrate; forming a first pillar-shaped semiconductor element above the first conductor, wherein the first pillar-shaped semiconductor element comprises a first heavily doped layer of a first conductivity type, a second lightly doped layer above and in contact with the first heavily doped layer, and a third heavily doped layer of a second conductivity type above and in contact with the second lightly doped layer, the second conductivity type opposite the first conductivity type; forming a first dielectric antifuse above the third heavily doped layer of the first pillar-shaped semiconductor element; and forming a second conductor above the first dielectric antifuse.

2011-11-24

20110287616

Bottom anode schottky diode structure and method - This invention discloses a bottom-anode Schottky (BAS) diode that includes an anode electrode disposed on a bottom surface of a semiconductor substrate. The bottom-anode Schottky diode further includes a sinker dopant region disposed at a depth in the semiconductor substrate extending substantially to the anode electrode disposed on the bottom surface of the semiconductor and the sinker dopant region covered by a buried Schottky barrier metal functioning as a Schottky anode. The BAS diode further includes a lateral cathode region extended laterally from a cathode electrode near a top surface of the semiconductor substrate opposite the Schottky barrier metal wherein the lateral cathode region doped with an opposite dopant from the sinker dopant region and interfacing the sinker dopant region whereby a current path is formed from the cathode electrode to the anode electrode through the lateral cathode region and the sinker dopant region in applying a forward bias voltage and the sinker dopant region depleting the cathode region in applying a reverse bias voltage for blocking a leakage current.

2011-11-24

20110287617

METHOD OF MANUFACTURING SUPER-JUNCTION SEMICONDUCTOR DEVICE - A method of manufacturing a super-junction semiconductor device facilitates suppressing the shape change caused in the alignment mark in the upper epitaxial layer transferred from the alignment mark in the lower epitaxial layer to be small enough to detect the transferred alignment mark with a few additional steps, even if the epitaxial layer growth rate is high. Alignment mark groups, each formed of trenches including parallel linear planar patterns and used in any of the multiple epitaxial layer growth cycles, are formed collectively on a scribe line between semiconductor chip sections; and the mesa region width between the trenches in each alignment mark group indicated by the distance between the single-headed arrows, facing opposite to each other and drawn in alignment mark groups is set to be one fourth of the designed total epitaxial layer thickness at the end of each epitaxial layer growth cycle or longer.

2011-11-24

20110287618

METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR APPARATUS - Disclosed is a method of manufacturing a silicon carbide semiconductor apparatus which provides a smooth silicon carbide surface while maintaining a high impurity activation ratio. The method of manufacturing a silicon carbide semiconductor apparatus which forms an impurity region in the surface layer of a silicon carbide substrate includes the steps of implanting an impurity into the surface layer of the silicon carbide substrate, forming a carbon film on the surface of the silicon carbide substrate, preliminarily heating the silicon carbide substrate with the carbon film as a protective film, and thermally activating the silicon carbide substrate with the carbon film as a protective film.

2011-11-24

20110287619

Flash Memory Cell Arrays Having Dual Control Gates Per Memory Cell Charge Storage Element - A flash NAND type EEPROM system with individual ones of an array of charge storage elements, such as floating gates, being capacitively coupled with at least two control gate lines. The control gate lines are preferably positioned between floating gates to be coupled with sidewalls of floating gates. The memory cell coupling ratio is desirably increased, as a result. Both control gate lines on opposite sides of a selected row of floating gates are usually raised to the same voltage while the second control gate lines coupled to unselected rows of floating gates immediately adjacent and on opposite sides of the selected row are kept low. The control gate lines can also be capacitively coupled with the substrate in order to selectively raise its voltage in the region of selected floating gates. The length of the floating gates and the thicknesses of the control gate lines can be made less than the minimum resolution element of the process by forming an etch mask of spacers.

2011-11-24

20110287620

METHOD OF ADJUSTING METAL GATE WORK FUNCTION OF NMOS DEVICE - The present invention provides a method of adjusting a metal gate work function of an NMOS device, comprising: depositing a layer of metal nitride film or metal film on a high K dielectric as a metal gate electrode by a physical vapor deposition process; implanting elements such as Tb, Er, Yb or Sr into the metal gate electrode by an ion implantation process; performing a high temperature annealing so that the doped metal ions are driven to and accumulate on the interface between the metal gate electrode and the high K gate dielectric, or form dipoles by an interface reaction on the interface between the high K gate dielectric and SiO

2011-11-24

20110287621

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - To improve a charge retention characteristic of a nonvolatile memory transistor. A first insulating film, a charge trapping film, and a second insulating film are formed between a semiconductor substrate and a conductive film. The charge trapping film is formed of a silicon nitride film including an upper region having a low concentration of hydrogen and a lower region having a high concentration of hydrogen. Such a silicon nitride film is formed in such a manner that a silicon nitride film including 15 atomic % or more hydrogen is formed by a chemical vapor deposition method and an upper portion of the silicon nitride film is nitrided. The nitridation treatment is performed by nitriding the silicon nitride film by nitrogen radicals produced in plasma of a nitrogen gas.

2011-11-24

20110287622

Transistors with Multilayered Dielectric Films and Methods of Manufacturing Such Transistors - Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a mixture thereof, and an upper dielectric film on the lower dielectric film, the upper dielectric film comprising a Group III metal oxide, Group III metal nitride, Group XIII metal oxide or Group XIII metal nitride. A gate electrode is provided on the multilayered dielectric film.

2011-11-24

20110287623

Three-Dimensional Nonvolatile Memory Devices Having Sub-Divided Active Bars and Methods of Manufacturing Such Devices - Nonvolatile memory devices are provided and methods of manufacturing such devices. In the method, conductive layers and insulating layers are alternatingly stacked on a substrate. A first sub-active bar is formed which penetrates a first subset of the conductive layers and a first subset of the insulating layers. The first sub-active bar is electrically connected with the substrate. A second sub-active bar is formed which penetrates a second subset of the conductive layers and a second subset of the insulating layers. The second sub-active bar is electrically connected to the first sub-active bar. A width of a bottom portion of the second sub-active bar is less than a width of a top portion of the second sub-active bar.

2011-11-24

20110287624

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - To reduce capacitance between each adjacent two word lines in a semiconductor memory device, a first insulating film is formed, with a first gate insulating film thereunder, in an interstice between gates respectively of each adjacent two memory transistors, and in an interstice between a gate of a selective transistor and a gate of a memory transistor adjacent thereto. Additionally, a second insulating film is formed on the first insulating film, sides of the gate of each memory transistor, and a side, facing the memory transistor, of the gate of the selective transistor. A third insulating film is formed parallel to a semiconductor substrate so as to cover a metal silicide film, the first and second insulating films and fourth and fifth insulating films. Avoid part is provided in the interstice between each adjacent two gates of the memory transistors, and in the interstice between the gate of the selective transistor and the gate of the memory transistor adjacent thereto. A bottom and two sides of each void part are shielded by the second insulating film, and a top of each void part is shielded by the third insulating film.

2011-11-24

20110287625

METHODS OF FORMING A PATTERN, METHODS OF FORMING A GATE STRUCTURE AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - A method of forming a pattern in a semiconductor device includes forming an etching object layer on a substrate, the etching object layer is an oxide that is substantially free of impurities. A mask is formed on the etching object layer, the mask is an oxide that includes impurities. The etching object layer is patterned using the mask as an etching mask and then the mask is removed. The mask is removed using an etchant having an etching selectivity to an oxide that is substantially free of impurities and an oxide that includes impurities during removing of the mask to limit damage to the patterned etching object layer during removal of the mask.

SEMICONDUCTOR TEST PAD STRUCTURES - A semiconductor test pad interconnect structure with integrated die-separation protective barriers. The interconnect structure includes a plurality of stacked metal layers each having an electrically conductive test pad separated from other test pads by a dielectric material layer. In one embodiment, at least one metallic via bar is embedded into the interconnect structure and electrically interconnects each of the test pads in the metal layers together. The via bar extends substantially along an entire first side defined by each test pad in some embodiments. In other embodiments, a pair of opposing via bars may be provided that are arranged on opposite sides of a die singulation saw cut line defined in a scribe band on a semiconductor wafer.

2011-11-24

20110287628

Activation Treatments in Plating Processes - A method of forming a device includes performing a first plating process to form a first metallic feature, and performing an activation treatment to a surface of the first metallic feature in an activation treatment solution, wherein the activation treatment solution includes a treatment agent in de-ionized (DI) water. After the step of performing the activation treatment, performing a second plating process to form a second metallic feature and contacting the surface of the first metallic feature.

2011-11-24

20110287629

SILICON FILM FORMATION METHOD AND SILICON FILM FORMATION APPARATUS - A silicon film formation method includes a first film formation operation, an etching operation, and a second film formation operation. In the first film formation operation, a first silicon film is formed to fill the groove of the object to be processed. In the etching operation, an opening of the groove is widened by etching the first silicon film formed in the first film formation operation. In the second film formation operation, a second silicon film is formed on the groove having the opening widened in the etching operation to fill the groove. Accordingly, a silicon film is formed on a groove of an object to be processed having the groove provided thereon.

2011-11-24

20110287630

Methods of Processing Semiconductor Substrates In Forming Scribe Line Alignment Marks - A method of processing a semiconductor substrate in forming scribe line alignment marks includes forming pitch multiplied non-circuitry features within scribe line area of a semiconductor substrate. Individual of the features, in cross-section, have a maximum width which is less than a minimum photolithographic feature dimension used in lithographically patterning the substrate. Photoresist is deposited over the features. Such is patterned to form photoresist blocks that are individually received between a respective pair of the features in the cross-section. Individual of the features of the respective pairs have a laterally innermost sidewall in the cross-section. Individual of the photoresist blocks have an opposing pair of first pattern edges in the cross-section that are spaced laterally inward of the laterally innermost sidewalls of the respective pair of the features. Individual of the photoresist blocks have an opposing pair of second pattern edges in the cross-section that self-align laterally outward of the first pattern edges to the laterally innermost sidewalls of the features during the patterning.

2011-11-24

20110287631

PLASMA PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A plasma processing apparatus and a method of manufacturing a semiconductor device which can prevent a discharge from occurring between a substrate such as a semiconductor wafer or the like, and a base material of a lower electrode or a peripheral structure of the base material, and can improve yield and productivity. The plasma processing apparatus includes a processing chamber, a lower electrode, an upper electrode, and a plurality of lifter pins for supporting a substrate to be processed. Each of the lifter pins includes a pin body part and a lid part which is disposed on a top portion of the pin body part and has an outer diameter greater than an outer diameter of the pin body part. The lower electrode includes through-holes for lifter pins each of which includes a pin body receiving part, which has an inner diameter less than the outer diameter of the lid part and receives the pin body part, and a lid receiving part, which is formed in an upper portion of the pin body receiving part and receives the cover portion, and in which the lifter pins are disposed. In a state where the lifter pins are lowered, the lid part is received in the lid receiving part, and the upper portion of the pin body receiving part is blocked by the lid part.

2011-11-24

20110287632

MOVABLE CHAMBER LINER PLASMA CONFINEMENT SCREEN COMBINATION FOR PLASMA PROCESSING APPARATUSES - A movable symmetric chamber liner in a plasma reaction chamber, for protecting the plasma reaction chamber, enhancing the plasma density and uniformity, and reducing process gas consumption, comprising a cylindrical wall, a bottom wall with a plurality of openings, a raised inner rim with an embedded heater, heater contacts, and RF ground return contacts. The chamber liner is moved by actuators between an upper position at which substrates can be transferred into and out of the chamber, and a lower position at which substrate are processed in the chamber. The actuators also provide electrical connection to the heater and RF ground return contacts.

2011-11-24

20110287633

ULTRA HIGH SELECTIVITY ASHABLE HARD MASK FILM - A method of forming an amorphous carbon layer on a substrate in a substrate processing chamber, includes introducing a hydrocarbon source into the processing chamber, introducing argon, alone or in combination with helium, hydrogen, nitrogen, and combinations thereof, into the processing chamber, wherein the argon has a volumetric flow rate to hydrocarbon source volumetric flow rate ratio of about 10:1 to about 20:1, generating a plasma in the processing chamber at a substantially lower pressure of about 2 Torr to 10 Torr, and forming a conformal amorphous carbon layer on the substrate.