Although immersion-based 193nm
lithography has been able to provide significant improvements in
resolution, a through-pitch solution for the critical dimensions of the
CMOS 32nm technology node is not currently attainable. The commonly
used lithography approach is to create all patterns per metal layer in
a single exposure. Double patterning is the most likely choice to
create damascene features of a half pitch of about 50nm, which will be
a typical value for the 1X layers of the CMOS 32nm technology node. The
consequences of this patterning choice on the other process steps in
the damascene flow are under examination, while the potential of this
patterning approach for the creation of structures for the CMOS 22nm
node is being stressed.