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描述

General Description:The Full and Empty outputs of a Synchronous FIFO synthesized by the1.5.0 and 1.4 versions of CORE Generator do not appear to behavecorrectly in VHDL behavioral simulation using the Viewlogic Speedwave,Active-VHDL, and Summit Visual HDL simulators. On these platforms, bothoutputs are permanently asserted.

解决方案

1

Modify the code:

There are four processes in the FIFO model that are triggered by the rising edge of c_i. The code currently looks like this:

PROCESS BEGIN WAIT UNTIL c_i'EVENT; IF (c_i'LAST_VALUE='0' AND c_i='1') THEN ... END IF; END PROCESS;

The simulator is never proceeding past the WAIT statement.

The problem is that the Viewlogic Speedwave simulator is VHDL-93 compliant, whereas the behavioral model generated for the FIFO by CORE Generator is currently only VHDL-87 compliant. Xilinx software releases up to and including M1.5 support VHDL-87 only.

As a workaround, the condition that triggers the code following the WAIT statement (a change in the c_i signal) can be modified as follows:

PROCESS BEGIN WAIT UNTIL (c_i'EVENT) AND (c_i='1'); ... END PROCESS;

With the addition of the additional (c_i='1') condition, the change in c_i is detected by Speedwave, and the simulation works correctly.

2

Use a different simulator.

The simulation works properly on MTI.

3

Another code change that will function correctly under VHDL-93 is to modify the following code: