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Description

The Plasma CPU is a small synthesizable 32-bit RISC microprocessor. It is currently running a live web server with an interrupt controller, UART, SRAM or DDR SDRAM controller, and Ethernet controller. The Plasma CPU executes all MIPS I(TM) user mode instructions except unaligned load and store operations (see "Avoiding Limitations" below).

This "clean room" CPU core is implemented in VHDL with either a two or three-stage pipeline. It is running at 25 MHz on a Xilinx FPGA and also verified on an Altera FPGA.

Success Stories

The Plasma CPU along with the Plasma RTOS and TCP/IP protocol stack are now running a live Web Server on a Xilinx FPGA.

Block diagram

IMAGE: cpu.gif

FILE: cpu.gif
DESCRIPTION:

Example Instruction

The CPU is implemented with a two or three stage pipeline with an additional optional stage for memory read and writes. (Using the three stage pipeline enables "pipeline.vhd" which delays some control signals into the next stage.)
An ADD instruction would take the following steps:

Stage #0:

1. The "pc_next" entity passes the program counter (PC) to the "mem_ctrl" entity which fetches the opcode from memory.

Stage #1:

2. The memory returns the opcode.

Stage #2:

3. "Mem_ctrl" passes the opcode to the "control" entity.
4. "Control" converts the 32-bit opcode to a 60-bit VLWI opcode and sends control signals to the other entities.
5. Based on the rs_index and rt_index control signals, "reg_bank" sends the 32-bit reg_source and reg_target to "bus_mux".

Stage #3 (part of stage #2 if using two stage pipeline):

6. Based on the a_source and b_source control signals, "bus_mux" multiplexes reg_source onto a_bus and reg_target onto b_bus.
7. Based on the alu_func control signals, "alu" adds the values from a_bus and b_bus and places the result on c_bus.
8. Based on the c_source control signals, "bus_mux" multiplexes c_bus onto reg_dest.
9. Based on the rd_index control signal, "reg_bank" saves reg_dest into the correct register.

Downloads

The Opencores Subversion web page can create the 130KB plasma_latest.tar.gz file containing all the latest code.

Tools

The MIPS(tm) GCC ELF compiler for Windows is available gccmips_elf.zip (2.4MB). The OpenCores server wouldn't let me save zip files so I had to rename it with an '.odt' extention. Rename the file from gccmips_elf.odt to gccmips_elf.zip before unzipping the files into the trunk\gccmips_elf directory. Add this directory to your executable PATH environment: set path=%PATH%;YOUR_DIR\trunk\gccmips_elf

If you use Windows and don't have a Microsoft C compiler for Windows, you will need pre-compiled versions of the tools (rename as tools.zip) which should be placed in the tools directory.

You may also need a Windows version of gmake. Rename the file gmake_zip.odt to gmake.zip before unzipping.

Supporting Documentation

See the tabs at the top for additional build instructions:

The Plasma CPU instruction set

Building the tools

Additional Linux GNU MIPS tools

Building the Plasma RTOS

Building the Plasma TCP/IP stack

The implementation is based on information found in:

"MIPS RISC Architecture" by Gerry Kane and Joe Heinrich

"The Designer's Guide to VHDL" by Peter J. Ashenden

The MIPS I(TM) instruction set can be found by:

Go to the MIPS Technologies, Inc. Web site http://www.mips.com/.

Under the Products menu, click on Resource Library.

Click on Product Materials in the submenu on the left.

Click on MIPS Architecture from the next menu on the left.

Finally, click on the link for "MIPS32® Architecture for Programmers Volume II: The MIPS32® Instruction Set (.pdf)".

Big/Little Endian

The CPU core operates in Big Endian mode by default. To operate in Little Endian mode, change "little_endian" from "00" to "11" in the file mem_ctrl.vhd.

Bus Interface

All signals are active high. Here are the signals for writing a character to address 0xffff when using a two stage pipeline:

Status

Currently running on an Altera EP20K200EFC484-2X FPGA and a Xilinx XC3S500 and XC3S200 FPGA.

Also running on a Xilinx Spartan-3E starter kit with DDR SDRAM, Ethernet MAC, and Flash Controller.

Running at 50 MHz on newer Xilinx FPGAs with three stage pipeline.

See "opcodes.asm" for regression test.

Supports Interrupts.

Includes several C test programs: Calculating PI; Prime Numbers; Showing Numbers Using Words; the Plasma RTOS; and single precision floating point library.

Disclaimer

MIPS(R) is a registered trademark and MIPS I(TM) is a trademark of MIPS Technologies, Inc. in the United States and other countries. MIPS Technologies, Inc. does not endorse and is not associated with this project. OpenCores and Steve Rhoads are not affiliated in any way with MIPS Technologies, Inc.

Legal Notice

The Plasma CPU project has been placed into the public domain by its original author and is free for commercial and non-commercial use.

This software is provided "as is" and any express or implied warranties, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose are disclaimed.

Avoiding Limitations

This section describes how to avoid the two main limitations of the Plasma CPU core. The first limitation is that unaligned load and store operations are not supported since they were patented. This means that when loading or storing 32-bit values the memory address must be on a 32-bit aligned address. [The patent for the unaligned memory access instructions expired Dec 23, 2006.]

Most RISC CPUs have limited support for unaligned memory accesses. The GCC MIPS compiler does not normally generate unaligned memory accesses. Try compiling a C program and then look in the listing file if any of these MIPS instructions are used: LWL, LWR, SWL, or SWR. If needed, there is a GCC patch to never generate unaligned memory accesses at ultra-embedded->GCC Modifications.

The second main limitation of the Plasma CPU is that exceptions (BREAK and SYSCALL opcodes) must not be placed immediately after a branch instruction (in the branch delay slot). The main uses for exceptions are software interrupts for debugger support and calling operating system calls.