Detailed Description

This class represents an assumption made on an AddRec expression.

Given an affine AddRec expression {a,+,b}, we assume that it has the nssw or nusw flags (defined below) in the first X iterations of the loop, where X is a SCEV expression returned by getPredicatedBackedgeTakenCount).

Note that this does not imply that X is equal to the backedge taken count. This means that if we have a nusw predicate for i32 {0,+,1} with a predicated backedge taken count of X, we only guarantee that {0,+,1} has nusw in the first X iterations. {0,+,1} may still wrap in the loop if we have more than X iterations.

Member Enumeration Documentation

The increment is considered to be signed, and a + b (where b is the increment) is considered to wrap if: zext(a + b) != zext(a) + sext(b)

If Signed is a function that takes an n-bit tuple and maps to the integer domain as the tuples value interpreted as twos complement, and Unsigned a function that takes an n-bit tuple and maps to the integer domain as as the base two value of input tuple, then a + b has IncrementNUSW iff:

Note that the IncrementNUSW flag is not commutative: if base + inc has IncrementNUSW, then inc + base doesn't neccessarily have this property. The reason for this is that this is used for sign/zero extending affine AddRec SCEV expressions when a SCEVWrapPredicate is assumed. A {base,+,inc} expression is already non-commutative with regards to base and inc, since it is interpreted as: (((base + inc) + inc) + inc) ...