Clock gating is one of useful techniques to reduce the dynamic power consumption
of synchronous sequential circuits. To reduce the power consumption of clock tree, previous
work has shown that clock control logic should be synthesized in the high-level
synthesis stage. However, previous work may suffer from a large circuit area overhead
on the clock control logic. In this paper, we present an ILP (integer linear programming)
formulation to consider both the clock tree and the clock control logic. Our optimization
goal is not only to conform to the constraint on the overall power consumption, but also to
minimize the area overhead of clock control logic. Compared with previous work, benchmark
data show that our approach can greatly reduce the circuit area overhead under the
same constraint on the overall power consumption.

Received May 19, 2011; revised August 22, 2011; accepted February 19, 2012.
Communicated by Yao-Wen Chang.
* A preliminary version of this paper has been presented in 22nd VLSI Design/CAD Symposium [17]. This work was supported in part by the National Science Council of Taiwan, under Grant No. NSC 97-2221-E-033-053-MY3.