A new semiconductor package promises higher performance and higher pin counts
for the larger ICs now under development for wireless and cellular
communications applications. It is compatible with existing assembly equipment.

The growing market for high-performance, high-pin-count chips continues to
dictate the development of new IC packages. One of the latest is the very small
peripheral array (VSPA) package, developed by the Archistrat Technology
division of The Panda Project, a maker of computer systems located in Boca
Raton, FL.
The proprietary package squeezes 320 leads into a 27 x 27-mm area that houses
many standard IC chips. This is more leads than on a 208-lead plastic quad
flatpack (PQFP) measuring 31 x 31 mm. It is also more than a plastic ball grid
array (PBGA) occupying the same 27 x 27-mm package size can accommodate.
Moreover, the VSPA package has shorter leads and thus exhibits less inductance
than QFPs, PBGAs, and tape-automated-bonding (TAB) packages. The table compares
both size and performance characteristics for the VSPA against other
high-density packages.
The VSPA package has been tested at frequencies up to 3.5 GHz. Its small size
and improved inductance characteristics make it better suited than PQFPs for
housing high-performance chips for cellular and wireless communications,
particularly the larger ones now being developed. PBGAs can be made with fairly
short leads (solder bumps) and low inductance at competitive costs, though some
users may find inspecting and reworking these bumped packages difficult. TAB,
another high-density packaging technology, requires very large production
volumes to be economically viable.
The VSPA package consists of a molded plastic frame that has pins inserted in
three rows on its periphery. The semiconductor die is attached to a copper
plate that also forms the back of the package. This plate acts as a heat sink
to provide good thermal conductivity between the die and the ambient air. The
chip is then wire-bonded to the plastic frame that surrounds the die cavity.
The entire package is then placed cavity-down on the pc board. The package is
compatible with existing die attachment, wire bonding, and pick-and-place
equipment, thus saving assembly costs.
Initially, the patent-pending package will be built by Archistrat in a 320- or
360-lead configuration. However, the company plans to eventually offer a wider
range of lead counts as well as offer the process to licensees wishing to build
the package themselves. For more information, contact Jeff Mehler, corporate
communications manager for The Panda Project, at 407-994-2300, or .
--Spencer Chin