Abstract—A new dual-loop digital phase-locked loop (DPLL) architecture is presented. It employs a stochastic time-to-digital converter (STDC) and a high-frequency delta–sigma dithering to achieve wide PLL bandwidth and low jitter at the same time. The STDC exploits the stochastic properties of a set of latches to achieve high resolution. A prototype DPLL test chip has been fabricated in a 0.13- m CMOS process, features a 0.7–1.7-GHz oscillator tuning range and a 6.9-ps rms jitter, and consumes 17 mW under 1.2-V supply while operating at 1.2 GHz. Index Terms—Digital phase-locked loop (DPLL), digitally controlled oscillator (DCO), stochastic time-to-digital converter (STDC).

Fig. 1. Block diagram and noise sources of a digital PLL.

I. INTRODUCTION

R

ECENT ADVANCES in integrated-circuit (IC) technology are oriented toward making fabrication processes suitable for digital designs. Although systems of today are designed with a digital paradigm, analog blocks are still required for these systems-on-a-chip. Gate current leakage, component characteristics of MOS mismatches, layout-dependent – transistors, and many more effects make analog design in a deep-submicrometer process a very challenging task [1]. To alleviate all these problems, digital equivalent implementations of analog circuits should be used whenever possible. A digital implementation of phase-locked loops (PLLs) has several advantages in comparison to their analog counterparts: easy scalability with process shrink, elimination of the noise-susceptible analog control for a voltage-controlled oscillator (VCO), and the inherent noise immunity of digital circuits. Recently, several digital PLLs (DPLLs) have been reported [2], [3], which demonstrate the ability of a digital implementation to achieve the performance of analog PLLs.Manuscript received December 04, 2007; revised April 05, 2008, June 16, 2008, and December 02, 2008. First published December 02, 2008; current version published August 14, 2009. This work was supported by Semiconductor Research Corporation under Contract 2003-HJ-1076. This paper was recommended by Associate Editor G. Manganaro. V. Kratyuk was with the School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR 97331 USA. He is now with Silicon Laboratories Inc., Beaverton, OR 97006 USA (e-mail: v.kratyuk@gmail. com). P. K. Hanumolu, U. Moon, and K. Mayaram are with the School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR 97331 USA (e-mail: hanumolu@eecs.oregonstate.edu). K. Ok was with the School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR 97331 USA. He is now with MaxLinear Inc., Carlsbad, CA 92011 USA. Digital Object Identi?er 10.1109/TCSI.2008.2010109

A block diagram of an integer- digital PLL (referred to as digital PLL in the rest of this paper) is shown in Fig. 1. It consists of a time-to-digital converter (TDC), which performs the function of a phase detector (PD), a digital loop ?lter (DLF), a digitally controlled oscillator (DCO), and a feedback divider. The TDC senses the time difference between the reference clock and the DCO divided clock and converts it to a digis related ital format. The time resolution of the TDC by to the phase resolution (1) The digitized phase error information is ?ltered by the DLF and then used to control the DCO. In the case of a ring-oscillator-based DCO, frequency tuning can be performed by digitally turning on and off bias current sources. When an LC-based DCO is employed, frequency tuning is done by switching on and off the tank capacitors. There are two major sources of noise in digital PLLs. They are quantization noise from the TDC and oscillator noise. The ?ltering of the quantization noise from the TDC requires a low DPLL bandwidth, while the suppression of the DCO phase noise mandates a high bandwidth. Therefore, the DPLL architecture of Fig. 1 suffers from con?icting requirements on the DPLL bandwidth. In order to alleviate this bandwidth tradeoff, existing high-performance digital PLLs employ low-noise LC oscillators [4], [5]. This allows one to keep the DPLL bandwidth small and thus to ?lter phase-quantization noise from the TDC. On the contrary, in this paper, a ring oscillator is used, and the DPLL bandwidth is extended to achieve enough suppression of the oscillator phase noise. Thus, a high-resolution TDC is needed to reduce the amount of added quantization noise. For more comprehensive study of DPLL noise, the interested reader is referred to [6]. This paper describes a novel digital PLL with a high-resolution stochastic TDC (STDC) [7] and is organized as follows. Prior-art high-resolution TDCs are described in Section II, followed by the design and analysis of the STDC in Section III.

Section IV presents the architecture of the proposed digital PLL, followed by the circuit details of the DPLL implementation in Section V. Experimental results are presented in Section VI, and conclusions are drawn in Section VII.

II. TDC—PRIOR ART A signi?cant amount of research has been done in prior years to identify ways to build a high-resolution TDC. As a result, many time digitizing methods are described in the literature. The simplest TDC is based on a delay line composed of buffers (Fig. 2). Inverters are used in [8] for the with a delay time propagates through the delay line, delay line. The signal and when the signal arrives, the outputs of all buffers are read into a register and then decoded. The digital output is a code that represents the time difference between two signals . with a resolution of Despite its simplicity and ease of implementation, this approach suffers from several drawbacks. The resolution of such a TDC depends on process variations and ambient conditions, and is furthermore limited by the time delay of a single buffer. A delay-locked loop (DLL) can be utilized to calibrate the delay line [9] and make the resolution tolerant to process variations and ambient conditions. However, buffers with controlled delay are needed for the DLL operation. Such buffers have larger delay than buffers with ?xed delay due to the control circuitry. Thus, the use of controlled delay buffers increases the lower limit on the resolution of the TDC. Since a buffer propagation delay is used as a measurement unit, the TDCs described earlier suffer from a hardware limit on resolution. The coarse resolution of these TDCs results in a large quantization noise that is added to the system. This noise can be suppressed only by a low DPLL bandwidth. Recently, a scrambling TDC has been proposed in [10], which is based on a gated ring oscillator composed of tristate inverters. It uses oversampling and ?rst-order noise shaping to achieve a substantial improvement in resolution by averaging many consecutive results. The use of such a TDC in DPLLs is limited to cases where the reference frequency is much higher than the PLL bandwidth. A very promising high-resolution TDC has recently been proposed in [11]. This TDC employs two-stage conversion by a delay-line-based TDC. The time residue after the ?rst stage is ampli?ed by a state-of-the-art time ampli?er and then processed by a second stage. The main disadvantage of this TDC is its large area and relatively complex design, which leads to nontrivial scaling as the process shrinks. Given that the time measurement

Fig. 3. Vernier-delay-line-based TDC.

is done by a delay line, a calibration is necessary in this case as well. A TDC, proposed in [12], is based on a Vernier delay line and can thus achieve ?ner resolution. The Vernier delay line utilizes and , respectively, as two delay chains with delays and propagate through the shown in Fig. 3. Signals delay lines, and the time difference between them is decreased after each stage. The position in the by delay line at which both signals are at the same time de?nes the . time difference between them with resolution The resolution of this TDC does not depend on the delays of the unit elements used in the delay chains but rather on their difference. Therefore, time intervals that are smaller than a single inverter delay in a given process can be measured. This approach also utilizes a DLL for calibration purposes. The calibration is done on a replica delay line. Since calibration and measurements are done using different delay lines, their matching is a big concern in this approach, particularly in a deep-submicrometer process. Also, the calibrating DLL is usually composed of analog circuits and is thus not consistent with a digital PLL concept. Another way to achieve a resolution that is better than a single delay element is described in [13]. A delay line consisting of parallel buffers is utilized in this technique, as shown in Fig. 4. The delay of each buffer differs from that of the previous one by , which is set by adding a load capacitance. a certain time signal propagates through the buffers, whose outputs The signal arrives. Clearly, are sampled by a register when the such an approach suffers from random mismatches of both the delay elements and the load capacitors. Most of the aforementioned methods for time digitizing suffer from random mismatches. Their performance will degrade as the IC industry moves further toward deep-submicrometer processes. In this paper, a new digital PLL with a TDC that is similar to the one in [14], which advantageously uses random mismatches, is proposed. This method overcomes the weeknesses of the other approaches. It is able to achieve high resolution and, thus, low phase-quantization noise. A stochastic approach to data conversion has recently been exploited in the voltage domain for an analog-to-digital converter in [15].

A set of latches or arbiters exhibit random mismatches resulting from process variations. Thus, latches have inherent input offset voltages that create different thresholds for each latch. By providing the same input signal to all latches and summing their outputs, a precise time difference between the two input signals can be determined. An input voltage offset is affected by different mismatch sources in a latch. Since all the arbiters are identical, they have identical offset distributions. Therefore, according to the central limit theorem [16], the cumulative distribution of the input voltage offsets for a set of arbiters will approximately be normal or Gaussian. In Fig. 6, the outputs of all latches are summed. This is equivalent to the integration of a Gaussian-distributed random variable. Thus, the time difference to the output code characteristic of the STDC has a shape that is similar to that of the Gauss error function. B. Analysis of the STDC

III. STDC A. Principle of Operation An STDC exploits the stochastic properties of a set of latches to achieve high resolution. Fig. 5 shows latch-based TDCs with a different number of latches. The upper portion of the ?gure shows the block diagrams of TDCs, while the bottom portion shows the rising edges of two input signals. Let us ?rst consider a 1-bit TDC that is implemented with one latch, as shown in Fig. 5(a). There are two inputs to the latch, namely, signals 1 and 2. If signal 2 arrives after signal 1 crosses the threshold of the latch, i.e., after time , the TDC will report a “ 1;” otherwise, the TDC will report a “ 1.” In other words, the 1-bit TDC behaves as a bang-bang PD. Fig. 5(b) shows a 2-bit TDC that employs three latches with different thresholds. The different thresholds can be created by giving an input offset to each latch. The output value of such a TDC is voltage de?ned by the time when signal 2 arrives. For example, if it arbut before , the output of the TDC rives after time will be a “ 1,” which is after signal 1 crosses but before . In the same way, an -bit TDC can be realized it crosses latches [Fig. 5(c)], creating different with thresholds. Assuming that the signal slope is constant over all voltage threshold spreads, it can be concluded that the thresholds in time are proportional to the voltage thresholds.

According to the previously made assumption, the voltage threshold in arbiters has a Gaussian distribution. As was mentioned earlier, thresholds in time are proportional to the voltage thresholds. Thus, the time thresholds are also normally is distributed. The standard deviation of the time thresholds by related to that of voltage thresholds (2) where is the slope of a signal, is a random variable of the is the standard deviation of the time time thresholds, and thresholds. Under a zero-mean assumption, the distribution of the time thresholds is given by (3) Assume that the ?rst signal arrives at time . Given , the digital output of the STDC, the number of arbiters when the time difference between two signals is , can be determine by

(4)

This equation is the time-to-digital characteristic of a stochastic TDC.

The most important property of a TDC in a digital PLL is the gain. Since the time-to-digital characteristic of the stochastic TDC (4) is not linear, the gain changes, depending on the input time difference . If a DPLL is in lock, the input time difference is close to zero, and thus, the gain of the STDC can be determined for the in-lock condition by taking the time deriva, resulting in tive of (4) when (5) Since there is an expectation that 99.7% of the normally dis, this value may be contributed data lie in an interval of sidered as the absolute limit of operation for an STDC with a large number of arbiters. If the input time difference exceeds range, the STDC saturates and is able to report only the its maximum or minimum value. In this case, the operation of the STDC is similar to that of a bang-bang or binary PD. The resolution of the STDC in the vicinity of a zero input time difference is the inverse of the STDC gain (6) The resolution of the TDC depends on factors such as the following: the number of arbiters used, the arbiter circuit, the statistical properties of the devices used, and the slope of the input signals. The conversion range versus resolution tradeoff can be seen from (6), given that the conversion range is approximately . The TDC quantization step is proportional to the conversion range for a given number of arbiters. In order to improve the conversion range, the area of the arbiter devices should be reduced for higher device mismatches. Alternatively, the slope of the input signals can be reduced, but this will degrade the noise performance since slow edges are more susceptible to noise. The number of arbiters can be chosen based on the required resolution for a ?xed conversion range. The slope of the input signals can vary with process, supply voltage, and temperature (PVT). Also, the statistical properties of devices are not easily predicted. Therefore, the resolution (and gain) of the STDC cannot be predicted and has to be calibrated to ensure the stability of the DPLL’s ?ne loop for any PVT corner. If the gain of the STDC is known, the correction can easily be implemented in the digital domain. Calibration of the STDC is a challenging task, given that a picosecond-order time resolution has to be veri?ed, and is beyond the scope of our work. The interested reader is referred to [14] for an overview of STDC calibration techniques. Without affecting the conversion range, the resolution of the STDC can be changed by truncating its digital output or by activating or deactivating a required number of arbiters. It is also possible to trade the conversion range for resolution by changing the input-signal slope or by changing the statistical properties of an arbiter. The latter can be done by introducing controlled deterministic offsets in the arbiters. C. Implementation of the STDC A 6-bit stochastic TDC was implemented and consists of a set of latches and a digital encoder (Fig. 7).Fig. 8. Block diagram of an arbiter. Fig. 7. Stochastic TDC.

Fig. 9. Arbiter decision circuit.

Each arbiter in Fig. 7 consists of an arbiter circuit itself, followed by an SR latch and a D ?ip-?op, as shown in Fig. 8. As shown in Fig. 9, an arbiter circuit [14] determines which signal comes ?rst and generates an SB or RB signal. An SR latch after the arbiter reduces the probability of getting into a metastable state. The output of the SR latch is sampled by a D ?ip-?op, giving a 1-bit output to the encoder. The clock for the sampling D ?ip-?op should arrive after the SR latch is set but before it could change state due to the falling edges of the input signals. A quadrature clock derived from the DCO divided output has been used in our case. In Fig. 10, behavioral simulations of 100 stochastic TDCs are shown. The behavioral simulation is performed using a Simulink model. Two signals with a time difference are generated and passed to the decision circuitry. The decision circuit ?rst slices one signal based on randomly generated voltage thresholds, representing a voltage-to-time-offset conversion. The number of thresholds in the model is equal to the number of arbiters in the actual circuit (64 in our case). After that, both signals are given to a ?ip-?op to determine which signal arrived ?rst. The output of the ?ip-?op is processed to a digital output

the number of arbiters used and the frequency of operation. The simulated power consumption of the designed STDC is 2.7 mW. IV. DIGITAL PLL A. Digital PLL ArchitectureFig. 11. Stochastic TDC transfer characteristic.

code , which is plotted versus the input time difference in Fig. 10. Each simulation uses a new seed for generating random threshold voltages. When the DPLL is in lock, the input time difference is small, and the DPLL operates in the vicinity of a zero output code. The differential and integral nonlinearities (DNL and INL, respectively) in this region can be considered as a measure of the STDC linearity. A typical STDC transfer characteristic is shown in Fig. 11, together with a linear ?t. The corresponding INL and DNL are shown in Fig. 12. From this ?gure, the nonlinearity of the STDC is about 2 LSBs, which results in a 1-bit loss of resolution. A more coarse resolution will manifest itself as additional noise. The possibility of creating a high-resolution TDC and implementation simplicity are the main advantages of the stochastic approach to the design of a TDC. The penalty for that is bigger area. The power consumption of an STDC mainly depends on

A block diagram of the proposed DPLL architecture is shown in Fig. 13. It consists of two loops: a ?ne loop and a coarse loop. On power up, only the coarse loop is active. In the coarse loop, the bang-bang PFD (!!PFD) senses only the sign of the phase and the frequency difference between the reference signal and the divided oscillator clock . This information is ?ltered by the 12-bit DLF (DLF1) and is truncated and passed to the 8-bit DAC. The DAC converts a digital word into a current value that controls the DCO. The DCO has two control inputs for the coarse and ?ne loops. The lock detector (LD) monitors the 1-bit output of the bang-bang PFD and asserts an in-lock signal when the number of 0s and 1s are almost equal (within 64 units). When lock is detected, the LD freezes the coarse loop and activates the ?ne loop, which was held reset at the middle value of its frequency range. When the coarse loop is frozen, no data from the bang-bang PFD is delivered to the DLF1, which means that the integral part of it preserves the stored value and, thus, the frequency set by the coarse loop. The feedback dividers and are made from true single-phase clock ?ip-?ops in a divide-by-two con?guration. Both of them divide the frequency by a factor of four.

The stochastic TDC works as a PD in the ?ne loop. It measures the time difference between the rising edges of the and the divided oscillator clock . reference signal The measured time difference has the phase information embedded in it. The 6-bit digital output of the STDC is ?ltered by a 14-bit DLF (DLF2) and then given to the digital modulator (DSM). Since the resolution of the DCO is limited, it cannot accommodate a high-resolution signal from the loop ?lter. The purpose of the DSM is to requantize a low-frequency high-resolution digital signal into a high-frequency low-resolution one. In spite of the loss in resolution for a particular sample of the signal, the average resolution of the signal remains . unchanged. The DSM is clocked at a frequency of Both loop ?lters are proportional–integral controllers with ratio between the integral and proportional paths. B. Analysis of the Digital PLL The ?ne loop of the digital PLL has been designed using a charge-pump PLL analogy, as described in [17]. First, an -domain prototype has been designed. This is then converted into a -domain representation using the bilinear transform. The resulting small-signal -domain model for the ?ne loop of the DPLL is shown in Fig. 14. The DPLL inherits the stability properties of the -domain prototype. represents the following: 1) The cumulative loop delay the unit delay due to the sampling nature of phase detection in the loop; 2) the unit delay due to a register at the output of the DLF (Section V-B); and 3) a quarter of unit delay due to the . DSM. Thus, the cumulative delay in our design is The DSM is not shown in Fig. 14 because its signal transfer function is equal to one. From Fig. 14, the forward gain of the ?ne loop is given by

Fig. 15. Magnitude and phase responses of the DPLL’s ?ne loop.

Fig. 16. Bang-bang PFD.

DPLL’s magnitude response has been done by modulating the reference clock with a single tone at the frequency of interest and then observing spurs in the reference clock and DPLL output spectra at the same offset frequency. V. CIRCUIT DESIGN Since the proposed DPLL mostly consists of digital circuits that can be synthesized from a standard logic library or can manually be built from digital gates, more attention in this section will be paid to the design of the analog- and mixed-signal blocks used in the DPLL. A. Bang-Bang PFD The bang-bang phase-frequency detector in the coarse loop consists of a conventional PFD and a sampling D ?ip-?op (Fig. 16). The PFD produces up (UP) and down (DN) pulses. The time difference between the rising edges of the UP and DN pulses de?nes the phase-frequency difference of the two input signals. The UP pulse is sampled by the DN pulse to determine the sign of the phase-frequency error. The UP and DN pulses should suf?ciently be wide to drive the sampling D ?ip-?op. It is possible to make a PFD with a multibit digital output by digitizing the UP and DN pulses using a TDC. This will reduce the locking time of the coarse loop and improve the noise performance. Since the locking time and noise of the

(7) The closed-loop transfer function can be expressed as (8) Since no matching data was provided for the fabrication process, the design has been done with a 1-ps assumption for the resolution of the STDC. The resolution of the STDC has been estimated from ?ne-loop bandwidth measurements to be approximately 0.7 ps. Fig. 15 shows the magnitude and phase responses of the DPLL obtained from (8) using the estimated value for the STDC resolution. As a reference, the measured data points are also shown in Fig. 15. The measurement of the

coarse loop are not a concern, a 1-bit bang-bang PFD has been implemented. B. DLFs After the bang-bang PFD and the STDC, the phase-frequency information (or only the phase information in the case of STDC) in digital format is passed to loop ?lters DLF1 and DLF2. The structure of both loop ?lters is the same and is shown in Fig. 17. and The loop ?lter consists of a proportional path with gain an integral path with gain . Since the values of and are chosen to be a power of two, the gain operation is performed by a left-shift operation. A delaying integrator has been used in the integral path. It is possible to use a nondelaying integrator as well, but in this case, the critical timing path of the two adders had to be less than the period of the clock. A register consisting of D ?ip-?ops is added at the output of the loop ?lter to synchronize the output data with the clock in order to clean up glitches that might appear due to the adder operation. This register adds an additional one clock period delay to the loop. This is necessary in order to ensure proper operation of the DAC in the coarse loop and the DSM in the ?ne loop. C. DSM The DSM, shown in Fig. 18, is a single-loop second-order error-feedback structure. It has three output levels: 1, 0, and 1. The DSM is clocked by the oscillator’s frequency divided by four and can operate with a clock up to 500 MHz. To allow for such a high-frequency clock, the adders in the DSM were built using carry save, carry select, and carry look-ahead techniques. D. DCO The DCO shown in Fig. 19 consists of two DACs, namely, 8-bit coarse-loop DAC (CDAC) and three-level ?ne-loop DAC (FDAC), serving the coarse and ?ne loops, respectively, and a VCO.

Fig. 19. DCO.

Fig. 20. Unit current cell.

An 8-bit thermometer-coded current-steering DAC was used to convert the DLF output to the coarse analog control for the oscillator. A thermometer coding is used to guarantee monotonicity. The CDAC consists of an array of 256 current sources, a row decoder, and a column decoder. Each of the 256 current sources has a decoding logic and a differential current source, as shown in Fig. 20. The unit cell current is equal to 4 A, which results in the coarse-loop DCO gain kHz/LSB. It is important to note that a more area-ef?cient segmented architecture can be used to implement the digital-to-analog converter with guaranteed monotonicity. The CDAC is interfaced with the oscillator through an active is subtracted from a current mirror. The CDAC current ?xed bias current . The resulting current is mirrored to the oscillator, resulting in a 64-MHz tuning range. A capacitor is added between the control voltage node and the power supply to minimize glitches/ripples while maintaining loop stability. The DSM output controls the FDAC, which consists of two differential current sources. A unit differential current source is

shown in Fig. 20. The FDAC current is subtracted from and mirrored to the oscillator, resulting a ?xed bias current in a 2-MHz tuning range. Each current source delivers 4 A of current, which results in a 1-MHz frequency step after mirroring to the oscillator. An active current mirror was also used here to provide additional ?ltering of noise from the DSM. Since the dominant pole of this ?lter is much higher than the loop bandwidth, it has been ignored in the previous ?ne-loop analysis for simplicity. E. VCO As shown in Fig. 21, the VCO is a ?ve-stage ring oscillator. The delay cell is a pseudodifferential inverter where a pMOS latch is used to couple the two single-ended current-starved inverters to achieve a differential output. To achieve a low VCO gain, only one of the ?ve stages is controlled by the PLL. An additional nMOS latch is added to the controlled stage to further reduce the VCO gain. The rest of the stages are controlled by a ?xed bias voltage . This voltage is produced by sending external current via an on-chip diode-connected transistor. A 1- A change in the external current changes the VCO output frequency by 1 MHz. VI. EXPERIMENTAL RESULTS The proposed DPLL test chip has been fabricated using a 0.13- m CMOS process and occupies 0.6 mm of area (Fig. 22).

Fig. 24. DPLL phase noise.

A large portion of the DPLL is occupied by the CDAC and the stochastic TDC. Two-thirds of the stochastic TDC area is occupied by the latches, and one-third of the area is occupied by the encoder. The bottom right-hand side in Fig. 22 consists of the digital blocks: DLFs, LD, and DSM. A small area in the lower left is occupied by the rest of the analog circuitry. To avoid deterministic mismatch in the STDC, we carefully used common layout techniques to match clock paths: 1) The length of clock wires were matched, and 2) higher levels of metal layers were used for clocks where possible to avoid uneven fringing capacitances. The output power spectral density (PSD) of the ?ne and coarse loops in lock measured at 1.2 GHz is shown in Fig. 23. The right curve represents the ?ne-loop PSD, while the left curve represents the coarse-loop PSD shifted to the left in frequency for display purposes only. The coarse-loop PSD has spurs at about 4-MHz offset from the carrier that comes from the limit-cycle behavior of the bang-bang PLL. The bandwidth of the DPLL with the ?ne loop is about 4 MHz. The phase-noise plots of the ?ne and coarse loops are shown in Fig. 24. The phase noise of the ?ne loop is measured to be about 97 dBc/Hz at 1-MHz offset frequency.

dithering to achieve wide PLL bandwidth and low jitter at the same time. The STDC exploited the stochastic properties of a set of latches. Traditionally undesirable randomly mismatched devices were used for high-resolution time measurements. Because the resolution of the STDC was limited only by the number of latches used, an arbitrarily high resolution could be achieved. The test chip has been fabricated in a 0.13- m CMOS process, and the measured results have been presented. The DPLL featured a 0.7–1.7-GHz oscillator tuning range and a 6.9-ps rms jitter and consumed 17 mW under 1.2-V supply while operating at 1.2 GHz. ACKNOWLEDGMENT The authors would like to thank Samsung Electronics for providing the IC fabrication.

The jitters measured in the coarse and ?ne loops are shown in Figs. 25 and 26, respectively. The coarse loop has 23.6 ps of rms jitter (89 ps pk–pk), and the ?ne loop has 6.9 ps of rms jitter (56 ps pk–pk). It is clear from Fig. 25 that the coarse-loop jitter has a large portion of deterministic time uncertainties coming from the limit-cycle behavior of the loop. Table I summarizes the DPLL design. Table II compares the performance of our STDC implementation with other state-of-the-art TDCs. VII. CONCLUSION A novel digital PLL with a stochastic TDC was presented. It employed an STDC and a high-frequency delta–sigma

Kerem Ok (M’05) received the B.S. degree in electrical and computer engineering from Lafayette College, Easton, PA, in 2003 and the M.S. degree in electrical and computer engineering from the School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, in 2005. He joined MaxLinear Inc., Carlsbad, CA, in 2005, where he has been working on frequency synthesizers for tuner applications.

Un-Ku Moon (S’92–M’94–SM’99–F’09) received the B.S. degree from the University of Washington, Seattle, in 1987, the M.Eng. degree from Cornell University, Ithaca, NY, in 1989, and the Ph.D. degree from the University of Illinois at Urbana-Champaign, in 1994. He has been with the School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, since 1998, where he is currently a Professor. Before joining Oregon State University, he was with Bell Laboratories from 1988 to 1989 and from 1994 to 1998. Dr. Moon has served as an Associate Editor for the IEEE JOURNAL OF SOLIDSTATE CIRCUITS and the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, as the Editor-in-Chief of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, and on the Technical Program Committee of the IEEE Custom Integrated Circuits Conference. He also served on the IEEE Solid-State Circuits Society (SSCS) Administrative Committee (AdCom) and the IEEE Circuits and Systems Society (CASS) Board of Governors (BoG) as the SSCS representative to CASS. He currently serves as the Deputy Editor-in-Chief of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, and on the Technical Program Committee of the IEEE International Solid-State Circuits Conference and the IEEE VLSI Circuits Symposium.

Volodymyr Kratyuk (S’02–M’07) received the B.S.(Hons.) and M.S.(Hons.) degrees in physical electronics from National Technical University, Kyiv, Ukraine, in 1997 and 1999, respectively, and the M.S. and Ph.D. degrees in electrical engineering from the School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, in 2003 and 2006, respectively. From August to December 2004, he was with Texas Instruments Incorporated, Dallas, TX, working on high-performance preampli?ers for hard disk drives. Since 2007, he has been with Silicon Laboratories Inc., Beaverton, OR. His research interests include frequency synthesizers, digital equivalent implementation of analog circuits, high-speed clocking, and low-noise analog circuits.

Pavan Kumar Hanumolu (S’99–M’07) received the B.E. (Hons.) degree from the Birla Institute of Technology and Science, Pilani, India, in 1998, the M.S. degree from the Worcester Polytechnic Institute, Worcester, MA, in 2001, and the Ph.D. degree from the Oregon State University, Corvallis, in 2006. He is currently an Assistant Professor in the School of Electrical Engineering and Computer Science, Oregon State University. His research interests include high-speed, low-power I/O interfaces, digital techniques to compensate for analog circuit imperfections, time-based data converter techniques, and power-management circuits. Dr. Hanumolu currently serves as an Associate Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING and is on the Technical Program Committee of the IEEE Custom Integrated Circuits Conference and the Analog Signal Processing Technical Committee of the IEEE Circuits and Systems Society.

Kartikeya Mayaram (S’82–M’88–SM’99–F’05) received the B.E.(Hons.) degree in electrical engineering from Birla Institute of Technology and Science, Pilani, India, in 1981, the M.S. degree in electrical engineering from the State University of New York, Stony Brook, in 1982, and the Ph.D. degree in electrical engineering from the University of California, Berkeley, in 1988. From 1988 to 1992, he was a Member of the Technical Staff with the Semiconductor Process and Design Center, Texas Instruments Incorporated, Dallas, TX. From 1992 to 1996, he was a Member of the Technical Staff with Bell Laboratories, Allentown, PA. He was an Associate Professor with the School of Electrical Engineering and Computer Science, Washington State University, Pullman, from 1996 to 1999 and with the School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, from 2000 to 2003, where he is currently a Professor. His research interests include circuit simulation, device simulation and modeling, simulation and modeling of substrate coupling in mixed-signal ICs, integrated simulation environments for microsystems, and analog/RF design. Dr. Mayaram received the National Science Foundation CAREER Award in 1997. He has served on the Technical Program Committees of several conferences and was on the editorial board of the IEEE TRANSACTIONS ON COMPUTERAIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS as an Associate Editor from 1995 to 2001 and as the Editor-in-Chief from 2002 to 2005.