George W. Conner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

Abstract: According to some aspects, a system and method for processing messages in a plurality of successive cycles is provided. One such system may include a plurality of first circuits, each first circuit configured to output a message, the plurality of first circuits configured to operate synchronously, a first plurality of buffers, each buffer associated with a respective first circuit and configured to store a message output by the respective first circuit, a communication path configured to receive the plurality of messages from the buffers and to perform aggregation of the messages, thereby generating an aggregated indication, and one or more second circuits. The one or more second circuits are configured to operate synchronously and to receive the aggregated indication, wherein buffers of the first plurality of buffers are configured to store messages from respective first circuits for different times.

Abstract: An electronic system, comprising a first semiconductor device, a second semiconductor device, a clock circuit, and a plurality of independently adjustable calibration circuits connected in each of the plurality of serial data paths. The first semiconductor device may comprise a plurality of Serializer-Deserializer interfaces. The second semiconductor device may comprise a plurality of serial data interfaces coupled to the plurality of Serializer-Deserializer interfaces to provide a plurality of serial data paths between the first semiconductor device and the second semiconductor device. The plurality of Serializer-Deserializer interfaces and the plurality of serial data interfaces may be clocked from a clock signal derived from the clock circuit. The plurality of independently adjustable calibration circuits may be configured to compensate for timing differences across the plurality of serial data paths.

Abstract: An electronic system, comprising a first semiconductor device, a second semiconductor device, a clock circuit, and a plurality of independently adjustable calibration circuits connected in each of the plurality of serial data paths. The first semiconductor device may comprise a plurality of Serializer-Deserializer interfaces. The second semiconductor device may comprise a plurality of serial data interfaces coupled to the plurality of Serializer-Deserializer interfaces to provide a plurality of serial data paths between the first semiconductor device and the second semiconductor device. The plurality of Serializer-Deserializer interfaces and the plurality of serial data interfaces may be clocked from a clock signal derived from the clock circuit. The plurality of independently adjustable calibration circuits may be configured to compensate for timing differences across the plurality of serial data paths.

Abstract: According to some aspects, a system and method for processing messages in a plurality of successive cycles is provided. One such system comprises a plurality of first circuits, each first circuit configured to output a message, the plurality of first circuits configured to operate synchronously, a first plurality of buffers, each buffer associated with a respective first circuit and configured to store a message output by the respective first circuit, a communication path configured to receive the plurality of messages from the buffers and to perform aggregation of the messages, thereby generating an aggregated indication, and one or more second circuits. The one or more second circuits are configured to operate synchronously and to receive the aggregated indication, wherein buffers of the first plurality of buffers are configured to store messages from respective first circuits for different times.

Abstract: In one embodiment, provided is a protocol specific circuit for simulating a functional operational environment into which a device-under-test is placed for functional testing. The protocol specific circuit includes a protocol aware circuit constructed to receive a non-deterministic signal communicated by a device-under-test and to control a transfer of the test stimulus signal to the device-under-test in response to the a non-deterministic signal.

Abstract: In some implementations, a method for testing is provided, which includes simulating a functional operational environment for a first type device-under-test with a tester. This includes recognizing a non-deterministic response signal having a predetermined protocol, receiving the non-deterministic response signal from the first type device-under-test, ascertaining an expected stimulus signal to be transferred to the first type device-under-test from the non-deterministic response signal based on the predetermined protocol, and initiating transmission of the expected stimulus signal to the first type device-under-test. The method further includes simulating a functional operational environment for a second type device-under-test with the tester after testing the first type device-under-test.

Abstract: In one embodiment, a protocol aware circuit for automatic test equipment, which includes a protocol generation circuit constructed to retrieve protocol unique data and format the protocol unique data with a selected protocol definition corresponding to a device under test for testing the device under test. The protocol generation circuit may be constructed to retrieve the selected protocol definition from a protocol definition table.

Abstract: A semiconductor device tester includes programmable hardware configured to test a semiconductor device under test. The programmable hardware is programmed with two or more pattern generators to control a flow of data to and from the semiconductor device under test.

Abstract: In one embodiment, a protocol aware circuit for automatic test equipment, which includes a protocol generation circuit constructed to retrieve protocol unique data and format the protocol unique data with a selected protocol definition corresponding to a device under test for testing the device under test. The protocol generation circuit may be constructed to retrieve the selected protocol definition from a protocol definition table.

Abstract: In one embodiment, a protocol aware circuit for automatic test equipment, which includes a protocol generation circuit constructed to retrieve protocol unique data and format the protocol unique data with a selected protocol definition corresponding to a device under test for testing the device under test. The protocol generation circuit may be constructed to retrieve the selected protocol definition from a protocol definition table.

Abstract: A digital data signal capture circuit for synchronization of received digital data signals includes a transition detector for determining a state transition of the received digital data signal. The transition detector samples the received digital data signal at a first time, a second time and a third time and determines whether the transition occurs between the first time and the second time and whether it occurs between the first time and third time and generates an increment/decrement signal indicating a position for the transition. A strobe adjust circuit generates a strobe signal based on the increment/decrement signal. A capture circuit captures the received digital data signal using the strobe signal.

Abstract: A semiconductor device tester includes programmable hardware configured to test a semiconductor device under test. The programmable hardware is programmed with two or more pattern generators to control a flow of data to and from the semiconductor device under test.

Abstract: In one embodiment, provided is a protocol specific circuit for simulating a functional operational environment into which a device-under-test is placed for functional testing. The protocol specific circuit includes a protocol aware circuit constructed to receive a non-deterministic signal communicated by a device-under-test and to control a transfer of the test stimulus signal to the device-under-test in response to the a non-deterministic signal.

Abstract: In some implementations, a method for testing is provided, which includes simulating a functional operational environment for a first type device-under-test with a tester. This includes recognizing a non-deterministic response signal having a predetermined protocol, receiving the non-deterministic response signal from the first type device-under-test, ascertaining an expected stimulus signal to be transferred to the first type device-under-test from the non-deterministic response signal based on the predetermined protocol, and initiating transmission of the expected stimulus signal to the first type device-under-test. The method further includes simulating a functional operational environment for a second type device-under-test with the tester after testing the first type device-under-test.

Abstract: In one embodiment, a protocol aware circuit for automatic test equipment, which includes a protocol generation circuit constructed to retrieve protocol unique data and format the protocol unique data with a selected protocol definition corresponding to a device under test for testing the device under test. The protocol generation circuit may be constructed to retrieve the selected protocol definition from a protocol definition table.

Abstract: Data can be processed in automatic test equipment by dividing the test sites into groups and processing each group using a corresponding processor in a group of processors. Sections of the test equipment can communicate via a tester bus to a particularly designed multi-stream switch. The multi-stream switch can communicates with a plurality of processors via a plurality of processor busses. Each of the processors can run a separate instance of test software without interfering with software running on any other of the processors. The inventive protocol can be embodied essentially in hardware that can be adapted to an existing infrastructure without requiring substantial modifications of existing hardware or software.

Abstract: A digital data signal capture circuit for synchronization of received digital data signals includes a transition detector for determining a state transition of the received digital data signal. The transition detector samples the received digital data signal at a first time, a second time and a third time and determines whether the transition occurs between the first time and the second time and whether it occurs between the first time and third time and generates an increment/decrement signal indicating a position for the transition. A strobe adjust circuit generates a strobe signal based on the increment/decrement signal. A capture circuit captures the received digital data signal using the strobe signal.

Abstract: A synchronous clock signal can be adjusted relative to a data signal by decreasing a delay in the synchronous clock signal if a transition of a data signal occurs before a pulse of an offset clock signal which is delayed by one half cycle relative to the synchronous clock signal. The synchronous clock signal can be delayed if the transition of the data signal occurs after the pulse of the offset synchronous clock signal.

Abstract: In some implementations, a method for testing is provided, which includes simulating a functional operational environment for a first type device-under-test with a tester. This includes recognizing a non-deterministic response signal having a predetermined protocol, receiving the non-deterministic response signal from the first type device-under-test, ascertaining an expected stimulus signal to be transferred to the first type device-under-test from the non-deterministic response signal based on the predetermined protocol, and initiating transmission of the expected stimulus signal to the first type device-under-test. The method further includes simulating a functional operational environment for a second type device-under-test with the tester after testing the first type device-under-test.

Abstract: In one embodiment, provided is a protocol specific circuit for simulating a functional operational environment into which a device-under-test is placed for functional testing. The protocol specific circuit includes a protocol aware circuit constructed to receive a non-deterministic signal communicated by a device-under-test and to control a transfer of the test stimulus signal to the device-under-test in response to the a non-deterministic signal.