Cosmic Circuits M-PHY solution supports both the HS-G1 (1.5Gbps) and HS-G2 (3Gbps) modes and is available in multiple process technologies ranging from 85nm to 28nm. The silicon has been characterized across supply, temperature and process corners and detailed characterization reports will be available very soon. Here is a video showcasing Cosmic Circuits validation platform and methodology for the MIPI M-PHY:

S2C announces that TAKUMI Corporation, a Japan-based advanced Graphics Intellectual Properties (IP) provider, has implemented a series of Graphics IP cores on S2C’s rapid FPGA-based prototyping systems including GS3000and GSV3000 cores. These TAKUMI IP cores have been fully validated in FPGAs and can be easily demonstrated to and evaluated by customers; thereby significantly reduce system-on-chip (SoC) integration time.

TAKUMI’s GSHARK family of IP is the graphics solution to accelerate display rendering on a variety of embedded systems including mobile devices, digital home appliances and in-car information systems. Uniquely designed and customized to support embedded systems, GSHARK-TAKUMI family extensively lines up graphics IP cores addressing different embedded system use models, for the best IP selection.

Toshio Nakama, S2C’s Chief Executive Officer, said,” Integrating a complex IP core, such as a 3D graphics IP, in a SoC design often requires tremendous amount of verification effort such as verifying the correctness of all hardware functions, evaluating SoC bus efficiency and testing software compatibilities. And, the best methodology today for performing these tasks is by using FPGA-based prototypes that closely resemble the entire design operating at or close to actual speed, many months before actual silicon is available. We are very pleased to work with TAKUMI to provide SoC developers a series of advanced graphics IP cores already mapped on FPGA-based prototypes that can significantly shorten IP integration into SoC design and allow early start of software development and testing.”