AmbiLobe

I have not studied this Due debug facility, but it appears to be compatible with the JTAG standard Joint Test Access Group. The four pins would be used according to publicly available documentation for JTAG. A "Boundary Scan" should be accessible which consists of a shift register of vast proportions. You can shift out all states represented on latches in a chain of latches. the Boundary Scan is common on a microprocessor. You also may have access to the internal scan chain in the CPU core. That also is a second chain of flip flops in a chain with thousands of bit states representing proprietary and public microprocessor flags and state info.

What kind of debugger can I use on that 4pin debug header?Would it only work on AVR Studio?

Thanks,RI

Its a JTAG/SWD header, a common 0.1" connector although an unusual form factor for JTAG. I use the 10 pin JTAG/SWD header.

You'll need a suitable JTAG/SWD adapter, the Segger Jlink EDU version is fairly cheap and works with many IDE's including Atmel Studio. There are several other ways to do it, it is a question of selecting an adapter supported by your IDE, or vice versa.

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