ATM Chip Database

Programmable ATM cell processor

The MXT3010 is designed to perform cell manipulation and transmission in the data path of ATM cell streams and can be applied in applications including segmentation and reassembly, inverse multiplexing, port processing, traffic shaping, circuit emulation, IP bridging and cells-in-frames adaptation. The MXT3010 is based on a custom Risc processor core developed by Maker exclusively for ATM applications. It supports traffic management and flow control at full line rates for 155Mbps and 622Mbps communications. The MXT3010 is capable of bi-directional OC-3 or unidirectional OC-12 operation at full line rates regardless of packet size. It supports tens of thousands of concurrent virtual connections and is compliant with the ATM Forum's TRAffic Management 4.0 specification for independent shaping of traffic on each connection. The Risc core is a custom soft-wired ATM network (SWAN) processor developed by Maker. The Risc CPU executes one instruction per cycle at rates up to 100 MIPS and features a specialized memory access architecture designed by Maker. Maker's MXT3010 cell scheduling allocates per-connection bandwidth dynamically for advanced traffic management and simultaneous support of CBR, VBR and ABR classes of service. Two independent direct memory access engines and a UTOPIA port controller perform parallel data transfers across tow general system interfaces and an industry-standard UTOPIA (universal test and operations interface for ATM) interface.