28nm: The Last Node of Moore's Law

After the 28nm node, we can continue to make transistors smaller, but not cheaper.

We have been hearing about the imminent demise of Moore's Law quite a lot recently. Most of these predictions have been targeting the 7nm node and 2020 as the end-point. But we need to recognize that, in fact, 28nm is actually the last node of Moore's Law.

Beyond this point, we can continue to make smaller transistors and pack more of them into the same size die, but we cannot continue to reduce the cost. In most cases, in fact, the same SoC will actually have a higher cost!

The complexity for minimum component costs has increased at a rate of roughly a factor of two per year. Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years.

Clearly, Moore's Law is about "The complexity for minimum component costs," and the minimum component cost will be at the 28nm node for many years, as we will detail in the remainder of this blog.

Hartmann is making the case that the "Moore's Law discontinuation due to cost stagnation or increase" applies to bulk technologies, which is the technology base of the majority of the industry. ST's information is backed by GlobalFoundries as we can see from the following chart presented at the 2013 SOI Consortium workshop in Kyoto, Japan.

The above GlobalFoundries chart shows that the lowest-cost transistor is at the polySiON 28nm node. Beyond 28nm, scaling becomes extremely expensive due to double litho, HKMG, FinFET, etc. The increase in wafer cost is illustrated by the recent NVidia chart from Semicon Japan from December 2013, as illustrated below:

However, the SoC end product silicon area is dependent on the SRAM bit cell size far more than on the general transistor density. This is the fundamental challenge now facing dimensional scaling. SRAM bit-scaling has been dramatically slowed beyond 28nm. At 28nm, the bitcell size is about 0.12µm². The following chart by IMEC was reported in "Status update on logic and memory roadmaps" in October 2013:

Beyond 28nm, the SRAM bit-scaling rate is about 20% per node instead of the historical 50%. And the situation is actually far worse as is illustrated by the following chart, which was presented at ISSCC 2014 in an invited paper by Dinesh Maheshwari, CTO of Memory Products Division at Cypress Semiconductors. It was also at the center of our recent blog, "Embedded SRAM Scaling is Broken and with it Moore's Law."

Moreover, SoCs need I/O pads and their circuits, and other analog circuitry, all of which scale at a rate far less than 2X per node. Furthermore, the exponential increase in BEOL RC results in an exponential increase of number of drivers and repeaters, as is illustrated by the following chart, which was presented by Geoffrey Yeap, VP of Technology at Qualcomm in his invited IEDM 2013 paper. This suppresses the effective gate density increase to a factor of only X1.6, or less.

Summarizing all of these factors, it is clear that -- for most SoCs -- 28nm will be the node for "minimum component costs" for the coming years. As an industry, we are facing a paradigm shift because dimensional scaling is no longer the path for cost scaling. New paths need to be explored such as SOI and monolithic 3D integration. It is therefore fitting that the traditional IEEE conference on SOI has expanded its scope and renamed itself as IEEE S3S: SOI technology, 3D Integration, and Subthreshold Microelectronics.

The 2014 S3S conference is scheduled for October 6 through October 9, 2014, at the Westin San Francisco Airport. This new unified conference will help us to improve efficiency and establish this conference as a world-class international venue to present and learn about the most up-to-date trends in CMOS and post-CMOS scaling. The conference will provide both educational and cutting edge research in SOI and monolithic 3D and other supporting domains.

These technologies were not part of the mainstream semiconductor past. Accordingly, it is a golden opportunity to catch up with these technologies now. Please mark your calendar for this opportunity to contribute to and learn about SOI and monolithic 3D technology, as these technologies are well positioned to maintain the semiconductor industry's momentum into the future.

Hi Max - you are unsure of 5, 10, or 20 years. I agree, the crystal ball is mucho muddied right now. But we as an industry had better figure it out fast. With the economics flat or nearly flatted at 28nm, only a very few will see a need to go lower (for some other reason than cost scaling). I wonder about the slowing of innovation from this bottoming out as well. However, an aspect that may help us do this sooner rather than later: since 28nm will be around for a long long time, being the bottom of the cost bathtub, it is the perfect platform to try out monolithic 3d techniques (and any other ideas out there), especially for SoCs. The NAND folks are already getting there.....

It will be nice to see TSMC or Intel showing better cost of transistors. What I have seen out there is density chart which is actually do not result in reduce transistor cost due to the higher wafer cost. BUT this is well known by now, the real problem is the SoC costs !, it will be nice if you really read the blog before posting comments. Please look again at the SRAM density chart from the recent ISSCC 2014. If effectively the density increase from 28nm to 16nm is about 10% than the SoC cost will much higher at 16nm. Unless you can show data that is different you need to admit that 28 nm costs would be the cheapest for SoC for a while. And you are advise to read a previous blog published by EE Times " Why 450mm Will Be Pushed-Back Even Further" http://www.eetimes.com/author.asp?section_id=36&doc_id=1321239& , which provide additional support to the problem with embedded SRAM scaling. So regardless if you like monolithic 3D or not the 28nm is the last node of Moore's Law.

The industry is in a deep dodo -- 450mm (infinitely?) delayed, EUV (infinitely?) delayed, and even pure logic transistors cost is not dropping anymore. One can believe Intel's charts if one chooses to but, clearly, their life is at stake over this question, so they must be optimistic or short their own stock. Everyone else's data shows level cost at best, somewhat up realistically.

But this blog brings the other whammy to the table -- memory shrink ... that barely happens anymore. Which means that complex chip cost below 28nm will go up. Significanly.

Broadwell is right around the corner. Lets see what their die sizes are at 16nm. Perhaps SRAM amount will stay the same to compensate for poor SRAM scaling.

Intel is a good example to use since they don't need to take a margin hit in desktops and and servers. If 16nm really costs the same as 22nm they will have to reduce the die size by 50% to give the same margins.

22nm vs 28nm is just margin case because no need for double patterning yet(according to intel). Why hasn't TSMC just migrated to 22nm without it ? Or is really hard to make 22nm work with single patterning ?

EUV is now being considered for 7 nm insertion with double patterning (10 nm insertion decision point past). I am not sure if that is an improvement to the cost curve. The source power target is not fixed, has to keep moving up.

It's a good question, it might be just to differentiate from Intel's 22 nm. But the aggressive DP cost might be too high to be tolerated by customers, maybe they'll go for 16 nm to get FinFET benefit (if any) as well.