The objective of this project is to simulate a power system fed by a Type III doubly fed wind turbine generator (DFIG) and verify its operation by emulating a DFIG using a motor generator set. The team is to create the control algorithms for the generator side of the DFIG as well. This will be accomplished with RSCAD simulation software and a physical PIC24 microcontroller.

Problem Definition

Background

Currently in the power industry, "green" energy generation has a higher priority over traditional generation from fossil fuels such as coal or natural gas. One of the most common "green" production methods is to harness the wind. Today there are numerous wind farms with hundreds of wind turbine generators producing green energy. These wind farms are a huge monetary investment. Therefore protecting these wind turbines and keeping these green technologies in production under varying conditions has become a concern. The newer types of wind turbines (Type III and IV) can be modeled as a Doubly Fed Induction Generator (DFIG). Currently, the effects of faults on type III/IV wind turbines and the responses of the DFIGs to faults are not completely understood.

Nearly all new megawatt-scale wind power plants being developed employ either variable-speed doubly-fed asynchronous (Type III) or full converter-based (Type IV) wind turbine generators (WTGs). These two WTG types can produce energy over a wide range of wind speeds, allow for fast and independent control of active and reactive power, limit fault current, and comply with low-voltage ride-through (LVRT) requirements set forth by industry regulatory agencies.

For faults near the WTG terminals, the fault current can be several times the rated full-load current and is only limited by the system and the WTG impedances. The fault current characteristics for Type I and Type II WTGs are accurately represented in most commercially available short-circuit analysis tools used by protection engineers. Type III and Type IV WTGs, on the other hand, have much more complex fault current characteristics and are governed by the proprietary controls of the converters used in these generators.

For Type III and Type IV WTGs, the fault current contributions are usually limited to 1.1 to 1.2 times the rated full-load current, following any transients. This makes it very difficult to use a number of the widely available short-circuit analysis tools employed by protection engineers without causing erroneous breaker trips.

Design Goals

- Create RSCAD Software Simulation model of DFIG fed power system

- Program DFIG control algorithm into microcontroller fed generator side drive controls

- Ensure RSCAD DFIG model output matches physical DFIG output

Specifications

Below is our refined specification sheet. After our design review, we are confident that we can meet these requirements.

Deliverables

Project Learning

RTDS and RSCAD

RTDS Rack

Runtime Output of SLG Fault

Before testing the effects of faults on the DFIG, we will first model the system in RSCAD software and run simulations using the RTDS system. This will give us a better idea of how the system will react to various types of faults before we do physical testing using the model power system. The simulations are carried out in a RSCAD Runtime file. An example of a runtime output can be seen in the figure to right.

The RSCAD model and runtime will also allow us to verify the accuracy of the transient and steady state behavior of our DFIG. We have parameterized the internal impedances of the physical DFIG and have input these values into our model in an attempt to achieve a nearly identical response.

Model Power System

Once we have a good idea of what to expect, we plan to connect the DFIG to the model power system and test faults in different locations throughout the system. This should verify or disprove the validity of our computer simulations.

Physical Generator and Controls

Motor/Generator Set with Controls

Once we have our RSCAD model up and running, we hope to create a working control system for a phycical DFIG located next to the Model Power System. Once we have our DFIG operating properly, we can apply faults to the system and verify that both our simulation and physical setup agree with each other.

Hardware Control Loop Effort

Phase-Locked Loop Block in Simulink

The first effort to implement microcontroller-based controls utilized a Park's Transformation in a phase locked loop. We analyzed how to incorporate these functions into a format that could be used by a microcontroller.

SEL Relays

SEL 421

SEL 411L

If time permits, we would like to design a detection/protection scheme using SEL relays. We are currently doing research on which relay will allow us to detect and protect faults most effectively. We are currently looking at two different relay options: the SEL 421 and the SEL 411L. Both have a variety of detection and protection technologies that will help us solve the problem. Once we determine which detection technology will work best for our project, we should be able to make a definitive choice of which relay we plan to use.

Team Information

Team Member

TEAM MEMBER

BIOGRAPHY

Drew McKinnon, E.E.

mcki7291@vandals.uidaho.edu

Drew McKinnon is a senior in electrical engineering at the University of Idaho. He received an ASEE from North Idaho College. He grew up in Oregon and Washinton and is interested in power systems integration. He enjoys reading, listening to music, and spending time with his family.

Andrew Miles, E.E.

mile4558@vandals.uidaho.edu

Andrew Miles is an electrical engineering senior at the University of Idaho. Andrew is currently finishing his Bachelor of Science degree in electrical engineering with an emphasis on power systems. He grew up in Juneau, Alaska and enjoys spending time outdoors and playing french horn.

Cody J. Swisher, E.E.

swis4861@vandals.uidaho.edu

Cody Swisher is an electrical engineering student at the University of Idaho. Cody is currently finishing his Bachelor of Science degree in electrical engineering, with an emphasis on power systems and signal processing. He was born in Spokane, Washington but has lived all across the world. He enjoys reading, watching football, fishing and playing video games.

Tiras Newman, E.E.

newm6560@vandals.uidaho.edu

Tiras is a senior in University of Idaho's electrical engineering program. He has a background in power generation as an engineering intern with the US Army Corps of Engineers at Lower Granite Lock and Dam as well as John Day Lock and Dam. He served as the head of maintenance for the Wendell School District in Wendell Idaho after spending four years as a journeyman electrician. Tiras previously ran a busy woodworking business. He's also very good looking and you can't deny his wit.