In the private cache organization, most of the L1 cache misses can be handled by the L2 cache, so the number of remote on-chip L2 cache accesses is reduced and it is not necessary to cross the interconnection network, which reduces the miss latency.

The experiments show, through running-time measurements and processor-event measurements, that some matrices cause many more cache misses in the left-looking algorithm than in the multifrontal one, while others cause many more cache misses in the multifrontal algorithm than in the left-looking one.

In the trace-driven simulation model, however, instructions may wait at different stages in the pipeline because of resource conflicts, incorrect speculative execution, data dependencies, serialization, cache misses, and many other reasons [2].

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