Aldec optimizes FPGA routing for power and performance

ALINT from Aldec is an advanced static design analysis and checking solution that decreases verification time by identifying critical issues early in the RTL design phase of ASIC and FPGA designs.

The latest release of ALINT delivers performance improvements, a team-based task management utility, and a new premium rule library that includes checkers to optimize routing resources in designs targeting today’s largest FPGAs.

“Although each device family is unique as a place and route target, mismanagement of routing resources negatively impacts resource utilization, performance and power,” said Dmitry Melnik, Product Manager, Aldec Software Division. “Within the RTL, routing-unaware design styles limit choices for the place and route tools later in the design cycle. This results in additional routing capacitance and delay, and consequently increased power and impaired performance. In contrast, routing-aware design techniques improve routing utilization and allow place and route applications to consume less of the target device and produce better quality results.”

Logic placement at different levels of design hierarchy (hierarchical design)

Sub-optimal cross-hierarchy interconnections that increase fanout

I/O port registering issues

The guidelines supported in ALINT’s premium rule library enable logic synthesis and place and route tools to provide more efficient chip utilization. The new rules benefit not only FPGA designs but are also equally applicable to ASIC designs that use multiple FPGA boards for prototyping, where partitioning and resource management can be very challenging.

AvailabilityALINT is available today with premium rule plug-in for FPGA routing resources optimization as an add-on option. ALINT is distributed worldwide (please contact your local ALDEC sales office for pricing.

Click Here for product release notes detailing new features and enhancements and a free 30-day evaluation.

If you found this article to be of interest, visit Programmable Logic Designline where – in addition to my Max's Cool Beans blogs – you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).

Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).