AMBA Specifications

Facilitate Right-First-Time Development of Multi-Processor Designs

The ARM® AMBA® protocols are an open standard, on-chip interconnect specification for the connection and management of functional blocks in a System-on-Chip (SoC). It facilitates right-first-time development of multi-processor designs with large numbers of controllers and peripherals.

AMBA5 CHI (Coherent Hub Interface) specification is the latest addition to the AMBA family adding a new protocol for the interface architecture, highly scalable SoCs required by many server and networking applications.

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AMBA enables IP re-use

IP re-use is essential in reducing SoC development costs and timescales. AMBA specifications provide interface standards that enables IP re-use if the following essential requirements are met:

Flexibility

IP re-use requires a common standard while supporting a wide variety of SoCs with different power, performance and area requirements. With its ACE, AXI, AHB and APB interface protocols, AMBA 4 has the flexibility to match every requirement. With AMBA 5 CHI interface ARM extends performance and scalability to many coherent processors.

Wide Adoption

There is a large amount of IP available in the industry today. AMBA caters for this IP and engineers across the globe have accepted it as a standard and use it daily. It is the most widely adopted industry standard for on-chip connectivity for IP products varying from; Memory Controllers, Interconnects, Trace solutions, GPU's, CPU's

Compatibility

It is a standard interface specification that ensures compatibility between IP components from different design teams or vendors. The AMBA specifications are available as both a written specification as well as a set of assertions that unambiguously define the interface protocol, thus ensuring this level of compatibility.

Support

The wide adoption of AMBA specifications throughout the semiconductor industry has driven a comprehensive market in third party IP products and tools to support the development of AMBA based systems. The availability of SystemVerilog assertions for AMBApromote this industry wide participation.

AMBA 5 CHI Performance

The latest generation, highest performance AMBA 5 interface called CHI for Coherent Hub Interface is targeted at the highest performance, highly scalable SoCs found in networking and server applications. Support for:

Support for high frequency, non-blocking coherent data transfer between many processors

Quality of Service (QoS) to ensure optimal overall system performance across all masters

A layered model to allow separation of communication and transport protocols

AMBA 4 Performance

The AMBA 4 specification includes AXI4 and ACE (AXI Coherency Extensions). It is targeted at high bandwidth, high clock frequency system designs and includes features that make it suitable for high-speed interconnect typical in mobile and consumer applications. The key features and benefits of the AXI protocol are:

It has been architected for scalability to maintain performance as the number of components and quantity of traffic rises. This includes placing additional requirements on masters to respond to coherent snoop transactions that means forward progress for particular masters can be more easily guaranteed in a congested system. The separation of the identification mechanism into master identifiers and transaction identifiers allows the interconnect to be constructed in a more efficient manner.

The CHI protocol provides a Quality of Service (QoS) mechanism to control how resources in the system shared by many processors are allocated without needing a detailed understanding of every component and how they might interact.

The CHI specification separates the protocol and transport layers to allow differing implementations to provide the optimal trade-off between performance, power and area.

The CHI specification is currently available to partners integrating SoCs or developing IP or tools that implement it. Please contact your ARM account manager for details on obtaining a copy.

AMBA 4 Specifications

The AMBA 4 specification adds another five interface protocols on top of the AMBA 3 specifications.

ACE-Lite

The ACE-Lite protocol is a small subset of ACE signals that offer I/O, or one-way, coherency, where ACE masters maintain the cache coherency of ACE-Lite masters.. ACE-Lite masters can still snoop ACE master caches, but other masters cannot snoop ACE-Lite master's caches. ACE-Lite also supports barriers.

AXI4

The AXI4 protocol is an update to AXI3 to enhance the performance and utilization of the interconnect when used by multiple masters. It includes the following enhancements:

Support for burst lengths up to 256 beats

Quality of Service signaling

Support for multiple region interfaces

AXI4-Lite

The AXI4-Lite protocol is a subset of the AXI4 protocol intended for communication with simpler, smaller control register-style interfaces in components. The key features of the AXI4-Lite interface are:

All transactions are burst length of one

All data accesses are the same size as the width of the data bus

Exclusive accesses are not supported

AXI4-Stream

The AXI4-Stream protocol is designed for unidirectional data transfers from master to slave with greatly reduced signal routing. Key features of the protocol are:

Supports single and multiple data streams using the same set of shared wires

AMBA 3 AHB Interface

The AMBA 3 AHB interface specification enables highly efficient interconnect between simpler peripherals in a single frequency subsystem where the performance of AMBA 3 AXI is not required. Its fixed pipelined structure and unidirectional channels enable compatibility with peripherals developed for the AMBA 2 AHB-Lite specification.

AMBA 3 ATB Interface

The AMBA 3 ATB interface specification adds a data agnostic interface for trace data in a trace system to the AMBA specification. The trace components and bus sit in parallel with the peripherals and interconnect and provide visibility for debug purposes.

AMBA 2 Specifications

The AMBA 3 specification replaces AMBA 2 and should be used for new designs. Existing AMBA 2 peripherals can be used in an AMBA 3 based system. The AMBA 2 specification defines a set of two interface protocols:

AMBA 2 AHB Interface

The AMBA 2 AHB interface specification enables highly efficient interconnect between masters in a single frequency system. This interface includes all of the capabilities of the AMBA 3 AHB interface but also enables the use of arbitration between masters in the construction.

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