Report: Computing has hit 'power wall'

WASHINGTON – As Moore’s Law runs out of steam and computing goes mobile, technologists are searching for ways to make the leap to new parallel programming frameworks that can leverage low-power multicore architectures.

The moved has been spurred by growing industry concern that today’s microprocessor computing engines have hit a “power wall”. That in turn has prompted a re-evaluation of the roadmap for high-performance computing, a reassessment that yielded a new study published by the National Research Council on the future of computing performance. The report’s bottom line is summed up in its subtitle: “Game Over or Next Level?”

“The era of sequential computing must give way to a new era in which parallelism is at the forefront,” the report asserts. “The next generation of discoveries is likely to require advances at both the hardware and software levels….”

The challenge, added the report’s editor, Samuel Fuller, chief technology officer at Analog Devices, is whether “we can develop software environments to develop new applications for multicore architectures.” What is needed are new parallel programming environments, Fuller said. “The breakthrough needs to be in the software environment.”

As single processors and CMOS technology approach the end of the technology line, the computing report concludes that chip designers and software developers alike must shift their focus to parallelism.

To that end, the report specifically recommends that research funded by industry, government and universities along with partnerships among them should focus on:

Overhauling the traditional computing “stack” to account for parallelism and resource-management challenges;

Investing in new parallel architectures that are driven by emerging applications like mobile computing;

Investing in R&D that focuses on power efficiency at all system levels. Further, the report recommends that R&D should directly address the looming “power wall” issue by “making logic gates more power efficient” and by looking beyond CMOS to lower-power device technologies.

As for software, some experts argue that the Open Source movement could help lead the charge in developing new programming methods for leveraging parallel processors. Open Source projects tend to operate like successful electronics industry consortia, according to David Liddle, a computer industry veteran who now serves as a general partner with U.S. Venture Partners. The Open Source movement has had a “huge impact” on computing, Liddle said, and a new effort is needed “to create the momentum necessary to attack the software” problem.

Others insist that performance improvements in devices like mobile phone SoCs have been hampered by power limits. “We’re in this box,” said Mark Horowitz, chairman of the electrical engineering department at Stanford University and chief scientist at Rambus Inc. “Performance now comes with a power penalty.”

The consensus among experts gathered here this week to consider the computing study recommendations, is that chip designers and software developers are now bound more tightly together as they seek a new paradigm for high-performance computing. Ultimately, it all comes down to power.

The more active a processor is; the more power it consumes. The more processors are running; the more power it consumes. It is the law. How can we achieve better performance w/o consuming more power?
On the other hands, parallelism is no doubt the future to hammer out the performance of next generation computing and to balance performance and power consumption. What would be the best strategies - on developer level or on compiler level or on processor level?

Within a technology, more processor activity and more processors require more power. However, new technologies may require less power. If we still ran computers using tubes, activating the complexity of current smartphones would trigger power outages in our homes rather than operating easily on a small battery. The trick is to find new technologies that are even less power hungry.

The discussion on another story regarding parallel architectures brought out several good points, including the thought that maybe it's time to reexamine the Von Neumann architecture. Is it time to rethink these fundamental assumptions?
Larry M.

The power consumption is a major criteria for the electronics only in the case of battery operated systems. Otherwise I do not think the power consumed by the electronic components is not going to create any major difference. I would like to see more research in the better battery technologies and more alternative energy sources.

The performance requirements are just increasing (games, video,...). In order to get a system meet the performance requirements they are only three solutions: raw clock speed, parallelism and dedicated processors.
Raw clock speed comes at the expense of power. In low geometry processes there is a choose between different Vt voltages. The lower the higher the speed and the power consumption. Parallelism can be obtained by either hardware or software. The first solution is hardware by using mult-issue out of order super scalar architectures. Also high end processor use power expensive branch predictors. Software parallelism comes however power-wise for free.
The last issue is about dedicated processors or rather the cost of legacy support. The extreme is the use of specialised processors for 3D graphics or even audio playback. Intel still needs to support the old 8086 instruction set. So they place down complex instruction decoders. ARM on the other hand supports more instruction set and is thus more efficient.

Parallel processing will help, but maybe we need more than that. Perhaps it's time to look not only at parallel equal processing cores, but also at collections of tailored processors For example, the Nvidia processor with a graphic core and a general computing core.
In the personal computer world, it's been well established that systems benefit from a combination of a graphics processor and a general computing processor. Years ago, floating point was done in software, or with a discrete co-processor. Today systems have the processing core(s), with built in floating point, and discrete graphic processors. Perhaps more efficiencies could be gained by developing dedicated database cores, communications cores and that like.
The requirements for high performance graphics work are different from that of database, and from communications, signal processing and a number of other functions. Make each processing core as efficient for the type of work that it's designed for and less computing power will be required to translate a general purpose core to the specific needs of some of these sub-systems.

Using parallel architectures we can trade area for dynamic power consumption. We can get the desired speed performance even if we operate at lower frequency. Because, the propagation delay is nearly inversely proportional to operating voltage, if we decide to operate the system at lower frequency, then we can be able to run the system at lower operating voltage. Since dynamic power dissipation is proportional to square of the operating voltage, parallel processing results in lower power consumption. This basically allows us to trade area for power. But, in certain problems, e. g, in some signal processing problems like digital filtering, where latency of computation is not a main issue, one can achieve lower power consumption by pipelining with less area overhead compared to parallel processing.

Yes, time has come to re-examine these assumptions. However, we have to do it in an incremental way because there are economic concerns here. Billions and billions of investment in hardware, software and applications have been expended with the Von-Neumann paradigm in mind. It is not reasonable to put that aside in favour of a new paradigm no matter how great is this new paradigm in theory.

For sure that would help but there is always an issue of critical mass and economies of scale. Graphics can afford specialised, increasingly powerful, and relatively cheap processors because of the size of the market. Who is going to take the hit of a large investment for equivalent technologies in other applications? What is the killer app.?