HDL Verifier

HDL Verifier

HDL Verifier™ automatically generates test benches for Verilog® and VHDL® design verification. You can use MATLAB® or Simulink® to directly stimulate your design and then analyze its response using HDL cosimulation or FPGA-in-the-loop with Xilinx®, Intel®, and Microsemi® FPGA boards. This approach eliminates the need to author standalone Verilog or VHDL test benches.

HDL Verifier also generates components that reuse MATLAB and Simulink models natively in simulators from Cadence®, Mentor Graphics®, and Synopsys®. These components can be used as verification checker models or as stimuli in more complex test-bench environments such as those that use the Universal Verification Methodology (UVM).

HDL Cosimulation

Debug and Verify System Designs

Use system test benches and golden reference models in MATLAB and Simulinkto verify that Verilog or VHDL code meets system specifications. Verify designs using MATLAB or Simulink with Cadence® Incisive® and Xcelium™ simulators, Mentor Graphics® ModelSim® and Questa® simulators, or the Xilinx® Vivado® simulator.

SystemVerilog Assertions

Generate native SystemVerilog assertions from assertions in your Simulink model. Use the generated assertions to ensure consistent validation of design behavior across Simulink and your production verification environment.

FPGA Data Capture

Capture high-speed signals from designs executing on an FPGA and automatically load them into MATLAB for viewing and analysis. Analyze signals throughout your design to verify expected behavior or investigate anomalies.

FPGA Testing Automation

Perform hardware verification from test benches in MATLAB or Simulink by generating FPGA bitstreams through integration with Xilinx, Intel, and Microsemi development tools. Add test points to Simulink models to capturing signals and loading them into MATLAB for viewing and analysis.

IP-XACT Support

Customize the TLM interfaces of the components you generate by importing IP-XACT™ XML files. Use TLM generator to produce IP-XACT files with mapping information between Simulink and generated TLM components.