@lleiva: Do you think that all ED will move from HDL to HLS? The end of days for HDLs is coming soon?

This is a tricky one. As I said in my talk, when we used to design a tth egate level and the more to RTL and Synthesis came along, a lot of designers resisted it. The ones who continued to resist are no longer designers. Now we have HLS -- there will always be a need for some amount of "hand-crafted design" at the RTL level (in the same way that we still used hand-crafted assembly language in some performance-critical software applications), but in the same way tha twriting programs in C is faster/easier than writing them in assembly, capturing designs at a high level and using HLS conveys a lot of advantages... I woudl say that most designers will be using a mix of HLS and RTL in just a coupel of years...

aburgin: Class suggestion: I've programmed in a dozen different languages, A great idea for a course would be a high level look at programming in C to create new generation FPGA's. I saw hins in the presntation, but it's only a snapshot... It looked fascinating

That's a good idea -- maybe we will do that in a future class. FYI, at Design West 2013 (next April) I will be hosting/moderating a free session titled "Learn 11 Computer Languages in 120 Minutes" where I give a 10 min intro then have 11 experts each talking for 10 mins about languages like C C+ SystemC SystemVerilog PSL, MyHDL...

@tomerb... no problem. I don't take it personally... the best part of this technology is engaging with you guys because (a) it's fun and (b) you make the course more than just a presentation... if we could all be in the same room, i think we'd have a blast. Thanks for joining in!

@Brian. I hope you saw the wink ;) at the end of my whine about interruptions. It's a tough balance I'm sure. It's nice when you bring relevant stuff from the chat stream into the lecture, and when you keep the chat stream on track with Questions relevant to the lecture. Max's timing through the slides feels pretty good to me; it's just not a lot of time, but that's not a bad thing either. Thx to both of you.

vyasa: Can you explain about the tesbench ? How its layered structure will be formed? Will it be taken care by the tool and the transactor?

Verification is a vast area in its own right. There are tools tha twill generate guided random sequences -- there are techniques using transaction level models to drive the abstract versions of the design and then coupl ethese with transactors to drive the lower-level representations of the design -- this truly is a vast area -- way to complex to go into here...

Class suggestion: I've programmed in a dozen different languages, A great idea for a course would be a high level look at programming in C to create new generation FPGA's. I saw hins in the presntation, but it's only a snapshot... It looked fascinating

gsbo: If I'm just starting out with Xilinx (zynq), which design tool should I learn?

Vivado, ISE or PlanAhead?

ISE is the previous generation -- but still widely in use. Vivady just came out -- PlanAhead is available with both -- in fact PlanAhead is the main "Cockpit" for Vivado -- personally if you are starting now I woudl say learn Vivado -- but then it depends on wha tdevices you are using -- if you are using FPGAs from a couple of generations ago you might be better off with ISE...

If we use a design tools based on C/C+ and on a Transaction Stream testbench are we capable to evaluate the peformance of different solutions ? If so, how ? Is a simulator provided by the design tool ?

If we use a design tools based on C/C+ and on a Transaction Stream testbench are we capable to evaluate the peformance of different solutions ? If so, how ? Is a simulator provided by the design tool ?

Our SoC/ASIC is targeted at a high performance electromechanical storage device for highly cost-competitive markets. The design is fairly stable so there is no need for the experimentation which an FPGA would provide and the FPGA is too costly in performance and dollars to include in mass production. But our early prototypes did use FPGA's.

1st language was BASIC on a Radio Shack TRS-80 III, in 1980. Today am programming with C and Assembly for ARM-based devices. Have not personally worked with a hardware design language, but work very closely with people who do.

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