Advanced Vector Extensions

Advanced Vector Extensions (AVX, also known as Sandy Bridge New Extensions) are extensions to the x86instruction set architecture for microprocessors from Intel and AMD proposed by Intel in March 2008 and first supported by Intel with the Sandy Bridge[1] processor shipping in Q1 2011 and later on by AMD with the Bulldozer[2] processor shipping in Q3 2011. AVX provides new features, new instructions and a new coding scheme.

AVX2 expands most integer commands to 256 bits and introduces fused multiply-accumulate (FMA) operations. AVX-512 expands AVX to 512-bit support using a new EVEX prefix encoding proposed by Intel in July 2013 and first supported by Intel with the Knights Landing processor, which shipped in 2016.[3][4]

The width of the SIMD register file is increased from 128 bits to 256 bits, and renamed from XMM0–XMM7 to YMM0–YMM7 (in x86-64 mode, YMM0–YMM15). In processors with AVX support, the legacy SSE instructions (which previously operated on 128-bit XMM registers) can be extended using the VEX prefix to operate on the lower 128 bits of the YMM registers.

AVX-512 register scheme as extension from the AVX (YMM0-YMM15) and SSE (XMM0-XMM15) registers

511256

255128

1270

ZMM0

YMM0

XMM0

ZMM1

YMM1

XMM1

ZMM2

YMM2

XMM2

ZMM3

YMM3

XMM3

ZMM4

YMM4

XMM4

ZMM5

YMM5

XMM5

ZMM6

YMM6

XMM6

ZMM7

YMM7

XMM7

ZMM8

YMM8

XMM8

ZMM9

YMM9

XMM9

ZMM10

YMM10

XMM10

ZMM11

YMM11

XMM11

ZMM12

YMM12

XMM12

ZMM13

YMM13

XMM13

ZMM14

YMM14

XMM14

ZMM15

YMM15

XMM15

ZMM16

YMM16

XMM16

ZMM17

YMM17

XMM17

ZMM18

YMM18

XMM18

ZMM19

YMM19

XMM19

ZMM20

YMM20

XMM20

ZMM21

YMM21

XMM21

ZMM22

YMM22

XMM22

ZMM23

YMM23

XMM23

ZMM24

YMM24

XMM24

ZMM25

YMM25

XMM25

ZMM26

YMM26

XMM26

ZMM27

YMM27

XMM27

ZMM28

YMM28

XMM28

ZMM29

YMM29

XMM29

ZMM30

YMM30

XMM30

ZMM31

YMM31

XMM31

AVX introduces a three-operand SIMD instruction format, where the destination register is distinct from the two source operands. For example, an SSE instruction using the conventional two-operand form a = a + b can now use a non-destructive three-operand form c = a + b, preserving both source operands. AVX's three-operand format is limited to the instructions with SIMD operands (YMM), and does not include instructions with general purpose registers (e.g. EAX). Such support will first appear in AVX2.[5]

The new VEX coding scheme introduces a new set of code prefixes that extends the opcode space, allows instructions to have more than two operands, and allows SIMD vector registers to be longer than 128 bits. The VEX prefix can also be used on the legacy SSE instructions giving them a three-operand form, and making them interact more efficiently with AVX instructions without the need for VZEROUPPER and VZEROALL.

The AVX instructions support both 128-bit and 256-bit SIMD. The 128-bit versions can be useful to improve old code without needing to widen the vectorization, and avoid the penalty of going from SSE to AVX, they are also faster on some early AMD implementations of AVX. This mode is sometimes known as AVX-128.[7]

These AVX instructions are in addition to the ones that are 256-bit extensions of the legacy 128-bit SSE instructions; most are usable on both 128-bit and 256-bit operands.

Instruction

Description

VBROADCASTSS, VBROADCASTSD, VBROADCASTF128

Copy a 32-bit, 64-bit or 128-bit memory operand to all elements of a XMM or YMM vector register.

VINSERTF128

Replaces either the lower half or the upper half of a 256-bit YMM register with the value of a 128-bit source operand. The other half of the destination is unchanged.

VEXTRACTF128

Extracts either the lower half or the upper half of a 256-bit YMM register and copies the value to a 128-bit destination operand.

VMASKMOVPS, VMASKMOVPD

Conditionally reads any number of elements from a SIMD vector memory operand into a destination register, leaving the remaining vector elements unread and setting the corresponding elements in the destination register to zero. Alternatively, conditionally writes any number of elements from a SIMD vector register operand to a vector memory operand, leaving the remaining elements of the memory operand unchanged. On the AMD Jaguar processor architecture, this instruction with a memory source operand takes more than 300 clock cycles when the mask is zero, in which case the instruction should do nothing. This appears to be a design flaw.[8]

VPERMILPS, VPERMILPD

Permute In-Lane. Shuffle the 32-bit or 64-bit vector elements of one input operand. These are in-lane 256-bit instructions, meaning that they operate on all 256 bits with two separate 128-bit shuffles, so they can not shuffle across the 128-bit lanes.[9]

VPERM2F128

Shuffle the four 128-bit vector elements of two 256-bit source operands into a 256-bit destination operand, with an immediate constant as selector.

VZEROALL

Set all YMM registers to zero and tag them as unused. Used when switching between 128-bit use and 256-bit use.

VZEROUPPER

Set the upper half of all YMM registers to zero. Used when switching between 128-bit use and 256-bit use.

GCC starting with version 4.6 (although there was a 4.3 branch with certain support) and the Intel Compiler Suite starting with version 11.1 support AVX. The Visual Studio 2010/2012 compiler supports AVX via intrinsic and /arch:AVX switch. The Open64 compiler version 4.5.1 supports AVX with -mavx flag. Absoft supports with -mavx flag. PathScale supports via the -mavx flag. The Free Pascal compiler supports AVX and AVX2 with the -CfAVX and -CfAVX2 switches from version 2.7.1. The Vector Pascal compiler supports AVX via the -cpuAVX32 flag. The GNU Assembler (GAS) inline assembly functions support these instructions (accessible via GCC), as do Intel primitives and the Intel inline assembler (closely compatible to GAS, although more general in its handling of local references within inline code). Other assemblers such as MASM VS2010 version, YASM,[14]FASM, NASM and JWASM.

AVX adds new register-state through the 256-bit wide YMM register file, so explicit operating system support is required to properly save and restore AVX's expanded registers between context switches. The following operating system versions support AVX:

Advanced Vector Extensions 2 (AVX2), also known as Haswell New Instructions,[5] is an expansion of the AVX instruction set introduced in Intel's Haswell microarchitecture. AVX2 makes the following additions:

Copy a 32-bit or 64-bit register operand to all elements of a XMM or YMM vector register. These are register versions of the same instructions in AVX1. There is no 128-bit version however, but the same effect can be simply achieved using VINSERTF128.

VPBROADCASTB, VPBROADCASTW, VPBROADCASTD, VPBROADCASTQ

Copy an 8, 16, 32 or 64-bit integer register or memory operand to all elements of a XMM or YMM vector register.

VBROADCASTI128

Copy a 128-bit memory operand to all elements of a YMM vector register.

VINSERTI128

Replaces either the lower half or the upper half of a 256-bit YMM register with the value of a 128-bit source operand. The other half of the destination is unchanged.

VEXTRACTI128

Extracts either the lower half or the upper half of a 256-bit YMM register and copies the value to a 128-bit destination operand.

VGATHERDPD, VGATHERQPD, VGATHERDPS, VGATHERQPS

Gathers single or double precision floating point values using either 32 or 64-bit indices and scale.

VPGATHERDD, VPGATHERDQ, VPGATHERQD, VPGATHERQQ

Gathers 32 or 64-bit integer values using either 32 or 64-bit indices and scale.

VPMASKMOVD, VPMASKMOVQ

Conditionally reads any number of elements from a SIMD vector memory operand into a destination register, leaving the remaining vector elements unread and setting the corresponding elements in the destination register to zero. Alternatively, conditionally writes any number of elements from a SIMD vector register operand to a vector memory operand, leaving the remaining elements of the memory operand unchanged.

VPERMPS, VPERMD

Shuffle the eight 32-bit vector elements of one 256-bit source operand into a 256-bit destination operand, with a register or memory operand as selector.

VPERMPD, VPERMQ

Shuffle the four 64-bit vector elements of one 256-bit source operand into a 256-bit destination operand, with a register or memory operand as selector.

VPERM2I128

Shuffle the four 128-bit vector elements of two 256-bit source operands into a 256-bit destination operand, with an immediate constant as selector.

AVX-512 are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture proposed by Intel in July 2013, and scheduled to be supported in 2015 with Intel's Knights Landing processor.[3]

AVX-512 instruction are encoded with the new EVEX prefix. It allows 4 operands, 7 new 64-bit opmask registers, scalar memory mode with automatic broadcast, explicit rounding control, and compressed displacement memory addressing mode. The width of the register file is increased to 512 bits and total register count increased to 32 (registers ZMM0-ZMM31) in x86-64 mode.

AVX-512 consists of multiple extensions not all meant to be supported by all processors implementing them. The instruction set consists of the following:

AVX-512 Foundation – adds several new instructions and expands most 32-bit and 64-bit floating point SSE-SSE4.1 and AVX/AVX2 instructions with EVEX coding scheme to support the 512-bit registers, operation masks, parameter broadcasting, and embedded rounding and exception control

Only the core extension AVX-512F (AVX-512 Foundation) is required by all implementations, though all current processors also support CD (conflict detection); computing coprocessors will additionally support ER, PF, 4VNNIW, 4FMAPS, and VPOPCNTDQ, while desktop processors will support VL, DQ, BW, IFMA, VBMI, VPOPCNTDQ, VPCLMULQDQ etc.

The updated SSE/AVX instructions in AVX-512F use the same mnemonics as AVX versions; they can operate on 512-bit ZMM registers, and will also support 128/256 bit XMM/YMM registers (with AVX-512VL) and byte, word, doubleword and quadword integer operands (with AVX-512BW/DQ and VBMI).[23]:23