Comments

The x2APIC architecture provides a new x2apic mode, which allows for the
increased range of processor addressability ( > 8 bit apic ID support),
MSR access to APIC registers, etc. The x2apic specification can be found
at:
http://download.intel.com/design/processor/specupdt/318148.pdf
It's been requested (I've CC'd Yinying) that we enable the
CONFIG_X86_X2APIC option in Maverick:
BugLink: http://bugs.launchpad.net/bugs/597091
config X86_X2APIC
bool "Support x2apic"
depends on X86_LOCAL_APIC && X86_64 && INTR_REMAP
---help---
This enables x2apic support on CPUs that have this feature.
This allows 32-bit apic IDs (so it can support very large systems),
and accesses the local apic via MSRs not via mmio.
If you don't know what to do here, say N.

On 06/22/2010 06:54 PM, Leann Ogasawara wrote:
> The x2APIC architecture provides a new x2apic mode, which allows for the> increased range of processor addressability (> 8 bit apic ID support),> MSR access to APIC registers, etc. The x2apic specification can be found> at:>> http://download.intel.com/design/processor/specupdt/318148.pdf>> It's been requested (I've CC'd Yinying) that we enable the> CONFIG_X86_X2APIC option in Maverick:>> BugLink: http://bugs.launchpad.net/bugs/597091>> config X86_X2APIC> bool "Support x2apic"> depends on X86_LOCAL_APIC&& X86_64&& INTR_REMAP> ---help---> This enables x2apic support on CPUs that have this feature.>> This allows 32-bit apic IDs (so it can support very large systems),> and accesses the local apic via MSRs not via mmio.>> If you don't know what to do here, say N.> =====>
The URL you've noted does not seem to be valid.
rtg