IP Roundtable, Part 5: Is EDA Unfair Competition?

Multiple instances of EDA tools are essential for IP core development. Do Cadence and Synopsys have an unfair advantage in developing IP cores?

At the end of the previous segment of this experts' roundtable, we were talking about the number of IP companies being bought by EDA companies. We continue to explore the relationship between IP developers and EDA companies here. Taking part in today's discussion are Warren Savage, CEO of IPextreme; John Koeter, vice president of marketing for the solutions group at Synopsys; and Chris Rowen, Cadence Fellow and CTO at Tensilica.

EE Times: How easy is it for IP companies to get EDA licenses both for compatibility testing and for their development needs?

Warren Savage: What you can do with the tools is usually written into the license agreements. We have relationships with all the EDA companies and license specifically for the purpose of testing and compatibility. We have built that support into our Xena systems so that customer IP is agnostic.

John Koeter: There's a big difference between using a tool for interoperability testing and using the tool to get value from it. That is the intrinsic value of the tool. We have other EDA vendors' tools [for testing purposes], and we get great discounts on them.

EE Times: Does it give you a competitive advantage because you have a set of in-house development tools? Does Synopsys give you the EDA tools for free to develop your IP, or do you have to factor tool costs into the cost of developing the IP?

Koeter: Tools are free for internal use.

EE Times: So, I presume that gives you an advantage over the external companies because they have to pay for the tools.

Koeter: Yes, certainly.

Chris Rowen: It's also an example of the economies of scale. The marginal cost of another simulator or synthesis seat is really just the cost of the hardware to run it on. I think it is a small factor in consolidation.

Savage: I would say that, for emerging IP-only companies, EDA is the No. 1 impediment for those companies to compete, especially in mixed-signal. It's gigantically expensive.

Rowen: Warren and I have bought a lot of EDA tools.

Savage: How much of our budget, our VC money, has gone to the EDA companies?

Rowen: How much money? It's huge. The biggest outlays that Tensilica made were to Synopsys and Cadence. I think we got great discounts, and we were treated very well by both companies. There are no complaints. It's just expensive stuff.

EE Times: I have heard some IP developers saying that they need scaled-back tools because they don't have to deal with such large capacity or performance [as full SoC developers]. But, as well as reduced capacity and performance, they want reduced cost.

Savage: I'm not sure about that.

Rowen: I'd say we want whatever the next grade is above whatever they're selling now. I mean, I think our demands in terms of the tools are extreme.

Savage: I think I completely agree. There may be some basic cases, but...

Rowen: There's a lot of value in those tools, and we'd like more -- more capability, faster run times, higher levels of optimization. There is an infinite appetite in these high-end products for more optimized tools and more optimized flows. They're expensive, but what they do is so essential. I wouldn't put what we do in the category of "Can you give me a cheaper, dumber tool?" I don't need the OrCad of synthesis and place and route to do this.

Koeter: If you just look at hardening a processor. You could run dozens of experiments with different floor plans and different constraint files. You know, you have to do that design exploration in order to get the best results.

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I would love to have other IP developers weigh in on this issue. How crippling are EDA tool costs for IP developers? Do the EDA companies have too big an advantage in developing IP?