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This tarball contains Verilog-A compact lookup table models for 7nm channel length Si FinFET with different underlaps which can be used in HSPICE netlists for circuit simulations. Device simulation data for constructing the lookup table model was generated using NEMO5 atomistic...

Public examples have been removed. Please see the regression test resource https://nanohub.org/resources/19171revision 8163Updated August 8, 2012bulk_Cu NCN_summer_school_2012Python_solverbulk_GaAs_band_structure Nitrides...