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Abstract

Efficient use of silicon area in integrated devices can be achieved with a special kerf alignment scheme, whereby the effects of epi shift are accurately compensated for during isolation mask alignment. thus eliminating the need for extensive spacings on the chip to ensure adequate clearances between isolation region and subcollectors.

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United States

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English (United States)

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Precise Symmetrical Alignment of Isolation Regions and Subcollectors

Efficient use of silicon area in integrated devices can be achieved with a
special kerf alignment scheme, whereby the effects of epi shift are accurately
compensated for during isolation mask alignment. thus eliminating the need for
extensive spacings on the chip to ensure adequate clearances between isolation
region and subcollectors.

In integrated circuits, it is common practice that in order to prevent the P+
isolation junction from hitting the N+ subcollector, the P+ isolation is removed
from the proximity of the N+ to the extent of the sum of the following tolerances:
the mask alignment tolerance, the amount of isolation (sideways) out diffusion,
the amount of subcollector (sideways) out diffusion and the amount of epi shift.
As shown in Fig. 1, the epi shift at 1 is generally 50% of the total dimensional
tolerance required for this problem and is a significant factor in increasing chip
size. It is common knowledge that the amount and direction of the epi shift can
be controlled; i.e., by control of epi growth conditions, crystalline orientation of
the substrate and choice of wafer flat location.

The following approach has completely eliminated the loss of chip area,
denoted at 4 in Fig. 2, which would normally be caused by the alignment
clearance tolerance requirements due to epi shift, through the application of a
special kerf alignment scheme. The technique for adequately compensating fo...