We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Firefox,
Internet Explorer 11,
Safari. Thank you!

AR# 22135

MIG 1.4 - Can I run the generated DDR SDRAM or DDR2 SDRAM controller at frequencies below 135 MHz?

Description

Can I run the generated DDR SDRAM or DDR2 SDRAM controllers at frequencies below 135 MHz?

Solution

The existing MIG 1.4 design was tested only down to 135 MHz.

The mem_interface_top_tap_ctrl module has to be modified for frequencies below 135 MHz. In the existing code, when only one edge of DQS is detected, the data is delayed by the number of taps it took to detect the first edge + 16 taps. Depending on the phase relationship, if it takes 48 taps to detect the first edge and 16 is added to this, the 6-bit tap counter rolls over to zero. This causes the calibration logic to start over again and causes it to loop indefinitely.

The proposed modification is to delay the data by half the number of taps it took to detect the first edge (if the first edge was detected in 40 taps or more). This will change the read enable logic, as well. The design files have this fix and have been tested on hardware. Starting in MIG 1.5, this will be incorporated into the source files. For earlier versions of the controller, download the modified source below. The patch file has been tested on hardware.

The MAXDELAY constraint can be relaxed at lower frequencies. In fact, they are not required if the period constraint is set as follows without FFS(*).