An internal presentation slide leaked to the press reveals some details of AMD's next generation "Trinity" APUs that succeed current generation A-Series "Llano" Fusion series. The presentation was run by AMD's principal foundry partner, Global Foundries, outlining upcoming products built on the 32 nm High-K metal gate transistor (HKMG) process. With Trinity, AMD is expecting a 50% improvement in gigaFLOP performance over the present generation, which doesn't sound far-fetched considering it will use next-generation Piledriver CPU core architecture and Radeon HD 7000 series graphics, which uses VLIW4 stream processor architecture.

Piledriver is an evolved x86 architecture that uses the modular shared resource design of Bulldozer, with much higher IPC compared to Stars architecture. VLIW4 stream processors ensure higher performance per square millimeter die area. Trinity will be available for notebooks as "Comal" and "Virgo" for desktops. They will be branded in the A-Series. AMD expects a 2012 market entry for the two.

I'd like to see a successor to the E series as well because my E-350 is a nice little APU that could be so much better with a dual channel DDR3 controller (hopefully with even higher speeds than 1066) and some next generation cores. I think the 6310 beats out my GeForce 7300 LE that I have laying around.

Getting that AMD apus will be on the same pcb as their discrete gpus from that slide seems like a stretch. No less, I find fudzilla to be a questionable source at times. "Trinity" makes it sound more like optimization for apu/discrete amd gpu combinations.

by: theubersmurfGetting that AMD apus will be on the same pcb as their discrete gpus from that slide seems like a stretch. No less, I find fudzilla to be a questionable source at times. "Trinity" makes it sound more like optimization for apu/discrete amd gpu combinations.

Say what now? There is no PCB. The CPU/GPU/IMC/Northbridge (and maybe some other stuff) are all on the die of the processor. :wtf:

VLIW4 to SIMD – This change allows for better GPGPU performance. VLIW5 and VLIW4 were efficient for graphics calculations, but not for general purpose (varying) CPU computations. SIMD brings the best of both worlds. In fact, Nvidia has been using this for quite some time within their Fermi architecture.

Unified Memory – Both CPU and GPU can utilize the same address spaces. The GPU now has built in address translation hardware just for this specific design implementation.

Improved C++ GPGPU programming and debugging support – Previously developers had to utilize assembly and some C to achieve the desired implementation. Now programmers can take full advantage of a high level language with AMD GPUs.

Compute Units – Instead of the traditional steam processor, AMD will utilized its new SIMD architecute (which is comprised of multiple ALUs making up a 16 bit wide vector SIMD block). Each compute unit has 4 SIMD blocks with an L1 cache. Overall, each CU with have its own L1 cache and all CU’s will share a L2 cache (which all Nvidia and AMD GPU’s currently employ).

Partially Resident Textures (PRT) – As with John Carmack’s MegaTexture technology, textures can now be partially loaded in memory for quicker access. This allows for the use of larger textures to be more efficiently used on a much larger scale than previous implementations. The main differnece is of course that insead of being implemented via software (id tech 5) it will now be implemented via hardware.