The first step of this study was the development of a model for information processing systems. In this stage of modeling the system is described as a set of nodes (gate cirsuits) and wires (transmission lines) in the topological space. The topological feature of the system is defined in terms of the fractal dimension, which is related to Rent's rule, derived analytically here for the first time, and further to the average wiring length to be used in a later stage of the analysis. Ways to project a topological graph onto a physical space are considered in view of the constraints on amnufacturing, namely, the basic form of projection is assumed as that onto elementary tiles, and the system morphology depends on how those tiles are assembled. All possible morphologies of assembling tiles were listed up, and from among them, the stack morphology was chosen as a focus of further study. The stack morphology has a widest scalability and the associative features such as the wiring length and the heat transfer characteristics are given by concise equations.An algorithm was developed for the cube stack system, by which one can determine the optimun size of element tiles and the optimum spacing between tiles. Since heat transfer data dir ectly applicable to situations of interest are scarce in the open literature, heat transfer experiments were conducted using a fluorinert coolant and microchannel heat sources fabricated on silicon chips.