Tech Beat: Monolayer molybdenite forms first-rate flash memory

The hot topic of conversation on the DRAM side might be 3-D memory, but when it comes to tackling the biggest issue on the flash memory front—shrinking cell size—2-D might just be the thing. Although the flash memory market is on a growth curve, its future depends on increasing data density, which means reducing cell sizes. The problem is that the floating gate that accumulates or releases charge in a flash memory cell can only be reduced to a certain size before it becomes too small to store sufficient electrons for clear write/rewrite. Although the industry is busy working on a bevy of flash alternatives, the answer may not be how we’re building the memory but what we’re building it with. By starting with a 2-D heterostructure of molybdenite (MoS2) monolayers and graphene, researchers at the École Polytechnique Fédérale de Lausanne (EPFL) have demonstrated a prototype flash memory that shows potential as a highly scalable, power sipping version of the nonvolatile memory we know and love.

Gate layer thickness isn’t the only barrier to scaling flash memory. Capacitive coupling between floating gate and drain electrode can both let the drain field penetrate too deeply into the transistor channel and also cause interference with neighboring cells. Reducing floating gate thickness can help mitigate this effect, but that brings us back to the primary problem of charge trapping. As a result, the EPFL group has been investigating monolayer alternatives for semiconducting channels, interconnects, and charge trapping layers.

A project spearheaded by Andras Kis, director of the Laboratory of Nanometer Electronics and Structures (LANES) at EPFL, the work is an extension of earlier research into molybdenite, which he processes into a single-layer flakes using the same method applied to produce graphene. Unlike graphene, molybdenite has a direct bandgap, in this case 1.8 eV, making it useful for semiconductor applications. For Kis and his team, this fits into a larger goal of developing a 2-D materials system for microelectronics. With MoS2 as semiconductor, graphene as interconnect, and a dielectric like boron nitride (BN), the team would have a full portfolio of single-layer materials to produce devices. Such monolayers could be harnessed for the fabrication of flexible electronics. To be useful, of course, microelectronics typically need memory; hence the current work.

2-D flash memoryThe group started with a heterostructure that featured a flake of monolayer MoS2 as a semiconducting channel, with a stripe of graphene on either side to act as the source and drain electrodes (see figure 1). The floating gate is formed by four- to five-layer thick multilayer graphene (MLG), separated from the MoS2 by a tunneling oxide formed of a multilayer stack of aluminum oxide (Al2O3) and hafnium oxide (HfO2). An additional, thicker barrier oxide of Al2O3 and HfO2 separates the floating gate from the control gate.

The work function of the floating-gate material affects the depth of the potential well, which controls its ability to retain electrons. Interestingly, although the work function of graphene can be tuned electrostatically or chemically, it is not sensitive to the number of layers. At the same time, MLG provides a higher density of states (better than 4.4 x 1013/cm2eV) compared to single-layer graphene (8 x 1012/cm2eV), which directly affects the ability of the material to store charge. Using MLG for the floating gate aids in the scalability of the overall device.

Electrons reach the MLG floating gate by traveling from the MoS2 channel through the insulating structure via Fowler-Nordheim tunneling. The band gap characteristics of MoS2 make it highly sensitive to charge distribution in the floating gate, which amplifies the difference between the voltages required for the write and erase states. Because the layer is so thin, the external electric field created by the trapped charge does not decay much as in penetrates into the material.

The proof is in the performance The group took the devices through comprehensive testing. A few highlights? Plots of drain-source current versus control-gate voltage VCG captured during voltage sweeps designed to monitor the response of the floating gate during charge/discharge revealed strong hysteresis with higher VCG required for the erase step than the write step, corresponding to a transfer characteristic, or memory window, of roughly 8 V.

In dynamic testing, the team put the devices through repeated program and erase states, demonstrating good performance for 120 cycles. Granted, that’s not enterprise-class performance, but this is an initial prototype, with much room for fine tuning. Perhaps more interesting is that the difference between write current (10-8 to 10-7 A) and read current (10-12 to 10-10 A) is around four orders of magnitude, making the devices good candidates for multi-level storage.

Of course, a key performance metric of nonvolatile memory is, well, its non-volatility. The team programmed the memory, then monitored variation in threshold voltage over time. According to their modeling and analysis, the floating gate would still retain 30% of initial charge 10 years after the write step.

Although the results are promising, the work is still in its earliest stages. Possible steps for improvement would include improving blocking oxide layer that lies between the floating gate and the control gate. For now, though, Kis quite pleased with the team’s results. “For our memory model, we combined the unique electronic properties of MoS2 with graphene’s amazing conductivity,” explains Andras Kis, author of the study and director of LANES. “Combining these two materials enabled us to make great progress in miniaturization, and also using these transistors, we can make flexible nanoelectronic devices."