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SRAM in FinFET technology

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed are several methods to tune the local source drain epitaxy in the Static Random Access Memory (SRAM) regions, resulting in smaller diamond shaped epitaxy around SRAM fins and higher Ron in SRAM fins. This enables current approaches for SRAM in fin Field Effect Transistor (FET) technology to be extended to three-dimensional (3D) technology.

Country

Undisclosed

Language

English (United States)

This text was extracted from a PDF file.

This is the abbreviated version, containing approximately
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SRAM in FinFET technology

Fin Field Effect Transistor (FinFET) technology requires Static Random Access Memory (SRAM) areas to support logic devices. SRAM needs higher Ron than fin in logic areas. In planar technology, higher Ron is accomplished my making the active area (Rx) smaller. This approach does not work in three-dimensional (3D) technology, such as FinFET or Nanowires, because it requires the fins to be locally shortened. A new structure is needed.

The novel solution provides several methods (explained in embodiments, below) to tune the local source drain epitaxy in the SRAM regions, resulting in smaller diamond shaped epitaxy around SRAM fins. The final structure has less contact area and less dopant, resulting in higher Ron in SRAM fins.

Figure 1: Embodiment #1. This method implants the source/drain (SD) region of SRAM fins prior to (global) source drain epitaxy. Fins are degraded/or amorphized. The SD epitaxy reduces to little or nothing; therefore, the final structure has a reduced contact area and less Dopant, resulting in higher Ron in SRAM fins.

Figure 2: Embodiment #2. This method is to recess fins in the SD region of the SRAM fins prior to (global) source drain epitaxy.

Figure 3: Embodiment #2, cont'd. The fins are shorter, resulting in smaller diamond shaped epitaxy around SRAM fins; therefore, the final structure has a reduced contact area and less dopant, resulting in higher Ron in SRAM fins.