What Is VHDL? VHDL Capabilities

VHDL is an acronym for VHSlC Hardware Description Language (VHSIC is an acronym for
Very High Speed Integrated Circuits). It is a hardware
description language that can be used to model a digital system at many levels
of abstraction ranging from the algorithmic level to the gate level. The
complexity of the digital system being modeled could vary from that of a simple
gate to a complete digital electronic system, or anything in between. The
digital system can also be described hierarchically. Timing can also be
explicitly modeled in the same description.

The VHDL language can be regarded as an integrated amalgamation of
the following languages:

sequential language +

concurrent language +

net-list language +

timing specifications +

waveform generation language => VHDL

Therefore, the language has constructs that enable you to express
the concurrent or sequential behavior of a digital system with or without
timing. It also allows you to model the system as an interconnection of
components. Test waveforms can also be generated using the same constructs. All
the above constructs may be combined to provide a comprehensive description of
the system in a single model.

The language not only defines the syntax but also defines very
clear simulation semantics for each language construct. Therefore, models
written in this language can be verified using a VHDL simulator. It is a
strongly typed language and is often verbose to write. It inherits many of its
features, especially the sequential language part, from the Ada programming
language. Because VHDL provides an extensive range of modeling capabilities, it
is often difficult to understand. Fortunately, it is possible to quickly
assimilate a core subset of the language that is both easy and simple to
understand without learning the more complex features. This subset is usually
sufficient to model most applications. The complete language, however, has
sufficient power to capture the descriptions of the most complex chips to a
complete electronic system.

(Ada is a registered trademark of the U.S. Government, Ada Joint
Program Office)

Capabilities:

The following are the major capabilities that the language
provides along with the features that differentiate it from other hardware
description languages.

The language can be used as an
exchange medium between chip vendors and CAD tool users. Different chip vendors
can provide VHDL descriptions of their components to system designers. CAD tool
users can use it to capture the behavior of the design at a high level of
abstraction for functional simulation.

The language can also be used as a
communication medium between different CAD and CAE tools, for example, a
schematic capture program may be used to generate a VHDL description for the
design which can be used as an input to a simulation program.

The language supports hierarchy, that
is, a digital system can be modeled as a set of interconnected components; each
component, in turn, can be modeled as a set of interconnected subcomponents.

The language is not
technology-specific, but is capable of supporting technology-specific features.
It can also support various hardware technologies, for example, you may define
new logic types and new components, you may also specify technology-specific
attributes. By being technology independent, the same behavior model can. be
synthesized into different vendor libraries.

It supports both synchronous and
asynchronous timing models.

Various digital modeling techniques
such as finite-state machine descriptions, algorithmic descriptions, and
boolean equations can be modeled using the language.

The language is publicly available,
human readable, machine readable, and above all, it is not proprietary.

It supports a wide range, of
abstraction levels ranging from abstract behavioral descriptions to very
precise gate-level descriptions. It does not, however, support modeling at or
below the transistor level. It allows a design to be captured at a mixed level
using a single coherent language.

Arbitrarily large designs can be.
modeled using the language and there are no limitations that are imposed by the
language on the size of a design.

The language has elements that make
large scale design modeling easier, for example, components, functions,
procedures, and packages.

There is no need to learn a different
language for simulation control. Test benches can be written using the same
language to test other VHDL models.

Nominal propagation delays, min-max
delays, setup and hold timing, timing constraints, and spike detection can all
be described very naturally in this language.

Generics and attributes are also
useful in describing parameterized designs.

A model can not only describe the
functionality of a design, but can also contain information about the design
itself 'in terms of user-defined attributes, for example, total area and speed.

A common language can be used to
describe library components from different vendors. Tools that understand VHDL
models will have no difficulty in reading models from a variety of vendors
since the language is a standard.

Models written in this language can be
verified by simulation since precise simulation semantics are defined for each
language construct.

Behavioral models that conform to a
certain synthesis description style are capable of being synthesized to
gate-level descriptions.

The capability of defining new data
types provides the power to describe and simulate a new design technique at a
very high level of abstraction without any concern about the implementation
details.

What Is VHDL? VHDL Capabilities
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Rating: 5 What Is VHDL? VHDL is an acronym for VHSlC Hardware Description Language (VHSIC is an acronym for Very High Speed Integrated Circuits). ...