Introduction

Nanotechnology can be termed as the ability to accurately manipulate matter on nanoscale dimensions, which is normlly in the the range 1 to 100 nm. Nanotechnology has enabled performance enhancement of traditional devices like the CMOS transistor and helped develop new technology and devices.

The application of nanotechnology has dramatically increased over the last few years and it is possible to assertively say that very few areas of human technology are exempt from its potential benefits.

This paper on nanoscale etching is most relevant to the information and communication sector but can also be used the energy and medical sector.

Etching involves selectively removing solid material through a mask to produce two or three dimensional structures in the fabrication of devices. The classic example is in etching steps required for monolithic integrated circuit fabrication (such as Complementary-Metal-Oxide Silicon (CMOS) transistor chips) with feature sizes on the micron scale and now much less.

This article will focus on the top down technique of ICP etching and will use specific techniques and results for nano-imprint technology and photonic crystal fabrication, as well as show the nanoscale etching capability for a wide range of materials and devices. The results are all achieved in Oxford Instruments ICP tools, demonstrating a strong capability in nanoscale etching.

Figure 1. From the ITRS 2010 Update, plotting product half-pitch gate length against year of production [2]

The ICP tools

The ICP tools used for nanoscale etching processes explained in this paper are all Oxford Instruments PlasmaPro® System 100 configured with various ICP sources. A schematic of an ICP180 etch chamber is shown in Figure 2 and a photograph of a PlasmaPro System 100 with the Cobra source is shown in Figure 3.

Figure 2. Schematic of the PlasmaPro® System100 ICP180 tool

Figure 3. Plasmapro System 100 ICP Cobra

The ICP sources have a cylindrical design with an RF power applied to a coil outside of an insulating to generate a high density plasma wherein the ion density is generally more than 1011/cm3. An electrostatic shield around the ICP tube makes sure that the ICP power is purely inductively coupled (i.e. ‘true-ICP’). The wafers are clamped either electrostatically or mechanically to the temperature-controlled lower electrode. Helium pressure is applied to the wafer rear side to ensure good thermal conductance between the wafer and the chuck. Smaller samples or pieces may be fitted to a carrier wafer with a thermally conductive compound.

Oxford Instruments ICP systems provide an optional wide temperature electrode often useful in nanoscale etching. Electrode temperature is controllable over a range of -150°C to +400°C. In general substrate temperature has a marked effect on the etch result, as the volatlity of the etch species is controlled and hence the chemical component of the process is influenced, affecting not only etch rate, selectivity and profile, but also surface roughness.

The systems are generally operated over a pressure range 0.1 to 100 mT by automatic pressure control. Gases are fed in through the top of the source or through a gas ring around the wafer electrode.

The PlasmaPro System 100 ICP180 is suited for up to 100mm diameter wafers. Oxford Instruments also offers an R&D tool, the PlasmaPro NGP 80 ICP 65 (usable area 50 mm diameter), and tools with larger diameter capacity: the PlasmaPro System 100 Cobra (200 mm), the PlasmaPro System 133 ICP380 (300 mm) and the PlasmaPro NGP1000 Viper (450 mm). The Cobra source is suitable for R&D or production, whereas the other two systems are primarily for production.

Other than a large usable area than the ICP180 source, the latest Cobra source offers increased flexibility through options of

1) Active spacer: enables independent control of ion distribution and offers optimised process uniformity across the electrode. 2) Pulsing: ICP Source Pulsing reduces wafer charging, for improved high aspect ratio etching. It may also be used for adjustment of ion radical ratios. Bias power pulsing (usually with low frequency power) reduces notching at interfaces with insulators and reduces aspect ratio dependent etching (ARDE). 3) Close coupled gas pod is useful for gas chopped processes such as Bosch etching to reduce gas mixing in short process steps.

Difficulties and Limits of Nanoscale Etching

Etching on the nanoscale is very tough for two basic reasons: 1) more difficult transport of neutrals species in and out of ever smaller features and 2) increased effects of charging by ions and electrons as sidewalls get closer together. The situation is compounded by the fact that in the design of smaller devices, usually the lateral shrink is more than the vertical shrink so the aspect ratio h/d rises as illustrated in Figure 4.

A critical parameter determining the progress of neutrals in and out of a trench is the sticking coefficient. Figure 6 offers real examples where the sticking coefficients and passivation are not optimally managed.

The next basic reason for the increasing challenge of nanoscale etching is the increased effects of charging by ions and electrons as sidewalls get closer together. Charged species experience a lateral force (charge q multiplied by the electric field E) which is inversely proportional to the square of the distance y from the sidewalls:

qE ∝ 1/y2

ions moving almost vertically are deflected towards the sidewalls, and at higher aspect ratio there are a higher percentage of ions experiencing significant deflection. See Figure 7.

Figure 8. Directional effects of charge [(a) Electron charges build up at the mouths of features. (b) Either balancing currents flow or charges builds up more.)]

In contrast, electrons with their much greater mobility in the plasma move isotropically, both in the bulk plasma and close to surfaces, and they tend to build up at the mouths of openings in the surface as shown in Figure 8a. If the substrate is insulating or electrically isolated like silicon-on-insulator (SOI) then charge build up will be worse as shown in Figure 8b.

Figure 9 gives examples where positive ion deflection is causing “notches” at the top or bottom of the feature, or the passivation is removed in the middle causing bowing. The additional fault of trenching at the base (deeper etching against the sidewall) is also associated with ion deflection.

Figure 9. Notch at top of feature

Nanoscale Etching by ICP

In this section several examples of successful nanoscale etching by ICP systems from Oxford Instruments are presented and discussed.

Nano-imprint Lithography

Nano Imprint Lithography (NIL) is a versatile, economic, flexible and high throughput (parallel) method for fabrication of down to 10nm (and shrinking) structures even over large areas (wafers) [8]. It has applications in semiconductor memory, micro and nano fluidics, optical devices e.g. LEDs and lasers, life science, e.g. lab-on-a-chip systems, bio-sensors, radio frequency components, renewable energy and new nanotech devices. The basic process flow of NIL is shown in Figure 10.

Figure 10. Schematic of the NIL process

A. A stamp is fabricated by electron beam lithography (EBL) and dry etching

B. The stamp is pressed into a soft thermoplastic, thermosetting or UV-curable polymer on a substrate combined with heating or UV radiation

Stamp etch

Requirements for a good stamp etch are vertical or very near vertical profiles (but no negative slope at all to avoid damaging the NIL polymer as the stamp is pulled out), Smooth sidewalls, uniform depths and critical dimensions (CD). It is also desirable to avoid trenching.

Figure 11 shows a chromium (Cr) masked quartz stamp etched in the System 100 ICP180 chamber using a C4F8-based plasma chemistry. 30nm features are etched to a depth of 200nm at a rate of 85nm/min ±<1% across a 2inch wafer. The selectivity over Cr was >170: 1. The profile is 89-90°, smooth and trench-free at the base.

Figure 11. High quality nanoscale quartz etching for NIL stamp

The quartz profile was optimised by means of the set electrode temperature as shown in Figure 12, while trenching was eliminated by using low enough DC bias – see Figure 13.

Figure 12. Simple profile control by temperature

Figure 13. Trench control by DC bias reduction

Cr is often used as a hard mask for the quartz stamp etch. Figure 14 shows a nanoscale Cr etch with features down to 70nm.

Descum NIL residual

The second area that needs an etch process is the descum of the NIL residual. Some “scum” is inevitable after the stamp presses into the NIL polymer and releases. Low scum is preferable of course (a ratio of HR/Hl 0.1 is considered very good e.g. 20nm of scum for a 200nm polymer film. See Figure 15).

Figure 15. Residual NIL polymer after stamping step

Requirements for a good descum are to remove the scum whilst minimising changes in profile and CD.

Figure 16 is an example of a descum process of BCB polymer leaving 10nm intact using an O2-SF6 ICP process.

Figure 16. Nanoscale BCB lines descummed by ICP

NIL Nanoscale Etching

Having prepared the imprinted polymer it is very often used as an etch mask.

Photonic Crystal Hole Etching

A photonic crystal is a periodic arrangement of holes in 1-d, 2-d or 3-d that creates a photonic band gap structure- see for example Figure 17. In a photonic crystal ‘forbidden’ wavelengths for light propagation arise much like forbidden electron energies within a semiconductor crystal.

The requirements of photonic crystal hole etching are generally to achieve smooth vertical walls and sometimes high aspect ratio. Some examples of two dimensional photonic crystal hole etches follow. These processes of course may be used for other nanotechnology applications such as those requiring ‘nanopores’.

The best process used a (polymer free) Cl2/N2/Ar chemistry. Cl2 is the etch gas, N2 provides sidewall passivation and Ar is used as a diluent. The OI wide temperature electrode is used with a set temperature above 200°C

An etched depth of 2.9µm for 180nm diameter hole size was achieved: an aspect ratio of 16:1. The etch rate was 1.75µm/min

Selection of other nanoscale ICP etching processes

In Figure 19 to 21, examples are given of three ICP silicon etch processes with complementary attributes for nanoscale etching. The first is a room temperature process using a C4F8-SF6 gas mixture (Figure 19). The second is the cryogenic process using a SF6-O2 gas mixture (Figure 20). The third process is an HBr-O2 process that can offer very high selectivity over SiO2 achievable by controlled O2 substitution (Figure 21).

Summary

A review of ICP etching for nanotechnology has been given. The paper explains the increasing difficulty of nanoscale etching and it has been stated that current ICP technology is good for several years more to below 20nm half pitch. Advances in technology are needed to get smaller and to what may be the ultimate limit for etching of around 5 nm will require advances in the technology to achieve better control of neutrals and charged species. New hardware developments may involve controllable frequency and pulsed plasmas, better substrate temperature control and advanced software control – for instance feedback loops using optical emission spectroscopy and other diagnostic techniques, parameter ramping.

Many examples of high quality nanoscale etches by Oxford Instruments ICP systems have been given and we are continually adding to our ‘portfolio’ of materials etched and applications in the highly important area of nanotechnology.