Book review: CHIPS 2020

Peter Clarke reviews Chips 2020: A Guide to the Future of Nanoelectronics, which sets out to discuss the need for and means of a transition from nanometer electronics to femtojoule electronics.

The creation of the book CHIPS 2020 - A Guide to the Future of Nanoelectronics, edited by Bernd Hoefflinger with contributions by authors from across the semiconductor field, was, according to Hoefflinger, prompted by signs of the imminent end of the electronics miniaturization roadmap at somewhere between 20-nm and 10-nm.

It is Hoefflinger's thesis that while current ideas may continue to serve they cannot alone move the semiconductor industry forward to 2020 in the manner to which we have all become accustomed. The fundamental problems of statistical variance in few-electron devices and energy consumption are already biting us and will require changes in the design and manufacture of integrated circuits. And it is with some emphasis on the radical, rather than the evolutionary approach that has served us to date, that Hoefflinger has written.

And so Chips 2020 sets out to explain the 20-nm to 10-nm transistor limits across a number of different applications and to discuss a transition from nanometer electronics, with the emphasis on physical dimensions and material cost, to femtojoule electronics with the emphasis on energy per chip function and energy cost.

The book's chapters provides an almost definitive list of hot topics and includes chapters on logic and computing, analog-digital interfaces, interconnects and transceivers, memories, 3-D integration, MEMS sensors, image sensors, power efficient design and energy harvesting and chip autonomy.

Many of the chapters are contributed by others and edited by Hoefflinger, many are authored by Hoefflinger himself. Notable contributors from the commercial sector include: Greg Delagi of Texas Instruments, Christian Jacobi, Peter Hans Roth and Kai Weber of IBM, Georg Kimmich of ST-Ericsson, Burn Lin of Taiwan Semiconductor Manufacturing Co. Ltd., Jiri Marek of Robert Bosch GmbH and Barry Pangrle of Mentor Graphics.

The book offers some far-reaching and fundamental insights. For example, in a chapter on the future of eight specific chip technologies Hoefflinger writes of CMOS: "The push for 10-nm transistors means supply voltages <400-mV heading towards 200-mV, attractive for high density memory and mobile systems. Allowances for speed and signal integrity can mean diminishing returns." Hoefflinger also expects to see a move to a different form of signal regneration circuit and differential signaling, both things that are likely to take up more real-estate.

With the observation that the once popular topics of neural networks and fuzzy logic have been relegated to the sidelines as software-only solutions Hoefflinger gives some thought to cellular neural networks and modeling of neuromorphic systems in silicon as one of the ways in which parallel processing and algorithm-to-processor bottlenecks may be overcome.

The extreme breadth of the book means that inevitably some topics are dealt with in less detail than others. I myself would have liked to have seen more discussion of the complex field of non-volatile memory devices, one of the areas where electron limitations and radical innovation are playing out in the research and commercial domains most dynamically.

But even where the book limits itself to explaining and documenting the state-of-the-art it is always clear and well referenced. And its breadth almost serves as a definition of the topics that mark the frontier of semiconductors for the next decade.

The 474-page CHIPS 2020: A Guide to the Future of Nanoelectronics, edited by Bernd Hoefflinger

The authors discuss, among other things, ubiquitous communication based on mobile companions, health and care supported by autonomous implants and by personal care-bots, safe and efficient mobility assisted by co-pilots and internet-based education for a billion people from kindergarden to retirement.

This book is aimed at educated readers who want an easy read but one that does not skimp on references or scientific accuracy. It is suitable both for the student, researcher or recent graduate that wants to understand where the challenges lie in chips, and for experienced managers, investors and policy makers, who may have been looking at the trees for so long that they will now benefit from this look at the forest.

About the author

Bernd Hoefflinger has spent a career in microelectronics with time in the U.S. as assistant professor of electrical engineering at Cornell, before returning to Germany as Siemens' first MOS product manager and then going on to co-found the University of Dortmund. Professorships at Minnesota and Purdue preceded the formation in 1985 of the Institute for Microelectronics, Stuttgart (IMS), which he helped establish as a leader in high dynamic range CMOS image sensors. Hoefflinger retired in 2006, but clearly not completely, because he has co-authored and edited an excellent book.

On the strength of this work, if Hoefflinger could be persuaded to delve into some of these individual "hot topics" in more depth, they too would be welcome compendia and useful additions to the landscape of engineering literature.

The 474-page hardback book is published by Springer and comes with 314 illustrations with 162 in color. The book is priced at $109/£72.00/€79.95 before local taxes. It is also available through Amazon.

Monolithic 3D provides ~10,000x more vertical connectivity. 3D IC as an alternative to 0.7x scaling is about maintaining Moore Law of doubling the amount of devices but instead of making them smaller just have them in two layers (and tomorrow 4). To do so we need very rich vertical connectivity ~ comparable to horizontal connectivity.

Yes, it is clear that the conventional 0.7x scaling down that our great industry has enjoyed has now reached the phase of diminishing returns.
The escalating cost of litho, the escalating cost of process R&D, the escalating interconnect delay, the issues of device variations and few other factors all point to the diminishing advantages of scaling down. But Moore's Law can keep on going as monolithic 3D is becoming practical. In fact, NAND Flash companies are already buying equipment for monolithic 3D products. Applied Material's blog “3D for Dummies” http://blog.appliedmaterials.com/3d-chip-technology illustrates it and MonolithIC 3D Inc. has released multiple flows for producing monolithic 3D logic and memories. MonolithIC 3D would enable the industry to continue the pace of doubling complexity while reducing cost and power. Reduction of cost would derive from the reduction of equipment cost and the ability to process multiple layers using the same litho step.
In short: we can continue to increase integration, but we might need to change the way we do it.

Yes, it is clear that the conventional 0.7x scaling down that our great industry has enjoyed has now reached the phase of diminishing returns.
The escalating cost of litho, the escalating cost of process R&D, the escalating interconnect delay, the issues of device variations and few other factors all point to the diminishing advantages of scaling down. But Moore's Law can keep on going as monolithic 3D is becoming practical. In fact, NAND Flash companies are already buying equipment for monolithic 3D products. Applied Material's blog “3D for Dummies” http://blog.appliedmaterials.com/3d-chip-technology illustrates it and MonolithIC 3D Inc. has released multiple flows for producing monolithic 3D logic and memories. MonolithIC 3D would enable the industry to continue the pace of doubling complexity while reducing cost and power. Reduction of cost would derive from the reduction of equipment cost and the ability to process multiple layers using the same litho step.
In short: we can continue to increase integration, but we might need to change the way we do it.