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Application-specific standard products (ASSPs) and application-specific integrated circuits (ASICs) are expected to become more than fifty percent of the $10 billion VLSI Digital Signal Processing (DSP) market in year 2000. With rapidly shrinking time-to-market (TTM) requirements, and multiple design goals that seek to optimize sample rate, clock speed, area, and power, the novel core-based behavioral synthesis methodology presented in this book shows how organizations can meet these new challenges effectively and consistently over the next decade.

The authors show how VLSI chips can be rapidly designed within a VHDL-based synthesis environment using a pre-designed library of core components. The core library represents synthesizable units of behavior (function and control) that are both application-specific and organization-specific, empowering the chip designer with a competitive advantage. The key to the quick-turnaround is the high amount of systematic reuse utilized within the design methodology. The percolation of accurate power, speed, area, and timing information to higher levels of abstraction allows rapid and efficient exploration of the design space facilitating the optimization of these objectives individually or concurrently. System integration and test of ASICs into board-level designs is also facilitated.

Abstract:

Modern digital signal processing applications provide a large challenge to the system designer. Algorithms are becoming increasingly complex, and yet they must be realized with tight performance constraints. This book shows a way to effectively resolve this tension by retaining the high-level conciseness of VHDL.Read more...