Simon is the vice president and general manager of the Design and Synthesis Division at Mentor Graphics and the speaker quoted in Mark LaPedus article. He thinks he was misunderstood, and wanted to make clear what his position about this subject is. In the final analysis his opinion is quite close to what I observed in my column and, to be fair, I am reprinting, with Simon's permission, his email to me.

Gabe,
I would have titled the EE Times article "EDA tools are giving gas to FPGAs".

I guess it may just be the market that is making everyone downbeat, but I sure was pretty optimistic in my keynote at the inaugural FPGA Summit in early December, so the EE Times article tenor seemed a bit off to me. Just to be clear, I'm very bullish on FPGAs. I spent the whole initial part of the speech focusing on all the positive trends that are occurring in the FPGA industry that indicate a bright future. These include:

The fact that over 50% of designers in a recent EE Times indicated they intend to increase use FPGAs in the next two years

Steady growth in FPGA revenue

More diverse use of FPGAs in multiple growth markets

FPGA design "going global" and expanding into all continents of the world

The second half of my speech dwelt on design complexity and the emerging solutions required to address them. The growing complexity of FPGAs was a huge positive and by no means a negative as described in the article. Because of the FPGA size and range of capabilities they enable to extend the market reach to areas where other technologies dominated in the past. They also enable us to offer advancements in design tools that complement and extend the current EDA offerings to address emerging bottlenecks in FPGA design, specifically algorithmic content, system level IP and low power. EDA invests in the automation of complex implementations of these functions so that FPGA customers can use them with a click of the mouse.

In addition, to the tools to address new challenges, the keynote speech covered the importance of the complete flow that covers all the traditional design steps including design creation, design analysis, synthesis, verification and PCB design. These tools need to continue and work seamlessly and be interoperable with the all FPGA vendor flows.

I concluded my speech with the summary:

FPGAs are scaling up to ASIC/SOC and present a great design innovation opportunity

Productivity of FPGA designs is improved with a complete tool set

Productivity of FPGA design can be further improved by adopting High Level Synthesis and TLM for better power, performance and area designs.

I hope this sets the record straight with many users who are currently using FPGAs and intend to grow the use of FPGAs in the near future.