I'd like to open a thread about linear CMOS, which is the technique of making digital chips behave in an analog way. The topic is well known, so perhaps someone might want to contribute some documents or links on the topic. Myself, I'd rather experiment and create in most cases. Anyway, I'll be doing some prototyping and reporting my results here. As always your input is welcomed and appreciated!

Last night I made no progress, however tonight I got back to basics and learned some things.

The first thing is really obvious but it should be stated for your awareness, which is that you only want to use inverting gates with Linear CMOS. Non-inverting gates have positive feedback which acts like hysteresis in comparator circuits.

The next thing I learned is that Linear CMOS works at DC but you need to compensate it. At some values (many really) the gate will oscillate, so what I did was put a cap to ground on the input node of the gate. I used 0.1uF caps and they worked just fine. The result was that the output was an inverted version of the input, with an artificial ground built-in at Vdd/2 approximately.

I tested a NAND gate with both inputs tied together (forming an inverter) first with a gain of one and it properly inverted the signal. Then I tested a NAND gate without connecting the two inputs, which is pretty cool IMHO. You just use two feedback resistors, two input resistors, and two compensation capacitors - should be easy to visualize so I won't draw it out. This made a nifty sort of summing amp with unusual characteristics.

Those characteristics are that if one input is held near ground and the other input is swept, you get a full range of output (and vice versa due to symmetry). However if you sweep both inputs together you do not get a gain of two, the gain is still one.

To properly characterize that I'd have to plot about 100 data points or so, and I don't feel like doing that especially without a voltmeter (mine broke, I'm working with a scope only). Then the data plot would be either a family of curves or a 3D plot or both. Maybe I'll get around to doing that sometime.

Oh yes, I should also mention that even with compensation, the output tends to oscillate when both inputs are near Vdd/2. I'm not sure what can be done about that.

So in summary, Linear CMOS NAND gates work in both single and double (and most likely more) input configurations, just hook them up properly and compensate them to make them work well. More to follow later, enjoy!

in my fiddling i have found that 4011 nands and 4001 nors do oscillate quite a bit, but 4049 and 4069 do not oscillate nearly as much. you can also put a cap in the feedback path to minimize oscillations.

i have had some trouble doing CV stuff that didnt have the bias voltage... I believe its possible, cus i've seen envelope followers and stuff be made, which go from zero to whatever +V using inverters. ill have to do more fiddling in that regard.

Do the other parts without the oscillation have hysteresis? that would explain it. Of course, you might either want or not want that oscillation in a music circuit, depending on that you are trying to create.

Well it's 3am and i don't feel like prototyping any more tonight so I'll update you on my progress. I made four linear CMOS gates which I hooked into a self-oscillating structure that didn't work at all. When I fail, i fail spectacularly or not at all, haha. Then tonight i made some good progress.

I built a pair of oscillators, one ten times slower than the other one, out of NAND gates. The each have a kill switch and the NAND gates have a feedback resistor so they will oscillate properly even with no Schmidt trigger on them. Got lucky there. They sound squareish and look it on the scope, though rather distorted looking.

I saved the four linear CMOS gates when I ripped out their interconnect so now I can hook them up to the oscillators for really weird sounds. I put capacitors in the feedback path of the linear gates to act as a single pole low-pass filter, with different capacitor values on the different inputs. The gain of the gates is two.

JovianPyx in chat pointed out that the gate transfer functions should be sigmoidal, which I feel is correct. In fact, you can visualize the transfer functions. They are plateaus with smooth sigmoidal transitions between them. This represents a two-dimentional distortion function so the sound should have some of the audio qualities of guitar distortion pedals. cool, huh?

One of my favorite subjects... Two parts mentioned in previous posts are the 4069 (or 4069UB) and 4049. Both ICs are hex inverters.

The 4049 was designed as a way to drive TTL from CMOS. As such, it has different transistors in it's output "totem pole" such that it can sink much more current than it sources. There is also an unbuffered version of the 4049 (4049UB), but it also has the same asymmetrical output transistor configuration. When used in a linear circuit, this will cause the distortion to be different for the negative and positive half cycles of waveforms. That can be good or bad depending on exactly what you want.

The 4069UB is different in that it has symmetrical output transistors such that sink and source current is the same.

Note that both 4069UB and 4049UB will distort an input signal when used as a linear amplifier because the gain of the little two transistor amplifier is not consistent with respect to the input voltage. When the input voltage is (Vdd-Vss)/2, the gain is highest. As the input voltage moves away from this point, the gain reduces. This sigmoid gain transfer function causes some distortion that is similar to the way vacuum tubes distort. I've personally used this distortion to make a triangle to "sine" converter. I put sine in quotes because it's not a precise sine, but to my ears, it's very close.

While standard CMOS 4xxx series parts are spec'd at 15 volts power supply, most are also spec'd at 18 volts absolute maximum. (see the datasheet for the part per manufacturer to make sure). You can use 4xxx parts with a dual supply, but be careful, for example, if you try to power from +15 and -15, the IC will very likely release the magic smoke. I mention dual supply because most modular synths have them and it's convenient when you're trying to make a linear CMOS amplifier emulate an opamp - you don't need to make a virtual ground with dual supply, but as I mentioned, the maximum ratings should be followed if you expect reliability. Because of the supply voltage limitation, if you want to use a dual supply it's best to make a separate one for the CMOS stuff. +6 and -6 is easy enough and one can mess with diodes to push those a bit higher (assuming fixed voltage regulators). I've had very good results with +5 and -5. Because many mfrs spec absolute maximum at 18 volts, you can try +9 and -9, but at your own risk.

Note also that CMOS that is run in linear amplifier mode tends to draw a bit of current, more than an opamp. The CMOS gate will draw the most current when the input voltage is at (Vdd-Vss)/2 which is often when the system is at rest. Because of this, CMOS linear amps can run warm or even hot. Others have suggested to me that it's wise not to use more than 3 of the 6 gates in a package as linear amplifiers to keep the IC from heating up too much.

Last but not least, I'd like to mention the 4007. It's internal structure is somewhat like the 4069UB in that it's transistors are symmetrical and sink as much current as they source. This is one of my favorite ICs because it is really a kind of CMOS transistor array. It can become 3 linear amplifiers or some of the transistors can be used as single NMOS or single PMOS transistors. Lots of interesting things can be done with these and there are some ideas in some of the datasheets. I've not seen linear amplification mentioned in the datasheets, but I know it works because I've used them that way.

Also, take note of the part numbers of 4049 and 4069. I believe that 4069 is the same as 4069UB. The UB means "unbuffered". 4049 however has two versions, one is buffered, the other, 4049UB is unbuffered. The unbuffered gates are just two MOS transistors in a totem pole with the gates connected together to form the input. Output is taken from the connection between the two MOS transistors. The difference is the presence of extra buffer transistors which drastically increase the gain. The buffered 4049 has 6 transistors per inverter gate, basically, it is 3 inverter stages cascaded. It is my opinion that the UB or unbuffered parts make better linear action than the buffered parts - but your milage may vary._________________FPGA, dsPIC and Fatman Synth Stuff

Time flies like a banana.Fruit flies when you're having fun.BTW, Do these genes make my ass look fat?corruptio optimi pessima

I've been looking at this a little bit over the last couple days. I can't understand how the 4066 is working as the cuttoff control for the filter. There is an HF oscillator on the switch control? How does that work?

I'd also like to see some of the circuits you mention in schematic form inventor. NAND gate in linear mode is interesting to me._________________∆ A. MAGIC PULSEWAVE ELECTRONICS ∆

I'll take a stab - looking at the MXR env filt schematic, gate A1D (which is NOT running in linear mode, so will have an output of either logic high or logic low) drives the 4066 control inputs.. It appears to be fed by the sum of the output of two circuits, the line of gates below the filter (the envelope generator) and a little "ring" of gates below that. That ring of gates looks to me like an oscillator, probably pseudo sine or triangle. This would mean that at least for part of the time, the gate A1D outputs a rectangular wave with duty cycle controlled by the envelope generator - this is then fed to the control inputs of the 4066 gates controlling the filter. The on-off-on-off action will control the cutoff because the effective input resistance to each of the integrators varies with the duty cycle of the rectangular wave created by the little oscillator. The input resistance regulates the charging current into the integrating capacitor, thus the cutoff frequency is controlled by the duty cycle applied to the 4066 control inputs. I didn't calculate the oscillator frequency, but I'll bet it's above human hearing, so it won't be audible. It looks to me like the envelope changes the switching threshold of gate A1D and that is what changes the duty cycle the gate A1D sees.

This technique of controlling a filter is known as "switched capacitor".

Note that this analysis was done without owning one, without having heard one and without being able to probe the circuit with an oscilloscope. If this is wrong - someone please correct..._________________FPGA, dsPIC and Fatman Synth Stuff

Time flies like a banana.Fruit flies when you're having fun.BTW, Do these genes make my ass look fat?corruptio optimi pessima

I'd like to take a moment to thank each of you for your contributions to this thread, it has generated more interest than I imagined and more tech than I can understand without extensive study. Also thanks to all our lurkers for reading our aimless jaberwocky. Some thoughts about linear CMOS:

You can make artificial intelligence with it! I realized this while rethinking JovianPyx's description of the NAND and NOR transfer functions. They are basically shaped into four quadrants, each with a logic value of 0 or 1 and a sigmoidal transition between these regions. Imagine a 3D plot with four plateaus and smooth hilly terrain between.

Well, those transfer functions are basically just fuzzy logic control surfaces. This topic is also well known as a google search produced entire books on the subject!

Going in another direction, we have a sigmoidal transfer function which spells neural net to me. With multiple inputs and a sigmoidal decider, we have a neuron.

Also, since there is a request for a schematic of the NAND amplifier, I'll go run off and draw one up right now. Be back soon.

Here is the schematic of the NAND and NOR linear CMOS amplifiers. I put an inverter amplifier at the top for reference. Note that dual feedback provides for adjusting the transfer function by weighting the inputs differently. Also the input caps perform a high-pass function (and dc blocking as well), and can be removed for DC operation. The feedback caps perform a low-pass function.

One way to think of these amps is that they are like opamps with two inverting inputs, no non-inverting input, and self-biasing. Or you could think of them as having a non-inverting input that was referenced to vdd/2. whatever.

Also you can use any number of inputs as long as there is inversion you're fine. You can also use some tangled logic mess if you wish, just as long as the inversion works out properly (and I'm not sure how that would work for complex logic expressions).

On a related note, I am using these NAND and NOR amps in my Lunetta challenge project, we will hear how well that works.

A word of caution from a veteran IC designer. CMOS logic is standardized only in function, and to some degree in the specs. But CMOS logic does not have linear specs. The fact that they can be used in linear mode is a fortunate accident, so to speak.

It is possible that a given CMOS logic chip will not even have the same internal circuit as one from another company with the same number, for example, 4011B. There are many ways to skin a cat. Also, the circuit diagrams of the internal circuits of ICs that sometimes appear on application notes or spec sheets are not guaranteed to be accurate. They are often simplified for illustrative purposes.

Thus, if you analyze the linear characteristics of one part, it may not correspond to one from another company, or even from the same company. This is especially true if you use the device in the linear mode for which there are no specs, of factory test programs.

Just keep this in mind when you experiment. It could get frustrating when you have a neat circuit that works just the way you want, but it won't work when you swap out a device. Thus, I suggest keep your circuits simple. If you want to design linear (analog) circuits, it might be best to use parts intended for that purpose.

PS: This is also true of linear ICs. Most reputable equipment manufacturers will independently test incoming parts to be sure they meet their criteria for use, before they install them on their boards._________________--Howard
my music and other stuff

I can echo a tiny bit of what you expressed - a friend of mine, Rene Schmitz, had designed a nice sawtooth oscillator using 3 gates of a 4069UB. He posted his schematic, so I tried to build the circuit, but it went all crazy with weird "oscillations" (hash) in the waveform that was horribly wrong. Emails back and forth revealed that I was using the exact same manufacturer, but I was using different gates within the device than Rene did for different bits of that oscillator. When I got is pin-mapping and made mine identical to his, it worked correctly. Apparently, he had gotten lucky enough to stumble upon the pin connections that worked properly, but didn't include the pin numbers on his schematic.

So as an addendum to what mosc just wrote, it might be nice that if we make linear circuits with CMOS, we should probably document the manufacturer of the chips we use and the pins that are used for each function so that others trying to replicate these circuits have a better chance of success._________________FPGA, dsPIC and Fatman Synth Stuff

Time flies like a banana.Fruit flies when you're having fun.BTW, Do these genes make my ass look fat?corruptio optimi pessima

Good comment. I can appreciate your frustration. That's why I posted this heads up. If you have a tricky logic circuit, sometimes you can run into similar problems.

When you start designing very fancy analog circuits, the capacitors can be a problem too. 20 pf is an approximation, you know. Rob Hordijk has some fascinating horror stories about capacitors. He has a special cache of caps that are made for medical electronics he uses.

Yes, I designed everything from CMOS Op Amps for very low voltage applications to 32 bit floating point DSPs. At one time I was the expert on CMOS op amps with very good power supply rejection ratios. Not anymore. The DSP work was as part of a huge team. I was also involved in a lot of early experimental HDTV circuits. I'm retired from that now. electro-music.com is more fun...

Wow I found an equation graphing application in the Utilities folder under Applications on my Mac and it's nice. I used it to create the attached image of a NOR transfer function. It is a graph of z=1/(1+e^(10x)+e^(10y)), which is not normalized or biased quite properly but it does show the general shape.

Notice the four quadrant plateaus with sigmoidal transitions between them. Notice the logic equation is such that the output is one only when the inputs are both zero. Notice how the function is kind of a mix of logic and analog, or could be viewed as a fuzzy control surface or a neural net transfer function.

While awaiting my Goldmine bag o' chips, I have been experimenting with and trying to understand the linear CMOS and FET world. As usual, I learn a little and make a few mistakes and end up with something interesting.

Here is a schematic of something not entirely unlike a VCA. I drew it as an inverter, but it seems to work with all the boolean 4000-series logic chips I have. More inputs and other gates on the chip lead to more unpredictable fun.

Feed in an analog audio signal and a slow triangle LFO CV and you see the audio signal fade up and fade down, albeit usually with a some distortion of the analog input signal. Strangely, in different situations I saw different kinds of results making Audio Output 1 better sometimes and Audio Output 2 better other times. But Audio Output 2 tended to be more square off--but not always.

I guess the FET transistors inside the chip vary between pulling down (and squelching) the audio and passing it as-is, controlled by the logic input pin.

With unpredictabilities of linear CMOS, I should mention I fed this the output from standard 40106/4093 oscillators, from PICs, and from buffered LM324 pseudo-triangle LFOs. I outputted into a voltage divider, then through a capacitor, into my mixer.

In contrast: The YAVCO VCO uses a CV input to the power pin on an oscillator and the result is a change in frequency, thus it is FM. The Hex VCA on the 4049UB uses inputs on each side of an inverter and gets its output through Vcc and GND connected together.

Please comment with other similar circuits and other variations on these ideas.

Take a look at the 4007 IC. The internal schematic (remembering the caveat posted by mosc regarding these) would allow using 2 of the gates separately as weird VCAs. If you do this kind of thing with the 4049 (for example), you have only one audio input and 6 CV inputs.

The schematic below (which takes the same idea as you posted and creates two VCAs with one IC) does not show the parasitic static protection diodes and you should know that some of them aren't used and thus disables some of the protection. However, I've done things like this before and hadn't seen problems. I don't show any input resistors here, you can add them where needed. This is just a sketch of a basic idea - I have not tried it, but I think it will work.

Get a copy of the Texas Instruments datasheet for the 4007, the internal schematic with the diodes is shown in that document along with other goodies.

A note about this kind of VCA - it will distort. That may not be bad, but it should be understood. The reason is that the gain of the little 2 transistor amps is not constant. Gain is highest when the input is (Vdd-Vss)/2 and reduces as the input gets higher or lower than that. Noting that the input is a variable voltage applied as Vdd, the distortion will change as the signal changes. It won't matter much if the input is a rectangular waveform and the output may sound just like the input in that case. If the input is some other waveform, it will definately be distorted.

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