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Contiguous Allocation Main memory usually into two partitions: –Resident operating system, usually held in low memory with interrupt vector –User processes then held in high memory Relocation registers used to protect user processes from each other, and from changing operating-system code and data –Base register contains value of smallest physical address –Limit register contains range of logical addresses – each logical address must be less than the limit register –MMU maps logical address dynamically

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Dynamic Storage-Allocation Problem First-fit: Allocate the first hole that is big enough Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless ordered by size –Produces the smallest leftover hole Worst-fit: Allocate the largest hole; must also search entire list –Produces the largest leftover hole How to satisfy a request of size n from a list of free holes First-fit and best-fit better than worst-fit in terms of speed and storage utilization

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Fragmentation External Fragmentation – total memory space exists to satisfy a request, but it is not contiguous Internal Fragmentation – allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used Reduce external fragmentation by compaction –Shuffle memory contents to place all free memory together in one large block –Compaction is possible only if relocation is dynamic, and is done at execution time –I/O problem Latch job in memory while it is involved in I/O Do I/O only into OS buffers

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Paging Logical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available Divide physical memory into fixed-sized blocks called frames (size is power of 2, between 512 bytes and 8,192 bytes) Divide logical memory into blocks of same size called pages Keep track of all free frames To run a program of size n pages, need to find n free frames and load program Set up a page table to translate logical to physical addresses Internal fragmentation

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Address Translation Scheme Address generated by CPU is divided into: –Page number (p) – used as an index into a page table which contains base address of each page in physical memory –Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit –For given logical address space 2 m and page size 2 n page number page offset p d m - n n

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Paging Hardware

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Paging Model of Logical and Physical Memory

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Paging Example 32-byte memory and 4-byte pages

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Free Frames Before allocation After allocation

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Implementation of Page Table Page table is kept in main memory Page-table base register (PTBR) points to the page table Page-table length register (PRLR) indicates size of the page table In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction. The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs) Some TLBs store address-space identifiers (ASIDs) in each TLB entry – uniquely identifies each process to provide address-space protection for that process

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Memory Protection Memory protection implemented by associating protection bit with each frame Valid-invalid bit attached to each entry in the page table: –valid indicates that the associated page is in the process logical address space, and is thus a legal page –invalid indicates that the page is not in the process logical address space

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Valid (v) or Invalid (i) Bit In A Page Table

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Shared Pages Shared code –One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems). –Shared code must appear in same location in the logical address space of all processes Private code and data –Each process keeps a separate copy of the code and data –The pages for the private code and data can appear anywhere in the logical address space

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Two-Level Paging Example A logical address (on 32-bit machine with 1K page size) is divided into: –a page number consisting of 22 bits –a page offset consisting of 10 bits Since the page table is paged, the page number is further divided into: –a 12-bit page number –a 10-bit page offset Thus, a logical address is as follows: where p i is an index into the outer page table, and p 2 is the displacement within the page of the outer page table page number page offset pipi p2p2 d 12 10

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Address-Translation Scheme

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Three-level Paging Scheme

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Hashed Page Tables Common in address spaces > 32 bits The virtual page number is hashed into a page table –This page table contains a chain of elements hashing to the same location Virtual page numbers are compared in this chain searching for a match –If a match is found, the corresponding physical frame is extracted

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Hashed Page Table

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Inverted Page Table One entry for each real page of memory Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs Use hash table to limit the search to one or at most a few page-table entries

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Memory-management scheme that supports user view of memory A program is a collection of segments –A segment is a logical unit such as: main program procedure function method object local variables, global variables common block stack symbol table arrays