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Abstract:

The gate of the access transistor of a 1 transistor 1 resistor (1T1R)
type RRAM cell is biased relative to the source of the access transistor
using a current mirror. Under the influence of a voltage applied across
the 1T1R cell (e.g., via the bit line), the RRAM memory element switches
from a higher resistance to a lower resistance. As the RRAM memory
element switches from the higher resistance to the lower resistance, the
current through the RRAM cell switches from being substantially
determined by the higher resistance of the RRAM device (while the access
transistor is operating in the linear region) to being substantially
determined by the saturation region operating point of the access
transistor.

Claims:

1. A method of changing a state of a resistive change memory element of
an integrated circuit device, the method comprising: generating a
reference current; biasing an access transistor coupled to the resistive
change memory element to establish a bias of the access transistor; and,
based on the bias of the access transistor, using a current mirror to
establish from the reference current, a current that flows through the
resistive change memory element.

2. The method of claim 1, wherein the current mirror comprises a
transistor receiving the reference current to generate the bias of the
access transistor.

3. The method of claim 2, wherein the resistive change memory element is
part of a resistive change memory cell that is part of an array of
resistive change memory cells addressable by a plurality of bit lines and
a plurality of word lines, a first node of the resistive change memory
cell is connected to a bit line of the array, a second node of the
resistive change memory cell is connected to a common source line of the
array, and a third node of the resistive change memory cell is connected
to a word line of the array.

4. The method of claim 3, wherein the access transistor is a field-effect
transistor having a source, a gate, and a drain, the gate being connected
to the bit line bit line of the array and the source is connected to the
common source line of the array.

5. The method of claim 4, wherein the bias of the access transistor
determines a second voltage difference between the source and the gate,
the second voltage difference determining the current passing through the
resistive change memory element.

6. The method of claim 5, wherein the resistive change memory element is
disposed in series with the drain and the source of the access transistor
and between the first node and the second node.

7. A method of performing a memory operation in an integrated circuit
memory device to change a state of a resistive change memory element in
an array having a plurality of bit lines and a plurality of word lines,
comprising: providing a first voltage on a bit line of the plurality of
bit lines to change a state of a resistive change memory cell; and,
providing a second voltage on a word line of the plurality of word lines,
the second voltage to bias an access transistor using a current mirror to
establish, from a reference current a current that flows through the
resistive change memory element.

8. The method of claim 7, wherein a voltage across the resistive change
memory element changes a resistance of the resistive change memory
element from a first resistance to a second resistance.

9. The method of claim 8, wherein the first resistance is greater than
the second resistance.

10. The method of claim 7, wherein the second voltage determines a gate
to source voltage of a field-effect transistor (FET) of the resistive
change memory cell.

11. The method of claim 10, wherein the current flows from the bitline
through the resistive change memory element and a channel of the FET
while a resistance of the resistive change memory element is changed.

12. The method of claim 11, wherein the current is limited to the
reference current by the FET in response to the gate to source voltage.

13. The method of claim 10, wherein the gate to source voltage is
determined by a diode-connected FET.

14. The method of claim 13, wherein the FET and the diode-connected FET
have matched gate lengths.

15. An integrated circuit, comprising: at least one memory cell having an
access transistor coupled to a resistive change memory element; a
reference current generator; and, a word line driver circuit to receive a
reference current from the reference current generator, to generate a
bias, and to bias the access transistor such that the reference current
is mirrored as a current that flows through the access transistor.

16. The method of claim 15, wherein a resistance of the resistive change
memory element of the resistive change memory cell changes from a first
resistance to a second resistance.

17. The method of claim 16, wherein the first resistance is greater than
the second resistance.

18. The integrated circuit of claim 17, wherein the word line driver
circuit is to bias the access transistor by setting a voltage on a word
line connected to a gate of the access transistor.

19. The integrated circuit of claim 17, wherein the resistive change
memory element is connected in series with the access transistor to
receive a programming voltage across the resistive change memory element
in response to the access transistor turning on to an amount controlled
by the bias generated by the word line driver circuit.

20. The integrated circuit of claim 18, wherein a bit line is connected
to the resistive change memory element to supply a program voltage used
to change the resistive change memory element, and a current flowing
through the resistive change memory element is limited to a peak current
by the biasing of the access transistor by the word line driver circuit.

21-36. (canceled)

Description:

TECHNICAL FIELD

[0001] The present disclosure relates to techniques and circuits for
setting a state of a resistively switched memory device. More
specifically, but not exclusively, the present disclosure relates to
controlling the current through a resistively switched memory device as
it is switched from a high resistance state to a lower resistance state.

BACKGROUND

[0002] Several types of non-volatile memory have been developed that rely
on resistive memory elements that change resistance under certain
conditions. This general category of memory may be referred to as
resistive change memory (a.k.a., resistive random access memory--RRAM).
An RRAM memory element represents stored information as a high resistance
state and one or more distinct low resistance states. A dielectric, which
is normally insulating, can be made to conduct through the formation of a
conducting filament or path. This filament is formed as a result of the
application of a sufficiently high voltage (i.e., electric field).

[0003] Depending on the type of RRAM memory element, the conduction path
formation can arise from different mechanisms. These mechanisms include
defect modification, metal migration, ion migration, etc. Forming the
filament is generally referred to as "setting" the RRAM memory element.
Breaking the filament, usually by applying an appropriately high voltage
of an opposite polarity, results in the RRAM memory element resuming a
high resistance. This process is generally referred to as "resetting" the
RRAM memory element. The RRAM memory element may be "set" and "reset"
many times by appropriately applied voltages.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] FIG. 1 is a schematic diagram illustrating an RRAM circuit.

[0005]FIG. 2 is a flowchart illustrating a method of limiting RRAM
current.

[0007]FIG. 4 is a flowchart illustrating a method of changing a state of
an RRAM cell in an array.

[0008] FIG. 5 is a block diagram illustrating an RRAM memory array.

[0009]FIG. 6 is a flowchart illustrating a method of limiting current
while changing a state of an RRAM device.

[0010]FIG. 7 is a block diagram illustrating an RRAM memory detailing a
word line driver.

[0011] FIG. 8 is a flowchart illustrating a method of programming a
plurality of RRAM cells.

[0012]FIG. 9 is a graph of various currents and voltages associated with
limiting current while changing of a state of an RRAM cell.

[0013] FIG. 10 is a block diagram of a computer system.

DETAILED DESCRIPTION

[0014] The process of "setting" an RRAM memory element involves applying a
sufficiently high voltage (i.e., electric field) across the RRAM memory
element. This electric field causes a dramatic reduction in the
resistance of the RRAM memory element. This reduction in the resistance
of the RRAM memory element remains until the device is "reset" by the
application of another sufficiently high voltage--usually of opposite
polarity. In some implementations, RRAM memory elements may be paired
with an access transistor in an RRAM cell. The access transistor
selectively allows current to be passed through, and voltage applied to,
the RRAM memory element so that its state may be determined and/or
changed. These cells may be arranged in an array so that a particular
RRAM cell in the array may be set, reset, or read. Typically, a column of
the array is accessed (or controlled) via a conductive path (or wire)
that is referred to as a bit line. A row of the array is accessed (or
controlled) via a conductive path (or wire) that is referred to a word
line.

[0015] In an embodiment, during the process of "setting" a 1-transistor
1-resistor (1T1R) type RRAM cell, the access transistor is biased to act
as a current limiter. The gate of the access transistor, which is
typically controlled by a word line, is biased relative to the source of
the access transistor using a current mirror. This current mirror may
comprise a diode connected transistor as a master transistor of the
current mirror and the access transistor of an RRAM cell as the slave
transistor of the current mirror. The access transistor, as the slave
transistor of the current mirror, limits the current through the RRAM
device to approximately the reference current through the master
transistor of the current mirror. Under the influence of a voltage
applied across the 1T1R cell (e.g., via the bit line), the RRAM memory
element switches from a higher resistance to a lower resistance. As the
RRAM memory element switches from the higher resistance to the lower
resistance, the current through the RRAM cell switches from being
substantially determined by the higher resistance of the RRAM device
(while the access transistor is operating in the linear region) to being
substantially determined by the saturation region operating point of the
access transistor.

[0016] In other words, in an embodiment, to "set" an RRAM cell, a
programming voltage is applied across the RRAM memory element and an
access transistor. At the same time, a gate-to-source bias voltage is
applied to the access transistor. This gate-to-source bias voltage may be
generated from a reference supplied to a circuit that includes the access
transistor as the slave transistor of a current mirror. Since the access
transistor is in a relatively low impedance conductive state in response
to being biased, the programming voltage is initially almost entirely
across the RRAM memory element. Thus, the current through the cell is
substantially determined by the resistance of the RRAM memory element.
The current through the cell is substantially determined by the
resistance of the RRAM memory element because the drain-to-source
resistance of the biased access transistor is much less than the
resistance of the unset RRAM memory element.

[0017] The voltage across the RRAM memory element causes the RRAM memory
element, after some period of time, to decrease in resistance. This
resulting decrease in resistance causes an increase in current through
both the RRAM memory element and the access transistor. At some point,
the decreasing resistance of the RRAM memory element and the increasing
current through the access transistor result in a drain-to-source voltage
of the access transistor that places the access transistor in the
saturation region of operation.

[0018] In the saturation region of operation, the current through the
access transistor, and thus the RRAM memory element, is substantially
determined by the gate-to-source voltage of the access transistor. Thus,
the current through the RRAM memory element is limited by the current
mirror circuit that includes the access transistor. The current is
limited to approximately a predetermined amount. Limiting the current
through the RRAM memory element also reduces the voltage across the RRAM
memory element. In an embodiment, the limited current through the RRAM
memory element results in a voltage across the RRAM memory element that
is low enough to substantially stop further reductions in the resistance
of the RRAM memory element.

[0019] FIG. 1 is a schematic diagram illustrating an RRAM circuit. In FIG.
1, RRAM circuit 100 comprises RRAM cell 110, diode connected transistor
104, and current reference 106. RRAM cell 110 comprises access transistor
101 and RRAM memory element 102. The sources of transistor 104 and access
transistor 101 are connected to a common node (node SL). The drain of
access transistor 101 is connected to a first terminal of RRAM memory
element 102 (node CN). A second terminal of RRAM memory element 102 is
connected to a bit line (node BL).

[0020] One type of RRAM memory element comprises a solid electrolyte such
as Germanium-Selenide-Silver (GeSeAg). To "set" this type of resistive
change memory element, an electric field is applied across the device.
This electric field (i.e., voltage) causes metal ions from an electrode
on one side of the device to migrate and form at least one filament
across the device. This filament may be referred to in some literature as
a channel. The filament reduces the cell resistance by providing a more
conductive path across the device than existed prior to the device being
set. To "reset" the device, an electric field with opposite polarity is
applied. This pulls the metal ions back toward the electrode. As a
result, the filament is broken and the resistance of the device is
increased.

[0021] The gates of access transistor 101 and transistor 104 are connected
to the drain of transistor 104. This node may be a word line (node WL).
The drain of transistor 104 is also connected to receive the current
flowing through current reference 106. Thus, transistor 104 and access
transistor 101 form a current mirror. A current mirror is a circuit
designed to copy a current through one active device, acting as a master
(e.g., transistor 104), by controlling a second active device, acting as
a slave (e.g., access transistor 101), thus keeping the current through
the second device constant regardless of loading. The current mirroring
operation may be dependent upon the second device operating in the
appropriate region of operation, for example, the saturation region of a
field-effect transistor (FET). It should be understood that current
mirrors may be constructed or configured from other types of devices,
such as bipolar junction transistors, etc.

[0022] Before being set, RRAM memory element 102 typically has a large
resistance. This resistance may be on the order of 106-108 ohms
To set RRAM memory element (i.e., to reduce its resistance to a value on
the order of 103-105 ohms), a set voltage is applied to the bit
line, BL. This set voltage may be referred to as VSET. For the
purposes of the following discussion, the node SL will be used as the
reference voltage (i.e., signal ground). Thus, VSET is referenced to
the node SL. The voltage across RRAM memory element 102 is determined by
the drain-to-source voltage of access transistor 101. In other words,
ΔV102=VBL-VDS, 101. Therefore, the current through
RRAM memory element 102 (and also the drain current of access transistor
101) is:

ICELL=ΔV102/R102.

[0023] To illustrate the set operation, assume that WL and BL are
initially at 0V (relative to SL). Thus, node CN is also at 0V. The word
line is then enabled by turning on current reference 106. This brings WL
slightly above the threshold voltage of transistor 104 (VTN). The
bit line (BL) is then transitioned from 0V to VSET. Because
R102 is initially very large relative to the drain-to-source
resistance of access transistor 101 when access transistor 101 is
operating in the linear region, this increases the voltage across RRAM
element 102 to approximately VSET. This approximately VSET
voltage across RRAM element 102 causes the resistance of RRAM memory
element 102 (i.e., R102) to drop by several orders of magnitude as
RRAM memory element transitions to the set state. As R102 drops, the
current through RRAM memory element 102, ICELL, (and thus the drain
current of access transistor 101) increases. At some point as ICELL
increases, access transistor 101 enters the saturation region of
operation. When access transistor 101 is in the saturation region of
operation, ICELL is limited to approximately the current through
current reference 106 (I106).

[0024] With ICELL limited, the voltage across RRAM memory element 102
approaches I106*R102 (i.e.,
ΔV102≈I106*R102). Since VSET is
typically fixed during this operation, the drain-to-source voltage of
access transistor 101, VDS, 101, increases if R102 continues to
decrease. The amount VDS, 101 increases is based on the resistance
of R102 (which may continue to decrease) and ICELL. By
Kirchhoff's voltage law, increases in VDS, 101 correspond to an
equivalent reduction in ΔV102. Reductions in ΔV102
slow or stop the decrease in R102 until equilibrium is reached.
Thus, the set operation is self-limiting and is controlled by I106.
In an embodiment, the equilibrium current through RRAM memory element 102
may be controlled to be a predetermined multiple (e.g., 1:1, 2.5:1, 1:3,
etc.) of current reference 106 by designing the width-to-length ratios of
access transistor 101 and transistor 104 to be appropriate multiples of
each other. For operations other than, for example, the set operation
described above, the WL may be asserted to a high logical level voltage
to turn the access transistor 101 to a fully on state such that
ICELL is not limited as in the set state described above. Such
operations include for example, read operations or write operations that
reset the cell, in the event that set and reset operations are performed
as separate operations. In another embodiment, the wordline current
limiting effect (for example as in the ICELL generation approach
described above) may be used during a read operation to limit the maximum
read current for a cell. This may provide for benefits such as reducing
read noise, preventing read disturb, or allowing more cells to be read
simultaneously.

[0025] Because the limiting of the set current is effectively done inside
RRAM cell 110, the slowing and stopping of further resistance reductions
in RRAM memory element 102 may be very fast. This slowing and stopping
may be very fast because it is independent of bit line resistance and
capacitance. This may enable the use of much larger memory arrays thereby
saving die area. It may also enable in much better control (i.e.,
tolerances) of the final set resistance of the RRAM memory elements 102
in an array.

[0026] The preceding example was discussed in terms of the word line being
biased before the bit line was biased to VSET. However, it should be
noted that in an embodiment the bit line may be biased to VSET
before (or simultaneously with) the word line being biased to slightly
above the threshold voltage of transistor 104.

[0027] In FIG. 1, access transistor 101 is shown as an n-channel
field-effect transistor (NFET). It should be readily understood that in
other embodiments, access transistor 101 may be a p-channel field-effect
transistor (PFET). In this case, transistor 104 may also be a PFET
transistor.

[0028]FIG. 2 is a flowchart illustrating a method of limiting RRAM
current. The steps illustrated in FIG. 2 may be performed by (or on) one
or more elements of RRAM circuit 100. A reference current is generated
(202). For example, current reference 106 may be turned on (or gated
through transistor 104) to provide a reference current I106. An
access transistor that is coupled to a resistive change memory element is
biased (204). For example, when reference current I106 is provided
to transistor 104, transistor 104 may cause WL to be brought above the
threshold voltage of transistor 104. Because the gate of access
transistor 101 is also connected to WL, and the sources of transistor 104
and access transistor 101 are both connected to SL, causing WL to be
brought above the threshold voltage of transistor 104 biases access
transistor 101 to above the threshold voltage of transistor 104.

[0029] Based on the biasing, a current mirror is used to establish from
the reference current a current that flows through the resistive change
memory element (206). For example, transistor 104 and access transistor
101 form a current mirror. The current through current reference 106
(i.e., I106), which also flows through transistor 104, establishes
the biasing of access transistor 101. As described previously, when the
resistance of RRAM memory element drops as it is being set, the current
through RRAM memory element 102, ICELL, (and thus the drain current
of access transistor 101) increases. At some point as ICELL
increases, access transistor 101 enters the saturation region of
operation. When access transistor 101 is in the saturation region of
operation, ICELL is limited to approximately the current through
current reference 106 (I106) by the biasing of access transistor
101. This biasing is established by the current mirror configuration
formed by transistor 104 and access transistor 101.

[0030]FIG. 3 is a block diagram illustrating an RRAM memory array. In
FIG. 3, RRAM memory array 300 comprises RRAM cell array 320, bit line
control and bias 330, word line control and bias 340, and current
reference 306. RRAM cell array 320 is comprised of a plurality of RRAM
cells 310-313 arranged in rows and columns. In FIG. 3, RRAM cells 310 and
311 are shown in the top row. RRAM cells 312 and 313 are shown in the
next row. RRAM cells 310 and 312 are shown in the leftmost column. RRAM
cells 311 and 313 are shown in the next column to the right. Current
reference 306 is coupled to word line control and bias 340.

[0031] Each RRAM cell 310-313 comprises a resistive change memory element
302 and an access transistor 301. The gate of each access transistor 301
in a row is connected to a word line. The source of each access
transistor 301 is connected to a common source line. The common source
lines of each row are also connected to word line control and bias 340. A
first terminal of each resistive change memory element 302 of each RRAM
cell 310-313 is connected to a bit line. A second terminal of each
resistive change memory element 302 is connected to the drain of the
access transistor 301 for that RRAM cell 310-313.

[0032] Each row of RRAM cell array 320 is connected to the same word line.
I.e., in FIG. 3, RRAM cells 310 and 311 are connected to the same word
line. RRAM cells 312 and 313 are connected to a word line, which is a
different word line than is connected to RRAM cells 310-311. The word
lines of RRAM cell array 320 are coupled to word line control and bias
340. Each column of RRAM cell array 320 is connected to the same bit
line. I.e., in FIG. 3, RRAM cells 310 and 312 are connected to the same
bit line. RRAM cells 311 and 313 are connected to a bit line, which is a
different bit line than is connected to RRAM cells 310-311. The bit lines
of RRAM cell array 320 are coupled to bit line control and bias 330.
Thus, each RRAM cell 310-313 is uniquely addressable in RRAM array 320 by
a combination of activating a word line to access all of the RRAM cells
of a row (e.g., RRAM cells 310-311) and to read/write data to a
particular RRAM cell of that row via an individual bit line (e.g., RRAM
cell 310 via the leftmost bit line in FIG. 3).

[0033] To set a particular RRAM cell (for example, RRAM cell 310), the
word line and bit line combination that are unique to that cell are
initially set at 0V (as referenced to the sources of access transistor
301 in each RRAM cell 310-313) by word line control and bias 340 and bit
line control and bias 330, respectively. Thus, the drain node of the
access transistor 301 for that cell is also at 0V. Word line control and
bias 340 brings the word line slightly above the threshold voltage of the
access transistor 301. Word line control and bias may generate this
voltage using a current mirror to mirror current reference 306.

[0034] The bit lines for the selected cells are then transitioned from 0V
to a potential that is high enough to cause resistive change memory
element 302 to transition from a high resistance state to a low
resistance state (e.g., VSET). The bit lines for non-selected cells
are kept at 0V. Thus, the bit lines, by being either at a high potential
or at 0V, determine which cells connected to the selected word line are
to simultaneously set.

[0035] Because the resistance of resistive change memory element 302 is
initially very large relative to the drain-to-source resistance of the
biased access transistor 301, the voltage across resistive change memory
element 302 transitions to approximately the voltage on the bit line.
This voltage across resistive change memory element 302 causes the
resistance of resistive change memory element 302 to drop by as much as
several orders of magnitude as resistive change memory element 302
transitions to the set state. In an embodiment, the voltage across
resistive change memory element 302 may be controlled to cause the
resistance of resistive change memory element 302 to drop by an amount
that is smaller than several orders of magnitude. As the resistance of
resistive change memory element 302 drops, the current through resistive
change memory element 302 increases. At some point as this current
increases, access transistor 301 enters the saturation region of
operation. When access transistor 301 is in the saturation region of
operation, the current flowing from the bit line, through resistive
change memory element 302 and access transistor 301 may be limited to
approximately the current through current reference 306 by the bias
output by word line control and bias 340.

[0036] With the current through the RRAM cell 310-313 limited, the voltage
across resistive change memory element 302 approaches a value determined
by the bias of access transistor 301. Since the voltage on the bit line
is typically fixed during this operation, the drain-to-source voltage of
access transistor 301 increases if the resistance of resistive change
memory element 302 continues to decrease. The amount the drain-to-source
voltage of access transistor 301 increases is based on the resistance of
the resistive change memory element 302. By Kirchhoff's voltage law,
increases in the drain-to-source voltage of access transistor 301
correspond to decreases in the voltage across resistive change memory
element 302. Reducing the voltage across of resistive change memory
element 302 slows or stops the decrease in the resistance of resistive
change memory element 302 until equilibrium is reached. Thus, the set
operation is self-limiting and is controlled by the voltage on the word
line. Since the voltage on the word line may be set by word line control
and bias 340 based on current reference 306, the equilibrium current
through the RRAM cell 310-313 being set may be controlled to be a
predetermined multiple (e.g., 1:1, 2.5:1, 1:3, etc.) of current reference
306.

[0037] The preceding example was discussed in terms of the word line being
biased before the bit line was biased to a high potential. However, it
should be noted that in an embodiment the bit line may be biased to
before (or simultaneously with) the word line being biased.

[0038]FIG. 4 is a flowchart illustrating a method of changing a state of
an RRAM cell in an array. The steps illustrated in FIG. 4 may be
performed by (or on) one or more elements of RRAM circuit 100 and/or RRAM
memory 300. A first voltage is provided on a bit line to change a state
of a resistive change memory cell (402). For example, bit line control
and bias 330 may transition a bit line to a potential that is high enough
to cause resistive change memory element 302 to transition from a high
resistance state to a low resistance state.

[0039] A second voltage is established from a reference current using a
current mirror (404). For example, word line control and bias 340 may
generate a word line bias voltage using a current mirror configuration
that receives current reference 306. The second voltage is provided to a
word line to bias an access transistor (406). For example, word line
control and bias 330 may provide the word line bias voltage between a
word line and a common source line. This word line bias voltage may bias
one or more access transistors 301 of a row in RRAM array 320 such that
an equilibrium current through an RRAM cell 310-313 being set by the
first voltage may be controlled to be a predetermined multiple (e.g.,
1:1, 2.5:1, 1:3, etc.) of current reference 306.

[0041] Similar to RRAM memory 300, each RRAM cell 510-513 comprises a
resistive change memory element 502 and an access transistor 501. The
gate of each access transistor 501 in a row is connected to a word line.
Each word line is coupled to word line control/drivers 540. A first
terminal of each resistive change memory element 502 is connected to a
bit line of RRAM cell array 520. A second terminal of each resistive
change memory element 502 is connected to the drain of the access
transistor 501 for that RRAM cell 510-513.

[0042] Each row of RRAM cell array 520 is connected to the same word line
which is unique to that row or RRAM cell array 520. The word lines of
RRAM cell array 520 are coupled to word line control/drivers 540. Each
column of RRAM cell array 320 is connected to the same bit line which is
unique to that column of RRAM cell array 520. The bit lines of RRAM cell
array 520 are coupled to bit line control 530. Thus, each RRAM cell
310-313 is uniquely addressable by a combination of activating a word
line to access all of RRAM cells of a row and to receive/send results to
a particular RRAM cell of that row via an individual bit line.

[0043] The source of each access transistor 501 in RRAM cell array 520 is
connected to source line driver 560. Source line driver 560, in
combination with word line control/drivers 540, enable the set of some
RRAM cells 510-513 in a row while other RRAM cells 510-513 in the row are
reset. To illustrate, consider a case where RRAM cell 510 is being set
and RRAM cell 511 is simultaneously being reset.

[0044] To perform this operation, source line driver 560 transitions from
0V to a potential that is high enough to cause resistive change memory
element 502 of RRAM cell 511 to transition from a low resistance state to
a high resistance state (e.g., VRESET). This voltage VRESET may
be generated by source line voltage generator 552 and supplied to one or
more common source lines of RRAM cell array 520 via source line driver
560. The bit line for RRAM cell 511, which is being reset, is held at 0V.
The bit line for RRAM cell 510, which is being set, is transitioned from
0V to a potential that is high enough to cause resistive change memory
element 502 of RRAM cell 510 to transition from a high resistance state
to a low resistance state. Because the source of access transistor 501
for RRAM cell 510 is at VRESET, the bit line for RRAM cell 510 must
be raised to a potential that is at least VRESET higher than
VSET. In other words, the bit line for RRAM cell 510 is raised to a
potential voltage of VSET+VRESET. This voltage of
VSET+VRESET may be generated by bit line voltage generator 550
and supplied to at least one bit line of RRAM cell array 520 via bit line
control 530.

[0045] Word line control/drivers 540 brings the word line for RRAM cells
510-511 to a potential slightly above VRESET plus the threshold
voltage of the access transistors 501 (i.e.,
≈VTN+VRESET). Word line control/drivers 540 may
generate this voltage from a current generated by reference current
generator 506. Word line control/drivers 540 may generate this voltage
using a current mirror to mirror the current received from reference
current generator 506.

[0046] With the word line at approximately VTN+VRESET, and the
bit line for RRAM cell 511 being at 0V, resistive change memory element
502 is exposed to a potential of VRESET--except that the polarity is
reversed with respect to VSET (i.e., -VRESET). This voltage
causes resistive change memory element 502 of RRAM cell 511 to transition
from a low resistance state to a high resistance state. The polarity of
the voltage applied to resistive change memory element 502 of RRAM cell
511 to reset it is the opposite polarity as VSET because that is
typically what is required to reset resistive change memory element 502
from a lower resistance state to a higher resistance state. Resistive
change memory element 502 of RRAM cell 511 is exposed to a potential of
-VRESET because access transistor 501 of RRAM cell 511 acts in a
source-follower configuration.

[0047] The 0V on the bit line for RRAM cell 511 pulls the drain of access
transistor 501 of RRAM cell 511 to 0V. Since the gate of access
transistor 501 of RRAM cell 511 is at VTN+VRESET, which is at
least an n-channel FET threshold voltage above both the source and drain
of access transistor 501 of RRAM cell 511, access transistor 501 of RRAM
cell 511 turns on. This allows the potential on the source of access
transistor 501 of RRAM cell 511 (i.e., VRESET) to be passed to the
internal node of RRAM cell 511--thus applying -VRESET to resistive
change memory element 502 of RRAM cell 511 to reset it. The -VRESET
voltage across resistive change memory element 502 of RRAM cell 511
causes the resistance of resistive change memory element 502 of RRAM cell
511 to increase by several orders of magnitude as resistive change memory
element 502 or RRAM cell 511 transitions to the reset state.

[0048] With the word line at approximately VTN+VRESET, and the
bit line for RRAM cell 510 being at VSET+VRESET, the resistance
of resistive change memory element 502 of RRAM cell 510 is initially
exposed to a potential of VSET. This voltage across resistive change
memory element 502 of RRAM cell 510 causes the resistance of resistive
change memory element 502 of RRAM cell 510 to drop by several orders of
magnitude as resistive change memory element 502 of RRAM cell 510
transitions to the set state. As the resistance of resistive change
memory element 502 of RRAM cell 510 drops, the current through resistive
change memory element 502 of RRAM cell 510 increases. At some point as
this current increases, access transistor 501 of RRAM cell 510 enters the
saturation region of operation. When access transistor 501 of RRAM cell
510 is in the saturation region of operation, the current flowing from
the bit line of RRAM cell 510, through resistive change memory element
502 and access transistor 501 of RRAM cell 510 may be limited in response
to the voltage driven on the word line by word line control/drivers 540.

[0049] The voltage driven on the word line by word line control/drivers
540 may be set such that, when the access transistor 501 of RRAM cell 510
reaches saturation, only approximately the current supplied by reference
current generator 506 is allowed by access transistor 501 of RRAM cell
510 to flow through resistive change memory element 502. In an
embodiment, the equilibrium current through the RRAM cell 510 may be
controlled to be a predetermined multiple (e.g., 1:1, 2.5:1, 1:3, etc.)
of the current received from reference current generator 506. The
equilibrium current through the RRAM cell 510 may be controlled to be the
predetermined multiple of the current received from reference current
generator 506 by designing the width-to-length ratios of access
transistor 501 of RRAM cell 510 and a transistor (not shown) of word line
control/drivers 540 that receives a current from reference current
generator 506 to be appropriate multiples of each other.

[0050] The word lines of the non-selected rows (e.g., RRAM cells 512-513)
are driven by word line control/drivers 540 to 0V. This ensures that the
access transistors 501 of non-selected RRAM cells 512-513 are off. The
access transistors 501 of non-selected RRAM cells 512-513 are off because
the gates of these access transistors 501 are less than an n-channel
threshold voltage above either the source or drain of these access
transistors 501. This results in the potential across the resistive
change memory elements 502 of RRAM cells 512-513 being 0V or
approximately 0V--thus not changing their state.

[0051] In FIG. 5, source line driver 560 is shown on the opposite side of
RRAM cell array 520 as word line control/drivers 540. However, this is
merely for the purposes of illustration. Source line driver 560 may
reside on the same side as, or be integrated with, word line
control/drivers 540.

[0052]FIG. 6 is a flowchart illustrating a method of limiting current
while changing a state of an RRAM device. The steps illustrated in FIG. 6
may be performed by (or on) one or more elements of RRAM circuit 100,
RRAM memory 300, and/or RRAM memory 500. A first voltage is applied to a
terminal of a variable resistive element (602). For example, a potential
of VSET+VRESET may be applied to the bit line for RRAM cell 510
thereby applying a VSET+VRESET voltage across resistive change
memory element 502 of RRAM cell 510.

[0053] An operating point of a transistor in a memory cell that limits
current through the variable resistive element is determined. The
operating point of the transistor is determined by applying a second
voltage to a control node of the transistor while the variable resistive
element is changing from a first resistance to a second resistance (604).
For example, word line control/drivers 540 may determine the operating
point of access transistor 501 of RRAM cell 510 by applying a bias
voltage to the word line of RRAM cell 510. This bias voltage may result
in access transistor 501 of RRAM cell 510 operating in the linear region
of operation as resistive change memory element 502 of RRAM cell 510
changes from a higher resistance to a lower resistance. This bias voltage
may result in access transistor 501 of RRAM cell 510 operating in the
saturation region of operation thereby limiting the current through as
resistive change memory element 502 of RRAM cell 510 as resistive change
memory element 502 of RRAM cell 510 changes from a higher resistance to a
lower resistance.

[0054] The variable resistive element is caused to change from the first
resistance to the second resistance (606). For example, the potential of
VSET+VRESET on the bit line of RRAM cell 510, and a potential
of VRESET on a source line of RRAM cell 510, and the second voltage
on the gate of access transistor 501 of RRAM cell 510, may cause
resistive change memory element 502 of RRAM cell 510 to change from a
higher resistance to a lower resistance. As resistive change memory
element 502 of RRAM cell 510 changes from a higher resistance to a lower
resistance, the operating point of access transistor 501 of RRAM cell 510
may limit the current through resistive change memory element 502 of RRAM
cell 510.

[0056] Similar to RRAM memory 300 and RRAM memory 500, each RRAM cell
710-713 comprises a resistive change memory element 702 and an access
transistor 701. The gate of each access transistor 701 in a row is
connected to a word line 703. Each word line 703 of a row is uniquely
coupled to word line driver 741-742. A first terminal of each resistive
change memory element 702 or a column is uniquely connected to a bit line
705. A second terminal of each resistive change memory element 702 is
connected to the drain of the access transistor 701 for that RRAM cell
710-713. Thus, each RRAM cell 710-713 is uniquely addressable by a
combination of activating a word line 703 to access all of the RRAM cells
of a row and to receive and send results to a particular RRAM cell
710-713 of that row via a bit line 705.

[0057] The source of each access transistor 701 is connected to source
line driver 760 via a common source line 704. Source line driver 760, in
combination with word line control/drivers 740, enable the set of some
RRAM cells 710-713 in a row while other RRAM cells 710-713 in the row are
reset. This was described previously in the discussion of FIG. 5 and
therefore will not be repeated here for the sake of brevity. Word line
drivers 741-742 may provide the word line voltages (biases) and
transitions described previously in association with RRAM memory 300 and
RRAM memory 500.

[0058] Word line drivers 741-742 comprise p-channel field effect
transistor (PFET) 745, and n-channel field effect transistors (NFETs) 746
and 747. The source of PFET 745 is connected to receive a reference
current from reference current generator 706. The drain of PFET 745 is
connected to word line 703. The drain of NFET 746 is connected to word
line 703. The source of NFET 746 is connected to a signal reference
voltage (e.g., signal ground or VSS.) The drain and gate of NFET 747
is connected to word line 703. Because of these connections, NFET 747 may
be referred to as a diode connected transistor or diode connected FET.
The source of diode connected NFET 747 is connected to common source line
704. The gates of PFET 745 and NFET 746 are coupled to word line
decode/control 740.

[0059] To program (i.e., set and reset RRAM cells 710-713) a row of RRAM
memory 700, word line decode/control 740 outputs a logical high (or "1")
to all of the word line drivers 741-742 except the selected word line
driver connected to the selected row. This ensures that NFET 746 is on.
This pulls each of the non-selected word lines to a low voltage potential
ensuring that the access transistors 701 of each of the non-selected rows
remain off during the programming process. Keeping the access transistors
701 of the non-selected rows results in the potential across the
resistive change memory elements 702 of the non-selected RRAM cell rows
being 0V, or approximately 0V--thus not changing the state of the
resistive change memory elements 702 in those rows. The logical high
output to the non-selected drivers also ensures that PFET 745 is off.
Thus, the current output by reference current generator 706 is not
allowed to pass through PFET 745 of the word line drivers 741-742 of the
non-selected rows.

[0060] For the following discussion, assume that RRAM cells 710 and 711
represent the selected row. Word line decode/control 740 outputs a
logical low (or "0") to the word line driver of the selected row. This
logical low causes NFET 746 to be off and PFET 745 to be on. Since only
one row is receiving a logical low from word line decode/control 740, the
entire current from reference current generator 706 flows to source line
driver 760 via PFET 745 of the selected row and diode connected FET 747.
The current flowing through diode connected FET 747 causes diode
connected FET 747 to produce a bias voltage between word line 703 and
common source line 704.

[0061] This bias voltage between word line 703 and common source line 704
of the selected row is such that the current flowing through diode
connected FET 747 is "mirrored" by the access transistors 701 of the RRAM
cells 710-711 of the selected row. In other words, when PFET 745 is on,
it allows the current produced by reference current generator 706 to flow
through diode connected FET 747 of the selected row. Diode connected FET
747 is coupled to the access transistors 701 in such a way as to form a
"current mirror" whereby, when access transistors 701 of the selected row
are operating in the saturation region, the current flowing through
access transistors 701 (and thus the current flowing through the
resistive change memory elements 702) of the selected row may be limited.
This limited current is determined by the current flowing through diode
connected FET 747. The current limitation may be approximately the same
as the current flowing though diode connected FET 747, or approximately a
multiple of that current. Current limits that are a multiple of the
current flowing through diode connected FET 747 may be configured by
choosing appropriate ratios between the width-to-length ratios of diode
connected FET 747 and access transistors 701.

[0062] In FIG. 7, source line driver 760 is shown on the opposite side of
RRAM cell array 720 as word line decode/control 740. However, this is
merely for the purposes of illustration. Source line driver 760 may
reside on the same side as, or be integrated with, word line
control/drivers 740. In addition, in an embodiment, PFET 745 may be
replaced with, or wired in parallel with an NFET or some other form of
pass-gate.

[0063] Also in FIG. 7, access transistors 701 are shown as NFETs.
Likewise, NFET 746 and FET 747 are shown as NFETs, and PFET 745 is a
PFET. It should be understood that in other embodiments, access
transistors 701 may be implemented as PFETs. In these embodiments, the
function of FET 747 may be implemented as a PFET. Also, as appropriate,
the function of PFET 745 may be replaced with an appropriately wired and
controlled NFET. The function of NFET 746 may be replaced with an
appropriately wired and controlled PFET.

[0064] FIG. 8 is a flowchart illustrating a method of programming a
plurality of RRAM cells. The steps illustrated in FIG. 8 may be performed
by (or on) one or more elements of RRAM circuit 100, RRAM memory 300,
RRAM memory 500, and/or RRAM memory 700.

[0065] A VRESET voltage potential is applied to a common source line
(802). For example, source line driver 760 may apply a VRESET
voltage generated by source line voltage generator 752 to one or more
common source lines 704 of RRAM cell array 720. A VSET+VRESET
voltage is applied to a selected bit line (804). For example, bit line
control 730 may apply a VSET+VRESET voltage generated by bit
line voltage generator 750 to bit line 705.

[0066] A signal ground (VSS) voltage is applied to non-selected word
lines (806). For example, word line decode/control 740 may control word
line driver 742 to apply a VSS potential to its associated word
line. A bias voltage of approximately (but typically larger than)
VRESET plus the threshold voltage of an access transistor is applied
to a selected word line (808). The bias voltage applied is approximately
enough greater than VRESET to allow a desired, but limited, current
to flow. For example, a reference current flowing through diode connected
FET 747 may generate a bias voltage for word line 703. This bias voltage
may cause access transistors 701 to limit the current flowing through the
resistive change memory elements 702 of the selected row. The reference
current flowing through diode connected FET 747 may be supplied via a
gating FET (such as PFET 745) which ensures that only the word line
driver 741 associated with the selected row generates the bias voltage on
the selected word line 703.

[0067]FIG. 9 is a graph of various currents and voltages associated with
limiting current while changing of a state of an RRAM cell. In FIG. 9,
the bit line voltage is transitioned from approximately 0V to
approximately 1V. Concurrent with this transition, the voltage across the
resistive memory element (for example, RRAM memory element 102)
transitions from approximately 0V to approximately 1V. At a later time,
the resistance of the resistive memory element falls from about 1
MΩ to a relatively low value (e.g., 10 kΩ). This fall in
resistance is a result of the voltage across the resistive memory
element. During the fall in resistance of the resistive memory element,
the current though the resistive memory element increases. Then, after
increasing for a period of time, the current though the resistive memory
element is reduced and limited by the access transistor to approximately
an equilibrium value.

[0068] The methods, systems and devices described above may be implemented
in computer systems, or stored by computer systems. The methods described
above may also be stored on a computer readable medium. Devices,
circuits, and systems described herein may be implemented using
computer-aided design tools available in the art, and embodied by
computer-readable files containing software descriptions of such
circuits. This includes, but is not limited to one or more elements of
RRAM circuit 100, RRAM memory 300, RRAM memory 500, and/or RRAM memory
700, and their components. These software descriptions may be:
behavioral, register transfer, logic component, transistor, and layout
geometry-level descriptions. Moreover, the software descriptions may be
stored on storage media or communicated by carrier waves.

[0069] Data formats in which such descriptions may be implemented include,
but are not limited to: formats supporting behavioral languages like C,
formats supporting register transfer level (RTL) languages like Verilog
and VHDL, formats supporting geometry description languages (such as
GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and
languages. Moreover, data transfers of such files on machine-readable
media may be done electronically over the diverse media on the Internet
or, for example, via email. Note that physical files may be implemented
on machine-readable media such as: 4 mm magnetic tape, 8 mm magnetic
tape, 31/2 inch floppy media, CDs, DVDs, and so on.

[0070] FIG. 10 illustrates a block diagram of a computer system. Computer
system 1000 includes communication interface 1020, processing system
1030, storage system 1040, and user interface 1060. Processing system
1030 is operatively coupled to storage system 1040. Storage system 1040
stores software 1050 and data 1070. Storage system 1040 may include one
or more of memory systems 100, 200, 300, or 400. Processing system 1030
is operatively coupled to communication interface 1020 and user interface
1060. Computer system 1000 may comprise a programmed general-purpose
computer. Computer system 1000 may include a microprocessor. Computer
system 1000 may comprise programmable or special purpose circuitry.
Computer system 1000 may be distributed among multiple devices,
processors, storage, and/or interfaces that together comprise elements
1020-1070.

[0072] Processing system 1030 retrieves and executes software 1050 from
storage system 1040. Processing system may retrieve and store data 1070.
Processing system may also retrieve and store data via communication
interface 1020. Processing system 1050 may create or modify software 1050
or data 1070 to achieve a tangible result. Processing system may control
communication interface 1020 or user interface 1070 to achieve a tangible
result. Processing system may retrieve and execute remotely stored
software via communication interface 1020.

[0073] Software 1050 and remotely stored software may comprise an
operating system, utilities, drivers, networking software, and other
software typically executed by a computer system. Software 1050 may
comprise an application program, applet, firmware, or other form of
machine-readable processing instructions typically executed by a computer
system. When executed by processing system 1030, software 1050 or
remotely stored software may direct computer system 1000 to operate as
described herein.

[0074] The above description and associated figures teach the best mode of
the invention. The following claims specify the scope of the invention.
Note that some aspects of the best mode may not fall within the scope of
the invention as specified by the claims. Those skilled in the art will
appreciate that the features described above can be combined in various
ways to form multiple variations of the invention. As a result, the
invention is not limited to the specific embodiments described above, but
only by the following claims and their equivalents.