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JESD204

Product Description

The LogiCORE™ IP JESD204 core is designed to Joint Electron Devices Engineering Council (JEDEC®) JESD204B or JESD204C standard. The JESD204 specifications describe serial data interfaces and the link protocols between data converters and logic devices.

The JESD204B IP core supports line rates of up to 12.5 Gbps characterized to the JESD204B specification and line rates up to 16.1 Gbps not characterized to the JESD204B specification and between 1-32 lane configurations. The IP Core can be configured as JESD204B Transmitter for interfacing to DAC device or JESD204B Receiver for interfacing to ADC device.

The JESD204C IP core implements a JESD204C compatible interface supporting line rates from 1 Gb/s to 32 Gb/s. Each core supports between 1-8 lane configurations and can be combined with other cores to achieve more lanes. The IP Core can be configured as JESD204C Transmitter for interfacing to DAC device using either a 64B66B or 8B10B link layer.

The JESD204 IP cores are delivered as a netlist along with the supporting wrapper files.

Key Features and Benefits

JESD204B

Designed to JEDEC JESD204B specification

Supports scrambling and initial lane alignment

Supports 1-256 Octets per frame and 1-32 frames per multi-frame

Supports 1 to 32 lane configurations

Supports line rates up to 12.5 Gbps certified to the JESD204B spec

Supports line rates up to 16.3 Gpbs not certified to the JESD204B spec

JESD204C

Designed to JEDEC® JESD204C Standard

Supports up to eight lanes per core and greater number of lanes using multiple cores

Supports 64B66B and 8B10B link layers

Supports FEC Encoding (TX) and Decoding (RX) on the 64B66B link layer

Supports CRC-12, CMD and FEC meta data modes on the 64B66B link layer

Supports subclass 0 and 1 on the 64B66B link layer and Subclass 0, 1 and 2 on the 8B10B link layer

Supports Transceiver sharing between TX and RX cores using the JESD204_PHY core