ABSTRACT
In digital signal processing convolution is
a fundamental computation that is ubiquitous in
many application areas. In order to compute
convolution of long sequence, Overlap-Add
method (OLA) and Overlap-Save method (OLS)
methods are employed. In this paper, block
convolution process is proposed using a multiplier
architecture based on vertical and crosswise
algorithm of Ancient Indian Vedic Mathematics
and embedding it in OLA method for reducing
calculations.And as the vedic multiplier is been
used it is named as Vedic convolution
algorithm.The coding is done in VHDL (Very
High Speed Integrated Circuits Hardware
Description Language) for the FPGA , as it is
FIGURE 1: Block diagram of the process followed.
being increasingly used for variety
of computationally intensive
applications.Simulation and synthesis is done II. CONVOLUTION
using Xilinx. Convolution [12] is the mathematical process that
Keywords - Convolution; Overlap-Add (OLA); relates the output, y(t), of a linear, time-invariant
Overlap-Save (OLS); Vedic Maths; VHDl . system [4] to its input, x(t), and impulse response,
h(t).
I. INTRODUCTION
In this paper, Urdhva-Tiryakbhyam Sutra [7] is first
applied to the binary number system and is used to
develop digital multiplier architecture. This Sutra
also shows the effectiveness of reducing the N×N
multiplier [18] structure into an efficient 4×4
multiplier structures. This work presents a systematic
design methodology for fast and area efficient digital
multiplier based on Vedic mathematics [6]. The basic
work proposed in this paper is been explained using
the block diagram in Fig 1.

In this paper, the block convolution [21] algorithm is
implemented in VHDL (Very High Speed Integrated
Circuited Hardware Description Language) [3] and FIGURE 2: Overlap add method.
the FPGA synthesis and logic simulation are done
using Xilinx ISE design suite 12.1 The overlap-add method [13] (OLA) is an efficient
way to evaluate the discrete convolution between a
very long signal x[n] with a finite impulse response
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.Jan-Feb 2012.
The basic rule for the multiplication of two
numbers of 6 digits is shown using the line drawing
as follows.
The methedology followed in this proposed work is
explained using the flow diagrams below.
Steps:
i) 4 X 6 = 24: 2. Similarly for any number of digits this
multiplication technique of ancient Indian Vedic
mathematics [6] can be used. We
discuss multiplication of two.
vi) Respective digits are added.And as
we are performing block convolution using overlap
add method this sample is divided into 16 input data
block for OLA method.1 shows the concept of overlap add [11]
method by Zero-pad length-L blocks by M−1
samples.
ii) (3 X 6) + (4 x 1) = 18 + 4 = 22. METHEDOLOGY FOLLOWED
In this proposed paper we have made a convolution
with x(n) and h(n) both having 256 samples. Asmita Haveliya / International Journal of Engineering Research and Applications (IJERA)
ISSN: 2248-9622 www. URDHVA-TIRYAGBHYAM SUTRA
Urdhva-Tiryagbhyam [19] is the general formula
applicable to all cases of multiplication and also in
the division of a large number by another large
number.678-684
h[n]. overlapped by M−1
samples. three digit numbers
with this method by placing the carried over digits
under the first row and proceed. FIGURE 4: General rule for a 6 digit by 6 digit
multiplication. It means vertically and crosswise. each having 16 elements.
iii) (2 X 6) + (3 X 1) + (4 X 3) = 12 + 3 + 12 = 27.
FIGURE 3: General rule for a 3 digit by 3 digit
multiplication.ijera. 1. 2. 2. Issue 1.
the carried over digit is placed below fourth digit.
IV. Add successive blocks. the carried over dividing the input sequence of length 256 into 16
digit is placed below fifth digit. pp. the carried over
digit is placed below third digit.
v) (2X3) =6. input blocks of length 16.
III. 2. so that the tails sum to produce the complete
linear convolution.The Fig.
This flow “A” is the stimulus module which is
iv) (2 X 1) + (3 X 3) = 2 + 9 = 11.com
Vol. the carried over digit is placed below
the second digit.

066Mb/s
multiplication is to be done.000
BlockRAM 38Mb
DSP Slices 2. has made it feasible to provide hardware for
application specific computation design. FPGA
The introduction of field programmable gate arrays
(FPGA). TABLE I.The vedic convolution
algorothm proposed in this paper is been simulated
and synthesised using the xilinx design suite 12.This Bandwidth (full duplex)
block is Vedic multiplier which is used wherever Memory Interface 1. and thus result in significant
savings in cost and design cycle.
TABLE II.1. SUMMARY OF VERTEX 6 FEATURES
Features Virtex-6
Logic Cells 760.Jan-Feb 2012.com
Vol. 2.
V.1
with the device family as Vertex 6 (low power). Issue 1.the
The flow “C” is overlap add module which helps summary of the device description of the vertex
in providing efficient area and speed of the proposed FPGA used is explained in the table below
architechture as it reduces the complexity of the
calculation. pp. Asmita Haveliya / International Journal of Engineering Research and Applications (IJERA)
ISSN: 2248-9622 www. (DDR3)
PCI Express® Interface Gen2x8
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.016
DSP Performance 2. The changes
in designs in FPGA’s [20] can be accomplished
within a few hours.678-684
This flow “B” is the convolution module which is
performing the convolution of individual block with
16 elements. FPGAs offer speed
comparable to dedicated and fixed hardware systems
for parallel algorithm.ijera. SUMMARY OF FPGA FEATURES
Device Family Vertex 6
Device XC6VLX75TL
Package FF484
Speed Grade -3L
The features of the vertex 6 FPGA used in this
proposed work with Xilinx Design Suite 12. as
described the Xilinx are listed in the table below.419GMACS
(symmetric FIR)
Transceiver Count 72
Transceiver Speed 11.18Gb/s
This flow “D” is the main block which reduces the Total Transceiver 536Gb/s
calculation complexity to a very wide extent.

678-684
Agile Mixed Signal Yes
(AMS)/XADC
Configuration AES Yes
I/O Pins 1. Asmita Haveliya / International Journal of Engineering Research and Applications (IJERA)
ISSN: 2248-9622 www.The table below
shows the synthesis report of the proposed work with
the logic resource utilization.200
I/O Voltage 1. 2.89 secs
Total memory usage is 317328 kilobytes
The following are the simulation results of the
proposed work.
TABLE III. 1.
Total REAL time to Xst completion: 775.
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. there is a considerable
improvement in their performance.2V. RESULTS
The main point of this paper was to introduce a
method for calculating the linear convolution sum of
two finite length sequences that is easy to learn and
perform.8V. pp.5V
EasyPath Cost Reduction Yes
Solution
VI.ijera.5V.It has been found on embedding Vedic
multiplication for OLA. 1.00 secs
Total CPU time to Xst completion: 774.Jan-Feb 2012.
2. SUMMARY OF SYNTHESIS REPORT
Device Utilization Summary (estimated values)
Logic Used Available Utilization
Utilization
Number of 988 93120 1%
Slice Registers
Number of 10799 46560 23%
Slice LUTs
Number of 408 11379 3%
fully used
LUT-FF pairs
Number of 625 240 260%
bonded IOBs
Number of 1 32 3%
BUFG/BUFG
CTRLs
The other constraints of the synthesis report are as
follows. Issue 1.com
Vol.