64A -40C - 85C

64M2

This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. For packaging information, see Packaging information on page 61.

PC1 PC2 PC3 PC4 PC5 PC6 PC7

PD0 PD1

Notes:

1. For full details on pinout and alternate pin functions refer to Pinout and Pin Functions on page 49. 2. The large center pad underneath the QFN/MLF package should be soldered to ground on the board to ensure good mechanical stability.

PD2 PD3 PD4 PD5 PD6

27 28 29 30 31 32

USART0

T/C0:1

T/C0:1

T/C0

TWI

TWI

SPI

SPI

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XMEGA A33. OverviewThe Atmel AVR XMEGA A3 is a family of low power, high performance and peripheral rich CMOS 8/16-bit microcontrollers based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the XMEGA A3 achieves throughputs approaching 1 Million Instructions Per Second (MIPS) per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR CPU combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction, executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times faster than conventional single-accumulator or CISC based microcontrollers. The XMEGA A3 devices provide the following features: In-System Programmable Flash with Read-While-Write capabilities, Internal EEPROM and SRAM, four-channel DMA Controller, eight-channel Event System, Programmable Multi-level Interrupt Controller, 50 general purpose I/O lines, 16-bit Real Time Counter (RTC), seven flexible 16-bit Timer/Counters with compare modes and PWM, seven USARTs, two Two Wire Serial Interfaces (TWIs), three Serial Peripheral Interfaces (SPIs), AES and DES crypto engine, two 8-channel 12-bit ADCs with optional differential input with programmable gain, one 2-channel 12-bit DACs, four analog comparators with window mode, programmable Watchdog Timer with separate Internal Oscillator, accurate internal oscillators with PLL and prescaler and programmable Brown-Out Detection. The Program and Debug Interface (PDI), a fast 2-pin interface for programming and debugging, is available. The devices also have an IEEE std. 1149.1 compliant JTAG test interface, and this can also be used for On-chip Debug and programming. The XMEGA A3 devices have five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, DMA Controller, Event System, Interrupt Controller and all peripherals to continue functioning. The Power-down mode saves the SRAM and register contents but stops the oscillators, disabling all other functions until the next TWI or pin-change interrupt, or Reset. In Power-save mode, the asynchronous Real Time Counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. In Standby mode, the Crystal/Resonator Oscillator is kept running while the rest of the device is sleeping. This allows very fast start-up from external crystal combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. To further reduce power consumption, the peripheral clock for each individual peripheral can optionally be stopped in Active mode and Idle sleep mode. The device is manufactured using Atmel's high-density nonvolatile memory technology. The program Flash memory can be reprogrammed in-system through the PDI or JTAG. A Bootloader running in the device can use any interface to download the application program to the Flash memory. The Bootloader software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8/16-bit RISC CPU with In-System Self-Programmable Flash, the Atmel XMEGA A3 is a powerful microcontroller family that provides a highly flexible and cost effective solution for many embedded applications. The XMEGA A3 devices are supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.

GND RESET/ PDI_CLK

EVENT ROUTING NETWORK

To Clock Generator PORT C (8) PORT D (8) PORT E (8)

TOSC2 PC[0..7] PD[0..7] PE[0..7]

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XMEGA A34. ResourcesA comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.

4.1

Recommended reading XMEGA Manual XMEGA Application Notes This device data sheet only contains part specific information and a short description of each peripheral and module. The XMEGA Manual describes the modules and peripherals in depth. The XMEGA application notes contain example code and show applied use of the modules and peripherals. The XMEGA Manual and Application Notes are available from http://www.atmel.com/avr.

5. DisclaimerFor devices that are not available yet, typical values contained in this datasheet are based on simulations and characterization of other AVR XMEGA microcontrollers manufactured on the same process technology. Min. and Max values will be available after the device is characterized.

OverviewThe XMEGA A3 uses an 8/16-bit AVR CPU. The main function of the AVR CPU is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations and control peripherals. Interrupt handling is described in a separate section. Figure 6-1 on page 7 shows the CPU block diagram. Figure 6-1. CPU block diagramDATA BUS

Program Counter

Flash Program Memory 32 x 8 General Purpose Registers

OCD

Instruction Register

STATUS/ CONTROL

Instruction Decode

ALU

Multiplier/ DES

DATA BUS

Peripheral Module 1

Peripheral Module 2

SRAM

EEPROM

PMIC

The AVR uses a Harvard architecture - with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipeline. While one instruction is being executed, the next instruction is pre-fetched from the program memory.

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XMEGA A3This concept enables instructions to be executed in every clock cycle. The program memory is In-System Re-programmable Flash memory.

6.3

Register FileThe fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File - in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing - enabling efficient address calculations. One of these address pointers can also be used as an address pointer for look up tables in Flash program memory.

6.4

ALU - Arithmetic Logic Unit

The high performance Arithmetic Logic Unit (ALU) supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. After an arithmetic or logic operation, the Status Register is updated to reflect information about the result of the operation. The ALU operations are divided into three main categories arithmetic, logical, and bit-functions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for easy implementation of 32-bit arithmetic. The ALU also provides a powerful multiplier supporting both signed and unsigned multiplication and fractional format.

6.5

Program FlowWhen the device is powered on, the CPU starts to execute instructions from the lowest address in the Flash Program Memory 0. The Program Counter (PC) addresses the next instruction to be fetched. After a reset, the PC is set to location 0. Program flow is provided by conditional and unconditional jump and call instructions, capable of addressing the whole address space directly. Most AVR instructions use a 16-bit word format, while a limited number uses a 32-bit format. During interrupts and subroutine calls, the return address PC is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. After reset the Stack Pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR CPU.

OverviewThe AVR architecture has two main memory spaces, the Program Memory and the Data Memory. In addition, the XMEGA A3 features an EEPROM Memory for non-volatile data storage. All three memory spaces are linear and require no paging. The available memory size configurations are shown in Ordering Information on page 2. In addition each device has a Flash memory signature row for calibration data, device identification, serial number etc. Non-volatile memory spaces can be locked for further write or read/write operations. This prevents unrestricted access to the application software.

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XMEGA A37.3 In-System Programmable Flash Program MemoryThe XMEGA A3 devices contains On-chip In-System Programmable Flash memory for program storage, see Figure 7-1 on page 10. Since all AVR instructions are 16- or 32-bits wide, each Flash address location is 16 bits. The Program Flash memory space is divided into Application and Boot sections. Both sections have dedicated Lock Bits for setting restrictions on write or read/write operations. The Store Program Memory (SPM) instruction must reside in the Boot Section when used to write to the Flash memory. A third section inside the Application section is referred to as the Application Table section which has separate Lock bits for storage of write or read/write protection. The Application Table section can be used for storing non-volatile data or application software.

The Application Table Section and Boot Section can also be used for general application software.

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XMEGA A37.4 Data MemoryThe Data Memory consist of the I/O Memory, EEPROM and SRAM memories, all within one linear address space, see Figure 7-2 on page 11. To simplify development, the memory map for all devices in the family is identical and with empty, reserved memory space for smaller devices.

Figure 7-2.

Data Memory Map (Hexadecimal address)

ATxmega192A3 I/O Registers (4 KB) EEPROM (2 KB)RESERVED

Byte Address 0 FFF 1000 17FF

Byte Address 0 FFF 1000 17FF

ATxmega128A3 I/O Registers (4 KB) EEPROM (2 KB)

RESERVED

Byte Address 0 FFF 1000 17FF

ATxmega64A3 I/O Registers (4 KB) EEPROM (2 KB)

RESERVED

2000 5FFF

Internal SRAM (16 KB)

2000 3FFF

Internal SRAM (8 KB)

2000 2FFF

Internal SRAM (4 KB)

Byte Address 0 FFF 1000

ATxmega256A3 I/O Registers (4 KB) EEPROM (4 KB)

1FFF 2000 5FFF Internal SRAM (16 KB)

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XMEGA A37.4.1 I/O Memory All peripherals and modules are addressable through I/O memory locations in the data memory space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store (ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the CPU and the I/O Memory. The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F directly. I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. The value of single bits can be checked by using the SBIS and SBIC instructions on these registers. The I/O memory address for all peripherals and modules in XMEGA A3 is shown in the Peripheral Module Address Map on page 56. 7.4.2 SRAM Data Memory The XMEGA A3 devices have internal SRAM memory for data storage. 7.4.3 EEPROM Data Memory The XMEGA A3 devices have internal EEPROM memory for non-volatile data storage. It is addressable either in a separate data space or it can be memory mapped into the normal data memory space. The EEPROM memory supports both byte and page access.

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XMEGA A37.5 Production Signature RowThe Production Signature Row is a separate memory section for factory programmed data. It contains calibration data for functions such as oscillators and analog modules. The production signature row also contains a device ID that identify each microcontroller device type, and a serial number that is unique for each manufactured device. The device ID for the available XMEGA A3 devices is shown in Table 7-1 on page 13. The serial number consist of the production LOT number, wafer number, and wafer coordinates for the device. The production signature row can not be written or erased, but it can be read from both application software and external programming. Table 7-1. Device ID bytes for XMEGA A3 devices.Device Byte 2 ATxmega64A3 ATxmega128A3 ATxmega192A3 ATxmega256A3 42 42 44 42 Device ID bytes Byte 1 96 97 97 98 Byte 0 1E 1E 1E 1E

7.6

User Signature Row

The User Signature Row is a separate memory section that is fully accessible (read and write) from application software and external programming. The user signature row is one flash page in size, and is meant for static user parameter storage, such as calibration data, custom serial numbers or identification numbers, random number seeds etc. This section is not erased by Chip Erase commands that erase the Flash, and requires a dedicated erase command. This ensures parameter storage during multiple program/erase session and on-chip debug sessions.

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XMEGA A37.7 Flash and EEPROM Page SizeThe Flash Program Memory and EEPROM data memory are organized in pages. The pages are word accessible for the Flash and byte accessible for the EEPROM. Table 7-2 on page 14 shows the Flash Program Memory organization. Flash write and erase operations are performed on one page at a time, while reading the Flash is done one byte at a time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) gives the page number and the least significant address bits (FWORD) gives the word in the page.

Number of words and Pages in the Flash.

Table 7-3 on page 14 shows EEPROM memory organization for the XMEGA A3 devices. EEEPROM write and erase operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at a time. For EEPROM access the NVM Address Register (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) gives the page number and the least significant address bits (E2BYTE) gives the byte in the page.

OverviewThe XMEGA A3 has a Direct Memory Access (DMA) Controller to move data between memories and peripherals in the data space. The DMA controller uses the same data bus as the CPU to transfer data. It has 4 channels that can be configured independently. Each DMA channel can perform data transfers in blocks of configurable size from 1 to 64K bytes. A repeat counter can be used to repeat each block transfer for single transactions up to 16M bytes. Each DMA channel can be configured to access the source and destination memory address with incrementing, decrementing or static addressing. The addressing is independent for source and destination address. When the transaction is complete the original source and destination address can automatically be reloaded to be ready for the next transaction. The DMAC can access all the peripherals through their I/O memory registers, and the DMA may be used for automatic transfer of data to/from communication modules, as well as automatic data retrieval from ADC conversions, data transfer to DAC conversions, or data transfer to or from port pins. A wide range of transfer triggers is available from the peripherals, Event System and software. Each DMA channel has different transfer triggers. To allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer when the first is finished and vice versa. The DMA controller can read from memory mapped EEPROM, but it cannot write to the EEPROM or access the Flash.

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XMEGA A3

9. Event System9.1 Features

Inter-peripheral communication and signalling with minimum latency CPU and DMA independent operation 8 Event Channels allows for up to 8 signals to be routed at the same time Events can be generated by Timer/Counters (TCxn) Real Time Counter (RTC) Analog to Digital Converters (ADCx) Analog Comparators (ACx) Ports (PORTx) System Clock (ClkSYS) Software (CPU) Events can be used by Timer/Counters (TCxn) Analog to Digital Converters (ADCx) Digital to Analog Converters (DACx) Ports (PORTx) DMA Controller (DMAC) IR Communication Module (IRCOM) The same event can be used by multiple peripherals for synchronized timing Advanced Features Manual Event Generation from software (CPU) Quadrature Decoding Digital Filtering Functions in Active and Idle mode

9.2

OverviewThe Event System is a set of features for inter-peripheral communication. It enables the possibility for a change of state in one peripheral to automatically trigger actions in one or more peripherals. What changes in a peripheral that will trigger actions in other peripherals are configurable by software. It is a simple, but powerful system as it allows for autonomous control of peripherals without any use of interrupts, CPU or DMA resources. The indication of a change in a peripheral is referred to as an event, and is usually the same as the interrupt conditions for that peripheral. Events are passed between peripherals using a dedicated routing network called the Event Routing Network. Figure 9-1 on page 17 shows a basic block diagram of the Event System with the Event Routing Network and the peripherals to which it is connected. This highly flexible system can be used for simple routing of signals, pin functions or for sequencing of events. The maximum latency is two CPU clock cycles from when an event is generated in one peripheral, until the actions are triggered in one or more other peripherals. The Event System is functional in both Active and Idle modes.

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XMEGA A3Figure 9-1. Event system block diagram.

PORTx

ClkSYS

CPU

ADCx Event Routing Network DACx

RTC

ACx

IRCOM

T/Cxn

DMAC

The Event Routing Network can directly connect together ADCs, DACs, Analog Comparators (ACx), I/O ports (PORTx), the Real-time Counter (RTC), Timer/Counters (T/C) and the IR Communication Module (IRCOM). Events can also be generated from software (CPU). All events from all peripherals are always routed into the Event Routing Network. This consist of eight multiplexers where each can be configured in software to select which event to be routed into that event channel. All eight event channels are connected to the peripherals that can use events, and each of these peripherals can be configured to use events from one or more event channels to automatically trigger a software selectable action.

OverviewXMEGA A3 has an advanced clock system, supporting a large number of clock sources. It incorporates both integrated oscillators, external crystal oscillators and resonators. A high frequency Phase Locked Loop (PLL) and clock prescalers can be controlled from software to generate a wide range of clock frequencies from the clock source input. It is possible to switch between clock sources from software during run-time. After reset the device will always start up running from the 2 Mhz internal oscillator. A calibration feature is available, and can be used for automatic run-time calibration of the internal 2 MHz and 32 MHz oscillators. This reduce frequency drift over voltage and temperature. A Crystal Oscillator Failure Monitor can be enabled to issue a Non-Maskable Interrupt and switch to internal oscillator if the external oscillator fails. Figure 10-1 on page 19 shows the principal clock system in XMEGA A3.

PERIPHERALS ADC DAC

CLOCK CONTROL clkPER UNIT with PLL and Prescaler

PORTS ... DMA INTERRUPT EVSYS RAM

32.768 KHz Crystal Oscillator

0.4 - 16 MHz Crystal Oscillator

CPU

clkCPU NVM MEMORY

External Clock Input FLASH EEPROM

Each clock source is briefly described in the following sub-sections.

10.310.3.1

Clock Options32 kHz Ultra Low Power Internal Oscillator The 32 kHz Ultra Low Power (ULP) Internal Oscillator is a very low power consumption clock source. It is used for the Watchdog Timer, Brown-Out Detection and as an asynchronous clock source for the Real Time Counter. This oscillator cannot be used as the system clock source, and it cannot be directly controlled from software.

10.3.2

32.768 kHz Calibrated Internal Oscillator The 32.768 kHz Calibrated Internal Oscillator is a high accuracy clock source that can be used as the system clock source or as an asynchronous clock source for the Real Time Counter. It is calibrated during production to provide a default frequency which is close to its nominal frequency.

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XMEGA A310.3.3 32.768 kHz Crystal Oscillator The 32.768 kHz Crystal Oscillator is a low power driver for an external watch crystal. It can be used as system clock source or as asynchronous clock source for the Real Time Counter. 10.3.4 0.4 - 16 MHz Crystal Oscillator The 0.4 - 16 MHz Crystal Oscillator is a driver intended for driving both external resonators and crystals ranging from 400 kHz to 16 MHz. 10.3.5 2 MHz Run-time Calibrated Internal Oscillator The 2 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated during production to provide a default frequency which is close to its nominal frequency. The oscillator can use the 32.768 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator as a source for calibrating the frequency run-time to compensate for temperature and voltage drift hereby optimizing the accuracy of the oscillator. 10.3.6 32 MHz Run-time Calibrated Internal Oscillator The 32 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated during production to provide a default frequency which is close to its nominal frequency. The oscillator can use the 32.768 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator as a source for calibrating the frequency run-time to compensate for temperature and voltage drift hereby optimizing the accuracy of the oscillator. 10.3.7 External Clock input The external clock input gives the possibility to connect a clock from an external source. 10.3.8 PLL with Multiplication factor 1 - 31x The PLL provides the possibility of multiplying a frequency by any number from 1 to 31. In combination with the prescalers, this gives a wide range of output frequencies from all clock sources.

OverviewThe XMEGA A3 provides various sleep modes tailored to reduce power consumption to a minimum. All sleep modes are available and can be entered from Active mode. In Active mode the CPU is executing application code. The application code decides when and which sleep mode to enter. Interrupts from enabled peripherals and all enabled reset sources can restore the microcontroller from sleep to Active mode. In addition, Power Reduction registers provide a method to stop the clock to individual peripherals from software. When this is done, the current state of the peripheral is frozen and there is no power consumption from that peripheral. This reduces the power consumption in Active mode and Idle sleep mode.

11.311.3.1

Sleep ModesIdle Mode In Idle mode the CPU and Non-Volatile Memory are stopped, but all peripherals including the Interrupt Controller, Event System and DMA Controller are kept running. Interrupt requests from all enabled interrupts will wake the device.

11.3.2

Power-down Mode In Power-down mode all system clock sources, and the asynchronous Real Time Counter (RTC) clock source, are stopped. This allows operation of asynchronous modules only. The only interrupts that can wake up the MCU are the Two Wire Interface address match interrupts, and asynchronous port interrupts, e.g pin change.

11.3.3

Power-save Mode Power-save mode is identical to Power-down, with one exception: If the RTC is enabled, it will keep running during sleep and the device can also wake up from RTC interrupts.

11.3.4

Standby Mode Standby mode is identical to Power-down with the exception that all enabled system clock sources are kept running, while the CPU, Peripheral and RTC clocks are stopped. This reduces the wake-up time when external crystals or resonators are used.

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XMEGA A311.3.5 Extended Standby Mode Extended Standby mode is identical to Power-save mode with the exception that all enabled system clock sources are kept running while the CPU and Peripheral clocks are stopped. This reduces the wake-up time when external crystals or resonators are used.

Resetting the AVR

During reset, all I/O registers are set to their initial values. The SRAM content is not reset. Application execution starts from the Reset Vector. The instruction placed at the Reset Vector should be an Absolute Jump (JMP) instruction to the reset handling routine. By default the Reset Vector address is the lowest Flash program memory address, 0, but it is possible to move the Reset Vector to the first address in the Boot Section. The I/O ports of the AVR are immediately tri-stated when a reset source goes active. The reset functionality is asynchronous, so no running clock is required to reset the device. After the device is reset, the reset source can be determined by the application by reading the Reset Status Register.

12.312.3.1

Reset SourcesPower-On Reset The MCU is reset when the supply voltage VCC is below the Power-on Reset threshold voltage.

12.3.2

External Reset The MCU is reset when a low level is present on the RESET pin.

12.3.3

Watchdog Reset The MCU is reset when the Watchdog Timer period expires and the Watchdog Reset is enabled. The Watchdog Timer runs from a dedicated oscillator independent of the System Clock. For more details see WDT - Watchdog Timer on page 24.

12.3.4

Brown-Out Reset The MCU is reset when the supply voltage VCC is below the Brown-Out Reset threshold voltage and the Brown-out Detector is enabled. The Brown-out threshold voltage is programmable.

12.3.5

PDI reset The MCU can be reset through the Program and Debug Interface (PDI).

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XMEGA A312.3.6 Software reset The MCU can be reset by the CPU writing to a special I/O register through a timed sequence.

OverviewThe XMEGA A3 has a Watchdog Timer (WDT). The WDT will run continuously when turned on and if the Watchdog Timer is not reset within a software configurable time-out period, the microcontroller will be reset. The Watchdog Reset (WDR) instruction must be run by software to reset the WDT, and prevent microcontroller reset. The WDT has a Window mode. In this mode the WDR instruction must be run within a specified period called a window. Application software can set the minimum and maximum limits for this window. If the WDR instruction is not executed inside the window limits, the microcontroller will be reset. A protection mechanism using a timed write sequence is implemented in order to prevent unwanted enabling, disabling or change of WDT settings. For maximum safety, the WDT also has an Always-on mode. This mode is enabled by programming a fuse. In Always-on mode, application software can not disable the WDT.

OverviewXMEGA A3 has a Programmable Multi-level Interrupt Controller (PMIC). All peripherals can define three different priority levels for interrupts; high, medium or low. Medium level interrupts may interrupt low level interrupt service routines. High level interrupts may interrupt both lowand medium level interrupt service routines. Low level interrupts have an optional round robin scheme to make sure all interrupts are serviced within a certain amount of time. The built in oscillator failure detection mechanism can issue a Non-Maskable Interrupt (NMI).

14.3

Interrupt vectorsWhen an interrupt is serviced, the program counter will jump to the interrupt vector address. The interrupt vector is the sum of the peripherals base interrupt address and the offset address for specific interrupts in each peripheral. The base addresses for the XMEGA A3 devices are shown in Table 14-1. Offset addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA A manual. For peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 14-1. The program address is the word address.

OverviewThe XMEGA A3 devices have flexible General Purpose I/O Ports. A port consists of up to 8 pins, ranging from pin 0 to pin 7. The ports implement several functions, including synchronous/asynchronous input sensing, pin change interrupts and configurable output settings. All functions are individual per pin, but several pins may be configured in a single operation.

15.3

I/O configurationAll port pins (Pn) have programmable output configuration. In addition, all port pins have an inverted I/O function. For an input, this means inverting the signal between the port pin and the pin register. For an output, this means inverting the output signal between the port register and the port pin. The inverted I/O function can be used also when the pin is used for alternate functions.

Figure 15-6. I/O configuration - Wired-AND with optional pull-up

Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in Figure 15-7 on page 30. Figure 15-7. Input sensing system overviewAsynchronous sensing

EDGE DETECT

Interrupt Control

IREQ

Synchronous sensing Pn Synchronizer

INn D Q D Q

EDGE DETECT

Event

INVERTED I/O

When a pin is configured with inverted I/O, the pin value is inverted before the input sensing.

15.5

Port InterruptEach port has two interrupts with separate priority and interrupt vector. All pins on the port can be individually selected as source for each of the interrupts. The interrupts are then triggered according to the input sense configuration for each pin configured as source for the interrupt.

15.6

Alternate Port Functions

In addition to the input/output functions on all port pins, most pins have alternate functions. This means that other modules or peripherals connected to the port can use the port pins for their functions, such as communication or pulse-width modulation. Pinout and Pin Functions on page 49 shows which modules on peripherals that enable alternate functions on a pin, and which alternate functions that are available on a pin.

OverviewXMEGA A3 has seven Timer/Counters, four Timer/Counter 0 and three Timer/Counter 1. The difference between them is that Timer/Counter 0 has four Compare/Capture channels, while Timer/Counter 1 has two Compare/Capture channels. The Timer/Counters (T/C) are 16-bit and can count any clock, event or external input in the microcontroller. A programmable prescaler is available to get a useful T/C resolution. Updates of Timer and Compare registers are double buffered to ensure glitch free operation. Single slope PWM, dual slope PWM and frequency generation waveforms can be generated using the Compare Channels. Through the Event System, any input pin or event in the microcontroller can be used to trigger input capture, hence no dedicated pins is required for this. The input capture has a noise canceller to avoid incorrect capture of the T/C, and can be used to do frequency and pulse width measurements. A wide range of interrupt or event sources are available, including T/C Overflow, Compare match and Capture for each Compare/Capture channel in the T/C. PORTC, PORTD and PORTE each has one Timer/Counter 0 and one Timer/Counter1. PORTF has one Timer/Counter 0. Notation of these are TCC0 (Time/Counter C0), TCC1, TCD0, TCD1, TCE0, TCE1 and TCF0, respectively.

The Hi-Resolution Extension can be enabled to increase the waveform generation resolution by 2 bits (4x). This is available for all Timer/Counters. See Hi-Res - High Resolution Extension on page 34 for more details. The Advanced Waveform Extension can be enabled to provide extra and more advanced features for the Timer/Counter. This are only available for Timer/Counter 0. See AWEX - Advanced Waveform Extension on page 33 for more details.

OverviewThe Advanced Waveform Extension (AWEX) provides extra features to the Timer/Counter in Waveform Generation (WG) modes. The AWEX enables easy and safe implementation of for example, advanced motor control (AC, BLDC, SR, and Stepper) and power control applications. Any WG output from a Timer/Counter 0 is split into a complimentary pair of outputs when any AWEX feature is enabled. These output pairs go through a Dead-Time Insertion (DTI) unit that enables generation of the non-inverted Low Side (LS) and inverted High Side (HS) of the WG output with dead time insertion between LS and HS switching. The DTI output will override the normal port value according to the port override setting. Optionally the final output can be inverted by using the invert I/O setting for the port pin. The Pattern Generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In addition, the waveform generator output from Compare Channel A can be distributed to, and override all port pins. When the Pattern Generator unit is enabled, the DTI unit is bypassed. The Fault Protection unit is connected to the Event System. This enables any event to trigger a fault condition that will disable the AWEX output. Several event channels can be used to trigger fault on several different conditions. The AWEX is available for TCC0. The notation of this is AWEXC.

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XMEGA A318. Hi-Res - High Resolution Extension18.1 Features Increases Waveform Generator resolution by 2-bits (4x) Supports Frequency, single- and dual-slope PWM operation Supports the AWEX when this is enabled and used for the same Timer/Counter

18.2

OverviewThe Hi-Resolution (Hi-Res) Extension is able to increase the resolution of the waveform generation output by a factor of 4. When enabled for a Timer/Counter, the Fast Peripheral clock running at four times the CPU clock speed will be as input to the Timer/Counter. The High Resolution Extension can also be used when an AWEX is enabled and used with a Timer/Counter. XMEGA A3 devices have four Hi-Res Extensions that each can be enabled for each Timer/Counters pair on PORTC, PORTD, PORTE and PORTF. The notation of these are HIRESC, HIRESD, HIRESE and HIRESF, respectively.

OverviewThe XMEGA A3 includes a 16-bit Real-time Counter (RTC). The RTC can be clocked from an accurate 32.768 kHz Crystal Oscillator, the 32.768 kHz Calibrated Internal Oscillator, or from the 32 kHz Ultra Low Power Internal Oscillator. The RTC includes both a Period and a Compare register. For details, see Figure 19-1. A wide range of Resolution and Time-out periods can be configured using the RTC. With a maximum resolution of 30.5 s, time-out periods range up to 2000 seconds. With a resolution of 1 second, the maximum time-out period is over 18 hours (65536 seconds). Figure 19-1. Real-time Counter overview

OverviewThe Two-Wire Interface (TWI) is a bi-directional wired-AND bus with only two lines, the clock (SCL) line and the data (SDA) line. The protocol makes it possible to interconnect up to 128 individually addressable devices. Since it is a multi-master bus, one or more devices capable of taking control of the bus can be connected. The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. Mechanisms for resolving bus contention are inherent in the TWI protocol. PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE.

OverviewThe Serial Peripheral Interface (SPI) allows high-speed full-duplex, synchronous data transfer between different devices. Devices can communicate using a master-slave scheme, and data is transferred both to and from the devices simultaneously. PORTC, PORTD, and PORTE each has one SPI. Notation of these peripherals are SPIC, SPID, and SPIE respectively.

OverviewThe Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly flexible serial communication module. The USART supports full duplex communication, and both asynchronous and clocked synchronous operation. The USART can also be set in Master SPI mode to be used for SPI communication. Communication is frame based, and the frame format can be customized to support a wide range of standards. The USART is buffered in both direction, enabling continued data transmission without any delay between frames. There are separate interrupt vectors for receive and transmit complete, enabling fully interrupt driven communication. Frame error and buffer overflow are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can also be enabled. One USART can use the IRCOM module to support IrDA 1.4 physical compliant pulse modulation and demodulation for baud rates up to 115.2 kbps. PORTC, PORTD, and PORTE each has two USARTs, while PORTF has one USART only. Notation of these peripherals are USARTC0, USARTC1, USARTD0, USARTD1, USARTE0, USARTE1 and USARTF0, respectively.

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XMEGA A323. IRCOM - IR Communication Module23.1 Features Pulse modulation/demodulation for infrared communication Compatible to IrDA 1.4 physical for baud rates up to 115.2 kbps Selectable pulse modulation scheme 3/16 of baud rate period Fixed pulse period, 8-bit programmable Pulse modulation disabled Built in filtering Can be connected to and used by one USART at a time

23.2

OverviewXMEGA contains an Infrared Communication Module (IRCOM) for IrDA communication with baud rates up to 115.2 kbps. This supports three modulation schemes: 3/16 of baud rate period, fixed programmable pulse time based on the Peripheral Clock speed, or pulse modulation disabled. There is one IRCOM available which can be connected to any USART to enable infrared pulse coding/decoding for that USART.

OverviewThe Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two commonly used encryption standards. These are supported through an AES peripheral module and a DES CPU instruction. All communication interfaces and the CPU can optionally use AES and DES encrypted communication and data storage. DES is supported by a DES instruction in the AVR XMEGA CPU. The 8-byte key and 8-byte data blocks must be loaded into the Register file, and then DES must be executed 16 times to encrypt/decrypt the data block. The AES Crypto Module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key. The key and data must be loaded into the key and state memory in the module before encryption/decryption is started. It takes 375 peripheral clock cycles before the encryption/decryption is done and decrypted/encrypted data can be read out, and an optional interrupt can be generated. The AES Crypto Module also has DMA support with transfer triggers when encryption/decryption is done and optional auto-start of encryption/decryption when the state memory is fully loaded.

OverviewXMEGA A3 devices have two Analog to Digital Converters (ADC), see Figure 25-1 on page 42. The two ADC modules can be operated simultaneously, individually or synchronized. The ADC converts analog voltages to digital values. The ADC has 12-bit resolution and is capable of converting up to 2 million samples per second. The input selection is flexible, and both single-ended and differential measurements can be done. For differential measurements an optional gain stage is available to increase the dynamic range. In addition several internal signal inputs are available. The ADC can provide both signed and unsigned results. This is a pipeline ADC. A pipeline ADC consists of several consecutive stages, where each stage convert one part of the result. The pipeline design enables high sample rate at low clock speeds, and remove limitations on samples speed versus propagation delay. This also means that a new analog voltage can be sampled and a new ADC measurement started while other ADC measurements are ongoing. ADC measurements can either be started by application software or an incoming event from another peripheral in the device. Four different result registers with individual input selection (MUX selection) are provided to make it easier for the application to keep track of the data. Each result register and MUX selection pair is referred to as an ADC Channel. It is possible to use DMA to move ADC results directly to memory or peripherals when conversions are done. Both internal and external analog reference voltages can be used. An accurate internal 1.0V reference is available. An integrated temperature sensor is available and the output from this can be measured with the ADC. The output from the DAC, VCC/10 and the Bandgap voltage can also be measured by the ADC.

Configuration Reference selection

Channel A Register Channel B Register

Pin inputs

ADC Channel C Register Channel D Register

Pin inputs

1-64 X

Event Trigger

Each ADC has four MUX selection registers with a corresponding result register. This means that four channels can be sampled within 1.5 s without any intervention by the application other than starting the conversion. The results will be available in the result registers. The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from 3.5 s for 12-bit to 2.5 s for 8-bit result. ADC conversion results are provided left- or right adjusted with optional 1 or 0 padding. This eases calculation when the result is represented as a signed integer (signed 16-bit number). PORTA and PORTB each has one ADC. Notation of these peripherals are ADCA and ADCB, respectively.

OverviewThe XMEGA A3 features one two-channel, 12-bit, 1 Msps DACs with built-in offset and gain calibration, see Figure 26-1 on page 43. A DAC converts a digital value into an analog signal. The DAC may use an internal 1.0 voltage as the upper limit for conversion, but it is also possible to use the supply voltage or any applied voltage in-between. The external reference input is shared with the ADC reference input. Figure 26-1. DAC overviewConfiguration Reference selection

Channel A Register

Channel A

DACChannel B Register Channel B

Event Trigger

The DAC has one continuous output with high drive capabilities for both resistive and capacitive loads. It is also possible to split the continuous time channel into two Sample and Hold (S/H) channels, each with separate data conversion registers. A DAC conversion may be started from the application software by writing the data conversion registers. The DAC can also be configured to do conversions triggered by the Event System to have regular timing, independent of the application software. DMA may be used for transferring data from memory locations to DAC data registers. The DAC has a built-in calibration system to reduce offset and gain error when loading with a calibration value from software. PORTB each has one DAC. Notation of this peripheral is DACB.

OverviewXMEGA A3 features four Analog Comparators (AC). An Analog Comparator compares two voltages, and the output indicates which input is largest. The Analog Comparator may be configured to give interrupt requests and/or events upon several different combinations of input change. Both hysteresis and propagation delays may be adjusted in order to find the optimal operation for each application. A wide range of input selection is available, both external pins and several internal signals can be used. The Analog Comparators are always grouped in pairs (AC0 and AC1) on each analog port. They have identical behavior but separate control registers. Optionally, the state of the comparator is directly available on a pin. PORTA and PORTB each has one AC pair. Notations are ACA and ACB, respectively.

XMEGA A328. OCD - On-chip Debug28.1 Features Complete Program Flow Control Go, Stop, Reset, Step into, Step over, Step out, Run-to-Cursor Debugging on C and high-level language source code level Debugging on Assembler and disassembler level 1 dedicated program address or source level breakpoint for AVR Studio / debugger 4 Hardware Breakpoints Unlimited Number of User Program Breakpoints Unlimited Number of User Data Breakpoints, with break on: Data location read, write or both read and write Data location content equal or not equal to a value Data location content is greater or less than a value Data location content is within or outside a range Bits of a data location are equal or not equal to a value Non-Intrusive Operation No hardware or software resources in the device are used High Speed Operation No limitation on debug/programming clock frequency versus system clock frequency

28.2

OverviewThe XMEGA A3 has a powerful On-Chip Debug (OCD) system that - in combination with Atmels development tools - provides all the necessary functions to debug an application. It has support for program and data breakpoints, and can debug an application from C and high level language source code level, as well as assembler and disassembler level. It has full Non-Intrusive Operation and no hardware or software resources in the device are used. The ODC system is accessed through an external debugging tool which connects to the JTAG or PDI physical interfaces. Refer to Program and Debug Interfaces on page 48.

OverviewThe programming and debug facilities are accessed through the JTAG and PDI physical interfaces. The PDI physical interface uses one dedicated pin together with the Reset pin, and no general purpose pins are used. JTAG uses four general purpose pins on PORTB. The PDI is an Atmel proprietary protocol for communication between the microcontroller and Atmels or third party development tools.

29.3

IEEE 1149.1 (JTAG) Boundary-scan

The JTAG physical layer handles the basic low-level serial communication over four I/O lines named TMS, TCK, TDI, and TDO. It complies to the IEEE Std. 1149.1 for test access port and boundary scan.

29.3.1

Boundary-scan Order Table 30-8 on page 53 shows the Scan order between TDI and TDO when the Boundary-scan chain is selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The scan order follows the pin-out order. Bit 4, 5, 6 and 7 of Port B is not in the scan chain, since these pins constitute the TAP pins when the JTAG is enabled.

29.3.2

Boundary-scan Description Language Files Boundary-scan Description Language (BSDL) files describe Boundary-scan capable devices in a standard format used by automated test-generation software. The order and function of bits in the Boundary-scan Data Register are included in this description. BSDL files are available for ATxmega256/192/128/64A3 devices. See Table 30-8 on page 53 for ATxmega256/192/128/64A3 Boundary Scan Order.

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XMEGA A330. Pinout and Pin FunctionsThe pinout of XMEGA A3 is shown in on page 2. In addition to general I/O functionality, each pin may have several function. This will depend on which peripheral is enabled and connected to the actual pin. Only one of the alternate pin functions can be used at time.

30.130.1.1

Alternate Pin Function Description

The tables below show the notation for all pin functions available and describe its function. Operation/Power SupplyVCC AVCC GND Digital supply voltage Analog supply voltage Ground

30.1.2

Port Interrupt functions

SYNC ASYNC Port pin with full synchronous and limited asynchronous interrupt function Port pin with full synchronous and full asynchronous interrupt function

XMEGA A334. Electrical CharacteristicsAll typical values are measured at T = 25C unless other temperature condition is given. All minimum and maximum values are valid across operating temperature and voltage unless other conditions are given.

34.1

Absolute Maximum Ratings*

*NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

1. All Power Reduction Registers set. 2. All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1 MHz External clock with no prescaling.

35.12 PDI Speed

Figure 35-42. PDI Speed vs. Vcc35 30 25fMAX [MHz]

25 C

20 15 10 5 0 1.6 1.8 2 2.2 2.4 2.6 VCC [V] 2.8 3 3.2 3.4 3.6

928068TAVR12/10

XMEGA A336. Errata36.136.1.1

ATxmega256A3rev. E Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously VCC voltage scaler for AC is non-linear ADC has increased INL error for some operating conditions ADC gain stage output range is limited to 2.4 V ADC Event on compare match non-functional Bandgap measurement with the ADC is non-functional when VCC is below 2.7V Accuracy lost on first three samples after switching input to ADC gain stage Configuration of PGM and CWCM not as described in XMEGA A Manual PWM is not restarted properly after a fault in cycle-by-cycle mode BOD will be enabled at any reset DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V DAC has increased INL or noise for some operating conditions DAC refresh may be blocked in S/H mode Conversion lost on DAC channel B in event triggered mode EEPROM page buffer always written when NVM DATA0 is written Pending full asynchronous pin change interrupts will not wake the device Pin configuration does not affect Analog Comparator Output NMI Flag for Crystal Oscillator Failure automatically cleared Crystal start-up time required after power-save even if crystal is source for RTC RTC Counter value not correctly read after sleep Pending asynchronous RTC-interrupts will not wake up device TWI Transmit collision flag not cleared on repeated start Clearing TWI Stop Interrupt Flag may lock the bus TWI START condition at bus timeout will cause transaction to be dropped TWI Data Interrupt Flag (DIF) erroneously read as set WDR instruction inside closed window will not issue reset

1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as input for another AC, the first comparator will be affected for up to 1 s and could potentially give a wrong comparison result. Problem fix/Workaround If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before enabling any of them. 2. VCC voltage scaler for AC is non-linear The 6-bit VCC voltage scaler in the Analog Comparators is non-linear.

Problem fix/Workaround Use external voltage input for the analog comparator if accurate voltage levels are needed 3. ADC has increased INL error for some operating conditions Some ADC configurations or operating condition will result in increased INL error. In signed mode INL is increased to: 6LSB for sample rates above 1Msps, and up to 8 LSB for 2Msps sample rate. 6LSB for reference voltage below 1.1V when VCC is above 3.0V. 20LSB for ambient temperature below 0 degree C and reference voltage below 1.3V. In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used. Problem fix/Workaround None, avoid using the ADC in the above configurations in order to prevent increased INL error. Use the ADC in signed mode also for single ended measurements. 4. ADC gain stage output range is limited to 2.4 V The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential input will only give correct output when below 2.4 V/gain. For the available gain settings, this gives a differential input range of: 1x 2x 4x 8x 16x 32x 64x gain: gain: gain: gain: gain: gain: gain: 2.4 1.2 0.6 300 150 75 38 V V V mV mV mV mV

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XMEGA A3Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a correct result, or keep ADC voltage reference below 2.4 V. 5. ADC Event on compare match non-functional ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to BELOW or ABOVE. Problem fix/Workaround Enable and use interrupt on compare match when using the compare function. 6. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V The ADC can not be used to do bandgap measurements when VCC is below 2.7V. Problem fix/Workaround None. 7. Accuracy lost on first three samples after switching input to ADC gain stage Due to memory effect in the ADC gain stage, the first three samples after changing input channel must be disregarded to achieve 12-bit accuracy. Problem fix/Workaround Run three ADC conversions and discard these results after changing input channels to ADC gain stage. 8. Configuration of PGM and CWCM not as described in XMEGA A Manual Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM), but not Common Waveform Channel Mode. Enabling Pattern Generation Mode (PGM) and not Common W aveform Channel Mode (CWCM) will enable both Pattern Generation Mode and Common Waveform Channel Mode. Problem fix/Workaround Table 36-1. Configure PWM and CWCM according to this table:PGM 0 0 1 1 CWCM 0 1 0 1 Description PGM and CWCM disabled PGM enabled PGM and CWCM enabled PGM enabled

9. PWM is not restarted properly after a fault in cycle-by-cycle mode When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present. Problem fix/Workaround Do a write to any AWeX I/O register to re-enable the output. 10. BOD will be enabled after any reset If any reset source goes active, the BOD will be enabled and keep the device in reset if the VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be released until VCC is above the programmed BOD level even if the BOD is disabled.

958068TAVR12/10

XMEGA A3Problem fix/Workaround Do not set the BOD level higher than VCC even if the BOD is not used. 11. DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V Using the DAC with a reference voltage above 2.4V or VCC - 0.6V will give inaccurate output when converting codes that give below 0.75V output: 10 LSB for continuous mode 200 LSB for Sample and Hold mode Problem fix/Workaround None. 12. DAC has increased INL or noise for some operating conditions Some DAC configurations or operating condition will result in increased output error. Continous mode: 5 LSB Sample and hold mode: 15 LSB Sample and hold mode for reference above 2.0v: up to 100 LSB Problem fix/Workaround None. 13. DAC refresh may be blocked in S/H mode If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this will block refresh signals to the second channel. Problem fix/Workaround When using the DAC in S/H mode, ensure that none of the channels is running at maximum conversion rate, or ensure that the conversion rate of both channels is high enough to not require refresh. 14. Conversion lost on DAC channel B in event triggered mode If during dual channel operation channel 1 is set in auto trigged conversion mode, channel 1 conversions are occasionally lost. This means that not all data-values written to the Channel 1 data register are converted. Problem fix/Workaround Keep the DAC conversion interval in the range 000-001 (1 and 3 CLK), and limit the Peripheral clock frequency so the conversion internal never is shorter than 1.5 s. 15. EEPROM page buffer always written when NVM DATA0 is written If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM page buffer. Problem fix/Workaround Before writing to NVM DATA0, for example when doing software CRC or flash page buffer write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM DATA0 when EELOAD is set.

968068TAVR12/10

XMEGA A316. Pending full asynchronous pin change interrupts will not wake the device Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. This applies when entering all sleep modes where the System Clock is stopped. Problem fix/Workaround None. 17. Pin configuration does not affect Analog Comparator output The Output/Pull and inverted pin configuration does not affect the Analog Comparator output. Problem fix/Workaround None for Output/Pull configuration. For inverted I/O, configure the Analog Comparator to give an inverted result (i.e. connect positive input to the negative AC input and vice versa), or use and external inverter to change polarity of Analog Comparator output. 18. NMI Flag for Crystal Oscillator Failure automatically cleared NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI interrupt handler. Problem fix/Workaround This device revision has only one NMI interrupt source, so checking the interrupt source in software is not required. 19. Crystal start-up time required after power-save even if crystal is source for RTC Even if 32.768 kHz crystal is used for RTC during sleep, the clock from the crystal will not be ready for the system before the specified start-up time. See "XOSCSEL[3:0]: Crystal Oscillator Selection" in XMEGA A Manual. If BOD is used in active mode, the BOD will be on during this period (0.5s). Problem fix/Workaround If faster start-up is required, go to sleep with internal oscillator as system clock. 20. RTC Counter value not correctly read after sleep If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to bit 0 of RTC PER as the device is entering sleep, the value in the RTC count register can not be read correctly within the first prescaled RTC clock cycle after wakeup. The value read will be the same as the value in the register when entering sleep. The same applies if RTC Compare Match is used as wake-up source. Problem fix/Workaround Wait at least one prescaled RTC clock cycle before reading the RTC CNT value. 21. Pending asynchronous RTC-interrupts will not wake up device Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. Problem fix/Workaround None.

978068TAVR12/10

XMEGA A322. TWI Transmit collision flag not cleared on repeated start The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only cleared on start. Problem fix/Workaround Clear the flag in software after address interrupt. 23. Clearing TWI Stop Interrupt Flag may lock the bus If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets this flag due to a new address received, CLKHOLD is not cleared and the SCL line is not released. This will lock the bus. Problem fix/Workaround Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for the SCL pin to be low before clearing APIF. Code:/* Only clear the interrupt flag if within a "safe zone". */ while ( /* Bus not IDLE: */ ((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) != TWI_MASTER_BUSSTATE_IDLE_gc)) && /* SCL not held by slave: */ !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Ensure that the SCL line is low */ if ( !(COMMS_PORT.IN & PIN1_bm) ) if ( !(COMMS_PORT.IN & PIN1_bm) ) break; } /* Check for an pending address match interrupt */ if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Safely clear interrupt flag */ COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm; }

24. TWI START condition at bus timeout will cause transaction to be dropped If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected, the transaction will be dropped. Problem fix/Workaround None. 25. TWI Data Interrupt Flag erroneously read as set When issuing the TWI slave response command CMD=0b11, it takes 1 Peripheral Clock cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command will show the DIF still set. Problem fix/Workaround Add one NOP instruction before checking DIF.

988068TAVR12/10

XMEGA A326. WDR instruction inside closed window will not issue reset When a WDR instruction is execute within one ULP clock cycle after updating the window control register, the counter can be cleared without giving a system reset. Problem fix/Workaround Wait at least one ULP clock cycle before executing a WDR instruction.

998068TAVR12/10

XMEGA A336.1.2 rev. B Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously VCC voltage scaler for AC is non-linear ADC has increased INL error for some operating conditions ADC gain stage output range is limited to 2.4 V ADC Event on compare match non-functional Bandgap measurement with the ADC is non-functional when VCC is below 2.7V Accuracy lost on first three samples after switching input to ADC gain stage Configuration of PGM and CWCM not as described in XMEGA A Manual PWM is not restarted properly after a fault in cycle-by-cycle mode BOD will be enabled at any reset DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V DAC has increased INL or noise for some operating conditions DAC refresh may be blocked in S/H mode Conversion lost on DAC channel B in event triggered mode EEPROM page buffer always written when NVM DATA0 is written Pending full asynchronous pin change interrupts will not wake the device Pin configuration does not affect Analog Comparator Output NMI Flag for Crystal Oscillator Failure automatically cleared Writing EEPROM or Flash while reading any of them will not work Crystal start-up time required after power-save even if crystal is source for RTC RTC Counter value not correctly read after sleep Pending asynchronous RTC-interrupts will not wake up device TWI Transmit collision flag not cleared on repeated start Clearing TWI Stop Interrupt Flag may lock the bus TWI START condition at bus timeout will cause transaction to be dropped TWI Data Interrupt Flag (DIF) erroneously read as set WDR instruction inside closed window will not issue reset

1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as input for another AC, the first comparator will be affected for up to 1 s and could potentially give a wrong comparison result. Problem fix/Workaround If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before enabling any of them. 2. VCC voltage scaler for AC is non-linear The 6-bit VCC voltage scaler in the Analog Comparators is non-linear.

Problem fix/Workaround Use external voltage input for the analog comparator if accurate voltage levels are needed 3. ADC has increased INL error for some operating conditions Some ADC configurations or operating condition will result in increased INL error. In signed mode INL is increased to: 6LSB for sample rates above 1Msps, and up to 8LSB for 2Msps sample rate. 6LSB for reference voltage below 1.1V when VCC is above 3.0V. 20LSB for ambient temperature below 0 degree C and reference voltage below 1.3V. In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used. Problem fix/Workaround None, avoid using the ADC in the above configurations in order to prevent increased INL error. Use the ADC in signed mode also for single ended measurements. 4. ADC gain stage output range is limited to 2.4 V The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential input will only give correct output when below 2.4 V/gain. For the available gain settings, this gives a differential input range of: 1x 2x 4x 8x 16x 32x 64x gain: gain: gain: gain: gain: gain: gain: 2.4 1.2 0.6 300 150 75 38 V V V mV mV mV mV

1018068TAVR12/10

XMEGA A3Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a correct result, or keep ADC voltage reference below 2.4 V. 5. ADC Event on compare match non-functional ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to BELOW or ABOVE. Problem fix/Workaround Enable and use interrupt on compare match when using the compare function. 6. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V The ADC can not be used to do bandgap measurements when VCC is below 2.7V. Problem fix/Workaround None. 7. Accuracy lost on first three samples after switching input to ADC gain stage Due to memory effect in the ADC gain stage, the first three samples after changing input channel must be disregarded to achieve 12-bit accuracy. Problem fix/Workaround Run three ADC conversions and discard these results after changing input channels to ADC gain stage. 8. Configuration of PGM and CWCM not as described in XMEGA A Manual Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM), but not Common Waveform Channel Mode. Enabling Pattern Generation Mode (PGM) and not Common W aveform Channel Mode (CWCM) will enable both Pattern Generation Mode and Common Waveform Channel Mode. Problem fix/Workaround Table 36-2. Configure PWM and CWCM according to this table:PGM 0 0 1 1 CWCM 0 1 0 1 Description PGM and CWCM disabled PGM enabled PGM and CWCM enabled PGM enabled

9. PWM is not restarted properly after a fault in cycle-by-cycle mode When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present. Problem fix/Workaround Do a write to any AWeX I/O register to re-enable the output. 10. BOD will be enabled after any reset If any reset source goes active, the BOD will be enabled and keep the device in reset if the VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be released until VCC is above the programmed BOD level even if the BOD is disabled.

1028068TAVR12/10

XMEGA A3Problem fix/Workaround Do not set the BOD level higher than VCC even if the BOD is not used. 11. DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V Using the DAC with a reference voltage above 2.4V or VCC - 0.6V will give inaccurate output when converting codes that give below 0.75V output: 10 LSB for continuous mode 200 LSB for Sample and Hold mode Problem fix/Workaround None. 12. DAC has increased INL or noise for some operating conditions Some DAC configurations or operating condition will result in increased output error. Continous mode: 5 LSB Sample and hold mode: 15 LSB Sample and hold mode for reference above 2.0v: up to 100 LSB Problem fix/Workaround None. 13. DAC refresh may be blocked in S/H mode If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this will block refresh signals to the second channel. Problem fix/Workaround When using the DAC in S/H mode, ensure that none of the channels is running at maximum conversion rate, or ensure that the conversion rate of both channels is high enough to not require refresh. 14. Conversion lost on DAC channel B in event triggered mode If during dual channel operation channel 1 is set in auto trigged conversion mode, channel 1 conversions are occasionally lost. This means that not all data-values written to the Channel 1 data register are converted. Problem fix/Workaround Keep the DAC conversion interval in the range 000-001 (1 and 3 CLK), and limit the Peripheral clock frequency so the conversion internal never is shorter than 1.5 s. 15. EEPROM page buffer always written when NVM DATA0 is written If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM page buffer. Problem fix/Workaround Before writing to NVM DATA0, for example when doing software CRC or flash page buffer write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM DATA0 when EELOAD is set.

1038068TAVR12/10

XMEGA A316. Pending full asynchronous pin change interrupts will not wake the device Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. This applies when entering all sleep modes where the System Clock is stopped. Problem fix/Workaround None. 17. Pin configuration does not affect Analog Comparator output The Output/Pull and inverted pin configuration does not affect the Analog Comparator output. Problem fix/Workaround None for Output/Pull configuration. For inverted I/O, configure the Analog Comparator to give an inverted result (i.e. connect positive input to the negative AC input and vice versa), or use and external inverter to change polarity of Analog Comparator output. 18. NMI Flag for Crystal Oscillator Failure automatically cleared NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI interrupt handler. Problem fix/Workaround This device revision has only one NMI interrupt source, so checking the interrupt source in software is not required. 19. Writing EEPROM or Flash while reading any of them will not work The EEPROM and Flash cannot be written while reading EEPROM or Flash, or while executing code in Active mode. Problem fix/Workaround Enter IDLE sleep mode within 2.5 s (Five 2 MHz clock cycles and 80 32 MHz clock cycles) after starting an EEPROM or flash write operation. W ake-up source must either be EEPROM ready or NVM ready interrupt. Alternatively set up a Timer/Counter to give an overflow interrupt 7 ms after the erase or write operation has started, or 13 ms after atomic erase-and-write operation has started, and then enter IDLE sleep mode. 20. Crystal start-up time required after power-save even if crystal is source for RTC Even if 32.768 kHz crystal is used for RTC during sleep, the clock from the crystal will not be ready for the system before the specified start-up time. See "XOSCSEL[3:0]: Crystal Oscillator Selection" in XMEGA A Manual. If BOD is used in active mode, the BOD will be on during this period (0.5s). Problem fix/Workaround If faster start-up is required, go to sleep with internal oscillator as system clock. 21. RTC Counter value not correctly read after sleep If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to bit 0 of RTC PER as the device is entering sleep, the value in the RTC count register can not be read correctly within the first prescaled RTC clock cycle after wakeup. The value read will be the same as the value in the register when entering sleep. The same applies if RTC Compare Match is used as wake-up source.

1048068TAVR12/10

XMEGA A3Problem fix/Workaround Wait at least one prescaled RTC clock cycle before reading the RTC CNT value. 22. Pending asynchronous RTC-interrupts will not wake up device Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. Problem fix/Workaround None. 23. TWI Transmit collision flag not cleared on repeated start The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only cleared on start. Problem fix/Workaround Clear the flag in software after address interrupt. 24. Clearing TWI Stop Interrupt Flag may lock the bus If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets this flag due to a new address received, CLKHOLD is not cleared and the SCL line is not released. This will lock the bus. Problem fix/Workaround Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for the SCL pin to be low before clearing APIF. Code:/* Only clear the interrupt flag if within a "safe zone". */ while ( /* Bus not IDLE: */ ((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) != TWI_MASTER_BUSSTATE_IDLE_gc)) && /* SCL not held by slave: */ !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Ensure that the SCL line is low */ if ( !(COMMS_PORT.IN & PIN1_bm) ) if ( !(COMMS_PORT.IN & PIN1_bm) ) break; } /* Check for an pending address match interrupt */ if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Safely clear interrupt flag */ COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm; }

25. TWI START condition at bus timeout will cause transaction to be dropped If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected, the transaction will be dropped.

1058068TAVR12/10

XMEGA A3Problem fix/Workaround None. 26. TWI Data Interrupt Flag erroneously read as set When issuing the TWI slave response command CMD=0b11, it takes 1 Peripheral Clock cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command will show the DIF still set. Problem fix/Workaround Add one NOP instruction before checking DIF. 27. WDR instruction inside closed window will not issue reset When a WDR instruction is execute within one ULP clock cycle after updating the window control register, the counter can be cleared without giving a system reset. Problem fix/Workaround Wait at least one ULP clock cycle before executing a WDR instruction.

1068068TAVR12/10

XMEGA A336.1.3 rev. A Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously ADC gain stage output range is limited to 2.4V Sampled BOD in Active mode will cause noise when bandgap is used as reference Flash Power Reduction Mode can not be enabled when entering sleep mode JTAG enable does not override Analog Comparator B output Bandgap measurement with the ADC is non-functional when VCC is below 2.7V DAC refresh may be blocked in S/H mode BOD will be enabled after any reset Both DFLLs and both oscillators has to be enabled for one to work Operating frequency and voltage limitations Inverted I/O enable does not affect Analog Comparator Output

1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously If the bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as input for the another AC, the first comparator will be affected for up to 1 us and could potentially give a wrong comparison result. Problem fix/Workaround If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before enabling any of them. 2. ADC gain stage output range is limited to 2.4 V The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential input will only give correct output when below 2.4 V/gain. For the available gain settings, this gives a differential input range of: 1x 2x 4x 8x 16x 32x 64x gain: gain: gain: gain: gain: gain: gain: 2.4 1.2 0.6 300 150 75 38 V V V mV mV mV mV

Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a correct result, or keep ADC voltage reference below 2.4 V. 3. Sampled BOD in Active mode will cause noise when bandgap is used as reference Using the BOD in sampled mode when the device is running in Active or Idle mode will add noise on the bandgap reference for ADC, DAC and Analog Comparator. Problem fix/Workaround If the bandgap is used as reference for either the ADC, DAC and Analog Comparator, the BOD must not be set in sampled mode.

1078068TAVR12/10

XMEGA A34. Flash Power Reduction Mode can not be enabled when entering sleep mode If Flash Power Reduction Mode is enabled when a deep sleep mode, the device will only wake up on every fourth wake-up request. If Flash Power Reduction Mode is enabled when entering Idle sleep mode, the wake-up time will vary with up to 16 CPU clock cycles. Problem fix/Workaround Disable Flash Power Reduction mode before entering sleep mode. 5. JTAG enable does not override Analog Comparator B output When JTAG is enabled this will not override the Anlog Comparator B (ACB)ouput, AC0OUT on pin 7 if this is enabled. Problem fix/Workaround AC0OUT for ACB should not be enabled when JTAG is used. Use only analog comparator output for ACA when JTAG is used, or use the PDI as debug interface. 6. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V The ADC cannot be used to do bandgap measurements when VCC is below 2.7V. Problem fix/Workaround If internal voltages must be measured when VCC is below 2.7V, measure the internal 1.00V reference instead of the bandgap. 7. DAC refresh may be blocked in S/H mode If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this will block refresh signals to the second channel. Problem fix/Workarund When using the DAC in S/H mode, ensure that none of the channels is running at maximum conversion rate, or ensure that the conversion rate of both channels is high enough to not require refresh. 8. BOD will be enabled after any reset If any reset source goes active, the BOD will be enabled and keep the device in reset if the VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be released until VCC is above the programmed BOD level even if the BOD is disabled. Problem fix/Workaround Do not set the BOD level higher than VCC even if the BOD is not used. 9. Both DFLLs and both oscillators has to be enabled for one to work In order to use the automatic runtime calibration for the 2 MHz or the 32MHz internal oscillators, the DFLL for both oscillators and both oscillators has to be enabled for one to work. Problem fix/Workaround Enable both the DFLLs and both oscillators when using automatic runtime calibration for one of the internal oscillators.

Safe operating area

Problem fix/Workaround None, avoid using the device outside these frequnecy and voltage limitations. 11. Inverted I/O enable does not affect Analog Comparator Output The inverted I/O pin function does not affect the Analog Comparator output function. Problem fix/Workarund Configure the analog comparator setup to give a inverted result (i.e. connect positive input to the negative AC input and vice versa), or use and externel inverter to change polarity of Analog Comparator Output.

1098068TAVR12/10

XMEGA A336.236.2.1

ATxmega192A3, ATxmega128A3, ATxmega64A3

rev. E Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously VCC voltage scaler for AC is non-linear ADC has increased INL error for some operating conditions ADC gain stage output range is limited to 2.4 V ADC Event on compare match non-functional Bandgap measurement with the ADC is non-functional when VCC is below 2.7V Accuracy lost on first three samples after switching input to ADC gain stage Configuration of PGM and CWCM not as described in XMEGA A Manual PWM is not restarted properly after a fault in cycle-by-cycle mode BOD will be enabled at any reset DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V DAC has increased INL or noise for some operating conditions DAC refresh may be blocked in S/H mode Conversion lost on DAC channel B in event triggered mode EEPROM page buffer always written when NVM DATA0 is written Pending full asynchronous pin change interrupts will not wake the device Pin configuration does not affect Analog Comparator Output NMI Flag for Crystal Oscillator Failure automatically cleared Crystal start-up time required after power-save even if crystal is source for RTC RTC Counter value not correctly read after sleep Pending asynchronous RTC-interrupts will not wake up device TWI Transmit collision flag not cleared on repeated start Clearing TWI Stop Interrupt Flag may lock the bus TWI START condition at bus timeout will cause transaction to be dropped TWI Data Interrupt Flag (DIF) erroneously read as set WDR instruction inside closed window will not issue reset

1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as input for another AC, the first comparator will be affected for up to 1 s and could potentially give a wrong comparison result. Problem fix/Workaround If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before enabling any of them. 2. VCC voltage scaler for AC is non-linear The 6-bit VCC voltage scaler in the Analog Comparators is non-linear.

Problem fix/Workaround Use external voltage input for the analog comparator if accurate voltage levels are needed 3. ADC has increased INL error for some operating conditions Some ADC configurations or operating condition will result in increased INL error. In signed mode INL is increased to: 6LSB for sample rates above 1Msps, and up to 8 LSB for 2Msps sample rate. 6LSB for reference voltage below 1.1V when VCC is above 3.0V. 20LSB for ambient temperature below 0 degree C and reference voltage below 1.3V. In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used. Problem fix/Workaround None, avoid using the ADC in the above configurations in order to prevent increased INL error. Use the ADC in signed mode also for single ended measurements. 4. ADC gain stage output range is limited to 2.4 V The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential input will only give correct output when below 2.4 V/gain. For the available gain settings, this gives a differential input range of: 1x 2x 4x 8x 16x 32x 64x gain: gain: gain: gain: gain: gain: gain: 2.4 1.2 0.6 300 150 75 38 V V V mV mV mV mV

1118068TAVR12/10

XMEGA A3Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a correct result, or keep ADC voltage reference below 2.4 V. 5. ADC Event on compare match non-functional ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to BELOW or ABOVE. Problem fix/Workaround Enable and use interrupt on compare match when using the compare function. 6. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V The ADC can not be used to do bandgap measurements when VCC is below 2.7V. Problem fix/Workaround None. 7. Accuracy lost on first three samples after switching input to ADC gain stage Due to memory effect in the ADC gain stage, the first three samples after changing input channel must be disregarded to achieve 12-bit accuracy. Problem fix/Workaround Run three ADC conversions and discard these results after changing input channels to ADC gain stage. 8. Configuration of PGM and CWCM not as described in XMEGA A Manual Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM), but not Common Waveform Channel Mode. Enabling Pattern Generation Mode (PGM) and not Common W aveform Channel Mode (CWCM) will enable both Pattern Generation Mode and Common Waveform Channel Mode. Problem fix/Workaround Table 36-3. Configure PWM and CWCM according to this table:PGM 0 0 1 1 CWCM 0 1 0 1 Description PGM and CWCM disabled PGM enabled PGM and CWCM enabled PGM enabled

9. PWM is not restarted properly after a fault in cycle-by-cycle mode When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present. Problem fix/Workaround Do a write to any AWeX I/O register to re-enable the output. 10. BOD will be enabled after any reset If any reset source goes active, the BOD will be enabled and keep the device in reset if the VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be released until VCC is above the programmed BOD level even if the BOD is disabled.

1128068TAVR12/10

XMEGA A3Problem fix/Workaround Do not set the BOD level higher than VCC even if the BOD is not used. 11. DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V Using the DAC with a reference voltage above 2.4V or VCC - 0.6V will give inaccurate output when converting codes that give below 0.75V output: 10 LSB for continuous mode 200 LSB for Sample and Hold mode Problem fix/Workaround None. 12. DAC has increased INL or noise for some operating conditions Some DAC configurations or operating condition will result in increased output error. Continous mode: 5 LSB Sample and hold mode: 15 LSB Sample and hold mode for reference above 2.0v: up to 100 LSB Problem fix/Workaround None. 13. DAC refresh may be blocked in S/H mode If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this will block refresh signals to the second channel. Problem fix/Workaround When using the DAC in S/H mode, ensure that none of the channels is running at maximum conversion rate, or ensure that the conversion rate of both channels is high enough to not require refresh. 14. Conversion lost on DAC channel B in event triggered mode If during dual channel operation channel 1 is set in auto trigged conversion mode, channel 1 conversions are occasionally lost. This means that not all data-values written to the Channel 1 data register are converted. Problem fix/Workaround Keep the DAC conversion interval in the range 000-001 (1 and 3 CLK), and limit the Peripheral clock frequency so the conversion internal never is shorter than 1.5 s. 15. EEPROM page buffer always written when NVM DATA0 is written If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM page buffer. Problem fix/Workaround Before writing to NVM DATA0, for example when doing software CRC or flash page buffer write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM DATA0 when EELOAD is set.

1138068TAVR12/10

XMEGA A316. Pending full asynchronous pin change interrupts will not wake the device Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. This applies when entering all sleep modes where the System Clock is stopped. Problem fix/Workaround None. 17. Pin configuration does not affect Analog Comparator output The Output/Pull and inverted pin configuration does not affect the Analog Comparator output. Problem fix/Workaround None for Output/Pull configuration. For inverted I/O, configure the Analog Comparator to give an inverted result (i.e. connect positive input to the negative AC input and vice versa), or use and external inverter to change polarity of Analog Comparator output. 18. NMI Flag for Crystal Oscillator Failure automatically cleared NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI interrupt handler. Problem fix/Workaround This device revision has only one NMI interrupt source, so checking the interrupt source in software is not required. 19. Crystal start-up time required after power-save even if crystal is source for RTC Even if 32.768 kHz crystal is used for RTC during sleep, the clock from the crystal will not be ready for the system before the specified start-up time. See "XOSCSEL[3:0]: Crystal Oscillator Selection" in XMEGA A Manual. If BOD is used in active mode, the BOD will be on during this period (0.5s). Problem fix/Workaround If faster start-up is required, go to sleep with internal oscillator as system clock. 20. RTC Counter value not correctly read after sleep If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to bit 0 of RTC PER as the device is entering sleep, the value in the RTC count register can not be read correctly within the first prescaled RTC clock cycle after wakeup. The value read will be the same as the value in the register when entering sleep. The same applies if RTC Compare Match is used as wake-up source. Problem fix/Workaround Wait at least one prescaled RTC clock cycle before reading the RTC CNT value. 21. Pending asynchronous RTC-interrupts will not wake up device Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. Problem fix/Workaround None.

1148068TAVR12/10

XMEGA A322. TWI Transmit collision flag not cleared on repeated start The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only cleared on start. Problem fix/Workaround Clear the flag in software after address interrupt. 23. Clearing TWI Stop Interrupt Flag may lock the bus If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets this flag due to a new address received, CLKHOLD is not cleared and the SCL line is not released. This will lock the bus. Problem fix/Workaround Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for the SCL pin to be low before clearing APIF. Code:/* Only clear the interrupt flag if within a "safe zone". */ while ( /* Bus not IDLE: */ ((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) != TWI_MASTER_BUSSTATE_IDLE_gc)) && /* SCL not held by slave: */ !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Ensure that the SCL line is low */ if ( !(COMMS_PORT.IN & PIN1_bm) ) if ( !(COMMS_PORT.IN & PIN1_bm) ) break; } /* Check for an pending address match interrupt */ if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Safely clear interrupt flag */ COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm; }

24. TWI START condition at bus timeout will cause transaction to be dropped If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected, the transaction will be dropped. Problem fix/Workaround None. 25. TWI Data Interrupt Flag erroneously read as set When issuing the TWI slave response command CMD=0b11, it takes 1 Peripheral Clock cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command will show the DIF still set. Problem fix/Workaround Add one NOP instruction before checking DIF.

1158068TAVR12/10

XMEGA A326. WDR instruction inside closed window will not issue reset When a WDR instruction is execute within one ULP clock cycle after updating the window control register, the counter can be cleared without giving a system reset. Problem fix/Workaround Wait at least one ULP clock cycle before executing a WDR instruction.

1168068TAVR12/10

XMEGA A336.2.2 rev. B Bandgap voltage input for the ACs can not be changed when used for both ACs simultaneously VCC voltage scaler for AC is non-linear ADC has increased INL error for some operating conditions ADC gain stage output range is limited to 2.4 V ADC Event on compare match non-functional Bandgap measurement with the ADC is non-functional when VCC is below 2.7V Accuracy lost on first three samples after switching input to ADC gain stage Configuration of PGM and CWCM not as described in XMEGA A Manual PWM is not restarted properly after a fault in cycle-by-cycle mode BOD will be enabled at any reset DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V DAC has increased INL or noise for some operating conditions DAC refresh may be blocked in S/H mode Conversion lost on DAC channel B in event triggered mode EEPROM page buffer always written when NVM DATA0 is written Pending full asynchronous pin change interrupts will not wake the device Pin configuration does not affect Analog Comparator Output NMI Flag for Crystal Oscillator Failure automatically cleared Writing EEPROM or Flash while reading any of them will not work Crystal start-up time required after power-save even if crystal is source for RTC RTC Counter value not correctly read after sleep Pending asynchronous RTC-interrupts will not wake up device TWI Transmit collision flag not cleared on repeated start Clearing TWI Stop Interrupt Flag may lock the bus TWI START condition at bus timeout will cause transaction to be dropped TWI Data Interrupt Flag (DIF) erroneously read as set WDR instruction inside closed window will not issue reset

1. Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously If the Bandgap voltage is selected as input for one Analog Comparator (AC) and then selected/deselected as input for another AC, the first comparator will be affected for up to 1 s and could potentially give a wrong comparison result. Problem fix/Workaround If the Bandgap is required for both ACs simultaneously, configure the input selection for both ACs before enabling any of them. 2. VCC voltage scaler for AC is non-linear The 6-bit VCC voltage scaler in the Analog Comparators is non-linear.

Problem fix/Workaround Use external voltage input for the analog comparator if accurate voltage levels are needed 3. ADC has increased INL error for some operating conditions Some ADC configurations or operating condition will result in increased INL error. In signed mode INL is increased to: 6LSB for sample rates above 1Msps, and up to 8 LSB for 2Msps sample rate. 6LSB for reference voltage below 1.1V when VCC is above 3.0V. 20LSB for ambient temperature below 0 degree C and reference voltage below 1.3V. In unsigned mode, the INL error cannot be guaranteed, and this mode should not be used. Problem fix/Workaround None, avoid using the ADC in the above configurations in order to prevent increased INL error. Use the ADC in signed mode also for single ended measurements. 4. ADC gain stage output range is limited to 2.4 V The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential input will only give correct output when below 2.4 V/gain. For the available gain settings, this gives a differential input range of: 1x 2x 4x 8x 16x 32x 64x gain: gain: gain: gain: gain: gain: gain: 2.4 1.2 0.6 300 150 75 38 V V V mV mV mV mV

1188068TAVR12/10

XMEGA A3Problem fix/Workaround Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a correct result, or keep ADC voltage reference below 2.4 V. 5. ADC Event on compare match non-functional ADC signalling event will be given at every conversion complete even if Interrupt mode (INTMODE) is set to BELOW or ABOVE. Problem fix/Workaround Enable and use interrupt on compare match when using the compare function. 6. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V The ADC can not be used to do bandgap measurements when VCC is below 2.7V. Problem fix/Workaround None. 7. Accuracy lost on first three samples after switching input to ADC gain stage Due to memory effect in the ADC gain stage, the first three samples after changing input channel must be disregarded to achieve 12-bit accuracy. Problem fix/Workaround Run three ADC conversions and discard these results after changing input channels to ADC gain stage. 8. Configuration of PGM and CWCM not as described in XMEGA A Manual Enabling Common Waveform Channel Mode will enable Pattern generation mode (PGM), but not Common Waveform Channel Mode. Enabling Pattern Generation Mode (PGM) and not Common W aveform Channel Mode (CWCM) will enable both Pattern Generation Mode and Common Waveform Channel Mode. Problem fix/Workaround Table 36-4. Configure PWM and CWCM according to this table:PGM 0 0 1 1 CWCM 0 1 0 1 Description PGM and CWCM disabled PGM enabled PGM and CWCM enabled PGM enabled

9. PWM is not restarted properly after a fault in cycle-by-cycle mode When the AWeX fault restore mode is set to cycle-by-cycle, the waveform output will not return to normal operation at first update after fault condition is no longer present. Problem fix/Workaround Do a write to any AWeX I/O register to re-enable the output. 10. BOD will be enabled after any reset If any reset source goes active, the BOD will be enabled and keep the device in reset if the VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be released until VCC is above the programmed BOD level even if the BOD is disabled.

1198068TAVR12/10

XMEGA A3Problem fix/Workaround Do not set the BOD level higher than VCC even if the BOD is not used. 11. DAC is nonlinear and inaccurate when reference is above 2.4V or VCC - 0.6V Using the DAC with a reference voltage above 2.4V or VCC - 0.6V will give inaccurate output when converting codes that give below 0.75V output: 10 LSB for continuous mode 200 LSB for Sample and Hold mode Problem fix/Workaround None. 12. DAC has increased INL or noise for some operating conditions Some DAC configurations or operating condition will result in increased output error. Continous mode: 5 LSB Sample and hold mode: 15 LSB Sample and hold mode for reference above 2.0v: up to 100 LSB Problem fix/Workaround None. 13. DAC refresh may be blocked in S/H mode If the DAC is running in Sample and Hold (S/H) mode and conversion for one channel is done at maximum rate (i.e. the DAC is always busy doing conversion for this channel), this will block refresh signals to the second channel. Problem fix/Workaround When using the DAC in S/H mode, ensure that none of the channels is running at maximum conversion rate, or ensure that the conversion rate of both channels is high enough to not require refresh. 14. Conversion lost on DAC channel B in event triggered mode If during dual channel operation channel 1 is set in auto trigged conversion mode, channel 1 conversions are occasionally lost. This means that not all data-values written to the Channel 1 data register are converted. Problem fix/Workaround Keep the DAC conversion interval in the range 000-001 (1 and 3 CLK), and limit the Peripheral clock frequency so the conversion internal never is shorter than 1.5 s. 15. EEPROM page buffer always written when NVM DATA0 is written If the EEPROM is memory mapped, writing to NVM DATA0 will corrupt data in the EEPROM page buffer. Problem fix/Workaround Before writing to NVM DATA0, for example when doing software CRC or flash page buffer write, check if EEPROM page buffer active loading flag (EELOAD) is set. Do not write NVM DATA0 when EELOAD is set.

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XMEGA A316. Pending full asynchronous pin change interrupts will not wake the device Any full asynchronous pin-change Interrupt from pin 2, on any port, that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. This applies when entering all sleep modes where the System Clock is stopped. Problem fix/Workaround None. 17. Pin configuration does not affect Analog Comparator output The Output/Pull and inverted pin configuration does not affect the Analog Comparator output. Problem fix/Workaround None for Output/Pull configuration. For inverted I/O, configure the Analog Comparator to give an inverted result (i.e. connect positive input to the negative AC input and vice versa), or use and external inverter to change polarity of Analog Comparator output. 18. NMI Flag for Crystal Oscillator Failure automatically cleared NMI flag for Crystal Oscillator Failure (XOSCFDIF) will be automatically cleared when executing the NMI interrupt handler. Problem fix/Workaround This device revision has only one NMI interrupt source, so checking the interrupt source in software is not required. 19. Writing EEPROM or Flash while reading any of them will not work The EEPROM and Flash cannot be written while reading EEPROM or Flash, or while executing code in Active mode. Problem fix/Workaround Enter IDLE sleep mode within 2.5 s (Five 2 MHz clock cycles and 80 32 MHz clock cycles) after starting an EEPROM or flash write operation. W ake-up source must either be EEPROM ready or NVM ready interrupt. Alternatively set up a Timer/Counter to give an overflow interrupt 7 ms after the erase or write operation has started, or 13 ms after atomic erase-and-write operation has started, and then enter IDLE sleep mode. 20. Crystal start-up time required after power-save even if crystal is source for RTC Even if 32.768 kHz crystal is used for RTC during sleep, the clock from the crystal will not be ready for the system before the specified start-up time. See "XOSCSEL[3:0]: Crystal Oscillator Selection" in XMEGA A Manual. If BOD is used in active mode, the BOD will be on during this period (0.5s). Problem fix/Workaround If faster start-up is required, go to sleep with internal oscillator as system clock. 21. RTC Counter value not correctly read after sleep If the RTC is set to wake up the device on RTC Overflow and bit 0 of RTC CNT is identical to bit 0 of RTC PER as the device is entering sleep, the value in the RTC count register can not be read correctly within the first prescaled RTC clock cycle after wakeup. The value read will be the same as the value in the register when entering sleep. The same applies if RTC Compare Match is used as wake-up source.

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XMEGA A3Problem fix/Workaround Wait at least one prescaled RTC clock cycle before reading the RTC CNT value. 22. Pending asynchronous RTC-interrupts will not wake up device Asynchronous Interrupts from the Real-Time-Counter that is pending when the sleep instruction is executed, will be ignored until the device is woken from another source or the source triggers again. Problem fix/Workaround None. 23. TWI Transmit collision flag not cleared on repeated start The TWI transmit collision flag should be automatically cleared on start and repeated start, but is only cleared on start. Problem fix/Workaround Clear the flag in software after address interrupt. 24. Clearing TWI Stop Interrupt Flag may lock the bus If software clears the STOP Interrupt Flag (APIF) on the same Peripheral Clock cycle as the hardware sets this flag due to a new address received, CLKHOLD is not cleared and the SCL line is not released. This will lock the bus. Problem fix/Workaround Check if the bus state is IDLE. If this is the case, it is safe to clear APIF. If the bus state is not IDLE, wait for the SCL pin to be low before clearing APIF. Code:/* Only clear the interrupt flag if within a "safe zone". */ while ( /* Bus not IDLE: */ ((COMMS_TWI.MASTER.STATUS & TWI_MASTER_BUSSTATE_gm) != TWI_MASTER_BUSSTATE_IDLE_gc)) && /* SCL not held by slave: */ !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Ensure that the SCL line is low */ if ( !(COMMS_PORT.IN & PIN1_bm) ) if ( !(COMMS_PORT.IN & PIN1_bm) ) break; } /* Check for an pending address match interrupt */ if ( !(COMMS_TWI.SLAVE.STATUS & TWI_SLAVE_CLKHOLD_bm) ) { /* Safely clear interrupt flag */ COMMS_TWI.SLAVE.STATUS |= (uint8_t)TWI_SLAVE_APIF_bm; }

25. TWI START condition at bus timeout will cause transaction to be dropped If Bus Timeout is enabled and a timeout occurs on the same Peripheral Clock cycle as a START is detected, the transaction will be dropped.

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XMEGA A3Problem fix/Workaround None. 26. TWI Data Interrupt Flag erroneously read as set When issuing the TWI slave response command CMD=0b11, it takes 1 Peripheral Clock cycle to clear the data interrupt flag (DIF). A read of DIF directly after issuing the command will show the DIF still set. Problem fix/Workaround Add one NOP instruction before checking DIF. 27. WDR instruction inside closed window will not issue reset When a WDR instruction is execute within one ULP clock cycle after updating the window control register, the counter can be cleared without giving a system reset. Problem fix/Workaround Wait at least one ULP clock cycle before executing a WDR instruction.

36.2.3

rev. A Not sampled.

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XMEGA A337. Datasheet Revision HistoryPlease note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision.

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