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Abstract:

A grid tied inverter connectable to an electricity grid having a DC to DC
current fed push-pull inverter to generate a current waveform from a DC
voltage source. The push-pull inverter includes a transformer having a
first side winding connectable to a battery and a second side winding
connectable to the grid. The first end of the second side winding is
connected between two diodes connected in series between a positive and
negative output rail and being oriented in the same direction. The second
end of the second side winding is connected between two capacitors
connected in series between the positive and negative output rail. A
further winding is connected at one end between the two capacitors and at
its other end between another two diodes connected in series between the
positive and negative output rail.

Claims:

1. A grid tied inverter connectable to an electricity grid, the grid tied
inverter comprising a DC to DC current fed push-pull inverter operable to
generate a current waveform from a DC voltage source, the current
waveform being substantially synchronised to the electricity grid, the
push-pull inverter comprising a transformer having first side winding
connectable to a battery and a second side winding connectable to the
grid, wherein a first end of the second side winding of the transformer
is connected between a first diode and a second diode, the first diode
and second diode being connected in series between a positive output rail
and a negative output rail and being oriented in the same direction; a
second end of the second side winding of the transformer is connected
between a first capacitor and a second capacitor, the first capacitor and
second capacitor being connected in series between the positive output
rail and the negative output rail; a further winding is connected at one
end between the first capacitor and the second capacitor, and is
connected at its other end between a third diode and a fourth diode, the
third diode and the fourth diode being connected in series between the
positive output rail and the negative output rail and both being oriented
in the same direction as the first diode and the second diode.

2. A grid tied inverter according to claim 1, wherein the further winding
has substantially the same number of turns as the second side transformer
winding.

3. A grid tied inverter according to claim 1, wherein the further winding
is connected at the one end to the first capacitor and the second
capacitor via a resistor.

4. A grid tied inverter according to claim 1, wherein a resistor is
connected across the first capacitor.

5. A grid tied inverter according to claim 1, wherein a resistor is
connected across the second capacitor.

6. A grid tied inverter according to claim 1, wherein a first field
effect transistor and a second field effect transistor are connected in
series between the positive rail and the negative rail, the body diodes
of each of the first and second field effect transistors being oriented
in the same direction; and the second end of the second transformer
winding is connected between the first and second field effect
transistors.

7. A grid tied inverter according to claim 6, wherein a fifth diode is
connected in series with the first field effect transistor between the
second end of the second winding and one of the positive and negative
rails, the fifth diode being oriented in the opposition direction to the
body diode of the first field effect transistor.

8. A grid tied inverter according to claim 7, wherein the fifth diode is
a Schottky diode.

9. A grid tied inverter according to claim 7, wherein a sixth diode is
connected in series with the second field effect transistor between the
second end of the second winding and the other of the positive and
negative rails, the sixth diode being oriented in the opposition
direction to the body diode of the second field effect transistor.

10. A grid tied inverter according to claim 9, wherein the sixth diode is
a Schottky diode.

11. A method of operating a grid tied inverter connectable to an
electricity grid, the grid tied inverter comprising a DC to DC current
fed push-pull inverter, the method comprising generating a current
waveform from a DC voltage source, the current waveform being
substantially synchronised to the electricity grid, the push-pull
inverter comprising a transformer having first side winding connectable
to a battery and a second side winding connectable to the grid, wherein a
first end of the second side winding of the transformer is connected
between a first diode and a second diode, the first diode and second
diode being connected in series between a positive output rail and a
negative output rail and being oriented in the same direction; a second
end of the second side winding of the transformer is connected between a
first capacitor and a second capacitor, the first capacitor and second
capacitor being connected in series between the positive output rail and
the negative output rail; a further winding is connected at one end
between the first capacitor and the second capacitor, and is connected at
its other end between a third diode and a fourth diode, the third diode
and the fourth diode being connected in series between the positive
output rail and the negative output rail and both being oriented in the
same direction as the first diode and the second diode.

12. A method according to claim 11, wherein the further winding has
substantially the same number of turns as the second side transformer
winding.

13. A method according to claim 11, wherein the further winding is
connected at the one end to the first capacitor and the second capacitor
via a resistor.

14. A method according to claim 11, wherein a resistor is connected
across the first capacitor.

15. A method according to claim 11, wherein a resistor is connected
across the second capacitor.

16. A method according to claim 11, wherein a first field effect
transistor and a second field effect transistor are connected in series
between the positive rail and the negative rail, the body diodes of each
of the first and second field effect transistors being oriented in the
same direction; and the second end of the second transformer winding is
connected between the first and second field effect transistors.

17. A method according to claim 16, wherein a fifth diode is connected in
series with the first field effect transistor between the second end of
the second winding and one of the positive and negative rails, the fifth
diode being oriented in the opposition direction to the body diode of the
first field effect transistor.

18. A method according to claim 17, wherein the fifth diode is a Schottky
diode.

19. A method according to claim 17, wherein a sixth diode is connected in
series with the second field effect transistor between the second end of
the second winding and the other of the positive and negative rails, the
sixth diode being oriented in the opposition direction to the body diode
of the second field effect transistor.

20. A method according to claim 19, wherein the sixth diode is a Schottky
diode.

21. A system comprising a grid tied inverter according to claim 1
connected between a DC source and the grid.

22. A computer program comprising computer readable instructions which,
when loaded onto a computer configure the computer to perform a method
according to claim 11.

23. A storage medium configured to store the computer program of claim 22
therein or thereon.

Description:

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a grid tied inverter, method and
system.

[0003] 2. Description of the Prior Art

[0004] It is becoming increasingly attractive for domestic consumers of
electricity to provide electricity for the grid. This is particularly
important given the rapid increase in electricity usage, especially
during peak demand.

[0005] It is possible to provide this electricity using so-called
"Grid-Tied Inverters". These are DC-DC converters which connect banks of
batteries to the grid. These inverters tend to be very large and
expensive.

[0006] It is an aim of the present invention to address these issues.

SUMMARY OF THE INVENTION

[0007] According to a first aspect, there is provided a grid tied inverter
connectable to an electricity grid, the grid tied inverter comprising a
DC to DC current fed push-pull converter operable to generate a current
waveform from a DC voltage source, the current waveform being
substantially synchronised to the electricity grid, the push-pull
converter comprising a transformer having a first side connectable to a
battery and a second side connectable to the grid, wherein each of the
two primary sides is connected to ground via a switching transistor; and
respective voltage clamps are connected between the respective primary
side of the transformer and the respective switching transistor, the
voltage clamp commutating the current from the respective primary side of
the transformer when the switching transistor is turned off.

[0008] The voltage clamp may comprise a capacitor connected to ground, and
a switching transistor connected in series with the capacitor.

[0009] The first side of the transformer may have a first winding which is
connected to a first transistor switch and a second transistor switch,
the second transistor switch is a field effect transistor having the
anode of the body diode connected to the first winding, whereby the first
switch is connected to ground and the second switch is connected to a
first capacitor, the first capacitor being connected between the second
switch and ground, wherein to allow current flow through the first
winding, the first switch is configured to be on and the second switch is
configured to be off, and after a predetermined period of current flow,
the first switch is configured to be off, whereby a predetermined period
thereafter the second switch is configured to be on.

[0010] Prior to the first switch being switched on again, the second
switch may be configured to be switched off.

[0011] According to another aspect, there is provided a method of
operating a grid tied inverter which is connectable to an electricity
grid, the grid tied inverter comprising a DC to DC current led push-pull
converter, the method comprising generating a current waveform from a DC
voltage source, the current waveform being substantially synchronised to
the electricity grid, the push-pull converter comprising a transformer
having a first side connectable to a battery and a second side
connectable to the grid, wherein each of the two primary sides is
connected to ground via a switching transistor; and respective voltage
clamps are connected between the respective primary side of the
transformer and the respective switching transistor, wherein in the
clamp, the method comprises commutating the current from the respective
primary side of the transformer when the switching transistor is turned
off.

[0012] The voltage clamp may comprise a capacitor connected to ground, and
a switching transistor connected in series with the capacitor.

[0013] The first side of the transformer may have a first winding which is
connected to a first transistor switch and a second transistor switch,
the second transistor switch is a field effect transistor having the
anode of the body diode connected to the first winding, whereby the first
switch is connected to ground and the second switch is connected to a
first capacitor, the first capacitor being connected between the second
switch and ground, wherein to allow current flow through the first
winding, the method comprises switching the first switch on and the
second switch off, and after a predetermined period of current flow,
switching the first switch off, whereby a predetermined period thereafter
switching the second switch on.

[0014] Prior to the first switch being switched on again, the second
switch may be switched off.

[0015] According to another aspect, there is provided a system comprising
a grid tied inverter according to any one of the above embodiments
connected between a DC voltage source and the grid.

[0016] There is also provided a computer program containing computer
readable instructions which when loaded onto a computer configure the
computer to perform a method according to any one of the embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other object, features and advantages of the
invention will be apparent from the following detailed description of
illustrative embodiments which is to be read in connection with the
accompanying drawings, in which:

[0018]FIG. 1 shows a block diagram according an embodiment of the present
invention;

[0021]FIG. 4 shows the secondary side of the transformer according to
embodiments of the present invention;

[0022] FIG. 5 shows a control loop which controls the duty cycle of the
circuit shown in FIG. 2;

[0023] FIGS. 6A to 6C show a first configuration of planar transformer;
and

[0024] FIGS. 7A to 7C show a second configuration of planar transformer.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] With reference to FIG. 1, a system 100 is shown. The system 100
comprises a battery 110, a DC to DC converter 120 and an unfolding
circuit 130. The DC to DC converter 120 and the unfolding circuit 130
form the grid tied inverter according to embodiments of the invention.

[0026] The unfolding circuit 130 is connected to a mains electricity
supply provided by the mains electricity grid (not shown) and the DC to
DC converter 120 is connected to the battery 110.

[0027] The battery 110 is, in embodiments, a 2 kWh battery which is
typically made up of a number of battery cells. Each battery cell may be
rated at 30 Ah. The battery 110 is a DC voltage source capable of
delivering around 1 kW of power at any one time. The invention is not
however, limited to this and any size and type of battery may be also
used in embodiments.

[0028] The grid tied inverter is connected to the battery 110. The DC to
DC converter 120 is connected to the battery 110 using, in embodiments,
standard IEC form power inlets, which will typically include an
integrated fuse unit (not shown). An example of this is a 4 pin XLR type
male socket.

[0029] The output waveform from the DC to DC converter 120 is shown in
FIG. 1. The output waveform from the DC to DC converter 120 is a current
waveform that resembles a fully rectified signal. In other words,
although the output from the DC to DC converter 120 is in fact a DC
current and is not produced using a bridge circuit, it resembles and is
shaped like a fully rectified signal as will be apparent from the
discussion of FIG. 2.

[0030] The unfolding circuit 130 receives the fully rectified signal and
switches the polarity of the output from the DC to DC converter 120 at
100 Hz to generate an AC signal that has an instantaneous voltage similar
to that of the electricity grid. In other words, alternating ones of the
"humps" of the current waveform generated by the DC to DC converter 120
are switched to an opposite polarity. The output of the unfolding circuit
130 is therefore an AC signal with a frequency of around 50 Hz to match
that of the grid. This is shown in FIG. 1.

[0031] Although the above describes the system 100 as being suitable in
one mode to transfer electricity which is stored on the battery 110 onto
the grid, the system 100 can equally be used in reverse. In other words,
the system 100 can operate in a second mode which allows the battery 110
to be charged using electricity supplied by the grid. Accordingly, one
embodiment provides a bidirectional current fed DC to DC converter which
relies on downstream unfolding circuitry to generated an AC waveform from
its output.

[0032] Referring to FIG. 2, the battery 110 is shown as connected to the
DC to DC converter 120. The components of the DC to DC converter 120 are
surrounded by a dashed box. The output of the DC to DC converter 120 is
fed into the unfolding circuit 130 whose components are surrounded by
another dashed box.

[0033] The operation of the DC to DC converter 120 will be described in
more detail with reference to FIG. 3. However, a description of the
structure of the DC to DC converter 120 and the unfolding circuit 130
will be provided with reference to FIG. 2.

[0034] The battery 110 is shown as a single cell device in FIG. 2
connected to the DC to DC converter 120. However, as noted above, in
embodiments, the battery 110 comprises a plurality of cells.

[0035] The battery 110 is connected across a decoupling capacitor C6. A
first terminal of a first switching transistor Q1 is connected in series
with the battery 110. Connected between the second terminal of the first
switching transistor Q1 and ground is a second switching transistor Q2. A
first terminal of a first inductor L1 is connected to the second terminal
of the first switching transistor Q1. The first switching transistor Q1,
the second switching transistor Q2 and the first inductor L1 are arranged
as a synchronous buck converter. The second terminal of the first
inductor L1 is connected to a split primary winding of a transformer. In
embodiments, the second terminal of the first inductor L1 is connected to
a first terminal of a first primary winding of the transformer and a
first terminal of a second primary winding of the transformer.

[0036] The first terminal of a third switching transistor Q3 is connected
to the second terminal of the first primary winding and the second
terminal of the third switching transistor Q3 is connected to ground. The
first terminal of a fourth switching transistor Q4 is connected to the
second terminal of the second primary winding and the second terminal of
the fourth switching transistor Q4 is connected to ground.

[0037] A first terminal of a fifth switching transistor Q5 is connected
between the second terminal of the first primary winding and the first
terminal of the third switching transistor Q3. A first capacitor C1 is
connected between the second terminal of the fifth switching transistor
Q5 and ground. A first terminal of a sixth switching transistor Q6 is
connected between the second terminal of the second primary winding and
the first terminal of the fourth switching transistor. A second capacitor
C2 is connected between the second terminal of the sixth switching
transistor Q6 and ground.

[0038] A first terminal of the secondary winding of the transformer is
connected to a second terminal of a third capacitor C3 and the first
terminal of a fourth capacitor C4. The second terminal of the fourth
capacitor C4 is connected to a negative rail. The first terminal of the
third capacitor C3 is connected to a positive rail. A cathode terminal of
a first diode D1 is also connected to the positive rail. The anode
terminal of the first diode D1 is connected to a second terminal of the
secondary winding of the transformer. The cathode terminal of a second
diode D2 is also connected to the second terminal of the secondary
winding of the transformer. The anode terminal of the second diode D2 is
connected to the negative rail.

[0039] The cathode terminal of the second diode D2 is connected to the
anode terminal of a third diode D3. An eighth switching transistor Q8 is
connected between the between the cathode terminal of the third diode D3
and the negative rail. A second terminal of a seventh switching
transistor Q7 is connected to the second terminal of the secondary
winding of the transformer. The first terminal of the seventh switching
transistor Q7 is connected to the cathode terminal of a fourth diode D4.
The second terminal of the fourth diode D4 is connected to the positive
rail. A fifth capacitor C5 is connected between the cathode terminal of
the fourth diode D4 and the negative rail. It should be noted here that
the third and fourth diodes D3 and D4 are Schottky diodes which exhibit a
fast switching capability and which have a low forward voltage drop.

[0040] As noted before, connected to the DC-DC converter 120 is an
unfolding circuit 130. The unfolding circuit 130 is connected in parallel
to the fifth capacitor C5. The unfolding circuit 130 includes a ninth to
twelfth switching transistor Q9-Q12. The ninth switching transistor Q9
has a first terminal connected to the positive rail and a second terminal
connected to a negative output line. The tenth switching transistor Q10
is connected between the positive rail and a positive output line. The
eleventh switching transistor Q11 is connected between the negative
output line and the negative rail, and the twelfth switching transistor
Q12 is connected between the negative rail and the positive output line.
The positive and negative output lines connect to the electricity grid.
In embodiments, filter circuitry is provided between the positive and
negative output lines and the electricity grid.

[0041] It should be noted here that the ninth to twelfth switching
transistors Q9 to Q12 are power MOSFET (Metal Oxide Semi-conductor Field
Effect Transistors) transistors. This means that a diode exists between
the drain (cathode) and source (anode) of the MOSFET. This is sometimes
referred to as the "body diode" and exists in any field effect type
transistor. In the ninth switching transistor Q9 the drain is connected
to the positive rail, in the tenth switching transistor Q10 the drain is
connected to the positive rail, in the eleventh switching transistor Q11,
the drain is connected to the negative output rail and in the twelfth
switching transistor Q12, the drain is connected to the positive output
rail.

[0042] In other words, in the first mode (battery to grid), the ninth to
twelfth switching transistors Q9 to Q12 are switched to generate an
appropriate output waveform, and in the second mode (grid to battery),
the ninth to twelfth switching transistors Q9 to Q12 are not switched
meaning that the body diode between the drain and source of each MOSFET
cause the ninth to twelfth switching transistors Q9 to Q12 to operate as
a full bridge rectifier which produces a fully rectified signal across
the fifth capacitor C5. This ensures that the grid tied inverter can
operate in both modes and is therefore bi-directional. This reduces the
size and cost of the grid tied inverter which might conventionally have
had one circuit operating in the first mode and a second, parallel,
circuit operating in the second mode.

[0043] Referring to FIG. 3, an explanation of the operation of the DC to
DC converter 120 will now be given.

[0044] As will be appreciated by the skilled person, the DC to DC
converter 120 is configured as a current fed push-pull converter. In
other words, the output from the DC to DC converter 120 resembles a
rectified current signal. This is different to conventional DC to DC
converter 120 in grid tied inverters which produce voltage waveforms.
However, any minor differences between the voltage waveform generated by
the grid tied inverter and the grid onto which the electricity is fed
will result in large currents being generated (due to the low resistance
of the grid and filters placed between the grid tied inverter and the
grid). Therefore, conventionally, designers have altered the resistance
characteristics of the filters to mitigate the large current values.
However, this is very complicated and results in complex circuitry.

[0045] In order to address this, the output from the DC to DC converter
120 is a current waveform. This reduces the need to adjust the filter
resistance and therefore reduces circuitry complexity.

[0046] In order to generate the current waveform, the duty cycle of the DC
to DC converter 120 is adjusted. The control mechanism to generate the
duty cycle will be explained later with reference to FIG. 5.

[0047] In addition to the DC to DC converter 120 being configured as a
current fed push-pull converter, additional switches Q1 and D2 are
included as shown in FIG. 2. The inclusion of the switches Q1 and Q2
provide an advantage. Although not conventional in the field of grid tied
inverters, if a current fed push-pull converter was used, it would only
be possible to produce current for an output line voltage above n.Vbat
(where n is the turns ratio of the transformer). In other words, it would
only be possible to generate an output voltage waveform between n.Vbat
and the peak voltage of the domestic supply. This is because for output
line voltages below this value, the voltage across the inductor L1 would
be 0V as the reflected voltage at the transformer side of L1 would be
equal to Vbat.

[0048] In order to generate an output line voltage across the range 0V to
peak line voltage (which in embodiments is 325V), when the voltage of the
line drops to n.Vbat, additional switches Q1 and Q2 are added. These two
switches form a Buck-Boost circuit. It is possible for the DC to DC
converter 120 to continuously operate in Buck-Boost mode. However, in
order to reduce switching losses, the Buck-Boost switches are only
operated when the line voltage is equal to of less than n.Vbat. In other
words, as the Buck-Boost mode is only required when the line voltage is
at or below n.Vbat, the Buck-Boost mode is only operated when the line
voltage is at or below n.Vbat.

[0049] In order to determine when to operate Buck-Boost mode, the voltage
across the battery is monitored. The product of the voltage across the
battery and the turns ratio of the transformer is calculated. This is
compared with the instantaneous output line voltage. When the result of
this comparison indicates that the output line voltage is less than the
product of the voltage across the battery and the turns ratio of the
transformer, the Buck-Boost mode is activated. It should be noted that
the mechanism to monitor the voltages and perform the calculation are not
described hereinafter as they would be appreciated by the skilled person.
For example, the process could be handled by a digital signal processor
based on voltage samples taken from the DC to DC converter circuitry.

[0050] In the following description, it should be noted that Q1 and Q2 are
switched. In other words, in the following description, the operation of
the circuit in Buck-Boost mode will be described.

[0051] During the "on" time of the duty cycle, Q1, Q3 and Q4 are switched
on (i.e. the switch is closed). In order to avoid "shoot-through" (i.e. a
shorted path to ground), Q2 is switched "off" or is an open switch. As
can be seen in graph A of FIG. 3, the drain voltage of Q2 during the "on"
time is the battery voltage. As Q3 and Q4 are switched on, the voltage
across both primary windings is 0V. Accordingly, the battery voltage
appears across the first inductor L1. This means that current (IL) flows
through the first inductor L1 and that current flows in the first and
second primary winding of the transformer. In embodiments, current IL/2
will flow in each of the first and second primary winding. As would be
appreciated by the skilled person, as no voltage appears across the first
and second primary winding, no voltage will appear across the secondary
winding. Accordingly, the output of the DC to DC converter 120 will be
the current supplied by the fifth capacitor C5.

[0052] During the "off" time of the duty cycle, Q1 is switched off and Q2
is switched on. In order to avoid shoot-through, there is a slight delay
between these transitions. During the first "off" time, Q3 is left on and
Q4 is switched off. As Q1 is switched off, the voltage across the first
inductor L1 reverses. The sixth switching transistor Q6 is a MOSFET
transistor. Therefore, the drain of the sixth switching transistor Q6 is
connected to the second capacitor C2. Accordingly, even though the sixth
switching transistor Q6 is switched off, the diode effect within the
sixth switching transistor Q6 acts as a commutation diode to reduce the
effect of the sudden change in the voltage across the second primary
winding of the transformer. The commutation diode clamps the peak voltage
across the fourth switching transistor Q4 to 2Vline/n where Vline is the
instantaneous voltage of the grid and n is the turns ratio of the
transformer, which in embodiments is 3 (i.e. 3 times the number of coils
on the secondary side of the transformer compared with the totality of
the primary side).

[0053] After a short delay of around 20 ns the sixth switching transistor
Q6 is switched on allowing current reversal. In other words, when Q6 is
switched on, current can flow out of the second capacitor C2 through Q6.
As current flows through the second primary winding, via Q6 and the
second capacitor C2, a voltage is induced in the secondary winding. This
forward biases first diode D1 and therefore transfers energy to the
unfolding circuit 130. This is shown by graph D in FIG. 3.

[0054] As is shown in graph F of FIG. 3, the drain current through the
sixth switching transistor Q6 varies linearly over the off time of the
duty cycle from +Il/2 to -Il/2. This is because the amp-seconds balance
on clamp capacitor C2 must be maintained. During the subsequent "on" part
of the duty cycle, Q4 needs to be switched on and Q6 needs to be switched
off. It is advantageous to switch Q6 off slightly before Q4 is switched
on. This is because as the current has reversed, the voltage across Q4
collapses allowing the turn-on of Q4 under zero voltage conditions. This
reduces switching losses and therefore improves the efficiency of the DC
to DC converter 120.

[0055] The next "on" time of the duty cycle is performed. In this, the
switches and operation is the same as the previous "on" time and so will
not be repeated here.

[0056] The next "off" time of the duty cycle is very similar to that
explained above. However, during this "off" time, Q4 is left on and Q3 is
switched off. Accordingly, Q5, which is a MOSFET switch, has a diode
effect across its body which commutates the current through the first
primary winding of the transformer. Therefore, the voltage across Q3 is
2VLine/n. Again, Q5 is switched on a short time later and the current
reverses. This means that the voltage across the transformer is -Vline/2.
As shown in graph F of FIG. 3, during this second "off" time, the drain
current through Q5 varies linearly over the off time of the duty cycle
from +Il/2 to -Il/2. Therefore, during the next "on" cycle, Q5 is
switched off slightly before Q3 is switched on and again, the voltage
across Q3 collapses allowing the turn-on of Q3 under zero voltage
conditions.

[0057] As noted above, this explanation refers to the circuit operating in
Buck-Boost mode. In other words, the above describes the operation of the
DC to DC converter 120 when the line voltage is less than or equal to
n.Vbat. When the line voltage is greater than n.Vbat, the DC to DC
converter will operate in a Boost mode. In this situation, the switching
of all the transistors is the same except Q2 is always off. Therefore, in
the case that the DC to DC converter 120 is operating in the Boost mode,
the voltage across L1 during the off-time drops from Vline/n to
(Vline/n)-Vbat.

[0058] This means that when the DC to DC converter 120 switches between
operating in Boost mode to Buck-Boost mode, the current through the
inductor L1 can change rapidly. In order to reduce the effect of this,
the Buck-Boost mode is activated slightly early. In other words, although
it is possible to start operating in Buck-Boost mode when the line
voltage is less than or equal to n.Vbat, the DC to DC converter 120
begins operating in Buck Boost mode when the output line voltage is
n.Vbat+δ (where δ is a small voltage around 1.5V). Similarly,
although it is possible to stop operating in Buck-Boost mode when the
line voltage is greater than n.Vbat, the DC to DC converter 120 stops
operating in Buck-Boost mode (and in Boost mode alone), when the output
line voltage reaches n.Vbat+δ.

[0059] Although the above describes activating the Buck-Boost mode early
by identifying when the output line voltage reaches n.Vbat+δ,
potentially noise on the output line could inadvertently trigger a switch
in the mode. In order to reduce the possibility of this, in embodiments
the timing of the switch is changed. In other words, the Buck-Boost mode
is triggered earlier in time than would normally be anticipated (rather
than using voltage as the trigger). In order to achieve this, the phase
of the output line voltage is monitored. During a complete cycle of the
output voltage, the phase of the output will vary between 0 and
360°. The phase selected as the change over phase varies depending
on the ratio of output line voltage to battery voltage. However, in
typical embodiments, the phase at switch will be around 37°.

[0060] As noted hereinbefore, the above allows the DC to DC converter 120
to generate a current waveform that resembles a fully rectified AC
current waveform at the output of the DC to DC converter 120. In order to
apply this to the grid, the unfolding circuit 130 needs to generate a
full-wave rectified sinusoid having an instantaneous voltage matching the
grid. In order to achieve this, the unfolding circuit 130 is commutated
at 100 Hz. In other words, the switching transistors Q10 and Q11 are
commutated as one pair, and switching transistors Q9 and Q12 are
commutated as a second pair. By commutating the switching transistors in
this manner, the switching losses are reduced compared to conventional
techniques where typical bridges are commutated at higher frequencies
such as 20-50 kHz.

[0061] As noted above, the output current from the DC to DC converter 120
flows in D1 and D2. These two diodes act as rectifier diodes. Q7 and Q8
are MOSFETs. As such, they have body diodes. Q7 and Q8 also operate only
when the grid tied inverter operates in the grid to battery mode as will
be explained later. Therefore, during the battery to grid mode (or first
mode) Q7 and Q8 are left off. However, even though Q7 and Q8 are off, as
Q7 and Q8 are field effect transistors, they have a body diode effect
even when switched off. To prevent the reverse recovery current of the
body diodes from reducing efficiency, Schottky diodes D3 and D4 prevent
current flow onto the positive and negative lines. In other words,
Schottky diodes D3 and D4, are orientated to oppose the orientation of
the body diodes of Q7 and Q8. If the Schottky diodes D3 and D4 were not
present, the reverse recovery current of these body diodes circulates and
appear on the primary side of the transformer. In embodiments, the
reverse recovery current appears in the loop comprising of Q3 and Q4
during the "on" time. This increases the conduction losses for these
devices. It should be noted here that any other type of diode would
suffice (i.e. Schottky diodes are not necessary). However, Schottky
diodes are better than any other type of diode because they have a lower
turn on voltage which improves the efficiency of the circuit.

[0062] The operation of the circuit in the second mode (or grid to battery
mode) will now be described. In the second mode, the transistors Q9 to
Q12 (unfolding circuitry) are not switched, and remain static to form a
rectifier circuit. In order to operate in the second mode, Q7 and Q8 are
switched. Clearly, in order to avoid cross conduction, Q7 and Q8 are not
switched to be "on" at the same time.

[0063] During the even "on" time during the grid to battery mode Q7 is
switched on meaning that Q8 remains off. Current flows from the grid,
through D4 and into the transformer winding (via C3). This induces a
voltage of Vline/2 across C3 and thus the transformer winding. In
buck-boost mode during the grid to battery mode, Q3 and Q6 are on, Q1 is
off, and Q2 is on. This results in a voltage of n.Vline/2 being applied
across L1. Due to the split winding, a voltage of Vline/n appears across
Q4.

[0064] During the buck-boost "off" time, Q6 is switched off first. This
reduces the voltage across Q4 to zero so that when Q4 is switched on
during the next buck-boost "on" time, Q4 can be switched under zero
voltage conditions which reduces losses significantly. This has already
been explained with reference to the battery to grid mode. It should be
noted however that during this "off" time, Q4 is still off. Additionally,
Q7 is switched off. Thus, during this "off" time, Q6, Q7 and Q8 are off
and Q2, Q3 and Q4 are on. Accordingly, the transformer voltage is zero
with a current of IL/2 flowing through each of the primary winding legs.
The voltage across L1 is therefore Vbat.

[0065] During the odd "on" time, Q8 is switched on and Q7 is off. Current
flows from the grid, through D3 and into the transformer winding (via
C4). This induces a voltage of Vline/2 across C4 and thus the transformer
winding. Therefore, a voltage of n.Vline/2 appears across L1.

[0066] It should be noted that the voltage appearing across nVline/2
assumes that the voltage across C3 and C4 is the same during each
switching cycle. Although for the majority of cases, this is correct,
there is a slight possibility that this may not always be the case. In
the case that the voltage across C3 and C4 is not the same during each
switching cycle, an imbalance in L1 occurs. This is because the voltage
across C3 and C4 during the respective cycles appears across the
transformer which charges L1. Therefore, over a number of cycles, the
imbalance in L1 increases the difference between the voltages across C3
and C4. In other words, the presence of L1 acts to increase a voltage
difference across the transformer during successive "odd" and "even" on
times. This positive feedback results in saturation of the transformer
core. As would be appreciated, during saturation, the transformer acts as
a short circuit. As will be explained later, a balance winding may be
introduced into the circuit to mitigate this effect.

[0067] An example circuit configuration for the balance winding is
schematically illustrated in FIG. 4. As will be appreciated from a
comparison of FIG. 4 and FIG. 2, FIG. 4 shows a portion of the secondary
side circuitry of the DC-DC inverter 120 shown in FIG. 2, with like
circuit elements being indicated with like reference numerals. The
secondary side transformer winding is identified in FIG. 4 as T2. In
addition, FIG. 4 shows a number of additional circuit elements which are
intended to prevent, or at least reduce, the incidence of transformer
saturation. This additional circuitry includes a further winding TB which
is connected at one end via a resistor R1 between the capacitor C3 and
the capacitor C4, and is connected at its other end between a diode D5
and a diode D6. The diodes D5 and D6 are connected in series between the
positive output rail and the negative output rail and are both oriented
in the same direction (that is, towards one or other of the positive
output rail and the negative output rail) as the diode D1 and the diode
D2.

[0068] As will be appreciated, it is desirable that the end of the
transformer winding T2 between the capacitors C3 and C4 be stable. In an
ideal circuit, the voltage drop across C3 and C4 would be identical,
achieving this, but in a real circuit an imbalance may arise at this
point, resulting in transformer saturation. This is mitigated in the
present case by the further winding TB which functions as one half of a
potential divider, with the transformer winding T2 serving as the other
half of the potential divider. It will be appreciated that, by
configuring T2 and TB to store substantially the same amount of energy,
for example by using the same or a similar number of transformer turns
for each winding, the mid point between T2 and TB, and thus the mid point
between the capacitors C3 and C4, can be stabilised. The resistor R1
serves to reduce the effect of ripple voltages on the windings, with any
ripple voltages becoming superimposed across the resistor R1. If the
resistor R1 was not present, a large current would flow through the
balance winding.

[0069] In addition to the potential divider provided by the further
winding TB, the midpoint between the capacitors C3 and C4 is also
stabilised by connecting resistors R2 and R3 across the capacitors C3 and
C4. The resisters R2 and R3 have substantially the same resistance, and
form a further potential divider between the positive and negative rails
to stabilise the mid point while the grid tied inverter is not switching.

[0070] Returning to the discussion about the grid to battery mode, as with
the even "on" time, Q1 is off and Q2 is on. However, unlike the even "on"
time, Q4 is switched on (under zero voltage conditions explained above),
and Q5 is switched on. Q6 remains off and Q3 is switched off. The
operation of the circuit is then similar to that explained with reference
to the even "on" time. However, during the next "off" time, Q5 is
switched off first so that when Q3 is switched on during the next
buck-boost "on" time, Q5 can be switched under zero voltage conditions.

[0071] As with the battery to grid mode, in boost mode, Q1 is left on for
the entire switching cycle to reduce the voltage across the inductor
during the on time from Vline/n to (V line/n)-Vbat.

[0072] Control of the push-pull converter is implemented in part by
setting the duty cycle of the DC-DC converter 120. More particularly, the
ratio of the "on" time to the "off" time is varied with respect to time
to generate a desired current waveform. The desired current waveform for
output by the DC-DC converter 120 resembles a fully rectified AC current
waveform. In one embodiment, this is achieved by way of a DSP (Digital
Signal Processor) set reference current and inner and outer control
loops. FIG. 5 schematically illustrates such a control circuit 200 and
its connections to the DC-DC converter 120 and unfolding circuitry 130.

[0073] The control circuit 200 comprises an outer loop comparator 140
which receives a line current output Iline from the unfolding stage
130 and a digitally synthesised reference current Iref received from
a DSP (not shown). The outer loop comparator 140 generates an outer loop
error signal εouter from the difference
(Iline-Iref) between the received line current Iline and
the reference current Iref and passes this to an outer loop error
amplifier 145. The outer loop comparator 140 and the outer loop error
amplifier 145 serve as an outer control loop. The outer loop error
amplifier 145 amplifies the outer loop error signal εouter
generated by the outer loop comparator 140 and passes it to an inner loop
of the control circuit 200 as Eouter. In particular, the inner loop
comprises an inner loop comparator 150 which receives the amplified outer
loop error signal Eouter from the outer loop and a measured inductor
current Iind from the DC-DC converter 120. The inner loop comparator
150 generates an inner loop error signal εinner from the
difference (Iind-Eouter) between the measured inductor current
Iind and the amplified error signal Eouter from the outer loop.
The inner loop error signal εinner is then passed to an
inner loop error amplifier 155 which amplifies the inner loop error
signal generated by the inner loop comparator 150 and passes it to a
pulse width modulator 160, which used the amplified outer loop error
signal to modulate a saw tooth reference waveform to form a duty cycle
control signal Dctrl. The duty cycle control signal Dctrl then
serves to control the timing of the switching of the various transistors
described in FIG. 2. It will be appreciated that the duty cycle control
signal Dctrl may not directly control all of the switches--in some
cases an offset or inverted version of the duty cycle control signal
Dctrl will be used to drive a particular switch, resulting in a
desired relative timing delay between particular switch transitions.

[0074] It will be appreciated that the amplified outer loop error signal
Eouter represents a difference between the output current presently
being output from the unfolding stage 130 and a digitally controlled
reference current. It will be understood that the digitally controlled
reference current is in effect a target current which the analogue
circuitry of the DC-DC converter and the unfolding stage 130 is intended
to follow. This outer loop process therefore drives a relatively slow
change in the desired output line current. The inner control loop on the
other hand changed rapidly as a function of the inductor current. The
inductor current is in effect modulated in a particular direction by the
error signal generated from the outer control loop to achieve the desired
gradual change in line current via the duty cycle control signal
Dctrl.

[0075] As discussed above, the DC-DC converter is operable in both a buck
boost mode and a boost mode. The purpose of the buck boost mode is to
permit the output voltage to reach 0V, which is necessary in generating
the desired output waveform. However, the additional transistor switching
results in undesirable switching losses in the transistor Q2. In order to
reduce the impact of these switching losses, the buck boost mode is
active only during generation of a lower portion of a voltage waveform.
During the upper portion of the voltage waveform the buck boost topology
is not necessary to obtain the required voltage levels, and so a boost
mode is used in which the transistor Q2 remains on.

[0076] Although the foregoing has been discussed with reference to a
battery or batteries being the DC source, the invention is not so
limited. Any type of DC source may be equally used.

[0077] Also, although the foregoing has been described with reference to
circuit elements, in embodiments these elements may be controlled by a
computer program. Such a computer program comprises computer readable
instructions which, when loaded onto a computer configure the computer to
perform the method of the embodiments. This program may be stored on a
storage medium such as an optical disc or on a server for distribution on
a network. The software may be stored on memory within the grid tied
inverter which may provide the switching timings, for example using the
digital signal processor.

[0078] The above DC-DC converter comprises a transformer. Various
transformer types are possible. Planar transformers, for example
providing windings mounted on a plurality of printed circuit boards, are
known. A problem with such transformers is that the plural printed
circuit board need to be structurally and electrically connected together
during the assembly and manufacture process. More particularly, in a
conventional planar transformer the windings would be separately soldered
or welded together. It is believed that an increase in efficiency can be
accomplished by creating the transformer from stamped parts or PCB
sections and connecting these components using the main PCB, rather than
directly. This may be better from an assembly and manufacturing
perspective.

[0079] Referring to FIGS. 6A to 6C, a first configuration of such a planar
transformer, utilising a stepped design, is schematically illustrated.
Referring first to FIG. 6A, a primary winding is formed over three cards,
1:1, 1:2 and 1:3, each with a core receiving aperture 1112, 1114, 1116, a
first side winding track 1122, 1124, 1126, a second side winding track
1132, 1134, 1136 and different terminal positions 1142, 1144, 1146 at the
edge of the respective card. Each of the primary cards is intended for
location in a respectively labelled slot in FIG. 6c. A secondary winding
is shown in FIG. 6B, and is formed over three cards, 2:1, 2:2 and 2:3,
again each with a core receiving aperture 1212, 1214, 1216, a first side
winding track 1222, 1224, 1226, a second side winding track 1232, 1234,
1236 and different terminal positions 1242, 1244, 1246 at the edge of the
respective card. Each of the secondary cards is located at a respectively
labelled slot in FIG. 6c. FIG. 6c illustrates six slots of a motherboard
to which the PCR transformer (in the form of the six cards of FIGS. 6A
and 6B) is to be mounted. Connections between the slots in the
motherboard serve to complete the circuits of the primary and secondary
windings by connecting together the six cards. In a slot 1:1 dedicated to
the card 1:1, an input connection 1301 is provided which serves as a
first terminal for the primary winding. The other connection shown in
slot 1:1 is used to connect to the slot 1:2 dedicated to the card 1:2.
The slot 1:2 is connected to the slot 1:3 in a like manner. The slot 1:3
comprises an output connection 1303 which serves as a second terminal for
the primary winding. In a slot 2:1 dedicated to the card 2:1, an input
connection 1305 is provided which serves as a first terminal for the
secondary winding. The other connection shown in the slot 2:1 is used to
connect to the slot 2:2 dedicated to the card 2:2. The slot 2:2 is
connected to the slot 2:3 in a like manner. The slot 2:3 comprises an
output connection 1307 which serves as a second terminal for the
secondary winding. The edge terminals of the cards and slots are stepped
between cards to permit connections between slots.

[0080] Referring to FIGS. 7A to 7C, a second configuration of a planar
transformer, utilising a alternating design, is schematically
illustrated. Referring first to FIG. 7A, a primary winding is formed over
three identical cards A, each with a core receiving aperture 2112, 2114,
2116, a first side winding track 2122, 2124, 2126, a second side winding
track 2132, 2134, 2136 and the same terminal positions 2142, 2144, 2146
at the edge of the respective card. Each of the primary cards is intended
for location in a respectively labelled slot in FIG. 7C. A secondary
winding is shown in FIG. 7B, and is formed over three identical cards B,
again each with a core receiving aperture 2212, 2214, 2216, a first side
winding track 2222, 2224, 2226, a second side winding track 2232, 2234,
2236 and the same terminal positions 2242, 2244, 2246 at the edge of the
respective card. Each of the secondary cards is located at a respectively
labelled slot in FIG. 7C. FIG. 7C illustrates six slots of a motherboard
to which the PCB transformer (in the form of the six cards of FIGS. 7A
and 7B) is to be mounted. Connections between the slots in the
motherboard serve to complete the circuits of the primary and secondary
windings by connecting together the six cards. In a slot A1 dedicated to
one of the A cards, an input connection 2311 is provided which serves as
a first terminal for the primary winding. The other connection shown in
slot A1 is used to connect to the slot A2 dedicated to a second of the A
cards. The slot A2 is connected to the slot A3 in a like manner. The slot
A3 comprises an output connection 2313 which serves as a second terminal
for the primary winding. In a slot B1 dedicated to one of the B cards, an
input connection 2315 is provided which serves as a first terminal for
the secondary winding. The other connection shown in the slot B1 is used
to connect to the slot B2 dedicated to a second of the B cards. The slot
B2 is connected to the slot B3 in a like manner. The slot B3 comprises an
output connection 2317 which serves as a second terminal for the
secondary winding. The edge terminals of the cards are identical in this
embodiment, and the terminals within subsequent slots of a particular
winding are alternated in orientation to permit connections between
slots. In this case, current flow reverses each time so that the
cross-slot connection can alternate between one end of the slot and the
other. An advantage of this configuration is that each of the primary
cards (A) can be the same (no need to step the terminal positions), and
each of the secondary cards (B) can be the same.

[0081] A method of manufacturing a transformer is envisaged, comprising
the steps of:

[0082] providing a first plurality of cards carrying portions of a primary
winding, and a second plurality of cards carrying portions of a secondary
winding, each portion comprising an electrically conducting track having
two terminals at one edge of the card;

[0083] providing a board having a plurality of slots for receiving the
first plurality of cards and the second plurality of cards, the slots
being electrically connected together; and

[0084] inserting the first plurality of cards and the second plurality of
cards into the plurality of slots; wherein

[0085] the electrical connections within the plurality of slots complete a
circuit with the first plurality of cards to form the primary winding,
and complete a circuit with the second plurality of cards to form the
secondary winding.

[0086] Although illustrative embodiments of the invention have been
described in detail herein with reference to the accompanying drawings,
it is to be understood that the invention is not limited to those precise
embodiments, and that various changes and modifications can be effected
therein by one skilled in the art without departing from the scope and
spirit of the invention as defined by the appended claims.

Patent applications by SONY CORPORATION

Patent applications in class By semiconductor rectifier and inverter

Patent applications in all subclasses By semiconductor rectifier and inverter