VERILOG example using VIVADO 2015 with ZYBO FPGA board

Aim

In this tutorial I will use Verilog with classical FPGA design. I bought perfect modern FPGA board ZYBO (ZYnq BOard) based on Xilinx Z-7010 from Digilent but latest tools from Xilinx VIVADO 2015.2 more focused on AP SoC programming while I want to just pure FPGA design without any linuxes bootloaders etc. So I wrote this tutorial to help people like me 🙂

In this example we make simple scheme: 2 signals IN and 4 OUT.

Preconditions: Adding Zybo Board to Vivado

Vivado 2015.2 under Windows 7 64 bit was used with 16 GB of RAM.

Before using Zybo with Vivado you should add Zybo Definitions File to Vivado.