CPUs Up Close

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Amazingly, to this day the fundamental design of mainstream microprocessors and computers is still based on principles from the 1940s. The structure created by John Mauchly and J. Presper Eckert (developers of the ENIAC), and formalized by mathematician and computer scientist John Von Neumann, allowed memory to hold both program instructions and data. This stored program concept, later called Von Neumann Architecture, no longer required hard-wiring of instructions, enabling easy reprogramming and revolutionizing computing.

Today’s CPUs also utilize a Harvard Architecture loosely based on the Harvard Mark I from the 1940s, which had separate memory blocks for instructions and data. For example, modern processors generally divide the onboard L1 cache into separate instruction and data areas. (L2 and L3 caches, however, typically include both instructions and data, making them unified caches.)

Programs at the lowest levelthose communicating directly with the CPUmust be in machine language, which represents instructions and data for the processor as binary numbers. The last we looked, though, few people enjoy writing programs consisting of code like 1000101111010000. Assembly language, a slightly higher-level tool, eases the process by representing operations and data symbolically, resulting in directives like MOV AX, 9 instead of 101110000000100100000000. An assembler program then converts the symbolic code into machine language. Higher-level languages like C perform the translation using compiler software.

Many CPU instructions specify some operation, like add, multiply, or compare, to be carried out on an operanddata the processor often stores in registers (temporary internal holding locations), but may also fetch from cache or main memory. Different types of instructions may vary in length. Current CPUs, like the Pentium 4 and Athlon64, decode variable-length x86 instructions into one or a few simpler, fixed-length internal instructions called micro-ops, which are not accessible outside the CPU.

Although compatible microprocessors must produce identical results for identical instructions, internal designs and operation may be entirely different. For example, the AMD Athlon 64, unlike the Pentium 4, initially decodes an instruction into one or more intermediate macro-ops (complex instructions require several macro-ops), which are ultimately converted into one or more micro-ops.

Internal architecture may even differ within CPU families and in succeeding generations of highly compatible processor families, such as the Intel 386, 486, and Pentium. Later generations often add instruction-set enhancements such as MMX (Multimedia Extensions) and SSE (Streaming Single-Instruction, Multiple-Data Extensions) in the case of Intel processors. AMD64, which extended the AMD x86 architecture to enable 64-bit instructions and addressing, is another example.

Whatever their differences, though, processors execute instructions sequentially unless a comparison result, an external interrupt, or some other event causes a branch. A program counter in the CPU keeps track of which instruction is current and which to fetch next. The processor fetches data from memory (either on-board caches or external system RAM), places it in registers, performs calculations such as comparisons and string operations, and writes results to either internal registers or external memory.

An input clock signal keeps everything operating at a specific rate. Within the processor, the signal may be subdivided into multiple, higher-frequency clocks to synchronize higher-speed operations. But the big trick is organizing the processor’s architecture so instructions execute as efficiently and quickly as possible, a talent that ultimately influences the CPU’s cost, size, and performance.