Posts Tagged ‘forecast’

Editor’s Note: In Solid State Technology’s November 1995 Asia/Pacific Supplement this editor wrote of the PRC’s status and plans for IC fabs titled “Progress creeps forward”. SEMICON/China 1995 was held in a small hall in Shanghai with 125 exhibitors and 5000 attendees discussing production of just 245M ICs units having happened in the entire country in 1994. Motorola’s Fab17 in Tianjin was planned to be able to yield 360M IC from 200mm wafers.

China has been successfully investing in technology to reach global competitiveness for many decades. Integrated circuit (IC) manufacturing technology is highly strategic for countries, enabling both economically-valuable commercial fabs as well as military power. The Wassenaar Arrangement (WA) between 40-some states has restricted exports to China of “leading” technology with potential “dual-use” by industry and military. Using the terminology of IC fab nodes/generations, WA has typically restricted exports to fab tools capable of processing ICs three nodes behind (n-3) the leading edge of commercial capability (https://en.wikipedia.org/wiki/14_nanometer). In 1995 the leading edge was 0.35 microns, so 1 micron and above was the WA limit. In 2015 the leading edge is 14nm, so 45nm and above is the WA limit, but local capability has already effectively bypassed this restriction.

On February 9, 2015, trade-organization SEMI announced (http://www.semi.org/en/node/54596) the successful lobbying of the U.S. Department of Commerce to declare the export controls on certain etch equipment and technology ineffective, thereby allowing US equipment companies to sell high-volume manufacturing (HVM) tools with capabilities closer to the leading-edge into China. Following years of discussion and negotiations, SEMI had submitted a formal petition for the Commerce Department’s Bureau of Industry and Security (BIS) to examine the foreign availably of anisotropic plasma dry etching equipment, having identified AMEC (amec-inc.com) as providing an indigenous Chinese manufacturing capability. AMEC has announced that it’s tool is being used by Samsung for V-NAND HVM (https://finance.yahoo.com/news/amec-ships-advanced-etch-tool-150000063.html), which is certainly a “leading-edge” product that happens to be made using 45nm node (n-3) design rules.

“The Future is in the Past: Projecting and Plotting the Potential Rate of Growth and Trajectory of the Structural Change of the Chinese Economy for the Next 20 Years” by Jun Zhang et al. from the Institute of World Economics and Politics, Chinese Academy of Social Sciences was first published online in 2015 (DOI: 10.1111/cwe.12098). Thanks to economic growth at an average speed of more than 9.7% annually in China over the past 35 years, it is estimated that today’s China per capital GDP has already reached approximately 23% of the USA. Because of the significant rise in per-capita income over the past 30 years, China has started to see a rapid demographic transition and a gradual rise in labor costs as seen in other high-performing East Asian economies. Benchmarking to the experiences of East Asian high-performing economies from 1950 to 2010, this paper projects potential growth rate of per-capita GDP (adjusted by purchasing power parity) for China at ~6.02% from 2015 to 2035.

The PRC still works with 5-year-plans. Figure 1 shows Deng Xiaoping touring a government-run fab during the 8th 5-year-plan (1991-1995) when central planning of local resources dominated Chinese IC industry. Paramount leader Deng had famously proclaimed, “Poverty is not socialism. To be rich is glorious,” which allowed for private enterprise and different economic classes. As reported by Robert Lawrence Kuhn in 2007’s “What Will China Look Like in 2035” in Bloomberg Business (http://www.bloomberg.com/bw/stories/2007-10-16/what-will-china-look-like-in-2035-businessweek-business-news-stock-market-and-financial-advice), researchers at the Institute of Quantitative & Technical Economics of the Chinese Academy of Social Sciences—the official government think tank housing more than 3,000 scholars and researchers—in 2007 predict that by 2030 China’s economic reform will have been basically completed, such that the major issue will be the “adjustment of interests” among different classes.

Figure 1: Deng Xiaoping is shown Shanghai Belling’s fab by General Manager Lu Dechun during the 8th 5-year-plan (1991-1995). Such small fabs are not globally competitive. (Source: Ed Korczynski)

In 2014, McKinsey&Company published proprietary research (http://www.mckinsey.com/insights/high_tech_telecoms_internet/semiconductors_in_china_brave_new_world_or_same_old_story) that >50% of PCs, and 30-40% of embedded systems contain content designed in China, either directly by mainland companies or emerging from the Chinese labs of global players. Since fewer chip designs will be moving to technologies that are 22nm node and below, low-cost Chinese technology companies will soon be able to address a larger part of the global market. Chinese companies will become more aggressive in pursuing international mergers and acquisitions, to acquire global intellectual property and expertise to be transferred back home.

Figure 2 shows that ICs represent the single greatest import cost for China, so there is great incentive to develop competitive internal fab capacity. The government, recognizing the failure of earlier centrally-planned investment initiatives, now takes a market-based investment approach. The target is a compound annual growth rate (CAGR) for the industry of 20%, with potential financial support from the government of up to 1 trillion renminbi ($170 billion) over the next five to ten years. To avoid the fragmentation issues of the past, the government will focus on creating national champions—a small set of leaders in each critical segment of the semiconductor market (including design, manufacturing, tools, and assembly and test) and a few provinces in which there is the potential to develop industry clusters.

Figure 2: The leading imports to China in 2014, showing that integrated circuits (IC) cost the country more than oil. (Source: China’s customs)

Global Cooperation and Competition

The remaining leading IC manufacturers in the world—Intel, Samsung, and TSMC—are all involved in mainland Chinese fabs. Intel’s Fab68 in Dalian began production of logic chips in 2010. Samsung’s Fab in Xian began production of V-NAND chips in 2014. TSMC has announced it is seeking approval to build a wholly-owned 300mm foundry in Nanjing (http://www.wsj.com/articles/taiwan-semiconductor-plans-to-build-chip-plant-in-china-1449503714), after rival UMC’s has invested in a jointly-owned foundry now being built in Xiamen.

“We do see significant growth, and a big part of that is due to investment by the Chinese government,” said Handel Jones of IC Insights during SEMICON Europa 2015. “Up to US$20B of government subsidy has been earmarked for IC manufacturing investment in China.” Jones forecasts that by 2025 up to 30% of global design starts will be in China, many to be designed by the ~500 fabless companies in China today. Jones estimates the total R&D investment in China today for 5G wireless technology is about US$2B per year, with about one-half of that just by Huawei Technologies Co. Ltd.

Due to the inevitable atomic-limits of Moore’s Law scaling, it is likely that the industry will have reached the end of new nodes in the next 20 years. By then, “trailing-edge” will include everything that is in R&D today, from quantum-devices to CMOS-photonic chips, of which it is highly likely that China will have globally competitive design and manufacturing capability. While today a net importer of ICs, by the year 2035 it seems likely China will be a net exporter of ICs.

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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.

Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.

In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.

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