A computer system includes a memory for storing instructions executable by a processor and an on-chip trace memory having a plurality of locations for storing trace information that indicates execution flow in the processor. A trace access instruction provides for access to the on-chip trace memory ...

A processor provides trace synchronization information to ensure that address information for reconstructing instruction execution flow is provided in trace records with sufficient frequency. A trace record is provided for instructions that change the program flow such as conditional branches. Howev ...

A processor has both a serial debug port and a parallel debug port. The processor includes a processor core. The serial debug port is formed of a plurality of pins configured to send and receive signals to and from external software debug equipment. The parallel debug port is formed of a plurality o ...

A processor provides trace capability. Trace information can be provided over a communication port that is operable both as a trace port and as a parallel debug port. The trace port provides trace information indicating instruction execution flow in the processor core. The operation of the communica ...

An apparatus and method for integrating the delivery of data from a multiplicity of sources to a set of user electronic devices that present audio, video and digital information to the user is implemented. These devices may include conventional television displays, personal computers, and other conv ...

An archery target comprising a stack of carpet strips placed upon a base, with the side edges of the strips facing toward the archer. The strips are maintained under compressive force by a pair of flexible bands wrapped around front and rear portions of the stack and the base. The stack preferably i ...

An integrated circuit includes a performance monitoring circuit which includes an adaptive adder circuit coupled to receive a first input signal indicative of a performance parameter of the integrated circuit and to provide a count value as a measure of the probability of the performance parameter. ...

A host computer system is coupled to a target computer system for operating in a debug environment. The host computer system includes a status register which can be interrogated. A programming interface encoded in computer readable media and executable on the host computer system, provides at least ...

A system for handling multiple nested interrupts in a microprocessor device using C language interrupt handlers in which each interrupt handier is executed in two distinct stages, which are a Freeze mode handler and a signal handler, is disclosed. Upon the occurrence of each interrupt, a microproces ...

A processor-based device supports performance optimization with use of an adaptive digital element. The adaptive digital element generates probability data corresponding to a probability of a performance parameter of the processor-based device. The probability data is repeatedly compared to input da ...