We have posted a new Application Note for the AT91x40 Series on the ATMEL website. This application note provides directions to hardware designers when designing a board based on one of the AT91x40 microcontroller series and the AT91FR40x Flash-based products. The focus is on the verifications to be carried out at the board schematics level, thus assuring the highest probability of a right-first-time system.
For convenience, I attach it in this post.

Of course, the NWAIT pin is only to give more than the programmable Standard Wait States provided by the EBI. It is its only goal. After the NWAIT des-assertion, the EBI completes the remaining Standard Wait States. This is the rule.

Ok, I can use NWAIT together with the programmed wait states. But at wich point should the NWAIT signal be asserted?

During the first low period of MCKI after the NCS is asserted or on every low period of the MCKI. Of course allways with respect to the rising edge of MCKI (setup and hold times).

I have the following problem:

The AT91FR40162 should access a very slow device. The CPU must run at 75 MHz. The external device is a CPLD. The EBI is set up with 2 waitstates.
I want assert the NWAIT in the second low period of the MCKI.

This should result in the following timing: 1 waitstate from the EBI; several additional waitstates from the NWAIT and the remanig waitstate from the EBI.

If the NWAIT pin is sampled on every low period of MCKI (with active CS) it should be not a problem.

Hope you could give me additional hints on the behaivor of the NWAIT signal.

You have just to be scrupulous in abiding rising/falling edge time assertion (as you said), but you can assert the NWAIT pin when you want (at first, or second or... access time in term of cycle access) or I can say: It is not obligatory to assert NWAIT pin during the first access cycle. Is it your question/issue exactly ?