Aims

This module requires the full design, implementation, testing and
inter-operability of a complex hardware and software system.

Syllabus

This subject is lab-centric and project-based. The first class is the
only scheduled lecture. During the term, groups of two or three
students will work together to develop a fully functional IP
router. The groups will consist of at least one student familiar with
designing hardware in Verilog and one student who is comfortable
writing large, system-level network programs in C. Students will be
paired by area on the first day of class.

The hardware uses the NetFPGA boards which provide a programmable
hardware platform for developing network equipment. Given the Verilog
HDL code for a simple four port switch the hardware designer will
extend/modify/discard this code to provide the functionality of a
four-port IP router. A set of tools are provided to assist the student
with design, verification and synthesis.

Coursework

Practical work

Two supervised laboratory slots are scheduled per week; however,
additional laboratory work will be required to complete this
project. In addition to ad-hoc availability, each group will have
one-on-one time with the lecturer for a fixed slot each week to track
progress.

Additional time is provided both for small-group tutorials on
specialist skills, not present in all the incumbent students. Precise
material to be covered is heavily dictated by the students on the
course but material has included: perl, unix, make, advanced verilog,
digital design including metastability issues, software timer loops,
protocol implementation, Dikjstra's algorithm, along with using
debugging tools such as gdb and modelsim.

Deliverables are due at the end of each week; exact details of dates
and mechanism will be provided at the time of the module.