Programmable Logic has become more and more common as a core technology used to build electronic systems. By integrating soft-core or hardcore processors, these devices have become complete systems on a chip, steadily displacing general purpose processors and ASICs. In particular, high performance systems are now almost always implemented with FPGAs.
This course will give you the foundation for FPGA design in Embedded Systems along with practical design skills. You will learn what an FPGA is and how this technology was developed, how to select the best FPGA architecture for a given application, how to use state of the art software tools for FPGA development, and solve critical digital design problems using FPGAs. You use FPGA development tools to complete several example designs, including a custom processor. If you are thinking of a career in Electronics Design or an engineer looking at a career change, this is a great course to enhance your career opportunities.
Hardware Requirements:
You must have access to computer resources to run the development tools, a PC running either Windows 7, 8, or 10 or a recent Linux OS which must be RHEL 6.5 or CentOS Linux 6.5 or later. Either Linux OS could be run as a virtual machine under Windows 8 or 10. The tools do not run on Apple Mac computers. Whatever the OS, the computer must have at least 8 GB of RAM. Most new laptops will have this, or it may be possible to upgrade the memory.

GF

I really enjoyed this course. The instructor is by far the best I have encountered on any on-line (or classroom) course. I'm now waiting for the rest of the specialisation.

SD

Apr 24, 2019

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Simply awsesome, i was unaware of what actually is fpga designing or what days an fpga designer do, now I know the basics of it and am happy to learn, Thanks coursera

Na lição

FPGA Architectures: SRAM, FLASH, and Anti-fuse

FPGAs are programmable, and the program resides in a memory which determines how the logic and routing in the device is configured. In Module 3 you will learn the pros and cons of FLASH-based, SRAM-based, and Anti-Fuse based FPGAs. A survey of modern FPGA architectures will give you the tools to determine which type of FPGA is the best fit for a design. Architectures will be explored from the basic core logic cell up to consideration of large Intellectual Property (IP) blocks that are available on many FPGAs.

Ministrado por

Timothy Scherr

Senior Instructor and Professor of Engineering Practice

Transcrição

In this video, we will continue our survey of modern programmable logic devices where CPLDs and smaller FPGAs from Altera, including the MAX 5, the MAX 10, and the Cyclone 5. The goal in programmable logic device selection is to pick the best fit part for our requirements. We will use the programmable logic device selection criteria we established earlier to evaluate these devices as listed here. Here's a portion of the Altera Max V CPLD Family Device handbook. The Altera Max V has re-programmable flash configuration and user memory, although the routing switches are based on SRAM. On power-up the device transfers the configuration memory in flash to the S ram in about half a millisecond. Note that the logic available is up to 2,210 logic elements, more logic than the other CPLD's we have considered. Speed is limited to 304 megahertz on global clock buffers which is about par with other CPLD's. Maximum static power drives between 0.09 and 2 milliamps depending on the part size. So these are low power parts. Dynamic power's not specified. We use the power play analyzer tool to determine it. This device has up to 271 IO pins, an 8:1 ratio of logic cells to IO. There are nine supported I/O standards. Data retention's not specified. Programming cycles' endurance is somewhat minimal. There is deterministic timing, 7 nanoseconds pin-to-pin delay. Design security is enhanced by the integration of the configuration memory on a single chip. This is a picture of the Max V logic element. It looks more like an MPGA logic element than a CPLD. It's the heart of this LE. It's a four input and a flip-flop. This is because the Max V was designed as a crossover device between a CPLD and a MPGA. In reality, it's more like an MPGA than an CPLD. This next picture shows the overall layout of the MAX V device which is basically a sea of logic array block or labs connected by row and column routing. Each lab contains ten logic elements. Contrast the Max V floor plan with this floor plan for the Max10. It looks more sophisticated, which it is. And better yet, it's in color. The MAX 10 is a more recent part and consistent with the trend includes more hard IP blocks, like the PLLs and the ADC. This is a mixed signal part with both analog and digital functions on the chip. Here is a logic element diagram for the MAX 10. It's almost identical to the MAX 5 logic element with 4 input lop and a flip flop at the heart and some carry change and mock signal selection. Even though the max family has been a cpld family Altera finally dropped all pretense with the max ten and does call it an fpga. Here is a portion of the altera max 10 fpga family device handbook. The Altera Max 10 has reprogrammable flash configuration and user memory, although the routing switches are based on SRAM. On power up, the device transfers the configuration memory in flash to the SRAM in about half a millisecond. Note there are up to 50,000 logic elements, a good size for a small FPGA. Speed is limited to 450 megahertz on global. Very fast for a small FPGA. Power is not specified. Use the power play analyzer tool to determine it. Five watts is the limit for this part. This device is up to 500 IO pins, a ten to one ratio of logic cells to IO. There are 31 supported IO standards. Notice there are migration paths between pin compatible parts with different logic amounts. This is a very beneficial arrangement, especially when requirements change during a project, as no board layout is required even if the amount of logic used increases. A number of hard IP blocks have been added including block memory. Multipliers, PLLs, ADCs, and external memory interface. Data retention is 20 years with ten thousand programming cycles endurance which is good. Designed security is enhanced by the integration of the configuration memory on a single chip. Next, let's look at the product table for the Cyclone V Small FPGA. The Cyclone V has reprogrammable SRAM configuration and routing. So it needs an external nonvolatile configuration memory. On power up, the device transfers the configuration information to the internal SRAM. Notice there are up to 300,000 logic elements, a considerable amount for a small FPGA. Speed is limited to 550 megahertz on global clock buffers. Very good for a small FPGA. Power is not specified. Use the power play analyzer tool to determine it. This device has up to 480 I/O pins, a 600 to one ratio of logic cells to I/O. There are 34 supported I/O standards. A number of hard IP blocks have been added including block memory, multipliers, PLLs, DSP blocks, Hi-speed transceivers and external memory interfaces. This shows the layout of the overall Cyclone Five, with the logic cells, ram blocks, blocks, PLL's, transceiver and memory interfaces. The basic logic element for the Cyclone Five is the Adaptive Logic Module or ALM. It consists of an 8-input adaptive LUT, two Full Adders, and four foot-plot registers. This register-rich logic element allows more design-packing capability than previous generations. The LUT can also be configured as a 32 by 2 dual-port S-RAM. The ALM can become a three input adder by combining the full adders with let arithmetic. This is a picture of the ALM in the normal mode. This is the same ALM as previously shown. It's just another view of it as it operates in a particular mode. Recall the four bit comparator. How many comparator bits can be implemented in a in a max 10 case there are only 4 inputs so a two bit comparator can be created. Larger comparators require that the lots be cascaded, although the logic is efficiently used there is an added delay relative to the cpld implementation. In the Cyclone v case. The six independent input will handle three bits of comparator, so wider comparators can be made with less delay. How many full adders can be made in a logic cell? For the MAX 10 each log can create one full bit adder because of the addition of the so one LE equals one bit adder. However from a previous video, we used three Cyclone ALMs to implement a four bit adder, so each ALM creates about 1.33 adders. In this video we have learned, Altera offers the MAX V CPLD and MAX 10 and Cyclone V FPGA families for smaller logic designs. The MAX V and MAX 10 are single chip solutions with more I/O combined with reasonable logic density and efficient 4-input LUT logic cell. The MAX 10 adds analog signal processing via an on-chip ADC. The Cyclone V is a good entry level FPGA with good speed and logic density combined with a considerable amount of hard IP blocks. Including Block memory, PLLs, Multipliers and DSP blocks, High Speed Transceivers and External Memory Interfaces.