preston@tera.com (Preston Briggs) writes:
|> And that's the whole deal. With instruction caches, you can make the
|> hardwired instruction cycle as fast as microcode. There's no reason
|> to have a separate level of instruction interpretation.

True.

However you can build flash (or ordinary) ROM, much denser than SRAM.
In fact much denser than even DRAM theoretically since you don't need
the storage capacitor. I'm not sure of the exact SRAM:ROM area ratio,
maybe around 8:1?

Many cheap microcontrollers and DSPs have large chunks of ROM, with
some even having flash ROM on chip (e.g., the new TMS320F206&7 DSPs
will have 64KB of flash ROM on board).

Of course, it's difficult to make a case for say 32KB of L1 flash ROM
alongside the L1 instruction cache in a general purpose system. Are
any routines so important they're worth embedding at the L1 level?
Either to reduce total L1 miss penalties, or reduce worst-case
latencies?