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The VCS implementation of uvm_reg_bit_bash_seq UVM register bit bash sequence performs a
model.reset()
in the sequence body, before starting the core do_block() task.
Due to this reset, any configurations made to the DUT before starting the bit bash sequence is lost in the mirror model, while the DUT still has the configuration intact. This is causing failures during the bit-bash process, resulting in a test fail. There is no knob to override the reset functionality, nor can I extend the sequence and bypass the reset.
Any thoughts on this? Any work around for this?
~Chethan

Looking for suggestions on the best approach to modeling something akin the following.
value1 and value0 are implemented as value_reg[31:0] in RTL. The value actually stored in this register is always whatever you wrote to it. However, what you read back, and what HW sees when it looks at this register depends on the value of value_mode.
When value_mode == DIRECT, you'll read back the whatever value is physically stored in value_reg[15:0] as value0 and value_reg[31:16] as value1.
When value_mode == MULT, you'll read back a computed value instead. Let quotient == value_reg[15:0] * value_reg[31:16]. Then you'll read back quotient[15:0] as value0 and quotient[31:16] as value1.
Right now I've just added tasks write_value( bit [15:0] a, bit [15:0 b ), read_value( output bit [31:0] quotient ) to the register model, which look at value_mode before accessing value_reg. In both cases, write_value() just writes parameters a and b to value0 and value1 using the register model. When value_mode == DIRECT, read_value() reads value0 and value1 multiplies them and returns the result. When value_mode == MULT, read_value() reads value0 and value1, concats them and returns the result.
I'm contemplating adding some kind of virtual register to the register model instead of the tasks. Then, implement the logic using either callbacks or a custom front door. It also needs to preserve support for multiple address maps.
The goal is to prevent multiple scoreboards and coverage classes which are referencing these registers from having to implement the same computation. The idea of a virtual register is to provide the same uvm_reg API to the user as other registers. A side benefit is the user only makes a single call to read the 32 bit value, rather than making two calls.
Cheers.

Hello,
We have a test bench environment where we have 2 objects of the same SPI env class.
The SPI env sets the sequencer for the RAL model as follows:
reg_model.default_map.set_sequencer(spi_master_agt.mem_sqr, reg2spi_adapter);
The transaction type handled by the spi_master_agt.mem_sqr is spi_mem_tr.
Now I need to extend the spi_mem_tr to spi_mem_tr_1 and spi_mem_tr_2, and then override spi_mem_tr with those separately for the 2 objects of the SPI env class.
// Below does not work
set_inst_override_by_type
( .relative_inst_path("env.spi_m[0].*"), // Here spi_m[0] is the first instance of the SPI env
.original_type(spi_mem_tr::get_type()),
.override_type(spi_mem_tr_1::get_type()));
set_inst_override_by_type
( .relative_inst_path("env.spi_m[1].*"), // Here spi_m[1] is the second instance of the SPI env
.original_type(spi_mem_tr::get_type()),
.override_type(spi_mem_tr_2::get_type()));
// This does not work too!
set_inst_override_by_type
( .relative_inst_path("env.*"),
.original_type(spi_mem_tr::get_type()),
.override_type(spi_mem_tr_1::get_type()));
// Even this does not work!
// So looks like "inst" override by type does not work for tr objects in RAL
// connecting agents?
set_inst_override_by_type
( .relative_inst_path("*"),
.original_type(spi_mem_tr::get_type()),
.override_type(spi_mem_tr_1::get_type()));
// Other the other hand, below works, BUT that overrides the tr in both SPI env objects
// That is not what I want; I need to override using different types for the
// two SPI env objects
spi_mem_tr::type_id::set_type_override(spi_mem_tr_1::get_type());
Questions:
Is it possible to do instance specific overrides over transaction class inside the SPI agent connecting to my RAL model?
If so, what is the correct way to set the relative_inst_path?
If not, are there any hacks to achieve the same?
The fact that the global type override does work gives me some hope.

Hi,
We are using snps ralgen to generate the regmodel.
It appears that the ralgen creates only the default map.
We would like to have 2 maps for 2 separated if masters. Is there an online example for such case?
A post gen script can do one of the following 2 options:
1. add another instance of uvm_reg_map and copy/clone the ready map after finished build
2. add another instance of uvm_reg_map, and duplicate any map1.add_reg and map1.add_submap to map2
Which is preferable?
Thanks!
Elihai

Hi,
I have a question refer to strange messages created by RAL read command.
When the register is read, I receive a message like:
uvm_pkg::uvm_parent_child_link l103=config_dmaw_seq r107=transfer
Do you know how to prevent these messages?
Regards,
Moshe

Hello all,
Sorry for stupid question.
I have my registers defined as, reg1, reg2, reg3.....................reg64.
Now i want to drive a single value (ZERO) to all register using for loop.
so i implemented,
for (integer i = 0; i<65; i = i+1);
des_data[0:7] = 8'h00;
block_obj.$sformatf("reg%0d",i).write(status, des_data, UVM_FRONTDOOR,.parent(this));
But i am unable to achieve so.
Any one else can suggest alternate solution or logic for the above problem ??

Hi,
I wanted to use the field.mirror() task provided in the uvm_reg_field class to check only a particular field. However, I see that the field.mirror() task is just calling the parent register mirror task. Hence the entire register is read and compared which I didn't intend to do. I tried this in my sequence and I see the above mentioned behavior. This looks like a serious bug. Can you please confirm this.
Regards,
Shreyas

Hello All,
I have some queries regarding RAL model :
(1.) How to declare any particular Register's filed as "signed" in RAL model?
(2.) By default all the register fields in RAL model are "unsigned" or "signed"?
If possible please guide me for the same.
Thanks,
Bonny G. Vora

Not sure do you have similar problem? I have a problem in handling the reset value in RAL.
f the reset value of a field in the register is don't care, what can I do for it?
Now my plan is extend a new access type. For this kind of registers, the read value in reset test is not checked.
Do you guys think it is a feasible way? Thanks.