There was never an intent to require that the Base Address registers had to
be implemented in a specific order. The wording in 2.1 implied it, but the
wording was meant to tell software to begin looking at offset 0x10 and then
continue from there (ie, you can't start looking from 0x24, otherwise you
might get confused by 64-bit BARs). This was clarified in the 2.2 spec.
The PCI Compliance tests that have been available since shortly after 2.1
was released have always made sure that system BIOSes could handle BARs
implemented in any order. And it's been years since we've seen a BIOS that
had a problem with BARs not beginning at 0x10.
Granted, these tests are geared to the volume market, but they have been
ported to some other architectures (Alpha for instance) by individual
vendors.
Brad Hosler
PCI SIG Technical Support
-----Original Message-----
From: Lame Brooks-G14738 [mailto:Brooks_Lame@mcg.mot.com]
Sent: Thursday, September 16, 1999 3:37 PM
To: Mailing List Recipients
Subject: Why was this changed in 2.2? RE: What if BASE0 is not
implemented ?
I agree. The only reason I can think of for this change between 2.1 and 2.2
is to allow some devices that were not 2.1 compliant, to be compliant under
2.2. This is _not_ a good reason. If I were writing BIOS or other config
software, the 2.1 requirement is cleaner and allows config algorithms to be
faster since they can stop upon finding an unimplemented BAR. So, the
question remains, why was it changed? And, do all the BIOS writers realize
that it was changed? -- BrooksL
> > > I was under the impression that BARs should be impemented
> in consecutive
> > > order from 0, but don't recall the reference for that.
> > > -- BrooksL
> >
>
> I had the same impression (that BARs needed to be implemented
> in order), but
> I looked in the 2.2 spec quickly this morning and couldn't find it.
>
> However, just so that other people don't think that they're
> going crazy
> either, I did just go back and find these:
>
> PCI 2.1, section 6.2.5.1., page 197, paragraph 4, sentence 2:
> "The first Base Address register is always located at offset 10h. The
> second register may be at offset 14h or 18h depending on the size of
> the first. The offsets of subsequent Base Address registers are
> determined by the size of previous Base Addresss registers."
>
> and PCI 2.2, section 6.1.5.1., page 204, paragraph 1, sentence 2:
> "A device may use any of the locations to implement Base Address
> registers. An implemented 64-bit Base Address register consumes two
> consectutive DWORD locations. Software looking for implemented Base
> Address registers must start at offset 10h and continue upwards
> through offset 24h."
>
> It would be nice if someone who was involved in this change from 2.1
> to 2.2 would explain why things have changed. It seems to me that
> the net result of this change is to possably invalidate alot of
> existing 2.1 configuration software for no real gain at all. *sigh*
>
> -Richard
>