Many believe that the race for GHz ended with the Pentium 4 architecture, but you wouldn’t be able to tell by looking at the speed of these two upcoming IBM processors. According to the agenda of the International Solid State Circuits conference, IBM’s Power6 Processor will operate at speeds of over 5GHz in high-performance applications. The second-generation of the Cell Broadband Engine processor, which was co-developed by IBM, Sony and Toshiba, will run at 6GHz. More details of Intel's "teraflop-on-a-chip" network processor will also be revealed.

The ISSCC2007 advanced program (PDF) claims IBM Power6 server processors are expected to begin shipping in 2007. Although it has been widely believed that the processors will run at a clock frequency between 4GHz and 5GHz, information provided by IBM for the ISSCC agenda states otherwise. The processor will run at over 5GHz in “high-performance applications” while also running at under 100 watts in “power sensitive applications.”’

IBM states that the Power6 offers “ultra-high frequency operation, aggressive power reduction, a highly scalable memory subsystem, and mainframe-like reliability, availability, and serviceability.” The dual-core 341 square millimeter processor features 700 million transistors. It is constructed using a 65-nanometer manufacturing process.

The ISSCC program also revealed technical details of the second generation IBM, Sony and Toshiba Cell Broadband Engine. The first generation of the chip, which is currently used in the Sony PlayStation 3, runs at frequencies up to 3.2GHz. The second generation chip, on the other hand, will receive a frequency boost of nearly 3GHz and have an operating frequency of 6GHz at 1.3V. In addition, it will be constructed using 65nm CMOS SOI technology and will feature a dual power supply helping increase memory performance.

Despite IBM’s evident advancements in clock speed, Intel will still be holding firm to its multi-core approach to performance. According to the program schedule for ISSCC, Intel will reveal more details regarding its 80-core Tera-scale processor which can run 1.28 trillion floating-point operations per second.

Described as a “network-on-chip architecture,” the 225 square millimeter chip has 80 cores, each operating at 4GHz. The die is built using a 65nm process and is able to “achieve a peak performance of 1.0TFLOPS at 1V while dissipating 98W.” Currently, the processor is not able to run conventional applications for Intel chips.

Even though the chip is currently little more than a prototype, Intel CEO Paul Otellini claims it will be available within five years. The processor was first announced last September at the Intel Developer Forum.

The International Solid-State Circuits Conference will be taking place February 11-15 at the San Francisco Marriott Hotel. Other notable appearances will be given by Sun Microsystems, who will be discussing its Niagara2 processors, and AMD, who will be talking about its quad-core Barcelona processors expected to ship mid-2007.

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