Synchronized communication systems are operated based on a group of common system clocks. In most telecom applications, the main system clock is distributed to system boards via the backplane or cables.

Additional considerations for the clock signal are related to operational concerns. Telecom equipment often requires repair and replacement while actively powered. Devices connected to the backplane must be able to operate during hot swap operation. This implies protection from damage during hot-swap, while also avoiding impact to other signals that are running on the backplane.

These considerations result in a secondary set of requirements including: ESD protection, glitch-free driver operation, receiver fail-safe and high-impedance driver operation

Current approaches

There are several approaches to distribute clock signals over the backplane. Possible topologies include point-to-point, multidrop, and multipoint. For each topology single-ended or differential signal levels can be used. Each solution has its benefits and shortcomings.

In a point-to-point topology, shown in Figure 1-a, two master clock boards send out signals to other slave boards through different signal paths. Each slave board receives two clock signals: one from the primary clock module and another from the secondary clock module. The major advantage of point-to-point distribution is signal quality. Having a single transmitter coupled to a single receiver provides the lowest jitter clock signal. The disadvantage of this approach is the abundance of signal paths. This increases the PCB layout complexity and manufacturing cost.

With a multidrop topology, shown in Figure 1-b, the redundant, point-to-point signal paths are replaced by two multidrop signal buses. Each bus consists of a single master located on a clock module, with receivers located on each system card. The advantage of the multidrop topology is simplification of the backplane layout, which can provide greater area for signal isolation while also reducing unnecessary PCB layers. If a one-way signal distribution is necessary in a system, the multidrop topology could save system cost with its simplified PCB layout.

A multidrop system does, however, suffer from some shortcomings. In most telecom equipment, the installation of slave boards per shelf is not fixed. Boards may be present in one application, while absent in a second configuration. The loaded impedance of a signal path varies with the number of installed boards. This variability results in the need to compromise on a bus termination resistance. Additional concerns arise when "hot-swapping." When a board is plugged into a system it changes the loaded impedance. This transient condition can affect the signal quality seen throughout the system.

Figure 1-c shows a multipoint topology, which appears similar to the multidrop approach. The key difference is that multipoint supports bi-directional, or multiple driver communication. A multipoint bus allows any driver to send clock signals to the other receivers. Clock distribution can be simplified using multipoint, as the primary and secondary clock drivers can share the same bus lines, with the active source being determined based upon some system considerations. Additional possibilities exist with a multipoint system such as dynamic configuration of the clock source as well. As seen in Figure 1-c, a multipoint design provides the easiest PCB layout as well.

Compared to single-ended signals, differential signals provide the obvious advantage of common-mode noise cancellation. Smaller voltage swings provide two more additional advantages compared to single-ended signals: lower EMI and lower power consumption. The primary drawback of differential signaling is the need for twice as many conductors as required by single-ended solutions.

Differential signaling devices in common use include LVPECL, LVDS and CML. LVPECL is an evolution from negative ECL logic. LVPECL uses a 3.3V supply voltage, with termination through 50-ohm pull-down resistors to Vtt (Vcc-2.0 V) on both outputs. In general, LVPECL provides an output differential voltage of ~800 mV

LVDS is specified to provide a minimum 250mV output differential voltage across a 100-ohm termination. The easy-to-use termination of LVDS has resulted in more and more point-to-point topologies relying on it for noise sensitive application.

CML is a third differential signaling approach. CML drivers are simple to implement, provide high-speed operation, and require a simple 50-ohm pull-up termination to Vcc at the receiving end of the bus.

M-LVDS is a new differential signaling technology that has been specifically designed for the multipoint backplane environment. M-LVDS drivers provide at least 480mV differential signal across a 50-ohm termination. Figure 3 shows the main logic levels for 3.3V low voltage differential signal levels.

Figure 3: Low voltage differential signal levels reflect a 1-V swing.

M-LVDS features for clock distribution

The TIA/EIA-899 standard, M-LVDS (Multipoint Low Voltage Differential Signaling), is the first industrial standard that specifies a low voltage differential signal level for the true multipoint application. The driver is specified to drive up to a total of 32 loads while incorporating slew rate control to limit the transition times to 1ns or longer. This minimum 1-ns slew rate allows for longer stub lengths, which is always a concern in backplane designs.

Two classes of receiver are included in the standard: Type-1 and Type-2. Type-1 receivers have input differential threshold voltages set at 50mV and "50mV; Type-2 receiver thresholds are set at 150mV and 50mV. The input differential voltage (VID) is defined as the positive input voltage (VI+) minus the negative input voltage (VI-), i.e. VID = VI+ - VI-. The M-LVDS type-2 receiver allows fail-safe operation under conditions where (a) all drivers are in the OFF condition; where (b) a receiver is disconnected from the interconnecting media; where (c) the interconnecting media is open/short-circuited; and (d) where more than one driver is active.

The maximum signaling rate of M-LVDS is specified at 500Mbits/s. This signaling rate allows for clock signal transmission for most common synchronous system clock frequencies, which are typically less than 200MHz. Currently available devices provide 8kV HBM ESD protection and driver glitch-free operation. The M-LVDS standard provides features that ably meet the requirements needed to distribute clock signals over a backplane.

The PCI Industrial Computer Manufacturers Groups (PICMG)
Advanced Telecom Computing Architecture (AdvancedTCATM) specification "AdvancedTCATM PICMG3.0 " identifies M-LVDS as the signaling level to be used for clock distribution up to 100MHz. Currently available M-LVDS devices support a cost-saving multipoint topology backplane with better noise-immune differential signaling.

PICMG3.0 includes a synchronous system clock interface with 6 pairs of differential clock buses. These buses support 3 different clock frequencies as well as redundancy. The PICMG3.0 specification allows for dynamic distribution of the clock signals, resulting in the need for true multipoint operation. AdvancedTCATM-compliant equipment is now being introduced to the market to support the development of next-generation network infrastructure equipment.

Sample Application

Third generation basestations represent a good example of the value of M-LVDS as a clock distribution solution. Modern basestations include numerous high-speed (> 1Gbps) point-to-point serial data links. Basestation modules are interconnected with a common control bus that could be implemented using M-LVDS. All modules are synchronized via redundant clock modules that distribute system timing. A W-CDMA system, for example, provides a 30.72MHz clock signal to all modules. This clock signal can be transmitted by M-LVDS drivers and receivers. Redundant clock modules can share the same backplane clock bus, simplifying backplane design. Clock module repair/replacement is supported with M-LVDS due to its hot-swap features. M-LVDS driver strength provides clock distribution for up to 32 M-LVDS receiver loads. Type-2 receivers can be incorporated into each module to provide fail-safe protection

M-LVDS drivers and repeaters can also be used to distribute system clocks between shelves in a basestation using CAT5 or similar cables. Using M-LVDS drivers and receivers in a singly terminated architecture provides greater than 800mV of noise margin, while still keeping system power at lower levels than an ECL-class solutions.

Figure 4 shows how clock distribution in a basestation could be implemented using M-LVDS. SN65MLVD206 devices could be used for all drivers and receivers. The redundant clock modules are installed in a shelf separated from the channel cards. 30.72MHz clock signals are sent via CAT5 cable and M-LVDS drivers to baseband control modules. The control modules receive and re-transmit the clock signals via a multipoint architecture within a shelf. M-LVDS Type-2 transceivers have been selected as receivers to provide fail-safe operation on the baseband control module. A 100-ohm termination is required at the receiver side.

Figure 4: Basestation clock distribution using M-LVDs.

A differential multipoint configuration within a shelf is illustrated in the same figure. After receipt of the clock signal, the baseband control module may perform some processing (frequency scaling, jitter cleaning, etc), and then it re-transmits the subsystem clock signal to other modules in shelf 1. M-LVDS Type-2 transceivers (MR1~16) are chosen to allow fail-safe operation. Two termination resistors are located at the ends of the differential bus on the backplane. The resistor termination value is determined by the loaded impedance of the bus.

Demonstration system results

A compact PCI compatible demonstration system has been designed and developed to study the performance of differential multipoint backplanes with M-LVDS transceivers. The demonstration system shown in Figure 5 includes 21 cards installed in one shelf. Two slots provide system power with the other 19 slots configured for general purposed interface modules. A 30.72MHz clock signal was provided to the M-LVDS driver on module 1. The system is fully loaded with M-LVDS interface modules. An oscilloscope was connected to the module 19, and waveform was measured from the receiver output. The measurement shows that the duty cycle of the 30.72MHz clock signal was very close to 50% duty cycle of the input clock source. The random jitter after transmission through the backplane is negligible. A minor reflection noise was seen, VOLP ~100mV, at the LVTTL output, which can be improved with better impedance matching on the line. The demonstration system shows the quality of clock signal that can be distributed in a heavily loaded differential multipoint backplane.

Figure 5: Demonstration system results from a dynamic clock distribution.

Telecommunication equipment designs are increasing in complexity as well as density. The overwhelming trend is toward a serialized backplane for distribution of high-speed payloads. In parallel with these serialized data streams are control and clock distribution subsystems. Both control and clock designs can be simplified using M-LVDS technology. True multipoint operation, low power, and hundreds of Mbps signaling provide improved solutions for new equipment design. Multipoint-LVDS allows low voltage signaling to be incorporated in a shared-media environment. Shared-media, bussed designs simplify backplane design and can reduce costs in the backplane as well as system cards. M-LVDS devices are currently available supporting bussed operation at 200Mbps, allowing clock distribution for most common infrastructure equipment.