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Description

General Description:How do I instantiate special Virtex-E I/O standards (LVDS, LVPECL)?

Solution

1

FPGA Express version 3.3.1 and older contain all the special Virtex I/O Standard buffers.These buffers can be instantiated for any port, and FPGA Express will recognize that they are input or output buffers.

However, FPGA Express 3.3.1 an older do not contain the new Virtex-E I/O buffers, so special techniques must be used when synthesizing.

If all or most of the ports in your design use special Virtex/E I/O standards, one option is to instantiate all of the I/O buffers. Because all the I/O buffers will already exist in the HDL code, you must not allow FPGA Express to insert I/O buffers. Deselect the "Insert I/O Pads" checkbox in Foundation, or select the "Do Not Insert I/O Pads" box in FPGA Express.

In these cases, you must do three things:

1. Instantiate all the Virtex, Virtex-E and standard I/O buffers, but NO pads.2. Include all I/O ports in the top-level port declaration.3. Do NOT allow FPGA Express to insert pads.

2

If only a few of the ports in your design use the special Virtex-E I/O Standards, you may allow FPGA Express to insert pads for all the ports EXCEPT the ones using the Virtex-E standards.Because FPGA Express does not know about these buffers, it will place an extra IBUF or OBUFon these ports, which will lead to errors during implementation.

In these cases, you must do three things:

1. Instantiate the Virtex-E buffers AND their pads.2. Do NOT include these ports in the top-level port declaration.3. Allow FPGA Express to insert pads for all other ports, including any Virtex- (non-E)instantiated buffers. Check the "Insert I/O Pads" box (Foundation) or uncheck the "Do Not Insert I/O Pads" box (FPGA Express).

Here are the code examples from Resolution 1 with extra logic. Ports clk, rst and ce will use the default LVTTL standard, and ports din, dout_p and dout_n use the LVDS standard.