EATONTOWN, N.J.—(BUSINESS WIRE)—March 10, 2009—
CebaTech Inc., an innovative intellectual property (IP) provider, has
announced that it is taking its IP business to the next level with a
library of rapidly tunable IP cores, CebaRIP cores, targeted at
system-on-chip (SoC), ASIC and FPGA designs. CebaRIP cores can be
optimized to meet specific application requirements significantly faster
and more cost-effectively than is possible with established IP
development flows. The initial offering is targeted at the IP
realization of standard algorithms used extensively in storage, storage
area network (SAN), network-attached storage (NAS), and networking
applications, including compression, encryption, fingerprinting, and
more. In addition to these standard CebaRIP cores, CebaTech also
implements customers’ proprietary algorithms as rapidly tunable cores.

CebaRIP tunable cores meet an important need in the deployment of
silicon IP – the need to tune a given IP design for reuse in multiple
application scenarios, each with different performance, power, area and
cost requirements.

“After licensing CebaTech’s tunable GZIP compression IP core, we
determined the need for three new features which required significant
design changes. CebaTech executed the changes and delivered the new,
verified RTL in four to five days,” commented Jiebing Wang, VP of
Engineering for Hifn (NASDAQ:HIFN), a provider of storage and network
security products. “CebaTech’s rapidly tunable IP approach delivered a
core that exactly met our requirements – and in a market-beating cycle
time.”

The CebaRIP cores leverage both CebaTech’s in-depth storage/network
application domain expertise and a high-level synthesis (HLS) design
flow based on its in-house C2R Compiler™ solution. Using its HLS
technology, CebaTech quickly analyzes candidate IP architectures,
achieving the requisite trade-offs much faster than traditional manual
approaches. The technology then generates the IP’s RTL implementation
automatically. The CebaRIP core approach not only eliminates the time
and effort required by manual RTL development, but also enables the fast
implementation of engineering change orders (ECOs) at any stage in the
design.

“Using traditional IP design methods, the need to re-purpose IP for
different applications significantly slows time to market and
simultaneously increases development costs,” commented Ramana Jampala,
CEO, CebaTech. “Late-stage ECOs can be especially disruptive to the time
and cost budget. The standard “fixed” IP library approach cannot solve
these problems, but rapidly tunable IP can – and does. Our customers
regard CebaRIP cores as a strategic differentiator.”

Taking performance to the limit

To achieve greater on-chip performance, multiple disparate CebaRIP cores
can be configured in a plug-and-play ensemble. To boost in-system
performance by an order of magnitude or more, CebaTech develops and
provides turnkey board-level, CebaRIP-enabled plug-and-play coprocessor
subsystems that offload the central processing unit (CPU). The turnkey
service includes ASIC and FPGA design, hardware/software system
integration and test, and conformance certifications.

“Our HLS technology enables us to modify algorithms, analyze candidate
architectures and generate RTL very quickly. Using traditional IP
development approaches, the Hifn modifications would have taken a month,
or more,” commented Chad Spackman, CebaTech’s CTO. “The customer used to
have a choice between fast access to often non-optimal IP, or a long
time to market for customized IP that exactly meets requirements. Now
the customer has fast access to optimal, customized IP – the best of
both worlds.”

Availability

All four CebaRIP cores are available immediately.

About CebaTech

CebaTech Inc. develops rapidly tunable silicon intellectual property
(IP) cores to accelerate the realization of complex software algorithms
in silicon, boosting the productivity of engineering teams focused on
advanced SoC, ASIC and FPGA systems design. CebaTech’s IP offering
includes cores for network, storage, storage area network (SAN),
network-attached storage (NAS), communication applications, as well as
turnkey coprocessor subsystem design. CebaTech’s IP is supported by IP
development services, and leverages in-house high level synthesis
technology that speeds time to market, eliminates development
bottlenecks, and reduces development costs. For further information,
please contact Cebatech by email at
Email Contact
or telephone at 732-440-1280, ext. 200.