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The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

Techniques & Tools

The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference.
After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

Analog/Mixed Signal

The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

Coverage Forum

Additional Forums

The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

Mentor Learning Center

The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

Replies

I believe your question is quite useless, because you can make a big list of things to added to the UVM but nobody does need them. Improvements should be always considered with respect to to certain functionalities or applications.
Please specify your question.

This is a great question. It's also a good one for the SystemVerilog standard. The best improvement for both of them is making them even more stable by fixing all their bugs. The big problem with design by committee is that you can always get new energy from people to add in new features, but it's much more difficult to get the same kind of energy to fix bugs.

And then there's the issue of how one defines a bug. That's easy when a feature is completely unusable (see recent discussions of uvm_reg_fifo, but crosses the line into an enhancement when its missing a key feature to make it completely usable. (see discussions on umm_reg_map

Since the UVM is now just an IEEE document like the SystemVerilog standard, not actual code, my personal opinion is working on improving the standard to make sure it captures the intent of all features correctly the way people want it implemented.

So, Killing a sequence mid-flight jammed my sequencer and it took me a better part of the day to understand what was happening. UVM gave me no error/warning to help me traige the issue. I think these can be made better.

It does of course. All I am saying is an Error message would have made traige easy.
Consider a typical SOC when there are 100s of other threads going. Somebody locking the sequencer kills the test for everybody else. For that bloke's block it might have worked since he ends his test after this, but when ported over, it would be a debug nightmare and partly because UVM does not point it out.

Yes, there is still an Accellera committee that maintains the reference implementation. But since they are made up of the same people, usually one of them is dormant while the other is active. Ideally the code and the documentation should be in sync, but that's not always the case.