Abstract:
Aggressive MOS scaling has led to the need to characterize 1/f or
flicker noise at higher frequencies for circuit design or process
development. Measurement challenges include identifying the corner
frequency amid extrinsic background noise, detecting higher corner
frequencies and dealing with systems that are difficult to setup and
control. Limitations of existing on-wafer flicker measurement systems
include limited bandwidth and a high noise floor that is further
complicated by the need to measure across a broad thermal range.
Generally these systems are difficult to configure to gain optimal
performance and must be dedicated to 1/f use. Cascade Microtech has
addressed these issues by providing an integrated optimized system -
wafer prober, thermal system, test electronics, software,
instrumentation and support - all inclusive. Bandwidth is extended to
30 MHz at practical R load values by reducing signal path capacitance
and keeping the paths short. Advanced SMU filters have been applied
which provide an extremely low noise floor for measurement all the way
to 30 MHz. There two switchable operating modes – 1/f mode and DC
parametric for standard tests.

Abstract:
Accelicon Technologies, Inc. based in Cupertino California, is a
technology leader in device-level modeling and validation, as well as
PDK-level validation. Profitable, in it’s sixth year, and with over 60
customers worldwide, Accelicon has established itself as a market
leader as well. Accelicon’s products are: MBP for device-level
extraction and model generation, MQA for device-level model validation,
and PQA for PDK validation. MBP is the next-generation device-level
model extraction and generation solution, incorporating superior
optimization and simulation for ‘order of magnitude’ performance
improvement. Innovative patented features, such as task tree ordering
and equation viewer, enable unparalleled ease of use. MQA is a
rules-driven device-level model validation solution used by foundries
for model QA and semiconductor design houses for model qualification.
MQA is also used for model and simulator comparison as well as a
documentation standard. PQA automates the SPICE analysis of DFM
parasitics on the layout. Second-order layout-dependent effects,
characteristic in finer geometry processes, are significantly
complicating PDK validation, thus requiring automated validation
techniques.

Abstract:
In this poster we present highly accurate High Voltage LDMOS-transistor
models for analog applications. Special sub-circuits are demonstrated
in order to model symmetrical and unsymmetrical N- and P-LDMOS
transistors with emphasis on modeling of on resistor (RON), quasi
saturation effects, body currents and parasitic diode/bipolar effects
in addition to the standard MOS effects. The high flexibility of the
sub-circuits allows individual configurations for all kind of LDMOS
transistors. The paper shows different implementations of the parasitic
behavior with diodes or BJTs for length and width scalable isolated and
non isolated n- and p- channel HV transistors.

Abstract:
The work carried out by our group has led to the development of compact
small-signal models for different types of Multiple-Gate MOSFETs
(MuGFETs), such as Gate All Around (GAA) and symmetrical and
asymmetrical Double Gate (DG) MOSFETs and FinFETs. These models have
been extended to the high frequency and noise analysis. The
small-signal models have been extended to high-frequency and noise
analysis using the active transmission line approach. The intrinsic
device is split into several sections along the channel length. A local
intrinsic small-signal model is used in each section, in which the
analytical expressions of the quasi-static parameters are used. The
diffusion noise and gate tunneling noise sources are included in the
local small-signal model.

Abstract:
Electrical device parameters such as leakage current and threshold
voltage of FinFETs are dominated by the height of the potential barrier
which the carriers have to surmount to enter the drift region of the
channel. In this poster we present an analytical, structure-oriented
model for the potential barrier in undoped FinFETs, which inherently
includes short-channel effects. For that, we solve the 3D Laplace
equation in a cross-section of the channel which is located at the
position of the potential barrier. By a specially developed analytical
technique we reduce the problem to a 2D Laplace equation still
including the third dimension. This equation can be solved in
closed-form under use of the conformal mapping technique. We derived
closed-form models for subthreshold slope and threshold voltage. The
models showing slope degradation and increase of DIBL effect by channel
length reduction are in good agreement with numerical results down to a
channel length of 20nm.

Abstract:
An explicit compact model for both
undoped FinFET and symmetric double-gate MOSFET is presented. The core
of the model relies on a robust algorithm for computing the mobile
charge density as an explicit function of the terminal voltages, making
the model suitable for circuit design and simulation. It is made of
simple relationships that are really helpful for the circuit designer.
The model v1.1 takes into account short-channel effects such as
threshold voltage roll-off, DIBL, subthreshold slope degradation and
mobility degradation. It is accurate for channel length down to 60 nm
and silicon thickness (Fin or body) between 10 and 25 nm. A beta
version (forthcoming v1.2) is now accounting for quantum-mechanical
effects and allows simulating devices with a Fin thinner than 3 nm. Our
modeling approach results in a physics-based formulation in all regions
of operation and is valid for both static and dynamic modes of
operation. Model validation is carried out by comparison with 2D and 3D
numerical simulations for DG MOSFET and FinFET, respectively.

Abstract:
CMOS technology development is one
of the main activities of the Division of Silicon Microsystem and
Nanostructure Technology and of the Department of Integrated Circuits
and Systems in the ITE. The technology is offered to the academies
within a multi-project-wafer service. For this purpose a design kit for
the CADENCE design system has been developed. Many efforts have been
also undertaken to integrate the CMOS process with techniques for
fabrication of ionizing radiation detectors, ISFETs and MEMS.
Implementation of the FD SOI CMOS technology developed in the UCL is
now a key issue. For the development of the processes and devices
simulation tools (e.g. ISE-TCAD, COVENTOR, SEMulator3D,
Matlab/Simulink) are used. They are perspective for the investigation
of the dispersion of multi-gate MOSFETs electrical characteristics.
Characterization is done using a Keithley system and a set of parameter
extraction tools. The collaboration between ITE and WUT enables
detailed investigation of the Si/SiO2 interface based on a unique setup
for charge-pumping measurements.

Abstract:
We present a precise two-dimensional current and capacitance model for
nanoscale double-gate and gate-all-around MOSFETs covering a wide range
of operating conditions, geometries and material combinations. The
modeling in the sub-threshold regime is based on conformal mapping
techniques. In moderate to strong inversion, we obtain self-consistent
results based on the 2D Poisson’s equation. The results are in
excellent agreement with numerical simulations.

Abstract:
This work describes a method that
enables fully automated parameter extraction of model parameters. It
has been applied to a well known model, whose first proposed parameter
extraction procedure required human assistance. The extraction method
basically consists of a queen bee genetic algorithm. The difference in
this method is that the mutations that originate the new generations,
even though they are random, are bound to follow certain directives
regarding sign and typical deviation. As a result, the new populations
are generated in such a way that the controlled parameters are going to
approach their correct value although the total adjustment of the
operation is worse, thus avoiding falling in local minima and
drastically improving the convergence time. In order to test the
method, we generated 1000 sets of OTFT characteristic curves, each one
from a random set of parameters. The parameter extraction process
provided errors of less than 1% in the worst adjusted parameter when
comparing with the set of parameters used to generate the curve,
without the need for intervention by a human operator.

Abstract:
A new compact analytical model recently developed for symmetric
double-gate MOSFETs that accounts for doped silicon layer, variable
mobility and short-channel effects, is used for modeling of FinFETs
behavior at different temperatures up to 200°C. FinFETs with the
following features are analyzed: highK-metal gate stack; channel doping
of about1015 cm-3; fin width of 25 nm; fin height of 65 nm and channel
lengths of 10 mm and 80 nm [3]. The transfer characteristics at 20 mV
and 1 V are measured and modeled at different temperatures: 20°C; 75°C;
100°C; 150°C and 200°C. Excellent coincidence between the measured and
the calculated characteristics are obtained including the subthreshold
swing variation with temperature demonstrating the accuracy of the
model.

Abstract:
The extraction of the series extrinsic resistances is a critical issue
for the RF modeling of the MOS transistors. The classical DC methods
allow to determine the total series drain-source resistance (Rs + Rd),
whereas proper RF modeling requires the knowledge of the series
resistances Rs and Rd separately, as well as the gate resistance, Rg.
Well-known RF characterization techniques have been proposed in the
literature to extract properly these three parasitic resistances.
However, those RF characterization techniques present some limitations
to accurately extract these series resistances, and thus the intrinsic
parameters of the measured transistor. The main RF techniques are the
Lovelace, Torres-Torres, Raskin and Bracle´s methods. In this paper, we
introduce some of these issues. The main concern is the noise related
to the scattering parameters (S-parameters) measurements. Lovelace and
Torres-Torres´ techniques are quite sensitive to the noise, making
difficult to determine adequately the resistances, even if some
pre-treatments are applied on measured S-parameters. Raskin´s method is
also sensitive to the measurement noise but the use of smoothing
techniques improves the extraction results. Additionally, the Raskin´s
method requires the analysis of impedance parameters over a wide
frequency band. For deep-submicron devices, the excursion of the
impedance parameters plots needed to determine the series resistances
is significantly reduced, then loosing accuracy on the extracted
values. On the other hand, the Bracale´s method is much less sensitive
to measurement noise. Furthermore, the extraction can be performed
based on a single frequency point. However, that technique does not
consider the effect of the mobility degradation due to the transversal
electric field and the asymmetry related to the transistor. The
mobility degradation produces the overestimation of the source and
drain resistances and the underestimation of the gate resistance, while
the asymmetry has a big impact on the accuracy of the source and drain
resistances. The weaknesses and advantages of each RF extraction method
will be presented in details and based on these analyses and
conclusions a new RF extraction method will be proposed.
iation with temperature demonstrating the accuracy of the
model.