Intel® Stratix® 10 and Intel Arria® 10 FPGAs and SoCs provide high performance of memory interfaces on 14 nm and 20 nm nodes respectively with hardened memory controllers. These hard memory controllers offer several advantages over soft memory controller options, and some of the benefits include:

Enables shorter engineering cycles and faster time to market because timing is pre-closed in the hardened logic

Saves user logic resources

Achieves higher performance in terms of fMAX, efficiency and latency

Allows for a lower power memory interface solution

Arria V and Cyclone® V devices also support hard memory interfaces. Typical expected performance and utilization figures for these hard controllers and PHYs are provided in the External Memory Interface Handbook.

Continuously advancing semiconductor process technologies have increase component integration, functionality, and performance in embedded systems. While increased capabilities reap huge rewards, one side effect of higher-performance memory systems is that more attention must be paid to the probability of soft errors.

Decreasing supply voltages cause integrated circuits to be more susceptible to various types of electromagnetic and particle radiation. As DRAM memory size in embedded systems grows to 100s of megabytes, soft errors due to alpha particles that occurs naturally may exceed acceptable levels. As interface speeds exceed 1 Gbps, excessive noise and jitter may cause errors in the transmission lines to and from the external memory.

Figure 1 Typical External DDR Memory Architecture

Error Resilience Through Error Correction Code

Driven by the increasing probability of soft errors, many designers are considering to add ECC to external DDR memory. ECC allows correction of single bit errors and drastically reduces the chance of a system failure. Intel® SoC FPGAs are well positioned to support ECC, as all required logic functions are integrated into the device. ECC on external memory can be enabled simply by extending the width of the DDR memory, as shown in Figure 1.

System-Level Approach to Error Resilience

SoCs extend support toward error resilience by including support for ECC on its large internal memories, specifically the level 2 cache of 512 KB and data buffers in on-chip peripherals.

High-performance embedded systems often use a 32 bit data bus to external DDR to obtain high throughput and frequently have a need for error resilience through ECC. The Intel SoC FPGA provides the high-performance and reliable combination of ECC and 32 bit interfacing.

The stated performances are the maximum clock rates supported in Intel® FPGAs based on the listed features across supported high-speed memory standards.

The maximum clock rates are only estimates based on a standalone FPGA ALTMEMPHY or UniPHY with Nios®-based sequencer and high-performance controller II instance generated with the default controller parameters in the Intel FPGA IP. For the actual performance of your design, you must always compile and perform timing analysis for your design in the Intel Quartus® Prime software.

The External Memory Interface Spec Estimator tool is available now for beta usage, subject to the External Memory Interface Spec Estimator Disclaimer. We would like to hear your feedback so we can fix potential browser compatibility issues and improve the overall value. If you are reporting technical issues, please include the browser and operating system (OS) information.