A.L.S.E the FPGA Expertshttps://www.alse-fr.com/
A.L.S.E: Advanced Logic Synthesis for Electronics, offers a complete range of Services, IPs, Training courses and Boards to help you with the design of FPGA-based and EmbeddedSystems..enSPIP - www.spip.netA.L.S.E the FPGA Expertshttps://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L144xH43/siteon0-ccad2.png?1505816372https://www.alse-fr.com/
43144HyperRAM Memory Controllerhttps://www.alse-fr.com/Hyper-RAM-Controller.html
https://www.alse-fr.com/Hyper-RAM-Controller.html2017-11-28T07:29:40Ztext/htmlenEtienne Laurendeau
<p>The new HyperRAM memories, based on low-power <span class="caps">PSRAM</span> technology, are a very welcome addition to the traditional <span class="caps">RAM</span> memories portfolio : they have been optimized for Mobile and Automotive applications. <br class='autobr' /> They provide good Bandwidth performance <br class='autobr' /> The interface, known as “HyperBus”, offers a low signal count (Address, Command and Data using only eight <span class="caps">DQ</span> pins) <br class='autobr' /> They offer Low Power consumption <br class='autobr' /> Typical power consumption during burst read is about 60 mA only. <br class='autobr' /> User-friendly protocol, with (…)</p>
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<a href="https://www.alse-fr.com/-Memory-Controllers-38-.html" rel="directory">Memory Controllers</a>
<div class='rss_chapo'><p>The new HyperRAM memories, based on low-power <span class="caps">PSRAM</span> technology, are a very welcome addition to the traditional <span class="caps">RAM</span> memories portfolio : they have been optimized for Mobile and Automotive applications.</p>
<ul class="spip"><li> They provide good Bandwidth performance</li><li> The interface, known as “HyperBus”, offers a low signal count (Address, Command and Data using only eight <span class="caps">DQ</span> pins)</li><li> They offer Low Power consumption<br class='manualbr' />Typical power consumption during burst read is about 60 mA only.</li><li> User-friendly protocol, with Hidden Refresh mode, for example</li><li> Most devices are available for Automotive Temperature range…</li></ul>
<p><span class="caps">ALSE</span> has designed a very-low resource usage <strong>HyperBus Memory Controller</strong>, in order to provide an easy interface to the HyperRAM memories, along with high performance (up to 333 MBytes/s, which is x1.5 times faster than a 16 bits <span class="caps">PSRAM</span> running @ 108MHz).</p></div>
<div class='rss_texte'><h2 class="spip">Main Technical Features</h2><ul class="spip"><li> <strong>High-Performance Controller</strong> supporting <strong>Burst</strong> Mode for Read/Write transfers, to get optimized bandwidth and minimal switch fabric overhead.</li><li> Memory Operating Frequency typically up to 166 MHz, depending on <span class="caps"><abbr title="Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.">FPGA</abbr></span> and Memory speed grades, and (more marginally) on the customer <span class="caps"><abbr title="Printed Circuit Board. A key and potentially extremely complex piece in any project.">PCB</abbr></span>. This delivers a bandwidth up to 333 MBytes/s, with only 12 x <span class="caps">IO</span> pins (<span class="caps">CS</span>, Clk/Clk_n, <span class="caps">DQS</span>, <span class="caps">DQ</span>[7:0])</li><li> <strong>16 bits Slave Data Interface</strong> with <strong>Burst</strong> support.</li><li> _ Typically, the Controller will serve a Master that can be an Altera Nios <span class="caps">II</span> <span class="caps">CPU</span>, with or without caches, with or without Burst mode. A hardware master (<span class="caps">DMA</span>) is of course also possible (e.g : Video streaming DMAs, etc…)</li><li> <strong>16 bits Slave Register Interface</strong> to access HyperRAM memory registers (for configuring Output Drive Strength, Burst Wrap, etc…)</li><li> <strong>Very low <span class="caps">FPGA</span> resource usage</strong> : less than 200 x Logic Cells, and 2 x memory blocks</li><li> Versatile : This <span class="caps"><abbr title="Intellectual Property. A usually complex function developed, tested and sold off-the-shelf to be re-used in customer's designs. Ranges from Processor cores to Memory Controllers to Video processing blocks etc… Some IPs are available from the FPGA vendor (free or at cost) or from 3rd parties.">IP</abbr></span> can be used in <strong>all <span class="caps">FPGA</span> devices</strong> (Intel / Altera, Xilinx, Lattice, MicroSemi / Actel) with internal memory blocks.</li><li> Intel Qsys (Platform Designer) compliant</li><li> Provided with sophisticated <strong><span class="caps">SDC</span> Timing Constraints</strong>, Hardware Tester Reference Designs on <span class="caps">FPGA</span> dev Kits (including the <em class="spip">Intel Cyclone 10 <span class="caps">LP</span> <span class="caps">FPGA</span> Evaluation Kit</em>), etc…</li></ul><h2 class="spip">Typical waveforms</h2>
<p>Here is above a typical waveform of a Write access, with initial Latency.</p>
<dl class='spip_document_56 spip_documents spip_documents_center'> <dt><img src='https://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH186/hyper_write-fa342.png?1511854356' width='500' height='186' alt="hyper write - PNG - 30.9 kb" /></dt> <dd class="crayon document-titre-56 spip_doc_titre" style="width:350px;"><strong>hyper write</strong></dd> </dl>
<p>Here is above a typical waveform of a Read accesses, with initial Latency.</p>
<dl class='spip_document_57 spip_documents spip_documents_center'> <dt><img src='https://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH204/hyper_read-ec678.png?1511854356' width='500' height='204' alt="hyper read - PNG - 34.9 kb" /></dt> <dd class="crayon document-titre-57 spip_doc_titre" style="width:350px;"><strong>hyper read</strong></dd> </dl><h2 class="spip">Examples of supported Memories</h2><ul class="spip"><li> <span class="caps">ISSI</span> <span class="caps">IS66</span>/<span class="caps">67WVH8M8ALL</span>/<span class="caps">BLL</span> - 64Mb</li><li> Cypress <span class="caps">S27KL</span>/S0641 - 64Mb</li><li> Cypress <span class="caps">S70KL</span>/S1281 - 128Mb</li><li> etc …</li></ul></div>
Aurora 8b/10b IP Corehttps://www.alse-fr.com/Aurora-8b-10b-IP-Core.html
https://www.alse-fr.com/Aurora-8b-10b-IP-Core.html2017-10-31T12:18:05Ztext/htmlenEtienne Laurendeau
<p>The Aurora 8b/10b <span class="caps">IP</span> Core is a lightweight high-speed serial protocol suitable for chip-to-chip, board-to-board and backplane applications using high speed transceivers. <br class='autobr' />
For Xilinx users, Aurora is available as a Xilinx Logicore <span class="caps">IP</span>. <br class='autobr' />
Our <span class="caps">IP</span> makes Aurora available to ASICs and to other FPGAs, including of course Intel-FPGAs (formerly Altera). <br class='autobr' />
Our <span class="caps">IP</span> provides an efficient way to interconnect an Intel-<span class="caps">FPGA</span> and a Xilinx <span class="caps">FPGA</span>, or any other chip (…)</p>
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<a href="https://www.alse-fr.com/-IP-s-.html" rel="directory">IPs</a>
<div class='rss_chapo'><p>The Aurora 8b/10b <span class="caps"><abbr title="Intellectual Property. A usually complex function developed, tested and sold off-the-shelf to be re-used in customer's designs. Ranges from Processor cores to Memory Controllers to Video processing blocks etc… Some IPs are available from the FPGA vendor (free or at cost) or from 3rd parties.">IP</abbr></span> Core is a lightweight high-speed serial protocol suitable for chip-to-chip, board-to-board and backplane applications using high speed transceivers.<br class='manualbr' />For Xilinx users, Aurora is available as a Xilinx Logicore <span class="caps">IP</span>. <br class='manualbr' />Our <span class="caps">IP</span> makes Aurora available to ASICs and to other FPGAs, including of course Intel-FPGAs (formerly Altera).<br class='manualbr' />Our <span class="caps">IP</span> provides an efficient way to interconnect an Intel-<span class="caps"><abbr title="Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.">FPGA</abbr></span> and a Xilinx <span class="caps">FPGA</span>, or any other chip (<span class="caps"><abbr title="Application Specific Integrated Circuit. It is a Custom Design chip implementing usually many functions and designed by a customer. As opposed to Programmable devices or to ASSPs.">ASIC</abbr></span>, <span class="caps"><abbr title="(from Wiki) an Application Specific Standard Product is an integrated circuit that implements a specific function that appeals to a wide market (examples are microprocessors, DSPs, various controllers etc). ASSPs are available as off-the-shelf components.">ASSP</abbr></span>, etc …) using the Aurora protocol. It can even be used to interconnect two Intel-FPGAs together, in replacement of other proprietary or complex High-Speed Serial protocols (like Serial Lite 3 or PCIExpress).<br class='manualbr' />The Figure below shows a typical application of the <span class="caps">IP</span> :</p>
<dl class='spip_document_53 spip_documents spip_documents_center'> <dt><img src='https://www.alse-fr.com/sites/alse-fr.com/IMG/png/aurora_typical_application.png' width='851' height='302' alt="Aurora Typical Application - PNG - 59.5 kb" /></dt> <dd class="crayon document-titre-53 spip_doc_titre" style="width:350px;"><strong>Aurora Typical Application</strong></dd> </dl></div>
<div class='rss_texte'><h2 class="spip">Main Aurora-Protocol Supported Features</h2><ul class="spip"><li> Full-Duplex and Simplex Tx Operations.</li><li> Currently demonstrated at up to 6.6 Gbps (Gigabits per seconds) per Transceiver lane. Higher bitrates are possible depending on the Device Transceiver characteristics.</li><li> Up to 16 Transceiver lanes.</li><li> Framing and Streaming interface.</li><li> Payload Data User Frames (<span class="caps">PDU</span>)</li><li> User Flow Control (<span class="caps">UFC</span>).</li><li> Native Flow Control (<span class="caps">NFC</span>), in immediate and completion mode.</li><li> Additional <span class="caps">CRC</span> for <span class="caps">PDU</span> Frames</li><li> 8b/10b Encoding / Decoding.</li><li> Clock Compensation sequence generation.</li><li> Per lane polarity inversion and skew compensation.</li><li> User datapath depending on number of lanes and 16bits/32bits mode per Transceiver lane. Examples : <br class='manualbr' />-> in a x1 /32bits configuration, the user datapath is 32bits.<br class='manualbr' />-> in a x4 /32bits configuration, the user datapath is 128bits.<br class='manualbr' />-> in a x4 /16bits configuration, the user datapath is 64bits.</li></ul>
<p>Not (yet) supported :</p>
<ul class="spip"><li> Simplex Rx Operation</li></ul><h2 class="spip">Other Technical Features</h2><ul class="spip"><li> Most recent Intel-FPGAs are supported : Arria 10, Stratix V, Arria V, Cyclone V. For other Altera / Intel families, or for any other <span class="caps"><abbr title="Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.">FPGA</abbr></span> vendor (e.g : Lattice), please contact <span class="caps">ALSE</span>.</li><li> <span class="caps">AXI</span> streaming / Avalon-<span class="caps">ST</span> compatible for User interfaces (<span class="caps">PDU</span>, <span class="caps">NFC</span>, <span class="caps">UFC</span>)</li><li> <strong>Very low <span class="caps">FPGA</span> resource usage</strong> : typically less than 1000 ALMs / 2 Memory Blocks for a Full <span class="caps"><abbr title="Intellectual Property. A usually complex function developed, tested and sold off-the-shelf to be re-used in customer's designs. Ranges from Processor cores to Memory Controllers to Video processing blocks etc… Some IPs are available from the FPGA vendor (free or at cost) or from 3rd parties.">IP</abbr></span> in a x1 (1 lane) configuration</li><li> Provided with <span class="caps">SDC</span> Timing Constraints and <span class="caps">QIP</span> file for easy integration</li><li> <strong>Hardware Tester Reference Designs</strong></li></ul><h2 class="spip">Examples of existing Hardware Tester Reference Designs</h2><ul class="spip"><li> CycloneV Clovis -> Xilinx Virtex6 <span class="caps">ML605</span>, x1 - 3.125Gbps</li><li> CycloneV Clovis -> Xilinx Virtex7 <span class="caps">VC707</span>, x1 - 3.125Gbps</li><li> Arria10 Attila -> Xilinx Virtex7 <span class="caps">VC707</span>, x1 - 6.25Gbps</li><li> Arria10 Achilles -> Arria10 Attila, x4 - 6.25Gbps</li><li> etc …</li></ul></div>
Designing for Stratix 10 FPGAshttps://www.alse-fr.com/Designing-for-Stratix-10-FPGAs.html
https://www.alse-fr.com/Designing-for-Stratix-10-FPGAs.html2017-08-16T10:21:19Ztext/htmlenBertrand Cuzeau
<p>The new Intel 14 nm Stratix 10 <span class="caps">FPGA</span> family offer unprecedented performance. <br class='autobr' />
However, taking full advantage of this new architecture and associated design tools requires to adopt new design techniques and use a new generation of tools. We have the proper trainings offer to help customers. <br class='autobr' />
This ApNote is merely an illustration of how to achieve simply good performance with little efforts.
<br class='autobr' /> Ultimate performance will require more efforts, but starting from a sound design will always (…)</p>
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<a href="https://www.alse-fr.com/-Application-Notes-.html" rel="directory">Application Notes</a>
<div class='rss_chapo'><p>The new Intel 14 nm Stratix 10 <span class="caps"><abbr title="Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.">FPGA</abbr></span> family offer unprecedented performance.</p>
<p>However, taking full advantage of this new architecture and associated design tools requires to adopt new design techniques and use a new generation of tools. We have the proper trainings offer to help customers.</p>
<p>This ApNote is merely an illustration of how to achieve simply good performance with little efforts.<br class='autobr' />
Ultimate performance will require more efforts, but starting from a sound design will always help.</p></div>
NUMERIC_STD Issue.https://www.alse-fr.com/20-NUMERIC_STD-Issue.html
https://www.alse-fr.com/20-NUMERIC_STD-Issue.html2017-03-01T13:28:56Ztext/htmlenBertrand Cuzeau<p>This article describes an error that I found only recently in NUMERIC_STD.</p>
<p>Conclusion : do not multiply signed or unsigned vectors by an integer !</p>
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<a href="https://www.alse-fr.com/-VHDL-helper-.html" rel="directory">VHDL helper</a>
<div class='rss_texte'><h2 class="spip">Description</h2>
<p>The <span class="caps">IEEE</span> numeric_std library issued (eg) in Nov 1994, and which (as of March 2017) is still used in the latest versions of the Simulation and Synthesis tools, implements incorrectly the multiplications of signed/unsigned vectors by an integer.</p>
<p>Fixing these functions is not difficult but my attempt to have the <span class="caps"><abbr title="VHSIC Hardware Description Language. _ A consequence of the US DOD's VHSIC program, this language (normalized as IEEE 1076) was created to describe accurately the behavior of High Speed Integrated Circuits.">VHDL</abbr></span> working group adopt the fix has been so far unsuccessful. But even if I had quickly succeeded, the change would not have been available probably for many (many) years !</p>
<p>So it's best that you understand the problem and learn how to avoid it.</p>
<h2 class="spip">Functions affected</h2>
<p>Here are the original prototypes (in <span class="caps">IEEE</span>.numeric_std) :</p>
<div style='text-align: left;' class='spip_code' dir='ltr'><code> -- Id: A.17<br /> function "*" ( L: UNSIGNED; R: NATURAL) return UNSIGNED;<br /> -- Result subtype: UNSIGNED((L'length+L'length-1) downto 0).<br /> -- Result: Multiplies an UNSIGNED vector, L, with a non-negative <br /> -- INTEGER, R. R is converted to an UNSIGNED vector of <br /> -- SIZE L'length before multiplication.<br /> <br /> -- Id: A.18<br /> function "*" ( L: NATURAL; R: UNSIGNED) return UNSIGNED;<br /> -- Result subtype: UNSIGNED((R'length+R'length-1) downto 0).<br /> -- Result: Multiplies an UNSIGNED vector, R, with a non-negative <br /> -- INTEGER, L. L is converted to an UNSIGNED vector of <br /> -- SIZE R'length before multiplication.<br /> <br /> -- Id: A.19<br /> function "*" ( L: SIGNED; R: INTEGER) return SIGNED;<br /> -- Result subtype: SIGNED((L'length+L'length-1) downto 0)<br /> -- Result: Multiplies a SIGNED vector, L, with an INTEGER, R. R is<br /> -- converted to a SIGNED vector of SIZE L'length before <br /> -- multiplication.<br /> <br /> -- Id: A.20<br /> function "*" ( L: INTEGER; R: SIGNED) return SIGNED;<br /> -- Result subtype: SIGNED((R'length+R'length-1) downto 0)<br /> -- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is<br /> -- converted to a SIGNED vector of SIZE R'length before <br /> -- multiplication.</code></div><h2 class="spip">Issue</h2>
<p>As we can see above (in the comments), when multiplying a vector by an integer, the integer is converted into a vector <em class="spip">of the same width as the other operand</em> !!!</p>
<p>As a consequence, the result's width is forced to two times the width of the signed/unsigned vector, just as if the vector was squared (multiplied by itself), which absolutely does <span class="caps">NOT</span> make sense.</p>
<p>The result is either too short or too large.</p>
<h2 class="spip">Consequences</h2><ul class="spip"><li> Multiplying a vector by 1 (or a small integer) creates a vector twice as large. <br class='manualbr' />Quite inefficient, a bit ridiculous, but relatively harmless.</li><li> Multiplying a 128-bits vector by 7 (eg) creates a 256-bits results.<br class='manualbr' />Same remark as above.</li><li> The result of Multiplying an 8-bits unsigned vector by 256 is a 16-bits vector (okay by chance) but <strong class="caractencadre-spip spip">with a value of <span class="caps">ZERO</span></strong> ! See the test case included.<br class='manualbr' />This is definitely <span class="caps">VERY</span> <span class="caps">WRONG</span> :-( and the multiplication result is not usable.</li><li> Multiplying a 8-bits signed vector by 1000 (decimal) produces an incorrect result (actually V * 232) and the result is limited to 16 bits anyway.<br class='manualbr' />This is also very wrong.</li></ul>
<p>Note that simulators will typically issue truncation warnings <em class="spip">during the simulation</em> (run-time) in the most offending cases, or refuse to compile if the result width is not what the user believed (which is how I uncovered the issue).<br class='manualbr' />But Synthesis tools will compile and generate hardware which can potentially produce incorrect results, and this is not acceptable.</p>
<h2 class="spip">Are these functions useful ?</h2>
<p>Certainly. They are required by the principle of numeric_std which is to extend arithmetic operators to vectors that represent numbers (signed and unsigned).</p>
<p>Moreover, Synthesis tools are usually relatively smart when they see multiplications by constants, in which case they know how to replace the multiplication by adder(s).</p>
<p>However, their use has been limited (which explains why the incorrect implementation hasn't been reported heavily before).<br class='autobr' />
One can note that the older Synopsys library “std_logic_arith” did not provide the multiplication of signed/unsigned vector by integers, and therefore could not have the same problem.</p>
<h2 class="spip">Repairing NUMERIC_STD ?</h2>
<p>Fixing the affected functions is not complicated : it suffices to convert the natural or integer into a <strong class="caractencadre-spip spip">32-bits</strong> vector !<br class='autobr' />
The resulting width at least starts making some sense (=Operand width + 32) and no truncation / incorrect result can occur.<br class='autobr' />
If the result is still too large for you (like when you multiply by an integer <em class="spip">range</em>), you just have to resize the result. If you loose information in the resize (you resized into a too short vector), you would get a run time warning as usual.</p>
<p><strong class="caractencadre-spip spip"><span class="caps">BUT</span>, the issue is that numeric_std will probably never be fixed !</strong></p>
<p>So you have to take care of your code and make sure you are not affected by the library errors, as explained below.</p>
<h2 class="spip">Conclusion</h2>
<p>In spite of the library clumsiness (shift operators, and this bug in particular), I still keep recommending using numeric_std instead of other non-<span class="caps">IEEE</span> libraries.</p>
<p>My <a href='https://www.alse-fr.com/VHDL-Coding-Guide.html' class='spip_in'><strong><span class="caps">VHDL</span> Coding Style Guide</strong></a> is updated :</p>
<ul class="spip"><li> Do not multiply signed/unsigned vectors by Integers.
<ul class="spip"><li> Use slices and adders if you multiply by an integer constant</li><li> Convert the integer in a properly sized signed or unsigned vector before multiplying.</li></ul></li></ul>
<p>and the older recommendation remains :</p>
<ul class="spip"><li> Avoid using shift/rotate operators from numeric_std (use slices & concatenation)</li></ul>
<p>And finally : kudos to the incredible Technical Support at Mentor / Model Technology !</p></div>
VHDL Coding Guidehttps://www.alse-fr.com/VHDL-Coding-Guide.html
https://www.alse-fr.com/VHDL-Coding-Guide.html2016-11-08T18:34:05Ztext/htmlenBertrand Cuzeau<p>This <span class="caps"><abbr title="VHSIC Hardware Description Language. _ A consequence of the US DOD's VHSIC program, this language (normalized as IEEE 1076) was created to describe accurately the behavior of High Speed Integrated Circuits.">VHDL</abbr></span> Coding Guide can significantly help improve your coding style as well as the quality of your designs !</p>
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<a href="https://www.alse-fr.com/-VHDL-Coding-Guide-40-.html" rel="directory">VHDL Coding Guide</a>
<div class='rss_chapo'><p>By our (long) experience, many designers code without using any Coding Guide. <br class='manualbr' />From the smallest one-man operation to the largest multi-national company, this is never good.<br class='manualbr' />However, we have also seen some totally counter-productive Coding Guides (usually in large companies).<br class='manualbr' />This was the motivation in creating this document in 2004. <br class='autobr' />
Surprisingly, this Guide has remained extremely stable and the 2016 version is very close to the original version, which is an indication of its quality !</p></div>
<div class='rss_texte'><h2 class="spip">Introduction</h2>
<p>These rules and coding style are the result of more than 23 years of <span class="caps"><abbr title="Hardware Description Language. _ Some HDLs are : Verilog, SystemVerilog, VHDL, SystemC. _ First-generation (now obsolete) HDLs : Abel, CUPL etc">HDL</abbr></span> design and teaching experience, hundreds of complex <span class="caps"><abbr title="Application Specific Integrated Circuit. It is a Custom Design chip implementing usually many functions and designed by a customer. As opposed to Programmable devices or to ASSPs.">ASIC</abbr></span> & <span class="caps"><abbr title="Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.">FPGA</abbr></span> projects, hundreds of thousands of lines of code, and the development of a very rich portfolio of complex IPs.</p>
<p>This Coding Guide is “reasonable”: small and simple enough to be easily remembered, “no-nonense” in that only useful rules have been kept. However it is covering a lot of the usual mistakes and it can significantly enhance the quality of the <span class="caps"><abbr title="VHSIC Hardware Description Language. _ A consequence of the US DOD's VHSIC program, this language (normalized as IEEE 1076) was created to describe accurately the behavior of High Speed Integrated Circuits.">VHDL</abbr></span> code.</p>
<h2 class="spip">Caveat</h2>
<p>It is probably useful to remind at this stage that :</p>
<ol class="spip"><li> Following the rules is not sufficient <em class="spip">per se</em>: this Coding Guide is in no way teaching the fundamental principles that any <span class="caps">HDL</span> designer must master to create efficient and reliably working designs.<br class='manualbr' />It is the purpose of our <em class="spip">Training Courses</em> !</li></ol><ol class="spip"><li> The other way around is also true: some of these rules can be bent while a correct, working, design is achieved, if there is a good understanding of the potential issues that may result.</li></ol><ol class="spip"><li> The Naming Conventions proposed here are not absolute rules. You may decide to adopt other naming conventions, but it is not acceptable to not have any naming convention enforced at all!</li></ol>
<p>In summary, this document is only proposing a number of recommendations that, if followed, will reduce the design risks and globally augment the code quality and reliability.</p>
<h2 class="spip">Copyright <span class="caps">ALSE</span></h2>
<p>These Coding Rules are copyright <span class="caps">ALSE</span>. <br class='autobr' />
If you want to reproduce them or use them by any means, you must contact <span class="caps">ALSE</span> and request an authorization.<br class='autobr' />
However, strictly personal use is allowed.</p>
<h2 class="spip">Obtaining the full document</h2>
<p>You can view the complete Guide using the link below.</p></div>
PowerLinkhttps://www.alse-fr.com/PowerLink.html
https://www.alse-fr.com/PowerLink.html2016-11-08T06:34:56Ztext/htmlenBertrand Cuzeau, Sylvain Lesne<p><span class="caps">POWERLINK</span> is our choice as of Standard Real-time Industrial Ethernet Network. We have acquired a serious know-how and we have the capability to quickly port this network to any <span class="caps"><abbr title="Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.">FPGA</abbr></span>, as we have done for the Altera Max10 when it became available.</p>
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<a href="https://www.alse-fr.com/-Industrial-Ethernet-.html" rel="directory">Industrial Ethernet</a>
<div class='rss_texte'><h2 class="spip">Introduction</h2>
<p>After accumulating some experience with other Industrial Networks on <span class="caps"><abbr title="Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.">FPGA</abbr></span>, we converged on retaining only <a href="http://www.ethernet-powerlink.org/" class='spip_out' rel='external'><span class="caps">POWERLINK</span></a> as well as our own Ultra-Low Latency Gigabit ring.</p>
<p><span class="caps">POWERLINK</span> is a fast real-time field bus based on standard Ethernet. <a href="http://openpowerlink.sourceforge.net/web/" class='spip_out' rel='external'>openPOWERLINK</a> is an open-source implementation of this protocol, and comes with example designs targeting Intel (previously Altera) FPGAs.</p>
<h2 class="spip">Experience</h2>
<p>Our experience with <span class="caps">POWERLINK</span> was very successful :</p>
<ul class="spip"><li> We quickly mastered the <span class="caps">POWERLINK</span> Slave Development Kit</li><li> We were able to build fully working slaves on very low cost <span class="caps">FPGA</span> boards (including the $25 BeMicroMax10 !)</li><li> The interaction with the openPOWERLINK maintainers was easy and productive.</li><li> B&R offers a serious support for Powerlink adopters.</li></ul>
<p>Take a look at <a href='https://www.alse-fr.com/sites/alse-fr.com/IMG/pdf/openpowerlink_max10.pdf' class='spip_in' title="this presentation – PDF (1.1 Mb)" type='application/pdf'>this presentation</a> to find out more details about the systems we implemented.</p></div>
Synchronous SRAM (SSRAM) Controllerhttps://www.alse-fr.com/Synchronous-SRAM-SSRAM-Controller.html
https://www.alse-fr.com/Synchronous-SRAM-SSRAM-Controller.html2016-11-07T14:28:21Ztext/htmlenEtienne Laurendeau
<p>Low Latency is often very important in many fields such as cache-based products, broadcast, networking and communications applications, video streaming / video games, etc … <br class='autobr' />
Synchronous <span class="caps">SRAM</span> memories are very good candidates for such latency-sensitive applications, thanks to their (very) low latency (typically one clock cycle), high performance. <br class='autobr' />
Interfacing such memories to an <span class="caps">FPGA</span> is easy using the optimized <span class="caps">ALSE</span> controller. Thanks to its very small <span class="caps">FPGA</span> footprint and low resource usage, (…)</p>
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<a href="https://www.alse-fr.com/-Memory-Controllers-38-.html" rel="directory">Memory Controllers</a>
<div class='rss_chapo'><p>Low Latency is often very important in many fields such as cache-based products, broadcast, networking and communications applications, video streaming / video games, etc … <br class='manualbr' />Synchronous <span class="caps">SRAM</span> memories are very good candidates for such latency-sensitive applications, thanks to their (very) low latency (typically one clock cycle), high performance. <br class='manualbr' />Interfacing such memories to an <span class="caps"><abbr title="Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.">FPGA</abbr></span> is easy using the optimized <span class="caps">ALSE</span> controller. Thanks to its very small <span class="caps">FPGA</span> footprint and low resource usage, this controller fits in the smallest FPGAs, which makes it also perfect for the Automotive and Consumer Markets.</p></div>
<div class='rss_texte'><h2 class="spip">Main Technical Features</h2><ul class="spip"><li> <strong>High-Performance Controller</strong> supporting <strong>Burst </strong> Mode for Read/Write transfers, to get optimized transfer speed and minimal switch fabric overhead.</li><li> Memory Operating Frequency typically up to 133 MHz, depending on <span class="caps"><abbr title="Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.">FPGA</abbr></span> and Memory speed grades, and (more marginally) on the customer <span class="caps"><abbr title="Printed Circuit Board. A key and potentially extremely complex piece in any project.">PCB</abbr></span> characteristics.</li><li> <strong>32bits Slave Interface</strong> (Avalon-<span class="caps">MM</span> based) with <strong>Burst</strong> support. Typically, the Controller will serve a Master that can be an Altera Nios <span class="caps">II</span> <span class="caps">CPU</span> (32bits), with or without caches, with or without Burst mode. A hardware master (<span class="caps">DMA</span>) is of course also possible (e.g : Video streaming DMAs, etc …)</li><li> Specific version of the controller for <strong>No Bus Latency</strong> memories, also called Zero Wait States memories (such as <span class="caps">ISSI</span> <span class="caps">IS61NLF204836B</span> / <span class="caps">IS61NLF409618B</span>, or Cypress <span class="caps">CY7C1471BV33</span> / <span class="caps">CY7C1473BV33</span>), for <strong>100% bandwidth</strong> utilization (no dead cycles)</li><li> <strong>Very low <span class="caps">FPGA</span> resource usage</strong> : less than 200 Logic Cells, and two memory blocks</li><li> Versatile : This <span class="caps"><abbr title="Intellectual Property. A usually complex function developed, tested and sold off-the-shelf to be re-used in customer's designs. Ranges from Processor cores to Memory Controllers to Video processing blocks etc… Some IPs are available from the FPGA vendor (free or at cost) or from 3rd parties.">IP</abbr></span> can be used in <strong>all <span class="caps">FPGA</span> devices</strong> (Intel / Altera, Xilinx, Lattice, MicroSemi / Actel) having internal memory blocks.</li><li> Provided with sophisticated <strong><span class="caps">SDC</span> Timing Constraints</strong>, Hardware Tester Reference Designs, etc…</li></ul><h2 class="spip">Typical waveforms</h2><dl class='spip_document_40 spip_documents spip_documents_center'> <dt><img src='https://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH403/ssram_no_bus_latency_waveforms-f7547.jpg?1505816372' width='500' height='403' alt="SSRAM no bus latency waveform - JPEG - 196.3 kb" /></dt> <dd class="crayon document-titre-40 spip_doc_titre" style="width:350px;"><strong><span class="caps">SSRAM</span> no bus latency waveform</strong></dd> </dl>
<p>Here is above a typical waveform of consecutive Read/Write accesses, with/without bursts, with Zero Wait state (no bus latency) and thus 100% bandwidth utilization. The clock can be up to 133 MHz here.</p>
<h2 class="spip">Examples of supported Memories</h2><ul class="spip"><li> <span class="caps">ISSI</span> <span class="caps">IS61LPS25632B</span></li><li> <span class="caps">ISSI</span> <span class="caps">IS61NLF204836B</span>/<span class="caps">IS61NLF409618B</span></li><li> Cypress <span class="caps">CY7C1471BV33</span> / <span class="caps">CY7C1473BV33</span></li><li> etc …</li></ul></div>
Ultra Low Latency Networkhttps://www.alse-fr.com/Ultra-Low-Latency-Network.html
https://www.alse-fr.com/Ultra-Low-Latency-Network.html2016-10-04T17:24:21Ztext/htmlenBertrand Cuzeau<p>No existing Industrial Network provided the performance (latency & throughput) that a customer application required, so we have developed this Ultra-Low Latency redundant network.</p>
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<a href="https://www.alse-fr.com/-Industrial-Ethernet-.html" rel="directory">Industrial Ethernet</a>
<div class='rss_texte'><h2 class="spip">Introduction</h2>
<p>Gigabit Ethernet over copper twisted pairs (<span class="caps">1000BASE</span>-T) is an ubiquitous, easy,<br class='autobr' />
and extremely reliable Physical Medium.<br class='manualbr' /><span class="caps">ALSE</span> has developed a lot of experience around this technology, like the very<br class='autobr' />
innovative <span class="caps"><abbr title="Gigabit Ethernet Data Exchange Kit. “Hardware Stack” Concept invented by ALSE, GEDEK is a processor-less autonomous block which implements the Ethernet protocols required to establish, maintain, and perform high performance data exchange over standard Ethernet.">GEDEK</abbr></span> communication kit (processor-less hardware stack) and allowed<br class='autobr' />
achieving reliably unprecedented data throughput. This technology has been used<br class='autobr' />
in hundreds of systems all over the world.</p>
<p>One of our clients expressed the need to build an architecture with up to more<br class='autobr' />
than 20 regulation and control boards interconnected together, and with a<br class='autobr' />
requirement that all boards should be updated with the regulation data<br class='autobr' />
from <span class="caps">ALL</span> <span class="caps">OTHER</span> boards during the first half of a single <span class="caps">PWM</span> cycle<br class='autobr' />
(targeted at 20 kHz).<br class='autobr' />
In other words, all the boards should see all the other board's data in no more<br class='autobr' />
than 25 micro-seconds.</p>
<p>Another requirement was the ability to implement <em class="spip">redundancy</em>.</p>
<p>Quite naturally <strong>Gigabit Ethernet</strong> comes to mind to implement the inter-boards communication.<br class='manualbr' />However, even under underestimated conditions (20 slaves, 20 kHz, no redundancy),<br class='autobr' />
40 Ethernet frames must circulate in much less than 25 µs.<br class='autobr' />
This simple calculation shows that a standard (store-forward) architecture,<br class='autobr' />
even with a near zero delay (like <span class="caps">GEDEK</span>) would be outperformed by a ratio greater<br class='autobr' />
than four !</p>
<h2 class="spip">Are existing solutions available ?</h2>
<p>We conducted a careful pre-study and reached the conclusion that <span class="caps">NO</span> <span class="caps">SOLUTION</span> existed<br class='autobr' />
in the market that reached only a fraction of the performance required !</p>
<p>The table below, extracted from a very <a href="http://www.ethernet-powerlink.org/fileadmin/user_upload/Dokumente/Dokumente/EPSG_IEF2ndEdition_en_WEB.pdf" class='spip_out' rel='external'>interesting article</a> about Industrial Ethernet shows the state of the art.</p>
<p>[table]</p>
<dl class='spip_document_37 spip_documents spip_documents_center'> <dt> <img alt="Industrial Ethernet standards Cycle Time" src='https://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L474xH310/indnetwcycletime-e5817.jpg?1505816372' width='474' height='310' /> </dt> <dd class="crayon document-titre-37 spip_doc_titre" style="width:350px;"><strong>Industrial Ethernet standards Cycle Time</strong></dd> </dl><h2 class="spip">Our solution</h2><ul class="spip"><li> We use completely <strong>standard <span class="caps">IEEE</span> 802.3-2008 Ethernet frames</strong>.</li></ul><ul class="spip"><li> We implement a <strong>“circular” bi-directional (dual) ring</strong>.<br class='autobr' />
Two frames circulate in opposite directions for a full turn, thus already<br class='autobr' />
implementing a first redundancy.</li></ul><ul class="spip"><li> We use the <strong>Cut-Through Forwarding</strong> technology in our own optimized switch<br class='autobr' />
to reach an absolute minimal latency.</li></ul><ul class="spip"><li> We use the <strong>Summation Frame</strong> method<br class='autobr' />
(each node adds it's own data in a slot of the circulating frame).</li></ul><ul class="spip"><li> We use a <strong>fully Hardware implementation</strong>, thus removing any software interaction<br class='autobr' />
or limitation to the performance. In Hardware, decisions can be taken in less<br class='autobr' />
than 10 nanoseconds (ie practically at each incoming byte in the GbE link),<br class='autobr' />
with no jitter.</li></ul><ul class="spip"><li> We re-used (and customized) our optimized and well proven Gigabit-only <span class="caps"><abbr title="Media Access Controller. The Ethernet (802.3) MAC block is connected to the Media Interface of the Ethernet PHY (the PHYsical transceiver chip) in order to send and receive streams of bytes.">MAC</abbr></span><br class='autobr' />
(Media Access Control).</li></ul>
<p>Note : We have implemented several clever optimizations to further reduce our cut-through<br class='autobr' />
switch latency. The details are only available after signing an <span class="caps">NDA</span>.</p>
<h2 class="spip">Network Topology</h2>
<p>The figure below shows 9 boards connected together, one of which being the Master.</p>
<dl class='spip_document_39 spip_documents spip_documents_center'> <dt> <img alt="Network (ring) Topology" src='https://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH555/netw_topo-37157.jpg?1505816372' width='500' height='555' /> </dt> <dd class="crayon document-titre-39 spip_doc_titre" style="width:350px;"><strong>Network (ring) Topology</strong></dd> </dl><h2 class="spip">Test System</h2>
<p>We have used 9 <span class="caps">DE2</span>-115 <span class="caps"><abbr title="Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.">FPGA</abbr></span> kits attached together mechanically to form a “tower”.<br class='autobr' />
See picture below. The <span class="caps">DE2</span>-115 (used in some Training courses) was available and it comes with two <span class="caps">GBE</span> interfaces (Marvell 88E1111 <span class="caps"><abbr title="PHYsical Interface. Device in charge of handling (encoding and decoding) the lowest layer of the protocol (the physical signals). In case of Ethernet, the PHY chip is connected to the magnetics &#38; RJ45 on one side, and offers a normalized data interface (MII, GMII, RGMII, SGMII etc).">PHY</abbr></span>).</p>
<p>This setup allows to practically measure with great precision the achieved<br class='autobr' />
latency in realistic conditions (including the delays in the Marvell Gigabit PHYs).<br class='autobr' />
The results were extremely close to our simulations.</p>
<dl class='spip_document_38 spip_documents spip_documents_center'> <dt> <img alt="Tower of DE2-115" src='https://www.alse-fr.com/sites/alse-fr.com/local/cache-vignettes/L500xH667/tower-7f982.jpg?1505816372' width='500' height='667' /> </dt> <dd class="crayon document-titre-38 spip_doc_titre" style="width:350px;"><strong>Tower of <span class="caps">DE2</span>-115</strong></dd> </dl><h2 class="spip">Complementary tools</h2>
<p>We have developed an “Embedded Sniffer” : a special version of the Master<br class='autobr' />
forwards all (or some) circulating frames to another (3<sup class="typo_exposants">rd</sup>) Ethernet port for<br class='autobr' />
analysis with a <span class="caps">PC</span> using Wireshark, without disturbing the Ring network.</p>
<h2 class="spip">Conclusion</h2>
<p>Our technology (based on an optimized ultra-low latency Gigabit Ethernet cut-through switch) can enable a new range of industrial applications that were not feasible so far.</p></div>
<div class='rss_ps'><p>If your system consists of several boards that need to communicate<br class='autobr' />
with each other and exchange data with very small delays and latency,<br class='autobr' />
our technology may help you.<br class='autobr' />
Do not hesitate to <a href='https://www.alse-fr.com/Contact.html' class='spip_in'>Contact us</a></p></div>
PCI Express for FPGAshttps://www.alse-fr.com/PCI-Express.html
https://www.alse-fr.com/PCI-Express.html2016-10-03T21:16:30Ztext/htmlenBertrand Cuzeau, Guillaume JOLI<p>Most <span class="caps"><abbr title="Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.">FPGA</abbr></span> designers still find it very difficult to use <span class="caps">PCI</span> Express in a project. <br class='manualbr' />We have designed a lot of <span class="caps">PCI</span> Express IPs and we do not believe in the “off-the-shelf” model.<br class='manualbr' />We can create just the <span class="caps"><abbr title="Intellectual Property. A usually complex function developed, tested and sold off-the-shelf to be re-used in customer's designs. Ranges from Processor cores to Memory Controllers to Video processing blocks etc… Some IPs are available from the FPGA vendor (free or at cost) or from 3rd parties.">IP</abbr></span> you need, even including the proper driver, in a matter of days.</p>
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<a href="https://www.alse-fr.com/-IP-s-.html" rel="directory">IPs</a>
<div class='rss_texte'><h2 class="spip">Assumption</h2>
<p>In this section, we assume you are wanting to use an <span class="caps"><abbr title="Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.">FPGA</abbr></span> that includes a Hardware PCIe block. While it is possible to design PCIe “soft-IPs”, this cannot be true for Gen2 and Gen3, and it's definitely not a good idea for several other reasons. So we are not offering soft-IPs, just IPs that use the low-level “Hard IPs” that can be found in all modern FPGAs.</p>
<h2 class="spip">Introduction</h2>
<p>FPGAs including <span class="caps">PCI</span> Express hard-IPs have been available for a relatively long time. However, it is still surprisingly difficult to use this interface in a project and we keep seeing customers struggling.</p>
<p>We can find several explanations :</p>
<ul class="spip"><li> The protocol itself is rich and therefore quite complex</li><li> The concepts behind PCIe are not trivial</li><li> The <span class="caps">FPGA</span>'s Hard-IPs are also quite complex themselves, and configurable beasts</li><li> The PCIe bandwidth is usually very high, so moving data efficiently is often an absolute requirement. This typically means using Modular <span class="caps">SGDMA</span> engines and serving them adequately.</li><li> The amount of data exchanged is also often very high (for example high-res images at high frame rate).</li><li> The “other side” (often a <span class="caps">PC</span> or a processor) has to run a “driver” that talks to the <span class="caps">FPGA</span>. And this driver has to be developed while being perfectly aligned with the hardware. And it's often difficult to find both high-end Hardware <em class="spip">and</em> Software specialists available for the project and working together.</li><li> “Example Designs”, “Reference Designs”, “Best In Class” designs etc are usually a lost cause and can make you err rather than being helpful.</li></ul><h2 class="spip">Forget about Cut & Paste…</h2>
<p>“Google programming” (trying to re-use existing code publicly available) won't cut it.<br class='manualbr' />If you do not really and exhaustively master the subject, you won't be able to build and debug something which will work reliably and with the performance you expect.</p>
<h2 class="spip">Bespoke ? Way to go !</h2>
<p>By experience, the way a given application needs to use the <span class="caps">PCI</span> Express interface is typically quite unique : the Generation number, the <span class="caps">FPGA</span> family, the number of lanes, the type of transfer, the number of BARs, the presence of <span class="caps">ROM</span>, the type of data, the data flow, the software constraints, the memory constraints, etc…</p>
<p>In practice, we have given up the idea of putting a “standard” PCIe <span class="caps"><abbr title="Intellectual Property. A usually complex function developed, tested and sold off-the-shelf to be re-used in customer's designs. Ranges from Processor cores to Memory Controllers to Video processing blocks etc… Some IPs are available from the FPGA vendor (free or at cost) or from 3rd parties.">IP</abbr></span> on the shelf, in favor of a model where we can design an <span class="caps">IP</span> that matches exactly the design requirements, while offering it at competitive prices, and even as source code if desired !</p>
<p>We have a good history of projects where we were able to address extremely tough challenges with reasonable efforts. Our know-how combined with the number of projects <br class='autobr' />
we have designed are the assurance of a rapid convergence and allow us to propose very fair prices.</p>
<h2 class="spip">We will train you !</h2>
<p>The second reason why we can help you efficiently (beyond designing the Interface for you) is that we can train you and make sure you become familiar enough with the <span class="caps">PCI</span> Express protocol, with the Hard <span class="caps">IP</span>, with our code and with the Driver. And that, consequently, you won't need us to maintain and iterate your design.</p>
<p>We can even train you <em class="spip">before</em> you (or <span class="caps">ALSE</span>) start your design. After the training, you can decide whether it's better to let us design this part or if you want to do it yourself.<br class='manualbr' />Keep in mind that we always try to figure out what is best <span class="caps">FOR</span> <span class="caps">YOU</span> !</p>
<h2 class="spip">Win-Win</h2>
<p>This approach is the only Win-Win solution : you have a working high-performance solution, with our backup, and you will have gained enough competence to be autonomous throughout your project's life. You end up with the lowest possible cost and the highest gained competence.</p>
<h2 class="spip">Where to start ?</h2>
<p>If your project is going to require a <span class="caps">PCI</span> Express interface and if you think we might help you, then <a href='https://www.alse-fr.com/Contact.html' class='spip_in'>Contact us</a> (and tick “<span class="caps">PCI</span> Express” in the list). We'll get back to you and send you a list of questions to quickly determinate if we are in the best position to help you.</p></div>
<div class='rss_ps'><p>Don't waste time struggling with PCIe by yourself if you don't have all the competence. We can help you gain the required know-how, we can help you with your design, or we can create the exact interface your design needs. Faster and cheaper !</p></div>
Embedded Softwarehttps://www.alse-fr.com/Embedded-Software-101.html
https://www.alse-fr.com/Embedded-Software-101.html2016-09-27T15:09:22Ztext/htmlenSylvain Lesne
<p>With more and more complex and powerful Processor cores included in recent FPGAs, we have developed a deep competence in Embedded Systems and Embedded Software. It covers from embedded soft cores to <span class="caps">ARM</span> High Performance Systems. And indeed, beyond bare metal, we are clearly focused on Embedded Linux. <br class='autobr' /> Custom board support packages <br class='autobr' />
One of the biggest challenges when developing software targeting a soft core embedded in an <span class="caps">FPGA</span> (such as the Nios <span class="caps">II</span>) or a hardened <span class="caps">ARM</span> application-class (…)</p>
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<a href="https://www.alse-fr.com/-Embedded-Systems-.html" rel="directory">Embedded Systems</a>
<div class='rss_chapo'><p>With more and more complex and powerful Processor cores included in recent FPGAs, we have developed a deep competence in Embedded Systems and Embedded Software. It covers from embedded soft cores to <span class="caps">ARM</span> High Performance Systems. And indeed, beyond bare metal, we are clearly focused on Embedded Linux.</p></div>
<div class='rss_texte'><h2 class="spip"> Custom board support packages </h2>
<p>One of the biggest challenges when developing software targeting a soft core embedded in an <span class="caps"><abbr title="Field Programmable Gate Array. Standard devices that are customized at power up by loading a Programming pattern (aka bitstream) contained in a non-volatile memory. Users can develop completely custom functions and applications with off-the-shelf FPGAs.">FPGA</abbr></span> (such as the <a href="https://www.altera.com/products/processors/overview.html" class='spip_out' rel='external'>Nios <span class="caps">II</span></a>) or a hardened <span class="caps">ARM</span> application-class processor (such as in the <a href="https://www.altera.com/products/soc/overview.html" class='spip_out' rel='external'>SoC-<span class="caps">FPGA</span> components</a>) is taking into account the flexibility of the <span class="caps">FPGA</span>, which allows to implement a completely custom system on chip.</p>
<p><span class="caps">ALSE</span> can develop a board support package (<span class="caps">BSP</span>) tailor-made for any custom system based on those technologies in a matter of days. Such a <span class="caps">BSP</span> is typically composed of a bootloader (U-Boot) and a Linux-based custom distribution, including a software development kit allowing the customer to develop in-house applications on top of this <span class="caps">BSP</span>.</p>
<p>We usually use the <a href="https://buildroot.org/" class='spip_out' rel='external'>Buildroot integration tool</a> to generate our BSPs, as its set of features and ease of use are a good fit for a lot of small to medium-scale embedded Linux projects. However, we're also familiar with the <a href="https://www.yoctoproject.org/" class='spip_out' rel='external'>Yocto Project</a>.</p>
<h2 class="spip"> Custom peripherals and drivers </h2>
<p>As highlighted above, an <span class="caps">FPGA</span>-based system is bound to contain some custom-made peripherals. To properly access those peripherals from a running Linux system, custom drivers are needed. Developing such a driver (including, of course, device tree awareness) is well within <span class="caps">ALSE</span>'s competence range.</p>
<p>One example of a driver we commonly integrate is one which provides an easy and clean way for the applications running on the processor to exchange data with the <span class="caps">FPGA</span>.</p>
<p>The main appeal of our <span class="caps"><abbr title="Gigabit Ethernet Data Exchange Kit. “Hardware Stack” Concept invented by ALSE, GEDEK is a processor-less autonomous block which implements the Ethernet protocols required to establish, maintain, and perform high performance data exchange over standard Ethernet.">GEDEK</abbr></span> <span class="caps"><abbr title="Intellectual Property. A usually complex function developed, tested and sold off-the-shelf to be re-used in customer's designs. Ranges from Processor cores to Memory Controllers to Video processing blocks etc… Some IPs are available from the FPGA vendor (free or at cost) or from 3rd parties.">IP</abbr></span> is to be able to use Ethernet communication without any processor. However it also features a <em class="spip">raw port</em>, allowing a processor to use it as a “standard” <span class="caps"><abbr title="Media Access Controller. The Ethernet (802.3) MAC block is connected to the Media Interface of the Ethernet PHY (the PHYsical transceiver chip) in order to send and receive streams of bytes.">MAC</abbr></span> device, <em class="spip">alongside</em> the normal <span class="caps">GEDEK</span> operation. We've developed a driver allowing this feature.</p>
<h2 class="spip"> Remote update </h2>
<p>There is a common need in embedded systems to be able to update the application software. The usual embedded constraints mean that this is a non-trivial problem.</p>
<p>We implemented a generic solution to this need, with the following features:</p>
<ul class="spip"><li> Robustness against power cuts and failed upgrades;</li><li> Whole-system image updates;
<ul class="spip"><li> In contrast with a package manager, not safe in most embedded systems.</li><li> In order to keep user data intact, overlay filesystem support can easily be added.</li></ul></li><li> Customizable way to deliver the upgrade payload (through a web-server or any custom application);</li><li> Based on open-source components;</li><li> Able to validate signed images with OpenSSL.</li></ul></div>