Memory IP startup pursues FinFET, FDSOI processes

LONDON – SureCore Ltd. (Sheffield, England), a startup semiconductor IP company, has received U.K. government support to help it focus on low-power physical IP for next-generation silicon manufacturing processes. The company is looking to develop memory IP – SRAM initially – for FinFET and FDSOI processes, which are likely to be brought up at silicon foundries in the near future.

Both of these manufacturing processes are significantly different to the bulk planar CMOS process that has prevailed up until this time.

SureCore claims that, using a combination of detailed analysis and advanced statistical modeling, it has designed an SRAM memory structure suitable for integration in advanced logic processes that consumes less than half the power of existing versions. The company also said that its grant support of £250,000 (about $380,000) from the U.K. government's Technology Strategy Board will help it work with major foundries. The company said it will produce a demonstrator chip to help calibrate and showcase its array control and sensing schemes that are key parts of its SRAM technology.

The company is a spin-off from Glasgow University and is working with simulation company Gold Standard Simulations Ltd. (GSS). Professor Asen Asenov, CEO of GSS and James Watt Professor of electrical engineering at Glasgow, has a seat on the board of directors of SureCore.

At the 28-nm node there are only about 100 dopant atoms in the channel and the position of these atoms has a significant effect on operating parameters such as threshold voltage. SureCore said it expects to create physical IP to exploit the disruptive effects of statistical variation in manufacturing processes and provide improved power performance and manufacturability.

The demand for on-chip memory now regularly exceeds 50 percent and is expected to go to 70 percent in coming years and memory is a function that is particularly sensitive to process variability.

"We have proven the technology in simulation but to fully characterize and demonstrate its benefits implementation in silicon is a must. This is a critical next step in demonstrating the value of our IP to our customers," said Paul Wells, CEO of SureCore, in a statement.