We show that a technique previously introduced for subthreshold leakage reduction can be effectively used to reduce gate leakage power dissipation in future CMOS circuits operating in stand-by mode. The technique gave one order of magnitude gate leakage savings with a certain input pattern for the evaluated two-input NAND gate. Also, we make a detailed analysis of mechanisms causing different direct oxide tunneling currents that will contribute to gate leakage power dissipation in future CMOS circuits.

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BibTeX @conference{Drazdziulis2003,author={Drazdziulis, Mindaugas and Larsson-Edefors, Per},title={A Gate Leakage Reduction Strategy for Future CMOS Circuits},booktitle={Proceedings of the 29th European Solid-State Circuits Conference, ESSCIRC 2003, Estoril, 16-18 September 2003},isbn={0-7803-7995-0},pages={317-320},abstract={We show that a technique previously introduced for subthreshold leakage reduction can be effectively used to reduce gate leakage power dissipation in future CMOS circuits operating in stand-by mode. The technique gave one order of magnitude gate leakage savings with a certain input pattern for the evaluated two-input NAND gate. Also, we make a detailed analysis of mechanisms causing different direct oxide tunneling currents that will contribute to gate leakage power dissipation in future CMOS circuits.},year={2003},}

RefWorks RT Conference ProceedingsSR ElectronicID 17602A1 Drazdziulis, MindaugasA1 Larsson-Edefors, PerT1 A Gate Leakage Reduction Strategy for Future CMOS CircuitsYR 2003T2 Proceedings of the 29th European Solid-State Circuits Conference, ESSCIRC 2003, Estoril, 16-18 September 2003SN 0-7803-7995-0SP 317OP 320AB We show that a technique previously introduced for subthreshold leakage reduction can be effectively used to reduce gate leakage power dissipation in future CMOS circuits operating in stand-by mode. The technique gave one order of magnitude gate leakage savings with a certain input pattern for the evaluated two-input NAND gate. Also, we make a detailed analysis of mechanisms causing different direct oxide tunneling currents that will contribute to gate leakage power dissipation in future CMOS circuits.LA engDO 10.1109/ESSCIRC.2003.1257136LK http://dx.doi.org/10.1109/ESSCIRC.2003.1257136OL 30