METHOD OF MANUFACTURING SOLID-STATE IMAGE SENSOR - A method of manufacturing a solid-state image sensor, comprising preparing a semiconductor substrate including a photoelectric converter and an insulating film which includes an opening and is formed in a region above the photoelectric converter, depositing a material having a refractive index higher than the insulating film in the opening, and annealing the material deposited in the opening by irradiating the material with one of light and radiation, wherein a light waveguide which is configured to guide an incident light to the photoelectric converter is formed through the depositing and the annealing.

2012-12-20

20120322197

Solid Group IIIA Particles Formed Via Quenching - Methods and devices are provided for forming thin-films from solid group IIIA-based particles. In one embodiment, a process for forming solid particles is provided. The method includes providing a first suspension of solid and/or liquid particles containing at least one group IIIA element. A material may be added to substantially increase the melting point of at least one set of group IIIA-containing particles in the suspension into higher-melting solid particles comprising an alloy of the group IIIA element and at least a part of the added material. The suspension may be deposited onto a substrate to form a precursor layer on the substrate and the precursor layer is reacted in a suitable atmosphere to form a film.

2012-12-20

20120322198

METHODS FOR SUBLIMATION OF Mg AND INCORPORATION INTO CdTe FILMS TO FORM TERNARY COMPOSITIONS - A method for sublimating a thin film of Magnesium (Mg) on a semiconductor structure for improved efficiency is described. One embodiment includes a method comprised of providing a semiconductor substrate in a vacuum chamber, wherein the substrate comprises a window layer and an absorber layer made of CdTe. The method further includes heating the substrate to a diffusion temperature or greater followed by depositing a Mg film on the absorber layer using a sublimation process, wherein at least a portion of the Mg forms a Cd

2012-12-20

20120322199

PATTERNED DOPING FOR POLYSILICON EMITTER SOLAR CELLS - An improved method of manufacturing a polysilicon solar cell is disclosed. To create the polysilicon layer, which has p-type and n-type regions, the layer is grown in the presence of one type of dopant. After the doped polysilicon layer has been created, ions of the opposite dopant conductivity are selectively implanted into portions of the polysilicon layer. This selective implant may be performed using a shadow mask.

2012-12-20

20120322200

NON-LITHOGRAPHIC METHOD OF PATTERNING CONTACTS FOR A PHOTOVOLTAIC DEVICE - A dielectric material layer is formed on a front surface of a photovoltaic device. A patterned PMMA-type-material-including layer is formed on the dielectric material layer, and the pattern is transferred into the top portion of the photovoltaic device to form trenches in which contact structures can be formed. In one embodiment, a blanket PMMA-type-material-including layer is deposited on the dielectric material layer, and is patterned by laser ablation that removes ablated portions of PMMA-type-material. The PMMA-type-material-including layer may also include a dye to enhance absorption of the laser beam. In another embodiment, a blanket PMMA-type-material-including layer may be deposited on the dielectric material layer and mechanically patterned to form channels therein. In yet another embodiment, a patterned PMMA-type-material-including layer is stamped on top of the dielectric material layer.

2012-12-20

20120322201

STACKED SEMICONDUCTOR PACKAGE AND STACKING METHOD THEREOF - A stacked semiconductor package technique applicable to semiconductor chips having pins short enough that the semiconductor chips cannot be directly bonded together is provided. A printed circuit board (PCB) is inserted into a space between pins of an upper semiconductor chip and the exterior of bodies of stacked semiconductor chips. The PCB includes a plurality of conductive patterns at locations corresponding to the respective pins. The respective conductive patterns and the corresponding respective pins of the upper and lower semiconductor chips are bonded together. The PCB includes a plurality of recess patterns on one side, the recess patterns having the same pitch as the pins of the semiconductor chips. The PCB is disposed across the pins of the lower semiconductor chip, and thereby easily arranged with the stacked semiconductor chips.

2012-12-20

20120322202

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device includes a supporting board, a first semiconductor element mounted on a main surface of the supporting board; and an electronic component provided between the supporting board and the first semiconductor element; wherein the supporting board includes a concave part formed in a direction separated from the first semiconductor element; and at least a part of the electronic component is accommodated in the concave part.

2012-12-20

20120322203

METHOD TO CONSTRUCT SYSTEMS - A method to construct first and second configurable systems including: providing a first configurable system including a first die and a second die, where the first die is diced from a first wafer and the second die is diced from a second wafer and the first die is connected to the second die using at least one through-silicon-via (TSV); providing a second configurable system including a third die and a fourth die, where the third die is diced from a third wafer and the fourth die is diced from a fourth wafer and the third die is connected to the fourth die using at least one through-silicon-via (TSV); where processing the first wafer and the third wafer utilizes a majority of masks that are substantially same; and where the first die is larger than the third die.

2012-12-20

20120322204

SEMICONDUCTOR ELEMENT AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a semiconductor device includes preparing a semiconductor element including a main surface over which a wiring layer is formed, forming a seed layer over the main surface, forming a resist layer over the main surface such that the resist layer covers the seed layer, removing a part of the resist layer by exposing and developing the resist layer, in which a part of the wiring layer is exposed from the removed part of the resist layer, forming a plurality of conductive posts electrically connected to the wiring layer at the removed part of the resist layer, forming a solder layer at each top of the plurality of conductive posts, removing a residual resist layer over the main surface, removing an area other than an area which overlaps with the seed layer, and melting the solder layer and forming a surface shape.

2012-12-20

20120322205

METHOD FOR MANUFACTURING WIRING SUBSTRATE - A method for manufacturing a wiring substrate includes forming a first pad and a second pad on one side of a substrate, plating a surface of the second pad to form a bonding pad used for a wire-bonded connection, covering a surface of the first pad with an adhesive layer, adhering solder powder to the adhesive layer, applying flux containing halogen to the substrate, and melting the solder powder and covering the first pad with a solder to form a connection pad used for a flip-chip-connection. The flux has a halogen concentration of less than or equal to 0.15 wt %.

2012-12-20

20120322206

METHOD FOR WAFER LEVEL PACKAGING OF ELECTRONIC DEVICES - A method of packaging a semiconductor device that incorporates the formation of cavities about electronic devices during the packaging process. In one example, the device package includes a first substrate having a first recess formed therein, a second substrate having a second recess formed therein, and an electronic device mounted in the first recess. The first and second substrates are joined together with the first and second recesses substantially overlying one another so as to form a cavity around the electronic device.

2012-12-20

20120322207

SEMICONDUCTOR PACKAGE WITH ADHESIVE MATERIAL PRE-PRINTED ON THE LEAD FRAME AND CHIP, AND ITS MANUFACTURING METHOD - This invention discloses a semiconductor package with adhesive material pre-printed on the lead frame and chip, and the manufacturing method. The adhesive material is applied onto the chip carrier and the pin of the lead frame and also on the front electrode of the semiconductor chip via pre-printing. The back of the semiconductor chip is adhered on the chip carrier, and the front electrode of the semiconductor chip and the pin are connected respectively with a metal connector. The size, shape and thickness of the adhesive material are applied according to different application requirements according to size and shapes of the contact zone of the semiconductor chip and the metal connector. Particularly, the adhesive zones are formed by pre-printing the adhesive material thus significantly enhance the quality and performance of semiconductor products, and improves the productivity.

2012-12-20

20120322208

ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - A method for manufacturing an electronic device includes forming a resin film over a wafer, the wafer including a plurality of elements formed therein, each of the elements including a functional unit, patterning the resin film to form a plurality of frame members, each of the frame members being provided on each of the elements and surrounding the functional unit, dividing the wafer into the elements, and providing an encapsulation.

2012-12-20

20120322209

SEMICONDUCTOR DEVICE WITH HEAT SPREADER - A BGA type semiconductor device includes: a substrate having wirings and electrodes; a semiconductor element disposed on the substrate, having a rectangular plan shape, and a plurality of electrodes disposed along each side of the semiconductor element; a plurality of wires connecting the electrodes on the semiconductor element with the electrodes on the substrate; a heat dissipation member disposed on the substrate, covering the semiconductor element, and having openings formed in areas facing apex portions of the plurality of wires connected to the electrodes formed along each side of the semiconductor element; and a sealing resin member for covering and sealing the semiconductor element and heat dissipation member.

2012-12-20

20120322210

SEMICONDUCTOR DEVICE AND MANUFACTURING OF THE SEMICONDUCTOR DEVICE - A semiconductor device. In one embodiment the device includes a carrier. A first material is deposited on the carrier. The first material has an elastic modulus of less than 100 MPa. A semiconductor chip is placed over the first material. A second material is deposited on the semiconductor chip, the second material being electrically insulating. A metal layer is placed over the second material.

2012-12-20

20120322211

DIE BACKSIDE STANDOFF STRUCTURES FOR SEMICONDUCTOR DEVICES - Standoff structures that can be used on the die backside of semiconductor devices and methods for making the same are described. The devices contain a silicon substrate with an integrated circuit on the front side of the substrate and a backmetal layer on the backside of the substrate. Standoff structures made of Cu of Ni are formed on the backmetal layer and are embedded in a Sn-containing layer that covers the backmetal layer and the standoff structures. The standoff structures can be isolated from each other so that they are not connected and can also be configured to substantially mirror indentations in the leadframe that is attached to the Sn-containing layer. Other embodiments are described.

2012-12-20

20120322212

WIRELESS CHIP AND MANUFACTURING METHOD THEREOF - It is an object of the present invention to reduce the cost of a wireless chip, further, to reduce the cost of a wireless chip by enabling the mass production of a wireless chip, and furthermore, to provide a downsized and lightweight wireless chip. A wireless chip in which a thin film integrated circuit peeled from a glass substrate or a quartz substrate is formed between a first base material and a second base material is provided according to the invention. As compared with a wireless chip formed from a silicon substrate, the wireless chip according to the invention realizes downsizing, thinness, and lightweight. The thin film integrated circuit included in the wireless chip according to the invention at least has an n-type thin film transistor having an LDD (Lightly Doped Drain) structure, a p-type thin film transistor having a single drain structure, and a conductive layer functioning as an antenna.

2012-12-20

20120322213

SUBSTRATE FOR LIQUID CRYSTAL DISPLAY DEVICE INCLUDING PERIPHERAL LINES HAVING OPENINGS AND FABRICATING METHOD THEREOF - A liquid crystal display device includes a substrate having a display region and a non-display region. In the display region, the gate line and a data line cross to define a pixel region and a thin film transistor is disposed at the crossing portion of the gate and data lines. The thin film transistor includes a gate electrode and source and drain electrodes. A peripheral line having a plurality of openings is disposed in the non-display region. The openings are slits, rectangles, circles, or triangles. The openings relieve plasma during dry-etching of the peripheral line. A pixel electrode is connected to the drain electrode in the pixel region.

2012-12-20

20120322214

METHOD AND STRUCTURE FOR ESTABLISHING CONTACTS IN THIN FILM TRANSISTOR DEVICES - The roughness and structural height of printed metal lines is used to pin a fluid. This fluid deposits a top contact material which is connected to the bottom printed contacts through pinholes in the hydrophobic polymer layer. This results in a sandwich-like contact structure achieved in a self-aligned deposition process and having improved source-drain contact for all-additive printed circuits. In one form, the present technique is used for thin film transistor applications, but it may be applied to electrodes in general.

2012-12-20

20120322215

COMMUNICATION - An electronic device includes a conductive channel defining a crystal structure and having a length and a thickness t

2012-12-20

20120322216

METHOD FOR REDUCING POLY-DEPLETION IN DUAL GATE CMOS FABRICATION PROCESS - Disclosed is a method for reducing poly-depletion in a dual gate CMOS fabrication process. The method reduces the poly-depletion in a dual gate CMOS fabrication process by increasing the doping efficiency in a gate polysilicon film. In order to increase the doping efficiency, the method employs the following four technical principles. First, the doping efficiency is increased when the dose of N+ ion implantation is increased. Second, the doping efficiency is increased when the thickness of N+ polysilicon is reduced. Third, the increase of depletion caused by the reduction of the channel width is inhibited when the EFH is adjusted to be less than 0. Fourth, the overall doping efficiency is increased when each step of polysilicon deposition and ion implantation is divided into multiple steps.

2012-12-20

20120322217

FABRICATION METHOD OF TRENCHED POWER SEMICONDUCTOR DEVICE WITH SOURCE TRENCH - A fabrication method of a trenched power semiconductor device with source trench is provided. Firstly, at least two gate trenches are formed in a base. Then, a dielectric layer and a polysilicon structure are sequentially formed in the gate trench. Afterward, at least a source trench is formed between the neighboring gate trenches. Next, the dielectric layer and a second polysilicon structure are sequentially formed in the source trench. The second polysilicon structure is located in a lower portion of the source trench. Then, the exposed portion of the dielectric layer in the source trench is removed to expose a source region and a body region. Finally, a conductive structure is filled into the source trench to electrically connect the second polysilicon structure, the body region, and the source region.

2012-12-20

20120322218

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes the following steps. Firstly, a dummy gate structure having a dummy gate electrode layer is provided. Then, the dummy gate electrode layer is removed to form an opening in the dummy gate structure, thereby exposing an underlying layer beneath the dummy gate electrode layer. Then, an ammonium hydroxide treatment process is performed to treat the dummy gate structure. Afterwards, a metal material is filled into the opening.

METHOD OF PROCESSING MIM CAPACITORS TO REDUCE LEAKAGE CURRENT - A method for processing dielectric materials and electrodes to decrease leakage current is disclosed. The method includes a post dielectric anneal treatment in an oxidizing atmosphere to reduce the concentration of oxygen vacancies in the dielectric material. The method further includes a post metallization anneal treatment in an oxidizing atmosphere to reduce the concentration of interface states at the electrode/dielectric interface and to further reduce the concentration of oxygen vacancies in the dielectric material.

2012-12-20

20120322221

MOLYBDENUM OXIDE TOP ELECTRODE FOR DRAM CAPACITORS - A metal oxide bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a desired composition and crystal structure. An example is crystalline MoO

METHODS OF MANUFACTURING PHASE-CHANGE MEMORY DEVICES - A phase-change memory device includes a word line on a substrate and a phase-change memory cell on the word line and comprising a phase-change material pattern. The device also includes a non-uniform conductivity layer pattern comprising a conductive region on the phase-change material pattern and a non-conductive region contiguous therewith. The device further includes a bit line on the conductive region of the non-uniform conductivity layer pattern. In some embodiments, the phase-change memory cell may further include a diode on the word line, a heating electrode on the diode and wherein the phase-change material layer is disposed on the heating electrode. An ohmic contact layer and a contact plug may be disposed between the diode and the heating electrode.

2012-12-20

20120322224

METHOD OF FABRICATING SEMICONDUCTOR DEVICE - In a method of fabricating a semiconductor device, a target layer and a first material layer are sequentially formed on a substrate. A plurality of second material layer patterns are formed on the first material layer, the second material layer patterns extending in a first horizontal direction. A plurality of hardmask patterns extending in a second horizontal direction are formed on the plurality of second material layer patterns and the first material layer, wherein the second horizontal direction is different from the first horizontal direction. A first material layer pattern is formed by etching the first material layer using the plurality of hardmask patterns and the plurality of second material layer patterns as etch masks. A target layer pattern with a plurality of holes is formed by etching the target layer using the first material layer pattern as an etch mask.

2012-12-20

20120322225

Method of Forming Conductive Contacts on a Semiconductor Device with Embedded Memory and the Resulting Device - A method is disclosed that includes forming a conductive logic contact in a logic area of a semiconductor device, forming a bit line contact and a capacitor contact in a memory array of the semiconductor device, and performing at least one first common process to form a first metallization layer comprising a first conductive line in the logic area that is conductively coupled to the conductive logic contact and a bit line in the memory array that is conductively coupled to the bit line contact. The method further includes performing at least one second common process to form a second metallization layer comprising a first conductive structure conductively coupled to the first conductive line in the logic area and a second conductive structure in the memory array that that is conductively coupled to the capacitor contact.

2012-12-20

20120322226

SEMICONDUCTOR DEVICE PRODUCTION METHOD - A semiconductor device production method includes: treating a wafer which contains a silicon substrate with dilute hydrofluoric acid in a bath; introducing water into the bath while discharging the dilute hydrofluoric acid from the bath; and introducing H

2012-12-20

20120322227

METHOD FOR CONTROLLED LAYER TRANSFER - A method of controlled layer transfer is provided. The method includes providing a stressor layer to a base substrate. The stressor layer has a stressor layer portion located atop an upper surface of the base substrate and a self-pinning stressor layer portion located adjacent each sidewall edge of the base substrate. A spalling inhibitor is then applied atop the stressor layer portion of the base substrate, and thereafter the self-pinning stressor layer portion of the stressor layer is decoupled from the stressor layer portion. A portion of the base substrate that is located beneath the stressor layer portion is then spalled from the original base substrate. The spalling includes displacing the spalling inhibitor from atop the stressor layer portion. After spalling, the stressor layer portion is removed from atop a spalled portion of the base substrate.

2012-12-20

20120322228

METHOD FOR FORMING SOI SUBSTRATE AND APPARATUS FOR FORMING THE SAME - A bond substrate is attached with an incline toward the setting surface of a base substrate. Accordingly, an attachment starting portion can be limited. Further, the bond substrate is provided so that part of the bond substrate extends beyond a support base and the part is closest to the base substrate. Because of this, part of the bond substrate is separated from the support base with the use of an end portion of the support base as a fulcrum point because the support base is not provided below the contact portion, and attachment sequentially proceeds from a portion which gets close to the base substrate; thus, stable attachment can be performed without an air layer remaining at the interface between the bond substrate and the base substrate.

2012-12-20

20120322229

METHOD FOR BONDING TWO SUBSTRATES - The invention relates to a method for bonding two substrates by applying an activation treatment to at least one of the substrates, and performing the contacting step of the two substrates under partial vacuum. Due to the combination of the two steps, it is possible to carry out the bonding and obtain high bonding energy with a reduced number of bonding voids. The invention is in particular applicable to a substrate of processed or at least partially processed devices.

2012-12-20

20120322230

METHOD FOR FORMING TWO DEVICE WAFERS FROM A SINGLE BASE SUBSTRATE UTILIZING A CONTROLLED SPALLING PROCESS - The present disclosure provides a method for forming two device wafers starting from a single base substrate. The method includes first providing a structure which includes a base substrate with device layers located on, or within, a topmost surface and a bottommost surface of the base substrate. The base substrate may have double side polished surfaces. The structure including the device layers is spalled in a region within the base substrate that is between the device layers. The spalling provides a first device wafer including a portion of the base substrate and one of the device layers, and a second device wafer including another portion of the base substrate and the other of the device layer.

2012-12-20

20120322231

SEMICONDUCTOR WAFER PROCESSING METHOD - A semiconductor wafer has a device area where a plurality of semiconductor devices are respectively formed in a plurality of regions partitioned by a plurality of crossing division lines formed on the front side of the semiconductor wafer and a peripheral area surrounding the device area. The back side of the semiconductor wafer corresponding to the device area is ground to thereby form a circular recess and an annular projection surrounding the circular recess. In a chip stacked wafer forming step, a plurality of semiconductor device chips are provided on the bottom surface of the circular recess of the semiconductor wafer at the positions respectively corresponding to the semiconductor devices of the semiconductor wafer. The chip stacked wafer is ground to reduce the thickness of each semiconductor device chip to a finished thickness, and a through electrode is formed in each semiconductor device of the semiconductor wafer.

2012-12-20

20120322232

MULTI-STEP AND ASYMMETRICALLY SHAPED LASER BEAM SCRIBING - Methods of dicing substrates by both laser scribing and plasma etching. A method includes laser ablating material layers, the ablating leading with a first irradiance and following with a second irradiance, different than the first. An asymmetrically shaped beam having an asymmetrical spatial profile along the direction of travel, multiple passes of a beam adjusted to have different irradiance levels, and multiple laser beams having various irradiance levels may be utilized to ablate at least a mask with the first irradiance and expose the substrate with the second irradiance.

2012-12-20

20120322233

WATER SOLUBLE MASK FOR SUBSTRATE DICING BY LASER AND PLASMA ETCH - Methods of dicing substrates having a plurality of ICs. A method includes forming a mask comprising a water soluble material layer over the semiconductor substrate. The mask is patterned with a femtosecond laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. The substrate is then etched through the gaps in the patterned mask to singulate the IC and the water soluble material layer washed off.

2012-12-20

20120322234

IN-SITU DEPOSITED MASK LAYER FOR DEVICE SINGULATION BY LASER SCRIBING AND PLASMA ETCH - Methods of dicing substrates by both laser scribing and plasma etching. A method includes forming an in-situ mask with a plasma etch chamber by accumulating a thickness of plasma deposited polymer to protect IC bump surfaces from a subsequent plasma etch. Second mask materials, such as a water soluble mask material may be utilized along with the plasma deposited polymer. At least some portion of the mask is patterned with a femtosecond laser scribing process to provide a patterned mask with trenches. The patterning exposing regions of the substrate between the ICs in which the substrate is plasma etched to singulate the IC and the water soluble material layer washed off.

2012-12-20

20120322235

WAFER DICING USING HYBRID GALVANIC LASER SCRIBING PROCESS WITH PLASMA ETCH - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a galvanic laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.

2012-12-20

20120322236

WAFER DICING USING PULSE TRAIN LASER WITH MULTIPLE-PULSE BURSTS AND PLASMA ETCH - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask is composed of a layer covering and protecting the integrated circuits. The mask is patterned with a pulse train laser scribing process using multiple-pulse bursts to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits.

2012-12-20

20120322237

LASER AND PLASMA ETCH WAFER DICING USING PHYSICALLY-REMOVABLE MASK - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The mask covers and protects the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to form singulated integrated circuits. The patterned mask is then separated from the singulated integrated circuits.

2012-12-20

20120322238

LASER AND PLASMA ETCH WAFER DICING USING WATER-SOLUBLE DIE ATTACH FILM - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer. The semiconductor wafer is disposed on a water-soluble die attach film. The mask covers and protects the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to form singulated integrated circuits. The water-soluble die attach film is then patterned with an aqueous solution.

2012-12-20

20120322239

HYBRID LASER AND PLASMA ETCH WAFER DICING USING SUBSTRATE CARRIER - Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The semiconductor wafer is supported by a substrate carrier. The mask is then patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits while supported by the substrate carrier.

2012-12-20

20120322240

DAMAGE ISOLATION BY SHAPED BEAM DELIVERY IN LASER SCRIBING PROCESS - Methods and apparatuses for dicing substrates by both laser scribing and plasma etching. A method includes laser ablating material layers, the ablating by a laser beam with a centrally peaked spatial power profile to form an ablated trench in the substrate below thin film device layers which is positively sloped. In an embodiment, a femtosecond laser forms a positively sloped ablation profile which facilitates vertically-oriented propagation of microcracks in the substrate at the ablated trench bottom. With minimal lateral runout of microcracks, a subsequent anisotropic plasma etch removes the microcracks for a cleanly singulated chip with good reliability.

2012-12-20

20120322241

MULTI-LAYER MASK FOR SUBSTRATE DICING BY LASER AND PLASMA ETCH - Methods of dicing substrates having a plurality of ICs. A method includes forming a multi-layered mask comprising a first mask material layer soluble in a solvent over the semiconductor substrate and a second mask material layer, insoluble in the solvent, over the first mask material layer. The multi-layered mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the substrate between the ICs. The substrate is then plasma etched through the gaps in the patterned mask to singulate the IC with the second mask material layer protecting the first mask material layer for at least a portion of the plasma etch. The soluble material layer is dissolved subsequent to singulation to remove the multi-layered mask.

2012-12-20

20120322242

MULTI-STEP AND ASYMMETRICALLY SHAPED LASER BEAM SCRIBING - Methods of dicing substrates by both laser scribing and plasma etching. A method includes laser ablating material layers, the ablating leading with a first irradiance and following with a second irradiance, lower than the first. Multiple passes of a beam adjusted to have different fluence level or multiple laser beams having various fluence levels may be utilized to ablate mask and IC layers to expose a substrate with the first fluence level and then clean off redeposited materials from the trench bottom with the second fluence level. A laser scribe apparatus employing a beam splitter may provide first and second beams of different fluence from a single laser.

2012-12-20

20120322243

APPARATUS AND METHOD FOR ELECTROCHEMICAL PROCESSING OF THIN FILMS ON RESISTIVE SUBSTRATES - An electrochemical process comprising: providing a 125 mm or larger semiconductor wafer in electrical contact with a conducting surface, wherein at least a portion of the semiconductor wafer is in contact with an electrolytic solution, said semiconductor wafer functioning as a first electrode; providing a second electrode in the electrolytic solution, the first and second electrode connected to opposite ends of an electric power source; and irradiating a surface of the semiconductor wafer with a light source as an electric current is applied across the first and the second electrodes. The invention is also directed to an apparatus including a light source and electrochemical components to conduct the electrochemical process.

2012-12-20

20120322244

METHOD FOR CONTROLLED REMOVAL OF A SEMICONDUCTOR DEVICE LAYER FROM A BASE SUBSTRATE - A method of removing a semiconductor device layer from a base substrate is provided that includes providing a crack propagation layer on an upper surface of a base substrate. A semiconductor device layer including at least one semiconductor device is formed on the crack propagation layer. Next, end portions of the crack propagation layer are etched to initiate a crack in the crack propagation layer. The etched crack propagation layer is then cleaved to provide a cleaved crack propagation layer portion to a surface of the semiconductor device layer and another cleaved crack propagation layer portion to the upper surface of the base substrate. The cleaved crack propagation layer portion is removed from the surface of the semiconductor device layer and the another cleaved crack propagation layer portion is removed from the upper surface of the base substrate.

FABRICATION METHODS OF INTEGRATED SEMICONDUCTOR STRUCTURE - A method for manufacturing the integrated circuit device including, providing a substrate having a first region and a second region. Forming a dielectric layer over the substrate in the first region and the second region. Forming a sacrificial gate layer over the dielectric layer. Patterning the sacrificial gate layer and the dielectric layer to form gate stacks in the first and second regions. Forming an ILD layer within the gate stacks in the first and second regions. Removing the sacrificial gate layer in the first and second regions. Forming a protector over the dielectric layer in the first region; and thereafter removing the dielectric layer in the second region.

2012-12-20

20120322247

METHOD FOR FABRICATING HIGH VOLTAGE TRANSISTOR - A method for fabricating a high voltage transistor includes the following steps. Firstly, a substrate is provided. A first sacrificial oxide layer and a hard mask layer are sequentially formed over the substrate. The hard mask layer is removed, thereby exposing the first sacrificial oxide layer. Then, a second sacrificial oxide layer is formed on the first sacrificial oxide layer. Afterwards, an ion-implanting process is performed to introduce a dopant into the substrate through the second sacrificial oxide layer and the first sacrificial oxide layer, thereby producing a high voltage first-type field region of the high voltage transistor.

2012-12-20

20120322248

ION IMPLANTATION APPARATUS AND ION IMPLANTATION METHOD - An ion implantation method in which an ion beam is scanned in a beam scanning direction and a wafer is mechanically scanned in a direction perpendicular to the beam scanning direction, includes setting a wafer rotation angle with respect to the ion beam so as to be varied, wherein a set angle of the wafer rotation angle is changed in a stepwise manner so as to implant ions into the wafer at each set angle, and wherein a wafer scanning region length is set to be varied, and, at the same time, a beam scanning speed of the ion beam is changed, in ion implantation at each set angle in a plurality of ion implantation operations during one rotation of the wafer, such that the ions are implanted into the wafer and dose amount non-uniformity in a wafer surface in other semiconductor manufacturing processes is corrected.

2012-12-20

20120322249

MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE - In a manufacturing method of a semiconductor structure, a substrate having a front surface and a back surface is provided. The front surface has a device layer thereon and conductive plugs electrically connected to the device layer. A thinning process is performed on the back surface of the substrate, such that the back surface of the substrate and surfaces of the conductive plugs have a distance therebetween. Holes are formed in the substrate from the back surface to the conductive plugs, so as to form a porous film. An oxidization process is performed, such that the porous film correspondingly is reacted to form an oxide material layer. A polishing process is performed on the oxide material layer to expose the surfaces of the conductive plugs.

2012-12-20

20120322250

N-Metal Film Deposition With Initiation Layer - Provided are methods of depositing N-Metals onto a substrate. Some methods comprise providing an initiation layer of TaM or TiM layer on a substrate, wherein M is selected from aluminum, carbon, noble metals, gallium, silicon, germanium and combinations thereof; and exposing the substrate having the TaM or TiM layer to a treatment process comprising soaking the surface of the substrate with a reducing agent to provided a treated initiation layer.

2012-12-20

20120322251

Borderless Contacts For Semiconductor Devices - In one exemplary embodiment of the invention, a method (e.g., to fabricate a semiconductor device having a borderless contact) including: forming a first gate structure on a substrate; depositing an interlevel dielectric over the first gate structure; planarizing the interlevel dielectric to expose a top surface of the first gate structure; removing at least a portion of the first gate structure; forming a second gate structure in place of the first gate structure; forming a contact area for the borderless contact by removing a portion of the interlevel dielectric; and forming the borderless contact by filling the contact area with a metal-containing material.

2012-12-20

20120322252

SEMICONDUCTOR MEMORY DEVICE COMPRISING THREE-DIMENSIONAL MEMORY CELL ARRAY - A semiconductor memory device includes a substantially planar substrate; a memory string vertical to the substrate, the memory string comprising a plurality of storage cells; and a plurality of elongated word lines, each word line including a first portion substantially parallel to the substrate and connected to the memory string and a second portion substantially inclined relative to the substrate and extending above the substrate, wherein a first group of the plurality of word lines are electrically connected to first conductive lines disposed at a first side of the memory string, and a second group of the plurality of word lines are electrically connected to second conductive lines disposed at a second side of the memory string.

2012-12-20

20120322253

METHOD FOR REDUCING INTERFACIAL LAYER THICKNESS FOR HIGH-K AND METAL GATE STACK - This description relates to a method including forming an interfacial layer over a semiconductor substrate. The method further includes etching back the interfacial layer. The method further includes performing an ultraviolet (UV) curing process on the interfacial layer. The UV curing process includes supplying a gas flow rate ranging from 10 standard cubic centimeters per minute (sccm) to 5 standard liters per minute (slm), wherein the gas comprises inert gas, and heating the interfacial layer at a temperature less than or equal to 700° C. The method further includes depositing a high-k dielectric material over the interfacial layer.

2012-12-20

20120322254

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - A method of manufacturing a semiconductor device of the present invention includes a first step of forming a metal oxide film containing at least one or more kinds of elements selected from the group consisting of hafnium, yttrium, lanthanum, aluminium, zirconium, strontium, titanium, barium, tantalum, niobium, on a substrate having a metal thin film formed on the surface, at a first temperature allowing no oxidization of the metal thin film to occur, and allowing the metal oxide film to be set in an amorphous state; and a second step of forming a metal oxide film containing at least one or more kinds of elements selected from the group consisting of hafnium, yttrium, lanthanum, aluminium, zirconium, strontium, titanium, barium, tantalum, niobium on the metal oxide film formed in the first step, up to a target film thickness, at a second temperature exceeding the first temperature.

2012-12-20

20120322255

Metal Bump Formation - A system and method for forming metal bumps is provided. An embodiment comprises attaching conductive material to a carrier medium and then contacting the conductive material to conductive regions of a substrate. Portions of the conductive material are then bonded to the conductive regions using a bonding process to form conductive caps on the conductive regions, and residual conductive material and the carrier medium are removed. A reflow process is used to reflow the conductive caps into conductive bumps.

2012-12-20

20120322256

Manufacturing Method of a High Performance Metal-Oxide-Metal - The manufacturing method of the high performance metal-oxide-metal according to the present invention resolves the problems of implementing high capacitance in the metal-oxide-metal region by the steps of filling with a low-k material both in the metal-oxide-metal region and the metal interconnection region, utilizing performing selective photolithography and etching of the first dielectric layer to define metal-oxide-metal (MOM for short) region, and fulfilling the MOM region with high dielectric constant (high-k) material to realize a high performance MOM capacitor. Using the present method, high-k material and low-k material within the same film layer are realized. High-k material region is used as MOM to achieve high capacitor c, thereby reducing the area used by chips and further improving the electrics performance.

2012-12-20

20120322257

METHOD OF FILLING A DEEP ETCH FEATURE - A method for anisotropically plasma etching a semiconductor wafer is disclosed. The method comprises supporting a wafer in an environment operative to form a plasma, such as a plasma reactor, and providing an etching mixture to the environment. The etching mixture comprises at least one etch component, at least one passivation component, and at least one passivation material removal component.

2012-12-20

20120322258

MODULATED DEPOSITION PROCESS FOR STRESS CONTROL IN THICK TiN FILMS - A multi-layer TiN film with reduced tensile stress and discontinuous grain structure, and a method of fabricating the TiN film are disclosed. The TiN layers are formed by PVD or IMP in a nitrogen plasma. Tensile stress in a center layer of the film is reduced by increasing N

2012-12-20

20120322259

DEFECT FREE DEEP TRENCH METHOD FOR SEMICONDUCTOR CHIP - A method for forming large substantially defect-free void areas on a semiconductor integrated circuit chip includes processing the chip through the passivation level processing operations then forming one or more openings in a designated blank area of the integrated circuit chip in a separate dedicated etching operation. The one or more openings may constitute 5-10% or more of the total area of the semiconductor chip. The void areas are deep trench openings that extend through the passivation layer and through all of the other material layers in the blank area exposing the substrate surface in one embodiment and through all material layers except for a field oxide layer formed directly on the substrate in another embodiment.

2012-12-20

20120322260

THROUGH-SILICON VIA FORMING METHOD - A through-silicon via forming method includes the following steps. Firstly, a semiconductor substrate is provided. Then, a through-silicon via conductor is formed in the semiconductor substrate, and a topside of the through-silicon via conductor is allowed to be at the same level as a surface of the semiconductor substrate. Afterwards, a portion of the through-silicon via conductor is removed, and the topside of the through-silicon via conductor is allowed to be at a level lower than the surface of the semiconductor substrate, so that a recess is formed over the through-silicon via conductor.

2012-12-20

20120322261

Methods for Via Structure with Improved Reliability - Methods for forming a via structure are provided. The method includes depositing a first-layer conductive line over a semiconductor substrate, forming a dielectric layer over the first-layer conductive line, forming a via opening in the dielectric layer and exposing the first-layer conductive line in the via opening, forming a recess portion in the first-layer conductive line, and filling the via opening to form a via extending through the dielectric layer to the first-layer conductive line. The via has a substantially tapered profile and substantially extends into the recess in the first-layer conductive line.

2012-12-20

20120322262

N-Metal Film Deposition With Initiation Layer - Provided are methods of depositing N-Metals onto a substrate. Methods include first depositing an initiation layer. The initiation layer may comprise or consist of cobalt, tantalum, nickel, titanium or TaAlC. These initiation layers can be used to deposit TaC

2012-12-20

20120322263

METHODS OF ETCHING SINGLE CRYSTAL SILICON - A single crystal silicon etching method includes providing a single crystal silicon substrate having at least one trench therein. The substrate is exposed to a buffered fluoride etch solution which undercuts the silicon to provide lateral shelves when patterned in the <100> direction. The resulting structure includes an undercut feature when patterned in the <100> direction.

2012-12-20

20120322264

AQUEOUS POLISHING AGENT AND GRAFT COPOLYMERS AND THEIR USE IN A PROCESS FOR POLISHING PATTERNED AND UNSTRUCTURED METAL SURFACES - An aqueous polishing agent, comprising, as the abrasive, at least one kind of polymer particles (A) finely dispersed in the aqueous phase and having at their surface a plurality of at least one kind of functional groups (al) capable of interacting with the metals and/or the metal oxides on top of the surfaces to be polished and forming complexes with the said metals and metal cations, the said polymer particles (A) being preparable by the emulsion or suspension polymerization of at least one monomer containing at least one radically polymerizable double bond in the presence of at least one oligomer or polymer containing a plurality of functional groups (a1); graft copolymers preparable by the emulsion or suspension polymerization of at least one monomer containing at least one radically polymerizable double bond in the presence of at least one oligomeric or polymeric aminotriazine-polyamine condensate; and a process for the chemical and mechanical polishing of patterned and unstructured metal surfaces making use of the said aqueous polishing agent.

2012-12-20

20120322265

POLY OPENING POLISH PROCESS - A poly opening polish process includes the following steps. A semi-finished semiconductor component is provided. The semi-finished semiconductor component includes a substrate, a gate disposed on the substrate, and a dielectric layer disposed on the substrate and covering the gate. A first polishing process is applied onto the dielectric layer. A second polishing process is applied to the gate. The second polishing process utilizes a wetting solution including a water soluble polymer surfactant, an alkaline compound and water. The poly opening polish process can effectively remove an oxide residue formed in the chemical mechanical polish, thereby improving the performance of the integrated circuit and reducing the production cost of the integrated circuit.

2012-12-20

20120322266

Methods of Forming Semiconductor Constructions - The invention includes methods in which silicon is removed from titanium-containing container structures with an etching composition having a phosphorus-and-oxygen-containing compound therein. The etching composition can, for example, include one or both of ammonium hydroxide and tetra-methyl ammonium hydroxide. The invention also includes methods in which titanium-containing whiskers are removed from between titanium-containing capacitor electrodes. Such removal can be, for example, accomplished with an etch utilizing one or more of hydrofluoric acid, ammonium fluoride, nitric acid and hydrogen peroxide.

2012-12-20

20120322267

METHOD OF PATTERNING A SUBSTRATE - In various embodiments, a method of patterning a substrate may include: forming an auxiliary layer on or above a substrate and forming a plasma etch mask layer on or above the auxiliary layer, wherein the auxiliary layer is configured such that it may be removed from the substrate more easily than the plasma etch mask layer; patterning the plasma etch mask layer and the auxiliary layer such that at least a portion of the substrate is exposed; patterning the substrate by means of a plasma etch process using the patterned plasma etch mask layer as a plasma etch mask.

2012-12-20

20120322268

METHOD OF FORMING A PATTERN - A method of forming a pattern includes forming a mask pattern on a substrate; etching the substrate by deep reactive ion etching (DRIE) and by using the mask pattern as an etch mask; partially removing the mask pattern to expose a portion of an upper surface of the substrate; and etching the exposed portion of the upper surface of the substrate. In the method, when a pattern is formed by DRIE, an upper portion of the pattern does not protrude or scarcely protrudes, and scallops of a sidewall of the pattern are smooth, and thus a conformal material layer may be easily formed on a surface of the pattern.

2012-12-20

20120322269

Methods of Fabricating Substrates - A method of fabricating a substrate includes forming first and second spaced features over a substrate. The first spaced features have elevationally outermost regions which are different in composition from elevationally outermost regions of the second spaced features. The first and second spaced features alternate with one another. Every other first feature is removed from the substrate and pairs of immediately adjacent second features are formed which alternate with individual of remaining of the first features. After such act of removing, the substrate is processed through a mask pattern comprising the pairs of immediately adjacent second features which alternate with individual of the remaining of the first features. Other embodiments are disclosed.

2012-12-20

20120322270

POWERED GRID FOR PLASMA CHAMBER - A plasma processing chamber and methods for operating the chamber are provided. An exemplary chamber includes an electrostatic chuck for receiving a substrate and a dielectric window connected to a top portion of the chamber. An inner side of dielectric window faces a plasma processing region that is above the electrostatic chuck and an outer side of the dielectric window is exterior to the plasma processing region. Inner and outer coils are disposed above the outer side of the dielectric window, and the inner and outer coils are connected to a first RF power source. A powered grid is disposed between the outer side of dielectric window and the inner and outer coils. The powered grid is connected to a second RF power source that is independent from the first RF power source.

2012-12-20

20120322271

IDENTIFICATION OF DIES ON A SEMICONDUCTOR WAFER - A semiconductor wafer includes multiple dies and a die identification region adjacent to or on each die. The die identification region can include a wafer indicator and a pattern of die locations representing die locations on the wafer. A die identification marker is provided in each pattern of die locations in the die identification region specifying a location of a respective die on the wafer.

2012-12-20

20120322272

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, comprising: forming n-channel field-effect transistors on a silicon substrate; forming a first insulating film covering the field-effect transistors; shrinking the first insulating film; forming a second insulating film over the first insulating film; and shrinking the second insulating film, wherein the forming an insulating film covering the field-effect transistors and the shrinking the insulating film are repeated a plurality of time.

2012-12-20

20120322273

COATING FILM FORMING METHOD AND COATING FILM FORMING APPARATUS - A coating film forming method according to an embodiment, includes rotating a substrate, supplying a chemical solution for forming a coating film onto the rotating substrate, and supplying a liquid having a lower temperature than an atmosphere of the substrate to an edge of the substrate from a back side of the substrate while a film is formed by supplying the chemical solution onto the rotating substrate.

ROTATABLE COAXIAL ADAPTOR FOR LINKING HIGH FREQUENCY COAXIAL CABLES - A rotatable coaxial adaptor for linking high frequency coaxial cables has a first mounting block, a first bearing, a first rotary part, a connecting sleeve, a second bearing and a second mounting block. The first bearing and the first rotary part are mounted in the first mounting block and the first rotary part has a first joining tube connected to a coaxial cable. The connecting sleeve is secured to the first mounting block. The second bearing is mounted around the connecting sleeve. The second mounting block with a second joining tube connected to another coaxial cable is mounted around the second bearing and the connecting sleeve. With the structure mentioned above, the coaxial cables will not be driven to bend when devices connected to the coaxial cables are moved. Therefore, the coaxial cables can be protected from damage.

2012-12-20

20120322276

ELECTRONIC DEVICE WITH CONNECTOR - An electronic device includes a housing, a circuit board arranged in the housing, a first connector, and a second connector. The first connector includes a panel formed at a first end of the first connector and located at an outer surface of the housing. The panel defines a number of first sockets to. A number of pins extend from a second end of the first connector. The second connector includes a first connecting portion and a second connecting portion. The first connecting portion defines a number of sockets to connect the pins of the first connector. The second connecting portion includes a number of pins connected to the circuit board.

2012-12-20

20120322277

FITTING CONFIRMATION CONSTRUCTION OF CONNECTOR FOR CONNECTING CIRCUIT BOARD - A fitting confirmation construction includes a confirmation part in a first connector and a confirmation opening in a second connector. A rib is provided in the confirmation opening. A height of the confirmation part is equal to a height of the rib and the confirmation part and the rib are positioned on a same line, on a viewing direction which is viewed from an obliquely upper position rearward in an inserting direction of the second connector through the confirmation opening, in a state that the second connector is completely fit with the first connector.

SOLDERABLE ELASTIC ELECTRIC CONTACT TERMINAL - Provided is a solderable elastic electric contact terminal, which includes an elastic core having a height smaller than a width thereof, and including two or more through holes separately disposed therein and having a dumbbell shaped cross section, wherein the through holes extend along a longitudinal direction of the elastic core, an elastic rubber coating layer enveloping the elastic core to adhere thereto, and a heat-resistant polymer film having a surface adhered to the elastic rubber coating layer to envelop the elastic rubber coating layer, and another surface integrally formed with a metal layer. A top surface of the metal layer is horizontal for vacuum pickup.

2012-12-20

20120322280

PLUG CAP - One object of the invention is to provide a plug cap that more reliably prevents the leakage of current by suppressing the ingress of water from a gap between a terminal body and a rubber member.

2012-12-20

20120322281

FLIP-COVERED PORTABLE MEMORY STORAGE DEVICE - A portable memory storage device with a miniaturized memory storage assembly package with electrical contacts that further includes a casing, the casing holding the memory package and having a first end portion, a cover, the cover being rotatable about the first end portion of the casing, and at least a plug for engaging the cover and the casing and being fitted about the first end portion of the casing. When the cover is rotated about the first end portion of the casing to selectively cover or expose the electrical contacts, the plug rotates about the first end portion with the cover. Further, the first end portion includes a groove on an interior side surface, and when the cover is at a first locked state, a projection of the plug abuts against a side of the groove. The electrical contacts can be formed in accordance with the USB Specification.

2012-12-20

20120322282

SPECIAL USB PLUG HAVING DIFFERENT STRUCTURE FROM STANDARD USB PLUG AND USB RECEPTACLE MATABLE WITH THE SPECIAL USB PLUG - A universal serial bus (USB) receptacle with which and from which a standard USB plug and a special USB plug are selectively matable and removable along a predetermined direction. The standard USB plug is in accordance with a USB standard so as to have a standard shell. The special USB plug has a special shell so as to have a different structure from the standard shell. The USB receptacle comprises a detector. The detector has a contact portion. The contact portion is arranged at a position where the standard shell does not arrive when the standard USB plug is mated with the USB receptacle. The special shell is connected to the contact portion at the position when the special USB plug is mated with the USB receptacle.

2012-12-20

20120322283

CARD EDGE CONNECTOR AND ASSEMBLY INCLUDING THE SAME - A card edge connector includes a dielectric housing having an end portion configured to receive a latch/eject member for ejecting and latching a card module in a pivot manner The latch/eject member includes a lower end surface, which is located outside the dielectric housing when the latch/eject member is in the locking position.

Waterproof Connector - A water-proof connector includes a connector body and an outer housing surrounding the connector body and fixed to a case. The connector body has contacts and a main body housing having a main body receiving portion receiving a mating connector and holding the contacts. The outer housing includes an outer receiving portion accommodating the main body receiving portion of the connector body and receiving the mating connector with the main body receiving portion and a guide cylinder corresponding to a projection provided in the case when assembled to the case. The space between the case and the outer housing is sealed by a seal member at an outer side of the outer receiving portion.

SOCKET AND MOTHERBOARD WITH THE SAME - A socket for selectively mounting on a board includes a housing and a latch. The housing includes a first side plate and a second side plate parallel to the first side plate. The first and second side plates define an elongated slot therebetween for reception of the board. The latch includes an axle, a body and a fastening portion. The axle is pivotably coupled to the housing at one end of the slot. The body has one end joined to the axle and the other end to the fastening portion. The fastening portion is constructed for engagement with the board. In addition, the lateral width of the body of the latch in the direction along the width of the first side plate is smaller than that of the axle in the same direction.

2012-12-20

20120322288

ELECTRICAL CONNECTOR AND TERMINAL THEREOF - An electrical connector includes an insulating body and a plurality of terminals assembled in the insulating body. The terminal has a fastening strip of which a bottom end is bent towards one side of the fastening strip and then protrudes rearward to form a soldering portion. A top end of the fastening strip is bent towards the other side of the fastening strip and then extends forward to form a first contact portion which has a front end thereof arched upward to project out of the insulating body for electrically connecting with one circuit. A second contact portion is formed at a substantial middle of a front edge of the fastening strip and further exposed outside the insulating body for electrically connecting with another circuit.

2012-12-20

20120322289

CABLE CONNECTOR JOINT FASTENING STRUCTURE - A cable connector joint fastening structure includes a male connector, a female connector, and a fastener. The male connector includes a male terminal body with a male terminal joint, a freely rotating screw sleeve locked around the external periphery of the male terminal joint. The female connector includes a female terminal body with a female terminal joint, and an insert space formed in the female terminal joint for inserting the male terminal joint, and the screw sleeve is screwed and coupled to the female terminal joint. The fastener includes a pivot portion formed at an external side of the female connector, and a locking arm pivotally installed onto the pivot portion, extended towards the male terminal body, disposed across the screw sleeve, and locked to the male connector.

2012-12-20

20120322290

POWER SUPPLY UNIT WITH REPLACEABLE PLUG - The instant disclosure relates to a power supply unit that is compatible with different plug types and can be plugged to the power outlet at different directions. The power supply unit comprises a main body and a plug. The plug can be assembled to and connected electrically with the main body with ease. The power supply unit can be used more broadly in different regions and provide more options when plugging to the power outlet.

2012-12-20

20120322291

ELECTRIC SOCKET AND BEARING BODY THEREFOR - The invention provides an electric socket and a bearing body therefor. The bearing body includes a housing for accommodating the electrically connecting terminal, having a plurality of sidewalls that are connected and a bottom; a baffled portion on one of the sidewalls; a rib provided on the sidewall and extending longitudinally from one side to the other side of the one of the sidewalls; and a plurality of conductive pins penetrating the bottom. When the electrically connecting terminal is fit into the housing, the baffled portion opposes against the fastener of the electrically connecting terminal, and the rib is located against an outer surface of the electrically connecting terminal, thereby preventing detachment of the electrically connecting terminal from the electric socket.

2012-12-20

20120322292

ELECTRICAL CONNECTOR ASSEMBLY EQUIPPED WITH ENHANCED LOCKING MECHANISM THEREON - An electrical connector assembly includes a receptacle connector and a plug connector. The receptacle connector includes a housing unit defining a mating cavity communicating with an exterior via an insertion opening at a front end thereof. A plurality of contact grooves are defined within the housing unit and extend along a front-to-rear direction. A plurality of contacts are arranged in the contact grooves in a side-by-side manner. A pair of elastic locking devices are disposed at opposite sides of the mating cavity and each has a pair of locking arms projecting into the mating cavity. The locking arms are formed within a common plane which is perpendicular to the front-to-rear direction. The plug connector is inserted into the mating cavity and clipped by the locking arms so as to realize a better retaining effect.

2012-12-20

20120322293

ELECTRIC CONNECTOR - To prevent, with a simple structure, deformation such as a twist of an actuator at the time of moving operation and easily check the operation state of an actuator to easily and reliably establish an electrical connection, inclined surface parts are provided at both end portions in a longitudinal direction in end faces on a rotational radial outer side of the actuator pinching or freeing a signal transmission medium to approximately uniformly act an entire pressing force of an operator over a full length of the actuator. With this, a situation that the actuator is pressed as being twisted is eliminated to achieve an excellent action of pinching the signal transmission medium and an easy and reliable visual check of the state of rotation of the actuator.