ASGtools

ASGtools is a bundle of tools for generating asynchronous (clockless) circuits.

BALSA [1] provides a design flow where asynchronous circuits are created from high-level specifications, but the syntax-driven translation often results in performance overhead. To improve this, we exploit the fact that bundled-data circuits can be divided into data and control path. Hence, tailored optimisation techniques can be applied to both paths separately. We have introduced such an approach in [2], [3]. In this abstract we present a tool suite implementing this flow.

Fig. 1 shows the overall design system. Just like the original BALSA flow, we start with a Balsa program which is transformed into a Breeze netlist with the Balsa compiler. A Breeze netlist specifies a network of handshake (HS)-components e.g. communicating via the 4-phase bundled data HS-protocol. This network can be visualised with ASGbreezeGui. Afterwards, a Verilog netlist is generated from this Breeze file. In the original design flow this is done by BALSA-NETLIST – we introduce ASGresyn, a new (resynthesis) tool which will do this step in an optimised manner. The Verilog netlist, its derived delay file and a testbench for the design (e.g. generated by ASGtestGen) are given to a simulator to perform tests.

ASGresyn

ASGresyn implements the resynthesis procedure as described in [3], i.e. it generates an optimised Verilog netlist from a Breeze specification. Fig. 2 shows the internal architecture of this tool. The central operation is the splitting of the HScomponents into control and data path. The Data Path Generator and the Merging Agent are integrated into the tool itself. All other agents are seperate programs: DesiJ, ASGlogic, and breeze2stg are developed in-house, while PCOMP [4], PETRIFY [5], and PUNF/MPSAT [6] are third party. ASGresyn orchestrates all programs by calling them depending on the configuration and maintaining the generated data.

DesiJ and breeze2stg

DesiJ decomposes large STGs into smaller ones to tackle state space explosion [7] using an adjusted STG decomposition algorithm [8]. Moreover, a part of DesiJ called breeze2stg is responsible for generating STGs for the control part of a Breeze description [2]. For a more detailed description (excluding the latest features) on DesiJ see [9].

ASGlogic

ASGlogic is a logic synthesiser generating a Verilog implementation from an STG specification. The implementation of the state graph construction and equation derivation are based on the ideas from [10]. For technology mapping, we implemented methods presented in [11]. However, we are still working on enhancing the technology decomposition algorithm. As a main feature, ASGlogic provides a proper reset insertion mechanism. Note that ESPRESSO [12] is used for logic minimisation and CSC solving is delegated to PETRIFY or, alternatively, PUNF/MPSAT.

ASGtestGen

ASGTestGen produces test patterns from a Breeze netlist to verify implementations of it. It generates stimuli targeting maximal test coverage. Thus even unfamiliar Balsa programs can be verified. This work is still in progress.

ASGbreezeGui

ASGbreezeGui provides a graphical representation of a Breeze netlist with support for hierarchical designs.

[6] V. Khomenko, M. Koutny, and A. Yakovlev, “Detecting state coding conflicts in stg unfoldings using sat,” in Application of Concurrency to System Design, 2003. Proceedings. Third International Conference on, June 2003, pp. 51–60.