Title (de)

Title (fr)

Publication

Application

Priority

DE 19849909 A 19981029

Abstract (en)

The circuit has at least one logic arrangement (1) for outputting binary signals with at least one memory arrangement (120) for storing the binary output signals at times defined by a clock signal (13). At least one memory arrangement (120) has several memory cells (9,121), each with an output connected to a common output (6) via a changeover stage, from one state change of the clock signal to the next