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Is using thermal grease that significant a cost saving measure? I believe that it saves cash, but is the difference that significant? For all the r and d and fab complexity that goes into these chips, it seems like a rather small and petty way to save few bucks for such significant thermal benefits.

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Paste is expensive. Its 1/3 the price of a watercooler for your chip.
Cheap paste and watercooler keeps your chip running at 40-45 Celsius. My R1800x does.
Hot running Intel chips developing cracks is a no go. Having to overamp your chips right out of the factory to compete is an engineering flaw, among others.

I will say Intel Engineers aren't stupid. It's also not that costly in terms of profit margins. Micro-cracks don't seem like much of an issue as they solder Xeons for servers. So the above suggestion it's about conflict-free materials by the process of elimination may be true. So maybe they just used solder now temporarily for the worst offenders temperature wise and will stop using it again soon.

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Coldstarts are worse than hotstarts. Wear is tear. My experience. I had servers run 24/7 for 7 years straight. No prob. I had workstations getting shut of twice a day. Bang, dang, 2-3 years. My laptop literally shut never off and still running after 12 years. It is what it is.

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@photonboy yes even if they made a billion per day it still has the same low failure as a percentage.... the quantity however is much much higher. 10million failed units higher to be exact. And every unit costs money... so now your looking at 2 billion dollars lost at $200 per.
I would say they are justified in keeping failures lower.

I will say Intel Engineers aren't stupid. It's also not that costly in terms of profit margins. Micro-cracks don't seem like much of an issue as they solder Xeons for servers. So the above suggestion it's about conflict-free materials by the process of elimination may be true. So maybe they just used solder now temporarily for the worst offenders temperature wise and will stop using it again soon.

Micorcracks aren't as much of an issue with larger die, which Xeons tend to have.

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Is using thermal grease that significant a cost saving measure? I believe that it saves cash, but is the difference that significant? For all the r and d and fab complexity that goes into these chips, it seems like a rather small and petty way to save few bucks for such significant thermal benefits.

With bean-counters involved, a difference of a penny a unit is a big deal. While this is anecdotal, it shows my point: I know a guy that worked for a company that produced guitar amps. For one of their products, he found a way to make the amp more reliable, less prone to failure. He pitched his modification to its design, which only raised the production cost by $0.01 per unit. The bean-counters of the company rejected the idea because it broke the price-point... and failures under warranty were already covered under the corresponding budget.

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(Intel): We did this, because we need that 2$ of solder way more than you, the customers, paying over-priced products due to our inability to transition our 14nm process to 10nm process. Thank you for your support as a s**cker.

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This: "Intel has also long preached the perils of solder TIM, which can lead to shorter lifespans due to microcracks in the solder TIM that form during heat-induced expansion and contraction. That's more of a concern with smaller die, such as the six-core die on the -9400F. "

After... this: "But enthusiasts still love solder TIM for its superior cooling effects, and AMD's adoption of the material has made it a must-have for enthusiast-class chips. "

Any report on AMD CPU failing because of solder...? Probably not... Once again, typical Intel propaganda, misinformation and lies.

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I'm quite darn sure the micro-crack issue is greatly exaggerated to save face from the real issue - The money intel saves on cheap toothpaste tim vs proper soldering on high end dt chips even marketed as overclock able chips.

The issue with increased heat that the TIM causes is the shortened lifespan of the silicon especially so if pushed further due to overclocking and its inability to transfer enough heat between an loaded cpu and a good cooler making the CPU far warmer than the cooler normally allow with proper transfer.

But that's of-course conveniently left out of the discussion as it would point towards TIM as the superior solution that companies who care about their product would use...

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@photonboy yes even if they made a billion per day it still has the same low failure as a percentage.... the quantity however is much much higher. 10million failed units higher to be exact. And every unit costs money... so now your looking at 2 billion dollars lost at $200 per.
I would say they are justified in keeping failures lower.

As per the article:
"Of course, when you punch out north of a million die per day like Intel does, even a 1% increase in failure rates equates to a huge hit to the bottom line."

I'm just saying it's a strange way to word it. When you talk about the "bottom line" it's still relative. 1% is 1%.

*Also, a working CPU that was just MANUFACTURED doesn't get thrown in the garbage because you have sTIM instead of using paste in between the CPU chip and the heatspreader.

These potential solder-related failures would take YEARS to occur typically and that's going to be after a Warranty expires anyway.

So the entire "bottom line" comment in the article makes NO SENSE at all.

I will say Intel Engineers aren't stupid. It's also not that costly in terms of profit margins. Micro-cracks don't seem like much of an issue as they solder Xeons for servers. So the above suggestion it's about conflict-free materials by the process of elimination may be true. So maybe they just used solder now temporarily for the worst offenders temperature wise and will stop using it again soon.

Micorcracks aren't as much of an issue with larger die, which Xeons tend to have.

Even in those large die cases I don't think we have seen any numbers on fail rates. Really we are talking about micro cracks due to the expansion and contraction of the silicon and metal occurring at different rates. I don't know the expansion differences involved but it seems like you would need a pretty large die for this issue to show up at even a small percentage.

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