Flow motion

By Chris Edwards

Published Thursday, May 29, 2008

Reusable cores have changed the way that NXP does chip designs, and it has applied techniques that could affect the way everyone does it.

In chip-design, people tend to talk of flows - based on the idea that development is a waterfall process that moves from specification through the design of register-transfer level (RTL) logic using hardware description languages to the physical layout and routing of gates. Finally, the design is analysed as a sea of interconnected transistors to gauge whether it will work and result in a high yield once devices have been made at the fab.

Today, large chipmakers such as NXP Semiconductors are moving to fab-light strategies - where they outsource much of their production of system-on-chip (SoC) devices to foundries. So it looks as though the design flow looks to be the place where the chipmakers need to focus. But it is not as simple as that, says Barry Dennington, NXP's senior vice president in charge of design in an interview with E&T at the Design Automation and Test in Europe (DATE) conference.

"The RTL-to-gates flow is not commoditised. But we are experts in developing these flows. We are best-in-class or at least as good as the competition in developing them," says Dennington. But the company does not see that much value in assembling its own RTL-to-gates flow or in writing tools that can be supplied by specialists.

"We have made a big move by saying: 'We don't want to buy 20 different tools to form a design flow'. We made a stronger commitment last year to Cadence and we will really make that partnership work. We will go hand-in-hand with them to develop techniques collaboratively," says Dennington. Areas of collaboration include low-power design - NXP has adopted the Common Power Format originally developed by Cadence - and in techniques to make it easier to put different radio-frequency interfaces on the same chip.

"We are trying as much as possible to eliminate the internal tools. There is no point trying to make a better Spice simulator," Dennington claims. "If it is commercially available then we will buy it. We want to focus on things that are differentiating."

However, it does not mean that NXP sees Cadence as its sole supplier or, more importantly, the creator of a complete flow that the chipmaker can use across the company, from standalone analogue chips to SoCs.

"Nobody has offered a flow in the market. I am interested in talking to companies who would like to do that. It is something disruptive that is yet to come," Dennington says. Although the EDA suppliers can provide tools to make up a flow, none have, so far, built an environment that glues them together into a cohesive whole, and which automates the most repetitive processes. The startup Reshape made some forays into this area, having acted as a design-services company, but it was forced to shut its doors in 2006, its assets bought up by Magma. "We saw a lot of benefit in Reshape," Dennington claims, especially when it came to working with Magma's Talus implementation tools.

"Automation has to come," argues Dennington. "We focus automation on anything that is repeatable in the design process."

NXP has a number of initiatives to streamline the design process, such as 'flawless design'. The aim, says Dennington, is to get to the point where a major SoC project, not just a variant, should be fully functional with, at most, one change to a metal mask after tapeout.

"We hold frequent design reviews. They can take a full day. The teams go through checklists of: 'Have you checked that and observed this?'" Dennington explains. As common approaches are developed and rendered into a form that can be automated, the flow is updated. "We then refresh the checklist to include things that you still have to do manually."

Measurement

Measurement has become a core part of how NXP organises chip design. For a number of years, the chipmaker has benchmarked some of its projects against the database built by Numetrics Management Systems (E&T, March 8).

"We started a few pilots with NXP about four years ago," says Ron Collett, Numetrics' president and CEO. "One of the groups that we piloted with was the identification group. They studied it and said it looks very powerful. We then launched into a multi-year deal with them.

"The big difference now is that the planning solution is being deployed across NXP. They are deploying all their IC projects."

Dennington notes: "We have gone from the situation where we say to teams, 'We would like you to use Numetrics', to where it is mandatory that they use Numetrics. The tools give us great predictability and they allow us to set targets on our suppliers."

Collett adds: "We are benchmarking all their project plans against industry norms. And applying tools to estimate cycle times. For example, if I change staffing levels, how will that change the cycle time?"

The focus on project manage-ment rather than individual design tools is something that NXP expects to pay off, says Dennington: "Much better discipline and governance allows us to use multiple design teams much more efficiently. That is part of working on exellence in execution. It is taking away one variable and one unknown."

Having used the Numetrics database for benchmarking and planning hardware development, Dennington says NXP is now working with Numetrics on techniques for doing the same for embedded software.

Collett says NXP is not alone in adopting the benchmarking approach developed by Numetrics: "We are working with six of the top ten manufacturers. It would be inappropriate for me to say if NXP is ahead but NXP is certainly a leader in formalising this approach."

The move to more focused design management is symptomatic of the way in which parts of the design flow have become standard across chipmakers. "They all buy their EDA tools from the same companies. The methodologies are all common. To a great extent, the difference comes down to the people and the organisational dynamics.

"The software-metrics work is in the research lab," says Collett.

"You have to have competitive tools and flows and no one has yet cornered a market on those things. But it is the application, the discipline that distinguishes things. In a trite way, it is the culture," Collett explains.

Speed of execution is one way that the large chipmakers now see themselves differentiating as they move to fab-light strategies. With less focus on manufacturing and even on trying to differentiate through physical implementation, the focus has to be on the high-level design and how fast it can be put together.

Machine approach

Ultimately, NXP is looking for a kind of production line that will let the company quickly produce variants of chips based on a mixture of its own and third-party IP. But some things still have to happen in the world of IP.

Dennington claims: "IP is still the largest reason for respins. We need a machine approach to check it and verify it, rather than take it on one at a time. It is where formal verification can come in. Some IP has more than 200 configurations. What we need is a machine approach that lets us go back and formally verify it quickly.

"Most techniques take a long time and it is tough to get the speed of execution across the whole family of IP. We are working with some partners on that right now."

However, the use of ready-made IP has been fundamental to assembling SoCs. As a driving force in the Spirit Consortium, NXP has embraced the IP-Xact specification to make it possible to define and store IP configurations in a database that can be used to automate the assembly of much of the chip. The result was an internal tool called NXBuilder.

"The big advantage is that all the IP is in an 'IP Yellow Pages'. It is not ready for full-chip design, including I/O, yet. But it is good for complex designs with three or four processors. It is very capable," says Dennington.

Warren Savage, president of IPextreme, which packages cores developed by chipmakers, claims: "They have developed a culture of reuse and I have never seen it on this scale. I have seen in the last ten years that people have done these reuse programmes. And then it all starts falling backwards. But NXP has a way to keep this programme on track.

"It has been the result of almost four years of development and has picked up really good traction in the last 12 months. The first product to use it was in automotive and we kicked out the early bugs. It is now used across 14 different businesses. It is now at the point where we have EDA companies knocking on our door to get more engaged. They are coming to us to see what they can do to participate in that flow. Some companies are very interested in connecting with NXBuilder."

However, there is a tension between what NXP's management sees as differentiating design tools and those that are approaching the level of commodity. "Where NXP is focused on differentiating is really in the system-solution area and then providing other breakthroughs in things like NXBuilder," concludes Dennington.