Generate HDL Code Using the Simscape HDL Workflow Advisor

If you have a license for HDL Coder™, you can generate HDL code from your Simscape™ model for deployment onto FPGA platforms using the Simscape HDL Workflow Advisor. The Simscape HDL Workflow Advisor first helps you to convert your Simscape model to a Simulink® implementation. It then converts the Simulink model to HDL code using HDL Coder. Converting your Simscape model to HDL code allows you to:

Accelerate the simulation of physical systems by using an optimized
implementation of Simscape models

Use the reconfigurability and parallelism capabilities of the FPGA for rapid
prototyping

Simulate the HDL implementation in real time using hardware-in-the-loop (HIL)
simulation

Simscape HDL Workflow Advisor Steps

The general workflow for converting a Simscape model to HDL code using the Simscape HDL Workflow Advisor consists of these steps.

Generate baseline results for your Simscape model.

Ensure that the model contains only linear or switched linear blocks by
using the simscape.findNonLinearBlocks function. This
function detects the nonlinear blocks in your Simscape model. The function returns the number and type of networks,
that is, linear, switched linear, or nonlinear, based on the blocks that the
network contains. The function also returns the names of any blocks that
yield nonlinear equations. Update or replace any blocks that yield nonlinear
equations.

Ensure that simulation results of the model, which now contains no blocks
that yield nonlinear equations, match the baseline results.

Configure the Simulink model for HDL code generation by running the
hdlsetup function. The
hdlsetup function configures the
fixed-step solver for HDL code generation compatibility and
specifies the simulation start and stop times.

Save the model parameters and validation model generation
settings.

Generate code using the makehdl
function.

Limitations

The Simscape HDL Workflow Advisor does not work for Simscape networks that contain:

Events.

Mode charts.

Delays.

Enabled runtime parameters.

Periodic sources.

Nonlinearities that result from network connectivity. If your model does
contain a nonlinearity of this sort, the sschdladvisor
function may run all tasks to completion, but generates a zero-value
output.

Generate HDL Code for a Simscape Model Using the Simscape HDL Workflow Advisor

This example shows how to convert your Simscape model to HDL code using the Simscape HDL Workflow Advisor. To learn how to configure your Simscape network and Simulink model for real-time simulation and HDL code generation, see Model Preparation. To open a
version of the model that is already prepared for using the Simscape HDL Workflow Advisor, see Generate HDL Code by Using the Simscape HDL Workflow Advisor.

Model Preparation

To prepare your Simscape model for conversion to HDL code for FPGA deployment:

Open the model and show hidden block names. At the MATLAB® command prompt,
enter

To compare the baseline simulation results to results from modified
versions of the model later, remove the data point limitation on the
Load Voltage scope block and enable data
logging to the Simulation Data Inspector for the signal that inputs data
to the scope.

In the configuration parameters for the scope, for the
Logging parameters, clear the
option to limit data points.

Right-click the connection line to the Load
Voltage scope block and select
Log selected signals.

The logging badge marks the signal in the model.

Simulate the model and view the results in the Simulation Data
Inspector.

As needed, press the spacebar on your keyboard to fit the Simulation
Data Inspector plot to view.

The baseline simulation results are as expected for the full-wave
bridge rectifier load voltage.

The Simscape HDL Workflow Advisor cannot convert nonlinear networks to
HDL Code. Before running the advisor, identify and replace blocks that
cause your network to be nonlinear. To identify the blocks, use the
simcape.findNonlearBlocks function.

simscape.findNonlinearBlocks(baselineModel)

Found network that contains nonlinear equations in the following blocks:
'ssc_bridge_rectifier/AC Voltage Source'
The number of linear or switched linear networks in the model is 0.
The number of nonlinear networks in the model is 1.
ans =
1×1 cell array
{'ssc_bridge_rectifier/AC Voltage Source'}

You can replace the Simscape periodic source by adding a Simscape
Controlled Voltage Source block in the
Simscape network with a Simulink
Sine Wave block outside the network. An added benefit is
that you can configure the frequency and amplitude for the Sine
Wave block at run time during real-time simulation.

Delete the AC Voltage
Source block.

Add a Sine Wave block from the Simulink Sources library.

Add a Simulink-PS Converter
block from the Simscape Utilities library.

Connect the Sine Wave block to the
Simulink-PS Converter
block and the Simulink-PS
Converter block to the
Controlled Voltage Source
block.

The Simulink model is configured for variable-step simulation. If you
specify the Sine Wave block sample time as
-1, for inheriting the sample time, the
simulation generates a warning. Instead, specify the sample time for the
Sine Wave as 0 by using a
workspace variable that you can later adjust for improving simulation
speed or accuracy. The removed AC Voltage
Source block has a Peak
amplitude of sqrt(2)*120V and a Frequency of
60Hz.

Configure the Sine Wave block.

Define the sample time in the
workspace.

Ts = 1e-5;

Set the Amplitude parameter to
sqrt(2)*120.

Set the Frequency (rad/sec) parameter
to 60*2*pi.

Set the Sample time parameter to
Ts.

Ensure that there are no blocks that cause your network to be
nonlinear.

To examine the progress of the Simscape HDL Workflow Advisor later, add and connect a
Digital Clock block from the Simulink Sources library and a Display block from
the Simulink / Sinks library, as shown in the figure. For the
Digital Clock, specify Ts for
Sample time parameter.

The model is currently simulating in continuous time using a
variable-step solver. For real time-simulation, a fixed-step solver is
required for discrete-time simulation. Sample time colors and
annotations help you to determine if your model contains any continuous
settings. To turn on sample time colors and annotations, in the
Simulink model window, select Display >
Sample Time > All.

The model diagram updates and the Sample Time Legend displays.

Configure the model for real-time simulation.

Configure the Simulink model for fixed-step, fixed-cost simulation.
In the Model Configuration Parameters, for the
Solver parameters, set:

Set Type to
Fixed-step.

Set Solver to
discrete (no continuous
states).

Configure the Simscape network for fixed-step, fixed-cost simulation.
For the Solver Configuration
block:

Select Use local
solver.

Ensure that Solver type is
set to Backward
Euler.

Specify Ts for the
Sample time.

Simulate the model and compare the results to the baseline results in
the Simulation Data
Inspector.

Generate HDL Code by Using the Simscape HDL Workflow Advisor

Generate HDL code by running the Simscape HDL Workflow Advisor either on the Simscape model that you prepared by stepping through Model Preparation or on a
Simscape model that is already prepared for code generation.

Rename the model.

To continue working with the model that you prepared for HDL
code generation, rename the model
ssc_model.

To open and use a model that is already prepared for HDL code
generation, at the MATLAB command prompt,
enter

Extract the state-space coefficients. Select State-space conversion > Get state-space parameters and then click Run this task. The
conversion can take some time. The Display block in the model
window shows the elapsed simulation time.

After running the task, the advisor displays a summary of the state-space
representation and a table of parameters.

Number of states: 5

Number of inputs: 1

Number of outputs: 1

Number of modes: 7

Discrete sample time: 1e-05

Parameter

Parameter
size

A

5 x 5 x 7

B

5 x 1 x 7

F0

5 x 1 x 7

C

1 x 5 x 7

D

1 x 1 x 7

Y0

1 x 1 x 7

The size of the state, mode, and parameter data helps you estimate how
much of the FPGA resources are required to deploy the model. The higher the
values, the more FPGA resources are required. The input and output data
indicate the number and type of I/O connections needed for real-time
deployment and visualization.

When the implementation model is generated, the advisor reports that the
task is passed and displays a link to the generated implementation model,
which is named gmStateSpaceHDL_ssc_model.

Open the generated implementation model by clicking the provided
link.

The model contains blocks labeled:

Subsystem — Simulink subsystem that contains the prepared model and any
signal routing that the Simscape HDL Workflow Advisor adds. For
this model, the advisor adds a Goto block that
routes the Sine Wave block input to the
HDL Subsystem.

T — From block that
routes the Sine Wave block input from the
Subsystem block to the HDL
Subsystem block.

Rate Transition1 — Handles the
transfer of data between blocks operating at different
rates.

HDL Subsystem —Simulink subsystem that contains an HDL code generation
compatible version of your Simscape network. For this model, the advisor adds a
Goto block that routes the Sine
Wave block input to the HDL
Subsystem block.

Scope — Displays the load
voltage.

Prepare the HDL Subsystem for a simulation
comparison to the baseline results:

Delete the TFrom block.

Copy and paste the Sine Wave block from
the Subsystem block into the top-level
model.

Connect the Sine Wave block to the
Rate Transition1 block.

Delete the Subsystem block, which
contains the baseline model.

Enable data logging to the Simulation Data Inspector for the
signal that goes to the Scope block.

To ensure that the HDL subsystem corresponds to your original Simscape model, simulate the model and compare the results to the
baseline simulation
results.

The HDL code generation report opens and includes any
generated errors or warnings. The report includes a link to the
resource utilization report, which describes the resource
requirements for FPGA deployment.

The generated HDL code and validation model are saved in the
hdlsrc\gmStateSpaceHDL_ssc_model\html directory.
The generated code is saved as
HDL_Subsystem_tc.vhd.

To generate HDL code for deployment to a specified target, use the HDL
Workflow Advisor.

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