Western Digital has announced that it will begin production of 96-layer 3D NAND in 2018. It will make triple-level cell and quad-level cell NAND with die capacities ranging from 256 Gb to 1 Tb. QLC NAND is predicted to have 100-150 program/erase cycles (endurance) compared to about 1000 for TLC:

Given such endurance, it is logical to expect 3D QLC NAND to be used for primarily removable storage as well as for ultra-high capacity datacenter drives for the so-called near-WORM (write once read many) storage applications. For example, Toshiba last year discussed a QLC-based datacenter SSD with 100 TB capacity for WORM apps.

Western Digital plans to begin sampling of select 96-layer BiCS4 3D NAND configurations in the second half of this year, but the manufacturer does not specify which dies will sample when. As for mass production, Western Digital intends to start volume manufacturing of their 96-layer 256 Gb 3D NAND in 2018, with other dies to follow later. Based on Western Digital's announcements made earlier, the company will gradually introduce more sophisticated BiCS4 96-layer configurations in 2018 and 2019, before moving to BiCS5 sometimes in 2020. That said, it makes sense to expect the highest capacity BiCS4 ICs to ship later rather than sooner.

[BiCS = "Bit-Cost Scaling". Yes, it does not make sense to me, either. --Ed.]

Related Stories

Western Digital has started sampling its 96-layer 3D NAND chips featuring QLC architecture that stores four bits per cell. The chip happens to be the world's highest-capacity 3D NAND device. The company expects to commence volume shipments of this memory chip already this calendar year.

Western Digital's 96-layer BICS4 3D QLC NAND chip can store up to 1.33 Tb of raw data, or around 166 GB. The IC will be initially used for consumer products Western Digital sells under the SanDisk brand, so think of memory cards (e.g., high-capacity SD and microSD products), USB drives, and some other devices. The manufacturer expects its 3D QLD[sic] NAND memory to be used in a variety of applications, including retail, mobile, embedded, client, and enterprise, but does not elaborate on timing at this point.

The 1.33-Tb BICS4 IC is Western Digital's second-gen 3D QLC NAND device. Last year the company announced its BICS3 64-layer 3D QLC chips featuring a 768 Gb capacity, but it is unclear whether they have ever been used for commercial products. Meanwhile, it is clear that the device was used to learn about 3D QLC behavior in general (i.e., endurance, read errors, retention, etc.)

[...] What is noteworthy is that officially the BiCS4 range was to include both TLC and QLC ICs with capacities ranging from 256 Gb to 1 Tb, so the 1.33 Tb IC is a surprising addition to the lineup which signals Western Digital's confidence of its technology.

Recent products have been using 512 Gb per die NAND, with 768 Gb and 1 Tb on the horizon. Samsung's announced 128 TB SSD was supposed to use 1 Tb 3D QLC dies, so ~1.33 Tb dies could bring that capacity to about 170 TB. Given a couple more generations of NAND or some fancy die/package stacking, and we will probably see a 1 petabyte SSD.

64-layer 3D NAND is shipping, but the 256Gbit die will come and go rapidly. That's what makes this NAND cycle different. Many of the companies we've spoken to do not want to invest in products with such a limited shelf life. The 512Gbit die are right around the corner from the fabs. Some estimates put a major ramp up coming before mid year. The technology offers a 2x capacity increase while taking only a little more space on the wafer. The bits per wafer doesn't double, but it gets very close. The retail products coming in the second half of 2018 with have a heavy impact on SSD pricing. Some estimates from engineers we've spoken with put retail pricing on track for a 20% to 30% reduction over similar-capacity products shipping today.

Emerging technologies and form factors that reduce the material costs will also play a role. Toshiba Memory America showcased the new RC100 NVMe SSD that uses multi-chip packaging to cram the controller and flash in a single package.

Both Toshiba (or whomever ends up buying Toshiba's memory fabrication assets) and Western Digital (WD) have both recently announced plans to produce 3D QLC (four bits per cell) NAND:

Western Digital's SanDisk subsidiary and Toshiba have a long history of jointly developing and manufacturing NAND flash memory. While that relationship has been strained by Toshiba's recent financial troubles and attempts to sell of their share of the memory business, the companies are continuing to develop new flash memory technology and are still taking turns making new announcements. In recent months both companies have started sampling SSDs using their 64-layer BiCS3 TLC 3D NAND and have announced that their next generation BiCS4 3D NAND will be a 96-layer design.

Yesterday Western Digital made a small announcement about their other main strategy for increasing density: storing more bits per memory cell. Western Digital will introduce four bit per cell QLC parts built on their 64-layer BiCS3 process, with a capacity of 768Gb (96GB) per die. This is a substantial increase over the 512Gb BiCS3 TLC parts that will be hitting the market soon, and represents not only an increase in in bits stored per memory cell but an increase in the overall size of the memory array. These new 3D QLC NAND parts are clearly intended to offer the best price per GB that Western Digital can manage, but Western Digital claims performance will still be close to that of their 3D TLC NAND. Western Digital's announcement did not mention write endurance, but Toshiba's earlier announcement of 3D QLC NAND claimed endurance of 1000 program/erase cycles, far higher than industry expectations of 100-150 P/E cycles for 3D QLC and comparable to 3D TLC NAND.

Western Digital will showcase SSDs and removable flash media using QLC NAND at the Flash Memory Summit from August 8-10.

Will QLC NAND endurance become a bigger issue than it is with TLC? Will this be used primarily for high density cold storage like Facebook has asked for?

Samsung has announced a 30.72 TB SSD. It uses 64-layer 512 Gb TLC NAND dies, with 16 of each stacked to make a 1 TB package. It has 40 GB of DDR4 DRAM cache, also using layered packages:

The PM1643 drive also applies Through Silicon Via (TSV) technology to interconnect 8Gb DDR4 chips, creating 10 4GB TSV DRAM packages, totaling 40GB of DRAM. This marks the first time that TSV-applied DRAM has been used in an SSD.

Complementing the SSD's hardware ingenuity is enhanced software that supports metadata protection as well as data retention and recovery from sudden power failures, and an error correction code (ECC) algorithm to ensure high reliability and minimal storage maintenance. Furthermore, the SSD provides a robust endurance level of one full drive write per day (DWPD), which translates into writing 30.72TB of data every day over the five-year warranty period without failure. The PM1643 also offers a mean time between failures (MTBF) of two million hours.

Samsung started manufacturing initial quantities of the 30.72TB SSDs in January and plans to expand the lineup later this year – with 15.36TB, 7.68TB, 3.84TB, 1.92TB, 960GB and 800GB versions – to further drive the growth of all-flash-arrays and accelerate the transition from hard disk drives (HDDs) to SSDs in the enterprise market.

Toshiba was hoping to complete a deal with the winning bidder at a shareholder meeting yesterday. In the weeks leading up to that meeting, Toshiba had to issue several reminders of how desperate their financial state is: disclosing new legal actions against them by investors seeking damages pertaining to Toshiba's accounting scandals, announcing that the Tokyo and Nagoya stock exchanges are moving toward delisting Toshiba, and revising their outlook for fiscal year 2016 to reflect a negative shareholder equity of (¥581.6B). Meanwhile, Western Digital reiterated their objection to Toshiba selling the memory business to a third party and warned several third parties that they would view participation in the sale as tortious interference. Most recently, Western Digital also reportedly resubmitted its bid for Toshiba's memory business with an offer around ¥2 trillion, close to the amount offered by the consortium Toshiba had previously selected as the preferred bidder. Toshiba for their part has made no mention of Western Digital's offer.

In the aftermath of yesterday's shareholder meeting, Toshiba made several announcements. As expected, Toshiba was not able to finalize a sale of the Toshiba Memory Corporation subsidiary they have consolidated the memory-related assets under, but they are continuing to negotiate with the consortium. Toshiba announced plans for further investment in the joint venture's Fab 6 in Yokkaichi, Japan, and questioned whether SanDisk would jointly invest in the 3D NAND fab. Toshiba also announced that it has filed a lawsuit in the Tokyo District Court against Western Digital alleging unfair competition and seeking an injunction and damages. Toshiba claims that Western Digital is exaggerating their consent rights and also alleges that Western Digital has improperly obtained Toshiba trade secrets by transferring some employees from SanDisk to Western Digital whom have access to Toshiba confidential information through the joint ventures.

Toshiba last week announced its first 3D NAND flash memory chips featuring [the] QLC (quadruple level cell) BiCS architecture. The new components feature 64 layers and developers of SSDs and SSD [controllers] have already received samples of the devices, which Toshiba plans to use for various types of storage solutions.

[...] Besides [its] intention to produce 768 Gb 3D QLC NAND flash for the aforementioned devices, the most interesting part of Toshiba's announcement is [the] endurance specification for the upcoming components. According to the company, its 3D QLC NAND is targeted for ~1000 program/erase cycles, which is close to TLC NAND flash. This is considerably higher than the amount of P/E cycles (100 – 150) expected for QLC by the industry over the years. At first thought, it comes across [as] a typo - didn't they mean 100?. But the email we received was quite clear:

- What's the number of P/E cycles supported by Toshiba's QLC NAND?- QLC P/E is targeted for 1K cycles.

Endurance miracle putting QLC on par with TLC, or idle talk about a product that won't be out for 1-2 years?

For now, let's talk about the goods we'll see over the next year. The biggest news to come out of the new Samsung campus is QLC flash. Samsung's customers set performance and endurance specifications and don't care about the underlying technology as long as those needs are met. Samsung says it can achieve its targets with its first generation QLC (4-bits per cell) V-NAND technology.

The first product pre-announcement (it doesn't have a product number yet) is a 128TB SAS SSD using QLC technology with a 1TB die size. The company plans to go beyond 16 die per package using chip stacking technology that will yield 32 die per package, a flash industry record.

someone needs to learn about unpowered retention..(Score: 2) by qzm on Saturday July 01 2017, @11:27AM

'Given such endurance, it is logical to expect 3D QLC NAND to be used for primarily removable storage'

Except that the unpowered data retention, with such small write endurances, is likely to be TERRIBLE.

WORM applications may well be ok - as the controller continuously scans the cells and refreshes ones drifting (thank you, advanced ecc..)However, removable storage, with the implication of long term unpowered data retention? I suspect not.

QLC, without a major improvement in cell stability, is going to be a long term reliability disaster.I can see poor low-end consumers wearing the fallout from that one - cheap SSD drives in OEM equipment that are unreliable but 'meet industrystandards'.