Language compliance VCS supports all popular design and verification languages, including SystemVerilog, Verilog, VHDL, OpenVera™, SystemC™, and the Accellera® UVM™, VMM, and OVM methodologies (Figure 2). VCS’ support for Accellera UVM also includes access to the VMM/UVM interoperability kit, which enables the use of VMM with UVM and vice versa. Besides supporting digital circuit design, VCS also supports analog and mixedanalog designs through Verilog-AMS, SPICE and SPF. This comprehensive support for advanced flows and methodologies enables VCS to help users develop the highest-quality mixed language functional verification environments in the shortest amount of time.

Performance
VCS is the industry’s highest performance simulation solution. VCS offers both industry-leading compile time and run time performance improvement technologies.

Compile time reduction for SoC designs

VCS provides advanced tools for reducing compile turnaround time for complex SoC designs, including Precompiled IP support targeted at IP integration flows, Partition Compile to isolate portions of the testbench that are not changing during development cycles, and Dynamic Reconfiguration to compile for a target and select which model is used at runtime (Figure 4). Combined, these tools offer the most comprehensive set of solutions to maximize compile efficiency, and reduce turnaround time for SoC verification flows.

Figure 4. Dynamic reconfiguration

Partition compile VCS’ Partition Compile technology allow users to achieve up to 10x faster compile time by only recompiling code that has changed, and reusing the libraries for the unchanged modules already compiled earlier.

Dynamic Reconfiguration VCS’ Dynamic Reconfiguration (Figure 4) feature enables turnaround time reduction over entire regressions by allowing users to compile once, and run different configurations/testbenches without need for recompiles. All debug and coverage features work seamlessly regardless of configuration.

Simulation runtime reduction
VCS’ high performance simulation engines are continuously improved with state-of-the-art performance and memory optimization technologies. These technologies provide best-in-class out of the box performance, and also support tuning simulator performance to a wide variety of user environments.

Save/RestoreSave/Restore feature (Figure 5) lets the user save the state of simulation in a file for it to be restored at another time or on a different machine. Designs that have a long design initialization simulation can benefit from this feature by saving the initial state and restoring the simulation to after initialization in subsequent runs thereby reducing simulation time.

Multicore Support VCS’ multicore technology offers two robust use models: design-level parallelism (DLP) and application-level parallelism (ALP) (Figure 6). DLP enables users to concurrently simulate multiple instances of a core, several partitions of a large design, or a combination of the two. ALP allows users to run testbench, assertions, coverage, and debugging concurrently on multiple cores. Multicore technology has shown up to 2x runtime speed ups on GLS designs.

Native Low PowerVCS’ Native Low Power (NLP) simulation technology provides VCS with comprehensive low power verification and debug capabilities. NLP integration with Verdi also enables easy LP debug with advanced LP features, and provides excellent support for LP assertions and coverage for coverage-driven verification flows. VCS’ native low power solution allows user to perform multi-voltage simulations so that they can feel the freedom to implement several techniques for power management.

X-Propagation Certain RTL semantics, such as using x-value to denote indeterminate state, may not model actual hardware behavior accurately. Instead of having to rely on increasingly costly gate level simulation, VCS provides a way to simulate x-propagation in multiple modes to model x-value in either more, less or equally optimistic modelling as compared to the regular gate-level simulation

AMS CosimulationVCS provides many benefits for AMS designers namely – real number modeling, native low power and advanced methodology with AMS testbench. In addition, all analog and mixed signal data can be viewed in Verdi’s advanced AMS debug environment, which is natively integrated with VCS to enable fastest analysis and finding root cause.

Native Integrations
Native integrations between the high performance VCS simulation engine and the other advanced engines in the Synopsys Verification Continuum Platform (Figure 3) enables improvements in time-to-market by up to months.

Conclusion
With VCS, not only does one get the industry leading performance and capacity in simulation, but also the fully integrated suite of technologies and tools built around the simulator to drive any verification strategy a designer wants to execute. The product roadmap for VCS technologies and verification flow in general follows the path treaded by the design leaders in the industry. In addition, VCS comes with the top-notch support so that verification schedules stay on track.