HES-DVM™ 2013.11 Delivers Increased Speed and Debugging

Introducing Turbo Mode and HesDebugApi

Aldec recently released HES-DVM 2013.11 which introduces an array of customer-requested new features and improved debugging capabilities, speed, and co-emulation infrastructure.

Here we’ll cover two new features: HesDebugApi and SCE-MI Turbo Mode.

HesDebug API is a C/C++ interface for all debugging features of the HES emulation platform. The API arms the testbench with functions that change the way designs are verified during emulation – moving from traditional black-box verification approach to a white-box verification approach. The HES debug API provides access to all the debug functions readily available from the HW Debugger GUI interface.

Such features include:

Stop and Run emulation clocks

Select Dynamic Debug probes for capturing into waveform

Check for Dynamic Debug probe value at any time

Configure Static Probes groups

Configure triggers and breakpoints

Check for triggers status

Access data in HES-DVM mapped memories via back-door interface

Upload HES-DVM mapped memories

A new Controlled Clocks (CClocks) generator module is also available in the HES-DVM 2013.11 SCE-MI infrastructure. In addition to SCE-MI compliant clock generation, it provides Turbo Mode, which allows running emulation orders of magnitude faster in the case of using multiple asynchronous clocks. SCE-MI specification requires that any Cclock is derived from Uclock (uncontrolled clock) by division. Asynchronous clocks may have completely unrelated periods, so deriving them from the common Uclock requires the latter to have much higher frequency. Given that Uclock is the fastest emulated clock, Cclocks derived in SCE-MI compliant mode would be much slower. The Turbo Mode allows increasing speed of Cclocks preserving their frequency relations to each other but not to UClock.

Bill is responsible for Aldec Hardware Emulation and SoC / ASIC Prototyping. He received his B.S. in Computer Engineering from Auburn University in Alabama in 2011, and currently undertaking his M.S in Electrical Engineering with a focus on hardware emulation methodology and Built-In-Self-Test for high capacity FPGAs. He is also currently a graduate research assistant for the University of Nevada Systems and Integration laboratory studying Network-on-Chip BIST strategies.