Hybrid Domino XOR Gate with Dual Threshold Voltage Transistors

Milad Alizadeh, Mozhgan Golzani, Mohammad Poliki

Abstract

At the present time, in integrated circuit technology CMOS, low power design is an important subject in system design. In order to achieve this target, power consumption must be minimized. In this article two new domino XOR gates in 45nm technology are presented. First proposed circuits adopt hybrid transistor topology in the pull-down network with all transistors being low threshold voltages. A second proposed circuit adopts hybrid topology with dual threshold voltage transistors. By eliminating two input inverter and preventing the pulse flow to the output node during the precharge phase, power consumption in this circuit is reduced. First proposed circuit reduces active mode power consumption by 78.91% and 54.55% as compared to standard N-type domino XOR and P-type domino XOR.. Similarly, second proposed circuit reduces active mode power consumption by 81.43% and 59.98% as compared to standard N-type domino XOR and P-type domino XOR.