Efficient adiabatic circuits recycle I/O power

Heat generated by CMOS switching is the bane of semiconductor designers and developers of end-user products. At the chip level, wasted energy in the form of heat becomes more of a problem with each new process geometry. Designers expect that sometime in the next 20 years, conventional process technology will reach a point at which any current flow will generate sufficient heat to melt ultrafine circuit features.

The implications for product developers are more immediate, particularly in battery-powered designs. The energy density provided by emerging battery technologies is not scaling with the processing power necessary to satisfy market demand for more features and functionality in PDAs, mobile phones, laptop PCs and other modern must-haves. Device developers currently have to trade off features against an acceptable battery size. In any case, high-energy-density battery technologies, such as lithium-ion, are also more expensive.

The traditional means of tackling the problem, such as shrinking transistor sizes, have made possible vast efficiency gains in the core of a typical mobile processor. Total consumption continues to rise, however, since many more transistors are fabricated on the chip. In addition, process shrinks fail to correct the impending "melting transistor" problem. Further measures to reduce heat dissipation include lowering current leakage using alternative material technologies, such as improved gate dielectrics.

These techniques alone, however, are unlikely to deliver the energy savings the industry and markets are looking for. Such problems demand a more radical approach offering new techniques.

Among those new techniques, reversible, or "adiabatic," computing holds out the promise of greatly increased energy efficiency by eliminating the constant destruction of information and increasing entropy that happens within conventional computing processes.

The adiabatic concept is rooted in the early 1960s, when researcher Rolf Landauer proved that energy is wasted by erasing data, rather than by computing the data itself. (R. Landauer, "Irreversibility and Heat Generation in the Computing Process," IBM J. Research and Development, Vol. 3; July 1961, 183-191.)

Since Landauer's Principle emerged, researchers have been developing computing processes that recycle computed data, rather than continually erasing bits in the process of generating new computations. For example, subtracting instead of erasing can theoretically clear a register bit without expending wasted energy as heat.

A commercially available, high-speed processor performing fully adiabatic computing will be a long time coming. For one thing, it demands a completely new approach to processor design.

Nonetheless, adiabatic circuits are poised to deliver tangible rewards right now by addressing specific on-chip functions that conventionally consume a large proportion of a processor's total power demand. For example, the efficiency gains in the core have dwarfed improvements in the I/O pin drivers. Since each chip has hundreds or thousands of I/O pin drivers, these now contribute disproportionately to the processor's overall energy consumption.

Textbooks offer designers two approaches to terminating an I/O line: series or parallel termination using a resistor. In either case, the resistor's purpose is to deliberately destroy the energy contained in the fast edges of the propagated signals. Terminating with a series resistor is the established choice for midspeed signals over short distances, such as those encountered in portable systems.

In a classic, textbook series termination, energy is first drawn from the battery to charge the load capacitance, later only to be discharged again. The load capacitance and the transition frequency control the total rate of energy loss or power consumption according to the equation: power = fCV2. This energy finally dissipates as heat in the driver output resistance. Making that resistance smaller will make the circuit faster but does not improve the efficiency.

It is also important to note that the output resistance of the driver should equal the impedance of the line, because the outward-bound wave voltage doubles when it reaches the destination and reflects back toward the source. Without the matched resistance, a full-height wave would be launched, and when voltage doubled, the reflection would wreak havoc with signal integrity and EMC. Each complete cycle follows the same pattern, first drawing energy from the battery to charge the load capacitance, which is later discharged. Every transition results in heat generation.

Now, ignore the textbook. Consider an adiabatic driver built using a three-pole switch. Fig. 1 contrasts this with a conventional driver. The low-resistance center position is connected not to a battery but to an on-chip MOS energy storage capacitor precharged to half the supply voltage.

Moving the switch to its center position launches a half-height outbound wave without burning power in a resistor. Instead, the current is supplied directly and efficiently from the storage capacitor. Since it is not possible to eliminate all losses, a small amount of energy is taken from the battery.

During an opposite transition, from high to low, the direction of current flow is reversed. Stored energy in the load can therefore be restored to the energy storage capacitor, making the complete cycle a nearly lossless, or adiabatic, process.

Adiabatic Logic Ltd. has used this principle to build an Intelligent Output Driver (IOD) capable of providing up to a 75 percent power savings. As a further benefit, termination resistors are no longer required, saving board space and bill-of-materials costs in the end product.

Fig. 2 shows a schematic of the IOD, which contains pull-up and pull-down MOSFETs like a conventional driver, as well as a much larger MOSFET with low "on" resistance in the 2- to 5-ohm range. This connects the output pad to a midrail reservoir capacitor only during transitions. The small control circuit shown adapts the timing of the switch to synchronize with the return of the reflected wave. This is very important. It allows the IOD to actively mimic an ideally matched series termination resistor. Designers no longer have to optimize the termination resistance post layout. The IOD can also respond adaptively to the timing of real events on the line, and thereby always ensure optimally fast signal rise and fall times without inviting EMC worries.

In general, adiabatic switching blocks occupy a larger silicon area than their conventional predecessors. As can be seen from Fig. 2, the IOD makes for a more complex pin driver on the IC, resulting in increased silicon area compared with a conventional driver. Much of this is occupied by the reservoir capacitor. In current developments, this corresponds to an extra 0.01 mm2 to 0.02 mm2 per pad.

Even though this area is much smaller than that required by the external resistors of a conventional solution, delivering a substantial net size reduction in the end product, this overhead must be reduced if the IOD is to become generally accepted.

This is already happening, as thinner-oxide CMOS processes reduce the area required to achieve a given capacitance while also reducing the size of the drive transistors. In addition, the general drive toward miniaturization implies slowly decreasing load capacitance and will therefore call for a smaller reservoir capacitance.

Those complementary effects mean that the overhead to implement IOD on-chip is diminishing quickly.

The first silicon implementation of IOD, built on a 0.6-micron CMOS process, ran in October 2003 and achieved power savings of more than 50 percent in chip I/O. The next challenge is to make adiabatic circuit elements easy to integrate into otherwise conventional CMOS designs. Shrink-wrapped IP blocks compatible with familiar design tools, for example, would enable chip designers to gain adiabatic efficiency advantages quickly and cost-effectively.

Adiabatic logic could be the key to satisfying market demands for high functionality within the power limitations imposed by battery size and weight restrictions. Knowledge gained from this emerging generation could be pivotal in opening the door to extremely low energy, reversible computing in the future.