2019-01-21T12:53:30ZSensing Cell-Culture Assays with Low-Cost Circuitryhttp://hdl.handle.net/10261/172901
Título: Sensing Cell-Culture Assays with Low-Cost Circuitry
Autor: Pérez, Pablo; Huertas, Gloria; Maldonado-Jacobi, Andrés; Martín, María; Serrano, Juan A.; Olmo, Alberto; Daza, Paula; Yúfera, Alberto
Resumen: An alternative approach for cell-culture end-point protocols is proposed herein. This new technique is suitable for real-time remote sensing. It is based on Electrical Cell-substrate Impedance Spectroscopy (ECIS) and employs the Oscillation-Based Test (OBT) method. Simple and straightforward circuit blocks form the basis of the proposed measurement system. Oscillation parameters - frequency and amplitude - constitute the outcome, directly correlated with the culture status. A user can remotely track the evolution of cell cultures in real time over the complete experiment through a web tool continuously displaying the acquired data. Experiments carried out with commercial electrodes and a well-established cell line (AA8) are described, obtaining the cell number in real time from growth assays. The electrodes have been electrically characterized along the design flow in order to predict the system performance and the sensitivity curves. Curves for 1-week cell growth are reported. The obtained experimental results validate the proposed OBT for cell-culture characterization. Furthermore, the proposed electrode model provides a good approximation for the cell number and the time evolution of the studied cultures.2018-12-03T12:06:57ZOn Practical Issues for Stochastic STDP Hardware With 1-bit Synaptic Weightshttp://hdl.handle.net/10261/171863
Título: On Practical Issues for Stochastic STDP Hardware With 1-bit Synaptic Weights
Autor: Yousefzadeh, Amirreza; Stromatias, Evangelos; Soto, Miguel; Serrano-Gotarredona, Teresa; Linares-Barranco, Bernabé
Resumen: In computational neuroscience, synaptic plasticity learning rules are typically studied
using the full 64-bit floating point precision computers provide. However, for dedicated
hardware implementations, the precision used not only penalizes directly the required
memory resources, but also the computing, communication, and energy resources.
When it comes to hardware engineering, a key question is always to find the minimum
number of necessary bits to keep the neurocomputational system working satisfactorily.
Here we present some techniques and results obtained when limiting synaptic weights
to 1-bit precision, applied to a Spike-Timing-Dependent-Plasticity (STDP) learning rule in
Spiking Neural Networks (SNN). We first illustrate the 1-bit synapses STDP operation
by replicating a classical biological experiment on visual orientation tuning, using a
simple four neuron setup. After this, we apply 1-bit STDP learning to the hidden
feature extraction layer of a 2-layer system, where for the second (and output) layer
we use already reported SNN classifiers. The systems are tested on two spiking
datasets: a Dynamic Vision Sensor (DVS) recorded poker card symbols dataset and
a Poisson-distributed spike representation MNIST dataset version. Tests are performed
using the in-house MegaSim event-driven behavioral simulator and by implementing the
systems on FPGA (Field Programmable Gate Array) hardware2018-11-05T12:02:57ZOn-The-Fly Deployment of Deep Neural Networks on Heterogeneous Hardware in a Low-Cost Smart Camerahttp://hdl.handle.net/10261/171797
Título: On-The-Fly Deployment of Deep Neural Networks on Heterogeneous Hardware in a Low-Cost Smart Camera
Autor: Velasco-Montero, Delia; Fernández-Berni, J.; Carmona-Galán, R.; Rodríguez-Vázquez, Ángel
Resumen: This demo showcases a low-cost smart camera where different hardware configurations can be selected to perform image recognition on deep neural networks. Both the hardware configuration and the network model can be changed any time on the fly. Up to 24 hardware-model combinations are possible, enabling dynamic reconfiguration according to prescribed application requirements.2018-11-02T08:14:08ZOptimum Network/Framework Selection from High-Level Specifications in Embeddhttp://hdl.handle.net/10261/171796
Título: Optimum Network/Framework Selection from High-Level Specifications in Embedd
Autor: Velasco-Montero, Delia; Fernández-Berni, J.; Carmona-Galán, R.; Rodríguez-Vázquez, Ángel
Resumen: This paper benchmarks 16 combinations of popular Deep
Neural Networks for 1000-category image recognition and Deep Learn-
ing frameworks on an embedded platform. A Figure of Merit based on
high-level specifications is introduced. By sweeping the relative weight
of accuracy, throughput and power consumption on global performance,
we demonstrate that only a reduced set of the analyzed combinations
must actually be considered for real deployment. We also report the op-
timum network/framework selection for all possible application scenarios
de ned in those terms, i.e. weighted balance of the aforementioned pa-
rameters. Our approach can be extended to other networks, frameworks
and performance parameters, thus supporting system-level design deci-
sions in the ever-changing ecosystem of Deep Learning technology
Descripción: in Advanced Concepts for Intelligent Vision Systems (ACIVS), Poitiers, France, September 2018, ISBN 978-3-030-01448-3,2018-11-02T08:05:38Z