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High-Speed I/O

Aug 17, 2014

In the previous blog on PCB Insertion Loss and High-Speed Buses, we described how this loss increases with greater link speed. Designing for higher link speeds may, as a consequence, drive up PCB cost. This blog explains some techniques to mitigate this cost increase.

Jul 20, 2014

In Part 1 of this blog, we discussed some of the limitations of ICT, boundary-scan, and conventional functional test for testing memories. This Part 2 reviews methodologies that overcome these constraints.

Jun 22, 2014

In the article DDR4 Memory Timing Margining, we described more sophisticated DDR margining tests, which determine crosstalk coupling between aggressor channels, dwords (lanes 0-31), words, bytes and lanes. How can designers use these capabilities?

Jun 15, 2014

At their developers conference two weeks ago, PCI-SIG representatives talked about doubling the bandwidth of PCI Express 3.0, while still preserving channel runs of up to 20 inches, the length of the traditional server’s data path. How is this achieved?

Jun 08, 2014

In a previous blog, we touched on some of the key attributes of Intel QuickPath Interconnect versus PCI Express Gen3, to explain why the acceptable bit error rate threshold of Intel QPI is two orders of magnitude lower. This article elaborates on how some of the key design features of QPI contribute to this more stringent requirement.

Jun 01, 2014

Serial ATA (SATA)-based systems come in a wide range of topologies and trace/cable lengths. This presents signal integrity challenges due to signal loss, reflection and crosstalk; causing SATA device detection problems, lack of interoperability, slower performance, and increased radio frequency interference. What are the main issues, and how do designers mitigate them?

May 01, 2014

The Intel Cougar Point SATA bug. Adaptive equalization and power consumption. The sources of single-bit and multi-bit DDR3 and DDR4 memory errors. These are all topics which are top-of-mind for design and test engineers. And they’re key to designing and delivering high-speed designs which perform well in the field and have sufficient margin to withstand the rigors of real-world conditions.

ASSET’s new eBook, System Marginality Validation of DDR3 | DDR4 Memory and Serial I/O, describes a new software and embedded instrumentation-based methodology for validating overall system margins. This approach, System Marginality Validation, checks on the margins of a system as a whole, as opposed to simply measuring the signal integrity of one or two channels or lanes. It also easily takes into account silicon and circuit board defects and process variances, voltage, temperature, humidity and other effects, giving a level of confidence in a system’s performance and resistance to crashes, hangs, and “surprise link down” effects.

For more on the technology behind System Marginality Validation, click here.

Apr 27, 2014

The required Bit Error Rate (BER) of Intel® QuickPath Interconnect (QPI) is 1 error in 10E14 bits. The BER threshold of PCI Express is 1 error in 10E12 bits. What might account for the two orders of magnitude difference?