Power domain verification: Beyond traditional DRC, LVS and ERC

For many power domain issues, functional simulation can be performed successfully without catching the circuit error...

Is the world analog or digital? If you are an IC designer, you know that the answer to this, of course, is both. High performance processing, data transfer, and data storage are largely digital concerns, but interaction with the outside world requires communication (wired and wireless), interpretation of information from external sensors, and production or interpretation of audio and video inputs. Such a wide variety in circuit needs essentially means that there is no “one size fits all” for design styles and flows, even for circuits that exist on the same die.

To implement circuits with compelling functionality that addresses complicated market requirements, circuit designers must integrate a wide range of IP that satisfies communication, data processing, data storage, and interface requirements. For many years now, designers have been creating single-chip solutions that contain analog, RF, processor, memory, and other components that were previously discrete devices. Additionally, designers must address the growing concern of power consumption that is driven by battery life, cost, and heating/cooling concerns. Therefore, it should come as no surprise that modern IC designs are implemented with not one, but several, power domains to ensure that analog, digital, and power consumption requirements are met.

This evolution of circuit design incurs added complexity for circuit reliability. Analog blocks that operate with a VDD of 5V will not operate faithfully in regions where the power supply is less than that. Scarier still is that digital portions of the design could fail completely if they are connected inappropriately to high voltage regions.

Historically, reliability issues have been solved through simulation, which requires significant resources and experience, both to run and to interpret results. The problem with simulation today is two-fold. First, as design size increases, so does simulation time, making it a less attractive option for today’s massive designs. Second, for many power domain issues, functional simulation can be performed successfully without catching the circuit error. For example, if you connect a digital circuit to a high VDD, will circuit simulation or static timing analysis show you incorrect results? In many cases, the answer is no—the results from simulation will look reasonable, but if the circuit is manufactured with the high VDD power supply, the circuit will fail sometime out in the field. The question then becomes, without simulation, how can designers ensure the reliability of their designs?

What is needed is a scalable solution that can characterize the physical system and verify the design against known rules, avoiding all but the most essential simulations.

To understand the scope of the challenge, let’s discuss the verification of signals paths in multiple power domain designs. Low-power verification requires system knowledge and careful tracking of typically large numbers of power domains. In multiple power domain designs, system integration and IP reuse complicate circuit verification, due to the multiple connections between different domains. Design hierarchy and constraints must be considered when specific rules are applied on a top cell and/or pad frame, but other rules must be applied between blocks that cross multiple power domains. Tracking the rules and the nets to which they apply is by no means a trivial task when performed manually.

Power domain checking: Managing many power domainsMultiple power domains involve multiple on and off chip power supplies (Figure 1). What I’ll discuss is a top-down, comprehensive approach that validates design intent and ensures that your design is robust against circuit failure due to inappropriate use of power supplies.

The first step is to verify that your high-level design specification matches your circuit implementation. This is the time to catch errors early in the process. Errors found at this stage are usually easily corrected and there is plenty of time to implement the appropriate remedy. Most designers capture the power strategy for the circuit in a standard specification called a Universal Power Format (UPF) file. The UPF file defines the various power domains and identifies which circuits need to be implemented in those domains.

Calibre® PERC™ is one example of a tool that can perform this high-level verification by comparing the UPF specification with circuit-level schematics. It can validate that each circuit block is correctly integrated into the appropriate power domain. This initial verification is necessary, as it validates that high-level circuit blocks are operating in the appropriate power region. It also sets the stage for the next step in validating the connection between blocks between power regions.

Power domain checking: Level-shiftersWhen a design has a signal that goes from one power domain to another, designers need to ensure that level shifter circuitry is in place to connect circuits that use different voltage levels. Level shifter cells are critical for the proper implementation of power management, and their absence can result in functional failures. However, there may be several different circuit configurations that represent level shifters. Each configuration might have different performance characteristics, but often it’s simply that designers have their own favorite way of drawing a level shifter.

Level shifter verification must be able to recognize all of these configurations, and evaluate the design for the presence or absence of level shifter circuitry, as well as the correct configuration of the level shifter circuitry (Figure 2).

Figure 2. Level shifter verification between different power domains for various level shifter configurations.

Power domain checking: Voltage propagationAs a final step, and for complete verification, Calibre PERC can be used to check the voltages for every device in the design. Given that each new process node produces transistors with thinner and thinner gate oxides, this seems to be a prudent thing to do. Many designers are concerned about Electrical OverStress (EOS) in their designs, and analyzing the voltages for every device is a robust way of protecting circuits against EOS issues.

However, given that there are billions of transistors in a modern design, checking voltages for every single one seems impractical. It certainly can’t be done with circuit simulation. However, because Calibre PERC operates hierarchically, it has the performance and capacity necessary to reliably and automatically assign voltages to every net, node, device, pin, and transistor in the full-chip design, and then perform the appropriate analysis to validate that the assigned voltage is within specification for each circuit element.

Figure 3. Automated voltage assignment and validation

In summary, new tools are emerging to help designers solve circuit reliability issues in today’s massive and complex designs. Calibre PERC is one example of these new automated capabilities, including topology checking, UPF verification, and voltage propagation, that are needed to resolve reliability concerns that arise due to usage of multiple power supplies in modern circuits. Advanced reliability verification is now essential for reducing susceptibility to premature or catastrophic failures, while also providing the diagnostic insight that can help you improve yield and device reliability in future designs.

AuthorCarey Robertson is a Director of Product Marketing at Mentor Graphics Corp., overseeing the marketing activities for Calibre PERC, LVS and extraction products. He has been with Mentor Graphics for 14 years in various product and technical marketing roles. Prior to Mentor Graphics, Carey was a design engineer at Digital Equipment Corp., working on microprocessor design. Carey holds a BS from Stanford University and an MS from UC Berkeley. He may be contacted at carey_robertson@mentor.com.

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