Intel's 45nm 'Nehalem' processor architecture, due for release later this year, will see the chip maker adopt AMD's approach to cache structure: small per-core Level 1 and Level 2 caches connected to a big, shared Level 3 cache.
Nehalem, which will form the basis for two-, four- and eight-core processors, will contain 64KB of …

Cheater

If Intel claimed that they make the best processor, why do they have to borrow AMD cache plan for? Why don't they create their own architecture than using other architecture?And let see how well will they stand against the 45 Quad Shanghai, Deneb, Montreal, Suzuki, Bulldozer, and Sandtiger.

Borrowed?

If I buy one of these chips, what happens when Intel give the cache layout back?

Seriously, I would have thought that cache sizes and connectivity were pretty much determined by the speed of the cores, the plumbing joining them to the outside world, and the assumptions about typical workload. I also expect we've seen similar plans in the mainframe and RISC world. To accuse Intel of borrowing AMD's plan is a bit like accusing bats of pinching the idea of wings from the birds, oblivious to the fact that insects got there first.

I'm not saying Nehalem's design isn't newsworthy, but I do question the choice of language.

borrowed... really?

L3 shared cache is old intel server technology adopted by the K10m architecture (Phenom and Barcelona). so did intel really borrowed this from AMD?

borrowed/copied... here are some facts;

1. The use of a true 128-bit internal datapath. On previous CPUs based on K8 microarchitecture the internal datapath was of 64 bits only. This was a problem for SSE instructions, since SSE registers, called XMM, are 128-bit long. So, when executing an instruction that manipulated a 128-bit data, this operation had to be broke down into two 64-bit operations. The new 128-bit data path makes K10 microarchitecture faster to process SSE instructions that manipulate 128-bit data compared to K8 microarchitecture.

Intel processors based on Core microarchitecture (Core 2 Duo, for example) also have 128-bit internal datapaths , while Intel processors based on Netburst microarchitecture (Pentium 4 and Pentium D) have a 64-bit internal datapaths.

AMD is calling this new feature “AMD Wide Floating Point Accelerator”.

2. The fetch unit fetches 32 bytes (256 bits) of data per clock cycle from the L1 instruction cache – this is the double CPUs based on K8 architecture could fetch per clock cycle. Intel CPUs based on Core microarchitecture, like Core 2 Duo, also fetches 32 bytes per clock cycle.

3. K10 architecture adds a shared L3 memory cache (OLD INTEL SERVER CHIP TECHNOLOGY) inside the CPU... The size of this cache will depend on the CPU model, just like what happens with the size of L2 cache.