Who wants SOI sauce?

By Christine Evans-Pughe and Chris Edwards

Published Friday, July 4, 2008

At the beginning of October, a group of chipmakers and tools suppliers formed a consortium to try to take the technology of silicon-on-insulator (SOI) chips out of the realm of high-end processors into the mainstream.

The SOI Consortium launched with 19 members after two companies – wafer-maker Soitec and circuit-designer ARM – decided that it was time to give SOI a push. The companies ran a joint forum earlier in the year and, according to André Auberton-Hervé, CEO of Soitec, found that there was interest in forming some kind of consortium.

The other companies in the consortium have performed research into SOI or have based product lines on the technology. They include AMD, Freescale Semiconductor, IBM, NXP, Samsung, STMicroelectronics, TSMC and UMC. Design tools vendor Cadence Design Systems has joined, as have equipment makers KLA-Tencor, Lam Research and SEH Europe and SOI memory specialist Innovative Silicon.

Tom Lantzsch, vice president of marketing for libraries at ARM, said: “Our mission is to accelerate SOI innovation into broad markets. The transfer away from bulk silicon requires a collaborative effort. The next wave of adopters need access to a complete range of design platforms.

”Auberton-Hervé said the focus of the consortium’s push will be on consumer electronics. “SOI plays a role in meeting many of the key needs of consumers of electronics inside and outside the home. It is about meeting their power and heat dissipation needs. Consumers care about battery life so that they can duplicate their home entertainment experience on the road.”

Auberton-Hervé added: “The early adopters have proven that SOI is powerful. The community outside these first adopters is very attracted to what SOI can do but they want a better understanding of how to use SOI.”

The consortium plans to perform benchmarking exercises to demonstrate how SOI compares with bulk CMOS and to share best practices in the industry. But is the industry ready for SOI? Although there is plenty of interest in the technology and it could provide a solution to some of the problems of bulk CMOS, some of those who have joined the SOI Consortium are not quite ready to make the jump.

“We see SOI very much as a high-performance niche,” said Chuck Byers, director of brand management at TSMC. “Any new initiative like that requires our attention but we see it as a niche process. It certainly has a way to go. Are we developing it in-house? Absolutely. Are we joining industry consortiums? Yes. But we see it as a niche.”

René Penning de Vries, chief technology officer for NXP, said: “SOI is important at the high-performance end. But for plain vanilla, low-cost products, I doubt that it will be so important. It is an adder to the cost of a wafer.”

Andy Shen, senior director of brand management at TSMC, agreed: “This stuff is so expen­sive. That is a major issue. It is mainly the materials that add to the cost, but we are talking multiples more expensive.”

Shen claimed that adding SOI to a process would mean a change to the production tools needed in the fab, adding to its overall cost. “And there are training considerations. It is cost on cost on cost,” Shen claimed. “Although we have a small investigation team, most of our resources are focused on bulk CMOS. The performance advantage that SOI can claim, that can be compensated if TSMC can get to the next node quickly. And we see a pretty good life for bulk CMOS down to 22nm. We don’t see a barrier to stop us from making 22nm.”

However, TSMC has not ruled out making SOI and continues to research into the technology. Shen said: “If there are enough people coming along who want SOI, then TSMC will certainly support it.”SOI may prove useful in dealing with some of the problems with variability that bulk CMOS is beginning to experience. “Most probably, it will be that, at 32nm, the main push for SOI will be to reduce variability,” said Professor Asen Asenov of the University of Glasgow.

“Up to 45nm, the workhorse was conventional bulk CMOS,” said Asenov. “A CMOS transistor is electrostatically controlled by doping but variability increases with doping concentration. In the past this was to some extent compensated by scaling of the gate-oxide thickness. Then the oxide stopped scaling because it was becoming too thin to act as an effective insulator. And we have to compensate by doping more.

"For 32nm, people are talking seriously about using thin-body SOI now that companies realise that the major issue is variability,” added Asenov.

“The 32nm generation will be a pivotal node for semiconductor manufacturers because we are dealing with layers only a few atoms thick, where quantum mechanical effects become more and more important,” said Gilles Thomas, STMicroelectronics R&D co-operative programmes manager and co-ordinator of the EU-funded Pullnano project. The team is working on fully depleted SOI to deal with the problems of variability in sub-40nm processes.

One way in which SOI could help is by reducing the amount of doping that is needed to create an effective transistor channel. SOI transistors are more or less undoped. As a result, they do not suffer from the effects that heavily doped bulk CMOS transistors are beginning to exhibit as geometries scale down.

However, SOI is not immune to other sources of variability. For example, it is just as troubled by line-edge roughness – in which the transistor assumes an irregular, unpredictable shape caused by the interaction between light and the chemical resists used to define chip-level features. SOI could exacerbate some problems with smaller transistors, particularly in the high-performance end of the business where it has an edge. The biggest issue is with the electrons smashing into the crystal lattice as they are swept through the transistor channel. This imparts heat which needs to be dissipated quickly to prevent problems. Asenov said SOI tends to suffer more with this kind of self-heating.

Work by IBM researchers to be presented at the 2007 IEDM conference has indicated that most of the heat generated by E F the transistor passes through the gate rather than through the oxide substrate. The thermal conductivity of the gate stack and the interconnect is better than that of the oxide surrounding the drain and source areas.

One factor that has discouraged designers from looking at SOI for products other than ultralow-power or high-speed processors is that of dealing with the technology’s side effects. However, ARM reckons that the complexities of partially depleted SOI devices are now well understood and the technology is ready for use in ASIC design. Speaking at the SAME conference in Sophia Antipolis, France, Yves Laplanche, who works on IP improvements and design characterisation at ARM’s SOI technology group in Grenoble (formerly the company Soisic), said that ASIC designers who use properly characterised IP libraries will find designing for SOI no different from bulk CMOS.

Odd behaviour

Although isolating transistors from the silicon substrate provides a way of boosting transistor performance, the partially depleted SOI technology – the focus of most of today’s SOI activity – have introduced some new behavioural peculiarities, caused by a phenomenon known as the history effect.

The history effect is the result of a non-depleted region called the floating body that sits between the transistor and the insulated substrate and trap charges. These charges alter the body potential of the transistor and cause its threshold voltage to vary, and in turn alter the propagation delay. In other words, the propagation delay is no longer constant but depends on the transistor’s previous state. The floating body can also turn on the parasitic bipolar transistor contained in the partially depleted device. These novel effects change the way standard cells and memories need to be characterised and built.

Laplanche’s overall message was that there are complexities in SOI but they can be controlled in designs. “All variability can scare people,” he said, “But we’ve made it invisible. We have addressed the issues surrounding the history effect and so you can switch to SOI from the bulk library with no change in the tools.”

Test chips

In June, UMC and ARM announced they had taped-out a test chip with ARM’s SOI libraries on UMC’s 65nm process. Compared to a bulk CMOS device, the SOI design apparently saved 20 per cent in area and 30 per cent in power consumption.

Memory is another area of attention. “The companies looking at SOI are those working with memory,” said Asenov. AMD and Hynix are looking at using the ZRAM from Innovative Silicon as an alternative to existing memory technologies. The cost savings that result from a more efficient DRAM cell could provide the push that SOI needs.

Design techniques SOI tolerance

The unusual circuit properties of partially depleted silicon-on-insulator (SOI) demand special attention. However, it is possible to hide the so-called history effect.

Taking an inverter as a simple example, Yves Laplanche, who works on IP improvements and design characterisation at ARM’s SOI technology group, explained that the rise and fall propagation delays through an inverter differ depending on whether the inverter was previously in an idle state corresponding to a low input (zero) or a high input (one). Depending on the input signal shape, the propagation delays will converge to the same value and the inverter reach a steady state. In other words, the transistor behaviour varies between two boundaries.

But the history effect is known and predictable, said Laplanche, and the added delays are small compared to traditional variations and matching problems at 65 and 45nm. “In a chain composed of three inverters for an actual 45nm technology at 25C, the variations due to history effects are lower than 2 per cent whereas the process corners induce a variation of 15 per cent,” he explained.

Calculating the history effect for a larger number of states, such as those encountered in logic gates, is trickier. Laplanche’s group has evaluated the history effect ratio for different input configurations of a two-input NAND cell, which has four input states (00, 10, 01, 11). They have also calculated the propagation delay from one input pin to the output. Their figures indicate a low history effect ratio for both inputs of the NAND cell. They also show that the input pin can be selected to minimise its history effect variability. But a minimum history effect doesn’t apparently correspond to a minimum propagation delay.

The floating body has the biggest impact on SRAM cell design because the history effect is directly related to the information stored in the cell and any changes in it. It introduces a read current variation that depends on previous cell activity: the two extreme states are either a cell containing a zero state for a long time or a cell set to ‘one’ for a long time and just switched to zero before reading. It also affects the propagation delay in self-timing loops, which can lead to read errors due to wrong timing. And it lowers the sensitivity in the sense amplifiers. To help solve these issues, ARM is using body-tied devices to allow bulk-like matching behaviours, although at the expense of area and some performance.

During the SRAM writing process, the parasitic bipolar transistors of the cells’ pass gates can switch on. This happens in certain configurations, such as when all the cells in a row are high for a long time. The effect is to pull the bit-line up. To write a zero (low) on the bitline in such a configuration, SOI SRAM cells need to have a stronger write amplifier than usual to counterbalance the additional current from the parasitic transistors.

In the future, said Laplanche, technologies that exploit the history effect to create memory cells, such as the Innovative Silicon (ISi) ZRAM, may well come to replace SRAM. The ZRAM developed by ISi stores bits as charges on the gate of a conventional SOI transistor, so it does not need a separate capacitor in the way that existing dynamic random access memories (DRAMs) do. This reduces the amount of die area needed for the memory array compared with both DRAM and SRAM, which typically need four or six transistors per binary bit stored. Because the technology can be used with standard logic transistor structures, the company is concentrating on selling the ZRAM as an alternative to embedded DRAM and SRAM.

At the ESSCIRC conference in Munich in September, Hitachi fellow Kiyoo Itoh said a twin-DRAM cell could provide SRAM-like behaviour in low-power designs.

Which SOI do you want to use?

The form of silicon-on-insulator (SOI) technology used today is known as partially depleted. It is a product of the thickness of the silicon layer that lies underneath the transistor’s gate and above the silicon-dioxide insulator of the wafer’s body.

The term ‘partially depleted’ refers to the way that, when the transistor is turned off, not all of the carriers are removed from the silicon layer. The area directly underneath the gate will be clear, but there will be a layer of electrons or holes beneath. This leads to the floating-body effect, where the switching behaviour of the transistor – seen in a change in the threshold voltage – depends on the previous state of the transistor.

One way around the floating-body effect is to reduce the thickness of the channel. This is the idea behind fully depleted or thin-body SOI. Because the channel is so thin, all of the carriers should be removed from the channel when the device is switched off. However, today, there are very fully depleted devices in use.

In 2002, Oki Electric said it started to ship low-power devices based on a fully depleted transistor design. The main target was for comparatively slow devices, such as the processors used in wristwatches. For high-performance processors, partially depleted SOI remains the popular choice.

Although it gets rid of the history effect, the problem with thin-body, full depleted SOI is that it reduces the mobility of carriers in the transistor channel. This slows the device down, removing a lot of SOI’s speed advantage. Researchers from CEA-LETI may have found a way round this, by putting strained silicon into the ultra-thin channel of an experimental 18nm-gate transistor. Even with silicon film thicknesses as low as 2.5nm, the strained silicon improved performance by up to 40 per cent. The team will discuss the results at the upcoming IEDM conference.

Work with experimental devices at Toshiba and the University of Tokyo has agreed with the CEA-LETI findings: that strain can improve performance even in the thinnest silicon channels. It worked even in a device that was just 1.8nm thick. Strain-silicon formed the basis of a project undertaken by members of the European Union-sponsored project Pullnano, although the focus was on producing what they claimed is the smallest SRAM cell to be developed so far on an SOI process.

Like the CEA-LETI researchers, the Pullnano team used an ultra-thin body, fully depleted transistor design coupled with a metal gate and high-k gate dielectric. The first SRAM cell produced using the Pullnano design measures 0.248µm2, about the same size as one produced by UMC on a 45nm bulk CMOS process last year. But the team worked on scaling the cell down to hit 0.179µm2.

The body of the transistor is 10nm thick and the gate stack uses a combination of a hafnium-based dielectric – similar to the dielectrics that are to be used by those manufacturers who have made the jump – with a titanium nitride/polysilicon electrode. The team used the same strain techniques as those employed for a 45nm predecessor process based on bulk silicon wafers.