dual-edge sensitivity

I'm trying to use both edges of my clock signal to count for a clock divider using VHDL. Behaviorally, the simulation works, but it won't synthesize. I'm using a Xilinx Spartan-3e FPGA. I tried it in Verilog and I'm getting the same results. Is this something that VHDL is not allowing me to do or is it my FPGA? Here's an example:

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You are trying to clock a flip flop on both edges, I don´t think that is possible with any Xilinx FPGA.
Spartan 3 has a DCM (Digital Clock Manager) that can divide the clock for you. Search the home page for application notes.

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You can never use both edges of a clock in the same process for a synthesizable design. You must create 2 seperate processes with one using a rising_edge and the other the falling_edge. I'm not sure why you would ever need to count both edges since if you count one you essentially double it to indicate that you have counted both. You might want to explain a little better what you're tying to accomplish.

It is possible to use the high & low levels of the clock to possibly mux different data onto the same line to double throughput speeds. I would recommend simply doubling the clock speed in this case though for a more precise design.

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