Automated solution enables effective testing of 3d stacked ICs

A new generation of super chips could become a reality following imec's collaboration with Cadence to deliver an automated solution for testing 3d stacked ICs.

According to the Belgian research institute, the partnership will provide the design for test (dft) and automatic test pattern generation (atpg) technology to make it easier to test 3d ICs with 'through silicon via' (tsv) functionality. The 3d dft architecture is based on the concept of die level test wrappers and will enable the testing of chips with tsvs at all three stages of stacking.