Preview

Features

Includes a comprehensive study of state-of-the-art communication architectures for SoC

Offers a practical review of industry standards and manufactured implementations

Surveys more recent approaches and technologies to convey industry developments and trends

Presents case studies to aid designers’ conception of new architectures

Provides chapter-end conclusions, glossaries, bibliographies, and a list of references

Summary

A presentation of state-of-the-art approaches from an industrial applications perspective, Communication Architectures for Systems-on-Chip shows professionals, researchers, and students how to attack the problem of data communication in the manufacture of SoC architectures.

With its lucid illustration of current trends and research improving the performance, quality, and reliability of transactions, this is an essential reference for anyone dealing with communication mechanisms for embedded systems, systems-on-chip, and multiprocessor architectures—or trying to overcome existing limitations. Exploring architectures currently implemented in manufactured SoCs—and those being proposed—this book analyzes a wide range of applications, including:

Well-established communication buses

Less common networks-on-chip

Modern technologies that include the use of carbon nanotubes (CNTs)

Optical links used to speed up data transfer and boost both security and quality of service (QoS)

The book’s contributors pay special attention to newer problems, including how to protect transactions of critical on-chip information (personal data, security keys, etc.) from an external attack. They examine mechanisms, revise communication protocols involved, and analyze overall impact on system performance.

Editor(s) Bio

Jose L. Ayala got a M.S. in Telecommunications Engineering from Politecnica University of Madrid in 2001, and a M.S. in Physics from the Open University of Spain in 2002. After that, he pursued his Ph.D on Electronic Engineering at the Department of Electrical Engineering of the Politecnica University of Madrid. He is currently an Associate Professor at the Department of Computer Architecture of the Complutense University of Madrid.