Tom,
In answer to your question about hardware with disparity control,
"some yes and some no". Some hardware will have the ability to
send/receive patterns with defined disparity. Hence, publishing
the preferred 10-bit pattern (in the style of the MJS Annex B ?)
would improve the odds that everyone is using the same pattern.
Regards,
Mike
"Lindsay, Tom" wrote:
>
> Hi Mike -
>
> As always, you understand all quite well.
>
> I do not know what control there can be in disparity. In terms of the
> document, I would like to add a statement along the lines of "For jitter
> and other compliance testing with this pattern, it is recommended that
> all lanes begin with negative running disparity and that the IPG be
> strictly controlled as shown."
>
> Since this is a test mode, it should be possible to "jump" disparity
> without upsetting too much. I suspect, however, that most folks probably
> don't have that level of control in their silicon?? (that is a
> question).
...
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