Besides x86 and x86-64 architectures, coreboot support also exists for the AMD Geode solutions. Support started with the Geode GX processor developed by AMD for the OLPC, Artec Group then added Geode LX support for its model DBE61 ThinCan. Recently, that code was adopted by AMD and further polished for the OLPC after they upgraded to the Geode LX platform. That code is now being further developed by the coreboot community to support other AMD Geode solutions. Coreboot can be flashed onto an AMD Geode platform using Flashrom.

From that initial development on AMD Geode based platforms, coreboot support has been extended onto many AMD processors and chipsets. The processor list includes Family 0Fh and 10h (K8 core), and recently Family 14h (Bobcat core, FusionAPU). Coreboot support also extends to AMD chipsets: RS690, RS7xx, SB600, and SB8xx.

Coreboot typically loads a Linux kernel, but it can load any other stand-aloneELF executable, such as iPXE, gPXE or Etherboot that can boot a Linux kernel over a network, or SeaBIOS[14] that can load a Linux kernel, Microsoft Windows 2000 and later, and BSDs (previously, Windows 2000/XP and OpenBSD support was provided by ADLO[15][16]). Coreboot can also load a kernel from any supported device, such as Myrinet, Quadrics, or SCI cluster interconnects. Booting other kernels directly is also possible, such as a Plan 9 kernel. Instead of loading a kernel directly, coreboot can pass control to a dedicated boot loader, such as a coreboot-capable version of GNU GRUB 2.

Coreboot is written primarily in C, with a small amount of assembly code. Choosing C as the primary programming language enabled easier code audits, which result in improved security. The source code is released under the GNU GPL version 2 license.

Coreboot performs the absolute minimal amount of hardware initialization and then passes control to the operating system. As a result, there is no coreboot code running once the operating system has taken control; in particular, System Management Mode (SMM) is not activated.[17] A feature of coreboot is that the x86 version runs in 32-bit mode after executing only ten instructions[18] (almost all other x86 BIOSes run exclusively in 16-bit mode). This is similar to the modern UEFI firmware, which is used on newer PC hardware.

By itself, coreboot does not provide BIOS call services. The SeaBIOS payload can be used to provide BIOS calls and thus allow coreboot to load operating systems that require those services, such as Windows 2000/XP/Vista/7 and BSDs. However, most modern operating systems access hardware in another manner and only use BIOS calls during early initialization and as a fallback mechanism.

The most difficult hardware that coreboot initializes is the DRAM controllers and DRAM. In some cases, technical documentation on this subject is NDA restricted or unavailable. RAM initialization is particularly difficult because before the RAM is initialized it cannot be used. Therefore, to initialize DRAM controllers and DRAM, the initialization code may have only the CPU's general purpose registers or Cache-as-RAM as temporary storage.

romcc, a Ccompiler that uses registers instead of RAM, eases the task. Using romcc, it is relatively easy to make SMBus accesses to the SPD ROMs of the DRAM DIMMs, that allows the RAM to be used.

With newer x86 processors, the processor cache can be used as RAM until DRAM is initialized. The processor cache has to be initialized into Cache-as-RAM[19][20] mode as well, but this needs fewer instructions than initializing DRAM. Also, the Cache-as-RAM mode initialization is specific to CPU architectures, thus more generic than DRAM initialization, which is specific to each chipset and mainboard.

Since coreboot must initialize the bare hardware, it must be ported to every chipset and motherboard that it supports. Before initializing RAM, coreboot initializes the serial port (addressing cache and registers only), so it can send out debug text to a connected terminal. It can also send byte codes to port 0x80 that are displayed on a two-hex-digit display of a connected POST card.

Another porting aid is the commercial "RD1 BIOS Savior" product from IOSS,[21] which is a combination of two boot memory devices that plugs into the boot memory socket and has a manual switch to select between the two devices. The computer can boot from one device, and then the switch can be toggled to allow the computer to reprogram or "flash" the second device. A more expensive alternative is an external EPROM/flash programmer.

There are also CPU emulators that either replace the CPU or connect via a JTAG port, with the Sage SmartProbe[22] being an example. Code can be built on, or downloaded to, BIOS emulators rather than flashing the BIOS device.

^"As an innovator in embedded networking solutions, AMD is proud to collaborate with Deciso to offer a new open source firewall alternative," said Scott Aylor, corporate vice president and general manager, AMD Embedded Solutions. "The AMD Embedded G-Series SOC enables Deciso to deliver an ultra-low power design for the new OPNsense firewall appliance, without comprising performance and stability." "Deciso delivers new open source turnkey firewall alternative". PR Newswire. January 9, 2015. Retrieved 1 March 2015.