I'm starting to finally add various Tube devices to the BBC Micro range. These are 2nd processors that can be added and the official Acorn devices include 6502, 65C102, Z80, 32016, 80186, 80286, ARM. They (parasite) communicate with the BBC Micro (host) via a Tube ULA (Ferranti and later Acorn). The Tube ULA is fairly well documented and I've added this as a new machine device (tube). When working we'll be able to promote some machines to working bbcmt, bbcm512 and support the currently not supported software lists bbc_flop_6502, bbc_flop_z80, etc.

So far I have 6502 and almost 65C102 working, just need to check interrupts are fully handled between host and parasite CPU's.6502 2nd Processor:The Z80 is in progress but I'll come back to that later.

I need a little advice on the 80186. The Tube device has 8 registers to be addressed from the parasite CPU. The 8-bit CPU's map these consecutively so I have handlers parasite_r, parasite_w and for the Z80 are addressed:

Is there a way to map my 8 registers into even locations only, ie. 0x80, 0x82, 0x84, 0x86, 0x88, 0x8a, 0x8c, 0x8e. Or should I just create another set of handlers in my tube_device, parasite_x86_r, parasite_x86_w?

Is there a way to map my 8 registers into even locations only, ie. 0x80, 0x82, 0x84, 0x86, 0x88, 0x8a, 0x8c, 0x8e. Or should I just create another set of handlers in my tube_device, parasite_x86_r, parasite_x86_w?

That's right, I think. Using a 0xff mask will map it into the even addresses on a little endian machine like the 80186.

The error message about the input line queue means the 65c102 isn't servicing and lowering the interrupts fast enough. You may need a higher MCFG_QUANTUM() value if the 65c102 is otherwise hooked up correctly.

The error message about the input line queue means the 65c102 isn't servicing and lowering the interrupts fast enough. You may need a higher MCFG_QUANTUM() value if the 65c102 is otherwise hooked up correctly.

Thanks, though I more suspect that I need to implement some timing in my new tube_device, will come back to it later.

The 65C102 is now running, though with known interrupt issues:

The Z80 is also fully implemented with no known issues. It runs Acorn CP/M from the softlist and Colossal Cave:

From that schematic, Timer 0 toggles the HOLD pin (and appears to have something to do with the DRAM refresh, similar to one of the timers on PCs) and Timer 1 produces NMIs either on the 80186 or the host system via the Tube chip depending how a jumper is set. (The schematic shows it in the "on the 80186" position).