On Mon, Jul 20, 2009 at 08:47:47AM -0700, steven mosher wrote:
> A while back Wolfgang mentioned that he and I were starting a new venture.Drop
> by and say hello.
Congratulations on getting there!
>http://www.qi-hardware.com/
LOL. My first thought was "quarter-inch hardware". :-)
I suspect many of the people attracted by the hardware keyboard of the
ben-NanoNote will be looking to replace the 320x240 screen with a 640x480
screen. That would also make it comply with the 80x24 character terminal
size prescribed in the Linux kernel coding style.
I was going to ask how many hours of kernel compilation the battery lasts
for, but 32 MB is on the short side for that.
People can go on for eons about the choice of CPU. My only real gripe
with the MIPS is the lack of a register+register addressing mode. Apart from
that, it an anonymous RISC architecture.
The PowerPC has the rlw(i)nm(i) "rotate left word (immediate) and mask(ed
insert)" swiss army knife kind of instruction that you wouldn't expect to find
in a RISC architecture. But it executes in one cycle, so who gives a damn?
Pre-update addressing is available.
The PA-RISC has only rotate right instructions and one of the least readable
sets of instruction mnemonics I've seen.
The Alpha was an early adopter of a 64-bit word size that still hasn't shown
a major advantage over 32 bits.
The Sparc has windowed registers and delayed branches. Try showing a loop
disassembly where the loop counter is incremented after the branch to
someone who doesn't know about delayed branch instructions. :-)
The ARM is the odd man out: Predicated execution, an implicit shift/rotate
in most instructions, complex addressing modes including
auto-increment/decrement and only 16 general purpose registers where 32 is
the norm. Probably a good match for an assembler level programmer with
an m68k background.
The average Python scripter will be unaware of any such differences.
--
Rask Ingemann Lambertsen
Danish law requires addresses in e-mail to be logged and stored for a year