The research activity is focused on the identification of high efficiency (and compatibly low distortion) power amplifier design strategies for radar, satellite and communication applications.

Different design solutions have been investigated and developed to design high efficiency power amplifiers (PAs) based on harmonic turning strategies and architectures to further increase the average efficiency when complex modulated signals are adopted.

In the former approaches, a major effort from the designer is dedicated to the choice and realization of suitable harmonic terminating schemes, with the general philosophy to minimize the dissipated dc power on the active device while appropriately shaping the current and/or voltage waveforms: in particular, maximum output voltage must occur at low (or zero) current levels and maximum current corresponding at very low voltages.

Starting from a simplified model for the active device and reviewing the power balance conditions, the PAs design strategies have been identified and classified unifying their theoretical approach.

Closed-form expressions are derived for the major design quantities, together with the optimum fundamental and harmonics loading of the active device.

A comparison is carried out and useful design criteria are inferred for the design of input and output networks of high efficiency/high frequency power amplifiers.

The developed high efficiency design methodologies have been adopted to design several PAs, based on GaAs or GaN devices in both hybrid or monolithic versions.

Moreover, to account for the actual requests for PAs able to operate in different standards and frequency applications, the harmonic tuning strategy has been extended for the design of multi-band PAs.

In this context, it has been developed a theory and the corresponding design relationships to synthesize multi frequency and multi harmonics passive matching networks, aimed to implement the HT strategy realizing concurrent PAs.

Recently, major efforts have been dedicated to the identification of architecture to improve the efficiency performance achievable from a PA involved in systems with high peak-to-average power ratios, as for instance in WCDMA or UMTS applications.

In this case, due to the large input signal dynamic range, even if harmonic tuning design approaches can increase the stand-alone PA performance, it becomes mandatory to operate at a system level also. As a consequence, some "old" solutions have been recently resurrected to overcome the drawbacks related to these kind of signals. In particular, two main strategies have been revisited, namely the Doherty (DPA) and the Envelope Tracking techniques. The former exploit the concept of a dynamic load while the latter of dynamic bias conditions, both with the aim to force the amplifier stage to work at maximum efficiency levels for a predefined input dynamic range.

Regarding the Doherty amplifier, a new simplified theory to analyze its behavior and to infer useful design guidelines have been developed, assuming for the Main amplifier a class AB bias condition, while for the Auxiliary amplifier a Class C bias condition.

The developed theory has been validated throughout the realization of several DPA amplifiers based on GaN.

The DPA synthesis relationships have been further extended to account for different biasing conditions, harmonic tuning strategies and iinovative architecture have been developed and patented.

Several demanding applications require microwave and millimeter-wave receiving front-ends featured by extremely low noise performance. Among them, the focus has been posed on two different areas: receivers for satellite communications and the cryogenic low noise receivers for radio-astronomy applications.

Referring to the former one, high interest is actually in the extension of satellite communication payloads to the millimeter-wave frequency range, where a wider bandwidth is available, bringing in a larger set of potential services and capabilities. To this goal, a primary target consists then in the design and realization of compact and broadband low noise amplifiers, featured by state-of-the art performance. The accomplishment of the given specifications is then realized by using high-performance technologies: in the present case, a 70nm HEMT metamorphic technology has been adopted, featured by monolithic realization of a complete set of passive components. The result has been the design and the realization of amplifying chips featured by 30 dB gain all over the complete Ka Band and over (25-50GHz) with less than 1.5 dB noise figure. The amplifiers are going to be mounted and characterized for on-carrier operation, for subsequent potential use in satellite payloads.

Regarding Radio-astronomy applications, the interest has been posed on the realization, in monolithic form, of an integrated receiver, to form a focal plane array in the focus (primary or secondary one) of large aperture antennas. This approach allows the multi-beam operation and the versatile use both in frequency and pointing of large radio-astronomy antennas. In close cooperation with the Istituto di Radio Astronomia (IRA-INAF), a complete chip-set for signal low noise amplification, amplitude digital control (4 bits/6 bits), phase digital control (6 bits) has been designed realized and tested. The measured results, obtained utilizing OMMIC foundry and covering the 4 - 8 GHz Broadband operation of the single functions demonstrate remarkable performances, consisting in 1 dB noise figure (room temperature, OFB), 30 dB Gain, good i/o matching for the LNA. Buffered attenuation and phase shifting characteristics well agrees with expected performances. All the system components will be cooled to 20 K (LNA) or to 70 K (Phase and amplitude control). The former exhibits, at 25 K room temperature, the remarkable performance of 8 K equivalent noise temperature.

In addition, to move towards higher frequencies and make use of the new facilities that will be available at the radio-astronomy institutes around the world (e.g. the new SRT, Sardinia Radio Telescope), a W band amplifier has been designed and realized, featured by 20 dB gain all over the operating bandwidth (75-110 GHz) and less than 3 dB noise figure at room temperature. Cryogenic (20K) characterization is under way. More recently, as part of the FP7 Project RadioNet, investigations are being carried out regarding high density millimeter-wave multi-pixel cameras operating at cryogenic temperatures (Apricot JRA).

Development of circuital models and design procedures for microwave and millimeter waves MEMS components

G. Bartolucci

The research activities have been essentially focused on the high frequency microelectromechanical system (MEMS) components. More in detail, a first topic of the developed research activity is the mechanical modeling of MEMS capacitive shunt connected devices realized in coplanar waveguide technology.

Another aspect of the microelectromechanical structure behavior which has been investigated is the presence of non linear effects in a typical MEMS element excited by a high power RF signal: an analytic approach quite different from the conventional ones previously proposed in literature has been adopted.

Recently the research activity has been also partially devoted to the development of a novel design procedure for RF MEMS switches. The chosen configuration is composed by two transmission line sections separated a metal membrane providing a shunt connected capacitor. By means of a bias voltage it is possible to actuate the switch and therefore to change the capacitance value. A rigorous analytic circuital model based on the image parameter representation of a two port network has been developed for such a structure. Closed form equations have been presented and design considerations have been discussed. The result is a new methodology for the synthesis of microelectromechanical capacive switches in shunt configuration more general rigorous and efficient than those ones presented in previous papers.

Investigation on the more suitable technologies to register human body movements in 3D space with great spatial accuracy is a very challenging task, because a wide range of applications are concerned, from registration of post-stroke rehabilitation or sports performance, to monitoring of movement of disabled or elderly people, only to give some examples. The possibilities offered by piezoresistive bend sensors applied as wearable devices integrated on body garments are explored. Piezoresistive sensors can be usefully adopted to recover human joint bend angles for body movement tracking. Due to their pliability, sensitivity and cheapness, they could be a valid alternative to movement analysis systems based on optoelectronic devices or inertial electronic sensors. This research suggests a new approach to model their electrical behavior during bending and extension movements, in order to predict their real-time performance during different kind of applications. To simulate the sensor electrical behavior with no mind to its physical characteristics, simple and accurate behavioral models were developed, based on RLC resonant circuits and fitted on the sensor electrical response under fast bending and extension movements. The extracted models are applied to simulate and evaluate the sensor behavior in tracking human movements, such as knee rotations of walkers and runners.

Organic and nanostructured devices have been investigated, realized and simulated. Organic solar cells have been realized by using both a multilayer technology on ITO substrate. Both Graetzel and all-organic type cells

have been fabricated and characterized. Several techniques have been used for

encapsulation of the devices. All-plastic thin film transistors (OTFT) have been obtained via peeling techniques using contact electro-polymerization. Pentacene has been used as organic semiconductors. Carbon Nanotubes have been used to realize nanotriodes based on field emission. Several simulators have been developed to describe and optimize the behavior of organic devices

and nanostructures. A Green's functions based tool has been optimized to describe transport in carbon nanotubes and other molecular electronic devices. A new multiscale tool "TiberCAD" has been developed to describe transport in 1D/2D/3D organic devices.

Several simulators have been used and/or developed to simulate the behavior of electronic and optoelectronic devices. Finite Element simulations have been

used to to study the electrical characteristics of GaN-based HEMTs. In particular we have optimized GaN based HEMTs with respect to frequency and power. Both electronic and optical properties of the nanonostructure has been calculated by means of k.p and tight-binding methods. A combined 3D drift-diffusion + strain simulator has been developed and implemented withing the TiberCAD simulator. The photoconductance method has been used to study the channel temperature in both GaAs and GaN based HEMTs.

In this research different techniques for the implementation of high speed and low power architectures for DSP are faced. The research investigates mainly the use of non-conventional number representations in order to obtain high speed and low power systems. The main topic is the use of the Residue Number System (RNS) and, in particular regards the input and output conversion blocks in fact, the Binary to RNS and the RNS to Binary converters, are bottlenecks in the implementation of high-performance RNS based DSP architectures.

In this research some new architectures for the output conversion have been developed. These architectures show some important implementation advantages. Moreover, the new techniques are interesting from the theoretical point of view. In fact, the new method generalizes the algorithms presented in the literature. In terms of the application of the RNS to subsystems, at present, the research has been focused on the simulation and development of complex coefficients FIR filters and polyphase filter banks based on the QRNS (Quadratic Residue Number System) arithmetic.

Another aspect of the research is the development of processing platform based on reconfigurable devices. The research analyzed the possibility to use this platform in autonomous radio for space application. The idea is to have a reconfigurable radio, able to adapt its communication standard to the divers rovers presents in a planet surface. A special high resolution DDS was also developed.

We also studied and developed a simulator for the study of radar based on compressive sampling. Compressive sampling is a new method that reduces the radar analog interface complexity (in particular the stages for IF conversion and the ADC) for special class of signals (called “sparse signals). This technique is very promising for the production of future radars.

A last topic considered in this research area is the design of hardware and mixed (hardware and software) architectures for crypto systems. In this frame we developed a set of architectures for communication and video flows.

Reduction of the power consumption is today one of most critical tasks for a DSP system designer. We faced this issue considering the effects on power consumption of the arithmetic operators. We considered different methods to reach these objectives

The use of alternative number systems in the implementation of application specific processors has gained a remarkable importance in recent years because of the lower power consumption over their traditional (e.g. two's complement) counterparts. The renewed success of the Residue Number System (RNS) is mainly related to the low power requirements, but also to the availability of hardware platforms, such as FPGAs, particularly suitable for the implementation of RNS arithmetic blocks. Techniques to implement RNS operations are often based on look-up tables, which are the basic blocks to instantiate combinational logic in FPGAs. As the research shown, similar advantages are also obtained for ASIC technology.

In some DSP systems, output errors can be well tolerated in some mode of working. For this reason we can propose arithmetic operator with imprecise computation but very simplified structure. These operators are also characterized by a very reduce power consumption.

The idea of this research started with the observation that also in high performance systems, simple operations that are frequently repeated can produce performance degradation. This is related to the methods used for the optimization of the microprocessors and DSPs. Their architectures are focused to an efficient implementation of the most expensive operation as, for example, additions and multiplication, while the less common or less expensive operations are not implemented in hardware. As a consequence we have that simple operations not included in the original architectures produce a significant degradation of the performance. As an example we can cite operations that use a reduced number of bits (with respect to the native processor wordlength) or operations that don’t use each bit in the same way (considering two operands, some bits are xored, other bit are anded). The implementation of this operation is very inefficient for the scarce flexibility of the hardware operators. Our goal is to improve the performance (as speed and power consumption) of the processor accelerating these “simple” operations.

A possible solution for achieving the goals is the introduction of a reconfigurable hardware that is able to adapt itself to the specific operations required by the algorithms. This hardware is indicated as Reconfigurable Unit (or RU). In this way in the program we can mix conventional operations (those belonging to conventional Instruction Set , IS, of the processor) with special operations (i.e. operations implemented in the RU after the proper reconfiguration). In our work we consider the following constraints for the RU.

1) It must implement very simple operations

2) Each operation must be performed in a single or few clock cycles.

3) Its hardware complexity must be very low (if compared to the processor complexity). One of the most important task in the design of an efficient architecture based on a processor + a reconfigurable unit, is the definition of a suitable interfacing mechanism between these two resources.

With the integration of Hardware Accelerators in a standard microprocessor it’s possible to obtain a reduction of the microprocessor energy consumption with a significant performance improvement.

In this research is focused on the various signal processing techniques used to realize different kinds human-machine interfaces.

In the last years we focused our attention on brain-computer interface. A brain-computer interface allows a person to transfer thoughts and commands to a computer directly. Instead of using a keyboard, mouse, light pen or other input device, a user of such an interface simply thinks his or her commands and the computer responds to them.

Some of the latest work involves hooking a user up to electroencephalography sensors (better known as EEG sensors) that are connected to a computer on one end and the user's head on the other. The user wears a kind of cap with sensors on it designed to capture brain activity, and the interface measures the subject's brain responses and sends the information to a computer running a particular application such as a text input program.

We developed different methods for the processing EEG signals in order to extract the useful information. Moreover we developed a system for the acquisition of the brain signals stimulated by blinking lights and for controlling the different options in a menu.