RISC-V is a new instruction set architecture (ISA) designed to be scalable for a wide variety of applications. Open-sources and easy to implement, it has been named the ISA for and by the people, free of those pesky licensing fees that can weigh heavy upon BOMs.

Every embedded motor control solution contains hardware and software. And as motor control solutions are closely connected to mechanics and typically have a long product lifetime, they require much more reliable microcontroller platforms than for example user interfaces. ARM has been a reliable, stable and powerful platform over the past years. But the tendency towards consolidation of manufacturers offering M-Series ARM-controllers and the licensing model call for a new, open instruction set controller type to assure long-term availability and development.

ARM and x86 are the two leading architectures dominating the industry, followed by ARC, MIPS, Power, and Tensilica. All other ISAs are obsolete by now – either taken over by bigger ones, or simply didn’t make the cut. As a result, valuable time and money invested in the other ISAs and products using those ISAs are written off.

This doesn’t mean that the survivors of the consolidation phase are safe. If anything, Broadcom’s 130 billion USD bid to take over Qualcomm has shown that publicly traded companies can easily be subject to takeovers. So, who’s to say when the next ISA owned by a public company disappears? Sure, this won’t happen overnight, but the risk is always there.

Que RISC-V. Easy to implement, the reduced instruction set computer (RISC) set to become a standard open architecture – governed by the RISC-V foundation – for industry implementations, mitigating the risk of depending on a few manufacturers.

As with everything open source, everyone can join in to help evolve processor IP cores – which is why RISC-V has the potential to become the industry standard. It can be implemented in almost any FPGA and Microsemi states that RISC-V beats other soft-core processors such as the ARM Cortex M1, NIOS II/EF and MicroBlaze. Regardless of its performance (2.01 CoreMark/MHz), the biggest benefit is that RISC-V is open source – poised to develop faster than licensed ISAs and protected against takeovers that might make it obsolete.

Using Microsemi’s FPGAs with RISC-V cores, we’ve joined the cause – developing motor and motion control solutions that will stay available.