Design and characterization of low power and low noise truly all-digital clock and data recovery circuit for SERDES devices

Abstract

This paper presents a true all-digital referenceless mixed FLL/DLL quarter-rate clock and data recovery (CDR) circuit for SERDES devices. Key circuit blocks include a quarter-rate frequency detector, a quarter-rate phase detector, an eight-phase signal generator, and a low-jitter digitallycontrolled oscillator (DCO). The circuit is referenceless operating at an internally generated signal with a frequency equal to one-fourth of the incoming data rate. It can achieve phase and frequency detection at a PRBS data stream as well as inherent 1-to-4 demultiplexing. Though, there exists few numbers of dual-loop fractional rate CDR circuits, however the proposed circuit is entirely digital, synthesizable from a Verilog hardware description language and hence requires no filter, analog or off-FPGA components. Furthermore, a Verilog-based description of the circuit makes it easy to implement on various FPGA platform as well as an integrated circuit with inconsiderable modification. The design has been synthesized and implemented on the Altera DE2-70 development board. The CDR achieves BER lower than 10-12 (using bathtub plot), consumes 590-W power while operating at 167.5 Mb/s, the tracking range of the CDR corresponds to 167.32 Mb/s to 193.6 Mb/s data range. The measured RMS and peak-to-peak jitters of the recovered clock are 47.3 ps and 297 ps, respectively, at 167.5 Mb/s and 223-1 PRBS input stream.

title = "Design and characterization of low power and low noise truly all-digital clock and data recovery circuit for SERDES devices",

abstract = "This paper presents a true all-digital referenceless mixed FLL/DLL quarter-rate clock and data recovery (CDR) circuit for SERDES devices. Key circuit blocks include a quarter-rate frequency detector, a quarter-rate phase detector, an eight-phase signal generator, and a low-jitter digitallycontrolled oscillator (DCO). The circuit is referenceless operating at an internally generated signal with a frequency equal to one-fourth of the incoming data rate. It can achieve phase and frequency detection at a PRBS data stream as well as inherent 1-to-4 demultiplexing. Though, there exists few numbers of dual-loop fractional rate CDR circuits, however the proposed circuit is entirely digital, synthesizable from a Verilog hardware description language and hence requires no filter, analog or off-FPGA components. Furthermore, a Verilog-based description of the circuit makes it easy to implement on various FPGA platform as well as an integrated circuit with inconsiderable modification. The design has been synthesized and implemented on the Altera DE2-70 development board. The CDR achieves BER lower than 10-12 (using bathtub plot), consumes 590-W power while operating at 167.5 Mb/s, the tracking range of the CDR corresponds to 167.32 Mb/s to 193.6 Mb/s data range. The measured RMS and peak-to-peak jitters of the recovered clock are 47.3 ps and 297 ps, respectively, at 167.5 Mb/s and 223-1 PRBS input stream.",

N2 - This paper presents a true all-digital referenceless mixed FLL/DLL quarter-rate clock and data recovery (CDR) circuit for SERDES devices. Key circuit blocks include a quarter-rate frequency detector, a quarter-rate phase detector, an eight-phase signal generator, and a low-jitter digitallycontrolled oscillator (DCO). The circuit is referenceless operating at an internally generated signal with a frequency equal to one-fourth of the incoming data rate. It can achieve phase and frequency detection at a PRBS data stream as well as inherent 1-to-4 demultiplexing. Though, there exists few numbers of dual-loop fractional rate CDR circuits, however the proposed circuit is entirely digital, synthesizable from a Verilog hardware description language and hence requires no filter, analog or off-FPGA components. Furthermore, a Verilog-based description of the circuit makes it easy to implement on various FPGA platform as well as an integrated circuit with inconsiderable modification. The design has been synthesized and implemented on the Altera DE2-70 development board. The CDR achieves BER lower than 10-12 (using bathtub plot), consumes 590-W power while operating at 167.5 Mb/s, the tracking range of the CDR corresponds to 167.32 Mb/s to 193.6 Mb/s data range. The measured RMS and peak-to-peak jitters of the recovered clock are 47.3 ps and 297 ps, respectively, at 167.5 Mb/s and 223-1 PRBS input stream.

AB - This paper presents a true all-digital referenceless mixed FLL/DLL quarter-rate clock and data recovery (CDR) circuit for SERDES devices. Key circuit blocks include a quarter-rate frequency detector, a quarter-rate phase detector, an eight-phase signal generator, and a low-jitter digitallycontrolled oscillator (DCO). The circuit is referenceless operating at an internally generated signal with a frequency equal to one-fourth of the incoming data rate. It can achieve phase and frequency detection at a PRBS data stream as well as inherent 1-to-4 demultiplexing. Though, there exists few numbers of dual-loop fractional rate CDR circuits, however the proposed circuit is entirely digital, synthesizable from a Verilog hardware description language and hence requires no filter, analog or off-FPGA components. Furthermore, a Verilog-based description of the circuit makes it easy to implement on various FPGA platform as well as an integrated circuit with inconsiderable modification. The design has been synthesized and implemented on the Altera DE2-70 development board. The CDR achieves BER lower than 10-12 (using bathtub plot), consumes 590-W power while operating at 167.5 Mb/s, the tracking range of the CDR corresponds to 167.32 Mb/s to 193.6 Mb/s data range. The measured RMS and peak-to-peak jitters of the recovered clock are 47.3 ps and 297 ps, respectively, at 167.5 Mb/s and 223-1 PRBS input stream.