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H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof

H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer

H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials

H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers

H01L21/3105—After-treatment

H01L21/311—Etching the insulating layers by chemical or physical means

H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof

H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34

H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers

H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers

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H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34

H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers

H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane

H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

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H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof

H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34

H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers

H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane

H01L21/0338—Process specially adapted to improve the resolution of the mask

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H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof

H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer

H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials

H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment

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H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof

H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer

H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials

H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

H01L21/3088—Process specially adapted to improve the resolution of the mask

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H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof

H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer

H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials

H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers

H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers

H01L21/321—After treatment

H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer

H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof

H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70

H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing

H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches

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H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate

H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body

H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration

H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components

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H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate

H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier

H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body

H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration

Abstract

In some embodiments, methods for forming a masking pattern for an integrated circuit are disclosed. In one embodiment, mandrels defining a first pattern are formed in a first masking layer over a target layer. A second masking layer is deposited to at least partially fill spaces of the first pattern. Sacrificial structures are formed between the mandrels and the second masking layer. After depositing the second masking layer and forming the sacrificial structures, the sacrificial structures are removed to define gaps between the mandrels and the second masking layer, thereby defining a second pattern. The second pattern includes at least parts of the mandrels and intervening mask features alternating with the mandrels. The second pattern may be transferred into the target layer. In some embodiments, the method allows the formation of features having a high density and a small pitch while also allowing the formation of features having various shapes and sizes.

Description

CLAIM FOR PRIORITY

This application claims the priority benefit under 35 U.S.C. §119(e) of Provisional Application Ser. No. 61/117,526, filed Nov. 24, 2008. The full disclosure of this priority application is incorporated herein by reference.

As a consequence of many factors, including demand for increased portability, computing power, memory capacity and energy efficiency, integrated circuits are continuously being made more dense. The sizes of the constituent features that form the integrated circuits, e.g., electrical devices and interconnect lines, are constantly being decreased to facilitate this scaling.

The trend of decreasing feature size is evident, for example, in memory circuits or devices such as dynamic random access memories (DRAMs), flash memory, static random access memories (SRAMs), ferroelectric (FE) memories, etc. To take one example, DRAM typically comprises millions of identical circuit elements, known as memory cells. In general, a capacitor-based memory cell, such as in conventional DRAM, typically consists of two electrical devices: a storage capacitor and an access field effect transistor. Each memory cell is an addressable location that can store one bit (binary digit) of data. A bit can be written to a cell through the transistor and can be read by sensing charge in the capacitor. Some memory technologies employ elements that can act as both a storage device and a switch (e.g., dendritic memory employing silver-doped chalcogenide glass) and some nonvolatile memories do not require switches for each cell (e.g., magnetoresistive RAM). In addition, in some technologies, some elements can act as both charge storage and charge sensing devices. For example, this is the case with flash memory, thus, allowing this type of memory to have one of the smallest cell sizes (4F2) of all memory technologies. In general, by decreasing the sizes of the electrical devices that constitute a memory cell and the sizes of the conducting lines that access the memory cells, the memory devices can be made smaller. Additionally, storage capacities can be increased by fitting more memory cells on a given area in the memory devices.

The continual reduction in feature sizes places ever greater demands on the techniques used to form the features. For example, photolithography is commonly used to pattern features, such as conductive lines. The concept of pitch can be used to describe the sizes of these features. Pitch is defined as the distance between an identical point in two neighboring features when the pattern includes repeating features, as in arrays. These features are typically defined by spaces between adjacent features, which spaces are typically filled by a material, such as an insulator. As a result, pitch can be viewed as the sum of the width of a feature and of the width of the space on one side of the feature separating that feature from a neighboring feature. However, due to factors such as optics and light or radiation wavelength, photolithography techniques each have a minimum pitch below which a particular photolithographic technique cannot reliably form features. Thus, the minimum pitch of a photolithographic technique is an obstacle to continued feature size reduction.

“Pitch doubling” or “pitch multiplication” is one method for extending the capabilities of photolithographic techniques beyond their minimum pitch. A pitch multiplication method is illustrated in FIGS. 1A-1F and described in U.S. Pat. No. 5,328,810, issued to Lowrey et al., the entire disclosure of which is incorporated herein by reference. With reference to FIG. 1A, a pattern of lines 10 is photolithographically formed in a photoresist layer, which overlies a layer 20 of an expendable material, which in turn overlies a substrate 30. As shown in FIG. 1B, the pattern is then transferred using an etch (for example, an anisotropic etch) to the layer 20, thereby forming placeholders, or mandrels, 40. The photoresist lines 10 can be stripped and the mandrels 40 can be isotropically etched to increase the distance between neighboring mandrels 40, as shown in FIG. 1C. A layer 50 of spacer material is subsequently deposited over the mandrels 40, as shown in FIG. 1D. Spacers 60, i.e., the material extending or originally formed extending from sidewalls of another material, are then formed on the sides of the mandrels 40. The spacer formation is accomplished by preferentially etching the spacer material from the horizontal surfaces 70 and 80 in a directional spacer etch, as shown in FIG. 1E. The remaining mandrels 40 are then removed, leaving behind only the spacers 60, which together act as a mask for patterning, as shown in FIG. 1F. Thus, where a given pitch previously included a pattern defining one feature and one space, the same width now includes two features and two spaces, with the spaces defined by, e.g., the spacers 60. As a result, the smallest feature size possible with a photolithographic technique is effectively decreased.

While the pitch is actually halved in the example above, this reduction in pitch is conventionally referred to as pitch “doubling,” or, more generally, pitch “multiplication.” Thus, conventionally, “multiplication” of pitch by a certain factor actually involves reducing the pitch by that factor. The conventional terminology is retained herein.

Because a spacer pattern typically follows the outlines of mandrels, pitch multiplication is generally useful for forming regularly spaced linear features, such as conductive interconnect lines in a memory array. However, in addition to features which extend linearly over relatively large distances (e.g., conductive interconnect lines), integrated circuits typically contain features having various shapes and sizes which can be difficult to form by conventional pitch multiplication processes. In addition, the continuing reduction in the sizes of integrated circuits has provided a continuing demand for reductions in the sizes of features.

Accordingly, there is a continuing need for methods of forming features having a small pitch and high density.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be better understood from the Detailed Description of the Preferred Embodiments and from the appended drawings, which are meant to illustrate and not to limit certain embodiments of the invention, and wherein:

FIGS. 1A-1F are schematic, cross-sectional side views showing a sequence of masking patterns for forming conductive lines, in accordance with a prior art pitch doubling method;

FIGS. 3A-3K are schematic, cross-sectional views showing a process sequence for forming features in a target layer, in accordance with some embodiments;

FIGS. 4A-4H are schematic, cross-sectional views showing a process sequence for forming features in a target layer, in accordance with other embodiments;

FIGS. 5A-5D are schematic, cross-sectional views showing a process sequence for forming features in a target layer, in accordance with yet other embodiments;

FIGS. 6A-6E are schematic, cross-sectional views showing a process sequence for forming features in a target layer, in accordance with yet other embodiments;

FIGS. 7A-7F are schematic, cross-sectional views showing a process sequence for forming features in a target layer, in accordance with yet other embodiments;

FIGS. 8A-8E are schematic, cross-sectional views showing a process sequence for forming features in a target layer, in accordance with yet other embodiments;

FIGS. 9A-9D are schematic, cross-sectional views showing a process sequence for forming features in a target layer, using anti-spacers and spacers, in accordance with yet other embodiments;

FIGS. 10A-12B are schematic, top plan views and cross-sectional views showing a process sequence for forming three dimensional features in a target layer, in accordance with some embodiments, wherein FIGS. 10A, 11A, and 12A are schematic, top plan views; FIG. 10B is a cross-sectional view of FIG. 10A, taken along the line 10B-10B; FIGS. 11B and 11C are cross-sectional views of FIG. 11A, taken along the lines 11B-11B and 11C-11C, respectively; and FIG. 12B is a cross-sectional view of FIG. 12A, taken along the line 12B-12B;

FIG. 12C is a schematic perspective view of a structure resulting from the process of FIGS. 10A-12B;

FIGS. 13A-15B are schematic, top plan views and cross-sectional views showing a process sequence for forming three dimensional features in a target layer, in accordance with some embodiments, wherein FIGS. 13A and 14A are schematic, top plan views; FIG. 13B is a cross-section of FIG. 13A, taken along the line 13B-13B; FIGS. 14B and 14C are cross-sectional views of FIG. 14A, taken along the lines 14B-14B and 14C-14C, respectively; and FIGS. 15A and 15B are cross-sectional views of FIG. 14A, taken along the lines 14B-14B and 14C-14C, respectively, after a pattern of features has been transferred into the target layer;

FIG. 15C is a schematic, perspective view of a structure resulting from the process of FIGS. 13A-15B; and

FIGS. 16A-16D are schematic, top plan views showing a process sequence for forming landing pads, in accordance with some embodiments.

DETAILED DESCRIPTION

In the context of this document, the term “integrated circuit (IC) device” refers to a semiconductor device, including, but not limited to, a memory device and a microprocessor. The memory device may be a volatile memory such as a random access memory (RAM) or non-volatile memory such as a read-only memory (ROM). Examples of RAMs include dynamic random access memories (DRAMs) and static random access memories (SRAMs). Examples of ROMs include programmable read-only memories (PROMs), erasable programmable read-only memories (EPROMs), electrically-erasable programmable read-only memories (EEPROMs), and flash memories.

The term “semiconductor substrate” is defined to mean any construction comprising semiconductor materials, including, but not limited to, bulk semiconductor materials such as a semiconductor wafer (either alone or in integrated assemblies comprising other materials thereon) and semiconductor material layers (either alone or in integrated assemblies comprising other materials). The term “substrate” refers to any supporting substrate, including, but not limited to, the semiconductor substrates described above. Also in the context of this document, the term “layer” encompasses both the singular and the plural unless otherwise indicated. A layer may overlie a portion of, or the entirety of, a substrate.

The term, “features,” as used herein, refers to parts of a pattern, such as lines, spaces, via, pillars, trenches, troughs, or moats. The term, “mandrels,” as used herein, refers to mask features formed at a vertical level. The term, “intervening mask features, as used herein, refers to mask features that are formed between two immediately neighboring mandrels.

The term “array” refers to a regularly repeating pattern of IC elements on a semiconductor substrate. For example, a memory array typically has a number of identical memory cells in a matrix form. Logic arrays may similarly include repeating patterns of conductive lines and/or transistors.

The term, “target layer,” as used herein, refers to a layer in which a pattern of features is formed. A target layer may be part of a semiconductor substrate. A target layer may include metal, semiconductor, and/or insulator.

It will also be appreciated that transferring a pattern from a first (e.g., masking) level to a second level involves forming features in the second level that generally correspond to features on the first level. For example, the path of lines in the second level will generally follow the path of lines on the first level. The location of other features on the second level will correspond to the location of similar features on the first level. The precise shapes and sizes of corresponding features can vary from the first level to the second level, however due, for example, to trim and growth steps. As another example, depending upon etch chemistries and conditions, the sizes of and relative spacings between the features forming the transferred pattern can be enlarged or diminished relative to the pattern on the first level, while still resembling the same initial “pattern.”

While “processing” through masks is described for some embodiments as etching to transfer a hard mask pattern into a target layer, the skilled artisan will appreciate that processing in other embodiments can comprise, e.g., oxidation, nitridation, selective deposition, doping, etc. through the masks.

In some embodiments, methods are provided for forming a masking pattern for an electronic device, such as an integrated circuit. First, mandrels defining a first pattern are formed in a first masking layer provided over a target layer. As nonlimiting examples, the mandrels may be formed of a resist, a hard mask material, or part of a substrate. A second masking layer is deposited in spaces between the mandrels. The second masking layer at least partly fills the spaces between the mandrels. In some embodiments, the second masking layer may bury the first pattern.

Before or after depositing the second masking layer, one or more sacrificial structures are formed to define a second pattern having a smaller pitch than the first pattern. In some embodiments, the one or more sacrificial structures may be formed by altering, e.g., chemically altering, portions of either or both of the mandrels and the second masking layer. In other embodiments, the one or more sacrificial structures may be formed by growing or depositing a layer of a material that is different, or selectively etchable relative to, those of the first and second masking layers before depositing the second masking layer. The resulting intermediate masking structures according to some embodiments are shown in FIGS. 2A and 2B.

In FIG. 2A, an intermediate masking structure 200A includes mandrels 130, a second masking layer 140, and sacrificial structures 150 that are formed on a target layer 110. The mandrels 130 are spaced apart. The sacrificial structures 150 are formed on top and side surfaces 130a, 130b of the mandrels 130. The second masking layer 140 fills the remainder of the spaces between the mandrels 130.

Referring to FIG. 2B, another intermediate masking structure 200B includes mandrels 130, a second masking layer 140, sacrificial structures 150, and partial gap fillers 155 formed on a target layer 110. The mandrels 130 are spaced apart from one another on the target layer 110. The sacrificial structures 150 are conformally formed on top and side surfaces 130a, 130b of the mandrels 130. The partial gap fillers 155 are formed of the same material as the material of the sacrificial structures. The partial gap fillers 155 are formed on top surfaces 112 of the target layer 110 between the mandrels 130 covered with the sacrificial structures 150. In some embodiments, the partial gap fillers 155 may be formed simultaneously with the sacrificial structures 150. The second masking layer 140 fills the remaining spaces between the mandrels 130.

The sacrificial structures 150 are removed to create gaps between the mandrels 130 and the second masking layer 140. Such sacrificial structures are referred to as “anti-spacers” in the context of this document. The resulting masking structure may include the mandrels 130 and intervening mask features formed of the second masking layer 140 (FIG. 2A). Alternatively, the resulting masking structure may include the mandrels 130 and intervening mask features including the second masking layer 140 and the partial gap fillers (FIG. 2B). In some embodiments, the mandrels 130 and the intervening mask features alternate with each other, and together define a second pattern.

In some embodiments, the mandrels in the second pattern have a first pitch between two adjacent mandrels. The intervening mask features in the second pattern have a pitch substantially the same as the first pitch. The mandrels and intervening mask features are both used as masking features for the second pattern. The second pattern has a second pitch defined by the mandrels and an immediately adjacent one of the intervening mask features. The second pitch is about a half of the first pitch. Thus, the foregoing process and features provide pitch doubling, that is, the second pattern has a pitch that is half of the pitch of the first pattern. In other embodiments, the pitch of the second pattern may be further reduced by performing an additional process employing anti-spacers as described herein, or by blanket depositing and etching spacer material to form spacers on sidewalls of the mandrels and intervening mask features.

The methods described herein can be used for forming three dimensional structures in a target layer. The three dimensional structures include, but are not limited to, lines, trenches, vias, posts, pillars, troughs, moats, and two or more of the foregoing. In addition, the methods can form structures having different sizes and shapes, for example, variable width conductive lines and landing pads.

The methods discussed above and described below in the context of certain embodiments allow decreases in pitch and increases in the density of features. In addition, the methods allow forming features having various shapes and sizes with a low number of patterning steps.

With reference again to FIGS. 2A and 2B, various processes can be adapted for forming the mandrels 130, the second masking layer 140, the sacrificial structures 150, and/or partial gap fillers 155. Examples of such processes include, but are not limited to, those listed in Table 1.

TABLE 1

Processes

Lithography (LG)

Furnace (FF)

UV cure (UVC)

Single layer etch (SLE)

Chemical vapor deposition

UV bake (UVB)

(CVD)

Multi layer etch (MLE)

Physical vapor deposition

Vacuum bake (VB)

(PVD)

Diffusion limited shrink

Spin-on deposition (SO)

Plating process (PU)

(DLS)

Diffusion limited growth

Wet development (WD)

Hard mask formation (HM)

(DLG)

Thermal freeze (TF)

Solvent development (SD)

Chemical shrink (CS)

Plasma freeze (PF)

Dry development (DD)

Plasma shrink (PS)

Vapor freeze (VF)

Plasma etch (PE)

Crosslinking (CL)

Chemical freeze (CF)

Plasma descum (PD)

Chemical growth (CG)

Exposure freeze (EF)

Chemical descum (CD)

Plasma growth (PG)

Thermal reflow (TR)

Slim process (SL)

Vapor treatment (VT)

Chemical reflow (CR)

Image reversal (IR)

Silation process (SP)

Atomic layer deposition

Overcoating (OC)

Reactive ion etch (RIE)

(ALD)

Plasma deposition (PD)

Anti-spacer formation (AS)

Phase change (PC)

Deprotection process (DPP)

Selectivity change (SEC)

Solubility change (SC)

The processes and materials of Tables 1 and 2 will be understood by those of skill in the art, particularly in view of the present disclosure. In Table 1, the term “single level etch” refers to a process in which a single layer is provided and etched to form features of a pattern. The term “multi level etch” refers to a process in which multiple layers are provided and etched to form features of a pattern. The term “diffusion limited shrink” refers to a process in which a solubility change in a feature is caused by a coat, thereby allowing a decrease in a dimension of the feature. The term “diffusion limited growth” refers to a process in which a material is chemically attached to a pre-existing feature, e.g., through a reaction or adsorption, thereby increasing the dimension of the feature.

The term “freeze” refers to a surface treatment that protects a pattern by maintaining the integrity of the boundaries of the features forming the pattern; for example, freezing a pattern formed by a photoresist to prevent it from dissolving into an overlying photoresist layer. In some instances, a “freeze” process can be performed to change the chemical solubility of a material that is being “frozen.” After the freeze process, the frozen material no longer exhibits solubility to solvents which would otherwise dissolve the material before the freeze process. For example, a photoresist, after being subjected to a freeze process, would be insoluble to solvents, such as propylene glycol monomethyl ether acetate (PGMEA) or ethyl lactate.

The term “reflow” refers to a process inducing a feature size change, a line increase, and a space decrease, for example, a thermal process that is designed for such a feature size shift to occur. The term “deprotection process” refers to a process in which a feature protected from a chemical reaction or dissolution by a solvent is released and allowed to become reactive or soluble. The term “furnace” refers to a process that includes a thermal bake at a temperature ranging typically, but not limited to, from about 250° C. to about 1000° C. The term “solvent development” refers to a process in which an unconventional solvent-based developer (e.g., a solvent other than tetramethylammonium hydroxide (TMAH)) is used to define a pattern.

The term “descum” refers to a process for removing small portions or residues of a material. The term “slim process” refers to a process that induces a feature size change, namely, a size decrease and a space increase. The term “overcoating” refers to a process of depositing or spinning-on a layer over an existing layer. The term “anti-spacer formation” refers to a process of forming anti-spacers, as described herein. The term “selectivity change” refers to an etch process having the ability to differentiate the etch rate of a target material from the etch rate of a non-target material. The term “plating process” refers to an electrochemical process of depositing a metal on an existing layer(s). The term “shrink” refers to a process for reducing a size of a feature. The term “plasma growth” refers to a process designed to add additional material to an existing feature, with assistance of a plasma operation. The term “vapor treatment” refers to a process in which a gas phase material is used to interact with a substrate. The term “silation process” refers to a process of forming a silane compound. The term “phase change” refers to a process in which a substrate undergoes a phase change during the process. The term “solubility change” refers to a process that changes the solubility of a material in a specific solution.

The mandrels 130, the second masking layer 140, the sacrificial structures 150, and/or partial gap fillers 155 may be formed of various materials. Examples of such materials include, but are not limited to, those listed in Table 2.

TABLE 2

Materials

oxide (OX)

Spin on glass (SOG)

nitride (N)

Tetraethylorthosilicate (TEOS)

silicon oxide (SiO)

Metal-containing hard mask (MHM)

Silicon hard mask (SHM)

Image reversal film (IRF)

Titanium polymer (TP)

tetramethylammonium hydroxide

(THAM) developer (TD)

Silicon polymer (SP)

Solvent developer (SD)

Deposited ARC - SiOxN (DARC)

Gas (GAS)

Bottom Antireflective Coating

Hexamethyldisilazane (HMDS)

(BARC)

Specific development chemistry

Diethylaminotrimethlysilane

(SDS)

(DEATS)

Photoresist (PR)

Spin on overcoat (SOO)

Deposited underlayer (DUL)

Deposited overcoat (DO)

Spin on underlayer (SUL)

Vapor freeze chemistry (VFC)

Reactivity promoter (RP)

Solvent suspensions (PGMEA

or other)

In Table 2, the term “specific development chemistry” refers to a chemical or material, such as butyl acetate or other customized solvents for development. The term “underlayer” refers to a layer of material used for a pattern transfer into an underlying layer. The term “reactivity promoter” refers to a chemical agent that promotes the growth of an organic material on a feature. A reactivity promoter may or may not act as a catalyst to a reaction which it promotes. A reactivity promoter may contribute to the attachment of one material to the surface of another material. Thus, it will be appreciated that the various materials of Table 2 may be formed by one or more of the processes of Table 1. Advantageously, the materials can be combined together and possibly with other materials to form masks for defining patterns. This list is for illustrative purposes only, such that the application of the processes noted herein to some embodiments of the invention may be expressed. The list is not intended to be exhaustive, and as such materials and techniques used in the anti-spacer formation are not limited to this list.

For example, in certain embodiments, a method is provided for forming a masking pattern for an electronic device, such as an integrated circuit. First, mandrels defining a first pattern are formed in a first masking layer deposited over a target layer. As nonlimiting examples, the mandrels may be formed of a resist or a hard mask material. A second masking layer is deposited on and over the first masking layer to at least partly bury the first pattern while maintaining the first pattern. The first pattern may be maintained by subjecting the first pattern to a surface treatment using, for example, a so-called freeze technique, prior to depositing the second masking layer.

Portions of the second masking layer proximate to the mandrels are chemically altered such that the portions are more chemically removable (have higher etchability) than unaltered parts of the second masking layer. The chemically altered portions are immediately adjacent the mandrels and have a selected width, and can be referred to as “anti-spacers” in the context of this document. In some embodiments, the chemical alteration can be achieved by a bake that drives an acid- or base-initiated reaction using an acid or base diffused from the mandrels. The anti-spacers may not expand into the mandrels in this embodiment.

In some other embodiments, both portions of the mandrels immediately adjacent to the second masking layer and portions of the second masking layer immediately adjacent to the mandrels may be chemically altered. In such embodiments, the altered portions of both the mandrels and the second masking layer form anti-spacers. In yet other embodiments, portions of the mandrels immediately adjacent to the second masking layer may be chemically altered while substantially no portion of the second masking layer is chemically altered, thereby forming anti-spacers only in the altered portions of the mandrels.

The chemically altered portions are removed, exposing the mandrels. In certain embodiments, an additional step(s) can be performed to remove any material over the chemically altered portions to expose top surfaces of the chemically altered portions before removing the chemically altered portions. The remainder of the second masking layer forms intervening mask features. The mandrels and the intervening mask features together define a second pattern. The second pattern is transferred into the target layer.

Reference will now be made to the Figures, in which like numerals refer to like parts throughout.

FIGS. 3A-3K illustrate a method of forming a masking pattern using anti-spacers in accordance with some embodiments. Referring to FIG. 3A, a hard mask layer 120 is provided over a target layer 110. In addition, a first resist layer 230 is provided over the hard mask layer 120.

The target layer 110 may be a layer in which various IC components, parts, and structures are to be formed through IC fabrication processes. Examples of the components, parts, and structures include transistors, capacitors, resistors, diodes, conductive lines, electrodes, spacers, trenches, etc. The identity of the target layer material depends on the type of device to be formed in the target layer 110. Examples of target layer materials include, but are not limited to, insulators, semiconductors, and metals. The target layer 110 may be formed over a substrate, for example, a semiconductor substrate in certain embodiments. In certain other embodiments, at least a portion of a semiconductor substrate forms the target layer 110.

The hard mask layer 120 is a layer that provides a pattern to be transferred into the target layer 110. As described herein, the hard mask layer 120 is patterned to form an array of features that serve as a mask for the target layer 110, e.g., in an etch step. While illustrated with one hard mask layer, the processes described herein can employ two or more hard mask layers. In certain embodiments, the hard mask layer 120 may be omitted.

In some embodiments, the hard mask layer 120 may be formed of an inorganic material. In the illustrated embodiment, the hard mask layer 120 is formed of a dielectric anti-reflective coating (DARC), for example, silicon-rich silicon oxynitride (SiOxNy). The DARC layer may contain silicon in an amount from about 30 wt % to about 80 wt % with reference to the total weight of the layer. The DARC layer may contain silicon in an amount from 35 wt % to about 70 wt % with reference to the total weight of the layer. In other embodiments, the hard mask layer 120 may be formed of silicon, silicon oxide (SiO2) or silicon nitride (Si3N4). In yet other embodiments, the hard mask layer 120 may be formed of an organic material. For example, the hard mask layer 120 may be formed of amorphous carbon. The skilled artisan will appreciate that various other hard mask materials can be used for the hard mask layer 120. In some embodiments, the hard mask layer 120 may have a thickness of between about 80 nm and about 800 nm, optionally between about 1 μm and about 3 μm.

The first resist layer 230 may be formed of a first resist material. The first resist material is selected based on the type of lithography used for patterning the first resist layer 230. Examples of such lithography include, but are not limited to, ultraviolet (UV) lithography, extreme ultraviolet (EUV) lithography, X-ray lithography and imprint contact lithography. In the illustrated embodiment, the first resist material is a photoresist, such as a positive resist. The skilled artisan will, however, appreciate that the material of the first resist layer 230 may be varied depending on lithography, availability of selective etch chemistries and IC design.

Optionally, a bottom anti-reflective coating (BARC) layer (not shown) may be provided between the first resist layer 230 and the hard mask layer 120. BARCs, which are typically organic, enhance resolution by preventing reflections of the ultraviolet (UV) radiation that activates the photoresist. BARCs are widely available, and are usually selected based upon the selection of the resist material and the UV wavelength. BARCs, which are typically polymer-based, are usually removed along with the overlying photoresist. The optional BARC layer may have a thickness of between about 200 Å and about 600 Å, optionally between about 300 Å and about 500 Å.

Referring to FIG. 3B, the first resist layer 230 is exposed to a pattern of light directed through a photomask over the first resist layer 230. In the illustrated embodiment, the first resist layer 230 is formed of a positive photoresist. Exposed portions 232 of the first resist layer 230 become soluble in a developer while unexposed portions 234 of the first resist layer 230 remain insoluble in the developer. In other embodiments, the first resist layer 230 may be formed of a negative photoresist. In such embodiments, exposed portions 234 of the first resist layer 230 become insoluble in a developer while unexposed portions 232 of the first resist layer 230 remain soluble in the developer.

After the exposure to the pattern of light, the first resist layer 230 is subjected to development using any suitable developer. Examples of developers include, but are not limited to, sodium hydroxide and tetramethylammonium hydroxide (TMAH). In certain embodiments, rinsing solutions (e.g., propylene glycol monomethyl ether acetate (PGMEA) and/or propylene glycol monomethyl ether (PGME)) can also be used for the development. In certain embodiments, a post-exposure bake (PEB) may be performed after the exposure and before the development. In the illustrated embodiment, the exposed portions 232 of the first resist layer 230 are removed by the development.

Referring to FIG. 3C, the remaining unexposed portions 234 of the first resist layer 230 form mandrels 234. The mandrels 234 provide a first pattern 231 while exposing surfaces 122 of the hard mask layer 120. The first pattern 231 has a first pitch P1 between two neighboring mandrels 234, as shown in FIG. 3B. Each of the mandrels 234 has a top surface 236 and a side surface 238. The illustrated mandrels 234 have a substantially rectangular or square cross-section. The skilled artisan will, however, appreciate that the cross-sectional shape of the mandrels 234 can be different from that illustrated. For example, the cross-sectional slope can be rounded.

Referring to FIG. 3D, a chemically active species, for example, an acid solution, is deposited over the structure shown in FIG. 3C. In one embodiment, the acid solution can be a spin-on coating that covers the mandrels 234 and the exposed portions 122 of the hard mask layer 120. The acid solution can include an acid such as a conventional photo resist PAG or other organic acid. Subsequently, a bake process is conducted to thermally diffuse the acid into at least portions of the features 234 that are proximate to the top and side surfaces 236, 238 thereof. In some embodiments, the acid may coat the top and side surfaces 236, 238 of the features 234 without being diffused into the features 234. In other embodiments where the features 234 are formed of a material containing a selected amount of acid, this step may be omitted. In certain embodiments, a base solution may be deposited over the structure in place of the acid solution.

Referring to FIG. 3E, the mandrels 234 may be subjected to a surface treatment. The surfaces 236, 238 of the mandrels 234 are modified such that the integrity of the mandrels 234 is maintained while a second resist layer is formed and patterned thereon. The surface treatment may form a barrier coat or protective layer 236 on the surfaces 236, 238 of the mandrels 234. Such a surface treatment can be referred to as “freeze” in the context of this document. The surface treatment may or may not change the lateral dimensions of the mandrels 234, and may or may not change the spacings between adjacent mandrels 234.

The mandrels 234 can be frozen by various freeze techniques. In one embodiment, the mandrels 234 can be frozen by chemical freeze, using a commercially available fluid overcoat. An example of a chemical freeze technique is disclosed by JSR corporation of Tokyo, Japan in their present product line.

In another embodiment, the mandrels 234 can be frozen by a plasma freeze. A plasma freeze can be conducted, using a plasma directed to the mandrels 234. Examples of plasmas include a fluorine-containing plasma generated from, e.g., a fluorocarbon (e.g., CF4, C4F6, and/or C4F8), a hydrofluorocarbon (e.g., CH2F2, and/or CHF3), or NF3. An example plasma freeze technique is disclosed by U.S. patent application Ser. No. 12/201,744, filed Aug. 29, 2008, entitled “METHODS OF FORMING A PHOTORESIST-COMPRISING PATTERN ON A SUBSTRATE” (Inventors: Zhang et al.). In yet another embodiment, the mandrels 234 can be frozen by a thermal freeze. The thermal freeze can be conducted at a temperature between about 110° C. and about 180° C. An example of a thermal freeze technique is disclosed by Tokyo Ohka Kogyo Co., Ltd. of Kawasaki-shi, Kanagawa Prefecture, Japan in their commercially available products.

Referring to FIG. 3F, a second resist layer 240 is blanket deposited over the mandrels 234 and the exposed surfaces 122 of the hard mask layer 120. The second resist layer 240 can have a substantially planar top surface 244. The second resist layer 240 may be formed of a second resist material. The second resist material may be of the same composition as the first resist material or of a different composition from the first resist material. The first and second resist materials may be of the same or different type with regard to being positive or negative photoresist.

In some embodiments, the second resist material may include a chemically amplified photoresist. The chemically amplified photoresist may be an acid-catalyzed or base-catalyzed material. Examples of chemically amplified photoresists include, but are not limited to, 193 nm and 248 nm photo resists. Some I-line materials are also chemically amplified.

In certain embodiments, the second resist material may include a bottom anti-reflective coating (BARC) material modified to be suitable for a solubility change by acid or base diffusion. The skilled artisan will appreciate that any material showing a solubility change caused by the acid or base diffusion can be used in place of the second resist material.

The second resist layer 240 may be formed to have a thickness sufficient to cover the top surface 236 of the mandrels 234. Portions 242 of the second resist layer 240 overlying the top surfaces 236 of the mandrels 234 can be referred to as “top coat” in the context of this document. The top coats 242 may have a thickness selected such that all the resulting masking features have substantially the same height after the frozen mandrels 234 and other features that will be formed from portions of the second resist layer 240 are subjected to development. The resulting masking features will form a pattern to be transferred into the underlying target layer 110.

Referring to FIG. 3G, the structure of FIG. 3F is subjected to a bake. In one embodiment, the bake may be conducted at a temperature of about 110° C. to about 220° C. for about 0.5 min. to about 3 min. In another embodiment, the bake may be conducted at a temperature of about 110° C. to about 160° C. In embodiments where the second resist layer 240 is formed of an acid-catalyzed chemically amplified resist, the bake drives an acid-catalyzed reaction that alters the solubility of the second resist layer 240 in a developer. The acid-catalyzed reaction changes portions 250 of the second resist layer 240 that are proximate to the mandrels 234, causing those changed portions to become soluble in the developer. The portions 250 of the second resist layer 240 may include the top coats 242 of the second resist layer 240 and portions 244 adjoining the side surfaces 238 of the mandrels 234. The portions 250 that become soluble can be referred to as “anti-spacers.”

The acid-catalyzed reaction is initiated at or near the top and side surfaces 236, 238 of the mandrels 234 during the bake step. For example, an acid diffused into the mandrels 234 during the step of FIG. 3D now diffuses into the top coats 242 and the adjoining portions 244 of the second resist layer 240 (as indicated by arrows in FIG. 3G), and changes the solubility of the portions 242, 244, thereby forming anti-spacers 250 around and on top of the mandrels 234. The width WI of the anti-spacers 250 can be controlled by changing, for example, the bake time and/or temperature, the porosity of layer 240, and the size of acid species.

In other embodiments where the second resist layer 240 is formed of a base-catalyzed chemically amplified resist, the bake drives a base-catalyzed reaction that may alter the solubility of the second resist layer 240 in a developer. In such an embodiment, a base solution is provided in the step of FIG. 3D, rather than an acid solution. The skilled artisan will appreciate that anti-spacers can be formed in the same manner as in the embodiment described herein in connection with FIG. 3G.

In certain embodiments, other portions (not shown) of the second resist layer 240 may be optionally exposed to a pattern of light before or after the bake step. This exposure step can be used to form patterns in the other areas by photolithography, rather than by forming anti-spacers. During this optional exposure step, the structure shown in FIG. 3F or 3G may be blocked from light, if the structures are formed of a positive photoresist. This optional exposure step can form structures larger in width than the structures shown in FIG. 3H. In certain embodiments, the optional exposure step can be used to form structures in a peripheral region of an IC device or substrate while methods employing anti-spacers can be used to form structures in an array region of the IC device or substrate.

Referring to FIG. 3H, the structure resulting from the step of FIG. 3G is subjected to development which serves to selectively remove the anti-spacers 250. Any suitable developer may be used to remove the anti-spacers 250 (FIG. 3G). Examples of developers include, but are not limited to, sodium hydroxide and tetramethylammonium hydroxide (TMAH). In certain embodiments, rinsing solutions (e.g., propylene glycol monomethyl ether acetate (PGMEA) and/or propylene glycol monomethyl ether (PGME)) can also be used for the development. In one embodiment, this development step can be performed at room temperature for about 0.5 min. to about 3 min.

This step exposes the pre-existing mandrels 234 while defining intervening mask features 248 formed of the second resist material. The illustrated intervening mask features 248 have a T-shaped top portion, but the skilled artisan will appreciate that the shape of the intervening mask features 248 can vary, depending on the conditions (e.g., temperature, duration, etc.) of the development. The mandrels 234 may have a first height H1 and the intervening mask features 248 may have a second height H2 that is greater than the first height H1.

Referring to FIG. 3I, the developer may also anisotropically remove at least part of top portions of the mandrels 234 and the intervening mask features 248. The mandrels 234, which have been frozen, may be developed at a slower rate than the intervening mask features 248. Thus, after the completion of the development, the mandrels 234 and the intervening mask features 248 can have substantially the same height H3 as each other if the thicknesses of the top coats 242 of the second layer 240 have been selected such that the heights of the mandrels 234 and the intervening mask features 248 are substantially the same as each other after the development. As shown in FIG. 3I, both of the mandrels 234 and the intervening mask features 248 can have rounded top portions. In certain embodiments, an isotropic etch process may be conducted after the development to reduce the widths of the mandrels 234 and the intervening mask features 248.

The mandrels 234 and the intervening mask features 248 together provide a second pattern 260, as shown in FIG. 3I. The second pattern 260 has a second pitch P2 between neighboring features. The second pitch P2 is about half of the first pitch P1 in the illustrated embodiment.

Referring to FIG. 3J, an etch step is conducted to transfer the second pattern 260 into the underlying hard mask layer 120. The second pattern 260 may be transferred into the hard mask layer 120 using any suitable etch process. The etch process can be a dry or wet etch process. In one embodiment, the etch process can be a plasma etch process, for example, a high density plasma etch process. The plasma etch process may be an anisotropic etch process.

Referring to FIG. 3K, the target layer 110 is etched through the hard mask layer 120. As a result, trenches or troughs 205 are formed in the target layer 110. In some embodiments, through-holes can be formed through the target layer 110.

In certain embodiments, an etch stop layer (not pictured) can be used between the hard mask layer 120 and the target layer 110. The etch stop can be made of, for example, DARC or silicon nitride, depending upon the composition of the target layer 110. The etch stop avoids damage to the target layer 110 during the etching of the hard mask layer 120, such as during pattern transfer to the hard mask layer 120 or during removal of the hard mask layer 120. This may be particularly desirable when the target layer 110 is a metal, such as a metallization layer.

When processing (e.g., etching) of the target layer is completed, the hard mask layer 120 and the overlying features 234, 248 may be removed by etch processes, such as a wet etch. Subsequently, additional steps such as metallizations may be conducted to form integrated circuits.

FIGS. 4A-4H illustrate a method of forming a masking pattern using anti-spacers in accordance with other embodiments. In these embodiments, the mandrels are formed from a hard mask layer or other material other than a photoresist layer. Referring to FIG. 4A, the method includes providing the target layer 110. Details of the target layer 110 can be as described above in connection with FIG. 3A.

A hard mask layer is formed over the target layer 110. In some embodiments, the hard mask layer may be formed of a silicon-containing organic material. The silicon-containing organic layer may contain silicon in an amount from about 10 wt % to about 35 wt % with reference to the total weight of the layer. An example of a silicon-containing organic materials includes, but is not limited to, SHB-A629 (available from Shin Etsu, Tokyo, Japan). In such an embodiment, the hard mask layer may have a thickness of between about 40 nm and about 800 nm, optionally between about 1 μm and about 3 μm.

The hard mask layer is then patterned to form mandrels 330, as shown in FIG. 4A. The hard mask layer can be patterned using any suitable process, including, but not limited to, a photolithographic process in which photoresist is patterned and the pattern is transferred to the hard mask layer. The mandrels 330 are spaced apart from one another and have a first pitch P1 and expose surfaces 112 of the target layer 110.

Referring to FIG. 4B, a chemically active species, for example, an acid solution, is deposited on the structure shown in FIG. 4A. In one embodiment, the acid solution can be spin-on deposited on the structure to cover the mandrels 330 and the exposed surfaces 112 of the target layer 110. The acid solution can include any organic acid, such as a PAG. Subsequently, a bake process is conducted to thermally diffuse the acid into at least portions of the mandrels 330 proximate to the top and side surfaces 332, 334 of the mandrels 330. In this embodiment, the mandrels 330 are at least partially permeable to the acid while the target layer 110 is substantially impermeable to the acid. Thus, the mandrels 330 can have an acid coat 336 on the surfaces 332, 334 thereof while the exposed portions 112 of the target layer 110 do not have an acid coat formed thereon, as shown in FIG. 4C. In other embodiments, the chemically active species may be in the form of a gas or may be in the solid state.

Referring to FIG. 4D, a resist layer 340 is formed over the mandrels 330 and the exposed portions 112 of the target layer 110 and may have a substantially planar top surface 344. The resist layer 340 may be formed of a resist material that is the same as the second resist material described above in connection with FIG. 3F. In one embodiment, the resist material may include a chemically amplified resist. The chemically amplified resist may be either acid-catalyzed or base-catalyzed. In other embodiments where the resist material is a base-catalyzed resist, a base coat (rather than an acid coat) is provided over the mandrels 330 and the exposed portions 112 of the target layer 110 in the step of FIG. 4C. Other details of forming the resist layer 340 can be as described above in connection with FIG. 3F.

Referring to FIG. 4E, the structure resulting from the step of FIG. 4D is subjected to a bake. The bake forms anti-spacers 350 at the sides and on top of the mandrels 330. Other details of the bake step can be as described in connection with FIG. 3G.

In certain embodiments, other portions (not shown) of the resist layer 340 may be optionally exposed to a pattern of light before or after the bake step of FIG. 4E. This exposure step can be used to form patterns in the other portions by photolithography, rather than by forming anti-spacers. During this optional exposure step, the structure shown in FIG. 4E may be blocked from light, if the structures are formed of a positive photoresist. This optional exposure step can form structures larger in width than the structures shown in FIG. 4F. In certain embodiments, the optional exposure step can be used form structures in a peripheral region of an IC device or substrate while methods employing anti-spacers can be used to form structures in an array region of the IC device or substrate.

Referring to FIG. 4F, the structure resulting from the step of FIG. 4E is subjected to development to remove the anti-spacers 350. This step exposes the pre-existing mandrels 330 formed of the hard mask material while forming intervening mask features 345 formed of the resist material. The illustrated intervening mask features 345 have a T-shaped top portion, but the skilled artisan will appreciate that the shape of the intervening mask features 345 can vary, depending on the conditions (e.g., temperature, duration, etc.) of the development. The mandrels 330 may have a first height H1 and the intervening mask features 345 have a second height H2 that is greater than the first height H1.

The developer can also remove at least part of the top portions of the intervening mask features 345. However, the mandrels 330, which are formed of a hard mask material, may not be eroded by the developer. Thus, after the completion of the development, the mandrels 330 and the intervening mask features 345 may have substantially the same height H3 as each other. As shown in FIG. 4G, the mandrels 330 may retain their original shape while the intervening mask features 345 may have rounded top portions.

The mandrels 330 and the intervening mask features 345 together provide a second pattern 360, as shown in FIG. 4G. The second pattern 360 has a second pitch P2 between a mandrel 330 and a neighboring intervening mask feature 345. The second pitch P2 is about half of the first pitch P1 in the illustrated embodiment.

Referring to FIG. 4H, an etch step is conducted to transfer the second pattern 360 into the target layer 110. The second pattern 360 may be transferred into the target layer 110 using any suitable etch process. The etch process can be a dry or wet etch process. In one embodiment, the etch process can be a plasma etch process, optionally a high density plasma etch process. The plasma etch process may be an anisotropic etch process. Other details of this step can be as described above in connection with FIG. 3K.

In the illustrated embodiment, trenches or troughs 305 (or through-holes in other embodiments) are formed in the target layer 110. Because the mandrels 330 (formed of a hard mask material) may be etched at a faster rate than the intervening mask features 345 (formed of a photoresist) during the transfer step of FIG. 4H, the height H4 of the remaining mandrels 330 may be greater than the height H5 of the remaining intervening mask features 345 after the completion of the transfer step.

When processing (e.g., etching) of the target layer 110 is completed, the mandrels 330 and the intervening mask features 345 may be removed by known etch processes, such as a wet etch step. Subsequently, additional steps such as metallization may be conducted to complete integrated circuits.

FIGS. 5A-5D illustrate a method of forming a masking pattern using anti-spacers in accordance with yet other embodiments. Referring to FIG. 5A, the method includes providing the target layer 110. Details of the target layer 110 can be as described above in connection with FIG. 3A. Hard mask layer 120 is formed on the target layer 110. Details of the hard mask layer 120 can be as described above in connection with FIG. 3A. In certain embodiments, the hard mask layer 120 may be omitted.

Then, mandrels 430 are formed of a photoresist material on the hard mask layer 120. Details of forming the mandrels 430 can be as described above in connection with FIGS. 3A-3C. The mandrels 430 provide a first pattern 431 while exposing surfaces 122 of the hard mask layer 120. The first pattern 431 has a first pitch P1 between two neighboring mandrels 430, as shown in FIG. 5A. Each of the mandrels 430 has a top surface 436 and a side surface 438. The illustrated mandrels 430 have a substantially rectangular or square cross-section. The skilled artisan will, however, appreciate that the cross-sectional shape of the mandrels 430 can be different from that illustrated.

Then, a chemically active species 432, for example, an acid or base solution, is deposited on the structure shown in FIG. 5A. In some embodiments, the acid or base solution can be spin-on deposited on the structure to cover the mandrels 430 and the exposed portions 122 of the hard mask layer 120. The details of the acid or base solution can be as described above in connection with FIG. 3D.

Referring to FIG. 5B, the structure of FIG. 5A is subjected to a bake. The details of the bake can be as described above in connection with FIG. 3G. The bake drives an acid- or base-catalyzed reaction that alters the solubility of portions 452, 454 of the mandrels 430. The acid- or base-catalyzed reaction changes top portions 452 and side portions 454 of the mandrels 430, causing those changed portions to become soluble in a developer. The top and side portions 452, 454 of the mandrels 430 form anti-spacers 450. Thus, the resulting mandrels 430′ have a reduced size both vertically and horizontally. Such mandrels 430′ can be referred to as reduced mandrels in the context of this document.

Subsequently, the reduced mandrels 430′ covered with the anti-spacers 450 may be subjected to a surface treatment. Surfaces of the anti-spacers 450 are modified such that the integrity of the mandrels is maintained while a second resist layer is formed thereon. The details of the surface treatment can be as described above in connection with FIG. 3E.

Referring to FIG. 5C, a second masking layer 440 is blanket deposited over the anti-spacers 450 and the exposed surfaces 122 of the hard mask layer 120. In other embodiments, the second masking layer may have a smaller height than the anti-spacers such that the second masking layer surrounds sidewalls of the anti-spacers while exposing top surfaces of the anti-spacers. The second masking layer 440 may be formed of an image reversal material, such as an Image Reversal Overcoat (IROC) material and other similar materials, e.g., as outlined in US Patent Application Publication No. 2009/0081595 from Shin-Etsu Chemical Co., Ltd (Tokyo, Japan). Bottom Anti-Reflection Coating (BARC) materials can also be used for the second masking layer 440. Other details of this step can be as described above in connection with FIG. 3F.

In the illustrated embodiment, the second masking layer 440 may be formed to have a thickness sufficient to cover the top portions 452 of the anti-spacers 450. Portions of the second masking layer 440 overlying the top portions 452 of the anti-spacers 450 may be referred to as “top coats” in the context of this document.

Referring to FIG. 5D, the structure resulting from the step of FIG. 5C is subjected to development. Any suitable developer may be used to remove the anti-spacers 450 (FIG. 5C). This step exposes the reduced mandrels 430′ while defining intervening mask features 448 formed of the material of the second masking layer 440.

The reduced mandrels 430′ and the intervening mask features 448 together provide a second pattern 460. The second pattern 460 has a second pitch P2 between a reduced mandrel 430′ and a neighboring intervening mask feature 448. The second pitch P2 is about half of the first pitch P1 (FIG. 5A) in the illustrated embodiment. Other details of this step can be as described above in connection with FIG. 3H. The step shown in FIG. 5D can be followed by steps as described above in connection with FIGS. 3I to 3K to transfer the second pattern 460 into the target layer 110.

In some other embodiments, mandrels defining a first pattern are formed in a first masking layer provided over a target layer. One or more sacrificial structures may be formed by conformally growing or depositing a layer to cover at least exposed sidewall surfaces of the mandrels. The layer may be formed of a material that is different from that of the first masking layer.

A second masking layer is deposited to fill spaces defined by the mandrels covered with the sacrificial structures. In some embodiments, the second masking layer may cover top surfaces and sidewalls of the mandrels covered with the sacrificial structures. In such embodiments, an additional step(s), e.g., a descum step, can be performed to remove portions of the second masking layer over the sacrificial structures to expose top surfaces of the sacrificial structures. In other embodiments, the second masking layer may have a smaller height than the anti-spacers such that the second masking layer surrounds sidewalls of the anti-spacers while exposing top surfaces of the anti-spacers. The second masking layer may be formed of a material different from the material of the sacrificial structures.

Then, the sacrificial structures are removed, exposing the mandrels. The remaining parts of the second masking layer form intervening masking features. The mandrels and the intervening mask features together define a second pattern. The second pattern is transferred into the target layer.

FIGS. 6A-6E illustrate a method of forming a masking pattern by growing anti-spacers. In these embodiments, mandrels may be formed from a hard mask layer or other material other than a photoresist layer, as discussed with reference to FIG. 4A.

Referring to FIG. 6A, the target layer 110 is provided. Details of the target layer 110 can be as described above in connection with FIG. 3A. A hard mask layer is formed over the target layer 110, and is patterned to form mandrels 330, as shown in FIG. 6A. The mandrels 330 are spaced apart from one another with a first pitch P1 while exposing surfaces 112 of the target layer 110. Each of the mandrels 330 has a top surface 332 and side surfaces 334. Other details of this step can be as described above in connection with FIG. 4A.

Referring to FIG. 6B, a sacrificial material, such as an organic material, is grown on the top and side surfaces 332, 334 of the mandrels 330, while exposing substantial portions of the exposed surfaces 112 of the target layer 110. Examples of such organic materials include, but are not limited to, perhydropolysilazane (PHPS) or polyhedral oligomeric silsesquioxanes (POSS). The organic material can be grown by a diffusion limited growth technique. In some embodiments, the reaction temperature may be between about 100° C. and about 180° C., which may be below the glass transition temperature Tg of the original mandrel material. Attachment of the sacrificial material may be catalyzed by another wet treatment or a material that may be present in the chemical formulation of the mandrel. Critical dimensions can then be modulated by controlling reaction temperature in combination with the chemical compositions used in the sacrificial material. The organic material forms anti-spacers 650 that include top portions 652 and side portions 654 covering the top and side surfaces 332, 334, respectively, of the mandrels 330.

Referring to FIG. 6C, a second masking layer 640 is blanket deposited by, for example, spin-on deposition, over the anti-spacers 650 and the exposed surfaces 112 of the target layer 110. The second masking layer 440 may be formed of a silicon hard mask material, such as STH1125B manufactured by Shin-Etsu Chemical Co., Ltd (Tokyo, Japan) or similar commercial hardmask material readily available to those versed in the art. Other details of this step can be as described above in connection with FIG. 5C. In the illustrated embodiment, the second masking layer 640 may be formed to have a thickness sufficient to slightly cover top portions 652 of the anti-spacers 650. Portions of the second masking layer 640 overlying the top portions 652 of the anti-spacers 650 may be referred to as “top coats” in the context of this document.

Referring to FIG. 6D, the structure resulting from the step of FIG. 6C is subjected to a chemical descum process. The chemical descum process serves to remove the top coats of the second masking layer 640, thereby exposing the top portions 652 of the anti-spacers 650. As non-limiting examples, the chemical descum may be performed using a wet etch or a plasma etch such as a buffered oxide etch (BOE) dip process or Argon sputter etch. Tetramethylammonium hydroxide (TMAH) developer can also be used to clean up these feature areas at a temperature ranging from about 10° C. to about 50° C.

Referring to FIG. 6E, the structure resulting from the step of FIG. 6D is subjected to an etch process to remove the anti-spacers 650. Any suitable etchant may be used to remove the anti-spacers 650, depending on the organic material. In some embodiments where the organic material is a pure hydrocarbon-based material, the etchant can be a dry etchant, such as O2 or halide-based plasma, or a wet etchant, such as tetramethylammonium hydroxide (TMAH), propylene glycol monomethyl ether (PGME), propylene glycol monomethyl ether acetate (PGMEA), or any other suitable organic solvent. This step exposes the mandrels 330 formed of the hard mask material while defining intervening mask features 645 formed of the silicon hard mask material or mandrel material that may have used a process to ensure that its solubility is compatible with the wet etch. For the purpose of this document, such processes can be “freeze” techniques and they serve to limit the solubility of the mandrels in a wet etch process. These “freeze” techniques can take on various forms, for example, a thermal cross linking agent in a resist.

The mandrels 330 and the intervening mask features 645 together define a second pattern 660. The second pattern 660 has a second pitch P2 between a mandrel 330 and a neighboring intervening mask feature 645. The second pitch P2 is about half of the first pitch P1 in the illustrated embodiment. Other details of this step can be as described above in connection with FIG. 3H. The step shown in FIG. 6E can be followed by steps as described above in connection with FIGS. 3I to 3K to transfer the second pattern 660 into the target layer 110.

FIGS. 7A-7F illustrate a method of forming a masking pattern using anti-spacers in accordance with yet other embodiments. In these embodiments, mandrels may be formed from a hard mask layer or any other suitable material, using a process that allows selective growth of anti-spacers. A photoresist can be used in the step shown in FIG. 7A as long as it is appropriately mated to the processing requirements, e.g., with regard to solubility. In such an embodiment, a photoresist used herein can withstand subsequent process steps. This can be achieved with a different solvent resist system, such as an alcohol-based resist or can be achieved with a “freeze” technique.

Referring to FIG. 7A, the method includes providing the target layer 110. Details of the target layer 110 can be as described above in connection with FIG. 3A. A hard mask layer is formed over the target layer 110, and is patterned to form mandrels 330, as shown in FIG. 7A. The mandrels 330 are spaced apart from one another with a first pitch P1 while exposing surfaces 112 of the target layer 110. Each of the mandrels 330 has a top surface 332 and side surfaces 334. Other details of this step can be as described above in connection with FIG. 4A.

Referring to FIG. 7B, a reactivity promoter 655 is deposited on the top and side surfaces 332, 334 of the mandrels 330 without covering the exposed surfaces 112 of the target layer 110. The reactivity promoter serves to facilitate the growth of an organic material on the surfaces of the mandrels 330 at the next step. Examples of such reactivity promoters include, but are not limited to, AZ materials used in RELACS (Resolution Enhancement Lithography Assisted by Chemical Shrink) processes, and a material including a hydroxyl group or organic acid designed to condition the reactivity of the mandrels to a material that covers the mandrels.

Referring to FIG. 7C, a sacrificial material, such as an organic material, is grown on the top and side surfaces 332, 334 of the mandrels 330 that are covered with the reactivity promoter 655. The organic material does not cover the exposed surfaces 112 of the target layer 110 except for portions 112a of the exposed surfaces 112 proximate to the mandrels 330. Examples of such organic materials include, but are not limited to, PHPS or a chain hydrocarbon with a bonding affinity to the mandrels covered with the reactivity promoter. The organic material can be grown by a diffusion limited growth technique by means of a fluid overcoat at a controlled temperature, for example, in a range between about 10° C. and about 180° C. The organic material forms anti-spacers 650 that cover the top and side surfaces 332, 334 of the mandrels 330.

Referring to FIG. 7D, a second masking layer 640 is blanket deposited by, for example, spin-on deposition, over the anti-spacers 650 and the exposed surfaces 112 of the target layer 110. The second masking layer 640 can optionally cover top surfaces of the anti-spacers 650. The second masking layer 640 may be formed of, for example, a silicon hard mask material. The details of this step can be as described above in connection with FIG. 6C.

Referring to FIG. 7E, the structure resulting from the step of FIG. 7D is subjected to a chemical descum process. The details of this step can be as described above in connection with FIG. 6D.

Referring to FIG. 7F, the structure resulting from the step of FIG. 7E is subjected to an etch process to remove the anti-spacers 650. The details of this step can be as described above in connection with FIG. 6E. This step exposes the mandrels 330 formed of the hard mask material while defining intervening mask features 645 formed of the material forming the second masking layer 640, e.g., a silicon hard mask material.

The mandrels 330 and the intervening mask features 645 together define a second pattern 660. The second pattern 660 has a second pitch P2 between a mandrel 330 and a neighboring intervening mask feature 645. The second pitch P2 is about half of the first pitch P1 in the illustrated embodiment. Other details of this step can be as described above in connection with FIG. 3H. The step shown in FIG. 7F can be followed by steps as described above in connection with FIGS. 3I to 3K to transfer the second pattern 660 into the target layer 110.

FIGS. 8A-8F illustrate a method of forming a masking pattern using anti-spacers in accordance with yet other embodiments. In these embodiments, mandrels may be formed from a hard mask layer or any other suitable material compatible with blanket deposition of an anti-spacer material, including materials discussed with reference to FIG. 4A.

Referring to FIG. 8A, the method includes providing a target layer 110. Details of the target layer 110 can be as described above in connection with FIG. 3A. A hard mask layer is formed over the target layer 110, and is patterned to form mandrels 330, as shown in FIG. 8A. The mandrels 330 are spaced apart from one another with a first pitch P1 while exposing surfaces 112 of the target layer 110. Each of the mandrels 330 has a top surface 332 and side surfaces 334. Other details of this step can be as described above in connection with FIG. 4A.

Referring to FIG. 8B, a sacrificial material is conformally deposited on the top and side surfaces 332, 334 of the mandrels 330 and the exposed surfaces 112 of the target layer 110. Examples of such sacrificial materials include, but are not limited to, BARC, DARC, photoresist, silicon-on-glass (SOG), and hardmask type material. The sacrificial material can be deposited by, for example, spin-on coat or deposition. Portions 852, 854 of the sacrificial material that cover the top and side surfaces 332, 334, respectively, of the mandrels 330 form anti-spacers 850. Portions 855 of the sacrificial material formed on the surfaces 112 of the target layer 110 may be referred to as “partial gap fillers” in the context of this document.

Referring to FIG. 8C, a second masking layer 640 is deposited over the partial gap fillers 855 and can also extend over the anti-spacers 850. Other details of this step can be as described above in connection with FIG. 6C.

Referring to FIG. 8D, to expose anti-spacers 850 in embodiments where the anti-spacers 850 are covered, the structure resulting from the step of FIG. 8C is subjected to a chemical descum process. The details of this step can be as described above in connection with FIG. 6D.

Referring to FIG. 8E, the structure resulting from the step of FIG. 8D is subjected to an etch process to remove the anti-spacers 850. The etch process may use an anisotropic etch process, using any suitable dry etchant, such as C2F4, O2, Hbr, or F2. In one embodiment where the organic material is a photoresist, the etchant can be a dry etchant, such as C2F4, O2, Hbr, and F2. This step exposes the mandrels 330 formed of the hard mask material while defining intervening mask features 845 between the mandrels 330. Each of the features 845 includes a structure 645 formed of the silicon hard mask material and a partial gap filler 855 underlying the structure 645.

The mandrels 330 and the intervening mask features 845 together define a second pattern 860. The second pattern 860 has a second pitch P2 between a mandrel 330 and a neighboring intervening mask feature 845. The second pitch P2 is about half of the first pitch P1 in the illustrated embodiment. Other details of this step can be as described above in connection with FIG. 3H. The step shown in FIG. 8E can be followed by steps as described above in connection with FIGS. 3I to 3K to transfer the second pattern 860 into the target layer 110.

In some embodiments, a masking pattern formed by the methods described herein may be used for further pitch multiplication. The pitch of the masking pattern may be further reduced by conducting an additional process using anti-spacers. For example, anti-spacers may be formed around the mask features left after anti-spacer removal, e.g., including the mandrels 234 and intervening mask features 248, as shown in FIG. 3I, and the pitch of the resulting features can be reduced to about half of the second pitch P2.

In such embodiments, a second set of anti-spacers are formed around and optionally over the mask features by repeating the steps of FIGS. 3D-3I, FIGS. 4A-4E, FIGS. 5A-5C, FIGS. 6A-6D, FIGS. 7A-7E, or FIGS. 8A-8D. In some embodiments, the second set of anti-spacers may be formed by depositing a third masking layer to at least partially bury the second pattern and chemically altering portions of the third masking layer to form the second set of anti-spacers, as in the steps shown in FIGS. 3D-3I, FIGS. 4A-4E, or FIGS. 5A-5C. In other embodiments, the second set of anti-spacers may be formed by growing a second set of anti-spacers on the mask features, as in the steps shown in FIGS. 6A-6D, FIGS. 7A-7E, or FIGS. 8A-8D, and a third masking layer is deposited to fill spaces between the mask features covered with the anti-spacers.

Subsequently, the second set of anti-spacers are removed while leaving at least portions of the third masking layer to form additional intervening mask features. The mandrels, the intervening mask features, and the additional intervening mask features together define a third pattern having a pitch that is about a half of the pitch of the second pattern. The skilled artisan will appreciate that further pitch multiplication is also possible by repeating the process of forming and removing anti-spacers. The steps described above can be repeated if desired for more pitch reduction.

In other embodiments, a masking pattern formed by the methods described above may be used for additional pitch multiplication in combination with a process employing so-called spacers.

FIGS. 9A-9D illustrate a method of forming a masking pattern, using anti-spacers and spacers in accordance with one embodiment. In the illustrated embodiment, features forming a masking pattern can have a smaller pitch than the pitches P2 of the second patterns 260, 360, 460, 660, and 860 described above in connection with FIGS. 3I, 4G, 5D, 6E, 7F, and 8E.

Referring to FIG. 9A, the target layer 110 is provided. The details of the target layer 110 can be as described above in connection with FIGS. 3A, 4A, 5A, 6A, 7A, and 8A.

A first pattern 920 is formed on the target layer 110. The first pattern 920 may include mandrels 922 and intervening mask features 924. In the context of this embodiment, the mandrels 922 and the intervening mask features 924 may be collectively referred to as “first masking features.” The mandrels 922 and the intervening mask features 924 can be formed by the method described above in connection with FIGS. 3A-3I, FIGS. 4A-4G, FIGS. 5A-5D, FIGS. 6A-6E, FIGS. 7A-7F, or FIGS. 8A-8E. In certain embodiments, one or more hard mask layers (not shown) can be formed on the target layer 110, and the first pattern 920 can be formed on the one or more hard mask layers. The first pattern 920 may correspond to any one of the second patterns 260, 360, 460, 660, and 860 described above in connection with FIGS. 3I, 4G, 5D, 6E, 7F, and 8E.

As shown in FIG. 9A, the mandrels 922 have a first pitch P1 therebetween. In the first pattern 920, however, two neighboring first masking features (i.e., a mandrel 922 and a neighboring intervening mask feature 924) have a second pitch P2 that is about half of the first pitch P1. In some embodiments, the first masking features 922, 924 in the first pattern 920 may be trimmed or shrunk by an isotropic etching process to increase the distance between neighboring features.

Next, as shown in FIG. 9B, a layer 930 of spacer material may be blanket-deposited conformally over exposed surfaces, including the target layer 110 and the tops and sidewalls of the first masking features 922, 924.

The spacer material can be any material capable of use as a mask to transfer a pattern to the underlying target layer 110. The spacer material preferably: 1) can be deposited with good step coverage, 2) can be deposited at a temperature compatible with the target layer 110 and 3) can be selectively etched relative to the target layer 110. In one embodiment, the spacer material 930 is silicon oxide. In other non-limiting embodiments, the spacer material may be polysilicon or a low temperature oxide (LTO).

The spacer material may be deposited by any suitable method, including, but not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), spin-coating, or casting. ALD may have the advantages of both low temperature deposition and high conformality. The thickness of the layer 930 corresponds to the width of the spacers 935 and may be determined based upon the desired width of those spacers 935 (FIG. 9C). For example, in some embodiments, the layer 930 may be deposited to a thickness of about 20-80 nm and, optionally, about 40-60 nm. In some embodiments, the step coverage is about 80% or greater and, optionally, about 90% or greater.

In certain embodiments, the spacer material may be one of a class of materials available from Clariant International, Ltd. (so-called “AZ R” materials), such as the materials designated as AZ R200™, AZ R500™, and AZ R600™. In other embodiments, the spacer material may be an “AZ R” material with one or more inorganic components (e.g., one or more of titanium, carbon, fluorine, bromine, silicon, and germanium) dispersed therein. The “AZ R” materials contain organic compositions which cross-link upon exposure to acid released from chemically-amplified resist. Specifically, an “AZ R” material may be coated across photoresist, and subsequently the resist may be baked at a temperature of about 100° C. to about 120° C. to diffuse acid from the resist and into the “AZ R” material to form chemical cross-links within regions of the material proximate the resist. Portions of the material adjacent the resist are thus selectively hardened relative to other portions of material in which acids have not diffused. The material may then be exposed to conditions which selectively remove the non-hardened portions relative to the hardened portions. Such removal may be accomplished using, for example, 10% isopropyl alcohol in the ionized water, or a solution marketed as “SOLUTION C™” by Clariant International, Ltd. The processes using the “AZ R” materials are sometimes considered examples of RELACS (Resolution Enhancement Lithography Assisted by Chemical Shrink) processes. Examples of spacers formed by RELACS processes are disclosed by U.S. patent application Ser. No. 12/125,725, filed May 22, 2008, entitled “METHODS OF FORMING STRUCTURES SUPPORTED BY SEMICONDUCTOR SUBSTRATES” (inventor: Anton deVilliers).

Referring to FIG. 9C, the spacer layer 930 is then subjected to an anisotropic etch to remove spacer material from horizontal surfaces 912 of the target layer 110 and the first masking features 922, 924. In an embodiment where the spacer layer 930 is formed of a silicon oxide material, an etch, also known as a spacer etch, can be performed on the silicon oxide material, using a fluorocarbon plasma, e.g., containing CF4/CHF3, C4F8/CH2F2 or CHF3/Ar plasma. The etchants are chosen to be selective for the spacer material relative to the target layer 110.

Referring to FIG. 9D, the first masking features 922, 924 are removed to leave freestanding spacers 935. In one embodiment, the first masking features 922, 924 may be removed by an oxygen-containing plasma etch, such as an etch using HBr/O2/N2 and SO2/O2.

In the illustrated embodiment, the spacers 935 form a second pattern 950 having a third pitch P3. The third pitch P3 is roughly half of the second pitch P2 between neighboring first masking features 922, 924 in the first pattern 920. For example, where the first pitch P1 is about 200 nm, spacers 935 having a pitch of about 50 nm or less can be formed.

Next, the second pattern 950 provided by the spacers 935 is transferred into the target layer 110 (not shown). The pattern transfer can be performed using any suitable etch process selective for the target layer 110 relative to the spacers 935. Other details of this step can be as described above with reference to FIG. 3K or 4H. The target layer 110 may be further processed to form complete IC devices.

In some embodiments, three dimensional structures can be formed by the methods described above. The three dimensional structures can include, but are not limited to, lines, trenches, vias, pillars, posts, troughs, and moats.

FIGS. 10A-12C illustrate a method of forming an array of isolated trenches or vias in a target layer, using anti-spacers in accordance with some embodiments. In one embodiment, referring to FIGS. 10A and 10B, mandrels 1020 extending in the y-direction are formed by, for example, depositing and patterning a first resist layer on the target layer 110, as described above in connection with FIG. 3C. A second resist layer 1040 is formed over the mandrels 1020 and the target layer 110. First anti-spacers 1050 extending in the y-direction are formed around and on top of the mandrels 1020, thereby defining intervening mask features 1048 extending in the y-direction. The details of these steps can be as described above in connection with FIGS. 3D-3G.

Subsequently, the structure shown in FIGS. 10A and 10B is subjected to a freeze step such that the top surface of the second resist layer 1040 is maintained during a subsequent step. The details of this freeze step can be as described above in connection with FIG. 3E.

Referring to FIGS. 11A-11C, mandrels 1120 extending in the x-direction are formed by depositing and patterning a third resist layer on the second resist layer 1040 in the manner described above in connection with FIG. 3C. A fourth resist layer 1140 is formed over the mandrels 1120 and the second resist layer 1040. Second anti-spacers 1150 extending in the x-direction are formed around and on top of the mandrels 1120, thereby defining intervening mask features 1148 extending in the x-direction. The details of this process can be as described above in connection with FIGS. 3D-3G.

Subsequently, the structure shown in FIGS. 11A-11C is subjected to development using a suitable developer. The developer removes the second anti-spacers 1150, thereby exposing parts of the first anti-spacers 1050 and the intervening mask features 1048. Then, the developer further removes the exposed parts of the first anti-spacers 1050, thereby creating an array of holes 1160 defined by the features 1020, 1048, 1120, 1148, as shown in FIGS. 12A and 12B. Then, a pattern formed by the array of holes 1160 is transferred into the target layer 110 in the manner described above in connection with FIG. 3K. The mask features 520, 548 are sequentially removed. A resulting structure of the target layer 110, which includes an array of isolated holes 1005, is shown in FIG. 12C.

In certain embodiments, the holes 1005 can be filled with a material (e.g., a dielectric material, a conductive material, or a semiconductor) such that structures formed in the holes 1005 can serve as posts or pillars in a resulting electronic circuit. In other embodiments, the method described above may be adapted for forming isolated holes, e.g., contact vias or trenches, depending on the design of the electronic circuit.

In other embodiments, the mandrels 1020 and the intervening mask features 1048 extending in the y-direction can be formed by any of the methods described above in connection with FIGS. 3A-3I, FIGS. 4A-4G, FIGS. 5A-5D, FIGS. 6A-6E, FIGS. 7A-7F, or FIGS. 8A-8E. Then, the mandrels 1120 and the intervening mask features 1148 extending in the x-direction can be formed over the mandrels 1020 and the intervening mask features 1048 by any of the methods described above in connection with FIGS. 3A-3I, FIGS. 4A-4G, FIGS. 5A-5D, FIGS. 6A-6E, FIGS. 7A-7F, or FIGS. 8A-8E. In some embodiments, a freeze step is required after forming the mandrels 1020 and the intervening mask features 1048 and before forming the mandrels 1120 and the intervening mask features 1148. In other embodiments, no freeze step is required after forming the mandrels 1020 and the intervening mask features 1048 and before forming the mandrels 1120 and the intervening mask features 1148.

FIGS. 13A-15B illustrate a method of forming an array of pillars or posts in a target layer using anti-spacers. In one embodiment, referring to FIGS. 13A and 13B, mandrels 1320 extending in the y-direction are formed by depositing and patterning a first resist layer on the target layer 110, as described above in connection with FIG. 3C. Intervening mask features 1348 extending in the y-direction and alternating with the mandrels 1320 are formed by forming and removing anti-spacers as described above in connection with FIGS. 3D-3I. Subsequently, a pattern defined by the mandrels 1320 and intervening mask features 1348 is transferred into the target layer 110 in the manner described above in connection with FIG. 3K. Exposed portions of the target layer 110 are etched, as shown in FIG. 13B, defining elongated trenches or troughs 1302 alternating with elongated mesas 1301 (unetched portions) in the target layer 110.

Referring to FIGS. 14A-14C, mandrels 1420 extending in the x-direction are formed by depositing and patterning a third resist layer over the target layer 110 in the manner described above in connection with FIG. 3C. During this step, because the mandrels 1320 and the intervening mask features 1348 have not been subjected to a freeze step, the deposition of the third resist layer wipes the pattern formed by the mandrels 1320 and the intervening mask features 1348 (the deposited resist blends with the existing resist). Subsequently, intervening mask features 1448 extending in the x-direction and alternating with the mandrels 1420 are formed by forming and removing anti-spacers in the manner described above in connection with FIGS. 3D-3I. A pattern defined by the mandrels 1420 and the intervening mask features 1448 is transferred into the target layer 110, as shown in FIGS. 15A and 15B, in the manner described above in connection with FIG. 3K. Exposed portions of the elongated trenches or troughs 1302 of the target layer 110 are etched, as shown in FIG. 15A, defining isolated holes or vias 1303 in the target layer 110. Simultaneously, exposed portions of the mesas 1301 of the target layer 110 are etched, defining pillars or posts 1305, as shown in FIG. 15B. A resulting structure in the target layer 110, which includes an array of isolated pillars or posts 1305 and isolated holes 1303, is shown in FIG. 15C.

In other embodiments, the mandrels 1320 and the intervening mask features 1348 extending in the y-direction can be formed by any of the methods described above in connection with FIGS. 3A-3I, FIGS. 4A-4G, FIGS. 5A-5D, FIGS. 6A-6E, FIGS. 7A-7F, or FIGS. 8A-8E. Then, the mandrels 1420 and the intervening mask features 1448 extending in the x-direction can be formed over the mandrels 1320 and the intervening mask features 1348 by any of the methods described above in connection with FIGS. 3A-3I, FIGS. 4A-4G, FIGS. 5A-5D, FIGS. 6A-6E, FIGS. 7A-7F, or FIGS. 8A-8E.

Electronic devices, such as IC devices, typically include a plurality of conductive lines (for example, interconnects) and landing contact pads that electrically connect the conductive lines to other levels in the IC. The “landing contact pads” may also be referred to as “landing pads” or “contact tabs.” The conductive lines typically have a width narrower than the widths of the landing pads. A conventional pitch multiplication process using spacers allows formation of conductive lines having a narrower line-width than that allowed by an available photolithographic process. However, because a masking pattern defined by such spacers can only provide features having such a narrow line-width, it can be difficult to form larger width landing pads using spacers.

In some embodiments, a process involving anti-spacers may be used to simultaneously form conductive lines and landing pads integrated with the conductive lines. Such a process can provide a single masking pattern for forming pitch-multiplied conductive lines as well as landing pads wider than the conductive lines.

FIGS. 16A-16C illustrate a method of forming conductive lines and landing pads in an electronic device (for example, an IC circuit), using anti-spacers in accordance with some embodiments. Referring to FIG. 16A, mandrels 1620 are formed over a target layer 110 that is formed of a conductive material, such as copper, gold, silver, or an alloy thereof. Each of the mandrels 1620 may include a line mask feature 1622 that has a first width LW1, and a landing pad mask feature 1624 that has a second width LW2. The landing pad mask feature 1624 is connected to one end of the line mask feature 1622.

In the illustrated embodiment, the line mask features 1622 of the mandrels 1620 extend parallel to one another. In other embodiments, the configurations of the line mask features 1622 of the mandrels 1620 can vary, depending on the design of the electronic device formed by the method. The second width LW2 can be selected, depending on the size of a landing pad to be formed in the target layer 110, and is greater than the first width LW1. In one embodiment, the second width LW2 is about 0.5 to about 5 times greater than the first width LW1. The illustrated landing pad mask feature 1624 has a substantially circular shape, but the skilled artisan will appreciate the landing pad mask feature 1624 can have various other shapes such as a square shape, a rectangular shape, an oval shape, or the like, depending on the desired shape of the landing pad. The mandrels 1620 can be formed as described above in connection with FIGS. 3A-3C.

Referring to FIG. 16B, intervening mask features 1630 are formed between two neighboring ones of the mandrels 1620 by forming and removing anti-spacers (not shown). Each of the intervening mask features 1630 may include a line mask feature 1632 that has a third width LW3, and a landing pad mask feature 1634 that has a fourth width LW4. The line mask features 1632 of the intervening mask features 1630 extend parallel to one another and to the line mask features 1622 of the mandrels 1620. In the illustrated embodiment, the third width LW3 is substantially the same as the first width LW1, and the fourth width LW4 is substantially the same as the second width LW2. In other embodiments, the third width LW3 can be different from the first width LW1, and/or the fourth width LW4 can be different from the second width LW2. The intervening mask features 1630 can be formed as described above in connection with FIGS. 3D-3I.

In other embodiments, the mandrels 1620 and the intervening mask features 1630 can be formed by any of the methods described above in connection with FIGS. 4A-4G, FIGS. 5A-5D, FIGS. 6A-6E, FIGS. 7A-7F, or FIGS. 8A-8E.

Referring to FIG. 16C, a cut mask 1650 is provided over the structure of FIG. 16B. The cut mask 1650 includes an opening 1652 that exposes parts of the landing pad mask features 1634 of the intervening mask features 1630 (and optionally end parts of the landing pad mask features 1624 of the mandrels 1620) while blocking the other portions of the features 1620, 1630. The opening 1652 is shaped such that the landing pad mask features 1634 of the intervening mask features 1630 are electrically separated from one another by a subsequent etch process. The exposed parts of the landing pad mask features 1624, 1634 of the features 1620, 1630 are removed by any suitable etch process that can remove the materials of the landing pad mask features selectively relative to the target layer 110.

The mask 1650 is removed and the resulting features 1620, 1630 after the etch process are shown in FIG. 16D. A pattern defined by the mandrels and intervening mask features 1620, 1630 is transferred into the target layer 110 in the manner described above in connection with FIG. 3K.

In another embodiment, a pattern formed by the features 1620, 1630 shown in FIG. 16B is first transferred into the target layer 110, and then landing pads are defined by another etch step so as to be electrically isolated from one another. The skilled artisan will appreciate that various modifications can be made to the methods described above, depending on the design of the electronic device.

In the embodiments described above, the landing pads can be formed simultaneously with conductive lines, thus eliminating separate steps for defining and connecting the landing pads to conductive lines. Yet, the pitch of the conductive lines can be reduced at least to the same extent as in a conventional pitch multiplication process using spacers. While the embodiments above were described in connection with forming conductive lines and landing pads, the skilled artisan will appreciate that the embodiments can be adapted for forming various other structures or parts of electronic devices where different shapes or sizes of features are formed simultaneously.

In some embodiments, electronic devices, such as arrays in IC's, can be made by the methods described above. The electronic devices may also include a system including a microprocessor and/or a memory device, each of which includes features arranged in an array. Such a system may be a computer system, an electronic system, or an electromechanical system.

Examples of electronic devices include, but are not limited to, consumer electronic products, electronic circuits, electronic circuit components, parts of the consumer electronic products, electronic test equipments, etc. The consumer electronic products may include, but are not limited to, a mobile phone, a telephone, a television, a computer monitor, a computer, a hand-held computer, a personal digital assistant (PDA), a microwave, a refrigerator, a stereo system, a cassette recorder or player, a DVD player, a CD player, a VCR, an MP3 player, a radio, a camcorder, a camera, a digital camera, a portable memory chip, a washer, a dryer, a washer/dryer, a copier, a facsimile machine, a scanner, a multi functional peripheral device, a wrist watch, a clock, etc. Further, the electronic device may include unfinished intermediate products.

Thus, it will be understood that the invention can take the form of various embodiments, some of which are discussed above and below.

In one embodiment, a method of forming features in an electronic device includes forming mandrels defining a first pattern in a first masking layer on one or more underlying layers comprising a target layer. The first pattern includes spaces between the mandrels, and has a first pitch. The method also includes depositing a second masking layer to at least partly fill the spaces of the first pattern. The second masking layer contacts the one or more underlying layers through the spaces between the mandrels. The method further includes forming sacrificial structures to define gaps between at least parts of the mandrels and at least parts of the second masking layer; and after depositing the second masking layer and forming the sacrificial structures, removing the sacrificial structures to define a second pattern having a second pitch smaller than the first pitch. The second pattern includes the at least parts of the mandrels and intervening mask features alternating with the at least parts of the mandrels.

In another embodiment, a method of forming features in an electronic device includes photolithographically forming mandrels defining a first pattern in a first masking layer over a target layer. The first pattern includes spaces between the mandrels, and has a first pitch. The method also includes depositing a second masking layer to at least partially fill the spaces of the first pattern; forming sacrificial structures to define gaps between at least parts of the mandrels and at least parts of the second masking layer; and after depositing the second masking layer and forming the sacrificial structures, removing the sacrificial structures to define a second pattern having a second pitch smaller than the first pitch. The second pattern includes the at least parts of the mandrels and intervening mask features alternating with the at least parts of the mandrels.

In yet another embodiment, a method of forming an integrated circuit includes forming a first pattern comprising first lines extending substantially parallel to one another in a first direction over a target layer. Forming the first pattern includes: providing first mandrels in a first masking layer over the target layer, the first mandrels having spaces therebetween; depositing a second masking layer to at least partially fill the spaces between the first mandrels; and forming first sacrificial structures to define gaps between at least parts of the first mandrels and at least parts of the second masking layer. The method also includes forming a second pattern comprising second lines extending substantially parallel to one another in a second direction over the first pattern, the second direction being different from the first direction. Forming the second pattern includes: providing second mandrels in a third masking layer over the second masking layer, the second mandrels having spaces therebetween; depositing a fourth masking layer to at least partially fill the spaces between the second mandrels; and forming second sacrificial structures to define gaps between at least parts of the second mandrels and at least parts of the fourth masking layer. The method further includes: removing the first sacrificial structures; removing the second sacrificial structures; and etching the target layer through the first pattern, the second pattern, or a combination of the first and second patterns.

Although this invention has been described in terms of certain preferred embodiments, other embodiments that are apparent to those of ordinary skill in the art, including embodiments that do not provide all of the features and advantages set forth herein, are also within the scope of this invention. Accordingly, the scope of the present invention is defined only by reference to the appended claims.

Claims (31)

What is claimed is:

1. A method of forming features in an electronic device, the method comprising:

forming mandrels defining a first pattern in a first masking layer on one or more underlying layers comprising a target layer, the first pattern including spaces between the mandrels, and having a first pitch;

depositing a layer with a chemically active species in the spaces between the mandrels;

removing the layer with the chemically active species;

subsequently depositing a second masking layer to at least partly fill the spaces of the first pattern, the second masking layer contacting the one or more underlying layers through the spaces between the mandrels;

subsequently photolithographically defining a photolithographic pattern in a portion of the electronic device spaced apart from and on a same level as the mandrels;

forming sacrificial structures to define gaps between at least parts of the mandrels and at least parts of the second masking layer;

after depositing the second masking layer and forming the sacrificial structures, removing the sacrificial structures to define a second pattern having a second pitch smaller than the first pitch, wherein the second pattern includes the at least parts of the mandrels and intervening mask features alternating with the at least parts of the mandrels; and

subsequently subjecting the mandrels and intervening mask features to an anisotropic etch to round top corners of the intervening mask features.

2. The method of claim 1, wherein forming the mandrels comprises defining the mandrels in a photoresist layer or a hard mask layer.

3. The method of claim 1, further comprising providing one or more hard mask layers over the target layer, wherein forming the mandrels comprises forming the mandrels on the one or more hard mask layers.

4. The method of claim 1, wherein the first pattern has a first pitch, and wherein the second pattern has a second pitch that is about half of the first pitch.

5. The method of claim 1, wherein forming the sacrificial structures comprises chemically altering portions of either or both of the mandrels and the second masking layer immediately adjacent to boundaries between the mandrels and the second masking layer, thereby increasing an etchability of the chemically altered portions, and wherein removing the sacrificial structures comprises removing the chemically altered portions while leaving unaltered portions of the mandrels and the second masking layer to together define the second pattern, the unaltered portions of the second masking layer forming the intervening mask features.

6. The method of claim 5, wherein chemically altering the portions comprises chemically altering portions of the second masking layer immediately adjacent to the mandrels, while altering substantially no portion of the mandrels.

7. The method of claim 5, wherein chemically altering the portions comprises chemically altering portions of the mandrels immediately adjacent to the second masking layer, while altering substantially no portion of the second masking layer.

9. The method of claim 5, wherein chemically altering the portions comprises chemically altering portions of both the mandrels and the second masking layer.

10. The method of claim 5, wherein chemically altering the portions comprises diffusing the chemically active species into the portions.

11. The method of claim 5, wherein forming the mandrels comprises defining the mandrels in a photoresist layer, further comprising subjecting the mandrels to a surface treatment such that the first pattern is protected while depositing the second masking layer.

13. The method of claim 5, wherein the second masking layer comprises a chemically amplified resist.

14. The method of claim 13, wherein the second masking layer comprises an acid-based or base-based chemically amplified resist.

15. The method of claim 5, wherein chemically altering the portions comprises subjecting the portions to a bake.

16. The method of claim 15, wherein subjecting the portions to the bake comprises heating the portions to a temperature between about 110° C. and about 160° C.

17. The method of claim 5, wherein chemically altering the portions comprises chemically altering the portions such that the chemically altered portions are more soluble in a developer than the unaltered portions.

19. The method of claim 18, further comprising removing top portions of the intervening mask features with the developer after removing the chemically altered portions.

20. The method of claim 19, wherein removing the top portions of the intervening mask features comprises removing the top portions of the intervening mask features such that a height of the intervening mask features from the target layer is substantially the same as a height of the mandrels from the target layer.

21. The method of claim 1, further comprising transferring the second pattern into the target layer.

22. The method of claim 1, further comprising, after removing the sacrificial structures:

depositing a third masking layer to at least partially fill spaces of the second pattern;

forming second sacrificial structures to define gaps between at least parts of the second pattern and at least parts of the third masking layer; and

after depositing the third masking layer and forming the second sacrificial structures, removing the second sacrificial structures to define additional intervening mask features, wherein the mandrels, the intervening mask features, and the additional intervening mask features together define a third pattern that has a third pitch smaller than the second pitch.

23. The method of claim 1, wherein the mandrels comprise line mask features extending in a first direction substantially parallel to one another;

wherein the mandrels further comprise landing pad mask features at least partially aligned with one another, each of the landing pad mask features being connected to one end of a respective one of the line mask features thereof;

wherein the intervening mask features comprise line mask features extending in the first direction substantially parallel to one another and alternating with the line mask features of the mandrels;

wherein the intervening mask features further comprise landing pad mask features alternating with the landing pad mask features of the mandrels, each of the landing pad mask features of the intervening mask features being connected to one end of a respective one of the line mask features thereof, two or more of the landing pad mask features of the intervening mask features being connected to one another, wherein the widths of the landing pad mask features are greater than the widths of the line mask features.

24. The method of claim 23, further comprising disconnecting the landing pad mask features of the intervening mask features.

providing a cut mask over the mandrels and the intervening mask features, the cut mask exposing portions of the intervening mask features that connect the two or more landing pad mask features of the intervening mask features; and

removing the exposed portions of the intervening mask features.

26. The method of claim 24, further comprising etching the target layer through a pattern defined at least partly by the mandrels and the intervening mask features after disconnecting the landing pad mask features of the intervening mask features.

27. The method of claim 1, wherein subsequently photolithographically defining the photolithographic pattern is performed after forming sacrificial structures.

28. The method of claim 1, wherein subsequently photolithographically defining the photolithographic pattern forms the photolithographic pattern in a peripheral region of the electronic device.

29. A method of forming features in an electronic device, the method comprising:

photolithographically forming mandrels defining a first pattern in a first masking layer over a target layer, the first pattern including spaces between the mandrels, and having a first pitch;

depositing a layer with a chemically active species in the spaces between the mandrels;

removing the layer with the chemically active species;

subsequently depositing a second masking layer to at least partially fill the spaces of the first pattern;

subsequently photolithographically defining a photolithographic pattern in a portion of the electronic device spaced apart from and on a same level as the mandrels;

forming sacrificial structures to define gaps between at least parts of the mandrels and at least parts of the second masking layer;

after depositing the second masking layer and forming the sacrificial structures, removing the sacrificial structures to define a second pattern having a second pitch smaller than the first pitch, wherein the second pattern includes the at least parts of the mandrels and intervening mask features alternating with the at least parts of the mandrels; and

subsequently subjecting the mandrels and intervening mask features to an anisotropic etch to round top corners of the intervening mask features.

Method for forming a structure in the surface of a substrate - with an auxiliary structure laterally bounding an initial masking structure, followed by selective removal of masking structure using the auxiliary structure as an etching mask

Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry

Semiconductor integrated circuit device and the process of manufacturing the same having poly-silicon plug, wiring trenches and bit lines formed in the wiring trenches having a width finer than a predetermined size

Method for forming a structure in the surface of a substrate - with an auxiliary structure laterally bounding an initial masking structure, followed by selective removal of masking structure using the auxiliary structure as an etching mask

Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry

Semiconductor integrated circuit device and the process of manufacturing the same having poly-silicon plug, wiring trenches and bit lines formed in the wiring trenches having a width finer than a predetermined size