CDNLive: Verification Challenges Driving Innovation

Verification is a strong theme at this year’s CDNLive conference, with more than half the papers looking at the tips and challenges of delivering a fully functional design.

Hybrid verification techniques need to bring together high-level modeling, RTL, and software development, and it seems there are as many different ways to do this as there are SoC developers.

David Allen of Cadence looks at several case studies of how this challenge is being tackled successfully. These range from Nvidia’s abstract CPU model coupled with RTL to AMD’s cycle accurate core simulation coupled with peripherals in a hardware emulator. Broadcom takes yet another approach co-developing and co-validating hardware and software before the SoC tapeout. All of these different approaches can be brought together with coordinated interfaces for verification and validation.

There are plenty of other ways of enhancing the verification chain, particularly with mixed signal designs. SMDH is combining SystemC and SpecMan with SystemVerilog for verification of mixed signal designs, while Jerry Chang shows how Texas Instruments clearly defined the interfaces of a power management SoC and the verification tools to make sure the whole system could be easily debugged.

Meanwhile STMicroelectronics is using UVM to derive the verification of an image processing chip from a transaction-based TLM reference model. Abhishek Jain looks at how this speeds up verification without having to wait for the RTL to be available.

Verification can even be used to improve the efficiency of the implementation. LSI is using formal methods to identify unused code, not in the software but in the RTL. This helps improve the test coverage but also identifies code that is not needed, boosting the efficiency of the design, according to Yuri Tatarnikov and Khaled Labib of LSI.

Several tracks at the conference are dedicated to verification, and the technology also appears in other elements such as high-level design tools, helping SoC developers address key challenges in their designs.