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Input Timing Constraints Setup time: t setup = time before the clock edge that data must be stable (i.e. not changing) Hold time: t hold = time after the clock edge that data must be stable Aperture time: t a = time around clock edge that data must be stable (t a = t setup + t hold ) 5

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Clock Skew The clock doesnt arrive at all registers at the same time Skew is the difference between two clock edges Examine the worst case to guarantee that the dynamic discipline is not violated for any register – many registers in a system! 14