New technology doubles its area capacitance & improves performances at high-frequency

FUJITSU INTERCONNECT TECHNOLOGIES LIMIED (Headquarters: Nagano City, President & CEO: Yoichi Bando) has developed the New enhanced TFC embedding packaging substrate “GigaModule-EC 2.0”. And we are pleased to announce that we have started to ship a sample substrate. This new technology “GigaModule-EC 2.0” doubles its electrical capacitance per unit area, comparing with the current TFC embedding(2) substrate “GigaModule-EC” for the latest high-end servers(3).

Background

To make high performance and energy-saving semiconductor devices work stably and correctly, power management is becoming very important in the power supply system. A decoupling capacitor with large capacity and low power impedance, at a wide range of frequency up to ultra-high frequency, is strongly needed for the power supply stabilization.
It is necessary to place the decoupling capacitor at very short distance from a device to achieve good power integrity with low power inductance. However, the main difficulty is to secure installing place for the decoupling capacity and a space for enough capacitance for the latest semiconductor packaging technology, where miniaturization is necessary.

Features

With this new technology TFC is aimed to be embedded just under the die in a semiconductor packaging substrate, enabling low power impedance at a wide range of high frequency area. This new technology “GigaModule-EC 2.0” doubles its electrical capacitance per unit area, comparing with the current technology “GigaModule-EC”.

The decoupling performance is effective in a wide area, ranging from low to high frequency, by embedding TFC right under the semiconductor. By this area capacitance increase, the effective applications expand to uses such as large switching currents.

2.

Effective use of spaces

The die-bonding area and the wiring area can be effectively used by embedding TFC into the lamination layer, contributing to the miniaturization of semiconductor packaging substrates. This area capacitance increase contributes to the further miniaturization of the packaging substrates.

3.

Electric capacitance is designed as needed

The shape of the TFC capacitor is formed with the etching process, so the electric capacity can be set as designed.
The area density of electric capacity of TFC is very large, 2.0μF/cm2, and can be used for various usages.

Packaging Substrate Sample

Fig.1 Layer constructions of GigaModule-EC2.0

Fig.2 Outlook of sample substrate

Features of Substrate Sample

Features of TFC

Layer Construction

8 Layers Coreless

Thickness

0.4mm

Bump pitch

150μm

# of TFC embedded

1 set

Electric capacity

2.0μF/cm2

Relative dielectric constant

1,000 or less

Tanδ

0.2 or less

Operating voltage (max)

4.0V

TFC thickness (max)

35μm (after embedded)

Data Source: TDK Corporation

Applying the GigaModule-EC 2.0 series for semiconductor substrates packaging ensures the performance gain of semiconductor devices and the improvement of mounting density, improving customer’s product competitiveness and innovative performance.

[1]

Thin Film Capacitor

[2]

The TFC technology, jointly developed with Sony Semiconductor Solutions Limited, is used for the TFC embedding process.

[3]

Packaging substrates of the latest SPARC Processor “SPARC64™ XII” for Fujitsu UNIX Server “SPARC M12” have started to use this TFC technology.