Intel May Finally Utilize Silicon-on-Insulator for 22nm Process Tech.

After years of criticizing silicon-on-insulator technology, Intel Corp. may finally adopt it to increase performance of its future chips, according to an analyst. Believe it or not, but the adoption may be just a year away as the chipmaker if rumoured to endorse SOI with its 22nm process technology.

''We believe Intel will introduce a germanium (III V) channel and full depleted SOI at 22nm. This will give Intel a quantum leap in performance over what they are achieving and leave competitors 3-5 years behind. The 22nm process should be in manufacturing at Intel in Q4 2011," said Gus Richard, an analyst with Piper Jaffray & Co., in a report, according to EETimes web-site.

In the recent several quarters Intel has been revealing pieces of information about its 22nm process technology/technologies that will be used to manufacture Ivy Bridge-generation of microprocessors as well as system-on-chip devices. The company has not said a word about usage of SOI.

The Santa Clara, California-based maker of central processing units (CPUs) displayed its first 22nm test wafer with SRAM memory as well as logic circuits to be used in future Intel microprocessors in September '09 and said that the process technology relies on a third-generation high-k metal gate transistor technology for improved performance and lower leakage power. In early April, 2010, the company said that in case of 22nm fabrication process Intel’s research group had a variety of novel transistor and interconnect ideas in the “pipeline”, including III-V channel materials, multi-gate transistors, 3-D stacking and others. In June '10 Intel revealed a paper describing development of a 22nm floating body cell (FBC) memory on a bulk wafer "of the kind in use in high volume manufacturing today" and said that earlier results were achieved on much more expensive SOI wafers, a rather clear implication that SOI is not a part of its 22nm.

Generally speaking, nothing certain is presently known about Intel's 22nm process technology. But while the probability of SOI usage on 22nm is not too high, there is no smoke without fire, and the company may utilize silicon-on-insulator wafers sometime in future.

''Intel's lithography roadmap is to use immersion double and multi- patterning at the 22-nm and 16-nm nodes. We note that Intel has consistently pushed lithography one generation further than any other manufacturer. What enables the company to do this in our view is the fact it is vertically integrated (design and manufacturing), has its own mask shop and uses restrictive design rules. At 11nm in 2015, Intel's options are multi-beam e-beam, EUV and quintuple patterning with 193 immersions. It is questionable whether any of these alternatives will be economically viable," added Mr. Richard.

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At 22nm, Intel will stay on a bulk technology, Bohr said. Intel is on track to introduce its 22nm MPUs at the end of 2011.

Now working on pathfinding technologies for the 15nm generation, Bohr said, "Fully depleted technologies have inherent low-power advantages." Intel is exploring a range of options, Bohr said, including tri-gate devices and fully depleted planar technologies. Intel has a decision to make in about six months [mid-2010], when it will lock in the process architecture for its 15nm technology.

A planar, fully depleted (FD) technology could only be constructed on a silicon-on-insulator (SOI) substrate, Bohr said, but a tri-gate or finFET device could be created on either bulk or SOI wafers.

Gartner analyst Freeman said he believes that Intel and IBM will stick by their traditional guns, with Intel shying away from SOI substrates as long as possible and IBM pushing SOI as hard as it can. The Intel tri-gate structure, Freeman noted, "doesn't have to use SOI, because the area gets so small. There is still leakage at the substrate, but it is not a given that Intel has to go to SOI."