Grasp the critical issues for a functioning JESD204B interface

JESD204B is a recently approved JEDEC Standard for serial data interfacing between converters and digital processing devices. As a third-generation standard, it addresses some of the limitations of the earlier versions. Among the benefits of this interface are reductions in required board area for data-interface routing, reduces setup and hold timing requirements and enables smaller packages for converter and logic devices. New analog/digital converters from various vendors, such as the AD9250 from Analog Devices, use this interface.

There is a tradeoff to realizing the benefits of JESD204B, as it has complexities and subtleties which distinguish it from existing interface formats and protocols. As with any standard, it is clear that the interface must function seamlessly to gain popularity and traction versus more common interfaces, such as single data rate or double data rate CMOS or LVDS. Although the JESD204B standard is documented by JEDEC, some specific information about it is subject to interpretation or may be spread over multiple references. It is also obvious that it would be extremely helpful if there was a concise guide that provided an overview of the standard, how it works, and how to troubleshoot it if issues arise.

This article explains the interface from an ADC to FPGA for JESD204B, how to identify when it’s working right, and, perhaps more important, how troubleshoot it if something isn’t quite right. The troubleshooting techniques discussed can use commonly available test and measurement equipment including oscilloscopes and logic analyzers along with software tools such as the Chipscope from Xilinx or SignalTap from Altera. Interface signaling is also explained to allow a single or multiple approaches to visualize the signaling.

JESD204B overviewThe JESD204B standard provides a method to interface one or multiple data converters to a digital-signal processing device (typically, an ADC or DAC to an FPGA) over a higher-speed serial interface compared to the more typical parallel data transfers. The interface, which runs at up to 12.5 Gbps/Lane, uses a framed serial data link with embedded clock and alignment characters. The interface eases implementation of the data interface of high-speed converters by reducing the number of traces between devices, thus reducing trace-matching requirements, and removing setup- and hold-timing constraint issues. Since a link needs to be established prior to data transfer, there are new challenges and techniques required to identify that the interface is working properly and, if not, what to do.

Starting with a brief explanation of how the standard works. JESD204B use three phases to establish the synchronized link: Code Group Synchronization (CGS), Initial Lane Synchronization (ILAS), and Data Transmission Phase. Required signals for the link are a shared reference clock (device clock), at least one differential CML physical data electrical connection (called a lane) and at least one other synchronization signal (SYNC~ and possibly SYSREF). The signals used depend upon the Subclass:

Subclass 0 is adequate in many cases and so will be the focus of this article. Subclass 1 and Subclass 2 provide a method to establish deterministic latency. This is important in application when synchronizing multiple devices or system synchronization or fixed latency is required (such as when a system needs a known sampling-edge for an event or an event must react to an input signal within a specified time).

Figure 1 shows a simplified JESD204B Link from the Tx Device (ADC) to the Rx Device (FPGA), with data from one ADC going over one lane.

Figure 1. JESD204B link diagram for 1 ADC to an FPGA through 1 Lane.(Click Here to see a larger, more detailed version of this image)

Although there are many variables within the JESD204B specification, some have particular importance when establishing a link. These key variables from the specification are (Note: these values are typically represented as ‘X-1’) :

M : Number of converters

L : Number of Physical Lanes

F: Number of Octets per Frame, also

K : Number of frames per Multiframe

N & N’ : Converter Resolution and Number of bits used per sample (multiple of 4), respectively. N’ value is N value plus control and dummy bits.

Subclass 0: Synchronization StepsAs noted above, many applications can use the relatively simpler Subclass 0 Mode of operation. This is also the easiest mode to establish and for which to verify a link. Subclass 0 uses three phases to establish and monitor synchronization: CGS Phase, ILAS Phase and Data Phase. The figures associated with each phase present the data in different formats, as they might be seen on an oscilloscope, logic analyzer or FPGA virtual I/O analyzer such as Xilinx ChipScope or Altera SignalTap.The Code Group Synchronization (CGS) PhaseThe most significant parts of the CGS Phase that can be observed over the link are shown in Figure 2, along with a description of the five highlighted points of the figure.

Figure 2. Logic output of JESD204B Subclass 0 link signals during CGS Phase (assumes two lanes, one device with two ADCs). (Click Here to see a larger, more detailed version of this image)

The RX issues a synchronization request by driving the SYNC~ pin low.

The TX transmits /K28.5/ symbols (10 bits/symbol), unscrambled beginning on the next symbol.

The RX synchronizes when it receives at least 4 consecutive /K28.5/ symbols without error and then the RX drives the SYNC~ pin High.

RX must receive at least four 8B/10B Characters without error otherwise synchronization fails and the link stays in CGS phase.

CGS Phase ends and ILAS Phase begins.

The /K28.5/ character, also just known as /K/ within the JESD204B standard, can be exhibited as shown in Figure 3. The standard requires a running neutral disparity. The 8B10B coding allows a balanced sequence that on average contains an equal amount of 1’s and 0’s. Each 8B10B character can have a positive (more 1’s) or negative (more 0’s) disparity, and the parity of the current character is determined by the current sum of the previous characters sent and this is typically accomplished by alternately transmitting a positive parity word, followed by a negative parity word; the figure shows both polarities of the K28.5 Symbol.

Figure 3. Logic Output of K28.5 Characters and how it propagates through the JESD204B Tx signal path.(Click Here to see a larger, more detailed version of this image)

Note these key points:

Serial Value represents the logic levels of the 10 bits transmitted over the lane as would be seen by an Oscilloscope measuring the physical interface.

8B/10B Value represents the logic values (10 bits) transmitted over the lane as might be seen by a logic analyzer measuring the physical interface.

Data value and Data logic represent the logic levels of the symbol inside the JESD204B Tx block before 8B10B coding, as would be seen on in an FPGA logic analysis tool such as Xilinx’s ChipScope or Altera’s SignalTap.

Symbol represents the hex value of the character that is to be transmitted, noting parity for PHY layer

Character is shown to indicate the JESD204B Character as it is referred to in the JEDEC specification.

The ILAS PhaseIn the ILAS phase there are four multiframes which allow the RX to align lanes from all links and also allows the RX to verify the link parameters. Alignment is required to accommodate trace length differences and any character skew the receivers introduce. Each successive multiframe immediately follows the previous one of four, Figure 4. Whether or not the scrambling link parameter is enabled, ILAS is always transmitted without scrambling.

Figure 4. Logic output of JESD204B Subclass 0 link signals during ILAS Phase.(Click Here to see a larger, more detailed version of this image)

The ILAS phase begins after SYNC~ has been de-asserted (goes high). After the transmit block has internally tracked (within the ADC) a full Multiframe, it will begin to transmit four multiframes. Dummy samples are inserted between the required characters so that full multiframes are transmitted, Figure 5.

Figure 5. Figure of K character [K28.5], R character [K28.0], A character [K28.3] and Q character [K28.4].(Click Here to see a larger, more detailed version of this image)

The four multiframes consist of the following:

Multiframe 1: Begins with an /R/ character [K28.0] and ends with an /A/ character [K28.3].

Multiframe 2: Begins with an /R/ character followed by a /Q/ [K28.4] character, followed by link configuration parameters over 14 configuration octets (Table 1), and ends with an /A/ character.

Data phase with Character Replacement enabledIn the data-transmission phase, frame alignment is monitored with control characters. Character replacement is used at the end of frames. There is no additional overhead to accommodate data or frame alignment during the Data Phase. Character replacement allows an Alignment Character to be issued at a Frame Boundary ‘If and Only If’ the last character of the current frame may be replaced with the Last Character of the Last Frame; facilitating (occasional) confirmation that the alignment has not changed since the ILAS sequence.

Character replacement in the transmitter occurs in the following instances:

If scrambling is disabled and the last octet of the frame or multiframe equals the octet value of the previous frame.

If scrambling is enabled and the last octet of the multiframe is equal to 0x7C, or the last octet of a frame is equal to 0xFC.

Transmitters and Receivers each maintain a MultiFrame Counter (LMFC) that perpetually count to (F*K)-1 and then wrap back to ‘0’ to count again (ignoring internal word width). A common (sourced) SYSREF is issued to all transmitters and receivers which use the SYSREF to reset their LMFC’s, after which all LMFC’s should be synchronized (within one clock) to each other.

At the release of SYNC (seen by all devices) the transmitter begins ILAS at the next (TX) LMFC wrap to ‘0’. If F*K has been properly set to be greater than the (Transmit Encode time)+(Line Propagation time)+(Receiver Decode time), Received Data will propagate out of the Receiver’s SERDES before the next LMFC. The receiver will pass the data into a FIFO, which will begin outputting data at the next (RX) LMFC boundary. This ‘known relationship’ between the transmitter’s SERDES input and the receiver’s FIFO output are known as the ‘Deterministic Latency’.What can go wrong?JESD204B can be a complicated interface standard, with many operational subtleties. Finding out why it is not working requires a good understanding of likely scenarios:

Stuck in CGS mode: If SYNC stays at logic low level; or pulse high for <4 Multiframe:

1) Checking the board, un-powered:

SYSREF and SYNC~ signaling should be dc coupled.

With the board unpowered, check that the board SYNC~ connections from the SYNC~ source (typically from the FPGA or DAC) to the SYNC~ input (typically ADC or FPGA) are good and low impedance.

Check that the pull down or pull up resistors are not dominating the signaling, for example if values are too small or shorted and therefore cannot be driven correctly.

Verify that the differential-pairs traces (and cables, if used) of JESD204B link are matched.

Verify differential impedance of the traces is 100 ?.

2) Checking the board, powered:

If there is a buffer/translator in the SYNC path, make sure it is functioning properly.

Check that SYNC~ source and board circuitry (both SYNC+ and SYNC- , if differential) are properly configured to produce logic levels compliant for the SYNC~ Receive device. If logic level is not compliant, then review circuitry for source and receive configurations to find the problem. Otherwise consult device manufacturer.

Check that the JESD204B Serial Transmitter and board circuitry are properly configured to produce the correct logic levels for the JESD204B Serial Data Receiver. If logic level is not compliant review circuitry of source and receive configurations to find the problem. Otherwise consult device manufacturer.

3) Checking SYNC~ signaling:

If SYNC~ is static and logic low, the link is not progressing beyond the CGS Phase. There is either an issue with the data being sent, or the JESD204B receiver is not decoding the samples properly. Verify /K/ characters are being sent, verify receive configuration settings, verify SYNC~ source, review board circuitry and consider overdriving SYNC~ signal and attempt to force link into ILAS mode to isolate link RX vs TX issues. Otherwise consult device manufacturer.

If SYNC~ is static and logic high, verify the SYNC~ logic level is configured correctly in the source device. Check pull-up and pull-down resistors.

If SYNC~ pulses high and returns to logic-low state for less than six multiframe periods, the JESD204B Link is progressing beyond the CGS phase but not beyond ILAS phase. This would suggest the /K/ characters are okay and the basic function of the CDR are working. Proceed to ILAS Troubleshooting section.

If SYNC~ pulses high for a duration of more than six Multiframe periods, the Link is progressing beyond the ILAS phase and is malfunctioning in the Data Phase; see the Data phase section for troubleshooting tips.

4) Checking Serial Data

Verify the TX data rate and the receiver’s expected rate are the same.

Measure lanes with high-impedance probe (differential probe, if possible); if characters appear incorrect, make sure lane differential traces are matched, the return path on the PCB is not interrupted, and devices are properly soldered on the PCA. Unlike the (SEEMINGLY) random characters of ILAS and Data-Phase, CGS characters are easily recognizable on a scope (if a high-enough speed scope is available).

Verify /K/ characters with high impedance probe. (If /K/ characters are correct, the Tx side of the link is working properly. If /K/ characters are not correct, the Tx device or the board Lanes signal have an issue.

If DC coupled, verify that the transmitter and receiver common-mode voltage is within specification for the devices. (Depending upon implementation, the transmitter common mode voltage can range from 490 to 1135 mV. Depending upon implementation, the receiver common mode voltage can range from 490 to 1300 mV.)

Verify the transmitter CML differential voltage on the Data Lanes (Note: the CML differential voltage is calculated as 2 times the voltage swing of each leg of the signal). (The transmitter CML differential voltage can range from 0.5 to 1.0Vpk-pk for speeds up to 3.125 Gbps. The transmitter CML differential voltage can range from 0.4 to 0.75Vpk-pk for speeds up to 6.374 Gbps. The transmitter CML differential voltage can range from 0.360 to 0.770Vpk-pk for speeds up to 12.5 Gbps.)

Verify the receiver CML differential voltage on the Data Lanes (Note: the CML differential voltage is calculated as 2 times the voltage swing of each leg of the signal). (The receiver CML differential voltage can range from 0.175 to 1.0Vpk-pk for speeds up to 3.125 Gbps. The receiver CML differential voltage can range from 0.125 to 0.75Vpkpk for speeds up to 6.374 Gbps. The receiver CML differential voltage can range from 0.110 to 1.05Vpk-pk for speeds up to 12.5 Gbps.)

If pre-emphasis is an option, enable and observe data signals along the data path.

Verify that the M and L values match between the Transmitter and Receiver, otherwise the data rates may not match. For example, M=2 and L=2 will expect ½ the datarate over the serial interface as compared to the M=2 and L=1 case.

Ensure the Device Clock going to the transmitter and receiver is phase locked and at the correct frequency.

Can’t get beyond ILAS mode: If SYNC pulses high for approximately 4 Multiframes:

1) Link parameter conflicts

Verify link parameters are not offset by 1 (many parameters are specified as value -1)

Verify ILAS Multiframes are transmitting properly, verify Link parameters on the Tx device, the RX device and those transmitted in ILAS second Multiframe.

2) Verify all lanes are functioning properly. Ensure there are no Multilane/Multilink conflicts.

Get into data phase but occasionally link resets (returns to CGS and ILAS before returning to Data phase):

Invalid setup and hold time of Periodic or Gapped Periodic SYSREF or SYNC~ signal.

Link Parameter conflicts

Character replacement conflicts

Scrambling problem, if enabled

Lane data corruption, noisy or jitter could force the Eye Diagram to close

Spurious clocking or excessive jitter on Device Clock

Other general tips when troubleshooting link:

Run converter and link at slowest allowed speed, this allows use of lower-bandwidth measurement instruments that are more readily available.

Set minimum allowed combinations of M, L, K, S

Use test modes when possible

Use Subclass 0, for troubleshooting

Disable scrambling while troubleshooting

This troubleshooting guide cannot be all inclusive, but provides a good basic baseline for an engineer working with and wanting to learn about a JESD204B link.

This summary of the JESD204B specification and provides practical information about the Link. Hopefully, engineers getting involved with this latest high-performance interface standard will find it informative, and helpful if troubleshooting is required.

About the authorsAnthony Desimone is an Application Engineer in the High Speed Converter Group at Analog Devices. He has a BSEE from the University of Lowell (Massachusetts) and an MSEE from Tufts University.

Michael Giancioppo is an Application Engineer in the High Speed Converter Group at Analog Devices.

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Analog Devices is not planning on releasing JESD204 IP for FPGA use. Instead, interoperability work is ongoing with FPGA vendors and IP houses to ensure that the available IP works properly with our converters. This allows the designer to select an IP that is optimized for their chosen logic device and application.
Analog Devices offers an FPGA reference design section on the wiki page (wiki.analog.com) including one for a JESD204B Analog to digital converter (AD9250). The AD9250 JESD204B reference design is located at: wiki.analog.com/resources/fpga/xilinx/interposer/ad9250.

Hi guys,
This looks like a good, practical overview of the JESD204B standard. Since I'm sure Analog Devices would like this to be as easy as possible for people to adopt, are you planning to release a Verilog or VHDL IP core that engineers can just drop in and connect to FPGA transceivers? The standard seems straightforward but it looks like there's a fair amount of firmware development involved. Just curious, I know there are other manufacturers would probably gain from such an effort on your part.
Thanks!