With the approach of the limits imposed by the silicon technolgy and advent of the multicore era, the EDA community is faced with the challenge on how to efficiently manage the -possibly vast - amount of resources that are projected to being placed in future MPSoCs. These challenges requires a strong multidisciplinary approach, spanning from new power management techinques, innovative computer architecures, operating systems support, compilers, laguages and developers' support.
Computer architects, in particular, are developing new techniques to anticipate the increased complexity of the MPSoCs of the future. Memory hierarchies, in particular, are drawing relevant attention as they are already known to be a critical bottleneck of this generation's MPSoCs.
A promising approach to address these issues roots itself in the Autonomic Computing initiative, which claims that higher performance may be attained by enabling MPSoCs to monitor and adequatly adapt themselves at runtime based upon varying environment conditions and users' goals. This adaptation may take the form of a mechanism to vary number or kind of cores, the kind of cache hierarchy or the power requirements of the MPSoC itself.
In this thesis, the focus is set on the memory hirarchy and organization in the next generation of MPSoCs. Particular emphasis is placed on the caching subsystem, which is adequately augmented so as to allow it to monitor and adapt itself to varying operating conditions, advancing the state of the art of adaptive cache mechanisms. An adaptive cache coherent protocol is also developed to cope with the peculiar charachteristics of the adaptive cache system.