Jas

Abhijit Jas, Austin, TX US

Patent application number

Description

Published

20090172529

DEVICE, SYSTEM, AND METHOD FOR OPTIMIZED CONCURRENT ERROR DETECTION - A method, apparatus and system for accepting a plurality of user-selected properties pre-designated for detecting errors in portions of a circuit, accepting a plurality of user-selected erroneous outputs, each of which may correspond to one of the plurality of user-selected set of properties, executing a simulation of the circuit for each of the plurality of user-selected properties, detecting in the output of the simulation, one of the plurality of user-selected erroneous outputs of the circuit for the corresponding one of the plurality of user-selected properties, and performing error correction on the circuit for the corresponding one of the plurality of user-selected properties. A method, apparatus and system for automatically selecting a subset of a set of inputs which when input into a circuit simulation generate erroneous output data to a primary output of the circuit and performing error correction on the circuit therewith. Other embodiments are described and claimed.

07-02-2009

20120232825

FUNCTIONAL FABRIC-BASED TEST CONTROLLER FOR FUNCTIONAL AND STRUCTURAL TEST AND DEBUG - A Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to the Test Wrappers via an interconnect fabric. The Test Wrappers employ interface with one or more test ports to provide test data, control, and/or stimulus signals to the IP block to facilitate circuit-level testing of the IP block. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric. The TAM may be implemented in a fabric-to-fabric bridge, enabling testing of IP blocks connected to fabrics on both sides of the bridge.

09-13-2012

20120233504

FUNCTIONAL FABRIC BASED TEST ACCESS MECHANISM FOR SOCS - A Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to the Test Wrappers via an interconnect fabric. The Test Wrappers employ one or more test ports to provide test data, control, and/or stimulus signals to the IP block to facilitate circuit-level testing of the IP block. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric.

09-13-2012

20120233514

FUNCTIONAL FABRIC BASED TEST WRAPPER FOR CIRCUIT TESTING OF IP BLOCKS - A Test Wrapper and associated Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to one or more Test Wrappers via an interconnect fabric. The Test Wrappers interface with one or more IP test ports to provide test data, control, and/or stimulus signals to the IP blocks to facilitate circuit-level testing of the IP blocks. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric. Test wrappers may also be configured to test multiple IP blocks comprising a test partition.

09-13-2012

20130268808

FUNCTIONAL FABRIC BASED TEST ACCESS MECHANISM FOR SOCS - A Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to the Test Wrappers via an interconnect fabric. The Test Wrappers employ one or more test ports to provide test data, control, and/or stimulus signals to the IP block to facilitate circuit-level testing of the IP block. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric.

10-10-2013

Patent applications by Abhijit Jas, Austin, TX US

Frank Jas, Scotts Valley, CA US

Patent application number

Description

Published

20150242628

System and Method for Detection of Malicious Hypertext Transfer Protocol Chains - A system configured to detect malware is described. The system configured to detect malware including a data collector configured to detect at least a first hypertext transfer object in a chain of a plurality of hypertext transfer objects. The data collector further configured to analyze at least the first hypertext transfer object for one or more events. And, the data collector configured to generate a list of events based on the analysis of at least the first hypertext transfer object.

08-27-2015

20150244730

System And Method For Verifying And Detecting Malware - A system configured to detect malware is described. The system including an infection verification pack configured to perform behavior detonation; identify a malware object based on machine-learning; and select one or more persistent artifacts of the malware on the target system based on one or more algorithms applied to behavior traces of the malware object to select one or more persistent artifacts of the malware on the target system.

08-27-2015

20150244732

Systems And Methods For Malware Detection And Mitigation - Systems and methods for monitoring malware events in a computer networking environment are described. The systems and methods including the steps of identifying a plurality of suspect objects comprising data about network transactions or computer operations suspected of being linked to a security risk; transmitting the suspect objects to an inspection service operating on one or more general purpose digital computers, wherein the inspection service inspects the suspect objects using a plurality of inspection methods to create digital information about the nature of the potential threat posed by the suspect objects; transmitting said digital information to an analytical service operating on one or more general purpose digital computers, wherein the analytical service performs a plurality of analytical algorithms to categorize the suspect objects with one or more scores for each suspect object based on their security threat; transmitting said one or more scores to a correlation facility which aggregates a plurality of scores, optionally with other information about each suspect objects, into the form of aggregate data representing one or more aggregate features of a plurality of suspect objects; and generating an infection verification pack (IVP) comprising routines which, when run on an end-point machine within the computer networking environment, will mitigate a suspected security threat.

08-27-2015

Gerhard Jas, Leuna DE

Patent application number

Description

Published

20090005535

Solution-Phase Synthesis of Leuprolide and Its Intermediates - The invention relates to a process for producing the nonapeptide leuprolide and the intermediate N-protected oligopetides thereof, wherein at least one peptide bond of the compound is formed by reacting an activated carboxylic acid and an amine component in a continuous flow.

Johal Jas, Colorado Springs, CO US

Patent application number

Description

Published

20080232167

Current controlled recall schema - A memory circuit includes a controlled current source coupled to an input to a nonvolatile cell, and a second controlled current source coupled to a volatile cell, the volatile cell coupled to receive current from the controlled current source via the nonvolatile cell.

09-25-2008

Vijaya Jas, Austin, TX US

Patent application number

Description

Published

20110099258

Dynamic Control of Autonomic Management of a Data Center - A method, system, and article for autonomizing autonomic management of a data center, with the data center having at least one computer system and an associated component. Data is collected from the data center and used as input to identify a data center policy. A set of capabilities of elements of the data center are detected and cataloged based upon the collected data. At least one policy is dynamically selected from at least one set of master policies in a policy directory with the selected policy to support the cataloged capabilities of the data center, and to dynamically control selective application and to adapt parameters for quality of service. The selected policy is applied to manage the data center.

04-28-2011

20110196957

Real-Time Policy Visualization by Configuration Item to Demonstrate Real-Time and Historical Interaction of Policies - Multiple policy engines may be integrated with a change and configuration change database to enable coordination of multiple policies by an embodiment comprising: a data center having a plurality of configuration items and connected to a network; a database connected to the network; a plurality of policy engines connected to the network; wherein each of the plurality of policy engines is configured to apply one or more policies to the data center in accordance with an awareness of all configuration item changes made by all other policy engines connected to the network; wherein the awareness comprises a plurality of relationships, each relationship being between a policy data and a configuration item.