Low Power Frequency Synthesis for 60 GHz Applications

The design of 60 GHz transceivers requires a stable local oscillator for up and down conversion of the RF signal being transmitted or received. A voltage controlled oscillator (VCO) is used, locked to a stable frequency reference using a phase locked loop (PLL) as shown in Figure 1. The VCO must have a wide tuning range in order to ensure the correct frequencies can be reached despite PVT variations and should have low phase noise so as not to corrupt the wanted signal through reciprocal mixing. Achieving a wide tuning range is difficult at these frequencies due to the low quality factor of varactors, while decreasing noise tends to increase power consumption. Moreover, the design of the PLL requires high speed dividers to bring down the oscillation frequency to the reference frequency for comparison. The first highest-frequency divider stages are typically power-hungry and require careful design to assure their capture range exceeds the tuning range of the VCO. This research focuses on the design of 60 GHz PLLs both from an architectural and circuit design standpoint with a particular emphasis on low power consumption.