Abstract:

Memory cells having memory elements self-aligned with the emitters of
bipolar junction transistor access devices are described herein, as well
as methods for manufacturing such devices. A memory device as described
herein comprises a plurality of memory cells. Memory cells in the
plurality of memory cells include a bipolar junction transistor
comprising an emitter comprising a pillar of doped polysilicon. The
memory cells include an insulating element over the emitter and having an
opening extending through the insulating layer, the opening centered over
the emitter. The memory cells also include a memory element within the
opening and electrically coupled to the emitter.

Claims:

1. A memory device comprising a plurality of memory cells, memory cells in
the plurality of memory cells comprising:a bipolar junction transistor
comprising an emitter comprising a pillar of doped polysilicon;an
insulating element over the emitter and having an opening extending
through the insulating element, the opening centered over the emitter;
anda memory element within the opening and electrically coupled to the
emitter.

2. The memory device of claim 1, wherein:the pillar of doped polysilicon
of the memory cells have sides that, when projected above over the
emitter, define a cylinder over the emitter; andthe opening is centered
within the cylinder.

3. The memory device of claim 1, wherein the memory elements of the memory
cells have respective bottom surfaces with a surface area less than that
of a top surface of the corresponding emitter.

4. The memory device of claim 1, wherein the emitters of the memory cells
further comprise a conductive cap comprising silicide on the pillar of
doped polysilicon.

5. The device of claim 1, wherein the insulating elements of the memory
cells have an outer surface vertically aligned with an outer surface of
the corresponding emitter.

6. The device of claim 5, wherein memory cells in the plurality of memory
cells further comprise a sidewall spacer surrounding the insulating
element and the emitter.

7. The device of claim 1, further comprising a single-crystalline
semiconductor substrate and a plurality of word lines within the
single-crystalline semiconductor substrate, the emitters of the memory
cells contacting a corresponding word line in the plurality of word
lines, wherein the bipolar junction transistors of the memory cells
further comprise:a portion of the corresponding word line underlying the
emitter acting as a base; anda collector comprising a portion of the
single-crystalline substrate underlying the base.

8. The device of claim 7, wherein the word lines further comprise top
conductors comprising silicide on top surfaces of the regions between the
emitters of adjacent memory cells.

9. The device of claim 7, further comprising sidewall conductors
comprising silicide on sidewall surfaces of the word lines.

12. The device of claim 7, further comprising a plurality of bit lines,
wherein the memory elements of the memory cells are electrically coupled
between the emitter and a corresponding bit line in the plurality of bit
lines.

13. The device of claim 12, further comprising conductive contacts
contacting the single-crystalline substrate and coupled to a reference
voltage.

14. A method for manufacturing a memory device comprising forming a
plurality of memory cells, forming memory cells in the plurality of
memory cells comprising:forming a bipolar junction transistor comprising
an emitter comprising a pillar of doped polysilicon;forming an insulating
element over the emitter and having an opening extending through the
insulating element, the opening centered over the emitter; andforming a
memory element within the opening and electrically coupled to the
emitter.

15. The method of claim 14, wherein:the pillar of doped polysilicon of the
memory cells have sides that, when projected over the emitter, define a
cylinder over the emitter; andthe opening is centered within the
cylinder.

16. The method of claim 14, wherein the emitters of the memory cells
further comprise a conductive cap comprising silicide on the pillar of
doped polysilicon.

17. The method of claim 14, wherein the insulating elements of the memory
cells have an outer surface vertically aligned with an outer surface of
the corresponding emitter.

18. The method of claim 17, wherein forming memory cells in the plurality
of memory cells further comprise forming a sidewall spacer surrounding
the insulating element and the emitter.

19. The method of claim 14, further comprising:forming a
single-crystalline semiconductor substrate;forming a plurality of word
lines within the single-crystalline substrate, the emitters of the memory
cells contacting a corresponding word line in the plurality of word
lines, wherein the bipolar junction transistors of the memory cells
further comprise a portion of the corresponding word line underlying the
emitter acting as a base, and a collector comprising a portion of the
single-crystalline substrate underlying the base; andforming a plurality
of bit lines, wherein the memory elements of the memory cells are
electrically coupled between the emitter and a corresponding bit line in
the plurality of bit lines.

20. The method of claim 19, wherein forming the word lines further
comprise forming top conductors comprising silicide on top surfaces of
the regions between the emitters of adjacent memory cells.

21. The method of claim 14, further comprising forming conductive contacts
contacting the single-crystalline substrate and coupled to a reference
voltage.

22. A method for manufacturing a memory device, the method
comprising:forming a single-crystalline substrate having a first
conductivity type;forming a plurality of dielectric trenches within the
single-crystalline substrate;forming a plurality of word lines within the
single-crystalline substrate, adjacent word lines in the plurality of
word lines separated by a dielectric trench in the plurality of
dielectric trenches;forming a structure overlying the single-crystalline
substrate, the structure comprising doped polysilicon material,
conductive cap material on the doped polysilicon material, and
sacrificial material on the conductive cap material;patterning the
structure to form a plurality of stacks on the word lines;forming
sidewall spacers on sidewalls of the stacks;removing the sacrificial
material to define vias;forming an insulating layer within the vias, the
insulating layer defining openings;forming memory elements within the
openings; andforming a plurality of bit lines on the memory elements.

23. The method of claim 22, further comprising performing an implantation
process to form more highly doped regions within the word lines between
adjacent stacks after the step of forming the sidewalls spacers.

24. The method of claim 22, further comprising forming top conductors
comprising silicide on top surfaces of the more highly doped regions of
the word lines.

25. The method of claim 22, wherein the memory device comprises a memory
region and a periphery region, the word lines within the memory region,
and further comprising:depositing gate dielectric material within the
memory region and the periphery region after the step of forming the
plurality of word lines and before the step of forming the structure
overlying the single-crystalline substrate;removing the gate dielectric
material within the memory region; andforming a logic device within the
periphery region and electrically coupled to bit lines in the plurality
of bit lines and word lines in the plurality of word lines, the logic
device comprising a gate structure overlying the single-crystalline
substrate and first and second doped regions within the
single-crystalline substrate, the gate structure comprising a doped
polysilicon portion comprising the doped polysilicon material on the gate
dielectric material and a conductive cap portion comprising the
conductive cap material on the doped polysilicon portion.

26. The method of claim 25, wherein the forming the logic device
comprises:patterning the doped polysilicon material and the conductive
cap material within the periphery region;performing a lightly doped drain
implantation process to form lightly doped regions within the
single-crystalline substrate;forming a dielectric spacer on a sidewall of
the doped polysilicon portion and conductive cap portion; andforming a
second implantation process to form the first and second doped regions
within the single-crystalline substrate.

27. The method of claim 22, wherein the forming the single-crystalline
substrate and the forming the plurality of word lines comprise:forming
the single-crystalline substrate;forming the plurality of dielectric
trenches within the single-crystalline substrate;removing a portion of
material from the dielectric trenches to expose sidewall surfaces of the
single-crystalline substrate;forming sidewall conductors comprising
silicide on the exposed sidewall surfaces of the single-crystalline
substrate;filling the dielectric trenches with dielectric material;
andimplanting dopants within the single-crystalline substrate between the
dielectric trenches to form the word lines.

[0002]International Business Machines Corporation, a New York corporation,
and Macronix International Corporation, Ltd., a Taiwan corporation, are
parties to a Joint Research Agreement.

BACKGROUND OF THE INVENTION

[0003]1. Field of the Invention

[0004]The present invention relates to high density memory devices based
on phase change based memory materials, including chalcogenide based
materials and on other programmable resistive materials, and methods for
manufacturing such devices.

[0005]2. Description of Related Art

[0006]Phase change based memory materials, like chalcogenide based
materials and similar materials, can be caused to change phase between an
amorphous state and a crystalline state by application of electrical
current at levels suitable for implementation in integrated circuits. The
generally amorphous state is characterized by higher electrical
resistivity than the generally crystalline state, which can be readily
sensed to indicate data. These properties have generated interest in
using programmable resistive material to form nonvolatile memory
circuits, which can be read and written with random access.

[0007]The change from the amorphous to the crystalline state is generally
a lower current operation. The change from crystalline to amorphous,
referred to as reset herein, is generally a higher current operation,
which includes a short high current density pulse to melt or breakdown
the crystalline structure, after which the phase change material cools
quickly, quenching the molten phase change material and allowing at least
a portion of the phase change material to stabilize in the amorphous
state.

[0008]Because the phase change occurs as a result of heating, a relatively
large current is needed in order to heat the phase change material and
induce the desired phase change. Issues have arisen in obtaining the
necessary current for phase change memory cells having field effect
transistor access devices due to the relatively low current drive of
field effect transistors.

[0009]Bipolar junction transistors can provide larger current drive than
field effect transistors, but the integration of bipolar junction
transistors with CMOS peripheral circuitry is difficult and may result in
highly complex designs and manufacturing processes.

[0010]The magnitude of the current can be reduced by reducing the size of
the phase change memory element in the cell, so that higher current
densities are achieved with small absolute current values through the
phase change memory element. However, problems have arisen in
manufacturing devices with very small dimensions and with variations in
manufacturing processes needed to meet the tight tolerance requirements
necessary for large scale high-density memory devices.

[0012]Memory cells having memory elements self-aligned with the emitters
of bipolar junction transistor access devices are described herein. A
memory device as described herein comprises a plurality of memory cells.
Memory cells in the plurality of memory cells include a bipolar junction
transistor comprising an emitter comprising a pillar of doped
polysilicon. An insulating element is over the emitter and has an opening
extending through the insulating element, the opening centered over the
emitter. A memory element is within the opening and is electrically
coupled to the emitter.

[0013]In embodiments the emitter can be formed during the formation of a
sacrificial element used to define the location of the subsequently
formed memory element. The sacrificial element is removed to define a via
overlying the emitter and an insulating element is formed in the via. The
memory element is formed within an opening defined by the insulating
element. The opening defined by the insulating element can be formed by
processes which result in very small variations in the sublithographic
width of the memory element across an array of memory cells.

[0014]A memory cell described herein results in the active region within
the memory element that can be made extremely small, thereby reducing the
magnitude of the current needed to induce a phase change. The width of
the memory element within the opening defined by the insulating element
is less than that of the doped polysilicon pillar and conductive cap
acting as the emitter, and preferably less than a minimum feature size
for a process, for example a lithographic process, used to form the doped
polysilicon pillar, conductive cap, and bit lines. The small width
concentrates current density within the memory element, thereby reducing
the magnitude of the current needed to induce a phase change in the
active region. Additionally, the insulating element may provide some
thermal isolation to the active region, which also helps to reduce the
amount of current necessary to induce a phase change. Furthermore, the
remaining portion of the memory element can provide some thermal
isolation from the bit line for the active region.

[0015]A method for manufacturing a memory device described herein
comprises forming a single-crystalline substrate having a first
conductivity type. A plurality of dielectric trenches and a plurality of
word lines are formed within the single-crystalline substrate. Adjacent
word lines are separated by a dielectric trench in the plurality of
dielectric trenches. A structure is formed overlying the
single-crystalline substrate, the structure comprising doped polysilicon
material, conductive cap material on the doped polysilicon material, and
a sacrificial material on the conductive cap material. The structure is
patterned to form a plurality of stacks on the word lines. Sidewall
spacers are formed on sidewalls of the stacks. The sacrificial material
is removed to define vias, and an insulating layer is formed within the
vias, the insulating layer defining openings. Memory elements are formed
within the openings, and a plurality of bit lines are formed on the
memory elements.

[0016]In embodiments described herein logic devices in the periphery
region and the memory cells having bipolar junction transistors in the
memory region are manufactured concurrently. Gate dielectric material is
formed within the memory and periphery regions. The gate dielectric
material is removed from the memory region, and a layer of doped
polysilicon material and a layer of conductive cap material are formed
within the memory and periphery regions. The gates of the logic devices
and the emitters of the bipolar junction transistor access devices are
both formed using the material of the layers of doped polysilicon
material and the conductive cap material. As a result, memory devices
described herein include phase change memory cells with bipolar junction
transistor access devices compatible with CMOS peripheral circuitry while
also addressing the complexity of design integration and manufacturing
processes.

[0017]Other aspects and advantages of the present invention can be seen on
review of the drawings, the detailed description, and the claims which
follow.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018]FIG. 1 illustrates a schematic diagram of a portion of a memory cell
array implemented using memory cells having bipolar junction transistors
with polysilicon emitters and self-aligned memory elements as described
herein.

[0019]FIGS. 2A and 2B illustrate cross-sectional views of a portion of
memory cells arranged in the array, FIG. 2A taken along the bit lines and
FIG. 2B taken along the word lines.

[0020]FIG. 3A illustrates a cross-sectional view of a second embodiment
similar to the embodiment of FIGS. 2A-2B, with a top conductor comprising
silicide on the top surfaces of the more highly doped regions of the word
lines.

[0021]FIGS. 4-17b illustrate steps in a fabrication sequence for
manufacturing an array of memory cells having bipolar junction
transistors with polysilicon emitters and self-aligned memory elements as
described herein.

[0022]FIGS. 18-21 illustrate an alternative embodiment to that illustrated
in FIGS. 5A-5B for forming word lines.

[0023]FIG. 22 is a simplified block diagram of an integrated circuit
including a memory array implemented using memory cells having bipolar
junction transistors with polysilicon emitters and self-aligned memory
elements as described herein.

DETAILED DESCRIPTION

[0024]The following description of the disclosure will typically be with
reference to specific structural embodiments and methods. It is to be
understood that there is no intention to limit the disclosure to the
specifically disclosed embodiments and methods, but that the disclosure
may be practiced using other features, elements, methods and embodiments.
Preferred embodiments are described to illustrate the present disclosure,
not to limit its scope, which is defined by the claims. Those of ordinary
skill in the art will recognize a variety of equivalent variations on the
description that follows. Like elements in various embodiments are
commonly referred to with like reference numerals.

[0025]FIG. 1 illustrates a schematic diagram of a portion of a memory cell
array 100 implemented using memory cells having bipolar junction
transistors with polysilicon emitters and self-aligned memory elements as
described herein.

[0026]As shown in the schematic diagram of FIG. 1, each of the memory
cells of array 100 includes a bipolar junction transistor access device
and a memory element arranged in electrical series, the memory elements
capable of being set to one of a plurality of resistive states and thus
capable of storing one or more bits of data.

[0027]The array 100 comprises a plurality of word lines 130 including word
lines 130a, 130b, 130c, 130d extending in parallel in a first direction
and in electrical communication with word line decoder/driver 150. The
word lines 130 are coupled to the base terminals of the bipolar access
transistors of the array 100.

[0028]A plurality of bit lines 120 including bit lines 120a, 120b, 120c,
120d extend in parallel in a second direction and are in electrical
communication with bit line decoder 160. The emitter terminals of the
respective bipolar junction transistors are coupled to a corresponding
bit line 120 via the memory elements.

[0029]The memory cells of the array 100 are coupled in a common collector
configuration. In a common collector configuration, the collector
terminals of the memory cells are coupled to a constant reference
voltage, and the input and output are the base and emitter terminals
respectively. Thus, in operation voltages on the bit lines 120 and word
lines 130 induce a current to from the bit lines 120 to the collector
terminals, or vice versa, through the emitter terminals and the memory
elements.

[0030]In FIG. 1 the collector terminals are coupled to ground.
Alternatively the collector terminals may be coupled to a voltage source
for applying a reference voltage other than ground. See, for example,
Biasing Arrangement Supply Voltages, Current Sources 2236 of FIG. 22.

[0031]Memory cell 110 is representative of the memory cells of array 100
and comprises bipolar junction transistor 115 and phase change memory
element 125 arranged in electrical series. The base terminal of the
bipolar junction transistor 115 is coupled to the word line 130b, and the
emitter terminal of the transistor 115 is coupled to the bit line 120b
via the phase change memory element 125.

[0032]Reading or writing to memory cell 110 of array 100 can be achieved
by applying appropriate voltages and/or currents to the corresponding
word line 130b and the corresponding bit line 120b to induce a current
through the selected memory cell 110. The level and duration of the
voltages/currents applied is dependent upon the operation performed, e.g.
a reading operation or a writing operation.

[0033]In a reset (erase) operation of the memory cell 110, a reset pulse
applied to the word line 130b, and the bit line 120b induces a current
through the memory element 125 to cause a transition of an active region
of the memory element 125 into an amorphous phase, thereby setting the
phase change material to a resistance within a resistive value range
associated with the reset state. The reset pulse is a relatively high
energy pulse, sufficient to raise the temperature of at least the active
region of the memory element 125 above the transition (crystallization)
temperature of the phase change material and also above the melting
temperature to place at least the active region in a liquid state. The
reset pulse is then quickly terminated, resulting in a relatively quick
quenching time as the active region quickly cools to below the transition
temperature so that the active region stabilizes to a generally amorphous
phase.

[0034]In a set (or program) operation of memory cell 110, a program pulse
is applied to the word line 130b and the bit line 120b of suitable
amplitude and duration to induce a current through the memory cell 110
sufficient to raise the temperature of at least a portion of the active
region above the transition temperature and cause a transition of at
least a portion of the active region from the amorphous phase into a
crystalline phase, this transition lowering the resistance of the memory
element 125 and setting the memory cell 110 to the desired state.

[0035]In a read (or sense) operation of the data value stored in the
memory cell 110, a read pulse applied to the corresponding word line 130b
and the corresponding bit line 120b of suitable amplitude and duration to
induce current to flow that does not result in the memory element 125
undergoing a change in resistive state. The current through the memory
cell 110 is dependent upon the resistance of the memory element 125 and
thus the data value stored in the memory cell 110. Thus, the data state
of the memory cell may be determined, for example, by comparison of the
current on bit line 120b with a suitable reference current by sense
amplifiers of block 165.

[0036]FIGS. 2A and 2B illustrate cross-sectional views of a portion of
memory cells (including representative memory cell 110) arranged in the
array 100, FIG. 2A taken along the bit lines 120 and FIG. 2B taken along
the word lines 130.

[0037]The array 100 includes a memory region 280 and a periphery region
285 on a single-crystalline semiconductor substrate 200. The periphery
region 285 includes logic device 286 having a gate structure 287 on a
gate dielectric layer 293 and overlying the substrate 200, and doped
regions 288, 289 acting as the source and drain regions. The gate
structure 287 comprises a conductive cap 291 on a doped polysilicon
portion 290, and a dielectric spacer 292 on the sidewall of the
conductive cap 291 and doped polysilicon portion 290. The conductive cap
291 comprises a silicide containing, for example, Ti, W, Co, Ni, or Ta. A
conductive plug 295 is coupled to doped region 288 and extends to the top
surface of dielectric 294 to contact bit line 120b, the dielectric 294
comprising one or more layers of dielectric material. A conductive plug
296 is coupled to doped region 289 and extends to the top surface of
dielectric 294 to contact line 297.

[0038]The memory region 280 includes a well 202 having a first
conductivity type within substrate 200, the well 202 comprising a first
doped region 205 and a second doped region 210 more highly doped than the
first doped region 205. The substrate 200 also includes word lines 130
within the well 202 and extending in a first direction into and out of
the cross-section illustrated in FIG. 2A, the word lines 130 separated by
dielectric trenches (trench isolation structures) 230 comprising
dielectric material within the well. The word lines 130 have a second
conductivity type opposite the first conductivity type.

[0039]The memory cell 110 includes a doped polysilicon pillar 220 having
the first conductivity type, the doped polysilicon pillar 220 contacting
the corresponding word line 130b. The doped polysilicon pillar 220 is
more highly doped than the portion of the word line 130b underlying the
doped polysilicon pillar 220. Thus the pillar 220 and the word line 130b
define a pn junction near the interface 222 that is largely inside the
word line 130b.

[0040]The memory cell 110 includes a conductive cap 240 on the doped
polysilicon pillar 220. In the illustrated embodiment the conductive cap
240 comprises a silicide containing, for example, Ti, W, Co, Ni, or Ta.
The conductive cap 240 provides a low resistance contact between the
doped polysilicon pillar 220 and memory element 125, assists in
maintaining the uniformity of current in the doped polysilicon pillar 220
during operation by providing a contact surface that is more highly
conductive than the polysilicon material of pillar 220, and can be used
as a protective etch stop layer for the doped polysilicon pillar 220
during selective etching of material overlying the pillar 220. In some
embodiments the conductive cap 240 may be omitted.

[0042]As can be seen in FIG. 2B, the word lines 130 include regions
between the doped polysilicon pillars 220 more highly doped than the
regions which underlie the spacers 260 and doped polysilicon pillars 220,
the more highly doped regions helping to improve the electrical
conductivity of the word lines 130 and thus reducing the loading of the
word lines 130 and improving the uniformity of the array. Additionally,
the more lightly doped regions of the word lines 130 underlying the doped
polysilicon pillars 220 improve the breakdown voltage of the pn junction
therebetween.

[0043]The doped polysilicon pillar 220 and conductive cap 240 act as the
emitter of the bipolar junction transistor 115 of the memory cell 110. A
portion of the word line 130b underlying the pillar 220 acts as the base
of the bipolar junction transistor 115 of the memory cell 110. A portion
of the well underlying the word line 130b acts as a collector of the
bipolar junction transistor 115 of the memory cell 110.

[0044]Conductive contacts 215 couple the second doped region 210 of the
well 202 to the conductive material 140 coupled to a reference voltage.

[0047]Memory element 125 is within an opening defined by a insulating
element 245 and electrically couples the conductive cap 240 to the bit
line 120b. As a result, the memory element 125 has a bottom surface with
a surface area less than that of the top surface of the emitter. The
memory element 125 may comprise, for example, one or more materials from
the group of Ge, Sb, Te, Se, In, Ti, Ga, Bi, Sn, Cu, Pd, Pb, Ag, S, Si,
O, P, As, N and Au.

[0048]The insulating element 245 preferably comprises material resistant
to diffusion of the memory material of memory element 160. In some
embodiments the material of insulating element 245 is chosen for low
thermal conductivity for reasons discussed in more detail below.

[0049]The bit lines 120, including bit line 120b acting as a top electrode
for the memory cell 110, extend into and out of the cross-section
illustrated in FIG. 2B. In the illustrated embodiment the bit lines 120
comprise a first conductive layer contacting the memory elements, and a
second conductive layer on the first conductive layer. Alternatively, the
bit lines 120 may comprise a single conductive layer.

[0050]Advantages of having both layers for the bit lines 120 include
choosing the material of the first conductive layer for compatibility
with the material of memory element 125, while material of the second
conductive layer can be chosen for other advantages such as higher
electrical conductivity than the material of the first conductive layer.
In the illustrated embodiment the first conductive layer comprises TiN
and the second conductive layer comprises Al. TiN may be preferred for
the first conductive layer in embodiments in which the memory element 120
comprises GST (discussed below) because it makes good contact with GST,
it is a common material used in semiconductor manufacturing, and it
provides a good diffusion barrier. Alternatively, the first conductive
layer may be TaN, TiAlN or TaAlN.

[0051]As further examples, the first and second conductive layer of the
bit lines 120 may each comprise one or more elements selected from the
group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, N, O, and Ru
and combinations thereof

[0052]In the illustrated embodiment the conductive material 140 and the
line 297 also comprise first and second conductive layers like that of
the bit lines 120. Alternatively, the conductive material 140 and line
297 may each comprise one or more layers of material each comprising, for
example, one or more elements discussed above with reference to the bit
lines 120.

[0053]The insulating element 245 has sides 246 vertically aligned with
sides 221 of the emitter (doped polysilicon pillar 220 and conductive cap
210) to define sidewall 262, and a sidewall spacer 260 comprising
dielectric material is on the sidewall 262 and surrounds the emitter and
the insulating element 245.

[0054]The sides 221 of the emitter, when projected above the emitter,
define a cylinder over the emitter. In the illustrated embodiment of
FIGS. 2A-2B the cylinder defined by the sides 221 of the emitter can be
observed as the sides 246 of the insulating element 245. In the
illustrated embodiment the cylinder defined by the sides 221 of the
emitter has a circular cross-section since the emitter has a circular
cross-section. Alternatively, the cylinder defined by the sides 221 of
the emitter may have a cross-section that is square, elliptical,
rectangular, or somewhat irregularly shaped, depending on the
cross-sectional shape of the emitter.

[0055]In the cross-sectional views illustrated in FIGS. 2A and 2B, the
insulating element 245 has an opening centered within the cylinder
defined by the sides 221 of the emitter, and the memory element 125 is
within the opening and is self-aligned with the emitter (doped
polysilicon pillar 220 and the conductive cap 240). In the manufacturing
embodiment described in more detail below with reference to FIGS. 4 to
17, the doped polysilicon pillar 220 and conductive cap 240 are formed
during the patterning of material which defines the locations of the
subsequently formed insulating element 245 and memory element 125. The
spacer 260 is then formed and the patterned material is selectively
removed to form a via defined by the spacer 260 and overlying the
conductive cap 240. The insulating element 245 is then formed within the
via and has an opening centered on the conductive cap 240, and the memory
element 125 is formed within the opening defined by the insulating
element 245.

[0056]Also described in more detail below with reference to FIGS. 4 to 17,
gate dielectric material is formed within the memory and periphery
regions. The gate dielectric material is removed from the memory region,
and a layer of doped polysilicon material and a layer of conductive cap
material are formed within the memory and periphery regions. The gates of
the logic devices and the emitters of the bipolar junction transistor
access devices are both formed using the material of the layers of doped
polysilicon material and the conductive cap material. As a result, memory
devices described herein include phase change memory cells with bipolar
junction transistor access devices compatible with CMOS peripheral
circuitry while also addressing the complexity of design integration and
manufacturing processes.

[0057]In operation, voltages on the bit line 120b, and word line 130b can
induce a current to flow from the emitter through the memory cell 110 to
the collector.

[0058]The active region 128 is the region of the memory element 125 in
which the memory material is induced to change between at least two solid
phases. As can be appreciated, the active region 128 can be made
extremely small in the illustrated structure, thereby reducing the
magnitude of the current needed to induce a phase change. The width 129
of the memory element 125 within the opening defined by the insulating
element 245 is less than that of the doped polysilicon pillar 220 and
conductive cap 240, and preferably less than a minimum feature size for a
process, for example a lithographic process, used to form the doped
polysilicon pillar 220, conductive cap 240, and bit lines 120. The small
width 129 concentrates current density within the memory element 125,
thereby reducing the magnitude of the current needed to induce a phase
change in the active region 128. Additionally, the insulating element 245
may provide some thermal isolation to the active region 128, which also
helps to reduce the amount of current necessary to induce a phase change.
Furthermore, the remaining portion of the memory element 125 can provide
some thermal isolation from the bit line 120b for the active region 128.

[0059]As described above, bipolar junction transistors can provide larger
current drive than field effect transistors. Additionally, since the
emitters of the transistors comprise doped polysilicon material a
relatively large current gain can be obtained, which reduces the amount
of current needed on the word lines 130 to induce the phase change in the
memory elements. The reduced amount of current on the word lines 130
reduces the cross-talk between devices sharing the same word line, thus
improving the performance of the array. The reduced current on the word
lines 130 will also prevent parasitic BJT behavior in which the emitter
of a neighboring memory cell acts as a collector.

[0060]FIG. 3A illustrates a cross-sectional view of a second embodiment
similar to the embodiment of FIGS. 2A-2B, with a top conductor 300
comprising silicide on the top surfaces of the more highly doped regions
of the word lines 130. The top conductor 300 comprises silicide
containing, for example, Ti, W, Co, Ni, or Ta. The top conductor 300
increases the electrical conductivity of the word lines 130 and thus
reduces the turn on current and the loading of the word lines 130,
resulting in improved uniformity of the array. The top conductor 300
comprising silicide also removes minority carriers from the word lines
130 to prevent parasitic BJT behavior. Also, as shown in FIG. 21, in some
embodiments sidewall conductors 1900 comprising silicide are formed on
the sidewalls of the word lines 130. The silicide sidewall conductors
1900 remove minority carriers from the word lines and improve
conductivity of the word lines 130.

[0061]Embodiments of the memory cells described herein include phase
change based memory materials, including chalcogenide based materials and
other materials, for the memory element. Chalcogens include any of the
four elements oxygen (O), sulfur (S), selenium (Se), and tellurium (Te),
forming part of group VIA of the periodic table. Chalcogenides comprise
compounds of a chalcogen with a more electropositive element or radical.
Chalcogenide alloys comprise combinations of chalcogenides with other
materials such as transition metals. A chalcogenide alloy usually
contains one or more elements from group IVA of the periodic table of
elements, such as germanium (Ge) and tin (Sn). Often, chalcogenide alloys
include combinations including one or more of antimony (Sb), gallium
(Ga), indium (In), and silver (Ag). Many phase change based memory
materials have been described in technical literature, including alloys
of: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te,
Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S.
In the family of Ge/Sb/Te alloys, a wide range of alloy compositions may
be workable. The compositions can be characterized as
TeaGebSb.sub.100-(a-b). One researcher has described the most
useful alloys as having an average concentration of Te in the deposited
materials well below 70%, typically below about 60% and ranged in general
from as low as about 23% up to about 58% Te and most preferably about 48%
to 58% Te. Concentrations of Ge were above about 5% and ranged from a low
of about 8% to about 30% average in the material, remaining generally
below 50%. Most preferably, concentrations of Ge ranged from about 8% to
about 40%. The remainder of the principal constituent elements in this
composition was Sb. These percentages are atomic percentages that total
100% of the atoms of the constituent elements. (Ovshinsky U.S. Pat. No.
5,687,112 patent, cols. 10-11.) Particular alloys evaluated by another
researcher include Ge2Sb2Te5, GeSb2Te4 and GeSb4Te7 (Noboru Yamada,
"Potential of Ge--Sb--Te Phase-Change Optical Disks for High-Data-Rate
Recording", SPIE v.3109, pp. 28-37 (1997).) More generally, a transition
metal such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb),
palladium (Pd), platinum (Pt) and mixtures or alloys thereof may be
combined with Ge/Sb/Te to form a phase change alloy that has programmable
resistive properties. Specific examples of memory materials that may be
useful are given in Ovshinsky '112 at columns 11-13, which examples are
hereby incorporated by reference.

[0063]Phase change alloys are capable of being switched between a first
structural state in which the material is in a generally amorphous solid
phase, and a second structural state in which the material is in a
generally crystalline solid phase in its local order in the active
channel region of the cell. These alloys are at least bistable. The term
amorphous is used to refer to a relatively less ordered structure, more
disordered than a single crystal, which has the detectable
characteristics such as higher electrical resistivity than the
crystalline phase. The term crystalline is used to refer to a relatively
more ordered structure, more ordered than in an amorphous structure,
which has detectable characteristics such as lower electrical resistivity
than the amorphous phase. Typically, phase change materials may be
electrically switched between different detectable states of local order
across the spectrum between completely amorphous and completely
crystalline states. Other material characteristics affected by the change
between amorphous and crystalline phases include atomic order, free
electron density and activation energy. The material may be switched
either into different solid phases or into mixtures of two or more solid
phases, providing a gray scale between completely amorphous and
completely crystalline states. The electrical properties in the material
may vary accordingly.

[0064]Phase change alloys can be changed from one phase state to another
by application of electrical pulses. It has been observed that a shorter,
higher amplitude pulse tends to change the phase change material to a
generally amorphous state. A longer, lower amplitude pulse tends to
change the phase change material to a generally crystalline state. The
energy in a shorter, higher amplitude pulse is high enough to allow for
bonds of the crystalline structure to be broken and short enough to
prevent the atoms from realigning into a crystalline state. Appropriate
profiles for pulses can be determined, without undue experimentation,
specifically adapted to a particular phase change alloy. In following
sections of the disclosure, the phase change material is referred to as
GST, and it will be understood that other types of phase change materials
can be used. A material useful for implementation of a PCRAM described
herein is Ge2Sb2Te5.

[0065]Other programmable resistive memory materials may be used in other
embodiments of the invention, including other materials that use
different crystal phase changes to determine resistance, or other memory
materials that use an electrical pulse to change the resistance state.
Examples include materials for use in resistance random access memory
(RRAM) such as metal-oxides including tungsten-oxide (WOx), NiO,
Nb2O5, CuO2, Ta2O5, Al2O3, CoO,
Fe2O3, HfO2, TiO2, SrTiO3, (BaSr)TiO3.
Additional examples include materials for use in magnetoresistance random
access memory (MRAM) such as spin-torque-transfer (STT) MRAM, for example
at least one of CoFeB, Fe, Co, Ni, Gd, Dy, CoFe, NiFe, MnAs, MnBi, MnSb,
CrO2, MnOFe2O3, FeOFe2O5, NiOFe2O3,
MgOFe2, EuO, and Y3Fe5O12. See, for example, US
Publication No 2007/0176251 entitled "Magnetic Memory Device and Method
of Fabricating the Same", which is incorporated by reference herein.
Additional examples include solid electrolyte materials used for
programmable-metallization-cell (PMC) memory, or nano-ionic memory, such
as silver-doped germanium sulfide electrolytes and copper-doped germanium
sulfide electrolytes. See, for example, N. E. Gilbert et al., "A macro
model of programmable metallization cell devices," Solid-State
Electronics 49 (2005) 1813-1819, which is incorporated by reference
herein.

[0066]An exemplary method for forming chalcogenide material uses
PVD-sputtering or magnetron-sputtering method with source gas(es) of Ar,
N2, and/or He, etc. at the pressure of 1 mTorr˜100 mTorr. The
deposition is usually done at room temperature. A collimator with an
aspect ratio of 1˜5 can be used to improve the fill-in performance.
To improve the fill-in performance, a DC bias of several tens of volts to
several hundreds of volts is also used. On the other hand, the
combination of DC bias and the collimater can be used simultaneously. An
exemplary method for forming chalcogenide material using chemical vapor
deposition (CVD) is disclosed in US Publication No 2006/0172067 entitled
"Chemical Vapor Deposition of Chalcogenide Materials", which is
incorporated by reference herein. Another exemplary method for forming
chalcogenide material using CVD is disclosed in Lee, et al., "Highly
Scalable Phase Change Memory with CVD GeSbTe for Sub 50 nm Generation,
2007 Symposium on VLSI Technology Digest of Technical Papers, pp.
102-103.

[0067]A post-deposition annealing treatment in a vacuum or in an N2
ambient is optionally performed to improve the crystallize state of
chalcogenide material. The annealing temperature typically ranges from
100° C. to 400° C. with an anneal time of less than 30
minutes.

[0068]FIGS. 4-17 illustrate steps in a fabrication sequence for
manufacturing an array of memory cells having bipolar junction
transistors with polysilicon emitters and self-aligned memory elements as
described herein.

[0069]FIG. 4 illustrates a first step of forming a substrate including a
well 202 within the memory region 280 comprising first and second doped
regions 205, 210 and dielectric trenches 230 within the well 202 and
extending into and out of the cross-section illustrated in FIG. 4. The
first and second doped regions 205, 210 can be formed by implantation and
activation annealing processes as known in the art. In the illustrated
embodiment the first doped region 205 comprises doped N-type material of
substrate 200, and the second doped region 210 comprises highly doped
N-type (N+) material of substrate 200. In an alternative embodiment the
first doped region 205 comprises doped P-type material of substrate 200,
and the second doped region 210 comprises highly doped P-type (P+)
material of substrate 200.

[0070]Next, word lines 130 are formed by implantation within the first
doped region 205 of the well, resulting in the structure illustrated in
the cross-sectional views of FIGS. 5A and 5B. Also, in the illustrated
embodiment a second ion implantation step is performed within the well to
form a highly doped region extending from the top surface of the
substrate 200 to the second doped region 210. The word lines 130 have the
second conductivity type, and in the illustrated embodiment the word
lines 130 comprise doped P-type material of substrate 200. In an
alternative embodiment the word lines 130 comprise doped N-type material
of substrate 200.

[0071]Next, gate dielectric layer 293 is formed on the structure
illustrated in FIGS. 5A-5B within the memory region 280 and the periphery
region 285, resulting in the structure illustrated in FIG. 6. In the
illustrated embodiment the gate dielectric layer 293 comprises silicon
dioxide.

[0072]Next, the dielectric layer 293 is removed from the memory region 280
of the structure illustrated in FIGS. 6A-6B, a layer 700 of doped
polysilicon material having the first conductivity type is formed, and a
layer 710 conductive cap material is formed on the doped polysilicon
layer 700, resulting in the structure illustrated in the cross-sectional
views of FIGS. 7A and 7B. The conductive cap material of layer 710
comprises a silicide containing, for example, Ti, W, Co, Ni, or Ta. In
one embodiment the layer 710 comprises cobalt silicide (CoSi) and is
formed by depositing a layer of cobalt and performing a rapid thermal
process (RTP) such that the cobalt reacts with the silicon of the layer
700 to form the layer 710. It is understood that other silicides may also
be formed in this manner by deposition of titanium, arsenic, doped
nickel, or alloys thereof, in a manner similar to the example described
herein using cobalt.

[0073]Next, the logic device 286 is formed within the periphery region 285
of the structure illustrated in FIGS. 7A-7B, resulting in the structure
illustrated in FIGS. 8A and 8B. In the illustrated embodiment the logic
device 286 is formed by patterning the layers 700 and 710 within the
periphery region 285 to form the doped polysilicon portion 290 and
conductive cap 291 of the gate structure 287, performing a lightly doped
drain (LDD) implantation process to form lightly doped regions within the
substrate 200 adjacent the gate structure 287, forming the insulating
layer 292 on the sidewall of the conductive cap 291 and doped polysilicon
portion 290, and performing a second implantation process to form doped
regions 288, 289 acting as the source and drain of the logic device 286.
Alternatively, other techniques may be used to form the logic device 286.

[0074]Next, a layer 900 of dielectric material is formed on the structure
illustrated in FIGS. 8A-8B, resulting in the structure illustrated in
FIGS. 9A and 9B. In the illustrated embodiment the layer 900 comprises
silicon nitride.

[0075]Next, layers 900, 700, and 710 within the memory region 280 of FIGS.
9A-9B are patterned to form a plurality of multi-layer stacks 1000 on the
word lines 130, resulting in the structure illustrated in FIGS. 10A and
10B. The multi-layer stacks 1000 can be formed, for example, by forming a
mask (for example a layer of patterned photoresist) on layer 900
overlying the locations of the multi-layer stacks 1000, and then etching
through layers 900, 700, and 710 using the mask as an etch mask.

[0076]As can be seen in FIGS. 10A and 10B, each of the multi-layer stacks
1000 includes a doped polysilicon pillar 220 comprising material from
layer 700 (See FIGS. 9A-9B) on the corresponding word line 130 to define
a pn junction near the interface 222 therebetween, a conductive cap 240
comprising material from layer 710 (See FIGS. 9A-9B) on the pillar 220,
and a sacrificial element 1010 comprising material from layer 900 on the
conductive cap 240.

[0077]In the illustrated embodiment the multi-layer stacks 1000 have a
circular cross-section. Alternatively, in embodiments the multi-layer
stacks 1000 may have a cross-section that is square, elliptical,
rectangular, or somewhat irregularly shaped, depending on the
manufacturing technique used to form the multi-layer stacks 1000.

[0078]Next, sidewall spacers 260 comprising dielectric material are formed
on the sidewalls of the multi-layer stacks 1000, an implantation process
is performed to form more highly doped regions of the portions of the
word lines 130 between adjacent spacers 260, and top conductors 300
comprising self-aligned silicide (salicide) are formed on the more highly
doped regions of the word lines 130, resulting in the structure
illustrated in FIGS. 11A and 11B. In some embodiments the top conductors
300 may be omitted.

[0079]The sidewall spacers 260 can be formed by depositing a conformal
layer of sidewall spacer material on the structure illustrated in FIGS.
10A-10B, and anisotropically etching the conformal layer to form the
sidewall spacers 260. The sidewall spacers protect the stacks 1000 and
the interface between the stacks 1000 and the word lines 130 during the
silicide process that forms the top conductors.

[0080]In one embodiment the top conductors 300 comprise cobalt silicide
(CoSi) and are formed by depositing a layer of cobalt and performing a
rapid thermal process (RTP) such that the cobalt reacts with the silicon
of the word lines 130 to form the top conductors. It is understood that
other silicides may also be formed in this manner by deposition of
titanium, arsenic, doped nickel, or alloys thereof, in a manner similar
to the example described herein using cobalt.

[0081]Next, dielectric layer 270 is formed on the structure illustrated in
FIGS. 11A-11B and a planarization process such as CMP is performed to
expose top surfaces of the sacrificial elements 1010 of the multi-layer
stacks 1000, resulting in the structure illustrated in FIGS. 12A and 12B.

[0082]Next, an array of conductive contacts 215 are formed through the
dielectric 260 to contact the second doped region 210 of the well and
conductive pillars 295, 296 are formed to contact doped regions 288 and
289 respectively, resulting in the structure illustrated in FIGS. 13A and
13B.

[0083]Next, the sacrificial elements 1010 of FIGS. 13A-13B are removed to
form vias 1400 defined by the spacers 260 and extending down to the
conductive caps 240, resulting in the structure illustrated in FIGS. 14A
and 14B.

[0084]Next, insulating elements 245 are formed within the vias 1400 of
FIGS. 14A-14B, resulting in the structure illustrated in FIGS. 15A-15B.
The insulating elements 245 define self-centered openings 1510 within the
vias 1400, and in the illustrated embodiment the insulating elements 245
comprise silicon nitride.

[0085]The insulating elements 245 may be formed by forming an insulating
dielectric material layer on the structure illustrated in FIGS. 14A-14B,
and anisotropically etching the dielectric material layer to expose a
portion of the conductive caps 240.

[0086]The insulating elements 245 may alternatively be formed by forming a
material layer on the top surface of the dielectric 270 and having
openings overlying the vias 1400. A selective undercutting etch is then
performed on the vias 1400 such that the spacers 260 are etched while
leaving the material layer on the top surface of the dielectric 270
intact. Insulating layer material is in then formed in the via 1400,
which due to the selective undercutting etch process results in a
self-aligned void in the insulating layer material being formed within
the via 1400. Next, an anisotropic etching process is performed on the
insulating layer material to open the void, and etching continues until a
portion of the top surface of the conductive cap 240 is exposed in the
region below the void, thereby forming the insulating element 245
comprising insulating layer material within the void 1400.

[0087]Next, the memory elements 125 are formed within the openings 1510
defined by the insulating elements 245 of the structure illustrated in
FIGS. 15A-15B, resulting in the structure illustrated in FIGS. 16A-16B.
The memory elements 125 may be formed by deposition of memory material on
the structure illustrated in FIGS. 15A-15B, followed by a planarization
process such as CMP.

[0088]Next, the bit lines 120, conductive material 140 coupled to a
reference voltage, and line 297 are formed on the structure illustrated
in FIGS. 16A-16B, resulting in the structure illustrated in FIGS.
17A-17B. In the illustrated embodiment the bits lines 120, conductive
material 140, and line 297 comprise first and second conductive layers
and are formed by depositing the first and second conductive layers and
patterning the layers.

[0089]As described above, the doped polysilicon pillars 220 and conductive
caps 240 are formed during the formation of sacrificial elements 1010
which define the locations of the subsequently formed insulating elements
245 and memory elements 125. The spacers 260 are then formed and the
sacrificial elements 1010 are selectively removed to form vias 1400
defined by the spacers 260 and overlying the conductive caps 240. The
insulating elements 245 are then formed within the vias 1400 and have
openings centered within the cylinder defined by the sides of the
emitter, and the memory element 125 is formed within an opening 1510
defined by the insulating element 245. Thus, the memory elements are
centered on and self-aligned to the doped polysilicon pillars 220 and the
conductive caps 240, the doped polysilicon pillars 220 and conductive
caps 240 acting as the emitters of the bipolar junction transistors of
the memory cells.

[0090]Since the logic devices in the periphery region and the memory cells
having bipolar junction transistors in the memory region are manufactured
concurrently in the manufacturing steps described, the memory device has
a reduced complexity and addresses the compatibility of design
integration issues discussed above, thereby reducing the cost. As
described above, bipolar junction transistors can provide larger current
drive than field effect transistors. Additionally, since the emitters of
the transistors comprise doped polysilicon material a relatively large
current gain can be obtained, which reduces the amount of current needed
on the word lines 130 to induce the phase change in the memory elements.
The reduced amount of current on the word lines 130 reduces the
cross-talk between devices sharing the same word line, thus improving the
performance of the array.

[0092]As illustrated in the cross-sectional view of FIG. 18, etching is
performed to remove a portion of the dielectric material of the
dielectric trenches 230 of FIG. 4, thereby exposing sidewall surfaces
1800 of first doped region 205 of the well between the dielectric
trenches 230.

[0093]Next, sidewall conductors 1900 are formed on the exposed sidewall
surfaces 1800 of the first doped region 205 of the well of FIG. 18,
resulting in the structure illustrated in the cross-sectional view of
FIG. 19. The sidewall conductors 1900 comprise a silicide containing, for
example, Ti, W, Co, Ni, or Ta. The sidewall conductors 1900 can be formed
by depositing a silicide precursor on the exposed sidewall surfaces 1800
and annealing to cause silicide formation. Then the remaining silicide
precursor on the substrate is removed, leaving the self-aligned silicide
sidewall conductors on the sides of sidewall surfaces 1800. Typical
silicide precursors include metals or combinations of metals such as
cobalt, titanium, nickel, molybdenum, tungsten, tantalum, and platinum.
Also, silicide precursors may include metal nitrides or other metal
compounds. The resulting silicide sidewall conductors 1900 removes
minority carriers from the word lines and improves conductivity of the
word lines 130.

[0094]Next, dielectric material is formed on the structure illustrated in
FIG. 19 to fill the dielectric trenches 230, resulting in the structure
shown in the cross-sectional view of FIG. 20.

[0095]Next, ion implantation is performed to implant dopants to form word
lines 130, the word lines 130 having a conductivity type opposite that of
the first and second doped regions 205 and 210 of the well and resulting
in the structure illustrated in the cross-sectional view of FIG. 21.

[0096]FIG. 22 is a simplified block diagram of an integrated circuit 2210
including a memory array 100 implemented using memory cells having
bipolar junction transistors with polysilicon emitters and self-aligned
memory elements as described herein. A word line decoder 2214 having
read, set and reset modes is coupled to and in electrical communication
with a plurality of word lines 2216 arranged along rows in the memory
array 100. A bit line (column) decoder 2218 is in electrical
communication with a plurality of bit lines 2220 arranged along columns
in the array 100 for reading, setting, and resetting the phase change
memory cells (not shown) in array 100. Addresses are supplied on bus 2222
to word line decoder and drivers 2214 and bit line decoder 2218. Sense
amplifiers and data-in structures in block 2224, including voltage and/or
current sources for the read, set, and reset modes are coupled to bit
line decoder 2218 via data bus 2226. Data is supplied via a data-in line
2228 from input/output ports on integrated circuit 2210, or from other
data sources internal or external to integrated circuit 2210, to data-in
structures in block 2224. Other circuitry 2230 may be included on
integrated circuit 2210, such as a general purpose processor or special
purpose application circuitry, or a combination of modules providing
system-on-a-chip functionality supported by array 100. Data is supplied
via a data-out line 2232 from the sense amplifiers in block 2224 to
input/output ports on integrated circuit 2210, or to other data
destinations internal or external to integrated circuit 2210.

[0097]A controller 2234 implemented in this example, using a bias
arrangement state machine, controls the application of bias arrangement
supply voltages and current sources 2236, such as read, program, erase,
erase verify and program verify voltages and/or currents. Controller 2234
may be implemented using special-purpose logic circuitry as known in the
art. In alternative embodiments, controller 2234 comprises a
general-purpose processor, which may be implemented on the same
integrated circuit to execute a computer program to control the
operations of the device. In yet other embodiments, a combination of
special-purpose logic circuitry and a general-purpose processor may be
utilized for implementation of controller 2234.

[0098]While the present invention is disclosed by reference to the
preferred embodiments and examples detailed above, it is to be understood
that these examples are intended in an illustrative rather than in a
limiting sense. It is contemplated that modifications and combinations
will readily occur to those skilled in the art, which modifications and
combinations will be within the spirit of the invention and the scope of
the following claims. What is claimed is: