Market and Technology Drivers to Bring 3D-IC to Production

TAIPEI, Taiwan — August 7, 2013 — With semiconductor technology moving
towards systematic integration of stacked heterogeneous chips and 3D-IC becoming
a mainstream trend, the latest developments will be featured at 3D-IC & Substrate
Pavilion and Advanced Packaging Technology Symposium at SEMICON Taiwan 2013 (September 4-6) and the SiP Global
Summit 2013 (September 4-6)
at TWTC Nangang Exhibition Hall in Taipei, Taiwan. Design tools, manufacturing,
packaging and testing solutions for 2.5D-IC process are available this year, and
the most important issue is how to improve its throughput to enable 2.5D-IC mass
production in 2014.

Taiwan is situated
in the strategic location of the world's IC packaging and testing industry, with
the world's largest packaging and testing company, ASE, as well as SPIL, PTI,
and ChipMOS — the top ten in the world — reaching a global packaging and
testing foundry market share of over 50 percent. Amkor and STATS ChipPAC have also set up
plants in Taiwan. According to an ITIS second quarter forecast this year, the Taiwan
IC packaging and testing industry will significantly grow by 15.5 percent, and the
driving force is from growing demands from
the networking, graphics, wireless, computing device, and mobile handsets
markets.

Serving the growing demands of the
networking, graphics, wireless, and computing device markets with 3D Integrated
Circuits (3D- IC) is a challenging task for the semiconductor industry.
Increasingly, there is a stronger focus on heterogeneous integration through
System-in-a-Package (SiP) technology. According to Yole Développement, the
market value of all the devices using TSV packaged in 3D in the 3D-IC or
3D-WLCSP platforms (CMOS image sensors, Ambient Light Sensors, Power
Amplifiers, RF and inertial MEMS) was worth $2.7 billion in 2011. By 2017, the
market value will hit almost $40 billion, representing 9 percent of the total
semiconductor value.

TechNavio analysts
forecast the global 3D-IC market to grow at a CAGR of 19.7 percent over the
period 2012-2016. One of the key factors contributing to this market growth is
the huge demand for memory-enhanced applications. To meet the exhilarating
market demand, Taiwan’s leading outsourced semiconductor assembly and test
companies — ASE and SPIL — will expand their capex for increase bumping, flip
chip and copper wire bonding capacity. ASE has set aside a capex budget of US$ 0.7
billion and SPIL of US$ 498.9 million for 2013.

"While 2.5D with TSV have been widely
adopted in CMOS sensors and MEMS, affordable stacked memory is not yet
available. In addition, many companies are also looking at alternatives
to silicon interposers, such as glass interposers, to bring the price
down. So, even 2.5D has been delayed and questions remain about its
configuration at high volume." said Terry Tsao, president of SEMI Taiwan. "For
heterogeneous integration of memory and logic, the industry still needs design
tools, thermal solutions, continued work on wafer bonding and de-bonding, and
accepted test methodologies, to name a few requirements. The SIP Global
Summit will explore these barriers and opportunities to accelerate 3D IC's
beyond today's applications.”

Given the growing
importance of packaging and testing in the global semiconductor supply chain,
SEMI will hold the SiP Global Summit 2013 from September 5-6 under the auspices
of SEMI’s Taiwan Packaging and Testing Committee as well as major international
enterprises and research organizations.

This two-day SiP
Global Summit 2013 (www.SiPGlobalSummit.org)
will consist of two major forums: 3D-IC
Technology and Embedded Technology with representatives from 20 of the world’s best
IT firms slated to share insights into 3D-IC, TSV, silicon interposer and
embedded substrate technologies.
Participants in the summit will include TSMC, ASE, SPIL, Unimicron,
Amkor, Qualcomm, STATS ChipPAC, research institutes and market research
organizations including Fraunhofer IZM and Industrial Technology Research
Institute (ITRI).

3D-IC Technology Forum: The Power of Synergy. While the whole supply chain is
preparing for 3D-IC readiness with a developing infrastructure and facilities
to support its go-to-market ecosystem, the industry is looking forward to
achieving a faster volume adoption and wider market penetration. This forum
will provide further guidance on the path between 2.5D-IC and 3D-IC from both
market and technology drivers. The core issues of yield, standardization and
cost will also be addressed to ensure maturity for high-volume 2.5D/3D-IC
production with TSV.

Embedded Technology Forum：Bridging The Last Mile: Chip-to-Substrate
Interconnections. Will "embedded die" be a cost-effective 3D solution? For
potential mobile applications, embedded die has been considered another
3D-compatible technology and key element for miniaturization and ultra-thin 3D
packaging. To explore the path forward to cost-effective 3D approach, the Forum
gathers key contributors to share their latest achievements with technology
progress in process and materials and re-visit the production readiness and
cost structure.

About SEMI
SEMI is the global industry association
serving the micro- and nanoelectronics manufacturing supply chains. Our 1,900
member companies are the engine of the future, enabling smarter, faster and
more economical products that improve our lives. Since 1970, SEMI has been
committed to helping members grow more profitably, create new markets and meet
common industry challenges. SEMI maintains offices in Bangalore, Beijing,
Berlin, Brussels, Grenoble, Hsinchu, Moscow, San Jose, Seoul, Shanghai,
Singapore, Tokyo, and Washington, D.C. For more information, visit www.semi.org.