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Method for Making Lateral PNP Devices

Publishing Venue

IBM

Related People

Antipov, I: AUTHOR

Abstract

In polycrystalline silicon base contact vertical NPN transistors, the spacing between emitters and polycrystalline silicon base contacts is defined by the silicon dioxide wall. By adding a few extra process steps, this type of silicon dioxide wall can also be used to define the space between the collector and emitter of a lateral PNP, thus allowing the making of narrow base width lateral PNPs. In addition, it will also reduce the emitter size of the lateral PNP below the minimum allowable image, thus reducing the area of the stray diode.

Country

United States

Language

English (United States)

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Method for Making Lateral PNP Devices

In polycrystalline silicon base contact vertical NPN transistors, the spacing
between emitters and polycrystalline silicon base contacts is defined by the
silicon dioxide wall. By adding a few extra process steps, this type of silicon
dioxide wall can also be used to define the space between the collector and
emitter of a lateral PNP, thus allowing the making of narrow base width lateral
PNPs. In addition, it will also reduce the emitter size of the lateral PNP below the
minimum allowable image, thus reducing the area of the stray diode.

Since the NPN and lateral PNP (LPNP) devices are processed
simultaneously, the initial process steps are common to both. The subcollector
10 of the NPN transistor and the sub base 11 of the LPNP transistor are formed
simultaneously In the substrate 8 using a suitable N dopant, such as arsenic.
Prior processing had provided epitaxially deposited N layer 12, dielectric isolation
regions 13 between the NPN and LPNP transistors, and dielectric isolation
regions 14 between certain regions within these transistors. Under regions 13 are
P+ regions 15 to further junctionally isolate these transistors. The polycrystalline
silicon external base for the NPN device and the polycrystalline silicon collector
for the LPNP device are also formed simultaneously by depositing a
polycrystalline silicon layer 16 over the device surface having exposed silicon
surfaces in certain regions of these devices. A silicon nitr...