Abstract

The present invention provides an on-die termination circuit capable of supplying an accurate termination resistor without being affected by PVT fluctuations. The present invention provides a feedback signal of a level of a plurality of bits of a code signal with respect to an input-resistance. Feedback means for; Code signal generating means for generating the plurality of bits of the code signal such that the feedback signal has a level corresponding to a reference voltage; And drive control means for repeatedly driving the code signal generation means while continuously activating the feedback means in response to an initialization signal.

Description

FIG. 2 is an internal circuit diagram of the feedback unit of FIG. 1. FIG.

3 is an operational waveform diagram of an on die termination circuit according to the prior art;

4 illustrates a malfunction of the on-die termination circuit according to the prior art during PVT fluctuations.

FIG. 5 is a block diagram illustrating an on-die termination circuit according to a first embodiment of the present invention. FIG.

6 is an internal circuit diagram of a feedback unit of FIG. 5;

7 is an operation waveform diagram of an on die termination circuit according to a second embodiment of the present invention;

* Explanation of symbols for the main parts of the drawings

100: control unit

120: pulse signal generation unit

140: end point notification unit

160: first driving signal generator

180: second driving signal generator

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly to an on die termination circuit capable of supplying accurate termination resistors with little influence from PVT variations.

In general, various semiconductor devices implemented as integrated circuit chips such as CPUs, memories, and gate arrays are used in various electrical products, such as personal computers, servers, or workstations. In most cases, the semiconductor device has a receiving circuit for receiving various signals transmitted from the outside world through an input pad and an output circuit for providing an internal signal to the outside through an output pad.

On the other hand, as the speed of operation of electrical products is increased, the swing width of signals interfaced between the semiconductor devices is gradually decreasing. The reason is to minimize the delay time for signal transmission. However, as the swing width of the signal decreases, the influence on external noise increases, and the reflection of the signal due to impedance mismatching (hereinafter referred to as mismatching) at the interface stage becomes more serious. The impedance mismatch occurs due to external noise, fluctuations in power supply voltage, change in operating temperature, change in manufacturing process, or the like. When impedance mismatching occurs, high-speed data transfer is difficult and output data output from the data output terminal of the semiconductor device may be distorted. Therefore, when the semiconductor device on the receiving side receives the distorted output signal to the input terminal, problems such as setup / hold fail or misjudgement of the input level may frequently occur.

Accordingly, the semiconductor device on the receiving side, which requires a high speed of operation, employs an impedance matching circuit called on-chip termination or on-die termination near a pad in the integrated circuit chip. Typically, in an on-die termination scheme, source termination is performed by an output circuit on the transmission side, and parallel termination is performed by a termination circuit connected in parallel to a receiver circuit connected to the input pad on the receiver side.

1 is a conceptual diagram of a general on die termination circuit.

Referring to FIG. 1, the on-die termination circuit receives a driving signal EN to feed back the level of the code signal P_CD <0: 4> with respect to the input-resistance ZQ as a feedback signal P_FD. Compared to the unit 20 and the comparator 30 for detecting and outputting a level difference between the feedback signal P_FD with respect to the reference voltage VREF in response to the drive signal EN and the comparison drive signal LTCH_EN. A counting unit 40 for up-counting or down-counting the code signal P_CD <0: 4> in response to the output signal of the unit 30, and the driving signal EN in response to the initialization signal RST. ) And a control unit 10 for repeatedly activating the comparison driving signal LTCH_EN.

The control unit 10 counts the pulse signal generator 12 for generating the pulse signal CALP at regular intervals in response to the initialization signal RST, and counts the number of activations of the pulse signal 12 to terminate the signal CAL_STP. The end point notification unit 14 and the driving signal EN and the comparison driving signal LTCH_EN are repeatedly activated in response to the pulse signal CALP and the driving signal EN in response to the ending signal CAL_STP. ) And a driving signal generator 16 to deactivate the comparison driving signal LTCH_EN.

For reference, the input-resistance ZQ is a signal applied through an input pin from the outside, and 240 kV is connected between the input pin and the ground voltage.

In addition, the code signal P_CD <0: 4> has a level value in the form of a binary code.

In addition, although not shown in the drawing, the on-die termination circuit further includes a termination resistor providing unit for supplying a termination-resistance having a resistance value corresponding to the code signal P_CD <0: 4> to the data pad.

FIG. 2 is an internal circuit diagram of the feedback unit 20 of FIG. 1.

Referring to FIG. 2, the feedback unit 20 outputs a code signal P_CD <0: 4> as a selection signal CD <0: 4> in response to the driving signal EN. And a feedback signal providing unit 24 for outputting the voltage level of the selection signal CD <0: 4> for the input-resistance ZQ as the feedback signal P_FD.

The signal input unit 22 receives a plurality of NAND gates for outputting the selection signal CD <0: 4> by taking the driving signal EN and one of the plurality of code signals P_CD <0: 4> as inputs. Include.

The feedback signal providing unit 24 includes a plurality of PMOS transistors having one of a plurality of code signals CD <0: 4> as gate inputs and a source terminal connected to a voltage VDDQ, a drain terminal and an output node of each PMOS transistor. The voltage across the output node is output as a feedback signal P_FD, including a plurality of resistors connected between the input node and the input-resistance ZQ connected to the output node.

Referring to the operation briefly, the signal input unit 22 inverts the code signal P_CD <0: 4> when the driving signal EN is activated to the logic level 'H', so that the selection signal CD <0: 4 >)

Next, the feedback signal providing unit 24 has a resistor connected to one end of the PMOS transistor turned on by the activation of the corresponding signal among the selection signals CD <0: 4> in parallel to the output node, thereby providing the feedback signal P_FD. ) In other words, the feedback signal P_FD is determined by the pull-up resistor formed by connecting the drain terminal of the active PMOS transistor in parallel to the output node and the resistance ratio of the input-resistance ZQ connected to the output node. The voltage level is determined.

Meanwhile, the driving of the on die termination circuit shown in FIGS. 1 and 2 will be described with reference to the drawings.

3 is an operational waveform diagram of an on die termination circuit according to the related art.

Referring to FIG. 3, when the semiconductor memory device is initially driven, the power-up signal PWRUP is activated in the form of a pulse as the level of the external voltage is stabilized. At this time, the initialization signal RST is also activated.

Subsequently, the pulse signal generator 12 generates the pulse signal CALP at regular intervals in response to the initialization signal RST, and the driving signal generator 16 responds to each time the pulse signal CALP is activated. The driving signal EN and the comparison driving signal LTCH_EN are activated. Here, the comparison driving signal LTCH_EN is activated twice while the driving signal EN is activated once.

Subsequently, the feedback unit 20 outputs the level of the code signal P_CD <0: 4> for the input-resistance ZQ as the feedback signal P_FD in response to the driving signal EN.

Subsequently, the comparator 30 detects and outputs a level difference between the feedback signal P_FD with respect to the reference voltage VREF in response to the activation of the driving signal EN and the comparison driving signal LTCH_EN.

Next, the counting unit 40 down-counts or up-counts the current code signal P_CD <0: 4> according to the logic level of the output signal of the comparator 30 to perform a new code signal P_CD. <0: 4>).

On the other hand, when the feedback unit 20 is activated once, the comparator 30 and the counting unit 40 are driven twice. As described above, the comparison driving signal LTCH_UP is 2 during the activation of the driving signal EN. Because it is activated once.

Subsequently, the driving as described above is repeated for 10 times, after which the driving signal generator 16 no longer generates the driving signal EN and the comparison driving signal LTCH_EN by the end point notification unit 14. Do not.

That is, the end point notification unit 14 activates the end signal CAL_STP when the number of activations of the pulse signal CALP reaches 10 or more times. Subsequently, the driving signal generator 16 deactivates the driving signal EN and the comparison driving signal LTCH_EN in response to the activation of the termination signal CAL_STP.

As described above, the on-die termination circuit is repeatedly driven to adjust the feedback signal P_FD to have a level corresponding to the reference voltage VREF, so that the termination resistor supplied by the code signal P_CD <0: 4> is input-. It has the same resistance value as the resistor ZQ.

For reference, the reference voltage VREF has 1 / 2VDDQ. Therefore, the code signals P_CD <0: 4> are adjusted so that the feedback signal P_FD has the same 1 / 2VDDQ as the reference voltage VREF.

On the other hand, the on-die termination circuit according to the prior art does not provide a termination resistor corresponding to the input-resistance (ZQ) when the PVT fluctuates, thereby causing a problem that the semiconductor memory device including the on-die termination circuit malfunctions. This will be described in detail with reference to the drawings.

FIG. 4 is a diagram illustrating a malfunction of the on-die termination circuit according to the prior art during PVT fluctuations. In particular, FIG. 4 illustrates a level change of the feedback signal P_FD during one driving signal EN activation.

Referring to FIG. 4, since the feedback unit 20 is activated by activating the driving signal EN, feedback is performed by the pull-up resistor and the input-resistance ZQ corresponding to the code signal P_CD <0: 4>. The level of the signal P_FD develops.

However, when the first comparison driving signal LTCH_EN is activated, 'a' indicates that the feedback signal P_FD does not completely transition to a level corresponding to the pull-up resistor and the input-resistance ZQ. Therefore, when the first comparison driving signal LTCH_EN is activated, the comparing unit 30 and the counting unit 40 are driven by receiving a feedback signal P_FD having an incorrect level.

Specifically, since the level of the feedback signal P_FD does not completely transition at the time of activation of the first comparison driving signal LTCH_EN, the comparator 30 compares the level of the feedback signal P_FD with respect to the reference voltage VREF. The output signal is output at the logic level 'L' by determining that it is low, and the counting unit 40 up-counts the code signals P_CD <0: 4> in response to the output signal of the comparing unit 30. Subsequently, at the time of activation of the second comparison driving signal LTCH_EN, the level transition of the feedback signal P_FD according to the pull-up resistor and the input resistance is terminated, and the code signal P_CD <0: 4> is increased by the first driving. Counted, the level of the feedback signal P_FD becomes higher than the reference voltage VREF. Therefore, since the level of the feedback signal P_FD is higher than the reference voltage VREF, the comparison unit 30 outputs the output signal at the logic level 'H', and the counting unit 40 outputs the code signal P_CD <0: 4. Down-counting>). Therefore, the comparison unit 30 and the counting unit 40 up-count the code signal P_CD <0: 4> once and down-count once during the activation of the driving signal EN.

Therefore, the on-die termination circuit according to the prior art repeatedly performs the above-described driving ten times, and repeatedly performs up-counting and down-counting for each driving. Therefore, the code signals P_CD <0: 4> are not substantially changed.

For reference, the transition time of the feedback signal as described above depends on the capacitance of the pad to which the input-resist is applied and the resistance value of the pull-up resistor in the feedback unit. For example, the transition time is long when the capacitance is large and the pull-up resistance is large. In addition, the transition time is lengthened by the PVT variation.

On the other hand, the on-die termination circuit according to the prior art does not perform a normal operation due to the PVT fluctuation, it is unable to supply a termination resistor corresponding to the input-resistance. Termination resistors are used to allow the semiconductor memory device to receive inputs such as commands, addresses, and data normally. Incorrect termination resistors cause malfunctions because the semiconductor memory device does not receive external inputs normally.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide an on die termination circuit capable of supplying an accurate termination resistor without being affected by PVT fluctuations.

According to an aspect of the present invention, there is provided an on-die termination circuit comprising: feedback means for outputting a level having a plurality of bits of a code signal with respect to an input resistance as a feedback signal; Code signal generating means for generating the plurality of bits of the code signal such that the feedback signal has a level corresponding to a reference voltage; And drive control means for repeatedly driving the code signal generation means while continuously activating the feedback means in response to an initialization signal.

According to another aspect of the present invention, there is provided an on-die termination circuit comprising: feedback means for outputting, as a feedback signal, a level of a plurality of bits of a code signal to an input-resist in response to first and second drive signals; Code signal generating means for generating the plurality of bits of code signals such that the feedback signal has a level corresponding to a reference voltage in response to the first driving signal and the comparison driving signal; And continuously activate the second driving signal during the first period in response to an initialization signal, repeatedly activate the second driving signal during the second period, and drive the first driving during the first and second periods. And control means for repeatedly activating the signal and the comparison driving signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

FIG. 5 is a block diagram illustrating an on-die termination circuit according to a first embodiment of the present invention.

Referring to FIG. 5, the on-die termination circuit according to the present invention has the code signal P_CD <0: 4> with respect to the input-resistance ZQ in response to the first and second driving signals EN and AUTO_EN. The feedback unit 200 for outputting the level as the feedback signal P_FD, and the level at which the feedback signal P_FD corresponds to the reference voltage VREF in response to the first driving signal EN and the comparison driving signal LTCH_EN. The code signal generators 300 and 400 for generating the code signals P_CD <0: 4> and the feedback signal 200 are continuously activated in response to the initialization signal RST. And a controller 100 for repeatedly driving the generators 300 and 400.

The controller 100 generates a pulse signal CALP at a specific cycle in response to the initialization signal RST, and the auto-section signal CAL9 in response to the activation of the pulse signal CALP. ), And when the pulse signal CALP is activated N or more times, the end point notification unit 140 for activating the end signal CAL_STP and deactivating the auto-segment signal CAL9 and the pulse signal CALP The first driving signal EN activates the first driving signal EN and the comparison driving signal LTCH_EN and deactivates the first driving signal EN and the comparison driving signal LTCH_EN in response to the termination signal CAL_STP. The generation unit 160 includes a second driving signal generator 180 for generating the second driving signal AUTO_EN in response to the auto-section signal CAL9 and the initialization signal RST.

For reference, in the first embodiment, N is a natural number, which is 10.

In addition, the code signal generators 300 and 400 detect and output a level difference between the feedback signal P_FD with respect to the reference voltage VREF in response to the first driving signal EN and the comparison driving signal LTCH_EN. Comparator 300 and a counting unit 400 for up-counting or down-counting the code signal (P_CD <0: 4>) in response to the output signal of the comparator 300.

As described above, in the on-die termination circuit according to the present invention, the driving of the comparator 300 and the counting unit 400 is repeatedly performed while the feedback unit 200 is continuously turned on when the initialization signal RST is activated. do. In other words, even if the transition time of the feedback signal P_FD is longer as a result of the PVT variation, since the feedback unit 200 is continuously turned on, the feedback signal P_FD of the completed level is supplied after a certain transition time. do. Therefore, the comparator 300 and the counting unit 400 receive the feedback signal P_FD of the wrong level in the state where the transition is not completed during the initial driving. After that, the level of the feedback signal P_FD remains stable. In this state, since the driving of the comparator 300 and the counting unit 400 is repeatedly performed, an initial malfunction can be corrected.

6 is an internal circuit diagram of the feedback unit 200 of FIG. 5.

Referring to FIG. 6, the feedback unit 200 receives the first and second driving signals EN and AUTO_EN, and generates an input control signal and a code in response to the input control signal. A signal input unit 240 for receiving the signal P_CD <0: 4> and outputting the selection signal CD <0: 4>, and a selection signal CD <0: 4> for the input-resistance ZQ. A feedback signal providing unit 260 for outputting a voltage level of?) As a feedback signal P_FD.

The input controller 220 is an inverter for inverting the output signal of the NOR gate NR1 having the first and second driving signals EN and AUTO_EN and the NOR gate NR1 as an input-control signal. (I1).

The signal input unit 240 receives the input-control signal and the code signal P_CD <0> and applies the NAND gate ND1 for outputting the selection signal CD <0>, and applies the input-control signal and the code signal P_CD <1>. A NAND gate ND2 for receiving the selection signal CD <1>, an NAND gate ND3 for outputting the selection signal CD <2> by receiving an input-control signal and a code signal P_CD <2>, and -NAND gate for outputting the selection signal CD <3> by receiving the control signal and the code signal P_CD <3>, and the selection signal CD <4> by receiving the input-control signal and the code signal P_CD <4>. It includes a NAND gate (ND5) for outputting.

The feedback signal providing unit 260 has one of a plurality of code signals CD <0: 4> as a gate input, and the first to fifth PMOS transistors PM1, PM2, PM3, and PM4 having a source terminal connected to the voltage VDDQ. , PM5), a plurality of resistors R1, R2, R3, R4, R5 connected between the output terminal and the drain terminal of each of the PMOS transistors PM1, PM2, PM3, PM4, PM5, and the output node Including the input-resistance ZQ, the voltage across the output node is output as a feedback signal P_FD.

Referring briefly to the operation, when one of the first driving signal EN or the second driving signal AUTO_EN is activated, the input controller 220 activates the input-control signal to a logic level 'H' in response thereto.

Subsequently, the signal input unit 240 inverts the code signals P_CD <0: 4> in response to the logic level 'H' of the input-control signal and outputs the selected signals CD <0: 4>. In addition, when the input-control signal is deactivated to the logic level 'L', all of the selection signals CD <0: 4> are set to the logic level 'H, regardless of the level of the code signal P_CD <0: 4>. 'To disable it.

Subsequently, the feedback signal providing unit 260 connects a resistor connected to one end of the PMOS transistor turned on by activation of the corresponding signal among the selection signals CD <0: 4> to the output node in parallel, so that the feedback signal P_FD ) In other words, the feedback signal P_FD is determined by a pull-up resistor formed by parallel connection of the drain terminal of the active PMOS transistor connected to the output node and the resistance ratio of the input-resistance ZQ connected to the output node. The voltage level of is determined.

Meanwhile, the operation of the on die termination circuit illustrated in FIGS. 5 and 6 will be briefly described.

First, when the semiconductor memory device is initially driven, as the level of the external voltage is stabilized, the power-up signal PWRUP is activated in the form of a pulse. At this time, the initialization signal RST is also activated.

Subsequently, the pulse signal generator 120 generates the pulse signal CALP at regular intervals in response to the initialization signal RST. Subsequently, the end point notification unit 140 continuously activates the auto-section signal CAL9 in response to the activation of the first pulse signal CALP. Subsequently, the first driving signal generator 160 activates the first driving signal EN and the comparison driving signal LTCH_EN in the form of a pulse each time the pulse signal CALP is activated. In addition, the second driving signal generator 180 activates the second driving signal AUTO_EN in response to the activation of the auto-section signal CAL9 and the initialization signal RST. Here, the comparison driving signal LTCH_EN is activated twice while the first driving signal EN is activated once.

Subsequently, the feedback unit 200 converts the level of the code signal P_CD <0: 4> of the input-resistance ZQ into the feedback signal P_FD in response to the first or second driving signals EN and AUTO_EN. Output In other words, since the second driving signal AUTO_EN is continuously activated from the activation of the initialization signal RST to the deactivation of the auto-section signal CAL9, the feedback unit 200 is connected to the second driving signal AUTO_EN. It is continuously activated.

Next, the comparator 300 detects and outputs a level difference between the feedback signal P_FD with respect to the reference voltage VREF in response to the activation of the first driving signal EN and the comparison driving signal LTCH_EN. Next, the counting unit 400 down-counts or up-counts the current code signal P_CD <0: 4> according to the logic level of the output signal of the comparator 300 to perform a new code signal P_CD. <0: 4>).

Thereafter, when the end point notification unit 140 detects the pulse signal more than 10 times, the end point notification unit 140 deactivates the auto-section signal CAL9 and activates the end signal CAL_STP. Subsequently, the first driving signal generator 160 no longer generates the first driving signal EN and the comparison driving signal LTCH_EN in response to the termination signal CAL_STP. The second driving signal generator 180 inactivates the second driving signal AUTO_EN in response to the deactivation of the auto-section signal CAL9.

On the other hand, the on die termination circuit continuously activates the feedback section. Therefore, as the feedback unit is repeatedly turned on / off while the conventional comparator and the counting unit are repeatedly driven, a feedback signal having an incorrect level is applied to the comparator and the counting unit while the output signal of the feedback unit is not completely transitioned. Prevents malfunctions that occurred. In other words, by adjusting the feedback signal P_FD to have a level corresponding to the reference voltage VREF, the termination resistor supplied by the code signal P_CD <0: 4> is equal to the input-resistance ZQ. To have.

For reference, the reference voltage VREF has 1 / 2VDDQ. Therefore, the code signals P_CD <0: 4> are adjusted so that the feedback signal P_FD has the same 1 / 2VDDQ as the reference voltage.

As described above, the on-die termination circuit according to the present invention generates a plurality of bits of code signals such that an initialization signal is applied to set a termination resistor corresponding to the input-resistance, wherein the code signal has a voltage level with respect to the input-resistance. In transmitting as a feedback signal, it is continuously supplied for a predetermined time. Therefore, the feedback signal does not sufficiently transition at the time of driving the conventional comparator and the counting unit, thereby preventing a malfunction that has occurred.

As described above, the on-die termination circuit according to the first embodiment is continuously active while the on-die termination is driven, thereby preventing malfunctions caused by the transition time of the feedback signal by the on / off of the feedback unit. can do.

Meanwhile, in the on-die termination circuit according to the second embodiment of the present invention, the driving section of the feedback unit is shorter than the driving section of the on-die termination circuit so that the termination is performed in the same environment as when the on-die termination is driven in the auto refresh state. The resistance can be measured. This will be described in detail with reference to FIG. 7.

7 is an operation waveform diagram of an on die termination circuit according to a second exemplary embodiment of the present invention.

For reference, when the end point notification unit 140 according to the second embodiment activates the auto-section signal CAL9 in response to the activation of the pulse signal CALP, and the pulse signal CALP is activated at least M times, The auto-section signal CAL9 is deactivated, and when the pulse signal CALP is activated N times or more, the end signal CAL_STP is activated. Where M is less than N, and M and N are natural numbers. In the present embodiment, it is assumed that M is 9 and N is 15.

As illustrated in FIG. 7, when the initialization signal RST is applied and the pulse signal CALP is activated nine times or more, the end point notification unit 200 according to the second embodiment deactivates only the auto-section signal CAL9. Unlike the first embodiment, the termination signal CAL_STP is not activated.

Subsequently, the second driving signal generator 180 deactivates the second driving signal AUTO_EN in response to the deactivation of the auto-section signal AUTO_EN, and the first driving signal generator 160 generates the pulse signal CALP. Each time is activated, the pulse-shaped first driving signal EN and the comparison driving signal LTCH_EN are continuously activated. Here, the comparison driving signal LTCH_EN is activated twice each time during the first activation of the first driving signal EN.

Subsequently, since the feedback unit 200 is controlled only by the first driving signal EN activated in the form of a pulse, turn-on / turn-off is repeated. While the feedback unit 200 is turned on by the first driving signal EN, the comparison unit 300 and the counting unit 400 controlled by the comparison driving signal LTCH_EN are activated twice, and the feedback signal P_FD is activated. The code signal P_CD <0: 4> is generated to have a level corresponding to.

Thereafter, when the pulse signal CALP is detected 15 times or more, the end point notification unit 140 activates the end signal CAL_STP. Subsequently, the first driving signal generator 160 inactivates the first driving signal EN and the comparison driving signal LTCH_EN in response to the end signal CAL_STP.

As described above, the on-die termination circuit according to the second embodiment of the present invention provides the feedback unit 200 through the second driving signal AUTO_EN which is activated from the activation of the initialization signal RST until the auto-section signal CAL9 is deactivated. ) Is continuously activated, and the first section repeatedly driving the comparator 300 and the counting unit 400, and from the deactivation of the second driving signal AUTO_EN until the end signal CAL_STP is activated. The first driving signal EN repeatedly performs the turn-on / turn-off of the feedback unit 200 and has a second section for driving the comparator 300 and the counting unit 400 together.

That is, the feedback unit P_FD of the conventionally incompletely transitioned state is compared with the first unit for driving the comparator 300 and the counting unit 400 while the feedback unit 200 is continuously activated. 300 and the counting unit 400 may be prevented from malfunctioning caused by being applied. In addition, the auto-refresh command is applied after the initial setting of the termination resistor through the second section for driving the comparator 300 and the counting unit 400 while turning on / off the feedback unit 200 to terminate the termination resistor. Since the driving is performed under the same conditions as the resetting operation, the error of the normal operation can be minimized.

Meanwhile, in the second embodiment, when the pulse signal is applied more than 9 times, the second driving signal is inactivated. However, the present invention is not limited by the number of times of driving 15 times as one embodiment.

In addition, the present invention is not limited by the number of activation times of the first driving signal and the comparison driving signal after the initialization signal is applied.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

The present invention described above can supply a termination resistor that is insensitive to PVT (Process, Voltage, Temperature) change.

Claims (15)

Feedback means for outputting, as a feedback signal, a level of the plurality of bits of the code signal with respect to the input-resistance;

Code signal generating means for generating the plurality of bits of the code signal such that the feedback signal has a level corresponding to a reference voltage; And

Drive control means for repeatedly driving said code signal generation means while activating said feedback means in response to an initialization signal;

An on die termination circuit comprising:

The method of claim 1,

The control means,

A pulse signal generator for generating a pulse signal at a specific period in response to the initialization signal;

An end point notification unit for activating an auto-section signal in response to the activation of the pulse signal, deactivating the auto-section signal and activating an end signal when the pulse signal is activated N or more times;

A second driving signal generator for generating a second driving signal in response to activation of the auto-section signal and the initialization signal;

A first driving signal generator for activating a first driving signal and a comparison driving signal each time the pulse signal is activated, and deactivating the first driving signal and the comparison driving signal in response to the end signal;

The first or second driving signal controls the driving of the feedback means,

The first driving signal and the comparison driving signal control driving of the code signal generating means.

On die termination circuit characterized in that.

Feedback means for outputting, as a feedback signal, the level of the plurality of bits of the code signal with respect to the input-resist in response to the first and second drive signals;

Code signal generating means for generating the plurality of bits of code signals such that the feedback signal has a level corresponding to a reference voltage in response to the first driving signal and the comparison driving signal; And

In response to an initialization signal, activation of the second driving signal is continuously maintained during the first period, and the second driving signal is repeatedly activated during the second period, and the first driving signal during the first and second periods. And control means for repeatedly activating the comparison driving signal.

An on die termination circuit comprising:

delete

The method of claim 3,

The control means,

A pulse signal generator for generating a pulse signal at a specific period in response to the initialization signal;

An end point notification unit for activating an auto-section signal in response to the activation of the pulse signal, deactivating the auto-section signal when the pulse signal is activated M or more times, and activating an end signal when the pulse signal is activated N or more times;

A second driving signal generator for generating a second driving signal in response to activation of the auto-section signal and the initialization signal;

A first driving signal generator configured to activate the first driving signal and the comparison driving signal each time the pulse signal is activated, and not to activate the first driving signal and the comparison driving signal in response to the end signal;

M and N are natural numbers and M is smaller than N

On die termination circuit characterized in that.

The method according to claim 2 or 5,

The second driving signal generator,

A first NAND gate having the auto-division signal and the initialization signal as inputs;

And a first inverter for inverting the output signal of the first NAND gate and outputting the second drive signal.

On die termination circuit characterized in that.

The method of claim 6,

And said comparison drive signal is activated twice during activation of said first drive signal.

The method of claim 7, wherein

The feedback means,

An input controller configured to receive the first and second driving signals and generate an input-control signal;

A signal input unit for outputting the plurality of code signals as a selection signal of a plurality of bits in response to the input-control signal;

And a feedback signal providing unit for outputting a voltage level of the plurality of bits of the selection signal for the input-resistance as the feedback signal.

On die termination circuit characterized in that.

The method of claim 8,

The input control unit,

A first NOR gate having the first and second driving signals as inputs;

And a second inverter for inverting the output signal of the first NOR gate to output the input-control signal.

On die termination circuit characterized in that.

The method of claim 9,

The signal input unit,

A second NAND gate configured to receive the input-control signal and the first code signal and output a first selection signal;

A third NAND gate for receiving the input-control signal and the second code signal and outputting a second selection signal;

A fourth NAND gate for receiving the input control signal and the third code signal and outputting a third selection signal;

A fifth NAND gate for receiving the input-control signal and the fourth code signal and outputting a fourth selection signal;

On die termination circuit characterized in that.

The method of claim 10,

The feedback signal providing unit,

First to fifth PMOS transistors having one of first to fifth code signals as a gate input, and having a source terminal connected to the first voltage;

First to fifth resistors connected between the drain terminal of each of the first to fifth PMOS transistors and an output node thereof;

Including the input-resistance connected to the output node,

Outputting the voltage across the output node as the feedback signal

On die termination circuit characterized in that.

The method of claim 11,

The code signal generating means,

A comparator for detecting and outputting a level difference between the feedback signal with respect to a reference voltage in response to activation of the first driving signal and the comparison driving signal;

And a counting unit configured to up-count or down-count the first to fifth code signals in response to the output signal of the comparator.

On die termination circuit characterized in that.

Continuously outputting a level of the plurality of bits of the code signal with respect to the input-resistance as a feedback signal; And

During the outputting of the feedback signal, repeating the step of adjusting the code signal of the plurality of bits such that the feedback signal has a level corresponding to a target reference voltage.

On-die termination circuit driving method comprising a.

Outputting a level of the plurality of bits of the code signal with respect to the input resistance as a feedback signal;

Adjusting the plurality of bits of the code signal such that the feedback signal has a level corresponding to a target reference voltage,

During the first period, the adjusting step is repeatedly performed while the outputting step of the feedback signal is continuously performed.

Repeating the adjustment step while repeatedly turning on and off the feedback signal output step during the second period after the end of the first period;

A method of driving an on-dimination circuit, characterized in that.

The method of claim 5,

The first period means from the activation of the initialization signal to the time of deactivation of the auto-section signal,

The second section means from the deactivation time of the auto-section signal to the activation time of the end signal.