This paper addresses the framework for building critical recommended rules and a methodology for devising scoring
models using simulation or silicon data. Recommended rules need to be applied to critical layout configurations (edge or
polygon based geometric relations), which can cause yield issues depending on layout context and process variability.
Determining of critical recommended rules is the first step for this framework. Based on process specifications and
design rule calculations, recommended rules are characterized by evaluating the manufacturability response to
improvements in a layout-dependent parameter. This study is applied to critical 20nm recommended rules. In order to
enable the scoring of layouts, this paper also discusses a CAD framework involved in supporting use-models for
improving the DFM-compliance of a physical design.