Before trying to rely upon CPUID, a program must properly detect and sometimes
enable the instruction. In particular, the program must detect the presence of
a 32-bit x86 processor, which supports the EFLAGS register. Next -- if it is a
Cyrix or a NexGen processor -- the CPUID instruction may have to be enabled. Then
the program must try to toggle the ID bit in the EFLAGS register, to determine
whether the instruction is supported or not. Note that the program may face one
of the early Intel P5 processors: they do neither return a vendor ID string
nor the maximum supported standard level (when level 0000_0000h is queried).
Finally, notice that some chips support a partially programmable CPUID
instruction -- thanks to those idiot programmers who hard-coded "GenuineIntel"
all over the place...

If the PSN has been disabled, then the PSN feature flag will read as 0. In addition the value for the maximum
supported standard level (reported by standard level 0000_0000h, register EAX) will be lower.

#2

The Intel P6 processor does not support SEP, but inadvertently reports it.

#3

If the APIC has been disabled, then the APIC feature flag will read as 0.

#4

Early AMD K5 processors (SSA5) inadvertently used this bit to report PGE support.

#5

Some processors do support CMPXCHG8B, but don't report it by default. This is due to a Windows NT bug.

standard level 0000_0002h

input

EAX=0000_0002h

get processor configuration descriptors

output

AL

number of times this level must be queried to obtain all configuration descriptors #1

Because AL is 01h, one invocation of the level is enough to obtain all the
configuration descriptors. All of them are valid because their highest bits
are 0. This P6 processor includes a 4K/M code/data TLB, an 8+8 KB code/data
L1 cache and an integrated 512 KB code and data L2 cache.

notes

descriptions

#1

In a MP system special precautions must be taken when executing standard level 0000_0002h more than once.
In particular it must be ensured that the same CPU is used during that entire process.

#2

Programs must not expect any particular order for the reported configuration descriptors.

This level is only supported and enabled if the PSN feature flag is set. The
reported processor serial number should be combined with the vendor ID string
and the processor type/family/model/stepping value, to distinguish cases in
which two processors from different vendors happen to have the same serial
number. Finally, it should be noted that most vendors can not guarantee that
their serial numbers are truely unique.

standard level 0000_0004h

input

EAX=0000_0004h

get cache configuration descriptors #1

ECX=xxxx_xxxxh

cache level to query (e.g. 0=L1D, 1=L2, or 0=L1D, 1=L1I, 2=L2)

output

EAX

bits

description

31...26

cores per package - 1

25...14

threads per cache - 1

13...10

reserved

9

fully associative?

8

self-initializing?

7...5

cache level (starts at 1)

4...0

cache type (0=null, 1=data, 2=code, 3=unified, 4...31=reserved)

EBX

bits

description

31...22

ways of associativity - 1

21...12

physical line partitions - 1

11...0

system coherency line size - 1

ECX

bits

description

31...0

sets - 1

EDX

bits

description

31...3

reserved

2

complex indexing?

1

inclusive of lower levels?

0

write-back invalidate?

note

description

#1

This level is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug.

standard level 0000_0005h

input

EAX=0000_0005h

get MON information #1

output

EAX

bits

description

31...16

reserved

15...0

smallest monitor line size in bytes

EBX

bits

description

31...16

reserved

15...0

largest monitor line size in bytes

ECX

bits

description

31...2

reserved

1

treat interrupts as break events, even when interrupts are disabled

0

enumeration of MWAIT extensions (beyond EAX and EBX)

EDX

bits

description

31...28

number of C7 sub C-states for MWAIT

27...24

number of C6 sub C-states for MWAIT

23...20

number of C5 sub C-states for MWAIT

19...16

number of C4 sub C-states for MWAIT (starting with Core 7: C7)

15...12

number of C3 sub C-states for MWAIT (starting with Core 7: C6)

11...8

number of C2 sub C-states for MWAIT

7...4

number of C1 sub C-states for MWAIT

3...0

number of C0 sub C-states for MWAIT

note

description

#1

This level is only enabled if MISC_ENABLE.LCMV is set to 0. This is due to a Windows NT bug.

While Transmeta Crusoe processors have 256 entries, the CPUID definition constrains them to reporting only 255.
For compatibility reasons they report their unified TLB twice: once for the code TLB, and once for the data TLB.

extended level 8000_0006h

input

EAX=8000_0006h

get L2/L3 cache and L2 TLB configuration descriptors

output

EAX

4/2 MB L2 TLB configuration descriptor #1

bits

description

31...28

data TLB associativity #2

27...16

data TLB entries

15...12

code TLB associativity #2

11...0

code TLB entries

EBX

4 KB L2 TLB configuration descriptor #1

bits

description

31...28

data TLB associativity #2

27...16

data TLB entries

15...12

code TLB associativity #2

11...0

code TLB entries

ECX

unified L2 cache configuration descriptor #3

bits

description

31...16 #5

unified L2 cache size in KBs #4

15...12 #5

unified L2 cache associativity #2, #6

11...8 #5

unified L2 cache lines per tag

7...0

unified L2 cache line size in bytes

EDX

unified L3 cache configuration descriptor

bits

description

31...18

unified L3 cache size in 512 KB chunks

17...16

reserved

15...12

unified L3 cache associativity #2

11...8

unified L3 cache lines per tag

7...0

unified L3 cache line size in bytes

notes

descriptions

#1

A unified L2 TLB is indicated by a value of 0000h in the upper 16 bits.