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Designing Electronic Chips for Excellence

April 24, 2013

Electronic chips responsible for data processing in digital devices like computers and phones weren't always high on the list in the war against counterfeiting. However, as chips have become more complex, and components of the design and manufacturing process are divided among different parties, control over the end product no longer lies in the designer's hands, which increases vulnerability in terms of safety and reliability.

As counterfeiters and hackers target electronic hardware, NYU Abu Dhabi Assistant Professor of Computer Engineering Ozgur Sinanoglu believes the best way to safeguard chips is to build protective mechanisms into the hardware itself — effectively designing a chip that outsmarts attackers by making itself inaccessible to unauthorized users.

Sinanoglu, who directs the Design for Excellence (DfX) lab at NYUAD, leads a research team of four students — three NYU-Poly PhD students, Samah Saeed, Sachhidh Kannan, and Chandra K.H. Suresh; and Abishek Ramdas, an NYU-Poly master's student — as well as postdoctoral researcher Subidh Ali.

Sinanoglu's 13 years of experience in integrated circuit testing for manufacturing defects have given him a unique perspective as he approaches issues related to the security and reliability of chip design and production. Throughout his academic and professional career, including two years at telecommunications company Qualcomm, he has specialized in devising strategies to improve testing efficiency, a process that Sinanoglu said currently accounts for approximately 30 percent of total overall production costs.

During this time, he found that by considering testing accessibility in the design stage, manufacturers could make a chip with embedded hardware mechanisms allowing for deeper and more comprehensive access into different regions of the chip at the same time — facilitating more expedient testing. While the DfX lab continues research in the field of testing efficiency, it is using similar principles and techniques to tackle a range of emerging security threats that have propagated with increasingly globalized manufacturing processes.

"We are the first ones to take a testing approach to security," Sinanoglu said. "They bear a lot of similarities, namely defects and security attacks. Dealing with chip defects is a mature field that is 60 to 70 years old, and there are software tools and techniques that are already available that we can apply to security challenges. There are key differences between the two that must be considered as well, however. Defects are random in nature and are typically testable, while attacks have been deliberately camouflaged. We collaborate closely with Professor Ramesh Karri's group at NYU-Poly, who are security experts, in devising solutions against security threats."

Security threats include counterfeiting, in which defective fabricated chips that were rejected during testing, but not properly destroyed, are fed back into the supply chain. Intellectual circuit piracy may also occur when the designed chip is fabricated in an overseas production facility, which produces more than the original order, selling the surplus on the black market. Yet another form of attack is the injection of hardware Trojans directly into the chips during the process of fabrication — this additional hardware may later serve the malicious purpose of hacking or accessing information off the chip.

According to SEMI, a global industry association serving the manufacturing supply chain for micro- and nano-electronics industries, these kinds of security threats are estimated to result in a loss of USD 4 billion annually within the industry. Methods such as design encryption, through the addition of protective hardware on the chip, can help protect its integrity as it goes through various phases of the design and fabrication process.

While the DfX lab continues research in the field of testing efficiency, it is using similar principles and techniques to tackle a range of emerging security threats that have propagated with increasingly globalized manufacturing processes.

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"A chip design has inputs and outputs through which information enters and exits. If I, for example, add additional hardware into the design that is specifically controlled by additional inputs, I can make sure the design works only when correct inputs are fed in," Sinanoglu said. "This creates a locking mechanism controlled by the designer, so the chip can't be worked by someone who doesn't know the key for the right inputs. This logic encryption can be made more comprehensive by designing in a unique key for every fabricated chip — the key is held only by the designer, who must provide the key combination for production, providing the designer with a metering mechanism."

Protecting against human interference is not the only issue to address in ensuring the reliability of electronic chips, however. Sometimes integrated circuits are defect-free and have not been subject to malicious hardware, yet may still fail due to environmental interference. Transient errors, or glitches, may result from factors like radiation-induced alpha particles from the chip's material decay releasing and striking the chip. While this does not damage the chip, the particle, which carries a positive charge, can flip a value on the chip. These soft errors are typically seen as isolated events; however, these glitches, if large enough, may result in erroneous computations. As electronic chips become smaller and faster, they are more susceptible to this kind of error, which is particularly difficult to detect. The DfX research team is currently investigating hardware and software support to more effectively detect and correct these errors when they occur, improving the performance and power-efficiency of existing detection techniques.

Sinanoglu is also continuing his research in the field of chip testing, looking specifically at adaptive testing, which takes into account process variation that occurs during the manufacturing of chips. While chips of the same design are mass-produced on large-size wafers and then sliced into individual units, they may have very slight variations in certain elements such as wire thickness due to the minute size of each unit. Traditionally, testing has been conducted on chips uniformly, with the assumption that they are identical. However, adaptive testing first identifies characteristics of the chip and customizes the test to the individual chip, resulting in more accurate defect detection.

"Before you even fabricate the chips, you have a set of expectations on the possible variations of the chip that you might receive, so you can plan appropriate versions of the test," Sinanoglu explained. "The challenge that remains is how to categorize them in a way that when you pick a chip randomly, you know which test to apply. Ideally, slow and fast chips must be tested differently."

There are design techniques that may help, he said. For example, quick time-related measurements from monitoring circuitries added into a chip can help identify which group the chip belongs to, as these measurements correlate closely with the length of the critical path — the path that takes the longest computation time — on the chip. As the goal is to apply timing-based tests on the critical path of a chip, the result of these quick measurements can be used to efficiently select the most appropriate test for that particular chip.

As the DfX lab focuses on data chip security and reliability through developing built-in hardware design solutions and accompanying Computer-aided Design (CAD) software tools, it is also investigating cutting-edge technology in the area of memory storage and chip design.

The most prominent technology currently used for memory storage in computing and electronic devices, known as static random-access memory (SRAM), is beginning to reach its limits in terms of power efficiency, speed, and size. The most promising alternate logic and memory design technology with potential to make significant advances in these areas, resistive random-access memory (RRAM), is currently in the stage of investigation and development. The technology, which is nearing accessibility for commercial use, will have a significant impact on the electronic devices that pervade modern-day life. PhD student Kannan was the first Middle East-based recipient of the IBM Great Minds Internship in 2012, through which he is actively continuing his work in this area.

Sinanoglu, who joined NYUAD in the fall of 2010 and moved to Abu Dhabi the following year, has published more than 90 conference and journal papers, and has received three patents, while having several filed patents in process. He was also the recipient of the best paper award of VLSI Test Symposium 2011 for his published work, co-authored by PhD student Saeed, on controlling power dissipation in an electronic chip during the testing phase.