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Since 1987 - Covering the Fastest Computers in the World and the People Who Run ThemThu, 17 Aug 2017 22:33:47 +0000en-UShourly1https://wordpress.org/?v=4.8.160365857US, Europe, Japan Deepen Research Computing Partnershiphttps://www.hpcwire.com/2017/05/18/us-europe-japan-deepen-research-computing-partership/?utm_source=rss&utm_medium=rss&utm_campaign=us-europe-japan-deepen-research-computing-partership
https://www.hpcwire.com/2017/05/18/us-europe-japan-deepen-research-computing-partership/#respondThu, 18 May 2017 18:08:00 +0000https://www.hpcwire.com/?p=35712On May 17, 2017, a ceremony was held during the PRACEdays 2017 conference in Barcelona to announce the memorandum of understanding (MOU) between PRACE in Europe, RIST in Japan, and XSEDE in the United States. The MOU allows for the promotion and sharing of resources between the organizations, including PRACE’s federated resources in Europe, the […]

]]>On May 17, 2017, a ceremony was held during the PRACEdays 2017 conference in Barcelona to announce the memorandum of understanding (MOU) between PRACE in Europe, RIST in Japan, and XSEDE in the United States. The MOU allows for the promotion and sharing of resources between the organizations, including PRACE’s federated resources in Europe, the K computer and other systems in Japan, and XSEDE’s network of HPC systems and advanced digital services in the US.

Discussing details of the enhanced partnership were Dr. Anwar Osseyran, council chair of the Partnership for Advanced Computing in Europe (PRACE); John Towns, principal investigator and project director for the Extreme Science and Engineering Discovery Environment (XSEDE); and Masahiro Seki, president of the Research Organization for Information Science and Technology (RIST).

“The aim is to stimulate collaboration in the area of research and computational science by sharing information on the usage of supercomputers,” said Dr. Osseyran. “The collaboration will be of mutual benefit, reciprocity and equality and we will identify the capabilities of cooperation in the areas of science, technology and industry. [Further, the MOU] will reinforce the HPC ecosystems for all of us.”

The agreement builds on the partners’ work with the International HPC Summer School. (The eighth such event will take place June 25 to June 30, 2017, in Boulder, Colorado, United States. Compute Canada is also a partner.)

“As research becomes much more an international endeavor, the need for infrastructure to collaborate closely and support those research endeavors becomes even more important,” said John Towns. “Having the agreement such as the one we have signed now facilitates the collaboration of the infrastructures and allows us to promote science and engineering and industry work and the use of HPC resources and very importantly the associated services and support staff that surround them. Being able to effectively use these resources is quite important and often they are very difficult as the technology moves very rapidly, so having access to the expertise is also critical. I’m very happy to be a part of this and I look forward to our work [together].”

“The three parties — PRACE, XSEDE and RIST — have recognized the importance of trilateral collaboration,” said Masahiro Seki. “Finalizing the MOU today makes me happier than anything else. In the new MOU, we will continuously implement exchange of information in the area of promotional shared use of supercomputers; at the same time our collaboration will be accelerated through the users of all the members of the partnering organizations, and especially the trilateral union will be of great help to promote advanced supercomputing in the field of science and technology and in industry.”

The ceremony commemorates the official signing which took place on April 4, 2017. The agreement contains the following elements:

(1) Exchange of information: Mutual exchange of experiences and knowledge in user selection and user support etc. is helpful for the three parties in order to execute their projects more effectively and efficiently.

(2) Interaction amongst the staff of the parties in pursuing any identified collaboration opportunities: Due to the complex and international nature of science, engineering and analytics challenge problems that require highly advanced computing solutions, collaborative support between RIST, PRACE and XSEDE will enhance the productivity of globally distributed research teams.

(3) Holding technical meetings: Technical meetings will be held to support cross organizational information exchange and collaboration.

]]>The European Union is expanding its efforts to promote energy-efficient computing with funding for hardware research aimed at next-generation high-end processors.

“The European Commission wants Europe to avail [itself] of a new family of processors with a significantly better energy/performance ratio compared to current offerings, specifically tailored for high-performance, low-power server-side applications,” Sandro D’Elia of the European Commission, told a computing conference this week.

D’Elia, of the commission’s directorate for communications networks, content and technology, said the agency is seeking to harness exascale computing performance while supporting emerging Internet of Things and other applications requiring more horsepower and reduced power consumption.

The EU chip effort parallels and earlier Euroserver project that includes European electronics heavyweights such as SoftBank’s U.K.-based ARM chip unit and STMicroelectronics that is pursuing a next-generation “micro-server” or “server on a chip.” The effort assumes that shrinking the size of future server components will help reduce datacenter energy consumption.

The EU chip initiative also is being promoted by a project called High Performance and Embedded Architecture and Compilation. The latest iteration of the HiPEAC project was launched in January with a dozen European partners led by Ghent University.

The Euro processor effort is part of a European Commission technology effort called Horizon 2020. According to an EC solicitation released this week, “The trend towards ‘Smart Anything Everywhere’ must be supported by innovations allowing a very significant reduction of two complementary aspects: the cost and complexity of software development for modern architectures, and the energy footprint of computation and communication.”

Hence, chip initiative seeks to tackle the hardware limitations of current processor technologies, particularly efforts to deliver exascale computing based on low-power processors. “This is a serious problem for the development of very promising application areas, [for example], at the convergence between high performance computing, big data and deep learning,” a program overview stressed.

The EU effort envisions development of secure, low-power processors for platforms based on “highly parallel and heterogeneous architectures.” Targeted applications include server workloads and high-performance computing applications in datacenters where energy efficiency and size constraints are critical.

As data-driven architectures emerge, the effort also seeks to address processing applications that move low-power computing resource closer to data at the network edge. That means emerging low-power processor designs also will require hardware-based security features, program officials said.

As of Thursday (Nov. 10) the Horizon 2020 project reported that 264 proposals have been submitted related to the EU processor initiative. “Proposals will provide programming environments and tools optimized for specific application domains of significant economic value, ideally covering the complete software stack from runtime systems to application programming,” the project web site states.

Among the current technology limitations to be addressed are power density, thermal management, memory access speed and latency along with improving on- and off-chip communications. The effort also is targeting support for the growing list of real-time applications such as streaming data.

]]>Under the H2020 High Performance Computing call (Towards exascale high performance computing) MANGO project was awarded funding of 5.8 million euro for three years of research till October 2018. Coordinated by prof. Jose Flich from University of Valencia, consortium includes École polytechnique fédérale de Lausanne, Politecnico di Milano, University of Zagreb, Centro Regionale Information Communication Technology and industrial partners: Eaton Corporation, Pro Design Electronic GmbH, Thales Group and Philips.

The MANGO (exploring Manycore Architectures for Next-GeneratiOn HPC systems) research project aims at addressing power, performance and predictability (the PPP space) in future High-Performance Computing systems. It starts from the fundamental intuition that effective techniques for all three goals ultimately rely on customization to adapt the computing resources to reach the desired Quality of Service (QoS). From this starting point, MANGO will explore different but interrelated mechanisms at various architectural levels, as well as at the level of the system software. In particular, to explore a new positioning across the PPP space, MANGO will investigate system-wide, holistic, proactive thermal and power management aimed at extreme-scale energy efficiency

The performance/power efficiency wall poses the major challenge faced nowadays by HPC. Looking straight at the heart of the problem, the hurdle to the full exploitation of today computing technologies ultimately lies in the gap between the applications’ demand and the underlying computing architecture: the closer the computing system matches the structure of the application, the most efficiently the available computing power is exploited. Consequently, enabling a deeper customization of architectures to applications is the main pathway towards computation power efficiency.

The MANGO project will build on this consideration and will set inherent architecture-level support for application-based customization as one of its underlying pillars. In addition to mere performance and power-efficiency, it is of paramount importance to meet new nonfunctional requirements posed by emerging classes of applications. In particular, a growing number of HPC applications demand some form of time-predictability, or more generally Quality-of-Service (QoS), particularly in those scenarios where correctness depends on both performance and timing requirements and the failure to meet either of them is critical. Examples of such time-critical application include:

online video transcoding – the server-side on-the-fly conversion of video contents, which involves very computation-intensive operations on huge amounts of data to be performed within near real-time deadlines.

Time predictability and QoS, unfortunately, are a relatively unexplored area in HPC. While traditional HPC systems are based on a “the faster, the better” principle, realtimeness is a feature typically found in systems used for mission-critical applications, where timing constraints usually prevail over performance requirements. In such scenarios, the most straightforward way of ensuring isolation and time-predictability is through resource overprovisioning, which is in striking contrast to power/performance optimization.

In fact, predictability, power, and performance appear to be three inherently diverging perspectives on HPC. We collectively refer to this range of tradeoffs, well captured in figure above, as the PPP space. The combined optimization of PPP figures is made even more challenging by new delivery models, such as outsourced and cloud based HPC, which are dramatically widening the amount and the type of HPC demand. In fact, cloud enables resource usage and business model flexibility, but it inherently requires virtualization and large scale capacity computing support, where many unrelated, competing applications with very different workloads are served concurrently.

The essential objective of MANGO is to achieve extreme resource efficiency in future QoS-sensitive HPC through ambitious cross-boundary architecture exploration.

The research will investigate the architectural implications of the emerging requirements of HPC applications, aiming at the definition of new-generation high-performance, power-efficient, deeply heterogeneous architectures with native mechanisms for isolation and quality-of-service.

To achieve such ambitious objectives, MANGO will avoid conservative paths. Instead, its disruptive approach will challenge several basic assumptions, exploring new many-core architectures specifically targeted at HPC. The project will involve many different and deeply interrelated mechanisms at various architectural levels:

heterogeneous computing cores

memory architecture

interconnect

runtime resource management

power monitoring and cooling

programming models

In particular, to gain a system-wide understanding of the deep interplay of mechanisms along the PPP axes, MANGO will explore holistic proactive thermal and power management aimed at energy optimization, creating a hitherto inexistent link between hardware and software effects and involving all layers modeling in HPC server, rack, and datacenter conception.

Ultimately, the combined interplay of the multi-level innovative solutions brought by MANGO will result in a new positioning in the PPP space, ensuring sustainable performance as high as 100 PFLOPS for the realistic levels of power consumption delivered to QoS-sensitive applications in large-scale capacity computing scenarios.

Particularly relevant for current European HPC strategies, the results achieved by the project will provide essential building blocks at the architectural level enabling the full realization of the long-term objectives foreseen by the ETP4HPC strategic research agenda.

]]>https://www.hpcwire.com/2016/06/27/mango-project-tackles-power-performance-predictability-future-hpc/feed/028278EU Projects Unite on Heterogeneous ARM-based Exascale Prototypehttps://www.hpcwire.com/2016/02/24/eu-projects-unite-exascale-prototype/?utm_source=rss&utm_medium=rss&utm_campaign=eu-projects-unite-exascale-prototype
https://www.hpcwire.com/2016/02/24/eu-projects-unite-exascale-prototype/#respondWed, 24 Feb 2016 19:13:38 +0000http://www.hpcwire.com/?p=25152A trio of partner projects based in Europe – Exanest, Exanode and Ecoscale – are working in close collaboration to develop the building blocks for an exascale architecture prototype that will, as they describe, put the power of ten million computers into a single supercomputer. The effort is unique in seeking to advance the ARM64 + […]

]]>A trio of partner projects based in Europe – Exanest, Exanode and Ecoscale – are working in close collaboration to develop the building blocks for an exascale architecture prototype that will, as they describe, put the power of ten million computers into a single supercomputer. The effort is unique in seeking to advance the ARM64 + FPGA architecture as a foundational “general-purpose” exascale platform.

Funded for three years as part of Europe’s Horizon2020 program, the partners are coordinating their efforts with the goal of building an early “straw man” prototype late this year that will consist of more than one-thousand energy-efficient ARM cores, reconfigurable logic, plus advanced storage, memory, cooling and packaging technologies.

Exanest is the project partner that is focused on the system level, including interconnection, storage, packaging and cooling. And as the name implies, Exanode is responsible for the compute node and the memory of that compute node. Ecoscale focuses on employing and managing reconfigurable logic as accelerators within the system.

Exanest

Manolis Katevenis, the project coordinator for Exanest and head of computer architecture at FORTH-ICS in Greece, explains that Exanest has set an early target of 2016 to build this “relatively-large” first prototype, comprised of at least one-thousand ARM cores.

He says, “We are starting early with a prototype based on existing technology because we want system software to be developed and applications to start being ported and tuned. For the remainder of the two years, there will be ongoing software development, plus research on interconnects, storage and cooling technologies. We also believe that there will be new interesting compute nodes coming out from our partner projects and we will use such nodes.”

In discussing target workloads, Katevenis emphasizes flexibility and breadth, echoing the sentiments we are hearing from across the HPC community. The goal for this platform is to be able to support a range of applications, both on the traditional compute and physics side and the data-intensive side. A look at the Exanest partner list hints at the kind of high-performance applications that will be supported: astrophysics, nuclear physics, simulation-based engineering, and even in-memory databases with partner MonetDB Solutions. Allinea will be providing the ARMv8 profiling and debugging tools.

Although the projects are still in the specification phase, they will be making selections with the aim of overcoming the specific challenges related to exascale. Areas of focus include compact packaging, permanent storage, interconnection, resilience and application behavior. Some of the design decisions were revealed in this poster from Exanest that shows a diagram of the daughterboard and blade design. Note that Xilinx is a key partner.

To achieve a complete prototype capable of running real-world benchmarks and applications by 2018, the primary partners are collaborating with a number of other academic groups and industry partners using co-design principles to develop the hardware and software elements. This is a classic public-private arrangement where academic and industrial partners join forces and industrial partners benefit by being able to reuse the technology that is developed.

On the technology side, packaging and cooling is a key focus for Exanest, which will rely on Iceotope, the immersive cooling vendor, to design an innovative cooling environment. The first prototype will employ Iceotope technology and there is the expectation that technology with even higher power density will be developed as the project progresses.

One of the primary criteria for the project partners is low-energy consumption for the main processor. They have chosen 64-bit ARM processors as their main compute engine. Katevenis affirms that having a processor that consumes dramatically less power allows many more cores to be packaged in the same physical volume and within the same total power consumption budget. “One way we will achieve scale is this low-power consumption,” says the project lead, “but another is by having accelerators to provide floating point performance boost to appropriate applications.”

As for topology, the Exanest team is discussing the family of networks that includes fat trees and Dragonfly topology. They will be linking blades through optical fibers that they can plug and unplug allowing them to experiment with more than one topology. Exanest will also be using FPGAs for building the interconnection network so they can experiment with novel protocols.

Exanode

Denis Dutoit, the project coordinator for Exanode, tells HPCwire the goal of that project is to build a node-level prototype with technologies that exhibit exascale potential. The three building blocks are heterogeneous compute elements (ARM-v8 low-power processors plus various accelerators, namely FPGAs although ASICs and GPGPUs may also be explored); 3D interposer integration for compute density; and, continuing the efforts of the EUROSERVER project, an advanced memory scheme for low-latency, high-bandwidth memory access, scalable to exabyte levels.

Dutoit, who is the strategic marketing manager, architecture, IC design and embedded software division at CEA-Leti, notes that this is a technology driven project at the start, but on top of this prototype, there will be a complete software stack for HPC capability. Evaluation will be done first will be done on the node level, explains Dutoit. They will utilize emulated hardware first and representative HPC applications to evaluate at the level nodes, but after that, Exanest will reuse these compute nodes and integrate them into their complete machine to do the full testing and evaluation with real applications.

There will be a formal effort to productize the resulting technology through a partnership with Kaleao, a UK company that focuses on energy-efficient, compact hyperconverged platforms.

Ecoscale

Iakovos Mavroidis, project coordinator for Ecoscale, says that while there are three main projects, he sees it as one big project with Ecoscale dedicated to reconfigurable computing.

A member of Computer Architecture and VLSI Systems (CARV) Laboratory of FORTH-ICS and a member of Telecommunication Systems Institute, Mavroidis notes that the main problem being addressed is how to improve today’s HPC servers. Simple scaling without improving technologies is unfeasible due to utility costs and power consumption limitations. Ecoscale is tackling these challenges by proposing a scale-out hybrid MPI+OpenCL programming environment and a runtime system, along with a hardware architecture which is tailored to the needs of HPC applications. The programming model and runtime system follows a hierarchical approach where the system is partitioned into multiple autonomous workers (i.e. compute nodes).

“The main focus of Ecoscale is to support shared partitioned reconfigurable resources, accessed by these compute nodes,” says Mavroidis. “The intention is to have a global notion of the reconfigurable resources so that each compute node can access remote reconfigurable resources not only its own local resources. The logic can also be shared by several compute nodes working in parallel.” To accomplish this, workers are interconnected in a tree-like structure in order to form larger Partitioned Global Address Space (PGAS) partitions, which are further hierarchically interconnected via an MPI protocol.

“The virtualization will happen automatically in hardware and it has to be done because reconfigurable resources are very limited unless remote access is enabled,” states Mavroidis. “The aim is to provide a user-friendly way for the programmer to use all the reconfigurable logic in the system. This requires a very high-speed low-latency interconnection topology and this is what Exanest will provide.”

Mavroidis explains there must be means for the programmer to access the system and at a higher-level the run-time system has to be redefined to understand the needs of the application so it can reconfigure the machine. He believes that in order to fully implement this, there will need to be innovation in all the layers of the stack, and also the programming model itself will also need to be redefined. The partners are aiming to support most of the existing and common HPC libraries in order to make this architecture available to most of the existing applications.

The main focus of Ecoscale is to automate out the complexity of FPGA programming. Anyone who has watched FPGAs struggle to get a foothold in HPC knows this is not an easy task, but the need for low-power performance is driving interest and innovation. “The programmer should not have to be aware that the machine uses reconfigurable computing, but rather be able to write the program using high-level programming model such as MPI or Standard C,” states Mavroidis.

On a related note, Exanest project partner BeeGFS has just announced that the BeeGFS parallel file system is now available as open source from www.beegfs.com. “Although BeeGFS can already run out of the box on ARM systems today, this project [Exanest] will give us the opportunity to make sure that we can deliver the maximum performance on this architecture as well,” shares Bernd Lietzow, BeeGFS head for Exanest.

]]>https://www.hpcwire.com/2016/02/24/eu-projects-unite-exascale-prototype/feed/025152TOP500 Trends That Cannot Be Ignoredhttps://www.hpcwire.com/2015/11/16/christallizing-top500-trends-that-cannot-be-ignored/?utm_source=rss&utm_medium=rss&utm_campaign=christallizing-top500-trends-that-cannot-be-ignored
https://www.hpcwire.com/2015/11/16/christallizing-top500-trends-that-cannot-be-ignored/#commentsMon, 16 Nov 2015 14:01:07 +0000http://www.hpcwire.com/?p=22803The 46th edition of the twice-yearly TOP500 list is hot off the presses and while there’s not much to break the monotony at the peak, this is in many ways a pivotal edition of the list in that it makes it hard to dismiss two trends in particular: China’s ascendance and flattening growth trajectories. But before we […]

]]>The 46th edition of the twice-yearly TOP500 list is hot off the presses and while there’s not much to break the monotony at the peak, this is in many ways a pivotal edition of the list in that it makes it hard to dismiss two trends in particular: China’s ascendance and flattening growth trajectories.

But before we unpack those gleanings, let’s start at the top. Yes, Tianhe-2, the supercomputer developed by China’s National University of Defense Technology, is still number one for the sixth time in a row with a LINPACK performance of 33.86 petaflops (54.9 peak); and Titan, a Cray XK7 system installed at DOE’s Oak Ridge National Laboratory, is still number two with 17.59 petaflops LINPACK (27.1 peak).

As a matter of fact, the whole top-five block is right where it was in June 2013:

The only movement the list has seen in the past few years is in the bottom half of the top ten, where we see two newcomers, both Crays. At number six, the Trinity supercomputer, procured by the Alliance for Computing at Extreme Scale (ACES, a Los Alamos and Sandia national laboratories partnership), achieved 8.1 petaflops LINPACK (11 petaflops peak). At number eight, the Hazel-Hen system, installed at the HLRS – Höchstleistungsrechenzentrum Stuttgart, in Germany, reported 5.6 petaflops LINPACK (7.4 peak).

The Cray Trinity install is the first half of a much larger system, reportedly on track to reach 42 peak petaflops when it gets a massive Knight Landing injection in 2016 (it’s aggregate memory capacity will be 2.11 petabytes). The current install is a Cray XC30 based on “Haswells,” specifically Xeon E5-2698v3 16C 2.3GHz processors. When complete, Trinity will be a single system that contains both the Haswell parts and Intel’s next-generation Xeon Phi processors (Knights Landing). The Haswell partition provides a natural transition path for many of the legacy codes running on Cielo, the current NNSA supercomputer sited at Los Alamos. ACES’ RFP partner NERSC is using a similar strategy — and it’s Cori Phase 1 system will be live any day now (read more on NERSC’s new digs here).

“Hazel Hen” at the High Performance Computing Center Stuttgart (HLRS), member of the Gauss Centre for Supercomputing, got on the upper echelon of the list thanks to an upgrade that doubled its compute power from 2.7 to 5.6 petaflops. The Cray XC40 system, now officially open for operation as the most powerful HPC system of PRACE (Partnership for Advanced Computing in Europe), leverages the latest Intel Xeon processor technologies and the CRAY Aries interconnect with Dragonfly network topology. The installation’s 41 system cabinets host 7,712 compute notes with a total of 185,088 Intel Haswell E5-2680 v3 compute cores.

As the TOP500 authors observe, the top ten is experiencing a low level of turnover, a slowing trend that began in 2008. “Six of the top 10 systems were installed in 2011 or 2012, Tianhe-2 in 2013 and only Trinity, Hazel-Hen, and Shaheen II in Saudi Arabia were installed in 2015,” they write.

This stagnation has come to be reflected in long-term performance trajectories with the first, last and sum of systems figures lagging behind historical trends The growth of the average performance of all systems in the list has slowed since 2013, dropping to about 55 percent per years. The performance of the last system on the list (#500) has taken a marked turn in recent years: from 1994 to 2008 it grew by 90 percent per year, but since 2008 it only grows by 55 percent per year, the list authors point out.

Every year of stagnation the flattening effect becomes more clear with a break-point occurring in 2008 and 2013 as Berkeley Lab Deputy Director Horst Simon has elucidated. The numbers would be even flatter if not for the boost provided by strong turnover at the top in the 2011-2013 timeframe. Without a fresh crop of over-achievers, the overall lag has nothing to hide behind. And while there are multi-petaflops systems in the pipeline (the fulfillment of the CORAL and NERSC-8/ACES RFPs, speaking to US interests), they are arriving too late to offset the new trends.

That’s the big picture snapshot, but what this list is even more likely to be remembered for are changing global market dynamics, in which US dominance can no longer be taken for granted. This November, China proved it is serious about filling in its supercomputing portfolio, which it has expanded by nearly a factor of three — going from 37 in July to 109 systems today. This is an unquestionably a steep jump, but a look at China’s system share from year to year shows how this climb has played out since about 2000. The question here of course is whether this ground can be regained or if this is the new reality.

System share by country over time. US is pink and China is red. Source: TOP500

As list share is a zero sum game, the United States has lost TOP500 ground, falling to the lowest point since the TOP500 list was created in 1993 with just 199 systems on this list down from 233 in July. The European share has also declined — down to 107 systems compared to 141 on the last list. Europe now lags behind Asia, which now claims 173 systems, up from 107 from the previous list.

A few more important data points from the TOP500 authors:

China is at the number two position in terms of both system share and performance share (as it has been since June 2013).

The European share (107 systems compared to 141 last time) has fallen and is now lower than the Asian share of 173 systems., up from 107 in June 2015.

Japan has 36 systems, down from 39.

In Europe, Germany is the clear leader with 32 systems followed by France and the UK at 18 systems each.

Sugon, a vendor from China is now ahead of IBM in the system category with 49 systems.

There’s still a lot more to unpack. The official list will be published tomorrow and we will follow up with more insights and reporting from the TOP500 BoF, which takes place Tuesday night at the Austin Convention Center.

For now, the TOP500 folks have put together this poster (PDF), which offers a lot to ponder, like chip share, accelerator diversity and the rise of industry.

]]>https://www.hpcwire.com/2015/11/16/christallizing-top500-trends-that-cannot-be-ignored/feed/122803Europe Launches Ultrascale Computing Initiativehttps://www.hpcwire.com/2014/09/15/europe-launches-ultrascale-computing-initative/?utm_source=rss&utm_medium=rss&utm_campaign=europe-launches-ultrascale-computing-initative
https://www.hpcwire.com/2014/09/15/europe-launches-ultrascale-computing-initative/#respondMon, 15 Sep 2014 23:42:44 +0000http://www.hpcwire.com/?p=15149NESUS – or Network for Sustainable Ultrascale Computing – formed earlier this year to study the challenges of ultrascale computing. Launched with about 30 European partner countries, the cross-community initiative has grown to include 39 European countries and six countries from other continents. The goal: to produce a catalogue of open source applications for large-scale complex systems […]

]]>NESUS – or Network for Sustainable Ultrascale Computing – formed earlier this year to study the challenges of ultrascale computing. Launched with about 30 European partner countries, the cross-community initiative has grown to include 39 European countries and six countries from other continents. The goal: to produce a catalogue of open source applications for large-scale complex systems two to three orders of magnitude larger than today’s systems.

Funded by the European Cooperation in Science and Technology (COST), NESUS Action seeks to establish an open European research network that pursues sustainable strategies for ultrascale computing. The first step will be to identify synergies at the cross-section of HPC, large scale distributed systems, and big data with an emphasis on programmability, scalability, resilience, energy efficiency, and data management.

NESUS is one of the largest European research networks of this type. Coordinated by Universidad Carlos III de Madrid (UC3M), NESUS will provide a meeting place to facilitate scientific collaboration into various research topics, including sustainable system software and applications. NESUS also has the goal of promoting the leadership of Europe, as well as advancing science, the economy, and society.

Although there are other efforts targeting large scale computing systems research in Europe, COST Action projects like NESUS emphasize pan-European coordination, connectivity and networking as a means of reducing redundancy and inefficiency.

The program is part of a larger effort to develop large parallel supercomputers, exaflop-class systems, by the 2020 timeframe. The solution is likely to involve datacenters with hundreds of thousands of computers coordinating with distributed memory systems.

Ultrascale computers are expected to employ both parallel and distributed computing technologies. “Ultimately, the idea is to have both architectures converge to solve problems in what we call ultrascale,” said Jesús Carretero, professor in the UC3M Department of Computer Science and project coordinator.

“Ultrascale systems combine the advantages of distributed and parallel computing systems,” observes a statement from UC3M. “The former is a type of computing in which many tasks are executed at the same time coordinately to solve one problem, based on the principle that a big problem can be divided into many smaller ones that are simultaneously solved. The latter system, in both grid and cloud computing, uses a large number of computers organized into clusters in a distributed infrastructure, and can execute millions of tasks at the same time usually working on independent problems and big data.”

When it comes to the next generation of ultrascale computing systems, it’s not just the size that is being scaled, it is the complexity as well as the requirements for energy efficiency.

“We try to analyze all the challenges there are and see how they can be studied holistically and integrated, to be able to provide a more sustainable system,” explains Carretero.

“It is the largest COST Action ever, which shows the interest that exists for it,” the professor continued.

Under the NESUS banner, some two hundred scientists from more than 40 countries are exploring what the next generation of ultrascale computing systems will be like. Nearly 40 percent of the workforce are young researchers as part of COST’s commitment to sustainability is facilitating an ecosystem of scientists for the future of the European Union.

Although the NESUS project is scheduled to conclude in 2018, the program reflects a degree of targeted R&D that is crucial to fielding useful exascale-class systems by the 2020 timeline. Such machines are expected to enable major advances in genomics, weather/climate modeling, human brain research, and countless other disciplines. You can read more about the project’s six-phase approach, here.

]]>Edinburgh Parallel Computing Centre (EPCC) is announcing a new HPC cloud project, called Fortissimo, aimed at boosting the competitiveness of European industry, specifically small and medium-sized enterprises (SMEs) who use digital simulation and modeling. The three-year effort, which is being led by EPCC, will focus on the development of a cloud of HPC resources.

Fortissimo represents a consortium of 45 partners who have identified the need for a high performance computing cloud infrastructure to run simulation services. The effort aims to help the European manufacturing community better compete in the international marketplace.

Among the partners are manufacturing companies, application developers, domain experts, IT solution providers and HPC cloud service providers from 14 countries. Fortissimo is being coordinated by the University of Edinburgh and funded by the European Commission within the7th Framework Programme.

“With total costs of €22 million and funding from the European Commission of €16 million, this is a major project for EPCC,” explains EPCC Executive Director Dr. Mark Parsons.

It is understood that digital manufacturing provides a competitive advantage to companies small and large, but while larger, more established outfits are in a better position to access these tools, SMEs face greater technological and financial hurdles. In fact this segment of the manufacturing sector has been defined as the “missing middle” because they are missing out on the benefits of advanced computing.

“The goal of Fortissimo is to overcome this impasse through the provision of simulation services and tools running on a cloud infrastructure,” notes the project press release.

“A ‘one-stop-shop’ will greatly simplify access to advanced simulation, particularly to SMEs,” it continues “This will make hardware, expertise, applications, visualisation and tools easily available and affordable on a pay-per-use basis. In doing this Fortissimo will create and demonstrate a viable and sustainable commercial ecosystem.”

The first leg of the project will be to set up teams of projects – with each team involving a company with a modeling and simulation challenge, HPC experts and HPC service providers. The initial run will involve 45 partners and 20 experiments. The experiments, which have already been defined, include simulation of continuous casting and die casting, environmental control and urban planning, and aerodynamic design and optimization. There will be additional open calls for experiments at month 12 and month 18 of the project. EPCC expects the total participation will grow to around 90 partners and 50-60 experiments by the end of the project.

]]>https://www.hpcwire.com/2013/10/11/eu_launches_hpc_cloud_experiment/feed/08346PRACE Envisions Supercomputing for Allhttps://www.hpcwire.com/2013/09/24/prace_envisions_supercomputing_for_all/?utm_source=rss&utm_medium=rss&utm_campaign=prace_envisions_supercomputing_for_all
https://www.hpcwire.com/2013/09/24/prace_envisions_supercomputing_for_all/#respondTue, 24 Sep 2013 07:00:00 +0000http://www.hpcwire.com/2013/09/24/prace_envisions_supercomputing_for_all/PRACE is working directly with EU institutions, academia and industry to usher in the next frontier for HPC in Europe, to extend and leverage the benefits of advanced computing technology.

]]>Having brought its transformative powers to bear on the world of science, HPC is primed to work its magic on industry. Among the benefits of a well-executed HPC strategy are increased productivity, improved decision-making and an overall boost in innovation and competitiveness.

National and business interests around the world are turning to HPC to leverage its revitalizing potential as effects from the Great Recession linger much longer than anticipated. “To outcompute is to outcompete” has become the motto for the 21st century.

PRACE, the Partnership for Advanced Computing in Europe, has embraced another motto as well, and that’s “supercomputing for all.”

PRACE is working directly with EU institutions, academia and industry to usher in the next frontier for HPC in Europe, to extend and leverage the benefits of advanced computing technology. As provider of 80 percent of the HPC capacity for research in Europe, PRACE is well positioned to champion this new paradigm.

Catherine Rivière, Chair of the PRACE Council, weighed in at a recent event, where these topics were addressed. “In three years, some real breakthroughs have been realised because of the possibility to have access to big computers,” said Rivière. But given the competitive global landscape, “it is essential for European countries to keep access to such capacity and to make the best use of HPC in the upcoming years.”

Meeting oncoming challenges in fields like personalized medicine, climate change and energy independence will require “new tools to cope with big data; new working processes to take into account multi-disciplinary problems and teams; and new physical models,” notes Rivière.

Of course developing these technologies does not come cheaply. Konstantinos Glinos, Head of the eInfrastructure Unit at DG Connect in the European Commission, maintains that Europe will need “to increase its investments in HPC in order to be in a leading position.” He adds that ‘the challenge of ‘big data’ and the transition to ‘exascale’ computing provide an opportunity.”

The importance of HPC and partner technologies, cloud and big data, were the topic of a Science|Business debate held in Brussels earlier this month, called “Supercomputers for all: The next frontier for Europe’s high performance computing.” According to Rivière and other experts at the event “the full potential of the technology has yet to be explored, either by science or industry.”

]]>https://www.hpcwire.com/2013/09/24/prace_envisions_supercomputing_for_all/feed/03812ADEPT Emphasizes Energy-Efficient Parallelismhttps://www.hpcwire.com/2013/08/29/adept_emphasizes_energy-efficient_parallism/?utm_source=rss&utm_medium=rss&utm_campaign=adept_emphasizes_energy-efficient_parallism
https://www.hpcwire.com/2013/08/29/adept_emphasizes_energy-efficient_parallism/#respondThu, 29 Aug 2013 07:00:00 +0000http://www.hpcwire.com/2013/08/29/adept_emphasizes_energy-efficient_parallism/The EU-funded ADEPT project is exploring the energy-efficient use of parallel technologies by combining the talents of HPC and the embedded sector. The goal is to develop a tool for modeling and predicting the power and performance characteristics of parallel systems.

]]>It’s one of the most talked about issues in the HPC community: the sheer amount of power required by the coming generation of supercomputers. The figures are staggering. Built with today’s technology, the yearly power bill for an exascale machine would be in the neighborhood of a half-billion dollars.

Hitting the exascale target will require a cohesive yet multi-faceted effort. There are programs in place working on the various parts: the memory wall, the power wall, the programming challenge and so forth. The EU-funded ADEPT project is exploring the energy-efficient use of parallel technologies.

ADEPT, which stands for ADdressing Energy in Parallel Technologies, has two main parts: 1) help HPC software developers exploit parallelism for performance, and 2) assist embedded systems engineers with managing energy usage.

The end goal is the creation of a tool that will help users model and predict the power consumption and performance of their code.

In essence, ADEPT combines the talents of the HPC and embedded communities, drawing on the unique strengths of each sector: parallelization on the HPC side and energy management on the embedded side. It’s an opportunity for each discipline to learn from the other.

“The strength of the HPC world lies primarily in software application parallelisation: concurrent computation is used to speed up the overall time an application requires run to completion,” remarks the project website. “As a result, HPC software developers are also experts in parallel performance analysis and performance optimisation.”

It continues: “The embedded systems sector excels in managing energy usage because it is often constrained by fixed power and energy budgets.

“The strengths of one sector are the relative weakness of the other: power management and power efficiency in HPC are in their infancy, but they are becoming increasingly important with HPC systems requiring more and more power; and while continuing to be constrained by energy and power budgets, recent advances in low-power multi-core processors have widened the choice of hardware architectures for embedded systems and are increasingly forcing embedded programmers to use parallel computing techniques that are more familiar to HPC programmers.”

The program reflects the new energy-aware HPC paradigm. Between the high-cost of energy and its environmental implications, high-performance computing, and computing in general, have by necessity begun to emphasize performance-per-watt over pure performance. To this end, ADEPT aims to provide a better understanding of how parallel software and hardware use power. Reducing the power usage of large-scale applications will help make exascale systems more feasible from an economic and environmental standpoint.

ADEPT is scheduled to run three years, commencing on Sept. 1, 2013. The program is facilitated by Edinburgh Parallel Computing Centre, the supercomputing center at the University of Edinburgh, and includes partners Uppsala University (Sweden), Alpha Data (UK), Ericsson AB (Sweden) and Ghent University (Belgium).

]]>https://www.hpcwire.com/2013/08/29/adept_emphasizes_energy-efficient_parallism/feed/03900EGI Cloud: SLAs and Summer Schoolhttps://www.hpcwire.com/2013/08/28/egi_cloud_slas_and_summer_school/?utm_source=rss&utm_medium=rss&utm_campaign=egi_cloud_slas_and_summer_school
https://www.hpcwire.com/2013/08/28/egi_cloud_slas_and_summer_school/#respondWed, 28 Aug 2013 07:00:00 +0000http://www.hpcwire.com/2013/08/28/egi_cloud_slas_and_summer_school/The EGI Federated Cloud is a new kind of research e-infrastructure designed to serve the scientific community. In support of this mission, the EGI has contributed to a report on service level agreements and also provided hands-on training.

]]>As cloud computing has evolved, so have users’ expectations. Increasingly, users are demanding clearly specified, legally binding service level agreements (SLA) from their cloud providers. The EGI is providing guidance on this important aspect of cloud computing in a new European Commission report, called Cloud Computing Service Level Agreements.

“The rapid evolution of the cloud market is leading to the emergence of new services, new ways for service provisioning and new interaction and collaboration models both amongst cloud providers and service ecosystems exploiting cloud resources,” write the report’s authors.

“Service Level Agreements (SLAs) govern the aforementioned relationships by defining the terms of engagement for the participating entities,” they continue. “Besides setting the expectations by dictating the quality and the type of service, SLAs are also increasingly considered by the providers as the key differentiator to achieve competitive advantage.”

The report introduces recommendations for the complete SLA lifecycle and documents the on-going policy work on SLAs performed by the Cloud Select Industry Group (SIG). For the 11 key recommendations, the comprehensive 61-page document sets out a path to implementation, including a goal, proposed steps and potential contributors.

“There are many kinds of clouds out there and there is not just one special ‘Cloud SLA.'” explains Michel Drescher, EGI.eu’s Technical Manager. “For example at EGI we are providing an Infrastructure as a Service cloud platform. This is very different to what others are doing so we’re creating template SLAs to make it easier for small communities to get up and running.”

In other EGI cloud news, EGI.eu and the University of Messina provided training for users of the EGI Federated Cloud at the Cloud Summer School Almere, from July 22-26, 2013. The course provided students with hands-on experience on actual resources located in the Czech Republic (CESnet) and in Spain (CESGA).

In the past, instruction had been based on a simplified local test cloud, but this was the first time that the secure production cloud was employed in training exercises. Students ran their applications in a real secure federated cloud environment. EGI.eu plans to use this model as the template for further training sessions.

Leading the effort were Michel Drescher with EGI and Massimo Villari, professor at the University of Messina. Local support was provided by the Windesheim University and Genias Benelux.

“For us this is a step towards Cloud 2.0. where everything is much easier to set up,” reported Massimo Villari.

“For EGI.eu this was a very good experience, getting out of our comfort zone and not only provide services to scientists, but also to tutors. I also learned a lot from working with the students that brought in some fresh ideas,” said Michel Drescher.