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Progress on 450mm at G450C

At Semicon Europa last week, Paul Farrar, general manager of G450C, provided an update on the consortium’s progress in demonstrating 450mm process capability. He said 25 tools will be installed in the Albany cleanroom by the end of 2013, progress has been made on notchless wafers with a 1.5mm edge exclusion zone, they have seen significant progress in wafer quality, and automation and wafer carriers are working.

G450C is an initiative by five big chip makers — Intel, TSMC, GLOBALFOUNDRIES, IBM and Samsung – partnered with New York state and CNSE. The main goal is to develop 10nm capability on 450mm wafers in 2015 or 2016. “What we have to demonstrate is that a film on 300mm, when we scale it up to 450mm, we can do it with the same capability and, more importantly, at a very significantly reduced cost per process area. In other words $/cm2 need to go down significantly. That’s how you hit the scaling that we’ve typically seen in a wafer transition which is in the 30% range,” Farrar said.

G450C aims to develop 10nm capability on 450mm wafers in 2015/2016.

Farrar said the facility looks quite different now than it did in March, when it was fairly empty. 18 tools have been installed so far, with a total of 25 tools delivered into the Albany complex by the end of 2013. “2013 is the year that I call install and debug,” Farrar said. “We’ll have approximately 50% of the toolset in the facility by the year end. It doesn’t mean that they’ll all be up and running but they will be placed in Albany or virtually at the suppliers, with about 35% of the toolset coming in 2014 and the last little bit that will be delivered will be the lithography tool in early 2015.” The program is organized around unit processes, including: film deposition and growth, wafer clean and strip, CMP and other processes, inspection and metrology, etch and plasma strip, and lithography.

In call cases, G450C will have at least one process that will be required for the 14nm flow. In most cases (about 70%) they will have multiple suppliers, at least two and sometimes three. “At the end, we’ll have both unit process and what I would call modules – 2 or three step processes – demonstrated. And then our member companies will take those building blocks and they will put their devices and their IP and then go build out factories,” Farrar said.

Farrar showed data demonstrating significant progress in wafer quality. He noted that they now have one wafer supplier and a second one coming on line. He also said automation and carriers were working well. “I don’t think they’ll be showstoppers. There are always things you can learn but those are working reasonably well,” he said.

G450C is also trying to take advantage of having a clean slate to make a switch from notched wafers – which provide a useful indicator regarding the crystal orientation of the silicon – to notchless wafers, which are perfect circles. “If you think about the physics around a notch, it really makes it difficult to get uniform films,” Farrar said. “A circle is a lower stress form. We get 1-1.5% better in getting closer to the edge. Using chips around the notch and perhaps getting to 1.5mm edge exclusion. We won’t get there if we don’t have notchless wafers. Our goal is to collaborate with our IC makers, our tool suppliers and materials suppliers, along with our facilities group.”

Probably the most critical part of the 450mm puzzle is lithography. Farrar said the consortia has been working with Nikon. “We were able to work with Nikon so that we now have immersion capability, in Japan, starting in June of 2014 and we’ll then have that tool installed in Albany at the end of the first quarter of 2015. We will have a true lithography capability which will enable us to get the efficient and actual process recipes that the deposition supplier will need to see so that they can demonstrate the capabilities at the 450 wafer form factor,” he said. “In the interim, we’re working on DSA (directed self assembly). We’re starting to see some pretty good results. I don’t think this will be a high volume technique but it’s a way that we can get something that works started in the early process modules in 2013 and early 2014.”

Wafer quality has improved, and wafer reclaim efforts are underway. “When we started this program, we had a handful of wafers. That was in the 2012 timeframe. We started to get reasonable test and monitor wafers in late 2012, and if you look at where we are today, in the 2nd half of 2013, we have a quality spec where we’re hitting bout 98% of the area is in spec, and the particle level is effectively every wafer is meeting the specification. We still need a little work on wafer flatness,” Farrar said. The next step is what he called “prime” wafers, which they expect to have in the middle of 2014.

Due to the delay of Intel’s 14nm FinFET manufacturing to the first quarter of 2014, TSMC’s first 16nm FinFET will be the most advanced process technology to be manufactured below Intel’s 22nm node in the 4th quarter of 2013. The device electrical transfer characteristics to be presented at the IEDM look impressive, and will be very interesting if Intel’s 14nm FinFET data could be published for a comparison.