Carry Look Ahead Adders

Carry Look Ahead Adder:

In ripple carry adders, the carry propagation time is the major speed limiting factor asseen in the previous lesson.

Most other arithmetic operations, e.g. multiplication and division are implemented usingseveral add/subtract steps. Thus, improving the speed of addition will improve the speedof all other arithmetic operations.

Accordingly, reducing the carry propagation delay of adders is of great importance.

Different logic design approaches have been employed to overcome the carrypropagation problem.

One widely used approach employs the principle of carry look-ahead solves this problemby calculating the carry signals in advance, based on the input signals.

This type of adder circuit is called as carry look-ahead adder (CLA adder). It is based onthe fact that a carry signal will be generated in two cases:

(1) when both bits Ai and Bi are 1, or

(2) when one of the two bits is 1 and the carry-in (carry of the previous stage) is 1.

To understand the carry propagation problem, let’s consider the case of adding two n-bitnumbers A and B.The Figure shows the full adder circuit used to add the operand bits in the ith column;namely Ai & Bi and the carry bit coming from the previous column (Ci ).

In this circuit, the 2 internal signals Pi and Gi are given by:

Pi = Ai ⊕ Bi ……………………..(1)G i = Ai B i ……………….……(2)

The output sum and carry can be defined as :

Si = Pi ⊕ Ci ……………………(3)C i +1 = G i + Pi C i …………(4)

Gi is known as the carry Generate signal since a carry (Ci+1) is generated whenever Gi=1, regardless of the input carry (Ci).

In other words, each carry signal is expressed as a direct SOP function of C0 rather thanits preceding carry signal.

Since the Boolean expression for each output carry is expressed in SOP form, it can beimplemented in two-level circuits.

The 2-level implementation of the carry signals has a propagation delay of 2 gates, i.e.,2τ.

The 4-bit carry look-ahead (CLA) adder consists of 3 levels of logic:

First level: Generates all the P & G signals. Four sets of P & G logic (each consists of anXOR gate and an AND gate). Output signals of this level (P’s & G’s) will be valid after1τ.

Second level: The Carry Look-Ahead (CLA) logic block which consists of four 2-levelimplementation logic circuits. It generates the carry signals (C1, C2, C3, and C4) asdefined by the above expressions. Output signals of this level (C1, C2, C3, and C4) will bevalid after 3τ.

Third level: Four XOR gates which generate the sum signals (Si) (Si = Pi ⊕ Ci). Outputsignals of this level (S0, S1, S2, and S3) will be valid after 4τ.Thus, the 4 Sum signals (S0, S1, S2 & S3) will all be valid after a total delay of 4τcompared to a delay of (2n+1)τ for Ripple Carry adders.

For a 4-bit adder (n = 4), the Ripple Carry adder delay is 9τ.

The disadvantage of the CLA adders is that the carry expressions (and hence logic)become quite complex for more than 4 bits.

Thus, CLA adders are usually implemented as 4-bit modules that are used to build largersize adders.

Binary Parallel Adder/Subtractor:

The addition and subtraction operations can be done using an Adder-Subtractor circuit.The figure shows the logic diagram of a 4-bit Adder-Subtractor circuit. B3 A3 B2 A2 B1 A1 B0 A0

C3 C2 C1 C0 FA FA FA FA

C4 S3 S2 S1 S0The circuit has a mode control signal M which determines if the circuit is to operate as anadder or a subtractor.

Each XOR gate receives input M and one of the inputs of B, i.e., Bi. To understand thebehavior of XOR gate consider its truth table given below. If one input of XOR gate iszero then the output of XOR will be same as the second input. While if one input ofXOR gate is one then the output of XOR will be complement of the second input. A B XOR 0 0 0 0 1 1 1 0 1 1 1 0

(see animation in authorware)

So when M = 0, the output of XOR gate will be Bi ⊕ 0 = Bi. If the full adders receive thevalue of B, and the input carry C0 is 0, the circuit performs A plus B.

When M = 1, the output of XOR gate will be Bi ⊕ 1 = Bi’. If the full adders receive thevalue of B’, and the input carry C0 is 1, the circuit performs A plus 1’s complement of Bplus 1, which is equal to A minus B.BCD Adder:If two BCD digits are added then their sum result will not always be in BCD.Consider the two given examples. 0110 = 6 Correct: Result +0011 = +3 is in BCD. 1001 = 9

0101 = 5 Wrong: Result is +0111 = + 7 not in BCD. 1100 = 12In the first example, result is in BCD while in the second example it is not in BCD.

Four bits are needed to represent all BCD digits (0 – 9). But with four bits we canrepresent up to 16 values (0000 through 1111). The extra six values (1010 through 1111)are not valid BCD digits.

Correction is done through the addition of 6 to the result to skip the six invalid values asshown in the truth table by yellow color.Consider the given examples of non-BCD sum result and its correction.

The logic circuit that checks the necessary BCD correction can be derived by detectingthe condition where the resulting binary sum is 01010 through 10011 (decimal 10through 19).

It can be done by considering the shown truth table, in which the function F is true whenthe digit is not a valid BCD digit. It can be simplified using a 5-variable K-map.

But detecting values 1010 through 1111 (decimal 10 through 15) can also be done byusing a 4-variable K-map as shown in the figure.

Values greater than 1111, i.e., from 10000 through 10011 (decimal 16 through 19) can bedetected by the carry out (CO) which equals 1 only for these output values. So, F = CO =1 for these values. Hence, F is true when CO is true OR when (Z3 Z2 + Z3 Z1) is true.Thus, the correction step (adding 0110) is performed if the following function equals 1: F = CO + Z3 Z2 + Z3 Z1The circuit of the BCD adder will be as shown in the figure.

Addend Augend

Carry 4-bit binary Carry

The two BCD digits, together with the input carry, are first added in the top 4-bit binaryadder to produce the binary sum. The bottom 4-bit binary adder is used to add thecorrection factor to the binary result of the top binary adder.

Note: ¾ When the Output carry is equal to zero, the correction factor equals zero. ¾ When the Output carry is equal to one, the correction factor is 0110.

The output carry generated from the bottom binary adder is ignored, since it suppliesinformation already available at the output-carry terminal.

A decimal parallel adder that adds n decimal digits needs n BCD adder stages. Theoutput carry from one stage must be connected to the input carry of the next higher-orderstage.

Binary Multiplier:Multiplication of binary numbers is performed in the same way as with decimal numbers.The multiplicand is multiplied by each bit of the multiplier, starting from the leastsignificant bit.

The result of each such multiplication forms a partial product. Successive partial productsare shifted one bit to the left.

The product is obtained by adding these shifted partial products.

Example 1: Consider an example of multiplication of two numbers, say A and B (2 bits

each), C = A x B.

The first partial product is formed by multiplying the B1B0 by A0. The multiplication oftwo bits such as A0 and B0 produces a 1 if both bits are 1; otherwise it produces a 0 likean AND operation. So the partial products can be implemented with AND gates.

The second partial product is formed by multiplying the B1B0 by A1 and is shifted oneposition to the left.

(see animation in authorware)

The two partial products are added with two half adders (HA). Usually there are morebits in the partial products, and then it will be necessary to use FAs.

The least significant bit of the product does not have to go through an adder, since it isformed by the output of the first AND gate as shown in the Figure.A binary multiplier with more bits can be constructed in a similar manner.