A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second...http://www.google.com/patents/US7459791?utm_source=gb-gplus-sharePatent US7459791 - Post passivation interconnection schemes on top of IC chip

A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Images(6)

Claims(20)

1. A chip comprising:

a silicon substrate;

a first internal circuit in or on said silicon substrate;

an ESD circuit in or on said silicon substrate;

a dielectric layer over said silicon substrate;

a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said ESD circuit;

a first via in said dielectric layer and directly over said first internal circuit, wherein said first via is connected to said first internal circuit;

a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride;

a second via in said passivation layer, wherein said second via is connected to said first interconnecting structure;

a third via in said passivation layer and directly over said first via, wherein said third via is connected to said first via; and

a second interconnecting structure over said passivation layer and over said second and third vias, wherein said second interconnecting structure is connected to said second and third vias, and wherein said ESD circuit is connected to said first internal circuit through, in sequence, said first interconnecting structure, said second via, said second interconnecting structure, said third via and said first via.

2. The chip of claim 1 further comprising a second internal circuit in or on said silicon substrate, a third interconnecting structure over said silicon substrate and in said dielectric layer, wherein said third interconnecting structure is connected to said second internal circuit, and a fourth via in said passivation layer, wherein said fourth via is connected to said second and third interconnecting structures, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first via, said third via, said second interconnecting structure, said fourth via and said third interconnecting structure, and wherein said ESD circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said second via, said second interconnecting structure, said fourth via and said third interconnecting structure.

3. The chip of claim 2 further comprising a third internal circuit in or on said silicon substrate, wherein said third internal circuit is connected to said second internal circuit through said third interconnecting structure, wherein said first internal circuit is connected to said third internal circuit through, in sequence, said first via, said third via, said second interconnecting structure, said fourth via and said third interconnecting structure, and wherein said ESD circuit is connected to said third internal circuit though, in sequence, said first interconnecting structure, said second via, said second interconnecting structure, said fourth via and said third interconnecting structure.

4. The chip of claim 1, wherein said second interconnecting structure comprises a power bus over said passivation layer and over said second and third vias, wherein said power bus is connected to said second and third vias, and wherein said ESD circuit is connected to said first internal circuit through said power bus.

5. The chip of claim 1, wherein said second interconnecting structure comprises a ground bus over said passivation layer and over said second and third vias, wherein said ground bus is connected to said second and third vias, and wherein said ESD circuit is connected to said first internal circuit through said ground bus.

6. A chip comprising:

a silicon substrate;

a first internal circuit in or on said silicon substrate;

an ESD circuit in or on said silicon substrate;

a dielectric layer over said silicon substrate;

a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said ESD circuit;

a first via in said dielectric layer and directly over said first internal circuit, wherein said first via is connected to said first internal circuit;

a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride;

a polymer layer over said passivation layer;

a second via in said polymer layer, wherein said second via is connected to said first interconnecting structure;

a third via in said polymer layer and directly over said first via, wherein said third via is connected to said first via; and

a second interconnecting structure in said polymer layer and over said passivation layer, wherein said second interconnecting structure is connected to said second and third vias, and wherein said ESD circuit is connected to said first internal circuit through, in sequence, said first interconnecting structure, said second via, said second interconnecting structure, said third via and said first via.

7. The chip of claim 6 further comprising a second internal circuit in or on said silicon substrate, a third interconnecting structure over said silicon substrate and in said dielectric layer, wherein said third interconnecting structure is connected to said second internal circuit, and a fourth via in said polymer layer, wherein said fourth via is connected to said second and third interconnecting structures, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said first via, said third via, said second interconnecting structure, said fourth via and said third interconnecting structure, and wherein said ESD circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said second via, said second interconnecting structure, said fourth via and said third interconnecting structure.

8. The chip of claim 7 further comprising a third internal circuit in or on said silicon substrate, wherein said third internal circuit is connected to said second internal circuit through said third interconnecting structure, wherein said first internal circuit is connected to said third internal circuit through, in sequence, said first via, said third via, said second interconnecting structure, said fourth via and said third interconnecting structure, and wherein said ESD circuit is connected to said third internal circuit through, in sequence, said first interconnecting structure, said second via, said second interconnecting structure, said fourth via and said third interconnecting structure.

9. The chip of claim 6, wherein said second interconnecting structure comprises a power bus in said polymer layer and over said passivation layer, wherein said power bus is connected to said second and third vias, and wherein said ESD circuit is connected to said first internal circuit through said power bus.

10. The chip of claim 6, wherein said second interconnecting structure comprises a ground bus in said polymer layer and over said passivation layer, wherein said ground bus is connected to said second and third vias, and wherein said ESD circuit is connected to said first internal circuit through said ground bus.

11. The chip of claim 6, wherein said polymer layer has a thickness greater than 2 micrometers.

12. A chip comprising:

a silicon substrate;

a first internal circuit in or on said silicon substrate;

an ESD circuit in or on said silicon substrate;

a dielectric layer over said silicon substrate;

a first interconnecting structure over said silicon substrate and in said dielectric layer, wherein said first interconnecting structure is connected to said ESD circuit;

a second interconnecting structure over said silicon substrate and in said dielectric layer, wherein said second interconnecting structure is connected to said first internal circuit;

a passivation layer over said dielectric layer, wherein said passivation layer comprises a nitride;

a first via in said passivation layer, wherein said first via is connected to said first interconnecting structure;

a second via in said passivation layer, wherein said second via is connected to said second interconnecting structure;

a third interconnecting structure over said passivation layer and over said first and second vias, wherein said third interconnecting structure is connected to said first and second vias, wherein said ESD circuit is connected to said first internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure, and wherein said ESD circuit is connected, in parallel with said first internal circuit, to an external connection point of said third interconnecting structure; and

a polymer over said third interconnecting structure and over said passivation layer.

13. The chip of claim 12 further comprising a second internal circuit in or on said silicon substrate, wherein said second interconnecting structure is connected to said second internal circuit, wherein said first internal circuit is connected to said second internal circuit through said second interconnecting structure, and wherein said ESD circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure.

14. The chip of claim 13 further comprising a third internal circuit in or on said silicon substrate, wherein said second interconnecting structure is connected to said third internal circuit, wherein said first and second internal circuits are connected to said third internal circuit through said second interconnecting structure, and wherein said ESD circuit is connected to said third internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said second via and said second interconnecting structure.

15. The chip of claim 13 further comprising a third internal circuit in or on said silicon substrate, a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said fourth interconnecting structure is connected to said third internal circuit, and a third via in said passivation layer, wherein said third via is connected to said third and fourth interconnecting structures, wherein said first and second internal circuits are connected to said third internal circuit through, in sequence, said second interconnecting structure, said second via, said third interconnecting structure, said third via and said fourth interconnecting structure, and wherein said ESD circuit is connected to said third internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said third via and said fourth interconnecting structure.

16. The chip of claim 15 further comprising a fourth internal circuit in or on said silicon substrate, wherein said fourth interconnecting structure is connected to said fourth internal circuit, wherein said third internal circuit is connected to said fourth internal circuit through said fourth interconnecting structure, wherein said first and second internal circuits are connected to said fourth internal circuit through, in sequence, said second interconnecting structure, said second via, said third interconnecting structure, said third via and said fourth interconnecting structure, and wherein said ESD circuit is connected to said fourth internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said third via and said fourth interconnecting structure.

17. The chip of claim 12 further comprising a second internal circuit in or on said silicon substrate, a fourth interconnecting structure over said silicon substrate and in said dielectric layer, wherein said fourth interconnecting structure is connected to said second internal circuit, and a third via in said passivation layer, wherein said third via is connected to said third and fourth interconnecting structures, wherein said first internal circuit is connected to said second internal circuit through, in sequence, said second interconnecting structure, said second via, said third interconnecting structure, said third via and said fourth interconnecting structure, and wherein said ESD circuit is connected to said second internal circuit through, in sequence, said first interconnecting structure, said first via, said third interconnecting structure, said third via and said fourth interconnecting structure.

18. The chip of claim 12, wherein said third interconnecting structure comprises a power bus over said passivation layer and over said first and second vias, wherein said power bus is connected to said first and second vias, and wherein said ESD circuit is connected to said first internal circuit through said power bus.

19. The chip of claim 12, wherein said third interconnecting structure comprises a ground bus over said passivation layer and over said first and second vias, wherein said ground bus is connected to said first and second vias, and wherein said ESD circuit is connected to said first internal circuit through said ground bus.

20. The chip of claim 12, wherein said passivation layer further comprises an oxide.

Description

This application is a continuation of application Ser. No. 11/273,071, filed on Nov. 14, 2005, now pending, which is a continuation of application Ser. No. 10/653,628, filed on Sep. 2, 2003, now pending, which is a continuation of application Ser. No. 10/278,106, filed on Oct. 22, 2002, now U.S. Pat. No. 6,734,563, which is a division of application Ser. No. 09/691,497, filed on Oct. 18, 2000, now U.S. Pat. No. 6,495,442.

RELATED PATENT APPLICATIONS

This application is related to U.S. Ser. No. 09/251,183, filed on Feb. 17, 1999, now U.S. Pat. No. 6,383,916, which is a continuation-in-part of U.S. Ser. No. 09/216,791, filed on Dec. 21, 1998, now abandoned. This application is also related to U.S. Ser. No. 09/637,926, filed on Aug. 14, 2000, now abandoned.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of post-passivation processing for the creation of conductive interconnects.

(2) Description of the Prior Art

Improvements in semiconductor device performance are typically obtained by scaling down the geometric dimensions of the Integrated Circuits; this results in a decrease in the cost per die while at the same time some aspects of semiconductor device performance are improved. The metal connections which connect the Integrated Circuit to other circuit or system components become of relative more importance and have, with the further miniaturization of the IC, an increasingly negative impact on the circuit-performance. The parasitic capacitance and resistance of the metal interconnections increase, which degrades the chip performance significantly. Of most concern in this respect is the voltage drop along the power and ground buses and the RC delay of the critical signal paths. Attempts to reduce the resistance by using wider metal lines result in higher capacitance of these wires.

To solve this problem, one approach has been to develop low resistance metal (such as copper) for the wires while low dielectric materials are used in between signal lines. Current practice is to create metal interconnection networks under a layer of passivation, this approach however limits the interconnect network to fine line interconnects, associated with parasitic capacitance and high line resistivity. The latter two parameters, because of their relatively high values, degrade device performance, resulting in even more severe effects for higher frequency applications and for long interconnect lines that are, for instance, used for clock distribution lines. Also, fine line interconnect metal cannot carry high values of current that is typically needed for ground busses and for power busses.

It has previously been stated that it is of interest to the semiconductor art to provide a method of creating interconnect lines that removes typical limitations that are imposed on the interconnect wires, such as unwanted parasitic capacitances and high interconnect line resistivity. The invention provides such a method. An analogy can be drawn in this respect whereby the currently (prior art) used fine-line interconnection schemes, which are created under a layer of passivation, are the streets in a city; in the post-passivation interconnection scheme of the present invention, the interconnections that are created above a layer of passivation can be considered the freeways between cities.

FIG. 1 shows a cross section of a silicon substrate on the surface of which has been created a conductive interconnect network. The structure that is shown in cross section in FIG. 1 addresses only and is limited to prior art power and ground distribution networks. The various features that have been highlighted in FIG. 1 are the following:

40, a silicon substrate on the surface of which has been created an interconnect network

42, a sample number of semiconductor circuits that have been created in or on the surface of the substrate 40

44, two electrostatic discharge (ESD) circuits created in or on the surface of the substrate 40; one ESD circuit is provided for each pin that is accessible for external connections (pins 52, see below)

46 is a layer in which interconnect lines are provided; these interconnect lines are above the surface of substrate 40 and under the layer 48 of passivation and represent a typical application of prior art fine-line interconnects; these fine-line interconnects in layer 46 typically have high resistivity and high parasitic capacitance

48 is a layer of passivation that is deposited over the surface of the layer 46 in which interconnect lines are provided

50 is a power or ground bus that connects to the circuits 42 via fine-line interconnect lines provided in layer 46; this power or ground bus 50 is typically of wider metal since this power or ground bus carries the accumulated current or ground connection for the devices 42

52 is a power or ground pin that passes through the layer 48 of passivation and that has been connected to the power or ground bus 50.

From the above the following can be summarized: circuits 42 and 44 are created in or on the surface of a silicon substrate 40, interconnect lines in layer 46 are created for these circuits 42 and 44 for further interconnection to external circuitry, the circuits 42 and 44 are, on a per I/O pin basis, provided with an ESD circuit 44, these circuits 42 together with the ESD circuit 44 are connected to a power or ground pin 52 that penetrates a layer 48 of passivation. The layer 48 of passivation is the final layer that overlies the created interconnect line structure, and the interconnect lines underneath the layer 48 of passivation are fine line interconnects and have all the electrical disadvantages of fine line interconnects such as high resistivity and high parasitic capacitance.

Relating to the cross section that is shown in FIG. 1, the following comments applies: ESD circuits 44 are, as is known-in the art, provided for the protection of semiconductor circuits 42 against unexpected electrical charges. For this reason, each pin that connects to a semiconductor circuit 42 must be provided with an ESD circuit 44.

FIG. 2 shows a cross section of a prior art configuration that resembles the cross section shown in FIG. 1. The structure that is shown in cross section in FIG. 2 however addresses only and is limited to clock and signal distribution networks. FIG. 2 shows in addition (to the previously highlighted aspects of FIG. 1):

45 are two ESD circuits that are provided in or on the surface of the substrate 40; ESD circuits 45 are always required for any external connection to an input/output (I/O) pin 56

45′ which are circuits that can be receiver or driver or I/O circuits for input (receiver) or output (driver) or I/O purposes respectively

54 is a clock bus

56 is a clock or signal pin that has been extended through the layer 48 of passivation.

The same comments apply to the cross section that is shown in FIG. 2 as previously have been made with respect to FIG. 1, with as a summary statement that the layer 48 of passivation is the final layer that overlies the created structure, and the interconnect lines in layer 46 underneath the layer 48 of passivation are fine line interconnects and have all the electrical disadvantages of fine line interconnects such as high resistivity and high parasitic capacitance.

Further applies to the cross section that is shown in FIG. 2, where pins 56 are signal or clock pins:

pins 56 must be connected to ESD circuits 45 and driver/receiver or I/O circuits 45′

for signal or clock pins 56, these pins 56 must be connected not only to ESD circuits 45 but also to driver or receiver or I/O circuits, highlighted as circuits 45′ in FIG. 2

after (clock and signal) stimuli have passed through the ESD circuits 45 and driver/receiver or I/O circuits 45′, these stimuli are further routed using, under prior art methods, fine-line interconnect wires in layer 46. A layer 48 of passivation is deposited over the dielectric layer 46 in which the interconnect network has been created.

It is therefore of interest to the semiconductor art to provide a method of creating interconnect lines that removes typical limitations that are imposed on the interconnect wires, such as unwanted parasitic capacitances and high interconnect line resistivity.

SUMMARY OF THE INVENTION

A principal objective of the invention is to provide a method for the creation of interconnect metal that allows for the use of thick and wide metal.

Another objective of the invention is to provide a method for the creation of interconnect metal that uses the application of thick layer of dielectric such as polymer.

Yet another objective of the invention is to provide a method that allows for the creation of long interconnect lines, whereby these long interconnect lines do not have high resistance or introduce high parasitic capacitance.

A still further objective of the invention is to create interconnect lines that can carry high values of current for the creation of power and ground distribution networks.

A still further objective of the invention is to create interconnect metal that can be created using cost effective methods by creating the interconnect metal over a layer of passivation after the layer of passivation has been deposited.

In accordance with the objectives of the invention a new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric; a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross section of a silicon substrate over which a prior art fine-line interconnect network is created over which a layer of passivation is deposited; power and/or ground pins are provided through the layer of passivation for external connection. The structure that is shown in cross section in FIG. 1 addresses only and is limited to prior art power and ground distribution networks.

FIG. 2 is a cross section of a silicon substrate over which a prior art fine-line interconnect network is created over which a layer of passivation is deposited; clock and/or signal pins are provided through the layer of passivation for external connection. The structure that is shown in cross section in FIG. 2 addresses only and is limited to prior art clock and signal distribution networks.

FIG. 3a is a cross section of a silicon substrate over which an interconnect network is created according to the invention. Power and/or ground pins are provided through the layer of passivation for external connection. The structure that is shown in cross section in FIGS. 3a and 3b addresses only and is limited to power and ground distribution networks of the invention.

FIG. 3b shows power and ground distribution lines that are below a layer of passivation and power and ground distribution lines that are above a layer of passivation.

FIG. 4a is a cross section of a silicon substrate over which an interconnect network is created according to the invention. An ESD and/or driver and/or receiver circuit access pin is provided through the layer of dielectric for external connection. The structure that is shown in cross section in FIGS. 4a and 4b addresses only and is limited to clock and signal distribution networks of the invention.

FIG. 4b shows clock and signal distribution lines that are below a layer of passivation and clock and signal distribution lines that are above a layer of passivation.

FIG. 5a is a cross section of a silicon substrate over which an interconnect network is created according to the invention. No I/O connect pin is provided through the layer of dielectric for external connection. The structure that is shown in cross section in FIGS. 4a and 4b addresses only and is limited to clock and signal distribution networks of the invention.

FIG. 5b shows clock and signal distribution lines that are below a layer of passivation and clock and signal distribution lines that are above a layer of passivation.

FIG. 6 shows a cross section of the interconnection scheme of the referenced application invention.

FIG. 7a shows a cross section of a simplified version of the substrate and the layers that are created on the surface of the substrate under the processes of the referenced application.

FIG. 7b shows an inductor has been added above the layer of passivation.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

For purposes of reference and for clarity of understanding, FIG. 6 is taken from related U.S. application Ser. No. 09/251,183 and is herein incorporated by reference.

Referring now more specifically to FIG. 6, there is shown a cross section of one implementation of the referenced application. The surface of silicon substrate 10 has been provided with transistors and other devices (not shown in FIG. 6). The surface of substrate 10 is covered by a dielectric layer 12, layer 12 of dielectric is therefore deposited over the devices that have been provided in the surface of the substrate and over the substrate 10. Conductive interconnect lines 11 are provided inside layer 12 that connect to the semiconductor devices that have been provided in the surface of substrate 10.

Layers 14 (two examples are shown) represent all of the metal layers and dielectric layers that are typically created on top of the dielectric layer 12. Layers 14 that are shown in FIG. 6 may therefore contain multiple layers of dielectric or insulation and the like, conductive interconnect lines 13 made up of the network of electrical connections that are created throughout layers 14. Overlying and on the surface of layers 14 are points 16 of electrical contact. These points 16 of electrical contact can for instance be bond pads that establish the electrical interconnects to the transistors and other devices that have been provided in the surface of the substrate 10. These points of contact 16 are points of interconnect within the IC arrangement that need to be further connected to surrounding circuitry. A passivation layer 18, formed of for example silicon nitride, is deposited over the surface of layer 14 to protect underlying layers from moisture, contamination, etc.

The key steps of the above referenced application begin with the deposition of a thick layer 20 of polyimide that is deposited over the surface of layer 18. Access must be provided to points of electrical contact 16, for this reason a pattern of openings 22, 36 and 38 is etched through the polyimide layer 20 and the passivation layer 18. The pattern of openings 22, 36 and 38 aligns with the pattern of electrical contact points 16. Contact points 16 are, by means of the openings 22/36/38 that are created in the layer 20 of polyimide, electrically extended to the surface of layer 20.

The above referenced material that is used for the deposition of layer 20 is polyimide; the material that can be used for this layer is not limited to polyimide but can contain any of the known polymers (SiClxOy). The indicated polyimide is the preferred material to be used for the processes of the invention for the thick layer 20 of polymer. Examples of polymers that can be used are silicons, carbons, fluoride, chlorides, oxygens, silicone elastomer, parylene or teflon, polycarbonate (PC), polysterene (PS), polyoxide (PO), poly polooxide (PPO), benzocyclobutene (BCB).

Electrical contact contacting with the contact points 16 can now be established by filling the openings 22/36/38 with a conductive material. The top surfaces 24 of these metal conductors that are contained in openings 22/36/38 can now be used for connection of the IC to its environment, and for further integration into the surrounding electrical circuitry. The semiconductor devices that have been provided in the surface of substrate 10 can, via the conductive interconnects contained in openings 22/36/38, be further connected to surrounding components and circuitry. Interconnect pads 26 and 28 are formed on top of surfaces 24 of the metal interconnects contained in openings 22, 36 and 38. These pads 26 and 28 can be of any design in width and thickness to accommodate specific circuit design requirements. A pad 26 or 28 can, for instance, be used as a flip chip pad. Other pads 26 or 28 can be used for power distribution or as a ground or signal bus. The following connections can, for instance, be made to the pads shown in FIG. 6: pad 26 can serve as a flip chip pad, and pad 28 can serve as a flip chip pad or can be connected to electrical power or to electrical ground or to an electrical signal bus. Pad size and the standard rules and restrictions of electrical circuit design determine the electrical connections to which a given pad 26 or 28 lends itself.

The following comments relate to the size and the number of the contact points 16, as shown in FIG. 6. Because these contact points 16 are located on top of a thin dielectric (layer 14, FIG. 6) the pad size cannot be too large since a large pad size brings the circuits a large capacitance. In addition, a large pad size will interfere with the routing capability of that layer of metal. It is therefore preferred to keep the size of the pad 16 relatively small. The size of pad 16 is however also directly related with the aspect ratio of vias 22/36/38. An aspect ratio of about 5 is acceptable for the consideration of via etching and via filling. Based on these considerations, the size of the contact pad 16 can be in the order of 0.5 μm to 30 μm, the exact size being dependent on the thickness of layers 18 and 20.

For higher aspect ratio vias, the vias are filled with via plugs before the deposition of the metal layers 26 and 28. However, for vias that have lower aspect ratios (for example less than 2), the via plugs may not be needed in which case the metal of layers 26 and 28 can directly establish contact with the pads 16.

The referenced application does not impose a limitation on the number of contact pads that can be included in the design, this number is not only dependent on package design requirements but is mostly dependent on the internal circuit design requirements. Layer 18 in FIG. 6 can be a typical IC passivation layer.

The most frequently used passivation layer in the present state of the art is plasma enhanced CVD (PECVD) oxide and nitride. In creating layer 18 of passivation, a layer of approximately 0.5 μm PECVD oxide can be deposited first followed by a layer of approximately 0.7 μm nitride. Passivation layer 18 is very important because it protects the device wafer from moisture and foreign ion contamination. The positioning of this layer between the sub-micron process (of the integrated circuit) and the tens-micron process (of the interconnecting metallization structure) is of critical importance since it allows for a cheaper process that possibly has less stringent clean room requirements for the process of creating the interconnecting metallization structure.

Layer 20 is a thick polymer dielectric layer (for example polyimide) that has a thickness in excess of 2 μm (after curing). The range of the polymer thickness can vary from 2 μm to 150 μm, dependent on electrical design requirements.

For the deposition of layer 20 the Hitachi-Dupont polyimide HD 2732 or 2734 can, for example, be used. The polyimide layer 20 can be spin-on coated and cured. After spin-on coating, the polyimide layer 20 will be cured at 400 degrees C. for 1 hour in a vacuum or nitrogen ambient. For thicker polyimide film 20, the polyimide film 20 can be multiple coated and cured.

Another material that can be used to create layer 20 is the polymer benzocyclobutene (BCB). This polymer is at this time commercially produced by for instance Dow Chemical and has recently gained acceptance to be used instead of typical polyimide application.

The dimensions of openings 22, 36 and 38 have previously been discussed. The dimension of the opening together with the dielectric thickness determines the aspect ratio of the opening. The aspect ratio challenges the via etch process and the metal filling capability. This leads to a diameter for openings 22/36/38 in the range of from approximately 0.5 μm to 30 μm. The height for openings 22/36/38 can be in the range of approximately 2 μm to 150 μm. The aspect ratio of openings 22/36/38 is designed such that filling of the via with metal can be accomplished. The via can be filled with CVD metal such as CVD tungsten or CVD copper, with electro-less nickel, with a damascene metal filling process, with electroplating copper, etc. As previously stated, for low aspect ratio vias, the filling of the vias is not required as an extra processing step. A direct contact can be established between the metal layers 26 and 28 and the contact pads 16.

The referenced application can be further extended by applying multiple layers of polymer (such as polyimide) and can therefore be adapted to a larger variety of applications. The function of the structure that has been described in FIG. 6 can be further extended by depositing a second layer of polyimide on top of the previously deposited layer 20 and overlaying the pads 26 and 28. Selective etching and metal deposition or electro plating of metal can further create additional contact points on the surface of the second layer of polyimide that can be interconnected with pads 26 and 28. Additional layers of polyimide and the thereon created contact pads can be customized to a particular application; the indicated extension of multiple layers of polyimides greatly enhances the flexibility and usefulness of the referenced application.

FIG. 6 shows a basic design advantage of the referenced application. This advantage allows for the sub-micron or fine-lines that run in the immediate vicinity of the metal layers 14 and the contact points 16 to be extended in an upward direction 30 through metal interconnect in the opening 36; this extension continues in the direction 32 in the horizontal plane of the metal interconnect 28 and comes back down in the downward direction 34 through metal interconnect in the opening 38. The functions and constructs of the passivation layer 18 and the insulating layer 20 remain as previously highlighted. This basic design advantage of the invention is to “elevate” or “fan-out” the fine-line interconnects and to remove these interconnects from the micro and sub-micro level to a metal interconnect level that has considerably larger dimensions and that therefore has smaller resistance and capacitance and is easier and more cost effective to manufacture. This aspect of the referenced application does not include any aspect of pad re-distribution and therefore has an inherent quality of simplicity. It therefore further adds to the importance of the referenced application in that it makes micro and sub-micro wiring accessible at a wide and thick metal level. The interconnections in the openings 22, 36 and 38 interconnect the fine-level metal by going up through the passivation and polymer or polyimide dielectric layers 18 and 20, continuing through the wide and thick metal level on the polymer layer 20 for a distance, and continuing by descending from the wide and thick metal level back down to the fine-metal level by again passing down through the passivation and polymer or polyimide dielectric layers 18 and 20. The extensions that are in this manner accomplished can extend fine-metal interconnect points 16 of any particular type, such as signal point or power point or ground point, to wide and thick metal line 26 and 28. The laws of physics and electronics will impose limitations, if any, to the interconnect established in this manner, and the limiting factors will be the conventional electrical limiting factors of resistance, propagation delay, RC constants and others. What in the referenced application is of importance is that the referenced application provides much broader latitude in being able to apply these laws and provides a considerably extended scope of the application and use of Integrated Circuits and the adaptation of these circuits to a wide and thick metal environment.

This completes the discussion of the construct shown for purposes of reference in FIG. 6. Following will further be discussed the cross sections that are shown in FIGS. 7a and 7b.

FIG. 7a shows, for reasons of clarity, a simplified cross section of the substrate and the layers that are created on the surface of the substrate under the processes of the invention; the highlighted areas that are shown have previously been identified as:

10 the silicon substrate

12 is a layer of dielectric that has been deposited over the surface of the substrate 10

14 is an interconnect layer that contains interconnect lines, vias and contact points

16 are the contact points on the surface of the interconnect layer 14

18 is a layer of passivation into which openings have been created through which the contact points 16 can be accessed

20 is a thick layer of polymer, and

21 are the conductive plugs that have been provided through the layer 20 of polyimide.

The thick layer 20 of polymer can be coated in liquid form on the surface of the layer 18 of passivation or can be laminated over the surface of layer 18 of passivation by dry film application. Vias that are required for the creation of conductive plugs 21 can be defined by conventional processes of photolithography or can be created using laser (drill) technology.

It is clear from previous discussions that the structure of layers that is shown in cross section in FIG. 7a has been created so that additional electrical components such as an inductor, a capacitor and the like can be created on the surface of layer 20 of polyimide and in electrical contact with conductive plugs 21. Layer 12 of dielectric may, in the cross section that is shown in FIG. 7a, be part of layer 14 since layer 14 is a layer of Intra Level Dielectric (ILD) within which layer 12 can be readily integrated.

With respect to the cross section that is shown in FIG. 7b, the same layers that have been identified for FIG. 7a are again provided in this cross section. Additionally has been shown the upper layer 17 of the silicon substrate 10 that contains active semiconductor devices. Also shown is cross section of an inductor 19 that has been created on the surface of layer 18 of passivation. It must again be emphasized that the ohmic resistivity of the metal that is used for the inductor 19 must be as low as possible. For this reason, the use of a thick layer of metal, for instance gold, is preferred for the formation of inductor 19, and it has been shown that a thick layer of gold, increases the Q value of inductor 19 from about 5 to about 20 for 2.4 GHz applications, which represents a significant improvement in the Q value of inductor 19.

Referring now specifically to FIG. 3a, this figure refers only to power and ground pins and does not address signal or clock pins. There is shown in FIG. 3a a cross section of a silicon substrate 40 over which an interconnect network is created according to the invention, with a wide and thick wire interconnect network 66 created in a thick layer 64 of dielectric overlying a layer 62 of passivation. A power and/or ground pin 68 is provided through the thick layer 64 of dielectric for external connection. Following are the various features that are shown in FIG. 3a:

40 is the silicon substrate on the surface of which interconnect lines are created in accordance with the invention

42 are semiconductor circuits that are created in or on the surface of substrate 40

44 is an ESD circuit that is provided for the protection of circuits 42

58 is a layer in which connection pads are created to the semiconductor devices 42 that have been created in or on the surface of substrate 40

60 is a layer of dielectric in which fine-line interconnects have been created overlying the layer 58 in which the connection pads 58 are created to the semiconductor devices 42

61 is one of the vias that have been provided in layer 60; more such vias 61 are shown in FIG. 3a but are, for reasons of simplicity, not highlighted

62 is a layer of passivation that has been deposited overlying the layer 60 of dielectric in which fine-line interconnects are formed

63 is one of vias that passes through layer 62 of passivation; more such vias 63 are shown in FIG. 3a but are, for reasons of simplicity, not highlighted

64 is a layer of dielectric in which, as a post-passivation process, interconnects have been created

65 is a power or ground bus that is connected to the ESD circuit 44, originating in layer 64 and further passing through layers 62 and 60

66 is a power or ground bus providing power or ground (for multiple connection pads in layer 58)

67 is a via that is created overlying the layer 62 of passivation; more such vias 67 are shown in FIG. 3a but are, for reasons of simplicity, not highlighted

68 is a power or ground pin for the multiple semiconductor devices 42 in layer 58.

From the cross section that is shown in FIG. 3a, its is clear that, most importantly, the ability to create interconnects to semiconductor devices 42 that have been created in or on the surface of a substrate 40 has been extended by creating these interconnects not only as fine-line interconnects in layer 60 but extending the interconnect by creating a wide, thick wire interconnect network 66 overlying a layer 62 of passivation. This provides immediate and significant benefits in that the interconnect network 66 that is created overlying the layer 62 of passivation can now contain sturdier, that is thicker and wider, interconnect lines. The thick, wide metal interconnects 66 can be used for power and ground distribution, and this distribution 66 takes place above a layer 62 of passivation and partially replaces and extends the conventional method of having for these purposes a fine-line distribution interconnect network in layer 60 under the layer 62 of passivation.

Some points of interest can be listed at this time as they relate to prior art methods and to the invention.

Prior Art:

provides an ESD circuit for each pin that is used for external input/output interconnect

provides, after ESD stimuli have passed through the ESD circuits, a fine-line interconnect network for further distribution of the power and ground stimuli, and

the fine-line power and ground distribution network is created underneath a layer of passivation.

It must, in this respect and related to the above provided comments, be remembered that power and ground pins do not require drivers and/or receiver circuitry.

The Invention:

does not need to create an ESD circuit for each pin that is used for external input/output interconnect, in view of the more robust wiring that drives the ESD circuit, resulting in reduced power loss by an unexpected power surge over the interconnect line, resulting in more power being delivered to the ESD circuit, and

allows for the power and ground interconnects to be directly connected to the internal circuits of a semiconductor device, either without an ESD circuit or with a smaller than regular ESD circuit (as previously explained).

The method that is used to create the interconnect network that is shown in cross section in FIG. 3a addresses only the use of power and ground connections and does not apply to clock and signal interconnect lines. FIG. 3a can be summarized as follows: a silicon substrate 40 is provided in the surface of which have been created semiconductor devices 42 and at least one electrostatic discharge (ESD) circuit 44, a first layer 60 of dielectric is deposited over the substrate 40, and a fine-line interconnect network 61 is created in the first layer 60 of dielectric making contact with the active circuits 42 and the ESD circuit 44. A layer 62 of passivation is deposited over the surface of the first layer 60 of dielectric, and a pattern of metal plugs 63 is created in the layer 62 of passivation that aligns with points of contact created in the surface of the first layer 60 of dielectric. A second layer 64 of dielectric is deposited over the surface of the layer 62 of passivation, and a wide thick line interconnect network 66 is created in said the layer 64 of dielectric, connected to the ESD circuits 44. A point of electrical contact 68 comprising a power or ground contact is provided in the surface of said second layer 64 of dielectric. The ESD circuit 44 is connected, in parallel with the internal circuits 42, to an external connection point 68.

FIG. 3b provides further insight into the creation of the power and ground interconnect lines of the invention whereby these interconnect lines have been shown with interconnect lines 66 and interconnect lines 66′. Interconnect lines 66 have been created above the layer 62 of passivation and act as global power and ground interconnect lines. Interconnect lines 66′ have been created below the layer 62 of passivation and act as local power and ground interconnect lines.

Referring now to FIG. 4a, FIG. 4a addresses the interconnections of signal and clock line. In FIG. 4a there is shown a cross section of a silicon substrate 40 over which an interconnect network is created according to the invention. An access pin 70 to an ESD circuit 45 or driver circuits 45′ or receiver circuits 45′ or I/O circuits 45′ is provided through the surface of the layer 64 of dielectric for external connection. The ESD circuit 45 is required for all circuits 42 to which an I/O connection 70 is established, and the I/O interconnect 70 can also be provided to a receiver circuit 45′ or a driver circuit 45′ or an I/O circuit 45′.

The features not previously highlighted in FIGS. 3a and 3b but shown in FIG. 4a are:

the invention provides an interconnect network comprising wide, thick interconnect lines 72 for distribution of the clock and signal stimuli

the invention creates an interconnect network of thick, wide interconnect lines 72 for the clock and signal stimuli overlying a layer 62 of passivation,

70 is an external connection (pin) that is provided for the ESD circuit 45 and for driver/receiver/I/O circuit 45′, and pin 70 provides an external access for clock and signal stimuli to circuits 45 and 45′, and

72 is a clock or signal bus that is created in the dielectric layer 64 using thick, wide wires for interconnect lines; it must be noted that the clock and signal interconnect line distribution 72 is entirely contained within the layer 64 without providing an external point of I/O interconnect.

The method that is used to create the interconnect network that is shown in cross section in FIG. 4a can be summarized as follows. A silicon substrate 40 is provided, and active circuits 42, 45 and 45′ have been created in the surface of the substrate 40 including an ESD circuit 45, receiver 45′, driver 45′ and I/O circuit 45′. First layers 60 of dielectric of inorganic material are deposited over the substrate 40, and a fine-line interconnect network 61 is created in the layers 60 of dielectric, making contact with the active circuitry 42, 45 and 45′. A layer 62 of passivation is deposited over the first thin layers 60 of dielectric, a pattern of metal plugs 63 is created in the layer 62 of passivation, and the metal interconnects 63 align with points of electrical contact in the surface of the first layers 60 of dielectric. One or more thicker layers 64 of dielectric are deposited over the surface of the layer 62 of passivation, typically of an organic material, and a wide thick line interconnect network 72 is created in the thicker layer 64 of dielectric, making electrical contact with the metal plugs 63 or the metal pads of the fine-line interconnect network 61 in or under the layer 62 of passivation, and connected to the semiconductor devices 42 and receiver 45′, driver 45′ or I/O circuit 45′. A point 70 of electrical contact is provided in the surface of the second layer 64 of dielectric and connected to the ESD circuit 45, and receiver 45′, driver 45′ or I/O circuit 45′. The driver, receiver or I/O circuit 45′ is connected in series between the wide thick line interconnect network 72 and the external connection point 70. The ESD circuit 45 is connected, in parallel with the driver, receiver or I/O circuit 45′, to the external connection point 70.

FIG. 4b provides further insight into the creation of the signal and clock interconnect lines of the invention whereby these interconnect lines have been shown with interconnect lines 71 and interconnect lines 71′. Interconnect lines 71 have been created above the layer 62 of passivation and act as global signal and clock interconnect lines. Interconnect lines 71′ have been created below the layer 62 of passivation and act as local signal and clock interconnect lines.

FIG. 5a shows a cross section of a silicon substrate 40 over which an interconnect network is created according to the invention, with the interconnect network 74 created in a thick layer 64 of dielectric overlying a layer 62 of passivation. No ESD, receiver, driver or I/O circuit access pin is provided through the surface of the layer 64 of dielectric for external connection. Shown in FIG. 5a and not previously highlighted is the clock or signal interconnect line 74, providing for an interconnect scheme of thick, wide lines overlying a passivation layer 62 whereby no external I/O connections are provided. Due to the thick, wide lines of the interconnect network 74 that is created overlying a passivation layer 62, the clock and signal distribution 74 can take place entirely within the layer 64, as opposed to prior art methods where, for clock and signal distribution lines, each thick, wide interconnect line (where such thick, wide interconnect lines are used) must be provided with at least one I/O connect point for off-chip connection.

The method that is used to create the wide thick interconnect lines that is shown in cross section in FIG. 5a can be summarized as follows and is similar to that described above for FIG. 4a. A silicon substrate 40 is provided, and active devices 42 have been provided in the surface of the substrate 40. First thin layers 60 of dielectric are deposited over the surface of the substrate 40, and a fine-line interconnect network 61 is created in the first layers 60 of dielectric comprising fine-line interconnect lines, making contact with points of electrical contact of the active devices 42 in the surface of the substrate 42. A layer 62 of passivation is deposited over the surface of the first layers 60 of dielectric, and a pattern of conductive interconnects 63 is created in the layer 62 of passivation that aligns with the points of electrical contact of the fine-line interconnect network 61 in the surface of the first layer 60 of dielectric. One or more second layers 64 of dielectric are deposited over the surface of the layer 62 of passivation, the interconnect network 74 in the second layers 64 of dielectric making electrical contact with the conductive interconnects 63 in the layer 62 of passivation.

FIG. 5b provides further insight into the creation of the signal and clock interconnect lines of the invention whereby these interconnect lines have been shown with interconnect lines 74 and interconnect lines 74′. Interconnect lines 74 have been created above the layer 62 of passivation and can act as global signal and clock interconnect lines. Interconnect lines 74′ have been created below the layer 62 of passivation and act as local signal and clock interconnect lines.

It must further be emphasized that, where FIGS. 3-5 show a fine-line interconnect network in the layer 60 that underlies the layer 62 of passivation, the invention also enables and can be further extended with the complete elimination of the fine-line interconnect network in the layer 60, however, creating an interconnect network in the layer 64 that uses only thick, wide wires. For this application of the invention, the first layer of dielectric 60 is not applied, and the layer 62 of passivation is deposited directly over the surface of the created semiconductor devices 42 in or on the surface of substrate 40.

It is further of value to briefly discuss the above implemented and addressed distinction between fine-line interconnect lines and wide, thick interconnect lines. The following points apply in this respect:

the prior art fine line interconnect lines are created underneath a layer of passivation, the wide, thick interconnect lines of the invention are created above a layer of passivation

the fine-line interconnect lines are typically created in a layer of inorganic dielectric, the thick wide interconnect lines are typically created in a layer of dielectric comprising polymer. This is because an inorganic material cannot be deposited as a thick layer of dielectric because such a layer of dielectric would develop fissures and crack as a result

fine-line interconnect metal is typically created using methods of sputter with resist etching or of damascene processes using oxide etch with electroplating after which CMP is applied. Either one of these two approaches cannot create thick metal due to cost considerations or oxide cracking

thick, wide interconnect lines can be created by first sputtering a thin metal base layer, coating and patterning a thick layer of photoresist, applying a thick layer of metal by electroplating, removing the patterned thick layer of photoresist and performing metal base etching (of the sputtered thin metal base layer). This method allows for the creation of a pattern of very thick metal, and metal thickness in excess of 1 μm can in this manner be achieved while the thickness of the layer of dielectric in which the thick metal interconnect lines are created can be in excess of 2 μm.

Although the invention has been described and illustrated with reference to specific illustrative embodiments thereof, it is not intended that the invention be limited to those illustrative embodiments. Those skilled in the art will recognize that variations and modifications can be made without departing from the spirit of the invention. It is therefore intended to include within the invention all such variations and modifications which fall within the scope of the appended claims and equivalents thereof.