Intel wants ExaFLOPs performance by 2020

Aharon Etengoff, 20th June 2011

Intel VP Kirk Skaugen has outlined Santa Clara's vision of achieving ExaFLOP/s performance - a quintillion computer operations per second - by the end of this decade.

According to Skaugen, reaching exascale levels of performance will not only require the combined efforts of industry and governments, but also approaches being pioneered by Intel, such as Many Integrated Core (MIC) architecture.

"While Xeon processors are the clear architecture of choice for the current TOP500 list of supercomputers, Intel is further expanding its focus on high-performance computing by enabling the industry for the next frontier with our Many Integrated Core architecture for petascale and future exascale workloads," he explained.

"[We are] uniquely equipped with unparalleled manufacturing technologies, new architecture innovations and a familiar software programming environment that will bring us closer to this exciting exascale goal."

"Like the latter technology, Intel believes it can parlay the its manycore design into future exascale systems. Recycling the design from the aborted Larrabee graphics processor effort, MIC was recast as an high performance coprocessor for HPC," Feldman explained.

"This product redirection was unveiled in May 2010 during last year's ISC event. Since then Intel has been passing out MIC software development platforms (SDPs) to selected users in the HPC community, [which are] basically Knights Ferry coprocessor cards - the MIC prototype - with up to two GB of GDDR5 memory. The cards are [then] hooked up, via PCIe, to host systems with one or more Xeon CPUs."

With the tri-gate 22nm Knights Corner due to arrive in 2012, Feldman pointed out that performance-wise, MIC would have to be capable of hitting a rather "fast-moving target," as both Nvidia and AMD have significantly upped the FLOPS count for GPUs over the last few years.

"2012 will see the introduction of Nvidia's 'Kepler' GPU, an architecture that aims to triple the performance of the current generation Fermi parts," he said.

"Also, since Intel has not released any performance numbers for double precision floating point code, it remains to be seen how MIC will perform in this important realm."