Power Gating

May 24, 2015, anysilicon

Power Gating is the most effective low power design technique to save leakage power. With shrinking technologies, leakage power (standby power) is of growing concern to designers. Power gating involves the use of header and/or footer transistors which cut-off the connection of the circuit from the power supply and the ground respectively, thereby considerably reducing leakage power.

The biggest disadvantage of power gating is the time taken by the circuit to switch between the sleep and the on modes. As an enhancement to power gating, State Retention Power Gating (SRPG) is another technique to reduce leakage power while retaining the last state of the circuit.