In a previous email thread, we debated the merits of usinga single clock in each direction on the XGMII, versus using4 (frequency locked, but phase independent) clocks in each direction, with a clock dedicated to each of the four "lanes".

Without repeating the discussion, it is safe to summarize thatthe majority opinion (from among those who expressed an opinion)was to stay with one clock in each direction.

So, I would like to toss out another question for your consideration.

Should we use a two phase clock? Clock and ClockBar?

Some designers have suggested that this will make the ASIC andsystem timing more managable, because it is difficult to getsymetric drive strengths from the clock output buffers, andthe asymetry degrades the timing. With a two phase clock, youwould still have asymetry on the data signals, but at leastyou won't have to account for the asymetry on the clock.

At first blush, this seems like a modest addition. One more pinin each direction.