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Solution

"The ability of an agent to spread assertion of qualified signals over several clocks is referred to as "stepping". This notion allows an agent with "weak" output buffers to drive a set of signals to a valid state over several clocks (continuous stepping), thereby reducing the ground current load generated by each buffer. An alternative approach allows an agent with "strong" output buffers to drive a subset of them on each of several clock edges until they are all driven (discrete stepping), thereby reducing the number of signals that must be switched simultaneously. All agents must be able to handle address and data stepping while generating it is optional.

Either continuous or discrete stepping allows an agent to trade off performance for cost (fewer power/ground pins). When using the continuous stepping approach, care must be taken to avoid mutual coupling between critical control signals that must be sampled on each clock edge and the stepped signals that may be transitioning on a clock edge. Performance critical peripherals should apply this "permission" sparingly.

Stepping is only permitted on AD[31:0], AD[63:32], PAR, PAR64#, and IDSEL."

Xilinx address steps (pre-drive) for one cycle to extend the clock-to-valid time by one clock period. Xilinx does not address step (pre-drive) for any reason related to clock-to-data times. Please note the distinction, on the output side, there are two delay paths through the FPGA output buffers:

* clock to data (through output buffer "data" path)

* clock to valid (through output buffer "enable" path)

Xilinx is fully capable of achieving both the clock-to-data and clock-to-valid from the IOB flip-flops. However, for a non-address stepping design to work, you must register both the DATA and OE signal to use the OFD and TFD in the IOB.

Registering up to 72 enable flops in the IOB creates a problem very similar to the output clock enable situation in which Xilinx resorts to PCI_CE as a solution in many cases.

Consequently, to solve what is basically a timing problem, Xilinx uses address stepping. Xilinx steps the output enables, which are not registered in the IOB, but not the data, which is registered in the IOB. In some cases, the "value" on AD during the first cycle of address stepping is likely to be useless because Xilinx does not clock out the real address until the next cycle. Xilinx uses that time to "warm up" the drivers.

In PCI Spec 2.2, Xilinx used Address Stepping as defined above and, as a result, the Address Stepping bit in the cores command register was set to a 1.

Address stepping in 2.3 is defined as follows in section 3.6.3:

"Stepping is only permitted on IDSEL pins as a result of being driven by an AD signal through a series resistor. IDSEL is qualified by the combination of FRAME# and a decoded Type 0 configuration command. Output buffer technologies with a slow tri-state enable to AD and C/BE# active time are permitted to enable the AD and C/BE# buffers a clock cycle prior to the assertion of FRAME# for non-configuration transactions (these devices must still meet the Toff time of Table 4-6)."

The functionality of the Xilinx core has not changed in terms of address stepping; Xilinx is compliant to PCI Rev 2.3.