TSMC presses ahead with 40nm half node

Published Tuesday, March 25, 2008

TSMC has started the rollout of its 40nm ‘half-node’ process, about six months after shipping production wafers from its 45nm technology.

The foundry said the 40nm is a direct shrink of the 45nm process, reducing the dimensions and pitches by about 90 per cent, and comes in two forms: a low-power version, 40LP, and a general-purpose variant, 40G. The company claimed that the 40nm process offers a gate-density improvement of 2.35 times over chips made using the 65nm technology. The pitch of the first metal layer has been reduced to 126nm, said JC Huang, technical manager in the advanced process division at TSMC.

Huang claimed that active power consumption has been cut in the new process, thanks to reductions in bulk capacitance. Compared with the 45nm process, active power should be about 15 per cent lower.

TSMC said it now has the smallest SRAM cell size, measuring 0.242µm2. However, the company said at last year’s International Electron Device Meeting (IEDM) that it had managed to build SRAM cells as small as 0.202µm2. Huang said the size of the SRAM cell in customer designs would depend on their requirements for minimum supply voltage and yield expectations: smaller SRAM cells are expected to have lower yield because of the effects of statistical variability. To improve yield in high-speed memory arrays, TSMC is offering libraries with more robust eight-transistor cells as well as conventional six-transistor designs.

TSMC said some customers have run trials with portions of chip designs on the 40nm process and that multi-project wafer runs will begin next month.

TSMC is continuing to use immersion lithography for the 40nm process: the move to double exposure, which Intel has already applied with dry lithography at 45nm, is expected to come with the launch of the 32nm process late next year.

Image: An engineer examines a reticle used to draw on-chip features at one of TSMC's fabs