Hello. My name is Ken Chan, and welcome to this presentation, which will discuss the concepts of signal to noise ratio and noise spectral density in high-speed data converters. The first part of the presentation will go over the concept of signal to noise ratio, or SNR, by defining the meaning of SNR. A more detailed examination of the different components that make up the noise portion of SNR will be explored. This includes thermal noise, quantization noise, and jitter of the quantization clock. An example of a calculation of SNR that is dominated by jitter will be provided. The second part of the presentation will examine the concept of noise spectral density, or NSD, and describe how this is different from SNR. Finally, a design example will be presented, which will highlight how an NSD can be used to estimate the performance of the output of a DAC as it pertains to noise floor related performance specifications.
In real systems, signals are generally corrupted by noise, which results in a noisy signal. Simply stated, the signal to noise ratio, or SNR, is the signal power compared to the noise power in a given signal bandwidth. Typically, this is calculated by performing a fast Fourier transform, or FFT, and looking at the fundamental signal power and noise floor power in the frequency domain. The noise floor power is typically the integration of all of the noise within a given frequency bandwidth, excluding the fundamental signal and the harmonics of the fundamental. SNR is then simply the difference between the signal power and the integrated noise floor power. Since SNR is the difference between the signal power and the noise power, there are only two ways to increase the SNR. First, the signal power may be increased to a maximum of the full-scale range. Increasing the input signal strength above the full-scale range is not recommended and will adversely affect the performance of the ADC.
The second way to increase SNR is to decrease the noise power. Noise power is typically a result of a combination of quantization noise, noise caused by clock jitter, and noise caused by the ADC aperture jitter and circuit thermal noise. Reducing one or all of these noise sources may help to increase the SNR performance. Assuming that the signal power is kept constant at a fixed level, the SNR can be estimated by looking at the noise power contribution from each of the noise sources. Each of the noise power sources can be treated independently. The three different noise power sources are quantization noise, clock jitter noise, and thermal and transistor noise. Design choices such as ADC selection will include N bits of quantization noise, ADC aperture jitter, and the thermal noise of the ADC design.
Sampling clock choice will result in clock jitter noise, and the choice of the sampling rate of the ADC would generally dictate the bandwidth over which the noise is integrated. In general, this is usually the first Nyquist up to FS over 2. The quantization error can be calculated based on the theoretical quantization error, assuming a sine wave input. This is given by 6.02 dB per bit plus 1.76 dB. This determines the maximum possible SNR for N number of bits. In a real ADC, there are other limiting factors, such as sampling clock jitter, ADC aperture jitter, thermal noise, other system noise sources, the oversampling rate of the converter, and the application channel bandwidth.
There are generally three sources of circuit noise, shot noise, flicker, and thermal noise. Shot noise is caused by the P-N junction's DC bias current and is not constant. It generally has a white noise spectral profile. Flicker noise is caused by active circuits and electron carrier movements and generally has a 1 over F shape near-DC. Thermal noise is caused by the thermal excitation of the resistors and generally has a white noise distribution. Noise in an ADC is dominated by the track-and-hold circuit thermal noise contribution from the input resistor, Limiting the noise bandwidth to the RC bandwidth, The resulting thermal noise power is given by kT over C.
Clock jitter is defined as the random variation of the clock edge compared to its ideal point in time. Variations in this edge will cause the converter to sample the data at non-ideal points in time, resulting in an error which will contribute to the overall noise and impact SNR. The theoretical limit of SNR due to jitter is defined as the minus 20 log 2, pi, f, n times total jitter. Total jitter is the combined jitter from the clock source and the additional jitter caused by the internal ADC clock circuits, also referred to as aperture jitter. Clock jitter will cause incorrect samples of the input waveform and will be more prevalent with higher input frequencies. The SNR impact from jitter can be plotted alongside the SNR impact from the thermal noise. At the lower input frequencies, the thermal noise is dominant, while at the higher input frequencies, the noise caused by the jitter dominates. The resulting SNR can be thought of as the sum of the SNR impairments from jitter and thermal noise.
The plot on the right can be used to illustrate the greater impact that jitter has on higher frequency input signals. It is quite obvious that with lower frequency inputs, the possible error is much smaller than with higher input frequencies. As mentioned earlier, the total jitter is a combination of the sampling clock jitter and the aperture jitter. The clock jitter is the contribution from the external sampling clock source and can be measured on a phase noise analyzer. The aperture jitter is internal to the ADC clock circuits and cannot be measured by a phase noise analyzer. This is usually characterized by using very clean clocks and high-input frequencies to make an estimate of the total jitter based on the measured SNR. Then, using the measured external sampling clock phase noise, an estimate of the internal aperture jitter can be derived.
This is an example phase noise plot measured on a phase noise analyzer of a sampling clock running at 122.88 megahertz. The jitter is the integration of the phase noise from 10 kilohertz to 10 megahertz. In this case, the resulting jitter is 299 femtoseconds. A simple estimation can also be done for the jitter of a clock source if the phase noise plot is available. In the previous example, the integrated phase noise between 10 kilohertz and 10 megahertz is given as minus 75.72 dBc per hertz. With f clock equal to 122.88 megahertz, the equation yields a jitter of 299.77 femtoseconds.
Some considerations also need to be made for the traditional calculation of SNR based on the jitter and the input signal frequency. Previously, the theoretical limit of SNR due to jitter was defined as a function of the total jitter and the input frequency. However, this implies that the SNR would be the same for an input frequency regardless of the sampling rate. Then the question would be what advantage would oversampling have. Why not use undersampling for every application? It turns out that the SNR calculation has some dependence on the sampling clock frequency as well as the input frequency. By substituting the sampling clock jitter equation into the SNR equation, the result is two terms. One is based on the integrated phase noise, and the second is a term based on the oversampling of the input frequency by the sampling frequency. This correction term allows SNR to be improved if oversampling is used.
This is the more general equation for ADC SNR. This general equation is important because it gives a better estimate of the SNR performance of the ADC as compared to the traditional equation, which uses a simplified estimation of the impact of jitter on the SNR regardless of the sampling frequency or the input signal frequency. In most cases, the ADC clock is well filtered and will have better noise at larger frequency offsets. In some cases, the system requirements are often limited to a specific bandwidth, where you only care about the noise floor performance in a specific band. Using the traditional estimate for SNR would require a much more stringent noise spec and may not be achievable, or make the solution more complex and more expensive than it needs to be. Looking at the SNR performance at a specific frequency and over a specific bandwidth allows a more optimized system solution.
A simple experiment was performed to validate the general ADC SNR equation. A high-speed DAC was used to generate a clock with a known exaggerated level of noise around the clock frequency. This was used to drive the ADC sampling clock, and two different input signals were sent into the ADC. One tone was at 10 megahertz, and the other was 100 megahertz. The resulting signals captured by the ADC are overlaid and shown together. As expected, the sampling clock phase noise is coupled onto the input signals at 10 megahertz and 100 megahertz. The oversampling correction factor improves the phase noise at 10 megahertz by the oversampling ratio of 25 times, resulting in a 28 dB reduction in noise power. Also, at 100 megahertz, the oversampling is 2.5 times, resulting in a reduction in noise power of 8 dB.
The next section will discuss the concept of noise floor in the DAC output. Here, noise spectral density, or NSD, is the preferred specification versus SNR. The estimate of the SNR for DACs is the same as for ADCs. Similarly, the noise floor is made up of contributions from quantization, clock and aperture jitter, and thermal and transistor noise. The jitter limit for SNR is also treated the same way. For DACs, the NSD specification is generally more important than SNR. The shape of the NSD around the carrier must generally meet some transmission mask. Usually, when SNR is required, the system will often limit the bandwidth of the signal with a bandpass or low-pass filter. The noise floor can then be estimated within the pass band of the filter using the NSD. This is one of the main reasons most new data sheets are reporting NSD, bandwidth-limited versus SNR, first Nyquist.
In real systems, there is usually some tight filter around a band of interest, and all of the spectrum outside this band is filtered out. Instead of reporting the noise floor for the entire first Nyquist, it is more convenient to show the noise power per hertz and then estimate the noise floor within the pass-band frequencies of the filter. Let's consider a simple example where a DAC3484 is running at 1.2288 gigasamples per second and is generating a frequency of interest within the first 100 megahertz. Let's assume the NSD for the DAC3484 is at minus 160 dBc per hertz. If a low-pass filter with a frequency corner around FS over 2, or first Nyquist, is used and the noise floor is calculated for the entire first Nyquist, the resulting noise floor is minus 72.12 dBFS. However, if a low-pass filter is used with a corner frequency around 100 megahertz, then the noise floor within 100 megahertz is minus 80 dBFS. Fs By looking at the relevant noise floor only, the specification is better by approximately 8 dB.
The SNR of a DAC can be converted from the NSD specification. The NSD specification is the power of the 1-hertz bin. To convert this to SNR over a certain bandwidth, you can simply multiply this by the hertz bandwidth. For the case of the typical SNR, which is specified over Nyquist, or FS over 2, you would calculate the noise floor based on the NSD then adding 10 log FS over 2. This noise floor can then be subtracted from the fundamental signal power to give the SNR. For our real case of the DAC3484, the NSD is specified approximately minus 160 dBc per hertz. If the DAC was sampling at 1.25 gigasamples per second, then the noise floor is then calculated as minus 60 dBc per Hertz plus 10 log 1.25 gig divided by 2, or minus 160 dBc plus 88 dB, resulting in an SNR of 72 dBFS. Fs
In summary, the noise floor of ADCs and DACs can be specified in terms of SNR and NSD. Depending on the application, it may be better to use one or the other. It is best to keep in mind some of the important points about NSD and SNR when deciding which one to use. SNR estimates based on jitter are convenient estimates for SNR across the entire Nyquist band. However, these may be too pessimistic for bandwidth limited applications. SNR estimates based on an NSD measured at an offset frequency do not account for close-in phase noise, which could impact in-band measurements such as percent EVM. NSD is useful for out-of-band estimates such as noise-limited ACPR. Using the clock NSD curves and bandwidth-limited noise calculations along with the general equation for SNR would be the ideal solution for in-band and out-of-band estimates. Thank you for watching this presentation. 您好。 我是 Ken Chan， 歡迎您觀看此簡報， 我們將 探討高速 資料轉換器的 訊噪比和 雜訊頻譜密度 相關概念。 簡報的第一 部分會透過 定義訊噪比， 也就是 SNR 的意義， 來探討 SNR 相關概念。 接著會更 仔細探討構成 SNR 雜訊部分的 各種組成。 其中包含 熱雜訊、量化雜訊和 量化時脈抖動。 我們會提供 受抖動影響的 SNR 計算範例。 簡報的第二 部分會檢視 雜訊頻譜密度， 也就是 NSD 的概念， 並說明其與 SNR 有何不同。 最後我們會 提供設計範例， 由於其與 雜訊位準 相關性能 規格有關， 因此將會特別 說明如何運用 NSD 來估計 DAC 輸出性能。 在實際系統中， 訊號通常會 遭雜訊破壞，因而產生 有雜訊的訊號。 簡單地說， 訊噪比，或稱 SNR， 是在指定訊號 頻寬下訊號功率與 雜訊功率的比較結果。 計算方式 通常是執行快速傅立葉 轉換，又稱 FFT， 並觀察頻域中的 基本訊號功率與 雜訊底線功率結果。 雜訊底線 功率通常指在 指定頻寬 中，除了 基頻訊號 與基頻諧波 以外的所有 雜訊積分值。 SNR 是訊號 功率與雜訊 底線功率積分值 間的差異。 由於 SNR 是 訊號功率與 雜訊功率間的 差異，因此提升 SNR 只有兩種方式。 第一種方式是將 訊號功率提升至 最大全幅範圍。 我們不建議 將輸入訊號強度 增加到超過 全幅範圍， 會對 ADC 性能 造成負面影響。 第二種提升 SNR 的 方式是減少雜訊功率。 雜訊功率 通常是量化雜訊、 時脈抖動 造成的雜訊、 ADC 孔徑 抖動造成的 雜訊及電路熱雜訊的 組合結果。 熱雜訊.
減少其中 一個或全部 雜訊來源可幫助 提升 SNR 性能。 假設訊號 功率保持在 固定位準， 我們便可透過 每個雜訊 來源的雜訊功率 組成進行 SNR 評估。 每個雜訊功率來源 都可視為獨立。 這三種雜訊 功率來源為 量化雜訊、 時脈抖動雜訊 及熱與 電晶體雜訊。 選擇 ADC 等設計決定 會包含量化 雜訊的 N 位元、 ADC 擷取抖動及 ADC 設計的熱雜訊。 取樣時脈選擇 會造成時脈抖動雜訊， ADC 取樣率 選擇則 通常會 決定雜訊 結合的頻寬。 一般來說，通常是 第一個 Nyquist 區到 FS 除以 2。 在假設正弦波 輸入的情況下， 我們可依量化 誤差理論值 來計算量化誤差。 計算方式為每位元 6.02 dB 加上 1.76 dB。 此算式可判定 N 個位元數的 最大 SNR 值。 實際 ADC 中 還有其他限制 因素，例如取樣 時脈抖動、ADC 孔徑抖動、 熱雜訊、其他系統 雜訊來源、轉換器 超取樣率及 應用通道頻寬。 電路雜訊 來源通常 有三種：散射雜訊、 閃爍雜訊與熱雜訊。 散射雜訊是由 P-N 接面的 DC 偏壓電流所造成， 並且不會保持恆定。 通常具有 白雜訊頻譜。 閃爍雜訊是 由主動電路和 電子載波移動所造成， 通常會有 1/F 波形接近 DC。 熱雜訊則是由 電阻器熱激發 所造成，通常具有 白雜訊分布。 ADC 中的雜訊 受輸入電阻之 追蹤與保持電路 熱雜訊分布影響， 雜訊頻寬受限 於 RC 頻寬， 得到的熱雜訊 功率可以 kT/C 求得。 時脈抖動的定義為 時脈訊號緣 相較於其理想時間點的 隨機變化。 此訊號緣中的 變異會造成 轉換器在 非理想時間點下 進行資料取樣， 產生誤差進而影響 整體雜訊與 SNR。 因抖動所造成的 SNR 理論限制為 負 20 乘上 log 2 π f n 乘以總抖動。 總抖動是 時脈源抖動和 內部 ADC 時脈電路所造成的 額外抖動總和， 又可稱為孔徑抖動。 時脈抖動會 造成輸入波形 取樣錯誤， 在高輸入頻率下 更是常見。 我們可對抖動及 熱雜訊所帶來的 SNR 影響進行繪製。 熱雜訊在 低輸入頻率下 為主要雜訊， 而在高輸入頻率下， 主要雜訊則是 抖動所造成的雜訊。 我們可將 得到的 SNR 視為抖動和熱雜訊 所造成的 SNR 缺損總和。 右圖可 用來說明 抖動對高頻率 輸入訊號 所產生的較大影響。 很明顯在 低頻率輸入下， 可能誤差 比高輸入頻率 小很多。 如同先前所述， 總抖動 包含取樣 時脈抖動 和孔徑抖動。 時脈抖動是 來自外部 取樣時脈 來源的分布， 可透過相位雜訊 分析儀進行測量。 孔徑抖動只發生在 ADC 時脈電路內部， 無法透過相位雜訊 分析儀進行測量。 通常會利用 非常清楚的時脈 和高輸入頻率 來進行特性分析， 並根據 SNR 測量值 估計總抖動。 接著會利用 外部取樣時脈 相位雜訊測量值， 得到內部孔徑抖動的 估計值。 這是取樣時脈 以 122.88 MHz 執行時， 在相位雜訊 分析儀測量到的 相位雜訊圖範例。 抖動是從 10 kHz 到 10 MHz 的 相位雜訊積分值。 此例中得到的 抖動值為 299 飛秒。 若有相位 雜訊圖， 我們也可 執行簡單的 時脈源抖動估算。 在前一個範例中， 10 kHz 到 10 MHz 間 相位雜訊 積分值為每赫茲 負 75.72 dBc。 f 時派等於 122.88 MHz， 即可得到公式 結果為 299.77 飛秒。 以抖動和 輸入訊號頻率 進行 SNR 傳統計算時， 也需注意一些 其他考量。 先前提到 抖動造成的 SNR 理論限制為總抖動 與輸入頻率的函數。 頻率.
但這代表 不管取樣率 為何，輸入 頻率的 SNR 都會相同。 於是問題 變成超取樣的 優點究竟為何。 為何不在每個應用中 採用低取樣呢？ 原來 SNR 計算會因取樣 時脈頻率 與輸入頻率 略受影響。 若將取樣 時脈抖動公式 帶入 SNR 公式， 即可得到兩個部分。 一個與相位 雜訊積分值有關， 另一個 則以取樣頻率的 輸入頻率 超取樣為基礎。 若使用超取樣， 此修正項便能 改善 SNR。 這是較通用的 ADC SNR 公式。 此通用公式 非常重要， 因為與利用 抖動對 SNR 的影響， 而不考慮 取樣頻率或 輸入訊號頻率的 傳統公式簡化計算相比， 此公式可對 ADC SNR 性能 進行更精確的估算。 頻率.
在大多數情況下， ADC 時脈都會經過完整濾波， 在頻率偏移較大時 也會有較佳雜訊表現。 在部分情況下， 系統要求常會 限制在特定頻寬， 因此我們只會 注意特定頻寬下的 雜訊底線性能。 使用傳統 SNR 估算會需要 更嚴格的 雜訊規格， 這些規格有 可能無法達成， 或是會使解決方案的 複雜性與成本 超出所需程度。 觀察特定頻率 和特定頻寬下的 SNR 性能，可幫助得到 更具最佳化的系統 解決方案.
我們執行了一個 簡單的實驗， 來驗證 ADC SNR 的 通用公式。 我們利用高速 ADC，產生在 時脈頻率 附近雜訊 已知過大的時脈。 我們將其用來驅動 ADC 取樣時脈， 並有兩個不同 輸入訊號送入 ADC。 其中一個 音頻為 10 MHz， 另一個則是 100 MHz。 ADC 擷取到的 結果訊號會 重疊並一起顯示。 如同我們預期， 取樣時脈相位雜訊 在 10 MHz 和 100 MHz 下 會耦合在 輸入訊號上。 超取樣 修正係數 透過 25 倍 超取樣率 提升 10 MHz 的 相位雜訊， 使得雜訊 功率減少 28 dB。 而在 100 MHz， 超取樣 為 2.5 倍， 造成雜訊功率 減少 8 dB。 下一個部份我們會討論 DAC 輸出雜訊底線的 概念。 雜訊頻譜 密度又稱 NSD， 是偏好規格與 SNR 的關係。 DAC SNR 的估算值 與 ADC 相同。 同樣的， 雜訊底線是由 量化組成、 時脈與孔徑抖動， 以及熱與電阻器 雜訊構成。 SNR 抖動限制的 處理方式也相同。 對 DAC 而言， NSD 規格通常 會比 SNR 來得重要。 NSD 在載波 附近的波形 通常必須符合 某些傳輸遮罩。 通常在需要 SNR 的時候， 系統常會以 帶通或低通 濾波器限制 訊號頻寬。 接著便可在 濾波器的通帶中， 利用 NSD 估算雜訊底線。 這也是大多數 新產品說明書 會說明 NSD、有限頻寬與 SNR 關係、 第一個 Nyquist 區等資訊的主因之一。 在實際系統中， 想要觀測的頻段 附近通常會有 較嚴格的濾波器， 此頻段外的所有 頻譜都會經過濾波。 相較於回報 整個第一 Nyquist 區的 雜訊底線， 顯示每赫茲 雜訊功率後再計算 濾波器通帶 頻率的雜訊底線， 會是比較 方便的做法。 我們來思考 一個簡單的範例， 範例中 DAC3484 在 1.2288 GSPS 下執行， 並在前 100 MHz 中 產生所需頻率。 我們假設 DAC3484 的 NSD 為每赫茲負 160 dBc。 若採用 角頻率為 FS/2 或第一 Nyquist 區的低通濾波器， 便可計算整個 第一 Nyquist 區的 雜訊底線，得到的 雜訊底線為 負 72.12 dBFS。 但若採用 角頻率 約為 100 MHz 的 低通濾波器， 那麼在 100 MHz 內的 雜訊底線則是負 80 dBFS。 若只看相關 雜訊底線， 規格最好是 在 8 dB 左右。 DAC 的 SNR 可透過 NSD 規格 轉換得到。 NSD 規格是 1 赫茲 間隔的功率。 若要將此轉換成 特定頻寬 SNR， 只要乘上赫茲 頻寬即可得到。 若為 Nyquist 區 或 FS/2 的 傳統 SNR， 則可利用 NSD 的雜訊 底線， 再加上 10 log FS/2 進行計算。 接著可將基頻 訊號功率 減去雜訊底線， 得到 SNR。 以 DAC3484 實際範例來說， NSD 是在 每赫茲 負 160 dBc。 若 DAC 的取樣率 為 1.25 GSPS， 則可求得 雜訊底線為 每赫茲負 60 dBc 加上 10 log 1.25 GB 除以 2， 也就是負 160 dBc 加 88 dB， 得到的 SNR 為 72 dBFS。 Fs 總結來說， ADC 和 DAC 的 雜訊底線可透過 SNR 和 NSD 來求得。 您可視應用 來決定何者 比較適合。 決定使用 哪一個時，最好能 將 NSD 與 SNR 的 重點銘記在心。 以抖動為計算基礎的 SNR 是能夠方便 估算整個 Nyquist 頻段 SNR 的算法。 但對有限頻寬應用 而言可能會太過 悲觀。 以偏移頻率 測量到的 NSD 為基礎， 所求得之 SNR 估算值不考慮近載波相位雜訊， 可能會影響 EVM 百分比等頻內測量值。 EVM.
NSD 對有限 雜訊 ACPR 等 頻外測量非常有幫助。 運用時脈 NSD 曲線 和有限頻寬雜訊 計算，再搭配 SNR 通用公式， 會是頻內與 頻外測量的 理想解決方案。 感謝您收看 本簡報。

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Date:
July 28, 2017

This video is part of the TI Precision Labs – ADCs curriculum. The 1st part of the presentation will go over the concept of Signal to Noise Ratio or SNR, by defining the meaning of SNR. A more detailed examination of the different components that make up the noise portion of SNR will be explored. This includes thermal noise, quantization noise, and jitter of the quantization clock. An example of a calculation of SNR that is dominated by jitter will be provided.

The 2nd part of the presentation will examine the concept of Noise Spectral Density or NSD, and describe how this is different from SNR. Finally a design example will be presented which will highlight how NSD can be used to estimate the performance of the output of a DAC as it pertains to noise floor related performance specifications.