topic Re: HSWAPEN pin as user IO in Spartan® Family FPGAs (Archived)https://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/186214#M13964
<P>sutejmalaya,</P>
<P>&nbsp;</P>
<P>1. Please do not attach a new question or topic to an existing thread.&nbsp; Start a new thread!</P>
<P>&nbsp;</P>
<P>2. When posting a request for help, please include all the necessary and useful details.&nbsp; For example, you do not specify which FPGA family you are using!</P>
<P>&nbsp;</P>
<P>3.&nbsp; For each FPGA family, Xilinx provides a through and exhaustive Configuration User Guide.&nbsp; In each of the Configuration User Guides you will find descriptions of the behaviour of all FPGA pins for</P>
<P>&nbsp;</P>
<UL>
<LI>before configuration</LI>
<LI>during configuration</LI>
<LI>after configuration</LI>
</UL>
<P>For the Spartan-6 family, the Configuration User Guide is document UG380.</P>
<P>For Spartan-3/3a/3e/3an families, the Configuration User Guide is document UG332.</P>
<P>&nbsp;</P>
<P style="padding-left: 30px;"><EM><FONT color="#008000">Can we keep the PULLDOWN attribute to HSWAPEN during Configuration ??</FONT></EM></P>
<P>&nbsp;</P>
<P>4.&nbsp; The PULLDOWN attribute does not have any effect until after configuration is successfully completed.&nbsp; You must control the logic level of the HSWAPEN pin before and during configuration, either with external component(s) or with the provided internal weak pullup.</P>
<P>&nbsp;</P>
<P>If you have additional questions, I recommend you start a new thread.</P>
<P>&nbsp;</P>
<P>-- Bob Elkind</P>Tue, 25 Oct 2011 10:36:13 GMTeteam002011-10-25T10:36:13ZHSWAPEN pin as user IOhttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/123532#M9589
<P>Hi,</P>
<P>&nbsp;</P>
<P>I have a board with Spartan-6 mounted on it. <BR /><BR />I am using HSWAP pin as an User I/O. <BR /><BR />I forgot to put an external pull-down resitor on HSAWP pin, will it have any problem in configuring the FPGA ? <BR /><BR />please help me.</P>
<P>&nbsp;</P>Fri, 28 Jan 2011 18:51:20 GMThttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/123532#M9589jobsb2011-01-28T18:51:20ZRe: HSWAPEN pin as user IOhttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/123536#M9590
<P>j,</P>
<P>&nbsp;</P>
<P>Page 38:</P>
<P>&nbsp;</P>
<P><A href="http://www.xilinx.com/support/documentation/user_guides/ug380.pdf" target="_blank" rel="nofollow">http://www.xilinx.com/support/documentation/user_guides/ug380.pdf</A></P>
<P>&nbsp;</P>
<P>Tells you what the pin does.&nbsp; So, I ask you the question, does it matter to how you have wired your board if the IOs are pulled high with weak pullups, or if they are floating while the device configures?</P>
<P>&nbsp;</P>
<P>&nbsp;</P>Fri, 28 Jan 2011 18:56:53 GMThttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/123536#M9590austin2011-01-28T18:56:53ZRe: HSWAPEN pin as user IOhttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/123546#M9591
Fri, 28 Jan 2011 19:11:26 GMThttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/123546#M9591jobsb2011-01-28T19:11:26ZRe: HSWAPEN pin as user IOhttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/123548#M9592
<P>Austin,</P>
<P>&nbsp;</P>
<P>the hswapen is used as an IO for wiring the pci bus.</P>
<P>&nbsp;</P>Fri, 28 Jan 2011 19:14:31 GMThttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/123548#M9592jobsb2011-01-28T19:14:31ZRe: HSWAPEN pin as user IOhttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/123552#M9593
<P>j,</P>
<P>&nbsp;</P>
<P>So, if the pin is floating while the part is configured, how does that matter?</P>
<P><BR />If the pin is floating, it might be high, in which case all the other IO will be pulled high weakly, or it might be low, in which case all the other IO will be left floating.</P>
<P><BR />Consider both cases for all other IO, and for this pin,m consider it is floating:&nbsp; neither high, nor low.</P>
<P><BR />How will that affect the application?&nbsp; Once the part is configured, everything will be as you have programmed it to be, so this is only what happens, before DONE goes high.</P>
<P>&nbsp;</P>Fri, 28 Jan 2011 19:52:24 GMThttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/123552#M9593austin2011-01-28T19:52:24ZRe: HSWAPEN pin as user IOhttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/123610#M9596
<P>Austin,</P>
<P>&nbsp;</P>
<P>In simple words, that means the fpga will be configured without any issues.</P>
<P>am i right?</P>
<P>&nbsp;</P>Sat, 29 Jan 2011 03:34:47 GMThttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/123610#M9596jobsb2011-01-29T03:34:47ZRe: HSWAPEN pin as user IOhttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/123616#M9597
<BLOCKQUOTE>
<P><EM><FONT color="#008000">Austin, In simple words, that means the fpga will be configured without any issues. am i right?</FONT></EM></P>
</BLOCKQUOTE>
<P>I hope Austin will forgive me for this kibitz...</P>
<P>&nbsp;</P>
<P>J,&nbsp; What Austin is saying is</P>
<P>&nbsp;</P>
<UL>
<LI>the input level of the <STRONG><FONT face="courier new,courier" color="#0000ff">HSWAPEN </FONT></STRONG>pin will not, by itself, prevent successful FPGA configuration.</LI>
</UL>
<UL>
<LI>the indeterminate state of the <STRONG><FONT face="courier new,courier" color="#0000ff">HSWAPEN</FONT></STRONG> pin <EM>may </EM>affect <EM>other circuitry </EM>on the board, and this <EM><STRONG>may </STRONG></EM>interfere with successful configuration.&nbsp; As the board designer, it is up to you to chase down these possibilities and rule them out as potential problems, one by one.</LI>
</UL>
<P><FONT color="#800080"><STRONG>If</STRONG></FONT> your FPGA configures unreliably, that <FONT color="#800080"><STRONG>might</STRONG></FONT> be the result of indirect interference which <STRONG><FONT color="#800080">migh</FONT></STRONG>t be attributable to the HSWAPEN pin use.&nbsp; This assertion involves at least three "<STRONG><FONT color="#800080">might</FONT></STRONG>" and "<STRONG><FONT color="#800080">if</FONT></STRONG>" conditions.</P>
<P>&nbsp;</P>
<P>- Bob Elkind</P>Sat, 29 Jan 2011 04:40:06 GMThttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/123616#M9597eteam002011-01-29T04:40:06ZRe: HSWAPEN pin as user IOhttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/123966#M9623
<P>Bob,</P>
<P><BR />Your help is greatly appreciated.&nbsp; Anytime.</P>
<P>&nbsp;</P>
<P>&nbsp;</P>Mon, 31 Jan 2011 15:23:09 GMThttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/123966#M9623austin2011-01-31T15:23:09ZRe: HSWAPEN pin as user IOhttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/124042#M9625
<P>Austin, Bob,</P>
<P>&nbsp;</P>
<P>Thanks.</P>
<P>On Page 39 of Ug380.pdf, the HSWAPEN pin is INPUT before configuration and is an IO only after configuration.</P>
<P>Does this really matter?</P>
<P>What if it is used as an output? </P>
<P>&nbsp;</P>
<P>&nbsp;</P>Mon, 31 Jan 2011 18:48:30 GMThttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/124042#M9625jobsb2011-01-31T18:48:30ZRe: HSWAPEN pin as user IOhttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/124046#M9626
<P>j,</P>
<P>&nbsp;</P>
<P>If you want to use it as an output, be sure to pull it high, or low, with a large enough resistor, so that when it becomes an output, you are not driving a low resistance to Vcco, or to ground.&nbsp; Best practice is not to leave it floating, but to assert it (waekly) with a resistor just small enough to guarantee&nbsp; a low, or a high.</P>
<P>&nbsp;</P>
<P>The worst case leakage on any IO pin is + or - 10uA.&nbsp; So, for example, I would like to supply 10 uA with less than a .1v voltage drop, I get .1/20uA, or about 10 Kohms.<EM>&nbsp;</EM>&nbsp; Now 10 Kohms is a very small load for even the weakest output driver (2mA), so it can be ignored after configuration.</P>
<P>&nbsp;</P>
<P>&nbsp;</P>
<P>&nbsp;</P>
<P>&nbsp;</P>Mon, 31 Jan 2011 18:55:39 GMThttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/124046#M9626austin2011-01-31T18:55:39ZRe: HSWAPEN pin as user IOhttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/124048#M9627
<P>Austin,</P>
<P>&nbsp;</P>
<P>The pin has been used as an IO (in this case as an output). There is no provision now to pull it high or low through resistor. </P>
<P>&nbsp;</P>Mon, 31 Jan 2011 18:58:10 GMThttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/124048#M9627jobsb2011-01-31T18:58:10ZRe: HSWAPEN pin as user IOhttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/124066#M9629
<BLOCKQUOTE>
<P><EM><FONT color="#008000">The pin has been used as an IO (in this case as an output). There is no provision now to pull it high or low through resistor.</FONT></EM></P>
</BLOCKQUOTE>
<P>In response to your original post --</P>
<BLOCKQUOTE>
<P><EM><FONT color="#008000">I forgot to put an external pull-down resitor on HSAWP pin, will it have any problem in configuring the FPGA ?</FONT></EM></P>
</BLOCKQUOTE>
<P>The answer is still <FONT color="#0000ff"><STRONG><EM>maybe yes, maybe no, depending on what else is "happening" on the board.</EM></STRONG></FONT></P>
<P>&nbsp;</P>
<P>Are you seeing any odd or inconsistent behaviour with respect to FPGA configuration?&nbsp; If yes, then it would be a good idea to dig a bit deeper.</P>
<P>&nbsp;</P>
<P>- Bob Elkind</P>Mon, 31 Jan 2011 20:32:32 GMThttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/124066#M9629eteam002011-01-31T20:32:32ZRe: HSWAPEN pin as user IOhttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/186188#M13963
Hello Austin,<BR /><BR /> <BR /><BR />I am new to schematic design and i missed a pulldown on HSWAPEN. Now i am using it as an normal IO<BR /><BR /> <BR /><BR />Can we keep the PULLDOWN attribute to HSWAPEN during Configuration ??<BR />Tue, 25 Oct 2011 09:25:00 GMThttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/186188#M13963sutejmalaya2011-10-25T09:25:00ZRe: HSWAPEN pin as user IOhttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/186214#M13964
<P>sutejmalaya,</P>
<P>&nbsp;</P>
<P>1. Please do not attach a new question or topic to an existing thread.&nbsp; Start a new thread!</P>
<P>&nbsp;</P>
<P>2. When posting a request for help, please include all the necessary and useful details.&nbsp; For example, you do not specify which FPGA family you are using!</P>
<P>&nbsp;</P>
<P>3.&nbsp; For each FPGA family, Xilinx provides a through and exhaustive Configuration User Guide.&nbsp; In each of the Configuration User Guides you will find descriptions of the behaviour of all FPGA pins for</P>
<P>&nbsp;</P>
<UL>
<LI>before configuration</LI>
<LI>during configuration</LI>
<LI>after configuration</LI>
</UL>
<P>For the Spartan-6 family, the Configuration User Guide is document UG380.</P>
<P>For Spartan-3/3a/3e/3an families, the Configuration User Guide is document UG332.</P>
<P>&nbsp;</P>
<P style="padding-left: 30px;"><EM><FONT color="#008000">Can we keep the PULLDOWN attribute to HSWAPEN during Configuration ??</FONT></EM></P>
<P>&nbsp;</P>
<P>4.&nbsp; The PULLDOWN attribute does not have any effect until after configuration is successfully completed.&nbsp; You must control the logic level of the HSWAPEN pin before and during configuration, either with external component(s) or with the provided internal weak pullup.</P>
<P>&nbsp;</P>
<P>If you have additional questions, I recommend you start a new thread.</P>
<P>&nbsp;</P>
<P>-- Bob Elkind</P>Tue, 25 Oct 2011 10:36:13 GMThttps://forums.xilinx.com/t5/Spartan-Family-FPGAs-Archived/HSWAPEN-pin-as-user-IO/m-p/186214#M13964eteam002011-10-25T10:36:13Z