The above will simulate the accesses contained in the file “example_access_stream” on a 8KB cache with 16B line size.
This will use a direct mapped cache (ways = 1), the replacement policy will be ignored, use no prefetching, and will
save the results to “results.csv”.

Lower misses does not necessarily mean better performance. Higher line sizes make each miss cost more cycles.
For a better estimate of performance, the simulator estimates the total fetch cycles.

The estimated fetch cycles is an estimate of how many cycles are used to fetch data from memory as a result of all the misses.
This is an estimate, based on the rough estimate of 25 cycles per fetch for a 16B line size. Knowing this,
we can estimate the cycle counts for other line sizes using the fact that loading each additional word takes an additional
2 cycles.

For the DE4 DDR2 ram, each additional word takes 1 word and the default fetch cycles are lower.
Tweak the #defines at the top of cache_sim.cpp as needed for more accurate estimates

## GETTING THE ACCESS STREAM ##

To get the access stream, you need to modify the tiger processor to print out the accessed addresses. To do this, do the following: