Rating Vote:

Latching Push-Button Initial State

02/24/2017 5:14 AM

Dear Engineers,

I've nicked this neat design for a power-switch of the web. It works as expected with the exception of the initial state. Connecting the 0.1uF capacitor to the power rail should keep the output low, when power is first applied, but it does not. Any suggestions?

Re: Latching Push-Button Initial State

02/25/2017 12:06 AM

I see a discharge path through the 100k resistor, but I fail to see the point of that capacitor at all. If it were to be connected to ground rather than the +ve rail, then it would switch the PMOS on immediately, but I don't see how it holds it off as shown.

I would have expected that the 100k resistor was sufficient to hold Vgs at rail volts and therefore off. Perhaps a voltage divider between -ve/gate/+ve with highest resistance at -ve side might work.

It appears that once energised, the press button would need to be held down until the 10 mic capacitor discharged below threshold for the NMOS to turn off thus allowing the PMOS Vgs to rise to source volts and turn the load off.

Re: Latching Push-Button Initial State

03/08/2017 5:10 AM

Thanks to everyone for the help!

@ 67model: you're right about the load, it was shown incorrectly connected to the anode, instead of the negative terminal. I've corrected the schematic and made a simulation in LTSpice to confirm (wrong FETs, I know):

still @ 67model: I hear you with regards to using a mechanical switch, but do you have any reference designs/part nr. I can see? From what I saw, the relays are pretty big and the circuits controlling them (to get PUSH/HOLD --> ON/OFF functionality) are just as complicated as the one above.

After simulation, I've simply re-made the circuit in a fresh board and that seem to help. The voltage on the load now behaves as expected, with a couple of exceptions:

a) The button hold time is still relatively long (about 7 seconds) even with the capacitance reduced to 4.7uF. Its 10uF in the original design and they claim i takes only 3 second to discharge it.

b) The button needs to be released to drop the load voltage. It would me much more convenient, if the voltage dropped while the button is held. Otherwise one doesn't know, when the button can actually be released!

Re: Latching Push-Button Initial State

Re: Latching Push-Button Initial State

03/08/2017 1:22 PM

I notice ,on your PCB, that capacitors look like tantalum electrolytic. Leakage is significant, e.g. AVX list 0.8 microamp for 4mm7 16V @ 25 'C, compared to about 1.5 microamp charging current when it gets near 11V in your circuit. This will slow down the the last volt or two of the charge. Plus, I think you will find that the leakage data is "out of the box" and there will be an increase when you solder it in, maybe 100%.

Add in - to drop gate volts of + side FET to 1 volt means drain current of RSR020N06 must fall to 10 microamp (R1 is 100k), not 1 mA.

- the 1N4148 diode will drop about 0.5 volt, which means, at the tail-end R4 has just 0.5V across it, not 1 volt.

So you are set-up for a time constant much longer than "RC". I can believe 7 sec - I suggest you use yr modelling software to measure + side FET gate-source volts.

b) As I see it, if you hold button long enough -ve side FET will turn off, feedback of 4mm7 cap will give positive feed back to turn off both FET quick - no letting go of button. But real world has AC pickup volts on your finger.

Re: Latching Push-Button Initial State

03/10/2017 10:33 AM

Interesting, it seems if the input voltage is 8.4V (from the battery) the output voltage drops without having to release the button. But if it's powered by 12V (from the AC power supply), button has to be released first (I can hold the button forever and it will not go down)! Why do you think that is?

Also @67model, what capacitors should I use to reduce leakage current?

Re: Latching Push-Button Initial State

03/10/2017 1:29 PM

Releasing the button does give a pulse, via C5, to turn off + side FET.

On the effect of supply voltage, the gate-source leakage of high current, low on resistance FETs is high, the data sheet for that *020* type is 10 microamp max @ 20V, 25'C and increases much with high temperature.

A better capacitor may not make circuit work reliably therefore. I suggest you measure voltage gate-source on + side FET as check on "- side" FET source-drain current - 100k resistor drops 1V @ 10 microamp. You can use resistor & rotary pot from supply, to vary gate voltage of -side FET & see how its drain current is affected.

Also, as mentioned by other, a schottky diode will have a lower volt drop than 1N4148,reducing gate-source voltage of -side FET.

There is much less leakage with plastic film capacitors, but values like 4mm7 are extreme, bulky & costly. PET film are readily available, polystyrene has about lowest leakage but much bigger & impractical.

I suggest you just reduce the capacitance of the 4mm7 to give a shorter & more convenient time, which will also reduce leakage. Higher voltage Tantalum cap will also give lower leakage.

I suggest you connect your caps to supply via voltmeter [DVM usually 1 meg resistance, which means 1 volt per microamp, you can shunt meter with 111k to get 10 microamp full-scale] and find out leakage for yourself. Always best to find out for yourself what really happens, then you really know. You will, of course, get a charging curve, so it may take minutes for current to tail off.

Re: Latching Push-Button Initial State

03/10/2017 1:40 PM

The leakage current of capacitors does fall with voltage, so 8.4 volts may drop C3 leakage enough for circuit to work as claimed. As I suggested, find out yourself, by using pot from supply to vary voltage on capacitor while measuring current with DVM.