When do transmit FIFO data and receive FIFO data register reset?

Question:

When are the transmit FIFO data register (SCFTDR) and receive FIFO data register (SCFRDR) reset, in case the TFRST bit and RFRST bit in the FIFO control register (SCFCR) are set to 1 in the serial communication interface with FIFO (SCIF)?

Answer:

The transmit FIFO data register (SCFTDR) and receive FIFO data register (SCFRDR) are reset when the FRST bit and RFRST bit are set to 1. The reset operation is retained while the TFRST bit and RFRST bit are 1.