We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Firefox,
Internet Explorer 11,
Safari. Thank you!

AR# 35579

Description

When I add an ATC2 core to my design with "State" mode enabled I see a fatal error in Map.

FATAL_ERROR:Pack:pks3eiobregrules.c:973:1.16 - The dual data rate register symbol "test3_timing/U0/I_SMODEC.U_ATC/u_atp_iob/i_state.i_tdm1x.U_CLK_ODDR/i_s3.u_o ddr/test3_timing/U0/I_SMODEC.U_ATC/u_atp_iob/i_state.i_tdm1x.U_CLK_ODDR/i_s3. u_oddr/ODDR2.C0D1" has no input signal. Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.

How do I work around this issue?

Solution

To work around this issue, you must use "Timing" mode when generating the core.