The modern SoC is designed with many modular IP blocks that have been commercially licensed or reused from previous designs, along with some new proprietary components. Integrating all of the components has typically proven to be time-consuming and error-prone as designers stitch their SoCs together by hand or rigid and outdated scripts. Challenges also exist in the form of highly configurable IP blocks such as the interconnect fabric and debug & trace subsystem.

The Socrates™ Design Environment (DE) is a complete tooling solution that handles the configuration and integration of ARM-based SoCs quickly and efficiently. It is through tooling that IP blocks can become greater than the sum of their parts, optimized for performance across the entire system.

Socrates tooling works together seamlessly to deliver an intelligent system design flow

]]>http://www10.edacafe.com/blogs/corevalues/2015/06/03/system-assembly-through-intelligent-configuration/feed/072From months to days: an IP integration innovation at 52DAChttp://www10.edacafe.com/blogs/corevalues/2015/05/26/64/
http://www10.edacafe.com/blogs/corevalues/2015/05/26/64/#respondTue, 26 May 2015 10:10:37 +0000http://www10.edacafe.com/blogs/corevalues/?p=64Some innovations give such an exponential productivity shift that they are often only appreciated when viewed with the perspective of history. Isambard Kingdom Brunel built the first train line from London to Bristol and cut down the travel times from days to hours. In doing so he actually moved time itself; at the time Bristol was 30 minutes behind London. Clocks in the 19th century were based off sunrise and sunset in each location as it was never necessary to be so precise when travel between two places meant a much longer journey. However the real benefit he provided was literally giving time to people, by shortening the travel time it enabled people to dedicate time to solving other problems. The spread of train tracks across the UK and the rest of the world enabled the rapid development of the Industrial Revolution that provided the foundation for the modern world. There is a fantastic documentary on Isambard Brunel on YouTube for those who wish to find out more.

The Clifton suspension bridge in Bristol. A revolutionary construct in 1864 that dramatically cut travel times between London and Bristol

The narrative of saving time on one task to allow a person focus on other issues is incredibly apt when referring to tools that help with SoC development. Ever since the birth of the EDA movement in the 1980’s, tools have played a key role in automating tasks and freeing up time to work on more important design decisions.

When you look at the way SoCs and subsystems are put together currently, it consists of manually stitching using RTL. Nowadays, for example, an ARM® CoreSight™ debug and trace subsystem will consist of thousands of connections, hundreds of registers and hundreds of interface ports. That all adds up to a highly complex bit of IP. Trying to stitch this together in a way that gets the most out of the system, knowing where the interfaces are and what they need to do, requires true experts that have intimate knowledge of how the architecture works. Even for someone with vast experience it is still a time-consuming, error-prone process that requires constant reference to TRMs. Let’s face it: everybody has something better to be doing than looking at TRMs. Add into that the fact that designers are using IP from different sources which may not all be on the same standard; some in RTL and some in IP-XACT. Today it takes months to properly build a functional subsystem.

As the premier design automation conference, DAC is instrumental in showcasing technology that brings huge improvements to SoC development. This year at DAC52 ARM will unveil new technologies that will transform the way complex debug subsystems and entire SoCs are configured and integrated. Similar to Brunel’s breakthrough 150 years ago, it will reduce the time scale required from months to days and enable system architects to focus their attention on delivering performance improvements through system optimization instead of toiling away at manual stitching. In a previous conversation with ARM IP Tooling Architect David Murray, he gave away a few hints into how this productivity shift will be achieved,

“What we’re trying to do here is use the metadata to give a fast, correct configuration in a system context. What I mean by system context is that you can see how different system requirements have a knock-on effect on the configuration of each IP and the system as a whole. What that allows us to do is reduce the time that’s spent on actually integrating the parts into a system because 90% of that work will have been done through intelligent configuration. In order to realize our ‘System in a Day’ vision for IP integration we need to do it through intelligent configuration. You need to have a solution for these complex IP blocks so that they can reconfigure themselves as the system is being defined”.

This level of fast configuration that can show the system implications in real time is a revolutionary step forward in terms of SoC development. Its true value may only be seen in a few years when users of the technology have squeezed even more performance out of SoCs with the time that has been freed up for them. Find out more about ARM’s commitment to simplifying the process of system integration at Booth #2428 at 52DAC.