EXTRACTED TIMING MODEL (ETM)

ETMs are used extensively in modern SoC designs to speed up the turn-around time of timing analysis. By abstracting away, the contents of the block, analysis time is dramatically reduced. This allows designers an accurate view of full-chip timing without the excessive run times associated with flat analysis.

However, using ETMs requires several steps. Step one, the designer needs to verify the results matching the netlist and SDC. Step two, generate a new full-chip SDC with the block(s) replaced with ETM models. Step three, verify the ETM-based full-chip SDC file matches the flat view. With Timevision ETM these steps are performed automatically, allowing the use of ETM-based timing flows without the manual effort necessary to support them.

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Dr. Sam Appleton

President & CEO

As a CEO and co-founder of Ausdia, Sam has been a driving force in the product
planning,
product development and market analysis for Timevision, the company’s flagship
platform.
Prior to Ausdia, he held technical lead roles at Azul Systems, where he managed the
implementation & physical methodology for three generations of custom SMP
processors,
from 500 to 900Mhz and 1.2B transistors. Prior to Azul systems Sam held a variety of
technical management positions at Reshape, Cosine Communications and Silicon
Graphics.

Sam received a Ph.D. in Electronic Engineering from the University of Adelaide,
South
Australia focused on high-performance asynchronous circuit & logic design and has
personally been involved in more than 20 tape-outs from 1um to 28nm.