The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.

A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.

"The InFO design flow is an example of another important collaboration between Cadence and TSMC that our customers appreciate and benefit from," said Steve Durrill, senior product engineering group director at Cadence. "We are continuing to work together to develop the seamlessly integrated implementation and signoff InFO solution so designers can meet increasingly tight market windows as they target TSMC's most advanced manufacturing processes."

"The current InFO advanced wafer-level packaging technology provides cost-effective system scaling to increase system bandwidth," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "We are working closely with Cadence to provide additional benefits to our joint customers with faster design turnaround time due to the smooth integration of signoff analysis tools."

About Cadence

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at www.cadence.com.