tag: constraints

Xiaolin Chen, senior AE at Synopsys, looks at what’s good enough coverage, what makes one assertion better than another, and where the potential holes are in verification.
https://youtu.be/nBtKE0gDHBU » read more

For the past three years, Oski Technology has facilitated a gathering of formal verification experts over dinner to discuss the problems and issues that they face. They discuss techniques they have been attempting with formal verification technologies, along with the results they have been achieving.
Semiconductor Engineering was there to record that conversation and to condense it into the ... » read more

This white paper addresses the specific need for designing constraints into your NI PXIe-6591R or PXIe-6592R High Speed Serial project. Constraints are an often overlooked requirement of the project and can take several weeks to analyze timing requirements on a design, implement constraints, and achieving successful compilations that pass timing. This guide will help reduce the amount of time s... » read more

Preparing articles for Semiconductor Engineering involves talking to a lot of people and then trying to fit their statements together in a way that is logical and fair. Sometimes a subject will come up in one of these calls that is not really on topic, but is still interesting. One such incident happened this week while doing research for the Verification 3.0 article.
The topic was constrain... » read more

Naturally, Accellera’s Portable Stimulus Standard (PSS) supports the powerful capabilities of advanced verification techniques that are well-known in the industry today, including object-oriented composition and constrained-random stimulus. But the PSS also supports a new constraint capability, called dynamic constraints.
Dynamic constraints support the critical mission of the PSS by makin... » read more

Over the past few years, lots of energy has been invested in improving the productivity and quality-of-results of design verification. A promising effort toward this end is that both commercial and in-house tools have been developed to improve the productivity and efficiency of verification at the block, subsystem, and system levels. These tools raise the level of abstraction, increase test-gen... » read more

The first release of the Portable Stimulus (PS) standard is slated for early next year. If it lives up to its promise, it could be the first new language and abstraction for verification in two decades.
[getentity id="22028" e_name="Accellera"] uncorked the PS Early Adopter release at the Design Automation Conference (DAC) in June. The standard has been more than two years in the making by t... » read more

A few months back, OneSpin asked engineers to solve the classic Einstein’s Riddle using a formal tool. The challenge became hugely popular, and we received many outstanding solutions. To check out the riddle itself and the top 10 solutions created by leading engineers, click here.
In this blog, we take another look at the riddle, review the best solutions and announce the winners.
We ha... » read more

It has been suggested that formal might replace simulation, at least in some parts of the design flow. Not likely! The question is, how can formal be layered on top of simulation flows to improve coverage and schedule?
The way formal is being used at the larger semiconductor companies is evolving. In many of these companies a small team of hardcore formal experts are employed across differen... » read more

Power scheduling, power integrity targets, voltage drop—these are just a few of the power-related challenges you’re no doubt managing in your SoC designs. There aren’t any easy answers, but there are some emerging—and promising—techniques.
Two such techniques, according to University of Toronto Professor Farid Najm, are constraints generation and constraints-based verification. “... » read more