AMD, Intel at it again, as both take aim at SoC

Advanced Micro Devices and Intel are ramping up system- on-chip capabilities, creating new prod- ucts and processes. Although both companies will continue to design high-end custom microprocessors, increasingly their competition will hinge on how well they assemble chips out of a stock of reusable cores.

In just the last quarter, Intel Corp. formally created a system-on-chip (SoC) enablement group under Gadi Singer, who has led many high-profile projects for the company. AMD could have a slight edge, claiming it started work more than three years ago on cores and design flows aimed at reuse.

Driving the trend is the shift from large, power-hungry CPUs to multicore processors. Intel and AMD are also gunning for a range of sockets outside their traditional PC markets, many of them in consumer markets.

"Every major element being developed going forward will be done in a way that makes it reusable," said Singer, who led Intel's efforts on its Pentium, Itanium and cellular processors and has been head of design automation software at the company. "We are defining practices, flows and architectures that will allow plug-and-play across all Intel products," he said of the new group.

Intel is not disclosing the group's head count or budget, but said that its mandate includes defining interconnects and test standards for silicon blocks and system-in-package devices. Singer and others noted that making the SoC shift will not be easy for a company with a long heritage of custom design at the circuit level aiming at top performance.

"Developing something that is highly modular requires more effort, which sometimes conflicts with other goals for a project, so we do get some pushback," said Singer. "But this extra effort is a very worthwhile investment. Going forward, having SoC capabilities will be part of our competitiveness."

Intel has said it has at least four SoCs in the works for systems outside its traditional PC markets. Tolapai is aimed at storage networks, Silverthorne at handhelds, Larabee at high-end visualization systems and Canmore at wired consumer devices. Each chip could be just the tip of a bigger iceberg.

"My group is funded to develop a family of ac-powered SoCs and the chips such as demodulators and tuners to go around them," said Bill Leszinske, general manager of Intel's consumer electronics group.

Leszinske joined the group two years ago in a reorganization that was initiated after Intel scrapped a high-profile effort to design silicon for microdisplays. In April, the group launched its first product, an Xscale-based CPU for set-top boxes, now used by Chunghwa Telecom in Taiwan. Besides the X86-based Canmore, it is also helping design a two-chip version of Tolapai aimed at printers.

"Intel is clearly playing catch-up in SoC methodology," said Bryan Lewis, a research vice president who tracks semiconductors for market watcher Gartner Inc. in San Jose, Calif. "It's very difficult to change a design culture, so Intel has its work cut out for it. They will be competing with Texas Instruments, STMicroelectronics and IBM, among others--and those companies definitely know the SoC game."

Many of Intel's competitors have a history of building ASICs, a market where SoC techniques were born. "Intel has been in and out of the ASIC market twice, and that has put them behind," said Lewis.

AMD in SoC Meanwhile, archrival AMD has been quietly working for more than three years on reusable X86 cores and an SoC design flow.

"I came to AMD with a strong charge to see the concept of SoC applied to the X86," said Chuck Moore, a senior fellow at AMD who formerly led the design of the Power4 at IBM.

Moore helped set up a 20-person SoC center of excellence that looked at issues such as interface standards and design flows. He is also leading the design of Bulldozer, AMD's next-generation X86 core, which aims to be reusable across a variety of PC processors.

"It was conceived from day one for use in multiple SoC products for multiple markets," said Moore.

A separate core, called Bobcat, is aimed at consumer devices scaling as low as 1 watt in power consumption. AMD has not yet disclosed details of its product plans for Bobcat.

Intel has a similar low-power X86 core in development in its ultramobility group. It will be available to Intel's internal SoC designers as a reusable core, Singer said.

As a result of its work to date, AMD has already defined address, data and control interfaces for SoCs. It has also defined wide, high-speed links with protocols optimized for on-chip communications, Moore said.

"The drive toward SoC...is an imperative in our industry. Without it, development costs would have skyrocketed," Moore said.

AMD's upcoming integrated notebook CPU, called Griffin, and its recently launched four-core server processor, Barcelona, are early products of the SoC work, Moore said. That's because they include memory controller and HyperTransport interface blocks more or less reused from other designs.

Looking ahead, AMD faces two major hurdles in SoC. On the marketing side, it needs to choose which blocks to integrate for which markets without generating too many point products.

"The SoC era opens up all sorts of opportunities to differentiate, but picking the right ones [is the trick]," said Moore. "It's a fantastic capability, but if misused it can blow up on you."

Facing another obstacle, this one on the technical side, AMD must find ways to bridge the CPU cores it makes in a silicon-on-insulator process with the media blocks built in standard CMOS by its ATI Technologies division.

"Bringing those two together is a big challenge for us," said Moore.

That said, AMD "got a shocking amount of IP [intellectual property] with ATI," said Moore, who called the IP one of "the motivating concepts" for the July 2006 merger.

For its part, Intel developed a block that handles MPEG-2 and H.264 decompression for the set-top-box chip it launched in April. It is upgrading that block, presumably for encoding, as part of the Canmore design. About two years ago, Intel also acquired the division of Zarlink Semiconductor that makes demodulators and tuners.

"We have long, multiyear road maps that include what IP we have or are developing and where we will work with partners [on IP]," said Leszinske of Intel's consumer electronics group.

One thing Intel does not yet have is a synthesizable, soft X86 macro core. But that could change in a year or so. As a research project, a handful of Intel's R&D engineers are developing a synthesizable X86 core and an SoC based on it, starting from a very simple internal research CPU core. The project could take a year.

"I have a thesis that in the future--about five to eight years from now--a synthesized design will not require any sacrifices in area or performance," said Shekhar Borkar, an Intel senior fellow and director of the company's circuit research lab. "If this thesis is true, everything people build in the future will be SoCs."

He pointed to a paper from the most recent VLSI Symposium, in which Toshiba reported a synthesized version of IBM's Cell processor with similar performance but about 30 percent less area.

Meanwhile, both Intel and AMD are pursuing advances in on-chip interconnects and design tools.

Intel will use the so-called Quick Path Interconnect debuting in next year's Nehalem processors as its primary coherent interconnect for a select group of coprocessors and chip sets. It is developing its Geneseo technology as a candidate for PCI Express version 3.0 that would link its CPUs to all other internal and external devices.

For its part, AMD is using coherent and noncoherent versions of HyperTransport. But the boundaries around those interconnects and the two that Intel is using could one day blur, said AMD's Moore.

"An interesting question is how these two pairs of standards will start to mingle," he said, suggesting multiprotocol links serving multiple purposes.

In addition, "there could be interesting protocol extensions beyond coherency for the next generation of HyperTransport," Moore added. Rather than communicating and synchronizing through memory, devices could link up in ways that "are more optimal," he said.

As for software design tools, AMD has evolved the flow used for its initial K8 Opteron chips in two directions. One flow targets full-custom designs and is used for cores such as Bulldozer. The other is aimed at SoCs and can import blocks from other ASIC flows used in-house.

AMD reevaluates its EDA tools each year, but to date has largely stuck with its major suppliers. Rather than develop new tools itself, it is working to support new levels of abstraction and hierarchies in existing tools.

"There is value in continuity [of tools and EDA vendors], but we don't let that prevent us from doing something new to get better short-term results and long-term potential," Moore said.

For its part, Intel is trying to consolidate "multiple tool flows [now in use for SoCs] into a unified SoC flow," a process that may take two years, said Singer. "You can't influence very much some products that are already in the pipeline, but you have much more influence over new products."

"Intel's heritage is to create a lot of our own design tools, but we are evolving to using more industry-standard tools," added Leszinske.