Event Qualifiers

Event specifiers for these PMCs support the following common qualifiers:

rsp=value

Configure the Off-core Response bits.

REQ_DMND_DATA_RD

Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches.

REQ_DMND_RFO

Counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO prefetches.

REQ_DMND_IFETCH

Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches.

REQ_WB

Counts the number of writeback (modified to exclusive) transactions.

REQ_PF_DATA_RD

Counts the number of data cacheline reads generated by L2 prefetchers.

REQ_PF_RFO

Counts the number of RFO requests generated by L2 prefetchers.

REQ_PF_IFETCH

Counts the number of code reads generated by L2 prefetchers.

REQ_PF_LLC_DATA_RD

L2 prefetcher to L3 for loads.

REQ_PF_LLC_RFO

RFO requests generated by L2 prefetcher

REQ_PF_LLC_IFETCH

L2 prefetcher to L3 for instruction fetches.

REQ_BUS_LOCKS

Bus lock and split lock requests.

REQ_STRM_ST

Streaming store requests.

REQ_OTHER

Any other request that crosses IDI, including I/O.

RES_ANY

Catch all value for any response types.

RES_SUPPLIER_NO_SUPP

No Supplier Information available.

RES_SUPPLIER_LLC_HITM

M-state initial lookup stat in L3.

RES_SUPPLIER_LLC_HITE

E-state.

RES_SUPPLIER_LLC_HITS

S-state.

RES_SUPPLIER_LLC_HITF

F-state.

RES_SUPPLIER_LOCAL

Local DRAM Controller.

RES_SNOOP_SNP_NONE

No details on snoop-related information.

RES_SNOOP_SNP_NO_NEEDED

No snoop was needed to satisfy the request.

RES_SNOOP_SNP_MISS

A snoop was needed and it missed all snooped caches: -For LLC Hit, ReslHitl was returned by all cores -For LLC Miss, Rspl was returned by all sockets and data was returned from DRAM.

RES_SNOOP_HIT_NO_FWD

A snoop was needed and it hits in at least one snooped cache. Hit denotes a cache-line was valid before snoop effect. This includes: -Snoop Hit w/ Invalidation (LLC Hit, RFO) -Snoop Hit, Left Shared (LLC Hit/Miss, IFetch/Data_RD) -Snoop Hit w/ Invalidation and No Forward (LLC Miss, RFO Hit S) In the LLC Miss case, data is returned from DRAM.

RES_SNOOP_HIT_FWD

A snoop was needed and data was forwarded from a remote socket. This includes: -Snoop Forward Clean, Left Shared (LLC Hit/Miss, IFetch/Data_RD/RFT).

RES_SNOOP_HITM

A snoop was needed and it HitM-ed in local or remote cache. HitM denotes a cache-line was in modified state before effect as a results of snoop. This includes: -Snoop HitM w/ WB (LLC miss, IFetch/Data_RD) -Snoop Forward Modified w/ Invalidation (LLC Hit/Miss, RFO) -Snoop MtoS (LLC Hit, IFetch/Data_RD).

RES_NON_DRAM

Target was non-DRAM system address. This includes MMIO transactions.

cmask=value

Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to
value.

edge

Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true.

inv

Invert the sense of comparison when the “
cmask” qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the “
cmask” qualifier.

(Event 07H, Umask 08H) The number of times that load operations are temporarily blocked because of older stores, with addresses that are not yet known. A load operation may incur more than one block of this type.

TLB_LOAD_MISSES.MISS_CAUSES_A_WALK

(Event 08H, Umask 01H) Misses in all TLB levels that cause a page walk of any page size.

(Event 2EH, Umask 4FH) This event counts requests originating from the core that reference a cache line in the last level cache.

LONGEST_LAT_CACHE.MISS

(Event 2EH, Umask 41H) This event counts each cache miss condition for references to the last level cache.

CPU_CLK_UNHALTED.THREAD_P

(Event 3CH, Umask 00H) Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling.

CPU_CLK_THREAD_UNHALTED.REF_XCLK

(Event 3CH, Umask 01H) Increments at the frequency of XCLK (100 MHz) when not halted.

L1D_PEND_MISS.PENDING

(Event 48H, Umask 01H) Increments the number of outstanding L1D misses every cycle. Set Cmaks = 1 and Edge =1 to count occurrences.

(Event 4EH, Umask 02H) Hardware Prefetch requests that miss the L1D cache. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for example.

L1D.REPLACEMENT

(Event 51H, Umask 01H) Counts the number of lines brought into the L1 data cache.

(Event B6H, Umask 01H) Counts executed load operations with all the following traits: 1. addressing of the format [base + offset], 2. the offset is between 1 and 2047, 3. the address specified in the base register is in one page and the address [base+offset] is in another page.

(Event E6H, Umask 01H) Counts the number of times the front end is re- steered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.

HISTORY

The
pmc library first appeared in
FreeBSD 6.0.

AUTHORS

The
Performance Counters Library (libpmc, -lpmc) library was written by
Joseph Koshy <jkoshy@FreeBSD.org>. The support for the Sandy Bridge Xeon microarchitecture was written by
Hiren Panchasara <hiren.panchasara@gmail.com>.