The problem is this line makes a hardware divisor value (baud_rate) to become 1 step larger than it should be, resulting in 2x lower communication frequency than it is possible under given in HZ desired limitation. Let's say I'm going to have a power-of-2-casted divisor of 0x80. Then __builtin_ffs() returns "8" as it should; baud_rate then becomes "7", which is 0b111 - and that value corresponds to f_PCLK/256 according to STM32F4xx refman, not f_PCLK/128!

What we need is harware divisor values equal to 0b000 for 0,1 and 2 division rates, and "baud_rate-2" for all other cases. So i suggest the following code: