Sign up to receive free email alerts when patent applications with chosen keywords are publishedSIGN UP

Abstract:

A semiconductor device along with circuits including the same and methods
of operating the same are described. The device includes an electrically
floating body region, and a gate is disposed over a first portion of the
body region. The device includes a source region adjoining a second
portion of the body region, the second portion adjacent the first portion
and separating the source region from the first portion. The device
includes a drain region adjoining a third portion of the body region, the
third portion adjacent the first portion and separating the drain region
from the first portion.

Claims:

1. An integrated circuit device comprising: a memory cell including a
transistor, the transistor comprising: a body region configured to be
electrically floating; a gate disposed over a first portion of the body
region; a source region adjoining a second portion of the body region,
the second portion adjacent the first portion and separating the source
region from the first portion; and a drain region adjoining a third
portion of the body region, the third portion adjacent the first portion
and separating the drain region from the first portion; wherein the
memory cell is configured to store a first data state representative of a
first charge in the first portion of the body region; wherein the memory
cell is configured to store a second data state representative of a
second charge in the first portion of the body region; and data write
circuitry coupled to the memory cell, the data write circuitry configured
to apply first write control signals to the memory cell to write the
first data state to the memory cell and second write control signals to
the memory cell to write the second data state to the memory cell,
wherein, in response to first write control signals, the electrically
floating body transistor generates a first source current which
substantially provides the first charge in the first portion of the body
region.

2. The integrated circuit device of claim 1, wherein the first write
control signals cause the first source current.

3. The integrated circuit device of claim 1, wherein the first write
control signals include a signal applied to the gate and a signal applied
to the source region, wherein the signal applied to the gate includes a
first voltage having a first amplitude and a second voltage having a
second amplitude.

4. The integrated circuit device of claim 1, wherein the first write
control signals include a signal applied to the gate and a signal applied
to the drain region, wherein the signal applied to the gate includes a
first voltage having a first amplitude and a second voltage having a
second amplitude.

5. The integrated circuit device of claim 1, wherein the first write
control signals cause a potential difference between the source region
and the drain region.

6. The integrated circuit device of claim 5, wherein the first write
control signals include a signal applied to the gate, wherein the signal
applied to the gate includes a first voltage having a first amplitude and
a second voltage having a second amplitude.

7. The integrated circuit device of claim 1, wherein the first write
control signals include a signal applied to the gate, a signal applied to
the source region, and a signal applied to the drain region to cause the
first source current, wherein: the signal applied to the source region
includes a first voltage having a first amplitude; the signal applied to
the drain region includes a second voltage having a second amplitude; and
the signal applied to the gate includes a third voltage having a third
amplitude and a fourth voltage having a fourth amplitude.

8. The integrated circuit device of claim 1, wherein the first write
control signals cause a first potential difference between the source
region and the drain region and include a signal applied to the gate that
includes a first voltage, wherein the first write control signals cause
an accumulation of minority carriers in the first portion of the body
region.

9. The integrated circuit device of claim 8, wherein the minority
carriers accumulate at a surface region of the first portion of body
region that is disposed near a gate dielectric, which is disposed between
the gate and the first portion of the body region.

10. The integrated circuit device of claim 8, wherein the minority
carriers accumulate at a surface region of the first portion of the body
region, wherein the surface region is disconnected from the source region
by the second portion of the body region.

11. The integrated circuit device of claim 8, wherein the minority
carriers accumulate at a surface region of the first portion of the body
region, wherein the surface region is disconnected from the drain region
by the third portion of the body region.

12. The integrated circuit device of claim 8, wherein the first write
control signals cause the first source current in the body region as a
result of impact ionization induced by the minority carriers.

13. The integrated circuit device of claim 8, wherein the signal applied
to the gate temporally changes to a second voltage that causes an
accumulation of majority carriers in the first portion of the body
region, wherein the majority carriers result in the first data state.

14. The integrated circuit device of claim 8, wherein the second write
control signals cause a second potential difference between the source
region and the drain region and include a signal applied to the gate that
includes the first voltage, wherein the second write control signals
prevent the first data state from being written into the first portion of
the body transistor.

15. The integrated circuit device of claim 8, wherein the second
potential difference is relatively less than the first potential
difference.

16. The integrated circuit device of claim 1, comprising data sense
circuitry coupled to the memory cell and configured to sense the data
state of the memory cell, wherein, in response to read control signals
applied to the memory cell, the transistor generates a second source
current which is representative of the data state of the memory cell,
wherein the data sense circuitry determines the data state of the memory
cell at least substantially based on the second source current.

17. The integrated circuit device of claim 16, wherein the read control
signals include signals applied to one or more of the gate, source
region, and drain region to cause the second source current which is
representative of the data state of the memory cell.

18. The integrated circuit device of claim 16, wherein the read control
signals cause a first potential difference between the source region and
the drain region.

19. The integrated circuit device of claim 18, wherein the signal applied
to the gate includes a negative voltage pulse.

20. The integrated circuit device of claim 1, wherein the source region
of the memory cell is connected to a source region of one or more
additional memory cells in a row of memory cells in the integrated
circuit device.

Description:

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This patent application is a continuation of U.S. patent
application Ser. No. 13/547,717, filed Jul. 12, 2012, which is a
divisional of U.S. patent application Ser. No. 12/019,320, filed Jan. 24,
2008, now U.S. Pat. No. 8,264,041, issued Sep. 11, 2012, which claims the
benefit of U.S. Provisional Patent Application No. 60/897,686, filed Jan.
26, 2007, each of which is hereby incorporated by reference herein in its
entirety.

[0003] The inventions relate to a semiconductor device, architecture,
memory cell, array, and techniques for controlling and/or operating such
device, cell, and array. More particularly, in one aspect, the inventions
relate to a dynamic random access memory ("DRAM") cell, array,
architecture and device, wherein the memory cell includes an electrically
floating body configured or operated to store an electrical charge.

BACKGROUND

[0004] There is a continuing trend to employ and/or fabricate advanced
integrated circuits using techniques, materials and devices that improve
performance, reduce leakage current and enhance overall scaling.
Semiconductor-on-Insulator (SOI) is a material in which such devices may
be fabricated or disposed on or in (hereinafter collectively "on"). Such
devices are known as SOI devices and include, for example, partially
depleted (PD), fully depleted (FD) devices, multiple gate devices (for
example, double or triple gate), and Fin-FET.

[0005] One type of dynamic random access memory cell is based on, among
other things, the electrically floating body effect of SOI transistors;
see, for example, U.S. Pat. No. 6,969,662 (the '662 patent). In this
regard, the dynamic random access memory cell may consist of a PD or a FD
SOI transistor (or transistor formed in bulk material/substrate) on
having a channel, which is disposed adjacent to the body and separated
from the channel by a gate dielectric. The body region of the transistor
is electrically floating in view of the insulation layer (or
non-conductive region, for example, in a bulk-type material/substrate)
disposed beneath the body region. The state of the memory cell is
determined by the concentration of charge within the body region of the
SOI transistor.

[0006] With reference to FIGS. 1A, 1B and 1C, in one embodiment,
semiconductor DRAM array 10 includes a plurality of memory cells 12 each
including transistor 14 having gate 16, body region 18, which is
configured to be electrically floating, source region 20 and drain region
22. The body region 18 is disposed between source region 20 and drain
region 22. Moreover, body region 18 is disposed on or above region 24,
which may be an insulation region (for example, in an SOI
material/substrate) or non-conductive region (for example, in a bulk-type
material/substrate). The insulation or non-conductive region 24 may be
disposed on substrate 26.

[0007] Data is written into or read from a selected memory cell by
applying suitable control signals to a selected word line(s) 28, a
selected source line(s) 30 and/or a selected bit line(s) 32. In response,
charge carriers are accumulated in or emitted and/or ejected from
electrically floating body region 18 wherein the data states are defined
by the amount of carriers within electrically floating body region 18.
Notably, the entire contents of the '662 patent, including, for example,
the features, attributes, architectures, configurations, materials,
techniques and advantages described and illustrated therein, are
incorporated by reference herein.

[0009] Notably, for at least the purposes of this discussion, logic high
or logic "1" corresponds to, for example, an increased concentration of
majority carries in the body region relative to an un-programmed device
and/or a device that is programmed with logic low or logic "0". In
contrast, logic low or logic "0" corresponds to, for example, a reduced
concentration of majority carries in the body region relative to an
un-programmed device and/or a device that is programmed with logic high
or logic "1".

[0010] In one conventional technique, the memory cell is read by applying
a small bias to the drain of the transistor as well as a gate bias which
is above the threshold voltage of the transistor. In this regard, in the
context of memory cells employing N-type transistors, a positive voltage
is applied to one or more word lines 28 to enable the reading of the
memory cells associated with such word lines. The amount of drain current
is determined or affected by the charge stored in the electrically
floating body region of the transistor. As such, conventional reading
techniques sense the amount of the channel current provided/generated in
response to the application of a predetermined voltage on the gate of the
transistor of the memory cell to determine the state of the memory cell;
a floating body memory cell may have two or more different current states
corresponding to two or more different logical states (for example, two
different current conditions/states corresponding to the two different
logical states: "1" and "0").

[0012] Notably, conventional programming/reading techniques often lead to
relatively large power consumption (due to, for example, high writing "0"
current) and relatively small memory programming window. The present
inventions, in one aspect, are directed to a combination of the
programming/reading methods which allows relatively low power memory
programming and provides a relatively larger memory programming window
(e.g., both relative to at least the conventional programming
techniques). This new approach may also provide a floating body memory
cell that may provide better power consumption and may include improved
retention characteristics.

INCORPORATION BY REFERENCE

[0013] Each patent, patent application, and/or publication mentioned in
this specification is herein incorporated by reference in its entirety to
the same extent as if each individual patent, patent application, and/or
publication was specifically and individually indicated to be
incorporated by reference.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In the course of the detailed description to follow, reference will
be made to the attached drawings. These drawings show different aspects
of the present inventions and, where appropriate, reference numerals
illustrating like structures, components, materials and/or elements in
different figures are labeled similarly. It is understood that various
combinations of the structures, components, materials and/or elements,
other than those specifically shown, are contemplated and are within the
scope of the present inventions.

[0015] Moreover, there are many inventions described and illustrated
herein. The present inventions are neither limited to any single aspect
nor embodiment thereof, nor to any combinations and/or permutations of
such aspects and/or embodiments. Moreover, each of the aspects of the
present inventions, and/or embodiments thereof, may be employed alone or
in combination with one or more of the other aspects of the present
inventions and/or embodiments thereof. For the sake of brevity, many of
those permutations and combinations will not be discussed separately
herein.

[0016] FIG. 1A is a schematic representation of a prior art DRAM array
including a plurality of memory cells comprised of one electrically
floating body transistor;

[0018] FIG. 1C is a cross-sectional view of the prior art memory cell of
FIG. 1B, cross-sectioned along line C-C;

[0019] FIGS. 2A and 2B are exemplary schematic illustrations of the charge
relationship, for a given data state, of the floating body, source and
drain regions of a prior art memory cell comprised of one electrically
floating body transistor (PD-SOI NMOS);

[0020] FIGS. 3A and 3B are exemplary schematic and general illustrations
of conventional methods to program a memory cell to logic state "1"
(i.e., generate or provide an excess of majority carrier in the
electrically floating body of the transistor (an N-type channel
transistor in this exemplary embodiment) of the memory cell of FIG. 1B;
majority carriers in these exemplary embodiments are generated or
provided by the channel electron impact ionization (FIG. 3A) and by GIDL
or band to band tunneling (FIG. 3B);

[0021] FIGS. 4A, 4B and 4C are exemplary schematics and general
illustrations of conventional methods to program a memory cell to logic
state "0" (i.e., provide relatively fewer majority carrier by removing
majority carriers from the electrically floating body of the transistor
of the memory cell of FIG. 1B; majority carriers may be removed through
the drain region/terminal of the transistor (FIG. 4A), the source
region/terminal of the transistor (FIG. 4B), and through both drain and
source regions/terminals of the transistor via using the back gate pulses
applied to the substrate/backside terminal of the transistor of the
memory cell (FIG. 4C);

[0022]FIG. 5 illustrates an exemplary schematic (and control signal) of a
conventional reading technique, the state of the memory cell may be
determined by sensing the amount of the channel current
provided/generated by the transistor of the memory cell in response to
the application of a predetermined voltage on the gate of the transistor;

[0025] FIG. 7B is an example characteristic curve of electrically floating
body transistor, under an embodiment;

[0026] FIGS. 8A and 8B show various stages of operation of transistor when
writing or programming logic "1", under an embodiment;

[0027] FIGS. 9A and 9B show various stages of operation of transistor when
writing or programming logic "0", under an embodiment;

[0028] FIG. 10 shows an example schematic (and control signal) of an
example embodiment of an aspect of the present inventions of holding or
maintaining the data state of a memory cell when programming, for
example, a neighboring memory cell to a predetermined data state (for
example, logic state "1" and/or logic state "0");

[0029] FIG. 11 is an example of an operation under which the data state of
a memory cell may be read and/or determined by applying control signals
having predetermined voltages to gate and source region and drain region
of transistor, under an embodiment;

[0030] FIG. 12 is a plot of voltage levels versus time for examples of
each of write "0", write "1", and read operations, under an embodiment;

[0031] FIG. 13 is a flow diagram for forming a transistor, under an
embodiment;

[0032] FIG. 14 shows an electrically floating body transistor in which the
first portion of the body region is made discontinuous with only the
drain by a third portion of the body region, under an embodiment;

[0033] FIG. 15 shows an electrically floating body transistor in which the
first portion of the body region is made discontinuous with only the
drain by a third portion of the body region, under an embodiment; the
source region includes a highly-doped (HD) portion and a lightly-doped
(LD) portion;

[0034] FIG. 16 shows an electrically floating body transistor in which the
first portion of the body region is made discontinuous with only the
source by a second portion of the body region, under an embodiment;

[0035] FIG. 17 shows an electrically floating body transistor in which the
first portion of the body region is made discontinuous with the only the
source by a second portion of the body region, under an embodiment; the
drain region includes a highly-doped portion and a lightly-doped portion;

[0036] FIG. 18 shows an electrically floating body transistor in which the
first portion of the body region is made discontinuous with both the
source and drain regions, and each of the source and drain regions
comprise LD and/or HD portions, under an embodiment;

[0037] FIG. 19 shows an electrically floating body transistor in which the
first portion of the body region is made discontinuous with both the
source and drain regions, and each of the source and drain regions are
LD, under an embodiment;

[0038] FIG. 20 shows an electrically floating body transistor in which the
first portion of the body region is made discontinuous with both the
source and drain regions, and the source region is LD and the drain
region is HD, under an embodiment;

[0039] FIG. 21 shows an electrically floating body transistor in which the
first portion of the body region is made discontinuous with both the
source and drain regions, and the source region is HD and the drain
region is LD, under an embodiment;

[0040]FIG. 22 shows an electrically floating body transistor in which the
first portion of the body region is made discontinuous with both the
source and drain regions, and each of the source and drain regions are
HD, under an embodiment;

[0041] FIGS. 23A and 23B are schematic block diagrams of embodiments of an
integrated circuit device including, among other things, a memory cell
array, data sense and write circuitry, memory cell selection and control
circuitry, according certain aspects of the present inventions; and

[0042] FIGS. 24, 25 and 26 illustrate an embodiment of an exemplary memory
array having a plurality of memory cells and employing a separate source
line configuration for each row of memory cells, according to certain
aspects of the present inventions.

DETAILED DESCRIPTION

[0043] There are many inventions described herein as well as many aspects
and embodiments of those inventions. In one aspect, the present
inventions are directed to a semiconductor device including an
electrically floating body. In another aspect, the present inventions are
directed to techniques to control and/or operate a semiconductor memory
cell (and memory cell array having a plurality of such memory cells as
well as an integrated circuit device including a memory cell array)
having one or more electrically floating body transistors in which an
electrical charge is stored in the body region of the electrically
floating body transistor. The techniques of the present inventions may
employ intrinsic bipolar transistor currents (referred to herein as
"source" currents) to control, write and/or read a data state in such a
memory cell. In this regard, the present inventions may employ the
intrinsic source current to control, write and/or read a data state in/of
the electrically floating body transistor of the memory cell.

[0044] The present inventions are also directed to semiconductor memory
cell, array, circuitry and device to implement such control and operation
techniques. Notably, the memory cell and/or memory cell array may
comprise a portion of an integrated circuit device, for example, logic
device (such as, a microcontroller or microprocessor) or a portion of a
memory device (such as, a discrete memory).

[0045]FIG. 6 shows an electrically floating body transistor 14, under an
embodiment. The transistor 14 includes a body region 18 configured to be
electrically floating. The body region 18 includes three portions or
regions 18-1/18-2/18-3 that collectively define the electrically floating
body 18. Each of the three portions 18-1/18-2/18-3 comprises the same or
similar material (e.g., P-type in this example). The transistor 14
includes a gate 16 disposed over the first portion 18-1 of the body
region 18. A gate dielectric 32 (e.g., gate oxide) is disposed between
the gate 16 and the body region 18, and spacers SP are adjacent the gate
dielectric 32.

[0046] A source region 20 adjoins a second portion 18-2 of the body region
18; the second portion 18-2 of the body region is adjacent the first
portion 18-1 and separates the source region 20 from the first portion
18-1. A drain region 22 adjoins a third portion 18-3 of the body region
18; the third portion 18-3 of the body region is adjacent the first
portion 18-1 and separates the drain region 22 from the first portion
18-1. The source region 20 and/or drain region 22 is created using
conventional doping or implantation techniques but is not so limited. The
second portion 18-2 and third portion 18-3 of the body region function to
electrically "disconnect" (e.g., disconnect any charge that may
accumulate, disconnect any inversion channel that may form) in the first
portion 18-1 from one or more of the source 20 and the drain 22 as
described in detail below.

[0047] An inversion channel is generated in the body region of
conventional MOSFET devices in response to the application of control
signals to the MOFSET. Once formed the inversion channel provides a
continuous electrical channel from the source region to the body region.
The inversion channel of conventional devices spans the entire body
region as a result of the source and drain regions being configured,
relative to the gate, to each underlie the gate. In this manner,
application of the appropriate gate voltage to a conventional device
causes the inversion channel to form a continuous electrical channel from
the source to the drain region.

[0048] In contrast to conventional MOSFET devices, however, the source 20
and/or drain 22 regions of an embodiment are configured so that no
portion of the source 20 and/or drain 22 regions is positioned under the
gate 16. Configuration of the source 20 and/or drain 22 regions of an
embodiment includes configuration through control of the shape and/or
size of the doped source 20 and/or doped drain 22 regions of the
transistor. Because only the first portion 18-1 of the body region is
under the gate 16, charge that may accumulate or an inversion channel
that may form is found only in the first portion 18-1 when the
appropriate control signal is applied to the gate 16. No charge is
accumulated and no inversion channel is formed in the second portion 18-2
and/or third portion 18-3 because these portions do not underlie the gate
16. The second portion 18-2 and/or third portion 18-3 therefore cause
accumulated charge if any (or inversion channel if formed) to be
discontinuous with the source region 20 and/or drain region 22.

[0049] As a result of the application of gate voltage to transistor 14,
charge builds up in the first portion 18-1 of the body region 18, but
current does not flow in the body region 18 because of the absence of
accumulated charge and/or a continuous inversion channel between the
source and drain regions. The discontinuous configuration of the first
portion 18-1 of the body region relative to the source and drain regions
therefore acts as an "open circuit" relative to the flow of current
between the source 20 and drain 22 regions. Any charge present in the
body region 18 thus causes transistor 14 to behave like a capacitor
because the region of charge in the body 18-1 is disconnected from the
source 20 and/or drain 22 regions.

[0050]FIG. 7A shows electrically floating body transistor 14
schematically illustrated as including a MOS capacitor "component" and an
intrinsic bipolar transistor "component", under an embodiment. In one
aspect, the present inventions employ the intrinsic bipolar transistor
"component" to program/write as well as read memory cell 12. In this
regard, the intrinsic bipolar transistor generates and/or produces a
source or bipolar transistor current which is employed to program/write
the data state in memory cell 12 and read the data state of memory cell
12. Notably, in this example embodiment, electrically floating body
transistor 14 is an N-channel device. As such, majority carriers 34 are
"holes".

[0051] The bipolar transistor 14 of an embodiment has a floating body,
meaning the potential is not fixed or "floating". The potential for
example depends on the charge at the gate. A conventional bipolar
transistor requires each of base current, emitter current, and collector
current for proper operation. Any base of the transistor 14 in this
embodiment, however, is floating and not fixed because there is no base
contact as found in conventional bipolar FETs; the current in this
transistor is therefore referred to herein as a "source" current produced
by impact ionization in the body region as described below.

[0052] FIG. 7B is an example characteristic curve of electrically floating
body transistor 14, under an embodiment. The characteristic curve shows a
significant increase in source current (e.g., "log I") at and above a
specific threshold value of the potential difference between applied
source voltage and applied drain voltage ("source-drain potential
difference"). The reason for this is that a voltage differential at or
above a certain threshold generates a high electric field in the body
region. The high electric field results in impact ionization in the first
portion 18-1 of the body region 18, a process during which electrons or
particles with enough energy generate majority carriers i.e. holes. The
impact ionization drives majority carriers to the body region, which
increases the body potential, while any minority carriers flow to the
drain (or source) region. The increased body potential results in an
increase in source current in the body region; thus, the excess majority
carriers of the body region generate source current of transistor 14 of
an embodiment.

[0053] FIGS. 8A and 8B show operation of transistor 14 when writing or
programming logic "1", under an embodiment. The transistor 14 of this
embodiment is an N-channel or nMOS FET, but is not so limited; transistor
14 may be a P-channel or pMOS FET in an alternative embodiment. The
N-channel device includes source 20 and drain 22 regions comprising
N+-type material while the body region 18 comprises a P-type material.

[0054] A logic "1" programming operation of an embodiment includes a two
stage control signal application during which the gate voltage is changed
from a first voltage level to a second voltage level. In operation, when
writing or programming logic "1", in one embodiment, control signals
having predetermined voltages (for example, Vg=0.5 v, Vs=0 v, and Vd=2.5
v) are initially applied during stage one to gate 16, source region 20
and drain region 22 (respectively) of transistor 14 of memory cell 12
(FIG. 8A). The stage one control signals may result in an accumulation of
minority carriers (not shown) in the electrically floating body 18. As a
result of the polarity (e.g., positive) of the control signal applied to
the gate with the stage one control signals, any minority carriers that
happen to be present in the body region 18 accumulate in the first
portion 18-1 of the body 18. The minority carriers may accumulate in an
area of the first portion 18-1 under the gate, but are not so limited.

[0055] The physical behavior in the first portion 18-1 of the body 18 in
response to the stage one control signals of an embodiment is in contrast
to conventional transistor devices in which an inversion channel (also
referred to as an "N-channel") forms under the gate in an area that is
close to the interface between gate dielectric 32 and electrically
floating body 18. The inversion channel is of the same type as the source
and drain regions (e.g., N-type in an nMOS FET) and functions to
electrically couple the source and drain regions.

[0056] The inversion channel, however, is not generally formed in the
transistor 14 of an embodiment and, additionally, the accumulation of
minority carriers in the first portion 18-1 of the body if any is
discontinuous with the source 20 and/or drain 22 regions of the device.
The reason that no inversion channel is formed in the transistor 14 is
because, as the first portion 18-1 of the body 18 is electrically
"disconnected" from the source 20 and drain 22 regions, the time required
to create an inversion channel during a programming operation is quite
long relative to a writing time for example. Therefore, considering an
example writing time of an embodiment approximately in a range of 1-10
nanoseconds, and considering the time required for generation of an
inversion channel in the "disconnected" first portion 18-1 of the body is
much longer than 10 nanoseconds, an inversion channel is not generally
created in the transistor 14 during typical programming operations.
Similarly, relatively few or no minority carriers accumulate in the body
region.

[0057] Furthermore, even if an inversion channel were to form in the first
portion 18-1 of the body region as a result of the gate voltage, the
inversion channel would not form in the second 18-2 and third 18-3
portions of the body region because these regions 18-2/18-3 are not under
the gate. Therefore, any inversion channel formed under the embodiments
described herein would be "disconnected" from or discontinuous with the
source 20 and drain 22 regions.

[0058] The lack of an inversion channel or discontinuous inversion channel
(if one were to form) of the transistor of an embodiment is in contrast
to conventional transistors in which the inversion channel forms and
spreads from the source to the drain and provides conductivity of the
transistor. However, the configuration of these conventional devices is
such that the gate overlays the entire body region between the source and
drain regions, and the programming times are of a length that ensures
formation of an inversion channel when appropriate voltages are applied,
thereby creating a continuous inversion channel that "connects" the
source and drain regions upon application of the appropriate polarity
signal at the gate.

[0059] The stage one control signals also generate or provide a source
current in electrically floating body region 18 of transistor 14. More
specifically, the potential difference between the source voltage and the
drain voltage (e.g., 2.5 volts) is greater than the threshold required to
turn on the bipolar transistor. Therefore, source current of the
transistor causes or produces impact ionization and/or the avalanche
multiplication phenomenon among particles in the electrically floating
body region 18. The impact ionization produces, provides, and/or
generates an excess of majority carriers 806 (FIG. 8B) in the
electrically floating body region 18 of transistor 14 of memory cell 12
as described above.

[0060] Notably, it is preferred that the source current responsible for
impact ionization and/or avalanche multiplication in electrically
floating body region 18 is initiated or induced by the control signal
applied to gate 16 of transistor 14 along with the potential difference
between the source 20 and drain 22 regions. Such a control signal may
induce channel impact ionization which raises or increases the potential
of body region 18 and "turns on", produces, causes and/or induces a
source current in transistor 14. One advantage of the proposed
writing/programming technique is that a large amount of the excess
majority carriers 806 may be generated and stored in electrically
floating body region 18 of transistor 14.

[0061] The stage two control signals are subsequently applied to the
transistor when writing or programming logic "1" as described above. The
stage two control signals are control signals having predetermined
voltages (for example, Vg=-1.0 v, Vs=0 v, and Vd=2.5 v) applied to gate
16, source region 20 and drain region 22 (respectively) of transistor 14
of memory cell 12 (FIG. 8B) subsequent to stage one. As a result of the
polarity (e.g., negative) of the control signal applied to the gate with
the stage two control signals, the majority carriers 806 of the body
region 18 accumulate near the surface of the first portion 18-1 of the
body region (FIG. 8B). The polarity of the gate signal (e.g., negative)
combined with the floating body causes he majority carriers 806 to become
trapped or "stored" near the surface of the first portion 18-1 of the
body region. In this manner the body region 18 of the transistor "stores"
charge (e.g., equivalently, functions like a capacitor). Thus, in this
embodiment, the predetermined voltages of the stage one and stage two
control signals program or write logic "1" in memory cell 12 via impact
ionization and/or avalanche multiplication in electrically floating body
region 18.

[0062] FIGS. 9A and 9B show operation of transistor 14 when writing or
programming logic "0", under an embodiment. A logic "0" programming
operation of an embodiment includes a two stage control signal
application during which the gate voltage is changed from a first voltage
level to a second voltage level. In operation, when writing or
programming logic "0", in one embodiment, control signals having
predetermined voltages (for example, Vg=0.5 v, Vs=0.5 v, and Vd=2.5 v)
are initially applied during stage one to gate 16, source region 20 and
drain region 22 (respectively) of transistor 14 of memory cell 12 (FIG.
9A). The stage one control signals may result in an accumulation of
minority carriers (not shown) in the electrically floating body 18. More
specifically, as a result of the polarity (e.g., positive) of the control
signal applied to the gate with the stage one control signals, any
accumulation of minority carriers occurs under the gate 16 in the first
portion 18-1 of the body region, in an area that is close to the
interface between gate dielectric 32 and electrically floating body 18 as
described above. Any minority carriers that accumulate are in the first
portion 18-1 of the body region as a result of the gate voltage, and thus
do not accumulate in the second 18-2 and third 18-3 portions of the body
region. Therefore, the accumulated charge of the body region 18 is
discontinuous with the source 20 and drain 22 regions.

[0063] The potential difference between the source voltage and the drain
voltage (e.g., 2.0 volts) of the stage one control signals, however, is
less than the threshold required to turn on transistor 14. Consequently,
no impact ionization takes place among particles in the body region 18
and no bipolar or source current is produced in the electrically floating
body region 18. Thus, no excess of majority carriers are generated in the
electrically floating body region 18 of transistor 14 of memory cell 12.

[0064] The stage two control signals are subsequently applied to the
transistor 14 when writing or programming logic "0" as described above.
The stage two control signals are control signals having predetermined
voltages (for example, Vg=-1.0 v, Vs=0.5 v, and Vd=2.5 v) applied to gate
16, source region 20 and drain region 22 (respectively) of transistor 14
of memory cell 12 (FIG. 9B) subsequent to stage one. The polarity (e.g.,
negative) of the gate signal may result in any minority carriers that
accumulate being removed from electrically floating body region 18 of
transistor 14 via one or more of the source region 20 and the drain
region 22. Furthermore, the polarity of the gate signal (e.g., negative)
causes any minority carriers remaining in the body region 18 to be
trapped or "stored" near the surface of the first portion of the body
region 18. The result is an absence of excess majority carriers in the
body region 18 so that, in this manner, the predetermined voltages of the
stage one and stage two control signals program or write logic "0" in
memory cell 12.

[0065] A logic "0" programming operation of an alternative embodiment
includes a two stage control signal application during which the gate
voltage is changed from a first voltage level to a second voltage level.
In operation, when writing or programming logic "0", in this alternative
embodiment, control signals having predetermined voltages (for example,
Vg=0 v, Vs=0 v, and Vd=0 v) are initially applied during stage one to
gate 16, source region 20 and drain region 22 (respectively) of
transistor 14 of memory cell 12.

[0066] The voltage levels described here as control signals to implement
the write operations are provided merely as examples, and the embodiments
described herein are not limited to these voltage levels. The control
signals increase the potential of electrically floating body region 18
which "turns on", produces, causes and/or induces a source current in the
transistor of the memory cell. In the context of a write operation, the
source current generates majority carriers in the electrically floating
body region which are then stored. In the context of a read operation,
the data state may be determined primarily by, sensed substantially using
and/or based substantially on the source current that is responsive to
the read control signals and significantly less by the interface channel
current component, which is less significant and/or negligible relatively
to the bipolar component.

[0067] Accordingly, the voltage levels to implement the write operations
are merely examples of control signals. Indeed, the indicated voltage
levels may be relative or absolute. Alternatively, the voltages indicated
may be relative in that each voltage level, for example, may be increased
or decreased by a given voltage amount (for example, each of the gate,
source, and drain voltage may be increased or decreased by 0.5, 1.0 and
2.0 volts) whether one or more of the voltages (for example, the source,
drain or gate voltages) become or are positive and negative.

[0068] In one embodiment, the memory cell 12 may be implemented in a
memory cell array. When a memory cell is implemented in a memory cell
array configuration, it may be advantageous to implement a "holding"
operation or condition to certain memory cells when programming one or
more other memory cells of the array in order to improve or enhance the
retention characteristics of such certain memory cells. In this regard,
the transistor of the memory cell may be placed in a "holding" state via
application of control signals (having predetermined voltages) which are
applied to the gate and the source and drain regions of the transistor of
the memory cells which are not involved in the write or read operations.

[0069] For example, with reference to FIG. 10, such control signals
provide, cause and/or induce majority carrier accumulation in an area
that is close to the interface between gate dielectric 32 and
electrically floating body 18. In this embodiment, it may be preferable
to apply a negative voltage to gate 16 where transistor 14 is an
N-channel type transistor 14. The proposed holding condition may provide
enhanced retention characteristics.

[0070] With reference to FIG. 11, in one embodiment, the data state of
memory cell 12 may be read and/or determined by applying control signals
having predetermined voltages to gate 16 and source region 20 and drain
region 22 of transistor 14 (for example, Vg=-1.0 v, Vs=0 v and Vd=2.5 v,
respectively). Such control signals, in combination, induce and/or cause
a source current in memory cells 12 that are programmed to logic "1" as
described above. As such, sensing circuitry (for example, a cross-coupled
sense amplifier), which is coupled to transistor 14 (for example, drain
region 22) of memory cell 12, senses the data state using primarily
and/or based substantially on the source current. Notably, for those
memory cells 12 that are programmed to logic "0", such control signals
induce, cause and/or produce little to no source current (for example, a
considerable, substantial or sufficiently measurable source current).

[0071] Thus, in response to read control signals, electrically floating
body transistor 14 generates a source current which is representative of
the data state of memory cell 12. Where the data state is logic high or
logic "1", electrically floating body transistor 14 provides a
substantially greater source current than where the data state is logic
low or logic "0". Electrically floating body transistor 14 may provide
little to no source current when the data state is logic low or logic
"0". As discussed in more detail below, data sensing circuitry determines
the data state of the memory cell based substantially on the source
current induced, caused and/or produced in response to the read control
signals.

[0072] The voltage levels described here as control signals to implement
the read operations are provided merely as examples, and the embodiments
described herein are not limited to these voltage levels. The indicated
voltage levels may be relative or absolute. Alternatively, the voltages
indicated may be relative in that each voltage level, for example, may be
increased or decreased by a given voltage amount (for example, each
voltage may be increased or decreased by 0.5, 1.0 and 2.0 volts) whether
one or more of the voltages (for example, the source, drain or gate
voltages) become or are positive and negative.

[0073] FIG. 12 is a plot of voltage levels versus time for examples of
each of write "0", write "1", and read operations, under an embodiment.
These examples are described in detail above. The voltage levels for each
of the source and drain are interchangeable as a result of the MOSFET
being a symmetrical device; therefore, voltage levels shown or described
herein as applied to the source can be applied to the drain, while
voltage levels shown or described herein as applied to the drain can be
applied to the source.

[0074] As described above with reference to FIG. 6, electrically floating
body transistor 14 includes a body region 18 configured to be
electrically floating. The body region 18 includes three portions or
regions 18-1/18-2/18-3 that collectively define the electrically floating
body 18. The transistor 14 includes a gate 16 disposed over the first
portion 18-1 of the body region 18. A source region 20 adjoins a second
portion 18-2 of the body region 18, and a drain region 22 adjoins a third
portion 18-3 of the body region 18; the second portion 18-2 and third
portion 18-3 of the body region 18 each adjoin the first portion 18-1.
Consequently, the second portion 18-2 and third portion 18-3 of the body
region function to "disconnect" any charge that may accumulate and/or any
inversion channel that may form in the first portion 18-1 from one or
more of the source 20 and the drain 22.

[0075] FIG. 13 is a flow diagram for forming transistor 14, under an
embodiment. Transistor 14 is formed, generally, by forming 1302 a
semiconductor on an insulator. An insulating layer and a gate is formed
1304 over a first portion of the semiconductor. Spacers are formed 1306
over a second portion and a third portion of the semiconductor, and the
spacers adjoin the insulating layer. The first portion, second portion,
and third portion of the semiconductor collectively form the floating
body region. Formation of transistor 14 continues by forming 1308 a
source region through implantation of an impurity into a fourth portion
of the semiconductor after forming the spacers. The fourth portion of the
semiconductor is adjacent the second portion. A drain region is also
formed 1308 by implanting the impurity into a fifth portion of the
semiconductor after forming the spacers. The fifth portion of the
semiconductor is adjacent the third portion.

[0076] More specifically, in fabricating transistor 14, the gate is
defined and used as a mask during implantation of the semiconductor to
form the source and drain regions of the device. The spacers are then
formed prior to any implantation or doping of the semiconductor so that
all implantation of the semiconductor (e.g., implantation to form the
source and drain) is performed after formation of the spacers. This is in
contrast to conventional semiconductor processes in which a gate is
formed, followed by a first implantation process (e.g., to form a
lightly-doped portion of the source and drain regions), followed by
formation of the spaces, and followed by a second implantation process
(e.g., to form a highly-doped portion of the source and drain regions).

[0077] As a result of implanting only after formation of the spacers, the
doping profiles that result in creation of the source and/or drain region
are configured so that the body region includes the second 18-2 and/or
third 18-3 portions and thus extends beyond an extended lateral boundary
of the gate. The second 18-2 and/or third 18-3 portions of the body
region function to prevent any inversion channel formation through the
entire body region of the device because the area of the body region in
which the channel forms under the gate is not continuous with the source
and drain regions, as described above. Therefore, upon application of a
gate voltage that is appropriate to material of the body region, charge
accumulates in the body region of the device, but current cannot flow
between the source and drain regions because no inversion channel is
formed between the source and/or drain and any accumulated charge is
disconnected from the source and/or drain.

[0078] The transistor devices of various alternative embodiments can
provide a discontinuous region of any accumulated charge in the body by
disconnecting the first portion of the body as described herein at the
source region, the drain region, or both the source and drain regions.
Further, various doping densities (e.g., very light, light, high, and
very high doping) and/or profiles can be used in the source, body, and
drain regions of the transistor 14. Examples follow of various
alternative embodiments.

[0079] FIG. 14 shows an electrically floating body transistor 14 in which
the first portion 18-1 of the body region is made discontinuous with only
the drain by a third portion 18-3 of the body region, under an
embodiment.

[0080] FIG. 15 shows an electrically floating body transistor 14 in which
the first portion 18-1 of the body region is made discontinuous with only
the drain by a third portion 18-3 of the body region, under an
embodiment. The source region includes a highly-doped (HD) portion and a
lightly-doped (LD) portion.

[0081] FIG. 16 shows an electrically floating body transistor 14 in which
the first portion 18-1 of the body region is made discontinuous with only
the source by a second portion 18-2 of the body region, under an
embodiment.

[0082] FIG. 17 shows an electrically floating body transistor 14 in which
the first portion 18-1 of the body region is made discontinuous with the
only the source by a second portion 18-2 of the body region, under an
embodiment. The drain region includes a highly-doped portion and a
lightly-doped portion.

[0083] FIG. 18 shows an electrically floating body transistor 14 in which
the first portion 18-1 of the body region is made discontinuous with both
the source and drain regions, and each of the source and drain regions
comprise LD and/or HD portions, under an embodiment.

[0084] FIG. 19 shows an electrically floating body transistor 14 in which
the first portion 18-1 of the body region is made discontinuous with both
the source and drain regions, and each of the source and drain regions
are LD, under an embodiment.

[0085] FIG. 20 shows an electrically floating body transistor 14 in which
the first portion 18-1 of the body region is made discontinuous with both
the source and drain regions, and the source region is LD and the drain
region is HD, under an embodiment.

[0086] FIG. 21 shows an electrically floating body transistor 14 in which
the first portion 18-1 of the body region is made discontinuous with both
the source and drain regions, and the source region is HD and the drain
region is LD, under an embodiment.

[0087]FIG. 22 shows an electrically floating body transistor 14 in which
the first portion 18-1 of the body region is made discontinuous with both
the source and drain regions, and each of the source and drain regions
are HD, under an embodiment.

[0088] The programming techniques described above may consume less power
relative to conventional techniques (e.g., FIGS. 4A and 4B). The reduced
power consumption relates to the programming techniques of the present
inventions being implemented without employing a back gate terminal
(Compare, FIG. 4C), thereby reducing or eliminating the flow of any
source current in the device when the device is in an "off" state.
Furthermore, the current for writing or programming to logic "0" may be
smaller when compared to such conventional techniques.

[0089] The gate oxide thickness in conventional devices is required to be
substantial in order to not be broken down by the high electric field
potential. The high electric field potential results from the relatively
high potential difference required between the source and drain regions
during write operations. In contrast, however, the embodiments of
transistor 14 described herein produce a relatively lower potential
difference between the source and drain regions during write operations.
The lower potential difference results from the device configuration
described above which includes an increased distance between the source
and drain regions resulting from the configuration (e.g., size, shape,
etc.) of the source and drain regions relative to the gate region.
Because the electric field potential is reduced significantly with this
design, the gate oxide region can be thinner.

[0090] As mentioned above, the present inventions may be implemented in an
integrated circuit device (for example, a discrete memory device or a
device having embedded memory) including a memory array having a
plurality of memory cells arranged in a plurality of rows and columns
wherein each memory cell includes an electrically floating body
transistor. The memory arrays may comprise N-channel, P-channel and/or
both types of transistors. Indeed, circuitry that is peripheral to the
memory array (for example, data sense circuitry (for example, sense
amplifiers or comparators), memory cell selection and control circuitry
(for example, word line and/or source line drivers), as well as row and
column address decoders) may include P-channel and/or N-channel type
transistors.

[0091] For example, with reference to FIGS. 23A and 23B, the integrated
circuit device may include array 10, having a plurality of memory cells
12, data write and sense circuitry 36, and memory cell selection and
control circuitry 38. The data write and sense circuitry 36 reads data
from and writes data to selected memory cells 12. In one embodiment, data
write and sense circuitry 36 includes a plurality of data sense
amplifiers. Each data sense amplifier receives at least one bit line 32
and an output of reference generator circuitry (for example, a current or
voltage reference signal). In one embodiment, the data sense amplifier
may be a cross-coupled type sense amplifier as described and illustrated
in U.S. Pat. No. 7,301,838, filed by Waller and Carman, on Dec. 12, 2005,
and entitled "Sense Amplifier Circuitry and Architecture to Write Data
into and/or Read Data from Memory Cells", the application being
incorporated herein by reference in its entirety) to sense the data state
stored in memory cell 12 and/or write-back data into memory cell 12.

[0092] The data sense amplifier may employ voltage and/or current sensing
circuitry and/or techniques. In the context of current sensing, a current
sense amplifier may compare the current from the selected memory cell to
a reference current, for example, the current of one or more reference
cells. From that comparison, it may be determined whether memory cell 12
contained logic high (relatively more majority carries 34 contained
within body region 18) or logic low data state (relatively less majority
carries 28 contained within body region 18). Notably, the present
inventions may employ any type or form of data write and sense circuitry
36 (including one or more sense amplifiers, using voltage or current
sensing techniques, to sense the data state stored in memory cell 12) to
read the data stored in memory cells 12 and/or write data in memory cells
12.

[0093] Memory cell selection and control circuitry 38 selects and/or
enables one or more predetermined memory cells 12 to facilitate reading
data from and/or writing data to the memory cells 12 by applying a
control signal on one or more word lines 28. The memory cell selection
and control circuitry 38 may generate such control signals using address
data, for example, row address data. Indeed, memory cell selection and
control circuitry 38 may include a conventional word line decoder and/or
driver. There are many different control/selection techniques (and
circuitry) to implement the memory cell selection technique. Such
techniques, and circuitry, are well known to those skilled in the art.
All such control/selection techniques, and circuitry, whether now known
or later developed, are intended to fall within the scope of the present
inventions.

[0094] The present inventions may be implemented in any architecture,
layout, and/or configuration comprising memory cells having electrically
floating body transistors. For example, in one embodiment, memory array
10 including a plurality of memory cells 12 having a separate source line
for each row of memory cells (a row of memory cells includes a common
word line connected to the gates of each memory cell of the row). (See,
for example, FIGS. 24, 25 and 26). The memory array 10 may employ one or
more of the example programming, reading and/or holding techniques
described above.

[0095] In one embodiment, the present inventions are implemented in
conjunction with a two step write operation whereby all the memory cells
of a given row are written to a predetermined data state by first
executing a "clear" operation, whereby all of the memory cells of the
given row are written or programmed to logic "0", and thereafter
selective memory cells of the row are selectively write operation to the
predetermined data state (here logic "1"). The present inventions may
also be implemented in conjunction with a one step write operation
whereby selective memory cells of the selected row are selectively
written or programmed to either logic "1" or logic "0" without first
implementing a "clear" operation.

[0096] With reference to FIGS. 24 and 25, memory cells 12 may be
programmed using the two step operation wherein a given row of memory
cells are written to a first predetermined data state by first executing
a "clear" operation (which, in this example embodiment, all of the memory
cells of the given row are written or programmed to logic "0") and
thereafter selected memory cells are written to a second predetermined
data state (i.e., a selective write operation to the second predetermined
data state). The "clear" operation may be performed by writing or
programming each memory cell of the given row to a first predetermined
data state (in this example embodiment the first predetermined data state
is logic "0") using the inventive technique described above.

[0097] In particular, transistor of each memory cell 12 of a given row
(for example, memory cells 12a-12d) is controlled to store logic "0". In
this regard, stage one and stage two control signals to implement a clear
operation as described above are applied to the gate, the source region
and the drain region of the transistor of memory cells 12a-12d. In
response, the same logic state (for example, logic low or logic "0") is
stored in memory cells 12a-12d and the state of memory cells 12a-12d are
"cleared".

[0098] Thereafter, selected memory cells of the given row may be
programmed to the second predetermined logic state. In this regard, the
transistors of certain memory cells of a given row are written to the
second predetermined logic state in order to store the second
predetermined logic state in memory cells. For example, with reference to
FIG. 25, memory cells 12b and 12c are programmed to logic high or logic
"1" by applying (i) 0.5 v to the gate (via word line 28i), (ii) 0 v
to the source region (via source line 30), and (iii) 2.5 v to the drain
region (via bit line 32j+1 and 32j+2), followed by application
of -1.0 v to the gate (via word line 28i). In particular, such
control signals generate or provide an excess of majority carriers in the
electrically floating body region of the transistor of memory cells 12b
and 12c which corresponds to logic high or logic "1".

[0099] As mentioned above, it is preferred that the source current
responsible for impact ionization and/or avalanche multiplication in the
floating body is initiated or induced by the control signal (control
pulse) applied to the gate of the transistor. Such a signal/pulse may
induce the channel impact ionization which raises or increases the
potential of the electrically floating body region of the transistor of
memory cells 12b and 12c and "turns-on" and/or produces a source current
in transistor 14. One advantage of the proposed method is that a large
amount of the excess majority carriers may be generated and stored in the
electrically floating body region of the transistor of memory cells 12b
and 12c.

[0100] Notably, in this example embodiment, memory cells 12a and 12d are
maintained at logic low (or logic "0") by applying an inhibit control
signal to the drain region of each memory cell 12a and 12d. For example,
applying 0 v to the drain regions of memory cells 12a and 12d (via bit
lines 32j and 32j+4) inhibits writing logic high or logic "1"
into memory cells 12a and 12d during the selective write operation for
memory cells 12b and 12c.

[0101] A "holding" operation or condition may be used for the other memory
cells in memory cell array 10 to minimize and/or reduce the impact of the
write operation for memory cells 12a-12d connected to word line 28i.
With reference to FIGS. 24 and 25, in one embodiment, a holding voltage
is applied to the gates of the transistors of other memory cells of
memory cell array 10 (for example, each memory cell connected to word
lines 28i+1, 28i+2, 28i+3, and 28i+4). In one example
embodiment, a holding voltage of -1.2 v is applied to the gate of each
transistor of the memory cells connected to word lines 28i+1,
28i+2, 28i+3, and 28i+4. In this way, the impact of the
write operation of memory cells 12a-12d (which are connected to word line
28i) on the other memory cells of memory cell array 10 is minimized
and/or reduced.

[0102] A selected row of memory cells may be read by applying read control
signals to the associated word line 28 and associated source lines 30 and
sensing a signal (voltage and/or current) on associated bit lines 32. In
one example embodiment, with reference to FIG. 26, memory cells 12a-12d
are read by applying (i) -1.0 v to the gate (via word line 28i),
(ii) 0 v to the source region (via source line 30) and (iii) 2.5 v to the
drain region (via bit line 32j+1 and 32j+2). The data write and
sense circuitry 36 reads the data state of the memory cells 12a-12d by
sensing the response to the applied read control signals. In response to
the read control signals, memory cells 12a-12d generate a source current
which is representative of the data state of memory cells 12a-12d. In
this example, memory cells 12b and 12c (which were earlier programmed to
logic "1"), in response to the read control signals, generate a source
current which is considerably larger than any channel current. In
contrast, memory cells 12a and 12d (which were earlier programmed to
logic "0"), such control signals induce, cause and/or produce little to
no source current (for example, a considerable, substantial or
sufficiently measurable source current). The sense circuitry 36 senses
the data state using primarily and/or based substantially on the source
current.

[0103] Thus, in response to read control signals, the electrically
floating body transistor of each memory cell 12a-12d generates a source
current which is representative of the data state stored therein. The
data sensing circuitry in data write and sense circuitry 36 determines
the data state of memory cells 12a-12d based substantially on the source
current induced, caused and/or produced in response to the read control
signals. Notably, as mentioned above, a read operation may be performed
by applying other control signaling techniques.

[0104] Again, it may be advantageous to employ a "holding" operation or
condition for the other memory cells in memory cell array 10 to minimize
and/or reduce the impact of the read operation of memory cells 12a-12d.
With continued reference to FIG. 26, in one embodiment, a holding voltage
is applied to the gates of the transistors of other memory cells of
memory cell array 10 (for example, each memory cell connected to word
lines 28i+1, 28i+2, 28i+3, and 28i+4). In one example
embodiment, a holding voltage of -1.2 v is applied to the gate of each
transistor of the memory cells connected to word lines 28i+1,
28i+2, 28i+3, and 28i+4. In this way, the impact of the
read operation of memory cells 12a-12d (which are connected to word line
28i) on the other memory cells of memory cell array 10 is minimized
and/or reduced.

[0105] The programming and reading techniques described herein may be used
in conjunction with a plurality of memory cells arranged in an array of
memory cells. A memory array implementing the structure and techniques of
the present inventions may be controlled and configured including a
plurality of memory cells having a separate source line for each row of
memory cells (a row of memory cells includes a common word line). The
memory array may use any of the example programming, holding and/or
reading techniques described herein. The memory arrays may comprise
N-channel, P-channel and/or both types of transistors. Circuitry that is
peripheral to the memory array (for example, sense amplifiers or
comparators, row and column address decoders, as well as line drivers
(not illustrated herein)) may include P-channel and/or N-channel type
transistors. Where P-channel type transistors are employed as memory
cells in the memory array(s), suitable write and read voltages (for
example, negative voltages) are well known to those skilled in the art in
light of this disclosure.

[0106] The present inventions may be implemented in any electrically
floating body memory cell and memory cell array. For example, in certain
aspects, the present inventions are directed to a memory array, having a
plurality of memory cells each including an electrically floating body
transistor, and/or technique of programming data into one or more memory
cells of such a memory cell array. In this aspect of the inventions, the
data states of adjacent memory cells and/or memory cells that share a
word line may or may not be individually programmed.

[0107] With reference to FIGS. 23A and 23B, memory array 10 may comprise a
plurality of memory cells 12 of N-channel type, P-channel type and/or
both types of electrically floating body transistors. The memory array 10
includes a plurality of rows and columns (for example, in a matrix form)
of memory cells 12.

[0108] The circuitry which is peripheral to memory array 10 (for example,
data write and sense circuitry 36 (such as, for example, sense amplifiers
or comparators), memory cell selection and control circuitry 38 (such as,
for example, address decoders and word line drivers)) may include
P-channel type and/or N-channel type transistors. Where N-channel type
transistors or P-channel type transistors are employed as memory cells 12
in memory array(s) 10, suitable write voltages are known to those skilled
in the art.

[0109] As mentioned above, memory cells 12 (having electrically floating
body transistor 14) and memory cell array 10 of the present inventions
may be implemented in an integrated circuit device having a memory
portion and a logic portion (see, for example, FIG. 23A), or an
integrated circuit device that is primarily a memory device (see, for
example, FIG. 23B). Indeed, the present inventions may be implemented in
any device having one or more memory cells 12 (having electrically
floating body transistors) and/or memory cell arrays 10. For example,
with reference to FIG. 23A, an integrated circuit device may include
array 10, having a plurality of memory cells 12 (having electrically
floating body transistors), data write and sense circuitry, and memory
cell selection and control circuitry (not illustrated in detail). The
data write and sense circuitry writes data into and senses the data state
of one or more memory cells. The memory cell selection and control
circuitry selects and/or enables one or more predetermined memory cells
12 to be read by data sense circuitry during a read operation.

[0110] For example, the electrically floating body transistor, which
programmed (written to), controlled and/or read using the techniques of
the present inventions, may be employed in any electrically floating body
memory cell, and/or memory cell array architecture, layout, structure
and/or configuration employing such electrically floating body memory
cells. In this regard, an electrically floating body transistor, which
state is read using the techniques of the present inventions, may be
implemented in the memory cell, architecture, layout, structure and/or
configuration described and illustrated in the following U.S. patents and
non-provisional U.S. patent applications:

[0114] (4) U.S. Pat. No. 7,187,581, which was filed by Ferrant et al. on
Mar. 14, 2005 and entitled "Semiconductor Memory Device and Method of
Operating Same", and which is a divisional application of U.S. patent
application Ser. No. 10/840,009 (now abandoned);

[0119] Notably, the memory cells may be controlled (for example,
programmed or read) using any of the control circuitry described and
illustrated in the above-referenced eight (8) U.S. patents and patent
applications. For the sake of brevity, those discussions will not be
repeated; such control circuitry is incorporated herein by reference.
Indeed, all memory cell selection and control circuitry for programming,
reading, controlling and/or operating memory cells including electrically
floating body transistors, whether now known or later developed, are
intended to fall within the scope of the present inventions.

[0120] Moreover, the data write and data sense circuitry may include a
sense amplifier (not illustrated in detail herein) to read the data
stored in memory cells 12. The sense amplifier may sense the data state
stored in memory cell 12 using voltage or current sensing circuitry
and/or techniques. In the context of a current sense amplifier, the
current sense amplifier may compare the cell current to a reference
current, for example, the current of a reference cell (not illustrated).
From that comparison, it may be determined whether memory cell 12
contained logic high (relatively more majority carriers 34 contained
within body region 18) or logic low data state (relatively less majority
carriers 34 contained within body region 18). Such circuitry and
configurations thereof are well known in the art.

[0121] In addition, the present inventions may employ the reference
generation techniques (used in conjunction with the data sense circuitry
for the read operation) described and illustrated in U.S. patent
application Ser. No. 11/515,667, "Method and Circuitry to Generate a
Reference Current for Reading a Memory Cell, and Device Implementing
Same" filed Sep. 5, 2006 by Bauser, and claiming the benefit of U.S.
Provisional Patent Application Ser. No. 60/718,417, which was filed by
Bauser on Sep. 19, 2005, and entitled "Method and Circuitry to Generate a
Reference Current for Reading a Memory Cell Having an Electrically
Floating Body Transistor, and Device Implementing Same". The entire
contents of the U.S. patent application Ser. No. 11/515,667 are
incorporated herein by reference. Further, the present inventions may
also employ the read circuitry and techniques described and illustrated
in U.S. Pat. No. 6,912,150, which was filed by Portmann et al. on May 7,
2004, and entitled "Reference Current Generator, and Method of
Programming, Adjusting and/or Operating Same". The contents of U.S. Pat.
No. 6,912,150 are hereby incorporated by reference herein.

[0122] It should be further noted that while each memory cell 12 in the
example embodiments (described above) includes one transistor 14, memory
cell 12 may include two transistors, as described and illustrated in U.S.
Pat. No. 7,085,153, which was filed by Ferrant et al. on Apr. 22, 2004
and entitled "Semiconductor Memory Cell, Array, Architecture and Device,
and Method of Operating Same". The contents of U.S. Pat. No. 7,085,153
are hereby incorporated by reference herein.

[0123] Moreover, the present inventions may be components of or integrated
with multi-bit memory cell applications as described in U.S.
Non-Provisional patent application Ser. No. 11/703,429, which was filed
by Okhonin on Feb. 7, 2007, and entitled "Multi-Bit Memory Cell Having
Electrically Floating Body Transistor, and Method of Programming and
Reading Same" (U.S. Patent Application Publication No. 2007/0187775).

[0124] The electrically floating memory cells, transistors and/or memory
array(s) may be fabricated using well known techniques and/or materials.
Indeed, any fabrication technique and/or material, whether now known or
later developed, may be employed to fabricate the electrically floating
memory cells, transistors and/or memory array(s). For example, the
present inventions may employ silicon, germanium, silicon/germanium,
gallium arsenide or any other semiconductor material (whether bulk-type
or SOI) in which transistors may be formed. As such, the electrically
floating memory cells may be disposed on or in (collectively "on")
SOI-type substrate or a bulk-type substrate.

[0126] Memory array 10 (including SOI memory transistors) further may be
integrated with SOI logic transistors, as described and illustrated in
the Integrated Circuit Device Patent Applications. For example, in one
embodiment, an integrated circuit device includes memory section (having,
for example, partially depleted (PD) or fully depleted (FD) SOI memory
transistors 14) and logic section (having, for example, high performance
transistors, multiple gate transistors, and/or non-high performance
transistors (for example, single gate transistors that do not possess the
performance characteristics of high performance transistors).

[0127] Further, memory array(s) 10 may be comprised of N-channel,
P-channel and/or both types of transistors, as well as partially depleted
and/or fully depleted type transistors. For example, circuitry that is
peripheral to the memory array (for example, sense amplifiers or
comparators, row and column address decoders, as well as line drivers
(not illustrated herein)) may include FD-type transistors (whether
P-channel and/or N-channel type). Alternatively, such circuitry may
include PD-type transistors (whether P-channel and/or N-channel type).
There are many techniques to integrate both PD and/or FD-type transistors
on the same substrate (see, for example, U.S. Pat. No. 7,061,050, which
was filed by Fazan et al. on Feb. 18, 2004 and entitled "Semiconductor
Device"). All such techniques, whether now known or later developed, are
intended to fall within the scope of the present inventions. Where
P-channel type transistors are employed as memory cells 12 in the memory
array(s), suitable write and read voltages (for example, negative
voltages) are well known to those skilled in the art in light of this
disclosure.

[0128] Notably, electrically floating body transistor 14 may be a
symmetrical or non-symmetrical device. Where transistor 14 is
symmetrical, the source and drain regions are essentially
interchangeable. However, where transistor 14 is a non-symmetrical
device, the source or drain regions of transistor 14 have different
electrical, physical, doping concentration and/or doping profile
characteristics. As such, the source or drain regions of a
non-symmetrical device are typically not interchangeable. This
notwithstanding, the drain region of the electrically floating N-channel
transistor of the memory cell (whether the source and drain regions are
interchangeable or not) is that region of the transistor that is
connected to the bit line/sense amplifier.

[0129] Aspects of the present inventions described herein, and/or
embodiments thereof, may include a semiconductor device comprising one or
more of: a body region configured to be electrically floating; a gate
disposed over a first portion of the body region; a source region
adjoining a second portion of the body region, the second portion
adjacent the first portion and separating the source region from the
first portion; and a drain region adjoining a third portion of the body
region, the third portion adjacent the first portion and separating the
drain region from the first portion.

[0130] The device of an embodiment includes a first voltage coupled to the
gate. The first voltage may cause minority carriers to accumulate in the
first portion of the body region.

[0131] The minority carriers that may accumulate in an embodiment
accumulate at a surface region of the first portion of body region that
is juxtaposed or near a gate dielectric which is disposed between the
gate and the first portion of the body region.

[0132] The region of the device of an embodiment that includes the
minority carriers is disconnected from the source region by the second
portion of the body region.

[0133] The region of the device of an embodiment that includes the
minority carriers is disconnected from the drain region by the third
portion of the body region.

[0134] The device of an embodiment includes a first potential difference
coupled between the source and the drain, the first potential difference
generating source current as a result of impact ionization induced by the
minority carriers.

[0135] The device of an embodiment includes a second voltage coupled to
the gate after and instead of the first voltage, the second voltage
causing an accumulation of majority carriers in the first portion of the
body region, wherein the majority carriers result in the first data state
which is representative of a first charge in the body region.

[0136] The device of an embodiment includes a second potential difference
coupled between the source and the drain, the second potential difference
resulting in a second data state which is representative of a second
charge in the body region.

[0137] The device of an embodiment includes an insulating layer disposed
between the gate and the body region.

[0138] The body region of the device of an embodiment includes a first
type of semiconductor material.

[0139] The source region and drain region of the device of an embodiment
includes a second type of semiconductor material.

[0140] The source region of the device of an embodiment includes a lightly
doped region.

[0141] The source region of the device of an embodiment includes a highly
doped region.

[0142] The source region of the device of an embodiment includes a lightly
doped region and a highly doped region.

[0143] The drain region of the device of an embodiment includes a lightly
doped region.

[0144] The drain region of the device of an embodiment includes a highly
doped region.

[0145] The drain region of the device of an embodiment includes a lightly
doped region and a highly doped region.

[0146] Aspects of the present inventions described herein, and/or
embodiments thereof, may include a semiconductor device comprising one or
more of: a gate; a body region partially disposed under the gate and
electrically floating; and a source region and a drain region adjacent
the body region, wherein one or more of the source region and the drain
region include a doped region shaped so that a farthermost boundary of
the doped region is separated from a portion of the body region
underlying the gate.

[0147] Aspects of the present inventions described herein, and/or
embodiments thereof, may include a semiconductor device comprising one or
more of: a gate; a body region configured as an electrically floating
body, the body region configured so that material forming the body region
extends beyond at least one lateral boundary of the gate; and a source
region and a drain region adjacent the body region.

[0148] Aspects of the present inventions described herein, and/or
embodiments thereof, may include a transistor comprising one or more of:
a floating body region on a insulating substrate; a gate disposed over a
portion of the floating body region; and a source region and a drain
region, wherein a doping profile of one or more of the source and the
drain region is configured to prevent formation of a contiguous current
channel extending between the source region and the drain region through
the floating body region.

[0149] Aspects of the present inventions described herein, and/or
embodiments thereof, may include a method for forming a transistor,
comprising one or more of: forming a semiconductor on an insulator;
forming an insulating layer and a gate over a first portion of the
semiconductor; forming spacers over a second portion and a third portion
of the semiconductor, the spacers adjoining the insulating layer, wherein
the first portion, second portion, and third portion form a floating body
region; forming a source region by implanting an impurity into a fourth
portion of the semiconductor after forming the spacers, the fourth
portion adjacent the second portion; and forming a drain region by
implanting the impurity into a fifth portion of the semiconductor after
forming the spacers, the fifth portion adjacent the third portion.

[0150] The body region formed under the method of forming a transistor of
an embodiment comprises a first type of semiconductor material.

[0151] The source region and drain region formed under the method of
forming a transistor of an embodiment each comprise a second type of
semiconductor material that is different from the first type.

[0152] Implanting the impurity into the fourth portion under the method of
forming a transistor of an embodiment includes implanting to form a
lightly doped source region.

[0153] Implanting the impurity into the fourth portion under the method of
forming a transistor of an embodiment includes implanting to form a
highly doped source region.

[0154] Implanting the impurity into the fourth portion under the method of
forming a transistor of an embodiment includes implanting to form a
source region that includes both a lightly doped source portion and a
highly doped source portion.

[0155] Implanting the impurity into the fifth portion under the method of
forming a transistor of an embodiment includes implanting to form a
lightly doped drain region.

[0156] Implanting the impurity into the fifth portion under the method of
forming a transistor of an embodiment includes implanting to form a
highly doped drain region.

[0157] Implanting the impurity into the fifth portion under the method of
forming a transistor of an embodiment includes implanting to form a drain
region that includes both a lightly doped drain portion and a highly
doped drain portion.

[0158] Aspects of the present inventions described herein, and/or
embodiments thereof, may include a method for forming an integrated
circuit device, the method comprising one or more of: forming a
semiconductor on an insulator; forming an insulating layer and a gate
over a first portion of the semiconductor; forming spacers over a second
portion and a third portion of the semiconductor, the spacers adjoining
the insulating layer, wherein the first portion, second portion, and
third portion form a floating body region; forming a source region by
implanting an impurity into a fourth portion of the semiconductor after
forming the spacers, the fourth portion adjacent the second portion; and
forming a drain region by implanting the impurity into a fifth portion of
the semiconductor after forming the spacers, the fifth portion adjacent
the third portion.

[0159] Aspects of the present inventions described herein, and/or
embodiments thereof, may include a method for forming a semiconductor
device, the semiconductor device produced by the method comprising one or
more of: a body region configured to be electrically floating; a gate
disposed over a first portion of the body region; a source region
adjoining a second portion of the body region, the second portion
adjacent the first portion and separating the source region from the
first portion; and a drain region adjoining a third portion of the body
region, the third portion adjacent the first portion and separating the
drain region from the first portion.

[0160] Aspects of the present inventions described herein, and/or
embodiments thereof, may include an integrated circuit device comprising
one or more of: a memory cell including a transistor, the transistor
comprising one or more of a body region configured to be electrically
floating, a gate disposed over a first portion of the body region, a
source region adjoining a second portion of the body region, the second
portion adjacent the first portion and separating the source region from
the first portion, and a drain region adjoining a third portion of the
body region, the third portion adjacent the first portion and separating
the drain region from the first portion; wherein the memory cell includes
a first data state representative of a first charge in the first portion
of the body region, wherein the memory cell includes a second data state
representative of a second charge in the first portion of the body
region; data write circuitry coupled to the memory cell, the data write
circuitry configured to apply first write control signals to the memory
cell to write the first data state and second write control signals to
the memory cell to write the second data state, wherein, in response to
first write control signals, the electrically floating body transistor
generates a first source current which substantially provides the first
charge in the first portion of the body region.

[0161] The first write control signals of the integrated circuit device of
an embodiment cause, provide, produce and/or induce the first source
current.

[0162] The first write control signals of the integrated circuit device of
an embodiment include a signal applied to the gate and a signal applied
to the source region, wherein the signal applied to the gate includes a
first voltage having a first amplitude and a second voltage having a
second amplitude.

[0163] The first write control signals of the integrated circuit device of
an embodiment include a signal applied to the gate and a signal applied
to the drain region, wherein the signal applied to the gate includes a
first voltage having a first amplitude and a second voltage having a
second amplitude.

[0164] The first write control signals of the integrated circuit device of
an embodiment include a potential difference applied between the source
region and the drain region.

[0165] The first write control signals of the integrated circuit device of
an embodiment include a signal applied to the gate, wherein the signal
applied to the gate includes a first voltage having a first amplitude and
a second voltage having a second amplitude.

[0166] The first write control signals of the integrated circuit device of
an embodiment include a signal applied to the gate, a signal applied to
the source region, and a signal applied to the drain region to cause,
provide, produce and/or induce the first source current, wherein one or
more of: the signal applied to the source region includes a first voltage
having a first amplitude; the signal applied to the drain region includes
a second voltage having a second amplitude; and the signal applied to the
gate includes a third voltage having a third amplitude and a fourth
voltage having a fourth amplitude.

[0167] The first write control signals of the integrated circuit device of
an embodiment include a first potential difference applied between the
source region and the drain region and a signal applied to the gate that
includes a first voltage, wherein the first write control signals may
cause, provide, produce and/or induce an accumulation of minority
carriers in the first portion of the body region.

[0168] The minority carriers of the integrated circuit device of an
embodiment accumulate at a surface region of the first portion of body
region that is juxtaposed or near a gate dielectric which is disposed
between the gate and the first portion of the body region.

[0169] The minority carriers of the integrated circuit device of an
embodiment accumulate at a surface region of the first portion of the
body region, wherein the surface region is disconnected from the source
region by the second portion of the body region.

[0170] The minority carriers of the integrated circuit device of an
embodiment accumulate at a surface region of the first portion of the
body region, wherein the surface region is disconnected from the drain
region by the third portion of the body region.

[0171] The first write control signals of the integrated circuit device of
an embodiment cause, provide, produce and/or induce source current in the
body region as a result of impact ionization induced by the minority
carriers.

[0172] The signal applied to the gate of the integrated circuit device of
an embodiment temporally changes to a second voltage that causes,
provides, produces and/or induces an accumulation of majority carriers in
the first portion of the body region, wherein the majority carriers
result in the first data state.

[0173] The second write control signals of the integrated circuit device
of an embodiment include a second potential difference applied between
the source region and the drain region and a signal applied to the gate
that includes the first voltage, wherein the second write control signals
prevent the first data state from being written into the first portion of
the body transistor.

[0174] The second potential difference of the integrated circuit device of
an embodiment is relatively less than the first potential difference.

[0175] The integrated circuit device of an embodiment comprises data sense
circuitry coupled to the memory cell and configured to sense the data
state of the memory cell, wherein, in response to read control signals
applied to the memory cell, the transistor generates a second source
current which is representative of the data state of the memory cell,
wherein the data sense circuitry determines the data state of the memory
cell at least substantially based on the second source current.

[0176] The read control signals of the integrated circuit device of an
embodiment include a signal applied to the gate, source region, and drain
region to cause, force and/or induce the source current which is
representative of the data state of the memory cell.

[0177] The read control signals of the integrated circuit device of an
embodiment include a first potential difference applied between the
source region and the drain region.

[0178] The signal applied to the gate region of the integrated circuit
device of an embodiment includes a negative voltage pulse.

[0179] Aspects of the present inventions described herein, and/or
embodiments thereof, may include an integrated circuit device comprising
one or more of: a memory cell array including one or more of a plurality
of word lines, plurality of source lines, plurality of bit lines, and
plurality of memory cells arranged in a matrix of rows and columns;
wherein each memory cell includes a transistor comprising one or more of
a body region configured to be electrically floating, a gate disposed
over a first portion of the body region, the gate coupled to an
associated word line, a source region adjoining a second portion of the
body region, the second portion adjacent the first portion and separating
the source region from the first portion, the source region coupled to an
associated source line, and a drain region adjoining a third portion of
the body region, the third portion adjacent the first portion and
separating the drain region from the first portion, the drain region
coupled to an associated bit line, wherein each memory cell includes a
first data state representative of a first charge in the first portion of
the body region, wherein each memory cell includes a second data state
representative of a second charge in the first portion of the body
region, wherein the source region of each memory cell of a first row of
memory cells is connected to a first source line; data write circuitry
coupled to the memory cells of the first row of memory cells, the data
write circuitry configured to apply first write control signals to memory
cells of the first row of memory cells to write the first data state and
second write control signals to memory cells of the first row of memory
cells to write the second data state, wherein, in response to first write
control signals applied to at least a portion of the memory cells of the
first row of memory cells, the electrically floating body transistor of
each memory cell of the portion of the memory cells of the first row of
memory cells generates a first source current which at least
substantially provides the first charge in the first body region of the
electrically floating body transistor of the portion of the memory cells
of the first row of memory cells.

[0180] The source region of each memory cell of a second row of memory
cells of the integrated circuit device of an embodiment is connected to
the first source line.

[0181] The integrated circuit device of an embodiment comprises one or
more of: the source region of each memory cell of a second row of memory
cells connected to a second source line; the source region of each memory
cell of a third row of memory cells connected to a second source line,
wherein the second and third rows of memory cells are adjacent to the
first row of memory cells.

[0182] The first write control signals of the integrated circuit device of
an embodiment cause, provide, produce and/or induce the first source
current.

[0183] The first write control signals of the integrated circuit device of
an embodiment include a signal applied to the gate and a signal applied
to the source region, wherein the signal applied to the gate includes a
first voltage having a first amplitude and a second voltage having a
second amplitude.

[0184] The first write control signals of the integrated circuit device of
an embodiment include a signal applied to the gate and a signal applied
to the drain region, wherein the signal applied to the gate includes a
first voltage having a first amplitude and a second voltage having a
second amplitude.

[0185] The first write control signals of the integrated circuit device of
an embodiment include a potential difference applied between the source
region and the drain region.

[0186] The first write control signals of the integrated circuit device of
an embodiment include a signal applied to the gate, wherein the signal
applied to the gate includes a first voltage having a first amplitude and
a second voltage having a second amplitude.

[0187] The data write circuitry of the integrated circuit device of an
embodiment, prior to applying the first write control signals, applies
the second write control signals to all of the memory cells of the first
row of memory cells to write the second data state therein.

[0188] The data write circuitry of the integrated circuit device of an
embodiment at least substantially simultaneously applies one or more of:
the first write control signals to the portion of the memory cells of the
first row of memory cells to write the first data state therein; and the
second write control signals to the other portion of the memory cells of
the first row of memory cells to write the second data state therein.

[0189] The first write control signals of the integrated circuit device of
an embodiment include a signal applied to the gate, a signal applied to
the source region, and a signal applied to the drain region of one or
more memory cells of the first row of memory cells to cause, provide,
produce and/or induce the first source current, wherein one or more of:
the signal applied to the source region includes a first voltage having a
first amplitude; the signal applied to the drain region includes a second
voltage having a second amplitude; and the signal applied to the gate
includes a third voltage having a third amplitude and a fourth voltage
having a fourth amplitude.

[0190] The first write control signals of the integrated circuit device of
an embodiment include a first potential difference applied between the
source region and the drain region and a signal applied to the gate of
one or more memory cells of the first row of memory cells that includes a
first voltage, wherein the first write control signals may cause,
provide, produce and/or induce an accumulation of minority carriers at a
surface region of the first portion of the body region.

[0191] The surface region of the first portion of body region of the
integrated circuit device of an embodiment is juxtaposed or near a gate
dielectric which is disposed between the gate and the first portion of
the body region.

[0192] The surface region of the integrated circuit device of an
embodiment is disconnected from the source region by the second portion
of the body region.

[0193] The surface region of the integrated circuit device of an
embodiment is disconnected from the drain region by the third portion of
the body region.

[0194] The first write control signals of the integrated circuit device of
an embodiment cause, provide, produce and/or induce source current in the
body region as a result of impact ionization induced by the minority
carriers.

[0195] The signal applied to the gate of the integrated circuit device of
an embodiment temporally changes to a second voltage that causes,
provides, produces and/or induces an accumulation of majority carriers in
the body region, wherein the majority carriers result in the first data
state.

[0196] The integrated circuit device of an embodiment comprises data sense
circuitry coupled to each memory cell of the plurality of memory cells
and configured to sense the data state of the memory cells, wherein, in
response to read control signals applied to the memory cells, the
transistor of each memory cell generates a second source current which is
representative of the data state of the memory cell, wherein the data
sense circuitry determines the data state of the memory cell at least
substantially based on the second source current.

[0197] The read control signals of the integrated circuit device of an
embodiment include a signal applied to the gate, source region, and drain
region to cause, force and/or induce the source current which is
representative of the data state of the memory cell.

[0198] The read control signals of the integrated circuit device of an
embodiment include a first potential difference applied between the
source region and the drain region.

[0199] The signal applied to the gate region of the integrated circuit
device of an embodiment includes a negative voltage pulse.

[0200] There are many inventions described and illustrated herein. While
certain embodiments, features, attributes and advantages of the
inventions have been described and illustrated, it should be understood
that many others, as well as different and/or similar embodiments,
features, attributes and advantages of the present inventions, are
apparent from the description and illustrations. As such, the
embodiments, features, attributes and advantages of the inventions
described and illustrated herein are not exhaustive and it should be
understood that such other, similar, as well as different, embodiments,
features, attributes and advantages of the present inventions are within
the scope of the present inventions.

[0201] As mentioned above, the illustrated/example voltage levels to
implement the read and write operations are merely examples. The
indicated voltage levels may be relative or absolute. Alternatively, the
voltages indicated may be relative in that each voltage level, for
example, may be increased or decreased by a given voltage amount (for
example, each voltage may be increased or decreased by 0.1, 0.15, 0.25,
0.5, 1 volt) whether one or more of the voltages (for example, the
source, drain or gate voltages) become or are positive and negative.

[0202] The illustrated/example voltage levels and timing to implement the
write and read operations are merely examples. In this regard, in certain
embodiments, the control signals increase the potential of electrically
floating body region of the transistor of the memory cell which "turns
on" or produces a source current in the transistor. In the context of a
write operation, the source current generates majority carriers in the
electrically floating body region which are then stored. In the context
of a read operation, the data state may be determined primarily by,
sensed substantially using and/or based substantially on the source
current that is responsive to the read control signals and significantly
less by the interface channel current component, which is less
significant and/or negligible relatively to the bipolar component.

[0203] As mentioned above, each of the aspects of the present inventions,
and/or embodiments thereof, may be employed alone or in combination with
one or more of such aspects and/or embodiments. For the sake of brevity,
those permutations and combinations will not be discussed separately
herein. As such, the present inventions are neither limited to any single
aspect (nor embodiment thereof), nor to any combinations and/or
permutations of such aspects and/or embodiments.

[0204] Moreover, the above embodiments of the present inventions are
merely example embodiments. They are not intended to be exhaustive or to
limit the inventions to the precise forms, techniques, materials and/or
configurations disclosed. Many modifications and variations are possible
in light of the above teaching. It is to be understood that other
embodiments may be utilized and operational changes may be made without
departing from the scope of the present inventions. As such, the
foregoing description of the example embodiments of the inventions has
been presented for the purposes of illustration and description. Many
modifications and variations are possible in light of the above teaching.
It is intended that the scope of the inventions not be limited solely to
the description above.