the following questions might be simple, but I'm not getting the answer by myself.

Suppose that you have three processes (A, B and C) running on the SCC on different cores. B and C send messages to A.

The messages have a size of two bytes. The senders will write in different locations of A's MPB. Let's say, B writes at address 0x0 and C writes at address 0x2. The message from B arrives at the MPB of A just before the message from C does.

Does A get the correct messages from both senders when reading from the MPB (including MPBT cache invalidate)? Or can the message from B be overwritten by C on some way?

(Remark: B and C are not sending the messages in multiples of cachelines)