... GND or VCC. Refer to Section 7.7 for more information. This pin is latched to input during a power on or reset condition. Pull high to set the RTL8201BL into MII mode operation. Set low for SNI mode. This pin can be directly connected to GND or VCC. In test mode, this pin is an output pin and ...

... LED Interface/PHY Address Config These five pins are latched into the RTL8201BL during power up reset to configure PHY address [0:4] used for MII management register interface. And then, in normal operation after initial reset, they are used as driving pins for status indication LED. The driving polarity, active low or active high, is determined by each latched status of the PHY address [4:0] during power-up reset ...

... Register Descriptions This section will describe definitions and usage for each of the registers available in the RTL8201BL. 6.1 Register 0 Basic Mode Control Register Address Name Description/Usage 0:<15> Reset This bit sets the status and control registers of the PHY in a default state. This bit is self-clearing. ...

... Reserved 1:<6> MF Preamble The RTL8201BL will accept management frames Suppression with preamble suppressed. The RTL8201BL accepts management frames without preamble. A Minimum of 32 preamble bits are required for the first SMI read/write transaction after reset. One idle bit is required between any two management transactions as per IEEE802 ...

... MII and Management Interface 7.1.1 Data Transition To set the RTL8201BL for MII mode operation, pull MII/SNIB pin high and properly set the ANE, SPEED, and DUPLEX pins. The MII (Media Independent Interface 18-signal interface which is described in IEEE 802.3u supplying a standard interface between PHY and MAC layer. This interface operates in two frequencies – ...

... FLP and wait for the link partner to respond. If the RTL8201BL receives FPL, then the auto-negotiation process will go on receives NLP, then the RTL8201BL will change to 10Mbps and half duplex mode receives a 100Mbps IDLE pattern, it will change to 100Mbps and half duplex mode. ...

... RPTR pin: Pull high to set the RTL8201BL into repeater mode. This pin is pulled low by default. Please refer to the section covering Repeater mode operation. 3) LDPS pin: Pull high to set the RTL8201BL into LDPS mode. This pin is pulled low by default. Please refer to the section covering Power Down mode and Link Down Power Saving. ...

... The RTL8201BL also supports the traditional 7-wire serial interface to cooperate with legacy MACs or embedded systems. To setup for this mode of operation, pull the MII/SNIB pin low and by doing so, the RTL8201BL will ignore the setup of the ANE and SPEED pins. In this mode, the RTL8201BL will set the default to work in 10Mbps and Half-duplex mode. But the RTL8201BL may also support full duplex mode operation if the DUPLEX pin has been pulled high ...

... The digital functions in this mode are still available which allows reacquisition of analog functions. 2) LDPS mode: Setting bit 12 of register pulling the LDPS pin high will put the RTL8201BL into LDPS (Link Down Power Saving) mode. In LDPS mode, the RTL8201BL will detect the link status to decide whether or not to turn off the transmit function ...

... Reset, and Transmit Bias(RTSET) The RTL8201BL can be reset by pulling the RESETB pin low for about 10ms, then pulling the pin high. It can also be reset by setting bit 15 of register and then setting it back to 0. Reset will clear the registers and re-initialize them, and the media interface will first disconnect and restart the auto-negotiation/parallel detection process ...

... FEFI is an alternative in-band signaling method which is composed of 84 consecutive ‘1’ followed by one ‘0’. From the point of view of the RTL8201BL, when this pattern is detected three times, Reg.1.4 is set, which means the transmit path (the Remote side’s receive path) has a problem. On the other hand, the incoming signal failure in causing a link OK will force the RTL8201BL to start sending this pattern, which in turn causes the remote side to detect a Far-End-Fault ...