Steve Wallach, a supercomputing legend, has participated in all 20 supercomputing shows and will be honored at the 2008 event with IEEE’s Seymour Cray Award for his “contribution to high-performance computing through design of innovative vector and parallel computing systems, notably the Convex mini-supercomputer series, a distinguished industrial career and acts of public service.”

The Seymour Cray Award, established in 1998 by the IEEE Computer Society Board of Governors, is given each year to individuals whose innovative contributions to high-performance computing systems best exemplify the creative spirit demonstrated by the late Seymour Cray. Steve Wallach will accept the award on November 20 at 1:30 p.m. at SC08. In addition he will give a plenary presentation, “Processor Architecture: Past, Present, Future” on Wednesday, November 19 at 1:30 p.m.

Those who know Steve Wallach know he is never short on opinions, especially when it comes to high performance computing. HPCwire talked to Wallach about everything from the future of HPC to his philosophy on building a successful HPC business.

HPCwire: First of all, congratulations on the award. What’s the best thing about winning the Cray award?

Steve Wallach: Everything. This is one of our industry’s greatest honors and I am deeply appreciative. To be associated with Seymour Cray, even in name only, is phenomenal. When I was notified, I was speechless. When the Cray 1 was announced, I read every piece of literature I could find on it. Seymour Cray and his designs had an effect on me, from a technical perspective, more than any other single event.

HPCwire: What’s the single biggest change you’ve seen in high-performance computing in the past 20 years?

Wallach: Perhaps the biggest change is the leveling of the uniprocessor performance. For all practical purposes, with the leveling off of clock frequency and memory bandwidth, the performance of ONE processor core has not changed much. Thus, we have multicore and massive parallelism. In fact, if one calculates the memory bandwidth per core (total memory bandwidth divided by the number of cores) it is DECREASING over time (normalized for peak gflops/core). I was a member of several government studies (National Academy of Engineering and Defense Science Board) that highlighted this leveling-off phenomena.

If we can’t access the data, we can’t operate on the data. This is one reason the industry is looking into ways to create semantically rich instructions. We know we can achieve more compute performance once the data is located within the core’s memory/register infrastructure.

HPCwire: You state in your plenary presentation that the past 40 years has taught us that the “system that is easier to program will always win.” Why is that?

Wallach: It boils down to two issues: cost of ownership and cost of development. At a recent Los Alamos Conference, it was pointed out that the cost of a programmer for one year is MORE than the cost of acquiring a TERAFLOP (peak performance) system. We need to address the software productivity issue. Of course this is one of the main objectives of DARPA’s HPCS (High Productivity Computer Systems) program.

We address both issues with our new servers. For example, the Convey overall system hardware and software architecture is identical to the x86, with coprocessor instructions appearing as extensions to the x86. Thus, programmers benefit from 100 percent productivity and portability.

The Convey coprocessor and the Intel x86 share a common cache-coherent physical and virtual address space. What this means is that the programmer does not need to manage the physical memory on the coprocessor nor explicitly move data back and forth between the x86 main memory and the coprocessor main memory.

Finally, the Convey-engineered, ANSI standard C, C++, and Fortran compiler automatically generates x86 and coprocessor instructions. Only one compiler is used, which is a significant contrast to various forms of attached accelerators that use two or more compilers. Existing applications can be compiled as is, and language subsets and/or non-standard extensions are not required to use the Convey coprocessor.

HPCwire: After all the history with parallel programming, why is HPC application development still so problematic?

Wallach: As Yogi Berra said: “It is déjà vu all over again.” Many of the issues discussed and analyzed today, existed 20 years ago. Many applications still have code that is 20 years old. Many applications still have “serial math” as their underpinning. And before we forget, our universities are really not teaching parallel programming. But now HPC applications are moving into a different application space called Data Intensive Computing. The computer centers at Google and Microsoft are substantially larger than what was once thought of as a “classic” HPC center. The industry needs to put more time and money into software productivity — and we are doing that. Just last March, for example, Microsoft and Intel announced a joint research initiative focusing on improving programming tools for multicore processing.

HPCwire: What’s happened to innovation in high-performance computing?

Wallach: It’s always there. HPC represents the leading — and sometimes the bleeding — edge of computing coupled with a variety of practical applications. Innovation also rules in the area of results gained from HPC. Without supercomputing power, we wouldn’t understand the human genome, travel to Mars, or — as our first customer the University of California, San Diego is experiencing — initiate unrestricted “blind searches” of massive protein databases to look for possible and unanticipated modifications in proteins. Modifications are particularly important for the study of diseases where multiple genes are involved, such as heart disease or cancer.

HPCwire: What is next for high performance computing?

Wallach: I believe there will be two major thrusts. One thrust will be in the software development area. We need new paradigms. At the recent Salishan Conference, this was pointed out over and over again. I expect we begin to have more widespread use of PGAS (Partitioned Global Address Space) languages. These languages are more productive than using MPI. And, with the introduction of Intel’s QPI, coupled with AMD’s HT, I expect PGAS to accelerate.

The other major thrust will be the widespread use of optical interconnects. We need more bisection bandwidth for the next generation MPPs. We also need more bandwidth for chip-to-chip connections. The telecommunications industry uses DWDM (dense wavelength division multiplexing) optics for all its long haul communications. Hopefully, a combination of Moore’s Law and material advances will bring this technology to centimeter-length busses.

HPCwire: What’s your philosophy of the HPC business and how has it changed over the years?

Wallach: It’s all about value for the customer — a philosophy that has stayed constant over the years. How do we make life easier for the customer? As an engineering company driven by engineers for engineers, we understand what makes one product difficult to work with and another one easy and we strive for easy. While our customers will probably buy our servers for the performance gains and price value, we’ll win their trust and enthusiasm by being the easiest to program.

We’ve focused on making it easy for programmers, developers and system administrators to use our product. We know that they will be the ones who ultimately have to make our solutions work. We actively consider ease-of-use in all our decisions knowing that we want them to be our most enthusiastic fans in the future.

HPCwire: What advice would you give to up-and-coming computer scientists?

Wallach: I am not sure I am the best person to answer this! I practice what I call “Eclectic Engineering.” I believe to be innovative and productive you need to know as much as possible about the entire application/problem before focusing on one particular aspect. So, even if you want to be a compiler writer, you should know how to connect a logic analyzer to a circuit board.

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