PCIe 3.1 PHY in TSMC(12/16nm, 28nm and 40nm)

M31 PCIe 3.1 PHY IP provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications. The PCIe 3.1 IP supports a complete range of PCIe 3.1 Base applications and is compliant with the PIPE 4.3 specification. The IP integrates high-speed mixed signal circuits to support PCIe 3.1 traffic at 8Gbps. It is backward compatible with PCIe 2.1 data rate at 5.0Gbps and PCIe 1.1 data rate at 2.5Gbps. With the supports for both TX and RX equalization techniques,the PCIe 3.1 IP can meet the requirements for different channel conditions.