If this is your first visit, be sure to
check out the FAQ by clicking the
link above. You may have to register
before you can post: click the register link above to proceed. To start viewing messages,
select the forum that you want to visit from the selection below.

CMOS commands

STANDARD CMOS

Date and Timedefinition: Allows user to set date and timeoptions: Any date and time the user feels like settingresults: None really, unless the user is stupid

IDE Channel settings/HDD Disk C typedefinition: Hard Disk C type refers to the number of the system's primary (master) hard drive. The default number is 47, which specify that the user must enter the drive specifications according to the HDD manual.options: Cyln (# of cylinders), Heads (# of heads), WPcom (Write precompensation, useless in modern computers), LZone (same as Wpcom), Sect (# of sectors per track), Size (Calculated from # of heads, cylinders, and sectors)results: Allows user to set hard drive manufacturer specifications about the hard drive to be installed in the system.

Primary Displaydefinition: Set type of display standard being used, and in the case of two video adapters, the primary one.options: VGA/PGA/EGA, black/white, Mono, Hercules, MDAresults: Depending on the type of video adapter or monitor being used, the above setting should be set in accordance with manufacturers specifications.

Halt on (post error displays)definition: User defines if the computer will display an error message if it encounters problems with the boot sequence. options: Enable/Disableresults: If enabled, the computer will display an error message

ADVANCED SMOST SETP/BIOS FEATURES

Above 1 MB Memory Testdefinition: Allow the user to set whether the system will check the memory above 1 MB for errors.options: Enable/Disableresults: Typically disabled for faster boot. Test also conducted in HIMEM.SYS driver for DOS 6.0 with XMS (Extended Memory Specification).

Memory parity error checkdefinition: Enabling this feature will allow the system to test for bit errors in the memory. Every byte will contain an extra bit to make the parity even or odd.options: Enable/Disableresults: If the memory fails the test then an error message will appear stating there is a RAM failure. Most modern memory chips are of such high quality as to make this setting obsolete.

System Boot sequencedefinition: Enables user to set the order of the drives in which the BIOS will search for an operating system.options: A, C, SCSI/EXT
C, A, SCSI/EXT
C, CD-ROM, A
CD-ROM, C, A
D, A, SCSI/EXT (only when you have at least 2 IDE hard disks)
E, A, SCSI/EXT (only when you have at least 3 IDE hard disks)
F, A, SCSI (only when you have 4 IDE hard disks)\
SCSI/EXT, A, C
SCSI/EXT, C, A
A, SCSI/EXT, C
LS/ZIP,Cresults: Each variation defines the order in which the BIOS will search for an OS.

Swap Floppy Drivedefinition: This option allows the user to switch the logical arrangement of the floppy drives without opening the case. options: Enable/Disableresults: Enable switches the mapped access to the two floppy drives in the system

Boot up Floppy Seekdefinition: Allows the user to set whether the BIOS searches for a floppy in the boot process. options: Enable/Disableresults: Enable searches for floppy, error message if not identified, detect number of tracks (40 or 80)

Boot up system speed (fast boot up)definition: This specifies the processor speed that the system will boot from. options: High, Lowresults: The HIGH setting is recommended for a faster boot process. If problems occur during the boot process the use the low setting.

External/Internal Cachedefinition: Define whether the L2 cache is external or internal, often in two different menu items.options: Enable/Disableresults: Depending on location of L2 cache on motherboard or chip, this setting will define that.

BIOS/SYSTEM/VIDEO ROM Shadowingdefinition: Allows the user to set whether Shadowing will be used to accelerate the BIOS read process.options: Enable/Disable results: BIOS are copied to the system RAM for quicker access. Improves the BIOS performance as it is read through a 64-bit DRAM bus as opposed to an 8-bit XT bus.

CHIPSET FEATURES/ADVANCED CHIPSET SETUP

AT Bus Clock Selectiondefinition: Gives a division of the CPU clock (System Clock) so it can reach the ISA-EISA bus clock. options: CLK/x, (or CLKIN/x and CLK2/x) CLK refers to the processor speed and x is an integer value like 2, 3, 4, 5, etc. results: This setting is for data exchange with ISA cards. The setting must be just right, too high or too low will adversely affect system performance.

Memory Read Wait Statedefinition: Determines how long the memory controller should wait before sending the read data to the data requester (CPU, peripherals, etc.) options: 0 Cycle, 1 Cycleresults: The 0 Cycle option provides optimal performance but may cause system instabilities. The 1 Cycle option causes the memory controller to wait one cycle before sending data. This is the default.

Memory Write Wait Statedefinition: This Determines how long the memory controller should wait before sending the write data to the requester.) options: 0 Cycle, 1 Cycleresults: The 0 Cycle option provides optimal performance but may cause system instabilities. The 1 Cycle option causes the memory controller to wait one cycle before sending data. This is the default.

Cache Read Optiondefinition: Referred to as SRAM Read wait state or Cache Read Hit Burst. Sets the specification of the number of clocks needed to load four 32-bit words into a CPU internal cache. Clocks per word.options: 2-1-1-1 (5 clocks to load 4 words), 3-1-1-1 (6 clocks), 3-2-2-2, 4-1-1-1, other simple integer values…results: The lower the computer can support the better.

IDE Multi Block Mode (IDE Block Mode)definition: This setting enables IDE drives to transfer several sectors of data per interrupt depending on the setting. options: Mode 0 (Standard mode transferring a single sector at a time), Mode 1 (no interrupts), Mode 2 (sectors are transferred in a single burst, Mode 3 (32-bit instructions with speeds up to 11.1 MBps, Mode 4 (up to 16.7 MBps), Mode 5 (up to 20 MBps)results: The more sectors transferred per interrupt will increase the Hard drive speed in respect to reading and writing data. Setting the too high can cause errors with the Com, serial, ports, etc.

DRAM lead off timing/Refresh Ratedefinition: This option allows the user to adjust the time needed before the data written to DRAM can be accessed and DRAM refresh intervals.options: 3,4 for Leadoff timing; 7.8 µsec, 15.6 µsec, 31.2 µsec, 64 µsec, 128 µsec for refresh rate.results: Set leadoff timing to 3 for faster access to DRAM or to 4 if there are system stability issues to be dealt with. The refresh rate determines the amount of rows and order in which the memory will refresh. Increasing the interval will increase performance unless taken to the extreme.

System BIOS Cacheabledefinition: Enables a user to speed access to the BIOS, which may not be necessary as the OS does not really need to access the system BIOS very much.options: Enable/Disableresults: Speeds access to the system BIOS by caching the system BIOS ROM at F0000h-FFFFFh

PCI Passive Release/PCI Delayed Transactiondefinition: Allows the user to define whether the chipset’s embedded 32-bit write buffer to support delayed transaction cyclesoptions: Enable/Disableresults: Enabling this allows the chipset's embedded 32-bit write buffer to support delayed transaction cycles This frees the PCI bus up to perform other duties while it is processing the ISA transaction, which is buffered. This is because ISA is much slower than PCI. It is recommended to keep this option Enabled.

PLUG and PLAY/PCI or PNP/PCI CONFIG

Latency Timer (PCI Clocks)definition: Allows control of the length of time each PCI device controls access of the bus before the next.options: 0 - 255results: The larger the value, the longer the PCI device can keep control of the bus, which improves bandwidth. Conversely, other PCI devices must wait until they have access.

Slot X Using INT#definition: Selects an INT# channel for a PCI Slot.options: A, B, C, D, Autoresults: #A is allocated automatically. Extra channels are assigned as necessitated by the card.

Xth available IRQdefinition: Allows selection or map of IRQ for one of the available INT#s. 1st available options: 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, 15, 1st available, NAresults: 1st available will select the first open IRQ, NA means the IRQ is assigned to the ISA bus and not available to PCI.

Peripheral Configurationdefinition: This sets the method by which the system receives the legacy card information.options: Use ICU, Use Setup Utilityresults: the Use ICU option if there is a P-n-P BIOS that can automatically detect and configure the system I/O devices. The Use Setup Utility option lets the user provide the system setup information to the BIOS by using setup utility software. If there is P-n-P, then its use is recommended.

Video Configurationdefinition: Set type of display standard being used, and in the case of two video adapters, the primary one.options: CGA/VGA/PGA/EGA, black/white, Mono, Hercules, MDAresults: Depending on the type of video adapter or monitor being used, the above setting should be set in accordance with manufacturers specifications.

HDD Block Modedefinition: Block mode enables data to be sent from multiple sectors at once instead of the previous single sector method. This greatly speeds up hard disk access. If disabled then only 512 bytes of data can be sent per interrupt which would slow down the system. This option should be enabled, but use caution with Windows NT because of problems with data corruption.options: Enable/Disableresults: The BIOS will automatically detect if your hard disk supports block transfers and configure the proper block transfer settings for it. Up to 64KB of data can be transferred per interrupt.

IDE Settings: PIO/UDMAdefinition: Allows the user to set the Programmed Input/Output or Ultra DMA mode for the master and slave devices. options: 0, 1, 2, 3, 4, Autoresults: Auto allows BIOS auto detection. Over clocking may result in a loss of data.

Dozedefinition: Amount of time before the system will reduce 80% of activity.options: specify amount of timeresults: Amount specified defines amount of idle time before the system reduces activity.

Standby (Stby)definition: Amount of time before the system will reduce 92% of activity.options: specify amount of timeresults: Amount specified defines amount of idle time before the system reduces activity.

Suspenddefinition: Amount of time after the system goes in the most inactive state possible, which is 99%. After this state, the system will require a warm up period so the CPU, hard disk and monitor may go online.options: specify amount of timeresults: Amount specified defines amount of idle time before the system reduces activity.

Power Button Overridedefinition: Allows user to decide how to boot the machine.options: Button Only, Keyboard 98, Hot Key, Mouse Left, Mouse Rightresults: Setting defines what button must be pressed to boot the machine.

SECURITY

Password-Supervisory/Userdefinition: Set a password that will be requested upon boot.options: No password/Disabled (Default), Enabled results: Improves security by giving the supervisor control over who accesses the system and their privileges (Read-Only, Read-Write, etc.) while they are using the system.

for me there no need to make huge changes in ur cmos. just use the default. still working. just set the boot and ide detecting. but very good work bro. must put much effort on in. very useful to most of us

Well.... do you have any idea about RAS Delay and CAS Delay. Also &quot;Memory Hole at 15-16M&quot;.

RAS: Row Addressing Strobe
CAS: Column Addressing Strobe

Those strobes are the way Memory is addressed by the cpu. The delay is the amount of ticks the cpu waits before sending the data on. The registers in the cpu must be full of said addressed data or errors will occur. The shorter the tick the faster the machine is able to refresh it's internal registers.

I think(not sure) that the 15-16 meg hole defines which address that is using for memory "Paging" a window that is used to address ranges outside the cpu's address bus.