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AR# 42756

Description

This article contains issues resolved in theVirtex-6 FPGA Integrated Block v2.4 Wrapper for PCI Express that are alsolisted in the readme.txt file that accompanies this version of the core. These are issues that were fixed as part of the update from the previous version of the core.

Solution

VHDL is not supported for the Root Port configuration at the time of this release.

Core Interface Signal change.

CR 579319

The transaction interface has been updated to use m_axis_rx_tkeep and s_axis_tx_tkeep, instead of m_axis_rx_tstrb and s_axis_tx_tstrb.

TLP Drop issue resolved - 8-lane Gen2 configuration only.

CR 593825

Issue resolved where a TLP presented at the User Transmit interface was getting dropped by the AXI bridge. The TLP would get dropped when there was a concurrent transmission of an internally generated TLP.

Issue resolved where the path of a file in the ".xise" file was incorrect causing the file to not get pulled in correctly.

GTX DFEDLYOVRD setting updated.

CR 594024

The DFEDLYOVRD setting in the GTX wrapper has been updated to be set to '0', per GTX User Guide recommendation.

Buffering Optimized for Bus Mastering applications with 512 byte MPS.

CR 591841

Issue resolved where the Example Design Simulation was not working when Buffering Optimized for Bus Mastering Applications option was selected, in conjunction with MPS setting of 512 bytes.

Revision History 01/18/2012 - Modified format to use a single AR for all known issues and referenced 45723 for all known issues. Any issue that was listed here is now in AR 45723. 12/14/2011 - Added 43531 12/02/2011 - Minor update to fix formatting for viewing in Documentation Center. 07/06/2011 - Initial Release.