Chipzilla chiefzilla admits tiny gates are really hard

Intel has surprised the IT world by changing its plans. Let's break down what's happened.

At IDF in 2013, Chipzilla boasted that it could get processors fabricated using a groundbreaking 10-nanometer process onto the market by 2015. It later pushed that date to 2016, and on Wednesday of this week it pushed the new chips back even further, to the second half of 2017.

That would have left an awkward gap in Intel's roadmap. The chipmaker is due to start rolling out its 14nm "Skylake" processors this autumn, and the 10nm "Cannonlake" chips were to be the follow-up. But with Cannonlake now due in 2017, Intel would have been left with nothing to show for 2016 – which explains why on Wednesday it promised to put out another 14nm series, this one codenamed "Kaby Lake."

This means we'll eventually have three families of 14nm Intel chips: Broadwell from 2014, Skylake in 2015, and Kaby Lake in late 2016. Then the 10nm Cannonlake parts will follow in 2017.

As usual, these are all just codenames. Once they reach the market, Broadwell parts are branded fifth-generation Intel Core chips (Core i3, i5, and i7) plus various flavors of Xeon, Core M, Pentium and Celeron. Similarly, Skylake parts will be branded sixth-generation Intel Core chips (Core i3, i5, and i7) and so on. We don't know the commercial branding for Cannonlake or Kaby Lake yet.

Tick-tock

The important point is that this episode is embarrassing for Intel, because it breaks the traditional "tick-tock" rhythm of its product release cycle. Typically, it first shrinks a microarchitecture to a new process size (the tick) and then it rolls out a new microarchitecture using that process size (the tock). There's usually a 12 to 18-month gap between the ticks and tocks.

Each new process size generally brings increased performance and lower power consumption, while each new microarchitecture is supposed to bring improvements and new features to the processor cores.

The most recent tick was Broadwell in 2014, which brought the Haswell microarchitecture to the 14nm process. The tock in 2015 will introduce the new Skylake microarchitecture, also at 14nm.

The next tick was supposed to be Cannonlake. Instead we'll get Kaby Lake, another 14nm series that neither introduces a new microarchitecture nor shrinks the process size. It's neither a tick nor a tock. It's a missed beat.

Getting down to 10nm isn't easy

The reason for the change of plans is because shrinking transistor gates down to 10nm and producing reliable chips that people will want to fit to their PCs and servers is hard.

"The lithography is continuing to get more difficult as you try and scale and the number of multi-pattern steps you have to do is increasing," he said, adding. "This is the longest period of time without a lithography node change."

The process shrink to 10nm will in fact be a major step for the industry. Generally speaking, the smaller the transistor gates, the higher you can safely drive the clock rate, and the lower the dynamic power consumption. But once you shrink past 14nm, current leakage becomes a problem, the chip starts sucking juice when it's idle, and you start to lose the theoretical benefits of the smaller process. Solving this problem is Intel's biggest challenge.

Sticking fins around the gates of the transistors mitigates this leakage somewhat, but creating these so-called Tri-Gate transistors likewise becomes more and more difficult the smaller you go. At one point a technique called extreme ultraviolet lithography (EUV) was thought to be the key to solving this problem to reach 10nm, but the technology is proving difficult to master, and Intel says it is not using EUV to craft its 10nm gates.

Meanwhile, IBM and its friends claim to have gone as low as 7nm, but their chips are lab experiments and are nowhere near production. Intel likewise says it still has its eyes on the 7nm prize, even though it has yet to conquer 10nm.

The effect on the industry

Effectively, Intel is hitting the brakes. It remains king of the semiconductor manufacturing world, yet it's having to slow its pace. Its boffins are battling to overcome the physical effects that kick in when you're trying to create electronic components 10 billionths of metre in size.

At worst, it is losing its lead over its chipmaker rivals, giving them time to catch up – although Intel seems confident they are running into the same problems it is.

The IT world expects processors with new features and improvements to performance and power consumption to arrive in line with Intel's two-year tick-tock rhythm. Wait a year for a tick, then a year later for the tock. The inserted pause, caused by the delays in getting 10nm working, will upset those purchasing and deployment plans, which could be a particular headache for customers who are planning to build out their data centers with thousands of new machines.

But Krzanich seemed confident that letting up on the gas, at least for now, is the right move – with the understanding that Intel will aim to get back onto its customary two-year cycle as soon as possible.

"Our customers said, 'Look, we really want you to be predictable. That's as important as getting to that leading edge'," Krzanich said during Wednesday's earnings call. "We chose to actually just go ahead and insert – since nothing else had changed – insert this third wave [with Kaby Lake]. When we go from 10-nanometer to 7-nanometer, it will be another set of parameters that we'll reevaluate this."

Intel's customers were leaning on the chip biz to confirm that it was on schedule, Krzanich said. Now we have our answer: it's not. ®

PS: Interestingly, Krzanich said Intel will "continue to support and develop [Altera's] ARM-based products," following his company's acquisition of the FPGA maker.