VivadoDesignSuiteStaticTimingAnalysisandXilinxDesignConstraints

This course offers detailed training on the Vivado® software tool flow, Xilinx design constraints (XDC), and static timing analysis (STA). Learn to use good FPGA design practices and all FPGA resources to advantage. Learn to fully and appropriately constrain your design by using industry-standard XDC constraints. Learn how the the Vivado IDE design database is structured and learn to traverse the design. Create appropriate timing reports to perform full STA and how to appropriately synthesize your design.

You will also learn the FPGA design best practices and skills to be successful using the Vivado Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado software. This course encapsulates this information with an UltraFast™ design methodology case study. The UltraFast design methodology checklist is also introduced.

Level

FPGA 3

Training Duration

3 days

Who Should Attend?

FPGA designers with intermediate knowledge of HDL and FPGA architecture, and some experience with the Xilinx Vivado Design Suite

Lab 2: Vivado IDE Clocks – Create complete XDC constraints for the clocking resources in a design. Implement the design and use the available clocking reports to verify results. Understand the first step in the Xilinx baselining recommendation.

Lab 3: I/O Constraints – Create input and output constraints for a source-synchronous design by using the Timing Constraints utility. You will also generate useful timing reports to verify the timing results. Understand the second step in the baselining recommendation.

Lab 4: Timing Exceptions – Use the Timing Constraints window to enter timing exceptions in the XDC format. You will also generate a useful timing report to verify the timing results. Understand the third and last step in the baselining recommendation.

Lab 5: Resets – Investigate the proper design and use of resets. Examine the impact of seeing a design built originally with asynchronous resets, having resets removed, and finally with synchronous resets only used where necessary.

Lab 6: SRL and DSP Inference – Evaluate the implementation results of a design that uses asynchronous resets and infers more dedicated hardware resources when resets are selectively removed from the design. You will also learn how to infer the DSP hardware resources for other common functions required by most FPGA designs.

Lab 7: Timing Closure and Design Conversion – Learn how a generic processor design was optimized for the 7 series device architecture with basic design changes that impacted the dedicated hardware usage, design speed, and the device utilization.