There have been many details made available at the Intel
Developer Forum about future Clarkdale desktop and
Arrandale mobile chips. Yields are very good and defect
density is steadily decreasing. They will be launched very soon
as part of the 32nm Westmere family.

Intel also revealed some details about production of chips using
the Sandy
Bridge architecture in 2010. The company's "tick-tock"
strategy of alternating annual process shrinks and new
microarchitecture has been quite effective. The Westmere die
shrink will be the next "tick", while Sandy Bridge
will be the next "tock". After that will come the 22nm
Ivy Bridge shrink in 2011, followed by the new Haswell
microarchitecture in 2012.

Intel showed off the first 32nm SRAM test chips at the IDF in
2007, and this year they showed us their first 22nm SRAM test
chips. With the 22nm process, Intel will be able to produce four
times the number of chips per wafer of the 45nm process, thus making
CPUs even cheaper once the process reaches mature yields.

DailyTech received not one, but two briefings on the 22nm
process by Mark Bohr, an Intel Senior Fellow and Director of Process
Architecture and Integration. He works in Intel's Logic Technology
Development group located at the D1D development fab in Hillsboro,
Oregon. His primary responsibility is to direct process development
for Intel's advanced logic technologies.

Intel is the first in the semiconductor industry to demonstrate
working 22nm circuits. Their 22nm shuttle chip contains not only SRAM
circuitry, but also logic and mixed signal transistors such as
phase lock loop (PLL) circuits. It is a 364 Mbit sized array
consisting of over 2.9 billion transistors and built using Intel's
third generation of High-K/Metal Gate technology. Shuttle chips
are used to test different types of logic during the development
phase, but these chips will have the same transistor and interconnect
features as on 22nm CPUs in the Ivy Bridge family.

Being able to demonstrate working 22nm SRAMs is an important
milestone towards being able to build working 22nm CPUs. There are
currently two types of SRAM cells that have been built so far. There
is a 0.092 square micron cell designed for high performance CPUs, and
a 0.108 square micron cell for for low voltage
applications such as Atom SoC designs.

Fab D1D is currently producing 32nm chips in the Westmere
family, but there is also a large portion dedicated to
producing Sandy Bridge and Ivy Bridge silicon. The
lessons learned will be used to develop the P1270 high
performance logic process for Ivy Bridge chips, but will also
lead to the development of the P1271 SoC process for 22nm Atom
chips. Intel plans to speed up the introduction of P1271 so that
it will be available just three months after P1270.

Intel is
planning to use 193nm immersion lithography for critical layers, and
double patterning for the rest. The company is unlikely to use EUV
(Extreme UltraViolet) tools even for the 15nm process in 2013, but
may consider them for use in the 11nm process that
will be introduced in 2015.

Intel CEO Paul Otellini has
repeatedly committed to expanding the company's sales in the SoC and
embedded markets as he thinks that will be the next major drivers for
Intel's growth. He thinks there is a market for billions of these
devices, but they must be small and cheap in order to be commercially
viable. In the future, we may end up with Atom chips being
produced first on the leading edge, with mobility, server, and
desktop designs coming later.

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