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Compiling and performance

SPARC Architecture 2011

With what appears to be minimal fanfare, an update of the SPARC Architecture has been released. If you ever look at SPARC disassembly code, then this is the document that you need to bookmark. If you are not familiar with it, then it basically describes how a SPARC processor should behave - it doesn't describe a particular implementation, just the "generic" processor. As with all revisions, it supercedes the SPARC v9 book published back in the 90s, having both corrections, and definitions of new instructions. Anyway, should be an interesting read

Thanks. Few questions:
* What are Fast Trap Handlers, how many cycles are these typically handled in? Any examples of what they're used for today?
* Do SPARCs have a fault-on-branch instruction of some sort?
* 9.2.1.2 Non Cacheable *with-no* side effect. It appears they are un-cached and incoherent, is that correct? Any idea what these are used for? Thread Local memory?

About

Darryl Gove is a senior engineer in the Solaris Studio team, working on optimising applications and benchmarks for current and future processors. He is also the author of the books:Multicore Application ProgrammingSolaris Application ProgrammingThe Developer's EdgeFree Download