9.24.1 M68HC11 and M68HC12 Options

The Motorola 68HC11 and 68HC12 version of as
have a few machine dependent options.

-m68hc11

This option switches the assembler into the M68HC11 mode. In this mode, the assembler only accepts 68HC11 operands and mnemonics. It produces code for the 68HC11.

-m68hc12

This option switches the assembler into the M68HC12 mode. In this mode, the assembler also accepts 68HC12 operands and mnemonics. It produces code for the 68HC12. A few 68HC11 instructions are replaced by some 68HC12 instructions as recommended by Motorola specifications.

-m68hcs12

This option switches the assembler into the M68HCS12 mode. This mode is similar to ‘-m68hc12
’ but specifies to assemble for the 68HCS12 series. The only difference is on the assembling of the ‘movb
’ and ‘movw
’ instruction when a PC-relative operand is used.

-mm9s12x

This option switches the assembler into the M9S12X mode. This mode is similar to ‘-m68hc12
’ but specifies to assemble for the S12X series which is a superset of the HCS12.

-mm9s12xg

This option switches the assembler into the XGATE mode for the RISC co-processor featured on some S12X-family chips.

This option controls the ABI and indicates to use a 16-bit integer ABI. It has no effect on the assembled instructions. This is the default.

-mlong

This option controls the ABI and indicates to use a 32-bit integer ABI.

-mshort-double

This option controls the ABI and indicates to use a 32-bit float ABI. This is the default.

-mlong-double

This option controls the ABI and indicates to use a 64-bit float ABI.

--strict-direct-mode

You can use the ‘--strict-direct-mode
’ option to disable the automatic translation of direct page mode addressing into extended mode when the instruction does not support direct mode. For example, the ‘clr
’ instruction does not support direct page mode addressing. When it is used with the direct page mode, as
will ignore it and generate an absolute addressing. This option prevents as
from doing this, and the wrong usage of the direct page mode will raise an error.

--short-branches

The ‘--short-branches
’ option turns off the translation of relative branches into absolute branches when the branch offset is out of range. By default as
transforms the relative branch (‘bsr
’, ‘bgt
’, ‘bge
’, ‘beq
’, ‘bne
’, ‘ble
’, ‘blt
’, ‘bhi
’, ‘bcc
’, ‘bls
’, ‘bcs
’, ‘bmi
’, ‘bvs
’,
‘bvs
’, ‘bra
’) into an absolute branch when the offset is out of the -128 .. 127 range. In that case, the ‘bsr
’ instruction is translated into a ‘jsr
’, the ‘bra
’ instruction is translated into a ‘jmp
’ and the conditional branches instructions are inverted and followed by a ‘jmp
’. This option disables these translations and as
will generate an error if a relative branch is out of range. This option does not affect the optimization associated to the ‘jbra
’, ‘jbsr
’ and ‘jbXX
’ pseudo opcodes.

--force-long-branches

The ‘--force-long-branches
’ option forces the translation of relative branches into absolute branches. This option does not affect the optimization associated to the ‘jbra
’, ‘jbsr
’ and ‘jbXX
’ pseudo opcodes.

--print-insn-syntax

You can use the ‘--print-insn-syntax
’ option to obtain the syntax description of the instruction when an error is detected.

--print-opcodes

The ‘--print-opcodes
’ option prints the list of all the instructions with their syntax. The first item of each line represents the instruction name and the rest of the line indicates the possible operands for that instruction. The list is printed in alphabetical order. Once the list is printed as
exits.

--generate-example

The ‘--generate-example
’ option is similar to ‘--print-opcodes
’ but it generates an example for each instruction instead.