CGO 2018: Call for Participation Registration is open at http://cgo.org/cgo2018/registration/ **Early registration ends on January 11th 11:59pm, 2018 any time on earth.** **CGO 2018 is also offering travel support for students attending US or non-US universities.** For more information see: http://cgo.org/cgo2018/travel-grants/

Call for Shadow PC Participation The 23rd International Conference on Architectural Support for Programming Languages and Operating Systems ASPLOS is organizing a shadow program committee for ASPLOS 2018. If you are interested in participating, please send an email to the shadow PC organizers: Johann Hauswald (University of Michigan, jahausw AT umich.edu) and Yunqi Zhang (University of Michigan, yunqi AT umich.edu) before July 31st, 2017. Please include a short paragraph describing your current research, areas of expertise, and publications: this will help us with selecting candidates and assigning papers for review. Feel free to reach out should you have any questions.

This tutorial will introduce the user to OpenPiton including how to use the framework to build different designs. OpenPiton is an open source framework designed to enable scalable architecture research prototypes from 1 core to 500 million cores. OpenPiton is the world’s first open source, general-purpose, multithreaded manycore processor and framework. OpenPiton leverages the industry hardened OpenSPARC T1 core with modifications and builds upon it with a scratch-built, scalable uncore creating a flexible, modern manycore design.

Tutorial: Microarchitecture Level Reliability Assessment: Throughput and Accuracy Early assessment of the vulnerability of microprocessor components to hardware faults can drive effective protection decisions. Microarchitecture-level simulators are employed for such early assessments and can deliver reliability reports for a large number of hardware structures taking into consideration the masking effects of the entire stack of hardware and software layers. Statistical fault injection at the microarchitecture level is a very accurate approach which, however, may suffer from low throughput if a statistically significant assessment is required. This tutorial focuses on recent advances delivered by the Computer Architecture Lab of the University of Athens in the area of microarchitecture level reliability assessment using statistical fault injection. We present GeFIN (Gem5-based Fault Injector) a state-of-the-art microarchitecture level fault injection framework built on Gem5 simulator. GeFIN supports massive and fast injection campaigns for all different types of faults (transient, permanent, intermittent) on arbitrary combinations of several dozens of microarchitectural components modeled in Gem5. We first present the baseline Gem5 engine as well as AVF (Architectural Vulnerability Factor) and FIT (Failures in Time) measurements reported by the tool which are reports fine-grained fault effects classifications. We also present two GeFIN add-ons designed to improve the throughput of the injections campaigns but preserve the accuracy of the reliability measurements. The first add-on is a set of speed-up methods on GeFIN individual runs themselves and the second add-on is MeRLiN a fault classification approach based on dynamic instruction profiling which aims at pruning the number of faults in extremely large fault lists. Both add-ons deliver large throughput improvements (several orders of magnitude) for comprehensive (and thus statistically significant) fault injection campaigns while they preserve the reported AVF measurements. The tutorial includes measurements for different microarchitectural configurations (corresponding to different CPU models), discussion about ACE analysis and fault injection at the microarchitecture level, discussion about CPU and GPU reliability assessment at the microarchitecture level as well as comparison between microarchitecture-level and register-transfer level fault injection on a commercial CPU model.

Tutorial on Hardware Architectures for Deep Neural Networks co-located with MICRO-50 Speakers: Joel Emer (Nvidia/MIT), Vivienne Sze (MIT), Yu-Hsin Chen (MIT) Deep neural networks (DNNs) are currently widely used for many AI applications including computer vision, speech recognition, robotics, etc. While DNNs deliver state-of-the-art accuracy on many AI tasks, it comes at the cost of high computational complexity. Accordingly, designing efficient hardware architectures for deep neural networks is an important step towards enabling the wide deployment of DNNs in AI systems. In this tutorial, we will provide an overview of DNNs, discuss the tradeoffs of the various architectures that support DNNs including CPU, GPU, FPGA and ASIC, and highlight important benchmarking/comparison metrics and design considerations. We will then describe recent techniques that reduce the computation cost of DNNs from both the hardware architecture and network algorithm perspective. Finally, we will discuss the different hardware requirements for inference and training.

The workshop on ‘Exploiting Accelerator Diversity for Cognitive Workloads’ will explore acceleration opportunities in existing and upcoming workflows, particularly in the cognitive domain. It will also explore the creation of a community & ecosystem around POWER9 acceleration technology for academics and industry practitioners. This workshop is co-located with the 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-2017).

PACT’2017 – Call for Participation – The purpose of PACT 2017 is to bring together researchers from architecture, compilers, applications and languages to present and discuss innovative research of common interest. We invite attendees to register for our exciting program this year consisting of many informative workshops/tutorials, leading industry keynotes and conference papers and posters.

The International Symposium on Low Power Electronics and Design (ISLPED) is the premier forum for presentation of innovative research in all aspects of low power electronics and design, ranging from process technologies and analog/digital circuits, simulation and synthesis tools, system-level design and optimization, to system software and applications.

The ACACES Summer School is a one week summer school for computer architects and tool builders working in the field of high performance computer architecture, compilation and embedded systems. The school aims at the dissemination of advanced scientific knowledge and the promotion of international contacts among scientists from academia and industry. A distinguishing feature of this Summer School is its broad scope ranging from low level technological issues to advanced compilation techniques and entrepreneurship. In the design of modern computer systems one has to be knowledgeable about architecture as well as about the quality of the code, and how to improve it. This summer school offers the ideal mix of the two worlds, both at the entry level and at the most advanced level.

Workshop on Trends In Machine-Learning: Perspective from ML Research and Industry in conjunction with ISCA 2017 Toronto, Canada June 25, 2017 Machine-Learning has now become a pervasive tool used throughout the industry. This trend, combined with the pDetails…

Tutorial on Hardware Architectures for Deep Neural Networks Speakers: Joel Emer (Nvidia/MIT), Vivienne Sze (MIT), Yu-Hsin Chen (MIT) Deep neural networks (DNNs) are currently widely used for many AI applications including computer vision, speech recognition, robotics, etc. While DNNs deliver state-of-the-art accuracy on many AI tasks, it comes at the cost of high computational complexity. Accordingly, designing efficient hardware architectures for deep neural networks is an important step towards enabling the wide deployment of DNNs in AI systems. In this tutorial, we will provide an overview of DNNs, discuss the tradeoffs of the various architectures that support DNNs including CPU, GPU, FPGA and ASIC, and highlight important benchmarking/comparison metrics and design considerations. We will then describe recent techniques that reduce the computation cost of DNNs from both the hardware architecture and network algorithm perspective. Finally, we will discuss the different hardware requirements for inference and training. More info at http://eyeriss.mit.edu/tutorial.html

You are cordially invited to the 10th annual IEEE International Symposium on Hardware Oriented Security and Trust (HOST). HOST 2017 will feature a rich one-week program. Major highlights include: 1. This year marks the 10th anniversary of HOST. 2. ForDetails…

The IEEE Symposium on Field Programmable Custom Computing Machines (FCCM) is the original and premier forum for presenting and discussing new research related to computing that exploits the unique features and capabilities of FPGAs and other reconfigurable hardware.

You are cordially invited to participate in the 10th Anniversary Edition of Cyber-Physical Systems Week (CPS Week). CPS Week is the premier event on Cyber-Physical Systems research. It brings together five top conferences (HSCC, ICCPS, IoTDI, IPSN, RTAS) and eleven workshops on cyber-physical systems research, in addition to competitions and various exhibitions from both industry and academia.

The 22nd ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS 2017) Xi’an, China, April 8–12, 2017 ASPLOS is the premier forum for multidisciplinary systems research spanning computer architecturDetails…

This tutorial will introduce the basic notions of quantum computing and will address the main challenges when building a large-scale quantum computer. The tutorial will provide hands-on exercises based on the QX simulator platform and will allow participants to understand what quantum circuits and quantum gates are.

We will be holding a Learning gem5 Tutorial and a gem5 coding sprint at HPCA 2017 on February 5th in Austin, TX. The morning will consist of a “Learning gem5” half-day course. In the afternoon, we invite all gem5 developers senior, junior, and new developers to a “coding sprint.”

The International Symposium on High-Performance Computer Architecture provides a high-quality forum for scientists and engineers to present their latest research findings in this rapidly-changing field. Authors are invited to submit papers on all aspects of high-performance computer architecture.

The International Symposium on Code Generation and Optimization (CGO) provides a premier venue to bring together researchers and practitioners working at the interface of hardware and software on a wide range of optimization and code generation techniques and related issues. The conference spans the spectrum from purely static to fully dynamic approaches, and from pure software-based methods to specific architectural features and support for code generation and optimization.

September 25, 2016
to September 27, 2016
in Providence, Rhode Island, USA

IISWC provides a high-quality international forum to bring together researchers and practitioners from academia and industry to discuss cutting-edge research on understanding and characterization of workloads that run on all types of computing systems. Whether they are smart phones and deeply embedded systems at the low end or massively parallel systems at the high end, the design of future computing machines can be significantly improved if we understand the characteristics of the workloads that are expected to run on them.

Workshop on In-Memory and In-Storage Computing with Emerging Technologies invites you to share your research and creative endeavors with your colleagues. Our program features 6 selected papers on a variety of subjects including computer architecture and algorithms based on resistive memory technologies such as memristors, RRAM, PCM, 3D Xpoint, STT-MRAM and others. Authors will present a wide range of potential applications including digital computing, non-volatile storage with processing capabilities, neuromorphic computing, etc. We will further discuss the use of emerging technologies as an enabler of the next generation of new architectures that address the major shortcomings of today’s conventional high-performance computing such as latency, energy, power efficiency and scalability.

The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to interdisciplinary research on on-chip, chip-scale, and multichip package scale communication technology, architecture, design methods, applications and systems. NOCS brings together scientists and engineers working on NoC innovations and applications from inter-related research communities, including computer architecture, networking, circuits and systems, packaging, embedded systems, and design automation.

The tutorial is a step to overcome the increasing barrier of entry for conducting mobile computer architecture research. We present a series of tools and infrastructures that enable computer system and architecture research in the mobile computing space. The tutorial will span three key components of mobile computing: software, hardware, and end-users.

This tutorial will introduce the user to OpenPiton including how to use the framework to build different designs. The tutorial will introduce the verification framework (Verilog simulation), how to synthesize an OpenPiton processor for a Xilinx FPGA board, it will demonstrate booting Linux on an FPGA version of OpenPiton, it will familiarize users with how to use the OpenPiton framework to target an ASIC tapeout, and it will show users how to configure and extend the OpenPiton architecture to enable architecture research. This tutorial will be hands-on so please bring a laptop.

May 12, 2016
to May 13, 2016
in University of North Carolina at Chapel Hill, USA

Applications are invited to a 1.5 day oral history workshop, to be held Thursday and Friday, May 12-13, 2016 at the University of North Carolina at Chapel Hill, North Carolina. The workshop will be led by Mary Marshall Clark, director of the Columbia Center for Oral History (CCOH)

EEE International Symposium on Performance Analysis of Systems and Software. The focus is on performance-related problems, solutions, methods and tools for software and system performance and power analysis and optimisation.

The International Symposium on High-Performance Computer Architecture provides a high-quality forum for scientists and engineers to present their latest research findings in this rapidly-changing field. HPCA-22 will be held in conjunction with the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP-2016) and the 14th International Symposium on Code Generation and Optimization (CGO-2016).

The CWWMCA Workshop brings together women and under-represented minorities in academia, industry, and government to promote the recruitment, retention and progression of women and under-represented groups with research interests in computer architecture.

In this hands-on, interactive tutorial, you will learn how to efficiently build accurate, run-time power models using real hardware platforms using a specially built software tool. Starting from the basics of how power is consumed in a modern system-on-chip through static and dynamic power in the underlying transistors, we show how activity, voltage and frequency affect the power consumption.

Hot Interconnects (HotI) is the premier international forum for researchers and developers of state- of-the-art hardware and software architectures and implementations for interconnection networks of all scales, ranging from multi-core on-chip interconnects to those within systems, clusters, data centers, and clouds. This yearly conference is attended by leaders in industry and academia, creating a wealth of opportunities to interact with individuals at the forefront of this field.

NAS provides a high-quality international forum to bring together researchers and practitioners from academia and industry to discuss cutting-edge research on networking, high-performance computer architecture, and parallel and distributed data storage technologies.

The 26th IEEE International Conference on Application-specific Systems, Architectures and Processors 2015 (ASAP 2015) takes place July 27-29, 2015 at the University of Toronto in Toronto, Canada. ASAP is a premiere IEEE conference covering all aspects of application-specific computing, including systems, architectures, processors, and design methodologies/tools.

Building prototype systems can be one of the best ways to validate assumptions, gain intuition about practical design issues, and provide platforms for future software research. While the research ideas behind these prototypes can be published in top-tier conferences, there are not many venues suitable for focusing on the actual prototype itself. At the same time, building an FPGA, ASIC, or full-custom computer architecture prototype is a non-trivial endeavor and requires a significant financial and time commitment. This workshop is intended as a forum for the builders in our community to share their practical on-the-ground experiences, to provide a status update on their progress, and to convey insights for those considering prototyping their ideas.

CARD 2015 presents three mini-panels consisting of three experts in the field, two as panelists and the third as a moderator/panelist. The purpose of this workshop is to serve as a forum in which experts in each field can debate the state of the field and future directions. The format is designed to quickly focus on areas of disagreement, rather than expounding on areas of agreement which, presumably, have ceased to be controversial, at least between the two panelists. The mini-panels are intended to help clarify the open issues of each topic and to discuss those open issues. The hope is that the workshop will be useful to a diverse audience from a graduate student looking for good thesis topic areas to a senior researcher who wants to hear the opinions of other area experts.

The International Symposium on Computer Architecture (ISCA) is the premier forum for new ideas and experimental results in computer architecture. ISCA is sponsored by ACM SIGARCH and IEEE Computer Society TCCA.

The International Symposium on Computer Architecture (ISCA) is the premier forum for new ideas and experimental results in computer architecture. This year ISCA will be held in the Oregon Convention Center in Portland, Oregon during June 13-17, 2015. Sponsored by ACM SIGARCH and IEEE TCCA.

WAX 2015 is a workshop on approximate computing, a research direction that asks how computer systems can be made better, faster, more efficient, and less complex by relaxing the requirement that they be exactly correct. Approximation arises from sources as diverse as sensors, machine learning algorithms, and big data applications. Approximate systems raise questions from across the system stack, from circuits to applications. WAX is avenue for discussion, debate, and brainstorming on all of these topics.

ANCS is the premier forum for presenting and discussing original research that explores the relationship between the algorithms and architectures of data communication networks and the hardware and software elements from which these networks are built. This includes both experimental and theoretical analysis. To recognize and foster the increasing importance of research into the co-design of computer and network systems, the conference also places an emphasis on systems issues arising from the interaction of computer and network architectures.

ASPLOS is the premier forum for multidisciplinary systems research spanning computer architecture and hardware, programming languages and compilers, operating systems and networking, as well as applications and user interfaces.

The 4th Annual Non-Volatile Memories Workshop (NVMW 2013) provides a unique showcase for outstanding research on solid state, non-volatile memories. It features a “vertically integrated”program that includes presentations on a wide range of topics spanning devices, data encoding, systems architecture, and applications.

NVMW provides a unique showcase for outstanding research on solid state, non-volatile memories. It features a “vertically integrated” program that includes presentations on devices, data encoding, systems architecture, and applications related to these exciting new data storage technologies.

February 7, 2015
to February 11, 2015
in San Francisco Bay Area, California, USA

HPCA is a premier annual computer architecture conference sponsored by the Computer Society of the Institute of Electrical and Electronics Engineers (IEEE CS). It will bring together researchers, academics, and industrial engineers from all over the world.

February 7, 2015
to February 11, 2015
in San Francisco Bay Area, California, USA

HPCA is a premier annual computer architecture conference sponsored by the Computer Society of the Institute of Electrical and Electronics Engineers (IEEE CS). It will bring together researchers, academics, and industrial engineers from all over the world.

The HiPEAC conference is the premier European forum for experts in computer architecture, programming models, compilers and operating systems for embedded and general-purpose systems. Associated workshops, tutorials, special sessions, several large poster sessions and an industrial exhibition will run in parallel with the conference. The three day event attracts about 500 delegates each year.

RISC-V (pronounced “risk-5”) is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education, but which we now hope will become a standard open architecture for industry implementations. RISC-V was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley, but has been made freely available open-source under the BSD license for anyone to use.

IEEE Micro will publish its yearly Micro’s Top Picks from Computer Architecture Conferences as its May / June 2015 issue. This issue collects some of this year’s most significant research papers in computer architecture based on novelty and potential for long-term impact. The community input website will be open between Dec 18, 2014 and Jan 17, 2015. Reviews will be anonymous to the authors but they will not be anonymous to the selection committee.

The International Symposium on Microarchitecture (MICRO) is the premier forum for the presentation and discussion of new ideas in microarchitecture, compilers, hardware/software interfaces, and design of advanced computing and communication systems.

This symposium is dedicated to the understanding and characterization of workloads that run on all types of computing systems. New applications and programming paradigms continue to emerge rapidly as the diversity and performance of computers increase. On one hand, improvements in computing technology are usually based on a solid understanding and analysis of existing workloads. On the other hand, computing workloads evolve and change with advances in microarchitecture, compilers, programming languages, and networking communication technologies. Whether they are smart phones and deeply embedded systems at the low end or massively parallel systems at the high end, the design of future computing machines can be significantly improved if we understand the characteristics of the workloads that are expected to run on them. This symposium will focus on characterizing and understanding emerging applications in consumer, commercial and scientific computing.

3D IC is emerging as a promising approach to extend Moore’s law, overcome pin bandwidth limitations, and improve digital platform density and cost beyond a single chip. 3D IC as a technology, however, also introduces a number of key design, methodological, implementation and technological challenges that must be overcome to become practical and cost-effective.

Computing Frontiers is a gathering for people to share and discuss such work, focusing on a wide spectrum of advanced technologies and radically new solutions relevant to the development of the whole spectrum of computer systems, from embedded to high-performance computing.

Future multi-core architectures will present a variety of challenges for system developers, such as non-cache-coherent memory, heterogeneous processing cores and the exploitation of novel architectural features. SFMA ’14 is a forum for researchers in the architecture, operating systems, language runtime and virtual machine communities to present and discuss their experiences with the new generation of highly-parallel hardware.

The 2014 IEEE International Symposium on Performance Analysis of Systems and Software is sponsored by the IEEE Computer Society’s Technical Committee on Internet, Technical Committee on Computer Architecture, and Technical Committee on Microprogramming and Microarchitecture.

The 5th Annual Non-Volatile Memories Workshop (NVMW 2014) provides a unique showcase for outstanding research on solid state, non-volatile memories. It features a “vertically integrated” program that includes includes presentations on a wide range of topics spanning devices, data encoding, systems architecture, and applications:

The emergence of cloud computing as a dominant computing platform highlights the need for practical and rigorous architectural evaluation of server systems. Such evaluation mandates the use of a variety of real-world server workloads, all of which are radically different from traditional desktop and scientific benchmarks.

The emergence of cloud computing as a dominant computing platform highlights the need for practical and rigorous architectural evaluation of server systems. Such evaluation mandates the use of a variety of real-world server workloads, all of which are radically different from traditional desktop and scientific benchmarks. Unfortunately, deep and complex software stacks of both conventional (e.g., OLTP, DSS) and emerging scale-out (e.g., Media Streaming, Web Search) server workloads make the evaluation process even harder and slower, postponing the adoption of realistic server benchmarks within the architectural community.

ASPLOS is the premier forum for multidisciplinary systems research spanning computer architecture and hardware, programming languages and compilers, and operating systems and networking. The program covers cross-cutting research spanning mobile systems to data centers, targeting diverse goals such as performance, energy efficiency, resiliency, and security.

ASPLOS is the premier forum for multidisciplinary systems research spanning computer architecture and hardware, programming languages and compilers, and operating systems and networking. The program covers cross-cutting research spanning mobile systems to data centers, targeting diverse goals such as performance, energy efficiency, resiliency, and security.

The International Symposium on Code Generation and Optimization (CGO) provides a premier venue to bring together researchers and practitioners working at the interface of hardware and software on a wide range of optimization and code generation techniques and related issues.

Established in 1992, ICPADS has been a major international forum in the parallel and distributed systems area. ICPADS 2013 will be held in Seoul, December 15-18, 2013. Seoul is a city of various culture and variation. There is a wide range of modern and fusion culture of the West and the East, along with cutting edge technology. The conference venue, COEX convention center is located at Gangnam district that is famous for a song, Gangnam Style, by Korean singer Psy. The conference provides an international forum for scientists, engineers, and users to exchange and share their experiences, ideas, and latest results on all aspects of parallel and distributed systems.

The International Symposium on Microarchitecture (MICRO) is the premier forum for the presentation and discussion of new ideas in microarchitecture, compilers, hardware/software interfaces, and design of advanced computing and communication systems. The goal of MICRO is to bring together researchers in the fields of microarchitecture, compilers, and systems for technical exchange. The MICRO community has enjoyed having close interaction between academic researchers and industrial designers — we aim to continue and strengthen this longstanding tradition at the 46th MICRO in Davis

The 8th IEEE International Conference on Networking, Architecture, and Storage (NAS 2013), June 17 – July 19, 2013, Xi’an, China, will serve as an international forum to bring together researchers and practitioners from academia and industry to discuss cutting-edge research on networking, high-performance computer architecture, and parallel and distributed data storage technologies. NAS 2013 will expose participants to the most recent developments in the interdisciplinary areas.

The ACACES Summer School is a one week summer school for computer architects and tool builders working in the field of high performance computer architecture, compilation and embedded systems. The school aims at the dissemination of advanced scientific knowledge and the promotion of international contacts among scientists from academia and industry. A distinguishing feature of this Summer School is its broad scope ranging from low level technological issues to advanced compilation techniques. In the design of modern computer systems one has to be knowledgeable about architecture as well as about the quality of the code, and how to improve it. This summer school offers the ideal mix of the two worlds, both at the entry level and at the most advanced level.

SYSTOR provides a forum for interaction across the systems and storage community: international, academic, and industrial, for both students and more established members. The program include high-quality experimental and practical research papers encompassing all aspects of computer systems, with an emphasis on storage.

The emergence of cloud computing as a dominant computing platform highlights the need for a common architectural evaluation basis of cloud server systems. CloudSuite is an on-going effort towards this end, aimed at providing a contemporary suite of benchmarks that represent popular scale-out cloud applications commonly found in today’s datacenters.

General-purpose GPUs (GPGPUs) are becoming prevalent in mainstream computing, and performance per watt has emerged as a more crucial evaluation metric than peak performance. As such, GPU architects require robust tools that will enable them to quickly explore new ways to optimize GPGPUs for energy efficiency. We propose a new GPGPU power model that is configurable, capable of cycle-level calculations, and carefully validated against real hardware measurements.

This tutorial will present attendees with the techniques and methodologies to leverage the SST/macro simulator and the Eiger performance modeling framework for modeling large scale applications on upcoming supercomputer hardware.

The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to interdisciplinary research on on-chip and chip-scale communication technology, architecture, design methods, applications and systems. NOCS brings together scientists and engineers working on NoC innovations and applications from inter-related research communities, including computer architecture, networking, circuits and systems, embedded systems, and design automation.

The IEEE International Symposium on Performance Analysis of Systems and Software provides a forum for sharing advanced academic and industrial research work focused on performance analysis in the design of computer systems and software.

The growing complexity and shrinking geometries of modern device technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching. Growing concern about intermittent errors, unstable storage cells, and the effects of aging are influencing system design. This workshop provides a forum for discussing current research and practice in system-level error management. Participants from industry and academia explore both current technologies and future research directions (including nanotechnology). SELSE is soliciting papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes.

Recently, there has been an explosive growth in Internet services, greatly increasing the importance of data center systems. Applications served from ìthe cloudî are driving data center growth and quickly overtaking traditional workstations. Although there are many analytic and simulation tools for evaluating components of desktop and server architectures in detail, scalable modeling tools are noticeably missing.

The program committee has put together a strong technical program with a record number of accepted papers (51 regular papers + 4 industrial session papers). We also have scheduled five tutorials and four workshops. We look forward to your participation in this important event.

February 23, 2013
to February 27, 2013
in Intercontinental Hotel, Shenzhen, China

PPoPP is a forum for leading work on all aspects of parallel programming, including foundational and theoretical aspects, techniques, languages, compilers, runtime systems, tools, and practical experiences. In the context of the symposium, “parallel programming” encompasses work on concurrent and parallel systems (multicore, multithreaded, heterogeneous, clustered systems, distributed systems, grids, clouds, and large scale machines).

IISWC is the premier international conference dedicated to the understanding and characterization of workloads that run on all types of computing systems. Whether they are PDAs/smartphones at the low end or supercomputers at the high end, the design of future computing machines can be significantly improved if we understand the characteristics of the workloads that are expected to run on them. IISWC 2012 will focus on characterizing and understanding these modern computer applications.

ANCS is a systems-oriented research conference, presenting original work that explores the relationship between the architecture of modern computer networks and the architecture of the individual hardware and software elements from which these networks are built. This year’s conference emphasizes in its paper selection research on computer and network systems that provide the foundations of emerging network technologies and the future Internet.

The 2012 edition of the ICCD conference marks its 30th anniversary, where special sessions, keynotes, and other events will commemorate this milestone. ICCD is proud to be one of the venues with the longest tradition in the area.

ACM SIGARCH

SIGARCH serves a unique community of computer professionals working on the forefront of computer design in both industry and academia. It is ACM’s primary forum to interchange ideas about tomorrow’s hardware and its interactions with software.