Is the waveform right if device DSL is put between bank ACT and next ACT?

Question:

When I set the Row Precharge period setting bit (SDTR.RP[2:0]) in the SDRAM settings to one cycle and checked its waveform, it looks like one cycle of a device deselect command (DSL) is inserted between the bank active command (ACT) and the next ACT. Is this waveform correct?

Answer:

When the Row Precharge period setting bit (SDTR.RP[2:0]) is set to one cycle, if the bus is accessed consecutively at equal to or less than the SDRAM bus width, a device deselect command (DSL) is inserted between bus accesses.
For example, when the SDRAM bus width is 16 bits and byte access is performed twice, a DSL is inserted between the first single read and the second single read.
Conversely, when the SDRAM bus width is 8 bits and word access is performed, a DSL is not inserted between the first single read and the second single read.
Therefore, the insertion of one DSL cycle may be due to the consecutive access described above. Please check the SDRAM bus width and the bus access size you are using.