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AR# 8158

Description

General Description:

During configuration, the FPGA checks each data frame for the appropriate start and stop bits and by default performs a Cyclic Redundancy Check (CRC) to ensure the transmitted data was received correctly. If any of these bits cause a mismatch, the configuration process is aborted and INIT is driven low to signal the error. Why is this happening?

Solution

The following issues can cause this problem:

The bit stream is targeted for the wrong device:

The same FPGA device size may be available in multiple family types; it would therefore have a different bit streams for each family. For example, the XC4010D, XC4010A, XC4010E, and XC4010XL all have different data frame sizes, so they are not bit stream-compatible.

Ensure that your design implementation targets the exact same device as that on your application board.

Timing violations and clock glitches:

Typically, when an FPGA is connected directly to a memory element, performance characteristics and timing specifications are not points of concern. However, if the address or data paths are being passed through secondary devices or are subject to any extra delay, the access time of the storage element becomes important in relation to the required setup time for the FPGA. Verify that the timing characteristics for the configuration data path of the application conform to the Configuration Switching Characteristics and Timing Specifications outlined in the Xilinx Programmable Logic Data Book.

Signal glitching may be caused by interference from other signals traced close by or by "Ground Bounce" from other devices. Make sure that the FPGA is well decoupled. (Xilinx recommends a 0.1uF and 0.01uF capacitor pair per VCC/GND pair -- try to place these as close to the FPGA as possible, as more than an inch of distance will make them useless.)

Verify that the Setup and Hold timing for the data to the clock meet the specifications in the Data Book. Another problem could be glitching on the clock line. Try adding a decoupling capacitor to the clock line to filter out high-frequency noise. (A 50 pF cap should be sufficient.) If the glitching is in the very high-frequency range, the capacitance of an oscilloscope probe could actually be enough to mask it. Try restarting the configuration while probing the CCLK line.

Data is shifted backwards:

Check to see if the data is backwards by capturing the first two bytes of the Header on the DOUT pin. If the configuration data is being accessed in byte words and shifted serially into the FPGA, a shift in the wrong direction will result in an observation of <0000 0100> instead of <0010 0000> on DOUT. (This is not valid for Express Mode configuration.)

The memory algorithm is outdated:

If the configuration data is stored in and accessed from a memory device such as a Flash RAM, EPROM or SPROM, ensure that the correct data is stored in the element. Such programmable memory devices require constant program algorithm updates.

If a new device is programmed with an older algorithm, incorrect data may be stored, even if the programmer verified the data. Contact the manufacturer of the storage element or memory device to obtain the correct algorithm version.

Express Mode is not enabled in BitGen:

If you are programming in Express Mode, and "-g ExpressMode:Enable" is not set in BitGen, a frame error can occur.