We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Firefox,
Internet Explorer 11,
Safari. Thank you!

AR# 25030

Description

When running PAR for Spartan3A, the following OFFSET timing constraints in the UCF may not meet timing specifications because the VALID number is not correct for frequency of 105 Mhz. The correct number should be 4.00 ns instead of 3.00 ns.

OFFSET = IN -1.00 ns VALID 3.00 ns BEFORE RDClk_P TIMEGRP RD_DDR_R ;

OFFSET = IN -5.50 ns VALID 3.00 ns BEFORE RDClk_P TIMEGRP RD_DDR_F ;

OFFSET = IN -1.00 ns VALID 3.00 ns BEFORE RDClk_P TIMEGRP RC_DDR_R ;

OFFSET = IN -5.50 ns VALID 3.00 ns BEFORE RDClk_P TIMEGRP RC_DDR_F ;

Solution

Changing the OFFSET timing constraints in the UCF file can resolve this issue: