Cortex-A57 Processor

The ARM Cortex-A57 processor is a proven, high-performance 32-bit and 64-bit core. It was designed to extend the capabilities of mobile and enterprise computing applications including compute-intensive 64-bit applications such as high-end computer, tablet and server products.

The processor’s advanced performance characteristics open it up to an extremely wide range of applications, delivering high-efficiency solutions in servers, and defining user experience in tablet and high-end smartphones.

The processor can be implemented individually or paired with the Cortex-A53 processor in an ARM big.LITTLE™ configuration that enables scalable performance and optimal energy-efficiency. It is supported by a range of optimized IP targeted at designing the most efficient complete ARM-based devices. ARM Mali™ processors support all graphics, video and display demands, ARM POP™ IP solutions deliver an accelerated time-to-market, and optimized System IP provides the interconnect and peripheral components.

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Overview

Consumer products have demanded increasingly more performance from their processors over the last few years and this led us to design the Cortex-A57 processor. Smartphones are transitioning from content consumption devices to content creation devices. Now that smartphones are able to capture high-quality video and photographs, consumers want to edit and share this content, driving the need for further processing power delivered by the Cortex-A57 processor. Content creation is not limited to multimedia, but also documents.

A Cortex-A57 processor-based smartphone, wirelessly connected to a screen, keyboard and mouse, delivers a full laptop experience that consumers receive from their typical laptop today. It can deliver all the compute capability a typical consumer needs both today and in next generation devices. The processor also runs legacy ARM 32-bit applications, ensuring the continuity of the ARM ecosystem.

The Cortex-A57 processor features cache coherent interoperability with ARM Mali family graphics processing units (GPUs) for GPU compute applications. It also has a range of optional reliability and scalability features to enable usage in high-performance enterprise applications, and connects seamlessly to ARM interconnect IP with up to 16 core configurations now, and more in the future.

ARM’s big.LITTLE technology means the Cortex-A57 processor can be paired with the architecturally aligned Cortex-A53 processor to create processing clusters which optimize power consumption in consumer devices. The technology automatically assigns high-performance tasks to the Cortex-A57 processor (big), and assigns the more frequent, low-power tasks to the Cortex-A53 processor (LITTLE).

Applications

The Cortex-A57 is designed for use in a range of devices which require the highest performance in ARM's low-power architecture.

Key target markets include:

Premium smartphones

Enterprise servers

Home server

Wireless Infrastructure

Digital TV

The Cortex-A57 processor achieves high levels of performance through a range of microarchitectual implementations and an updated version of the ARM architecture. On the microarchitectual side, the processor features a highly out-of-order, multi-issue pipeline tuned for modern workloads with DSP and NEON™ SIMD extensions mandatory with each core. The inclusion of cryptography extensions improves performance on cryptography algorithms by 10 times over the current generation of processors. It delivers significantly more performance than the Cortex-A15, at a higher level of power efficiency.

The Cortex-A57 processor utilizes the ARMv8-A architecture, enabling power-efficient 64-bit support while maintaining compatibility with existing 32-bit software. As such, the architecture can run in two states. The AArch32 execution state runs existing ARM 32-bit applications while the AArch64 state executes applications in 64-bit code. The ability to provide 64-bit support significantly raises the performance level of the processor, and is ensuring that ARM continues to provide for next-generation devices requiring the right balance of power and performance.

Hardware support for Floating-Point operations in half-, single- and double-precision Floating-Point arithmetic. Now with IEE754-2008 enhancements

Yes

Yes

big.LITTLE technology

ARM big.LITTLE processing is a power-optimization technology where high-performance ARM CPU cores are combined with the most efficient ARM CPU cores to deliver peak-performance capacity, higher sustained performance, and increased parallel processing performance, at significantly lower average power. The Cortex-A57 acts as a big processor and is paired in a configuration with the Cortex-A53 processor.

Increased actual instruction throughput in a broader range of scenarios. In cases where instructions are blocked on a dependency the processor can look for other instructions to run. Full out-of-order scheduling on all execution paths allows more types of instructions to be re-ordered, keeping the back end of the pipeline full more of the time. Support for high-bandwidth out of order back-end, 128 in-flight instructions, instruction-result handling optimized for 32-bit and 64-bit operands.

Performance optimized L2 cache design allows more than one CPU in the cluster to access the L2 at the same time. Sophisticated per-core hardware prefetch units improve memory loads into L2. A balanced design approach allows reduced latency and lower power in the L2 subsystem.

48 entry I-side uTLB allows large set of pages to be handled very quickly by the memory management unit. 32-entry fully-associative D-TLBs (with large-page support) are more responsive to modern memory access patterns.

Way-prediction, tag-reduction, cache-lookup suppression, and other features minimize dynamic power.

Advanced MultiCore Features

The processor also utilizes the widely established ARM MPCore multicore technology, enabling performance scalability and control over power consumption to exceed the performance of today's comparable high-performance devices while remaining within tight mobile power constraints. Multicore processing provides the ability for any of the four component processors, within a cluster, to shut down when not in use, for instance when the device is in standby mode, to save power. When higher performance is required, every processor is in use to meet the demand while still sharing the workload to keep power consumption as low as possible.

Snoop Control Unit (SCU)

The SCU is responsible for managing the interconnect, arbitration, communication, cache to cache and system memory transfers, cache coherence and other capabilities for the processor. The Cortex-A57 processor also exposes these capabilities to other system accelerators and non-cached DMA driven peripherals to increase performance and reduce system wide power consumption. This system coherence also reduces software complexity involved in maintaining software coherence within each OS driver.

Accelerator Coherence Port

This AMBA 4 AXI compatible slave interface on the SCU provides an interconnect point for masters that are interfaced directly with the Cortex-A15 processor. This interface supports all standard read and write transactions without additional coherence requirements. However, any read transactions to a coherent region of memory will interact with the SCU to test whether the information is already stored in the L1 caches. The SCU will enforce write coherence before the write is forwarded to the memory system and may allocate into the L2 cache, removing the power and performance impact of writing directly to off chip memory

Generic Interrupt Controller (GIC)

Implementing the standardized and architected interrupt controller, the GIC provides a rich and flexible approach to inter-processor communication and the routing and prioritization of system interrupts. Supporting up to 224 independent interrupts, under software control, each interrupt can be distributed across CPU, hardware prioritized, and routed between the operating system and TrustZone software management layer. This routing flexibility and the support for virtualization of interrupts into the operating system, provides one of the key features required to enhance the capabilities of a solution utilizing a hypervisor.

Overview

The Cortex-A57 processor can be incorporated into an SOC using a broad range of ARM technology including System IP, Physical IP, and development tools. A broad range of SoC and software design solutions, tools and services from the ARM Connected Community complements this technology. This provides ARM partners with a smooth path through the development, verification and production of fully functional, compelling devices while significantly reducing time-to-market.

Graphics Processors

The Mali family of products combine to provide the complete graphics stack for all embedded graphics needs, enabling device manufacturers and content developers to deliver the highest quality, cutting-edge graphics solutions across the broadest range of consumer devices.

The Cortex-A57 can be used with all Mali high-end graphics processors, and the Mali-DP500 display processor and Mali-V500 video processor are also compatible.

System IP

The ARM CoreLink™ interconnect and memory controller system IP addresses the critical challenge of efficiently moving and storing data between up to 16 Cortex-A series processors, high-performance media processors and dynamic memories to optimize the system performance and power consumption of the SoC. The CoreLink system IP enables SoC designers to maximize the utilization of system memory bandwidth and reduce static and dynamic latencies. While the ARM CoreSight technology provides complete on-chip debug and correlated, real-time trace visibility for all cores of the Cortex-A57 processor, reducing risk and speeding development of high-quality multiprocessing software. The new ARM CoreLink CCN-504 Cache Coherent Network provides optimum system bandwidth and latency. The CCN-504 provides AMBA 4 AXI Coherency Extensions (ACE) compliant ports for full coherency between multiple Cortex-A series processors, better utilizing caches and simplifying software development. This feature is essential for high-bandwidth applications including gaming, servers and networking that require clusters of coherent single and multicore processors. Combined with the ARM CoreLink network interconnect and memory controller IP, the CCN increases system performance and power efficiency.

The CoreLink CCI-400 or CoreLink CCI-500 Cache Coherent Interconnect provides the big.LITTLE interconnect for use with Cortex-A53 for client applications including smartphone and tablet application processors.

Physical IP

ARM Physical IP Platforms deliver process optimized IP, for best-in-class implementations of the Cortex-A57 processor at 20nm and below. A set of high-performance POP™ IP containing advanced ARM Physical IP for 28nm technologies supports the Cortex-A57, to enable rapid development of leadership physical implementations. POP IP supports the ARM strategy of offering specifically targeted Physical IP to enable partners to achieve tuned implementations of ARM cores. ARM is uniquely positioned to design the optimization packages in parallel with the Cortex-A57 processor design, enabling the processor and physical IP combination to deliver high-class performance in a mobile power envelope while facilitating rapid time-to-market.

Tools Support

ARM DS-5 Development Studio fully supports all ARM processors as well as a wide range of third party tools, operating systems and EDA flows. DS-5 is unique in its ability to provide solutions that take full advantage of the complete ARM technology portfolio, offering a comprehensive range of software tools to create, debug and optimize systems based on the Cortex-A57 processor.

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