I'm building a dual CGS34 ASR module with the CGS58 Utility LFO as one module. I'm waiting for a panel from FPE and some more components to arrive so I have time to worry about untested details...

The power headers on the three boards are all going to be ganged in line for one power input harness from the buss. Bad idea?

Are the LED's on the utility LFO going to be a significant source of HF noise for the power rails in the ASR's? I'm using ferrite beads to cut down on as much as possible but still am concerned about this. Oh, and the LFO's pulse out will drive the ASR's unless an external clock is plugged into the break-in jack.

I can leave off the LED's and see what happens. I plan to fly them with MTA connectors anyway so they are easily unplugged.

BTW, here is the MOTM (5U) format panel layout. It is using a system of looping and series (3 or 6 stage) switching for some fun on the ASR's.

I do not think you will have any problem with just 2 LEDs. You could use superbright LEDs which require 4k7 to 10k resistors to reduce the brightness. This will use a lot less current, less drain on the PSU etc.

so at higher vco frequencies, with a constant voltage at the cv in, i get a noticable "pop" or "click" that goes along with the clock pulses. i'm thinking this might be the 'warble' that ken talks about being a difference in opamp offsets (with the 3140) but I used lf356's so this shouldn't be an issue.
does anyone have any ideas what could be causing this? it's definitely still completely useable, just wondering if this is normal. thanks!_________________http://www.youtube.com/user/borisandfef

Thanks for the replies. The brighter LED idea sounds good but I hate those blue ones with a passion.

If this module works out the way I'll put up a drawing of the switch logic on the series/loop function. There is interruption of the clock and cv on the "B" register when in series. Everything is done from register "A". The tricky part is the logic between loop with series or loop without series. All clock input jacks are interruptible to break in on the clocks from their adjacent LFO banks.

so at higher vco frequencies, with a constant voltage at the cv in, i get a noticable "pop" or "click" that goes along with the clock pulses. i'm thinking this might be the 'warble' that ken talks about being a difference in opamp offsets (with the 3140) but I used lf356's so this shouldn't be an issue.
does anyone have any ideas what could be causing this? it's definitely still completely useable, just wondering if this is normal. thanks!

All mine are pretty clean except for one. The first stage on the ASR has a +15v jump that lasts about 15% duty cycle of the incoming clock. I tried several external clocks and all do the same. The rest of the stages respond fine.

Below is an image of the offender. The red line is reference voltage input from a step sequencer and the yellow is the first stage of the ASR.

I didn't socket the 356's so I'm crying now. Could this be a wonky capacitor or should I just suck it up and replace the 356?

You can hear this spike at around 8 minutes into this video of the demo of this module.

Here is a better view of what's going on. The +15v spike is actually one whole clock cycle.

The red line is the input reference voltage form a step sequencer which is clocked the same as the ASR. The Yellow line is the first output buffer.

The step sequence is three steps of +5v, 0v and -5v to keep it simple. As is evident, the spike occurs every fourth clock pulse and lasts the entire clock duty cycle.

Since the original post of this, I've changed two of the 356's, the CD4052 switches and the TL074 buffer. I fixed a ground fault to two of the CX caps and cold solder to a resistor on the clock input buffer. Still it is the same problem.

I have more 356's coming in the mail so I'll change them. Since this is only happening every fourth clock cycle it suggests there is an S&H problem - right?

How do I check these LF356's better than "place your finger across the legs" technique that Ken suggested?

Edit - Or check for solderbirdge between pin 15 and pin 16. (Though that would affect the other stages as well.

But since it's cyclical - I.e. every 4th step, something is wrong when it reads from the S&H cell. So my guess would be it's either pin 11, 12, 14 or 15 of the 4052._________________http://www.thehumancomparator.net/

It is fixed. There was a lifted pad on one of the jumper lines at either pin 11 or 14 of the 4052b chip. zthee gets the prize!

I do have a new question regarding the voltage droop which is (to my knowledge) a common thing on these ASR's. I'm see about 160mv difference in stage 1, 200mv on stage 2 and 220mv on stage three. That much difference from the input voltage (lets say 0 volts). The voltage difference stays the smae regardless of the scale. In other words, if there is 5 volts input then there is 5.16 at stage 1 etc..

I can build a circuit comprised of a 20k resistor and a 4k7 trimmer at the output buffer and the -15v pickup (basically replacing the 22k resistors), but my question is - could building this circuit with .1% resistors (instead of 1%) help to alleviate some of the droop or is it something entirely unrelated?

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