Via Talks Up 64-Bit, Dual-Core Plans

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SAN JOSE — Via Technologies Inc. announced plans to move into the 64-bit generation on Tuesday, with the disclosure of its 64-bit “CN” or “Isaiah” processor.

Via did not reveal when the processor would ship, but Glenn Henry, the president of Via’s Centaur Technology processor division, told ExtremeTech in an interview that early 2006 “was not a bad guess”.

With Via’s announcement, all three of the major PC microprocessor companies have now announced a timetable to shift to the 64-bit generation. Henry, who for years has touted low power and a small die size as the chief requirements for designing processors, said the CN chip would be entirely compatible with previous Via processors as well as the X86-64 extensions that AMD originally designed and Intel emulated, Henry said. However, the CN will be a “clean sheet” design: a fresh start, he added.

In addition, Henry said Via has begun thinking about multi-core designs, although they won’t be the primary thrust of the company, he said. Instead, Via will likely produce multi-core “derivatives” of the company’s single-core parts as a complement to its single-core offerings, he said in an interview.

Henry said he did not plan to disclose the speed of the CN processor, or many of its features. “As you’re probably familiar with by now, we’re letting megahertz be what it is,” he said.

Instead, Via’s design constraints include dramatically improving the floating-point performance by two to three times compared to the current design, he said. A microprocessor’s integer performance is closely tied to the chip’s clock speed. Floating-point performance, on the other hand, is more dependent on the chip’s microarchitectural design. Both the improvements in floating-point performance and the 64-bit extensions are a recognition that multimedia will play a growing role in microprocessor design constraints, even in the low-cost PC market Via has traditionally served, Henry said. The floating-point path will be 128 bits wide, according to Henry’s slides. The chip will also add an additional SSE instruction, a 4x32x32 integer instruction.

The CN will also include additional security enhancements and a larger level-2 cache, Henry added, as well as an embedded north bridge memory controller. Henry did not disclose what type of memory the CN would use.

Via’s current roadmap calls for the current C5J “Esther” design  a 2.0-GHz, 90-nm part — to sample in the fourth quarter of 2004 and ship in the first quarter of 2005. Via’s roadmap also includes three more designs, which Henry said he did not plan to discuss: the C5Q, a 0.13-micron processor; the C5R, its 0.11-micron successor; and the C5W, a part that will be fabricated on a 90-nm SOI process.

Editor’s Note: This story was updated on 2:13 PM PDT on Oct. 5, 2004..

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