Even though Qualcomm is fabless, it is looking to learn about the advanced CMOS processes below 22-nm and to accelerate scaling for next-generation logic and memory products.

In May 2011, IMEC announced that another fabless company, Nvidia Corp. had joined IMEC's core CMOS program on advanced CMOS scaling as an Insite member.

"We continue to invest heavily into technology leadership which includes advanced semiconductor technologies," said Jim Thompson, executive vice president of engineering at Qualcomm Technologies Inc., in a statement issued by IMEC. "We have collaborated with IMEC on the 3-D stacking program for the last four years and we look forward to expanding our engagement with IMEC to include CMOS research and the new MRAM program."

@supersonic76, I was checking up on this. Indeed, I would think even 32 nm hp is not yet nailed down, given the serious LER (well exceeding 10%). That's why there has even been talk of EUV being used in double patterning context, like complementary lithography proposed by Intel. Of course, consideration of double patterning defeats purpose of considering EUV.
http://www.euvlitho.com/2012/P36.pdf

I believe they run test structures.
There is some data that is private and some that is communal.
I suspect some wafers are communal and some private and confidential.
Things like lithography metrics benefit from totalling everybodies' wafers.

For technologies which are equally extremely high risk to all companies (like EUV), it makes sense to have the collaboration model, with actual data and information being shared. For technologies of unequally high risk (like FinFETs) the value may be realized only for some companies, e.g., Qualcomm instead of Intel in the case of FinFETs.