July 2009 – DAC Preview

Welcome to the July issue of IP Times – your source for semiconductor Intellectual Property (IP) news, trends, and developments – from the industry’s trusted IP partner. See what Virage Logic has planned for the 2009 Design Automation Conference (DAC) coming up in San Francisco, California.

Resource Center

Issues in SoC Methodology Although statistical design methodology and modeling offers enormous potential, designers may not be ready to fully deploy this methodology at the SoC level. We don’t even know all the possible pitfalls yet, but here is a list of some important questions to consider…
Go to the Vipster Blog.

Virage Logic in the News

Virage Logic Offers Broadest Portfolio of Embedded Non-Volatile Memory Solutions at TSMC Virage Logic announced that it offers the broadest portfolio of embedded non-volatile memory (NVM) at TSMC, with fully qualified IP solutions ranging from 250nm down to 65nm. With a comprehensive selection of multi-time programmable (MTP) and few-time programmable (FTP) NVM IP, the AEON® product family addresses the needs of wireless, automotive, analog, power management and security applications.
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Virage Logic Sees Strong Adoption of Company’s Broad 40nm IP Product Portfolio Since being named TSMC's 40nm early development partner in 2007, the company has seen strong adoption of its extensive 40nm product portfolio. Comprising embedded SRAMS, embedded memory test and repair, logic libraries, and memory development software, the Company's silicon-proven 40nm product offering has been designed to optimize area, performance, power and yield. Learn how you can find the
Sure Path to 40nm Success.
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Virage Logic Expands Presence in India to Serve Growing Market Demand for Broad IP Portfolio Virage Logic has expanded its presence in India with the appointment of CoreEL as its sales representative. CoreEL joins a growing global network of sales representatives that complement and expand the reach of Virage Logic's direct sales channel.
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Auto Industry Replaces Fuse Technology with Standard CMOS Based MTP; Adds Functionality, Testability and Reliability – ChipEstimate.com The automotive industry has always set the bar in terms of quality and reliability metrics. Yield issues that cause a production line to go down can cost a manufacturer millions of dollars per day, and a field failure that requires a product recall can run into the hundreds of millions of dollars.
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Should Dual Rail Go Mainstream in Deep Nanometer Era? – Electronic Design Deep sub-nanometer designs are stressed with large process variability. SRAM-bits have the most aggressive design rules in the SoCs, and the most variability. A dual rail solution offsets some of the variability at the cost of additional design efforts. Dual rail solutions appear to be complex, but several area, power, and performance tradeoffs can be made to simplify the design.
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Memory Interface IP Sector Heats Up – EE Times Virage Logic and other memory interface IP vendors are now seeing an upswing in business, analysts said. The severe downturn is causing a growing number of OEMs to evaluate or rationalize their internal IP efforts.
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AEON® Memory Technology Gets Automotive Qualification – EE Times The non-volatile AEON memory technology has been qualified for automotive use according to the AEC-Q100 standard. The technology could compete with certain applications where hitherto EEPROMs and Flash memory has been used.
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Tool Automates Power Optimization of Embedded SoC Memories – Electronic Design In developing PowerPro MG, Calypto worked closely with Virage Logic to ensure that the tool would support Virage Logic’s 40nm SiWare™ Memory compilers. The SiWare memories are highly configurable with options to control area, speed, power, and yield. From a power perspective, the memories offer multiple modes: a run mode, a standby mode (light sleep), a shutdown mode, and a dormant mode (deep sleep).
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Upcoming Industry Events

As the industry’s trusted semiconductor IP partner, Virage Logic participates in a variety of global industry events to help educate the SoC design community on the latest advanced IP technology. See below for a list of upcoming events where you can hear Virage Logic’s IP experts address the complex issues facing the industry today.

Design Automation Conference (DAC)
July 27-30, 2009
Moscone Convention Center, San Francisco, CaliforniaTSMC Open Innovation Forum – Booth #822The Virage Logic IP experts will be exhibiting and speaking at DAC in the TSMC Open Innovation Forum booth to highlight the latest developments in advanced IP technology. Learn how you can take the
Sure Path to 40nm Success – stop by to meet the team and hear more about our embedded SRAMs, embedded NVMs, embedded memory test and repair, logic libraries, memory development software, and DDR/interface IP solutions. Visit our website for more information about
Virage Logic at DAC. Sign up today to attend DAC in San Francisco.
Register.

Learn more about Virage Logic at one of these interactive panels or informative sessions at DAC:

International Symposium on Low Power Electronics and Design 2009 (ISLPED 2009) August 19-21, 2009 The Westin Hotel San Francisco Airport, Millbrae, California Dr. Yankin Tanurhan, Vice President and General Manager of Virage Logic’s NVM Business, will be giving a keynote presentation on “Dealing with Disaggregation in the Ever-changing World of Semiconductors.” Register.

Upcoming VIP Partner Events

Virage Logic’s VIP Partner Program brings together technology and business alliances with our industry partners for the benefit of our mutual customers. As part of the VIP Partner Program, Virage Logic supports our partners’ global events, such as the ones listed below.

Virage Logic Membership Has its Access Privileges

Become a Virage Logic Member for exclusive access to Foundry-Sponsored IP, technical documentation, and much more! It only takes a few minutes to become a Virage Logic Member.
Sign up today and begin enjoying the benefits of Virage Logic Membership.

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