I have been using Xilinx tools (Vivado 2018-2019.1, SDK, Petalinux tools) for previous Zynq7000 projects but in my current project we are using Zynq Ultrascale+ MPSoC.We bought an Ultra96v2 dev board to test the chip that's going on the prototype pcb. I can run the out-of-box instructions on the card for Linux platform and can even get PYNQ to work.

My problem is that our application isn't targeting Linux at this point. It is a hard real-time control application and runs on the R5-core. We are NOT interested in machine vision or any of that hype and running linux as master is not an option here.

There doesn't seem to be any reference design or decent example of creating a basic hardware design with PS-block, some GPIOs, UART, Timers, non-volatile memory etc.I have found the board preset and constraints files from Github, but failed to create even a simple design in Vivado because just adding the Zynq PS-block and applying board presets induces weird errors that lead down a rabbit hole.

Can somebody share a design, tutorial or something targeting Vivado and SDK (not Vitis) version 2019.1 and bare-metal/FreeRTOS development? I'm starting to feel really frustrated with the lack of simple examples. Moreover Vitis seems to break all backward compatibility and only target high-end devices, ML etc. so those examples are out of the question.

Sorry for the trouble. Can you confirm that you have the Avnet board definition files installed and you can target the board in Vivado? I've never done anything with the R5, but we could give it a try. I can certainly give you some starting points with the A53. Are you able to run something simple, like a UART-only design and Hello World? Are you booting from SD Card or over JTAG?

There are other resources out there that aren't specific to Ultra96 that might be useful. This is a good one:

Thanks for the links, but I'd already gone through those before. I have the board files installed and they show in the menus.It's just that when I apply the board preset or just try to validate my design without modifications to the ZynqUS+ or MB blocks. I get bunch of weird errors that tracing down produces even more errors.

I'm more of a software guy than HDL so I would just need a couple of HW platforms that had all the common peripherals and Zynq block or Microblaze block so I could get to work with these.

If you would like a more populated system, you can build Avnet's out-of-box hardware platform, which is the same as what we include in our BSP. The instructions for doing this are spelled out in this blog by narrucmot:

Thanks a lot, finally got it to build after fighting with TCL and path names for a while.Seems to have most if not all of the basic peripherals. Peripheral tests PASS and now have a solid debug configuration.

I have been using Xilinx tools (Vivado 2018-2019.1, SDK, Petalinux tools) for previous Zynq7000 projects but in my current project we are using Zynq Ultrascale+ MPSoC.We bought an Ultra96v2 dev board to test the chip that's going on the prototype pcb. I can run the out-of-box instructions on the card for Linux platform and can even get PYNQ to work.

My problem is that our application isn't targeting Linux at this point. It is a hard real-time control application and runs on the R5-core. We are NOT interested in machine vision or any of that hype and running linux as master is not an option here.

There doesn't seem to be any reference design or decent example of creating a basic hardware design with PS-block, some GPIOs, UART, Timers, non-volatile memory etc.I have found the board preset and constraints files from Github, but failed to create even a simple design in Vivado because just adding the Zynq PS-block and applying board presets induces weird errors that lead down a rabbit hole.

Can somebody share a design, tutorial or something targeting Vivado and SDK (not Vitis) version 2019.1 and bare-metal/FreeRTOS development? I'm starting to feel really frustrated with the lack of simple examples. Moreover Vitis seems to break all backward compatibility and only target high-end devices, ML etc. so those examples are out of the question.