Technology details and results will be presented at the 2011 International Electron Devices Meeting (IEDM) being held in Washington DC, starting December 5th.

The biggest contributor to power consumption is supply voltage. Previously, the power supply voltage of CMOS steadily reduced to approximately 1.0V at the 130nm technology node, but it has not reduced much further as technology has scaled to the 28nm node. To reduce the power supply voltage, one of the biggest obstacles is the minimum operating voltage of embedded SRAM blocks.

By combining SuVolta's Deeply Depleted Channel (DDC) transistor technology - a component of the PowerShrink platform - and Fujitsu Semiconductor's process technology, the two companies have verified that a 576Kb SRAM can work well at approximately 0.4V by reducing CMOS transistor threshold voltage (VT) variation to half. This technology matches well with existing infrastructures including existing system-on-chip (SoC) design layouts, existing design schemes such as body bias control, and existing manufacturing tools.

SuVolta argues that one reason that the scaling of supply voltage stopped at the 130-nm node was because of random dopant fluctuation (RDF) in the implanted dopants in the transistor channel. RDF results in variation in threshold voltage (VT) between different transistors on a chip.

DDC achieves tight control of dopants in layers of epitaxial silicon growth to define a thin channel at the start of the manufacturing process. Thereafter the process is a conventional bulk CMOS process but without the need to inject dopants using ion implantation. According to the Fujitsu paper intra-die VT variation is reduced by half through the use of DDC compared with Fujitsu's non-DDC 65-nm CMOS.

Fujitsu Semiconductor plans to advance the technology and in order to respond to the need for low-power consumption and/or low voltage operation in consumer products, mobile devices and other offerings.