Using a clock pulse to control the change of state of the flip-flop synchronizes its operation with the rest of th circuit.this avoids the “race condition” that can occur with the RS flip-flop. The device is triggered by the negative(falling) edge of yhe clock pulse.

The RS Flip-Flop Has An Undesired Operating Condition, Where 1 Level At Both Inputs Will Cause Both Outputs To Go To 0 Level. This Undefined Condition Must Be Avoided. Circuits Involving Feedback Ill Lead To A “Race Condition” Where The Output Will Be Unpredictable.

CIRCUIT DIAGRAM:-

SR FLIP FLOP CIRCUIT DIAGRAM

TRUTH TABLE:

S

R

Q

Staff

0

0

NC

NC

NO CHANGE

0

1

0

1

RESET

1

0

1

0

SET

1

1

1/0

1/0

FORBIDDENT STATE

RS flip-flop are not suited for sequential circuits without additional circuitry. Alone they are used for debouncing switches and holding states, such a in alarm systems.