HiTas -- Static Timing Analyser

HiTas is a static timing analysis tool. Its strength lies in its transparent
hierarchical approach combined with the ability to perform analysis at the
transistor-level, cell-level or a mixture of the two.

The transistor-level analysis brings the possiblity of handling full-custom circuits not
individually but also as blocks within the hierachy of a complete chip. In addition,
working at transistor level removes the need for costly and time consuming
re-characterization when performing the analysis at different corners. The fact that
delays are dynamically calculated throughout the design means that the differences in
local context are automatically taken into account such as power supply variations due to
IR drop, or simply using different voltages for low-power applications.

Yagle provides automatic generation of a behaviral model (in vhdl or Verilog)
directly from a transistor netlist. Its major strength is the ability to take into
account functional correlation between signals. This optimizes the partitioning and
functional characterization as well as providing the means for automatically identifying
and characterizing most kind of memory elements. Yagle is able to mix the totally
automatic approach with a pattern-matching approach. This allows functional abstraction
of circuits containing a mixture of analog and digital. This can be used to handle RAMs
which contain sense amplifiers for example.

This tools are based on the PhD works of Amjad Hajjar (1992), Karim
Dioury (1998) Anthony Lester (1999) Grégoire Avot (2003) under the
supervision of Alain Greiner, Pirouz Bazargan-Sabet and Marie-Minerve
Louërat.