EDA spec describes power

Santa Cruz, Calif. -- With all the attention paid to IC power management problems at 90 nanometers and below, it may be surprising that there's no standard way to express power specifications. An industry coalition led by Cadence Design Systems Inc. proposes to change that by developing a Common Power Format (CPF) that could be read by tools throughout the design flow.

The coalition, Power Forward, counts Advanced Micro Devices, ARM, ATI Technologies, Fujitsu, Freescale Semiconductor, NEC and Taiwan Semiconductor Manufacturing Co. (TSMC) as members. No other EDA companies are involved yet, but Cadence representatives say they hope competitors will come on board after an initial development effort culminates in early 2007.

"The whole issue is that there's no way of specifying what your power intent is," said Chi-Ping Hsu, corporate vice president of synthesis solutions at Cadence. "That's especially true with multiple power domains, multiple supply voltages and frequency scaling." The result, said Hsu, is a "fragmented" design flow with different file formats for each tool in the flow.

Such a flow is extremely difficult to automate. Once tools can read and understand power intent consistently, Hsu said, "we can automate so many things that were not possible before."

Many chip designers identify dynamic and leakage power consumption as the most glaring problem at 90 and 65 nm. "The scaling of the process is stalling because of power," Hsu said, and "we don't see any dramatic new change in process technology to address this issue. So this time we have to do a design-related power reduction, as opposed to hoping some miracle will occur on the process side."

Low power is a critical priority at Freescale Semiconductor Inc., said Chekib Akrout, vice president of design technology. "We have a very strong capability to manage timing," he noted, but "we don't have the technology to really design for power, or the automated tools that will help us. From the Power Forward initiative, we hope to get to the level of capability, in terms of tools and automation, to develop low-power chips across all our businesses."

"There is a void right now in terms of the ability to transfer power information up and down the design chain," said Ed Wan, senior director of design services marketing at TSMC. "I think a format that is adopted by a majority of users will help in creating low-power solutions throughout the design chain."

The Power Forward initiative isn't starting with a blank sheet of paper; a draft specification for the CPF already exists inside Cadence. Hsu called the approach a flexible format, more like a TCL scripting language than an HDL. Designers can express their power intent, constraints and methodology and specify library and intellectual-property intent.

Jan Willis, Cadence's senior vice president for industry alliances, said the initiative's first members will "roll up their sleeves" with the hope of having a draft proposal by January. At that time, she said, the initiative will open the doors to broader participation and approach a standards body that can provide a home for the emerging standard. "We want the entire industry, including competitors, to be involved and to use this as a standard," she said.

Other EDA vendors won't participate until January, which could be controversial. "It's a tricky balance," she said. "We had the idea and we have the implementation, and we think that if we want to go faster, the focus needs to be on the user community and the design chain."