> > I am trying to get a feel for how one might mix 3-volt level signaling and> > 5-volt level signaling PCI bus driver/receivers on a common PCI bus.>

On Mon, 26 Feb 96 22:03:34 EST Andy Ingraham wrote:

> Perhaps you didn't mean to say "signaling"? 3-volt signaling and 5-volt> signaling -- as in sections 4.2.1 and 4.2.2 of the PCI spec -- are mutually> exclusive environments that can never mix. (Like mixing TTL and ECL.)> > What you can do, however, is use a device that is powered by 3.3V, and> outputs 0/3-volt output levels, on a PCI bus designated as a 5V> signaling environment. This is what you referred to as "3-volt level> signaling and '5-volt compliant.'"> > This arrangement is permitted because the output voltage specs of the> 5V signaling environment are wide enough to encompass what you might> call 3V switching levels, even though they are indeed "5V signaling> environment" PCI levels.> > And by the way, the output levels of these 3.3V-powered, 5V signaling> devices is rather similar to good old TTL, which, despite having 5V> power, might drive only as high as 2.4V in the high state. The 5V PCI> switching levels are essentially TTL levels.> > There are other differences besides the lack of clamping diodes that> differentiate 3.3V signaling devices from 5V signaling devices, but that> is one of the biggies.>

The choice Andy proposes is one which I have been working with from a
circuit rather than a model point of view. We have an automotive
customer who desires reduced system operating power while reducing
battery drain during key off. The MCU is powered by a nominal 3.3 volt
supply and interfaces with other system chips powered by 5 volts. The
IC technology for the MCU is CMOS which requires special attention to
the pin I/O driver design. First supplying switching levels from .4 to
2.4 volts is not a big problem. The problem comes in when the I/O pin
is configured as an input driven by a 5.5 volt source. The normal
configuration of a CMOS P-channel device creates a foward bias
parasitic diode from pin to the 3 volt IC rail (P-ch drain to backgate)
which will raise the IC power current limited by the 5 volt external
driving source. There are methods to protect from this but it comes
with a cost (usually silicon area, complexity and degraded speed).
Third, the problem gets worse for advanced CMOS technologies employing
< 110 A gate oxide thickness. This implies g/d, g/s, and g/b breakdowns
close to 5.5 volts. With the advanced technology we have to protect
both N-ch pulldown and P-ch pullup from this breakdown (protect N-ch or
P-ch - gate at Vss from drain at 5.5 volts). I have recently completed a
design of one of these 3 volt - 5 volt friendly type I/O drivers and
its not pretty but it works.