A dissertation submitted in partial fulfillment of the requirementsfor the degree of Doctor of Philosophyin the School of Electrical Engineering and Computer Sciencein the College of Engineering and Computer Scienceat the University of Central FloridaOrlando, Florida

ABSTRACTThe power requirements for leading edge digital integrated circuits have becomeincreasingly demanding. Power converter systems must be faster, more flexible, more preciselycontrollable and easily monitored. Meanwhile, in addition to control process, the new functionssuch as power sequencing, communication with other systems, voltage dynamic programming,load line specifications, phase current balance, protection, power status monitoring and systemdiagnosis are going into today’s power supply systems. Digital controllers, compared withanalog controllers, are in a favorable position to provide basic feedback control as well as thosepower management functions with lower cost and great flexibility.The dissertation gives an overview of digital controlled power supply systems bycomparing with conventional analog controlled power systems in term of system architecture,modeling methods, and design approaches. In addition, digital power management, as one of themost valuable and “cheap” function, is introduced in Chapter 2. Based on a leading-edge digitalcontroller product, Chapter 3 focuses on digital PID compensator design methodologies, designissues, and optimization and development of digital controlled single-phase point-of-load (POL)dc-dc converter.Nonlinear control is another valuable advantage of digital controllers over analogcontrollers. Based on the modeling of an isolated half-bridge dc-dc converter, a nonlinear controlmethod is proposed in Chapter 4. Nonlinear adaptive PID compensation scheme is implementedbased on digital controller Si8250. The variable PID coefficient during transients improvespower system’s transient response and thus output capacitance can be reduced to save cost. InivChapter 5, another nonlinear compensation algorithm is proposed for asymmetric flyback-forward half bridge dc-dc converter to reduce the system loop gain’s dependence on the inputvoltage, and improve the system’s dynamic response at high input line.In Chapter 6, a unified pulse width modulation (PWM) scheme is proposed to extend theduty-cycle-shift (DCS) control, where PWM pattern is adaptively generated according to theinput voltage level, such that the power converter’s voltage stress are reduced and efficiency isimproved. With the great flexibility of digital PWM modulation offered by the digital controllerSi8250, the proposed control scheme is implemented and verified.Conclusion of the dissertation work and suggestions for future work in related directionsare given in final Chapter.

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This document is dedicated to my parents.viACKNOWLEDGMENTSI would like to express my sincere appreciation to my advisor, Dr. Issa Batarseh, for his forhis guidance, encouragement and support. Dr. Issa Batarseh’s extensive vision and creativethinking have been the source of inspiration for me throughout this work. His personality andmanagement experience are examples for me.I am grateful to my committee members, Dr. Louis Chow, Dr. Wasfy Mikhael, Dr.Christopher Iannello, Dr. Takis Kasparis, Dr. Jiann S. Yuan and Dr. Thomas Wu for theirvaluable suggestions and numerous help.It was a great pleasure to work in the Power Electronics Laboratory at the University ofCentral Florida Center. I am truly indebted to Dr. Hong Mao, Dr. Jaber A. Abu Qahouq, Dr.Shiguo Luo, Dr. Weihong Qiu, for their valuable guidance and help, made this dissertationpossible. I would also like to acknowledge my team members Dr. Songquan Deng , OsamaAbdul-Rahman, Liangbin Yao, Shangyang Xiao for their useful discussion and support.I would like to thank the digital power group in Silabs, Don Alfano, Ka leung and JinwenXiao. It is a pleasure to work with such a talented, hard-working and creative group. And I alsolike to express my gratitude to my friends, Jinwen Xiao, Yufang Jin, Alex Cai, Xiaolin Guo,their friendship and help have made my stay in Austin pleasant and enjoyable.My heartfelt appreciation goes toward my family who has always been there with their loveand encouragement.Yangyang WenMarch 2007viiTABLE OF CONTENTS

The advances and explosion in VLSI technologies for the past thirty years impose newchallenges for delivering high-quality power to processors. As transistor lithography dropsdramatically below the 0.1um level, Moore’s Law promises sufficient transistor density andspeed extremely increased. The power requirements for leading edge processors and ASICs havebecome increasingly demanding. Power converter system must be faster, more flexible, moreprecisely controllable and easily monitored. Meanwhile, in addition to control process, the newfunctions such as power sequencing, VID programming, load line specifications, phase currentbalance, protection and power status monitoring involve more and more to power system [A1].This proceeding toward increased speed and performance is taxing the limits of today’spower systems. Power architecture is needed to meet higher requirements, more functionalityand new challenges while delivering high performance, fast time-to-market, and scalability. Thisdemand from the controller and the continuing advance of digital technology has pushed manypower manufactures to look at digital power control.The relatively early application of digital power control is motor control [A2]. However,for high-frequency switching power converters used in computing and telecom power systems,digital power faces new challenges and need to raise new functionalities and solutions for moredemanding power requirements. The digital control for dc-dc converters has been becoming a2hotspot in both industry and academia in the past 4 years. It was expected that the revenue ofdigital power reach $1 billion in the year of 2010, which includes the products of both digitalpower management and digital power loop control.“Digital Power” is defined as digitally controlled power products that provideconfiguration, monitoring, and supervisory functions, even extended to fully digital loop control.It is important to note that “digital power” really includes two different areas of powertechnologies. One is “digital control”, the real-time, cycle-by-cycle control of power switches.The other area is “digital power management” [A3]. Figure 1-1 is showing a multi-POL powermanagement system with PMBus protocol, which is based on physical transport layer SMBus. Inthe system, each POL is controlled under its own digital loop. The system host manages multiplePOLs through the series SMbus. The power management may include switching frequencyadjustment, sequencing, voltage margining, voltage/current/temperature monitoring andprotection etc.

Form power converter designer’s perspectives, digital controllers have many advantagesover their analog counterparts. An analog controller needs a number of passive components andoccupies large footprint. The values of those analog components are sensitive to temperature.Those sensitivity and aging effect limits the mass-production of products. Compared with theanalog controller, digital controllers provides easy of integration and improves systemreliability. Since only a few components are needed, digital controlled system is less sensitive tocomponents tolerance, and the Mean Time Between Failures (MTBF) can be reduced. One of themost important benefits digital controllers provide is the flexibility. By utilizing the program4memory, sophisticated control and monitoring schemes can be built in digital control systems.For example, the control functionality and parameters can be changed to meet the newrequirements, which results in less design and development time - faster time-to-market [A4].Fundamentally, digital architectures differ from analog ones in the fact that digitalcontrollers use AD converters to digitize current and voltage information, and complete thecompensation and regulation based on programmable digital filters techniques. Additionally,digital architectures utilize some forms of program memory, which not only allows for moresophisticated monitoring and control schemes such as nonlinear control, but also adds a softwaregraphical user interface (GUI) as a design tool to simplify the system design. These GUIs areused in the design phase to configure the digital controller for specific design parameters andreduce the product development time. Moreover, digital processes tend to exist in smallergeometries, offering lower-cost solutions where there is a high degree of circuit functionintegration.The use of software to change the controller functionality makes a system based on adigital controller very flexible. The digital controller offers the ability to add, eliminate or changeany parameter in the system in order to meet new requirements, or to optimize and calibrate thesystem. For example, the same POL (Point of Load) can be programmed to meet different designspecifications allowing the supplier to have a single module that meets several design points. Italso offers the capability to integrate and cascade multiple systems together because of the easeof integrating communication capability into the digital controller. For example, where multiplePOL boards are used, the need of current sharing can be implemented through a standardcommunication bus without the need for any hardware additions.5Systems based on digital controllers require fewer components, which decreases themean time before failure (MTBF) of the system. For example, all the components for thefeedback loop are eliminated along with the "select at test” and "select according to designspecification” components. The added capability of monitoring protection and prevention alsoincreases the system reliability. For instance, an engineer can choose to monitor the systemtemperature to decrease the current limit level, or turn on a fan. This scenario decreases the stresson the power components and fans.

SDLC RVinVoG(z)-+DigitalCompensatorVrefd(n)E(n)U(n)KDPWM

Figure 1-2 Typical digital controlled switching power converter

A typical digital controlled switching power converter is shown in Figure 1-2.Compared with analog controller, DPWM in the digital controller performs the same function ofdrive signal generation as the analog counterpart, but it does so by “calculating” and “timing” thedesired duration of ON and OFF periods of its output signal. By contrast, an analog PWMusually operates by triggering ON at a clock transition and triggering OFF when a fixed voltage6“ramp” reaches a pre-set trip voltage. In addition, unlike analog controller, the digital systemcompensation is conducted under “clock” in discrete domain. Those differences offer digitalcontrolled system some advantages and but also challenges.

The digital compensation is typically implemented with PI or PID style subsystem,which translates a digital representation of output voltage into duty-cycle information fed toDPWM block. PID controller adjusts the output voltage on a programmable reference byadjusting pulse width, in real-time, to provide output voltage regulation. The PID compensator isrequired to compensate for gain and phase-shift factors around the control loop to achievedesirable performance as in the analog controller. In digital controlled systems, there isadditional phase shift arising from time delays in processing the digital data. The major gain andphase-shift factors in an analog system are considered when designing a digital controlledsystem, taking into consideration the time delay from AD conversion and other delay factors.AD converter converters analog output voltage to digital data. Each binary “word”,containing upwards of N bits of data, is sent to the PID control law processor at a high clock rate.Analog control provides very fine resolution for output voltage adjustment. In principle, anoutput voltage can be regulated close to any programmed reference, and the precision is onlylimited by the steady-state error, thermal effects and system noise. On the other hand, a digitalcontrol loop has a finite set of discrete “set points” resulting from the resolution of “quantizingelements” in the system.The usual digital compensator design methods includedirect digital designand digitalredesignapproaches. Fordirect designapproach, a discrete model of switching power converterthat includes sampled analog components is first constructed; then, the compensator design isdirectly conducted in discrete Z-domain.7Digital redesignassumes the sampling frequency is much greater than the systemcrossover frequency, so the design equivalent approach is accurate. First a linear model of aswitching power converter is established based on some assumptions such as low-frequencysmall-signal disturbance. Based on the liner model, the controller design is done in S domain.Finally, the design of analog compensator is mapped into Z domain to complete the digitalcontroller design.It has been known that, to design a converter system incorporating feedback controlloop to meet the specification, the dynamic model of the switching converter is needed. Thepurpose of the model is to analyze and design the power system to meet the requirements. Fromthe feedback design perspective, it is desired to design a feedback system, such that the outputvoltage is precisely regulated, and the output is insensitive to disturbances from input voltageand load. For a digital controlled power converter, the modeling of the power stage is asimportant as in analog controlled power systems.The coming question is how we could implement a digital controller? As we know,power electronics systems themselves are typically a complex combination of linear, nonlinearand switching elements. High-frequency converters add another dimension of complexitybecause of their fast dynamics. Real-time power electronics systems, therefore, demand the useof high-speed data acquisition and control. Unlike analog control, digital control introduceslatency due to feedback parameter quantization and calculation times. To minimize these delays,digital control functional blocks are characterized by high data throughput and low latency, inparticular the loop compensation and DPWM modulation algorithms. While variousimplementations have been reported, the most common digital controller implementations can be8grouped into three major types: programmable signal processor (typically a digital signalprocessor (DSP)), custom hardware, or some combination of both [A5].The DSP executes discrete time calculations of control variable values in real time.Some suppliers offer DSPs with Flash memory allowing the user to address multiple systemtopologies and control strategies with a common processor platform. However, this approach islimited by DSP throughput, which, in turn, is limited by the DSP clock frequency and memoryresources. These factors adversely impact cost, size, supply current and scalability at higherDPWM frequencies.The dedicated hardware-based approach uses fixed architecture state machines toexecute the control algorithm. Hardware can be optimized for cost and performance making thisa potentially lower-cost and more efficient approach than the DSP. However, this approach lacksflexibility because the control hardware cannot be significantly changed once fabricated.Therefore, the hardware must be designed for a specific end application, which adverselyimpacts non-recurring engineering cost and time-to-market and increases design risk.The other digital controller implementation type is IC device combined the hardwarecontrolling and microprocessor management functions, so extracted maximum benefit from each.For instance, Silabs’ Si8250 is a mixed-signal device partitioned into a hardware digitalcontroller comprised of a digital signal processor (DSP) controller and an instruction basedmicrocontroller (MCU) system management processor section.Digital power provides and additional functionality and extreme flexibility to the powerconverter systems. However, there are several issues needed to be carefully considered whendesigning a digitally controlled power converter system. These issues include digitalcompensator design, resolution of ADC and DPWM, and quantization and limit word length9effect of digital coefficients. Unlike analog controllers in power converters, the digital controlledsystem is pretty probably affected by ADC’s performance. A complete analog controlled powersystem could be simpler and cheaper than a high-speed and high-resolution ADC. Therefore, thecost and performance of an ADC conflict with each other. Moreover, available microcontrollersor DSPs are now still too slow and too costly for the power converter applications. A high speedand high resolution of DPWM is also too costly for the power application. Furthermore, digitalcontroller increases the complexity of the system due to ADC and digital processing and needmore software knowledge for power designers. With advance of technology, the issuesmentioned above could be resolved in the near future. Without doubt, digital control is a trend inpower converter applications.

1.2 Dissertation Outline and Major Results

The dissertation is organized into four parts and divided into eight chapters. Part I of thedissertation consists of Chapter 1 and 2, which introduce the fundamental of digital controlledpower systems, review and compare analog and digital power systems, and modeling and designapproaches for digital controlled power converters. Part II - chapter 3 focuses on the digital PIDcompensator design methodology, design issues, and optimization and development of digitalcontrolled single-phase POL converter based on the digital controller Si8250. Part III consistingof chapters 4, 5 and 6 proposes two digital control schemes for half bridge dc-dc converter basedon the DC and AC modeling of half bridge dc-dc converters. An adaptive nonlinearcompensation algorithm is proposed for asymmetric half bridge dc-dc converter in Chapter 5,and a digital adaptive unified control scheme for half bridge converter is proposed to extend the10“duty cycle shift (DCS)” concept. Chapter 7 proposes control architecture of voltage regulationfeaturing fast transient response, which can be favorably implemented with digital control.Chapter 2 first offers an overview of modeling techniques for power converters. Analogand digital controller design techniques are discussed, respectively. Particularly, digital controltheory and design methodology are presented in this chapter. Digital management, as a part ofdigital power, is reviewed in the end o f Chapter 2.Chapter 3 addresses the digital controller design challenges and presents digital controldesign approaches to reduce the design and development time. In the conventional redesignmethod, a controller designed in S domain is mapped to digital Z domain. However, the obtainedPID coefficients in Z domain is hard to tune up due to power designers’ limited knowledge in Zdomain. Based on redesign method, Chapter 3 presents a design approach, which remaps thedigital coefficients to continuous time domain, and thus optimizes digital coefficients directly indiscrete domain. Due to limited resolution of ADC and DPWM, calculation error of digitalcoefficients and quantization effect, the performance of a digital controlled power system isdegraded. Based on the constructed PID structure, those key issues are discussed in Chapter 3. APOL demo prototype is designed and developed with digital controller- combinedMCU/hardware IC Si8250 based on the presented design approach. A nonlinear controlalgorithm trigged by large-signal output voltage transients is proposed and implemented on thePOL prototype. The experimental result shows that digital controller is favorable inimplementing advanced control techniques.Chapter 4 investigates digital controlled high-frequency-switched half-bridge dc-dc converterin term of modeling, digital controller design and control system realization. First a unifiedaverage space-state model is established for the half-bridge dc-dc converter with current doubler11rectifier considering the parasitic DC parameters. Based on the dc model, a number of importantissues of current doubler rectification in both symmetric and asymmetric HB dc-dc convertersare presented. Based on the unified small signal model, a digital controller is designed to meetthe converter system performance requirement withdigital

redesignmethod. This digitalcontroller is implemented with Si8250. Experiment results and comparison of two digitalcontrollers are also given.Chapter 5 first investigates a new half-bridge flyback-forward converter topology. In thistopology, a forward half-wave rectification is presented as the secondary rectifier associated withasymmetric half-bridge converter. Compared to the center-tapped rectification, the transformersecondary winding structures is simplified and better transformer window utilization is achieved.Compared to the current doubler rectification, only one inductor is used and the inductorutilization is improved. Meanwhile, the average small-signal model of an AHB flyback-forwardconverter is derived with the average state-space small signal modeling method. Based on themodel, the nonlinear characteristics of this topology are investigated. A nonlinear adaptivecontrol is proposed and implemented in the simulation to achieve a unified loop gain and systembandwidth under load and input voltage variations based on a digital PI compensation.In Chapter 6, DCS (Duty Cycle Shift) PWM control concept is extended to a unifiedPWM control scheme, which is between asymmetric control and the original DCS control.Corresponding mathematical model is established to analyze a half bridge DC-DC converterunder control of the proposed unified PWM scheme. With the digital controller Si8250, theimplementation of the proposed scheme is easy to implement. By changing the coefficient of thecontrol scheme, the control mode can adaptively slide from one mode to another. The digital12control offers this advanced control great flexibility. Experimental results show the performanceimprovement under control of extended DCS PWM scheme.Chapter 7 gives a brief conclusion of the dissertation work and comes to suggestions forfuture work in related directions.132 ANALOG AND DIGITAL CONTROLLED DC-DC CONVERTERS2.1 Introduction

Regulated power converter system invariably requires feedback control. In a typical dc-dcconverter application, the output voltage is regulated regardless of changes of input voltage orload. To design a converter system incorporating feedback control loop to meet the specification,we need to know how variations in the input voltage, the load current, or the duty cycle affect theoutput voltage. Mathematical model of the switching power converter is necessarily constructedto analyze and design a power converter system [B1, B2].As of today, most feedback controllers for dc-dc converters are based on analogtechnique, where comparators and amplifiers and so on analog circuits are typically utilized tocontrol a dc-dc converter. The switching frequency and compensator coefficients consist ofresistors and capacitors, where the components values are sensitive to noise and temperature. Asa result, the component tolerance and ambient temperature may affect mass production andsystem reliability. In addition, an analog system is inflexible in term of changing controlparameters such as switching frequency and PID coefficients.Digital controllers for switching power supplies offer a number of advantages including areduction of the number of passive components, programmability, flexibility, implementation ofmore advanced control algorithms and reduced sensitivity to parameter variations. In addition,digital techniques ease the communication. Those techniques provide digital communicationinterface that allows a host or system level processor to control and monitor power converters.

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This chapter will first discuss about modeling techniques of power converter since amathematical model is the representation of a power converter. Analog and digital controlled dc-dc converters as well as the associated design techniques are also discussed, respectively. Analogcontroller design approaches has been mature for many years, in the other hand, digital controllerdesign for dc-dc converter needs more research work since digital control of dc-dc conversion isa relatively new field. This chapter discusses the fundamental of digital modeling and designapproaches. In the end, digital power management is also addressed in the chapter.

2.2 Modeling of High Frequency Switching DC-DC ConvertersModeling is the representation of physical circuits by mathematical means. For a powerconverter, it is desired to design a feedback system such that the output voltage is regulatedaccurately, and is insensitive to disturbances in input voltage or in the load current. In addition,the feedback system should be stable, and properties such as transient overshoot, settling timeand steady-state regulation should meet specifications. To design a system with requirement likethose, we need a dynamic AC model of the switching power converters [B1].The basic concept to predict ac behavior is to average the converter waveforms over oneswitching cycle. Thereby the desired DC and low frequency AC components of waveforms areexposed. Since switching power converters are nonlinear systems, by perturbing and linearizingthe average model about a quiescent operating point, small-signal linearized models could beconstructed.15There are two well-known variants of ac modeling method,state-space averaging, and

circuit averaging.Averaged switch modelingas an extension of circuit averaging is also used inmany applications widely.Thestate-space averagingtechnique generates the low-frequency small-signal acequations of PWM dc-dc converters. Converter transfer functions and equivalent circuit modelscan be obtained. The converter contains independent state variables such as inductor currents andcapacitor voltages, that form the state vectorx(t), and the converter is driven by independentsources that form the input vectoru(t). The output vectory(t) contains dependent signals ofinterest. During the first subinterval, when the switches are in position 1 for timedTs, theconverter reduces to a linear circuit whose equations can be written in the following state-spaceform:1 11 1( )( ) ( )( ) ( ) ( )dx tAx t Bu tdtyt C x t Eu t= += +2-1The matrices1 1 1 1, , andAB C Edescribe the network connections during the firstsubinterval. The duty cycled(t) may now be a time-varying quantity. During the secondsubinterval, the converter reduces to another linear circuit, whose state space equations are

2 22 2( )( ) ( )( ) ( ) ( )dx tAx t B u tdty t C x t E u t= += +2-2

16The matrices2 2 2 2, , andAB C Edescribe the network connections during the secondsubinterval, of length (1 –d)Ts. It is assumed that the natural frequencies of the converternetwork are much smaller than the switching frequency. This assumption coincides with thesmall ripple approximation, and is usually satisfied in well-designed converters. It allows thehigh-frequency switching harmonics to be removed by an averaging process. In addition, thewaveforms are linearized about a dc quiescent operating point. The converter waveforms areexpressed as quiescent values plus small ac variations, as follows:( ) ( )y t Y y t= +)

These equations describe how small ac variations in the input vector and duty cycleexcite variations in the state and output vectors.The circuit averaging technique also yields equivalent results, but the derivation involvesmanipulation of circuits rather than equations. Switching elements are replaced by dependentvoltage and current sources, whose waveforms are defined to be identical to the switchwaveforms of the actual circuits. This leads to a circuit having a time-invariant topology. Thewaveforms are then averaged to remove the switching ripple, and perturbed and linearized abouta quiescent operating point to obtain a small-signal model.18To be specific, usually the switches in converters can be represented by two-port networkwith terminal waveforms1 1 2 2( ), ( ), ( ), ( )v t i t v t i t. And with any two-port network, two of theseterminal quantities can be treated as independent inputs to the switch network. The remainingtwo can be viewed as dependant signals. For example, for a boost converter, we replace theswitch network with two-port network with independent sources as inductor current1( )i t andoutput voltage2( )v t, which correctly represent the dependent output waveforms of the switchnetwork.

Figure 2-1 Boost converter example

Figure 2-2 Replace the switches with independent network

The next step is averaging circuit. The basic assumption is made that the natural timeconstants of the converter are much longer than the switching period, so that the converter19contains low-pass filtering of the switching harmonics. One may average converters over theswitching period Ts removing the switching harmonics, while preserving the low-frequencycomponents of the waveforms. So if we average the switch dependent waveforms withconsidering duty cycle, the circuit will be shown in Figure 2-3. The ( )d t′represents 1 ( )d t−

derived from the operation of the boost converter.

Figure 2-3 Averaged switch model

The model in Figure 2-3 is still nonlinear since the dependent source involves themultiplication of ( )d t′and inductor current1( )i t and output voltage2( )v t. The network can belinearized by perturbing and linearzing the converter waveforms about a quiescent operatingpoint, let

In equations 2-9, the model contains both dc and small signal as terms. Since the smallsignal assumption is satisfied the high order term likeˆˆ( ) ( )v t d t can be neglected. Then linearizedmodel is obtained in Figure 2-4. Then replace dependent generators with an ideal transformer, asin Figure 2-5.

Figure 2-4 Linearized circuit-averaged converter model

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Figure 2-5 Final linearized circuit-averaged model

Figure 2-5 shows the complete circuit-averaged model, which functions simultaneouslyas the dc and the small signal as equivalent circuit for the boost converter. This model-derivedprocedure suggests that, to obtain a small signal ac converter model we need only to replace theswitch network with its averaged model. This procedure is called averaged switch modeling.

2.3 Analog Controlled DC-DC ConvertersIt’s known that the goal of designing a control system is to change system parameters toachieve certain desired system characteristics or performance. Therefore, it is necessary to haveknowledge of system plant response and the loop response before design the feedback controller[B1, B2, B3]. The small signal models derived in section 2.2 are usually used to find the effectsof feedback on the small signal transfer functions of the regulator.A block diagram of a typical analog controlled buck small signal model is shown inFigure 2-6. The output voltage is sensed with gain( )H s, which is usually a voltage divider. Thesense outputˆ( ) ( )oH s v sis compared withrefVto generate the error signalˆ( )ev s. The objectiveof feedback loop is to makeˆ( ) ( )oH s v sequal torefVregardless of the load and line disturbances.22That is to say, if the feedback system works perfectly, the error signal should be zero. To achievesmall error signal here is one of the objectives of compensator network( )G s.ˆ ( )cv sis controlsignal generated by compensator and is fed into PWM to achieve the duty cycle gate signal fordrivers.-+ˆLId1:dinILIDˆinV dLIoVˆ( )loadi sˆ( )gV s1MVˆ( )d sˆ( ) ( )oH s v sˆ( )ev sˆ( )cv s

Figure 2-6 Analog controlled buck feedback model

So the system loop gain,( )T s, is defined in general as the product of the gains aroundthe forward and feedback paths of the loop.

( ) ( ) ( )( )vdMH s G s G sT sV=2-1023Where2( ) 0( )( )ˆ( )( 1)ino invdv sv s VG sLd sLCs sRΛΛ== =++.The loop gain is a measure of how well the feedback system works: a large loop gainleads to better regulation of the output as long as adequate phase margin is maintained. Alsostability and transient performance can be assessed using the phase margin test of loop gain. Tobe specific, the objective of compensation is to design the feedback network with suitable gainand phase delay to achieve a desirable bandwidth and sufficient phase margin, in order to makesystem achieve desired steady state accuracy, transient response, relative stability and thesensitivity to change in system parameters.There are several typical types of analog compensation consisting of an amplifier and RCnetwork. Lead compensator is also called proportional-derivative (PD) controller, which isusually utilized to improve the phase margin in a system originally consisting of a two poles. Thepossible side effect of PD compensation is that the PD compensator is sensitive to noise due tothe derivative function.Lag compensator (also called proportional-integral PI) is used to increase the lowfrequency loop gain, such that the output is better regulated at dc and at frequencies well belowthe loop crossover frequency. Combined PID compensator is to obtain both wide bandwidth andlarge dc loop gain for reduced steady-state error. The conventional Type III PID compensatorconsisting of an operational amplifier and RC network is realized in Figure 2-7 and thefrequency response is shown in Figure 2-8. It is observed that, at low frequency, the integratorpole in the same manner as the PI compensator leads to large low-frequency loop gain andaccurate regulation of low frequency component. The zero fz adds phase lead to improve the24phase margin as in PD compensator. High frequency poles fp1 and fp2 prevent the switchingripple from the disturbance of the PWM.

In generally, when one designs feedback compensation loop for power stage, it is desiredto achieve loop bandwidth below 1/5 to 1/10 of switching frequency. In this case, the phase delaydue to PWM modulation could be ignored. To achieve small steady state error and ‘flat’ closed-loop output impedance, the dc gain and low frequency gain should be as large as possible. The25loop gain is usually required to be –20dc/dec at the crossover frequency in order to havesufficient phase margin. Beyond crossover frequency, loop gain with a slope of –40 dB/decprovides good rejection of high frequency noise. The phase margin is required larger than 45 degand the Gain margin is higher than 6 dB to 12 dB in general.

2.4 Digital Controlled Power Converter and Theoretical BasisConventional controllers for dc-dc converters are based on duty ratio adjustment forvoltage regulation, and most of the commercially available controller products are based onanalog techniques. Even though the above-mentioned analog control techniques have beenmatured, they are limited by sensitivity to noise and temperature, component parameter variation,and non-flexibility.Digital controllers for switching power supplies offer a number of advantages includingreduced number of passive components, programmability, implementation of more advancedcontrol algorithms and additional power management, as well as reduced sensitivity to parametervariations.A typical digital control system is shown in Figure 2-9. The system contains a sampler todetect continuous analog signal at discrete instances of time. Before a data hold is employed toreconstruct the original signal, a digital compensator block is added to improve systemperformance [B4].

26SamplerPlantDigitalcompensatorData holdC(t)e(t)

Figure 2-9 Typical digital control system

A commonly used method of data reconstruction is polynomial extrapolation [B4]. Usinga Taylor’s series expansion, one can express )(te as:

.....)(!2)())(()()(2+−′′+−′+= nTtnTenTtnTenTete 2-11

If the first term above is used, the data hold is called a zero-order hold (ZOH), which isexpressed as )()()(0Ttutute −−=. The corresponding transfer function issesGTsh−−=1)(0, sothe frequency response of the zero-order hold can be obtained as)/(0/)/sin()(sjssheTjGωπωωπωωπωω−=, and response in frequency domain of ZOH is shown inFigure 2-10.27

Figure 2-10 Frequency responses of ZOH

According to the Shannon sampling theorem, when the input signal is reconstructed, anyfrequencies 2/sωω> will reflect into the frequency range 2/0sωω<<. This effect is calledfrequency aliasing. The frequency aliasing can be prevented either by increasingsωor by placingan analog antialiasing filter in front of the sampler. The antialiasing filter is a low pass filter thatremoves any frequency components in )(te that is greater than 2/sω, since the low pass filtersintroduce phase lag. However, the cutoff frequency of the antialiasing filter cannot be made solow as to destabilize the control system.28

From the phase plot of zero-order hold, we can see that the zero-order hold introduces thephase lag into the system. When the bandwidth of the system is equal to the sampling frequency,the phase delay goes to0180. Generally, in order to make the phase delay of the zero-order holdas small as possible, the sampling frequency should be greater than the system bandwidth by atleast 10 times, which means the phase delay goes to01810/=sω.Applying digital control theory to power converter, compared to analog controlled system,the digital controlled power converter is shown in Figure 2-11. The output voltage is sensed bysensor circuit, and then the sense outputˆ( ) ( )oH s v sis sampled by AD converter. The digitalsensed output is compared with the reference signalrefvand thus digital error signal isgenerated. The digital compensator generates the duty cycle control signal according to the inputerror signalˆ ( )cv zand feeds the control signals into PWM to get the drive signal to power stage[B5, B6].

WherePWMG andADCG are the gain of DPWM module and gain of AD converter respectively.PWMG is the ratio of PWM switching frequency and clock frequency, which is[B6]

PWMPWMClockfGf=2-11

ADCGis reverse proportional to resolution LSB of ADC, or [B6]:30

1ADCGLSB=2-22

Therefore, the DPWM and ADC introduce the gain changes to loop gain over analogcontroller, which need to be considered when designing the digital compensator.Meanwhile, the sensitivity of the AD converter, inherent time delay of thecalculation/sampling and the precision of the numerical value all affect the performance of thesystem. It is therefore necessary to give careful consideration to ADC sampling frequency andresolution design.Generally speaking, ADC resolution is determined by the precision requirements ofpower stages. That is to say, the LSB value of ADC must be smaller than the minimum requiredoutput voltage resolution. The sampling frequency of ADC should generally be 10 or 20 times ofsystem bandwidth to minimize phase delay due to sampling.DPWM acts as a DA converter, and generates pulse width modulated switchingwaveforms for driving power stage switches. Since the discrete change in duty ratio due toresolution of DPWM, there is a corresponding discrete change in output voltage. It is importantthat the value of the minimum output voltage change be smaller than the LSB size of the ADC toavoid limit cycle oscillation. Therefore, the DPWM resolution must be greater than theresolution of ADC. This point will be discussed more in Chapter 3.

312.5 Digital Controller Design MethodologyUsually, digital compensator design has two design methods:Digital redesignapproachanddirect digital designapproach [B5]. Indirect designapproach first discrete model ofsampled analog components is built. Then, the compensator design is done directly in Z-domainincluding the accurate modeling of sampling functions. With thedirect design, the frequencyresponse techniques, such as gain margin and phase margin, can be used also.Digital redesignassumes the sampling frequency is much greater than the systemcrossover frequency, so the design equivalent approach is accurate. This approach first modelsthe discrete components as analog components approximately, and then designs the analogcontroller with standard analog control technique. Finally, it maps the analog compensator intodigital with equivalent mapping methods. Since the techniques of modeling power converter tolinear continuous time domain are well known, this dissertation will focus on theDigitalredesignapproachAs mentioned in above section, usually an analog PID compensator is consists ofproportional coefficientKp, integral coefficientKiand derivative coefficient.Kd. So an s-transform PID description in continuous time domain is shown in equation 2-23,

Therefore, the discrete-time equations can be written in “difference equation” andinfinite summation forms, as the dual to the continuous-time differential and integral forms:( ) ( ) ( 1) ( 1)c c c eiTv n v n v n v nτ= − − = − − and1( ) ( )nc ekiTv n v kτ−=−∞= −∑. We will use theterminology of difference equation, but continue to use the recursive form due to theconvenience in working with the z-transform and hardware implementation [B4]. The z-transform is a discrete-time, sampled-data dual of the Laplace transform, which containsduals of all the well known intuitive characteristics and can be used to analyze constantcoefficient, linear difference equations:

Z-transform: ( ) ( )nnc cnv z v n z=∞−=−∞=∑

Laplace transform: ( ) ( )stc cv s v t e dt∞−−∞=∫2-26

34Note that withsTz e= the z-transform has the form of a sampled version of the Laplacetransform. Therefore, the s-plane stability boundary, s jω=maps to the unit circle in the z-plane (j Tz eω=). Thus our considerations before with the s-plane “left-half-plane (LHP)” willmap to considerations inside the z-plane “unit-circle”, as shown in Figure 2-14.

37Figure2-17 is the frequency response comparison of the continuous time (black), ZOH(red) and Bilinear (blue) mapping of integrator. The discrete time responses are reallyaccurate when frequency is much less than sampling frequency, but exhibits aliasing whenfrequency is larger than half of the sampling frequency.

Besides ZOH and bilinear, there are a number of other different approaches arecommonly used to estimate the transformation from continuous to discrete filter designs. Weare going to compare three widely used approaches: Bilinear, Pole-zero mapping andTriangle hold transformation [B5~B6].

38As discussed above, Bilinear transformation (BLT) basically performs approximationto integral using the area of a trapezoid between points. It is using pre-warping to map theentire left-half s-plane to inside the unit circle. This perfectly maps the stability axisjωtounit circle, and there is no aliasing consequently. The basic procedures are first selecting acritical frequency (e.g. relative to sampling, filter corner or system crossover frequency)critω

to match, and then substitute for s in ( )H s to determine ( )H z:

( )1tan/2 1( ) ( )critcritzsT zH z H sωω−= ⋅+=2-27

With Bilinear transformation (BLT) the number of poles and zeros are equal. Ifnumber of poles is more than that of zeros, additional zeros ats=∞are mapped to1z=−,and this represents the highest frequency /2sfavailable in the z-domain. If the number ofzeros is more than that of poles, additional poles ats=∞are mapped to1z = −, whichcreates problems in a compensator since it creates significant peaking as f approaches /2sf.Since the BLT maps the entire s-domain LHP once around the unit circle, there is no aliasingin added poles.The Pole-Zero Mapping method maps all poles and finite zeros using thetransformation pole or zero ats a=−using pole ataTz e−=. If there aremmore poles thanzeros (e.g. zeros ats = ∞), then mapmzeros to1z=−. This requires the ability to apply thecurrent input to the current output (as discussed below). Then set the gain of the filter suchthat the magnitude of ( )H z matches the magnitude of ( )H s at a critical frequency (such as39the crossover frequency). But we must consider how to map when the number of poles andzeros are different. If the number of poles is more than that of zeros, additional zeros ats = ∞are mapped to 1z = − and this represents the highest frequency /2sfavailable in the z-domain and is a reasonable mapping. But if the number of zeros is more than that of poles, adirect pole-zero map of pole ats=∞is to0z=. So these poles must be added to make thesystem realizable (causal). Mapping to0z=represents a1z−unit delay, which correspondsto an effectivesTedelay term in the s-domain transfer function. Alternatively, poles can beplaced in the Z-plane; this requires manual modification of pole/zero mapping. As anadditional pole is moved from0z=to1z=−, peaking is introduced in the magnituderesponse.Triangle Hold effectively extrapolates samples of the continuous time filter in a straightline, then solves for the z-transform of the samples like the following equation:2( 1) ( )( ) ( )z H sH z ZTz s−=. Triangle hold always results in the same number of poles and zeros(just as with the BLT), however, extra zeros are NOT mapped to 1z=−.There are many options for hardware implementation for this digital compensatorfunction. The delays can be implemented as a code step (DSP/micro) or a clocked latch(FPGA/custom), and multiply and add blocks can be implemented in arithmetic units,dedicated multipliers, or look-up tables, which are especially useful when a reduced set ofpossible inputs can be pre-computed. The digital coefficients can be hardwired, boot-timeprogrammable, or real-time adaptive with look-up tables, can also create non-linear controlpossibilities.

1 1 1( ) 22 1 1P I D ssz zG z K K K ffz z+−= + +−+2-28WherePKis the gain in the proportional path,IKthe gain in the integral path, andDKthegain in the derivative path andsfsampling frequency. But in most cases, to easilyimplement the digital compensator, a typical digital PID structure is shown is Figure 2-18.This PID structure is corresponding to Equation 2-29, which provides one pole and two zeros.

111( ) ( ) (1 )1P I DG z K K K zz−−= + + −−2-29

IKDKPK

Figure 2-18 Typical digital PID structure

41TermKp applies a proportional gain to the error ( )E n. As the gain term is increased, thepower supply responds faster to changes in ( )d n, but decreases system damping and stability.Step response overshoot and ringing could be caused by too a large value of the gain term.Integral termKireduces steady state error to zero. The integrator has infinite dc gain,and consequently adjusts the mean supply output voltage to drive its input to zero. The amountof time power supply takes to reach its steady state is inversely proportional to the integral gainKi. Instability and oscillation can also be caused by too large value of the integral term. Toosmall of an integral gain can result in limit cycle oscillation.The derivative termKdcan improve stability, reduce step-response overshoot and reducestep-response time. The derivative term is proportional to the rate of change of the error signal( )E n and therefore improves controller reaction time by predicting changes in the error.Following an output disturbance, the supply output will return to its nominal value faster asKd

is increased, however output overshoot could be caused by too much damping from thederivative term.

2.6

Digital Power System ManagementDigital Power is usually defined as digitally controlled power products that provideconfiguration, monitoring, and supervisory functions, which extends to full loop control. It isimportant to note that “digital power” really includes two different areas of power technology.One is “digital control”, the real-time, cycle-by-cycle control of the switches. The other area is“digital power management” [B9].42“Digital control” involves feedback control design, which is the main contribution of thisdissertation. “Digital power management” generally refers to non-real-time interaction with apower converter to:•

Configure or program a power converter’s operational characteristics oridentification information.•

Control the converter (e.g. turn it on, turn it off, adjust the output).•

Monitor the state of the converter.Digital power management is growing in popularity for two reasons. First, it allows the userto do things that are not possible with a purely analog system, like communication, power-upsequencing, margining and other configuration chores. An analog system does not allow the userto retrieve a converter’s status. The reported information can be in the form of binaryinformation or as parametric information. For example, the unit is on or off, is OK or has a fault,or has normal temperature or is operating in an overtemperature condition. The parametricinformation could be output voltage, output current or temperature. If the status information isstored in non-volatile memory and is available after a fault, this information can be very useful indetermining the real cause of failure. Because “no problem found” faults a large problem withthe system Original equipment manufacturers, the ability to retrieve a converter’s operatingcondition in the moments before a failure is reported may save a lot of money in service costs.Second, digital power management makes some tasks easier and cheaper than in theanalog domain. For example, in the application of wide range of output voltage, theprogrammability of digital power management allows to change the output voltage just bysending commands over a communications link and not by changing voltage divider. And alsofor adjustment of protection thresholds, such as output overcurrent or overtemperature, digital