Thanks, John,
Your suggestion is helpful. But the other thing I have
to face is the connections to GND and PWR. If let the
Orcad autoroute them, I am not always satified with
the result. If I do it one by one, it's boring and
time wasting. So I 'm wondering if there is a function
which can remeber what I do and just follow me or I
can combine the ICs and the connections as one unit.

wy

--- Jon Keeble <[email protected]> wrote:
> Orcad supports a concept of autoplace on a grid.
>
> You could
> (1) auto place the ICs on a grid
> (2) auto place the bypass caps on another grid of
> the same dimensions
> somewhere else
> (3) block move one set of parts over the other set
> of parts
>
> Orcad also supports the concept of component group.
>
> If you identify the IC and its bypasses as belonging
> to a group, then all
> the parts in the group can be made to
> move together.
>
> By the way: there has been some discussion of
> bypassing recently. You may
> want to review the idea of having
> a lot of identically valued bypass caps, and you may
> not need two per chip.
>
> The latest Orcad revision is 9.1, and it fixes a lot
> of problems in 9.0.
>
>
>
> -----Original Message-----
> From: Yu Wang <[email protected]>
> To: [email protected]> <[email protected]>
> Date: Wednesday, March 22, 2000 1:52 AM
> Subject: [SI-LIST] : how to combine multi components
> together with Orcad
> layout
>
>
> >Hi, all experts there,
> >I am using Orcad(Ver.9.0) Layout plus to implement
> my
> >design in which more than 30 pieces SMT
> FIFOs(TQFP128)
> >and more than 70 pieces SMT 16 bit buffers and
> >latchs(TVSOP48) are used. So I have to lay more
> than
> >250 decoupling capacitors down and connect them to
> the
> >PWR and GND pins. It's a tough work. However,
> because
> >the layout and the connections of the capacitors
> for
> >each FIFO or for each TVSOP48 chip are same. Then I
> >think I can combine one FIFO and its capacitors
> >together and regard them as one unit. It will
> simplify
> >the job definitely. But I haven't found the tool
> >within Orcad to realize it. What I am doing is
> >creating a new layout pattern in which I use
> obstacle
> >to draw some of the footprints of the chip and all
> the
> >footprints of the capacitors and all the
> connections
> >just like the old Orcad layout library did. Right
> now,
> >for prototype,
> >it can work good because I can solder the
> capacitors
> >by hand. But, what I am worrying about is that in
> the
> >future when I send it to production, the capacitors
> >would not be assembled by machine. That will be a
> >nightmare.
> >So please, give any suggestions. Thanks a lot.
> >
> >
> >
> >=====
> >Yu Wang, Ph.D
> >U.T. MD Anderson Cancer Center
> >1100 Holcombe Blvd., Box 217
> >Houston, TX, 77030
> >Tel:713-745-1671
> >
> >__________________________________________________
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