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Among Design Constraints, Power Assumes The Throne

Over the past few years, the “power problem” has
registered more strongly on the radars of system
design teams. Portable and handheld consumer
electronics keep shrinking. Hence, so do their
batteries. Meanwhile, no one wants to sacrifice runtime in
their mobile phones despite the desire to have cell phones
go a long way toward replacing laptops. Thus, the onus
falls on system-on-a-chip (SoC) designers to navigate the
tradeoffs necessary to make that happen.

In turn, the harried designers look pleadingly to the
EDA industry for methodologies that enable their quest to
subvert the laws of physics. In 2008, it’s all about power for
EDA, in terms of tools, methodologies, and even standards.
There will be a spate of announcements having to do with
low-power design in the next year or two spanning all those
areas (see the figure).

Trust, but Verify
Verification remains very challenging—
even more so when it’s tied to the increasing issues
surrounding power consumption. It’s a given that designers
must find ways to optimize and reduce energy consumption,
starting at the early phases in the design process where
there is more potential savings and greater implementation
flexibility. But what’s sometimes overlooked is that the
changes that are made to influence power can negatively
impact verification.

As a result, design teams will need to invest more than ever
in verification. Formal techniques are becoming more widely
used to snare a growing percentage of bugs, and this trend
will only accelerate. There is also broader use of electronic system-
level (ESL) methodologies as designers grasp for greater
productivity in both the design and verification spheres.

For 2008, look for power and ESL to increase the role of
sequential equivalence checking in verification. Advanced
techniques and tools such as sequential equivalence checking
will complement existing simulation-based methods.
Designers will spend more time on power optimization and
look to automation for sequential RTL clock gating.

Decent Standards
There has been some wrangling
among EDA vendors this year with respect to a uniform
expression of design intent for power that can be carried
throughout the flow. There are indications, though, that the
battle over power formats may have a mercifully swift end in
the form of a single IEEE standard.

One of the competing standards, the Unified Power Format
(UPF), was created through a joint effort involving several
key EDA players (Magma Design Automation, Mentor
Graphics, and Synopsys) as well as a number of prominent
systems houses (ARM, LSI, Infineon, Intel, Nokia, Nordic,
and Texas Instruments). The UPF, which had been donated
to Accellera, has now in turn been donated to the IEEE’s
P1801 low-power working group.

Perhaps 2008 will be the year in which the industry coalesces
around a single workable standard for the expression
of power intent, which would gladden the hearts of those
who depend on their flows to maintain interoperability in
various respects.

What's Next
On the implementation side, we’ll begin
to see a transition from timing-driven place-and-route to
power-driven place-and-route. With netlists accounting for
as much as 40% of the power budget, a shift to power-driven
place-and-route tools can help designers identify their key
sources of power consumption in a design and reduce net
capacitance. Reducing routing resources can decrease dynamic
power consumption by as much as 30% for a typical
design, some claim.

In general, 2008 could be the real breakout year for
virtual prototyping. In 2007, most large design projects
attempted to use virtual prototypes in one form or another.
In 2008, designers will be trying to improve the prototyping
process to get more acceptable speed, accuracy, and overall
usability from their prototypes. There will be efforts from
EDA vendors to improve the interoperability of high-level
models as well as their reusability.