IO-Link 2 Port Master Solution with Renesas Single Chip

Overview IO-Link 2 Port Master Solution with Renesas Single Chip

Ready to use solution

Reduces your time to market

Proved quality

Pre Certified

Chip provided from ( μPD78F806x)

With the Renesas Single Chip a scalable IO Link Master solution can build up. The SIP Chip contains all necessary modules for a full blown 2 Port IO Link V1.1 Master including data storage. The link to the Host controller is done by the TMG TE SPIAPI. All software is delivered as ANSI-C source code. The firmware of the SIP can be used as it is. A binary image is delivered also, which gives the chance to reference our test report.

The interface is based on a SPI sum telegram. Because of this technology only one SPI interface with one chip select for up to 16 SIP chips is necessary. The host library is delivered as ANSI-C source code and can be ported easily to different host controllers. Host controller requirements: