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AR# 9684

5.1i Timing Analyzer/Trace (TRCE) - Paths that lead to and from block RAM are being incorrectly constrained (BRAMS_PORTA)

Description

Paths surrounding dual-port block RAM are incorrectly constrained or not constrained at all (i.e., a particular path uses a constraint that is declared on the other clock domain of the DPR).

Solution

In this case, TNM_NET constraints are spreading to both ports of a block RAM, even though they are clocked by different signals. When a TNM traces into an instance, it includes the entire instance in that group, regardless of the pin into which it is traced. For block RAMs, this means that both ports are grouped, even if the TNM traces into an input on only one port.

In version 3.1i, new keywords were added in an attempt to address this problem, but the keywords are not currently documented. The keywords can be used as seen in the following example:

NET "CLKA_IN" TNM_NET = BRAMS_PORTA CLKA_IN;

NET "CLKA_IN" TNM_NET = FFS CLKA_IN;

NET "CLKB_IN" TNM_NET = BRAMS_PORTB CLKB_IN;

NET "CLKB_IN" TNM_NET = FFS CLKB_IN;

NOTE: You must apply the same group name to the same net multiple times in order to use multiple qualifiers.

Care should be taken when using these new qualifiers in your designs. For instance, the normal "RAMS" keyword includes both LUT RAMs and block RAMs, and always both ports of the latter. This can cause problems if the same clock signal drives both LUT RAMs and block RAMs.