Failure Mechanisms in High Voltage Printed Circuit Boards

The absence of humidity and the presence of a vacuum in the operating environment will provide a degree of safety above that provided in the minimum spacing requirements displayed in IPC-2221. Voltage transients of similar duration (10 nS) to the voltage spikes seen in power diode (see CALCE Report “Lifetime Assessment of Wedge Bonds in a High Current Diode”) will also provide an additional safety factor above minimum spacings recommended in IPC-2221. Operating temperatures above room temperature and processing defects will lead to a reduction in the electrical field stress necessary to induce dielectric failure.

A thorough physics-of-failure (PoF) approach is recommended to determine the integrity of a printed circuit board that violates IPC-2221. PoF is based upon documenting the assembly architecture, operational environment, and material properties, determining the relevant failure mechanisms, accurate measurement of the environmental loads (average and maximum electrical field stress), and the use of an acceleration factor to take into consideration degradation during operational lifetime. This assessment will provide a more accurate understanding of the reliability of the polyimide printed circuit board than a critical analysis of the spacing requirements defined in IPC-2221.

The electrical conductor spacing requirements defined in Table 6-1 in IPC-2221 are based upon research that was performed by Dr. Charles Jennings of Sandia National Laboratories. The results of Dr. Jennings research was published in IPC-TP-117, Electrical Properties of Printed Wiring Boards, in September 1976. IPC-TP-117 focused on dielectric breakdown, current carrying capacity and insulation resistance for 2-sided bare, coated, and encapsulated (epoxy and urethane) FR-5 (glass reinforced Fire-Resistant epoxy) printed wiring boards. Breakdown testing was conducted in air (767 Torr) and at low pressures (500 Torr).