We present GoldMine, a methodology for generating assertions automatically. Our method involves a combination of data mining and static analysis of the Register Transfer Level (RTL) design. The RTL design is first simulated to generate data about the design’s dynamic behavior. The generated data is then mined for "candidate assertions" that are likely to be invariants. We present both a decision tree supervised learning algorithm as well as a coverage guided mining algorithm for generating high-quality assertions. These candidate assertions are then passed through a formal verification engine to filter out the spurious candidates. The assertions that are attested as true by the formal engine are system invariants. These are then evaluated by a process of designer ranking that is provided as feedback to the data mining engine. We present results of using GoldMine for assertion generation of the RTL of Sun’s OpenSparc T2 many-threaded processor. Our results show that GoldMine can generate complex, high-coverage assertions in RTL, thereby minimizing human effort in this process.