The parasitic-aware flow reduces the number of late-stage design and layout iterations due to parasitic effects by accurately estimating pre-layout interconnect parasitics using process-based models. Additionally, interconnect parasitic constraints can also be specified in the schematic and then automatically verified in the layout. "What-if" analysis on completed layouts is also supported. This capability enables designers to easily analyze the effects of transistor parameter changes without modifying the layout and taking into account the actual layout interconnect parasitics.

The LDE-aware capability helps accelerate the layout process by reducing design iterations to accommodate LDE. This method allows designers to model the layout-dependent effects during the initial pre-layout design phase and accelerate time-to-tapeout.

Synopsys plans to demonstrate Custom Designer with the TSMC AMS Reference Flow 2.0 in several locations at DAC 2011, which takes place in San Diego, Calif. June 5 to 8 2011.