Thermals And New Technology Nodes

I recently had a friend in EDA ask me about how important thermal analysis is going to be with new FinFET technologies. I told him that I honestly haven’t had too much direct experience with 16nm FinFET yet, but in general, I’d expect thermal analysis to be somewhat more important as feature sizes shrink regardless of whether it’s FinFET or planar. Part of my reasoning behind this is that smaller feature sizes can lead to even greater concentrations in hotspots, i.e. you’re taking the same level of activity (before any increase in clock speed) and squeezing it into an even smaller chip area and that designers are using thermal “headroom” to help increase performance as shown in Figure 1 below.

Figure 1. Available Thermal Headroom Source: AMD HotChips 2013

The next question is what’s happening with leakage power? In general, I’d say that the expectations are that leakage should be better for FinFET than planar.

Figure 2 is taken from the famous presentation available here. A point that was noted here back in May 2012 though was that the move from 32nm to 22nm FinFET did see better power characteristics, but actually saw an increase in the power density for comparable parts. This would tend to make thermals more important at the smaller node.

Given the above, it may not be too surprising that people are hearing conflicting opinions on the matter. A lot of it may very well depend on the designs, the planned operating voltages and how aggressive the designers are with the technology. For aggressive designs, designers are going to want to be able to “boost” voltages and clock frequencies to squeeze as much performance out of the chip as possible.

In a multi-core scenario that means that you’re now taking “shrunken” cores and based on their surroundings (like thermals), boosting them to higher levels that use more power. In these types of scenarios, I think that thermal analysis could be crucial. If temperature gradients get too large the chip can actually fracture. In less aggressive designs, lower leakage and lower voltages may actually make the problem look a little better than the previous technology node.

A recent article at BSN had this to say about a demonstration at IDF, “The exact clockspeed was not specified. In this specific demo APUs from the Y-series were compared, that are aimed at high-performance tablets. While Haswell managed to run Cinebench with a power consumption of 6.8W, Broadwell would be able to achieve the same performance at 4.9W. That equates to a 28% reduction only by means of new manufacturing technology.”

Now, this is Intel going from “22nm” FinFET to “14nm” FinFET. I put the technology node in quotes because, quite frankly, it’s not really clear what this even means any more (see here). 16nm vs. 14nm? GLOBALFOUNDRIES said that they’re doing 14XM, (which is really based on 20nm interconnect) and Intel had to match the “14”? Perhaps this is more marketing than anything else? Anyway, I digress. Let’s just say that it’s *really* 22nm -> 14nm. Then we should expect better than a 2:1 reduction in area (that would’ve been at 15.6nm). At 14nm it should really look like ~2.5:1. If this is really the area reduction then to stay at constant power density (W/mm^2) Broadwell should drop to 2.75W instead of only 4.9W. If Intel is really seeing 22->14 type of scaling then the power density has increased by 78%. If the area scaled more like 1/2 then the power density jumped by 44%. Either way, this would imply to me that thermals are probably more important at 14 than 22.

Now if they were moving from a 22nm planar process to a 14nm FinFET process, it’s quite likely that they’d be starting at something higher than 6.8W. Say that 22nm FinFET is good for 30% better power than 22nm planar (and that may be generous) that would be the equivalent to starting at about 9.7W then the apparent jump in power density would be only about 1% at 1/2 scaling but at 22->14 scaling they would still see a 25% increase in power density.

One thought that comes to mind too is that if GLOBALFOUNDRIES and TSMC are really shoving smaller FinFET transistors under larger node (20nm) interconnect that the area and wire capacitance may not drop much from a 20nm planar design either. Are customers looking at going directly from 28nm -> FinFET or from 20nm -> FinFET? Both GLOBALFOUNDRIES and TSMC are effectively trying to pull FinFETs in a year so more customers may be jumping directly from 28nm to FinFET. Apparently Intel played the same metal pitch game at 22nm so there may not be that much difference in the interconnect sizes between Intel, TSMC and GLOBALFOUNDRIES at 14nm/16nm after all. If competitors like GLOBALFOUNDRIES, Samsung and TSMC can deliver on their FinFET nodes in 2015 and Intel is possibly pushing their FinFET production out a bit, maybe the process race will just get a bit more interesting again.

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Barry Pangrle

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Barry Pangrle is an independent power architect and consultant with expertise in power/energy-aware design and verification from a semiconductor and EDA perspective.

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[…] “node” back (or at least discontinued the practice of eliminating it). In a previous blog on Thermals and New Technology Nodes, I wrote about TSMC and GlobalFoundries using their 20nm interconnect for their first generation […]