450mm and EUV: Critical Challenges Facing the Semiconductor Industry

450mm and EUV: Critical Challenges Facing the
Semiconductor Industry

At the April 25 Silicon Valley Lunch Forum, speakers from Applied Materials, ASML, and Intel discussed the critical challenges of 450mm and EUV facing the semiconductor industry. Both subjects are expected to major topics at SEMICON West 2013, as leading players will present updated schedules and discuss critical barriers and needs.

Jim Koonmen, senior VP at ASML and GM at Brion, discussed how
the transition from 300mm to 450mm will increase manufacturing efficiencies
for very high-volume manufacturing but it’s a challenging proposition. He said that customers are increasingly
concerned about manufacturing cost. ASML will enable continuous cost
reduction, primarily through shrink, although shrink becomes a bigger risk
for customers given the overall technology risk. 450mm looks like a “doable”
cost reduction scenario, but that 450mm provides limited cost benefit for
scanning systems and that significant enhancements in overlay are required next
to wafer size increase to accommodate the roadmap.

With massive
funding from leading chip makers, ASML has initiated 450mm development programs
on two platforms and four wavelengths. He sees early version tools in
2015/16, with volume systems in 2018.

Koonmen focused on
the EUV Source Power Roadmap that ASML and Cymer collaborated on. In graph
below, see the relationship between power and productivity (wafers per hour).
In 2009, we were at about 2 W; today we are at about 55 W and 43 wafers per
hour. He said that their goal is to reach 250 W target in 2015. An update on
this progress is expected at SEMICON West.

Register by May 10 (save $150) for FREE access to over 50 hours of
technical programs and over 560 exhibitors on the
show floor.

450mm for Productivity and Cost

Source: ASML, April 25, 2013

In summary, Koonmen said that in combination
with a holistic approach, immersion technology is capable of supporting shrink
to 14 and 10 nm. Once power is sufficient for 125 wafers per hour, EUV becomes
technology of choice for high-volume production of key layers. Koonmen believes
that the industry will align on 450mm insertion point around 10nm node… “EUV first,
450mm later.” He emphasized that more and
deeper partnerships are required throughout the industry to maintain speed and
affordability.

On the other hand, Steve Johnston, Ph.D. is director, External Programs and Supplier
Technology Integration, Technology Manufacturing Engineering at Intel Corporation, focused on the development of EUV and 450mm
equipment/materials infrastructures to enable cost-effective manufacturing and
grow the industry. He said that it’s increasingly clear
that collaboration and scale are key. Two programs that will reduce the wafer
cost —the introduction of both EUV and 450mm.
Graph below compares different patterning cost options.

EUV
and 450mm Reduce Technology Driven Wafer Cost

Increase
to Enable Continued Growth

Source:
A. Steegen, IMEC, ITF 2012 (from Intel slide)

Source: Intel

Johnston
said that you can look at different process flows and different type of
equipment but “the overall notion that EUV is a vehicle to enable scaling but
also realize cost decreases is important.”
He focused on a graph that looks at 450mm in terms of dollars per
square mm of silicon processed. He noted that the historical data points for
200mm shows costs increasing to an upper control limit and then dropping back
down at the initial introduction of 300mm.
The costs increase again as new technology is introduced with
scaling. He anticipates a similar
situation with 450mm.

“I’m
not saying that’s when we are going to introduce 450mm; for us, 10nm is 2015,”
Johnston said. He stated that the point was that “at the 10nm node, we are
expecting it to exceed the historical threshold for when we have changed wafer
size transitions in the past.”

He emphasized that flawless and synchronized
execution across the industry is required to realize benefits.

About EUV, Johnston
stated that progress is being made through the efforts of many but key challenges
remain. He said that on the positive side, the intrinsic hardware performance of
EUV is roughly in line with ArF. While resist performance looks reasonable for
18-20nm half pitch, it needs improvement for tighter pitches. Also positive, he stated that integrated data
shows EUV matched to ArF for defectivity and CD control and that there is steady
progress on mask blanks.

But on the negative side, Johnston noted that source
power is gating and well behind schedule and reticle defectivity is a
significant concern — reticle inspection capability is needed in time and reticle
pellicle program is gaining momentum.

Both EUV and 450mm require close industry
collaboration across many levels and in many forms. He emphasized that while EUV
is progressing, source power and reticle defectivity remain significant
concerns.

Kirk Hasserjian, corporate VP,
Strategic Programs, Silicon Systems Group at Applied Materials, explored the key factors for a successful
transition to 450mm, including how the 450C consortium is moving forward with
the help of the companies that are involved.
He stressed that the synchronization of timelines is really important.

Source: Applied Materials, April 2013

The graph below shows how parallel
development drive the need for efficient R&D. How efficient is the industry
is with R&D dollars? Hasserjian
said, “This representative graph of what the industry is going through.
Spending for 300mm spending for R&D and then going through the platform
transitions that are needed and the infrastructure that needs to be put in for
450 — causes a bubble. Within the industry, this bubble is very difficult to
absorb.” He said it was crucial to drive for more efficient R&D, and that “flattening
out the bubble is key.”

“2018 is coming and it’s already 2013 now,” Hasserjian
stated, getting a chuckle from the audience when he noted that “that’s quite a
few years between now and then…a lot of things could happen, and typically bad
things happen” referring to issues that could push 450mm out even further,
making the transition more difficult.

Source: Applied Materials, April 2013

He also talked about collaboration — “the
need to collaborate early and intimately” with an open dialog between IC
makers, equipment suppliers and materials suppliers on these key topics: Joint
R&D, Tool Design, Fab Layout, and Technology Requirements. He also touched on Standardization,
Innovation, and the need for Supply Chain Readiness as Key Factors for a
successful transition