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EDID structure versions range from v1.0 to v1.4; all these define
upwards-compatible 128-byte structures. EDID structure v2.0 defined a
new 256-byte structure, but subsequently has been deprecated and
replaced by v1.3 which support multiple exension blocks.[citation
needed] HDMI versions 1.0–1.3c use EDID structure v1.3.[1]
Before Display Data Channel (DDC) and EDID were defined, there was no
standard way for a graphics card to know what kind of display device
it was connected to. Some VGA connectors in personal computers
provided a basic form of identification by connecting one, two or
three pins to ground, but this coding was not standardized.
The channel for transmitting the EDID from the display to the graphics
card is usually the I²C-bus, defined in DDC2B (DDC1 used a different
serial format which never gained popularity).
The EDID is often stored in the monitor in a memory device called a
serial PROM (programmable read-only memory) or EEPROM (electrically
erasable PROM) and is accessible via the I²C-bus at address 0x50.[2]
The EDID PROM can often be read by the host PC even if the display
itself is turned off.
Many software packages can read and display the EDID information, such
as read-edid[3] for Linux and DOS, PowerStrip[4] for Microsoft Windows
and XFree86 for Linux and BSD unix. Mac OS X natively reads EDID
information and programs such as SwitchResX[5] or DisplayConfigX[6]
can display the information as well as use it to define custom
resolutions.
Enhanced EDID was introduced at the same time as E-DDC; it introduced
EDID structure version 1.3 which supports multiple extensions blocks
and deprecated EDID version 2.0 structure (although it can be
supported as an extension). Data fields for preferred timing, range
limits, and monitor name are required in E-EDID. E-EDID also supports
dual GTF timings and aspect ratio change.[clarification needed]
With the use of extensions, E-EDID string can be lengthened up to 32
KBytes.
EDID Extensions assigned by VESA[edit]

Limitations[edit]
Some graphics card drivers have historically coped poorly with the
EDID, using only its standard timing descriptors rather than its
Detailed Timing Descriptors (DTDs). Even in cases where the DTDs were
read, the drivers are/were still often limited by the standard timing
descriptor limitation that the horizontal/vertical resolutions must be
evenly divisible by 8. This means that many graphics cards cannot
express the native resolutions of the most common wide screen flat
panel displays and liquid crystal display televisions. The number of
vertical pixels is calculated from the horizontal resolution and the
selected aspect ratio. To be fully expressible, the size of wide
screen display must thus be a multiple of 16×9 pixels. For 1366×768
pixel Wide XGA panels the nearest resolution expressible in the EDID
standard timing descriptor syntax is 1360×765 pixels, typically
leading to 3 pixel thin black bars. Specifying 1368 pixels as the
screen width would yield an unnatural screen height of 769.5 pixels.
Many Wide XGA panels do not advertise their native resolution in the
standard timing descriptors, instead offering only a resolution of
1280×768. Some panels advertise a resolution only slightly smaller
than the native, such as 1360×765. For these panels to be able to
show a pixel perfect image, the EDID data must be ignored by the
display driver or the driver must correctly interpret the DTD and be
able to resolve resolutions whose size is not divisible by 8. Special
programs are available to override the standard timing descriptors
from EDID data. Even this is not always possible, as some vendors'
graphics drivers (notably those of Intel) require specific registry
hacks to implement custom resolutions, which can make it very
difficult to use the screen's native resolution.[7]
EDID 1.4 data format[edit]

EDID structure, version 1.4[8][9]

Bytes
Description

0–19
Header information

0–7
Fixed header pattern: 00 FF FF FF FF FF FF 00

8–9
Manufacturer ID. This is a legacy Plug and Play ID assigned by
Microsoft, which is a big-endian 16-bit value made up of three 5-bit
letters: 00001=A, 00010=B, ... 11010=Z. E.g. 24 4d = 0 01001 00010
01101 = "IBM".

EIA/CEA-861 extension block[edit]
The CEA EDID Timing Extension was first introduced in EIA/CEA-861, and
has since been updated several times, most notably with the −861B
revision (which was version 3 of the extension, adding Short Video
Descriptors and advanced audio capability/configuration information),
−861D (published in July 2006 and containing updates to the audio
segments), −861E, and −861F which was published on June 4,
2013.[10] According to Brian Markwalter, senior vice president,
research and standards, CEA, −861F "includes a number of noteworthy
enhancements, including support for several new Ultra HD and
widescreen video formats and additional colorimetry schemes.”[11]
The most recent version, CTA-861-G[12], originally published in
November 2016, was made available for free in November 2017 after some
necessary changes due to a trademark complaint.
Version 1 (as defined in −861) allowed the specification of video
timings only through the use of 18-byte Detailed Timing Descriptors
(DTD) (as detailed in EDID 1.3 data format above). In all cases, the
"preferred" timing should be the first DTD listed in a CEA EDID Timing
Extension.
Version 2 (as defined in −861A) added the capability to designate a
number of DTDs as "native" and also included some "basic discovery"
functionality for whether the display device contains support for
"basic audio", YCbCr pixel formats, and underscan.
Version 3 (from the −861B spec) allows two different ways to specify
the timings of available digital TV[clarification needed] formats: As
in Version 1 & 2 by the use of 18-byte DTDs, or by the use of the
Short Video Descriptor (SVD) (see below). HDMI 1.0 -1.3c uses
this[which?] version.
Version 3 also includes four new optional types of data blocks: Video
Data Blocks containing the aforementioned Short Video Descripter
(SVD), Audio Data Blocks containing Short Audio Descriptors (SAD),
Speaker Allocation Data Blocks containing information about the
speaker configuration of the display device, and Vendor Specific Data
Blocks which can contain information specific to a given vendor's use.
CEA EDID Timing Extension data format - Version 3[edit]

Byte sequence
00: Extension tag (which kind of extension block this is); 02h for CEA
EDID
01: Revision number (Version number); 03h for Version 3
02: Byte number (decimal) within this block where the 18-byte DTDs
begin. If no non-DTD data is present
in this extension block, the value should be set to 04h (the byte
after next). If set to 00h,
there are no DTDs present in this block and no non-DTD data.
03: Number of Native DTDs present, other Version 2+ information
bit 7: 1 if display supports underscan, 0 if not
bit 6: 1 if display supports basic audio, 0 if not
bit 5: 1 if display supports YCbCr 4:4:4, 0 if not
bit 4: 1 if display supports YCbCr 4:2:2, 0 if not
bit 3..0: total number of native formats in the DTDs included in
this block
04: Start of Data Block Collection. If byte 02 is set to 04h, this is
where the DTD collection
begins. If byte 02 is set to another value, byte 04 is where the
Data Block Collection begins,
and the DTD collection follows immediately thereafter.

The Data Block Collection contains one or more data blocks detailing
video, audio, and speaker
placement information about the display. The blocks can be placed in
any order, and the initial
byte of each block defines both its type and its length:
bit 7..5: Block Type Tag (1 is audio, 2 is video, 3 is vendor
specific, 4 is speaker
allocation, all other values Reserved)
bit 4..0: Total number of bytes in this block following this byte
Once one data block has ended, the next byte is assumed to be the
beginning of the next data
block. This is the case until the byte (designated in Byte 02, above)
where the DTDs are known
to begin.

'''Video Data Blocks''' will contain one or more 1-byte Short
Video Descriptors (SVDs). They are
decoded as follows:
bit 7: 1 to designate that this should be considered a "native"
resolution, 0 for non-native
bit 6..0: index value to a table of standard
resolutions/timings from CEA/EIA-861:

*Short video descriptors 20 & 39 are both 1920x1080i@50 16:9 but
differ in the amount of vertical
total lines which are 1125 and 1250, respectively.

Notes: Parentheses indicate instances where pixels are repeated to
meet the minimum speed
requirements of the interface. For example, in the 720X240p case, the
pixels on each line
are double-clocked. In the (2880)X480i case, the number of pixels on
each line, and thus
the number of times that they are repeated, is variable, and is sent
to the DTV monitor by
the source device.

Increased Hactive expressions include “2x” and “4x” indicate
two and four times the reference
resolution, respectively.

The CEA/EIA-861/A standard included only numbers 1-7 and numbers 17-22
above (but not as short
video descriptors which were introduced in CEA/EIA-861B) and are
considered primary video format
timings.
The CEA/EIA-861B standard has the first 34 short video descriptors
above. It is used by HDMI 1.0-1.2a.
The CEA/EIA-861C standard has the first 59 short video descriptors
above. It is used by HDMI 1.3-1.3c
The CEA/EIA-861D standard has the first 64 short video descriptors
above. It is used by HDMI 1.4-1.4b
The CEA/EIA-861E standard has the first 107 short video descriptors
above. It is used by HDMI 2.0-2.0b
The CTA-861F standard has the first 193 short video descriptors above.
It is used by HDMI 2.1
The CTA-861G standard has the full 219 short video descriptors above.
It is used by HDMI 2.1

If a Speaker Allocation Data Block is present, it will consist of
three bytes. The second and
third are Reserved (all 0), but the first contains information about
which speakers are present in
the display device:
bit 7: Reserved (0)
bit 6: Rear Left Center / Rear Right Center present for 1,
absent for 0
bit 5: Front Left Center / Front Right Center present for 1,
absent for 0
bit 4: Rear Center present for 1, absent for 0
bit 3: Rear Left / Rear Right present for 1, absent for 0
bit 2: Front Center present for 1, absent for 0
bit 1: LFE present for 1, absent for 0
bit 0: Front Left / Front Right present for 1, absent for 0

Note that for speakers with right and left polarity, it is assumed
that both
left and right are present.

"d": byte (designated in byte 02) where DTDs begin. 18-byte DTD
strings continue for an unspecified
length (modulo 18) until a "00 00" is as the first bytes of a
prospective DTD. At this point,
the DTDs are known to be complete, and the start address of the "00
00" can be considered to be "XX"
(see below)
"XX"-126: Post-DTD padding. Should be populated with 00h
127: Checksum - This byte must be programmed such that the sum of all
128 bytes equals 00h.