Constraint management is an important step of the FPGA design flow. Mastering constraints is instrumental to achieving successful timing closure and reducing development time.

The highly interactive and practical workshop is designed to help attendees make the most of their time away from projects by providing technical information that can be used to maximize productivity back in the office.

Topics covered will include: - Steps to creating clock constraints, - Importance of Baselining a design, - Different methods to enter design constraints, - How to include variables and conditional statements within constraint files, - How to modify and remove constraints both manually and using graphical tools, - Shortcuts to create and add constraints directly from Xilinx reports and design analysis tools.