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AR# 62590

Description

I receive the following errors when I validate a block diagram, even if I connect axi_msk_bresp and axi_msk_rresp to input pins of util_vector_logic.

ERROR: [xilinx.com:ip:util_vector_logic:1.0-10] /axi_msk_bresp: Both input pins Op1 and Op2 of ip "/axi_msk_bresp" must be connected ERROR: [xilinx.com:ip:util_vector_logic:1.0-10] /axi_msk_rresp: Both input pins Op1 and Op2 of ip "/axi_msk_rresp" must be connected

What can cause this problem?

Solution

There is a known issue in Vivado 2014.2 where util_vector_logic uses [0:1] for two bits of data while AXI interconnect uses [1:0].

To work around the problem, you can create your own gate (for example AND) by using HDL code, integrate it into an IP, and then use it to replace util_vector_logic.