PCI Express 3.0 Delayed Till 2011

In a bid to ensure backwards compatibility of PCI Express 3.0 standard, PCI SIG (special interest group) has reportedly decided to delay the official setting of the standard till mid-2010. The move automatically sets back the implementation of the standard till mid-2011. It remains to be seen whether delay of the standard may also push back certain products.

The third-generation incarnation of PCI Express has numerous advantages over existing bus specifications. The PCIe 3.0 will operate at 8.0GHz speed, will have different electrical models and will move to 128-bit and 130-bit encoding schemes (from 8- and 10-bit schemes).

"In this particular case, with pushing the technology so hard, and with PCI gen 3 providing so much more capabilities but with the need to be still backwards-compatible, we had to do the diligence required to move the date,” said Al Yanes, the president of PCI SIG, reports PC Magazine web-site.

It is interesting to note that late in July Advanced Micro Devices and Hewlett Packard proposed a number of extensions for PCI Express 3.0, reports EETimes web-site.

One of the extensions is protocol multiplexing, a feature that would allow chips to dynamically switch between seven different protocols in addition to PCIe using the shared set of pins. This would allow creation of chips that would be compatible with PCIe, HyperTransport, QuickPath Interconnect, Ethernet and other buses at the same time.

Another extension is called lightweight notification and would allow co-processors or peripheral chips to talk to each other through system memory using a PCIe transaction without interrupting a host processor. For example, an Ethernet switch could respond to commands to encrypt and decrypt specific data packets while a host processor is inactive.