OK!!
how to estimate ota targets of design? especially for a 12b pipeline adc using 10 1.5bit/stage
HOW MUCH gain
HOW MUCH BANDWIDTH
HOW MUCH LOAD CAPACITOR
oh god would you please anyone share some experience? that's why does exist isn't it? if I'm wrong let me know.

Hi,
I have a boubt in the second stage of fully differential output ota. I used PMOS loads, Is it double size needed in the second stage than 1stage of PMOS loads?
Why PMOS loads needed double size than 1st stage?
Thanks!

... the ota is a (single stage) telescopic one. I understand it gives a higher output resistance
The ota's gain is approximately gm*rout, so the telescopic ota has a higher gain than the simple ota, hence provides better accuracy.

Hello all,
I understand that the larger the gain the less the effect of offset since the more its impact on the output is supressed.
But does offset itself reduce gain?
Say my input diff pair contributes significant Vt mismatch leading to offset. Would this reduce my Aol?
Thanks,
Diarmuid

Hi guys.
I am designing a Symmetrical ota and I am facing a problem. The maximum gain that I am able to get is around 50dB with a current consumption of 700uA. The GBW is aprox. 130MHz.
The circuit that I am talking about is this
I wo

A gm-C circuit (ota + capacitor) is perfectly working as integrator, if it's feeding a high impedance load, e.g. a MOSFET buffer. You should be able to find plenty of literature examples.
The resistors provide "source degeneration", reducing the ota'S gain and increasing it's linearity and input voltage range.

Whenever you use an NMOS Active Load referred to ground to drive a PMOS gain stage referred to VDD you'll have a systematic offset.
Symmetrical ota is an option or use a 2 stage amplifier (higher DC gain -> better Vp/Vn matching)

This is a simple two stage ota ... with fully differential output at first stage and single ended at the second stage. gain will be approx gm^2 (ro || ro)^2 .. assuming the all the ro and gms are same.
The MOS arm connected to VB2 is used for CMFB (Common Mode Feedback) as the first stage is fully differential.
Working of the CMFB Loop (as

I have an ota with an op-amp I-V converter giving output at unity gain on a 20Hz +/- 5V sine wave input. It works fine, basic circuit is
I wanted to swap the op amp I-V converter for a transistor output -

Dear all,
I designed a current mirror. Some papers such as said the DC gain is
A0 = gm1 x B x ro3.
I computed it with mine, but, in the simulation, the B factor doesn't seems to have any impact on the DC gain, only on the GBW. Not sure if there

PM requirement is calculated with loop gain. For a closed-loop system with a closed loop gain larger than 1, ota PM requirement is lower, i.e., can be lower than 45 degree. A buffer (closed gain is 1) has the worst situation and requires largest PM.
I do not know how to calculate a current integrator loop (...)

Hi,
I am designing a 2-stage miller ota like the one in the attachment.
I need 72dB DC-gain, currently I'm stuck on 57.8dB.
I've calculated an expression for the gain:
Av(DC) = gm1(Ro1//Ro3)(Ro5//Ro6)
What do you think of this expression?
My instinct would say:
Av(DC) = gm1(Ro1//Ro3)gm5(Ro5//Ro6)
However the last doesn't

Hello,
I'm drawing a 2 stage fully differential miller ota with 2 CMFB networks. These CMFB networks are ideal and contain a vcvs with a gain "Acm". However, when I put 2 instances on my schematic and use the ADE (Analog Design Environment) to retrieve the variables I only get 1 variable Acm for the 2 blocks. I wish to control them independently

I'm going to design a two stage folded cascode ota.
first stage is folded cascode(nmos input pair) to provide gain
second stage is common source to increase the output range
compensation is cascode compensation
My question is in my circuit, how to find poles and zeroes?
It had a compex trasformer Eq. & I couldnt simple it.
Thanks a

I have a major problem and i am out of ideas so any suggestions will be great....
below is the image of the circuit i am trying to simulate: its for an ota using 90nm technology: the requirements are
1. high linearity 2. high gain 3.low noise... the only difference in my circuit from the one in the image is that i am using all PMOSs
1) http

I am designing an ota but i am getting a very small linearity range... i need to increase the linearity.. I added passive resistors at the differential pair but i am not getting any improvements... so any ideas???
Thanks

Dear all,
I am trying to understand the feedback connection with the ota in band-gap reference. The following is the circuit i am using now:86694
Can anyone please tell me why the branch in which BJTs in serial with the resistor is connected to the positive port of the ota, not the negative one?
Thank you very much!

Hello Analog guys
I designed a current mirror ota with a partial positive feedback, the circuit is like the one I attached from Gregorian book, Figure Nr. 3.41.
After I finished the design , I have simulated the circuit with and without the positive feedback as shown in the first and second image respectively.
Here I have a couple of ques

Hello,
I need to design an ota in 0.13 ?m CMOS (1.2 V) technology. My specs are:
Av=80 db
GBW>250 MHz.
Slew rate > 100v/?s
It is possible with a single telescopic stage to achieve this results?
Any idea about the power need for achieve this specs?
Regards

I have been trying to find some papers on this but am coming up short.
I have heard that if you place a very broad band ota in parallel with a narrow band, the narrow band helps keep the loop stable.
But what is the exact impact? If ota1 has BW of x and ota has bw of 3x, is the bandwidth of the system, 4x/2=2x? or is it 4x? I also (...)

Hi!,
We have just designed a 2 stage ota with a cascoded differential pair as the first stage and a common source amplifier as the second stage. The gain is 59.3dB and we need to measure the slew rate. Can anyone please tell me how to go about measuring the slew rate?
The method that we were using is to supply a 1Vpp pulse at the input and us

Am I understanding this correctly. I have an ota and given that the f3db is 60 and I want to increase its gain but the as the gain increases the value of the f3db decreases and the ouput resistance also increases and vice versa so there's no way to have a high increase in gain of ota while maintaining the (...)

Hello
I am designing a class A amplifier to put later on the output of my operation amplifier, I have found that the output is not symmetrical about the half of the supply voltage as it the case of my op-amp, you can see that the gain at VDD= 2.5 the gain is zero ehich will kill the gain of the op-amp when I connect it.
So how can I (...)

Dear friend
I am designing a fully differential amplifier for the first time. I would design the CMFB for the ota shown in image
I would use continuous time CMFB, while all the references I have only discussed the SC CMFB for this circuit. If any one can help me I will be tha

The problem isn't clear. You are showing an ota topology in post #3, it basically "mirrors" the bias current of the input stage into the output node (possibly with a gain factor in the current sources), thus the maximum output current will be symmetrical and meet your intention of symmetrical slew rate with capacitive load.

I am a beginner in Cadence,I am designing a two stage ota. My design has folded cascoded configuration in the first stage with class AB along with current mirrors in the 2nd stage.I have attained saturation for all transistors except for one,which is now operating in linear region. My output shows amplification,but i get a triangle wave with ac ga

Dear Friends:
Several months ago,I have designed a two-stage ota and fabricated in 0.18um CMOS technology.Now,I faced with some problems in testing my ota.I have already worked out some close-loop test procedures for the ota,however,recently I have seen some papers showing their open-loop test results using network analyzer.I have no idea (...)

Hi,
I have very basic question in mind. How do we decide DC gain of OPAMP or ota irrespective of application ? Does it decide on basis of settling error voltage or it has some other relation.
If you have any good and basic refernce for it. then, please share it.

Hi Varunkant2k:
Thanks for your help.
Voltage mode have High impedance nod
and the High impedance you mentioned is the Rout of the EA?
And now I am confused about the function of EA, usually, its function is described as "amplify the error signal ", however, after adding the compensation net, the gain is determined by the ratio of

Hello guys.
i am designing a ota in weak inversion... and the voltage gain looks good but the gm behavior shows very low values at low frequencies it this normal?
I calcuate that from the ratio of the output current over the voltage input. It this correct?
73483
its only for gathering the idea for weak inversion

HI i am new to the analog based circuit design.. I have been designing folded cascode ota for 9-bit 200MSPS pipeline ADC in 90nm CMOS technology with the following specifications
power supply =1v
dc gain= 62db
unity gain b/w =1.162Ghz
phase margin =68.38deg
But when i simulate the following ota for dc (...)

Hello everyone,
I have designed ota for hearing aid application. I want to measure THD of ota. How can i measure it?
The value that i get is it in percentage or not?
Another query is that gain of the ota is the ratio of output current to input voltage or ratio of output voltage to input voltage?
please help me i (...)

I am simulating a fully differential ota for a class project. I have the basic specs where I would like them (like gain,BW,PM). But, when I run my transient sims, I am seeing Vout and Voutb are not symmetric. Both are pulled up to about the common mode votlage of 1.1V and then are clipped. My differential output looks okay (Does this imply it i

Hi,
We have designed 14 bit pipelined ADC, which is working up to 120MSPS at schematic level. But, after post layout, I see a settling gets delayed in MDAC (gain of 4) output. I see the dip before raising or very under damped behaviour. I found ota layout causing more than 1.5 pf extra parasitic capacitance in layout.

Hello every one,
I have attached design of programmable ota. but i dont know how to measure parameters like gain, phase, CMRR, PSRR, slew rate etc. To measure all this parameters i have used one test bench which is also attached here.
But problem is that i have measured gain in db, which is negative and phase is also negative.
In test (...)

I need some help on tunable transconductance(variable gain) amp plz provide all link available
Do you know that commercial transconductance amplifiers (ota's) in most cases (if not in all) are gain-tunable using the external bias current Iabc (abc=amplifier bias current) ?

Hello everyone,
I want to plot transconductance(gm) Vs. Vid curve for ota. How to draw it plz show me method?
And also tell me how to create emacs file for spectre simulator to perform transconductance measurements?
Thank you in advance.

Sir,Thanxa lot for your helped me to some extent but m finding difficulty in transient response??
But still i find problem in calculating gain margin??....can u tel me how to calculate it from plots???
For a wideswingfoldedota i got phase margin of this value correct??...

I'm trying to learn about the different types of differential amp/ota configurations. My aim is to build a VCA based on either a differential pair or a discrete ota.
The differential amplifier config above gives me unity gain. F

Hi ,I?m designing a 14bit 100MS/s Pipelined ADC (1.8v 0.18um CMOS) and need to an ota(for front end T/H and MDAC of first stage) with this minimum requirements DC gain:96dB and Fugbw:662MHz with CL=10pf(CS =6.6pf)my main question is that how much margin must be considered in ota design(how much DC gain and unity (...)

Hi,
The transistor level specifications would depend on the ota architecture you are using.
But, in general ota is similar to any TA; TA amplifies single-ended signals whereas the difference of two signals will be amplified in an ota.
* The gain of ota is still Gm*Ro
* slew rate is Imax/Cload
etc.
I (...)

Hi all....
I am designing peak detector for adaptive flash ADC
While designing I stuck with the topology for ota?
Please help me in deciding whether to use Coscade ota or gain boosting ota or any other type??
Please provide me with some details and study materials
Please provide me link.
My mail ID is

signal BANDWiDTH is 25 khz...n my sampling frequency is 100 MHZ...i need to determine R and C values of integrator... for the first and second integrator confused in choosing them.... and how abt the constraints on first and Second ota of on gain n bandwidth....
can u plz help me out R and C values of using SCR feedb

Im designing an ota with 0.18um Umc tech....a total current of 400 uA is used...when i plot gain in db vs input common mode level... im gettin a very sharp spike at 0.9v and the gain is significantly reducing after and before 0.9v... the response i hav got is correct or not... if nt correct then hw shal i reduce the over (...)

LAW,
is it wise to measure the open-loop gain for a device that has a 10kohms output resistance?
Such a device can be classified (nearly) as an ota.
Do you intend to measure without any (nominal) load?