Solder joints in electronic assemblies are typically subjected to thermal cycling, either in actual application or in accelerated life testing used for qualification. Mismatches in the thermal expansion coefficients of the assembly materials leads to the solder joints being subjected to cyclic (positive/negative) mechanical strains and stresses. This cyclic loading leads to thermomechanical fatigue damage that involves damage accumulation, crack initiation, crack propagation, and failure. While the effects of aging on solder constitutive behavior (stress-strain and creep) have been examined in some detail, there have been no prior studies on the effects of aging on solder failure and fatigue behavior. In this investigation, we have examined the effects of aging on the cyclic stress-strain behavior of lead free solders. Uniaxial SAC lead free solder specimens were subjected to cyclic (tension/compression) mechanical loading. Samples were cyclically loaded under both strain control (constant positive and negative strain limits) and stress control (constant positive and negative stress limits). The hysteresis loop size (area) was calculated from the measured cyclic stress-strain curves for a given solder alloy and temperature. This area represents the strain energy density dissipated per cycle, which can be typically correlated to the damage accumulation in the joint. The tests in this investigation were performed with SAC105 solder alloy. Prior to cyclic loading, the specimens in this study were aged (preconditioned) at 125 °C for various aging times (0-6 months). From the recorded cyclic stress strain curves, we have been able to characterize and empirically model the evolution of the solder hysteresis loops with aging. Similar to solder stress-strain and creep behaviors, there is a strong effect of aging on the hysteresis loop size (and thus the rate of damage accumulation) in the solder specimens. The observed degradations in the fatigue/cyclic behavior of the lead free solders are highly accelerated for lower silver content alloys (e.g., SAC105), and for aging and testing at higher temperatures. In our current work, we are also subjecting aged solder samples to cyclic loading until failure occurs. Our ultimate goal is to understand the effects of aging on the thermomechanical fatigue life.

Electronic products are subjected to high G-levels during mechanical shock and vibration. Failure-modes include solderjoint failures, pad cratering, chip-cracking, copper trace fracture, and underfill fillet failures. The second-level interconnects may be experience high-strain rates and accrue damage during repetitive exposure to mechanical shock. Industry migration to leadfree solders has resulted in proliferation of a wide variety of solder alloy compositions. Few of the popular tin-silver-copper alloys include Sn1Ag0.5Cu and Sn3Ag0.5Cu. The high strain rate properties of leadfree solder alloys are scarce. Typical material tests systems are not well suited for measurement of high strain rates typical of mechanical shock. Previously, high strain rates techniques such as the Split Hopkinson Pressure Bar (SHPB) can be used for strain rates of 1000 per sec. However, measurement of materials at strain rates of 1-100 per sec which are typical of mechanical shock is difficult to address. In this paper, a new test-technique developed by the authors has been presented for measurement of material constitutive behavior. The instrument enables attaining strain rates in the neighborhood of 1 to 100 per sec. High speed cameras operating at 300,000 fps have been used in conjunction with digital image correlation for the measurement of full-field strain during the test. Constancy of cross-head velocity has been demonstrated during the test from the unloaded state to the specimen failure. Solder alloy constitutive behavior has been measured for SAC105, and SAC305 solders. Constitutive model has been fit to the material data. Samples have been tested at various time under thermal aging at 25°C and 125°C. The constitutive model has been embedded into an explicit finite element framework for the purpose of life-prediction of leadfree interconnects. Test assemblies has been fabricated and tested under JEDEC JESD22-B111 specified condition for mechanical shock. Model predictions have been correlated with experimental data.

Goldmann Constants and Norris-Landzberg acceleration factors for lead-free solders have been developed based on ridge regression models (RR) for reliability prediction and part selection of area-array packaging architectures under thermomechanical loads. Ridge regression adds a small positive bias to the diagonal of the covariance matrix to prevent high sensitivity to variables that are correlated. The proposed procedure proves to be a better tool for prediction than multiple-linear regression models. Models have been developed in conjunction with Stepwise Regression Methods for identification of the main effects. Package architectures studied include, BGA packages mounted on copper-core and no-core printed circuit assemblies in harsh environments. The models have been developed based on thermo-mechanical reliability data acquired on copper-core and no-core assemblies in four different thermal cycling conditions. Packages with Sn3Ag0.5Cu solder alloy interconnects have been examined. The models have been developed based on perturbation of accelerated test thermo-mechanical failure data. Data has been gathered on nine different thermal cycle conditions with SAC305 alloys. The thermal cycle conditions differ in temperature range, dwell times, maximum temperature and minimum temperature to enable development of constants needed for the life prediction and assessment of acceleration factors. Norris-Landzberg acceleration factors have been benchmarked against previously published values. In addition, model predictions have been validated against validation datasets which have not been used for model development. Convergence of statistical models with experimental data has been demonstrated using a single factor design of experiment study for individual factors including temperature cycle magnitude, relative coefficient of thermal expansion, and diagonal length of the chip. The predicted and measured acceleration factors have also been computed and correlated. Good correlations have been achieved for parameters examined.

In this paper, fracture properties of Sn3Ag0.5Cu leadfree high strain-rate solder-copper interface have been evaluated and validated with those from experimental methods. Bi-material Copper-Solder specimen have been tested at strain rates typical of shock and vibration with impact-hammer tensile testing machine. Models for crack initiation and propagation have been developed using Line spring method and extended finite element method (XFEM). Critical stress intensity factor for Sn3Ag0.5Cu solder-copper interface have been extracted from line spring models. Displacements and derivatives of displacements have been measured at crack tip and near interface of bi-material specimen using high speed imaging in conjunction with digital image correlation. Specimens have been tested at strain rates of 20s-1 and 55s-1 and the event is monitored using high speed data acquisition system as well as high speed cameras with frame rates in the neighborhood of 300,000 fps. Previously the authors have applied the technique of XFEM and DIC for predicting failure location and to develop constitutive models in leaded and few leadfree solder alloys [Lall 2010a]. The measured fracture properties have been applied to prediction of failure in ball-grid arrays subjected to high-g shock loading in the neighborhood of 12500g in JEDEC configuration. Prediction of fracture in board assemblies using explicit finite element full-field models of board assemblies under transient-shock is new. Stress intensity factor at Copper pad and bulk solder interface is also evaluated in ball grid array packages.

Electronic assemblies have been monitored using state-space vectors from resistance spectroscopy, phase-sensitive detection and particle filtering (PF) to quantify damage initiation, progression and remaining useful life of the electronic assembly. A prognostication health management (PHM) methodology has been presented for electronic components subjected to mechanical shock and vibration. The presented methodology is an advancement of the state-of-art, which presently focuses on reactive failure detection and provides limited or no insight into the system reliability and residual life. Previously damage initiation, damage progression, and residual life in the pre-failure space has been correlated with microstructural damage based proxies, feature vectors based on time, spectral and joint time-frequency characteristics of electronics [Lall2004a-d, 2005a-b, 2006a-f, 2007a-e, 2008a-f]. Precise resistance measurements based on the resistance spectroscopy method have been used to monitor interconnects for damage and prognosticate failure [Lall 2009a,b, 2010a,b, Constable 1992, 2001]. In this paper, the effectiveness of the proposed particle filter and resistance spectroscopy based approach in a prognostic health management (PHM) framework has been demonstrated for electronics. The measured state variable has been related to the underlying damage state using non-linear finite element analysis. The particle filter has been used to estimate the state variable, rate of change of the state variable, acceleration of the state variable and construct a feature vector. The estimated state-space parameters have been used to extrapolate the feature vector into the future and predict the time-to-failure at which the feature vector will cross the failure threshold. Remaining useful life has been calculated based on the evolution of the state space feature vector. Standard prognostic health management metrics were used to quantify the performance of the algorithm against the actual remaining useful life. Application to part replacement decisions for ultrahigh reliability system has been demonstrated. Using the technique described in the paper the appropriate time to reorder a replacement part could be monitored, and defended statistically. Robustness of the prognostication algorithm has been quantified using standard performance evaluation metrics.

Electronic systems under extreme shock and vibration environments including shock and vibration may sustain several failure modes simultaneously. Previous experience of the authors indicates that the dominant failure modes experienced by packages in a drop and shock frame work are in the solder interconnects including cracks at the package and the board interface, pad cratering, copper trace fatigue, and bulk failure in the solder joint. In this paper, a method has been presented for failure mode classification using a combination of Karhunen Loéve transform with parity-based stepwise supervised training of a perceptrons. Early classification of multiple failure modes in the pre-failure space using supervised neural networks in conjunction with Karhunen Loéve transform is new. Feature space has been formed by joint time frequency analysis. Since the cumulative damage may be accrued under repetitive loading with exposure to multiple shock events, the area array assemblies have been exposed to shock and feature vectors constructed to track damage initiation and progression. Error Back propagation learning algorithm has been used for stepwise parity of each particular failure mode. The classified failure modes and failure regions belonging to each particular failure modes in the feature space are also validated by simulation of the designed neural network used for parity of feature space. Statistical similarity and validation of different classified dominant failure modes is performed by multivariate analysis of variance and Hoteling's T-square. The results of different classified dominant failure modes are also correlated with the experimental cross sections of the failed test assemblies. The methodology adopted in this paper can perform real-time fault monitoring with identification of specific dominant failure mode and is scalable to system level reliability.

In this work, the viscoplastic mechanical response of a typical underfill encapsulant has been characterized via rate dependent stress-strain testing over a wide temperature range, and creep testing for a large range of applied stress levels and temperatures. A specimen preparation procedure has been developed to manufacture 80 x 5 mm uniaxial tension test samples with a specified thickness of .5 mm. The test specimens are dispensed and cured with production equipment using the same conditions as those used in actual flip chip assembly, and no release agent is required to extract them from the mold. Using the manufactured test specimens, a microscale tension-torsion testing machine has been used to evaluate stressstrain and creep behavior of the underfill material as a function of temperature. Stress-strain curves have been measured at 5 temperatures (25, 50, 75, 100 and 125 C), and strain rates spanning over 5 orders of magnitude. In addition, creep curves have been evaluated for the same 5 temperatures and several stress levels. With the obtained mechanical property data, several viscoelastic and viscoplastic material models have been fit to the data, and optimum constitutive models for subsequent use in finite element simulations have been determined.

The consumer electronics industry stands at a critical juncture where manufacturers strive to incorporate more functionality in smaller packages. In the highly competitive consumer electronics market, a continued demand for products with smallest possible form-factor yet high functionality has led to the proliferation of 3D packaging technologies. Package-on- Package (PoP) architectures, in particular have attracted a lot of interest, especially in portable electronics industry. The advantages of these stacked 3D architectures include simplified and compact design, savings of board space allowing for more package landings, reduced pin counts and optimized production costs. While a lot of recent research, in the field of PoP architectures has been focused on development of optimum process flows and warpage control during reflow, the effects of reflow parameters on the quality of PoP build and the associated reflow defects including warpage have not been extensively researched. Additionally, studies on reliability issues associated with PoP assemblies in drop and shock environments are scarce. Since PoP architectures find their applications mainly in portable electronics, which are susceptible to frequent drops and careless handling at the hand of the consumer, the reliability of PoP architectures in environments representative of the real world is critical to their success in the industry. In this study, Single component PoP test vehicles have been fabricated as per JEDEC standards for quantifying the reliability of PoP packages in drop and shock. Daisy chained double-stack PoP components have been used to identify failure for subsequent drop/shock performance analysis. Experimental strain data acquired using Digital Image Correlation and high speed continuity data- for identifying failure has been used in conjunction with validated FE simulations of drop test events; for development of life prediction models for PoP architectures. Validated node based global-local FE simulations are used to predict strains in critical solder balls in both layers of the PoP stack. The drop/shock reliability studies and life prediction models presented in this work, present an insight into PoP failures and eliminate the need for exhaustive testing procedures.

The thermal performance of an electronic device is heavily dependent on the properties of the printed circuit board (PCB) to which it is attached. However, even small variations in the process used to fabricate a PCB can have drastic effects on its thermal properties. Therefore, it is necessary to experimentally verify that each stage in the manufacturing process is producing the desired result. Steady state thermal resistance measurements, taken with a comparative cut bar apparatus based on ASTM D 5470-06, were used to compare PCBs manufactured from the same design by different vendors and the effects of vias filled with epoxy versus unfilled vias on the thermal resistance of a PCB. It was found that the thermal resistance of the PCBs varied by as much as 30% between vendors and that the PCBs with epoxy filled vias had a higher thermal resistance than those with unfilled vias, possibly due to the order in which the manufacturing steps were taken.

Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of flip chip area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials, second level CBGA solder joints, organic PCB, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high CTE ceramic substrates, lead free solder joints, higher levels of power generation, and larger heat sinks with increased clamping forces. Die stress effects are of concern due to several reasons including degradation of silicon device performance (mobility/speed), damage that can occur to the copper/low-k top level interconnect layers, and potential mechanical failure of the silicon in extreme cases. In this work, we have used test chips containing piezoresistive sensors to measure the buildup of mechanical stresses in a microprocessor die after various steps of the CBGA assembly process, as well as due to heat sink clamping. The developed normal stresses are compressive (triaxial compression) across the die surface, with significant in-plane and out-of-plane (interfacial) shear stresses also present at the die corners. The compressive stresses have been found to increase with each assembly step (flip chip solder joint reflow, underfill dispense and cure, lid attachment, CBGA assembly to PCB, and heat sink clamping). Levels exceeding 500 MPa have been observed for extremely high heat sink clamping forces. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 x 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to the high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the individual test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. A metallic lid and second level solder balls were attached to complete the flip chip ceramic BGA components. After every packaging step (flip chip solder ball reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. Finally, CBGAs with the stress sensing chips were soldered to organic PCB test boards. A simulated heat sink loading was then applied, and the stresses were measured as a function of the clamping force. The heat sink clamping pressure distribution was monitored using in-situ resistive sensors in the TIM2 position between the lid and heat sink. The measured stress changes due to heat sink clamping where correlated with finite element simulations. With suitable detail in the models, excellent correlation has been obtained.

The microstructure, mechanical response, and failure behavior of lead free solder joints in electronic assemblies are constantly evolving when exposed to isothermal aging and/or thermal cycling environments. Over the past several years, we have demonstrated that the observed material behavior variations of Sn-Ag-Cu (SAC) lead free solders during room temperature aging (25 C) and elevated temperature aging (50, 75, 100, 125, and 150 C) were unexpectedly large and universally detrimental to reliability. The measured stress strain data demonstrated large reductions in stiffness, yield stress, ultimate strength, and strain to failure (up to 50%) during the first 6 months after reflow solidification. In addition, even more dramatic evolution was observed in the creep response of aged solders, where up to 100X increases were found in the steady state (secondary) creep strain rate (creep compliance) of lead free solders that were simply aged at room temperature. For elevated temperature aging at 125 C, the creep strain rate was observed to change even more dramatically (up to 10,000X increase). There is much interest in the industry on establishing optimal SAC-based lead free solder alloys that minimize aging effects and thus enhance thermal cycling and elevated temperature reliability. During the past year, we have extended our previous studies to include several doped SAC alloys (SAC-X) where the standard SAC alloys have been modified with small percentages of one or two additional elements (X). Materials under consideration include SAC0307-X, Sn-.7Cu-X, SAC305-X, SAC3595-X and SAC3810-X. Using dopants (e.g. Bi, In, Ni, La, Mg, Mn, Ce, Co, Ti, etc.) has become widespread to enhance shock/drop reliability, and we have extended this approach to examine the ability of dopants reduce the effects of aging and extend thermal cycling reliability. In the current paper, we concentrate on showing results for SACXTM, which has the composition Sn-0.3Ag-0.7Cu-X with X = 0.1Bi. We have performed aging under 5 different conditions including room temperature (25 C), and four elevated temperatures (50, 75, 100 and 125). We have also extended the duration of aging considered in our experiments to up to 12 months of aging on selected alloys. Variations of the mechanical and creep properties (elastic modulus, yield stress, ultimate strength, creep compliance, etc.) have been observed. We have correlated the aging results for the doped SAX-X alloy with our prior data for the "standard" lead free alloys SACN05 (SAC105, SAC205, SAC305, SAC405). The doped SAC-X alloy shows improvements (reductions) in the aging-induced degradation in stiffness, strength, and creep rate when compared to SAC105, even though it has lower silver content. In addition, the doped SAC-X alloy has been observed to reach a stabilized microstructure more rapidly when aged. Mathematical models for the observed aging variations have been established so that the variation of the stress-strain and creep properties can be predicted as a function of aging time and aging temperature.

A technique has been developed for monitoring the structural damage accrued in BGA interconnects during operation in vibration environments. The technique uses resistance spectroscopy based state space vectors, rate of change of the state variable, and acceleration of the state variable in conjunction with Extended Kalman Filter and is intended for the pre-failure time-history of the component. Condition monitoring using the presented technique can provide knowledge of impending failure in high reliability applications where the risks associated with loss-of-functionality are too high to bear. The methodology has been demonstrated on SAC305 leadfree area-array electronic assemblies subjected to vibration. Future state of the system has been estimated based on a second order Extended Kalman Filter model and a Bayesian Framework. The measured state variable has been related to the underlying interconnect damage using plastic strain. Performance of the prognostication health management algorithm during the vibration test has been quantified using performance evaluation metrics. Model predictions have been correlated with experimental data. The presented approach is applicable to functional systems where corner interconnects in area-array packages may be often redundant. Prognostic metrics including α-λ metric, beta, and relative accuracy have been used to assess the performance of the damage proxies. The presented approach enables the estimation of residual life based on level of risk averseness.

Mixed formulation solder alloys refer to specific combinations of Sn-37Pb and SAC305 (96.5Sn-3.0Ag-0.5Cu). They present a solution for the interim period before Pb-free electronic assemblies are universally accepted. In this work, the surfaces of mixed formulation solder alloys have been studied by in-situ and real-time Auger electron spectroscopy as a function of temperature as the alloys are raised above the melting point. With increasing temperature, there is a growing fraction of low-level, bulk contaminants that segregate to the alloy surfaces. In particular, the amount of surface C is nearly ~50-60 at. % C at the melting point. The segregating impurities inhibit solder ability by providing a blocking layer to reaction between the alloy and substrate. A similar phenomenon has been observed over a wide range of (SAC and non-SAC) alloys synthesized by a variety of techniques. That solder alloy surfaces at melting have a radically different composition from the bulk uncovers a key variable that helps to explain the wide variability in contact angles reported in previous studies of wetting and adhesion.

Wetting of Sn-Ag-Cu (SAC) series solder alloys to solid substrates is strongly influenced by surface segregation of low-level bulk impurities in the alloys. We report in situ and real-time Auger electron spectroscopy measurements of SAC alloy surface compositions as a function of temperature as the alloys are taken through the melting point. A dramatic increase in the amount of surface C (and frequently O) is observed with temperature, and in some cases the alloy surface is nearly 80 at.% C at the melting point. The C originates from low-level impurities incorporated during alloy synthesis and inhibits wetting because C acts as a blocking layer to reaction between the alloy and substrate. A similar phenomenon has been observed over a wide range of (SAC and non-SAC) alloys synthesized by a variety of techniques. That solder alloy surfaces at melting have a radically different composition from the bulk uncovers a key variable that helps to explain the wide variability in contact angles reported in previous studies of wetting and adhesion.

An anomaly detection and failure mode classification method has been developed for electronic assemblies with multiple failure modes. The presented prognostic health management method targets the pre-failure space of the electronic assembly life to trigger repair or replacement of impending failures. Presently, health monitoring systems focus on reactive diagnostic detection of failure modes. Examples of diagnostic detection include the built in self test and on-board diagnostics. In this paper, damage pre-cursors from timespectral measurements of the electronic assemblies has been measured under applied vibration and shock stimulus. The time-evolution of spectral content of the damage pre-cursors has been studied using joint time frequency analysis in a fullfield manner on the printed circuit assembly. Frequency moments have been used to build a feature vector. Evolution of the feature vector with damage initiation and progression has been studied under shock and vibration. The feature vector from multiple locations in the board assemblies has been mapped into a de-correlated feature space using Sammon's mapping. Several chip-scale packages have been studied, with SAC305 and SAC405 leadfree second-level interconnects. Transient strain has been measured during the drop-event using digital image correlation and high-speed cameras operating at 100,000 fps. Continuity has been monitored simultaneously for failure identification. In addition, explicit finite element models have been developed and various kinds of failure modes have been simulated such as solder ball cracking, trace fracture, package falloff and solder ball failure. The neural net has been trained using simulated data-sets created from error-seeded models with specific failure modes. The neural net has then been used to identify and classify the failure modes in board assemblies experimentally. Supervised learning of multilayer neural net in conjunction with parity has been used to identify the hardseparation boundaries between failure mode clusters in the de-correlated feature space. The assemblies have been crosssectioned to verify the identified failure modes. Crosssections indicate that the experimentally measured failures modes correlate well with the position of the cluster in the decorrelated feature space.

Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of flip chip area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials, second level CBGA solder joints, organic PCB, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high CTE ceramic substrates, lead free solder joints, higher levels of power generation, and larger heat sinks with increased clamping forces. Die stress effects are of concern due to several reasons including degradation of silicon device performance (mobility/speed), damage that can occur to the copper/low-k top level interconnect layers, and potential mechanical failure of the silicon in extreme cases. In this work, we have used test chips containing piezoresistive sensors to measure the buildup of mechanical stresses in a microprocessor die after various steps of the assembly process, as well as due to heat sink clamping and subsequent powered operation. The developed normal stresses are compressive (triaxial compression) across the die surface, with significant in-plane and out-of-plane (interfacial) shear stresses also present at the die corners. The compressive stresses increase with each assembly step (flip chip solder joint reflow, underfill dispense and cure, lid attachment, CBGA assembly to PCB, and heat sink clamping). Levels exceeding 500 MPa have been observed for extremely high heat sink clamping forces. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 x 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to the high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the individual test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. A metallic lid and second level solder balls were attached to complete the flip chip ceramic BGA components. After every packaging step (flip chip solder ball reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were remeasured, so that the die stresses induced by each assembly operation could be characterized. Finally, CBGAs with the stress sensing chips were soldered to organic PCB test boards. A simulated heat sink was then attached, and the stresses were measured as a function of the clamping force. The heat sink clamping pressure distribution was monitored using in-situ resistive sensors in the TIM2 position between the lid and heat sink. The experimental test chip stress measurements were correlated with finite element simulations of the packaging process. A novel sequential modeling approach has been utilized to predict the build-up of compressive stress. The utilized method incorporates precise thermal histories of the packaging process, element creation, and nonlinear temperature and time dependent material properties. With suitable detail in the models, excellent correlation has been obtained with the sensor data throughout all packaging processes and during simulated heat sink clamping.

Electronic products are subjected to high G-levels during mechanical shock and vibration. Failure-modes include solder-joint failures, pad cratering, chip-cracking, copper trace fracture, and underfill fillet failures. The second-level interconnects may be experience high-strain rates and accrue damage during repetitive exposure to mechanical shock. Industry migration to leadfree solders has resulted in proliferation of a wide variety of solder alloy compositions. Few of the popular tin-silver-copper alloys include Sn1Ag0.5Cu and Sn3Ag0.5Cu. The high strain rate properties of leadfree solder alloys are scarce. Typical material tests systems are not well suited for measurement of high strain rates typical of mechanical shock. Previously, high strain rates techniques such as the Split Hopkinson Pressure Bar (SHPB) can be used for strain rates of 1000 per sec. However, measurement of materials at strain rates of 1- 100 per sec which are typical of mechanical shock is difficult to address. In this paper, a new test-technique developed by the authors has been presented for measurement of material constitutive behavior. The instrument enables attaining strain rates in the neighborhood of 1 to 100 per sec. High speed cameras operating at 300,000 fps have been used in conjunction with digital image correlation for the measurement of full-field strain during the test. Constancy of cross-head velocity has been demonstrated during the test from the unloaded state to the specimen failure. Solder alloy constitutive behavior has been measured for SAC105, and SAC305 solders. Constitutive model has been fit to the material data. Samples have been tested at various time under thermal aging at 25°C and 125°C. The constitutive model has been embedded into an explicit finite element framework for the purpose of life-prediction of leadfree interconnects. Test assemblies has been fabricated and tested under JEDEC JESD22-B111 specified condition for mechanical shock. Model predictions have been correlated with experimental data.

Solder joints in electronic assemblies are typically subjected to thermal cycling, either in actual application or in accelerated life testing used for qualification. Mismatches in the thermal expansion coefficients of the assembly materials leads to the solder joints being subjected to cyclic (positive/negative) mechanical strains and stresses. This cyclic loading leads to thermomechanical fatigue damage that involves damage accumulation, crack initiation, crack propagation, and failure. While the effects of aging on solder constitutive behavior (stress-strain and creep) have been examined in some detail, there have been no prior studies on the effects of aging on solder failure and fatigue behavior. In this investigation, we have examined the effects of several parameters (aging, temperature, strain/stress limits, and solder alloy composition) on the cyclic stress-strain behavior of lead free solders. Uniaxial SAC lead free solder specimens were subjected to cyclic (tension/compression) mechanical loading. Samples were cyclically loaded under both strain control (constant positive and negative strain limits) and stress control (constant positive and negative stress limits). The hysteresis loop size (area) was calculated from the measured cyclic stress-strain curves for a given solder alloy and temperature. This area represents the strain energy density dissipated per cycle, which can be typically correlated to the damage accumulation in the joint. Most tests in this investigation were performed with SAC105 solder alloy. However, the effect of solder composition was examined in a limited way by testing four SAC alloys (SAC105, SAC205, SAC305, SAC405) with varying silver content (1-4%) under strain controlled cycling. In addition, the effect of the testing temperature has also been studied by performing cyclic testing of SAC405 samples at four different temperatures (25, 50, 75, and 100 °C). Prior to cyclic loading, the specimens in this study were aged (preconditioned) at 125 °C for various aging times (0-6 months). From the recorded cyclic stress-strain curves, we have been able to characterize and empirically model the evolution of the solder hysteresis loops with aging. Similar to solder stress-strain and creep behaviors, there is a strong effect of aging on the hysteresis loop size (and thus the rate of damage accumulation) in the solder specimens. The observed degradations in the fatigue/cyclic behavior of the lead free solders are highly accelerated for lower silver content alloys (e.g., SAC105), and for aging and testing at higher temperatures. In our current work, we are also subjecting aged solder samples to cyclic loading until failure occurs. Our ultimate goal is to understand the effects of aging on the thermomechanical fatigue life.

In this paper, a prognostication health management (PHM) methodology has been presented for electronic components subjected to mechanical shock and vibration. Electronic assemblies have been monitored using state-space vectors from resistance spectroscopy, phase-sensitive detection and particle filtering (PF) to quantify damage initiation, progression and remaining useful life of the electronic assembly. The presented methodology is an advancement of the state-of-art, which presently focuses on reactive failure detection and provides limited or no insight into the system reliability and residual life. Previously damage initiation, damage progression, and residual life in the pre-failure space has been correlated with micro-structural damage based proxies, feature vectors based on time, spectral and joint timefrequency characteristics of electronics [Lall2004a-d, 2005a-b, 2006a-f, 2007a-e, 2008a-f]. Precise resistance measurements based on the resistance spectroscopy method have been used to monitor interconnects for damage and prognosticate failure [Lall 2009a,b, 2010a,b, Constable 1992, 2001]. In this paper, the effectiveness of the proposed particle filter and resistance spectroscopy based approach in a prognostic health management (PHM) framework has been demonstrated for electronics. The measured state variable has been related to the underlying damage state using non-linear finite element analysis. The particle filter has been used to estimate the state variable, rate of change of the state variable, acceleration of the state variable and construct a feature vector. The estimated state-space parameters have been used to extrapolate the feature vector into the future and predict the time-to-failure at which the feature vector will cross the failure threshold. Remaining useful life has been calculated based on the evolution of the state space feature vector. Standard prognostic health management metrics were used to quantify the performance of the algorithm against the actual remaining useful life. Application to part replacement decisions for ultra-high reliability system has been demonstrated. Using the technique described in the paper the appropriate time to re-order a replacement part could be monitored, and defended statistically. Robustness of the prognostication algorithm has been quantified using standard performance evaluation metrics.

With the transition to lead-free, the electronics industry has widely adopted matte Sn for use component surface finishes. However, it is well know that plated Sn finishes can result in Sn whisker formation. After significant work by numerous researchers, the exact mechanism for Sn whisker growth is still unknown. While industry standard test have been developed, there are no acceleration factors to correlate the laboratory test results to field life. Furthermore, testing (JESD22A121) of components with industry accepted mitigation strategies has still shown whisker growth in excess of allowable standards (JESD201A). The addition of bismuth, to Sn plating reduces whisker growth length. Sn whisker growth, solder wetting, backward compatibility and reliability are discussed.

Structural damage to BGA interconnects incurred during vibration testing has been monitored in the pre-failure space using resistance spectroscopy based state space vectors, rate of change of the state variable, and acceleration of the state variable. The technique is intended for condition monitoring in high reliability applications where the knowledge of impending failure is critical and the risks in terms of loss-of-functionality are too high to bear. Future state of the system has been estimated based on a second order Kalman Filter model and a Bayesian Framework. The measured state variable has been related to the underlying interconnect damage in the form of inelastic strain energy density. Performance of the prognostication health management algorithm during the vibration test has been quantified using performance evaluation metrics. The methodology has been demonstrated on leadfree area-array electronic assemblies subjected to vibration. Model predictions have been correlated with experimental data. The presented approach is applicable to functional systems where corner interconnects in area-array packages may be often redundant. Prognostic metrics including α-λ metric, sample standard deviation, mean square error, mean absolute percentage error, average bias, relative accuracy, and cumulative relative accuracy have been used to assess the performance of the damage proxies. The presented approach enables the estimation of residual life based on level of risk averseness.

Electronic systems under extreme shock and vibration environments including shock and vibration may sustain several failure modes simultaneously. Previous experience of the authors indicates that the dominant failure modes experienced by packages in a drop and shock frame work are in the solder interconnects including cracks at the package and the board interface, pad cratering, copper trace fatigue, and bulk-failure in the solder joint. In this paper, a method has been presented for failure mode classification using a combination of Karhunen Loéve transform with parity-based stepwise supervised training of a perceptrons. Early classification of multiple failure modes in the pre-failure space using supervised neural networks in conjunction with Karhunen Loéve transform is new. Feature space has been formed by joint time frequency analysis. Since the cumulative damage may be accrued under repetitive loading with exposure to multiple shock events, the area array assemblies have been exposed to shock and feature vectors constructed to track damage initiation and progression. Error Back propagation learning algorithm has been used for stepwise parity of each particular failure mode. The classified failure modes and failure regions belonging to each particular failure modes in the feature space are also validated by simulation of the designed neural network used for parity of feature space. Statistical similarity and validation of different classified dominant failure modes is performed by multivariate analysis of variance and Hoteling's T-square. The results of different classified dominant failure modes are also correlated with the experimental cross sections of the failed test assemblies. The methodology adopted in this paper can perform real-time fault monitoring with identification of specific dominant failure mode and is scalable to system level reliability.

Field deployed electronics may accrue damage due to environmental exposure and usage after finite period of service but may not often have any macro-indicators of failure such as cracks or delamination. A method to interrogate the damage state of field deployed electronics in the pre-failure space may allow insight into the damage initiation, progression, and remaining useful life of the deployed system. Aging has been previously shown to effect the reliability and constitutive behavior of second-level leadfree interconnects. Prognostication of accrued damage and assessment of residual life can provide valuable insight into impending failure. In this paper, field deployed parts have been extracted and prognosticated for accrued damage and remaining useful life in an anticipated future deployment environment. A subset of the field deployed parts have been tested to failure in the anticipated field deployed environment to validate the assessment of remaining useful life. In addition, some parts have been subjected to additional know thermo-mechanical stresses and the incremental damage accrued validated with respect to the amount of additional damage imposed on the assemblies. The presented methodology uses leading indicators of failure based on micro-structural evolution of damage to identify accrued damage in electronic systems subjected to sequential stresses of thermal aging and thermal cycling. Damage equivalency methodologies have been developed to map damage accrued in thermal aging to the reduction in thermo-mechanical cyclic life based on damage proxies. The expected error with interrogation of system state and assessment of residual life has been quantified. Prognostic metrics including α-λ metric, sample standard deviation, mean square error, mean absolute percentage error, average bias, relative accuracy, and cumulative relative accuracy have been used to compare the performance of the damage proxies.

The Pb-free Electronics Manhattan Project was motivated by the desire to mitigate the increasing risk associated with the proliferation and use of commercial Pb-free electronics in OEM products. The concept for a Pb-free Electronics Manhattan Project was initialized, formulated, and "socialized" across industry and the customer community in order to obtain sponsorship and general consensus. The project was envisioned as a single, fully-funded team of nationally recognized scientists and engineers working cooperatively over a three-year period, focused on addressing the use of Pb-free electronics in A&D products. The project has been segmented into three phases with the primary funding (estimated to be $105M) expected in Phase 3, which has been renamed to the "Pb-free Electronics Risk Reduction Program" to better convey its intent. Phase 1 established the baseline in terms of documented current practices used across industry and identification of the issues and gaps associated with those practices. Phase 2 articulates the roadmap for the future work required to mitigate those issues and close the gaps in order to reach an acceptable risk level. These two phases form the basis for Phase 3, which will focus on the conduct of specific technical research and development tasks that address the identified technical knowledge gaps. Phases 1 and 2 were planned as distinct two-week separate projects conducted in a single geographical location, such as national lab, using a skilled set of recognized scientists and engineers. The Phase 2 R&D Roadmap, including a detailed Technical Approach, is the subject of this report.

Leading indicators of failure have been developed based on high-frequency characteristics, and system-transfer function derived from resistance spectroscopy measurements during shock and vibration. The technique is intended for condition monitoring in high reliability applications where the knowledge of impending failure is critical and the risks in terms of loss-of-functionality are too high to bear. Previously, resistance spectroscopy measurements [Constable 1992, Lizzul 1994, Prassana 1995] have been used during thermal cycling tests to monitor damage progression due to thermo-mechanical stresses. The development of resistance spectroscopy based damage pre-cursors for prognostication under shock and vibration is new. In this paper, the highfrequency characteristics, and system transfer function based on resistance spectroscopy measurements have been correlated with the damage progression in electronics during shock and vibration. Packages being examined include ceramic area-array packages. Second level interconnect technologies examined include copper-reinforced solder column, SAC305 solder ball, and 90Pb10Sn high-lead solder ball. Assemblies have been subjected to 1500g, 0.5 ms pulse [JESD-B2111]. Continuity has been monitored in-situ during the shock test for identification of part-failure. Resistance spectroscopy based damage pre-cursors have been correlated with the optically measured transient strain based feature vectors. High speed cameras have been used to capture the transient strain histories during shock-impact. Statistical pattern recognition techniques have been used to identify damage initiation and progression and determine the statistical significance in variance between healthy and damaged assemblies. Models for healthy and damaged packages have been developed based on package characteristics. Data presented shows that high-frequency characteristics and system-transfer characteristics based on resistance spectroscopy measurements can be used for condition-monitoring, damage initiation and progression in electronic systems. A positive prognostic distance has been demonstrated for each of the interconnect technologies tested.

low-silver SnAgCu (SAC) lead free alloys is investigated in a harsh thermal environment of -55 to 125 C. Four configuration of test boards were assembled all having identical 100 I/O, 0.8mm pitch chip array ball grid array (CABGA) packages. Previous researchers have demonstrated the superior performance of low-silver leadfree alloys in shock and vibration. The presented study focuses on understanding the low-silver alloys reliability and the effect of dopants for prolonged operation under thermo-mechanical stresses in harsh environments. A direct comparison has been made between the low-silver alloys with and without dopants, keeping the package architecture and board assembly construction identical amongst the board assemblies tested. Solder alloys studied include SAC105, Sn0307, SACX, andSACX+. Accelerated test data has been gathered under thermal cycling from -55 to 125°C with ten minute dwells at each extreme. Weibull distributions have been created for all four-alloys and failure modes studied with cross-sections.

Electronic assemblies deployed in harsh environments may be subjected to multiple thermal environments during the use-life of the equipment. Often the equipment may not have any macro-indicators of damage such as cracks or delamination. Quantification of thermal environments during use-life is often not feasible because of the data-capture and storage requirements, and the overhead on core-system functionality. There is need for tools and techniques to quantify damage in deployed systems in absence of macro-indicators of damage without knowledge of prior stress history. The presented PHM framework is targeted towards high reliability applications such as avionic and space systems. In this paper, Sn3.0Ag0.5Cu alloy packages have been subjected to multiple thermal cycling environments including -55 to 125C and 0 to 100C. Assemblies investigated include area-array packages soldered on FR4 printed circuit cards. The methodology involves the use of condition monitoring devices, for gathering data on damage pre-cursors at periodic intervals. Damage-state interrogation technique has been developed based on the Levenberg-Marquardt Algorithm in conjunction with the microstructural damage evolution proxies. The presented technique is applicable to electronic assemblies which have been deployed on one thermal environment, then withdrawn from service and targeted for redeployment in a different thermal environment. Test cases have been presented to demonstrate the viability of the technique for assessment of prior damage, operational readiness and residual life for assemblies exposed to multiple thermo-mechanical environments. Prognosticated prior damage and the residual life show good correlation with experimental data, demonstrating the validity of the presented technique for multiple thermo-mechanical environments.

On-chip piezoresistive stress sensors represent a unique approach for characterizing stresses in silicon die embedded within complicated packaging architectures. In this work, we have used test chips containing such sensors to measure the stresses induced in microprocessor die after various steps of the assembly process, as well as the stress changes occurring due to thermal cycling. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 x 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. Finally, a metallic lid was attached to complete the ceramic LGA package. After every packaging step (solder reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. A set of low stress test fixtures was developed to eliminate clamping induced stresses being generated during the sensor resistance measurements. The build-up of the die stresses was found to be monotonically increasing, and the relative severity of each assembly step was judged and compared. This combined approach allowed for various material sets (solders, underfills, TIM materials, lid metals, and lid adhesives) to be analyzed and rated for their contribution to the die stress level. After first level packaging of the chips on the ceramic chip carriers, experiments have been performed to analyze the effects of thermal cycling on the die stresses. Thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). After various durations of cycling, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded. From the resistance data, the stresses at each site were calculated and plotted versus time.

Requirements for system availability for ultrahigh reliability electronic systems such as airborne and space electronic systems are driving the need for advanced health monitoring techniques for the early detection of the onset of damage. Aerospace electronic systems usually face a very harsh environment, requiring them to survive the high strain rates, e.g., during launch and reentry, and thermal environments, including extremely low and high temperatures. Traditional health monitoring methodologies have relied on reactive methods of failure detection often providing little or no insight into the remaining useful life of the system. In this paper, a mathematical approach for the interrogation of the system state under cyclic thermomechanical stresses has been developed for six different lead-free solder alloy systems. Data have been collected for leading indicators of failure for alloy systems, including Sn3Ag0.5Cu, Sn0.3Ag0.7Cu, Sn1Ag0.5Cu, Sn0.3Ag0.5Cu0.1Bi, Sn0.2Ag0.5Cu0.1Bi0.1Ni, and 96.5Sn3.5Ag second-level interconnects under the application of cyclic thermomechanical loads. The methodology presented resides in the prefailure space of the system in which no macroindicators such as cracks or delamination exist. Systems subjected to thermomechanical damage have been interrogated for the system state and the computed damage state correlated with the known imposed damage. The approach involves the use of condition monitoring devices which can be interrogated for damage proxies at finite time intervals. The interrogation techniques are based on the derivation of damage proxies and system prior-damage-based nonlinear least square methods, including the Levenberg-Marquardt algorithm. The system's residual life is computed based on residual-life computation algorithms.

In this paper, a new technique has been developed for health monitoring and failure mode classification based on measured damage pre-cursors. A feature extraction technique in the joint-time frequency domain has been developed along with pattern classifiers for fault diagnosis of electronics at productlevel. The Karhunen Loéve transform (KLT) has been used for feature reduction and de-correlation of the feature vectors for fault mode classification in electronic assemblies. Euclidean, and Mahalanobis, and Bayesian distance classifiers based on joint-time frequency analysis, have been used for classification of the resulting feature space. In this paper, various fault modes such as solder inter-connect failure, interconnect missing, chip delamination chip cracking etc in various packaging architectures have been classified using clustering of feature vectors based on the KLT approach. The clustered damage pre-cursors have been correlated with underlying damage. Several chip-scale packages have been studied, with leadfree second-level interconnects including SAC105, SAC305 alloys. Transient strain has been measured during the drop-event using digital image correlation and high-speed cameras operating at 100,000 fps. Continuity has been monitored simultaneously for failure identification. Fault-mode classification has been done using KLT and jointtime- frequency analysis of the experimental data. In addition, explicit finite element models have been developed and various kinds of failure modes have been simulated such as solder ball cracking, trace fracture, package falloff and solder ball failure. Models using cohesive elements present at the solder joint-copper pad interface at both the PCB and package side have also been created to study the traction-separation behavior of solder. Fault modes predicted by simulation based pre-cursors have been correlated with those from experimental data.

The microstructure, mechanical response, and failure behavior of lead free solder joints in electronic assemblies are constantly evolving when exposed to isothermal aging and/or thermal cycling environments. In our prior work on aging effects, we have demonstrated that the observed material behavior variations of Sn-Ag-Cu (SAC) lead free solders during room temperature aging (25 °C) and elevated temperature aging (125 °C) were unexpectedly large and universally detrimental to reliability. Such effects for lead free solder materials are especially important for the harsh applications environments present in high performance computing and in automotive, aerospace, and defense applications. However, there has been little work in the literature, and the work that has been done has concentrated on the degradation of solder ball shear strength (e.g. Dage Shear Tester). Current finite element models for solder joint reliability during thermal cycling accelerated life testing are based on traditional solder constitutive and failure models that do not evolve with material aging. Thus, there will be significant errors in the calculations with the new lead free SAC alloys that illustrate dramatic aging phenomena. In the current work, we have extended our previous studies to include a full test matrix of aging temperatures and solder alloys. The effects of aging on mechanical behavior have been examined by performing stress-strain and creep tests on four different SAC alloys (SAC105, SAC205, SAC305, SAC405) that were aged for various durations (0-6 months) at room temperature (25 °C), and several elevated temperatures (50, 75, 100, and 125 °C). Analogous tests were performed with 63Sn-37Pb eutectic solder samples for comparison purposes. Variations of the mechanical and creep properties (elastic modulus, yield stress, ultimate strength, creep compliance, etc.) were observed and modeled as a function of aging time and aging temperature. The chosen selection of SAC alloys has allowed us to explore the effects of silver content on aging behavior (we have examined SACN05 with N= 1%, 2%, 3%, and 4% silver; with all alloys containing 0.5% copper). In order to reduce the aging induced degradation of the material behavior of the SAC alloys, we are testing several doped SAC alloys in our ongoing work. These materials include SAC0307-X, SAC105-X, and SAC305-X; where the standard SAC alloys have been modified by the addition of small percentages of one or more additional elements (X). Using dopants (e.g. Bi, In, Ni, La, Mg, Mn, Ce, Co, Ti, Zn etc.) has become widespread to enhance shock/drop reliability, and we have extended this approach to examine the ability of dopants to reduce the effects of aging and extend thermal cycling reliability.

Abstract The microstructure, mechanical response, and failure behavior of lead free solder joints in electronic assemblies are constantly evolving when exposed to isothermal aging and/or thermal cycling environments. In our prior work on aging effects, we have demonstrated that large degradations occur in the material properties (stiffness and strength) and creep behavior of Sn-Ag-Cu (SAC) lead free solders during aging. These effects are universally detrimental to reliability and are exacerbated as the aging temperature and aging time increases. Conversely, changes due to aging have been shown to be relatively small in conventional Sn-Pb solders. Aging effects for lead free solder materials are especially important for the harsh applications environments present in high performance computing and in automotive, aerospace, and defense applications. In the current investigation, we have extended our previous studies to include a full test matrix of aging temperatures and SAC lead free solder alloys. In an attempt to reduce the aging induced degradation of the material behavior of SAC solders, we are also exploring various doped SAC-X alloys. These materials are SAC solders that have been modified by the addition of small percentages of one or more additional elements (X). Using dopants (e.g. Bi, In, Ni, La, Mg, Mn, Ce, Co, Ti, Zn, etc.) has become widespread to enhance shock/drop reliability, wetting, and other properties; and we have extended this approach to examine the ability of dopants to reduce the effects of aging and extend thermal cycling reliability. The effects of aging on mechanical behavior have been examined by performing stress-strain and creep tests on solder samples that were aged for various durations (0-6 months) at room temperature (25 °C), and several elevated temperatures (50, 75, 100, and 125 °C). Four "standard" SAC alloys have been examined in this work including SAC105, SAC205, SAC305, and SAC405. This selection has allowed us to explore the effects of silver content on aging behavior (we have examined SACN05 with N= 1%, 2%, 3%, and 4% silver; with all alloys containing 0.5% copper). The doped SAC solder materials being considered in our ongoing studies include SAC0307-X, SAC105-X, and SAC305-X. In this work, we will concentrate on presenting the results for SAC0307-X (SAC-X), where X is 0.1%Bi. This alloy has been proposed as a lower cost SAC variation suitable for enhancing drop reliability. For all of the solders, variations of the mechanical and creep properties (elastic modulus, yield stress, ultimate strength, creep compliance, etc.) were observed and modeled as a function of aging time and aging temperature. Our findings show that the doped SAC-X alloy illustrates reduced degradations with aging for all of the aging temperatures considered. The stress-strain and creep mechanical properties of SAC-X are better than those of SAC105 after short durations of aging, and approach those of SAC205 with longer aging times. After long term aging, the SAC-X alloy was found to have more stable behavior than all of the standard SACN05 alloys. Analogous tests were performed with 63Sn-37Pb eutectic solder samples for comparison purposes.

Portable electronic products subjected to transient shock may exhibit multiple failure modes in vicinity of the interconnects. Failure is often diagnosed by loss of functionality using techniques including the built-in self test, which provides limited insight into reliability and remaining useful life. In this paper prognostic framework for electronic systems has been developed with neural network based self organizing maps. The presented approach resides in the pre-failure space with a focus on electronic systems with multiple failure modes. Unsupervised learning of the neural net has been used to train the neural net for identification of individual failure modes. Feature vectors have been developed based on damage pre-cursors from time-spectral measurements. The clustered damage pre-cursors have been correlated with failure modes of the underlying damage. Several chip-scale packages have been studied, with leadfree second-level interconnects including SAC305, SAC405 alloys. Transient strain has been measured during the drop-event using digital image correlation and high-speed cameras operating at 100,000 fps. Continuity has been monitored simultaneously for failure identification. In addition, explicit finite element models have been developed and various kinds of failure modes have been simulated such as solder ball cracking, trace fracture, package falloff and solder ball failure. Fault modes predicted by simulation based pre-cursors have been correlated with those from experimental data. Activation of different neurons in the lattice for various failure modes and combinations of failure modes has been demonstrated. Previously the authors have developed techniques based on statistical pattern recognition for leading indication of impending failure and detection of damage initiation and progression [Lall 2006a, 2007a, 2008]. Early classification of multiple failure modes in the pre-failure space is new.

Models for crack initiation and propagation in leadfree solders under shock-impact events have been developed using extended finite element method (XFEM). XFEM enables the modeling the solder interconnect without explicitly meshing the crack surface. The crack propagated in crack domain along the solution dependent path with no requirement of remeshing the model. Interface damage properties of the copper-solder interface have been characterized at high strain rate on a bi-material specimen using high-speed imaging in conjunction with digital image correlation. Damage properties have been used as input to the XFEM models. The XFEM submodels have been developed using node-based submodeling, transient displacement and velocity histories from digital image correlation measurements with high-speed imaging of board assemblies during shock. Four interconnect types have been modeled using XFEM including Sn3Ag0.5Cu, 90Pb10Sn, Cu-Reinforced Columns, and63Sn37Pb interconnects on ceramic ball-grid arrays. In addition, Sn3Ag0.5Cu on plastic ball-grid arrays have also been modeled. Extended finite element models have been correlated with cohesive-zone models along with experimental results. The board assemblies have been tested at 1,500g and 12,500g. The failed assemblies have been cross-sectioned and the failure modes correlated with model predictions. The predicted failure modes for all four interconnect types correlate well with the observed locations for failure. Previously, the authors have developed explicit finite element models, cohesive-zone models, and global-local models for prediction of transient dynamics and life prediction of electronics [Lall 2004, 2005, 2006a-c, 2007a-e, 2008a-d]. Previous researchers have applied XFEM in various other fields such as concrete, composite materials [Unger 2007, Hettich 2008]. Damage and life prediction of transient dynamics in electronics interconnects using XFEM in conjunction with digital image correlation and explicit submodeling is new.

Structural damage to BGA interconnects incurred during vibration testing has been monitored in the pre-failure space using resistance spectroscopy based state space vectors, rate of change of the state variable, and acceleration of the state variable. The technique is intended for condition monitoring in high reliability applications where the knowledge of impending failure is critical and the risks in terms of loss-offunctionality are too high to bear. Future state of the system has been estimated based on a second order Kalman Filter model and a Bayesian Framework. The measured state variable has been related to the underlying interconnect damage in the form of inelastic strain energy density. Performance of the prognostication health management algorithm during the vibration test has been quantified using performance evaluation metrics. The methodology has been demonstrated on leadfree area-array electronic assemblies subjected to vibration. Model predictions have been correlated with experimental data. The presented approach is applicable to functional systems where corner interconnects in area-array packages may be often redundant. Prognostic metrics including alpha - Lambda metric, sample standard deviation, mean square error, mean absolute percentage error, average bias, relative accuracy, and cumulative relative accuracy have been used to assess the performance of the damage proxies. The presented approach enables the estimation of residual life based on level of risk averseness.

On-chip piezoresistive stress sensors represent a unique approach for characterizing stresses in silicon die embedded within complicated packaging architectures. In this work, we have used test chips containing such sensors to measure the stresses induced in microprocessor die after various steps of the assembly process, as well as to continuously characterize the in-situ die surface stress during slow temperature changes and thermal cycling experiments. The utilized (111) silicon sensor rosettes were able to measure the complete threedimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 x 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. Finally, a metallic lid was attached to complete the ceramic LGA package. After every packaging step (solder reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. A set of low stress test fixtures was developed to eliminate clamping induced stresses being generated during the sensor resistance measurements. The build-up of the die stresses was found to be monotonically increasing, and the relative severity of each assembly step was judged and compared. In addition, finite element models of the packaging process were developed and correlated with the test chip data. This combined approach allowed for various material sets (solders, underfills, TIM materials, lid metals, and lid adhesives) to be analyzed and rated for their contribution to the die stress level. After first level packaging of the chips on the ceramic chip carriers, experiments have been performed to analyze the effects of slow (quasi-static) temperature changes and thermal cycling on the die stresses. Thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). After various durations of cycling, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded. From the resistance data, the stresses at each site were calculated and plotted versus time.

Electronic systems are often stored for long periods prior to deployment in the intended environment. Aging has been previously shown to effect the reliability and constitutive behavior of second-level leadfree interconnects. Deployed systems may be subjected to cyclic thermo-mechanical loads subsequent to deployment. Prognostication of accrued damage and assessment of residual life is extremely critical for ultra-high reliability systems in which the cost of failure is too high. The presented methodology uses leading indicators of failure based on microstructural evolution of damage to identify impending failure in electronic systems subjected to sequential stresses of thermal aging and thermal cycling. The methodology has been demonstrated on area-array ball-grid array test assemblies with Sn3Ag0.5Cu interconnects subjected to thermal aging at 125°C and thermal cycling from -55 to 125°C for various lengths of time and cycles. Damage equivalency methodologies have been developed to map damage accrued in thermal aging to the reduction in thermomechanical cyclic life based on damage proxies. Assemblies have been prognosticated to assess the error with interrogation of system state and assessment of residual life. Prognostic metrics including alpha - lambda metric, sample standard deviation, mean square error, mean absolute percentage error, average bias, relative accuracy, and cumulative relative accuracy have been used to compare the performance of the damage proxies.

Driven by the trends towards miniaturization and increased functionality, modern electronic systems are being built into more intricate and smaller packages. The mechanical robustness of these smaller and more complex packages is of great concern to the electronics industry. With advances in packaging technology, more reliable interconnects are being designed as a result of which the accountability for failure shifts to copper traces which form the primary failure mode. Previous researchers have addressed copper trace fatigue reliability [Farley 2009] and existence of copper-trace failures in drop-shock [Tee 2009]. This paper addresses the need for life prediction models for PWB copper traces in shock and vibration environments. The study focuses on high cycle fatigue of copper traces which is simulated by subjecting the PWB to vibrations in first mode until failure. Owing to the complexity of the test vehicle, global-local finite element models were developed for simulating the board response. The study addresses the need for empirical rules for trace layout on the PWB which ensure maximum reliability. The effect of trace orientation, trace-pad fillet angle and trace width on its reliability has been investigated. Using Digital Image Correlation based strain responses and Finite Element Model based stress responses, mathematical models for damage accumulation and life prediction of copper traces have been formulated and validated with experimental failure statistics.

Mechanical and thermal shock tested boards populated by TSOP and TQFP parts with surface finishes Sn, SnCu, NiPdAu, and SnPb were examined by SEM/EDX techniques for whisker growth. As a function of finish type, SnPb finishes contained the most whiskers, Sn and SnCu showed intermediate amounts of whiskering, while NiPdAu finishes showed no whiskers. Typical whisker lengths varied from 5-25 microns. As a function of shock method, no whiskers were observed on NiPdAu finishes for either shock condition, while Sn, SnPb, and SnCu finishes favored whiskering under thermal shock conditions. EDX spectra on individual whiskers showed predominantly Sn with expected amounts of C, O, and N from atmospheric exposure and Au due to the necessity of Au coating the specimens before SEM analysis.

Microelectronic encapsulants exhibit evolving properties that change significantly with environmental exposures such as isothermal aging and thermal cycling. Such aging effects are exacerbated at higher temperatures typical of thermal cycling qualification tests for harsh environment electronic packaging. In this work, the material behavior changes occurring in flip chip underfill encapsulants (silica filled epoxies) have been characterized for isothermal aging at four different temperatures that are below, near, and above the Tg of the material. A microscale tension-torsion testing machine has been used to evaluate the creep behavior of the underfill material at several temperatures, after various durations of environmental exposure. A novel method has been developed to fabricate underfill uniaxial test specimens so that they accurately reflect the encapsulant layer present in flip chip assemblies. Using the developed specimen preparation procedure, samples were prepared and isothermally aged for up to 10 months at 80, 100, 125, and 150 °C. Creep tests were then performed on both non-aged and aged samples at three different elevated temperatures where creep is significant (80, 100, and 125 °C). The changes in mechanical behavior were recorded for the various aging temperatures and durations of isothermal exposure. Empirical models have been developed to predict the evolution of the creep strain rate as a function of temperature, aging time, and aging temperature.

Electronic packages subjected to drop and shock have been simulated using alternative theory known as peridynamic theory in the realm of FEM. In peridynamics, problems are formulated in terms of integral equation which is a substitute to conventional solid mechanics theory where problems are formulated in terms of partial differential equations. This alternative approach is more potent than conventional finiteelement method because the integral equations remain valid even at discontinuities which enables to model crack initiation and crack propagation which can occur at multiple locations simultaneously. Previously, Agwai [2008] has demonstrated the use of peridynamic models using EMU code. In this paper, a peridynamic-theory based drop and shock model has been developed via finite element code using truss elements [Macek 2007]. The method enables the implementation of peridynamic theory in a commercial finite-element platform. Model predictions of peridynamic-models have been validated with experimentation for leadfree solder alloys system.

Electronic assemblies deployed in harsh environments may be subjected to multiple thermal environments during the use-life of the equipment. Often the equipment may not have any macro-indicators of damage such as cracks or delamination. Quantification of thermal environments during use-life is often not feasible because of the data-capture and storage requirements, and the overhead on core-system functionality. There is need for tools and techniques to quantify damage in deployed systems in absence of macro-indicators of damage without knowledge of prior stress history. The presented PHM framework is targeted towards high reliability applications such as avionic and space systems. In this paper, Sn3.0Ag0.5Cu alloy packages have been subjected to multiple thermal cycling environments including -55 to 125C and 0 to 100C. Assemblies investigated include area-array packages soldered on FR4 printed circuit cards. The methodology involves the use of condition monitoring devices, for gathering data on damage pre-cursors at periodic intervals. Damage-state interrogation technique has been developed based on the Levenberg-Marquardt Algorithm in conjunction with the microstructural damage evolution proxies. The presented technique is applicable to electronic assemblies which have been deployed on one thermal environment, then withdrawn from service and targeted for redeployment in a different thermal environment. Test cases have been presented to demonstrate the viability of the technique for assessment of prior damage, operational readiness and residual life for assemblies exposed to multiple thermomechanical environments. Prognosticated prior damage and the residual life show good correlation with experimental data, demonstrating the validity of the presented technique for multiple thermo-mechanical environments.

In this paper, a mathematical approach for interrogation of system-state under cyclic thermo-mechanical stresses has been developed for three-different lead-free solder alloy systems. Data have been collected for leading indicators-of-failure for alloy systems including, Sn1Ag0.5Cu, Sn3Ag0.5Cu, Sn4Ag0.5Cu second- level interconnects under the application of cyclic thermo-mechanical loads. Methodology presented resides in the pre-failure space of the system in which no macro-indicators such as cracks or delamination exist. Systems subjected to thermo-mechanical damage have been interrogated for system state and the computed damage state correlated with known imposed damage. The approach involves the use of condition monitoring devices which can be interrogated for damage proxies at finite time-intervals. Interrogation techniques are based on non-linear least-squares methods. Various techniques including the Levenberg-Marquardt Algorithm have been investigated. The system's residual life is computed based on residual-life computation algorithms. Detection of system-state significantly prior to catastrophic failure can significantly impact the reliability and availability of electronic systems. Requirements for system availability for ultra-high reliability electronic systems are driving the need for advanced heath monitoring techniques for early detection of onset of damage. Traditional health monitoring methodologies have relied on reactive methods of failure detection often providing little on no insight into the remaining useful life of the system.

In this paper, a leading indicators based approach has been developed for prognostics and health monitoring of electronic systems. The approach focuses on the prefailure space and methodologies for quantification of damage progression and residual life in electronic equipment subjected to shock and vibration loads using the dynamic response of the electronic equipment. Traditional health monitoring methodologies have relied on reactive methods of failure detection often providing little or no insight into the remaining useful life of the system. The proposed techniques have a wideapplicability to electronic systems requiring high reliability. Operational readiness and high-system availability are critical for reduction of uncertainty in mission-critical electronic systems. Examples include aerospace-electronic systems which usually face a very harsh environment, requiring them to survive the high strain rates, e.g. during launch and re-entry and thermal environments including extreme low and high temperatures and implantable biological systems such as pacemakers and defibrillators. Prognostic indicators can trigger preventive maintenance based on need instead of "fear-of-failure". Auto-regressive (AR), wavelet packet energy decomposition, and time-frequency (TFA) techniques have been investigated for system identification, condition monitoring, and fault detection and diagnosis in electronic systems. The test vehicle subjected to repeated proof-load events consists of a wide frequency range. In this approach the known auto correlation sequence of the feature vectors, is extrapolated to estimate auto correlation sequence at unknown lags. One of the main advantages of the AR technique is that it is primarily a signal based technique. Reduced reliance on system analysis helps avoid errors which otherwise may render the process of fault detection and diagnosis quite complex and dependent on the skills of the analyst. Results of the present study show that the AR and TFA based health monitoring techniques are feasible for fault detection and damage-assessment in electronic units. Explicit finite element models have been developed and various kinds of failure modes have been simulated such as solder ball cracking, package falloff and solder ball failure.

Thermal cycling accelerated life testing is often used to qualify area array packages (e.g. Ball Grid Arrays and Flip Chip) for various applications. Finite element life predictions for thermal cycling configurations are challenging due to the complicated temperature/time dependent constitutive relations and failure criteria needed for solders and encapsulants and their interfaces, aging/evolving material behavior (e.g. solders), difficulties in modeling plating finishes, the complicated geometries of typical electronic assemblies, etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling is difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, we really know quite little about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling. In our research, we are using test chips containing piezoresistive stress sensors to continuously characterize the in-situ die surface stress during long-term thermal cycling of several different area array packaging technologies including plastic ball grid array (PBGA) components, ceramic ball grid array (CBGA) components, and flip chip on laminate assemblies. The utilized (111) silicon test chips are able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The die stresses are initially measured at room temperature after packaging. The assemblies are then subjected to thermal cycling over various temperature ranges including 0 to 100 °C, -40 to 125 °C, and -55 to 125 °C, for up to 3000 thermal cycles. During the thermal cycling, sensor resistances at critical locations on the die device surface (e.g. the die center and die corners) are recorded. From the resistance data, the stresses at each site can be calculated and plotted versus time. The experimental observations show significant cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage. The observed stress variations as a function of thermal cycling duration are also being correlated with the observed delaminations at the die surface (as measured using scanning acoustic microscopy (C-SAM)) and finite element simulations that include material constitutive models that incorporate thermal aging effects.

Microelectronic encapsulants exhibit evolving properties that change significantly with environmental exposures such as isothermal aging and thermal cycling. Such aging effects are exacerbated at higher temperatures typical of thermal cycling qualification tests for harsh environment electronic packaging. In this work, the material behavior changes occurring in flip chip underfill encapsulants (silica filled epoxies) have been characterized for isothermal aging at four different temperatures that are below, near, and above the Tg of the material. A microscale tension-torsion testing machine has been used to evaluate the uniaxial tensile stress-strain and creep behaviors of the underfill material at several temperatures, after various durations of environmental exposure. A novel method has been developed to fabricate underfill uniaxial test specimens so that they accurately reflect the encapsulant layer present in flip chip assemblies. Using the developed specimen preparation procedure, samples were prepared and isothermal aged for up to 10 months at 80, 100, 125, and 150 °C. Stress-strain and creep tests were then performed on both non-aged and aged samples at several different temperatures (25, 50, 75, 100, 125, and 150 °C). The changes in mechanical behavior were recorded for the various aging temperatures and durations of isothermal exposure. Empirical models have been developed to predict the evolution of the material properties (modulus, strength) and the creep strain rate as a function of temperature, aging time, and aging temperature.

The microstructure, mechanical response, and failure behavior of lead free solder joints in electronic assemblies are constantly evolving when exposed to isothermal aging and/or thermal cycling environments. In our prior work on aging effects, we have demonstrated that the observed material behavior variations of Sn-Ag-Cu (SAC) lead free solders during room temperature aging (25 °C) and elevated temperature aging (125 °C) were unexpectedly large and universally detrimental to reliability. Such effects for lead free solder materials are especially important for the harsh applications environments present in high performance computing and in automotive, aerospace, and defense applications. However, there has been little work in the literature, and the work that has been done has concentrated on the degradation of solder ball shear strength (e.g. Dage Shear Tester). Current finite element models for solder joint reliability during thermal cycling accelerated life testing are based on traditional solder constitutive and failure models that do not evolve with material aging. Thus, there will be significant errors in the calculations with the new lead free SAC alloys that illustrate dramatic aging phenomena. In the current work, we have extended our previous studies to include a full test matrix of aging temperatures and solder alloys. The effects of aging on mechanical behavior have been examined by performing stress-strain and creep tests on four different SAC alloys (SAC105, SAC205, SAC305, SAC405) that were aged for various durations (0-6 months) at room temperature (25 °C), and several elevated temperatures (50, 75, 100, and 125 °C). Analogous tests were performed with 63Sn-37Pb eutectic solder samples for comparison purposes. Variations of the mechanical and creep properties (elastic modulus, yield stress, ultimate strength, creep compliance, etc.) were observed and modeled as a function of aging time and aging temperature. The chosen selection of SAC alloys has allowed us to explore the effects of silver content on aging behavior (we have examined SACN05 with N= 1%, 2%, 3%, and 4% silver; with all alloys containing 0.5% copper). In order to reduce the aging induced degradation of the material behavior of the SAC alloys, we are testing several doped SAC alloys in our ongoing work. These materials include SAC0307-X, SAC105-X, and SAC305-X; where the standard SAC alloys have been modified by the addition of small percentages of one or more additional elements (X). Using dopants (e.g. Bi, In, Ni, La, Mg, Mn, Ce, Co, Ti, etc.) has become widespread to enhance shock/drop reliability, and we have extended this approach to examine the ability of dopants to reduce the effects of aging and extend thermal cycling reliability.

The transition from tin-lead to lead free soldering in the electronics manufacturing industry has been in progress for the past 10 years. In the interim period before lead free assemblies are uniformly accepted, mixed formulation solder joints are becoming commonplace in electronic assemblies. For example, area array components (BGA/CSP) are frequently available only with lead free Sn-Ag-Cu (SAC) solder balls. Such parts are often assembled to printed circuit boards using traditional 63Sn-37Pb solder paste. The resulting solder joints contain unusual quaternary alloys of Sn, Ag, Cu, and Pb. In addition, the alloy composition can vary across the solder joint based on the paste to ball solder volumes and the reflow profile utilized. The mechanical and physical properties of such Sn-Ag-Cu-Pb alloys have not been explored extensively in the literature. In addition, the reliability of mixed formulation solder joints is poorly understood. In this work, we have explored the physical properties and mechanical behavior of mixed formulation solder materials. Seven different mixture ratios of 63Sn-37Pb and SAC305 solder materials have been formed, which include five carefully controlled mixtures of the two solder alloys (by weight percentage) and the two extreme cases (pure Sn-Pb and pure SAC). For the various percentage mixtures, the melting point, pasty range, stress-strain curves, mechanical properties (modulus, strength), and creep curves have been characterized. The variations of the mechanical properties and creep rates with aging at room temperature (25 °C) and elevated temperature (100 °C) have also been measured. Finally, the microstructures realized with the various mixtures have been found and correlated to the mechanical measurements and microstructures found in actual mixed formulation BGA solder joints. The results for the mechanical and physical properties show a very complicated dependence on the mixture ratio.

Goldmann Constants and Norris-Landzberg acceleration factors for lead-free solders have been developed based on principal component regression models (PCR) for reliability prediction and part selection of area-array packaging architectures under thermo-mechanical loads. Models have been developed in conjunction with Stepwise Regression Methods for identification of the main effects. Package architectures studied include, BGA packages mounted on copper-core and no-core printed circuit assemblies in harsh environments. The models have been developed based on thermo-mechanical reliability data acquired on copper-core and no-core assemblies in four different thermal cycling conditions. Packages with Sn3Ag0.5Cu solder alloy interconnects have been examined. The models have been developed based on perturbation of accelerated test thermomechanical failure data. Data has been gathered on nine different thermal cycle conditions with SAC305 alloys. The thermal cycle conditions differ in temperature range, dwell times, maximum temperature and minimum temperature to enable development of constants needed for the life prediction and assessment of acceleration factors. Goldmann Constants and the Norris-Landzberg acceleration factors have been benchmarked against previously published values. In addition, model predictions have been validated against validation data-sets which have not been used for model development. Convergence of statistical models with experimental data has been demonstrated using a single factor design of experiment study for individual factors including temperature cycle magnitude, relative coefficient of thermal expansion, and diagonal length of the chip. The predicted and measured acceleration factors have also been computed and correlated. Good correlations have been achieved for parameters examined. Previously, the feasibility of using multiple linear regression models for reliability prediction has been demonstrated for flex-substrate BGA packages [Lall 2004, 2005], flip-chip packages [Lall 2005] and ceramic BGA packages [Lall 2007]. The presented methodology is valuable in the development of fatigue damage constants for the application specific accelerated test data-sets and provides a method to develop institutional learning based on prior accelerated test data.

Failures in electronics subjected to shock and vibration are typically diagnosed using the built-in self test (BIST) or using continuity monitoring of daisy-chained packages. The BIST which is extensively used for diagnostics or identification of failure, is focused on reactive failure detection and provides limited insight into reliability and residual life. In this paper, a new technique has been developed for health monitoring and failure mode classification based on measured damage pre-cursors. A feature extraction technique in the joint-time frequency domain has been developed along with pattern classifiers for fault diagnosis of electronics at product-level. The Karhunen Loéve transform (KLT) has been used for feature reduction and de-correlation of the feature vectors for fault mode classification in electronic assemblies. Euclidean, and Mahalanobis, and Bayesian distance classifiers based on joint-time frequency analysis, have been used for classification of the resulting feature space. Previously, the authors have developed damage precursors based on time and spectral techniques for health monitoring of electronics without reliance on continuity data from daisy-chained packages. Statistical Pattern Recognition techniques based on wavelet packet energy decomposition [Lall 2006a] have been studied by authors for quantification of shock damage in electronic assemblies, and auto-regressive moving average, and time-frequency techniques have been investigated for system identification, condition monitoring, and fault detection and diagnosis in electronic systems [Lall 2008]. However, identification of specific failure modes was not possible. In this paper, various fault modes such as solder inter-connect failure, inter-connect missing, chip delamination chip cracking etc in various packaging architectures have been classified using clustering of feature vectors based on the KLT approach [Goumas 2002]. The KLT de-correlates the feature space and identifies dominant directions to describe the space, eliminating directions that encode little useful information about the features [Qian 1996, Schalkoff 1972, Theodoridis 1998, Tou 1974]. The clustered damage precursors have been correlated with underlying damage. Several chip-scale packages have been studied, with leadfree second-level interconnects including SAC105, SAC305 alloys. Transient strain has been measured during the dropevent using digital image correlation and high-speed cameras operating at 100,000 fps. Continuity has been monitored simultaneously for failure identification. Fault-mode classification has been done using KLT and joint-timefrequency analysis of the experimental data. In addition, explicit finite element models have been developed and various kinds of failure modes have been simulated such as solder ball cracking, trace fracture, package falloff and solder ball failure. Models using cohesive elements present at the solder joint-copper pad interface at both the PCB and package side have also been created to study the traction-separation behavior of solder. Fault modes predicted by simulation based pre-cursors have been correlated with those from experimental data.

Relative damage-index based on the leadfree interconnect transient strain history from digital image correlation, explicit finite-elements, cohesive-zone elements, and component's survivability envelope has been developed for life-prediction of two-leadfree electronic alloy systems. Life prediction of pristine and thermally-aged assemblies, have been investigated. Solder alloy system studied include Sn1Ag0.5Cu, and 96.5Sn3.5Ag. Transient strains during the shock-impact have been measured using digital image correlation in conjunction with high-speed cameras operating at 50,000 fps. Both the board strains and the package strains have been measured in a variety of drop orientations including JEDEC horizontal drop orientation, vertical drop orientation and intermediate drop orientations. In addition the effect of sequential stresses of thermal aging and shockimpact on the failure mechanisms has also been studied. The thermal aging condition used for the study includes 125°C for 100hrs. The presented methodology addresses the need for life prediction of new lead-free alloy-systems under shock and vibration, which is largely beyond the state of art. Three failure modes have been predicted including interfacial failure at the copper-solder interface, solder-PCB interface, and the solder joint failure. Explicit non-linear finite element models with cohesive-zone elements have been developed and correlated with experimental results. Velocity data from digital image correlation has been used to drive the attachment degrees of freedom of the submodel and extract transient interconnect strain histories. Explicit finite-element sub-modeling has been correlated with the full-field strain in various locations, orientations, on both the package and the board-side. The survivability of the leadfree interconnections under sequential loading (thermal aging and shock-impact) from simulation has been compared with pristine circuit assemblies subjected to shock-impact. Sequential loading changes the failure modes and decreases the drop reliability as compared to the room temperature experimental results. Damage index based survivability envelope is intended for component integration to ensure reliability in harsh environments.

Leading indicators of failure have been developed based on high-frequency characteristics, and system-transfer function derived from resistance spectroscopy measurements during shock and vibration. The technique is intended for condition monitoring in high reliability applications where the knowledge of impending failure is critical and the risks in terms of loss-of-functionality are too high to bear. Previously, resistance spectroscopy measurements [Constable 1992, Lizzul 1994, Prassana 1995] have been used during thermal cycling tests to monitor damage progression due to thermo-mechanical stresses. The development of resistance spectroscopy based damage pre-cursors for prognostication under shock and vibration is new. In this paper, the highfrequency characteristics, and system transfer function based on resistance spectroscopy measurements have been correlated with the damage progression in electronics during shock and vibration. Packages being examined include ceramic area-array packages. Second level interconnect technologies examined include copper-reinforced solder column, SAC305 solder ball, and 90Pb10Sn high-lead solder ball. Assemblies have been subjected to 1500g, 0.5 ms pulse [JESD-B2111]. Continuity has been monitored in-situ during the shock test for identification of part-failure. Resistance spectroscopy based damage pre-cursors have been correlated with the optically measured transient strain based feature vectors. High speed cameras have been used to capture the transient strain histories during shock-impact. Statistical pattern recognition techniques have been used to identify damage initiation and progression and determine the statistical significance in variance between healthy and damaged assemblies. Models for healthy and damaged packages have been developed based on package characteristics. Data presented shows that high-frequency characteristics and system-transfer characteristics based on resistance spectroscopy measurements can be used for condition-monitoring, damage initiation and progression in electronic systems. A positive prognostic distance has been demonstrated for each of the interconnect technologies tested.

In this paper, a methodology to predict failure of electronics under shock and vibration loads has been investigated. Reliability prediction models have been developed using optical feature extraction techniques for 6-leadfree solder alloy systems. Solder alloy systems investigated include, Sn1Ag0.5Cu, Sn3Ag0.5Cu, Sn0.3Ag0.7Cu, Sn0.3Ag0.7Cu0.1Bi, Sn0.2Ag0.7Cu0.1Bi-0.1Ni, 96.5Sn3.5Ag. Previously, Digital Image Correlation (DIC) has been used for measurement of thermally-induced deformation and material characterisation. In this paper, DIC has been used for transient dynamic measurements, and optical feature extraction. Board assemblies have been subjected to shock-impact in various orientations including the zero-degree JEDEC drop and the vertical free-drop. Transient deformation has been measured using both DIC and the strain gages. Measurements have been taken on both the package and the board side of the assemblies. Accuracy of high-speed optical measurement has been compared with that from discrete strain gages. Package architectures examined include-flex ball-grid arrays, tape-array ball-grid arrays, and metal lead-frame packages. Explicit finite-element models have been developed and correlated with experimental data. Three models were developed: smeared property models: Timoshenko-beam models: and explicit sub-models. The potential of damage identification and tracking for various solder alloys has been investigated. Data on the identification of damage proxies for competing failure mechanisms at the copper-to-solder, solder-to-printed circuit board, and copper-to-package substrate has been presented. Design envelopes have been developed based on Statistical Pattern Recognition (SPR). The design-envelope is intended for component integration to ensure survivability in shock and vibration environments at a user-specified confidence level.

Electronic assemblies deployed in harsh environments may be subjected to multiple thermal environments during the use-life of the equipment. Often the equipment may not have any macro-indicators of damage such as cracks or delamination. Quantification of thermal environments during use-life is often not feasible because of the data-capture and storage requirements, and the overhead on core-system functionality. There is need for tools and techniques to quantify damage in deployed systems in absence of macro-indicators of damage without knowledge of prior stress history. The presented PHM framework is targeted towards high reliability applications such as avionic and space systems. In this paper, Sn3.0Ag0.5Cu alloy packages have been subjected to multiple thermal cycling environments including -55 to 125C and 0 to 100C. Assemblies investigated include area-array packages soldered on FR4 printed circuit cards. The methodology involves the use of condition monitoring devices, for gathering data on damage pre-cursors at periodic intervals. Damage-state interrogation technique has been developed based on the Levenberg-Marquardt Algorithm in conjunction with the microstructural damage evolution proxies. The presented technique is applicable to electronic assemblies which have been deployed on one thermal environment, then withdrawn from service and targeted for redeployment in a different thermal environment. Test cases have been presented to demonstrate the viability of the technique for assessment of prior damage, operational readiness and residual life for assemblies exposed to multiple thermo-mechanical environments. Prognosticated prior damage and the residual life show good correlation with experimental data, demonstrating the validity of the presented technique for multiple thermo-mechanical environments.

Failures in electronics subjected to shock and vibration are typically diagnosed using the built-in self test (BIST) or using continuity monitoring of daisy-chained packages. The BIST which is extensively used for diagnostics or identification of failure, is focused on reactive failure detection and provides limited insight into reliability and residual life. In this paper, a new technique has been developed for health monitoring and failure mode classification based on measured damage precursors. A feature extraction technique in the joint-time frequency domain has been developed along with pattern classifiers for fault diagnosis of electronics at product-level. The Karhunen Loéve transform (KLT) has been used for feature reduction and de-correlation of the feature vectors for fault mode classification in electronic assemblies. Euclidean, and Mahalanobis, and Bayesian distance classifiers based on joint-time frequency analysis, have been used for classification of the resulting feature space. Previously, the authors have developed damage pre-cursors based on time and spectral techniques for health monitoring of electronics without reliance on continuity data from daisy chained packages. Statistical Pattern Recognition techniques based on wavelet packet energy decomposition [Lall 2006a] have been studied by authors for quantification of shock damage in electronic assemblies, and auto-regressive moving average, and time-frequency techniques have been investigated for system identification, condition monitoring, and fault detection and diagnosis in electronic systems [Lall 2008]. However, identification of specific failure modes was not possible. In this paper, various fault modes such as solder inter-connect failure, inter-connect missing, chip delamination chip cracking etc in various packaging architectures have been classified using clustering of feature vectors based on the KLT approach [Goumas 2002]. The KLT de-correlates the feature space and identifies dominant directions to describe the space, eliminating directions that encode little useful information about the features [Qian 1996, Schalkoff 1972, Theodoridis 1998, Tou 1974]. The clustered damage pre-cursors have been correlated with underlying damage. Several chip-scale packages have been studied, with leadfree second-level interconnects including SAC105, SAC305 alloys. Transient strain has been measured during the drop-event using digital image correlation and high-speed cameras operating at 100,000 fps. Continuity has been monitored simultaneously for failure identification. Fault-mode classification has been done using KLT and joint-time-frequency analysis of the experimental data. In addition, explicit finite element models have been developed and various kinds of failure modes have been simulated such as solder ball cracking, trace fracture, package falloff and solder ball failure. Models using cohesive elements present at the solder joint-copper pad interface at both the PCB and package side have also been created to study the tractionseparation behavior of solder. Fault modes predicted by simulation based pre-cursors have been correlated with those from experimental data.

A comprehensive multi-physics theoretical model of a solenoid valve used in an automobile transmission is constructed using the finite element method. The multi-physics model includes the coupled effects of electromagnetic, thermodynamics and solid mechanics. The resulting finite element model of the solenoid valve provides useful information on the temperature distribution, mechanical and thermal deformations, and stresses. The model results predict that the solenoid valve is susceptible to a coupled electrical-thermomechanical failure mechanism. The coil can generate heat which can cause compressive stress and high temperatures that in turn could fail the insulation between the coil wires. The model facilitates the characterization of the solenoid valve performance, life and reliability and can be used as a predictive tool in future solenoid design.

This work studies the reliability of a solenoid valve (SV) used in automobile transmissions through a joint theoretical and experimental approach. The goal of this work is to use accelerated tests to characterize SV failure and correlate the results to new comprehensive finite element models (Part 1). A custom test apparatus has been designed and built to simultaneously monitor and actuate up to four SVs. The test apparatus is capable of applying a controlled duty cycle, current and actuation frequency. The SVs are also placed in a thermal chamber so that the ambient temperature can be controlled precisely. The apparatus measures in real-time the temperature, current, and voltage of each SV. A series of tests have been conducted to produce repeated failures of the SV. The failure of the SV appears to be caused by overheating and failure of the insulation used in the solenoid coil. The current tests are run at a 100 °C ambient temperature, 16.8 V of average peak voltage, 50% duty cycle, and 60 Hz actuation frequency. Upon failure, the solenoid electrical resistance drops to a significantly lower value due to shorting of the solenoid coil. This drop in resistance causes a measurable and noticeable increase in the average current. The insulation also melts and exits the SV. Hence, increasing ambient temperature and current is believed to cause a decrease in SV reliability.

Relative damage-index based on the leadfree interconnect transient strain history from digital image correlation, explicit finite-elements, cohesive-zone elements, and component's survivability envelope has been developed for life-prediction of two-leadfree electronic alloy systems. Life prediction of pristine and thermally-aged assemblies, have been investigated. Solder alloy system studied include Sn1Ag0.5Cu, and 96.5Sn3.5Ag. Transient strains during the shock-impact have been measured using digital image correlation in conjunction with high-speed cameras operating at 50,000 fps. Both the board strains and the package strains have been measured in a variety of drop orientations including JEDEC horizontal drop orientation, vertical drop orientation and intermediate drop orientations. In addition the effect of sequential stresses of thermal aging and shock-impact on the failure mechanisms has also been studied. The thermal aging condition used for the study includes 125°C for 100hrs. The presented methodology addresses the need for life prediction of new lead-free alloy-systems under shock and vibration, which is largely beyond the state of art. Three failure modes have been predicted including interfacial failure at the copper-solder interface, solder-PCB interface, and the solder joint failure. Explicit nonlinear finite element models with cohesive-zone elements have been developed and correlated with experimental results. Velocity data from digital image correlation has been used to drive the attachment degrees of freedom of the submodel and extract transient interconnect strain histories. Explicit finite-element sub-modeling has been correlated with the full-field strain in various locations, orientations, on both the package and the board-side. The survivability of the leadfree interconnections under sequential loading (thermal aging and shock-impact) from simulation has been compared with pristine circuit assemblies subjected to shock-impact. Sequential loading changes the failure modes and decreases the drop reliability as compared to the room temperature experimental results. Damage index based survivability envelope is intended for component integration to ensure reliability in harsh environments.

Failures in electronics subjected to shock and vibration are typically diagnosed using the built-in self test (BIST) or using continuity monitoring of daisy-chained packages. The BIST which is extensively used for diagnostics or identification of failure, is focused on reactive failure detection and provides limited insight into reliability and residual life. In this paper, a new technique has been developed for health monitoring and failure mode classification based on measured damage pre-cursors. A feature extraction technique in the joint-time frequency domain has been developed along with pattern classifiers for fault diagnosis of electronics at product-level. The Karhunen Loéve transform (KLT) has been used for feature reduction and de-correlation of the feature vectors for fault mode classification in electronic assemblies. Euclidean, and Mahalanobis, and Bayesian distance classifiers based on joint-time frequency analysis, have been used for classification of the resulting feature space. Previously, the authors have developed damage pre-cursors based on time and spectral techniques for health monitoring of electronics without reliance on continuity data from daisy-chained packages. Statistical Pattern Recognition techniques based on wavelet packet energy decomposition [Lall 2006a] have been studied by authors for quantification of shock damage in electronic assemblies, and auto-regressive moving average, and timefrequency techniques have been investigated for system identification, condition monitoring, and fault detection and diagnosis in electronic systems [Lall 2008]. However, identification of specific failure modes was not possible. In this paper, various fault modes such as solder inter-connect failure, inter-connect missing, chip delamination chip cracking etc in various packaging architectures have been classified using clustering of feature vectors based on the KLT approach [Goumas 2002]. The KLT de-correlates the feature space and identifies dominant directions to describe the space, eliminating directions that encode little useful information about the features [Qian 1996, Schalkoff 1972, Theodoridis 1998, Tou 1974]. The clustered damage pre-cursors have been correlated with underlying damage. Several chip-scale packages have been studied, with leadfree second-level interconnects including SAC105, SAC305 alloys. Transient strain has been measured during the drop-event using digital image correlation and high-speed cameras operating at 100,000 fps. Continuity has been monitored simultaneously for failure identification. Fault-mode classification has been done using KLT and joint-timefrequency analysis of the experimental data. In addition, explicit finite element models have been developed and various kinds of failure modes have been simulated such as solder ball cracking, trace fracture, package falloff and solder ball failure. Models using cohesive elements present at the solder joint-copper pad interface at both the PCB and package side have also been created to study the traction-separation behavior of solder. Fault modes predicted by simulation based pre-cursors have been correlated with those from experimental data.

The microstructure, mechanical response, and failure behavior of lead free solder joints in electronic assemblies are constantly evolving when exposed to isothermal aging and/or thermal cycling environments. In our prior work on aging effects, we have demonstrated that the observed material behavior variations of Sn-Ag-Cu (SAC) lead free solders during room temperature aging (25 °C) and elevated temperature aging (125 °C) were unexpectedly large and universally detrimental to reliability. Such effects for lead free solder materials are especially important for the harsh applications environments present in high performance computing and in automotive, aerospace, and defense applications. However, there has been little work in the literature, and the work that has been done has concentrated on the degradation of solder ball shear strength (e.g. Dage Shear Tester). Current finite element models for solder joint reliability during thermal cycling accelerated life testing are based on traditional solder constitutive and failure models that do not evolve with material aging. Thus, there will be significant errors in the calculations with the new lead free SAC alloys that illustrate dramatic aging phenomena. In the current work, we have extended our previous studies to include a full test matrix of aging temperatures and solder alloys. The effects of aging on mechanical behavior have been examined by performing stress-strain and creep tests on four different SAC alloys (SAC105, SAC205, SAC305, SAC405) that were aged for various durations (0-6 months) at room temperature (25 °C), and several elevated temperatures (50, 75, 100, and 125 °C). Analogous tests were performed with 63Sn-37Pb eutectic solder samples for comparison purposes. The chosen selection of SAC alloys has allowed us to explore the effects of silver content on aging behavior (we have examined SACN05 with N = 1%, 2%, 3%, and 4% silver; with all alloys containing 0.5% copper). Variations of the mechanical and creep properties (elastic modulus, yield stress, ultimate strength, creep compliance, etc.) have been observed and modeled as a function of aging time and aging temperature. In this paper, we report on the results of the creep experiments.

Leading indicators of failure have been developed based on high-frequency characteristics, and system-trasfer function derived from resistance spectroscopy measurements during shock and vibration. The technique is intended for condition monitoring in high reliability applications where the knowledge of impending failure is critical and the risks in terms of loss-of-functionality are too high to bear. The high-frequency characateristics, and system transfer function based on resistance spectroscopy measurements have been correlated with the damage progression in electroncis during shock and vibration. Packages examined include ceramic area-array packages. Second-level interconnect technologies examined include copper-reinforced solder column, SAC305 solder ball, and 90Pb10Sn high-lead solder ball. Assemblies have been subjected to 1500g, 0.5 ms pulse. A positive prognostic distance has been demonstrated for each of the interconnect technologies tested.

In this work, the effects of underfill cure temperature and JEDEC MSL preconditioning on underfill mechanical and strength properties, as well as flip chip assembly reliability have been explored. Baseline stress-strain curves, mechanical properties, and interfacial shear strengths of a capillary underfill were recorded for curing at 150 °C and 165 °C (30 minutes). In addition, the changes in the mechanical and strength properties resulting from MSL3 and MSL2 moisture preconditioning were evaluated. The MSL preconditioning of the underfill samples included the JEDEC specified humidity and temperature exposures, plus three simulated reflows at 245 °C or 260 °C. Thermal cycling life tests from -55 to 125 °C were also conducted on daisy chain flip chip assemblies incorporating the same underfill. The test matrix for the reliability testing included both 150 °C and 165 °C curing profiles, and two levels of precondition (none and MSL3). Finally, the failure mechanisms in the flip chip assemblies were studied using CSAM, x-ray and SEM analyses. The results clearly indicate the advantages of the higher curing temperature including improved mechanical properties, superior thermal cycling fatigue life, and enhanced resistance to detrimental effects from moisture exposure and solder reflow.

As automotive electronics grow, reduction of size in electronic packages becomes a trend due to particular space requirements and material costs. The locations of automotive electronics are currently being shifted to under-the-hood, like the controllers can be embedded in the modules of engine or the transmission. Hence the thermal issues become more severe to the electrical packages. Another issue is the transition from Tin-lead to Lead-free. The Restriction of the Use of Hazardous Substances (RoHs) has been carried out on electronics in Europe and Asia. The transition is not a progress, but a challenge as many reliability issues involved. In the past years, researches have proved that the reliability of PBGA can be changed through altering the design parameters. However, most reliability researches were implemented on tin lead material, for instance, tin lead solder BGA balls and tin lead solder paste. Along with the increasing percentage of lead-free material, we still have some critical reliability issues of BGAs to be waiting for being resolved. In this study, we focus on the lead-free solder applied in BGAs by different combinations, like SAC BGA solder balls using Tin-lead solder paste, Tin-lead solder balls using Tin-lead solder paste. The accelerated life testing (liquid and air) is put to test whether PBGA electronic packages can withstand the automotive under-the-hood operating conditions. We adopt accelerated life testing (ALT) to overstress the electronic package and reduce the mean life to failure. For both of SAC and SnPb being used in this research, the physical properties of mixed formulation solder alloy would be analyzed. Through the analysis of mixture ratio between SnPb and SAC, we can get the comparisons in different solder-ball / solder-paste combinations.

Electronic assemblies deployed in harsh environments may be subjected to multiple thermal environments during the use-life of the equipment. Often the equipment may not have any macro-indicators of damage such as cracks or delamination. Quantification of thermal environments during use-life is often not feasible because of the data-capture and storage requirements, and the overhead on core-system functionality. There is need for tools and techniques to quantify damage in deployed systems in absence of macro-indicators of damage without knowledge of prior stress history. The presented PHM framework is targeted towards high reliability applications such as avionic and space systems. In this paper, Sn3.0Ag0.5Cu alloy packages have been subjected to multiple thermal cycling environments including -55 to 125C and 0 to 100C. Assemblies investigated include area-array packages soldered on FR4 printed circuit cards. The methodology involves the use of condition monitoring devices, for gathering data on damage pre-cursors at periodic intervals. Damage-state interrogation technique has been developed based on the Levenberg-Marquardt Algorithm in conjunction with the microstructural damage evolution proxies. The presented technique is applicable to electronic assemblies which have been deployed on one thermal environment, then withdrawn from service and targeted for redeployment in a different thermal environment. Test cases have been presented to demonstrate the viability of the technique for assessment of prior damage, operational readiness and residual life for assemblies exposed to multiple thermo-mechanical environments. Prognosticated prior damage and the residual life show good correlation with experimental data, demonstrating the validity of the presented technique for multiple thermo-mechanical environments.

Method for extraction of solder-interconnect strain history has been developed for area-array packages subjected to transient-deformation during shock. Relative damage-index based on the leadfree interconnect transient strain history from digital image correlation, explicit finite-elements, cohesive-zone elements, and component's survivability envelope has been developed for life-prediction of two-leadfree electronic alloy systems. Life prediction of pristine and thermally-aged assemblies, have been investigated. Solder alloy system studied include Sn1Ag0.5Cu, and 96.5Sn3.5Ag. Transient strains during the shock-impact have been measured using digital image correlation in conjunction with high-speed cameras operating at 50,000 fps. Both the board strains and the package strains have been measured in a variety of drop orientations including JEDEC horizontal drop orientation, vertical drop orientation and intermediate drop orientations. In addition the effect of sequential stresses of thermal aging and shock-impact on the failure mechanisms has also been studied. The thermal aging condition used for the study includes 125°C for 100hrs. The presented methodology addresses the need for life prediction of new lead-free alloy-systems under shock and vibration, which is largely beyond the state of art. Three failure modes have been predicted including interfacial failure at the copper-solder interface, solder-PCB interface, and the solder joint failure. Explicit non-linear finite element models with cohesive-zone elements have been developed and correlated with experimental results. Velocity data from digital image correlation has been used to drive the attachment degrees of freedom of the submodel and extract transient interconnect strain histories. Explicit finite-element sub-modeling has been correlated with the full-field strain in various locations, orientations, on both the package and the board-side. The survivability of the leadfree interconnections under sequential loading (thermal aging and shock-impact) from simulation has been compared with pristine circuit assemblies subjected to shock-impact. Sequential loading changes the failure modes and decreases the drop reliability as compared to the room temperature experimental results. Damage index based survivability envelope is intended for component integration to ensure reliability in harsh environments. Index Terms: Leadfree Alloys, Ball grid array (BGA), digital image correlation, solder joint fatigue, transient dynamics, shock reliability prediction, Finite element models.

Thermal cycling accelerated life testing is often used to qualify area array packages (e.g. Ball Grid Arrays and Flip Chip) for various applications. Finite element life predictions for thermal cycling configurations are challenging due to the complicated temperature/time dependent constitutive relations and failure criteria needed for solders and encapsulants and their interfaces, aging/evolving material behavior (e.g. solders), difficulties in modeling plating finishes, the complicated geometries of typical electronic assemblies, etc. In addition, insitu measurements of stresses and strains in assemblies subjected to temperature cycling is difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, we really know quite little about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling. In our research, we are using test chips containing piezoresistive stress sensors to continuously characterize the insitu die surface stress during long-term thermal cycling of several different area array packaging technologies including plastic ball grid array (PBGA) components, ceramic ball grid array (CBGA) components, and flip chip on laminate assemblies. The utilized (111) silicon test chips are able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The die stresses are initially measured at room temperature after packaging. The assemblies are then subjected to thermal cycling over various temperature ranges including 0 to 100 °C, -40 to 125 °C, and -55 to 125 °C, for up to 3000 thermal cycles. During the thermal cycling, sensor resistances at critical locations on the die device surface (e.g. the die center and die corners) are recorded. From the resistance data, the stresses at each site can be calculated and plotted versus time. The experimental observations show significant cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage. The observed stress variations as a function of thermal cycling duration are also being correlated with the observed delaminations at the die surface (as measured using scanning acoustic microscopy (C-SAM)) and finite element simulations that include material constitutive models that incorporate thermal aging effects.

Leading indicators of failure have been developed based on high-frequency characteristics, and system-transfer function derived from resistance spectroscopy measurements during shock and vibration. The technique is intended for condition monitoring in high reliability applications where the knowledge of impending failure is critical and the risks in terms of loss-offunctionality are too high to bear. Previously, resistance spectroscopy measurements [Constable 1992, Lizzul 1994, Prassana 1995] have been used during thermal cycling tests to monitor damage progression due to thermo-mechanical stresses. The development of resistance spectroscopy based damage pre-cursors for prognostication under shock and vibration is new. In this paper, the high-frequency characteristics, and system transfer function based on resistance spectroscopy measurements have been correlated with the damage progression in electronics during shock and vibration. Packages being examined include ceramic area-array packages. Second level interconnect technologies examined include copper-reinforced solder column, SAC305 solder ball, and 90Pb10Sn high-lead solder ball. Assemblies have been subjected to 1500g, 0.5 ms pulse [JESD-B2111]. Continuity has been monitored in-situ during the shock test for identification of part-failure. Resistance spectroscopy based damage pre-cursors have been correlated with the optically measured transient strain based feature vectors. High speed cameras have been used to capture the transient strain histories during shock-impact. Statistical pattern recognition techniques have been used to identify damage initiation and progression and determine the statistical significance in variance between healthy and damaged assemblies. Models for healthy and damaged packages have been developed based on package characteristics. Data presented shows that high-frequency characteristics and system-transfer characteristics based on resistance spectroscopy measurements can be used for condition-monitoring, damage initiation and progression in electronic systems. A positive prognostic distance has been demonstrated for each of the interconnect technologies tested.

Electronic assemblies deployed in harsh environments may be subjected to multiple thermal environments during the use-life of the equipment. Often the equipment may not have any macro-indicators of damage such as cracks or delamination. Quantification of thermal environments during use-life is often not feasible because of the data-capture and storage requirements, and the overhead on core-system functionality. There is need for tools and techniques to quantify damage in deployed systems in absence of macro-indicators of damage without knowledge of prior stress history. The presented PHM framework is targeted towards high reliability applications such as avionic and space systems. In this paper, Sn3.0Ag0.5Cu alloy packages have been subjected to multiple thermal cycling environments including -55 to 125C and 0 to 100C. Assemblies investigated include area-array packages soldered on FR4 printed circuit cards. The methodology involves the use of condition monitoring devices, for gathering data on damage pre-cursors at periodic intervals. Damage-state interrogation technique has been developed based on the Levenberg-Marquardt Algorithm in conjunction with the microstructural damage evolution proxies. The presented technique is applicable to electronic assemblies which have been deployed on one thermal environment, then withdrawn from service and targeted for redeployment in a different thermal environment. Test cases have been presented to demonstrate the viability of the technique for assessment of prior damage, operational readiness and residual life for assemblies exposed to multiple thermo-mechanical environments. Prognosticated prior damage and the residual life show good correlation with experimental data, demonstrating the validity of the presented technique for multiple thermo-mechanical environments.

Modeling transient-dynamics of electronic assemblies is a multiscale problem requiring methodologies which allow the capture of layer dimensions of solder interconnects, pads, and chip-level interconnects simultaneously with assembly architecture and rigid-body motion. Computational effort needed to attain fine mesh to model chip interconnects while capturing the system-level dynamic behavior is challenging. Product-level testing depends heavily on experimental methods and is influenced by various factors such as the drop height, orientation of drop, and variations in product design. Modeling and simulation of integrated circuit (IC) packages are very efficient tools for design analysis and optimization. Previously, various modeling approaches have been pursued to predict the transient dynamics of electronics assemblies assuming symmetry of the electronic assemblies. In this paper, modeling approaches to predict the solder joint reliability in electronic assemblies subjected to high mechanical shocks have been developed. Two modeling approaches are proposed in this paper to enable life prediction under both symmetric and anti-symmetric transient-deformation. In the first approach, drop simulations of printed circuit board assemblies in various orientations have been carried out using beam-shell modeling methodologies without any assumptions of symmetry. This approach enables the prediction of full-field stress-strain distribution in the system over the entire drop event. Transient dynamic behavior of the board assemblies in free and JEDEC drop has been measured using high-speed strain and displacement measurements. Relative displacement and strain histories predicted by modeling have been correlated with experimental data. Failure data obtained by solder joint array tensile tests on ball grid array packages is used as a failure proxy to predict the failure in solder interconnections modeled using Timoshenko beam elements in the global model. In the second approach, cohesive elements have been incorporated in the local model at the solder joint-copper pad interface at both the printed circuit board (PCB) and package side. The constitutive response of the cohesive elements was based on a traction-separation behavior derived from fracture mechanics. Damage initiation and evolution criteria are specified to ensure progressive degradation of the material stiffness leading to cohesive element failure. Use of cohesive zone modeling (CZM) enabled the detection of dynamic crack initiation and propagation leading to intermetallic compound (IMC) brittle failure in PCB assemblies subject to drop impact. Data on solder interconnect failure has been obtained under free-drop and JEDEC-drop test.

Electronics may be subjected to shock, vibration, and drop-impact during shipping, handling and during normal usage. Measurement of transient dynamic deformation of the electronics assemblies during the shock and vibration can yield significant insights in understanding the occurrence of failure modes and the development of failure envelopes. Failure-modes include solder-joint failures, pad cratering, chip-cracking, copper trace fracture, and underfill fillet failures. Previous researchers have measured the transient-dynamics of board assemblies with high-speed imaging in conjunction with high-speed image analysis for measurement of relative displacement, angle, velocity, and acceleration. In addition, high-speed data-acquisition systems with discrete strain gages have been used for measurements of transient strain and with accelerometers for measurement of transient acceleration. Development of accurate models requires better understanding of full-field strain deformation in board assemblies. In this paper, the use of digital image correlation (DIC) with ultra high-speed imaging has been used for full-field measurement of transient strain in various board assemblies subjected to shock in various orientations. Measurements have been taken on both the package and the board side of the assemblies. Accuracy of high-speed optical measurement has been compared with that from discrete strain gages. Package architectures examined include- flex ball-grid arrays, tape-array ball-grid arrays, and metal lead-frame packages. Explicit finite-element models have been developed and correlated with experimental data. Models developed include, smeared property models, Timoshenko-beam models, and explicit sub-models. The solder strains have been computed from the explicit finite element models for life prediction in shock.

The built-in stress test (BIST) is extensively used for diagnostics or identification of failure. The current version of BIST approach is focused on reactive failure detection and provides limited insight into reliability and residual life. A new approach has been developed to monitor product-level damage during shock and vibration. The approach focuses on the prefailure space and methodologies for quantification of failure in electronic equipment subject to shock and vibration loads using the dynamic response of the electronic equipment. The presented methodologies are applicable at the system level for the identification of impending failures to trigger repair or replacement significantly prior to failure. Leading indicators of shock-damage have been developed to correlate with the damage initiation and progression in shock and drop of electronic assemblies. Three methodologies have been investigated for feature extraction and health monitoring including development of a new solder interconnect built-in reliability test, FFT-based statistical-pattern recognition, and time-frequency moments based statistical pattern recognition. The solder-joint built-in reliability test has been developed for detecting high resistance and intermittent faults in operational, fully programmed field programmable gate arrays. Frequency band energy is computed using FFT and utilized as the classification feature to check for damage and failure in the assembly. In addition, the time-frequency analysis has been used to study the energy densities of the signal in both time and frequency domains, and provide information about the time evolution of frequency content of transient strain signal. Closed-form models and explicit finite-element models have been developed for the eigen frequencies, mode shapes, and transient response of electronic assemblies with various boundary conditions and component placement configurations. Model predictions have been validated with experimental data from modal analysis. Pristine configurations have been perturbed to quantify the degradation in confidence values with progression of damage. Sensitivity of leading indicators of shock damage to subtle changes in boundary conditions, effective flexural rigidity, and transient strain response has been quantified.

In this paper, a methodology for prognostication- of-electronics has been developed for assessment of residual life in deployed electronic components, and the determination of damage-state in absence of macro-indicators of failure. Proxies for leading indicators-of-failure have been identified and correlated with damage progression under thermomechanical loads. Examples of proxies include micro-structural evolution characterized by average phase size and intermetallic growth rate in solder interconnects. Validity of damage proxies has been investigated for both 63Sn37Pb leaded and SnAgCu lead-free electronics. Structures examined include plastic ball grid array format electronic and MEMS packages and discrete devices assembled with FR4-06 laminates. The focus of the research presented in this paper is on interrogation of the aged material's damage state and enhancing the understanding of damage progression. Instead of life prediction of new components, the research is aimed at the development of damage relationships for determination of residual life of aged electronics and the assessment of design margins. The prognostic indicators presented in this paper can be used for health monitoring of electronic assemblies.

The microstructure, mechanical response, and failure behavior of lead free solder joints in electronic assemblies are constantly evolving when exposed to isothermal aging and/or thermal cycling environments. In our prior work on aging effects, we have demonstrated that the observed material behavior variations of Sn-Ag-Cu (SAC) lead free solders during room temperature aging (25 °C) and elevated temperature aging (125 °C) were unexpectedly large and universally detrimental to reliability. Such effects for lead free solder materials are especially important for the harsh applications environments present in high performance computing and in automotive, aerospace, and defense applications. However, there has been little work in the literature, and the work that has been done has concentrated on the degradation of solder ball shear strength (e.g. Dage Shear Tester). Current finite element models for solder joint reliability during thermal cycling accelerated life testing are based on traditional solder constitutive and failure models that do not evolve with material aging. Thus, there will be significant errors in the calculations with the new lead free SAC alloys that illustrate dramatic aging phenomena. In the current work, we have extended our previous studies to include a full test matrix of aging temperatures and solder alloys. The effects of aging on mechanical behavior have been examined by performing stress-strain and creep tests on four different SAC alloys (SAC105, SAC205, SAC305, SAC405) that were aged for various durations (0-6 months) at room temperature (25 °C), and several elevated temperatures (50, 75, 100, and 125 °C). Analogous tests were performed with 63Sn- 37Pb eutectic solder samples for comparison purposes. Variations of the mechanical and creep properties (elastic modulus, yield stress, ultimate strength, creep compliance, etc.) were observed and modeled as a function of aging time and aging temperature. In this paper, we report on the creep results. The chosen selection of SAC alloys has allowed us to explore the effects of silver content on aging behavior (we have examined SACN05 with N= 1%, 2%, 3%, and 4% silver; with all alloys containing 0.5% copper). In order to reduce the aging induced degradation of the material behavior of the SAC alloys, we are testing several doped SAC alloys in our ongoing work. These materials include SAC0307-X, SAC105-X, and SAC305-X; where the standard SAC alloys have been modified by the addition of small percentages of one or more additional elements (X). Using dopants (e.g. Bi, In, Ni, La, Mg, Mn, Ce, Co, Ti, etc.) has become widespread to enhance shock/drop reliability, and we have extended this approach to examine the ability of dopants to reduce the effects of aging and extend thermal cycling reliability.

Multi-element resistor rosettes on silicon are widely utilized to measure integrated circuit die stress in electronic packages and other applications. Previous analyses of many sources of error have led to rosette optimization and the realization that temperature compensated stress extraction should be used whenever possible. A previous paper initated a study of the errors in stress extraction due to the inherent uncertainty in knowledge of the values of the piezoresistive coefficients and temperature. In this work, we apply the earlier results to an analysis of the sensitivities and errors in the extracted stresses on an integrated circuit die in a flip-chip package. A finite-element model for a basic flip-chip configuration is utilized to estimate the stress across the surface of the silicon die. These results are used to evaluate the stress sensitivities to coefficient and temperature errors throughout the die surface. The sensitivities are stress dependent and vary widely from very small to very large over the die surface. The results confirm that temperature compensated rosette configurations should be utilized whenever possible.

Failures in electronics subjected to shock and vibration are typically diagnosed using the built-in self test (BIST) or using continuity monitoring of daisy-chained packages. The BIST which is extensively used for diagnostics or identification of failure, is focused on reactive failure detection and provides limited insight into reliability and residual life. In this paper, a new technique has been developed for health monitoring and failure mode classification based on measured damage precursors. A feature extraction technique in the joint-time frequency domain has been developed along with pattern classifiers for fault diagnosis of electronics at product-level. The Karhunen Loéve transform (KLT) has been used for feature reduction and de-correlation of the feature vectors for fault mode classification in electronic assemblies. Euclidean, and Mahalanobis, and Bayesian distance classifiers based on joint-time frequency analysis, have been used for classification of the resulting feature space. Previously, the authors have developed damage pre-cursors based on time and spectral techniques for health monitoring of electronics without reliance on continuity data from daisychained packages. Statistical Pattern Recognition techniques based on wavelet packet energy decomposition [Lall 2006a] have been studied by authors for quantification of shock damage in electronic assemblies, and auto-regressive moving average, and time-frequency techniques have been investigated for system identification, condition monitoring, and fault detection and diagnosis in electronic systems [Lall 2008]. However, identification of specific failure modes was not possible. In this paper, various fault modes such as solder inter-connect failure, inter-connect missing, chip delamination chip cracking etc in various packaging architectures have been classified using clustering of feature vectors based on the KLT approach [Goumas 2002]. The KLT de-correlates the feature space and identifies dominant directions to describe the space, eliminating directions that encode little useful information about the features [Qian 1996, Schalkoff 1972, Theodoridis 1998, Tou 1974]. The clustered damage pre-cursors have been correlated with underlying damage. Several chip-scale packages have been studied, with leadfree second-level interconnects including SAC105, SAC305 alloys. Transient strain has been measured during the drop-event using digital image correlation and high-speed cameras operating at 100,000 fps. Continuity has been monitored simultaneously for failure identification. Fault-mode classification has been done using KLT and joint-time-frequency analysis of the experimental data. In addition, explicit finite element models have been developed and various kinds of failure modes have been simulated such as solder ball cracking, trace fracture, package falloff and solder ball failure. Models using cohesive elements present at the solder joint-copper pad interface at both the PCB and package side have also been created to study the tractionseparation behavior of solder. Fault modes predicted by simulation based pre-cursors have been correlated with those from experimental data.

Electronic assemblies deployed in harsh environments may be subjected to multiple thermal environments during the use-life of the equipment. Often the equipment may not have any macro-indicators of damage such as cracks or delamination. Quantification of thermal environments during use-life is often not feasible because of the data-capture and storage requirements, and the overhead on core-system functionality. There is need for tools and techniques to quantify damage in deployed systems in absence of macro-indicators of damage without knowledge of prior stress history. The presented PHM framework is targeted towards high reliability applications such as avionic and space systems. In this paper, Sn3.0Ag0.5Cu alloy packages have been subjected to multiple thermal cycling environments including -55 to 125C and 0 to 100C. Assemblies investigated include area-array packages soldered on FR4 printed circuit cards. The methodology involves the use of condition monitoring devices, for gathering data on damage pre-cursors at periodic intervals. Damage-state interrogation technique has been developed based on the Levenberg-Marquardt Algorithm in conjunction with the microstructural damage evolution proxies. The presented technique is applicable to electronic assemblies which have been deployed on one thermal environment, then withdrawn from service and targeted for redeployment in a different thermal environment. Test cases have been presented to demonstrate the viability of the technique for assessment of prior damage, operational readiness and residual life for assemblies exposed to multiple thermo-mechanical environments. Prognosticated prior damage and the residual life show good correlation with experimental data, demonstrating the validity of the presented technique for multiple thermo-mechanical environments.

Relative damage-index based on the leadfree interconnect transient strain history from digital image correlation, explicit finite-elements, cohesive-zone elements, and component's survivability envelope has been developed for life-prediction of two-leadfree electronic alloy systems. Life prediction of pristine and thermally-aged assemblies, have been investigated. Solder alloy system studied include Sn1Ag0.5Cu, and 96.5Sn3.5Ag. Transient strains during the shock-impact have been measured using digital image correlation in conjunction with high-speed cameras operating at 50,000 fps. Both the board strains and the package strains have been measured in a variety of drop orientations including JEDEC horizontal drop orientation, vertical drop orientation and intermediate drop orientations. In addition the effect of sequential stresses of thermal aging and shock-impact on the failure mechanisms has also been studied. The thermal aging condition used for the study includes 125°C for 100hrs. The presented methodology addresses the need for life prediction of new lead-free alloysystems under shock and vibration, which is largely beyond the state of art. Three failure modes have been predicted including interfacial failure at the copper-solder interface, solder-PCB interface, and the solder joint failure. Explicit non-linear finite element models with cohesive-zone elements have been developed and correlated with experimental results. Velocity data from digital image correlation has been used to drive the attachment degrees of freedom of the submodel and extract transient interconnect strain histories. Explicit finite-element sub-modeling has been correlated with the full-field strain in various locations, orientations, on both the package and the board-side. The survivability of the leadfree interconnections under sequential loading (thermal aging and shock-impact) from simulation has been compared with pristine circuit assemblies subjected to shock-impact. Sequential loading changes the failure modes and decreases the drop reliability as compared to the room temperature experimental results. Damage index based survivability envelope is intended for component integration to ensure reliability in harsh environments.

Leading indicators of failure have been developed based on high-frequency characteristics, and system-transfer function derived from resistance spectroscopy measurements during shock and vibration. The technique is intended for condition monitoring in high reliability applications where the knowledge of impending failure is critical and the risks in terms of loss-offunctionality are too high to bear. Previously, resistance spectroscopy measurements [Constable 1992, Lizzul 1994, Prassana 1995] have been used during thermal cycling tests to monitor damage progression due to thermo-mechanical stresses. The development of resistance spectroscopy based damage pre-cursors for prognostication under shock and vibration is new. In this paper, the high-frequency characteristics, and system transfer function based on resistance spectroscopy measurements have been correlated with the damage progression in electronics during shock and vibration. Packages being examined include ceramic area-array packages. Second level interconnect technologies examined include copper-reinforced solder column, SAC305 solder ball, and 90Pb10Sn high-lead solder ball. Assemblies have been subjected to 1500g, 0.5 ms pulse [JESD-B2111]. Continuity has been monitored in-situ during the shock test for identification of part-failure. Resistance spectroscopy based damage pre-cursors have been correlated with the optically measured transient strain based feature vectors. High speed cameras have been used to capture the transient strain histories during shock-impact. Statistical pattern recognition techniques have been used to identify damage initiation and progression and determine the statistical significance in variance between healthy and damaged assemblies. Models for healthy and damaged packages have been developed based on package characteristics. Data presented shows that high-frequency characteristics and system-transfer characteristics based on resistance spectroscopy measurements can be used for condition-monitoring, damage initiation and progression in electronic systems. A positive prognostic distance has been demonstrated for each of the interconnect technologies tested.

Goldmann Constants and Norris-Landzberg acceleration factors for lead-free solders have been developed based on principal component regression models (PCR) for reliability prediction and part selection of area-array packaging architectures under thermo-mechanical loads. Models have been developed in conjunction with Stepwise Regression Methods for identification of the main effects. Package architectures studied include, BGA packages mounted on copper-core and no-core printed circuit assemblies in harsh environments. The models have been developed based on thermo-mechanical reliability data acquired on copper-core and no-core assemblies in four different thermal cycling conditions. Packages with Sn3Ag0.5Cu solder alloy interconnects have been examined. The models have been developed based on perturbation of accelerated test thermo-mechanical failure data. Data has been gathered on nine different thermal cycle conditions with SAC305 alloys. The thermal cycle conditions differ in temperature range, dwell times, maximum temperature and minimum temperature to enable development of constants needed for the life prediction and assessment of acceleration factors. Goldmann Constants and the Norris-Landzberg acceleration factors have been benchmarked against previously published values. In addition, model predictions have been validated against validation data-sets which have not been used for model development. Convergence of statistical models with experimental data has been demonstrated using a single factor design of experiment study for individual factors including temperature cycle magnitude, relative coefficient of thermal expansion, and diagonal length of the chip. The predicted and measured acceleration factors have also been computed and correlated. Good correlations have been achieved for parameters examined. Previously, the feasibility of using multiple linear regression models for reliability prediction has been demonstrated for flex-substrate BGA packages [Lall 2004, 2005], flip-chip packages [Lall 2005] and ceramic BGA packages [Lall 2007]. The presented methodology is valuable in the development of fatigue damage constants for the application specific accelerated test data-sets and provides a method to develop institutional learning based on prior accelerated test data.

Microelectronic encapsulants exhibit evolving properties that change significantly with environmental exposures such as isothermal aging and thermal cycling. Such aging effects are exacerbated at higher temperatures typical of thermal cycling qualification tests for harsh environment electronic packaging. In this work, measurements of material behavior changes occurring in flip chip underfill encapsulants exposed to isothermal aging have been performed. A novel method has been developed to fabricate freestanding underfill uniaxial test specimens so that they accurately reflect the encapsulant layer present in flip chip assemblies. Using the developed specimen preparation procedure, isothermal aging effects have been characterized at several elevated temperatures (+ 80, +100, +125, and +150 °C). Samples have been aged at the four temperatures for periods up to 6 months. Stress-strain and creep tests have been performed on non-aged and aged samples, and the changes in mechanical behavior have been recorded for the various aging temperatures and durations of isothermal exposure. Empirical models have been developed to predict the evolution of the material properties (modulus, strength) and the creep strain rate as a function of temperature, aging time, and aging temperature. The evaluated underfill illustrated softening behavior at temperatures exceeding 100 °C, although the documented Tg ranged from 130-150 °C. The obtained results showed an obvious enhancement of the underfill mechanical properties as a function of the aging temperature and aging time. Both the effective elastic modulus (initial slope) and ultimate tensile strength (highest stress before failure) increase monotonically with the amount of isothermal aging or aging temperature, regardless of whether the aging temperature is below, at, or above the Tg of the material. From the creep results, it was seen that at a given time, the creep strains were much lower for the aged samples relative to the non-aged samples. Thermal aging has a significant effect on the secondary creep rate, which decreases with both the aging temperature and the aging time. Up to a 100X reduction in the creep rate was observed, and the major changes occurred during the first 50 days of the isothermal aging.

A nun-destructive method was used to determine the effects of thermal cycling on the thermal performance of a PCB attached to an aluminum substrate with a thermal adhesive. This method allows for a comparison of the thermal performance of various TIMs in an industrial application. Testing was done on FR4 and Flex boards, both with and without over molding, attached using PSA and an alternative adhesive. Baseline measurements were taken, then the boards were cycled from -40 to 125°C on a 90-minute cycle with 15-minute dwells at the target temperatures. It was found that both adhesives showed an increase in thermal conductivity, possibly due to curing, and delamination occurred at 17 out of 35 locations with the alternative adhesive within the first 1000 cycles while no delamination occurred with the PSA.

On-chip piezoresistive stress sensors represent a unique approach for characterizing stresses in silicon die embedded within complicated packaging architectures. In this work, we have used test chips containing such sensors to measure the stresses induced in microprocessor die after various steps of the assembly process, as well as to continuously characterize the in-situ die surface stress during thermal cycling and power cycling. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 x 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. Finally, a metallic lid was attached to complete the ceramic LGA package. After every packaging step (solder reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. The build-up of the die stresses was found to be monotonically increasing, and the relative severity of each assembly step was judged and compared. Such an approach also allows for various material sets (solders, underfills, TIM materials, lid metals, and lid adhesives) to be analyzed and rated for their contribution to the die stress level. After first level packaging of the chips on the ceramic chip carriers, initial experiments have been performed to analyze the effects of thermal cycling and power cycling on the die stresses. Thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). Power cycling of selected parts was performed by exciting the on-chip heaters on the test chips with power levels typical of microprocessor die. During the thermal/power cycling, sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously. From the resistance data, the stresses at each site were calculated and plotted versus time. The experimental observations show some cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage. The observed stress variations as a function of temperature cycling duration are currently being correlated with the delaminations occurring at the interfaces between the die and underfill and the die and lid adhesive. In addition, finite element models of the packages are being developed and correlated with the data.

The transition from tin-lead to lead free soldering in the electronics manufacturing industry has been in progress for the past 10 years. In the interim period before lead free assemblies are uniformly accepted, mixed formulation solder joints are becoming commonplace in electronic assemblies. For example, area array components (BGA/CSP) are frequently available only with lead free Sn-Ag-Cu (SAC) solder balls. Such parts are often assembled to printed circuit boards using traditional 63Sn-37Pb solder paste. The resulting solder joints contain unusual quaternary alloys of Sn, Ag, Cu, and Pb. In addition, the alloy composition can vary across the solder joint based on the paste to ball solder volumes and the reflow profile utilized. The mechanical and physical properties of such Sn- Ag-Cu-Pb alloys have not been explored extensively in the literature. In addition, the reliability of mixed formulation solder joints is poorly understood. In this work, we have explored the physical properties and mechanical behavior of mixed formulation solder materials. Seven different mixture ratios of 63Sn-37Pb and SAC305 solder materials have been formed, which include five carefully controlled mixtures of the two solder alloys (by weight percentage) and the two extreme cases (pure Sn-Pb and pure SAC). For the various percentage mixtures, the melting point, pasty range, stress-strain curves, mechanical properties (modulus, strength), and creep curves have been characterized. The variations of the mechanical properties and creep rates with aging at room temperature (25 °C) and elevated temperature (100 °C) have also been measured. Finally, the microstructures realized with the various mixtures have been found and correlated to the mechanical measurements and microstructures found in actual mixed formulation BGA solder joints. The results for the mechanical and physical properties show a very complicated dependence on the mixture ratio.

A wavelet-packet energy decomposition, and time frequency analysis based approach has been developed to monitor system-level damage in implantable biological electronic systems such as pacemakers and defibrillators. The approach focuses is on the pre-failure space and methodologies for quantification of failure in electronic equipment. Presented methodologies are applicable at the system-level for identification of impending failures to trigger repair or replacement significantly prior to failure. Leading indicators of shock-damage have been developed to correlate with the damage initiation and progression in under variety of stresses in electronic system. Currently, the built-in stress test (BIST) which is extensively used for diagnostics or identification of failure, is focused on reactive failure detection and provides limited insight into reliability and residual life. Statistical Pattern Recognition Techniques including, wavelet packet energy decomposition, and time-frequency (TFA) techniques have been investigated for system identification, condition monitoring, and fault detection and diagnosis in electronic systems. Reduced reliance on system analysis helps avoid errors which otherwise may render the process of fault detection and diagnosis quite complex and dependent on the skill of the analyst. Explicit finite element models have been developed and various kinds of failure modes have been simulated such as solder ball cracking, package fall off and solder ball failure. The above damage monitoring approach is not based on electrical continuity and hence can be applied to any biological system irrespective of the interconnections. The damage index developed provides parametric damage progression data, thus removing the limitation of current failure testing, where the damage progression can not be monitored.

electronics manufacturing industry has been in steady progress for many years all over the world. However, this fundamental change in soldering technique is by no means an achieved task and there are still some critical issues waiting to be resolved. At the same time, an interim stage characterized by mixed application of tin-lead and lead free solders has been widely acknowledged within the industry. Both benefits and uncertainties involved in this interim stage have been gradually investigated and discussed. One critical issue that causes contradiction in study is the compatibility between lead free solders (especially Sn-Ag- Cu alloy system) and tin-lead solders. For example, area array components (BGA/CSP) with lead free SAC solder balls are often assembled to printed circuit boards using traditional 63Sn-37Pb solder paste. Some studies suggest improved reliability of solder joints, whereas others indicate inferior performance. This contradiction may be caused by various reasons, but the lack of data on the mechanical and physical properties of this Sn-Ag-Cu + Pb alloy formed at solder joints is the problem that needs to be addressed in the first place. In current study, the physical and mechanical properties of mixed formulation solder alloys have been explored. Seven different mixture ratios of 63Sn-37Pb and SAC305 solder alloys have been formed, which include five carefully controlled mixtures of the two solder alloys (by weight percentage) and the two extreme cases (pure Sn-Pb and pure SAC305). For the various percentage mixtures, the melting point, pasty range, microstructure and mechanical properties (modulus and strength) have been characterized. Aging effects have been explored in detail. The results show a very complicated nonlinear dependence of properties on the mixture ratio.

Aerospace-electronic systems usually face a very harsh environment, requiring them to survive the high strain rates, e.g. during launch and re-entry and thermal environments including extreme low and high temperatures. Traditional health monitoring methodologies have relied on reactive methods of failure detection often providing little or no insight into the remaining useful life of the system. In this paper, a mathematical approach for interrogation of system state under cyclic thermomechanical stresses has been developed for 6-different leadfree solder alloy systems. Data has been collected for leading indicators of failure for alloy systems including, Sn3Ag0.5Cu, Sn3Ag0.7Cu, Sn1Ag0.5Cu, Sn0.3Ag0.5Cu0.1Bi, Sn0.2Ag0.5Cu0.1Bi0.1Ni, 96.5Sn3.5Ag second-level interconnects under the application of cyclic thermo-mechanical loads. Methodology presented resides in the pre-failure space of the system in which no macro-indicators such as cracks or delamination exist. Systems subjected to thermo-mechanical damage have been interrogated for system state and the computed damage state correlated with known imposed damage. The approach involves the use of condition monitoring devices which can be interrogated for damage proxies at finite timeintervals. Interrogation techniques are based on derivation of damage proxies, and system prior damage based non-linear least-squares methods including the Levenberg-Marquardt Algorithm. The system's residual life is computed based on residual-life computation algorithms.

In this paper, the feature extraction for health monitoring based on optical measurements of transientstrain from digital image correlation (DIC) in conjunction with ultra high-speed imaging has been investigated. Full-field measurement of transient strain have been made in various board assemblies subjected to shock in various orientations. Feature-extraction for health monitoring of leadfree area array architectures based on statistical pattern recognition has been presented. Previous researchers have measured the transient-dynamics of board assemblies with high-speed imaging in conjunction with high-speed image analysis for measurement of relative displacement, angle, velocity, and acceleration [Lall 2006, Che 2006], high-speed data-acquisition systems with discrete strain gages [Lall 2004, 2005, Liang 2005] and with accelerometers for measurement of transient acceleration [Dunford 2004, Goyal 2000, Seah 2005]. Degradation in confidence value gives a leading indication of component failure. Package architectures examined include-flex ball-grid arrays, tape-array ballgrid arrays, and metal lead-frame packages. Statistical Pattern Recognition Techniques including, mahalanobisdistance approach, wavelet packet energy decomposition, and time-frequency (TFA) techniques have been investigated for system identification, condition monitoring, and fault detection and diagnosis in electronic systems. Explicit finite element models have been developed and various kinds of failure modes have been simulated such as solder ball cracking, package fall off and solder ball failure. Models developed include, smeared property models, Timoshenko-beam models, and explicit sub-models. Explicit finite-element models have been correlated with experimental data. The presented approach does not depend on continuity and therefore does not need daisy-chained devices for detection of failure.

In this paper, a mathematical approach for interrogation of system state under cyclic thermo-mechanical stresses has been developed for 6-different leadfree solder alloy systems. Data has been collected for leading indicators of failure for alloy systems including, Sn1Ag0.5Cu, Sn3Ag0.5Cu, Sn4Ag0.5Cu second-level interconnects under the application of cyclic thermo-mechanical loads. Methodology presented resides in the pre-failure space of the system in which no macroindicators such as cracks or delamination exist. Systems subjected to thermo-mechanical damage have been interrogated for system state and the computed damage state correlated with known imposed damage. The approach involves the use of condition monitoring devices which can be interrogated for damage proxies at finite time-intervals. Interrogation techniques are based on non-linear least-squares methods. Various techniques including the Levenberg-Marquardt Algorithm have been investigated. The system's residual life is computed based on residual-life computation algorithms. Detection of system-state significantly prior to catastrophic failure can significantly impact the reliability and availability of electronic systems. Requirements for system availability for ultra-high reliability electronic systems are driving the need for advanced heath monitoring techniques for early detection of onset of damage. Traditional health monitoring methodologies have relied on reactive methods of failure detection often providing little on no insight into the remaining useful life of the system.

In this work, thermo-mechanical models for reliability prediction of BGA package interconnects mounted on integral copper-core (Cu-CORE) and no integral copper core (NO-CORE) printed circuit assemblies in harsh environments have been developed. The models have been developed based on thermo-mechanical reliability data acquired on Cu-CORE and NO-CORE assemblies in four different thermal cycling conditions. Solder alloys examined include SnPb and SAC alloys. Multivariate linear regression (MLR), and non-linear finite element models have been developed for prediction of geometry and material effects. The models presented in this paper provide decision guidance for smart selection of component packaging technologies and perturbing product designs for minimal risk insertion of new packaging technologies. In addition, qualitative parameter interaction effects, which are often ignored in closed-form modeling, have been incorporated in this work. The statistics models are based on accelerated test data acquired as part of this paper, in harsh environments, while finite-element models are based on damage mechanics and material constitutive behavior. Convergence of statistical, failure mechanics, and FEAbased model sensitivities with experimental data has been demonstrated. Validation of model predictions with accelerated test data is presented for various parameters including Die to Package Ratio, Ball Count, Ball Diameter, Package Pad Diameter, Surface Finish, Temperature Cycle Condition. The modeling methodology shows good correlation with experimental data.

Product level assessment of drop and shock reliability relies heavily on experimental test methods. Prediction of drop and shock survivability is largely beyond the state-of-art. However, the use of experimental approach to test out every possible design variation, and identify the one that gives the maximum design margin is often not feasible because of product development cycle time and cost constraints. Presently, one of the primary methodologies for evaluating shock and vibration survivability of electronic packaging is the JEDEC drop test method, JESD22-B111 which tests board-level reliability of packaging. However, packages in electronic products may be subjected to a wide-array of boundary conditions beyond those targeted in the test method. In this paper, a failure-envelope approach based on wavelet transforms and damage proxies has been developed to model drop and shock survivability of electronic packaging. Data on damage progression under transient-shock and vibration in both 95.5Sn4.0Ag0.5Cu and 63Sn37Pb ball-grid arrays (BGAs) has been presented. Component types examined include&mdash;flex-substrate and rigid substrate BGAs. Dynamic measurements like acceleration, strain and resistance are measured and analyzed using high-speed data acquisition system capable of capturing in-situ strain, continuity and acceleration data in excess of five million samples per second. High-speed video at 150 000 fps per second has been used to capture the deformation kinematics. The concept of relative damage index has been used to both evaluate and predict damage progression during transient shock. The failure-envelope provides a fundamental basis for development of component integration guidelines to ensure survivability in shock and vibration environments at a user-specified confidence level. The approach is scalable to application at system-level. Explicit finite-element models have been developed for prediction of shock survivability based on the failure envelope. Model predictions have been correlated with experimental data for both leaded and leadfree BGAs.

environments, requiring them to survive the high strain rates, e.g. during launch and re-entry and thermal environments including extreme low and high temperatures. Requirements for system availability and ultra-high reliability in airborne and space electronic systems are driving the need for advanced heath monitoring techniques and early detection of the onset of damage. Traditional health monitoring methodologies have relied on reactive methods of failure detection often providing little on no insight into the remaining useful life of the system. Detection of system-state significantly prior to catastrophic failure can significantly impact the reliability and availability of electronic systems. Previously, Lall, et. al. [2004, 2005, 2006, 2007] have developed methodologies for health management and prognostication of electronic systems based on leading indicators. In this paper, a mathematical approach for interrogation of system state under cyclic and isothermal thermo-mechanical stresses has been developed for 6-different leadfree solder alloy systems. Thermal cycles may be experienced by electronics due to power cycling or environmental cycling. Data has been collected for leading indicators of failure for alloy systems including, Sn-3Ag-0.5Cu, Sn-3Ag-0.7Cu, Sn-1Ag- 0.5Cu, Sn-0.3Ag-0.5Cu-0.1Bi, Sn-0.2Ag-0.5Cu-0.1Bi- 0.1Ni, 96.5Sn-3.5Ag second-level interconnects under the application of cyclic thermo-mechanical loads. Methodology presented resides in the pre-failure space of the system in which no macro-indicators such as cracks or delamination exist. Systems subjected to thermo-mechanical damage have been interrogated for system state and the computed damage state correlated with known imposed damage. The approach involves the use of condition monitoring devices which can be interrogated for damage proxies at finite time-intervals. Damage proxies are based on the micro-structural evolution of damage. Interrogation techniques involve the derivation of damage proxies, and system's prior-damage based non-linear least-squares methods including the Levenberg-Marquardt Algorithm. The system's residual life is computed based on residuallife computation algorithms.

ball-grid array packaging under shock and vibration has been developed using optical measurements based on digital image correlation (DIC) in conjunction with ultra highspeed imaging. Full-field transient strains have been measured on various board assemblies subjected to shock in various orientations. Solder alloy systems investigated include, Sn-1Ag-0.5Cu, Sn-3Ag-0.5Cu, Sn-0.3Ag-0.7Cu, Sn-0.3Ag-0.7Cu-0.1Bi, Sn-0.2Ag-0.7Cu-0.1Bi-0.1Ni, 96.5Sn-3.5Ag. Previously, digital image correlation in electronics industry has been used to study the stresses in packaging under thermal loads, and material characterization. The use of digital image correlation to study survivability, and develop a leading-indication of failure is new. Board assemblies have been subjected to shock-impact in various orientations including the JEDEC zero-degree drop and the vertical free-drop. Transient deformation has been measured using both digital image correlation and the strain gages. Measurements have been taken on both the package and the board side of the assemblies. Accuracy of high-speed optical measurement has been compared with that from discrete strain gages. Explicit finite-element models have been developed and correlated with experimental data. Models developed include, smeared property models, Timoshenko-beam models, and explicit sub-models. The potential of damage identification and tracking for various solder alloys has been investigated. Data on identification of damage proxies for competing failure mechanisms at the copper-to-solder, solder-to-printed circuit board, and copper-to-package substrate has been presented. Design envelopes have been developed based on statistical pattern recognition. The design-envelope is intended for component integration to ensure survivability in shock and vibration environments at a user-specified confidence level.

Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials, second level solder joints, organic PCB, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high CTE ceramic substrates, lead free solder joints, higher level of power generation, and larger heat sinks. Die stress effects are of concern due to the possible degradation of silicon device performance (mobility/speed) and due to the possible damage that can occur to the copper/low-k top level interconnect layers. In this work, we have used test chips containing piezoresistive sensors to measure the stresses induced in microprocessor die after various steps of the assembly process. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 x 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to the high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the stress test die. The chips were reflowed to the ceramic substrate, and then underfilled and cured. Finally, a metallic lid was attached to complete the ceramic LGA package. After every packaging step (solder reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. The build-up of the die stresses was found to be monotonically increasing, and the relative severity of each assembly step was judged and compared. Such an approach allows for various material sets (solders, underfills, TIM materials, lid metals, and lid adhesives) to be analyzed and rated for their contribution to the die stress level.

Silica particles are used as a filler material in electronic underfills to reduce coefficient of thermal expansion of the underfill-epoxy matrix. In traditional underfills, the size of silica particles is in the micrometer range. Reduction in particle sizes into the nanometer range has the potential of attaining higher volume fraction particle loading in the underfills and greater control over underfill properties for higher reliability applications. Presently, no-flow underfills have very low or no filler content because micron-size filler particles hinder solder joint formation. Nano-silica underfills have the potential of attaining higher filler loading in no-flow underfills without hindering solder interconnect formation [9], [16]. In this paper, property prediction models based on representative volume element (RVE) and modified random spatial adsortion have been developed. The models can be used for development of nano-silica underfills with desirable thermo-mechanical properties. Temperature dependent thermo-mechanical properties of nano-underfills have been evaluated and correlated with models in a temperature range of 175 C to +150 C. Properties investigated include, temperature dependent stress-strain, creep and stress relaxation behavior. Nano-underfills on 63Sn37Pb eutectic and 95.5Sn3.5Ag1.0Cu leadfree flip-chip devices have been subjected to thermal shock tests in the range of 55 C to 125 C and 55 C to 150 C, respectively. The trade-offs between using nano-fillers instead of micron-fillers on thermo-mechanical properties and reliability has been benchmarked.

Whiskering refers to the formation of slender, long, metallic filaments, much thinner than a human hair, that grow on a metallic thin film surface. They are readily observed for pure and alloyed zinc (Zn), silver (Ag), cadmium (Cd), indium (In), and tin (Sn) surfaces. The longest reported whisker length is 4.5 mm long but most high-aspect ratio whiskers range from 1-500 µm. The focus of this research is upon Sn whiskers. Sn whiskers pose serious reliability problems for the electronics industry and are known to be the source of failure in a wide range of electronic devices, such as nuclear power facilities, heart pacemakers, commercial satellites, aviation radar, telecommunication equipment, and desktop computers. The problem with whiskering has been recently exacerbated by the worldwide shift to lead (Pb) free electronics and the continuing reduction in electrical contact pitches. A thorough understanding of the growth mechanism of Sn whiskers is urgently needed. Currently, there is no universally accepted model that explains the broad range of observations on whiskering. The goals of this research are: 1) to develop a more detailed understanding of the physical mechanisms leading to the initiation and growth of Sn whiskers and 2) to outline reasonable mitigation strategies that could be followed to reduce or eliminate the problem of Sn whiskers. The major contributions of this work are: 1) A reliable method for growing Sn whiskers with predictable incubation times has been developed and tested, 2) A surface oxide is not necessary for whisker growth, 3) Intermetallic compounds (IMC) are not necessary for whisker growth, 4) Smoother, not rougher, substrate surfaces promote whisker growth, 5) Whiskers grow under both compressive and tensile thin film stress states, 6) Whisker growth increases with externally applied compression and tension forces, 7) Sn whiskers are composed of pure Sn except for the expected thin, native Sn oxide on their surface, 8) For Sn on brass, the atom feedstock for whiskers lies within the film exclusively; the brass substrate does not contribute to whisker production, 9) The volume of film consumed by a metallic whisker is a simple volumetric calculation, 10) There are likely to be multiple mechanisms of whisker growth depending on the substrate &mdash; thin film system, and 11) In general, the thickness of a metallic film does not have an effect on whisker growth qualities.

Thermal cycling accelerated life testing is often used to qualify packages for various pplications. Finite element life predictions for thermal cycling configurations is challenging due to the complicated temperature/time dependent constitutive relations and failure criteria needed for solders and encapsulants and their interfaces, aging/evolving material behavior (e.g. solders), difficulties in modeling plating finishes, the complicated geometries of typical electronic assemblies, etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling is difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, we really know quite little about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling. In our research, we are using test chips containing piezoresistive stress sensors to continuously characterize the in-situ die surface stress during long-term thermal cycling of several different area array packaging technologies including plastic ball grid array (PGA) components, ceramic ball grid array (CBGA) components, and flip chip on laminate assemblies. The utilized (111) silicon test chips are able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The die stresses are initially measured at room temperature after packaging. The assemblies are then subjected to thermal cycling from -40 to 125 °C or from -55 to 125 °C for up to 3000 thermal cycles. During the thermal cycling, sensor resistances at critical locations on the die device surface (e.g. die center and die corners) are recorded. From the resistance data, the stresses at each site can be calculated and plotted versus time. The experimental observations show significant cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage. The observed stress variations as a function of thermal cycling duration are also being correlated with the observed delaminations at the die surface (as measured using scanning acoustic microscopy (C-SAM)) and finite element simulations that include material constitutive models that incorporate thermal aging effects.

Electronic products may be subjected to shock and vibration during shipping, normal usage, and accidental drop. High strain rate transient bending produced by such loads may result in failure of fine pitch electronic interconnects. Current experimental techniques rely on electrical resistance for determination of failure. Significant advantage can be gained by prior knowledge of impending failure for applications where the consequences of system failure may be catastrophic. This research effort focuses on an alternate approach to damage quantification in electronic assemblies subjected to shock and vibration, without testing for electrical continuity. The proposed approach can be extended to monitor product level damage. In this paper, statistical pattern recognition and leading indicators of shock damage have been used to study the damage initiation and progression in shock and drop of electronic assemblies. Statistical pattern recognition is currently being employed in a variety of engineering and scientific disciplines such as biology, psychology, medicine, marketing, artificial intelligence, computer vision, and remote sensing [1]. The application quantification of shock damage in electronic assemblies is new. Previously, free vibration of rectangular plates has been studied by various researchers [2]-[6] for development of analytical closed form models. In this paper, closed form models have been developed for the eigen frequencies and mode shapes of electronic assemblies with various boundary conditions and component placement configurations. Model predictions have been validated with experimental data from modal analysis. Pristine configurations have been perturbed to quantify the degradation in confidence values with progression of damage. Sensitivity of leading indicators of shock damage to subtle changes in boundary conditions, effective flexural rigidity, and transient strain response has been quantified. A damage index for experimental damage monitoring has been developed using the failure indicators. The above damage monitoring approach is not based on electrical continuity and hence can be applied to any electronic assembly structure irrespective of the interconnections. The damage index developed provides parametric damage progression data, thus removing the limitation of current failure testing, where the damage progression cannot be monitored. Hence the proposed method does not require the assumption that the failure occurs abruptly after some number of drops and can be extended to product level drops.

Requirements for system availability for ultra-high reliability electronic systems such as airborne and space electronic systems are driving the need for advanced heath monitoring techniques for early detection of the onset of damage. Aerospace-electronic systems usually face a very harsh environment, requiring them to survive the high strain rates, e.g. during launch and re-entry and thermal environments including extreme low and high temperatures. Traditional health monitoring methodologies have relied on reactive methods of failure detection often providing little on no insight into the remaining useful life of the system. Detection of system-state significantly prior to catastrophic failure can significantly impact the reliability and availability of electronic systems. Previously, Lall, et. al. [2004, 2005, 2006, 2007] have developed methodologies for health management and interrogation of system state of electronic systems based on leading indicators. Examples of damage pre-cursors include micro-structural evolution, intermetallics, stress and stress gradients. Pre-cursors have been developed for both eutectic 63Sn37Pb and Sn4Ag0.5Cu alloy systems on a variety of area-array architectures.

A design-envelope approach based on optical feature extraction techniques has been investigated for drop and shock survivability of electronic packaging has been presented for 6-leadfree solder alloy systems. Solder alloy systems investigated include, Sn1Ag0.5Cu, Sn3Ag0.5Cu, Sn0.3Ag0.7Cu, Sn0.3Ag0.7Cu0.1Bi, Sn0.2Ag0.7Cu0.1Bi-0.1Ni, 96.5Sn3.5Ag. Previously, digital image correlation (DIC) has been used for measurement of thermally-induced deformation and material-characterization. In this paper, DIC has been used for transient dynamic measurements, and optical feature extraction. Board assemblies have been subjected to shock-impact in various orientations including the JEDEC zero-degree drop and the vertical free-drop. Transient deformation has been measured using both digital image correlation and the strain gages. Measurements have been taken on both the package and the board side of the assemblies. Accuracy of high-speed optical measurement has been compared with that from discrete strain gages. Package architectures examined include-flex ball-grid arrays, tapearray ball-grid arrays, and metal lead-frame packages. Explicit finite-element models have been developed and correlated with experimental data. Models developed include, smeared property models, Timoshenko-beam models, and explicit sub-models. The potential of damage identification and tracking for various solder alloys has been investigated. Data on identification of damage proxies for competing failure mechanisms at the copper-to-solder, solder-to-printed circuit board, and copper-to-package substrate has been presented. Design envelopes have been developed based on statistical pattern recognition. The design-envelope is intended for component integration to ensure survivability in shock and vibration environments at a user-specified confidence level.

A new approach based on auto-regressive and timefrequency analysis has been developed to monitor systemlevel damage in implantable biological electronic systems such as pacemakers and defibrillators. The approach focuses is on the pre-failure space and methodologies for quantification of failure in implantable biological electronics subjected to shock and vibration loads using the dynamic response. Presented methodologies are applicable at the system-level for identification of impending failures to trigger repair or replacement significantly prior to failure. Leading indicators of shock-damage have been developed to correlate with the damage initiation and progression in under variety of stresses in electronic systems. The approach is based on monitoring critical solder interconnects, and sensing the change in test-signal characteristics prior to failure, in addition to monitoring the transient strain characteristics optically using digital image correlation and strain gages. Previously, SPR based on wavelet packet energy decomposition and the Mahalanobis distance approach have been studied by the authors for quantification of shock damage in electronic assemblies [Lall 2006a,b]. In this paper, Auto-regressive (AR), wavelet packet energy decomposition, and time-frequency (TFA) techniques have been investigated for system identification, condition monitoring, and fault detection and diagnosis in implantable biological electronic systems. One of the main advantages of the AR technique is that it is primarily a signal based technique. Reduced reliance on system analysis helps avoid errors which otherwise may render the process of fault detection and diagnosis quite complex and dependent on the skills of the analyst. Results of the present study show that the AR and TFA based health monitoring techniques are feasible for fault detection and damage-assessment in electronic units. Explicit finite element models have been developed and various kinds of failure modes have been simulated such as solder ball cracking, package falloff and solder ball failure.

Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials, second level solder joints, organic PCB, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high CTE ceramic substrates, lead free solder joints, higher level of power generation, and larger heat sinks. Die stress effects are of concern due to the possible degradation of silicon device performance (mobility/speed) and due to the possible damage that can occur to the copper/low-k top level interconnect layers. In this work, we have used test chips containing piezoresistive sensors to measure the stresses induced in microprocessor die after various steps of the assembly process. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 x 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to the high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the stress test die. The chips were reflowed to the ceramic substrate, and then underfilled and cured. Finally, a metallic lid was attached to complete the ceramic LGA package. After every packaging step (solder reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. The build-up of the die stresses was found to be monotonically increasing, and the relative severity of each assembly step was judged and compared. Such an approach allows for various material sets (solders, underfills, TIM materials, lid metals, and lid adhesives) to be analyzed and rated for their contribution to the die stress level.

The microstructure, mechanical response, and failure behavior of lead free solder joints in electronic assemblies are constantly evolving when exposed to isothermal aging and/or thermal cycling environments. In our prior work on aging effects (Ma, et al., ECTC 2006 and ECTC 2007), we demonstrated that the observed material behavior variations of SAC305 and SAC405 lead free solders during room temperature aging (25 °C) and elevated temperature aging (125 °C) were unexpectedly large and universally detrimental to reliability. Such effects for lead free solder materials are especially important for the harsh applications environments present in high performance computing and in automotive, aerospace, and defense applications. However, there has been little work in the literature, and the work that has been done has concentrated on the degradation of solder ball shear strength (e.g. Dage Shear Tester). Current finite element models for solder joint reliability during thermal cycling accelerated life testing are based on traditional solder constitutive and failure models that do not evolve with material aging. Thus, there will be significant errors in the calculations with the new lead free SAC alloys that illustrate dramatic aging phenomena. In the current work, we have extended our previous studies to include a full test matrix of aging temperatures and solder alloys. The effects of aging on mechanical behavior are being examined by performing stress-strain and creep tests on four different SAC alloys (SAC105, SAC205, SAC305, SAC405) that were aged for various durations (0-12 months) at room temperature (25 °C), and several elevated temperatures (50, 75, 100, and 125 °C). Analogous tests are being performed with 63Sn-37Pb eutectic solder samples for comparison purposes. Variations of the mechanical and creep properties (elastic modulus, yield stress, ultimate strength, creep compliance, etc.) are being observed and modeled as a function of aging time and aging temperature. In addition, the chosen selection of SAC alloys has allowed us to explore the effects of silver content on aging behavior (we have examined SACN05 with N= 1%, 2%, 3%, and 4% silver; with all alloys containing 0.5% copper). In this paper, we concentrate on presentation of the creep results from our ongoing studies. The results obtained in this work have demonstrated the significant effects of elevated temperature exposure on the creep behavior of solder joints. As expected, the creep rates evolved more dramatically when the aging temperature was increased. In addition, the effects of aging were shown to be significant even for aging temperature slightly above room temperature (e.g. T = 75 °C). The recorded data demonstrate that the creep behaviors of lead free and tin-lead solders experience a "cross-over point" where the lead free solders begin to creep at higher rates than standard 63Sn-37Pb solder for the same stress level. These cross-over points were observed to exist for all four of the SAC solder alloys, and for all of the aging temperatures except for room temperature. In addition, the lower silver content alloys (e.g. SAC105) were observed to be much more sensitive to aging (have greater changes in the creep rate for a given aging time) than the higher silver content alloys (e.g. SAC405). The times required before the cross-overs occurred were reduced when considering higher aging temperatures or SAC alloys with lower silver content. The cross-over points are definitely present for all of the SAC alloys when they are subjected to 100 C aging present in typical computer server environments.

In this paper, principal component regression models (PCR)have been investigated for reliability prediction and part selection of area package architectures under thermomechanical loads in conjunction with stepwise regression methods. Package architectures studied include, BGA packages mounted on CU-CORE and NO-CORE printed circuit assemblies in harsh environments. The models have been developed based on thermo-mechanical reliability data acquired on copper-core and no-core assemblies in four different thermal cycling conditions. Solder alloys examined include SnPb and SAC Alloys. The models presented in this paper provide decision guidance for smart selection and substitution to address component obsolescence by perturbing product designs for minimal risk insertion of new packaging technologies. It is conceivable for commercial off the shelf parts to become unavailable during the production-life of a product. Typical Commercial-of-the-Shelf parts are manufactured for a period of two to four years, and IC manufacturing processes are available for five to six years. It is envisioned that the reliability assessment models will enable turn-key evaluation of geometric architecture, material properties, and operating conditions effects on thermo-mechanical reliability. The presented approach enables the evaluation of qualitative parameter interaction effects, which are often ignored in closed-form modeling, have been incorporated in this work. Previously, the feasibility of using multiple linear regression models for reliability prediction has been demonstrated for flex-substrate BGA packages [1, 2], flip-chip packages [3, 4] and ceramic BGA packages [5] Convergence of statistical models with experimental data and finite element models has been demonstrated using a single factor design of experiment study. In addition, the power-law dependencies of individual variables have been correlated with established failure mechanics models. PCR approach uses the potentially important variables from stepwise regression. The statistics models are based on accelerated test data acquired as part of this paper, in harsh environments, while finite-element models are based on damage mechanics and material constitutive behavior. Sensitivity relations for geometry, materials, and architectures based on statistical models, and FEA models have been developed.

In this paper, the accuracy of optical measurements based on digital image correlation (DIC) with ultra high-speed imaging has been investigated for full-field measurement of transient strain in various board assemblies subjected to shock in various orientations. Previous researchers have measured the transient-dynamics of board assemblies with high-speed imaging in conjunction with high-speed image analysis for measurement of relative displacement, angle, velocity, and acceleration [1, 2], high-speed data-acquisition systems with discrete strain gages [3, 4, 5] and with accelerometers for measurement of transient acceleration [6, 7, 8]. Survivability envelope approach for leadfree area array architectures based on high-speed optical measurements and statistical pattern recognition has been presented. Degradation in confidence value gives a leading indication of component failure. Package architectures examined include-flex ball-grid arrays, tape-array ball-grid arrays, and metal lead-frame packages. Explicit finite-element models have been developed and correlated with experimental data. Models developed include, smeared property models, Timoshenko-beam models, and explicit sub-models.

Electrical contacts may be subjected to wear because of shock, vibration, and thermo-mechanical stresses resulting in fretting, increase in contact resistance, and eventual failure over the lifetime of the product. Previously, models have been constructed for various applications to simulate wear for dry unidirectional-sliding wear of a square-pin [1], unidirectional sliding of pin on disk [2], and wear mechanism maps for steel-on-steel contacts [3]. In this paper, a wear simulation model for fretting of reciprocating curved spring-loaded contacts has been proposed, based on instantaneous estimation of wear rate, which is time-integrated over a larger number of cycles, with continual update of the contact geometry during the simulation process. Arbitrary Lagrangian-Eulerian adaptive meshing has been used to simulate the wear phenomena. Model predictions of wear have been compared to experimental data plots, available from existing literature, to validate both, the 2D and 3D models. A large number of wear cycles have been simulated for common contact geometries, and the wear accrued computed in conjunction with the wear surface updates. The presented analysis is applicable to wide variety of contact systems found in consumer and defense applications including, RAM memory-card sockets, SD-card sockets, microprocessor, ZIF sockets, and fuzz button contacts.

Microelectronic encapsulants exhibit evolving properties that change significantly with environmental exposures such as isothermal aging and thermal cycling. Such aging effects are exacerbated at higher temperatures typical of thermal cycling qualification tests for harsh environment electronic packaging. In this work, the material behavior changes occurring in flip chip underfill encapsulants (silica filled epoxies) have been characterized for isothermal aging at four different temperatures that are below, near, and above the Tg of the material. A microscale tension-torsion testing machine has been used to evaluate the uniaxial tensile stress-strain and creep behaviors of the underfill material at several temperatures, after various durations of environmental exposure. A novel method has been developed to fabricate underfill uniaxial test specimens so that they accurately reflect the encapsulant layer present in flip chip assemblies. Using the developed specimen preparation procedure, samples were prepared and isothermal aged for up to 6 months at 80, 100, 125, and 150 °C. Stress-strain and creep tests were then performed on both non-aged and aged samples at several different temperatures (25, 50, 75, 100, 125, and 150 °C). The changes in mechanical behavior were recorded for the various aging temperatures and durations of isothermal exposure.

In this work, thermo-mechanical models for reliability prediction of BGA package interconnects mounted on integral copper-core (Cu-CORE) and no integral copper core (NO-CORE) printed circuit assemblies in harsh environments have been developed. The models have been developed based on thermo-mechanical reliability data acquired on Cu-CORE and NO-CORE assemblies in four different thermal cycling conditions. Solder alloys examined include SnPb and SAC alloys. Multivariate linear regression (MLR), and non-linear finite element models have been developed for prediction of geometry and material effects. The models presented in this paper provide decision guidance for smart selection of component packaging technologies and perturbing product designs for minimal risk insertion of new packaging technologies. In addition, qualitative parameter interaction effects, which are often ignored in closed-form modeling, have been incorporated in this work. The statistics models are based on accelerated test data acquired as part of this paper, in harsh environments, while finite-element models are based on damage mechanics and material constitutive behavior. Convergence of statistical, failure mechanics, and FEAbased model sensitivities with experimental data has been demonstrated. Validation of model predictions with accelerated test data is presented for various parameters including Die to Package Ratio, Ball Count, Ball Diameter, Package Pad Diameter, Surface Finish, Temperature Cycle Condition. The modeling methodology shows good correlation with experimental data.

Product miniaturization trends in microelectronics industry are driving the need for smaller, faster, more reliable, less expensive IC's. Area array packages have been increasingly targeted for use in harsh environments such as automotive underhood, military and space applications but system-level decision support and part-selection tools and techniques for thermo-mechanical reliability trade-offs while addressing part obsolescence in extreme environments are scarce. The models presented in this paper provide decision guidance for smart selection and substitution to address component obsolescence by perturbing product designs for minimal risk insertion of new packaging technologies. It is conceivable for commercial off the shelf parts to become unavailable during the production-life of a product. Typical Commercial-of-the-Shelf parts are manufactured for a period of two to four years, and IC manufacturing processes are available for five to six years. It is envisioned that the reliability assessment models will enable turn-key evaluation of geometric architecture, material properties, and operating conditions effects on thermo-mechanical reliability. The presented approach enables the evaluation of qualitative parameter interaction effects, which are often ignored in closed-form modeling, have been incorporated in this work. Previously, the feasibility of using multiple linear regression models for reliability prediction has been demonstrated for flex-substrate BGA packages [1, 2], flip-chip packages [3, 4] and ceramic BGA packages [5] In this paper, principal component regression models (PCR) have been investigated for reliability prediction and part selection of area package architectures under thermomechanical loads in conjunction with stepwise regression methods. Package architectures studied include, BGA packages mounted on CU-CORE and NO-CORE printed circuit assemblies in harsh environments. The models have been developed based on thermo-mechanical reliability data acquired on copper-core and no-core assemblies in four different thermal cycling conditions. Solder alloys examined include SnPb and SAC Alloys.

In the present paper auto-regressive and time-frequency based techniques have been investigated to predict and monitor the damage in implantable biological electronics such as pacemakers and defibrillators. The approach focuses is on the pre-failure space and methodologies for quantification of failure in electronic equipment subjected to shock and vibration loads using the dynamic response of the electronic equipment. Presented methodologies are applicable at the system-level for identification of impending failures to trigger repair or replacement significantly prior to failure. Leading indicators of shock-damage have been developed to correlate with the damage initiation and progression in under variety of stresses in electronic systems. The approach is based on monitoring critical solder interconnects, and sensing the change in testsignal characteristics prior to failure, in addition to monitoring the transient strain characteristics optically using digital image correlation and strain gages. Previously, SPR based on wavelet packet energy decomposition and the Mahalanobis distance approach have been studied by the authors for quantification of shock damage in electronic assemblies [Lall 2006a,b]. In this paper, Auto-regressive (AR), wavelet packet energy decomposition, and time-frequency (TFA) techniques have been investigated for system identification, condition monitoring, and fault detection and diagnosis in implantable biological electronic systems. One of the main advantages of the AR technique is that it is primarily a signal based technique. Reduced reliance on system analysis helps avoid errors which otherwise may render the process of fault detection and diagnosis quite complex and dependent on the skills of the analyst. Results of the present study show that the AR and TFA based health monitoring techniques are feasible for fault detection and damage-assessment in electronic units. Explicit finite element models have been developed and various kinds of failure modes have been simulated such as solder ball cracking, package falloff and solder ball failure.

In this paper, a design-envelope approach based on optical feature extraction techniques has been investigated for drop and shock survivability of electronic packaging has been presented for 6-leadfree solder alloy systems. Solder alloy systems investigated include, Sn1Ag0.5Cu, Sn3Ag0.5Cu, Sn0.3Ag0.7Cu, Sn0.3Ag0.7Cu0.1Bi, Sn0.2Ag0.7Cu0.1Bi-0.1Ni, 96.5Sn3.5Ag. Previously, digital image correlation (DIC) has been used for measurement of thermally-induced deformation and material-characterization. In this paper, DIC has been used for transient dynamic measurements, and optical feature extraction. Board assemblies have been subjected to shock-impact in various orientations including the JEDEC zero-degree drop and the vertical free-drop. Transient deformation has been measured using both digital image correlation and the strain gages. Measurements have been taken on both the package and the board side of the assemblies. Accuracy of high-speed optical measurement has been compared with that from discrete strain gages. Package architectures examined includeflex ball-grid arrays, tape-array ball-grid arrays, and metal lead-frame packages. Explicit finite-element models have been developed and correlated with experimental data. Models developed include, smeared property models, Timoshenko-beam models, and explicit sub-models. The potential of damage identification and tracking for various solder alloys has been investigated. Data on identification of damage proxies for competing failure mechanisms at the copper-to-solder, solder-to-printed circuit board, and copper-to-package substrate has been presented. Design envelopes have been developed based on statistical pattern recognition. The designenvelope is intended for component integration to ensure survivability in shock and vibration environments at a user-specified confidence level.

Designing harsh environment electronics continue to increase in difficulty to a rapid increase in feature content while electronics packaging technologies are often providing less reliability. In addition, restricted under-the-hood airflow and integrated (mechatronic) designs are significantly increasing operating temperatures toward their maximum operating capability. To provide a cost effective design, automotive electronics designers are pursuing circuit board assemblies directly attached to a metal plate. For cost purposes, this metal plate can also be used as part of the module housing to provide protection, as well as thermal efficiency. Unfortunately, the metal backing can often further reduce component reliability due to increases in substrate coefficient of thermal expansion. The paper investigates the impact of metal attachment on component reliability as it investigates the use of several board attachment options. These analyses are compared to finite element modeling to further understand the causes of earlier failure. In addition, the impact of additional component encapsulants and conformal coatings are investigated. Because all attachment materials must meet a certain thermal performance (both initial design and long-term performance) the thermal efficiencies of these design options are investigated, as well as the delamination due to product life. Finally, failure analyses are presented and ensure that failures match expected characteristics.

Conductive adhesives have been used for many applications as alternatives for tin lead solder and for many applications where solders are not desirable. Often passive devices are the most critical components related to long-term reliability for harsh environment electronics. This study investigates the impact of the termination of these components on long-term reliability of electrically conductive materials. The study considers six termination options on three different component body sizes. Two conductive adhesive materials are studied using a gold plated laminate circuit board. Contact resistance and component shear strength are measured under thermal cycling conditions from -40&176;C to +150°C. This test investigated these material conditions over the course of 2000 thermal cycles.

Stress sensing test chips are widely utilized to investigate integrated circuit die stresses arising from assembly and packaging operations. In order to utilize these test chips to measure stresses over a wide range of temperatures, one must have values of six piezoresistive coefficients for n- and p-type silicon over the temperature range of interest. However, the literature provides limited data over the desired range, and even the data at room temperature exhibit wide discrepancies in magnitude as well as sign. Thus, this work focuses on an extensive experimental study of the temperature dependence of the fundamental piezoresistive coefficients,

Piezoresistive stress sensors on the (111) surface of silicon offer the unique ability to measure the complete stress state at a point in the (111) material. However, four-point bending or wafer-level calibration methods can measure only four of the six piezoresistive coefficients for p- and n-type resistors required for application of these sensors. In this work, a hydrostatic test method has been developed in which a high-capacity pressure vessel is used to apply a triaxial load to a single die over the 25 C to +100 C temperature range. The slopes of the adjusted resistance change versus pressure plots yield pressure coefficients for p- and n-type silicon that provide the additional information necessary to fully determine the complete set of piezoresistive coefficients.

Stress sensing test chips fabricated on (001) and (111) silicon surfaces are capable of measuring die stresses arising from assembly and packaging operations. The chips incorporate resistor or transistor sensing elements that are used to measure stresses via the observation of the changes in their resistivity/mobility. The piezoresistive behavior of such sensors is characterized by three piezoresistive (pi) coefficients, which are electro-mechanical material constants. Stress sensor rosette elements are often designed with serpentine layouts in order to achieve acceptable resistance for measurement and to eliminate area lost to multiple contacts. The transverse sensitivity of such designs induces errors in the values of piezoresistive coefficients extracted from the sensor elements, and two cases are important. First, in order to determine values of the three fundamental piezoresistive coefficients of silicon, any transverse sensitivity dependencies must be corrected for, or eliminated from, the calibration elements. In contrast, however, application of the resistors as stress sensors requires the use of uncorrected values of the piezoresistive coefficients in the stress data reduction. This work focuses on a study of transverse sensitivity effects in resistors fabricated in silicon and corrected values of the piezoresistive coefficients are confirmed experimentally by comparing pairs of resistive stress sensors (transverse and transverse-free) on the (001) silicon wafer plane. The stress sensitivity for transverse-free cases was observed to be approximately 25-30% larger than that for transverse cases. The effects of crystallographic misalignment and lateral diffusion that occur during the fabrication process are also included in the discussion.

Surface roughness has many effects in contacting engineering surfaces and electrical connectors are no exception. In connectors, the roughness on the surfaces causes added electrical resistance (known as electrical contact resistance (ECR)). This work presents a new method for modeling ECR while considering the multiscale nature of surfaces in the contact mechanics and electrical resistivity theory. Based on Archard's "protuberance upon protuberance" theory, this method employs sinusoids stacked into layers to represent the rough surface. However, many models already exist ranging from statistical to other forms of multi-scale methods. There is considerable debate in the field of contact mechanics as to which method is the "best". Since all methods have various advantages and disadvantages, this work makes a comparison between several different models. In particular, results from the sinusoidal multiscale model are evaluated alongside results from statistical methods for both perfectly elastic and elastic-plastic deformation. This effort has shown qualitative similarities despite quantitative discrepancies.

A new multiscale model of thermal contact resistance (TCR) between real rough surfaces is presented, which builds on Archard's multiscale description of surface roughness. The objective of this work is to construct the new model and use it to evaluate the effects of scale dependent surface features and properties on TCR. The model includes many details affecting TCR and is also fairly easy to implement. Multiscale fractal based models often oversimplify the contact mechanics by assuming that the surfaces are self-affine, the contact area is simply a geometrical truncation of the surfaces, and the pressure is a constant value independent of geometry and material properties. Concern has grown over the effectiveness of frequently used statistical rough surface contact models due to the inadequacies in capturing the true multiscale nature of surfaces (i.e., surfaces have multiple scales of surface features). The model developed in this paper incorporates several variables, including scale dependent yield strength and scale dependent spreading resistance to develop a new model that can be used to evaluate TCR. The results suggest that scale dependent mechanical properties are more influential than scale dependent thermal properties. When compared to an existing TCR model, this very inclusive model shows the same qualitative trend. Results also show the significance of capturing multiscale roughness when addressing the thermal contact resistance problem.

Any engineering component possesses roughness on its surface when it is observed microscopically, including electrical connectors. Electrical connectors usually consist of a spring and a pin. In this study, the spring part is in the shape of a compliant curved beam whereas the pin one is of a flat form and these two parts are in contact during operation. This work presents a multi-physics (structural, electrical and thermal) finite element model of the bulk region of an electrical connector. The rough surfaces of the spring and pin parts are considered using a multi-scale sinusoidal rough surface (MSRS) contact model. The resulting coupled multi-physics connector model is used to analyze the performance of the connector while the applied current is incremented from 5 to 20 A. As expected, this produced a proportional rise in voltage drop and temperature across the bulk regions of the connector parts. The coupled multi-physics model together with the MSRS model should provide greater accuracy in the prediction of contact forces, electrical contact resistance (ECR) and thermal contact resistance (TCR). The present work also provides valuable information on stresses and strains distributions, current flow and temperature variations in the bulk regions of the electrical connector.

With the implementation of RoHS directives regarding Pb-free electronics, pure tin (Sn) films and board finishes offer potentially serious reliability issues due to Sn whisker formation. A key aspect of Sn whiskers is their material composition, which has been assumed pure crystalline Sn since 1951. Due to the submicron width (~ 0.25 µm) of high aspect ratio whiskers, it has been difficult for even state-of- the-art materials techniques to provide clear, unambiguous data on Sn whiskers and, in particular, the surfaces of Sn whiskers. In this study, high resolution Auger electron spectroscopy (AES) has been used to determine both the surface and bulk composition of high aspect ratio Sn whiskers. The whiskers were grown from intrinsically stressed thin films (~ 6000 Å) of Sn on brass, deposited using cylindrical magnetron sputtering techniques. Results show that the whiskers are 100% Sn at the whisker base, shaft, tip, and up to a substantial depth into the whisker bulk. No evidence of pull-up from the brass substrate or surface contaminants is observed in the whiskers. A remarkable aspect of the growth is that high aspect ratio whiskers ~ 10-100 µm in length containing no brass are grown from a ~ 0.6 µm thin film of Sn on brass.

Implementation of Pb-free electronics has resulted in use of pure Sn surface finishes which are known to pose reliability issues due to the spontaneous growth of Sn whiskers. In this study, atomic force microscopy (AFM) has been used to investigate the effect of surface roughness on Sn whisker growth. The varying (brass) substrate roughness conditions have been created by an unpolished, an electrochemically-polished, and a mechanically-polished surface. Subsequent Sn deposition using magnetron sputtering produced a thin (~ 6000 Å) Sn film on the brass. Results show that the smoother brass substrates produced significantly more Sn whiskers than rougher surfaces. Both the quantity of whiskers is greater and the average whisker length is longer as the brass smoothness increases. This is contrary to conventional wisdom which presumed that rougher surfaces offered more film stress and enhanced whisker growth.

The current work has studied the reliability of a solenoid valve (SV) used in automobile transmissions through a joint theoretical and experimental approach. Based on an extensive literature search, the most common failures seen in solenoid valves appear to be due to either overpowering and eventual overheating of the valves, or wearing out of the valve components. The goal of this work is to use accelerated tests to characterize SV failure and correlate the results to new comprehensive finite element models. A custom test apparatus has been designed and built to simultaneously monitor and actuate up to four SVs using the LabView™ programming language environment and a National Instruments™ Data Acquisition device. The test apparatus is capable of applying a controlled duty cycle, applied voltage and actuation frequency. The SVs are also placed in a thermal chamber so that the ambient temperature can be controlled precisely. The apparatus measures in real-time the temperature, current, and voltage of each SV. A multimeter is used to measure the electrical resistance across each SV. A series of tests have been conducted to produce repeated failures of the SVs. The failure of the SV appears to be caused by overheating and failure of the insulation used in the solenoid coil. The current tests are run at a 100°C ambient temperature, 16.8V of average peak voltage, 50% duty cycle, and 60 Hz actuation frequency. Upon failure, the solenoid electrical resistance drops to a significantly lower value due to shorting of the solenoid coil. This drop in resistance causes a measurable and noticeable increase in the average current. The insulation also melts and exits the SV. Hence, increasing ambient temperature and current is believed to cause a decrease in SV reliability. In addition, a comprehensive multiphysics theoretical model of the SV is constructed using the commercial finite element software ANSYS™. The multiphysics model includes the coupled effects of electromagnetic, thermodynamics and solid mechanics. The resulting finite element model of the SV provides useful information on the temperature distribution, mechanical and thermal deformations, and stresses. The model is also correlated to the experimental results and can be used as a predictive tool in future solenoid design. Finally, a proposed solution to improve SV reliability is to increase heat conduction and convection away from the SV, or by decreasing the ambient temperature or find an insulation material resistant to high temperatures.

The microstructure, mechanical response, and failure behavior of lead free solder joints in electronic assemblies are constantly evolving when exposed to isothermal aging and/or thermal cycling environments. In our prior work on aging effects (Ma, et al., ECTC 2006), we demonstrated that the observed material behavior variations of SAC405 and SAC305 lead free solders during room temperature aging (25 °C) were unexpectedly large and universally detrimental to reliability. Such effects for lead free solder materials are much more dramatic at the higher aging temperatures (e.g. 100-150 °C) typical of the harsh environments present in high performance computing and in automotive, aerospace, and defense applications. However, there has been little work in the literature, and the work that has been done has concentrated on the degradation of solder ball shear strength (e.g. Dage Shear Tester). Current finite element models for solder joint reliability during thermal cycling accelerated life testing are based on traditional solder constitutive and failure models that do not evolve with material aging. Thus, there will be significant errors in the calculations with the new lead free SAC alloys that illustrate dramatic aging phenomena. In the current work, we have explored the effects of elevated temperature isothermal aging on the mechanical behavior and reliability of lead free solders. The effects of aging on mechanical behavior have been examined by performing stress-strain and creep tests on SAC405 and SAC305 samples that were aged for various durations (0-6 months) at several elevated temperatures (80, 100, 125, and 150 °C). Analogous tests were performed with 63Sn-37Pb eutectic solder samples for comparison purposes. Variations of the temperature dependent mechanical properties (elastic modulus, yield stress, ultimate strength, creep compliance, etc.) were observed and modeled as a function of aging time and temperature. In this paper, we have concentrated our efforts on presenting the results for samples aged at 125 °C. In addition, the new elevated temperature aging data were correlated with our room temperature results from last year's investigation. The results obtained in this work have demonstrated the significant effects of elevated temperature exposure on solder joints. As expected, the mechanical properties evolved at a higher rate and experienced larger changes during elevated temperature aging (compared to room temperature aging). After approximately 200 hours of aging, the lead free solder joint material properties were observed to degrade at a nearly constant rate. We have developed a mathematical model to predict the variation of the properties with aging time and aging temperature. Our data for the evolution of the creep response of solders with elevated temperature aging show that the creep behavior of lead free and tin-lead solders experience a "cross-over point" where lead free solders begin to creep at higher rates than standard 63Sn-37Pb solder for the same stress level. Such an effect is not observed for solder joints aged at room temperature, where SAC alloys always creep at lower rates than Sn-Pb solder.

Researchers have developed many models to simulate the elasto-plastic contact of spheres. However, there does not appear to exist a closed-form analytical model for elasto-plastic three-dimensional sinusoidal contact. This work uses a finite element model (FEM) to characterize elasto-plastic sinusoidal contact. Although at initial contact the sphere and sinusoidal case are very similar and can both be described by the classic elastic Hertz contact case, once the contact is pressed past a certain range of deformation the two cases are very different. The model produces equations which can be used to approximately relate the area of contact to the contact pressure for elastoplastic sinusoidal contact. The equations are fit to the FEM results and existing elastic solutions of sinusoidal contact. An empirical expression for the average pressure which causes complete contact between elasto-plastic sinusoidal contacts is also provided.

Electronics may be subjected to shock, vibration, and drop-impact during shipping, handling and during normal usage. Measurement of transient dynamic deformation of the electronics assemblies during the shock and vibration can yield significant insights in understanding the occurrence of failure modes and the development of failure envelopes. Failure-modes include solder-joint failures, pad cratering, chip-cracking, copper trace fracture, and underfill fillet failures. Previous researchers have measured the transient-dynamics of board assemblies with high-speed imaging in conjunction with highspeed image analysis for measurement of relative displacement, angle, velocity, and acceleration [Lall 2006, Che 2006]. In addition, high-speed data-acquisition systems with discrete strain gages have been used for measurements of transient strain [Lall 2004, 2005, Liang 2005] and with accelerometers for measurement of transient acceleration [Dunford 2004, Goyal 2000, Seah 2005]. Development of accurate models requires better understanding of full-field strain deformation in board assemblies. In this paper, the use of digital image correlation (DIC) with ultra high-speed imaging has been used for full-field measurement of transient strain in various board assemblies subjected to shock in various orientations. Measurements have been taken on both the package and the board side of the assemblies. Accuracy of high-speed optical measurement has been compared with that from discrete strain gages. Package architectures examined include-flex ball-grid arrays, tape-array ball-grid arrays, and metal lead-frame packages. Explicit finite-element models have been developed and correlated with experimental data. Models developed include, smeared property models, Timoshenko-beam models, and explicit sub-models. The solder strains have been computed from the explicit finite element models for life prediction in shock.

Modeling transient-dynamics of electronic assemblies is a multi-scale problem requiring methodologies which allow the capture of layer dimensions of solder interconnects, pads, and chip-level interconnects simultaneously with assembly architecture and rigid-body motion. Computational effort needed to attain fine mesh to model chip interconnects while capturing the system-level dynamic behavior is challenging. Product-level testing depends heavily on experimental methods and is influenced by various factors such as the drop height, orientation of drop, and variations in product design. Modeling and simulation of IC packages are very efficient tools for design analysis and optimization. Previously, various modeling approaches have been pursued to predict the transient dynamics of electronics assemblies assuming symmetry of the electronic assemblies. In this paper, modeling approaches to predict the solder joint reliability in electronic assemblies subjected to high mechanical shocks have been developed. Two modeling approaches are proposed in this paper to enable life prediction under both symmetric and anti-symmetric transientdeformation. In the first approach, drop simulations of printed circuit board assemblies in various orientations have been carried out using beam-shell modeling methodologies without any assumptions of symmetry. This approach enables the prediction of full-field stress-strain distribution in the system over the entire drop event. Transient dynamic behavior of the board assemblies in free and JEDEC drop has been measured using high-speed strain and displacement measurements. Relative displacement and strain histories predicted by modeling have been correlated with experimental data. Failure data obtained by solder joint array tensile tests on ball grid array packages is used as a failure proxy to predict the failure in solder interconnections modeled using Timoshenko beam elements in the global model. In the second approach, cohesive elements have been incorporated in the local model at the solder joint-copper pad interface at both the PCB and package side. The constitutive response of the cohesive elements was based on a tractionseparation behavior derived from fracture mechanics. Damage initiation and evolution criteria are specified to ensure progressive degradation of the material stiffness leading to cohesive element failure. Use of cohesive zone modeling enabled the detection of dynamic crack initiation and propagation leading to IMC brittle failure in PCB assemblies subject to drop impact. Data on solder interconnect failure has been obtained under free-drop and JEDEC-drop test.

Electronics may be subjected to shock, vibration, and drop-impact during shipping, handling and during normal usage. Measurement of transient dynamic deformation of the electronics assemblies during the shock and vibration can yield significant insights in understanding the occurrence of failure modes and the development of failure envelopes. Failure-modes include solder-joint failures, pad cratering, chip-cracking, copper trace fracture, and underfill fillet failures. Previous researchers have measured the transientdynamics of board assemblies with high-speed imaging in conjunction with high-speed image analysis for measurement of relative displacement, angle, velocity, and acceleration [Lall 2006, Che 2006]. In addition, high-speed dataacquisition systems with discrete strain gages have been used for measurements of transient strain [Lall 2004, 2005, Liang 2005] and with accelerometers for measurement of transient acceleration [Dunford 2004, Goyal 2000, Seah 2005]. Development of accurate models requires better understanding of full-field strain deformation in board assemblies. In this paper, the use of digital image correlation (DIC) with ultra high-speed imaging has been used for full-field measurement of transient strain in various board assemblies subjected to shock in various orientations. Measurements have been taken on both the package and the board side of the assemblies. Accuracy of high-speed optical measurement has been compared with that from discrete strain gages. Package architectures examined include-flex ball-grid arrays, tapearray ball-grid arrays, and metal lead-frame packages. Explicit finite-element models have been developed and correlated with experimental data. Models developed include, smeared property models, Timoshenko-beam models, and explicit sub-models. The solder strains have been computed from the explicit finite element models for life prediction in shock.

Methodologies for prognostication and health monitoring can significantly impact electronic reliability for applications in which even minimal risk of failure may be unbearable. Presently, health monitoring approaches such as the built-in self-test (BIST) are based on reactive failure diagnostics and unable to determine residual-life or estimate residualreliability [Allen 2003, Drees 2004, Gao 2002, Rosenthal 1990]. Prognostics health-monitoring (PHM) approach presented in this paper is different from state-of-art diagnostics and resides in the pre-failure-space of the electronic-system, in which no macro-indicators such as cracks or delamination exist. Applications for the presented PHM framework include, consumer applications such as automotive safety systems including front and rear impact protection system, chassiscontrol systems, x-by-wire systems; and defense applications such as avionics systems, naval electronic warfare systems. The presented PHM methodologies enable the estimation of prior damage in deployed electronics by interrogation of the system state. The presented methodologies will trigger repair or replacement, significantly prior to failure. The approach involves the use of condition monitoring devices which can be interrogated for damage proxies at finite time-intervals. The system's residual life is computed based on residual-life computation algorithms. Previously, Lall, et. al. [2004, 2005, 2006] have developed several leading indicators of failure. In this paper a mathematical approach has been presented to calculate the prior damage in electronics subjected to cyclic and isothermal thermo-mechanical loads. Electronic components operating in a harsh environment may be subjected to both temperature variations in addition to thermal aging during use-life. Data has been collected for leading indicators of failure for 95.5Sn4Ag0.5Cu first-level interconnects under both single and sequential application of cyclic and isothermal thermomechanical loads. Methodology for the determination of prior damage history has been presented using non-linear least-squares method based interrogation techniques. The methodology presented used the Levenberg-Marquardt Algorithm. Test vehicle includes various area-array packaging architectures soldered on Immersion Ag finish, subjected to thermal cycling in the range of -40°C to 125°C and isothermal aging at 125°C.

The built-in stress test (BIST) is extensively used for diagnostics or identification of failure. The current version of BIST approach is focused on reactive failure detection and provides limited insight into reliability and residual life. A new approach has been developed to monitor product-level damage during shock and vibration. The approach focuses is on the pre-failure space and methodologies for quantification of failure in electronic equipment subjected to shock and vibration loads using the dynamic response of the electronic equipment. Presented methodologies are applicable at the system-level for identification of impending failures to trigger repair or replacement significantly prior to failure. Leading indicators of shock-damage have been developed to correlate with the damage initiation and progression in shock and drop of electronic assemblies. Three methodologies have been investigated for feature extraction and health monitoring including development of a new solder-interconnect built-in reliability test, FFT based statistical-pattern recognition, and time-frequency moments based statistical pattern recognition. The solder-joint built-inreliability- test has been developed for detecting highresistance and intermittent faults in operational, fully programmed field programmable gate arrays. Frequency band energy is computed using FFT and utilized as the classification feature to check for damage and failure in the assembly. In addition, the Time Frequency Analysis has been used to study of the energy densities of the signal in both time and frequency domain, and provide information about the time-evolution of frequency content of transient-strain signal. Closed-form models have been developed for the eigenfrequencies and mode-shapes of electronic assemblies with various boundary conditions and component placement configurations. Model predictions have been validated with experimental data from modal analysis. Pristine configurations have been perturbed to quantify the degradation in confidence values with progression of damage. Sensitivity of leading indicators of shock-damage to subtle changes in boundary conditions, effective flexural rigidity, and transient strain response have been quantified. Explicit finite element models have been developed and various kinds of failure modes have been simulated such as solder ball cracking, package falloff and solder ball failure. This allows the physical quantification of solder ball crack damage in the form of confidence values and provides a damage index that can be utilized for the health monitoring of solder interconnects in an electronic assembly.

Thermal cycling accelerated life testing is an established technique for thermo-mechanical evaluation and qualification of electronic packages. Finite element life predictions for thermal cycling configurations are challenging due to several reasons including the complicated temperature/time dependent constitutive relations and failure criteria needed for solders, encapsulants and their interfaces; aging/evolving material behavior for the packaging materials (e.g. solders); difficulties in modeling plating finishes; the complicated geometries of typical electronic assemblies; etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling are difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, little is known about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling. In this work, we have used test chips containing piezoresistive stress sensors to characterize the in-situ die surface stress during long-term thermal cycling of electronic packaging assemblies. Using (111) silicon test chips, the complete three-dimensional stress state (all 6 stress components) was measured at each rosette site by monitoring the resistance changes occurring in the sensors. The packaging configuration studied in this work was flip chip on laminate where 5 x 5 mm perimeter bumped die were assembled on FR-406 substrates. Three different thermal cycling temperature profiles were considered. In each case, the die stresses were initially measured at room temperature after packaging. The packaged assemblies were then subjected to thermal cycling and measurements were made either incrementally or continuously during the environmental exposures. In the incremental measurements, the packages were removed from the chamber after various durations of thermal cycling (e.g. 250, 500, 750, 1000 cycles, etc.), and the sensor resistances were measured at room temperature. In the continuous measurements, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously during the thermal cycling exposure. From the resistance data, the stresses at each site were calculated and plotted versus time. The experimental observations show cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage.

The built-in stress test (BIST) is extensively used for diagnostics or identification of failure. The current version of BIST approach is focused on reactive failure detection and provides limited insight into reliability and residual life. A new approach has been developed to monitor product-level damage during shock and vibration. The approach focuses on the prefailure space and methodologies for quantification of failure in electronic equipment subjected to shock and vibration loads using the dynamic response of the electronic equipment. Presented methodologies are applicable at the system-level for identification of impending failures to trigger repair or replacement significantly prior to failure. Leading indicators of shock-damage have been developed to correlate with the damage initiation and progression in shock and drop of electronic assemblies. Three methodologies have been investigated for feature extraction and health monitoring including development of a new solder-interconnect built-in reliability test, FFT based statistical-pattern recognition, and time-frequency moments based statistical pattern recognition. The solder-joint built-inreliability- test has been developed for detecting high-resistance and intermittent faults in operational, fully programmed field programmable gate arrays. Frequency band energy is computed using FFT and utilized as the classification feature to check for damage and failure in the assembly. In addition, the Time Frequency Analysis has been used to study of the energy densities of the signal in both time and frequency domain, and provide information about the time-evolution of frequency content of transient-strain signal. Closed-form models have been developed for the eigen-frequencies and mode-shapes of electronic assemblies with various boundary conditions and component placement configurations. Model predictions have been validated with experimental data from modal analysis. Pristine configurations have been perturbed to quantify the degradation in confidence values with progression of damage. Sensitivity of leading indicators of shock-damage to subtle changes in boundary conditions, effective flexural rigidity, and transient strain response have been quantified. Explicit finite element models have been developed and various kinds of failure modes have been simulated such as solder ball cracking, package falloff and solder ball failure. This allows the physical quantification of solder ball crack damage in the form of confidence values and provides a damage index that can be utilized for the health monitoring of solder interconnects in an electronic assembly.

Methodologies for prognostication and health monitoring can significantly impact electronic reliability for applications in which even minimal risk of failure may be unbearable. Presently, health monitoring approaches such as the built-in self-test (BIST) are based on reactive failure diagnostics and unable to determine residual-life or estimate residual-reliability [Allen 2003, Drees 2004, Gao 2002, Rosenthal 1990]. Prognostics health-monitoring (PHM) approach presented in this paper is different from state-of-art diagnostics and resides in the prefailure- space of the electronic-system, in which no macroindicators such as cracks or delamination exist. Applications for the presented PHM framework include, consumer applications such as automotive safety systems including front and rear impact protection system, chassis control systems, x-by-wire systems; and defense applications such as avionics systems, naval electronic warfare systems. The presented PHM methodologies enable the estimation of prior damage in deployed electronics by interrogation of the system state. The presented methodologies will trigger repair or replacement, significantly prior to failure. The approach involves the use of condition monitoring devices which can be interrogated for damage proxies at finite time-intervals. The system's residual life is computed based on residual-life computation algorithms. Previously, Lall, et. al. [2004, 2005, 2006] have developed several leading indicators of failure. In this paper a mathematical approach has been presented to calculate the prior damage in electronics subjected to cyclic and isothermal thermomechanical loads. Electronic components operating in a harsh environment may be subjected to both temperature variations in addition to thermal aging during use-life. Data has been collected for leading indicators of failure for 95.5Sn4Ag0.5Cu first-level interconnects under both single and sequential application of cyclic and isothermal thermo-mechanical loads. Methodology for the determination of prior damage history has been presented using non-linear least-squares method based interrogation techniques. The methodology presented used the Levenberg-Marquardt Algorithm. Test vehicle includes various area-array packaging architectures soldered on Immersion Ag finish, subjected to thermal cycling in the range of -40°C to 125°C and isothermal aging at 125°C.

Thermal cycling accelerated life testing is an established technique for thermo-mechanical evaluation and qualification of electronic packages. Finite element life predictions for thermal cycling configurations are challenging due to several reasons including the complicated temperature/time dependent constitutive relations and failure criteria needed for solders, encapsulants and their interfaces; aging/evolving material behavior for the packaging materials (e.g. solders); difficulties in modeling plating finishes; the complicated geometries of typical electronic assemblies; etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling are difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, little is known about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling. In this work, we have used test chips containing piezoresistive stress sensors to characterize the in-situ die surface stress during long-term thermal cycling of electronic packaging assemblies. Using (111) silicon test chips, the complete three-dimensional stress state (all 6 stress components) was measured at each rosette site by monitoring the resistance changes occurring in the sensors. The packaging configuration studied in this work was flip chip on laminate where 5 x 5 mm perimeter bumped die were assembled on FR-406 substrates. Two different thermal cycling temperature profiles from -40 to 125 °C were considered. In each case, the die stresses were initially measured at room temperature after packaging. The packaged assemblies were then subjected to thermal cycling and measurements were made either incrementally or continuously during the environmental exposures. In the incremental measurements, the packages were removed from the chamber after various durations of thermal cycling (e.g. 250, 500, 750, 1000 cycles, etc.), and the sensor resistances were measured at room temperature. In the continuous measurements, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously during the thermal cycling exposure. From the resistance data, the stresses at each site were calculated and plotted versus time. The experimental observations show cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage.

In this work, thermo-mechanical models for reliability prediction of BGA package interconnects mounted on integral copper-core (CU-CORE) and no integral copper core (NO-CORE) printed circuit assemblies in harsh environments have been developed. The models have been developed based on thermo-mechanical reliability data acquired on CU-CORE and NO-CORE assemblies in four different thermal cycling conditions. Solder alloys examined include SnPb and SAC alloys. The models presented in this paper provide decision guidance for smart selection of component packaging technologies and perturbing product designs for minimal risk insertion of new packaging technologies. In addition, qualitative parameter interaction effects, which are often ignored in closed-form modeling, have been incorporated in this work. Multivariate linear regression (MLR), and non-linear finite element models have been developed for prediction of geometry and material effects. MLR approach uses the potentially important variables from stepwise regression. The statistics models are based on accelerated test data acquired as part of this paper, in harsh environments, while finite-element models are based on damage mechanics and material constitutive behavior. Sensitivity relations for geometry, materials, and architectures based on statistical models, and FEA models have been developed. Convergence of statistical, failure mechanics, and FEAbased model sensitivities with experimental data has been demonstrated. Validation of model predictions with accelerated test data is presented.

This work attempts to quantify the effect of repeated initial connector insertions and roughness on electrical contact resistance. Experimental measurements show that the electrical contact resistance increases measurably with repeated insertions. They also show that with repeated insertions the connector spring is plastically deformed, thus causing the force closing the contact across the surfaces to decrease. A multi-scale rough surface contact model was used to estimate the actual electrical contact resistance (ECR) versus applied force curve of the connector. As expected, the multiscale ECR model predicts that the ECR will decrease with applied force. Since the contact force decreases with each insertion of the connector due to plastic deformation, the model will predict that the ECR will also increase with each insertion. When the added resistance from a measurable layer of tin oxide is included, the multiscale ECR model shows fairly good agreement with the experimental measurements.

This study models the electrical contact resistance (ECR) between two surfaces separated by an anisotropic conductive film. The film is made up of an epoxy with conductive spherical particles(metallic) dispersed within. In practical situations the particles are often heavily loaded and will undergo severe plastic deformation and may essentially be flattened out. In between the particles and the surfaces there may also be an ultra-thin insulating film (consisting of epoxy) which causes considerable electrical resistance between the surfaces. In the past this effect has been neglected and the predicted ECR was much lower than that measured experimentally. This added resistance is considered using electron tunneling theory. The severe plastic deformation of the spherical particles is modeled using a new expanded elasto-plastic spherical contact model. This work also investigates the effect of compression of the separating epoxy film on the electrical contact resistance. The model finds that the high experimental ECR measurements can be accounted for by including the existence of a thin insulating film through the electron tunneling model.

Multicontact MEMS relays laterally actuated using electrostatic comb-drive actuators are reported. The relay consists of a movable main beam anchored to the substrate using two identical folded suspension springs. Multicontact RF ports consist of five movable fingers connected to the movable main beam and six fixed fingers anchored to the substrate. Comb-drive actuators located at the top and bottom ends of the main beam enable bidirectional actuation of the RF contacts. The MEMS relays were fabricated using the MetalMUMPs process, which uses 20- µm-thick electroplated nickel as the structural layer. A 3- µm-thick gold layer was electroplated at the electrical contact surfaces. An example MEMS relay with planar contacts of area 80 µm x20 µm and a spacing of 10 µm between the movable and fixed contacting surfaces is discussed. The overall size of the relay is approximately 3 mm x 3 mm. "Resistance versus applied voltage" characteristics of the MEMS relay have been measured for applied DC bias voltages in the range of 172 V to 220 V. A multiscale rough surface contact model was used to estimate the actual electrical contact resistance versus applied force curve of these devices. The multiscale model showed good qualitative agreement with the experimental measurements but requires more refinement to achieve good quantitative agreement.

Thermal cycling accelerated life testing is an established technique for thermo-mechanical evaluation and qualification of electronic packages. Finite element life predictions for thermal cycling configurations are challenging due to several reasons including the complicated temperature/time dependent constitutive relations and failure criteria needed for solders, encapsulants and their interfaces; aging/evolving material behavior for the packaging materials (e.g. solders); difficulties in modeling plating finishes; the complicated geometries of typical electronic assemblies; etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling are difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, little is known about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling. In this work, we have used test chips containing piezoresistive stress sensors to characterize the in-situ die surface stress during long-term thermal cycling of electronic packaging assemblies. Using (111) silicon test chips, the complete threedimensional stress state (all 6 stress components) was measured at each rosette site by monitoring the resistance changes occurring in the sensors. The packaging configuration studied in this work was flip chip on laminate where 5 x 5 mm perimeter bumped die were assembled on FR-406 substrates. Three different thermal cycling temperature profiles were considered. In each case, the die stresses were initially measured at room temperature after packaging. The packaged assemblies were then subjected to thermal cycling and measurements were made either incrementally or continuously during the environmental exposures. In the incremental measurements, the packages were removed from the chamber after various durations of thermal cycling (e.g. 250, 500, 750, 1000 cycles, etc.), and the sensor resistances were measured at room temperature. In the continuous measurements, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously during the thermal cycling exposure. From the resistance data, the stresses at each site were calculated and plotted versus time. The experimental observations show cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage.

The thermal performance of Ball Grid Array packages depends upon many parameters including die size, use of thermal balls, number of perimeter balls, use of underfill, and printed circuit board heat spreader and thermal via design. Thermal cycling can affect the integrity of thermal paths in and around the BGA as a result of the cracking of solder balls and delamination of the package, including at underfill interfaces. In this study, the impact of thermal cycling on the thermal performance of BGA's was investigated and quantified. A number of test boards which included a range of the parameters cited above were experimentally examined. A baseline thermal resistance was measured for each case, which was verified with numerical thermal modeling. The boards were then subjected to thermal cycling from -40°C to 125°C. Every 250 cycles the thermal performance was measured. Packages expected to be least reliable (with large die and no underfill), showed an increase in thermal resistance after 750 thermal cycles. Further increases in thermal resistance were observed with continuous thermal cycling until solder joint failure occurred at 1250 cycles, preventing additional measurements. Finite element analysis identified critical thermal and perimeter solder balls as the most likely sites for cracking. Boards were cross-sectioned and examined for solder joint cracks and delamination to identify the cause for the observed increases in thermal resistance. Cracking was found in the critical thermal and perimeter solder balls.

The microstructure, mechanical response, and failure behavior of lead free solder joints in electronic assemblies are constantly evolving when exposed to isothermal aging and/or thermal cycling environments. In our prior work on aging effects (Ma, et al., ECTC 2006), we demonstrated that the observed material behavior variations of SAC405 and SAC305 lead free solders during room temperature aging (25 °C) were unexpectedly large and universally detrimental to reliability. Such effects for lead free solder materials are much more dramatic at the higher aging temperatures (e.g. 100-150 °C) typical of the harsh environments present in high performance computing and in automotive, aerospace, and defense applications. However, there has been little work in the literature, and the work that has been done has concentrated on the degradation of solder ball shear strength (e.g. Dage Shear Tester). Current finite element models for solder joint reliability during thermal cycling accelerated life testing are based on traditional solder constitutive and failure models that do not evolve with material aging. Thus, there will be significant errors in the calculations with the new lead free SAC alloys that illustrate dramatic aging phenomena. In the current work, we have explored the effects of elevated temperature isothermal aging on the mechanical behavior and reliability of lead free solders. The effects of aging on mechanical behavior have been examined by performing stress-strain and creep tests on SAC405 and SAC305 samples that were aged for various durations (0-6 months) at several elevated temperatures (80, 100, 125, and 150 °C). Analogous tests were performed with 63Sn-37Pb eutectic solder samples for comparison purposes. Variations of the temperature dependent mechanical properties (elastic modulus, yield stress, ultimate strength, creep compliance, etc.) were observed and modeled as a function of aging time and temperature. In this paper, we have concentrated our efforts on presenting the results for samples aged at 125 °C. In addition, the new elevated temperature aging data were correlated with our room temperature results from last year's investigation. The results obtained in this work have demonstrated the significant effects of elevated temperature exposure on solder joints. As expected, the mechanical properties evolved at a higher rate and experienced larger changes during elevated temperature aging (compared to room temperature aging). After approximately 200 hours of aging, the lead free solder joint material properties were observed to degrade at a nearly constant rate. We have developed a mathematical model to predict the variation of the properties with aging time and aging temperature. Our data for the evolution of the creep response of solders with elevated temperature aging show that the creep behavior of lead free and tin-lead solders experience a "crossover point" where lead free solders begin to creep at higher rates than standard 63Sn-37Pb solder for the same stress level. Such an effect is not observed for solder joints aged at room temperature, where SAC alloys always creep at lower rates than Sn-Pb solder.

driving the need for smaller, faster, and more reliable less expensive IC's. Area array packages have been increasingly targeted for use in harsh environments such as automotive underhood, military and space applications but system-level decision support and part-selection tools and techniques for thermo-mechanical reliability trade-offs while addressing part obsolescence in extreme environments are scarce. Typical Commercial-of-the-Shelf parts are manufactured for a period of two to four years, and IC manufacturing processes are available for five to six years. Leading-edge IC-manufacturing processes change every 12 to 18 months. The IC manufacturers upgrade their manufacturing lines to support these new technologies [Stogdill 1999, Solomon 2000, Howard 2002, Anghel 2003]. It is conceivable for parts to become unavailable during the production-life of a product. Reliability assessment models to aid part selection and substitution of obsolete components based on turn-key evaluation of geometric architecture, material properties, and operating conditions effects on thermo-mechanical reliability may be useful in performing reliability tradeoffs. In this paper, two statistical methods have been investigated for development of reliability prediction and part selection models including, Multivariate Regression and Principal Component Models in conjunction with Stepwise Regression Methods. Package architectures studied include, Flip chip, FlexBGA, CBGA and CCGA area-array packages. The models have been developed based on perturbation of accelerated test thermomechanical failure data. The potential of the models to target the qualitative parameters beyond those addressed in first-order closed form models has been demonstrated. Convergence of statistical models with experimental data has been demonstrated using a single factor design of experiment study. In addition, the power-law dependencies of individual variables have been correlated with established failure mechanics models. Parameter interaction effects, which are often ignored in closed form modeling, have been incorporated in this work.

The built-in stress test (BIST) is extensively used for diagnostics or identification of failure. The current version of BIST approach is focused on reactive failure detection and provides limited insight into reliability and residual life. A new approach has been developed to monitor product-level damage during shock and vibration. The approach focuses on the prefailure space and methodologies for quantification of failure in electronic equipment subjected to shock and vibration loads using the dynamic response of the electronic equipment. Presented methodologies are applicable at the system-level for identification of impending failures to trigger repair or replacement significantly prior to failure. Leading indicators of shock-damage have been developed to correlate with the damage initiation and progression in shock and drop of electronic assemblies. Three methodologies have been investigated for feature extraction and health monitoring including development of a new solder-interconnect built-in reliability test, FFT based statistical-pattern recognition, and time-frequency moments based statistical pattern recognition. The solder-joint built-inreliability- test has been developed for detecting high-resistance and intermittent faults in operational, fully programmed field programmable gate arrays. Frequency band energy is computed using FFT and utilized as the classification feature to check for damage and failure in the assembly. In addition, the Time Frequency Analysis has been used to study of the energy densities of the signal in both time and frequency domain, and provide information about the time-evolution of frequency content of transient-strain signal. Closed-form models have been developed for the eigen-frequencies and mode-shapes of electronic assemblies with various boundary conditions and component placement configurations. Model predictions have been validated with experimental data from modal analysis. Pristine configurations have been perturbed to quantify the degradation in confidence values with progression of damage. Sensitivity of leading indicators of shock-damage to subtle changes in boundary conditions, effective flexural rigidity, and transient strain response have been quantified. Explicit finite element models have been developed and various kinds of failure modes have been simulated such as solder ball cracking, package falloff and solder ball failure. This allows the physical quantification of solder ball crack damage in the form of confidence values and provides a damage index that can be utilized for the health monitoring of solder interconnects in an electronic assembly.

Portable electronics is subjected to extreme accelerations in shock and drop impact. Product development cycle times and the cost constraints often restrict the number of design variations tested for drop robustness prior to identification of the final configuration. Simulation models capable of predicting transient dynamics can provide valuable insight into the design reliability under shock environments. In this study, explicit finite element models have been used to study the transient dynamics of printed circuit boards during drop from 6 ft. Methodologies for modeling components using smeared-property formulations have been investigated. Reduced integration element formulations examined include shell and solid elements. Model predictions have been validated with experimental data. Results show that models with smeared properties can predict transient-dynamic response of board assemblies in drop impact fairly accurately. High-speed data acquisition system has been used to capture in situ strain, continuity, and acceleration data in excess of 10e6 samples/s. Ultra-high-speed video at 40,000 fps has been used to capture the deformation kinematics. Component types examined include plastic ball-grid arrays, tape-array ball-grid array, quad-flat-no-lead package, and conduction-cooled ball-grid array. Model predictions have been correlated with experimental data. Impact of experimental error sources on model correlation with experiments has been also investigated.

Methodologies for prognostication and health monitoring can significantly impact electronic reliability for applications in which even minimal risk of failure may be unbearable. Presently, health monitoring approaches such as the built-in self-test (BIST) are based on reactive failure diagnostics and unable to determine residual-life or estimate residual-reliability [Allen 2003, Drees 2004, Gao 2002, Rosenthal 1990]. Prognostics health-monitoring (PHM) approach presented in this paper is different from state-of-art diagnostics and resides in the prefailure- space of the electronic-system, in which no macroindicators such as cracks or delamination exist. Applications for the presented PHM framework include, consumer applications such as automotive safety systems including front and rear impact protection system, chassiscontrol systems, x-by-wire systems; and defense applications such as avionics systems, naval electronic warfare systems. The presented PHM methodologies enable the estimation of prior damage in deployed electronics by interrogation of the system state. The presented methodologies will trigger repair or replacement, significantly prior to failure. The approach involves the use of condition monitoring devices which can be interrogated for damage proxies at finite time-intervals. The system's residual life is computed based on residual-life computation algorithms. Previously, Lall, et. al. [2004, 2005, 2006] have developed several leading indicators of failure. In this paper a mathematical approach has been presented to calculate the prior damage in electronics subjected to cyclic and isothermal thermomechanical loads. Electronic components operating in a harsh environment may be subjected to both temperature variations in addition to thermal aging during use-life. Data has been collected for leading indicators of failure for 95.5Sn4Ag0.5Cu first-level interconnects under both single and sequential application of cyclic and isothermal thermo-mechanical loads. Methodology for the determination of prior damage history has been presented using non-linear least-squares method based interrogation techniques. The methodology presented used the Levenberg-Marquardt Algorithm. Test vehicle includes various area-array packaging architectures soldered on Immersion Ag finish, subjected to thermal cycling in the range of -40°C to 125°C and isothermal aging at 125°C.

Connector fretting propensity is generally evaluated through an exhaustive series of experimental tests, making the connector design and validation process time consuming and costly. Thus, a method using modeling and simulation techniques to predict the influence of various design factors on vibration-induced fretting propensity in electrical connectors method would very beneficial to those responsible for connector design and application. One approach is to use detailed finite element models for the connector system to relate the actual dynamics of the contact interface to the threshold vibration levels required for the onset of fretting and the relative motion transfer function. The present study describes one such model for a single tin-plated blade / receptacle connector pair. Concurrent simulation and experimental studies were performed to evaluate the threshold vibration levels as a function of excitation frequency, interface friction coefficient, and normal force. Good correlation between the experimentally observed results and those predicted by the models was obtained. Some insights and observations with regard to the effectiveness of such a modeling approach are also presented.

Damage pre-cursors based health management and prognostication methodology has been presented for electronic systems in harsh environments. The framework has been developed based on a development of correlation between damage pre-cursors and underlying degradation mechanisms in lead-free packaging architectures. The proposed methodology eliminates the need for knowledge of prior stress histories and enables interrogation of system state using the identified damage pre-cursors. Test vehicle includes various area-array packaging architectures subjected to single thermo-mechanical stresses including thermal cycling in the range of -40 C to 125 C and isothermal aging at 125 C. Experimental data on damage pre-cursors has been presented for packaging architectures encompassing flex-substrate ball grid arrays, chip-array ball grid arrays, and plastic ball grid arrays. Examples of damage proxies include phase-growth parameter, intermetallic thickness and interfacial stress variations. Damage proxies have been correlated with residual life. The damage proxies have also been correlated with computational finite-element model predictions. Plastic and creep strain energy densities have been correlated to the identified damage proxies.

Modeling approaches for first-level solder interconnects in shock and drop of electronics assemblies have been developed without any assumptions of geometric symmetry or loading symmetry. The problem involves multiple scales from macroscale transient-dynamics of electronic assembly to microstructural damage history of interconnects. Previous modeling approaches include, solid-to-solid submodeling using a half test PCB board, shell-to-solid submodeling technique using a quarter-symmetry model. Inclusion of model symmetry in state-of-the-art models saves computational time but targets primarily symmetric mode shapes. The modeling approach proposed in this paper enables prediction of both symmetric and antisymmetric modes, which may dominate an actual drop-event. Approaches investigated include smeared property models, Timoshenko-beam element models, explicit submodels, and continuum-shell models. Transient dynamic behavior of the board assemblies in free and JEDEC drop has been measured using high-speed strain and displacement measurements. Model predictions have been correlated with experimental data.

Damage pre-cursors based health management and prognostication methodology has been presented for electronic systems in harsh environments. The framework has been developed based on a development of correlation between damage pre-cursors and underlying degradation mechanisms in lead-free packaging architectures. The proposed methodology eliminates the need for knowledge of prior stress histories and enables interrogation of system state using the identified damage pre-cursors. Test vehicle includes various area-array packaging architectures subjected to single thermo-mechanical stresses including thermal cycling in the range of -40°C to 125°C and isothermal aging at 125°C. Experimental data on damage pre-cursors has been presented for packaging architectures encompassing flex-substrate ball grid arrays, chip-array ball grid arrays, and plastic ball grid arrays. Examples of damage proxies include, phase-growth parameter, intermetallic thickness and interfacial stress variations. Damage proxies have correlated with residual life. The damage proxies have also been correlated with computational finite-element model predictions. Plastic and creep strain energy densities have been correlated to the identified damage proxies.

There is a fundamental need for development of predictive techniques for electronic failure mechanisms in shock and drop-impact. Presently, one of the primary methodologies for assessment of shock and vibration survivability of electronic packaging is the JEDEC drop test method, JESD22-B111 which tests board-level reliability of packaging. However, packages in electronic products may be subjected to a widearray of boundary conditions beyond those targeted in the test method. Development of damage-equivalency methodologies will be invaluable in correlating standard test conditions to widely varying design-use conditions. In this paper, the development of a solder-joint stress based relative damage index has been investigated to establish a method for damage equivalency. Modal Analysis, Wavelet Decomposition, and Explicit Finite Element analysis has been used to assess reliability performance of the electronic boards. Deformation kinematics have been measured with the help of ultra high-speed data acquisition and video systems. Experimental data has been correlated to the finite element models. Failure predictions along with their modes and mechanisms have been discussed. Damage proxies for failure mechanisms in first-level interconnects have been developed. The approach is scalable to a wide variety of electronic applications. Component types examined include, plastic ball-grid arrays, flex ball-grid arrays for various pitch sizes between 0.5 mm to 1mm in both 63Sn37Pb and 95.5Sn4.0Ag0.5Cu solder alloy compositions. Dynamic measurements like acceleration, strain and resistance are measured and analyzed using highspeed data acquisition system capable of capturing in-situ strain, continuity and acceleration data in excess of 5 million samples per second. Ultra high-speed video upto 50,000 fps has been used to capture the deformation kinematics. Experimental results are correlated with finite element models which include reduced integration element formulations.

In this paper, the modeling approaches for first-level solder interconnects in shock and drop of electronics assemblies have been developed without any assumptions of geometric-symmetry or loading symmetry. The problem involves multiple scales from macro-scale transient-dynamics of electronic assembly to micro-structural damage history of interconnects. Previous modeling approaches include, solid-to-solid submodeling [Zhu, et. al. 2001] using a half test PCB board, shell-to-solid sub-modeling technique using a quartersymmetry model [Ren, et. al. 2003, 2004]. Inclusion of model symmetry in state-of-art models saves computational time, but targets primarily symmetric mode shapes. The modeling approach proposed in this paper enables prediction of both symmetric and anti-symmetric modes, which may dominate an actual drop-event. Approaches investigated include, smeared property models, Timoshenko-beam element models, explicit sub-models, and continuum-shell models. Transient dynamic behavior of the board assemblies in free and JEDEC-drop has been measured using high-speed strain and displacement measurements. Model predictions have been correlated with experimental data.

Electronic products may be subjected shock and vibration during shipping, normal usage and accidental drop. Highstrain rate transient bending produced by such loads may result in failure of fine-pitch electronics. Current experimental techniques rely on electrical resistance for determination of failure. Significant advantage can be gained by prior knowledge of impending failure for applications where the consequences of system-failure may be catastrophic. This research effort focuses on an alternate approach to damage-quantification in electronic assemblies subjected to shock and vibration, without testing for electrical continuity. The proposed approach can be extended to monitor product-level damage. In this paper, statistical pattern recognition and leading indicators of shock-damage have been used to study the damage initiation and progression in shock and drop of electronic assemblies. Statistical pattern recognition is currently being employed in a variety of engineering and scientific disciplines such as biology, psychology, medicine, marketing, artificial intelligence, computer vision and remote sensing [Jain, et. al. 2000]. The application quantification of shock damage in electronic assemblies is new. Previously, free vibration of rectangular plates has been studied by various researchers [Leissa 1969, Young 1950, Gorman 1982, Gurgoze 1984, Wu 2003] for development of analytical closed-form models. In this paper, closed-form models have been developed for the eigen-frequencies and mode-shapes of electronic assemblies with various boundary conditions and component placement configurations. Model predictions have been validated with experimental data from modal analysis. Pristine configurations have been perturbed to quantify the degradation in confidence values with progression of damage. Sensitivity of leading indicators of shock-damage to subtle changes in boundary conditions, effective flexural rigidity, and transient strain response have been quantified. A damage index for Experimental Damage Monitoring has been developed using the failure indicators. The above damage monitoring approach is not based on electrical continuity and hence can be applied to any electronic assembly structure irrespective of the interconnections. The damage index developed provides parametric damage progression data, thus removing the limitation of current failure testing, where the damage progression can not be monitored. Hence the proposed method does not require the assumption that the failure occurs abruptly after some number of drops and can be extended to product level drops.

The current state of the art in managing system reliability is geared toward the development of predictive models for unaged pristine materials. The current state of art allows the prediction of time-to-failure for a pristine material under known loading conditions based on relationships such as the Paris' power law [16], [17], the Coffin-Manson relationship [2], [13], [23], [24], and the S-N diagram. There is a need for methods and processes which will allow interrogation of material state in complex systems and subsystems to determine the remaining useful life prior to repair or replacement. This capability of determination of material or system state is called prognosis. In this paper, a methodology for prognostication of electronics has been demonstrated with data of leading indicators of failure for accurate assessment of product damage prior to appearance of any macro indicators of damage. Proxies for leading indicators of failure have been identified. Examples of proxies include microstructural evolution characterized by average phase size and correlated to time and equivalent creep strain rate, and stresses at interface of silicon structures. Structures examined include an electronics package and microelectromechanical systems package and interconnections. The test vehicle includes packages that have been mounted on a metal-backed printed circuit board typical of electronics deployed in harsh environments. In application environment, the metal backing provides thermal dissipation, mechanical stability, and interconnections reliability. Since an aged material knows its state, the research presented in this paper focuses on enhancing the understanding of material damage to facilitate proper interrogation of material state. A mathematical relationship has been developed between phase growth rate and time-to-1-percent failure to enable the computation of damage manifested and a forward estimate of residual life.

Increased use of sensors and controls in automotive applications has resulted in significant emphasis on the deployment of electronics directly mounted on the engine and transmission. Increased shock, vibration, and higher temperatures necessitate the fundamental understanding of damage mechanisms which will be active in these environments. Electronics typical of office benign environments use FR-4 printed circuit boards (PCBs). Automotive applications typically use high glass-transition temperature laminates such as FR4-06 glass/epoxy laminate material ( g = 164.9 C). In automotive underhood application environments, metal-backing of PCBs is being targeted for thermal dissipation, mechanical stability, and nterconnections reliability. In this study, the effect of metal-backed boards on the interconnect reliability has been evaluated. Previous studies on electronic reliability for automotive environments have addressed the damage mechanics of solder joints in plastic ball-grid arrays (BGAs) on nonmetal backed substrates and ceramic BGAs on nonmetal backed substrates. Other failure mechanisms investigated include delamination of PCB from metal backing. The test vehicle is a metal backed FR4-06 laminate. Metal backings investigated include aluminum and beryllium copper. Three adhesives have been investigated for metal backing including arlon, pressure sensitive adhesive, and pre-preg. The use of conformal coating for reliability improvement has also been investigated. Component architectures tested include plastic BGA devices, C2BGA devices, quad flat no-lead (QFN), and discrete resistors. Reliability of the component architectures has been evaluated for hot air solder level and electroless Ni/Au finishes. Crack propagation and intermetallic thickness data has been acquired as a function of cycle count. Reliability data has been acquired on all these architectures. Material constitutive behavior of arlon and pressure sensitive adhesive has been measured using uniaxial test samples. The measured material constitutive behavior has been incorporated into nonlinear finite element simulations. Predictive models have been developed for the dominant failure mechanisms for all the component architectures tested.

Drop-induced failures are most dominant in portable electronic products. In this study, explicit finite element models have been used to predict the transient dynamic behavior of various area-array package architectures assembled to printed circuit boards after drop-impact. Parameters predicted include field-quantities and their derivatives including displacement and strain. Methodologies for modeling components using smeared property formulations have been investigated. Reduced integration element formulations examined include&mdash;shell and solid elements. Model predictions have been validated with experimental data. Results show that models with smeared properties can predict transient-dynamic response of board assemblies in drop-impact, fairly accurately. A high-speed data acquisition system has been used to capture in-situ strain, continuity, and acceleration data in excess of 1 million samples per second. Ultra high-speed video at 40 000 fps has been used to capture the deformation kinematics. Component types examined include&mdash;plastic ball-grid arrays (BGAs), tape-array BGA, quad-flat no-lead packages (QFN), and conduction-cooled ball-grid arrays (C2BGA). Model predictions have been correlated with experimental data. Impact of experimental error sources on model correlation with experiments has also been investigated.

Damage pre-cursors based health management and prognostication methodology has been presented for electronic systems in harsh environments. The framework has been developed based on a development of correlation between damage precursors and underlying degradation mechanisms in lead-free packaging architectures. The proposed methodology eliminates the need for knowledge of prior stress histories and enables interrogation of system state using the identified damage precursors. Test vehicle includes various area-array packaging architectures subjected to single thermo-mechanical stresses including thermal cycling in the range of -40°C to 125°C and isothermal aging at 125°C. Experimental data on damage precursors has been presented for packaging architectures encompassing flex-substrate ball grid arrays, chip-array ball grid arrays, and plastic ball grid arrays. Examples of damage proxies include, phase-growth parameter, intermetallic thickness and interfacial stress variations. Damage proxies have correlated with residual life. The damage proxies have also been correlated with computational finite-element model predictions. Plastic and creep strain energy densities have been correlated to the identified damage proxies.

Solder materials demonstrate evolving microstructure and mechanical behavior that changes significantly with environmental exposures such as isothermal aging and thermal cycling. These aging effects are greatly exacerbated at higher temperatures typical of thermal cycling qualification tests for harsh environment electronic packaging. In the current study, mechanical measurements of thermal aging effects and material behavior evolution of lead free solders have been performed. Extreme care has been taken so that the fabricated solder uniaxial test specimens accurately reflect the solder materials present in actual lead free solder joints. A novel specimen preparation procedure has been developed where the solder uniaxial test specimens are formed in high precision rectangular cross-section glass tubes using a vacuum suction process. The tubes are then sent through a SMT reflow to re-melt the solder in the tubes and subject them to any desired temperature profile (i.e. same as actual solder joints). Using specimens fabricated with the developed procedure, isothermal aging effects and viscoplastic material behavior evolution have been characterized for 95.5Sn-4.0Ag-0.5Cu (SAC405) and 96.5Sn-3.0Ag-0.5Cu (SAC305) lead free solders, which are commonly used as the solder ball alloy in lead free BGAs and other components. Analogous tests were performed with 63Sn-37Pb eutectic solder samples for comparison purposes. In our total experimental program, samples have been solidified with both reflowed and water quenching temperature profiles, and isothermal aging has been performed at room temperature (25 °C) and elevated temperatures (100 °C, 125 °C and 150 °C). In this paper, we have concentrated on reporting the results of the room temperature aging experiments. Variations of the temperature dependent mechanical properties (elastic modulus, yield stress, ultimate strength, creep compliance, etc.) were observed and modeled as a function of room temperature aging time. Microstructural changes during room temperature aging have also been recorded for the solder alloys and correlated with the observed mechanical behavior changes.

In this work, risk-management and decision-support models for reliability prediction of flip chip packages in harsh environments have been presented. The models presented in this paper provide decision guidance for smart selection of component packaging technologies and perturbing product designs for minimal risk insertion of new packaging technologies. In addition, qualitative parameter interaction effects, which are often ignored in closed-form modeling, have been incorporated in this work. Previous studies have focused on development of modeling tools at sub-scale or component level. The tools are often available only in an offline manner for decision support and risk assessment of advanced technology programs. There is need for a turn key approach, for making trade-offs between geometry and materials and quantitatively evaluating the impact on reliability. Multivariate linear regression and robust principal components regression methods were used for developing these models. The first approach uses the potentially important variables from stepwise regression, and the second approach uses the principal components obtained from the eigen-values and eigen-vectors, for model building.. Principal-component models have been included because if their added ability in addressing multi-collinearity. The statistics models are based on accelerated test data in harsh environments, while failure mechanics models are based on damage mechanics and material constitutive behavior. Statistical models developed in the present work are based on failure data collected from the published literature and extensive accelerated test reliability database in harsh environments, collected by center of advanced vehicle electronics. Sensitivity relations for geometry, materials, and architectures based on statistical models, failure mechanics based closed form models and FEA models have been developed. Convergence of statistical, failure mechanics, and FEA based model sensitivities with experimental data has been demonstrated.

Piezoresistive sensors fabricated on (100) and (111) silicon surfaces are capable of measuring from four to all six components of the stress state at a point on the surface of an integrated circuit die. Such resistor-based sensors have been successfully designed and fabricated on these wafer planes and have been used successfully for measurement of die stresses in electronic packages by many research teams. In this paper, classical van der Pauw (VDP) structures, traditionally used for sheet resistance measurement, are shown to provide more than three times the sensitivity of standard resistor sensors. A single four-terminal VDP device replaces two resistor rosette elements and inherently utilizes the high-accuracy four-wire resistance measurement method. Theoretical expressions are developed for the change in resistance of the VDP device as a function of the individual stress components resolved in wafer coordinate systems on both the (100) and (111) silicon surfaces, and it is predicted theoretically that VDP devices will exhibit more than three times higher sensitivity to stress than standard resistor sensors. Design, fabrication, and experimental characterization of VDP and resistor test structures are presented for both silicon surfaces, and numerical simulation is used to help resolve discrepancies between theory and experiment. Sources of experimental error are identified, and the 3.16 times sensitivity enhancement of the VDP device is confirmed.

In this work, the effects of underfill cure temperature and JEDEC MSL preconditioning on underfill mechanical and strength properties, as well as flip chip assembly reliability have been explored. Baseline stress-strain curves, mechanical properties, and interfacial shear strengths of a capillary underfill were recorded for curing at 150 °C and 165 °C (30 minutes). In addition, the changes in the mechanical and strength properties resulting from MSL3 and MSL2 preconditioning were evaluated. The MSL preconditioning of the underfill samples included the JEDEC specified humidity and temperature exposures, plus three simulated reflows at 245 °C or 260 °C. Thermal cycling life tests from -55 to 125 °C were also conducted on daisy chain flip chip assemblies incorporating the same underfill. The test matrix for the reliability testing included both 150 °C and 165 °C curing profiles, and two levels of precondition (none and MSL3). Finally, the failure mechanisms in the flip chip assemblies were studied using CSAM, x-ray and SEM analyses. The results clearly indicate the advantages of the higher curing temperature including improved mechanical properties, superior thermal cycling fatigue life, and enhanced resistance to detrimental effects from moisture exposure and solder reflow.

There is a fundamental need for development of predictive techniques for electronic failure mechanisms in shock and drop-impact. Presently, one of the primary methodologies for assessment of shock and vibration survivability of electronic packaging is the JEDEC drop test method, JESD22-B111 which tests board-level reliability of packaging. However, packages in electronic products may be subjected to a widearray of boundary conditions beyond those targeted in the test method. Development of damage-equivalency methodologies will be invaluable in correlating standard test conditions to widely varying design-use conditions. In this paper, the development of a solder-joint stress based relative damage index has been investigated to establish a method for damage equivalency. Modal Analysis, Wavelet Decomposition, and Explicit Finite Element analysis has been used to assess reliability performance of the electronic boards. Deformation kinematics have been measured with the help of ultra high-speed data acquisition and video systems. Experimental data has been correlated to the finite element models. Failure predictions along with their modes and mechanisms have been discussed. Damage proxies for failure mechanisms in first-level interconnects have been developed. The approach is scalable to a wide variety of electronic applications. Component types examined include, plastic ball-grid arrays, flex ball-grid arrays for various pitch sizes between 0.5 mm to 1mm in both 63Sn37Pb and 95.5Sn4.0Ag0.5Cu solder alloy compositions. Dynamic measurements like acceleration, strain and resistance are measured and analyzed using highspeed data acquisition system capable of capturing in-situ strain, continuity and acceleration data in excess of 5 million samples per second. Ultra high-speed video upto 50,000 fps has been used to capture the deformation kinematics. Experimental results are correlated with finite element models which include reduced integration element formulations. Keywords: Shock, Vibration, Drop-Impact, Ball-Grid Arrays, Life-Prediction, Reliability

Solders and encapsulants used in electronic packaging exhibit evolving properties that change significantly with environmental exposures such as isothermal aging and thermal cycling. Such physical aging effects are exacerbated at higher temperatures typical of thermal cycling qualification tests for harsh environment electronic packaging. In this work, measurements of material behavior changes occurring in lead free solders and flip chip underfill encapsulants exposed to isothermal aging have been performed. Novel methods have been developed to fabricate solder and underfill uniaxial test specimens so that they accurately reflect the encapsulant layer present in flip chip assemblies. Using the developed specimen preparation procedures, mechanical testing has been performed on samples aged for up to 6 months at several different temperatures ranging from room temperature (25 °C) up to 150 °C. Stress-strain and creep tests have been performed on non-aged and aged samples, and the changes in mechanical behavior have been recorded for various durations of isothermal exposure.

Flip chip packaging technology has become one of the mainstream choices for future chip level package solutions to meet the ever increasing demand of miniaturization and high I/O requirements. Significant difference in the thermal expansion coefficients of silicon chip and organic-laminate substrate may subject the devices to thermo-mechanical failure mechanisms including interfacial-delamination, dielectric fracture, and solder-interconnect failure. Solder joint thermal-fatigue is a dominant failure mechanism in flip chip device interconnects. There is a need for predictive tools and techniques in product design for optimization and trade-off studies. Accelerated testing is a time consuming and resourceintensive process. Modeling and simulation techniques are an attractive alternative for calculation of stresses, strains and life prediction. Previous studies have shown the effect of material and geometric parameters on the reliability of rigid organic laminate printed circuit boards. Both 2-D (two dimensional) and 3-D (three dimensional) models have been used for the analysis [Pang 1997, Syed 2001]. Usually 3-D models have been shown to give better accuracy and more realistic results as compared to the 2-D models [Vandevelde 2003, Zahn 2003]. Comprehensive models for lead-free flip-chip bump metallurgies addressing main-factor and interactions effects between underfill properties, substrateproperties with interfacial-delamination and solderinterconnect fatigue are scarce and the effects of flip-chip on metal-backed flex not well understood. In this paper the scope of geometry and material parameters and their effect on reliability has been broadened and the effects of metalbacked flex-substrate on interconnect reliability studied. Nonlinear implicit finite element models have been developed for thermo-mechanical reliability of leaded and lead-free flip-chip devices on metal backed flex and the variation geometry and material parameters on reliability studied.

Electronic assemblies are approximately "stress free" near their assembly temperature, which is typically above 150 °C when encapsulants and solders are involved. As the assemblies are cooled below room temperature, the temperature difference between ambient and "stress free" conditions becomes extremely high, and the thermal expansion mismatch induced stresses, strains, and deformations in the assembly can become very large. This phenomenon is exacerbated by the changes in material behavior that occur at extreme low temperatures present in proposed NASA lunar and Mars missions. In particular, encapsulants become much more stiff/brittle losing their typical nonlinear/inelastic stress-strain characteristics and high strains to failure, and the yield stresses for solders become very high. In this work, we evaluated the mechanical performance and reliability of flip chip on laminate assemblies subjected to extreme low temperatures. Stress measurements have been made in the flip chip assemblies during thermal cycling using stress test chips incorporating piezoresistive sensor rosettes. The (111) silicon test chips were 5 x 5 mm in size, with perimeter solder balls on a 200-micron pitch. The obtained stress measurement data correlated well with the predictions of nonlinear finite element models. A microtester has been used to characterize the stress-strain behavior of the solder, underfill encapsulant, and PCB from -180 to +150 C to aid in the numerical simulations.

Solder materials demonstrate evolving microstructure and mechanical behavior that changes significantly with environmental exposures such as isothermal aging and thermal cycling. These aging effects are greatly exacerbated at higher temperatures typical of thermal cycling qualification tests for harsh environment electronic packaging. In the current study, mechanical measurements of thermal aging effects and material behavior evolution of lead free solders have been performed. Extreme care has been taken so that the fabricated solder uniaxial test specimens accurately reflect the solder materials present in actual lead free solder joints. A novel specimen preparation procedure has been developed where the solder uniaxial test specimens are formed in high precision rectangular cross-section glass tubes using a vacuum suction process. The tubes are then sent through a SMT reflow to remelt the solder in the tubes and subject them to any desired temperature profile (i.e. same as actual solder joints). Using specimens fabricated with the developed procedure, isothermal aging effects and viscoplastic material behavior evolution have been characterized for 95.5Sn-4.0Ag-0.5Cu (SAC405) and 96.5Sn-3.0Ag-0.5Cu (SAC305) lead free solders, which are commonly used as the solder ball alloy in lead free BGAs and other components. Analogous tests were performed with 63Sn-37Pb eutectic solder samples for comparison purposes. In our total experimental program, samples have been solidified with both reflowed and water quenching temperature profiles, and isothermal aging has been performed at room temperature (25 °C) and elevated temperatures (100 °C, 125 °C and 150 °C). In this paper, we have concentrated on reporting the results of the room temperature aging experiments. Variations of the temperature dependent mechanical properties (elastic modulus, yield stress, ultimate strength, creep compliance, etc.) were observed and modeled as a function of room temperature aging time. Microstructural changes during room temperature aging have also been recorded for the solder alloys and correlated with the observed mechanical behavior changes.

Silica filled epoxy encapsulants used for microelectronic packaging are known to exhibit evolving properties that change significantly with environmental exposures such as isothermal aging and thermal cycling. Most aging effects are typically exacerbated at higher temperatures at or above the glass transition temperature (Tg) of the encapsulant. Such extremes are often used during the high temperature dwells present in thermal cycling qualification tests for harsh environment electronic packaging. In this work, the first measurements of material behavior changes occurring in flip chip underfill encapsulants exposed to isothermal aging at temperatures near the Tg of the material have been performed. A microscale tension-torsion testing machine was used to evaluate the uniaxial tensile stress-strain and creep behaviors of an underfill material at several temperatures, after various durations of isothermal aging at 125 °C. A novel method has been developed to fabricate underfill uniaxial test specimens so that they accurately reflect the encapsulant layer present in flip chip assemblies. Using the developed specimen preparation procedure, samples were prepared and then aged for up to 500 hours at 125 °C. Stress-strain and creep tests have been performed on both non-aged and aged samples, and the changes in mechanical behavior were recorded for various durations of isothermal exposure. The obtained results showed an obvious degradation of the underfill mechanical properties and creep behavior as a function of the duration of the prior aging/preconditioning at 125 °C. Both the elastic modulus and ultimate tensile strength decline monotonically with the amount of isothermal aging. The observed trends suggest that this underfill will eventually lose all rigidity and cohesion if aged appropriately long at 125 °C.

The thermal performance of Ball Grid Array packages depends upon many parameters including die size, use of thermal balls, number of perimeter balls, use of underfill, and printed circuit board heat spreader and thermal via and spreader design. Thermal cycling can affect the integrity of thermal paths in and around the BGA as a result of the cracking of solder balls and delamination of the package, including at underfill interfaces. In this study, the impact of thermal cycling on the thermal performance of BGA's was investigated and quantified. A number of test boards which included a range of the parameters cited above were experimentally examined. A baseline thermal resistance was measured for each case, which was verified with numerical thermal modeling. The boards were then subjected to thermal cycling from -40°C to 125°C. Every 250 cycles the thermal performance was measured. Packages expected to be least reliable (with large die and no underfill), showed an increase in thermal resistance after 750 thermal cycles. Further increases in thermal resistance were observed with continuous thermal cycling until solder joint failure occurred at 1250 cycles, preventing additional measurements. The correlation between thermal cycling and thermal resistance was then analyzed using a numerical structural simulation model that predicted crack initiation in the solder joints. The first observed thermal resistance increase occurred in close proximity to the number of cycles where the finite element model predicted initiation of cracking in the thermal solder balls.

In this work, we report on our efforts to develop high reliability flip chip on laminate assemblies for deployment in harsh thermal cycling environments characteristic of ground and aerospace vehicles (e.g. -55 to 150 °C). Reliability enhancement has been achieved through the use of a novel low expansion, high stiffness, and relatively low cost laminate substrate material that virtually eliminates CTE mismatches between the silicon die and top layer PCB interconnect. The utilized laminate features a sandwich construction that contains standard FR-406 outer layers surrounding a low expansion high thermal conductivity carbon fiber-reinforced composite core (STABLCOR®). Through both experimental testing and modeling, we have demonstrated that robust flip chip assemblies can be produced that illustrate ultra-high solder joint reliability during thermal cycling and extremely low die stresses. Liquid to liquid thermal shock testing has been performed on test assemblies incorporating daisy chain test die, and piezoresistive test chips have been used to characterize temperature dependent die stresses. In both sets of experiments, results obtained using the hybrid PCB laminate with FR-406 outer layers and carbon fiber core have been compared to those obtained with more traditional glass-epoxy laminate substrates including FR-406 and NELCO 4000-13. Nonlinear finite element modeling results for the low expansion flip chip on laminate assemblies have been correlated with the experimental data. Mechanical testing of the carbon fiber-reinforced laminate materials was used to demonstrate its high elastic modulus over a wide temperature range. In addition, unconstrained thermal expansion measurements have also been performed on the hybrid laminate materials using strain gages to demonstrate their low CTE characteristics.

Presently, no-flow underfills have very low or no filler content because micron-size filler particles hinder solder joint formation. Nano-silica underfills have the potential of attaining higher filler loading in no-flow underfills without hindering solder interconnect formation [13, 22]. The silica particles reduce coefficient of thermal expansion of the underfill-epoxy matrix. In traditional underfills, the size of silica particles is in the micrometer range. In this paper, property prediction models based on representative volume element (RVE) and modified random spatial adsorption (RSA) have been developed. The models utilize statistically isotropic random-placement of nanoparticles, in addition to random size-distribution of particles for analysis of material. Volume fractions upto 40 percent of nano-silica filler have been studied. Properties predicted and correlated with experimental data include, coefficient of thermal expansion, elastic modulus, poisson's ratio, and viscoelastic properties including stress relaxation under applied strain. All properties have been measured in the temperature range of -175C to +150°C. Nano-underfills with 10 percent and 22 percent volume fraction of filler assembled with 63Sn37Pb eutectic and 95.5Sn3.5Ag1.0Cu leadfree flipchip devices have been subjected to thermal shock tests in the range of - 55 to 125°C and - 55 to 150°C respectively. The trade-offs between using nano-fillers instead of micron-fillers on thermo-mechanical properties and reliability has been benchmarked.

We report the first high lateral resolution Auger electron spectroscopic (AES) measurements on high aspect ratio Sn whiskers. The whiskers were grown from stressed thin films (~ 6000 Å) of Sn on brass using a magnetron sputtering system. The stress states were controlled by background Ar sputtering pressure to produce films containing compressive and no stress. The Auger spectra show that, after sputter cleaning, the whisker is 100% Sn at all locations along the whisker shaft, at the growing blunt end of the shaft, and with depth (~ 1000 Å) into the side of the whisker. The "as received" Sn whisker surface shows the expected ~ 200 Å of native Sn oxide at all locations and the O signal disappeared after 200 Å of sputter cleaning. There was no evidence of oxygen within the bulk of the whisker. That brass is not observed in the whisker supports the notion that whisker formation is a result of material mass transport which affects stress (usually compressive) relief and argues against extrusion mechanisms through a cracked surface oxide to explain whiskering phenomena. Parallel experiments to compare whisker growth on atomically clean and oxide-covered Sn surface show no differences in whiskering propensity, in agreement with correlating work at NIST. A remarkable aspect of the whisker growth is that high aspect ratio whiskers ~ 100-500 µm in length containing no brass are grown from a ~ 0.6 µm thin film of Sn.

Solder materials demonstrate evolving microstructure and mechanical behavior that changes significantly with environmental exposures such as isothermal aging and thermal cycling. These aging effects are greatly exacerbated at higher temperatures typical of thermal cycling qualification tests for harsh environment electronic packaging. In the current study, mechanical measurements of thermal aging effects and material behavior evolution of lead free solders have been performed. Extreme care has been taken so that the fabricated solder uniaxial test specimens accurately reflect the solder materials present in actual lead free solder joints. A novel specimen preparation procedure has been developed where the solder uniaxial test specimens are formed in high precision rectangular cross-section glass tubes using a vacuum suction process. The tubes are then sent through a SMT reflow to re-melt the solder in the tubes and subject them to any desired temperature profile (i.e. same as actual solder joints). Using specimens fabricated with the developed procedure, isothermal aging effects and viscoplastic material behavior evolution have been characterized for 95.5Sn-4.0Ag-0.5Cu (SAC405) and 96.5Sn-3.0Ag-0.5Cu (SAC305) lead free solders, which are commonly used as the solder ball alloy in lead free BGAs and other components. Analogous tests were performed with 63Sn-37Pb eutectic solder samples for comparison purposes. In our total experimental program, samples have been solidified with both reflowed and water quenching temperature profiles, and isothermal aging has been performed at room temperature (25 °C) and elevated temperatures (100 °C, 125 °C and 150 °C). In this paper, we have concentrated on reporting the results of the room temperature aging experiments. Variations of the temperature dependent mechanical properties (elastic modulus, yield stress, ultimate strength, creep compliance, etc.) were observed and modeled as a function of room temperature aging time. Microstructural changes during room temperature aging have also been recorded for the solder alloys and correlated with the observed mechanical behavior changes.

Electronic products may be subjected shock and vibration during shipping, normal usage and accidental drop. High-strain rate transient bending produced by such loads may result in failure of fine-pitch electronics. Current experimental techniques rely on electrical resistance for determination of failure. Significant advantage can be gained by prior knowledge of impending failure for applications where the consequences of system-failure may be catastrophic. This research effort focuses on an alternate approach to damage-quantification in electronic assemblies subjected to shock and vibration, without testing for electrical continuity. The proposed approach can be extended to monitor product-level damage. In this paper, statistical pattern recognition and leading indicators of shock-damage have been used to study the damage initiation and progression in shock and drop of electronic assemblies. Statistical pattern recognition is currently being employed in a variety of engineering and scientific disciplines such as biology, psychology, medicine, marketing, artificial intelligence, computer vision and remote sensing [Jain, et. al. 2000]. The application quantification of shock damage in electronic assemblies is new. Previously, free vibration of rectangular plates has been studied by various researchers [Leissa 1969, Young 1950, Gorman 1982, Gurgoze 1984, Wu 2003] for development of analytical closed-form models. In this paper, closed-form models have been developed for the eigen-frequencies and mode-shapes of electronic assemblies with various boundary conditions and component placement configurations. Model predictions have been validated with experimental data from modal analysis. Pristine configurations have been perturbed to quantify the degradation in confidence values with progression of damage. Sensitivity of leading indicators of shock-damage to subtle changes in boundary conditions, effective flexural rigidity, and transient strain response have been quantified. A damage index for Experimental Damage Monitoring has been developed using the failure indicators. The above damage monitoring approach is not based on electrical continuity and hence can be applied to any electronic assembly structure irrespective of the interconnections. The damage index developed provides parametric damage progression data, thus removing the limitation of current failure testing, where the damage progression can not be monitored. Hence the proposed method does not require the assumption that the failure occurs abruptly after some number of drops and can be extended to product level drops.

The objective of this work is to develop a greater understanding of the mechanisms controlling fretting under various vibration conditions. This information is intended to provide a basis for understanding and reducing this potential problem in automotive connectors. Toward this end, an experimental study of connector samples under multifrequency vibration has been conducted. The primary connector being investigated is a single row PC-type connector. A secondary specimen tested is a single row automotive connector.

Statistical methods are used to model elasto-plastic contact between two rough surfaces using a recent finite element model of elasto-plastic hemispherical contact and also recent advances in strain gradient modeling. The elasto-plastic hemispherical contact model used to model individual asperities accounts for a varying hardness effect due to deformation of the contact geometry that has been documented by other works. The strain gradient model accounts for changes in hardness due to scaling effects. The contact between surfaces with hypothetical material and surface properties, such as the elastic modulus, yield strength, and roughness are modeled. A model is also constructed to consider a variable asperity contact radius to evaluate if the strain gradient model will affect it differently. The models produce predictions for contact area, contact force, and surface separation. The strain gradient effects decrease the real area of contact and increase the average contact load in comparison to the model without these effects. The strain gradient model seems to have a larger influence on the predictions of contact load and area than does considering a variable asperity contact radius for the cases considered in this work.

This work describes a non-statistical multi-scale model of the normal contact between rough surfaces. The model produces predictions for contact area as a function of contact load, and is compared to the traditional Greenwood andWilliamson (GW) and Majumdar and Bhushan (MB) rough surface contact models, which represent single-scale statistical and fractal analyses, respectively. The current model incorporates the effect of asperity deformations at multiple scales into a simple framework for modeling the contact between nominally flat rough surfaces. Similar to the "protuberance upon protuberance" theory proposed by Archard, the model considers the effect of having smaller asperities located on top of larger asperities in repeated fashion with increasing detail down to the limits of current measurement techniques. The parameters describing the surface topography (areal asperity density and asperity radius) are calculated from an FFT performed of the surface profile. Thus, the model considers multi-scale effects, which fractal methods have addressed, while attempting to more accurately incorporate the deformation mechanics into the solution. After the FFT of a real surface is calculated, the computational resources needed for the method are very small. Perhaps surprisingly, the trends produced by this non-statistical multi-scale model are quite similar to those arising from the GW and MB models, but seem largely unaffected by the sampling resolution at the employed surface data.

The reliability of electrostatically actuated ohmic contact type MEMS relays has been investigated. Multi-contact MEMS relays laterally actuated using electrostatic comb-drive actuators were used in this study. The MEMS relays were fabricated using the MetalMUMPs process, which uses a 20 µm thick electroplated nickel as the structural layer. A 3 µm thick gold layer was electroplated on the electrical contact surfaces. An example MEMS relay with planar contacts of area 80 µm x 20 µm and spacing of 10 µm between the movable and fixed contacting surfaces is discussed. The overall size of the relay is approximately 3 mm x 3 mm. "Resistance versus applied voltage" characteristics have been studied. At an applied dc bias voltage of 120 V, the movable fingers make initial contact with the fixed fingers. The "resistance versus applied voltage" characteristics have been measured for an applied bias voltage in the range of 172-220 V. Reliability testing of the MEMS relay up to one million actuations has been carried out and the resistance degradation with actuation cycles is discussed.

In this work, we report on our efforts to develop high reliability flip chip on laminate assemblies for deployment in harsh thermal cycling environments characteristic of ground and aerospace vehicles (e.g. -55 to 150 °C). Reliability enhancement has been achieved through the use of a novel low expansion, high stiffness, and relatively low cost laminate substrate material that virtually eliminates CTE mismatches between the silicon die and top layer PCB interconnect. The utilized laminate features a sandwich construction that contains standard FR-406 outer layers surrounding a low expansion high thermal conductivity carbon fiber-reinforced composite core (STABLCOR®). Through both experimental testing and modeling, we have demonstrated that robust flip chip assemblies can be produced that illustrate ultra-high solder joint reliability during thermal cycling and extremely low die stresses. Liquid to liquid thermal shock testing has been performed on test assemblies incorporating daisy chain test die, and piezoresistive test chips have been used to characterize temperature dependent die stresses. In both sets of experiments, results obtained using the hybrid PCB laminate with FR-406 outer layers and carbon fiber core have been compared to those obtained with more traditional glass-epoxy laminate substrates including FR-406 and NELCO 4000-13. Nonlinear finite element modeling results for the low expansion flip chip on laminate assemblies have been correlated with the experimental data. Unconstrained thermal expansion measurements have also been performed on the hybrid laminate materials using strain gages to demonstrate their low CTE characteristics. Other experimental testing has demonstrated that the new laminate successfully passes toxicity, flammability, and vacuum stability testing as required for pressurized and un-pressurized space applications.

Minimizing device side die stresses is especially important when multiple copper/low-k interconnect redistribution layers are present. Mechanical stress distributions in packaged silicon die resulting during assembly or environmental testing can be accurately characterized using test chips incorporating integral piezoresistive sensors. In this paper, measurements of thermally induced stresses in flip chip on laminate assemblies are presented. Transient die stress measurements have been made during underfill cure, and the room temperature die stresses in final cured assemblies have been compared for several different underfill encapsulants. In addition, stress variations have been monitored in the assembled flip chip die as the test boards were subjected to slow temperature changes from -40 to +150 C. Using these measurements and ongoing numerical simulations, valuable insight has been gained on the effects of assembly variables and underfill material properties on the reliability of flip chip packages.

In the current work, the decision-support models for deployment of flip-chip devices under various harsh thermal environments have been presented. The current work is targeted towards government contractors, OEMs, and 3rd party contract manufacturers who intend to select part architectures and board designs based on specified mission requirements. In addition, the mathematical models presented in this paper provide decision guidance for smart selection of flip-chip packaging technologies and for perturbing presently-deployed product designs for minimal risk insertion of new materials and architectures. The models serve as an aid for understanding the sensitivity of component reliability to geometry, package architecture, material properties and board attributes to enable educated selection of appropriate device formats. Modeling tools and techniques for assessment of component reliability in extreme environments are scarce. Previous studies have focused on development of modeling tools at sub-scale level. The tools are often available only in an offline manner for decision support and risk assessment of advanced technology programs. There is need for a turn key approach, for making trade-offs between geometry and materials and quantitatively evaluating the impact on reliability. Application of flip-chip assemblies and underfills in benign office environments and wireless applications is not new, however their reliability in extreme environments is still not very well understood. The perturbation approach presented in this paper enables higher-accuracy model prediction by perturbing known accelerated-test data-sets using models, using factors which quantify the sensitivity of reliability to various design, material, architecture and environmental parameters. The models are based on a combination of statistics and failure mechanics. In addition, parameter interaction effects, which are often ignored in closed form modeling, have been incorporated in the proposed hybrid approach. The statistics models are based on accelerated test data in harsh environments, while failure mechanics models are based on damage mechanics and material constitutive behavior. Convergence between statistical model sensitivities and failure mechanics based model sensitivities has been demonstrated. Predictions of sensitivities have also been validated against the experimental test data.

In traditional underfills, the size of silica particles is in the micrometer range. Reduction in particle sizes into the nanometer range has the potential of attaining higher volume fraction particle loading in the underfills and greater control over underfill properties for higher reliability applications. Silica particles are used as a filler material in electronic underfills to reduce coefficient of thermal expansion of the underfill-epoxy matrix. Presently, no-flow underfills have very low or no filler content because micron-size filler particles hinder solder joint formation. Nano-silica underfills have the potential of attaining higher filler loading in no-flow underfills without hindering solder interconnect formation [Shi 1999, Liu 2001]. In this paper, property prediction models based on representative volume element (RVE) and modified random spatial adsortion have been developed. The models can be used for development of nano-silica underfills with desirable thermo-mechanical properties. Temperature dependent thermo-mechanical properties of nano-underfills have been evaluated and correlated with models in a temperature range of -175°C to +150 °C. Properties investigated include, temperature dependent stress-strain, creep and stress relaxation behavior. Nano-underfills on 63Sn37Pb eutectic and 95.5Sn3.5Ag1.0Cu leadfree flip-chip devices have been subjected to thermal shock tests in the range of -55 to 125°C and -55 to 150°C respectively. The trade-offs between using nano-fillers instead of micron-fillers on thermo-mechanical properties and reliability has been benchmarked.

In this paper, prognostic indicators for electronic packages have been developed for determination of damage-state in absence of macro-indicators of failure. A methodology for prognostication-of-electronics has been developed for accurate assessment of residual life in a deployed electronic components. Proxies for leading indicators-of-failure have been correlated with damage progression under thermo-mechanical loads. Examples of proxies include &mdash; micro-structural evolution characterized by average phase size, intermetallic growth rate in solder interconnects, and on-chip stresses. Validity of damage proxies has been investigated for both 63Sn37Pb leaded and SnAgCu leadfree electronics. Structures examined include &mdash; plastic ball grid array format electronic and MEMS Packages and discrete devices assembled with FR4-06 laminates. In addition, mechanical stresses on the device side of the flip chip die have been measured in-situ, using (111) silicon stress sensor chips containing piezoresistive sensor rosettes under thermo-mechanical loads. Patterns in stress history have been studied and correlated to appearance of damage. Focus of the research presented in this paper is on interrogation of the aged material's damage state and enhancing the understanding of damage progression. The research is aimed at development of damage relationships for determination of residual life of aged electronics and assessment of design margins instead of life prediction of new components. The prognostic indicators presented in this paper, can be used for health monitoring of electronic assemblies.

In this paper, a methodology for prognostication-ofelectronics has been developed for accurate assessment of residual life in a deployed electronic components, and determination of damage-state in absence of macro-indicators of failure. Proxies for leading indicators-of-failure have been identified and correlated with damage progression under thermomechanical loads. Examples of proxies include &mdash; microstructural evolution characterized by average phase size and intermetallic growth rate in solder interconnects. Validity of damage proxies has been investigated for both 63Sn37Pb leaded and SnAgCu leadfree electronics. Structures examined include &mdash; plastic ball grid array format electronic and MEMS Packages and discrete devices assembled with FR4-06 laminates. Focus of the research presented in this paper is on interrogation of the aged material's damage state and enhancing the understanding of damage progression. The research is aimed at development of damage relationships for determination of residual life of aged electronics and assessment of design margins instead of life prediction of new components. The prognostic indicators presented in this paper, can be used for health monitoring of electronic assemblies.

Underfill encapsulation is used with flip chip die assembled to laminate substrates to distribute and minimize the solder joint strains, thus improving thermal cycling fatigue life. Any delaminations that occur at the underfill/die interface will propagate to the neighboring solder bumps and lead to solder joint fatigue and failure. The onset and propagation of delaminations in flip chip assemblies exposed to thermal cycling are governed by the cyclic stresses and damage occurring at the underfill to die interface. For this reason, underfills are optimized by increasing their adhesion strength, interfacial fracture toughness, and resistance to thermal aging. In this work, we have sought to develop a fundamental understanding of delamination initiation and growth in flip chip assemblies through simultaneous characterization of the stress and delamination states at the die to underfill interface. Mechanical stresses on the device side of the flip chip die have been measured using special (111) silicon stress test chips containing piezoresistive sensor rosettes that are capable of measuring the complete three-dimensional silicon surface stress state in the silicon (including the interfacial shear and normal stresses at the die to underfill interface). By continuous monitoring of the sensor resistances, the die surface stresses were measured during post-assembly thermal cycling environmental testing from -40 to 125 C. With this approach, the stress distributions across the chip, and the stress variations at particular locations at the die to underfill interface have been interrogated for the entire life of the flip chip assembly. In order to correlate the stress changes at the sensor sites with delamination onset and propagation, CSAM evaluation of the test assemblies was performed after every 125 thermal cycles. A total of 75 flip chip assemblies with 3 different underfills have been evaluated. For each assembly, the complete histories of three-dimensional die surface stresses and delamination propagation have been recorded versus the number of thermal cycles. Through these measurements, we have been able to identify the stress histories that lead to delamination initiation for each underfill encapsulant, and the variation of the stresses that occur before and during delamination propagation. The progressions of stress and delamination have been mapped across the entire surface of the die, and a series of stress/delamination videos have been produced. One of the most important discoveries is that the shear stresses occurring at the corners of flip chip die have been demonstrated to be a suitable proxy for prognostic determination of future delamination initiations and growth.

Product level assessment of drop and shock reliability relies heavily on experimental test methods. Prediction of drop and shock survivability is largely beyond the state-of-art. However, the use of experimental approach to test out every possible design variation, and identify the one that gives the maximum design margin is often not feasible because of product development cycle time and cost constraints. Presently, one of the primary methodologies for evaluating shock and vibration survivability of electronic packaging is the JEDEC drop test method, JESD22-B111 which tests board-level reliability of packaging. However, packages in electronic products may be subjected to a wide-array of boundary conditions beyond those targeted in the test method. In this paper, a failure-envelope approach based on wavelet transforms and damage proxies has been developed to model drop and shock survivability of electronic packaging. Data on damage progression under transient-shock and vibration in both 95.5Sn4.0Ag0.5Cu and 63Sn37Pb ball-grid arrays has been presented. Component types examined include &mdash; flex-substrate and rigid substrate ball-grid arrays. Dynamic measurements like acceleration, strain and resistance are measured and analyzed using high-speed data acquisition system capable of capturing insitu strain, continuity and acceleration data in excess of 5 million samples per second. Ultra high-speed video at 150,000 fps per second has been used to capture the deformation kinematics. The concept of relative damage index has been used to both evaluate and predict damage progression during transient shock. The failure-envelope provides a fundamental basis for development of component integration guidelines to ensure survivability in shock and vibration environments at a userspecified confidence level. The approach is scalable to application at system-level. Explicit finite-element models have been developed for prediction of shock survivability based on the failure envelope. Model predictions have been correlated with experimental data for both leaded and leadfree ball-grid arrays.

High stresses in semiconductor die and other packaging elements can be developed in electronic assemblies subjected to extremely low ambient temperatures leading to reliability concerns. In this work, we have characterized and modeled the silicon die stresses occurring in flip chip assemblies at low temperatures. Stress measurements have been made at temperatures down to -180 °C using test chips incorporating piezoresistive sensor rosettes. The obtained stress measurement data have been correlated with the predictions of nonlinear finite element models. A microtester has been used to characterize the stress-strain behavior of the solders and encapsulants from -180 to +150 °C to aid in this modeling effort.

High stresses in semiconductor die and other packaging elements can be developed in electronic assemblies subjected to extremely low ambient temperatures leading to reliability concerns. In this work, we have characterized and modeled the silicon die stresses occurring in chip on board assemblies at low temperatures. Stress measurements have been made in both flip chip and chip-and-wire assemblies down to -180 C using test chips incorporating piezoresistive sensor rosettes. The obtained stress measurement data have been correlated with the predictions of nonlinear finite element models. A microtester has been used to characterize the stress-strain behavior of the solders and encapsulants from -180 to 150 C to aid in this modeling effort.

Fretting corrosion induced by vibration is a topic of major concern for automotive applications, often leading to increased contact resistance and connector failure. Presently, modeling of the behavior of connectors during fretting corrosion is a difficult matter, requiring many parameters, and is generally highly nonlinear in nature. Experimental testing of sample connectors is currently the only practical method of evaluating connector performance; however, testing can be a time-consuming and inexact task. Prior work by the authors studied the fretting behavior of connectors subjected to single frequency vibration. Correlation of experimental results with simulated behavior showed that, for the primary mode of connector interface motion observed (rocking-type motion), the relative moment at the interface was a good indicator of the observed fretting rate. It was also shown that the moment applied as the result of a given excitation level and frequency could reasonably be predicted via simulation. The current work extends this approach to random vibration profiles, which are a more realistic representation of the connector application environment. A simple model is developed which relates the early stage fretting corrosion rate to the threshold vibration levels for the connector, the dynamic characteristics of the connector/wiring con- figuration, and the vibration profile. A high degree of consistency between this model and the experimental data was demonstrated. Interestingly, regardless of the excitation profile applied to the overall system, the existence of a characteristic vibration threshold at the connector interface was observed.

In flip chip assemblies, delamination failure of the underfill to die or underfill to PCB interface leads to interfacial crack growth and early solder ball fatigue. Reliability can be enhanced by maximizing the underfill adhesion to the die passivation and PCB soldermask. In the first part of this study, various test methods for measuring the underfill to soldermask adhesion were investigated by using Finite Element Analysis. A new test method based on the Iosipescu technique was then used to evaluate the shear strength of the underfill to PCB interface. Several tests were then performed to characterize the effects of different environmental conditions such as humidity exposure, thermal cycling, and thermal shock on the shear strength. In the second part of this investigation, the mechanical responses of underfill encapsulants have been characterized via material testing. A tension-torsion micro tester has been used to evaluate stress-strain characteristics and mechanical properties of underfill materials as a function of temperature. A specimen preparation procedure has been developed to cast 5 mil thick underfill uniaxial tension test specimens that are cured in a reflow oven using the same conditions as those used in actual flip chip assembly.

Reliable, consistent, and comprehensive material property data are needed for microelectronic encapsulants for the purpose of mechanical design, reliability assessment, and process optimization of electronic packages. In our research efforts, the mechanical responses of several different capillary flow snap cure underfill encapsulants are being characterized. A microscale tension-torsion testing machine has been used to evaluate the uniaxial tensile stress-strain behavior of underfill materials as a function of temperature and strain rate. A critical step to achieving accurate experimental results has been the development of a sample preparation procedure that produces mechanical test specimens that reflect the properties of true underfill encapsulant layers. In the developed method, 75-125 mm (3-5 mil) thick underfill uniaxial tension specimens are dispensed and cured using production equipment and the same processing conditions as those used with actual flip chip assemblies. A three parameter hyperbolic tangent empirical model has been shown to provide accurate fits to the observed underfill nonlinear stress-strain behavior over a range of temperatures and strain rates. In addition, the first measurements of underfill mechanical behavior at cryogenic temperatures have been made.

The ternary intermetallic compound Au 0.5Ni 0.5Sn4 forms at the Sn-37Pb/ENIG solder interface during aging and temperature cycling, leading to increased interfacial cracking and a corresponding decrease in solder joint reliability for 15 mm ball grid array (BGA) structures. The (Au,Ni)Sn4 intermetallic forms at both the board finish (bottom) and component side (top) of the solder joint for isothermally aged, temperature-cycled, and (aged + cycled) joints. For control specimens (reflow only), no cracks or interfacial Au are observed. For isothermally aged joints (170 and 340 hours @ 125 C), a broken, discontinuous layer of (Au,Ni)Sn4 is observed, but no cracking is observed. For temperature-cycled joints, lowered reliability and interfacial cracking occurs along a continuous (Au,Ni)Sn4 intermetallic layer on the solder side of the interface after ~ 450 hours of cycling. Aging + cycling did little to inhibit cracking or formation of (Au,Ni)Sn4. Development of a continuous (Au,Ni)Sn4 film at the interface is the key failure mechanism. At low cycle numbers where high joint reliability is observed, the (Au,Ni)Sn4 layer is broken, discontinuous, and not fully developed. At higher cycle numbers and longer aging times, the (Au,Ni)Sn4 layer becomes continuous and encourages crack growth along the intermetallic interface and consequent lower reliability. The correlation of interfacial smoothness with lowered reliability is consistent with recent work showing that, when intermetallic compounds form smoothly at the solder interface, the mechanical properties are degraded (compared to a rough intermetallic) due to the decreased resistance to shear along the interface

Silica particles are used as a filler material in electronic underfills to reduce coefficient of thermal expansion of the underfill-epoxy matrix. In traditional underfills, the size of silica particles is in the micrometer range. Reduction in particle sizes into the nanometer range has the potential of attaining higher volume fraction particle loading in the underfills and greater control over underfill properties for higher reliability applications. Presently, no-flow underfills have very low or no filler content because micron-size filler particles hinder solder joint formation. Nano-silica underfills have the potential of attaining higher filler loading in no-flow underfills without hindering solder interconnect formation [Shi 1999, Liu 2001]. In this paper, property prediction models based on representative volume element (RVE) and modified random spatial adsortion have been developed. The models can be used for development of nano-silica underfills with desirable thermo-mechanical properties. Temperature dependent thermo-mechanical properties of nano-underfills have been evaluated and correlated with models in a temperature range of -175 °C to +150 °C. Properties investigated include, temperature dependent stress-strain, creep and stress relaxation behavior. Nano-underfills on 63Sn37Pb eutectic and 95.5Sn3.5Ag1.0Cu leadfree flip-chip devices have been subjected to thermal shock tests in the range of -55 to 125 °C and -55 to 150 °C respectively. The trade-offs between using nano-fillers instead of micron-fillers on thermo-mechanical properties and reliability has been benchmarked.

Modeling tools and techniques for assessment of component reliability in extreme environments are scarce. Previous studies have focused on development of modeling tools at sub-scale or component level. The tools are often available only in an offline manner for decision support and risk assessment of advanced technology programs. There is need for a turn key approach, for making trade-offs between geometry and materials and quantitatively evaluating the impact on reliability. Application of flip-chip assemblies and underfills in benign office environments and wireless applications is not new, however their reliability in extreme environments is still not very well understood. In the current work, the decision-support models for deployment of flip-chip devices under various harsh thermal environments have been presented. The current work is targeted towards government contractors, OEMs, and 3rd party contract manufacturers who intend to select part architectures and board designs based on specified mission requirements. In addition, the mathematical models presented in this paper provide decision guidance for smart selection of component packaging technologies and perturbing presently-deployed product designs for minimal risk insertion of new packaging technologies. The models serve as an aid for understanding the sensitivity of component reliability to geometry, package architecture, material properties and board attributes to enable educated selection of appropriate device formats. The perturbation approach presented in this paper enables higher-accuracy model prediction by perturbing known accelerated-test data-sets using models, using factors which quantify the sensitivity of reliability to various design, material, architecture and environmental parameters. The models are based on a combination of statistics and failure mechanics. In addition, parameter interaction effects, which are often ignored in closed form modeling, have been incorporated in the proposed hybrid approach. The statistics models are based on accelerated test data in harsh environments, while failure mechanics models are based on damage mechanics and material constitutive behavior. Convergence between statistical model sensitivities and failure mechanics based model sensitivities has been demonstrated. Predictions of sensitivities have also been validated against the experimental test data.

Underfill encapsulation is used with flip chip die assembled to laminate substrates to distribute and minimize the solder joint strains, thus improving thermal cycling fatigue life. Any delaminations that occur at the underfill/die interface will propagate to the neighboring solder bumps and lead to solder joint fatigue and failure. The onset and propagation of delaminations in flip chip assemblies exposed to thermal cycling are governed by the cyclic stresses and damage occurring at the underfill to die interface. For this reason, underfills are optimized by increasing their adhesion strength, interfacial fracture toughness, and resistance to thermal aging. In this work, we have sought to develop a fundamental understanding of delamination initiation and growth in flip chip assemblies through simultaneous characterization of the stress and delamination states at the die to underfill interface. Mechanical stresses on the device side of the flip chip die have been measured using special (111) silicon stress test chips containing piezoresistive sensor rosettes that are capable of measuring the complete three-dimensional silicon surface stress state in the silicon (including the interfacial shear and normal stresses at the die to underfill interface). By continuous monitoring of the sensor resistances, the die surface stresses were measured during post-assembly thermal cycling environmental testing from -40 to 125 C. With this approach, the stress distributions across the chip, and the stress variations at particular locations at the die to underfill interface have been interrogated for the entire life of the flip chip assembly. In order to correlate the stress changes at the sensor sites with delamination onset and propagation, CSAM evaluation of the test assemblies was performed after every 125 thermal cycles. A total of 75 flip chip assemblies with 3 different underfills have been evaluated. For each assembly, the complete histories of three-dimensional die surface stresses and delamination propagation have been recorded versus the number of thermal cycles. With this approach, we have been able to identify the stress histories that lead to delamination initiation for each underfill encapsulant, and the variation of the stresses that occur before and during delamination propagation. The progressions of stress and delamination have been mapped across the entire surface of the die, and a series of stress/delamination videos have been produced. One of the most important discoveries is that the shear stresses occurring at the corners of flip chip die have been demonstrated to be a suitable proxy for prognostic determination of future delamination initiations and growth.

In this work, we report on our efforts to develop ultra-high reliability flip chip on laminate assemblies for deployment in harsh thermal cycling environments characteristic of ground and aerospace vehicles (e.g. -55 to 150 C). Reliability enhancement has been achieved through the use of a novel low expansion, high stiffness, and relatively low cost laminate substrate material that virtually eliminates CTE mismatches between the silicon die and top layer PCB interconnect. The utilized laminate features a sandwich construction that contains standard FR-406 outer layers surrounding a low expansion high thermal conductivity carbon fiber-reinforced composite core (STABLCOR). Through both experimental testing and modeling, we have demonstrated that robust flip chip assemblies can be produced that illustrate ultra-high solder joint reliability during thermal cycling and extremely low die stresses. Liquid to liquid thermal shock testing has been performed on test assemblies incorporating daisy chain test die, and piezoresistive test chips have been used to characterize temperature dependent die stresses. In both sets of experiments, results obtained using the hybrid PCB laminate with FR-406 outer layers and carbon fiber core have been compared to those obtained with more traditional glass-epoxy laminate substrates including FR-406 and NELCO 4000-13. Nonlinear finite element modeling results for the low expansion flip chip on laminate assemblies have been correlated with the experimental data. Unconstrained thermal expansion measurements have also been performed on the hybrid laminate materials using strain gages to demonstrate their low CTE characteristics. Other experimental testing has demonstrated that the new laminate successfully passes toxicity, flammability, and vacuum stability testing as required for pressurized and un-pressurized space applications.

In this paper, a methodology for prognostication-of-electronics has been developed for accurate assessment of residual life in a deployed electronic components, and determination of damage-state in absence of macro-indicators of failure. Proxies for leading indicators-of-failure have been identified and correlated with damage progression under thermo-mechanical loads. Examples of proxies include &mdash; micro-structural evolution characterized by average phase size and intermetallic growth rate in solder interconnects. Validity of damage proxies has been investigated for both 63Sn37Pb leaded and SnAgCu leadfree electronics. Structures examined include &mdash; plastic ball grid array format electronic and MEMS Packages and discrete devices assembled with FR4-06 laminates. Focus of the research presented in this paper is on interrogation of the aged material's damage state and enhancing the understanding of damage progression. The research is aimed at development of damage relationships for determination of residual life of aged electronics and assessment of design margins instead of life prediction of new components. The prognostic indicators presented in this paper, can be used for health monitoring of electronic assemblies.

Product level assessment of drop and shock reliability relies heavily on experimental test methods. Prediction of drop and shock survivability is largely beyond the state-of-art. However, the use of experimental approach to test out every possible design variation, and identify the one that gives the maximum design margin is often not feasible because of product development cycle time and cost constraints. Presently, one of the primary methodologies for evaluating shock and vibration survivability of electronic packaging is the JEDEC drop test method, JESD22-B111 which tests board-level reliability of packaging. However, packages in electronic products may be subjected to a wide-array of boundary conditions beyond those targeted in the test method. In this paper, a failure-envelope approach based on wavelet transforms and damage proxies has been developed to model drop and shock survivability of electronic packaging. Data on damage progression under transient-shock and vibration in both 95.5Sn4.0Ag0.5Cu and 63Sn37Pb ball-grid arrays has been presented. Component types examined include &mdash; flex-substrate and rigid substrate ball-grid arrays. Dynamic measurements like acceleration, strain and resistance are measured and analyzed using high-speed data acquisition system capable of capturing in-situ strain, continuity and acceleration data in excess of 5 million samples per second. Ultra high-speed video at 150,000 fps per second has been used to capture the deformation kinematics. The concept of relative damage index has been used to both evaluate and predict damage progression during transient shock. The failure-envelope provides a fundamental basis for development of component integration guidelines to ensure survivability in shock and vibration environments at a user-specified confidence level. The approach is scalable to application at system-level. Explicit finite-element models have been developed for prediction of shock survivability based on the failure envelope. Model predictions have been correlated with experimental data for both leaded and leadfree ball-grid arrays.

In this paper, a methodology for prognostication-of-electronics has been developed for accurate assessment of residual life in a deployed electronic components, and determination of damage-state in absence of macro-indicators of failure. Proxies for leading indicators-of-failure have been identified and correlated with damage progression under thermomechanical loads. Examples of proxies include &mdash; microstructural evolution characterized by average phase size and intermetallic growth rate in solder interconnects. Validity of damage proxies has been investigated for both 63Sn37Pb leaded and SnAgCu leadfree electronics. Structures examined include &mdash; plastic ball grid array format electronic and MEMS Packages and discrete devices assembled with FR4-06 laminates. Focus of the research presented in this paper is on interrogation of the aged material's damage state and enhancing the understanding of damage progression. The research is aimed at development of damage relationships for determination of residual life of aged electronics and assessment of design margins instead of life prediction of new components. The prognostic indicators presented in this paper, can be used for health monitoring of electronic assemblies.

Product level assessment of drop and shock reliability relies heavily on experimental test methods. Prediction of drop and shock survivability is largely beyond the state-of-art. However, the use of experimental approach to test out every possible design variation, and identify the one that gives the maximum design margin is often not feasible because of product development cycle time and cost constraints. Presently, one of the primary methodologies for evaluating shock and vibration survivability of electronic packaging is the JEDEC drop test method, JESD22-B111 which tests board-level reliability of packaging. However, packages in electronic products may be subjected to a wide-array of boundary conditions beyond those targeted in the test method. In this paper, a failure-envelope approach based on wavelet transforms and damage proxies has been developed to model drop and shock survivability of electronic packaging. Data on damage progression under transient-shock and vibration in both 95.5Sn4.0Ag0.5Cu and 63Sn37Pb ball-grid arrays has been presented. Component types examined include &mdash; flex-substrate and rigid substrate ball-grid arrays. Dynamic measurements like acceleration, strain and resistance are measured and analyzed using high-speed data acquisition system capable of capturing insitu strain, continuity and acceleration data in excess of 5 million samples per second. Ultra high-speed video at 150,000 fps per second has been used to capture the deformation kinematics. The concept of relative damage index has been used to both evaluate and predict damage progression during transient shock. The failure-envelope provides a fundamental basis for development of component integration guidelines to ensure survivability in shock and vibration environments at a userspecified confidence level. The approach is scalable to application at system-level. Explicit finite-element models have been developed for prediction of shock survivability based on the failure envelope. Model predictions have been correlated with experimental data for both leaded and leadfree ball-grid arrays.

Lead free soldering is replacing tin lead soldering in electronics manufacturing at a mixed pace. The International Printed Circuits (IPC) society estimates that in 2005 over 50% of all Japanese soldering was lead free while North American electronics manufacturing used only 7% lead free solder. The 2006 European Union requirements of lead free and certain US requirements will certainly require more lead free application in the near future. While the move to lead free solder will grow over the next five years, there are many applications where lead free solder will not be required or practical. Many of these applications involve harsh environment electronics. However, these same applications may be forced to use packages designed for lead-free soldering due to component availability. This paper investigates the impact on component reliability of using lead-free solder (SnAgCu) balls for plastic ball grid array packages with SnPb (63/37) solder. The component reliability for these packages is investigated for high temperature applications (-40C to +125C). Also investigated is the impact of different printed circuit board platings on component reliability.

The use of chip-scale packages (CSPs) has expanded rapidly, particularly in portable electronic products. Many CSP designs will meet the thermal cycle or thermal shock requirements for these applications. However, mechanical shock (drop) and bending requirements often necessitate the use of underfills to increase the mechanical strength of the CSP-to-board connection. Capillary flow underfills processed after reflow provide the most common solution to improving mechanical reliability. However, capillary underfill dispense, flow, and cure steps and the associated equipment add cost and complexity to the assembly process. Corner bonding provides an alternate approach. Dots of underfill are dispensed at the four corners of the CSP site after solder paste print but before CSP placement. During reflow, the underfill cures, providing mechanical coupling between the CSP and the board at the corners of the CSP. Since only small areas of underfill are used, board dehydration is not required. This paper examines the manufacturing process for corner bonding including dispense volume, CSP placement, and reflow. Drop test results are then presented. A conventional, capillary process was used for comparison of drop test results. Test results with corner bonding were intermediate between complete capillary underfill and nonunderfilled CSPs. Finite-element modeling results for the drop test are also included.

In this paper, a methodology for prognostication-of-electronics has been developed for accurate assessment of residual life in a deployed electronic components, and determination of damage-state in absence of macro-indicators of failure. Proxies for leading indicators-of-failure have been identified and correlated with damage progression under thermo-mechanical loads. Examples of proxies include &mdash; micro-structural evolution characterized by average phase size and intermetallic growth rate in solder interconnects. Validity of damage proxies has been investigated for both 63Sn37Pb leaded and SnAgCu leadfree electronics. Structures examined include &mdash; plastic ball grid array format electronic and MEMS Packages and discrete devices assembled with FR4-06 laminates. Focus of the research presented in this paper is on interrogation of the aged material's damage state and enhancing the understanding of damage progression. The research is aimed at development of damage relationships for determination of residual life of aged electronics and assessment of design margins instead of life prediction of new components. The prognostic indicators presented in this paper, can be used for health monitoring of electronic assemblies.

Fine-pitch ball grid arrays (BGAs) and underfills have been used in benign office environments and wireless applications for a number of years, however their reliability in harsh environments is not well understood. In this work, the design guidelines development effort for deployment of fine-pitch ball-grid array packages in the harsh environments have been presented. Guidelines are targeted toward government contractors, OEMs, and third party contract manufacturers who intend to select part architectures and board designs based on specified mission requirements. The guidelines are intended as an aid for understanding the sensitivity of component eliability to geometry, package architecture, material properties and board attributes in ifferent thermal environments in order to uantitatively evaluate the impact of these parameters on the component reliability. The intent is to develop a tool for doing tradeoffs between geometry, materials and quantitatively evaluating the impact on reliability. ensitivity relations for geometry, materials, and architectures based on statistical models and failure mechanics based closed form models have been developed. Convergence between tatistical model sensitivities and failure mechanics based sensitivities has been demonstrated. Predictions of sensitivities have been validated against experimental test data.

Traditional reflow profiles for lead-free soldering typically require longer processing times due to elevated peak temperatures and flux activation times defined by solder paste suppliers. These profiles become particularly challenging when a wide variety of packaging types are integrated within a single circuit design. Further difficulty is presented when product designs with high thermal mass, such as heat slugs and metal substrates, are processed. These designs create large thermal gradients throughout a circuit assembly and add further complexity to finding an "optimal" profile window. All of these issues create a significant increase in reflow processing times for lead-free soldering. This paper investigates these increased processing times required for high volume manufacturing of lead-free electronics. A study of typical process capacity and real throughput capacity is presented. The study evaluates high volume electronics manufacturing ranging from small circuit assemblies (e.g. cell phone) to large circuit assemblies (e.g. automotive and computers) and investigates a series of "best" reflow profiles to accelerate the standard lead-free process window to meet a targeted manufacturing capacity using an automated profiling system. A test vehicle is then fabricated using this defined process window and tested for quality (solder voiding and appearance) and solder joint reliability (accelerated life testing). The designed test vehicle includes components from a large physical distribution including: small and large BGAs, QFNs, and any type discrete components. During assembly, virtual profiling is used to document any deviations to the process profile window. The quality and reliability data are presented within this publication and failure analysis is included to determine the capability of this proposed profile. When employed, this profiling strategy allows many manufacturers to reduce the processing time for reflowing lead-free circuit assemblies without significant lost in manufacturing quality or reliability. Furthermore, this study provides a sound understanding and limitations for using accelerated profiling speeds for lead-free soldering applications.

Reliable, consistent, and comprehensive material property data are needed for microelectronic encapsulants for the purpose of mechanical design, reliability assessment, and process optimization of electronic packages. In our research efforts, the mechanical responses of several different capillary flow snap cure underfill encapsulants are being characterized. A microscale tension-torsion testing machine has been used to evaluate the uniaxial tensile stress-strain behavior of underfill materials as a function of temperature and strain rate. A critical step to achieving accurate experimental results has been the development of a sample preparation procedure that produces mechanical test specimens that reflect the properties of true underfill encapsulant layers. In the developed method, 75-125 m (3-5 mil) thick underfill uniaxial tension specimens are dispensed and cured using production equipment and the same processing conditions as those used with actual flip chip assemblies. A three parameter hyperbolic tangent empirical model has been shown to provide accurate fits to the observed underfill nonlinear stress-strain behavior over a range of temperatures and strain rates. In addition, the first measurements of underfill mechanical behavior at cryogenic temperatures have been made.

In this work, we report on our efforts to develop ultra-high reliability flip chip on laminate assemblies for deployment in harsh thermal cycling environments characteristic of ground and aerospace vehicles (e.g. -55 to 150 °C). Reliability enhancement has been achieved through the use of a novel low expansion, high stiffness, and relatively low cost laminate substrate material that virtually eliminates CTE mismatches between the silicon die and top layer PCB interconnect. The utilized laminate features a sandwich construction that contains standard FR-406 outer layers surrounding a low expansion high thermal conductivity carbon fiber-reinforced composite core (STABLCOR). Through both experimental testing and modeling, we have demonstrated that robust flip chip assemblies can be produced that illustrate ultra-high solder joint reliability during thermal cycling and extremely low die stresses. Liquid to liquid thermal shock testing has been performed on test assemblies incorporating daisy chain test die, and piezoresistive test chips have been used to characterize temperature dependent die stresses. In both sets of experiments, results obtained using the hybrid PCB laminate with FR-406 outer layers and carbon fiber core have been compared to those obtained with more traditional glass-epoxy laminate substrates including FR-406 and NELCO 4000-13. Nonlinear finite element modeling results for the low expansion flip chip on laminate assemblies have been correlated with the experimental data. Unconstrained thermal expansion measurements have also been performed on the hybrid laminate materials using strain gages to demonstrate their low CTE characteristics. Other experimental testing has demonstrated that the new laminate successfully passes toxicity, flammability, and vacuum stability testing as required for pressurized and un-pressurized space applications.

Underfill encapsulation is used with flip chip die assembled to laminate substrates to distribute and minimize the solder joint strains, thus improving thermal cycling fatigue life. Any delaminations that occur at the underfill/die interface will propagate to the neighboring solder bumps and lead to solder joint fatigue and failure. The onset and propagation of delaminations in flip chip assemblies exposed to thermal cycling are governed by the cyclic stresses and damage occurring at the underfill to die interface. For this reason, underfills are optimized by increasing their adhesion strength, interfacial fracture toughness, and resistance to thermal aging. In this work, we have sought to develop a fundamental understanding of delamination initiation and growth in flip chip assemblies through simultaneous characterization of the stress and delamination states at the die to underfill interface. Mechanical stresses on the device side of the flip chip die have been measured using special (111) silicon stress test chips containing piezoresistive sensor rosettes that are capable of measuring the complete three-dimensional silicon surface stress state in the silicon (including the interfacial shear and normal stresses at the die to underfill interface). By continuous monitoring of the sensor resistances, the die surface stresses were measured during post-assembly thermal cycling environmental testing from -40 to 125 C. With this approach, the stress distributions across the chip, and the stress variations at particular locations at the die to underfill interface have been interrogated for the entire life of the flip chip assembly. In order to correlate the stress changes at the sensor sites with delamination onset and propagation, CSAM evaluation of the test assemblies was performed after every 125 thermal cycles. A total of 75 flip chip assemblies with 3 different underfills have been evaluated. For each assembly, the complete histories of three-dimensional die surface stresses and delamination propagation have been recorded versus the number of thermal cycles. With this approach, we have been able to identify the stress histories that lead to delamination initiation for each underfill encapsulant, and the variation of the stresses that occur before and during delamination propagation. The progressions of stress and delamination have been mapped across the entire surface of the die, and a series of stress/delamination videos have been produced. One of the most important discoveries is that the shear stresses occurring at the corners of flip chip die have been demonstrated to be a suitable proxy for prognostic determination of future delamination initiations and growth.

Minimizing device side die stresses is especially important when multiple copper/low-k interconnect redistribution layers are present. Mechanical stress distributions in packaged silicon die resulting during assembly or nvironmental testing can be accurately characterized using test chips incorporating integral piezoresistive sensors. In this paper, measurements of thermally induced stresses in flip chip on laminate assemblies are presented. Transient die stress measurements have been made during underfill cure, and the room temperature die stresses in final cured assemblies have been compared for several different underfill encapsulants. In addition, stress variations have been monitored in the assembled flip chip die as the test boards were subjected to slow temperature changes from 40 to +150 C. Using these measurements and ongoing numerical simulations, valuable insight has been gained on the effects of assembly variables and underfill material properties on the reliability of flip chip packages.

Modeling tools and techniques for assessment of component reliability in extreme environments are scarce. Previous studies have focused on development of modeling tools at sub-scale or component level. The tools are often available only in an offline manner for decision support and risk assessment of advanced technology programs. There is need for a turn key approach, for making trade-offs between geometry and materials and quantitatively evaluating the impact on reliability. Application of flip-chip assemblies and underfills in benign office environments and wireless applications is not new, however their reliability in extreme environments is still not very well understood. In the current work, the decision-support models for deployment of flip-chip devices under various harsh thermal environments have been presented. The current work is targeted towards government contractors, OEMs, and 3rd party contract manufacturers who intend to select part architectures and board designs based on specified mission requirements. In addition, the mathematical models presented in this paper provide decision guidance for smart selection of component packaging technologies and perturbing presentlydeployed product designs for minimal risk insertion of new packaging technologies. The models serve as an aid for understanding the sensitivity of component reliability to geometry, package architecture, material properties and board attributes to enable educated selection of appropriate device formats. The perturbation approach presented in this paper enables higher-accuracy model prediction by perturbing known accelerated-test data-sets using models, using factors which quantify the sensitivity of reliability to various design, material, architecture and environmental parameters. The models are based on a combination of statistics and failure mechanics. In addition, parameter interaction effects, which are often ignored in closed form modeling, have been incorporated in the proposed hybrid approach. The statistics models are based on accelerated test data in harsh environments, while failure mechanics models are based on damage mechanics and material constitutive behavior. Convergence between statistical model sensitivities and failure mechanics based model sensitivities has been demonstrated. Predictions of sensitivities have also been validated against the experimental test data.

Silica particles are used as a filler material in electronic underfills to reduce coefficient of thermal expansion of the underfill-epoxy matrix. In traditional underfills, the size of silica particles is in the micrometer range. Reduction in particle sizes into the nanometer range has the potential of attaining higher volume fraction particle loading in the underfills and greater control over underfill properties for higher reliability applications. Presently, no-flow underfills have very low or no filler content because micron-size filler particles hinder solder joint formation. Nano-silica underfills have the potential of attaining higher filler loading in no-flow underfills without hindering solder interconnect formation [Shi 1999, Liu 2001]. In this paper, property prediction models based on representative volume element (RVE) and modified random spatial adsortion have been developed. The models can be used for development of nano-silica underfills with desirable thermo-mechanical properties. Temperature dependent thermo-mechanical properties of nano-underfills have been evaluated and correlated with models in a temperature range of -175°C to +150 °C. Properties investigated include, temperature dependent stress-strain, creep and stress relaxation behavior. Nano-underfills on 63Sn37Pb eutectic and 95.5Sn3.5Ag1.0Cu leadfree flip-chip devices have been subjected to thermal shock tests in the range of -55 to 125°C and -55 to 150°C respectively. The trade-offs between using nano-fillers instead of micron-fillers on thermo-mechanical properties and reliability has been benchmarked.

The underhood automotive environment is harsh and current trends in the automotive electronics industry will be pushing the temperature envelope for electronic components. The desire to place engine control units on the engine and transmission control units either on or in the transmission will push the ambient temperature above 125 C. However, extreme cost pressures, increasing reliability demands (10 year/241 350 m) and the cost of field failures (recalls, liability, customer loyalty) will make the shift to higher temperatures occur incrementally. The coolest spots on engine and in the transmission will be used. These large bodies do provide considerable heat sinking to reduce temperature rise due to power dissipation in the control unit. The majority of near term applications will be at 150 C or less and these will be worst case temperatures, not nominal. The transition to X-by-wire technology, replacing mechanical and hydraulic systems with electromechanical systems will require more power electronics. Integration of power transistors and smart power devices into the electromechanical actuator will require power devices to operate at 175 C to 200 C. Hybrid electric vehicles and fuel cell vehicles will also drive the demand for higher temperature power electronics. In the case of hybrid electric and fuel cell vehicles, the high temperature will be due to power dissipation. The alternates to high-temperature devices are thermal management systems which add weight and cost. Finally, the number of sensors in vehicles is increasing as more electrically controlled systems are added. Many of these sensors must work in high-temperature environments. The harshest applications are exhaust gas sensors and cylinder pressure or combustion sensors. High-temperature electronics use in automotive systems will continue to grow, but it will be gradual as cost and reliability issues are addressed. This paper examines the motivation for higher temperature operation, the packaging limitations even at 125 C with newer package styles and concludes with a review of challenges at both the semiconductor device and packaging level as temperatures push beyond 125 C.

In this study, the effect of metal-backed boards on the interconnect reliability has been evaluated. Previous studies on electronic reliability for automotive environments have addressed the damage mechanics of solder joints in plastic ball-grid arrays on non-metal backed substrates [Lall et. al 2003, Syed et. al 1996, Evans et. al 1997, Mawer et. al 1999] and ceramic BGAs on non-metal backed substrates [Darveaux et. al 1992, 1995, 2000]. Other failure mechanisms investigated include &mdash; delamination of PCB from metal backing. Increased use of sensors and controls in automotive applications has resulted in significant emphasis on the deployment of electronics directly mounted on the engine and transmission. Increased shock, vibration, and higher temperatures necessitate the fundamental understanding of damage mechanisms which will be active in these environments. Electronics typical of office benign environments uses FR-4 printed circuit boards. Automotive application typically use high glass-transition temperature laminates such as FR4-06 glass/epoxy laminate material (Tg = 164.9°C). In application environments, metal-backing of printed circuits boards is being targeted for thermal dissipation, mechanical stability and interconnections reliability. The test vehicle is a metal backed FR4-06 laminate. The printed circuit board has an aluminum metal backing, attached with pressure sensitive adhesive (PSA). Component architectures tested include &mdash; plastic ball grid array devices, C2BGA devices, QFN, and discrete resistors. Reliability of the component architectures has been evaluated for HASL. Crack propagation and intermetallic thickness data has been acquired as a function of cycle count. Reliability data has been acquired on all these architectures. Material constitutive behavior of PSA has been measured using uniaxial test samples. The measured constitutive behavior has been incorporated into non-linear finite element simulations. Predictive models have been developed for the dominant failure mechanisms for all the component architectures tested.

Drop-induced failures are most dominant in portable electronic products. In this study, explicit finite element models have been used to study the transient dynamics of printed circuit boards during drop from 6ft. Methodologies for modeling components using smeared property formulations have been investigated. Reduced integration element formulations examined include &mdash; shell and solid elements. Model predictions have been validated with experimental data. Results show that models with smeared properties can predict transient-dynamic response of board assemblies in drop-impact, fairly accurately. High-speed data acquisition system has been used to capture in-situ strain, continuity and acceleration data in excess of 1 million samples per second. Ultra high-speed video at 40,000 fps per second has been used to capture the deformation kinematics. Component types examined include &mdash; plastic ball-grid arrays, tape-array BGA, QFN, and C2BGA. Model predictions have been correlated with experimental data. Impact of experimental error sources on model correlation with experiments also has been investigated

The current state-of-art in managing system reliability is geared towards the development of life-prediction models for un-aged pristine materials under known loading conditions based on relationships such as the Paris's Power Law [Paris, et. al 1960 1961], Coffin-Manson Relationship [Coffin 1954; Tavernelli, et. al. 1959; Smith, et. al. 1964; Manson, et. al. 1964] and the S-N Diagram. There is need for methods and processes which will allow interrogation of complex systems and sub-systems to determine the remaining useful life prior to repair or replacement. This capability of determination of material or system state is called "prognosis". In this paper, a methodology for prognosis-of-electronics has been demonstrated with data of leading indicators of failure for accurate assessment of product damage significantly prior to appearance of any macro-indicators of damage. Proxies for leading indicators of failure have been developed including &mdash; micro-structural evolution characterized by average phase size and interfacial stresses at interface of silicon structures. Structures examined include &mdash; electronics package, MEMS Packages and interconnections on a metal backed printed circuit board typical of electronics deployed in harsh environments. Since, an aged material knows its state the research presented in this paper focuses on enhancing the understanding of material damage to facilitate proper interrogation of material state. Mathematical relationship has been developed between phase growth rate and time-to-1-percent failure to enable the computation of damage manifested and a forward estimate of residual life.

To achieve adequate solder joint reliability when using small Ball Grid Array (BGA) components, it is often necessary to use underfill encapsulants. Underfills also have an important role in heat transfer from die to board. In this study, the impact of underfill materials on the thermal performance of BGA's was investigated and quantified. A fixture and a fully automated data acquisition system were developed to measure the junction to case thermal resistance in underfilled BGAs assembled to laminate substrates. In the developed apparatus, the back of the FR-4 printed circuit boards (PCBs) were instrumented with thermocouples, and then maintained at a constant temperature using a water bath. Special thermal test chips with onboard heaters and diode temperature sensors were encapsulated in the BGAs so that the power dissipation could be controlled and the die surface temperature measured. Using the described system, several studies were completed including the rating of the thermal performance of several underfill materials and the examination of various thermal via designs in the PCBs. A 10-30% reduction in the thermal resistance was observed for underfilled components. After initial testing, the samples were subjected to thermal cycling (-40 to 125 °C), to evaluate thermal performance degradation (due to cracking of the thermal solder balls, underfill delaminations, and underfill material property changes). Steady state and transient finite element models of the thermal BGA geometries have been correlated to the thermal resistance measurements.

Reliable, consistent, and comprehensive material property data are needed for microelectronic encapsulants for the purpose of mechanical design, reliability assessment, and process optimization of electronic packages. In our research efforts, the mechanical responses of several different capillary flow snap cure underfill encapsulants are being characterized. A microscale tension-torsion testing machine has been used to evaluate the uniaxial tensile stress-strain behavior of underfill materials as a function of temperature, strain rate, specimen dimensions, humidity, thermal cycling exposure, etc. A critical step to achieving accurate experimental results has been the development of a sample preparation procedure that produces mechanical test specimens that reflect the properties of true underfill encapsulant layers. In the developed method, 75-125 ~tm (3- 5 rail) thick underfill uniaxial tension specimens are dispensed and cured using production equipment and the same processing conditions as those used with actual flip chip assemblies. Although several underfills have been examined, this work features results for the mechanical response of a single typical capillary flow snap cure underfill. A three parameter hyperbolic tangent empirical model has been shown to provide accurate fits to the observed underfill nonlinear stress-strain behavior over a range of temperatures and strain rates.

Fine-Pitch BGAs and underfills have been used in benign office environments and wireless applications for a number of years, however their reliability in harsh environments is not well understood. In this work, the design guidelines development effort for deployment of fine-pitch ball-grid array packages in the harsh environments have been presented. Guidelines are targeted towards government contractors, OEMs, and 3rd party contract manufacturers who intend to select part architectures and board designs based on specified mission requirements. The guidelines are intended as an aid for understanding the sensitivity of component reliability to geometry, package architecture, material properties and board attributes in different thermal environments in order to quantitatively evaluate the impact of these parameters on the component reliability. The intent is to develop a tool for doing trade-offs between geometry, materials and quantitatively evaluating the impact on reliability. Sensitivity relations for geometry, materials, and architectures based on statistical models and failure mechanics based closed form models have been developed. Convergence between statistical model sensitivities and failure mechanics based sensitivities has been demonstrated. Predictions of sensitivities have been validated against experimental test data.

Mechanical stress distributions in packaged silicon die that have resulted during assembly or environmental testing can be accurately characterized using test chips incorporating integral piezoresistive sensors. In this paper, measurements of thermally induced stresses in flip chip on laminate assemblies are presented. Transient die stress measurements have been made during underfill cure, and the room temperature die stresses in final cured assemblies have been compared for several different underfill encapsulants. In addition, stress variations have been monitored in the assembled flip chip die as the test boards were subjected to slow temperature changes from -40 to +150 °C. Using these measurements and ongoing numerical simulations, valuable insight has been gained on the effects of assembly variables and underfill material properties on the reliability of flip chip packages.

The solder joint reliability of ceramic chip resistors assembled to laminate substrates has been a long time concern for systems exposed to harsh environments such as those found in automotive and aerospace applications. This is due to a combination of the extreme temperature excursions experienced by the assemblies along with the large coefficient of thermal expansion mismatches between the alumina bodies of the chip resistors and the glass-epoxy composites of the printed circuit boards (PCBs). These reliability challenges are exacerbated for components with larger physical size (distance to neutral point) such as the 2512 resistors used in situations where higher voltages and/or currents lead to power dissipations up to 1 Watt. In this work, the thermal cycling reliability of several 2512 chip resistor lead free solder joint configurations has been investigated. In an initial study, a comparison has been made between the solder joint reliabilities obtained with components fabricated with both tin-lead and pure tin solder terminations. In the main portion of the reliability testing, two temperature ranges (-40 to 125 °C and -40 to 150 °C) and five different solder alloys have been examined. The investigated solders include the normal eutectic SnAgCu (SAC) alloy recommended by earlier studies (95.5Sn-3.8Ag-0.7Cu), and three variations of the lead free ternary SAC alloy that include small quaternary additions of bismuth and indium to enhance fatigue resistance. For each configuration, thermal cycling failure data has been gathered and analysed using two-parameter Weibull models to rank the relative material performances. The obtained lead free results have been compared to data for standard 63Sn-37Pb joints. In addition, a second set of thermally cycled samples was used for microscopy studies to examine crack propagation, changes in the microstructure of the solders, and intermetallic growth at the solder to PCB pad interfaces.

Migration to lead free solders is underway in the electronics industry for several reasons including pending legislation, environmental concerns, and desire to provide market differentiations. Reliable, consistent, and comprehensive material property data are needed for the solders used in electronic packaging for the purpose of mechanical design, reliability assessment, and process optimization. In this work, the mechanical response of a typical Sn-Ag-Cu lead free solder alloy has been characterized in uniaxial tension. A microscale tension-torsion testing machine has been used to evaluate the uniaxial tensile stress-strain and creep behavior of solder materials as a function of temperature. A critical step to achieving accurate experimental results has been the development of a sample preparation procedure that produces mechanical test specimens that reflect the microstructure and properties of true electronic package solder joints. An elastic-plastic model has been shown to provide accurate fits to the observed nonlinear stress-strain behavior over a range of temperatures and strain rates. In addition, creep behaviors of lead-free solder have been recorded at different temperatures and stress levels. Further experimental tests are ongoing. The measurements completed in this study will provide the basic mechanical property data needed for performing accurate finite element analyses of various lead free electronic assemblies.

The solder joint reliability of ceramic chip resistors assembled to laminate substrates has been a long time concern for systems exposed to harsh environments such as those found in automotive and aerospace applications. This is due to a combination of the extreme temperature excursions experienced by the assemblies along with the large coefficient of thermal expansion mismatches between the alumina bodies of the chip resistors and the glass-epoxy composites of the printed circuit boards (PCBs). These reliability challenges are exacerbated for components with larger physical size (distance to neutral point) such as the 2512 resistors used in situations where higher voltages and/or currents lead to power dissipations up to 1 Watt. In this work, the thermal cycling reliability of several 2512 chip resistor lead free solder joint configurations has been investigated. In an initial study, a comparison has been made between the solder joint reliabilities obtained with components fabricated with both tin-lead and pure tin solder terminations. In the main portion of the reliability testing, two temperature ranges (-40 to 125 °C and -40 to 150 °C) and five different solder alloys have been examined. The investigated solders include the normal eutectic SnAgCu (SAC) alloy recommended by earlier studies (95.5Sn-3.8Ag-0.7Cu), and three variations of the lead free ternary SAC alloy that include small quaternary additions of bismuth and indium to enhance fatigue resistance. For each configuration, thermal cycling failure data has been gathered and analysed using two-parameter Weibull models to rank the relative material performances. The obtained lead free results have been compared to data for standard 63Sn-37Pb joints. In addition, a second set of thermally cycled samples was used for microscopy studies to examine crack propagation, changes in the microstructure of the solders, and intermetallic growth at the solder to PCB pad interfaces.

The current state-of-art in managing system reliability is geared towards the development of predictive models for un-aged pristine materials. Present state of art allows the prediction of time-to-failure for a pristine material under known loading conditions based on relationships such as the Paris's Power Law [Paris, et. al 1960 1961], Coffin-Manson Relationship [Coffin 1954; Tavernelli, et. al. 1959; Smith, et. al. 1964; Manson, et. al. 1964] and the S-N Diagram. There is need for methods and processes which will allow interrogation of complex systems and sub-systems to determine the remaining useful life prior to repair or replacement. This capability of determination of material or system state is called "prognosis". In this paper, a methodology for prognostication-ofelectronics has been demonstrated with data of leading indicators of failure for accurate assessment of product damage significantly prior to appearance of any macroindicators of damage. Proxies for leading indicators of failure have been identified. Examples of proxies include &mdash; micro-structural evolution characterized by average phase size and correlated to time and equivalent creep strain rate, and stresses at interface of silicon structures. Structures examined include &mdash; electronics package, MEMS Package and interconnections. The test vehicle includes packages that have been mounted on a metal backed printed circuit board typical of electronics deployed in harsh environments. In application environment, the metal-backing provides thermal dissipation, mechanical stability and interconnections reliability. Since, an aged material knows its state the research presented in this paper focuses on enhancing the understanding of material damage to facilitate proper interrogation of material state.

Increased use of sensors and controls in automotive applications has resulted in significant emphasis on the deployment of electronics directly mounted on the engine and transmission. Increased shock, vibration, and higher temperatures necessitate the fundamental understanding of damage mechanisms which will be active in these environments. Electronics typical of office benign environments uses FR-4 printed circuit boards. Automotive application typically use high glass-transition temperature laminates such as FR-406 glass/epoxy laminate material (Tg = 164.9°C). In application environments, metal backing of printed circuits boards is being targeted for thermal dissipation, mechanical stability and interconnections reliability. There have been several studies on electronic reliability for automotive environments [Lall 2003, Syed 1996, Evans 1997, Mawer 1999]. However, none of the previous studies address the damage mechanics of electronics on metal backed substrates. Published data on crack propagation has targeted ceramic BGAs [Darveaux 1992, 1995, 2000] and plastic BGAs on glass-epoxy laminate [Lall 2003]. In this work, the effect of metal-backed boards on the interconnect reliability will be evaluated. Other failure mechanisms investigated include &mdash; delamination of PCB from metal backing. The test vehicle is a metal backed FR4-06 laminate. Metal backings investigated include &mdash; aluminum and beryllium copper. Three adhesive have been investigated for metal backing including &mdash; arlon, pressure sensitive adhesive and pre-preg. The use of conformal coating for reliability improvement has also been investigated. Component architectures tested include &mdash; plastic ball grid array devices, C2BGA devices, QFN, and discrete resistors. Reliability of the component architectures has been evaluated for HASL and electroless Ni/Au finishes. Crack propagation and intermetallic thickness data has been acquired as a function of cycle count. Reliability data has been acquired on all these architectures. Material constitutive behavior of arlon and PSA has been measured using uni-axial test samples. The measured constitutive behavior has been incorporated into non-linear finite element simulations. Predictive models have been developed for the dominant failure mechanisms for all the component architectures tested.

Single frequency vibration tests were used to induce fretting corrosion in tin alloy plated contacts. The samples used in this study were connectors consisting of 25 pairs of mated pin and socket contacts. Experimental results for a variety of vibration levels, frequencies, and wiring tie-off lengths are presented. The experiments consisted of running a series of vibration tests at each frequency where the excitation level was stepped through a range of g-levels. During each test run contact resistance was monitored as a performance characteristic. The results exhibit threshold behavior at each frequency for the onset of fretting degradation. Typically a plateau region was observed where similar g-levels produced similar fretting rates. It was also found that outside the plateau region the g-levels varied according to the dynamic behavior of the mechanical system. In addition, a transfer matrix model was used to analyze these results. An empirical fit of the data correlated well with the model when damping was used. This analysis revealed the importance of the bending moment induced at the contact interface as a result of excitation levels and tie-off configurations. Consequently, it is concluded that dynamic response of the mechanical system under various g-levels and tie off configurations can greatly impact the performance of a connector system subjected to vibration stresses.

The paper describes an optimization model for allocating solder-paste printing inspection that explicitly considers the economic tradeoff between board yield and inspection accuracy. The paper also shows that the use of a heuristic solution method for solving the post-printing inspection allocation model is effective and efficient for high-volume electronics manufacturing. The model has been developed using real production and visual inspection data provided by a high-volume electronics manufacturer located in Huntsville, AL. In addition, randomly generated problems are used to evaluate the performance of the proposed heuristic. Results from a large case study show that when compared with a full post-printing inspection, the heuristic approach provides a solution that can increase the total expected gains by 15%.

This paper describes an optimization model for allocating inspection efforts at each stage in a serial multi-stage assembly line. The model explicitly considers the economic tradeoffs between product yield and inspection accuracy. The paper also shows that the use of a heuristic solution method, simulated annealing, is effective and efficient for solving the inspection allocation model. Problem instances have been developed using real production and visual inspection data provided by a local high-volume electronics manufacturer. In addition, randomly generated problems are used to evaluate the performance of the proposed heuristic.

Increased use of sensors and controls in automotive applications has resulted in significant emphasis on the deployment of electronics directly mounted on the engine and transmission. Increased shock, vibration, and higher temperatures necessitate the fundamental understanding of damage mechanisms which will be active in these environments. Electronics typical of office benign environments uses FR-4 printed circuit boards. Automotive application typically use high glass-transition temperature laminates such as FR-406 glass/epoxy laminate material (Tg = 164.9 °C). In application environments, metal backing of printed circuits boards is being targeted for thermal dissipation, mechanical stability and interconnections reliability. There have been several studies on electronic reliability for automotive environments [Lall 2003, Syed 1996, Evans 1997, Mawer 1999]. However, none of the previous studies address the damage mechanics of electronics on metal backed substrates. Published data on crack propagation has targeted ceramic BGAs [Darveaux 1992, 1995, 2000] and plastic BGAs on glass-epoxy laminate [Lall 2003]. In this work, the effect of metal-backed boards on the interconnect reliability will be evaluated. Other failure mechanisms investigated include &mdash; delamination of PCB from metal backing. The test vehicle is a metal backed FR4-06 laminate. Metal backings investigated include &mdash; aluminum and beryllium copper. Three adhesive have been investigated for metal backing including &mdash; arlon, pressure sensitive adhesive and pre-preg. The use of conformal coating for reliability improvement has also been investigated. Component architectures tested include &mdash; plastic ball grid array devices, C2BGA devices, QFN, and discrete resistors. Reliability of the component architectures has been evaluated for HASL and electroless Ni/Au finishes. Crack propagation and intermetallic thickness data has been acquired as a function of cycle count. Reliability data has been acquired on all these architectures. Material constitutive behavior of arlon and PSA has been measured using uni-axial test samples. The measured constitutive behavior has been incorporated into non-linear finite element simulations. Predictive models have been developed for the dominant failure mechanisms for all the component architectures tested.

In response to the legislative initiatives presently underway to remove lead from electronic components, an experimental study was undertaken to determine the susceptibility of lead-free electrodeposited connector finishes to metallic whisker formation, the reliability failure mode presently of greatest concern to the electronics industry. The first phase of the study included exposure of mechanically stressed electroplated finishes to thermal aging, elevated temperature / humidity, and thermal cycling conditions. The samples examined during this phase included various pure Sn, SnCu, and SnBi plating configurations. Based upon the results of these initial environmental aging studies, some of which lasted as long as 16 months, it was determined that a finish of pure Sn over Ni would be the most suitable for minimizing the likelihood of whisker formation. The second phase of the study focused on comparing the whisker susceptibility of matte Sn to bright Sn (both over a nickel barrier layer) during exposure to either thermal aging, elevated temperature / humidity, or room temperature aging conditions. The second phase samples were pre-conditioned via temperature cycling rather than mechanically induced stressing of the electrodeposit. The susceptibility of each plated finish to whisker formation has been extensively documented via a scanning electron microscopy (SEM) evaluation. The implications with respect to whisker mitigation strategies and whisker testing methodologies are also discussed.

Drop-induced failures are most dominant in portable electronic products. In this study, explicit finite element models have been used to study the transient dynamics of printed circuit boards during drop from 6ft. Methodologies for modeling components using smeared property formulations have been investigated. Reduced integration element formulations examined include &mash; shell and solid elements. Model predictions have been validated with experimental data. Results show that models with smeared properties can predict transient-dynamic response of board assemblies in drop-impact, fairly accurately. High-speed data acquisition system has been used to capture in-situ strain, continuity and acceleration data in excess of 1 million samples per second. Ultra high-speed video at 40,000 fps per second has been used to capture the deformation kinematics. Component types examined include &mdash; plastic ball-grid arrays, tape-array BGA, QFN, and C2BGA. Model predictions have been correlated with experimental data. Impact of experimental error sources on model correlation with experiments also has been investigated.

Fine-Pitch BGAs and underfills have been used in benign office environments and wireless applications for a number of years, however their reliability in harsh environments is not well understood. In this work, the design guidelines development effort for deployment of fine-pitch ball-grid array packages in the harsh environments have been presented. Guidelines are targeted towards government contractors, OEMs, and 3rd party contract manufacturers who intend to select part architectures and board designs based on specified mission requirements. The guidelines are intended as an aid for understanding the sensitivity of component reliability to geometry, package architecture, material properties and board attributes in different thermal environments in order to quantitatively evaluate the impact of these parameters on the component reliability. The intent is to develop a tool for doing trade-offs between geometry, materials and quantitatively evaluating the impact on reliability. Sensitivity relations for geometry, materials, and architectures based on statistical models and failure mechanics based closed form models have been developed. Convergence between statistical model sensitivities and failure mechanics based sensitivities has been demonstrated. Predictions of sensitivities have been validated against experimental test data.

Automotive suppliers are striving to meet the challenges of products which must be designed to include increasingly advanced features while maximizing both fuel efficiency and cist effectiveness. This change has a significant impact on engine and transmission controllers which are being forced to operate in harsher environments with higher operating temperatures. To meet these needs, automotive electronics suppliers have pursued the use of metal-back laminate (typically FR4-06) substrates. These substrates provide an opportunity for very good heat sinking and use the metal backing as part of the housing assembly. One disadvantage of this design is the detrimental impact on solder joint reliability for many component packages. While there are many issues which must be addressed before metal-backed laminate substrates are deployed into automotive applications, this paper primarily focuses on the impact on component reliability for these applications. The focus of the research within this study is threefold; to determine overall component reliability using metal-backed laminate substrates, to investigate the impact of these substrates on the reflow process, and to study the impact of an alternate plating (ENIG) on component reliability. The results of this research will aid automotive companies in designing more robust controller modules for future vehicle generations.

We report the observation of real-time, in situ, wetting and spreading dynamics for 57Bi-42Sn-1Ag solder paste on Ni-Au surfaces during melting in a scanning electron microscope. The 57Bi-42Sn-1Ag is a low melting (139 C) Pb-free eutectic alloy currently under consideration by automobile manufacturers for use in instrument displays. We find that, while there is excellent wetting of 57Bi-42Sn-1Ag solder paste on Ni-Au, there is almost no spreading. A large amount of Bi segregates to the surface of 57Bi-42Sn-1Ag solder balls during the sintering process. At melting, excessive flux outgassing and pooling are observed, several melted solder balls float on top of the flux, and substantial elemental segregation occurs during the first minutes of wetting. Neither Ni nor Au fully intermixes throughout the alloy at the interface within seconds of wetting. Bi does not move outward with the expanding alloy front. This combination of detrimental effects forms voids in the solder paste, contributes to low reliability of solder joints, and complicates the materials science at the solder-substrate interface as shown by Auger electron spectroscopy. Reliability work in progress (3000 cycles) shows that 57Bi-42Sn-1Ag on Ni-Au is less reliable than eutectic Sn-37Pb on Ni-Au for 2512 chip resistors cycled from -40 to 125 C.

Fine-Pitch BGAs and underfills have been used in benign office environments and wireless applications for a number of years, however their reliability in automotive underhood environment is not well understood. In this work, the reliability of fine-pitch PBGA packages has been evaluated in the automotive underhood environment. Experimental studies indicate that the CTE as measured by TMA typically starts to change at 10-15 C lower temperature than the Tg specified by DSC potentially extending the change in CTE well into the accelerated test envelope in the neighborhood of 125 C. High Tg substrates with glass-transition temperatures much higher than the 125 C high temperature limit are therefore not subject to the effect of high coefficient of thermal expansion close to the high temperature of the accelerated test. Darveaux's damage relationships were derived on CBGA assemblies, with predominantly SMD pads and 62Sn36Pb2Ag solder. In addition to significant differences in the crack propagation paths for the two pad constructions, SMD pads fail significantly faster than NSMD pads in thermal fatigue. The thermal mismatch on CBGA's is much larger than PBGA assemblies. Crack propagation in CBGA's is often observed predominantly on the package side as opposed to both package and board side for PBGAs. In the present study, crack propagation data has been acquired on assemblies with 15 mm, 17 mm, and 23 mm size plastic BGAs with NSMD pads and 63Sn37Pb on high-Tg printed circuit boards. The data has been benchmarked against Darveaux's data on CBGA assemblies. Experimental matrix also encompasses the effect of BT substrate thickness on reliability. Damage constants have been developed and compared against existing Darveaux Constants. Prediction error has been quantified for both sets of constants.

The solder joint reliability of ceramic chip resistors assembled to laminate substrates has been a long time concern for systems exposed to harsh environments such as those found in automotive and aerospace applications. This is due to a combination of the extreme temperature excursions experienced by the assemblies along with the large coefficient of thermal expansion mismatches between the alumina bodies of the chip resistors and the glass-epoxy composites of the printed circuit boards (PCBs). These reliability challenges are exacerbated for components with larger physical size (distance to neutral point) such as the 2512 resistors used in situations where higher voltages and/or currents lead to power dissipations up to 1 Watt. In this work, the thermal cycling reliability of several 2512 chip resistor lead free solder joint configurations has been investigated. In an initial study, a comparison has been made between the solder joint reliabilities obtained with components fabricated with both tin-lead and pure tin solder terminations. In the main portion of the reliability testing, two temperature ranges (-40 to 125 C and -40 to 150 C) and five different solder alloys have been examined. The investigated solders include the normal eutectic SnAgCu (SAC) alloy recommended by earlier studies (95.5Sn-3.8Ag-0.7Cu), and three variations of the lead free ternary SAC alloy that include small quaternary additions of bismuth and indium to enhance fatigue resistance. For each configuration, thermal cycling failure data has been gathered and analysed using two-parameter Weibull models to rank the relative material performances. The obtained lead free results have been compared to data for standard 63Sn-37Pb joints. In addition, a second set of thermally cycled samples was used for microscopy studies to examine crack propagation, changes in the microstructure of the solders, and intermetallic growth at the solder to PCB pad interfaces.

Fine-Pitch BGAs and underfills have been used in benign office environments and wireless applications for a number of years, however their reliability in automotive underhood environment is not well understood. In this work, the reliability of fine-pitch PBGA packages has been evaluated in the automotive underhood environment. Experimental studies indicate that the CTE as measured by TMA typically starts to change at 10-15°C lower temperature than the Tg specified by DSC potentially extending the change in CTE well into the accelerated test envelope in the neighborhood of 125°C. High Tg substrates with glass-transition temperatures much higher than the 125°C high temperature limit are therefore not subject to the effect of high coefficient of thermal expansion close to the high temperature of the accelerated test. Darveaux's damage relationships [1992, 1995, 2000] were derived on CBGA assemblies, with predominantly SMD pads and 62Sn36Pb2Ag solder. In addition to significant differences in the crack propagation paths for the two pad constructions, SMD pads fail significantly faster than NSMD pads in thermal fatigue. The thermal mismatch on CBGA's is much larger than PBGA assemblies. Crack propagation in CBGA's is often observed predominantly on the package side as opposed to both package and board side for PBGAs. In the present study, crack propagation data has been acquired on assemblies with 15 mm, 17 mm, and 23 mm size plastic BGAs with NSMD pads and 63Sn37Pb on high-Tg printed circuit boards. The data has been benchmarked against Darveaux's data on CBGA assemblies. Experimental matrix also encompasses the effect of BT substrate thickness on reliability. Damage constants have been developed and compared against existing Darveaux Constants. Prediction error has been quantified for both sets of constants.

Reduction in size of portable products such as cellular phones and camcorders has led to the miniaturization of integrated circuit packages. Fine-pitch BGA (FBGA) packages has been gaining its popularity due to compact in size and relatively low costing. With further down-sizing in package height, reliability issues like die cracking and warpage have surfaced as potential failures. Die cracks results in malfunction of an IC package, while the latter causes difficulty in board surface mounting. In this study, effects of package height on the die stress and warpage have been assessed by FEA. With overmold height ranging from 0.4~0.6mm and substrate from 0.16~0.32mm thick, the Overall Package Thickness coding from "T" (1.00<A<=1.20mm) to "W" (0.65<A<=0.80mm) are being analyzed. Results revealed that die stress and warpage decreases with increase in overmold thickness. However, an increment in the substrate thickness constituted to a rise in die stress and warpage. It was found that "top clearance" (distance between active die side and package top) of the package contributed to different trends in die stresses. Trends of results in varying the package and die sizes are also being investigated. The findings have provided guidelines for in-house designers in containing possible failures in FBGA packages.

Mechanical stress distributions in packaged silicon die that have resulted during assembly or environmental testing can be accurately characterized using test chips incorporating integral piezoresistive sensors. In this paper, an overview of recent measurements made in flip chip on laminate assemblies with (111) silicon test chips is presented. Transient die stress measurements have been made during underfill cure, and the room temperature die stresses in final cured assemblies have been compared for several different underfill encapsulants. The experimental stress measurements in the flip chip samples were then correlated with finite element predictions for the tested configurations. In addition, stress variations have been monitored in the assembled flip chip die as the test boards were subjected to slow temperature changes from -40 to +150 °C. Finally the stress variations occurring during thermal cycling from -40 to +125 °C have been characterized. These measurements have been correlated with the delaminations occurring at the die passivation to underfill interface measured using C-mode Scanning Acoustic Microscopy (C-SAM). Using the measurements and numerical simulations, valuable insight has been gained on the effects of assembly variables and underfill material properties on the reliability of flip chip packages.

Reliable, consistent, and comprehensive material property data are needed for microelectronic encapsulants for the purpose of mechanical design, reliability assessment, and process optimization of electronic packages. In our research efforts, the mechanical responses of several different capillary flow snap cure underfill encapsulants are being characterized. A microscale tension-torsion testing machine has been used to evaluate the uniaxial tensile stress-strain behavior of underfill materials as a function of temperature, strain rate, specimen dimensions, humidity, thermal cycling exposure, etc. A critical step to achieving accurate experimental results has been the development of a sample preparation procedure that produces mechanical test specimens that reflect the properties of true underfill encapsulant layers. In the developed method, 75-125 µm (3-5 mil) thick underfill uniaxial tension specimens are dispensed and cured using production equipment and the same processing conditions as those used with actual flip chip assemblies. Although several underfills have been examined, this work features results for the mechanical response of a single typical capillary flow snap cure underfill. A three parameter hyperbolic tangent empirical model has been shown to provide accurate fits to the observed underfill nonlinear stress-strain behavior over a range of temperatures and strain rates. In addition, typical creep data are presented.

Fretting corrosion induced by vibration is a topic of major concern for automotive applications, often leading to increased contact resistance and connector failure. Presently, modeling of the behavior of connectors during fretting corrosion is a difficult matter, requiring many parameters, and is generally highly nonlinear in nature. Experimental testing of sample connectors is currently the only practical method of evaluating connector performance; however, testing can be a timeconsuming and inexact task. Prior work by the authors studied the fretting behavior of connectors subjected to single frequency vibration. Correlation of experimental results with simulated behavior showed that, for the primary mode of connector interface motion observed (rocking-type motion), the relative moment at the interface was a good indicator of the observed fretting rate. It was also shown that the moment applied as the result of a given excitation level and frequency could reasonably be predicted via simulation. The current work extends this approach to random vibration profiles, which are a more realistic representation of the connector application environment. A simple model is developed which relates the early stage fretting corrosion rate to the threshold vibration levels for the connector, the dynamic characteristics of the connector / wiring configuration, and the vibration profile. A high degree of consistency between this model and the experimental data was demonstrated. Interestingly, regardless of the excitation profile applied to the overall system, the existence of a characteristic vibration threshold at the connector interface was observed.

An optimization model for allocating solder-paste printing inspection is described. The model considers the economic tradeoff between board yield and inspection accuracy. The model is developed using real production and visual inspection data provided by a high-volume electronics manufacturer located in Huntsville, Alabama. In addition, randomly generated problem instances are used to evaluate the performance of the proposed solution method. Results from a large case study show that when it compared with full post-printing inspection, the proposed model provides an allocation solution that can increase the total expected gains by 15%.

Fine-Pitch BGAs and underfills have been used in benign office environments and wireless applications for a number of years, however their reliability in automotive underhood environment is not well understood. In this work, the reliability of fine-pitch PBGA packages has been evaluated in the automotive underhood environment. Experimental studies indicate that the CTE as measured by TMA typically starts to change at 10-15°C lower temperature than the Tg specified by DSC potentially extending the change in CTE well into the accelerated test envelope in the neighborhood of 125°C. High Tg substrates with glass-transition temperatures much higher than the 125°C high temperature limit are therefore not subject to the effect of high coefficient of thermal expansion close to the high temperature of the accelerated test. Darveaux's damage relationships [1992, 1995, 2000] were derived on CBGA assemblies, with predominantly SMD pads and 62Sn36Pb2Ag solder. In addition to significant differences in the crack propagation paths for the two pad constructions, SMD pads fail significantly faster than NSMD pads in thermal fatigue. The thermal mismatch on CBGA's is much larger than PBGA assemblies. Crack propagation in CBGA's is often observed predominantly on the package side as opposed to both package and board side for PBGAs. In the present study, crack propagation data has been acquired on assemblies with 15 mm, 17 mm, and 23 mm size plastic BGAs with NSMD pads and 63Sn37Pb on high-Tg printed circuit boards. The data has been benchmarked against Darveaux's data on CBGA assemblies. Experimental matrix also encompasses the effect of BT substrate thickness on reliability. Damage constants have been developed and compared against existing Darveaux Constants. Prediction error has been quantified for both sets of constants.

Reliable, consistent, and comprehensive material property data are needed for microelectronic encapsulants for the purpose of mechanical design, reliability assessment, and process optimization of electronic packages. In our research efforts, the mechanical responses of several different capillary flow snap cure underfill encapsulants are being characterized. A microscale tension-torsion testing machine has been used to evaluate the uniaxial tensile stress-strain behavior of underfill materials as a function of temperature, strain rate, specimen dimensions, humidity, thermal cycling exposure, etc. A critical step to achieving accurate experimental results has been the development of a sample preparation procedure that produces mechanical test specimens that reflect the properties of true underfill encapsulant layers. In the developed method, 75-125 µm (3-5 mil) thick underfill uniaxial tension specimens are dispensed and cured using production equipment and the same processing conditions as those used with actual flip chip assemblies. Although several underfills have been examined, this work features results for the mechanical response of a single typical capillary flow snap cure underfill. A three parameter hyperbolic tangent empirical model has been shown to provide accurate fits to the observed underfill nonlinear stress-strain behavior over a range of temperatures and strain rates. In addition, typical creep data are presented.

The use of CSPs has expanded rapidly, particularly in portable electronic products. Many CSP designs will meet the thermal cycle or thermal shock requirements for these applications. However, mechanical shock (drop) and bending requirements often necessitate the use of underfills to increase the mechanical strength of the CSP-to-board connection. Capillary flow underfills processed after reflow, provide the most common solution to improving mechanical reliability. However, capillary underfill adds board dehydration, underfill dispense, flow and cure steps and the associated equipment to the assembly process. Corner bonding provides an alternate approach. Dots of underfill are dispensed at the four corners of the CSP site after solder paste print, but before CSP placement. During reflow the underfill cures, providing mechanical coupling between the CSP and the board at the corners of the CSP. Since only small areas of underfill are used, board dehydration is not required. This paper examines the manufacturing process for corner bonding including dispense volume, CSP placement and reflow. Drop test results are then presented. A conventional, capillary process was used for comparison of drop test results. Test results with corner bonding were intermediate between complete capillary underfill and non-underfilled CSPs. Finite element modeling results for the drop test are also included.

Fine-Pitch BGAs and underfills have been used in benign office environments and wireless applications for a number of years, however their reliability in automotive underhood environment is not well understood. In this work, the reliability of fine-pitch PBGA packages has been evaluated in the automotive underhood environment. Experimental studies indicate that the CTE as measured by TMA typically starts to change at 10-15°C lower temperature than the Tg specified by DSC potentially extending the change in CTE well into the accelerated test envelope in the neighborhood of 125°C. High Tg substrates with glass-transition temperatures much higher than the 125°C high temperature limit are therefore not subject to the effect of high coefficient of thermal expansion close to the high temperature of the accelerated test. Darveaux's damage relationships [1992, 1995, 2000] were derived on CBGA assemblies, with predominantly SMD pads and 62Sn36Pb2Ag solder. In addition to significant differences in the crack propagation paths for the two pad constructions, SMD pads fail significantly faster than NSMD pads in thermal fatigue. The thermal mismatch on CBGA's is much larger than PBGA assemblies. Crack propagation in CBGA's is often observed predominantly on the package side as opposed to both package and board side for PBGAs. In the present study, crack propagation data has been acquired on assemblies with 15 mm, 17 mm, and 23 mm size plastic BGAs with NSMD pads and 63Sn37Pb on high-Tg printed circuit boards. The data has been benchmarked against Darveaux's data on CBGA assemblies. Experimental matrix also encompasses the effect of BT substrate thickness on reliability. Damage constants have been developed and compared against existing Darveaux Constants. Prediction error has been quantified for both sets of constants.

The use of underfills in electronic applications is becoming more prevelant with the decrease in package pitch to 0.5 mm and the increase in I/Os. Underfill encapsulation is typically used in flip chip on laminate assemblies to more evenly distribute and minimize the solder joint strains, thus improving thermal cycling fatigue life. The material constitutive and damage behavior of underfills is however poorly understood. Typical underfill material data sheets often do not provide the parameters required for development of accurate predictive models. In this paper a new methodology for preparation of thin uniaxial test samples for mechanical testing of underfills has been used to better understand the non-linear constitutive behavior of underfills. Bulk underfill samples exhibit different behavior because of non-uniform curing and the effect of sample thickness on the response of underfill layers. A microscale tension-torsion testing machine has been used to measure stress-strain, creep, and stress relaxation behavior if several underfills as a function of temperature. Thermal-fatigue reliability response of various permutation of underfill materials have been analyzed using statistical models. The effect of thermal aging, thermal cycling, and moisture pre-conditioning on the constitutive behavior of materials have been analyzed. Models have been developed to represent the underfill behavior in an operating range of -40 to 125C.

In this study, we have examined the thermal cycling reliability of several lead free chip resistor solder joint configurations. Five sizes of resistors (2512, 1206, 0805, 0603, 0402), 2 temperature ranges (-40 to 125 °C and -40 to 150 °C), and five different solder types have been examined. The solders include the normal SnAgCu alloy recommended by earlier studies (95.5Sn-3.8Ag-0.7Cu), and several variations that include small percentages of Bismuth and Indium to enhance fatigue resistance. Results have been compared to data for standard 63Sn-37Pb joints.

The use of CSPs has expanded rapidly, particularly in portable electronic products. Many CSP designs will meet the thermal cycle or thermal shock requirements for these applications. However, mechanical shock (drop) and bending requirements often necessitate the use of underfills to increase the mechanical strength of the CSP-to-board connection. Capillary flow underfills processed after reflow, provide the most common solution to improving mechanical reliability. However, capillary underfill adds board dehydration, underfill dispense, flow and cure steps and the associated equipment to the assembly process. Corner bonding provides an alternate approach. Dots of underfill are dispensed at the four corners of the CSP site after solder paste print, but before CSP placement. During reflow the underfill cures, providing mechanical coupling between the CSP and the board at the corners of the CSP. Since only small areas of underfill are used, board dehydration is not required. This paper examines the manufacturing process for corner bonding including dispense volume, CSP placement and reflow. Drop test results are then presented. A conventional, capillary process was used for comparison of drop test results. Test results with corner bonding were intermediate between complete capillary underfill and non-underfilled CSPs. Finite element modeling results for the drop test are also included.

Fine-Pitch BGAs and underfills have been used in benign office environments and wireless applications for a number of years, however their reliability in automotive underhood environment is not well understood. In this work, the reliability of fine-pitch PBGA packages has been evaluated in the automotive underhood environment. Experimental studies indicate that the CTE as measured by TMA typically starts to change at 10-15°C lower temperature than the Tg specified by DSC potentially extending the change in CTE well into the accelerated test envelope in the neighborhood of 125°C. High Tg substrates with glass-transition temperatures much higher than the 125°C high temperature limit are therefore not subject to the effect of high coefficient of thermal expansion close to the high temperature of the accelerated test. Darveaux's damage relationships [1992, 1995, 2000] were derived on CBGA assemblies, with predominantly SMD pads and 62Sn36Pb2Ag solder. In addition to significant differences in the crack propagation paths for the two pad constructions, SMD pads fail significantly faster than NSMD pads in thermal fatigue. The thermal mismatch on CBGA's is much larger than PBGA assemblies. Crack propagation in CBGA's is often observed predominantly on the package side as opposed to both package and board side for PBGAs. In the present study, crack propagation data has been acquired on assemblies with 15 mm, 17 mm, and 23 mm size plastic BGAs with NSMD pads and 63Sn37Pb on high-Tg printed circuit boards. The data has been benchmarked against Darveaux's data on CBGA assemblies. Experimental matrix also encompasses the effect of BT substrate thickness on reliability. Damage constants have been developed and compared against existing Darveaux Constants. Prediction error has been quantified for both sets of constants.

Mechanical stress distributions in packaged silicon die that have resulted during assembly or environmental testing can be accurately characterized using test chips incorporating integral piezoresistive sensors. In this paper, an overview of recent measurements made in flip chip on laminate assemblies with (111) silicon test chips is presented. Transient die stress measurements have been made during underfill cure, and the room temperature die stresses in final cured assemblies have been compared for several different underfill encapsulants. The experimental stress measurements in the flip chip samples were then correlated with finite element predictions for the tested configurations. In addition, stress variations have been monitored in the assembled flip chip die as the test boards were subjected to slow temperature changes from -40 to +150 °C. Finally the stress variations occurring during thermal cycling from -40 to +125 °C have been characterized. These measurements have been correlated with the delaminations occurring at the die passivation to underfill interface measured using C-mode Scanning Acoustic Microscopy (C-SAM). Using the measurements and numerical simulations, valuable insight has been gained on the effects of assembly variables and underfill material properties on the reliability of flip chip packages.

For a successful transition to Pb-free manufacturing in electronics assembly, it is critical to understand the behavior of Pb-free solders (in bulk and paste form) and their interaction with the Pb-free printed wiring board (PWB) finishes. This paper presents the results obtained from solder paste spread tests and wetting balance experiments with several Pb-free solder alloys and Pb-free PWB finishes. The solder alloys studied were Sn3.4Ag4.8Bi, Sn4.0Ag0.5Cu, Sn3.5Ag and Sn0.7Cu. Eutectic Sn37Pb was used as a reference. The PWB surface finishes were Sn, NiAu, Ag and OSP. Wetting balance experiments were conducted in air while the spread tests were performed in air and nitrogen to understand the effect of reflow atmosphere on the spreading. Surface analyzes techniques such as Nomarski phase contrast microscopy, Auger electron spectroscopy (AES) and x-ray photoelectron spectroscopy (XPS) were used to characterize the as-received PWB finishes. Sequential electrochemical reduction analysis (SERA) was also performed on the as-received PWB test coupons and on the Sn test coupons after multiple reflow cycles. The effect of multiple reflow cycles on the wetting performance, spreading and the surface composition of the PWB finishes was studied. Index Terms: Pb-free PWB finish, Pb-free solder, solderability.

In this work, the under-the-hood reliability of smaller PBGA packages has been evaluated in the automotive thermal cycling environment. Various methods of enhancing reliability have been explored including increased BT substrate thickness, the utilization of NSMD pads on the BGA component, alternative PCB plating finishes, and the use of underfill encapsulants. A set of test boards was assembled with several 15 and 17 mm body size BGA components from two different vendors. In addition to non-underfilled parts, the enhancements achieved with four different underfill encapsulants have been explored. Larger 23 mm BGAs have also been included in the test matrix as a control/reference. The assembled test vehicles have been subjected to 6000 thermal cycles over the range -40 to 125 °C, and the daisy-chain resistances of the various components were monitored throughout the testing. Logged failures have been statistically analyzed using two parameter Weibull models. The analysis results have allowed the board level reliabilities of the examined BGA components to be compared and ranked, and the reliability enhancements achieved with various underfills to be accessed. Detailed failure analyses have also been performed to find the locations of solder joint fatigue crack growth, and to identify other failure modes occurring in underfilled parts.

Single frequency vibration tests were used to induce fretting corrosion in tin alloy plated contacts. The samples used in this study were connectors consisting of 25 pairs of mated pin and socket contacts. Experimental results for a variety of vibration levels, frequencies, and wiring tie-off lengths are presented. The experiments consisted of running a series of vibration tests at each frequency where the excitation level was stepped through a range of g-levels. During each test run contact resistance was monitored as a performance characteristic. The results exhibit threshold behavior at each frequency for the onset of fretting degradation. Typically a plateau region was observed where similar g-levels produced similar fretting rates. It was also found that outside the plateau region the g-levels varied according to the dynamic behavior of the mechanical system. In addition, a transfer matrix model was used to analyze these results. An empirical fit of the data correlated well with the model when damping was used. This analysis revealed the importance of the bending moment induced at the contact interface as a result of excitation levels and tie-off configurations. Consequently, it is concluded that dynamic response of the mechanical system under various g-levels and tie off configurations can greatly impact the performance of a connector system subjected to vibration stresses.

Fine pitch BGAs and chip scale packages have been developed as an alternative to direct flip chip attachment for high-density electronics. The larger solder sphere diameter and higher standoff of CSPs and fine pitch BGAs improve thermal cycle reliability while the larger pitch relaxes wiring congestion on the printed wiring board. Fine pitch BGAs and CSPs also allow rework to replace defective devices. Thermal cycle reliability has been shown to meet many consumer application requirements. However, fine pitch BGAs and CSPs have difficulty meeting mechanical shock and substrate flexing tests for portable electronics applications. The fine pitch BGA used in the study was a 10 mm package with the die wire bonded. The package substrate was bismaleimide-triazine (BT) and the solder sphere diameter was 0.56 mm. Two types of underfill were examined. The first was a fast flow, snap cure underfill. This material rapidly flows under the package and can be cured in five minutes at 165 C using an in-line convection oven. The second underfill was a thermally reworkable underfill for those applications requiring device removal and replacement. The paper discusses the assembly and rework process. In addition, liquid-to-liquid thermal shock data is presented along with mechanical shock and flexing test results.