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p. 517
–524
(8)
A new modified form of the Friis equation for the noise figure of a cascade of stages that can be used when one or more of the stages in the cascade have noise-aliasing properties is derived. The application of the modified noise figure equation in the noise analysis of a subsampling receiver front-end is given and the equation is verified in a circuit-level simulation. The modified Friis equation gives insight into the noise behaviour of subsampling radio receiver architectures and shows that the very high noise figures often associated with subsampling mixers can be misleading in a system context.

p. 525
–532
(8)
A novel design for a stacked inductor using RLC elements is presented. The proposed model used to predict the stacked inductor is based on a 4-port circuit design with semi-empirical derivation. The modified RS formulas are implemented accurately to predict the series resistance of the stacked inductor. The verification has been carried out using a mature 0.18 μm process to fabricate stacked inductor with various sizes and types. All the measured data are extracted from a silicon device based on a physical layered test system (PLTS). The predicted and measured S-parameter results show excellent correlation in terms of performance for frequencies up to 15 GHz. A high-Q on-chip active inductor is demonstrated using a multiple turns stacked inductor.

p. 533
–538
(6)
A new flexible AES architecture is proposed that can perform both encryption and decryption with 128-, 192-, and 256-bit key options by a novel on-the-fly key generation module. The corresponding subkeys for encryption and decryption are generated concurrently as the appropriate configuration parameters (signals) are set. The proposed design operates in CBCk (cipher block chain) mode and processes three blocks of data simultaneously. The architecture is simulated in Verilog HDL and implemented in FPGA and ASIC designs. The performance comparison indicates that the design has high throughput and small circuit area.

p. 539
–544
(6)
Frequency analysis using DFT (discrete Fourier transform) or its faster computational technique (FFT) is an obvious choice for the entire image and signal processing domain where spectral leakage or picket fence effect is a major problem. Earlier works describe the software and ROM-based implementation of windowing functions to overcome the above-mentioned problems during spectral analysis. In this work we have proposed a CORDIC (co-ordinate rotation digital computer)-based unified windowing architecture to remove the spectral leakage, picket fence effect and resolution problems with different tradeoff between mainlobe and sidelobe in the frequency domain. A parallel-pipelined architecture has been adopted for the present design to ensure high throughput for real-time applications with the latency equal to twice of CORDIC length plus three extra cycles. This unified architecture includes a combination of linear CORDIC and circular CORDIC with FIFO and a few multiplexers where the selection of window and its length are user defined. We have synthesised this architecture with 0.18 μm CMOS technology using Synopsys Design Analyser. The total estimated dynamic power was found to be 350 mW with an operating frequency of 125 MHz and total cell area 11 mm2 (approximately).

p. 545
–551
(7)
The sequence-pair, a data structure with applications in packing-based VLSI module placement, has received significant amounts of research effort as the core of simulated annealing optimisers. Nevertheless, its application within genetic algorithm frameworks has not been adequately investigated. This paper presents a genetic algorithm approach to rectangle packing using the sequence-pair. The method is extended to handle symmetry constraints, a requirement often arising in the placement of analogue circuits. Genetic operators are developed taking into account the specific properties of the sequence-pair, and the algorithm is tested on several MCNC benchmarks.