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Abstract

In a typical data processing system, after the Storage Control Unit (SCU) has been selected, it is hardware controlled and cycles through its function independent of the reloadable control store (RCS). The only hardware signals that can be tested by diagnostic programs are those that are still in the active (or inactive) state at the end of the operation. (An operation typically involves many cycles.)

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United States

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English (United States)

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Storage Control Unit Sequence and Cycle Scanner

In a typical data processing system, after the Storage Control Unit (SCU)
has been selected, it is hardware controlled and cycles through its function
independent of the reloadable control store (RCS). The only hardware signals
that can be tested by diagnostic programs are those that are still in the active (or
inactive) state at the end of the operation. (An operation typically involves many
cycles.)

The mechanism illustrated provides a method for testing a signal in any
selected cycle, to record and/or test a sequence of events for numerous cycles
utilizing machine speed diagnostic microprograms.

In a system which includes a service processor (SVP), a microcode
command is sent to the SVP to set and freeze the console clocks to a selected
value (1, 2, 4, P bit times and 1, 2, 4, 8, 16, 32, 64, 128, 256 log address lines).
A microcode command is then given to sample the bit time lines and set this
value into the clock sample select latches CSSL. The log address lines are also
sampled and set into the cycle counter. The CSSL contents are decoded to
select a specific clock pulse within the selected cycle. The cycle counter contains
the number of cycles to be counted and goes to zero on the selected cycle.

After the CSSL's and the cycle counter have been set, the microcode
command to set and freeze the console clocks is again sent to the SVP, this time
set to the log address of the signal to be tested. A path is now es...