For this schematic to work, you have to insert some dummy component between wires e.g. wire CAP1_DrvL and wire [0]. Try a virtual mux or make your own (empy pass-thru) component.

Another way: instead of joining the CAP1_DrvL and [0], name the whole wire as CAP1_DrvL[0] by specifying both the wire name and bit number. In this case, you must use same name CAP1_DrvL[0] for the wire on the other sheet.

Lastly, shrinking the bus as you did (vertical line) is overkill. It is enough that you named it [7:0] once. You can remove all those fancy ingexes ([7:6], [7:5],..,[7:1] ) - Creator will do bus joining automatically.