Floorplanning is an important step in physical design of VLSI circuits. It is used to plan the positions of a set of circuit modules on a chip in order to optimize the circuit performance. However, modern floorplanning takes better care of providing extra options to place dedicated modules in the hierarchical designs to align circuit blocks one by one within certain bounding box for helping sequential data transfer (bus or pipeline) signal in the VLSI circuit. In this paper, the placement of circuit blocks with alignment constraints can be handled using B*tree representation with Differential Evolutionary algorithm. In order to reduce the solution space, feasibility conditions of nonslicing floorplan with alignment constraints have been examined. The properties associated with our proposed Differential Evolutionary algorithm provide the way to produce optimal floorplan. Experimental results based on the MCNC benchmark circuits with the alignment constraint shows that our Differential algorithm can produce promising solutions.