The MC74HC4046A is similar in function to the MC14046 Metal gate CMOS device. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC4046A phase­locked loop contains three phase comparators, a voltage­controlled oscillator (VCO) and unity gain op­amp DEMOUT. The comparators have two common signal inputs, COMP IN, and SIG IN. Input SIG IN and COMP IN can be used directly coupled to large voltage signals, or indirectly coupled (with a series capacitor to small voltage signals). The self­bias circuit adjusts small voltage signals in the linear region of the amplifier. Phase comparator 1 (an exclusive OR gate) provides a digital error signal PC1 OUT and maintains 90 degrees phase shift at the center frequency between SIG IN and COMP IN signals (both at 50% duty cycle). Phase comparator 2 (with leading­edge sensing logic) provides digital error signals PC2 OUT and PCP OUT and maintains a 0 degree phase shift between SIG IN and COMP IN signals (duty cycle is immaterial). The linear VCO produces an output signal VCOOUT whose frequency is determined by the voltage of input VCO IN signal and the capacitor and resistors connected to pins C1B, R1 and R2. The unity gain op­amp output DEMOUT with an external resistor is used where the VCO IN signal is needed but no loading can be tolerated. The inhibit input, when high, disables the VCO and all op­amps to minimize standby power consumption. Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication, frequency discrimination, tone decoding, data synchronization and conditioning, voltage­to­frequency conversion and motor speed control.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating Plastic DIP: ­ 10 mW/_C from to 125_C SOIC Package: ­ 7 mW/_C from to 125_C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High­Speed CMOS Data Book (DL129/D).