Process Integration

Leading-edge semiconductor manufacturing requires the integration of hundreds of process steps to fabricate transistors with increasingly sophisticated 3D geometry. Greater process complexity has, in turn, dramatically increased the number of costly, time-consuming silicon build-and-test learning cycles required to bring new technology nodes to production. Virtual fabrication with SEMulator3D can reduce or replace these learning cycles with predictive integrated process modeling. SEMulator3D enables 3D visualization of the full, integrated process flow across the full spectrum of designs, and provides engineers with valuable insight. But visualization is just the beginning. SEMulator3D provides quantitative output that can predict process-design sensitivities, yield-limiting mechanisms and parametric dependencies before fabricating actual devices.

Process Window Characterization

Process windows continue to diminish with shrinking geometry and device complexity, making identification of sensitivities and process interactions critical. Virtual fabrication enables rapid characterization of the entire integrated process flow, so the effects of variations in individual or multiple processes can be explored quantitatively. Consider, for instance, a hypothetical FinFET flow where previous process steps affect the growth of SiGe stressors on the fins. The SiGe epitaxial growth depends strongly on the amount of fin erosion prior to epitaxy. Figure 1 highlights the steps that influence fin erosion.

Visualization alone is useful for diagnostic purposes, but quantitative results are even more valuable. By inserting Virtual Metrology steps in the process sequence, engineers can perform quantitative analyses like they do in the fab. SEMulator3D metrology steps can even extract parameters that cannot be easily measured in the fab, such as cross-section area or 3D contact area.

Continuing the FinFET FEOL example, results from a virtual experiment (Figure 2) show that differences of 2nm in fin erosion act to nearly double the SiGe cross-section area, which could have a critical performance impact. Virtual fabrication results like these can be used to improve the experiments run in silicon learning cycles, and investigate sensitivities beyond those typically explored due to constraints on development resources. Equally important, development resources can be proactively focused on a technology’s most critical unit processes to ensure manufacturing readiness.

Cross-Wafer Uniformity

Cross-wafer uniformity is a key metric in the fab and the net result of numerous unit process interactions. SEMulator3D Expeditor can be used to perform virtual experiments to characterize cross-wafer uniformity. Consider, for instance, a hypothetical BEOL process module for the M1-V1-M2 via chain. Expeditor can run a full-factorial experiment that covers the eleven most significant unit process variables in a few hours on a notebook PC. A metrology step extracts M2 Cu cross-section area, something that would require labor-intensive failure analysis in the fab. Quantitative results from this experiment are shown in Figure 3 using an industry-standard, 49-point wafer map.

In typical process integration, all unit processes are independently optimized for cross-wafer uniformity. SEMulator3D can certainly be used to optimize unit processes. However, it is also possible to improve the cross-wafer uniformity of integrated structures by process changes that drive individual processes away from uniformity. That’s where SEMulator3D really comes into its own, offering a unique capability.