this is the first time I'm using the analog comparator. I'm trying to compare AIN0 and AIN1. A pulse is applied to AIN0 and a rising ramp to AIN1. Once the value of AIN1 is higher than the maximum of the pulses on AIN0, no more falling edges should occur, right? So my goal is to trigger an interrupt on every falling edge of the comparator and detect a missing edge to calculate my results.

// Analog Comparator Multiplexed Input: // If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog Comparator. ADCSRB &= ~(1<<ACME);

// Setup of ACSR (Comparator Register) // Bit 7(MSB) : ACD: Analog Comparator Disable; When this bit is written logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode. When chang- ing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. // Bit 6 : ACBG: Analog Comparator Bandgap Select; When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. When the bandgap reference is used as input to the Analog Comparator, it will take a certain time for the voltage to stabilize. If not stabilized, the first conversion may give a wrong value. // Bit 5 : ACO: Analog Comparator Output; The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1 - 2 clock cycles. // Bit 4 : ACI: Analog Comparator Interrupt Flag; This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag. // Bit 3 : ACIE: Analog Comparator Interrupt Enable; When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator interrupt is activated. When written logic zero, the interrupt is disabled. // Bit 2 : ACIC: Analog Comparator Input Capture Enable; When written logic one, this bit enables the input capture function in Timer/Counter1 to be triggered by the Analog Comparator. The comparator output is in this case directly connected to the input capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the Analog Comparator and the input capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask Register (TIMSK1) must be set. // Bit 1,0(LSB): ACIS1, ACIS0: Analog Comparator Interrupt Mode Select; These bits determine which comparator events that trigger the Analog Comparator interrupt. /* ACIS1 | ACIS0 | Interrupt Mode 0 0 Comparator Interrupt on Output Toggle. 0 1 Reserved. 1 0 Comparator Interrupt on Falling Output Edge. 1 1 Comparator Interrupt on Rising Output Edge. */ ACSR = B00011010;

// Disable digital input buffer // AIN1, AIN0 Digital Input Disable: When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding PIN Reg- ister bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the dig- ital input buffer. DIDR1 |= (1<< AIN0D); DIDR1 |= (1<< AIN1D);

By the way, I have another question on that topic.I'm using Timer1 to generate an interrupt every Xµs that triggers the pulse for the comparator. That means that the comparator interrupt will be triggered just before the other interrupt finishes. Somewhere I heard, that interrupts aren't allowed within interrupts. Is that true? If the Arduino "remembers" that there was another(different) interrupt during the timer interrupt and executes it afterwards, that would be fine because the comparator interrupt only increments a value and timing isn't important, as long as it doesn't forget the comparator interrupt.

In your case, the ACI flag will be set while the timer isr is being serviced. The execution will return to where it was before the timer isr was executed, and then jump right back to the analog comparator isr (assuming no other interrupt flags are set).

The typical approach then is to charge up a fully depleted cap and measure the current during the initial charge up. The comparator is probably not a very good tool for this.

Unless you have a different approach?

I feed the DUT with a constant current(chopped by the generated pulse), amplify the generated voltage over the DUT and compare it to the voltage of a reference cap that is being charged by a constant current(==> linear rising voltage). If you want to read more, here's a link: http://members.ozemail.com.au/~bobpar/k7214.pdf I basically just added some stuff I wanted and converted it to be Arduino based.

The comparator(and C10) is essentially there for an extremely fast analogRead(), which otherwise wouldn't be possible fast enough.The goal of an ESR meter is to make measurements in circuit possible and if you charge the capacitor you'd activate other stuff in there.http://en.wikipedia.org/wiki/Equivalent_series_resistance