Tuesday August 8, 2017 at 4:10 p.m. Dr. Shanthi Pavan, Professor of Electrical Engineering at the Indian Institute of Technology, will be presenting “Design Considerations for Power Efficient Continuous-Time Delta Sigma ADCs”.

Abstract: Continuous-time Delta-Sigma Modulators (CTDSMs) are a compelling choice for the design of high resolution analog-to-digital converters. Many delta-sigma architectures have been published (and continue to be invented). This leaves the designer with a bewildering array of choices, many of which seem to pull in opposite directions. Further, it is often difficult to make a clear comparison of various architectures, as they have been designed for dissimilar specifications, by different design groups, and in different technology nodes. This talk examines various design alternatives for the design of power efficient single-loop continuous-time delta sigma converters.

Biography: Shanthi Pavan obtained the B.Tech degree in Electronics and Communication Engineering from the Indian Institute of Technology, Madras in 1995 and the Masters and Doctoral degrees from Columbia University, New York in 1997 and 1999 respectively. He is now with the Indian Institute of Technology-Madras, where he is a Professor of Electrical Engineering. His research interests are in the areas of high-speed analog circuit design and signal processing. Dr.Pavan is the recipient of many awards for teaching and research, including the IEEE Circuits and Systems Society Darlington Best Paper Award and the Shanti Swarup Bhatnagar Award (from the Government of India). He has served as the Editor-in-Chief of the IEEE Transactions on Circuits and Systems: Part I – Regular Papers. He is a Fellow of the Indian National Academy of Engineering.

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