Models and compliance testsuites are developed 100% in SystemVerilog and UVM.
Memory models support all speed modes and configurations including parameter files for the major SDRAM and RDIMM/LRDIMM vendors including Samsung and Micron. Memory models support a full SDRAM/DIMM user API with many advanced features not included in many “free” models such as

RDIMM/LRDIMM-level verification is performed using the Avery provided plug’n’play testbench and compliance testsuite focusing on RCD and DB functional and overall timing requirements.

SoC/memory controller verification is performed using the Avery DDR chip/DIMM memory models to test memory controller functions such as memory refresh and control modes such as DDR4’s PDA and modereg readout.

DDR-Xactor supports the JEDEC SDRAM standards including DDR4, DDR3, and the JEDEC mobile memory standards including LPDDR4 and LPDDR3, and DRAM module standards for RCD and DB. DDR-Xactor also supports the DFI-PHY 3.1 standards.

“DDR4 memory systems are significantly more challenging to get right than in previous generations. Avery is in a position to assist memory controller, PHY, and RDIMM/LRDIMM makers with the robust models, timing and protocol checking, and compliance testsuites for comprehensive functional verification and performance tuning”, says Chilai Huang, president of Avery Design Systems.