TSMC, Samsung Diverge at 7nm

SAN FRANCISCO — Samsung and TSMC gave two very different glimpses of their work on 7nm process technology at the International Solid State Circuits Conference (ISSCC) here. Both companies presented work on SRAMs, typically a key driver for next-generation nodes.

TSMC’s paper described a test chip that could pass for a commercial part and said it had “healthy” yields. Samsung described its use of extreme ultraviolet (EUV) lithography to repair what was clearly a research device, suggesting what it will call 7nm could still be years away.

Both papers need to be viewed through the lens of ISSCC, a gathering place for some 3,000 upwardly mobile chip designers from around the world. Both foundries want to make the case they are at the leading edge of next-generation foundry services. Unfortunately they diverge on what they will call 7nm.

TSMC has apparently won the lion’s share of Apple’s iPhone SoC business, which requires slight improvements in process technology every year. Thus, TSMC started making in volume 10nm chips this year for the iPhone 7 and needs to ramp 7nm chips for the iPhone 8 next year.

Without Apple’s business, Samsung can afford to step back from the name game to some extent. Thus, it will put off its 7nm node but show leadership by being among the first to use, in some form, EUV.

Both companies are making admirable advances. One analyst recently said the foundries are essentially leapfrogging each other and chip giant Intel.

But details are scarce. At ISSCC, TSMC described a 256 Mbit SRAM test chip using its 7nm process to hit a bit-cell area of 0.027mm2, making it the “smallest SRAM be in risk production this year,” said Jonathan Chang, director of TSMC’s memory group, in his talk.

The resulting SRAM macro will be 0.34x smaller than TSMC’s 16nm version. It uses seven metal layers and has an overall die size of 42mm2.

The key detail from Chang's talk is this SRAM is almost fully baked. “We are able to yield it right now, with a very, very healthy Vmin…that meets out design targets,” he said.

Next page: Samsung describes one limited job for EUV

TSMC's commercial SRAM will be in risk production this year. (Images: ISSCC)

The general rule for coming in late on a node, is that you need to come in with higher density. For this reason, Samsung needs to bring in the 8LPP and Intel is bringing in the SAQP and even GlobalFoundries may be scaling aggressively. But generally they will aim to leave TSMC with the least dense 7nm, even with its projected 7nm+ case.

I'm skeptical of that - why would Intel re-brand their nodes? Foundry customers are (I should hope!) educated enough to not care about that, but only the power/performance/area characteristics of the process. Besides, if such a marketing driven decision was made, what stops TSMC from doing a tweak of their 7nm and calling it 5nm, and renaming their 5nm as 3nm to stay one step ahead?

The numbers are meaningless for everyeone as it is, it isn't like Intel's 14nm process actually has any anything measuring 14nm. Nowadays the numbers just denote equivalency to historical process nodes when 180nm actually meant something was 180nm. Does it really matter if you achieve scaling to double the number of transistors per sq mm by shrinking the gate width by sqrt(2) or by using a different type of transistor structure with a smaller footprint for the same gate width?

Yeah I think they meant to say using 10nm for this year's iPhone (presumably called iPhone 8) and 7nm for next years (iPhone 8S?)

Of course their 10nm is roughly equal to Intel's 14nm, and their 7nm roughly equal to Intel's 10nm, so a lot of it is marketing driven. But they will have caught up to Intel who are scheduled to ramp their 10nm at around the same time TSMC ramps 7nm.

"The resulting SRAM macro will be 0.34x smaller than TSMC's 16nm version". This reads like TSMC's 7nm is only 34% "smaller" than its 16nm. The 7nm area scaling should be 0.34x or 34% footprint of 16nm.