The reliability of thin gate oxides grown by rapid thermal oxidation in O/sub 2/ followed by one and two step postoxidation annealing (POA) in N/sub 2/ was studied. The one step POA was carried out by switching O/sub 2/ into N/sub 2/ immediately after oxidation without changing temperature, while the two step POA was cooled down first and subsequently heated to the same temperature as oxidation in...
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In this letter, we find an efficient way to suppress UV damage on the characteristics of polysilicon thin-film transistors (TFTs) during hydrogenation for high density TFT SRAM. Polysilicon TFT can be free from UV damage during hydrogenation if the channel region is shielded by a metal line of the same width as channel. After hydrogenation, the metal shielded TFT shows an excellent subthreshold sw...
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This paper addresses the analysis of the Insulated Base MOS-Controlled Thyristor (IBMCT), a novel MOS-thyristor structure compatible with IGBT process technology. The IBMCT turn-off process is based on the existence of a Floating Ohmic Contact (FOC) which allows fast hole removal from the p-body region. The device operation mode and its electrical characteristics are analyzed with the aid of 2-D n...
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Temperature profiles resulting from self-heating in SOI-LDMOS devices with uniformly doped and linearly graded drift regions were measured using a resistance thermometry technique. Two-dimensional electrothermal device simulations were performed and the results agreed with the experiments. Because of the different power dissipation profiles, RESURF devices with a uniformly doped drift region assum...
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We have fabricated a self-aligned offset-gated poly-Si thin film transistor (TFT) by employing a novel photoresist reflow process. The gate structure of the new device is consisted of two unique patterns: A main-gate and a sub-gate. The new fabrication method extends the gate-oxide over the offset region. With the assistance of the sub-gate and reflowed photoresist a self-aligned offset region is ...
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Novel fingerprint scanning arrays based upon capacitance sensing have been made. Each sensor element consists of a capacitor electrode and two poly-Si thin film transistors for addressing and read out. The devices were fabricated on glass, polyimide and polyethersulphone substrates using a low temperature (<250/spl deg/C) process.
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In this letter, a sensitive and simple technique for parasitic interconnect capacitance measurement and extraction is presented. This on-chip technique is based upon an efficient test structure design that utilizes only two transistors in addition to the unknown interconnect capacitance to be characterized. No reference capacitor is needed. The measurement itself is also simple; only a dc current ...
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