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About Michael J. Miller

Miller, who was editor-in-chief of PC Magazine from 1991 to 2005, authors this blog for PC Magazine to share his thoughts on PC-related products. No investment advice is offered in this blog. All duties are disclaimed. Miller works separately for a private investment firm which may at any time invest in companies whose products are discussed in this blog, and no disclosure of securities transactions will be made.

Common Platform Technology Forum: Chip-Making at 14nm and Below

Yesterday I attended the Common Platform Technology Forum, where IBM, Globalfoundries, and Samsung presented the technology they will use to manufacture chips in the future. This group, originally set up by IBM to distribute its chip making technologies, essentially takes a basic process created by IBM and its partners, and then moves it to Globalfoundries and Samsung for high-volume manufacturing.

Here are the highlights:

Development of 14nm FinFET process technology (creating 3D-like transistors) seems to be on track, most likely with the foundries starting production in 2014 and products based on that production likely to appear by 2015. (Intel is already shipping FinFETs, which it calls "Tri-Gate" transistors, on 22nm but Intel is different in that it primarily is its own customer, with a single basic design, and foundries need to support a much wider range of customers.) Note that the Common Platform version of this process, as discussed by Globalfoundries earlier, combines FinFET technology on the "front-end" with the same "back-end" as its 20nm process.

While everyone agrees EUV (extreme ultraviolet) lithography will be necessary sometime in the future, it is taking longer to develop and facing more issues than expected. Now it isn't likely to be used until 7nm production or even later.

Where the Common Platform group once talked about making its processes identical from each of its manufacturers so customers could migrate from one to another easily, the focus now seems to be on creating a core process technology and then letting the individual foundries (Globalfoundries and Samsung) customize them for their specific customers.

The migration to 20nm and 14nm production will not create as much cost reduction per transistor, as manufacturers have come to expect from new process nodes. (Typically, you get twice as many transistors per node—Moore's Law—but at a slightly higher cost.) But 20nm adds more cost because it will require "double-patterning" of lithography for the first time, and the 14nm node the Common Platform partners are talking about isn't really a full shrink, as it uses the 20nm "back-end." But executives said they expect to be back on the normal economics in the move to 10nm.

Here are some details:

Mike Cadigan, VP of IBM Microelectronics, talked about how the Common Platform has evolved over the past 10 years. It has gone from a group designed to create an alternative to foundry leader TSMC to one that now includes the number two and three foundries (Globalfoundries and Samsung Semiconductor), based on technology that comes from IBM research and the other companies. In particular, he pointed to a new semiconductor research and development facility in Albany, NY, built in conjunction with the state and partners, where IBM is now working with its top five equipment suppliers on projects such as developing EUV.

Cadigan (above) alluded to the difficulty of moving to the next generation of technology. "All of us are on a treadmill," he said, but suggested the Common Platform model gives its members the ability to leverage work done by the members and their partners.

"Our industry is vital to society," he said, noting how silicon is driving everything from smartphones to self-driving cars to new healthcare are devices.

Later, in a question-and-answer session, he said that there have been significant changes in how the Common Platform group works over the years. The previous process involved IBM creating the basic technology and putting it to work in its East Fishkill manufacturing plant, then passing on the whole process to its partners. Now, he said, once IBM has the basic technology working, it goes directly to Globalfoundries and Samsung, speeding the time to market.

IBM Says Chip-Making Facing Major Discontinuities

Gary Patton, vice president of IBM Semiconductor Research and Development Center, gave the deep dive into the technology, discussing the challenges facing chip makers in the years ahead.

"We're at a discontinuity," said Patton (above), with chip making undergoing a major change. He said this isn't the first time the industry has seen such issues, nor will it be the last. The industry reached the physical limits of planar CMOS and gate oxide, so it had to move to strained silicon and high-k/metal gate materials. Now, he said, we're at the limit of planar devices, so we need to transition to the "3D era," both in terms of transistors themselves (i.e., FinFETs) and in packaging using concepts such as chip stacking. In the next decade, he said, we will reach the limit of atomic dimensions and will need to move to technologies such as silicon nanowires, carbon nanotubes, and photonics.

To make all this work, it is important that foundries no longer act just as manufacturing companies, but work with their customers and the tool suppliers in a design/technology "co-optimization," in which the process acts more like a "virtual IDM" (Integrated Device Manufacturer).

Patton touched on the need for continued research, talking about IBM's research facilities in Yorktown, Almaden, and Zurich and how for the twentieth year in a row, IBM has been granted the most patents. He talked about the importance of partners as well, in particular pointing to the Albany Nanotech Research Facility, which was built in partnership with New York State and Suny/Albany CNSE, along with Sematech and a host of materials and equipment suppliers.

A lot of his talk centered on the challenges facing EUV, which he called "the biggest change in the history of the lithography industry." He noted that if EUV is ready to go at 7nm, it will produce crisper images, and thus better performing chips than other technologies. But there are big challenges. To start with, EUV equipment now has only a 30-watt power source and it needs to get to 250 watts for cost-effective production. That would require a nearly tenfold improvement. Another issue is dealing with defect control on the EUV mask.

As he described the process, it seems almost like science fiction: You start by spraying molten tin at 150 miles per hour, hit it with a laser in a pre-pulse to distribute it, blast with another laser to create a plasma, and then bounce the light off mirrors to create the actual light beam and make sure it hits the wafer at the right point. He compared this with trying to a hit a baseball in a one-inch zone into the exact same spot in the stands 10 billion times a day.

IBM is working with lithography maker ASML and light source maker Cymer (which ASML is in the process of acquiring) to help speed EUV to market. The research facility in Albany is designed to be a "center of excellence" and IBM is now hoping to get tools in there by April. Patton said this will not be ready for 14nm or 10nm production, but may be for 7nm or later.

In the meantime, IBM is doing a lot of work with improving yields using multiple patterning, which involves using multiple masks. At 20nm, this involves double-patterning, where multiple masks are used to create the patterns. But to make this efficient requires a lot of work, so IBM has been working with the tool design (EDA) vendors so chip designers can take a standard cell design flow or create a custom flow, but still be more efficient.

At 10nm, he talked about using other techniques, such as sidewall image transfer (SIT) and directed self-assembly, where chemistry helps the layout of the transistor. The idea here is that instead of quadruple patterning, you can still do double patterning, which should be much less expensive.

Patton also spent a lot of time talking about how new device structures are needed. Existing FinFETs struggle from performance and variability issues, and but IBM is working on creating narrower bands to improve these issues.

At 7nm and beyond, he said, new device structures will be needed, such as silicon nanowires and carbon nanotubes. Carbon nanotubes have the potential to offer a tenfold improvement in either power or performance, but it has its own challenges, such as the need to separate out metallic from semiconductor carbon nanotubes and to place it on the right place on the chip. IBM recently announced that it now has more than 10,000 working carbon nanotubes on a chip.

Another area of interest is improving the interconnects, and Patton said that between 4nm and 8nm, the industry will move to nanophotonics. He discussed IBM's recent demonstration of a chip that combines photonics with silicon.

Ultimately, the goal is to integrate 3D and photonics together on a single chip. Patton concluded by talking about a chip he'd like to see with three planes: one with logic with about 300 cores; another with memory (with 30GB of embedded DRAM); and another photonic plane, providing an on-chip optical network.

Globalfoundries and Samsung Promise Full Production of 14nm Wafers in 2014

Representatives of both Globalfoundries and Samsung talked about how they were meeting the challenges of moving to 14nm and FinFETs.

Mike Noonen, executive vice president of marketing, sales, quality and design for Globalfoundries, talked about how the company is introducing a low-power 20nm process this year. It has already announced its 14XM process, which uses 14nm FinFETs with a more cost effective back-end. He said Globalfoundries expects to have early 14nm production this year, with full production of the 14XM process in the first half of 2014.

Among other things, Noonen (above) talked about partnerships at 14XM, including working with Synopsys on design tools, Rambus for interconnects, and ARM with its Artisan physical IP. He said a dual-core Cortex-A9 shows 62 percent power reduction or 61 percent performance improvement on 14XM compared with the foundry's 28SLP process.

Looking even further forward, Globalfoundries is expanding its Fab 8 in Malta, NY, and hopes to have full production of 10nm (10XM) in the second half of 2015.

K.H. Kim, executive VP of Samsung Electronics, who heads Samsung's foundry operations, said that a lot of people in the industry were skeptical of the Common Platform Alliance's "gate-first" approach to high-k/metal gate manufacturing, but that it was "really successful" in helping the company increase battery life and performance for mobile processors.

The company is ready to offer 14nm FinFET technology, as sub-20nm planar technologies cannot deliver acceptable performance. Kim (above) said there are three main challenges with FinFET technologies: dealing with process variations, channel width issues, and 3D modeling and extraction. But between IBM, Samsung, and Globalfoundries, Samsung has the leading number of patents and publications in 3D technology and thus the Common Platform group has addressed these challenges.

In particular, Kim talked about an "ISDA process development" to address variation and parasitic resistance; creating a development kit through work with UC Berkeley, CMG and tools vendors Synopsys, Cadence, and Mentor Graphics; and licensing IP from ARM, Synopsys, and Analog Bits to make it easier for chip designs to create 14nm System-on-Chip designs.

Working with ARM and Cadence, he said Samsung has created the first Cortex-A7 designs with FinFETs, and is ready to offer FinFETs to its customers. This year is mainly a year for validation and design, Kim said, with full production coming next year. He also noted that Samsung currently has two foundries, S1 in Korea and S2 in Austin, Texas. It is building a new fab in Korea aimed at 20nm and 14nm production, which is slated to start operation in late 2014 or early 2015.

In a question-and-answer session, Cadigan addressed the issues of moving to 450 mm wafers for producing chip, as compared with the 300 mm wafers that are now common. He noted a new consortium developing 450 mm technology in Albany, NY, and said that while the time is still up in the air, he expects industry adoption of 450mm will be "toward the latter part of this decade." He said he would expect EUV to come to the market first in 350mm and shortly thereafter at 450mm.

Noonen concluded that session by calling chip-making "the most complex business in the history of humankind," and it's clear that it involves a series of amazing technology breakthroughs.

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