Verilog Source Code Obfuscator

The Verilog Obfuscator tool scrambles Verilog source code
to make it very difficult to understand or reverse-engineer (example).
This provides significant protection for source code intellectual property that must be shipped to a customer.
It is a member of SD's
family of Source Code Obfuscators.

Topics

Semantic Designs- Our Goal

To enable our customers to produce and maintain timely, robust and economical software by providing world-class Software Engineering tools using deep language and problem knowledge with high degrees of automation.