Multi-core analysis made easy with the Nexus 5001 debug spec

In System on Chip (SoC)
architectures, the ability to effectively analyze problems and optimize
operations using real time in-system instrumentation is recognized as
one of the most effective methods for completing product development.

Perhaps nowhere is this need more prevalent than for multi-core architectures, since
this is an areas where traditional processor simulation and system
analysis methodologies tend to break down when faced with issues such
as concurrent programming and multiple processor flows, asynchronous
operations, core-to-core integration issues, etc.

Real (either prototype or production) hardware provides the best
source of information for this type of analysis, but often suffers from
visibility into functionality of the system, such as processor
instruction flow and data movement on embedded buses, which are not
typically made available at the pin IO. Increasing the visibility of
these embedded operations typically requires an instrumentation
subsystem.

Debug solutions vary greatly with different IP vendors, which can
make integrating debug and instrumentation systems for heterogeneous
multi-core architectures difficult. In this is dynamic area, the most
mature standardized solutions addressing system instrumentation and
debug are those based on IEEE 5001, also widely referred to as Nexus.

Some background on Nexus 5001
The initialIEEE 5001 Nexus
specification was developed in 1999 is an IEEE standard for debug
interfaces of embedded systems and processors, and has since been
implemented in numerous devices.

Unlike other debug solutions, that are typically proprietary to a
processor or tools vender, Nexus is openly defined and consistently
supported by a variety of tools vendor and across a range of processor
cores. Nexus standards are commercially supported by the Nexus 5001
Forum, which includes silicon suppliers, tools developers, IP
companies, and end users. [1]

Nexus was developed to provide extended debug capability, addressing
the limitations of JTAG (IEEE 1149.1) when used for
data intensive analysis operations such as trace and calibration. While
JTAG remains a widely used interface for on-chip debug, its serial
architecture has inherent limitations in supporting the speed and
bandwidth needed in analysis of modern devices.

Nexus is compatible with JTAG, and in basic run control modes, can
be implemented using only a JTAG serial port; but more significantly,
Nexus supports the use of high bandwidth interfaces to efficiently
transport data between the silicon targets and debug tools. Wider
bandwidth and higher speed data interfaces allow for simpler and more
powerful debug interfaces than JTAG based debug architectures.

This has significant advantages for multi-core systems, where larger
mounts of data can be needed for analysis.. Multi-core debug is a
significantly more complex and data intensive analysis problem than
single core debug, since in addition to having to debug the application
software for each processor core, there are new considerations related
to the communications between processors, multiple processors sharing
of common resources (memory peripherals, etc.), synchronization for
systems where processors or buses may not be running the same speed,
etc.