I'm running the AD9361 in TDD mode (adi-fmcomm2.dtsi is attached) and I notice that in Manual gain mode the large and small ADC overranges flags and digital saturation flag are set on every IQ collect, even if the gain is 1dB. The actual data looks OK though.

I was able to fix this by commenting out the following two following two SPI writes in ad9361.c (also attached)

When the device enters the RX state from ALERT (be it TDD, FDD, or FDD IND) the ADC will enable and will set the Over-range Signals (0x2B8 & 0x2B9). These can be seen on the CTRL_OUT signals also

If these signals are not reset using either a gain change, or using bits 0x107[D7&D6] they will remain high (even if input power is not breaching the thresholds)

In Slow AGC and Fast AGC Mode, the AD936X automatically resets this signals after the AGC Attack Delay (0x022). The device does this by asserting and de-asserting the 0x107[D7 & D6] bits. This can be seen on the CTRL_OUT signals.

In MGC Mode, the device does not assert the reset bits. Thus, the Over-range signals will remain high unless a gain change occurs or the user manually resets the detectors with writes to 0x107[D7&D6].

It should be made clear to users that intend on using MGC that the ADC and LMT Detectors must be manually reset (with a gain change or with a SPI write to 0x107) after entering RX state.

When the device enters the RX state from ALERT (be it TDD, FDD, or FDD IND) the ADC will enable and will set the Over-range Signals (0x2B8 & 0x2B9). These can be seen on the CTRL_OUT signals also

If these signals are not reset using either a gain change, or using bits 0x107[D7&D6] they will remain high (even if input power is not breaching the thresholds)

In Slow AGC and Fast AGC Mode, the AD936X automatically resets this signals after the AGC Attack Delay (0x022). The device does this by asserting and de-asserting the 0x107[D7 & D6] bits. This can be seen on the CTRL_OUT signals.

In MGC Mode, the device does not assert the reset bits. Thus, the Over-range signals will remain high unless a gain change occurs or the user manually resets the detectors with writes to 0x107[D7&D6].

It should be made clear to users that intend on using MGC that the ADC and LMT Detectors must be manually reset (with a gain change or with a SPI write to 0x107) after entering RX state.

When the device enters the RX state from ALERT (be it TDD, FDD, or FDD IND) the ADC will enable and will set the Over-range Signals (0x2B8 & 0x2B9). These can be seen on the CTRL_OUT signals also

If these signals are not reset using either a gain change, or using bits 0x107[D7&D6] they will remain high (even if input power is not breaching the thresholds)

In Slow AGC and Fast AGC Mode, the AD936X automatically resets this signals after the AGC Attack Delay (0x022). The device does this by asserting and de-asserting the 0x107[D7 & D6] bits. This can be seen on the CTRL_OUT signals.

In MGC Mode, the device does not assert the reset bits. Thus, the Over-range signals will remain high unless a gain change occurs or the user manually resets the detectors with writes to 0x107[D7&D6].

It should be made clear that intend on using MGC that the ADC and LMT Detectors must be manually reset (with a gain change or with a SPI write to 0x107) after entering RX state.