Using the following 2 arguments can't we conclude that the counter is Synchronous::

1)

Assume that the counter and gate delays are negligible

If counter delay is assumed to be negligible, then this counter is definately a synchronous counter as in case of asynchronous counter, for an N bit Asynchronous counter, the total propagation delay is N*Tp where Tp is the individual delay of each flip flop involved in counter.

Also, when this is synchronous counter, as soon as the output of bits reaches, 0101, clear logic gets activated and "Assuming no delays" this will quickly make the output appear 0000 and we won't get to see 5 as output of the counter.

To see 5 as the output, either we need to make clear logic work at 6 or we need to add delay to clear logic equal to 1 time period of clock pulse. Till, the next clock pulse comes, just before that our clear logic can be switched on and set counter to 0.

So answer here is (C)

2)

the output of 0101 from the counter isn't stable. I.E. the output lines of the counter will show 0101 but will immediately be reset to 0. I have drawn this conclusion from the table which states that when clear is 1, the counter will not care about the clock or any other parameter and clear the counter to 0.

I am under the impression that only the stable outputs of a counter can be considered as valid sequences.

@ bikram sir ,
but Sir it is not going to effect clr bcz clr has connection with output not input .... a/c to me at clk =0 the counter value was 0011 and at clk=1 it resets it to 0000 and then
when it reached to 0101 then it clears .

we get clear when we reach 0101 is true , but that state won't exist till next clock , before next clock pulse value will be reset to zero , whenever clock applied it goes to 0001 because in the last cycle itself it clear the output of counter to zero.

Praveen sir, I think C should be the answer as the output of 0101 from the counter isn't stable. I.E. the output lines of the counter will show 0101 but will immediately be reset to 0. I have drawn this conclusion from the table which states that when clear is 1, the counter will not care about the clock or any other parameter and clear the counter to 0. (also stated by pramod).

I am under the impression that only the stable outputs of a counter can be considered as valid sequences. Is this assumption wrong? Please advice.

If counter delay is assumed to be negligible, then this counter is definately a synchronous counter as in case of asynchronous counter, for an N bit Asynchronous counter, the total propagation delay is N*Tp where Tp is the individual delay of each flip flop involved in counter.

Also, when this is synchronous counter, as soon as the output of bits reaches, 0101, clear logic gets activated and "Assuming no delays" this will quickly make the output appear 0000 and we won't get to see 5 as output of the counter.

To see 5 as the output, either we need to make clear logic work at 6 or we need to add delay to clear logic equal to 1 time period of clock pulse. Till, the next clock pulse comes, just before that our clear logic can be switched on and set counter to 0.

@rahul ,here when Load will be set to $1$ then we will load this input $0011$to output.But you can see here Load is set to 0 and it will never change throughut the functionality so we are not using this input at all.

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+19 votes

(C) is the correct answer!

$Remark:$
1. If $clear = 1$, counter will be reset to 0000 $\underline{\text{without any delay, and counter doesn't count 5}}$.
2. If $load=1$, counter will be loaded with the input 0011, but note that $\underline{\text{counter counts 5 in this case}}$ unlike clear input.
3. Counter counts from $0$ to $4$.
4. Clear and Load are direct inputs, it means they can be applied to the counter without using any pulse.

When the output reaches the count of 1001, both A0 and A3 become 1, making the output of the AND gate equal to 1. $\underline{\text{This condition activates the Load input; therefore, on the next clock edge the register does not}}$ $\underline{\text{count, but is loaded from its four inputs}}$. Since all four inputs are connected to logic 0, $\underline{\text{an all‐0’s value is loaded into the register following the count of 1001}}$. Thus, the circuit goes through the count from 0000 through 1001 and back to 0000, as is required in a BCD counter.

$\underline{\text{ In Fig (b), the NAND gate detects the count of 1010, but as soon as this count occurs,}}$ $\underline{\text{the register is cleared. The count 1010 has no chance of staying}}$ $\underline{\text{on for any appreciable time, because the register goes immediately to 0}}$

If $clear=1$, then clear the counter.

If $clear=0, load = 0, count = 1,$ counter counts.

$load = 1,$ loads the input to the counter.

If $load = 1$, then counter will be loaded with $i/p = 0011$

to the given counter, $count = 1 \\ load = 0 \\ clock = \uparrow$

$\underline{\text{Note:}}$ If o/p of $AND$ gate is led to $load$, then counter will be loaded with $0011$.

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+14 votes

Using the following 2 arguments we can conclude that the counter is Synchronous::

1)

Assume that the counter and gate delays are negligible

If counter delay is assumed to be negligible, then this counter is definately a synchronous counter as in case of asynchronous counter, for an N bit Asynchronous counter, the total propagation delay is N*Tp where Tp is the individual delay of each flip flop involved in counter.

Also, when this is synchronous counter, as soon as the output of bits reaches, 0101, clear logic gets activated and "Assuming no delays" this will quickly make the output appear 0000 and we won't get to see 5 as output of the counter.

To see 5 as the output, either we need to make clear logic work at 6 or we need to add delay to clear logic equal to 1 time period of clock pulse. Till, the next clock pulse comes, just before that our clear logic can be switched on and set counter to 0.

2)

The output of 0101 from the counter isn't stable. I.E. the output lines of the counter will show 0101 but will immediately be reset to 0. I have drawn this conclusion from the table which states that when clear is 1, the counter will not care about the clock or any other parameter and clear the counter to 0.

I am under the impression that only the stable outputs of a counter can be considered as valid sequences.