Tensilica is known for its customizable microprocessor core, the Xtensa configurable processor. Other products include: HiFi audio/voice DSPs with a software library of over 225 codecs from Cadence and over 100 software partners; Vision DSPs that handle complex algorithms in imaging, video, computer vision, and neural networks; and ConnX family of baseband DSPs ranging from the dual-MAC ConnX D2 to the 64-MAC ConnX BBE64EP.

Tensilica was founded in 1997 by Chris Rowen (one of the founders of MIPS Technologies) and was initially staffed by former employees of several other Silicon Valley processor and electronic design automation companies. It employed Earl Killian, who contributed to the MIPS architecture, as chief software architect for several years.[1] On March 11, 2013, Cadence Design Systems announced its intent to buy Tensilica for approximately $380 million in cash.[2] Cadence completed the acquisition in April 2013, with a cash outlay at closing of approximately $326 million. [3]

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Cadence Tensilica develops SIP blocks to be included on the chip (IC) designs of products of their licensees, such as system on a chips for embedded systems, particularly in mobile, home entertainment, and communications. Tensilica processors are delivered as synthesizable RTL for easy integration into chip designs.

An Xtensa processor can be customized into anything from a small, low-power cache-less microcontroller to a high-performance 16-way SIMD processor, 3-issue VLIWDSP core, or a 1 TMAC/sec neural network processor. All Cadence standard DSPs are based on the Xtensa architecture.

Using the supplied customization tools, customers can extend the Xtensa base instruction set by adding new user-defined instructions. Extensions can include SIMD instructions, new register files, and additional data transfer interfaces for multiprocessor communication. After the final processor configuration is made and submitted, the Tensilica processor generator service builds the configured Xtensa IP core, processor design kit, and software development kit. This process is highly automated so designers can quickly experiment with different instruction additions, testing the performance improvements and power trade-offs of the various alternatives.

The Xtensa instruction set is designed to meet the diverse requirements of dataplane processing. This 32-bit architecture features a compact 16- and 24-bit instruction set with modeless switching for maximum power efficiency and performance. The base instruction set has 80 RISC instructions and includes a 32-bit ALU, up to 64 general-purpose 32-bit registers, and six special-purpose registers.

Microsoft HoloLens uses special custom-designed TSMC-fabricated 28nm coprocessor that has 24 Tensilica DSP cores. It has around 65 million logic gates, 8MB of SRAM, and an additional layer of 1GB of low-power DDR3 RAM.[8]