Well, all sounds good and cheesy as said! Claims were made that the proposed bailout was the need of the hour and that it was needed very badly and a failure to do so will turn the economic crisis into a catastrophe. But one question everyone had was the moral dilemma that faced the Congress and the White house in the question that if the recipients of the stimulus package should continue to outsource jobs :-). The main objective of the bailout plan was in the creation of jobs for Americans.

Will American citizens only be the sole benefactor of the bailout package? Outsourcing companies outside the U.S. including here in India and the Philippines benefited from the demand of manpower for jobs in consumer services like jobs in research, bill payment and collection, credit analysis and investment banking. The logical conclusion was that companies should be allowed freedom to manage as what they may deem good for their business. Every outsourcing company cannot possibly take all the jobs that a U.S. company requires.

In an era where companies need to stay competitive, not to earn big but just to survive, outsourcing can complement the operations of a company as it is an efficient way to run the company’s operations. The first step a troubled company takes is to save money and instantaneously reduce cost. A company should compare their operations to their competitors to see exactly what is lacking and continuously adapt. There are issues that the stimulus package is not a debate on protectionism and taxpayers are not served well with the continuing export of jobs by the very companies that need the bailout package. The jobs from financial institutions that are in the center of attention are in research, banking and back office.

Meanwhile, President Obama is also aware that revolutions in communication and technology has sent jobs to any place in the world with Internet connection and according to him the fact that the world is more competitive cannot be reversed. Outsourcing of American jobs overseas cannot be reversed and U.S. workers need to compete for jobs with other people on the other side of the globe. This is how globalization is defined. The government must invest in research and innovation to create jobs and industries as the country’s problems on economic front cannot be overcome by building protectionist walls.

In contrast what is speculated to happen in the next couple of months is that, the H1-B's will be laid off in the U.S. This laid off workforce, will be re-hired in India to a great extent in the coming months due to outsourcing by the U.S firms.

Lets wait and see how much the U.S can manage without the H1-B's in general.

In india, being laid off is a taboo. Though most of us have thought through some sort of a plan, it will be foolish to think that gone are the days to pretend this is not happening. I personally having gone through that phase in the US during the last recession, it is somewhat familiar to me in the post-layoff days while saying i am not completely immune.

Today there is a generation of us in the indian workforce, totally unfamiliar with layoffs, and totally unfamiliar with the idea that a job is actually 100% insecure. The good news about this is that there is not a huge difference between someone laid off and someone not laid off in that all of us feel vulnerable, scared and cheated in some ways.

Which also means that some etiquette has to be followed in that it is different than it used to be for talking to someone who’s been laid off.

1. Never ask "how's the job hunt?" Because the job hunt doesn't change much from day to day, but it's far more demoralizing to report that in someones face.

2. Ask about things like hobbies, kids, and their health – all interesting topics to talk about.

3. Talk about the current affairs & industry news in general - Tell the person what you're working on. Trends you're hearing about. Personnel shifts you've seen. Also, gossip counts as news. Workplace gossip is a positive way to bond. Forget what your mom told you about gossip being bad karma. In this case, gossip equals good karma.

4. Offer atleast one good contact - You need not pretend that connecting in LinkedIn or facebook is going to help his cause, because he should have been building the network long before the layoff loomed. But you could offer up one person you know well who could talk with the person.

5. Acknowledge trouble with the significant other - On this is tricky! More men are getting laid off than women, which puts women in a bad spot because most women choose a husband thinking he'll earn more. Today it's a fair game, and even compassionate to acknowledge.

6. Don't be shy of gratitude - Tell a co-worker who’s been laid off that you miss him or her. And what you miss. It's hard to keep up morale when you're looking for a job. And so often we forget what we are talented at because rejection makes us feel totally un-talented.

Harry Gries has announced what could be the first SaaS EDA roundtable. He had been discussing this for a while on his blog on how this new trend in IT could be leveraged for the EDA industry and to a sort of feasibilty analysis. This will be held at 2009 DVCon and below are the details.

The SaaS and Cloud Computing Roundtable will be held from 6:30 - 8:00 pm on Wed Feb 25th in the Monterey/Carmel rooms at the San Jose Doubletree Hotel. This is immediately following the DVCon reception down the hall, so grab a drink and a bite and then wander on over.

The format will consist of 5 brief (presentations from people involved in various perspectives in SaaS and cloud computing for EDA:

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Why don't our governments force all mobile phone companies to use a single connector on their chargers, in order to eliminate the mountains of e-waste generated by switching chargers every time you switch phones. Transformer bricks with esoteric connectors are the most common form of electronic crap we see on street-vendors' blankets around the world (literally thousands and thousands of them in Mumbai's Chor Bazaar and street and box shops in Bangalore), and given that they all put out nearly the same voltage and amperage, it really does seem like pure waste.

LG Electronics and Intel have announced a collaboration based on Intel's Moorestown silicon and the Linux Moblin v2.0 software platform at the Mobile World Congress in Barcelona Yesterday. The future LG device, which is being described as a smartphone is expected to be one of the first Moorestown designs to market.

[Via Slashdot] On CNet.com, Brooke Crowthers has a review of some flops in the chip-making world — from IBM, Intel, and AMD — and the hype that surrounded them, which is arguably as interesting as the chips' failures.

“Everyone should get a lecture on why their first design will not work in the field.” Here are some of the very few but primary reasons that getting a single design to work correctly for a few minutes in a lab is much easier than getting thousands of systems to work correctly for months at a time in dozens of countries around the world.

1. Did you forget to force your “unreachable” state to transition to an initial (reset) state? Clock glitches, power surges, radiation, high EM etc will occasionally cause your system to jump to a state that is not defined. When this happens, your design should reset itself, rather than crash or generatel illegal outputs.

2. Do you have internal registers that you cannot access or test? If you can set a register you must have some way of reading the register from outside the chip. In many cases inaccessible or stale registers can cause unexplained system behavior that cannot be debugged. Only full system reset can recover the system to a sane state.

3. Is there any chip in the system that controls your chip? It could be possible that this other chip is buggy. All of your external control lines should be able to be disabled or controlled, so that you can isolate the source of the problem.

4. Not enough decoupling capacitors on your board? The analog world is cruel and very unusual. Voltage spikes, current surges, crosstalk, etc can all corrupt the integrity of digital signals. Trying to save a few cents on decoupling capacitors can cause headaches and significant financial costs in the future.

5. Did you only test your system in the lab, not in the real world? As a product, systems will need to be run for months in the field to encounter all known and unknown issues. Simulation and simple lab testing won’t catch all of the weirdness of the real world. This will be the limit of real world stress test.

6. Did you not adequately test the corner cases and boundary conditions? Every corner case is as important as the main case. Even if some weird event happens only once every six months, if you do not handle it correctly, the bug can still make your system unreliable, unusable and of-course unsellable.

DES MOINES, Iowa - U.S. Immigration and Customs Enforcement (ICE) agents arrested 11 individuals in seven states Wednesday as part of an investigation into suspected visa and mail fraud. Matthew G. Whitaker, U.S. Attorney for the Southern District of Iowa, announced the operation, which was carried out by federal, state and local law enforcement agencies in Iowa, California, Massachusetts, Texas, Pennsylvania, Kentucky and New Jersey.

To meet the International Technology Roadmap for Semiconductors (ITRS) forecast that device with gate length of sub-10nm will be fabricated by 2016 advanced gate stacks with high-k dielectrics are of intensive research interests. Stringent power requirements in the chips also dictate replacement of silicon dioxide as it has already reached the direct tunneling regime. Currently, many different high-k materials have been explored to replace the silicon dioxide as gate dielectrics. So, what is it that makes High-K dielectrics so attractive in today's technology scaling raodmaps :-)?

In cutting edge silicon nanoelectronics both high-k and low-k dielectrics are needed to implement fully functional and very high-density integrated circuits, although for drastically different reasons. High-k dielectrics are needed in MOS gate stacks to maintain sufficiently high capacitance of the metal (gate)-dielectric-Si structure in MOS/CMOS transistors. Due to the continued scaling of the channel lengths, and hence reduced gate area, the need to maintain sufficient capacitance of the MOS gate stack was met by gradual decrease of the thickness of SiO2 gate oxide Obviously such scaling cannot continue indefinitely as at a certain point gate oxide will become so thin (thinner than about 1 nm) that, due to excessive tunneling current, it would stop playing the role of an insulator. Hence, dielectric featuring k higher than 3.9, i.e. one assuring same capacitive coupling but at the larger physical thickness of the film, must be used instead of SiO2 as a gate dielectric in advanced MOS/CMOS integrated circuits.

On the opposite end of the spectrum finds itself a multi-layer metallization scheme in which inter-layerdielectric (ILD) is used to electrically insulate metal lines. In this case it is of critical importance that the capacitive coupling between adjacent interconnect lines is as limited as possible. Hence, a low-k dielectric must be used to assure as little capacitive coupling (low “cross-talk”) between interconnect lines as possible.

Whether the problem is with high-k dielectrics for MOS gates or low-k dielectrics for ILDs, lack of viable technical solutions in either of these areas will bring any future progress in mainstream silicon technology to a screeching halt. The reliability requirements and challenges of some short-listed high-k dielectrics such as HfO2 and HfSiO2 are widely used by Intel for its 32nm technology nodes for its upcoming processors.

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This is a story about Raj, name changed for privacy reasons. When I first met him he was a student and an intern in my team. His personality fit exceptionally well into the culture and he worked very hard while in the company. The job was one that I liken to a grudge job for most of us who had to help fill-in during rush times at our start-up. The task was repeatedly running simulations for many in my team and to collate the results while writing some scripts to ease his job, do an analysis that justifies the purpose of the design and share it with the team. For the most part to start of with, he had no clue what he was doing. The team members were least helpful except for the manager who hired him and who frequently challenged his intellect with logic puzzles that he had no problem with :-)

From an Intern to a full time Design Engineer, the transition was seamless.

Raj stuck with that job through the temporary time which I think was initially 6 months then extended for another 3 months to accommodate for his masters thesis and at the end we offered him a permanent position doing the same tasks! He came on-board and meshed right into the culture. He had built relationships the whole time he was an Intern and the transition to full-time was that much easier since he already had friends at work. His tasks and role remained the same for a while.

At a year of service with the company Raj took on a new role at work. At a start-up there all sorts of opportunities to wear new hats and he transitioned to a bigger role. We were a small group (<10) and didn’t have an official RTL expert in-house. So Raj took on this role while creating new RTL blocks for existing Matlab designs and simultaneously learned Verilog since he came from a VHDL background. As we grew as a company Raj put together FPGA Boards and setup the system setup for system level simulations in a Emulation environment.

But EVERY Job Is Temporary

The hard part of this story is that with the downturn in the economy of 2000-2001 our business had to change to maintain control of our destiny and one of those changes was Raj was laid off along with 50% of our colleagues. The layoffs are fresh in my mind. Good friends, including Raj, who had put in so much sweat equity to stand this company up were suddenly gone. Most of those that were gone pondered daily questioning why and what are they going to do, but Raj’s approach appeared to be the same as when he was an Intern. In his words “I’m looking for the next opportunity”.

In any economy, but especially one like our current situation take any position you can get and once you get in look for those opportunities that allow you to shine. All jobs/positions are created because there is a need within the company. So if it’s running simulations blindly or writing trivial scripts that challenge the intellect of you superiors, give it your best and create a place for yourself within the organization.

These chip art images were either extracted through lapping techniques, magnification and/or Polaroid capturing. Typically chips have a unique "signature" or a identification number to recognize and expect to be logic, memory, gates, or a product of some kind. However, these signatures are the designer's, the engineer's and in some cases a company logo. They have left their mark in and for history. The chip collection is complemented with imagination which takes no space on a shelf, requires no conservation and cannot typically be exhibited.

... a historical and operational perspective on how these photographs are captured: laboratory engineers and technicians capture these images on a catch-as-catch-can basis... many of these photographs are years old and cannot be [easily] identified... the images were simply posted on a board and then [staff] went about the business at hand ... - Integrated Circuit Engineering Corporation

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Development of semiconductor heterostructures used in high-speed and opto-electronic systems; The Nobel Prize in Physics 2000.

Zhores I. Alferov was born in Vitebsk, Belorussia, USSR, on March 15, 1930. In 1952, he graduated from the Department of Electronics of V. I. Ulyanov (Lenin) Electrotechnical Institute in Leningrad. Since 1953 he has been a staff member of the Physico-Technical Institute where he held consecutively the following positions: junior researcher (1953–1964), senior researcher (1964–1967), head of the laboratory (1967–1987), director (1987–present). He earned scientific degrees: a candidate of sciences in technology in 1961 and a doctor of sciences in physics and mathematics in 1970, both from the Ioffe Institute.

Since 1962 he has been working in the area of III–V semiconductor heterostructures. His outstanding contributions to physics and technology of III–V semiconductor heterostructures, especially investigations of injection properties, development of lasers, solar cells, LED's, and epitaxy processes have led to the creation of modern heterostructure physics and electronics.

In 1973 Zh. I. Alferov took over the chair of optoelectronics at the St Petersburg State Electrotechnical University (former V. I. Ulyanov (Lenin) Electrotechnical Institute) and in 1988 he was appointed to Dean of the Faculty of Physics and Technology at the St Petersburg Technical University.

He was elected a corresponding member of the USSR Academy of Sciences in 1972 and Academy's full member in 1979. From 1989 onward, he has been Vice-President of the USSR (Russian) Academy of Sciences and President of its St Petersburg Scientific Center.

He is Editor-in-Chief of a Russian journal, Pis'ma v Zhurnal Tekhnicheskoi Fiziki (English-language version—Technical Physics Letters) and a member of the Editorial Board of a Russian journal Nauka i Zhizn' (Science and Life).