FDRE_1 is a D-type flip-flop with data (D), clock enable (CE), and
synchronous reset (R) inputs and data output (Q). The synchronous
reset (R) input, when high, overrides all other inputs and resets
Q to low on a falling clock edge. The data on the D input is
propagated to Q on a falling clock edge when R is not high and when
CE is high.

cellInterfaceDeterminesUniqueNetlistStructure()
When false, the default behavior of this method, each cell will list itself
separately in a netlist, guaranteeing that the netlist will not have invalid
data at the expense of a larger file-size.

Constructs a new fdre_1_g, connecting each Wire to the port whose name is given by the accompanying String parameter
The initial String parameter specifies the instance name.
The final String parameters set the generics , INIT

Constructs a new fdre_1_g, connecting each Wire to the port whose name is given by the accompanying String parameter
Note: this includes enough wires for the implicit ports.
The final String parameters set the generics , INIT

Constructs a new fdre_1_g, connecting each Wire to the port whose name is given by the accompanying String parameter
Note: this includes enough wires for the implicit ports.
The initial String parameter specifies the instance name.

Constructs a new fdre_1_g, connecting each Wire to the port whose name is given by the accompanying String parameter
Note: this includes enough wires for the implicit ports.
The initial String parameter specifies the instance name.
The final String parameters set the generics , INIT

fdre_1_g

Constructs a new fdre_1_g, connecting its ports as given by the String-Wire pairs in the ArgBlockList. Any generic assignments are made through String-String pairs in the ArgBlockList.
The initial String parameter is the instance name.

Parameters:

parent - The parent Cell to the fdre_1_g

instanceName - The instance name of the fdre_1_g

abl - The list of String-Wire pairs for port assignments, and String-String pairs for generic assignments.

Method Detail

clock

Users define synchronous behavior in this method using standard JHDL constructs.
The simulator detects whether clock() has been implemented by calling this
function directly and checking for an exception.

cellInterfaceDeterminesUniqueNetlistStructure

When false, the default behavior of this method, each cell will list itself
separately in a netlist, guaranteeing that the netlist will not have invalid
data at the expense of a larger file-size. Overriding this method to return true
allows JHDL to save memory and netlists to be smaller by sharing the netlist
structures that are guaranteed to be identical.
NOTE: Do not override this unless every possible condition responsible for structural
differences in a class (types and amount of children cells created, and arrangements
of wires connected to ports) is included in the cellInterface[] of that class.