Archive for March, 2009

What does an obscure announcement about beam epitaxy have to do with system-level design?

Plenty, if you’re designing optical network systems (ONS). Such systems continue to find applications in the macro world of computer network and the micro world of Micro-Electro-Mechanical (MEM) chips. The later requires an understanding of microphotonics, which deals with the direction of light on a microscopic scale.

From a material science standpoint, the really tricky part of micro-optics is in the growth of the appropriate epitaxial layers onto silicon wafers. Epitaxy refers to the method of depositing a monocrystalline film (or epitaxial layer) onto a monocrystalline substrate. The key phrase is “depositing a monocrystalline film,” which requires that similar crystalline structures must be grown (or enticed to grow) onto the surface of the silicon wafer. Epitaxy is used in silicon-based manufacturing processes for BJTs and modern CMOS devices, but also GaAs compounds.

Why am I rambling on about epitaxial layers? Aside from the fact that it’s interesting, measuring the purity of such layers was once part of my job. It’s easy to grow oxides on a silicon substrate – just leave the wafer exposed to air for a few hours. But theses are not the expitaxial layers that you want, especially for microphotonic applications. Growing ferroelectric expitaxial layers is needed for such applications, which, for a number of reasons, is a very difficult task.

Now you can understand why I was interested with the recent announcement from the Center for Nanoscale Materials (CNM) at Argonne National Laboratory.

“Complex Oxide Molecular Beam Epitaxy — This technology allows pure complex oxides films to be grown epitaxially; of special interest are films that are ferroelectric, ferromagnetic, or superconducting. Alternating layers can be deposited to allow the observation of novel properties at the boundary or interface.”

From the obscure world of epitaxy to the common world of optical networks, a good system-level designer must know it all. (Eat your heart out, James Burke.)

There are three critical parameters to which all hardware engineers must pay heed – power, performance and area. The equivalent parameters for software engineers are power (via hardware)-performance and size (memory). While these three elemental factors are dependent upon one another, perhaps the most critical is power. Without power, electronics serve no function aside from esthetics.

Power covers a broad range of topics, from creation and conversion-amplification to delivery. In the chip, package and board world, power design is a nontrivial exercise – just look at the proliferation of tools, formats and methodologies.

Power designs represent real pain-points for hardware and software engineers alike. The last several decades have seen an increasing concern for the shrinking power budgets in chip designs. Today’s consumer movements toward green technology and ever increasing mobility means that low power has become the number one design issue for system architectures through RTL and beyond – to the pack and board level areas, as well.

The challenge of low power, coupled with the increase urgency for such designs, makes the decision to offer a low-power community portal a simple one. The breadth of industries represented by our sponsors – from EDA and IP to even hardware – is a further indication of the importance of this market.

As always, Ed, myself and all our editors look forward to hearing from our readers. Let us know what pain-points you are feeling and what topic areas you’d like to see. Cheers!