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The use of simulation software was instrumental in optimizing the performance of an IC for millimeter-wave communications at E-band frequencies.

With the growing demand to wirelessly communicate voice, video, and data from point to point, effective use of European Telecommunications Standards Institute (ETSI) E-band frequencies from 71 to 76 GHz and 81 to 86 GHz has become imperative. A number of different high-frequency components are vital for building E-band communications systems, including gallium-arsenide (GaAs) pseudomorphic high-electron-mobility-transistor (pHEMT) frequency doublers, quadruplers, and power amplifiers (PAs).

Suitable output-power levels and power-added efficiency (PAE) are concerns for the E-band amplifiers, while power levels of +15 dBm or higher have been shown to be helpful for the local oscillators (LOs) that feed linear frequency downconverter and upconverter mixers for high quadrature-amplitude-modulation (QAM) radio systems and direct transmission for low QAM systems. Higher output power [more than +20 dBm (100 mW)] is desirable from linear E-band system PAs, with research and design communities both working toward achieving an ultimate goal of 1 W (+30 dBm) power at E-band system antennas.

In quest of circuitry for E-band systems, a grant from the Australian government brought together Australia’s Macquarie University, MACOM Technology Solutions, and WIN Semiconductors Corp. to partner on the development of a high-performance integrated-circuit (IC) process suitable for E-band use. To demonstrate its capabilities, the process was applied to the design of a Q-band-to-E-band frequency doubler and K-band-to-E-band quadrupler, including an E-band PA.

The doubler provides +15 dBm output power over the full ETSI E-bands. The quadrupler offers more power over a narrower bandwidth, as might be used for a radio system with an LO between the two E-band channels. The quadrupler delivers a maximum output level of +19.2 dBm. The PA generates more than +23 dBm (200 mW) output power over the two ETSI E-band frequency ranges, with maximum power of +24.2 dBm (265 mW).

WIN Semiconductor’s PP10 WIN process was chosen to fabricate these ICs, due to its high transition frequency, fT and high power capabilities. Unfortunately, the team had no previous experience correlating preproduction measurements of individual field-effect transistors (FETs) to production FETs, let alone to overall circuit performance, so the design and fabrication efforts would also be educational experiences.

Performance levels for the circuit designs for the doubler, quadrupler, and PA were simulated with Microwave Office® high-frequency design software from AWR Corp., using models extracted from multiple-bias S-parameter measurements on a small test transistor. The circuits were fabricated using the PP10 0.10-μm GaAs pHEMT process, with an fT of 135 GHz, transconductance of 725 mS/mm, and breakdown voltage of +9 VDC.

The doubler was a two-stage, Q-band amplifier that drove a single-ended doubling element consisting of a FET biased close to pinchoff, which in turn drove a four-stage, E-band PA. The quadrupler contained an additional K-band pre-amplifier and a K-to-Q doubling element. The output device in both circuits was a 4 x 50 μm transistor.

The power amplifier featured a four-stage, balanced topology with the final transistor in each arm being a 6 x 50 μm device customized for optimum balance among gain, channel temperature, and output power. The monolithic-microwave-integrated-circuit (MMIC) frequency doubler was 2750 x 1250 μm to fit the dicing requirements of other circuits on this wafer. The PA layout was similarly influenced by the size of adjacent circuits, and could be reduced in a production version.

A three-step process was used for the design of all circuits. In the initial step, a schematic-based circuit served as a design starting point, to provide performance levels roughly in agreement with targeted specifications. Linear design was primarily performed during this first pass, with the cursory inclusion of some nonlinear performance aspects. During the second step of the design process, individual subcircuits were laid out and the AWR EXTACT™ flow was used with the AXIEM® three-dimensional planar electromagnetic (EM) simulator from AWR to provide more accurate block-level design insights into the desired circuitry.

In the final step of the design process, critical portions of the entire chip-level metallization were run through the EXTRACT flow and compared to block-level simulations and overall target performance. Final verification of the design—including design-rule check (DRC) and layout versus schematic (LVS) operations—were performed with the AWR software before tape-out of the circuits for fabrication.