Join more than 400 international participants including leaders and executives from industry, academia, and government in this celebration of our industry and SEMICON Korea. Engage customers, peers, and important decision-makers at this exclusive networking event.

New application is rising- AI, Automotive in semiconductor industry and it is time to look it up for understanding its impact in semiconductor market. Also, China market is still interesting theme for our industry due to its potential and investment scale. You can explore these issues as well as semiconductor equipment and materials outlook in one place!

As device technology shrinks to sub-10 nm, we expect a lot of challenges in process integration. Thus, many chip makers are considering EUV lithography to mitigate process risk and to reduce process integration time. However, EUV lithography also has many technical challenges. On the other hand, 3D memory process also brings another technical issue in many aspects. Therefore, we believe the role of Metrology & Inspection is getting more and more important to enable sub-10nm and 3D device.

This year, celebrating its 10th anniversary, MI Forum will cover the theme as “MI: An Enabler of Future Devices” with technical experts from worldwide. We hope you can get better understanding on MI challenges and solutions for upcoming process technologies in the forum and build the network with industry leaders in MI Networking reception, which will be held after the forum as well.

Date: Feb 1(Thu), 2018

Time: 10:00-18:00

Room: #402, Conference Room (South), COEX

Theme: MI: An Enabler for Future Devices

Language: English and Korean (Simultaneous interpretation will NOT be provided​)​

MI Reception is a special event for MI industry to build the global networking through supply chain and to get together for business opportunities. More than 200 people including MI Forum attendees, speakers and MI Committee members are expected to attend.

This short course tutorial is designed as basic course for new engineers who is working at etching technology related area. With the practical lecture from device makers, equipment suppliers and academia, you will learn the hottest issues and challenges in plasma & etching process and fundamental technologies as well.

Advanced Lithography session of the STS 2018 will offer the opportunities to review the latest trends in the mainstream lithography technologies under the theme of "EUV High Volume Manufacturing and Beyond".

Recently there are a lot of progresses achieved in EUV and as a result EUV is getting considered as a manufacturing means more seriously than before. For the sake of the solid migration to the manufacturing phase, the readiness of each component of EUV will be reviewed during this meeting including overview, exposure tools, optics, material, mask, and process by the prominent leading figures of the corresponding area. In addition, the next generation EUV technologies like high-NA EUV and EUV double pattering will be discussed to disclose the potential issues and to prepare collaboratively throughout the industry.

Date: Jan 31(Wed), 2018

Time: 13:00-18:00

Room: #307, Conference Room (South), COEX

Theme: EUV High Volume Manufacturing and Beyond

Language: English (Simultaneous interpretation will NOT be provided)​​

In this session, we will be able to share the most up-to-date research and development results in the field of Advanced Materials and Process Technology which are the key enablers of the future semiconductor devices. Many prominent authors from the academia and industries will cover various functional materials research area and semiconductor devices not only in the view point of the fundamental but also for the mass production. Especially, topics regarding material innovation for semiconductor application will be highlighted and technical challenges for mass production will be discussed. Excellent 8 presentations including 3 outstanding invited talks will be given and will cover the major technical issues and the leading edge solutions.

Semiconductor scaling is becoming increasingly challenging, requiring more than mere conventional dimension scaling. Two different approaches can be taken at this moment. One approach is to find new specific applications, such as automotive and IoT, based on the current technology. Another approach is to use innovative device structures to overcome the limitations of the current structure. This session will discuss such challenges and the exciting future that lies ahead with distinguished 6 speakers from all of the world.

Date: Jan 31(Wed), 2018

Time: 13:00-16:50

Room: #317, Conference Room (South), COEX

Theme: Challenges to Future Device Technology

Language: English (Simultaneous interpretation will NOT be provided​​)

These days the semiconductor business is expanding more rapidly since Big Data and AI (Artificial Intelligence) technologies need plenty of chips as well as processor chips. Two technologies become the most promising ones for the future industry and they will change fundamentally the industrial structure and our normal lives all over the world. The skyrocketing needs for memories makes all chip makers to focus on scale down current DRAM, VNAND new memories. In addition, the high performance processors needs also more scale downed logic chips. As the scaling down is continuing, dry etching technology will confront the process limit eventually so it is the right time to discuss about the new etch technologies for overcoming the limit in this annual SEMICON symposium.

We prepared deep and wide touching on the critical and key etch technologies like new Pulsed Etch, ALE (Atomic Layer Etch), Ultra-high Energy Ion Etch, very-Low Temp. Etch and Etch Simulation technologies. These are essential technologies for solving the scaling down issue and, furthermore, for Big Data and AI era. We invited the academia and industry expertise who can share the vision and solutions for next generation etching technologies- please join us to gain keen insight of future.

Continuous shrinkage of device dimension to nm level requires new materials and novel device structure which demand a new paradigm in contamination control and planarization to improve the production yield and device reliability. CFM technology has become more critical in device manufacturing below 20 nm devices. Film loss-free and damage free cleaning technology face severe challenges for next-generation device fabrication. Also, CMP has grown to be one of the essential technologies for advanced node device fabrications such as FinFET, III/V materials and V-NAND. 7-nm logic technology is already under developing now, and CMP will play the leading role on patterning for sub-7 nm FEOL and MOL process steps. To overcome the new CMP challenges, the consumables should play a more critical role. The purpose of this session is to increase the level of understanding on current and future CFM/CMP technology.

Date: Feb 1(Thu), 2018

Time: 13:00-17:00

Room: #308, Conference Room (South), COEX

Theme: CMP & Cleaning for Emerging Technology

Language: English (Simultaneous interpretation will NOT be provided​)​

As packaging, wafer level and heterogeneous system assembly in general, electronic systems for future mobility, 5G, AI and Automotive are targeting to find solutions for those key critical aspects of packaging: Performance, Flexibility and Cost competitiveness. Those solutions will make huge connection among system and system such as sensor and logic, logic and memory, antenna and logic. So we are expecting to make a new vision era how packaging as a SIP, FOWLP, 3D IC, and 2.5D IC will open to new market as a heart of 4th industry generation. To address those, chip-packaging-system interaction needs to be better understood. The experts of device design, FABs engineering, packaging, and system need to move closer together. Materials and Equipments need to be developed and tested for electronic systems. Those are the challenging but this session is helping to share the recent advanced packaging information.

Date: Feb 1(Thu),2018

Time: 13:00-18:25

Room: #317, Conference Room (South), COEX

Theme: Advanced Packaging in a New Era

Language: English (Simultaneous interpretation will NOT be provided)​​

Smart automotive is driving a new market for semiconductor. Connected car and autonomous driving system need integrated system, advanced safety features, and infortainment- the value of chips are getting higher than ever in car industry. In a road to smart driving, the challenge of smart automotive is the challenge of semiconductor. As the industry expects to make a fully autonomous car by 2030, the collaboration with semiconductor industry will be essential. This forum will figure out how smart automotive are changing our driving experience and how the semiconductor plays the key role in the new smart world.

Date: Jan 31(Wed), 2018

Time: 14:00-17:30

Room: #402, Conference Room (South), COEX

Theme: Drive Smart

Language: Korean and English (Simultaneous interpretation will be provided)

Technology is evolving at lightning speed – faster than ever before. The increasing adoption of IoT technologies, robotics, automation, software and data analytics means that virtually all industries and sectors are set to experience significant change. Even semiconductor industry which is well-known as highly automated manufacturing also continues to pursue smarter solutions in order to overcome various new challenges in an increasingly complexed fab operation environment.

In this forum, presenters from all over the world will share their insights on the latest trends and emerging technologies in Smart Manufacturing areas such as IoT, Cloud Computing, Big Data, Machine Learning, and Artificial Intelligence focusing on implications in semiconductor industry. They will also illustrate the benefits of realizing “Smart Manufacturing” through the adoption of new methods, new systems, and new solutions.

Date: Feb 1(Thu), 2018

Time: 13:00-16:30

Room: #301, Conference Room (South), COEX

Language: English and Korean (Simultaneous interpretation will NOT be provided)

The 5G and Big Data, key issues in next connected world are increasing demand for putting more pressure on test costs due to higher coverage requirements. Test must become smarter to address the increased quality demands, while at the same time remaining economical. To address these challenges, test industry is struggling with increasing instrumentation integration, smarter strategies, self-test, adaptive test, system-level test, as well as more sophisticated test hardware. In this Test Forum, you can get the clues to overcome these challenges from industry expertise.

Date: Jan 31(Wed), 2018

Time: 13:00-17:10

Room: #318, Conference Room (South), COEX

Language: English and Korean (Simultaneous interpretation will NOT be provided)​​