1As a legitimate owner of a SEGGER Flasher, you can always download
the latest software free of charge. Typically, Segger support older models with new software at least 3 years after end of life.

Available software

In order to setup Flasher PRO for stand-alone operation, you need the J-Flash software from the J-Link software and documentation package.

Supported CPU cores / devices

Flasher PRO supports a wide range of cores/devices.

JTAG interface connection (20 pin)

There is a standard 20 pin connector defined by ARM. Flasher PRO has a built-in 20-pin JTAG connector, which is compatible with this standard.

JTAG interface connector signals:

Pin

Signal

Type

Description

1

VTref

Input

This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators and to control the output logic levels to the target. It is normally fed from Vdd of the target board and must not have a series resistor.

2

Vsupply

NC

This pin is not connected in Flasher PRO. It is reserved for compatibility with other equipment. Connect to Vdd or leave open in target system.

3

nTRST

Output

JTAG Reset. Output from Flasher PRO to the Reset signal of the target JTAG port. Typically connected to nTRST of the target CPU. This pin is normally pulled HIGH on the target to avoid unintentional resets when there is no connection.

5

TDI

Output

JTAG data input of target CPU.
It is recommended that this pin is pulled to a defined state on the target board.
Typically connected to TDI on target CPU.

7

TMS

Output

JTAG mode set input of target CPU.
This pin should be pulled up on the target.
Typically connected to TMS on target CPU.

9

TCK

Output

JTAG clock signal to target CPU.
It is recommended that this pin is pulled to a defined state on the target board.
Typically connected to TCK on target CPU.

11

RTCK

Input

Return test clock signal from the target.
Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, you can use a returned, and retimed, TCK to dynamically control the TCK rate. Flasher PRO supports adaptive clocking, which waits for TCK changes to be echoed correctly before making further changes. Connect to RTCK if available, otherwise to GND.

Target CPU reset signal. Typically connected to the RESET pin of the target CPU, which is typically called "nRST", "nRESET" or "RESET".

17

DBGRQ

NC

This pin is not connected in Flasher PRO.
It is reserved for compatibility with other equipment to be used as a debug request signal to the target system.
Typically connected to DBGRQ if available, otherwise left open.

19

5V-Target supply

Output

This pin can be used to supply power to the target hardware.

Notes:

All pins marked NC are not connected inside Flasher PRO. Any signal can be applied here; Flasher PRO will simply ignore such a signal.

Pins 4, 6, 8, 10, 12, 14, 16, 18, 20 are GND pins connected to GND in Flasher PRO. They should also be connected to GND in the target system.

Pin 2 is not connected inside Flasher PRO. A lot of targets have pin 1 and pin 2 connected. Some targets use pin 2 instead of pin 1 to supply VCC. These targets will not work with Flasher PRO, unless Pin 1 and Pin 2 are connected on the target's JTAG connector.

Pin 3 (TRST) should be connected to target CPUs TRST pin (sometimes called NTRST). Flasher PRO will also work if this pin is not connected, but you may experience some limitations when debugging. TRST should be separate from the CPU Reset (pin 15)

Pin 11 (RTCK) should be connected to RTCK if available, otherwise to GND.

Pin 19 (5V-Target supply) of the connector can be used to supply power to the target hardware. Supply volatage is 5V, max. current is 300mA. The output current is monitored and protected agains overload and short-circuit.

Power can be controlled via the J-Link commander. The following commands are available to control power:

Target interfaces

Since Flasher PRO is compatible to J-Link it also supports the same target interfaces. Currently the following target interfaces are supported:

JTAG

SWD

Please note, that Flasher PRO currently does not support SWO.

Performance of MCUs with internal flash memory

following table lists program and erase performance values for different controllers.

Microcontroller

Size [KByte]

Erase time [sec]

Program time [sec]

Verify time [sec]

Total time [sec]

Analog Devices

62

2.943

2.286

0.563

5.792

Atmel AT91SAM7S64

64

---

3.488

0.438

3.926

Atmel AT91SAM7S256

256

---

7.709

1.053

8.762

NXP LPC1768

512

3.740

8.559

5.092

17.391

NXP LPC2106

120

0.448

1.204

0.634

2.286

NXP LPC2129

248

0.449

2.916

1.347

4.712

NXP LPC2138

500

0.448

5.488

2.649

8.585

NXP LPC2148

500

0.448

5.632

2.721

8.801

NXP LPC2294

2048

0.808

15.976

9.669

26.453

NXP LPC2478

504

0.448

5.419

2.559

8.426

ST STM32F103ZE

512

0.028

18.763

3.939

22.730

ST STR711

272

0.429

5.476

4.742

10.647

ST STR912

544

1.167

12.907

5.236

19.310

TI TMS470R1B1M

1024

2.289

8.147

5.362

15.798

JTAG Speed

There are basically three types of speed settings:

Fixed JTAG speed

Automatic JTAG speed

Adaptive clocking

Fixed JTAG speed
The target is clocked at a fixed clock speed. The maximum JTAG speed the target can handle depends on the target itself. In general ARM cores without JTAG synchronization logic (such as ARM7-TDMI) can handle JTAG speeds up to the CPU speed, ARM cores with JTAG synchronization logic (such as ARM7-TDMI-S, ARM946E-S, ARM966EJ-S) can handle JTAG speeds up to 1/6 of the CPU speed. JTAG speeds of more than 10 MHz are not recommended.

NOTE:
On ARM cores without synchronization logic, this may not work reliably, since the CPU core may be clocked slower than the maximum JTAG speed.

Adaptive clocking
If the target provides the RTCK signal, select the adaptive clocking function to synchronize the clock to the processor clock outside the core. This ensures there are no synchronization problems over the JTAG interface.

NOTE:
If you use the adaptive clocking feature, transmission delays, gate delays, and synchronization requirements result in a lower maximum clock frequency than with non-adaptive clocking. Do not use adaptive clocking unless it is required by the hardware design.