Micron's Automata Exploits Parallelism to Solve Big Data Problems

DENVER -- Micron unveiled what it claims is a fundamentally different new processor architecture at Supercomputing 2013 that speeds up the search and analysis of complex and unstructured data streams. The sneak peak of its Automata Processor (AP) architecture was accompanied by the establishment of a Center for Automata Computing at the University of Virginia.

In an interview from the conference floor via telephone, Micron’s director of Automata Processor technology development Paul Dlugosch told EE Times that Automata is different than conventional CPUs in that its computing fabric is made up of tens of thousands to millions of processing elements that are interconnected. Its design is based on an adaptation of memory array architecture, exploiting the inherent bit-parallelism of traditional SDRAM.

“Many of the most complex, computational problems that face our industry today require a substantial amount of parallelism in order to increase the performance of the computing system,” said Dlugosch.

Conventional SDRAM is organized into a two-dimensional array of rows and columns and accesses a memory cell for any read or write operation. The memory, said Dlugosch, is not used to store data; it is used to stream back analysis of data. The AP architecture uses a DDR3-like memory interface and will be made available as single components or as DIMM modules.

Micron will also make available graphic design and simulation tools and a software development kit (SDK) to help developers design, compile, test, and deploy their own applications. A PCIe board populated with AP DIMMs will be available to early access application developers so they can begin plug-in development of AP applications. Samples of the AP and the SDK will available in 2014.

Automata has been in development for seven years, spurred by customer requests for even faster speeds. Dlugosch said Micron decided it was time to take a different approach to solve problems consistently voiced by CPU vendors and OEMs: Memory is the bottleneck. This problem has been exacerbated since the early days of big data in 2007, he said.

The architecture is aimed specifically at advanced computing capabilities, particularly analytics, where high-performance computing meets big data to solve problems in the areas of bioinformatics and network security analysis. The applications require deep analysis of data streams that contain spatial and temporal information and are often challenged by memory constraints.

Micron has partnered with a number of research institutions to foster adoption of the technology, including the Georgia Institute of Technology and the University of Missouri, while the University of Virginia has established the Center for Automata Computing with the help of seed funding from Micron.

Stu Wolf, professor of materials science and physics at the university, also attending the conference and instrumental in setting up the center, said problems are already being solved using the technology. One early project is designed to help researchers in biomedical engineering analyze huge volumes of DNA data and cellular imagery. Other potential applications include interpretation of social science datasets, data analysis for personal and national security, and design verification in engineering.

“This particular architecture and the way it has been configured allows a problem size to be much larger in any conventional computer,” said Wolf, adding that researchers who have started using it have found Micron’s SDK easy to work with.

Chirag Dekate, IDC’s research manager for HPC/Data Analysis, said Micron’s AP architecture was one of the highlights for him at Supercomputing 2013. “It is an extremely innovative architecture. It is the first processor of its kind.”

Because the AP architecture is data-flow based, it is well suited for certain problems, such as the emerging area of graph analytics, said Dekate, and having an SDK to program the processor is a compelling feature.

He said it’s important to note that the AP architecture is a first-generation technology and it is not suitable for all computing problems.

Micron’s choice beyond releasing an incremental update is a high-risk proposition, Dekate said. “They’re willing to innovate in what is quite a complex and dynamic ecosystem.”

If Micron marketing does its job, in 3 or 4 years there will be an AP chip in every cell phone and tablet offloading facial and speech recognition. There will be multiple AP chips in every new automobile for collision avoidance. Finally, every robot, drone, and autonomous device will have a handfull. These things will cost about $2 each if the die sizes are to be believed.

The AP is not a computer even though Micron claims it is a processor. It is a computer peripheral, more like a GPU for patterns. There will never be thousands of programmers coding for it. Rather there will be a set of state libraries to perform common API functions.

They do seem to have adopted the processor on DIMM technique we proposed about 6 years ago for our CPU in DRAM. http://www.venraytechnology.com/Implementations.htm

Don't know much about Automata Processor (AP)...please forgive me for a novice question.
"Its design is based on an adaptation of memory array architecture"...sounds more like an architecture similar to that of a CPLD...how does a AP architecture compare to that of a CPLD or FPGA?

I've lost count of how many novel and ground breaking parallel processors I've written about in 20 years at EE Times that have died quiet deaths because no one could write code for them. Is this any different?

According to the article, the AP architecture is data-flow based. In the past, dataflow architecture was also proposed for network procesing applications (e.g. xelerated dataflow network processor) but the main challenge is the programming complexity and the programming restrictions of these architectures.

Also it looks similar to the transputer processors architecture that were targetting parallel computing.

However, this automata processor seems to have included both an efficient programming framework/SDK and an efficient silicon implementation.

Processing big data sounds like an ideal application for parallel processing: huge quantities of data each of which nbeed to be processed through the same algorithms. I used a massively parallel processor (32,000 processors as I recall) in 1979 for image processing and was amazed at the work that could be done with just a 1 MHz clocked system. The pixels in images are just a special case of big data.

At most it is a new way of accessing the memories, in digital systems dealing with data is nothing but dealing with memories, Big Data Problems still demands a universal way to handle any problem associated with it, but still this solutions if claiming good results in certain directions, let's see how much it actually becomes effective.