The Contract No B-0210-IAP1-GC covering the Research & Technology Project entitled "System-on-Chip" (SoC) was signed on 13 July 2011 by THALES Communications & Security S.A. (FR) in its capacity of Leading Contractor of the SoC Consortium and the EDA (Contracting Authority).

Digital Processing and their enabling components and technologies are keys for more digitalisation in the battlefield and within the projected forces, for new algorithms towards higher performing sensing and more processing capacity and for more security in net centric missions and operations.The workshop in March 2005 under Weao Cepa2 organisation has addressed the related stakes of future programs, the needs and the military specificities of their enabling technologies (processing performance, swap, hardware programmability, middleware, security/crypto, safety, ...) which can be shared at European level, the design methodology and tools for applications portability and their long term availability and also the technology access within Europe. This proposal takes into account the outputs and recommendations from the workshop. It brings together the several contributing actors such to build complementary and add-ons technologies at European level for Defence applications.ASIC or SoC are still mandatory to provide System Level integration capabilities for future Defence programs at same level as consumer products, but which the related military functions and when no structured European based solution can be identified at that time for low volume at low cost.The FPGAs (Field Programmable Gate Arrays ) that provide now over million gates, targeting system integration and performance achievements allowing their usage in a wide range of military applications do not cover the whole domain. The FPGAs are evolving now in high performance heterogeneous System-On-Programmable-Chip (SoPC) targeting real-time embedded applications, however high gate counts FPGA are power greedy, raising for some applications thermal and integration issues.US dependency is nearly total for the general purpose processors (GPP), and digital signal processors (DSP) as well as for ADC/DAC converters used in digital front ends in radar and radio systems. US dependency is complete for FPGA solutions. It appears also that the more advanced US solutions may not be accessible to the European Defence manufacturers.ASICs generally provide completely hardwired integration. However, the Defence applications are demanding for more flexibility for the embedded SW but also for the Hardware to update/improve more easily the global solution. System-on-Chip solutions (SoC) have been adopted in commercial applications, a breakthrough in integration is expected in Defence applications while adopting and levering the SoC technology in Defence products.The 2 major goals of EDA SoC project is to give access to the defence equipment manufacturers for designing complex System on chip in an advanced technology and to bring system level integration methodology compliant with security and safety requirements.The related issues in the R&D EDA SoC project are:

To investigate the new potentials and possibilities offered by an advanced technology and by new embedded configurable structures in structured SoC technology.

To investigate a tool box and methodology compatible with security requirements, applicable to FPGA and programmable SoC. To validate it on existing FPGA device at European level.

To investigate new architecture to facilitate evolution and upgrade in a DO254 environment

To consolidate the technology access for defence equipment manufacturer

Therefore, the objectives of this proposal are:

Identify the requirements of the applications that require advanced technologies and high level of integration to cope with the high performance and/or power consumption issues, size ... This set of application provides the inputs to identify the targeted technology and the specific requirements.

Develop the identified building blocks in the advanced technology to integrate them into a test vehicle, prototype it and validate it.

Define and demonstrate the secure component and perform an evaluation by recognised centre.

Define and demonstrate a framework architecture for DO254 application

Consolidate the technology access scheme for European actors in Defence domain.