At 146 square millimeters the memory die is more than 25 percent smaller than the company's same-capacity MLC NAND memory and it is intended for use in removable storage, including flash memory cards and USB drives. On the assumption of reasonable process yield a small die area results in more memories per wafer, lower costs for the manufacturer and lower prices for the buyer.

Micron expects removable storage to consume 35 percent of NAND memory in 2013. The 128-Gbit NAND is sampling with selected customers and will be in volume production in the second quarter of 2013, Micron said.

No details of the read or write performance, or the cycling endurance of the memory were provided by Micron in a press release but a paper is due to be presented on the 128-Gbit TLC NAND device at the upcoming International Solid-State Circuits Conference (ISSCC) on Feb. 19 at 3:15pm, in San Francisco, California.

16-Gbytes of storage required four die at 34-nm and two die at 25-nm. Micron claims an area saving of 25 percent at 20-nm over the previous generation.

I agree it's odd but the paper presents that way. Maybe the TLC reliability is as expected. Still, didn't even get any ECC assurance. I assume there will be or this is for really error-tolerant products. The FG interference curve was also presented ominously enough.

iniewski, apparently you and I have very different data collections. I recently had to switch from a 1.5 Terabyte hard drive for backup to a 3.0 Terabyte hard drive because my data wouldn't fit on the 1.5 Terabyte drive.