We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Firefox,
Internet Explorer 11,
Safari. Thank you!

AR# 21485

7.1i EDK Service Pack 2 - PLB_IPIF_v2_01_a slave attachment does not respond to IP master read and master enable PLB IPIF does not work when C_Burst_Enable is False

Description

General Description:

When generic C_SUPPORT_BURST is False, and PLB IPIF is used in pure master configuration (not master-slave), certain signals are not initialized (not in Bus_Reset, as in default configuration), but are used within "if statements" in read mode. This causes master accesses to not generate M_Request on the bus.

"Error Message:

---------------------------------------

Signals have value 'U', even after reset is over.

Look at :

lcl_rdDAck_i

lcl_rdComp_i

lcl_wrcomp_i

lcl_wrdack_i

lcl_wr_en

In addition,

The PLB IPIF that is incorporated by the Wizard for the User Master support must always have bursting enabled. This is a known issue for the User Master enabled.

Solution

Make sure that your design has overridden the defaults (False) of these two PLB IPIF parameters by setting them to True in the PLB IPIF instance:

C_DEV_BURST_ENABLE : BOOLEAN := true;

Burst Enable for IPIF Interface (and cacheline support)

C_DEV_FAST_DATA_XFER : Boolean := true;

If Burst is enabled, then this parameter allows the selection of a fast data transfer mode of one clock per data beat (FPGA-resource intensive) or a slower multi-clock per data beat transfer mode (saves FPGA resources).