Kanai Ghosh: A singular effort that changes the conversation

There’s a guy working away in Bangalore today who would like to change your ideas about what you pay for EDA tools. His name is Kanai Ghosh and his tool suite is called edautils, as in EDA Utilities. I spoke with Kanai on Skype recently about his efforts.

He told me that after a number of years working in EDA and CAD tool development, he decided to design his own suite of tools. Now several years into that process, working nights and weekends in and around his day job, Kanai’s tools are available for free download on his website.

Per Kanai, edautils pays particular attention to problems associated with integrating IP into larger SoC projects – a critical problem, he says, because today’s design projects can include more than 250 pieces of IP. In addition, today’s SoC has “multiple power and voltage domains” which the designer has to deal with by changing the design on the fly as the design constraints evolve, the designer constantly making “tradeoffs between power/performance/area and the project budget.”

To meet these challenges, Kanai says he designed the Baya SoC platform integration tool, a part of edautil, to “take advantage of the IEEE 1685-2009 IP-XACT initiative. Baya is available in both GUI and Tcl command modes, includes more than 100 Tcl commands, a low-level API for users to manipulate the design database, and has a design-maturing reporting feature based on unconnected pins/ports in the design in progress.”

Meanwhile, Kanai says the other portion of the edautil suite, the Bridig tool, provides a set of “miscellaneous utilities around VHDL and Verilog that automate many small steps in the design process which previously had to be handled manually.

During our conversation and a follow-on email, Kanai emphasized that both the Baya and Brigid tools have been implemented on Java: “It’s one of the most quickly evolving programming languages [in use today], which is widely used to develop software. Using Java, new applications can be developed quickly and easily without thinking about the memory/pointer issues that come up with C/C++.”

Addressing concerns about code written in Java, Kanai said, “Nowadays, one can buy a fast computer with many GB of memory at a very low price. So even if Java is slow and requires more memory than working in C/C++, the effectiveness of today’s compute machines makes up for that speed. And there are lots of resources available on the web based on Java, which makes that choice even more appropriate.”

Clearly, Kanai Ghosh has been working hard. If you’re worried, however, that he’s been spending his nights and weekends developing all of this stuff, but having little or no traction out in the real world, think again. Kanai told me many thousands of people around the world are aware of his work:

“The total download of edautils in 2012 was more than 10,000. Even this year, I can tell you that there are an amazing number of people who have downloaded edautils. And those downloads are coming from many well-known companies, spanning across semiconductors and EDA, and even universities – over 60,000 unique visitors to my website since I launched edautils.com in January 2012!”

If the amount of traffic coming to his website is any indication, and the wide range of companies accessing the tools, Kanai has clearly succeeded in making an impact. His is the type of effort that changes the conversation about how people develop tools for design, and what they pay for them.

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You can see many testimonials listed on the front page of www.edautils.com, including users from Intel, TI, and Renesas.

We have been using verilog testbench generator (http://www.edautils.com/VlogTBGen.html), Java version, in Unix. That is really usefull in coding process and easy to use. We got help from people of Edautils and it was fast and efficient. I would recommend their tools. 🙂

EDAUtils is one (if not the only one) of the most comprehensive tools for SoC design and integration and it is available for free.
I included EDAUtils in the latest OpenTech Package as featured application among all free open source designs and tools and I believe with a lot of efforts it will grow to be one of the major tools in this domain.

Kanai is outstanding and very responsive. The baya-shell is solid and very intuitive and easy for constructing modules using tcl. Very useful set of utilities for any design team that wants to spend time designing rather than writing scripts and utils from scratch. Highly recommended!

Kanai produced an excellent tool set, which is very useful for a complex system-on-chip integration flows.
We were skeptical in the beginning, but later got really impressed by a high quality and ease of use.

Bridgit IPXACT creator helps us to pack register, bus and module interfaces into a IEEE standard *.xml SPIRIT format to ensure high reusability in the future and protect our investments.

I high recommend using Kanai’s products for every system-on-chip manufacturer and invest Venture Capital to support further improvement and commercialization.

We are developing and using in our FPGA design practice open source tool, that provides HDL simulation directly in MATLAB and Simulink (http://code.google.com/p/vmodel/). Our tool is based on Verilator well-known open source simulator. And as Verilator out tool cannot simulate VHDL designs. But with vhdl2verilog translator we can solve this problems. Also I should mention EDAUtils support. They reply very fast and really try to help with your problem

Please add a feature to export the results of the design browser and dependency browser. I am looking to use the output of these tools in my design documentation. I would like some “pretty” output that I can use. It could be simply indented text lines that look like the tree structure generated by the tools. It would be even better if it was rich text, or if I could simply copy and paste from the existing display window into Word or other rich-text program.