Let us consider the instruction JMP Label (PC← Label) and
derive its execution control sequence. This unconditional
jump instruction will load the program counter with the address
of Label such that in the next fetch cycle, the instruction is
fetched from the address given by Label.

In relative addressing (short and near jumps),
what is stored in the instruction is not the absolute
address of label but an offset from the PC, i.e.,
Label - PC. Note that PC will be pointing at the instruction
following the JMP instruction. When the CPU executes the
JMP instruction, it will add the content of PC to the offset
stored in the instruction to get the actual address of Label,
i.e. (Label-PC)+PC= Label.

The execution control sequence for the JMP Label instruction
for the single-bus CPU is given in the following table:

Control Sequence

Active Signals

T4

PCout, Yin

T5

(offset-field-of-IR)out, ALU (C=A+B), Zin

T6

Zout, PCin, END

In T4, the content of PC is stored in the Y register.
In T5, the offset field of the IR, which contains Label-PC,
is put on the CPU bus and added with Y and the result is stored
in Z. At this point Z will contain the actual address
of Label. In T6, the content of the Z register, which is
the address of Label, is stored in PC and the execution control
sequence is terminated by the END signal.

The execution control sequence of the JMP Label instruction
for the single-bus CPU is demonstrated in the next figure:

Fig. m300126.1 Execution Control Sequence for JMP Instruction in a Single-Bus CPU