hi,
when the register width differs from the bus width and one register access results in a series of bus transactions，such as
using 32bit-width data bus can access 64-register dut by separated two times，this can be interrupted by grabed
sequence，such as interrrupt sequence, A example of transaction_order may be
A_upper( upper 32 bit of A register，suppose higher priority ) -----> Interrupt service sequence(may be access interrupt clear or mask register (two times ) -----> A_Lower( lower 32 bit of A register)
whether the transaction order is corrected or not ? this may cause some unright something?,thank you

Hi!
often,in uvm test, host controller write or read registers through addresses,so, I define some parameter in a package using `define in replace of register address.
then , import the package into my test lib package,
compile in order , test lib package is compiled lastly,
but when compling code ,report macro address can't find?
How to using package rightly in UVM?
Large projects may have many packages with complex interdependencies,How to using it rightly ?
thanks.
/wszhong

Hi！
uvm_component_name_check_visitor
This specialized visitor analyze the naming of the current component. The established rule set ensures that a component.get_full_name() is parsable, unique, printable to order to avoid any ambiguities when messages are being emitted.
ruleset a legal name is composed of
allowed charset “A-z:_0-9[](){}-: “
whitespace-as-is, no-balancing delimiter semantic, no escape sequences
path delimiter not allowed anywhere in the name
whether the name abc:_[] is legal or not ？how to use it?

sorry,payloadseqment is a mis-spelling error when written this question. in sequence_item.svh,
rand [7:0] payloadsegment[]; // payloadsegment that payload of some packets
https://verificationacademy.com/forums/uvm/why-payloadsegment0-not-legal-c-identifier-namebut-payloadseqment0
Dave_59 says as follows
"This warning is generated by Questa's built-in UVM-aware debug facilities. In order to use the debugging tools, the UVM created paths need the ability to be parsed by the command line. All vendor tools have this problem. You can ignore these warnings if you do not plan to use these debug facilities.
Note that the upcoming UVM 1.2 standard plans to require proper identifier names, not just any string. You will get an error if you do not fix them. See http://www.eda.org/svdb/view.php?id=4712
"
indeed, if not add "+incdir+$(questa_uvm_pkg) $(questa_uvm_pkg)/questa_uvm_pkg.sv", lot of warnings that sees if very Annoying will not be reported。

in order to watch UVM_details windows in questasim10.2c/10.2b,vlog option + questa_uvm_pkg options.
Makefile as follows:
questa_uvm_pkg=/app/mentor/questasim_10.2c/questasim/verilog_src/
vlog +incdir+$(uvm_home)/src $(uvm_home)/src/uvm.sv \ +incdir+$(questa_uvm_pkg) $(questa_uvm_pkg)/questa_uvm_pkg.sv ...............
under of simulation,report warning as follows:
questasim/verilog_src/questa_uvm_pkg_1.2/src/questa_recorder.svh(364) @4080840000: reporter [iLLEGALNAME] 'payloadsegment[0]' is not a legal c identifier name.change to questasim/verilog_src/questa_uvm_pkg_1.2/src/questa_recorder.svh(366) @4080840000: reporter [iLLEGALNAME] 'payloadsegment_0_' Attibutes mus be named as a legal cidentifier.
and in monitor.svh, foreach(payloadsegment) payloadsegment=data;
and in UVM_details window, as sequence is added to waves
,we sees randomized sequence item ,payloadsegment_0_,payloadsegment_1_,payloadsegment_2_。
why payloadsegment is not legal c identifier?!
but if the same codes rerun in questasim10.1d,above warning not reported.