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AR# 20796

描述

To achieve the maximum frequency performance of the DCM in the high-frequency mode (HF), the clock input must be connected to the DCM using BUFG. Additionally, the design must be implemented in the ISE 7.1i Service Pack 1. For more information on Virtex-4 Errata, see (Xilinx Answer 20529), items #1 and #4.

For all SPI-4.2 Core users targeting Virtex-4, be advised that the following cores and configurations are affected:

(Dynamic Phase Alignment mode is not affected, and the Static Alignment Mode using Regional Clocking is not affected. However, the design still needs to be implemented using ISE 7.1i with Service Pack 1 or later, to maintain full DCM maximum frequency performance.)

Source Core

- Source core is not affected by this errata since all input to DCM is already routed through BUFG, or the DCM is not in the HIGH frequency mode.

- However, the design still needs to be implemented using ISE 7.1i with Service Pack 1 or later, to maintain full DCM maximum frequency performance.

解决方案

If SPI-4.2 Core is in Static Alignment Mode and uses Global Clocking Option:

2. If possible, use Static Alignment Mode with regional clocking scheme or Dynamic Alignment mode. If this is not possible, contact an SPI-4.2 expert or IP Marketing person at: dean.armintrout@xilinx.com.

Regardless of your Sink core setting (Static or Dynamic), SPI-4.2 Core still uses DCM in the HIGH frequency mode. Therefore, it is necessary to implement your design using ISE 7.1i with Service Pack 1 or later.