Intel's Penryn processors will push desktop PCs to run 40 per cent faster for gaming than the latest Intel Core 2 Extreme chip, a company executive said Monday, giving details on the new chip design planned to reach markets in the second half of 2007.

Likewise, Penryn-powered workstations will deliver a 45 per cent improvement for bandwidth-intensive tasks, versus today's quad-core Intel Xeon, said Sean Maloney, Intel's executive vice president and chief sales and marketing officer. Intel will achieve the feat by shrinking its chip features from 60 nanometers to 45nm and by using "high-k metal gate" transistors, which are arguably the biggest breakthrough in microchip technology in 40 years, he said.

Maloney spoke to reporters in a preview of comments the company plans to make at its Intel Developer Forum (IDF) in Beijing Tuesday. This is the first full IDF show Intel has held in China, and marks another step in the company's commitment to developing its products with Chinese expertise and employees, he said. Intel has already invested US$200 million in Chinese ventures through its Intel Capital arm, and announced in March that it plans to build a $2.5 billion chip fabrication plant in Dalian, with plans to hire many more workers than the current 6,000 Chinese it now employs.

In other advances, Intel will deliver a new line of high-end multiprocessor server chips code-named "Caneland" in the third quarter of 2007. This Xeon 7300 series will include a quad-core and dual-core chips running in 80-watt and 50-watt versions for blade servers. Those chips could help Intel compete with a major new chip release from competitor Advanced Micro Devices Inc. (AMD), which plans to unveil its "Barcelona" Opteron server chip in the middle of 2007.

Intel also said it plans to shrink enterprise-level platforms down to the size of a single chip. Under this "Tolopai" project, designers will create a system-on-chip (SOC) platform by integrating several components into a single processor, reducing chip size by up to 45 per cent and power consumption by 20 per cent compared to a standard four-chip design, Maloney said.

The approach is similar to an SOC plan Intel announced on April 3 for low-wattage embedded tasks like print imaging and in-vehicle automotive platforms. That version of the strategy reduces three chips to one by combining the main processor with its memory control and I/O control hubs.

Intel will use this same design in its CE 2110 Media Processor, a SOC architecture that could allow consumer electronics vendors to make simpler designs for digital home products. By 2008, Intel will begin selling the chip as a common foundation that spans products from PCs to consumer electronics, including laptops, televisions, set-top boxes and other networked media players.

Finally, Intel shared its plans for a programmable architecture code-named "Larrabee" that could allow a system to run at trillions of floating point operations per second (teraflops) of performance, a huge boon to applications in scientific computing, mining, visualization, financial analytics and health care. Pressed for further details on the conference call, Maloney declined to describe it more precisely.