The SPARC-V9, CWP register is decremented during a RESTORE instruction, and incremented during
a SAVE instruction. This is the opposite of PSR.CWP's behavior in SPARC-V8. This
change has no effect on nonprivileged instructions.

E.1.2 Alternate Space Access

Load- and store-alternate instructions to one-half of the alternate spaces can now be
included in user code. In SPARC-V9, loads and stores to ASIs 0016 .. 7f16
are privileged; those to ASIs 8016 .. FF16 are nonprivileged. In SPARC-V8, access to
alternate address spaces is privileged.

E.1.3 Byte Order

SPARC-V9 supports both little- and big-endian byte orders for data accesses only; instruction
accesses are always performed using big-endian byte order. In SPARC-V8, all data and
instruction accesses are performed in big-endian byte order.