Lack of coordination between asynchronous resets and synchronous logic clocks leads to intermittent failures on power up. In this series of articles, we discuss the requirements and challenges of asynchronous reset and explore advanced solutions for ASIC vs FPGA designs.

Asynchronous resets are traditionally employed in VLSI designs for bringing synchronous circuitry to a known state after power up. Asynchronous reset release operation must be coordinated with the synchronous logic clock signal to eliminate synchronization failures due to possible contention between the reset and the clock. A lack of such coordination leads to intermittent failures on power up. The problem exacerbates when large, multiple-clock domain designs are considered. In addition to the synchronization issues, the distribution of an asynchronous reset to millions of flip-flops is challenging, calling for techniques similar to CTS (Clock Tree Synthesis) and requiring similar area and routing resources.

The requirements and challenges of asynchronous reset are reviewed, focusing on synchronization and distribution issues. The drawbacks of classic solutions for reset synchronization (reset tree source synchronization) and distribution (reset tree synthesis) are discussed. Advanced solutions for faster and simpler timing convergence and more reliable reset synchronization and distribution are presented. Different approaches for ASIC versus FPGA designs are detailed.

Part 1 (this article) describes the issues surrounding asynchronous resets and outlines approaches for resolving those issues. Part 2 discusses additional solutions for correct asynchronous reset in ASIC and FPGA. Some useful special cases are discussed in Part 3.

1. Asynchronous reset challenges

A reset function is normally included in digital VLSI designs in order to bring the logic to a known state. Reset is mostly required for the control logic and may be eliminated from the data path logic, reducing logic area. Reset may be either synchronous or asynchronous relative to the clock signal.

Synchronous reset requires an active clock, incurs certain clock-cycle related latency and may impact the timing of the data paths. On the other hand, synchronous resets are deterministic and do not incur metastability.

Asynchronous reset does not require an active clock to bring flip-flops to a known state, has a lower latency than a synchronous reset and can exploit special flip-flop input pins that do not affect data path timing. However, asynchronous resets have a number of drawbacks:

They may cause metastability in flip-flops, leading to a non-deterministic behavior.

Asynchronous resets must be made directly accessible to enable DFT.

The asynchronous resets may incur reliability problems in rad-hard applications, being susceptible to Single Event Transient (SET) phenomena ‎[1].

Leaving aside the discussion on which type of reset is better ‎[2], in this article we focus on issues and solutions related to asynchronous resets. Some of the techniques presented in this paper are applicable to both asynchronous and synchronous resets.

In many cases asynchronous resets can be replaced by synchronous ones, but there are some situations in which the asynchronous reset functionality is compulsory. One example is a synchronous design that gets no active clock at power up (the clock is either unstable or gated for power reduction), but requires a certain known state for its external interfaces. Another example is low power design that is required to minimize power during the power up process, having no active clocks.

The employment of asynchronous reset is not straightforward. Although the relative timing between clock and reset can be ignored during reset assertion, the reset release must be synchronized to the clock. Avoiding the reset release edge synchronization may lead to metastability. Referring to Figure 1, an active high asynchronous reset is shown. The reset assertion (a) affects flip-flop output Q within a deterministically bounded time (propagation delay, TR-pd) and regardless of clock signal CLK. During reset release (b), setup and hold timing conditions must be satisfied for the RST port relative to the clock port CLK. A violation of the setup and hold conditions for the RST port (aka reset recovery and removal timing) may cause the flip-flop to become metastable, causing design failure due to switching to an unknown state. Note that this situation is similar to the violation of setup and hold conditions for the flip-flop data port, D.