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Since 1987 - Covering the Fastest Computers in the World and the People Who Run ThemFri, 09 Dec 2016 13:18:37 +0000en-UShourly1https://wordpress.org/?v=4.760365857K Computer Runs First Accurate Model of Abrupt Torrential Rainhttps://www.hpcwire.com/2016/08/09/k-computer-runs-first-accurate-model-abrupt-torrential-rain/?utm_source=rss&utm_medium=rss&utm_campaign=k-computer-runs-first-accurate-model-abrupt-torrential-rain
https://www.hpcwire.com/2016/08/09/k-computer-runs-first-accurate-model-abrupt-torrential-rain/#respondTue, 09 Aug 2016 20:51:32 +0000https://www.hpcwire.com/?p=29230Supercomputers have long been used in weather forecasting but not for abrupt, highly localized events. Now for the first time, a group of researchers using the K computer used the powerful K computer and advanced radar observational data to accurately predict the occurrence of torrential rains in localized areas. These latter events can arise in […]

]]>Supercomputers have long been used in weather forecasting but not for abrupt, highly localized events. Now for the first time, a group of researchers using the K computer used the powerful K computer and advanced radar observational data to accurately predict the occurrence of torrential rains in localized areas. These latter events can arise in just a few minutes when cumulonimbus clouds suddenly develop.

The key to the success is rapid “big data assimilation” using computational power to synchronize data between large-scale computer simulations and observational data. Researchers also used a much finer grid than the typical 1-2 km spacing of most models. The work done by an international team will be published later this month in the August issue of the Bulletin of the American Meteorological Society.

In this instance, researchers used the nonhydrostatic mesoscale model used by the Japan Meteorological Agency, but with 100-meter grid. Led by Takemasa Miyoshi of the RIKEN Advanced Center for Computational Science (AICS), researchers first carried out 100 parallel simulations of a convective weather system using the much finer grid spacing. They produced a high-resolution three-dimensional distribution map of rain every 30 seconds, 120 times more rapidly than the typical hourly updated systems operated at the world’s weather prediction centers today.

To test the accuracy of the system, the researchers attempted to model a real case—a sudden storm that took place on July 13, 2013 in Kyoto, close enough to Osaka that it was caught by the radars at Osaka University. Pure simulations without rapid incorporation of finer-grained observational data were unable to replicate the rain; incorporation of observational data allowed the computer to accurately represent the actual storm.

“Supercomputers are becoming more and more powerful, and are allowing us to incorporate ever more advanced data into simulations. Our study shows that in the future, it will be possible to use weather forecasting to predict severe local weather phenomena such as torrential rains,” said Miyoshi.

]]>Researchers at the Japan Agency for Marine-Earth Science and Technology (JAMSTEC) reported simulating global seismic wave propagation with a best-ever accuracy of 1.2 sec seismic period for a three-dimensional Earth model on Japan’s K supercomputer. Optimizing the code allowed them achieve sustained performance of 1.24 petaflops on the K computer, which is 11.84% of its peak performance.

Their work is reported in the International Journal of High Performance Computing Applications (A 1.8 trillion degrees-of-freedom, 1.24 petaflops global seismic wave simulation on the K computer, Feb. 28). The study will help understand earthquake occurrence mechanisms and the Earth’s internal structures more precisely and is expected to make significant contributions to disaster prevention and mitigation.

As noted in the abstract from their paper, the work was computationally challenging:

“…Our seismic simulations use a total of 665.2 billion grid points and resolve 1.8 trillion degrees of freedom. To realize these large-scale computations, we optimize a widely used community software code to efficiently address all hardware parallelization, especially thread-level parallelization to solve the bottleneck of memory usage for coarse-grained parallelization. The new code exhibits excellent strong scaling for the time stepping loop, that is, parallel efficiency on 82,134 nodes relative to 36,504 nodes is 99.54%…”

The research group was led by Dr. Seiji Tsuboi at Center for Earth Information Science and Technology (CEIST). In 2003, a similar study group achieved the computed theoretical seismograms with what was then a record-breaking 5 second frequency for realistic three -dimensional Earth with the Earth Simulator.

]]>https://www.hpcwire.com/2016/03/17/k-computer-achieves-accurate-global-seismic-wave-propagation-simulation/feed/125710Details Emerging on Japan’s Future Exascale Systemhttps://www.hpcwire.com/2014/03/18/details-emerge-japans-future-exascale-system/?utm_source=rss&utm_medium=rss&utm_campaign=details-emerge-japans-future-exascale-system
https://www.hpcwire.com/2014/03/18/details-emerge-japans-future-exascale-system/#respondWed, 19 Mar 2014 04:00:13 +0000http://www.hpcwire.com/?p=8451The Big Data and Extreme Computing meeting in Fukuoka, Japan concluded recently, pushing a great deal of information about international progress toward exascale initiatives into the global community. As the host country, Japan had ample opportunity to gather many of the researchers building out the next incarnation of the K Computer, which is expected to […]

]]>The Big Data and Extreme Computing meeting in Fukuoka, Japan concluded recently, pushing a great deal of information about international progress toward exascale initiatives into the global community.

As the host country, Japan had ample opportunity to gather many of the researchers building out the next incarnation of the K Computer, which is expected to be the country’s first exascale system—a $1.38 billion undertaking that’s already underway with expected installation in 2019 and full-steam production in 2020.

According to the roadmap put forth by Yoshio Kawaguchi from Japan’s Office for Promotion of Computing Science/MEXT, basic development for the future system is swiftly moving on software, accelerator, processor and scientific project planning fronts. Fujitsu, Hitachi and NEC are key vendors providing the system and support, along with technical staff at the University of Tokyo, the University of Tsukuba, the Tokyo Institute of Technology, Tohoku University and of course, at RIKEN, site of the K Computer and future hub of its successor.

Called “postK” in reference to its ability to step up the power of the original former top system, K, the timeline for the exascale system is laid out as a projection–with additional research notes (summarized below) to highlight various tracks of the early development and system/stack design.

Japan has its sights set on a number of potential problems that might be solved on postK, including the development of safer cars, the evolution of drugs with mitigated or reduced side effects, better prediction and responses to natural disasters, and specific projects, like the development of better batteries, the creation of electronic devices using novel materials, and the enhanced ability to kick galaxy simulation up several (thousand) notches.

Of course, to do all of this at a reasonable cost is going to take some serious innovation. A few of the key researchers behind the components to building postK shared details, including Dr. Mitsushisa Sato from the Center for Computational Sciences at the University of Tsukba and team leader for the Programming Environment Research Team behind the K Computer at RIKEN.

His work is centered around optimal accelerators for massive heterogeneous systems, which has led to the creation of what the team calls an “extreme SIMD architecture” designed for compute oriented applications. This involves tightly coupled accelerators and a few unique memory refinements, including the addition of high bandwidth memory (HBM in the chart below).

This architecture would be designed to tackle molecular dynamics and N-body-type simulations as well as stencil apps and according to Sato, will aim for high performance in the area of around 10 teraflops per chip using a 10nm silicon technology that will arrive somewhere in the 2018-2020 timeframe. While that’s not staggering when you really think about it, the real story seems to be (at this point anyway) that most of the crunch is being handled by the on-board accelerator with the added weight of the memory on the same package and associated networking.

Sato and team are exploring possible programming models for this approach via a C extension for the in-the-weeds aspects, an OpenACC-based model for stencil applications to help ease porting existing codes, a DSL and application framework for building with as well as the option of OpenCL. There is no mention of CUDA here, which should likely tell you something about the nature of the accelerator. Again, as with all aspects of this article, we’ll be following up as soon as we can secure more information.

On the processor front, this is again seen as a natural evolution of the K system. According to Yutaka Ishikawa from the University of Tokyo, the team will carry over lessons learned with the general processor environment to target far greater efficiency and to meet a software stack that’s designed for both the proposed and commodity-based systems.The ridiculously bright yellow chart on the left shows the various processor approaches they’ve been testing during their current cycles.

In a presentation from the application and system feasibility study teams, they noted the many parallels in terms of challenges and potential problems the system could solve between K and the exascale system of 2020. The K Computer, which was put into production in 2011, currently has over 1,431 users and is running around 136 projects. Each of the sites in Japan’s national infrastructure is dedicated to a specific strategic application area (although not exclusively running projects in the domain). At RIKEN the K system is devoted in particular to life sciences and drug design problems. Other sites are focused on materials science, climate and geosciences, manufacturing and astrophysics. The system has supported two notable Gordon Bell prizes since its inception, in addition to topping the Top 500 list in 2011.

Keep in mind that the United States is a partner on the software side of the project. As Kawaguchi’s slide highlights, the partnership will continue into the next phases of system development. The team notes that “international collaboration for system software has been considered”

We’ll be bringing much more insight into this story as soon as we’re able to secure it but we did want to point to the details as soon as possible. You can view more about these and other presentations around exascale (not to mention a lot of talk about big data) at the main site, where the presentations have just gone live: http://www.exascale.org/bdec/agenda/fukuoka-japan

Our thanks to Dr. Jack Dongarra to the early insight he was able to provide. Follow-up coming soon, stay tuned…

]]>https://www.hpcwire.com/2014/03/18/details-emerge-japans-future-exascale-system/feed/08451Japan’s Manufacturers Cozy Up to Supercomputinghttps://www.hpcwire.com/2014/01/27/japans-manufacturers-cozy-supercomputing/?utm_source=rss&utm_medium=rss&utm_campaign=japans-manufacturers-cozy-supercomputing
https://www.hpcwire.com/2014/01/27/japans-manufacturers-cozy-supercomputing/#respondMon, 27 Jan 2014 21:57:31 +0000http://www.hpcwire.com/?p=3385Beyond a pure passion for technology and the thrill of turning ideas into reality, there is a hugely practical basis for investment in advanced computing. Supercomputers and other computational technologies bolster economic competitiveness, a notion that nearly all academic, industry and government leaders have embraced. As supercomputers become more powerful, manufacturers can run bigger and […]

]]>Beyond a pure passion for technology and the thrill of turning ideas into reality, there is a hugely practical basis for investment in advanced computing. Supercomputers and other computational technologies bolster economic competitiveness, a notion that nearly all academic, industry and government leaders have embraced. As supercomputers become more powerful, manufacturers can run bigger and more complex models, saving time and money in the process.

In Japan, manufacturers are increasingly turning to the nation’s fastest supercomputers – such as the 10-petaflop K supercomputer, installed at Japan’s RIKEN research institute – to get a leg up on the competition. As an article in Nikkei Asian Review details, Japanese business and research organizations are exploring how to best leverage the potential of the K computer and similar powerful computing machines. There are several projects in place now, which are expected to yield results within a couple of years.

Software developed for K is being used by carmakers Toyota Motor and Suzuki Motor, and Bridgestone, the tire maker, to help them design their next-generation of products. The hardware-software combination is making it possible for the manufacturers to meet their prototyping needs without having to build full-scale physical designs. Not only is the digital approach less costly and time-consuming, it enables greater innovation as new ideas can be tried out with a few clicks of the keyboard. Testing a large number of design parameters in a physical format just wouldn’t be feasible from an economic or time standpoint.

Developed by a team of specialists from 13 companies with the cooperation of Hokkaido University, the software simulates the air resistance created by a car by interpreting the space around a car as a grid of 2.3 billion segments. The computer simulation reflects how the air movement is affected by different driving conditions, for example a passing vehicle of a strong crosswind.

Digital modeling enables engineers to determine the most aerodynamic shapes. Lower wind resistance enables vehicles to be more fuel-efficient and increases steerability. Previously, automakers had to construct large wind tunnels and run tests using full-scale models. The supercomputer helps minimize the need for expensive physical testing. It can even find flaws that would previously have gone undetected in a a physical mockup, according to K engineers.

In addition to the auto industry, Japan is also expanding its supercomputing efforts into the shipbuilding field. Instead of simulating air flow, design software developed by the Shipbuilding Research Center of Japan shows how a ship’s movement creates turbulence in water as small as 1mm. By enabling shipbuilders to forego testing of real-life floating models in enormous tanks, the design costs for such vessels can be reduced by up to 50 percent.

The Fujitsu-RIKEN K supercomputer is also being used to enable a faster pace of discovery in materials science and pharmaceutical research. While the main user base for the K system are universities and labs, the Research Organization for Information Science and Technology (RIST), which manages the allocation process, also maintains a number of industry relationships. RIST accepted 42 applications for projects using the K in fiscal 2014, up from 27 in 2012.

Going forward, Japan’s science ministry is working to develop an exascale supercomputer, 100 times faster than the K, by 2020.

]]>https://www.hpcwire.com/2014/01/27/japans-manufacturers-cozy-supercomputing/feed/03385Floating Funding to Exascale Islandhttps://www.hpcwire.com/2013/05/09/floating_funding_to_exascale_island/?utm_source=rss&utm_medium=rss&utm_campaign=floating_funding_to_exascale_island
https://www.hpcwire.com/2013/05/09/floating_funding_to_exascale_island/#respondThu, 09 May 2013 07:00:00 +0000http://www.hpcwire.com/?p=4058The Japanese government has revealed its plans to best its previous K Computer efforts with what they hope will be the first exascale system...

]]>The Japanese government has revealed its plans to best its previous K Computer efforts with what they hope will be the first exascale system.

Reports indicate that the country’s Education, Culture, Sports, Science and Technology Ministry (talk about a broad reach) is preparing a funding request to begin toiling at the first design phases of the eventual extreme-scale K replacement—one that is expected to pay dividends by next year if approved.

While Japan has made its formal entry into the exascale race with this announcement, it’s not aiming much higher than others with noteworthy funding toward the lofty goal. The Japanese government anticipates an exascale reality for the same 2020 target that other similarly-motivated nations are aiming to reach.

According to one Japanese news outlet, these exascale ambitions come at a relatively reasonable price, about the same as the K development costs—110 billion yen, or around $1.1 billion. Compared to cost projections elsewhere on the planet, this is bargain. Consider, for instance, India’s recent exascale funding effort worth $2 billion and the U.S. projects, which project a long-term investment of billions.

In the United States, these investments were kicked with $125 million in 2012 to fund preliminary research—an amount that wasn’t kicked back into the extreme scale pool this year with the most recent round of NSF funding despite the consensus that exascale by 2020 will remain a target.

At this point, it appears the $1.1 billion investment is to fund the conceptual design phase in Japan, although there are still details pending about the partner institutions and companies behind the research.

Funding numbers for exascale are all relative, since there are numerous cost considerations around the many phases of exascale; from research and development (which this funding appears to be supporting exclusively), then eventually system design and acquisition, and finally, the incredible resources to power an exascale machine.

]]>https://www.hpcwire.com/2013/05/09/floating_funding_to_exascale_island/feed/04058A Tale of Two Power Envelopeshttps://www.hpcwire.com/2012/04/10/a_tale_of_two_power_envelopes/?utm_source=rss&utm_medium=rss&utm_campaign=a_tale_of_two_power_envelopes
https://www.hpcwire.com/2012/04/10/a_tale_of_two_power_envelopes/#respondTue, 10 Apr 2012 07:00:00 +0000http://www.hpcwire.com/?p=4491Increases in the energy efficiency of microprocessors and sensors launched the mobile computing industry, but has left supercomputing users wanting more.

]]>It’s no secret that a main roadblock on the trail to exascale computing comes in the form of high power consumption. Throughout the history of computing, performance, and to a great extent, performance per watt, has grown exponentially in accordance to Moore’s law. However, there seems to be a growing divide between the power efficiency of smaller devices and the world’s fastest supercomputing clusters.

Jonathan Koomey of Technology Review wrote an article this week talking about the energy efficiency of computing devices. Specifically, he focused on the ratio of flops per kilowatt-hour (kWH), noting that the power required to perform a computational task is roughly halved every 18 months. Koomey points out that as processors have become increasingly power efficient, it has opened up whole new application areas, especially for battery-dependent mobile computing.

More than ever before, computers can simply do more with less. One of the most telling instances of this trend is seen in mobile and sensor-based devices. Koomey points to sensors that run on as little as 50 microwatts of energy and require no direct power source. Created by Joshua Smith from the University of Washington, these sensors gather energy from radio and television signals and relay weather information to indoor displays.

On the opposite side of the spectrum is Japan’s K Computer, which draws 12.7 megawatts of energy to deliver 10.5 petaflops. In this arena, performance is still the driver, with supercomputing users expecting roughly a 1000-fold increase in flops every decade. That’s about ten times the rate of increase that is naturally delivered by Moore’s Law. As a result, the annual cost of power for these high-end machines – about a million dollars per megawatt per year – is now a major limiting factor for new deployments.

Koomey points out that in theory the K Computer’s computational performance would be matched in the next 20 years by a device using less power than a typical toaster. Unfortunately, scientists and enterprises that need those flops today don’t have the luxury of time to wait.

Takeaway

While consumer-based devices are benefitting from the natural progression of energy efficiency delivered by the semiconductor industry, it’s simply not good enough to meet the needs of HPC users, especially for those at the top end. To reach exascale computing within reasonable power limits by the end of the decade, architectural innovation will be needed on top of what Moore’s Law will be able to deliver

]]>Hideaki Fujitani is a professor at Tokyo University’s Laboratory for Systems Biology and Medicine (LSBM). He has a supercomputer and aims to cure cancer with it — that according to a recent article in The Japan Times, in which Fujitani’s work is described.

According to the article, Fujitani spends most of his time running simulations of antibodies bonding, or attempting to bond, to antigens. For those of you who slept during biology class, antibodies are proteins the immune system uses to attach to antigens (foreign molecules); in this case Fujitani is studying antigens specific to cancer cells. The LSBM, led by Tatsuhiko Kodoma, is focused developing drugs for patients with recurring and advanced stages of cancer.

The simulations are aimed at making an antibody bond to and neutralize an antigen. There is one catch though, the simulation is of 30,000 to 40,000 atoms, made up of antigen, antibody and surrounding water. Also, the molecules move extremely fast, “A molecule moves in about 1 femtosecond, gradually changing the shape of proteins over microseconds,” says Fujitani, “To see the dynamics, you need to solve about one billion equations. If one CPU were able to solve one equation per second, it would still take 32 years to solve all the problems. That’s why we need the fastest supercomputer with lots of CPUs.”

Luckily for Fujitani the LSBM acquired a 612-core supercomputer in 2010 that can crack 34 teraflops. Just months after the super’s arrival, he was verifying his simulation results with an X-Ray of an actual antibody. As amazing as his work may seem, gaining support for computer-aided drug development was not so simple. He struggled to receive support from Fujitsu, his former employer, and the Japanese pharmaceutical industry, before taking his talents to the University of Tokyo.

Because of the nature of his practice, Fujitani can always use more computational power. Fortunately he will soon be getting that with a project that will tap into what is currently the fastest computer in the world, the 10-petaflop K computer. “The K will be 240 times faster than the machine here, so we can do the calculations much more quickly, and run different programs simultaneously,” he continued, “What takes a month to simulate here will be done in three or four days.”

Fujitani seems confident that the work he and the rest of Kodoma’s team will be able to find a cure for cancer. He says that in the future even people with advanced stages of cancer will be able to be cured.

]]>https://www.hpcwire.com/2012/02/13/working_fast_to_slow_things_down/feed/04545What I Learned at the International Supercomputing Conferencehttps://www.hpcwire.com/2011/06/23/what_i_learned_at_the_international_supercomputing_conference/?utm_source=rss&utm_medium=rss&utm_campaign=what_i_learned_at_the_international_supercomputing_conference
https://www.hpcwire.com/2011/06/23/what_i_learned_at_the_international_supercomputing_conference/#respondThu, 23 Jun 2011 07:00:00 +0000http://www.hpcwire.com/?p=4822HPC accelerator competition is heating up and Japanese supers are scrambling for watts.

]]>Flying halfway around the world to just gather news seems like a waste of time in the information age. But when it comes to supercomputing shows like ISC, being there in person cannot be duplicated by the remote experience, despite live streaming sessions, video blogs, and ISC twitter feeds.

Part of that has to do with the fact that information just seems to flow more freely under the chaotic conditions of a busy show floor. The other aspect is that exhibitors assume they’re talking to potential prospects, so the vendors tend to be a little looser lipped than I’m used to as a journalist.

For example, although Intel wasn’t willing to share with me over email last week that their first Many Integrated Core (MIC) product, aka Knights Corner, would support ECC memory, one person in the Intel booth at ISC did indeed confirm that MIC would be released with such support. (The Knights Ferry prototype is using a vanilla, i.e., non-ECC, graphics memory controller.) Like I mentioned in my original reporting of this week’s MIC news, it would be inconceivable not to have ECC support in this HPC product, so no big surprise here.

I also found out that the peak performance on the Knights Ferry prototype is 1.2 single precision (SP) teraflops. Given that the next year’s Knights Corner product will be on 22nm technology and will have about twice as many cores, I expect it will at least double that SP floating point teraflops, with maybe half the number for double precision (DP).

The GPU contingent from AMD won’t be intimidated from such floppery though. They told me that the next version of the FireStream HPC product will have twice the performance of the current model. The 9350 and 9370 products being shipped today deliver 528 DP gigaflops and 2.64 SP teraflops. The new FireStreams will be announced this fall — around SC11, I’m guessing — and will start shipping sometime in early 2012.

Meanwhile NVIDIA says it will deliver its next generation Kepler GPU architecture in 2012, At an ISC presentation by Nvidian Sumit Gupta, he estimated the new GPU will deliver about 5 DP gigaflops per watt, or maybe even better than that. “Kepler is going to be an amazing performance per watt GPU,” he promised.

If NVIDIA maintains the same thermal envelope as the current Fermi-class devices (225-250 watts), then the Kepler GPUs will be well north of a double precision teraflop. In fact all three 2012 HPC accelerators look to top one DP teraflop, but it is unlikely that any will reach 2 teraflops. With that kind of performance parity, the competitive differentiators may be energy efficiency and ease of programming.

In the latter case, Intel may have the edge. I heard a number of comments here in Hamburg that MIC is more straightforward to program than a GPU, at least to get an initial, non-optimized port — not just because it’s based on the x86 architecture, but because it lends itself more easily to standard multicore-style programming frameworks, like OpenMP. That indeed will warm the hearts of many application developers, inasmuch as a lots of code is already parallelized with OpenMP.

On the other hand, CUDA remains the more mature software environment for manycore acceleration at this point, and AMD said that the upcoming FireStream offerings will also include more advanced tools, libraries, and drivers. In any case, software development for accelerator programming is bound to get easier over the next year, but the devil will be in the details.

On the energy efficiency front, it looks like all three HPC accelerator offerings will need at least need 200 watts to hit a teraflop. It remains to be seen if Intel, NVIDIA, or AMD will have any appreciable edge.

On the broader topic of energy efficiency, there was lots of chatter at the conference about exascale power budgets. The current goal of US federal agencies is to have an exaflop fit into 20MW. That means to run such a system will cost about $20 million per year in the US and 20 million euros in Europe. Unfortunately, a number of people in the know at ISC thought that was quite an optimistic figure for the first exaflop systems. Estimates for these early machines ranged from as much 40MW (Cray CTO Steve Scott) to 200 MW (LSU prof Thomas Sterling).

The power problem is not a showstopper though. There are 100MW datacenters today and if the political will is there to fund power-sucking monsters at this scale, it could be done. Eventually exaflop systems will use 20MW, and less, but perhaps not the first crop of machines.

On a related note, Japan’s March 11 earthquake/tsunami disaster is already forcing that nation’s HPC community to deal with reduced power availability. Not that they weren’t already focused on energy efficiency. Japanese supercomputing has always had to adhere to strict power budgets since the nation lacks significant indigenous energy resources. But the situation is especially acute right now.

In a presentation at ISC, the University of Tsukuba’s Taisuke Boku told the audience that in the wake of the disaster, four one-gigawatt power plants are now offline. According to him, Tokyo residents, businesses, and other organizations (including HPC centers) will be required to cut their power usage by 15 percent this summer because of the downed plants.

Boku said this summer the university’s PACS-CS supercomputer will be shut down during the day, from 9:00 am to 9:00 pm, to deal with the power restriction shortage. And this is expected to continue for a number of years while Japan rebuilds its power plant infrastructure. The irony here is that PACS-CS uses low voltage Xeons, so is already is built for energy-efficient operation.

An even bigger irony is that the Japanese K Computer, which captured the number one spot on the TOP500 list is using about 10MW. The fact that an 8-petaflop machine uses half the 20MW that people are aiming for in an exaflop machine should be sobering enough. The bigger problem though is that power consumption for the top systems is increasing faster than gains in energy efficiency. As we say in the HPC biz, that doesn’t scale.

I actually have more to report from my Hamburg excursion, including some interesting developments to create net zero carbon HPC datacenters. But that will have to wait for another time.