"Design Compiler's topographical technology cuts weeks off of our project schedules by eliminating the time-consuming iterations between synthesis and layout that were previously required to close on design goals."

"Our success is driven by the timely delivery of highly reliable products to market. Design Compiler has made fast implementation time a reality by encapsulating synthesis and design-for-test into a single comprehensive solution that addresses our most challenging design and test requirements."

Albert Li, Director, Design Service Division, Global Unichip Corp.

"Design Compiler has been essential in meeting our design schedules on time for many years, and it continues to evolve to address our most challenging requirements."

Yan-Qiu Diao, Director, R&D Operations,HiSilicon Technologies

"Over the years, Design Compiler has delivered quality-of-results that exceed our design requirements. We have used Design Compiler to successfully tape-out hundreds of designs."

Rick Veres, Design Technology Manager, Honeywell Microelectronics

"Synopsys Design Compiler has consistently evolved to meet the most demanding needs of IBM's ASIC customers."

Richard Busch, Director of ASIC Products, IBM

"We continue to use Design Compiler because it has delivered extremely high quality-of-results for our complex designs and enables us to rapidly integrate new technologies."

"Design Compiler continually brings us innovative technologies that not only improve quality-of-results but also cut design time by delivering tight correlation with layout."

Jack Kao, Director of Design Service Dept., PGC

"For the last few years, we have used Design Compiler’s Topographical technology to find and fix design issues during synthesis to give us predictable implementation. We see Design Compiler 2010 synthesis results closely correlating to physical results, while accelerating placement in IC Compiler by 1.5X. This tight correlation between synthesis and layout, along with faster runtimes, is exactly what we need for reducing iterations and significantly shortening design schedules in 65 nanometer and smaller process technologies."

Shih-Arn Hwang,Deputy Director R&D CenterRealtek

"Cutting design time and improving design performance are essential to keep our competitiveness in the marketplace. With the new physical guidance extension to topographical technology we are seeing 5 percent correlation between Design Compiler and IC Compiler, up to 2X faster placement in IC Compiler and better design timing. We are adopting the new technology innovations in Design Compiler to minimize iterations while meeting our design goals in shorter timeframes."

"Manufacturing highly reliable products at low cost is essential to our business model. Having design-for-test built into Design Compiler makes it easy to implement cost-effective test that simultaneously meets timing, area and power targets."

"Our member companies are continuously seeking ways to cut design time to get to production faster. Design Compiler innovations such as topographical technology have been key to helping designers achieve higher productivity."

"Over the years Synopsys has introduced cutting-edge synthesis technologies to help our designers and customers achieve a faster path to TSMC silicon. Design Compiler has been a vital part of the TSMC Reference Flow for 10 years."