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Abstract

This article describes pipelining of pre-normalization of floating-point numbers in the Hex Fraction Chip (HFRAC) of the Engineering Scientific Accelerator card (ESA). The ESA performs Hex floating-point arithmetic. The HFRAC Chip contains the arrays which hold floating-point data, perform floating-point arithmetic exponent calculations, and perform normalization, of which there are two types: (Image Omitted) 1. Pre-normalization: shifting left of fractions of operands read out of array to eliminate leading zeroes. Exponent is updated by subtracting the shift amount from its value. 2. Post-normalization: shifting left of fractions of arithmetic results to eliminate leading zeroes before writing results into arrays.

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United States

Language

English (United States)

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Page 1 of 5

Pipeline Control in Pre-Norm Logic

This article describes pipelining of pre-normalization of
floating-point numbers in the Hex Fraction Chip (HFRAC) of the
Engineering Scientific Accelerator card (ESA). The ESA performs Hex
floating-point arithmetic. The HFRAC Chip contains the arrays which
hold floating-point data, perform floating-point arithmetic exponent
calculations, and perform normalization, of which there are two
types:

(Image Omitted)

1. Pre-normalization: shifting left of fractions of

operands read out of array to eliminate leading

zeroes. Exponent is updated by subtracting the

shift amount from its value.

2. Post-normalization: shifting left of fractions of

arithmetic results to eliminate leading zeroes

before writing results into arrays. Exponent is

updated by subtracting the shift amount from its

value. The logic necessary to perform the fraction portion
of normalization is a leading zero detect and a shifter. There is
one leading zero

(Image Omitted)

detect, and one
shifter on the HFRAC, which perform both pre-normalization and
post-normalization. (Fig. 1 contains a high-level block diagram which
displays the two distinct paths through the fraction normalization
logic). As can be seen in Fig. 1, a floating-point operand fraction
is read out of the array and latched up in the operand fraction
latch. If the operand requires pre-norm, the operand fraction is
routed through the normalization logic. After pre-norm, the operand
fraction is sent out on the operand fraction bus for arithmetic
processing. If the operand does not require pre-norm, the operand is
sent out on the operand fraction bus unaltered. Fig. 1 also shows the
floating-point result path through the normalization logic. An
incoming result fraction is latched up in the result fraction latch.

The latched data is then routed through the fraction normalization
logic and is stored in the floating-point data array when
post-normalization is complete. Fig. 2 is a block diagram of the
exponent normalization update which occurs in parallel with the
fraction shift. The fraction and

(Image Omitted)

exponent of a floating-point operand are read out of the array
simultaneously. If pre-norm is required, the exponent is routed
through the normalization logic and is decremented by the fraction
leading zero detect amount. After the pre-norm is complete, the

1

Page 2 of 5

exponent is routed through the exponent arithmetic manipulation
logic. If pre-norm is not required, then the exponent undergoes
arithmetic manipulation immediately. After exponent arithmetic
manipulation is complete, the exponent arithmetic result is latched
up in the intermediate exponent latch. The intermediate exponent
will reside in this latch until the corresponding arithmetic fraction
result arrives at the HFRAC. When this event occurs, the
intermediate exponent is routed through the normalization logic, so
that it can be updated by the amount of the post- norm shift
performed on the corresponding fra...