Optical offset signal cancellation for optical receiver

A laser driver for high speed interconnections may convert a digital signal to a current train of a bias mode to represent logical zero and of a modulation mode to represent logical one. An optical signal thus produced may include an optical offset. An optical receiver may include a photo-detector to receive the optical signal and generate a current signal, which includes a corresponding current offset. A first amplifier stage converts the current signal to a voltage signal and a second amplifier stage generates a digital output from the voltage signal. One or more low-pass filters may be used to filter the digital output and generate a filtered offset signal for a differential amplifier to generate an offset cancellation signal. The offset cancellation signal may be provided to offset cancellation circuitry to remove the current offset from the current signal generated by the photo-detector.

Description

RELATED APPLICATIONS

This is a continuation-in-part claiming, under 35 U.S.C. § 120, the benefit of the filing date of application Ser. No. 10/816,026 and of application Ser. No. 10/816,321, which were filed on Mar. 31, 2004 and are currently pending.

FIELD OF THE DISCLOSURE

This disclosure relates generally to the field of optical interconnects. In particular, the disclosure relates to an optical receiver with a current offset cancellation.

BACKGROUND OF THE DISCLOSURE

In the past decade optical communications has become an integral technology component for information systems. As semiconductor technology and advanced computing architectures have resulted in processors that operate at frequencies in multiples of GHz, electrical interconnects have become performance bottlenecks.

In 1998, researchers at Bell Labs transmitted 100 simultaneous optical signals using dense wave-division multiplexing over a distance of 400 km, each signal transmitted at a rate of 10 Gbps (gigabits per second). Therefore, optical interconnects show great promise in meeting the ever increasing demand for high speed communications.

The physical layer of an optical communication system may include a transmitter and a receiver, which communicate through an optical pipe such as an optical fiber or a wave guide. The optical transmitter may typically include a light emitter, circuitry to drive or modulate optical signals through the light emitter in response to electronic signals, a clock, and circuitry to convert and/or to encode data into a sequence of electronic signals. The optical receiver may typically include a light detector, circuitry to amplify the output of the light detector, clock recovery circuitry, and circuitry to sample and/or decode the data from the received signals.

Several characteristics of optical communication systems are critical to design choices. Speed is one of the most important characteristics. The rate at which an optical signal can be modulated and the transmitted data can be recovered, may determine, for example, the type of light emitter used, the design of the circuitry to drive or modulate the optical signals through the light emitter and/or the circuitry to amplify the output of the light detector and sample received signals. If an optical communication system is to be suitable to present and future processors operating at frequencies in multiples of GHz, it must be scalable at least to data rates of multiple Gbps.

Cost is another important characteristic of an optical communication system to be used as a component in information systems. If the optical components are not available in cost competitive technologies that are compatible with other components of the information system, they provide little advantage over duplication of existing electrical interconnects.

Reliability of the optical communication system in a variety of operating conditions and accounting for various manufacturing process variations is yet another important characteristic. The optical communication system must be reliable even if components of one manufacturing process are connected to components of another manufacturing process and these components must continue to be reliable, for example, in conditions of great heat or cold.

Such considerations have not been sufficiently addressed in prior art optical communication systems.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings.

FIG. 12 illustrates a flow diagram for one alternative embodiment of a process to receive optical signals

DETAILED DESCRIPTION

Methods and apparatus for optical signaling are disclosed herein. In one embodiment comprising a transmitter, a laser driver converts a digital voltage sequence to a current signal having a bias mode adjustable by a bias control and a modulation mode adjustable by a modulation control. A laser generates an optical signal responsive to the current signal of the laser driver. One embodiment of a laser driver for high speed optical interconnections includes a buffered level shifter (BLS) to shift the input voltage level to an appropriate level. In some embodiments the BLS may be tuned to provide a desired level shift with an impedance matched to the driving load. In some embodiments circuitry may also be provided to reduce any overshoot of the output signal and/or to reduce a frequency dependent part of the impedance seen by the AC signals

In one alternative embodiment comprising a receiver, a photo-detector receives an optical signal and generates a single ended current signal. A laser driver for high speed interconnections may convert a digital voltage sequence to a current signal of a bias mode to represent logical zero and of a modulation mode to represent logical one. An optical signal thus produced may include an optical offset. A transimpedance amplifier circuit converts the single ended current signal to a voltage signal. Some embodiments of the transimpedance amplifier circuit include an impedance matching capacitance for differential impedance matching. A second amplifier stage generates a digital output from the voltage signal. One or more low-pass filters may be used to filter the digital output and generate a filtered offset signal for a differential amplifier to generate an offset cancellation signal. The offset cancellation signal may be provided to offset cancellation circuitry to remove the current offset from the current signal generated by the photo-detector. A clock recovery circuit generates an aligned clock signal and a sampler circuit retrieves a digital voltage sequence from the aligned clock signal and the digital output.

These and other embodiments of the present invention may be realized in accordance with the following teachings and it should be evident that various modifications and changes may be made in the following teachings without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than restrictive sense and the invention measured only in terms of the claims and their equivalents.

FIG. 1a illustrates an embodiment of an exemplary optical signaling system 101. One such embodiment of optical signaling system 101 comprises an interface control 110 to interface with devices (not shown) for transmission and reception of data via optical signaling system 101, and a phase locked loop (PLL) circuit 119 to generate a clock signal from reference clock 118. Optical signaling system 101 also comprises serializer circuits 111, 121, . . . 131, each to receive the clock signal from PLL circuit 119 and to convert N-bit data from interface control 110 to a digital voltage input sequence for laser diode drivers 112, 122, . . . 132 respectively. Laser diode driver circuits 112, 122, . . . 132 are respectively coupled with control circuitry 114, 124, . . . 134, each comprising a bias control circuit and/or a modulation control circuit. Each of the laser diode driver circuits 112, 122, . . . 132 may receive a digital voltage input sequence and generate a corresponding current signal having a bias mode adjustable by their respective bias control circuit and a modulation mode adjustable by their respective modulation control circuit. Details of the bias control and modulation control are discussed further below, especially with respect to FIGS. 6a and 6b.

It will be appreciated that alternative embodiment of an optical signaling system may comprise only the circuitry for transmitting optical signals or alternatively only the circuitry for receiving optical signals in accordance with optical signaling system 101 or 102 without departing from the principles of the present invention. It will also be appreciated that the techniques of optical signaling systems 101 or 102 may be useful with a variety of technologies, for example: in semiconductor devices with wave guides, or between devices with optical fiber, or with Fabry-Perot (FP) lasers, or with distributed feedback (DFB) lasers, or with vertical-cavity surface emitting lasers (VCSELs), or with light emitting diodes (LEDs) rather than lasers. Further, if laser diodes 142, 152, . . . 162 and laser diodes 144, 154, . . . 164 are selected to generate optical signals of differing wave lengths responsive to the current signals of the laser diode drivers 112, 122, . . . 132, then techniques, such as wave division multiplexing (WDM) for example, may be used to increase the capacity and reduce the number and/or cost of the optical fiber or other wave guide channels connecting transmitters and receivers.

FIG. 2 illustrates an embodiment of a laser driver circuit 201 including a buffered level shifter circuit 211 to shift an input voltage level of modulation driver 213 to a first voltage level to generate a current of a modulation mode and to shift the input voltage level of bias driver 214 to a second voltage level to generate a current of a bias mode. For one embodiment, modulation driver 213 generates a 1-20 mA alternating current (AC) in modulation mode to represent a logical one (1) and bias driver 214 generates a 1-10 mA direct current (DC) in bias mode to represent a logical zero (0).

In the example embodiment of FIG. 2, a VCSEL laser diode 218 being driven by laser driver circuit 201 is anticipated to operate up to approximately 5-15 GHz or more producing data rates up to approximately 10-30 Gbps or more. In alternate embodiments, laser driver circuit 201 may also provide for modulation and/or bias mode adjustment, for example, for temperature variations, and may be useful to drive high speed DBF lasers, or FP lasers, or even LEDs at lower speeds.

Capacitor 215 may be a metal oxide semiconductor (MOS) capacitor coupled with bias driver 214 to reduce alternating current (AC) effects. In one embodiment, the capacitance value may be chosen as approximately 1 nF for capacitor 215. In one embodiment, the impedance value of package trace 217 may be approximately 50Ω and so the resistive value may be chosen as approximately 50Ω for resistor 216. Resistor 216 may be adjustable in some embodiments and may comprise, for example, one or more MOS field-effect transistors (MOSFETs).

FIG. 3 illustrates one alternative embodiment of a laser driver circuit 301 including a buffered level shifter circuit 311 tunable through k+1 control inputs to shift an input voltage level of modulation circuit 312 to a first voltage level to generate a current of a modulation mode and to shift the input voltage level of modulation circuit 312 to a second voltage level to generate a current of a bias mode. Details of embodiments of the buffered level shifter circuit 311 are discussed further below, especially with respect to FIGS. 4a and 4b.

Some embodiments of laser diode driver circuit 301 include a modulation control circuit 313 adjustable through up to n+1 control inputs to control generation of the current in modulation mode responsive to the input voltage level being shifted to the first voltage level. Some embodiments of laser diode driver circuit 301 include a bias control circuit 314 adjustable through up to m+1 control inputs to control generation of the current in bias mode responsive to the input voltage level being shifted to the second voltage level. Details of embodiments of the modulation circuit 312, modulation control circuit 313 and bias control circuit 314 are discussed further below, especially with respect to FIGS. 6a and 6b.

In one embodiment, the resistive value for resistor 316 may be chosen so to substantially match the impedance of package trace 317. A capacitance 315 may also be coupled with the bias control circuit 314. In some embodiments of laser diode driver circuit 301, an array of capacitors 501 is coupled with the bias control circuit 314 to reduce the AC component effects of the bias mode current. In one embodiment, the total capacitance value may be chosen as approximately 1 nF or less for capacitor 315. Details of the array of capacitors 501 are discussed further below, especially with respect to FIG. 5.

VCSEL laser diode 318 is being driven by a current IVCSEL of laser driver circuit 301, but in alternate embodiments, laser driver circuit 301 may be used to drive other types of lasers or LEDs.

FIG. 4a illustrates an embodiment of a buffed level shifter 401 for use in a laser driver circuit or other light emitting device driver. Buffered level shifter circuit 401 is tunable through k+1 control inputs to shift an input voltage level of a modulation circuit to a controlled voltage level at a controlled rate and with adjustable impedance. For example, responsive to a transitioning input, DIN, the inverter formed by pMOSFET 414 and nMOSFET 415 begins shifting the voltage level of DOUT in the opposite direction. If the control input, cs0, is set, then the transitioning input gated by gates 420 and 421 is propagated to the inverter formed by pMOSFET 410 and nMOSFET 411, which assists with shifting the voltage level of DOUT in the opposite direction of transitioning input, DIN. Similarly if any of the control inputs up to and including csk are set, then the transitioning input gated by corresponding pairs of gates up to and including 422 and 423 is propagated to their corresponding inverters up to and including the inverter formed by pMOSFET 412 and nMOSFET 413, which assist with shifting the voltage level of DOUT in the opposite direction of the transitioning input, DIN.

For one embodiment of a buffed level shifter 401, devices of the inverter formed by pMOSFET 410 and nMOSFET 411 up to and including the inverter formed by pMOSFET 412 and nMOSFET 413 may be sized in conveniently selected multiples, for example, powers of two (1×, 2×, 4×, etc.) to facilitate more precise tuning of the voltage level, rate and impedance through the k+1 control inputs.

FIG. 4b illustrates an alternative embodiment of a buffed level shifter 402 for use in a laser driver circuit or other light emitting device driver. Buffered level shifter circuit 402 is tunable through k+1 control inputs to shift an input voltage level of a modulation circuit to a controlled voltage level at a controlled rate and with adjustable impedance. For example, responsive to a transitioning input, DIN, the inverter formed by pMOSFET 414 and nMOSFET 415 begins shifting the voltage level of DOUT in the opposite direction. If any of the even control inputs, cs0, up to and including csk−1 are set, then the transitioning input gated by corresponding gates from 420 up to and including 422 is propagated to a corresponding pMOSFET 410 up to and including 412, which assist with shifting the voltage level of DOUT toward VCC when the input, DIN, is transitioning in the opposite direction (away from VCC). If any of the odd control inputs, cs1, up to and including csk are set, then the transitioning input gated by corresponding gates from 421 up to and including 423 is propagated to a corresponding nMOSFET 411 up to and including 413, which assist with shifting the voltage level of DOUT away from VCC when the input, DIN, is transitioning in the opposite direction (toward VCC). Therefore in buffed level shifter 402, control inputs for pMOSFET devices 410 up to and including 412 and for nMOSFET 411 up to and including 413 may be set to tune the voltage levels, transition rates and impedances independently for rising and falling transitions through the k+1 control inputs.

It will be appreciated that the buffered level shifter may be modified in arrangement and detail by those skilled in the art without departing from the principles of the present invention, for example, being realized as another type of tunable segmented driver or alternatively as a conventional inverter array.

FIG. 5 illustrates an embodiment of an array of capacitors 501 for use in a laser driver circuit or other light emitting device driver. In order to reduce the series resistance introduced by a large capacitor, capacitor 215 or 315 may be partitioned into hundreds of small MOS capacitors 510, 511, . . . 516 and arrayed as shown in FIG. 5. Thus the series resistance realized may be negligible when compared with the termination resistance, for example, of approximately 50Ω for resistor 216.

FIG. 6a illustrates another alternative embodiment of a diode driver circuit 601 for a laser or an LED including a buffered level shifter circuit 611 tunable through k+1 control inputs to shift an input voltage level of modulation circuit 612 to a first voltage level to generate a current of a modulation mode and to shift the input voltage level of modulation circuit 612 to a second voltage level to generate a current of a bias mode.

For some embodiments of driver circuit 601, a CMOS modulation circuit 612 causes current, ILE, of the modulation mode to flow from the VccLE source through nMOSFET 622 responsive to the input voltage level being shifted to the first voltage level. Modulation circuit 612 causes a current to flow from the Vcc source through pMOSFET 621 and current, ILE, of the bias mode to flow from the VccLE source through resistor 616 responsive to the input voltage level being shifted to the second voltage level.

Diode driver circuit 601 includes a modulation control circuit 613 adjustable through up to n+1 control inputs to control generation of the current in modulation mode responsive to the input voltage level being shifted to the first voltage level. Diode driver circuit 601 also includes a bias control circuit 614 adjustable through up to m+1 control inputs to control generation of the current in bias mode responsive to the input voltage level being shifted to the second voltage level.

For some embodiments of a modulation control circuit 613, nMOSFET 630 and/or nMOSFET 631 up through nMOSFET 632 may be sized in conveniently selected multiples, for example, powers of two (1×, 2×, 4×, etc.) to facilitate more precise adjustment of the current in modulation mode through the n+1 control inputs, mc0, mc1, . . . mcn. For some embodiments of a bias control circuit 614, nMOSFET 640 and/or nMOSFET 641 up through nMOSFET 642 may be sized in conveniently selected multiples to facilitate more precise adjustment of the current in bias mode through the m+1 control inputs, bc0, bc1, . . . bcm. It will be appreciated that any or all of the control inputs for modulation control circuit 613 and/or bias control circuit 614 may come from a central control unit or self adaptive control circuit(s).

In one embodiment, the resistive value for resistor 616 may be chosen so to substantially match a package trace impedance. Capacitor 615 may also be coupled with the bias control circuit 614 to reduce the AC component effects of the bias mode current.

Light emitter 618 may represent a VCSEL laser diode, or a DBF laser diode, or a multi-quantum well (MQW) or buried hereto (BH) or other style of FP laser diode, or an edge- or surface-emitting LED being driven by a current ILE of driver circuit 601.

FIG. 6b illustrates another alternative embodiment of a VCSEL laser diode driver circuit 602 including tunable buffered level shifter circuit 611 to shift the input voltage level of modulation circuit 652 to a first voltage level to generate a current of a modulation mode and to shift the input voltage level of modulation circuit 652 to a second voltage level to generate a current of a bias mode.

For some embodiments of driver circuit 602, a CMOS modulation circuit 652 causes current, IVCSEL, of the modulation mode to flow from the VccVCSEL voltage source through nMOSFET 622 and nMOSFET 623 responsive to the input voltage level being shifted to the first voltage level. Modulation circuit 652 causes a current to flow from the Vcc source through pMOSFET 621 and current, IVCSEL, of the bias mode to flow from the VccVCSEL source through resistor 616 responsive to the input voltage level being shifted to the second voltage level. For some embodiments of modulation circuit 652, the input gate of nMOSFET 623 may be coupled with the Vcc source or some other source voltage to reduce current overshoot of IVCSEL.

Driver circuit 602 includes adjustable modulation control circuit 613 to control generation of the current in modulation mode responsive to the input of the first voltage level and adjustable bias control circuit 614 to control generation of the current in bias mode responsive to the input of the second voltage level.

Modulation control circuit 613 provides for adjustment of the current in modulation mode through nMOSFET 630 and/or nMOSFET 631 up through nMOSFET 632 and the corresponding n+1 control inputs, mc0, mc1, . . . mcn. Bias control circuit 614 provides for adjustment of the current in bias mode through nMOSFET 640 and/or nMOSFET 641 up through nMOSFET 642 and the corresponding m+1 control inputs, bc0, bc1, . . . bcm. Control inputs for modulation control circuit 613 and/or bias control circuit 614 may come from a central control unit or self adaptive control circuit(s).

The resistive value for resistor 616 may be chosen so to substantially match a package trace impedance. Capacitor 615 may be coupled with bias control circuit 614 to reduce the AC component effects of the bias mode current. VCSEL laser diode 658 is being driven by a current IVCSEL of driver circuit 602, but in alternate embodiments, driver circuit 602 may be used to drive other types of lasers or LEDs.

It will be appreciated that a laser driver for high speed interconnections may convert a digital signal to a current train of a bias mode to represent logical zero and of a modulation mode to represent logical one. The operation of such a laser driver to achieve nominal switching performance may typically require a DC bias. Thus the optical signal produced by the laser may include an optical offset.

FIG. 7a illustrates an embodiment of an optical receiver 701. Optical receiver 701 includes photo-detector 745 to receive the optical signal and generate a current signal at input port 716, which includes a corresponding current offset. A first transimpedence amplifier stage 741 converts the current signal to a voltage signal and a second post amplifier stage 751 generates a digital output at output port 718 from the voltage signal. An offset cancellation circuitry 704 comprises a low-pass filter to filter the digital output and generate a filtered offset signal for a differential amplifier to generate an offset cancellation signal. The offset cancellation signal is provided to the offset cancellation circuitry 704 to remove the current offset at input port 716 from the current signal generated by the photo-detector 745.

FIG. 7b illustrates alternative embodiment of an optical receiver 702. Optical receiver 702 includes photo-detector current source 745 to receive the optical signal and generate a current signal at input port 716, which includes a corresponding current offset. A first transimpedence amplifier stage 743 driven by photo-detector current source 745 and capacitor 747 converts the current signal to voltage signals and a second post amplifier stage 753 generates digital outputs at output ports 718 and 719 from the voltage signals. An offset cancellation circuitry 706 comprises low-pass filters to filter the digital outputs and generate filtered offset signals for a differential amplifier to generate an offset cancellation signal. The offset cancellation signal is provided to the offset cancellation circuitry 706 to remove the current offset at input port 716 from the current signal generated by the photo-detector 745.

FIG. 7c illustrates an embodiment at the circuit level of a transimpedance amplifier 703 driven by a photo-detector current source 745 and capacitor 747 for use in an optical receiver. The amplifier of FIG. 7c provides a differential output voltage {VOUT, VOUT} at output ports 718 and 719. Ideally, under noiseless conditions these voltages may be written as VOUT=v+V0 and VOUT=−v+V0, where v is a small-signal voltage and V0 a voltage between ground and supply voltage VDD. In some embodiments, V0=VDD/2. (If the two supply voltages are VDD and VSS rather than VDD and ground, then clearly VDD>V0>VSS.) Ideally, the small-signal voltage v is proportional to the small-signal photo-detector current IPD.

It is expected that noise due to power supply and substrate coupling will be equally present in both voltages VOUT and VOUT. The differential voltage {VOUT, VOUT} may be further amplified by differential post-amplifiers. Differencing the two components of the differential voltage {VOUT, VOUT}, or differencing its differential amplification, subtracts out much of the noise. In this way, it is expected that the embodiment of FIG. 7c has utility in noisy environments.

The amplifier of FIG. 7c has three stage pairs. Each pair has two inverter amplifiers. The first pair of stages has a first inverter comprising pMOSFET 710 and nMOSFET 712, and a second inverter comprising pMOSFET 711 and nMOSFET 713. Resistor 714 provides negative feedback for the first inverter pMOSFET 710 and nMOSFET 712, and resistor 715 provide negative feedback for the second inverter pMOSFET 711 and nMOSFET 713. These inverter amplifiers are matched. That is, pMOSFETs 710 and 711 are matched to each other, i.e., they have the same betas, nMOSFETs 712 and 713 are matched to each other, and resistors 714 and 715 have the same resistance value.

Each of the inverter amplifiers with negative feedback in the first stage pair is seen to be a simple transimpedance amplifier, where under reasonable assumptions the low frequency transimpedance is the resistance of resistor 714 for the first inverter amplifier and 715 for the second inverter amplifier. These resistors also set the bias levels of the pMOSFETs and nMOSFETs in the first stage pair so that the inverter amplifiers operate in their linear high gain region, and resistor 714 also provides a current path for the photo-detector.

The first inverter amplifier in the first stage pair has its input port 716 connected to the photo-detector. However, input port 717 is connected to an impedance matching capacitor 747 having the same capacitance as photo-detector capacitor 746 for differential impedance matching. It will be appreciated that photo-detector capacitor 746 may represent the inherent capacitance of a combined package trace and photo-detector current source 745. More generally, input port 717 should be loaded by the same impedance as seen by input port 716 looking into the photo-detector, or whatever source is driving the amplifier.

The second (or middle) stage pair in the embodiment of FIG. 7 has two inverter amplifiers, the first inverter amplifier comprises pMOSFET 720 and nMOSFET 722, and the second inverter amplifier comprises pMOSFET 721 and nMOSFET 723. Resistor 725 provides feedback from output port 736 of the first inverter amplifier in the second stage pair to input port 727 of the second inverter amplifier in the second stage pair. Resistor 724 provides feedback from output port 737 of the second inverter amplifier in the second stage pair to input port 726 of the first inverter amplifier in the second stage pair. The first and second inverter amplifiers in the second stage pair are matched to each other, and the resistors 724 and 725 have the same resistance.

The third stage pair in the embodiment of FIG. 7c is identical in structure to the first stage pair. However, although resistors 728 and 729 are matched to each other, i.e., they have the same resistance, they need not necessarily have the same resistance as resistors 714 and 715. Similarly, although pMOSFETs 730 and 731 are matched to each other, they are not necessarily matched to pMOSFETs 710 and 711. A similar statement applies to nMOSFETs 732 and 733. The inverters with negative feedback used in the first and second stage pairs of FIG. 7c may be referred to as shunt-shunt feedback amplifier stages.

By employing resistive cross coupling (resistors 724 and 725) between the two inverter amplifiers in the second stage pair, the signal is complementary coupled while the resistive network helps to attenuate common noise That is, the signal is coupled through resistive voltage dividers while the common noise is attenuated. (Resistors 714 and 724 form one of the voltage dividers, and resistors 715 and 725 form the other one.) The coupling intensity and common mode noise attenuation depend on the value of the resistors 724 and 725 relative to the feedback resistors 714 and 715 and the feedback resistors 728 and 729. In one embodiment, the resistive values may be chosen as 200Ω for resistors 714 and 715, 100Ω for resistors 724 and 725, and 300Ω for resistors 728 and 729. These resistive values are meant to represent relative ratios of resistive values, so that the resistors may be scaled to maintain these relative ratios.

Various modifications may be made to the disclosed embodiments without departing from the scope of the invention as claimed below. For example, other resistive feedback elements may be used in place of the resistors in FIG. 7c. As one example, pMOSFETs may be used. In other embodiments, nMOSFETs may be used, or various combinations of different resistive feedback elements may be used.

FIG. 7d illustrates an alternative embodiment of offset cancellation in an optical receiver 708. Optical receiver 708 includes photo-detector current source 745 to receive the optical signal and generate a current signal at input port 716, which includes a corresponding current offset. A first transimpedence amplifier stage 743 driven by photo-detector current source 745 and capacitor 747 converts the current signal to voltage signals and a second post amplifier stage 753 generates digital outputs at output ports 718 and 719 from the voltage signals. An offset cancellation circuitry 706 comprises low-pass filter 748 and low-pass filter 749 to filter the digital output voltages VOUT and VOUT and to generate filtered offset signals for a differential amplifier at gate inputs of nMOSFETs 738 and 739 to generate an offset cancellation signal. The offset cancellation signal is provided to the offset cancellation circuitry 706 at gate input of nMOSFETs 744 to remove the current offset at input port 716 from the current signal generated by the photo-detector source 745.

Offset cancellation circuitry may be used to remove the low-pass filtered portion of the current signal, enabling a high gain in the receiver independent of the offset amplitude. Thus greater sensitivity and more robust operation is permitted and the receiver is tolerant of signal amplitude variations. Low-pass filtering the output voltages VOUT and VOUT at the end of the amplification chain provides for negligible impact to the current signal input from any transistor mismatch offset in the differential amplifier circuit.

FIG. 8 illustrates another alternative embodiment of an optical signaling system 801 comprising an interface control 810 to interface with devices (not shown) for transmission and reception of data via optical signaling system 801, and a phase locked loop (PLL) circuit 819 to generate a clock signal from reference clock 818. Optical signaling system 801 also comprises serializer circuits 811, 821, . . . 831, each to receive the clock signal from PLL circuit 819 and to convert data from interface control 810 to a digital voltage input sequence for laser diode drivers 812, 822, . . . 832 respectively. Laser diode driver circuits 812, 822, . . . 832 are respectively coupled with control circuitry 814, 824, . . . 834, each comprising a bias control circuit and/or a modulation control circuit. Each of the laser diode driver circuits 812, 822, . . . 832 may receive a digital voltage input sequence and generate a corresponding current signal having a bias mode adjustable by their respective bias control circuit and a modulation mode adjustable by their respective modulation control circuit.

FIG. 9 illustrates an embodiment of a clock recovery circuit 901 for use in an optical receiver. Some embodiments of lock recovery circuit 901 comprise a delay locked loop (DLL) 911 and a phase interpolator 932 to generate an aligned clock signal from the reference clock signal received from an optical channel. In operation, the reference clock signal, CLK, is input to DLL 911. DLL 911 may generate multiple equally-delayed differential signals. These multiple equally-delayed differential signals may be buffered by clock buffering circuitry 920 for input to phase interpolator 932. Clock buffering circuitry 920 comprises controlled delay elements 921-924. The delays of controlled delay elements 921-924 along with controlled delay element 910 may be adjusted by DLL 911 control voltage(s). The phase interpolator 932 aligns the edges of the aligned clock signal, CLKOUT, with a data stream center in a much higher resolution.

FIG. 10 illustrates a flow diagram for one embodiment of a process 1001 to transmit and a process 1002 to receive optical signals. Processes 1001 and 1002 and other processes herein disclosed are performed by processing blocks that may comprise dedicated hardware or software or firmware operation codes executable by general purpose machines or by special purpose machines or by a combination of both.

Transmitting begins in processing block 1011 where an N-bit data is serialized to generate a digital voltage sequence. Processing continues in processing block 1012 where the digital voltage sequence is converted to a first current signal having an adjustable bias mode and an adjustable modulation mode, for example as described above with reference to FIGS. 3, 6a and 6b. In processing block 1013, a laser diode or light emitting diode is driven using the first current signal to generate an optical signal transmission.

Receiving begins in processing block 1014 where an optical signal reception is converted by a photo detector into a first single-ended voltage signal. In processing block 1015, the first single-ended voltage signal and a second single-ended voltage signal are complimentary and resistively coupled, for example as described above with reference to FIG. 7, to generated a differential voltage signal to attenuate common signal noise. Finally, in processing block 1016, the differential voltage signal is sampled and deserialized to generate the transmitted data.

It will be appreciated that while both transmission and reception of optical signals may occur in a single device, the data being transmitted by one device may typically be received by another device.

FIG. 11a illustrates a flow diagram for one alternative embodiment of a process 1101 to transmit optical signals. Transmitting begins with processing block 1111 where a digital clock signal is generated. In processing block 1112 an N-bit data is serialized using the digital clock signal to generate a digital voltage sequence. Processing continues in processing block 1113 where the digital voltage sequence is converted to a data current signal having an adjustable bias mode and an adjustable modulation mode. In processing block 1114, a laser diode or light emitting diode is driven using the data current signal to generate an optical data signal transmission. In processing block 1115, the digital clock signal is converted to a clock current signal having an adjustable bias mode and an adjustable modulation mode. Processing continues in processing block 1116 where a laser diode or light emitting diode is driven using the clock current signal to generate an optical clock signal transmission.

It will be appreciated that one or more of the processing blocks of process 1001, 1002, 1101 and/or 1102 may be executed in parallel or concurrently or out of the order depicted without departing from the principles of the present invention. For example, it would be anticipated that transmitting of process 1001 and receiving of process 1002 may occur in various orders within a system including in parallel or concurrently or out of the order depicted; or that processing blocks 1113-1116 may be executed in parallel or concurrently or out of the order depicted. Therefore the drawings are to be regarded in an illustrative rather than a restrictive sense.

FIG. 11b illustrates a flow diagram for another alternative embodiment of a process 1102 to transmit optical signals. Transmitting begins with processing block 1121 where a digital voltage sequence is generated. Processing continues in processing block 1122 where the digital voltage sequence is converted to a current signal having an adjustable bias mode and an adjustable modulation mode. In processing block 1123, the bias mode of the current signal is optionally adjusted through one or more bias control inputs. In processing block 1124, the modulation mode of the current signal is optionally adjusted through one or more modulation control inputs. In processing block 1115, a laser diode or light emitting diode is driven using the current signal to generate an optical data signal transmission.

FIG. 12 illustrates a flow diagram for one alternative embodiment of a process to receive optical signals. Receiving begins in processing block 1211 where an optical data signal reception is converted by a photo detector into a single-ended data voltage signal. Processing continues in processing block 1212 where the single-ended data voltage signal and another single-ended voltage signal are complimentary and resistively coupled to generated a differential voltage signal and to attenuate common signal noise. In processing block 1213 an optical clock signal reception is converted by a photo detector into a single-ended clock voltage signal. Processing continues in processing block 1214 where the single-ended clock voltage signal and another single-ended voltage signal are complimentary and resistively coupled to generated a differential clock voltage signal and to attenuate common signal noise. In processing block 1215 a digital clock signal is recovered from the differential clock signal using a DLL and a phase interpolator. Finally, using the digital clock signal in processing block 1016, the differential data voltage signal is sampled and deserialized to generate the transmitted data.

Thus, processes using integrated high speed optical I/O circuitry may provide very high bandwidth digital interconnects.

The above description is intended to illustrate preferred embodiments of the present invention. From the discussion above it should also be apparent that especially in such an area of technology, where growth is fast and further advancements are not easily foreseen, the invention may be modified in arrangement and detail by those skilled in the art without departing from the principles of the present invention within the scope of the accompanying claims and their equivalents.

Claims

1. An optical receiver comprising:

a first photo-detector to receive a first optical signal and to generate a first current signal;

a first amplifier stage to convert the first current signal to a differential voltage signal comprising a first voltage signal and a second voltage signal, the first amplifier stage comprising a first transimpedance amplifier circuit;

a second amplifier stage coupled with the first amplifier stage to generate a differential digital output comprising a first digital output and a second digital output;

a first low-pass filter circuit to filter the first digital output and generate a first filtered offset signal;

a differential amplifier to receive the first filtered offset signal and a bias voltage and to generate an offset cancellation signal; and

an offset cancellation circuit to receive the offset cancellation signal and to remove a current offset from the first current signal.

2. The optical receiver of claim 1 comprising a second low-pass filter circuit to filter the second digital output and generate a second filtered offset signal; said differential amplifier to receive the first and second filtered offset signals and a bias voltage to generate said offset cancellation signal.

3. The optical receiver of claim 1 wherein said first transimpedance amplifier circuit complimentary couples a first single-ended voltage signal corresponding to the first current signal with a second single-ended voltage signal to generate the differential voltage signal comprising the first voltage signal and the second voltage signal, and resistively couples said first and second single-ended voltage signals to attenuate a common signal noise.

4. The optical receiver of claim 3, said first transimpedance amplifier circuit further comprising: a differential impedance matching capacitor to provide an input impedance for the second single-ended voltage signal to match a package trace impedance corresponding to the first photo-detector.

5. The optical receiver of claim 4 wherein said second amplifier stage generates a differential digital output comprising the first digital output and a second digital output.

6. The optical receiver of claim 5 further comprising:

a second photo-detector to receive a second optical signal and to generate a second current signal;

a second transimpedance amplifier circuit coupled with a third amplifier stage to convert the second current signal to a differential clock signal;

a clock recovery circuit having a phase interpolator to generate an aligned clock signal for said differential digital output from the differential clock signal.

7. The optical receiver of claim 6 further comprising:

a delay locked loop to generate a plurality of clock phases from the differential clock signal; and

said phase interpolator to generate the aligned clock signal from the plurality of clock phases.

8. An optical signaling system comprising:

a laser driver to receive a first digital voltage sequence and to generate a first current signal; a laser to generate a first optical signal responsive to the first current signal of the laser driver;

a first photo-detector to receive a second optical signal and to generate a second current signal;

a first amplifier stage having a first transimpedance amplifier circuit to convert the second current signal to a first differential voltage signal;

a second amplifier stage to generate a differential digital output comprising a first digital output and a second digital output from the first differential voltage signal;

a first low-pass filter circuit to filter the first digital output and generate a first filtered offset signal;

a second low-pass filter circuit to filter the second digital output and generate a second filtered offset signal; said differential amplifier to receive the first and second filtered offset signals and a bias voltage to generate said offset cancellation signal;

a differential amplifier to receive the first filtered offset signal and a bias voltage and to generate an offset cancellation signal; and

an offset cancellation circuit to receive the offset cancellation signal and to remove a current offset from the first current signal.

9. The optical signaling system of claim 8 further comprising: a tunable buffered level shifter to shift an input of the laser driver to a controlled voltage level responsive to a transition of said first digital voltage sequence.

10. The optical signaling system of claim 9, said laser driver further comprising:

a bias control and a modulation control, wherein the first current signal has a bias mode adjustable by said bias control and a modulation mode adjustable by said modulation control;

a CMOS modulation circuit having a pMOSFET, a first nMOSFET and a second nMOSFET, the CMOS modulation circuit to cause the first current signal in the modulation mode to flow between the laser, the first nMOSFET and the second nMOSFET responsive to the input of the laser driver being shifted to a first voltage level, and to causes the first current signal in the bias mode to flow between the laser and the bias control when another current flows through the pMOSFET responsive to the input of the laser driver being shifted to a second voltage level.

11. The optical signaling system of claim 10 wherein an input gate of the third nMOSFET is to reduce an overshoot of the first current signal.

12. The optical signaling system of claim 10 wherein adjusting the modulation mode of the current signal is accomplished by setting one or more inputs of the modulation control.

13. The optical signaling system of claim 10 wherein adjusting the bias mode of the current signal is accomplished by setting one or more inputs of the bias control.

14. The optical signaling system of claim 8 wherein said first transimpedance amplifier circuit complimentary couples a first single-ended voltage signal corresponding to the first current signal with a second single-ended voltage signal to generated said first differential voltage signal, and resistively couples said first and second single-ended voltage signals to attenuate a common signal noise.

15. The optical signaling system of claim 14, said first transimpedance amplifier circuit further comprising: a differential impedance matching capacitor to provide an input impedance for the second single-ended voltage signal to match a package trace impedance corresponding to the first photo-detector.

16. The optical signaling system of claim 8 further comprising:

a second photo-detector to receive a third optical signal and to generate a third current signal;

a second transimpedance amplifier circuit coupled with a third amplifier stage to convert the third current signal to a differential clock signal;

a clock recovery circuit having a phase interpolator to generate an aligned clock signal for said differential digital output from the differential clock signal.

17. The optical signaling system of claim 16 further comprising: a delay locked loop to generate a plurality of clock phases from the differential clock signal; and said phase interpolator to generate the aligned clock signal from the plurality of clock phases.

18. An optical signaling system comprising:

a laser driver to generate a first current signal having a bias mode and a modulation mode;

a laser to generate a first optical signal responsive to the first current signal of the laser driver; a first photo-detector to receive a second optical signal and to generate a second current signal;

a first amplifier stage to convert the second current signal to a differential voltage signal comprising a first voltage signal and a second voltage signal, said first amplifier stage comprises a first transimpedance amplifier circuit;

a second amplifier stage to generate a differential digital output comprising a first digital output and a second digital output from the first voltage signal and the second voltage signal;

a first low-pass filter circuit to filter the first digital output and generate a first filtered offset signal;

a differential amplifier to receive the first filtered offset signal and a bias voltage and to generate an offset cancellation signal; and

an offset cancellation circuit to receive the offset cancellation signal and to remove a current offset from the first current signal.

19. The optical signaling system of claim 18 comprising a second low-pass filter circuit to filter the second digital output and generate a second filtered offset signal; said differential amplifier to receive the first and second filtered offset signals and a bias voltage to generate said offset cancellation signal.

20. The optical signaling system of claim 18 said laser driver further comprising: a bias control and a modulation control, wherein the bias mode of the first current signal is adjustable by said bias control and the modulation mode of the first current signal is adjustable by said modulation control.