Apparatus for Efficiently Coupling Light from a Light Source into a Thin Object - An apparatus for efficiently coupling light from a light source into a thin object such as a rod or a sheet is disclosed. In an embodiment, the apparatus comprises a sheet and a linear light source placed along the edge of the sheet. The light from linear light source is coupled into the sheet using one or more concentrator blocks. In another embodiment, the apparatus comprises a rod and a point light source placed near one end of the rod. The light from point light source is coupled into the rod using one or more concentrator blocks.

2011-01-20

20110013419

LINEAR LIGHT GUIDING MODULE - A linear light guiding module is provided, which includes a linear light guiding body, a plurality of light emitting bodies, a plurality of heat sinks, and a plurality of fans. With the linear light guiding body, the light emitting bodies, and the heat sinks linearly arranged, or with the fans further integrated, the linear light guiding module of the present invention has a small size and an effective heat-dissipation effect. Since only one linear light guiding module needs to be disposed on one side of a light guide plate, the linear light guiding module can be used in large-sized liquid crystal display panels. Moreover, the number of the linear light guiding modules used is decreased while the requirements for high brightness and brightness uniformity can still be met, so the cost can be reduced.

2011-01-20

20110013420

LIGHT EMITTING DEVICES AND APPLICATIONS THEREOF - In one aspect, the present invention provides light emitting devices, including light fixtures and luminaires. In some embodiments, a light emitting device comprises at least one light source, a lightguide operable to receive light from the at least one light source at a first location on the lightguide, at least one light extraction region optically coupled to the lightguide and a substantially non-scattering region along a portion of the lightguide.

2011-01-20

20110013421

BACKLIGHT UNIT - The present invention relates to a backlight unit including a plurality of light guide plates, each discretely arranged with an interval, one or more light sources formed at a lateral surface of the plurality of light guide plates, and a filling material filled among the plurality of light guide plates and having a lower refractive index than that of the light guide plate, whereby each of the plurality of light guide plates can be split-driven to guarantee a uniform luminance at an interval among the plurality of light guide plates.

2011-01-20

20110013422

LIGHT-EMITTING DEVICE - This application relates to a light-emitting device comprising a light channel having an upper surface, a lower surface opposite to the upper surface, an inner surface intersecting with each of the upper and lower surface by different angles, and an escape surface; and a light-emitting element having a bottom surface substantially parallel to the inner surface and emitting light traveling inside the light channel toward the escape surface. In an embodiment, the escape surface of the light-emitting device is an inclined plane with lens array thereon.

2011-01-20

20110013423

LIGHT INJECTION SYSTEM AND METHOD FOR UNIFORM LUMINOSITY OF WAVEGUIDE-BASED DISPLAYS - The attenuation of light per unit length in a waveguide as a result of active pixels (i.e., open pixels) may be corrected or mitigated by injecting apodized light into the waveguide. A light injection system and method is provided to enhance the luminous uniformity of the active pixels in a waveguide-based display. Embodiments of the present invention include a slab waveguide having a first edge and a second edge that intersect at a vertex, a first light source disposed along the first edge, and a second light source disposed along the second edge. The first light source, or the second light source, or both, comprises an apodized light source.

2011-01-20

20110013424

FORWARD CONVERTER WITH SECONDARY SIDE POST-REGULATION AND ZERO VOLTAGE SWITCHING - The present invention discloses a forward converter with secondary side post-regulation and zero voltage switching, where the primary side power loop may adopt a single or a dual transistor structure, driven by a primary side driving circuit with a constant duty ratio so that the voltage waveform across the secondary side power winding has a constant pulse width; the secondary side power loop uses a controllable switch, a magnetic amplifier (MA) or an N channel metal oxide semiconductor field transistor (NMOS), to blank the leading edge of the voltage waveform across the secondary side power winding, regulate the output voltage, and achieve zero voltage switching of primary side switch transistors.

2011-01-20

20110013425

High step-up ratio soft-switched flyback converter - A converter circuit includes a transformer having a first side and a second side. The converter circuit also includes a switch coupled to the first side of the transformer. The converter circuit further includes a rectifying diode coupled to the second side of the transformer and to a first output terminal of the converter circuit. In addition, the converter circuit includes a clamping diode coupled to the second side of the transformer, to the rectifying diode, and to a second output terminal of the converter circuit. The converter circuit may include a boost section and a flyback section. The converter circuit may also include an active clamp and an isolated flyback section.

2011-01-20

20110013426

SNUBBER CAPACITOR GENERATING AN AUXILLARY POWER SUPPLY VOLTAGE - An integrated circuit (IC) forming a pulse-width modulator controls the switching operation of an output stage of a switching power supply. A snubber capacitor that is coupled to a primary winding of a transformer of the output stage is used for producing a capacitive coupled charging current. The capacitive coupled charging current is coupled to a filter or charge storage second capacitor for producing in the second capacitor a first portion of a second power supply voltage. During a portion of a switching cycle of the output stage, the snubber capacitor is coupled to an inductor to form a resonant circuit. The resonant circuit produces in the second capacitor a second portion of the second power supply voltage for energizing the IC. The second power supply voltage is used for energizing the IC.

2011-01-20

20110013427

UTILITY GRID POWER AVERAGING AND CONDITIONING - As system is disclosed for providing power averaging for the utility grids and more specifically to utilizing a unique EESU unit with the capability to store electrical energy over 24 hour periods each day and provide power averaging to homes, commercial, and industrial sites to reduce the peak power requirements. Charging such power averaging units during the non-peak times and delivering the energy during the peak-demands times provides for more efficient utilization of utility-grid power-generating plants and the already existing power transmission lines. Such a unit may also have the capability of isolating the users from utility-grid power failures, transients, and AC noise.

2011-01-20

20110013428

MODULAR MULTI-PULSE TRANSFORMER RECTIFIER FOR USE IN ASYMMETRIC MULTI-LEVEL POWER CONVERTER - In one embodiment, the present invention includes a system having multiple modular transformers each including a primary winding coupled to an input power source and phase-shifted secondary windings each coupled to a power cell. The system further includes different phase output lines coupled to a load. These lines may include first, second and third phase output lines.

2011-01-20

20110013429

DC SOURCE ASSEMBLIES - Embodiments of DC source assemblies of power inverter systems of the type suitable for deployment in a vehicle having an electrically grounded chassis are provided. An embodiment of a DC source assembly comprises a housing, a DC source disposed within the housing, a first terminal, and a second terminal. The DC source also comprises a first capacitor having a first electrode electrically coupled to the housing, and a second electrode electrically coupled to the first terminal. The DC source assembly further comprises a second capacitor having a first electrode electrically coupled to the housing, and a second electrode electrically coupled to the second terminal.

2011-01-20

20110013430

POWER SUPPLY APPARATUS AND ELECTRONIC DEVICE HAVING THE POWER SUPPLY APPARATUS - A power supply to improve an EMI characteristic and an electronic device having the power supply. The power supply includes a power converter to convert an alternating current (AC) power applied from outside to a direct current (DC) power, a ground portion to supply a ground power to the power converter and a noise attenuator to reduce noise by blocking a harmonic current generated by a driving of the power converter from passing through the ground portion. Accordingly, the stable ground power can be supplied to the internal elements by avoiding the potential change of the ground power and the noise caused by the flow of the harmonic current can be reduced by shortening the harmonic current path. Therefore, the EMI characteristic can be improved.

2011-01-20

20110013431

SWITCHING POWER CONVERSION CIRCUIT AND POWER SYPPLY USING SAME - A switching power conversion circuit receives an input voltage and generates an output voltage to a system circuit. The switching power conversion circuit includes a power circuit, a feedback circuit, a control circuit, and an initiation circuit. The power circuit includes a first switch circuit. The feedback circuit generates a feedback signal according to a power-status signal and the output voltage. The first switching circuit is conducted or shut off according to the feedback signal under control of the control circuit, so that the input voltage is converted into the output voltage and the first auxiliary voltage by the power circuit. If the power-status signal is in an off status, a ratio of the feedback signal to the output voltage is equal to a first feedback ratio and the magnitude of the first auxiliary voltage is lower than a normal operating voltage value, so that the control circuit is disabled.

2011-01-20

20110013432

Systems, Methods, and Apparatus for Operating a Power Converter - Embodiments of the invention can provide systems, methods, and apparatus for operating a power converter. According to one embodiment, a system for operating a power converter can be provided. The system can include a direct current (DC) power source with an output electrically coupled to an input of the power converter. The system can also include a controller operable to modify the performance of the DC power source through the power converter. As part of this modification, the controller can determine whether a low voltage ride (LVRT) event exists in a load and can adjust the DC power source when a LVRT event occurs.

2011-01-20

20110013433

Systems, Methods, and Apparatus for Converting Direct Current (DC) Power to Alternating Current (AC) Power - Embodiments of the invention can provide systems, methods, and apparatus for converting direct current (DC) power to alternating current (AC) power. According to one embodiment, a system for converting DC power to AC power can be provided. The system can include a DC power source that provides a first DC power signal to a converter. Coupled to the converter can be a controller for transforming the first DC power signal into a plurality of AC power signals. The controller can also phase shift at least one of the plurality of AC power signals and combine the phase shifted AC power signal with at least one of the other of the plurality of AC power signals to provide a second DC power signal. The controller can also convert the second DC power signal to an AC power signal.

2011-01-20

20110013434

POWER CONVERTER WITH EXTREMELY LOW STANDBY POWER CONSUMPTION - The present invention relates to a power converter with extremely low standby power consumption. The power converter comprises a rectification module having at least one unilateral switch which has a control terminal, an anode terminal and a cathode terminal. The control terminal is coupled to a control signal, wherein when the control signal issues a first level, the channel between the anode terminal and the cathode terminal is enabled to act as a unilateral switch; and when the control signal issues a second level, the channel between the anode terminal and the cathode terminal is open circuited.

2011-01-20

20110013435

AC DETECTION CIRCUIT FOR POWER SUPPLY - There is provided an alternating current (AC) detection circuit for power supply, the AC circuit including: a rectifying part rectifying an AC voltage; a voltage division part dividing the voltage rectified by the rectifying part according to a preset division ratio; a voltage stabilization circuit part stabilizing the voltage divided by the voltage division part; and a first square wave generating part comparing the voltage stabilized by the voltage stabilization circuit part with an internal reference voltage, and generating a first square wave signal having a duty ratio according to comparison results between the stabilized voltage and the internal reference

2011-01-20

20110013436

BRIDGELESS PFC CIRCUIT SYSTEM HAVING CURRENT SENSING CIRCUIT AND CONTROLLING METHOD THEREOF - The configurations of a bridgeless PFC circuit system and a controlling method thereof are provided. The proposed system includes a bridgeless PFC circuit including a first bridge arm having a first and a second terminals and a first middle point, a second bridge arm having a first and a second terminals and a second middle point, and a bidirectional switch coupled between the first middle point and the second middle point, and an inductor coupled between the first middle point and an AC power source coupled to the second middle point, and a current sensing circuit including a first current transformer sensing a first current flowing through the bidirectional switch, which having a primary side winding coupled to the bidirectional switch and a first and a second secondary side windings, and a switching device coupled to the two secondary side windings.

2011-01-20

20110013437

DC-DC Converter And Its Controlling Method - A unidirectional DC-DC converter and method of control thereof. The converter includes a DC power-supply, a buck converter circuit having a first main switching element, a boost converter circuit having a second main switching element, a first snubber capacitor, a first inversely-parallel diode, a control device, and an output diode.

2011-01-20

20110013438

INVERTER TOPOLOGIES USABLE WITH REACTIVE POWER - The present invention generally relates to power electronic switching circuits and in particular to inverter modules employing two or more controlled switches that can be used with reactive loads. An inverter circuit is provided which comprises first and second input terminals for being connected to a DC power source; first and second output terminals for outputting an AC voltage; at least one metal oxide semiconductor field effect transistor, MOSFET, having a parasitic body diode. The inverter circuit further comprises at least one disabling element for disabling said body diode. This may result in an improved efficiency of the inverter circuit in combination with a reactive power capability. Further, a semiconductor switching device is disclosed, comprising at least one metal oxide semiconductor field effect transistor, MOSFET, and at least one insulated gate bipolar transistor, IGBT, wherein said MOSFET and said IGBT are connected in parallel.

RECTIFIER CIRCUIT - Switches perform switching at a timing when a first phase voltage and a second phase voltage outputted from a three-phase voltage source have a phase difference of 90°. Then, a three-phase/two-phase conversion inductor outputs a pair of AC currents, and a rectification and a single-phase pulse-width modulation are performed on each of AC currents. Modulated currents obtained as a result of the rectification and the single-phase pulse-width modulation are synthesized, to generate an output current, which is supplied to a circuit in which a capacitor and a load are connected in parallel with each other.

2011-01-20

20110013441

STATIC CONVERTER AND METHOD FOR STARTING UP THE CONVERTER - A static converter is disclosed. In at least one embodiment, the static converter includes a power converter circuit which has a plurality of interconnected module branches, wherein each module branch has one or more electrically series-connected two-pole submodules as switchable voltage sources which each include a capacitor as an energy store and power semiconductors as electronic switching elements. A device for precharging the capacitors is included, including at least one power electronics device for providing an adjustable precharge current. The at least one power electronics device, being supplied with power by an auxiliary supply system and being connected to a converter bridge via a precharge transformer, can be used to achieve a sufficiently high voltage level for the capacitors of the submodules when the converter is started up so as to achieve firstly the minimum voltage for supplying power to the power semiconductors and secondly the minimum voltage for synchronization to the systems. A method for starting up such a converter is also disclosed.

2011-01-20

20110013442

USING STORAGE CELLS TO PERFORM COMPUTATION - An in-memory processor includes a memory array which stores data and an activation unit to activate at least two cells in a column of the memory array at generally the same time thereby to generate a Boolean function output of the data of the at least two cells. Another embodiment shows a content addressable memory (CAM) unit without any in-cell comparator circuitry.

2011-01-20

20110013443

Novel high speed two transistor/two bit NOR read only memory - A mask programmable NOR ROM circuit includes serially connected ROM transistors. A drain of a topmost ROM transistor is connected to a bit line and a source of a bottommost ROM transistor is connected to a source line. A source of one ROM transistor is solely connected with a drain of an immediately adjacent ROM transistor. The ROM transistors are programmed by placing a resist mask having openings for selectively modifying a first threshold voltage level of chosen ROM transistors by implanting a threshold voltage modifying impurity. A selected ROM transistor is read by connecting the source line to a sense amplifier circuit and setting the bit line to a read biasing voltage level. The gate of the selected ROM transistor is set to a moderately high read voltage level. The gates of all unselected ROM transistor is set to a very high read voltage level.

2011-01-20

20110013444

LOW LEAKAGE ROM ARCHITECURE - A Read only memory (ROM) with minimum leakage includes a ROM array including a first transistor, wherein a drain, a source, a gate, and a bulk of the first transistor is electrically connected to a logic zero in the idle state for ensuring zero junction and sub-threshold leakage current. The drain of the first transistor is electrically connected to a main bit line through a second transistor. The second transistor includes a gate, electrically connected to a first decoding circuit, a drain, electrically connected to the main bit line. A first reference bit line is electrically connected to a drain of a third transistor, wherein gate of the third transistor is electrically connected to a second decoding circuit for generating a stop read signal. A second reference bit line, electrically connected to the first decoding circuit through a first sensing unit for generating a stop pre-charge signal.

2011-01-20

20110013445

Bias Temperature Instability-Influenced Storage Cell - In a method of using a memory cell employing a field effect transistor (FET), the FET is heated to a first temperature sufficient to support bias temperature instability in the FET. The bit line is driven to a high voltage state. The word line is driven to a predetermined voltage state that causes bias temperature instability in the FET. The temperature, the high voltage state on the bit line and the predetermined voltage state on the word line are maintained for an amount of time sufficient to change a threshold voltage of the FET to a state where a desired data value is stored on the FET. The FET is cooled to a second temperature that is cooler than the first temperature after the amount of time has expired.

2011-01-20

20110013446

REFRESH CIRCUITRY FOR PHASE CHANGE MEMORY - A memory device as described herein includes a reference array of phase change memory cells and a memory array of phase change memory cells, where a difference between a current data set stored in the reference array and an expected data set is used to determine when to refresh the memory array. The high resistance state for the reference array is a “partial reset” state having a minimum resistance less than that of the high resistance state for the memory array. Sense circuitry is adapted to read the memory cells of the reference array and to generate a refresh command signal if there is a difference between a current data set stored in the reference array and an expected data set, and control circuitry responsive to the refresh command signal to perform a refresh operation on the memory cells of the memory array.

2011-01-20

20110013447

SEMICONDUCTOR DEVICE - A phase change memory capable of highly reliable operations is provided. A semiconductor device has a memory array having a structure in which memory cells are stacked including memory layers using a chalcogenide material and diodes, and initialization conditions and write conditions are changed according to the layer in which a selected memory cell is positioned. The initialization conditions and write conditions (herein, reset conditions) are changed according to the operation by selecting a current mirror circuit according to the operation and by a control mechanism of a reset current in a voltage select circuit and the current mirror circuit.

2011-01-20

20110013448

MAGNETIC ELEMENT WITH A FAST SPIN TRANSFER TORQUE WRITING PROCEDURE - A magnetic tunnel junction, comprising a reference layer having a fixed magnetization direction, a first storage layer having a magnetization direction that is adjustable relative to the magnetization direction of the reference layer by passing a write current through said magnetic tunnel junction, and an insulating layer disposed between said reference layer and first storage layer; characterized in that the magnetic tunnel junction further comprises a polarizing device to polarize the spins of the write current oriented perpendicular with the magnetization direction of the reference layer; and wherein said first storage layer has a damping constant above 0.02. A magnetic memory device formed by assembling an array of the magnetic tunnel junction can be fabricated resulting in lower power consumption.

2011-01-20

20110013449

SELF-ALIGNED PATTERNING METHOD BY USING NON-CONFORMAL FILM AND ETCH BACK FOR FLASH MEMORY AND OTHER SEMICONDUCTUR APPLICATIONS - A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal oxide is deposited over the charge trapping layer to form a thick oxide on top of the core source/drain region and a pinch off and a void at the top of the STI trench. An etch is performed on the pinch-off oxide and the thin oxide on the trapping layer on the STI oxide. The trapping layer is then partially etched between the core cells. A dip-off of the oxide on the trapping layer is performed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide and thus isolate the trap layer.

2011-01-20

20110013450

METHOD FOR ADAPTIVE SETTING OF STATE VOLTAGE LEVELS IN NON-VOLATILE MEMORY - A method in which non-volatile memory device is accessed using voltages which are customized to the device, and/or to portions of the device, such as blocks or word lines of non-volatile storage elements. The accessing can include programming, verifying or reading. By customizing the voltages, performance can be optimized, including addressing changes in threshold voltage which are caused by program disturb. In one approach, different sets of storage elements in a memory device are programmed with random test data. A threshold voltage distribution is determined for the different sets of storage elements. A set of voltages is determined based on the threshold voltage distribution, and stored in a non-volatile storage location for subsequent use in accessing the different sets of storage elements. The set of voltages may be determined at the time of manufacture for subsequent use in accessing data by the end user.

2011-01-20

20110013451

NON-VOLATILE MEMORY DEVICE WITH BOTH SINGLE AND MULTIPLE LEVEL CELLS - A non-volatile memory array with both single level cells and multilevel cells. The single level and multilevel cells, in one embodiment, are alternated either along each bit line. An alternate embodiment alternates the single and multilevel cells along both the bit lines and the word lines so that no single level cell is adjacent to another single level cell in either the word line or the bit line directions.

2011-01-20

20110013452

SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a first memory, a second memory and a control circuit. The first memory includes a first bank number. The second memory includes a second bank number larger than the first bank number. The control circuit controls a precharge operation with respect to bit lines provided in the first and second memories. When performing, with respect to the first memory, a synchronous operation that is effected in synchronization with a clock, the control circuit changes over a second precharge operation to an operation time different from a first precharge operation during a period from the end of the initial first precharge operation to the start of the subsequent second precharge operation after receiving an address.

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device comprises: a plurality of first memory strings; a first select transistor having one end thereof connected to one end of the first memory strings; a first line commonly connected to the other end of a plurality of the first select transistors; a switch circuit having one end thereof connected to the first line; and a second line commonly connected to the other end of a plurality of the switch circuits. The switch circuit controls electrical connection between the second line and the first line.

2011-01-20

20110013455

NON-VOLATILE MEMORY SERIAL CORE ARCHITECTURE - A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing wide data buses. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.

2011-01-20

20110013456

SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REDUCING CHIP SIZE - According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.

MEMORY DEVICES SUPPORTING SIMULTANEOUS PROGRAMMING OF MULTIPLE CELLS AND PROGRAMMING METHODS THEREOF - Some embodiments of the present invention provide methods of programming memory devices that include an array of vertical channels passing through a stacked plurality of word plates, wherein respective columns of vertical channels are configured to be coupled to respective bit lines. In some method embodiments, potentials of the vertical channels are boosted, followed by selectively applying respective data to vertical channels via the bit lines to thereby selectively change the potentials of the vertical channels according to the data. A program voltage is subsequently applied to a selected word plate to thereby program a plurality of cells.

2011-01-20

20110013459

METHOD OF PROGRAMMING/ERASING THE NONVOLATILE MEMORY - A method for programming/erasing a nonvolatile memory uses the multi-stage pulses to program/erase the memory so as to reduce the slow program/erase bit issue. The method applies a first predetermined voltage bias to a memory cell for a predetermined number of times. Each time the voltage bias is applied to the memory cell the memory is verified against a criterion. If the verification failed after the predetermined number of times applying the first predetermined voltage bias, a second predetermined voltage bias is applied to program/erase the nonvolatile memory. If the verification failed after applying the second predetermined voltage bias, a third predetermined voltage bias is applied to program/erase the nonvolatile memory.

2011-01-20

20110013460

DYNAMICALLY ADJUSTABLE ERASE AND PROGRAM LEVELS FOR NON-VOLATILE MEMORY - Degradation of non-volatile storage elements is reduced by adaptively adjusting erase-verify levels and program-verify levels. The number of erase pulses, or the highest erase pulse amplitude, needed to complete an erase operation is determined. When the number, or amplitude, reaches a limit, the erase-verify level is increased. As the erase-verify level is increased, the number of required erase pulses decreases since the erase operation can be completed more easily. An accelerating increase in the degradation is thus avoided. One or more program-verify levels can also be increased in concert with changes in the erase-verify level. The one or more program-verify levels can increase by the same increment as the erase-verify level to maintain a constant threshold voltage window between the erased state and a programmed state, or by a different increment. Implementations with binary or multi-level storage elements are provided.

2011-01-20

20110013461

NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE - For data erase from an electrically erasable and programmable non-volatile memory cell, the following operations are performed: an erase operation to apply an erase pulse voltage to a memory cell for data erase, an erase verify operation to verify whether data erase is completed, and a step-up operation to increase the erase pulse voltage by a certain step-up voltage if data erase is not completed. A control unit controls voltages so that at least a first erase pulse voltage initially generated in the erase operation has a longer rise time than that of a second erase pulse voltage generated subsequent to the first erase pulse voltage.

2011-01-20

20110013462

Method for Operating Memory - A memory operating method includes the following steps. First, a memory with a charge storage structure is provided. Next, the memory is biased to a first threshold voltage. Then, the memory is biased to a second threshold voltage. Next, the memory is biased to a third threshold voltage. The first threshold voltage is higher than a first level. The second threshold voltage is lower than a second level. The third threshold voltage is approximating or equal to the second level.

2011-01-20

20110013463

Method of Forming Memory Devices by Performing Halogen Ion Implantation and Diffusion Processes - Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

2011-01-20

20110013464

Semiconductor memory device having hierarchical bit line structure and method of driving the semiconductor memory device - The semiconductor memory device includes a first memory cell array including at least one first memory cell and at least one second memory cell corresponding to the at least one first memory cell, a first low bit line connected to the at least one first memory cell, a first low complementary bit line connected to the at least one second memory cell, a first switch unit having a first terminal connected to the first low bit line, a second switch unit having a first terminal connected to the first low complementary bit line, a first global bit line connected to a second terminal of the first switch unit, a first global complementary bit line connected to a second terminal of the second switch unit, and a plurality of sensing amplifying units connected to the first global bit line and the first global complementary bit line.

2011-01-20

20110013465

INTEGRATORS FOR DELTA-SIGMA MODULATORS - Methods, systems and devices are disclosed. Among the disclosed devices is an electronic device that, in certain embodiments, includes a plurality of memory elements or imaging elements connected to a bit-line and a delta-sigma modulator connected to the bit-line. The delta-sigma modulator may include an integrator having a differential amplifier.

2011-01-20

20110013466

SEMICONDUCTOR APPARATUS AND DATA READING METHOD - A semiconductor device includes multiple memory cells, a first and second digit lines, where either of them is coupled to the memory cell to be read, a sense amplifier having a first and second sense nodes that are respectively connected to the first and second digit lines, a first switch between the first digit line and the first sense node, a second switch between the second digit line and the second sense node, and a control circuit that outputs a first and second control signals for controlling a conducive state of the first and second switches. When an activation of the sense amplifier is started, the control circuit makes the first and second switches conductive and disconnects the first or second switch corresponding to the digit line to which the memory cell to be read is not connected according to a potential difference between the first and second sense nodes.

2011-01-20

20110013467

System and Method for Reading Memory - A novel memory reading circuit includes a bit line for transmitting data bits within the memory, a plurality of storage elements for storing bits of data, and a precharge circuit coupled to the bit line for charging the bit line when the precharge circuit is in a charging state, the precharge circuit being operative to remain in the charging state at time when the storage elements assert the stored bits of data on the bit line. The memory may be a single-ended, static random access memory (“SRAM”). The SRAM circuits of the invention may be incorporated into each of a plurality of individual computers arrayed on a single die.

2011-01-20

20110013468

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING SAME - A memory cell is provided at an intersection of a word line and a bit line. A sense amplifier circuit senses and amplifies a signal on the bit line. Replica circuits include a replica cell configured to retain certain data fixedly. A signal detection circuit detects an output signal that rises up at the latest timing among output signals output from the plurality of replica circuits respectively and outputs a detection signal. A delay circuit delays the detection signal. The sense amplifier circuit is activated based on the delayed signal.

2011-01-20

20110013469

Redundancy circuits and semiconductor memory devices - A redundancy circuit includes at least one fuse set circuit and a fuse control circuit. The at least one fuse set circuit includes a plurality of fuse cells, each of the plurality of fuse cells having a first transistor and a second transistor having same sizes. The first transistor has a first contact resistance and the second transistor has a second contact resistance different from the first contact resistance. Each of the plurality of fuse cells stores a fuse address indicating a defective cell in a repair operation and outputs a repair address corresponding to the stored fuse address. The fuse control circuit, connected to the plurality of fuse cells, controls the plurality of fuse cells in response to a program signal and a precharge signal such that the corresponding fuse address is stored in each of the fuse cells.

2011-01-20

20110013470

Structure and Method for Screening SRAMS - An integrated circuit containing an SRAM that provides a switch to decouple the SRAM wordline voltage from the SRAM array voltage during screening and that also provides different wordline and array voltages during a portion of the SRAM bit screening test. A method for screening SRAM bits in an SRAM array in which the wordline voltage is different than the array voltage during a portion of the screening test.

2011-01-20

20110013471

CURRENT MODE DATA SENSING AND PROPAGATION USING VOLTAGE AMPLIFIER - A method and a circuit for current mode data sensing and propagation by using voltage amplifier are provided. Example embodiments may include providing an output signal from a voltage amplifier in response to the voltage amplifier receiving an input signal. The method may include providing a current output signal from a voltage-to-current converter in response to the voltage-to-current converter receiving the output signal. The output signal may be used to drive a current sense amplifier.

2011-01-20

20110013472

SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device includes a memory array, an address counter, an address detecting circuit and a control circuit. The memory array has a plurality of memory cells arranged at crossing positions of word lines and bit lines. The address counter increments an address including a row address and a column address in synchronism with a clock to sequentially output the incremented addresses. The address detecting circuit detects an address previous to an address including a row address to which the row address is switched at the address output from the address counter to output a detection signal. The control circuit performs a precharging operation to the bit lines connected to the memory cells according to the detection signal output from the address detecting circuit.

2011-01-20

20110013473

METHOD OF MIXING - A method of mixing including providing a flexible container which comprises at least two components, assembling the components from outside the flexible container to form a centrally disposed magnetic driven shaft with at least one impeller, whereby the integrity of the flexible container is maintained, filling the flexible container having the centrally disposed magnetic driven shaft with one or more ingredients of the contents to be mixed; engaging a magnetic element of the centrally disposed magnetic driven shaft with an external magnetic drive element; analyzing the contents of the flexible container using at least one sensor or a sampling line on the flexible container; and draining the contents of the flexible container through a drain port at the bottom of the flexible container.

2011-01-20

20110013474

DISPOSABLE MIXING VESSEL - A disposable mixing vessel comprising a flexible container, a centrally disposed shaft having first and second ends with one or more impellers thereon and a magnetic element associated with a first shaft end, a first flange adapted to rotatably engage the first shaft end and a second flange adapted to rotatably engage the second shaft end.

BLENDER JAR INTERLOCK - A collar assembly for coupling a blade assembly and a removable jar to the base of a motorized blender includes an interlock assembly that prevents coupling of the blade assembly to the blender motor unless the jar is secured to the collar assembly, and prevents removal of the jar from the collar assembly when the collar and blade assembly is coupled to the blender base.

2011-01-20

20110013479

Multi-Dimensional Rotary Mixer - A multi-dimensional rotary mixer includes a stand, a frame mounted to the stand, and a mixing vessel mounted to the frame. The frame is rotatable around a first axis of rotation and the mixing vessel is rotatable around a second axis of rotation, the second axis of rotation being substantially orthogonal to the first axis of rotation. The mixer also includes a first drive motor coupled to the frame to rotate the frame about the first axis of rotation and a second drive motor mounted to the frame and coupled to the mixing vessel to rotate the mixing vessel about the second axis of rotation.

2011-01-20

20110013480

COMMUNICATION DEVICE AND COMMUNICATION METHOD - A communication device includes: an ultrasonic oscillating unit which detects or generates an ultrasonic wave; a communication unit which transmits and receives information using the ultrasonic wave; a storage unit which stores a table to which a communication command to designate communication with the another communication device is allocated in time series, the table being shared by the another communication device; and a control unit which shifts the communication unit to one of a transmitting state, a receiving state, and a standby state that is neither the transmitting nor the receiving state, synchronously with the another communication device on the basis of the communication command in the table.

2011-01-20

20110013481

METHOD AND APPARATUS FOR DETECTING MARINE DEPOSITS - Noise compensation in controlled source electromagnetics (CSEM) comprises measuring time-varying magnetic gradients of the marine environment subjected to CSEM. From the measured magnetic gradients, oceanographic electric and magnetic field noise is determined and used for noise compensation of CSEM measurements of electric and magnetic fields. Selection of magnetic gradient measurement provides improved measurement of oceanographic magnetic noise as other electromagnetic noise sources produce negligible magnetic gradients in the marine environment. Electric field noise is then predicted from the magnetic measurements.

2011-01-20

20110013482

Variable Timing ZENSEIS - Seismic systems and methods are provided to collect variable seismic data, for coordinating source energy and receiver data as well as using both to obtain high resolution seismic data.

2011-01-20

20110013483

System and method for suppression of seismic multiple reflection signals - A method of modeling seismic wave-field data in order to suppress near-surface and sub-surface related multiple reflection signals is provided. The reflection signals include main primary reflection signals, main random noise signals, main multiple reflection signals, residual primary reflection signals, residual random noise signals, and residual multiple reflection signals. Main random noise signals are separated from the reflection signals using a frequency-wavenumber domain method to provide data having suppressed main random noise. Main primary reflection signals are separated from the data having suppressed main random noise using frequency-wavenumber filtering and weighted median filtering to provide data having suppressed main random noise and main primary reflections. Multiple reflection signals are modeled using parabolic path summation on the data having suppressed main random noise and main primary reflections.

2011-01-20

20110013484

Linear and circular downscan imaging sonar - A method for providing a combined linear and circular downscan sonar display may include receiving linear downscan sonar data from a linear downscan transducer, receiving conical downscan sonar data from a circular downscan transducer, and combining the linear downscan sonar data and the conical downscan sonar data to produce combined downscan sonar data. A corresponding computer program product and apparatus are also provided.

2011-01-20

20110013485

Downscan imaging sonar - A downscan imaging sonar utilizes a linear transducer element to provide improved images of the sea floor and other objects in the water column beneath a vessel. A transducer array may include a plurality of transducer elements and each one of the plurality of transducer elements may include a substantially rectangular shape configured to produce a sonar beam having a beamwidth in a direction parallel to longitudinal length of the transducer elements that is significantly less than a beamwidth of the sonar beam in a direction perpendicular to the longitudinal length of the transducer elements. The plurality of transducer elements may be positioned such that longitudinal lengths of at least two of the plurality of transducer elements are parallel to each other. The plurality of transducer elements may also include at least a first linear transducer element, a second linear transducer element and a third linear transducer element. The first linear transducer element may be positioned within the housing to project sonar pulses from a first side of the housing in a direction substantially perpendicular to a centerline of the housing. The second linear transducer element may be positioned within the housing to lie in a plane with the first linear transducer element and project sonar pulses from a second side of the housing that is substantially opposite of the first side. The third linear transducer element may be positioned within the housing to project sonar pulses in a direction substantially perpendicular to the plane.

2011-01-20

20110013486

SCANNER - An ultrasonic scanner has an encoder contacting a drum containing an array. The scanning assembly can be replaced via a snap fit formation. The encoder and drum are resiliently biased and movable relative to the chassis. The array can also be movable relative to the chassis.

2011-01-20

20110013487

APPARATUS, SYSTEMS AND METHODS FOR ENHANCED DETECTION, SYNCHRONIZATION AND ONLINE DOPPLER SCALE ESTIMATION FOR UNDERWATER ACOUSTIC COMMUNICATIONS - Advantageous online and/or real-time OFDM-based underwater acoustic (UWA) apparatus, systems and methods are provided according to the present disclosure. The apparatus, systems and methods employ a receiver with a bank of parallel branches, with each branch having a self-correlator matched to a different waveform scaling factor. A detection is declared when any of the branches leads to a correlation metric larger than a pre-defined threshold. The branch with the largest metric yields a Doppler scale estimate and a coarse synchronization point. The proposed apparatus, systems and methods use one OFDM preamble, thereby avoiding the need to buffer the whole data packet before data demodulation and enabling online and/or real-time operation. Thus, the disclosed apparatus, systems and methods are advantageously applicable to UWA communications.

2011-01-20

20110013488

SUB-BEAM FORMING RECEIVER CIRCUITRY FOR ULTRASOUND SYSTEM - Multi-channel receiver circuitry for a sub-beam forming receiver of an ultrasound system in which digital filtering, down-sampling and successive data storage circuitry impose programmable fine and coarse time delays on received digital data signals.

2011-01-20

20110013489

SYNCHRONIZATION OF SYSTEM TIME IN ELECTRONIC DEVICE - A method and apparatus for synchronizing a system time in an electronic device are provided. The method may include: when the electronic device is executing a boot process, disabling an external time obtaining function of the electronic device for obtaining an external reference time, obtaining an internal clock time from an internal clock unit of the electronic device and synchronizing a system time of the electronic device with the internal clock time; and when the electronic device has completed the boot process, enabling the external time obtaining function to obtain the external reference time.

Timepiece With Wireless Communication Function - A timepiece with a wireless function, including a movement for displaying time; a conductive case that holds the movement; a crystal that is disposed on the face side of the case and covers the face side of the movement; a conductive plate that is electrically conductive, disposed between the movement and the crystal, and reflects radio waves; and an antenna that has a substantially annular, conductive antenna electrode, and is disposed along the outside edge of the conductive plate between the conductive plate and the crystal.

2011-01-20

20110013492

Chronograph timepiece - A chronograph timepiece makes it possible to make sure that it normally operates at the time of an initial starting operation such as system resetting without having to perform a difficult operation or the like. When a system reset signal is input to a system reset terminal and it is detected that initial starting has been effected, a processing unit enables a time hand and a chronograph hand to move after permitting the time hand to perform a predetermined demonstration hand movement when both a start/stop switch and a reset switch have not been simultaneously operated; when these switches have been simultaneously operated, the processing unit enables the time hand and the chronograph hand to move without permitting demonstration hand movement.

2011-01-20

20110013493

Chronograph timepiece - When it is judged that a chronograph second counter and a chronograph minute counter have measured a maximum measurement time, a maximum measurement control unit controls a drive pulse generation circuit so as to drive and stop a motor such that chronograph hand stops at predetermined positions. When, in this state, a restarting operation is performed on a start/stop button, a normal chronograph measurement operation is restarted. At this time, a mechanical structure has been restored to a reset state, so that even at the time of restarting after the measurement of the maximum measurement time, the load at the starting operation is the same as that of the normal operation, thus generating no sense of incongruity.

2011-01-20

20110013494

ELECTRONIC TIMEPIECE - An electronic timepiece includes a limiting circuit that is controlled by the rotation detecting circuit and limits output of a locking pulse PL. The electronic timepiece prevents the display of the incorrect current time due to impact, by executing impact detection when rotation is detected, and prevents errant hand operation in a magnetic field by not outputting a locking pulse PL by prohibiting impact detection when non-rotation is detected. The electronic timepiece controls the limiting circuit using a ranking-down storing circuit and if the electronic timepiece employs multi-stage load correction, executes impact detection when regularly occurring non-rotation is detected. Thereby, errant deviation in the display of the current time due to impact is prevented. The electronic timepiece prohibits the impact detection and causes the locking pulse PL not to be output when non-rotation other than those occurring regularly is detected. Thereby, errant hand operation in a magnetic field is prevented.

Heat-assisted magnetic recording head with laser diode fixed to slider - A heat-assisted magnetic recording head includes a slider, an edge-emitting laser diode fixed to the slider, and an external mirror provided outside the slider. The slider includes a magnetic pole, a waveguide, a near-field light generating element, and a substrate. The substrate has a top surface facing toward the magnetic pole, the near-field light generating element and the waveguide. The slider has a top surface that lies above the top surface of the substrate, at an end of the slider farther from the top surface of the substrate. The laser diode includes: an active layer; an emitting end face that lies at an end in a direction parallel to the plane of the active layer and includes an emission part for emitting laser light; and a bottom surface that lies at an end in a direction perpendicular to the plane of the active layer. The laser diode is arranged so that the bottom surface faces the top surface of the slider. The external mirror reflects the laser light emitted from the emission part toward the waveguide.

2011-01-20

20110013498

OPERATING ELEMENT AND REPRODUCER - An operating element for receiving from an operator an instruction about reading speed and reading order of stored data includes: a rotatable operating disc part (

INFORMATION REPRODUCTION APPARATUS AND INFORMATION REPRODUCTION METHOD - A small size circuit reproducing data with low error rate even when a signal includes a non-linear distortion is desired. In such a circuit, the Viterbi method is performed. In the Viterbi method, branch metrics are calculated based on a difference of a sampled reproduction signal and a predetermined expectation values. Path metrics are calculated from the branch metrics. Paths among the plurality of paths having the calculated path metrics and merging at a same state are compared with one another. Based on the magnitude of the compared path metrics, survivor path is selected. In the circuit, for the path metrics of paths merging at a same state, offset corresponding to a determination result until a merging point is added to the paths for the comparison for determining the survivor path from the plurality of merging paths.

2011-01-20

20110013501

UNIVERSAL MULTIMEDIA DISTRIBUTION, STORAGE, AND PLAYBACK SYSTEMS AND METHODS - Universal multimedia distribution, storage, and playback systems, devices, and methods are disclosed herein. A media distribution kiosk located at a retail establishment provides a user with access to a multitude of different forms of digital multimedia that may be purchased and downloaded onto a portable media transporter device. The portable media transporter device may then be inserted into a media storage and playback device that is capable of transcoding and storing the media on a hard disk drive. Additionally, the media storage and playback device is capable of transcoding, storing, and playing information residing on various other media formats such as DVD (movies, audio, gaming software), CD, and memory cards. Digital rights management (DRM) security measures employed at the kiosk and at the transporter and storage/playback devices ensure the integrity of the media transferred to the user.

2011-01-20

20110013502

OPTICAL PICK-UP AND OPTICAL INFORMATION RECORDING AND REPRODUCING APPARATUS - An optical pick-up which permits the relative position of a diffracting optical element and a photodetector to be adjusted by feedback control with signals which are generated when more than one kind of diffracted light differing in order is received, the diffracted light occurring as the reflected light from the optical disc is divided and diffracted by the diffracting optical element having multiple regions. The photodetector which detects the light beam passing through the central region of the diffracting optical element and generates RF signals is juxtaposed with sub-photodetectors, so that they receive reflected stray light from out-of-focus layers and perform computation to calculate the reflected stray light component which the RF signal detector receives, thereby detecting only the component of signals of the reflected light from a target layer.

2011-01-20

20110013503

OPTICALLY-READABLE DISK WITH COPY PROTECTION DEVICE - An optically-readable disk includes a device that disrupts readability of the disk when the disk is spun at an angular velocity substantially greater than required to play the disk in its intended playing device, or when a defined integral of velocity and time is exceeded. The device may include a fluid container that disperses a data-disruptive fluid. The device may include a membrane or layer that is disrupted when the disk is rotated above a defined angular velocity, or when a defined integral of velocity and time is exceeded. The device may include an electro-optical material that is activated by an electrical signal from a controller in response to an input from a sensor responsive to motion of the disk.

2011-01-20

20110013504

METHOD FOR OPTIMIZED REFERENCE SIGNAL DOWNLINK TRANSMISSION IN A WIRELESS COMMUNICATION SYSTEM - A method and system optimizes the transmission of a downlink reference signal (DLRS) in a wireless communication system that uses orthogonal division multiple access (OFDMA) for the downlink. Each Node-B (base station) is capable of transmitting the DLRS reference symbols in different subframes of the OFDM radio frame and changing both the number and location of the subframes in response to changing network conditions. The network conditions include the number of terminals being served by the Node-B and multiple access interference (MAI) from adjacent Node-Bs.

BASE STATION APPARATUS AND COMMUNICATION CONTROL METHOD - A base station apparatus capable of communicating with a user equipment terminal using a downlink shared channel is disclosed. The base station apparatus includes a user selection unit selecting a user equipment terminal to which radio resources are to be allocated, the selection being based on whether there is a MAC-layer control signal to be transmitted to the user equipment terminal.

2011-01-20

20110013507

Smart Protection Escalation Mechanism Prevention - Techniques are provided for detecting at a controller associated with a physical layer of a network an occurrence of a failure within the physical layer of the network. In response to detecting the failure, the controller sends messages to at least first and second nodes in a transport layer of the network, where the messages are configured to indicate normal operations in the physical layer so as to prevent execution of transport layer protection processes for a period of time.

2011-01-20

20110013508

NON-STOP FORWARDING IN A MULTI-CHASSIS ROUTER - State information is synchronized between a plurality of routing engines in a multi-chassis router according to a synchronization gradient. An example multi-chassis router is described that includes a primary routing engine and a standby routing engine in each chassis. According to the synchronization gradient, the primary routing engine of a control node updates state information on the standby routing engine of the control node prior to updating the primary routing engines of the other chassis. The primary routing engines of the other chassis update state information in respective standby routing engines prior to updating state information in consumers. If a primary routing engine fails, the corresponding standby routing engine assumes control of the primary routing engine's duties. Upon assuming control, a standby routing engine resumes updating state information without having to resend state information or interrupt packet forwarding.

2011-01-20

20110013509

NETWORK NODE AND METHOD FOR ESTABLISHING NETWORK PATH AND SENDING DATA - The disclosure relates to the mesh network technology, and in particular, to a network node and a method for establishing a path and transmitting data. A method for establishing a network path is provided in an embodiment of the present invention. The method includes: receiving a gateway notification forwarded by a node with a trunk path and setting up a routing request timer; sending a routing request that contains information about whether a path is the trunk path after the routing request timer times out; receiving a route reply that is generated by the gateway after receiving the routing request from the gateway through the trunk path. In addition, a network node for implementing the method is provided in an embodiment of the present invention.

2011-01-20

20110013510

SYSTEM AND METHOD FOR PROVIDING A STABLE AND TAMPER PROOF COMMUNICATION BETWEEN A VEHICLE, A VEHICLE RELATED UNIT, AND A REMOTE SYSTEM - Systems and methods for providing a stable communication between a vehicle's on-board connectivity layer include at least one vehicle located communication node and at least one vehicle associatable communication node, and an off-board connectivity layer including at least one remote system located communication node, wherein each communication node communicates with at least one other communication node over a communication connection, and in case the communication connection to the at least one communication node is disturbed or interrupted, a communication connection to another communication node is established.

2011-01-20

20110013511

End-to-end pattern classification based congestion detection using SVM - Because packets dropped due to network congestion cannot reach the intended receiver whereas corrupted packets can still be received, the reception status of multiple packets is different for congested and non-congested paths. This difference reflects a spatial variation in the received data stream that is indicative of congestion. Network congestion detection is described that treats the reception status of sequences of multiple packets as patterns and converts the problem of congestion detection into a two-class pattern classification problem. A Support Vector Machine (SVM) classifier is trained to classify the reception status of sequences of packets as being indicative or not of network congestion. If network congestion is detected, congestion control measures can then be taken. Extensive simulations demonstrate high detection accuracy under different network parameters.

2011-01-20

20110013512

TRANSMISSION CONTROL PROTOCOL (TCP) CONGESTION CONTROL USING TRANSMISSION DELAY COMPONENTS - According to the present disclosure, methods and apparatus are provided to improve the Transmission Control Protocol (TCP) for data such as delay sensitive or bursty data. A maximum send window is adjusted using forward queuing delay and maximum bandwidth parameters. Reverse queuing delay and the number of packets drops are not factored into generation of the maximum send window. Network buffer occupation is bounded and a congestion window is effectively varied using rate shaping and gradual size increases based at least partially on the number acknowledged packets.

2011-01-20

20110013513

Wi-Fi Quality of Service Signaling - The transmission of signaling frames in a QoS system may be prioritized over the transmission of content frames carrying time-sensitive information. The signaling frames and the content frames may belong to a single communication session. Alternatively, the signaling frames may belong to a different communication session than the content frames. The signaling frames and the content frames may be audio frames, video frames or frames of other time-sensitive information.

METHOD FOR ACCELERATING THE ACTIVATION OF A MBMS SERVICE - The invention relates to a method for accelerating the activation of a MBMS service distributed by a service provider to a plurality of user equipments UEs in the form of MBMS data packets, MBMS data packet, comprising each, compressed header information and a payload, characterized by:—creating a specific MBMS service data flow containing only header information,—transmitting said specific MBMS service data flow to the UE separately from said MBMS data packets.

2011-01-20

20110013516

Control of Background Data Transfers - Control of background data transfers is described. In an embodiment, a background data transfer is controlled at a receiver node by measuring a time period taken to receive from a sender node a data sequence of the same size as a receive window. The time period is used to evaluate available network capacity, and the network capacity used to calculate a new window size. The new window size is applied and communicated to the sender node. In another embodiment, a background data transfer is controlled at a receiver node by measuring a quantity of data received from a sender node during a first control interval. The measured quantity is used to evaluate available network capacity, and the network capacity used to calculate a new receive window size and a second control interval duration. The new window size is applied for the second control interval, and communicated to the sender node.

2011-01-20

20110013517

SYSTEM AND METHOD FOR PROVIDING LOWER-LAYER PATH VALIDATION FOR HIGHER-LAYER AUTONOMOUS SYSTEMS - An approach is provided for validating lower layer paths for higher layer networks. A request for path cost information is generated relating to a path traversing a first autonomous system and a second autonomous system, wherein each of the autonomous systems utilizes different cost metrics. The path cost information is received associated with reservation of capacity for the path. The path cost information is evaluated. The reservation is selectively accepted based on the evaluation.