37 Nonoverlapping ClocksNonoverlapping clocks can prevent racesAs long as nonoverlap exceeds clock skewWe will use them in this class for safe designIndustry manages skew more carefully instead1: Circuits & Layout

38 Gate Layout Layout can be very time consumingDesign gates to fit together nicelyBuild a library of standard cellsStandard cell design methodologyVDD and GND should abut (standard height)Adjacent gates should satisfy design rulesnMOS at bottom and pMOS at topAll gates include well and substrate contacts1: Circuits & Layout