The "microYASEP" is a compatible subset of the usual YASEP but with many
limitations, like only 23 instructions (not yet all implemented), 2 cycles per
instruction (no pipeline), not even data memory access... It is designed for
tiny FPGAs and the core source code takes about 350 lines in VHDL. Data widths
are 16 bits but could potentially be even smaller if needed (I'll have to
check). I think it will run around 12 MIPS for the first system that will use
it, it could be faster but this is useless.

This would not be possible without all the software tools I have written in
the last months and years ! I can now assemble and export in hexadecimal or
VHDL, create new custom configuration files with a few clicks, or tweak details
at will. I have created a new system of "CPU profiles" that goes beyond the
basic YASEP16/YASEP32 distinction.

The microYASEP is just one of the several possible microarchitectures
possible with the YASEP. Later configurations will be faster, larger and with
more features like the multiplier, shifter and memory interfaces... But with
one first application and a running, basic core, the whole YASEP design can
tune its details with more real-life feedback !