Liquid Pro does carry some risks, but if you have already performed the riskiest part, which is the IHS removal, applying a little conductive TIM underneath the IHS doesn't sound so risky. I don't see any exposed traces or capacitors underneath the IHS. The bonding of Liquid Pro is a serious drawback when you are applying it on top of the IHS between the IHS and the heatsink, since you might need to detach the heatsink occasionally to perform maintanence on it. But it is not like you need to take off the IHS for maintenance, below the IHS actually sounds like the ideal use for Liquid Pro.

Anyways, hats off for having the guts to delid your Ivy Bridge. I am still not sure if I want to delid mine after reading all the failed attempts on the various forums. My temps aren't that bad even in a non air conditioned room at 4.5Ghz in the summer, and deliding it might make it harder to resell if in the future.

graysky wrote:

@Tzupy - No need to apologize for linking. You can add 'forms tight bonds between surfaces' to your list of why LP is a bad idea.

When finished cleaning up both pieces, apply TIM to the die, place it back in the MB, and gently place the IHS on it. Lock it into place in the MB with the mounting bracket that will hold the IHS to the chip securely thus keeping you from having to glue down the IHS.

IMO if this de-lidding practice becomes popular, Intel has 2 choices:1. Use a quality TIM instead, and also a thinner layer of it. This would make many knowledgeable customers happy.2. Make the de-lidding more difficult, in order to discourage the practice. IMO this second option is more likely to happen.

Latest info on delidding Ivy is that the TIM Intel used isn't that bad as many thought, including myself.It's just that it's too thick, for reasons still unknown. I apologize to Intel for calling them scrooges (on the TIM).This leaves open the possibility of an Ivy revision that minimizes the thickness of the TIM and gets better temps.

Yes it is possible to get rid of the IHS but only if you use watercooling, the waterblock shouldn't break the bare die, while a 1kg heatsink would probably break it.Link to forum post with plenty of tests at Anandtech: http://forums.anandtech.com/showthread. ... &t=2285595

I have couple of ideas. Intel using sub-par greese due to cost reasons does not seem very likely, as others have explained. Instead:

1) Tolerances and gap between IHS and the die. The reason CPUs nowadays have IHS in the first place is to protect the CPU die; under no circumances may the IHS press so tightly against the die the die breaks. Because we're talking about small fractions of millimeters here, it's very hard to mass manufacture metallic parts that would be just the right size in every case; this means Intel has to leave a bit larger than ideal gap to avoid having to replace CPUs due to die breaking even when the IHS assembly gets closer to the die than on average.

When you replaced the thermal grease, you also removed a very thin layer of the rubber between IHS and the PCB - this fraction might mean your IHS is now closer to the die and thus more vulnerable to breaking if worst comes to worst, but also reducing the thermal resistance between IHS and the die.

Here's my results on delidding 3770K and putting Liquid Pro between the IHS and the die Before 4.3Ghz 1.155v*After 4.3Ghz 1.155v* (didn't touch any settings in between)After 4.5Ghz 1.186v* **

So before I got average temperature of 75*C across all cores. After 59.25*C. So that makes an average drop of 15.75*C across all cores while hottest core dropping an interesting 17*C.TIM between IHS and CPU cooler is MX-2. CPU cooler is Thermalright True Spirit which has a single Gentle Typhoon 1850rpm on push configuration. Case is as it's mentioned in my signature and same for the fans. The fans were running at 100% during the tests and the ambient temperature hovered around 23-24*C

*voltages checked with multimeter from the voltage measuring points on the Gene-Z motherboard.**Handbrake x264 encoding seems to require a tad more voltage. At 1.190v set I was getting WHEA errors and encoding stopping. At 1.195v the same and at 1.200v it just shows occasionally a WHEA error. I now stopped the encode and I'll drop it back down to 1.190v (1.186v according to my multimeter under load) and up my memory voltage because that was what I lowered after taking that screenshot. Although I did run memtest with 7.3gb load for 200% coverage and it didn't find anything. Hmm.. I'll try upping the ram voltage by 0.05v and lower the cpu voltage back down couple of notches to see what happens during Handbrake encoding..

Although you might expect to see some improvement, 16C is surprising. Are you sure that this is like for like? It's just interesting to note that the motherboard CPU temperature only changes by 10C and what might cause this. While I don't doubt that there is some improvement, unless you can say that everything else is the same it is hard to see it being that much. To really prove this you would need to undo what you have done and show that it gets worse by the same amount. This is of course unless you had a sample with a poorly stuck down IHS.

I'm surprised that no one seems to be lapping the bottom of the heat spreader to set the die to ihs gap to 0.000".

You just need a depth mic and some patience.

I haven't seen custom heat spreaders either, I think there might be some gains to be had by making one the maximum size that will fit through the retention clamp to give a larger contact patch for a heat sink like a Xigmatek S1284 with 4 direct contact heat pipes.

Those doubting my results go read OCN's delidding club. Lots of folks there with even better results.And you might want to check Idontcare's thread over at Anandtech forums. He has documented this delidding stuff really well and why we get such a good results. (which is the IHS distance from the die mostly)

E: Oh and edh.. The "motherboard cpu temperature" is the same temperature "sensor" that real temp accesses. A fact that you can clearly see how inaccurate AISuiteII is for monitoring temperatures.It actually just freezes when you load the CPU heavily. And I took those screenshots under load so Realtemp was showing the temperature WHEN I took the screenshot but AISuiteII was showing the temperature what it was BEFORE IBT began it's stress round.Also the tim application before delid was the same as after, I always use a certain amount and I apply it in a certain way.

We still don't know why Intel opted to go this route...I don't think is was to save a few pennies. My guess: is that it's something to do with the 22nm process node. Maybe the difference in coefficient of thermal expansion between the silicon in this process and the solder used was too high...maybe there were stress/fracture/reliability issues...maybe that's why they opted to go with TIM. <shrug>

We still don't know why Intel opted to go this route...I don't think is was to save a few pennies. My guess: is that it's something to do with the 22nm process node. Maybe the difference in coefficient of thermal expansion between the silicon in this process and the solder used was too high...maybe there were stress/fracture/reliability issues...maybe that's why they opted to go with TIM. <shrug>

Stay tuned and see what happens at 14nm

Yeah, could be. And maybe because the heat output is getting lower, they are thinking solder isn't needed anymore anyway. Would be nice of Intel to at least explain themselves though.

TIM _and_ seemingly a bit of excessive spacing as well. Perhaps the assembly line started breaking the 22nm fabbed chips in early tests. It couldn't simply be a case of "oh what the hell we're well on top again so why bother"?

We still don't know why Intel opted to go this route...I don't think is was to save a few pennies. My guess: is that it's something to do with the 22nm process node. Maybe the difference in coefficient of thermal expansion between the silicon in this process and the solder used was too high...maybe there were stress/fracture/reliability issues...maybe that's why they opted to go with TIM. <shrug>

Stay tuned and see what happens at 14nm

Spot on with the "Maybe the difference in coefficient of thermal expansion between the silicon in this process and the solder used was too high" In fact Intel commissioned a study on it some time ago, If like me your interested this makes very interesting reading (PDF warning)The Material Optimization and Reliability Characterization of an Indium-Solder Thermal Interface Material for CPU Packaging(warning PDF)To cut a long story short when using solder on larger die size there is some cracking at the corners, with the die shrink it became impossible to prevent this cracking from migrating towards the center of the die.

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