#1: FIFO write ready bit in INT status register is stuck to 1. It is stuck forever as soon as fifo is used for writing even once. Therefore if interrupt is shared (and here it is), its easy to 'service' the device while it doesn't need any service

#2: Its not possible to stuff the FIFO before TPC transfer. One really have to wait for write ready interrupt, even though thewrite ready status is stuck.

#3: TPCs with non 4 aligned length woes: Facts:

* non 4 aligned DMA write hangs the system hard, maybe on bus level.

* PIO read succedes but controller truncates the data stored in theFIFO to closest 4 byte boundary. That is if you read 26 bytes, it will save 24 bytes in the FIFO

* TPC_P0, TPC_P1 not aligned transfters work just fine despite astatement in the datasheet (only mention of this problem)

#4: As soon as write PIO is used, then later write DMA fails. Facts:

* This is triggered only by PIO write of registers (only happens in ms_block.c when it writes param + oob. Thats whymspro_blk isn't affected) Doing short DMA writes is a nice workaround.