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The Xilinx documentation for Zynq SoC does not cover certain aspects because it is already defined by ARM. To confirm the values of the DDR section values in translation_table.s, it is necessary to reference both ARM and Xilinx documentation.

In this case, the ARM document that needs to be referenced is the ARM Architecture Reference Manual (AARM). It can be found on ARM's website. First time users will need to register to log in.

Once AARM is opened, look back at the DDR table entry. An uncommon element that would make for a narrow search is "TEX." One of the first hits for "TEX" in the AARM is a table describing the descriptor formats for a page table section. Below this table are descriptions of each descriptor and reference pages for more information. From here, it is easy to follow the documentation references to determine the values of each descriptor and what they correspond to.

Staying with "TEX" as the example, more information concerning it can be found in the Memory Region Attributes Section. This section provides an encoding table for the "TEX", "C", and "B" descriptors. A value of 0x15de6 corresponds to S=b1 TEX=b101 AP=b11, Domain=b1111, C=b0, B=b1 per the initial table. The encoding table allows users to cross reference the values of descriptors to their corresponding parameter.

Table 3-1 provides an explanation for Cache Controller Behavior during SCU Requests. Find the attributes above in the ARMv7 Equivalent column of this table. A Zynq transaction equivalent of Outer write-back, write-allocate is Cacheable write-back, allocate on read and write.

Therefore, a value of 0x15de6 in the DDR section of the BSP page table corresponds to a transaction of cacheable write-back, allocating on read and write.