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Abstract:

Embodiments of the present invention provide an adaptive cache system and
an adaptive cache system for a hybrid storage system. Specifically, in a
typical embodiment, an input/out (I/O) traffic analysis component is
provided for monitoring data traffic and providing a traffic analysis
based thereon. An adaptive cache algorithm component is coupled to the
I/O traffic analysis component for applying a set of algorithms to
determine a storage schema for handling the data traffic. Further, an
adaptive cache policy component is coupled to the adaptive cache
algorithm component. The adaptive cache policy component applies a set of
caching policies and makes storage determinations based on the traffic
analysis and the storage schema. Based on the storage determinations,
data traffic can be stored (e.g., cached) among a set of storage devices
coupled to the adaptive cache policy component. Such storage components
can include one or more of the following: a low-high cache, a
low-mid-high cache, a low speed storage component, a middle speed storage
component and/or a high speed storage component.

Claims:

1. An adaptive cache system, comprising: an input/out (I/O) traffic
analysis component for monitoring data traffic and providing a traffic
analysis based thereon; an adaptive cache algorithm component coupled to
the I/O traffic analysis component for applying a set of algorithms to
determine a storage schema for handling the data traffic; an adaptive
cache policy component coupled to the adaptive cache algorithm component
for applying a set of caching policies and making storage determinations
based on the traffic analysis and the storage schema; and a set of
storage devices coupled to the adaptive cache policy component for
storing the data traffic based on the storage determinations.

2. The adaptive cache system of claim 1, the set of storage devices
comprising a low-high cache coupled to the adaptive cache policy
component.

3. The adaptive cache system of claim 2, the set of storage devices
further comprising a low speed storage component coupled to the low-high
cache.

4. The adaptive cache system of claim 3, the low speed storage component
comprising at least one of the following: a high density drive or flash
memory.

5. The adaptive cache system of claim 3, the set of storage devices
further comprising a high speed storage component coupled to the low-high
cache.

6. The adaptive cache system of claim 5, the high speed storage component
comprising at least one of the following: dynamic random access memory,
or a semiconductor storage device.

7. The adaptive cache system of claim 1, further comprising a cache
manager for managing the adaptive cache system.

8. An adaptive cache system for a hybrid storage system, comprising: an
input/out (I/O) traffic analysis component for monitoring data traffic
and providing a traffic analysis based thereon; an adaptive cache
algorithm component coupled to the I/O traffic analysis component for
applying a set of algorithms to determine a storage schema for handling
the data traffic; an adaptive cache policy component coupled to the
adaptive cache algorithm component for applying a set of caching policies
and making storage determinations based on the traffic analysis and the
storage schema; and a low-mid-high cache coupled to the adaptive cache
policy component for storing the data traffic based on the storage
determinations.

9. The adaptive cache system of claim 8, further comprising a low speed
storage component coupled to the low-mid-high cache.

10. The adaptive cache system of claim 9, the low speed storage component
comprising at least one of the following: a high density drive, or flash
memory.

11. The adaptive cache system of claim 9, further comprising a high speed
storage component coupled to the low-high cache.

12. The adaptive cache system of claim 11, the high speed storage
component comprising at least one of the following: dynamic random access
memory, or a semiconductor storage device.

13. The adaptive cache system of claim 11, further comprising a middle
speed storage component coupled to the low-mid-high cache.

15. The adaptive cache system of claim 8, further comprising a cache
manager for managing the adaptive cache system.

16. A method for producing an adaptive cache system, comprising:
providing an input/out (I/O) traffic analysis component for monitoring
data traffic and providing a traffic analysis based thereon; coupling an
adaptive cache algorithm component to the I/O traffic analysis component
for applying a set of algorithms to determine a storage schema for
handling the data traffic; coupling an adaptive cache policy component to
the adaptive cache algorithm component for applying a set of caching
policies and making storage determinations based on the traffic analysis
and the storage schema; and coupling a set of storage devices to the
adaptive cache policy component for storing the data traffic based on the
storage determinations.

17. The adaptive cache system of claim 16, the set of storage devices
comprising: a cache coupled to the adaptive cache policy component; a low
speed storage component coupled to the cache; and a high speed storage
component coupled to the cache.

18. The adaptive cache system of 17, further comprising coupling a middle
speed storage component to the cache.

19. The adaptive cache system of claim 17, the cache comprising a
low-high cache.

20. The adaptive cache system of claim 17, the cache comprising a
low-mid-high cache.

Description:

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is related in some aspects to commonly-owned,
co-pending application Ser. No. 12/758,937, entitled "SEMICONDUCTOR
STORAGE DEVICE", filed on Apr. 13, 2010, the entire contents of which are
herein incorporated by reference. This application is also related in
some aspects to commonly-owned, co-pending application Ser. No.
12/816,508 entitled SEMICONDUCTOR STORAGE DEVICE BASED CACHE MANAGER",
filed on Jun. 16, 2010, the entire contents of which are herein
incorporated by reference.

FIELD OF THE INVENTION

[0002] The present invention relates to a semiconductor storage device
(SSD) of a PCI-Express (PCI-e) type. Specifically, the present invention
relates to an SSD-based cache system.

BACKGROUND OF THE INVENTION

[0003] As the need for more computer storage grows, more efficient
solutions are being sought. As is known, there are various hard disk
solutions that store/read data in a mechanical manner as a data storage
medium. Unfortunately, data processing speed associated with hard disks
is often slow. Moreover, existing solutions still use interfaces that
cannot catch up with the data processing speed of memory disks having
high speed data input/output performance as an interface between the data
storage medium and the host. Therefore, there is a problem in the
existing area in that the performance of the memory disk cannot be
property utilized.

SUMMARY OF THE INVENTION

[0004] Embodiments of the present invention provide an adaptive cache
system and an adaptive cache system for a hybrid storage system.
Specifically, in a typical embodiment, an input/out (I/O) traffic
analysis component is provided for monitoring data traffic and providing
a traffic analysis based thereon. An adaptive cache algorithm component
is coupled to the I/O traffic analysis component for applying a set of
algorithms to determine a storage schema for handling the data traffic.
Further, an adaptive cache policy component is coupled to the adaptive
cache algorithm component. The adaptive cache policy component applies a
set of caching policies and makes storage determinations based on the
traffic analysis and the storage schema. Based on the storage
determinations, data traffic can be stored (e.g., cached) among a set of
storage devices coupled to the adaptive cache policy component. Such
storage components can include one or more of the following: a low-high
cache, a low-mid-high cache, a low speed storage component, a middle
speed storage component and/or a high speed storage component.

[0005] A first aspect of the present invention provides an adaptive cache
system, comprising: an input/out (I/O) traffic analysis component for
monitoring data traffic and providing a traffic analysis based thereon;
an adaptive cache algorithm component coupled to the I/O traffic analysis
component for applying a set of algorithms to determine a storage schema
for handling the data traffic; an adaptive cache policy component coupled
to the adaptive cache algorithm component for applying a set of caching
policies and making storage determinations based on the traffic analysis
and the storage schema; and a set of storage devices coupled to the
adaptive cache policy component for storing the data traffic based the
storage determinations.

[0006] A second aspect of the present invention provides an adaptive cache
system for a hybrid storage system, comprising: an input/out (I/O)
traffic analysis component for monitoring data traffic and providing a
traffic analysis based thereon; an adaptive cache algorithm component
coupled to the I/O traffic analysis component for applying a set of
algorithms to determine a storage schema for handling the data traffic;
an adaptive cache policy component coupled to the adaptive cache
algorithm component for applying a set of caching policies and making
storage determinations based on the traffic analysis and the storage
schema; and a low-mid-high cache coupled to the adaptive cache policy
component for storing the data traffic based on the storage
determinations.

[0007] A third aspect of the present invention provides a method for
producing an adaptive cache system, comprising: providing an input/out
(I/O) traffic analysis component for monitoring data traffic and
providing a traffic analysis based thereon; coupling an adaptive cache
algorithm component to the I/O traffic analysis component for applying a
set of algorithms to determine a storage schema for handling the data
traffic; coupling an adaptive cache policy component to the adaptive
cache algorithm component for applying a set of caching policies and
making storage determinations based on the traffic analysis and the
storage schema; and coupling a set of storage devices to the adaptive
cache policy component for storing the data traffic based on the storage
determinations.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] These and other features of this invention will be more readily
understood from the following detailed description of the various aspects
of the invention taken in conjunction with the accompanying drawings in
which:

[0009] FIG. 1 is a diagram illustrating a configuration of a storage
device of a PCI-Express (PCI-e) type according to an embodiment of the
present invention.

[0010] FIG. 2 is a diagram of the high speed SSD of FIG. 1 according to an
embodiment of the present invention.

[0011]FIG. 3 is a diagram illustrating a configuration of a controller
unit in FIG. 1 according to an embodiment of the present invention.

[0012]FIG. 4 is a diagram of a cache manager according an embodiment of
the present invention.

[0013] FIG. 5 is a diagram of an adaptive cache system according to an
embodiment of the present invention.

[0014] FIG. 6 is a diagram an adaptive cache system for a hybrid storage
system according to an embodiment of the present invention.

[0015] The drawings are not necessarily to scale. The drawings are merely
schematic representations, not intended to portray specific parameters of
the invention. The drawings are intended to depict only typical
embodiments of the invention, and therefore should not be considered as
limiting the scope of the invention. In the drawings, like numbering
represents like elements.

DETAILED DESCRIPTION OF THE INVENTION

[0016] Exemplary embodiments will now be described more fully herein with
reference to the accompanying drawings, in which exemplary embodiments
are shown. This disclosure may, however, be embodied in many different
forms and should not be construed as limited to the exemplary embodiments
set forth therein. Rather, these exemplary embodiments are provided so
that this disclosure will be thorough and complete and will fully convey
the scope of this disclosure to those skilled in the art. In the
description, details of well-known features and techniques may be omitted
to avoid unnecessarily obscuring the presented embodiments.

[0017] The terminology used herein is for the purpose of describing
particular embodiments only and is not intended to be limited to this
disclosure. As used herein, the singular forms "a", "an", and "the" are
intended to include the plural forms as well, unless the context clearly
indicates otherwise. Furthermore, the use of the terms "a", "an", etc.,
do not denote a limitation of quantity, but rather denote the presence of
at least one of the referenced items. It will be further understood that
the terms "comprises" and/or "comprising", or "includes" and/or
"including", when used in this specification, specify the presence of
stated features, regions, integers, steps, operations, elements, and/or
components, but do not preclude the presence or addition of one or more
other features, regions, integers, steps, operations, elements,
components, and/or groups thereof. Moreover, as used herein, the term
RAID means redundant array of independent disks (originally redundant
array of inexpensive disks). In general, RAID technology is a way of
storing the same data in different places (thus, redundantly) on multiple
hard disks. By placing data on multiple disks, I/O (input/output)
operations can overlap in a balanced way, improving performance. Since
multiple disks increase the mean time between failures (MTBF), storing
data redundantly also increases fault tolerance.

[0018] Unless otherwise defined, all terms (including technical and
scientific terms) used herein have the same meaning as commonly
understood by one of ordinary skill in the art. It will be further
understood that terms such as those defined in commonly used dictionaries
should be interpreted as having a meaning that is consistent with their
meaning in the context of the relevant art and the present disclosure,
and will not be interpreted in an idealized or overly formal sense unless
expressly so defined herein.

[0019] Hereinafter, a storage device of a PCI-Express (PCI-e) type
according to an embodiment will be described in detail with reference to
the accompanying drawings.

[0020] Embodiments of the present invention provide an adaptive cache
system and an adaptive cache system for a hybrid storage system.
Specifically, in a typical embodiment, an input/out (I/O) traffic
analysis component is provided for monitoring data traffic and providing
a traffic analysis based thereon. An adaptive cache algorithm component
is coupled to the I/O traffic analysis component for applying a set of
algorithms to determine a storage schema for handling the data traffic.
Further, an adaptive cache policy component is coupled to the adaptive
cache algorithm component. The adaptive cache policy component applies a
set of caching policies and makes storage determinations based on the
traffic analysis and the storage schema. Based on the storage
determinations, data traffic can be stored (e.g., cached) among a set of
storage devices coupled to the adaptive cache policy component. Such
storage components can include one or more of the following: a low-high
cache, a low-mid-high cache, a low speed storage component, a middle
speed storage component and/or a high speed storage component.

[0021] The storage device of a PCI-Express (PCI-e) type supports a low
speed data processing speed for a host by adjusting synchronization of a
data signal transmitted/received between the host and a memory disk
during data communications between the host and the memory disk through a
periphery interface such as a PCI-Express interface, and simultaneously
supports a high speed data processing speed for the memory disk, thereby
supporting the performance of the memory to enable high speed data
processing in an existing interface environment at the maximum. It is
understood in advance that although PCI-Express technology will be
utilized in a typical embodiment, other alternatives are possible. For
example, the present invention could utilize Serial Attached Small
Computer System Interface (SAS)/Serial Advanced Technology Advancement
(SATA) technology in which a SAS/SATA type storage device is provided
that utilizes a SAS/SATA interface

[0022] Referring now to FIG. 1, a diagram schematically illustrating a
configuration of a PCI-Express type, RAID controlled semiconductor
storage device (e.g., for providing storage for a serially attached
computer device) according to an embodiment of the invention is shown. As
depicted, FIG. 1 shows a RAID controlled PCI-Express type storage device
110 according to an embodiment of the invention which includes a SSD
memory disk unit 100 (referred to herein as SSD memory disk unit, SSD,
and/or SSD memory disk unit) comprising: a plurality of memory disks
having a plurality of volatile semiconductor memories/memory units (also
referred to herein as high speed SSD memory disk units 100); a RAID
controller 800 coupled to SSD memory disk units 100; an interface unit
200 (e.g., PCI-Express host) which interfaces between the SSD memory disk
unit and a host; a controller unit 300; an auxiliary power source unit
400 that is charged to maintain a predetermined power using the power
transferred from the host through the PCI-Express host interface unit; a
power source control unit 500 that supplies the power transferred from
the host through the PCI-Express host interface unit to the controller
unit 300, the SSD memory disk units 100, the backup storage unit, and the
backup control unit which, when the power transferred from the host
through the PCI-Express host interface unit is blocked or an error occurs
in the power transferred from the host, receives power from the auxiliary
power source unit and supplies the power to the SSD memory disk unit
through the controller unit; a backup storage unit 600A-B that stores
data of the SSD memory disk unit; and a backup control unit 700 that
backs up data stored in the SSD memory disk unit in the backup storage
unit, according to an instruction from the host or when an error occurs
in the power transmitted from the host; and a redundant array of
independent disks (RAID) controller 800 coupled to SSD memory disk unit
100, controller 300, and internal backup controller 700.

[0023] The SSD memory disk unit 100 includes a plurality of memory disks
provided with a plurality of volatile semiconductor memories for high
speed data input/output (for example, DDR, DDR2, DDR3, SDRAM, and the
like), and inputs and outputs data according to the control of the
controller 300. The SSD memory disk unit 100 may have a configuration in
which the memory disks are arrayed in parallel.

[0024] The PCI-Express host interface unit 200 interfaces between a host
and the SSD memory disk unit 100. The host may be a computer system or
the like, which is provided with a PCI-Express interface and a power
source supply device.

[0040] Referring now to FIG. 2, a diagram schematically illustrating a
configuration of the high speed SSD 100 is shown. As depicted, SSD memory
disk unit 100 comprises: a host interface 202 (e.g., PCI-Express host)
(which can be interface 200 of FIG. 1, or a separate interface as shown);
a Direct Memory Access (DMA) controller 302 interfacing with a backup
control module 700; an ECC controller 304; and a memory controller 306
for controlling one or more blocks 604 of memory 602 that are used as
high speed storage. Also shown are backup controller 700 coupled to DMA
controller and backup storage unit 600A coupled to backup controller 700.

[0041] In general, DMA is a feature of modern computers and
microprocessors that allows certain hardware subsystems within the
computer to access system memory for reading and/or writing independently
of the central processing unit. Many hardware systems use DMA including
disk drive controllers, graphics cards, network cards, and sound cards.
DMA is also used for intra-chip data transfer in multi-core processors,
especially in multiprocessor system-on-chips, where its processing
element is equipped with a local memory (often called scratchpad memory)
and DMA is used for transferring data between the local memory and the
main memory. Computers that have DMA channels can transfer data to and
from devices with much less CPU overhead than computers without a DMA
channel. Similarly, a processing element inside a multi-core processor
can transfer data to and from its local memory without occupying its
processor time and allowing computation and data transfer concurrency.

[0042] Without DMA, using programmed input/output (PIO) mode for
communication with peripheral devices, or load/store instructions in the
case of multi-core chips, the CPU is typically fully occupied for the
entire duration of the read or write operation, and is thus unavailable
to perform other work. With DMA, the CPU would initiate the transfer, do
other operations while the transfer is in progress, and receive an
interrupt from the DMA controller once the operation has been done. This
is especially useful in real-time computing applications where not
stalling behind concurrent operations is critical.

[0043] Referring now to FIG. 3, the controller unit 300 of FIG. 1 is shown
as comprising: a memory control module 310 which controls data
input/output of the SSD memory disk unit 100; a DMA control module 320
which controls the memory control module 310 to store the data in the SSD
memory disk unit 100, or reads data from the SSD memory disk unit 100 to
provide the data to the host, according to an instruction from the host
received through the PCI-Express host interface unit 200; a buffer 330
which buffers data according to the control of the DMA control module
320; a synchronization control module 340 which, when receiving a data
signal corresponding to the data read from the SSD memory disk unit 100
by the control of the DMA control module 320 through the DMA control
module 320 and the memory control module 310, adjusts synchronization of
a data signal so as to have a communication speed corresponding to a
PCI-Express communications protocol to transmit the synchronized data
signal to the PCI-Express host interface unit 200, and when receiving a
data signal from the host through the PCI-Express host interface unit
200, adjusts synchronization of the data signal so as to have a
transmission speed corresponding to a communications protocol (for
example, PCI, PCI-x, or PCI-e, and the like) used by the SSD memory disk
unit 100 to transmit the synchronized data signal to the SSD memory disk
unit 100 through the DMA control module 320 and the memory control module
310; and a high speed interface module 350 which processes the data
transmitted/received between the synchronization control module 340 and
the DMA control module 320 at high speed. Here, the high speed interface
module 350 includes a buffer having a double buffer structure and a
buffer having a circular queue structure, and processes the data
transmitted/received between the synchronization control module 340 and
the DMA control module 320 without loss at high speed by buffering the
data and adjusting data clocks.

[0044] Referring now to FIG. 4, a SSD based cache manager 308 according to
the present invention is shown. As shown, a cache balancer 360 is coupled
to a set of cache meta data units 362. A set of cache algorithms 364
utilizes the set of cache meta data units to determine optimal data
caching operations. A cache adaptation manger 366 is coupled to and sends
volume information to the cache balancer 360. Typically, this information
is computed using the set of cache algorithms. A monitoring manager 368
is coupled to the cache adaptation manager 366. Also shown is a
reliability manager 369 that receives the cache meta data units 362.

[0045] In a typical embodiment, the following functions are performed:
[0046] Cache balancer 360 balances a load across the SSD based cache
manager 308; [0047] Cache adaptation manager 366 sends volume information
to the cache balancer 360; [0048] Monitoring manager 368 collects data
patterns and sends the data patterns to the cache balancer 360; [0049]
SSD cache manager 308 is usable being used as a buffer cache. [0050] Set
of algorithms 364 enables autonomic reconfiguration of the SSD based
cache manager. [0051] Set of cache algorithms 364 are configured to run
independently.

[0052] Referring to FIG. 5, an adaptive cache system (e.g., as managed by
and/or implemented in conjunction with cache manager 308 of FIG. 4)
according to an embodiment of the present invention is shown. As shown,
the system comprises a low-high speed cache component 426 coupled to a
low speed storage component 428 (e.g., high density drive (HDD), flash
memory, etc.) and a high speed storage component 430 (e.g., dynamic
random access memory (DRAM), semiconductor storage device (SSD), etc.).
As further shown, the system comprises: an input/out (I/O) traffic
analysis component 420 for analyzing/monitoring data traffic being
received, and an adaptive cache algorithm component 422 for applying a
set of algorithms to determine the manner and location (i.e., a schema)
in which data received should be cached. In general, the set of
algorithms will be applied using analysis results from I/O traffic
analysis component. Still yet, an adaptive cache policy component 424 can
be provided for applying caching policies and making storage
determinations based on the traffic analysis and/or results of cache
algorithm computation(s). Once algorithm(s) and policies have been
applied, data can be communicated to low-high cache component 426 for
caching and/or storage in low speed storage component 428 and/or high
speed storage component 430.

[0053] Referring to FIG. 6, an adaptive cache system for a hybrid storage
system (e.g., as managed by and/or implemented in conjunction with cache
manager 308 of FIG. 4) according to an embodiment of the present
invention is shown. As shown, the system comprises a low-medium
(mid)-high speed cache component 432 coupled to a low speed storage
component 428 (e.g., high density drive (HDD), flash memory, etc.), a
high speed storage component 430 (e.g., dynamic random access memory
(DRAM), semiconductor storage device (SSD), etc.), and a middle speed
storage component 434 (e.g., parameter random access memory (PRAM),
ferroelectric random access memory (FRAM), magnetoresistive random access
memory (MRAM), or a semiconductor storage device (SSD), etc.). As further
shown, the system comprises: an input/out (I/O) traffic analysis
component 420 for analyzing/monitoring data traffic being received, and
an adaptive cache algorithm component 422 for applying a set of
algorithms to determine the manner and location (i.e., a schema) in which
data received should be cached. In general, the set of algorithms will be
applied using analysis results from I/O traffic analysis component. Still
yet, an adaptive cache policy component 424 can be provided for applying
caching policies and making storage determinations based on the traffic
analysis and/or results of cache algorithm computation(s). Once
algorithm(s) and policies have been applied, data can be communicated to
low-mid-high cache component 432 for caching and/or storage in low speed
storage component 428, middle speed storage component 434 and/or high
speed storage component 430.

[0054] Referring back to FIG. 1, auxiliary power source unit 400 may be
configured as a rechargeable battery or the like, so that it is normally
charged to maintain a predetermined power using power transferred from
the host through the PCI-Express host interface unit 200 and supplies the
charged power to the power source control unit 500 according to the
control of the power source control unit 500.

[0055] The power source control unit 500 supplies the power transferred
from the host through the PCI-Express host interface unit 200 to the
controller unit 300, the SSD memory disk unit 100, the backup storage
unit 600A-B, and the backup control unit 700.

[0056] In addition, when an error occurs in a power source of the host
because the power transmitted from the host through the PCI-Express host
interface unit 200 is blocked, or the power transmitted from the host
deviates from a threshold value, the power source control unit 500
receives power from the auxiliary power source unit 400 and supplies the
power to the SSD memory disk unit 100 through the controller unit 300.

[0057] The backup storage unit 600A-B is configured as a low speed
non-volatile storage device such as a hard disk and stores data of the
SSD memory disk unit 100.

[0058] The backup control unit 700 backs up data stored in the SSD memory
disk unit 100 in the backup storage unit 600A-B by controlling the data
input/output of the backup storage unit 600A-B and backs up the data
stored in the SSD memory disk unit 100 in the backup storage unit 600A-B
according to an instruction from the host, or when an error occurs in the
power source of the host due to a deviation of the power transmitted from
the host deviates from the threshold value.

[0059] The storage device of a serial-attached small computer system
interface/serial advanced technology attachment (PCI-Express) type
supports a low speed data processing speed for a host by adjusting
synchronization of a data signal transmitted/received between the host
and a memory disk during data communications between the host and the
memory disk through a PCI-Express interface, and simultaneously supports
a high speed data processing speed for the memory disk, thereby
supporting the performance of the memory to enable high speed data
processing in an existing interface environment at the maximum.

[0060] While the exemplary embodiments have been shown and described, it
will be understood by those skilled in the art that various changes in
form and details may be made thereto without departing from the spirit
and scope of this disclosure as defined by the appended claims. In
addition, many modifications can be made to adapt a particular situation
or material to the teachings of this disclosure without departing from
the essential scope thereof. Therefore, it is intended that this
disclosure not be limited to the particular exemplary embodiments
disclosed as the best mode contemplated for carrying out this disclosure,
but that this disclosure will include all embodiments falling within the
scope of the appended claims.

[0061] The foregoing description of various aspects of the invention has
been presented for purposes of illustration and description. It is not
intended to be exhaustive or to limit the invention to the precise form
disclosed and, obviously, many modifications and variations are possible.
Such modifications and variations that may be apparent to a person
skilled in the art are intended to be included within the scope of the
invention as defined by the accompanying claims.