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How to improve system level testability. By Brian Harrington.

Built in self test (BIST), a technique once reserved for use in complex digital chips, can now be found in many devices with relatively small amounts of digital content. And the move to finer line process geometries has enabled several Analog Devices’ data converters to include BIST functionality.
For the chip manufacturer, BIST can help simplify the device characterisation process by providing greater visibility into the device. It can also reduce manufacturing test time by allowing autonomous testing of some subset of the chip.
BIST can realise even greater benefits at the system level, where on chip BIST functionality is incorporated into the system level design. As systems become more complex, integrating individual components with BIST allows a hierarchical test strategy to be implemented, providing a powerful means of enhancing system reliability.
At the system level, BIST functionality can be used in the design phase to characterise digital interface timing between the digital processors and the data converters. Without BIST, bit errors in the digital interface must be detected by changes in the converters’ noise floor. This type of error detection is much less sensitive than a digitally based BIST signature check, which can detect a single bit error. This same digital interface check can be performed on the production test floor, or in system level self tests in the field.