AccelerComm and Achronix enable fast time to market with 5G polar code for Speedcore eFPGAs

Achronix Semiconductor Corporation, a leader in field programmable gate array (FPGA)-based hardware accelerator devices and embedded FPGA (eFPGA), announced its collaboration with AccelerComm Ltd, a semiconductor intellectual property (IP) company focusing on next-generation wireless communications acceleration. AccelerComm’s patent-pending Polar Code IP has been ported to support the Achronix portfolio of FPGA products, enabling rapid time to market and customization for 5G Enhanced Mobile Broadband (eMBB) utilizing New Radio. AccelerComm IP has been integrated with ACE design tools to target Achronix Speedcore™ eFPGA.

Polar forward error correction (FEC) codes are utilized in the control channel of high-performance 5G systems. The AccelerComm polar code solution is built around a unique memory architecture that delivers the right information to the right processing elements at the right time, improving hardware efficiency, power efficiency and latency. The availability of this IP for the Achronix Speedcore eFPGA fabric enables a lower power and higher throughput solution than alternative, software-based approaches. Instantiating the polar code IP within an eFPGA-equipped application specific integrated circuit (ASIC) or system on chip (SoC) enables an integrated solution with minimal communication latency and low-power consumption.

“We are pleased to be working with AccelerComm as part of the Achronix Partner Program,” says Mike Fitton, Achronix senior director, product planning and business development. “The ability to instantiate AccelerComm’s industry-leading Polar Code IP in our eFPGA allows Speedcore-enabled ASIC and SoCs to be updated to support new standards. We see that the ability to flexibly reprogram a hardware accelerator for new requirements and emerging standards is going to be fundamental for cost-effective 5G deployments.”