Debug Task Group tech-debug@lists.riscv.org

Group Description

Welcome to the RISC-V Debug Task Group secure area. The Debug Task Group's goal is the ratification of a specification for how to enable low-level hardware debugging on RISC-V implementations. In this section of the RISC-V Foundation Workspace you will find meeting minutes and slides, updated on a regular basis. Access to this area is restricted to members of the Debug Task Group. For updates, keep an eye on this space and the task group mailing list:debug@workspace.riscv.org. Success Criteria: A Foundation-Ratified Specification for Run/Halt debug of RISC-V based systems. This is desired by the 8th RISC-V Workshop in Barcelona, May 2018. Auxiliary Goals: Reference implementations & reference SW implementations, Documented SW conventions for debug-related tasks; Explicitly Out of Scope: Trace specification