On Monday 15 November 2004 16:00, Ignatios Souvatzis wrote:
> I wonder whether somebody here can share his wisdom with us
>
> In short: which part of the chipset driver should drive the PCMCIA slot
> reset line --- and what is the minimum time required?
There are timing diagrams in chapter 4 of the PCMCIA spec that provide a lot
of detail on this, although it's hard to read.
According to the standard, #RESET is not driven by the host during the initial
Vcc ramp (100ms max), and is asserted after that. In the pcic and pccbb
drivers, I assert the RESET bit before applying Vcc for a couple of reasons:
1) It is automatically switched by most PCMCIA controllers when we hit a
certain voltage level, so it does no harm.
2) Some flash devices tie #RESET to Vpp through a resistor, so that asserting
#RESET will drain any residual current from the Vpp circuitry. You want this
to be done ASAP.
The sequencing I recommend is:
a) Assert RESET in software. (It's active low on the pin, but which way it is
in software varies.)
b) Turn on socket power.
c) Wait for at least the Vcc rising time (Tpr, 100ms). (We use 200ms in pcic
because some lame handheld devices ramp up too slowly, in violation of the
spec.)
d) Negate RESET.
e) Wait for the RESET setup time (Tsu, 20ms).
f) Wait for READY (up to 5s).
This is the sequencing that pcic and pccbb use now, and there are no known
incompatibilities with it.