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AR# 58670

2013.4 Vivado IP Release Notes - All IP Change Log Information

Description

This answer record contains a comprehensive list of IP change log information from Vivado 2013.4 in a single location which allows you to see all IP changes without having to installing the Vivado Design Suite.

Solution

100G Ethernet (1.0)

* Version 1.0

* Initial release

* CAUI10 mode supported

* Note:This core is released for simulation only. Hardware implementation is not supported with this release.

32-bit Initiator/Target for PCI (7-Series) (5.0)

* Version 5.0 (Rev. 3)

* Zynq devices marked as production

* Fixed syntax error in wave.sv file

3GPP LTE Channel Estimator (2.0)

* Version 2.0 (Rev. 3)

* Support for Kintex UltraScale devices at Pre-Production Status

3GPP LTE MIMO Decoder (3.0)

* Version 3.0 (Rev. 3)

* Support for Kintex UltraScale devices at Pre-Production Status

3GPP LTE MIMO Encoder (4.0)

* Version 4.0 (Rev. 3)

* Support for Kintex UltraScale devices at Pre-Production Status

3GPP Mixed Mode Turbo Decoder (2.0)

* Version 2.0 (Rev. 3)

* C model changes so that the C model can be used along with C models from other cores. This changes exported types and function names. See smoke test and c model .h for examples and prototypes.

* Support for Kintex UltraScale devices at Pre-Production Status

3GPP Turbo Encoder (5.0)

* Version 5.0 (Rev. 3)

* Support for Kintex UltraScale devices at Pre-Production Status

3GPPLTE Turbo Encoder (4.0)

* Version 4.0 (Rev. 3)

* Support for Kintex UltraScale devices at Pre-Production Status

64-bit Initiator/Target for PCI (7-Series) (5.0)

* Version 5.0 (Rev. 3)

* Zynq devices marked as production

* Fixed syntax error in wave.sv file

7 Series FPGAs Transceivers Wizard (3.1)

* Version 3.1

* Reset FSM updates- removed the posedge detection logic for plllock

* GTZ updates- added new line rate support and updated xdc file for the constraints

* Increased the number of optional transceiver control and status ports

* Arbitrate on low TVALID cycles is now disabled if Arbitrate on max transfers is 1. Parameter has no meaning in this configuration.

* Arbitrate on low TVALID cycles must be greater than one if there are multiple slaves and multiple masters and Arbitrate on max transfers is not 1. This is to prevent deadlock situations.

AXI4-Stream to Video Out (3.0)

* Version 3.0 (Rev. 3)

* Kintex UltraScale Pre-Production support

* Automotive Zynq devices support

Accumulator (12.0)

* Version 12.0 (Rev. 3)

* GUI tooltips added for INIT values

* Support for Kintex UltraScale devices at Pre-Production Status

Adder Subtracter (12.0)

* Version 12.0 (Rev. 3)

* Latency is now restricted to the output width. Previously the GUI allowed illegal values

* Tooltips added to GUI

* Support for Kintex UltraScale devices at Pre-Production Status

Asynchronous Sample Rate Converter (2.0)

* Version 2.0 (Rev. 2)

* No changes

Aurora 64B66B (9.1)

* Version 9.1

* Increased the number of optional transceiver control and status ports

Aurora 8B10B (10.1)

* Version 10.1

* Increased the number of optional transceiver control and status ports

Binary Counter (12.0)

* Version 12.0 (Rev. 3)

* Tooltips added to GUI

* Support for Kintex UltraScale devices at Pre-Production Status

Block Memory Generator (8.1)

* Version 8.1

* The Primitive output registers are made "ON" by default in the stand alone mode

* Added cascaded support for ltraScale devices to construct 64Kx1 primitive by using two 32Kx1 primitives

* Added support for UltraScale devices

CIC Compiler (4.0)

* Version 4.0 (Rev. 3)

* Support for Kintex UltraScale devices at Pre-Production Status

CORDIC (6.0)

* Version 6.0 (Rev. 3)

* C model modified to be interoperable with C models from other cores. The xip_array_* structures and interface functions xip_array_<type>_get_data and xip_array_<type>_set_data are renamed xip_<core>_array_<type>_[]set|get]_data.

* Support for Kintex UltraScale devices at Pre-Production Status

CPRI (8.1)

* Version 8.1

* Added version register.

* Kintex UltraScale Pre-Production support.

* Added optional transceiver control and status ports.

* For IP Integrator, previous bus I/F names have been renamed for consistency. Upgraded IP Integrator designs using this core will require reconnection of the Bus I/F's.

* Improved current and previous AXI4-Stream video stream synchronization. The core now waits for a start of frame (SOF) signal on the 'previous' input stream, coming from the VDMA, while dropping samples on the current input. After the SOF is captured, the previous channel is held up, while the core waits for SOF on the current input.

* Similar synchronization mechanism is employed for EOF signals. The core now can recover from cable disconnect - reconnect, or the system starting with a partial frame.

* Addition of Dynamic Cancellation Pulse(CP) computation Mode where CP is computed dynamically based on power and frequency for individual carriers. This is called Dynamic Mode. This mode is required only if incoming data is frequency hopping and/or power hopping.

* In Dynamic Mode, Tuser field has been added to the AXI4 stream (s_axis_din_tuser) that contains control information for the Dynamic CP computation.

* Static Mode is similar to PC-CFR v4.0 where static Cancellation Pulse coefficients can be loaded through AXI-Lite interface

* Support for multiple air interfaces including frequency hopping MC-GSM up to 8 GSM carriers

* Support for hard clipper final stage (optional)

* GUI changes include a new input field Max Peak Detect Window instead of two earlier input fields Cancellation Pulse Length and Latency. This change applies to both Static and Dynamic Mode

* GUI Implementation tab also shows an AXI4 Stream port structure

* C Model has also been updated to reflect the Dynamic CP computation.

* For more information on the above changes, please refer to the product guide

Processor System Reset (5.0)

* Version 5.0 (Rev. 3)

* Added exdes.xdc file

* Changed the associated resets for slowest_sync_clk

* Kintex UltraScale Pre-Production support

QSGMII (3.1)

* Version 3.1

* Kintex UltraScale Pre-Production support

* GT updates for Series-7 transceivers (RX/TX Startup FSM updates)

* Increased the number of optional transceiver control and status ports

RAM-based Shift Register (12.0)

* Version 12.0 (Rev. 3)

* Missing tooltips added to GUI

* GUI error on change of radix fixed.

* Support for Kintex UltraScale devices at Pre-Production Status

RGB to YCrCb Color-Space Converter (7.1)

* Version 7.1 (Rev. 1)

* Kintex UltraScale Pre-Production support

RXAUI (4.1)

* Version 4.1

* Added support for UltraScale

* Increased the number of optional transceiver control and status ports.

Reed-Solomon Decoder (9.0)

* Version 9.0 (Rev. 3)

* Change to end of simulation message in demonstration testbench.

* Support for Kintex UltraScale devices at Pre-Production Status

Reed-Solomon Encoder (9.0)

* Version 9.0 (Rev. 3)

* Support for Kintex UltraScale devices at Pre-Production Status

S/PDIF (2.0)

* Version 2.0 (Rev. 3)

* Updated rtl files to refer sub cores from central area instead of local files

* Refactored the encrypted HDL to remove a level of design hierarchy and updated all core level XDC constraints where appropriate. Most customer designs will not be creating XDC constraints which target logic within this core and so will be unaffected by this change.

* Removed all generic parameters that passed through the readable HDL hierarchy of the core. Generic parameters now only appear on the instantiation of the top level of the encrypted HDL portion of the core.

* A new example design XDC file is provided to show customers how to override default XDC settings provided by the core itself for setup and hold timing adjustment of the selected physical interface. This additional example XDC file is named <component_name>_user_phytiming.xdc

* Added clock buffer information to the clocks defined in the out of context XDC file to support hierarchical design flows.

* Added clock constraints for refclk, the IDELAYCTRL reference clock, to the out of context XDC for applicable permutations.

UltraScale FPGAs Transceivers Wizard (1.1)

* Version 1.1

* Added several new transceiver configuration preset options

* Added support for the user data width sizing helper block

* Added recovered clock output options in the Physical Resources tab

* Added initial support for simulation of the CAUI-4 preset utilizing GTY transceivers

UltraScale FPGA Gen3 Integrated Block for PCI Express (2.0)

* Version 2.0

* Enabled all EP configurations

* Enabled Advanced Mode

* Enabled Xilinx Development Board and added option "KCU105"

* RP simulation model in the test bench support only for x8Gen3 configuration