Links

Images

Classifications

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof

H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70

H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

H01L21/76841—Barrier, adhesion or liner layers

H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric

H—ELECTRICITY

H01—BASIC ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof

H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70

H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure

H—ELECTRICITY

H01—BASIC ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof

H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70

H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics

H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors

Abstract

PURPOSE: A method for forming a metal interconnection of a semiconductor device is provided to improve step coverage of a copper film without using CMP(Chemical Mechanical Polishing). CONSTITUTION: An insulating layer(2) with a contact hole is formed on a conductive layer(1). The first diffusion barrier layer(3) is deposited on the resultant structure. The first copper film(4) is partially filled in the contact hole by PVD(Physical Vapor Deposition). The second copper film(5) is entirely filled in the contact hole by PVD. The resultant structure is planarized by annealing under inert gas or hydrogen gas atmosphere. An anti-reflective layer(6) is formed on the second copper film. A metal interconnection(10) is then formed by patterning the anti-reflective layer, the second and first copper film, and the first diffusion barrier layer.

실리콘 기판 또는 도전층 상부에 콘택홀이 구비되는 절연막을 형성하는 단계와, Forming an insulating film to be a contact hole provided in the silicon substrate or the conductive layer,

상기 콘택홀을 포함한 전체표면상부에 제1확산방지막을 증착하는 단계와, Depositing a first diffusion preventing film on the upper entire surface including the contact holes,

스퍼터링 챔버에서 물리기상증착방법을 이용하여 전체 금속배선 두께의 50% 이하로 제1구리막을 증착하는 단계와, Depositing by physical vapor deposition method in a sputtering chamber to less than 50% of the thickness of the metal wiring of copper film, and

불활성가스 또는 수소가스 분위기 하에서 열처리하여 상부구조를 평탄화시키는 단계와, And the step of flattening a top structure by heat treatment in an inert gas or hydrogen gas atmosphere,

상기 제2구리막 상부에 반사방지막을 증착하는 단계와, Comprising the steps of: depositing the first anti-reflection film on the second copper layer thereon,

금속배선 마스크를 이용한 사진식각공정으로 상기 반사방지막, 제2구리막, 제1구리막 및 제1확산방지막을 식각하여 금속배선을 형성하는 단계와, A photolithography process using a metallization mask and etching to form a metal wiring to the anti-reflection film and the second copper film, the first copper layer and the first diffusion barrier,

상기 금속배선의 표면에 선택적으로 제2확산방지막을 형성하는 단계를 포함하는 것과, As including the step of selectively forming a second diffusion barrier on the surface of the metal wiring,

상기 제1 및 제2 확산방지막은 실리나이트라이드 계통의 합금으로 형성하는 것과, As the first and the second diffusion preventing film is formed of an alloy of silico-nitride systems,

상기 제1 및 제2 확산방지막은 Ta/TaSiN 또는 W/WSiN 인 것과, It said first and second diffusion barrier is that the Ta / W or TaSiN / WSiN,

상기 콘택홀(20) 저부면에 형성된 자연 산화막(도시안됨)을 제거하고, 전체표면상부에 확산방지막인 제1확산방지금속층(3)을 형성한다. Removing a natural oxide film (not shown) formed in the contact holes 20, the bottom surface, and to form a diffusion preventing film on the entire upper surface of the first diffusion preventing metal layer (3).

이때, 상기 제1확산방지금속층(3)은 Ta/TaSiN 또는 W/WSiN등의 실리나이트라이드 계통의 합금 형태로 형성한다. At this time, the first diffusion preventing metal layer 3 is formed of the alloy in the form of silica nitride system such as Ta / W or TaSiN / WSiN.

이때, 상기 제2구리막(5) 형성공정은 동일 증착 챔버 내에서 실시하거나 다른 증착 챔버로 웨이퍼를 이동시킨 후 실시한다. At this time, the second copper film 5 forming step is carried out after having carried out, or moving the wafer to the other deposition chamber in the same deposition chamber.여기서, 상기 제2구리막(5)은 고온 고진공으로 유지된 증착 챔버에서 400 - 650 ℃ 의 온도 및 1 - 5 kW 의 전력으로 증착한다. Here, the second copper film 5 is 400 in a deposition chamber maintained at a high temperature vacuum-deposited to a 5 kW power - temperature and 1 of 650 ℃.

상기의 공정이 완료되면 콘택홀(20) 상부의 상기 제2구리막(5) 표면이 평탄화되지만 상기 콘택홀(20)의 내부에 보이드(8)가 발생될 수 있다. When the process is complete, the contact hole 20, the second copper film 5, the upper surface of the planarization, but may be a void 8 is generated in the interior of the contact holes 20.

도 4를 참조하면, 상기 도 3의 제2 구리막(5)의 증착공정후 웨이퍼의 이동없이 아르곤과 같은 불활성가스 또는 수소 가스를 유입시켜 650 - 800 ℃ 의 온도에서 수분간 열처리함으로써 상기 제2구리막(5)이 상기 보이드(8)로 플로우되어 상기 보이드(8)가 제거된다. The second by several minutes and heat treatment at a temperature of 800 ℃ - 4, FIG. 3 to the inlet of an inert gas or hydrogen gas, such as argon, without any movement of the deposition process after the wafer of the second copper layer (5) 650 copper film 5 is flow into the voids 8, wherein the voids (8) is removed.

도 5를 참조하면, 상기 제2구리막(5) 상부에 반사 방지층(6)을 증착하고 금속 배선 마스크(도시안됨)를 이용한 사진식각공정으로 상기 반사방지층(6), 제2구리막(5), 제1구리막(4) 및 제1확산방지금속층(3)을 선택적으로 식각하여 금속배선(10)을 형성한다. 5, the second copper film 5 by photolithography deposition of the antireflection layer (6) on the top and using a metallization mask (not shown), the anti-reflection layer 6, a second copper layer (5 ), first by selectively etching the copper film 4 and the first diffusion preventing metal layer 3 to form the metal wiring 10.

도 6을 참조하면, 상기 금속배선(10)의 표면에 확산방지막인 제2확산방지금속층(7)을 형성한다. Referring to Figure 6, to form a diffusion preventing film in the second diffusion preventing metal layer (7) on the surface of the metal wiring 10.

이때, 상기 제2확산방지금속층(7)은 선택적 화학 기상 증착방법으로 상기 제1확산방지금속층(3)과 같은 물질을 증착하여 형성한다. At this time, the second diffusion preventing metal layer (7) is formed by depositing a material such as the first diffusion preventing metal layer (3) by selective chemical vapor deposition method.이때, 상기 제2확산방지금속층(7)은 상기 금속배선(10)의 측벽과 상부에만 증착되어 구리의 확산을 방지할 수 있다. At this time, the second diffusion preventing metal layer 7 is deposited only on the side walls and the upper part of the metal wiring 10 can be prevented from diffusion of copper.

이상에서 설명한 바와 같이 본 발명에 따른 반도체소자의 금속배선 형성방법은, 양산에 널리 사용해온 물리 기상 증착방법인 스퍼터링 장치를 이용하여 실용화시킬 수 있고, 불활성가스 또는 수소가스 분위기 하에서의 열처리공정으로 별도의 CMP 공정없이 구리막의 평탄화를 이룰 수 있는 효과를 제공한다. A metal wiring method for forming a semiconductor device according to the present invention as described above, it is possible to put to practical use by using a physical vapor deposition method, the sputtering device been widely used in mass production, a separate inert gas or heat treatment step under a hydrogen gas atmosphere. It provides an effect that can be achieved for a copper film without flattening CMP process.

Claims (10)

Translated from Korean

실리콘 기판 또는 도전층 상부에 콘택홀이 구비되는 절연막을 형성하는 단계와, Forming an insulating film to be a contact hole provided in the silicon substrate or the conductive layer,

상기 콘택홀을 포함한 전체표면상부에 제1확산방지막을 증착하는 단계와, Depositing a first diffusion preventing film on the upper entire surface including the contact holes,

스퍼터링 챔버에서 물리기상증착방법을 이용하여 전체 금속배선 두께의 50% 이하로 제1구리막을 증착하는 단계와, Depositing by physical vapor deposition method in a sputtering chamber to less than 50% of the thickness of the metal wiring of copper film, and

불활성가스 또는 수소가스 분위기 하에서 열처리하여 상부구조를 평탄화시키는 단계와, And the step of flattening a top structure by heat treatment in an inert gas or hydrogen gas atmosphere,

상기 제2구리막 상부에 반사방지막을 증착하는 단계와, Comprising the steps of: depositing the first anti-reflection film on the second copper layer thereon,

금속배선 마스크를 이용한 사진식각공정으로 상기 반사방지막, 제2구리막, 제1구리막 및 제1확산방지막을 식각하여 금속배선을 형성하는 단계와, A photolithography process using a metallization mask and etching to form a metal wiring to the anti-reflection film and the second copper film, the first copper layer and the first diffusion barrier,

상기 제1 및 제2 확산방지막은 실리나이트라이드 계통의 합금으로 형성하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법. It said first and second diffusion prevention film is a metal wiring method for forming a semiconductor device characterized by forming an alloy of silico-nitride system.

제 1 항에 있어서, According to claim 1,

상기 제 1 및 제 2 확산방지막은 Ta/TaSiN 또는 W/WSiN 인 것을 특징으로 하는 반도체소자의 금속배선 형성방법. Said first and second diffusion barrier is formed in the metal wiring method of a semiconductor device which is characterized in that the Ta / W or TaSiN / WSiN.

상기 제1확산방지막은 막질향상을 위한 후처리공정을 실시하는 것을 특징으로 하는 반도체소자의 금속배선 형성방법. The first diffusion preventing film is a metal wiring method for forming a semiconductor device characterized in that after the performed treatment process for improving the film quality.