TSMC's R&D boss addresses 40-nm yields, high-k, litho

SAN JOSE, Calif. -- At the TSMC Japan Executive Forum in Yokohama this week, Shang-Yi Chiang, senior vice president of R&D at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), addressed several issues about the silicon foundry giant.

Chiang discussed TSMC's 40-nm capacity, yield issues, high-k and lithography. EE Times obtained a transcript of the presentation. Here's some of the issues discussed:

1. 40-nm capacity issues

(As previously reported, Nvidia Corp. and others are struggling to get their 40-nm wafers from TSMC.)

Chiang: ''There are four major messages I'd like to deliver in this presentation. Number one is 40-nanometer technology happened to be a very high demand in the early stage, so we saw the customer demand ramp up so quick, more than what we had seen before for 40-nanometer, and we are working very hard to make up the volume.

At this stage we only have fab 12 ready to tape production of 40 nanometer and we are able to do about 80,000 wafers per quarter at the moment. These are twelve-inch wafers. And this will be doubled by the end of this year, to 160,000 twelve-inch wafers for 40 nanometer capacity by the end of this year, and partly from fab 12 and partly from fab 14.''

2. 40-nm yield issues

(For some time, TSMC has struggled with 40-nm issues.)

Chiang: ''You all heard about TSMC is challenge during the early part of last year. I report to you we are glad all this problems was behind us. We resolve this yield problem in the second half of last year. So we're glad the yield issue was over, and we are building the capacity very aggressively to fulfill the very high demand from our customers.

Moving to 45 and 40 nanometer is a lot more challenging. This is the first time we began to use 193 nanometer shrink immersion. That means the photo resist during exposure will be merged in water and is a very high potential defect. For this a very big challenge. We began to develop the third generation. We began to use the second generation low k material with a k value of 2.5 and at this k value the material become quite fragile so there is a lot of potential issues in the package side. So moving to 40 nanometer that's why it's getting pretty challenging, pretty difficult to do.''

3. Progess at 28-nm

(Several months ago, TSMC rolled out its 28-nm, which will have several options.)

Chiang: ''The first node we're going to release for the 28-nanometer will be we call the 28 LP. This is our poly gate and silicon oxide nitrate version. We will establish production at the end of June this year, about four months from now, and this is for the low power application. Again, no high-k metal gate.''

4. Progress on high-k and metal gate

(At 28-nm, TSMC is expected to have a high-k/metal-gate option.)

Chiang: ''The first high-k metal gate we call 28 HP for the high performance application will be introduce the end of September this year, and followed by three months later December will be the 28 HPL. This is the first high-k metal gate introduction for the low power application.

At this moment the only way we know how to do that is the gate last approach. So I firmly believe everybody will migrate to using gate last in the future generation, and could be as early as 22, 20 nanometer mode. Even some of our competitors who claim gate first have unique advantage, I firmly believe they will move to gate last very quickly.

There are for the gate last process. It happen you can achieve the higher constraint from silicon germanium because by the time you remove the poly silicon from the gate the silicon gemainium can push the channel in a little bit to have more strength in the channel. But by far the biggest advantage, and that's why TSMC achieves the gate last is the first one you can have different work functions for different gate metal.''