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Description

General Description:When I simulate a design with CORE Generator Dual-Port Block Memory, the simulator reports the following message:

WARNING [STX-RNGDEF]:/nfs/ibu_apps/xilinx/E.30/verilog/src/XilinxCoreLib/BLKMEM-DP_V3_0.v, line 783: module BLKMEMDP_V3_0, instanceao16f_fifo32x32_1rs_1w.uMEM.inst, Design Error: Out of rangememory select on pipelinea. [1] is selected, but only [0:0] is defined.

Solution

The problem is in Verilog behavioral model "blkmemdp_v3_2.v" and earlier versions of the "dp blk" memory. This problem will be fixed inDual-Port Block Memory v4_0, which is scheduled to be released in the E_IP1 update in late October, 2001.