Figure 7.

Schematic views of ZnO NW FET and polarization model for FE NPs surrounding a NW. (a) A schematic view of a top-gate FET-based nonvolatile memory device. For a top-gate
ZnO NW FET where a ZnO NW is incorporated with FE NPs, cross-linked poly (4-vinylphenol)
(c-PVP) was used as a gate dielectric. (b,c) The schematic views of a simplified polarization model for FE NPs surrounding a
NW. The lines show the electric field distribution between a ZnO NW and a gate electrode.
Electric dipole moments are reoriented along electric field lines, resulting in different
polarization states according to the gate electric field strength. Furthermore, affected
by more reoriented electric dipole moments, the denser the equipotential lines around
the upper part of a NW are, the easier it is to induce more polarized charges at the
FE-NW interface. Thus, different conductance states result from different net amounts
of reoriented electric dipole moments dependent on the applied gate electric field
strength.