8 Cortex-M0+ 32-bit RISC processor2-stage pipeline von Neumann architectureARMv6-M architecture16-bit Thumb instruction set with Thumb-2 technology.Load-Store Architecture56 InstructionsBecause there are several generations of ARM processors, the architectures of these processors are also divided into different version.Where each version defines a programmers model, instruction set, exception mechanism.

9 Simplified Block DiagramNVIC The NVIC is an embedded interrupt controller that supports low latency interruptprocessing. Up to 32 Interrupt signals. Priority features, tail-chaining and External NMI.The system timer SysTick, is a 24-bit count-down timer. Use this as a Real TimeOperating System (RTOS) tick timer or as a simple counterWIC can detect an interrupt and wake the processor from deep sleep mode.The WIC is not programmable, and does not have any registers or user interface.When the WIC is enabled and the processor enters deep sleep mode, the power management unitin the system can power down most of the Cortex-M0+ processor.MPU –Debug System: It allows to handle breakpoint and watchpoints.Debug Access Port . JTAG or Serial Wire .(5 & 2 lines)

11 Programmers modelThread mode Executes application software. The processor enters Thread mode when itcomes out of reset.Handler mode Handles exceptions. The processor returns to Thread mode when it hasfinished all exception processingUnprivileged The software:• has limited access to system registers using the MSR and MRSinstructions, and cannot use the CPS instruction to mask interrupts• cannot access the system timer, NVIC, or system control block• might have restricted access to memory or peripherals.Unprivileged software executes at the unprivileged level.Privileged The software can use all the instructions and has access to all resources.Privileged software executes at the privileged level.StacksThe processor uses a full descending stack.

12 Memory model 4GB of memory address space Code Region SRAM RegionPeripheral RegionRAM RegionDevice RegionInternal Private Peripheral BusDivided into a number of regions. Each region has its recommended usage.Support only aligned transfersExternal Device .- 2* 512MB does not allow program execution. Used for general data storage.External RAM MB allows program executionPeripheral. Not execution allowed. Connected to AHB bus or APB.SRAM.- 512MBCode.- Vector Table, code and data.

14 Ultra-low Power ModesExpands beyond typical run, sleep and deep sleep modes with power options designed to maximize battery life in varying applicationsModeDefinitionRunMCU can be run at full speed. Supports Compute Operation clocking option where bus and system clock are disabled for lowest power core processing and energy-saving peripherals with an alternate asynchronous clock source are operational.VLP Run(VLPR)MCU maximum frequency is restricted to 4MHz core/platform and 1 MHz bus/flash clock. Supports Compute Operation clocking option. LVD protection is off and flash programming is disallowed.WaitAllows all peripherals to function, while CPU goes to sleep reducing power consumption. No Compute Operation clocking option.VLP Wait(VLPW)Similar to VLP Run, with CPU in sleep to further reduce power. No Compute Operation clocking option.StopMCU is in static state with LVD protection on. Energy-saving peripherals are operational with Asynchronous DMA (ADMA) feature that can wake-up DMA to perform transfer and return to current mode when complete. AWIC detects wake-up source for CPU. Lowest power mode with option to keep PLL active.VLP Stop(VLPS)MCU is in static state with LVD protection off. Energy-saving peripherals are operational with ADMA feature. AWIC detects wake-up source for CPU.LL Stop(LLS)MCU is in low leakage state retention power mode. LLWU detects wake-up source for CPU including LPTMR, RTC, TSI, CMP, and select pin interrupts. Fast <4.3us wake-up.VLL Stop 3 (VLLS3)MCU is placed in a low leakage mode powering down most internal logic. All system RAM contents are retained and I/O states held. LLWU controls wake-up source for CPU similar to LLS mode.VLL Stop 1(VLLS1)Similar to VLLS3 with no RAM or register file retention.VLL Stop 0(VLLS0)Pin wakeup supported. LPTMR, RTC, TSI and CMP wake-up supported with external clock. No RAM or register file retention. Optional POR brown-out detection circuitry.RUNSLEEPDEEP SLEEP

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