B.1.1. Registered signals

To ensure ease of integration of the cache controller into
embedded applications, and to simplify synthesis flow, the following design
techniques have been used:

a single rising
edge clock times all activity

all signals and buses are unidirectional

all inputs are required to be synchronous to the
relevant clock, CLK, or HCLK.

These techniques simplify the definition of the top-level
cache controller signals because all outputs change from the rising
edge and all inputs are sampled with the rising edge of the clock.
In addition, all signals are either input or output only. Bidirectional
signals are not used.