Changing technology at 10nm will be too late. FinFET introduction has not given the advantage the companies thought it would due to complexity and litho limitation among many other things but i guess until someone else prove that FDSOI is better then companies will reconsider.

I guess it is possible that at some point finFET would be build on Soi substrate, personally I don,t think that would happen...looks too complicated...there is no reasons why the two consortiums would not continue developing what they put massive r&d investments already in

Michigan0, the reason SOITEC delivers 12nm SOI wafer is not because they cannot deliver thinner wafers. It is simply because they are asked to do so. Any person familar with CMOS technology recongnizes that you need to consume a few nanometer to form STI (pad oxide needed before deposited pad nitride), then you need a few nanometer oxide for your I/O devices. Once you do the math, you realize that for a taget channel thickness of 6-7 nanometer you have to start somewhat thicker and this is exactly what has been asked from SOITEC and SEH. Unless you want to use deposited oxide for pad-ox and I/O devices (which is of course inferior to thermal oxide) this is what you'd need. Again, anybody that processed CMOS wafers knows that thermal oxidation is precisely controlled -- for our reference gate oxide was about 1nm thick with less than 5% variation before people switched to high-k.

As far as thickness control goes, in fact FDSOI has significant advantage over FinFET. The device is planar, which means you have a variety of well established methods to monitor thickness on as-received wafer and during processing, including ellipsometry and AFM. Metrology is a big problem with FinFET. Let alone the loading effects in depositing the spacer in SIT process and in etching the fins. Yes, FinFET is in mass production but I can say with enough confidence that it did NOT deliver the promissed 50% reduction in power that was claimed back in 2011 even after supposedly toc of Haswell.