AbstractElectromigration (EM) is a phenomenon that has been well researched and understood by the design community. At mature nodes, its impact on digital integrated circuits, particularly signal interconnects, has been minimal, making signal EM analysis and fixing an optional design step. At 28 nm and beyond, this is no longer the case. Interconnects are getting thinner, running longer and switching at gigahertz speeds - all of which amplify the effects of EM. Signal EM analysis and fixing is turning into a design requirement that must be met during place and route. This article discusses the importance of signal EM and ways to address it in today’s complex designs. It also highlights the EM capabilities in IC Compiler with results from Altera’s successful adoption of the solution for its 28-nm high performance IPs.

Electromigration 101 - A refresherElectromigration (EM) is the gradual displacement of metal atoms in a semiconductor. It occurs when the current density through the conductor is high enough to cause the drift of metal ions (Fig 1).

Figure 1 : [Electromigration in a conductor], Source – Synopsys

EM decreases the reliability of integrated circuits (ICs). An EM failure at its worst manifests itself as either a void (open) or a hillock (short), which eventually leads to circuit malfunction (Fig 2).

Signal EM – Why it matters more than ever While EM and its impact on designs have long been understood, in mature technology nodes the effects were minimal and were not a big concern. Due to wider interconnects, lower operating speeds and smaller design sizes, manual methods or a conservative approach of oversizing wires for EM served as plausible solutions. However, at 28 nm and beyond, scaling trends in advanced technology nodes along with stringent and complex EM rules make designs more susceptible to EM – particularly on clock and data interconnects. As a result, signal EM and its effects can no longer be ignored.

Advanced technology trends Metal widths are shrinking because of geometry scaling, resulting in thinner interconnects. Interconnect lengths are also increasing to meet the complex device integration demands. These thin and long interconnects are switching at gigahertz speeds due to the push for higher performance. When combined, these factors result in higher current densities, which amplify the effects of signal EM at advanced technology nodes.

A clear indication of this trend can be seen in the chart below that plots EM violations seen on a sample block across varying technology nodes and clock frequencies (see Fig 2). At 28 nm, there are significantly more EM violations on signal interconnects compared to those at 65 and 40 nm.

Growing EM rule complexity In order to reflect the effects of advanced technologies, EM rules have also become more complex. EM rules are foundry-provided limits that specify allowable current densities for every metal layer. In the past, the limits provided were primarily width and junction-temperature based (as shown in Fig 4).

Figure 4: [Sample EM constraint table], Source -Synopsys

At 28 nm and below, we are seeing the addition of more dependencies, such as interconnect length, via dimensions and delta temperatures (metal line temperature increase over junction temperature when current passes through it).

EM analysis is a complex task that requires a significant amount of data interpretation and is compute intensive. With an increasing number of interconnects exposed to EM effects, fixing techniques must be automatic, accurate, and timing and design-rule check (DRC) aware. A stand-alone post place and route step would not be ideal as it would be iterative, require user expertise and can adversely affect performance.

For today’s complex and challenging designs, the only way to effectively analyze and fix signal EM is to address it during P&R.

The article clearly needs to emphasize the metric current density vs. current magnitude whether effective, RMS or average values! Temperature effects are of course important but current densities all the way to chip-to-chip (in case of 3D / 2.5D IC) and chip-to-package-level interconnects. Metal lines in IC can take 1E6 Amp/cm^2 current density but interconnects (flipchip or wirebond) and TSV's have lower limits.
MP Divakar