450 mm Wafer Transition

450 mm Wafer Transition

Industry Readiness Improves, but Timing and Funding Remain Uncertain

By Jonathan Davis, president, Global Semiconductor Business

The transition of leading-edge semiconductor manufacturing to 450mm wafers is one of the complex and challenging issues in our industry. Advocates claim larger wafers are necessary to keep pace with Moore’s Law cost targets; opponents claim it will restructure the industry, negatively impact profitability, and drain precious R&D funding away from essential innovations in scaling, cycle time improvements and manufacturing flexibility.

The International SEMATECH Manufacturing Initiative (ISMI) has made significant progress in moving the debate forward and facilitating industry readiness through wafer handling pilot lines, sample wafer loans, and other activities. SEMI, while advocating the need for a cogent economic and supply chain cost analysis as a prerequisite for implementing 450 mm manufacturing, has also contributed to the process through the SEMI Standards 450 mm Task Force and publication of the first 450 mm standards for wafer carriers and load ports. Companies and R&D consortia are also ready for the hard work involved in scientific research and product development.

Now, if the industry decides to adopt 450 mm wafer manufacturing, it will have to determine timing, funding mechanisms, and process. Will 450 mm full production be targeted for 2015, 2018 or sometime beyond 2020? How will the industry pay for the multi-billion R&D price tag for a 450 mm wafer transition? And, what process will the industry use to make informed, collective decisions on issues impacting multiple chip makers and a global supply chain?

This article will provide background information on the 450 mm consideration and the current state of industry readiness on this critical industry-wide planning issue.

The Case for Larger Wafers

In November of 2005, the SEMI and SEMATECH Board of Directors members met to discuss an industry-wide transition to larger wafers. Based on an analysis by ISMI, the industry was facing a significant deviation from the productivity improvements predicted by Moore’s Law. According to ISMI, wafer processing cost curves were shifting unfavorably and that the traditional rate of reduction in the cost per transistor could not be maintained without a wafer scale-up.

Improved silicon productivity is the primary argument for wafer size transitions. Increases in wafer area can increase the number of dies per wafer and lead to a theoretical reduction in die cost of approximately 30 percent (if all other costs remain constant). The semiconductor industry has been able to increase wafer size about once every 10 years. The industry first started using 200 mm wafers in 1991 and then switched to 300 mm wafers in 2001. ISMI’s original goal of changing to 450 mm wafers in 2012 would be consistent with that industry timeline.

Remembering the difficult and costly transition to 300 mm wafers, SEMI members formed the Equipment Productivity Working Group (EPWG) to conduct their own simulation, survey, and modeling to analyze the issues supporting the cost reduction contribution of a wafer scale-up. After two years of open, collaborative analysis, the EPWG concluded in a White Paper that 450 mm wafer scale-up represents a low-return, high-risk investment opportunity for the entire semiconductor ecosystem1.

Equipment suppliers and others argued that wafer size increases represent the single largest and most disruptive type of investment the industry could undertake, detracting from increasingly difficult challenges in scaling. Every piece of process and automation equipment must be redesigned, from crystal growing to final test. It was argued that technology requirements for 450 mm tools far exceed a simple linear size expansion of existing 300 mm tools. Wafer bow and flatness, wafer thermal expansion, loading and wavelength affects, new chamber designs, and other impacts will fundamentally alter the physics of patterning, deposition, etch, planarization, and other processes. Each of the nearly 1,000 steps required by today’s 300 mm processes will require ground-up scientific analysis and reengineering. Data processing and metrology requirements at the larger wafers will slow cycle time, and yield will be profoundly affected.

The debate about the economic justification and total cost for a 450 mm transition included questions on funding models. Equipment suppliers claimed the 300 mm transition benefitted only chip makers, and the supply chain has yet to recoup their R&D investment from the last wafer scale-up. SEMI estimated the R&D for the 300 mm transition at over $22 billion2. As early as 2005, SEMI asserted that industry was facing an R&D funding gap that threatened the continuation of Moore’s Law-related cost reductions. In 2006, SEMI claimed that “Before a successful transition to 450 mm can be conceived, the industry will need to fund the investment in a way that provides a reasonable return to the supply infrastructure whose participation will be required. At this time, it is not clear that there is a benefit to the industry that outweighs the increased cost of the equipment required.”

While the industry debated, the original 2012 target for 450 mm transition slipped away. The latest ITRS roadmap on semiconductor technology has pushed out the arrival of a viable 450mm tool set to 2014, with volume production expected 4-6 years later. With lithography roadmaps uncertain, new transistor designs and 3D IC in planning stages, and the industry still reeling from the worst downturn in history, firm targets for a wafer size transition seem elusive as ever. Yet, significant progress has been made and most observers feel the issue is now less a matter of if, than when. And, while funding a transition remains a difficult challenge, new funding models are starting to emerge, albeit behind closed doors.

Improving Industry Readiness

ISMI has been active in supporting 450 mm wafer development and material handling requirements through a number of programs and demonstration projects. They have created a “wafer bank” to lend test wafers to equipment developers, developed an interoperability test bed to support automation and material handling demonstrations, and created a set of equipment performance and EHS documents. Considerable work has been done on prototype testing of 450 mm factory integration equipment, including lab testing focused on 12 mm pitch FOUPs, MACs and load ports. They have evaluated multiple personal guided vehicles (PGVs) for wafer handling and verified pallet requirements for MAC shipping. Later this year, ISMI will demonstrate automated materials handling system (AMHS) components including new 450 mm stockers and overhead hoist transport systems.

ISMI has also created preliminary ISMI 450mm vacuum platform guidelines and published EQP software guidelines, but final evaluation of the feasibility of vacuum platform standardization won’t begin until 2013, according to ISMI.

SEMI International Standards development has also been progressing to enable pilot development and provide a platform for future development work. In July, SEMI M76 was adopted by the industry to detail test wafer requirements for various applications such as lithography, patterning, thermal processes, films and deposition. Also passed in July was SEMI standard E156 that relates to the storage and transport of 450 mm wafer carriers in a semiconductor factory.

These material handling demonstration, standards and guidelines activities are necessary and important work for the eventual development of a 450 mm pilot system, but critical process technology analysis has not begun. While wafer polishing processes have improved and particle levels have been dramatically reduced, wafer quality remains below the threshold for process research and development. Surface metals metrology is still in development and inspection equipment is not yet online. While ISMI claims there are no technical “shows stoppers” the fact remains the hard scientific work has yet begun.

Funding the Future?

In an attempt to begin to address the difficult 450 mm funding questions, in July ISMI acknowledged that the historical financial risk model for wafer- size transition funding is no longer relevant and that “risk-sharing with tool suppliers is expected to realize the 450mm transition.” ISMI’s planned mechanism is some type of cost sharing to lower the financial risk for tool and technology suppliers.

ISMI has announced they are prepared to engage in discussions and negotiations to support funding of R&D development, but how this approach will roll out across the supply chain is vague. Presumably ISMI will enter into a case-by-case funding approach with every supplier of every key tool set, or some subset of suppliers based on yet-to-be determined considerations. While much is still not known about scope, scale and strategy of this funding approach, it is a departure from traditional consortia funding and roadmap development models.

Keeping pace with Moore’s Law and the dramatic cost reductions that it has enabled has been the key driver behind the most important economic marvel of our time — the continued growth and proliferation of electronic goods and services. Fundamental to this growth has been highly-refined collaborative processes such as the ITRS and SEMI standards, and industry consortia to finance pre-competitive R&D. How these models and mechanisms for collaboration will operate in the coming years to support a transition to 450 mm wafers is an unfolding story yet to be fully revealed.

Note: This article was previously published by Synopsys in Wafer Focus.