A 5.4 GHz digitally controlled oscillator (DCO) has been implemented in a 90-nm CMOS process. It has three different frequency control words, coarse, medium, and fine. The coarse control bank uses MIM capacitors and differential MOS switches. The other banks use MOS varactors. The phase noise was measured at the output of an on-chip divide by 2 circuit. It is -132 dBc/Hz at 3 MHz offset from the 2.7 GHz carrier. The power consumption of the oscillator is 7.8 mW from a 1.2 V supply, resulting in a figure of merit (FOM) of 182 dB. The worst case FOM is 180 dB over the 21% tuning range.

@misc{88e867d8-f1a8-4568-a8b4-684acd535a9f,
abstract = {A 5.4 GHz digitally controlled oscillator (DCO) has been implemented in a 90-nm CMOS process. It has three different frequency control words, coarse, medium, and fine. The coarse control bank uses MIM capacitors and differential MOS switches. The other banks use MOS varactors. The phase noise was measured at the output of an on-chip divide by 2 circuit. It is -132 dBc/Hz at 3 MHz offset from the 2.7 GHz carrier. The power consumption of the oscillator is 7.8 mW from a 1.2 V supply, resulting in a figure of merit (FOM) of 182 dB. The worst case FOM is 180 dB over the 21% tuning range.},
author = {Lu, Ping and Sjöland, Henrik},
keyword = {DCO,VCO,Oscillator,ADPLL,RF,CMOS},
language = {eng},
pages = {4},
title = {A 5.4GHz 90-nm CMOS digitally controlled LC oscillator with 21% tuning range, 1.1MHz resolution, and 180dB FOM},
year = {2008},
}