posted: January 30, 2018 at 3:00am version: 1.5 revision: 93
Update at Mon Jan 29 13:26:39 EST 2018 by tim
Changed behavior of the "lvs" script so that the setup file can be specified as "nosetup" if the "lvs" command is being called interactively from a terminal or as part of a larger script where setup commands have been issued prior to running the "lvs" script. Similarly, the log file can be specified as "nolog" to prevent any log file from being generated.

posted: January 27, 2018 at 3:00am version: 1.5 revision: 92
Update at Fri Jan 26 11:58:05 EST 2018 by tim
Corrected a number of function returns, mainly to avoid compile- time warnings and errors. Removed the "-lazy" option from the Tcl load command, which is not needed when the stubs libraries are compiled in correctly, and which causes issues on some systems (e.g., Mac OS). Thanks to Matt Guthaus for the patch.

posted: December 17, 2017 at 3:00am version: 1.5 revision: 91
Corrected an issue in which netgen would attempt to find a file from a ".include" line by trying alternate extensions. This should be discouraged, as it happened that a file included "name.defparams", a file that didn't exist, and instead of calling out the missing file, it recast it to "name.spice" and caused it to drop into an infinite loop. Oops.Also:
Update at Thu Dec 14 21:50:32 EST 2017 by timAlso:
Merge branch 'master' into work

posted: October 11, 2017 at 3:00am version: 1.5 revision: 88
Corrected two errors in the serial combine function, one which misses a device if it has been already moved due to earlier merging in the serial combine routine, and runs off the end of the list; the other if the pin check routine falls on the last device in the list, leading to an incorrect check for a record where there is only a NULL.Also:
Update at Tue Oct 10 22:25:49 EDT 2017 by timAlso:
Merge branch 'master' into work

posted: August 25, 2017 at 3:00am version: 1.5 revision: 87
Prevented a crash condition in the error case in which ports are unordered at the time of reaching reorderpins(). Pins will be ordered arbitrarily (in the order of appearance in the linked list), but netgen will not crash.Also:
Update at Thu Aug 24 09:51:44 EDT 2017 by timAlso:
Merge branch 'master' into work

posted: June 21, 2017 at 3:00am version: 1.5 revision: 83
Implemented better black-box handling. Netlist with "stub" entries for subcircuits (.subckt ... .ends pair with cellname and pin names and pin order, but no contents) are automatically treated as black- box circuits if found and if the "-blackbox" option is passed to the "lvs" (scripted) command. The "equate pins" command can be used outside of a comparison to force two circuits (black-box or otherwise) to be matched by pin name (if not a black-box circuit, then this is a provisional name match, as a circuit comparison will order based on connectivity first, not pin names). So two sets of black-box circuit libraries can be used as long as their pin names match. One hack added to ignore the "!" at the end of global names when comparing pin names for matching. Otherwise, pin names must compare by case-insensitive string match.Also:
Update at Tue Jun 20 22:55:24 EDT 2017 by timAlso:
Merge branch 'master' into work

posted: June 20, 2017 at 3:00am version: 1.5 revision: 82
Added tilde expansion handling for .INCLUDE statements to the SPICE netlist read routine.Also:
Update at Mon Jun 19 12:39:00 EDT 2017 by timAlso:
Merge branch 'master' into workAlso:
New command option "model blackbox on|off" makes "readnet spice" treat empty subcircuits as blackbox cells automatically without requiring specific callse to "model blackbox" for each. Enabled in LVS script by giving option "-blackbox" at the end of the LVS command.Also:
Fixed the "cells -all" command so that it now matches the documentation, and behaves as intended, which is that "-all" is not a standalone option but is itself an optional qualifier to the "cells " command. So the options are "cells " and "cells -all ".Also:
Finally reworked "cells" command behavior into something consistent.Also:
Corrected the "property parallel none" command option so that it gets applied properly to all existing cells (as well as all future cells, but normally the former is applicable in a setup file for LVS).

posted: May 16, 2017 at 3:00am version: 1.5 revision: 80
Corrected the same error as a few commits back that causes a message about property errors to show up, not due to property errors, but due to proxy pins being inserted in the middle of a device record. However, the first one was fixed for the case of proxy pins being added to circuit 1, but the same fix was not made for the opposite case of proxy pins being added to circuit 2. This commit corrects that omission.Also:
Update at Mon May 15 16:31:00 EDT 2017 by timAlso:
Merge branch 'master' into work

posted: May 9, 2017 at 3:00am version: 1.5 revision: 79
Corrected rare case where a cell that is flattened is the first instance in a cell, and is empty, and causes the cell contents to be nulled out.Also:
Update at Mon May 8 20:56:58 EDT 2017 by timAlso:
Merge branch 'master' into workAlso:
Removed old comment from code referring to the development state.

posted: May 6, 2017 at 3:00am version: 1.5 revision: 78
Corrected error in combining property records of serial devices.Also:
Update at Fri May 5 17:36:29 EDT 2017 by timAlso:
Merge branch 'master' into workAlso:
Corrected an error placing proxy pins after the first pin of the first object if the (presumably top-level) cell has no pins (top-level cells not in a subcircuit definition satisfy this condition).

posted: April 26, 2017 at 3:00am version: 1.5 revision: 77
Corrected the .gitignore file, which was apparently missed when version 1.5 was first created in git.Also:
Update at Tue Apr 25 08:47:57 EDT 2017 by timAlso:
Merge branch 'master' into work

posted: March 7, 2017 at 3:00am version: 1.5 revision: 76
A few corrections to the JSON format output.Also:
Update at Mon Mar 6 14:01:25 EST 2017 by timAlso:
Merge branch 'master' into work

posted: February 28, 2017 at 3:00am version: 1.5 revision: 74
Corrected an error in the property match subroutine that was failing to stop at the end of an instance record without properties, leading to strange errors where netgen declares "There were property errors" but does not print any errors (because there aren't any).Also:
Update at Mon Feb 27 09:36:52 EST 2017 by timAlso:
Merge branch 'master' into work

posted: February 9, 2017 at 3:00am version: 1.5 revision: 73
Corrected an error where snprintf() was not used when printing formatted side-by-side output, causing a crash for names that exceed the 40-column limit.Also:
Update at Wed Feb 8 15:16:59 EST 2017 by timAlso:
Merge branch 'master' into work

posted: January 10, 2017 at 3:00am version: 1.5 revision: 72
Finished implementing the Tcl list output format, and added a routine to convert the list output format to a JSON output file, for easy readback, parsing, and display using python.Also:
Update at Mon Jan 9 12:52:59 EST 2017 by timAlso:
Merge branch 'master' into workAlso:
Removed backup file for netgen.tcl.in, and made corrections for the output JSON format, which was incorrect when some entries were empty.

posted: January 8, 2017 at 3:00am version: 1.5 revision: 71
Fixed a bug in the combine routine that causes a segfault; added preliminary support for a Tcl list output format.Also:
Update at Sat Jan 7 06:57:25 EST 2017 by timAlso:
Merge branch 'master' into work

posted: December 8, 2016 at 3:00am version: 1.5 revision: 69
Added more handling of serial/parallel device networks, including making any subcircuit serializable by using the new command option "property (device) serial|parallel enable|disable". Note that as of this commit, serial device detection is enabled but serial networks are not collapsed for matching, which will tend to lead to property errors in serial devices until this code is added, which should be in a day or two.Also:
Update at Wed Dec 7 15:01:55 EST 2016 by timAlso:
Merge branch 'master' into workAlso:
Several errors in the serial combination code fixed, and then the serial combination routine was disabled so as not to post a non-working version, since the parallel/serial property networks are not analyzed. This should be completed soon.Also:
Fixed an error that prevented 'circuit1' and 'circuit2' from being used in the general cell name format as advertised (in fact caused a segfault), without which all setup file have to be very circuit- specific.

posted: November 12, 2016 at 3:00am version: 1.5 revision: 68
Corrected an error in which property types were not promoted if an instance property did not match the cell property type, as long as the cell property types of the two compared cells matched. Along with a recent change that left "M" as a type double during SPICE netlist read-in, this caused "M" mismatches to be ignored, because the double value was ignored and the integer value was always zero.Also:
Update at Fri Nov 11 09:52:18 EST 2016 by timAlso:
Merge branch 'master' into work

posted: October 27, 2016 at 3:00am version: 1.5 revision: 67
Disabled the newest unfinished experimental code, which was not supposed to have been pushed to git yet.Also:
Update at Wed Oct 26 21:21:09 EDT 2016 by timAlso:
Merge branch 'master' into work

posted: October 26, 2016 at 3:00am version: 1.5 revision: 66
Changed behavior of property mismatch reporting. This is to help avoid the problem where non-critical properties cause devices not to match, resulting in apparent mismatches of matched devices. The current behavior now prints a statement about each device. However, the result is still somewhat ambiguous.Also:
Update at Tue Oct 25 11:29:17 EDT 2016 by timAlso:
Merge branch 'master' into work

posted: October 25, 2016 at 3:00am version: 1.5 revision: 65
Removed all instances of macro INLINE, as this is showing up now as failing on certain compilers. This undoubtedly reflects some change in gcc or the OS setup, but since modern compilers should be able to figure out for themselves when to inline a subroutine (or not), the inline hint is somewhat arcane and unnecessary.Also:
Update at Mon Oct 24 13:43:29 EDT 2016 by timAlso:
Merge branch 'master' into work

posted: October 19, 2016 at 3:00am version: 1.5 revision: 64
Corrected error in property matching, especially to handle problems with missing properties in instances that prevent matching (underlines need to add the code to apply defaults from the object where these occur).Also:
Update at Tue Oct 18 09:59:36 EDT 2016 by timAlso:
Merge branch 'master' into workAlso:
Corrected error that fails to remove property records of any instance that is deleted because it has been ignored with the 'ignore' command.Also:
Implemented command option 'ignore shorted', same syntax as 'ignore class', but removes instances of the specified class whose pins are shorted together. Currently requires that all pins must be shorted together.

posted: October 18, 2016 at 3:00am version: 1.5 revision: 63
Corrected parsing of resistor and capacitor values to include CDL-style expressions as well as numerical values.Also:
Update at Mon Oct 17 17:47:55 EDT 2016 by timAlso:
Merge branch 'master' into work

posted: September 10, 2016 at 3:00am version: 1.5 revision: 61
(1) Corrected output of "nodes" command, which was not handling the leading '/' of pin names and therefore failing to print anything; (2) Corrected 'addproxies', which was ending abruptly at the end of a circuit's object list, such that if an instance needing proxy pins added was the last object in the circuit, it would not get the proxy pins added, and therefore would fail LVS.Also:
Update at Fri Sep 9 09:47:45 EDT 2016 by timAlso:
Merge branch 'master' into work

posted: September 9, 2016 at 3:00am version: 1.5 revision: 60
Corrected error in tclnetgen for command option "property default", which did not return from the command after processing the "default" option.Also:
Update at Thu Sep 8 22:08:20 EDT 2016 by timAlso:
Merge branch 'master' into work

posted: July 22, 2016 at 3:00am version: 1.5 revision: 59
Updated configure script to extract the paths for the Tcl and Tk lib and include files, so that subsequent checks for those files are not disjoint from the contents of tclConfig.sh and tkConfig.sh.Also:
Update at Thu Jul 21 11:24:27 EDT 2016 by timAlso:
Merge branch 'master' into work

posted: July 17, 2016 at 3:00am version: 1.5 revision: 58
Corrected use of strdup instead of strsave, which causes a different malloc() to be called and can cause crashes.Also:
Update at Sat Jul 16 13:52:34 EDT 2016 by timAlso:
Merge branch 'master' into workAlso:
Added command option "property default" which acts similarly to "permute default" by (1) handling the usual case for MOSFETs (resistors and adding in parallel not yet implemented), and (2) being done automatically when no setup script is specified.Also:
Implemented critical property combining in parallel for devices such as resistors.Also:
Added resistors and inductors to the list of devices whose merging properties are defined by "property default".

posted: July 12, 2016 at 3:00am version: 1.5 revision: 57
Finished basic implementation of matching device properties to include calculations of effective width due to the addition of width of multiple device instances in parallel. The original behavior of splitting all "M=" devices into individual instances has been effectively inverted, instead combining all parallel devices of the same class into one, with multiple property records for devices with non-matching properties (e.g., width, length, etc.). Property matching combines devices with different "critical properties" (e.g., FET gate width) if these are defined in the setup using the "property merge" command.Also:
Update at Mon Jul 11 08:49:52 EDT 2016 by timAlso:
Merge branch 'master' into workAlso:
Removed the deprecated file flatten.c.bak.

posted: June 24, 2016 at 3:00am version: 1.5 revision: 56
Overhaul of the hash table method. Original method used global variables to iterate over hash table contents. This led to the inability to nest hash table iterators. Fixed by defining a wrapper structure that holds the actual hash table plus the size and iterator indexes. Not only does this solve the nesting problem, but it also avoids the need to pass the hash table size on every call, and that reduces the number of ways a hash table subroutine can go wrong (e.g., cannot access the table out of bounds simply by passing a size that is larger than was used to initialize the table).Also:
Update at Thu Jun 23 10:18:47 EDT 2016 by timAlso:
Merge branch 'master' into workAlso:
Extended the prematching phase to include matching of devices based on properties that can be traded with number of devices, such as MOSFET width, by merging. This initial implementation is somewhat limited, only dealing with properties that merge by summing. Only devices that do not match at all in the other circuit will be considered for merging. The feature includes a command option "property ... merge ..." that allows control over which devices can and cannot be merged.

posted: May 20, 2016 at 3:00am version: 1.5 revision: 55
Corrected a previously-working output of a list of cells with property errors at the end of LVS. The result of "verify matching" got overwritten by the result from matching pins, erasing the information about a cell having property errors.Also:
Update at Thu May 19 16:46:32 EDT 2016 by timAlso:
Merge branch 'master' into work

posted: May 17, 2016 at 3:00am version: 1.5 revision: 53
Fairly extensive modifications that allow for handling of, and comparisons between, duplicate cells (cells with the same netlist that may have more than one name in a circuit, or which for some reason appear with the same name more than once in a netlist). Added more checks to the list prematching, which prevents various troubles with cells having a mismatched hierarchy. Added a command option to "flatten class" to flatten instances only within a specific cell. Corrected one error in the pin matching routine. Added a check in the pin matching routine to look for pins that have been found to be no-connects after cleaning up the pin lists of the children of that cell.Also:
Update at Mon May 16 10:55:53 EDT 2016 by timAlso:
Merge branch 'master' into workAlso:
Added additional diagnostic statements.Also:
Removed files that should not be in the git repositoryAlso:
Updated the .gitignore file to avoid the .log and .so files.Also:
Corrected the "property tolerance" command in tclnetgen, and cleaned up some of the property matching output.

posted: May 6, 2016 at 3:00am version: 1.5 revision: 52
Corrected a line in FlattenUnmatched that would cause an infinite loop if attempting to flatten an empty cell.Also:
Update at Thu May 5 10:12:58 EDT 2016 by timAlso:
Merge branch 'master' into workAlso:
Fixed a potential crash condition in uniquepins().

posted: March 21, 2016 at 3:00am version: 1.5 revision: 51
Corrected handling of name matching so that if the setup file equates class "a" in circuit 1 with class "b" in circuit2, and if circuit 1 has a class called "b" and/or circuit 2 has a class called "a", then both classes are given a new hash to avoid conflicts with the (presumably) unrelated cells of the same name in the other netlist.Also:
Update at Sun Mar 20 11:44:06 EDT 2016 by timAlso:
Merge branch 'master' into workAlso:
Additional measure to ensure that name altered to avoid cross- netlist naming conflicts does not also cause a naming conflict.Also:
Corrected an additional error that let PropertyMatch() be called with arguments swapped with respect to Circuit1, Circuit2 definitions, which are fixed in PropertyMatch().Also:
Corrected an error causing a segfault on property mismatches where one cell is missing properties (failed to check for a NULL value before checking values internal to the structure that was NULL).

posted: March 17, 2016 at 3:00am version: 1.5 revision: 50
Corrected the device pre-matching routine to not segfault when a cell has zero instances in one of the surveyed cells.Also:
Update at Wed Mar 16 12:06:38 EDT 2016 by timAlso:
Merge branch 'master' into work

posted: December 8, 2015 at 3:00am version: 1.5 revision: 49
Corrected calls from the non-Tcl/Tk version to routines which have been modified in the Tcl/Tk version to take an additional argument for the file number. In the non-Tcl/Tk-compatibility mode, netgen should operate in a backwards-compatibility mode with filenum = -1.Also:
Update at Mon Dec 7 15:01:41 EST 2015 by timAlso:
Merge branch 'master' into work

posted: April 30, 2015 at 3:00am version: 1.5 revision: 39
Corrected error with .ext and .sim file reading, in which the (indirect) match and hash functions were undefined.Also:
Update at Wed Apr 29 17:08:52 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
Oops, somehow managed to run qflow in the netgen source directory and it dumped some files there. . .

posted: April 18, 2015 at 3:00am version: 1.5 revision: 38
Rewrote the prematch algorithm to accept decomposing a subcircuit if the resulting match is closer than the original match (as opposed to not allowing it to create a mismatch in the opposite direction, even if it's a very small mismatch compared to the original). Doing this led me to discover, more or less by accident, that the original prematch "step 1" of decomposing any subcircuit having no match in the other netlist is subsumed by "step 2", which is better able to determine when decomposing a subcircuit isn't going to be any help at all. This results in fewer circuits being decomposed, and therefore a cleaner/faster compare at the topmost level.Also:
Update at Fri Apr 17 10:08:50 EDT 2015 by timAlso:
Merge branch 'master' into work

posted: April 10, 2015 at 3:00am version: 1.5 revision: 37
Modified netgen.tcl to add return characters back into lines read from setup.tcl, or else it does not properly parse multi-line commands. Run commands by "uplevel 1", so that they run in the top-level scope, as they would from the Tcl command line. This move brings up the issue that "global" cannot be used without prefixing with "netgen::", which is stated plainly in the netgen output but should really be changed to make the problem go away, by not having a "global" command in netgen. Also: Corrected an error in MatchPins that would miscount pins when ignoring a pin disconnected in both netlists, generally causing a panic in memory allocation down the road.Also:
Update at Thu Apr 9 20:09:00 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
Revised the setup file evaluation to operate within the netgen namespace, to avoid gotchas with the command "global", on advice from Risto. Seems to work properly.

posted: April 9, 2015 at 3:00am version: 1.5 revision: 36
Binary input detector. . .Also:
Update at Wed Apr 8 09:31:29 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
Rewrote parts of the spice parser and expression parser until they pass the "/dev/urandom" test; the parser is now quite robust. Kept the code that stops on apparent binary input files, as it is more practical to stop processing rather than to assume that there is a netlist in there somewhere. . .Also:
Modified setup file parsing to evaluate one line at a time, and catch errors and report warnings about such errors without causing a halt to the LVS process. This replaces the specific "(ingored)" messages for commands like "permute", which now return error results. The consequences of this change are (1) you can type complete gibberish into the setup file, like "Hey, this is an error", and it will just spit out a warning; (2) you can't do loops, define procedures, etc., within the setup file, as it is now restricted to one command per line. However, you can get around this by adding a one-line "source " to parse a file with multi-line commands or structures.Also:
On a tip from Risto, modifed the setup file parsing using "info complete" to allow the parser to handle arbitrary Tcl scripts without complaint.

posted: April 8, 2015 at 3:00am version: 1.5 revision: 35
Corrected the expression parsing, which was incorrectly freeing the memory for a string that was never allocated, if the expression reduces to a single string.Also:
Update at Tue Apr 7 08:30:19 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
Corrected the property error reporting to properly report when two properties cannot be matched because they cannot be resolved to the same type (e.g., both type double, integer, or string), and to avoid promoting a type that is not really promotable (e.g., turning a fractional value into an integer).Also:
Corrected an error in inductor parsing that caused the inductor value to be taken as a model name, for inductors without models. Added additional support for other minor non-physical SPICE types such as voltage and current sources. They are modeled as black boxes, meaning that they only match pins but do not compare properties unless the properties are specifically called out in the setup file.Also:
Added inductors to the list of devices with default permutations.

posted: April 7, 2015 at 3:00am version: 1.5 revision: 34
Corrected parsing of numbers and expressions to disambiguate the use of +,-, and "e" as an exponent vs. use as arithmetic and variable names.Also:
Update at Mon Apr 6 20:18:45 EDT 2015 by timAlso:
Merge branch 'master' into work

posted: April 6, 2015 at 3:00am version: 1.5 revision: 33
Start of coding for handling of device combinations. Added command "combine", similar to "permute", with defaults defined, and the capability to override from the setup file. Currently has no function other than to set flags in the device record.Also:
Update at Sun Apr 5 21:04:52 EDT 2015 by timAlso:
Merge branch 'master' into work

posted: April 5, 2015 at 3:00am version: 1.5 revision: 32
Added a new set of subroutines to handle the arithmetic expressions that appear in CDL netlists, taking ".PARAM" statements for global values, plus substituting in the value of properties passed to instances from a subcircuit. It does not yet detect multiple uses of subcircuits with different sets of parameters. However, the code as it is now will handle most simple applications of parameter passing.Also:
Update at Sat Apr 4 21:44:08 EDT 2015 by timAlso:
Merge branch 'master' into work

posted: April 4, 2015 at 3:00am version: 1.5 revision: 31
Corrected error in property matching that would break on the first instance property not listed in the cell master, and ignore the rest of the properties. Added a hash table for handling parameters in spice files, but this feature is preliminary, and currently does nothing of interest.Also:
Update at Fri Apr 3 09:36:52 EDT 2015 by timAlso:
Merge branch 'master' into work

posted: April 3, 2015 at 3:00am version: 1.5 revision: 30
Fixed a number of errors related to handling the "permute" command, and corrected the common cellname parsing to properly handle the "*" wildcard.Also:
Update at Thu Apr 2 08:19:36 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
Corrected property matching so that (1) if one cell has properties that are not required and the other cell has no properties, no error will be raised, and (2) failure to match due to missing (required) properties is posted as a separate error message.Also:
Slight correction to print the instance name rather than the cell name of the instance missing properties; otherwise it's difficult to track down the offending entry in the netlist.Also:
Finally got around to cleaning up the "property" command. Command now works correctly with wildcards, like the other commands. Several parsing errors were found and corrected. No attempt yet to extend the command definition beyond what it was; mainly correcting existing errors in the established syntax.Also:
Corrected log output so that the final tally of property mismatched devices gets copied to the log. Otherwise the log can seem to indicate that everything matched perfectly, when some cells in the hierarchy had property mismatches.Also:
Corrected erroneous code in "permute forget", referencing a freed pointer.Also:
Corrected "property tolerance", which was setting an interpreter error result when given a floating-point value.

posted: April 2, 2015 at 3:00am version: 1.5 revision: 29
Implemented automorphism resolution by pin matching and property matching. If automorphic groups connect to pins, then the pins are compared by name and the name matching used to sort the automorphisms into unique sets. Then, properties are checked within each automorphic group, and the groups assigned new hash values based on equal numbers of components with matching properties in each circuit. Another match iteration is run following each sort. Remaining automorphic groups are then truly ambiguous, and are resolved arbitrarily.Also:
Update at Wed Apr 1 11:23:22 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
An attempt to clean up the output, preventing tabs from being dropped in the log file, putting the more useful node mismatch in front of the element mismatch, and changing names of various things that seem kind of arcane: element -> device, node -> net, cell -> circuit, automorphism -> symmetry, legal -> matching, illegal -> nonmatching. This should make the output a bit more human-comprehensible.Also:
Corrected the "permute" command, which was horribly broken. Implemented wildcard filenum on the "permute" command, untested, with hooks in place to extend the wildcard handling to most of the other commands that use the common filename syntax.Also:
Corrected a few bugs per bugzilla update on bug 10, and added handling of wildcard file number for most of the routines (but not yet including the "property" command).Also:
Corrected the filenumber return value of the common cellname parser in the case of a single top-level name. Corrected the error setting for "permute" commands that act on non-existent devices. Cleaned up another few minor aspects of the output formatting.

posted: April 1, 2015 at 3:00am version: 1.5 revision: 28
Corrected another missing check for a NULL value that causes a segfault when subcircuits have no pins.Also:
Update at Tue Mar 31 08:03:46 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
Missing reset of "haspins" in SPICE file read, caused only the first cell without pins to be seen to be treated as such.

posted: March 31, 2015 at 3:00am version: 1.5 revision: 27
Corrected an error that prevents the use of a comment line ('*') in the middle of a series of continuation lines ('+') in a SPICE netlist.Also:
Update at Mon Mar 30 13:50:01 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
Corrected a place where a name was printed just after freeing the memory for it.

posted: March 29, 2015 at 3:00am version: 1.5 revision: 25
Corrected crash condition caused by lack of a check for a null value in the pre-match subroutine. Also corrected the unique pins subroutine.Also:
Update at Sat Mar 28 21:04:00 EDT 2015 by timAlso:
Merge branch 'master' into work

posted: March 27, 2015 at 3:00am version: 1.5 revision: 24
Reworked the "valid_cellname" parse routine (again) so that the names "-circuit1" and "-circuit2" work under all conditions (previously were parsed only when used as individual items, not part of a list pair). Also stopped setting CurrentCell to NULL after ReadSpice(), which allows "-current" to be used as well, after reading in a cell. Need some kind of command or command option to specifically set the current cell, though.Also:
Update at Thu Mar 26 08:36:18 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
Added more to the pre-match survey, allowing cells that have differing numbers of elements in each circuit to be flattened if the matchup of elements will be improved by the flattening. (Still to do: improve matching based on parallel/serial combinations.)Also:
Added another element-matching routine to look for unmatched resistors of zero length or zero value, and remove them from the netlist while combining the endpoint nodes. This resolves problems where one netlist breaks up nets with fake resistors but the other one doesn't. In order to match zero-value devices, it is the responsibility of the end user to ensure that both netlists define them.

posted: March 26, 2015 at 3:00am version: 1.5 revision: 23
Corrected the case of proxy pins for subcircuits which truly have no pins. This is a bit of a hack, but appears to work correctly now in all cases. Cleaned up the IsPort() and IsGlobal() macros at the same time.Also:
Update at Wed Mar 25 20:43:09 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
Created a command option "compare assign " that will assign Circuit1 and Circuit2, without doing anything else, so that the setup file and other commands prior to running a comparison can make use of the "-circuit1" and "-circuit2" names to refer to the two cells.

posted: March 25, 2015 at 3:00am version: 1.5 revision: 22
Corrected an egregious error from the last check-in where an accidental "break" got inserted in the "CleanupPins" subroutine, causing complete corruption of the netlists when "reorderpins" was called.Also:
Update at Tue Mar 24 09:41:28 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
Added code to handle the rare case of a cell that has no ports (because it's connections to the parent cell are all through global nodes).Also:
Reworked the compare & flatten routine so that it is in its own subroutine and not part of CreateTwoLists(). With its own hash table and counts of matching and non-matching instances, it's in a better position to do more complicated matching, combining of devices, etc.

posted: March 24, 2015 at 3:00am version: 1.5 revision: 21
Modified the handling of pins such that netlists do not need to be flattened for the simple reason that their pin lists cannot be matched; netgen now adds unconnected dummy nodes to both sides as necessary to make them match. This makes the hierarchical output much cleaner.Also:
Update at Mon Mar 23 13:19:42 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
Added the number of instances flattend when reporting on the flattening of unmatched subcells.

posted: March 21, 2015 at 3:00am version: 1.5 revision: 20
Instituted two new procedures: (1) On first comparison, where number of elements are mismatching, a check is made for unmatched subcircuits that can be flattened. There is some issue where only a portion of non-matching circuits are flattened, requiring several passes, but the feature still works. (2) On mismatch of pins due to extra duplicate or unconnected pins on one circuit, the circuits are NOT flattened, but retained with the circuit lacking the extra nodes having those pins replaced with dummy equivalents. This may need more work and is considered tentative at the moment.Also:
Update at Fri Mar 20 11:08:26 EDT 2015 by timAlso:
Merge branch 'master' into work

posted: March 19, 2015 at 3:00am version: 1.5 revision: 19
Corrected the property check to avoid crashing when a property record exists but contains no properties. It is not yet clear to me how such a record got made, but for now, treating it the same way as having no properties seems reasonable.Also:
Update at Wed Mar 18 08:31:41 EDT 2015 by timAlso:
Merge branch 'master' into work

posted: March 18, 2015 at 3:00am version: 1.5 revision: 18
Fixed SPICE read-in to handle the case where a "+" continuation line is followed by nothing but whitespace before the next end-of-line. Previously, the end-of-line was being ignored in this case.Also:
Update at Tue Mar 17 20:46:42 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
Encountered a weird error with indexing from Tcl, corrected with an ugly hack. Pin matching during hierarchical comparison is now working again. Cleaned up a few other things, such as cell names not being printed in the status message from "equate pins".

posted: March 16, 2015 at 3:00am version: 1.5 revision: 17
Made a few corrections that prevent segfaults when encountering and attempting to match cells with different numbers of pins.Also:
Update at Sun Mar 15 19:02:27 EDT 2015 by timAlso:
Merge branch 'master' into work

posted: March 13, 2015 at 3:00am version: 1.5 revision: 15
Corrected output of "tolerance", where double and integer values were swapped, sent to the wrong Tcl command, and therefore mangled into unrecognizable numbers in the output. Also, the output was supposed to be lists of three values. . .Also:
Update at Thu Mar 12 16:12:37 EDT 2015 by timAlso:
Merge branch 'master' into work

posted: March 10, 2015 at 3:00am version: 1.5 revision: 14
Sweeping changes to the property handling. Previously property handling worked only under the assumption that the two netlists shared the underlying low-level devices. Since netlists are now kept entirely separate and devices are never shared, that assumption is now always false. So the property handling was changed to match between two instances of two cells, not two instances of the same cell. This revision should be considered highly unstable.Also:
Update at Mon Mar 9 17:31:50 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
Implemented one important form of the "equate class" command with pin lists.

posted: March 6, 2015 at 3:00am version: 1.5 revision: 13
Added error information dump when executing command-line arguments, in case of an error, so the error isn't just cast into the great void.Also:
Update at Thu Mar 5 19:35:55 EST 2015 by timAlso:
Merge branch 'master' into workAlso:
Additional correction to remove added whitespace introduced by the solution found on stackoverflow for parsing command-line arguments.Also:
Corrected part of the property check, which is to use a symmetric difference for the error computation.

posted: March 5, 2015 at 3:00am version: 1.5 revision: 12
Corrected readlib so that libraries read after a netlist read has already created placeholder cells will cause the instance pin names to be updated with the new pin names.Also:
Update at Wed Mar 4 11:08:38 EST 2015 by timAlso:
Merge branch 'master' into workAlso:
Implemented part of the "equate classes" command; have not finished the part that allows black-box pins to be named, ordered, and matched. Also cleaned up the few bits of code that spit warnings during the compile, so that the compile is clean.Also:
Corrected use of quotes when passed both to the console and to the terminal from the command line; for example: netgen lvs map9v3.spice "map9v3_synth.spice map9v3" The new method preserves quotes as a Tcl list in both cases.Also:
Added a command-line option "-batch" which acts like "-noconsole" except that it executes "quit" after executing the command-line arguments, so that it returns to the terminal prompt instead of the interpreter prompt.

posted: March 4, 2015 at 3:00am version: 1.5 revision: 11
First attempt at a "blackbox" method of specifying subcircuits, using the "readlib spice" command. See updated website command syntax description.Also:
Update at Tue Mar 3 20:48:07 EST 2015 by timAlso:
Merge branch 'master' into workAlso:
Made one change to set the circuit class appropriately for a black box component. Otherwise, "readlib" would not work right.

posted: March 3, 2015 at 3:00am version: 1.5 revision: 10
Corrected the common cellname syntax to include just a file number, as stated in the website command documentation. The file number by itself is equivalent to the top-level filename and top-level cell. Also added a command "canonical" to return a canonical form of a 2-item list {cellname file_number} for any valid cellname input. This is used by the "lvs" procedure to take the common cellname syntax as input. However, the common cellname syntax is only valid for files that have been read in, so the original restricted case of {filename cellname} is required when using the "lvs" command for a database that has not yet been read in. Also changed the "cells" command so that the option "all" is now "-all", to avoid confusion with a possible cell named "all"; and extended the command to include the option "-top" to print the names of top-level cells.Also:
Update at Mon Mar 2 09:22:13 EST 2015 by timAlso:
Merge branch 'master' into workAlso:
And once more corrected the cellname processing so that keywords "-circuit1", "-circuit2", and "-current" are parsed properly. It is possible that "-current" is not usable, but then, it's not a necessity.

posted: March 1, 2015 at 3:00am version: 1.5 revision: 9
Added quotes around "$@" in the netgen.sh script to preserve whitespace in arguments.Also:
Update at Sat Feb 28 12:21:08 EST 2015 by timAlso:
Merge branch 'master' into workAlso:
Fairly sweeping change to make all the commands consistent with respect to the naming of cells. See the updated documentation for syntax details. Due to the previous rampant inconsistency, some of the previous command options have a different syntax, but I have attempted to be as liberal as possible in the naming convention, so breaking of backwards compatibility is minimized.

posted: February 28, 2015 at 3:00am version: 1.5 revision: 8
Cleaned up handling of the console, such that batch mode works with the "-noconsole" switch, as it normally would. Redundant checks for the console were removed.Also:
Update at Fri Feb 27 13:18:12 EST 2015 by timAlso:
Merge branch 'master' into workAlso:
Removed some diagnostic text that got left behind. . .Also:
Corrected a bad error where the "ignore" command could delete anything in the object list between the cell being ignored and the next cell; sometimes this would include top-level nodes and other vitally important things.

posted: February 24, 2015 at 3:00am version: 1.5 revision: 7
Corrected behavior of the tkcon console, (1) so that on "quit", netgen calls the tkcon exit routine, so that tkcon will clean up after itself and save its history file, and (2) renaming the history file ".netgen_tkcon_hst", so that it will not interfere with the history file from other tools using tkcon.tcl.Also:
Update at Mon Feb 23 21:02:43 EST 2015 by timAlso:
Merge branch 'master' into work

posted: December 8, 2014 at 3:00am version: 1.5 revision: 6
Generate error message for cells that do not have pins, instead of crashing. Unfortunately, the database only lists pins (and properties), so that even though a cell with no pins (e.g., all connections are globals) is theoretically legal, it cannot be represented in netgen (possibly it could work to add a dummy property?).Also:
Update at Sun Dec 7 16:40:24 EST 2014 by timAlso:
Merge branch 'master' into workAlso:
Corrected the flattening routine so that it doesn't crash if attempting to flatten an empty cell.Also:
Modified the "global" command so that it (normally) acts on a file instead of a cell, although it can also be passed a cellname (in addition to the filename) to change the scope of specific signals in a specific cell (which was how "global" was implemented previously). In addition, any number of signal names to be made global can be put in the same command line.Also:
Modified the syntax of the "global" command so that it is similar to the "flatten" command syntax.

posted: December 3, 2014 at 3:00am version: 1.5 revision: 5
Revised .gitignore so that VERSION is included with a git clone commandAlso:
Update at Tue Dec 2 19:13:33 EST 2014 by timAlso:
Hmmm, that shouldn't happen. . .Also:
Playing tag with these files. . .Also:
Still playing file tag. . .

posted: December 2, 2014 at 3:00am version: 1.5 revision: 4
Corrected segfault if a nonexistent cell is passed to the "compare" command.Also:
Minor adjustment to last change, to print the name of the cell that was not found.Also:
Corrected error with the "lvs" script in which a badly formed regexp allows the first cell name containing the name of the cell being searched for to be returned as a match. Thanks to Risto Bell for the suggested patch.

posted: October 9, 2014 at 3:00am version: 1.5 revision: 3
Corrected an error that prevents the "nodes" command from working.Also:
Update at Wed Oct 8 08:10:54 EDT 2014 by timAlso:
Merge branch 'master' into workAlso:
Revising .gitignore. . . trying to figure out why files in ".gitignore" are being ignored by git (!)Also:
.gitignore is now workingAlso:
Doing that again; needed directory put in .gitignoreAlso:
And once again to fix .gitignore. . .Also:
Finally should have all the right files in the repository.Also:
Patched tkcon to be compatible with Tcl/Tk version 8.6.Also:
Correction to tkcon (fixing a typo!), otherwise bad things happen.

posted: September 24, 2014 at 3:00am version: 1.5 revision: 2
Corrected handling of cells that are used before being defined, which got broken by recent code changes.Also:
Update at Tue Sep 23 20:44:51 EDT 2014 by timAlso:
Merge branch 'master' into work

posted: September 10, 2016 at 3:00am version: 1.4 revision: 81
Same update as made to netgen-1.5 for using "load -lazy" with Tcl/Tk version 8.6 and up.Also:
Update at Fri Sep 9 11:09:06 EDT 2016 by timAlso:
Merge branch 'master' into work

posted: August 12, 2016 at 3:00am version: 1.4 revision: 80
Various small corrections to fix the compilation of the non-Tcl/Tk compile, which got broken some time ago.Also:
Update at Thu Aug 11 15:13:11 EDT 2016 by timAlso:
Merge branch 'master' into work

posted: July 22, 2016 at 3:00am version: 1.4 revision: 79
Updated configure script to extract the paths for the Tcl and Tk lib and include files, so that subsequent checks for those files are not disjoint from the contents of tclConfig.sh and tkConfig.sh.Also:
Update at Thu Jul 21 11:24:16 EDT 2016 by timAlso:
Merge branch 'master' into work

posted: September 30, 2015 at 3:00am version: 1.5 revision: 46
Corrected syntax information for the "equate" command, and added output text for the "flatten" command when called as a netgen command (as opposed to being called internally to LVS).Also:
Update at Tue Sep 29 21:51:04 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
Corrected an error in which renamed cells do not recalculate the classhash value based on the new name, so they will be treated as equal to the old cell despite the different name.Also:
Corrected an error in the name-matching of cells. This comparison would look for matching names from the "equate classes" command. However, it failed to do the reverse check, which is to make sure that if no forced match was found for a cell, but there was a name match, that the name-matched cell found is not being forcibly matched to something else.

posted: September 25, 2015 at 3:00am version: 1.5 revision: 45
Modified the name-checking when creating compare queues, such that matches explicitly called out in the setup file using "equate classes" will take precedence over same-name matching, instead of the other way around.Also:
Update at Thu Sep 24 08:26:50 EDT 2015 by timAlso:
Merge branch 'master' into work

posted: September 1, 2015 at 3:00am version: 1.5 revision: 44
Modified the detection of subcircuits such that it does not flag false errors about missing .ENDS statements on the top-level cell at EOF.Also:
Update at Mon Aug 31 09:34:21 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
Corrected an apparently non-functional call to feof(); random end-of-file will now properly terminate instead of re-reading the same line.

posted: August 21, 2015 at 3:00am version: 1.5 revision: 42
Corrected an infinite loop caused by lack of a return character after ".ends" (seems to be unique to that situation). Also, corrected a segfault caused by a cell definition containing only components that are uninstantiated subcircuits (recently added code makes references to CurrentCell without checking if it exists).Also:
Update at Thu Aug 20 22:13:39 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
Changed output behavior to print a "not checked" message when a cell has no elements and therefore cannot be checked. This message is only printed if "verify only" is used, preventing the message from being output several times. Switched from "stderr" to "stdout", so that it appears after "Result:" in the output, instead of before.

posted: August 10, 2015 at 3:00am version: 1.5 revision: 40
Added simple code to avoid printing confusing entry when one cell has no pins and the other does; the output was adding an entry attempting to match the "(no pins)" proxy pin.Also:
Did the same thing for the reverse case.

posted: May 18, 2015 at 3:00am version: 1.4 revision: 78
Make update; these files probably should be in .gitignore. . .Also:
Update at Sun May 17 21:14:46 EDT 2015 by timAlso:
Merge branch 'master' into work

posted: December 2, 2014 at 3:00am version: 1.4 revision: 77
Same change made to version 1.5, to prevent segmentation fault in the case of a bad cell name passed to the "compare" command.Also:
Update at Mon Dec 1 19:40:19 EST 2014 by timAlso:
Merge branch 'master' into workAlso:
Corrected error with the "lvs" script in which a badly formed regexp allows the first cell name containing the name of the cell being searched for to be returned as a match. Thanks to Risto Bell for the suggested patch.

posted: September 24, 2014 at 3:00am version: 1.4 revision: 75
Corrected handling of cells that are used before being defined, which got broken by recent code changes.Also:
Update at Tue Sep 23 20:44:40 EDT 2014 by timAlso:
Merge branch 'master' into work

Nov 24, 2007 at 4:55pm
Initial check-in of the development distribution. Added
automatic test of SPICE file format
for "readnet". Added true 4-port and 2-port devices. Added
read-in of device properties. Eliminated built-in device
classes; all device classes are generated on the fly as the
file is read in. For SPICE decks, the device model becomes
the device class, so that different device models are compared
independently. Added command option "equate classes" to force
equivalence between device classes in different circuits. Added
"lvs" command option to read in a file of class equivalences.

November 26, 2007 at 2:40am
Made some corrections to avoid confusing properties with nodes of
the same name, and to simplify the printout of "contents ".
Some simple tests indicate that LVS is working correctly with
subcircuit calls (spice X records).
Also:
Corrected an error that causes netgen to hang if "lvs" is given a
bad filename.

December 3, 2007 at 2:40am
Many, many changes. Implemented a set of internally-defined
device classes that encompasses pretty much everything (mostly
based on SPICE device model types), with some differences such as
a distinction between 3- and 4-terminal FETs, and similar items.
This internal type also encompasses the original "primitive"
flag, in that the internally-defined "subcircuit" device is
distinguished as the only non-primitive device. Completely
reworked device properties (again) such that only specific
properties (e.g., length, width, capacitor and resistor value)
are checked, and these are mapped into type double and kept
separate from other properties for quick comparison during LVS.
Reworked permutation to allow "standard" permutations of
source/drain on any device recognized internally as a FET, and
endpoints on internally-defined resistor classes, as well as
allowing (via script command) permuations to be defined on any
pins of any device class. Unfortunately, at the moment, the LVS
itself is hosed, as a result of one or more of the above changes.
The ability to translate between netlist formats is currently
rather limited, the most complete being the reading of SPICE
format files and the writing of "sim" format files. Diodes,
inductors, and transmission line models are not yet handled in
SPICE input.

December 10, 2007 at 2:40am
More changes. . . changed the "class equivalences" file passed to
the "lvs" procedure to a Tcl script setup file, in which class
equivalences would be merely one possibility. Permutations as
yet cannot be handled here because the permutations currently act
upon the netcmp database, and so must be run after the "compare"
command; whereas the setup file is executed prior to "compare".
Changed the way device properties are handled, so that properties
"of interest" to LVS are listed in the cell definition,
duplicated in a separate list in each instance, and converted to
type double (floating-point) where appropriate. The "properties
of interest" are defined at the time the cell definition is
created. There needs to be a method to add or subtract the
"properties of interest" from the cell definition.
Changed the way device models are handled, replacing the
"primitive" flag with a value indicating an internal model type.
Corrected read/write routines for sim and SPICE files, including
correct handling of device models and properties, and unmodeled
vs. modeled resistors and capacitors.
Also:
Changed the "permute" command such that it generates a list of
pins to permute, but the actual permuation is punted until the
element and node classes have been created. This allows the
"permute" command to be issued in the setup script.
Also:
Corrected property error checking, which now appears to be
correct, at least as verified by running on a few simple
examples. Added the capability to specify the degree to which
values are required to match (the "slop"), although for now this
is set to the default value of 1%, and there is no way to change
it (eventually a command will be added to manage property
comparison).
Also:
Updated the TO_DO list.
Also:
A couple more corrections to property checks, to make sure that
cells are considered matching if their classes are marked as
corresponding.
Also:
Added a few corrections for handling nested spice subcircuit
definitions. This allows LVS to run correctly on
hierarchically-defined files, although for now only the topmost
circuit is checked.

December 29, 2007 at 2:40am
Corrections that I failed to check into CVS last time. In
particular, the malloc/free routines are all now correctly
assigned to Tcl equivalents.

December 30, 2007 at 2:40am
Correction in property-checking code to prevent crashes when no
properties are specified (namely, on the last device in the
list).

December 31, 2007 at 2:40am
Basic hierarchical LVS has been implemented. However, a lot of
cleanup is needed with regard to the output it produces!

March 10, 2008 at 2:40am
Corrected an error that causes netgen to announce property errors
when there are no properties (this will happen on the last device
in the netlist, and shows up when the order of the last device is
different in the two netlists).

May 23, 2008 at 2:40am
2008-05-22 17:20 tim
Corrected the "package require -exact Tk" problem in tkcon.tcl,
which has already been corrected in the magic and IRSIM
distributions. The fix is necessary to run the Tcl/Tk-based
version with Tcl/Tk version 8.5.

July 7, 2008 at 2:40am
2008-07-06 11:24 tim
Added /usr/share/tcltk to the search path for Tcl and Tk in the
configure script, to conform to recent distributions of Ubuntu
Linux.

May 21, 2009 at 2:40am
2009-05-20 08:56 tim
Corrected an error found by Kan Chu in which a spice instance
name followed immediately by a continuation line is not parsed
correctly (the continuation line "+" is passed on as the first
pin connection).

July 28, 2009 at 2:40am
2009-07-27 06:47 tim
Corrected SPICE read-in of semiconductor resistors and
capacitors, which should not have a value in front of the model
name.
Also:
Additional correction, due to the fact that the syntax of the
semiconductor resistor and capacitor models in the standard SPICE
documentation conflicts with the example provided underneath. Is
the device value mandatory, optional, or prohibited?

August 28, 2010 at 2:40am
2010-08-27 18:01 tim
Numerous changes supporting hierarchical LVS and the ability to
read in files with subcells of the same name and keep them
distinct. Also, added the ability to compare subcells of files
from the "LVS" command, which avoids problems when one or both
files come from "library" type GDS files without a top-level
cell.

December 21, 2010 at 2:40am
2010-12-20 17:15 tim
Major changes to support hierarchical LVS. Finally encoded
routines to sort out port ordering between the schematic and
layout circuits. Many issues still to be resolved, but netgen
has now successfully run LVS on a magic-extracted hierarchical
SPICE deck vs. an xcircuit-generated (schematic capture)
hierarchical SPICE deck. Much hand-editing was required. Should
resolve these issues over the next several weeks.

December 24, 2010 at 2:40am
Updated compare routines to ignore disconnected nodes in either
circuit's netlist. Also: Modified the SPICE read routine to
rename instance pin references after read-in when the instance
was called before the cell was defined.

May 26, 2011 at 2:40am
Corrected an error that generated record 'x' into the output for all device types unknown to the .sim format (fallout from experimental handling of subcircuits in .sim).Also:
Correction to prevent segfaults on encountering unknown device models.

May 29, 2011 at 2:40am
Corrected a non-initialized variable which causes known model types such as "diode" in a spice file to be overwritten with a subcircuit class, causing confusion with the hierarchical LVS.Also:
Update at Sat May 28 06:19:36 PDT 2011 by timAlso:
Merge branch 'master' into work

May 30, 2011 at 2:40am
Updated netgen-1.4 to my most recent development fixes/additions, a number of which had not been committed.Also:
Update at Sun May 29 12:10:13 PDT 2011 by timAlso:
Merge branch 'master' into work

June 10, 2011 at 2:40am
Script files regenerated from sources. Changes in this commit are probably not meaningful.Also:
Update at Thu Jun 9 07:05:10 PDT 2011 by timAlso:
Modified .gitignore to avoid creating a new revision for changes to logfiles and regenerated script files.Also:
Merge branch 'master' into work

October 27, 2011 at 3:00am
Correction to netgen-1.4 to deal with undefined "CONST84" in Tcl code.Also:
Update at Wed Oct 26 05:20:40 PDT 2011 by timAlso:
Merge branch 'master' into work

October 30, 2011 at 3:00am
Corrected a bad error in sim files where transistor gate and drain are swapped on read-in.Also:
Update at Sat Oct 29 11:39:14 PDT 2011 by timAlso:
Merge branch 'master' into workAlso:
Redid the previous correction, changing the arguments in the subroutine instead of in the call, since it's the subroutine argument order that got changed, somehow.

March 29, 2012 at 3:00am
Update at Tue Mar 6 12:30:35 PST 2012 by timAlso:
Finished a basic implementation of the hierarchical LVS, which unfortunately I earlier abandoned when it was just shy of being completed. The hierarchical LVS now handles pin matching between pairs of cells, so that after the cells are declared matching, the pins are matched up so that the next hierarchical level of comparison will have the same pin order for both. Pins which are not electrically connected are shuffled to the end of the pin list so that cells with phantom pins can be correctly compared.Also:
Update at Wed Mar 28 10:22:00 EDT 2012 by timAlso:
Merge branch 'master' into workAlso:
Modifications to enable port sorting in hierarchical LVS. Work in progress.

September 2, 2012 at 3:00am
Corrected an error with a duplicate definition of netgeninterp. Also, changed the configuration script to match the search path used to find Tcl/Tk used in other tools. Finally, corrected an error where the /usr/local/lib/netgen/ directory was not created and would raise an error when trying to copy runtime files into it.Also:
Update at Sat Sep 1 20:46:33 EDT 2012 by timAlso:
Merge branch 'master' into work

September 4, 2012 at 3:00am
Corrected the order of libraries in the non-Tcl make of netcomp and friends. Some compiler setups can't take the reverse order, and fail to link properly.Also:
Update at Mon Sep 3 09:32:25 EDT 2012 by timAlso:
Merge branch 'master' into work

September 7, 2012 at 3:00am
Another configuration change for Tcl/Tk in lib64Also:
Update at Thu Sep 6 10:08:28 EDT 2012 by timAlso:
Merge branch 'master' into workAlso:
Also: Corrected a set of mixed calls to Tcl and C memory free routines.

September 13, 2012 at 3:00am
Added more functionality to the hierarchical LVS, which now properly flattens circuits that do not match initially. Also, added parsing for a ".include" record in a SPICE deck.Also:
Update at Wed Sep 12 13:23:17 EDT 2012 by timAlso:
Merge branch 'master' into workAlso:
(Small correction to last update)

September 16, 2012 at 3:00am
Finished corrections of the hierarchical LVS, including handling of global nodes through the flattening process.Also:
Update at Sat Sep 15 13:31:38 EDT 2012 by timAlso:
Merge branch 'master' into workAlso:
Corrected an issue with CurrentCell being undefined when a .subckt record is found in a SPICE netlist.

September 19, 2012 at 3:00am
Corrected a problem with a mismatch between an allocation using the system strdup() and freed using Tcl_Free().Also:
Update at Tue Sep 18 10:50:44 EDT 2012 by timAlso:
Merge branch 'master' into workAlso:
Fixed the fix, which unwisely deleted the much-needed Tcl_Strdup routine, which replaces strsave(), although probably unnecessarily.

September 21, 2012 at 3:00am
Corrected a bug that caused netgen to crash if an attempt was made to include a non-existant file using the ".include" card in a SPICE netlist.Also:
Update at Thu Sep 20 14:37:35 EDT 2012 by timAlso:
Merge branch 'master' into work

October 1, 2012 at 3:00am
Correction to parsing of ".global" statement in SPICE netlists: keyword can be followed by multiple arguments, and global node references can be backwards or forwards (i.g., ".global" can be stated after a node has been defined, or before).Also:
Update at Sun Sep 30 10:20:12 EDT 2012 by timAlso:
Merge branch 'master' into workAlso:
Corrected an error in the Tcl "lvs" script in which non-matching subcircuits do not report having an error, and do not flatten the subcircuits that do not match. This leaves the possibility that if the top-level circuit has correct connections into the bad subcircuits, the whole netlist will report as matching.

October 3, 2012 at 3:00am
Corrected a typo that crept into the last update. Fixed a rather bad error that failed to clear the current cell when reading a spice file, so the next file could end up believing that the previous file was its "parent".Also:
Update at Tue Oct 2 16:20:41 EDT 2012 by timAlso:
Merge branch 'master' into work

October 7, 2012 at 3:00am
Extensive corrections to the LVS comparison code, to properly handle global variables by forcing them to be local at each subcircuit compare, and pass them up to the parent cell as pins. Also created a new side-by-side output format that it much more easily readable than the original output. No attempt is made to organize nets or elements within an illegal fragment, which is next on the to-do list.Also:
Update at Sat Oct 6 13:28:00 EDT 2012 by timAlso:
Merge branch 'master' into workAlso:
One additional correction to avoid calling "MatchPins" and printing pin information for top-level cells that have no pin information.Also:
Correction to SPICE netlist reader: IsPort() should no longer include types GLOBAL and UNIQUEGLOBAL.Also:
. . . With a little syntactic cleanup

October 8, 2012 at 3:00am
A few more minor enhancements, to handle M=# expressions in capacitors and resistors, to specify the instance name of fundamental devices according to the notation in the SPICE file (instead of renumbering all devices according to an independent internal count), and more cleanly printing property errors.Also:
Update at Sun Oct 7 11:05:51 EDT 2012 by timAlso:
Merge branch 'master' into workAlso:
Added handling of the case where automorphisms in a subcell connect to subcell ports. In such cases, the subcell ports should be made permutable, so that the indistinguishable parts of the subcircuit may be called in different orders from the parent cells in each of the two circuits being compared, and they will be matched.Also:
Since property errors do not prevent netgen from declaring a match, it is easy for property errors to get lost in the middle of the output. So I put some code in to capture the names of cells with property errors and print them out at the end, so that they are easy to see.

October 9, 2012 at 3:00am
Added a side-by-side element count to the comparison output file for each cell. This includes matching up cells in circuit1 vs. circuit2, given that all instances should have been individually LVS'd first, and therefore marked as corresponding.Also:
Update at Mon Oct 8 12:36:31 EDT 2012 by timAlso:
Merge branch 'master' into work

October 12, 2012 at 3:00am
Corrected an error that would cause a segfault when reading in a SPICE file having no top-level circuit definition.Also:
Update at Thu Oct 11 10:55:29 EDT 2012 by timAlso:
Merge branch 'master' into workAlso:
Corrected the spice ".import" handling so that subcircuits in the imported file are correctly associated with the main circuit. However, this highlights the problem that it is not possible to read in a spice file of subcircuits independently, and attach those subcircuits to a top-level circuit.Also:
Another correction to formatted side-by-side printout of node fragments.

November 2, 2012 at 3:00am
Corrected the side-by-side illegal element partition output, which failed to separately count the indexes for the two sides and would become screwed up when either side had a permutable pin.Also:
Update at Thu Nov 1 15:08:55 EDT 2012 by timAlso:
Merge branch 'master' into workAlso:
And one more correction for printing the circuit summary when the 2nd circuit has more elements than the first.

November 3, 2012 at 3:00am
Some minor changes affecting printed output: Notice of flattening unmatched instances prior to comparison moved from console to comp.out. Illegal node partition output now lists all pin names for permutable pins, so as to avoid confusion.Also:
Update at Fri Nov 2 10:30:49 EDT 2012 by timAlso:
Merge branch 'master' into workAlso:
Corrected the output for command "nodes" so that it doesn't break on seeing a pin, and will continue until it finds a valid node name to print.Also:
Another addition to printout for "nodes" command, to add "(port of. . .)" when the only connection found is a port of the cell.Also:
Corrected another error: Netgen ignores partitions with two elements, which cannot be usefully subdivided, and apparently parts of the code depend on partitions being larger than one item. However, it failed to mark partitions with two elements from the same circuit as illegal. Changed code to make a quick check at the end of an iteration for partitions with 2 items from the same circuit, and mark those partitions as illegal. This results in a complete dump of all non-matching elements and nodes.Also:
Correction to most recent code change to create a 1-deeper nesting of lists when creating a Tcl list of node and element partitions.

November 4, 2012 at 3:00am
Addition of "-list" option to commands "print", "elements ", and "nodes ", and the addition of a 2nd optional argument to command "print" which can be "legal" or "illegal", to restrict printing to only legal or illegal partitions. The "-list" option passes back a Tcl list to the interpreter, instead of printing human-readable content to the console. This is the base code needed to write a GUI for the LVS function.Also:
Update at Sat Nov 3 13:39:15 EDT 2012 by timAlso:
Merge branch 'master' into work

May 14, 2013 at 3:00am
Corrected the LVS script to flatten circuits that match locally but fail to resolve automorphisms. Unfortunately, visual inspection in the test case suggests that the automorphisms should have been resolved. Nevertheless, failure to resolve automorphisms should result in subcircuit flattening.Also:
Update at Mon May 13 11:14:15 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
Corrected a rather bad error in handling global nodes in which the code to end on the last pin of a subcircuit call was wrong, allowing the netlist to get totally screwed up while resolving global nodes used in a subcircuit.

May 18, 2013 at 3:00am
Added some ability to parse and handle parameters for subcircuits and subcircuit calls. Currently, parameters describing equations are not evaluated, but the parameters are at least parsed and saved, and do not interfere with the parsing of port connections and subcircuit names.Also:
Update at Fri May 17 12:17:44 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
Corrected an error caused by having a global node name that is not used anywhere in the top-level cell.

May 21, 2013 at 3:00am
Found an obscure error where a cached nodename was sought using an index higher than the number of nodes. This error may have had its roots elsewhere, but the crash condition has been eliminated.Also:
Update at Mon May 20 19:36:01 EDT 2013 by timAlso:
Merge branch 'master' into work

May 23, 2013 at 3:00am
Added some CDL-netlist syntax parsing to the SPICE netlist reader. Also, the startup script now treats anything on the command line as a Tcl statement to evaluate, so a single-line command like "lvs" can be passed to netgen directly from the command line.Also:
Update at Wed May 22 13:16:37 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
Implemented new command "ignore class ", to force removal of certain classes from the database. Should be used with caution. Example: remove diodes that cannot be properly extracted from the layout, or remove parasitic devices (if they are separable from "real" devices by being the only ones not using a model name).

May 24, 2013 at 3:00am
Added rudimentary support for parameters passed from a subcircuit to a device. Only works for a hierarchy depth of 1 at the moment.Also:
Update at Thu May 23 16:58:37 EDT 2013 by timAlso:
Merge branch 'master' into work

May 25, 2013 at 3:00am
Removed a limitation in netgen that restricts input lines to 500 characters. Now, input lines are allocated as necessary to accept input lines of arbitrary length.Also:
Update at Fri May 24 13:35:49 EDT 2013 by timAlso:
Merge branch 'master' into work

May 26, 2013 at 3:00am
Corrected an error in the allocation of an expanded memory block for line input.Also:
Update at Sat May 25 13:24:55 EDT 2013 by timAlso:
Merge branch 'master' into work

May 29, 2013 at 3:00am
Various corrections and enhancements. Changed the hierarchy stack creation so that it more precisely matches cells by name from the hierarchy bottom, and works its way back up by level. Corrected some of the handling of global nodes when promoting to ports.Also:
Update at Tue May 28 12:00:39 EDT 2013 by timAlso:
Merge branch 'master' into work

May 30, 2013 at 3:00am
Several corrections to netgen, changed the SPICE reader's behavior to avoid copying the cellname as a prefix to the instance name if the instance name already has the cellname in it. Also, fixed an error that would prevent proper LVS where dummy nodes had been added to the 2nd circuit to match unconnected pins in the 1st circuit.Also:
Update at Wed May 29 18:03:59 EDT 2013 by timAlso:
Merge branch 'master' into work

May 31, 2013 at 3:00am
Last final set of modifications to hierarchical LVS; torture test example now agrees between hierarchical and non-hierarchical netlists.Also:
Update at Thu May 30 14:46:13 EDT 2013 by timAlso:
Merge branch 'master' into work

June 5, 2013 at 3:00am
Corrected an error in which an empty hierarchy stack during SPICE read was interpreted as an error, while it may simply mean that no nodes, instances, or devices were created prior to the first subcircuit definition. The stack should always be popped on seeing ".ENDS" unless the stack pointer itself is NULL.Also:
Update at Tue Jun 4 19:10:07 EDT 2013 by timAlso:
Merge branch 'master' into work

January 8, 2014 at 3:00am
Corrected an error where the style of prepending "X" to an instance name caused problems where a net named, e.g., "NOR2X1_1/Y" would be confused with an instance pin named, e.g., "XNOR2X1_1/Y". This has been corrected by naming instance pins using, e.g., "/NOR2X1_1/Y", although it would probably be better to use a character like '*' that would be illegal in a SPICE netlist rather than one that is commonly used in netlisting tools and therefore likely to show up as a node name in a netlist.Also:
Update at Tue Jan 7 12:06:25 EST 2014 by timAlso:
Merge branch 'master' into workAlso:
Cleanup of the printout of the "elements" and "nodes" commands to prevent them from requiring or printing the leading "/" prepended to instance names.

February 6, 2014 at 3:00am
Experimental code implementing case-insensitive hashing and comparison. Currently the loading of a SPICE file will force case-insensitive hashing, and comparing two SPICE files will force case-insensitive comparison. There needs to be individual control over the handling of each file. Most LVS is done between SPICE format files and there may never be a need for that kind of control.Also:
Update at Wed Feb 5 20:38:37 EST 2014 by timAlso:
Merge branch 'master' into work

April 11, 2014 at 3:00am
Cleaned up fscanf() calls in netfile.c to prevent array overruns.Also:
Update at Thu Apr 10 09:57:42 EDT 2014 by timAlso:
Merge branch 'master' into work

May 11, 2014 at 3:00am
Corrected an error that causes netgen to crash on a cell with no elements. This doesn't resolve problems with running hierarchical LVS on such a cell, but at least it stops the crashing.Also:
Update at Sat May 10 10:59:53 EDT 2014 by timAlso:
Merge branch 'master' into work

May 13, 2014 at 3:00am
Several key Tcl commands like "run" and "verify" no longer generate an error code for an empty cell. This prevents LVS from prematurely quitting when encountering a subcell with no contents.Also:
Update at Mon May 12 12:04:22 EDT 2014 by timAlso:
Merge branch 'master' into work

May 27, 2014 at 3:00am
Update at Mon May 26 09:55:09 EDT 2014 by tim

May 28, 2014 at 3:00am
Update at Tue May 27 19:10:19 EDT 2014 by tim

May 30, 2014 at 3:00am
Update at Thu May 29 10:52:49 EDT 2014 by tim

May 31, 2014 at 3:00am
Update at Fri May 30 14:41:23 EDT 2014 by tim

June 1, 2014 at 3:00am
Update at Sat May 31 14:50:56 EDT 2014 by tim

August 21, 2014 at 3:00am
Modified netgen.tcl to avoid using the "wm" command if Tk is not loaded. That single usage prevents netgen from being called in batch mode through tclsh; otherwise, it can run without the need for an X11 display present, greatly enhancing its portability.Also:
Update at Wed Aug 20 17:20:40 EDT 2014 by timAlso:
Merge branch 'master' into workAlso:
Corrected an error in which netgen loses filename information about SPICE "libraries" (for example, CDL files) that have no components on the top level. Without a filename attached to the file number, netgen is no longer able to differentiate between cells belonging to that filename and other filenames. Netgen now registers an empty cell with the filename, which solves the problem.

August 28, 2014 at 3:00am
Attempted to resolve a number of issues where having a low-level device in one circuit with the same name as a subcircuit in the other circuit causes a crash. Did not completely resolve this issue.Also:
Update at Wed Aug 27 14:57:24 EDT 2014 by timAlso:
Merge branch 'master' into work

August 30, 2014 at 3:00am
Corrected the SPICE file read routine so that file name in a ".include" statement are interpreted relative to the path of the file that included them, if the filename contains a relative path.Also:
Update at Fri Aug 29 14:49:15 EDT 2014 by timAlso:
Merge branch 'master' into work

September 5, 2014 at 3:00am
Added some missing model types to the "model" command. Also: Removed Tk calls from netgenexec.c, so that the executable "netgenexec" or the script call "netgen -noconsole" will run without requiring graphics accessibility.Also:
Update at Thu Sep 4 09:57:44 EDT 2014 by timAlso:
Merge branch 'master' into workAlso:
Implemented new command option "permute forget".

September 6, 2014 at 3:00am
Corrected an error introduced into recent code that prevents the use of "equate classes" in the setup file, as it would refuse to work until a netlist was read in. Only the "equate nodes" and "equate elements" need to have a netlist in memory to run; "equate classes" does not.Also:
Update at Fri Sep 5 10:04:53 EDT 2014 by timAlso:
Merge branch 'master' into workAlso:
Quick correction: "equate pins" also requires that a netlist have been read in first. Only "equate classes" can be run prior to a netlist read.Also:
Corrected a very bad error in which an "include" statement in a SPICE file would re-read the parent file instead.Also:
Rather a lot of coding, fixed a lot of memory allocation issues which get the tool a longer way toward being able to implement a reinitialization without crashing, and fixes problems where recent changes caused previously working LVS runs to break. Appears to be back to normal now.

September 8, 2014 at 3:00am
Corrected a major problem with subcircuit using multiplier "M=", which was generating unconnected instances for all but the first device.Also:
Update at Sun Sep 7 16:11:44 EDT 2014 by timAlso:
Merge branch 'master' into work

September 9, 2014 at 3:00am
Updated a few portions of the configure script to resolve differences with the similar configure script used for magic-8.0.Also:
Update at Mon Sep 8 08:47:31 EDT 2014 by timAlso:
Merge branch 'master' into work

September 13, 2014 at 3:00am
Sweeping changes to the code to stop the silliness with prepended underscores, and let cellnames be cellnames, and track which file is which throughout the comparison process.Also:
Update at Fri Sep 12 14:54:31 EDT 2014 by timAlso:
Merge branch 'master' into work

September 14, 2014 at 3:00am
Changed the "readnet" command so that it just returns the file number of a file if it has already been read, instead of attempting to read it again.Also:
Update at Sat Sep 13 21:06:28 EDT 2014 by timAlso:
Merge branch 'master' into work

September 15, 2014 at 3:00am
Reworked the "equate classes" command so that it now works correctly with the latest code. Note, however, that the command needs an additional option where one can specify both the cellname and the file.Also:
Update at Sun Sep 14 11:47:43 EDT 2014 by timAlso:
Merge branch 'master' into work

September 16, 2014 at 3:00am
Minor correction of the use of strchr() when it should have been strrchr() when searching for the '.' before a file extension.Also:
Update at Mon Sep 15 08:12:34 EDT 2014 by timAlso:
Merge branch 'master' into work

November 15, 2004
Changed the "make" method to GNU autoconf. Revised the
directory structure to put most of the Tcl-based stuff
into the "tcltk" subdirectory. The source itself is
essentially unchanged from version 1.2. Confirmed
compile and run for both the Tcl and non-Tcl versions.

August 6, 2005
Updated parts of the "make" process to match additions
to magic and xcircuit, and to address issues related
to compile and install on Cygwin. Cygwin users should
read the compile and install instructions on magic for
Windows.

September 3, 2005
Added Xilinx support. Thanks to Peter Welch for providing
the patch files. Thanks to Ingo Cyliax for the code itself,
which was added to a branch of netgen at the University of
Indiana, and about which I was unaware until Peter brought
it to my attention. Apparently that code branch is no
longer available for download from the CS department at
Indiana.

Also: Changed the Makefile process to parse the
file VERSION for version and revision information, not
the directory name. Switched the directory to the
name with the version number ("netgen-1.3.2") and the
symbolic link to the package name ("netgen"). It was
gently pointed out to me that I had this ass-backwards.

September 6, 2005
Added support for reading bipolar transistors from
SPICE decks.

September 7, 2005
Made some changes to prevent crashing on unexpected
input (in particular, undefined subcircuits) in
SPICE decks. Also, added the command "readlib" for
reading Actel and Xilinx libraries (formerly required
use of "readnet actel|xilinx" plus an unused dummy
argument, due to an error in the Tcl command-line
processing). A warning is posted if an attempt is
made to write a Xilinx or Actel format file without
first reading the associated library.

Februrary 23, 2006
Distribution compliance changes: CAD_HOME redefined to be
the same as "libdir", so that "libdir" can be defined
independently of "prefix" when running configure without
screwing up everything.

November 22, 2007 at 2:40am
Added handling for device types "z", "r", "c", and "b" when using
the netgen command "writenet sim". However, device properties
(length, width, resistance, etc.) are still not handled. . .

November 23, 2007 at 2:40am
Added rudimentary support for device properties. For the moment,
apart from the important aspect of having a database
representation for device properties such as length, width,
resistance, and capacitance, there is support for reading device
properties from SPICE files and writing those that are supported
by the sim format to .sim files. It is my intention to
eventually support property comparisons in LVS.

December 1, 2007 at 2:40am
Corrected some errors where strdup() and free() were called
instead of their Tcl counterparts.

March 12, 2003
Fixes the the "make config" process for Tcl/Tk compile. Also,
finished implementing the Tcl "log" command for log file
output, and added the script-level "lvs" command to replace
the original standalone program "netcomp".

March 24, 2003
Corrections to TCL command interface.

March 26, 2003
This version was never officially released.

March 31, 2003
Changes for interoperability with magic and IRSIM.

April 3, 2003
Changes to save position information in element names for
transistors read from .sim files.

September 22, 2003
Added the capability to handle "M=" syntax in SPICE files
for declaring multiple transistors with equal size and
connections.

September 30, 2003
Fixed an unfortunate problem with the "lvs" script command
in which it implies that circuits which pass the low-level
connectivity comparison match correctly. In fact, these
circuits may have errors. The fix checks this condition,
performs the high-level resolution of automorphisms, and
reports a final pass/fail condition.

December 14, 2002
This is a first draft. Only a few things
have been changed in this release other than the Tcl/Tk
port. There is now support for capacitors, resistors, bipolars,
poly-poly capacitors and resistors built with the pseudo-poly
layer in magic, in the SPICE, sim, and ext format read routines.
The Tcl version has a completely revamped command set, better
matching the general practices of Tcl command syntax (mainly
meaning commands are full words rather than single letters).
In addition, the command sets for "netgen" and "netcmp" have
been combined.

January 13, 2003
Massive speedup of several critical and badly-written
functions; reduced from O(N^2) to O(N). The "compare" command
is now virtually instantaneous. Commands "nodes" and "elements"
now give more relevant information regarding specific points
in the network. "sim" format retains position in the element
names (for FET and FET-like elements) for convenient traceback
to a layout or schematic.