7.6. Asynchronous errors

The L2 memory system has two outputs that indicate asynchronous
error conditions. An asynchronous external error condition exists
when either:

The nEXTERRIRQ output is LOW.

The nINTERRIRQ output
is LOW.

If an asynchronous error
condition is detected, the corresponding bit in the L2 Extended
Control Register is asserted. The asynchronous error condition can
be cleared by writing 0b0 to the corresponding
bit of the L2ECTLR. Software can only clear the L2ECTLR. Any attempt
to assert the error by writing the L2ECTLR is ignored. See L2 Extended Control Register, EL1 for more information.

Any external error associated with a load instruction is reported
back to the requestor along with an error response and this might
trigger an abort. Any external error associated with a Device, Non-cacheable,
or non-allocating write that misses in the L2, or a cache maintenance
operation is reported to the processor that issued the transaction
through a processor-specific interrupt request to the GIC.