The key challenge for enablement of a 2nd node of single-expose EUV patterning is understanding and mitigating the patterning-related defects that narrow the process window. Typical in-line inspection techniques, such as broadband plasma (291x) and e-beam systems, find it difficult to detect the main yield-detracting defects post-develop, and thus understanding the effects of process improvement strategies has become more challenging. New techniques and methodologies for detection of EUV lithography defects, along with judicious process partitioning, are required to develop process solutions that improve yield.

This paper will first discuss alternative techniques and methodologies for detection of lithography-related defects, such as scumming and microbridging. These strategies will then be used to gain a better understanding of the effects of material property changes, process partitioning, and hardware improvements, ultimately correlating them directly with electrical yield detractors .

Extreme ultraviolet lithography (EUVL) technology is one of the leading candidates under consideration for enabling the next generation of devices, for 7nm node and beyond. As the focus shifts to driving down the 'effective' k1 factor and enabling the full scaling entitlement of EUV patterning, new techniques and methods must be developed to reduce the overall defectivity, mitigate pattern collapse, and eliminate film-related defects. In addition, CD uniformity and LWR/LER must be improved in terms of patterning performance. Tokyo Electron Limited (TEL™) and IBM Corporation are continuously developing manufacturing quality processes for EUV. In this paper, we review the ongoing progress in coater/developer based processes (coating, developing, baking) that are required to enable EUV patterning.

Extreme ultraviolet lithography (EUVL) technology is one of the leading candidates for enabling the next generation devices, for 7nm node and beyond. As the technology matures, further improvement is required in the area of blanket film defectivity, pattern defectivity, CD uniformity, and LWR/LER. As EUV pitch scaling approaches sub 20 nm, new techniques and methods must be developed to reduce the overall defectivity, mitigate pattern collapse and eliminate film related defect. IBM Corporation and Tokyo Electron Limited (TELTM) are continuously collaborating to develop manufacturing quality processes for EUVL.

In this paper, we review key defectivity learning required to enable 7nm node and beyond technology. We will describe ongoing progress in addressing these challenges through track-based processes (coating, developer, baking), highlighting the limitations of common defect detection strategies and outlining methodologies necessary for accurate characterization and mitigation of blanket defectivity in EUV patterning stacks. We will further discuss defects related to pattern collapse and thinning of underlayer films.

Successful pattern transfer from the photoresist into the substrate depends on robust layers of lithographic films. Typically, an alternating sequence of inorganic (most often Si containing) and organic hardmask (HM) materials is used. Pattern transfer occurs then by using reactive ion etch (RIE) chemistry that is selective to one particular layer (such as: flurorinated RIE for Si HM). The impact of these RIE gases onto the layers acting as hardmask for the layer to be etched is typically neglected, except for known sputtering effects. We found that components of the RIE gases can penetrate deep into the “inert” layers and significantly modify them. For example, nitrogen used as component to etch spin-on carbon layers was found to travel up to 70 nm deep into Si HM materials and create layers with different material properties within this film. The question is being raised and discussed to which extent this atom implantation may impact the pattern transfer of the ever shrinking features.

Initial readiness of EUV (extreme ultraviolet) patterning was demonstrated in 2016 with IBM Alliance's 7nm device technology. The focus has now shifted to driving the 'effective' k1 factor and enabling the second generation of EUV patterning. With the substantial cost of EUV exposure there is significant interest in extending the capability to do single exposure patterning with EUV. To enable this, emphasis must be placed on the aspect ratios, adhesion, defectivity reduction, etch selectivity, and imaging control of the whole patterning process. Innovations in resist materials and processes must be included to realize the full entitlement of EUV lithography at 0.33NA. In addition, enhancements in the patterning process to enable good defectivity, lithographic process window, and post etch pattern fidelity are also required. Through this work, the fundamental material challenges in driving down the effective k1 factor will be highlighted.

The feature scaling and patterning control required for the 7nm node has introduced EUV as a candidate lithography technology for enablement. To be established as a front-up lithography solution for those requirements, all the associated aspects with yielding a technology are also in the process of being demonstrated, such as defectivity process window through patterning transfer and electrical yield. This paper will review the current status of those metrics for 7nm at IBM, but also focus on the challenges therein as the industry begins to look beyond 7nm. To address these challenges, some of the fundamental process aspects of holistic EUV patterning are explored and characterized. This includes detailing the contrast entitlement enabled by EUV, and subsequently characterizing state-of-the-art resist printing limits to realize that entitlement. Because of the small features being considered, the limits of film thinness need to be characterized, both for the resist and underlying SiARC or inorganic hardmask, and the subsequent defectivity, both of the native films and after pattern transfer. Also, as we prepare for the next node, multipatterning techniques will be validated in light of the above, in a way that employs the enabling aspects of EUV as well. This will thus demonstrate EUV not just as a technology that can print small features, but one where all aspects of the patterning are understood and enabling of a manufacturing-worthy technology.

EUV lithography is one of the main candidates for enabling the next generation of devices, primarily by enabling a lithography process that reduces complexity, and eventually, cost. IBM has installed the latest tool sets at the IBM EUV Center of Excellence in Albany to accelerate EUV lithography development for production use. Though the EUV cluster is capable of enabling the pitch requirements for the 7nm node, the dimensions in question represent a new regime in defectivity. Additionally, new classes of patterning materials are being explored, for which there is very little known up-front regarding known defect mechanisms. We will discuss the baseline cluster performance and the improvement strategy in terms of defectivity and pattern collapse in this paper by utilizing coater/developer techniques based on the new platform.

With current progress in exposure source power, novel resist materials, and post processing techniques, EUV is getting closer to the production environment. As reported continuously, SEMATECH established cycles of learning program. The data generated from the program has been utilized to measure current state of the art of EUV photoresist for production or pilot line use. Thanks to SEMATECH core and associate members’ attention to the project, numerous EUV samples have been tested and they were based on the best performing EUV resists from associate members. This year we completed the evaluations for under-layers, lines and spaces, and contact holes. We also applied track based techniques to drive both low line edge roughness control and enlarge the process window with techniques such as FIRMTM and track based smoothing process. In this paper we will discuss about the results from cycles of learning test and show post-processing results of the three best line and space resists when combined with different FIRMTM materials.

Evaluation of resist shrinkage and precision by critical dimension scanning electron microscope (CD-SEM) for EUV resist patterns at around 20 nm exposed by 0.33 NA EUV tool was conducted. To investigate interaction between EUV resist and electron beam, an accurate and fast measurement method of resist shrinkage was established. Our method can avoid saturation of shrinkage at large dose conditions which was a demerit in conventional method. By applying the new method, pattern size dependence of shrinkage was measured with various line and space (L/S) patterns down to 20 nm. The result shows that resist shrinkage of fine L/S EUV resist pattern largely depends on line width rather than space width. A well-known trade-off relationship between shrinkage and precision was observed for EUV resist pattern as well as ArF resist pattern. Shrinkage of 1.6 nm and precision of 0.13 nm for 18 nm EUV resist pattern were obtained at a typical CD-SEM condition. We also measured shrinkage and precision for a dense L/S pattern at various exposure focus and dose conditions using a FEM wafer to examine the impact of process variability. To investigate the influence of EUV shadowing effect, we measured them for both horizontal and vertical patterns at different slit locations in exposure field. No systematic change of shrinkage and precision was observed through exposure focus and dose in the process window across slit location for both horizontal and vertical L/S patterns.

The use of organic solvents in the development of chemically amplified (CA) resists has been known since the
introduction of DUV lithography into manufacturing over twenty years ago [1,2]. In this approach a negative tone image
is produced using an aqueous base developable positive tone resist developed in an organic solvent. Recently there has
been an increased interest in negative tone imaging due to superior performance for specific masking levels such as
narrow trenches and contact holes [3].
Negative tone imaging of this type is based on differences in the polarity between the exposed and unexposed regions of
the resist film. The dissolution contrast can be optimized by selecting a solvent with the proper match of solubility
parameters (polarity, hydrogen bonding and dispersion) to attain good solubility of the relatively nonpolar unexposed
resist and poor solubility of the deprotected acidic exposed film. Another approach is to tune the properties of the resist
polymer for a given solvent, creating a new optimized resist. We have explored a third methodology to achieve a high
contrast solvent developable system without a need to modify resist or solvent. In this report we describe a process that
exploits the differences in solubility between ionic and organic materials. In this method an ionic species is introduced
into the resist film following post-exposure bake to alter the polarity in such way that the resist contrast can be improved
in organic solvent development. We describe processes using pre-rinses and developers containing salts. Lithographic
response, characterized using contrast curves and imaging, is presented for a variety of resist platforms. We show
evidence for ionic incorporation into the resist film using SIMS, XPS, QCM and FTIR characterization. We demonstrate
the practical applicability of this method to 248nm, 193nm, e-beam and EUV exposures.

For projection printing imaging systems with fixed or restricted illumination modes, pupil filters may enhance imaging
for select features by blocking rays of light that negatively contribute to imaging. A method to design pupil filters for
the optimum printing of a select feature type and size is presented. With this method, a series of pupil filters have been developed and are being tested to enhance the resolution of the Albany Alpha Demo Tool (ADT, 0.25NA) in order to enable resist and process development at feature sizes relevant to the 10 and 7nm nodes. By only allowing light to
propagate to the wafer that positively contributes to imaging, six filters have been custom designed to optimize printing of the following sub-resolution feature types and sizes: 22 and 19 nm HP lines, 24 and 21 nm HP contacts, and 27×22 nm HP rectangular contacts. Development and installation of enabling hardware on the scanner is complete, six filters have been manufactured and imaging in resist has validated the concept. Over 20% improvement in tool resolution has been achieved for 22nm HP lines, allowing resist process development for NXE3300 conditions on the ADT. This paper discusses the theory behind the filter designs, the experimental in-resist evaluations, and other aspects of the development, to include challenges caused by the filters with slit uniformity, stray light, and reticle alignment.

Roughness control is a key technical issue in extreme ultraviolet (EUV) lithography. It applies to both line and space
(L/S) and contact hole (C/H) structures. Recently, SEMATECH and Tokyo Electron Limited (TEL) developed
several track-based techniques, including developer optimization, FIRM™ (Finishing up by Improved Rinse
Material), and smoothing to reduce structural roughness. The combination of these techniques improved line width
roughness (LWR) about 25% from the 2011 baseline of 32 nm L/S. C/H structures were also tested with the
combination process. This paper describes our latest L/S and C/H roughness performance post-lithography and postetch.
A feasibility study of negative tone develop (NTD) resists for EUV is also included.

During exposure in an EUV scanner, photoresist and other materials coated on a wafer are known to outgas various species. As a requirement to pattern materials in an ASML NXE scanner, these materials need to be screened for outgassing and possible optics contamination. As part of the testing process, a resist-coated wafer is exposed in a vacuum chamber mimicking the conditions inside an EUV scanner. The resist exposure source can be either EUV photons or electron beam (e-beam). This presentation will cover the results to date on a SEMATECH program to study resist outgassing from both the commercial system from EUV Tech and a custom Resist Outgassing and Exposure (ROX) tool. The EUV Tech results reported will be based on electron exposures of the photoresist, and the ROX results reported will be based on EUV photon exposures of the photoresist. The results reported will cover both tools and the measurements of over 80 commercial photoresists.

This paper demonstrates a new simulation-based methodology for optimizing critical dimension (CD) bias for contact holes (CH) arrays using several different extreme ultraviolet (EUV) resists that were fully calibrated and verified with physical resist models. The bias for CH was optimized using local CD uniformity (CDU) 3-sigma as a cost function. The CD sigma variations of near-neighbor contact holes were simulated as a function of dose-to-size and mask bias, averaged over a large number of stochastic trials. There is a distinct bias for minimum CD sigma accompanied by an increase in the process window. The results are confirmed with wafer data. We will discuss the results in terms of EUV photon shot noise coupled with resist parameters. The simulation results will be used to predict a parameter space for EUV resist that can optimize line edge roughness (LER)/resolution/process window and CDU. Finally, various tradeoffs will be presented that will enable the process to perform in a high volume manufacturing environment.

Line Edge Roughness (LER) continues to be a serious problem for high resolution 193 nm (ArF), E-beam and EUV resists despite years of research. Changes to the resist formulations, the use of low molecular weight (MW) materials, such as molecular glass resists, and special developers have all been used in attempts to minimize LER. In addition, much recent work has focused on post development processes such as rinses, special coatings and thermal treatments to reduce roughness. However there remains a lack of understanding of the origins of LER. Recently researchers have described interesting results based on the use of in situ high speed AFM to characterize LER during development.1 In this report we describe a complementary technique wherein the evolution of the roughness of the resist line is measured at different times during the development process. This is accomplished by using a specially designed flow cell 2-5 to control the developer contact time for a series of identically patterned fields and measuring the partially developed patterns with scanning electron microscopy (SEM). We will describe the results for different resist chemistries at 248 nm (KrF). In one aspect of this study, we examine resists that have been patterned at different aerial image contrast (AIC) to systematically probe its effect on LER 6 for a given resist. We intend to extend this work to different exposure systems including 193 nm, EUV and electron-beam.

Controlling line width roughness (LWR) is a critical issue in extreme ultraviolet lithography (EUVL). High
sensitivity, high resolution, and low LWR are required for EUV lithography resist. However, simultaneously
achieving optimal properties through chemical tuning alone is difficult. The track process is one of the factors
that impacts LWR. Enhancing track processes in EUV lithography is thus critical to controlling LWR.
This paper describes an approach to mitigating LWR based on optimizing track-based and etch-based
processes. It also presents the results of our newly developed track-based smoothing process as well as the
results of combining several track-based techniques. The latest LWR performance from using track-based
techniques, optimized track processes, and etch-based techniques will be highlighted.

The first use of extreme ultraviolet (EUV) lithography in logic manufacturing is targeted for the 14 nm node, with
possible earlier application to 20-nm node logic device back-end layers to demonstrate the technology. Use of EUV
lithography to pattern the via-levels will allow the use of dark-field EUV masks with low pattern densities and will
postpone the day when completely defect-free EUV mask blanks are needed. The quality of the imaging at the 14 nm
node with EUV lithography is considerably higher than with double-dipole or double-exposure double-etch 193-nm
immersion lithography, particularly for 2-dimensional patterns such as vias, because the Rayleigh k1-value when printing
with 0.25 numerical aperture (NA) EUV lithography is so much higher than with 1.35 NA 193-nm immersion
lithography and the process windows with EUV lithography are huge. In this paper, the status of EUV lithography
technology as seen from an end-user perspective is summarized and the current values of the most important metrics for
each of the critical elements of the technology are compared to the values needed for the insertion of EUVL into
production at the 14 nm technology node.

In this work, we investigate the Negative Tone Develop (NTD) process from a fundamental
materials/process interaction perspective. Several key differences exist between a negative tone develop
process and a traditional positive tone develop system. For example, the organic solvent dissolves the
unexposed material, while the deprotected resist remains intact. This causes key differences in key
patterning properties, such as pattern collapse, adhesion, remaining resist, and photoresist etch selectivity.
We have carried out fundamental studies to understand these new interactions between developer and
remaining resist with negative tone develop systems. We have characterized the dynamic dissolution
behavior of a model system with a quartz crystal microbalance with both positive and negative tone solvent
developers. We have also compared contrast curves, and a fundamental model of image collapse. In
addition, we present first results on Optical Proximity Correction (OPC) modeling results of current
Negative Tone Develop (NTD) resist/developer systems.

In this study, we have analyzed new data sets of pattern collapse obtained from 300 mm wafers which were coated with
a process-of-record (POR) EUV resist and exposed by an EUV Alpha-Demo tool (ADT) and a Vistec VB300 e-beam
exposure tool. In order to minimize any processing effects on pattern collapse, the same POR EUV track process was
applied to both exposures. A key metric of our analysis is the critical aspect ratio of collapse (CARC)1. We found that
CARC of POR EUV resist decreases monotonically with spacing, in the range of ~1.8-2.2 at ~32-54 nm space (60-80
nm pitch) for EUV, and ~1.5-2.1 at ~16-50 nm space (~46-80 nm pitch) for e-beam. We also estimated an apparent
Young's modulus of POR EUV resist by fitting a collapse model2 to the CARC data. The resulting modulus ~0.30 GPa
was much smaller than the modulus of typical polymer glasses (~1.0-5.0 GPa). Our findings suggest that due to a
significant decrease of resist mechanical properties and a sharp increase in capillary force, it will be challenging to
maintain aspect ratios above 2.0 for sub-30 nm resist spacing (sub-60 nm pitches). For patterning at these dimensions,
alternate processes and materials will become increasingly necessary, e.g. surfactant-based rinse solutions3 and other
approaches.

Spin-on underlayers are currently being employed by the lithographic industry to improve
the imaging performance of EUV resists. In this work, multiple examples have shown improved
line-edge roughness (LER) of an open-source resist using new open-source underlayers in
comparison to a primed silicon substrate. Additionally, several experiments demonstrate better
resist adhesion on underlayers that have lower coefficients of thermal expansion (CTE). Both
organic and inorganic underlayers provide better resist LER when their CTE is lower.

Pitch-split resist materials have been developed for the fabrication of sub-74 nm pitch semiconductor devices. A
thermal cure method is used to enable patterning of a second layer of resist over the initially formed layer. Process
window, critical dimension uniformity, defectivity and integration with fabricator applications have been explored. A
tone inversion process has been developed to enable the application of pitch split to dark field applications in addition to
standard bright field applications.

Underlayers (UL), such as organic planarizing layers (OPLs) or spin-on carbon (SOC) layers, play a very important role
in various integration schemes of chip manufacturing. One function of OPLs is to fill in pre-existing patterns on the
substrate, such as previously patterned vias, to enable lithographic patterning of the next level. More importantly, OPL
resistance to reactive ion etch (RIE) processes used to etch silicon-containing materials is essential for the successful
pattern transfer from the resist into the substrate. Typically, the pattern is first transferred into the OPL through a two-step
RIE sequence, followed by the transfer into the substrate by a fluorine-containing RIE step that leaves the OPL
pattern mainly intact. However, when the line/space patterns are scaled down to line widths below 35 nm, it was found
that this last RIE step induces severe pattern deformation ("wiggling") of the OPL material, which ultimately prevents
the successful pattern transfer into the substrate.
In this work, we developed an efficient process to evaluate OPL materials with respect to their pattern transfer
performance. This allowed us to systematically study material, substrate and etch process parameters and draw
conclusions about how changes in these parameters may improve the overall pattern transfer margin.

With 22nm logic node arriving prior to EUV implementation, alternative immersion optical lithographic processes
are required to drive down to smaller feature sizes. There is an ongoing effort to examine the application of the negative
tone imaging (NTI) process for current and future nodes. Although NTI has previously shown difficulties with respect to
swelling, high chemical reactivity with oxygen, and the need for special equipment needed for the solvent-based
development, NTI photoresists (PR) typically exhibit stronger adhesion to silicon than that of positive tone photoresists
(a characteristic that helps mitigate pattern collapse). We will provide suggestions on how to improve the image quality,
as well as the resulting defectivity, for desired geometries. This paper will primarily focus on the full litho process
optimization and demonstrate repeatable, and manufacturable critical dimension uniformity (CDU), and defectivity
optimization for trench and via structures.

Line width roughness (LWR) control is a critical issue in extreme ultraviolet lithography (EUVL). The
difficulty of controlling LWR and the need to minimize it have grown as the sensitivity of materials and
resolution in the resist patterning process has improved. Another critical feature that has become difficult to
control in EUVL and 22nm half-pitch systems is pattern collapse. The increase of aspect ratio that comes from
further scaling promotes the onset of pattern collapse. Both pattern collapse and LWR are easily observed in
EUVL and leading-edge ArF immersion lithography.
This paper will demonstrate recent gains in LWR control in leading EUV films using track-based processes,
etch-based improvements, and the results of combined techniques. Also the use of a newly developed EUV-specific
FIRM™ rinse chemistry to reduce pattern collapse will be discussed along with future development
activities and industry requirements for both LWR and pattern collapse.

For the logic generations of the 15 nm node and beyond, the printing of pitches at 64nm and below are needed.
For EUV lithography to replace ArF-based multi-exposure techniques, it is required to print these patterns in
a single exposure process. The k1 factor is roughly 0.6 for 64nm pitch at an NA of 0.25, and k1 ≈ 0.52 for
56nm pitch. These k1 numbers are of the same order at which model based OPC was introduced in KrF and
ArF lithography a decade or so earlier. While we have done earlier work that used model-based OPC for the
22nm node test devices using EUV,1 we used a simple threshold model without further resist model calibration.
For 64 nm pitch at an NA of 0.25, the OPC becomes more important, and at 56nm pitch it becomes critical.
For 15 nm node lithography, we resort to a full resist model calibration using tools that were adapted from
conventional optical lithography. We use a straight shrink 22 nm test layout to assess post-OPC printability of
a metal layer at pitches at 64 nm and 56 nm, and we use this information to correct test layouts.

A series of molecular glasses (MGs) protected with multiple tert-butoxylcarbonylmethyl (tBCM) groups are employed
as additives to enhance extreme ultra violet (EUV) photolithographic performance of a hydroxystyrene based
Environmentally Stable Chemically Amplified Photoresist (ESCAP). The tBCM groups deprotect to form carboxylic
acids that are capable of hydrogen bonding with chain segments of the polymer resist. This approach enables a
systematic study of the governing physics underlying the improved lithographic performance. While MGs inhibit
solubility in all cases, we find that differences in the structure of the MGs can significantly affect the photoacid
diffusivity. In our ongoing optimization of the structure and loading of MGs, photoacid generators (PAGs), and base
quenchers, 25 nm to 30 nm resolution has been achieved. The structure-property relationships and the synergistic effects
of employing small, multi-functional additives in the polymeric photoresists are studied using various characterizations.

As reported previously, the IBM Alliance has established a DETO (Double-Expose-Track-Optimized) baseline, in
collaboration with ASML, TEL, and CNSE, to evaluate commercially available DETO photoresist system for the
manufacturing of advanced logic devices. Although EUV lithography is the baseline strategy for <2x nm logic nodes,
alternative techniques are still being pursued. The DETO technique produces pitch-split patterns capable of supporting
16 nm and 11 nm node semiconductor devices. We present the long-term monitoring performances of CD uniformity
(CDU), overlay, and defectivity of our DETO process. CDU and overlay performances for controlled experiments are
also presented. Two alignment schemes in DETO are compared experimentally for their effects on inter-level & intralevel
overlays, and space CDU. We also experimented with methods for improving CDU, in which the CD-OptimizerTMand DoseMapperTM were evaluated separately and in tandem. Overlay improvements using the Correction Per Exposure
(CPE) and the intra-field High-Order Process Correction (i-HOPC) were compared against the usual linear correction
method. The effects of the exposure field size are also compared between a small field and the full field. Included in all
the above, we also compare the performances derived from stack-integrated wafers and bare-Si wafers.

Pitch doubling technologies are necessary for the 32nm half-pitch (HP) and beyond in order to extend optical
lithography. Many different techniques have been examined including Litho-Litho-Etch (LLE), Litho-Etch, Litho-Etch
(LELE), and Sidewall Image Transfer (SIT). Keeping all of the processes inside the litho cluster, as LLE achieves,
affords process simplification and potential for the lowest cost of ownership for pitch doubling. Within LLE alone, there
are varying approaches including spin-on chemical freeze materials, thermal cure, UV curable materials, among others.
The challenge is to provide robust process performance while still achieving the lowest cost of ownership.
For this paper, we are concentrating on the evaluation of the UV cure process. Our findings are the results of
optimization of the UV cure dose and bake conditions and its affect on the lithographic performance. The optimized
process was investigated for defectivity, critical dimension (CD), repeatability, pattern distortion, etch performance and
readiness for high volume manufacturing. With respect to CD, the investigation included absolute value change (shrinkage or growth) and CD uniformity (CDU). For pattern distortion, we investigated line shrinkage, corner rounding, and line end pull back. Defectivity checks were conducted for full wafer comparison pre and post the UV cure process. Manufacturability measures include throughput, cost of ownership and process stability.

Litho-Etch-Litho-Etch double patterning requires aggressive shrink of each sub-pattern's critical dimensions
to enable inter-digitation and pitch doubling. Application of this double patterning technique to elliptical contacts
introduces a new constraint to the CD shrink processes as controlling the 2-D aspect ratio of elliptical contacts is critical
for both device performance and yield. The impact of a track-applied chemical shrink and reactive ion etch [RIE] shrink
processes to pre/post RIE 2-D aspect ratios [2-D AR] have been evaluated. A methodology for controlling 2-D aspect
ratios with an aggressive CD shrink target is described using a 2:1 aspect ratio test pattern resulting in the successful
fabrication of 2:1 aspect ratio bottom CD contacts with 65% bias from the lithographic CD.

We are evaluating the readiness of extreme ultraviolet (EUV) lithography for insertion into production at the 15 nm
technology node by integrating it into standard semiconductor process flows because we believe that device integration
exercises provide the truest test of technology readiness and, at the same time, highlight the remaining critical issues. In
this paper, we describe the use of EUV lithography with the 0.25 NA Alpha Demo Tool (ADT) to pattern the contact and
first interconnect levels of a large (~24 mm x 32 mm) 22 nm node test chip using EUV masks with state-of-the-art
defectivity (~0.3 defects/cm2). We have found that: 1) the quality of EUVL printing at the 22 nm node is considerably
higher than the printing produced with 193 nm immersion lithography; 2) printing at the 22 nm node with EUV
lithography results in higher yield than double exposure double-etch 193i lithography; and 3) EUV lithography with the
0.25 NA ADT is capable of supporting some early device development work at the 15 nm technology node.

The development of Double-Patterning (DP) techniques continues to push forward aiming to extend the immersion
based lithography below 36 nm half pitch. There are widespread efforts to make DP viable for further scaling of
semiconductor devices. We have developed Develop/Etch/Develop/Etch (DE2) and Double-Expose-Track-Optimized
(DETO) techniques for producing pitch-split patterns capable of supporting semiconductor devices for the 16 nm and 11
nm nodes. The IBM Alliance has established a DETO baseline, in collaboration with ASML, TEL, CNSE, and KLATencor,
to evaluate the manufacturability of DETO by using commercially available resist systems. Presented in this
paper are the long-term performance results of these systems relevant to defectivity, overlay, and CD uniformity.

Numerous alternate processes are under industry-wide evaluation as simplifications to current double patterning
methods. Reduction in process complexity and cost may be achieved by use of photoresist stabilization methods that
eliminate one etch step by allowing a second resist to be patterned over the first resist pattern. Examples of stabilization
methods using numerous curing processes have been reported. At least some resist shrinkage during stabilization
appears to be generally observed for these methods. We evaluate the link between volumetric shrinkage and threedimensional
pattern distortion for a variety of resist geometries using experimental and simulation-based methods.
Experimental resists designed for double patterning using 172 nm UV resist curing were evaluated and showed
shrinkage of less than 10 percent. Several simplified metrology approaches for measuring shrinkage as well as inferring
shrinkage distortions were assessed. For top-down SEM measurements, elbow inner corner rounding measurements
appear to be a usefully robust method for estimating shrinkage distortion. Finite element analysis of resist structures
yields shrinkage distortions that are in good qualitative and quantitative agreement with experiments, and thus appears to
provide a provisionally general and useful method for predicting pattern distortions that arise during cure-based resist
stabilization methods used in double imaging.

As our ability to scale lithographic dimensions via reduction of actinic wavelength and increase of numerical
aperture (NA) comes to an end, we need to find alternative methods of increasing pattern density. Double-Patterning
techniques have attracted widespread interest for enabling further scaling of semiconductor devices. We have developed
DE2 (develop/etch/develop/etch) and DETO (Double-Expose-Track-Optimized) methods for producing pitch-split
patterns capable of supporting 16 and 11-nm node semiconductor devices. The IBM Alliance has established a DETO
baseline in collaboration with KT, TEL, ASML and JSR to evaluate commercially available resist-on-resist systems. In
this paper we will describe our automated engine for characterizing defectivity, line width and overlay performance for
our DETO process.

One method being used to reduce the overall lithography process complexity and cost is to utilize a topcoat-less photoresist. Development of these materials utilizes an additive to prevent water penetration and thus forms the same surface property characteristics created by advanced topcoats. The main challenge for topcoat-less resists is increasing the hydrophobicity without causing too much inhibition at the resist surface - which can lead to bridging or residue defects. The key to such a design is in the balance between leaching control versus dissolution characteristics of the
resist without disregarding lithography performance and increasing defectivity. The addition of materials into existing
ArF photoresists systems have been shown to modulate the contact angle in water-based immersion lithography. The
authors have focused this work on the reduction of defects to achieve defectivity levels that are equal or better than
existing systems.

Reticle defectivity was evaluated using two known approaches: direct reticle inspection and the inspection of the
wafer prints. The primary test vehicle was a reticle with a design consisting of 45 nm and 60 nm comb and
serpentine structures in different orientations. The reticle was inspected in reflected light on the KLA 587 in a die-todie
and a die-to-database mode. Wafers were exposed on a 0.25 NA full-field EUV exposure tool and inspected on a
KLA 2800. Both methods delivered two populations of defects which were correlated to identify coinciding
detections and mismatches. In addition, reticle defects were reviewed using scanning electron microscopy (SEM) to
assess the printability. Furthermore, some images of the defects found on the 45 nm reticle used in the previous
study [1] were collected using actinic (EUV) microscopy. The results of the observed mask defects are presented and
discussed together with a defect classification.

On the road to insertion of extreme ultraviolet (EUV) lithography into production at the 16 nm technology node and
below, we are testing its integration into standard semiconductor process flows for 22 nm node devices.
In this paper, we describe the patterning of two levels of a 22 nm node test chip using single-exposure EUV lithography;
the other layers of the test chip were patterned using 193 nm immersion lithography. We designed a full-field EUV
mask for contact and first interconnect levels using rule-based corrections to compensate for the EUV specific effects of
mask shadowing and imaging system flare. The resulting mask and the 0.25-NA EUV scanner utilized for the EUV
lithography steps were found to provide more than adequate patterning performance for the 22 nm node devices. The
CD uniformity across the exposure field and through a lot of wafers was approximately 6.1% (3σ) and the measured
overlay on a representative test chip wafer was 13.0 nm (x) and 12.2 nm (y). A trilayer resist process that provided
ample process latitude and sufficient etch selectivity for pattern transfer was utilized to pattern the contact and first
interconnect levels. The etch recipes provided good CD control, profiles and end-point discrimination.
The patterned integration wafers have been processed through metal deposition and polish at the contact level and are
now being patterned at the first interconnect level.

Historically, lithographic scaling was driven by both improvements in wavelength and numerical aperture. Recently,
the semiconductor industry completed the transition to 1.35NA immersion lithography. The industry
is now focusing on double patterning techniques (DPT) as a means to circumvent the limitations of Rayleigh
diffraction. Here, the IBM Alliance demonstrates the extendibility of several double patterning solutions that
enable scaling of logic constructs by decoupling the pattern spatially through mask design or temporally through
innovative processes. This paper details a set of solutions that have enabled early 22 nm learning through careful
lithography-design optimization.

We have used ASML's full field step-and-scan exposure tool for extreme ultraviolet lithography (EUVL), known as an
Alpha Demo Tool, to investigate one of the critical issues identified for EUVL, defectivity associated with EUV masks.
The main objective for this work was to investigate the infrastructure currently in place to examine defects on a EUV
reticle and identify their consequence in exposed resist. Unlike many previous investigations this work looks at
naturally occurring defects in a EUV exposed metal layer from a 45 nm node device. The EUV exposure was also
integrated into a standard process flow where the other layers were patterned using more conventional 193-nm
lithography techniques.
This presentation correlates reticle level defectivity to resulting wafer exposures. Defect inspection data from both the
28xx family of KLA-Tencor wafer inspection tool and Terascan reticle inspection tools are presented. Defect
populations were characterized with a KLA 5200 Review SEM. Observed defectivity modes were analyzed using both
conventional defect inspection methodology as well as advanced techniques in order to gain further insight. We find
good correlations between reticle level defects and the resulting wafer exposure defects.

In this paper, we describe the integration of EUV lithography into a standard semiconductor manufacturing flow to
produce demonstration devices. 45 nm logic test chips with functional transistors were fabricated using EUV lithography
to pattern the first interconnect level (metal 1).
This device fabrication exercise required the development of rule-based 'OPC' to correct for flare and mask shadowing
effects. These corrections were applied to the fabrication of a full-field mask. The resulting mask and the 0.25-NA fullfield
EUV scanner were found to provide more than adequate performance for this 45 nm logic node demonstration. The
CD uniformity across the field and through a lot of wafers was 6.6% (3σ) and the measured overlay on the test-chip
(product) wafers was well below 20 nm (mean + 3σ). A resist process was developed and performed well at a sensitivity
of 3.8 mJ/cm2, providing ample process latitude and etch selectivity for pattern transfer. The etch recipes provided good
CD control, profiles and end-point discrimination, allowing for good electrical connection to the underlying levels, as
evidenced by electrical test results.
Many transistors connected with Cu-metal lines defined using EUV lithography were tested electrically and found to
have characteristics very similar to 45 nm node transistors fabricated using more traditional methods.

Immersion lithography for the 32nm node and beyond requires advanced methods to control 193 nm radiation
reflected at the resist/BARC interface, due to the high incident angles that are verified under high numerical aperture
(NA) imaging conditions. Swing curve effects are exacerbated in the high NA regime, especially when highly reflective
substrates are used, and lead to critical dimension (CD) control problems. BARC reflectivity control is also particularly
critical when underlying surface topography is present in buried layers due to potential reflective notching problems. In
this work, a graded spin-on organic BARC was developed to enable appropriate reflectivity control under those
conditions. The graded BARC consists of two optically distinct polymers that are completely miscible in the casting
solution. Upon film coating and post-apply baking, the two polymers vertically phase-separate to form an optically
graded layer. Different characterization techniques have been applied to the study of the distribution of graded BARC
components to reveal the internal and surface composition of the optically graded film, which includes Variable Angle
Spectroscopic Ellipsometry (VASE) and Secondary Ion Mass Spectroscopy (SIMS). Also, optical constant optimization,
substrate compatibility, patterning defectivity and etch feasibility for graded BARC layers are described. Superior 193
nm lithographic performance and reflectivity control of graded BARC beyond 1.20 NA compared to conventional
BARCs is also demonstrated.

The 2007 International Technology Roadmap for Semiconductors (ITRS)1 specifies Extreme Ultraviolet (EUV)
lithography as one leading technology option for the 32nm half-pitch node, and significant world wide effort is being
focused towards this goal. Readiness of EUV photoresists is one of the risk areas. In 2007, the ITRS modified
performance targets for high-volume manufacturing EUV resists to better reflect fundamental resist materials challenges.
For 32nm half-pitch patterning at EUV, a photospeed range from 5-30 mJ/cm2 and low-frequency linewidth roughness
target of 1.7nm (3σ) have been specified. Towards this goal, the joint INVENT activity (AMD, CNSE, IBM, Micron,
and Qimonda) at Albany evaluated a broad range of EUV photoresists using the EUV MET at Lawrence Berkeley
National Laboratories (LBNL), and the EUV interferometer at the Paul Scherrer Institut (PSI), Switzerland. Program
goals targeted resist performance for 32nm and 22nm groundrule development activities, and included interim relaxation
of ITRS resist performance targets. This presentation will give an updated review of the results. Progress is evident in
all areas of EUV resist patterning, particularly contact/via and ultrathin resist film performance. We also describe a
simplified figure-of-merit approach useful for more quantitative assessment of the strengths and weaknesses of current
materials.

Over a period of last several years 193 nm immersion lithography from a remote and unlikely possibility
gradually became a reality in many fabrication facilities across the globe and solid candidate for high volume
manufacturing for the next generation technology node. It is being widely understood in the industry that top-coatless
resist approach is a desirable final stage of the immersion process development. However creating low-defect high
performance top-coatless resist materials requires understanding of the fundamental material properties of the top layer,
responsible for leaching suppression, immersion fluid meniscus stability, and in this way enabling high speed low-defect
scanning.
While a lot of progress has been made in implementing specific top coat materials into the process flow, clear
understanding effects of the top coat properties on the lithographic conditions and printing capability is still lacking. This
paper will discuss top coat materials design, properties and functional characteristics in application to novel
fluoroalcohol polymer-based immersion top coat.
We have used our fluoroalcohol based-series designs (titled MVP top coat materials further on in the paper) as a
test vehicle for establishing correlations between top coat performance and its physical and chemical properties including
hydrophobicity, molecular weight/dispersity etc. Effects of polymer-solvent interactions on the contact angle and
characteristics of the top coat material are explored, providing valuable understanding transferable to design of new
generation top coats and top-coatless materials. Our resultant new designs demonstrated excellent lithographic
performance, profiles and low leaching levels with commercially available resist and high receding contact angles,
comparable to the commercial top coat materials.

Scatterometry is emerging as a prominent metrology technique for lithography. Not only does scatterometry produce
line profile information such as sidewall angle and height along with line width, but the speed and nondestructive
nature of scatterometry accommodates in-line process applications. Scatterometry systems employ reflectometry or
ellipsometry to acquire spectra resulting from the interaction of the input radiation and a symmetrical grating array.
The systems may use fixed wavelengths or a range of wavelengths. The output spectral data is dependent on the
material and physical properties of the grating array and surrounding (subsurface, film stack) material layers. Typical
scatterometry draws on mathematically modeled spectra from known optical and physical parameters such as the
grating pitch and the index of refraction and absorption coefficient functions of the film stack materials. The optical
properties of the materials in the film stack are of particular interest and critical to scatterometry. Material vendors
typically supply constants associated with the optical dispersion models of resists and anti-reflective coatings used in
lithography. These constants are most often based on a Cauchy model for optical dispersion, a very simple model.
However, the optical properties of the photoresist or other coatings may not fit well to a Cauchy model or they may
change during process baking, exposure or just from aging. To make an accurate scatterometry model for patterned
photoresist, the material characteristics must also be modeled. Using these parameters, an accurate picture of the
lithographic materials can be generated. These methods can be applied to both dry and immersion lithography.
As immersion lithography gains a foothold in the manufacturing line, many initial processes will use standard dry
photoresist with the application of an immersion topcoat to protect the final lens element of the lithography tool, and
to reduce defects formed from substances leaching out of the photoresist. Although the goal for an immersion topcoat
is to be neutral to the resist process in terms of profiles, process windows, and CD control, many topcoats are not
completely benign. Topcoat induced resist thinning is a common but unwelcome attribute. In this paper we discuss the
use of scatterometry to characterize topcoat induced thickness changes, and use this technique to evaluate several
commercially available products. We will also demonstrate the ability of scatterometry to accurately determine resist
profile changes as a result of focal changes, topcoat interactions, and airborne contamination. Measurement stability
results are also shown, and correlation to CD-SEM and cross-section SEM are provided as a reference metrology.

The ability to extend 193 nm lithography resolution depends on increasing the numerical aperture (NA) of the exposure system, resulting in smaller depth of focus, which subsequently requires use of thinner photoresists. Bottom antireflective coatings (BARCs) are a necessity, but the organic composition of current 193 nm BARCs offers poor etch selectivity to the photoresist. As a result, image transfer with thin resists is becoming increasingly difficult. It is also more challenging to control reflectivity at high numerical apertures with a thin, single layer BARC.
To address these issues, IBM has developed a new class of silicon containing BARCs. These materials exhibit high etch selectivity that will significantly improve the performance of high NA 193 nm lithography. The incorporation of silicon in the backbone of the polymers comprising these BARCS affords a high etch selectivity to conventional organic resists and therefore these polymers can be used as thick planarizing BARCs. The optical constants of these BARCs have been tuned to provide good reflectivity control at NA > 1.2 These materials can also be used as part of a dual layer BARC scheme composed of the thin organosilicon based BARC coated over a planarizing organic underlayer. This scheme has also been optically tuned to provide reflectivity suppression at high incident angles. By utilizing a thick BARC, a novel contact hole shrink process is enabled that allows tapering of the sidewall angle and controlling the post-etch critical dimension (CD) bias. Structures of the silicon containing polymer, formulation chemistry, optical tunability, lithography at high NA and RIE pattern transfer are reported.

Successful developer-soluble topcoats have to fulfill numerous requirements; specifically they have to serve as a barrier layer and be compatible with the resist. Some of the requirements and compatibility issues have been understood; others are still under-investigation by the joint efforts of lithographers and resist chemists. This paper addresses these requirements from the perspective of overall lithographic performance for developer-soluble topcoats used in 193nm water immersion lithography. We demonstrate that with the optimized combination of resist and developer-soluble topcoat 90nm 1:1 dense lines can be printed using a prototype tool, ASML AT 1150i, and a binary image mask (BIM) with a maximum depth-of-focus (DOF) of ~1.2μm. An approximate 2X DOF improvement over dry lithography that was theoretically expected has been truly demonstrated. Topcoat related defectivity as well as defect reduction efforts are also discussed.

The interaction of water with the photoresist film stack is proving to be a key factor in the current generation of 193-nm immersion lithography. Photoresist performance, CD control, optics lifetime, defectivity, overlay and possibly even tool throughput can all be affected by this interaction. Defect control has been an area of increasing concern as the source of the defects can be quite different than that found in conventional dry lithography [1]. Defects can originate from the UPW (Ultra Pure Water) either as particulates or as dissolved solids that precipitate from residual droplets left behind after scanning. Another source of defects can be particulates generated by the immersion fluid as it flows through the exposure tool or as a consequence of water contact with the resist film or resist/topcoat film stack. Recently there have been reports of printable defects due to stains or "watermarks" on the surface of the photoresist [2]. In this report we describe techniques for the visualization of watermarking and particulate formation on a variety of film surfaces. We also describe experiments testing the staining of a variety of water contaminants and additives and their effect on imaging performance. We will also describe the effect of different topcoats on imaging and defectivity in terms of their surface properties.

Immersion Lithography continues to get more and more attention as a possible solution for the 45nm technology node puzzle. In 2005, there has, indeed, been a lot of progress made. It has gone from a laboratory curiosity to being one of the industry's prime contenders for the lithography technology of choice for the 45nm node. Yet a lot of work remains to be done before it's fully implemented into production. Today, there are over a dozen full field immersion scanners in R&D and pilot lines all around the world. The first full field, pre-production "Alpha" version of the ASML Twinscan AT 1150i was delivered to Albany NanoTech in August, 2004. A consortium made up of AMD, IBM, Infineon, and Micron Technology began early evaluation of immersion technology and in December of 2004, the production of the world's first Power PC microprocessor using immersion lithography, processed on this tool, was announced by IBM.
This paper will present a summary of some of the work that was done on this system over the past year. It will also provide an overview of Albany NanoTech, the facility, its capabilities, and the programs in place. Its operating model, which is heavily focused on cooperative joint ventures, is described. The immersion data presented is a review of the work done by AMD, IBM, Infineon Technologies, and Micron Technology, all members of the INVENT Lithography Consortium in place at Albany NanoTech. All the data was published and presented by the authors in much more detail at the 2005 International Symposium on Immersion Lithography, in Bruges, Belgium.

To evaluate the effect of water exposure to a resist stack a set of experiments was designed that introduce a pre- and post-exposure wetting time to a coated wafer. The ASML 1150i α-immersion scanner, integrated with a TEL-Lithius coater track, was used to investigate the formation of defects related to the extended wetting. In the first approach, wetting was achieved using a dynamic DI-water rinse in the developer module of the track. For the second approach the immersion hood was positioned over the wafer at a fixed position and time, subjecting the wafer area below the immersion hood to the flowing water. We investigated various resists and topcoats. Defect inspections were performed on these film stacks after imaging.

To make immersion lithography a reality in manufacturing, several challenges related to materials and defects must be addressed. Two such challenges include the development of water immersion compatible materials, and the vigorous pursuit of defect reduction with respect to both the films and the processes. Suitable resists and topcoats must be developed to be compatible with the water-soaked environment during exposure. Going beyond the requisite studies of component leaching from films into the water, and absorption of water into the films, application-specific optimization of photoresists and top coats will be required. This would involve an understanding of how a wide array of resist chemistry and formulations behave under immersion conditions. The intent of this paper is to compare lithographic performance under immersion and dry conditions of resists containing different polymer platforms, protecting groups, and formulations. The compatibility of several developer-soluble top-coat materials with a variety of resists is also studied with emphasis on profile control issues. With respect to defects, the sources are numerous. Bubbles and particles created during the imaging process, material remnants from incomplete removal of topcoats, and image collapse as related to resist swelling from water infusion are all sources of yield-limiting defects. Parallel efforts are required in the material development cycle focusing both on meeting the lithographic requirements, and on understanding and eliminating sources of defects. In this paper, efforts in the characterization and reduction of defects as related to materials chemistry and processing effects will be presented.

Critical lithographic dimensions will soon place particularly severe demands on the performance of chemically amplified (CA) resists. Although Extreme Ultraviolet (EUV) and 193 nm (immersion interferometric) lithographic results have demonstrated half pitch imaging down to 35 nm there is nonetheless a concern that image blur due to acid diffusion will begin to seriously impact the utility of CA photoresists. Previously we demonstrated that low activation energy resists and E-Beam lithography can be used to print line/space arrays with resolution approaching 20 nm. We described the factors impacting the reactivity of ketal/pHOST based resists and compared the attainable resolution under different processing conditions. In this report we describe studies on acid diffusion emphasizing the role of water in low Ea systems. We also discuss methods for the control of water absorption in low Ea resists.

Immersion lithography has emerged as the leading solution for semiconductor manufacturing for the 45nm node. With the emergence of the first full-field immersion lithography scanners, the technology is getting ready to be inserted in semiconductor manufacturing facilities throughout the world. In the initial implementation phase, the enhanced depth-of-focus provided by immersion will be utilized to mitigate the narrow process window in which leading-edge semiconductor manufacturing has been forced to operate, creating a new set of opportunities.1 The area of defects, however, has remained of critical concern for this technology. It has become clear that the ultimate proof of the readiness of immersion, especially from a defect point of view, must be attained by integrating the immersion process in a production environment. In this paper, we demonstrate that fully functional 90nm PowerPCTM microprocessors have been fabricated using immersion lithography for one of the litho-critical via levels, achieving the goal of confirming that immersion lithography is a viable manufacturing solution. For this demonstration, we utilized the AT1150i (ASML), currently at Albany NanoTech (NY). The system is a 0.75 NA full-field 193nm projection (4x) scanner. We were able to achieve lithographic and overlay performance that exceeded product specifications while achieving a sufficiently low defect count so as to have yielding chips and modules. We have classified the leading types of defects that can be attributed to the immersion process and have assessed their processing impact. Electrical characterization of the integrated devices confirmed full functionality at both wafer final test (WFT) and module test (MT).

The mask fabrication industry is slowly migrating to chemically amplified (CA) resists to take the advantages of their high contrast, resolution, and sensitivity. During this migration process, the industry has encountered several problems associated with CA resists such as baking homogeneity of thick mask plates on hot plates, footing on Cr masks, and storage stability of mask blanks. In addressing these issues, we have adopted a low Ea CA resist platform to overcome the bake latitude issue. The resist formulation has been reformulated to reduce the footing and a new package method has been introduced to extend the storage of the blanks. In addition, we will also discuss our studies on two major areas, such as sensitivity and etch resistance, which we think is extremely important for E-beam resists in the future. The mask industry started with 248nm DUV CA resist systems and then found out that there was a need for even higher sensitivity resist systems to address the throughput issue. In our early study, we have observed that by simply increasing photoacid generator loading in the resist formulation we were able to increase the sensitivity, but there was a significant reduction in the dose latitude. After studying the dissolution and inhibition properties of different PAGs, we have been able to optimize PAG and base loading in combination with proper choice of PAGs to achieve high sensitivity and large dose latitude. The new resist formulation exhibits a large dose latitude of 38% for 100 nm l/s images with high sensitivity of 4.4μC/cm2 at 100 kV. Due to the electron scattering effect and the image collapse issues with thicker resists, thinner imaging layer is desirable. Sufficient etch selectivity is needed to compensate the insufficient resist thickness. Therefore, there is a need to develop a high Cl2/O2 RIE (used in Cr etch process) etch resistant resist system for mask making. We have reported earlier that a resist formulation based on blending KRS-XE with SSQ polymer has resolved 50nm l/s resist images with etch rate 20% better than conventional novolak I-line resist systems. Since then, we have investigated a few new SSQ polymers and found some lithographic improvement in this new blending systems due to better compatibility of the SSQ polymer to the KRS-XE.

While evaluating 193 nm, and early versions of 157 nm and EUV resists, the lithography community has focused on post-develop LER values derived from image analysis of top-down SEM micrographs. These numbers, however, do not capture the tendency of a resist to facet and roughen during plasma etching processes. They also do not convey any information about the role of the anti-reflective coatings/hard masks in the transfer of resist roughness into the underlying substrate. From a manufacturing perspective, it is the "LER" of the final etched substrate that is more important. This paper systematically studies the impact of resist polymer platform and thickness, etching conditions, and presence of organic and inorganic anti-reflective coatings/hard masks on substrate roughening. An AFM technique, previously developed by Reynolds and Taylor, is used to measure the feature sidewall roughness as a function of etch depth. This technique enables us to calculate the sidewall roughness of the resist, ARC/hard mak and substrate surfaces simultaneously, and determine correlations that may exist between these values. The paper identifies and demonstrates patterning methodologies that can be used to achieve "smooth" substrate surfaces even when the resist is "thin".

Extending 193nm lithography to well below 100nm resolution will depend on high NA tooling coupled with thin resist processing. Semiconductor manufacturing uses BARC's (Bottom Antireflective Coating) based on organic spin coatable polymers, to improve the resolution by absorbing light that otherwise will be reflected back into the resist. However, the use of organic BARC's for patterning sub 100nm features will be limited due to poor etch selectivity to the photo resist. IBM has developed a new class of polymers that can function as planarizing BARC's. These materials show an etch selectivity to the photo resist in excess of 3:1 in fluorocarbon based ARC-open RIE chemistry. The hardmask properties of these materials for oxide open are equivalent to typical resists. Furthermore these materials can be implemented like organic ARC's and are stripped in resist strips available in manufacturing. Basic materials characterization data, optical tunability, lithographic performance with different resists, process window data, and complete integration schemes will be presented.

The importance of hardmask technology is becoming increasingly evident as the demand for high-resolution imaging dictates the use of ever-thinner resist films. An appropriately designed etch resistant hardmask used in conjunction with a thin resist can provide the combined lithographic and etch performance needed for sub-100 nm device fabrication. We have developed a silicon-based, plasma-enhanced chemical vapor deposition (PECVD) prepared material that performs both as an antireflective coating (ARC) and a hardmask and thus enables the use of thin resists for device fabrication. This ARC/hardmask material offers several advantages over organic bottom antireflective coatings (BARC). These benefits include excellent tunability of the material's optical properties, which allows superior substrate reflectivity control, and high etch selectivity to resist, exceeding 2:1. In addition, this material can serve as an effective hardmask etch barrier during the plasma etching of dielectric stacks, as the underlying silicon oxide etches eight times faster than this material in typical fluorocarbon plasma. These properties enable the pattering of features in 1-2 μm dielectric stacks using thin resists, imaging that would otherwise be impossible with conventional processing. Potential extendibility of this approach to feature sizes below 100nm has been also evaluated. High resolution images as small as 50nm, have been transferred into a 300nm thick SiO2 layer by using Si ARC/hardmask material as an etch mask. Lithographic performance and etch characteristics of a thin resist process over both single layer and index-graded ARC/hardmask materials will be shown.

Line edge roughness (LER) has been widely perceived to be one of the roadblocks to the continuing scaling of semiconductor devices. However, little evidence has been published on the impact of LER on device performance, particularly on the performance and the reliability of advanced interconnects. In this paper, we present such evidence from both the Front-End-Of-Line (FEOL) and Back-End-Of-Line (BEOL) standpoints. In the FEOL, we employed computer simulations to estimate the effects of LER on a number of performance parameters of sub-100nm transistors based on 2-dimensional and 3-dimensional device models. LER has been shown to affect both the average value and the variance of key device performance parameters for sub-100nm transistors. In the BEOL, we investigated the impact of LER on the performance of barrier layers in dual damascene copper interconnects. To this end, we emulated LER by roughening Si surfaces with controlled patterning by self-assembled diblock copolymers and reactive ion etching. In-situ time-resolved X-ray diffraction was used to study Cu diffusion through about 5nm Ta and TaN barrier layers deposited by plasma enhanced-atomic layer deposition (PE-ALD) on both smooth and rough surfaces. The X-ray diffraction results indicated that the surface roughness does not degrade barrier performance of the ALD Cu barriers. Mechanism of the roughness effects is also discussed. Line edge roughness is, however, expected to degrade copper interconnect performance by increasing copper electrical resistivity through enhanced electron surface scattering.

KRS-XE, a high performance chemically amplified photoresist designed specifically for e-beam mask making applications, has been enhanced to achieve reduced “footing” on chrome oxide surfaces while still maintaining the original lithographic characteristics that make KRS-XE a promising mask making candidate. These attributes include high resolution, superior bake latitudes, high vacuum stability, coated shelf life of greater than 2 months, and, most notably, the absence of a post exposure bake. In conjunction with the footing reduction the requisite sensitivity requirement of <10uC/cm2 with 50 keV exposure tools has been achieved while retaining the robust process latitude previously reported for this resist. Through a careful study of the photoresist formulation components a route to the ultra-high sensitivity of <2.5uC/cm2 at 50 keV has been elucidated which will further enhance throughput, decrease heating effects, and potentially be a suitable resist for e-beam projection lithography (EPL).

KRS-XE is a chemically amplified resist developed to enable electron-beam lithography for mask making at the 100nm node. This material has been shown to provide an excellent process window for mask manufacturing at this node. Characterization of this material using both 50keV raster and 75keV vector scan e-beam exposure systems will be presented. A higher sensitivity version of this material has been developed specifically for a vector, shaped beam 50keV application. Initial mask manufacturing results for this higher sensitivity version of KRS-XE will be presented for 75keV. In addition, recent developments using KRS-XE formulations modified to achieve high sensitivity and improved etch resistance will be discussed.

Extending current lithography capability in the case of severe topography is desired in trench-first dual-damascene process. We demonstrate a solution of applying the RELACS process on DUV bi-layer resist system to provide a planarization material with CD shrinkage ability. By combining these two commercially available processes, the cost saving of contact-reducing techniques can be realized on wafers with aggressive topography. The main results presented in this study include (1) process window of the bi-layer/RELACS is comparable with that of the bi-layer only process. (2) Across wafer CD uniformity of the bi-layer/RELACS process is improved compared to that of the bi-layer process alone. Further etch steps does not degrade CD uniformity either. Nice post etch across CD uniformity and cross-section photos from post etch show the image resist still retains enough etch resistance after RELACS process. (3) Among all geometry in this study, the maximum difference from two orientations is 2nm in width and 5 nm in length. (4) Geometry size shows a bigger effect on shrinkage, for the ellipse contacts with aspect ratio 2, it shrinks 14nm more in length direction than in width direction. For contacts with aspect ratio 1.3, the shrinkage difference between width and length is relative small (about 2nm). (5) Total CD shrinkage in the range of 40 to 60nm has been achieved. Baking temperature sensitivity is measured to be about 1.3 nm/ degree(s)C. The value of temperature sensitivity suggests possible lot-to-lot, wafer-to-wafer and across wafer CD control for mass production. (6) A set of horizontal contacts is employed for pitch dependency studies. From pitch size changes from 450nm to 700nm in length direction, the length shrinkage changes by 8% of the target CD. And for pitch size changes from 450nm to 850nm in width direction, the width shrinkage changes by 9% of the CD target. Post RELACS OPC may be necessary for critical cases to compensate the pitch dependency of CD changes.

Over the years for enhanced resolution, electron beam exposure tools have migrated to higher accelerating potentials. High kV exposure requires faster resist to offset the loss of absorbed radiation. In addition, in order to maintain throughput in mask writing tools, photoresist sensitivities of the order of 5(mu) C/cm2 at 50 kV are needed and likewise 5 (mu) C/cm2 at 100 kV for projection exposure tools. To meet this sensitivity requirement there is a keen interest in using chemically amplified resists (CAR). The CAR resists offer additional benefits such as high contrast, improved resolution, larger process windows, and dry resistance. This study is focused on enhancing the sensitivity of a low activation ketal protected polyhydroxystyrene. One such resist, which has been reported previously, is insensitive to the post apply bake temperature and does not require a post exposure bake. To enhance the resolution, process latitudes, and chemical contrast, base quenchers are usually added to limit the diffusion of the acid after exposure. To improve the sensitivity of the formulation, the effect of the acid generator (AGX), type of base, base concentrations and ratios in combination with the polymer protection level has been studied. Yields of acid formed were measured by titration and NMR. It was also found that both the AGX and base has an inhibition effect on dissolution. By increasing the among of AGX and decreasing the polymer protection level, the sensitivity of the formulation was improved while maintaining the resist contrast, resolution, vacuum stability, and bake latitudes. In addition, the sensitivity of the resist can be altered by quantity and type of added base. We have also investigated the effect of Pka of the base on the sensitivity, and process exposure latitude. The ionic onium acid generators or non ionic hydroxyimides provide adequate acid when coupled with adjusted concentrations of base to achieve 5 (mu) C/cm2 at 100 kV.

Several contact hole shrinking techniques have been discussed in the literature recently. Two notable techniques; Resolution Enhancement Lithography Assisted by Chemical Shrink (RELACSTM) and Resist Flow Process (RFP) were investigated in conjunction with several commercially available high activation energy chemically amplified materials and one bilayer material. During the course of this study the unique set of advantages along with the inconveniences associated with each technique were explored. It was not only the lithographic attributes of each technique that were of interest, but also characteristics that would effect manufacturability. To that end, experiments were designed so that standard statistical techniques could be employed at the data analysis stage. The attributes of interest were the amount and control of shrinkage, nested and isolated feature bias, process window comparisons, and line edge roughness. It will be shown how several of theses attributes are directly related to manufacturing issues such as lot-to-lot repeatability and linewidth variations across the wafer.

Recently, there is significant interest in using chemically amplified (CA) resists for electron beam (E-Beam) applications including mask making, direct write, and projection printing. CA resists provide superior lithographic performance in comparison to traditional non CA E-beam resists in particular high contrast, resolution, and sensitivity. Due to the electron scattering effect and the image collapse problem, thinner imaging layer is desirable. Sufficient etch selectivity is needed to compensate reduced resist thickness. Therefore, there is a need to have a high etch resistant resist system which can survive Cr etch (Cl2/O2RIE etchant) process in mask making. For device making, the thin film bilayer approach needs a resist that can withstand O2 etch for image transfer to the underlayer. We have found Si-O containing polymer has the etch characteristics for both applications. In the first approach, using a blend of KRS-XE and silsesquioxane polymer, we have been able to resolve resist images down to 50nm with etch rate 20% slower than conventional novolak I- line resist systems. In the second approach, we have investigated the copolymer of vinyl phenol and acrylate siloxy silane systems. Superior litho performance and etch properties have been observed. In this presentation, we will discuss the chemistry, the miscibility in blends, etch characteristics and lithographic performance of these resist systems.

The traditional mask making process uses chain scission-type resists such as PBS, poly(butene-1-sulfone), and ZEP, poly(methyl a-chloroacrylate-co-a-methylstyrene) for making masks with dimensions greater than 180nm. PBS resist requires a wet etch process to produce patterns in chrome. ZEP was employed for dry etch processing to meet the requirements of shrinking dimensions, optical proximity corrections and phase shift masks. However, ZEP offers low contrast, marginal etch resistance, organic solvent development, and concerns regarding resist heating with its high dose requirements1. Chemically Amplified Resist (CAR) systems are a very good choice for dimensions less than 180nm because of their high sensitivity and contrast, high resolution, dry etch resistance, aqueous development, and process latitude2. KRS-XE was developed as a high contrast CA resist based on ketal protecting groups that eliminate the need for post exposure bake (PEB). This resist can be used for a variety of electron beam exposures, and improves the capability to fabricate masks for devices smaller than 180nm. Many factors influence the performance of resists in mask making such as post apply bake, exposure dose, resist develop, and post exposure bake. These items will be discussed as well as the use of reactive ion etching (RIE) selectivity and pattern transfer.

The performance of KRS-XE, a low activation energy, chemically amplified resist designed specifically for mask making with electron beam lithography, has been extended in terms of its sensitivity, coated-film stability and etch resistance. By careful manipulation of resist composition, high sensitivity formulations have been generated that will allow exposure doses of less than 10 mC/cm2 with 50 keV electron beam tools. This sensitivity enhancement has been achieved without sacrificing the robust process latitude previously reported for this resist. The performance of this resist can be maintained, even in coated film form, for prolonged periods of time by careful packaging of the coated films. Additionally, formulations with etch resistance versus chlorine/oxygen plasma in excess of that of novolak-based resists have been generated by the incorporation of organometallic additives. The combination of these improvements leads to resist formulations that will allow the high resolution and throughput that is demanded for state-of-the art mask making applications.

This paper presents data obtained in developing a process using 193 nm lithography and the RELACS contact hole shrink technique. For the line/space levels, process windows showing resist performance using chrome on glass masks are presented. Data showing feature size linearity and the requirements for optical proximity correction (OPC) are presented. Some of the OPC trends observed are discussed and compared to results obtained using 248 nm lithography. Image shortening data also compares the results obtained in 193 and 248 lithography. Etch results for the new 193 resists are given and show the etch resistance of this relatively new class of photoresist materials. For contact hole and via levels, results using 193 lithography and COG masks show the importance of the mask error enhancement factor (MEEF), print bias and resolution. Due to the relative immaturity and performance of contact hole resists for 193 lithography, Clariant's RELACS process was investigated with 248 nm resists. In this process contact holes are printed larger than required and then reduced to the desired size by a chemical shrink process. Results obtained with 248 lithography using state of the art resists and phase shift masks are discussed. It was found that 140 nm contact holes with at least 0.5 micrometer depth of focus could be obtained. Cross sections and process windows are shown.

Silicon-containing bilayer thin-film imaging resists versus single layer resists for a variety of different mask types, from both a focus-expose window, etch selectivity, and process integration perspective are examined. Comparable lithographic performance is found for 248 nm single layer and bilayer resists for several mask levels including: a 135 nm dense contact/deep trench mask level, a 150 and 125 nm equal line space mask printed over trench topography, and dual damascene mask levels with both vias and line levels. The bilayer scheme is shown to significantly relax the dielectric to resist etch selectivity constraint for the case of a dense contact or trench hardmask level, where high aspect ratio dielectric features are required. Only a bilayer resist scheme in combination with a transfer etch process enables the line/space pattern transfer from the imaging layer to the bottom of a trench with a combined aspect ratio > 10. When the single layer resist depth of focus window is limited by both the topography and variations in the underlying dielectric stack thickness, as is the case for the dual damascene via and line levels, bilayer resist is shown to be a practical alternative.

Recently, there is a significant interest in using CA resists for electron beam (E-beam) mask making application. CA resists provide superior lithographic performance in comparison to traditional non CA E-beam resists in particular high contrast, resolution, and sensitivity. However, most current CA resists exhibit very large sensitivity to PAB and/or PEB temperatures resulting in significant impact on CD. In addition, image collapse issues associated with high aspect ratio patterning as well as electron scattering effects in low KeV tools necessitate thinner resists. Therefore, there is a need to have a high etch resistant resist system which can withstand the demanding chrome etch process. Previously, we reported on the KRS-XE resist which exhibits dry etch resistance comparable to the best deep UV resist and excellent lithographic performance and bake latitudes. No PEB is needed for this resist. In this paper, we report on an advanced KRS-XE resist formulation which exhibits dry etch resistance surpassing the industry standard, novolak, in the chrome etch process. This new resist also exhibits excellent lithographic performance - 50nm lines/space delineated and requires no PEB. This paper will highlight the lithographic and etch performance of this new resist.

As thin film imaging becomes an accepted means of producing high-resolution microelectronics features, a host of new challenges has emerged. A dose dependence on resist thickness has been observed and systematically measured for chemically amplified resists exposed with 75 keV electron beam radiation. The required dose to print 100nm images increased as the thickness of the film decreased. A physiochemical explanation for this dependence was sought which included exploring thickness-induced variations in thermal characteristics of the resist film. Over the range of film thickness examined, 80-360nm, these parameters were deemed unlikely contributors to this phenomenon. Ultimately the data suggests that the dose variation with thickness may correlate to differences in the population of chemically effective electron with energies in the range of 10 to 100 eV that are responsible for the sensitization of electron beam resists.

Patterning sub-150 nm features in dielectric stacks using single layer resist processes in conjunction with organic anti-reflective coatings (ARCs) is becoming very difficult. Typical organic ARC-open etch processes suffer from poor ARC-to-resist selectivities (~0.7), and are accompanied by critical dimension (CD) losses. The resist remaining is often not sufficient to prevent artifacts such as substrate microrevicing during subsequent etches. PECVD-Deposited titanium nitride and silicon oxynitride films have been investigated as ARC layers but their basic nature has caused residue formation at the resist/ARC interface. We have developed a PECVD-deposited material, TERA (Tunable Etch-Resistant ARC) that acts as an ARC at 248 nm and 193 nm wavelengths and provides excellent etch selectivity to resist surpassing those attained with organic ARCs. In addition, this material demonstrates excellent hard mask properties for subsequent dielectric etch steps. The optical properties of these films can be easily tuned to minimize substrate reflectance at either imaging wavelength by controlling the precursor composition and deposition conditions. The films are compatible with 248 nm and 193 nm resists - no footing, undercut or residue is observed during patterning. The films can be etched selectively to resist (selectivity ~2.5) that translates to less resist consumption during th ARC-open etch. Compared to resists, TERA demonstrates better etch resistance while patterning dielectric stacks - the silicon oxide-to-TERA Selectivity exceeds 8. In this paper, the excellent optical tunability and substrate reflectivity control achieved with TERA are discussed. Clean lithography using 248 nm, 193 nm and e- beam resists is shown. The etch characteristics of TERA in fluorocarbon and halogen-based plasma chemistries are discussed. Finally, the formation of 135 nm and 120 nm deep trench patterns in thick dielectric stacks using TERA in conjunction with commercial 248 nm and 193 nm resists, respectively is demonstrated. The extendability of this approach to pattern silicon without roughening or microrevicing using sub-200 nm thick resists is motivated.

Recently, there is significant interest in using CA resists for electron beam (E-Beam) applications including mask making, direct write, and projection printing. CA resists provide superior lithographic performance in comparison to traditional non CA E-beam resists in particular high contrast, resolution, and sensitivity. However, most current CA resists exhibit very large sensitivity to PAB and/or PEB temperatures resulting in significant impact on CD control. In addition, image collapse issues associated with high aspect ratio patterning as well as electron scattering effects in low KeV tools necessitate thinner resists. Therefore, there is a need to have a high etch resistant resist system that can withstand the demanding chrome etch process. Previously, we reported on the KRS-XE resist which exhibits dry etch resistance surpassing the industry standard, novolak, in the chrome etch process. This new resist also exhibits excellent lithographic performance - 75 nm lines/space and 55nm/110 space/lines delineated and requires no PEB. This paper will highlight the lithographic and etch performance of this new resist.

Bilayer thin film imaging is one approach to extend 248 nm optical lithography to 150 nm regime and beyond. In this paper, we report our progress in the development of a positive-tone bilayer resist system consisting of a thin silicon containing imaging layer over a recently developed crosslinked polymeric underlayer. The chemically amplified imaging layer resist is based on a novel dual-functional silicon containing monomer, tris(trimethylsilyl)silylethyl methacrylate, which in addition to providing etch resistance, also functions as the acid sensitive functionality. The stabilization of (beta) -silyl carboncation by silicon allows this moiety to serve as an acid sensitive protecting group. Thus high silicon content and high resist contrast are achieved simultaneously. Lithographic evaluation of the bilayer resist with a 0.63 NA and a 0.68 NA 248 nm exposure tool has demonstrated resolution down to 125 nm equal line/space features with a dose latitude of 16 percent and depth of focus (DOF) of 0.6 um. The dose latitude and DOF for 150 nm equal line/space features are 22 percent and 1.2 um, respectively. Finally, residue-free, ultra-high aspect ratio resist features have been obtained by O2 or O2/SO2 reactive ion etching using a high-density plasma etch system. The resist design, deprotection chemistry, lithographic and etch characteristics of the top layer, as well as the design of the new underlay, will be discussed.

The five major requirements for electron beam resists for chrome mask fabrication include high resolution, high speed, RIE etch resistance, thermal bake insensitivity, and long coated plate shelf life. High speed, high resolution and good RIE resistance are common attributes of chemically amplified resists (CAR) used primarily for Deep UV lithography. However, the environmental susceptibility to airborne amines, need for a long coated plate shelf life and the requirement for 140 Celsius postexpose bake (PEB) of some CAR or fundamental challenges of these families of resist for practical Cr lithography. We have been developing a series of fast amplified e beam resists which exhibit do not require PEB bake and are tolerant of airborne contaminants. The shelf life attributes of both negative and positive chemically amplified resists was examined and found to be susceptible to absorption of moisture. Some of the acid generators hydrolyzed in the dried films and led to changes in resist sensitivity or dark film loss. Long term film stability of CAR coated plates can be promoted by using hydrophobic solvents, stable acid generators, and most effectively by storage under anhydrous conditions.

We have designed and developed new silicon containing methacrylate monomers that can be used in bilayer resist systems. New monomers were developed because the commercially available silicon monomers were found to be unsuitable for our applications. During the course of the investigation we determined that these monomers were acid labile. We have developed a high resolution DUV bilayer resist system based on these monomers. Although most of our work was concentrated on 248 nm lithography, we have demonstrated that this chemistry can be extended to 193 nm applications.

Thin film interference plays an important role in critical dimension control of single layer resists causing large changes in the effective exposure dose due to small changes in optical phase. To overcome these problems bilayer resists have been proposed. Advantages to such systems include enhanced process latitude, enhanced resolution, and improved critical dimension control due to minimization of substrate reflectivity. In this paper, we have investigated the effects of the underlayer with respect to the optical properties as well as the chemical composition on the performance of bilayer resists for 248 nm lithography. The optimum optical constants (index of refraction n((lambda) ) and extinction coefficient k((lambda) )) of the underlayer were deduced by simulations. It was also found that with some underlayers, the optical properties could be tuned by controlling the processing conditions. Novolaks have been found to interact with the resist resulting in significant residue limiting the resolution of the 248 nm bilayer resist to 150 nm. Properly designing the underlayer with suitable optical constants and preventing resist/underlayer interaction resulted in 125 nm resolution with a 248 nm bilayer resist. We also investigated the use of an amorphous diamond-like carbon film as an underlayer material. Thin films, deposited by plasma enhanced chemical vapor deposition, offers advantages over spin on hard baked polymers because it can be deposited conformally with high optical purity. Furthermore, the composition and optical properties can be fine-tuned by changing the process parameters.

A negative-tone bilayer thin film imaged (TFI) resist has been developed for extension of 248 nm optical lithography to sub-150 nm regime. The bilayer TFI resist system consists of a thin (0.2 um) silicon containing top imaging layer and a thick (0.7 - 0.8 um) highly absorbing organic underlayer. The chemically amplified negative-tone top layer resist comprises of three major components: an aqueous base soluble silicon containing polymer, poly(hydroxybenzylsilsesquioxane); a crosslinking agent; and a photoacid generator. The highly absorptive underlayer is a hard baked novolak resist or a DUV ARC. Imaging of the top layer resist has shown resolutions down to 137.5 nm for line/space features and 130 nm for isolated features with 248 nm exposure tools and chrome on glass masks. The O2 reactive ion etch (RIE) selectively of the top layers versus a novolak underlayer is more than 25:1 as a result of the high silicon content in the silicon containing polymer. Furthermore, residue-free and nearly vertical wall profile image transfer to the underlayer has been achieved with RIE. Application of the negative-tone bilayer resist to 150 nm Gbit DRAM critical level lithography has been demonstrated. Resist line edge roughness is also discussed.

Non-chemically amplified resists offer advantages over chemically-amplified (CA) resists because they are less susceptible to temperature variations and contaminants. In order for non-CA resists to be viable, they have to perform lithographically at an equivalent level with the CA resists from the point of view of quantum yield, resolution and etch resistance. We report here on new non-CA resists based on polymer esters that undergo deesterification to the corresponding acids upon exposure to UV, x-ray and e-beam radiation. The efficiency of the radiation reaction is surprisingly high. The resulting poly acids are base soluble and can be employed as positive working resists. The resists are composed of polymers and copolymers of methacrylate esters. The sensitivity of one derivative to x-ray is 75 mJ/cm2 and to e-beam is 1.0 (mu) C/cm2 at 10 KV. Best resolution obtained was 125 nm with x-ray radiation.

To advance production processing well beyond 0.30 micrometer design rules, it is considered necessary to introduce deep-UV photolithography. Currently, most deep-UV photoresist systems are based on poly(4-hydroxystyrene) (PHS) resins, which have good thermal properties. When combined with photo-acid generators (PAG) and dissolution inhibitors, the thermal properties of the resulting resists are severely reduced. Since the Tg of these types of advanced resists are in the 100 to 120 degree Celsius region, it is necessary to apply a stabilization process to the resists prior to processing at high temperatures. This study investigates the application of electron beam stabilization processing to deep-UV resist materials. A PHS based deep-UV resist, and a solution of the PHS resin material, have been evaluated to determine the nature of the reactions induced by electron beam exposure. Chemical changes induced in the resist, or resin, are evaluated via FTIR analysis. Changes in optical properties are evaluated using UV/visible reflectance as well as changes in index of refraction. Film shrinkage is determined for all processing conditions. Thermal properties are evaluated by DSC and TGA techniques. The Tg of the processed resist is presented as a function of electron beam exposure. Thermal flow properties are evaluated via SEM cross sections of resist features exposed to high temperatures after electron beam stabilization. Electron beam stabilized films are demonstrated to withstand temperatures in excess of 200 degrees Celsius. The resist or resin materials properties are evaluated as a function of electron beam dose level and stabilization process temperature. Trends in materials properties are evaluated and optimized process conditions are presented for a range of production processing applications.

Accurate stepper setup is essential for getting good overlay performance on product wafers. As part of a typical stepper setup procedure, one or more wafers are exposed, developed, aligned to the initial exposure, and then exposed again in order to determine the x/y baseline position and grid rotation. By removing the wafer from the chuck for processing (baking and development) before the alignment and exposure, both pre-aligner and stage errors are introduced. If the alignment and second exposure could be made without removing the wafer from the stepper chuck, these two sources of error could be eliminated. This is possible if the resist has a strong and immediate latent image after exposure.

Acid catalyzed photoresists have been examined for exposure using the Helios compact synchrotron x-ray source at the IBM Advanced Lithography Facility. A fundamental challenge with these photoresists is the sensitivity to contamination from the environment. This study attempts to optimize a new type of Environmentally Stable Chemically Amplified Photoresist (ESCAP) developed by IBM Almaden Research Center. A key feature of this new resist is that it does not require an extra polymer topcoat to seal out airborne contaminants. The establishment of a base process and then the enhancement of exposure latitude was the main objective of the optimization. A 5 factor Taguchi optimization was designed to test the effects of post exposure bake (PEB) temperature, PEB time, post apply bake (PAB) temperature, PAB time and develop time. Sixteen wafers were utilized to explore 3 levels for each factor. Twenty-four additional wafers were run using the optimized process with slight variations. These were split into 3 runs for an estimate of noise. The second optimization used 4 factors with 3 interactions. The 200, 300, and 500 nm isolated line structures were examined. A test for maximum photospeed pointed to the same optimum region for latitude as well as sensitivity. Across all conditions a 5X change in dose for linewidth was shown while the exposure latitude for the 500 nm varied from 21 to 54%. The slopes fit to the subsequent plots ranged from 2 - 6 nm/mJ. The PEB latitude was seen to be 10 - 14 nm/ degree(s)C.

Excimer laser lithography combined with chemically amplified resists offers a viable approach to lithography at 0.5 micrometers and below. APEX-E, a positive tone deep-uv resist used in conjunction with a 0.44 NA excimer laser stepper is capable of 0.35 micrometers resolution. To improve the process window for this resist while reducing the performance variability, the Taguchi method of quality control was employed. The baseline process for APEX-E was characterized, then subsequently used as a comparison to the optimized process as suggested by the Taguchi experiments.

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Journal of Applied Remote SensingJournal of Astronomical Telescopes Instruments and SystemsJournal of Biomedical OpticsJournal of Electronic ImagingJournal of Medical ImagingJournal of Micro/Nanolithography, MEMS, and MOEMSJournal of NanophotonicsJournal of Photonics for EnergyNeurophotonicsOptical EngineeringSPIE Reviews