EliteTUM

2 years ago

MIDTERM
A linear circuit is shown below.
Pic: http://i45.tinypic.com/206flvd.png
The elements in this circuit have the following values: R1=200Ω, R2=200Ω, R3=100Ω, V1=5V, I1=0.001A and I2=0.005A
Determine the potentials at nodes A and B, assuming a ground node as shown in the figure.
(a) What is the value of voltage vA in Volts?
(b) What is the value of voltage vB in Volts?
Now let us determine if the answers you came up with satisfy the laws of physics.
What is the power (in Watts) dissipated in resistor R1?
What is the power (in Watts) dissipated in resistor R2?

What is the power (in Watts) dissipated in resistor R3?
What is the power (in Watts) coming out of the voltage source V1?
What is the power (in Watts) coming out of the current source I1?
What is the power (in Watts) coming out of the current source I2?

MIDTERM 2
For many purposes of gate design, we can model a MOSFET used as a switch simply as as an ideal switch and an "on-state resistor" RON. This is the SR model.
Assuming this model for the MOSFET, consider the inverter in the figure. This inverter is intended to be used as an element in a logic family with NAND and NOR gates.
Pic: http://i50.tinypic.com/4kgxf9.png
The static discipline required for this family is:
VS=5.0V, VOH=4.5V, VIH=4.0V, VIL=1.5V, VOL=1.0V.
What is the low noise margin (in Volts)?
What is the high noise margin (in Volts)?
What is the width of the forbidden region (in Volts)?
Suppose that the threshold voltage for the MOSFET is VT=2.0V and RON=19000.0Ω.
What is the minimum value of the pullup resistor RPuI (in Ohms) for which this inverter can obey the required static discipline?
Now, consider the NAND gate of this family. What is the minimum value of the pullup resistor RPuA (in Ohms) for which this inverter can obey the required static discipline?
How about the NOR gate of this family. What is the minimum value of the pullup resistor RPuO (in Ohms) for which this inverter can obey the required static discipline?
Assume that we implemented this family with the minimum pullup resistors that you have already calculated.
What is the maximum power (in Watts) consumed by the inverter?
What is the maximum power (in Watts) consumed by the NAND?
What is the maximum power (in Watts) consumed by the NOR?

MIDTERM 3
A nonlinear device Z has the i-v relationship shown below.
Pic: http://i50.tinypic.com/e9vgp5.png
This device is used in the circuit shown below, where "I" is the value of the current source.
Pic: http://i49.tinypic.com/2zs741c.png
Assuming that I=10A, what is the value of the voltage vo (in Volts)?
Now assuming that I=−3A, what is the value of the voltage vo (in Volts)?
Finally, for the last two parts assume that I=5A.
What is the value of the voltage vo (in Volts)?
What is the value of the voltage v1 (in Volts)?

MIDTERM 4
A startup company TransGadget has invented a new type of MOS-gated transistor called ExtremeT. The symbol for ExtremeT and its terminal voltage-current characteristics are given below:
Pic: http://i50.tinypic.com/2lc0n05.png
TransGadget wants to determine the usefulness of their invention by examining the large-signal input-output characteristics of two amplifiers built using ExtremeT. They hire you to figure this out.
First a source follower amplifier is built using ExtremeT, as shown below.
Pic: http://i47.tinypic.com/211nj9y.png
What is the expression for vOUT in terms of vIN, R, and b when vIN is greater than 0V?
ExtremeT is now used to build a different type of amplifier which uses two transistors as shown below.
Pic: http://i50.tinypic.com/rmmn4g.png
What is the expression for vOUT in terms of vIN, VS, R, and b for this amplifier when vIN is greater than 0V?

MIDTERM 5
The startup company TransGadget has also invented a MOS-gated transistor called SuperT, with the symbol and terminal voltage-current characteristics given below.
Pic: http://i45.tinypic.com/2sacjs8.png
Engineers of TransGadget build a common source amplifier using SuperT as shown below.
Pic: http://i47.tinypic.com/xpa7hd.png
Here, VS=80V, R=1.5kΩ, and the transistor parameter f=2mAV3. The amplifier is biased with VIN=2V.
What is the dc operating point (bias) output voltage VOUT (in Volts) of this amplifier?
What is the small signal gain (vOUT/vIN) of this amplifier when it is biased as above?

MIDTERM 6
The circuit below contains two dependent sources: a voltage controlled voltage source and a voltage controlled current source.
Pic: http://i47.tinypic.com/71oj03.png
The circuit elements have the following values: Vin=42V, R1=4Ω, R2=4Ω, R3=7Ω, A=1.5 and B=0.125.
What is the value of the current i1 (in Amps)?
What is the value of the output voltage vOUT (in Volts)?
We wish to create a Thevenin equivalent model of the above shown circuit as seen from its Output Port.
What is the value of the Thevenin equivalent voltage as seen from the Output Port (in Volts)?
What is the value of the Thevenin equivalent resistance (in Ohms) as seen from the Output Port?

Suppose that the threshold voltage for the MOSFET is VT=2.0V and RON=10000.0Ω.
What is the minimum value of the pullup resistor RPuI (in Ohms) for which this inverter can obey the required static discipline?

Suppose that the threshold voltage for the MOSFET is VT=2.0V and RON=10000.0Ω.
What is the minimum value of the pullup resistor RPuI (in Ohms) for which this inverter can obey the required static discipline?

@saadixyz : r1=r2=100,r3=200,i1=0.001,i2= 0.005.dan
1) What is the power (in Watts) coming out of the voltage source \(V_1\)?
2)What is the power (in Watts) coming out of the current source \(I_1\)?
3)What is the power (in Watts) coming out of the current source \(I_2\)?

Assume that we implemented this family with the minimum pullup resistors that you have already calculated.
What is the maximum power (in Watts) consumed by the inverter?
incorrect
What is the maximum power (in Watts) consumed by the NAND?
incorrect
What is the maximum power (in Watts) consumed by the NOR?

sSuppose that the threshold voltage for the MOSFET is VT=2.0V and RON=6000.0Ω.
What is the minimum value of the pullup resistor RPuI (in Ohms) for which this inverter can obey the required static discipline?

The static discipline required for this family is:
VS=5.0V, VOH=4.5V, VIH=4.0V, VIL=1.5V, VOL=1.0V.
What is the low noise margin (in Volts)?
correct
What is the high noise margin (in Volts)?
correct
What is the width of the forbidden region (in Volts)?
correct
Suppose that the threshold voltage for the MOSFET is VT=2.0V and RON=10000.0Ω.
What is the minimum value of the pullup resistor RPuI (in Ohms) for which this inverter can obey the required static discipline?
incorrect
Now, consider the NAND gate of this family. What is the minimum value of the pullup resistor RPuA (in Ohms) for which this inverter can obey the required static discipline?
incorrect
How about the NOR gate of this family. What is the minimum value of the pullup resistor RPuO (in Ohms) for which this inverter can obey the required static discipline?
incorrect
Assume that we implemented this family with the minimum pullup resistors that you have already calculated.
What is the maximum power (in Watts) consumed by the inverter?
incorrect
What is the maximum power (in Watts) consumed by the NAND?
incorrect
What is the maximum power (in Watts) consumed by the NOR?
some one help i always help people here lol

please help me question 3
A nonlinear device Z has the i-v relationship shown below.
This device is used in the circuit shown below, where "I" is the value of the current source.
1. Assuming that I=10A, what is the value of the voltage vo (in Volts)?
2. Now assuming that I=−3A, what is the value of the voltage vo (in Volts)?
Finally, for the last two parts assume that I=5A.
3. What is the value of the voltage vo (in Volts)?
4. What is the value of the voltage v1 (in Volts)?

Solution for q2
VS=5.0 VOH=4.5 VIH=4.0 VIL=1.5 VOL=1.0
The low noise margin is defined as VIL−VOL. For this problem, it is 0.5V. As an example, if an inverter outputs a valid voltage signal of 1.0V (VOL) to another inverter, then that signal can rise by 0.5V all the way to VIL, before it becomes an invalid logical 0 input to the second inverter.
The high noise margin is defined as VOH−VIH. For this problem, it is 0.5V. Again, if an inverter outputs a valid voltage signal of 4.5V(VOH) to another inverter, then that signal can fall by 0.5V, all the way to VIH before it becomes an invalid logical 1 input to the second inverter.
The width of the forbidden region is defined as VIH−VIL. For this problem, it is 2.5V. Valid inputs to our logic family are not allowed to fall between VIH and VIL.
When VGS for the MOSFET is below VT, the MOSFET behaves like an open circuit, and iDS=0. That means no voltage drops over RPUI and the output voltage of our inverter is VS, so this case is fine with out static discipline, since the output voltage is above VOH. For VGS≥VT, the MOSFET is on and behaves like a resistor with resistance RON with our model.
To find RPUI:
VOL=VS(RON)RON+RPUI
1=5(12000.0)(12000.0+RPUI)→RPUI=48000.0Ω
Similar to the inverter case, when either MOSFET is off, no current can flow through the pullup resistor because the MOSFETs and pullup resistor are in series. So VOUT for the NAND gate is simply VS when either MOSFET is off. When both MOSFETs are on, they behave like resistors with resistance RON. The two MOSFETs are in series, so we calculate:
To find RPUA:
VOL=VS(2RON)2RON+RPUA
1=5(24000.0)(24000.0+RPUA)→RPUA=96000.0Ω
When both MOSFETs are off, VOUT for the NOR gate is simply VS because no current can flow through either MOSFET or RPUO. When one MOSFET is on, VOUT is:
VS⋅(0.5)RON(0.5)RON+RPUO
because the MOSFETs are in parallel with each other. For the cases with one MOSFET on or both MOSFETs on, VOUT must be at least as small as VOL. For the case with one MOSFET on, RPUO must be at least 48000.0 Ω. For the case with both MOSFETs on, RPUO must be at least 24000.0 Ω. So for our NOR gate to satisfy the static discipline, RPUO must be at least 48000.0 Ω.
When the MOSFET in the inverter is off, no power is consumed because no current can flow as the MOSFET behaves like an open circuit. When it is on, VS must drop over RPUI and RON, so the power consumed is:
(VS)2RPUI+RON
Power consumed by inverter:
25V12000.0+48000.0Ω=0.000417W
When either MOSFET is off, no current flows through the MOSFETs or RPUA, so there is no power consumed. When both MOSFETs are on, VS must drop over RPUA and 2RON because the MOSFETs are in series with each other. The power consumed in this case is:
(VS)2RPUA+2RON
Power consumed by NAND:
25V2⋅12000.0+96000.0Ω=0.000208W
When both MOSFETs are off, no curernt can flow, so no power is consumed. When one MOSFET is on, VS must drop over RPUO and RON, so the power consumed is:
(VS)2RPUO+RON
When both MOSFETs are on, VS must drop over RPUO and 12 RON because the MOSFETs are in parallel, so the power consumed is:
(VS)2RPUO+0.5(RON)
The maximum power is consumed by the NOR gate in the latter case:
25V(12000.0∥12000.0)+48000.0Ω=0.000463W

Q No 3
Assuming that I=9A, what is the value of the voltage vo (in Volts)?
Now assuming that I=−3A, what is the value of the voltage vo (in Volts)?
Finally, for the last two parts assume that I=4A.
What is the value of the voltage vo (in Volts)?
What is the value of the voltage v1 (in Volts)?