Current projects

Classic CAF (Conductive Anodic Filamentation) is a two-step process, firstly the creation of a pathway by hydrolysis followed by electrochemical filament growth. Where there is no pathway there can be no CAF, hence existing acceleration factor equations which model the process as a single step are clearly incorrect. The project will determine a better acceleration factor equation for CAF and quantify the effects of voltage, temperature and humidity hopefully enabling shorter testing time for CAF material qualification.

The purpose of this project is to determine the effect of varying board thickness on the solder joint reliability (SJR) of a variety of devices that are attached to those boards. Opinions, modeling results, and data on this topic are conflicting. There have been no definitive studies published.

CAF (Conductive Anodic Filamentation) is normally characterized as an effect subject to the influences of design, process and materials. This adds complication to product development for laminate manufactures as lengthy failure analysis is normally required when CAF testing is performed using standard test vehicles. The project aim is to develop a test vehicle that will allow performance evaluation to be limited to laminate material only, thus eliminating the variables of design and process. It is expected that the project will lead to more focused and quicker laminate testing and development for CAF resistance.

Previous results from the Pb-Free PWB materials reliability project have indicated that for the MRT test board used there is a clear relationship between design features and the increased risk of material delamination through SMT reflow. Using modified design variants of the MRT test board, this project explores further the impact of reduced through hole via pitch and hole wall to hole wall spacing, board thickness, number of layers and position of power distribution planes on the occurrence of post SMT assembly material damage.

This project is a continuation of the Digital Speckle Correlation (DSC) Project, which consisted of a preliminary look at the reliability for on and off-stack buried structures by measuring the strains the structure see going through a reflow process. The name of the new project has been changed to Digital Image Speckle Correlation 2 (DISC2) for two reasons. Obviously, it is a continuation of the previous project and the other reason is to not use the DSC acronym, which is more commonly used for Differential Scanning Calorimetry, a technique which has nothing to do with the previous or the new, current project. The recently completed DSC Project used coupons from the very successful completed Multi-lam Project. For the DISC2 Project the Team will expand the scope of investigated structures.

This project will create empirical data which could be used in modelling tools, such as DFR’s Sherlock, CALCE’s SARA or full blown FEM tools such as ANSYS. The resultant model could predict reliability and give an evaluation of design trade-offs. The Digital Image Speckle method is much quicker than Accelerated Thermal Cycling, which can take months.

In our previous project Electro-Chemical Migration we found that a No Clean Flux, which is designed to leave a benign residue, can result in crevice and pitting corrosion. We also discovered the flux activators can remain on the board due to excessive flux or entrapment (ie,: Selective solder fixtures, Wicking into soldermask and Non solder mask defined pads).We already knew that harsh environments subjects devices to high humidity.This all means that Ions can be mobilized and cause corrosion on exposed copper features.In this follow-on project we would like to develop a Test Method for determining Pitting / Crevice Corrosion capability of a Solder Flux. We then would submit the method to IPC Cleaning and Coating Committee for consideration of an additional test within J-STD 004 to evaluate flux potential to propagate Pitting / Crevice Corrosion capability of a Solder Flux on Cu and Sn and subsequently work with the IPC Committee on Cleanings and Coatings to implement our recommendations.

Materials used in Electronic Products are getting more and more scrutiny by government agencies around the globe (RoHS, REACH, CA Prop 65 etc). To date the U.S. Military has not shown a strong interest in halogen free laminate. However some military analysts feel there is a need to understand if halogen free laminates can withstand the more rigorous military testing criteria. This project will evaluate several laminates using military / aerospace reliability testing criteria.

In the previous project "PTH Lifetime Predictor for TC", the lifetime predictor derived is applicable only when the strain is greater than 3.0x10-4. Below this level, the strain is mainly creep strain which does not obey the Manson-Coffin rule. This project serves to provide a better understanding of creep strain on PTH and the influence of copper plating roughness, using FEM simulations and verifying through high temperature (HT) testing. Once the creep characteristics of a typical PWB copper plating are identified, the creep consideration can be added into the AF equation of the PTH lifetime predictor.

The aim of the SAC Aging 3 project is to use the Alloy Common Test Vehicle and to perform baseline microstructural characterization on ambient aged and elevated temperature isothermally aged samples.In addition, it will perform failure mode analysis and characterization of ATC samples to determine extent of microstructural evolution and impact on final failure. At the same time the project will thermal cycle additional non-monitored samples for microstructural analysis at different thermal aging times and temperatures.

Current rework guidelines regarding the number of allowable reworks for a component site are inadequate and need to be upgraded or better understood with solid research.This project proposes to establish a limit for the number of reworks that can occur for components or particular component types on an assembly without impacting the overall reliability. The project will develop new guidelines for reworks to be used in PWA and will write a proposal for new specifications on rework of PWA which will be delivered to standards bodies for their consideration.

The Low Ag/No Process Characterization study of low Ag alloy solder paste showed that the candidate materials tested can be used in the process without major assembly defects. This project will evaluate the reliability of a selection of these solderpastes in comparison to the standard SAC305 paste for integration into a development assembly line. This is a two phase project, Phase 1 will assemble and test a QFN component to down select alloys for the following BGA Phase 2 which plans to assemble and test a BGA component with a SAC305 solder ball and the various candidate solderpaste.

The project will explore the efficacy and longevity of nano-coated stencils. There has been an evolutionary change from chemically etched to laser “drilled” to e-form stencils with the added techniques of aperture polishing and now application of nano-coatings. This project may explore different types of nano-coatings, small component apertures and the lifetime of such coatings subjected to repeated use and various types of stencil cleaning.

Many transmission lines on a high speed server or network board have signal budgets of 10dB or less. A 1 or 2 dB loss on a solder joint could result in signal integrity failures. This is comparable to the loss typical in a well designed FCBGA package. DC and event detectors find opens. One of the benefits we obtained from the TSV projects is our understanding of the RF measurement technique that was pioneered at NIST. We will attempt to use this technique where instead of using TSVs, we will use existing PCB designs and familiar components to generate a solder joint reliability study. We will compare DC measurements to RF measurements.

This project serves to evaluate the toughness of solder joints on boards, coated with various surface finishes, and assembled with large components and fine-pitch components using different solder alloys used in harsh-use environment. The assembled boards will go through thermal cycling and vibration tests (latter for thick boards only), and the results analysed to find the effects the various surface finishes, in both thin and thick coating, have on solder joints.

Warpage is an assembly manufacturing problem resulting in opens, weak joints, Head on Pillow (HOP) and None Wet Open (NWO) defects. With the IC's becoming increasingly thinner, the silicon has less ability to resist deformation of the component package. This deformation combined with short IC leads and a very flexible substrate often exceeds the termination-to-solder paste gap. The net result is that warpage will become an increasing problem in the future. Warpage as a result of the thickness of the IC's used,along with defects such as open joints or very weak joints can be caused by short leads on the IC's combined with very flexible carriers. This combination will most likely cause interconnections that will be poorly made or never made In phase 2 of this project, we will characterize the newly defined process from FCBGA Package Warpage 1 and develop a consistent methodology to use in normal production.

BGA pitch is moving steadily downward and high I/O BGAs are common at 1.0mm and 0.8mm pitch and starting to appear at 0.65mm pitch. Consumer PCB’s (smart phone, tablet, etc.) have already moved to large I/O BGA’s at 0.5mm and even 0.4mm pitch. This technology density is often supported by “Any Layer/Every Layer HDI PCB’s”. Generally the PCB’s used in Any Layer designs are very thin (typically 0.8mm thick or less). High density packages require 3 + stacks of microvias for routing (depending on how many I/O and design specifics) just to escape route these packages. It is inevitable that high I/O BGAs for high complexity products (Telecom, Server, etc.) will also trend downward in pitch, following the consumer trend.

The High Density Packaging User Group is starting a project to evaluate Vertical Conductive Structures – VeCS.VeCS is a relatively new patented technology by NextGIn Technology for creating a higher density of connections to the internal layers and with less distortion of the signal. The technology allows for less cutting of the ground/power planes for a better current carrying capacity and better reference plane for the striplines. The project will evaluate the reliability and signal integrity aspects of this technology as it pertains to our members technology interest.

Both VeCS 1 - For through board applications and VeCS 2- For blind structures will be evaluated.

Phase 5 of the Lead-Free PWB materials reliability program will evaluate selected latest generation PWB laminates. The testing program will include thermal analysis and stress testing, thermal cycling endurance, susceptibility to CAF and evaluation of electrical characteristics at high frequencies using a new connectorless SPP (short pulse propagation) design. Properties will be evaluated both before and after multiple simulated reflow conditions.

Network capabilities must now accommodate increasing demands for data transmission from business and consumer customer bases over fixed access and wireless networks at any time of day or night. These high traffic operational modes, coupled with energy saving modes at the component level, have the potential to induce new reliability challenges by adding new types of thermomechanical stress and strain to equipment. Rapid and frequent mini-power cycling is now being coupled with the well-known stress from diurnal cycling and typical thermal operating conditions. Network operations have long avoided traditional power cycling because power cycles are known to degrade solder joint performance and reduce the life and performance of hardware. The advent of Sn-based, Pb-free alloys for solder assembly is expected to increase susceptibility to power cycling-induced damage.