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Solution

To drive consistency between Xilinx IPs, signal names in the Verilog cores have been changed to use all lowercase. Therefore, the higher level module where the core is instantiated should now have the following signals listed below in lowercase. Please upgrade the core first before changing the core instantiation in the design.

PIPE_*ICAP_*

There are also new signals need to be added into the core instantiation:

drp_*init_pattern_buscfg_local_err

The * substitutes all character(s) following the specified prefix signal names.