Abstract

Voltage fluctuations caused by parasitic impedances in the power supply rails of modern ICs are a major concern in nowadays ICs. The voltage fluctuations are spread out to the diverse nodes of the internal sections causing two effects: a degradation of performances mainly impacting gate delays and
a noisy contamination of the quiescent levels of the logic that drives the node. Both effects are presented together, in this
paper, showing than both are a cause of errors in modern and future digital circuits. The paper groups both error mechanisms
and shows how the global error rate is related with the voltage deviation and the period of the clock of the digital system.

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