“As the DisplayPort standard matures, the verification of DisplayPort systems is becoming critical to delivering first time silicon success and rapid time to market,” said Carl Ruggiero, chief executive officer at Trilinear Technologies, Inc. “Trilinear develops world class DisplayPort products, and are pleased to now partner with Avery Design Systems who share our commitment to product quality. Both Trilinear and Avery have a history of delivering value and success to their customers.”

The new partnership enables Trilinear Technologies and Avery Design Systems to offer an integrated design and verification solution for DisplayPort Transmitter and Receiver customers. Support for the VESA standard includes DisplayPort 1.4, embedded DisplayPort 1.4b as well as Display Stream Compression 1.2. A fully integrated solution from Trilinear and Avery Designs is available now for both Transmitter and Receiver designs.

“We have been pleased to collaborate with Trilinear to support a complete pre-validated design and verification IP solution promoting higher quality and streamlining SoC development for our customers,” said Chris Browy, VP sales and marketing at Avery Design Systems. “Our SystemVerilog/UVM-based DP and eDP source and sink models support automated single and multi-stream video generation/reception, comprehensive protocol checking, and compliance testsuites suitable for IP controller-PHY through SoC-level verification and which can be extended for customer-specific sequence scenarios.”

About Trilinear Technologoes
Trilinear Technologies, Inc. is a privately funded firm founded in 2006 and headquartered in Lake Oswego, Oregon. The company develops high performance video hardware IP cores for ASIC and FPGA systems, and targets the broadcast, consumer display, medical, mobile devices, military, and security markets. Learn more at http://www.trilineartech.com.

About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, DP/eDP, HDMI, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.