Embedded Systems, USB, and Device Drivers

Vreelin High-Speed USB 2.0 Host Core for Xilinx FPGA’s

Vreelin’s USB 2.0 High-Speed Embedded Host core for Xilinx FPGA’s integrates into the Xilinx Vivado development environment. This allows developers to quickly add a USB 2.0 host interface into a Microblaze or Zynq project. The core has a small footprint of 700 slices’s on current generation Xilinx FPGA’s and uses a ULPI compliant external PHY that requires only 12 pins. The core attaches to the LMB bus as a slave device and appears as RAM. Push button system configuration with Vivado allows the designer to add, delete or modify the core. Multiple cores can be added to a design as needed. Fully plug and play compliant, the Vreelin USB 2.0 Host core includes working demonstrations firmware that supports up to 7 USB High-Speed or Full-Speed devices connected through a USB 2 HUB. Or, a single USB 2 device can be directly connected to the core’s root port.

Small and fast, the core supports up to 32 endpoints grouped into 4 endpoints per device. The core’s sequencer is designed to be efficient for FPGA use in smaller designs. Double buffering is available on each end point. The maximum packet size for Bulk and Interrupt endpoints is 512 bytes. ISO endpoints can be 1024 bytes. Up to 16 KB of BRAM Memory can be allocated as needed. As supplied the core uses 4 BRAM or 8KB. The type of each endpoint (bulk, interrupt, or ISO), the max packet size for each endpoint, and the endpoint’s buffer location in dual port RAM is configured by the firmware. HDL source code for the dual port RAM module is provided to allow the designer to minimize the foot print as required. To meet special circumstances, the core can be custom built by Vreelin with more or less than 32 endpoints / 8 devices and with other special features as required such as custom hardware interfaces for specific endpoints. The core sustains USB 2.0 high speed transfer rates up to the limits of the USB bus and is certified USB 2.0 Logo Compliant.

Supports Microblaze and Arm processors

Efficient Small Size: 700 slices’s on current generation Xilinx FPGA’s

Attaches to LMB for speed and efficiency. Looks like static RAM

Slave or Master AXI bus are available on request

Uses BRAM for Data Buffering

Supports external ULPI compliant PHY (12 pin I/F)

Works seamlessly with Microchip PHY’s (as well as other ULPI compliant PHY’s)