Parallel CRC Generator

Every modern communication protocol uses one or more error detection algorithms. Cyclic Redundancy Check, or CRC, is by far the most popular one. CRC properties are defined by the generator polynomial length and coefficients. The protocol specification usually defines CRC in hex or polynomial notation. For example, CRC5 used in USB 2.0 protocol is represented as 0×5 in hex notation or as G(x)=x5+x2+1 in the polynomial. This CRC is implemented in hardware as a shift register as shown in the following picture.

The problem is that in many cases shift register implementation is suboptimal. It only allows the calculation of one bit every clock. If a design has 32-bit wide datapath, meaning that every clock CRC module has to calculate CRC on 32-bit of data, this scheme will not work. Somehow this serial shift register implementation has to be converted into a parallel N-bit wide circuit, where N is the design datapath width, so that every clock N bits are processed.

I started researching the available literature on parallel CRC calculation methods and found only a handful of papers ([2], [3]) that deal with this issue. Most sources are academic and focus on the theoretical aspect of the problem. They are too impractical to implement in software or hardware for a quick code generation.

I came up with the following scheme that I’ve used to build an online Parallel CRC Generator tool. Here is a description of the steps in which I make use USB CRC5 mentioned above.

(3) Parallel CRC implementation is a function of N-bit data input as well as M-bit current state CRC, as shown in the above figure. We’re going to build two matrices: Mout (next state CRC) as a function of Min(current state CRC) when N=0 and Mout as a function of Nin when M=0.

(4) Using the routine from (2) calculate CRC for the N values when Min=0. Each value is one-hot encoded, that is there is only one bit set. For N=4 the values are 0×1, 0×2, 0×4, 0×8. Mout = F(Nin,Min=0)

(5) Build NxM matrix, Each row contains the results from (3) in increasing order. For example, 1’st row contains the result of input=0×1, 2′nd row is input=0×2, etc. The output is M-bit wide, which the desired CRC width. Here is the matrix for USB CRC5 with N=4.

(6) Each column in this matrix, and that’s the interesting part, represents an output bit Mout[i] as a function of Nin.

(7) Using the routine from (3) calculate CRC for the M values when Nin=0. Each value is one-hot encoded, that is there is only one bit set. For M=5 the values are 0×1, 0×2, 0×4, 0×8, 0×10. Mout = F(Nin=0,Min)

(8) Build MxM matrix, Each row contains the results from (7) in increasing order. Here is the matrix for USB CRC5 with N=4

(9) Now, build an equation for each Mout[i] bit: all Nin[j] and Min[k] bits in column [i] participate in the equation. The participating inputs are XORed together.

Mout[0] = Min[1]^Min[4]^Nin[0]^Nin[3]

Mout[1] = Min[2]^Nin[1]

Mout[2] = Min[1]^Min[3]^Min[4]^Nin[0]^Nin[2]^Nin[3]

Mout[3] = Min[2]^Min[4]^Nin[1]^Nin[3]

Mout[4] = Min[0]^Min[3]^Nin[2]

That is our parallel CRC.

I presume since the invention of the CRC algorithm more than 40 years ago, somebody has already came up with this approach. I just coulnd’t find it and “reinvented the wheel”.

Keep me posted if the CRC Generation tool works for you, or you need more clarifications on the algorithm.

[September 29th, 2010] Users frequently ask why their implementation of serial CRC doesn’t match the generated parallel CRC with the same polynomial. There are few reasons for that:
– bit order into serial CRC isn’t the same as how the data is fed into the parallel CRC
– input data bits are inverted
– LFSR is not initialized the same way. A lot of protocols initialize it with F-s, and that’s what is done in the parallel CRC.

Dear Evgeni,
I generated crc module for ethernet with 32 bit polynomial and 32 bit data input.
Used a standard udp frame and made a small testbench to test crc verilog module.
Calculated crc online http://www.lammertbies.nl/comm/info/crc-calculation.html
The 2 outputs donot match. Tried byte-reflect from its least-significant-bit-first order to the normal most-significant-bit first order. Does not seem to match.
Do I need to do something else ?

Hi,
I have a question. I am using the crc32 generator code from this site for poly : 04C11DB7 for data width 32 and 16. Theoretically, the result of 32-bits data should be cascaded result of 2 16-bit data like following code,
assign crc32_d32 = gen_crc32_d32(data[31:0], crc_in);
assign crc32_d16_l = gen_crc32_d16(data[15:0], crc_in);
assign crc32_d16_h = gen_crc32_d16(data[31:16],crc32_d16_l);
I think crc32_d32 should be equal to crc32_d16_h, but the simulation result is not for data that is not 32′h0.
Can anyone tell me why these 2 results are different?

I had tried to implement 1-bit and loop 32 times, but got different result with 32-bits/round and 16-bits 2 rounds. Suppose I should get 16-bits/round result after 16-th loop and 32-bits/round result at 32-th loop. I completely confused….

I am designing an Ethernet application where I am required to form the packet payload at a rate of 128-bits each clock. However, each clock, from 1 to 4 of the 32-bit words forming the 128 bits will be valid.

Can I use 4 32-bit CRC generators concurrently (1 for each of the 4 32-bit streams) and then combine the 4 CRC results at the end of the payload to form the complete CRC32 for the packet? Can the 4 partial results be easily combined?

Each of the four streams will look like this: “….D000D000D000…”, where each nibble in that string is 32-bit. “D” is a data dword, followed by 3 dwords of zeros. So after each 32-bit CRC calculation on data, you’d need to multiply the result by X^96.

Thank you for your reply. However, I didn’t really understand your answer. I will clarify my question.
I have 32-bit words, arriving in a 128-bit bus, that I must generate a 32-bit CRC for. Each clock, the 128-bit bus will either have the 1st, the 1st two, the 1st three, or all four 32-bit words valid. I must add these 1 to 4 words to my 32-bit CRC in one clock. This repeats each clock until the end of data. How do I generate my 32-bit CRC given I have a varying (1 to 4) number of words to add each clock? Can I use a 128in-32out CRC generator and set the invalid words to zeros? Will this give the proper result (the zeroed words not affecting the CRC result)? OR can I use 4 32in-32out CRC generators, 1 on each lane of the 128-bit bus, and get 4 CRC sub-results and then combine them? Will this work; how to combine? OR is there another approach? Thank you so much for your advice! Great website BTW.

I understand your question. This is, in fact, one of the most frequently asked things. The simplest approach is to have 4 CRC generators for 32-, 64-, 96-, and 128-bit data. Then select the output based on the number of valid words. There are more complex solutions involving finite field arithmetics that help save some area. But I haven’t yet seen those in public domain. If I have some time, I’ll enhance this CRC generator. But it’s not a priority.

Thank you for your suggestion. It sounds like I would use the combinational CRC result from all 4 generators and feed them through a 4-to-1 Mux to a single 32-bit registered CRC output. In this manner, the CRC registered output is properly updated, with 1 to 4 added words, each clock. Did I understand you correctly? OR are you suggesting I can use the 4 CRC generator registered outputs?

Hi Evgeni,
Let say for example that we have a datapath of 256 bits. Is it possible to compute the first 128 bytes CRC and the second 128 bytes CRC at the same time, and then combine them (so without injecting the first result in the second computation)?
Thanks!

This question about “interleaved” CRC calculation comes up quite often. The short answer is – not quite. One problem is that you need to account for 128-bit of leading and trailing zeros when calculating CRC on split data:
data[255:0] = {data[255:128],128′b0} ^ {128′b0,data[127:0]}.
You can calculate CRC for each 128-bit chunk, but then you need to adjust the result by x^128 multiplication over finite field before proceeding to the next 256-bit data chunk.

I try to generate the Verilog code for 16 bit width data and 16 CRC with 1+x2+x15+x16, step one works fine, but it stuck at step 2. it couldn’t generate the code for me. what is wrong with the web? I am using ie11.

I want to do CRC32 for my 128 bit data. The input data 128 bit is coming at each clock and i want to perform crc32 for that. I generated the verilog code with 802.3 polynominal[ data width=128bit, polynominal width-32 bit] and tried to verify the functionality. I have inverted the final CRC value from the Test bench and checked for the magical number in the simulation.But i didn’t get that. the same experiments worked for 32 bit data 32 bit polynominal CRC. Can you please let me know my 128 bit data with 32 bit CRC can be implemented or not??

Most of the problems with parallel CRCs are related to data ordering. I presume that serial CRC (when you feed one bit of data at a time) and 32-bit CRC (when you feed one DWORD of data at a time) are working.
If there is a mismatch in 128-bit CRC, one possibility is that 4 DWORDs of data are not ordered correctly (for example dw 0,1,2,3 vs. dw 3,2,1,0).
Another possibility is data misalignment. If your data doesn’t end at 128-bit boundary, you cannot include trailing zeros in 128-bit CRC calculation. There are several methods how to handle CRC checking of misaligned data.