Many analog frequency divider circuits were invented during the age of the vacuum tube. Some of these circuits even survived the germanium transistor age, but most were forgotten following the availability of inexpensive monolithic digital ICs such as flip-flops or more complicated counters. However, analog frequency dividers may still provide useful performance at very high frequencies where their digital counterparts may be extremely power hungry or not available at all.

Theory of Operation

The principle of operation of a simple divide-by-two analog divider is shown in Figure 1. The divider includes a balanced mixer and feedback amplifier. The input signal is fed to one mixer port while a power splitter provides part of the feedback as the output signal.

A quick analysis of circuit operation shows that positive feedback exists at half the input frequency. In other words, the mixer behaves as a phase conjugator for signals at half the input frequency. If the feedback has sufficient gain, oscillation of the circuit at half the input frequency can start from arbitrarily small signals such as thermal noise. Therefore, the circuit does not require any particular condition to start its operation.

Due to the phase conjugation of the feedback signal, frequency division by two occurs regardless of the phase shift introduced by the mixer or feedback amplifier. However, the phase of the output signal is precisely related to the phase of the input signal. Due to the phase conjugation, only two possible phase relationships (offset by 180°) exist between the input and output signals. Hence, the operation of the circuit is similar to a digital flip-flop where the transitions of the output are synchronous with the input transitions but the output signal phase is ambiguous (0° or 180°). The remaining unknown is the initial state of the flip-flop or the initial phase of the thermal noise that started the analog frequency divider.

On the other hand, a few differences exist between a digital flip-flop and analog divider. An emitter-coupled logic flip-flop usually will oscillate without an input signal. An analog divider will simply stop its operation since the feedback path is interrupted without an input signal to the mixer. Of course, the analog frequency divider requires a well-balanced mixer. If the mixer is not well balanced, crosstalk may occur between input and output ports, which may lead to parasitic oscillation of the feedback loop. Even if there is no oscillation, unwanted crosstalk between mixer ports severely degrades the operation of the divider.

A Divide-by-four Prototype

The problem that initiated the effort described in this article was the observation of STM-64 (10 Gbps) lightwave pulses on a sampling oscilloscope. The lightwave receiver only provided a clock output at 9.953 GHz while the sampling oscilloscope trigger input was specified only up to 2.5 GHz. A microwave frequency divide-by-four circuit was required to trigger the oscilloscope. Since the delivery times of advertised 10 GHz flip-flops were not acceptable, an analog divider had to be designed and built as quickly as possible.

Fortunately, the STM-64 clock frequency does not change significantly, meaning, in this case, a narrowband divider is completely sufficient. A practical narrowband analog divider circuit is shown in Figure 2 . A single high electron mobility transistor (HEMT) is used as a passive balanced mixer with no applied DC bias voltages. In this way, the AC signal applied to the gate cannot propagate to the drain, but can only modulate the channel resistance of the HEMT.

The input signal is first amplified to a known level and then applied to the drain of the HEMT through a diplexer network. The output signal is also taken from the drain of the HEMT, amplified by the feedback amplifier and fed back to the gate of the HEMT mixer. An output coupler provides the output signal.

The entire divide-by-two mixer circuit requires only three HEMTs (an input amplifier, mixer and feedback amplifier), a few surface-mount device (SMD) resistors and capacitors, and a few microstrip lines on a printed circuit board. A prototype circuit was first built for an input frequency of 10 GHz and an output frequency of 5 GHz. The prototype operated correctly over a bandwidth of approximately 10 percent of the center frequency.

Since a divide-by-four circuit was required to obtain the 2488 MHz trigger fromthe available 9953 MHz clock, a double-stage 10/2.5 GHz divider was developed. A detailed circuit diagram of this divider is shown in Figure 3 . It includes two similar divide-by-two stages and three amplifiers for 10, 5 and 2.5 GHz. Model ATF-35176 HEMTs with very simple bias networks are used in all stages.

The active components are installed on a microstrip board (shown in Figure 4 ) made of conventional FR4 0.8 mm (1/32")-thick glassfiber-epoxy laminate. The FR4 material is more than adequate since there are no high Q resonators. Using a lossy laminate like FR4 even has some advantages: HEMTs will hardly oscillate in the mm-wave range when installed on a lossy laminate, and the loss reduces their excessive gain.

The source leads of the HEMTs are grounded through holes in the laminate with a diameter of 3.2 mm (1/8"). Since plated through holes are not practical for a prototype, the holes are covered with thin copper foil on the groundplane side and then filled with solder. Finally, the active device is soldered from the microstrip side. Of course this simple technique is not useful for high volume production, however, for prototype work it allows very low ground inductances and easy component removal without destroying the component or printed circuit board.

The +5 V supply voltage is brought through 1 nF feedthrough capacitors installed in 3.2 mm (diameter) holes in the printed circuit board. Due to the simple bias arrangement, the current drain depends heavily on the Idss of the devices used. The overall current drain for the five HEMT amplifiers is approximately 300 mA.

Prototype Results

Three prototypes of the analog divider described previously were built and tested. Typical results for the input sensitivity are shown in Figure 5 . At each frequency, the divider operates correctly within a particular range of input power levels. Outside the indicated areas, the divider may operate erratically or may not provide any output at all.

From the diagram it may be concluded that the best input frequency is approximately 10.1 GHz. Similar results were also obtained using other prototypes, therefore, the overall design could be further optimized for 9.953 GHz. However, since the measured performance was determined to be sufficient, no further optimization was performed for the exact STM-64 clock frequency.

The device's operating area can be explained in part by the crosstalk of the HEMT mixer. The operation of the divider is enhanced at some frequencies and corrupted at others depending on the phase of the crosstalk. In order to redesign the divider for a different frequency range, the diplexer network must be modified and the optimum phase of the unwanted (but unavoidable) crosstalk between mixer ports must be determined.

Conclusion

A narrowband two-stage analog divide-by-four frequency divider that converts a 10 GHz input to 2.5 GHz has been developed. The circuit was constructed using HEMT devices on an FR4 printed circuit board. The resulting circuit was used to provide the trigger input to a 10 GHz sampling oscilloscope and supplanted the need for obtaining a commercial 10 GHz flip-flop divider.