In September 1975 I began as an employee of the Santa Barbara Operation (SBO) of Delco Electronics and later (1992) with the parent company in Kokomo,IN. In my early years at SBO my job was logic design. The job lasted until ICs with greater functionality eliminated the need for the hoards of logic designers then working. I reinvented myself as a Systems Engineer specializing in embedded computers and microcomputer applications. About half of my career was spent in aerospace, the other half in automotive. - John Waidner, Carmel, IN, June 2017

"M362F-2" was the product designation for the CPU used in the F-16A/B Fire Control Computer (FCC). I was one of the FCC designers in 1975/76. I was also one of the EFCC designers in 1978/79. The EFCC ("Enhanced" FCC) computer went into the F-16C/D aircraft and used the M372F processor. (It was the same processor that went into the C-5A/B MADAR system computer upgrade in the 80s.) Although the FCC and EFCC were very similar there were significant differences that I'll discuss in another post.

A note: Three production FCCs went into the F-117 to do number crunching. Some years after F-117 production ceased they were replaced by an IBM Federal Systems Division LRU, a much more capable math machine. Those three FCCs were no different than what went into the F-16A/B aircraft except: 1) the chassis was painted a darker shade of gray, 2) they had a different top assembly number, and 3) there was a 1/2" diameter dot colored "Rose Monet" painted on their face. (I kid you not; the color was selected by a woman, a weekend artist, who worked in the program management office.) I first saw the "vehicle" (it was never referred to as an aircraft) as a 2/3 scale plywood mockup at Lockheed's Skunk Works in Burbank. If you think the real thing looks odd you should have seen it in unpainted plywood. But I digress.

To correct an earlier post in this forum, the M362 CPU was not the computer used in the three subsystems General Motors' AC Electronics division supplied to the Apollo program: the command module guidance system IMU, the lunar lander flight control computer, or the lunar rover electric drive controller. I can elaborate if anyone is interested but it's probably not a topic for this forum.

Some FCC/M362F-2 details:

NomenclatureLRU is Line Replaceable Unit, i.e., the FCC itself which could be removed from an aircraft on the flight line, i.e., not in a hanger or special test facility, and replaced with a like item. SRU is Shop Replaceable Unit, one of the subassemblies of the FCC. As the term implies, an SRU is intended to be removed and replaced within the avionics maintenance shop.

Maintenance philosophyFCC maintenance was intended to be performed within the avionics shop. The shop's test equipment exercised a suspected faulty FCC to locate and isolate a fault to an SRU. The suspect SRU was removed, replaced, and sent to a central depot for repair. It was not repaired in the avionics shop due to the difficulty of training and maintaining the necessary skills, not to mention stocking a complement of replacement parts.

ManufacturerThe Santa Barbara Operation (SBO) of Delco Electronics (a division of General Motors) located on Hollister Ave in Goleta, CA. FSCN: 13160. Design and development in Goleta, CA, production manufacturing in Milwaukee, WI, at the GM plant in Oak Creek, WI. SBO supplied both the computer and its mounting rack in the F-16's avionics bay.

Mechanical and powerGeneral description: The FCC consisted of a set of nine circuit cards, a power supply, a backplane, two internal wire harnesses, and an aluminum chassis. The FCC was mounted in a rack that itself was mounted in the aircraft's avionics bay. The rack provided the electrical interfacing to the aircraft and a source of cooling air to the computer. The FCC was painted a shade of gray. When it's memory was empty the FCC was "unclassified." Once an operational flight program (OFP) was loaded into memory (in the avionics shop) the classification changed to reflect the OFP's classification, usually "secret," and a label affixed indicating both the revision level of the OFP and it's classification. A carrying handle was mounted on the front casting making the FCC "man portable" in USAF parlance. I don't recall the weight but it wasn't particularly heavy.Operating environment: Classed as "uninhabited fighter", meaning that FCC was exposed to the ambient temperature and pressure. The designation also implies that electrical power is not as well regulated as would be the case in a cargo aircraft (for example), although in practice the F-16's operating power was quite well regulated. Operating temperature range was spec'd as -55C to 125C. The FCC received a waiver to change -55C to -45C. Bipolar junction transistors (BJTs), which the transistor-transistor logic (TTL) ICs used in the FCC consist of, don't work well at -55C. The FCC required the waiver to meet the low temperature start up requirement. Ambient pressure was spec'd for altitudes ranging from -1200 feet (Dead Sea mean surface altitude) to 50,000 foot aircraft service ceiling. Another waiver was required to meet the radiated emissions EMI/EMC requirement. Neither waiver was needed for the EFCC.Circuit Cared Assembles: 1/2 ATR size circuit card modules (approx. 6" x 4.5"). Almost all digital parts (the majority) were 14 or 16 pin metal/ceramic flatpak. Larger parts were also in flatpak. Digital parts were mounted on both sides of a circuit card assembly (CCA). A max of 120 14 and 16 pin flatpak could be mounted on one CCA although in practice the part count didn't exceed ~100 parts. Each CCA consisted of two thin printed wiring boards with parts mounted on one side. These were called 'flimsys'. The two flimsys were glued together back to back to form the CCA module. Connections between one side and the other was provided by jumpers over the top of the module. if the card was predicted to run hotter than desired then a piece of copper or aluminum was included between the glued together flimsys to more efficiently transfer heat to the side walls of the chassis. The flimsys used 0.013" diameter plated through holes that were chemically etched rather than drilled as is done today. It was a proprietary process that we had to "sell" to each new customer. It didn't hurt that the process was the same one used to make the circuit cards for the Titan II INS and the three systems supplied to the Apollo program. CCA modules were housed in a 1/2 ATR chassis and interconnected to each other and the aircraft with a printed wiring CCA backplane.Chassis and CCA mounting: The CCAs were thermally connected by Bircher clips to hollow plenums that formed the sides of the chassis. Conditioned air supplied by the aircraft was exhausted through these plenums to cool the electronics, a method that greatly extended the life of the computer. The top and bottom of the chassis were closed by machined plates attached with multiple 6-32 captive fasteners. Three aircraft interface connectors (one for power, two for signal) were mounted on the rear casting and a 128 pin test connector on the front. Builders plate with name, manufacturer, FSCN, top assembly number, etc., was mounted on the front.Electronics assemblies: The electronic module complement: switching power supply, two CPU CCAs, two 16k core memory modules, two memory control CCAs (CDE, MLC), one analog (ADC), one miscellaneous digital (DIO), and three cards for the -1553 serial bus (one controller, two TX/RX cards).Power requirements: 115VAC single phase, 400 Hz, 150w, supplied by the aircraft's engine-driven three phase alternator.

Computer logical architectureInternal clock: 4.0 MHz, 250ns period, 50% duty cycleLogical layout: The FCC's electronic functions interfaced to a single 16 bit wide data bus that extended from memory, past the CPU, to the I/O. Bus arbitration was accomplished by the CPU which had priority over bus access. The data bus operated at the basic clock speed of 4.0 MHz. There were 16 prioritized interrupts to the processor although not all of them were used in the FCC. The internal bus had no parity or error detection/correction implemented although parity had been proposed with SBO's original bid. The highest level interrupt was sourced from the power module,designated "Power Off," to indicate that computer shutdown was immanent.Logic Technology: 54LSxx TTL, mostly from Texas Instruments, with a few 54xx and 54xx where speed was needed in a propagation path to make spec. Both SSI and MSI parts were used. SSI parts were mostly 54LS00 (quad NAND) and 54LS04 (hex inverter), 54LS74 (dual D flip-flop) and 54LS109 (dual JK flip-flop), although odd parts like the 54LS86 (quad exclusive OR) were also used. MSI parts included the bit slice ALU, multiplexers, decoders, counters, and a parity check function. Parts were speed derated 20% and allowed max junction temperature was derated from 125Cto 105C per General Dynamics prime item spec for the FCC.

MemoryWord size: 16 bits + 1 parity bitType: 32k magnetic core in two 16k modules. Core shape: torus. Material: an exotic ferrite harvested from the stacks of steel mill furnaces (really!). Individual core size: 0.013" with 0.007" hole. Two drive/sense wires, a column wire and a row wire, were routed through each core. These wires were on the order of 44-46 AWG magnet wire. Total number of cores per 16k module: 278,528, not counting spare rows and columns.Speed: 250ns read time. Since it was magnetic core, meaning the read operation was 'destructive' in that the read currents would flip the "1" bits to "0" as part of the sense process. Because of the flip the word had to be rewritten to restore the 1s which required another 250 ns, thus one complete memory cycle (e.g., read followed by restore) was 500 ns. To speed things up the two memory modules were designated ODD and EVEN. Since most memory accesses are from sequential addresses this arrangement made the effective memory cycle 250 ns. On the relatively rare occasions that two even or two odd access were required the processor had to wait for the restore cycle to complete before the second address could be access. The odd/even module assignments meant that the CPU rarely had to wait for the memory to 'catch up' with it.

CPUProcessor architecture: The CPU was a microprogrammed synchronous state machine with 16 registers, a bit slice ALU with look-ahead carry. It was a very regular architecture similar to Data General NOVA minicomputer. FCC/M362F-2 address range was 64k (16 bits).Physical: The CPU was contained on two CCAs and consisted of ~200 SSI and MSI 54LSxx family TTL parts.Instruction set: Proprietary with floating point and integer arithmetic. Some 'macro' instructions were implemented to speed processing the solution for missile intercept, gun firing aiming lead, dropping gravity bombs. These included ARCTAN (two quadrants), POLYnominal coefficients from curve fitting of radar data. Floating MULTiply two words to yield 32 bit result, 32 bit floating DIVide. I think there were two or three more but I forget what they were. The "F-2" designation meant that 1) it was a floating point processor, and 2) it was the second floating point implementation in the M362 product line. I don't have any recollection of the advertised instruction execution speed as these were the days before standardized throughput measuring benchmark programs. However, simple instructions would execute in 4 to 8 clock cycles. The macro instructions required on the order of a hundred clock cycles. There was no pipeline or cache to queue instructions or data nor a branch prediction algorithm.

Input/OutputOperation and control: The FCC Input/Output (I/O) suite consisted of digital and analog functions. Control of the I/O was via explicit Input (INP) and Output (OUT) instructions that transferred data to and from the I/O functions. The I/O instructions consisted of two data words: the frist being the I/O address code, the second being the data moved to or from the I/O function. Data to the I/O was typically control data to set or reset an output discrete, read the input discrete register, initialize and start the -1553 data bus controller, and reset the COP timer (see below).Analog: 4 input, 12 bit, +/- 10VDC successive approximation A/D converter. Allowing for input multiplexer settling, the conversion time was about 20 microseconds. Only two of the four input channels were used. Each one received a synchro signal from the aircraft's two fuel flow meters. Determining successive synchro shaft positions (and so it's rotation rate) was what the ARCTAN instruction was used for. ADC circuit card was designed to operate semi-autonomously beginning operation when commanded by the program. Data was returned to memory via direct memory access (DMA) followed by the ADC setting an interrupt to the CPU. The ADC operated until 1) power went away, or 2) the flight-program commanded it to stop.Digital: High level discretes (i.e., 28VDC signals from contact closures), low level discretes (5VDC, electronically sourced), one dual redundant Mil-Std-1553B bus. The high level input discretes had a 2ms filter on each input to suppress contact bounce. There were also both high level and low level output discretes.COP timer: Of note was the use of a computer operating properly (COP) timer, the first ever (I think) to be used in a USAF avionics LRU. The COP timer was located on the DIO CCA and operated from an independent clock. It had a preset period of about 50ms. The flight program was required to reset this timer before the period expired else an interrupt would be set, the program would effectively halt, and a light would illuminate within the pilot's view. The flight program's control loop was about 40ms long so there was ample time to execute the loop before resetting the COP timer. The purpose of this scheme was to stop the FCC and let the pilot know it was offline in the event that: 1) execution had left the flight program memory and "went off into the weeds" executing data or who knew what, 2) the FCC had suffered a massive failure (power supply, etc.), or 3) the FCC had suffered a failure that was detected by built in test (BIT). The use of a COP promulgated into other aircraft and into the entire automotive industry, but that's another story.

Power supply.Power for the FCC was supplied by an SRU that sourced 5VDC for logic circuits, +/- 15VDC for analog functions, and two different voltages for core memory operation. The 115VAC single phase 400Hz power was brought into the power supply module via a transformer. It was rectified and regulated by a switching regulator. Regulation was on the 5VDC logic power. The other voltages followed the %V output. The weight of the power supply module was ~20% of the FCC weight. The power module was rated for 150 watts.

As an aspiring EE (only have to finish my Master's thesis) this was truly a fascinating read.Even starting out, the fact that you used chemically etched through holes was a bit surprising (none of that laser rubbish, huh!).What did you use -1553 bus for? I guess weapons. Anything else?Oh boy, 54 series chips. Oldschool! Love it! I guess proper LSI and VLSI were a good while away still. And using flatpack? So your ICs were already SMD?And magnetic core memory. Brings a tear to my eye...200 parts CPU... ever did a transistor count?A SAR ADC... pretty dope. Was it something like this: http://www.analog.com/media/en/technica ... /AD572.pdf ?And perhaps most surprising of all.. a SMPS? Didn't know transistors existed back then that could switch high voltages.Sorry if this was a bit rambly. Just going with the flow as I read.

The chemically etched vias were the only way to make such a small hole when the technology was developed in the 50s. Nobody was making high speed drilling equipment to make holes that small. It worked so well, and since the tooling was paid for, we didn't give it up until the late 80s. The company had been using flatpaks since they had first become available with diode arrays in them.

We just supplied the -1553 bus interface. It consisted of a pair of controllers and a pair of TX/RX circuits in the interests of redundancy. As for it's use, you'll have to ask/look elsewhere. If I recall, the FCC was the bus controller. I think the backup controller was the navigation computer.

CPU and 200 parts. They were all 54LSxx parts so you'd have to go look at datasheets for the family to get a transistor count. But... a 54/74LS00 NAND gate was four transistors: one multiple emitter input device and a driver for the output totem pole transistor pair. They stopped publishing explicit circuits when MSI parts came out. The functions were only shown as the logical equivalent circuit. I will say that feature size was large enough that someone with good eyesight (me, at an earlier age) could see the individual transistors on the SSI chips.

The SAR we used required an external comparitor and precision voltage reference. The latter was home grown as I remember, not a purchased part. The SAR was in a ceramic and metal DIP rather than a flatpak. I wish I could tell you what part it was but it has been a very long time since I last saw a schematic of that CCA. However, if memory serves me right on this, it was made by Analog Devices.

The EFCC used the same core (13 mil with 7 mil hole) but packed them into a pair of 32k modules for a total of 64k memory. It was the last core module we made. With non-dynamic CMOS semiconductor memory becoming available and the USAF relenting on it's no-lithium battery policy, battery backed up memory was becoming doable both policy-wise and technically. Core memory was heavy, a power hog, generated a LOT of heat, and tricky to make work. You wouldn't believe the noise in our core modules and the minuscule signal produced by a core switching from 1 to 0. I will be forever in awe of the core designers. The fact that our 32k module worked, and worked well over temperature and vibration, earned the designers notice by one of the trade organizations (IEEE?). I'll talk more about those modules in the (coming soon) EFCC post. I'll also post about the 128k semiconductor memory retrofit we did for the FCC following the EFCC project.

Power supply switching devices: Remember that the AC input was to a transformer which produced a low voltage (12V?) for the switching circuit. The switching circuit drove a autotransformer that was tapped for the secondary DC voltages. Regulation was around the 5V. The other voltages relied on a constant load to remain within tolerance. The memory used currents produced by switched (off-on-off) constant sources so exact voltage values weren't so important. I think the supply used a switching device that was produced at Delco Electronics in Kokomo, IN, for early automotive electronic ignition systems. In a moment the name of the device technology will come to me... or not.

juretrn wrote:What did you use -1553 bus for? I guess weapons. Anything else?

Yes, it was an interesting story to read.F-16 was the first to use the 1552-bus, and except for the flight-control system all of the F-16 avionics was connected to the dual redundant 1553-bus.The next one out was the AH-64 i think.

So far as I know, and I'm not at all well informed on the YF-16 program, the proof of concept aircraft were not fully functional or used existing equipment in place of purpose-designed equipment. The latter came later after General Dynamics' entry in the competition was selected for production.