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Applied High Resolution Digital Control forUniversal Precision SystemsbyAaron John GawlikB.S., Mechanical Engineering, University of Minnesota (2006)Submitted to the Department of Mechanical Engineeringin partial fulfillment of the requirements for the degree ofMaster of Science in Mechanical Engineeringat theMASSACHUSETTS INSTITUTE OF TECHNOLOGYJune 2008@MassachusettsInstitute of Technology2008. All rights reserved.A uthor ........ ........................Department of Mechanical EngineeringMay 13, 2008Certified by.. ..............................David L. TrumperProfessor of Mechanical EngineeringThesis SupervisorAccepted by..........................................Lallit AnandChairman, Department Committeeon Graduate StudentsMASSACHLOSTTS INSTMlArE,OF TEOHNOLOGYJUL2 9 2008LIBRARIESI IIApplied High Resolution Digital Control for UniversalPrecision SystemsbyAaron JohnGawlikSubmitted to the Department of Mechanical Engineeringon May 13, 2008, in partial fulfillment of therequirements for the degree ofMaster of Science in Mechanical EngineeringAbstractThis thesis describes the design and characterization of a high-resolution analog in-terface for dSPACE digital control systems and a high-resolution, high-speed dataacquisition and control system. These designs are intended to enable higher precisiondigitalcontrol than currently available. The dSPACE system was previously designedwithin the PMC Lab and includes higher resolution A/D and D/A interfaces thannatively available. Characterization on the custom A/D channel demonstrates 20.1effective bits, or a 121 dB dynamic range, and the custom D/A channel demonstrates15.1 effective bits, or a 91 dB dynamic range. This compares to a 15.7 effective bits onthe A/D dSPACE channel and 12.3 effectivebits on the D/A dSPACE channel. Theincreased resolution is attainedby higher performance hardware and oversamplingandaveraging the A/D channel. The sampling rate is limited to 8 kHz.The high-resolution, high-speed data acquisition and control system can sampletwo A/D channels at 2.5 MHz and display/save an acquiredone second burst. TheA/D channel is characterizedat 109 dB dynamic range with a grounded input and 96dB dynamic range, or 0.74 nmRMS over a 50 pm range, with a fixtured capacitiveprobe. Acquisition at 2.5 MHz andclosed-loop control at 625 kHz sampling rate isimplementedon a National Instruments FPGA. The A/D circuit was designed andbuilt on a customprinted circuit board around the commercially available AD7760sigma-deltaconverter from Analog Devices and includes fully differential ±10V in-puts, a dedicated microcontroller to provide an initializationsequence, and digitalgalvanic isolation. LabVIEW FPGA code demonstratesarbitrary transfer fuictioncontrolimplementation. The digital platform is applied toa 1-DOF positioner todemonstrate 0.10 nm RMS controlover a 10 pm mechanical range when filtered tothe 1.5 kHz closed-loop bandwidth, which is limited by the A/D converterarchitecturepropagationdelay.Thesis Supervisor: David L. TrumperTitle: Professor of Mechanical EngineeringAcknowledgmentsI would first like to thank my advisor, Professor David Trumper. Professor Trumperhas been an inspiration with his knowledge of all things mechanical, electrical, andinterdisciplinary-related fields and provides insight that I would otherwise not haveconsidered. His hands-offstyle has allowed me to learn on my own and yet have theguiding support to keep my perfectionist traits on track towards a final destination.Because of him I am a more confident than ever in my engineering skills. His reviewof this thesis was essential to my own understanding and hopefully clearly conveyingmy work.I would also like to thank my family for their continual support, particularlymybrother Noah who haspersonal experience in many applications that I have dealt withthroughout this thesis work. His experience with LabVIEW FPGA implementationsand general digital controls provided an excellent soundboard as well as an honestopinion.David Ottenwas always willing to assist with the high-resolution dSPACE sys-temthat he designed, and his two notebooks of documentation were essential tounderstanding, characterizing, implementing, and improving the design.The amazing educators between MIT and Harvardprovided an understandingin multidisciplinefields that I would never have expected to achieve two years ago.Particularly I need to thank Professors Tom Hayes and Paul Horowitz for their fimda-mentally applied electronics course at Harvard, providingthe skills to write firmwareand design the AD7760 A/D PCB. Professor Horowitz was also awilling soundboardon high-resolution A/D characterization. I need to thank Professor James Robergeforpushing the students of 6.331 to constantly achieve more andinnovate on traditionaldesigns. Numerous earlymornings finishing labs, piece sets, and design problemswere worth the effort consideringwhat I learned and my gained confidence in ana-log design.Dr Kent Lundberg was critical thanks to his comprehensivenotes andrecitation lectures.TheNational Instruments FPGA implementation for high-speeddata acquisitionand control provided a source of frustrationat times but was eased by Lesley Yu - NIfieldapplications engineer, Carla Uribe - NI applications engineer, and Erik Goethert- Boston Engineering program manager.Lastly I need to thankmy fellow graduate students and support staff throughoutMIT. Ian MacKenzie provided a fundamental understandingof control and electro-magnetics, as well as time to work together on the high-speed AFM project forwhichthe FPGA-based systemwas designed for. We also found ourselves on the samecourse track and he was alwayswilling to discuss how he understood problems fromMEMS processes to the hybrid-pi modelto switching power converters. Kevin Miuwas also invaluable with all things controls, electrical, lab, and MITrelated. Hisworkeffort has been an inspiration. Other students that influenced my work includeLevi Wood, Eerik Hantsoo, AdamWahab, Dan Burns, Dan Kluk, and Dean Ljubicic.Laura Zagonjori was invaluable with purchasing,administrative tasks, and trackingwhen Professor Trumper would be next available as well as providinga reprieve froma windowless basement lab. I need to thank Lenny Rigione of the Ceramics Process-ing Research Laboratory for use of a6.5 Keithley digital multimeter. Finally LeslieRegan and the mechanical engineering graduate support staff have helped make thepast two years possible and even enjoyable.For Mom &DadContents1 Introduction 211.1 Project Goal and Summary .............. ......... 211.2 Motivation and Context ......................... 321.2.1 Digital Control Systems ................... .. 331.2.2 Analog-to-DigitalConversion Methods ............. 361.2.3 Digital-to-AnalogConverting Methods ............. 472 dSPACE Interoperable High-ResolutionAnalog Interface 512.1 System Description and Design ................... .. 522.2 System Characterizationand Results .................. 573 High-Speed, High-Resolution Digital Platform Requirements andSelection713.1 Application Description......................... 713.2 ADC Requirements and Selection ....................733.3 Digital Platform Requirements and Selection ..............803.4 DAC Requirements and Selection ................... .914 24-bit A/DCircuit & PCB Design954.1 Analog Interface .............................. 984.2 Power Regulation and Decoupling ....................1084.3 DigitalInterface and Microcontroller Design .............. 1104.4 PCB Construction and Debugging.................... 1175 LabVIEW Control Software5.1 High Level Layout .......................5.2 A/D Acquisition Interface....................5.3 D/A Output Interface ......................5.4 Digital Control Implementation .................5.4.1 PID Control ........................5.4.2 IIR Control from Arbitrary Discrete Transfer Function5.4.3 Additional Filter Implementations ............5.5 User Interface and Post-Processing .......... .....6 ExperimentalResults6.1 A/D Characterization Results ..........6.2 Sub-Nanometer Position Control Results ....7 Conclusions and Suggestions for Future Work7.1 Conclusions ....................7.2 Suggestions for Future Work ...........A SchematicsA.1 dSPACE High-Resolution ADC PCB SchematicA.2 dSPACE High-Resolution DAC PCB SchematicA.3 AD7760 PCB Schematic, Rev 4 .........A.4 AD7760 PCB Billof Materials, Rev 4 ......B AD7760 Microcontroller FirmwareC LabVIEW FPGA CodeC.1 A/D Acquisition State Machine .........C.2 D/A Output State Machine ...........C.3 Filter/ControllerFPGA Code ..........C.3.1 MatlabTransfer Function Output m-fileC.3.2 LabVIEW Generator Code ........121123127132133138140148151155155163177177180187188190191196197207207212215215216.........................................................................................................C.3.3 LabVIEWGenerated Filter Code............ .... ..220C.3.4Example of LabVIEWFPGAControl Implementation:Lag,Triple-Lead..........................222Listof Figures1-1 dSPACE high-resolution DAC (Left) and ADC (Right) PCB ...... 231-2 A/D noise floor (left) and A/D response to 10 Hz sine wave (right). Thestandard dSPACE (DS) and out high-resolution (HR) A/D channel arecompared. On the left is the zero-input case. The graph on the rightshows the response to a 1 mV amplitudesine wave. ........... 241-3 Small amplitude D/A output.The standard dSPACE D/A and andour high-resolution (HR) D/A are compared. ............... 241-4 ADC PCB (quarter shown for scale). ................... 271-5 IIR filter canonical control direct form II block diagram. ....... .291-6 Simplified schematic of sigma-delta analog operation, adapted from [1]. 401-7 Quantized sine wave with n = 2 bits. ................... 421-8 Block diagram of sigma-deltamodulator, adapted from [1]. ...... .431-9 Second-order sigma-delta modulation, adapted from [1].........441-10 Sigma-delta modulation noise distribution. ................ 441-11 Sigma-delta FIR filter response [2]. ....................451-12 D/A converter hardware architectures.1 - Weighted-resistor network.2.1 - Voltage output R-2R resistornetwork. 2.2 - Current output R-2R resistor network. The output node can be terminated at a virtualground of an op-amp to form a current-to-voltage converter. 3 - Seg-mented implementation ..........................482-1 dSPACE high-resolution DAC (Left) and ADC (Right) PCB...... 522-2 Magnitude frequency responseof averaging filter for N = 100 at 800kSPS, before decimation .......................... 542-3 dSPACE data flow withhigh-resolution platform, adapted from [3]. .562-4 dSPACE subsystem timing [4] .......................582-5 dSPACE and high-resolution latching timeline at 8 kHz sampling. ThedSPACE channels are represented by DS and the high-resolution arerepresented by HR. The time scale is microseconds. ........... 582-6 Phase delay of 100 Hz sine wave for several connection options. Thetime axis is in milliseconds. Digital system sample rate is 8 kHz. ...602-7 Frequency response comparison, up to the Nyquist frequency.Thefrequency response as measured with the dSPACE DSA for both mag-nitude (top) and phase (middle) and the magnitude frequency responseas measured with the HP DSA (bottom). ................. 612-8 Dynamic signal analyzer configurations for dSPACE software DSA(left) and hardware HP DSA(right). ................... 622-9 A/D noise floor (Left) and A/D responseto 10 Hz sine wave (Right). 632-10 High-resohltion characterization schematic for A/D and D/A channels. 642-11 RMS noise on A/D channels across full input range. .......... .652-12 Asymmetric RMS noise on high-resolution A/D channel across fullinput range. The original configuration has two capacitors references tocommon and the revised configuration has a single capacitor referencedbetween the differential signals. ..................... 662-13 High-resolution analog front-end configurations: asymmetric high-noiseconfiguration (left) and symmetric low-noise configuration (right). .. 662-14 High-resolution D/A glitch ...................... 672-15 D/A baseline noise with 1 MHz low-pass filter on differential amplifier. 682-16 RMS noise present on D/A channels across full range. A singledSPACED/A channel (dachl) is provided against several high-resolution D/Achannels (daxx) ........... ................... 692-17 Small amplitude D/A output.. ...................... 703-13-23-33-43-54-14-24-34-44-54-64-74-8 Analoginput differential amplifier anti-alias configurationfrequency4-94-104-114-124-134-144-154-16response ................... ..........Analog input PCBlayout. ...................PCB voltage regulation ....................Example of AD7760 supply decoupling. ............EMI suppression equivalentcircuit. ......... .....AD7760 PCB digital interface and components. ........Microcontroller code block diagram................AD7760 PCB clock management block diagram. ........Level translator simplified schematic[9]. ......... ..5-1 FPGA high level layout ..............5-2 Digitized control platform block diagram.......5-3 FPGA fmnctional elements. ...................106..... 107.....108.....109.....110.....111.....114.....115.....118..... 124.....125..... 125X3-SDFhardware by Innovative Integration [5]. ............Real-Time computer developed by Xiaodong Lu[6] ..........VMETRO embedded computing FPGA block diagram [7] ......Data acquisitionand control hardware overview. ............National Instruments PXIchassis with embedded controller and FPGAboard ...................................ADC PCB fimnctional diagram.......................ADC PCB with functional areas (quarter shown for scale) ......Differential input shift andscaling; analog input to PCB (left) andanalog input toAD7760 IC (right). ....................Fully differential amplifier symbol.....................Simplified fully differential amplifier internalcircuitry [8] .......Fully differentialamplifier with scaling and anti-aliasing components.Half-circuit analysis of symmetricfully differential amplifier with shuntcapacitor.The single capacitor (left) between differential signalscanbe replacedby two capacitors (right) referenced to ground ......78818788909697991001011021045-4 Block diagram of discrete sampling rate compressor,adapted from [10]. 1265-5 A/Dto FPGA signal propagation delays. .................1285-6A/D acquisition state diagram. ..................... 1295-7 Exampleof LabVIEW FPGA code for A/D acquisition- RaiseRD state. 1305-8 A/D data sample output two's complement format. ........... 1315-9 Converting two's complementto signed 32-bit integer .... ..... 1325-10 D/A output state diagram........................1345-11 FPGA sequential (left) versus parallel/pipeline (right)processing. Pipelineprocessing can be implemented with shift registers (top) or feedbacknodes (bottom ) ................... ............ 1355-12 Block diagram of discrete downsampler,adapted from [10]. ....... 1365-13 FIR N = 2 pole-zero map andfrequency response at 2.5 MHz samplingrate. .....................................1365-14 Expected frequency response for the digital controlsystem. ....... 1385-15 LabVIEW PIDblock ............................ 1395-16 IIR filtercanonical control direct form II block diagram. ........ 1415-17 FPGA IIR filtercode generation block diagram. ............. 1435-18 Quantizer error introduction in a fixed-pointfilter [11]. ......... 1435-19 Discrete-Timeintegrator with anti-windup example. ...........1495-20 N-point average window FPGA implementation. .............1505-21 Front panel user interface. ......................... 1536-1 Grounded input A/D count histogram................... 1566-2 Grounded input time responsein a 400 ps interval(top) and corre-spondingunfiltered FFT (bottom). ................... 1576-3A/D, FPGA, D/A system frequency response. The magnitudeof themeasured digital platform with delayand the expected with delay arecoincidentand thus the measured result is not independently visible. 1596-4 Power density spectrum to 1 kHzsine wave with coarse (left) and fine(right) scale .. ...............................1596-5 Grounding diagram for capacitive probe measurements with "star"earth ground configuration on experimental AFM scanner application.Stationary/fixturedprobe tests use the same configuration, althoughthe "isolation table" is replaced by the fixture............... 1646-6 FFTof the response of 50 Am probe on stationary target with 298 pVRMS unfiltered baseline noise.This was measured on with the customA/D PCB hardware and LabVIEW acquisition software. ........ 1656-7 2-DOFhigh-scan rate positioner CAD model [12]......... .. .1666-8 2-DOF high-scan rate positioner hardware. ........... ....1676-9 Spring-mass-damper mechanical model. .................. 1686-10Z-axis measured open-loop and expected system loop transmission ondSPACE control platform [12] ....................... 1696-11 Controlled z-axis time response (top) and FFT (bottom). ........ 1706-12 Relative comparison of unfiltered measured RMS position with dSPACEand FPGA digital platform closed-loop control to a constant referenceover 20 ms (left) and 2001s (right). .................... 1716-13 Z-axis measured open-loop and closed-loop loop transmission on FPGAcontrol platform. ............................. 1726-14 Z-axis measured step response and error. ................. 1736-15 Loop transmission measurement scheme. ................. 1746-16 Parametric amplitude control loop [12]. ........ .......... 1757-1 High-resolution D/A voltage referencenoise and effect of passive low-pass filtering: the voltage reference noise measured with a TektronixAM502 differential amplifier and 1 MHz low-pass filtering(left), thevoltage reference noise measured with the differential amplifier and 30kHz low-pass filtering (middle), and the voltage reference after a 4 kHzpassive low-pass filter measured with the differential amplifier and 1MHz low-pass filtering (right). ................... ...1817-2 Recommendedhigh-resolution, high-speed data acquisitionand controlenvironment. Separateacquisition and control A/D channels are usedfor data acquisition and control. TheD/A converter is replaced withone capable of a high output sample rate ................. 185List of Tables2.1 dSPACE Subsystem Timing ....................... 592.2 A/D Noise Floor Comparison ...................... 633.1 Analog-to-Digital Converter IC Commercial Options ......... 753.2 Analog-to-Digital Converter Commercial Options ........... 763.3 Innovative Integration X3-SDF Implementation Estimated Costs ...803.4Custom Real-Time Computer of Xiaodong Lu Estimated Costs .... 843.5 Xilinx Development Platform Estimated Costs ............. 853.6 Third-Party Digital Platform Estimated Costs ............. 863.7 National Instruments Digital PlatformEstimated Costs ........ 893.8 Digital Platform Estimated Comparison ................ 913.9 Digital-to-Analog Converter IC Commercial Options ......... 924.1 Differential Amplifier Component Values ................1054.2 Analog Input Differential AmplifierAnti-alias Pole Locations ..... 1066.1 Capacitive Probe Characterization and Baseline Measurement Results 162Chapter1IntroductionFor any precision motion control application, it is critical to maintain precision amongvarying engineeringfields and through the combination of actuators, mechanical sys-tems, sensors, electronics and digital computations, whichgenerally requires an ad-vanced knowledge and application of structural mechanics, design, analog electron-ics,digital electronics, electromagnetics, signal processing, and control. This thesisfocuses on enabling precision motion controlhardware systems by improving or de-signing digital control environments that increase performance over what is currentlyavailable.Precision control has a variety of definitions in a variety of applications. Precisionis technically the degree to which a measurement (e.g., the mean estimate of a treat-ment effect) is derived from a set of observations having small variation (i.e., close inmagnitude to each other) [13]. A narrow confidence interval indicates a more preciseestimate of effect thana wide confidence interval. Thisis applicable to digital data,where a more precise numerical value contains a greater number of meaningful bits.1.1 Project Goal and SummaryThis thesis focuses on two separate high precision digitalcontrol systems for differ-ent applications. The first focuses on creating more precise analog-to-digital (A/D)and digital-to-analog (D/A) interfacesfor the commonly used dSPACE [14] controlplatform. The PrecisionMotion Control (PMC) Laboratory at the MassachusettsInstitute of Technology, as well as the mechatronics anddigital control graduatecourses use varying products from dSPACE, Inc [14]. The platform is intendedas anembedded control environment with built-in peripherals, providing a real-time envi-ronment that can be programmed withMatlab's Simulink Real-Time Workshop [15].The DS1103 dSPACE platform provides 16-bit A/Ds and 14-bitD/As with doublefloating-point, or64-bit sliding window, calculations. Loop rates up to 100 kHz arepossible if the calculationload is small.David Otten, a research scientist previously with the PMC Laboratory, designedand built these interfaces [4] as a universal high-resolutionperipheral option opposedto the dSPACE native analog interfaces. The design was initially appliedto con-trol a sub-atomic measuringmachine (SAMM) at the University of North Carolina-Charlotte (UNCC) [16]. The high-resolution system by Ottenrequired the physicaldesign of the A/D and D/A channels and their software interfaceto the real-timedSPACE environment and Simulink functions. Up to 8 inputs or 6 outputs couldbe interfaced through a modular breakout PCB and Simulink software. Each A/Dand D/A channel is builton an individual PCB with dedicated power regulation.These are shown in Figure 1-1. A distinct feature are digitalisolators for galvanicisolationwhich break ground loops between the analog hardware plant and the digi-tal environment, a commonly significant sourceof disturbances or noise in precisionsystems.High-speed samplingand averaging is used to increase the A/D resolution to20.1 effective bits. A dedicated DSP onthe A/D PCB sums the A/D samples at800k samples per second (SPS) and counts the numberof samples. The sum andcount is then transferredto dSPACE hardware through the software interface whereit is averaged.This resolution compares to 15.7 effective bits as measured with thedSPACE A/D channels. Figure 1-2 shows a comparison betweenthe dSPACE (DS)and the high-resolution (HR) channel.Significant quantization relating to errorsdistributedover several LSB are apparent in the dSPACE baselinenoise response.These quantization levels are 305 mV/LSBfor a 16-bit converter on a 20 V range. TheFigure 1-1: dSPACE high-resolution DAC (Left)and ADC (Right) PCB.high-resolutionmeasurement however displays no discernablequantization levels andhas a noise level of 15 pV RMS. Likewise, the 1 mVamplitude sine wave demonstratesthe increased resolution performance as well.There was little characterizationdata available on the performanceof the twochannels when Iinherited the high-resolution design.Several anomalies appearedin initialtests that required design changes. Themost significant was a change tothefully differential analog front-end inputof the A/D converter. Initiallythe RMSnoise of a digital sample would varyfrom 16 to over 20 effective bits basedon theinput voltage level. This issue wassolved by altering the configurationof anti-aliasingcapacitors.A 16-bit D/APCB was designed and builtas a companion to the A/Dchannelwhich also utilizeddigital isolation a smallfootprint so it could be locatednearthe analog plant.Figure 1-3 demonstratesthe increased performancefor the high-resolution channelagainst the dSPACE channelfor a small amplitudeoutput. ThedSPACE D/Ahas a quanta size of 1.2mV for its 14-bit converterand the high-resolution D/A has a quantasize of 305 mV for the 16-bitoutput.This increasedresolution comesat the cost of a maximumloop rate of 8 kHz.A slave DSP onthe dSPACE hardwareis used to interfacewith the custom PCBs.Theslave DSP needs to interactwith the mainprocessor that runs theSimulink0 0.0 0.1 0.15 0.2 0.25 0.3 0.35 OA 045 0.5Tlme[SlTime[S]Figure 1-2: A/D noise floor (left) and A/D response to 10 Hz sine wave (right). Thestandard dSPACE(DS) and out high-resolution (HR) A/D channel are compared.On the left is the zero-input case. The graph on the right shows the response to a 1mV amplitudesine wave.A0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.0160.018 0.02Time[s]Figure 1-3: Small amplitude D/A output. The standard dSPACE D/A andand ourhigh-resolution (HR) D/A are compared.4+application and does so througha communication buffer that requires communicationtime. The slave DSP then clocks datato D/A channels and from A/D channels, whichrequires 32 clock cycles. The total process time is 113 As and is the limiting factorfor the maximum loop rate.Additional improvements to the prior system designedby David Otten includeddebugging of why only 6 of8 D/A channels were available at a time. I found thatalthough softwareprovided an 8-bit port in software, only 7 bits were available in thecabling pinout. Further, of these 7 bits, one was not correctly interfaced. The 7thD/A channel was implemented but in order to add the8th channel additional stepswouldneed to be added to the slave DSP and thus further decreasing the maximumloop rate.Other than the maximum loop rate constraint, thesehigh-resolution peripher-als appear as any dSPACE peripheral doesand are essentially invisible to the userto implement andoperate. Applications for this first work are systems requiringhigh-resolutionwith relatively low bandwidth, i.e. on the order of bandwidths ofHz. Examples include vibration isolation with bandwidths onthe order of 10 Hz orprecision atomic force microscopy,with bandwidths on the order of 100 Hz.The second half of this thesisfocuses on a high-speed, high-resolution data ac-quisitionand control digital platform. The design wasdriven by specifications fora high-speed atomic force microscope which requiredover 20-bit resolution data ac-quisition at greater than 1 MHzsampling rates as well as real-time control. Dataacquisition as opposedto control implies that while data mustbe sampled and storedat a given rate, processing of said data can bedone off-line and at slower rates. Thesespecifications require both hardware and softwareto be operating at high rates andhighresolutions, so it is attractive to use the samehardware and software to closethe control loop.Various commercialoptions were evaluated and it was determinedthat we shoulddesign our own A/D PCB builtaround a 24-bit, 2.5 million samples persecondconverter that is interfaced to field programmablegate array (FPGA) with ahostfor dataoffloading and supervisory control.A custom A/D PCB was designedandtested based on the Analog Devices AD7760 sigma-delta IC. Most of the design con-cepts were adapted from an evaluation board design available from Analog Devices.I considered purchasing the evaluation board and merely designing the interface elec-tronics, however the board was never available for purchase over the course of theproject. Furthermore, errors were discovered in the evaluation board design through-out the testing and debugging phase that would have limited its functionality had itbeen available.The A/D PCB incorporates the same digital galvanic isolators asthe high-resolutiondSPACE PCBs, as well as a dedicated microcontroller to provide an initialization se-quence for the A/D converter IC and supervisory control during operation. Locatingthe initialization sequence on the PCB actually reduces the hardware complexity be-cause fewer digital isolators arerequired, since only unidirectional digital isolators areavailable at the required data rates. Additionally, the inexpensive microcontroller re-duces expensive resources that need to be allocated from the FPGA. The operationalA/D PCB is shown in Figure 1-4, with a U.S. quarter for scale.Althoughthe A/D converter is listed as a 24-bit converter, the dynamic rangeis much less at high sampling speeds. The datasheet claims only 100 dB SNR at2.5 MSPS. Tests on a grounded input demonstrated 66 pV RMS noise over a ±10V range, which is equivalent to 109 dB RMS noise. Tests on a highperformancecapacitive probe fixtured to a stationary target matched the noise characterizationof the probe itself. The capacitive probe had a characterization noise level of 309 pVRMS and the A/D measured 298 pV RMS without any additional filtering.No viable commercial options were available at the time of initial design of theA/D PCB. Since that time a commercial option has become available from InnovativeIntegration [17] based on the same A/D hardware and similar processing hardware hasbecome available. In retrospect, usingthat commercial board would have saved somerepetitive design and debugging, however it would be less advantageous consideringcost and future flexibility in implementation and expansion.Several options existed as the digital processing platform. These ranged from acustomdesigned and programlmed array of dedicated digital signal processors (DSP)Figure 1-4: ADC PCB (quarter shownfor scale).to third-party hardware and software. Ultimately an FPGA-basedproduct fromNational Instruments[18] was selected that could operate with existing hardwarein lab. This existing hardware included a PXI chassis with a dedicated real-timecomputer. This computer runs a real-time operating system and has much higherreal-time performance than a Windows or even Unix-based system.National Instruments also supplied a high-level graphicalprogramming languageand environment (LabVIEW)for all hardware aspects. This included the develop-ment platform for the FPGA program, real-time application, and supervisory host.FPGAs are physically thousands of reprogrammable logic units that are connected byreprogrammable interconnects with logic suited to fixed bits of simpledata manipula-tion operations. LabVIEW provides high-level, complex operationswhich reduces thelearning curve for writing FPGA code and allowsimplementation of more complexapplications more quickly.FPGA code in the LabVIEW environment was written for 2.5 MHz data acquisi-tion and closed-loop control rates up to 625 kHz. Data acquisition from the D/Aiscompleted with a finite state machine clockedat 80 MHz. LabVIEW also providesother complex features that can be easily implemented.For example, direct memoryaccess was used to transferthe acquired samples directly into the host computer'smemorywithout being delayed by host processing. Although sustainability tests werenot completed, the system was able to store at 20 MB over one secondbursts. Thisenabled data storage and off-line post-processing.A D/A channel is also required to enable closed-loopoperation. Following anavailable product survey, I decided thatthe previously designed high-resolution D/Achannel for the dSPACE environmentwas an appropriate option for the FPGA systemas well. However, the closed-loop cycle rate is limited to 625 kHz by the rate at whichthe D/A can be clocked.Traditional linear feedback control can be quantitativelydesigned and is typicallyimplemented with lead-lag control. The NI LabVIEW FPGA module provides a PIDimplementation, howeverit is limited in functionality and flexibility. The PID coeffi-cients cannot be easily adapted to a lead configuration, and the data path islimited tou(z)e(z)Figure 1-5: IIR filter canonical control direct form II block diagram.16 bits whereas a 32-bit data path is preferred. The most efficient method to processa controller transfer function is in canonical direct from II, represented in Figure 1-5.The transfer functionis implemented as zero coefficients bi and pole coefficients aj.The canonic form reduces the ai and bi coefficients to the minimal representation anddirect form II reduces the number of delay/memory (z- 1) elements required. The onlyoperationsrequired for processing a direct form IIfilter are addition, multiplication,and state delays. The filters are defined as discrete-time filters in the z-plane withsampling time Ts = 400 ns. They are transformed from the s-plane with the Tustintransformation without warping. I found that time delays due to data transferringwere minimized by implementing control before decimation.A LabVIEW FPGA function is used to generate the controller filter code that iscompiled to the FPGA. The filter is an infinite impulse response filter because it hascoefficients in both the forward and reverse directions, indicating that there are non-zero poles and an impulse can persist infinitely. LabVIEW codewas written to importan arbitrary floating-point control filter and convert it to a fixed-point filter. Thisintroduces quantization errors as the overallword length and integer word lengths forthe coefficients are individually specified.Coefficients that are widely spaced, suchas 100, 0.1, and 10- 4, provide issues in quantization because they requireboth awide range and decimal precision.For filters whose performance depends on closelyspacedpoles, particularly as they approach theunit circle of the z-plane, significantquantization errors can often reduce performanceor introduce instability.In our approach, control filters designed in the real-timedomain are reduced tosecond-order stages. A cascaded transformation to can be used inthe LabVIEWfiltergeneration, however quantization can only be specified for theentire system,whereas when separate control filters are manuallycascaded then quantization canbe specified for each filter individually. Quantization settings arealso applied to otheroperations by the LabVIEW filter generation process, such as addition,multiplication,and delays. Delays are implementedas block RAM on the FPGA board and decreasesthe number of required registers.Fixed-point filters and theiroperations are implemented as integer operations.This requires a pre- and post-scaling by a fixeddecimal word length. Fixed-pointmultiplication also presents a challenging issue because for every operationof ordern, the output order is 2n.Two 16-bit integers multiplied together require a 32-bit output to avoid overflow saturation. Thereforea special multiplication blockwas created in LabVIEW that multiplies to the full precision andthen translatesback to the original order.This significantly reduces rounding errors. The blockwas implemented as paralleloperations to use more readily available logic blockson the FPGA and operate more efficiently. These multiplicationblocks were alsoused to implement arbitrary gains that a user can vary.Along with traditional lead-lagtransfer functions, other control oriented features are describedand used. Thisincludes saturationfor integral anti-windup and reference signal generation.This high-speed, high-resolution digitalplatform was implemented with AFMscanner hardware designedand built by Ian MacKenzie. The scanner has 2-axis po-sition feedbackfrom two high-performance capacitive probes from ADE [19],model6501 withranges of 40 and 50 pm. These probes have a baseline noiseof 181 and 309pV RMS, respectively, as characterized by ADEfor +10 V outputs at a bandwidthof 100 kHz.When sampled with the custom A/D channel, an approximate 100kHzdisturbance was generated within the capacitiveprobe driver and measurement elec-tronics. This is due to the A/D channel but the mechanism by which it is affectingthe measurement electronics is not known, despite extensive tests. The disturbancecan be measured even when the A/D channel is not connected but merely running inthe vicinity. Varying grounding configurations were able to reduce this disturbancebut it currently introduces the dominant noise content when the probe is measuringa stationary target.The A/D channel is ableto measure 252 and 298 pV RMSunfiltered, respectively,on a stationary target at 2.5 MSPS. Control was implemented on one of the axesdesigned for 10 pm range with the 40pm probe and achieved 430 pV RMSunfiltered,or 0.86 nm RMS. When filtered to the 1.5 kHz closed-loop bandwidth, control achieved0.10 nm RMS, equivalent to 111.7 dB dynamic range and 18.3 effectivebits. Theclosed-loop samplerate was 625 kHz and the phase margin at 1.5 kHz crossoverfrequency was 37 degrees. The control scheme was a triple-lead, single-lag controllerand was implementedas the series combinationof a loop gain, three IIR lead filters,and lag with anti-windup. The loop required approximately 20 degrees of additionalphase compensation due to the A/Dand processing time delay. The A/D is a sigma-deltaconverter and thus introduces a propagation delay of 10.8 ps. The remainingtime delay leading to a total of 23.2 ps is due to acquiring thedata, passing the databetween parallel loops,and passing the data through IIR control filters. The dataprocessing iscapable of a 400 ns sample rate with an arbitrary number of controlfilters because data pipelining is utilized. This maintains a high samplerate butalsoincreases the propagation delay. Alternatively the sample rate can be decreaseddown to the output rate of 625 kHz but the time delays associatedwith data transferswould then be increased. The closed-loop bandwidthcould be increased but the linearphase loss due to the time delays requiresincreasing lead control. This increasing leadcompensation is limited by the magnitude roll-off.The other axis consisted of a parametric amplitude controlloop. Although theFPGA designis presented, it was not implemented in hardware. The singleaxishowever demonstrates sub-nanometer control.1.2 Motivation and ContextAnalog electronics can resolve on the order of a part in a million in a carefully designedsetup. This relatesthe absolute range to the resolution of the system. Precision con-trol can thus be attained for meter ranges with sub-millimeter resolution, or micronranges with sub-nanometer resolutions. Analog electronics are then able to controlto this precision. The ability to actuate a given system andthen sense that motionis another issuealtogether. Precision motion control is driven by improving compo-nents with dominant noise contributions, which is a reason why piezoelectrics andelectromagnetics are common actuators; their precision is commonly limited to theelectronics driving them. This is also a reasonwhy mechanical flexures are extremelypopular for constrained motionas they allow linear motion without stiction and otherdiscontinuous affects on a fine scale. Similarly, technology in capacitive sensors, en-coders, and laser interferometry is providing higher precision position sensing.Analog controls can be applied in contrast to digital controls. Analog systemsare simple to implement for linear systems and high precision can easily be attainedfor high bandwidths with a low cost. However, analogcontrols are not very flexible.Digital systems on the other handle allow a multitude of control algorithms to beflexibly implemented, albeit at a greater cost, such as discontinuous, nonlinear, adap-tive, or feedforward control. Digital systems and their implemented control are alsonot prone to environmental conditions, to the first order, as opposed to capacitorsand resistors in analog systems. The maximum bandwidth for an analog system caneasily be greater than 1 MHz withbetter than 10 ppm resolution. It is difficult tomatch these specifications withdigital systems at this time.This thesis works to improve the available resolution and bandwidth of digitalcontrol systems. Chapter 2 describes a design for a high-resolution analog interfacethatwas previously designed and built by David Otten within the PMC lab as anotheroption to native dSPACE A/D and D/A converters.The design is characterized and Idescribe improvements for a lower baseline noise. Chapter 3 presents requirements fora high-resohltion and high-speed data acquisition and control digital platformas wellas viable options and the selected components. Subsequent chapters detail the designof the hardware, software, and control implementation as well ascharacterization andresults when the digital systemis applied to a 1-DOF positioner of 10 pm range andsub-nanometer control at 1.5 kHz crossover frequency.The remainder of this section describes various digital control, A/D, and D/Aarchitectures. These three components determinethe closed-loop precision and datarate.It is important to understand the background and available options for thevarious components and techniques within high-resolution digital systems and theassociated interfaces.1.2.1 Digital ControlSystemsDigital control uses electroniclogic to act on a system. The implemented hardwarecanrange from an ASIC to a microcontroller to a full dedicated computer. Thedifference between a piezoelectric actuator and astepper motor are analogous tothe difference betweenan analog and a digital control system; the digital systemis inherently finite precision whereas the analog system merely has a baselinenoisefloor. This introduces quantization in coefficientsand operations. The analog-to-digital and digital-to-analog interfacesare also finite precision and introduce their ownquantization. Anotherdifference between analog and digital systems is propagationdelays. Digitalsystems frequently have a non-negligible computation time. Highdata rates can be maintained by pipelined computations, however the time latencystill introduces a phase lag at the bandwidth of interest,which is troublesome forclosed-loop control bandwidth.Digital sampling usually introducesa zero-order hold at its output due to thediscontinuous natureof the input/output samples. The time delay fromthe input tothe output ofa digital system with ideal converters in this case ishalf the samplingtime T,. The timedelay due to computations or latency in the digitalsystem isTd. The total delay time is then Td +L.This demonstrates that it is necessary tominimize any system latency while also maintaininga high sampling rate for highbandwidthsystems. Computations with increasing precision,such as floating-pointas opposed to fixed-point, require more time to complete.The high-resolution, high-speed system described in Chapters 3 through 6 is im-plemented with a system that is expected to have a closed-loop bandwidth up to5 kHz. Typically a digital system requires requires a sampling rate on the orderof 10-20 times the closed-loop bandwidth [20], thus requiring a closed-loop rate ofapproximately 50-100 kHz for this bandwidth.The digital system architecture determines Td for a given controller. A digitalsystem, or a real-time computer, needs to provide low latency real-time services aswell as a user interface. Real-time services act onthe signal and determine thecontrolled output at afixed frequency. The user interface displaysmeasured signals,allows user interaction with gains and controllers, and provides data logging. Theearliest architecture to achieve these two services was the the Uni-Body architecturewhich operates with interruptsand a foreground-background architecture on a singlecomputer. An interrupt is initiated at a fixed frequency. The interrupt then runs thereal-time services in the background and the remaining time before the next interruptconstitutes the foreground where the user interface is processed. If the foregroundprocessing consumes too manyresources then loop jitter and latency is introduced.Running an operating system such as Windows requires a lot of resources and thefixed sampling rate needs to be decreased.The next architecture is the Dual-Body which has a host and a target. TheUni-Bodyarchitecture is implemented on the target computer with a dedicated real-time operating system (RTOS). The host machine runs an operating system such asWindows and displays the semi-real-time data transmitted from the target machine.The target machine sampling rate is still constrained by processing an interrupt, thereal-time services, and the foregroundservices. Examples of commercial Dual-Bodyarchitectures are Real-Time Windows Target by Mathworks, dSPACE, xPC Targetby Mathworks, and the Real-Time Module from National Instruments. Most of theseuse a singlededicated processor, such as a PowerPC or computer chip from Intel orAMD.Instead of interrupt-driven processing, polling operation can be implemented. Thisremoves the interrupt associated latency but also removes the host interface. This isgenerally not acceptable in real-time control applications, particularly in the controllerdevelopment process or when data acquisition is required.A multi-processor Dual-Body architecture is also becoming more popular, espe-cially because dualand quadcore processors are decreasing in price. The processorscommunicate with each other over direct inter-processor data busses. These systemsare capable of increased computing performance but are still limited by interruptassociated latency.A Triple-Body architecture decouples the foreground and background threads onthe target machine. This architecture dedicates one or more processors to the back-ground real-time services tasks and a separate processor to the foreground threadsand host machine interface. The foreground processor interfaces with the other pro-cessors on a shared data busand multi-port RAM. This has been implemented invarious applications [6, 21].Thus faronly traditional processor have been considered. Field programmablegate arrays (FPGA) are increasing in computational power while becomingless ex-pensive. The logic gatesare reconfigured for a specific application and the gatesare essentially reconfigured to a customizable dedicated electric circuit with clockingrates up to 200 MHz or greater. The FPGA can have many separatelogic circuitsthat are run in parallel. A single FPGA can then replace the multipleprocessors ofa Dual- or Triple-Body architecture.The computations are limited however becausethe logic architecture is suited for fixed-point simple bit operations. Even divisionrequires complex hardware to implementefficiently for both hardware utilization andoperation rate. Newer FPGA models arebeginning to incorporate dedicated pro-cessors directly into FPGA fabric, allowing for the high-speeddata transfer and bitoperations in the FPGA and complex data manipulationin the dedicated processor.Commercial vendors such as Innovative Integration [17]or VMETRO [22] provide anarray of FPGA/DSP combinationsintended for high loop rates.Along with sampling speed and time latency,another consideration is the precisionof the implementedcomputations. Data types from a single bit to signed integerstodouble precision are available in processors and fixed-point types are available inFPGAs. Floating-point computations can beemulated in IP programs on FPGAs,however they are extremely resource intensive. The fixed-point data type introducesquantization that needs to be considered in an error budget for the digital platform.The series of computations also needs to be analyzed so there are not underflows oroverflows to due rounding and saturation. Increasing data type resolutions requireeither increasing parallel hardware in an FPGA or a longer computation time indigital signal processors.Chapter 2 focuses on the analog interfaces as they are implemented with a dSPACEsystem. Computation precisionis considered briefly when the A/D oversample andaverage method is discussed. The limitingfactor in the system design is system la-tency due to data transfer to/from and within the dSPACE multiple processors. Therest of this thesis considers a suitable architecture and then suitable hardware toimplement for a high-resolution, high-speed digital acquisition and controlplatform.1.2.2 Analog-to-Digital Conversion MethodsA primary focus of this research effort is the design of analog-to-digital interfaces.It is possible to design the converter from discrete components, however commer-cial options are available with different architectures to meet our requirements forvarious applications. This section details differentanalog-to-digital converter (ADC)technologies and the application each type is designed for.State-of-the-art technology, in both research and commercial devices, demon-strates an inherent trade-off between resolution and sampling speed. Continuingdevelopment and advances are expected to follow this general trend [23]. High pre-cision instrumentation as well the communications industryhave continually pushedthe limits of ADCs. Reviews of the state-of-the-art devices have been published ev-ery 3-6 years over the last several decades, and while earlier ones demonstrate thecontinuing trends,the limits are being pushed further due to technological advances[23, 24, 25].Analog-to-digital conversion,as the name implies, is the interface between theanalog and digital environments. Many sensors, such as a capacitive probe or geo-phone, output an analog signal. This interface is then necessary in order to implementdigital acquisition or control. Critical criteria include the ADC native resolution andsignal distortion, or signal-to-noise ratio (SNR). Power consumption, the amount ofhardware required, and the characteristics of erroneous readings are also important.Other factors include the sampling rate, generally measured in samples per second(SPS), and the throughput delay. In a pipeline architecture, data must pass throughsequential stages. When a sample reaches one stage, a subsequent sample can enterthe previous stage, thus numerous samples can sequentially be passing through thepipeline at a time. Therefore the differentiation must be made between the samplingrate period T, and throughput delay Td.ADCs are available in several standard techniques. These include successive ap-proximation, flash, integrating, sigma-delta, pipeline, and hybrid technique convert-ers.Consumer driven markets are currentlypushing converters towards higher speedsat higher resolutionwhile reducing power consumption. This is partly achieved bylower supply voltages. This however requires smaller signal voltages that are thenmore susceptibleto noise from a variety of sourcessuch as power supplies, references,digital signals, electromagneticand radio frequency interference (EMI/RFI), and poorlayout, grounding, and decoupling techniques. Moves away from bipolar devices alsomean that ADCdifferential inputs are not generally referenced to ground and thusrequire differential amplifiersthat can scale and shift the signal.Flash ConverterA flash, or parallel-encoded, converteruses 21-1 comparators that are synchronouslyconverted where n is the number of bits of resolution. Thecomplementary compara-tor inputs are connectedto a corresponding reference voltage on an equally spacednetwork of 2" - 1 voltages. Digitallogic then decodes the output to n bits. Thedigital value is found at the break between comparatorsbeing on and being off. Thismethod is by far the fastest method and can convert a sample on the order of severalclock cycles. However, the hardware increases with the resolution. Not only doesit add complexity to implement that many comparators, but tolerances also becomeextremely tight on the reference voltage network. Also, false comparator values inthe thermometer code output can easily return a full scale error. Power consumptionis a concern because each comparator hasa minimum quiescent current. This cur-rent is increased in order to operate at high speeds. Assuming a 10-bit converter, 1kcomparators would be required as well as logic devices. Assuming 1 mA quiescentcurrent per comparator with a 5 V supply rail, the IC would need to dissipate over 5W of power.Typically flash converters do not require a sample and hold (S&H) because thesample is converted over a very small period and is not expected to be changing.Typically flash converters are available in 8 or 10-bit architectureswith samplingrates up to 1 GSPS.Successive ApproximationConverterSuccessive approximation register (SAR) converters, as the name implies, estimatewhat the sample voltage is, comparethe estimation to the sample, and then refinethe estimation. The SAR converter uses DAC feedback and a comparator to comparethe sample and estimation. A S&H circuit is required to maintain a constant voltageduring the conversion period. The successive approximations are bitwise. All bits areinitially zero and each bit under test is set to 1. The MSB comparison occurs first.If the sample is higher than the D/A voltage, the bit is left high and the next bit istested. This requires n conversions for n bits of resolution.The conversion time is limited by the settlingtime of the internal DAC. As theADC resolution increases, the required DAC settling time decreases as well because itmust settle to a finer resolution. Errors can be up to 1 full scale and be nonlinear dueto jumped codes for a constant input. SARconverters can reach 20 bit resolution butrequire longer conversion periods due to the additional number of approximationsrequired and the DAC settling time. Typically the integrated DAC uses charge-redistribution or a switched capacitor configuration. The digital sample is generallyready after n comparisons as there is negligible latency in theconversion process.Integration ConverterIntegration conversion is a very popular technique for precision instrumentation whenusing discrete components,however it has been used less with the advances of inte-grated circuits. Typicallydual integration is used. A referencevoltage is integrated,with an integrator op-amp configuration,for a given amount of time measured bya stableclock source and a counter. The integrator input is then switched to thesample voltage and integrated again. This essentially "deintegrates" the voltage backand when it reaches the initial voltage a comparator signals completion. The conver-sion is then proportional to thesample voltage and does not depend to first order onthe capacitoror clock speed. Absolute accuracy is limited by the voltage referenceand clock jitter. The resolution is limited by component errors,such as temperaturecoefficients and offsets, aswell as the clock rate. A benefit is that changes in thesample voltage areaveraged by the integration process, in particular at integer valuesof the integration frequency. This is useful for removing 60 Hz content onthe sample.The trade-off between conversionrate and resolution is one of the main drawbacksfor integrationconverters, however 18-bit converters are available at lower rates.Sigma-Delta ConverterSigma-delta (E - A) converters are a form of an integratorconverter and have becomemorepopular with technology improvements in integratedcircuits. Their analogelectronicsare simple compared to other techniques but are replaced by relativelycomplex operationsof oversampling, noise shaping, digital filtering,and decimationon the digital side. The analog electronicsare simplified as shown in Figure 1-6. Thevoltage inputis subtracted, or summed depending on theconfiguration, with a binaryVINIntegratorClockKfsN-BitsI-BitData Stream1-Bit DAC-VREFFigure 1-6: Simplified schematicof sigma-delta analog operation, adapted from [1].feedback signal. This signal is then integrated and comparedto a constant voltage.Thecomparator output is fed back to the input summing junction through a 1-bitDAC, creating the binaryfeedback. The comparator output is also fed to the digitalcircuitry as a bit stream, which is proportionalto the sample voltage. Because thefeedback is a single bit, the settling time is much faster than forSAR feedback.For example, givena DC input at VIN, the integrator is constantly ramping upor down at node A. Negative feedback through the single bit forces node B to beequal to VIN on average. Thisintuitively means that the average bitwise stream isproportional to VIN. A bitwise stream of all zeros relatesto -VREF and all onesrelatesto +VREF.In orderto understand the digital techniques employed, it is important to under-stand some fmndamentalconcepts. Quantization is the discretization of a continuoussignal. In this case, a samplevoltage is quantized to a digital word. The quanta sizeis synonymous with resolution, whichis defined byVRANGEVQ= (1.1)Forexample, a 1 V range with 8 bits has a resolution, or quanta size, of 3.9 mV.When a continuoussignal is quantized, there is inherentlyan error of as large as1the resolution. This can be seen in Figure 1-7 where the quanta size is 0.5. Note thatthe zero-order hold time delay is not shown. For a uniformly distributed signal acrossall quantization levels, the signal-to-noise ratio (SNR) is modeled as [26]SNR = 6.0206n + 4.77 - 10logl0or [dB](1.2)where 77 is the signal's peak-to-average-power ratio and n is the number of bits. Forasinusoidal signal77 = 2 [26],SNR f 1.763 + 6.0206n[dB] (1.3)This can be rearrangedto solve for the effective number of bits (ENOB) when theSNR, in dB, is measuredSNR - 1.763ENOB = - 1.763 (1.4)6.0206This is typically a better figure of merit compared to the specified number of bitsfor an ADC because it includes signal distortion. The effective number of bits isanalogous to numerical precision. The fact that a number canbe recorded with acertain precisiondoes not guarantee that the precision is actually 1 LSB. The ENOBdoes guarantee precision to this standard.For a signal that is sampled at a sampling rate of f,, the quantizationnoise poweris[27]02=(1.5)12The quantization noise in this modelhas a uniform spectrum is then spread from DCto the Nyquistfrequency, 1. Whenoversampling is implementedby a factorof K,the the Nyquist bandis -i-2. The simplest model assumes a uniformly distributedzeromean white noise [10]. The claim is also made that conversion values dependonpast conversions, so the error is not entirely uniformly distributed[28]. Quantizationis inherently a nonlinearprocess, but the linear models presented above givea simplemodel for its effects on a signal.In a sigma-delta converter, the original signal is maintainedwhile removing ad-ditional quantizationnoise by then digitally filtering theoversampled signal back to10.80.60.4- 0.20-0.2-0.4-0.6-0.8-1-- - ContinuousSi-- Quantized.-Error-..... ............. ...............i .......... ... ..........IIIN0 0.10.2 0.3 0.40.5 0.6 0.70.8 0.91Time [s]Figure 1-7:Quantized sinewave with n= 2 bits..The relationshipbetween theoversamplingratio K and theincreased effectiveresolution n' dueto removednoise spectra is[29]K = 22n'(1.6)Another stepthat can be includedbefore digitallyfilteringis noise shaping.Thisis the process ofshaping the quantizationnoiseso it lies abovethe passband ofthedigitaloutput filter.This is completedin the analogelectronics beforethe digitalfiltering. Fromthe simple, first-ordermodel shownin Figure 1-6,the bitwise streamis proportionalto the signal. Figure1-8 shows asimplified blockdiagram for theanalog sigma-deltamodulator adaptedfrom [30].The integrator isreplaced by atheoreticallyideal integrator withthe Laplace variables. In Figure 1-8,X is the inputsignal, Y is thesingle bit feedback, and Q is thequantization noise. By inspection,the blockdiagram is1Y = - (X -Y) + Q(1.7)S·· ·-·. ·r..... .... .............Figure 1-8: Block diagram of sigma-delta modulator, adaptedfrom [1].Solving for YgivesxsQY =+ (1.8)s+1 s+1By taking the frequency f limits, where s = 27rfi, the distribution of signal and noiseversus frequency is shown. As the frequency f -+ 0, the output Y approaches theinputsignal X and the quantizationnoise is not present. As the frequencyf - o00,the output Y approaches the quantization noise and the signal X is not present.Intuitively this is reasonable because the integrator acts as a low-pass average of theDC, non-zero input X and as a high-pass filter on the noise.Just as higher orders of integration increase attenuation, they also increase theirnoise shaping effect. Theadditional orders are obtained by adding another integratorand summation block asshown in Figure 1-9, adapted from [1, 31]. The noise is thenshaped as in Figure1-10. With these results, one would then intuitively increase theintegrator order until the noise is effectively eliminated in the band of interest. How-ever, the system would then become unstableassuming an infinite gain comparator.When assuming finite gaincomparators though, instability is not guaranteed. Byproperly monitoring the bitwise streamin the digital electronics, incipient instabilitycan be detected and prevented[30, 32, 33]. These details in which the converter canexhibit self-excited oscillations are another level ofcomplexity. Commercial ADCsare available with as high as fourth-order sigma-delta modulators.The digital filtering is not as simple as a low-pass filter shown in simplifiedde-scriptions. A finite impulseresponse (FIR) filter is digitally implemented and, as theIntegratorN-BitsFigure 1-9: Second-order sigma-delta modulation, adapted from [1].Figure 1-10: Sigma-delta modulation noise distribution.ClockIntegrator0-20-40--60'U- -80-1i00-120-140.1 %fl0 500 1000 1500 2000 2500FREQUENCY (kHz)Figure 1-11: Sigma-delta FIR filter response [2].name implies, has a finite response to an impulse. As opposed to an infinite impulseresponse (IIR) filter, which has internal feedback and can potentially respond indef-initely to a transient, an Nth orderFIR filter has a response that is N + 1 sampleslong. This FIR filter can be described to have a flat passband with relatively sharpcutoff. A large portion of the group delay is due to the phase delay of the FIR filter[34]. For the ADC implemented in Chapter4, the FIR filter response is shown inFigure 1-11. The group delay could be decreased by using a smaller order filter.Finallythe output signal is decimated (downsampled). High sampling rates areused to minimize noise content; however after digital filtering these additional samplesprovide no more information on the original signal. Therefore decimation by a factorof M could be accomplished by passing every Mth result anddropping the rest.Conceivably these samples couldbe averaged together before passing on. Assumingthe noise is a Gaussian distributed random signal in the M interval,the resolutionwould be increased by an additional factor of1(1.9)45PASS-BAND RIPPLE = 0.05dB-0.1dB FREQUENCY = 1.004MHz-3dB FREQUENCY = 1.06MHz.STOPBAND = 1.25MHzI " 'It is important that the output data rate after decimation is at least twicethe signalbandwidth so that signal information is not lost.Due to the single bit architecture of the ADC, the output is inherently very linearand errors are within a small windowas opposed to the potential missing codesof other ADC techniques. Sigma-delta converters generally operate with thebestresolutions at the highest rates, and exhibit a correspondingly high SNR within thisperformance area. Theseconverters are capable of high data rates but are limited inreal-time control due to the propagationdelay.Hybrid A/D ConverterA multitude of possibilities exist forcombining different A/D converting technologiesin an effort to balance hardware, resolution, and conversion speed.One method is tohave multiple flash converters for different ranges of bits. These are sometimes referredto assubranging or half-flash ADCs. For a 16-bit example, the 8 most significant bits(MSB) can be flash converted and the digital word can be fed back througha D/Aconverter and subtracted from the original analog value. The 8 leastsignificant bits(LSB) are then flash converted and the bits are combined [35]. Another method wouldbe to use successiveapproximation on the MSB and flash conversion on the LSB.While requiring a number of comparators on the order with flash converter, asuccessive approximation convertercan be produced from a chain of 2" - 1 resistorsand analog switches to track the sample. Theseresistors and switches replace theDAC of a typical SAR converter and does not have the discontinuous errors typicallyseen in SAR converters.However, the conversion rate for a new sample depends onthe change in the sample voltage from the previous conversion.Another SAR converter configuration uses several stageswith multiple ADC mod-ules. This creates a pipelined design. This increases the resolution with modestadditional hardware,however it also introduces a pipeline latency delay.1.2.3 Digital-to-Analog Converting MethodsA digital-to-analog converter generates an analog output based on a digital wordinput. Typically the voltage output is created by summing voltages representing adigital bit. The voltage can be created with a resistor or capacitor network and byswitching either a reference voltage or current to the proper input terminals of thenetwork as a function of the digital input.The simplest method is a weighted-resistor network which uses a single, constantvoltage across a resistor network. A 3-bit converter is shown in Figure 1-12. Theresistor values increase to 2' for an n-bit converter. The tolerances required for thetwo extremes of resistor values limit the resolution. The voltage across these parallelresistors creates a current that is then dropped across a load resistor, thus generatingan output voltage.An improved design is a weighted R-2R resistornetwork. The currents associatedwith each digital bit are created across repeated stages of 2R and R resistors. Twoconfigurations of a 3-bit converter is shown in Figure 1-12. The first methodcreatesa voltage output and the second produces a current output, which can be convertedto a voltage across an output op-amp.The accuracy is dependent on the resistormatching as well as load resistance. The resistors in the first method act as currentdividers and the current sum is dropped across a load resistor to create the outputvoltage. Without this output resistor, acurrent output is possible. The output bufferstage is typically more advanced thana single resistor, but rather an op-amp to drivethe outputwhich is generally the slowest part of the converter. Some high-speed D/Aconverters use a current output with a high-speed external op-amp to drive a voltageoutput.Hybrid combinations are common for high-precisionconverters, particularly withseparate MSB and LSB stages. For example, the AD768converter from AnalogDevicesuses current sources for the MSB portion and an R-2R ladder for the LSBportion and thetwo outputs are summed together. Accuracy can be maintained bydesigning the circuit on a single monolithicIC and laser trimming components duringr-----------------------------------------1.- 12.1 -Sv -.... IL.1~Figure 1-12: D/A converter hardware architectures. 1 - Weighted-resistor network.2.1 - Voltage output R-2R resistornetwork. 2.2 - Current output R-2R resistornetwork. The output node can be terminated at a virtual ground of an op-amp toform a current-to-voltage converter. 3 - Segmentedimplementationtesting before final packaging. Essentially all D/Aconverters are a combination ofeither current or voltage sources with current/voltage steering or current/voltagedividers.D/A converter resolution can range from6 to 18 bits with a settling times from15 ns to 100 Is [27, 35]. The settling time is defined as the time it takes to settle tothe specified accuracy. The update rate can be much higherhowever, and is limitedby the rate at which digital logic can be clockedin the D/A and in the internaldigital switching components.A fast settling time is essential to maintaining high-resolution when high update rates are necessary. Faster update rates are possiblewith parallel digital inputs. This removes a serial to parallel register within the D/Aconverter as well as the need to clock in up to 16 bits, generallywith a maximumclocking frequency of 40 MHz. Theparallel inputs also add hardware and necessarylogiclines, increasing the cost, physical footprint, and required logic lines from thecontrolling circuit.High-speed,high-resolution D/Aconverters are specifiedwith their resolution,update rate, settling time, and input format. The specific internal D/Aconversionimplementation has little effect on additional specifications.This chapter has presented an overviewof the work completed in this thesis, aswell as a background on high-resolutiondigital systems. These system require anunderstandingof the computation/data manipulation platform and the analog in-terfaces,both input and output, to the digital system. These architecturesimpactsystemperformance. Chapter2 discusses high-resolutionanalog interfacesdesigned,built, and tested for a dSPACE digital system.The remainder of the thesis describesa high-resolution, high-speeddigital platform designed, built, and appliedto an ex-perimental plant.Chapter 2dSPACE InteroperableHigh-Resolution AnalogInterfaceThis chapter describes high-resolution hardware and software designed to operatewith a dSPACE control environment.The hardware consists of a customA/D PCB,D/A PCB, and connector breakout PCB. The software consists of embedded firmwareon the A/D PCB and interface software for the dSPACE system. The hardware andsoftware was designed by David Otten as a research scientist with the Precision Mo-tion Control Laboratory in cooperation with the SAMM stage design at the Universityof North Carolina in Charlotte [16]. The design is considered freely available to thepublic'. This chapter describes the overalldesign as well as characterization andimprovements made to the design.The high-resolutionA/D and D/A system utilize a slave DSP on the dSPACE1103 PPC controller board to transfer data. The custom PCBs are shown in Figure2-1. The system provides galvanic isolation betweendSPACE and the plant to disruptground loopeffects. A small footprint permits the input/output to be located nearthe signal source/sinkto increase signal fidelity. The A/D channel uses an on-boardDSP and a high-speed A/D converterfor oversampling and averaging to increasethe effective number of bits from 18 to 20 bits compared toa maximum of 16 bitswith dSPACE.The D/A channel uses a precision 16-bit converter as opposed to the1Available at dspace.mit.eduFigure 2-1: dSPACEhigh-resolution DAC (Left) andADC (Right) PCB.dSPACE14-bit converter.Up to 8 A/D and7 D/A channels arerun to a dSPACEinterfaceboard through digitalmodular cabling.The increased resolutiongainedby oversamplingand averagingintroduces additionalphase lag of0.8 samples and amagnitudedecrease asthe signal frequencyapproaches the Nyquistfrequency. Thesamplingfrequency islimited to 8kHz dueto the slave DSP communication processes.2.1 SystemDescriptionand DesignThe dSPACE1103 PPC controllerboard (DS1103)uses a PowerPC604e runningat 400 MHzwith a slave TexasInstruments DSPrunning at 20 MHz.The DS1103supplies16-bit multiplexed ADCswith+10V rangeand 80 dB signal-to-noiseratio(SNR),as well as eight 14-bitDACs with +10V range. The high-resolutionPCBsinterfacewith the slaveDSP to take advantageof its processingpower, allowingtimeconsuming arithmeticto be completedby the DS1103 asopposed to on-boardthe slowerand less preciseA/D DSP. A serialinterface is usedto facilitate galvanicisolation with high-speeddigitalisolators. This isolatesthe plant electronicsfromthedSPACE systemin an effort to eliminateground loopsas well as allowingtheinput/outputboards to be poweredwith the samepower source asthe plant. Signalfidelity can bemaintained by locatingthe PCB boardsnear the signal source/sinkand then digitally interfacing the boards to a central dSPACE interface board.Oversampling and averaging improves the resolution of a signalthat is corruptedby white noise. In our implementation at most 100 samples can be averaged per cyclewith the A/D converter operating at 800 kSPS and the slave DSP at 8 kHz. The noiseis assumed to have a Gaussian distribution, and thus a sum of N equally weightedsamples divided by N reduces the standard deviation by .Therefore the expectedVrN*improvement isa factor of 10, or 3.3 effective bits. This also introduces an additionalTADSAMPL'time delay, where TADSAMPLE =1.25ps,into the feedback loop. The2frequency response of the averaging fitler to an impulse over the sampling period isgiven by [36]M1H(ejL )2M+1Ze-wk(2.1)k=-Mwhere M = .The magnitude of thisfrequency response is shown in Figure 2-2. Thewidth of the first lobe is ý, or approximately 50.3kHzfor 800 kSPS. The magnitudedecrease at higher frequencies is intuitively understoodby realizing the sample doesnot represent the precisesignal at that instant; rather it represents an average of thesignal since the last acquisition. At low frequencies there are many samples taken foreach sine wave so the magnitude decrease at the peaksis negligible, but at higherfrequencies where the signal is representedby only several samples, peaks becomeroundedoff showing a noticeable magnitude decrease. The discrete z-domaintransferfunction is1 + z-1 +...+ z- 98+ z- 99z99+ Z9+ ...+ z1 +1H (z)=10010z99(2.2)100 100z99where z is the z-transformation variable. Thisdigital filter is a boxcar finite impulseresponse (FIR) filter. Equation2.2 does not imply decimation however. Decimationcan be a distinctly separate process of taking every Nthpoint. By combining theboxcar filterwith the decimation, the full sample data can be utilizedfor higherresolution at a slower,decimated data rate. The boxcar filter and decimationisdiscussed further in Section 5.1.(Dma5o (radi anssam pie)a,2''EpraI'Frequency (Hz)Figure 2-2:Magnitude frequency response of averaging filter for N = 100 at 800kSPS,before decimation.The high-resolution A/D PCBdesigned by David Otten is built around a com-mercial, high-speed 18-bit A/D converter IC (AD7674) fromAnalog Devices which iscoupledwith a 16-bit fixed-point digital signal processor (DSP) IC (TMS320LF2604)commercially available fromTexas Instruments. The A/D converter operates at 800ksamples per second (SPS) while the DSP sumsthe samples and formats the data forserial transmission to the dSPACE slave DSP. The average is not calculatedon theDSP becausethe fixed-point precision limits accuracy.The A/D converter is providedwith a fully differential input front-end that canaccept up to +10 V signals. Thecircuit is built on a small printed circuit board(2.5" x 2.6") and located in an aluminum case thatcan be matched to any availableelectrical common. An 8-pinmodular connector is used for the high-speed digitalsignalsbetween the analog input board and dSPACE. The design uses readily availableethernet cables for cabling because their twisted pair construction andcontrolledimpedance is favorable and they are available pre-terminatedin a variety of lengths.Asa companion to the high-resolution A/D, a high-resolution D/A was also de-signed and built by David Otten. A 16-bit low glitch voltage outputD/A from LinearTechnology(LTC1650) is used. The circuit is also built on a small printed circuitboard that can be locatedclose to the destination of the signal and utilizes an isolatedinterface to the DS1103 to eliminate ground loop problems. The data for the D/A isserially shifted out of the DS1103 slave DSP at the same time the A/D data is shiftedin. This overlap efficientlyminimizes serial clock signals for transmitting data to andfrom the DS1103.The D/A IC itself only outputs a ±4.5 Vsignal. The output of the PCB is drivenwith a non-inverting op-amp configuration to scale the voltage to ±10 V. The resistorratio isR2 110kk = 1 + = 1 +10k=2.210(2.3)R, 90.9kwhere R1is between the inverting terminal and ground and R2is in the feedbackpath. Because the gain factor k is not exactly 2.222, the output range is limitedto +9.946 V. Hence a scale factor is included in the slave DSP to account for thisdifference. The results incorporate this scale factor, however it is essential to checkthis factor for any new setup as resistor tolerance or referenceaccuracies can varybetween PCBs.The relevant internalcomponents of the DS1103 relating to the high-resohlutionsystem areoutlined in Figure 2-3. The digital I/O are used to clock and transmitdata through the interface PCB to all channels. The DS1103 slave DSP reads from/tothe 32-bit I/O bus and the master processing unit performs the complex data ma-nipulation. Along with the high-resolution boards,2 interfaces for Zygo ZMI 4004interferometer boards are includedin David Otten's design, allowing up to 8 measure-ment channels. Thisadditional design implementation is not described herein but isdocumented in the availableresources [4, 16].Only 7 output D/A channels are available becausethe output data port onlyprovides 7 bits. The software and DS1103 board itself uses thefull 8 bits of the portbut the DS1103cabling and breakout box only brings out 7 bits. It is possible to useanother port however the data transferon the additional port limits the closed-loopsample rate to approximately 6 kHz as opposed to8 kHz. Cabling is provided for thisi-"Figure 2-3: dSPACEdata flow with high-resolution platform,adapted from [3].extra channel on thePCB interface board, and the two sets of compiledsoftware filesare available for the instancewhen all 8 D/A channels are required,albeit at a slowersampling rate.Initially only 6 channels were operationalbut during characterizationthe breakoutconnector PCB was rerouted for the 7th channel.The softwareinterface is implemented with threeprograms: a custom writtenSimulink S-Function, a set of user-definedfunctions for the slave DSP onthe DS1103PPCcontroller, and a custom firmwareprogram to control the A/D DSP.This DSPrequiresa one-time program write withspecific program emulation hardwarefromTI. A user-definedMatlab Simulink modelis generated for each specificapplicationwhere the S-Functionprovides a user interfacewith 8 inputs and 7 outputsin theSimulink environment.The S-Functiongenerates a communication pathbetween the DS1103 masterandslaveDSP. This includes dataformatting, scaling, sorting,and interfacing to the 16-bit communicationbuffer. The slave DSPinterfaces with the communicationbufferand then reformats the data from 16-bit words back into 32-bit words. One bit issent to each D/A channel and one bit is received from each A/D channel on eachclock pulse. The D/A channels require 16 bits for an output, and the A/D channelsrequire 32 bits to be acquired. Of the 32 bits there are 25 bits ofdata and 7 bitsrepresentingthe number of samples taken. For each instance where data is requestedby the slave DSP from the A/D DSP, 32 bits are transferred to the A/D DSP serialoutput buffer and a new sum is started. This allowsas many A/D samples N perperiod as possible.The sampling rateof dSPACE is limited by the time it takes to transfer andprocess data between the components of Figure 2-3. Table 2.1 details the functionswithin one Simulink time step. The majority of time is spent by the slave DSPtransferring and clocking data, as shown with Figure 2-4. This process isstraightline coded in assembly languageto minimize the delay time. The complete step timesubsequently limits the dSPACE sampling rate to 8 kHz. The relative time at whicheach channel is latched to the input or output is shown over 2 time samplesin Figure2-5. The dSPACE channels are represented withDS and the custom high-resolutionchannels are represented by HR. The timescale is given in ps.2.2 System Characterization and ResultsAll digital systemscreate a phase delay, or time lag, due to the processingand trans-port ofdigital signals. This requires at least one time step, as ittakes time for thedata to transfer from the Simulink model to the D/A convertersand then time forthe A/D converters to sample the data andsend it back to the Simulink model. Fig-ure 2-6 shows varioustime delays for different combinations of dSPACE(DS) andhigh-resolution (HR) systems.There is a single time sample delay from the DSD/Aoutput to the DS A/D input relative toan internally generated sine wave. The HRD/A to the DS A/D is not shown here, since it has the samephase lag because bothD/A channels are outputtedbefore the subsequent DS A/D reading. Thiswas alsoshown in Figure 2-5. The DS D/Ato HR A/D has a larger phase lag due totheA/D - Master DSPDIA - Master D SPFigure 2-4: dSPACE subsystemtiming [4].Time Sample 0L- Time Sample 1Figure2-5: dSPACE and high-resolution latchingtimeline at 8 kHz sampling.ThedSPACE channels are representedby DS and the high-resolution arerepresented byHR. The time scale is microseconds.8%Table 2.1: dSPACE Subsystem TimingMaster DSP - mdlUpdate FunctionFlush communication bufferAcquire D/A data from model and scaleSort channelsReformat dataOutput D/A data to comm. bufferSlave DSPAcquireD/A data from comm. bufferClock data to/from analoghardwareOutput A/D data to comm. bufferMaster DSP - mdlOutput FunctionAcquire A/D data from comm. bufferReformat dataSort ChannelsScale A/D data and output to modelComplete Cycle Time:Time [ps]0.960.680.131.311.7914.9448.2535.354.072.920.132.42112.95Total [ps]4.8798.549.54averaging from the previous time sample. The HR D/A to HR A/D delay is over 2time samples because for a given sample output, as shown in Figure 2-5, the A/Dinput is latched in before the output is latched out. This is in addition to the A/Daveraging over the preceding time sample.Thesedelays can also be viewed in the frequency domain. Figure 2-7 shows thefrequency responses of the four possible system combinations. The top magnitude