This paper describes a high-speed CMOS demultiplexer using redundant multi-valued logic (RMVL). The proposed circuit receives serial binary data and is converted to parallel redundant multi-valued data using RMVL. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the RMVL makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. Each integrator is composed of an accumulator, a window comparator, a decoder and a D flip flop. The demultiplexer is designed with TSMC standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation. The demultiplexer is achieved the maximum data rate of 20 Gb/s and the average power consumption of 95.85 mW.

In this research we present a novel method which combines and visualizes the design model and the FDM-based simulation result of solidification. Moreover we employ VR displays and visualize stereoscopic images to provide an effective analysis environment. First we reconstruct the solidification simulation result to a rectangular mesh model using a conventional simulation software. Then each point color of the reconstructed model represents a temperature value of its position. Next we map the two models by finding the nearest point of the reconstructed model for each point of the design model and then assign the point color of the design model as that of the reconstructed model. Before this mapping we apply mesh subdivision because the design model is composed of minimum number of points and that makes the point distribution of the design model not uniform compared with the reconstructed model. In this process the original shape is preserved in the manner that points are added to the mesh edge which length is longer than a predefined threshold value. The implemented system visualizes the solidification simulation data on the design model, which allows the user to understand the object geometry precisely. The immersive and realistic working environment constructed with use of VR display can support the user to discover the defect occurrence faster and more effectively.

A middleware in grid computing environment is required to support seamless on-demand services over diverse resource situations in order to meet various user requirements [1]. Since grid computing applications need situation-aware middleware services in this environment. In this paper, we propose a semantic middleware architecture to support dynamic software component reconfiguration based fault and service ontology to provide fault-tolerance in a grid computing environment. Our middleware includes autonomic management to detect faults, analyze causes of them, and plan semantically meaningful strategies to recover from the failure using pre-defined fault and service ontology trees. We implemented a referenced prototype, Web-service based Application Execution Environment(Wapee), as a proof-of-concept, and showed the efficiency in runtime recovery.

RFID technology has been gradually expanding its application. One of the important performance issues in RFID systems is to resolve the collision among multi-tags identification on restricted area. We consider a new anti-collision scheme based on Class Identification algorithm using Depth-First scheme. We evaluate how much performance can be improved by Class identification algorithm in the cases of Query-tree more then 17% identification rate and 150% performance.

In this paper, an efficient digit-serial systolic array is proposed for multiplication in finite field GF() using the polynomial basis representation. The proposed systolic array is based on the most significant digit first (MSD-first) multiplication algorithm and produces multiplication results at a rate of one every "m/D" clock cycles, where D is the selected digit size. Since the inner structure of the proposed multiplier is tree-type, critical path increases logarithmically proportional to D. Therefore, the computation delay of the proposed architecture is significantly less than previously proposed digit-serial systolic multipliers whose critical path increases proportional to D. Furthermore, since the new architecture has the features of a high regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementation.

Consolidating servers into a virtualized system increases entire system utilization, while suffers from performance degradation due to the additional virtualization layer. In this paper, we proposed a performance evaluation methodology for comparing virtualized systems with native non-virtualized systems. We defined a system waste rate per consolidated throughput as a metric, and described the method for calculating system waste rate and consolidated throughput for both of virtualized systems and non-virtualized systems. Using the proposing performance evaluation methodology, we established testbeds, evaluated their performance, and compared the metrics of both systems. As a result of the evaluation, we could show the appropriateness of our methodology and analyze the effect of the application characteristics.

Nowadays, most web sites are developed using dynamic web pages where web pages are generated and transmitted by web application programs. Therefore, the ratio of attacks injecting malevolent strings to vulnerable web applications is increasing. In this paper, we present a static program analyzer which analyzes whether a web application program has vulnerabilities to the SQL injection attack and the cross site scripting(XSS) attack. To analyze programs using abstract interpretation framework, we designed an abstract domain which models potential string set along with excluded strings and developed an abstract interpreter for the PHP language. Also, based on them, we implemented a static analyzer. According to our experiments, our analyzer has competitive analysis speed and accuracy compared with related research results.