Performance Modeling of Cache Memories for Manycore Processors

In many-core processor system, processes on each core compete for the shared resource such as shared Last Level Cache(Shared LLC). In this case, degradation of total system throughput could occur from unfair shared resource allocation. Our research goal is accurately and quickly estimating the resource requirement from stochastic modeling of process memory access behavior and improving the total throughput by providing QoS for each process.