Designing Efficient Deep Learning Systems

Deep learning is widely used for many artificial intelligence (AI) applications including computer vision, speech recognition, robotics, etc. While deep learning delivers state-of-the-art accuracy on many AI tasks, it comes at the cost of high computational complexity. Accordingly, designing efficient hardware systems to support deep learning is an important step towards enabling its wide deployment, particularly for embedded applications such as mobile, Internet of Things (IOT), and drones.

This course aims to provide a comprehensive tutorial and survey about the recent advances towards enabling the efficient processing of deep learning. Specifically, it will provide an overview of deep learning, discuss various hardware platforms and architectures that support deep learning, and highlight key trends in recent efficient processing techniques that reduce the cost of computation for deep learning either solely via hardware design changes or via joint hardware design and network algorithm changes. It will also summarize various development resources that can enable researchers and practitioners to quickly get started on deep learning design, and highlight important benchmarking metrics and design considerations that should be used for evaluating the rapidly growing number of deep learning hardware designs, optionally including algorithmic co-design, being proposed in academia and industry.

Who Should Attend:

This course is designed for research scientists, engineers, developers, project managers, startups and investors/venture capitalists who work with or develop artificial intelligence for hardware and systems, as well as mobile or embedded applications:

For project managers and investors/venture capitalists whose work involves assessing the viability or potential impact of a deep learning system and selecting a research direction or acquisition, this course aims to provide an overview of the recent trends as well as methods to assess the technical benefits and drawbacks of each approach or solution based on a comprehensive set of metrics.

For research scientists and engineers whose work involves designing and building deep learning systems, this course aims to provide an overview of the various state-of-the-art techniques that are being used to address the challenges of building efficient deep learning systems.

For startups and developers whose work involves developing deep learning algorithms and solutions for embedded applications and systems, this course aims to provide the insights necessary to select the best platform for your goals and needs. It will also highlight techniques that can be applied at the algorithm level to improve the energy-efficiency and speed of your proposed solution.

Course Schedule:

Day

Schedule

Day 1: 9:30am – 5:30pm

AM:

Introduction to Deep Learning

Deep Learning Applications

Development Resources for Deep Learning

PM:

Deep Learning on Programmable Platforms

Deep Learning on Specialized Hardware

Day 2: 9:30am – 5:30pm

AM:

Co-optimization of Algorithms and Hardware for Deep Learning

Application of Advanced Technologies to Deep Learning Systems

PM:

Training with Deep Learning

Metrics for evaluating Deep Learning Systems

Discussion on trends in Deep Learning

Reception (4:00pm – 5:30pm)

Instructors:

Vivienne Sze joined the EECS Department as an Assistant Professor in August 2013. She received the B.A.Sc. degree in Electrical Engineering from the University of Toronto in 2004, and the S.M. and Ph.D. degree in Electrical Engineering and Computer Science from MIT in 2006 and 2010, respectively. From September 2010 to July 2013, she was a Member of the Technical Staff in the Systems and Applications R&D Center at Texas Instruments. Prof. Sze’s research focuses on joint design of algorithms, architectures and circuits to build energy efficient and high performance systems. Her work on implementation-friendly video compression algorithms was used in the development of the latest video coding standard HEVC/H.265, enabling it to deliver better compression than previous standards, while still achieving high processing speeds and low hardware cost. She aims to develop energy-aware algorithms and efficient architectures for various energy-constrained applications including portable multimedia, health monitoring and distributed sensing.

She has received various awards including the Jin-Au Kong Outstanding Doctoral Thesis Prize in 2011, the 2007 DAC/ISSCC Student Design Contest Award, the 2008 A-SSCC Outstanding Design Award, the Natural Sciences and Engineering Research Council of Canada (NSERC) Julie Payette fellowship in 2004, the NSERC Postgraduate Scholarships in 2005 and 2007, and the Texas Instruments Graduate Woman’s Fellowship for Leadership in Microelectronics in 2008. In 2012, she was selected by IEEE-USA as one of the “New Faces of Engineering."