MATRICuS Inc.

The pages of this section will draw a sketch of the IC design company and its character. With broad strokes, it will give the history of both matricus inc. and the matricus group, introduce the work it carries out, and the individuals involved. Here you will discover basic facts that will help you understand what makes those of us that work in IC design at matricus tick, why we have been in business for so many years, and how we can work together with you on a program which will become as important to us as it is to you.

The LAYTOOLS Place and Route package may be used as a stand-alone tool or as an integrated component of the LAYTOOLS suite. Although initially targeted at medium-sized designs (100,000 gates) for mixed-signal application, it does integrate advanced algorithms which allow it to handle large numbers of cells and macros in an efficient manner without manual intervention

LAYVER is a sophisticated and comprehensive layout verification package that provides a complete set of tools to validate IC designs of any size and complexity. It offers database layer operations, spacing, intersection, extension, and sizing checks, as well as circuit extraction, and net-list comparison all under the same umbrella.

As silicon geometries shrink, device models become more complex and the number of elements that must be included in any simulation increase. A respectable simulator must accommodate such advances as well as provide the features and options to allow effective circuit development to be completed. Smash is that simulator.

SPE (Schematic Probe Environment) is a flexible and powerful full-function multi-level schematic capture environment developed particularly to enable IC circuit design engineers to enter schematics accurately, clearly and quickly. In addition it provides the ability to cross-probe between schematic and layout views using the network extracted.