Cadence, Northrop Grumman team on space ASICs

Cadence Design Systems and aerospace giant Northrop Grumman Corp. have jointly developed a design library that can be used to build the next generation of ASICs for military and space applications.

The result of the collaboration is a "radiation-hardened by design" SOI based on a standard cell and IP library that targets military and space applications, Northrop Grumman (Redondo Beach, Calif.) said Aug. 3.

The 90-nm rad-hard ASIC was designed to provide higher levels of integration, lower power performance and faster speeds, Stuart Linsky, vice president of satellite communications at Northrop Grumman’s Aerospace Systems unit, said in a statement. "This cell library enables users to design very large radiation-hardened ASICs in a low-power, high-performance semiconductor process for space applications,” Linsky added.

The library includes an array of 1V standard cell gates, a serializer/deserializer, phase-locked loop, SRAM compiler along with 1.8V and 2.5V input/output buffers.

After Cadence (San Jose, Calif.) and Northrop Grumman developed the cell library, multiple test chips were fabricated at Freescale Semiconductor’s commercial SOI foundry in Austin, Texas. Among them was a 5 million-gate ASIC. All were tested to validate the use of the cell library for space applications.

Radiation hardening allows devices used in space to resist damage from ionizing or particle radiation along with high-energy electromagnetic radiation.

"All were tested to validate the use of the cell library for space applications." Well, that's nice, but where's the beef? What SEU levels can the part withstand? More significantly, does this combination allow any Total Dose hardness? To what level? This is a nice press release, but there's no significant detail here.

Great news for Space Industries, this way it will be possible to reduce the board area and space will be avaliable to host a few more functionalities on the payload.
Now there is a strong need space grade FPGAs.