In the literature the influence of the conducting layer, sometimes called a floating gate, upon d.c.-MISFET characteristics is ignored or only treated in a phenomenological way. Our intentions in this paper are to present a study of the consequences of a conducting layer in an exact way by using the MISFET theory described earlier.

It is found that the d.c.-characteristics are influenced by parasitic capacitances from the conducting layer to source and drain and the charge-voltage relations along the channel of the MIS transistor.

The theoretical considerations are verified by simulations with Spice 2 and some experimental results and are in agreement with the characteristics already given in the literature referred to.