Firstly, make sure you meet the following requirements:
1. The unit under debug must have at least 1 USB 3 port out from Intel silicon.
2. The unit under debug must be configured in "Merge Debug Port Topology" that described in Skylake platform design guide under "platform debug and test hooks" chapter to enable both CPU and PCH debug. Without this topology routed on the board, DCI only has access to PCI which is not sufficient for platform level debug.
3. The unit under debug must enable DCI option in the BIOS setup menu in order for DCI to work properly. The DCI setting is available in BIOS RC.