Real-time sound rendering applications are memory-intensive and computation-intensive. To speed up computation and extend the simulated area, a real-time sound rendering system based on the hardware-oriented finite difference time domain algorithm (HO-FDTD) and time-sharing architecture is proposed and implemented by the field programmable gate array (FPGA) in this study. Compared with the traditional rendering system with parallel architecture, the proposed system extends by about 37 times in the simulated area because data are stored in the on-chip block memories instead of the D flip-flops. The hardware system becomes stable after 400 time steps in the impulse response. To render a three-minute Beethoven classical music clip, the hardware system carries it out in real-time while the software simulation takes about 63 min in a computer with 4 GB RAM and an AMD Phenom 9500 Quad-core processor running on 2.2 GHz.

Rights:

This is the author's version of the work. It is posted here by permission of The Japan Society of Applied Physics. Copyright (C) 2014 The Japan Society of Applied Physics. Tan Yiyu, Yasushi Inoguchi, Yukinori Sato, Makoto Otani, Yukio Iwaya, Hiroshi Matsuoka and Takao Tsuchiya, Japanese Journal of Applied Physics, 53(7s), 2014, 07KC14-1-07KC14-8. http://dx.doi.org/10.7567/JJAP.53.07KC14