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Inverter Chain Test Structure

Publishing Venue

IBM

Related People

Berger, HH: AUTHOR

Abstract

For test purposes, representative basic circuits of a monolithic (digital) design are connected in the form of inverter chains (e.g., through special masks). If one of these basic circuits of the chain fails, the whole chain fails (no or incorrect signal transmission), so that individual defects can be detected, localized (by scanning) and analyzed in a very large number of basic circuits. This principle is used for an MTL/I2L (Merged Transistor Logic) memory. The single cell of such a memory consists of two cross-coupled MTL inverters. Fig. A shows the equivalent circuit diagram of the MTL cell structure with the two inverters T1, T2 and T1', T2'. The injectors T1, T1' of the inverters are connected to a bit line pair BL0, BL1. The common emitters of T2, T2' are connected to the word line WLn.

Country

United States

Language

English (United States)

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Inverter Chain Test Structure

For test purposes, representative basic circuits of a monolithic (digital) design
are connected in the form of inverter chains (e.g., through special masks). If one
of these basic circuits of the chain fails, the whole chain fails (no or incorrect
signal transmission), so that individual defects can be detected, localized (by
scanning) and analyzed in a very large number of basic circuits. This principle is
used for an MTL/I2L (Merged Transistor Logic) memory. The single cell of such
a memory consists of two cross-coupled MTL inverters. Fig. A shows the
equivalent circuit diagram of the MTL cell structure with the two inverters T1, T2
and T1', T2'. The injectors T1, T1' of the inverters are connected to a bit line pair
BL0, BL1. The common emitters of T2, T2' are connected to the word line WLn.
In a (2k x 10) byte-organized chip with a parity bit and a redundant bit, the array
is subdivided into 10 sections with 128 words of 16 bits each. For four transistors
per cell, there are altogether 82,000 transistors in the array, of which even a
single defective one can be detected. According to an organization of 10 array
sections, 10 inverter chains are wired with 4096 inverters each, using the original
memory chip background. Thus, the actual array yield is 9 or 10 good sections (1
bit redundancy!). Only minor changes are required for reconnecting the memory
cell devices in the form of an inverter chain (Fig. B), so that any relevant defe...