It is not as simple @goafrit...smaller Vgs produces smaller Id current and the power goes down...but the device speed goes down too so now you need more time to complete the same task...it is not obvious at what Vgs or Vdd the energy will be minimized...fairly complex analysis is required...Kris

>> It is well proven in the literature that operating in sub-threshold minmizes power dissipation in digitla VLSI ckts

I am not aware you can bias digital circuits in sub-threhold. I know when they do sub-t, it is always in analog portion of circuits. Digital always needs to exceed Vmid and that is way ahead of the Vt (threshold voltage) which you must stay below in sub-threshold design

It is well proven in the literature that operating in sub-threshold minmizes power dissipation in digitla VLSI ckts...the optimum VDD is about 0.3V-0.6V...it is very interesting to see whether these academic studies extent to a real world of high complexity processor...hence my interests...Kris

What is the unique thing about sub-thresold work in the IoT? When you work in the weak inversion, you do not get great signals. In the analog domain, there are few opportunities as you can have exponential gain but your signal degrades. What is the magic here at sub-threshold that we need to know for ARM which is a digital/uP company?