Comments

U-boot needs a host controller or "hose" to interact with the PCI busses
behind them. This change installs a host controller during initialization
of the coreboot "board" which implements some of X86's basic PCI semantics.
This relies on some existing generic code, but also duplicates a little bit
of code from the sc520 implementation. Ideally we'd eliminate that
duplication at some point.
It looks like in order to scan buses beyond bus 0, we'll need to tell
u-boot's generic PCI configuration code what to do if it encounters a
bridge, specifically to scan the bus on the other side of it.
A hook is installed to configure PCI bus bridges as they encountered by
u-boot. The hook extracts the secondary bus number from the bridge's config
space and then recursively scans that bus.
Signed-off-by: Gabe Black <gabeblack@chromium.org>
---
board/chromebook-x86/coreboot/coreboot_pci.c | 33 ++++++++++++++++++++++++++
1 files changed, 33 insertions(+), 0 deletions(-)