Meta

Archive for January, 2011

Piyush Sancheti of Atrenta brings up a good point: for Ip to work as we envision it can, what players have to contribute to the quality effort? And what does each player type need to contribute? http://bit.ly/gpAHI1

I recently had a chance to talk with EDA veteran Jim Girand about what the Japanese market looked like for EDA and IP companies, especially startups. Jim has been in EDA since its inception. He’s been a sales executive with various EDA firms including SDA and Cadence, an angel investor, and continues to set up sales distribution channels in Japan for startups and mid-sized companies.

Ed: Jim, let me throw out an observation that may be totally off base. I say that a lot of the startups in our area bypass the Japanese market, preferring to get into the Chinese (mainland but also Taiwan) and Indian market first.

Jim: Well, Ed, I’m going to disagree with you there. It seems to me that there is a lot of potential upside to pursuing the Japanese market. The large electronic product companies do demand a lot from their design tool vendors but they also reward their vendors with loyalty and purchase orders. Of course the other Asian markets are potentially lucrative and will surely grab a larger percentage of the Asian TAM (total available market) over time. But the structure of Japanese sales has changed. It seems to me that there is a lot of potential upside to pursuing the Japanese market and Japan still has the largest EDA market overall among the Asia Pacific countries. The latest EDAC numbers show for Q3 2010, Japan alone was 18% of worldwide sales and all the rest of Asia Pacific combined excluding Japan was 21%.

Ed: Interesting. The distributors I knew of all seem to be gone except for Marubeni, Innotech and some smaller organizations. So let me ask: How has the Japan distribution channel structure changed in the past twenty years?Jim: Well, let me set context first. A historical perspective may illuminate why the Japan distribution channel has evolved to its current structure.
Traditionally, there were two choices; a full service trading organization that bought and resold EDA products or establishing a ‘K.K.’, a separate corporate entity staffed with local people dedicated to the supplier.

Ed: What’s the role of a trading organization?

Jim: So, the trading organization –– or distributor –– bought the EDA tools at a discount, marked up and resold them with a sizable margin. The margin covered currency translation, local sales and applications support, cost of collection and other costs such as marketing and administration. Often, the trading company would make a ‘pre-purchase’ to encourage the supplier to give good support to Japan and designate a part time applications engineer who would be trained to conduct demonstrations and evaluations. Further, these trading entities often had excellent reputations and high level relationships that helped the small EDA company get an introduction at the large customers. As the supplier matured and grew, he had a choice of getting the trading company to invest in more infrastructure or start a K.K, that could assume all or share sales and support responsibility.

Ed: I do remember that the distributors like SC Hytech and that group of smaller firms had great reputations for service and support.

Jim: So over time, users pushed harder for prices that were comparable to those in the U.S. They began to implicitly – if not explicitly – separate the services offered and assume responsibility for some or just do without. Sophisticated IDMs and systems companies concluded they could buy in U.S. dollars, and get early technical support from the headquarters, especially with advancing information technology that made it possible. In this high pressure environment that squeezed margins, some full service trading companies left the business and at the same time smaller, more flexible organizations and entrepreneurs took their place. Also, organizations such as those offering design services and local design automation tools added small U.S. suppliers to their suite of products.

Simply stated, competitive pressure starting from the end users has driven the Japan distribution channel, today, to be heterogeneous and have a wide variety of selling organizations. Also, not to be forgotten, EDA suppliers are designing their products so mere mortal circuit designers can use them – quickly. And technical support is oriented more toward the most sophisticated applications.

The end result of this evolution in the Japan distribution channel is all good. The end users will always demand and get superior EDA tools and support. Full service trading companies will have to demonstrate their infrastructure, long term high level relationships, local technical support and administration are efficient, a better local value than the end user getting these services piece meal.

Ed: And what of the sales rep?

Jim: Likewise, the independent sales representative must bring a persuasive contribution through the services he offers, beyond a good price, that will cause the end user to exert the extra effort to buy from him. And, going forward, we can be sure of one fact. The pressure on margins, the cost of sales, will only get stronger and felt from the local representative to deep into the supplier, driving all parties to be more efficient.

Ed: So what’s the effect of these changes for the small EDA vendor?

Jim: Now, from the perspective of the small EDA supplier seeking a distribution partner in Japan these changes in the channel structure can have profound effects. Namely, with a traditional trading company the sales development resources are ‘in country.’ You should have a designated sales manager who is responsible for the local infrastructure and getting your products introduced to the ‘A’ level end users. You will need to establish quotas, sales plans and be responsive when more advanced resources are requested.

At the other end of the spectrum, an individual sales representative will need much more guidance and particularly, technical support to help establish and successfully conduct evaluations. The supplier should plan on traveling to Japan often, perhaps once/quarter, make joint sales calls, conduct seminars and establish a corporate as well as technological identity with the end users. A much more active sales management role by the supplier is required here. At this time, there is no evidence whether the traditional trading company model is more effective than smaller organizations. More important, the supplier should think about the above considerations and choose an organization that will be compatible with his emerging culture.

Ed: Interesting, Jim. So there is no one formula on how to decide which works best for each type of company?

Jim: Not really. It depends on the considerations I mentioned earlier, plus the rapport established during the interview process, convergence of each organization’s interests, complementary product lines and existing relationships with prospective end users.

Ed: For those reader with questions, can they get hold of you?

Jim: Sure! I’d welcome their questions.

Ed: Jim, thanks for taking time to update us all on what’s going on in the Japanese distribution side of the EDA business.
…………………………………… Note: Jim Girand can be reached at jim@girand.com, website: www.girand.com.

Ron Craig, Senior Marketing Manager at Atrenta and an expert on the subject of timing constraints, was good enough to sit down with me (Liz Massingill) recently to talk about the subject—what the current problems are and how to fix them.This is the result of my interview with Ron.

Liz: Ron, I was shocked to see, in the survey you conducted, that 94% of designers have timing constraint problems that could stop their current designs dead in their tracks. But they also don’t see a way to change their current methodology. WHY?!?!?!?! Ron: There’s certainly no doubt that timing constraints remain and will continue to be a problem for design teams. The irony is that even though timing constraints are repeatedly an issue, most of these design teams feel that they know how to address all the problems that typically arise. It’s almost that the problems are viewed as less severe if the solutions are known.

Liz: Seems like the problem is more about changing the mindset.But why are designers running into increasing clock domain issues in the first place?Use of more IP? Process nodes going down to the next level? More complex designs?

Ron: The key culprit here seems to be IP. With IP, the functionality is reusable but the timing constraints are often not. Third party IP developers may well be experts in what the IP is supposed to do but not necessarily its implementation, leaving design teams with incomplete and inadequate timing constraints. On the other hand, IP reused from another design may well have been constrained in a way that’s not compatible with how you want to use it in your chip – especially if you need to change how the IP behaves. In today’s designs where IP amounts to 70% or more of a typical SoC, you end up with the constraint-driven implementation process becoming increasingly risky.

The process shrinks and more complex designs mean you simply can’t get away with having inadequate timing constraints anymore.

Liz: Well, what can they, ­or more appropriately, their project managers or internal CAD departments do about this increasing problem?

Ron: The key is to introduce more certainty into the whole process. Rather than taking an optimistic, or reactive approach to timing constraints, it makes a great deal of sense to put some effort in up-front to make sure that they are good. Many of our customers have noted that they simply can’t deal with the number of iterations it takes to refine timing constraints during the implementation phase of their projects, so they’re working on finalizing them up front as part of their RTL handoff. The trick for project managers or CAD people will be to introduce a methodology that their front end teams (who aren’t necessarily timing constraint experts) can easily adopt, and this is where comprehensive automated solutions such as SpyGlass-Constraints come into play.

Liz: So why isn’t this happening?Seems to me that an ounce of prevention is worth a pound of cure, as they say.

Ron: Let’s look at the two camps. First of all you have the RTL or front end team, who historically don’t want to take ownership of any part of the implementation process (even they know the design well enough to define its constraints). On the other side of that handoff ‘wall’ you have the back end team who feel that their expertise in this area, coupled with whatever the implementation and timing tools complain about, is enough of a solution. So depending on which side of that wall you sit on, you may feel that it’s either not your problem….or not a problem at all.

Liz: But we know there IS a problem, and it’ll only increase.So where in the design flow should project managers look first for a fix?

Ron: There is often a perception that timing constraints can’t be fully defined until you are actually using them – until you are in the thick of implementation or timing analysis. The problem with this is that your constraints end up being written so that you can close timing, instead of being defined to set the ground rules for timing closure. A classic example of this is the definition of timing exceptions – they’re often defined to mask timing violations, but in most cases they’re not exhaustively verified. A timing exception is a design characteristic, so can be defined and proven up-front before the implementation process even starts. It’s like an architect finalizing the plans after the building is complete. If your objectives aren’t clear how do you know when you are done?

Liz: I see what you are saying—it’s like putting the cart before the horse.Stop me, Ron, if I use another one of these old sayings.I’m dating myself. So who’s out there with technology that can help change the methodology and fix the timing disaster that’s looming?

Ron: It’s been possible to do some rudimentary timing constraint analysis in a range of implementation and STA tools since the advent of timing driven optimization. The problem with this approach, however, is that it’s largely a reactive one, and as a result doesn’t help reduce the risks in your implementation process. More recently, vendors (often ones outside the implementation/STA space) have started to provide solutions that allow the user to check the correctness of their constraints before implementation. What we’ve done with SpyGlass-Constraints is to take it one step further and look how timing constraint analysis is part of the bigger picture of reducing implementation risk. A great example of this is how we use our constraint verification methodology to ensure that data such as clock setup is in good shape before you use it to drive clock domain crossing (CDC) analysis. Again, it’s all about finding the issues up front and reducing risk later.

Liz: Well it’s intriguing…a Titanic-like iceberg of a design problem out there and we’re forging ahead…like the Titanic?

Ron: (laughs)Indeed – though given that the Titanic was built in my home city I always feel the need to point out that this particular disaster came about as a result of pilot error! To take your analogy further, I guess that the ‘iceberg’ here is a failure to close timing. Better guidance will definitely help you avoid that one.

Liz: Who knew?(laughs)Well, where can we learn more about this problem and how to fix it? Oh…and your customer survey…can we get a look at that?Sounds like some compelling information in there.

Ron: Yes, the customer survey was VERY telling and gives us a good leg up on what designers need to close at RTL for the next several generations of designs.In its current form, because we talked to customers, we can’t release it.

However, Bernard Murphy WILL refer to it at length in his DesignCon panel.

Liz: What panel is that?

Ron: At DesignCon we will be holding a panel on: “The Same Chip Killers keep Delaying your Schedules – What are you doing about it?” moderated by Ed Sperling, editor of System-Level Design. The panelists will discuss a broad range of issues, including timing constraints, the impact of IP etc. that repeatedly cause schedule slips. It will take place on Monday, January 31 at 4:45 p.m.