Verification IP complexity approaches design IP

Ah, how well I remember the "good old days" when being a digital design engineer involved oodles of fun basking in the sun and playing around with logic gates and not worrying much about anything else. In those happy days of yore, interfaces between things like microprocessors, memory devices, and peripherals largely involved only simple busses.

If you wanted to access a piece of data, you simply placed a value on the address bus and activated the "read" control signal. Similarly, if you wanted to store a byte of data, you placed a value on the address bus, another on the data bus, and activated the "write" control signal.

Of course life is much more complex now. Things like memory interfaces and high-speed serial interconnection standards like PCI Express are so complex that they can bring even the strongest amongst us to our knees. In a number of recent "Max Bytes" columns I've discussed a variety of PCI Express-centric design IP and verification IP (VIP) offerings, all of which have prompted a lot of interest with the guys and gals slogging away out there in the trenches.

In the case of VIP, the folks at Verisity Design seem to be pretty excited about their eVC (e Verification Component) solution for PCI Express-based designs. Just to refresh our memories, "e" is a sophisticated aspect-orientated hardware verification language which we might think of as a blend of C and Verilog with perhaps a hint of Pascal. An appropriate verification environment such as Verisity's SpecMan Elite subsequently uses e-based descriptions to guide simulations in an intelligent, directed manner.

Verification IP complexity

It's a worrying state of affairs when the verification IP is almost as complex as the design IP itself, but that's the stage we've reached with PCI Express. In the not-so-distant past, bus functional models (BFMs)  which could themselves be extremely sophisticated  were sufficient to test parallel interfaces such as PCI and PCI-X.

But times have moved on: in the case of interconnects like PCI Express, the variety of possible combinations and permutations is simply too large for most of us to wrap our brains around. This is where the power of Verisity's PCI Express eVC coupled with a SpecMan-type environment comes in, because it integrates constrained-random traffic generation, functional coverage (including functional coverage models) and a PCI-SIG compliance coverage suite into a single verification component.

This type of VIP is essential for verifying PCI Express IP, as well as complex chip designs that incorporate the PCI Express protocol. The eVC validates the wide variety of real-life scenarios the chip will encounter in actual usage by generating targeted "sequences;" that is, streams of transactions that can vary depending on specified constraints, error conditions, and the responses of the device under test. Better yet, an environment developed for module-level verification can be reused for system-on-chip-level and later for full-system-level verification, so you get "three bangs for your verification buck."

Of particular interest is the fact that the PCI Express specification involves a multi-layer protocol. When creating a PCI-based design, each layer typically has its own design team, where these teams are often based in different physical locations. In order to address this, Verisity's eVC has multiple layers consistent with the PCI Express stack. Each layer can be instantiated individually or in any combination with other layers.

This layered architecture provides a great deal of flexibility over the verification strategy for PCI Express cores. Users can develop each layer independently and the eVC can be used to verify these layers individually. If one design team provides only a single layer to other design groups, for example, a complete verification environment for that layer can delivered quickly and easily by using only the relevant PCI Express eVC layer. As more layers are made available, the eVC can be instructed to take account of these additional layers.

Another point well worth noting is that Verisity has eVCs available for a variety of interconnect standards, including AHB, AXI, Ethernet, USB, PCI, PCI-X, and PCI Express. All of these eVCs have a consistent user interface that provides for consistent configuration, a consistent test (sequence) creation interface, consistent coverage models, and consistent trace and debug facilities.

In a recent conversation with "yours truly," the folks from Verisity also mentioned that creating PCI Express-based designs requires a huge amount of "intellectual capital" because there are many different problems that need to be addressed. In some cases, the design team's knowledge of the more subtle machinations of PCI Express can be a little "light." In such circumstances, the Verisity team may stay on-site with their customers for a couple of weeks getting the environment up and running and teaching the engineering team all sorts of useful information about using and verifying their PCI Express implementations.

To date, Verisity's PCI Express eVC has been used by over 20 major semiconductor and systems customers, which certainly makes it worth an official "Cool Beans" from me. Until next time, have a good one!