Summary: A Novel Hardware-based Barrier Synchronization for Many-Core CMPs
JosŽe L. AbellŽan Juan FernŽandez
Dept. de IngenierŽia y TecnologŽia de Computadores
Facultad de InformŽatica - Universidad de Murcia
30100 Murcia, Spain
{jl.abellan,juanf,meacacio}@ditec.um.es
Manuel E. Acacio
Abstract
We present in this work a novel hardware-based bar-
rier mechanism for synchronization on many-core CMPs.
In particular, we leverage global interconnection lines
(G-lines) and S-CSMA technique, which have been used
to overcome some limitations of a flow control mechanism
(EVC) in the context of Networks-on-Chip, we propose a
simple G-line-based network that operates independently of
the main data network in order to carry out barrier syn-
chronizations. Next, we evaluate our approach by running
several applications on top of the Sim-PowerCMP perfor-
mance simulator. Our method only takes 4 cycles to carry
out the synchronization once all cores or threads have ar-