Apple, Samsung, Foundries Key to 3D ICs

SAN JOSE, Calif. – The semiconductor industry is in a standoff over the next big thing -- 3D chip stacks. Someone needs to blink before the technology will be viable for creating the next generation of high-performance, low-power systems.

It might be Globalfoundries undercutting rival TSMC on foundry prices for a 2.5D process -- if it can deliver it. It might be Samsung trying to widen its edge on Apple in smartphone and tablets. Or perhaps Nvidia will take a big hit on margins (maybe even a loss) to grab a big chunk of GPU marketshare and mindshare from rival Advanced Micro Devices.

That was the picture from a panel discussion where a member of the audience made a shocking disclosure the Apple A7 SoC in the iPhone 5s is "a poor man's 3D IC."

Xilinx talked about how it is already shipping 2.5D stacks where die are laid side-by-side on a silicon interposer. So far it has discussed products using multiple FPGAs or an FPGA and serdes on a chip.

The FPGA vendor will describe at the International Solid State Circuits Conference in February a product that puts two 65nm serdes next to an FPGA. It is also said to be working on devices with an ADC and DAC next to an FPGA for use in cellular base stations. So the applications for these relatively high-cost, low-volume products are slowly expanding.

But so far the Xilinx products are consuming less than 200 wafers a month, according to estimates. So what's the path to high volumes of tens or hundreds of thousands of wafers per month? In a word, torturous.

The reality is simple. Its been mentioned numerous times throughout prior comments. Simply put we need the volume equivalent to current MCU or DRAM. Volume will make 3-D affordable. So when there is demand for 200,000 WPM we will see mass adoption.

The reality is simple. Its been mentioned numerous times throughout prior comments. Simply put we need the volume equivalent to current MCU or DRAM. Volume will make 3-D affordable. So when there is demand for 200,000 WPM we will see mass adoption.

has any monolithic 3D chip with Logic on top of memory stack been built yet ? Quite aside from the process integration issues would n't the difference in floorplan between Memory and a SoC increase the interconnect length, thus largely negating the advantage of short vias ?

Apple's approach to poor man's 3D packaging must have logic behind it. Two of that can be very good yield for current manufacturing and Design for Testability. If you need to meet these two aspects, Apple's approach may be prudent.

Real 3D packagin may be more essential for wearable technology and devices.