The schematic spice deck uses estimates for the diffusion areas and
perimeters and has no fixed parasitic capacitances. Parallel
transistors are merged together. The
Alliance
extracted spice deck
also uses an estimate for the diffusion areas and perimeters, and the
fixed parasitic capacitance only considers area and not sidewall.
All capacitances are lumped to ground. The
transistor length is the value that will appear in the CIF
file, which for this technology is different to the one that should appear
in the spice deck (0.12µm instead of 0.13µm).

The spice deck extracted from
Magic
also has limitations which means that lambda values for the transistors
have to be extracted and a scaling has to be applied during Spice
simulation. This is done with a .OPTIONS card:

.OPTIONS scale=0.055

Resistance should be extracted and this should be possible with
Magic
but I have not succeeded so far.

The fixed parasitic capacitances extracted by
Alliance
and Magic
can be compared by lumping them all to ground.