Figure 10-1. Machine State Register (MSR)
13 WE Wait State Enable
0 The processor is not in the wait state.
1 The processor is in the wait state. If MSR[WE] = 1,
the processor remains in the wait state until an interrupt is taken,
a reset occurs, or an external debug tool clears WE.

Q_20: The documentation mentions three power states; active, standby and sleep.
Nowhere in the documentation have I found any detail on how those states are
managed and exactly what happens in the non-active states.
A_20: PowerPC 4XX CPU cores have several features that help conserve power:
* First, the circuit implementation of the CPU cores automatically does
clock gating to registers and latches when they are not being selected.
* The CPU cores provide for program accessible means of stopping most
activity by halting the execution pipeline.
* Chip-top logic can be used to inactivate the clock enable inputs to
the CPU or turn off the clocks external to the CPU core.
* Chip-top logic can also be used to reduce the frequency of the clocks
so that the CPU can continue to operate at a reduced capacity
The power states are defined as:
* Active: the normal operating mode where the CPU is executing instructions
* Standby: CPU clocks are active; the execution pipeline is stopped; an
interrupt will start execution.
* Sleep: CPU clocks are inactive or gated off; CPU can not be restarted via
software mechanism or interrupt. This must be done by chip-top logic
external to the CPU core

How to enter "Sleep" state on PPC440

- Condtion where CPU enters "Sleep" state

This core sleep request signal is sent to a CPM unit to indicate that the
core is requesting to be put into a sleep mode. This signal is asserted by
the processor when the CPU is in the wait state, (i.e. MSR[WE] is set
and no incomplete instructions are in progress, including APU
instructions), the caches are idle (no fill or flush
operations are in progress or pending), and the trace FIFO is empty.

- Condtion where CPU leave "Sleep" stete

Asserting following signal lines which are came from CPU core and are connected to
CPM(Clock and Power managment Module), enter CPU "Sleep" state. So to leave from
the state, those signals would be
de-asserted.
C440_cpmDECIrptReq Decrementer
C440 _cpmFITIrptReq Fixed interval timer
C440_cpmWDIrptReq WatchDog Output
C440_cpmTimerResetReq 2nd reset from WatchDog
C440_cpmMsrEE External Interrupt.
In short, CPU timers can be used to leave "Sleep" state.