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Abstract:

A semiconductor device having a substrate, a dielectric layer, a
polycrystalline silicon ("poly") resistor, a drain, and a source is
disclosed. After implantation, the poly resistor may have a lateral
doping profile with two peaks, one near each edge of the poly resistor,
and a trough near the middle of the poly resistor. Such a doping profile
can allow the poly resistor to have a resistance that is insensitive to
small variations in critical dimension of the poly resistor. The
resistance of the poly resistor may be determined by the doping dose of
the tilted implant used to form the poly resistor. The tilted implant may
be used to form the drain and the source of a transistor substantially
simultaneously as forming the poly resistor.

Claims:

1. A method of manufacturing a semiconductor device, comprising: forming
a dielectric layer on a substrate; forming a polycrystalline silicon
("poly") layer on the dielectric layer; forming a patterned masking layer
on the poly layer; etching a portion of the dielectric layer and a
portion of the poly layer using the patterned masking layer to form a
remaining portion of the dielectric layer and a remaining portion of the
poly layer; and implanting dopants at a tilted angle into the remaining
portion of the poly layer to form a poly resistor and into the substrate
to form lightly-doped drain regions, wherein the patterned masking layer
prevents implantation of dopants into the remaining portion of the poly
layer through a top surface of the patterned masking layer during the
implanting.

14. A semiconductor device, comprising: a substrate; a dielectric layer
on the substrate; and a poly resistor on the dielectric layer; wherein
the poly resistor was formed using a tilted implant.

15. The device of claim 14, wherein operation of the tilted implant
results in the poly resistor having a lateral doping concentration
profile with two peaks, one near each edge of the poly resistor, and with
a trough near the middle of the poly resistor.

16. The device of claim 15, wherein the lateral doping profile with two
peaks causes the poly resistor to have a resistance that is insensitive
to small variations in a critical dimension of the poly resistor.

17. The device of claim 16, wherein the critical dimension is greater
than or equal to 0.25 μm.

18. The device of claim 14, wherein the poly resistor has a resistance
that is determined by a doping dose of the tilted implant.

Description:

BACKGROUND

[0001] 1. Technical Field

[0002] This disclosure relates generally to improved semiconductor devices
and methods for making such devices.

[0003] 2. Related Art

[0004] In integrated circuit design, polycrystalline silicon ("poly")
resistors having sheet resistances greater than or equal to 10
kilo-ohms/square (kΩ/sq) and very low tolerances (i.e., very little
variations in resistance) are sometimes required. During the fabrication
process of an integrated circuit, poly resistors are formed by doping
poly layers. For the poly resistors to have the required sheet
resistances, an implant with an appropriate doping dose needs to be used.
In conventional manufacturing processes, the tolerance in resistance is
highly dependent on variations in the critical dimension of the poly
layer.

[0005] Thus, what is needed are semiconductor devices and methods for
manufacturing them wherein poly resistors are insensitive to variations
in their critical dimensions and can be formed using conventional
manufacturing processes.

BRIEF SUMMARY OF THE INVENTION

[0006] According to various embodiments, a method of manufacturing an
integrated circuit device and its resulting structure are described.
According to an example method, a dielectric layer is formed on a
substrate. A polycrystalline silicon ("poly") layer may be formed over
the dielectric layer, followed by the formation of a masking layer over
the poly layer. The dielectric layer, poly layer and masking layer may be
etched. A tilted implant may be used to dope the sidewalls of the poly
layer may be doped by the tilted implant, forming a poly resistor.
Substantially simultaneously as forming the poly resistor, the exposed
portions of the substrate may be doped to form a drain and a source of a
transistor.

[0007] A semiconductor device is also described. The semiconductor device
may include a substrate, a dielectric layer, a poly resistor, a drain and
a source. After implantation, the poly resistor may have a lateral doping
profile with two peaks, one near each edge of the poly resistor, and a
trough near the middle of the poly resistor. Such a doping profile can
allow the poly resistor to have a resistance that is insensitive to
variation in critical dimension of the poly resistor. The resistance of
the poly resistor may be determined by the doping dose of the tilted
implant used to form the poly resistor. The tilted implant may be used to
form the drain and the source of a transistor substantially
simultaneously as forming the poly resistor.

[0008] Further features and advantages of embodiments of the invention, as
well as the structure and operation of various embodiments of the
invention, are described in detail below with reference to the
accompanying drawings. It is noted that the invention is not limited to
the specific embodiments described herein. Such embodiments are presented
herein for illustrative purposes only. Additional embodiments will be
apparent to a person skilled in the relevant art(s) based on the
teachings contained herein.

BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES

[0009] Embodiments of the invention will now be described, by way of
example only, with reference to the accompanying schematic drawings in
which corresponding reference symbols indicate corresponding parts.
Further, the accompanying drawings, which are incorporated herein and
form part of the specification, illustrate embodiments of the present
invention, and, together with the description, further serve to explain
the principles of the invention and to enable a person skilled in the
relevant art(s) to make and use the invention.

[0010] FIG. 1 depicts a cross-section of a semiconductor device according
to an embodiment.

[0011] FIG. 2 depicts a cross-section of a semiconductor device being
doped according to an embodiment.

[0012] FIG. 3 depicts a cross-section of a semiconductor device being
doped according to an embodiment.

[0013] FIG. 4 depicts a cross-section of a semiconductor device with
doping concentration contour lines according to an embodiment.

[0014] FIG. 5 depicts the doping concentration profile across a
polycrystalline silicon ("poly") resistor of a semiconductor device
according to an embodiment.

[0015] FIG. 6 is a flowchart of a method of manufacturing a semiconductor
device with poly resistors according to various embodiments.

[0016] The features and advantages of embodiments of the present invention
will become more apparent from the detailed description set forth below
when taken in conjunction with the drawings. In the drawings, like
reference numbers generally indicate identical, functionally similar,
and/or structurally similar elements.

DETAILED DESCRIPTION OF THE INVENTION

[0017] This specification discloses one or more embodiments that
incorporate the features of this invention. The disclosed embodiment(s)
merely exemplify the present invention. The scope of the present
invention is not limited to the disclosed embodiment(s). The present
invention is defined by the claims appended hereto.

[0018] The embodiment(s) described, and references in the specification to
"one embodiment," "an embodiment," "an example embodiment," etc.,
indicate that the embodiment(s) described may include a particular
feature, structure, or characteristic, but every embodiment may not
necessarily include the particular feature, structure, or characteristic.
Moreover, such phrases are not necessarily referring to the same
embodiment. Further, when a particular feature, structure, or
characteristic is described in connection with an embodiment, it is
understood that it is within the knowledge of one skilled in the art to
effect such feature, structure, or characteristic in connection with
other embodiments whether or not explicitly described.

[0019] According to certain embodiments, when etching a material, at least
a portion of the material remains behind after the etching process is
completed. In contrast, when removing a material, all or substantially
all of the material is removed in the removal process.

[0020] In the teachings contained herein, various regions of a substrate
upon which devices are fabricated are mentioned. It should be understood
that these regions may exist anywhere on the substrate and furthermore
that the regions may not be mutually exclusive. That is, in some
embodiments, portions of one or more regions may overlap. It should be
understood that any number of regions may exist on the substrate and may
designate areas having certain types of devices or materials. In general,
the regions are used to conveniently describe areas of the substrate that
include similar devices and should not limit the scope or spirit of the
described embodiments.

[0021] In embodiments, the terms "forming," "form," "deposit," or
"dispose" refer to the act of applying a layer of material to the
substrate or another layer of material. Such terms are meant to describe
any possible layer-forming technique including, but not limited to,
thermal growth, sputtering, evaporation, chemical vapor deposition,
epitaxial growth, electroplating, etc. According to various embodiments,
for instance, deposition may be performed according to any appropriate
well-known method. For instance, deposition can comprise any process that
grows, coats, or transfers material onto a substrate. Some well-known
technologies include physical vapor deposition (PVD), chemical vapor
deposition (CVD), electrochemical deposition (ECD), molecular beam
epitaxy (MBE), atomic layer deposition (ALD), and plasma-enhanced CVD
(PECVD), amongst others.

[0022] In embodiments, the term "substrate" refers to silicon. However,
the substrate may also be any of a wide array of semiconductor materials
such as germanium, gallium arsenide, indium phosphide, etc. In other
embodiments, the substrate may be electrically non-conductive such as a
glass or sapphire wafer.

[0023] In embodiments, "mask" may comprise any appropriate material that
allows for selective removal (or etching) of an unmasked portion a
material. According to some embodiments, masking structures may comprise
a photoresist such as Poly(methyl methacrylate) (PMMA), Poly(methyl
glutarimide) (PMGI), a Phenol formaldehyde resin, a suitable epoxy, etc.

[0024] An example method for manufacturing a semiconductor device with
polycrystalline silicon ("poly") will now be described with respect to
FIGS. 1-3, which depict cross-sections of a semiconductor device 100 at
various stages during production. In FIG. 1, semiconductor device 100 is
depicted as having a substrate 102. A stack 104 has been formed on top of
substrate 102 according to a number of known methods. The present
disclosure is not limited to any particular method of producing stack
104. Indeed the spirit and scope of the invention includes any
appropriate method for forming stack 104. As can be seen in FIG. 1, stack
104 includes, over the substrate 102, a dielectric layer 106, such as,
but not limited to, silicon dioxide ("oxide"). A poly layer 108 has been
disposed over dielectric layer 106. A masking layer 110, such as, but not
limited to, silicon nitride ("nitride"), has been disposed over poly
layer 108.

[0025] According to an embodiment, FIG. 2 depicts semiconductor device 100
at a later point in the production process, where masking layer 110 has
been removed, for example by etching. Subsequently, substrate 102 and
poly layer 108 are exposed to an implantation process 202 that is
perpendicular to the surface of substrate 102 and the top surface of the
poly. It is to be appreciated that, in some embodiments, additional
masking and etching stages may be conducted to selectively implant poly
108 while preventing substrate 102 from being implanted. After such a
perpendicular implantation, the lateral doping concentration within poly
108 is uniform. Consequently, the resistance of poly 108 is highly
dependent on its critical dimension.

[0026] According to another embodiment, FIG. 3 depicts device 100 at a
later point in the production process, where substrate 102 and stack 104
are exposed to a tilted implantation process 302. For example, tilted
implantation process 302 may comprise, but is not limited to, four
rotations of p-type boron or boron fluoride ions at a tilt angle of 35
degrees and a doping dose of greater than or equal to 8×1013
ions/cm2. For boron ions, the doping energy level may be greater
than or equal to 10 keV. For boron fluoride ions, the doping energy level
may be greater than or equal to 60 keV. In yet another example, the
tilted implantation process may be a lightly doped drain (LDD)
implantation process where, for example, a lightly doped drain implant is
used. As can be seen in FIG. 3, unlike implantation process 202 in FIG.
2, tilted implantation process 302 allows ions to be implanted into the
sidewalls of poly layer 108, without the removal of masking layer 110.
Additionally, substantially simultaneously, the ions are implanted into
the exposed regions of substrate 102.

[0027] FIG. 4 depicts an exemplary result of the tilted implantation
process. The contour lines illustrate cross-sectional doping
concentration levels after implantation, in particular within substrate
102 and poly layer 108. In substrate 102, the doping concentration peaks
where substrate 102 is exposed, in regions 408 and 410. One of regions
408 and 410 can eventually form a drain of a transistor, while the other
can form source of the transistor, for example. In an embodiment, doped
poly layer 108 will eventually form a poly resistor. In poly layer 108,
the doping concentration after implantation is at a maximum close to each
edge, in regions 402 and 404, and is at a minimum in region 406. An
exemplary lateral doping concentration profile along line 412, across
poly layer 108, is depicted in FIG. 5.

[0028] FIG. 5 shows, for example, a doping concentration 504, which is the
number of ions, out of the total number of ions as implanted. As can be
seen in FIG. 5, doping concentration 504 has two peaks at points 506 and
508, close to each edge of poly layer 108, and one trough at point 510.
In an embodiment, as determined by desired implementation specifications,
the doping concentration C1 at points 506 and 508 can be, for
example, 50 to 100 times greater than the doping concentration C2 at
point 510. Doping concentration 504 having two peaks near the edges of
poly layer 108 indicates that the ions are concentrated near the edges.
As a result, small variations in the critical dimension, shown as "w" on
FIG. 5, of the poly layer 108 have negligible effect on the overall
doping concentration and thus the subsequent resistance of the poly
resistor. In other words, the resistance of the poly resistor is
practically insensitive to small variations in its critical dimension. It
is to be appreciated that, in an embodiment, although the dopants can
spread out and the doping profile can become more uniform after
annealing, the total number of ions in poly layer 108 and the resistance
of the poly resistor remain unchanged. In an embodiment, critical
dimension w is greater than or equal to 0.25 μm.

[0029] FIG. 6 depicts a method 600 of constructing a semiconductor device
such as device 300 according to various embodiments. The discussion of
FIG. 6 will make reference to FIG. 3, but it should be understood that
method 600 is not limited to the specific embodiment depicted in FIG. 3,
but is more generally applicable.

[0030] As shown in FIG. 6, method 600 begins at step 602 by forming a
dielectric layer (.g., dielectric layer 106) on a substrate 102. At step
604, poly layer 108 is formed over dielectric layer 106. At step 606,
masking layer 110 is formed over poly layer 108. Portions of dielectric
layer 106, poly layer 108 and masking layer 110 are etched at step 608.
At step 610, a tilted implantation process 302 is used to dope the
sidewalls of poly layer 108 and the exposed regions of substrate 102.

[0031] It is to be appreciated that the Detailed Description section, and
not the Summary and Abstract sections, is intended to be used to
interpret the claims. The Summary and Abstract sections may set forth one
or more but not all exemplary embodiments of the present invention as
contemplated by the inventor(s), and thus, are not intended to limit the
present invention and the appended claims in any way.

[0032] Embodiments of the present invention have been described above with
the aid of functional building blocks illustrating the implementation of
specified functions and relationships thereof. The boundaries of these
functional building blocks have been arbitrarily defined herein for the
convenience of the description. Alternate boundaries can be defined so
long as the specified functions and relationships thereof are
appropriately performed.

[0033] The foregoing description of the specific embodiments will so fully
reveal the general nature of the invention that others can, by applying
knowledge within the skill of the art, readily modify and/or adapt for
various applications such specific embodiments, without undue
experimentation, without departing from the general concept of the
present invention. Therefore, such adaptations and modifications are
intended to be within the meaning and range of equivalents of the
disclosed embodiments, based on the teaching and guidance presented
herein. It is to be understood that the phraseology or terminology herein
is for the purpose of description and not of limitation, such that the
terminology or phraseology of the present specification is to be
interpreted by the skilled artisan in light of the teachings and
guidance. Additionally, it should be understood that none of the examples
or explanations contained herein are meant to convey that the described
embodiments have been actually reduced to practice.

[0034] The breadth and scope of the present invention should not be
limited by any of the above-described exemplary embodiments, but should
be defined only in accordance with the following claims and their
equivalents.