A novel approach to achieve concurrent error detection in finite-field multiplication over GF(2m) that uses multiple-bit interlaced parity codes is presented. These codes are implemented as a generic parity checker, which means they can be used with any multiplier architecture. Relative to the number of parity bits used, much improved delay and error-detection performance are achieved c...
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A current-measuring technique is introduced, which promises to substantially enhance power analysis attacks against cryptographic co-processors. The proposed technique exploits an active circuit to measure the instantaneous current consumption of a device under attack while supplying, at the same time, the device with a stable voltage. Higher gain-bandwidth product, higher sensitivity and lower in...
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A capacitor-free CMOS low dropout regulator (LDR) using the nested Miller compensation with an active resistor (NMCAR) is presented. It can efficiently control the damping factor and reduce the required Miller compensation capacitance. It can also resolve the trade-off between dc loop gain and damping factor, which existed in the LDR using the nested Miller compensation. To reduce the total Miller...
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A fully integrated nanoelectromechanical system (NEMS) resonator together with a compact built-in complementary metal-oxide-semiconductor (CMOS) interfacing circuitry is presented. The proposed low-power second generation current conveyor circuit allows measuring the mechanical frequency response of the nanocantilever structure in the megahertz range. Detailed experimental results at different DC ...
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A low-voltage, low-noise, charge-sensitive preamplifier (CSA) for particle tracking using a silicon strip detector was designed. The preamplifier was optimised in terms of the total output noise performance using a noise minimisation technique based on the MOSFET noise small signal equivalent circuit and readout front-end noise optimisation criteria valid in the strong inversion region. The preamp...
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An analysis of a modified series-L / parallel-tuned Class-E power amplifier is presented, which includes the effects that a shunt capacitance placed across the switching device will have on Class-E behaviour. In the original series L/parallel-tuned topology in which the output transistor capacitance is not inherently included in the circuit, zero-current switching (ZCS) and zero-curr...
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With the continuing scaling of metal-oxide-semiconductor (MOS) devices, the hot-carrier (HC)-induced device degradation has become a major reliabiliy concern in sub- and deep-submicrometre MOS field-effect transistors (MOSFETs) and lateral double-diffused MOSFETs (LDMOSFETs). It is believed that the degradation is mainly due to the effects of the generated oxide-trapped charges and interface traps...
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