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Abstract:

A capacitor forming method includes forming an electrically conductive
support material over a substrate, with the support material containing
at least 25 at % carbon. The method includes forming an opening through
at least the support material where the opening has an aspect ratio of at
least 20:1 within a thickness of the support material. After forming the
opening, the method includes processing the support material to effect a
reduction in conductivity, and forming a capacitor structure in the
opening.

Claims:

1. A capacitor forming method comprising: forming a support material over
a substrate, the support material containing at least 20 at % carbon;
forming an opening through at least the support material to the
substrate, the support material having a thickness and the opening having
an aspect ratio of 20:1 or greater within the thickness of the support
material; after forming the opening, forming a capacitor structure
contacting the substrate and the support material in the opening; and
heating the support material to effectuate a reduction in conductivity
that increases a resistance of the support material by at least 4 decades
with less than a 10% mass loss of the support material.

3. The method of claim 2, wherein the method includes anisotropically
etching the opening using an organic spin-on anti-reflective coating
(ARC) on top of the low temperature ALD oxide etch mask.

4. The method of claim 1, wherein the carbon is primarily in the form of
an electrically conductive, carbon backbone polymer or a
hydrocarbon-containing, silicate backbone polymer.

5. The method of claim 4, wherein the support material further comprises
titanium and silicon, titanium does not exceed 7.7 at %, and silicon does
not exceed 12.5 at %.

6. The method of claim 1, wherein forming the support material includes
forming a non-crystalline, electrically conductive support material over
the substrate, which is primarily in the form of an electrically
conductive, carbon backbone polymer.

7. The method of claim 1, wherein the heating the support material to
effectuate the reduction in conductivity includes heating the support
material to at least approximately 180 degrees Celsius for at least 30
minutes.

8. The method of claim 1, wherein the support material comprises hydrogen
and about 5 at % or less of nitrogen, oxygen, sulfur, metals, and
semimetals.

9. A capacitor forming method comprising: forming an electrically
conductive material over a substrate, the electrically conductive
material containing at least 20 at % carbon; forming an opening in the
electrically conductive material; and after forming the opening,
processing the electrically conductive material to effect a reduction in
conductivity.

10. The method of claim 9, wherein forming the opening includes forming
the opening having an aspect ratio of at least 20:1 within a thickness of
the electrically conductive material.

11. The method of claim 9, wherein the method includes forming a
capacitor structure in the opening.

12. The method of claim 11, wherein forming the capacitor structure
includes: depositing a first conductive cell plate material; and
anisotropically etching support material between two or more container
structures to form a double-sided container structure after depositing
the first conductive cell plate material but before processing the
electrically conductive material to effect the reduction in conductivity.

13. The method of claim 9, wherein processing the electrically conductive
material to effect the reduction in conductivity includes heating the
electrically conductive material to approximately 180 degrees Celsius for
approximately 30 minutes.

14. The method of claim 9, wherein processing the electrically conductive
material to effect the reduction in conductivity includes heating the
electrically conductive material to a temperature at least 180 degrees
Celsius, but below 200 degrees Celsius, for approximately 30 minutes.

15. The method of claim 9, wherein processing the electrically conductive
material to effect the reduction in conductivity increases a resistance
of the electrically conductive material by at least 4 decades with less
than a 10% mass loss of the electrically conductive material.

16. The method of claim 9, wherein processing the support material to
effect the reduction in conductivity includes using photon irradiation
and/or electromagnetic field exposure.

17. The method of claim 9, wherein the electrically conductive material
comprises titanium not exceeding 7.7 at %, silicon not exceeding 12.5 at
%, hydrogen, and about 5 at % or less of nitrogen, oxygen, sulfur,
metals, and semimetals.

18. A capacitor forming method comprising: forming a conductive material
over a substrate, the conductive material containing at least 20 at %
carbon; forming a first opening having an aspect ratio of 20:1 or greater
in the conductive material; and after forming the first opening,
processing the conductive material to effect a reduction in conductivity
that increases a resistance of the conductive material by at least 4
decades with less than a 10% mass loss of the conductive material; and
forming a capacitor structure using the first opening.

19. The method of claim 18, wherein: the conductive material is initially
a non-crystalline support material primarily in the form of a carbon
backbone polymer or a hydrocarbon-containing silicate backbone polymer;
forming the first opening includes anisotropically etching the first
opening through the conductive material to the substrate; and processing
the conductive material to effect a reduction in conductivity includes
heating the conductive material after anisotropically etching.

20. The method of claim 18, wherein the method includes: forming a second
opening having an aspect ratio of 20:1 or greater in the conductive
material, wherein forming the capacitor structure using the first opening
includes: forming a conductive cell plate material in the first and
second openings; and removing at least a portion of the conductive
material between the first and second openings to form a double-sided
container structure before forming a dielectric material over conductive
cell plate material or processing the conductive material to effect the
reduction in conductivity.

Description:

PRIORITY APPLICATION INFORMATION

[0001] This application is a Divisional of U.S. application Ser. No.
12/099,577, filed Apr. 8, 2008, to be issued as U.S. Pat. No. 8,274,777
on Sep. 25, 2012, the specification of which is incorporated herein by
reference.

TECHNICAL FIELD

[0002] The invention relates to semiconductors and semiconductor
fabrication methods. More particularly, the invention relates to high
aspect ratio openings and etching methods for formation of high aspect
ratio openings.

BACKGROUND

[0003] Openings are formed in support materials so that microelectronic
structures may be formed in and their structure supported by the support
material. For example, a capacitor container for a dynamic random access
memory (DRAM) cell may be etched into a dielectric, such as silicon
dioxide (SiO2), which can be formed as a doped silicate glass. Use
of silicon dioxide dielectric can yield several disadvantages from an
etching standpoint. Dry etch of silicon dioxide has a large physical
component, that is, it is more like physical sputtering than like a
chemical etch. Its sputtering nature creates difficulty in obtaining a
straight profile since the etch does not exhibit a lateral component,
leading to a tapered profile.

[0004] The profile of an opening is of particular importance. The need for
accurately and precisely locating openings is in relation to other
structures is exemplified where contact holes or vias are provided
between devices. The profile of an opening is also important where
several adjacent openings are used to form vertical capacitive
structures. As the feature dimensions of devices decrease, the aspect
ratio (the ratio of depth to width) of the openings tend to increase. As
the aspect ratio increases, however, a phenomenon termed "twisting" can
occur.

[0005] In addition to tapered etch profiles, use of silicon dioxide also
may produce feature charging due to its insulative nature. Consequently,
the top of a feature, such as an opening in the silicon dioxide, charges
negatively relative to the bottom of the feature. Computer simulation has
shown the resulting vertical potential gradient as high as several
hundred volts, for example, 200 to 300 volts. Such a gradient may retard
the flux of positive ions that produce the etching effect and contribute
to aspect ratio dependent (ARD) etch, also known as reactive ion etch
(RIE) lag. As a result, as aspect ratio increases, etching may become
less effective.

[0006] Due to the physical component involved in a dry etch process of
silicon dioxide (SiO2), it is also possible for a lateral potential
gradient to exist. Features across a surface being etched might not be
symmetrical, resulting in feature charging differences in lateral
directions. Feature asymmetries may result from incoming photo
irregularities, asymmetries at the edge of an array compared to the
center of an array, or the stochastic nature of plasma polymer
deposition. Photo irregularities become apparent on inspection after the
development step during photolithography.

[0007] While a vertical electric field is responsible for aspect ratio
dependent etching (ARDE), a lateral potential gradient, i.e., electric
field, may orient the flux of positive ions away from true vertical,
leading to so-called twisting of etched features. Twisting occurs when
the etch front of the opening starts deviating from what is perpendicular
to the semiconductor substrate surface, for example, openings in the
shape of a corkscrew are possible. Twisting may become especially
noticeable in high aspect ratio (HAR) features. When etching a HAR or
other feature, openings may deflect laterally from true vertical.

[0008] The twisting phenomenon with respect to HAR openings is problematic
in that twisting reduces the efficiency of a contact by increasing the
distance between active device areas and by increasing the difficulty of
filling a contact with a conductive material, or can weaken or distort
vertical structures formed by etching. Such twisting may cause electrical
opens when the opening misses a landing contact, or may cause electrical
shorts when the opening twists into an adjacent feature, or may cause
unwanted variations in deposition layers upon distorted vertical
structures.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. 1A is a diagrammatic, cross-sectional view of a portion of a
semiconductor wafer comprising the cross-section shown in FIG. 1B along
the line 1A-1A.

[0010] FIG. 1B is a diagrammatic top view of a portion of the
semiconductor wafer at a preliminary processing stage of an embodiment.

[0011] FIG. 2A is a diagrammatic, cross-sectional view of the FIG. 2B
wafer portion comprising the cross-section shown in FIG. 2B along the
line 2A-2A.

[0012] FIG. 2B is a diagrammatic top view of the wafer portion shown at a
processing stage subsequent to that of FIG. 1B.

[0013] FIG. 3A is a diagrammatic, cross-sectional view of the FIG. 3B
wafer portion comprising the cross-section shown in FIG. 3B along the
line 3A-3A.

[0014] FIG. 3B is a diagrammatic top view of the wafer portion shown at a
processing stage subsequent to that of FIG. 2B.

[0015] FIG. 4A is a diagrammatic, cross-sectional view of the FIG. 4B
wafer portion comprising the cross-section shown in FIG. 4B along the
line 4A-4A.

[0016] FIG. 4B is a diagrammatic top view of the wafer portion shown at a
processing stage subsequent to that of FIG. 3B.

[0017] FIG. 4C is a diagrammatic, cross-sectional view along the line
4C-4C of FIG. 4B.

[0018] FIG. 5A is a diagrammatic, cross-sectional view of the FIG. 4A
wafer portion comprising the cross-section shown in FIG. 5B along the
line 5A-5A.

[0019] FIG. 5B is a diagrammatic top view of the wafer portion shown at a
processing stage subsequent to that of FIG. 5B.

[0020] FIG. 5C is a diagrammatic, cross-sectional view along the line
5C-5C of FIG. 5B.

[0021] FIG. 6 is a diagrammatic, cross-sectional view of a wafer portion
shown at a processing stage subsequent to that of FIG. 2A of an
embodiment including formation of a double-sided container.

[0022] FIG. 7 is a diagrammatic, cross-sectional view of a wafer portion
shown at a processing stage subsequent to that of FIG. 6 of an embodiment
including formation of a double-sided container.

[0023] FIG. 8 is a diagrammatic, cross-sectional view of a wafer portion
shown at a processing stage subsequent to that of FIG. 7 of an embodiment
including formation of a double-sided container.

DETAILED DESCRIPTION

[0024] The present disclosure includes methods, capacitors, and high
aspect ratio (HAR) structures, e.g., openings, vertical features. One
method embodiment of a capacitor forming method includes forming an
electrically conductive support material over a substrate, with the
support material containing at least 25 atomic percent (at %) carbon. The
method includes forming an opening through at least the support material
where the opening has an aspect ratio of at least 20:1 within a thickness
of the support material. After forming the opening, the method includes
processing the support material to effect a reduction in conductivity,
and forming a capacitor structure in the opening.

[0025] In memory devices and other semiconductor-based circuitry,
capacitors, e.g., MBit capacitors, are typically etched into substrates,
followed by deposition of cell plates and dielectrics, e.g.,
charge-separating layers. In previous approaches, fabrication of
capacitors includes formation in dielectric films, as well as conductive
films.

[0026] Dielectric films provide electrical isolation, particularly between
periphery devices. However, dielectric films are difficult to etch due to
their generally refractory nature and feature charging, e.g., the top of
a feature being negatively charged, while the bottom of a feature being
positively charged. Etching dielectric films is primarily physically
driven by high energy ion bombardment. Vertical electric fields resulting
from feature charging tend to repel positive ions from the bottom of the
feature, reducing etch rate and causing overly tapered feature profiles,
among other defects. Lateral electric fields resulting from feature
charging, arising for example from mask irregularities and/or the
stochastic nature of plasma etching, can result in feature twisting or
other feature irregularities.

[0027] Conductive films on the other hand, are easier to etch at high
aspect ratios (ARs) with chemically driven plasma. The chemically driven
plasma is not subject to electric field-induced feature distortion such
as twisting. For example, production of approximately 70:1 AR capacitors
formed in crystalline, i.e., conductive, silicon have been demonstrated
without twisting, with ARs in excess of 100:1 possible. However after
etching capacitor features, the conductive materials generally must be
stripped out and replaced with a dielectric, e.g., having reduced
conductivity, to provide insulation for separating electrical charges
within the capacitor.

[0028] According to one or more embodiments of the present disclosure,
semiconductor fabrication of various features include deposition of an
initially-conductive material, which is subsequently processed, e.g.,
after capacitor feature formation, to effect a change in the conductivity
of the material, e.g., reduce conductivity of the material such that it
may be utilized as a capacitor dielectric for electrical isolation of the
conductive charge-carrying plates. In this manner, the advantages
associated with the chemically driven plasma etching characteristics of a
conductive material may be realized in feature formation, without having
to subsequently remove the conductive material and replace it with
another, more insulative, material. Utilizing support material with
initially-conductive properties may reduce the tapered nature of etch
profiles, ARD etch, and feature twisting. Thereafter, the property of the
material is changed from an initially more conductive state, to a less
conductive state. In the less conductive state, the support material may
serve as the insulation between capacitor structures for example. Thus,
the same material achieves the advantages associated with etching
conductive material, as well as those associated with isolating devices
with non-conductive material, without the inefficiencies associated with
having to form, remove, and replace several materials during fabrication.

[0029] Such a change, e.g., reduction, in material conductivity, from
conductor to dielectric, is referred to herein as an electrical phase
change. An electrical phase change is not to be confused with a physical
phase change of the material, e.g., from a solid to a liquid, etc.
Furthermore, "conductor" and "dielectric," as used herein, are utilized
as relative classifications, rather than absolute classifications, i.e.,
a dielectric being less electrically-conductive than a conductor.

[0030] The use of support materials with better etching characteristics
may provide desired improvements. While such improvements may be
particularly noticeable in HAR features, they may nonetheless be realized
when etching features with lower aspect ratios.

[0031] The Figures herein follow a numbering convention in which the first
digit or digits correspond to the drawing Figure number and the remaining
digits identify an element or component in the drawing. Similar elements
or components between different Figures may be identified by the use of
similar digits. For example, 110 may reference element "10" in FIG. 1,
and a similar element may be referenced as 210 in FIG. 2. It should also
be apparent that the scaling on the figures does not represent precise
dimensions of the various elements illustrated therein.

[0032] In the following detailed description of the present disclosure,
reference is made to the accompanying drawings that form a part hereof,
and in which is shown by way of illustration how one or more embodiments
of the disclosure may be practiced. These embodiments are described in
sufficient detail to enable those of ordinary skill in the art to
practice the embodiments of this disclosure, and it is to be understood
that other embodiments may be utilized and that process, electrical,
and/or structural changes may be made without departing from the scope of
the present disclosure.

[0033] In the embodiment of FIGS. 1A and 1B, a portion of a semiconductor
wafer 110 is shown at a preliminary processing stage of an embodiment.
Portion 110 includes a substrate 112. Substrate 112 includes a
semi-conductive material. To aid in interpretation of the claims that
follow, the terms "semi-conductive" and "semiconductor" substrate are
defined to mean any construction comprising semi-conductive material,
including, but not limited to, bulk semi-conductive materials such as a
semi-conductive wafer (either alone or in assemblies comprising other
materials thereon), and semi-conductive material layers (either alone or
in assemblies comprising other materials). The term "substrate" refers to
any supporting structure, including, but not limited to, the
semi-conductive substrates described above.

[0034] In the embodiment of FIGS. 1A and 1B, substrate 112 is divided into
three defined regions 114, 116 and 118. Region 114 corresponds to a
memory array region. Region 118 corresponds to a region other than the
memory array region, and can correspond to, for example, a so-called
peripheral region. The region is referred to as a peripheral region
because it is peripheral to the memory array region. Typically, logic
circuitry and other circuitry associated with the control of data flow to
and from memory devices associated with memory array region 114 would be
associated with peripheral region 118. Region 116 corresponds to a
location between the memory array region 114 and the peripheral circuitry
associated with region 118. Dashed lines are provided through portion 110
to roughly indicate the various defined regions 114, 116 and 118
extending within the structure. Various circuit devices (not shown) could
be associated with peripheral region 118 at the processing stage of FIGS.
1A and 1B.

[0035] In the embodiment of FIG. 1A, a plurality of electrically
conductive node locations 120, 122, 124 and 126 are shown within memory
array region 114 of substrate 112. Node locations 120, 122, 124 and 126
can correspond to, for example, conductively-doped diffusion regions
within a semi-conductive material of substrate 112, and/or to conductive
pedestals associated with substrate 112. Although the node locations are
shown to be electrically conductive at the processing stage of FIG. 1A,
it is to be understood that the electrically conductive materials of the
node locations could be provided at a processing stage subsequent to that
of FIG. 1A (not shown). Node locations 120, 122, 124 and 126 can
ultimately be electrically connected with transistor constructions (not
shown in FIG. 1A) and can correspond to source/drain regions of the
transistor constructions, or can be ohmically connected to source/drain
regions of the transistor constructions. Transistor gates and other
components of the transistor constructions can be present within memory
array region 114 at the processing stage of FIG. 1A, or can be formed in
subsequent processing.

[0036] As shown in the embodiment of FIGS. 1A and 1B, support material 128
is formed over substrate 112. Support material 128 can comprise a single
layer (as shown) of homogeneous or non-homogeneous material, e.g., a
mixture, multiple layers of a single homogeneous or non-homogeneous
material, or multiple layers of differing composition and/or physical
properties.

[0037] According to one or more embodiments, support material 128 is a
conductive polymer that is stable to 375 degrees C., and is capable of
being formed and initially cured, i.e., to an electrically conductive
solid, to a post-cure/PEB thickness of at least 3 microns without
cracking. According to one or more embodiments, support material 128 is
capable of being formed and initially cured to a post-cure/PEB thickness
of 3-4 microns without cracking. According to one or more embodiments of
the present disclosure, the support material 128 is formed of a
conductive polymer blended with a polymer matrix in order to achieve a
desired thickness, as needed for formation of particular features.

[0038] Support material 128 can include of one or more electrically
insulative and/or electrically conductive materials. In particular,
support material 128 may contain at least 20 at % carbon. While 20 at %
carbon may be suitable for either insulative or conductive materials, a
support material with higher carbon content might contribute to increased
conductivity, depending upon the other materials. Consequently, in the
case of electrically conductive materials, support material 128 may
contain at least 25 at % carbon. According to one or more embodiments,
e.g., in the case of electrically conductive materials, support material
128 may contain at least 50 at % carbon.

[0039] The carbon may be primarily in the form of an electrically
conductive, carbon backbone polymer or a hydrocarbon-containing, silicate
backbone polymer, with or without a polymeric carrier "matrix," e.g., as
a mixture or blend. Although the silicate backbone polymer may be
electrically insulative, such polymers are typically electrically
conductive. Silicate backbone polymers are known containing as much as 36
at % carbon, but may or may not be conductive.

[0040] According to one or more embodiments, support material 128 is
electrically conductive, such that feature charging may be reduced. As a
result, vertical and/or lateral potential gradients may be reduced,
addressing the problems of aspect ratio dependent etch and twisting.
Reduction of feature charging thus becomes especially significant for
high aspect ratio features. In the case where support material 128 is
electrically conductive feature charging may be beneficially reduced.

[0041] According to one or more embodiments, support material 128 may
further include titanium and/or silicon. The silicon may be primarily in
the form of the hydrocarbon-containing, silicate backbone polymer.
Alternatively, the silicon may be in another form, for example, in
combination with an electrically conductive, carbon backbone polymer. The
titanium and/or silicon may be in the form of oxides, which are
insulative, or in other forms, which may be insulative or conductive.
Titanium and/or silicon may be provided to increase the rigidity of
support material 128 beyond the rigidity otherwise exhibited in the
absence of titanium and silicon. A more rigid support material 128 may
improve stability during subsequent processing. An amount of titanium
and/or silicon may be selected to produce the desired effect.

[0042] In an example embodiment where support material 128 does not
include titanium, the silicon might not exceed 26 at %. In an example
embodiment where support material 128 does not include silicon, the
titanium might not exceed 12 at %. In an example embodiment where support
material 128 includes both titanium and silicon, the titanium might not
exceed 7.7 at % and silicon might not exceed 12.5 at %.

[0043] According to one or more embodiments, the support material 128 is
non-crystalline. For example, support material 128 may consist of
amorphous carbon, intermediate carbon, transparent carbon, or a
combination thereof. In the context of the present disclosure,
"amorphous" carbon refers to carbon that is not crystalline. That is,
amorphous carbon includes "transparent" carbon which has some structural
regularity due to an increased prevalence of sp3 hybridized bonding
(four single bonds per carbon). However, transparent carbon does not
exhibit the high degree of structural regularity well known as
characteristic of crystalline carbon, for example, diamond, graphite,
etc. In comparison, fully amorphous carbon has no structural regularity
due to an increased prevalence of sp2 hybridized bonding (one double
bond and two single bonds per carbon) and literally "lacks definite
form," i.e. is amorphous. Fully amorphous carbon thus includes more
aromatic and/or unsaturated hydrocarbons. Understandably, amorphous
carbon also includes "intermediate" carbon positioned between fully
amorphous carbon and crystalline carbon with regard to its structural
regularity. Transparent carbon is thus within the realm of and is one
type of intermediate carbon.

[0044] One example of transparent carbon contains about 55 at % carbon and
about 40 at % hydrogen with the remainder nitrogen and/or oxygen. One
example of fully amorphous carbon includes about 70 at % carbon and about
25 at % hydrogen with the remainder nitrogen and/or oxygen. Consequently,
support material 28 may consist of from about 55 to about 70 at % carbon,
about 5 at % or less of nitrogen, oxygen, sulfur, metals, and semimetals
(any of which may be absent), and the remainder hydrogen. "Semimetals"
commonly refers at least to boron, silicon, arsenic, selenium, and
tellurium.

[0045] According to one or more embodiments, forming support material 128
may include applying a liquid, or viscous, mixture to substrate 112 and
initially curing the liquid mixture into a solid. Application of the
liquid mixture may be accomplished by spin-on techniques, as the same
will be appreciated by one of ordinary skill in the art. Forming support
material 128 might be accomplished using other techniques, for example,
chemical vapor deposition (CVD), etc. Known CVD techniques for depositing
transparent carbon include plasma enhanced CVD and thermal CVD. Plasma
enhanced CVD of transparent carbon often occurs at about 375° C.

[0046] The liquid mixture may be a mixture of polymer solids and a
carrier, and, optionally, a cross-linking agent and/or a catalyst.
Potentially suitable liquid mixtures include anti-reflective coating
(ARC) material mixtures and/or hard mask (HM) material mixtures. Liquid
mixtures known for use in forming anti-reflective coatings and/or hard
masks, instead of forming support materials, might be processed largely
according to a manufacturer's specifications, including a series of
heated baking and/or curing stages. Such initial processing may evaporate
the carrier and other components while cross-linking and/or catalytically
reacting, e.g., polymerizing, the polymer solids, leaving behind a
support material in keeping with the embodiments herein. According to one
or more embodiments of the present disclosure, such initial processing
does not alter the initial conductivity properties of the support
material; or if altered somewhat, the support material maintains
essentially conductive conductivity characteristics sufficient to achieve
high aspect ratio etching with chemically driven plasma with minimal
twisting deformities.

[0047] As further appreciated from the discussion herein, alteration of
known liquid mixtures and/or the manufacturer's recommended processing
may be useful to most effectively obtain a desired support material. In
addition to composition of the liquid mixture, consideration may be given
to selection of cure temperature and cure time as potentially affecting
composition and/or electrical characteristics of resulting support
materials. For example, curing conditions may influence the type of
bonding and/or cross-linking in the support material. Also, for spin-on
application, consideration may be given to selection of viscosity, spin
speed (revolutions per minute), and dispense volume as affecting
thickness of resulting support materials.

[0048] Curing of the support materials may occur in one or more steps,
stages or processes. An initial cure may be used to transform the
deposited liquid mixture into a solid having conductive electrical
properties. Subsequent curing steps or processes may then effect
additional changes to the support materials composition and/or electrical
characteristics. For example, these electrical characteristic changing
curing steps may include any single step, or combination of steps, of
heating, photon bombardment, irradiation, and/or exposure to
electromagnetic fields, to achieve the desired material electrical
property changes such as reducing conductivity of the support material.

[0049] Whereas initial curing processes to solidify the support material
from a liquid to a solid generally might occur before feature formation
therein, e.g., etching, subsequent curing processes, such as those set
forth above, may be performed after certain features are formed in the
support material. For example, after forming, e.g., etching, an opening
in the solid support material, further processing of the support
material, e.g., curing, may be accomplished to effect a reduction in
conductivity of the support material. After such further processing of
the support material, a capacitor structure may be formed in the opening,
with the capacitor implemented having the now reduced-conductivity
support material isolating container structures.

[0050] Embodiments of the present disclosure are not limited to capacitor
structures. Other integrated circuit structures and features which may
benefit from the advantages which may be realized by etching a material
having more conductive electrical characteristics, and more insulative,
i.e., less conductive, post-etch material electrical characteristics, are
contemplated by the present disclosure. For example, substrates, fins,
structural supports, isolation trenches, floating gate insulators, and
other charge insulating structures and features are all contemplated by
the present disclosure.

[0051] Various formulations of initially-conductive materials, which are
capable of further, e.g., post-etch, processing to reduce material
conductivity are possible. The exact formulation of the mixture may
depend on the features to be formed therein, and the conditions
encountered in processing other materials involved in the semiconductor
fabrication. Support material mixtures having a range or variety of
initial and subsequent conductivity are contemplated.

[0052] For any particular application, the support material mixture has an
initial conductivity large enough to mitigate twisting and other feature
distortions during etching or formation, to the degree required in the
particular application. A particular support material mixture should be
sufficiently easy to etch in oxygen containing plasma via chemically
driven, e.g., O radical, reactions. The support material mixture may be
cured to effect a change of conductivity, e.g., reduction, to a level
sufficient to provide the insulation desired of the particular feature
being formed. For example, a capacitor structure may call for
less-conductive post-etch electrical characteristics than an isolation
structure at one end of a number of memory device structures.

[0053] According to one example embodiment, the initially-conductive
material mixture is a blend of a conductive polymer and a polymeric
carrier "matrix." Certain properties of the blend may be changed by
subsequent processing. For example, a conductivity change, e.g., a
reduction, may be obtained by processing the mixture to cause a
separation of the conductive polymer and the matrix polymer into separate
micelles.

[0054] However, embodiments of the present disclosure are not limited to
such mixtures, and may include any number of constituent polymers and/or
non-polymer materials. Processing used to change conductivity after
etching may rearrange polymer structures of one or more constituents of
the mixture, or may cause micro or macro separation of certain mixture
constituents. For example, heating, irradiation, photon bombardment,
and/or electric and/or magnetic field exposure may be used to break
molecules, and/or to separate the conductive polymer and the matrix
polymer into separate micelles.

[0055] One such blend available from Brewer Science, Inc. of Rolla, Mo.
has an initial resistance of approximately 1 E7 ohms/square, and a
conductivity of approximately 2.5E-3 S/cm (Siemens per centimeter), which
is on the order of crystalline silicon (c-Si) having a conductivity of
approximately 12E-3 S/cm. According to one embodiment of a fabrication
method, the mixture is deposited and initially cured to a solid support
material. The solid support material is etched to form various features,
e.g., one or more capacitor structures. Subsequent to feature formation,
the support material is exposed to a 180 degree C. bake, which increases
the resistance, i.e., reduces the conductivity, of the blend by 4 orders
of magnitude, i.e., 4 decades, to more than 10E11 ohms/square.

[0056] In certain applications and structures, the increase in resistance
to more than 10E11 ohms/square, i.e., reduction in conductivity, may be
sufficient to isolate devices, despite being two to three decades below
the characteristics of SiO2. Additional insulative qualities of the
support material, e.g., higher post-curing resistivity, may be achieved
with other mixtures, and/or by other curing processes such as longer bake
times, higher bake temperatures, among others.

[0057] The reduction in conductivity, i.e., increase in resistivity,
effected by curing is not due to massive thermal degradation, or
volatilization of the support material. Due to the precise nature of
feature formation, loss of mass of the support material is undesirable.
Heating times and/or temperatures, or other curing process parameters,
are maintained within a range that will not result in massive thermal
degradation, or volatilization of the support material. For example with
respect to the blend available from Brewer Science, Inc. described above,
little mass loss occurs at curing temperatures of approximately 196
degrees Celsius, e.g., less than 10% mass loss observed with curing
temperatures less than 196 degrees C. Curing at temperature above 200
degrees Celsius, but less than 475 degrees Celsius, show less than 15%
mass loss.

[0058] According to one particular embodiment, curing of the support
material to effect a reduction in conductivity included heating to at
least 180 degrees C., but to less than 200 degrees C., for up to 30
minutes.

[0059] In further respect to the blend available from Brewer Science, Inc.
described above, curing at lower temperatures than 180 degrees resulted
in less reduction in conductivity for a given time. For example, heating
to 100 degrees C. for 30 minutes resulted in virtually no change in
material resistivity; heating to 120 degrees C. for 30 minutes resulted
in less than one (1) decade change in material resistivity; and heating
to 140 degrees C. for 30 minutes resulted in just slightly more than one
(1) decade change in material resistivity.

[0060] Examples of hard mask material mixtures include BSI.M05068B and
BSI.S07051 of a proprietary composition available from Brewer Science,
Inc. of Rolla, Mo. The former produces an organo-silicate hard mask
material containing about 36 at % carbon while the latter produces an
organo-titanate-silicate hard mask material containing about 22 at %
carbon, with both being insulative. An example of an ARC material mixture
includes BSI.M06089A of a proprietary composition also available from
Brewer Science, Inc. The mixture produces an organic (no titanium or
silicon) ARC material containing about 44 at % carbon, with the coating
being conductive. Examples of known classes of conductive polymers
include poly(acetylene)s, poly(pyrrole)s, poly(thiophene)s,
poly(aniline)s, poly(fluorene)s, poly(3-alkylthiophene)s,
polytetrathiafulvalenes, polynaphthalenes, poly(p-phenylene sulfide), and
poly(para-phenylene vinylene)s.

[0061] According to one or more embodiments, support material 128 can have
a thickness over substrate 112 of, for example, greater than about 1
micrometer (μm). Even so, the thickness might be less than about 3
μm or from 1.5 to 2 μm, according to a particular design rule.

[0062] As the reader will appreciate, the compositions discussed above for
support material 128 and/or the liquid mixtures that might form it have
not previously been considered for such a use. Previously, using silicon
dioxide dielectric for support material provided easy isolation of array
devices from peripheral devices. Also, silicon dioxide generally
withstands subsequent high temperature processing. Consequently, no known
consideration was given to using hydrocarbon-containing support material,
especially if electrically conductive. While providing beneficial etch
capabilities in forming various features, hydrocarbon-containing support
material might not withstand high temperature processing as well and, if
conductive, does not isolate peripheral, or adjacent, devices all by
itself.

[0063] FIG. 2A is a diagrammatic, cross-sectional view of the FIG. 1A
wafer portion 210 shown at a processing stage subsequent to that of FIG.
1A. A plurality of electrically conductive node locations 220, 222, 224
and 226 are shown within memory array region 214 of substrate 212. As
illustrated in the embodiments of FIGS. 2A and 2B, openings 232, 234,
236, 238, 240, 242, 244, 246, 248, 250, 252, 254, etc., are formed
through support material 228 to the node locations associated with an
upper surface of substrate 212, (with node locations 320, 322, 324 and
326 being shown in FIG. 3A). According to one or more embodiments, the
openings can have a high aspect ratio, meaning a ratio of about 20:1 or
greater, e.g., a ratio of 70:1 or greater. The openings can have an
elevation of from about 1 to about 3 μm, and a width of about 60
nanometers (nm) or less. The openings are shown to have circular outer
peripheries (as illustrated by the top view of FIG. 2B), but it is to be
understood that the openings can have other shapes. According to one or
more embodiments, the openings 232, 234, 236, 238, 240, 242, 244, 246,
248, 250, 252, 254, etc., can be used to form containers of capacitor
structures, as the same will be appreciated by one of ordinary skill in
the art.

[0064] According to one or more embodiments, the openings 232, 234, 236,
238, 240, 242, 244, 246, 248, 250, 252, 254, etc., are formed over memory
array region 214 of construction 210 and, while the openings are formed,
a trench 256 is formed within region 216 of construction 210. Although
trench 256 is shown formed simultaneously with the openings over memory
array region 214, and accordingly is shown formed utilizing the same etch
as that used to form the openings, it is to be understood that the trench
can be, in alternative processing (not shown), formed with an etch
separate from that used to form the openings over memory array region
214. Such etch used to form the trench can be conducted either prior to,
or after, the etch used to form the container openings associated with
memory array region 214. As one skilled in the art will appreciate, an
array of memory cells (including associated capacitor structures), may be
surrounded by a trench to provide physical isolation, for example as a
barrier to keep the etchback, e.g., HF acid used with oxide support
material, from attacking the periphery of the array.

[0065] According to one or more embodiments, formation of the container
openings within memory array region 214 and the trench within region 216
may be accomplished by first forming a photoresist mask (not shown) with
photolithographic processing, subsequently transferring a pattern from
the patterned mask to underlying material 228, and removing the patterned
photoresist mask. The photolithographic requirements associated with
formation of the patterned mask can be relatively stringent and,
accordingly, an antireflective coating material (not shown) can be
incorporated into support material 228, formed beneath support material
228, or formed over support material 228. Of course, if support material
228 is itself an anti-reflective coating (ARC) material, then such
measures might be omitted. In one or more embodiments, the ARC material
may include a spin-on film, e.g., a bottom antireflective coating (BARC)
material.

[0066] According to one or more embodiments, the support material 228
initially has relatively conductive electrical characteristics such that
the openings may be anisotropically etched into support material 228. In
such embodiments, the anisotropic etching may use a plasma generated from
a gas composition containing O2 along with SO2, SiCl4,
N2, or N2/CxHyF.sub.z, where x, y, and z are
integers, 0≦x≦6, 0≦y≦4, and
0≦z≦8. Examples of CxHyF.sub.z include
CH2F2, C4F8, C4F6, C6F6
(aromatic), C5F8, etc. One set of possible anisotropic etching
conditions includes supplying O2 and SO2 to an inductively
coupled plasma reactor at a total flow rate of about 50 to about 300
standard cubic centimeters per minute (seem) and a flow rate ratio of
O2 to SO2 of 1:2 to 2:1.

[0067] Another set of possible anisotropic etching conditions includes
supplying O2 and SiCl4 to an inductively coupled plasma reactor
at a total flow rate of about 500 to about 300 seem and a flow rate ratio
of O2 to SiCl4 of about 5:1. In either set, reactor temperature
may be from about 20° to about 100° C. or, more
specifically, from 50° to 70° C. Reactor pressure may be
from about 5 to about 100 milliTorr or, more specifically, from 20 to 40
milliTorr. Power supplied to the top plate may be from about 500 to about
1200 watts (W) or, more specifically, approximately 850 W. Reactor bias
may be from about 20 to about 200 volts or, more specifically,
approximately 110 volts. One example of an inductively coupled plasma
reactor includes a Lam 2300 Kiyo system available from Lam Research
Corporation in Fremont, Calif.

[0068] A further set of possible anisotropic etching conditions includes
supplying O2 and N2 to a capacitively coupled plasma reactor at
a total flow rate of about 100 to about 500 seem and a flow rate ratio of
O2 to N2 of 1:2 to 2:1. A still further set of possible
anisotropic etching conditions includes adding CHxFy, where x
and y are integers from 0 to 4 and the sum of x and y equals 4, to the
O2/N2 gas mixture to provide 10 to 50% of the total flow. In
either set, reactor temperature may be from about 20° to about
100° C. or, more specifically, from 50° to 70° C.
Reactor pressure may be from about 5 to about 100 milliTorr or, more
specifically, from 20 to 40 milliTorr. The reactor may operate at dual
frequency power with a high frequency power of about 200 to about 1000 W
supplied at 27 to 160 megaHertz (MHz) and a low frequency power of about
20 to about 1000 W supplied at 2 to 13.6 (MHz). One example of a
capacitively coupled plasma reactor includes a Lam 2300 Exelan system
available from Lam Research Corporation in Fremont, Calif.

[0069] The properties of support material 228 discussed above, especially
with carbon primarily in the form of an electrically conductive, carbon
backbone polymer, alone or in a blend, e.g., mixture, with a polymeric
carrier matrix, may be expected to allow much higher aspect ratios than
possible in silicon dioxide. The chemical component, as opposed to
physical sputtering component, in anisotropic etching of support material
228 is larger than that of silicon dioxide (SiO2). Such difference
is even more dramatic for carbon backbone polymers. Support material 228
may thus be more effectively anisotropically etched at high aspect
ratios.

[0070] In previous approaches, trench-style capacitors in crystalline
silicon (c-Si) have reported aspect ratios of 70:1, with 100:1
demonstrated in research and development. However, in such approaches a
silicon dioxide (SiO2) support material does not allow nearly as
high of aspect ratios due to the ease with which crystalline silicon
(c-Si) may be removed compared to silicon dioxide (SiO2). As such,
according to one or more embodiments of the present invention, support
material 228 may enable exceeding such aspect ratios given the properties
described herein, which make it more amenable to effective anisotropic
etching than crystalline silicon (c-Si).

[0071] Additionally, spin-on application of support material to a desired
thickness and etching of openings may be integrated into a wider variety
of process flows in comparison to forming trench-style capacitors in
crystalline silicon. Further, for process flows forming buried digit
lines, use of crystalline silicon would involve difficult and expensive
epitaxial growth of the silicon. In the event that support material 228
without titanium and/or silicon produces "bowing" of a feature during
etching, addition of titanium and/or silicon may decrease the lateral
etch rate and help produce a straighter profile.

[0072] According to one or more embodiments, openings 232, 234, 236, 238,
240, 242, 244, 246, 248, 250, 252, 254, etc., are formed in an array
within memory array region 214. Such array comprises rows and columns.
The rows can be considered to extend horizontally in the view of FIG. 2B,
and the columns can be considered to extend vertically in the view of
FIG. 2B. Alternative array arrangements are possible, including
offsetting each row by half of a cell compared to adjacent rows to allow
higher cell density.

[0073] Although openings 232, 234, 236, 238, 240, 242, 244, 246, 248, 250,
252, 254, etc., are described as extending only through support material
228 to underlying conductive nodes, such as nodes 220, 222, 224, and 226
as shown in FIG. 2, it is to be understood that one or more other layers
(not shown) can be provided between the nodes and support material 228
and that the openings can stop on the other layers. For instance, an etch
stop layer (not shown) can be provided between support material 228, in
FIGS. 2A, and nodes 220, 222, 224, and 226, so that the openings stop on
the etch stop layer. That is, an etch stop layer 230 is shown between
support material 228 and region 218 of substrate 212 in FIG. 2A.

[0074] An etch stop layer can protect underlying materials, such as the
surface of substrate 212 and/or electrical devices (not shown) supported
by the surface, during a subsequent removal of support material 228
(discussed below). An etch stop layer may also mitigate effects of etch
non-uniformities, if any. The openings can be extended through the etch
stop and to nodes 220, 222, 224, and 226 with a second etch after the
etch through support material 228. The etch stop can include any suitable
material to which support material 228 can be selectively etched, and
can, for example, be silicon nitride.

[0075] The figures that follow illustrate formation of capacitor
structures in the openings in the support material. However, embodiments
of the present invention are not so limited, and embodiments of the
present disclosure include formation of other microelectronic structures
as well. One skilled in the art will appreciate how aspects of the
illustrated embodiments may be incorporated into the fabrication of other
semiconductor features.

[0076] Following formation of the openings in the support material 228,
such as by etching, further processing, e.g., curing, of the support
material to effect a reduction in conductivity as described above, may be
accomplished either before, during, or after any of the following
capacitor fabrication steps. Depending on the particular application, or
support material composition, or capacitor fabrication techniques, the
supporting material 228 may, for example, be heated to change, e.g.,
reduce, the electrical conductivity properties of the support material.
This processing or curing of the supporting material to have higher
resistivity properties may be accomplished in one or more steps, all at
one time, or in time-segregated processing steps.

[0077] According to one or more particular embodiments, after openings are
formed, the support material is processed to effect a reduction in
conductivity by heating the support material to at least 180 degrees C.,
but to less than 200 degrees C., for up to 30 minutes. Thereafter,
fabrication of the capacitor structures illustrated in the following
figures is accomplished. According to one or more embodiments, the
capacitor structures illustrated in the following figures are fabricated,
and then the support material is processed to effect a reduction in
conductivity as detailed above. According to one or more embodiments, the
support material 228 is subjected to photon bombardment, irradiation,
and/or exposure to electromagnetic fields in addition to, or in lieu of,
the heating process described above in order to effect a change in the
electrical conductivity characteristics of the support material 228.

[0078] As one skilled in the art will appreciate, a conventional
transparent, e.g., amorphous, carbon/anti-reflective coating (TC/ARC)
masking strategy for forming the openings is not compatible with the
heating process having the temperature profile(s) discussed above (used
to reduce the conductivity of the support material). However, it will be
appreciated that a TC is not a suitable masking technique for a polymer
etch. Thus a low temperature ALD (atomic layer deposition) oxide might
function better as the etch mask. Such ALD oxides can be deposited at
temps as low as 50 degrees C. Depending on application, and feature
configuration, an organic spin-on ARC could be used on top of the oxide
if needed for photo resolution.

[0079] FIG. 3A is a diagrammatic, cross-sectional view of the FIG. 2A
wafer portion 310 shown at a processing stage subsequent to that of FIG.
2A. A plurality of electrically conductive node locations 320, 322, 324
and 326 are shown within memory array region 314 of substrate 312. In the
embodiments of FIGS. 3A and 3B, a conductive material 360 is formed
within openings 332, 334, 336, 338, 340, 342, 344, 346, 348, 350, 352,
354, etc., as well as within trench 356. Electrically conductive material
360 can be a homogeneous composition of electrically conductive material,
or can comprise multiple layers of electrically conductive material. The
electrically conductive materials within material 360 can comprise any
suitable materials, including, for example, metal, metal compounds, and
conductively-doped silicon. For example, conductive material 360 may
include titanium, titanium nitride, platinum, tungsten, silicon,
ruthenium, etc.

[0080] According to one or more embodiments, portions of conductive
material 360 within the openings in memory array region 314 can be
considered to form container structures within the openings. For
instance, FIG. 3A shows the portions of conductive material 360 within
openings 340,342, 344 and 346 corresponding to container structures 362,
364, 366 and 368. The container structures can be considered to include
inner surfaces 370 within the openings and outer surfaces 372 laterally
opposed to the inner surfaces. The outer surfaces 372 are shown in
contact with, and extending along, support material 328 in FIG. 3A.
However, other materials (not shown) might be formed between outer
surfaces 372 and support material 328.

[0081] According to one or more embodiments, portions of conductive
material 360 may ultimately be incorporated into a capacitor electrode,
for example, a capacitor storage node. Accordingly, conductive material
360 may be referred to as capacitor electrode material, or as capacitor
storage node material.

[0082] In the embodiment of FIGS. 3A and 3B, conductive material 360 is
only shown to partially fill openings 332, 334, 336, 338, 340, 342, 344,
346, 348, 350, 352, 354, etc., and thus forms container structures within
the openings. Alternatively, conductive material 360, either alone or in
combination with other conductive materials, can completely fill the
openings to form pedestal (or post) structures within the openings. The
structures formed from conductive material 360 in the openings, i.e., the
container structures or pedestal structures, can be referred to as
capacitor structures, since they may ultimately be incorporated into
capacitors.

[0084] According to one or more embodiments, as shown in FIGS. 4A-4C, the
remaining support material 428 is not intentionally removed. However,
embodiments of the present invention are not so limited, and certain
portions of the remaining support material 428 may be removed to further
form other topographical structures (see further discussion below with
respect to FIGS. 5A-5C).

[0085] As shown in FIGS. 4A-4C, the support material 428 remains opposing
outer surfaces 472 of the capacitor structures (such as, for example, the
container structures 462, 464, 466 and 468 of FIG. 4A). According to one
or more embodiments, in FIGS. 4A-4C, support material 428 remains over a
portion of memory array region 414. Additionally, according to one or
more embodiments, support material 428 remains integral with, or
adjacent, outer surfaces 472.

[0086] In the embodiment of FIGS. 4A-4C, support material 428 also remains
over region 416 and peripheral region 418. Other steps may be taken, as
necessary, to protect support material 428 over region 416 and/or
peripheral region 418. Such protection may depend on whether or when
support material 428 undergoes the changes to its electrical conductivity
characteristics described above.

[0087] Conductive material 460 associated with individual containers shown
in the embodiment of FIGS. 4A-4C bear the shape of an annulus or a ring.
It is to be understood, however, that material 460 may be formed in
different shapes. Also, as discussed previously, material 460 (alone or
in combination with other conductive materials) may be in the shape of a
pedestal instead of being in the shown shape of a container.

[0088] According to one or more embodiments of the present disclosure, the
electrical conductivity properties of support material 428 are reduced at
some point in the fabrication process, and thus, avoiding the need to
remove the support material which might require wet or dry stripping. An
example of removing the support material is provided in co-pending,
commonly assigned U.S. application Ser. No. 11/971,138, entitled,
"Capacitor Forming Methods", having common inventorship, filed Jan. 8,
2008. The reader will appreciate certain advantages and efficiency can be
gained by the methods of the present disclosure over techniques which
involve removing the support material.

[0089] Often, high aspect ratio structures, such as shown in the Figures,
are provided with retaining structures to reduce toppling during
processing. For simplicity, retaining structures are not shown herein but
may be included according to known techniques.

[0090] FIG. 5A is a diagrammatic, cross-sectional view of the FIG. 4A
wafer portion 510 shown at a processing stage subsequent to that of FIG.
4A. A plurality of electrically conductive node locations 520, 522, 524
and 526 are shown within memory array region 514 of substrate 512. In the
embodiment of FIGS. 5A-5C, a dielectric material 572 and a conductive
material 574 are formed within openings 532, 534, 536, 538, 540, 542,
544, 546, 548, 550, 552, 554, etc. Conductive material 560 of the
capacitor container structures can be referred to as a first capacitor
electrode, and conductive material 574 can be referred to as a second
capacitor electrode. The capacitor electrodes 560 and 574, together with
dielectric material 572, form an array of capacitor structures, 562, 564,
566, and 568, within the array of openings 532, 534, 536, 538, 540, 542,
544, 546, 548, 550, 552, 554, etc. The openings, together with trench
556, are shown in phantom view in FIG. 5C to indicate that such are below
conductive material 574 in the shown view. Although the shown capacitors
are container capacitors, it is to be understood that in alterative
embodiments the capacitors can also be pedestal capacitors, i.e., can
comprise the dielectric material 572 and the conductive material 574
extending around pedestals of material 560.

[0091] According to one or more embodiments, additional portions of the
remaining support material 528 may be removed after the openings, e.g.,
532, 534, 536, 538, 540, 542, 544, 546, 548, 550, 552, 554, etc., and
trench, e.g., 556, have been formed. For example, certain portions of the
remaining support material 528 may be removed over the memory array
region 514, but left intact in the peripheral region 518. According to
one or more embodiments, portions of the remaining support material 528
may be removed before and/or after deposition and isolation, e.g., via
CMP, of a lower capacitor cell plate, e.g., conductive material 560, to
form double-sided containers. The portions of the remaining support
material 528 may be removed in one or more removal steps. Thereafter, a
dielectric, e.g., dielectric material 572, and an upper cell plate, e.g.,
conductive material 574, may be deposited so as to wrap around both sides
of the double-sided container. One skilled in the art will appreciate
that support material, e.g., 528, may still be left intact in the
peripheral region 518 (as shown in FIGS. 5A-5B) to facilitate further
circuit integration features. Fabrication of a capacitor structure using
a double-sided container is further illustrated in FIGS. 6-8.

[0092] FIG. 6 is a diagrammatic, cross-sectional view of a wafer portion
shown at a processing stage subsequent to that of FIG. 2A of an
embodiment including formation of one or more double-sided containers. A
plurality of electrically conductive node locations 620, 622, 624 and 626
are shown within memory array region 614 of substrate 612. As one skilled
in the art will understand, a multiple sided container, e.g., a
double-sided container, may be used to fabricate a capacitor structure
with greater plate surface area, thus enabling greater capacitance in a
single device.

[0093] As shown in FIG. 6, a portion of the support material 628, e.g.,
between openings 642 and 644, is removed to a desired depth, for example
to provide adequate room above the area in which one or more double-sided
container structures are being formed to achieve desired deposition
distribution, and/or to accommodate certain structural features, and/or
in light of other processing constraints.

[0094] A conductive material 660 is formed within openings 640, 642, 644,
646, etc., as well as within trench 656. Electrically conductive material
660 can be a homogeneous composition of electrically conductive material
660, or can comprise multiple layers of electrically conductive material
(as was described above with regards to conductive material 360 in
conjunction with FIGS. 3A and 3B).

[0095] Embodiments of the present invention are not limited to having to
include the first additional removal of the support material 628 before
forming the first cell plate, e.g., electrically conductive material 660.
This step may be optional in certain fabrication processes, and/or
capacitor configurations. Thus, according to one or more embodiments,
this first additional removal of the support material 628, which
effectively reduces the vertical surface area on which electrically
conductive material 660 may be formed within openings 642 and 644, is
omitted.

[0096] According to one or more embodiments, portions of conductive
material 660 within the openings in memory array region 614 can be
considered to form one or more container structures, and/or one or more
double-sided container structures within the openings. For instance, FIG.
6 shows the portions of conductive material 660 within openings 640 and
646 corresponding to container structures 662 and 668, and within
openings 642 and 644 corresponding to a double-sided container
structures, e.g. 865 and 867 shown in FIG. 8, to be subsequently
fabricated from container structures 664 and 668.

[0097] Although two double-sided container structures are shown being
fabricated in FIGS. 6-8, embodiments of the invention are not so limited,
and may include any number of container structures, any number of
double-sided container structures, and/or any number of each in
combination. Although both single-sided and double-sided container
structures are shown being fabricated together in FIGS. 6-8, embodiments
of the invention are not so limited, and a memory array may be formed
using exclusively double-sided capacitor structures, surrounded by a
trench, for example.

[0098] The container structures, including those that will ultimately be
fabricated into double-sided container structures, can be considered to
include inner surfaces 670 within the openings and outer surfaces 672
laterally opposed to the inner surfaces 670. The outer surfaces 672
contact and extend along support material 628. However, other materials
(not shown) might be formed between outer surfaces 672 and support
material 628. According to one or more embodiments, portions of
conductive material 660 may ultimately be incorporated into a capacitor
electrode, for example, a capacitor storage node (as is shown in the
figures that follow). Accordingly, conductive material 660 may also be
referred to as capacitor electrode material, or as capacitor storage node
material.

[0099] In the embodiment of FIG. 6, conductive material 660 is only shown
to partially fill openings 640, 642, 644, 646, etc., and thus forms the
container structures within the openings. Alternatively, conductive
material 660, either alone or in combination with other conductive
materials, can completely fill the openings to form pedestal (or post)
structures within the openings. The structures formed from conductive
material 660 in the openings, i.e., the container structures or pedestal
structures, can be referred to as capacitor structures, since they may
ultimately be incorporated into capacitors.

[0100] FIG. 7 is a diagrammatic, cross-sectional view of a wafer portion
shown at a processing stage subsequent to that of FIG. 6 of an embodiment
including further processing towards formation of double-sided container
structures, i.e., having not only the inner surfaces 770, but also at
least one outer surface 772 of a container structure configured such that
conductive material 760 may be formed thereon. A plurality of
electrically conductive node locations 720, 722, 724 and 726 are shown
within memory array region 714 of substrate 712. Once the conductive
material 760 layer is formed on the support material, e.g., 628 shown in
FIG. 6, for each container structure, e.g., 762, 764. 766, and 768, the
support material 728 between container structures 764 and 768 is removed
as shown in FIG. 7, for example by forming another opening, e.g., 743,
between the conductive material 760 layers of container structures 764
and 766.

[0101] Opening 743 may be formed either before, or after, support material
is cured by the methods discussed above to effect a reduction in
conductivity. As one skilled in the art will appreciate, opening 743 may
be formed using wet etch, or dry etch, techniques (among others), as may
be appropriate to the conductivity of the support material at the time it
is being removed. The forming of opening 743 exposes opposing outer
surfaces 772 of container structures 764 and 766. As discussed above, the
unsupported conductive material 760 layers may, or may not, be of a
shorter vertical dimension than the conductive material 760 layers formed
on, or adjacent to, the support material 728 between other container
structures, e.g., between container structures 762 and 764, and between
container structures 766 and 768.

[0102] FIG. 8 is a diagrammatic, cross-sectional view of a wafer portion
shown at a processing stage subsequent to that of FIG. 7 of an embodiment
including formation of one or more double-sided containers. A plurality
of electrically conductive node locations 820, 822, 824 and 826 are shown
within memory array region 814 of substrate 812. According to one or more
embodiments, a dielectric material 872 and a conductive material 874 are
formed within openings 840, 842, 843, 844, 846, etc., including over the
top of the unsupported conductive material 860 layer bounding opening
843, as shown in FIG. 8. The dielectric material 872 and conductive
material 874 may be formed over the remaining exposed top portions of
remaining support material 828 (as shown) such that the dielectric
material 872 and a conductive material 874 layers are common to all
container openings, including double-sided container openings. However,
embodiments of the present disclosure are not so limited, and according
one or more embodiments, the dielectric material 872 and a conductive
material 874 layers are not extended over the exposed top portions of
remaining support material 828 between openings of one or more
containers.

[0103] Conductive material 860 of the capacitor container structures can
be referred to as a first capacitor electrode, and conductive material
874 can be referred to as a second capacitor electrode. The capacitor
electrodes 860 and 874, together with dielectric material 872
therebetween, form number of capacitor structures, e.g., 862 within
opening 840 and 868 within opening 846, and form a number of double-sided
capacitor structures, e.g., 865 within openings 842 and 843, 867 within
openings 843 and 844. Although the capacitor structures illustrated in
FIG. 8 include capacitors formed using container structures and
capacitors formed using double-sided container structures, it is to be
understood that in alterative embodiments the various capacitors can also
be pedestal capacitors, i.e., can comprise the dielectric material 872
and the conductive material 874 extending around pedestals of material
860.

[0104] According to one or more embodiments of the present disclosure,
subsequent to the above-described etching and/or support material removal
steps, any remaining support material, e.g., 828, may be cured by the
methods discussed above to effect a reduction in conductivity. In this
manner, isolation between discrete capacitor structures may be achieved
without removing and replacing the support material used to form openings
for the container structures and double-sided container structures.
However, embodiments of the present disclosure are not so limited. For
example, according to one or more embodiments, support material may be
cured by the methods discussed above to effect a reduction in
conductivity before support material, e.g., 728 in FIG. 7, is removed to
form an opening, e.g., 743 in FIG. 7, as part of double-sided container
fabrication.

[0105] According to one or more embodiments, transistor structures may be
formed using similar techniques as described above with respect to
capacitor structures. For example fin structures, e.g., for fin MOSFETs,
fin FETs, and other vertical and horizontal transistor configurations,
may be fabricated, e.g., etched, into a conductive support material,
which is subsequently processed to effect a conductivity change to
appropriately isolate such structures from one another or other devices.
The reader will appreciate; the transistor devices and capacitor
structures formed in accordance with the methodology described herein can
be incorporated together into an array of memory cells, e.g., DRAM cells,
SRAM cells, SDRAM cells, among others suitable high aspect ratio (HAR)
uses. Embodiments of the present invention are not so limited.

CONCLUSION

[0106] The present disclosure includes methods, capacitors, and high
aspect ratio (HAR) structures, e.g., contacts. One method embodiment
includes a capacitor forming method includes forming an electrically
conductive support material over a substrate, forming an opening through
at least the support material to the substrate where the support material
has a thickness and the opening has an aspect ratio of at least 20:1
within the thickness of the support material. After forming the opening,
the method includes forming a capacitor structure contacting the
substrate and the support material in the opening. The method includes
effecting a phase change to the support material with the support
material containing at least 25 at % carbon.

[0107] Although specific embodiments have been illustrated and described
herein, those of ordinary skill in the art will appreciate that an
arrangement calculated to achieve the same results can be substituted for
the specific embodiments shown. This disclosure is intended to cover
adaptations or variations of one or more embodiments of the present
disclosure. It is to be understood that the above description has been
made in an illustrative fashion, and not a restrictive one. Combination
of the above embodiments, and other embodiments not specifically
described herein will be apparent to those of skill in the art upon
reviewing the above description. The scope of the one or more embodiments
of the present disclosure includes other applications in which the above
structures and methods are used. Therefore, the scope of one or more
embodiments of the present disclosure should be determined with reference
to the appended claims, along with the full range of equivalents to which
such claims are entitled.

[0108] In the foregoing Detailed Description, some features are grouped
together in a single embodiment for the purpose of streamlining the
disclosure. This method of disclosure is not to be interpreted as
reflecting an intention that the disclosed embodiments of the present
disclosure have to use more features than are expressly recited in each
claim. Rather, as the following claims reflect, inventive subject matter
lies in less than all features of a single disclosed embodiment. Thus,
the following claims are hereby incorporated into the Detailed
Description, with each claim standing on its own as a separate
embodiment.