Synopsys, Inc. (Nasdaq:
SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today unveiled a new initiative to accelerate the verification of mixed-signal system-on-chip (SoC) designs. Launched today are the initial components of the initiative, which include a SystemVerilog-based methodology, AMS Testbench, and the new VCS® AMS mixed-signal verification solution that incorporates VCS functional verification and the CustomSim™ FastSPICE simulator. The VCS AMS solution enables advanced functional and low-power verification combined with industry-best performance and capacity for faster mixed-signal SoC regression testing.

Consumer electronics continue to drive technology convergence. As a result, a growing proportion of SoCs include digital and analog blocks from internal and third-party IP sources. The increasing use of sub-nanometer geometries also introduces process variations that increasingly affect circuit performance. The time and compute power required to verify these complex mixed-signal SoCs may exponentially increase the total cost of design. By deploying Synopsys' VCS AMS mixed-signal verification solution, design teams can achieve the throughput and accuracy they require to simulate today's complex mixed-signal SoCs. However, as mixed-signal SoC complexity grows, there is a new verification crisis on the horizon that requires additional focus on the overall verification methodology.

"Our mixed-signal designs are targeted at automotive and industrial applications that are increasingly dependent on intelligent, sensor-based SoC solutions," said Dirk Behrens, vice president of Automotive at Micronas. "To ensure high reliability, we must expand the role of proven advanced verification techniques from the digital domain to enable effective regression of our mixed-signal designs. Synopsys is leading the way by extending industry-standard SystemVerilog-based methodologies to address mixed-signal verification, enabling us to verify our designs faster and more thoroughly."

"At Rambus, we continue to advance our memory and interface IP cores with improved power efficiency and increased performance. As a result we face a growing challenge achieving adequate verification coverage for our complex mixed-signal I/O designs," said Anand Gopalan, senior director of engineering for Rambus, Inc. "We are committed to providing the best possible IP core solutions and the Synopsys VCS AMS mixed-signal verification solution and coverage-driven verification methodology allows us to achieve even higher levels of verification productivity and quality."

Coverage-driven digital-centric verification methodologies, such as the industry-standard Universal Verification Methodology (UVM), are broadly deployed. Such methodologies enable rapid development of constrained-random testbenches that can be run in parallel across compute farms to reduce overall turnaround time. Synopsys' AMS Testbench methodology removes a major productivity barrier in mixed-signal verification by extending these advanced techniques beyond the digital domain. Among the extensions provided with AMS Testbench are: constrained-random stimulus for analog signals; shaped source voltage generators; analog checkers and assertions; reference model integration with multiple abstraction levels, including SPICE and SystemVerilog; analog node sampling and monitoring; electrical-to-real data converters; SystemVerilog real number modeling; and analog functional coverage. Synopsys' AMS Testbench methodology extensions are complemented by native integration of advanced functional and low-power verification technologies available with the VCS AMS solution to boost throughput. Among the native technologies enhanced for mixed-signal verification are voltage-aware simulation driven by UPF-defined power intent specifications, SystemVerilog real number modeling and assertion checking. By building on the proven UVM standard, AMS Testbench enables design teams to rapidly extend their existing verification environments for mixed-signal SoC regression testing.

"The development of targeted methodologies and techniques is an essential requirement to address the design community's growing mixed-signal SoC design verification productivity and quality challenges," said Bijan Kiani, vice president of product marketing at Synopsys. "Based on key insights gained in working closely with our customers, Synopsys has developed many advanced verification technologies and integrated them into our simulator engines to deliver industry-best performance. Our mixed-signal verification initiative includes extensions to these technologies for mixed-signal applications and couples them with an advanced methodology to accelerate the on-time delivery of high-quality, reliable mixed-signal SoCs."

Availability

The VCS AMS mixed-signal verification solution provides access to VCS functional verification and the CustomSim FastSPICE simulator, and is expected to be available in calendar Q2 of 2014. VCS AMS is fully compatible with the recently announced
Verification Compiler™ product.

Synopsys, Inc. (Nasdaq:
SNPS) accelerates innovation in the global electronics market. As a leader in electronic design automation (EDA) and semiconductor IP, Synopsys delivers software, IP and services to help engineers address their design, verification, system and manufacturing challenges. Since 1986, engineers around the world have been using Synopsys technology to design and create billions of chips and systems. Learn more at
www.synopsys.com.