STOP! Are You Gambling On Your Memory IP?

Introduction
Kilopass (www.kilopass.com) and Sidense (www.sidense.com) both license one-time programmable (OTP) memory intellectual property (IP). These companies are currently in litigation with each other with regard to allegations of patent infringement.

Why should you be interested? Well, if you are building a new chip and you are licensing memory IP, you really need to have a high level of confidence that the IP you are licensing does not violate someone else's patents; otherwise you might find yourself in court at some stage.

To be honest, the legal part of all of this is something of a morass that will make your brain ache and your eyes water, but there's a lot of other stuff here that I think you will find to be of interest, including the underlying technology, the back story as to how all of this came about, and the ins-and-outs of the patent and patent litigation process. So, keeping all of this in mind, let us plunge into the fray with gusto and abandon...

Who Needs OTP Memory?As a starting point, let's first consider who needs one-time programmable (OTP) memory, which basically means that once you've programmed it that's it – there's no going back. After all, if no one wants to use this technology then patents become something of a non-issue. If you'd asked me a couple of weeks ago, I would have said that almost any other form of memory (SRAM, DRAM, Flash, etc.) was more interesting that OTP... how little I knew!

The first thing is that many chips need some sort of non-volatile (NV) memory that retains its contents when power is removed from the system. This sort of memory is of interest for all sorts of things, from storing security keys to boot code, firmware, application software, and so forth. Ideally, we also need something that is compatible with a standard CMOS fabrication process, because this will be cheaper to manufacture and it will be available on the market much faster than a technology that requires additional processing steps (traditional Flash and antifuse technologies typically lag the latest and greatest standard CMOS process by at least one technology node).

Now, there are esoteric NV technologies like FRAM (Ferroelectric RAM), MRAM (Magnetic RAM), and PCM (Phase Change Memory), but these are currently relegated to niche markets. Generally speaking, the mainstay of the NV market is dominated by the Flash and – to a lesser extent – E2PROM technologies, both of which are based on the concept of a floating gate as illustrated in Figure 1.

Figure 1. A Flash/E2PROM floating gate transistor.

Obviously this is a gross simplification (not the least that I’m not showing any of the terminals connected to the transistor), but it will suffice our purposes here. In its un-programmed state, the floating gate has no effect and the standard gate can be used to turn the transistor on and off as for a regular MOS transistor. By one means or another, however, it is possible to coerce electrons into the floating gate, in which case they will block the action of the standard gate. This can be used to determine if the transistor has been programmed or not; in turn, this can be used to reflect logic 0 or 1 values.

The advantage of the floating gate approach used in Flash and E2PROM memories is that – in addition to being non-volatile – this form of transistor can be cleared and reprogrammed over and over again. There are disadvantages, however, including the fact that creating these transistors requires additional processing steps to augment the standard CMOS process (anywhere from 4 to 30 layers may be required depending on the specific process and application). Also, additional transistors are required to perform the clearing and reprogramming operations. Yet another problem is that if a chip containing this form of memory is heated to 150 to 175°C – as can easily happen in harsh environments like automobile engines and industrial/enterprise and aerospace/defense applications – the electrons in the floating gate can acquire enough thermal energy to become mobile; in this case the floating gate starts to lose its charge and the chip "forgets" what's going on.

The alternative is to use OTP memory based on some form of antifuse. This has several advantages, including that fact that even if you take the chip apart and use a scanning electron microscope, it's virtually impossible to reverse-engineer which cells have and have not been programmed. Also, this form of memory can survive extremely harsh environments while still retaining its programmed state.

We will look at the actual physical implementation of OTP antifuse-based memory cells in a moment, but first let's consider who needs this form of memory. Actually, I was amazed to discover how popular this type of memory is. Over the last couple of years, OTP antifuse-based memory has started to see exponential growth and is becoming prolific in many market segments. A few examples are as follows:

Consumer: OTP memory is huge in things like set-top box (STB) applications where it's used for security keys, ROM patching and ROM replacement, in media processors, and in audio/video demodulators. OTP memory is also useful for storing boot and program code for things like display drivers and capacitive touch sensors.

Mobility: Mobile phones have evolved into "mobile everything." Modern mobile devices can require megabits of NV memory to store embedded boot code and program code. In many cases form factor and weight are paramount. It used to be that Flash/E2PROM was the only game in town; now OTP memory is becoming increasingly attractive.

Analog/Mixed-Signal: In the case of things like power amplifiers, CMOS image sensors, baseband processors, radio frequency (RF) transceivers, and power management ICs, OTP memory is widely used for calibration and trimming and parametric yield recovery.

Automotive: The deployment of infotainment (information delivery and entertainment systems) in automobiles has exploded over the last few years. Connectivity chips, MCUs, and audio and video DSPs, for example, all require proprietary keys and secure boot code for which OTP memory offers an ideal solution.

Industrial/Enterprise: The use of OTP memory is increasing dramatically in many forms of industrial and enterprise applications, from communications chips to devices used in surveillance cameras.

Aerospace/Defense: This is a tricky one, because these folks have started to use a lot of OTP, but no one really knows what for.

And the list goes on... One point I found particularly interesting was with regard to security in aerospace/defense applications. In order to protect sensitive algorithms stored in memory chips, it was not unknown for certain equipment to be equipped with small explosive charges, which could be detonated in an emergency situation.

Now, I don’t know about you, but when I'm using a piece of electronic equipment I personally prefer that it does not include high explosives. In the case of the modern OTP antifuse-based memory technology discussed in the next topic, each cell represents a logic 0 by default and the cell can be programmed to represent a logic 1. The point is that equipment using these devices can be created in such a way as to self-destruct by simply programming all of the cells in the memory to contain logic 1s. This has my vote over explosives every time!

Antifuses for the 21st Century Many of the early simple programmable logic devices were based on fusible-link technologies. When you purchased a device based on fusible links, all of the fuses were initially intact. By selectively applying pulses of relatively high voltage and current, it was possible to selectively remove undesired fuses, thereby programming the device. The alternative is to use links based on antifuses. In its un-programmed state, an antifuse has such a high resistance that it may be considered to be an open circuit (a break in the wire). However, antifuses can be selectively "grown" (programmed) by applying pulses of relatively high voltage and current. Both fusible-link and antifuse technologies are classed as being one-time programmable (OTP), because once you've blown a fuse or grown an antifuse there's no changing your mind and going back.

The early antifuses were relatively large and "clunky". The way I tend to visualize this is that an old-fashioned antifuse starts life as a microscopic column of amorphous (non-crystalline) silicon linking two metal tracks as illustrated in Figure 2(a).

Figure 2. Growing an old-fashioned antifuse.

In its un-programmed state, the amorphous silicon acts as an insulator with a very high resistance in excess of one billion ohms. The act of programming this particular element effectively "grows" a link by converting the insulating amorphous silicon into conducting polysilicon as illustrated in Figure 2(b). As usual, this figure is a gross simplification, not the least that we've omitted the big, chunky transistors required to grow (program) the antifuse and so forth. Also, creating this form of antifuse requires additional process steps on top of a standard CMOS process.

Now let's get just a little technical. Rather than create a cumbersome antifuse as discussed above, we would ideally like to create a small memory cell using a single MOS transistor based on a standard CMOS process and to be able to program that transistor to reflect a non-volatile logic 0 or logic 1. This simply wasn't possible until the beginning of the 2000s due to the sizes and thicknesses of the structures used to form silicon chips. Using a 500nm process, for example, the breakdown voltage of the oxide layer was significantly greater than the breakdown voltage of the junction. What this meant in real terms was that, before you managed to breakdown a transistor's oxide layer, everything else surrounding that transistor (charge pumps, sense amps, etc.) would be destroyed, which sort of defeats the purpose of doing it in the first place.

Figure 3. Junction vs. oxide breakdown voltages.

At some point on the way down to the 180nm technology node, however, things swapped over as illustrated in Figure 3. That is, the breakdown voltage of the oxide layer became smaller than the junction breakdown voltage. This meant that it was possible to apply enough voltage to break down the oxide without breaking down any surrounding transistors. In turn, this paved the way to create a new form of antifuse. All that was required was for someone to realize it...

But let's not go there just yet. For the moment, let's simply note that both Kilopass and Sidense arrived at what is known as a two-terminal, 1T (one transistor), split-channel structure as illustrated in Figure 4. (Personally I would have thought this should have been called a "split-gate" but that term has become associated with Flash technology, so maybe that's why "split-channel" is used here ... or maybe it's because the act of programming the transistor effectively “splits” the channel.)

Figure 4. Structure of a 1T split-channel OTP transistor.

In its un-programmed state this looks like a slightly unusual flavor of a standard MOS transistor as illustrated in Figure 4(a). The unusual element is that part of the gate oxide is very thin and part is thicker. Programming the device is achieved by applying sufficient potential to break down the gate oxide as illustrated in Figure 4(b), in which case the result behaves like a resistor or a diode depending on your point of view. For reasons that are beyond the scope of these discussions, but that appear intuitively obvious when you look at the illustration, the programmed region will be located at the point where the oxide layer changes thickness.

Interestingly enough, Kilopass describes this as using a non-standard CMOS process, while Sidense boast that they use a standard CMOS process. Initially I was a little puzzled by this, but it actually makes sense; technically they are both right in one way and both wrong in another. The thing is that the transistors used to form the logic cells in the core of a standard CMOS chip have a thin layer of gate oxide. Meanwhile, the transistors used to form the device's input/output (I/O) cells require a thicker layer of gate oxide. I didn’t know this before, but the way this is achieved is to first deposit (and etch etc.) a thin layer of oxide on all of the transistors forming both the logic and I/O cells, and to then deposit an additional layer of oxide only on the transistors forming the I/O cells.

In the case of a chip boasting 1T split-channel OTP transistors as illustrated in Figure 4, the step used to deposit the additional layer of oxide on the transistors forming the I/O cells is also used to create the thicker part of the gates in the OTP transistors. Thus, the reason Sidense can refer to this as being based on a standard CMOS process is that it doesn’t actually involve any additional process steps. Meanwhile, the reason the more-pedantic folks at Kilopass are correct in saying that this is not a standard CMOS process is that we don’t typically deposit thick oxide layers in the logic cell portion of the device (DRC violations will occur and we will have to get exemptions from the foundry), which means the transistor illustrated in Figure 4 will not appear in a foundry's standard cell library.

The Litigation LandscapeAs illustrated in Figure 5, in addition to the litigants themselves, there are four main players that US-based companies need to consider when contemplating litigation against their non-US-based counterparts.

Figure 5. The key players in the litigation landscape.

As usual, the following will be a gross simplification based on my meager understanding of what's going on, but I think it will be sufficient for us all to make sense of it.

The USPTO: We start with the United States Patent and Trademark Office (USPTO). These folks award patents and reexamine patents and rule on the validity of patents, but they do not concern themselves with, or rule on, any commercial consequences associated with a patent. Any action like appealing or revisiting a patent will cost each of the litigating parties around $100K (all monetary amounts in this paper are assumed to be in US dollars).

The US Courts: The court has no jurisdiction over a patent per se. All the court cares about are infringements to a patent. It’s the court's job to rule on damages, penalties, and other remedies. The whole process can take two or three years or more to litigate and an average patent case may cost anywhere between $1 million and $10 million depending on the number of appeals (it can cost much, much more in certain cases), and this doesn’t include any damages paid to the plaintive. Actually, this raises an important point in that if you unknowingly infringe a patent, then you are subject to whatever damages are awarded by the court; however, if you willfully infringe a patent, then any damages you owe to the plaintive are tripled.

The ITC: The International Trade Commission (ITC) cares about infringement of a patent in a different context to the courts. The ITC's duty, first and foremost, is to protect the interests of American commerce and American companies. One way they do this is to prevent products from coming into the country if those products are deemed to infringe patents held by American companies. The reason this is of interest here is that Sidense is a Canadian company as are some of its customers. The good news (for the American company bringing the action) is that if you bring an action before the ITC, then you are reasonable sure to receive an answer one way or the other in 12 to 15 months. Once again, however, this isn’t cheap; taking ITC litigation through trial can easily cost $10M or more.

Foreign Jurisdiction: This involves perusing patent litigation through the courts in other countries. Japan is of particular interest with regard to the litigation between Kilopass and Sidense because (a) Kilopass holds a Japanese patent for its 1T OTP memory cell technology and (b) a number of Japanese companies are using 1T OTP memory IP from Sidense.

It's important to note that the discussions above are not intended to imply that Kilopass intends to bring either the ITC or Foreign Jurisdictions into play – only that these are possibilities that a company in Kilopass's position may wish to consider.

Who Did What When?This is where things start to get a little tricky, which is why lawyers get paid the big bucks, so what follows is a "30,000-foot view." As we have already discussed, the two companies involved in this dispute are Kilopass and Sidense. We also need to introduce two of the key players: Jack Peng, founder and former CEO of Kilopass, and Wlodek Kurjanowicz, founder and current CTO of Sidense. Both of these guys have had long and illustrious careers. Suffice it to say that, prior to founding Kilopass in 2001, Jack was working with Flash-based FPGAs at Actel; and prior to founding Sidense in 2003, Wlodek was working on DRAM technology at MoSys.

When the gate oxide breakdown voltage fell below the junction breakdown voltage around the beginning of the 2000s, a new form of 1T antifuse-based OTP memory was an idea waiting to happen, so it's not surprising that two people might independently realize the potential of single-transistor OTP memory based on gate-oxide breakdown. Of course it's also not surprising that one of them would come up with the idea before the other.

We will probably never know the nitty-gritty details of who thought of what when. Ideas like this rarely spring into life in their full and final form; instead, they typically evolve over some period of time. What we do know as a matter of public record is that, since they were formed, both companies have filed a bunch of patents. At the time of this writing, Kilopass, for example, currently has a total of 57 patents applied for around the world, 5 of which are related to 1T technology. Of these 57 patents, 26 are in the US and, of these, 21 have been granted thus far. In particular, Kilopass applied for US patent 6,777,757 on a 1T antifuse-based memory cell in April 2002 and this patent was granted in August 2004. Meanwhile, Sidense claims over 70 patents granted or pending. In particular, Sidense applied for US patent 7,402,855 on a 1T antifuse-based memory cell in May 2005 and this patent was granted in July 2008. In May 2010 Kilopass filed an action to invalidate Sidense's ‘855 patent, but in Jan 2011 the USPTO affirmed an amended version of the ‘855 patent (Kilopass say they intend to appeal).

As an aside, it’s interesting to note that Kilopass never actually brought their 1T technology to the market; instead they decided to focus on a 2T technology that is absolutely based on a standard CMOS process, because they could bring this to the market faster and with less risk. However, Kilopass says that the fact that they didn’t market their 1T technology is irrelevant – the example they use is that if you own a car that's sat in your driveway, you may decide to take the car for a spin or you may decide to leave it standing. But even if you do leave your car doing nothing in your driveway, this doesn’t mean that your neighbor can wander over and drive off in it.

With regard to the litigation itself, the folks at Kilopass told me that they sent a letter to Sidense in 2005 saying "We believe you’re infringing our patent," and Sidense essentially wrote back saying "No we’re not." So why did Kilopass leave it until 2010 before formally bringing action against Sidense for patent infringement? The bottom line is that – as we discussed in the previous topic (The Litigation Landscape) – this sort of thing costs a lot of money and, as a small start-up company, Kilopass simply couldn’t afford it at the time.

In 2008 Charlie Cheng came on board as the new CEO at Kilopass. This was in the depths of the recent economic downturn, and Charlie had to make some harsh decisions, including reducing the workforce from 65 to 23 employees (now things are on the upswing the company has grown back to 40+ employees). Charlie also dramatically changed the company's business strategy in several directions. First, he extended Kilopass's foundry base from only TSMC to include a host other foundries. Later, in 2010, Kilopass branched out into a new 2T OTP memory product called Gusto.

The result of all this was that 2009 and 2010 were good years for Kilopass and, since sufficient funds were coming in, Charlie felt that Kilopass was now in a position to enforce its 1T patents. Of course it would be easy for people to portray Charlie as the bad guy in all of this – after all he's the one who decided to take Kilopass into battle. However, Charlie has been on both ends of the patent litigation process. In a previous company, Charlie was involved in the creation of a product that he says delivered great value to a group of customers that had been largely ignored, but someone else claimed patent infringement and shut them down. At that time Charlie thought this was extremely unfair, but now that he's on the other side of the process he says that it's his duty to do what’s right for the company, the investors, and the customers.

So where do things stand at the moment? Well, if you go to the Kilopass website (www.kilopass.com) and click the Litigation Update link at the bottom of the page, you'll be presented with a blow-by-blow account (there's a corresponding area on the Sidense website at www.sidense.com, but you have to register and be approved before you can see what's there).

Just to give you an idea as to how confusing this can all be. On 3 February 2011, Kilopass issued a press release with the subject "USPTO Validates One of Three Key Kilopass 1T Anti-Fuse Patents Asserted Against Sidense." On the same day, and relating to the same judgment, Sidense issued their own press release with the subject "USPTO Validates Sidense's Non-Infringement Position and Rejects Two Kilopass Patents." (The folks at Kilopass say that the validated patent is the important one and that they are working on getting the other two validated also; of course I’m sure that the folks at Sidense regard the two rejected patents as being of more interest.) Later, on 10 February 2011, the US District Court denied a motion for delay made by Sidense, which means it's now full steam ahead on the litigation express.

And that's where things stand at the time of this writing. Who is in the right and who is in the wrong? Who will win the battle of the patents? It would take a braver man that yours truly to make any sort of pronouncement or prediction in this area, not the least that I don’t want to be dragged into court myself (my dear old mother would be very displeased, let me tell you). All I can say is that, in researching this article, I've learned an awful lot about 1T OTP antifuse-based memory technology and I've found the whole patent process to be far more interesting than I would have ever supposed. Like many other folks (especially Kilopass and Sidense customers), from this point on I will be keenly watching how things unfold.

About the author
Clive (Max) Maxfield is founder, president, consultant, and chief bottle-washer at Maxfield High-Tech Consulting (www.CliveMaxfield.com). He is also editor of the EE Times Programmable Logic Designline website (www.eetimes.com/design/programmable-logic). Max is the author and co-author of a number of books, including Bebop to the Boolean Boogie (An Unconventional Guide to Electronics), The Design Warrior’s Guide to FPGAs, and How Computers Do Math. Max can be contacted at max@CliveMaxfield.com.

Fascinating as the wrangling is to watch, it's perhaps quite relevant to point out that there IS an option for one-time programmable non-volatile memory that does NOT have any legal worries or concerns associated-- Novocell Semiconductor was founded in 2001, was awarded some of the EARLIEST process and methods patents in the field, and licenses their (ok, OUR - wink) full line of products to SoC firms, IDMs, and foundries from 8 bit to 4Mbit sizes. Using Novocell's innovative Smartbit bit cell, which utilizes a dynamic programming method, the product line provides over 30 years data storage life, and a guaranteed 100% bit programming--assuring that all data is programmed at the time of hardbreakdown of the gate oxide.
Details at www.novocellsemi.com of course.