STRUCTURED ASIC is an intermediate technology between ASIC and
FPGA ,
offering high performance, a characteristic of ASIC, and low NRE cost,
a characteristic of FPGA. Using Structured ASIC allows products to be
introduced quickly to market, to have lower cost and to be designed
with ease.

In a FPGA, interconnects and logic blocks are programmable after
fabrication, offering high flexibility of design and ease of debugging
in prototyping. However, the capability of FPGAs to implement large
circuits is limited, in both size and speed, due to complexity in
programmable routing, and significant space occupied by programming
elements, e.g. SRAMs, MUXes. On the other hand, ASIC design flow is
expensive. Every different design needs a complete different set of
masks. The Structured ASIC is a solution between these two. It has
basically the same structure as a FPGA, but being mask-programmable
instead of field-programmable, by configuring one or several via
layers between metal layers. Every SRAM configuration bit can be
replaced by a choice of putting a via or not between metal contacts.

A number of commercial vendors have introduced structured ASIC
products. They have a wide range of configurability, from a single via
layer to 6 metal and 6 via layers. Altera's Hardcopy-II, eASIC's
Nextreme are examples of commercial structured ASICs.