I was working on this from within CCES. It dawned on me that maybe it was being effected by an automatic break point. So I unchecked them all and it still did not work. So I just tried from outside CCES and BOOM, it worked.

I would suggest you to kindly refer to Application Note EE-384 for more insight in Boot concepts in ADSP-SC58x processor.

In ADSP-SC58x, Cortex A5 is the primary core which does the boot processing for all the 3 cores and then comes out of reset. The application running in Cortex A5 should release the other two sharc cores out of reset.

From your description, following scenario is possible:

After boot process by ARM core for all 3 core, ARM comes out of reset.

Application in ARM releases SHARC0 out of reset, as a result of which SHARC0 starts running the application.

Now SHARC0 can release the SHARC1 out of reset and it will start booting.

If you suspect, that the SHARC0 is unable to release the SHARC1 from reset, then I would suggest you to try the similar behavior via emulator to confirm on whether this works with that or not.

Instead of using “adi_core_enable(ADI_CORE_SHARC1);” you can use the following function call from SHARC0 to check if that helps at your end or not:

void Release_SHARC1_from_reset()

{

*pREG_RCU0_CRSTAT =BITM_RCU_CRSTAT_CR2;

*pREG_RCU0_SIDIS=BITM_RCU_SIDIS_SI1;

int i=0;

for( i=0; i<100000; i++);

*pREG_RCU0_CRCTL=BITM_RCU_CRCTL_CR2;

while((*pREG_RCU0_CRSTAT&BITM_RCU_CRSTAT_CR2)==0);

*pREG_RCU0_SIDIS &= ~BITM_RCU_SIDIS_SI1;

*pREG_RCU0_CRCTL &= ~BITM_RCU_CRCTL_CR2;

while((*pREG_RCU0_CRSTAT&BITM_RCU_CRSTAT_CR2)==1);

}

Single stepping inside the adi_core_enable will let you know why it does not work.

Other thing which you can try is create a project as ADSP-21584 and then check the code for adi_core_enable(ADI_CORE_SHARC1) which will be getting generated in SHARC0 core.

I think the macro is defined in such a way, that it is assumed that for ADSP-SC58x processor, ARM is the primary core and it should only release the both cores out of reset.

In ADSP-21584, SHARC0 is the primary core and it release SHARC1 out of reset.

This will explain why by using the CCES API to release SHARC1 from SHARC0 was failing.