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Method to Eliminate REGISTER UPDATING in Microprogrammed Systems

Publishing Venue

IBM

Related People

Liang, BC: AUTHOR

Abstract

REGISTER UPDATING Consider a computer system containing a processor with its associated register files, which is being used to handle asequence of data of the same type - p(1), p(2), p(3) .., e.g., p(i) and p(i+1), are starting and ending points of a vector v(i). For each p(i), the processor generates a(i), b(i), c(i), .., which together with a(i-1), b(i-1), c(i-1), .., yield some result k(i-1). Let NEWA, NEWB, NEWC, ..; and OLDA, OLDB, OLDC, .. be a set of registers in the register file. The following is the program flow of the above system: A. Reading in data p(i), while a(i-1) is in OLDA, b(i-1) in OLDB, etc., (see step 4 below). B. Generating data a(i), b(i), c(i), .., and put them in registers NEWA, NEWB, NEWC, .. . (Image Omitted) C. From the contents of the registers OLDA, OLDB, OLDC, .., and NEWA, NEWB, NEWC, ..

Country

United States

Language

English (United States)

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This is the abbreviated version, containing approximately
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Method to Eliminate REGISTER UPDATING in Microprogrammed Systems

REGISTER UPDATING Consider a computer system containing a processor
with its associated register files, which is being used to handle asequence of data
of the same type - p(1), p(2), p(3) .., e.g., p(i) and p(i+1), are starting and ending
points of a vector v(i). For each p(i), the processor generates a(i), b(i), c(i), ..,
which together with a(i-1), b(i-1), c(i-1), .., yield some result k(i-1). Let NEWA,
NEWB, NEWC, ..; and OLDA, OLDB, OLDC, .. be a set of registers in the
register file. The following is the program flow of the above system: A. Reading
in data p(i), while a(i-1) is in OLDA, b(i-1) in OLDB, etc., (see step 4 below). B.
Generating data a(i), b(i), c(i), .., and put them in registers NEWA, NEWB,
NEWC, .. .

(Image Omitted)

C. From the contents of the registers OLDA, OLDB, OLDC, .., and NEWA,
NEWB, NEWC, ..; the result k(i-1) is generated. D. Updating the registers

(Image Omitted)

E. Repeating step 1 for p(i+1). Suppose the algorithm to generate k(i) from the
contents of the registers NEWA, NEWB, NEWC, .., and OLDA, OLDB, OLDC, ..,
is symmetric in nature; e.g., they represent the data for both end points of a
vector to be displayed in a graphics system. Then the register updating in step 4
above can be eliminated by a method discussed here -- adding a control to the
address line of the registers file. IMPLEMENTATION Suppose the system is
implemented by using bit-slice processor design (ALU, sequencer, and writable
control store, etc.). Also, assume that the register file contains 2**n 16-bit
registers. There are n bits in the microword representing the address of the
registers. A register ADDREG is added which can be loaded from the data bus.
Two signals are needed: A signal to load the register ADDREG. A signal (may be
controlled by 1 bit in the microword), called ADDCTRL, controls the least
significant r bits of the address line to the registers file: If the bit is 0, then the
address of the register is provided by the microcode. If the bit is 1, then the least
significant r bits of the address is provided by the logical OR of the least
significant r bits of ADDREG and those in microword (see Fig. 1), and the higher
(n-r) bits come from the microword. In the system in section 1, assume that its
register file contains 2**8 = 256 registers, and take r = 1.

(Image Omitted)

When the control bit ADDCRTL is asserted, REGA represents two registers
REGA(n) depending on the parity of n, the contents of ADDREG. A register
TEMREG and ADDREG are initially set to zero. The program flow of the system
then becomes: A. Reading in data p(i), B. Generating data a(i), b(i), c(i), ..,
and put them in registers REGA(i),REGB(i),REGC(i):.

(Image Omitted)

C. From the contents of the registers REGA(i),REGB(i),REGC(i), and REGA(i-
1),REGB(i-1),REGC(i-1); the result k(i-1) is generated. D. Adding 1 to the