Archive for August, 2012

In our latest blog entries, Synopsys mixed-signal customers talked about their verification flow. Those posts described known aspects of mixed-signal environment (such as for example behavioral modeling). I wanted to highlight today a slightly different usage of Synopsys mixed signal solution among some of our customers. Using performance and ease of use of CustomSim-VCS, DFT verification engineers are able to get a considerable speedup in their simulations.

Of course, when I am referring to DFT, I am not talking about Fourier Transform, but Design For Test

Rambus is one of those customers. Working closely with Synopsys, they presented a paper on this approach. The goal was to use CustomSim-VCS to drastically improve DFT logic and timing verification cycle-time and coverage.

In this interview, Bing Chuang from Rambus and Sumit Vishwakarma from Synopsys share their insights about using CustomSim –VCS for DFT Logic and Timing Verification, the flow they architected and the improved coverage and performance they were able to get.

If you read my blog or other EDA related blogs, you probably have already figured out that verification, specifically for mixed-signal designs, is getting increasingly complex. Different variables have to be taken in consideration: complexity of your design environment or topology, high-volume of regression runs, simulation speed are just a few of those . The verification methodology has also to support multiple languages, and work with different netlist formats available across the industry. As such, there is a crucial need for an integrated mixed-signal verification environment that focuses on functionality, reliability, and performance.

Well, today is your lucky day, Synopsys has such a tool :). CustomExplorer™ Ultra (CXU), is a GUI- and netlist-based verification platform that helps automate Verification regression tests without manually creating different configuration files or scripts.