We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Firefox,
Internet Explorer 11,
Safari. Thank you!

AR# 42569

Description

This article contains issues resolved in theSpartan-6 FPGA Integrated Block v2.3 Wrapper for PCI Express that are alsolisted in the readme.txt file that accompanies this version of the core. These are issues that were fixed as part of the update from the previous version of the core.

Solution

GTP Settings UpdatedCR 608469 The GTP settings have been updated, based on board characterization results, with the new settings providing better reliability and more margin across PVT.

LL_REPLAY_TIMEOUT Settings UpdatedCR 582996 The LL_REPLAY_TIMEOUT settings have been updated to account for RX L0s Latency.

User Interface Signal name changed from tstrb to tkeep.CR 579318 User Interface Signals s_axis_tx_tstrb[3:0] and m_axis_rx_tstrb[3:0] have been renamed to s_axis_tx_tkeep[3:0] and m_axis_rx_tkeep[3:0]. These signals are not needed for the Spartan-6 FPGA Integrated Block for PCI Express. However, these are needed for AXI compliance.

Revision History 01/18/2012 - Modified format to use a single AR for all known issues and referenced 45702 for all known issues. Any issue that was listed here is now in AR 45702. 10/08/2011 - Added 44442 07/06/2011 - Initial Release