Issues surrounding the integration of Hf-based high-κ dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate-stack process as well as optimization of other CMOS process steps enable robust metal/high-κ CMOSFETs with wide process latitude. HfO2 of a 2-nm physical thickness shows a very minimal transient charge trapping resulting f...
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For the first time, the tradeoffs between higher mobility (smaller bandgap) channel and lower band-to-band tunneling (BTBT) leakage have been investigated. In particular, through detailed experiments and simulations, the transport and leakage in ultrathin (UT) strained germanium (Ge) MOSFETs on bulk and silicon-on-insulator (SOI) have been examined. In the case of strained Ge MOSFETs on bulk Si, t...
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Large band-to-band tunneling (BTBT) leakage currents can ultimately limit the scalability of high-mobility (small-bandgap) materials. This paper presents a novel heterostructure double-gate FET (DGFET) that can significantly reduce BTBT leakage currents while retaining its high mobility, making it suitable for scaling into the sub-20-nm regime. In particular, through one-dimensional Poisson-Schrod...
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This paper reviews the history of strained-silicon and the adoption of uniaxial-process-induced strain in nearly all high-performance 90-, 65-, and 45-nm logic technologies to date. A more complete data set of n- and p-channel MOSFET piezoresistance and strain-altered gate tunneling is presented along with new insight into the physical mechanisms responsible for hole mobility enhancement. Strained...
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The combination of channel mobility-enhancement techniques such as strain engineering with nonclassical MOS device architectures, such as ultrathin-body (UTB) or double-gate structures, offers the promise of maximizing current drive while maintaining the electrostatic control required for aggressive device scaling in future technology nodes. The tradeoff between transport enhancement and OFF-state...
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The authors have developed short-channel strained-silicon-on-insulator (strained-SOI) MOSFETs on silicon-germanium (SiGe)-on-insulator (SGOI) substrates fabricated by the Ge condensation technique. 35-nm-gate-length strained-SOI MOSFETs were successfully fabricated. The strain in Si channel is still maintained for the gate length of 35 nm. The performance enhancement of over 15% was obtained in 70...
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The impact of different processing factors on the low-frequency (LF) noise of nMOSFETs fabricated in strained-silicon (SSi) substrates will be described. It is shown that the use of an SSi substrate can yield improved LF noise performance compared with standard Czochralski silicon material. This is demonstrated for both full-wafer and selective epitaxial SSi material. The lower 1/f noise points to...
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In this paper, the metal source/drain (S/D) Schottky-barrier (SB) MOSFET technology is reviewed. The technology offers several benefits that enable scaling to sub-30-nm gate lengths including extremely low parasitic S/D resistance (1% of the total device resistance), atomically abrupt junctions that enable the physical scaling of the device to sub-10-nm gate lengths, superior control of OFF-state ...
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In this paper, the potential for sub-10-nm junction formation of partial-melt laser annealing (PMLA), which is a combination of solid-phase regrowth and heat-assisted laser annealing (HALA), is demonstrated. HALA and PMLA are effective for reducing laser-energy density for dopant activation and for improving heating uniformity of device structure. The absence of melting at the dopant profile tail ...
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A positive bias temperature instability (PBTI) recovery transient technique is presented to investigate trap properties in HfSiON as high-k gate dielectric in nMOSFETs. Both large- and small-area nMOSFETs are characterized. In a large-area device, the post-PBTI drain current exhibits a recovery transient and follows logarithmic time dependence. In a small-area device, individual trapped electron e...
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Vertical MOSFETs, unlike conventional planar MOSFETs, do not have identical structures at the source and drain, but have very different gate overlaps and geometric configurations. This paper investigates the effect of the asymmetric source and drain geometries of surround-gate vertical MOSFETs on the drain leakage currents in the OFF-state region of operation. Measurements of gate-induced drain le...
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Multiple-gate devices, such as the planar double-gate (DG), triple-gate (TG), FinFET, Pi-Gate (PG), and Omega-Gate Silicon-on-Insulator (SOI) MOSFETs are potential candidates for achieving the performance targets of the International Roadmap of the Semiconductor Industry Association. In this paper, wideband experimental and three-dimensional simulation analyses have been carried out to compare the...
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Building on a previously presented compact gate capacitance (Cg-Vg) model, a computationally efficient and accurate physically based compact model of gate substrate-injected tunneling current (Ig-Vg) is provided for both ultrathin SiO2 and high-dielectric constant (high-κ) gate stacks of equivalent oxide thickness (EOT) down to ∼ 1 n...
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Complex logic functions based on cascading quantum wires (QWs) defined in a GaAs/AlGaAs-based two-dimensional electron gas by electron-beam lithography and wet chemical etching are demonstrated. The concept of connected QWs leads to a nanoelectronic full adder with independent carry- and sum-bit structures. Monolithic designs were fabricated and were found to also demonstrate simultaneous switchin...
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A new cost-effective driving method that can drive plasma-display panel cells without applying any driving waveform to the common electrode is proposed based on a Vt close-curve analysis. In this driving method, it is very important to prevent a misfiring discharge due to the inversion of the polarity of the wall charges accumulated between the scan and address electrodes. The measured ...
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Negative Bias Temperature Instability (NBTI)-induced degradation for ultra-scaled and future-generation MOSFETs is investigated. Numerical simulations based on Reaction-Diffusion framework are implemented. Geometric dependence of degradation arising from the transistor structure and scaling is incorporated into the model. The simulations are applied to narrow-width planar triple-gate and surround-...
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A self-consistent Poisson-Schrödinger solver is used to calculate the current in trigate n-channel silicon-on-insulator transistors with sections down to 2 nm × 2 nm. The minimum energy of the subbands and the threshold voltage increase as the cross-sectional area of the device is reduced and as the electron concentration in the channel is increased. As a consequence, the threshold volt...
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Aims & Scope

IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects.