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Semiconductor Device Fabrication

Semiconductor device fabrication is the process used to create chips, the integrated circuits that are present in everyday electrical and electronic devices. It is a multiple-step sequence of photographic and chemical processing steps during which electronic circuits are gradually created on a wafer made of pure semiconducting material. Silicon is the most commonly used semiconductor material today, along with various compound semiconductors.

The entire manufacturing process from start to packaged chips ready for shipment takes six to eight weeks and is performed in highly specialized facilities referred to as fabs.

Wafers

A typical wafer is made out of extremely pure silicon that is grown into mono-crystalline cylindrical ingots (boules) up to 12 in (300 mm) in diameter using the Czochralski process. These ingots are then sliced into wafers about 0.75 mm thick and polished to obtain a very regular and flat surface.

Once the wafers are prepared, many process steps are necessary to produce the desired semiconductor integrated circuit. In general, the steps can be grouped into four areas:

Front-end processing

Back-end processing

Test

Packaging

Processing

In semiconductor device fabrication, the various processing steps fall into four general categories: deposition, removal, patterning, and modification of electrical properties.

Removal processes are any that remove material from the wafer either in bulk or selective form and consist primarily of etch processes, both wet etching and dry etching such as reactive ion etch (RIE). Chemical-mechanical planarization (CMP) is also a removal process used between levels.

Patterning covers the series of processes that shape or alter the existing shape of the deposited materials and is generally referred to as lithography. For example, in conventional lithography, the wafer is coated with a chemical called a photoresist. The photoresist is exposed by a stepper, a machine that focuses, aligns, and moves the mask, exposing select portions of the wafer to short wavelength light. The unexposed regions are washed away by a developer solution. After etching or other processing, the remaining photoresist is removed by plasma ashing.

Modification of electrical properties has historically consisted of doping transistor sources and drains originally by diffusion furnaces and later by ion implantation. These doping processes are followed by furnace anneal or in advanced devices, by rapid thermal anneal (RTA) which serve to activate the implanted dopants. Modification of electrical properties now also extends to reduction of dielectric constant in low-k insulating materials via exposure to ultraviolet light in UV processing (UVP).

Many modern chips have eight or more levels produced in over 300 sequenced processing steps.

Front-End Processing

"Front End Processing" refers to the formation of the transistors directly on the silicon. The raw wafer is engineered by the growth of an ultrapure, virtually defect-free silicon layer through epitaxy. In the most advanced logic devices, prior to the silicon epitaxy step, tricks are performed to improve the performance of the transistors to be built. One method involves introducing a "straining step" wherein a silicon variant such as "silicon-germanium" (SiGe) is deposited. Once the epitaxial silicon is deposited, the crystal lattice becomes stretched somewhat, resulting in improved electronic mobility. Another method, called "silicon on insulator" technology involves the insertion of an insulating layer between the raw silicon wafer and the thin layer of subsequent silicon epitaxy. This method results in the creation of transistors with reduced parasitic effects.

Silicon Dioxide

Front end surface engineering is followed by: growth of the gate dielectric, traditionally silicon dioxide (SiO2), patterning of the gate, patterning of the source and drain regions, and subsequent implantation or diffusion of dopants to obtain the desired complementary electrical properties. In memory devices, storage cells, conventionally capacitors, are also fabricated at this time, either into the silicon surface or stacked above the transistor.

Metal Layers

Once the various semiconductor devices have been created they must be interconnected to form the desired electrical circuits. This "Back End Of Line" (BEOL the latter portion of the front end of wafer fabrication, not to be confused with "back end" of chip fabrication which refers to the package and test stages) involves creating metal interconnecting wires that are isolated by insulating dielectrics. The insulating material was traditionally a form of SiO2 or a silicate glass, but recently new low dielectric constant materials are being used. These dielectrics presently take the form of SiOC and have dielectric constants around 2.7 (compared to 3.9 for SiO2), although materials with constants as low as 2.2 are being offered to chipmakers.

Interconnect

Historically, the metal wires consisted of aluminum. In this approach to wiring often called "subtractive aluminum", blanket films of aluminum are deposited first, patterned, and then etched, leaving isolated wires. Dielectric material is then deposited over the exposed wires. The various metal layers are interconnected by etching holes, called "vias," in the insulating material and depositing tungsten in them with a CVD technique. This approach is still used in the fabrication of many memory chips such as dynamic random access memory (DRAM) as the number of interconnect levels is small, currently no more than four.

More recently, as the number of interconnect levels for logic has substantially increased due to the large number of transistors that are now interconnected in a modern microprocessor, the timing delay in the wiring has become significant prompting a change in wiring material from aluminum to copper and from the aforementioned silicon dioxides to newer low-K material. This performance enhancement also comes at a reduced cost via damascene processing that eliminates processing steps. In damascene processing, in contrast to subtractive aluminum technology, the dielectric material is deposited first as a blanket film and is patterned and etched leaving holes or trenches. In "single damascene" processing, copper is then deposited in the holes or trenches surrounded by a thin barrier film resulting in filled vias or wire "lines" respectively. In "dual damascene" technology, both the trench and via are fabricated before the deposition of copper resulting in formation of both the via and line simultaneously, further reducing the number of processing steps. The thin barrier film, called Copper Barrier Seed (CBS), is necessary to prevent copper diffusion into the dielectric. The ideal barrier film is effective, but is barely there. As the presence of excessive barrier film competes with the available copper wire cross section, formation of the thinnest yet continuous barrier represents one of the greatest ongoing challenges in copper processing today.

As the number of interconnect levels increases, planarization of the previous layers is required to ensure a flat surface prior to subsequent lithography. Without it, the levels would become increasingly crooked and extend outside the depth of focus of available lithography, interfering with the ability to pattern. CMP is the primary processing method to achieve such planarization although dry "etch back" is still sometimes employed if the number of interconnect levels is no more than three.

Wafer Test

The highly serialized nature of wafer processing has increased the demand for metrology in between the various processing steps. Wafer test metrology equipment is used to verify that the wafers are still good and haven't been damaged by previous processing steps. If the number of dies - the integrated circuits that will eventually become chips - on a wafer that measure as fails exceed a predetermined threshold, the wafer is scrapped rather than investing in further processing.

Device Test

Once the Back End Processing has been completed, the semiconductor devices are subjected to a variety of electrical tests to determine if they function properly. The proportion of devices on the wafer found to perform properly is referred to as the yield.

The fab tests the chips on the wafer with an electronic tester that presses tiny probes against the chip. The machine marks each bad chip with a drop of dye. The fab charges for test time; the prices are on the order of cents per second. Chips are often designed with testability features to speed testing, and reduce test costs.

A good chip design made by a good process will have more than 90% yield. A yield below 70% wastes too much material, losing money.

Good designs try to test and statistically manage corners: extremes of silicon behavior caused by operating temperature combined with the extremes of fab processing steps. Most designs cope with more than 64 corners.

Packaging

Once tested, the wafer is scored and then broken into individual dice. Only the good, undyed chips go on to be packaged.

Plastic or ceramic packaging involves mounting the die, connecting the die pads to the pins on the package, and sealing the die. Tiny wires are used to connect pads to the pins. In the old days, wires were attached by hand, but now purpose-built machines perform the task. Traditionally, the wires to the chips were gold, leading to a "lead frame" (pronounced "leed frame") of copper, that had been plated with solder, a mixture of tin and lead. Lead is poisonous, so lead-free "lead frames" are now the best practice.

Chip-scale package (CSP) is another packaging technology. Plastic packaged chips are usually considerably larger than the actual die, whereas CSP chips are nearly the size of the die. CSP can be constructed for each die before the wafer is diced.

The packaged chips are retested to ensure that they were not damaged during packaging and that the die-to-pin interconnect operation was performed correctly. A laser etches the chip's name and numbers on the package.

List of Steps

This is a list of processing techniques that are employed numerous times in a modern electronic device and do not necessarily imply a specific order:

Wafer backgrinding (to reduce the thickness of the wafer so the resulting chip can be put into a thin device like a smartcard or PCMCIA card.)

Die preparation

Wafer mounting

Die cutting

IC packaging

Die attachment

IC Bonding

Wire bonding

Flip chip

Tab bonding

IC encapsulation

Baking

Plating

Lasermarking

Trim and form

IC testing

History

When feature widths were far greater than about 10 micrometres, purity was not the issue that it is today in device manufacturing. But as the devices became more integrated the cleanrooms became even cleaner. Today, the fabs are pressurized with filtered air, to remove even the smallest particles which could come to rest on the wafers and contribute to defects. The workers in a semiconductor fabrication facility are required to wear cleanroom suits to protect the devices from human contamination.

In an effort to increase profits, semiconductor device manufacture spread from Texas and California in the 1960s to the rest of the world, such as Ireland, Israel, Japan, Taiwan, Korea, Singapore and China, and is a global business today.

Photolithography

Photolithography is a process used in microfabrication to selectively remove parts of a thin film (or the bulk of a substrate). It uses light to transfer a geometric pattern from a photomask to a light-sensitive chemical (photoresist, or simply "resist") on the substrate. A series of chemical treatments then engraves the exposure pattern into the material underneath the photoresist. In a complex integrated circuit (for example, modern CMOS), a wafer will go through the photolithographic cycle up to 50 times.

Photolithography resembles the conventional lithography used in printing, and shares some fundamental principles with photography. It is used because it affords exact control over the shape and size of the objects it creates, and because it can create patterns over an entire surface simultaneously. Its main disadvantages are that it requires a flat substrate to start with, it is not very effective at creating shapes that are not flat, and it can require extremely clean operating conditions.

Basic Procedure

A single iteration of photolithography combines several steps in sequence. Modern cleanrooms use automated, robotic wafertrack systems to coordinate the process. The procedure described here omits some advanced treatments, such as thinning agents or edge-bead removal.

Preparation

The wafer is initially heated to a temperature sufficient to drive off any moisture that may be present on the wafer surface. Wafers that have been in storage must be chemically cleaned to remove contamination. A liquid or gaseous "adhesion promoter", such as hexamethyldisilazane (HMDS), is applied to promote adhesion of the photoresist to the wafer.

Photoresist application

The wafer is covered with photoresist ("PR") by spin coating. A viscous, liquid solution of photoresist is dispensed onto the wafer, and the wafer is spun rapidly to produce a uniformly thick layer. The spin coating typically runs at 20 to 80 Hz for 30 to 60 seconds, and produces a layer between 2.5 and 0.5 micrometres thick.

The photoresist-coated wafer is then "soft-baked" or "prebaked" to drive off excess solvent, typically at 60 to 100 Â°C for 5 to 30 minutes. Sometimes a nitrogen atmosphere is used.

Exposure and developing

After prebaking, the photoresist is exposed to a pattern of intense light. Optical lithography typically uses ultraviolet light (see below). Positive photoresist, the most common type, becomes less chemically robust when exposed; negative photoresist becomes more robust. This chemical change allows some of the photoresist to be removed by a special solution, called "developer" by analogy with photographic developer. A post-exposure bake is performed before developing, typically to help reduce standing wave phenomena caused by the destructive and constructive interference patterns of the incident light.

The develop chemistry is delivered on a spinner, much like photoresist. Developers originally often contained sodium hydroxide (NaOH). However, sodium is considered an extremely undesirable contaminant in MOSFET fabrication because it degrades the insulating properties of gate oxides. Metal-ion-free developers such as tetramethylammonium hydroxide (TMAH) are now used.

The resulting wafer is then "hard-baked", typically at 120 to 180 Â°C for 20 to 30 minutes. The hard bake solidifies the remaining photoresist, to make a more durable protecting layer in future ion implantation, wet chemical etching, or plasma etching.

Exposure (printing) systems

Exposure systems typically produce an image on the wafer using a photomask. The light shines through the photomask, which blocks it in some areas and lets it pass in others. (Maskless lithography projects a precise beam directly onto the wafer without using a mask, but it is not widely used in commercial processes.) Exposure systems may be classified by the optics that transfer the image from the mask to the wafer.

Contact and proximity

A contact printer, the simplest exposure system, puts a photomask in direct contact with the wafer and exposes it to a uniform light. A proximity printer puts a small gap between the photomask and wafer. In both cases, the mask covers the entire wafer, and simultaneously patterns every die.

Contact printing is liable to damage both the mask and the wafer. Both contact and proximity lithography require the light intensity to be uniform across an entire wafer, and the mask to align precisely to features already on the wafer. As modern processes use increasingly large wafers, these conditions become increasingly difficult.

Research and prototyping processes often use contact lithography, because it uses inexpensive hardware and can achieve high optical resolution. The resolution is approximately the square root of the product of the wavelength and the gap distance. Hence, contact printing offers the best resolution, because its gap distance is approximately zero (neglecting the thickness of the photoresist itself). In addition, nanoimprint lithography may revive interest in this familiar technique, especially since the cost of ownership is expected to be low.

Steppers

A stepper is a system used in the manufacture of integrated circuits (ICs) that is similar in operation to a slide projector or a photographic enlarger. Steppers are an essential part of the complex process, called photolithography, that creates millions of microscopic circuit elements on the surface of tiny chips of silicon.

The silicon wafers are coated with photoresist, and placed in a cassette that holds a number of wafers. This is then placed in a part of the stepper called the wafer loader, usually located at the lower front of the stepper.

A robot in the wafer loader picks up one of the wafers from the cassette and loads it onto the wafer stage where it is aligned to enable another, finer alignment process that will occur later on.

The pattern of the circuitry for each chip is contained in a pattern etched in chrome on the reticle, which is a plate of transparent quartz. A typical reticle used in steppers is approximately 114 by 134 mm square, and about one centimeter thick.

A variety of reticles, each appropriate for one stage in the process, are contained in a rack in the reticle loader, usually located at the upper front of the stepper. Before the wafer is exposed a reticle is loaded onto the reticle stage by a robot, where it is also very precisely aligned. Since the same reticle can be used to expose many wafers, it is loaded once before a series of wafers is exposed, and is realigned periodically.

Once the wafer and reticle are in place and aligned, the wafer stage, which is moved very precisely in the X and Y directions (front to back and left to right) by worm screws or linear motors, carries the wafer so that the first of the many patterns (or "shots") to be exposed on it is located below the lens, directly under the reticle.

Although the wafer is aligned after it is placed on the wafer stage, this alignment is not sufficient to insure that the layer of circuitry to be printed onto the wafer exactly overlays previous layers already there. Therefore each shot is aligned using special alignment marks that are located in the pattern for each final IC chip. Once this fine alignment is completed, the shot is exposed by light from the stepper's illumination system that passes through the reticle, through a reduction lens, and on to the surface of the wafer. A process program or "recipe" determines the length of the exposure, the reticle used, as well as other factors that affect the exposure.

Each shot located in a grid pattern on the wafer is exposed in turn as the wafer is stepped back and forth under the lens. When all shots on the wafer are exposed, the wafer is unloaded by the wafer loader robot, and another wafer takes its place on the stage. The exposed wafer is eventually moved to a developer where the photoresist on its surface is exposed to developing chemicals that wash away areas of the photoresist, based on whether or not they were exposed to the light passing through the reticle. The developed surface is then subjected to other processes of photolithography.

Scanners

Scanners are steppers that increase the length of the area exposed in each shot (the exposure field) by moving the reticle stage and wafer stage in opposite directions to each other during the exposure. Instead of exposing the entire field at once, the exposure is made through an "exposure slit" that is as wide as the exposure field, but only a fraction of its length (such as a 9x25 mm slit for a 35x25 mm field). The image from the exposure slit is scanned across the exposure area.

There are several benefits to this technique. The field can be exposed with a lesser reduction of size from the reticle to the wafer (such as 4x reduction on a scanner, compared with 5x reduction on a stepper), while allowing a field size much larger than that which can be exposed with a typical stepper. Also the optical properties of the projection lens can be optimized in the area through which the image of the projection slit passes, while optical aberrations can be ignored outside of this area, because they will not affect the exposed area on the wafer.

Successful scanning requires extremely precise synchronization between the moving reticle and wafer stages during the exposure. Accomplishing this presents many technological challenges.

Dry etching

Dry etching refers to the removal of material, typically a masked pattern of semiconductor material, by exposing the material to a bombardment of ions (usually a plasma of nitrogen, chlorine and boron trichloride) that dislodge portions of the material from the exposed surface. Unlike with many (but not all, see isotropic etching) of the wet chemical etchants used in wet etching, the dry etching process typically etches directionally or anisotropically.

Explanation

Dry etching is used in conjunction with photolithographic techniques to attack certain areas of a semiconductor surface in order to form recesses in material, such as contact holes (which are contacts to the underlying semiconductor substrate) or via holes (which are holes that are formed to provide an interconnect path between conductive layers in the layered semiconductor device) or to otherwise remove portions of semiconductor layers where predominantly vertical sides are desired. In conjunction with semiconductor manufacturing, micromachining and display production the removal of organic residues by oxygen plasmas is sometimes correctly described as a dry etch process. However, also the term plasma ashing may be used.

Used, Surplus & Refurbished Dry Etch Equipment in our inventory:

Applied Materials

Lam Research

Tokyo Electron

Plasma Ashing Equipment

In semiconductor manufacturing plasma ashing is the process of removing the photoresist from an etched wafer. Using a plasma source, a monatomic reactive species is generated. Oxygen or fluorine are the most common reactive species. The reactive species combines with the photoresist to form ash which is removed with a vacuum pump.

Typically, monatomic (single atom) oxygen plasma is created by exposing oxygen gas (O2) to ionizing radiation. At the same time, many free radicals are formed which could damage the wafer. Newer, smaller circuitry is increasingly susceptible to these particles. Originally, plasma was generated in the process chamber, but as the need to get rid of free radicals has increased, many machines now use a downstream plasma configuration, where plasma is formed remotely and channeled to the wafer. This allows electrically charged particles time to recombine before they reach the wafer surface, and prevents damage to the wafer surface.

Monatomic oxygen is electrically neutral and although it does recombine during the channeling, it does so at a slower rate than the positively or negatively charged free radicals, which attract one another. Effectively, this means that when all of the free radicals have recombined, there is still a portion of the active species available for process. Because a large portion of the active specie is lost to recombination, process times may take longer. To some extent, these longer process times can be mitigated by increasing the temperature of the reaction area.

Used, Surplus & Refurbished Plasma Ashing Equiment in our inventory:

Gasonics

Mattson

Axcelis

Rapid Thermal Processing (RTP) Equipment

Rapid thermal processing (or RTP) refers to a semiconductor manufacturing process which heats silicon wafers to high temperatures (up to 1200 C or greater) on a timescale of several seconds or less. Such rapid heating rates are attained by high intensity lamps or laser process. These processes are used for a wide variety of applications in semiconductor manufacturing including dopant activation, thermal oxidation, metal reflow and chemical vapor deposition.

Temperature Control

One of the key challenges in rapid thermal processing is accurate measurement and control of the wafer temperature. Monitoring the ambient with a thermocouple is not feasible, in that the high temperature ramp rates prevent the wafer from coming to thermal equilibrium with the process chamber. One temperature control strategy involves in situ pyrometry to effect real time control.

Furnace Anneal

Furnace annealing is a process used in semiconductor device fabrication which consist of heating multiple semiconductor wafers in order to affect their electrical properties. Heat treatments are designed for different effects. Wafers can be heated in order to activate dopants, change film to film or film to wafer substrate interfaces, densify deposited films, change states of grown films, repair damage from implants, move dopants or drive dopants from one film into another or from a film into the wafer substrate.

Furnace anneals may be integrated into other furnace processing steps, such as oxidations, or may be processed on their own.

Furnace anneals are performed by equipment especially built to heat semiconductor wafers. Furnaces are capable of processing lots of wafers at a time but each process can last between several hours and a day.

Thermal Oxidation Equipment

In microfabrication, thermal oxidation is a way to produce a thin layer of oxide (usually silicon dioxide) on the surface of a wafer (semiconductor). The technique forces an oxidizing agent to diffuse into the wafer at high temperature and react with it. The rate of oxide growth is often predicted by the Deal-Grove model. Thermal oxidation may be applied to different materials, but this article will only consider oxidation of silicon substrates to produce silicon dioxide.

oxidation technology

Most thermal oxidation is performed in furnaces, at temperatures between 800 and 1200Â°C. A single furnace accepts many wafers at the same time, in a specially designed quartz rack (called a "boat"). Historically, the boat entered the oxidation chamber from the side (this design is called "horizontal"), and held the wafers vertically, beside each other. However, many modern designs hold the wafers horizontally, above and below each other, and load them into the oxidation chamber from below.

Vertical furnaces stand higher than horizontal furnaces, so they may not fit into some microfabrication facilities. However, they help to prevent dust contamination. Unlike horizontal furnaces, in which falling dust can contaminate any wafer, vertical furnaces only allow it to fall on the top wafer in the boat.

oxide quality

Wet oxygen is preferred to dry oxygen for growing thick oxides, because of the higher growth rate. However, fast oxidation leaves more dangling bonds at the silicon interface, which produce quantum states for electrons and allow current to leak along the interface. (This is called a "dirty" interface.) Wet oxidation also yields a lower-density oxide, with lower dielectric strength.

The long time required to grow a thick oxide in dry oxygen makes this process impractical. Thick oxides are usually grown with a long wet oxidation bracketed by short dry ones (a dry-wet-dry cycle). The beginning and ending dry oxidations produce films of high-quality oxide at the outer and inner surfaces of the oxide layer, respectively.

Mobile metal ions can degrade performance of MOSFETs (sodium is of particular concern). However, chlorine can immobilize sodium by forming sodium chloride. Chlorine is often introduced by adding hydrogen chloride or trichloroethylene to the oxidizing medium. Its presence also increases the rate of oxidation.

Chemical Vapor Deposition (CVD)

Chemical vapor deposition (CVD) is a chemical process used to produce high-purity, high-performance solid materials. The process is often used in the semiconductor industry to produce thin films. In a typical CVD process, the wafer (substrate) is exposed to one or more volatile precursors, which react and/or decompose on the substrate surface to produce the desired deposit. Frequently, volatile byproducts are also produced, which are removed by gas flow through the reaction chamber.

types of chemical vapor deposition

A number of forms of CVD are in wide use and are frequently referenced in the literature. These processes differ in the means by which chemical reactions are initiated (e.g., activation process) and process conditions.

Low-pressure CVD (LPCVD) - CVD processes at subatmospheric pressures. Reduced pressures tend to reduce unwanted gas-phase reactions and improve film uniformity across the wafer. Most modern CVD process are either LPCVD or UHVCVD.

Ultrahigh vacuum CVD (UHVCVD) - CVD processes at a very low pressure, typically below 10-6 Pa (~ 10-8 torr). Caution: in other fields, a lower division between high and ultra-high vacuum is common, often 10-7Pa.

Classified by physical characteristics of vapor

Aerosol assisted CVD (AACVD) - A CVD process in which the precursors are transported to the substrate by means of a liquid/gas aerosol, which can be generated ultrasonically. This technique is suitable for use with involatile precursors.

Direct liquid injection CVD (DLICVD) - A CVD process in which the precursors are in liquid form (liquid or solid dissolved in a convenient solvent). Liquid solutions are injected in a vaporization chamber towards injectors (typically car injectors). Then the precursors vapours are transported to the substrate as in classical CVD process. This technique is suitable for use on liquid or solid precursors. High growth rates can be reach using this technique.

Plasma methods (see also Plasma processing)

Microwave plasma-assisted CVD (MPCVD)

Plasma-Enhanced CVD (PECVD) - CVD processes that utilize a plasma to enhance chemical reaction rates of the precursors. PECVD processing allows deposition at lower temperatures, which is often critical in the manufacture of semiconductors.

Remote plasma-enhanced CVD (RPECVD) - Similar to PECVD except that the wafer substrate is not directly in the plasma discharge region. Removing the wafer from the plasma region allows processing temperatures down to room temperature.

Rapid thermal CVD (RTCVD) - CVD processes that use heating lamps or other methods to rapidly heat the wafer substrate. Heating only the substrate rather than the gas or chamber walls helps reduce unwanted gas phase reactions that can lead to particle formation.

Vapor phase epitaxy (VPE)

substances commonly deposited for ICs

This section discusses the CVD processes often used for integrated circuits (ICs). Particular materials are deposited best under particular conditions.

Polysilicon

Polycrystalline silicon is deposited from silane (SiH4), using the following reaction:

SiH4 ? Si + 2H2

This reaction is usually performed in LPCVD systems, with either pure silane feedstock, or a solution of silane with 70-80% nitrogen. Temperatures between 600 and 650 ?C and pressures between 25 and 150 Pa yield a growth rate between 10 and 20 nm per minute. An alternative process uses a hydrogen-based solution. The hydrogen reduces the growth rate, but the temperature is raised to 850 or even 1050 degrees Celsius to compensate.

Polysilicon may be grown directly with doping, if gases such as phosphine, arsine or diborane are added to the CVD chamber. Diborane increases the growth rate, but arsine and phosphine decrease it.

Silicon dioxide

Silicon dioxide (usually called simply "oxide" in the semiconductor industry) may be deposited by several different processes. Common source gases include silane and oxygen, dichlorosilane (SiCl2H2) and nitrous oxide (N2O), or tetraethylorthosilicate (TEOS; Si(OC2H5)4). The reactions are as follows:

SiH4 + O2 ? SiO2 + 2H2

SiCl2H2 + 2N2O ? SiO2 + 2N2 + 2HCl

Si(OC2H5)4 ? SiO2 + byproducts

The choice of source gas depends on the thermal stability of the substrate; for instance, aluminium is sensitive to high temperature. Silane deposits between 300 and 500 ?C, dichlorosilane at around 900 ?C, and TEOS between 650 and 750 ?C. However, silane produces a lower-quality oxide than the other methods (lower dielectric strength, for instance), and it deposits nonconformally. Any of these reactions may be used in LPCVD, but the silane reaction is also done in APCVD. CVD oxide invariably has lower quality than thermal oxide, but thermal oxidation can only be used in the earliest stages of IC manufacturing.

Oxide may also be grown with impurities (alloying or "doping"). This may have two purposes. During further process steps that occur at high temperature, the impurities may diffuse from the oxide into adjacent layers (most notably silicon) and dope them. Oxides containing 5% to 15% impurities by mass are often used for this purpose. In addition, silicon dioxide alloyed with phosphorus pentoxide ("P-glass") can be used to smooth out uneven surfaces. P-glass softens and reflows at temperatures above 1000 ?C. This process requires a phosphorus concentration of at least 6%, but concentrations above 8% can corrode aluminium. Phosphorus is deposited from phosphine gas and oxygen:

4PH3 + 5O2 ? 2P2O5 + 6H2

Glasses containing both boron and phosphorus (borophosphosilicate glass, BPSG) undergo viscous flow at lower temperatures; around 850 ?C is achievable with glasses containing around 5 weight % of both constituents, but stability in air can be difficult to achieve. Phosphorus oxide in high concentrations interacts with ambient moisture to produce phosphoric acid. Crystals of BPO4 can also precipitate from the flowing glass on cooling; these crystals are not readily etched in the standard reactive plasmas used to pattern oxides, and will result in circuit defects in integrated circuit manufacturing.

Lower temperature deposition of silicon dioxide and doped glasses from TEOS using ozone rather than oxygen has also been explored (350 to 500 ?C). Ozone glasses have excellent conformality but tend to be hygroscopic -- that is, they absorb water from the air due to the incorporation of silanol (Si-OH) in the glass. Infrared spectroscopy and mechanical strain as a function of temperature are valuable diagnostic tools for diagnosing such problems.

Silicon nitride

Silicon nitride is often used as an insulator and chemical barrier in manufacturing ICs. The following two reactions deposit nitride from the gas phase:

3SiH4 + 4NH3 ? Si3N4 + 12H2

3SiCl2H2 + 4NH3 ? Si3N4 + 6HCl + 6H2

Silicon nitride deposited by LPCVD contains up to 8% hydrogen. It also experiences strong tensile stress (physics), which may crack films thicker than 200 nm. However, it has higher resistivity and dielectric strength than most insulators commonly available in microfabrication (1016 ??cm and 10 MV/cm, respectively).

Another two reactions may be used in plasma to deposit SiNH:

2SiH4 + N2 ? 2SiNH + 3H2

SiH4 + NH3 ? SiNH + 3H2

These films have much less tensile stress, but worse electrical properties (resistivity 106 to 1015 ??cm, and dielectric
strength 1 to 5 MV/cm).

Metals

Some metals (notably aluminium and copper) are seldom or never deposited by CVD. As of 2002, a viable CVD process for copper did not exist, and the metal was deposited by electroplating. Aluminium can be deposited from tri-isobutyl aluminium, but physical vapor deposition methods are usually preferred.

However, CVD processes for molybdenum, tantalum, titanium and tungsten are widely used. These metals can form useful silicides when deposited onto silicon. Mo, Ta and Ti are deposited by LPCVD, from their pentachlorides. In general, for an arbitrary metal M, the reaction is as follows:

2MCl5 + 5H2 ? 2M + 10HCl

The usual source for tungsten is tungsten hexafluoride, which may be deposited in two ways:

Sputter Deposition

Sputter deposition is a method of depositing thin films by sputtering a block of source material onto a "substrate."

Sputtered atoms ejected into the gas phase are not in their thermodynamic equilibrium state, and tend to deposit on all surfaces in the vacuum chamber. A substrate (such as a wafer) placed in the chamber will be coated with a thin film. Sputtering usually uses an argon plasma.

Uses

Sputtering is used extensively in the semiconductor industry to deposit thin films of various materials in integrated circuit processing. Thin antireflection coatings on glass for optical applications are also deposited by sputtering. Because of the low substrate temperatures used, sputtering is an ideal method to deposit contact metals for thin-film transistors. Perhaps the most familiar products of sputtering are low-emissivity coatings on glass, used in double-pane window assemblies. The coating is a multilayer containing silver and metal oxides such as zinc oxide, tin oxide, or titanium dioxide. Sputtering is also used as the process to deposit the metal (Aluminum) layer during the fabrication of CD and DVD discs.

Comparison with other deposition methods

One important advantage of sputtering as a deposition technique is that the deposited films have the same composition as the source material. The equality of the film and target stoichiometry might be surprising since the sputter yield depends on the atomic weight of the atoms in the target. One might therefore expect one component of an alloy or mixture to sputter faster than the other components, leading to an enrichment of that component in the deposit. However, since only surface atoms can be sputtered, the faster ejection of one element leaves the surface enriched with the others, effectively counteracting the difference in sputter rates. This is in contrast to thermal evaporation techniques, where one component of the source may have a higher vapor pressure, resulting in a deposited film with a different composition than the source.

A typical ring-geometry sputter target, here gold showing the cathode made of the material to be deposited, the anode counter-electrode and an outer ring meant to prevent sputtering of the hearth that holds the target.

Sputter deposition also has an advantage over molecular beam epitaxy (MBE) due to its speed. The higher rate of deposition results in lower impurity incorporation because fewer impurities are able to reach the surface of the substrate in the same amount of time. Sputtering methods are consequently able to use process gases with far higher impurity concentrations than the vacuum pressure that MBE methods can tolerate. During sputter deposition the substrate may be bombarded by energetic ions and neutral atoms. Ions can be deflected with a substrate bias and neutral bombardment can be minimized by off-axis sputtering, but only at a cost in deposition rate. Plastic substrates cannot tolerate the bombardment and are usually coated via evaporation.

Types of sputter deposition

Sputtering sources are usually magnetrons that utilize strong electric and magnetic fields to trap electrons close to the surface of the magnetron, which is known as the target. The electrons follow helical paths around the magnetic field lines undergoing more ionizing collisions with gaseous neutrals near the target surface than would otherwise occur. The sputter gas is inert, typically argon. The extra argon ions created as a result of these collisions leads to a higher deposition rate. It also means that the plasma can be sustained at a lower pressure. The sputtered atoms are neutrally charged and so are unaffected by the magnetic trap. Charge build-up on insulating targets can be avoided with the use of RF sputtering where the sign of the anode-cathode bias is varied at a high rate. RF sputtering works well to produce highly insulating oxide films but only with the added expense of RF power supplies and impedance matching networks. Stray magnetic fields leaking from ferromagnetic targets also disturb the sputtering process. Specially designed sputter guns with unusually strong permanent magnets must often be used in compensation.

A magnetron sputter gun showing the target-mounting surface, the vacuum feedthrough, the power connector and the water lines. This design uses a disc target as opposed to the ring geometry illustrated above.

Ion-beam sputtering

Ion-beam sputtering (IBS) is a method in which the target is external to the ion source. A source can work without any magnetic field like in a Hot filament ionization gauge . In a Kaufman source ions are generated by collisions with electrons that are confined by a magnetic field as in a magnetron. They are then accelerated by the electric field emanating from a grid toward a target. As the ions leave the source they are neutralized by electrons from a second external filament. IBS has an advantage in that the energy and flux of ions can be controlled independently. Since the flux that strikes the target is composed of neutral atoms, either insulating or conducting targets can be sputtered. IBS has found application in the manufacture of thin-film heads for disk drives. A pressure gradient between the ion source and the sample chamber is generated by placing the gas inlet at the source and shooting through a tube in into the sample chamber. This saves gas and reduces contamination in UHV applications. The principal drawback of IBS is the large amount of maintenance required to keep the ion source operating.

Reactive sputtering

In reactive sputtering, the deposited film is formed by chemical reaction between the target material and a gas which is introduced into the vacuum chamber. Oxide and nitride films are often fabricated using reactive sputtering. The composition of the film can be controlled by varying the relative pressures of the inert and reactive gases. Film stoichiometry is an important parameter for optimizing functional properties like the stress in SiNx and the index of refraction of SiOx. The transparent indium tin oxide conductor that is used in optoelectronics and solar cells is made by reactive sputtering.

Ion-assisted deposition

In ion-assisted deposition (IAD), the substrate is exposed to a secondary ion beam operating at a lower power than the sputter gun. Usually a Kaufman source like that used in IBS supplies the secondary beam. IAD can be used to deposit carbon in diamond-like form on a substrate. Any carbon atoms landing on the substrate which fail to bond properly in the diamond crystal lattice will be knocked off by the secondary beam. NASA used this technique to experiment with depositing diamond films on turbine blades in the 1980s. IAS is used in other important industrial applications such as creating tetrahedral amorphous carbon surface coatings on hard disk platters and hard transition metal nitride coatings on medical implants.

High-target-utilization sputtering

High-target-utilisation sputtering "HiTUS" is specialized commercial process. More information may be found http://www.plasma-quest.com/hitus-technical-benefits.html The process based upon the remote generation of a high density plasma. The plasma is generated in a side chamber opening into the main process chamber, containing the target and the substrate to be coated. As the plasma is generated remotely, and not from the target itself (as in conventional magnetron sputtering), the ion current to the target is independent of the voltage applied to the target.

High Power Impulse Magnetron Sputtering (HIPIMS)

HIPIMS is a method for physical vapor deposition of thin films which is based on magnetron sputter deposition. HIPIMS utilises extremely high power densities of the order of kWcm-2 in short pulses (impulses) of tens of microseconds at low duty cycle of < 10%.

Ion Deposition

Ion implantation is a materials engineering process by which ions of a material can be implanted into another solid, thereby changing the physical properties of the solid. Ion implantation is used in semiconductor device fabrication and in metal finishing, as well as various applications in materials science research. The ions introduce both a chemical change in the target, in that they can be a different element than the target, and a structural change, in that the crystal structure of the target can be damaged or even destroyed.

Ion implantation setup with mass separator

Ion implantation equipment typically consists of an ion source, where ions of the desired element are produced, an accelerator, where the ions are electrostatically accelerated to a high energy, and a target chamber, where the ions impinge on a target, which is the material to be implanted. Each ion is typically a single atom, and thus the actual amount of material implanted in the target is the integral over time of the ion current. This amount is called the dose. The currents supplied by implanters are typically small (microamperes), and thus the dose which can be implanted in a reasonable amount of time is small. Thus, ion implantation finds application in cases where the amount of chemical change required is small.

Typical ion energies are in the range of 2 to 500 keV (1,600 to 80,000 aJ). Energies in the range 1 to 10 keV (160 to 1,600 aJ) can be used, but result in a penetration of only a few nanometers or less. Energies lower than this result in very little damage to the target, and fall under the designation ion beam deposition. Higher energies can also be used: accelerators capable of 5 MeV (800,000 aJ) are common. However, there is often great structural damage to the target, and because the depth distribution is broad, the net composition change at any point in the target will be small.

The energy of the ions, as well as the ion species and the composition of the target determine the depth of penetration of the ions in the solid: A monoenergetic ion beam will generally have a broad depth distribution. The average penetration depth is called the range of the ions. Under typical circumstances ion ranges will be between 10 nanometers and 1 micrometer. Thus, ion implantation is especially useful in cases where the chemical or structural change is desired to be near the surface of the target. Ions gradually lose their energy as they travel through the solid, both from occasional collisions with target atoms (which cause abrupt energy transfers) and from a mild drag from overlap of electron orbitals, which is a continuous process. The loss of ion energy in the target is called stopping.

Application in semiconductor device fabrication:

Doping

The introduction of dopants in a semiconductor is the most common application of ion implantation. Dopant ions such as boron, phosphorus or arsenic are generally created from a gas source, so that the purity of the source can be very high. These gases tend to be very hazardous. When implanted in a semiconductor, each dopant atom creates a charge carrier in the semiconductor (hole or electron, depending on if it is a p-type or n-type dopant), thus modifying the conductivity of the semiconductor in its vicinity.

Silicon on insulator

One prominent method for preparing SOI substrates from conventional silicon substrates is the SIMOX (Separation by IMplantation of OXygen) process, wherein a buried high dose oxygen implant is converted to silicon oxide by a high temperature annealing process.

Wafer bonding is an alternative method for preparing SOI, where a thermally or chemically oxidized silicon substrate is physically bonded to a second substrate, after which the second substrate is partially removed, leaving behind an active region of a specified thickness. While second substrate removal is commonly achieved via conventional etch or polish techniques, the SmartCut method developed by SOITEC employs ion implantation followed by substrate cleavage to determine the thickness of the remaining substrate.

Mesotaxy

Mesotaxy is the term for the growth of a crystallographically matching phase underneath the surface of the host crystal (compare to epitaxy, which is the growth of the matching phase on the surface of a substrate). In this process, ions are implanted at a high enough energy and dose into a material to create a layer of a second phase, and the temperature is controlled so that the crystal structure of the target is not destroyed. The crystal orientation of the layer can be engineered to match that of the target, even though the exact crystal structure and lattice constant may be very different. For example, after the implantation of nickel ions into a silicon wafer, a layer of nickel silicide can be grown in which the crystal orientation of the silicide matches that of the silicon.

Used, Surplus & Refurbished Ion Deposition Equipment in our inventory

Applied Materials

Axcelis

Varian

AG provides Used Chemical Mechanical Planarization (CMP) Equipment

Chemical-mechanical planarization or Chemical-mechanical polishing, commonly abbreviated CMP, is a technique used in semiconductor fabrication for planarizing the top surface of an in-process semiconductor wafer or other substrate.

Description

The process uses an abrasive and corrosive chemical slurry (commonly a colloid) in conjunction with a polishing pad and retaining ring, typically of a greater diameter than the wafer. The pad and wafer are pressed together by a dynamic polishing head and held in place by a plastic retaining ring. The dynamic polishing head is rotated with different axes of rotation (i.e., not concentric). This removes material and tends to even out any irregular topography, making the wafer flat or planar. This may be necessary in order to set up the wafer for the formation of additional circuit elements. For example, this might be necessary in order to bring the entire surface within the depth of field of a photolithography system, or to selectively remove material based on its position. Typical depth-of-field requirements are down to Angstrom levels for the latest 65 nm technology.

How it works

The process of material removal is not simply that of abrasive scraping, like sandpaper on wood. The chemicals in the slurry also react with and/or weaken the material to be removed. The abrasive accelerates this weakening process and the polishing pad helps to wipe the reacted materials from the surface. The process has been likened to that of a child eating a gummy candy. If the candy sits on the tongue without being scraped around, the candy becomes covered with a gel coating, but the majority of the candy is not affected. Only with a vigorous scraping does the candy dissolve away.

Another analogy is the act of brushing one's teeth. The toothbrush is the mechanical part and the toothpaste is the chemical part. Using either the toothbrush or the toothpaste alone will get one's teeth somewhat clean, but using the toothbrush and toothpaste together makes a superior process.

usage in semiconductor fabrication

Before about 1990 CMP was looked on as too "dirty" to be included in high-precision fabrication processes, since abrasion tends to create particles and the abrasives themselves are not without impurities. Since that time, the integrated circuit industry has moved from aluminium to copper conductors. This required the development of an additive patterning process, which relies on the unique abilities of CMP to remove material in a planar and uniform fashion and to stop repeatably at the interface between copper and oxide insulating layers (see Copper-based chips for details). Adoption of this process has made CMP processing much more widespread. In addition to aluminum and copper, CMP processes have been developed for polishing tungsten, silicon dioxide, and (recently) carbon nanotubes.[1]

Key metrics

Key metrics that are important for CMP are the following:

Rate of removal: How quickly can the material be removed?

Uniformity of removal: How uniform is the removal across the die and the wafer?

Planarity: How planar/flat is the surface after the removal process is complete?

Defects: How many defects and of what size are left behind on the wafer?