FPGA simulation

Once the hardware design entry is completed (using either a schematic or an HDL), you may want to simulate your design on a computer to gain confidence that it works correctly before running it in an FPGA.
Simulation requires a form of input stimulus and then FPGA simulator software can determine the corresponding outputs.

There are two ways to create input stimulus:

Using an interactive waveform editor (easy).

Using a testbench (a bit harder).

Interactive waveform editor

Using an interactive waveform editor, you enter the shape of the inputs (with a few clicks of your computer mouse), and the simulator software draws the shape of the outputs.

Interactive waveform editors were nice for beginners (easy to learn) but are now a dying breed (as much for their limitations than marketing reasons) so you will probably have to do it the hard way...

Testbench

A testbench is a non-synthesizable HDL design that creates stimulus for another (usually synthesizable) design.
It is a bit harder to setup than an interactive waveform editor but a lot more powerful.

For example, let's assume that this synthesizable "gates" circuit needs to be exercised.

module gates(a, b, q, r);input a, b;output q, r;

assign q = a & b; // one AND gateassign r = a | b; // one OR gateendmodule