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AR# 52207

描述

Naming conflicts can occur for designs instantiating Xilinx IP under the following conditions:

Xilinx IP development is using great care to assure that multiple versions and instances of an IP core can be used simultaneously in a design. However, in early versions of the Vivado tool, the following naming conflict issues exist.

解决方案

1) Vivado 2012.1 (Early Access customers only): An IP core uses a sub-module name with dynamic content depending on the IP Core customization. This issue has been seen in the following cores with Vivado Early Access (2012.1) and was fixed in Vivado 2012.2 Clocking WizardSelectIO WizardXACD Wizard

The work-around for these cores (In Vivado 2012.1 only) is to use the CORE Generator tool to generate the IP core, then add the IP to the Vivado Project. All these cores are fixed in the Vivado 2012.2 tools.

2) Vivado 2012.2 : If an IP has a parameterizable HDL file and does not deliver a simulatable source. If an IP delivers static HDL files that are customized by generics in the wrapper file, synthesis does not have a name conflict because the HDL does not change for all instances of the same IP, regardless of parameterization. However, for post synthesis simulation, the IP netlist will have conflicts with module names that have different contents because of the different parameterization. So, even though the modules were identical pre-synthesis, they will not necessarily be the same post-synthesis after all the generics and optimizations have been applied

For IP that do not deliver simulatable source, we recommend that the user synthesize the IP as top, then use write_verilog to generate a netlist that can be simulated. The problem is that post-synthesis the IP netlist will have conflicts with module names that have different contents because of the different parameterization. So, even though the modules were identical pre-synthesis, they will not necessarily be the same post-synthesis after all the generics and optimizations have been applied.