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Abstract:

Optimization of the implantation structure of a metal oxide silicon field
effect transistor (MOSFET) device fabricated using conventional
complementary metal oxide silicon (CMOS) logic foundry technology to
increase the breakdown voltage. The techniques used to optimize the
implantation structure involve lightly implanting the gate region,
displacing the drain region from the gate region, and implanting P-well
and N-well regions adjacent to one another without an isolation region in
between.

Claims:

1. A semiconductor device formed onto a substrate, comprising: a gate
region; a first well region having a first carrier concentration; a
second well region having a second carrier concentration, the first and
the second well regions being in substantial contact with each other
through a transition region, the transition region being located beneath
the gate region; a drain region having a third carrier concentration, the
third carrier concentration being greater than the first carrier
concentration; and a source region having a fourth carrier concentration,
the fourth carrier concentration being greater than the second carrier
concentration, wherein the gate region is displaced from the drain region
by a portion of the first well region.

2. The semiconductor device of claim 1, further comprising: a dielectric
region within the portion of the first well region.

3. The semiconductor device of claim 2, wherein the dielectric region
comprises: a first side and a second side, wherein the first side is in
substantial contact with the drain region, and wherein the second side is
located below a spacer, the spacer being in substantial contact with the
gate region.

4. The semiconductor device of claim 1, further comprising: a shallow
trench isolation region (STI) region within the portion of the first well
region.

5. The semiconductor device of claim 4, wherein the STI region comprises:
a first side and a second side, wherein the first side is in substantial
contact with the drain region, and wherein the second side is located
below a spacer, the spacer being in substantial contact with the gate
region.

6. The semiconductor device of claim 1, further comprising: a silicide
region in substantial contact with a top surface of the drain region.

7. The semiconductor device of claim 6, wherein the silicide region is
displaced from the gate region by a portion of a top surface of the
substrate that corresponds to the portion of the first well region.

8. The semiconductor device of claim 1, further comprising: a channel
located within the source region.

9. The semiconductor device of claim 1, wherein the drain region is
within the first we 1 region.

10. The semiconductor device of claim 1, wherein the source region is
within the second well region.

11. The semiconductor device of claim 1, wherein the first well region
and the drain region comprise a first type of material.

12. The semiconductor device of claim 1, wherein the second well region
comprises: a first type of material, and wherein the source region
comprises a second type of material, the first type of material being
different from the second type of material.

13. A semiconductor device, comprising: a source region within a
substrate; a drain region within the substrate; a gate region
substantially overlapping at least a portion of the source region; and a
dielectric region configured to: prevent overlap between the gate region
and the drain region; and provide resistance in a current path between
the source region and the drain region.

14. The semiconductor device of claim 13, wherein the dielectric region
is in contact with the drain region.

15. The semiconductor device of claim 13, wherein the dielectric region
substantially overlaps at least a portion of a spacer, the spacer being
in substantial contact with the gate region.

17. The semiconductor device of claim 13, further comprising: a first
well region within the substrate; a second well within the substrate, the
first and the second wells regions being in substantial contact with each
other through a transition region, the transition region being positioned
below the gate region.

18. The semiconductor device of claim 13, wherein the drain region and
first well region comprises: a first type of material.

19. The semiconductor device of claim 13, wherein the source region
comprises: a first type of material, and wherein the second well region
comprises: a second type of material, the first type of material being
different from the second type of material.

20. The semiconductor device of claim 13, further comprising: a silicide
region in substantial contact with the drain region and displaced from
the gate region by the dielectric region and a spacer.

Description:

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application is a continuation of U.S. patent
application Ser. No. 12/943,330, filed Nov. 10, 2010, which will issue as
U.S. Pat. No. 8,598,670 on Dec. 3, 2013, which is a continuation of U.S.
patent application Ser. No. 11/580,961, filed Oct. 16, 2006, now U.S.
Pat. No. 7,855,414, which claims the benefit of U.S. Provisional Patent
Appl. No. 60/833,787, filed Jul. 28, 2006, all of which is incorporated
herein by reference in their entirety.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention generally relates to semiconductors. More
specifically, the invention relates to increasing the breakdown voltage
of a semiconductor device.

[0004] 2. Background Art

[0005] Silicon semiconductor processing has evolved sophisticated
operations for fabricating integrated circuits. As advancement in
fabrication process technology continues, the operating voltage of the
integrated circuits has reduced, but the operating voltage of auxiliary
devices remains the same. Auxiliary devices are devices used in
conjunction with integrated circuits and can include printers, scanners,
disk drives, tape drives, microphones, speakers, cell phones and cameras
to provide some examples.

[0006] Auxiliary devices can operate at voltages above the breakdown
voltage of the transistors contained within the integrated circuit. As
the operating voltage applied to a transistor increases, the transistor
will eventually breakdown allowing an uncontrollable increase in current
to pass through the devices. Breakdown voltage is the voltage level where
this uncontrollable increase in current occurs. Examples of breakdown can
include punch-through, avalanche breakdown, and gate oxide breakdown to
provide some examples. Operating above the breakdown voltage for a
significant duration reduces the lifetime of the transistor.

[0007] Techniques are currently available to increase the voltage at which
breakdown occurs. These techniques can include the separate design of
input-output circuits using a high voltage process, double diffused drain
of other extended drain techniques, or the cascading of two individual
transistors to provide some examples. These techniques often increase the
fabrication cost by requiring additional process steps along with
additional substrate masking.

[0008] What is needed is a metal oxide semiconductor field effect
transistor (MOSFET) device and method for fabricating the same that
addresses one or more of the aforementioned shortcomings of conventional
MOSFET devices.

BRIEF DESCRIPTION OF THE DRAWINGS/FIGURES

[0009] The present invention is described with reference to the
accompanying drawings. In the drawings, like reference numbers indicate
identical or functionally similar elements. Additionally, the left most
digit(s) of a reference number identifies the drawing in which the
reference number first appears.

[0011]FIG. 2A illustrates a cross-sectional view of an n-type metal oxide
semiconductor (NMOS) structure according to an embodiment of the present
invention.

[0012]FIG. 2B illustrates a cross-sectional view of a p-type metal oxide
semiconductor (PMOS) structure according to an embodiment of the present
invention.

[0013]FIG. 3A illustrates a cross-sectional view of an n-type metal oxide
semiconductor (NMOS) structure with shallow trench isolation according to
an embodiment of the present invention.

[0014]FIG. 3B illustrates a cross-sectional view of a p-type metal oxide
semiconductor (PMOS) structure with shallow trench isolation according to
an embodiment of the present invention.

[0015] FIG. 4 illustrates an exemplary representation of a CMOS logic
foundry process used to fabricate an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0016] FIG. 1 illustrates a cross-sectional view of an n-type metal oxide
semiconductor (NMOS) structure 100 fabricated using a conventional CMOS
logic foundry technology. The conventional CMOS logic foundry technology
fabricates NMOS structure 100 onto a p-type substrate 102. Source 110 of
NMOS structure 100 includes N+ region 124 and N-LDD region 126. Likewise,
drain 114 of NMOS structure 100 includes N+ region 130 and N-LDD region
128. The "+" indicates that the region is implanted with a higher carrier
concentration than a region not designated by a "+." For instance, an N+
region generally has a greater number of excess electrons than an N-type
region. A P+ region typically has a greater number of excess holes than
the P-type substrate. N-LDD region 126 is in contact with N+ region 124
while N-LDD region 128 is in contact with N+ region 130. N-LDD region 126
and N-LDD region 128 are lightly implanted with n-type material to
provide a high resistance shallow diffusion region. N-LDD region 126
provides a high resistance shallow diffusion region from N+ region 124 to
gate 118 to reduce the effects of the electric field of N+ region 124.
N-LDD region 128 provides a high resistance shallow diffusion region from
N+ region 130 to gate 118 to reduce the effects of the electric field of
N+ region 130.

[0017] Shallow trench isolation regions 108a and 108b (hereinafter 108)
can provide isolation and protection for NMOS structure 100. Shallow
trench isolation region 108a is in contact with source 110 while shallow
trench isolation 108b is in contact with drain 114. Shallow trench
isolation region 108 is typically a dielectric material such as
SiO2, though any suitable material can be used Spacers 120a and 120b
(hereinafter a reference to spacer 120 will refer to spacers 120a and
120b while a reference to 120a or 120b will refer to that particular
spacer only) are included at the edges of the gate 118. Spacer 120a is
adjacent to source 110 and in contact with gate 118 while spacer 120b is
adjacent to drain 114 and in contact with gate 118. Spacers 120 are
typically a dielectric material, such as SiO2, though any suitable
material can be used A layer of silicide 116a, 116b, and 116c
(hereinafter 116) is formed upon source 110, gate 118, and drain 114 of
NMOS structure 100. The primary use of silicide, an alloy of metal and
silicon, is to form a low resistance interconnection between other
devices within the integrated circuit. Polycrystalline silicon a silicon
structure not having a single-crystalline structure, usually called "poly
Si" or "poly") gate 118 is located between source 110 and drain 114 on
top of gate oxide 112. A heavy implantation of n-type material into the
polycrystalline silicon generally forms gate 118.

[0018] A p-n junction is a potential barrier created by joining n-type and
p-type material. Without a bias voltage on gate 118, two p-n junctions
exist in series between source 110 and drain 114. One such junction is
located between drain 114 and substrate 102, and the other junction is
between the substrate 102 and source 110. These p-n junctions prevent
current conduction from source 110 to drain 114 upon the application of a
source to drain voltage. Upon grounding source 110 and applying a
positive voltage to gate 118, a voltage appears between gate 118 and
source 110. The positive voltage on gate 118 repels the positively
charged carrier holes from underneath gate oxide 112. The pushing away of
the carrier holes from gate oxide 112 interface into substrate 102 forms
a depletion region, or channel 122. Channel 122 is a carrier-depletion
region populated by the negative charge formed below the interface at
gate oxide 112 and substrate 102 by the electric field created between
gate 118 and substrate 102. In addition to repelling the carrier holes,
the positive gate voltage attracts carrier electrons from source 110 and
drain 114 into channel 122. When a sufficient number of carrier electrons
accumulate in channel 122, an n-type region is created connecting source
110 to drain 114. Applying a voltage between drain 114 and source 110
will cause current to flow through channel 122.

[0019] The amount of voltage applied between drain 114 and source 110 has
a limit. There is a point where the current passing through the p-n
junction increases uncontrollably resulting in breakdown. Breakdown
voltage is the voltage at which the p-n junctions breakdown. Examples of
breakdown can include avalanche breakdown, punch-through, and gate oxide
breakdown to provide some examples. As the voltage on drain 114 increases
the p-n junction between drain 114 and substrate 102 will eventually
suffer avalanche breakdown resulting in a rapid increase in current.
Avalanche breakdown results when carriers under the influence of an
electric field gain sufficient energy to break covalent bonds in atoms
with which they collide. The electric field accelerates these five
electrons to very high speeds knocking other electrons free from other
atoms. The electric field once again accelerates both the original
electron and the electron knocked free allowing both the original
electron and the electron knocked tree to strike other atoms knocking
more electrons free. As this process continues, an uncontrollable
increase it current occurs as a result of an exponential increase in the
number of free electrons moving through the material.

[0020] In addition to avalanche breakdown, the increase of voltage on
drain 114 can lead to another breakdown effect called punch through.
Punch through occurs when the voltage on drain 114 is increased to the
point causing the depletion region surrounding drain 114 to extend
through channel 122 to source 110 causing a rapid increase in current.
Related to punch through is the hot carrier effect. The hot carrier
effect refers to the effect of high energy electrons or holes generated
as a result of impact ionization at the drain side of the channel. These
high energy current carriers can leave the silicon and tunnel into gate
oxide 112 upon reaching a sufficiently high level of energy. For example,
the main cause of the channel hot electrons effect results from the
carrier electrons in channel 122 gaining sufficient energy to leave
substrate 102 and tunneling into gate oxide 112 causing degradation of
NMOS structure 100.

[0021] Further, as the operating voltage applied to a transistor
increases, the gate to source voltage will eventually cause a breakdown
of gate oxide 112. This breakdown of gate oxide 112, results permanent
damage to NMOS structure 100.

[0022]FIG. 2A illustrates a cross-sectional view of an n-type metal oxide
semiconductor (NMOS) structure according to an embodiment of the present
invention. The same conventional CMOS logic foundry technology as NMOS
structure 100 fabricates NMOS structure 200, but without the additional
masking or processing cost required by existing techniques.

[0024] Shallow trench isolation regions 108a and 108b can provide
isolation and protection for NMOS structure 200. Shallow trench isolation
region 108a is in contact with source 110, while shallow trench isolation
108b is in contact with drain 228. Polycrystalline silicon gate 218 is
located in between source 110 and drain 228 on top of gate oxide 112.
Channel 222 extends from source 110 to well transition 226 located
beneath gate 218. Spacers 120a and 120b are included at the ends of the
gate 218. Spacer 120a is adjacent to source 110 and in contact with gate
218 while spacer 120b is adjacent to drain 228 and in contact with gate
218. Placed upon source 110, gate 218, and drain 228 of NMOS structure
200 is a layer of silicide 116.

[0025] The resistance from drain 228 to source 110 is related to the point
at which punch through occurs. This resistance determines the point at
which the depletion region surrounding drain 228 extends through channel
222 to source 110. For example, a transistor with a greater drain to
source resistance requires a greater voltage for punch through to occur
than a transistor with a lesser drain to source resistance. An exemplary
embodiment of NMOS structure 200 displaces N+ region 130 from gate 218 by
displacement distance 224 and implants n-well 206 to form the overlap
region between gate 218 and drain 228 to increase the resistance from
drain 228 to source 110. Displacement distance 224 is the horizontal
distance from the edge of spacer 120b to N+ region 130. In an exemplary
embodiment, displacement distance 224 is 0.45 μm. To prevent the
carriers in channel 222 from prematurely leaving requires adjustment of
silicide 116c so that the region on top of substrate 102 between N+
region 130 and gate 218 lacks silicide. In other words, there is a gap in
the silicide layer between gate 218 and N+ region 130. The implantation
of N-well 206 is lighter than the implantation of N+ region 130. N-well
206 is necessary for the formation of channel 222 upon application of a
positive voltage to gate 218. Increasing the resistance from drain 228 to
source 110 with drain displacement and n-well implantation increases the
point required for the depletion region surrounding drain 228 extends
through channel 222 to source 110. As a result, the voltage at which
punch through occurs increases. In addition to increasing the voltage
required for punch through to occur, the displacement of N+ region 130
from gate 218 and implantation of n-well 206 onto NMOS structure 200
reduces the hot carrier effect. As a result in the increase in the
resistance from drain 228 to source 110, more energy is required for
current carriers to leave substrate 102 and tunnel into gate oxide 112.
For example, as compared to NMOS structure 100, because of the increase
in the resistance from drain 228 to source 110 of NMOS structure 200, the
carrier electrons in channel 222 of NMOS structure 200 require more
energy to leave substrate 102 and tunnel into gate oxide 112.

[0026] The point at which avalanche breakdown occurs relates to the
resistance from drain 228 to substrate 102. For example, a transistor
with a greater drain to substrate resistance has a greater avalanche
breakdown voltage than a transistor with a lesser drain to substrate
resistance. This resistance decreases the influence of the electric field
on the drain requiring more energy for the carriers to break covalent
bonds in atoms with which they collide. An exemplary embodiment of NMOS
structure 200 uses n-well 206 to increase the resistance from drain 228
to substrate 102. Implantation of n-well 206 creates a larger n-type
region in NMOS structure 200 as compared to NMOS structure 100. The
n-type region in NMOS structure 200 comprises both N+ region 130 and
n-well 206. As a result of this larger n-type region, the p-n junction
between the n-type region and substrate 102 is larger, thereby increasing
resistance from drain 228 to substrate 102. For an equivalent drain
region, the resistance from drain 228 to substrate 102 for NMOS structure
200 is greater than the resistance from drain 228 to substrate 102 for
NMOS structure 100. The increase in resistance from drain 228 to
substrate 102 in NMOS structure 200 requires a larger voltage to
accelerate carrier electrons to knock free atoms.

[0027] The point at which the breakdown of the gate oxide occurs relates
to the height of gate oxide 112. For example, a transistor with a greater
gate oxide height has a greater gate oxide breakdown voltage than a
transistor with a lesser gate oxide height. An exemplary embodiment of
NMOS structure 200 uses the principal of poly depletion to increase both
the effective thickness of gate oxide 112 and the voltage at which
breakdown of gate oxide 112 occurs. Poly depletion is a parasitic effect
whereby a voltage drop across the gate of a transistor causes the
formation of a depletion layer. This depletion layer depletes the gate of
current carriers increasing the effective gate oxide thickness.
Fabrication of the gate with either heavily implanted poly silicon or a
metal minimizes the effect of poly depletion. By fabricating the gate
with either heavily implanted poly silicon or metal provides the gate
with excess of current carriers making the formation of a depletion layer
across the gate more difficult.

[0028] Another exemplary embodiment of the present invention lightly
implants gate 218 with an n-type material to form an N- region. The "-"
indicates that the region is implanted with a lower carrier concentration
than a region not designated by a "-." For instance, a P- region
typically has a lesser number of excess carrier holes than a P+ region.
An N- region generally has a lesser number of excess carrier electrons
than an N+ region. In one embodiment, gate 218 of NMOS structure 200 is
lightly implanted with n-type material on the order of 1018 as
compared to the heavy implantation on the order of 1020 for gate 118
of NMOS structure 100. The removal of excess electrons in NMOS structure
200 makes the formation of a depletion layer across gate 218 easier as
compared to NMOS structure 100, thereby increasing the effective
thickness of gate oxide 112. As a result of the increased effective
thickness of gate oxide 112, the point at which the breakdown of gate
oxide 112 occurs is increased.

[0029] The threshold voltage is the gate to source voltage at which a
sufficient number of mobile electrons accumulate in channel 222 to form a
conducting channel. The p-type substrate used to fabricate NMOS structure
200 contains more carrier holes as compared to carrier electrons. By
applying a voltage to gate 218, the corresponding electric field causes
the carrier electrons in the substrate to become concentrated at the
region of substrate 102 nearest gate 218. A depletion region forms when
the concentration of carrier electrons is equal to that of the carrier
holes. NMOS structure 200 turns on when voltage applied at gate 218 is
larger than the threshold voltage. NMOS structure 200 turns on because
there are more carrier electrons than carrier holes in substrate 102 near
gate 218. To increase the number of holes located in substrate 102, NMOS
structure 200 implants p-well 204 starting from shallow isolation 108a,
extending beneath source 110, and terminating at well transition 226.
Well transition 226 is a region in substrate 102 where a region comprised
of p-well 204 changes to a region comprised of n-well 206. By increasing
the number of holes in substrate 102, formation of the depletion region
requires a greater number of electrons. Implanting p-well 204 onto
substrate 102 in NMOS structure 200 increases the threshold voltage, as
more electrons are required to accumulate in channel 222. In an exemplary
embodiment, well transition 226 is displaced horizontally 0.2 μm from
the edge of gate 218 adjacent to drain 228.

[0030]FIG. 2B illustrates a cross-sectional view of a p-type metal oxide
semiconductor (PMOS) structure according to an embodiment of the present
invention. The same conventional CMOS logic foundry technology as NMOS
structure 100 also fabricates PMOS structure 250, but without the
additional masking or processing cost required by existing techniques.

[0031] The conventional CMOS logic foundry technology fabricates PMOS
structure 250 by implanting a deep n-well 272 onto a p-type substrate
102. P-LDD region 276 is in contact with P+ region 274. P-LDD region 276
is lightly implanted with p-type material to provide a high resistance
shallow diffusion region. P-LDD region 276 provides a high resistance
shallow diffusion region from P+ region 274 to gate 268 to reduce the
effects of the electric field of P+ region 274. In contact with deep
n-well 272 are n-well 254 and p-well 256. Drain 264 of PMOS structure 250
includes P+ region 278 and P-well 206. Well transition 276 is a region in
substrate 102 where a region comprised of n-well 154 changes to a region
comprised of p-well 256. Shallow trench isolation regions 108a and 108b
can provide isolation and protection for PMOS structure 250. Shallow
trench isolation region 108a is in contact with source 260, while shallow
trench isolation 108b is in contact with drain 264. Polycrystalline
silicon gate 268 is located in between source 260 and drain 264 on top of
gate oxide 112. Channel 222 extends from source 260 to well transition
276 located beneath gate 268. Spacers 120a and 120b are included at the
ends of the gate 268. Spacer 120a is adjacent to source 260 and in
contact with gate 268 while spacer 120b is adjacent to drain 264 and in
contact with gate 268. Placed upon source 260, gate 218, and drain 264 of
NMOS structure 200 is a layer of silicide 116.

[0032] PMOS structure 250 increases the point at which breakdown occurs by
the same techniques as NMOS structure 200. An exemplary embodiment of
PMOS structure 250 displaces P+ region 278 from gate 268 by displacement
distance 224 and implants p-well 256 to increase the voltage at which
both punch through and the hot carrier effect occur by increasing the
resistance from drain 264 to source 260. Another exemplary embodiment of
PMOS structure 250 uses p-well 256 to increase the voltage at which
avalanche breakdown occurs by increasing resistance from drain 264 to
substrate 102. A further exemplary embodiment of PMOS structure 250
raises the breakdown point of gate oxide 112 by lightly implanting gate
268 with a p-type material to form a P- region. Those skilled in the art
will recognize that PMOS structure 250 operates in a manner similar to
that of NMOS structure 200.

[0033]FIG. 3A illustrates a cross-sectional view of an n-type metal oxide
semiconductor (NMOS) structure with shallow trench isolation according to
an embodiment of the present invention. The same conventional CMOS logic
foundry technology as NMOS structure 100 also fabricates NMOS structure
300, but without the additional masking or processing cost required by
existing techniques.

[0035] Shallow trench isolation region 108a is in contact with source 110,
while shallow trench isolation 108b is in contact with drain 228. Placed
in between drain 228 and gate 218 is a third shallow trench isolation
region 326. Polycrystalline silicon gate 218 is located in between source
110 and drain 228 on top of gate oxide 112. Channel 222 extends from
source 110 to well transition 226 located beneath gate 218. Spacers 120a
and 120b are included at the ends of the gate 218. Spacers 120a and 120b
are included at the ends of the gate 218. Spacer 120a is adjacent to
source 110 and in contact with gate 218 while spacer 120b is adjacent to
drain 228 and in contact with gate 218. Placed upon source 110, gate 218,
and drain 228 of NMOS structure 300 is a layer of silicide 116.

[0036] NMOS structure 300 increases point at which breakdown occurs by the
same techniques as NMOS structure 200. An exemplary embodiment of NMOS
structure 300 displaces N+ region 130 from gate 218 by displacement
distance 224 and implants n-well 106 to increase the voltage at which
both punch through and the hot carrier effect occur by increasing the
resistance from drain 228 to source 110. In addition to the techniques
used in NMOS structure 200, another exemplary embodiment of NMOS
structure 300 includes a shallow trench isolation region 326. Shallow
trench isolation region 326 is generally constructed with a dielectric
material such as SiO2, though any suitable material can be used. The
current flowing through channel 222 must circumvent shallow trench
isolation region 326 thereby further increasing the resistance from drain
228 to source 110 of NMOS structure 300 when compared with NMOS structure
200. As a result, the voltage where punch through and hot carrier effect
occurs is greater for NMOS structure 300. Another further exemplary
embodiment of NMOS structure 300 uses n-well 106 to increase the voltage
at which avalanche breakdown occurs by increasing resistance from drain
228 to substrate 102. An additional exemplary embodiment of NMOS
structure 300 raises the breakdown point of gate oxide 112 by lightly
implanting gate 218 with an n-type material to form an N- region. Those
skilled in the art will recognize that NMOS structure 300 operates in a
manner similar to that of NMOS structure 200.

[0037]FIG. 3B illustrates a cross-sectional view of a P-type metal oxide
semiconductor PMOS) structure with shallow trench isolation according to
an embodiment of the present invention. The same conventional CMOS logic
foundry technology as NMOS structure 100 also fabricates PMOS structure
350, but without the additional masking or processing cost required by
existing techniques.

[0038] The conventional CMOS logic foundry technology fabricates PMOS
structure 350 by implanting a deep n-well 272 onto a p-type substrate
102. P-LDD region 276 is in contact with P+ region 274. P-LDD region 276
is lightly implanted with p-type material to provide a high resistance
shallow diffusion region. P-LDD region 276 provides a high resistance
shallow diffusion region from P+ region 274 to gate 268 to reduce the
effects of the electric field of P+ region 274. In contact with deep
n-well 272 are n-well 254 and p-well 256. Drain 264 of PMOS structure 250
includes P+ region 278 and p-well 256. Well transition 276 is a region in
substrate 102 where a region comprised of n-well 254 changes to a region
comprised of p-well 256.

[0039] Shallow trench isolation regions 108a and 108b can provide
isolation and protection for PMOS structure 350. Shallow trench isolation
region 108a is in contact with source 260, while shallow trench isolation
108b is in contact with drain 264. Placed in between drain 264 and gate
268 is a third shallow trench isolation region 376. Polycrystalline
silicon gate 268 is located in between source 260 and drain 264 on top of
gate oxide 112. Channel 222 extends from source 260 to well transition
276 located beneath gate 268. Spacers 120a and 120b are included at the
ends of the gate 268. Spacer 120a is adjacent to source 260 and in
contact with gate 268 while spacer 120b is adjacent to drain 264 and in
contact with gate 268. Placed upon source 260, gate 268, and drain 264 of
PMOS structure 350 is a layer of silicide 116.

[0040] PMOS structure 350 increases point at which breakdown occurs by the
same techniques as NMOS structure 200. An exemplary embodiment of PMOS
structure 350 displaces P+ region 278 from gate 268 by displacement
distance 224 and implants p-well 256 to increase the voltage at which
both punch through and the hot carrier effect occur by increasing the
resistance from drain 264 to source 260. In addition to the techniques
used in NMOS structure 200, another exemplary embodiment of NMOS
structure 300 includes a shallow trench isolation region 326. Shallow
trench isolation region 326 is generally constructed with a dielectric
material such as SiO2, though any suitable material can be used. The
current flowing through channel 222 must circumvent shallow trench
isolation region 376 thereby further increasing the resistance from drain
264 to source 260 of PMOS structure 350 when compared with PMOS structure
250. As a result, the voltage where punch through and hot carrier effect
occurs is greater for PMOS structure 350. Another further exemplary
embodiment of PMOS structure 350 uses p-well 256 to increase the voltage
at which avalanche breakdown occurs by increasing resistance from drain
264 to substrate 102. An additional exemplary embodiment of PMOS
structure 350 raises the breakdown point of gate oxide 112 by lightly
implanting gate 268 with a p-type material to form a P- region. Those
skilled in the art will recognize that PMOS structure 350 operates in a
manner similar to that of NMOS structure 200.

[0042] Fabricate p-well and n-well, denoted as 402, entails implanting a
semiconductor substrate with an appropriate impurity to form a p-well or
an n-well. Implanting the substrate with boron, a p-type material, forms
the p-well, while implanting the substrate with phosphorous or arsenic,
both n-type materials, forms the n-well. For an NMOS device, the p-well
is located beneath source while the n-well is located beneath the drain.
For a PMOS, device the p-well is located beneath the drain while the
n-well is located beneath the source. In both instances, the p-well and
n-well are in contact with one another forming a transition region
whereby the impurity implanted onto the substrate changes from p-type
material to n-type material: no isolation region exists in between the
n-well and p-well. This transition region is located beneath the gate. In
exemplary embodiment, the transition region where the n-well and p-well
contact is beneath the gate and horizontally displaced 0.2 μm from the
edge of the gate adjacent to the drain.

[0043] Fabricate shallow trench isolation regions, denoted as 404, entails
depositing an etched semiconductor substrate with a dielectric material
such as SiO2, though any suitable material can be used, to form
shallow trench isolation regions. Fabricating a shallow trench isolation
region adjacent to the drain and another shallow trench isolation region
adjacent to the source provides isolation and protection to the
transistor. Depositing an additional shallow trench isolation region in
between the gate and the drain increases the breakdown voltage of the
transistor.

[0044] Fabricate gate, denoted as 406, entails implanting a semiconductor
substrate with polycrystalline silicon, though any suitable material can
be used, on top of a gate oxide to form the gate. Lightly implanting the
polycrystalline silicon with the appropriate impurity increases the
breakdown voltage of the transistor. Lightly implanting n-type material
onto the polycrystalline silicon to form an N- region creates the gate of
an NMOS device, while lightly implanting p-type material polycrystalline
silicon to form a P- region creates the gate of a PMOS device. In
exemplary embodiment, the gate is lightly implanted on the order of
1018.

[0045] Fabricate LDD, denoted as 408, entails implanting a semiconductor
substrate with an appropriate impurity to form a LDD region. For example,
lightly implanting the substrate with either phosphorous or arsenic, both
n-type materials, to create an N- region forms the LDD for an NMOS
device. Lightly implanting the substrate with boron, a p-type material,
to create a P- region forms the LDD for a PMOS device. When fabricating
the LDD for either an NMOS or PMOS device, a portion of the carrier
region comprising the LDD overlaps the gate.

[0046] Fabricate spacers, denoted as 410, entails depositing a dielectric
material such as SiO2, though any suitable material can be used on
top of a semiconductor substrate to form spacers. Each edge of the gate
contains a spacer. In other words, one spacer is adjacent to the source
and in contact with the gate while another spacer is adjacent to drain
and in contact with the gate.

[0047] Fabricate source and drain, denoted as 412, entails implanting a
semiconductor substrate with an appropriate impurity to form a source and
a drain. Heavily implanting the substrate with either phosphorous or
arsenic, both n-type materials, to create and N+ region forms the source
and the drain for an NMOS device. Heavily implanting the substrate with
boron, a p-type material, to create a P+ region forms the source and the
drain for a PMOS device. When fabricating the source or the drain for
either an NMOS or PMOS device, there is no overlap between the gate and
the carrier region comprising the source and the drain. The entire region
comprising the drain is horizontally displaced a specified distance from
the gate. In an exemplary embodiment, the entire drain region is
displaced 0.45 μm from the junction between the gate and a spacer in
contact with the gate.

[0048] Fabricate silicide region, denoted as 414, entails depositing metal
on top of poly silicon and then alloy to create silicide, though any
suitable material can be used, on top of the gate, the source, and the
drain of a transistor to form the connection between the fabricated
transistor and a metallization layer. The metallization layer forms the
interconnections between the fabricated transistor and other devices. In
an embodiment, the region of the semiconductor substrate in between the
gate and the drain lacks silicide. In other words, there is a gap in the
silicide layer between the gate and the drain, requiring the removal of
any silicide in this region.

CONCLUSION

[0049] Example embodiments of the methods, systems, and components of the
present invention have been described herein. As noted elsewhere, these
example embodiments have been described for illustrative purposes only,
and are not limiting. Other embodiments are possible and are covered by
the invention. Such other embodiments will be apparent to persons skilled
in the relevant art(s) based on the teachings contained herein. Thus, the
breadth and scope of the present invention should not be limited by any
of the above described exemplary embodiments, but should be defined only
in accordance with the following claims and their equivalents.

Patent applications by Akira Ito, Irvine, CA US

Patent applications by Henry Kuo-Shun Chen, Irvine, CA US

Patent applications by BROADCOM CORPORATION

Patent applications in class With means to increase breakdown voltage

Patent applications in all subclasses With means to increase breakdown voltage