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004 : Parallel/Series Merge and Reduction of Devices

The number of devices and the connection order might be different between the schematic and the layout in the following cases.

A gate width is increased by connecting several MOS devices in parallel.

One device in the schematic is composed of several devices in the layout.

The connection of the MOS devices forming a logic gate is different in the schematic and the layout.

The degree of freedom of the comparison can be improved by merging and reducing these devices.

2. Parallel Merge

The Parallel merge option merges devices of the same type that are connected in parallel into one element, regardless of the number of terminals (see par_mer.png
).

3. Series Merge

3.1. Passive Element Series Merge
The Series merge option merges devices of the same type that are connected in series into a single element. A pair of terminal devices must be connected to the same net in order to merge into one element (see ser_mer_pas.png
).

3.2. MOS, JFET and MESFET Series Merge
MOS, JFET, and MESFET devices with a common gate, and connected by their source/drain, can be merged into one element (see ser_mer.png
).

4. MOS, JFET, MESFET and Bipolar Parallel Reduction

The MOS, JFET, MESFET and Bipolar Parallel reduction option reduces the same type MOS, JFET, MESFET or bipolar transistors to a single element if they are connected in parallel with different gate (base) terminals. Once they are reduced, the resulting device will have swappable gate (base) terminals (see par_red.png
).

5. MOS, JFET, MESFET and Bipolar Series Reduction

The MOS, JFET, MESFET and Bipolar Series reduction option reduces the same type MOS, JFET, MESFET or bipolar transistors to a single element if they are connected in series with different gate (base) terminals. Once they are reduced, the resulting device will have swappable gate (base) terminals (see ser_red.png
).

6. Setting of Merge/Reduction

Merge/reduction is set in the Models tab in the Project Settings dialog (see project_settings.png
).

7. Execution of Parallel Merge

1) Launch Guardian LVS from Expert by selecting Verification->LVS->Launch LVS .
2) Load par_mer.gpr by clicking the Load button at the bottom of the Project Settings dialog.
3) Run LVS.
4) Check the LVS result. The netlists are NOT EQUIVALENT message will be displayed in the LVS log.
5) Turn on the Parallel merge option in the Models tab, and run LVS.
6) Check the LVS result. The message netlists are EQUIVALENT will be displayed.

8. Execution of Series Merge

1) Launch Guardian LVS .
2) Load ser_mer.gpr .
3) Run LVS.
4) Check the LVS result. The message netlists are NOT EQUIVALENT will be displayed.
5) Turn on the Series merge option in the Models tab, and run LVS.
6) Check the LVS result. The message netlists are EQUIVALENT will be displayed.

9. Execution of Parallel/Series Reduction

1) Launch Guardian LVS .
2) Load par_ser_red.gpr .
3) Run LVS.
4) Check the LVS result. The message netlists are topologically EQUIVALENT, and label mismatch is detected will be displayed.
5) Turn on the Parallel reduction and Series reduction options in the Models tab, and run LVS.
6) Check the LVS result. The message netlists are EQUIVALENT will be displayed.