Abstract:

A driver circuit provides fast settling times, slew rate control, and
power efficiency, while reducing the need for large external capacitors.
A voltage reference circuit generates a voltage reference signal. A
comparator compares the voltage reference signal and a driver output
signal and generates an output high voltage control signal. An output
driver includes a first and a second switch that are coupled together.
The first and second switches are further coupled to generate the driver
output signal in response to coupling the output high voltage control
signal to the control terminal of the first switch and coupling an input
signal to the control terminal of the second switch.

Claims:

1. A driver circuit, comprising:a voltage reference circuit that is
coupled to generate a voltage reference signal;a comparator that is
coupled to compare the voltage reference signal and a driver output
signal to generate an output high voltage control signal; andan output
driver comprising a first switch coupled to a second switch to generate
the driver output signal in response to the output high voltage control
signal and a first input signal.

2. The apparatus of claim 1, wherein the output high voltage control
signal is coupled to the first switch.

3. The apparatus of claim 1, wherein the input signal is coupled to the
second switch.

4. The apparatus of claim 1 wherein the voltage reference circuit is
programmable to select a desired output voltage for an output high level
of the driver output signal.

5. The apparatus of claim 1, further comprising a capacitor that is
coupled between ground and a node of the output driver from which the
output signal is generated.

6. The apparatus of claim 1, wherein the capacitor is external to a
substrate that comprises the output driver.

7. The apparatus of claim 1, further comprising a native mode transistor
that is coupled to the first and second switches.

8. The apparatus of claim 7, wherein the native mode transistor is an NMOS
transistor having a gate that is coupled to the voltage reference
circuit.

9. The apparatus of claim 1, further comprising a third switch that is
coupled to the first and second switch, wherein second and third switches
are complementary transistors and wherein a signal that is inverted from
the input signal is coupled to a gate of the third switch.

10. The apparatus of claim 9, further comprising a capacitor that is
coupled between ground and a node of the output driver from which the
output signal is generated.

11. The apparatus of claim 10, further comprising a third and fourth
switch that are coupled to the first and second switch, wherein second
and third switches are complementary transistors, wherein a signal that
is inverted from the input signal is coupled to a gate of the third
switch, and wherein the fourth switch is a native-mode NMOS transistor
having a gate that is coupled to the voltage reference circuit.

12. The apparatus of claim 1, wherein a capacitor that is not formed in a
same substrate of the driver circuit is not coupled to a node of the
output driver from which the output signal is generated.

13. The apparatus of claim 1, wherein a capacitance is 0.1 μF or
greater at a node of the output driver from which the output voltage is
generated.

14. A method, comprising:generating a reference voltage in response to a
voltage select signal;comparing a driver output signal to the reference
voltage to generate an output high voltage control signal; andgenerating
the driver output signal in response to a received input signal and the
output high voltage control signal.

15. The method of claim 14, further comprising providing a capacitance of
0.1 μF or greater at a node of the output driver from which the output
signal is generated.

16. The method of claim 14, further comprising arranging a native-mode
NMOS transistor to the first and second switches, the native-mode NMOS
transistor having a gate coupled to the reference voltage, and whereby a
slew rate of the driver output signal is further limited.

17. A transmitter, comprising:a programmable voltage reference circuit
that is coupled to generate a voltage reference signal;a comparator that
is coupled to compare the voltage reference signal and a driver output
signal and in response to generate an output high voltage control signal;
andan output driver comprising a first switch coupled to a second switch
to generate the driver output signal at an output node in response to the
output high voltage control signal and a received input signal, wherein
the output driver is arranged to decouple the output node from a power
supply in response to a power down signal.

18. The apparatus of claim 17, further comprising a capacitor that is
coupled between ground and the output node.

19. The apparatus of claim 18 wherein the capacitor is external to a
substrate that comprises the output driver and has a capacitance that is
0.1 μF or greater.

20. The apparatus of claim 17, further comprising a third switch that is
coupled to the first and second switch, wherein second and third switches
are complementary transistors and wherein a signal that is inverted from
the input signal is coupled to a gate of the third switch.

21. The apparatus of claim 20, further comprising a capacitor that is
coupled between ground and a node of the output driver from which the
output signal is generated.

22. The apparatus of claim 17, further comprising a third and fourth
switch that are coupled to the first and second switch, wherein second
and third switches are complementary transistors, wherein a signal that
is inverted from the input signal is coupled to a gate of the third
switch, and wherein the fourth switch is a native-mode NMOS transistor
having a gate that is coupled to the voltage reference circuit.

23. The apparatus of claim 22, wherein a capacitor that is not formed in a
same substrate of the driver circuit is not coupled to the output node.

Description:

TECHNICAL FIELD

[0001]This disclosure relates generally to regulators, and more
particularly, but not exclusively, relates to hybrid regulators for
integrated circuits.

BACKGROUND INFORMATION

[0002]In modern complementary metal oxide silicon (CMOS) technology, data
output circuits are generally implemented by a push-pull drive circuit.
Push-pull drive circuits include a pull-up device and a pull-down device.
The pull-up device generally uses PMOSFET to drive an output terminal to
a power supply voltage. The pull-down device generally uses NMOSFET to
drive an output terminal to a ground voltage. However, when different
voltage levels of power supplies are used to implement logic high voltage
(VOH) between two separate chips, to have the same logic high voltage, it
is necessary to limit output high voltage (VOH) from the higher power
supply output drive circuit. This disclosure shows a circuit that limits
output high voltage to a reference voltage level.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003]Non-limiting and non-exhaustive embodiments of the disclosure are
described with reference to the following figures, wherein like reference
numerals refer to like parts throughout the various views unless
otherwise specified.

[0004]FIG. 1 is an illustration of sample MIPI PHY output line levels.

[0005]FIG. 2 is an illustration of a driver circuit using a conventional
voltage regulator.

[0006]FIG. 3 is an illustration of a sample output voltage generation
circuit.

[0007]FIG. 4 is an illustration of a sample output voltage generation
circuit having stabilization using a native NMOS/NMOS transistor.

[0008]FIG. 5 is an illustration of a sample output driver having
capacitive circuit and a predriver circuit.

[0009]FIG. 6 is an illustration of a sample output driver having a
predriver circuit and stabilization using a native NMOS/NMOS transistor.

DETAILED DESCRIPTION

[0010]Embodiments of a hybrid on-chip regulator for limited output high
voltages are described herein. In the following description numerous
specific details are set forth to provide a thorough understanding of the
embodiments. One skilled in the relevant art will recognize, however,
that the techniques described herein can be practiced without one or more
of the specific details, or with other methods, components, materials,
etc. In other instances, well-known structures, materials, or operations
are not shown or described in detail to avoid obscuring certain aspects.

[0011]Reference throughout this specification to "one embodiment" or "an
embodiment" means that a particular feature, structure, or characteristic
described in connection with the embodiment is included in at least one
embodiment of the present invention. Thus, the appearances of the phrases
"in one embodiment" or "in an embodiment" in various places throughout
this specification are not necessarily all referring to the same
embodiment. Furthermore, the particular features, structures, or
characteristics may be combined in any suitable manner in one or more
embodiments.

[0012]In general, various high speed differential serial link standards
have been designed to accommodate increased off-chip data rate
communications. High speed USB, firewire (IEEE-1394), serial ATA and SCSI
are a few of the standards used for serial data transmission in the PC
industry. Low voltage differential signaling (LVDS) has also been
implemented in transmission-side serial data communications.

[0013]Additionally, vendors (such as cellular phone companies) have
proposed a "subLVDS" standard, which is a smaller voltage-swing variant
of the LVDS standard. SubLVDS has been suggested for use in the Compact
Camera Port 2 (CCP2) specification for serial communications between (for
example) image sensors and onboard systems.

[0014]CCP2 is part of the Standard Mobile Imaging Architecture (SMIA)
standard. Typical LVDS/subLVDS levels have an output common mode level
(Vcm) between supply voltages VDD and VSS. For example, transmitters (Tx)
for CCP2 normally have an output signal swing (Vod) of 150 mV with center
voltage Vcm at 0.9V.

[0015]In addition to high speed data (such as image data), low speed chip
control signals are often transmitted between host and client. Several
new protocols have been developed for high speed ("HS") to low power
("LP") state changes using common mode levels. A joint effort among
various cellular phone companies has defined a new physical layer (PHY)
standard. The PHY standard defines the Mobile Industry Processor
Interface (MIPI), which combines high speed image data transmission and
low speed control signals in a single communication signal path ("lane").

[0016]FIG. 1 is an illustration of sample MIPI PHY output line levels. A
transmitter functions (such as a "lane state") can be programmed by
driving the lane with certain line levels. For example, the high speed
transmission (HS-TX) drives the lane differentially with a low common
mode voltage level (Vcm: 0.2V) and small amplitude (Vod: 0.2 V). In the
HS-TX state the logic high level (Voh: 0.3V) of HS-TX is relatively much
lower than VDD.

[0017]During low speed transmission (LP-TX), the output signal normally
toggles between 0V and 1.2V. To signal a transition from the HS-TX to the
LP-TX state, an LP logic high is presented at the same time on both
output pads (Dp and Dn) by toggling the Vcm from a low level of 0.2V to a
high level of 1.2V. A receiver (coupled to the output of the transmitter)
on the client side adjusts its receiving state from HS to LP in response
to the asserted LP logic high presentation.

[0018]The MIPI standard specifies a high speed serial interface between
components inside a mobile device. As discussed above, the MIPI standard
low power signal specifies an output voltage swing of 1.2 volts having a
relatively slow rise and fall time. The 1.2 volts of output high voltage
is not normally the same as the power supply voltage provided by many
semiconductor technologies. The low power driver typically has a separate
1.2 volt power supply, which is normally driven from a regulator output
or from an output voltage limiting circuit.

[0019]The peak current of a low power driver can be over twenty milliamps
because the low power driver typically drives high capacitive loads while
it may power as many as six drivers working at the same time. When
voltage regulators are used to provide a 1.2 volt power supply for a
conventional push-pull CMOS low speed driver (as illustrated in FIG. 2
below), an external capacitor (having an example capacitance of 0.1
μF, for example) holds the Voh value and reduces the voltage ripple in
the output voltage. Such an approach adds an extra I/O (input/output)
pad, and cost, and increases components and space requirements of the
system.

[0020]FIG. 2 is an illustration of a driver circuit using a conventional
voltage regulator. Circuit 200 includes voltage regulator 210, pre-driver
220, PMOS transistor 230, NMOS transistor 240, and external capacitor
550. In operation, the power supply voltage for circuit 200 is generated
by the voltage regulator 210, which limits the logic high level of the
output signal. The output voltage of voltage regulator 210 is often used
as the supply voltage for as many as eight push-pull CMOS output driver
circuits. A push-pull CMOS output driver circuit can be formed by
coupling transistor 230 with transistor 240 in series as shown in the
Figure.

[0021]However, when the load current of the output driver circuit is
relatively high, voltage regulator 210 normally requires, for example, a
correspondingly larger capacitive value. An external capacitor is
typically used because the capacitive value required by many applications
is typically 0.1 μF or larger (which can be considered to be larger
than a capacitive value that can be economically supplied by a structure
in the integrated circuit).

[0022]The load current of the output can be defined using magnitude I and
time T. The load current can be supplied by the voltage regulator 210 for
providing a sufficient charge to keep the output voltage within specified
limits. The amount of charge (Q) is the product of capacitance (C) and
(V); thus. Q=IT=CV.

[0023]A regulator loop (which typically entails response times of greater
than 100 ns) is typically used to maintain a voltage of the output when
there is a change in the load current. The large capacitance of the
external capacitor serves to (temporarily) reduce an output voltage
change when the load current changes. When extra charge can be provided
by the external capacitor, the cumulative voltage drop of the output
voltage can be reduced considerably. When the length of time of the
cumulative voltage drop is at least as tong as the regulator loop
response time, the voltage drop can be corrected by the regulator loop,
which increases the regulator output voltage. Thus, at least a small
voltage ripple in the regulator output is usually encountered because of
the relatively long response time of the regulator loop.

[0024]When the external capacitor is not sufficiently large, the charge
provided by the external capacitor does not substantially reduce the
voltage drop over longer times. When the regulator loop corrects for the
voltage drop, the regulator loop may overshoot the desired regulated
voltage by reacting too strongly to the voltage drop. Likewise, the
regulator loop may undershoot the desired regulated voltage by reacting
to strongly to a voltage rise. The over (and under) shooting can cause
ripple in the regulator output voltage.

[0025]A reference voltage can also be used to limit the output high
voltage. When a reference voltage is applied to the gate of an NMOS
transistor, an output high voltage is generated at a level that is an
NMOS threshold (Vtn) below the reference voltage. The difference of the
output high voltage and the reference voltage can be 0.4-0.8 volts,
depending, on the process technology, and thus is often unsuited for
applications where the level of the output high voltage is specified to
be close to the reference voltage. Additionally, the level of the output
high voltage can vary over process corner conditions, supply voltage,
differences and changes in operating temperatures when using a
gate-coupled reference voltage without a feedback loop adjustment.

[0026]FIG. 3 is an illustration of a sample output voltage generator.
Output voltage generator 300 includes a voltage reference circuit 310,
output driver 320, comparator 330, and an output capacitance represented
by capacitor 340. Voltage reference circuit 310 can be programmable to
select a desired voltage for clamping the output voltage. Output driver
320 includes switches 321 and 322. In an embodiment, switches 321 and 322
are PMOS transistors, where each transistor has a gate for the control
terminal and a source and drain as non-control terminals.

[0027]The output of voltage reference circuit 310 is coupled to an
inverting input of comparator 330. The output of output driver 320 is
coupled to a non inverting input of comparator 330. The output of
comparator 330 is coupled to a control terminal of switch 321 (in output
driver 320). Switch 321 has a first non-control terminal coupled to a
power supply and a second non-control terminal coupled to a first
non-control terminal of switch 322. Switch 322 has a control terminal
that is coupled to a power down signal. The second non-control terminal
of switch 322 is coupled to a first terminal of the capacitor 340 (and to
the non-inverting terminal of comparator 330). A second terminal of
capacitor 340 is coupled to ground.

[0028]The voltage reference circuit of output voltage generator 300 is
coupled to generate a voltage reference signal. A comparator is coupled
to compare the voltage reference signal and a driver output voltage and
in response to turn on and off the current path for the final driver
output (not shown in this figure). An output voltage generator includes a
first and a second switch that are coupled (for example, in series such
that at least part of the current flowing through the first switch flows
through the second switch). The first and second switches are further
coupled to generate the driver output voltage in response to coupling the
output high voltage control signal to the control terminal of the first
switch.

[0029]In operation, output driver 300 uses the reference voltage signal to
limit the output high voltage. The power down signal can be used to drive
the gate of switch 322. When switch 321 is closed (conducting), the
driver output signal is driven in response to the power down signal. In
another embodiment, the power down signal conserves power when
transmission is not needed.

[0030]The reference voltage signal is compared with the driver output
voltage of output driver 320 so that an output high voltage control
signal is generated. When the driver output signal reaches the reference
voltage signal (when both switches 321 and 322 are closed), the output
high voltage control signal turns off the current path of output driver
320 by opening switch 321. Capacitor 340 provides a large load
capacitance that allows comparator 320 to respond quickly enough (with
respect to the response time of the feedback path of the of comparator
330) to turn off the current path so that feedback path is stabilized.
The load capacitance normally includes capacitive (parasitic or
otherwise) structures in the transmission path of the output signal.
Either (or both) switch 321 and 322 can be opened to conserve power for a
power-down mode.

[0031]FIG. 4 is an illustration of a sample output driver having
stabilization using a native NMOS transistor. Output driver 400 includes
a voltage reference circuit 410, output driver 420, comparator 430, and
output capacitance represented by capacitor 440. Voltage reference
circuit 410 can be programmable to select a desired voltage for the
output high level of the output voltage. Capacitor 440 can be a
capacitive load and/or energy storage device. Output driver 420 includes
switches 421, 422, and 423. In an embodiment, switches 421 and 422 are
PMOS transistors, and switch 423 is a "native" NMOS transistor. Native
NMOS typically has a threshold voltage that approaches 0 volts, and
conducts current until the voltage difference between gate and source
becomes 0 volts. Each transistor has a gate for the control terminal and
a source and drain as non-control terminals.

[0032]The output of voltage reference circuit 410 is coupled to the
control terminal of switch 423 and an inverting input of comparator 430.
The output voltage of output driver 420 (at the second non-control
terminal of switch 423) is coupled to a non-inverting input of comparator
430. The output of comparator 430 is coupled to a control terminal of
switch 422 (in output driver 420). Switch 422 has a first non-control
terminal coupled to first non-control terminal of switch 423 and a second
non-control terminal coupled to a second non-control terminal of switch
421. Switch 421 has a control terminal that is coupled to a power down
signal. The first non-control terminal of switch 421 is coupled to a
power supply. The second non-control terminal of switch 423 is coupled to
a transmission line and optionally to a first terminal of the capacitor
440. A second terminal of capacitor 440 is coupled to ground.

[0033]In operation, output driver 400 uses the reference voltage signal to
limit the output high voltage. The power down signal can be used to drive
the gate of switch 421. When switch 422 is closed (conducting), the
driver output signal is driven in response to the power down signal.

[0034]The reference voltage signal is compared with the driver output
signal of output driver 420 so that an output high voltage control signal
is generated. When the output voltage transitions from low to high,
(native NMOS) switch 423 serves as an analog switch, which lessens the
slew rate of the output voltage during the early ramp-up stage. The lower
slew rate provides additional stability because of the relatively slow
feedback loop provided through comparator 430.

[0035]When the driver output signal voltage reaches the reference voltage
signal (when both switches 422 and 421 are closed), the output high
voltage control signal turns off the current path of output driver 420 by
opening switch 422. The transmission line and/or capacitor 440 provide a
substantially large load capacitance that allows comparator 430 to
respond quickly enough to turn off the current path so that feedback path
is stabilized. As discussed above, the load capacitance normally includes
the capacitance of structures (parasitic or otherwise) in the
transmission path of the output voltage. Switch 422 and/or switch 421 can
be opened to conserve power for a power-down mode.

[0036]FIG. 5 is an illustration of a sample output driver having
capacitive stabilization and an input signal. Output driver 500 includes
a voltage reference circuit 510, output driver 520, comparator 530,
capacitor 540, and pre-driver 550. Voltage reference circuit 510 can be
programmable to select a desired voltage for the output high level of the
output signal. Capacitor 540 can be a capacitive load and/or energy
storage device. Output driver 520 includes switches 521, 522, and 523. In
an embodiment, switches 521 and 522 are PMOS transistors, and switch 523
is an NMOS transistor. Each transistor has a gate for the control
terminal and a source and drain as non-control terminals.

[0037]The output of voltage reference circuit 510 is coupled to an
inverting input of comparator 530. The non-inverting input of comparator
530 is coupled to the output of output driver 520 (at the second
non-control terminal of switch 522). The output of comparator 530 is
coupled to a control terminal of switch 522. An input signal is applied
to an input of pre-driver 550. A first output of pre-driver 550 is
coupled to a control terminal of switch 521 and a second output of
pre-driver 550 is coupled to a control terminal of switch 523.

[0038]Switch 521 has a first non-control terminal coupled to a power
supply and a second non-control terminal coupled to a first non-control
terminal of switch 522. Switch 522 has a second non-control terminal that
is coupled to a first non-control terminal of switch 523, which is the
output of output driver 520, and is further coupled to a first terminal
of the capacitor 540. A second terminal of capacitor 540 is coupled to
ground.

[0039]In operation, output driver 500 uses the reference voltage signal to
limit the output high voltage of output driver 520. The input signal is
inverted to two identical outputs by the pre-driver 550 and can be used
to drive the control terminals of switch 521 and switch 523. When switch
522 is closed (conducting), the driver output signal is driven in
response to the input signal. Switch 521 is used to couple the power
supply to the driver output signal in response to a high state of the
input signal.

[0040]The reference voltage signal is compared with the driver output
signal of output driver 520 so that an output high voltage control signal
is generated. When the driver output signal reaches the reference voltage
signal (when both switches 522 and 521 are closed and switch 523 is
open), the output high voltage control signal turns off the current path
of output driver 520 by opening switch 522. The transmission line and/or
capacitor 540 provide a substantially large load capacitance that allows
comparator 530 to respond quickly enough (with respect to the feedback
loop response time) to turn off the current path so that feedback path is
stabilized. As discussed above, the load capacitance normally includes
the capacitance of structures in the transmission path of the output
signal. Switch 522 and/or switch 521 can be opened to conserve power for
a power-down mode.

[0041]FIG. 6 is an illustration of a sample output driver having a
differential input signal and stabilization using an analog switch.
Output driver 600 includes a voltage reference circuit 610, output driver
620, comparator 630, and pre-driver 650. Voltage reference circuit 610
can be programmable to select a desired voltage for the output high level
of the output signal. Output driver 620 includes switches 621, 622, 623,
and 624. In an embodiment, switches 621 and 622 are PMOS transistors,
switch 623 is an NMOS transistor, and switch 624 is a native NMOS
transistor. Each transistor has a gate for the control terminal and a
source and drain as non-control terminals.

[0042]The output of voltage reference circuit 610 is coupled to an
inverting input of comparator 630 and the gate of switch 624. The
non-inverting input of comparator 630 is coupled to the output of output
driver 620. The output of comparator 630 is coupled to a control terminal
of switch 622 (in output driver 620). An input signal is applied to an
input of pre-driver 650. A first output of pre-driver 650 is coupled to a
control terminal of switch 621 and a second output of pre-driver 650 is
coupled to a control terminal of switch 623. The output signal of output
driver 620 is coupled to a non-inverting input of comparator 630.

[0043]Switch 621 has a first non-control terminal coupled to a power
supply and a second non-control terminal coupled to a first non-control
terminal of switch 622. Switch 622 has a second non-control terminal that
is coupled to a first non-control terminal of switch 624. Switch 624 has
a second non-control terminal (which is the output of output driver 620)
that is coupled to a first non-control terminal of switch 623.

[0044]In operation, output driver 600 uses the reference voltage signal to
limit the output high voltage. The input signal is inverted to two
identical outputs by the pre-driver 650 and can be used to drive the
gates of switch 621 and switch 623. When switch 622 is closed
(conducting), the driver output signal is driven in response to the input
signal. Switch 621 is used to couple the power supply to the driver
output signal in response to a high state of the input signal.

[0045]The reference voltage signal is compared with the driver output
signal of output driver 620 so that an output high voltage control signal
is generated. When the output voltage transitions from low to high,
(native NMOS) switch 624 serves as an analog switch, which lessens the
slew rate of the output voltage during the early ramp-up stage. The lower
slew rate provides additional stability because of the relatively slow
feedback loop provided through comparator 630.

[0046]When the driver output signal reaches the reference voltage signal
(when both switches 622 and 621 are closed and switch 623 is open), the
output high voltage control signal turns off the current path of output
driver 620 by opening switch 622. As discussed above, the load
capacitance of the transmission line affects the slew rate of the output
voltage and affects stability of the feedback loop produced by comparator
630. Switch 622 and/or switch 621 can be opened to conserve power for a
power-down mode.

[0047]The above description of illustrated embodiments of the invention,
including what is described in the Abstract, is not intended to be
exhaustive or to limit the invention to the precise forms disclosed.
While specific embodiments of, and examples for, the invention are
described herein for illustrative purposes, various modifications are
possible within the scope of the invention, as those skilled in the
relevant art will recognize.

[0048]These modifications can be made to the invention in light of the
above detailed description. The terms used in the following claims should
not be construed to limit the invention to the specific embodiments
disclosed in the specification. Rather, the scope of the invention is to
be determined entirely by the following claims, which are to be construed
in accordance with established doctrines of claim interpretation.