The use of charge storage on nanoscale particles has been realized in silicon integrated circuit memories [1,2] and utilized in commercial products[2]. An analysis has previously been made of the increasing portion of the threshold voltage being occupied by thermal noise levels and the bit error rates in digital logic and memory circuits [3-6]. This analysis has led to the prediction that there are fundamental limits imposed in digital circuits by thermal noise and that the scaling predicted by Moore’s law can not continue into the future. No consideration was, however, given to the errors that might be caused by l/f noise or random telegraph signals. In small transistors such as used in read sense amplifiers the l/f noise is caused by and can be characterized by random telegraph signals(RTS). These random signals can cause errors in the sense amplifiers and limit the ability to read the data stored in nanoscale memories. These noise signals can be equivalently represented in either the frequency domain or the time domain. The mean square noise of the read transistor is KF μ W (Vgs-Vt)(Vgs-Vt) /( 2 LLL f ) where, KF is the l/f noise parameter, L the length and W the width of the transistor channel, μ the mobility and (Vgs-Vt) the excess of gate voltage above threshold. The charge read error of a sense amplifer transistor can be expressed as ΔI Δt = sqrt(( KF W μ / 2 LLL ) ( ln (fh /fl) ) ) (Vgs-Vt) Δt where, fl and fh the low and high frequency bandwidth limits. Δt is the read interval time of the signal at the sense amplifier. The charge signal due to the memory element or transistor with 3nm nanoscale storage sites can be given as ΔIds Δt = (q μ (Vgs-Vt) / LL ) ΔNt Δt The minimum number of stored electrons, ΔNt, which can be sensed is then ΔNt = sqrt(( KF μ W L / 2 ) ( ln (fh/ fl) ) ) / (q μ ) which is limited or increases with the magnitude of the l/f noise and as the lower bandwidth decreases or time differences between read signals increases. This is the minimum number of electrons in a single memory element which can be detected. If one electron is stored, ΔNt = 1, then the time until there is an error can be calculated as the time to failure, tf = 1/fl. For a single memory element or cell is can be a very long time. Practical memories, however, have a very large number of individual elements or bits, N, typically a gigabit, and require very low bit error rates. If the failure rate is constant, 1/tf =fl, and there are N=lG bits then for a nanoscale memory the bit error rate will be around 10exp(-6) or there will be more than one bit error per year. This is higher than the desired rate of one per year. [4,6] [1] Muralidhar et al., “A 6 V embedded 90 nm silicon nanocrystal nonvolatile memory,” IEDM Digest, 2003, pp. 601-604. [2] B. Hradsky et al., “Nanocrystal physical attributes influencing non-volatile memory performance,” IEEE Device Research Conf., 2005, pp. 37-8. [3] L.B. Kish, Physics Letters, A 305, pp. 144-149, 2002. [4] L. Forbes, M. Mudrow and W. Wanalertlak, “Thermal noise and bit error rate limits in nanoscale memories,” IEE Electronics Letters, Vol. 42, No. 5, pp. 279-280,2 March 2006. [5] M. Mudrow, W. Wanalertlak and L. Forbes, "Thermal noise limits in nanoscale electronics," IEEE Workshop on Microelectronics and Electron Devices, Boise, 14 April 2006, pp. 39-40. [6] L. Forbes , M. Mudrow and W. Wanalertlak, "Thermal noise and bit error rate limits in nanoscale memories," NanoTech, Boston, 7-11 May 2006, Vol. 3, pp.78-81.