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Open Verification Library (OVL) Working Group

Charter

To define and deliver standard OVL LRM and libraries of assertion checkers to be used by design, integration and verification engineers to check for good/bad behavior in simulation, emulation and formal verification – provided in Verilog, System Verilog, VHDL, PSL, and SystemC.

This working group is currently inactive. For more information, please contact us.

Scope

The OVL library of assertion checkers is intended to be used by design, integration, and verification engineers to check for good/bad behavior in simulation, emulation, and formal verification.

The Open Verification Library (OVL) Working Group is responsible for the definition and development of the standard OVL language reference manual and assertion-checker libraries.

Background

OVL Version 2.8, released in December 2013, is the latest OVL release implemented in Verilog, VHDL, System Verilog and PSL (Verilog flavor).

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Resources

Errata and feedback: To report or see current errata of the standard OVL library, click here (Mantis reporter login required; select the standard OVL errata page). If you would like to report errata but are not a Mantis reporter, please send a message to the This email address is being protected from spambots. You need JavaScript enabled to view it..