Axel Scherer Bloghttp://community.cadence.com/search?q=*%3A*&category=blog&users=48486&sort=date%20descSearch results for '*:*' by user ID 48486en-USZimbra Community 8The Time is Ripe—SystemVerilog Adoption for Design Is Gaining Momentumhttp://feedproxy.google.com/~r/cadence/community/blogs/48486/~3/J04kwxlANFU/the-time-is-ripe-systemverilog-adoption-for-design-is-gaining-momentumThu, 30 Apr 2015 21:34:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1339098Axel Scherer/cadence_blogs_8/b/fv/archive/2015/04/30/the-time-is-ripe-systemverilog-adoption-for-design-is-gaining-momentum0On March 2, 2015, I had the privilege of moderating the Accelera tutorial at DVCon San Jose , which focused on the adoption challenges and the benefits of using SystemVerilog for design (SVD). The consensus was that, although it has been 10 years since the ratification of IEEE 1800 , we are finally seeing momentum in the adoption of language features that are extremely beneficial for modeling designs. In the verification arena, many features have been adopted quickly for two reasons: the productivity gap was very high and the adoption challenges were lower. However, in the design space, the adoption challenges are much higher. This is because a much larger set of tool types and vendor implementations must consistently support the same subset of the language in order to work productively. In the tutorial, we heard from Stu Sutherland of Sutherland HDL , who talked about the use of SystemVerilog assertions (SVA) in the design space. Junette Tan followed up by describing how PMC Sierra mounted a concerted effort, starting in 2010, to adopt SystemVerilog for design. She explained the challenges and the gains the company made by being an SVD pioneer. We captured a short video with Junette to summarize her talk. (Please visit the site to view this video) Then followed Mike Schaffstein, who illustrated the methodology he deployed to pilot SV for design at Qualcomm . He discussed the methodology and the SV constructs that work, and where the remaining challenges lie. Mike spoke in the video below about his experience. (Please visit the site to view this video) Finally there was a panel discussion that also allowed the audience to ask more questions. Overall, this session was very well attended, and as far as I know, it was the most heavily attended session at DVCon this year. As a benefit, the discussion and audience interaction was very lively. My thoughts on this tutorial are summarized in this video. (Please visit the site to view this video) The subsequent DVCon survey results showed that the vast majority of the attendees were inspired and excited by the tutorial, and many expressed their intent to start adoption of SystemVerilog for design in 2015. Axel Scherer, Chief Tech Adoption Guy Twitter: @axelschererhttp://community.cadence.com/cadence_blogs_8/b/fv/archive/2015/04/30/the-time-is-ripe-systemverilog-adoption-for-design-is-gaining-momentumMoore’s Law 2.0–How Small It Is To Be A 14nm FinFEThttp://feedproxy.google.com/~r/cadence/community/blogs/48486/~3/xa1QjID_FS8/moore-s-law-2-0-how-small-it-is-to-be-a-14nm-finfetThu, 16 Apr 2015 20:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1339089Axel Scherer/cadence_blogs_8/b/fv/archive/2015/04/16/moore-s-law-2-0-how-small-it-is-to-be-a-14nm-finfet0As I mentioned in my Blog on April 7, Moore’s law will turn 50 on April 19 . What I did not emphasize enough in my discussion on silicon process evolution is size , or more accurately tininess . In that post, I stated: “The fin width in a 14 nm process transistor is actually only 8nm ! This is equivalent to about 15 layers of silicon lattice.” But most people can not fathom what 8nm actually means. It is much smaller than you would assume. It truly is at the atomic scale, and the atomic scale is small beyond belief. Let’s put a common reference point into place for it: the width of a human hair . It is about 75 μm (micrometers) on average. So how many 8 nm fins would you need to put side by side to match a human hair? It is 9,375 fins! Another way of looking at this is speed. Human hair grows at about 1.25 cm per month. This means about 42 μm per day or 1.7μm per hour. So the question is how long would it take for a human hair to growth the width of a 14nm FinFET fin (8 nm). It would take only 0.017 seconds! How fast is this really? The blink of an eye takes about 0.35 seconds . Hence during the time it takes to blink, your hair would grow the length of about 20 times of the width of a 14nm FinFET fin. Now this is what I would call tiny! To hammer down the point let’s look at one more comparison. In 1971, the common structure size was 10 μm. This was also the year when the Intel microprocessor 4004 was released and transformed the entire industry. If we form a square of 10 μm x 10 μm, we get 100 μm2. We need to take into account that a single transistor in 10 μm technology is much larger than 100 μm2. The Intel 6T SRAM cell in 14nm FinFET is 0.0588 μm2. This means a 10 μm square could fit 1,700 bit cells or 10,204 transistors. Keep on scaling! Axel Scherer Related stories : -- Moore’s Law 2.0—The End and Beginning of a New Era!http://community.cadence.com/cadence_blogs_8/b/fv/archive/2015/04/16/moore-s-law-2-0-how-small-it-is-to-be-a-14nm-finfetMoore’s Law 2.0—The End and Beginning of a New Era!http://feedproxy.google.com/~r/cadence/community/blogs/48486/~3/D8UhuLuzZ4s/moore-s-law-2-0-the-end-and-beginning-of-a-new-eraTue, 07 Apr 2015 22:46:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1339078Axel Scherer/cadence_blogs_8/b/fv/archive/2015/04/07/moore-s-law-2-0-the-end-and-beginning-of-a-new-era0April 19 marks the 50 th anniversary of Moore’s law . This is not just a very significant anniversary for technology, but for all of mankind. Here is why. We have never before seen such explosive innovation on such a massive and sustained scale. Let me break it down. Gordon Moore formulated his vision about semiconductor complexity explosion in 1965. Originally, he predicted a doubling of the number of components on a chip every year. Later he revised it to occur every two years. What does this mean when we compare 1965 to 2015? It means 2 25 = 33,554,432 In other words, we have witnessed a 33 million-fold explosion in terms of transistors in an integrated circuit (IC). Today, the largest ICs count transistors in the billions! For example, Intel’s latest 15- core Xeon Ivy Bridge-EX has over 4 billion transistors. In no other field of human undertaking have we seen such a long stretch of exponential growth. It is absolutely astounding. Furthermore, in no other field can you predict that the complexity and its associated application potential will double every two years! However, we are standing at an inflection point. Moore’s law, let me call it Moore’s law 1.0, will most likely reach its end within a decade. The main premise of Moore’s law is driven by how many components can be packed on a chip. In Moore’s law 1.0 we dealt primarily with a two-dimensional area – the width and length of silicon structure to be manufactured. The latest process size is 14nm. The next-generation process size will be 10nm and 11nm, respectively. Why are even smaller structure sizes a problem, and why can we not go significantly into the sub-10nm space? It comes down to the size of the silicon atom and the associated silicon lattice. The lattice parameter alpha for silicon is only about 543 picometers. This means we are dealing with only about 18 layers of Si for a thickness of a 10nm wide lattice. However, with modern transistors things are even smaller as we are now using FinFET technology. The fin width in a 14nm process transistor is actually only 8nm ! This is equivalent to about 15 layers of silicon lattice. At the sub-10nm level, electromigration , and process variations in manufacturing , amongst other effects, will be so large that the end of conventional silicon chip manufacturing at high yields and chip longevity might be reached. However, we have a way out of this predicament. The solution is to build up. If we cannot make it 2D anymore, let’s make it 3D. Think about Manhattan , in New York City . When 2D space gets tight you build up into 3D space. The same thing is occurring in semiconductor manufacturing. Indeed Samsung recently announced a new type of Flash memory: V NAND Flash memory that stacks 32 component layers (up from 24) on top of each other, creating much more capacity per chip than has ever been seen before. The geometric regularity of memory elements lend themselves perfectly to this kind of application. But we need more than densely stacked memories. We need CPU cores, GPU cores, controllers, bridges, and so on. From a manufacturing perspective, Moore’s law will go into the Z-dimension to achieve its gains. However, from a computing perspective, the new paradigm will be massive parallelism . The only way to increase compute power is to leverage parallelism because we cannot increase clock frequency much further. The end of conventional silicon manufacturing will force us to go this direction. Subsequently, software development will need to adapt to take advantage of ultra-multi core computing. Ultra-multi core means initially hundreds, but soon thousands of cores and more. Conventional multi-threading won’t be enough and parallelism will no longer be for special applications or subsets of application. It will be the heart of compute speed, and any application with a need for high-speed computing will need to adapt to it. Intel and ARM-based chips have been multi-core for years. In fact, you can hardly buy a high-volume, single-core CPU any more. But those multi-cores all live in two dimensions. In the 3D world we will see a core explosion. Today you can buy an off-the-shelf 15-core, high-end Intel Xeon chip. Imagine if it was fabricated in 32 layers and you now suddenly have 480 cores on the chip! This is a different beast altogether and will change hardware and software development dramatically. Moore’s law 2.0 will be about component layers and the associated number of cores! Axel Scherer Chief Parallelism Guyhttp://community.cadence.com/cadence_blogs_8/b/fv/archive/2015/04/07/moore-s-law-2-0-the-end-and-beginning-of-a-new-eraIn New York–Boston/Brighton–Mountain View: Modern Formal and Simulation Educationhttp://feedproxy.google.com/~r/cadence/community/blogs/48486/~3/WGoAwfWinqw/in-new-york-boston-brighton-mountain-view-modern-formal-and-simulation-educationMon, 23 Mar 2015 19:13:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1339057Axel Scherer/cadence_blogs_8/b/fv/archive/2015/03/23/in-new-york-boston-brighton-mountain-view-modern-formal-and-simulation-education0Growing up in the &#39;80s can damage your memory – particularly when it comes to bad music. At DVCon 2015 in San Jose I spoke with Michael Theobald, PhD, who is an adjunct professor at Columbia University, and he told me about the Columbia campus in New York City, which I have never visited. Immediately, the awful song: New York - Rio -Tokyo came to mind and now it is stuck in my head (Google it at your own risk – you have been warned.) Consequently, I decided to transform this song title into the title of this blog post. When Michael teaches his students about formal analysis, he puts his verification approach in context, and in particular, when he talks about formal analysis for hardware verification. He told me that he recommends that his students to check out the Functional Verification course CS348 at Udacity , which was developed by Cadence. As of now, over 17,000 students have enrolled in this specialized course. (Please visit the site to view this video) So what does all of this have to do with the cities listed in the title: New York – Boston/Brighton Mountain View ? It’s easy: New York is the location of Columbia University Boston is where yours truly lives; actually in a suburb of Boston Brighton , UK is where my colleague and co-instructor Hannes Fr&#246;hlich lives Mountain View is where Udacity is located Michael, Hannes, and I share a passion for great education. Hannes and I are happy to see that Michael can leverage our work to expand the skills and knowledge of his students. Also, I am happy to educate you not only on the concepts and technical aspects of verification, but also on “important” aspects of our modern culture. For example, the chorus of the original New York-Rio-Tokyo lyrics are: In New York - Rio - Tokyo Or any other place you see, You feel that dancing fantasy. The 2015 version of the song should go like this: In New York – Boston/Brighton – Mountain View Or any other place you see You feel that verification methodology. Keep on learning! Axel Schererhttp://community.cadence.com/cadence_blogs_8/b/fv/archive/2015/03/23/in-new-york-boston-brighton-mountain-view-modern-formal-and-simulation-educationWhat Does It Take To Satisfy Your Need For Verification Speed? You Gotta RAK It!http://feedproxy.google.com/~r/cadence/community/blogs/48486/~3/PhuizCxXcEI/what-does-it-take-to-satisfy-your-need-for-verification-speed-you-gotta-rak-itFri, 13 Mar 2015 18:55:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1339047Axel Scherer/cadence_blogs_8/b/fv/archive/2015/03/13/what-does-it-take-to-satisfy-your-need-for-verification-speed-you-gotta-rak-it0A few weeks ago I discussed how bigger is (often) better . Obviously, everyone has a need for “ more cowbell ” as well as a need for speed. The questions to ask are: What do you have to do to accelerate your simulation runs? What are the basic factors to consider? How do you have to think about your testbench/verification environment and your DUT? What aspects really matter and what improvements can you expect? All of these questions are answered in an introductory Rapid Adoption Kit (RAK) to Verification Acceleration . This RAK provides you with the following collateral: An application note that explains the various relevant factors. A presentation that shows the basic concepts of verification acceleration. A video that is a narrated recording of the slides in the presentation. An example that shows three basic cases and starting points, respectively. A second video that walks you through the example. The simulation example also has performance profiling enabled so you can see the speed up that you can expect when moving to acceleration with the Palladium XP platform . Accelerate this! Axel Scherer, Chief Velocity Guyhttp://community.cadence.com/cadence_blogs_8/b/fv/archive/2015/03/13/what-does-it-take-to-satisfy-your-need-for-verification-speed-you-gotta-rak-itThere Will Be Blood – Ahem, Rather, Electrons If Apple Decides to Build a Carhttp://feedproxy.google.com/~r/cadence/community/blogs/48486/~3/34Emfjleas4/there-will-be-blood-ahem-rather-electrons-if-apple-decides-to-build-a-carWed, 25 Feb 2015 17:38:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1339024Axel Scherer/cadence_blogs_8/b/fv/archive/2015/02/25/there-will-be-blood-ahem-rather-electrons-if-apple-decides-to-build-a-car0Every modern device, even the ones with modest complexity, could never be developed by a single person at the quality, cost, and performance levels we enjoy today. This has been true for over 100 years – since the Industrial revolution. Modern product development is highly dependent on knowledge, research, and engineering skills developed in the past. Furthermore, not a single company is able to go it alone anymore. The complexities and the layers in modern devices are truly mind-boggling and involve disciplines like physics, chemistry, engineering, design, and even management. For a modern company to be successful, the key question is what to develop in-house, what to buy, or when to look for a partner. These decisions are highly complex and are a fundamental part of making a company successful. Further on, these decisions have to be reexamined all the time as markets are continuously evolving. Companies that successfully master these decisions can survive in the long run. Others will vanish. Companies have to determine where their sweet spot is for adding value, and cannot rest forever on that spot because the future will catch up with them very quickly. A prime example of a company with many interdependencies is Dell . At the beginning of the PC revolution, we had Intel and others developing and selling the core hardware components like CPUs and supporting chips. We had Microsoft creating the dominant operating system: MS-DOS and later Windows, and Office, the most popular and successful application software package. Neither Intel nor Microsoft sold PCs. They focused on their respective core competencies, and still do this today. Dell saw an opening in building PCs from the core technologies delivered by Intel, Microsoft, and others, and thus became a master of supply chain management and distribution. At their peak Dell had an astounding market share and was very clever and profitable for years. But then the PC market changed, and profit margins shrank significantly. Profitable growth in the PC market became harder to attain. Eventually, Dell struggled more and more just to get compensated for the value they delivered and the core competency they held. Today, Dell is a shadow of its former self because they were unable to reinvent themselves in ways the market demanded. Reinvention is not optional. It is a requirement to stay competitive and profitable. A counter example to the Dell story is IBM . They are proactively trying to adapt to ever-changing business conditions. Unlike Dell, IBM foresaw the declining trend in the PC industry and divested of it a long time ago by selling their PC division to Lenovo . IBM continued to do this. Right now they are in the process of divesting significant sections of their microelectronic business by selling it to GLOBALFOUNDRIES , formerly the semiconductor division of AMD . Being proactive about managing change is just a necessary business condition. However, it is not sufficient to guarantee success. How to enable change successfully and, thus, how to win, is where the true magic in business can be found. After the return in 1997 of Steve Jobs to Apple , we saw an unprecedented success story in change management. Even before Apple’s multiple transformations, we have seen other reformers like Lee Iacocca at Chrysler changing the mode of operation of a complete company. But at Chrysler, and many others, the change that occurred was not sustained and did not become a cornerstone of the company culture. Apple is the archetype in adapting to new markets. They are extremely proactive in pushing for change, and would rather cannibalize their own product lines to prevent the competition getting ahead of them. This can been seen in the evolution of the various iPod lines, which was the first significant foray out of the core business of personal computing. It was followed up by the iPhone, which is still extremely successful and profitable beyond any expectations. In all of these transitions and changes, Apple was very deliberate about what it did and which products it brought to market. The original Macintosh , introduced in 1984, was running on a Motorola processor. At the time that might have been a good choice. However, over time Motorola could not compete with Intel, and Apple was nervously sweating it out. In response to Intel’s dominance, Apple created a partnership with IBM and Motorola, called AIM , whose charter was to derive technology from IBM’s workstation processors in order to create a new generation of RISC CPUs to power the Macintosh line, which was called the PowerPC . One amazing aspect of this transition was that Apple kept the code base and existing software fully functional, without losing the support of third-party software companies. For a few years this actually worked. But after some time Apple again found itself in the same dilemma - AIM could not compete with Intel in the CPU business. Consequently, Apple did the unthinkable and switched the processor architecture for the second time, now from PowerPC to the x86 platform. And, the craziest part about this is that they survived both complex transitions, including the sustained support from key software application vendors such as Microsoft! In more recent history, Apple has made other bold decisions and come out on top. The original iPhone was powered by an SoC (the most important component of the hardware) developed by Samsung . However, Apple quickly realized that the SoC is a key part of the product puzzle that it needs to keep control of in order to stay competitive. They did not want to be dependent on Motorola, IBM, Intel, Samsung, or anyone else for a key component of their flagship product again. This made perfect economic sense, since the high volume of iPhone sales is in a totally different cost and profit ballpark than Mac sales. Thus, Apple went ahead and acquired a few small CPU houses that develop chips using ARM CPU cores. They integrated those companies very quickly and are now themselves transformed into a formidable SoC development house. In fact, Apple pioneered 64-bit SoCs in the mobile market, and they managed to make their SoC in the iPhone 6 the fastest mobile SoC in the market. When I hear business analysts or car industry experts say that Apple will not be able to develop an automobile, it shows me that they really do not understand this company and its potential. The core of their misunderstanding is that they believe that cars are made primarily from metal and, therefore, the core competency in car development ought to be mechanical engineering and heavy industrial manufacturing. But, remember, what you don’t develop in-house you can buy, or you can team up with a partner. This assumption might have been true years ago. But cars today are no longer predominantly mechanical devices. They are dominated by electronics. Most car manufacturers are still very slow to understand this and to change their approach to business. And, if they do not adapt quickly, their competitiveness will change in fundamental ways because if it is not Apple, it will be another company that will bring their electronics, and system and software integration expertise, to play to give established car manufacturers a real run for their money. This is the main point of the car product puzzle – There will be electrons! After this transition, some car companies will be shadows of themselves, and might not survive the transformation. Others will wake up to this new competition and transform themselves in order to stay in business. Market forces will bring about this change on a significant scale. Apple made the decision to develop their own mobile SoCs. They also write their own operating system and application software. They only buy parts that are not key to differentiation. If Apple decides to step into the automotive space they will bring their core competencies into play. They transformed OS X from a PC operating system (OS) to a mobile OS, and this was not just an adaption. They will create, or derive, an OS for the car and they will develop and integrate the key car SoCs and software technology themselves. No matter what Apple decides to do and how to do it, the car industry had better watch out. Electronics and software are the key for future innovation in most spaces, and in particular in the car industry. Axel Scherer Twitter: @axelschererhttp://community.cadence.com/cadence_blogs_8/b/fv/archive/2015/02/25/there-will-be-blood-ahem-rather-electrons-if-apple-decides-to-build-a-carBlast from the Past, Take 2: Why Are We Still Designing with Verilog 2000 – A DVCon Previewhttp://feedproxy.google.com/~r/cadence/community/blogs/48486/~3/TzZufsTrnNc/blast-from-the-past-take-2-why-are-we-still-designing-with-verilog-2000-a-dv-con-previewMon, 23 Feb 2015 17:50:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1339022Axel Scherer/cadence_blogs_8/b/fv/archive/2015/02/23/blast-from-the-past-take-2-why-are-we-still-designing-with-verilog-2000-a-dv-con-preview0SystemVerilog was ratified and released by the IEEE 10 years ago, in 2005. Since then, it has been rapidly adopted for verification. The reasons are simple – it is much more powerful than classic Verilog, and the language only has to be handled by a few classes of EDA tools, such as the Incisive Enterprise Simulator , for example. However, in the electronic design space we see a much slower rate of adoption than in verification, and for good reasons. When you model your device under test (DUT) using SystemVerilog design constructs, such as interfaces and enumerated types, to name a few, you need to make sure your entire tool chain supports them, which can include: linting, simulation, equivalence checking, property checking, synthesis, emulation, acceleration, and potentially other applications. In other words, when you model using SystemVerilog, the bar is much higher, and so is the risk for adoption. However, there are a few brave designers out there who have found ways to achieve the advantages of the new language features, while managing the risks. Those engineers are leading the way for broader-scale adoption within the industry. They have seen, and displayed, the possibilities of SystemVerilog, and they will share their experiences on Monday, March 2 at 9:00am PST in San Jose, CA at the DV Con 2015 Accellera tutorial , in a presentation titled: SystemVerilog Design: User Experience Defines Multi-Tool, Multi-Vendor Language Working Set . At the presentation, you will hear from Junette Tan of PMC-Sierra , as well as from Mike Schaffstein of Qualcomm . In addition, you will get insight from industry veteran Stu Sutherland about how to use SystemVerilog assertions as part of the design methodology. This is going to be very interesting and exciting. It is the real deal. The experiences related by these experts stem from the implementation of actual projects that went on to produce working silicon. Yours truly will be the MC, and I cannot wait to see you at the presentation in sunny California. Axel Scherer Twitter: @axelschererhttp://community.cadence.com/cadence_blogs_8/b/fv/archive/2015/02/23/blast-from-the-past-take-2-why-are-we-still-designing-with-verilog-2000-a-dv-con-previewThe Apple Car: Not a Question of Ability, But a Question of Intenthttp://feedproxy.google.com/~r/cadence/community/blogs/48486/~3/SKrggtmS8wM/the-apple-car-is-not-a-question-of-ability-it-is-a-question-of-intentTue, 17 Feb 2015 23:07:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1339013Axel Scherer/cadence_blogs_8/b/fv/archive/2015/02/17/the-apple-car-is-not-a-question-of-ability-it-is-a-question-of-intent0Rumors have been flying for years about whether Apple will create a car. Recently, this has gained more traction due to some key hires by Apple, and by boastful comments by an Apple employee , which is rather rare and unusual. It is easy to dismiss the idea of an actual Apple car because the context is multi-faceted. My opinion is that if Apple wants to build a car, they certainly can. It will not be a question of ability at all. The reason is that the car business has changed dramatically in recent decades to lower the barriers to entry. Car development has long ceased to be dominated by metal and mechanical aspects. It became an electronics and software problem years ago. A car has become an electronic device on wheels . Don’t believe me? Here is what Berthold Hellenthal of Audi’s electronic development department stated in May 2014 at the CDNLive users conference in Munich, Germany: 90% of innovation in vehicles today is based on electronics Every vehicle delivered to our customers contains about 6000 to 8000 semiconductors (Please visit the site to view this video) The amount of electronics and software in cars is increasing steadily. Now ask which company has mastered hardware and software development and integration? It is Apple. Moreover, they have the competence to take over the key portion of a tier 1 component supplier themselves in order to control their destiny more tightly, just as they have done with SoC development for the iPhone and the iPad. They use this as a key differentiator. The second important aspect of the Apple car question is the transformation from internal combustion engines, to hybrids and eventually to all-electric cars. Internal combustion engines have been refined and have become much more reliable in the last few decades. However, they are highly complex, contain lots of components, and are one of the most challenging areas of the automobile. You need fuel injection, a gas tank and pump, cooling, oil, exhaust system, catalytic converter, and on and on. It is an amazing sub-system of the car. Electric engines, however, are much less complicated. Consequently, this makes entry into the electric automobile manufacturing market much simpler. Additionally, we have witnessed what Tesla Motors has accomplished since 2003. A Silicon Valley company where the CEO is a software guy who has done the un-doable – create a new electric car company from scratch with an attractive product. Tesla Motors has shown that this is not a pipe dream, and that the complexities of automobile development are not insurmountable. Apple has also mastered supply chain management like few other companies in the electronics space have. The last factor is product distribution. When Apple started to open its own retail stores for direct sales and distribution, and in of all places expensive mall spaces, everyone thought they had lost their corporate minds. The prevailing trend was just the opposite – everything moves online. And the few computer dealers with stores like CompUSA, Gateway, and others vanished quickly. But Apple’s approach has not only been successful, they are now the most profitable retailer per square foot of sales floor space in the world, and by a wide margin. Direct sales also increases profitability and provides the ability to better control the sales process. You are not relying on the often not very informed sales staff of a traditional car dealer. You can directly and intimately show the customer where your product really shines. I have often been disappointed with how under-informed car sales personnel can be. In almost every car dealership showroom, even at high-end car dealers, the staff has no idea, or interest, in what they are actually selling. They lack both product passion and knowledge. Often, I had to inform the sales staff about the features of the cars they were selling. So here is my conclusion: Apple has engineering power, they have more cash than necessary, we have the current trend towards electric cars, and they have supply chain mastery and direct distribution processes. The stars are surely aligned. The question is now, does Apple want it? Is this a market they want to take on? Is this market ready for a disruption that can be sufficiently profitable for their standard business model. By the time Apple could launch a car, we will be just before the cusp of the transition to autonomous vehicles. This means we will be in a period where the markets are changing radically. Autonomous vehicles will be a disruption by themselves. Hence, it could be a compelling point to enter the market. The margins in the car industry are much lower than the ones Apple is used to. However, the same thing is true in computing and mobile. Apple has been able to create margins that others only dream of. History tells us that Apple can defy common wisdom. Still, taking on car development and distribution still would be a huge leap, even for Apple. Fan boys would love it and so would I. Not just to have the ability to drive an Apple car, but even more importantly to see how this changes the automobile market overall, how it makes it more competitive, and therefore improves products. The continued increasing complexity of automobile development in the electronics area, with the ever-increasing demands on software and systems, is a significant challenge for both auto manufacturers, as well as their suppliers. The EDA industry in general, and Cadence in particular, play a key role in enabling the next generation of automotive innovations. I can’t wait to see the car of the future, be it by Apple, Google , or the established car manufacturers. Keep driving and dreaming Axel Scherer Twitter: @axelschererhttp://community.cadence.com/cadence_blogs_8/b/fv/archive/2015/02/17/the-apple-car-is-not-a-question-of-ability-it-is-a-question-of-intentBlast From the Past—Or Debugging HDL Race Conditions And Glitcheshttp://feedproxy.google.com/~r/cadence/community/blogs/48486/~3/CKFINzk6f6E/debugging-verilog-race-conditions-and-glitchesThu, 05 Feb 2015 20:14:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1339001Axel Scherer/cadence_blogs_8/b/fv/archive/2015/02/05/debugging-verilog-race-conditions-and-glitches0In 1999, the movie Blast from the Past was released. It begins in Los Angeles in the 1960s, during the Cold War era. In this movie, a nerdy, engineering-type father was afraid of a potential conflict involving nuclear arms. He built a personal, massive fall out shelter/apartment underneath his home. No less than the great Christopher Walken of cowbell fame played the father! To make a long story short, an airplane crashed in the neighborhood and the father thought this meant that a nuclear bomb had been dropped. He took his pregnant wife with him downstairs and activated a timer that locked the shelter door for 30 years. During that time, his wife gave birth to a son, played by Brendan Fraser of The Mummy fame, who was deliberately named Adam. After 30 years Adam leaves the shelter and explores Los Angeles, which by then is in the 1990s, and it is both very scary and very exciting for him. After a while, he meets a girl, called Eve, of course, and played by Alicia Silverstone of Clueless fame. When Adam and Eve meet, Eve experiences a massive blast from the past because Adam exposes her to the culture and worldview of the 1960s. In today&#39;s engineering world, we face many blasts from the past as well. For example the original hardware description languages (HDLs) were developed in the 1980s. They allow for multiple events to occur in a single time slice. The consequence of this freedom was that EDA vendors, in particular simulation vendors, could make a judgment call in implementing features of the language where specific behavior was simply not stringently defined. Expect the unexpected This can lead to situations where identical HDL code leads to different results between different simulators. The use of proper coding style and using proper constructs can avoid the bulk, if not the entire problem. But we all know that this is more of an idealistic view of the world, rather than a practical view, when it comes to computer languages. One of the biggest complications is the occurrence of race conditions and zero time glitches. In practice, you might logically expect a certain value for a signal, but you might get something totally unexpected. Even when you analyze the signal’s value transition in a waveform display tool, you might find yourself in a totally alien world. However, if you are a Cadence customer, you are in luck, because we have tools for interpreting that world. When you probe a signal during a simulation, by default you only get an abstracted view of the world—you see the outcome of the logic evaluation of the simulator. This is done because it makes the waveform database much smaller, and accesses to it much faster, but it records viewer details. This is OK in most cases because hopefully, you have very few race conditions. However, with the Incisive simulator we can probe with higher level of granularity and also record the low-level events that occur before the final value of a signal is determined. In this case we use the event switch when creating the waveform database. Once you record your signal transitions in this way, you get the lowest level details, which you can then use to determine where the races or glitches originate. Figure 1 shows that multiple events occurred between the values of fifty and idle using the yellow one-shot symbol. Figure 1 Clearer picture You can then expand the so-called sequence time and you may see that a signal in between a clock rise or fall event will not just go from 0 to 1, or vice-versa, or even stay the same value! Figure 2 shows the events of the transition. In it you can see exactly what happens in between the signal value change. Figure 2 More importantly, you can see how the driving signals that affect the signal of interest move through different values before they settle. Be aware, that although this looks like a delay in the waveform display, it actually is not. Here, we are referring to RTL-level simulation, and what you see are the transitions during signal evaluation that are determined by the simulator. Debugging race conditions and glitches can be rather tricky. However, with the help of the event recording granularity built into the Incisive simulator, you can actually see what is going on and determine the root cause. Most often you will then recode your logic to eliminate the race so that your simulation will actually do what you expect. And remember the simulation does not violate the LRM. For more information see the product manual Viewing Events in Sequence Time and the associated video that walks your through the process. Keep your code clean and get rid of those race conditions and glitches! Axel Scherer Twitter: @axelscherer .http://community.cadence.com/cadence_blogs_8/b/fv/archive/2015/02/05/debugging-verilog-race-conditions-and-glitchesBefore There Was a Transaction, There Were Signalshttp://feedproxy.google.com/~r/cadence/community/blogs/48486/~3/TqWzCRmuQA0/before-there-was-a-transaction-there-were-signalsFri, 30 Jan 2015 21:25:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1338992Axel Scherer/cadence_blogs_8/b/fv/archive/2015/01/30/before-there-was-a-transaction-there-were-signals0Transaction-based verification has been around for many years. A transaction is an abstraction that consists of a single transfer of data and control signals. With today’s complex SoCs, we need to abstract in order to build complex verification environment and test scenarios. Indeed, we want to build hierarchies of transactions: From simple packets, to complex higher-level layers of traffic. In UVM, the lowest level transaction is defined as a sequence item . Sequence items are combined into a sequence, and sequences can be combined to create more complex sequences. So far, so good. (Please visit the site to view this video) The problem is that this hierarchical build-up can get fairly complex quickly. As these sequences and sequence items are typically randomized, you can end up with very funky traffic patterns. When you assess or debug your traffic and the associated constraints, it might be very hard to make sense of what actually happened. However, with Cadence verification tools, we have had the ability to record these transactions in the waveform database and view them in the waveform browser since the 1990s. The concept of transaction recording and viewing is virtually crying-out to be applied to UVM because UVM operates primarily at the transaction level. You can see how this works in the video embedded above. Stay abstract, stay sequential! Axel Scherer Twitter: @axelschererhttp://community.cadence.com/cadence_blogs_8/b/fv/archive/2015/01/30/before-there-was-a-transaction-there-were-signalsPablo Picasso and the Power of Abstraction: Make Sense of Your Verification Traffic Using the UVM Sequence Viewerhttp://feedproxy.google.com/~r/cadence/community/blogs/48486/~3/p2C5sjBAx5M/pablo-picasso-and-the-power-of-abstraction-make-sense-of-you-verification-traffic-using-the-uvm-sequence-viewerThu, 29 Jan 2015 23:04:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1338991Axel Scherer/cadence_blogs_8/b/fv/archive/2015/01/29/pablo-picasso-and-the-power-of-abstraction-make-sense-of-you-verification-traffic-using-the-uvm-sequence-viewer0Abstraction is a key concept that makes it easier for humans to deal with large and complex systems. Since abstraction reduces complexity, without abstraction, hardly any innovation would be possible because the human brain cannot process large sets of low-level items and make sense of them. Abstraction not only plays a significant role in engineering and science, but also in art. Artists started to abstract to show the essence of their subject. For example, Pablo Picasso used abstraction when he drew the essence of a bull , and many other artists followed with similar drawings. In a similar way, today’s engineers make use of abstraction to simplify the essence of their complex designs. (Please visit the site to view this video) The Universal Verification Methodology (UVM) has clearly become the predominant verification methodology and library. UVM provides a set of classes and an approach that is designed to make verification more productive, streamlined, and consistent. In order to make the use and the adoption of UVM easier, Cadence has added several GUI features that can help you in your interaction and debugging of your verification environment, and its associated tests. One of the gems of our extensions to UVM is the UVM Sequence Viewer . The Sequence Viewer provides you with the ability to abstract an essential and complex part of an advanced environment and test suite: the verification traffic (in the form of UVM sequences). In use, the UVM Sequence Viewer shows you all the sequences and sequence items that are in the simulation. You can see sequence hierarchies on a per-sequencer basis, including fields, and their values. You can also view them on a type-basis. The reduction in complexity enabled by the Sequence Viewer allows you to quickly get to the essence of the traffic of the test. And, it implicitly allows you to quickly assess if this traffic meets your expectation. Let’s abstract to get productive! Axel Scherer Twitter: @axelschererhttp://community.cadence.com/cadence_blogs_8/b/fv/archive/2015/01/29/pablo-picasso-and-the-power-of-abstraction-make-sense-of-you-verification-traffic-using-the-uvm-sequence-viewerSmall is Beautiful—How UVM Test Case Extraction Can Improve Your Constraint Analysis Productivityhttp://feedproxy.google.com/~r/cadence/community/blogs/48486/~3/m5i4w202yyA/small-is-beautiful-how-testcase-extraction-can-improve-your-constraint-analysis-productivityThu, 29 Jan 2015 00:47:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1338989Axel Scherer/cadence_blogs_8/b/fv/archive/2015/01/28/small-is-beautiful-how-testcase-extraction-can-improve-your-constraint-analysis-productivity0In the world formerly known as microelectronics, which is now actually nanoelectronics, small is sure beautiful. With the continued reduction in transistor size, we can afford to pack an insane amount of functionality into chips such as SoCs, while die sizes still remain tiny. The amount of functionality on a modern SoC is truly mind-boggling. Even when you deal with a subsystem, you drown in complexity and excess information. This can be particularly problematic in verification. Assume you are trying to stimulate your subsystem or complex block. You are very likely to use constrained random simulation with UVM. The problem is that the DUT complexity will make your constraints complex as well. This means that you need to produce a complex set of traffic into and out of the DUT. In some cases, you might not be able to solve all the required constraints in your head. This will make it hard to predict the expected outcome, and what you should do about it. This problem becomes compounded when you run a serious and long simulation. (Please visit the site to view this video) For example, after spending a few minutes before a randomization call, results might occur that do not meet your expectations. So you look at the results, tweak the constraints, and try again. This iterative effort can be very time consuming and annoying. Ideally, you want to focus only on a small subset of the UVM environment. You want to analyze and iterate with the set of constraints associated just with a particular randomization call, not with the whole environment. In the Incisive 13.2 release, we have released a test case extraction feature that will help you solve this dilemma, and allow you to increase your constraint analysis productivity. This feature extracts just the relevant constraint set in a highly reduced test case, and it runs very fast. Using the extracted test case, you can quickly run a large number of random seeds and analyze the randomization distribution that is achieved. You can debug constraint conflicts much faster this way, and get on with the verification. A quick demo is shown in the video embedded above. Once you have finished debugging the failure, and have obtained the expected result with the highly reduced test case, you can integrate your constraint changes back into the larger environment and get on with your main task of completing the verification of the DUT. This is a true hidden gem and can make your day. Keep on randomizing! Axel Scherer Incisive Product Expert Team Twitter , @axelschererhttp://community.cadence.com/cadence_blogs_8/b/fv/archive/2015/01/28/small-is-beautiful-how-testcase-extraction-can-improve-your-constraint-analysis-productivityPretty Fly For an Old Feature—Discovering Existing But Unknown Incisive Verification Featureshttp://feedproxy.google.com/~r/cadence/community/blogs/48486/~3/Hi3lt8Bwbm0/pretty-fly-for-an-old-feature_2d00_discovering-existing-but-unknown-incisive-verification-featuresThu, 22 Jan 2015 02:17:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1338877Axel Scherer/cadence_blogs_8/b/fv/archive/2015/01/21/pretty-fly-for-an-old-feature_2d00_discovering-existing-but-unknown-incisive-verification-features0It is the year 2014. We live in a highly mobile, wireless world, supported by cloud and associated network infrastructure. Therefore, the use of physical media, such as CDs, DVDs, BlueRay discs, and so on are fading quickly. Personally, because of the early adopter in me, I despise the use of physical media in this day and age. The few interactions I still have with it are limited to the use of CDs in my car, as the aux input connection is electrically noisy, and the Bluetooth interface does not support my smartphone for some reason. Mind you, my car is a model that is at the end of its lifecycle. This means the engineering for it was developed many years earlier. The average automobile development cycle is about seven years, and mine was originally released in 2003. Hence, in the worst-case scenario, the audio system was selected and developed around 1996. Most likely it was updated in model years thereafter. However, it would make sense that for my model, besides the FM/AM radio, the main audio source is Audio/MP3 CD. A few weeks ago, the following song popped into my head: &quot;Pretty Fly (for a White Guy)&quot; by The Offspring , which is some sort of Punk-Rock-Pop song that was popular in 1998. It is a pretty funny song. I bought it and my kids started to love it. This meant that they demanded I play it in the car for them. (Please visit the site to view this video) So, I had to burn a CD. I have not done that in years and was surprised that I even still had writable CDs in the house. I burned the CD with one other song just a few minutes before I drove my kids to a soccer game. In the rush, I did not add more songs to the playlist to complement &quot;Pretty Fly&quot;, so we had to listen to the two songs over and over again. Eventually, I got sick of it. Hence, I used the genius feature in Apple&#39;s iTunes to create a more interesting and longer playlist. Then I burned a new CD with about 15 songs. Fifteen songs are good , but even that will also get stale sooner or later. Why don&#39;t I go ahead and burn even more songs on a disk, you may ask? Hey, I could make an MP3 CD, which has far greater storage capacity that the old audio CD format. And if I recall correctly, my car&#39;s disk player does support the MP3 audio format , which is pretty exciting to me! So, I burned a disk with about 150 songs. I could not wait to put the MP3 disk into the car&#39;s disk drive and check if it worked. Unfortunately it did not! Hence I could not fight the staleness factor yet. Even worse, I could not expose my kids to more gems of &#39;90s or dare I say &#39;80s and &#39;70s music ;) But then I ran into a store and they had a nice 3.5mm to 3.5mm standard mini jack cable. In a moment of clarity I thought, maybe the aux noise is from the cable I have. And indeed that was the case. Obviously I should have debugged this years ago. The point I am making is this: We all use tools and devices that have features that we kind of know about, but are not fully aware of, or have never used. The same is true, of course, for verification in general, and Incisive in particular. When we talk to Incisive users, we often see the following interaction taking place: Application Engineer : &quot;Did you try feature X yet?&quot; Customer : &quot;Never heard of it.&quot; (Or they have heard of it, but never used it)! Application Engineer : &quot;Feature X provides the following functionality and could be used in the following way.&quot; Customer (tries feature X ): &quot;This is great stuff. I cannot believe I missed out on this for so long.&quot; In order to give you a whole set of features that you might not have used yet, I have collaborated with other members of the Incisive Application Engineering, Product Expert, and R&amp;D team to compile a list of 10 features likely to be unknown by many Incisive users. Waveform database probing with -event : Debug race conditions related to event ordering. Design file search : Find files associated with your debug session quickly. i prof (Incisive Performance Profiling) : The ability to perform Advanced Profiling for SystemVerilog, UVM, RTL, GLS. nchelp/ncbrowse: Two utilities to help you get more details about Error or Warning messages, combined with a browser to make message analysis easier. IEEE 1801 (aka UPF) Power Supply Network Browser : The easy way to debug your UPF power supply network. Quick diff in the waveform viewer : A fast way to detect unexpected signal differences. UVM Sequence Viewer : Making sense of UVM sequences and their hierarchy. Cloning of SystemVerilog randomization calls : Ability to extract the relevant code related to a randomization call. Test Case Optimizer : Trimming down a testcase to a small fraction of it size to recreate an issue: Error, Warning etc. Automated Transaction recording and viewing for UVM : Quickly turn UVM sequence activity in visual transactions. We will release specific posts for all of these features in the upcoming weeks. By the way, I disagree with the line in the song &quot;the world loves wanabees.&quot; It might have been meant in an ironic way, but the world loves the real deal . Keep on discovering unknown features! Axel Scherer, Chief Fly Guyhttp://community.cadence.com/cadence_blogs_8/b/fv/archive/2015/01/21/pretty-fly-for-an-old-feature_2d00_discovering-existing-but-unknown-incisive-verification-featuresIt’s a Kind of Magic: How Calculated Messages Can Make You a Hero, and There Can Be More than One!http://feedproxy.google.com/~r/cadence/community/blogs/48486/~3/9L4cB_CwBn0/it-s-a-kind-of-magic-how-calculated-messages-can-make-you-a-hero-and-there-can-be-more-than-oneMon, 19 Jan 2015 21:45:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1338974Axel Scherer/cadence_blogs_8/b/fv/archive/2015/01/19/it-s-a-kind-of-magic-how-calculated-messages-can-make-you-a-hero-and-there-can-be-more-than-one0At the risk of dating myself—oops, it is too late, I already did so last August while talking about display density innovation —I will use a metaphor from a nineteen eighties movie to illustrate the power of calculated messages . Sometimes you come across a feature, or a product, that deserves the term magical . The late Steve Jobs used it when introducing the iPad in January 2010 . [Sorry I only found an iTunes link for the official footage.] Some people think his comment was over the top, but I think he truly believed it. When I used an iPad in an Apple Store for the first time , I could sense what he meant. At that moment, he got me, and I am truly a fan, if you have not realized it by now. For modern innovations like high precision, useful touch interfaces on smartphones, magic really did happen; at least at the time when those products hit the market. By now we are all used to it, and we have stopped appreciating the magic of devices using iOS and Android, although they only hit the market in 2007 and 2008 respectively—a mere seven and eight years ago! In 1986, the movie Highlander was a big hit (at least in Europe), in particular with adolescent males. Although it is somewhat of a fantasy movie, which I typically cannot stand, I must admit I liked this one at the time. I’m not sure what I would think if I saw it today for the first time. I will find out once my kids watch it with me some day—and if I am not too forgetful, I’ll report back on this channel. The gist of the movie is that there are these magical guys, stemming from the Scottish Highlands who are immortal. This immortality however, is a curse rather than a blessing. As we follow the main characters through the centuries, we discover that, for some odd reason, all Highlanders need to kill each other. Their motto is: There can be only one! So, our hero kills the other Highlanders, with a sword nonetheless, and even in the 20th century, if I recall correctly. Some of his opponents are also acting this way. The group is reduced over time until there are only two Highlanders left. The last one standing will become a mere mortal and shed himself of the curse of immortality. As we have the advantage of being mortal already, we do not have to go through all this bloodshed. However, it would be great to have a little bit of pure magic at our disposal. And I am happy to say that Cadence can give you some. As I mentioned in my last post about IoT and Incisive Debug Analyzer , we have a very potent and innovative debug product in the Incisive Debug Analyzer (IDA) that can dramatically increase your debug productivity. And, it has some magic in it, too! One aspect of this IDA magic is a feature called: Calculated Messages , which is another way to help you reduce debug iterations. During a complex debug cycle, you are in a quest looking for answers, looking for the cause of a problem. In the Highlander movie, the quest was to become mortal. In debugging, the quest is bug root cause analysis. A typical debug database or simulation run produces tons of data. It is your job to navigate this ocean of data and extract meaningful bits to help you find the cause of a problem. Often, this involves the annotation of additional log messages. Classically, it requires a change to your code, testbench, or DUT and then yet another simulation run, and a stop at the watercooler, or an extended coffee break in cases where you have a complex and long-running test. The classic approach is extremely expensive because of the extra run time, wait time, associated frustration, and loss of productivity due to temporal discontinuity of the debug process. IDA’s calculated message feature addresses this problem head on. A typical verification environment already includes a lot of message generation capability. You can control the message verbosity, the debug scope, and so on. However, up until recently, you were stuck with what you had. Now, with the magical message generation feature of IDA, you can add incremental messages on the fly. (Please visit the site to view this video) In other words, you can calculate new messages, whose values for variables and such, can be derived from your debug database. This is pretty awesome and you need to try it as soon as possible! Many users have found this to be a killer feature of the Incisive Debug Analyzer. To get a better sense of the magic at work, see the video below. Our motto is not: There can be only one! Instead it is: We can be heroes (too and for more than one day)! Axel Schererhttp://community.cadence.com/cadence_blogs_8/b/fv/archive/2015/01/19/it-s-a-kind-of-magic-how-calculated-messages-can-make-you-a-hero-and-there-can-be-more-than-oneSatisfy Your Need for Verification Speed—How to Run Your UVM Cowbell on Palladium XP in Acceleration Modehttp://feedproxy.google.com/~r/cadence/community/blogs/48486/~3/NFINa4Aml2c/satisfy-your-need-for-verification-speed-how-to-run-your-uvm-cowbell-on-palladium-in-acceleration-modeFri, 16 Jan 2015 00:05:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1338970Axel Scherer/cadence_blogs_8/b/fv/archive/2015/01/15/satisfy-your-need-for-verification-speed-how-to-run-your-uvm-cowbell-on-palladium-in-acceleration-mode0If you have been living in the US for the last few years (if not, I have a treat for you) and have paid any attention to TV ads, you&#39;ve probably seen the AT&amp;T Bigger is Better commercials, where an adult interviews a group of young children about which qualities are important to them. The mantra is that bigger, faster, more is better. We all know that this is not always the case. However, in verification we know that a simulation can never be fast enough. (Please visit the site to view this video) As design complexities grow, you need more and more complex tests. You need more machines and you struggle with your available resources. This struggle is dangerous because it might impact both the quality as well as the productivity of your verification efforts. If you miss a bug because you did not run that all-important test, you are in big trouble. If you wrote the entire set of required tests, but your iteration time is too slow, you risk missing the market window. You can have the biggest compute farm in the world, but it probably won’t save you. The critical, long-running tests are the long poles in the tent and will forever dominate your verification iteration time. Simulation tests that run for many hours, or even days, might kill your productivity. When you are in this situation you should take a serious look into simulation acceleration using the Cadence Palladium XP hardware accelerator. The Palladium accelerator can address not only the long pole problem, but in addition, it opens up opportunities for you to write longer and more complex tests that would be unrealistic on a simulator. Many engineers are afraid of using hardware acceleration because it can be intimidating. However, Cadence has developed collateral that will help you to get started and productive quickly. In particular, we show you how a few tweaks to your UVM environment can accommodate both high-speed simulation, as well as acceleration, all from the same verification environment! To help you understand UVM-based acceleration, we have published a set of introductory videos that will explain the basic concepts and walk you through an example that you can also access as a rapid adoption kit from Cadence online support. Don&#39;t miss these videos here: (Please visit the site to view this video) Bruce Dickison , might have a need for “ more cowbell !&quot;, but we all have a need for speed! Axel Schererhttp://community.cadence.com/cadence_blogs_8/b/fv/archive/2015/01/15/satisfy-your-need-for-verification-speed-how-to-run-your-uvm-cowbell-on-palladium-in-acceleration-modeHow I First Heard About Sebastian Thrun and Udacityhttp://feedproxy.google.com/~r/cadence/community/blogs/48486/~3/o1zbuQX-Xtw/how-i-first-heard-about-sebastian-thrun-and-udacityFri, 09 Jan 2015 17:54:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1338958Axel Scherer/cadence_blogs_8/b/fv/archive/2015/01/09/how-i-first-heard-about-sebastian-thrun-and-udacity0Before my wife became a writer, she was a director at Massachusetts General Hospital . In this position she met a lot of interesting people. Among them was Dr. Thomas Bernard Kinane , a pediatric pulmonologist. One day, he recommended that she watch Sebastian Thrun on the Charlie Rose television show. She was impressed enough with Sebastian and what he had to say, that she made me sit down and view the show myself. (Please visit the site to view this video) On the show, Sebastian talked about, and demonstrated, a technological innovation called Google Glass [see Sebastian’s interview at time 16:40]. This was the first time Google Glass was shown to a journalist. Sebastian, among many other things, is a Google Fellow, designed Google StreetView , the self-driving car , was the leader of Google X Lab , and was a CMU and Standford professor for robotics and artificial intelligence. He is the most accomplished and revered innovator that I have had the pleasure to meet (more on that later). Google Glass is certainly very interesting to me, as an engineer. However, what really struck a chord with me was his mentioning of Udacity , the online university providing Massive Open Online Courses, MOOC s. In my position at Cadence Design Systems , I have been involved in developing training for engineers for many years. Before I learned about Udacity, I heard of the works of Salman Khan and his Khan Academy in an OnPoint interview . I was fascinated by his approach, and I tried to apply it to my work by creating a series of videos that help engineers ramp up on very specific and niche concepts and software features . It quickly became the most viewed video series on the Cadence YouTube channel. During this time we were exploring other methods for training more engineers in an effective manner. As a result, the MOOC approach that Udacity was taking sounded very compelling and suitable for our needs. Shortly after I watched the Charlie Rose interview [see the Udacity segment at time 26:40] I approached Udacity and got the opportunity to meet Sebastian himself. Somehow, I was able to convince him [it still baffles me as to how I pulled that off] to let Cadence create a class with Udacity! This class became CS348 Functional Hardware Verification . As a side note–a few months later, a Time magazine article titled College is Dead. Long Live College! about MOOCs and Udacity was published as the cover story. It was then that I found out that I was very lucky indeed to have been selected as an instructor, because Sebastian had already turned down 500 university professors who volunteered to create courses for Udacity! To wrap this up, my adventure with MOOCs and my encounter with Sebastian would have never occurred had my wife not had the insight to force me to view the Charlie Rose program. I am very grateful for her recommendation as it allowed me to become an instructor at Udacity . Stay udacious! Axel Schererhttp://community.cadence.com/cadence_blogs_8/b/fv/archive/2015/01/09/how-i-first-heard-about-sebastian-thrun-and-udacityComment on Expectations Versus Reality — How I Misjudged the Apple MacBook Pro Retina Displayhttp://feedproxy.google.com/~r/cadence/community/blogs/48486/~3/K_bNXrCump0/how-i-misjudged-the-apple-macbook-pro-retina-displayMon, 08 Sep 2014 20:39:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:2058Axel Schererhttp://community.cadence.com/cadence_blogs_8/b/fv/archive/2014/09/02/how-i-misjudged-the-apple-macbook-pro-retina-displayScott - Unfortunately, we do not have an immediate plan for OS X support for verification products.http://community.cadence.com/cadence_blogs_8/b/fv/archive/2014/09/02/how-i-misjudged-the-apple-macbook-pro-retina-displayMy First Internet of Things Device: Moving from a Manual to an Automated Process—Debug Analyzer vs. Simple Logginghttp://feedproxy.google.com/~r/cadence/community/blogs/48486/~3/R24RZCGFh64/my-first-internet-of-things-device-moving-from-a-manual-to-an-automated-processMon, 08 Sep 2014 17:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1338031Axel Scherer/cadence_blogs_8/b/fv/archive/2014/09/08/my-first-internet-of-things-device-moving-from-a-manual-to-an-automated-process0The Internet of Things (IoT) has been a buzzword for quite some time now. However, thus far it has not seen wide adoption or market penetration in the home; this, at least, has been my observation. And, in my circle of friends, hardly anyone has adopted any home IoT devices. Some have flirted with the idea of buying devices like the Nest advanced thermostat, now owed by Google. However, they have not pulled the trigger and actually bought any. Although I typically tend to be on the early adopter side of the bell curve when it comes to technology adoption-and I believe IoT will be big--I did not have a compelling reason to get into the game with devices for my home, at least until now. However, when I sat down and connected the dots, I realized that I have a perfect application for an IoT device. Many parents out there have experienced similar phases in the &quot;going to bed&quot; habits of their kids. My youngest son is in the phase of: Can&#39;t go to bed without the light on . He just traded with his older brother, who no longer has this problem. However, the light my little one &quot;demands&quot; cannot merely be a nightlight. It has to be a fairly bright light to satisfy him. Obviously, I do not want to have the light on all night for two reasons: It is not good for his sleep It is a waste of energy (even though I use CFLs) Hence, the typical nighttime drill is this: Potty time (use the toilet for you non-US folks out there) Teeth brushing Storybook reading Waiting until he is in a deep sleep and returning to shut his light off This routine works pretty well, but sometimes turning the light off wakes him up. There ought to be a better way, and there is. The other night I was too tired to walk over to turn off his light. But I still did it. However, I thought that this is too stupid a method to be using in 2014 - I needed to automate this process. So I searched around and found a smartphone-controllable LED light bulb for his room with the associated controller hub! Specifically, I got the TCP Connected smart lighting system. The experience was amazing. The hub setup was trivial and the app is very user friendly. You can witness my first test in the video below. (Please visit the site to view this video) Besides the buzz and the general interest in the space, IoT in general and home automation in particular, it&#39;s not just marketing hype--there are serious dollars behind it. One recent example is the $90M cash infusion into a company called Savant. Further on, Apple announced an API for this space called HomeKit at their developer conference in June. It seems that home automation with IoT devices is about to take off. However, one of the challenges to IoT home automation adoption is that old habits are hard to break. Even I, typically an early adopter of technology, sometimes get stuck in old and inefficient ways of performing a task. To this day I still tend to use vi when editing code on Linux-It is my default mode of operation. And, while I am fully aware of the advantages in editing e or SystemVerilog code using an IDE such as Eclipse , particularly when it is extended for the use of HVLs with DVT , it still takes a special effort to move away from such true and trusted approaches in order to gain additional automation and productivity. Many design and verification engineers follow similar habits. For example, when debugging code they spike it with lots of print statements and then peruse the resulting log file. There is nothing wrong with this approach in and of itself--it is a classic and trusted method that gives the developer the information he or she wants, while being productive. However, since code is getting continually more complex, like HDLs mixed with HVLs and so on., one quickly gets caught up in what can appear to be an infinite iterative loop. For example, because of a log message A , the developer now needs additional information, such as the value of a variable B , and so on. Consequently, the code has to be edited and re-edited, and the simulation has to run again and again. With a small verification environment, such iterations can be fairly quick. However, at a complex sub-system level, such iterations might take several minutes, or even hours, which can add up very quickly to a lot of frustrating wait time. Besides frustration and wasted time, debugging iterations like this can also reduce productivity in other ways. Debugging is a very complex and intellectually demanding task. Any interruption or wait time will reduce the debug progress. The person debugging has certain thoughts and assumption she uses in determining the cause of a failure. If it takes a long time to get answers to these assumptions, then the debug productivity is adversely affected. In other words, the human idea caching is reduced. It is exactly for this reason that Cadence introduced Incisive Debug Analyzer. With Incisive Debug Analyzer, large portions of the productivity problems inherent in iterated debugging are addressed. Many of the debug iteration loops are cut out of the process altogether. One still needs to annotate the code with debug messages. But those messages become smart log messages. A smart log message is an advanced log message that can come from multiple sources, be it HVL such as e [IEEE 1647] or SystemVerilog [IEEE 1800], HDL, C, C++ or even assertions. A powerful feature of Incisive Debug Analyzer smart logging is that it allows you to change the verbosity level of log messages without having to re-run the simulation. Incisive Debug Analyzer contains numerous other features that let you interact with log messages to hone in on the root cause of a bug more quickly. Smart logs are also synced up with the waveform database, providing a consistent view of the current simulation time. In addition, Incisive Debug Analyzer enables effective interactive debugging. For example, assume you are stepping through a simulation and you halt using a breakpoint. If you now advance the simulation accidentally, or if you halted because of a wrong assumption, you might have to start the simulation all over again. With Incisive Debug Analyzer, however, you can move both forward and backward through simulation time, reducing many simulation runs. You can do this because the HVL and HDL code is not being simulated. Instead, recorded values in the Incisive Debug Analyzer database are being stepped though. Consequently, the execution through time is orders of magnitude faster than in a live interactive simulation. These are just some of the ways Incisive Debug Analyzer can help your debug process. For a full description, check out this link . Bottom Line: Incisive Debug Analyzer can increase your debug productivity by automating a classic and manual debug process. Long live efficiency! Axel Scherer Incisive Product Expert Team Twitter , @axelschererhttp://community.cadence.com/cadence_blogs_8/b/fv/archive/2014/09/08/my-first-internet-of-things-device-moving-from-a-manual-to-an-automated-processComment on Expectations Versus Reality — How I Misjudged the Apple MacBook Pro Retina Displayhttp://feedproxy.google.com/~r/cadence/community/blogs/48486/~3/K_bNXrCump0/how-i-misjudged-the-apple-macbook-pro-retina-displayThu, 04 Sep 2014 08:27:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:2446Axel Schererhttp://community.cadence.com/cadence_blogs_8/b/fv/archive/2014/09/02/how-i-misjudged-the-apple-macbook-pro-retina-displayHi Daniel, Agree the 17&quot; is amazing. A west coast colleague is using one and it is awesome. But you still can see pixels ;)http://community.cadence.com/cadence_blogs_8/b/fv/archive/2014/09/02/how-i-misjudged-the-apple-macbook-pro-retina-displayComment on Expectations Versus Reality — How I Misjudged the Apple MacBook Pro Retina Displayhttp://feedproxy.google.com/~r/cadence/community/blogs/48486/~3/K_bNXrCump0/how-i-misjudged-the-apple-macbook-pro-retina-displayThu, 04 Sep 2014 08:25:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1704Axel Schererhttp://community.cadence.com/cadence_blogs_8/b/fv/archive/2014/09/02/how-i-misjudged-the-apple-macbook-pro-retina-displayHi Gary, Yes I am aware. But I have still a 15&quot; non-retina MPB. The retina is my wife&#39;s ;)http://community.cadence.com/cadence_blogs_8/b/fv/archive/2014/09/02/how-i-misjudged-the-apple-macbook-pro-retina-display