Computer vision algorithms, which play an significant role in vision processing, is widely applied in many aspects such as geology survey, traffic management and medical care, etc.. Most of the situations require the process to be real-timed, in other words, as fast as possible. Field Programmable Gate Arrays (FPGAs) have a advantage of parallelism fabric in programming, comparing to the serial communications of CPUs, which makes FPGA a perfect platform for implementing vision algorithms. These algorithms usually have a very high computation power because the objects, a large amount of pixels of a single picture, have to be proceeded not once, but many times. This project reconfigured onto the FPGA board, Terasic DE2i-150, a partial of a algorithm that has multiplexing computations. The algorithm of Harris corner detection is chosen, which contains an important step in many vision processing and is of good performance. The reconfiguration of the most time-consuming portion has synthesized onto the board and a result is presented to demonstrate the performance and the capacity of the FPGA. It shows that even a low-cost FPGA in 50MHz can achieve a faster speed than that of some CPUs due to the parallelism, which is the specialization of FPGAs and is unfeasible to apply to software.