case2a) Clock and data emerge at same time from source. Clock is given
somewhat more delay so data arrives at destination first.
Data transmitted on Clock(N)
Data received on Clock(N) for setup
Data held against Clock(N-1)
Setup does not require jitter to be include in calculation.
Hold requires jitter to be included in calculation.

case2b) Clock and data emerge at same time from source. Clock is given
somewhat less delay so clock arrives at destination first.
Data transmitted on Clock(N)
Data received on Clock(N+1) for setup
Data held against Clock(N)
Setup requires jitter to be include in calculation.
Hold does not require jitter to be included in calculation.

case2c) Clock is pre-timed to emerge from source when data is stable.
Clock and data are given equal delays to the destination, and arrive
alternating.
Data transmitted on Clock(N)
Data received on Clock(N+1) for setup
Data held against Clock(N-1)
Setup requires jitter to be include in calculation.
Hold requires jitter to be included in calculation.

In all cases, "jitter" means the jitter of the internal clock that drives
both the external clock and the data.

Case 2c might be used if there is a faster (2x) internal clock, or
rising/falling clock edges, that can be used to alternate the source
synchronous clock and the data transitions being driven. Invariably, that
2x clock has some jitter, which should be accounted for ... whether that is
done by building it into the IC specs (if it's a known quantity that is
determined solely by the IC), or by explicitly adding it later when you do
timing verification.

No matter what you do, it always helps to get a good understanding of
exactly what's doing what. I try to avoid blindly adding up numbers without
picturing it in my head (or on paper) to make sure it really makes sense.

Regards,
Andy

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