Abstract:

An active clamp circuit for electronic components includes two sets of
diode connected transistors that are inversely connected in parallel
across an output of the component for providing both positive and
negative differential conducting paths. The diode connected transistors
cooperatively operate to limit a differential output voltage between the
positive and negative conducting paths. An emitter follower buffer
includes the clamp circuit and is configured to limit RF energy incident
to an analog to digital converter (ADC). The emitter follower buffer
includes two input transistors having their emitters each connected to at
least one diode connected transistor connected to the clamp circuit. A
receiver includes the differential amplifier and an analog to digital
converter. A method for limiting the energy of analog signals in the
receiver includes the step of operating the clamp circuit to limit the
analog signals transmitted to the analog to digital converter (ADC).

Claims:

1. An active clamp circuit, comprising:an output adapted to provide a
differential voltage between a positive conducting path and a negative
conducting path;at least one first diode connected transistor structured
and arranged to pass a first current along the positive conducting path
between two conductive lines connected to the output; andat least one
second diode connected transistor structured and arranged to pass a
second current along the negative conducting path between the two
conductive lines;the at least one first diode connected transistor and
the at least one second diode connected transistor cooperatively operable
to adaptively limit the differential voltage at the output.

3. The active clamp circuit of claim 1, wherein the at least one first
diode connected transistor is configured to clamp the first current
responsive to a positive differential voltage of an input signal of the
active clamp circuit being greater than a positive clamping voltage
(Vclampp).

4. The active clamp circuit of claim 3, wherein the positive clamping
voltage (Vclampp) equals a sum of turn-on voltages (VBe) of the
at least one first diode connected transistor.

5. The active clamp circuit of claim 1, wherein the at least one second
diode connected transistor is configured to clamp the second current
responsive to a negative differential voltage of an input signal of the
active clamp circuit being less than a negative clamping voltage
(Vclampn).

6. The active clamp circuit of claim 5, wherein the negative clamping
voltage (Vclampn) equals a sum of turn-on voltages (VBe) of the
at least one second diode connected transistor.

7. The active clamp circuit of claim 1 further comprising:at least one
positive differential path diode connected transistor adapted to shift
down a first voltage along the positive conducting path; andat least one
negative differential path diode connected transistor adapted to shift
down a second voltage along the negative conducting path.

8. The active clamp circuit of claim 1, wherein the at least one positive
differential path diode connected transistor, the at least one negative
differential path diode connected transistor, the at least one first
diode connected transistor and the at least one second diode connected
transistor all comprise an equal number of transistors.

9. An active clamp circuit for an electronic component, the active clamp
circuit comprising:a positive input transistor adapted to pass an input
signal on the positive conducting path;a negative input transistor
adapted to pass the input signal on the negative conducting path;an
output adapted to provide a differential voltage between the positive
conducting path and the negative conducting path;at least one first diode
connected transistor electrically connected across the output and
configured to clamp the positive conducting path responsive to a positive
differential voltage (Voutp) of the output being greater than a
positive clamping voltage (Vclampp); andat least one second diode
connected transistor electrically connected across the output in inverse
parallel to the first diode connected transistor, the at least one second
diode connected transistor configured to clamp the negative conducting
path responsive to a negative differential voltage (Voutn) of the
output being less than that of a negative clamping voltage
(Vclampn).

10. The active clamp circuit of claim 9, wherein the at least one first
diode connected transistor comprises a plurality of first diode connected
transistors connected in series, and the at least one second diode
connected transistor comprises a plurality of second diode connected
transistors connected in series.

14. The active clamp circuit of claim 9, further comprising an external
attenuator electrically connected to the output terminal.

15. An emitter follower buffer for an electronic component, the emitter
follower buffer comprising:a positive input transistor adapted to pass an
input signal on the positive conducting path;a negative input transistor
adapted to pass the input signal on the negative conducting path;an
output adapted to provide a differential voltage between the positive
conducting path and the negative conducting path;a first set of a
plurality of first diode connected transistors electrically connected in
series across the output of the electronic component and configured to
clamp the positive conducting path responsive to a positive differential
voltage (Voutp) of the output being greater than a positive clamping
voltage (Vclampp); anda second set of a plurality of second diode
connected transistors electrically connected in series across the output
in inverse parallel to the first diode connected transistors, the second
set configured clamp the negative conducting path responsive to a
negative differential voltage (Voutn) of the output being less than
that of a negative clamping voltage (Vclampn);the positive clamping
voltage (Vclampp) being dependent on a number of the first diode
connected transistors and the negative clamping voltage (Vclampn)
being dependent on a number of the second diode connected transistors.

16. The emitter follower buffer of claim 15, wherein the positive clamping
voltage (Vclampp) is set at a predetermined voltage greater than or
equal to a sum of turn-on voltages (VBe) of the first diode
connected transistors.

17. The emitter follower buffer of claim 15, wherein the negative clamping
voltage (Vclampn) is set at a predetermined voltage greater than or
equal to a sum of turn-on voltages (VBe) of the second diode
connected transistors.

18. The emitter follower buffer of claim 15, wherein the first diode
connected transistors and the second diode connected transistors comprise
NPN transistors having their bases shorted to their drains.

19. The emitter follower buffer of claim 15, wherein the first diode
connected transistors and the second diode connected transistors are
connected emitter to collector.

20. The emitter follower buffer of claim 15 further comprising:a set of
positive differential path diode connected transistors adapted to shift
down a first voltage along the positive conducting path; anda set of
negative differential path diode connected transistors adapted to shift
down a second voltage along the negative conducting path.

21. The emitter follower buffer of claim 20, wherein the first set of the
plurality of first diode connected transistors, the second set of the
plurality of second diode connected transistors, the set of positive
differential path diode connected transistors, and the set of negative
differential path diode connected transistors all comprise an equal
number of transistors.

22. The emitter follower buffer of claim 15, further comprising:a positive
conducting path bias source in electrical communication with the first
set of the plurality of first diode connected transistors; anda negative
conducting path bias source in electrical communication with the second
set of the plurality of first diode connected transistors.

23. The emitter follower buffer of claim 15 further comprising an external
attenuator electrically connected to the output.

24. The emitter follower buffer of claim 15 wherein the output terminal is
in electrical communication with an analog to digital converter (ADC) and
the first set and the second set of diode connected transistors limit RF
energy incident to the analog to digital converter (ADC).

25. A receiver comprising:an analog to digital converter (ADC) configured
to convert analog signals to digital signals; andan emitter follower
buffer comprising:a positive input transistor adapted to pass an input
signal on a positive conducting path;a negative input transistor adapted
to pass the input signal on a negative conducting path;an output terminal
in electrical communication with the analog to digital converter and
adapted to provide a differential voltage between the positive conducting
path and the negative conducting path to the analog to digital
converter;a first set of a plurality of first diode connected transistors
electrically connected in series across the output terminal of the
electronic component and configured to clamp the positive conducting path
responsive to a positive differential voltage (Voutp) of the output
terminal being greater than a positive clamping voltage (Vclampp);
anda second set of a plurality of second diode connected transistors
electrically connected in series across the output terminal in inverse
parallel to the first diode connected transistors, the second set
configured to clamp the negative conducting path responsive to a negative
differential voltage (Voutn) of the output terminal being less than
that of a negative clamping voltage (Vclampn);the positive clamping
voltage (Vclampp) being dependent on a number of the second diode
connected transistors and the negative clamping voltage (Vclampn)
being dependent on a number of the second diode connected transistors.

26. The receiver of claim 25 further comprising an external attenuator
electrically connected to the output terminal.

27. The receiver of claim 25, wherein the receiver comprises a radar
receiver.

28. The receiver of claim 25, wherein the receiver comprises a radio
receiver.

29. A method for limiting energy of analog signals in an electrical device
having an output, comprising:converting the analog signals to digital
signals;connecting at least two sets of diode connected transistors in an
inverse parallel relationship across the device output;establishing a
clamping voltage across each of the at least two sets of diode connected
transistors;measuring an output voltage at the device output;comparing
the output voltage to each of the clamping voltages;selectively clamping
one of the at least two sets of diodes in response to the relative values
of the output voltage to each of the clamping voltages.

30. The method of claim 29 wherein one of the clamping voltages is a
positive voltage (Vclampp) and one of the clamping voltages is a
negative voltage (Vclampn)

31. The method of claim 30 further comprising setting the positive
clamping voltage (Vclampp) by selecting a turn-on voltage (VBe)
and at least one of the at least two sets of diode connected transistors.

32. The method of claim 30 further comprising setting the negative
clamping voltage (Vclampn) by selecting a turn-on voltage (VBe)
and the other of the at least two sets of diode connected transistors.

Description:

FIELD

[0001]This invention relates generally to the field of analog to digital
converters (ADCs), and more specifically to active clamp circuits.

BACKGROUND

[0002]Analog to digital converters (ADC's) are used in various electronic
systems for converting analog signals to corresponding digital signals.
An analog signal is any variable signal continuous in both time and
amplitude, whereas a digital signal is represented by a series of data
bits such as logical "0" and "1". With analog signals, small fluctuations
in the signal can imply meaning, but they may also be simply noise. With
repeated transmission, duplication and processing noise elements can
inadvertently become dominant. Translation of the analog signal to a
digital signal can achieve both high fidelity and perfect reproduction
capability and, as such, is often highly desirable.

[0003]One type of analog to digital converter (ADC) called a delta-sigma
ADC (also known as a sigma-delta ADC) subtracts a feedback signal from
the analog input signal to provide an error signal. The error signal is
then quantified and filtered to form a digital output signal.

[0004]High-resolution analog to digital converters (ADC) are used in
radar, missile and communication systems. For example, in receivers for
radar systems, RF signals are downconverted to an intermediate frequency
(IF), which are then fed into an analog to digital converter (ADC) for
conversion into digital signals.

[0005]One problem with analog to digital converters (ADCs) is that large
input signals can cause oscillation, or limit cycling, in the digital
output signals, which can shut down the entire system. For example, in a
radar receiver, large input signals (e.g., co-channel interference, large
main bang leakage due to mistimed bases, or bright close range targets
with improper gain control) can cause the analog to digital converter
(ADC) to oscillate. The analog to digital converter (ADC) can remain in
this state (i.e., oscillation of the digital output signals)
indefinitely, or until another strong input signal initiates a normal
operational state.

[0006]In order to alleviate oscillation, gain control circuits can be used
to detect and process signals that are outside of an acceptable signal
strength. For example, U.S. Pat. No. 7,088,794 to Nichols, and U.S. Pat.
No. 6,191,725 to Lavoie disclose radar systems having gain control
circuits. Another approach to this problem involves changing the
architecture of the analog to digital converter (ADC) to suppress limit
cycles.

[0007]Unfortunately neither of these approaches has achieved completely
satisfactory results. A particular shortcoming is a significant
degradation in receiver dynamic range.

[0008]Hence there is a need for a circuit that overcomes one or more of
the technical problems as stated above.

SUMMARY

[0009]This invention provides a clamp circuit for limiting energy to
certain electronic components including, but not limited to, receivers
such as may be found in radar and communication systems.

[0010]In particular, and by way of example only, according to one
embodiment of the present invention, provided is an active clamp circuit
for an electronic component including two sets of diode connected
transistors connected in inverse parallel across an output of the
component for providing a positive conducting path and a negative
conducting path between two conductive lines of the component output. The
sets of diode connected transistors cooperatively operate to limit a
differential voltage between the positive conducting path and the
negative conducting path provided to the following electronic component.
Each set of diode connected transistors is configured to clamp its
associated current path in response to a differential voltage (Vout)
at the output of the component being outside of a voltage range defined
by Vclampn and Vclampp. Thus, clamping is provided on a
positive current path when the positive differential voltage (Voutp)
of the output is greater than Vclampp. Likewise, clamping is
provided on a negative current path when the negative differential
voltage (Voutn) of the output is less than Vclampn. Prior to
the positive differential voltage (Voutp) at the output reaching the
clamping voltage (Vclampp), the diode connected transistors appear
transparent and do not significantly affect the small signal linearity of
the clamp circuit. A similar effect is found with respect to the negative
current path. The clamping voltages (Vclampn and Vclampp) are
dependent upon turn-on voltages (VBe) of the diode connected
transistors, and on the number of transistors in each set.

[0011]In an illustrative embodiment, the electronic component comprises an
emitter follower buffer in a differential configuration with a positive
and negative differential conducting path. The differential emitter
follower buffer includes positive and negative input transistors.
Following the input transistors of each conducting path may be at least
one diode configured transistor which is connected to the clamp circuit
and adapted to shift down a voltage along its associated conducting path.
The differential emitter follower buffer also includes positive and
negative differential path current sources, and can optionally include an
external attenuator for providing a non-discrete clamping voltage.

[0012]A method for limiting the energy of analog signals in a receiver
includes the steps of providing an ADC in the receiver, providing a
differential amplifier having an output connected to the ADC and a clamp
circuit comprising diode connected transistors connected in inverse
parallel, and then operating the clamp circuit to limit analog signals
transmitted to the ADC. The method can also include the step of setting a
clamping voltage (Vclamp) of the clamp circuit by selecting the
number of diode connected transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]Exemplary embodiments are illustrated in the referenced figures of
the drawings. It is intended that the embodiments and the figures
disclosed herein are to be considered illustrative rather than limiting.

[0014]FIG. 1 is an electrical schematic of a differential emitter follower
buffer having an active clamp circuit in accordance with at least one
embodiment;

[0015]FIG. 2 is a block diagram of a receiver incorporating the
differential emitter follower buffer illustrated in FIG. 1 in accordance
with at least one embodiment; and

[0016]FIG. 3 is a block diagram illustrating steps in a method for
limiting RF energy in the receiver in accordance with at least one
embodiment.

DETAILED DESCRIPTION

[0017]Before proceeding with the detailed description, it is to be
appreciated that the present teaching is by way of example only, not by
limitation. The concepts herein are not limited to use or application
with a specific type of adaptive clamp circuit or method of limiting
energy in a circuit. Thus, although the instrumentalities described
herein are for the convenience of explanation, shown and described with
respect to exemplary embodiments, it will be appreciated that the
principles herein may be applied equally in other types of clamp circuits
and clamping methodologies.

[0018]To further assist in the following description, the following
defined terms are provided.

[0019]As used herein, "transistor" is understood and appreciated to be a
bipolar junction transistor (BJT) constructed using a conventional
fabrication process, such as a silicon germanium (SiGe) fabrication
process. The BJTs can have an NPN configuration, or a PNP configuration.
In the description to follow the BJTs have three external terminals
including: a base (B), a collector (C), and an emitter (E). The concepts
described herein can be extended to the use of field effect transistors
(FETs).

[0020]A "diode connected transistor" is understood and appreciated to be a
BJT having two terminals shorted together to provide a diode
configuration in which current is transmitted in only one direction.

[0021]Referring to FIG. 1, an electronic component in the form of a
differential emitter follower buffer 100 is illustrated. The differential
emitter follower buffer 100 includes an NPN input transistor (112, 114)
for both the positive 102 and negative 104 differential conducting paths.
In at least one embodiment, the input transistors 112, 114 are NPN
transistors having their bases (B) connected to an input source 116. The
input source 116 is configured to provide analog input signals, such as
intermediate frequency (IF) signals derived from RF signals. The
collectors (C) of the input transistors 112, 114 are connected to Vcc
110.

[0022]The differential emitter follower buffer 100 (FIG. 1) also includes
an output terminal 124 for the positive differential path 102, and an
output terminal 126 for the negative differential path 104. A resistor
128 between the output terminals 124, 126 represents the differential
output load. The differential emitter follower buffer 100 also includes a
positive differential path bias current source 130 and negative
differential path bias current source 132, both of which are denoted
(lbias). As shown in FIG. 1, the bias current sources 130, 132 are
connected to ground 133.

[0023]The differential emitter follower buffer 100 (FIG. 1) also includes
a positive differential path diode connected transistor 118 having its
collector (C) connected to the emitter (E) of the NPN input transistor
112, and a negative differential path diode connected transistor 120
having its collector (C) connected to the emitter (E) of the NPN input
transistor 114. The diode connected transistors 118, 120 have their bases
(B) and their collectors (C) shorted together, such that the bases (B)
receive the output from the input transistors 112, 114. Diode connected
transistors 118, 120 are provided to shift down the voltage along the
current path.

[0024]The emitter follower buffer 100 (FIG. 1) also includes a clamp
circuit 122, which comprises a first set of diode connected transistors
134, and a second set of diode connected transistors 136 connected in
inverse parallel across the output terminals 124, 126 of the emitter
follower buffer 100. Diode connected transistors 138 and 140 provide a
negative clamping path. Diode connected transistors 142 and 144 are
connected in the opposite direction of diode connected transistors 138
and 140 to provide a positive clamping path.

[0025]In the clamp circuit 122 (FIG. 1), the negative conducting path
(represented by arrow 135) of the first set of diode connected
transistors 134 is inversely connected to the positive conducting path
(represented by arrow 137) of the second set of diode connected
transistors 136. This provides a current path through the first set of
diode connected transistors 134 for a negative differential voltage 124
at the output, denoted (Voutp), and a current path through the
second set of diode connected transistors 136 for a positive differential
voltage 126 at the output, denoted (Voutn).

[0026]The clamping voltage (Vclamp) can be expressed as either a
positive clamping voltage (Vclampp) or a negative clamping voltage
(Vclampn). During operation of the clamp circuit 122, if the
difference of the positive differential voltage 124 (Voutp) and the
negative differential voltage 126 (Vout) has a value less than the
positive clamping voltage (Vclampp), then the first diode connected
transistor 142 and the second diode connected transistor 144 of the first
set of diode connected transistors 136 are in an "OFF" state and appear
transparent to positive conducting path 136. Thus, no clamping is
provided on the positive conducting path 137. Similarly, if the
difference of the negative differential voltage 126 (Voutn) and the
positive differential voltage 124 (Voutp) has an absolute value less
than that of a negative clamping voltage (Vclampn) (i.e., is less
negative), then the first diode connected transistor 138 and the second
diode connected transistor 140 of the second set of diode connected
transistors 134 are in an "OFF" state and appear transparent to negative
conducting path 135. Thus, no clamping is provided on the negative
conducting path 135.

[0027]During operation of the clamp circuit 122, if the difference of the
positive differential voltage at output terminal 124 (Voutp) and the
negative differential voltage at output terminal 126 (Voutn) is
greater than the positive clamping voltage (Vclampp), then the first
diode connected transistor 142 and the second diode connected transistor
144 of the first set of diode connected transistors 136 are in an "ON"
state and provide clamping on positive conducting path 137. Similarly, if
the difference of the negative differential voltage at output terminal
126 (Voutn) and the positive differential voltage at output terminal
124 (Voutp) has an absolute value greater than that of the negative
clamping voltage (Vclampn) (i.e., is less negative), then the first
diode connected transistor 138 and the second diode connected transistor
140 of the second set of diode connected transistors 134 are in an "ON"
state and provide clamping on the negative conducting path 135.

[0028]In the clamp circuit 122, the positive clamping voltage
(Vclampp) is dependent on base-emitter turn-on voltages (VBe)
for the diode connected transistors 142, 144. The negative clamping
voltage (Vclampn) is dependent on base-emitter turn-on voltages
(VBe) for the diode connected transistors 138, 140. Also in the
clamp circuit 122, the positive clamping voltage (Vclampp) is a
function of the number of diode connected transistors 142, 144, as it is
derived from the sum of the base-emitter turn-on voltages (VBe) of
the diode connected transistors 142, 144. Similarly, the negative
clamping voltage (Vclampn) is a function of the number of diode
connected transistors 138, 140, as it is derived from the sum of the
base-emitter turn-on voltages (VBe) of the diode connected
transistors 138, 140. Moreover, for each set 134 and 136 it is understood
and appreciated that in at least one embodiment the number of diode
connected transistors is two, as shown, however, in alternative
embodiments a greater or lesser number may be employed. By way of
example, the clamping voltage (Vclampp or Vclampn) can be set
at a selected voltage relative to the sum of the base-emitter turn-on
voltages (VBe) for the diode connected transistors 138, 140 or 142,
144 (e.g., Vclampp or Vclampn=sum of (VBe)).

[0029]The minimum clamping voltage (Vclampp or Vclampn)
achievable by the clamp circuit 122 is attained when only a single diode
connected transistor 138, 140, 142 or 144 is connected in series across
the output terminals 124, 126. Similarly, the minimum clamping voltage
(Vclamp) can be increased by increasing the number of diode
connected transistors 138, 140, 142, 144. In the illustrative embodiment,
each set of diode connected transistors 134, 136 has two diode connected
transistors (138, 140) and (142, 144). However, it is to be understood
that each set of diode connected transistors 134, 136 can have any number
of diode connected transistors 138, 140, 142, 144 (e.g., from one to one
hundred).

[0030]To briefly restate, the clamp circuit 122 comprises at least one
first diode connected transistor (e.g., diode connected transistors 142,
144) structured and arranged to pass a first current along positive
conducting path 137 between two conductive lines connected to output
terminals 124, 126, and at least one second diode connected transistor
(e.g., diode connected transistors 138, 140) structured and arranged to
pass a second current along negative conducting path 135 opposite to the
first direction. The diode connected transistors 142, 144 and the diode
connected transistors 138, 140 cooperatively operate to adaptively limit
a differential output voltage at output terminals 124 and 126 of emitter
follower buffer 100 and clamp circuit 122.

[0031]Further, the diode connected transistors 142, 144 are configured to
clamp the positive current path 137 responsive to the difference of the
positive differential voltage 124 (Voutp) and negative differential
voltage of the output being greater than a positive clamping voltage
(Vclampp). The second diode connected transistors 138, 140 are
configured to clamp the negative current path 135 responsive to the
difference of the negative differential voltage 126 (Voutn) and the
positive differential voltage 124 (Voutp) of the output being less
than that of a negative clamping voltage (Vclampn). The positive
clamping voltage (Vclampp) is dependent upon turn-on voltages
(VBe) of the diode connected transistors 142, 144, and the negative
clamping voltage (Vclampn) is dependent upon turn-on voltages
(VBe) of the diode connected transistors 138, 140.

[0032]Optionally, in at least one embodiment, a non-discrete clamping
voltage (Vclampp or Vclampn) can be obtained by placing an
external attenuator 146 in electrical communication with the output
terminals 124, 126. The diode connected transistors 138, 140, 142, 144
provide only discrete clamping voltages (Vclampp and Vclampn),
with the configurable discrete clamping voltage levels (Vclampp and
Vclampn) being dependent on the turn-on voltages of the diode
connected transistors 138, 140, 142, 144. The external attenuator 146 may
be configured to further reduce a clamped output differential voltage at
output terminals 124, 126 such that a non-discrete clamping voltage is
provided.

[0033]The clamp circuit 122 provides clamping similar to a conventional
diode limiter but approaches an ideal diode response. In this regard,
conventional diode limiters have a soft "knee" in which the voltage
response through the limiter is not hard-clamped but is still non-linear.
One such conventional diode limiter is a ring quad diode manufactured by
Agilent Technologies of Santa Clara, Calif., designated as part number
"HSMS-2817". In advantageous contrast to these types of conventional
diode limiters, the present clamp circuit 122 (FIG. 1) has a much sharper
clamp knee, and significantly reduced small signal suppression over its
operating range, thereby recovering any lost dynamic range. Further, the
circuit topology of the clamp circuit (FIG. 1) is flexible, in that it
can be configured to clamp over a range of discrete voltage levels in
steps of diode drops by adding or removing diode connected transistors
138, 140, 142, 144. Further, the external attenuator 146 (FIG. 1) can be
used for clamp levels between the diode drops if needed.

[0034]Referring to FIG. 2, a receiver 200 incorporating the emitter
follower buffer 100 (FIG. 1) is illustrated. In other embodiments,
receiver 200 may comprise other types of radio receivers. The receiver
may be of a type used in radio radar, communication and other types of
electronic systems in which a clamping circuit may advantageously be
employed. In at least one embodiment, the receiver is a radar receiver.
The receiver 200 is configured to receive an analog RF input signal 202.
By way of example, the RF input signal 202 can comprise a radar pulse
converted to an intermediate frequency using techniques that are known in
the art. The receiver 200 also includes a mixer 204 configured to
downconvert the RF input signal 202 to an IF signal. The output of the
mixer 204 is connected to the emitter follower buffer 100 having the
clamp circuit 122 (FIG. 1) as previously described.

[0035]The receiver 200 (FIG. 2) also includes an analog to digital
converter (ADC) 206 having its input connected to the output of the
emitter follower buffer 100. The receiver 200 also includes a digital
signal processor (DSP) 208 configured to receive the digital signals from
the analog to digital converter (ADC) 206, and a graphical user interface
210 such as a display screen. During operation of the receiver 200 (FIG.
2) the emitter follower buffer 100 functions to limit IF energy to the
ADC 206.

[0036]FIG. 3 illustrates a method 300 in accordance with at least one
embodiment for limiting the energy of analog signals transmitted to the
ADC 206 of the receiver 200 (FIG. 2). It is also understood and
appreciated that the disclosed method need not be performed in the order
herein described, but that this order of description is exemplary of at
least one embodiment and has been selected for ease of discussion and
illustration.

[0037]The method 300 includes the steps of providing the receiver 200 with
the ADC 206 (step 302), providing the emitter follower buffer 100 having
the clamp circuit 122 connected to the ADC 206 (step 304), and then
operating the clamp circuit 122 to limit the analog signals transmitted
to the ADC 206 (step 306).

[0038]Changes may be made in the above methods, systems and structures
without departing from the scope hereof. It should thus be noted that the
matter contained in the above description and/or shown in the
accompanying drawings should be interpreted as illustrative and not in a
limiting sense. The following claims are intended to cover all generic
and specific features described herein, as well as all statements of the
scope of the present method, system and structure, which, as a matter of
language, might be said to fall there between.