Silicon technology demonstrator projects were fundamental in enabling the development of the Low Power Methodology Manual.

After leading their teams' collaboration to create ARM's first synthesizable ARM7 and ARM9 cores, Mike Keating and Dave Flynn both felt that they needed to use their own products as their customers do in order to understand how to make these products better. So, they developed a test chip that combined ARM and Synopsys IP and took it through a Synopsys tool flow to silicon. The experience was incredibly illuminating, and it contributed to improving the IP and tools from both companies. In this and subsequent collaborative projects, the teams found that there is no substitute for direct first-hand experience doing low-power IP-based designs.

They quickly realized that managing power was one of the key concerns of their customers, and SoC designers in general, so they followed the initial project with several low power technology demonstration projects.

DVS926 and ULTRA926 -- 60% Energy Savings

DVS926

ULTRA926

These projects focused on the managing dynamic power, especially through clock gating, dynamic voltage and frequency scaling (DVFS), and the use of ARM's Intelligent Energy Manager (IEM) technology. Running a Linux OS, the SoC is a complete system combining an ARM CPU and Synopsys DesignWare® IP, implemented through a Synopsys tool flow. By running the system only as fast as required for a given task, the IEM software and on-chip controller is able to lower the chip voltage, thus saving energy (power over time) proportional the square of the voltage change. Running real application software, these ICs demonstrated up to 60% energy savings and led directly to enhancements in the companies' IP, tools and reference methodologies.

The teams' most recent collaborative technology demonstrator resulted from the SALT (Synopsys ARM Low power Technology) project, for which they received working silicon late 2006. This project extended the previous dynamic power SoC to address static (leakage) power as well, critical for designs at 90nm and below. Techniques added in this SoC implementation include coarse-grain MTCMOS power gating, state retention power gating (SRPG), hibernation, back- and forward-biasing, and multi threshold optimization.

SALT Demonstrator System Board

Through this project, the teams were able to demonstrate numerous leakage mitigation design techniques, for example, managing in-rush current when waking up design blocks, and also directly measure the impact of each of these techniques. The SRPG implementation on the CPU was shown to save up 25x the leakage power compared to normal operating mode; and, like the dynamic power SoC projects, the SALT project led directly to enhancements in the companies' IP, tools and reference methodologies.