As Internet technology becomes more pervasive, homes are getting connected to cable or DSL. The increasing user demands for "always on" service along with multiple connectivity for voice and data is gradually making the presence of a residential gateway in every household a reality. A residential gateway should have routing and bridging capabilities along with seamless connectivity to contemporary...
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This paper describes the design and implementation of a spread spectrum based miniaturized communication system for an integrated sensor microsystem, to be implemented as part of a system-on-chip device. One of the most important tasks in such a system is to convey information reliably on a multiple access based environment. In addition to the minimization of interferences, the devices have strict...
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A MEMS (micro electro-mechanical system) resonator oscillator is presented in this paper. It is based on a transimpedance amplifier (current to voltage converter) with a voltage controllable gain. The complete architecture of the oscillator is designed to control the oscillation amplitudes. The novelty of this paper is the use of an MRC (MOS resistive circuit) as active element to control the gain...
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System-on-chip (SoC) architectures integrate several heterogeneous components onto a single chip. These components provide various capabilities such as dynamic voltage scaling, reconfiguration, multiple power states, etc., that can be exploited for performance optimization during application design. We propose a generic model (GenM) which captures the capabilities of a large class of SoC architect...
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SoC designs today comprise IP blocks from different design teams and vendors. Because of differing design styles being used on IPs, integrating them and verifying them is a challenge for design teams. One of the problems that we have found while integrating is the way reset or initialisation circuitry is implemented. Lack of knowledge of IPs often cause problems late in the design flow when we per...
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A successful industrial product has a lifespan of 20 or more years. Off-the-shelf ICs and ASICs both rely on fabrication processes which are obsolete far sooner. The modern ASIC design process offers excellent portability along with HDL (hardware description language) device descriptions and test benches. Older designs, typically captured as gates in schematics and validation files in proprietary ...
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An effective soft module floorplanning algorithm is proposed. It uses simulated annealing framework based on the sequence pair representation. Because a soft module may have many possible shapes, so it will take long time to find a good solution in simulated annealing method. We proposed a method which finds four candidates of module shape to be chosen in a simulated annealing process for each mod...
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In this paper, we present a methodology to perform a very fast system-level design space exploration of parameterized multimedia architectures. The methodology is applied to a functional model of a wireless multimedia platform developed by Accent. Our approach guarantees the correctness of the dataflow and finds pareto-optimal solutions by considering area, performances and power consumption. The ...
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This paper presents a novel HW/SW verification methodology called virtual in-circuit emulation, that is suitable for a platform-based design paradigm, where the main objective of co-verification is to validate the interaction between an existing core processor and some application-specific peripheral system. The proposed co-verification solution shares with conventional emulation schemes the possi...
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This paper addresses the problem of comparing the performance and the area and power consumption of integrated circuits built in different technologies. In the literature there are several methods described but these do not sufficiently take the velocity saturation into account. They either ignore velocity saturation or assume the device is always in velocity saturation. The approach presented in ...
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This paper presents an overall analysis of the redundancy in the information (addresses, instructions, and data) stored and exchanged between the processor and the memory system and evaluates the potential of compression in improving performance, power consumption, and cost of the memory system. Analysis of traces obtained with Sun Microsystems' Shade simulator simulating SPARC executables of nine...
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The impact of MPEG-4 video coding algorithms and their parameters on total energy (communication plus computation) is investigated. Specifically, the effect of the quantization parameter, number of B-frames, error-resilience techniques, content-based coding, and spatial and temporal scalability options are studied. Based on the simulation results, recommendations are made for the choice of these a...
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As technology scales down into deep-submicron, leakage energy is becoming a dominant source of energy consumption. Leakage energy is generally proportional to the area of a circuit, and caches constitute a large portion of the processor die area. Therefore, there has been much effort to reduce leakage energy in caches. Most techniques have been targeted at cell leakage energy optimization. Bitline...
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We present here a new paradigm based on a centralized architecture to realize electronic artificial retina. This original architecture, named connectionist retina, can execute in real time RBF (radial basis function) and MLP (multilayer perceptron) neural network applications. We demonstrate that this intelligent embedded system could be used for vision applications. We describe the realized proto...
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Microprocessor power dissipation is a growing concern, so much so that it threatens to limit future performance improvements. A major consumer of microprocessor power is the issue queue. Many microprocessors, such as the Compaq Alpha 21264 and IBM POWER4™, use a compacting latch-based issue queue design which has the advantage of simplicity of design and verification. The disadvan...
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This paper presents a novel high-bandwidth digital accelerator for image and graphics processing applications. The proposed architecture outperforms previously proposed processing-in-memory architectures in speed, area and power by up to several orders of magnitude. Several variations of the design have been implemented in 2.5 V 0.25 μm and 1.8 V 0.18 μm CMOS technology.
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Multimedia systems, such as interactive broadcast and satellite radios, have increasingly been demanding higher performance CPUs and higher performance DSPs to process the received data in real-time. In many cases, the performance of a general-purpose processor is not adequate, and this creates a demand for a system-on-chip device that processes the multimedia tasks efficiently and independently. ...
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Low power optimizations have become an integral part of designing computing systems. One important part of low power design is accurate and efficient power estimation during the design phase in order to meet the power specifications without a costly redesign process. Power estimation refers to the process of determining, with a high level of confidence, the power consumed by a circuit/component. A...
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In this paper, a novel VLSI architecture of an Ogg Vorbis decoder is proposed, dedicated for embedded applications. Aimed at the use of the decoder in portable audio appliances, first, the computational cost in a series of decoding processes is analyzed. As a result, the LSP (line spectrum pair) process is detected as a bottleneck to achieving realtime decoding by an embedded processor. Thus, the ...
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A new approach for power modeling of transversal filters based on a physically oriented design is presented. The approach is based on algebraic models fitted by correction functions which are determined from the distribution of the simulated, actual switching activity within filter macros. With these functions, even the dependency of the power models on input switching activities and statistical d...
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Blind source separation (BSS) of independent sources from their convolutive mixtures is a problem in many real-world multi-sensor applications. In this paper, we propose a new low-cost design and implementation of an improved BSS algorithm for audio signals based on ICA (Independent Component Analysis) technique. It is performed by implementing non-causal filters instead of causal filters within t...
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This article presents a power management scheme for a new circuit concept - the autonomous error-tolerant (AET) cell - the inner functionality, interconnectivity and reconfiguration of which have been presented earlier. In order to meet reliability and energy efficiency objectives, a special power management strategy and implementation of this strategy are proposed. The power management system con...
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