A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the...http://www.google.com/patents/US7751228?utm_source=gb-gplus-sharePatent US7751228 - Dielectric relaxation memory

A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the invention to be used as a memory device. A method of forming the trap cites involves an atomic layer deposition of a material at pre-determined areas in the dielectric layer.

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Claims(30)

1. A memory device comprising:

first and second electrodes;

a dielectric layer coupled between the first and second electrodes, wherein the dielectric layer includes a plurality of charge trap sites; and

an access device configured to read a first current and a second current based on respective first and second voltages applied between the first and second electrodes;

wherein the first and second currents are based on respective amounts of trapped charge in the plurality of charge trap sites when the respective first and second voltages are applied; and

wherein a difference between the first and second currents represents a logical state of the memory device.

2. The memory device of claim 1, wherein at least one of the first or second electrodes comprises doped polysilicon.

3. The memory device of claim 1, wherein at least one of the first or second electrodes comprises titanium nitride.

4. The memory device of claim 1, wherein at least one of the first or second electrodes comprises platinum.

5. The memory device of claim 1, wherein at least one of the first or second electrodes comprises palladium.

6. The memory device of claim 1, wherein at least one of the first or second electrodes comprises rhodium.

7. The memory device of claim 1, wherein at least one of the first or second electrodes comprises Pt—Rh.

8. The memory device of claim 1, wherein at least one of the first or second electrodes comprises ruthenium.

9. The memory device of claim 1, wherein at least one of the first or second electrodes comprises TuOx.

10. The memory device of claim 1, wherein at least one of the first or second electrodes comprises iridium.

11. The memory device of claim 1, wherein at least one of the first or second electrodes comprises IrOx.

12. The memory device of claim 1, wherein at least one of the first or second electrodes comprises of tantalum nitride.

13. The memory device of claim 1, wherein a first material of the dielectric layer comprises at least one of aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon dioxide or nitride.

14. The memory device of claim 13, wherein the dielectric layer further comprises a second material including hafnium oxide or tantalum oxide.

15. The memory device of claim 1, wherein the dielectric layer has a plurality of charge trap sites corresponding to one energy state.

16. The memory device of claim 1, wherein the dielectric layer has a plurality of charge trap sites corresponding to different respective energy states.

17. The memory device of claim 1, wherein the dielectric layer comprises first and second dielectric layers and has a trap site layer that is located between the first and second dielectric layers.

18. The memory device of claim 1, comprising a circuit for controlling reading out the difference between the first and second currents representing a logical state of the memory device.

19. The memory device of claim 1, wherein the plurality of charge trap sites includes at least one trap site formed from a dopant including at least one of hafnium, tantalum, zirconium, or aluminum.

20. A memory device comprising:

first and second electrodes;

a dielectric layer coupled between the first and second electrodes, wherein the dielectric layer includes a plurality of charge trap sites; and

an access device configured to read a first accumulated charge and a second accumulated charge based on respective first and second voltages applied between the first and second electrodes;

wherein the first and second accumulated charges are based on respective amounts of trapped charge in the plurality of charge trap sites when the respective first and second voltages are applied; and

wherein a difference between the first and second accumulated charges represents a logical state of the memory device.

21. The memory device of claim 20, wherein at least one of the first or second electrodes comprises at least one of doped polysilicon, titanium nitride, platinum, palladium, rhodium, Pt—Rh, ruthenium, TuOx, iridium, IrOx, or tantalum nitride.

22. The memory device of claim 20, wherein a first material of the dielectric layer comprises at least one of aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon dioxide or nitride.

23. The memory device of claim 22, wherein the dielectric layer further comprises a second material including hafnium oxide or tantalum oxide.

24. The memory device of claim 20, wherein the dielectric layer has a plurality of charge trap sites corresponding to one energy state.

25. The memory device of claim 20, wherein the dielectric layer has a plurality of charge trap sites corresponding to different respective energy states.

26. The memory device of claim 20, wherein the dielectric layer comprises first and second dielectric layers and has a trap site layer that is located between the first and second dielectric layers.

27. The memory device of claim 20, comprising a circuit for controlling reading out the difference between the first and second accumulated charges representing a logical state of the memory device.

28. The memory device of claim 20, wherein the plurality of charge trap sites includes at least one trap site formed from a dopant including at least one of hafnium, tantalum, zirconium, or aluminum.

29. A processor system comprising:

a processing unit for digital logic processing;

a memory device comprising:

a dielectric layer coupled between the first and second electrodes, wherein the dielectric layer includes a plurality of charge trap sites; and

an access device configured to read a first current and a second current based on respective first and second voltages applied between the first and second electrodes;

wherein the first and second currents are based on respective amounts of trapped charge in the plurality of charge trap sites when the respective first and second voltages are applied; and

a memory controller for controlling communication of the data stored by the memory device between the processing unit and the memory device; and

a controller circuit for controlling reading out the difference between the first and second currents representing a logical state of the memory device.

30. A processor system comprising:

a processing unit for digital logic processing;

a memory device comprising:

a dielectric layer coupled between the first and second electrodes, wherein the dielectric layer includes a plurality of charge trap sites; and

an access device configured to read a first accumulated charge and a second accumulated charge based on respective first and second voltages applied between the first and second electrodes;

wherein the first and second accumulated charges are based on respective amounts of trapped charge in the plurality of charge trap sites when the respective first and second voltages are applied; and

a memory controller for controlling communication of the data stored by the memory device between the processing unit and the memory device; and

a controller circuit for controlling reading out the difference between the first and second accumulated charges representing a logical state of the memory device.

Description

This application is a continuation of application Ser. No. 11/389,150, filed on Mar. 27, 2006 now U.S. Pat. No. 7,457,184, which is a divisional of application Ser. No. 10/930,774, filed on Sep. 1, 2004 now U.S. Pat. No. 7,388,248, both of which are incorporated herein by reference in their entireties. This application is related to co-pending application Ser. No. 11/389,149 filed Mar. 27, 2006, which is incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

The present invention relates to the field of memory devices, and in particular to a memory device that utilizes dielectric relaxation.

BACKGROUND OF THE INVENTION

A memory cell in an integrated circuit, such as a dynamic random access memory (DRAM) array, typically comprises a charge storage capacitor (or cell capacitor) coupled to an access device such as a metal oxide semiconductor field effect transistor (MOSFET). The MOSFET functions to apply or remove charge on the capacitor, thus effecting a logical state defined by the stored charge. The amount of charge stored on the capacitor is proportional to the capacitance C, defined by C=kk0A/d, where k is the dielectric constant of the capacitor dielectric, k0 is the vacuum permittivity, A is the electrode surface area and d is the distance between electrodes.

FIG. 1 illustrates a portion of a conventional DRAM memory circuit containing two neighboring DRAM cells 10. For each cell, one side of the storage capacitor 14 is connected to a reference voltage Vr, which is typically one half of the internal operating voltage (the voltage typically corresponding to a logical “1” value) of the circuit. The other side of the storage capacitor 14 is connected to the drain of an access field effect transistor 12. The gate of the access field effect transistor 12 is connected to a word line 18. The source of the field effect transistor 12 is connected to a bit line 16. With the cell 10 connected in this manner, it is apparent that the word line 18 controls access to the storage capacitor 14 by allowing or preventing a signal (corresponding to a logic “0” or a logic “1”) on the bit line 16 to be written to or read from the storage capacitor 14 only when a signal from the word line 18 is applied to a gate of the access transistor 12.

Capacitors, like the capacitors 14 shown in FIG. 1, suffer from current loss in two ways: (1) direct current leakage loss, which results in high power consumption, and (2) dielectric relaxation. Direct current leakage loss accounts for charge transport from one electrode to another across the dielectric. Direct current leakage also creates the need for a DRAM cell to be refreshed at frequent periods, as charge stored in the capacitor leaks to adjacent active areas on the memory cell. Dielectric relaxation, on the other hand, is a phenomenon that refers to a residual polarization within a dielectric material of a memory storage device when a voltage is applied to the device. Dielectric relaxation, which can be described mathematically in accordance with the Curie-von Schweidler behavior formula, is time-dependent. At least in ideal operation, however, dielectric relaxation is independent of the electrode material, dielectric thickness, and any direct leakage current from the dielectric layer. More significantly, dielectric relaxation is dependent on the type of dielectric materials used and becomes increasingly worse for high-k dielectric materials, which for other reasons are increasingly favored in integrated circuit fabrication.

FIG. 2A is an illustrative graph of current stored in a capacitor versus time for a capacitor 14 (FIG. 1). As shown in FIG. 2A, a capacitor that suffers only from direct current leakage, has a nearly horizontal slope (line 5) on this graph, meaning that the direct current loss is not dependent on time. As shown by line 1, however, when dielectric relaxation losses are realized, the slope of the line 1 changes significantly, and thus, the current loss from dielectric relaxation is dependent on time. Each of the dotted sloped lines 2-4 show possible relaxation leakage from a capacitor, which may change based on other factors such as the temperature and the applied voltage.

The current losses from dielectric relaxation are undesirable for many reasons. In DRAM devices, for example, dielectric relaxation can affect the effectiveness of some dielectrics, such as high-k dielectrics, used in the DRAM storage capacitors. In addition, dielectric relaxation can create a threshold shift that severely deteriorates MOSFET performance.

There is a need, therefore, for a memory cell capacitor structure that does not suffer from the undesirable effects of dielectric relaxation but rather can use this phenomenon in a beneficial manner. Accordingly, there is also needed a simple method of producing and operating the desired capacitor structure.

BRIEF SUMMARY OF THE INVENTION

The present invention provides a capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. Energy states may be used to distinguish logical states for the capacitor structure, allowing the invention to be used as a memory device. A method of forming the trap sites involves an atomic layer deposition of a material at pre-determined areas in the capacitor's dielectric layer.

In accordance with an exemplary method of operating the capacitor structure as a memory device, a write voltage is pulsed across the electrodes to fill some or all of the trap sites. The device may be subsequently read using a read voltage applied at the electrodes which senses the filled trap sites as a logical value. In addition, the refresh time may be tuned as desired by adjusting the density and energy state of the trap centers based on the selection of materials.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other advantages and features of the invention will become more apparent from the detailed description of exemplary embodiments provided below with reference to the accompanying drawings in which:

FIG. 1 is a circuit diagram of a portion of a conventional DRAM memory circuit;

FIG. 2A is a graph of current versus time for a conventional capacitor;

FIG. 2B is a model of a double potential well depicting dielectric relaxation;

FIG. 2C is an equivalence circuit depicting dielectric relaxation;

FIG. 3A is a cross sectional view of a portion of a capacitor formed in accordance with a first exemplary embodiment of the present invention;

FIG. 3B is a cross sectional view of a portion of a capacitor formed in accordance with a second exemplary embodiment of the present invention;

FIG. 4 is a diagram of a sequence of steps for operating a memory device employing an exemplary capacitor in accordance with the present invention; and

FIG. 5 illustrates a block diagram of a computer system having a memory element in accordance with the invention; and

FIG. 6 is a circuit diagram of a portion of a DRAM memory circuit employing an exemplary capacitor in accordance with the present invention.

DETAILED DESCRIPTION OF THE INVENTION

In the following description, reference is made to the accompanying drawings which will serve to illustrate the preferred embodiments of the invention. These embodiments provide sufficient detail to enable those skilled in the art to practice the invention. Of course other embodiments may be used and various changes may be made without departing from the scope of the present invention. The scope of this invention is defined by the appended claims.

FIG. 2B depicts a double potential well, shown as energy versus space, that models the behavior of a charge (e−) within a medium when an electric field (from an applied voltage source) is present. When an electric field is applied, the charge (e−) will hop from the left well to the right well, thereby changing its energy state. This change in state causes, in turn, a dipole moment creating a current pulse in the medium. Similarly, when the electric field is removed, the charge (e−) will eventually move back to its starting point in the left well. This produces a depolarization current having the same magnitude but opposite direction as that just discussed. The present invention utilizes the effect of the double well scenario by controlling the energy states of charges that are found in a dielectric material such that dielectric relaxation is not a problem but instead a tool for sensing the logical state of a memory device. Specifically, additional potential wells are created by applying an increased voltage into a dielectric having a higher k− material doped region. The additional wells contribute to the relaxation currents experienced in the dielectric medium, which is then sensed as a change in logical state.

FIG. 2C shows a circuit that depicts the current losses attributable to the dielectric relaxation phenomenon, as described in “A Comparative Study of Dielectric Relaxation Losses in Alternative Dielectrics,” Reisinger et al., IEEE (2000). As shown in the figure, an ideal capacitor circuit without suffering dielectric relaxation, has a capacitor with capacitance CHF and a resistor with resistance RLeak. When dielectric relaxation is considered, a series of RC shunts (R1C1 . . . RNCN) are created, each with a respective time constant of current decay. In the present invention, and as described in more detail below, high-k dielectric regions (e.g., 104 in FIG. 3A) are formed in a capacitor region. These regions create additional energy state wells (See FIG. 2B) and will be components of the RC circuit model shown in FIG. 2C. Thus, for a capacitor (e.g., 100 in FIG. 3A), the time dependence of the decaying currents will change when the additional energy wells are filled, which in turn, provides a change in current reading, thereby creating a memory effect.

Capacitors 100, 100′ formed in accordance with exemplary embodiments of the present invention are shown in cross-sectional view in FIGS. 3A and 3B. It should be understood that the portions shown are illustrative of an embodiment of the invention, and that the invention encompasses other devices that can be formed using different materials and processes than those described herein. Further, although reference is made to capacitor 100 being utilized in a DRAM memory circuit, the invention is similarly applicable to other types of memory devices that utilize capacitors as storage elements, and the invention is not limited to DRAM memory devices.

In accordance with a first exemplary embodiment of the invention, with reference to FIG. 3A, a layer of conductive material is formed, which serves as a bottom electrode 102A. The electrode 102A may be formed of any electrically conductive material, including, but not limited to, doped polysilicon and titanium nitride. Other possible materials for the electrodes 102A, 102B are Pt, Pd, Rh, Pt—Rh, Ru, TuOx, Ir, IrOx, and TaN.

Next, a layer 101 of dielectric material is formed over the bottom electrode 102A. The dielectric material for layer 101 may be, e.g., aluminum oxide, titanium oxide, hafnium oxide, zirconium oxide, or a nitride. Next, a top electrode layer 102B is formed above the dielectric layer 101, and may be formed of any conductive material. Trap sites 104 are then introduced into the dielectric layer 101. This introduction is preferably done by an atomic layer deposition at interstitial sites in the dielectric layer 101. For example, if the dielectric layer 101 is aluminum oxide, it may be doped at predetermined positions with hafnium, tantalum oxide or hafnium oxide to form charge trap sites 104 within the dielectric matrix 101. High-k materials such as (Ba)TiO3, SrTiO3, PbTiO3, and PbO3 make good trap sites 104, as these materials are known to have significant dielectric relaxation. Potential dopants for creating the trap sites 104 include Hf, Ta, Zr, and Al, which eventually form oxides creating the trap sites 104.

FIG. 3B shows a second exemplary embodiment of a capacitor 100′ constructed in accordance with the invention. The only difference between the first and second exemplary embodiments is the location of the trap sites 104 (FIG. 3A), 104′. In the second exemplary embodiment, the trap site 104′ is a layer of material sandwiched within the dielectric layer 101′. Specifically, during formation, a thin dielectric layer 101″ is formed on the bottom electrode 102A. Next, a thin layer 104′ of doping material, such as hafnium oxide or tantalum oxide, or some other high-k dielectric material is formed on the thin dielectric layer 101′. Next, a second thin dielectric layer 101″ is formed over the trap site layer 104′.

It should be understood that these two embodiments are only exemplary, and that other capacitor structures, like capacitors 100, 100′ are within the scope of the invention, and that trap sites 104, 104′ may be formed as desired. The remaining disclosure applies equally to each exemplary embodiment, and is made with reference to capacitor 100 solely for simplicity purposes.

It is within the scope of the invention that the capacitor 100 may be formed in any known configuration, such as a trench capacitor, a vertical capacitor, a container capacitor, or other capacitor configurations. It should also be understood that the capacitor 100 may be implemented in a memory device, such as in memory cell 10 as shown in FIG. 1. For exemplary purposes only, operation of the capacitor 100 is now described with reference to the memory cell 10 of FIG. 6, replacing the conventional capacitor 14 with the exemplary capacitor 100. As described above with reference to FIG. 1, to write data into the capacitor 100, a voltage from bit line 16 must travel through an access device, such as access transistor 12 to the capacitor 100. Similarly, to readout a charge from the capacitor 100, an appropriate signal is applied from the word line 18 to activate the access transistor 12 such that a charge from the capacitor 100 may be read out to the bit line 16.

With reference to FIGS. 4 and 2A, an exemplary method 200 of operating the capacitor 100 as a memory device is now described. At a time t0, an initial voltage V0 is applied to the capacitor 100, t0 represents the time at which this initial event in the method occurs. Using an appropriate read voltage, a current I0 is read out from the capacitor 100 at step 201, at a time t′ (FIG. 2A). I0 corresponds to the current output during readout at time t′, and in this instance, corresponds to a logical “0” value. t′ is a pre-determined time after the application of the initial voltage for performing this read cycle, which is selected based on optimizing the output current signal. With reference to FIG. 2A, the current I0 will be different for each of the sloped lines, but represents the value of the y-axis on the graph at time t′. As an alternative to reading out the current at a given time (i.e., I0), the total accumulated charge can be readout from the capacitor 100. In this instance, the readout is an amplified signal, which is graphically represented as the area under the curve, for each curve at time t′.

Next, at step 202, a write voltage VS, larger than the initial voltage V0 is applied to the capacitor dielectric 101 through one of the electrodes 102A. This higher voltage should cause some or all of the trap sites 104 to fill with charge. With reference to FIG. 2B, this corresponds to the charges “hopping” into a second energy well, and with reference to FIG. 2A, this effect in turn causes the capacitor discharge to follow a different sloped discharge profile line. As should be understood, following a different line will make the next current readout, assuming it occurs at time t′, to be different than the initial current readout. Therefore, the write voltage VS must be large enough to change the memory state of the cell. After the pulsed higher voltage VS is removed, the bias on the dielectric 101 is then returned to zero voltage. Subsequently, a second current readout is taken, at step 203, by applying an associated read voltage. Again, this may be a readout of the current I at time t′, or it can be the total accumulated charge.

The second current, IS, should be different than the pre-stress current I0 depending on the trapped charge, meaning the amount of charges in higher energy states. Accordingly, for any given bias condition, the field across the dielectric 101 will be lower or higher depending on the amount of trapped charge. This difference will determine the logical “1” state. Depending on the density and energy state of the trap sites 104, the trapped charge will dissipate during discharge, or return to its original condition, within a given time (e.g., 1 second). Thus, the capacitor 100 needs to be refreshed, at step 204, with application of VS to the dielectric 101 in order to restore the logical “1” state. The capacitor 100 of the current invention may be tailored to hold a logical “1” state for as long as a flash memory or as short as a DRAM cell.

The amount of applied voltage that is necessary to charge the trap sites 104 at step 202 depends on the energy level of the trap site 104 (which is the barrier height of the second well in FIG. 2B), which is, in turn, dependent on the materials used to form the sites 104 and the dielectric layer 101. Thus, an appropriate level for a write voltage V, should be chosen based on the materials of the capacitor 100 and the temperature during operation (which is also known to affect the relaxation).

FIG. 5 is a block diagram of a processor system 1200, which includes a memory circuit 1248, for example a DRAM circuit employing a capacitor 100 constructed in accordance with the invention. The processor system 1200, such as a computer system, generally comprises a central processing unit (CPU) 1244, such as a microprocessor, a digital signal processor, or other programmable digital logic devices, which communicates with an input/output (I/O) device 1246 over a bus 1252. The memory 1248 communicates with the system components over bus 1252 typically through a memory controller.

In the case of a computer system, the system 1200 may include peripheral devices such as a floppy disk drive 1254 and a compact disc (CD) ROM drive 1256, which also communicate with CPU 1244 over the bus 1252. Memory 1248 is preferably constructed as an integrated circuit, which includes one or more of the inventive capacitors 100. If desired, the memory 1248 may be combined with the processor, for example CPU 1244, in a single integrated circuit.

The above description and drawings are only to be considered illustrative of exemplary embodiments which achieve the features and advantages of the invention. Modification of, and substitutions to, specific process conditions and structures can be made without departing from the spirit and scope of the invention. Accordingly, the invention is not to be considered as being limited by the foregoing description and drawings, but is only limited by the scope of the appended claims.