ECTC: Focus on 3D integration and TSVs

A main focus of this year’s Electronic Components and Technology Conference (ECTC), held this week in San Diego, is 3D integration and through silicon vias (TSVs). “The biggest trend for the last couple of years has been 3D and TSV and it continues to be that way,” said David McCann of GLOBALFOUNDRIES and ECTC conference chair. This year, the conference features a set of sessions specifically on 3D TSVs, with minimal overlap. There’s also an additional session specifically on interposers, otherwise known as 2.5D. “The industry really wants to see 2.5D happen as an easier way to do 3D before all the 3D tools are in place,” McCann said. “The struggle is over how much is an interposer going to cost.”

Presently, that struggle appears to be between glass and silicon, where glass is a less expensive alternative. “Glass would be a cheaper approach to silicon interposers, but is limited to line space and via diameter,” McCann said. “Glass is not able to get as dense as silicon.” He said there may be a bifurcated market on interposers, where the high end is on silicon, and the low end is on glass. High end applications are devices such as microprocessors, which need high density, 1 micron lines and spaces. Low end devices are capabilities such as RF.

In terms of when TSVs will move into volume production for mainstream applications, McCann said that RF devices that already have TSVs because they have backside contact. Next, memory devices are in line to for TSV production. “I think there will be more and more memory stacks,” he said. Fabricating a memory stack internally for a memory company is easy (at least compared to alternative approaches) in that it doesn’t require an outside standard to be able to do the connection between the devices. “Next will be wide I/O or whatever wide I/O morphs into, maybe wide I/O2, where you get an apps processor with a wide I/O DRAM on top of it,” McCann said. “I think we’ll see those starting in 2013, first products in the industry and 2014 for adoption into 20nm. And then, following that, it’s very dependent upon standards. Wide I/O standard is critical for getting multiple memory suppliers to supply memory or a consuming company to use multiple suppliers,” he said. “Standards are going to enable products and those first 3D products are going to use devices that already exist and put TSVs into them.”

The real potential of 3D integration will come around 2017 or 2018, McCann believe, when heterogeneous stacks with different devices with different functions, such as memory, digital, analog , RF and power, are integrated in a stack. “There will be design tools that optimize the design of those devices for placement of blocks, TSVs and bumps for optimal performance. In the first products, we won’t have so much optimization, but more enablement, and then where we all really want to get to is that optimization of performance, “ McCann said. “What that will look like is say a bit of memory just above a processing cell, right where you want it. Or the analog the right where you want it to be placed with this very short vertical interconnect to the circuitry that it needs to communicate with. We’ll get to optimal block placement when the tools start getting available to help us co-design devices from different manufacturers for optimal performance.”

McCann acknowledged that testing these complex 3D stacks will be a major challenge, saying is revolves very much around IP. “If you think about DRAM and how it’s tested, it’s all internal to the DRAM company and it’s very tightly protected IP. Nobody wants to let that outside, understandably. Then you start thinking about 2.5D and 3D where you’ve got integrated memory – how do you do that? The assembly of those is not going to be at the memory manufacturer,” he said.

McCann believe stacked memory will evolve in two stages. The first stage will be it will be shipped as a completed component so that the memory company can continue to adhere to the business model of shipping a completed, tested, repaired device — a know good die.” That small stack will be placed on an apps processor for 3D, or on an interposer for 2.5D,” he said. The second part of it is what IP is needed for both the microprocessor and the memory to enable test. “We’ll start seeing test IP blocks from the foundries and the memory companies to enable test by using the processor to test the memory . I think we’re still exploring what that looks like. I can’t tell you what that’s going to end up looking like, but it’s clear that we’ve got to enable that together to enable the products,” McCann said.

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