What About DC Power Integrity? Part 2

Reference designs from chip makers serve as a starting point. However, you should establish your own power budget based on how you intend your product is to be used.

PCB power budgeting
In my previous blog on DC power integrity, I touched on some of the symptoms that can point toward power integrity problems in a PCB design. A great question to think about would be: "What is a good starting point for designing with power integrity in mind?"

There are well-established best-practices for designing with power in mind, but I still see quite a lot of designs where the PCB's power distribution is basically copied from a chip manufacturer's reference design. Often, this is done without a lot of concern for the customized nature of the product itself. Some of the difficulties and considerations with this approach are as follows.

When you're under the gun to finish a design, it's awfully tempting simply to copy the power supply from reference design material. This places a large -- and sometimes unwarranted -- amount of trust in the applications engineer who created the reference design. (In a sense, this is flattering, but it's also a bit naive.)

Your use of the product is never going to be exactly the same as the reference design. Reference design boards tend to be large, simple designs intended to show how to use a device. Your design will most likely include the device of interest along with myriad other systems vying for power. Your board, more likely than not, will be much more constrained for size and layer count than the reference design was.

Reference designs from chip makers serve as a decent starting point. However, the wise thing to do is establish your own power budget based on how you intend your product to be used.

Finding the current draw
First, you can find the worst-case (or maximum) current draw required. If you create your design based on this information, the product almost certainly will be very robust from a DC power point of view. However, the extra copper and space required may make it too large and costly. Many would consider this the over-engineered approach.

Once the worst-case power needs have been established, you can consider the use case of the parts in the design to figure out a more optimized solution. Luckily, good component manufacturers with high-quality data sheets provide the extra information needed to estimate this, but a few tricks and even some tools allow you to get a clearer view of the nominal and peak current requirements. Also, tradeoffs can be made here. Running the CPU at half the clock speed, for example, can halve its power consumption.

Just for fun, let's compare the power consumption requirements for two roughly equivalent ARM-Cortex M4 processors: the TM4C129XNCZAD from TI/Stellaris and the STM32F429xx from ST Micro. One thing they have in common is that the LDO regulator for the 1.2V core logic supply is included on the chip; the only thing needed is external bypassing capacitors.

TM4C129XNCZAD current consumption
The TI/Stellaris CPU data sheet provides the information I need starting on page 2,173. (Caw! They don't make 'em small these days.) What's nice here is that you can see the nominal and maximum current draw of the CPU with all the peripherals active, both at full clock speed (120 MHz) and at low speed (16 MHz), and with code executing from internal Flash and the high-speed SRAM.

Initially, I'm really just interested in the worst-case (or maximum) current consumption. In the TI data sheet, this specification is given as IDD_RUN in Flash loop execution. Table 32-74 shows it as 113 mA max. Perhaps a little surprisingly, the relationship between system clock and current consumption appears to be nonlinear, with only a 2.6x increase in current corresponding to a 7.5x increase in clock frequency. Most likely, this is because only the core CPU and memory are actually running at the full speed.

Now, 113 mA is not too bad for a fast microcontroller, but there's a gotcha. This table really specifies only the consumption of the core and peripheral functions. If you are running lots of general-purpose input/outputs (GPIOs) at the Fast GPIO Pad recommended conditions (up to 12 mA drive per pad with a 40% switching rate), you need to consider the additional current needed to drive the I/Os.

This is specified on pages 2,104 and 2,105 of the data sheet, where the recommended operating conditions for GPIOs are called out. Here you can see a cumulative maximum current recommendation for 88-116 mA per side of the die. So peak operating I/O current could be as high as ≈550 mA. In addition, I note that, on page 2,115, Table 32-15 shows an inrush current of the internal VDDCORE LDO regulator of 250 mA maximum. This could mean a peak power-up current draw of 250 mA, followed by increased draw once the code begins execution and starts banging away at the GPIOs.

@zeeglen: Once - and only once - I proposed similar. The software people were like to have me strung up, drawn, and quartered for even THINKING such a heretical notion.

I recall a computer in the UK -- you could purchase one with a certain amount of computing power for a certain price -- when your company needed more computing power, you could pay for an upgrade.

The technician would come round and pull out your mother board and plug in a new "super duper" motherboard with "twice the computing power" -- once back in his van, he would take your old board and swap the jumper from 1X clock to 2X clock, then that was the "new" board he would take into the next company...

This is a great post that should bring awareness to the board designers. I'd like to supplement the article content by proposing that simulations of the PDN (Power Distribution Network) be done prior to board fab (and during layout) to ensure that there's enough copper in the plane (or thick traces) that need to accomodate high current switching activities. In today's board design (specifically in the pwr/gnd plane structures) the designer needs to be aware that the pwr/gnd planes can be fragmented due to pin breakouts, via structures, narrow areas, etc... As such, the full current-carrying effects of the planes cannot be realized. There could be narrow areas (or neck-down) sections of the plane that must carry the required currents from the regulator to the destination devices. These types of areas are the bottlenecks in the plane structures and can cause significant (and dynamic) voltage drops when there are high current switching activities from the device power pins connecting to the rail (or GND return paths). The current will take the path of least resistance (ie. shortest path) to/from the voltage regulator so if these areas are not analyzed correctly there can be areas of high concentration of current density (mA/mil square) that potentially can heat up the traces causing breakdowns over time. The idea is to have sufficient copper pours to minimize the DC drop (or loss) voltage. The best way to fix the problem is to avoid it in the first place before the board is fabbed and components are stuffed. The bench used to be my favorite place to spend time but nowadays I spend more time in simulations than sitting on the bench measuring things. Simulations can identify issues before the board is fabbed... Now where would you rather spend time (and money)?