Patch

diff --git a/Documentation/DMA-attributes.txt b/Documentation/DMA-attributes.txtindex b768cc0..811a5d4 100644--- a/Documentation/DMA-attributes.txt+++ b/Documentation/DMA-attributes.txt@@ -31,3 +31,13 @@ may be weakly ordered, that is that reads and writes may pass each other.
Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING,
those that do not will simply ignore the attribute and exhibit default
behavior.
++DMA_ATTR_WRITE_COMBINE+----------------------++DMA_ATTR_WRITE_COMBINE specifies that writes to the mapping may be+buffered to improve performance.++Since it is optional for platforms to implement DMA_ATTR_WRITE_COMBINE,+those that do not will simply ignore the attribute and exhibit default+behavior.diff --git a/include/linux/dma-attrs.h b/include/linux/dma-attrs.hindex 71ad34e..ada61e1 100644--- a/include/linux/dma-attrs.h+++ b/include/linux/dma-attrs.h@@ -13,6 +13,7 @@
enum dma_attr {
DMA_ATTR_WRITE_BARRIER,
DMA_ATTR_WEAK_ORDERING,
+ DMA_ATTR_WRITE_COMBINE,
DMA_ATTR_MAX,
};