Adapteva close to sampling 28-nm, 64-core coprocessor

LONDON – Adapteva Inc. (Lexington, Mass.), a small and lean fabless startup that has developed a series of multicore floating-point processors, claims its latest device, a 28-nm 64-core processor is close to sampling.

The Epiphany architecture is designed to operate as an accelerator for DSP tasks such as speech recognition and image processing. The company has started out in specialized applications such as military, engineering services and financial markets, but is now looking to move into mobile applications.

In addition, according to Andreas Olofsson, the company's founder and CEO, the 28-nm device is Adapteva's fourth chip and the company is close to breakeven on a quarterly basis, all on less than $2 million of investment. The company has used Globalfoundries Inc. (Milpitas, Calif.) as its foundry to produce the 28-nm chip which clocks at 800-MHz.

With mask sets costing millions of dollars how is that possible? The answer is simple – multiproject wafer (MPW) runs, which mean mask costs are divided amongst multiple foundry customers. Olofsson said that Adapteva has deliberately targeted low volume, high value applications where it can meet demand from a small part of the area of a few wafers but for which the company can charge up to $1,000 per chip.

The company has taken in $1 million in revenue since summer of 2011 when it was selling its 65-nm 16-core processor. "We're close to breaking even on a quarterly basis," said Olofsson.

The fourth generation of the Epiphany multicore architecture IP is a 28-nm design with 64 independent RISC cores, each with 32-kbytes of memory on an 8.2 square millimeter die, which the company claims offers the highest energy efficiency of any floating point processor to date, at 70 GFLOPS/watt.

Andreas is a design god. Epiphany is the stripped down Deuce Coupe whipping the the rich kid's Corvette.
The clock propagation scheme is particularly innovative.
Protein folding and synthetic biology guys will shower him with money.

The local memory is too small and there is no DMA or cache controller. All data movement has to programmed in the code.
Sorry, love underdogs, but a better architecture is needed to make the chip useful. Team up with one of the better researchers in the field of many core processors and improve the product.