• Support a MAC data rate of 100 gigabit per second
-Provide physical layer specifications which support 100 gigabit per second operation over following:
-at least 40km on SMF
-at least 10km on SMF
-at least 100m on OM3 MMF
-at least 7m over a copper cable assembly

100 Gigabit Ethernet Physical Layer | 100 gbps Ethernet PHY

The figure-1 depicts sublayers of 100 gigabit ethernet physical layer. As shown in the figure, physical layer
composed of sublayers which include Reconciliation sublayer, CGMII, PCS, FEC(forward error correction),
PMA, PMD, AN(auto-negotiation) and MDI. In this article we will go through PCS sublayer and
multirate distribution concept at transmit as well as receive end of 100 Gbps ethernet physical layer.
For functions of other sublayers refer
40 Gigabit Ethernet Physical Layer.

The MAC layer, which corresponds to Layer 2 of the OSI model, is connected to the
medium either using optical fiber or copper cable by an Ethernet PHY device.
This PHY device corresponds to Layer 1 of the OSI model.

FEC and AN sublayers depends on physical layer medium.

The transmit PCS, therefore, performs the initial 64B/66B encoding and scrambling on the aggregate
channel (at 100 gigabits per second) before distributing 66-bit block in a round robin basis across the
multiple lanes.

The figure-2 depicts multilane transmitter of 100 gbps ethernet PHY.
For 100 Gigabit Ethernet, 20 PCS lanes have been choosen.
The number of electrical or optical interface widths supportable in this architecture is
equivalent to no. of factors of the total PCS lanes.
Hence, 20 PCS lanes support interface widths of 1, 2, 4, 5, 10 and 20 channels/wavelengths.

Figure-2 provides a look at how these 20 PCS lanes are multiplexed over fiber optic medium.
Single oair of fiber cable carry multiple lanes of data at different wavelengths of light.
These 20 PCS lanes carry ethernet frame data. These data is transmitted through the lanes as 64 bit chunks
of data with 2 bit header. This results into 66 bits per block of data.

Each PCS lane is provided with alignment markers. These are periodically inserted once every 16384 blocks.
The bandwidth required for these is created by deleting IPG(Interpacket Gap) characters transmitted between the
ethernet frames. IPG of 1 character is maintained. This rate adjustment concept maintains bit rate of 100 Gigabit as needed by
this ethernet physical layer.

As mentioned multiplexing is done at bit level and all the bits from same PCS lane follow the same electrical as well as optical path.
This will ensure that data from PCS lane is received in the correct bit order at the other end of link.

Let us understand PCS lane operation at transmit end.
• Frame data blocks in lane-0 are numbered 0.0, 0.1, 0.2 and
in lane-1 are numbered as 1.0, 1.1, 1.2 and so on.
• As mentioned first multiplexing takes place which uses round robin process to copy the
20 lanes of PCS data over 10 electrical lines for transmission into transceiver module.
• second multiplexing takes place which also uses same round robin process to copy 10 lanes of data
onto four lanes for transmission over the medium. Each of these 4 lanes will have effective data rate of about 25 Gbps.
These will make total of 100 Gbps rate over the 4 lanes.

The figure-3 depicts multilane receiver of 100 gbps ethernet PHY.
As shown here data is received over four lanes.
As mentioned, demultiplexing will take place where in four lanes of data is
received from optical medium.
These data are unpacked onto 10 electrical lanes and these 10 lanes are then unpacked onto 20 PCS lanes.