Embedded DRAM for a Reconfigurable Array

Abstract:
A field-programmable gate array, coupled with an on-chip 2 Mb DRAM bank
has been designed, to aid in the study of the tradeoffs involved in the
design of embedded DRAMs for FPGAs. The memory can be used both as
configuration storage, enabling configuration in under 5 usec, and
application data memory, providing application logic executing on the
array with up to 2 GB/sec data bandwidth. The variable latency of the
DRAM is hidden from the logic by a stall mechanism and an SRAM-like
interface.