SuVolta Power-Saving Chip Process Enters Production

Fujitsu Semiconductor has begun volume production of an image processor IC that uses Deeply Depleted Channel (DDC) technology from SuVolta.

The MB86S22AA Milbeaut image processor IC, made in a 55nm manufacturing process, provides twice the performance and consumes 30 percent less power compared with competitors' products made using finer geometry processes, Fujitsu claims. The chip is a seventh generation of the Milbeaut IC series. Milbeaut was introduced in 2000 and since then has been used in several generations of single-lens reflex cameras and mobile phones.

The chip includes an ARM Cortex-A5MP and is capable of performing lens distortion and lens resolution correction at a rate of 12 frames per seconds across 24-megapixels. It is also able to perform hardware assist for feature extraction from an image, Fujitsu said.

The DDC technology, which has been licensed from SuVolta by Fujitsu, uses doping techniques to create a ground plane under a transistor and represents an alternative way to build low-power logic transistors, in contrast to the fully depleted silicon-on-insulator (FDSOI) and FinFET processes that are currently being deployed across the industry. The SuVolta method appears to achieve results similar to the FDSOI approach but avoids the cost premium of starting with SOI wafers. In research papers, SuVolta and Fujitsu have reported operating transistors down to voltages of 0.4V. (See: IEDM: SuVolta transistor operates down to 0.4-V.)

Fujitsu was SuVolta's initial development partner and first licensee, and the MB86S22AA is the result of a program that has brought the DDC technology up in 65nm and 55nm manufacturing processes while meeting production, yield, and reliability requirements. In July SuVolta said it had six DDC deployment programs in place with top-tier semiconductor manufacturers covering manufacturing process ranging from 65nm down to 20nm. (See: SuVolta Process Wins ARM, UMC Support.)

The DDC transistor relies on tight control of dopant concentration and depletion depth. The no-, low-, and high-dopant concentrations are achieved through multiple growth phases of epitaxial silicon prior to device fabrication. (Source: SuVolta)

The DDC technology enables the reduction of both leakage power and active power consumption, because it reduces transistor threshold voltage variation and improves carrier mobility. As with the FDSOI process it is possible to trade off the gains.

With DDC, users can reduce total power consumption by up to 50 percent while matching the operating speed of the same circuit implemented in conventional transistors at the same planar geometry. Alternatively they can increase the clock frequency by up to 35 percent while matching the power consumption of the conventional design. The DDC approach also offers benefits in memory and analog circuits, as it is based on bulk planar CMOS and is applicable on processes from 90nm down to 20nm.

Working together, the companies have essentially implemented a mid-life kicker to Fujitsu's 55nm process technology, enabling advances in IC functionality with much less cost and redesign than those required by node migration to 40nm or 28nm. Since the majority of IC manufacturing today is at 90nm to 40nm process nodes, the implication and benefits to the industry are significant.