Abstract:

A semiconductor structure which includes a trench gate FET is formed as
follows. A plurality of trenches is formed in a semiconductor region
using a mask. The mask includes (i) a first insulating layer over a
surface of the semiconductor region, (ii) a first oxidation barrier layer
over the first insulating layer, and (iii) a second insulating layer over
the first oxidation barrier layer. A thick bottom dielectric (TBD) is
formed along the bottom of each trench. The first oxidation barrier layer
prevents formation of a dielectric layer along the surface of the
semiconductor region during formation of the TBD.

Claims:

1. A method of forming a semiconductor structure which includes a trench
gate FET, the method comprising:forming a plurality of trenches in a
semiconductor region using a mask which includes: (i) a first insulating
layer over a surface of the semiconductor region, (ii) a first oxidation
barrier layer over the first insulating layer, and (iii) a second
insulating layer over the first oxidation barrier layer; andforming a
thick bottom dielectric (TBD) along a bottom of each trench, the first
oxidation barrier layer preventing formation of a dielectric layer along
the surface of the semiconductor region during formation of the TBD.

2. The method of claim 1 wherein at least a portion of the second
insulating layer remains over and protects the first oxidation barrier
layer following formation of the plurality of trenches.

3. The method of claim 1 wherein the second insulating layer is thicker
than the first insulating layer.

4. The method of claim 1 wherein the semiconductor region comprises
silicon, and the TBD is formed by oxidizing the silicon using a local
oxidation of silicon (LOCOS) process.

5. The method of claim 1 further comprising:forming a second oxidation
barrier layer extending along opposing sidewalls of each trench but being
discontinuous along the bottom of each trench, the second oxidation
barrier layer preventing formation of a dielectric layer along the
opposing sidewalls of each trench during formation of the TBD.

6. The method of claim 5 further comprising:prior to forming the second
oxidation barrier layer, forming a third insulating layer along the
opposing sidewalls and along the bottom of each trench.

7. The method of claim 5 wherein the first and the second insulating
layers comprise oxide.

8. The method of claim 7 wherein the first and the second oxidation
barrier layers comprise nitride.

9. The method of claim 1 further comprising:after forming the plurality of
trenches, rounding bottom corners of each trench.

10. The method of claim 9 wherein the semiconductor region comprises
silicon, and the bottom corners of each trench are rounded using a
silicon etch process, wherein the second insulating layer protects the
first oxidation barrier layer during the silicon etch process.

11. The method of claim 1 further comprising:forming a gate electrode in
each trench over and in contact with the TBD.

12. The method of claim 11 wherein the trench gate FET is formed in one or
more FET regions of the semiconductor structure, and the semiconductor
structure further includes one or more Schottky regions, the method
further comprising:in the one or more FET regions:forming a body region
in the semiconductor region; andforming source regions in the body region
adjacent each trench.

13. The method of claim 12 further comprising:forming an interconnect
layer in the one or more FET regions and in the one or more Schottky
regions, the interconnect layer contacting mesa surfaces between adjacent
trenches in the one or more Schottky regions to form a Schottky contact,
the interconnect layer further contacting the source regions in the one
or more FET regions.

14. A method of forming a semiconductor structure which includes a trench
gate FET, the method comprising:forming a plurality of trenches in a
semiconductor region using a mask which includes: (i) a first oxide layer
over a surface of the semiconductor region, (ii) a first nitride layer
over the first oxide layer, and (iii) a second oxide layer over the first
nitride layer;forming a third oxide layer along opposing sidewalls and
bottom of each of the plurality of trenches;forming nitride spacers along
the opposing sidewalls of each trench over the third oxide layer;
andoxidizing silicon to form a thick bottom oxide (TBO) along the bottom
of each trench, the first nitride layer preventing formation of oxide
along the surface of the semiconductor region during the oxidizing of
silicon, and the nitride spacers preventing formation of oxide along the
opposing sidewalls of each trench during the oxidizing of silicon.

15. The method of claim 14 wherein at least a portion of the second oxide
layer remains over and protects the first nitride layer following
formation of the plurality of trenches.

16. The method of claim 14 further comprising:after forming the plurality
of trenches, rounding bottom corners of each trench.

17. The method of claim 16 wherein the semiconductor region comprises
silicon, and the bottom corners of each trench are rounded using a
silicon etch process, wherein the second oxide layer protects the first
nitride layer during the silicon etch process.

18. The method of claim 14 further comprising:removing the nitride spacers
and the third oxide layer from along the opposing sidewalls of each
trench;forming a gate oxide layer along the opposing sidewalls of each
trench; andforming a gate electrode in each trench over and in contact
with the TBO.

19. The method of claim 18 wherein the trench gate FET is formed in one or
more FET regions of the semiconductor structure, and the semiconductor
structure further includes one or more Schottky regions, the method
further comprising:in the one or more FET regions:forming a body region
in the semiconductor region; andforming source regions in the body region
adjacent each trench.

20. The method of claim 19 further comprising:forming an interconnect
layer in the one or more FET regions and in the one or more Schottky
regions, the interconnect layer contacting mesa surfaces between adjacent
trenches in the one or more Schottky regions to form a Schottky contact,
the interconnect layer further contacting the source regions in the one
or more FET regions.

21-49. (canceled)

50. The method of claim 37 wherein the shield electrode in each trench is
biased to same potential as the gate electrode.

51. A semiconductor structure which includes a shielded gate FET,
comprising:a plurality of trenches in a semiconductor region;a shield
electrode in a bottom portion of each trench;a gate electrode over the
shield electrode;a shield dielectric lining lower sidewalls of each
trench; anda thick bottom dielectric (TBD) lining a bottom of each
trench, wherein a thickness of the TBD is different than a thickness of
the shield dielectric.

52. The structure of claim 51 wherein the thickness of the TBD is greater
than the thickness of the shield dielectric.

53. The structure of claim 51 further comprising:an inter-electrode
dielectric (IED) extending between the shield electrode and the gate
electrode; anda gate dielectric lining upper sidewalls of each trench on
each side of the gate electrode.

54. The structure of claim 53 wherein a thickness of the gate dielectric
is less than the thickness of the shield dielectric.

55. The structure of claim 51 wherein the shielded gate FET is in one or
more FET regions of the semiconductor structure, and the semiconductor
structure further includes one or more Schottky regions, the structure
further comprising:in the one or more FET regions:a body region in the
semiconductor region; andsource regions in the body region adjacent each
trench.

56. The structure of claim 55 further comprising:an interconnect layer
extending over the one or more FET regions and over the one or more
Schottky regions, the interconnect layer contacting mesa surfaces between
adjacent trenches in the one or more Schottky regions to form a Schottky
contact, the interconnect layer further contacting the source regions in
the one or more FET regions.

Description:

BACKGROUND OF THE INVENTION

[0001]The present invention relates in general to semiconductor technology
and in particular to a structure and method for forming a thick bottom
dielectric (TBD) for trench-gate devices.

[0002]An important parameter in trench power metal-oxide-semiconductor
field-effect transistors (MOSFETs) is the total gate charge. In some
applications of conventional trench power MOSFETs, such as DC-DC
converters, the lower the gate charge the better the efficiency of the
overall design. One technique in reducing the gate charge is to reduce
the gate to drain capacitance by using a thick dielectric along the
bottom of the gate trench.

[0003]A conventional local oxidation of silicon (LOCOS) process is
commonly used to form the thick dielectric along the bottom of the
trench. This process often involves forming a silicon nitride layer along
the trench sidewalls to protect the sidewalls during formation of the
thick dielectric. However, the anisotropic etch used to remove the
silicon nitride along the bottom of the trench also removes the silicon
nitride extending over the mesa surfaces adjacent the trenches. As a
result, during formation of the thick dielectric along the bottom of the
trench, a similarly thick dielectric is formed over the mesa surfaces
adjacent to the trench.

[0004]A thick dielectric over the mesa surfaces can cause a number of
problems. First, the thick dielectric typically overhangs the upper
trench corners, which can cause voiding in the gate polysilicon.
Additionally, removing the thick dielectric from over the mesa surfaces
requires substantial etching, which can also etch the gate oxide along
the upper trench sidewalls leading to gate shorts and yield problems.
Also, variability in the thickness of the dielectric over the mesa
surfaces can cause variability in the body implant process causing
variability in the electrical parameters of the device.

[0005]Thus, there is a need for improved techniques for forming a thick
dielectric along the bottom of a gate trench.

BRIEF SUMMARY OF THE INVENTION

[0006]In accordance with an embodiment of the invention, a method of
forming a semiconductor structure which includes a trench gate field
effect transistor (FET) includes the following steps. A plurality of
trenches are formed in a semiconductor region using a mask which
includes: (i) a first insulating layer over a surface of the
semiconductor region, (ii) a first oxidation barrier layer over the first
insulating layer, and (iii) a second insulating layer over the first
oxidation barrier layer. A thick bottom dielectric (TBD) is formed along
the bottom of each trench. The first oxidation barrier layer prevents
formation of a dielectric layer along the surface of the semiconductor
region during formation of the TBD.

[0007]In one embodiment, at least a portion of the second insulating layer
remains over the first oxidation barrier layer following formation of the
plurality of trenches.

[0008]In another embodiment, the semiconductor region comprises silicon,
and the TBD is formed by oxidizing the silicon using a local oxidation of
silicon (LOCOS) process.

[0009]In another embodiment, a second oxidation barrier layer is formed
that extends along the opposing sidewalls of each trench but is
discontinuous along the bottom of each trench. The second oxidation
barrier layer prevents formation of a dielectric layer along the opposing
sidewalls of each trench during formation of the TBD.

[0010]In another embodiment, prior to forming the second oxidation barrier
layer, a third insulating layer is formed along the opposing sidewalls
and along the bottom of each trench.

[0011]In another embodiment, the semiconductor region comprises silicon,
and the bottom corners of each trench are rounded using a silicon etch
process. The second insulating layer protects the first oxidation barrier
layer during the silicon etch process.

[0012]In another embodiment, a gate electrode is formed in each trench
over and in contact with the TBD.

[0013]In yet another embodiment, the trench gate FET is formed in one or
more FET regions of the semiconductor structure, and the semiconductor
structure also includes one or more Schottky regions. In the FET regions,
a body region is formed in the semiconductor region, and source regions
are formed in the body region adjacent to each trench.

[0014]In still another embodiment, an interconnect layer is formed in the
one or more FET regions and in the one or more Schottky regions. The
interconnect layer contacts mesa surfaces between adjacent trenches in
the one or more Schottky regions to form a Schottky contact. The
interconnect layer also contacts the source regions in the one or more
FET regions.

[0015]In accordance with another embodiment of the invention, a method for
forming a semiconductor structure which includes a shielded gate FET
includes the following steps. A plurality of trenches are formed in a
semiconductor region using a mask which includes: (i) a first insulating
layer over a surface of the semiconductor region, (ii) a first oxidation
barrier layer over the first insulating layer, and (iii) a second
insulating layer over the first oxidation barrier layer. A shield
dielectric is formed that extends along at least lower sidewalls of each
trench. A thick bottom dielectric (TBD) is formed along the bottom of
each trench. The first oxidation barrier layer prevents formation of a
dielectric layer along the surface of the semiconductor region during
formation of the TBD. A shield electrode is formed disposed in a bottom
portion of each trench, and a gate electrode is formed over the shield
electrode.

[0016]In one embodiment, the semiconductor region includes a drift region
extending over a substrate. The drift region has a lower doping
concentration than the substrate. The plurality of trenches is formed to
extend through the drift region and terminate within the substrate.

[0017]In another embodiment, prior to forming the gate electrode, an
inter-electrode dielectric (IED) layer is formed over the shield
electrode.

[0018]In another embodiment, forming the IED layer comprises depositing
and oxide layer and recessing the oxide layer into each trench. The first
oxidation barrier layer protects the surface of the semiconductor region
during recessing the oxide layer.

[0019]In yet another embodiment, a gate dielectric is formed lining the
upper sidewalls of each trench. In some embodiments, the gate dielectric
is thinner than the shield dielectric.

[0020]The following detailed description and the accompanying drawings
provide a better understanding of the nature and advantages of the
present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021]FIGS. 1A-1I show simplified cross-section views at various steps in
a manufacturing process for forming a semiconductor structure that
includes trench-gate FET with a thick bottom dielectric (TBD), in
accordance with an embodiment of the invention;

[0022]FIG. 2 shows a simplified cross-section view of a trench-gate FET
structure, in accordance with an embodiment of the invention;

[0023]FIG. 3 shows a simplified cross-section view of a monolithically
integrated trench-gate FET and Schottky diode, in accordance with another
embodiment of the invention;

[0024]FIGS. 4A-4M show simplified cross-section views at various steps in
a manufacturing process for forming a semiconductor structure which
includes a shielded gate trench FET with a TBD, in accordance with an
embodiment of the invention;

[0025]FIG. 5 shows a simplified cross-section view of a shielded gate
trench FET structure, in accordance with an embodiment of the invention;
and

[0026]FIG. 6 shows a simplified cross-section view of a monolithically
integrated shielded gate trench FET and Schottky diode, in accordance
with another embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0027]In accordance with an embodiment of the invention, a thick
dielectric layer is formed along the bottom of the trenches in a
trench-gate FET while a similarly thick dielectric layer is prevented
from forming over the mesa surfaces of the semiconductor region adjacent
to each trench. An oxidation barrier layer protects the mesa surfaces
during formation of the thick dielectric layer. This oxidation barrier
layer is protected by an overlying insulating layer during trench
formation and the trench corner rounding process. These and other
advantages and features of the invention will be described more fully in
the context of exemplary embodiments next.

[0028]FIGS. 1A-1I show cross-section views at various steps in a
manufacturing process for forming a trench-gate FET with a TBD in
accordance with an embodiment of the invention. The following description
of the steps in the process flow is only exemplary, and it should be
understood that the scope of the invention is not to be limited to these
particular examples. For example, processing conditions such as
temperature, pressure, layer thickness and the like could be varied
without departing from the spirit of the invention.

[0029]In FIG. 1A, semiconductor region 100 is provided as the basis for
forming the trench-gate FET. In one embodiment, semiconductor region 100
includes an N-type epitaxial layer formed over a highly doped N+ type
substrate. Hard mask 101 includes three layers and is formed over surface
108 of semiconductor region 100. In one embodiment, hard mask 101
includes first insulating layer 102, first oxidation barrier layer 104,
and second insulating layer 106.

[0030]First insulating layer 102 is formed over surface 108 of
semiconductor region 100. In one embodiment, first insulating layer 102
comprises pad oxide having a thickness in the range of 50-300 Å and
is formed using conventional techniques.

[0031]First oxidation barrier layer 104 is formed over first insulating
layer 102. In one embodiment, layer 102 comprises pad oxide and layer 104
comprises silicon nitride. The silicon nitride may have a thickness in
the range of 1800-2200 Å and be formed using a conventional low
pressure chemical vapor deposition (LPCVD) process. The pad oxide
improves adhesion of the silicon nitride layer and serves as a buffer
between semiconductor region 100 and the higher stress silicon nitride
layer. The silicon nitride layer acts as an oxidation barrier to prevent
formation of a thick dielectric over the mesa surfaces during the process
for forming a TBD depicted in FIG. 1H. Oxidation inhibiting material
other than silicon nitride may also be used, and the precise
characteristics of first oxidation barrier layer 104 may be varied by
changes to gas ratios, temperature, pressure, and spacing of the
components in the deposition chamber.

[0032]Second insulating layer 106 is formed over first oxidation barrier
layer 104. In one embodiment, second insulating layer 106 comprises oxide
having a thickness in the range of 1300-1700 Å and may be formed
using a standard chemical vapor deposition (CVD) process. Other materials
exhibiting similar characteristics may also be used.

[0033]In FIG. 1B, hard mask 101 is patterned using a photo resist layer
(not shown) and standard photolithography and etching techniques. In FIG.
1C, a conventional anisotropic etch process may be used to form trench
110 extending into semiconductor region 100. As illustrated in FIG. 1C, a
top layer of second insulating layer 106 may be removed during the trench
etch process thus reducing the thickness of second insulating layer 106.
However, second insulating layer 106 may be formed to have sufficient
thickness so that at least a portion of second insulating layer 106
remains following the trench etch step. The remaining portion of second
insulating layer 106 protects the underlying first oxidation barrier
layer 104 from certain etch process(es) in subsequent steps. Following
trench formation, surfaces 108 adjacent to trench 110 form the mesa
surfaces referred to previously.

[0034]In FIG. 1D, the bottom corners of trench 110 are rounded to reduce
defect density. In one embodiment, semiconductor region 100 comprises
silicon, and the corners are rounded using a process that etches silicon.
As illustrated in FIG. 1D, the process may remove portions of
semiconductor region 100 along the sidewalls of trench 110 thus recessing
the sidewalls. In one embodiment, second insulating layer 106 is
resistant to the silicon etch and thus protects first oxidation barrier
layer 104 during the silicon etch process.

[0035]In FIG. 1E, third insulating layer 112 is formed covering the bottom
and sidewalls of trench 110. In one embodiment, third insulating layer
112 comprises thermal oxide having a thickness in the range of 100-400
Å and may be formed using conventional thermal oxidation techniques.
First oxidation barrier layer 104 prevents formation of third insulating
layer 112 over mesa surfaces 108.

[0036]In FIG. 1F, second oxidation barrier layer 114 is formed over third
insulating layer 112 along the sidewalls and bottom of trench 110 and
over hard mask 101. In one embodiment, layer 112 comprises oxide and
layer 114 comprises silicon nitride. The silicon nitride may be formed
using a conventional LPCVD process. The oxide improves adhesion of the
silicon nitride layer and serves to protect the underlying semiconductor
region 100 along the bottom of trench 110 during the etch carried out in
the next process step depicted in FIG. 1G. Oxidation inhibiting material
other than nitride may also be used, and the precise characteristics of
second oxidation barrier layer 114 may be varied by changes to gas
ratios, temperature, pressure, and spacing of the components in the
deposition chamber.

[0037]In FIG. 1G, second oxidation barrier layer 114 is removed from the
surface of hard mask 101 and along the bottom of trench 110 using a
conventional anisotropic etch process. Portions of second oxidation
barrier layer 114 remain along the opposing sidewalls of trench 110,
e.g., in the form of nitride spacers. In some embodiments, a variety of
conventional etchant materials and etch environments may be used. Etch
variables such as gas, gas ratio, and RF power may be tuned in accordance
with known techniques to accomplish the desired anisotropic etch process.

[0038]In FIG. 1H, TBD 116 is formed along the bottom of trench 110. In one
embodiment, semiconductor region 100 comprises silicon, and TBD 116 is
formed by oxidizing the silicon using a conventional local oxidation of
silicon (LOCOS) process. Second oxidation barrier layer 114 inhibits
sidewalls of trench 110 from oxidizing, and first oxidation barrier layer
104 inhibits mesa surfaces 108 from oxidizing. In one embodiment, TBD 116
has a thickness in the range of 2000-3000 Å. The process can be
either a wet or dry oxidation depending on the capability of second
oxidation barrier layer 114.

[0039]In FIG. 1I, conventional etch processes are carried out to remove
second oxidation barrier layer 114 and third insulating layer 112 from
the sidewalls of trench 110 and to remove the remaining portions of hard
mask 101. In an exemplary embodiment, conventional oxide etch processes
may be used to remove first, second, and third insulating layers 102,
106, and 112, and conventional silicon nitride etch processes may be used
to remove first and second oxidation barrier layers 104 and 114. The
oxide etch process may also remove a thin layer off the top of TBD 116.
However, this amount may be compensated for by modifying the dielectric
growth recipe parameters during the formation of TBD 116. Further, using
a thin first insulating layer 102 ensures that only a thin layer of TBD
116 is removed when removing first insulating layer 102. In one
embodiment, only TBD 116 remains along the bottom of trench 110 following
the etch process(es) as shown in FIG. 1I. In another embodiment, third
insulating material may be retained and may serve as the gate dielectric
of a field effect transistor.

[0040]With the formation of TBD 116, the remaining portions of the
trench-gate FET structure can be formed using any one of a number of
known techniques. FIG. 2 shows a cross-section view of such a trench-gate
FET structure, in accordance with an embodiment of the invention.

[0041]In FIG. 2, an epitaxial layer 234 that is doped N-type overlies a
highly doped N+ substrate 232. Body region 222 of P-type conductivity and
source regions 228 of N-type conductivity are formed in an upper portion
of epitaxial layer 234 using conventional ion implantation techniques.
The portion of epitaxial layer 234 that is bounded by body region 222 and
substrate 232 is commonly referred to as the drift region. The drift
region and substrate 232 form the drain region of the FET. Trench 210
extends into epitaxial layer 234 and terminates within the drift region.
Alternatively, trench 210 may be extended deeper to terminate within
substrate 232. Gate dielectric layer 218 is formed along the trench
sidewalls in the embodiment where third insulating layer 112 is removed
in an earlier step. Recessed gate electrode 220 is formed in trench 210
over TBD 216 and gate dielectric layer 218 using known techniques. Body
region 222 may be formed prior to forming trenches 210 or after forming
gate electrode 220, or at another stage of the process.

[0042]The cross section in FIG. 2 corresponds to an embodiment where an
open cell configuration is used with source regions 228 and trench 210
being stripe-shaped and extending parallel to one another. In this
embodiment, conventional techniques are used to form heavy body regions
230 of P-type conductivity periodically or continuously along the source
stripes. Heavy body regions 230 are formed in body regions 222 using
known techniques. A dielectric layer (e.g., BPSG) is formed over the
structure and then patterned. Following a reflow process, the dielectric
layer forms dielectric dome 224 extending over trench 210. A top
interconnect layer 226 (e.g., comprising metal) that electrically
contacts source regions 228 and heavy body regions 230 may be formed over
the entire structure. A backside drain interconnect layer (not shown) may
also be formed to contact the backside of substrate 232. The method of
the present invention is not limited to an open cell configuration. The
implementation of the present invention in a closed cell configuration
would be obvious to one skilled in the art in view of this disclosure.

[0043]As can be seen in FIGS. 1C-1D, second insulating layer 106 covers
and protects first oxidation barrier layer 104 during trench formation
and during the trench corner rounding processes. By preserving first
oxidation barrier layer 104, a thick dielectric is prevented from forming
over surfaces 108 during formation of TBD 116. This is advantageous for a
number of reasons. The absence of a thick dielectric over surfaces 108
greatly reduces the chance of polysilicon voiding, thus improving
manufacturing yield. Also, there is no need to remove the thick
dielectric from over the mesa surfaces, thus reducing the number of
processing steps and eliminating the possibility of removing portions of
the gate dielectric from along the upper trench sidewalls. In addition,
the absence of the thick dielectric over the mesa surfaces reduces the
variability in the body implant process, thus allowing for better
controlled implant characteristics as well as reducing variations in the
electrical parameters of the transistor.

[0044]The process depicted by FIGS. 1A-1I and the trench-gate FET
structure shown in FIG. 2 can also be advantageously integrated with
other device structures. For example, FIG. 3 shows a cross-section view
of a monolithically integrated trench-gate FET and Schottky diode
commonly referred to as a SynchFET, in accordance with another embodiment
of the invention.

[0046]P-type body regions 322 are located between adjacent trenches 310 in
the FET region and extend along the trench sidewalls. Highly doped N+
type source regions 328 are located directly above body regions 322
adjacent to the trench sidewalls. Source regions 328 vertically overlap
gate electrode 320. In one embodiment, body regions 322 and source
regions 328 are formed in an upper portion of epitaxial layer 334. When
the trench-gate MOSFET is turned on, a vertical channel is formed in body
regions 322 between each source region 328 and epitaxial layer 334 along
the trench sidewalls.

[0047]In FIG. 3, a conformal barrier layer 338 is formed over the FET and
Schottky regions. As can be seen, barrier layer 338 is substantially
planar in the Schottky region and extends over dielectric caps 324 in the
FET region. Conductive layer 326 (e.g., comprising aluminum) is formed
over barrier layer 338. Conductive layer 326 and barrier layer 338 form
the source interconnect. In the FET region, the source interconnect
electrically contacts heavy body regions 330 and source regions 328 but
is insulated from gate electrodes 320. In the Schottky region, a Schottky
contact is formed where the source interconnect contacts the mesa
surfaces between adjacent trenches. Thus, interconnect layer 326 serves
as the anode electrode of the Schottky diode in the Schottky region and
as the source interconnect of the FET in the FET region. Interconnect 326
also contacts gate electrodes 320 in the Schottky region. Thus, gate
electrodes 320 in the Schottky region are electrically biased to the
source potential during operation. A backside interconnect (not shown)
contacting substrate 332 serves as the drain interconnect in the FET
region and as the cathode electrode in the Schottky region. The process
depicted in FIGS. 1A-1I can be used to form TBD 116 in both the FET and
Schottky regions. The process steps for forming the substantially planar
surface in the Schottky region are described in the commonly assigned
patent application Ser. No. 11/747,847, titled "Structure and Method for
Forming a Planar Schottky Contact", filed May 11, 2007, which is
incorporated herein by reference in its entirety.

[0048]While the invention has been described using trench-gate MOSFET
embodiments, implementation of the invention in other gate structures
with a thick bottom dielectric as well as other types of power devices
would be obvious to one skilled in the art in view of this disclosure.
For example, the thick bottom dielectric may be implemented in a
structure that includes only the Schottky diode of FIG. 3. As another
example, FIGS. 4A-4M show cross-section views at various steps in a
manufacturing process for forming a shielded gate trench FET with a TBD
formed in accordance with an embodiment of the invention.

[0049]FIGS. 4A and 4B depict the formation and patterning of hard mask 401
and correspond to previously described FIGS. 1A and 1B and thus are not
described here in detail. In FIG. 4c, a conventional anisotropic etch may
be used to form trench 410 extending into semiconductor region 400.
Trench 410 may extend deeper into semiconductor region 400 than the
trenches in non-shielded gate embodiments to accommodate a shield
electrode. As illustrated in FIG. 4c, a top layer of second insulating
layer 406 may be removed during the trench etch process thus reducing the
thickness of second insulating layer 406. Where trench 410 extends deeper
than trench 110 in FIG. 1C, second insulating layer 406 in FIG. 4A may be
formed thicker than second insulating layer 106 in FIG. 1A to ensure that
at least a portion of second insulating layer 406 remains after the
formation of trench 410.

[0050]In FIG. 4D, the bottom corners of trench 410 are rounded to reduce
defect density in a manner similar to that described with regard to FIG.
1D. In FIG. 4E, shield dielectric 440 is formed covering the sidewalls
and bottom of trench 410 using known techniques. Following the formation
of shield dielectric 440, a substantially vertical profile along the
sidewalls of trench 410 and the edge of hard mask 401 may be desired.
Thus, depending on the desired thickness of shield dielectric 440, the
sidewalls of trench 410 may be recessed accordingly during the corner
rounding process depicted in FIG. 4D.

[0051]In FIG. 4F, second oxidation barrier layer 414 is formed over shield
dielectric 440 along the sidewalls and bottom of trench 410 and over hard
mask 401 in a manner similar to that described with regard to FIG. 1F. In
FIG. 4G, portions of second oxidation barrier layer 414 are removed from
the surface of hard mask 401 and along the bottom of trench 410 in a
manner similar to that described with regard to FIG. 1G.

[0052]In FIG. 4H, a thick bottom dielectric (TBD) 442 is formed along the
trench bottom where second oxidation barrier layer 414 is removed, in a
manner similar to that described with regard to FIG. 1H. In FIG. 4I, a
conventional etch process is carried out to remove second oxidation
barrier layer 414 from the sidewalls of trench 410. In one embodiment,
second oxidation barrier layer 414 comprises silicon nitride and is
removed using a conventional silicon nitride etch process.

[0053]In FIG. 4J, shield electrode 444 is formed in the lower portion of
trench 410 over TBD 442 using known techniques. In one embodiment, shield
electrode 444 comprises doped or undoped polysilicon. The polysilicon may
be deposited in trench 410 and then etched using a standard dry etch
process to recess the polysilicon in the lower portion of trench 410.
While in conventional shielded gate trench FET processes, a thick oxide
is typically formed to protect the mesa surfaces during the polysilicon
deep recess etch, the need for forming such a thick oxide over the mesa
surfaces is eliminated since previously formed first oxidation barrier
layer 404 advantageously protects mesa surfaces 408 during the
polysilicon deep recess etch. Second insulating layer 406 may be
completely removed during the polysilicon recess etch process.

[0054]In FIG. 4K, inter-electrode dielectric (IED) layer 446 is formed
over shield electrode 444. In one embodiment, IED layer 446 comprises
oxide and is formed using standard CVD and etch techniques. The oxide may
be deposited in trench 410 and etched using a standard dry and/or wet
etch to form IED layer 446 over shield electrode 444. In one embodiment,
only dry etch is advantageously used to recess the deposited oxide. In
conventional processes for forming the IED layer, after depositing oxide
using a CVD process, the deposited oxide typically needs to be recessed
deep into the trench and thus requires both dry etch and wet etch
processes. However, because of the presence of first oxidation barrier
layer 404 (e.g., comprising silicon nitride) protecting mesa surfaces
408, the deep recessing of the deposited oxide may be carried out using
only dry etch. This is advantageous in that dry etch is a more
controllable etch than wet etch, thus resulting in a more uniform IED
layer. The etch process may also remove shield dielectric 440 from along
the upper sidewalls of trench 410.

[0055]In FIG. 4L, gate dielectric layer 448 is formed along the upper
sidewalls of trench 410. In one embodiment, gate dielectric layer 448
comprises oxide having a thickness in the range of 100-700 Å and is
formed using conventional techniques. In some embodiments, gate
dielectric layer 448 is thinner than shield dielectric 440.

[0056]In FIG. 4M, gate electrode 450 is formed in trench 410 over IED
layer 446 and gate dielectric layer 448. In one embodiment, gate
electrode 450 comprises doped or undoped polysilicon and is formed using
conventional techniques. A dry etch process may be used to remove
portions of the polysilicon extending over the mesa regions. The etch
process may recess gate electrode 450 below surface 408 of semiconductor
region 400.

[0057]As can be seen in FIGS. 4C-4D, second insulating layer 406 covers
and protects first oxidation barrier layer 404 during trench formation
and the trench corner rounding processes. First oxidation barrier layer
404 in turn prevents the formation of a thick dielectric over surfaces
408 during formation of TBD 442. First oxidation barrier layer 404 also
protects mesa surfaces 408 during the polysilicon deep recess etch
depicted in FIG. 4J. Furthermore, in forming IED 446 depicted in FIGS. 4J
and 4K, the presence of first oxidation barrier layer 404 during the deep
oxide recess enables use of only a dry etch process (as opposed to both
dry and wet etch process used in conventional techniques), thus resulting
in formation of a uniform IED. In one embodiment, first oxidation barrier
layer 404 is removed following the formation of IED layer 446 using
conventional etch processes. In other embodiments, first oxidation
barrier layer 404 is not removed until after the formation of gate
dielectric 448 or after formation of gate electrode 450.

[0058]Also, unlike conventional shielded gate structures where the
dielectric layer along the trench bottom and along the lower trench
sidewalls are formed at the same time, TBD 442 is formed along the trench
bottom separately from shield dielectric 440 formed along lower trench
sidewalls. This enables each of these dielectric regions to be
independently designed to achieve the desired device characteristics. For
example, where shield electrode 444 is tied to the source potential,
shield dielectric 440 may be made thinner for improved charge balance,
which in turn allows the doping concentration in the drift region to be
increased (thus reducing the on-resistance) for the same breakdown
voltage characteristics. Alternatively, where shield electrode 444 is
tied to the gate potential, an accumulation region may be formed in the
drift region along the lower trench sidewalls when the FET is turned on.
The accumulation region in turn helps reduce the transistor
on-resistance. By using a thin shield dielectric 440, the accumulation
effect can be enhanced, while a thick dielectric layer may be used as TBD
442 to minimize the gate to drain capacitance. In yet another variation
where shield electrode 444 is tied to the drain, the high voltage
typically present across shield dielectric 440 (where shield electrode
444 is tied to the source potential) is eliminated, thus a thinner shield
dielectric 440 may be used without concerns of shield dielectric
breakdown. In yet another embodiment where a high voltage FET is desired
and shield electrode 444 is tied to the source potential, shield
electrode 440 can be made as thick as necessary to ensure that shield
dielectric 440 sustains the high voltages. Techniques for tying shield
electrode 444 to one of source, drain, or gate potential are well known
in the art. Note that the invention is not limited to the above
combinations of shield electrode biasing, shield dielectric thicknesses,
and drift region doping concentrations. Other combinations are also
possible depending on the design goals and the target application.

[0059]Referring back to FIG. 4M, with the formation of shield electrode
444 and gate electrode 450, the remaining portions of the shielded gate
trench FET structure can be formed using any one of a number of known
techniques. FIG. 5 shows a cross-section view of such a shielded gate
trench FET structure, in accordance with an embodiment of the invention.

[0060]In FIG. 5, N-type epitaxial layer overlies highly doped N+ type
substrate 532. Body region 522 of P-type conductivity and source regions
528 of N-type conductivity are formed in an upper portion of epitaxial
layer 534 using conventional ion implantation techniques. The portion of
epitaxial layer 534 bounded by body region 522 and substrate 532 forms
what is commonly known as the drift region. Trench 510 extends into
epitaxial layer 534 and terminates in the drift region. In an alternative
embodiment, trench 510 may extend through the drift region and terminate
in substrate 532. TBD 542 is formed along the bottom of trench 510, and
shield dielectric 540 is formed along the lower sidewalls of trench 510
adjacent to shield electrode 544. Gate dielectric layer 548 is formed
along the upper trench sidewalls adjacent to gate electrode 550. IED
layer 546 is formed between shield electrode 544 and gate electrode 550.

[0061]The cross section in FIG. 5 corresponds to an embodiment where an
open cell configuration is used with source regions 528 and trenches 510
being stripe-shaped and extending parallel to one another. In this
embodiment, conventional techniques are used to form heavy body regions
530 of P-type conductivity periodically or continuously along the source
stripes. Dielectric dome 524 extends over the trench and portions of
source regions 528. A top source interconnect layer 526 (e.g., comprising
metal) contacting source regions 528 may be formed over the structure. A
backside drain interconnect layer (e.g., comprising metal) contacting the
backside of substrate 532 may be formed. The structure and method of the
present invention are not limited to open cell configuration. The
implementation of the present invention in a closed cell configuration
would be obvious to one skilled in the art in view of this disclosure.

[0062]The process depicted in FIGS. 4A-4M and the shielded gate trench FET
structure shown in FIG. 5 can also be advantageously integrated with
other device structures. For example, FIG. 6 shows a cross-section view
of a monolithically integrated shielded gate trench FET and Schottky
diode, in accordance with another embodiment of the invention.

[0063]In FIG. 6, N-type epitaxial layer 634 overlies a highly doped N+
type substrate 632. A plurality of trenches 610 extend to a predetermined
depth within the drift region (bounded by substrate 632 and body region
622) or alternatively extend into and terminate within substrate 532.
Shield electrodes 644 are embedded in each trench 610 and are insulated
from the epitaxial layer 634 by TBD 642 and shield dielectric 640. Gate
electrodes 650 are formed in the upper portion of each trench 610 and are
insulated by gate dielectric 648. Gate electrodes 650 and shield
electrodes 644 are separated by IED layer 646. In one embodiment,
trenches 610 in the Schottky region may contain only a single electrode
(e.g., shield electrodes 644 or gate electrodes 650) while trenches 610
in the FET region contain both shield electrodes 644 and gate electrodes
650. This may be accomplished using conventional masking techniques
during the steps for forming the gate and shield electrodes.

[0064]P-type body regions 622 laterally extend between adjacent trenches
610 in the FET region and vertically along the trench sidewalls. Highly
doped N+ type source regions 628 are located directly above body regions
622 adjacent to the trench sidewalls. Source regions 628 vertically
overlap gate electrode 650. When the trench-gate MOSFET is turned on, a
vertical channel is formed in the body regions 622 between each source
region 628 and the epitaxial layer 634 along the trench sidewalls.

[0065]In FIG. 6, a conformal barrier layer 638 is formed over the FET and
Schottky regions. As can be seen, barrier layer 638 is substantially
planar in the Schottky region and extends over dielectric caps 624 in the
FET region. Conductive layer 626 is formed over barrier layer 638.
Conductive layer 626 and barrier layer 638 form the topside interconnect
which electrically contacts heavy body regions 630 and source regions 628
but is insulated from gate electrodes 650 in the FET region. In the
Schottky region, a Schottky contact is formed where the topside
interconnect contacts the mesa surfaces between adjacent trenches. Thus,
the topside interconnect serves as the anode electrode of the Schottky
diode in the Schottky region, and as the source interconnect of the FET
in the FET region. A backside interconnect (not shown) contacts substrate
632 and thus serves as the cathode electrode in the Schottky region and
as the source interconnect in the FET region.

[0066]Note that while the embodiments depicted by FIGS. 2, 3, 5, and 6
show n-channel FETs, p-channel FETs may be obtained by reversing the
polarity of the various semiconductor regions. Further, in the embodiment
where regions 200, 300, 500, 600 are epitaxial layers extending over a
substrate, MOSFETs are obtained where the substrate and the epitaxial
layer are of the same conductivity type, and IGBTs are obtained where the
substrate has the opposite conductivity type to that of the epitaxial
layer.

[0067]Although a number of specific embodiments are shown and described
above, embodiments of the invention are not limited thereto. For example,
it is understood that the doping polarities of the structures shown and
described could be reversed and/or the doping concentrations of the
various elements could be altered without departing from the invention.
Also, the various embodiments described above may be implemented in
silicon, silicon carbide, gallium arsenide, gallium nitride, diamond, or
other semiconductor materials. Further, the features of one or more
embodiments of the invention may be combined with one or more features of
other embodiments of the invention without departing from the scope of
the invention.

[0068]Therefore, the scope of the present invention should be determined
not with reference to the above description but should instead be
determined with reference to the appended claims, along with their full
scope of equivalents.