> > What causes ME to sweat nights is the fact that SSO causes driver> > starvation. For the last couple of years it's the largest single> > term in our clock-to-output timing.> > Since the tradition is to specify delays and timing with one output> switching at a time, how accurate do you suppose vendor's data> sheets are, these days?

There were (and, alas, are) many other things wrong with the
old lumped-load TTL-type timing specs. Not least is the
lumped-load timing model in the first place; specifying
the delay into a 50pf load makes 'hot' drivers seem faster
than lighter ones even when the actual intrinsic delay is
longer. For this and several other reasons that should be
obvious to those of moderate skill in the art, VLSI has
gone over to a timing model where we specify the intrinsic
delay to the 10% corner (330mV for a rising 3.3v signal,
2.97v for a falling 3.3v signal). Intrinsic ramp rates
are specified separately, ideally in the IBIS model.