In the context of the graduate school „System Design“ I'm researching simulation and formal verification of failure tolerant systems. Due to single transistors becoming smaller and requiring less voltage with each passing generation, it becomes more probable that a signal changes by outer influence like cosmic rays. For this reason, failure tolerance takes an important role in the design of new systems. Failure tolerance is meant to ensure that such a fault in a signal does not lead to an error that's visible for the user. In this context I specifically examine the processor Leon3.

Reliability is great concern in space-systems due to the lack of physical access, high costs of a space-launch and ionizing radiation from the sun. Especially the latter leads to transient and permanent changes on digital circuits which eventually leads to unwanted behavior.
My research interests lie in fault-tolerance techniques for digital systems at gate- as well as system-level by using hardware-software interaction.

My task in the workgroup is to explore new techniques for formalizing the natural language and combine the outcome with existing approaches. Furthermore I am interested in exact methods for verifying and testing conventional circuits as well as synthesis for quantum circuits.

I have my Master and PhD degrees from DIKU, Department of Computer Science, University of Copenhagen with a background in programming languages, program transformation, computer architectures, and theoretical aspect such as logic and complexity.
Lately I have applied this to the field of reversible computation, mainly designing languages to describe reversible logic and reversible logic circuits, and formalising the reversible logic model.
A hobby field of mine is distributed systems, where a special interest is implementations in Erlang (or other actor model languages).

I am working in the area of reversible logic. In particular, my research work focuses on developing approaches for synthesis and optimization. Besides that, I am interested in testing of reversible circuits.

My research is about robustness check of digital circuits with use of formal methods. The features sizes in VLSI circuits shrinking continuously. Thus, circuits becoming more and more vulnerable against transient faults. The currently developed methods of robustness verification have to be improved for real-world applications.

The development of correct and reliable concurrent programs is tedious and error-prone. Failures may show up only under very specific
interleavings of the execution threads. Similarly the field of concurrent programming lacks tool support for the needs of programmers. My research focuses on the design of automatic debugging methods for concurrent programs, including the detection of failures, the localization of the corresponding faults, and finally the repair of the programs.

My previous research were in the area of automatic testing and automatic test case generation.
In the work-group, I am working in the area of automatic debugging of embedded systems. In particular the analysis of the data-flow.

My research interests cover the area of reversible logic and quantum computing. In particular, I investigate how decision diagramm can be used for the embedding of Boolean functions and for the synthesis and debugging of reversible circuits.

The focus of my research is on reversible logic, which e.g. provides the basis for quantum computing and shows promising applications in the area of low-power design. In particular, I study the synthesis of reversible circuits based on hardware description languages. Besides that, I am involved in teaching.

There is a gap each between the natural language description of a system, its formal description and its implementation, which leads to incorrectness in system development processes. Within the graduate school “system design” I deal with trying to close these gaps one with (semi-) automatic natural language processing and the other with code generation from formal descriptions (like UML).

My research interest is mainly on visualization of circuits specified in Hardware Description Languages. Currently, I am focusing on the development of visualization methods for hardware systems described in ¨higher"levels.

My research interests lie in the area of system-level design and verification. Currently I focus on developing new simulative methods for System-On-Chip (SoC) verification at higher level of abstraction.

In general I am interested in topics of Human-Computer Interaction (HCI) as the creation of user interfaces, the development of novel interaction techniques, their implementation and evaluation. In the working group I am concentrating on the development of a user-friendly debugging interface.

My main focus lies in the research field of "reversible logic and quantum computing". In particular, I am interested in the optimization of reversible and quantum circuits in terms of costs, number of gates, depth, and complexity.

My main focus lies on the one hand in research and there specially in the technical documentation and formal specification from circuits and systems on the other hand in care of courses and seminars in basic and main studies.

My scope is the timing analysis of digital circuits with the focus on the efficient identification of false paths or the generation of stimuli for specific paths, respectively.
In particular, I investigate and develop approaches based on formal methods. These methods promise a high degree of robustness which is very important for practical use.

My role in the the work-group is about developing techniques for design-space exploration and visualization. These techniques are priory used in hardware-software co-design, to develop integrated environments which optimize the VLSI-CAD.

My research interest is the application of constraint programming techniques, such as arc-consistency, in the area of SMT-solving. In particular, I am trying to combine bit vector logic with the SAT problem.

I work at the Fraunhofer Institute for Integrated Circuits, Division Design Automation and strengthen the group from Dresden. My interests mainly lie, faithfully the slogan of the Fraunhofer Gesellschaft, in the application oriented research. Here some must be done in order to successfully use theoretical procedures and experimental methods in industrial practice. In this field I deal with static and dynamic analysis to assure the quality of circuits as well as to support formal verification.

I am a almost-one year postdoctoral researcher.
My research interest is in the application of formal methods for the
verification of SoC. More
precisely, I study the link between a model, its design and its specification.
My works aim at alleviating the model checking for a given component.
On the other hand, I work on an abstraction
method that builds a component abstraction directly from its specification. This
research plans to verify a composed component in the framework of
the counter-example guided abstraction refinement (CEGAR).
homepage: www-asim.lip6.fr/~cecile

My primary research interests are in the area of on-chip bus architecture synthesis, synthesis for robustness, and low power design. The main aim is to develop algorithms, which address the future SoC design challenges.

With increasing complexity of VLSI circuits, the costs for the test phase have risen dramatically. So testability issues have to be considered from the very beginning of the design process to control the test costs and to guarantee the testability of the circuit at the end of the manufacturing process.

In the past, my research interests focussed on the development of efficient algorithms and data structures for logic synthesis and simulation-based verification of circuits and systems. I think that there is still much work to do, as the problems arising here often are real "brainteasers". For the future, I plan to consider evolutionary (i.e., genetic) algorithms or search methods as known from Artificial Intelligence.

I hold a Post-Doctoral position at the Electrical Engineering Department at the University of São Paulo (Brazil). My research is focused on two lines: 1) high performance on-chip communication structures based on NoC for 2D and 3D technologies, including verification, design optimization and the inclusion of Quality-of-Service in network-based systems; and 2) embedded security design. It includes research on and implementation of innovative and low cost protection techniques (crypto/no crypto based) against side-channel attacks, fault attacks and denial-of-service attacks.

I am a Professor of ECE at Purdue University, West Lafayette, USA, where I also hold the Roscoe H. George Chair. My research interests include VLSI design/CAD for nano-scale Silicon and non-Silicon technologies, low-power electronics for portable computing and wireless communications, spintronics, and VLSI testing and verification. You can visit my web page for more information.

I work as a PhD student in the group of Computer Architecture. My research interests include Evolutionary Algorithms (EA) and Multi-Objective Optimization (MOO). The main focus is the optimization
of the process of circuit design. For this purpose, I plan to apply EAs and MOO to VLSI CAD problems, e.g. targeting applications in HW-SW-codesign and co-simulation.

I am visiting the computer architecture group until March 31, 2009 while on sabbatical leave from the University of Victoria, Canada where I am a Professor of Computer Science. My research interests include: logic design of reversible and quantum circuits, decision diagrams, multiple-valued logic and spectral logic. My UVic web page is located at www.cs.uvic.ca/~mmiller

I am an Associate Professor in the Electrical & computer engineering Department at the Univ. of Utah, USA. My area of interests are in fundamental CAD techniques for Synthesis and Verification of Digital VLSI and post-VLSI systems. I am on sabbatical leave, and spending some time from March - July at the Univ. of Bremen. My current research projects are in Logic & Physical Synthesis of Photonic Logic and also in Application of Computer Algebra Techniques in Design Automation. For more information, see: http://www.ece.utah.edu/~kalla

My research is in the area of Logic Synthesis. In the last years the focus has been on the synthesis and minimization of reversible logic functions. Reversible logic plays a significant role in the design of emerging quantum computers.

I am a PhD student at Duke University in Durham (North Carolina, USA) in the research group of Prof. Krishnendu Chakrabarty. My current research focuses on design-for-testability and ATPG for integrated circuits, including 3D-stacked ICs.

I am a Professor of Electrical and Computer Engineering at Duke University, Durham (North Carolina), USA. I am also a Chair Professor of Software Theory at Tsinghua University, Beijing, China for 2009-2012 and a Visiting Chair Professor in Computer Science and Information Engineering at National Cheng Kung University in Taiwan for 2012. My research interests include: testing and design-for-testability of integrated circuits; digital microfluidics, biochips, and cyberphysical systems; optimization of digital print and production system infrastructure . You can visit my web page for more information.
More Information: http://www.ee.duke.edu/~krish/