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SN74GTLPH16912GR

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Texas Instruments SN74GTLPH16912GR

The SN74GTLPH16912 is a medium-drive, 18-bit UBT transceiver that provides LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, and clock-enabled modes
of data transfer. The device provides a high-speed interface between cards operating at LVTTL logic levels and
a backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL)
backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input threshold levels,
improved differential input, OEC circuitry, and TI-OPC circuitry. Improved GTLP OEC and TI-OPC circuits
minimize bus-settling time and have been designed and tested using several backplane models. The medium
drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down
to 19 .

GTLP is the Texas Instruments (TI) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard
JESD 8-3. The ac specification of the SN74GTLPH16912 is given only at the preferred higher noise-margin
GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP
(VTT = 1.5 V and VREF = 1 V) signal levels.

Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input
reference voltage.

This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port
input/output connections, preventing disturbance of active data on the backplane during card insertion or
removal, and permits true live-insertion capability.

Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or
pulldown resistors with the bus-hold circuitry is not recommended.

When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, the output-enable (OE\) input should be tied to VCC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
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