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Abstract:

A semiconductor structure includes a first PMOS transistor element having
a gate region with a first gate metal associated with a PMOS work
function and a first NMOS transistor element having a gate region with a
second metal associated with a NMOS work function. The first PMOS
transistor element and the first NMOS transistor element form a first
CMOS device. The semiconductor structure also includes a second PMOS
transistor that is formed in part by concurrent deposition with the first
NMOS transistor element of the second metal associated with a NMOS work
function to form a second CMOS device with different operating
characteristics than the first CMOS device.

Claims:

1. A semiconductor structure, comprising; first and second PMOS
transistor elements and first and second NMOS transistor elements,
wherein the first PMOS transistor element and the first NMOS transistor
element establish a first CMOS transistor pair, and the second PMOS
transistor element and the second NMOS transistor element establish a
second CMOS transistor pair; a first threshold voltage setting region
extending under a gate of the first and second PMOS transistor elements,
the first threshold voltage region defining a depletion zone when a
voltage to the transistor elements is applied; a second threshold voltage
setting region extending under a gate of the first and second NMOS
transistor elements, the second threshold voltage setting region defining
a depletion zone when the voltage to the transistor elements is applied;
a substantially undoped channel region disposed above the first and
second threshold voltage setting regions and below the gates of each of
the first and second. PMOS transistor elements and the first and second
NMOS transistor elements; a deposited first gate metal only on the gate
of the first PMOS transistor element of the first CMOS transistor pair
and the gate of the second NMOS transistor element of the second CMOS
transistor pair; and a deposited second gate metal only on the gate of
the first NMOS transistor element of the first CMOS transistor pair and
the gate of the second PMOS transistor element of the second CMOS
transistor pair.

2. The structure of claim 1, wherein the second gate metal is a
modification of the first gate metal.

3. The structure of claim 1, wherein at least one of the first gate metal
and the second gate metal has a work function between 100 millivolts from
band edge to midgap.

4. The structure of claim 1, wherein at least one of the first gate metal
and the second gate metal has a work function selected to be between
midgap and 300 millivolts from midgap.

5. The structure of claim 1, further comprising: first and second PMOS
transistor elements and first and second NMOS transistor elements,
respectively formed after source and drain regions.

6. The structure of claim 1, further comprising: first and second PMOS
transistor elements and first and second NMOS transistor elements,
respectively formed prior to source and drain regions.

7. The structure of claim 1, further comprising: a body tap region
connected to at least one of the first and second PMOS transistor
elements and first and second NMOS transistor elements to selectively
apply a bias thereto.

9. The structure of claim 1, wherein the first NMOS transistor element
operates with a predetermined first leakage, the second NMOS transistor
element operates with a second leakage at least ten times lower than the
predetermined first leakage.

10. The structure of claim 1, wherein the first NMOS transistor element
operates with a predetermined first leakage, the second NMOS transistor
element operates with a second leakage at least fifty times lower than
the predetermined first leakage.

11. The structure of claim 1, further comprising: a first screening
region extending under a gate of the first and second PMOS transistor
elements and positioned below the first threshold voltage setting region;
a second screening region extending under a gate of the first and second
NMOS transistor elements and positioned below the second threshold
voltage setting region.

12. The structure of claim 11, wherein the first screening region has a
higher dopant concentration than the first threshold voltage setting
region.

13. The structure of claim 11, wherein the second screening region has a
higher dopant concentration than the second threshold voltage setting
region.

14. The structure of claim 11, wherein the first threshold voltage
setting region is in contact with the first screening region.

15. The structure of claim 11, wherein the second threshold voltage
setting region is in contact with the second screening region.

16. The structure of claim 11, wherein the first gate metal includes any
of tantalum silicon nitride (TaSiN), titanium nitride (TiN), and tantalum
nitride (TaN).

17. The structure of claim 11, wherein the second gate metal includes any
of ruthenium (Ru), molybdenum (Mo), or tungsten (W).

18. The structure of claim 11, wherein the first gate metal includes any
of aluminum, titanium, tantalum, and alloys thereof.

19. The structure of claim 11, wherein the second gate metal includes any
of nickel, platinum, iridium, and alloys thereof.

20. The structure of claim 11, wherein the first gate metal and the
second gate metal have a same composition of materials but with different
percentages of materials used.

Description:

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation of U.S. application Ser. No.
12/960,266 filed Dec. 3, 2010, which claims the benefit of U.S.
Provisional Application No. 61/357,002 filed Jun. 21, 2010, each of which
is hereby incorporated by reference herein.

TECHNICAL FIELD

[0002] The present disclosure relates in general to semiconductor
processing and more particularly to a structure and method for
fabrication thereof providing mixed gate metals.

BACKGROUND

[0003] Gate depletion issues, high gate resistance, high gate tunneling
currents, and boron penetration into a channel are problems encountered
when heavily doped polysilicon gates of conventional CMOS transistors are
shrunk. Some of these problems can be eliminated or greatly reduced by
use of metal gates. A metal gate eliminates polysilicon gate depletion
and boron penetration from the polysilicon into the channel, and also
reduces the gate sheet resistance.

[0004] However, simply replacing the polysilicon gate with a metal gate is
not generally possible, in part because of the different required gate
work function for effective operation of PMOS and NMOS transistors. To
control short channel effects and keep off-current low, a higher than
poly gate work function is required for NMOS and a lower than p+ poly
gate work function is required for PMOS, Switching between a polysilicon
gate work function suitable for a PMOS transistor and one suitable for an
NMOS transistor requires only a minor change to the polysilicon dopant
implant process. In contrast, if a mid-gap metal having a work function
intermediate to the PMOS and NMOS transistors is selected as a gate
metal, a transistor designer must deal with a high threshold voltage. For
example, a mid-gap metal having work function around silicon's mid gap
value of about 4.6 eV could be selected to provide symmetric benefit to
both PMOS and NMOS transistors. Such work function would result in
threshold voltages too high to be acceptable for high performance logic
applications, unless costly multiple metal post-processing or alloying is
used to differentiate the PMOS and NMOS gate work functions.

[0005] Because of such problems, transistor designers have utilized two
metals having differing work functions that are respectively appropriate
for PMOS and NMOS transistors. For example, a conventional high-k/metal
gate implementation can utilize a metal that works for NMOS (typically
with a work function between 4.05 eV and 4.6 CV) and a metal that works
with PMOS (typically of work function between 4.6 eV and 5.2 eV). Common
NMOS metals include tantalum silicon nitride (TaSiN), titanium nitride
(TiN), or tantalum nitride (TaN), all of which have a work function close
to the silicon conduction band. PMOS metals include ruthenium (Ru),
molybdenum (Mo), or tungsten (W), all of which have work functions close
to the silicon valence band.

[0006] While dual metal gate transistors can be produced cost effectively
for die composed of a single device transistor type, the situation is not
as clear for complex a system-on-a-chip (SoC) die having multiple
transistor types. A system-on-a-chip die can require multiple types of
digital and analog transistors to handle low and high speed logic,
memory, wireless, and input/output functions. Each device type may have a
different required set of PMOS and NMOS gate metals for optimal
operation. If only two metals are used for all device types, performance
compromises must be made, and certain types of devices may be
incompatible with each other. However, requiring expensive additional
masking and processing steps to deposit multiple sets of gate metal for
each device type is costly, time-consuming, and results in increased
failure rate.

SUMMARY

[0007] From the foregoing, it may be appreciated by those skilled in the
art that a need has arisen to provide multiple devices with varying
characteristics while reducing masking steps to obtain the multiple
devices. In accordance with the present disclosure, a structure with
multiple devices and method of fabrication thereof are provided that
substantially eliminate or greatly reduce disadvantages and problems
found in conventional semiconductor processing techniques.

[0008] According to an embodiment of the present disclosure, a
semiconductor structure is provided that includes a first PMOS transistor
element having a gate region with a first metal associated with a PMOS
work function and a first NMOS transistor element having a gate region
with a second metal associated with a NMOS work function. The first PMOS
transistor element and the first NMOS transistor element form a first
CMOS device. The semiconductor structure includes a second PMOS
transistor element has a gate region with the second gate metal and a
second NMOS transistor element having a gate region with the first gate
metal. The second PMOS transistor element and the second NMOS transistor
element form a second CMOS device with different operating
characteristics than the first CMOS device.

[0009] The present disclosure provides various technical advantages over
devices and fabrication techniques of conventional semiconductor
fabrication processes. For example, one technical advantage is in
providing high performance devices on a same substrate with low power
devices. Another technical advantage is to provide a first NMOS
transistor element with a NMOS work function, a first PMOS transistor
element with a PMOS work function, a second NMOS transistor element with
the PMOS work function, and a second NMOS transistor element with the
PMOS work function. Yet another technical advantage is to provide four
different transistor elements using two different gate metals in order to
have two CMOS devices with varying characteristics. Embodiments of the
present disclosure may enjoy some, all, or none of these advantages.
Other technical advantages may be readily apparent to one skilled in the
art from the following figures, description, and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] For a more complete understanding of the present disclosure,
reference is made to the following description taken in conjunction with
the accompanying drawings, wherein like reference numerals represent like
parts, in which:

[0011] FIG. 1 illustrates a block diagram of a system on a chip having
multiple device types;

[0012] FIG. 2 illustrates an example process flow for fabricating multiple
devices on a chip according to a first embodiment;

[0013] FIGS. 3A-3H illustrate the changes in the structure of the multiple
devices during the fabrication process of the first embodiment;

[0014] FIG. 4 illustrates an example process flow for fabricating multiple
devices on a chip according to a second embodiment;

[0015] FIGS. 5A-5E illustrate the changes in the structure of the multiple
devices during the fabrication process of the second embodiment;

[0016] FIG. 6 illustrates the structure with a channel region having a
screening region, a threshold voltage setting region, and an undoped
channel layer;

[0017] FIG. 7 illustrates the structure with a body tap region;

[0018] FIG. 8 illustrates a graph providing a relationship between on
current and work function difference for each of a PMOS and NMOS
transistor element;

[0019] FIG. 9 illustrates a graph providing a relationship between on
current and off current with work function difference for each of a PMOS
and NMOS transistor element.

DETAILED DESCRIPTION

[0020] FIG. 1 shows a block diagram of a system on a chip 100. Support of
multiple device types on a single die diced from a single wafer is often
required for high density integration of electronic devices. Common
device types can include various combinations of digital or analog
transistors that have distinct performance requirements, and require
differing structure, voltage, and interconnect conditions for operation.
Often called a system-on-a-chip (SoC), such integrated circuit die offer
smaller size, improved performance, and lower power usage than systems
that use multiple integrated circuit packages electrically connected
together by motherboard, stack package, or through silicon via
interconnects.

[0021] As seen in FIG. 1, a variety of different devices can exist on a
single SoC 100. The SoC 100 may include conventional digital logic
devices 104, analog devices 108, and conventional input 102 and output
106, high and low voltage threshold (VT) devices 112 and 114, and
possibly other devices 110, which may be interconnected to each other
within the die via a common bus, wire traces, or other suitable
interconnections. The device types can differ, for example, in size,
operating voltage, switching speed, threshold voltage, applied body bias,
source and drain dopant implants, gate stack dielectric materials, gate
metals, or digital or analog operation. The devices are preferably formed
or otherwise processed as hulk CMOS on a common substrate (as opposed to
silicon-on-insulator), typically silicon or other similar substrate, and
are often used in computing devices, embedded control systems, integrated
wireless controllers, cell phones, network routers or wireless points,
sensors, mechanical or electrical controllers, or the like.

[0022] As compared to manufacture of a die with a single device type,
multiple devices typically requires substantially more mask steps, since
the different device types are constructed using differing process
conditions. Regions of the die having one kind of device type must be
masked to protect them from damage during processing of regions of the
die having a second kind of device type. Typically, each additional
device type requires at least one additional mask step, and can require
even more depending on process compatibility of various devices. Since
each additional mask step used to process a die of a semiconductor wafer
increases cost, processing time, and possibility of manufacturing error,
improvements that minimize the required number of mask steps are useful.

[0023] One procedure for minimizing mask steps can take advantage of
device type differentiation by metal gate selection. Certain mask steps
can be eliminated or substantially reduced by swapping the PMOS and NMOS
metals between device types. For example, a semiconductor die can be
processed to have a first device type that has a first PMOS transistor
element with a metal gate M1 and a first NMOS transistor element
with a metal gate M2. Instead of using a different metal N3 or
additional process masking steps, a second device type on the same die
can be processed to form a second PMOS transistor element with a metal
gate M2 and a second NMOS transistor element with a metal gate
M1. In effect, the respective PMOS and NMOS gate metals are swapped
between device types, with the differing metal gate work functions
resulting in different device types. Processing is simplified because an
NMOS gate of a first CMOS device can be simultaneously built with a PMOS
gate of a second CMOS device. Similarly, a PMOS gate of the first CMOS
device can be simultaneously built with a NMOS gate of the second CMOS
device. Table I shows various combinations of gate metals and two
different device types each having NMOS and PMOS transistor elements,

[0024] This can be extended to larger numbers of devices with various
possible combinations of gate metals providing different device types,
each having NMOS and PMOS transistors.

[0025] Swapping metals can be optional, with certain combinations of
device types and NMOS PHOS transistors having the same metal selection.
In other situations, devices may have the same composition of materials
but with different percentages of materials used. The present disclosure
contemplates the use of any material for the gate regions of the
transistor elements as long as a variation in work function, of at least
approximately 100 millivolts as an example, is achieved between devices
where desired. A masking step is used to expose those PMOS and NMOS
transistor elements desired to have a first gate metal with a NMOS work
function. The mask is then stripped away to expose the remaining PMOS and
NMOS transistor elements desired to have a second gate metal with a PMOS
work function. Though not necessary as the second metal gate can be
formed on top of the first metal gate without changing transistor element
performance, another masking step may be used to cover the transistor
elements filled with the first gate metal. When using a third gate metal
and a fourth gate metal and beyond, additional masking steps are only
needed to ensure that each transistor element is initially filled with
the desired gate metal.

[0026] Typically, the gate metal used provides a non-semiconductive
material with a work function that approximates the work function of a
semiconductive material that is doped to be of the same conductivity
type. For example, a typical CMOS device may be formed with an n-channel
transistor element having a tantalum-based gate electrode with a work
function approximately the same as n-doped polysilicon. A p-channel
transistor element of the CMOS device may be formed with a tantalum
nitride-based gate electrode with a work function approximately the same
as p-doped polysilicon. By swapping the gate metals, a second CMOS device
may be concurrently formed having an n-channel transistor element with
the tantalum nitride-based gate electrode with a work function
approximately the same as p-doped polysilicon. Similarly, the second CMOS
device can be concurrently formed with the p-channel transistor element
having a tantalum-based gate electrode with a work function approximately
the same as n-doped polysilicon. Metals that provide a NMOS work function
between 4.1 eV and 4.3 eV include aluminum, titanium, and tantalum.
Metals that provide a PMOS work function between 4.8 eV and 5.1 eV
include nickel, platinum, and iridium. Through the use of alloying,
larger ranges of work function can be achieved. The range of interest for
transistor element work function is from band-edge to band-edge or 4.0 eV
to 5.2 eV. However, effective work functions are somewhat removed from
the band-edges. Such work functions range from about 4.2 eV to midgap for
NMOS and midgap to 5.0 eV for PMOS. Thus, the use of appropriate metals
and alloying can be used to tune the work function in a full range from
band-edge to band-edge and provide a work function within hundreds of
millivolts of a band-edge or from the midgap. It is contemplated that
improved device performance can be achieved at about 300 millivolts from
midgap though the use of differing performance characteristics may be
desired throughout the full range.

[0027] FIG. 2 shows one example of fabrication process 200 for
manufacturing a transistors according to an embodiment of the present
disclosure. FIGS. 3A-3H show the resulting structure 300 after each
process step. The process begins in block 202 by implanting N-well
regions 304 and 306 into a substrate 302 for PMOS transistor elements 301
and 303. Conventional photoresist techniques may be performed to mask
desired portions of substrate 302 and expose desired implant areas for
the N-well regions 304 and 306. The process continues in block 204 where
P-well regions 308 and 310 are implanted into substrate 302 for NMOS
transistor elements 305 and 307. Conventional photoresist techniques may
be performed to mask desired portions of substrate 302 and expose desired
implant areas for the P-well regions 308 and 310. PMOS transistor element
301 and NMOS transistor element 305 form a first device and NMOS
transistor element 307 and PMOS transistor element 303 form a second
device.

[0028] The process continues at block 206 with the formation of channel
regions 312 and 314 appropriate for each of PMOS transistor elements 301
and 303 and NMOS transistor elements 305 and 307. Device definition and
separation may be achieved at block 208 by forming separation regions 315
in structure 300, for example through shallow trench isolation. Initial
gate formation occurs at block 210 where a polysilicon region is
deposited on structure 300 and etched away where appropriate to leave
initial gate areas 316. Link regions 318 and 320 appropriate for each
PMOS transistor elements 301 and 303 and NMOS transistor elements 305 and
307 are implanted into channel region 312 at block 212. Spacer regions
322 may then be formed at block 214 abutting initial gate areas 316 to
prevent source/drain to body silicidation shorting. Source and drain
regions 324 and 326 are then implanted at block 216 through link regions
318 and 320 and channel regions 312 and 314 for each of PMOS transistor
elements 301 and 303 and NMOS transistor elements 305 and 307.
Conventional annealing steps may be performed at each implant step as
desired.

[0029] Formation of the final gate regions 328 and 330 begin at block 218
by depositing a salicide layer 332 and then removing the initial gate
areas 316. Work function metal deposition for PMOS transistor element 301
and NMOS transistor element 307 is performed at block 220. Work function
metal deposition for NMOS transistor element 305 and PMOS transistor
element 303 is performed at block 222. Metal fill deposition and polish
is performed at block 224 to define final gate regions 328 and 330. A
first metal type is used for PMOS transistor element 301 and NMOS
transistor element 307. A second metal type is used for NMOS transistor
element 305 and PMOS transistor element 303. Conventional processing is
then performed at block 226 to obtain the final structures for PMOS
transistor elements 301 and 303 and NMOS transistor elements 305 and 307.

[0030] Though described as process steps performed in a stated order,
particular process steps may be performed at different points in the
process flow and in a different order with respect to other process steps
as desired to achieve a similar final structure design.

[0031] For example, the present disclosure also contemplates a gate first
fabrication process. FIG. 4 shows the process steps 400 for generating
transistor elements by first forming the gates of the transistor
elements. FIGS. 5A-5E show the resulting structure 500 after each process
step. The process begins in block 402 by implanting N-well regions 504
and 506 into a substrate 502 for PMOS transistor elements 501 and 503.
Conventional photoresist techniques may be performed to mask desired
portions of substrate 502 and expose desired implant areas for the N-well
regions 504 and 506. The process continues in block 404 where P-well
regions 508 and 510 are implanted into substrate 502 for NMOS transistor
elements 505 and 507. Conventional photoresist techniques may be
performed to mask desired portions of substrate 502 and expose desired
implant areas for the P-well regions 508 and 510. PMOS transistor element
501 and NMOS transistor element 505 form a first transistor pair and NMOS
transistor element 505 and PMOS transistor element 503 form a second
transistor pair.

[0032] Device definition and separation may be achieved at block 406 by
forming separation regions 515 in structure 500, for example through
shallow trench isolation. Formation of metal gate regions 512 and 514
begins at block 408 by appropriate poly deposition, etching to define the
gate regions, masking of desired transistor element areas, and metal
deposition. In this example, PMOS transistor element 501 and NMOS
transistor element 507 will have a first metal type for their respective
gate electrode. NMOS transistor element 505 and PMOS transistor element
503 will have a second metal type for their respective gate electrodes.

[0033] Work function metal deposition for PMOS transistor element 501 and
NMOS transistor element 507 is performed at block 410 with, for example,
a PMOS work function metal. Work function metal deposition for NMOS
transistor element 505 and PMOS transistor element 503 is performed at
block 412 with, for example, a NMOS work function metal. Any other metal
fill deposition and polish is performed at block 414 to define gate
regions 512 and 514. Conventional processing is then performed at block
416 to obtain the final structures for PMOS transistor elements 501 and
503 and NMOS transistor elements 505 and 507.

[0034] Additional process steps may also be performed in order to provide
different transistor characteristics. For example, channel regions 312
and 314 may be formed by traditional ion implantation processes.
Alternatively, channel regions 312 and 314 may be formed as a
substantially undoped layer of silicon, silicon germanium, or other
suitable material epitaxially grown on substrate 302 or otherwise formed
thereon or therein. The undoped channel layer is not subjected to dopant
implantation and is considered undoped as long as the dopant
concentration is less than 5×1017 atoms/cm3.

[0035] FIG. 6 shows an alternative formation for a channel in any of PMOS
transistor elements 301 and 305 and NMOS transistor elements 303 and 307.
A deeply depleted channel may be implemented that includes a screening
region 602, a threshold voltage setting region 604, and an undoped
channel region 606. The threshold voltage setting region 604 can be
formed as a layer offset from both the screening region 602 and the
undoped channel region 606. Such an offset layer can be formed by delta
doping, implant into epitaxially grown layers, atomic layer deposition,
or other available techniques for forming a well-defined dopant layer
with a dopant concentration less than that of screening region 602. In
certain embodiments, threshold voltage setting region 606, while being
formed by implant, in-situ growth, or controlled diffusion from screening
region 602, may be in contact with screening region 602.

[0036] In certain cases, the use of the described threshold voltage
setting region 604 and/or undoped channel region 606 and screening region
602 may be required for device operation. For example, in advanced nodes
the chip supply voltage is often about one (1) volt, and a PMOS/NMOS
metal swap between devices without additional significant threshold
voltage adjustment can result some devices having an unacceptably high
threshold voltages near or greater than 1 volt. This would result in a
failure of the transistor to turn on or off, which in turn could result
in failure of the system on the chip or system electronics. Even if the
threshold voltage is nominally set lower than the supply voltage by
appropriate metal selections, if the threshold voltage distribution range
is not tightly controlled by use of the described threshold voltage
setting region 604 and/or undoped channel region 606 and screening region
602, there is a large probability of system failure (due to an
anomalously high threshold voltage device) when statistical variations in
threshold voltage of millions or billions of devices are considered.

[0037] Formation of these regions that enable statistically
well-controlled threshold voltage variation and allow for significant
threshold voltage adjustments, may be performed during formation of the
channel regions 312 and 314 in FIG. 3B at block 206 of FIG. 2. Screening
region 602 is a heavily doped region formed in the associated well
region. Screening region 602 has a greater dopant concentration than the
associated well region. Screening region 602 reduces any additional
charges that may be created by random dopant variation in threshold
voltage setting region 604. Screening region 602 creates image charges
that negate fixed charges associated with threshold voltage setting
region 604. By reducing this additional charge in threshold voltage
setting region 604, the variation of the threshold voltage can be
reduced. Furthermore, forming threshold voltage setting region 604 in an
offset region from both undoped channel region 606 and a gate dielectric
has several advantages. One advantage is the threshold voltage can be
tuned over a wide range without degrading the statistical spread in the
distribution (sigma VT). The second advantage of placing dopants in
an offset region results from nearly constant short channel effects even
when random dopant fluctuations occur in threshold voltage setting region
604. In contrast to devices having doped channels, undoped channel
devices with offset threshold voltage setting regions 604 will provide
nearly constant sub-threshold swing (typically about 80 to 110 mv/decade)
device to device, even for a large number of transistors, since random
dopant fluctuations are minimized.

[0038] Threshold voltage setting region 604 is used to set the threshold
voltage for the particular transistor element based in part on the number
of dopants implanted therein. For example, various combinations of
transistor elements may be formed. For advanced semiconductor process
nodes with 65 nm gate length and below, low VT transistor element
may be formed with a dopant concentration in the range of
0.5×1018 to 1.5×1018 atoms/cm3. A medium
VT transistor element may be formed with a dopant concentration in
the range of 1.5×1018 to 3.0×1018 atoms/cm3. A
high VT transistor element may be formed with a dopant concentration
in the range of 3.0×1018 to 6.0×1018
atoms/cm3. These dopant concentrations can be reduced by 25% to 50%
while maintaining the appropriate threshold voltage through the use of an
appropriate work function of the gate metal. Swapping the gate metals,
for example by providing a first gate metal with a PMOS work function in
a NMOS transistor element, allows for further flexibility in establishing
the threshold voltage for the transistor element.

[0039] FIG. 7 shows another embodiment of the structure that includes a
body tap region 702 electrically connected to N-well 706 or P-well 708 on
substrate 700. A body tap region 702 may be formed with any or all of
PMOS transistor elements 701 and 705 (not shown) and NMOS transistor
elements 703 and 707 (not shown). Though shown in relation to a channel
region having an undoped channel layer 714 over a screening region 710
and a threshold voltage setting region 712, the use of body tap region
702 can be equally implemented with a channel region having a standard
channel layer or a single undoped channel layer as described above. In
addition to shallow trench isolation (STI) 716, partial isolation region
715 may optionally be used to separate body tap region 702 from its
corresponding transistor element. Body tap region 702 allows for
additional bias control and can be used in the setting of the threshold
voltage. The use of body tap region 702 provides another way of modifying
the threshold voltage of the associated transistor element. Through body
tap region 702, a same magnitude of threshold voltage adjustment can be
achieved as provided with the use of threshold voltage setting region 712
and screening region 710.

[0040] Functionally, one result of swapping NMOS and PMOS metals with
different work functions between device types is modification of the
threshold voltage and off state current of the transistor. As will be
appreciated, threshold voltage and off state current are critical
parameters in transistor operation, particularly affecting overall device
power leakage and transistor switching speed. Low VT transistors
switch quickly with good operating current (Ion), but typically have
high current leakage (Ioff) in off or standby states. High VT
transistors are slower to switch, but typically have low current leakage
Ioff in off or standby states. SoC die can support both types of
transistors, grouped into high performance paths or slower access/low
power blocks.

[0041] The advantage of swapping NMOS and PMOS metals between two device
types is illustrated with respect to FIG. 8, which shows a graph 800 with
NMOS/PMOS Ion versus work function (WF) difference from silicon
midgap. The dotted line corresponds to PMOS type transistors, and the
solid line corresponds to NMOS type transistors. In FIG. 8, a possible
metal selection/gate work function for a first NMOS transistor element is
indicated by a solid circle 802, and possible metal selection/gate work
function for first PMOS transistor element is indicated by a dotted
circle 804. Swapping the PMOS/NMOS metals results in NMOS metal on a
second PMOS transistor element as indicated by the solid circle 806, and
a PMOS metal on a second NMOS transistor element as indicated by the
dotted circle 808.

[0042] Presented alternatively, graph 900 of FIG. 9 shows the data of FIG.
8 represented as Ion and Ioff for the same range of work
functions. The dotted line corresponds to PMOS type transistors and the
solid line corresponds to NMOS type transistors. In FIG. 9, a possible
metal selection/gate work function for a first NMOS transistor element is
indicated by a solid circle 902 and 908 and possible metal selection/gate
work function for first PMOS transistor element is indicated by a dotted
circle 904 and 906. With only two metals, four different device types of
greatly differing characteristics can be formed by the NMOS/PMOS swap.

[0043] Other advantages can be achieved by the structure disclosed herein.
For a given add, the structure enables coexistence of transistors (or
circuits) having the usual high VT, medium VT, and low VT
parameters that exist within a 1-40× leakage range with a new set
of transistors (or circuits) enabled by the gate metal swap with relative
leakages 50× or lower. In addition, a 25% percent reduction in
drive current from one device to another is also achieved between
transistor sets. For example, a first NMOS transistor element can be
formed with a predetermined first leakage while the second NMOS
transistor element can be formed with a second leakage that can be ten to
fifty times lower than the predetermined first leakage. In addition, a
first NMOS transistor element can be formed with a predetermined first
drive current while the second NMOS transistor element can be formed with
a second drive current that can be three to six times more than the
predetermined first drive current.

[0044] FIGS. 8 and 9 illustrate the advantage using only two metals to
create four different device types of greatly differing characteristics,
but this can be extended to greater numbers of device types. Swapping the
NMOS/PMOS metals allows up to twice the number of device types without
requiring additional mask steps (unless such mask steps are desired to
create additional device types). Generally, for some number of metals N
selected for a transistor element gate, 2N device types can be simply
formed on a Sod; without a substantial increase in processing or mask
steps.

[0045] As Will be appreciated, by selecting suitable metal/work function
for a transistor element's gate, while otherwise keeping device structure
and manufacturing processes the same, allows both high performance and
low power digital devices, for example, to be economically manufactured
on the same die. Alternatively, swapped NMOS/PMOS gate metal can allow
digital devices and analog devices to be constructed on the same SoC.
Similarly, high linear sensitivity analog devices and analog I/O devices,
or deeply depleted digital and analog devices (DDC) in combination with
any conventional analog or digital device can be formed. Further
improvements can be achieved in threshold voltage shifting capabilities
using an undoped channel as opposed to foundry doped channels that limit
the threshold voltage shifting range. Moreover, most SoC implementations
as shown in FIG. 1 mask out large sections of the substrate in order to
isolate devices to certain locations therein. Through selective masking
and device formation, adjacent transistor elements on a substrate may be
formed with different characteristics to make different device types that
may be connected together due to their proximity.

[0046] Although the present disclosure has been described in detail with
reference to a particular embodiment, it should be understood that
various other changes, substitutions, and alterations may be made hereto
without departing from the spirit and scope of the appended claims. For
example, although the present disclosure includes a description with
reference to a specific ordering of processes, other process sequencing
may be followed and other incidental process steps may be performed to
achieve the end result discussed herein.

[0047] Numerous other changes, substitutions, variations, alterations, and
modifications may be ascertained by those skilled in the art and it is
intended that the present disclosure encompass all such changes,
substitutions, variations, alterations, and modifications as falling
within the spirit and scope of the appended claims. Moreover, the present
disclosure is not intended to be limited in any way by any statement in
the specification that is not otherwise reflected in the appended claims.