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Tensilica ConnX Baseband Engine

The ConnX Baseband Engine is the first member of Tensilica’s ConnX family of digital signal processor (DSP) cores for system-on-chip (SOC) design. Its scalable, high-performance DSP architecture provides computational throughput of 16 18-bit MACs per cycle. The DSP core features an optimized instruction set, high memory bandwidth, scalable clustering, and efficient compiler support with an easy programming model for SIMD (Single Instruction, Multiple Data) vectorization, and other DSP functions. The ConnX Baseband Engine is also an effective solution for multi-standard fixed and mobile DTV broadcast demodulators. ConnX Baseband engine will sample first silicon in the third quarter of this year.

ConnX Baseband Engine Features

Aligned and unaligned vector load and store instructions for 16-bit(20b) and 32-bit(40b) data

While the ConnX Baseband Engine can be used in 3G applications, the architecture of the ConnX Baseband Engine is designed for 4G and beyond. It is designed for 8-way SIMD and 3-way VLIW for maximum throughput. It has two 160-byte vector register files supporting 20bx8 and 40bx4 vector types for DSP operations. It is extremely efficient at matrix operations, and offers rich vector operations with complex arithmetic support. It can do four complex FIR taps per cycle and one Radix-4 FFT butterfly per cycle.

The ConnX Baseband Engine achieves this efficiency with an application-specific instruction set optimized for DSP functions with native support for FFT, FIR filters, and complex matrix operations. By implementing many functions in hardware, the ConnX Baseband Engine gets the performance needed for 4G applications.

While many designs will only require one ConnX Baseband Engine, this architecture can be scaled easily with up to eight instances, providing over 250 GOPS (Giga Operations Per Second) performance.