However, that circuit uses +12/0/-12V, and the monotron runs on +5/0V.

The circuit did not work correctly when I tired it using +5/0V and a virtual ground for the opamp.

Does anyone have a schematic for a very simple envelope that will work with +5/0V? I am just looking for A and D. S is optional, and R won't work since the montron shut off its sound when the note is released._________________JacobWatters.com
Synth & DJ Product Specialist, Roland Canada

I'm trying to think of a specific schematic offhand, you could try Ray Wilson's WP-20 a/d generator. (This technique is used elsewhere as well.) Basically it involves charging and discharging a cap through a pot and a diode. Your attack time will be limited to the total "on" time of your gate, so I don't recommend using a pulse. But you should have no problems running something like that off of 5 volts.
Good luck, hope this helps.
c_z

Time flies like a banana.Fruit flies when you're having fun.BTW, Do these genes make my ass look fat?corruptio optimi pessimaLast edited by JovianPyx on Mon Feb 13, 2012 8:45 pm; edited 10 times in total

Sorry for the delayed response - I have been sick the past couple of days.

Scott - I will give yours a try this weekend. Thanks for posting the schematic.

If I can't get it to work, then I will try the Ray Wilson one.

Thanks JovianPyx and comrade_zero!

***EDIT***: Scott - the monotron uses +5/0V. There is no -5V. I will have to try the TL071 with a virtual ground and see if that works._________________JacobWatters.com
Synth & DJ Product Specialist, Roland Canada

That won't work. If that's the case, only +5 and 0, then try LM324 instead of TL07x. If the LM324 provides too much of a load (i.e., if it works, but the A and D times are too short), then increase capacitor C._________________FPGA, dsPIC and Fatman Synth Stuff

Time flies like a banana.Fruit flies when you're having fun.BTW, Do these genes make my ass look fat?corruptio optimi pessima

I've made a similar 555 timer envelope recently; using a regular monostable circuit you can input a gate signal to pin 4 (reset) and trigger to pin 2 (trigger), then the decay will act as a release too when the gate goes low. Also one will have to connect the potentiometers differently than in the above circuit, seems like it should work, but I don't think it does ... I would put two diodes in series with two potentiometers (diodes facing in different directions for charg/discharge (attack/decay+release)) between pins 6 and 7 and a 1k resistor on pin 7 to +V. that should just make the 555'er happier._________________As a mad scientist I am ruled by the dictum of science: "I could be wrong about this but lets find out"

I saw what you wrote in chat. It sounds like it's not triggering. Pin 2 should be normally about 5 volts when the circuit is idle. It should bounce briefly to zero volts when the gate is applied.

To test the rest of the circuit you can do the following which will test the 7555 setup without the gate to trigger converter.

1) disconnect the gate circtuit from pin 2 of 7555
2) set the Attack control to something around halfway.
3) set the Decay control to zero resistance.
4) connect 7555 pin 2 to +5 through a 10K resistor.
5) using a piece of wire, breifly ground pin 2 of 7555. This should trigger the AD to do a cycle. If it doesn't, there's a problem with the 7555 part. If it does, then there's a problem with the gate to trigger converter (like the resistor to ground after the cap is too big)._________________FPGA, dsPIC and Fatman Synth Stuff

Time flies like a banana.Fruit flies when you're having fun.BTW, Do these genes make my ass look fat?corruptio optimi pessima

This still isn't working correctly. My pulse signal is very weak after being filtered and sent through the opamp. Maybe that is the problem?

I can't test it our properly because I don't have a proper scope (just an app that uses my soundcard).

Could someone please test it out and let me know what values to use for the unmarked resistors and caps?

My gate signal 5V and stays on the entire duration of the note. You can probably use a 555 timer or 40106 osc for a test signal that turns off and on._________________JacobWatters.com
Synth & DJ Product Specialist, Roland Canada

I just saw your post after I posted mine. I tried your test, and it didn't work, so i guess it is the 7555 part that is mess up some how...._________________JacobWatters.com
Synth & DJ Product Specialist, Roland Canada

NE555 is a bipolar 555 timer part.
7555 (sometimes with other letters like ICL7555) is a CMOS part.

They are pin function interchangeable.

The bipolar 555 timer has a nasty habit of crowbarring the power supply when it changes the state of pin 3. This is because the IC design causes both output transistors to be on at the same time for an instant. This results in a current spike that can propogate to other circuits via the power supply connection.

The 7555 is CMOS and does not do the crowbar. The output system is designed with the intention that both output transistors are never both on at the same time. (In reality, there is a much smaller instant in time where both are on, but only "half way on" at the same time, this time is far smaller than that exhibited by the bipolar 555 and the on state is not saturation). In most circuits, the two are pin for pin interchangeable. Try the circuit on breadboard first to make sure a 7555 will work (most of the time it does). If a 7555 works - it is far preferable to a 555._________________FPGA, dsPIC and Fatman Synth Stuff

Time flies like a banana.Fruit flies when you're having fun.BTW, Do these genes make my ass look fat?corruptio optimi pessima

When triggered, pin 3 immediately goes high. This supplies the charging current for C through the ATTACK pot. Once the voltage on C reaches the threshhold, the transistor (internal to the 7555) turns on and begins to discharge C through the DECAY pot. This process causes a simple attack and decay voltage at AD output.

Note that there is a diode in the path from pin 3 to C. This prevents pin 3 from discharging the cap. Because of the diode, pin 3 can only charge C._________________FPGA, dsPIC and Fatman Synth Stuff

Time flies like a banana.Fruit flies when you're having fun.BTW, Do these genes make my ass look fat?corruptio optimi pessima

Hi whats the needed voltage to trigger the 7555 in this circuit?
With the monotron delay it doesnt seem to work (Gate -> circuit -> Cutoff)

The gate drops to 3.7 once I connect the circuit, and to 2.5 on the 324 (on all three +/- and out), which is what I get at the trigger pin as well and then nothing on output.
That seems to be just the positive input there really, the trigger signal drops to a tiny 0.10 DC spike through the 0.1 uf ceramic cap.

Obvious problem?
Like what is the proper capacitor type for 0.1, I dont see why it should block DC at all, yet its not polarized like the other one?

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