NAND Flash - The New Era of 4 bit per cell and Beyond

Based on the latest NAND products that Semiconductor Insights has analyzed thus far and compiling the information published in International Solid State Circuits Conference (ISSCC) 2009 papers in early February, we were able to identify the challenges and innovations of NAND Flash manufacturers made to weather the storm of the difficult economic times currently affecting them.

The most notable of features to the latest designs announced at ISSCC 2009 is 3 bit-per-cell and 4 bit-per-cell designs from Toshiba, SanDisk and Hynix which have advanced NAND Flash cell efficiency dramatically. NAND Flash industry has entered into an era of more than 250Mbit per mm2 of NAND die efficiency with the combination of advanced process technologies in 40 nanometer(nm) and 30nm class and innovative programming techniques supporting three and four bits per NAND Flash memory cell.

Compared to the efficiency in the range of 100 ~ 150Mbit per mm2 with 50nm and 40nm process and MLC (two bit per cell) technology released less than a year ago, this achievement is phenomenal given the continued price decline and the widespread struggle of the whole memory industry.

The overall architectures also show different choices that NAND manufacturers made. Toshiba and SanDisk designs are utilizing their ABL (All Bit Line) architecture that they introduced a year ago in all of their new designs.Samsung's 42nm design is based on its traditional architecture - using even and odd bit-lines separately. Hynix's 48nm 3 bit-per-cell 32Gbit NAND design also uses conventional bit-line architecture with two planes. Intel and Micron have adopted an architecture which has page buffers placed in the center of the die effectively reducing bit-line length and load in half-enhancing performance.

Since the introduction of the 40nm class process node, the reliability of a NAND cell under severe programming conditions has been one of the top priorities for NAND Flash developers. Different vendors adopted different ways to achieve the reliability while reducing the overhead of the added measures.

Toshiba and SanDisk have adopted two dummy word-lines (one on each end of a NAND string, next to select gates) to alleviate the electrical stress and achieve the level of reliability for the cells prone to degradations and failures due to Gate Induced Drain Leakage(GIDL). To minimize the overhead of the added word-lines to the die size, the size of NAND string has been doubled to 64 from traditional 32. The resulting size of NAND string with two dummy word-lines has become 66 (64 + 2). As a result of this architectural choice to achieve reliability of NAND cells, the bit-lines have become twice as long as they would have been had the NAND string size not been modified. Innovative driving of the control gate to alleviate this effect was adopted in NAND Flash by this new architecture. Toshiba and SanDisk maintained this NAND string structure developed in their 43nm product line (analyzed and confirmed by Semiconductor Insights' analysis) with their 32nm 3 bit-per-cell 32Gbit NAND design and 43nm 4 bit-per-cell 64Gbit NAND design as well.