Understand How Design Interdependencies Impact Circuit Performance

For the builders of tomorrow, creating the electronic systems that enable smart living will require advanced design technologies on multiple levels—semiconductor, chip packaging, system interconnect, hardware-software integration, system verification, and more. Past approaches to design that address these levels disjointedly are inadequate for the increasing complexity, low-power requirements, and shorter time-to-market challenges that designers face today. Successful companies will thrive by collaborating with ecosystem leaders in electronic design automation, intellectual property, chip fabrication, and other parts of the value chain to create a comprehensive environment for intelligent system design. Cadence® custom/analog/RF solutions are a key component of this strategy.

Selectively automating non-critical aspects of custom IC design allows engineers to focus on precision-crafting their designs. Cadence circuit design solutions, including the Virtuoso® Environment, Spectre® Simulation Solutions, and Liberate™ Characterization and Validation Solutions, as well as the specialized electrically aware design (EAD) and advanced-node flows, enable fast and accurate entry of design concepts, which includes managing design intent in a way that flows naturally in the schematic. Using this advanced, parasitic-aware environment, you can abstract and visualize the many interdependencies of an analog, RF, or mixed-signal design to understand and determine their effects on circuit performance.

Electrically aware design can enable us to save several iterations on the design of each block sensitive to parasitic effects. Depending on block complexity, design time savings can range from half a day to several days per block.