PowerPC G4 PMCs

These processors have 6 32-bit PMC registers. Salient features include:

6 32 bit PMC registers, with the ability to count events and to interrupt the processor.

Each of the 6 PMC registers has essentially a different event set, though some events are countable using multiple PMC registers.

Each PMC register has a user mode counterpart that may be read using the mfspr instruction.

PMC activity can be restricted to supervisor or user modes.

Interrupts occur on overflow into bit 31 of a PMC register. These interrupts are blockable (they aren't NMIs).

Interrupts can be configured to 'freeze' or 'start' PMCs. This allows cascaded counting.

The processor's timer registers can be used to trigger a PMC interrupt.

The processor's MSR register has a PMM bit. This bit can be tested to determine if the PMCs should be active.

PMC1 needs to be enabled for any of the PMCs to be active.

Libpmc/hwpmc Enhancements

It may be useful to add the concept of a 'counting set' to hwpmc(4). Briefly, a counting set has a 'sampling' PMC associated with a group of 'counting' PMCs. When the sampling PMC interrupts the CPU, hwpmc(4) would log all the counts of the associated counting PMCs to the log in addition to the sampled instruction pointer. Today's sampling and counting modes are both degenerate cases of this unified mode.