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1 Chapter Five The Processor: Datapath and Control (Parte B: multiciclo)

2 Multicycle ApproachBreak up the instructions into steps, each step takes a cyclebalance the amount of work to be donerestrict each cycle to use only one major functional unit1 ALU, 1 Memória, 1 Banco de RegistradoresAt the end of a cyclestore values for use in later cycles (easiest thing to do)introduce additional “internal” registersPCMemoryAdsIntuciaDgR#LUBO

9 Step 1: Instruction FetchUse PC to get instruction and put it in the Instruction Register.Increment the PC by 4 and put the result back in the PC.Can be described succinctly using RTL "Register-Transfer Language" IR = Memory[PC]; PC = PC + 4; Can we figure out the values of the control signals? What is the advantage of updating the PC now?

10 Step 2: Instruction Decode and Register FetchRead registers rs and rt in case we need themCompute the branch address in case the instruction is a branchRTL: A = Reg[IR[25-21]]; B = Reg[IR[20-16]]; ALUOut = PC + (sign-extend(IR[15-0]) << 2);We aren't setting any control lines based on the instruction type (we are busy "decoding" it in our control logic)

12 Step 4 (R-type or memory-access)Loads and stores access memory MDR = Memory[ALUOut]; or Memory[ALUOut] = B;R-type instructions finish Reg[IR[15-11]] = ALUOut; The write actually takes place at the end of the cycle on the edge

13 Write-back step Reg[IR[20-16]]= MDR;What about all the other instructions?

16 Simple QuestionsHow many cycles will it take to execute this code? lw $t2, 0($t3) lw $t3, 4($t3) beq $t2, $t3, Label #assume not add $t5, $t2, $t3 sw $t5, 8($t3) Label: ...What is going on during the 8th cycle of execution?In what cycle does the actual addition of $t2 and $t3 takes place?

17 Implementing the ControlValue of control signals is dependent upon:what instruction is being executedwhich step is being performedUse the information we’ve acculumated to specify a finite state machinespecify the finite state machine graphically, oruse microprogrammingImplementation can be derived from specification

22 PLA ImplementationIf I picked a horizontal or vertical line could you explain it?

23 ROM Implementation ROM = "Read Only Memory"values of memory locations are fixed ahead of timeA ROM can be used to implement a truth tableif the address is m-bits, we can address 2m entries in the ROM.our outputs are the bits of data that the address points to m is the "heigth", and n is the "width"mn

24 ROM ImplementationHow many inputs are there? 6 bits for opcode, 4 bits for state = 10 address lines (i.e., 210 = 1024 different addresses)How many outputs are there? 16 datapath-control outputs, 4 state bits = 20 outputsROM is 210 x 20 = 1K x 20 bits (and a rather unusual size)Rather wasteful, since for lots of the entries, the outputs are the same — i.e., opcode is often ignored

25 ROM vs PLABreak up the table into two parts — 4 state bits tell you the 16 outputs, x 16 bits of ROM — 10 bits tell you the 4 next state bits, 210 x 4 bits of ROM — Total: 4.3K bits of ROMPLA is much smaller — can share product terms — only need entries that produce an active output — can take into account don't caresSize is (#inputs  #product-terms) + (#outputs  #product-terms) For this example = (10x17)+(20x17) = 460 PLA cellsPLA cells usually about the size of a ROM cell (slightly bigger)