Bit-Level Analysis of an SRT Divider Circuit

It is impractical to verify multiplier or divider
circuits entirely at the bit-level
using ordered Binary
Decision Diagrams (BDDs), because the BDD representations
for these functions grow exponentially with the word
size. It is possible, however, to analyze individual stages
of these circuits using BDDs. Such analysis can be helpful
when implementing complex arithmetic algorithms. As a
demonstration, we show that Intel could have used BDDs to
detect erroneous look-up table entries in the Pentium(TM)
floating point divider. Going beyond verification, we show
that bit-level
analysis can be used to generate a correct
version of the table.