On
April 25, 2011, Plaintiffs filed suit against AU Optronics
Corporation, AU Optronics Corporation America, Chunghwa
Picture Tubes, Ltd., HannStar Display Corporation, Hannspree
North America, Inc., Chi Mei Innolux Corporation, and Chi Mei
Optoelectronics USA, Inc., alleging infringement of U.S.
Patent No. 5, 879, 958 ("the '958 Patent").
(Doc. No. 1.) The '958 Patent is titled "Method of
Producing an Electro-Optical Device" and relates to the
process of forming circuitry used in controlling liquid
crystal displays ("LCD"). Specifically, the
'958 Patent relates to the process for forming an array
of thin film transistors ("TFT") and pixel
electrodes that are used to control the light emission of an
LCD. Notably, the '958 Patent contains 17 embodiments
(identified as A-S) providing various manufacturing processes
that reduce the number of photolithographic steps.
See '958 Patent at 4:50-14:18 (describing
processes with four or five lithographic steps as opposed to
seven).

Claim 1
is the only issued claim in the '958 Patent. Claim 1
recites as follows:

1. A method for producing an electro-optical device in which
an electro-optical material is put between a pair of
substrates opposed to each other, at least a portion of
opposing surfaces of the substrates is insulative, a
plurality of source wirings and a plurality of gate wirings
are formed crossing each other on the surface of one of said
pair of substrates and a transparent pixel electrode and a
thin film transistor are formed at each of the crossing
points between the source wirings and the gate wirings,
wherein the method comprises:

a step G1 of forming a first metal film on the surface of
said one substrate,

a first photolithographic step G2 of patterning the first
metal film to form a gate electrode and a gate wiring,

a step G3 of forming a first insulator film, a semiconductor
film and an ohmic contact film on the surface of said one
substrate after the first photolithographic step,

a second photolithographic step G4 of patterning the
semiconductor active film and the ohmic contact film to form
a semiconductor portion above the gate electrode in a state
isolated from other portions,

a step G5 of forming a second metal film on the surface of
said one substrate after the second photolithographic step,

a third photolithographic step G6 of patterning the second
metal film and the ohmic contact film to form a source
electrode, a drain electrode and a channel portion,

a step G7 of forming a passivation film on the surface of
said one substrate after the third photolithographic step,
and

a fourth photolithographic step G8 of patterning the
passivation film to form a contact hole reaching the gate
wiring, a contact hole reaching the drain electrode and a
contact hole for source wiring and gate wiring connection
terminals,

a step G9 of forming a transparent conductive film on the
surface of said one substrate after the fourth
photolithographic step, and

a fifth photolithographic step G10 of patterning the
transparent conductive film to form a transparent pixel
electrode.

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