SGI tinkers with hybrid computer architecture

Seeking the best of both chip design worlds, SGI is working on high-performance computers that combine vector- and scalar-processing components.

To speed up high-performance computers, 'a stovepipe, single-paradigm architecture may not be the answer,' SGI's chief technology officer Eng Lim Goh said last week at the National High-Performance Computing and Communications Conference in Newport, R.I.

Typically, scalar processing and vector processing have been two distinct microprocessor design approaches.

For larger computational tasks, scalar processing has grown increasingly popular, largely thanks to Intel Corp. and its low-cost mass-produced computer chips that can be clustered together to make low-cost supercomputers.

But supercomputer makers such as Cray Inc. of Seattle and NEC Corp. of Tokyo have continued to develop vector-processing chips for large, mathematically intensive computations, tasks carried out by intelligence agencies and government laboratories.

SGI has studied both approaches and found each has distinct advantages and weaknesses in the parallel-processing environment, Goh said.

Vector processors are good at performing floating-point operations and memory access but slow at integer calculations. In contrast, scalar processors are good at integer operations but slow in memory access and unspectacular in floating-point operations.

Because of this dichotomy, program managers face trade-offs in systems design. 'So if you pick one or the other, it would be good in one portion and bad in the others,' Goh said. 'We were wondering if we could have a hybrid platform.'

SGI is developing an architecture that will include both scalar- and vector-processing elements. The new design would use scalar processor chip'such as Intel Itanium chips'as a base for operations but would also include an SGI-developed vector accelerator, along with a graphics processor, Goh said.

Another feature of the new chips would be a component that lets memory modules perform their own calculations, he said.

In large, shared-memory, multiple-processor systems, often one processor will call a large chunk of data from a memory module residing on another computer, only to perform one small modification on the data before placing it back into memory.

'Instead of bringing data to the microprocessor to compute, the [new] architecture would send the instruction to the memory and the memory would operate on itself,' Goh said.

SGI wants to unveil systems based on the hybrid architecture by 2007, although some components may start appearing earlier, he said.

About the Author

Joab Jackson is the senior technology editor for Government Computer News.