On Thursday next week, December 1st, the IP community is going to launch its own IP-centric conference, REUSE 2016. It’s an important moment: Can the conference live up to its potential, provide a unique venue for discussions of this critical technology niche, and offer something to the diverse IP industry that they would not find elsewhere – all bundled together in one conference?

There are four major issues that haunt the IP industry, four freedoms demanded by the diverse, global customer base that buys from the IP industry. If REUSE 2016 wants to become the forum for those who provide IP to those customers, all four of these issues need to be addressed on December 1st in one way or another.

No. 1) Has the IP that’s been procured for integration into a design been adequately vetted? Can customers be assured a particular block of IP will be more help than a hindrance in getting a design completed quickly, into production, and out into the market?

The environment within which a block of IP is supposed to function is so influential, it may actually overwhelm whatever good might be had from using that block. Has the IP been used in any environments similar to that of the pending project and, if so, are there clever strategies, or even workarounds, useful to using that IP? How can the IP vendor, especially the smaller, less-well-established vendors, provide answers and reassurance to their customers regarding these concerns?

No. 2) A related but separate issue: How prepared does an IP vendor need to be to provide design services? Often such services can prove critical to the success of integrating a vendor’s block of IP into a project.

Without the ability to provide expert design services, an IP vendor may find itself struggling to answer numerous ad-hoc questions that arise as the customer’s design team attempts to use that provider’s IP. And those questions can come at any hour of the day or night via phone calls, emails, texts – or even in some cases, as questions posted on social media asking for crowd-sourced help. Clearly, if those questions include negative reviews of the IP vendor it can be a real buzz killer, especially if they include comments about the vendor’s inability or unwillingness to respond to problems directly.

No. 3) The flip side of issue No. 2: Should an IP vendor be providing design services and/or tools that make it difficult, or appear to be difficult, for a customer to use design services or design tools from other vendors should they so choose?

In other words, does purchasing a block of IP from a particular vendor precipitate lock-in for the customer, giving them no choice but to purchase that vendor’s other offerings, tools, or services? When does the customer get to cry foul if they feel the vendor has co-opted any opportunity for the customer to reach out to a wide set of vendors for IP and tools, and the services needed to implement a design? How and when does the IP vendor assure customers that these concerns are unfounded?

No. 4) The most difficult problem facing the semiconductor industry toady is security: Security of proprietary designs during the product development phase. Security of the manufactured end-product and confidence it won’t be reverse-engineered, copied, and sold at below-market rates by nefarious competitors. Security for the end-product in the environment within which it operates; can it be hacked or otherwise altered to mislead, spy on, or other harm users of the final system?

All of these security concerns – proprietary design info, design theft during manufacturing, and security of the final product – are all relevant to the IP industry, no matter which category of IP a vendor is selling into. Today’s IP vendor must be ready to reassure all customers that the ‘black box’ IP block they are buying does not contain any kind of back door, trap door, malware, or cunning features that could put the eventual end-product/system in jeopardy.

So there they are: the Four Freedoms customers of the IP industry demand.

*Freedom from ignorance*Freedom from going it alone*Freedom from lock-in*Freedom from fear

Clearly, it’s no small feat to be able to prosper as an IP vendor when your customers feel free to demand all of this. But then, no one ever said playing in the IP industry would easy.

In today’s world of complex designs and even-more-complex commercial and geo-political pressures, the customers know what they need and it’s up to the 450+ IP vendors across the globe to try to meet those needs.

Which brings the discussion back to REUSE 2016. If the agenda for the day-long meeting on December 1st in Silicon Valley successfully touches on all Four Freedoms listed here, the conference will live up to its promise. It will become the singular venue, going forward, for discussing the things that really matter to the brave souls who provide design blocks to an IP-hungry world.

Ridgetop Group, a complex company based in Tucson, announced a “wide-ranging” partnership with San Jose-based BaySand to “leverage their complementary skills” and offer to SoC developers in Silicon Valley and Asia “design expertise and FPGA-to-ASIC conversion for mass production using Ridgetop Group technology.”

Together the companies say they will “work cooperatively to develop a series of new applications to increase their existing mixed-signal IP portfolios.”

Considering the growing emphasis on IP in the semiconductor supply chain, this news is of particular interest. The implication being IP companies need to provide design services to succeed. Ridgetop Group is an IP company, BaySand a design company. Together they provide what the market needs, good IP and design services tailored exactly to the system integration profile of a particular class of IP.

In fact, this partnership offers even more. Potential customers could look to BaySand as a design services with its “Silicon Platform”, evaluate the appropriateness of Ridgetop IP for a particular project, and then decide to use a mix of IP from Ridgetop and other vendors to round out their design. It’s a win-win for everyone.

Craig Wentzel, SVP of Worldwide Business Operations at Ridgetop Group, confirms this optimism in the Press Release: “Ridgetop Group and BaySand together will be a powerhouse of mixed-signal IP and service offerings. BaySand will be a creative and formidable partner marketing and selling our IP, general products and services throughout Silicon Valley and Asia.”

Moazzem Hossain, EVP for Design Solution at BaySand, doubles down on that optimism: “The benefits of combining Ridgetop Group’s IP portfolio with ours and our ASIC capabilities will offer shorter time to market and lower-cost manufacturing. Our partnership will catapult Ridgetop Group and its IP portfolio into new application and markets.”

***************Per Press Release

Ridgetop Group, founded in 2000, specializes in the development of advanced InstaCell and PDKChek microelectronic test structures, the ProChek family of semiconductor characterization instruments and mini-QStar test modules, and silicon-proven, mixed-signal IP, including MEMS-based 3D sensor technology. It has a unique, collaborative IP design portfolio and specializes in services and products whereby predictive reliability, diagnostics, and prognostics software creates value-added results for products ranging from ICs to complex systems in commercial and military aerospace applications.

Next Tuesday, November 15th, is the deadline for submitting research abstracts for the IP track at DAC 2017 in Austin in June. Paper manuscripts are due the following Tuesday. IP-themed session proposals are also due on that Tuesday, November 22nd, while Designer & IP Track proposals are due December 14th.

[NOTE: The December 14th date listed above is for invited Design Track & IP Track proposals. All other proposals for DAC 2017 Design Track & IP Track content can be submitted for review up until January 14, 2017. Thank you to DAC Press Chair Michelle Clancy for this important clarification.]

In other words, if you want to present within the IP Track at the 54th Design Automation Conference, you need to get going now.

The committee that will be overseeing review of these proposals is being headed up by Lattice Semiconductor’s Claude Moughanni – his group taking seriously their role in assembling an IP program that’s both informative and cutting edge.

So, why should you go to all the effort to submit something for review by this group? Is there really any benefit in taking the time to participate at DAC, next year or ever?

First of all, yes. Some really smart people in IP have fought really hard for a number of years to get this kind of program ‘real estate’ dedicated to the subject of developing, verifying and integrating reusable IP blocks. Respect the uphill struggle they’ve had to endure by taking advantage of this opening they’ve afforded you.

Second of all, despite the rise of vendor-specific shows – not the least being, SNUG, CDNLive, Mentor’s User Group, and ARM TechCon – all of these companies, and more, continue to invest time and resources in the Design Automation Conference. They do this because, although they might find it easier and cheaper to walk away, they still know the industry values this venue. If that were not the case, you would not find Synopsys, Cadence, Mentor, and ARM on the IP Track review committee.

Third, and finally – it should be of intense and relevant interest that next year’s DAC is being chaired by a true industry icon: Michael ‘Mac’ McNamara. Mac not only has decades of distinguished EDA service to his credit, he is currently the CEO of a company called AdaptIP.

In other words, at the very top of the leadership of the DAC Executive Committee sits an individual who fully comprehends the importance and pivotal nature of reusable design blocks, and the impact these design structures have had, and will continue to have, on the emergence of phenomenal semiconductor design and devices. McNamara understands IP, and now so does the entire ecosystem that supports the Design Automation Conference.

You should recognize this reality and embrace the opportunity: To further your own research, your own commercial enterprise, and the future of IP-driven design.

Check out the link to know that the upcoming conference, REUSE 2016, will be something to behold. Slated for Thursday, December 1st, at the Computer History Museum, the event website is glamorous and the promise of the show profound:

“REUSE 2016 is the first of an annual conference and trade show to bring together the semiconductor IP supply chain and its customers for a full day of everything to do with semiconductor IP. Hosted in the heart of Silicon Valley at the world-famous Computer History Museum, there could not be a more appropriate venue for a day focused on the hottest segment of the semiconductor industry.”

Topics up for discussion on December 1st include Embedded FGPAs for Architects, Power Reduction in IoT Devices, IO Library Reuse, Receiving Full Value for Your IP, SoC Timing Challenges, IP Subsystems for High Bandwidth Memory, and Open Source Hardware, among others.

Regarding being an exhibitor: That’s definitely a work in progress. You can still sign up to be an exhibitor, which is a very good idea as getting in on the ground floor is important for anyone interested in entrepreneurial outreach in Silicon Valley.

With 28 companies already signed up to sponsor the conference, it’s clear REUSE 2016 is going to be an important venue going forward. And most interesting of all, it’s free to one and all. Doesn’t get any better than that.

Raise your hand if you think innovation comes out of small, nimble, edgy startups. Keep your hand up if you think consolidation is antithetical to the inventive culture closely associated with small, nimble edgy startups where everybody works outside of their job description and above their grade. Now put your hand down and tell us what you think about yet another merger in the semiconductor industry.

Yes, happy for investors that Qualcomm is buying NXP, but the end result will be a nasty one for technical innovators in EDA. Yet another reduction in the number of customers for EDA tools. Not necessarily a reduction in the number of seats, but a reduction in the number of actual separate corporate entities looking for tools for chip design.

Of course, for those who love large, lumbering organizations with almost as many people in the typing pool as in the engineering pool – more consolidation is great news for the semiconductor business and for the electronic design automation business, as well.

However, for those who still remember when EDA was a Wild West full of crazy startups, wacky business ideas, and loads of shifting sands between a constantly morphing/re-morphing population of EDA startups and an also-always morphing/re-morphing population of chip-design customers – take note: Those days are gone. Forever.

Now it’s just going to be one mega EDA giant versus one of the other two mega EDA giants – which if Cadence buys Mentor will only be one mega giant – as they rumble and lurch through big deals with BIG customers, over golf games, special offsite selling junkets, and enough all-you-can-eat tool packaging deals to sink an aircraft carrier full of bland, tasteless Happy Meals.

Not to mention increasingly ponderous layers of EDA political influence peddling, and enough overt efforts to control the standards conversation in favor of their particular technology to make even Microsoft blush.

After all, the mega-semiconductor customers are only going to allow themselves to be serviced by mega-EDA companies. They will be otherwise impenetrable from an EDA sales point of view, especially if you’re a startup peddling new, untested technologies.

Also an EDA startup buzz killer in the Era of Consolidation? From IT to Purchasing, the fewer EDA tool vendors the better. The customers know it and the Big Three in EDA are rubbing their hands together in ecstasy over the situation.

And so the EDA industry is on the threshold of becoming nothing more than three calcified mega-cities of employees laboring away in huge, behemoth mother ships [read Death Stars] equipped with unlimited fire power. Each one of them more than capable of shooting down even the smallest inkling of out-of-the-box, freewheeling thinking. Able to extinguish with a single cease-and-desist the kind of zany zeitgeist that lead Mad dogs and Englishmen to actually contemplate starting a startup in EDA back in the day.

Yeah, it’s over. EDA as it was is over. Dead. The coffin shut. The lights gone out. The party ended. The bubbles burst. Taps have played out their mournful tune. The sun has set. It’s over.

Now only one question remains.

If you want to do a startup – crazy you. If you want to sorta feel like you are your own boss – crazy you. If you want to do something new, different, with possibly some grand upside potential. What can you do?

It’s simple. Do a startup that provides IP.

Forget about doing tools – although some sort of CAD assist to help integrate your product into the larger design would be helpful – but really, forget the tools.

Do IP.

There’s still a whole universe of opportunities out there in IP. And the needs are so pressing, the opportunities as big as the untamed prairie, the uncharted spaces at yet unmapped.

It won’t be easy, of course. It will require deep subject knowledge, a steady business sense, and nerves of steel to go up against existing IP behemoths such as ARM and Synopsys. But really, life is short. Live on the edge. Do a startup

Do IP.

***************October 27th Press Release …

Qualcomm Inc. and NXP Semiconductors N.V. today announced a definitive agreement, unanimously approved by the boards of directors of both companies, under which Qualcomm will acquire NXP. Pursuant to the agreement, a subsidiary of Qualcomm will commence a tender offer to acquire all of the issued and outstanding common shares of NXP for $110.00 per share in cash, representing a total enterprise value of approximately $47 billion.

Next week, DVCon is once again in Europe, October 19-20 in Munich. A marvelous agenda has been laid out for this year’s 2-day conference, including three keynoters that pretty much sum up the state of things in the industry here in 2016. If you want to know where to apply your resources – both human and material – over the next decade, look no farther than these three talks.

It’s a tiring trip from Silicon Valley to Bavaria, but the quality of these presentations, combined with the rest of the content at DVCon Europe, will make the trip well worth the effort. Hope you’re going.

* ARM’s Hobson Bullman will be speaking about the focus on design and verification in ARM’s Technology Services Group.

“As the world leader in semiconductor IP, ARM supplies technology that’s at the heart of billions of new devices manufactured every year.

“In order to make that possible, ARM has enabled an engineering infrastructure and workflow group to support the compute and tooling needs of ARM, called Technology Services Group, which enables and develops best practice and promotes effectiveness, understanding and continuous improvement.

“TSG tools and services are used by ARM engineers across all regions and functions, across software, process and system design, and physical implementation.

“In this Keynote, Hobson will address some of the methodology and infrastructure challenges faced, and solutions delivered by TSG, for delivering IP into a demanding partner base, across a wide variety of markets.”

* NXP Semiconductors’ Juergen Weyer will be speaking about the securely connected, self-driving car. Today’s absolute favorite topic at every semiconductor technology conference, it’s hard not to catch the enthusiasm.

“Few industries are as primed for radical change in the years ahead as the worldwide automotive market. Advanced driver assistance system (ADAS) features are increasingly common in entry-level new car models, and today’s high-end vehicles commonly receive over-the-air software updates and feature semi-autonomous driving functionality.

“Meanwhile, Silicon Valley start-ups and established auto OEMs alike are rushing to deliver the first true ‘self-driving’ cars, thereby ushering a new era in transportation based on some of the most profound technical advancements this mature industry has seen since its inception more than 100 years ago.

“The U.S. is taking bold steps towards implementing V2X technologies with a planned mandate and a Smart City Challenge that fosters the rapid introduction of latest mobility innovations.

* ESD Alliance’s Bob Smith will be speaking about Moore’s Law and the transition from chip-centric design to system-level design.

“The semiconductor design ecosystem is evolving from a chip-centric focus to a system-centric worldview. While SoCs and other complex semiconductor devices remain as critical building blocks, the design emphasis is shifting to system
design.

“Moore’s Law remains a key driver, although there are roadblocks in the path and it is clear that the industry is beginning a transition from integration at the transistor level to integration at the functional (block) level.

“The Electronic System Design Alliance (formerly EDAC) recognizes these major changes and has acknowledged them by upgrading its mission to recognize the breadth of activity across the entire design ecosystem.”

********************DVCon Europe Sponsors …

It is refreshing to see the sponsors this year include the Big Three – Synopsys, Cadence, and Mentor Graphics – as well as AMIQ.

Geoff Tate, founding CEO at Rambus, is busy – again. These days he’s leading the charge with a new FPGA-based enterprise that, per Tate, wants to be “the first to the party” – a party that’s all about providing FGPA-based IP to a market increasingly in need of these products.

When Tate and I spoke by phone recently, he offered the Flex Logix elevator pitch, and then focused on the company’s August press release.

“We are like the ARM of FPGA,” Tate said, and then laughed. “No, we are not expecting to be acquired by SoftBank anytime soon.”

“However, ARM was the first to successfully embed processors,” he said, “and at Flex Logic we are [doing that] with FPGAs.”

Asked about his background, Tate offered: “I used to be the processor vice president at AMD, and there I met a young guy through my VC contacts who told me he had a better way to build FPGAs.

“Together we talked to some chip companies and found interest in reconfigurable RTL blocks where the protocols can be subject to change even after the chip is soldered into the system.”

Given the pent-up demand for such things, Tate said, “The response to our product offering has been really good. I believe we have the possibility of being as big as the embedded processor market.”

“And certainly big enough to make our investors happy,” he added.

Again referencing his background: “I had been the founding CEO at Rambus back when there were only four people in the company, so I have been through this before.

“Clearly, there is a lot of customer interest in the Flex Logix technology, but in the early stages of something new like this, because hiccups can be so expensive, customers are cautious and conservative – and rightly so. Looking for early adopters who are [willing to work with us] is therefore critical.

“We proved our silicon a year ago, which triggered our first customer deal – it’s been under license for over a year – and now we are in the process of porting our technology with lead customers to another node.”

Addressing the recent Flex Logix press release, Tate said, “What we are announcing is [support for] the 40-nanometer new Ultra Low Power [40ULP] node from TSMC.

“We completed the design a couple of months ago, and now a chip is in the fab to prove the silicon. We will validate it to verify performance and power, and to establish that it meets all of the specs.”

“And which EDA vendors is Flex Logix using to do its work?” I asked.

Tate replied, “We use a combination of Cadence and Mentor Graphics for our physical chip design, Synopsys Synplify for the front end of our process, and our own custom software for the back half. Finally, we use Mentor test software to complete the design.”

“Your confidence.” I noted, “indicates the team has been working on a clear road map from the very beginning.”

Tate conquered, “Yes, although there have been some surprises in going from TSMC 28 nanometers to their 40-nanometer ultra low power node. But [this porting] means we have reacted to where there is the greatest customer traction.

“As a startup, it is extremely important to develop stuff that people will actually use. It’s also important to have customers help fine-tune the technology. Some want super-low power for battery life, while others just need low power.

“Our architecture is the same across process nodes, but it’s this fine tuning of power, performance and area – done at different nodes – that makes our working with leading customers [so valuable].

“The customers doing design at 40-nanometer ULP have a very different set of performance and power trade-offs than those working at 28 nanometers. The 40ULP people want a different set of options and much more control – and they want us to design our storage units [with a special emphasis] on sleep mode.”

“And, although we ourselves might have thought of some of the [modifications] they’ve suggested, it’s far more effective when working with great customers,” he added.

“And how does a young company like Flex Logix find those great customers?” I asked.

Tate chuckled, “We knock on a lot of doors. And my background in Silicon Valley helps as well. Our investors include Lux Capital and Eclipse Ventures. These guys also open doors for us.”

“But sometimes even great customers,” I said, “can carry a grudge on the NIH front, not invented here.”

“Actually,” Tate replied, “not in the [area of] embedded FPGAs. Almost nobody has chips with embedded FPGAs, so there are no internal organizations [within the customer] that we’re competing against.

“In a few places where people do have embedded FPGAs – once they’ve seen our architecture, they conclude that our design is way better than theirs, and our scalability is much better. [They see] they can work with us, save money, and get better end results.

“Again, it’s a question of finding a few customers. Today [we believe] less than 5 percent [of customers] understand embedded FPGAs. While the other 95 percent of them say, ‘Embedded FPGAs? What’s that?’

“For most customers, their problem is the need to reconfigure RTL blocks – and that’s how they think about it.”

“Do you personally have a background in the FPGA space?” I asked.

“Not really in the FGPA space,” he answered. “We are not competing with Xilinx or Altera, but we are using FPGA technology to enable our customers. Just like ARM-enabled smart phones that could not be made with discrete processors.

“And one of our board members, Pierre Lamond [Eclipse Ventures], co-founded National Semiconductor. He was chairman of the board at Cypress Semiconductor and Microchips, and on the board of Mellanox in Israel.

“Pierre has extensive semiconductor experience, yet says he’s not investing in any semiconductor deals now, because it too hard to make the financials work. If you build chips, you need to pay for the masks, you’ve got to carry inventory, and [deal with] expensive package design.

“Pierre is investing in us, however, because we are developing IP, not making chips. There’s a difference. The IP business model doesn’t need a lot of capital.

“What we are developing is a block that goes into the chip. We don’t have to be experts in anything in the semiconductor area, and we don’t have to pay for the 100 engineers [associated with all of that].”

Tate also noted that although he’s been asked to lead several startups in recent, it’s the technology and team at Flex Logix that’s compelled him to lead this one: “My co-founder, Cheng Wang, strikes me as smart and hardworking. He’s got the brains and I’ve got the business side. I kind of know if things are on the right track.”

“What about the basic stats for the company,” I asked. “Who? Where? When?”

Tate obliged: “We’re based in Mountain View, with low double digits employees. Our technology stems from the work that Cheng Wang did at UCLA, along with a couple of other guys – Professor Dan Markovic [headed the team].

“While Cheng was at UCLA, he [and his colleagues] did five different test chips with 1000 lookup-table FPGAs. Their last chip had 30,000 lookup tables, plus DSP acceleration.

“Cheng observed in designing these FPGA chips, that most of the area was in the programmable interconnect used to connect the logic blocks. They needed 80 percent for the programmable interconnect – traditionally connected in a mesh interconnect. Xilinx and Altera in the 1990s.

“But Cheng came up with a new interconnect structure, licensed to us by UCLA, with twice the density compared with traditional mesh. It also uses fewer metal layers, which is important for high-volume customers. That’s when he [started thinking], I could start an FPGA company with this.”

“If UCLA owns and licenses this technology, what’s to stop a nascent competitor from competing with Flex Logix using the same technology?” I asked.

Tate was quick to respond: “We are not starting from scratch – instead of being 20th to the party, we intend to be the first.

“Our customers have been very surprised that we could get to working silicon within a year after starting. But again, we are not starting from scratch.

“Instead, we are now tuning the technology for embedded FPGAs, which has required some architectural changes. Plus Cheng rewrote the software in a format that is much more robust for commercial use.”

“UCLA stands to win if you succeed?” I asked.

“Yes, they are the ones with the patents.” Tate said. “We pay UCLA some royalties, and some fees. But everyone wins if Flex Logic succeeds.

“There’s a belief that only optimists start companies, and we are all optimists here at Flex Logix. Two years ago, I would have spoken about all of this with more conditionals, but now the things we wanted to happen are definitely happening.”

His confidence prompted two queries: “Given your success at Rambus, do you believe lighting can strike twice? More importantly, are you enjoying yourself in all of this?”

Tate was unequivocal: “Yes and yes.”

“Look, I made a lot of money at Rambus. I’m not doing this for the money. Life is too short to do the things you don’t enjoy.”

*******************Copy Editor’s Note …

Thank you to Linley Gwennap of the Linley Group for kindly pointing out the subtle difference between affect and effect. His copy edit has been gratefully noted, and the change implemented in the title of this blog.

Synopsys has a problem. Per Norm Kelly, speaking at the ESD Alliance panel on September 14th in Silicon Valley, Synopsys loses fully a third of the revenue they’re owed each year for their vast catalog of IP because it’s stolen by Cheaters and used without paying any licensing or royalty fees.

Kelly said Synopsys earns about $200 million per year selling IP, and loses another $100 million to theft. Cheaters are a real problem, he lamented, and as Director of License Compliance for Synopsys he should know. Kelly did not have the floor to share these laments, however, until Warren Savage, GM of IP at Silvaco, opened the meeting.

Speaking from the podium as moderator of the evening’s discussion, Savage said the real problem is the bumblers, those designers and companies who lose track of licensing obligations for IP that was either purchased some time ago, or was brought into the design effort on a data stick fished out of the pocket of someone who’s joined the organization through a poorly managed M&A.

In other words, when Chuckles the Clown uses IP, often as not he doesn’t realize some monies are owed to the third-party IP vendor who created it in the first place. Savage offered this statistic: On an average SoC today, there are 150 to 200 blocks of IP, but only a small percentage of those blocks are actually paid for.

Chuckles the Clown is indeed alive and well in the IP user community and to blame for most of the lost revenue owed to an increasingly agitated IP vendor community, per Savage. He drove home the point with the proverbial foot-on-banana-peel graphic.

Savage and Kelly weren’t the only two at the front of the room on Wednesday night, however.

Also perched on speaker stools were KPMG’s Rob Ballow and Pricewaterhouse-Cooper’s Eric Stein. These two guys are accountants-turned-IP-sleuths, who handle audits of IP use in semiconductor companies on behalf of the IP vendors who sell the stuff.

How is IP usage audited? Ballow and Stein were not quite clear on the process, but basically it’s an issue of body language, is what we were told.

If somebody in a user company starts to hem, haw, look away, or fidget in their chair when they’re asked by outside auditors if IP is being used on projects without adequate licensing or fees being paid, the auditors know they’ve got a live one, a cheater.

Despite the tell in their body language, however, cheaters are often reluctant to confess to their crimes. Ballow amused his audience with one particularly momentous story.

An IP vendor in Europe sent out a notice to all of their customers worldwide announcing that an audit team was going to call on each and every customer to determine if any of the vendor’s IP was being used without proper licensing.

One of the vendor’s customers – a large company in Asia, according to Ballow – responded to the letter with a $10 million check sent by return post. The company said they were sending the money as a courtesy, but would not be submitting to an audit of any of their people or projects. The $10 million was a just-in-case payment for violations in case there were any, which there weren’t.

Larger lesson here? Audits are only optional, and must be submitted to voluntarily by the companies that use IP.

So much for Cheaters and Chuckles, now for the Chalk and Cheese.

There are several methods for tagging and tracking IP usage. These methods were discussed throughout the 2-hour session on Wednesday night, by Savage, Kelly, Ballow and Stein, and also by many in the audience who participated in the lively back-and-forth.

For instance there’s a long-standing IP tagging standard, promoted by Accellera. Per several speakers in the audience, however, that standard is rarely used, it’s not robust enough and therefore of little value.

More recently, Warren Savage – while still CEO at IPextreme, before his company was acquired by Silvaco – oversaw the development of a fingerprinting scheme that puts identifying markers on a block of IP that can be used to track the block throughout its integration into a design and subsequent manufacturing into a chip.

“Nobody in the semiconductor companies really wants to cheat,” Savage said, “which is why they need these tracking tools to help monitor all of the IP floating around out there.”

The fingerprinting strategy was announced late last year [see blog here], and is now a project that Silvaco continues to promote, with Savage leading the effort via his involvement with ESD Alliance.

[Hence this Wednesday’s panel was held on the Silvaco campus in Santa Clara and all in attendance were gifted with a nifty Silvaco-branded wireless mouse upon exiting the meeting.]

The value of this fingerprinting strategy notwithstanding, some in the audience still expressed profound skepticism over any kind of IP tagging, fingerprinting, or tracking tools and strategies. All of them can be circumvented, was the consensus.

Norm Kelly acknowledged the optimism of Warren Savage and also agreed with the pessimism he heard from the audience: “Yeah, most don’t want to cheat, but many companies do want to cheat. Soft IP is configurable and hard to fingerprint, but even hard IP can have the tagging layer removed.”

In other words, all of these protocols, tags, tools, and so forth, are no better than the meter maid’s Chalk on your tire. If you’ve exceeded the time limit in that parking spot, just move your car forward so the chalk mark is in a different location relative to the street, or smudge it out completely with the heel of your hand.

As one audience member put it on Wednesday night, “Cheaters who steal IP are truly nefarious. They steal the IP, they change it, and then they sell it. What can fingerprinting do to stop that?”

The chalk mark on IP is simply not powerful enough to stop the cheaters. So what strategy remains to those IP vendors who continue to insist they should be paid for the products they provide to an IP-hungry industry?

That’s where the Cheese comes in.

After the panel discussion was ended and the crowd began mingling, a very knowledgeable CEO approached me and offered the most defensive, and seemingly robust strategy to counter both Cheaters and Chuckles.

Issue a new version of your IP every 90 days, the new version is not backwards compatible, and ergo anybody looking for support for a piece of IP that’s older than 90 days is simply out of luck. The vendor company will know instantly that IP is being used without proper licensing and fees.

Old cheese is stinky cheese, and will not sit well if consumed. Eat it and suffer the consequences.

And there’s one more part to this very defensive stance, about which the knowledgeable CEO was absolutely blunt: “We don’t do business with people we do not trust.

“If we don’t trust them, it’s simply not worth our time. Period.”

*****************Addendum …

* You will be able to access the entirety of this extremely informative panel discussion very soon. It was taped and will be viewable shortly on the ESD Alliance website.

* The Core Store is an online repository, developed at IPextreme and now supported by Silvaco, where companies who chose to participate in the IP fingerprinting scheme can register their IP.

* The world of IP will be gathering for a debut conference in December 2016. Supported by the ESD Alliance, CAST, True Circuits, SoC Solutions, Certus, Silicon Creations and Silvaco, this one-day meeting will be held in Silicon Valley.

Over the last several weeks, the ESD Alliance has announced two more members, news of particular interest because both companies are IP vendors. C-Sky Microsystems provides 32-bit embedded CPU cores, and Silvaco provides EDA tools for development of analog/mixed-signal devices, power IC and memory design.

True, Silvaco doesn’t sound like an IP vendor until you remember that it just acquired IPextreme, a well-known player in the IP market headed up by Warren Savage. And Savage, now GM of Silvaco’s IP Division, has recently been named chair of the ESD Alliance Semiconductor IP Working Group, tasked with developing a common methodology, best practices for fingerprinting, and solutions for tracking and auditing IP.

Meanwhile, C-Sky Microsystems brings its own unique value proposition to ESD Alliance. Described in the Press Release as “the first IP company from China to join the ESD Alliance,” C-Sky says it intends to actively participate in Savages’ SIP Working Group. This second bit is admirable, but the first could prove complicated.

For many semiconductor design houses, China presents problems when it comes to manufacturing, a long-standing concern about IP protection during the manufacturing process. Relying on the vast semiconductor manufacturing infrastructure in Taiwan, instead, is for some the solution. A geographically beneficial location in Asia that is not associated with a country frequently accused of less-than-stringent IP protection protocols.

So herein lies the concerns. People who use IP, and the vendors who sell it, need processes for securing the pipeline, audits for tracking IP usage and the associated liabilities, costs, royalties. If an IP vendor is associated with a location or country that continues to generate concerns about IP protection, how can that vendor participate in the development of the aforementioned processes for tracking and auditing IP usage?

In 2009, I published a blog suggesting that the Common Platform was launched, subliminally, as the not-China option. Here isa link to that blog.

The messaging in that blog notwithstanding – to think we’ve come so far as to include a China-based IP company in the membership of the ESD Alliance is a great step forward in international understanding and/or faith in good global business practices.

Don’t be surprised, however, if this newest member of the ESD Alliance also generates some concerns. It may not be politically correct to air those concerns, but when has the business of making money ever been politically correct?

This is a touchy subject, no doubt about it. But failing to address these concerns could potentially undermine any good that’s been done so far by the ESD Alliance in enlarging its scope to include IP vendors in its ranks.

This week’s blog post is authored by Bill Finch, Senior VP at CAST, Inc., long-time provider of IP cores and platform IP products. The discussion below maps the evolution of technologies and strategies that produced today’s IoT to the critical road map needed to achieve tomorrow’s.

*****************IoT: The Second Coming

The second wave of the IoT is about to start. In the first wave, there was little clarity about what functionality really mattered. Engineers were tasked with getting products out ASAP. Because of the uncertainty and rush, most first-wave products were built around off-the-shelf parts made by IDMs (Integrated Device Manufacturers). The emphasis was on getting things working, not on optimization.

This will not be true in the second wave.

In many markets, we will see a resurgence of custom SoCs being designed with a much clearer concept of what will differentiate these products from the competition. We always knew that power consumption in edge devices was a big deal, and now we know – with a great deal of certainty – what activities consume power. Optimizing to deal with these functions will now be paramount.

Wireless transmissions, no matter the frequency or standard, have to be optimized. There is, however, a limit to what can be done. Sooner or later you have to turn on the radio. Therefore, the best approach is to process the raw data at the source to reduce its size. This means far more compute power will be needed at the edge than most people originally believed.

More computing at the edge also means more software at the edge. More software means bigger memories, which then consume more power. So controlling the size of the on-board memories requires new thinking as well.

One approach to meeting the challenge of optimizing power across the chip is to break the design down into sub-systems, each highly optimized for a particular function. Making this strategy work will require tiny processors that can each perform a single task very efficiently and then go to sleep immediately, once their job is done. Trying to force-fit a processor designed with the typical 32-bit architectures of pipelines and caches will not be good enough.

One way to reduce the size of the main on-chip memories is to take a cue from the Data Center experts: use a data compression strategy. This is a well-known and proven technology.

By compressing the firmware when writing, decompressing, and reading, memory requirements can be substantially reduced and a significant amount of power can be saved. Unlike in the Data Center where processing power is abundant, when this technique is applied at the chip level it must be done with hardware accelerators.

Beyond technical issues, success in the second wave of the IoT requires that costs come down significantly. Well thought out designs that can achieve the kinds of economies of scale typically seen in consumer markets will be necessary for corporate success and profitability.

Additionally, designing products that have a bill of materials with substantial built-in royalty streams will hold back success and lead to what in earlier generations was known as “profitless” prosperity: wildly successful products with margins so thin that no one made money.

Still, it remains to be seen whether the consolidation wave that has swept through the industry is going to lead to successful second-wave designs.

Most of the M&A of the past few years was focused on building products for smartphones and tablets and other leading edge consumer devices. These designs were giant multi-processor SoCs that required the latest bleeding edge process nodes to work. They required specialized design skills and large design teams.

Today, however, such a hugely expensive infrastructure is not at all necessary to build many of the optimized IoT designs that define the second wave.

That is why it is highly likely we will see a return to the days when a few smart people with the right ideas can actually bring to market successful designs built on much cheaper processes. Being free of corporate structures that dictate choices in IP and tools will allow a more creative design approach and more cost-effective – read “profitable” – IoT solutions.

Certainly one could ask, will funding be available? The answer depends on whether the Angels, the VCs and their brethren, can return to the days when they willingly took reasonable risks to fund people with a vision. The IoT will not be built on apps.

One last thought on funding: SoftBank (CEO Masayoshi Son, in particular) said they bought ARM because they saw the future and it was the IoT.

Since SoftBank only brings money to the table here, and ARM already has plenty of that, it remains to be seen how this helps anybody, either ARM or its customers. The IoT will not consume nearly as many of the large, expensive specialty processors that ARM has been delivering up until now.

Big royalties should be anathema to most IoT chip builders. SoftBank already has huge debt that only gets massively bigger with this purchase. There is a limit to how much more investors can stand before returns flow in. If ARM struggles at all, SoftBank could be in for a rough ride, and so will its customers.

We’re not there yet, but the second wave of the IoT is coming. The time to prepare is now.