Thanks Qusp, will do.
Actually couple already. Thought FIFO-Dual clock was capable of 384KHz but leds on the Dual Clock indicating up to 192KHz only. And then the isolator board, if inserted after the FIFO wouldn't it introduce additive jitter going through all the GMRs?

Speeds higher than 192 are indicated by combination of LEDs, I'm away from my comp at the moment but I am sure Ian has the combinations in the docs

All i2s lines are reclocked with the potato logic flipflops at output of the clock board so GMR additive jitter has no impact unless it misses the clock cycle input to the flipflop, if that was the case Ian's bit perfect tests would fail I expect. Delay through the flipflop should be the only jitter seen at the output which is how Ian comes up with his ~2ns spec.

Both of the clock board and I2S to PCM convertor board re-clock the I2S at last stage, in this case, only jitter from MCLK is significant. Dont worry about the signal path, additional jitter will be re-clocked anyway.

Thanks Qusp, will do.
Actually couple already. Thought FIFO-Dual clock was capable of 384KHz but leds on the Dual Clock indicating up to 192KHz only. And then the isolator board, if inserted after the FIFO wouldn't it introduce additive jitter going through all the GMRs?

thats OK, the 384 is indicated by both lit from memory, it was not initially designed for indicating such high speeds but copes no problem with latest FW. you could also look at using a little BGA sink on the FPGA

hochopeper has it pretty much right.

at my prompting the isolator board was designed to go between the fifo main board and clock board very deliberately. this way you even isolate the clock board from the possible slew and simultaneous switching noise from the FPGA and all that PC related ripple that comes before it if USB->i2s is used. this places it at the last point before the reclock stage

Effectively it allows the clock board to be married to the dac again. then its reclocked by the dual clock board + flip flops, effectively deleting the jitter from the isolator as well as that before it; aside from the XO + buffer self noise/jitter

initially the parts on the dual clock board were potato logic, but I think he changed to Ti for later versions of that board, changing back to potato logic for the si570 with more knowledge gained on their use. thats how it was anyway, perhaps he has changed back again on the dual XO too.

a possible experiment that I will do and perhaps you can too, is to power the output side/quiet side of the isolator and the clock buffers with the same power supply (or one that is grounded on the dac side ground plane directly) as is powering the logic/ring of the ESS dac. cant remember if its that specific, or just the same ground, same PSU, so could be any of them, even a beefed up flea with mosfet grounded/connected where the old (presumably now vacant/unused) clock reg was perhaps? just an idea

I believe EXA uses this technique too, this apparently helps with lower asynchronous mode DPLL bandwidth stability and has something to do with the star grounding, which if we are honest does seem to be a bit of a sticky point with the ESS dacs yes? they seem more easily disturbed by ripple on ground and their digital supply than you would think (only apparent when shooting for lowest DPLL, not 'best' defaults

alternatively a you could also reinforce the ground connection between the boards, with buss bar or something, though you would preferably use some way that didnt negate the vibrational decoupling.

Not that with the high clock speeds the fifo needs much help there and with sync mode its not really relevant, maybe worth some playtime though, if there is any possible way to discern the difference.

Acko, I know AKT is probably mostly aimed at the higher grade ESS chips. I have worked out a nice integration technique for the AKD23P though.

Ian's FIFO board has a silence output on J13, this is active high, so will need to be run through an inverter then to the general purpose isolator on its way to the MuteB pin on the ES9023. This will hopefully allow DAC noises and any noise during XO selection to be suppressed.

For the cost of a TTL inverter I think this would be pretty nice to have for the extra polish.

My AKD23P makes almost no noises during turn on in my current system, I'm not sure of it's behaviour with the FIFO though (waiting on next GB) so this isn't a problem per se but since Ian's already done the hard work, it would make sense for it to be used, right?

Thanks Qusp, points noted.
I have got the latest manuals and boards from Ian also. The Clock board is marked DoublerateDualClock with FW3.3. At first blush showing up to 352KHz only. Cannot seem to find the 384KHz rates. Not trying to be pedantic but I have plans to tap all these bits and direct them to an I2C comms chip on my upcoming SuperTrans module so that the Controller (AKC12) or Arduino can read them. As pointed out by GLT, in Sync mode the Sabre DAC gets disorientated trying to figure out sample rates by itself, so getting it direct from transport is the way to go.

Ian's FIFO board has a silence output on J13, this is active high, so will need to be run through an inverter then to the general purpose isolator on its way to the MuteB pin on the ES9023. This will hopefully allow DAC noises and any noise during XO selection to be suppressed.
For the cost of a TTL inverter I think this would be pretty nice to have for the extra polish.
Chris

It would a good thing to do for overall mute. Possibly simpler to kludge an open collector BJT (straddle the mute header of the AKD23)