I am trying to add RTL(Right-to-left) for my ASP.NET MVC4 with Kendo UI Q3 2014. I followed exactly the same in demos at http://demos.telerik.com/aspnet-mvc/maskedtextbox/right-to-left-support but it ...

I am trying to support RTL in my app but when I use android:supportsRtl="true" it is enable for all RTL languages.
But I am unable to support all of them.
For instance I don't support Arabic at the ...

I want to improve the operating frequency of my design, In the register to register timing analysis I have observed a lot of delay in the combinational elements. This is impacting the timing of the ...

I have a parameterized verilog module with a bitwidth that is variable depending on the value given in `define WIDTH.
However, I would like to be able to somehow change the value of WIDTH by passing ...

This might seem like a very naive question, but I have just started working with Verilog (I use Xilinx ISE, if that helps).
I am trying to implement a shift register that shifts input PI by the value ...

I have put images in
drawable-ldrtl-xxhdpi,
drawable-ldrtl-xhdpi,
drawable-ldrtl-hdpi,
drawable-ldrtl-mdpi
nexus Android 4.4 devices are picking images from this folder when language is arabic.
But ...

Is there any way to make default direction of hole css file to rtl instead of ltr, if not is there any tool that insert 'direction:rtl' in each css tags . Actually my css file have 20000 lines of code ...

How are signals/ports of peripheral in a microcontroller connected to the PAD ??
Say, my SoC has 'n' signals. then these 'n' signals will be connected to pad and then reach the top-level. How is this ...

I have some VHDL where a generic is the same name as a constant in an imported package. NCSIM seems to use the value of the constant from the package over the generic.
Rather than rename the generic ...

I want to write a module for GCD computing, using extended Euclidean algorithm. But the main problem is that I completely don't know how to do that without getting to the lowest (RTL) level. What I ...

I've a UVM test env where both golden C++ model and RTL are instantiated. In some cases my C++ model and RTL outputs will go out of order as C++ model is not cycle accurate. For in-order outputs, I ...

I am designing an RTL in verilog for LZSS Algorithm. I have a working code of for this algorithm in verilog. This code is pretty much written in C++ style in verilog. It runs and all looks good.
Now ...

I'm currently working in a project where I must take a Fibonacci algorithm high level description (C) and transform it in a RTL module written in VHDL. To do so, one would need to transform such high ...

I'm learning verilog, and when i don't know how a circuit will work just looking in the verilog code, I go to RTL viewer to see the digital logic. But in this code a strange component appears and I ...

I am writing a systemverilog cover group for my VHDL IP. My plan is to write a separate SV code where I assume that I have access to the internal signals of my VHDL ip. Afterwards, I will just do a ...

I am synthesizing some multiplication units in verilog and I was wondering if you generally get better results in terms of area/power savings if you implement your own CSA using booth encoding when ...

I want to create a program to parse Verilog and display a block diagram. Can someone help me regarding what algorithms I need to look into? I found a good Verilog parser, but now I need to find the ...

I've written a module in Verilog using vi as my editor and now I want to test it.
What are my options if I have no board?
How can I give my module inputs? Where can I see the results?
I have access to ...

Hi and thanks for seeing this.
I was pondering over the idea of an inactivity killswitch for SystemVerilog simulation.
Is there a way in which a prolonged (programmable) duration of inactivity when ...