G06T5/00—Image enhancement or restoration, e.g. from bit-mapped to bit-mapped creating a similar image

G06T5/006—Geometric correction

H—ELECTRICITY

H04—ELECTRIC COMMUNICATION TECHNIQUE

H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION

H04N9/00—Details of colour television systems

H04N9/04—Picture signal generators

H04N9/045—Picture signal generators using solid-state devices

Abstract

Systems and methods for correcting geometric distortion are provided. In one example, an electronic device may include an imaging device, which may obtain image data of a first resolution, and geometric distortion and scaling logic. The imaging device may include a sensor and a lens that causes some geometric distortion in the image data. The geometric distortion correction and scaling logic may scale and correct for geometric distortion in the image data by determining first pixel coordinates in uncorrected or partially corrected image data that, when resampled, would produce corrected output image data at second pixel coordinates. The geometric distortion correction and scaling logic may resample pixels around the image data at the first pixel coordinates to obtain the corrected output image data at the second pixel coordinates. The corrected output image data may be of a second resolution.

This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present techniques, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.

Digital imaging devices appear in handheld devices, computers, digital cameras, and a variety of other electronic devices. Once a digital imaging device acquires an image, an image processing pipeline may apply a number of image processing operations to generate a full color, processed image. Although conventional image processing techniques aim to produce a polished image, these techniques may not adequately address many image distortions and errors introduced by components of the imaging device. For example, defective pixels on the image sensor may produce image artifacts. Lens imperfections may produce an image with non-uniform light intensity. Sensor imperfections arising during manufacture may produce specific patterns of noise on different sensors. Furthermore, sensors from different vendors may reproduce color in perceptibly different ways.

Some conventional image processing techniques may also be relatively inefficient. In one example, certain operational blocks may spread distortions and errors to other areas of the image. In another example, lookup tables may be repeatedly loaded into local buffers from memory to process new image frames from different imaging devices. In addition, many conventional image processing techniques may cause image information to be lost during certain operations. For example, some operations may cause a pixel to be gained beyond a level that can be tracked in conventional image signal processors, resulting in an image with at least some pixels that have been arbitrarily clipped. Other operations may inaccurately reproduce some colors when one of the color channels has reached a maximum intensity. Still others may cause black level noise—noise occurring even when no light reaches the sensor—to be misconstrued as noise occurring only in a positive direction, producing gray-tinged black regions that should be completely black. Moreover, in some situations, images with high global contrast may have image information lost in shadows or obscured by highlights when global contrast operations are performed.

Other conventional image processing techniques may include image demosaicing and sharpening. Conventional demosaicing techniques, however, may not adequately account for the locations and direction of edges within the image, resulting in edge artifacts such as aliasing, checkerboard artifacts, or rainbow artifacts. Similarly, conventional sharpening techniques may not adequately account for existing noise in the image signal, or may be unable to distinguish the noise from edges and textured areas in the image.

SUMMARY

A summary of certain embodiments disclosed herein is set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of these certain embodiments and that these aspects are not intended to limit the scope of this disclosure. Indeed, this disclosure may encompass a variety of aspects that may not be set forth below.

Systems and methods for correcting geometric distortion are provided. In one example, an electronic device may include an imaging device, which may obtain image data of a first resolution, and geometric distortion and scaling logic. The imaging device may include a sensor and a lens that causes some geometric distortion in the image data. The geometric distortion correction and scaling logic may scale and correct for geometric distortion in the image data by determining first pixel coordinates in uncorrected or partially corrected image data that, when resampled, would produce corrected output image data at second pixel coordinates. The geometric distortion correction and scaling logic may resample pixels around the image data at the first pixel coordinates to obtain the corrected output image data at the second pixel coordinates. The corrected output image data may be of a second resolution.

Various refinements of the features noted above may exist in relation to various aspects of the present disclosure. Further features may also be incorporated in these various aspects as well. These refinements and additional features may exist individually or in any combination. For instance, various features discussed below in relation to one or more of the illustrated embodiments may be incorporated into any of the above-described aspects of the present disclosure alone or in any combination. The brief summary presented above is intended only to familiarize the reader with certain aspects and contexts of embodiments of the present disclosure without limitation to the claimed subject matter.

BRIEF DESCRIPTION OF THE DRAWINGS

The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawings will be provided by the Office upon request and payment of the necessary fee.

Various aspects of this disclosure may be better understood upon reading the following detailed description and upon reference to the drawings in which:

FIG. 1 is a simplified block diagram of components of an electronic device with imaging device(s) and image processing circuitry that may perform image processing, in accordance with an embodiment;

FIG. 2 shows a graphical representation of a 2×2 pixel block of a Bayer color filter array that may be implemented in the imaging device of FIG. 1;

FIG. 3 is a perspective view of the electronic device of FIG. 1 in the form of a notebook computing device, in accordance with an embodiment;

FIG. 4 is a front view of the electronic device of FIG. 1 in the form of a desktop computing device, in accordance with an embodiment;

FIG. 5 is a front view of the electronic device of FIG. 1 in the form of a handheld portable electronic device, in accordance with an embodiment;

FIG. 6 is a back view of the electronic device shown in FIG. 5;

FIG. 7 is a block diagram of the image processing circuitry and imaging device(s) of FIG. 1, in accordance with an embodiment;

FIG. 8 is a block diagram of an example of the image processing circuitry of FIG. 1, including statistics logic, a raw-format processing block, an RGB-format processing block, and a YCC-format processing block, in accordance with an embodiment;

FIG. 9 is flowchart depicting a method for processing image data in the ISP pipe processing logic 80 logic of FIG. 10, in accordance with an embodiment;

FIG. 10 is block diagram illustrating a configuration of double buffered registers and control registers that may be used for processing image data in the ISP pipe processing logic 80 logic, in accordance with an embodiment;

FIGS. 11-13 are timing diagrams depicting different modes for triggering the processing of an image frame, in accordance with an embodiment;

FIGS. 14 and 15 are diagrams depicting control registers in more detail, in accordance with an embodiment;

FIG. 16 is a flowchart depicting a method for using a front-end pixel processing unit to process image frames when the ISP pipe processing logic 80 logic of FIG. 10 is operating in a single sensor mode;

FIG. 17 is a flowchart depicting a method for using a front-end pixel processing unit to process image frames when the ISP pipe processing logic 80 logic of FIG. 10 is operating in a dual sensor mode;

FIG. 18 is a flowchart depicting a method for using a front-end pixel processing unit to process image frames when the ISP pipe processing logic 80 logic of FIG. 10 is operating in a dual sensor mode;

FIG. 19 is a flowchart depicting a method in which both image sensors are active, but wherein a first image sensor is sending image frames to a front-end pixel processing unit, while the second image sensor is sending image frames to a statistics processing unit so that imaging statistics for the second sensor are immediately available when the second image sensor continues sending image frames to the front-end pixel processing unit at a later time, in accordance with an embodiment.

FIG. 20 is a graphical depiction of a linear memory addressing format that may be applied to pixel formats stored in a memory of the electronic device of FIG. 1, in accordance with an embodiment;

FIG. 21 is graphical depiction of various imaging regions that may be defined within a source image frame captured by an image sensor, in accordance with an embodiment;

FIG. 22 is a graphical depiction of a technique for using the ISP pipe processing logic 80 processing unit to process overlapping vertical stripes of an image frame;

FIG. 23 is a diagram depicting how byte swapping may be applied to incoming image pixel data from memory using a swap code, in accordance with an embodiment;

FIG. 24 shows an example of how to determine a frame location in memory in a linear addressing format, in accordance with an embodiment;

FIGS. 25-28 show examples of memory formats for raw image data that may be supported by the image processing circuitry of FIG. 7 or FIG. 8, in accordance with an embodiment;

FIGS. 29-34 show examples of memory formats for full-color RGB image data that may be supported by the image processing circuitry of FIG. 7 or FIG. 8, in accordance with an embodiment;

FIGS. 35-39 show examples of memory formats for luma/chroma image data (YUV/YC1C2) that may be supported by the image processing circuitry of FIG. 7 or FIG. 8, in accordance with an embodiment;

FIG. 40 is a flowchart describing a method for processing image data using signed image data, in accordance with an embodiment;

FIG. 41 is a schematic illustration of scaling pixels of various bit-depths to a common unsigned 16-bit format, in accordance with an embodiment;

FIG. 42 is a flowchart describing embodiments of a method for converting unsigned 16-bit pixels into signed 17-bit pixels for processing using the ISP pipe processing logic of FIG. 8, in accordance with an embodiment;

FIG. 43 is a flowchart describing embodiments of a method for converting signed 17-bit pixels from the ISP pipe processing logic of FIG. 8 into 16-bit pixels for storage in memory, in accordance with an embodiment;

FIG. 44 is a block diagram of the ISP circuitry of FIG. 8 depicting how overflow handling may be performed, in accordance with an embodiment;

FIG. 45 is a flowchart depicting a method for overflow handling when an overflow condition occurs while image pixel data is being read from picture memory, in accordance with an embodiment;

FIG. 46 is a flowchart depicting a method for overflow handling when an overflow condition occurs while image pixel data is being read in from an image sensor interface, in accordance with an embodiment;

FIG. 47 is a flowchart depicting another method for overflow handling when an overflow condition occurs while image pixel data is being read in from an image sensor interface, in accordance with an embodiment;

FIG. 48 is more a more detailed block diagram showing embodiments of statistics processing logic that may be implemented in the ISP pipe processing logic, as shown in FIG. 8, in accordance with an embodiment;

FIG. 49 is a block diagram of sensor linearization logic that may be employed by the statistics processing logic of the ISP pipe processing logic, in accordance with an embodiment;

FIG. 50 is a block diagram illustrating sensor linearization lookup tables (LUTs) employed by the sensor linearization logic, in accordance with an embodiment;

FIG. 51 is a flowchart describing a method for linearizing image data from a sensor using the sensor linearization logic, in accordance with an embodiment;

FIG. 52 shows various image frame boundary cases that may be considered when applying techniques for detecting and correcting defective pixels during statistics processing by the statistics processing unit of FIG. 48, in accordance with an embodiment;

FIG. 53 is a flowchart illustrating a process for performing defective pixel detection and correction during statistics processing, in accordance with an embodiment;

FIG. 54 shows a three-dimensional profile depicting light intensity versus pixel position for a conventional lens of an imaging device;

FIG. 55 is a colored drawing that exhibits non-uniform light intensity across the image, which may be the result of lens shading irregularities;

FIG. 56 is a graphical illustration of a raw imaging frame that includes a lens shading correction region and a gain grid, in accordance with an embodiment;

FIG. 57 illustrates the interpolation of a gain value for an image pixel enclosed by four bordering grid gain points, in accordance with an embodiment;

FIG. 58 is a flowchart illustrating a process for determining interpolated gain values that may be applied to imaging pixels during a lens shading correction operation, in accordance with an embodiment;

FIG. 59 is a three-dimensional profile depicting interpolated gain values that may be applied to an image that exhibits the light intensity characteristics shown in FIG. 54 when performing lens shading correction, in accordance with an embodiment;

FIG. 60 shows the colored drawing from FIG. 55 that exhibits improved uniformity in light intensity after a lens shading correction operation is applied, in accordance with accordance aspects of the present disclosure;

FIG. 61 graphically illustrates how a radial distance between a current pixel and the center of an image may be calculated and used to determine a radial gain component for lens shading correction, in accordance with an embodiment;

FIG. 62 is a flowchart illustrating a process by which radial gains and interpolated gains from a gain grid are used to determine a total gain that may be applied to imaging pixels during a lens shading correction operation, in accordance with an embodiment;

FIG. 63 is a graph showing white areas and low and high color temperature axes in a color space;

FIG. 64 is a table showing how white balance gains may be configured for various reference illuminant conditions, in accordance with an embodiment;

FIG. 65 is a block diagram showing a statistics collection engine that may be implemented in the ISP pipe processing logic 80 processing logic, in accordance with an embodiment;

FIG. 66 illustrates the down-sampling of raw Bayer RGB data, in accordance with an embodiment;

FIG. 67 depicts a two-dimensional color histogram that may be collected by the statistics collection engine of FIG. 65, in accordance with an embodiment;

FIG. 69 is a more detailed view showing logic for implementing a pixel filter of the statistics collection engine, in accordance with an embodiment;

FIG. 70 is a graphical depiction of how the location of a pixel within a C1-C2 color space may be evaluated based on a pixel condition defined for a pixel filter, in accordance with an embodiment;

FIG. 71 is a graphical depiction of how the location of a pixel within a C1-C2 color space may be evaluated based on a pixel condition defined for a pixel filter, in accordance with another embodiment;

FIG. 72 is a graphical depiction of how the location of a pixel within a C1-C2 color space may be evaluated based on a pixel condition defined for a pixel filter, in accordance with yet a further embodiment;

FIG. 73 is a graph showing how image sensor integration times may be determined to compensate for flicker, in accordance with an embodiment;

FIG. 74 is a detailed block diagram showing logic that may be implemented in the statistics collection engine of FIG. 65 and configured to collect auto-focus statistics in accordance with an embodiment;

FIG. 75 is a graph depicting a technique for performing auto-focus using coarse and fine auto-focus scoring values, in accordance with an embodiment;

FIG. 76 is a flowchart depicting a process for performing auto-focus using coarse and fine auto-focus scoring values, in accordance with an embodiment;

FIGS. 77 and 78 show the decimation of raw Bayer data to obtain a white balanced luma value;

FIG. 79 shows a technique for performing auto-focus using relative auto-focus scoring values for each color component, in accordance with an embodiment;

FIG. 80 is a flowchart depicting a process for calculating fixed pattern noise statistics, in accordance with an embodiment;

FIG. 81 is a flowchart depicting a process for calculating fixed pattern noise statistics by dividing an input image into horizontal strips of the input image, in accordance with an embodiment;

FIG. 82A is a graphical depiction of how fixed pattern noise statistics is accumulated using a diagonal orientation, in accordance with an embodiment;

FIG. 82B is a graphical depiction of how fixed pattern noise statistics is accumulated using a column sum accumulation process within horizontal strips of the input image, in accordance with an embodiment;

FIG. 82C is a graphical depiction of how fixed pattern noise statistics is accumulated using a row sum accumulation process within horizontal strips of the input image, in accordance with an embodiment;

FIG. 83 is a block diagram of local image statistics logic of the statistics logic of the ISP pipe processing logic, which may collect statistics used in local tone mapping and/or highlight recovery, in accordance with an embodiment;

FIGS. 84 and 85 are block diagrams of luminance computation logic of the local image statistics logic, in accordance with an embodiment;

FIG. 86 is a block diagram of thumbnail generation logic of the local image statistics logic, in accordance with an embodiment;

FIG. 87 is a block diagram of local histogram generation logic of the local image statistics logic, in accordance with an embodiment;

FIG. 88 is an illustration of a first memory format for thumbnails generated by the local image statistics logic, in accordance with an embodiment;

FIG. 89 is an illustration of a second memory format for thumbnails generated by the local image statistics logic, in accordance with an embodiment;

FIG. 90 is an illustration of a memory format for local histograms generated by the local image statistics logic, in accordance with an embodiment;

FIG. 91 is a block diagram of a raw processor block and imaging device(s) of FIG. 1, in accordance with an embodiment;

FIG. 92 is an illustration of a memory format for a fixed pattern noise frame generated by the fixed pattern noise reduction (FPNR) logic, in accordance with an embodiment;

FIG. 93 is a flow diagram illustrating a fixed pattern noise reduction process, in accordance with an embodiment;

FIG. 94 is a flow diagram illustrating a fixed pattern noise reduction process using global offsets, in accordance with an embodiment;

FIG. 95 is a flow diagram illustrating an embodiment of a temporal filtering process performed by the raw processor block shown in FIG. 91, in accordance with an embodiment;

FIG. 96 illustrates a set of reference image pixels and a set of corresponding image pixels that may be used to determine one or more parameters for the temporal filtering process of FIG. 95, in accordance with an embodiment;

FIG. 97A and FIG. 97B illustrate two examples of a motion table being divided according to a number of brightness levels that may be used to determine one or more parameters for the temporal filtering process of FIG. 95, in accordance with an embodiment;

FIG. 98 is a flow diagram illustrating a more detailed description of a block in the flow diagram of FIG. 10, in accordance with one embodiment;

FIG. 99 is a process diagram illustrating how temporal filtering may be applied to image pixel data received by the raw processor shown in FIG. 91, in accordance with one embodiment.

FIG. 100 shows various image frame boundary cases that may be considered when applying techniques for detecting and correcting defective pixels during processing by the raw processing block shown in FIG. 91, in accordance with an embodiment;

FIG. 101 shows various pixel correction coefficients that may be considered when applying techniques for detecting and correcting defective pixels during processing by the raw processing block shown in FIG. 91, in accordance with an embodiment;

FIGS. 102-104 are flowcharts that depict various processes for detecting and correcting defective pixels that may be performed in the raw pixel processing block of FIG. 99, in accordance with an embodiment;

FIG. 105 is a flow diagram depicting a process for calculating noise statistics, in accordance with an embodiment;

FIG. 106 shows various gradients that may be considered when applying techniques for calculating noise statistics during processing by the raw processing block shown in FIG. 91, in accordance with an embodiment;

FIG. 107 is an illustration of a memory format for the noise statistics, in accordance with an embodiment;

FIG. 108 is an illustration of a 7×7 block of same-colored pixels on which spatial noise filtering may be applied;

FIG. 109 illustrates a high level process overview of the spatial noise filtering process, in accordance with an embodiment;

FIG. 110 illustrates a process for determining an attenuation factor for each filter tap of the SNF logic;

FIG. 111 is an illustration of a determination of a radial distance as the distance between a center point of an image frame and the current input pixel, in accordance with an embodiment;

FIG. 112 is a flowchart illustrating a process to determine a radial gain to be applied to the inverse noise standard deviation value determined by the attenuation factor determination process, in accordance with an embodiment;

FIG. 113 is a flowchart illustrating a process for determining an interpolated green value for the input pixel, in accordance with an embodiment;

FIG. 114 illustrates an example of how pixel absolute difference values may be determined when the SNF logic operates in a non-local means mode in applying spatial noise filtering to the 7×7 block of pixels of FIG. 108;

FIG. 115 illustrates an example of the SNF logic configured to operate in a three-dimensional mode, in accordance with an embodiment;

FIG. 116 is a flowchart illustrating a process for three-dimensional spatial noise filtering, in accordance with an embodiment;

FIG. 117 is a block diagram illustrating a process path for pixel data in the ISP pipe, in accordance with an embodiment;

FIG. 118 illustrates examples of various combinations of pixels with missing color samples;

FIG. 119 is a flowchart illustrating a process for computing clip levels and normalizing pixel values for a highlight recovery process, in accordance with an embodiment;

FIG. 120 is a flowchart illustrating a highlight recovery process, in accordance with an embodiment;

FIG. 121 is a full resolution sample of Bayer image data;

FIG. 122 is an example of the raw scaler logic applying 2×2 binning to the full resolution raw image data;

FIG. 123 is a re-sampled portion of binned image data after being processed by the raw scaler circuitry;

FIG. 124 is a block diagram of the raw scaler circuitry, in accordance with one embodiment;

FIG. 125 is a graphical depiction of input pixel locations and corresponding output pixel locations based on various DDAStep values;

FIG. 126 is a flow chart depicting a method for applying binning compensation filtering to image data received by the front-end pixel processing unit 130 in accordance with an embodiment;

FIG. 127 is a flow chart depicting the step for determining currPixel from the method of FIG. 126, in accordance with one embodiment;

FIG. 128 is the step for determining currIndex from the method of FIG. 126, in accordance with one embodiment;

FIG. 129 is an illustration of typical distortion curves for red, green, and blue color channels;

FIG. 130 is an illustration of a 1920×1080 resolution RAW frame that simulates the lens distortion of FIG. 129

FIG. 131 is an image, illustrating the results of applying demosaic logic to a frame with chromatic aberrations;

FIG. 132 is a graph illustrating the relative distortion for chromatic aberration correction;

FIG. 133 is a simulated image where chromatic aberrations are removed prior to demosaicing the image;

FIG. 134 is a block diagram of the raw scaler circuitry 1652, in accordance with an embodiment;

FIG. 135 is a block diagram illustrating the vertical resampler coordinate generator, in accordance with an embodiment;

FIG. 136 is a block diagram illustrating the vertical displacement computation, in accordance with an embodiment;

FIG. 137 is a block diagram illustrating the vertical sensor to component coordinate translation logic, in accordance with an embodiment;

FIG. 138 is an illustration of the green output samples aligning with the green input samples since there is no vertical scaling or binning compensation;

FIG. 139 is a diagram illustrating that if the Chromatic Aberration were a linear function of the radius, the offsets between red and green and between blue and green would be constant for each output line, but decreasing to zero near the vertical center of the frame;

FIG. 140 is a chart depicting vertical offsets from the green channel;

FIG. 141 is a block diagram illustrating one embodiment of the horizontal resampler coordinate generator, in accordance with an embodiment;

FIG. 142 is a block diagram illustrating the horizontal displacement computation logic, in accordance with an embodiment;

FIG. 143 is a block diagram illustrating the horizontal sensor to component coordinate translation logic, in accordance with an embodiment;

FIG. 144 is a diagram illustrating that since there is no horizontal scaling or binning compensation, the green output samples are aligned with the green input samples;

FIG. 145 is a diagram that illustrates the offset for the blue channel decreasing by 2

FIG. 146 is a diagram that illustrates the maximum offset between the vertical position of the center tap on the red (and blue) component and the corresponding green component;

FIG. 147 is a block diagram of RGB-format processing logic of the ISP pipe processing logic of FIG. 8, in accordance with an embodiment;

FIG. 148 is a graphical process flow that provides a general overview as to how demosaicing may be applied to a raw Bayer image pattern to produce a full color RGB;

FIG. 149 is a diagram that illustrates a 2×2 pixel grid configured in a Bayer CFA pattern, in accordance with an embodiment;

FIG. 150 is a diagram that illustrates the computation of the Eh and Ev values for a red pixel centered in the 5×5 pixel block at location (j, i), wherein j corresponds to a row and i corresponds to a column, in accordance with an embodiment;

FIG. 151 is a diagram that illustrates the computation of Eh and Ev values for a Gr pixel, however, the same filter may be applied on any interpolated red or blue pixel, in accordance with an embodiment;

FIG. 152 is an example of horizontal interpolation for determining Gh, in accordance with one embodiment;

FIG. 153 is five vertical pixels (R0, G1, R2, G3, and R4) of a red column of the Bayer image and their respective filtering coefficients, in accordance with an embodiment;

FIG. 154 is a block diagram illustrating filter coefficients useful for computing the GNU correction amount, in accordance with an embodiment;

FIG. 155 is a block diagram illustrating a definition of local green gradient filters, in accordance with embodiments;

FIG. 156 is a block diagramin illustrating vertical and horizontal red/blue gradient filters, in accordance with an embodiment

FIG. 157 is a diagram that illustrates a summary of the green interpolation on both red and blue pixels;

FIG. 158 is a diagram that illustrates various 3×3 blocks of the Bayer image pattern to which red and blue demosaicing may be applied, as well as interpolated green values (designated by G′) that may have been obtained during demosaicing on the green channel, in accordance with an embodiment;

FIG. 159 is a block diagram that depicts the determination of which color components are to be interpolated for a given input pixel P, in accordance with an embodiment;

FIG. 160 is a flow chart illustrating a process for interpolating a green value, in accordance with an embodiment;

FIG. 161 is a flow chart illustrating a process for interpolating a red value, in accordance with an embodiment;

FIG. 162 is a flow chart illustrating a process for interpolating a blue value, in accordance with an embodiment;

FIG. 163 depicts an example of an original image scene, which may be captured by the image sensor of the imaging device;

FIG. 164 is a raw Bayer image which may represent the raw pixel data captured by the image sensor;

FIG. 165 is an RGB image reconstructed using conventional demosaicing techniques, and may include artifacts, such as “checkerboard” artifacts at the edge;

FIG. 166 is an example of an image reconstructed using the demosaicing techniques, in accordance with an embodiment;

FIG. 167 is a simplified image of a scene with a bright area and a dark area, over which a first global gain has been applied that causes the bright area to be washed out, in accordance with an embodiment;

FIG. 168 is a simplified image of the scene with the bright area and the dark area, over which a second global gain has been applied that causes the dark area to be obscured, in accordance with an embodiment;

FIG. 169 is a simplified tone map of the scene of FIGS. 167 and 168, which relates local gains to the bright area and the dark area to preserve both highlight and dark image information, in accordance with an embodiment;

FIG. 170 is a simplified image of the scene of FIGS. 167 and 168, over which local gains have been applied using the tone map of FIG. 169, thereby preserving both highlight and dark image information, in accordance with an embodiment;

FIG. 171 is a block diagram representing an example of local tone mapping logic of the RGB-format processing logic of FIG. 147, in accordance with an embodiment;

FIG. 172 is a schematic diagram of a local tone map grid of a spatially varying lookup table of the local tone mapping logic of FIG. 171, in accordance with an embodiment;

FIG. 173 is an illustration of 2D interpolation to obtain values from the local tone map grid of FIG. 172, in accordance with an embodiment;

FIG. 174 is a block diagram of gain computation logic of the local tone mapping logic of FIG. 171, in accordance with an embodiment;

FIG. 175 is a plot representing a box function used in the gain computation logic of FIG. 174, in accordance with an embodiment;

FIG. 176 is a diagram of a 9Hx1V group of pixels filtered through a bilateral filter using the box function of FIG. 175, in accordance with an embodiment;

FIG. 177 is a block diagram of pin-to-white logic of the local tone mapping logic of FIG. 171, in accordance with an embodiment;

FIG. 181 is a block diagram of color correction logic using a 3D color lookup table, in accordance with an embodiment;

FIG. 182 is a diagram illustrating tetrahedral interpolation of values in the 3D color lookup table, in accordance with an embodiment;

FIG. 183 is a block diagram of YCC (e.g., YCbCr) processing logic of the ISP pipe processing logic of FIG. 8, in accordance with an embodiment;

FIG. 184 is a block diagram of luma sharpening logic of the YCC processing logic of FIG. 183, in accordance with an embodiment;

FIG. 185 is a block diagram of dot detection logic of the luma sharpening logic of FIG. 184, in accordance with an embodiment;

FIG. 186 is a block diagram of chroma suppression logic of the YCC processing logic of FIG. 183, in accordance with an embodiment;

FIG. 187 is a plot of chroma gain versus a sharp value of luma, which may be used in a lookup table to obtain a first attenuation factor in the chroma suppression logic of FIG. 186, in accordance with an embodiment;

FIG. 188 is a plot of chroma gain versus an unsharp value of luma, which may be used in a lookup table to obtain a second attenuation factor in the chroma suppression logic of FIG. 186, in accordance with an embodiment;

FIG. 189 is a block diagram of brightness, contrast, and color adjustment logic of the YCC processing logic of FIG. 183, in accordance with an embodiment;

FIG. 190 is a block diagram of horizontal chroma decimation logic of the YCC processing logic of FIG. 183, in accordance with an embodiment;

FIG. 191 is a block diagram of a first horizontal filter mode of the horizontal chroma decimation logic of FIG. 190, in accordance with an embodiment;

FIG. 192 is a plot representing a lancsoz filter waveform implemented in the first horizontal filter mode of FIG. 191, in accordance with an embodiment;

FIG. 193 is a block diagram of a second horizontal filter mode of the horizontal chroma decimation logic of FIG. 190, in accordance with an embodiment;

FIG. 194 is a schematic illustration of horizontal chroma decimation using the horizontal chroma decimation logic of FIG. 190, in accordance with an embodiment;

FIG. 195 is a block diagram of a YCC scaler with geometric distortion correction and scaling-formatting functions, in accordance with an embodiment;

FIG. 196 is a flowchart describing a method for geometric distortion correction, in accordance with an embodiment;

FIG. 197 is a plot of a vertical span in total lines of pixels used in a luminance component of the YCC scaler of FIG. 195, in accordance with an embodiment;

FIG. 198 is a plot of a vertical span in total lines of pixels used in a chrominance component of the YCC scaler of FIG. 195, in accordance with an embodiment;

FIG. 199 is a block diagram of a line buffer module of the YCC scaler of FIG. 195, in accordance with an embodiment;

FIG. 204 is a block diagram of an output shifter with a preload buffer used in the YCC scaler of FIG. 195, in accordance with an embodiment;

FIG. 205 is a block diagram of a line buffer controller to control writing in the YCC scaler of FIG. 195, in accordance with an embodiment;

FIG. 206 is a block diagram of vertical luminance coordinate generation logic to determine displacement caused by geometric distortion, in accordance with an embodiment;

FIG. 207 is a block diagram of vertical luminance displacement computation logic of the vertical luminance coordinate generation logic of FIG. 206, in accordance with an embodiment;

FIG. 208 is a block diagram of vertical luminance resampling filter logic of the YCC scaler of FIG. 195, in accordance with an embodiment;

FIG. 209 is a block diagram of horizontal luminance resampling filter logic of the YCC scaler of FIG. 195, in accordance with an embodiment;

FIG. 210 is a block diagram of horizontal chrominance resampling filter logic of the YCC scaler of FIG. 195, in accordance with an embodiment;

FIGS. 211-213 are block diagrams illustrating various processing orders of the YCC scaler logic and chromanoise reduction logic of the YCC processing logic of FIG. 183, in accordance with an embodiment;

FIG. 214 is a block diagram of the chromanoise reduction logic of the YCC processing logic of FIG. 183, in accordance with an embodiment;

FIG. 215 is an example of a 3×3 pixel filter, in accordance with an embodiment;

FIG. 216 is an example of a sparse 5×5 pixel filter enlarged from the 3×3 pixel filter of FIG. 215, in accordance with an embodiment;

FIGS. 217 and 218 represent a flowchart of a method for reducing chromanoise, in accordance with an embodiment; and

FIG. 219 is a flowchart of a method for determining a noise threshold for the method for reducing chromanoise of FIGS. 217 and 218.

FIG. 220 is a block diagram of line buffering used in correcting for geometric distortion, in accordance with an embodiment;

FIG. 221 is a flowchart describing a manner of separably correcting for geometric distortion in vertical and horizontal scalers, in accordance with an embodiment;

FIG. 222 is a block diagram of processing image data in a series of tiles, in accordance with an embodiment;

FIG. 223 is a block diagram of pixel data having a clipped pixel flag, in accordance with an embodiment;

FIG. 224 is an example image having a column offset fixed pattern noise, in accordance with an embodiment;

FIG. 225 is an example image after applying a column offset fixed pattern noise correction, in accordance with an embodiment;

FIG. 226 is an example image after with low frequency portions of image data and high frequency portions of image data, in accordance with an embodiment;

FIG. 227 is graph of noise statistics as represented by a plot of standard deviations for portions of image data versus pixel intensity values, in accordance with an embodiment;

FIG. 228 is an example image that has been corrected for geometric distortion, in accordance with an embodiment; and

FIG. 229 is an example of signed image data biasing throughout the raw processing logic of the image pipe processing logic, in accordance with an embodiment.

DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS

One or more specific embodiments of the present disclosure will be described below. These described embodiments are only examples of the presently disclosed techniques. Additionally, in an effort to provide a concise description of these embodiments, all features of an actual implementation may not be described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions may be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.

When introducing elements of various embodiments of the present disclosure, the articles “a,” “an,” and “the” are intended to mean that there are one or more of the elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that references to “one embodiment” or “embodiments” of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features.

Acquired image data may undergo significant processing before appearing as a finished image. Accordingly, the disclosure below will describe image processing circuitry that can efficiently process image data. Statistics logic of the image processing circuitry may obtain statistics associated with an image in raw format in parallel with other image data processing. A raw-format processing block may also process the raw image data, using the statistics to correct fixed pattern noise, defective pixels, recover highlights lost by the sensor, and/or perform other operations. An RGB-format processing block may employ a more efficient organization, better demosaicing, improved local tone mapping, and/or color correction to correct colors from image data from more than one sensor vendor. A YCC-format processing block may similarly offer a more efficient organization, as well as improved sharpening, geometric distortion correction, and chromanoise reduction. Moreover, many operations may be performed using signed, rather than unsigned, pixel data. Using signed pixel data may preserve image data when operations produce interim negative pixel results, as well when a sensor produces black level noise in the negative direction.

With this in mind, FIG. 1 is a block diagram illustrating an example of an electronic device 10 that may process image data using one or more of the image processing techniques briefly mentioned above. The electronic device 10 may be any suitable electronic device, such as a laptop or desktop computer, a mobile phone, a digital media player, or the like, that can receive and process image data. By way of example, the electronic device 10 may be a portable electronic device, such as a model of an iPod® or iPhone®, available from Apple Inc. of Cupertino, Calif. The electronic device 10 may be a desktop or notebook computer, such as a model of a MacBook®, MacBook® Pro, MacBook Air®, iMac®, Mac® Mini, or Mac Pro®, available from Apple Inc. In other embodiments, electronic device 10 may be a model of an electronic device from another manufacturer that is capable of acquiring and processing image data.

Regardless of form, the electronic device 10 may process image data using one or more of the image processing techniques presented in this disclosure. The electronic device 10 may include or operate on image data from one or more imaging devices, such as an integrated or external digital camera. Certain specific examples of the electronic device 10 will be discussed below with reference to FIGS. 3-6.

As shown in FIG. 1, the electronic device 10 may include various components. The functional blocks shown in FIG. 1 may represent hardware elements (including circuitry), software elements (including code stored on a computer-readable medium) or a combination of both hardware and software elements. In the example of FIG. 1, the electronic device 10 includes input/output (I/O) ports 12, input structures 14, one or more processors 16, a memory 18, nonvolatile storage 20, a temperature sensor 22, networking device 24, power source 26, display 28, one or more imaging devices 30, and image processing circuitry 32. It should be appreciated, however, that the components illustrated in FIG. 1 are provided only as an example. Other embodiments of the electronic device 10 may include more or fewer components. To provide one example, some embodiments of the electronic device 10 may not include the imaging device(s) 30. In any case, the image processing circuitry 32 may implement one or more of the image processing techniques discussed below. The image processing circuitry 32 may receive image data for image processing from the memory 18, the nonvolatile storage device(s) 20, the imaging device(s) 30, or any other suitable source.

Before continuing further, the reader should note that the system block diagram of the device 10 shown in FIG. 1 is intended to be a high-level control diagram depicting various components that may be included in such a device 10. That is, the connection lines between each individual component shown in FIG. 1 may not necessarily represent paths or directions through which data flows or is transmitted between various components of the device 10. Indeed, as discussed below, the depicted processor(s) 16 may, in some embodiments, include multiple processors, such as a main processor (e.g., CPU), and dedicated image and/or video processors. In such embodiments, the processing of image data may be primarily handled by these dedicated processors, thus effectively offloading such tasks from a main processor (CPU). In addition, the image processing circuitry 32 may communicate with the memory 18 directly via a direct memory access (DMA) bus.

Considering each of the components of FIG. 1, the I/O ports 12 may represent ports to connect to a variety of devices, such as a power source, an audio output device, or other electronic devices. For example, the I/O ports 12 may connect to an external imaging device, such as a digital camera, to acquire image data to be processed in the image processing circuitry 32. The input structures 14 may enable user input to the electronic device, and may include hardware keys, a touch-sensitive element of the display 28, and/or a microphone.

The processor(s) 16 may control the general operation of the device 10. For instance, the processor(s) 16 may execute an operating system, programs, user and application interfaces, and other functions of the electronic device 10. The processor(s) 16 may include one or more microprocessors and/or application-specific microprocessors (ASICs), or a combination of such processing components. For example, the processor(s) 16 may include one or more instruction set (e.g., RISC) processors, as well as graphics processors (GPU), video processors, audio processors and/or related chip sets. As may be appreciated, the processor(s) 16 may be coupled to one or more data buses for transferring data and instructions between various components of the device 10. In certain embodiments, the processor(s) 16 may provide the processing capability to execute an imaging applications on the electronic device 10, such as Photo Booth®, Aperture®, iPhoto®, Preview®, iMovie®, or Final Cut Pro® available from Apple Inc., or the “Camera” and/or “Photo” applications provided by Apple Inc. and available on some models of the iPhone®, iPod®, and iPad®.

A computer-readable medium, such as the memory 18 or the nonvolatile storage 20, may store the instructions or data to be processed by the processor(s) 16. The memory 18 may include any suitable memory device, such as random access memory (RAM) or read only memory (ROM). The nonvolatile storage 20 may include flash memory, a hard drive, or any other optical, magnetic, and/or solid-state storage media. The memory 18 and/or the nonvolatile storage 20 may store firmware, data files, image data, software programs and applications, and so forth. Such digital information may be used in image processing to control or supplement the image processing circuitry 32.

In some examples of the electronic device 10, the temperature sensor 22 may indicate a temperature associated with the imaging device(s) 30. Since fixed pattern noise may be exacerbated by higher temperatures, the image processing circuitry 32 may vary certain operations to remove fixed pattern noise depending on the temperature. The network device 24 may be a network controller or a network interface card (NIC), and may enable network communication over a local area network (LAN) (e.g., Wi-Fi), a personal area network (e.g., Bluetooth), and/or a wide area network (WAN) (e.g., a 3G or 4G data network). The power source 26 of the device 10 may include a Li-ion battery and/or a power supply unit (PSU) to draw power from an electrical outlet. The display 28 may display various images generated by device 10, such as a GUI for an operating system or image data (including still images and video data) processed by the image processing circuitry 32. The display 28 may be any suitable type of display, such as a liquid crystal display (LCD), plasma display, or an organic light emitting diode (OLED) display, for example. Additionally, as mentioned above, the display 28 may include a touch-sensitive element that may represent an input structure 14 of the electronic device 10.

The imaging device(s) 30 of the electronic device 10 may represent a digital camera that may acquire both still images and video. Each imaging device 30 may include a lens and an image sensor capture and convert light into electrical signals. By way of example, the image sensor may include a CMOS image sensor (e.g., a CMOS active-pixel sensor (APS)) or a CCD (charge-coupled device) sensor. Generally, the image sensor of the imaging device 30 includes an integrated circuit with an array of photodetectors. The array of photodetectors may detect the intensity of light captured at specific locations on the sensor. Photodetectors are generally only able to capture intensity, however, and may not detect the particular wavelength of the captured light.

Accordingly, the image sensor may include a color filter array (CFA) that may overlay the pixel array of the image sensor to capture color information. The color filter array may include an array of small color filters, each of which may overlap a respective location—namely, a picture element, or pixel—of the image sensor and filter the captured light by wavelength. Thus, together, the color filter array and the photodetectors may detect both the wavelength and intensity of light through the lens. The resulting image information may represent a frame of raw image data.

The color filter array may be a Bayer color filter array, an example of which appears in FIG. 2. A Bayer color filter array provides a filter pattern that captures 50% green elements, 25% red elements, and 25% blue elements of light reaching the sensor. In the example of FIG. 2, 2 green elements (Gr and Gb), 1 red element (R), and 1 blue element (B) will repeat in the pattern shown across the full pixel array of the sensor(s) of the imaging device(s) 30. Thus, an image sensor with a Bayer color filter array may provide information regarding the intensity of the light received by the imaging device 30 at the green, red, and blue wavelengths, whereby each image pixel records only one of the three colors (RGB). This information, which may be referred to as “raw image data” or data in the “raw domain,” may be processed using one or more demosaicing techniques to convert the raw image data into a full color image, generally by interpolating a set of red, green, and blue values for each pixel. As will be discussed further below, such demosaicing techniques may be performed by the image processing circuitry 32.

The image processing circuitry 32 may provide many other image processing steps, as well, including defective pixel detection and correction, fixed pattern noise reduction, lens shading correction, image sharpening, noise reduction, gamma correction, image enhancement, color-space conversion, image compression, chroma subsampling, local tone mapping, chroma noise reduction, image scaling operations, and so forth. In some embodiments, the image processing circuitry 32 may include various subcomponents and/or discrete units of logic that collectively form an image processing “pipeline” for performing each of the various image processing steps. These subcomponents may be implemented using hardware (e.g., digital signal processors or ASICs) or software, or via a combination of hardware and software components. The various image processing operations that may be provided by the image processing circuitry 32 will be discussed in greater detail below.

Before continuing, it should be noted that while various embodiments of the various image processing techniques discussed below may use a Bayer CFA, the presently disclosed techniques are not intended to be limited in this regard. Indeed, those skilled in the art will appreciate that the image processing techniques provided herein may be applicable to any suitable type of color filter array, including RGBW filters, CYGM filters, and so forth.

Regardless of the particular filter employed by the sensor of the imaging device(s) 30, the electronic device 10 may take any number of suitable forms. Some examples of these possible forms appear in FIGS. 3-6. Turning to FIG. 3, a notebook computer 40 may include a housing 42, the display 28, the I/O ports 12, and the input structures 14. The input structures 14 may include a keyboard and a touchpad mouse that are integrated with the housing 42. Additionally, the input structure 14 may include various other buttons and/or switches which may be used to interact with the computer 40, such as to power on or start the computer, to operate a GUI or an application running on the computer 40, as well as adjust various other aspects relating to operation of the computer 40 (e.g., sound volume, display brightness, etc.). The computer 40 may also include various I/O ports 12 that provide for connectivity to additional devices, as discussed above, such as a FireWire® or USB port, a high definition multimedia interface (HDMI) port, or any other type of port that is suitable for connecting to an external device. Additionally, the computer 40 may include network connectivity (e.g., network device 26), memory (e.g., memory 20), and storage capabilities (e.g., storage device 22), as described above with respect to FIG. 1.

The notebook computer 40 may include an integrated imaging device 30 (e.g., a camera). In other embodiments, the notebook computer 40 may use an external camera (e.g., an external USB camera or a “webcam”) connected to one or more of the I/O ports 12 instead of or in addition to the integrated imaging device 30. For instance, an external camera may be an iSight® camera available from Apple Inc. Images captured by the imaging device 30 may be viewed by a user using an image viewing application, or may be used by other applications, including video-conferencing applications, such as iChat®, and image editing/viewing applications, such as Photo Booth®, Aperture®, iPhoto®, or Preview®, which are available from Apple Inc. In certain embodiments, the depicted notebook computer 40 may be a model of a MacBook®, MacBook® Pro, MacBook Air®, or PowerBook® available from Apple Inc. In other embodiments, the computer 40 may be portable tablet computing device, such as a model of an iPad® from Apple Inc.

FIG. 4 shows the electronic device 10 in the form of a desktop computer 50. The desktop computer 50 may include a number of features that may be generally similar to those provided by the notebook computer 40 shown in FIG. 4, but may have a generally larger overall form factor. As shown, the desktop computer 50 may be housed in an enclosure 42 that includes the display 28, as well as various other components discussed above with regard to the block diagram shown in FIG. 1. Further, the desktop computer 50 may include an external keyboard and mouse (input structures 14) that may be coupled to the computer 50 via one or more I/O ports 12 (e.g., USB) or may communicate with the computer 50 wirelessly (e.g., RF, Bluetooth, etc.). The desktop computer 50 also includes an imaging device 30, which may be an integrated or external camera, as discussed above. In certain embodiments, the depicted desktop computer 50 may be a model of an iMac®, Mac® mini, or Mac Pro®, available from Apple Inc.

The electronic device 10 may also take the form of portable handheld device 60, as shown in FIGS. 5 and 6. By way of example, the handheld device 60 may be a model of an iPod® or iPhone® available from Apple Inc. The handheld device 60 includes an enclosure 42, which may function to protect the interior components from physical damage and to shield them from electromagnetic interference. The enclosure 42 also includes various user input structures 14 through which a user may interface with the handheld device 60. Each input structure 14 may control various device functions when pressed or actuated. As shown in FIG. 5, the handheld device 60 may also include various I/O ports 12. For instance, the depicted I/O ports 12 may include a proprietary connection port 12a for transmitting and receiving data files or for charging a power source 26 and an audio connection port 12b for connecting the device 60 to an audio output device (e.g., headphones or speakers). Further, in embodiments where the handheld device 60 provides mobile phone functionality, the device 60 may include an I/O port 12c for receiving a subscriber identify module (SIM) card.

The display device 28 may display images generated by the handheld device 60. For example, the display 28 may display system indicators 64 that may indicate device power status, signal strength, external device connections, and so forth. The display 28 may also display a GUI 52 that allows a user to interact with the device 60, as discussed above with reference to FIG. 4. The GUI 52 may include graphical elements, such as the icons 54 which may correspond to various applications that may be opened or executed upon detecting a user selection of a respective icon 54. By way of example, one of the icons 54 may represent a camera application 66 that may allow a user to operate an imaging device 30 (shown in phantom lines in FIG. 5). Referring briefly to FIG. 6, a rear view of the handheld electronic device 60 depicted in FIG. 5 is illustrated, which shows the imaging device 30 integrated with the housing 42 and positioned on the rear of the handheld device 60.

As mentioned above, image data acquired using the imaging device 30 or elsewhere may be processed using the image processing circuitry 32, which may include hardware (e.g., disposed within the enclosure 42) and/or software stored on one or more storage devices (e.g., memory 18 or nonvolatile storage 20) of the device 60. Images acquired using the camera application 66 and the imaging device 30 may be stored on the device 60 (e.g., in the nonvolatile storage 20) and may be viewed at a later time using a photo viewing application 68.

The handheld device 60 may also include various audio input and output elements. For example, the audio input/output elements, depicted generally by reference numeral 70, may include an input receiver, such as one or more microphones. The audio input/output elements 70 may include one or more output transmitters. Such output transmitters may include one or more speakers that may output sound from a media player application 72. In some embodiments (e.g., those in which the handheld device 60 includes a cell phone application), an additional audio output transmitter 74 may be provided, as shown in FIG. 5. Like the output transmitters of the audio input/output elements 70, the output transmitter 74 may also include one or more speakers to transmit audio signals to a user, such as voice data received during a telephone call.

Having provided some context with regard to possible forms that the electronic device 10 may take, the present discussion will now focus on the image processing circuitry 32 shown in FIG. 1. As mentioned above, the image processing circuitry 32 may be implemented using hardware and/or software components, and may include various processing units that define an image signal processing (ISP) pipeline. First, a general discussion of the operation of the various functional components of image processing circuitry 32 will be provided with reference to FIG. 7. More specific description of the components of the image processing circuitry 32 will be further provided below.

Referring to FIG. 7, the image processing circuitry 32 may include image signal processing (ISP) pipe logic 80, pixel scale and offset logic 82, control logic 84, and a back-end interface 86. To avoid processing image data from the imaging device 30 through some form of front-end image processing before processing the image data in the ISP pipe processing logic 80, the ISP pipe processing logic 80 may include image processing logic that may obtain image statistics in parallel with other image processing logic that may process image data to obtain a final processed image. The image statistics may be used to determine one or more control parameters for the ISP pipe logic 82 and/or the imaging device 30, as well as suitable software that may perform subsequent image processing on the image data.

The ISP pipe processing logic 80 may capture image data from an image sensor input signal. For instance, as shown in FIG. 7, the imaging device 30 may include lens(es) 88 and corresponding image sensor(s) 90. The image sensor(s) 90 may include a color filter array (e.g., a Bayer filter, such as that shown in FIG. 2) to capture both light intensity and wavelength information. This raw image data from the image sensor(s) 90 may be output 92 to a sensor interface 94. The sensor interface 94 may provide the raw image data 96 to the ISP pipe processing logic 80 via the scale and offset logic 82. By way of example, the sensor interface 94 may use a Standard Mobile Imaging Architecture (SMIA) interface or other serial or parallel camera interfaces, or some combination thereof. In certain embodiments, the ISP pipe processing logic 80 may operate within its own clock domain and may provide an asynchronous interface to the sensor interface 94 to support image sensors of different sizes and timing requirements. The sensor interface 94 may include, in some embodiments, a sub-interface on the sensor side (e.g., sensor-side interface) and a sub-interface on the ISP pipe processing logic 80 side, with the sub-interfaces forming the sensor interface 94. The sensor interface 94 may also provide the raw image data (shown as numeral 98) directly to picture memory 100, which may represent part of the memory 18 accessible via direct memory access (DMA).

The raw image data 96 may take any of a number of formats. For instance, each image pixel may have a bit-depth of 8, 10, 12, 14, or 16 bits. Various examples of memory formats showing how pixel data may be stored and addressed in memory are discussed in further detail below. The scale and offset logic 82 may convert the raw image data 96 from the sensor interface 94 into a signed, rather than unsigned, value. Processing the raw image data 96 in a signed format, rather than merely clipping the raw image data 96 to an unsigned format, may preserve image information that would otherwise be lost. To provide a brief example, noise on the image sensor(s) 90 may occur in a positive or negative direction. In other words, some pixels that should represent a particular light intensity may have values of a particular value, others may have noise resulting in values greater than the particular value, and still others may have noise resulting in values less than the particular value. When an area of the image sensor(s) 90 captures little or no light, sensor noise may increase or decrease individual pixel values such that the average pixel value is about zero. If only noise occurring in a negative direction is discarded, however, the average black color could rise above zero and would produce grayish-tinged black areas. Since the ISP pipe processing logic 80 may use signed image data, rather than merely clipping the negative noise away, the ISP pipe processing logic 80 may more accurately render dark black areas in images.

The ISP pipe processing logic 80 may process the raw image data 96 on a pixel-by-pixel basis. The ISP pipe processing logic 80 may perform one or more image processing operations on the raw image data 96 and collect statistics about the image data 96. The ISP pipe processing logic 80 may perform image processing using signed 17-bit data, and may collect statistics in 16-bit or 8-bit precision. In some embodiments, the ISP pipe processing logic 80 may collect statistics at a precision of 8-bits, raw pixel at a higher bit-depth may be down-sampled first to an 8-bit format. As may be appreciated, down-sampling to 8-bits may reduce hardware size (e.g., area) and also reduce processing resources (e.g., power). Collecting statistics in 16-bit precision, however, may produce image statistics both more accurate and more precise.

The ISP pipe processing logic 80 may also receive pixel data from the memory 100. As mentioned above and shown by reference numeral 98, the sensor interface 94 may send raw pixel data from the sensor(s) 90 to the memory 100. The raw pixel data stored in the memory 100 may be provided to the ISP pipe processing logic 80 for processing at another time. When the raw pixel data is provided via the memory 100, the scale and offset logic 82 may convert the raw pixel data to signed 17-bit pixel data 102. Upon receiving the raw image data from the sensor interface 94 or the memory 100, the ISP pipe processing logic 80 may perform various image processing operations, which will be discussed in greater detail below. In addition, the ISP pipe processing logic 80 may transfer signed 17-bit pixel data 102 in various stages of processing back to the memory 100 via the scale and offset logic 82. The ISP pipe processing logic 80 may also transfer and receive certain unsigned image data 104 (e.g., processed image data) to and from the memory 100, as will be discussed further below.

Moreover, throughout image processing, the control logic 84 may control various operations of image processing circuitry 32 (e.g., shifting pixel data into and out of the ISP pipe processing logic 80) via control signals 106. The control logic 84 may also control the operation of the imaging device(s) 30 (e.g., integration time to avoid flicker caused by certain types of interior lighting) via control signals 108. The control logic 84 may rely on statistical data determined by the ISP pipe processing logic 80. Such statistical data may include, for example, image sensor statistics relating to auto-exposure, auto-white balance, auto-focus, flicker detection, black level compensation (BLC), lens shading correction, and so forth. The control logic 84 may include a processor and/or microcontroller configured to execute one or more routines (e.g., firmware) that may determine, based upon the statistical data 102, the control signals 106 and 108. By way of example, the control signals 106 may include gain levels and color correction matrix (CCM) coefficients for auto-white balance and color adjustment (e.g., during RGB processing), as well as lens shading correction parameters which, as discussed below, may be determined based upon white point balance parameters. The control signals 108 may include sensor control parameters (e.g., gains, integration time for exposure control), camera flash control parameters, lens control parameters (e.g., focal length for focusing or zoom), or a combination of such parameters. In some embodiments, the control logic 84 may also analyze historical statistics, which may be stored on the electronic device 10 (e.g., in memory 18 or storage 20).

The ISP pipe processing logic 80 may output processed image data to the memory 100 (e.g., numeral 104) or to the ISP back-end interface 86 (e.g., numeral 110). The ISP back-end interface 86 may alternatively receive image data from the memory 100. In either case, the ISP back-end logic 86 may pass image data to other blocks for post-processing operations. For example, the ISP back-end interface 86 may pass the image data to other logic to detect certain features, such as faces, in the image data. Facial detection data may be fed to statistics processing components of the ISP pipe processing logic 80 as feedback data for auto-white balance, auto-focus, flicker, and auto-exposure statistics, as well as other suitable logic that may benefit from facial detection logic.

In further embodiments, the feature detection logic may also be configured to detect the locations of corners of objects in the image frame. This data may be used to identify the location of features in consecutive image frames in order to determine an estimation of global motion between frames, which may be used to perform certain image processing operations, such as image registration. In one embodiment, the identification of corner features and the like may be particularly useful for algorithms that combine multiple image frames, such as in certain high dynamic range (HDR) imaging algorithms, as well as certain panoramic stitching algorithms.

The ISP back-end interface 86 may output post-processed image data (e.g., numeral 114) to an encoder/decoder 116 to encode the image data. The encoded image data may be stored and then later decoded (e.g., numeral 118) to be displayed on the display 28. By way of example, the compression engine or “encoder” 116 may be a JPEG compression engine for encoding still images, an H.264 compression engine for encoding video images, or any other suitable compression engine, as well as a corresponding decompression engine to decode encoded image data. Additionally or alternatively, the ISP back-end interface 86 may output the post-processed image data (e.g., numeral 120) to the display 28. Additionally or alternatively, output from the ISP pipe processing logic 80 or the ISP back-end interface 86 may be stored in memory 100. The display 28 may read the image data from the memory 100 (e.g., numeral 122).

Overview of the ISP Pipe Processing Logic

A general organization of the ISP pipe processing logic 80 appears in FIG. 8. It should be appreciated that the ISP pipe processing logic 80 may receive image data from one of several different direct memory access (DMA) sources (illustrated as S0-S7) to one of several different DMA destinations (illustrated as D0-D7). A specific discussion about the relationship between each DMA source S0-S7 and destination D0-D7 will appear further below.

As shown in FIG. 8, two sensors 90a and 90b may provide raw image data through respective sensor interfaces 94a (also referred to as Sif0, Sens0, or S0) and 94b (also referred to as Sif1, Sens1, or S1) to input queues 130a and 130b. The sensor interfaces 94a and 94b represent two sources of pixel data that may be supplied to the ISP pipe processing logic 80. Specifically, the sensor interface 94a may be referred to as a source S0 and the sensor interface 94b may be referred to as a source 51. Raw image data from the sensor interface 94a (S0) or the sensor interface 94b (S1) may be stored in the memory 100 (destinations D0 or D1, respectively) or provided directly to the components of the ISP pipe processing logic 80. It should be appreciated that raw image data stored in the memory 100 may be provided to the components of the ISP pipe processing logic 80 at a later time.

Thus, raw image data from the sensor interfaces 94a (S0) or 94b (S1) or from the memory 100 (e.g., via DMA sources S2 or S3) may be transferred to a statistics logic 140a (referred to as a DMA destination D2) or a statistics logic 140b (referred to as a DMA destination D3). The statistics logic 140a and 140b may determine sets of statistics that may relate to auto-exposure, auto-white balance, auto-focus, flicker detection, black level compensation, lens shading correction, local tone mapping and highlight recovery, fixed pattern noise reduction, and so forth. In certain embodiments, when only one of the sensors 90a or 90b is actively acquiring images, the image data may be sent to both the statistics logic 140a and the statistics logic 140b if additional statistics are required. To provide one brief example, if both the statistics logic 140a and the statistics logic 140b are available, the statistics logic 140a may be used to collect statistics for one color space (e.g., RGB), and the statistics logic 140b may be used to collect statistics for another color space (e.g., YCbCr). Thus, if desired, the statistics logic 140a and 140b may operate in parallel to collect multiple sets of statistics for each frame of image data acquired by inactive sensor 90a or 90b.

In the example of FIG. 8, the two statistics logic 140a and 140b are essentially identical. As used herein, the statistics logic 140a may be referred to as StatsPipe0 or DMA destination D2 and the statistics logic 140b may be referred to as StastPipe1 or DMA destination D3. Each may receive image data from one of several sources (S0-S3), as conceptually illustrated by respective selection logic 142a and 142b. The statistics logic 140a and 140b also include respective image processing logic 144a and 144b to process pixel data before reaching a statistics core 146a or 146b. The statistics core 146a or 146b may collect image statistics using the image data processed through the image processing logic 144a or 144b and/or using raw image data that has not been processed by the image processing logic 144a or 144b.

The backend interface block 180 may alternatively receive image data from the memory 100 (conceptually illustrated by a selection logic 182), supplying the image data to a backend interface (BEIF) 184. The ISP pipe processing logic 80 can forward the processed pixel data stream to additional processing logic through the backend interface (BEIF) 184. The backend interface (BEIF) may be a YCbCr4:2:2 10-bit-per-component interface, where Cb and Cr data are interleaved every other luma (Y) sample. The total width of the interface thus may be 20 bits with chroma stored in bits 0-9 and luma stored in bits 10-19 (e.g., Y0Cb0, Y1Cr1, Y2Cb2, Y3Cr3, and so forth). Each pixel sample also may have an associated data valid signal.

As can be seen in FIG. 8, eight asynchronous DMA sources of data (S0-S7) may provide image data to components of the ISP type processing logic 80 to eight DMA destinations (D0-D7). Namely, the sources may include: (S0), a direct input from the sensor interface 94a; (S1), a direct input from the sensor interface 94b; (S2), Sensor0 90a data input or other raw image data from the memory 100; (S3), Sensor1 data input or other raw image data from the memory 100; (S4), raw image data retrieved from the memory 100 (also referred to as RawProcInDMA); (S5), raw image data or RGB-format image data retrieved from the memory 100 (also referred to as RgbProcInDMA); (S6), RGB-format image data retrieved from the memory 100 (also referred to as YccProcInDMA); and (S7), YCC-format image data retrieved from the memory 100 (also referred to as BEIFDMA). The destinations may include: (D0), a DMA destination to the memory 100 for image data obtained by Sensor0 90a (also referred to as Sif0DMA); (D1), a DMA destination in the memory 100 for image data obtained by Sensor1 90b (also referred to as Sif1DMA); (D2), the first statistics logic 140a (also referred to as StatsPipe0); (D3), the second statistics logic 140b (also referred to as StatsPipe1); (D4), a DMA destination to the raw block 150 (also referred to as RAWProc); (D5), the RGB block 160 (also referred to as RgbProc); (D6), the YCC block 170 (also referred to as YCCProc); and (D7), the back-end interface block 180 (also referred to as BEIF). Only certain DMA destinations may be valid for a particular source, as generally shown in Table 1 below:

Thus, for example, image data from Sensor0 90a (S0) may be transferred to destination D0 in the memory 100 (but not destination D1), to the first statistics logic 140a (D2) or the second statistics logic 140b (D3), or to the raw block 150 (D4). By extension, through the raw block 150, the image data from Sensor0 90a (S0) may be provided to the RGB block 160 (D5), the YCC block 170 (D6), or the backend interface block 180 (D7). Similarly, as shown in Table 1, sources S2 and S3 may provide image data to destinations D2, D3, D4, D5, D6, or D7, but not D0 or D1.

The scale and offset logic 82 also appears in FIG. 8. The scale and offset logic 82 may represent any suitable functions to programmably scale and/or offset input pixel data from an unsigned format to a signed format. In particular, in some embodiments, the scale and offset logic 82 represents functions implemented in DMA input and output channels to convert pixel data. Thus, it should be appreciated that the scale and offset logic may or may not convert image data, depending on the input pixel format and/or the format of the image data processed by the individual processing blocks. The operation of the scale and offset logic 82 is described in greater detail below with reference to FIGS. 40-43 below.

It should also be noted that the presently illustrated embodiment may allow the ISP pipe processing logic 80 to retain a certain number of previous frames (e.g., 5 frames) in memory. For example, due to a delay or lag between the time a user initiates a capture event (e.g., transitioning the image system from a preview mode to a capture or a recording mode, or even by just turning on or initializing the image sensor) using the image sensor to when an image scene is captured, not every frame that the user intended to capture may be captured and processed in substantially real-time. Thus, by retaining a certain number of previous frames in memory 100 (e.g., from a preview phase), these previous frames may be processed later or alongside the frames actually captured in response to the capture event, thus compensating for any such lag and providing a more complete set of image data.

A control unit 190 may control the operation of the ISP pipe processing logic 80. The control unit 190 may initialize and program control registers 192 (also referred to as “go registers”) to facilitate processing an image frame and to select appropriate register bank(s) to update double-buffered data registers. In some embodiments, the control unit 190 may also provide memory latency and quality of service (QOS) information. Further, the control unit 190 may also control dynamic clock gating, which may be used to disable clocks to one or more portions of the ISP pipe processing logic 80 when there is not enough data in the input queue 130 from an active sensor.

General Principles of Operation

Using the “go registers” mentioned above, the control unit 190 may control the manner in which various parameters for each of the processing units are updated. Generally, image processing in the ISP pipe processing logic 80 may operate on a frame-by-frame basis. As discussed above with reference to Table 1, the input to the processing units may be from the sensor interface (S0 or S1) or from memory 100 (e.g., S2-S7). Further, the processing units may employ various parameters and configuration data, which may be stored in corresponding data registers. In one embodiment, the data registers associated with each processing unit or destination may be grouped into blocks forming a register bank group. In the example of FIG. 8, several register bank groups may have block address space, certain of which may be duplicated to provide two banks of registers. Only the registers that are double buffered are instantiated in the second bank. If a register is not double buffered, the address in the second bank may be mapped to the address of the same register in the first bank.

For registers that are double buffered, registers from one bank are active and used by the processing units while the registers from the other bank are shadowed. The shadowed register may be updated by the control unit 190 during the current frame interval while hardware is using the active registers. The determination of which bank to use for a particular processing unit at a particular frame may be specified by a “NextDestBk” (next bank) field in a go register corresponding to the source providing the image data to the processing unit. Essentially, NextDestBk is a field that allows the control unit 190 to control which register bank becomes active on a triggering event for the subsequent frame.

Before discussing the operation of the go registers in detail, FIG. 9 provides a general flowchart 200 for processing image data on a frame-by-frame basis in accordance with the present techniques. The flowchart 200 may begin when the destination processing units (e.g., D2-D7) targeted by a data source (e.g., S0-S7) enter an idle state (block 202). This may indicate that processing for the current frame is completed and, therefore, the control unit 190 may prepare for processing the next frame. For instance, programmable parameters for each destination processing unit next may be updated (block 204). This may include, for example, updating the NextDestBk field in the go register corresponding to the source, as well as updating any parameters in the data registers corresponding to the destination units. Thereafter, a triggering event may place the destination units into a run state (block 206). Each destination unit targeted by the source then may complete its processing operations for the current frame (block 208), and the process may flow to block 202 to begin processing the next frame.

FIG. 10 depicts a block diagram view showing two banks of data registers 210 and 212 that may be used by the various destination units of the ISP-front end. For instance, Bank 0 (210) may include the data registers 1−n (210a-210d), and Bank 1 (212) may include the data registers 1−n (212a-212d). As discussed above, the embodiment shown in FIG. 10 may use a register bank (Bank 0) having any suitable number of register bank groups. Thus, in such embodiments, the register block address space of each register is duplicated to provide a second register bank (Bank 1).

FIG. 10 also illustrates go register 214 that may correspond to one of the sources. As shown, the go register 214 includes a “NextDestVld” field 216, the above-mentioned “NextDestBk” field 218, and a “NextSrcBk” field 219. These fields may be programmed before beginning to process the current frame. Particularly, NextDestVld may indicate the destination(s) to where data from the source is to be sent. As discussed above, NextDestBk may indicate a corresponding data register from either Bank0 or Bank1 for each destination targeted, as indicated by NextDestVld. NextSrcBk may indicate the source bank from which to obtain data (Bank0 or Bank1). Though not shown in FIG. 10, the go register 214 may also include an arming bit, referred to herein as a “go bit,” which may be set to arm the go register. When a triggering event 226 for a current frame is detected, NextDestVld, NextDestBk, and NextSrcBk may be copied into a “CurrDestVld” field 222, a “CurrDestBk” field 224, and a “CurrSrcBk” field 225 of a corresponding current or “active” register 220. In one embodiment, the current register(s) 220 may be read-only registers that may set by hardware, while remaining inaccessible to software commands within the ISP pipe processing logic 80.

As may be appreciated, for each DMA source S0-S7, a corresponding go register may be provided. The control unit 190 may use the go registers to control the sequencing of frame processing within the ISP pipe processing logic 80. Each source may be configured to operate asynchronously and can send data to any of its valid destinations. Further, it should be understood that for each destination, generally only one source may be active during a current frame.

With regard to the arming and triggering of the go register 214, asserting an arming bit or “go bit” in the go register 214 arms the corresponding source with the associated NextDestVld and NextDestBk fields. For triggering, various modes are available depending on whether the source input data is read from the memory 100 (e.g., S2-S7) or whether the source input data is from a sensor interface 94 (e.g., S0 or S1). For instance, if the input is from the memory 100, the arming of the go bit itself may serve as the triggering event, since the control unit 190 has control over when data is read from the memory 100. If the image frames are being input by the sensor interface 94, the triggering event may depend on the timing at which the corresponding go register is armed relative to when data from the sensor interface 94 is received. In accordance with the present embodiment, three different techniques for triggering timing from a sensor interface 94 input are shown in FIGS. 11-13.

Referring first to FIG. 11, a first scenario is illustrated in which triggering occurs once all destinations targeted by the source transition from a busy or run state to an idle state. Here, a data signal VVALID (228) represents an image data signal from a source. The pulse 230 represents a current frame of image data, the pulse 236 represents the next frame of image data, and the interval 232 represents a vertical blanking interval (VBLANK) 232 (e.g., represents the time differential between the last line of the current frame 230 and the next frame 236). The time differential between the rising edge and falling edge of the pulse 230 represents a frame interval 234. Thus, in FIG. 11, the source may be configured to trigger when all targeted destinations have finished processing operations on the current frame 230 and transition to an idle state. In this scenario, the source is armed (e.g., by setting the arming or “go” bit) before the destinations complete processing so that the source can trigger and initiate processing of the next frame 236 as soon as the targeted destinations go idle. During the vertical blanking interval 232 the processing units may be set up and configured for the next frame 236 using the register banks specified by the go register corresponding to the source before the sensor input data arrives. By way of example, read buffers used by the ISP pipe processing logic 80 may be filled before the next frame 236 arrives. In this case, shadowed registers corresponding to the active register banks may be updated after the triggering event, thus allowing for a full frame interval to setup the double-buffered registers for the next frame (e.g., after frame 236).

FIG. 12 illustrates a second scenario in which the source is triggered by arming the go bit in the go register corresponding to the source. Under this “trigger-on-go” configuration, the destination units targeted by the source are already idle and the arming of the go bit is the triggering event. This triggering mode may be used for registers that are not double-buffered and, therefore, are updated during vertical blanking (e.g., as opposed to updating a double-buffered shadow register during the frame interval 234).

FIG. 13 illustrates a third triggering mode in which the source is triggered upon detecting the start of the next frame, i.e., a rising VSYNC. However, it should be noted that in this mode, if the go register is armed (by setting the go bit) after the next frame 236 has already started processing, the source will use the target destinations and register banks corresponding to the previous frame, since the CurrDestVld and CurrDestBk fields are not updated before the destination start processing. This leaves no vertical blanking interval for setting up the destination processing units and may potentially result in dropped frames, particularly when operating in a dual sensor mode. It should be noted, however, that this mode may nonetheless result in accurate operation if the image processing circuitry 32 is operating in a single sensor mode that uses the same register banks for each frame (e.g., the destination (NextDestVld) and register banks (NextDestBk) do not change).

Referring now to FIGS. 14 and 16, control registers 214 (a “go register”) and 220 (a “current read-only register”) are respectively illustrated in more detail. The go register 214 includes an arming “go” bit 238, as well as the NextDestVld field 216, the NextDestBk field 218, and the NextSrcBk field 219. The current read-only register 220 includes the CurrDestVld field 222, the CurrDestBk field 224, and the CurrSrcBk field 225. It should be appreciated that the current read-only register 220 represents a read-only register that may indicate the current valid destinations and bank numbers.

As discussed above, each source (S0-S7) of the ISP pipe processing logic 80 may have a corresponding go register 214. In one embodiment, the go bit 238 may be a single-bit field. The go register 214 may be armed by setting the go bit 238 to 1, for example. The NextDestVld field 216 may contain a number of bits corresponding to the number of destinations in the ISP pipe processing logic 80. For instance, in the embodiment shown in FIG. 8, the ISP pipe processing logic 80 includes eight destinations D0-D7. Thus, the go register 214 may include eight bits in the NextDestVld field 216, with one bit corresponding to each destination. Targeted destinations in the NextDestVld field 216 may be set to 1. Similarly, the NextDestBk field 216 may contain a number of bits corresponding to the number of data registers in the ISP pipe processing logic 80. For instance, the embodiment of the ISP pipe processing logic 80 shown in FIG. 8 may include eight sources S0-S7. Accordingly, the NextDestBk field 218 may include eight bits, with one bit corresponding to each source register. Source registers corresponding to Bank 0 and 1 may be selected by setting their respective bit values to 0 or 1, respectively. Thus, using the go register 214, the source, upon triggering, knows precisely which destination units are to receive frame data, and which source banks are to be used for configuring the targeted destination units.

Additionally, to support the dual sensor configuration of the illustrated embodiments, the ISP pipe processing logic 80 may operate in a single sensor configuration mode (e.g., only one sensor is acquiring data) and/or a dual sensor configuration mode (e.g., both sensors are acquiring data). In a typical single sensor configuration, input data from a sensor interface 94, such as Sens0 (S0), is sent to StatsPipe0 (D2) (for statistics processing) and RAWProc (D4) (for pixel processing). In addition, sensor frames may also be sent to memory 100 (e.g., D0) for future processing, as discussed above.

An example of how the NextDestVld fields corresponding to each source of the ISP pipe processing logic 80 may be configured when operating in a single sensor mode is depicted below in Table 2.

TABLE 2

NextDestVld per source example: Single sensor mode

Sif0DMA

Sif1DMA

StatsPipe0

StatsPipe1

RAWProc

RgbProc

YCCProc

BEIF

(D0)

(D1)

(D2)

(D3)

(D4)

(D5)

(D6)

(D7)

Sens0

1

N/A

1

0

1

1

1

0

(S0)

Sens1

N/A

0

0

0

0

0

0

0

(S1)

Sens0DMA

N/A

N/A

0

N/A

0

0

0

0

(S2)

Sens1DMA

N/A

N/A

N/A

0

0

0

0

0

(S3)

RawProcinDMA

N/A

N/A

N/A

N/A

0

0

0

0

(S4)

RgbProcinDMA

N/A

N/A

N/A

N/A

N/A

0

0

0

(S5)

YccProcinDMA

N/A

N/A

N/A

N/A

N/A

N/A

0

0

(S6)

BEIFDMA

N/A

N/A

N/A

N/A

N/A

N/A

N/A

0

(S7)

As mentioned above with reference to Table 1, the ISP pipe processing logic 80 may be configured such that only certain destinations are valid for a particular source. Thus, the destinations in Table 2 marked with “N/A” or “0” are intended to indicate that the ISP pipe processing logic 80 is not configured to allow a particular source to send frame data to that destination. For such destinations, the bits of the NextDestVld field of the particular source corresponding to that destination may always be 0. It should be understood, however, that this is merely one embodiment and, indeed, in other embodiments, the ISP pipe processing logic 80 may be configured such that each source is capable of targeting each available destination unit.

The configuration shown above in Table 2 represents a single sensor mode in which only Sensor0 90a is providing frame data. For instance, the Sens0 Go register indicates destinations as being SIf0DMA, StatsPipe0, RAWProc, RgbProc, and YCCProc. Thus, when triggered, each frame of the Sensor0 image data, is sent to these destinations (where data is sent to RgbProc and YCCProc by way of RAWProc). As discussed above, SIf0DMA may store frames in memory 100 for later processing, StatsPipe0 may perform statistics collection, and RAWProc, RgbProc, and YCCProc may process the image data using the statistics from the StatsPipe0. Further, in some configurations where additional statistics are desired (e.g., statistics in different color spaces), StatsPipe1 may also be enabled (corresponding NextDestVld set to 1) during the single sensor mode. In such embodiments, the Sensor0 frame data is sent to both StatsPipe0 and StatsPipe1. Further, as shown in the present embodiment, only a single sensor interface (e.g., Sens0 or alternatively Sen0) is the only active source during the single sensor mode.

With this in mind, FIG. 16 provides a flowchart depicting a method 240 for processing frame data in the ISP pipe processing logic 80 when only a single sensor is active (e.g., Sensor 0). While the method 240 illustrates in particular the processing of Sensor0 frame data by The ISP pipe processing logic 80 as an example, it should be understood that this process may be applied to any other source and corresponding destination unit in the ISP pipe processing logic 80. Beginning at block 242, Sensor0 begins acquiring image data and sending the captured frames to the ISP pipe processing logic 80. The control unit 190 may initialize programming of the go register corresponding to Sens0 (the Sensor0 interface) to determine target destinations (including RAWProc) and what bank registers to use, as shown at block 244. Thereafter, decision logic 246 determines whether a source triggering event has occurred. As discussed above, frame data input from a sensor interface may use different triggering modes (FIGS. 11-13). If a trigger event is not detected, the process 240 continues to wait for the trigger. Once triggering occurs, the next frame becomes the current frame and is sent to RAWProc (and other target destinations) for processing at block 248. RAWProc may be configured using data parameters based on a corresponding data register specified in the NextDestBk field of the Sens0 Go register. After processing of the current frame is completed at block 250, the method 240 may return to block 244, at which the Sens0 Go register is programmed for the next frame.

When both Sensor0 and Sensor1 of the ISP pipe processing logic 80 are both active, statistics processing remains generally straightforward, since each sensor input may be processed by a respective statistics logic, StatsPipe0 and StatsPipe1. However, because the illustrated embodiment of the ISP pipe processing logic 80 provides only a single pixel processing pipeline (RAWProc to RgbProc to YCCProc), RAWProc, RgbProc, and YCCProc may be configured to alternate between processing frames corresponding to Sensor0 input data and frames corresponding to Sensor1 input data. As may be appreciated, the image frames are read from RAWProc in the illustrated embodiment to avoid a condition in which image data from one sensor is processed in real-time while image data from the other sensor is not processed in real-time. For instance, as shown in Table 3 below, which depicts one possible configuration of NextDestVld fields in the go registers for each source when the ISP pipe processing logic 80 is operating in a dual sensor mode, input data from each sensor is sent to memory (SIf0DMA and SIf1DMA) and to the corresponding statistics processing unit (StatsPipe0 and StatsPipe1).

TABLE 3

NextDestVld per source example: Dual sensor mode

Sif0DMA

Sif1DMA

StatsPipe0

StatsPipe1

RAWProc

RgbProc

YCCProc

BEIF

(D0)

(D1)

(D2)

(D3)

(D4)

(D5)

(D6)

(D7)

Sens0

1

N/A

1

0

0

0

0

0

(S0)

Sens1

N/A

1

0

1

0

0

0

0

(S1)

Sens0DMA

N/A

N/A

0

N/A

0

0

0

0

(S2)

Sens1DMA

N/A

N/A

N/A

0

0

0

0

0

(S3)

RawProcinDMA

N/A

N/A

N/A

N/A

1

1

1

0

(S4)

RgbProcinDMA

N/A

N/A

N/A

N/A

N/A

0

0

0

(S5)

YccProcinDMA

N/A

N/A

N/A

N/A

N/A

N/A

0

0

(S6)

BEIFDMA

N/A

N/A

N/A

N/A

N/A

N/A

N/A

0

(S7)

The sensor frames in memory are sent to RAWProc from the RAWProcInDMA source (S4), such that they alternate between Sensor0 and Sensor1 at a rate based on their corresponding frame rates. For instance, if Sensor0 and Sensor1 are both acquiring image data at a rate of 30 frames per second (fps), then their sensor frames may be interleaved in a 1-to-1 manner. If Sensor0 (30 fps) is acquiring image data at a rate twice that of Sensor1 (15 fps), then the interleaving may be 2-to-1, for example. That is, two frames of Sensor0 data are read out of memory for every one frame of Sensor1 data.

With this in mind, FIG. 16 depicts a method 252 for processing frame data in the ISP pipe processing logic 80 having two sensors acquiring image data simultaneously. At block 254, both Sensor0 and Sensor1 begin acquiring image frames. As may be appreciated, Sensor0 and Sensor1 may acquire the image frames using different frame rates, resolutions, and so forth. At block 256, the acquired frames from Sensor0 and Sensor1 written to memory 100 (e.g., using SIf0DMA and SIf1DMA destinations). Next, source RAWProcInDMA reads the frame data from the memory 100 in an alternating manner, as indicated at block 258. As discussed, frames may alternate between Sensor0 data and Sensor1 data depending on frame rate at which the data is acquired. At block 260, the next frame from RAWProcInDMA is acquired. Thereafter, at block 262, the NextDestVld and NextDestBk fields of the go register corresponding to the source, here RAWProcInDMA, is programmed depending on whether the next frame is Sensor0 or Sensor1 data. Thereafter, decision logic 264 determines whether a source triggering event has occurred. As discussed above, data input from memory may be triggered by arming the go bit (e.g., “trigger-on-go” mode). Thus, triggering may occur once the go bit of the go register is set to 1. Once triggering occurs, the next frame becomes the current frame and is sent to RAWProc for processing at block 266. As discussed above, RAWProc may be configured using data parameters based on a corresponding data register specified in the NextDestBk field of the corresponding go register. After processing of the current frame is completed at block 268, the method 252 may return to block 260 and continue.

A further operational event that the ISP pipe processing logic 80 may perform is a configuration change during image processing. For instance, such an event may occur when the ISP pipe processing logic 80 transitions from a single sensor configuration to a dual sensor configuration, or vice-versa. As discussed above, the NextDestVld fields for certain sources may be different depending on whether one or both image sensors are active. Thus, when the sensor configuration is changed, the ISP pipe processing logic 80 control unit 190 may release all destination units before they are targeted by a new source. This may avoid invalid configurations (e.g., assigning multiple sources to one destination). In one embodiment, the release of the destination units may be accomplished by setting the NextDestVld fields of all the go registers to 0, thus disabling all destinations, and arming the go bit. After the destination units are released, the go registers may be reconfigured depending on the current sensor mode, and image processing may continue.

A flowchart 270 for switching between single and dual sensor configurations is shown in FIG. 18. Beginning at block 272, a next frame of image data from a particular source of the ISP pipe processing logic 80 is identified. At block 274, the target destinations (NextDestVld) are programmed into the go register corresponding to the source. Next, at block 1368, depending on the target destinations, NextDestBk is programmed to point to the correct data registers associated with the target destinations. Thereafter, decision logic 278 determines whether a source triggering event has occurred. Once triggering occurs, the next frame is sent to the destination units specified by NextDestVld and processed by the destination units using the corresponding data registers specified by NextDestBk, as shown at block 280. The processing continues until block 282, at which the processing of the current frame is completed.

Subsequently, decision logic 284 determines whether there is a change in the target destinations for the source. As discussed above, NextDestVld settings of the go registers corresponding to Sens0 and Sens1 may vary depending on whether one sensor or two sensors are active. For instance, referring to Table 2, if only Sensor0 is active, Sensor0 data is sent to SIf0DMA, StatsPipe0, and RAWProc. However, referring to Table 3, if both Sensor0 and Sensor1 are active, then Sensor0 data is not sent directly to RAWProc. Instead, as mentioned above, Sensor0 and Sensor1 data is written to memory 100 and is read out to RAWProc in an alternating manner by source RAWProcInDMA (S4). Thus, if no target destination change is detected at decision logic 284, the control unit 190 deduces that the sensor configuration has not changed, and the method 270 returns to block 276, whereas the NextDestBk field of the source go register is programmed to point to the correct data registers for the next frame, and continues.

If, however, at decision logic 284, a destination change is detected, the control unit 190 may determine that a sensor configuration change has occurred. This could represent, for example, switching from single sensor mode to dual sensor mode, or shutting off the sensors altogether. Accordingly, the method 270 continues to block 286, at which all bits of the NextDestVld fields for all go registers are set to 0, thus effectively disabling the sending of frames to any destination on the next trigger. Then, at decision logic 288, a determination is made as to whether all destinations have transitioned to an idle state. If not, the method 270 waits at decision logic 288 until all destinations units have completed their current operations. Next, at decision logic 290, a determination is made as to whether image processing is to continue. For instance, if the destination change represented the deactivation of both Sensor0 and Sensor 1, then image processing ends at block 292. However, if it is determined that image processing is to continue, then the method 270 returns to block 274 and the NextDestVld fields of the go registers are programmed in accordance with the current operation mode (e.g., single sensor or dual sensor). As shown here, the steps 284-292 for clearing the go registers and destination fields may collectively be referred to by reference number 294.

Next, FIG. 19 shows a further embodiment by way of the flowchart (method 296) that provides for another dual sensor mode of operation. The method 296 depicts a condition in which one sensor (e.g., Sensor0) is actively acquiring image data and sending the image frames to The ISP pipe processing logic 80 for processing, while also sending the image frames to StatsPipe0 and/or memory 100 (Sif0DMA), while the other sensor (e.g., Sensor1) is inactive (e.g., turned off), as shown at block 298. Decision logic 300 then detects for a condition in which Sensor1 will become active on the next frame to send image data to RAWProc. If this condition is not met, then the method 296 returns to block 298. However, if this condition is met, then the method 296 proceeds by performing action 294 (collectively steps 284-292 of FIG. 19), whereby the destination fields of the sources are cleared and reconfigured at block 294. For instance, at block 294, the NextDestVld field of the go register associated with Sensor1 may be programmed to specify RAWProc as a destination, as well as StatsPipe1 and/or memory (Sif1DMA), while the NextDestVld field of the go register associated with Sensor0 may be programmed to clear RAWProc as a destination. In this embodiment, although frames captured by Sensor0 are not sent to RAWProc on the next frame, Sensor0 may remain active and continue to send its image frames to StatsPipe0, as shown at step 302, while Sensor1 captures and sends data to RAWProc for processing at step 304. Thus, both sensors, Sensor0 and Sensor1 may continue to operate in this “dual sensor” mode, although only image frames from one sensor are sent to RAWProc for processing. For the purposes of this example, a sensor sending frames to RAWProc for processing may be referred to as an “active sensor,” a sensor that is not sending frame RAWProc but is still sending data to the statistics processing units may be referred to as a “semi-active sensor,” and a sensor that is not acquiring data at all may be referred to as an “inactive sensor.”

One benefit of the foregoing technique is that the because statistics continue to be acquired for the semi-active sensor (Sensor0), the next time the semi-active sensor transitions to an active state and the current active sensor (Sensor1) transitions to a semi-active or inactive state, the semi-active sensor may begin acquiring data within one frame, since color balance and exposure parameters may already be available due to the continued collection of image statistics. This technique may be referred to as “hot switching” of the image sensors, and avoids drawbacks associated with “cold starts” of the image sensors (e.g., starting with no statistics information available). Further, to save power, since each source is asynchronous (as mentioned above), the semi-active sensor may operate at a reduced clock and/or frame rate during the semi-active period.

ISP Memory Format

Before continuing with a more detailed description of the statistics processing and pixel processing operations depicted in the ISP pipe processing logic 80 of FIG. 8, it is believed that a brief introduction regarding several types of memory addressing formats that may be used with the disclosed techniques, as well as a definition of various ISP frame regions, will help to facilitate a better understanding of the present subject matter.

FIG. 20 illustrates a linear addressing mode that may be applied to pixel data received from the image sensor(s) 90 and stored into memory (e.g., 100). The depicted example may be based upon a host interface block request size of 64 bytes. As may be appreciated, other embodiments may use different block request sizes (e.g., 32 bytes, 128 bytes, and so forth). In the linear addressing mode shown in FIG. 20, image samples are located in memory in sequential order. The term “linear stride” specifies the distance in bytes between 2 adjacent vertical pixels. In the present example, the starting base address of a plane is aligned to a 64-byte boundary and the linear stride may be a multiple of 64 (based upon the block request size).

With this in mind, various frame regions that may be defined within an image source frame are illustrated in FIG. 21. The format for a source frame provided to the image processing circuitry 32 may use the linear addressing mode discussed above, and may use pixel formats in 8, 10, 12, 14, or 16-bit precision (which ultimately may be converted to signed 17-bit format for image processing). The image source frame 306, as shown in FIG. 21, may include a sensor frame region 308, a raw frame region 308, and an active region 310. The sensor frame 308 is generally the maximum frame size that the image sensor 90 can provide to the image processing circuitry 32. The raw frame region 310 may be defined as the region of the sensor frame 308 that is sent to the ISP pipe processing logic 80. The active region 312 may be defined as a portion of the source frame 306, typically within the raw frame region 310, on which processing is performed for a particular image processing operation. In accordance with an embodiment, the active region 312 may be the same or may be different for different image processing operations.

In accordance with aspects of the present technique, the ISP pipe processing logic 80 only receives the raw frame 310. Thus, for the purposes of the present discussion, the global frame size for the ISP pipe processing logic 80 may be assumed as the raw frame size, as determined by the width 314 and height 316. In some embodiments, the offset from the boundaries of the sensor frame 308 to the raw frame 310 may be determined and/or maintained by the control logic 84. For instance, the control logic 84 may be include firmware that may determine the raw frame region 310 based upon input parameters, such as the x-offset 318 and the y-offset 320, that are specified relative to the sensor frame 308. Further, in some cases, a processing unit within the ISP pipe processing logic 80 or the ISP pipe logic 82 may have a defined active region, such that pixels in the raw frame but outside the active region 312 will not be processed, i.e., will left unchanged. For instance, an active region 312 for a particular processing unit having a width 322 and height 324 may be defined based upon an x-offset 326 and y-offset 328 relative to the raw frame 310. Further, where an active region is not specifically defined, one embodiment of the image processing circuitry 32 may assume that the active region 312 is the same as the raw frame 310 (e.g., x-offset 326 and y-offset 328 are both equal to 0). Thus, for the purposes of image processing operations performed on the image data, boundary conditions may be defined with respect to the boundaries of the raw frame 310 or active region 312. Additionally, in some embodiments, a window (frame) may be specified by identifying a starting and ending location in memory, rather than a starting location and window size information.

In some embodiments, the ISP pipe processing logic 80 (RAWProc) may also support processing an image frame by way of overlapping vertical stripes, as shown in FIG. 22. For instance, image processing in the present example may occur in three passes, with a left stripe (Stripe0), a middle stripe (Stripe1), and a right stripe (Stripe2). This may allow the ISP pipe processing logic 80 to process a wider image in multiple passes without the need for increasing line buffer size. This technique may be referred to as “stride addressing.”

When processing an image frame by multiple vertical stripes, the input frame is read with some overlap to allow for enough filter context overlap so that there is little or no difference between reading the image in multiple passes versus a single pass. For instance, in the present example, Stripe0 with a width SrcWidth0 and Stripe1 with a width SrcWidth1 partially overlap, as indicated by the overlapping region 330. Similarly, Stripe1 also overlaps on the right side with Stripe2 having a width of SrcWidth2, as indicated by the overlapping region 332. Here, the total stride is the sum of the width of each stripe (SrcWidth0, SrcWidth1, SrcWidth2) minus the widths (334, 336) of the overlapping regions 330 and 332. When writing the image frame to memory (e.g., 108), an active output region is defined and only data inside the output active region is written. As shown in FIG. 22, on a write to memory, each stripe is written based on non-overlapping widths of ActiveDst0, ActiveDst1, and ActiveDst2.

Additionally or alternatively, the ISP pipe processing logic 80 may support processing an image frame 5250 by way of overlapping tiles, as shown in FIG. 222. In the example of FIG. 222, processing all or part of an image frame in this way may involve processing six tiles 5252 (Tile0-Tile5) in six different passes in a 3×2 grid. As should be appreciated, any other suitable number of tiles may be processed. As with vertical stripe processing, the input tiles 5252 are read in to the ISP pipe processing logic 80 so as to allow sufficient overlap 5254 to permit filter context overlap. Doing this may avoid artifacts that might otherwise arise when the processed tiles 5252 are put back together in a final image. Thus, the source stride 5256 may include the sum of tile source widths 5258, each of which may overlap the other. Likewise, tile source heights 5260 may also overlap one another. The destination stride 5262 of the processed image frame may be the same as the source stride 5256. The active destination widths 5264 each may extend to a point within the overlapping area of the source widths 5258, and the destination heights 5266 may extend to a point within the overlapping area of the source heights 5260.

Using tile processing as shown in FIG. 222, input frames may be read with overlap to allow for enough filter context overlap so that there are few, if any, differences between one pass or multiple passes. As such, the DMA input to the ISP pipe processing logic 80 may read the additional pixel to accommodate the filter context of the component(s) of the ISP pipe processing logic 80 to which the data is sent. Namely, each pixel DMA output channel may define an active output region. The DMA may receive data for the entire processing frame size, but only those pixels that fall inside the active output region may be written to DMA. Software controlling the ISP pipe processing logic 80 may program the DMA registers to allow enough overlap for the context of the component(s) of the ISP pipe processing logic 80 to which the data is sent.

As discussed above, the image processing circuitry 32 may receive image data directly from a sensor interface (e.g., 94) or may receive image data from memory 100 (e.g., DMA memory). Where incoming data is provided from memory, the image processing circuitry 32 and the ISP pipe processing logic 80 may be configured to provide for byte swapping, wherein incoming pixel data from memory may be byte swapped before processing. In one embodiment, a swap code may be used to indicate whether adjacent double words, words, half words, or bytes of incoming data from memory are swapped. For instance, referring to FIG. 23, byte swapping may be performed on a 16 byte (bytes 0-15) set of data using a four-bit swap code.

As shown, the swap code may include four bits, which may be referred to as bit3, bit2, bit1, and bit0, from left to right. When all bits are set to 0, as shown by reference number 338, no byte swapping is performed. When bit3 is set to 1, as shown by reference number 340, double words (e.g., 8 bytes) are swapped. For instance, as shown in FIG. 25, the double word represented by bytes 0-7 is swapped with the double word represented by bytes 8-15. If bit2 is set to 1, as shown by reference number 342, word (e.g., 4 bytes) swapping is performed. In the illustrated example, this may result in the word represented by bytes 8-11 being swapped with the word represented by bytes 12-15, and the word represented by bytes 0-3 being swapped with the word represented by bytes 4-7. Similarly, if bit1 is set to 1, as shown by reference number 344, then half word (e.g., 2 bytes) swapping is performed (e.g., bytes 0-1 swapped with bytes 2-3, etc.) and if bit0 is set to 1, as shown by reference number 346, then byte swapping is performed.

In the present embodiment, swapping may be performed in by evaluating bits 3, 2, 1, and 0 of the swap code in an ordered manner. For example, if bits 3 and 2 are set to a value of 1, then double word swapping (bit3) is first performed, followed by word swapping (bit2). Thus, as shown in FIG. 23, when the swap code is set to “1111,” the end result is the incoming data being swapped from little endian format to big endian format.

Various read and write channels to memory 100 may be employed by the ISP pipe processing logic 80. In one embodiment, the read/write channels may share a common data bus, which may be provided using Advanced Microcontroller Bus Architecture, such as an Advanced Extensible Interface (AXI) bus, or any other suitable type of bus (AHB, ASB, APB, ATB, etc.). Depending on the image frame information (e.g., pixel format, address format, packing method) which, as discussed above, may be determined via a control register, an address generation block, which may be implemented as part of the control logic 84, may be configured to provide address and burst size information to the bus interface. By way of example the address calculation may depend various parameters, such as whether the pixel data is packed or unpacked, the pixel data format (e.g., RAW8, RAW10, RAW12, RAW14, RAW16, RGB, or YCbCr/YUV formats), whether tiled or linear addressing format is used, x- and y-offsets of the image frame data relative to the memory array, as well as frame width, height, and stride. Further parameters that may be used in calculation pixel addresses may include minimum pixel unit values (MPU), offset masks, a byte per MPU value (BPPU), and a Log 2 of MPU value (L2MPU). Table 4, which is shown below, illustrates the aforementioned parameters for packed and unpacked pixel formats, in accordance with an embodiment.

TABLE 4

Definition of L2MPU & BPPU

MPU

L2MPU

BPPU

(Minimum

(Log2

Offset-

(Bytes

Format

Pixel Unit)

of MPU)

Mask

Per MPU)

RAW8

Unpacked

1

0

0

1

RAW10

Packed

4

2

3

5

Unpacked

1

0

0

2

RAW12

Packed

4

2

3

6

Unpacked

1

0

0

2

RAW14

Packed

4

2

3

7

Unpacked

1

0

0

2

RAW16

Unpacked

1

0

0

2

RGB-888

1

0

0

4

RGB-666

1

0

0

4

RGB-565

1

0

0

2

RGB-16

1

0

0

8

YCC8_420 (2 Plane)

2

1

0

2

YCC10_420 (2 Plane)

2

1

0

4

YCC8_422 (2 Plane)

2

1

0

2

YCC10_422 (2 Plane)

2

1

0

4

YCC8_422 (1 Plane)

2

1

0

4

YCC10_422 (1 Plane)

2

1

0

8

As should be understood, the MPU and BPPU settings allow the image processing circuitry 32 to assess the number of pixels that need to be read in order to read one pixel, even if not all of the read data is needed. That is, the MPU and BPPU settings may allow the image processing circuitry 32 read in pixel data formats that are both aligned with (e.g., a multiple of 8 bits (1 byte) is used to store a pixel value) and unaligned with memory byte (e.g., pixel values are stored using fewer or greater than a multiple of 8 bits (1 byte), such as RAW10, RAW12, etc.). It may be noted that OffsetX may always be a multiple of two for all of the YCC formats. For 4:2:0 YCC formats, OffsetY may always be a multiple of two.

Referring to FIG. 24, an example showing the location of an image frame 350 stored in memory under linear addressing is illustrated, which each block representing 64 bytes (as discussed above in FIG. 21). In FIG. 24, the Stride is 4, meaning 4 blocks of 64 bytes. Referring to Table 4 above, the values for L2MPU and BPPU may depend on the format of the pixels in the frame 350. Software may program the base address (BaseAddr) of the frame in memory, along with OffsetX, OffsetY, Width, and Height in pixel units and the Stride in block units. These may be determined using the values of L2MPU and BPPU corresponding to the pixel format of the frame 350. The image processing circuitry 32 may calculate the position for the first pixel to fetch from the memory 100 at the BlockStart address.

Various memory formats of the image pixel data that may be supported by the image processing circuitry 32 will now be discussed in greater detail. These formats may include raw image data (e.g., Bayer RGB data), RGB color data, and YUV (YCC, luma/chroma data). First, formats for raw image pixels (e.g., Bayer data before demosaicing) in a destination/source frame that may be supported by embodiments of the image processing circuitry 32 are discussed. As mentioned, certain embodiments may support processing of image pixels at 8, 10, 12, 14, and 16-bit precision (scaled and offset to a signed 17-bit format). In the context of raw image data, 8, 10, 12, 14, and 16-bit raw pixel formats may be referred to herein as RAW8, RAW10, RAW12, RAW14, and RAW16 formats, respectively. Examples showing how each of the RAW8, RAW10, RAW12, RAW14, and RAW16 formats may be stored in memory are shown graphically unpacked forms in FIG. 25. For raw image formats having a bit-precision greater than 8 bits (and not being a multiple of 8-bits), the pixel data may also be stored in packed formats. For instance, FIG. 26 shows an example of how RAW10 image pixels may be stored in memory. Similarly, FIG. 27 and FIG. 28 illustrate examples by which RAW12 and RAW14 image pixels may be stored in memory. As will be discussed further below, when image data is being written to/read from memory, a control register associated with the sensor interface 94 may define the destination/source pixel format, whether the pixel is in a packed or unpacked format, addressing format (e.g., linear or tiled), and the swap code. Thus, the manner in which the pixel data is read and interpreted by, the image processing circuitry 32 may depend on the pixel format.

The image signal processing (ISP) circuitry 32 may also support certain formats of RGB color pixels in the sensor interface source/destination frame (e.g., 310). For instance, RGB image frames may be received from the sensor interface (e.g., in embodiments where the sensor interface includes on-board demosaicing logic) and saved to memory 100. In one embodiment, the ISP pipe processing logic 80 (RAWProc) may bypass pixel and statistics processing when RGB frames are being received. By way of example, the image processing circuitry 32 may support the following RGB pixel formats: RGB-565 and RGB-888. An example of how RGB-565 pixel data may be stored in memory is shown in FIG. 29. As illustrated, the RGB-565 format may provide one plane of an interleaved 5-bit red color component, 6-bit green color component, and 5-bit blue color component in RGB order. Thus, 16 bits total may be used to represent an RGB-565 pixel (e.g., {R0, G0, B0} or {R1, G1, B1}).

An RGB-888 format, as depicted in FIG. 30, may include one plane of interleaved 8-bit red, green, and blue color components in RGB order. In one embodiment, the image processing circuitry 32 may also support an RGB-666 format, which generally provides one plane of interleaved 6-bit red, green and blue color components in RGB order. In such embodiments, when an RGB-666 format is selected, the RGB-666 pixel data may be stored in memory using the RGB-888 format shown in FIG. 30, but with each pixel left justified and the two least significant bits (LSB) set as zero.

In certain embodiments, the image processing circuitry 32 may also support RGB pixel formats that allow pixels to have extended range and precision of floating point values. For instance, in one embodiment, the image processing circuitry 32 may support the RGB pixel format shown in FIG. 31, wherein a red (R0), green (G0), and blue (B0) color component is expressed as an 8-bit value, with a shared 8-bit exponent (E0). Thus, in such embodiments, the actual red (R′), green (G′) and blue (B′) values defined by R0, G0, B0, and E0 may be expressed as:
R′=R0[7:0]*2^E0[7:0]
G′=G0[7:0]*2^E0[7:0]
B′=B0[7:0]*2^E0[7:0]
This pixel format may be referred to as the RGBE format, which is also sometimes known as the Radiance image pixel format.

FIGS. 32 and 33 illustrate additional RGB pixel formats that may be supported by the image processing circuitry 32. Particularly, FIG. 32 depicts a pixel format that may store 9-bit red, green, and blue components with a 5-bit shared exponent. For instance, the upper eight bits [8:1] of each red, green, and blue pixel are stored in respective bytes in memory. An additional byte is used to store the 5-bit exponent (e.g., E0[4:0]) and the least significant bit [0] of each red, green, and blue pixel. Thus, in such embodiments, the actual red (R′), green (G′) and blue (B′) values defined by R0, G0, B0, and E0 may be expressed as:
R′=R0[8:0]*2^E0[4:0]
G′=G0[8:0]*2^E0[4:0]
B′=B0[8:0]*2^E0[4:0]
Further, the pixel format illustrated in FIG. 32 is also flexible in that it may be compatible with the RGB-888 format shown in FIG. 30. For example, in some embodiments, the image processing circuitry 32 may process the full RGB values with the exponential component, or may also process only the upper 8-bit portion [7:1] of each RGB color component in a manner similar to the RGB-888 format.

FIG. 33 depicts a pixel format that may store 10-bit red, green, and blue components with a 2-bit shared exponent. For instance, the upper 8-bits [9:2] of each red, green, and blue pixel are stored in respective bytes in memory. An additional byte is used to store the 2-bit exponent (e.g., E0[1:0]) and the least significant 2-bits [1:0] of each red, green, and blue pixel. Thus, in such embodiments, the actual red (R′), green (G′) and blue (B′) values defined by R0, G0, B0, and E0 may be expressed as:
R′=R0[9:0]*2^E0[1:0]
G′=G0[9:0]*2^E0[1:0]
B′=B0[9:0]*2^E0[1:0]
Additionally, like the pixel format shown in FIG. 32, the pixel format illustrated in FIG. 33 is also flexible in that it may be compatible with the RGB-888 format shown in FIG. 30. For example, in some embodiments, the image processing circuitry 32 may process the full RGB values with the exponential component, or may also process only the upper 8-bit portion (e.g., [9:2]) of each RGB color component in a manner similar to the RGB-888 format.

In addition, the image processing circuitry 32 may support 16-bit RGB format known as RGB-16. With RGB-16, one plane of interleaved 16-bit components in ARGB order, as illustrated in FIG. 34. For the RGB-888 format shown in FIG. 30 and the RGB-16 format shown in FIG. 34, alpha may be set to 0xFF and 0xFFFF, respectively, when pixel data is written to external memory 100. Alpha may be ignored when reading RGB-888 or RGB-16 formatted data from the memory 100. Image data of the RGB-16 format may not be supported from the sensor 90 outputs.

The image processing circuitry 32 may also further support certain formats of YCbCr (YUV) luma and chroma pixels in the sensor interface source/destination frame (e.g., 310). For instance, YCbCr image frames may be received from the sensor interface (e.g., in embodiments where the sensor interface includes on-board demosaicing logic and logic configured to convert RGB image data into a YCC color space) and saved to memory 100 and/or the output of the RgbProc 160 in YCC format may be saved to memory 100. In one embodiment, the ISP pipe processing logic 80 may bypass pixel and statistics processing when YCbCr frames are being received. By way of example, the image processing circuitry 32 may support the following YCbCr pixel formats: YCbCr4:4:4 16-bit, 1-plane; YCbCr-4:2:0 10-bit, 2-plane; YCbCr-4:2:2 10-bit, 1-plane; YCbCr-4:2:0 8-bit, 2-plane; and YCbCr-4:2:2 8-bit, 1-plane.

The YCbCr4:4:4 16-bit, 1-plane format may provide a single image plane with interleaved 16-bit components, as generally shown by FIG. 35. That is, both luma pixels (Y) and chroma pixels (Cb and Cr) may be represented in the same plane of memory in the YCbCr4:4:4 16-bit, 1-plane format. It may be noted that the YCbCr4:4:4 16-bit, 1-plane format is related to the RGB-16 format shown in FIG. 34.

The YCbCr-4:2:0, 8-bit, 2 plane pixel format and the YCbCr-4:2:0, 10-bit, 2 plane pixel format may provide two separate image planes in memory, one for luma pixels (Y) and one for chroma pixels (Cb, Cr), wherein the chroma plane interleaves the Cb and Cr pixel samples. Additionally, the chroma plane may be subsampled by one-half in both the horizontal (x) and vertical (y) directions. An example showing how YCbCr-4:2:0, 2 plane, data may be stored in memory is shown in FIG. 36, which depicts a luma plane 347 for storing the luma (Y) samples and a chroma plane 348 for storing chroma (Cb, Cr) samples. An example showing how YCbCr-4:2:0, 10-bit, 2 plane pixel data may be stored in the memory 100 appears in FIG. 37.

A YCbCr-4:2:2 8-bit, 1 plane format, which is shown in FIG. 38, may include one image plane of interleaved luma (Y) and chroma (Cb, Cr) pixel samples, with the chroma samples being subsampled by one-half both the horizontal (x) and vertical (y) directions. An example of a YCbCr-4:2:2 10-bit, 1-plane format appears in FIG. 39. In some embodiments, the image processing circuitry 32 may also support 10-bit YCbCr pixel formats by saving the pixel samples to memory using the above-described 8-bit format with rounding (e.g., the two least significant bits of the 10-bit data are rounded off). Further, as may be appreciated, YC1C2 values may also be stored using any of the RGB pixel formats discussed above in FIGS. 29-34, wherein each of the Y, C1, and C2 components are stored in a manner analogous to an R, G, and B component.

As shown above in Table 4, for pixels stored in RAW10, RAW12, and RAW14 packed formats, four pixels make a minimum pixel unit (MPU) of five, six, or seven bytes (BPPU), respectively. For instance, referring to the RAW10 pixel format example shown in FIG. 26, an MPU of four pixels P0-P3 includes 5 bytes, wherein the upper 8 bits of each of the pixels P0-P3 are stored in four respective bytes, and the lower 2 bytes of each of the pixels are stored in bits 0-7 of the 32-bit address 01h. Similarly, referring back to FIG. 27, an MPU of four pixels P0-P3 using the RAW 12 format includes 6 bytes, with the lower 4 bits of pixels P0 and P1 being stored in the byte corresponding to bits 16-23 of address 00h and the lower 4 bits of pixels P2 and P3 being stored in the byte corresponding to bits 8-15 of address 01h. FIG. 28 shows an MPU of four pixels P0-P3 using the RAW14 format as including 7 bytes, with 4 bytes for storing the upper 8 bits of each pixel of the MPU and 3 bytes for storing the lower 6 bits of each pixel of the MPU.

Using these pixel formats, it is possible at the end of a frame line to have a partial MPU where less than four pixels of the MPU are used (e.g., when the line width modulo four is non-zero). When reading a partial MPU, unused pixels may be ignored. Similarly, when writing a partial MPU to a destination frame, unused pixels may be written with a value of zero. Further, in some instances, the last MPU of a frame line may not align to a 64-byte block boundary. In one embodiment, bytes after the last MPU and up to the end of the last 64-byte block are not written.

Scale and Offset Logic

As will be discussed in greater detail below, pixel processing through certain functional blocks of the ISP pipe processing logic 80 may take place in a signed format. The signed image data may employ an offset allowing for greater headroom than footroom. Moreover, by offsetting input pixels to allow for some negative values, using signed image data instead of unsigned image data for image processing may preserve more image information in the final, processed image. In some embodiments, the signed format may be signed 17-bit data, but any other suitable size may be employed. Using 17-bit image data, the source pixel data may take up two bytes to simplify memory, and one bit may be added to account for sign. Using 9-bit data, the source pixel data may take up one byte. Any other suitable signed format may be employed. For example, the signed format may be signed 10-bit, 11-bit, 12-bit, 13-bit, 14-bit, 15-bit, or less than 9-bit or greater than 17-bit. Indeed, in some embodiments, the image data may be signed 25-bit image data or signed 33-bit image data to allow for signed versions of image data of 3 or 4 bytes. Accordingly, it should be understood that when the present disclosure refers to “signed 17-bit,” any other suitable bit depth may be employed. Moreover, although the present disclosure refers to signed 17-bit image data, floating point image data may alternatively be used (e.g., 9.3). Before and after processing image data in certain functional blocks of the ISP pipe processing logic 80, the scale and offset logic 82 may convert unsigned image data into signed image data.

A flowchart 360 of FIG. 40 provides an example of image processing involving signed image data. The flowchart 360 may begin when the ISP pipe processing logic 80 is programmed to receive image data from the memory 100 in an unsigned format (block 361). For instance, the StatsPipe0 140a, the StatsPipe1 140b, the RAWProc 150, and the RgbProc 160 may be programmed to receive raw image data, which may be stored in the memory 100 in one of the RAW8, RAW10, RAW12, RAW14, or RAW16 image data formats. As mentioned above, the scale and offset logic 82 may represent logical offset and scale functions implemented on both DMA input and DMA output pixel channels. The pixel offset and scale functions of the scale and offset logic 82 may be applied to all supported formats of raw image data (e.g., RAW8, RAW10, RAW12, RAW14, and/or RAW16), all supported formats of RGB pixel data (e.g., RGB-565, RGB-888, RGB-16), and YCC pixel data of the YCC4:4:4 format. In transferring the unsigned image data from the memory 100 and/or the sensors 90a and 90b, the scale and offset logic 82 may convert the unsigned image data to a signed format (e.g., signed 17-bit) by applying a programmable scale and/or offset to the image data (block 362).

As mentioned above, the ISP pipe processing logic 80 may perform various image processing operations using signed image data to preserve image information (block 363). For instance, operations that produce negative pixel values as outputs or interim pixel values could lose image information if these pixels were merely clipped to zero. Although negative pixel values could not be displayed on a display 28—the lowest pixel value will typically be 0 (black)—allowing negative pixel values during interim processing may preserve image information for pixels at or near the color black in the final processed image. To provide a brief example, noise on the image sensor(s) 90 may occur in a positive or negative direction from the correct value. In other words, some pixels that should represent a particular light intensity may have a particular value, others may have noise resulting in values greater than the particular value, and still others may have noise resulting in values less than the particular value. When an area of the image sensor(s) 90 captures little or no light, sensor noise may increase or decrease individual pixel values such that the average pixel value is about zero. Thus, when image data from the sensor(s) 90 is processed by the scale and offset logic 82, the pixel values may be offset so as to preserve the negative noise values rather than clipping the negative noise values away. In particular, if only noise occurring in a negative direction were discarded, the true black color could rise above zero and could produce grayish-tinged black areas. Thus, by using signed image data, the ISP pipe processing logic 80 may more accurately render dark black areas in images.

When the ISP pipe processing logic 80 has finished performing one or more operations on the image data, the image data may be programmed to be stored in a location of the memory 100. Before being stored in the memory 100, the scale and offset logic 82 may convert the signed image data back to an unsigned format (block 364).

Before image data is converted from unsigned data to signed data, whether from the sensor interfaces 94a (S0) or 94b (S1) or from the memory 100 (S2-S6), pixel data first may be scaled to encompass 16 bits. For example, the scale and offset logic 82 may convert input pixels of bit depths less than 16 bits to an unsigned 16-bit format by shifting the input pixels to the left to fit the 16-bit scale. In addition, the scale and offset logic 82 may, but not necessarily, replicate the most significant bits (MSBs) of the input pixel in the remaining least significant bits (LSBs). The results of scaling various formats with bit depths of less than 16 bits unsigned 16-bit pixels are shown in FIG. 41. As shown in FIG. 41, when pixels in the RAW8 format (numeral 365) are scaled to 16 bits, the entire pixel may be replicated in the LSBs; when pixels in the RAW10 format (numeral 366) are scaled to 16 bits, the upper 6 bits may be replicated in the LSBs; when pixels in the RAW12 format (numeral 367) are scaled to 16 bits, the upper 4 bits may be replicated in the LSBs; when pixels in the RAW14 format (numeral 368) are scaled to 16 bits, the upper 2 bits may be replicated in the LSBs; and, since pixels in the RAW16 format (numeral 369) already take up 16 bits, these pixels need not be scaled. The same procedure illustrated by FIG. 41 may also be applied to the RGB-565 and RGB-888 formats.

Such 16-bit unsigned image data may be converted to signed 17-bit image data as shown in a flowchart 370 of FIG. 42. The flowchart 370 may begin when input pixels are programmed to be transferred to a processing block of the ISP pipe processing logic 80 that receives signed 17-bit input data (block 371). Pixels with bit depths of less than 16 bits may be scaled to an unsigned 16-bit format in the manner of FIG. 41 (block 372). The scale and offset logic 82 then may apply a programmable scale and offset to the unsigned 16-bit pixels (block 373).

First, the scale and offset logic 82 may scale the input pixels by some scale value (block 374). The scale value may be programmable. In the example of FIG. 42, the scale and offset logic 82 may scale the input pixels using a right-shift operation, but other embodiments may involve any other suitable scaling logic (e.g., multiplication logic). Software may vary the scale value depending, for example, on the original format of the input pixel and/or other expected gains that will be applied during image processing. By way of example, the programmable scale value may be a right-shift of 0 to 8. Scaling the input pixels may enable software to control the amount of headroom in the pixel pipeline to accommodate the various gains applied in the ISP pipe processing logic 80. Thus, the input pixels will be less likely to lose information after gains are applied. In the case of RGB image data, the same or a different scale may be applied to R, G, and B channels.

After scaling, the scale and offset logic 82 may subtract an offset value from the scaled pixel (block 375). Subtracting the offset value sets a zero-value in the now-signed 17-bit data, allowing negative pixel values from the sensor to enter the ISP pipe processing logic 80. The offset value may be, as indicated in FIG. 42, a programmable 16-bit value. In other embodiments, the offset value may have a depth other than 16-bits. In the case of RGB image data, the same offset value may be applied to R, G, and B channels. Subtracting the offset value may provide software the ability to program the range available for negative pixel values through the ISP pipe processing logic 80. Specifically, by appropriately biasing the input pixel value range using the offset value, potential overflow and underflow conditions in the ISP pipe processing logic 80 may be avoided. After subtracting the offset value, the scale and offset logic 82 may output the input pixel in 17-bit signed format. The resulting 17-bit signed pixel value may be used by the ISP pipe processing logic 80 to perform various image processing operations, as will be discussed in greater detail below (block 376).

After some interim processing, it may be desirable to write pixel values to the memory 100. Since the pixels may have been processed in the 17-bit format, these pixels first may be converted back to the unsigned 16-bit format before being stored in the memory 100. One example of this conversion is described by a flowchart 380 of FIG. 43. At various stages of processing through the ISP pipe processing logic 80, image data that has been partially processed may be transferred to the memory 100. Thus, the flowchart 380 may begin when the memory 100 is programmed to receive signed 17-bit pixels out of the ISP pipe processing logic 80 (block 381).

Before storing the pixels in the memory 100, the programmable scale and offset logic 82 may de-apply the programmable scale and offset to convert the image data from the signed 17-bit format back to the unsigned 16-bit format (block 382). Specifically, the scale and offset logic 82 may first add the 16-bit offset value back into the pixel (block 383). Adding the offset value back into the pixel brings the pixel value back to an unsigned 16-bit range. Thus, the scale and offset logic 82 may also clip the pixel to the extent that the pixel value falls outside of the 16-bit range (block 384). The scale and offset logic 82 next may scale the pixel by the scale value (block 385). In some embodiments, the scale and offset logic 82 may left-shift the pixel, while in others, the scale and offset logic 82 may multiply the pixel by some value. The scale function essentially enable software to convert from a smaller pixel range used by the ISP pipe processing logic 80 to a larger range used by the memory 100. For instance, if the pixel value used by a process of the ISP pipe processing logic 80 employs a 10-bit format, the pixels may be converted to 16-bits in memory by left-shifting the pixel data by 6 before writing to the memory 100. Additionally, in some embodiments, the most significant bits (MSB) of the pixel may be replicated into the least significant bits (LSB) (block 386). In other embodiments, the actions of block 386 may not be carried out.

The scale and offset logic 82 thus will have converted the signed 17-bit pixels back to the unsigned 16-bit format. The upper bits of the 16-bit range may then be used to send pixel data to the DMA memory 100 (block 387). The number of the upper bits used to send the pixel data to the memory 100 may vary depending on the format of the image data. For example, RAW8 image data may use bits [15:8], RAW10 may use bits [15:6], RAW12 may use bits [15:4], RAW14 may use bits [15:2], and so forth.

In practice, the scale and offset logic 82 may permit image processing with headroom and footroom. As used herein, “headroom” refers to

ISP Overflow Handling

In accordance with an embodiment, the image processing circuitry 32 may provide overflow handling. For instance, an overflow condition (also referred to as “overrun”) may occur in certain situations where the ISP pipe processing logic 80 receives back-pressure from its own internal processing units, from downstream processing units (e.g., ISP back-end interface 86), or from a memory 100 destination (e.g., where the image data is to be written). Overflow conditions may occur when pixel data is being read in (e.g., either from the sensor interface or memory) faster than one or more processing blocks is able to process the data, or faster than the data may be written to a destination (e.g., memory 100).

As will be discussed further below, reading and writing to memory may contribute to overflow conditions. When the input data derives from a location in the memory 100, the image processing circuitry 32 may simply stall the reading of the input data when an overflow condition occurs until the overflow condition recovers. When image data is being read directly from an image sensor, however, the “live” data generally cannot be stalled, as the image sensor 90 is generally acquiring the image data in real time. For instance, the image sensor 90 may operate in accordance with a timing signal based upon its own internal clock and may output image frames at a certain frame rate, such as 15, 30, or 60 frames per second (fps). The sensor 90 inputs to the image processing circuitry 32 and memory 100 may thus include input queues which may buffer the incoming image data before it is processed (by the image processing circuitry 32) or written to memory (e.g., 100). Accordingly, if image data is being received at the input queue 130 faster than it can be read out of the queue 130 and processed or stored (e.g., written to memory 100), an overflow condition may occur. That is, if the buffers/queues are full, additional incoming pixels cannot be buffered and, depending on the overflow handling technique implemented, may be dropped.

FIG. 44 shows a block diagram of the image processing circuitry 32, focusing on features of the control logic 84 that may provide for overflow handling in accordance with an embodiment. As illustrated, image data associated with Sensor0 90a and Sensor 1 90b may be read in from memory 100 as sources S0 and S1 (by way of sensor input queues 130a and 130b) to the ISP pipe processing logic 80 (e.g., RAWProc 150), or may be provided to the ISP pipe processing logic 80 directly from the respective sensor interfaces. In the latter case, incoming pixel data from the image sensors 90a and 90b may be passed to input queues 400 and 402, respectively, before being sent to the ISP pipe processing logic 80.

When an overflow condition occurs, the processing block(s) (e.g., blocks 80, 82, or 120) or memory (e.g., 108) in which the overflow occurred may provide a signal (as indicated by signals 405, 407, and 408) to set a bit in an interrupt request (IRQ) register 404. In the present embodiment, the IRQ register 404 may be implemented as part of the control logic 84. Additionally, separate IRQ registers 404 may be implemented for each of Sensor0 image data and Sensor1 image data. Based on the value stored in the IRQ register 404, the control logic 84 may be able to determine which logic units within the ISP processing blocks 80, 82, 120 or memory 100 generated the overflow condition. The logic units may be referred to as “destination units,” as they may constitute destinations to which pixel data is sent. In some embodiments, the destination units may represent the destinations D0-D7. Based on the overflow conditions, the control logic 84 may also (e.g., through firmware/software handling) govern which frames are dropped (e.g., either not written to memory or not output to the display for viewing).

Once an overflow condition is detected, the manner in which overflow handling is carried may depend on whether the ISP pipe processing logic 80 is reading pixel data from memory 100 or from the image sensor input queues (e.g., buffers) 130a or 130b, which may be first-in-first-out (FIFO) queues. When input pixel data is read from memory 100 through, for example, an associated DMA interface, the ISP pipe processing logic 80 will stall the reading of the pixel data if it receives back-pressure as a result of an overflow condition being detected (e.g., via control logic 84 using the IRQ register(s) 404) from any downstream destination blocks which may include the ISP pipe processing logic 80, the ISP back-end interface 86, or the memory 100 in instances where the output of the ISP pipe processing logic 80 is written to memory 100. In this scenario, the control logic 84 may prevent overflow by stopping the reading of the pixel data from memory 100 until the overflow condition recovers. For instance, overflow recovery may be signaled when the downstream unit that is causing the overflow condition sets a corresponding bit in the IRQ register 404 indicating that the overflow is no longer occurring. An example of this process appears in a flowchart 410 of FIG. 45.

While overflow conditions may generally be monitored at the sensor input queues, it should be understood that many additional queues may be present between processing units of the image processing circuitry 32 (e.g., including internal units of the ISP pipe processing logic 80 and/or the ISP back-end logic 86). Additionally, the various internal units of the image processing circuitry 32 may also include line buffers, which may also function as queues. Thus, all the queues and line buffers of the image processing circuitry 32 may provide buffering. Accordingly, when the last processing block in a particular chain of processing blocks is full (e.g., its line buffers and any intermediate queues are full), back-pressure may be applied to the preceding (e.g., upstream) processing block and so forth, such that the back-pressure propagates up through the chain of logic until it reaches the sensor interface, where overflow conditions may be monitored. Thus, when an overflow occurs at the sensor interface, it may mean that all the downstream queues and line buffers are full.

As shown in FIG. 45, the flowchart 410 may begin at block 412, when pixel data for a current from is read from memory to the ISP pipe processing logic 80. Decision logic 414 may determine whether an overflow condition is present. This decision may involve determining the state of bits in the IRQ register(s) 404. If no overflow condition is detected, then the flowchart 410 returns to block 412 and continues to read in pixels from the current frame. If an overflow condition is detected by decision logic 414, pixels of the current frame may no longer be read from memory, as shown by block 416. Next, at decision logic 418, it is determined whether the overflow condition has recovered. If the overflow condition persists, the process may wait at the decision logic 418 until the overflow condition recovers. If decision logic 418 indicates that the overflow condition has recovered, the process proceeds to block 420 and pixel data for the current frame may resume being read from memory.

When an overflow condition occurs while input pixel data is being read in from the sensor interface(s) 90a or 90b, interrupts may indicate which downstream units (e.g., processing blocks or destination memory) generated the overflow. In one embodiment, overflow handling may be provided based on two scenarios. In a first scenario, the overflow condition occurs during an image frame, but recovers before the start of the subsequent image frame. In this case, input pixels from the image sensor are dropped until the overflow condition recovers and space becomes available in the input queue corresponding to the image sensor. The control logic 84 may use a counter 406 to track the number of dropped pixels and/or dropped frames. When the overflow condition recovers, the dropped pixels may be replaced with undefined pixel values (e.g., all 1's, all 0's, or a value programmed into a data register that sets what the undefined pixel values are), and downstream processing may resume. In a further embodiment, the dropped pixels may be replaced with a previous non-overflow pixel (e.g., the last “good” pixel read into the input buffer). Doing so may ensure that a correct number of pixels (e.g., a number of pixels corresponding to the number of pixels expected in a complete frame) is sent to the ISP pipe processing logic 80, thus enabling the ISP pipe processing logic 80 to output the correct number of pixels for the frame that was being read in from the sensor input queue when the overflow occurred.

While the correct number of pixels may be output by the ISP pipe processing logic 80 under this first scenario, depending on the number of pixels that were dropped and replaced during the overflow condition, software handling (e.g., firmware), which may be implemented as part of the control logic 84, may choose to drop (e.g., exclude) the frame from being sent to the display 28 and/or written to the memory 100. Such a determination may be based, for example, upon the value of the dropped pixel counter 406 compared to an acceptable dropped pixel threshold value. For instance, if an overflow condition occurs only briefly during the frame such that only a relatively small amount of pixels are dropped (e.g., and replaced with undefined or dummy values; e.g., 10-20 pixels or less), then the control logic 84 may choose to display and/or store this image despite the small number of dropped pixels, even though the presence of the replacement pixels may produce minor artifacts in the resulting image. However, owing to the small number of replacement pixels, such artifacts may go generally unnoticed or may be only marginally perceptible to a user. That is, the presence of any such artifacts due to the undefined pixels from the brief overflow condition may not significantly degrade the aesthetic quality of the image (e.g., any such degradation may be minimal or negligible to the human eye).

In a second scenario, the overflow condition may remain present into the start of the subsequent image frame. In this case, the pixels of the current frame are also dropped and counted like the first scenario described above. However, if an overflow condition is still present upon detecting a VSYNC rising edge (e.g., indicating the start of a subsequent frame), the ISP pipe processing logic 80 may hold off the next frame, thus dropping the entire next frame. In this scenario, the next frame and subsequent frames will continue to be dropped until overflow recovers. Once the overflow recovers, the previously current frame (e.g., the frame being read when the overflow was first detected) may replace its dropped pixels with the undefined pixel values, thus allowing the ISP pipe processing logic 80 to output the correct number of pixels for that frame. Thereafter, downstream processing may resume. As for the dropped frames, the control logic 84 may further include a counter that counts the number of dropped frames. This data may be used to adjust timings for audio-video synchronization. For instance, for video captured at 30 fps, each frame has a duration of approximately 33 milliseconds. Thus, if three frames are dropped due to overflow, then the control logic 84 may be configured to adjust audio-video synchronization parameters to account for the approximately 99 millisecond (33 milliseconds×3 frames) duration attributable to the dropped frames. For instance, to compensate for time attributable due to the dropped frames, the control logic 84 may control image output by repeating one or more previous frames.

An example of a flowchart 430 representing the above-discussed scenarios that may occur when input pixel data is being read from the sensor interfaces appears in FIG. 46. As shown, the flowchart 430 begins at block 432, at which pixel data for a current frame is read in from the sensor to the ISP pipe processing logic 80. Decision logic 434 then determines whether an overflow condition exists. If there is no overflow, the flowchart 430 continues, as pixels of the current frame are read (e.g., returning to block 432). If decision logic 434 determines that an overflow condition is present, then the flowchart 430 continues to block 436, where the next incoming pixel of the current frame is dropped. Next, decision logic 438 determines whether the current frame has ended and the next frame has begun. For instance, in one embodiment, this may include detecting a rising edge in the VSYNC signal. If the sensor is still sending the current frame, the flowchart 430 continues to decision logic 440, which determines whether the overflow condition originally detected at logic 434 is still present. If the overflow condition has not recovered, then the flowchart 430 proceeds to block 442, at which the dropped pixel counter is incremented (e.g., to account for the incoming pixel dropped at block 436). The method then returns to block 436 and continues.

If, at decision logic 438, it is detected that the current frame has ended and that the sensor 90 is sending the next frame (e.g., VSYNC rising detected), then the flowchart 430 proceeds to block 450. At block 450, all pixels of the next and subsequent frames are dropped as long as the overflow condition remains (e.g., shown by decision logic 452). As discussed above, a separate counter 406 may track the number of dropped frames, which may be used to adjust audio-video synchronization parameters. If decision logic 452 indicates that the overflow condition has recovered, then the dropped pixels from the initial frame in which the overflow condition first occurred are replaced with a number of undefined pixel values corresponding to the number of dropped pixels from that initial frame, as indicated by the dropped pixel counter. As mentioned above, the undefined pixel values may be all 1's, all 0's, a replacement value programmed into a data register, or may take the value of a previous pixel that was read before the overflow condition (e.g., the last pixel read before the overflow condition was detected). Accordingly, this allows the initial frame to be processed with the correct number of pixels and, at block 446, downstream image processing may continue, which may include writing the initial frame to memory. As also discussed above, depending on the number of pixels that were dropped in the frame, the control logic 84 may either choose to exclude or include the frame when outputting video data (e.g., if the number of dropped pixels is above or below an acceptable dropped pixel threshold). As may be appreciated, overflow handling may be performed separately for each input queue 400 and 402 of the image processing circuitry 32.

Another example of overflow handling that may be implemented in accordance with the present disclosure is shown in FIG. 47 by way of a flowchart 460. Here, overflow handling for an overflow condition that occurs during a current frame but recovers before the end of a current frame is handled in the same manner as shown in FIG. 46 and, therefore, those steps have thus been numbered with like reference numbers 432-446. The difference between the flowchart 460 of FIG. 47 and the flowchart 430 of FIG. 46 pertains to overflow handling when an overflow condition continues into the next frame. For instance, referring to decision logic 438, when the overflow condition continues into the next frame, rather than drop the next frame as in the flowchart 430 of FIG. 46, the flowchart 460 implements block 462, in which the dropped pixel counter is cleared, the sensor input queue is cleared, and the control logic 84 is signaled to drop the partial current frame. By clearing the sensor input queue and dropped pixel counter, the flowchart 460 prepares to acquire the next frame (which now becomes the current frame), returning the method to block 432. As may be appreciated, pixels for this current frame may be read into the sensor input queue. If the overflow condition recovers before the input queue becomes full, then downstream processing resumes. However, if the overflow condition persists, the flowchart 460 will continue from block 436 (e.g., begin dropping pixels until overflow either recovers or the next frame starts).

Statistics Logic

As mentioned above, the statistics logic 140a and 140b may collect various statistics about the image data. These statistics may include information relevant to the sensors 90a and 90b that capture and provide the raw image signals (e.g., Sif0, 94a and Sif1 94b), such as statistics relating to auto-exposure, auto-white balance, auto-focus, flicker detection, black level compensation, and lens shading correction, and so forth. The statistics logic 140a and 140b may also collect statistics used to control aspects of the ISP pipe processing logic 80, such as local tone mapping and local histogram statistics, local thumbnail statistics, fixed pattern noise statistics, and so forth.

An example of some of the components of the statistics logic 140a appears in FIG. 48. It may be recalled that the statistics logic 140a and 140b are substantially identical. As such, only statistics logic 140a is shown in FIG. 48, but it should be appreciated that the statistics logic 140b may contain similar components. The statistics logic 140a may receive raw image data deriving from the first sensor interface 94a (S0), the second sensor interface 94b (S1), or the memory 100 (S2 and S3). The image data may be converted to signed 17-bit format by the scale and offset logic 82, which is discussed above with reference to FIGS. 40-43. Since the scale and offset logic 82 may be implemented as functions of the DMA input, this element is not otherwise shown in FIG. 48. Selection logic 142a may select which of the input signals to process.

The statistics image processing logic 144a may process some of the input image data before collecting statistics in the statistics core 146a. As shown in FIG. 48, however, certain other image data may not be processed through the statistics image processing logic 144a. Image data that is processed through the statistics image processing logic 144a may be decimated, in some embodiments, to facilitate processing. By way of example, before substantial processing by the statistics image processing logic 144a, the image data may be decimated by a factor of four (e.g., 4×4 averaged). If decimating before substantial processing in the statistics image processing logic 144a (e.g., before sensor linearization (SLIN) logic 470), this may be noted by clipped pixel tracking, as will be described below.

The statistics core 146a may collect statistics using 8-bit or 16-bit data. Collecting statistics using 16-bit data may provide more precise statistics and may be advantageous for many applications (e.g., handling image data from high dynamic range (HDR) image sensors 90). Many legacy algorithms may use 8-bit statistics, however, so the statistics core 146a may collect 8-bit or 16-bit statistics based on a selection by the software controlling the ISP pipe processing logic 80. The statistics core 146a may include “3A” statistics collection logic 482 to collect statistics relating to auto-exposure, auto-white balance, auto-focus, and similar operations; fixed pattern noise (FPN) statistics collection logic 484; histogram statistics collection logic 486; and/or local statistics collection logic 488.

The statistics core 146a may receive the output of the IBLC logic 478 and convert the input pixels to 16-bit or 8-bit, scaling the input pixels appropriately. In addition, the FPN statistics collection logic 484 may receive interim image data output by the defective pixel replacement (DPR) block 474. The histogram statistics collection logic 486 may receive image data that is not processed through the statistics image processing logic 144a. Statistics from the statistic core 146a may be output to the memory 100 or to other processing blocks of the ISP pipe processing logic 80. How the components of the statistics core 146a collect statistics will be discussed in greater detail further below, following a discussion of the components of the statistics image processing logic 144a.

As discussed above, the statistics logic 140a and/or 140b may track clipped pixels using clipped pixel tracking logic 480. Although the clipped pixel tracking logic 480 is illustrated as a discrete functional block in FIG. 48, and may track pixels in a centralized way (e.g., an array of flags corresponding to every pixel being processed through the in some embodiments, clipped pixel tracking may be carried out diffusely throughout the statistics logic 140a and/or 140b. For example, pixels passing through the statistics logic 144a and/or 144b may be defined not only by pixel data, but also by a clipped pixel flag that moves with the pixel throughout the statistics logic 140a and/or 140b.

FIG. 223 provides one example of pixel data that may be used in the statistics processing logic 140a and/or 140b. In the example of FIG. 223, a pixel 5300 being processed through the statistics image processing logic 144a or 144b may include signed 17-bit pixel data 5302 and a clipped pixel flag 5304. In other embodiments, the pixel 5300 may include pixel data 5302 of any other suitable bit depth, which may be signed or unsigned. The clipped pixel flag 5304 may represent one or more bits that, when set, indicate that the pixel data 5302 has been clipped—that is, that the pixel data 5302 has been processed in such a way that the pixel data 5302 that some image information has been lost. When the pixel data 5302 has been clipped, the pixel data 5302 may not be reliable for collecting certain statistics.

The clipped pixel flag 5304 may indicate that and/or where the pixel data 5302 was clipped. In one example, the clipped pixel flag 5304 may be a single bit that may indicate only that the pixel 5300 has been clipped somewhere in the statistics image processing logic 144a and/or 144b. In other embodiments, however, the clipped pixel flag 5304 may take up more than one bit. For such embodiments, the clipped pixel flag 5304 may indicate not only that the pixel data 5302 has been clipped, but also the particular operation where it was clipped.

To provide a brief example of the operation of a multi-bit clipped pixel flag 5304, when the black level compensation (BLC) logic 472 causes the pixel 5300 to clip, the clipped pixel flag may be set to a numerical value to indicate that the BLC logic 472 caused the pixel 5300 to clip. For example, the clipped pixel flag 5304 may be a 3-bit value that is set to 0 when the pixel data 5302 is not clipped, to 1 when the sensor linearization (SLIN) logic 470 causes the pixel data 5302 to clip, to 2 when the BLC logic 472 causes the pixel data 5302 to clip, to 3 when the lens shading correction (LSC) logic 476 causes the pixel data 5302 to clip, and 4 when the IBLC logic 478 causes the pixel data 5302 to clip. Subsequently, particular logical blocks of the statistics cores 146a and/or 146b may determine to collect statistics using the pixel 5300 depending on whether clipping in the BLC logic 472, or the LSC logic 476 still results in image data usable by particular logic of the statistics core 146a and/or 146b. As should be appreciated, the above discussion presents only one example of such a multi-bit clipped pixel flag 5304. Other embodiments may include more or fewer bits and may also indicate, for example, when a pixel is clipped by more than one block, or may be concerned only with clipping caused by certain blocks.

In still other examples, the clipped pixel flag 5304 may indicate the extent of pixel data 5302 clipping. For instance, the clipped pixel flag 5304 may be set to a first value when an operation of the statistics image processing logic 144a and/or 144b would have been—had the pixel data 5302 had not been clipped—over the maximum value that can be stored in the pixel data 5302, but beneath a first threshold. The clipped pixel flag 5304 may be set to a second value when an operation of the statistics image processing logic 144a and/or 144b would have been—had the pixel data 5302 had not been clipped—at or above the first threshold.

In any case, the various functional blocks of the statistics cores 146a and/or 146b may use the clipped pixel flag 5304 or any other indications that a specific pixel has been clipped (e.g., discrete counters in the clipped pixel tracking logic 480) in collecting image statistics. For example, software controlling the ISP pipe processing logic 80 may program the various functional blocks of the statistics cores 146a and/or 146b to use or not to use certain pixels in calculating statistics based on whether the pixel has been clipped, where the pixel has been clipped, and/or the extent to which the pixel has been clipped. In this way, statistics collection using clipped pixels may vary depending on the reason for processing the pixels in the ISP pipe processing logic 80. The various functional blocks of the statistics image processing logic 144a may also vary operation based on whether a pixel is indicated as clipped. For instance, a pixel in a filter may not be considered if it has been clipped, which may prevent the clipped pixel from skewing the output with erroneous information.

Any of the statistics collection logic discussed below may include or exclude pixels from statistics collection depending on whether the pixel is indicated as clipped and/or where or to what extent the pixel is indicated as clipped (e.g., as indicated by a clipped pixel flag 5304 or by clipped pixel tracking logic 480). Namely, white balancing may incorrectly identify the color temperature of a scene if clipped pixels are used, so white balancing components of the 3A statistics collection logic 482 may discard clipped pixel values. Similarly, autofocus components of the 3A statistics collection logic 482 may discard clipped pixel values because using blown-out regions of the image data may generate incorrect focal results.

Whether a particular component of the statistics core 146a (including sub components, such as the various elements of the 3A statistics collection logic 482) uses a clipped pixel may be hard-coded or controlled by software. That is, in some embodiments, all components of the statistics core 146a may exclude clipped pixels from statistics. In other embodiments, software may control (e.g., toggle) whether particular components of the statistics core 146a use clipped pixels. Additionally or alternatively, a single global toggle selection may enable software to determine whether all of the components of the statistics core 146a consider clipped pixels in determining statistics.

Statistics Image Processing Logic

The discussion will now turn to the statistics image processing logic 144. It should be appreciated that many of the image processing operations discussed in relation to the statistics logic 140 may be employed in the same or a similar manner by the other image processing functional blocks of the ISP pipe processing logic 80, namely those of the raw processing logic (RAWProc) 150.

Sensor Linearization (SLIN) Logic

Raw image data received from some sensors 90, particularly high dynamic range (HDR) sensors, may be nonlinear. For instance, raw image data in a companding format first may need to be mapped from nonlinear space to a linear space. The sensor linearization logic 470 of the statistics image processing logic 144a may perform such a conversion. One example of the sensor linearization (SLIN) logic 470 appears in FIG. 49.

As seen in FIG. 49, the sensor linearization (SLIN) logic 470 may receive input pixels in raw format (e.g., signed 17-bit raw format) one pixel at a time. An input offset value (block 490) may be applied to each input pixel. If the pixel value exceeds the signed 17-bit range after the input offset is applied, the pixel value may be clamped and an input clip counter may be incremented. A pixel lookup block 492 may obtain a new pixel value by using the output of the input offset logic 490 as an index value to a lookup table (LUT) 494. The LUT 494 may map nonlinear input pixel values to linear output pixel values. In the example of FIG. 49, the LUT 494 of the sensor linearization (SLIN) logic 470 includes two banks of lookup tables 496a and 496b, each including respective lookup tables for each raw color pixel. As may be recalled from the discussion relating to FIG. 2, above, Bayer pixels of the raw image data format may be one of four colors: green-red (Gr), red (R), blue (B), and green-blue (Gb). As such, each bank of lookup tables 496a or 496b may include a respective lookup table (LUT) for each raw input pixel color component. These are represented as Gr LUT 498, R LUT 500, B LUT 502, and Gb LUT 504. After looking up the new pixel value via the pixel lookup block 492, the sensor linearization (SLIN) logic 470 may optionally apply an output offset 506 to produce an output pixel, now linearized, illustrated at numeral 508. If the pixel value after the output offset exceeds the signed 17-bit range, the pixel value may be clamped to the signed 17-bit range and an output clip counter may be incremented.

As seen in a more detailed schematic block diagram of the lookup table bank 496a shown in FIG. 50, each lookup table 498a, 500a, 502a, and 504a may include any suitable number of entries. The entries of the lookup tables 498, 500, 502, and 504 are noted as numerals 512, 514, 516, and 518, respectively. The entries 512, 514, 516, and 518 may be of any suitable number (e.g., 33, 65, 129, or, in the illustrated example, 257, or more) and may have any suitable bit depth (e.g., 8, 10, 12, 14, or, in the illustrated example, 16 bits, or more). The value of the entries 512, 514, 516, and 518 may represent pre-offset output pixel levels that map non-linear sensor values to linear image pixel values. In the example of FIG. 50, the 257 input entries of each lookup table 498, 500, 502, and 504 may be evenly distributed in the range of 8- to 16-bit input pixel values.

Only the lookup table bank 496a is shown in FIG. 50, but it should be appreciated that the lookup table bank 496b may operate in a substantially similar way. Because the lookup tables 498, 500, 502, and 504 are double-banked in the lookup table banks 496a and 496b, firmware may update one of the banks 496a or 496b while the sensor linearization (SLIN) logic 470 is processing the image data using the other bank (e.g., bank 496a). The lookup tables 498, 500, 502, and 504 may be loaded individually, or all four inactive tables can be loaded with the same values.

An example operation of the sensor linearization (SLIN) logic 470 appears in a flowchart 520 of FIG. 51. The flowchart 520 may begin when the sensor linearization (SLIN) logic 470 receives an input pixel in raw format (block 522). The sensor linearization (SLIN) logic 470 may apply an input offset value (block 524). The input offset value that is applied may be a signed value applied before the sensor linearization (SLIN) logic 470 looks up the new value of the pixel in the lookup tables 494. For negative pixel values, the pixel value selected from the lookup table 498, 500, 502, or 504 may be the absolute value of the input pixel. The sign of the image data may be applied after the resulting lookup table output value has been obtained. It may be appreciated that this is equivalent to miring the lookup tables 498, 500, 502, and 504 around zero.

As mentioned above, the 257 input entries 512, 514, 516, or 518 may be evenly distributed in the range of 8- to 16-bit input pixel values. Thus, when the input pixel value falls between the intervals of the 257 entries (e.g., between entries 54 and 55), the output values may be linearly interpolated using the two values between which the input pixel value falls. As should be appreciated, the input bit depth may determine the amount of interpolated bits. For 8-bit input, no interpolation need be performed. For 10-16 bit input pixels, however, the lower 2-8-bits will be used for interpolation. The firmware may thus select the fraction for interpolation based on the bit depth of the input pixels to obtain a output linear pixel output value.

Having retrieved a linearized pixel value from the lookup tables 494, the sensor linearization (SLIN) logic 470 may apply an output offset value (block 528). The output offset value may be signed (i.e., may add or subtract from the value obtained from the lookup tables 494). The sensor linearization (SLIN) logic 470 then may output the resulting linear pixels 508 to be processed by the black level compensation (BLC) block 472.

Black Level Compensation (BLC)

Returning to FIG. 48, the output of the sensor linearization (SLIN) logic 470 may be passed to the black level compensation (BLC) logic 472. The BLC logic 472 may provide for digital gain, offset, and clipping independently for each color component “c” (e.g., R, B, Gr, and Gb for Bayer) on the pixels used for statistics collection. For instance, as expressed by the following operation, the input value for the current pixel is first offset by a signed value, and then multiplied by a gain.
Y=(X+O[c])×G[c] (1),
where X represents the input pixel value for a given color component c (e.g., R, B, Gr, or Gb), O[c] represents a signed 16-bit offset for the current color component c, G[c] represents a gain value for the color component c, and Y represents the output pixel value. In one embodiment, the gain G[c] may be a 16-bit unsigned number with 2 integer bits and 14 fraction bits (e.g., 2.14 in floating point representation), and the gain G[c] may be applied with rounding. By way of example, the gain G[c] may have a range of between 0 to 4 (e.g., 4 times the input pixel value).

Next, as shown by Equation 2 below, the computed value Y, which is signed, may then be then clipped to a minimum and maximum range:
Y=(Y<min[c])?min[c]:(Y>max[c])?max[c]:Y) (2).

The variables min[c] and max[c] may represent signed 16-bit clipping values for the minimum and maximum output values, respectively. In one embodiment, the BLC logic 472 may also be configured to maintain a count of the number of pixels that were clipped above and below maximum and minimum, respectively, per color component. Additionally or alternatively, the clipped pixel tracking logic 480 may globally track pixels clipped throughout the statistics logic 140a. In some embodiments, when the pixel is clipped, a clipped pixel flag associated with the clipped pixel may be set to indicate that the pixel was clipped, that the pixel was clipped by the BLC logic 472, and/or the extent to which the pixel was clipped.

Defective Pixel Replacement

As may be appreciated, the image sensor(s) 90 may not always perfectly capture every pixel of light. Some of the pixels of the sensor(s) 90 may be “defective pixels,” a term that refers to imaging pixels within the image sensor(s) 90 that fail to sense light levels accurately. Defective pixels may attributable to a number of factors, and may include “hot” (or leaky) pixels, “stuck” pixels, and “dead pixels.” A “hot” pixel generally appears as being brighter than a non-defective pixel given the same amount of light at the same spatial location. Hot pixels may result due to reset failures and/or high leakage. For example, a hot pixel may exhibit a higher than normal charge leakage relative to non-defective pixels, and thus may appear brighter than non-defective pixels. Additionally, “dead” and “stuck” pixels may be the result of impurities, such as dust or other trace materials, contaminating the image sensor during the fabrication and/or assembly process, which may cause certain defective pixels to be darker or brighter than a non-defective pixel, or may cause a defective pixel to be fixed at a particular value regardless of the amount of light to which it is actually exposed. Additionally, dead and stuck pixels may also result from circuit failures that occur during operation of the image sensor. By way of example, a stuck pixel may appear as always being on (e.g., fully charged) and thus appears brighter, whereas a dead pixel appears as always being off.

The defective pixel replacement (DPR) logic 474 may correct defective pixels by replacing them with other values before the pixels are considered in statistics collection in the statistics core 146a. With reference again to FIG. 48, it may be seen that the DPR logic 474 appears after the BLC logic 472. By performing defective pixel replacement after, rather than before, black level compensation, the black levels may be more accurately represented (since replacing some of the defective pixels may disadvantageously change the black level of the image data). In other embodiments, however, the DPR logic 474 may occur before the BLC logic 472.

In one embodiment, defective pixel correction is performed independently for each color component (e.g., R, B, Gr, and Gb for a Bayer pattern). Generally, the DPR logic 474 may provide for dynamic defect correction, wherein the locations of defective pixels are determined automatically based upon directional gradients computed using neighboring pixels of the same color. As will be understand, the defects may be “dynamic” in the sense that the characterization of a pixel as being defective at a given time may depend on the image data in the neighboring pixels. By way of example, a stuck pixel that is always on maximum brightness may not be regarded as a defective pixel if the location of the stuck pixel is in an area of the current image that is dominate by brighter or white colors. Conversely, if the stuck pixel is in a region of the current image that is dominated by black or darker colors, then the stuck pixel may be identified as a defective pixel during processing by the DPR logic 474 and corrected accordingly.

The DPR logic 474 may use one or more horizontal neighboring pixels of the same color on each side of a current pixel to determine if the current pixel is defective using pixel-to-pixel directional gradients. If a current pixel is identified as being defective, the value of the defective pixel may be replaced with the value of a horizontal neighboring pixel. For instance, in one embodiment, five horizontal neighboring pixels of the same color that are inside the raw frame 310 (FIG. 21) boundary are used, wherein the five horizontal neighboring pixels include the current pixel and two neighboring pixels on either side. Thus, as illustrated in FIG. 52, for a given color component c and for the current pixel P, horizontal neighbor pixels P0, P1, P2, and P3 may be considered by the DPR logic 474. It should be noted, however, that depending on the location of the current pixel P, pixels outside the raw frame 310 are not considered when calculating pixel-to-pixel gradients.

For instance, as shown in FIG. 52, in a “left edge” case 540, the current pixel P is at the leftmost edge of the raw frame 310 and, thus, the neighboring pixels P0 and P1 outside of the raw frame 310 are not considered, leaving only the pixels P, P2, and P3 (N=3). In a “left edge +1” case 542, the current pixel P is one unit pixel away from the leftmost edge of the raw frame 310 and, thus, the pixel P0 is not considered. This leaves only the pixels P1, P, P2, and P3 (N=4). Further, in a “centered” case 544, pixels P0 and P1 on the left side of the current pixel P and pixels P2 and P3 on the right side of the current pixel P are within the raw frame 310 boundary and, therefore, all of the neighboring pixels P0, P1, P2, and P3 (N=5) are considered in calculating pixel-to-pixel gradients. Additionally, similar cases 546 and 548 may be encountered as the rightmost edge of the raw frame 310 is approached. For instance, given the “right edge −1” case 546, the current pixel P is one unit pixel away the rightmost edge of the raw frame 310 and, thus, the pixel P3 is not considered (N=4). Similarly, in the “right edge” case 548, the current pixel P is at the rightmost edge of the raw frame 310 and, thus, both of the neighboring pixels P2 and P3 are not considered (N=3).

In the illustrated embodiment, for each neighboring pixel (k=0 to 3) within the picture boundary (e.g., raw frame 310), the pixel-to-pixel gradients may be calculated as follows:
Gk=abs(P−Pk),for 0≦k≦3(only for k within the raw frame) (3).
Once the pixel-to-pixel gradients have been determined, defective pixel detection may be performed by the DPR logic 474 as follows. First, it is assumed that a pixel is defective if a certain number of its gradients Gk are at or below a particular threshold, denoted by the variable dprTh. Thus, for each pixel, a count (C) of the number of gradients for neighboring pixels inside the picture boundaries that are at or below the threshold dprTh is accumulated. By way of example, for each neighbor pixel inside the raw frame 310, the accumulated count C of the gradients Gk that are at or below the threshold dprTh may be computed as follows:

C=∑kN⁢(Gk≤⁢dprTh),⁢for⁢⁢0≤k≤3⁢⁢(only⁢⁢for⁢⁢k⁢⁢within⁢⁢the⁢⁢raw⁢⁢frame).(4)
As may be appreciated, depending on the color components, the threshold value dprTh may vary. Next, if the accumulated count C is determined to be less than or equal to a maximum count, denoted by the variable dprMaxC, then the pixel may be considered defective. This logic is expressed below:
if (C≧dprMaxC),then the pixel is defective (5).

Defective pixels are replaced using a number of replacement conventions. For instance, in one embodiment, a defective pixel may be replaced with the pixel to its immediate left, P1. At a boundary condition (e.g., P1 is outside of the raw frame 310), a defective pixel may replaced with the pixel to its immediate right, P2. Further, it should be understood that replacement values may be retained or propagated for successive defective pixel detection operations. For instance, referring to the set of horizontal pixels shown in FIG. 52, if P0 or P1 were previously identified by the DPR logic 474 as being defective pixels, their corresponding replacement values may be used for the defective pixel detection and replacement of the current pixel P.

To summarize the above-discussed defective pixel detection and correction techniques, a flowchart depicting such a process is provided in FIG. 53 and referred to by reference number 560. As shown, process 560 begins at step 562, at which a current pixel (P) is received and a set of neighbor pixels is identified. In accordance with the embodiment described above, the neighbor pixels may include two horizontal pixels of the same color component from opposite sides of the current pixel (e.g., P0, P1, P2, and P3). Next, at step 564, horizontal pixel-to-pixel gradients are calculated with respect to each neighboring pixel within the raw frame 310, as described in Equation 3 above. Thereafter, at step 566, a count C of the number of gradients that are less than or equal to a particular threshold dprTh is determined. As shown at decision logic 568, if C is less than or equal to dprMaxC, then the process 560 continues to step 570, and the current pixel is identified as being defective. The defective pixel is then corrected at step 572 using a replacement value. Additionally, referring back to decision logic 568, if C is greater than dprMaxC, then the process continues to step 574, and the current pixel is identified as not being defective, and its value is not changed.

It should be noted that the defective pixel detection/correction techniques applied during the ISP pipe processing logic 80 statistics processing may be less robust than defective pixel detection/correction that is performed in the ISP pipe logic 82. For instance, as will be discussed in further detail below, defective pixel detection/correction performed in the ISP pipe logic 82 may, in addition to dynamic defect correction, further provide for fixed defect correction, wherein the locations of defective pixels are known a priori and loaded in one or more defect tables. Further, dynamic defect correction may in the ISP pipe logic 82 may also consider pixel gradients in both horizontal and vertical directions, and may also provide for the detection/correction of speckling, as will be discussed below.

Lens Shading Correction (LSC)

The geometric optics of the lens may result in a drop-off in intensity that is roughly proportional to the distance from the lens optical center. Lens shading correction logic 476 may be used to correct these anomalies by applying a gain per pixel to compensate for these drop-offs in intensity.

Referring to FIG. 54, a three-dimensional profile 580 depicting light intensity versus pixel position for a typical lens is illustrated. As shown, the light intensity near the center 582 of the lens gradually drops off towards the corners or edges 584 of the lens. The lens shading irregularities depicted in FIG. 54 may be better illustrated by FIG. 55, which shows a photograph 586 that exhibits drop-offs in light intensity towards the corners and edges. Particularly, it should be noted that the light intensity at the approximate center of the image appears to be brighter than the light intensity at the corners and/or edges of the image.

In accordance with an embodiments, lens shading correction gains may be specified as a two-dimensional grid of gains per color channel (e.g., Gr, R, B, Gb for a Bayer filter). The gain grid points may be distributed at fixed horizontal and vertical intervals. The grid point gain data may be stored in memory external to the ISP circuitry, thus facilitating access to the data without necessitating a load of a portion of the grid into the ISP circuitry's internal memory. Further, because the external memory may include an increased capacity over the ISP circuitry's internal memory, grid point gain data for the entire sensor (or multiple sensors if so equipped) may be stored in the external memory. Thus, as will be described in more detail below, the ISP circuitry may simply reference a pointer to an external memory address where the grid point gain data is stored for the entire sensor and navigate to the relevant portion of the grid point gain data. The lens shading correction gains may be represented in the same order as they Bayer image and, in some embodiments, including a 16-bit gain per color component. As discussed above in FIG. 21, the raw frame 310 may include an active region 312 which defines an area on which processing is performed for a particular image processing operation. With regard to the lens shading correction operation, an active processing region, which may be referred to as the LSC region, is defined within the raw frame region 310. As will be discussed below, the LSC region may be completely inside or at the gain grid boundaries, otherwise results may be undefined.

For instance, referring to FIG. 56, an LSC region 588 and a gain grid 590 that may be defined within an input frame are shown. The LSC region 588 may have a width 592 and a height 594. Further, the starting pixel 595 of the LSC region 588 may be defined by an x-offset 596 and a y-offset 598 with respect to a lens shading gain base 600. For example, the x-offset 596 and y-offset 598 may define a grid frame offset from the lens shading gain base 300 to the first pixel in the LSC region 588. Thus, the relative position of the LSC region 588 to the gain grid 600 may be determined.

The horizontal (x-direction) and vertical (y-direction) grid point intervals 602 and 604, respectively, may be specified independently for each color channel. These grid point intervals 602 and 604 define the intervals between grid points of the same color channel. The grid point interval can be set to an arbitrary value in the horizontal and vertical directions. In the Raw Processing block lens correction shading discussed below, the grid point intervals may be set to 1 or between 4-256. In the statistics block lens shading correction, the grid point intervals may be between 16-256 in units of the Bayer quad. As will be discussed in more detail below, pixel gain values may be interpolated based upon the nearby grid gain values. However, when the intervals are set to 1, these gain values are not interpolated. Instead, the previous gain value read from the LSC gain memory is used.

The horizontal (x-direction) and vertical (y-direction) grid point spacing 606 and 608, respectively, may represent the position of the gain value of the Bayer quad gains relative to the first gain at the lens shading gain base 600. This spacing may be used to set the sampling interval of the gain values in the gain grid 600. In one example, when the gain grid 600 is co-located for all colors, the grid spacing is zero. Alternatively, when the grid gain points are equally spaced, the grid point spacing 606 and 608 will be half the grid intervals 602 and 604, respectively. The grid spacing 606 and 608 will necessarily be less than the grid intervals 602 and 604, respectively. Further, a lens shading correction gain stride 610 may represent the distance between two vertically adjacent gain grids 590.

The lens shading correction (LSC) gains may be represented in the same order as a Bayer image, with 16-bit gain per color component. The color of the first pixel in the LSC grid gain may be programmed by software. Each 16-bit representation may contain an LSC gain value with 13 fractional bits (e.g., a 3.13 bit representation). As can be appreciated, by utilizing the address of lens shading gain base 600 and the grid offsets, the same gain memory can be used while the sensor cropping region is changing. For example, instead of the ISP circuitry having to update grid gain values in internal memory, the ISP circuitry, by merely updating a few parameters (e.g., the grid point intervals 602 and 604), may align the proper grid points for the changed cropping region. By way of example only, this may be useful when cropping is used during digital zooming operations. Further, while the gain grid 600 shown in the embodiment of FIG. 56 is depicted as having generally equally spaced grid points, it should be understood that in other embodiments, the grid points may not necessarily be equally spaced. For instance, in some embodiments, the grid points may be distributed unevenly (e.g., logarithmically), such that the grid points are less concentrated in the center of the LSC region 588, but more concentrated towards the corners of the LSC region 588, typically where lens shading distortion is more noticeable.

In accordance with the presently disclosed lens shading correction techniques, when a current pixel location is located outside of the LSC region 588, no gain is applied (e.g., the pixel is passed unchanged). When the current pixel location is at a gain grid location, the gain value at that particular grid point may be used. However, when a current pixel location is between grid points, the gain may be interpolated using bilinear interpolation. An example of interpolating the gain for the pixel location “G” on FIG. 21 is provided below.

As shown in FIG. 57, the pixel G is between the grid points G0, G1, G2, and G3, which may correspond to the top-left, top-right, bottom-left, and bottom-right gains, respectively, relative to the current pixel location G. The horizontal and vertical size of the grid interval is represented by X and Y, respectively. Additionally, ii and jj represent the horizontal and vertical pixel offsets, respectively, relative to the position of the top left gain G0. Based upon these factors, the gain corresponding to the position G may thus be interpolated as follows:

G=(G⁢⁢0⁢(Y-jj)⁢(X-ii))+(G⁢⁢1⁢(Y-jj)⁢(ii))+(G⁢⁢2⁢(jj)⁢(X-ii))+(G⁢⁢3⁢(ii)⁢(jj))XY.(6⁢a)
The terms in Equation 6a above may then be combined to obtain the following expression:

G=G⁢⁢0⁡[XY-X⁡(jj)-Y⁡(ii)+(ii)⁢(jj)]+G⁢⁢1⁡[Y⁡(ii)-(ii)⁢(jj)]+G⁢⁢2⁡[X⁡(jj)-(ii)⁢(jj)]+G⁢⁢3⁡[(ii)⁢(jj)]XY.(6⁢b)
In one embodiment, since X and Y are constant for the input frame, a reciprocal value may be used to avoid a divide as follows:
G=(G0(Y−jj)(X−ii))+(G1(Y−jj)(ii)+(G2(jj)(X−ii))+(G3(ii)(jj))*recipricol)>>32
where reciprocal=(1<<32)/(XY).

In certain embodiments, the gain may have a range of between 0 and 8×. The interpolated gain between grid points may retain full precision. Further, because the input pixel is signed, the output from the lens shading correction is also signed.

Statistics regarding the lens shading correction input and output pixels may be useful for further processing in the ISP pipeline. For example, lens shading correction statistics may collect a number of pixels that are above a programmable threshold value before and/or after the lens shading correction is applied. For example, in some embodiments, a programmable threshold value may be set to a sensor's saturation value. The lens shading correction statistics may count the number of pixels at or above the sensor's saturation value before lens shading correction is applied. Further, a second threshold value may be set to a desired clip level at the output of the lens shading correction. The lens shading correction statistics may count the number of pixels at or above the desired clip level after lens shading correction has been applied. The lens shading correction statistics may also count the number of pixels that both are above the sensor's saturation value before lens shading correction is applied and are above the desired clip level after the lens shading correction is applied.

The lens shading correction techniques may be further illustrated by the process 612 shown in FIG. 58. As shown, process 612 begins at step 614, at which the position of a current pixel is determined relative to the boundaries of the LSC region 588 of FIG. 56. Next, decision logic 616 determines whether the current pixel position is within the LSC region 588. If the current pixel position is outside of the LSC region 588, the process 612 continues to step 618, and no gain is applied to the current pixel (e.g., the pixel passes unchanged).

If the current pixel position is within the LSC region 588, the process 612 continues to decision logic 620, at which it is further determined whether the current pixel position corresponds to a grid point within the gain grid 590. If the current pixel position corresponds to a grid point, then the gain value at that grid point is selected and applied to the current pixel, as shown at step 622. If the current pixel position does not correspond to a grid point, then the process 612 continues to step 624, and a gain is interpolated based upon the bordering grid points (e.g., G0, G1, G2, and G3 of FIG. 21). For instance, the interpolated gain may be computed in accordance with Equations 6a and 6b, as discussed above. Thereafter, the process 612 ends at step 626, at which the interpolated gain from step 624 is applied to the current pixel.

As will be appreciated, the process 612 may be repeated for each pixel of the image data. For instance, as shown in FIG. 59, a three-dimensional profile depicting the gains that may be applied to each pixel position within a LSC region (e.g. 588) is illustrated. As shown, the gain applied at the corners 628 of the image may be generally greater than the gain applied to the center 630 of the image due to the greater drop-off in light intensity at the corners, as shown in FIGS. 54 and 55. Using the presently described lens shading correction techniques, the appearance of light intensity drop-offs in the image may be reduced or substantially eliminated. For instance, FIG. 60 provides an example of how the photograph 632 from FIG. 55 may appear after lens shading correction is applied. As shown, compared to the original image from FIG. 55, the overall light intensity is generally more uniform across the image. Particularly, the light intensity at the approximate center of the image may be substantially equal to the light intensity values at the corners and/or edges of the image. Additionally, as mentioned above, the interpolated gain calculation (Equations 6a and 6b) may, in some embodiments, be replaced with an additive “delta” between grid points by taking advantage of the sequential column and row incrementing structure. As will be appreciated, this reduces computational complexity.

In further embodiments, in addition to using grid gains, a global gain per color component that is scaled as a function of the distance from the image center is used. The center of the image may be provided as an input parameter, and may be estimated by analyzing the light intensity amplitude of each image pixel in the uniformly illuminated image. The radial distance between the identified center pixel and the current pixel, may then be used to obtain a linearly scaled radial gain, Gr, as shown below:
Gr=Gp[c]×R (7),
where Gp[c] represents a global gain parameter for each color component c (e.g., R, B, Gr, and Gb components for a Bayer pattern), and wherein R represents the radial distance between the center pixel and the current pixel.

With reference to FIG. 61, which shows the LSC region 588 discussed above, the distance R may be calculated or estimated using several techniques. As shown, the pixel C corresponding to the image center may have the coordinates (x0, y0), and the current pixel G may have the coordinates (xG, yG). In one embodiment, the LSC logic 476 may calculate the distance R using the following equation:
R=√{square root over ((xG−x0)2+(yG−y0)2)}{square root over ((xG−x0)2+(yG−y0)2)} (8).

In another embodiment, a simpler estimation formula, shown below, may be utilized to obtain an estimated value for R.
R=α×max(abs(xG−x0),abs(yG−y0))+β×min(abs(xG−x0),abs(yG−y0)) (9).
In Equation 9, the estimation coefficients α and β may be scaled to 8-bit values. By way of example only, in one embodiment, a may be equal to approximately 123/128 and β may be equal to approximately 51/128 to provide an estimated value for R. Using these coefficient values, the largest error may be approximately 4%, with a median error of approximately 1.3%. Thus, even though the estimation technique may be somewhat less accurate than utilizing the calculation technique in determining R (Equation 8), the margin of error is low enough that the estimated values or R are suitable for determining radial gain components for the present lens shading correction techniques.

The radial gain Gr may then be multiplied by the interpolated grid gain value G (Equations 6a and 6b) for the current pixel to determine a total gain that may be applied to the current pixel. The output pixel Y is obtained by multiplying the input pixel value X with the total gain, as shown below:
Y=(G×Gr×X) (10).
Thus, in accordance with the present technique, lens shading correction may be performed using only the interpolated gain, both the interpolated gain and the radial gain components. Alternatively, lens shading correction may also be accomplished using only the radial gain in conjunction with a radial grid table that compensates for radial approximation errors. For example, instead of a rectangular gain grid 590, as shown in FIG. 56, a radial gain grid having a plurality of grid points defining gains in the radial and angular directions may be provided. Thus, when determining the gain to apply to a pixel that does not align with one of the radial grid points within the LSC region 588, interpolation may be applied using the four grid points that enclose the pixel to determine an appropriate interpolated lens shading gain.

Referring to FIG. 62, the use of interpolated and radial gain components in lens shading correction is illustrated by the process 634. It should be noted that the process 634 may include steps that are similar to the process 612, described above in FIG. 58. Accordingly, such steps have been numbered with like reference numerals. Beginning at step 636, the current pixel is received and its location relative to the LSC region 588 is determined. Next, decision logic 638 determines whether the current pixel position is within the LSC region 588. If the current pixel position is outside of the LSC region 588, the process 634 continues to step 640, and no gain is applied to the current pixel (e.g., the pixel passes unchanged). If the current pixel position is within the LSC region 588, then the process 634 may continue simultaneously to step 642 and decision logic 644. Referring first to step 642, data identifying the center of the image is retrieved. As discussed above, determining the center of the image may include analyzing light intensity amplitudes for the pixels under uniform illumination. This may occur during calibration, for instance. Thus, it should be understood that step 642 does not necessarily encompass repeatedly calculating the center of the image for processing each pixel, but may refer to retrieving the data (e.g., coordinates) of previously determined image center. Once the center of the image is identified, the process 634 may continue to step 646, wherein the distance between the image center and the current pixel location (R) is determined. As discussed above, the value of R may be calculated (Equation 8) or estimated (Equation 9). Then, at step 648, a radial gain component Gr may be computed using the distance R and global gain parameter corresponding to the color component of the current pixel (Equation 7). The radial gain component Gr may be used to determine the total gain, as will be discussed in step 650 below.

Referring back to decision logic 644, a determination is made as to whether the current pixel position corresponds to a grid point within the gain grid 590. If the current pixel position corresponds to a grid point, then the gain value at that grid point is determined, as shown at step 652. If the current pixel position does not correspond to a grid point, then the process 634 continues to step 654, and an interpolated gain is computed based upon the bordering grid points (e.g., G0, G1, G2, and G3 of FIG. 21). For instance, the interpolated gain may be computed in accordance with Equations 6a and 6b, as discussed above. Next, at step 650, a total gain is determined based upon the radial gain determined at step 346, as well as one of the grid gains (step 652) or the interpolated gain (step 654). As can be appreciated, this may depend on which branch decision logic 644 takes during the process 634. The total gain is then applied to the current pixel, as shown at step 656. Again, it should be noted that like the process 310, the process 340 may also be repeated for each pixel of the image data.

The use of the radial gain in conjunction with the grid gains may offer various advantages. For instance, using a radial gain allows for the use of single common gain grid for all color components. This may greatly reduce the total storage space required for storing separate gain grids for each color component. For instance, in a Bayer image sensor, the use of a single gain grid for each of the R, B, Gr, and Gb components may reduce the gain grid data by approximately 75%. As will be appreciated, this reduction in grid gain data may decrease implementation costs, as grid gain data tables may account for a significant portion of memory or chip area in image processing hardware. Further, depending upon the hardware implementation, the use of a single set of gain grid values may offer further advantages, such as reducing overall chip area (e.g., such as when the gain grid values are stored in an on-chip memory) and reducing memory bandwidth requirements (e.g., such as when the gain grid values are stored in an off-chip external memory).

When applying the gains using the LSC logic 476 results in a clipped pixel, this may be tracked, and the statistics core 146a and/or 146b may determine whether to use the pixel in certain statistics collection operations based on its clipped status. In one embodiment, the LSC logic 476 may also be configured to maintain a count of the number of pixels that were clipped above and below maximum and minimum, respectively, per color component. Additionally or alternatively, the clipped pixel tracking logic 480 may globally track pixels clipped throughout the statistics logic 140a. In some embodiments, when the pixel is clipped, a clipped pixel flag associated with the clipped pixel may be set to indicate that the pixel was clipped, that the pixel was clipped by the LSC logic 476, and/or the extent to which the pixel was clipped.

Inverse Black Level Compensation (IBLC)

Recalling FIG. 48, the output of the lens shading correction (LSC) logic 476 is subsequently forwarded to the inverse black level compensation (IBLC) logic 478. The IBLC logic 478 provides gain, offset and clip independently for each color component (e.g., R, B, Gr, and Gb), and generally performs the inverse function to the BLC logic 472. For instance, as shown by the following operation, the value of the input pixel is first multiplied by a gain and then offset by a signed value, before being clipped:

Y=((X+O1[c])*G[c])+O[c]

Y=(Y<min[c])?min[c]: (Y>max[c])?max[c]: Y
where X represents the input pixel value for a given color component c (e.g., R, B, Gr, or Gb), O[c] represents a signed 16-bit offset for the current color component c, G[c] represents a gain value for the color component c, and Y represents the output pixel value. In one embodiment, the gain G[c] may have a range of between approximately 0 to 4× (4 times the input pixel value X). The gains G[c] may represent 16-bit unsigned numbers with 14 fraction bits (2.14). The gain may be applied with rounding, and the min[c] and max[c] may be signed 16-bit clip values for the minimum and maximum output values, respectively. The output of the IBLC may be unsigned. Moreover, if the input pixels to the IBLC logic 478 are expected to go negative (when using a negative offset in the BLC logic 472), the IBLC logic 478 may not be bypassed and the minimum clip value may be set to zero. In bypass mode, the lower 16-bits of the pixel data coming from the LSC logic 476 may be passed through. Therefore, negative values (e.g., represented in twos complement) will not be clipped to zero, resulting instead in large positive numbers at the 16-bit unsigned output.

In one embodiment, the IBLC logic 478 may maintain a count of the number of pixels that were clipped above and below maximum and minimum, respectively, per color component. Additionally or alternatively, the clipped pixel tracking counter 480 may globally track pixels clipped throughout the statistics logic 140a, and/or an associated clipped pixel flag (e.g., 5304) may be set.

Statistics Collection

Thereafter, the output of the IBLC logic 478 is received by the statistics core 146, which may provide for the collection of various statistical data points about the image sensor(s) 90, such as those relating to auto-exposure (AE), auto-white balance (AWB), auto-focus (AF), flicker detection, and so forth. Additionally, the statistics core 146 may obtain fixed pattern noise statistics (FPN stats) using the FPN statistics logic 484 and local image statistics (e.g., local tone mapping statistics and thumbnail statistics) using the local statistics logic 488. These various statistics collection blocks of the statistics core 146a will be discussed below.

Before continuing further, it should also be noted that the various statistics collection blocks of the statistics core 146a and/or 146b may vary operation on pixels when the pixels are clipped (e.g., as indicated by a clipped pixel flag associated with the pixel, the clipped pixel tracking logic 480, and so forth). As mentioned above, in some embodiments, when the pixel is clipped, a clipped pixel flag associated with the clipped pixel may be set to indicate that the pixel was clipped, that the pixel was clipped by a particular functional block of the statistics image processing logic 144, and/or the extent to which the pixel was clipped. Certain of the statistics collection blocks may be configured always to exclude a pixel from statistics collection when the pixel is clipped. Additionally or alternatively, some or all of the statistics collection blocks may be programmed by software to consider or not to consider a clipped pixel in it calculations. Thus, the software controlling the ISP pipe processing logic 80 may determine whether to include clipped pixels depending, for example, on whether including clipped pixels would be detrimental to the particular statistics collected.

To provide a brief example, the “3A statistics” block discussed below includes auto-white-balance (AWB) statistics logic. The AWB logic generally is concerned with red and blue pixels, but not green. As such, red or blue pixels that have been clipped (e.g., as indicated by a clipped pixel flag) may not be used by the AWB statistics logic. On the other hand, green pixels that have been clipped (e.g., as indicated by a clipped pixel flag) may be used by the AWB statistics logic. That is, clipping of red or blue pixels may cause AWB statistics to be unreliable, while clipping of green pixels may not. This is only one example, and it should be understood that any of the various statistics collection blocks may selectively use pixels depending on whether they have been clipped.

“3A” Statistics Collection

As may be appreciated, AWB, AE, and AF statistics may be used in the acquisition of images in digital still cameras as well as video cameras. For simplicity, AWB, AE, and AF statistics may be collectively referred to herein as “3A statistics.” In the embodiment of the statistics logic 140a shown in FIG. 48, the architecture for the 3A statistics collection logic 482 may be implemented in hardware, software, or a combination of hardware and software. Further, control software or firmware (e.g., control logic 84) may be used to analyze the statistics data collected by the 3A statistics collection logic 482 and control various parameters of the lens (e.g., focal length), sensor (e.g., analog gains, integration times), and the ISP pipe processing logic 80 (e.g., digital gains, color correction matrix coefficients). In some embodiments, the image processing circuitry 32 may provide flexibility in statistics collection to enable control software or firmware to implement various AWB, AE, and AF algorithms.

With regard to white balancing (AWB), the image sensor response at each pixel may depend on the illumination source, since the light source is reflected from objects in the image scene. Thus, each pixel value recorded in the image scene is related to the color temperature of the light source. For instance, FIG. 63 shows a graph 789 illustrating the color range of white areas under low color and high color temperatures for a YCbCr color space. As shown, the x-axis of the graph 789 represents the blue-difference chroma (Cb) and the y-axis of the graph 789 represents red-difference chroma (Cr) of the YCbCr color space. The graph 789 also shows a low color temperature axis 790 and a high color temperature axis 791. The region 792 in which the axes 790 and 791 are positioned, represents the color range of white areas under low and high color temperatures in the YCbCr color space. It should be understood, however, that the YCbCr color space is merely one example of a color space that may be used in conjunction with auto white balance processing. Other embodiments may use any suitable color space. For instance, in certain embodiments, other suitable color spaces may include a Lab (CIELab) color space (e.g., based on CIE 1976), a red/blue normalized color space (e.g., an R/(R+2G+B) and B/(R+2G+B) color space; a R/G and B/G color space; a Cb/Y and Cr/Y color space, etc.). Accordingly, for the purposes of this disclosure, the axes of the color space used by the 3A statistics collection logic 482 may be referred to as C1 and C2 (as is the case in FIG. 63).

When a white object is illuminated under a low color temperature, it may appear reddish in the captured image. Conversely, a white object that is illuminated under a high color temperature may appear bluish in the captured image. The goal of white balancing is, therefore, to adjust RGB values such that the image appears to the human eye as if it were taken under canonical light. Thus, in the context of imaging statistics relating to white balance, color information about white objects are collected to determine the color temperature of the light source. In general, white balance algorithms may include two main steps. First, the color temperature of the light source is estimated. Second, the estimated color temperature is used to adjust color gain values and/or determine/adjust coefficients of a color correction matrix. Such gains may be a combination of analog and digital image sensor gains, as well as ISP digital gains.

For instance, in some embodiments, the imaging device 30 may be calibrated using multiple different reference illuminants. Accordingly, the white point of the current scene may be determined by selecting the color correction coefficients corresponding to a reference illuminant that most closely matches the illuminant of the current scene. By way of example, one embodiment may calibrate the imaging device 30 using five reference illuminants, a low color temperature illuminant, a middle-low color temperature illuminant, a middle color temperature illuminant, a middle-high color temperature illuminant, and a high color temperature illuminant. As shown in FIG. 64, one embodiment may define white balance gains using the following color correction profiles: Horizon (H) (simulating a color temperature of approximately 2300 degrees), Incandescent (A or IncA) (simulating a color temperature of approximately 2856 degrees), D50 (simulating a color temperature of approximately 5000 degrees), D65 (simulating a color temperature of approximately 6500 degrees), and D75 (simulating a color temperature of approximately 5640 degrees).

Depending on the illuminant of the current scene, white balance gains may be determined using the gains corresponding to the reference illuminant that most closely matches the current illuminant. For instance, if the 3A statistics collection logic 482 (described in more detail with reference to FIG. 65 below) determines that the current illuminant approximately matches the reference middle color temperature illuminant, D50, then white balance gains of approximately 1.37 and 1.23 may be applied to the red and blue color channels, respectively, while approximately no gain (1.0) is applied to the green channels (G0 and G1 for Bayer data). In some embodiments, if the current illuminant color temperature is in between two reference illuminants, white balance gains may be determined via interpolating the white balance gains between the two reference illuminants. Further, while the present example shows an imaging device being calibrated using H, A, D50, D65, and D75 illuminants, it should be understood that any suitable type of illuminant may be used for camera calibration, such as TL84 or CWF (fluorescent reference illuminants), and so forth.

As will be discussed further below, several statistics may be provided for AWB including a two-dimensional (2D) color histogram, and RGB or YCC sums to provide multiple programmable color ranges. For instance, in one embodiment, the 3A statistics collection logic 482 may provide a set of multiple pixel condition filters, of which a subset of the multiple pixel filters may be selected for AWB processing. In one embodiment, eight sets of filters, each with different configurable parameters, may be provided, and three sets of color range filters may be selected from the set for gathering tile statistics, as well as for gathering statistics for each floating window. By way of example, a first selected filter may be configured to cover the current color temperature to obtain accurate color estimation, a second selected filter may be configured to cover the low color temperature areas, and a third selected filter may be configured to cover the high color temperature areas. This particular configuration may enable the AWB algorithm to adjust the current color temperature area as the light source is changing. Further, the 2D color histogram may be used to determine the global and local illuminants and to determine various pixel filter thresholds for accumulating RGB values. Again, it should be understood that the selection of three pixel filters is meant to illustrate just one embodiment. In other embodiments, fewer or more pixel filters may be selected for AWB statistics.

Further, in addition to selecting three pixel filters, one additional pixel filter may also be used for auto-exposure (AE), which generally refers to a process of adjusting pixel integration time and gains to control the luminance of the captured image. For instance, auto-exposure may control the amount of light from the scene that is captured by the image sensor(s) by setting the integration time. In certain embodiments, tiles and floating windows of luminance statistics may be collected via the 3A statistics collection logic 482 and processed to determine integration and gain control parameters.

Further, auto-focus may refer to determining the optimal focal length of the lens in order to substantially optimize the focus of the image. In certain embodiments, floating windows of high frequency statistics may be collected and the focal length of the lens may be adjusted to bring an image into focus. As discussed further below, in one embodiment, auto-focus adjustments may use coarse and fine adjustments based upon one or more metrics, referred to as auto-focus scores (AF scores) to bring an image into focus. Further, in some embodiments, AF statistics/scores may be determined for different colors, and the relativity between the AF statistics/scores for each color channel may be used to determine the direction of focus.

As discussed above, the control logic 84, which may be a dedicated processor in the image processing circuitry 32 of the device 10, may process the collected statistical data to determine one or more control parameters for controlling the imaging device 30 and/or the image processing circuitry 32. For instance, such the control parameters may include parameters for operating the lens of the image sensor 90 (e.g., focal length adjustment parameters), image sensor parameters (e.g., analog and/or digital gains, integration time), as well as ISP pipe processing parameters (e.g., digital gain values, color correction matrix (CCM) coefficients). Additionally, as mentioned above, in certain embodiments, statistical processing may occur at a precision of 8-bits and, thus, raw pixel data having a higher bit-depth may be down-scaled to an 8-bit format for statistics purposes. As discussed above, down-scaling to 8-bits (or any other lower-bit resolution) may reduce hardware size (e.g., area) and also reduce processing complexity, as well as allow for the statistics data to be more robust to noise (e.g., using spatial averaging of the image data). The statistical processing of the statistics logic 146a and 146b may, alternatively, use a precision of 16 bits. Although the 16-bit statistics may be more precise than 8-bit statistics, some software may rely on legacy 8-bit statistics. As such, the statistics cores 146a and 146b may be controlled by software to operate at 8-bit and/or 16-bit precision.

With the foregoing in mind, FIG. 65 is a block diagram depicting logic for implementing one embodiment of the 3A statistics collection logic 482. As shown, the 3A statistics collection logic 482 may receive a signal 793 representing Bayer RGB data which, as shown in FIG. 48, may correspond to the output of the inverse BLC logic 478. The 3A statistics collection logic 482 may process the Bayer RGB data 793 to obtain various statistics 794, which may represent the output STATS0 of the 3A statistics collection logic 482, as shown in FIG. 48, or alternatively the output STATS1 of a statistics logic associated with the Sensor1 statistics processing unit 140b.

In the illustrated embodiment, for the statistics to be more robust to noise, the incoming Bayer RGB pixels 793 are first averaged by logic 795. For instance, the averaging may be performed in a window size of 4×4 sensor pixels consisting of four 2×2 Bayer quads (e.g., a 2×2 block of pixels representing the Bayer pattern), and the averaged red (R), green (G), and blue (B) values in the 4×4 window may be computed and, if desired, converted to 8-bits. This process is illustrates in more detail with respect to FIG. 66, which shows a 4×4 window 796 of pixels formed as four 2×2 Bayer quads 797. Using this arrangement, each color channel includes a 2×2 block of corresponding pixels within the window 796, and same-colored pixels may be summed and averaged to produce an average color value for each color channel within the window 796. For instance, red pixels 799 may be averaged to obtain an average red value (RAV) 803, and the blue pixels 800 may be averaged to obtain an average blue value (BAV) 804 within the sample 796. With regard to averaging of the green pixels, several techniques may be used since the Bayer pattern has twice as many green samples as red or blue samples. In one embodiment, the average green value (GAV) 802 may be obtained by averaging just the Gr pixels 798, just the Gb pixels 801, or all of the Gr and Gb pixels 798 and 801 together. In another embodiment, the Gr and Gb pixels 798 and 801 in each Bayer quad 797 may be averaged, and the average of the green values for each Bayer quad 797 may be further averaged together to obtain GAV 802. As may be appreciated, the averaging of the pixel values across pixel blocks may provide for the reduction of noise. Further, it should be understood that the use of a 4×4 block as a window sample is merely intended to provide one example. Indeed, in other embodiments, any suitable block size may be used (e.g., 8×8, 16×16, 32×32, etc.). It may be appreciated that a pixel may be considered clipped if any of the average values (RAV) 803, (BAY) 804, or (GAV) 802 is clipped.

Thereafter, the downscaled Bayer RGB values 806 are input to the color space conversion logic units 807 and 808. Because some of the 3A statistics data may rely upon pixel pixels after applying color space conversion, the color space conversion (CSC) logic 807 and CSC logic 808 may be configured to convert the down-sampled Bayer RGB values 806 into one or more other color spaces. In one embodiment, the CSC logic 807 may provide for a non-linear space conversion and the CSC logic 808 may provide for a linear space conversion. Thus, the CSC logic units 807 and 808 may convert the raw image data from sensor Bayer RGB to another color space (e.g., sRGBlinear, sRGB, YCbCr, etc.) that may be more ideal or suitable for performing white point estimation for white balance.

In the present example, the non-linear CSC logic 807 may be configured to perform a 3×3 matrix multiply, followed by a non-linear mapping implemented as a lookup table, and further followed by another 3×3 matrix multiply with an added offset. This allows for the 3A statistics color space conversion logic 807 to replicate the color processing of the RGB processing logic 160 in the ISP pipe processing logic 80 (e.g., applying white balance gain, applying a color correction matrix, applying RGB gamma adjustments, and performing color space conversion) for a given color temperature. It may also provide for the conversion of the Bayer RGB values to a more color consistent color space such as CIELab, or any of the other color spaces discussed above (e.g., YCbCr, a red/blue normalized color space, etc.). Under some conditions, a Lab color space may be more suitable for white balance operations because the chromaticity is more linear with respect to brightness.

As shown in FIG. 65, the output pixels from the Bayer RGB down-scaled signal 806 are processed with a first 3×3 color correction matrix (3A_CCM), referred to herein by reference number 808. In the present embodiment, the 3A_CCM 809 may be configured to convert from a camera RGB color space (camRGB), to a linear sRGB calibrated space (sRGBlinear). A programmable color space conversion that may be used in one embodiment is provided:

sRlinear =3A_CCM_00*R + 3A_CCM_01*G +

3A_CCM_02*B + 3A_CCM_OffsetR

SGlinear = 3A_CCM_10*R + 3A_CCM_11*G +

3A_CCM_12*B + 3A_CCM_OffsetG

sBlinear = 3A_CCM_20*R + 3A_CCM_21*G +

3A_CCM_22*B + 3A_CCM_OffsetB

sRlinear = (sRlinear < 3A_CCM_MIN[0]) ? 3A_CCM_MIN[0]:

(sRlinear > 3A_CCM_MAX[0]):

3A_CCM_MAX[0]):sRlinear

sGlinear = (sGlinear < 3A_CCM_MIN[1]) ? 3A_CCM_MIN[1]:

(sGlinear > 3A_CCM_MAX[1]):

3A_CCM_MAX[1]: sGlinear

sBlinear = (SGlinear < 3A_CCM_MIN[2]) ? 3A_CCM_MIN[2]:

(sBlinear > 3A_CCM_MAX[2]):

3A_CCM_MAX[2]: sBlinear

where the variables 3A_CCM—00 through 3A_CCM—22 represent signed coefficients of the matrix 808, the variable 3A_CCM_OffsetR represents a red pixel offset value, the variable 3A_CCM_OffsetG represents a green pixel offset value, and the variable 3A_CCM_OffsetB represents a blue pixel offset value. The variables 3A_CCM_MIN[c] and 3A_CCM_MAX[c] refer to maximum and minimum allowable pixel values, where c represents the color component red (0), green (1), or blue (2). These values may vary depending, for example, on the bit depth of the image data. Thus, each of the sRlinear, sGlinear, and sBlinear, components of the sRGBlinear color space may be determined first determining the sum of the red, blue, and green down-sampled Bayer RGB values with corresponding 3A_CCM coefficients applied, and then clipping this value to the minimum and maximum pixel values for 8-16-bit pixel data, as appropriate. The resulting sRGBlinear values are represented in FIG. 65 by reference number 810 as the output of the 3A_CCM 809. Additionally, the 3A statistics collection logic 482 may maintain a count of the number of clipped pixels for each of the sRlinear, sGlinear, and sBlinear components, as expressed below:

3A_CCM_R_clipcount_low : number of sRlinear pixels <

3A_CCM_MIN[0] clipped

3A_CCM_R_clipcount_high : number of sRlinear pixels >

3A_CCM_MAX[0] clipped

3A_CCM_G_clipcount_low : number of sGlinear pixels <

3A_CCM_MIN[1] clipped

3A_CCM_G_clipcount_high : number of sGlinear pixels >

3A_CCM_MAX[1] clipped

3A_CCM_B_clipcount_low : number of sBlinear pixels <

3A_CCM_MIN[2] clipped

3A_CCM_B_clipcount_high : number of sBlinear pixels >

3A_CCM_MAX[2] clipped

Next, the sRGBlinear pixels 810 may be processed using a non-linear lookup table 811 to produce sRGB pixels 812. The lookup table 811 may contain entries of 16-bit values, with each table entry value representing an output level. In one embodiment, the look-up table 811 may include 257 evenly distributed input entries. A table index may represent values in steps of 1 to 256, depending on the bit depth (e.g., 8-bit to 16-bit). When the input pixel value falls between intervals, the output values may be linearly interpolated.

As may be appreciated, the sRGB color space may represent the color space of the final image produced by the imaging device 30 for a given white point, as white balance statistics collection is performed in the color space of the final image produced by the image device. In one embodiment, a white point may be determined by matching the characteristics of the image scene to one or more reference illuminants based, for example, upon red-to-green and/or blue-to-green ratios. For instance, one reference illuminant may be D65, a CIE standard illuminant for simulating daylight conditions. In addition to D65, calibration of the imaging device 30 may also be performed for other different reference illuminants, and the white balance determination process may include determining a current illuminant so that processing (e.g., color balancing) may be adjusted for the current illuminant based on corresponding calibration points. By way of example, in one embodiment, the imaging device 30 and 3A statistics collection logic 482 may be calibrated using, in addition to D65, a cool white fluorescent (CWF) reference illuminant, the TL84 reference illuminant (another fluorescent source), and the IncA (or A) reference illuminant, which simulates incandescent lighting. Additionally, as discussed above, various other illuminants corresponding to different color temperatures (e.g., H, IncA, D50, D65, and D75, etc.) may also be used in camera calibration for white balance processing. Thus, a white point may be determined by analyzing an image scene and determining which reference illuminant most closely matches the current illuminant source.

Referring still to the non-linear CSC logic 807, the sRGB pixel output 812 of the look-up table 811 may be further processed with a second 3×3 color correction matrix 813, referred to herein as 3A_CSC. In the depicted embodiment, the 3A_CSC matrix 813 is shown as being configured to convert from the sRGB color space to the YCbCr color space, though it may be configured to convert the sRGB values into other color spaces as well. By way of example, the following programmable color space conversion may be used:

Y= 3A_CSC_00*sR + 3A_CSC_01*sG +

3A_CSC_02*sB + 3A_CSC_OffsetY

Y= (Y < 3A_CSC_MIN_Y) ? 3A_CSC_MIN_Y:

(Y > 3A_CSC_MAX_Y) ? 3A_CSC_MAX_Y: Y

C1=3A_CSC_10*sR + 3A_CSC_11*sG +

3A_CSC_12*sB

C2= 3A_CSC_20*sR + 3A_CSC_21*sG +

3A_CSC_22*sB

where 3A_CSC—00-3A_CSC—22 represent signed coefficients for the matrix 813 and 3A_CSC OffsetY represent signed offsets, and C1 and C2 represent different colors (e.g., blue-difference chroma (Cb) and red-difference chroma (Cr), respectively, in one embodiment). It should be understood that C1 and C2 may represent any suitable difference chroma colors, and need not necessarily be Cb and Cr. At this point, camC1 and camC2 pixels may be signed. The chroma scaling is optionally performed next:

C1 = C1 * ChromaScale * 255 / ((Y>>8) ? (Y>>8): 1); and

C2 = C2 * ChromaScale * 255 / ((Y>>8) ? (Y>>8): 1);

where ChromaScale is a scaling factor between 0 and 8. ChromaScale may take two possible values depending on the sign of camC1:

where 3A_CSC_MIN_C1, 3A_CSC_MIN_C2, 3A_CSC_MAX_C1, and 3A_CSC_MAX_C2 represent maximum and minimum values. The resulting output of the linear transform 813 may be a YC1C2 signal 814.

As shown above, in determining each component of YCbCr, appropriate coefficients from the matrix 813 are applied to the sRGB values 812 and the result is summed with a corresponding offset. Essentially, this step is a 3×1 matrix multiplication step. This result from the matrix multiplication is then clipped between a maximum and minimum value. The associated minimum and maximum clipping values may be programmable and may depend, for instance, on particular imaging or video standards (e.g., BT.601 or BT.709) being used.

The 3A statistics collection logic 482 may also maintain a count of the number of clipped pixels for each of the Y, C1, and C2 components, as expressed below. In some embodiments, the number of clipped pixels of each of the Y, C1, and C2 components may be maintained independent of clipped pixel tracking using clipped pixel flags (e.g., as shown in FIG. 223). The 3A statistics collection logic 482 may vary its operation based on either or both forms of clipped pixel tracking

3A_CSC_Y_clipcount_low

: number of Y

pixels < 3A_CSC_MIN_Y clipped

3A_CSC_Y_clipcount_high

: number of Y

pixels > 3A_CSC_MAX_Y clipped

3A_CSC_C1_clipcount_low

: number of C1

pixels < 3A_CSC_MIN_C1 clipped

3A_CSC_C1_clipcount_high

: number of C1

pixels > 3A_CSC_MAX_C1 clipped

3A_CSC_C2_clipcount_low

: number of C2

pixels < 3A_CSC_MIN_C2 clipped

3A_CSC_C2_clipcount_high

: number of C2

pixels > 3A_CSC_MAX_C2 clipped

The output pixels from the Bayer RGB down-sample signal 806 may also be provided to the linear color space conversion logic 808, which may be configured to implement a camera color space conversion. For instance, the output pixels 806 from the Bayer RGB down-sample logic 795 may be processed via another 3×3 color conversion matrix (3A_CSC2) 815 of the CSC logic 808 to convert from sensor RGB (camRGB) to a linear white-balanced color space (camYC1C2), wherein C1 and C2 may correspond to Cb and Cr, respectively. In one embodiment, the chroma pixels may be scaled by luma, which may be beneficial in implementing a color filter that has improved color consistency and is robust to color shifts due to luma changes. An example of how the camera color space conversion may be performed using the 3×3 matrix 815 is provided below:

camY

= 3A_CSC2_00*R + 3A_CSC2_01*G +

3A_CSC2_02*B + 3A— CSC2_OffsetY

camY

= (camY < 3A— CSC2_MIN_Y) ? 3A_CSC2_MIN_Y:

(camY > 3A_CSC2_MAX_Y)

? 3A_CSC2_MAX_Y: camY

camC1

= (3A_CSC2_10*R + 3A_CSC2_11*G + 3A_CSC2_12*B)

camC2

= (3A_CSC2_20*R + 3A_CSC2_21*G + 3A_CSC2_22*B)

where 3A_CSC2—00-3A_CSC2—22 represent signed coefficients for the matrix 815, 3A_CSC2_OffsetY represents a signed offset for camY, and camC1 and camC2 represent different colors (e.g., blue-difference chroma (Cb) and red-difference chroma (Cr), respectively). As shown above, to determine camY, corresponding coefficients from the matrix 815 are applied to the Bayer RGB values 806, and the result is summed with 3A_Offset2Y. This result is then clipped between a maximum and minimum value. As discussed above, the clipping limits may be programmable.

At this point, the camC1 and camC2 pixels of the output 816 are signed. As discussed above, in some embodiments, chroma pixels may be scaled. For example, one technique for implementing chroma scaling is shown below:

camC1

= camC1 * ChromaScale * 255 / ((camY>>8) ? (camY>>8): 1)

camC2

= camC2 * ChromaScale * 255 / ((camY>>8) ? (camY>>8): 1)

where ChromaScale represents a floating point scaling factor between 0 and 8. The expression (camY? camY:1) is meant to prevent a divide-by-zero condition. That is, if camY is equal to zero, the value of camY is set to 1. Further, in one embodiment, ChromaScale may be set to one of two possible values depending on the sign of camC1. For instance, as shown below, ChomaScale may be set to a first value (ChromaScale0) if camC1 is negative, or else may be set to a second value (ChromaScale1):

ChromaScale =

ChromaScale0 if(camC1 < 0)

ChromaScale1 otherwise

Thereafter, chroma offsets are added, and the camC1 and camC2 chroma pixels are clipped, as shown below, to generate corresponding unsigned pixel values:

camC1

= C1 + 3A— CSC2_OffsetC1

camC2

= C2 + 3A— CSC2_OffsetC2

camC1

= (camC1 < 3A_CSC2_MIN_C1) ? 3A_CSC2_MIN_C1:

(camC1 > 3A_CSC2_MAX_C1) ? 3A_CSC2_MAX_C1:

camC1

camC2

= (camC2 < 3A_CSC2_MIN_C2) ? 3A_CSC2_MIN_C2:

(camC2 > 3A_CSC2_MAX_C2) ? 3A_CSC2_MAX_C2:

camC2

wherein 3A_CSC2—00-3A_CSC2—22 are signed coefficients of the matrix 815, and 3A_Offset2C1 and 3A_Offset2C2 are signed offsets. Further, the number of pixels that are clipped for camY, camC1, and camC2 may be counted, as shown below:

3A_CSC2_Y_clipcount_low

: number of camY

pixels < 3A_CSC2_MIN_Y clipped

3A_CSC2_Y_clipcount_high

: number of camY

pixels > 3A_CSC2_MAX_Y clipped

3A_CSC2_C1_clipcount_low

: number of camC1

pixels < 3A_CSC2_MIN_C1 clipped

3A_CSC2_C1_clipcount_high

: number of camC1

pixels > 3A_CSC2_MAX_C1 clipped

3A_CSC2_C2_clipcount_low

: number of camC2

pixels < 3A_CSC2_MIN_C2 clipped

3A_CSC2_C2_clipcount_high

: number of camC2

pixels > 3A_CSC2_MAX_C2 clipped

Thus, the non-linear and linear color space conversion logic 807 and 808 may, in the present embodiment, provide pixel data in various color spaces: sRGBlinear (signal 810), sRGB (signal 812), YCbYr (signal 814), and camYCbCr (signal 816). It should be understood that the coefficients for each conversion matrix 809 (3A_CCM), 813 (3A_CSC), and 815 (3A_CSC2), as well as the values in the look-up table 811, may be independently set and programmed.

Referring still to FIG. 65, the chroma output pixels from either the non-linear color space conversion (YCbCr 814) or the camera color space conversion (camYCbCr 816) may be used to generate a two-dimensional (2D) color histogram 817. As shown, selection logic 818 and 819, which may be implemented as selection logics or by any other suitable logic, may be configured to select between luma and chroma pixels from either the non-linear or camera color space conversion. The selection logic 818 and 819 may operate in response to respective control signals, which, in one example, may be supplied by the main control logic 84 of the image processing circuitry 32 (FIG. 7) and may be set via software.

For the present example, it may be assumed that the selection logic 818 and 819 select the YC1C2 color space conversion (814), where the first component is Luma, and where C1, C2 are the first and second colors (e.g., Cb, Cr). A 2D histogram 817 in the C1-C2 color space is generated for one window. For instance, the window may be specified with a column start and width and a row start and height. The window position and size may be a multiple of 4 pixels. In one example, the color histogram 817 may include 64×64 bins for a total of 4096 bins. The bin boundaries may be at a fixed interval. To allow for zooming and panning the histogram collection in specific areas of the colorspace, a pixel scaling and offset may be specified. Values of C1 and C2 may be in the range [0,63] after offset and scaling, and may be used to determine the bin. The bin indices for C1 and C2, referred to herein by C1idx and C2idx, may be determined as follows:

C1idx = (C1_scale * (C1 − C1_offset))>>16

C2idx = (C2_scale * (C2 − C2_offset))>>16

In the equations above, C1_scale and C2_scale may be 17-bit unsigned integer scale values, and C1_offset and C2_offset may be 16-bit unsigned values. Allowed values for C1_scale and C2_scale may be in the range 0 to 2^16 to represent a floating point scale between 0 and 1. Once the indices are determined, the color histogram bins are incremented by a Count value if the bin indices are in the range [0, 63], as shown below. Effectively, this allows for weighting the color counts based on luma values (e.g., brighter pixels are weighted more heavily, instead of weighting everything equally (e.g., by 1)):

if (C1idx >= 0 && C1idx <= 63 && C2idx >= 0 && C2idx <= 63)

StatsC1C2Hist[C2idx][C1idx] += Count;

where Count is determined based on the selected luma value, Y in this example. As may be appreciated, the steps represented above may be implemented by a bin update logic block 821. Further, in one embodiment, multiple luma thresholds may be set to define luma intervals. By way of example, 15 luma thresholds referred to as Ythd[15] may define 16 luma intervals (e.g., with a first interval starting at 0 and the last interval ending at 65535). The Count values CountArr[15] may be defined for each interval. For instance, Count may be selected (e.g., by pixel condition logic 820) based on luma thresholds as follows:

Count = CountArr[15]; // initialize to last interval

for (level=0; level < 15)

{

if (Y <= Ythd[level])

{

Count = CountArr[level];

break;

}

}

As should be appreciated, in some embodiments, the Count value may or may not include clipped pixels. That is, in some embodiments, software may be able to program the bin update logic block 821 to consider a pixel only when the clipped pixel flag of the pixel has not been set.

With the foregoing in mind, FIG. 67 illustrates the color histogram with scaling and offsets set to zero for both C1 and C2. The divisions within the CbCr space represent each of the 64×64 bins (4096 total bins). FIG. 68 provides an example of zooming and panning within the 2D color histogram for additional precision, in which the input data has a bit depth of 16 bits. A rectangular area 822 specifies the location of the 64×64 bins.

At the start of a frame of image data, bin values are initialized to zero. For each pixel going into the 2D color histogram 817, the bin corresponding to the matching C1C2 value is incremented by a determined Count value which, as discussed above, may be based on the luma value. For each bin within the 2D histogram 817, the total pixel count is reported as part of the collected statistics data (e.g., STATS0). In one embodiment, the total pixel count for each bin may have a resolution of 25-bits, whereby an allocation of internal memory equal to 4096×25 bits is provided.

In some embodiments, RGB, sRGBlinear, sRGB or YC1C2 sums may be accumulated conditional on camYC1C2 or YC1C2 pixel masks or camYC1C2 or YC1C2 pixel conditions. These sums may be accumulated in conditional accumulation logic 823 as shown in FIG. 65. A more detailed view of the conditional accumulation logic 823 appears in FIG. 69. In the example of FIG. 69, the C1C2 signal 814 or the camY signal 816 may be selected by selection logic 824, 825, 826, and/or 827. The selected signal C1C2 signal 814 or the camY signal 816 may be used in conditional accumulation, as may be the RGB signal 806, the sRGBlinear signal 810, the sRGB signal 812, as selectable by selection logic 828, 829, 830, and/or 831. That is, the output of the selection logic 828, 829, 830, and/or 831 may be used to develop one of four counts, Count1, Count2, Count3, or Count4, in the illustrated example, via accumulation logic 832, 833, 834, and 835, respectively. As will be discussed below, the accumulation logic 832, 833, 834, and/or 835 may develop the counts based on one of several (e.g., one of eight different) pixel conditions 836, 837, and/or 838. Any other suitable number of different conditions may be employed. Additionally or alternatively, the accumulation logic 832, 833, 834, and/or 835 may develop the counts based on a pixel mask 839 or the camY signal 816 (clipped in clipping logic 840. Selection logic 841, 842, 843, and 844 may select from among these signals.

As noted above, in some embodiments, RGB, sRGBlinear, sRGB or YC1C2 sums may be accumulated conditional on a camYC1C2 or YC1C2 pixel mask. The Y, C1 and C2 values from either output of the non-linear color space conversion or the output of the camera color space conversion may be used to conditionally select RGB, sRGBlinear, sRGB or YC1C2 values to accumulate. In the example of FIG. 69, the pixel mask defines a 2D weighting map indexed by C1C2 colors. It may also conditioned by brightness—that is, a pixel may be included in the statistics if Ymin<=Y<=Ymax.

The 2D pixel filter mask 839 essentially may be the inverse of the 2D color histogram 817. It may contain a 2-dimensional array of weights. The mask may be specified as a 64×64 2D weight map. Each entry may contain a 4-bit weight, but any other suitable size weighting value may be used. The current C1 and C2 values may be scaled to provide the index into the 2D table to lookup the weight. The weight may be used to multiply the input value (RGB, sRGBlinear, sRGB, or YC1C2) for each qualifying pixel and then added to the RGB, sRGBlinear, sRGB, or YC1C2 pixel sums. The mask indices in C1 and C2, C1idx and C2idx, may be determined as follows:

C1idx = (C1_scale * (C1 − C1_offset))>>16; and

C2idx = (C2_scale * (C2 − C2_offset))>>16;

where C1_scale and C2_scale are 17-bit unsigned integer scale values, and C1_offset and C2_offset are 16-bit unsigned values. The allowed values of C1_scale and C2_scale may be in the range 0 to 2^16, and thus may represent a floating point scale between 0 and 1.0. The weight may be looked up in the table if the mask indices are in the range [0, 63], and applied to the input pixel values. When the pixel mask 839 is disabled, all pixels are accumulated in the pixel mask 839 by setting weight to 1. The process may be summarized as follows:

if (Pixel Mask is disabled)

Weight = 1

else

{

Weight = 0

if (C1idx >= 0 && C1idx <= 63 && C2idx >= 0 &&

C2idx <= 63 && Ymin <= Y <= Ymax

Weight = StatsC1C2Mask[C2idx][C1idx];

}

Rsum += (R * Weight (or Ysum))

Gsum += (G * Weight (or C1sum))

Bsum += (B * Weight (or C1sum))

Count = Count + Weight

Similarly to the pixel filter condition, in addition to pixel sums, the sum of horizontal and vertical positions of pixels that satisfied the pixel mask is reported. Doing so may allow software to compute the centroid of the window for the pixels that satisfy the condition by taking the average of the horizontal and vertical position sums.

The following statistics may be collected for qualifying pixels: 32-bit sums in 8-bit mode Or 40-bit sums in 16-bit mode: (Rsum, Gsum, Bsum) or (SRlinear—sum, SGlinear—sum, SBlinear—sum), or (sRsum, sGsum, sBsum) or (Ysum, C1sum, C2sum), a 24-bit pixel count, Count, which is a sum of the number of pixels that were included in the statistic (software can use the sum to generate an average in a tile or window). Note also that the Count may be incremented by the weights such that the Count can be used for computing the weighted average values from the sums.

Referring back to FIG. 65, the Bayer RGB pixels (signal 806), sRGBlinear pixels (signal 810), sRGB pixels (signal 812), and YC1C2 (e.g., YCbCr) pixels (signal 814) are provided to the set of pixel conditions 836, 837 . . . 838, whereby RGB, sRGBlinear, sRGB, YC1C2, or camYC1C2 sums may be accumulated conditionally upon either camYC1C2 or YC pixel conditions. That is, Y, C1 and C2 values from either output of the non-linear color space conversion (YC1C2) or the output of the camera color space conversion (camYC1C2) are used to conditionally select RGB, sRGBlinear, sRGB or YC1C2 values to accumulate. While the present embodiment depicts the 3A statistics collection logic 482 as having 8 conditions 836, 837 . . . 838, it should be understood that any number of pixel condition filters may be provided.

The pixels selected by the selection logic 828, 829, 830, and/or 831 may be accumulated. In one embodiment, the pixel condition may be defined using thresholds C1_min, C1_max, C2_min, C2_max, as shown in graph 789 of FIG. 63. A pixel is included in the statistics if it satisfies the following conditions:

1. C1_min<=C1<=C1_max

2. C2_min<=C2<=C2_max

3. abs((C2_delta*C1)−(C1_delta*C2)+Offset)<distance_max

4. Ymin<=Y<=Ymax.
Referring to graph 845 of FIG. 70, in one embodiment, the point 846 represents the values (C2, C1) corresponding to the current YC1C2 pixel data. C1 delta may be determined as the difference between C1—1 and C1—0, and C2_delta may be determined as the difference between C2—1 and C2—0. As shown in FIG. 70, the points (C1—0, C2—0) and (C1—1, C2—1) may define the minimum and maximum boundaries for C1 and C2. The Offset may be determined by multiplying C1_delta by the value 848 (C2_intercept) at where the line 847 intercepts the axis C2. Thus, assuming that Y, C1, and C2 satisfy the minimum and maximum boundary conditions, the selected pixels (Bayer RGB, sRGBlinear, sRGB, and YC1C2/camYC1C2) is included in the accumulation sum if its distance 849 from the line 847 is less than distance_max 850, which may be distance 849 in pixels from the line multiplied by a normalization factor:

distance_max=distance*sqrt(C1_delta^2+C2_delta^2)
In this example, distance, C1_delta and C2_delta may have a range of −255 to 255 when operating in 8-bit mode. Thus, distance_max 850 may be represented by 17 bits for 8-bit mode operation. When operating in 16-bit mode, distance C1_delta and C2_delta may have a range of −65535 to 65535. Thus, distance_max 834 may be represented by 33 bits for 16-bit mode operation. The points (C1—0, C2—0) and (C1—1, C2—1), as well as parameters for determining distance_max (e.g., normalization factor(s)), may be provided as part of the pixel condition logic 836, 837 . . . 839. As may be appreciated, the pixel condition logic 836, 837 . . . 839 may be configurable/programmable.

While the example shown in FIG. 70 depicts a pixel condition based on two sets of points (C1—0, C2—0) and (C1—1, C2—1), in additional embodiments, certain pixel filters may define more complex shapes and regions upon which pixel conditions are determined. For instance, FIG. 71 shows embodiments where a pixel filter may define a five-sided polygon 851 using points (C1—0, C2—0), (C1—1, C2—1), (C1—2, C2—2) and (C1—3, C2—3), and (C1—4, C2—4). Each side 852a-e may define a line condition. However, unlike the case shown in FIG. 70 (e.g., the pixel may be on either side of line 847 as long as distance_max is satisfied), the condition may be that the pixel (C1, C2) may be located on the side of the line 852a-e such that it is enclosed by the polygon 851. Thus, the pixel (C1, C2) is counted when the intersection of multiple line conditions is met. For instance, in FIG. 71, such an intersection occurs with respect to pixel 853a. However, pixel 853b fails to satisfy the line condition for line 852d and, therefore, would not be counted in the statistics when processed by a pixel filter configured in this manner.

In a further embodiment, shown in FIG. 72, a pixel condition may be determined based on overlapping shapes. For instance, FIG. 72 shows how a pixel filter may have pixel conditions defined using two overlapping shapes, here rectangles 8548a and 854b defined by points (C1—0, C2—0), (C1—1, C2—1), (C1—2, C2—2) and (C1—3, C2—3) and points (C1—4, C2—4), (C1—5, C2—5), (C1—6, C2—6) and (C1—7, C2—7), respectively. In this example, a pixel (C1, C2) may satisfy line conditions defined by such a pixel filter by being enclosed within the region collectively bounded by the shapes 854a and 854b (e.g., by satisfying the line conditions of each line defining both shapes). For instance, in FIG. 72, these conditions are satisfied with respect to pixel 855a. However, pixel 855b fails to satisfy these conditions (specifically with respect to line 856a of rectangle 854a and line 855b of rectangle 854b) and, therefore, would not be counted in the statistics when processed by a pixel filter configured in this manner.

For each pixel filter, qualifying pixels are identified based on the pixel conditions and, for qualifying pixel values, the following statistics may be collected by the 3A statistics engine 742: 32-bit sums in 8-bit mode or 36-bit sums in 16-bit mode: (Rsum, Gsum, Bsum) or (SRlinear—sum, SGlinear—sum, SBlinear—sum), or (sRsum, sGsum, SBsum) or (Ysum, C1sum, C2sum) and a 24-bit pixel count, Count, which may represent the sum of the number of pixels that were included in the statistic. In one embodiment, software may use the sum to generate an average in within a tile or window.

When the camYC1C2 pixels are selected by a pixel filter, color thresholds may be performed on scaled chroma values. For instance, since chroma intensity at the white points increases with luma value, the use of chroma scaled with the luma value in the pixel filter 824 may, in some instances, provide results with improved consistency. For example, minimum and maximum luma conditions may allow the filter to ignore dark and/or bright areas. If the pixel satisfies the YC1C2 pixel condition, the RGB, sRGBlinear, sRGB or YC1C2 values are accumulated. The selection of the pixel values by the selection logic 825 may depend on the type of information needed. For instance, for white balance, typically RGB or sRGBlinear pixels are selected. For detecting specific conditions, such as sky, grass, skin tones, etc., a YCC or sRGB pixel set may be more suitable.

In the present embodiment, eight sets of pixel conditions may be defined, one associated with each of the pixel filters. Some pixel conditions may be defined to carve an area in the C1-C2 color space (FIG. 63) where the white point is likely to be. This may be determined or estimated based on the current illuminant. Then, accumulated RGB sums may be used to determine the current white point based on the R/G and/or B/G ratios for white balance adjustments. Further, some pixel conditions may be defined or adapted to perform scene analysis and classifications. For example, some pixel filters and windows/tiles may be used to detect for conditions, such as blue sky in a top portion of an image frame, or green grass in a bottom portion of an image frame. This information can also be used to adjust white balance. Additionally, some pixel conditions may be defined or adapted to detect skin tones. For such filters, tiles may be used to detect areas of the image frame that have skin tone. By identifying these areas, the quality of skin tone may be improved by, for example, reducing the amount of noise filter in skin tone areas and/or decreasing the quantization in the video compression in those areas to improve quality.

The 3A statistics collection logic 482 may also provide for the collection of luma data. For instance, the luma value, camY, from the camera color space conversion (camYC1C2) may be used for accumulating luma sum statistics. In one embodiment, the following luma information is may be collected by the 3A statistics collection logic 482:

Ysum

: sum of camY

cond(Ysum)

: sum of camY that satisfies the condition:

Ymin <= camY < Ymax

Ycount1

: count of pixels where camY < Ymin,

Ycount2

: count of pixels where camY >= Ymax

Here, Ycount1 may represent the number of underexposed pixels and Ycount2 may represent the number of overexposed pixels. This may be used to determine whether the image is overexposed or underexposed. For instance, if the pixels do not saturate, the sum of camY (Ysum) may indicate average luma in a scene, which may be used to achieve a target AE exposure. For instance, in one embodiment, the average luma may be determined by dividing Ysum by the number of pixels. Further, by knowing the luma/AE statistics for tile statistics and window locations, AE metering may be performed. For instance, depending on the image scene, it may be desirable to weigh AE statistics at the center window more heavily than those at the edges of the image, such as may be in the case of a portrait.

In the presently illustrated embodiment, the 3A statistics collection logic may be configured to collect statistics in tiles and windows. In the illustrated configuration, one window may be defined for tile statistics 863. The window may be specified with a column start and width, and a row start and height. In one embodiment, the window position and size may be selected as a multiple of four pixels and, within this window, statistics are gathered in tiles of arbitrary sizes. By way of example, all tiles in the window may be selected such that they have the same size. The tile size may be set independently for horizontal and vertical directions and, in one embodiment, the maximum limit on the number of horizontal tiles may be set (e.g., a limit of 128 horizontal tiles). Further, in one embodiment, the minimum tile size may be set to 8 pixels wide by 4 pixels high, for example. Below are some examples of tile configurations based on different video/imaging modes and standards to obtain a window of 16×16 tiles:

VGA 640×480: the interval 40×30 pixels

HD 1280×720: the interval 80×45 pixels

HD 1920×1080: the interval 120×68 pixels

5 MP 2592×1944: the interval 162×122 pixels

8 MP 3280×2464: the interval 205×154 pixels

With regard to the present embodiment, from the eight available pixel filters 824 (PF0-PF7), four may be selected for tile statistics 863. For each tile, the following statistics may collected:

In the above-listed statistics, Count0-3 represents the count of pixels that satisfy pixel conditions corresponding to the selected four pixel filters. For example, if pixel filters PF0, PF1, PF5, and PF6 are selected as the four pixel filters for a particular tile or window, then the above-provided expressions may correspond to the Count values and sums corresponding to the pixel data (e.g., Bayer RGB, sRGBlinear, sRGB, YC1Y2, camYC1C2) which is selected for those filters. Additionally, the Count values may be used to normalize the statistics (e.g., by dividing color sums by the corresponding Count values). As shown, depending at least partially upon the types of statistics needed, the selected pixels filters may be configured to select between either one of Bayer RGB, sRGBlinear, or sRGB pixel data, or YC1C2 (non-linear or camera color space conversion depending on selection by logic) pixel data, and determine color sum statistics for the selected pixel data. Additionally, as discussed above the luma value, camY, from the camera color space conversion (camYC1C2) is also collected for luma sum information for auto-exposure (AE) statistics.

Additionally, the 3A statistics collection logic 482 may also be configured to collect statistics 861 for multiple windows. For instance, in one embodiment, up to eight floating windows may be used, with any rectangular region having a multiple of four pixels in each dimension (e.g., height×width), up to a maximum size corresponding to the size of the image frame. However, the location of the windows is not necessarily restricted to multiples of four pixels. For instance, windows can overlap with one another.

In the present embodiment, four pixel filters may be selected from the available eight pixel filters for each window. Statistics for each window may be collected in the same manner as for tiles, discussed above. Thus, for each window, the following statistics 861 may be collected:

In the above-listed statistics, Count0-3 represents the count of pixels that satisfy pixel conditions corresponding to the selected four pixel filters for a particular window. From the eight available pixel filters, the four active pixel filters may be selected independently for each window. Additionally, one of the sets of statistics may be collected using pixel filters or the camY luma statistics. The window statistics collected for AWB and AE may, in one embodiment, be mapped to one or more registers.

Referring still to FIG. 65, the 3A statistics collection logic 482 may also be configured to acquire luma row sum statistics 859 for one window using the luma value, camY, for the camera color space conversion. This information may be used to detect and compensate for flicker. Flicker is generated by a periodic variation in some fluorescent and incandescent light sources, typically caused by the AC power signal. For example, referring to FIG. 73, a graph illustrating how flicker may be caused by variations in a light source is shown. Flicker detection may thus be used to detect the frequency of the AC power used for the light source (e.g., 50 Hz or 60 Hz). Once the frequency is known, flicker may be avoided by setting the image sensor's integration time to an integer multiple of the flicker period.

To detect for flicker, the camera luma, camY, is accumulated over each row. Due to the down-sample of the incoming Bayer data, each camY value may corresponds to 4 rows of the original raw image data. Control logic and/or firmware may then perform a frequency analysis of the row average or, more reliably, of the row average differences over consecutive frames to determine the frequency of the AC power associated with a particular light source. For example, with respect to FIG. 73, integration times for the image sensor may be based on times t1, t2, t3, and t4 (e.g., such that integration occurs at times corresponding to when a lighting source exhibiting variations is generally at the same brightness level.

In one embodiment, a luma row sum window may be specified and statistics 859 are reported for pixels within that window. By way of example, for 1080p HD video capture, assuming a window of 1024 pixel high, 256 luma row sums are generated with 1-row resolution. Each accumulated value may be expressed with up to 32 bits for 16-bit camY values, for up to 1024 samples per row and up to 64 rows.

The 3A statistics collection logic 146 of FIG. 65 may also provide for the collection of auto-focus (AF) statistics 842 by way of the auto-focus statistics logic 5841. A functional block diagram showing embodiments of the AF statistics logic 5841 in more detail is provided in FIG. 74. As shown, the AF statistics logic 5841 may include a horizontal filter 5843 and an edge detector 5844 which is applied to the original Bayer RGB (not down-sampled), two 3×3 filters 5846 on Y from Bayer, and two 3×3 filters 5847 on camY. In general, the horizontal filter 5843 provides a fine resolution statistics per color component, the 3×3 filters 5846 may provide fine resolution statistics on BayerY (Bayer RGB with 3×1 transform (logic 5845) applied), and the 3×3 filters 5847 may provide coarser two-dimensional statistics on camY (since camY is obtained using down-scaled Bayer RGB data, i.e., logic 5815). Further, the logic 5841 may include logic 5852 for decimating the Bayer RGB data (e.g., 2×2 averaging, 4×4 averaging, etc.), and the decimated Bayer RGB data 5853 may be filtered using 3×3 filters 5854 to produce a filtered output 5855 for decimated Bayer RGB data. The present embodiment provides for 16 windows of statistics. At the raw frame boundaries, edge pixels are replicated for the filters of the AF statistics logic 841. The various components of the AF statistics logic 5841 are described in further detail below.

First, the horizontal edge detection process includes applying the horizontal filter 5843 for each color component (R, Gr, Gb, B) followed by an optional edge detector 5844 on each color component. Thus, depending on imaging conditions, this configuration allows for the AF statistic logic 5841 to be set up as a high pass filter with no edge detection (e.g., edge detector disabled) or, alternatively, as a low pass filter followed by an edge detector (e.g., edge detector enabled). For instance, in low light conditions, the horizontal filter 5843 may be more susceptible to noise and, therefore, the logic 5841 may configure the horizontal filter as a low pass filter followed by an enabled edge detector 5844. As shown, the control signal 5848 may enable or disable the edge detector 5844. The statistics from the different color channels are used to determine the direction of the focus to improve sharpness, since the different colors may focus at different depth. In particular, the AF statistics logic 5841 may provide for techniques to enabling auto-focus control using a combination of coarse and fine adjustments (e.g., to the focal length of the lens). Embodiments of such techniques are described in additional detail below.

In one embodiment the horizontal filter may be a 7-tap filter. The 7-tap horizontal filter may be followed by an optional edge detector on Red, Green and Blue samples. Thus, the AF statistics collection may be set up as a high pass filter with no edge detection. Additionally or alternatively, it can be set up as a low pass filter followed by an edge detector. The statistics from the different color channels may be used to determine the direction of the focus to improve sharpness, since the different colors may focus at different depths. The horizontal filter may be defined as follows:

Here, each coefficient af_horzfilt_coeff[0:3] may be in the range [−2, 2], and i represents the input pixel index for R, Gr, Gb or B. The filtered output out(i) may be clipped between a minimum and maximum value of −255 and 255, respectively. The filter coefficients may be defined independently per color component.

The optional edge detector 5844 may follow the output of the horizontal filter 5843. In one embodiment, the edge detector 5844 may be defined as:

edge(i) = abs(−2*out(i−1) + 2*out(i+1)) + abs(−out(i−2) + out(i+2))

edge (i) = max(0, min(65535, edge (i)))

Thus, the edge detector 5844, when enabled, may output a value based upon the two pixels on each side of the current input pixel i. The result may be clipped to a 16-bit value between 0 and 65535.

Depending on whether an edge is detected, the final output of the pixel filter (e.g., filter 5843 and detector 5844) may be selected as either the output of the horizontal filter 5843 or the output of the edge detector 5844. For instance, the output 5849 of the edge detector 5844 may be edge(i) if an edge is detected, or may be the absolute value of the horizontal filter output out(i) if no edge is detected. When operating in a 16-bit mode, the final output of the pixel filter may be selected to be either the output of the horizontal filter or the output of the edge detector the 16-bit mode):

edge(i)=(af_horzfilt_edge_en)? edge(i): abs(out(i))

In an 8-bit mode, the result is right shifted by 8 before accumulation:

edge(i)=(edge(i)>>8)

For each window, the accumulated value edge_sum[R,Gr,Gb,B], can selected to be either: (1) the sum of edge(j,i) for each pixel over the window, or (2) the maximum value of edge(j) across a line in the window, max(edge), summed over the lines in the window. The value of edge(j,i) is only accumulated if it is above a programmable threshold. In 8-bit mode, the number of bits required to store the maximum value of edge_sum[R,Gr,Gb,B] may be 30 bits, assuming a maximum AF window size of 4096×4096 (8 bit edge result, plus 22 bits AF window size). In 16-bit mode, the number of bits required may be 38 bits, assuming a maximum AF window size of 4096×4096 (with a 16-bit edge result, plus 22 bits for AF window size). In this case, the 32 least significant bits (LSBs) of the results are stored in one register, and the upper 6 most significant bits (MSBs) of the results are stored in a second register.

As discussed, the 3×3 filters 5847 for camY luma may include two programmable 3×3 filters, referred to as F0 and F1, which are applied to camY. The result of the filter 5847 goes to either a squared function or an absolute value function. The result is accumulated over a given AF window for both 3×3 filters F0 and F1 to generate a luma edge value. In one embodiment, the luma edge values at each camY pixel are defined as follows:

edgecamY_FX(j,i)

= FX * camY

= FX(0,0) * camY (j−1, i−1) + FX(0,1) * camY

(j−1, i) + FX(0,2) * camY (j−1, i+1) + FX(1,0) *

camY (j, i−1) + FX(1,1) * camY (j, i) + FX(1,2) *

camY (j, i+1) + FX(2,0) * camY (j+1, i−1) +

FX(2,1) * camY (j+1, i) + FX(2,2) * camY (j+1,

i+1)

edgecamY_FX(j,i)

= f(max(−65535, min(65535, edgecamY_FX(j,i))))

f(a)

= a{circumflex over ( )}2 or abs(a) for 16-bit mode, or

f(a)

= (a{circumflex over ( )}2)>>16 or (abs(a)>>8) for 8-bit mode

where FX represents the 3×3 programmable filters, F0 and F1, with signed coefficients in the range [−4, 4]. The indices j and i represent pixel locations in the camY image. As discussed above, the filter on camY may provide coarse resolution statistics, since camY is derived using down-scaled (e.g., 4×4 to 1) Bayer RGB data. For instance, in one embodiment, the filters F0 and F1 may be set using a Scharr operator, which offers improved rotational symmetry over a Sobel operator, an example of which is shown below:

F⁢⁢0=[-303-10010-303]F⁢⁢1=[-3-10-30003103]

For each window, the accumulated values 5850 determined by the filters 5847, edgecamY_FX_sum (where FX=F0 and F1), can selected to be either (1) the sum of edgecamY_FX(j,i) for each pixel over the window, or (2) the maximum value of edgecamY_FX(j) across a line in the window, summed over the lines in the window. In one embodiment, edgecamY_FX_sum may saturate to a 32-bit value when f(a) is set to a^2 to provide “peakier” statistics with a finer resolution. To avoid saturation, a maximum window size X*Y in raw frame pixels may be set such that it does not exceed a total of 1024×1024 pixels (e.g., i.e. X*Y<=1048576 pixels, with 16 bits per pixel plus 16 bits for AF window size). As noted above, f(a) may also be set as an absolute value to provide more linear statistics. In 16-bit mode, the number of bits required may be 52 bits, when a maximum AF window size of 4096×4096 (32 bits per pixel, plus 20 bits for AF window size) is used. For such a case, the 32 least significant bits (LSBs) of the results are stored in one register, and the upper 20 most significant bits (MSBs) of the results are stored in another register.

The AF 3×3 filters 846 on Bayer Y may defined in a similar manner as the 3×3 filters in camY, but they are applied to luma values Y generated from a Bayer quad (2×2 pixels). First, 8-bit Bayer RGB values are converted to Y with programmable coefficients in the range [0, 4] to generate a white balanced Y value, as shown below. The AF 3×3 filters on Y from Bayer are defined in a similar manner as the 3×3 filters in camY, but they are applied to Luma values Y generated from a Bayer quad (2×2 pixels). First, 16-bit Bayer RGB values are transformed to Y with programmable coefficients in the range [0, 4) to generate a white balanced Y:

Like the filters 5847 for camY, the 3×3 filters 5846 for bayerY luma may include two programmable 3×3 filters, referred to as F0 and F1, which are applied to bayerY. The result of the filter 5846 goes to either a squared function or an absolute value function. The result is accumulated over a given AF window for both 3×3 filters F0 and F1 to generate a luma edge value. In one embodiment, the luma edge values at each bayerY pixel are defined as follows:

where FX represents the 3×3 programmable filters, F0 and F1, with signed coefficients in the range [−4, 4]. The indices j and i represent pixel locations in the bayerY image. As discussed above, the filter on Bayer Y may provide fine resolution statistics, since the Bayer RGB signal received by the AF logic 5841 is not decimated. By way of examples only, the filters F0 and F1 of the filter logic 846 may be set using one of the following filter configurations:

[-1-1-1-18-1-1-1-1]⁢[-6106100-106-10-6]⁢[0-10-120000]

For each window, the accumulated values 5851 determined by the filters 5846, edgebayerY_FX_sum (where FX=F0 and F1), can selected to be either (1) the sum of edgebayerY_FX(j,i) for each pixel over the window, or (2) the maximum value of edgebayerY_FX(j) across a line in the window, summed over the lines in the window. In 8-bit mode, edgebayerY_FX_sum may saturate to 32-bits when f(a) is set to a^2. Thus, to avoid saturation, the maximum window size X*Y in raw frame pixels should be set such that it does not exceed a total of 512×512 pixels (e.g., X*Y<=262144, with 16 bits per pixel plus 16 bits for the AF window size). As discussed above, setting f(a) to a^2 may provide for peakier statistics, while setting f(a) to abs(a) may provide for more linear statistics. In 16-bit mode, the number of bits required may be 54 bits, assuming a maximum AF window size of 4096×4096, with 32 bits per pixel, plus 22 bits for AF window size. For such a case, the 32 least significant bits (LSBs) of the results are stored in one register, and the upper 22 most significant bits (MSBs) of the results are stored in a second register.

As discussed above, statistics 5842 for AF are collected for 16 windows. The windows may be any rectangular area with each dimension being a multiple of 4 pixels. Because each filtering logic 5846 and 5847 includes two filters, in some instances, one filter may be used for normalization over 4 pixels, and may be configured to filter in both vertical and horizontal directions. Further, in some embodiments, the AF logic 5841 may normalize the AF statistics by brightness. This may be accomplished by setting one or more of the filters of the logic blocks 5846 and 5847 as bypass filters. In certain embodiments, the location of the windows may be restricted to multiple of 4 pixels, and windows are permitted to overlap. For instance, one window may be used to acquire normalization values, while another window may be used for additional statistics, such as variance, as discussed below. In one embodiment, the AF filters (e.g., 5843, 5846, 5847) may not implement pixel replication at the edge of an image frame and, therefore, in order for the AF filters to use all valid pixels, the AF windows may be set such that they are each at least 4 pixels from the top edge of the frame, at least 8 pixels from the bottom edge of the frame and at least 12 pixels from the left/right edge of the frame. In 8-bit mode, the following statistics may be collected and reported for each window:

In 16-bit mode, the following statistics may be collected and reported per window:

38-bit edgeGr_sum for Gr

38-bit edgeR_sum for R

38-bit edgeB_sum for B

38-bit edgeGb_sum for Gb

52-bit edgebayerY_F0_sum for Y from Bayer for filter0

52-bit edgebayerY_F1_sum for Y from Bayer for filter1

54-bit edgecamY_F0_sum for camY for filter0

54-bit edgecamY_F1_sum for camY for filter1

The number of elements may include 16 (windows)×8 (Gr, R, B, Gb, bayerY_F0, bayerY_F1, camY_F0, camY_F1)×64 bits (1024 bytes). The most significant bits (MSBs) may be stored in one register and the remaining least significant bits (LSBs) may be stored in a second register. In addition to the output of the filter, the input pixel and the input pixel squared may also be reported for each of the 16 AF windows. This may be used, for example, to normalize the AF score.

Thus, in one embodiment, the accumulated value per window may be selected between: the output of the filter (which may be configured as a default setting), the input pixel, or the input pixel squared. The selection may be made for each of the 16 AF windows, and may apply to all of the 8 AF statistics (listed above) in a given window. This may be used to normalize the AF score between two overlapping windows, one of which is configured to collect the output of the filter and one of which is configured to collect the input pixel sum. Additionally, for calculating pixel variance in the case of two overlapping windows, one window may be configured to collect the input pixel sum, and another to collect the input pixel squared sum, thus providing for a variance that may be calculated as:
Variance=(avg_pixel2)−(avg_pixel)^2

Using the AF statistics, the ISP control logic 84 (FIG. 7) may be configured to adjust a focal length of the lens of an image device (e.g., 30) using a series of focal length adjustments based on coarse and fine auto-focus “scores” to bring an image into focus. As discussed above, the 3×3 filters 5847 for camY may provide for coarse statistics, while the horizontal filter 5843 and edge detector 5844 may provide for comparatively finer statistics per color component, while the 3×3 filters 5846 on BayerY may provide for fine statistics on BayerY. Further, the 3×3 filters 5854 on a decimated Bayer RGB signal 853 may provide coarse statistics for each color channel. As discussed further below, AF scores may be calculated based on filter output values for a particular input signal (e.g., sum of filter outputs F0 and F1 for camY, BayerY, Bayer RGB decimated, or based on horizontal/edge detector outputs, etc.).

FIG. 75 shows a graph 5857 that depicts curves 5858 and 5860 which represent coarse and fine AF scores, respectively. As shown, the coarse AF scores based upon the coarse statistics may have a more linear response across the focal distance of the lens. Thus, at any focal position, a lens movement may generate a change in an auto focus score which may be used to detect if the image is becoming more in focus or out of focus. For instance, an increase in a coarse AF score after a lens adjustment may indicate that the focal length is being adjusted in the correct direction (e.g., towards the optical focal position).

However, as the optical focal position is approached, the change in the coarse AF score for smaller lens adjustments steps may decrease, making it difficult to discern the correct direction of focal adjustment. For example, as shown on graph 857, the change in coarse AF score between coarse position (CP) CP1 and CP2 is represented by ΔC12, which shows an increase in the coarse from CP1 to CP2. However, as shown, from CP3 to CP4, the change ΔC34 in the coarse AF score (which passes through the optimal focal position (OFP)), though still increasing, is relatively smaller. It should be understood that the positions CP1-CP6 along the focal length L are not meant to necessarily correspond to the step sizes taken by the auto-focus logic along the focal length. That is, there may be additional steps taken between each coarse position that are not shown. The illustrated positions CP1-CP6 are only meant to show how the change in the coarse AF score may gradually decrease as the focal position approaches the OFP.

Once the approximate position of the OFP is determined (e.g., based on the coarse AF scores shown in FIG. 75, the approximate position of the OFP may be between CP3 and CP5), fine AF score values, represented by curve 860 may be evaluated to refine the focal position. For instance, fine AF scores may be flatter when the image is out of focus, so that a large lens positional change does not cause a large change in the fine AF score. However, as the focal position approaches the optical focal position (OFP), the fine AF score may change sharply with small positional adjustments. Thus, by locating a peak or apex 862 on the fine AF score curve 860, the OFP may be determined for the current image scene. Thus, to summarize, coarse AF scores may be used to determine the general vicinity of the optical focal position, while the fine AF scores may be used to pinpoints a more exact position within that vicinity.

In one embodiment, the auto-focus process may begin by acquiring coarse AF scores along the entire available focal length, beginning at position 0 and ending at position L (shown on graph 857) and determine the coarse AF scores at various step positions (e.g., CP1-CP6). In one embodiment, once the focal position of the lens has reached position L, the position may reset to 0 before evaluating AF scores at various focal positions. For instance, this may be due to coil settling time of a mechanical element controlling the focal position. In this embodiment, after resetting to position 0, the focal position may be adjusted toward position L to a position that first indicated a negative change in a coarse AF score, here position CP5 exhibiting a negative change ΔC45 with respect to position CP4. From position CP5, the focal position may be adjusted in smaller increments relative to increments used in the coarse AF score adjustments (e.g., positions FP1, FP2, FP3, etc.) back in the direction towards position 0, while searching for a peak 862 in the fine AF score curve 860. As discussed above, the focal position OFP corresponding to the peak 862 in the fine AF score curve 860 may be the optimal focal position for the current image scene.

As may be appreciated, the techniques described above for locating the optimal area and optimal position for focus may be referred to as “hill climbing,” in the sense that the changes in the curves for the AF scores 858 and 860 are analyzed to locate the OFP. Further, while the analysis of the coarse AF scores (curve 858) and the fine AF scores (curve 860) is shown as using same-sized steps for coarse score analysis (e.g., distance between CP1 and CP2) and same-sized steps for fine score analysis (e.g., distance between FP1 and FP2), in some embodiments, the step sizes may be varied depending on the change in the score from one position to the next. For instance, in one embodiment, the step size between CP3 and CP4 may be reduced relative to the step size between CP1 and CP2 since the overall delta in the coarse AF score (ΔC34) is less then the delta from CP1 to CP2 (ΔC12).

A method 864 depicting this process is illustrated in FIG. 76. Beginning at block 865, a coarse AF score is determined for image data at various steps along the focal length, from position 0 to position L (FIG. 75). Thereafter, at block 866, the coarse AF scores are analyzed and the coarse position exhibiting the first negative change in the coarse AF score is identified as a starting point for fine AF scoring analysis. For instance, subsequently, at block 867, the focal position is stepped back towards the initial position 0 at smaller steps, with the fine AF score at each step being analyzed until a peak in the AF score curve (e.g., curve 860 of FIG. 75) is located. At block 868, the focal position corresponding to the peak is set as the optimal focal position for the current image scene.

As discussed above, due to mechanical coil settling times, the embodiment of the technique shown in FIG. 76 may be adapted to acquire coarse AF scores along the entire focal length initially, rather than analyzing each coarse position one by one and searching for an optimal focus area. Other embodiments, however, in which coil settling times are less of a concern, may analyze coarse AF scores one by one at each step, instead of searching the entire focal length.

In certain embodiments, the AF scores may be determined using white balanced luma values derived from Bayer RGB data. For instance, the luma value, Y, may be derived by decimating a 2×2 Bayer quad by a factor of 2, as shown in FIG. 77, or by decimating a 4×4 pixel block consisting of four 2×2 Bayer quads by a factor of 4, as shown in FIG. 78. In one embodiment, AF scores may be determined using gradients. In another embodiment, AF scores may be determined by applying a 3×3 transform using a Scharr operator, which provides rotational symmetry while minimizing weighted mean squared angular errors in the Fourier domain. By way of example, the calculation of a coarse AF score on camY using a common Scharr operator (discussed above) is shown below:

AFScorecoarse=f([-303-10010-303]×in)+f([-3-10-30003103]×in),
where in represents the decimated luma Y value. In other embodiments, the AF score for both coarse and fine statistics may be calculated using other 3×3 transforms.

Auto focus adjustments may also be performed differently depending on the color components, since different wavelengths of light may be affected differently by the lens, which is one reason the horizontal filter 843 is applied to each color component independently. Thus, auto-focus may still be performed even in the present of chromatic aberration in the lens. For instance, because red and blue typically focuses at a different position or distance with respect to green when chromatic aberrations are present, relative AF scores for each color may be used to determine the direction to focus. This is better illustrated in FIG. 79, which shows the optimal focal position for blue, red, and green color channels for a lens 870. As shown, the optimal focal positions for red, green, and blue are depicted by reference letters R, G, and B respectively, each corresponding to an AF score, with a current focal position 872. Generally, in such a configuration, it may be desirable to select the optimal focus position as the position corresponding to the optimal focal position for green components (e.g., since Bayer RGB has twice as many green as red or blue components), here position G. Thus, it may be expected that for an optimal focal position, the green channel should exhibit the highest auto-focus score. Thus, based on the positions of the optimal focal positions for each color (with those closer to the lens having higher AF scores), the AF logic 5841 and associated control logic 84 may determine which direction to focus based on the relative AF scores for blue, green, and red. For instance, if the blue channel has a higher AF score relative to the green channel (as shown in FIG. 79), then the focal position is adjusted in the negative direction (towards the image sensor) without having to first analyze in the positive direction from the current position 872. In some embodiments, illuminant detection or analysis using color correlated temperatures (CCT) may be performed.

Further, as mentioned above, variance scores may also be used. For instance, pixel sums and pixel squared sum values may be accumulated for block sizes (e.g., 8×8-32×32 pixels), and may be used to derive variance scores (e.g., avg_pixel2)-(avg_pixel)^2). The variances may be summed to get a total variance score for each window. Smaller block sizes may be used to obtain fine variance scores, and larger block sizes may be used to obtain coarser variance scores.

Referring to the 3A statistics collection logic 482 of FIG. 65, the logic 146 may also be configured to collect component histograms 874 and 876. As may be appreciated, histograms may be used to analyze the pixel level distribution in an image. This may be useful for implementing certain functions, such as histogram equalization, where the histogram data is used to determine the histogram specification (histogram matching). By way of example, luma histograms may be used for AE (e.g., for adjusting/setting sensor integration times), and color histograms may be used for AWB. To provide a few examples, histograms may be 256, 128, 64 or 32 bins (where the top 8, 7, 6, and 5 bits of the pixel is used to determine the bin, respectively) for each color component, as specified by a bin size (BinSize).

A scale factor and offset may be applied to determine what range of the pixel data is collected. For example, the bin number may be obtained as follows:

idx=(hist_scale*(pixel−hist_offset))>>16.
In the equation above, hist_scale may represent a 17-bit unsigned number. Values of hist_scale that may be allowed may fall in the range 0 to 2^16, to represent a floating point scale between 0 and 1.0. The color histogram bins are incremented only if the bin indices are in the range [0, 255]:

if (idx >= 0 && idx < 256)

StatsHist[idx] += Count.

In the present example, the statistics logic 140 may include two histogram units. This first histogram 874 (Hist0) may be configured to collect pixel data as part of the statistics collection after the 4×4 decimation in the 3A statistics logic 482. For Hist0, the components may be selected to be RGB, sRGBlinear, sRGB or YC1C2 using selection circuit 880. Keeping in mind FIG. 48 while considering FIG. 68, the second histogram 876 (Hist1) shown in FIG. 68 may be configured to collect pixel data before the statistics pipeline, as generally illustrated by the histogram logic 486 of FIG. 48. Since the input to the statistics logic 140 can be negative, since the input interface may be signed 17-bit, the histogram data may be collected only for positive pixels. The raw Bayer RGB data (output from 146) may be decimated (to produce signal 878) using logic 882 by skipping pixels, as discussed further below. For the green channel, the color may be selected between Gr, Gb or both Gr and Gb (both Gr and Gb counts are accumulated in the Green bins).

In order to keep the histogram bin width the same between the two histograms, Hist1 may be configured to collect pixel data every 4 pixels (every other Bayer quad). The start of the histogram window determines the first Bayer quad location where the histogram starts accumulating. Starting at this location, every other Bayer quad is skipped horizontally and vertically for Hist1. The window start location can be any pixel position for Hist1 and, therefore pixels being skipped by the histogram calculation can be selected by changing the start window location. Hist1 can be used to collect data close to the black level to assist in dynamic black level compensation (BLC) logic 472. For Hist0, bins may be 20 bits. For Hist1, bins may be 22 bits. This allows for a maximum picture size of 4096 by 3120 (12 MP). The internal memory size to accommodate such sizes may be 3×256×20 bits for Hist0 (3 color components, 256 bins), and 4×256×22 bits for Hist1 (4 color components, 256 bins).

With regard to memory format, statistics for AWB/AE windows, AF windows, 2D color histogram, and component histograms may be mapped to registers to allow early access by firmware. In one embodiment, two memory pointers may be used to write statistics to memory, one for tile statistics 863, and one for luma row sums 859, followed by all other collected statistics. All statistics are written to external memory, which may be DMA memory. The memory address registers may be double-buffered so that a new location in memory can be specified on every frame. In addition, many statistics collected in 16-bit mode may take up two 32-bit registers (which respectively may be double-buffered) to accommodate statistics of up to 64 bits (e.g., a 40-bit statistics measurement with the first 32 bits taking up the first register and the remaining 8 bits taking up the 8 most significant bits of the second register).

Fixed Pattern Noise Statistics

Referring back to FIG. 48, the output of the DPR logic 474 may also be input into the fixed pattern noise (FPN) statistics collection logic 484, which may be used to calculate fixed pattern noise statistics regarding the interim image data output by the DPR block 474. The fixed pattern noise statistics may include statistics related to fixed pattern noise that may exist on the sensors 90. Fixed pattern noise (FPN) is typically due to variations in pixel or column properties that manifest as spatial noise. For example, variations in pixel-offset values may result from variations in dark current or in offsets of an amplifier chain coupled to the sensors 90.

In general, fixed pattern noise may include noise in the sensors 90 that has a repeating or fixed pattern. For example, the fixed pattern noise may include row-wise or column-wise fixed variations that may be removed such that higher quality images can be displayed. In another example, fixed pattern noise may be a diagonal fixed variation that occurs due to a manufacturing process such as a laser annealing process that creates a different amount of light going to the pixels, which may result in a noise that has a pattern. Thus, the fixed pattern noise may be a row-wise, column-wise, or diagonal-wise pattern. Alternatively, the fixed pattern noise may be a whole frame pattern that changes pixel-to-pixel but remains similar from frame-to-frame.

Typically, during the manufacturing process, a calibration procedure may determine the fixed pattern noise, which may be used to remove the fixed pattern noise. However, the fixed pattern noise may change over time due to temperature, integration time, etc. In this manner, the fixed pattern noise statistics determined by the FPN statistics collection logic 484 may be used to adapt the fixed pattern noise removal process on the fly as the fixed pattern noise changes. In addition to the aiding the fixed pattern noise removal process, the fixed pattern noise statistics may be used to estimate a signal-to-noise (SNR) ratio or determine various noise filtering configurations such as filtering strength, filtering coefficients, and the like.

In one embodiment, the FPN statistics collection logic 484 may determine the fixed pattern noise statistics by accumulating pixel values across an axis (e.g., horizontal, vertical, diagonal) of image data, thereby capturing a 1-D projection of the image data received by the sensors 90. The 1-D projection may later be processed down the ISP pipeline to determine the fixed pattern noise of image data and to provide parameters that may be used to cancel out the fixed pattern noise from the image data. In addition to determining the fixed pattern noise of image data, the FPN statistics collection logic 484 may identify any type of pattern displayed in the image data such as, for example, bar codes. The process for determining the fixed pattern noise statistics is described below with reference to FIG. 80.

At block 902, the FPN statistics collection logic 484 may receive an orientation for fixed noise statistics accumulation. The orientation for the fixed noise statistics accumulation may include a horizontal axis (i.e., row-wise), a vertical axis (i.e., column-wise), and/or any angular axis (i.e., diagonal-wise). In one embodiment, the orientation for the fixed noise statistics accumulation may be specified using control parameters stepX and stepY. Control parameter stepX may denote a value of a horizontal pixel coordinate increment from a respective pixel location. Likewise, control parameter stepY may denote a value of a vertical pixel coordinate increment from the respective pixel location. The FPN statistics collection logic 484 may program the stepX and stepY parameters based on the orientation of the fixed noise statistics accumulation received at block 902. For example, stepX=1 and stepY=0 may indicate column accumulation, whereas stepX=0 and stepY=1 may indicate a row accumulation.

Diagonal accumulation (i.e., angular orientation) may use stepX and stepY parameters that may correspond to fractional values. In one embodiment, control parameters stepX and stepY may be defined for each color component: Gr, R, B, and Gb. An example of a diagonal accumulation is illustrated FIG. 82A, which include a diagonal accumulation 930 that has a fractional stepX of 30/40 and a fractional stepY of 14/24.

At block 904, the FPN statistics collection logic 484 may determine the color component (c) and position (pos) for each pixel in the orientation specified at block 902. The color component (c) and position (pos) may be used as an index value into a sum array that corresponds to the accumulated pixel values along the specified orientation (i.e., fixed pattern noise statistics). In one embodiment, the color component (c) and the position (pos) of a respective pixel (p(j,i)) located at (j,i) may be determined based on the orientation specified at block 902 (i.e., stepX, stepY) and a size of the repeating fixed pattern noise (i.e., fpn_size[c)) as shown below:

c=current color component, 0-3

pos=(floor(pos_init[c]+stepX[c]*i+stepY[c]*j) modulo fpn_size[c])
where pos_init may indicate an initial position in the sum array for a first pixel of the active region with respect to color component Gr, R, B, or Gb, and fpn_size may indicate a size of a repeating pattern in the sum array with respect to the color component Gr, R, B, or Gb. As such, each color component may have its own sum array indexing.

At block 906, the FPN statistics collection logic 484 may add a pixel value of each pixel having the same color component in the specified orientation into a sum array. In this manner, the FPN statistics collection logic 484 may generate a sum array for each color component. In one embodiment, the sum array may be generated with respect to a particular color component that may be specified to the FPN statistics collection logic 484. The sum array may then be computed according to:

At block 910, the FPN statistics collection logic 484 may store the fixed pattern noise statistics for each color component determined at block 906 in the memory 100. For color-dependent fixed pattern noise statistics, the FPN statistics collection logic 484 may store the fixed pattern noise statistics in the memory 100 in an order based on the color component of the first pixel value in the corresponding sum array as follows:

Referring back to block 908, if the fixed pattern noise statistics are color-independent fixed pattern noise statistics, the FPN statistics collection logic 484 may proceed to block 912. At block 912, the FPN statistics collection logic 484 may combine the sum arrays for each color component to determine the fixed pattern noise statistics for the sensors 90. In one embodiment, the FPN statistics collection logic 484 may determine the sum array indices for each color component based on the parameter pos_init[c], stepX[c], stepY[c], and fpn_size[c] for one particular color component. The maximum fpn_size when determining color-independent fixed pattern noise statistics may be 4096, which may be based on a size of a buffer memory available to perform the process 900.

After determining the fixed pattern noise statistics, at block 914, the FPN statistics collection logic 484 may store the fixed pattern noise statistics in the memory 100. In one embodiment, the FPN statistics collection logic 484 may periodically perform the process 900 to identify fixed pattern noise that may be generated as the sensors 90 ages. In another embodiment, the FPN statistics collection logic 484 may perform the process 900 over multiple frames such that the orientation of the of the fixed pattern noise accumulation changes for each frame. For example, if the orientation is specified as a column-wise orientation, the FPN statistics collection logic 484 may first perform the process 900 on one frame of the image data with variables stepX and stepY defined as 0 and 1, respectively. The FPN statistics collection logic 484 may then perform the process 900 on the next frame of the image data with variables stepX and stepY altered such that the orientation becomes an angled orientation. The FPN statistics collection logic 484 may then continue altering its orientation for each frame of the image data such that the FPN statistics collection logic 484 may collect fixed pattern noise statistics at different angles of the image data to identify fixed pattern noise that may be present along various axes of the image data.

In one embodiment, the FPN statistics collection logic 484 may divide the received image data into multiple horizontal strips of the image such that each strip is of equal height. The FPN statistics collection logic 484 may then determine the FPN statistics for each horizontal strip independent of each other. By collecting FPN statistics for each horizontal strip of the image, it may be easier to distinguish image edges from the fixed pattern noise. Additionally, a correlation or another analysis process between the FPN statistics for each horizontal strip may be used to find a true fixed pattern noise. Keeping this in mind, FIG. 81 illustrates a process 920 that may be used to determine FPN statistics for multiple horizontal strips of the input image. Although process 920 describes a method for determining FPN statistics for multiple horizontal strips of the input image, it should be noted that in other embodiments, the process 920 may be performed with respect to multiple vertical strips of the input image.

At block 922, the FPN statistics collection logic 484 may divide the input image into multiple horizontal strips of equal height. At block 924, the FPN statistics collection logic 484 may calculate fixed pattern noise statistics for each horizontal strip of the input image. In one embodiment, the FPN statistics collection logic 484 may perform the process 900 described above with respect to FIG. 80 for each horizontal strip of the input image. As such, the FPN statistics collection logic 484 may determine a sum array that includes an accumulation of pixel values that correspond to a specified orientation (block 902) in a respective horizontal strip of the input image.

In another embodiment, at block 924, the FPN statistics collection logic 484 may determine the FPN statistics for every column in each horizontal strip of the input image. When determining the FPN statistics for every column in a horizontal strip of the input image (column sum), the FPN statistics collection logic 484 may ignore the values of parameters: pos_init, stepX, stepY and fpn_size. Instead, the FPN statistics collection logic 484 may add the pixel values in each column of the horizontal strip of the input image to a sum array. Once a pixel value on a last active line of the horizontal strip has been accumulated into the sum array, at block 926, the corresponding sum array may be stored in the memory 100. An example of a column sum accumulation according to the process 920 is illustrated in FIG. 82B.

In yet another embodiment, the FPN statistics collection logic 484 may determine the FPN statistics for every row in each horizontal strip of the input image. When determining the FPN statistics for every row in a horizontal strip of the input image (row sum), the FPN statistics collection logic 484 may ignore the values of parameters: pos_init, stepY and fpn_size. Instead, the FPN statistics collection logic 484 may set parameter, stepX, such that each row of the horizontal strip of the input image may be divided into multiple segments of pixels. The FPN statistics collection logic 484 may then sum the pixel values within a segment into one bin (0<stepX<1).

Once the pixel values in a segment have been accumulated, the FPN statistics collection logic 484 may add the accumulated pixel values of each segment in a horizontal strip to a sum array. When determining the sum array for each row in a horizontal strip, the FPN statistics collection logic 484 may use a specified stepX value that corresponds to one particular color component (e.g., stepX[0]). As such, the FPN statistics collection logic 484 may ignore the values for stepX that may have been specified for other color components (e.g., stepX[1:3]). An example of a row sum accumulation according to the process 920 is illustrated in FIG. 82C.

At block 926, the FPN statistics collection logic 484 may store the corresponding sum array for each horizontal strip in the memory 100.

In one embodiment, when determining the FPN statistics for every column or row in each horizontal strip of the input image, the FPN statistics collection logic 484 may not allow for a repeating pattern due to the horizontal strips. As such, the FPN statistics collection logic 484 may store a sum array before the FPN statistics have been accumulated for a horizontal strip. Therefore, the number of active lines inside a horizontal strip may correspond to a height of the horizontal strip such that the FPN statistics collection logic 484 may not skip any lines of pixels while determining the sum array.

As will be appreciated, when storing the FPN statistics for every column in each horizontal strip of the input image in the memory 100 at block 926, the FPN statistics collection logic 484 may store the corresponding sum arrays according to the following output order:

sum[2][0], sum[3][0], sum[2][1], sum[3][1], . . . , sum[2][width/2−1], sum[3][active_region_width/2−1]
where width corresponds to a width of the input image and where active_region_width corresponds to a width of the active region of the input image.

Further, when storing the FPN statistics for every row in each horizontal strip of the input image in the memory 100 at block 926, the FPN statistics collection logic 484 may store the corresponding sum arrays according to the following output order:

Odd rows: sum[2][0], sum[3][0], sum[2][1], sum[3][1], . . . , sum[2][N−1], sum[3][N−1]
where N=floor(stepX[0]*(active_region_width−1))+1 is the number of bins in a row for each enabled (i.e., specified) color component.

In one embodiment, the FPN statistics collection logic 484 may perform the process 920 over for each horizontal strip of the input image such that the orientation of the of the fixed pattern noise accumulation changes for each horizontal strip.

After determining the FPN statistics, the FPN statistics collection logic 484 may not count a number of pixels accumulated in each sum array. Instead, additional processing components may derive the pixel count based on the accumulation orientation and the size of any repeating pattern. For instance, the additional processing components may find the orientation of the fixed pattern noise and the size of any repeating fixed pattern noise by changing step size(s) (i.e., stepX/stepY) and repeating pattern size parameters during multiple frames of the fixed pattern noise statistics collection process. In one embodiment, the repeating pattern size parameter may be used when accumulating the sum array(s) since there could be more than 4096 columns or rows exceeding the sum array size when the image is rotated. On the other hand, when the size of repeating pattern is small, the number of pixels to be accumulated in a single column or row can be too big such that it overflows a corresponding register in the memory 100. In this case, the FPN statistics collection logic 484 may set the fpn_size parameter to be multiples of the actual repeating pattern size to split the sum into multiple array entries. In this manner, when an overflow occurs, the sum may saturate.

Local Image Statistics Collection

Certain processing blocks, such as the local tone mapping (LTM) logic 3004 and highlight recovery (HR) logic 1038 discussed further below, may use localized statistics to process image data. For example, as will be discussed below, the local tone mapping (LTM) logic 3004 may apply different tone curves to different areas of the image frame depending on the local luminances in the different areas of the image frame. The manner in which luminance may vary throughout the image frame may be collected and reported as individual pixel luminance values, thumbnails, and/or local histograms. The local image statistics logic 488 of the statistics core 146a (FIG. 48) may generate these statistics. Software or other processing blocks may employ the local statistics to control the operation of the ISP pipe processing logic 80. For instance, software may generate a local tone map based on the local statistics. The local tone map may be used by the local tone mapping (LTM) logic 3004 to apply an appropriate local tone curve to pixels depending on where the pixels are spatially located.

One example of the local image statistics logic 488 appears in FIG. 83. The local image statistics logic 488 may receive the Bayer RGB image data 793 output by the inverse black level compensation (IBLC) logic 478. It should be appreciated, however, that the local image statistics logic 488 may, alternatively, use YCC image data or image data in any other suitable color space. Considering an example involving the Bayer RGB image data 793, luminance computation logic 950 may compute several values relating to the luminance of the input pixels. These may include average luminance (Ylin_avg) 952, maximal luminance (Ylin_max) 954, pixel luminance (Ylin) 956 (which may represent the average luminance 952, the maximal luminance 954, or a blend of the average luminance 952 and the maximal luminance 954), and logarithmic luminance (Ylog) 958 (which may be a logarithmic expression of the pixel luminance (Ylin) 956). In alternative embodiments, the average luminance 952 and/or the maximal luminance 954 may be replaced or supplemented by a minimal luminance. The luminance computation logic 950 is discussed in greater detail below with reference to FIGS. 84 and 85.

The various luminance values, along with the Bayer RGB pixel data 793, may enter thumbnail generation logic 960. The thumbnail generation logic 960 may output thumbnails 962 based on any of these values. The thumbnails 962 may represent the input image data downscaled according to one of many downscaling techniques, as discussed below with reference to FIG. 86. The luminance values from the luminance computation logic 950 and the Bayer RGB input pixel data 793 may also enter local histogram generation logic 964. The local histogram generation logic may generate local histograms 966 from these values. One example of the local histogram logic 964 appears in FIG. 87, and will be discussed in greater detail below.

FIGS. 84 and 85 represent two examples of the luminance computation logic 950. Since the same luminance values may be employed in the local statistics logic 488 as the local tone mapping (LTM) logic 3004, the luminance computation logic 950 may replicate the process used in the LTM logic 3004. Thus, the properties of the luminance used by the local statistics logic 488 may be the same as the luminance values determined by the LTM logic 3004. In the example of FIG. 84, the Bayer RGB image data 793 first may be downsampled in 2×2 downsample logic 970. The 2×2 downsample logic 970 may downsample the Bayer RGB image data 793 by 2 horizontally and by 2 vertically to improve precision. As discussed above with reference to FIG. 66, for each Bayer quad, the R, G, and B pixel values may be collected. Thus, the 2×2 downsample logic 970 may downsample RGB image data 793 of the format R-Gr-Gb-B as follows:

Rbayer(x,y) = raw(2*x, 2*y);

Gbayer(x,y) = 0.5*raw(2*x,2*y+1) + 0.5*raw(2*x+1,2*y);

Bbayer(x,y) = raw(2*x+1,2*y+1);

R(x,y) = Gain[0]*(Rbayer(x,y)+OffsetIn[0])+OffsetOut[0];

G(x,y) = Gain[1]*(Gbayer(x,y)+OffsetIn[1])+OffsetOut[1]; and

B(x,y) = Gain[2]*(Bbayer(x,y)+OffsetIn[2])+OffsetOut[2];

where x=0-width/2−1 and y=0-height/2−1. The Gain, OffsetIn, and OffsetOut values may be chosen such that the above process mirrors the white balance gain of other components of the ISP pipe processing logic 80. That is, the output pixel values of R, G and B may be approximately photometrically equivalent to the pixel values generated from the raw image data processing logic (RAWProc) 150. In other embodiments, other downsampling logic (e.g., 4×4 downsampling logic) may be used instead, but it should be appreciated that he 2×2 downsample logic 970 may not perform averaging, and thus discrete luminance information may be preserved. In addition, RGB-format image data may be used instead of raw-format image data, in which case the image data need not be downsampled to obtain separate color components.

Average luminance computation logic 972 and maximal luminance computation logic 974 may process the downsampled image data from the 2×2 downsample logic 970. The average luminance computation logic 972 may compute the average luminance (Ylin_avg) 952 as follows:

Ylin_avg=(CoeffAvgY[0]*R+CoeffAvgY[1]*G+CoeffAvgY[2]*B+AvgYOffset+1<<(LumShift−1))>>LumShift,
where CoeffAvgY[0], CoeffAvgY[1] and CoeffAvgY[2] represent 2s-complement numbers (e.g., 16-bit 2s-complement numbers) to weight the color components and AvgYOffset represents a signed number (e.g., a 32-bit signed number). The value LumShift represents the number of bits to shift and can be chosen such that the luminance fills the entire 16 bits of range. As a result, CoeffAvgY may be understood to include 8 fractional bits, such that the luminance values cover the entire range. Using the full range may be valuable, since the spatially varying lookup tables (LUTs) used in the local tone mapping (LTM) logic 3004—which may be programmed by software based on the statistical luminance values, thumbnails, and/or local histograms—may have fixed input ranges. The average luminance (Ylin_avg) 952 may be clipped to minimum of zero and maximum of 65535.

The maximal luminance computation logic 974 may calculate the maximal luminance (Ylin_max) 954 using the maximal value of scaled R, G, and B values as the luminance:

Ylin_max=(max CoeffMaxY[0]*R, CoeffMaxY[1]*G, CoeffMaxY[2]*B)+1<<(LumShift−1))>>LumShift,
where CoeffMaxY[0], CoeffMaxY[1] and CoeffMaxY[2] may represent unsigned 16-bit numbers to weight the color components and Ylin_max may be clipped to minimum of zero and maximum of 65535. It maybe noted that this luminance definition has the advantage of keeping the signals in gamut after the tone curve is applied in the local tone mapping (LTM) logic 3004, discussed further below. With this definition of luminance, a pixel is considered to be bright if any of the color channels are bright. Using the maximal luminance (Ylin_max) 954 may prevent pixels with saturated colors from gaining up and falling out of gamut in the local tone mapping (LTM) logic 3004. If desired, a minimal luminance may be calculated in a similar manner, using a minimum rather than maximum operator and coefficients that may be the same or different from those above.

Mixing logic 976, based on a mixing coefficient from a mixing lookup table (LUT) 978, may blend the average luminance (Ylin_avg) 952 and the maximal luminance (Ylin_max) 954 (and/or the minimal luminance) to obtain the pixel luminance (Ylin) 956. The objective of the mixing logic 976 and the mixing LUT 978 may be to blend the luminance signals smoothly. Namely, the average luminance (Ylin_avg) 952 may be weighted more heavily in dark to mid-level brightness levels, while the maximal luminance (Ylin_max) 954 may be weighted more heavily in highlight brightness levels. Some embodiments may involve mixing minimal, maximal, and average luminances. For some of these embodiments, the minimal luminance may be weighted most heavily in dark brightness levels, the average luminance (Ylin_avg) 952 may be weighted most heavily in mid-level brightness levels, and the maximal luminance (Ylin_max) 954 may be weighted more heavily in highlight brightness levels.

With these objectives in mind, the mixing LUT 978 may be programmed with any suitable values to smoothly mix, for example, the two luminance signals 952 and 954 to produce the input pixel luminance (Ylin) 956. The mixing LUT 978 may represent a table with 257 entries of 16-bits each. The entries of the mixing LUT 978 may be evenly distributed between 0 and 65535. The index to the mixing LUT 978 may be either the average luminance (Ylin_avg) 952 or the maximal luminance (Ylin_max) 954, as selected in selection logic 980 by a signal (SelMix) 982. Selecting the average luminance (Ylin_avg) 952 to index the mixing LUT 978 may produce smoother transitions of luminance, while the maximal luminance (Ylin_max) 954 may produce more aggressive transitions. Thus, whether the selection signal (SelMix) 982 is used to select the average luminance (Ylin_avg) 952 or the maximal luminance (Ylin_max) 954 may depend on the presence or absence of noise in the image, the general brightness of the image, and so forth. In another embodiment, ratios between color channels may be used to index the mixing LUT 978 instead.

The following pseudo code represents one example of calculating the input pixel luminance (Ylin) 956 as shown in FIG. 84:

if selMix == 0

wMix = interp1D (Ylin_max , wMixLUT);

else

wMix = interp1D (Ylin_avg, wMixLUT);

Ylin = Ylin_avg*wMix + Ylin_max*(1−wMix ) =

(Ylin_avg−Ylin_max)*wMix + Ylin_max;

where wMixLUT represents the mixing LUT 978 with 257 entries evenly distributed between 0 and 65535, and interp1D denotes 1D linear interpolation employed with pixel values greater than 8 bits. The entries in wMixLUT may have unsigned 16 bit values with 15 fractional bits (i.e., 1.15) and the range of wMixLUT is between zero and one (i.e., 0<=wMixLUT<=1)—any value larger than 1 may be considered to be 1. The pixel luminance (Ylin) 956 may be an unsigned 16-bit value that is clipped to min of zero and max of 65535.

The input pixel luminance (Ylin) 956 may, in some examples, undergo offset, scaling, and log computation logic 984. Scaling, offsetting, and converting the luminance value to logarithmic form may convert the pixel luminance (Ylin) 956 into a more useful form. The offset, scaling, and log computation logic 984 may carry out the following computation, if implemented:

Ylog=CoeffLog_ScaleOut*log(max(CoeffLog_ScaleIn*(Ylin+CoeffLog_OffsetIn),CoeffLog_MinVal))+CoeffLog_OffsetOut.
In the equation above, Ylog represents an unsigned 16-bit value clipped to a minimum of 0 and maximum of 65535. To ensure numerical stability near zero, a minimum input value (CoeffLog_MinVal) may be specified. Offset coefficients CoeffLog_OffsetIn and (Ylin+CoeffLog_OffsetIn) may be signed 32-bit numbers with 15 fractional bits (17.15), while CoeffLog_OffsetOut may be signed 32-bit number with no fractional bit. Scale and minimum value coefficients, CoeffLog_ScaleOut, CoeffLog_ScaleIn, and CoeffLog_MinVal, may be specified with 23 bits, including a sign bit, a 6-bit signed exponent, and a 16-bit mantissa. The mantissa may be a fractional 0.16 value where the hardware concatenates an implied 1 on the most significant bit (MSB):

CoeffLog=(−1)sign*Mant*(2^Exp),
where:

−32<=Exp<=31

1.0<=Mant<2
This may allow a range of:

2^−32<=abs(CoeffLog)<2^32

In the equation above, the value CoeffLog_MinVal may be a positive number—thus, the sign bit may be ignored. Note that the output of loge may be represented as a signed 33 bit number 16 fractional bits.

Other examples of the luminance computation logic 950 may not employ the mixing logic 976 or mixing lookup table (LUT) 978. As shown in FIG. 85, the luminance computation logic 950 may, alternatively, involve a discrete selection between either the average luminance (Ylin_avg) 952 or the maximal luminance (Ylin_max) 954. For instance, selection logic 986 may select either the average luminance (Ylin_avg) 952 or the maximal luminance (Ylin_max) 954 based on the SelMix signal 982. The selected luminance value may be output as the input pixel luminance (Ylin) 956.

The SelMix signal 982 may be kept constant on a per-frame basis, or may vary as different regions of the image frame are processed. In one example, software controlling the ISP pipe processing logic 80 may vary the SelMix signal 982 depending on whether the region of the image frame is in a dark to mid-level brightness level or in a highlight brightness level. The SelMix signal 982 may select the average luminance (Ylin_avg) 952 when the luminance computation logic 950 is computing luminance in dark to mid-level brightness levels. The SelMix signal 982 may select the maximal luminance (Ylin_max) 954 when the luminance computation logic 950 is processing image pixels from a highlight region of the image frame. Doing so may preserve highlight information in the area predominated by highlights, while avoiding high-luminance noise in dark to mid-level brightness areas. In other embodiments, the software may vary the SelMix signal 982 when ratios of color components fall above or below a threshold.

The local tone mapping (LTM) logic 3004 or the highlight recovery (HR) logic 1038 may vary operation depending on certain thumbnail images generated by the thumbnail generation logic 960. For instance, in one example, the HR logic 1038 may focus on certain colors based on the thumbnails 962 from the thumbnail generation logic 960. Additionally, software or firmware may use the thumbnails 962 to, for instance, set the exposure, focus, and/or auto-white-balance. Moreover, tone curves (e.g., global or local tone curves) may be generated by software using the thumbnails 962 from the thumbnail generation logic 960 and/or local histograms 966 from the local histogram generation logic 966.

One example of the thumbnail generation logic 960 appears in FIG. 86, receiving as input the average luminance (Ylin_avg) 952, the maximal luminance (Ylin_max) 954, the input pixel luminance (Ylin) 956, the logarithmic luminance (Ylog) 958, and red (R), green (G), and blue (B) components of the Bayer RGB image data 793. Selection logic 990 may pass one of these signals to downsampling logic 992. The downsampling logic 992 may downsample the selected image data using one of four downsampling modes to produce one or more thumbnails 962. For each thumbnail 962 that the thumbnail generation logic 960 generates, the software controlling the ISP pipe processing logic 80 may select the input source (e.g., via selection logic 990) and the downsampling mode (e.g., selection logic 994). In one example, the thumbnail generation logic 960 may generate a maximum of six thumbnails 962, thumbnails based on R, G, and B signals count as three separate thumbnails 962. As illustrated, the downsampling logic 992 may employ one or more of the following four downsampling modes: a subsampling mode (SUB) 996, a block averaging mode (BLK) 998, a minimum block value mode (MIN) 1000, and a maximum block value mode (MAX) 1002.

In general, the downsampling logic 992 may downsample each block of the image frame down to a single pixel of a thumbnail 962. The size of the blocks may be specified by a programmable horizontal downsampling factor 1004 and a programmable vertical downsampling factor 1006 (e.g., a block size of 32×32). The width and height of the generated thumbnails 962 may be the width and height of the active region 312 (FIG. 21) at full sensor resolution, divided by the horizontal and vertical downsampling factors 1004 and 1006. The top-left corner of the thumbnail image 962 will be aligned to the top-left corner of the active region 312. When the width and height of the active region 312 are not multiples of the downsampling factors 1004 and 1006, certain bottom rows and/or right columns may not be used in the thumbnail generation, as partial tiles may be discarded. In at least one embodiment, the downsampling factors 1004 and 1006 and active region 312 may always be multiples of two pixels. The width of the thumbnail 962 may not exceed 128 pixels. Also, the minimum horizontal downsampling factor 1004 may be 16 (in full sensor resolution), and the maximum number of pixels being downsampled to one pixel may not exceed 2^14 at full sensor resolution. For example, a block measuring 128×128 pixels (in full sensor resolution) may be the largest block size when the width and height are constrained to be the same value.

The four downsampling modes 996, 998, 1000, and 1002 will now be discussed. The subsample mode (SUB) 996 may subsample the pixel data spatially. Offset values from the top-left corner of each block may be programmable. The block averaging mode (BLK) 998 may perform block averaging to obtain pixel values in the thumbnail images 962. For example, if the downsampling factors 1004 and 1006 have been selected to obtain 32×32 blocks of pixels, the pixels in the 32×32 block may be averaged to determine the pixel value in the thumbnail 962. The minimum pixel value mode (MIN) 1000 may select the minimum pixel value in each block to represent each pixel of the output thumbnail 962. The maximum pixel value mode (MAX) 1002 may select the maximum pixel value in each block to represent each pixel of the output thumbnail 962.

The offset values used in the subsampling mode (SUB) 996, as well as the downsampling factors 1004 and 1006, may be defined in units of pixels in the sensor resolution—that is, before downsampling by 2×2—and should be in multiples of two. As such, the downsampling offset values in the horizontal and vertical (Y) directions may be between 0 and the horizontal downsampling value divided by the vertical downsampling value, less 1. For thumbnails 962 that are obtained via the block averaging mode (BLK) 998, the reciprocal of the number of pixels (e.g., RecipNumPix=(1<<32)/numPix) may be provided by software controlling the ISP pipe processing logic 80.

The local histogram generation logic 964, an example of which appears in FIG. 87, may generate histograms of luminance intensities for each block of pixels, all blocks having the same size. As illustrated in FIG. 87, selection logic 1010 may select from among the average luminance (Ylin_avg) 952, the maximal luminance (Ylin_max) 954, the input pixel luminance (Ylin) 956, the logarithmic luminance (Ylog) 958, and red (R), green (G), and blue (B) components of the Bayer RGB image data 793. The selected signal may be received by local (block) histogram logic 1012, which may generate local histograms 966 in, for example, 32 bins of 16 bits each. Any other suitable number of bins of suitable bit depths may also be used.

As in the downsampling logic 992, the size of the block of pixels used for the local histograms 966 may have independently programmable horizontal and vertical sizes. That is, a programmable horizontal block size signal 1014 may specify the horizontal size of a pixel block and a vertical block size signal 1016 may specify the vertical size of a block of pixels. In one embodiment, the maximum number of horizontal blocks may not exceed 64 blocks. The minimum block size in the horizontal direction may be 64 pixels (at full sensor resolution). The block size in both directions and the active region 312 coordinates may be in multiples of two. When the width and height of the active region 312 are not multiples of the block sizes, bottom rows and/or right columns may not be used for local histogram generation, as partial tiles may be discarded. The maximum number of pixels in a block may not exceed 2^ 18 at full sensor resolution, in some embodiments. For example, 512×512 pixels in full sensor resolution may be the largest block size when the width and height are constrained to be the same value.

For each block, the local (block) histogram logic 1012 may compute a local histogram of the luminance. The resulting histogram 966 may have 32 bins, and the size of each bin may be the same across all bins. The bin number may be obtained as follows:

idx=(LocalHistScale*(Luminance−LocalHistOffset))>>16,
where LocalHistScale represents scaling for computing the histogram, Luminance represents the selected signal input to the local (block) histogram logic 1012, LocalHistOffset represents a programmable offset for computing the histogram. The local histogram at block number (i,j), where (i,j) represents the horizontal (i) and vertical (j) coordinates of the block, may be incremented as follows:

if (idx>=0 && idx<32)

LocalHist(i,j,idx) += Count;

Local histograms may be written to the memory 100 in scan order as the pixel block is processed, and if the pixel block was part of the active region 312. For each block, local histogram counts are written from the lowest index—that is, the darkest pixel count—to the highest index, or brightest pixel counts. In one example, each histogram bin may be represented by a 16-bit number. When each histogram bin is represented by a 16-bit number, the value of each bin may be saturated at 65535.

Considering the direct memory access (DMA) format of local image statistics, two memory pointers may be used to write statistics to the memory 100: one for local histograms 966 and one for thumbnails 962. The memory address registers may be double-buffered so that a new location in the memory 100 can be specified on every frame. FIGS. 88, 89, and 90 illustrate one example of a suitable memory format for the local statistics. In particular, FIGS. 88 and 89 illustrate thumbnail statistics written to memory in scan order as each local region—that is, each block—is complete (if the block is part of the active region 312). The thumbnail statistics 962 may be fully or partially enabled. When thumbnail statistics are partial enabled, only four thumbnail statistics may be written to memory, as shown in FIG. 88. When thumbnail statistics are all enabled, as shown in FIG. 89, six thumbnails may be written to memory. As shown in FIG. 90, and discussed above, local histogram statistics may include 32 bins of 16 bits each.

In some embodiments, an interrupt may be sent to the host when the local image statistics have been completed by the DMA for the active region. Also, the row number in (tile/block units) may be defined such that the interrupt occurs when the DMA has completed the defined row. This may allow firmware to begin early processing.

RAW Processing Logic

Referring again briefly to FIG. 8, the raw processing logic 150 may form an initial image processing block to operate on raw Bayer image data. Using the statistics collected in the statistics logic 140a and/or 140b (e.g., as interpreted by software running on the processor(s) 16 that may control the ISP pipe processing logic 80), the raw processing logic 150 may perform sensor linearization, black level compensation, fixed pattern noise reduction, temporal filtering, defective pixel detection and correction, spatial noise filtering, lens shading correction, white balance gain operations, highlight recovery, chromatic aberration correction and/or raw scaling, as will be discussed further below. As shown in the present embodiment, the input signal to the raw processing logic 150 may be the raw pixel output from the sensors 90 or raw pixel data from the memory 100, depending on the present configuration of the selection logic 142c.

Referring now to FIG. 91, a block diagram showing a more detailed view of an embodiment of the raw processing logic 150 is illustrated, in accordance with an embodiment of the present technique. As shown, the raw processing logic 150 includes sensor linearization (SLIN) logic 1022, black level compensation (BLC) logic 1024, fixed pattern noise reduction (FPNR) logic 1026, temporal filter logic (TF) 1028, defective pixel correction (DPC) logic 1030, which may share hardware logical blocks with noise statistics logic 1031 to share resources, spatial noise filter (SNF) logic 1032, lens shading correction (LSC) logic 1034, white balance gain (WBG) logic 1036, highlight recovery (HR) logic 1038, and raw scaler (RSCL) logic 1040. In one example, the raw processing logic 150 may pass raw image data through these logic blocks in the order above. In some embodiments, the SLIN logic 1022, the BLC logic 1024, the FPNR logic 1026, and the TF logic 1028 may benefit from occurring before the DPC logic 1030, since these blocks perform corrections at a pixel correction level. In another example, the raw scaler (RSCL) logic 1040 may occur between the defective pixel correction (DPC) logic 1030 and the spatial noise filter. In other examples, the temporal filter (TF) logic 1028 may take place between the spatial noise filter (SNF) logic 1032. For instance, the order may be the SLIN logic 1022, the BLC logic 1024, the FPNR logic 1026, the DPC logic 1030, the RSCL logic 1040, the SNF logic 1032, the TF logic 1028, the LSC logic 1034, the WBG logic 1036, and the HR logic 1038. These logic blocks are described in greater detail below.

Before continuing, it should be appreciated that the noise statistics logic is implemented in conjunction with the DPC logic 1030 because doing so permits reusing some of the same logic. In other embodiments, however, the noise statistics logic may be located in any number of other spaces in the pipeline. For instance, the noise statistics logic may occur after the FPNR logic 1026, after the TF logic 1028, and/or after the SNF logic 1032, and so forth. The noise statistics logic may also be located outside of the raw processing logic 150. For instance, the noise statistics logic may be located after the demosaicing (DEM) logic of the RGB processing logic 160 or the luminance (Y) sharpening logic or chromanoise reduction logic of the YCC processing logic 170. Indeed, the noise reduction logic may allow the determination of the noise standard deviation after these noise reduction blocks have operated on the pixel data. Thus, by monitoring the noise standard deviation before and after processing, the effectiveness of the noise reduction blocks may be gauged. When only one noise statistics logic block is used (e.g., the noise statistics logic appears only in conjunction with the DPC logic 1030 or only appears before TF logic 1028), the noise standard deviation at later blocks may be estimated from the noise standard deviation determined in the one noise statistics logic block. Moreover, when only one noise statistics logic block is used, it may be valuable to locate the noise statistics logic block before the SNF logic 1032 spreads noise around, which could alter the noise standard deviation of the image by spatially spreading noise.

Of note, the raw processing logic 150 may preserve more image information than many conventional techniques. Indeed, the raw processing logic 150 may operate on signed image data, which allows for a zero offset that can preserve negative noise. By processing the raw image data in a signed format, rather than merely clipping the raw image data to an unsigned format, image information that would otherwise be lost may be preserved. To provide a brief example, noise on the image sensor(s) 90 may occur in a positive or negative direction. In other words, some pixels that should represent a particular light intensity may have values of a particular (correct) value, others may have noise resulting in values greater than the particular value, and still others may have noise resulting in values less than the particular value. When an area of the image sensor(s) 90 captures little or no light, sensor noise may increase or decrease individual pixel values such that the average pixel value is about zero. If only noise occurring in a negative direction is discarded, however, the average black color could rise above zero and would produce grayish-tinged black areas.

In effect, the zero bias effectively centers the noise distribution from the sensor(s) 90 around zero, so that filters and functional operations can use pixels with information on both sides of the distribution. Thus, the average noise will be approximately zero. The distribution of noise may thus effectively cancel out to provide colors that more accurately reflect the scene that was captured. For example, noise from the sensor(s) 90 may be Gaussian with a mean of zero. Without applying the zero bias as taught in the present disclosure, the average black color will be at zero bias after the noise filter.

Since the ISP pipe processing logic 80 may use signed image data, rather than merely clipping the negative noise away, the ISP pipe processing logic 80 may more accurately render dark black areas in images. In alternative embodiments, only some of the raw processing logic 150 may employ signed image data. In general, however, the raw processing logic 150 may use signed image data at least through the noise statistics block and the SNF logic 1032, to allow for a more precise determination of the noise standard deviation (noise statistics) and to prevent spreading unwanted noise (SNF logic 1032).

The process of scaling and offsetting the input image data may take place as described above with reference to FIGS. 40-43 and FIG. 229. Scaling and offset logic 82 (not shown in FIG. 91) may be implemented as a function of the input and output direct memory access (DMA) logic that inputs and outputs image data to and from the memory 100 and raw processing logic 150.

Also of note is that the raw processing logic 150 does not perform demosaicing of raw image data into the RGB format. As such, the output of the raw processing logic 150 remains in the raw image format. Since the output of the raw processing logic 150 is in the raw format, the output of the raw processing logic 150 may be stored in the memory 100 and reprocessed through the raw processing logic 150 in multiple passes. For example, software running on the processor(s) 16 may control the ISP pipe processing logic 80 to make multiple passes on the same data, keeping the same or varying the control parameters of the raw processing logic 150 each time. Under certain conditions (e.g., low-light conditions or other high-noise conditions), multiple passes through the raw processing logic 150 may reduce noise in otherwise overly noisy images.

Moreover, in some embodiments, software may provide raw image data obtained from another imaging device than those of the electronic device 10 (e.g., a raw file obtained by a third-party camera system). To provide one example, the raw image data may be obtained by decompressing VLC compressed RAW images. The obtained raw image data may be processed through the raw processing logic 150 as if the image data had been obtained by the sensors 90. Software controlling the ISP pipe processing logic 80 may program the various functional blocks based on information related to the third-party camera, sensor, lens, etc. For instance, the lens shading correction (LSC) logic may adjust the radial gains based on the lens used in the third-party camera.

Sensor Linearization (SLIN)

As mentioned above, raw image data received from some sensors 90, particularly high dynamic range (HDR) sensors 90, may be nonlinear. The image processing of the raw processing logic 150, however, may operate on linear image data. The sensor linearization logic 1022 thus may convert nonlinear image data from the sensors 90 into linear image data that can be operated on by the raw processing logic 150. To provide one example, raw image data in a companding format first may be mapped from its encoded nonlinear state to a linear space for additional image processing. The sensor linearization logic 1022 may perform such a conversion.

The sensor linearization (SLIN) logic 1022 of the raw processing logic (RAWProc) 150 may operate in substantially the same way as the sensor linearization (SLIN) logic 470 of the statistics logic 140a and 140b. As such, sensor linearization (SLIN) logic 1022 may operate in the manner discussed above with reference to FIGS. 49-51.

Black Level Compensation (BLC)

The output of the sensor linearization (SLIN) logic 1022 may be passed to the black level compensation (BLC) logic 1024. The BLC logic 1024 may operate in substantially the same way as the BLC logic 472. Thus, the BLC logic 1024 may provide for digital gain, offset, and clipping independently for each color component “c” (e.g., R, B, Gr, and Gb for Bayer) on the pixels used for statistics collection. For instance, as expressed by the following operation, the input value for the current pixel is first offset by a signed value, and then multiplied by a gain:
Y=(X+O[c])×G[c],
where X represents the input pixel value for a given color component c (e.g., R, B, Gr, or Gb), O[c] represents a signed 16-bit offset for the current color component c, G[c] represents a gain value for the color component c, and Y represents the output pixel value. In one embodiment, the gain G[c] may be a 16-bit unsigned number with 2 integer bits and 14 fraction bits (e.g., 2.14 in floating point representation), and the gain G[c] may be applied with rounding. By way of example, the gain G[c] may have a range of between 0 to 4 (e.g., 4 times the input pixel value).

Next, as shown by the below, the computed value Y, which is signed, may then be then clipped to a minimum and maximum range:
Y=(Y<min[c])?min[c]:(Y>max[c])?max[c]:Y).

The variables min[c] and max[c] may represent signed 16-bit clipping values for the minimum and maximum output values, respectively. In one embodiment, the BLC logic 1024 may also be configured to maintain a count of the number of pixels that were clipped above and below maximum and minimum, respectively, per color component.

Fixed Pattern Noise Reduction (FPNR)

Subsequently, the output of the BLC logic 1024 is forwarded to a fixed pattern noise reduction (FPNR) block 1026. The FPNR block 1026 may use the fixed pattern noise statistics generated by the FPN statistics logic 484 to remove the fixed pattern noise from raw image data received from some sensors 90. For instance, the FPNR block 1026 may extract the fixed pattern noise in the raw image by identifying the pattern with the highest energy in the FPN statistics determined by the FPN statistics logic 484. As discussed above with reference to FIGS. 80-82 (FPN statistics logic 484), fixed pattern noise (FPN) is generally due to variations in pixel or column properties that manifest themselves as spatial noise. For example, variations in pixel-offset values may result from variations in dark current or in offsets of an amplifier chain coupled to the sensors 90.

In general, fixed pattern noise may include noise in the sensors 90 that has a repeating or fixed pattern. For example, the fixed pattern noise may include row-wise or column-wise fixed variations that may be removed such that higher quality images can be displayed. In another example, fixed pattern noise may be a diagonal fixed variation that occurs due to a manufacturing process such as a laser annealing process that creates a different amount of light going to the pixels, which may result in a noise that has a pattern. Thus, the fixed pattern noise may be a row-wise, column-wise, or diagonal-wise pattern. Alternatively, the fixed pattern noise may be a whole frame pattern that changes pixel-to-pixel but remains similar from frame-to-frame.

Typically, during the manufacturing process, a calibration procedure may determine the fixed pattern noise, which may be used to remove the fixed pattern noise. However, the fixed pattern noise may change over time due to temperature, integration time, etc. In this manner, the fixed pattern noise statistics determined by the FPN statistics logic 484, as described above, may be used by the FPNR block 1026 to adapt the fixed pattern noise removal process on the fly as the fixed pattern noise changes.

In one embodiment, the fixed pattern noise may correspond to variations in gain and offsets of pixel intensity values as indicated in the fixed pattern noise statistics determined by the FPN statistics logic 484. The FPNR block 1026 may remove the offset fixed pattern noise by subtracting a dark frame from the input image. The dark frame may be an image captured by the sensors 90 in the dark (e.g., an image of noise in the sensor 90a). In this manner, the dark frame may be generated by capturing image data with a closed shutter or during camera calibration. In general, the dark frame may change based on an integration time, a temperature, and/or other external factors. In one embodiment, the offset may be generated by a linear combination of two or more dark frames. For instance, a dark frame acquired with an integration time of 10 ms may be bilinearly interpolated with a dark from with an integration time of 20 ms.

As mentioned above, in addition to offsets of pixel values, the fixed pattern noise may include gain fixed pattern noise. Gain fixed pattern noise may be a ratio between an optical power on a pixel versus an electrical signal output on the pixel. For instance, the gain fixed pattern noise may be pixel-to-pixel response non-uniformity (PRNU). The FPNR block 1026 may remove the gain fixed pattern noise by multiplying different gain values to pixels, thereby compensating for the PRNU effects on the pixels.

In one embodiment, the offset and gain components for each pixel in an input image may be stored in an offset look-up table (LUT) and a gain LUT, respectively. Each LUT may be calibrated based on various types of fixed pattern noise, which may be identified using the fixed pattern noise statistics. In addition to or in lieu of being calibrated based on the various types of fixed pattern noise, each LUT may be calibrated based on a temperature value acquired by the temperature sensor or an integration time for the sensors(s) 90. For instance, each LUT may be calibrated based on a per-unit temperature value change on the temperature sensor. By storing the offset and gain components for each pixel in LUTs, the offset and gain components may be represented using fewer bits per pixel and may be used to specify a non-linear mapping. The offset and gain components for each pixel may be stored in a fixed pattern noise frame. In one embodiment, the fixed pattern noise frame 1060, as illustrated in FIG. 92, may include packed bits that encode two offsets and a gain. A first offset 1062 in the fixed pattern noise frame 1060 may be located in the least significant bits of the fixed pattern noise frame 1060 followed by a second offset 1064, and then followed by a gain 1066. The fixed pattern noise frame may be represented in 8, 10, 12, 14, or 16-bit. As such, the fixed pattern noise frame width (fpn_frame_bitdepth) may be determined by the RAW format (RAW8, 10, 12, 14 or 16) of the input image.

After determining the width of the fixed pattern noise frame, the width of the offsets and gain in the fixed pattern noise frame 1060 may be programmed. In this manner, the number of bits used for each offset (1062 and 1064) in the fixed pattern noise frame 1060 may be specified (frame_off_width[0] and frame_off_width[1]) prior to when the offsets of the fixed pattern noise frame of a pixel are set. For example, with a RAW16 input image, bit widths for the first offset 1062, the second offset 1064, and the gain 1066 may be set to 6, 6, and 4, respectively. Alternatively, if the gain 1066 is not required, the first offset 1062 and the second offset 1064 may be set to 8 bit each. In one embodiment, the fixed pattern noise frame 1060 may include only one offset as opposed to two offsets.

The bits of the fixed pattern noise frame not being used for an offset may consequently be used for the gain portion 1066 of the fixed pattern noise frame 1060. Since the gain portion 1066 of the fixed pattern noise frame 1060 may be fractional value, the number of bits to be used as the fractional value of the gain may also be specified (frame_gain_fraction) prior to the gain is set in the fixed pattern noise frame 1060 for a pixel.

After determining the fixed pattern noise frame 1060 (offset and gain values) to compensate for the fixed pattern noise of a pixel, the FPNR block 1026 may subtract an offset and apply a gain (up or down) to the pixel, thereby compensating for the fixed pattern noise in the input image. Additional details with regard to compensating for the fixed pattern noise in the input image are discussed below with reference to FIG. 93.

At block 1072, the FPNR block 1026 may determine an offset value and a gain value for each pixel based on the fixed pattern noise frame for each pixel as shown below:

frame_offset[0] = fpn (j,i) & frame_off_mask[0]

frame_offset[1] = (fpn (j,i) & frame_off_mask[1])>>

frame_off_width[0]

frame_gain = ((fpn (j,i) & frame_gain_mask))>>(frame_off_width[0] +

frame_off_width[1])

where frame_offset[0] corresponds to the first offset 1062 and frame_off_mask[0] corresponds to a mask for the first offset 1062, frame_offset[1] corresponds to the second offset 1064, frame_off_mask[1] corresponds to a mask for the second offset 1064, frame_gain_mask correspond to a mask for the gain 1066, and fpn (j,i) corresponds to a fixed pattern noise frame for a pixel in the input image located at (j, i).

In another embodiment, if an offset LUT is enabled and/or a gain LUT is enabled, the FPNR block 1026 may apply a mask to the fixed pattern noise frame 1060 for a respective pixel based on the mask and the fixed pattern noise frame as follows:

if (offset_LUT_en)

frame_offset[0] = offset_LUT [fpn (j,i) & frame_off_mask[0]]

frame_offset[1] = offset_LUT [fpn (j,i) & frame_off_mask[1])>>

frame_off_width[0]]

if (gain_LUT_en)

frame_gain = gain_LUT [fpn (j,i) & frame_gain_mask))>>

(frame_off_width[0] + frame_off_width[1]]

where offset_LUT represents an interpolation of the offset from a look-up table for the offset, frame_off_width [0] corresponds to a number of bits used in the fixed pattern noise frame to specify the first offset 1062, frame_off_width [1] corresponds to a number of bits used in the fixed pattern noise frame to specify the second offset 1064, and gain_LUT represents an interpolation of the gain from a look-up table for the gain 1066.

The total frame_offset may then be determined as follows:

frame_off=frame_off_weight[0]*frame_offset[0]+frame_off_weight[1]*frame_offset[1]
where frame_off_weight [0] corresponds to a weighting factor for the first offset 1062, and frame_off_weight [1] corresponds to a weighting factor for the second offset 1064.

As shown in the equations above, after appropriate masking of the fixed pattern noise frame, the FPNR block 1026 may use lookup-table operations to determine an offset and gain for the respective pixel. In one embodiment, an optional linear interpolation between look-up table values may be performed if the offset width of the fixed pattern noise frame is larger than the number of entries in the LUT. As such, the interpolation may occur if the width of the offset or gain is larger than the corresponding LUT size. The offset_LUT may include signed 17-bit output levels such that the spacing on the input is a maximum value between 1 and 2^(offset width−7). As such, if the offset is 7 bit or less, the spacing is 1 and the FPNR block 1026 may not perform any interpolation. The gain LUT may include unsigned 16-bit output levels such that the spacing on the input is a maximum value between 1 and 2^(gain width−6). Therefore, if the gain is 6 bit or less, the spacing is 1 and the FPNR block 1026 may not perform any interpolation.

At block 1074, the FPNR block 1026 may determine if a row fixed pattern noise correction feature has been enabled (i.e., row_fpn_en=1). The row fixed pattern noise correction feature may be enabled if the FPN statistics logic 484 collects fixed pattern noise that indicates a row-wise fixed pattern noise in the input image. In one embodiment, the row fixed pattern noise correction feature may be enabled with respect to each color component (i.e., row_fpn_en[c]=1). If the row fixed pattern noise correction feature is enabled, then the FPNR block 1026 may proceed to block 1076.

At block 1076, the FPNR block 1026 may determine the fixed pattern noise correction factors for each row of the input image similar as to how the fixed pattern noise correction factors for each pixel has been determined as described above. In one embodiment, the FPNR block 1026 may determine an offset value and a gain value for each row based on the fixed pattern noise frame for each row as shown below:

row_offset[0] = row_fpn[floor(row_pos)] & row_off_mask[0]

row_offset[1] = (row_fpn[floor(row_pos)] & row_off_mask[1])>>

row_off_width[0]

row_gain = ((row_fpn[floor(row_pos)] & row_gain_mask))>>

(row_off_width[0] + row_off_width[1])

where

row_pos = ((row_pos_init[c] + row_stepX[c]*i + row_stepY[c]*j)

modulo row_fpn_size[c]) + row_pos_offset[c]

and where row_offset[0] corresponds to the first offset 1062 and row_off_mask[0] corresponds to a mask for the first offset 1062, row_offset[1] corresponds to the second offset 1064, row_off_mask[1] corresponds to a mask for the second offset 1064, row_gain_mask correspond to a mask for the gain 1066, row_fpn[floor(row_pos)] corresponds to the fixed pattern noise frame for a respective row located at floor(row_pos), row_pos corresponds to a current row position of the respective pixel in the active region per color component, row_off_width[0] corresponds to a number of bits the row fixed pattern noise frame that are used to specify the first offset 1062, row_off_width[1] corresponds to a number of bits the row fixed pattern noise frame that are used to specify the second offset 1064, and row_gain corresponds to the gain 1066 in the row fixed pattern noise frame, row_pos_init[c] corresponds to an initial position in a row fixed pattern noise array, which may be determined based on fixed pattern noise statistics or calibration data obtained from a supplier of the sensors 90, for a first pixel of an active region per color component in the input image, row_stepX[c] corresponds to a horizontal step size in the row fixed pattern noise array per color component, row_stepY[c] corresponds to a vertical step size in the row fixed pattern noise array per color component, row_fpn_size[c] corresponds to the size of a repeating pattern in the row fixed pattern noise array per color component, and row_pos_offset[c] corresponds to an offset in the row fixed pattern noise array for the position of the first element per color component.

In another embodiment, if an offset LUT is enabled and/or a gain LUT is enabled, the FPNR block 1026 may apply a mask to the fixed pattern noise frame 1060 for a respective pixel based on the mask and the fixed pattern noise frame as follows:

if (offset_LUT_en)

row_offset[0] = offset_LUT [row_fpn[floor(row_pos)] &

row_off_mask[0]]

row_offset[1] = offset_LUT [(row_fpn[floor(row_pos)] &

row_off_mask[1])>> row_off_width[0]]

if (gain_LUT_en)

row_gain = gain_LUT [((row_fpn[floor(row_pos)] &

row_gain_mask))>>(row_off_width[0] + row_off_width[1])]

where row_off_width [0] corresponds to a number of bits used in the fixed pattern noise frame to specify the first offset 1062, and row_off_width [1] corresponds to a number of bits used in the fixed pattern noise frame to specify the second offset 1064.

The total row offset may then be determined as follows:

row_off=row_off_weight[0]*row_offset[0]+row_off_weight[1]*row_offset[1]
where row_off_weight [0] corresponds to a weighting factor for the first offset 1062, and row_off_weight [1] corresponds to a weighting factor for the second offset 1064.

After setting the row offset value and the row gain value as shown above, the FPNR block 1026 may proceed to block 1078.

Referring back to block 1074, if the row fixed pattern noise correction feature is not enabled for one or more color components (i.e., row_fpn_en=0), then the FPNR block 1026 may set a row offset value in the row fixed pattern noise frame to 0 and set the gain value in the row fixed pattern noise frame to 1 as shown below:

row_off=0

row_gain=(1<<row_gain_fraction)
where row_gain_fraction corresponds to a number of bits to be used for the row_gain portion of the row fixed pattern noise frame. After setting the row offset value and the row gain value, the FPNR block 1026 may proceed to block 1078.

At block 1078, the FPNR block 1026 may determine the fixed pattern noise correction factors for each column of the input image similar as to how the fixed pattern noise correction factors for each pixel has been determined as described above for each pixel and each row of the input image. In one embodiment, the FPNR block 1026 may determine an offset value and a gain value for each column based on the fixed pattern noise frame for each column as shown below:

col_offset[0] = col_fpn[floor(col_pos)] & col_off_mask[0]

col_offset[1] = (col_fpn[floor(col_pos)] & col_off_mask[1])>>

col_off_width[0]

col_gain = ((col_fpn[floor(col_pos)] & col_gain_mask))>>

(col_off_width[0] + col_off_width[1])

where

col_pos = ((col_pos_init[c] + col_stepX[c]*i + col_stepY[c]*j) modulo

col_fpn_size[c]) + col_pos_offset[c]

and where col_offset[0] corresponds to the first offset 1062 and col_off_mask[0] corresponds to a mask for the first offset 1062, col_offset[1] corresponds to the second offset 1064, col_off_mask[1] corresponds to a mask for the second offset 1064, col_gain_mask correspond to a mask for the gain 1066, col_fpn[floor(col_pos)] corresponds to the fixed pattern noise frame for a respective column located at floor(col_pos), col_pos corresponds to a current column position of the respective pixel in the active region per color component, col_off_width[0] corresponds to a number of bits the column fixed pattern noise frame that are used to specify the first offset 1062, col_off_width[1] corresponds to a number of bits the column fixed pattern noise frame that are used to specify the second offset 1064, and col_gain corresponds to the gain 1066 in the column fixed pattern noise frame, col_pos_init[c] corresponds to an initial position in a column fixed pattern noise array, which may be determined based on fixed pattern noise statistics or calibration data obtained from a supplier of the sensors 90, for a first pixel of an active region per color component in the input image, col_stepX[c] corresponds to a horizontal step size in the row fixed pattern noise array per color component, col_stepY[c] corresponds to a vertical step size in the column fixed pattern noise array per color component, col_fpn_size[c] corresponds to the size of a repeating pattern in the column fixed pattern noise array per color component, and col_pos_offset[c] corresponds to an offset in the column fixed pattern noise array for the position of the first element per color component.

In another embodiment, if an offset LUT is enabled and/or a gain LUT is enabled, the FPNR block 1026 may apply a mask to the fixed pattern noise frame 1060 for a respective pixel based on the mask and the fixed pattern noise frame as follows:

if (offset_LUT_en)

col_offset[0] = offset_LUT [col_fpn[floor(col_pos)] &

col_off_mas[0]]

col_offset[1] = offset_LUT [(col_fpn[floor(col_pos)] &

col_off_mask[1])>> col_off_width[0]]

if (gain_LUT_en)

col_gain = gain_LUT [((col_fpn[floor(col_pos)] &

col_gain_mask))>>( col_off_width[0] + col_off_width[1])]

where col_off_width [0] corresponds to a number of bits used in the fixed pattern noise frame to specify the first offset 1062, and col_off_width [1] corresponds to a number of bits used in the fixed pattern noise frame to specify the second offset 1064.

The total column offset may then be determined as follows:

col_off=col_off_weight[0]*col_offset[0]+col_off_weight[1]*col_offset[1]
where col_off_weight [0] corresponds to a weighting factor for the first offset 1062, and col_off_weight [1] corresponds to a weighting factor for the second offset 1064.

The column fixed pattern noise frame may be represented in the same manner as the pixel fixed pattern noise frame of FIG. 92. The column offset (col_off) may be used to represent a pattern of a known frequency using a horizontal step size (col_stepX[c]) and a vertical step size (col_stepY[c]) into a column offset array. In one embodiment, a position in a column fixed pattern noise table (col_pos_init) may be represented as a 14.16 fractional number. In one embodiment, the column fixed pattern noise table may be generated based on the fixed pattern noise statistics. Similarly, the horizontal step (col_stepX[c]) and the vertical step (col_stepY[c]) may be represented as a 14.16 fractional number. As such, the FPNR block 1026 may maintain the column fixed pattern noise position in the column fixed pattern noise table (col_pos) and increment the column fixed pattern noise position by a corresponding horizontal step (col_stepX[c]). The horizontal step may be truncated to a closed integer value to provide a precise step value. At the end of every row in the input image, the FPNR block 1026 may increment the column fixed pattern noise position (col_pos) by the vertical step (col_stepY[c]). The column fixed pattern noise position (col_pos) may then wraps around when it reaches the maximum index of the column fixed pattern noise table. After setting the column offset value and the column gain value as described above, the FPNR block 1026 may proceed to block 1082.

Referring back to block 1078, if the column fixed pattern noise correction feature is not enabled for one or more color components (i.e., col_fpn_en[c]=1), then the FPNR block 1026 may set a column offset value in the column fixed pattern noise frame to 0 and set the gain value in the column fixed pattern noise frame to 1 as shown below:

col_off=0

col_gain=(1<<col_gain_fraction)
where col_gain_fraction corresponds to a number of bits to be used for the column gain portion of the row fixed pattern noise frame. After setting the column offset value and the column gain value, the FPNR block 1026 may proceed to block 1082.

At block 1082, the FPNR block 1026 may apply the fixed pattern noise offsets and gains (i.e., fixed pattern noise correction factors per pixel, row, and/or column) determined at blocks 1072, 1076, and 1080 to the input image. An example of the effects of applying the fixed pattern noise offsets and gains as described in process 1070 above is illustrated in FIG. 224 and FIG. 225. In one embodiment, the image illustrated in FIG. 224 may correspond to image data received by the FPNR block 1026, and the image illustrated in FIG. 225 may correspond to image data processed by the FPNR block 1026 to remove the column offset fixed pattern noise from the image data.

In addition to the fixed pattern noise correction factors per pixel, row, and/or column, the FPNR block 1026 may also apply global input and output offsets as described below with reference to FIG. 94. At block 1092, the FPNR block 1026 may receive global input and/or output offset values for the input image. At block 1094, the FPNR block 1026 may determine whether the global offset values are to be added before applying the gain values of the fixed pattern noise correction factors that correspond to the pixel, row, and/or column of the input image.

If the global offset values are to be added before applying the gain values of the fixed pattern noise correction factors, the FPNR block 1026 may proceed to block 1096. At block 1096, the FPNR block 1026 may apply the fixed pattern noise correction factors and the global offsets as follows:

where tmp corresponds to a temporary value, x(j,i) corresponds to a pixel value for the respective pixel, offset_in[c] corresponds to a global input offset per color component, and offset_out[c] corresponds to a global output offset per color component.

Referring back to block 1094, if the global offset values are not to be added before applying the gain values of the fixed pattern noise correction factors, the FPNR block 1026 may proceed to block 1098. At block 1098, the FPNR block 1026 may apply the fixed pattern noise correction factors and the global offsets as follows:

In one embodiment, the FPNR block 1026 may bypass the fixed pattern noise processes (1070 and 1090) described in FIG. 93 and FIG. 94 if the value of the respective pixel is not between a low threshold value and a high threshold value. As such, the FPNR block 1026 may evaluate whether the value of each pixel (x(j,i)) is less than a low threshold value (BypassThdLow) or greater than a high threshold value (BypasshdHigh) as shown below.

(x(j,i)<BypassThdLow∥x(j,i)>BypassThdHigh)

If the value of the respective pixel (x(j,i)) is less than a low threshold value (BypassThdLow) or greater than a high threshold value (BypasshdHigh), the FPNR block 1026 may bypass the fixed pattern noise processes (1070 and 1090) for the respective pixel.

In one embodiment, the FPNR block 1026 may compensate for the fixed pattern noise in the input image based on a temperature value acquired from the temperature sensor 22 or an integration time for the sensor(s) 90. Here, look-up tables for various temperature values that acquired by the temperature sensor 22 and/or integration times that correspond to the sensor(s) 90 may include correction factors for each pixel in the input image. Like the look-up tables described above, the look-up tables for various temperature values and/or integration times may include offset values and gain values, which may be used to correct each pixel in the input image for fixed pattern noise. In one embodiment, the FPNR block 1026 may determine the current temperature value of the temperature sensor 22 and/or the integration time of the sensor(s) 90 and interpolate the temperature value and/or the integration time based on the corresponding look-up tables, which may be stored in the memory 18. In one embodiment, the look-up tables for various temperature values and/or integration times may be combined with the look-up tables described above, which may be determined based on a type of fixed pattern noise, to determine more accurate correction factors for each pixel in the input image.

Temporal Filter (TF)

The output of the FPNR block 1026 may be input into the temporal filter block 1028, as depicted in FIG. 91. In addition to the output of the FPNR block 1026, the temporal filter block 1028 may receive raw image data that may be stored in or written to the memory 110 or may be provided directly from the sensors 94 via sensors interfaces 94 (not shown). The temporal filter block 1028 may perform various image processing operations on the received image data on a pixel-by-pixel basis. In one embodiment, the temporal filter block 1028 may be used to reduce noise by averaging frames of image data in the temporal direction. As such, the temporal filter block 1028 may blend prior frames of the image data into each pixel of the image data. In addition to the image data, the temporal filter block 1028 may also receive and output various signals (e.g., Rin, Hin, Hout, and Yout—which may represent motion history and luma data used during temporal filtering) when performing the pixel processing operations, as will be discussed further below. The output of the pixel temporal filter block 1028 may then be forwarded to the defective pixel correction (DPC) block 1030 or may be sent to the memory 110.

In one embodiment, the temporal filter block 1028 may be pixel-adaptive based upon motion and brightness characteristics. For instance, when pixel motion is high, the filtering strength may be reduced in order to avoid the appearance of “trailing” or “ghosting artifacts” in the resulting processed image, whereas the filtering strength may be increased when little or no motion is detected. Additionally, the filtering strength may also be adjusted based upon brightness data (e.g., “luma”). For instance, as image brightness increases, filtering artifacts may become more noticeable to the human eye. Thus, the filtering strength may be further reduced when a pixel has a high level of brightness.

In applying temporal filtering, the temporal filter block 1028 may receive reference pixel data (Rin) and motion history input data (Hin), which may be from a previous filtered or original frame. Using these parameters, the temporal filter block 1028 may provide motion history output data (Hout) and filtered pixel output (Yout). The filtered pixel output Yout may then be forwarded to the DPC block 1030, as mentioned above.

In one embodiment, the temporal filter block 1028 may apply filter coefficients to pixel data from the received image data to generate the filtered pixel output (Yout). The filter coefficients may be adjusted adaptively on a per pixel basis based at least partially upon motion data between an input pixel x(t) and a reference pixel r(t−1). For instance, the input pixel x(t), with the variable “t” denoting a temporal value, may be compared to the reference pixel r(t−1) in a previously filtered frame or a previous original frame to determine the motion data associated with the input pixel. In one embodiment, the motion data may be used to generate a motion table index value (m) that corresponds to a motion table (M). The motion table (M) may contain the filter coefficients that may be used to generate the filtered pixel output (Yout). In one embodiment, the motion table (M) may be indexed according to motion data (e.g., motion table index value) and a brightness value of a pixel. As such, the temporal filter block 1028 may retrieve filter coefficients from the motion table (M) and apply the filter coefficients to the pixel data to generate filtered pixel output (Yout). The process for generating filtered pixel output (Yout) employed by the temporal filter block 1028 is described in greater detail below with reference to FIGS. 95-98.

In one embodiment, the motion table (M) may generally be oriented such that pixels exhibiting high motion values may have coefficient values equal to 0. As such, the motion table (M) may set a maximum motion value as the first motion value that has a 0 coefficient value. The motion table (M) may then divide the number of entries in the table by the maximum motion value to determine the filter coefficient for each entry in the motion table (M).

Referring to FIG. 95, a flow diagram of a method 1110 for temporally filtering the image data received by the temporal filter block 1028 is illustrated. Although the method 1110 indicates a particular order of operation, it should be understood that the method 1110 is not limited to the illustrated order. Instead, the method 1110 may be performed in any suitable order. In one embodiment, the method 1110 may be performed by the temporal filter block 1028 of FIG. 91.

At block 1112, the temporal filter 1028 may receive image data. At block 1114, the temporal filter block 1028 may determine a motion delta value for each respective pixel in the image data. The motion delta value may represent the amount of motion occurring in a respective pixel between frames. The motion delta value may be determined by calculating the difference between a pixel value for the respective pixel in a respective frame and a pixel value for the respective pixel in its previous frame. By comparing these two time dependent pixel values, the temporal filter block 1028 may represent the amount of motion occurring in the respective pixel in the motion delta value.

In one embodiment, the motion delta d(j,i,t) may be computed by determining the maximum of three absolute deltas between original and reference pixels for three horizontally collocated pixels of the same color, as demonstrated in the formula below:
d(j,i,t)=max3[abs(x(j,i−2,t)−r(j,i−2,t)),
(abs(x(j,i,t)−r(j,i,t)),
(abs(x(j,i+2,t)−r(j,i+2,t))]
where x(j, i, t) corresponds to the pixel value of a pixel, j corresponds to the vertical position of the pixel, i corresponds to the horizontal position of the pixel, t corresponds to time.

By determining the maximum of the three absolute deltas between original and reference pixels for three horizontally collocated pixels of the same color, the temporal filter block 1028 may more accurately represent the motion in the respective pixel with respect to the three horizontally collocated pixels of the same color.

To calculate the motion delta d(j,i,t) for the respective pixel, the temporal filter block 1028 may first receive data regarding a spatial location of the respective pixel. The temporal filter block 1028 may then identify the reference pixel from a previous frame (collocated reference pixel) based on the spatial location of the respective pixel. For instance, referring briefly to FIG. 96, the spatial locations of three reference pixels 1130, 1132, and 1134 that are collocated with original input pixels 1136, 1138, and 1140 are illustrated. As shown in FIG. 96, the collocated reference pixels 1130, 1132, and 1134 are located in the same spatial position as original input pixels 1136, 1138, and 1140. However, the reference pixels 1130, 1132, and 1134 are located in a previous frame in time as indicated by “t−1,” where t represents the current frame in time.

In one embodiment, instead of using three collocated horizontal pixels, the temporal filter block 1028 may calculate the motion delta d(j,i,t) for the respective pixel by determining the maximum of absolute deltas between original and reference pixels for N×N collocated pixels of the same color. For instance, the temporal filter block 1029 may determine the absolute delta between the original pixel values and the reference pixel values for 3×3 or 5×5 collocated pixels of the same color.

After calculating the motion delta d(j,i,t), the temporal filter block 1028 may use the motion delta d(j,i,t) to determine a filter coefficient to be applied to the pixel value x(j,i,t). As mentioned above, when pixel motion is high, the filtering strength (i.e., filter coefficient) may be reduced in order to avoid the appearance of “trailing” or “ghosting artifacts” in the resulting processed image. In one embodiment, the temporal filter block 1028 may determine the filter coefficient for a respective pixel using a motion table (M). The motion table (M) may include a number of filter coefficients (K) which may be predetermined based on a noise variance for different brightness values of a pixel. In one embodiment, the motion table (M) may be indexed according to a motion table lookup index (m) and a brightness value (b) for the respective pixel as shown below.
M[b][m]
where b corresponds to a brightness value of a pixel and m corresponds to a motion table lookup index for the pixel.

The motion table lookup index (m) may represent a motion for the respective pixel. As such, the motion table lookup index (m) may be determined based on the motion delta d(j,i,t) and a motion history value (i.e., motion delta d(j,i,t−1) of the reference pixel at time t−1) for the respective pixel. Keeping this in mind, at block 1116, the temporal filter block 1028 may determine the motion table lookup index (m) for the respective pixel. In one embodiment, the motion lookup index lookup (m) and the motion history output h(t) may be determined using the following formulas:
m=gain_rad*gain[comp]*(d(j,i,t)+h(j,i,t−1))
h(j,i,t)=d(j,i,t)+K*(h(j,i,t−1)−d(j,i,t))
where gain_rad is a radial gain lookup table interpolation function that performs a linear interpolation between a radial gain table and a radius of an optical center of a pixel, K is a filter coefficient from the motion table M, d(j,i,t) corresponds to the motion delta value for a pixel at time t, h(j,i,t−1) corresponds to the motion delta value for a pixel at time t−1, and gain[comp] corresponds to a gain associated with the color of the pixel.

In addition to the motion table lookup index (m), the motion table (M) may be indexed according to a brightness value (b) for the respective pixel. As mentioned above, as image brightness increases, filtering artifacts may become more noticeable to the human eye. Thus, the filter coefficients (K) in the motion table (M) may be indexed such that the filter coefficients (K) may decrease as the brightness value of the pixel increases. In one embodiment, the motion table (M) may be set to a number of brightness levels such that each brightness level may be defined as a percentage of a maximum brightness value. In this manner, the filter coefficients (K) may be adjusted based on the brightness level of the pixel.

In one embodiment, the brightness level adjusted filter coefficients (K) may be represented in the motion table (M) by setting the motion table (M) to multiple brightness levels. That is, multiple motion tables may be used to represent the motion table (M) for each brightness level such that each of the multiple motion table may include filter coefficients (K) adjusted according to the brightness level of the pixel. For instance, the motion table (M) may be set to three brightness levels such that each of the three brightness levels may be associated with a respective motion table (e.g., motion table (M1), (M2), and (M3)). Each respective motion table may include 65 entries. The three brightness levels may correspond to 0% of the maximum brightness value for the respective pixel, 50% of the maximum brightness value for the respective pixel, and 100% of the maximum brightness value for the respective pixel.

Alternatively, the motion table (M) may be set to five brightness levels (e.g., motion table (M1), (M2), (M3), (M4), and (M5)) such that each motion table may include 65 entries. The five brightness levels may correspond to 0% of the maximum brightness value for the respective pixel, 25% of the maximum brightness value for the respective pixel, 50% of the maximum brightness value for the respective pixel, 75% of the maximum brightness value for the respective pixel, and 100% of the maximum brightness value for the respective pixel. FIG. 12A and FIG. 12B illustrate the three brightness level and five brightness level embodiments described above.

Although the motion table (M) has been described as being set to multiple brightness levels, it should be noted that in one embodiment the motion table (M) may be set to just one brightness level. In this case, the motion table (M) may be a one-dimensional table with 257 entries that may be stored in a corresponding memory.

Keeping the foregoing in mind, at block 1118, the temporal filter block 1028 may determine a brightness value of the respective pixel. At block 1120, the temporal filter block 1028 may determine whether the motion table (M) is set to more than one brightness level. If the motion table (M) is set to one brightness level, the temporal filter block 1028 may proceed to block 1124. If, however, the motion table (M) is set to more than one brightness level, the temporal filter block 1028 may proceed to block 1122.

When the motion table is set to one brightness level, at block 1124, the temporal filter block 1028 may determine a motion table filter coefficient (e.g., K) based on the single motion table (M) and the motion table lookup index (m) of the respective pixel. The process for determining the motion table filter coefficient (K) is described in greater detail below with reference to FIG. 98, which describes a method 1150 for determining a motion table filter coefficient (K) for the respective pixel.

Referring to FIG. 98, at block 1152, the temporal filter block 1028 may identify at least two motion table lookup indexes (e.g., m1 and m2) for the motion table (M). The two identified motion table lookup indexes (m1 and m2) for the motion table (M) may correspond to two motion table lookup indexes that are adjacent to (e.g., above and below) the motion table lookup index (m) for the respective pixel determined at block 1116. Here, the temporal filter block 1028 may identify at least two motion table lookup indexes (e.g., m1 and m2) for the motion table (M) because the motion table (M) may not have an index value that exactly matches the motion table lookup index (m) determined at block 1116. By identifying the at least two motion table lookup indexes (e.g., m1 and m2) adjacent to the motion table lookup index (m), the temporal filter block 1028 may be able to interpolate a filter coefficient value that corresponds to the motion table lookup index (m) using the filter coefficient values for the two motion table lookup indexes (e.g., m1 and m2). In this manner, the temporal filter block 1028 may determine a filter coefficient that may most effectively filter the respective pixel.

Keeping this mind, at block 1154, the temporal filter block 1028 may use the two adjacent motion table lookup indexes (m1 and m2) and retrieve two motion table filter coefficients (e.g., K1 and K2) from the motion table (M). In one embodiment, the motion table filter coefficients may be determined based on the following equation:
K=M[b][m]=M[x(j,i,t)][gain_rad*gain[comp]*(d(j,i,t)+h(j,i,t−1))]
where b, m, x(j,i,t), gain_rad, gain[comp], d(j,i,t), and h(j,I,t−1) are the same as defined above.

Referring back to FIG. 95, at block 1126, the temporal filter block 1028 may linearly interpolate the interpolated motion table filter coefficient (K3) with the brightness value (b) of the respective pixel (from block 1118) to determine a final filter coefficient (e.g., K) for the respective pixel.

Referring back to block 1120, if the motion table (M) is set to more than one brightness level, the temporal filter block 1028 may proceed to block 1122. At block 1122, the temporal filter block 1028 may identify at least two brightness levels (e.g., brightness levels 1 & 2) that are adjacent to the brightness value (b) for the respective pixel. As such, the temporal filter block 1028 may identify two brightness levels that correspond to a brightness level above and below the brightness value of the respective pixel. Here, the temporal filter block 1028 may identify the two brightness levels above and below the brightness value of the respective pixel because none of the brightness levels may exactly matches the brightness value of the pixel. By identifying the two brightness levels above and below the brightness value of the respective pixel, the temporal filter block 1028 may be able to interpolate a filter coefficient value for the respective pixel that account for the brightness value of the respective pixel.

After identifying the two brightness levels adjacent to the brightness value of the respective pixel, at block 1124, the temporal filter block 1028 may determine two motion table filter coefficients (e.g., K1 & K2) that correspond to the two motion tables (e.g., motion table 1 & 2) associated with the two identified brightness levels (e.g., brightness level 1 & 2). As mentioned above, the process for determining the motion table filter coefficients is described in greater detail with reference to FIG. 98.

Referring again to FIG. 98, at block 1152, the temporal filter block 1028 may first identify at least two motion table lookup indexes for each motion table associated with two brightness levels (e.g., index 1 and 2 for motion table 1; index 3 and 4 for motion table 2). The two identified motion table lookup indexes for each motion table may correspond to motion table lookup indexes that are adjacent to (e.g., above and below) the motion table lookup index (m) for the respective pixel. As mentioned above, by identifying the two motion table lookup indexes for each motion table associated with two brightness levels (e.g., index 1 and 2 for motion table 1; index 3 and 4 for motion table 2), the temporal filter block 1028 may be able to interpolate a filter coefficient value for each brightness level even though each motion table may not have an index value that exactly matches the motion table lookup index (m) determined at block 1116.

Keeping this in mind, at block 1154, the temporal filter block 1028 may retrieve two motion table filter coefficients from each motion table (e.g., K3 & K4 from motion table 1, K5 & K6 from motion table 2) using the two adjacent motion table lookup indexes (e.g., index 1 and 2 for motion table 1; index 3 and 4 for motion table 2). In one embodiment, the motion table filter coefficients may be determined based the equations listed above.

At block 1156, the temporal filter block 1028 may linearly interpolate the two motion table filter coefficients from each motion table (K3 & K4 from motion table 1, K5 & K6 from motion table 2) to determine an interpolated motion table filter coefficient that most closely corresponds to a filter coefficient that may have been retrieved from the motion tables (motion table 1 & 2) using the motion table lookup index (m) determined at block 1116.

Referring back to FIG. 95, at block 1126, the temporal filter block 1028 may linearly interpolate the two interpolated motion table filter coefficients (K1 and K2) determined at block 1124 with the brightness value (b) of the respective pixel determined at block 1118. As a result, the temporal filter block 1028 may determine a final filter coefficient (e.g., K) for the respective pixel that has been adjusted to account for the motion occurring within the respective pixel and the brightness value of the pixel. That is, since noise variance changes with the brightness and motion values of a pixel, the temporal filter block 1028 may modify the filtering strength (filter coefficient) to account for motion occurring within a pixel and a brightness value of the pixel, thereby avoiding trailing or ghosting artifacts from being displayed in the image.

In addition to the processes described above with reference to FIG. 95 and FIG. 98, additional temporal filtering steps may be performed to further remove noise from the image data received by the temporal filter block 1028. This noise, however, may not be related to the motion occurring within a pixel. For instance, FIG. 99 illustrates a process diagram depicting a temporal filtering process 1160 that may be performed within the temporal filter block 1028. As shown in process 1160, the temporal filter block 1028 may include a 2-tap filter such that its filter coefficients may be adjusted adaptively on a per pixel basis based at least partially upon motion and brightness data. In one embodiment, temporal filter block 1028 may perform the processes described above with reference to FIG. 95 and FIG. 98 in a first tap of the temporal filtering process 1160 (the motion table 1162). As shown in FIG. 99, the temporal filter block 1028 may output a motion history value h(t) and a filter coefficient (K) for each pixel in the raw image data from the motion table 1162.

In one embodiment, after determining the filter coefficient (K) from the motion table 1162, the temporal filter block 1028 may use the brightness value (b) of the respective pixel x(j,i,t) to generate a luma table lookup index (l) in a luma table (L) 1164. As mentioned above, as image brightness increases, filtering artifacts may become more noticeable to the human eye. Thus, the filtering strength may be further reduced when a pixel has a high level of brightness. In one embodiment, the luma table (L) may contain attenuation factors that between 0 and 1 that may be used to account for the brightness of the image without regard to the motion occurring within the image. In one embodiment, the attenuation factors from the luma table (L) may be selected based upon the luma table lookup index (l).

As such, a second filter coefficient, K′, may be calculated by multiplying the first filter coefficient (K) by the luma attenuation factor, as shown in the following equation:
K′=K×L[gain_rad*gain[comp]*x(j,i,t)]

The determined value for K′ may then be used as the filtering coefficient by the temporal filter block 1028. As such, the temporal filter block 1028 may account for the motion of each pixel of the image with reference to its brightness value and may account for the brightness value of each pixel of the image independent of its motion value. In one embodiment, the temporal filter block 1028 may be an infinite impulse response (IIR) filter using previous filtered frame or as a finite impulse response (FIR) filter using previous original frame. The temporal filter block 1028 may compute the filtered output pixel (Yout) using the current input pixel x(t), the reference pixel r(t−1), and the filter coefficient K′ using the following formula:
y(j,i,t)=x(j,i,t)+K′(r(j,i,t−1)−x(j,i,t))
The temporal filtering process 1160 shown in FIG. 99 may be performed on a pixel-by-pixel basis. In one embodiment, the same motion table (M) and luma table (L) may be used for all color components (e.g., R, G, and B).
Defective Pixel Correction (DPC)

Referring back to FIG. 91, the output of the temporal filter block 1028 is subsequently forwarded to the defective pixel correction logic 1030. In one embodiment, the temporal filter block 1028 may forward signed 17-bit data to the defective pixel detection and correction (DPC) logic 1030 which may be capable of operating on signed pixels. As discussed above with reference to FIG. 48 (DPR logic 474), defective pixels may attributable to a number of factors, and may include “hot” (or leaky) pixels, “stuck” pixels, and “dead pixels, wherein hot pixels exhibit a higher than normal charge leakage relative to non-defective pixels, and thus may appear brighter than non-defective pixel, and wherein a stuck pixel appears as always being on (e.g., fully charged) and thus appears brighter, whereas a dead pixel appears as always being off. As such, it may be desirable to have a pixel detection scheme that is robust enough to identify and address different types of failure scenarios. Particularly, when compared to the DPR logic 474, which may provide only dynamic defect detection/correction, the DPR logic 1030 may provide for fixed or static defect detection/correction, dynamic defect detection/correction, as well as speckle removal.

In accordance with embodiments of the presently disclosed techniques, defective pixel correction/detection performed by the DPR logic 1030 may occur independently for each color component (e.g., R, B, Gr, and Gb), and may include various operations for detecting defective pixels, as well as for correcting the detected defective pixels. For instance, in one embodiment, the defective pixel detection operations may provide for the detection of static defects, dynamics defects, as well as the detection of speckle, which may refer to the electrical interferences or noise (e.g., photon noise) that may be present in the imaging sensor. By analogy, speckle may appear on an image as seemingly random noise artifacts, similar to the manner in which static may appear on a display, such as a television display. Further, as noted above, dynamic defection correction is regarded as being dynamic in the sense that the characterization of a pixel as being defective at a given time may depend on the image data in the neighboring pixels. For example, a stuck pixel that is always on maximum brightness may not be regarded as a defective pixel if the location of the stuck pixel is in an area of the current image that is dominate by bright white colors. Conversely, if the stuck pixel is in a region of the current image that is dominated by black or darker colors, then the stuck pixel may be identified as a defective pixel during processing by the DPR logic 1030 and corrected accordingly.

With regard to static defect detection, the location of each pixel is compared to a static defect table, which may store data corresponding to the location of pixels that are known to be defective. For instance, in one embodiment, the DPR logic 1030 may monitor the detection of defective pixels (e.g., using a counter mechanism or register) and, if a particular pixel is observed as repeatedly failing, the location of that pixel is stored into the static defect table. Thus, during static defect detection, if it is determined that the location of the current pixel is in the static defect table, then the current pixel is identified as being a defective pixel, and a replacement value is determined and temporarily stored. In one embodiment, the replacement value may be the value of the previous pixel (based on scan order) of the same color component. The replacement value may be used to correct the static defect during dynamic/speckle defect detection and correction, as will be discussed below. Additionally, if the previous pixel is outside of the raw frame 308 (FIG. 21), then its value is not used, and the static defect may be corrected during the dynamic defect correction process. Further, due to memory considerations, the static defect table may store a finite number of location entries. For instance, in one embodiment, the static defect table may be implemented as a FIF0 queue configured to store a total of 16 locations for every two lines of image data. The locations in defined in the static defect table will, nonetheless, be corrected using a previous pixel replacement value (rather than via the dynamic defect detection process discussed below). As mentioned above, embodiments of the present technique may also provide for updating the static defect table intermittently over time.

Embodiments may provide for the static defect table to be implemented in on-chip memory or off-chip memory. As may be appreciated, using an on-chip implementation may increase overall chip area/size, while using an off-chip implementation may reduce chip area/size, but increase memory bandwidth requirements. Thus, it should be understood that the static defect table may be implemented either on-chip or off-chip depending on specific implementation requirements, i.e., the total number of pixels that are to be stored within the static defect table.

The dynamic defect and speckle detection processes may be time-shifted with respect to the static defect detection process discussed above. For instance, in one embodiment, the dynamic defect and speckle detection process may begin after the static defect detection process has analyzed two scan lines (e.g., rows) of pixels. As can be appreciated, this allows for the identification of static defects and their respective replacement values to be determined before dynamic/speckle detection occurs. For example, during the dynamic/speckle detection process, if the current pixel was previously marked as being a static defect, rather than applying dynamic/speckle detection operations, the static defect is simply corrected using the previously assessed replacement value.

With regard to dynamic defect and speckle detection, these processes may occur sequentially or in parallel. The dynamic defect and speckle detection and correction that is performed by the DPR logic 1030 may rely on adaptive edge detection using pixel-to-pixel direction gradients. In one embodiment, the DPR logic 1030 may select the eight immediate neighbors of the current pixel having the same color component that are within the raw frame 308 (FIG. 21) are used. In other words, the current pixels and its eight immediate neighbors P0, P1, P2, P3, P4, P5, P6, and P7 may form a 3×3 area, as shown below in FIG. 63.

It should be noted, however, that depending on the location of the current pixel P, pixels outside the raw frame 310 are not considered when calculating pixel-to-pixel gradients. For example, with regard to the “top-left” case 1172 shown in FIG. 100, the current pixel P is at the top-left corner of the raw frame 308 and, thus, the neighboring pixels P0, P1, P2, P3, and P5 outside of the raw frame 308 are not considered, leaving only the pixels P4, P6, and P7 (N=3). In the “top” case 1174, the current pixel P is at the top-most edge of the raw frame 308 and, thus, the neighboring pixels P0, P1, and P2 outside of the raw frame 308 are not considered, leaving only the pixels P3, P4, P5, P6, and P7 (N=5). Next, in the “top-right” case 1176, the current pixel P is at the top-right corner of the raw frame 308 and, thus, the neighboring pixels P0, P1, P2, P4, and P7 outside of the raw frame 308 are not considered, leaving only the pixels P3, P5, and P6 (N=3). In the “left” case 1178, the current pixel P is at the left-most edge of the raw frame 308 and, thus, the neighboring pixels P0, P3, and P5 outside of the raw frame 308 are not considered, leaving only the pixels P1, P2, P4, P6, and P7 (N=5).

In the “center” case 1180, all pixels P0-P7 lie within the raw frame 308 and are thus used in determining the pixel-to-pixel gradients (N=8). In the “right” case 1182, the current pixel P is at the right-most edge of the raw frame 308 and, thus, the neighboring pixels P2, P4, and P7 outside of the raw frame 308 are not considered, leaving only the pixels P0, P1, P3, P5, and P6 (N=5). Additionally, in the “bottom-left” case 1184, the current pixel P is at the bottom-left corner of the raw frame 308 and, thus, the neighboring pixels P0, P3, P5, P6, and P7 outside of the raw frame 308 are not considered, leaving only the pixels P1, P2, and P4 (N=3). In the “bottom” case 1186, the current pixel P is at the bottom-most edge of the raw frame 308 and, thus, the neighboring pixels P5, P6, and P7 outside of the raw frame 308 are not considered, leaving only the pixels P0, P1, P2, P3, and P4 (N=5). Finally, in the “bottom-right” case 1188, the current pixel P is at the bottom-right corner of the raw frame 308 and, thus, the neighboring pixels P2, P4, P5, P6, and P7 outside of the raw frame 308 are not considered, leaving only the pixels P0, P1, and P3 (N=3).

In one embodiment, the DPR logic 1030 may correct for defective pixels from the bottom-left part of the image to the top-right part of the image. As such, when a pixel being evaluated is not at the boundaries of the raw frame 308, neighboring pixels P0-P4 may not have been corrected by the DPR logic 1030, while the defects in the neighboring pixels P5-P7 may have been corrected (if any defects were present). In another embodiment, when a pixel being evaluated is at the top edge, pixel P0 may be uncorrected and instead pixel P3 may be replicated in the place of pixel P0. Similarly, when a pixel being evaluated is at the bottom edge, pixel P5 may be uncorrected and instead P3 may be replicated in its place.

Thus, depending upon the position of the current pixel P, the number of pixels used in determining the pixel-to-pixel gradients may be 3, 5, or 8. In the illustrated embodiment, for each neighboring pixel (k=0 to 7) within the picture boundary (e.g., raw frame 308), the pixel-to-pixel gradients may be calculated as follows:
Gk=abs(P−Pk),for 0≦k≦7(only for k within the raw frame)
where the value for each pixel (k=0 to 7) is a 17-bit signed value. An average gradient, Gay, may be calculated as the difference between the current pixel and the average, Pav, of its surrounding pixels, as shown by the equations below:

Pav=(∑kN⁢Pk)N,wherein⁢⁢N=3,5,or⁢⁢8⁢⁢(depending⁢⁢on⁢⁢pixel⁢⁢position)⁢Gav⁢=abs⁡(P-Pav)
The pixel-to-pixel gradient values may be used in determining a dynamic defect case, and the average of the neighboring pixels may be used in identifying speckle cases, as discussed further below.

In one embodiment, the average pixel value, Pav, of the neighboring pixels may account for neighboring defective pixels by the excluding the minimum and maximum values of the neighboring pixels (K=0 to 7) when determining the average pixel value, Pav. In this manner, a defective pixel is assumed to correspond to either the minimum and/or maximum pixel value among the surrounding neighbor pixels (P0 . . . P7). By excluding the minimum and maximum pixel values from the computation of the average pixel value, Pav, the average pixel value, Pav, may account for the defective neighboring pixels and may be more robust for processing. In the illustrated embodiment of FIG. 100, for each neighboring pixel (k=0 to 7) within the picture boundary (e.g., raw frame 308), the average pixel value, Pav, may be calculated as follows:

P=min(Pk)

Pmax=max(Pk)

Pmax=(P0+P1+P2+P3+P4+P5+P6+P7−Pmax−Pmin)/6

In one embodiment, dynamic defect detection may be performed by the DPR logic 1030 as follows. First, it is assumed that a pixel is defective if a certain number of the gradients Gk are at or below a particular threshold, denoted by the variable defect_thd (dynamic defect threshold). Thus, for each pixel, a count (C) of the number of gradients for neighboring pixels inside the picture boundaries that are at or below the threshold defect_thd is accumulated. The threshold defect_thd may be a combination of a fixed threshold component and a dynamic threshold component that may depend on the “activity” present the surrounding pixels. For instance, in one embodiment, the dynamic threshold component for defect_thd may be determined by calculating a high frequency component value Phf based upon summing the absolute difference between the average pixel values Pav and each neighboring pixel, as illustrated below:

Phf=8N⁢∑kN⁢abs⁡(Pav-Pk)⁢⁢wherein⁢⁢N=3,5,or⁢⁢8
In instances where the pixel is located at an image corner (N=3) or at an image edge (N=5), the Phf may be multiplied by the 8/3 or 8/5, respectively. As can be appreciated, this ensures that the high frequency component Phf is normalized based on eight neighboring pixels (N=8).

Once Phf is determined, the dynamic defect detection threshold defect_thd may be computed for each color component based on the average pixel value Pav and the high frequency component Phf. More specifically, the dynamic defect detection threshold defect_thd may be determined by first identifying two brightness levels (x0 and x1) that are above and below the average pixel value Pav. In one embodiment, five equally spaced brightness levels may be defined between 0 and 2^16. As such, the brightness value may be represented by a 16-bit value between 0 and 65,536, which may correspond to a signed 17-bit pixel value. Accordingly, each brightness level may include 16,384 values such that each pixel value may fit within one of the brightness levels. Further, each brightness level may be denoted a brightness value (x_val) that corresponds to a multiple of 16,384 (16,384*i where i=0, 1, 2, 3, 4).

In one embodiment, a defect threshold array (defect_thd) may be defined for each brightness level. After identifying the two brightness levels (x0 and x1) that are above and below the average pixel value Pav, two defect threshold values (defect_thd0 and defect_thd1) that may be used to determine the dynamic defect detection threshold defect_thd may be calculated as follows:

tmp0=dpc_thd0[c][x0];

tmp1=dpc_thd0[c][x1];

defect_thd0=(((tmp0*(x1_val−Pav))+((tmp1*(Pav−x0_val))+8192)/16384;

tmp0=dpc_thd1[c][x0];

tmp1=dpc_thd1[c][x1];

defect_thd1=(((tmp0*(x1_val−Pav))+((tmp1*(Pav−x0_val))+8192)/16384;
where tmp0 and tmp1 are temporary values; dpc_thd0[c][x0], dpc_thd0[c][x1], dpc_thd1[c][x0], dpc_thd1[c][x1] are data arrays associated with each identified brightness level such that the data arrays include defect detection threshold values indexed according to color component (c) and brightness level (x0/x1), and x1_val and x2_val are brightness values associated with each of the identified brightness level.

In one embodiment, the dynamic defect detection threshold defect_thd may be determined by interpolating the two defect threshold values (defect_thd0 and defect_thd1) as follows:

defect_thd=defect_thd0+(defect_thd1*Phf+2048)/4096

In another embodiment, the dynamic defect detection threshold defect_thd may be determined by as a max between the defect threshold value defect_thd0 and the defect threshold value defect_thd1*Phf/4096 as shown below:

defect_thd=max (defect_thd0, (defect_thd1*Phf+2048)/4096)

As mentioned above, for each pixel, a count C of the number of gradients for neighboring pixels inside the picture boundaries that are at or below the threshold defect_thd is determined. For instance, for each neighboring pixel within the raw frame 308, the accumulated count C of the gradients Gk that are at or below the threshold defect_thd may be computed as follows:

C=∑kN⁢(Gk≤defect_thd),for⁢⁢0≤k≤7⁢⁢(only⁢⁢for⁢⁢k⁢⁢within⁢⁢the⁢⁢raw⁢⁢frame)
Next, if the accumulated count C is determined to be less than or equal to a maximum count, denoted by the variable defect_max, then the pixel may be considered as a dynamic defect. In one embodiment, different values for defect_max may be provided for N=3 (corner), N=5 (edge), and N=8 conditions. This logic is expressed below:

if (C<defect_max), then the current pixel P is defective.

As mentioned above, the location of defective pixels may be stored into the static defect table. In some embodiments, the minimum gradient value (min(Gk)) calculated during dynamic defect detection for the current pixel may be stored and may be used to sort the defective pixels, such that a greater minimum gradient value indicates a greater “severity” of a defect and should be corrected during pixel correction before less severe defects are corrected. In one embodiment, a pixel may need to be processed over multiple imaging frames before being stored into the static defect table, such as by filtering the locations of defective pixels over time. In the latter embodiment, the location of the defective pixel may be stored into the static defect table only if the defect appears in a particular number of consecutive images at the same location. Further, in some embodiments, the static defect table may be configured to sort the stored defective pixel locations based upon the minimum gradient values. For instance, the highest minimum gradient value may indicate a defect of greater “severity.” By ordering the locations in this manner, the priority of static defect correction may be set, such that the most severe or important defects are corrected first. Additionally, the static defect table may be updated over time to include newly detected static defects, and ordering them accordingly based on their respective minimum gradient values.

Speckle detection, which may occur in parallel with the dynamic defect detection process described above, may be performed by determining if the value Gav (Equation 52b) is above a speckle detection threshold despeckle_thd. Like the dynamic defect threshold defect_thd, the speckle threshold despeckle_thd may also include fixed and dynamic components, referred to by despeckle_thd0 and despeckle_thd1, respectively. In general, the fixed and dynamic components despeckle_thd0 and despeckle_thd1 may be set more “aggressively” compared to the defect_thd0 and defect_thd1 values, in order to avoid falsely detecting speckle in areas of the image that may be more heavily textured and others, such as text, foliage, certain fabric patterns, etc. Accordingly, in one embodiment, the dynamic speckle threshold component despeckle_thd1 may be increased for high-texture areas of the image, and decreased for “flatter” or more uniform areas.

In one embodiment, the speckle detection threshold despeckle_thd may be computed similar to how the dynamic defect detection threshold defect_thd is computed as described above. As such, a despeckle threshold array (dpc_desp_thd) may be defined for each brightness level. After identifying the two brightness levels (x0 and x1) that are above and below the average pixel value Pav, two despeckle threshold values (dpc_desp_thd0 and dpc_desp_thd1) used to determine the speckle detection threshold despeckle_thd may be determined as follows:

tmp0=dpc_desp_thd0[c][x0];

tmp1=dpc_desp_thd0[c][x1];

despecklethd0=(((tmp0*(x1_val−Pav))+((tmp1*(Pav−x0_val))+8192)/16384;

tmp0=dpc_desp_thd1[c][x0];

tmp1=dpc_desp_thd1[c][x1];

despeckle_thd1=(((tmp0*(x1_val−Pav))+((tmp1*(Pav−x0_val))+8192)/16384;
where tmp0 and tmp1 are temporary values; dpc_desp_thd0[c][x0], dpc_desp_thd0[c][x1], dpc_desp_thd1[c][x0], dpc_desp_thd1[c][x1] are data arrays associated with each identified brightness level such that the data arrays include defect detection threshold values indexed according to color component (c) and brightness level (x0/x1), and x1_val and x2 val are brightness values associated with each of the identifsamied brightness level.

In one embodiment, the speckle detection threshold despeckle_thd may be determined by interpolating the two speckle detection threshold values (despeckle_thd0 and despeckle_thd1) as follows:

despeckle_thd=despeckle_thd0+(despeckle_thd1*Phf+2048)/4096

In another embodiment, the speckle detection threshold despeckle_thd may be determined by as a max between the speckle threshold value despeckle_thd0 and the speckle threshold value despeckle_thd1*Phf/4096 as shown below:

despeckle_thd=max (despeckle_thd0, (despeckle_thd1*Phf+2048)/4096)
The detection of speckle may then be determined in accordance with the following expression:

if (Gav>despeckle_thd), then the current pixel P is speckled.

Once defective pixels have been identified, the DPR logic 1030 may store the locations of the defective pixels to the memory 100. The DPR logic 1030 may then use the stored locations of the defective pixels to determine the static defect table. The DPR logic 1030 may maintain a counter that specifies a maximum number of defective pixels written into the memory 100 (dpc_dynamic_max). In one embodiment, the DPR logic 1030 may store each location of the defective pixel in the memory 100 as a 32-bit word. The 32-bit word may include bits 0-11 that represent the column number, bits 12-23 that represent the row number, and bits 24-31 that represent either a scaled version of the minimum gradient value (i.e., min(Gk)) or a scaled version of the defective pixel value before correction. In one embodiment, the DPR logic 1030 may use the scaled version of the defective pixel value before correction if specified by a user (e.g., if variable DynamicDMAOutPixelEn is set to 1). When Gmin is selected for bits 24-31, since only 8 bits are available, the DPR logic 1030 may shift Gmin by some amount (e.g., GminShift).

In one embodiment, the stored Gmin scaled value may be obtained as min(0xff, Gmin>>GminShift), where GminShift is a programmable parameter. In this manner, the DPR logic 1030 may select a range and saturate if Gmin[15:0] is larger than the selected range. If the DPR logic 1030 may use the scaled version of the defective pixel value before correction if specified by a user (e.g., if variable DynamicDMAOutPixelEn is set to 1), in place of the Gmin value, the bits 8-15 of the uncorrected defective may also be included. Here, the pixel value included is the original pixel value (if stored in memory 100) or statically replaced value (if not stored in memory 100). Also, it should be noted that the pixel value corresponds to a value that is obtained before subtracting a ZeroBias. In one embodiment, the DPR logic 1030 may use the input pixel value to determine the distribution of defective pixels, which may be useful to determine the statistics of Random Telegraph Signal (RTS) noise. If the number of entries written into the memory 100 is not a multiple of 64-bytes, the DPR logic 1030 may write zeros to complete the remaining bytes in the last 64-byte block. In one embodiment, the DPR logic 1030 may ensure that the allocated portion of the memory 100 is a multiple of 64-bytes.

After identifying and storing the locations of the defective pixels, the DPR logic 1030 may apply pixel correction operations depending on the type of defect detected. For instance, if the defective pixel was identified as a static defect, the pixel is replaced with the stored replacement value, as discussed above (e.g., the value of the previous pixel of the same color component). If the pixel was identified as either a dynamic defect or as speckle, then pixel correction may be performed as follows.

In one embodiment, gradients may be computed as the sum of the absolute difference between the center pixel and a first and second neighbor pixels (e.g., computation of Gk of Equation 51) for four directions, a horizontal (h) direction, a vertical (v) direction, a diagonal-positive direction (dp), and a diagonal-negative direction (dn), as shown below:

Gh=G3+G4

Gv=G1+G6

Gdp=G2+G5

Gdn=G0+G7

Next, the corrective pixel value Pc may be determined via linear interpolation of the two neighboring pixels associated with the directional gradient Gh, Gv, Gdp, and Gdn that has the smallest value. For instance, in one embodiment, the logic statement below may express the calculation of PC:

if⁡(min==Gh)PC=P3+P42;else⁢⁢if⁢⁢(min==Gv)PC=P1+P62;else⁢⁢if⁡(min==Gdp)PC=P2+P52;else⁢⁢if⁡(min==Gdn)PC=P0+P72;
The pixel correction techniques implemented by the DPR logic 1030 may also provide for exceptions at boundary conditions. For instance, if one of the two neighboring pixels associated with the selected interpolation direction is outside of the raw frame, then the value of the neighbor pixel that is within the raw frame is substituted instead. Thus, using this technique, the corrective pixel value will be equivalent to the value of the neighbor pixel within the raw frame. As mentioned above, neighboring pixels P0-P3 may not have been corrected by DPR logic 1030, while the defects in the neighboring pixels P4-P7 may have been corrected.

In another embodiment, pixel correction operations may use pixel values from other Bayer color components to correct the defective pixels. By using high-frequency information from other Bayer color components, the pixel correction operations may reduce color artifacts from being introduced in the defective pixel corrected image.

When correcting the defective pixels using pixel values from other Bayer color components, the 5×5 neighboring pixels (including those from other color components) may be convolved with a symmetric filter that has 5×5 spatial support. The coefficients that may be used in conjunction with the symmetric filter may be defined with respect to the defective pixel as shown in FIG. 101. In one embodiment, each color component (Gr, R, B, Gb) may have 8 programmable coefficients such that each coefficient may be a signed 16-bit number with 12 fractional bits. The center tap may be set to 0 since it corresponds to the defective pixels. In total, there may be 32 programmable coefficients to define four 5×5 filter kernels for correcting the defective pixels.

In one embodiment, the coefficients that may be used in conjunction with the symmetric filter may be trained using a standard film photograph or an image acquired using a charge-coupled device (i.e., reference image). That is, the coefficients may be determined by comparing the image data acquired by the sensors 90 and the reference image using various analysis processes such as, for example, a least square fit, a genetic learning algorithm, or a 1st order absolute difference.

The defective pixel correction process using 5×5 filtering may include interpolating the pixel values surrounding the respective defective pixel using the respective coefficients for the surrounding pixels. This process is summarized as follows.

outPix(j,i)=max(0, min(65535, filtVal));
where im(j,i) denotes the pixel value for the defective pixel located at (j, i) such that i denotes a horizontal location and j denotes a vertical location of a pixel, and n indicates a Bayer color component of the pixel.

It should be noted that the defective pixel detection/correction techniques applied by the DPR logic 1030 during the raw processing block 150 is more robust compared to the DPR logic 474 described above. As discussed in the embodiment above, the DPR logic 474 performs only dynamic defect detection and correction using neighboring pixels in only the horizontal direction, whereas the DPR logic 1030 provides for the detection and correction of static defects, dynamic defects, as well as speckle, using neighboring pixels in both horizontal and vertical directions.

As may be appreciated, the storage of the location of the defective pixels using a static defect table may provide for temporal filtering of defective pixels with lower memory requirements. For instance, compared to many conventional techniques which store entire images and apply temporal filtering to identify static defects over time, embodiments of the present technique only store the locations of defective pixels, which may typically be done using only a fraction of the memory required to store an entire image frame. Further, as discussed above, the storing of a minimum gradient value (min(Gk)), allows for an efficient use of the static defect table prioritizing the order of the locations at which defective pixels are corrected (e.g., beginning with those that will be most visible).

Additionally, the use of thresholds that include a dynamic component (e.g., defect_thd1 and despeckle_thd1) may help to reduce false defect detections, a problem often encountered in conventional image processing systems when processing high texture areas of an image (e.g., text, foliage, certain fabric patterns, etc.). Further, the use of directional gradients (e.g., h, v, dp, dn) for pixel correction may reduce the appearance of visual artifacts if a false defect detection occurs. For instance, filtering in the minimum gradient direction may result in a correction that still yields acceptable results under most cases, even in cases of false detection. Additionally, the inclusion of the current pixel P in the gradient calculation may improve the accuracy of the gradient detection, particularly in the case of hot pixels.

The above-discussed defective pixel detection and correction techniques implemented by the DPR logic 1030 may be summarized by a series of flowcharts provided in FIGS. 102-104. For instance, referring first to FIG. 102, a process 1200 for detecting static defects is illustrated. Beginning initially at step 1202, an input pixel P is received at a first time, T0. Next, at step 1204, the location of the pixel P is compared to the values stored in a static defect table. Decision logic 1206 determines whether the location of the pixel P is found in the static defect table. If the location of P is in the static defect table, then the process 1200 continues to step 1208, wherein the pixel P is marked as a static defect and a replacement value is determined. As discussed above, the replacement value may be determined based upon the value of the previous pixel (in scan order) of the same color component. The process 1200 then continues to step 1210, at which the process 1200 proceeds to the dynamic and speckle detection process 1220, illustrated in FIG. 103. Additionally, if at decision logic 1206, the location of the pixel P is determined not to be in the static defect table, then the process 1200 proceeds to step 1210 without performing step 1208.

Continuing to FIG. 103, the input pixel P is received at time T1, as shown by step 1222, for processing to determine whether a dynamic defect or speckle is present. Time T1 may represent a time-shift with respect to the static defect detection process 1200 of FIG. 101. As discussed above, the dynamic defect and speckle detection process may begin after the static defect detection process has analyzed two scan lines (e.g., rows) of pixels, thus allowing time for the identification of static defects and their respective replacement values to be determined before dynamic/speckle detection occurs.

The decision logic 1224 determines if the input pixel P was previously marked as a static defect (e.g., by step 1208 of process 1200). If P is marked as a static defect, then the process 1220 may continue to the pixel correction process shown in FIG. 103 and may bypass the rest of the steps shown in FIG. 103. If the decision logic 1224 determines that the input pixel P is not a static defect, then the process continues to step 1226, and neighboring pixels are identified that may be used in the dynamic defect and speckle process. For instance, in accordance with the embodiment discussed above and illustrated in FIG. 100, the neighboring pixels may include the immediate 8 neighbors of the pixel P (e.g., P0-P7), thus forming a 3×3 pixel area. Next, at step 1228, pixel-to-pixel gradients are calculated with respect to each neighboring pixel within the raw frame 308. Additionally, an average gradient (Gav) may be calculated as the difference between the current pixel and the average of its surrounding pixels, as shown above.

The process 1220 then branches to step 1230 for dynamic defect detection and to decision logic 1238 for speckle detection. As noted above, dynamic defect detection and speckle detection may, in some embodiments, occur in parallel. At step 1230, a count C of the number of gradients that are less than or equal to the threshold defect_thd is determined. As described above, the threshold defect_thd may include fixed and dynamic components. If C is less than or equal to a maximum count, dynMaxC, then the process 1220 continues to step 1236, and the current pixel is marked as being a dynamic defect. Thereafter, the process 1220 may continue to the pixel correction process shown in FIG. 104, which will be discussed below.

Returning back the branch after step 1228, for speckle detection, the decision logic 1238 determines whether the average gradient Gav is greater than a speckle detection threshold despeckle_thd, which may also include a fixed and dynamic component. If Gav is greater than the threshold despeckle_thd, then the pixel P is marked as containing speckle at step 1000 and, thereafter, the process 1220 continues to FIG. 104 for the correction of the speckled pixel. Further, if the output of both of the decision logic blocks 1232 and 1238 are “NO,” then this indicates that the pixel P does not contain dynamic defects, speckle, or even static defects (decision logic 1224). Thus, when the outputs of decision logic 1232 and 1238 are both “NO,” the process 1220 may conclude at step 1234, whereby the pixel P is passed unchanged, as no defects (e.g., static, dynamic, or speckle) were detected.

Continuing to FIG. 104, a pixel correction process 1250 in accordance with the techniques described above is provided. At step 1252, the input pixel P is received from process 1220 of FIG. 103. It should be noted that the pixel P may be received by process 1250 from step 1224 (static defect) or from steps 1236 (dynamic defect) and 1240 (speckle defect). The decision logic 1254 then determines whether the pixel P is marked as a static defect. If the pixel P is a static defect, then the process 1250 continues and ends at step 1256, whereby the static defect is corrected using the replacement value determined at step 1208 (FIG. 102).

If the pixel P is not identified as a static defect, then the process 1250 continues from decision logic 1254 to step 1258, and directional gradients are calculated. For instance, as discussed above, the gradients may be computed as the sum of the absolute difference between the center pixel and first and second neighboring pixels for four directions (h, v, dp, and dn). Next, at step 1260, the directional gradient having the smallest value is identified and, thereafter, decision logic 1262 assesses whether one of the two neighboring pixels associated with the minimum gradient is located outside of the image frame (e.g., raw frame 310). If both neighboring pixels are within the image frame, then the process 1250 continues to step 1264, and a pixel correction value (PC) is determined by applying linear interpolation to the values of the two neighboring pixels. Thereafter, the input pixel P may be corrected using the interpolated pixel correction value PC, as shown at step 1270.

Returning to the decision logic 1262, if it is determined that one of the two neighboring pixels are located outside of the image frame (e.g., raw frame 308), then instead of using the value of the outside pixel (Pout), the DPR logic 1030 may substitute the value of Pout with the value of the other neighboring pixel that is inside the image frame (Pin), as shown at step 1266. Thereafter, at step 1268, the pixel correction value PC is determined by interpolating the values of Pin and the substituted value of Pout. In other words, in this case, PC may be equivalent to the value of Pin. Concluding at step 1270, the pixel P is corrected using the value PC. Before continuing, it should be understood that the particular defective pixel detection and correction processes discussed herein with reference to the DPR logic 1030 are intended to reflect only one possible embodiment of the present technique. Indeed, depending on design and/or cost constraints, a number of variations are possible, and features may be added or removed such that the overall complexity and robustness of the defect detection/correction logic is between the simpler detection/correction logic 474 and the defect detection/correction logic discussed here with reference to the DPR logic 1030.

Noise Statistics

After performing the defect detection/correction logic, the DPR logic 1030 may send to defective pixel corrected image data to the noise statistics logic 1031 to compute noise statistics for the input image. The noise statistics for the input image may enable various image processing stages in the raw block 150 such as, for example, the defective pixel detection/correction process, a spatial noise filtering process, a demosaicing process, and/or an image sharpening process. These processes may use the noise statistics to more accurately perform their respective functions even though they may not be used to filter noise from the image data. For instance, a spatial noise filtering process, which will be described in detail later, may use noise statistics to properly filter dark and bright regions of the image data, even though the dark and bright regions of the image data may not be attributed to noise. As such, in one embodiment, the noise statistics logic 1031 may be implemented after each process in the raw block 150 since the noise may change after each process.

The noise statistics may include a standard deviation of noise versus a pixel intensity. Although the noise statistics may be measured during a calibration process while manufacturing the ISP pipe, the noise statistics may not be accurate as the environment (e.g. temperature) surrounding the sensors 90. Furthermore, reliable calibration of the noise statistics (noise profile) may not be a straightforward process; instead, reliable calibration of the noise statistics may use an extensive noise calibration process that may be prohibitively expensive.

In general, the noise statistics for the input image may be generated by first determining dominant gradient orientations for non-overlapping portions of the input image. After determining the dominant gradient orientations for each non-overlapping portion of the input image, a count of the dominant gradient orientations for non-overlapping portions of the input image may be calculated and stored in the memory 100. In addition to the count of dominant gradient orientations, the noise statistics may include a peak and a sum of gradient magnitudes for each non-overlapping portion of the input image. In one embodiment, the noise statistics logic 1031 may be performed within the DPR logic 1030 because the noise statistics are based on a computation of gradients, which is a function that is also performed by the DPR logic 1030. In this manner, the line buffers for the gradient computation may be used by the DPR logic 1030 to determine gradients in connection with the defective pixel detection/correction process and the noise statistics generation process. Although the DPR logic 1030 may be used to generate the noise statistics, in other embodiments other components in the raw block 150 may be used to perform the noise statistics logic 1031. Additional details with regard to how the noise statistics logic 1031 may compute the noise statistics for the input image is described in process 1280 below with reference to FIG. 105.

At block 1282, the noise statistics logic 1031 may identify portions or local regions on the input image where noise may be best estimated. Each portion on the input image may be a non-overlapping block of pixels on the input image. In one embodiment, the non-overlapping portions on the input image that may be well-suited for calculating noise statistics may include a flat surface. A flat surface on the input image may have gradient orientations that have a low frequency, an isotropic distribution, and a peak gradient magnitude that is relatively small as compared to the other gradients in a respective non-overlapping portion of the input image. For instance, FIG. 226 illustrates an example of low frequency portions (5402) of an input image and high frequency portions (5404) of the input image. As shown in FIG. 226, the low frequency portions 5402 of the input image may include relatively similar color such that each pixel in the portion may exhibit the same pixel intensity values.

After identifying the portions of the input image that may be well-suited to calculate the noise statistics, the noise statistics logic 1031 may be capable of estimating the noise statistics for the input image using just these portions.

At block 1284, the noise statistics logic 1031 may compute gradients for each portion of the input image. In one embodiment, the noise statistics logic 1031 may compute spatial gradient for one of the color components of the Bayer quads in each portion of the input image. As such, the Bayer color component may be specified to the noise statistics logic 1031 prior to performing the process 1280. For example, the noise statistics logic 1031 may compute the spatial gradients for the Bayer color component-Gr after the color component Gr has been specified to the noise statistics logic 1031. An example of a portion of the input image is illustrated in FIG. 106. The pixels (i.e., P, P0 . . . P7) shown in FIG. 106 may denote pixel values for the specified color component.

In one embodiment, the pixel data from the sensors 90 may have been scaled up to fit a range of the raw block 150. For example, a 10-bit image sensor may be scaled up by 4 in order to fully use the range of the raw block 150. In this manner, the sensors 90 may scale the pixel data down by 4 to compute the spatial gradient. Accordingly, when computing the spatial gradients, the noise statistics logic 1031 may bit-shift the spatial gradients (with rounding) by a specified amount (PixShift). The spatial gradients for a portion of the input image as illustrated in FIG. 106 may be calculated as follows:

G0═(P4−P3)>>PixShift;

G1=(P3−P4)>>PixShift;

G2=(P6−P1)>>PixShift;

G3=(P1−P6)>>PixShift;

G4=(P7−P0)>>PixShift;

G5=(P0−P7)>>PixShift;

G6=(P5−P2)>>PixShift;

G7=(P2−P5)>>PixShift;

At block 1286, the noise statistics logic 1031 may generate noise statistics for the input image based on the spatial gradients for each portion of the input image. In one embodiment, the noise statistics logic 1031 may generate a histogram that counts the dominant gradient orientations for each of portion of the input image. The histogram may include a number of bins (e.g., bin[0] to bin[7]) that correspond to maximum spatial gradient values for G0 through G7. As such, the noise statistics logic 1031 may determine which spatial gradient has the maximum value in each portion of the image. After determining the maximum spatial gradient for each portion of the input image, the noise statistics logic 1031 may increment respective bins in the histogram that corresponds to the orientation of the maximum spatial gradients for the respective portions of the input image. For example, when gradient G1 has the maximum (positive) value among the set of G0 through G7 for a respective portion of the input image, the noise statistics logic 1031 may increment bin[1] in the histogram by one.

In one embodiment, the histogram of dominant orientations may be represented as 16-bit values with two fractional bits. If more than one gradient the portion of the input image have the same maximum gradient value, the noise statistics logic 1031 may use fractional bits to account for ties. For instance, if G0 and G1 in a respective portion of the input image both have the same maximum gradient value, then the noise statistics logic 1031 may increment bin[0] and bin[1] of the histogram by ½. In one embodiment, the noise statistics logic 1031 may increment the respective bins of the histogram by ½ when there are two or three gradients that have the same maximum gradient values. In another embodiment, the noise statistics logic 1031 may increment the respective bins of the histogram by ¼ when there are four or more gradients that have the same maximum gradient values.

In one embodiment, the noise statistics logic 1031 may use the histogram of dominant gradient orientations to determine a standard deviation of the gradients in each non-overlapping portion of the input image. For instance, the noise statistics logic 1031 may compute the standard-deviation for and standard-deviation-mean for each non-overlapping portion of image. Using the resulting standard-deviation versus pixel intensity pairs, the noise statistics logic 1031 may perform a curve fitting operation to acquire standard-deviation versus pixel intensity curves. In one embodiment, the noise statistics logic 1031 may perform an outlier rejection, which may remove some of the outlier standard deviation values from the curve fitting operation. The curve fitting operation may be performed using linear, quadratic, or polynomial curves. FIG. 227 illustrates an example graph of the standard deviation values for each portion of the input image with respect to the pixel intensity value. Outlier standard deviation values are illustrated in FIG. 227 as “+” symbols.

In addition to the histogram of dominant gradient orientations, at block 1286, the noise statistics logic 1031 may determine a sum of the pixel intensities, a peak gradient magnitude, a sum of the gradient magnitudes for each portion of the input image, and a mean value for the sum of the gradient magnitudes for each portion of the input image. The peak gradient magnitude may be represented as a 16-bit value, and the sum of the gradient magnitude and the sum of the pixel intensities may be represented as 32-bit values. In one embodiment, when determining the sum of the pixel intensities, the sum of the gradient magnitudes for each portion of the input image, and/or the mean gradient magnitude sum value for each portion of the input image may be the same size. As such, the size of the portion of the input image may be set independently for the horizontal and vertical directions. The maximum number of horizontal portions of the input image may not exceed 128. Further, the size of the portions of the input image may be a multiple of two. The minimum horizontal interval between each portion of the input image may be 16 pixels wide in half-sensor-resolution and 32 pixels in full-sensor-resolution. The maximum number of pixels in each portion of the input (at full sensor resolution) may not to a predetermined number of bits (e.g., bit depth).

In one embodiment, the noise statistics logic 1031 may determine the gradient magnitude as follows:

Grad_Mag=(abs(G0)+abs (G2)+1)/2;
At block 1288, the noise statistics logic 1031 may store the histogram of dominant orientation, the sum of the pixel intensities, the peak gradient magnitude, and the sum of the gradient magnitudes (noise statistics) in memory 100 in scan order. In one embodiment, the DPR logic 1030 may store the noise statistics as the portion of the image is complete and if the portion was part of the active region. FIG. 107 illustrates an example of the memory format for storing the noise statistics for each portion of the input image.

In one embodiment, the noise statistics logic 1031 may compute the horizontal/vertical/diagonal gradients using a filter convolution. For example, filter coefficients for a horizontal filter (h) may be set to [0.5 0-0.5], and the noise statistics logic 1031 may compute the horizontal gradient using a filter convolution and the filter coefficients. In another embodiment, the noise statistics logic 1031 may compute the horizontal gradient and vertical gradient for each pixel and then compute the orientation of the gradient using an arctangent function. For instance, theta=arctan (vertical_gradient/horizontal_gradient). Here, the noise statistics logic 1031 may bin the thetas for each pixel into the histogram.

After the noise statistics are stored in memory 100, various components may access the noise statistics to perform their respective operations. For instance, the noise statistics may be used to peform various operations including, for example, demosaicing operations, noise filtering operations, image sharpening operations, and the like. The noise statistics may be used to verify the accuracy of these operations, improve the effectiveness of these operations, and the like.

Spatial Noise Filter (SNF)

The output of the DPC logic may be passed to the spatial noise filter (SNF) logic 1032 for further processing. Thus, the discussion now turns to the SNF logic. As illustrated, in the present embodiment, the DPC logic is provided prior to the SNF logic 1032. This is because the initial temporal filtering process generally uses only co-located pixels (e.g., pixels from an adjacent frame in the temporal direction), and thus does not spatially spread noise and/or defects. However, spatial filtering filters the pixels in the spatial direction and, therefore, noise and/or defects present in the pixels may be spread spatially. Accordingly, defective pixel correction is applied prior to spatial filtering to reduce the spread of such defects.

In one embodiment, the SNF logic 1032 may be implemented as a two-dimensional spatial noise filter that is configured to support both a bilateral filtering mode and a non-local means filtering mode, both of which are discussed in further detail below. The SNF logic 1032 may process the raw pixels to reduce noise by averaging neighboring pixels that are similar in brightness. Referring first to the bilateral mode, this mode may be pixel adaptive based on a brightness difference between a current input pixel and its neighbors, such that when a pixel difference is high, filtering strength is reduced to avoid blurring edges. The SNF logic 1032 operates on raw pixels and may be implemented as a non-separable filter to perform a weighted average of local samples (e.g., neighboring pixels) that are close to a current input pixel both in space and intensity. For instance, in one embodiment, the SNF logic 1032 may include a 7×7 filter (with 49 filter taps) per color component to process a 7×7 block of same-colored pixels within a raw frame (e.g., 310 of FIG. 21), wherein the filter coefficients at each filter tap may adaptively change based upon the similarity (e.g., in brightness) of a pixel at the filter tap when compared to the current input pixel, which may be located at the center within the 7×7 block.

FIG. 108 shows a 7×7 block of same-colored pixels (P0-P48) on which spatial noise filtering may be applied by the SNF logic 1032, wherein the pixel designated by P24 may be the current input pixel at location (j,i) located at the center of the 7×7 block, and on which spatial filtering is being applied. For instance, assuming the raw image data is Bayer raw image data, all of the pixels in the 7×7 block may be of either red (R) pixels, green (either Gb or Gr) pixels, or blue (B) pixels. Further, while a 7×7 block is shown in the present embodiment, it should be appreciated that smaller or larger pixel block sizes may be used in conjunction with the presently disclosed techniques. For instance, in some embodiments, the SNF logic 1032 may include 9 filter taps and operate on a 3×3 block of same-colored pixels, 25 filter taps and operate on a 5×5 block of same-colored pixels, or may include 81 filter taps and operate on a 9×9 block of same-colored pixels.

To more clearly explain the spatial noise filtering process provided by the SNF logic 1032, a general description of the spatial noise filtering process will now be provided with reference to the process 1330 depicted in FIG. 109. The process 1330 is intended to provide an initial high level overview of the spatial noise filtering process, with more specific details of the spatial noise filtering process, including examples of equations and formulas that may be utilized in certain embodiments, being described further below.

The process 1330 begins at block 1334, at which a current input pixel P located at spatial location (j,i) is received, and a neighboring set of same-colored pixels for spatial noise filtering is identified. For example, a set of neighbor pixels may correspond to the 7×7 block 1328 and the input pixel may be the center pixel P24 of the 7×7 block, as shown above in FIG. 108. Next, at block 1334, filtering coefficients for each filter tap of the SNF logic 1032 are identified. In the present embodiment, each filter tap of the SNF logic 1032 may correspond to one of the pixels within the 7×7 block and may include a filtering coefficient. Thus, in the present example, a total of 49 filter coefficients may be provided. In certain embodiments, the SNF filtering coefficients may be derived based upon a Gaussian function with a standard deviation measured in pixels.

At block 1336, an absolute difference is determined between the input pixel P(j,i) and each of the neighbor pixels within the 7×7 block 1328. This value, delta (Δ) may then be used to determine an attenuation factor for each filter tap of the SNF logic 1032, as indicated by block 1338. As will be discussed further below, the attenuation factor for each neighbor pixel may depend on the brightness of the current input pixel P(j,i), the radial distance of the input pixel P(j,i) from the center of the raw frame 310 (FIG. 21), as well as the pixel difference between the input pixel P(j,i) and the neighbor pixel. Thereafter, at block 1340, the attenuation factors from block 1338 are applied to each respective filter tap of the SNF logic 1032 to obtain a set of attenuated filtering coefficients. At block 1342, each attenuated filtering coefficient is applied to its respective pixel within the 7×7 block. Finally, at block 1344, a spatially filtered output value O(j,i) that corresponds to the input pixel P(j,i) may be determined by normalizing the filter taps of the SNF logic 1032. In one embodiment, this may include dividing the sum of the filtered pixels from block 1342 by the sum of the attenuated filter coefficients from block 1340.

Having provided a general description of a spatial filtering process 1330 that may be performed by one embodiment of the SNF logic 1032, certain aspects of the process 1330 are now described in further detail. For instance with regard to block 1336 of the process 1330, the absolute difference values may be calculated when operating in the bilateral mode by determining the absolute difference between P(j,i) and each neighbor pixel. For instance, referring to FIG. 108, the absolute difference corresponding to pixel P0 may be the absolute value of (P0-P24), the absolute difference corresponding to pixel P1 may be the absolute value of (P1-P24), the absolute difference corresponding to pixel P2 may be the absolute value of (P2-P24), and so forth. Thus, an absolute difference value for each pixel within the 7×7 block 1328 may be determined in this manner to provide a total of 49 absolute difference values. Further, with regard to the 7×7 block 1328, if the current input pixel P(j,i) is located near an edge of the raw frame 310, such that there are not enough pixels in one or more directions to complete the 7×7 block, edge pixels of the current color component may be replicated. For instance, suppose a current input pixel is instead at location P31 in FIG. 108. In this scenario, an additional upper row of pixels may be needed to complete the 7×7 block, and this may be accomplished by replicating pixels P42-P48 in the y-direction.

The block 1338 of the process 1330 for determining an attenuation factor for each filter tap of the SNF logic 1032 is illustrated in more detail as a sub-process shown in FIG. 110 and including sub-blocks 1346-1354, in accordance with one embodiment. As shown in FIG. 110, the sub-process 1338 may be performed for each pixel of the 7×7 block and begins at sub-block 1346, where the parameters delta (Δ) (representing the absolute difference between the input pixel P and a current neighbor pixel), P (representing the value of the input pixel), and the coordinates j and i (representing the spatial location of the input pixel P) are received. At sub-block 1348, the value of the input pixel (P) may be evaluated against multiple brightness intervals to identify an interval in which the value P lies. By way of example only, one embodiment may provide a total of 18 brightness intervals (defined by 19 brightness levels), with 17 brightness levels spanning the range of 0 to 2^15 (2048 interval in 16-bit) in equal intervals and with the last two (18th and 19th brightness levels) being located at 2^15+2^14 and 2^16 (16384), respectively. For instance, a pixel P having a value of 13000 may fall in the interval defined between the 18th and 19th brightness levels. For the brightness lookup, negative pixel values are clipped to zero. As can be appreciated, such an embodiment may be employed when the raw pixel data received by the SNF logic 1032 includes 16-bit raw pixel data. If the received pixel data is less than 16-bits, it may be up-sampled, and if the received pixel data is greater than 16-bits, it may be down-sampled prior to being received by the SNF logic 1032. Further, in certain embodiments, the brightness levels and their corresponding brightness values may be stored using a look-up table.

In some embodiments, the low and high brightness values may be determined by the following logic:

for (i=0; i<16; i++)

{

if (p<2048*(i+1))

{

x0 = i; termine lower brightness level

x1 = i+1; //determine upper brightness level

x0_val = 2048*i

x1_val = 2048*(i+1)

}

}

// the last two intervals

if (p > 2{circumflex over ( )}15)

{

if (p <=2{circumflex over ( )}15 + 2{circumflex over ( )}14)

{

x0 = 16

x1 = 17

x0_val = 2{circumflex over ( )}15

x1_val = x0 + 2{circumflex over ( )}14

}

else

{

x0= 17

x1= 18

x0_val = 2{circumflex over ( )}15 + 2{circumflex over ( )}14

x1_val= 2{circumflex over ( )}16

}

}

Once the brightness interval corresponding to P is identified, the upper and lower levels of the selected brightness interval from sub-block 1348, as well as their corresponding brightness values, may be used to determine an inverse noise standard deviation value (e.g., 1/std_dev) for P, as shown at sub-block 1350. In one embodiment, an array of inverse noise standard deviation values may be provided, wherein a standard noise deviation value defined for each brightness level and color component. For instance, the inverse noise standard deviation values may be provided as an array, std_dev_inv[c] [brightness_level]:((0≦c≦3); (0≦brightness_level≦18)), wherein the first index element corresponds to a color components [c], which may correspond to four Bayer color components (R, Gb, Gr, B) in the present embodiment, and the second index element corresponds to one of the 19 brightness levels [brightness_level] provided in the present embodiment. Thus, in the present embodiment, a total of 19 brightness-based parameters for each of 4 color components (e.g., the R, Gb, Gr, and B components of Bayer raw pixel data) are provided. The inverse noise standard deviation values may be specified by firmware (e.g., executed by control logic 84).

Further, while the present embodiment depicts the determination of the brightness interval as being based upon a parameter equal to the value (P) of the current input pixel, in other embodiments, the parameter used to determine the brightness interval may be used on an average brightness of a subset of pixels within the 7×7 pixel block that are centered about the current input pixel. For instance, referring to FIG. 108, rather than determining the brightness interval using only the value of the current input pixel (P24), the average value (PAVG) of the pixels forming a 3×3 block centered at pixel P24 may be used (e.g., pixels P32, P31, P30, P25, P24, P23, P18, P17, and P16). Accordingly, the determination of the brightness interval and the corresponding upper and lower brightness levels may be based upon PAVG in such embodiments. As can be appreciated, the use of an averaged brightness (e.g., PAVG) may be more robust to noise compared to using only the value of the current input pixel (e.g., P24).

In certain embodiments, the std_dev_inv values may be specified using 22 bits, with a 6-bit signed exponent (Exp) and a 16-bit mantissa (Mant) as shown below:

std_dev_inv=Mant*(2^Exp);
wherein Exp has a range of −32<=Exp<=31 and wherein Mant has a range of 1.0<=Mant<2. Collectively, this may allow a range of:

Using the upper and lower brightness values from sub-block 1348, upper and lower inverse noise standard deviation values corresponding to P may be selected from the std_dev_inv array and interpolated to obtain an inverse noise standard deviation (std_dev_inv) value for P. For instance, in one embodiment, this process may be performed as follows:

std_dev_inv0 = snf_dev_inv[c][x0];

std_dev_inv1 = snf_dev_inv[c][x1];

x_interval = x1_val − x0_val;

std_dev_inv = [((std_dev_inv0 * (x1_val−P)) +

((std_dev_inv1 * (P−x0_val))] /

x_interval;

wherein std_dev_inv0 corresponds to the inverse noise standard deviation value of the lower brightness level, wherein std_dev_inv1 corresponds to the inverse noise standard deviation value of the upper brightness level, wherein x1_val and x0_val correspond to the brightness values of the upper and lower brightness levels, respectively, and wherein x_interval corresponds to the difference between the upper and lower brightness values. The value std_dev_inv represents the interpolation of std_dev_inv0 and std_dev_inv1.

Thereafter, at sub-block 1352, a radial gain is selected based upon the spatial location (e.g., radius) of the input pixel P relative to a center of the current image frame. For instance, referring to FIG. 111, a radial distance (R_val) 1358 may be determined as the distance between a center point of an image frame (e.g., raw frame 310) having the coordinates (snf_x0, snf_y0) and the current input pixel P with the coordinates (x, y). In one embodiment, the radial distance or radius, R_val, may be determined as follows:
R_val=√{square root over (((x−snf—x0)2+(y−snf—y0)2)}{square root over (((x−snf—x0)2+(y−snf—y0)2)}
Once the R_val is determined, a sub-process corresponding to block 1352, which is represented by blocks 1364-1372 of FIG. 112, may be performed to determine a radial gain to be applied to the inverse noise standard deviation value std_dev_inv determined at block 1350 of FIG. 110.

As shown in FIG. 112, the blocks 1364-1372 of the sub-process 1352 begins at sub-block 1364, wherein a radius (R_val) from the center (C) of the image frame to the position of the current input pixel (P) is determined. In one embodiment, this determination may be based upon Equation 1, provided above. Next, at sub-block 1366, the value of R_val may be evaluated against multiple radius intervals to identify an interval in which R_val is located. By way of example only, one embodiment may provide a total of 3 radius intervals, which may be defined by a first radius of 0 (e.g., located at the center (snf_x0, snf_y0) of the frame) and second, third, and fourth radius points. In one embodiment, the radius points, which may be defined by an array snf_rad[r]:(1≦r≦3), may be used as exponential components to calculate a radius. For example, the first radius point, snf_rad[1], may define a radius equal to 2^snf_rad[1]. Thus, the first radius interval may have a range from 0 to 2^snf_rad[1], the second radius interval may have a range from 2^snf_rad[1] to 2^snf_rad[2], and so forth.

Once a radius interval corresponding to R_val is identified, the upper radius point (R1) and lower radius point (R0) and their respective values may be determined, as shown at block 1368. In one embodiment, this process may be performed as follows:

R0_val =

0 if(R0==center); else 2{circumflex over ( )}snf_rad[R0];

R1_val =

2{circumflex over ( )}snf_rad[R1];

R_interval

= R1_val − R0_val;

wherein R0_val corresponds to radius value associated with the lower radius point, wherein R1_val corresponds to the radius value associated with the upper radius point, and wherein R interval represents the difference between R1_val and R0_val.

While the above-discussed embodiment provides three radius intervals using the image frame center and three additional radius points, it should be appreciated that any suitable number of radius intervals may be provided in other embodiments using more or fewer radius points. Further, the above-discussed embodiment provides radius points that begin from the center of the image frame and progress outwards towards the edge/corners of the image frame. However, because the radius points are used as exponential components (e.g., 2^snf_rad[r]), the range of the radius intervals may increase exponentially as they get farther away from the image center. In some embodiments, this may result in larger radius intervals closer to the edges and corners of the image frame, which may reduce the resolution at which radius points and radial gains may be defined. In one embodiment, if greater resolution is desired at the edges/corners of the image, rather than defining radius intervals and radius points as beginning from the center of an image frame, radius intervals and radius points may be defined beginning from a maximum radius, Rmax, and may progress inwards towards the center of the image frame. Thus, more radius intervals may be concentrated towards the edges of the image frame, thereby providing greater radial resolution and more radial gain parameters closer the edges. In a further embodiment, rather than using the radius points as exponential components for calculating radius intervals, multiple equally spaced intervals may be provided in higher concentration. For instance, in one embodiment, 32 radius intervals of equal ranges may be provided between the center of the image and a maximum radius (Rmax). Further, in certain embodiments, radius points and their defined intervals may be stored in a look-up table.

Referring still to FIG. 112, the upper and lower radius points may then be used to determine upper and lower radial gains, as depicted by sub-block 1368. As can be appreciated, the image frame may be subjected to intensity drop-offs that generally increase as the radial distance from center of the image frame increases. This may be due at least in part to the optical geometry of the lens (e.g., 88) of the image capture device 30. Accordingly, the radial gains may be set such that they generally increase for and the radius values farther away from the center. In one embodiment, the radial gains may have a range of from between approximately 0-4 and may be represented as 16-bit values with a 2-bit integer component and a 14-bit fraction component.

In one embodiment, the radial gains may be defined by an array snf_rad_gain[g]:(0<g<3), wherein radial gains corresponding to the upper and lower points may be determined as follows:

G0=snf_rad_gain[R0];

G1=snf_rad_gain[R1];
Thereafter, at sub-block 1370, the lower and upper radial gains, G0 and G1, may be interpolated using the below expression to determine an interpolated radial gain (G):

G=[((G0*(R1_val−R_val))+((G1*(R_val−R0_val))]/Rinterval;
The interpolated radial gain G may then be applied to inverse noise standard deviation value (std_dev_inv determined from block 1350 of FIG. 110), as shown at sub-block 1372, which may produce a gained inverse noise standard deviation value, referred to herein as std_dev_inv_gained. As will be appreciated, in certain embodiments, the radial gain values may be stored using a look-up table.

Then, returning to FIG. 110 and continuing to sub-block 1354, an attenuation function is used to determine an attenuation factor. In some embodiments, the attenuation function may be based upon a Gaussian function. For instance, since sensor noise (photon noise) is multiplicative, the variance of the noise increases with brightness. Accordingly, the attenuation function may depend on the brightness of the current input pixel, which is represented here by std_dev_inv_gained. Thus, the attenuation factor that is to be applied to the filter coefficient of the current neighbor pixel may be calculated using the gained inverse noise standard deviation value (std_dev_inv_gained) and the absolute difference (Δ) between the current pixel P and the current neighbor pixel. For instance, in one embodiment, the attenuation factor (Attn) at each filter tap may be determined using the following equation:
Attn=e(−0.5(delta2×std—dev—inv—gained2))
wherein delta represents the pixel difference between the current input pixel (P) and each neighbor pixel. For the current input pixel P at the center, the attenuation factor may be set to 1 (e.g., no attenuation is applied at the center tap of the 7×7 block).

As shown in the present embodiment, the attenuation factors for all taps of the SNF logic 1032 may be determined using the same gained standard deviation inverse value for all filter taps (e.g., std_dev_inv_gained), which is based on the radial distance between the center pixel and the center of the image frame. In further embodiments, separate respective standard deviation inverse values could also be determined for each filter taps. For instance, for each neighboring pixel, a radial distance between the neighboring pixel and the center of the image frame may be determined and, using the radial distance between the neighboring pixel and the center of the image frame (instead of the radial distance between the center pixel and the center of the image frame), a radial gain may be selected and applied to the standard deviation inverse value determined at block 1350 of FIG. 110 to determine a unique gained standard deviation inverse value for each filter tap.

As will be appreciated, the determination of an attenuation factor (Attn) may be performed for each filter tap of the SNF logic 1032 to obtain an attenuation factor, which may be applied to each filtering coefficient. Thus, assuming a 7×7 filter is used, as a result of block 1354, 49 attenuation factors may be determined, one for each filter tap of the 7×7 SNF logic 1032. Referring back to FIG. 109, particularly to block 1340 of the process 1330, the attenuation factors from block 1338 (as determined by sub-block 1354 of FIG. 110) may be applied to each filter tap of the SNF logic 1032 to obtain a resulting set of attenuated filtering coefficients.

As discussed above, each attenuated filtering coefficient is then applied to its respective pixel within the 7×7 block on which the SNF logic 1032 operates, as shown by block 1342 of process 1330. For normalization purposes, a sum (tap_sum) of all the attenuated filtering coefficients as well as a pixel sum (pix_sum) of all the filtered pixel values may be determined. For instance, at block 1344, a spatially filtered output value O(j,i) that corresponds to the input pixel P(j,i) may be determined by dividing the sum of the filtered pixels (pix_sum) by the sum of the attenuated filter coefficients (tap_sum). Thus, the process 1330 illustrated in FIG. 109 provides an embodiment which details how spatial noise filtering may be applied to one input pixel. As will be appreciated, to apply spatial noise filtering to an entire raw frame of pixel data, the process 1330 may be repeated for each pixel within a current raw frame using the spatial filtering techniques discussed above. In a further embodiment, the determination of attenuation factors for the SNF logic 1032 filter taps may be performed using values obtained from a set look-up tables with interpolation of table values. For instance, in one embodiment, attenuation values may be stored in a three-dimensional look-up table, referred to herein as snf_attn[c][α][delta], wherein [c] represents a color component index having a range of 0-3 (e.g., representing the four color components of Bayer raw data), x represents a pixel brightness index having a range of 0-4, and delta represents a pixel difference index having a range of 0-32. In such an embodiment, the table snf_attn may store attenuation values having a range from 0.0 to 1.0, with a 14-bit fraction. An array snf_attn_max[c][α] may define a maximum pixel difference per color component (0-3) for each pixel brightness (x). In one embodiment, when pixel differences are greater than 2^snf_attn_max, the attenuation factor may be set to 0.

The snf_attn table may store attenuation factors that cover the pixel difference range from 0 to 2^ [(snf_bright_thd)−1], where snf_bright_thd[c][thd] defines pixel brightness_level thresholds (thd=0-2) per component (c=0-3), with thresholds being represented as 2^snf_bright_thd[c][i]. As can be appreciated, this may represent the pixel thresholds for the snf_attn pixel brightness index. For example, the first threshold may be equal to 0, and the last threshold may be equal to 2^14−1, thus defining 4 intervals. The attenuation factors for each filter tap may be obtained by linear interpolation from the closest pixel brightness (x) and pixel differences values (delta).

Referring now to FIG. 113, a flow chart showing another embodiment of sub-process 1338 is illustrated in accordance with the above-described embodiment. The sub-process 1338 illustrated in FIG. 113 includes sub-blocks 1374-286, and depicts a process for using a look-up table based approach for interpolating attenuation values to obtain an attenuation values for a current filter tap. As shown the sub-process 1338 of FIG. 113 begins at sub-block 1374, where parameters corresponding to the value of the current input pixel (P) and the pixel difference (delta) between P and the neighbor pixel corresponding to the current filter tap. As discussed above, in one embodiment, rather than providing just the value of the current input pixel, the brightness value P could also be provided as an average of brightness values of the pixels in a 3×3 pixel block centered at the current input pixel.

Next, the sub-process 1338 continues to sub-blocks 1378 and 1380. At these sub-blocks, lower and upper pixel difference levels based each of the lower and upper brightness levels (x0 and x1) are determined. For instance, at sub-block 1378, lower and upper pixel difference levels (d0—0 and d1_x0) corresponding to the lower brightness level (x0) are determined, and at sub-block 1380, lower and upper pixel difference levels (d0_x1 and d1_x1) corresponding to the upper brightness level (x0) are determined. In one embodiment, the processes at sub-blocks 1378 and 1380 may be determined using the following logic:

Thereafter, sub-block 1378 may continue to sub-block 1382, and sub-block 1380 may continue to sub-block 1384. As shown in FIG. 113, at sub-blocks 1380 and 1384, first and second attenuation factors corresponding to the upper and lower brightness levels, respectively, may be determined using the table snf_attn and the delta levels determined at sub-blocks 1378 and 1380. For instance, in one embodiment, the determination of the first and second attenuation factors (attn0 and attn1) at sub-blocks 1382 and 1384 may be performed using the following logic:

//attn (first attenuation factor) corresponding to x0

attn0 = (snf_attn[c][x0][d0_x0] * (d1_x0*interval_x0 − delta) +

snf_attn[c][x0][d1_x0] * (delta − d0_x0*interval_x0))

>> shift_x0;

//attn (first attenuation factor) corresponding to x1

attn1 = (snf_attn[c][x1][d0_x1] * (d1_x1*interval_x1 − delta) +

snf_attn[c][x1][(d1_x1] * (delta − d0_x1*interval_x1))

>> shift_x1;

Thereafter, the first and second attenuation factors may be interpolated, as shown at sub-block 1386, to obtain a final attenuation factor (attn) that may be applied to the current filter tap. In one embodiment, the interpolation of the first and second attenuation factor may be accomplished using the following logic:

x0_value = 2{circumflex over ( )}snf_bright_thd[c][x0];

x1_value = 2{circumflex over ( )}snf_bright_thd[c][x1];

x_interval = x1_value − x0_value;

attn = (((attn0 * (x1_value − P))+((attn1 * (P − x0_value))) /

x_interval;

The sub-process 1338 may be repeated for each filter tap to obtain a corresponding attenuation factor. Once the attenuation factors for each filter tap have been determined, the sub-process 1338 may return to block 1350 of the process 1330 shown in FIG. 109, and the process 1330 may continue, as described above. As will be appreciated, the look-up table snf_attn may be programmed such that its attenuation values are modeled based upon a Gaussian distribution (e.g., a function similar to Equation 2 above). Further, while snf_attn is described as providing a range of attenuation values ranging from 0.0 to 1.0, in other embodiments, snf_attn may also provide values greater than 1.0 (e.g. from 0.0 to 4.0). Thus, if a factor greater than 1 is selected, this may implement image sharpening, where larger pixel differences (deltas) are amplified and/or increased.

The processes discussed above with respect to FIGS. 10-15 have been described in the context of a bilateral filtering mode that may be implemented by the SNF logic 1032 shown in FIG. 8. As mentioned above, in certain embodiments, the SNF logic 1032 may also be configured to operate in a non-local means filtering mode. The non-local means filtering mode may be performed in a similar manner as with the bilateral filtering mode, except that an absolute difference value between the current input pixel P(j,i) and each neighbor pixel within the 7×7 block (FIG. 108) is determined by taking the sum of absolute differences of a 3×3 window centered around the current pixel against a 3×3 window centered around each neighbor pixel, and then normalizing the result by the number of pixels (e.g., 9 pixels when a 3×3 window is used).

FIG. 114 shows an example of how pixel absolute difference values may be determined when the SNF logic 1032 operates in a non-local means mode in applying spatial noise filtering to the 7×7 block of pixels 1328 (originally depicted in FIG. 108). When determining an absolute pixel difference between the input pixel P24 and P0, a 3×3 window 1390 of pixels centered about P24 is compared to a 3×3 window 1392 of pixels centered about P0. Since P0 is located at the edge of the 7×7 block 1328, the 3×3 window is obtained by replicating edge pixels P7, P0, and P1. The replicated pixels are depicted here by reference number 1394.

The absolute difference value is then calculated by obtaining a sum of the absolute differences between each corresponding pixel in the windows 1390 and 1392, and normalizing the result by the total number of pixels in a window. For instance, when determining the absolute difference value between P24 and P0 in the non-local means mode, the absolute differences between each of P32 and P8, P31 and P7, P30 and P7, P25 and P1, P24 and P0, P23 and P0, P18 and P1, P17 and P0, and P16 and P0 are summed to obtain a total absolute difference between the windows 1390 and 1392. The total absolute difference value is then normalized by the number of pixels in a window, which may be done here by dividing the total absolute difference value by 9. Similarly, when determining the absolute difference value between P24 and P11, the 3×3 window 1390 and the 3×3 window 1396 (centered about P11) are compared, and the absolute difference between each of P32 and P19, P31 and P18, P30 and P17, P25 and P12, P24 and P11, P23 and P10, P18 and P5, P17 and P6, and P16 and P7 are summed to determine a total absolute difference between the windows 1390 and 1396, and then divided by 9 to obtain a normalized absolute difference value between P24 and P11. As can be appreciated, this process may then be repeated for each neighbor pixel within the 7×7 block 1328 by comparing the 3×3 window 1390 with 3×3 windows centered about every other neighbor pixel within the 7×7 block 1328, with edge pixels being replicated for neighbor pixels located at the edges of the 7×7 block.

The absolute pixel difference values calculated using this non-local means mode technique may similarly be used in the process 1330 of FIG. 109 to determine attenuation factors and radial gains for applying spatial noise filtering to the input pixel (e.g. P24). In other words, the non-local means mode of filtering is generally similar to the bilateral mode discussed above, with the exception that the pixel differences are calculated by comparing summed and normalized pixel differences using 3×3 windows centered around a neighbor pixel and the input pixel within the 7×7 block 1328 rather than simply taking the absolute difference between a single neighbor pixel and the input pixel. Additionally, the use of a 3×3 window in the present embodiment is only intended to provide one example of a non-local means filtering technique, and should not be construed as being limiting in this regard. Indeed, other embodiments, may utilize 5×5 windows within the 7×7 block, or 5×5 or 7×7 windows within a larger pixel block (e.g., 11×11 pixels, 13×13 pixels, etc.), for example.

In some embodiments, the selection of either the bilateral or non-local means filtering mode by the SNF logic 1032 may be determined by one or more parameters set by the control logic 84, such as by toggling a variable in software or by a value written to a hardware control register. The use of the non-local means filtering mode may offer some advantages in certain image conditions. For instance, the non-local means filtering made may exhibit increased robustness over the bilateral filtering mode by improving de-noising in flat fields while preserving edges. This may improve overall image sharpness. However, as shown above, the non-local means filtering mode may require that the SNF logic 1032 perform significantly more computations, including at least 10 additional processing steps for comparing each neighbor pixel to the current input pixel, including 8 additional pixel difference calculations for each 3×3 window (for each of the eight pixels surrounding the input pixel and the neighbor pixel), a calculation to determine the sum of the pixel absolute differences, and a calculation to normalize the pixel absolute difference total. Thus, for 48 neighbor pixels, this may result in at least 480 (48*10) processing steps. Thus, in instances where processing cycles, power, and/or resources are limited, the SNF logic 1032 may be configured to operate in the bilateral mode.

In the above-discussed embodiments, the SNF logic 1032 was described as operating as a two-dimensional filter. In a further embodiment, the SNF logic 1032 may also be configured to operate in a three-dimensional mode, which is illustrated in FIG. 115. In the three-dimensional mode, spatial noise filtering may be performed by further applying the spatial filtering process 1330 (FIG. 109) in the temporal direction. For instance, three-dimensional spatial filtering may include using a 7×7 block 1328 of neighbor pixels of a current frame of image data (at time t) to apply spatial filtering to a current input pixel (P24t) to obtain a first spatially filtered output value corresponding to the current input pixel. Spatial filtering may also be applied to the current input pixel (P24t) using co-located neighbor pixels from a 7×7 block 1400 in a previous frame of image data (at time t−1) to obtain a second spatially filtered output value corresponding to the current input pixel. The first and second spatially filtered values may be combined using weighted averaging to obtain a final spatially filtered output value corresponding to the current input pixel. As will be appreciated, three-dimensional spatial noise filtering may be performed using either the bilateral mode or the non-local means mode discussed above.

A process 1410 depicting an embodiment for three-dimensional spatial noise filtering is depicted in more detail in FIG. 116. For instance, the process 1410 begins at block 1412 and receives a current input pixel P from a current from at time t. Referring concurrently to FIG. 115, the current pixel P may correspond to P24t from the 7×7 block 1328. Next, at block 1414, a set of neighbor pixels in the current frame (time t) on which the SNF logic 1032 may operate is identified. This set of neighbor pixels may be represented by the 7×7 block 1328 from time t, as shown in FIG. 115. Additionally, at block 1416, which may occur concurrently with block 1414, a set of neighbor pixels in a previous frame from time t−1, which are co-located with the pixels of the 7×7 block 1328 at time t, are identified. This set of co-located neighbor pixels may be represented by the 7×7 block 1400 from time t−1, as shown in FIG. 115.

Next, at block 1418, filtering coefficients for each filter tap of the SNF logic 1032 are determined. In the depicted embodiment, the same filtering coefficients may be applied to the pixel data from time t and from time t−1. However, as discussed below, the attenuation factors applied to the filtering coefficients may vary between the pixels at time t and at time t−1 depending on differences in the absolute difference values between the input pixel (P24) and the neighbor pixels of the current frame (at time t) and the neighbor pixels of the previous frame (at time t−1). Referring now to blocks 1420-1428, these blocks generally represent the process 1330 discussed above in FIG. 109. For instance, at block 1420, absolute difference values between the current input pixel P at time t and the neighbor pixel within the 7×7 block 1328 of time t are determined. As will be appreciated, the absolute difference values may be determined using either of the bilateral or non-local means techniques described above. Using the absolute difference values from block 1420, a first set of attenuation factors corresponding to the pixels at time t are determined at block 1422. At block 1424, the first set of attenuation factors may then be applied to the filtering coefficients of the SNF logic 1032 to obtain a first set of attenuated filtering coefficients for the pixels at time t. Then, the first set of attenuated filtering coefficients is applied to the pixels from time t within the 7×7 block 1328, as indicated by block 1426. Thereafter, a spatially filtered value for the input pixel P based on the neighbor pixel values at time t is determined at block 1428. For example, as discussed above, obtaining the spatially filtered value may include normalizing the sum of the filtered pixels from block 1426 by the sum of the first set of attenuated filter coefficients determined at block 1424.

Blocks 1430-1438 may occur generally concurrently with blocks 1420-1428, and represent the spatial filtering process 1330 of FIG. 109 being applied to the input pixel P using the co-located neighbor pixels (e.g., within the 7×7 block 1400) from time t−1. That is, the spatial filtering process is essentially repeated in blocks 1430-1438 for the current input pixel P, but with respect to the neighbor pixels from time t−1 instead of the current pixels from time t. For example, at block 1430, absolute difference values between the current input pixel P at time t and the neighbor pixel within the 7×7 block 1400 of time t−1 are determined. Using the absolute difference values from block 1430, a second set of attenuation factors corresponding to the pixels at time t−1 are determined at block 1432. At block 1434, the second set of attenuation factors may then be applied to the filtering coefficients of the SNF logic 1032 to obtain a second set of attenuated filtering coefficients for the pixels at time t−1. Subsequently, the second set of attenuated filtering coefficients is applied to the pixels from time t−1 within the 7×7 block 1400, as indicated by block 1436. Thereafter, a spatially filtered value for the input pixel P based on the neighbor pixel values at time t−1 is determined at block 1438.

Once the spatially filtered values for P at time t and time t−1 are determined, they may be combined using weighted averaging, as depicted by block 1440. For instance, in one embodiment, the output of the SNF logic 1032 may simply be determined as the mean of the spatially filtered values at time t and time t−1 (e.g., equal weighting). In other embodiments, the current frame (time t) may be weighted more heavily. For instance, the output of the SNF logic 1032 may be determined as being 80 percent of the spatially filtered value from time t and 20 percent of the spatially filtered value from time t−1, or 60 percent of the spatially filtered value from time t and 40 percent of the spatially filtered value from time t−1, and so forth. In a further embodiments, three-dimensional spatial filtering may also utilize more than one previous frame. For instance, in the SNF logic 1032 could also apply the spatial filtering processing using the current pixel P with respect to co-located neighbor pixels from the frame at time t−1, as well as one or more additional previous image frames (e.g., at time t−2, time t−3, etc.). In such embodiments, weighted averaging may thus be performed on three or more spatially filtered values corresponding to different times. For instance, by way of example only, in one embodiment where the SNF logic 1032 operates on a current frame (time t) and two previous frames (time t−1 and time t−2), the weighting may be such that the spatially filtered value from time t is weighted 60 percent, the spatially filtered value from time t−1 is weighted 30 percent, and the spatially filtered value from time t−2 is weighted 10 percent.

In another embodiment, rather than simply averaging the spatially filtered values corresponding to times t and t−1, normalization may be performed on all filter taps from the current and previous image data. For instance, in an embodiment where a 7×7 block of pixels is evaluated at times t and t−1 (e.g., 49 taps at time t and 49 taps at time t−1 for a total of 98 taps), attenuation may be applied to all of the taps and the resulting filtered pixel values at both times t and t−1 may be summed and normalized by dividing the sum by the sum of the attenuated filter coefficients at both times t and t−1. As will be appreciated, in some embodiments, this technique may offer improved accuracy compared to techniques that use either an equal or weighted average by excluding pixel-to-pixel variations. Additionally, this technique may be useful in implementations where it is difficult to select an appropriate/ideal weighting parameter.

Additionally, it should be noted that the pixels from time t−1 may be selected as either the original (e.g., non-filtered) pixels of the previous frame, in which case the SNF logic 1032 operates as a non-recursive filter, or as the filtered pixels of the previous frame, in which case the SNF logic 1032 operates as a recursive filter. In one embodiment, the SNF logic 1032 may be capable of operating in both recursive and non-recursive modes, with the selection of the filtering mode being determined by control logic 84.

In some embodiments, the SNF logic 1032 may be initialized using a calibration procedure. In one embodiment, the calibration of the SNF logic 1032 may be based upon measured noise levels in the image sensor at different light levels. For instance, noise variance, which may be measured as part of the calibration of the image capture device(s) 30 (e.g., a camera) may be used by the control logic 84 (e.g., firmware) to determine spatial noise filter coefficients, as well as standard deviation values for spatial noise filtering.

Simple Demosaicing (DEM) for Highlight Recovery (HR)

Having described the operation and various processing techniques associated with the spatial noise filter logic 1032, the present discussion will now turn to a discussion of the processing that may occur between the signal noise filter logic and raw scaler logic. Namely, as illustrated in FIG. 117, a simple demosaicing process 1482, lens shading correction logic 1034, white balance gains logic 1036, and highlight recovery logic 1038 may be applied to the outputs from the spatial noise filter logic 1032. When the highlight recovery logic 1038 is disabled, these missing color samples are not needed, and the simple demosaicing process 1482 may simply return 0 values for the interpolated color channels 1486, passing only the known color values 1484. However, as will be discussed in more detail below, the simple demosaicing process 1482 may be an optional step, useful when the highlight recovery logic 1038 is enabled. Hence, the simple demosaicing process 1482 is illustrated as part of the highlight recovery logic 1038.

The simple demosaicing process 1482 may interpolate missing color samples (e.g., color channels) using bi-linear interpolation. For example, green-red, blue, and green-blue color channel values may be interpolated for a red pixel; red, blue and green-blue color channels may be interpolated for green-red pixels; green-red, red, and blue pixels may be interpolated for green-blue pixels; and green-red, green-blue, and red color channel values may be interpolated for blue pixels. To further illustrate the simple demosaicing process, FIG. 118 illustrates various combinations of pixels and the following formulas illustrate how the missing color samples may be interpolated from the combinations of pixels.

For Red on Green-red: R′11=(R10+R12)/2

For Red on Green-blue: R′11=(R01+R21)/2

For Red on Blue: R′11=(R00+R02+R20+R22)/4

For Blue on Green-red: B′11=(B01+B21)/2

For Blue on Green-blue: B′11=(B10+B12)/2

For Blue on Red: B′11=(B00+B02+B20+B22)/4

For Green-red on Red: Green-red′11=(G10+G12)/2

For Green-red on Blue: Green-red′11=G01+G21)/2

For Green-red on Green-blue: Green-red′11=(G00+G02+G 20+G22)/4

For Green-blue on red: Green-blue′11=(G01+G21)/2

For Green-blue on blue: Green-blue′11=(G10+G12)/2

For Green-blue on Green-red: Green-blue′11=(G00+G02+G20+G22)/4

Once the interpolated color values have been calculated, the values along with the pre-existing pixel values are provided to the lens shading correction logic 1034 for further processing.

Lens Shading Correction (LSC)

Referring again back to the block diagram shown in FIG. 117, the output of the simple demosaic logic 1482 is subsequently sent to the lens shading correction (LSC) logic 1034 for processing. As discussed above, lens shading correction techniques may include applying an appropriate gain on a per-pixel basis to compensate for drop-offs in light intensity, which may be the result of the geometric optics of the lens, imperfections in manufacturing, misalignment of the microlens array and the color array filter, and so forth. Further, the infrared (IR) filter in some lenses may cause the drop-off to be illuminant-dependent and, thus, lens shading gains may be adapted depending upon the light source detected.

In the depicted embodiment, the LSC logic 1034 of the ISP pipe 82 may be implemented in a similar manner, and thus provide generally the same functions, as the LSC logic 476 of the ISP pipe processing logic 80, as discussed above with reference to FIGS. 54-62. Accordingly, in order to avoid redundancy, it should be understood that the LSC logic 1034 of the presently illustrated embodiment is configured to operate in generally the same manner as the LSC logic 476 and, as such, the description of the lens shading correction techniques provided above will not be repeated here. However, to generally summarize, it should be understood that the LSC logic 1034 may process each color component of the raw pixel data stream independently to determine a gain to apply to the current pixel. In accordance with the above-discussed embodiments, the lens shading correction gain may be determined based upon a defined set of gain grid points distributed across the imaging frame, wherein the interval between each grid point is defined by a number of pixels (e.g., 8 pixels, 16 pixels etc.). If the location of the current pixel corresponds to a grid point, then the gain value associated with that grid point is applied to the current pixel. However, if the location of the current pixel is between grid points (e.g., G0, G1, G2, and G3 of FIG. 74), then the LSC gain value may be calculated by interpolation of the grid points between which the current pixel is located (Equations 13a and 13b). This process is depicted by the process 612 of FIG. 58. Further, as mentioned above with respect to FIG. 56, in some embodiments, the grid points may be distributed unevenly (e.g., logarithmically), such that the grid points are less concentrated in the center of the LSC region 588, but more concentrated towards the corners of the LSC region 588, typically where lens shading distortion is more noticeable.

Additionally, as discussed above with reference to FIGS. 61 and 62, the LSC logic 1034 may also apply a radial gain component with the grid gain values. The radial gain component may be determined based upon distance of the current pixel from the center of the image (Equations 14-16). As mentioned, using a radial gain allows for the use of single common gain grid for all color components, which may greatly reduce the total storage space required for storing separate gain grids for each color component. This reduction in grid gain data may decrease implementation costs, as grid gain data tables may account for a significant portion of memory or chip area in image processing hardware.

White Balance Gain (WBG)

The outputs from the lens shading correction logic 1034 may be sent to the white balancing gains (WBG) logic 1036. The WBG logic 1036 provides digital gains for white balance, offset, and clip independently for each of the color components (e.g., Gr, R,B, and Gb). The lens shading correction logic 1034 provides an input including each for the color components at each pixel where one component is the original Bayer pixel value 1484 and the other three components are demosaiced or interpolated pixel values 1486. The WBG logic 1036 applies white balance gains to all four components at each pixel. First, the input value is offselt by a signed value, multiplied by a gain in the range of 0 to 4×, offset by a second signed value and then clipped to a [min, max] range as follows:

Y[c]=((X[c]+O1[c])*G[c]+O2[c])

Y[c]=(Y[c]<min[c])?min[c]: Y[c]>max[c]: max[c]: Y[c]
where X[c] is the input pixel value (c=Gr, R, B, and Gb), O1[c] is a signed input offset for component c, G[c] is the gain value for component c, O2[c] is a signed output offset for component c, min[c] is a clip value for the minimum output values, and max[c] is a clip value for the maximum output values. The gains G[c] are 16-bit unsigned numbers with 14 fraction bits (e.g., a 2.14 representation). Gain may be applied with rounding.

The outputs from the WBG logic 1036 may include four components values at each pixel with a signed 17-bit representation. The number of pixels that were clipped above and below max and min for the component of the Bayer color of the pixel (e.g., the Gr components are counted for Gr pixels). These outputs of the WBG logic 1036 are provided to highlight recovery (HR) logic, which will now be discussed in detail.

Highlight Recovery (HR)

Image sensors have finite ranges of illuminance that may be captured. When the sensors for particular pixels receive an amount of light exceeding these finite ranges, the pixel values clip to the maximum pixel value. For example, with a 10-bit sensor, any illuminance larger than the one corresponding to the pixel value of 1023 is mapped to 1023 even though the brightness may be much higher. Previously, because the pixel values were limited by the sensor's range, some color information was lost because the pixel values were set to the maximum range values without compensating for values beyond the sensor's finite range. Thus, in many instances, the colors were incorrect since the clip level is different for each color channel and pixel location after white balancing and lens shading correction logic is applied. For example, a white cloud can appear as magenta if highlight recovery is not performed. In certain embodiments, when one color channel clips, ISP logic may clip each of the other color channels. However, such an embodiment may lead to an unnecessary loss of an effective dynamic range of pixel values.

The highlight recovery (HR) logic attempts to estimate pixel values that are clipped based upon the pixel values of other color channels that are not clipped. For example, when the green channel is clipped while the red and blue channels are not clipped, the highlight recovery logic may predict a value for the green channel using the unclipped values from the red and blue channels. Thus, as discussed above, the interpolated color channel values may be useful to aid in the highlight recovery pixel value estimations. While the examples described herein specifically discuss pixels arranged in a Bayer pattern (red, green-red, green-blue, and blue), other alternatives may be available. For example, color channels could each be treated separately, forming pixel color arrangements (e.g., red, green, blue, and white).

As illustrated in FIG. 117 and will be discussed in detail below, the highlight recovery logic 1038 may include clip level computations and pixel intensity normalization logic 1490. FIG. 119 illustrates the clip level computations and pixel intensity normalization logic 1490 in more detail. First, the green-red and green-blue color values are merged into one green value at each pixel (block 1512). For a green-red pixel, the green-red value is used. For a green-blue pixel, the green-blue value is used. For a red or blue pixel, the green-red and green-blue pixel values are averaged (e.g., (Green-blue+Green-red)/2). Next, at block 1514, the clip levels for the pixels are computed. The clip level is computed from the maximum value of the sensor and the gains applied in the lens shading correction logic 1034. The clip level computations may be calculated solely for the color component related to the pixel. For example, for a red pixel, the red clip level is computed. The clip levels may be determined as follows:
The clip level of the red pixels=Maximum sensor level for the red pixels*Lens shading gain applied to the red pixel+a programmable offset to the red clip levels.
The clip level of the green-red pixels=Maximum sensor level for the green-red pixels*Lens shading gain applied to the green-red pixels+a programmable offset to the green-red clip levels.
The clip level of the green-blue pixels=Maximum sensor level for the green-blue pixels*Lens shading gain applied to the green-blue pixels+a programmable offset to the green-blue clip levels.
The clip level of the blue pixels=Maximum sensor level for the blue pixels*Lens shading gain appled to the blue pixels+a programmable offset to the blue clip levels.

Because the lens shading gains were computed by the LSC logic 1034, they do not need to be recalculated for highlight recovery. Instead, these gains are merely provided by the LSC logic 1034 to the highlight recovery logic 1038.

The calculated clip values may be represented by 17 bits of data. The pixel values may be normalized by these clip values of the pixel color (block 1516). Specifically, the color channel pixel values of a pixel (e.g., the red, green′, and blue values) may be divided by the clip level associated with the Bayer color of the pixel. For example, the denominator for normalizing a red pixel would be the clip level of the red pixel. As discussed above, the green pixel values have been merged, and thus only three normalization values may need to be calculated for each pixel. In one example, the following formulas may be useful in normalizing the pixel values of a red pixel:

Once the normalized pixel intensity normalization values are calculated, they may be provided to the appropriate 3-d color lookup table 1492 (CLUT) to obtain the predicted highlight recovery logic values for the pixel. FIG. 120 illustrates a process 1550 for using the normalization values to obtain the appropriate highlight recovery values. First, the normalized values are provided to the appropriate CLUT 1492 (block 1552). In certain embodiments, there may be three CLUTs 1492 useful for the highlight recovery logic 1038. Each of the CLUTs 1492 may be associated with a particular color channel (e.g., Red, Green, or Blue).

The CLUTs 1492 may take in the pixel intensity normalization values for a pixel and output “recovered” normalized values that most closely relate to the normalized values (block 1554). The recovered normalized values may be derived from computer algorithms based upon any number of parameters. For example, the algorithms for determining the normalized values stored in the CLUTs 1492 may include preferred white balance settings, a time of day (e.g., sunset vs. noon, which may have different significance), and/or a subject of the captured image (e.g., a blue sky vs. a sunset). The CLUTs 1492 may include indices based upon the normalized color channel values where there are three equally spaced entries for the corresponding color of the CLUT 1492 and nine equally spaced entries for the colors not corresponding to the CLUT. For example, the red CLUT, represented by RLUT below, is indexed based upon normalized red, green, and blue values. The red CLUT may include three equally spaced red entries defined by the red minimum and maximum values, R min and R max, respectively. The green and blue indices may include nine equally spaced indices defined by the green and blue minimum and maximum values (minG_R, maxG_R, minB_R, and maxB_R). Further, the green CLUT may include three equally spaced green entries defined by the green minimum and maximum values, G min and G max, respectively. The red and blue indices may include nine equally spaced indices defined by the red and blue minimum and maximum values (minR_G, maxR_G, minB_G, and maxB_G). Additionally, the blue CLUT may include three equally spaced blue entries defined by the blue minimum and maximum values, B min and B max, respectively. The red and green indices may include nine equally spaced indices defined by the red and green minimum and maximum values (minR_B, maxR_B, minG_B, and maxG_B).

As discussed above, the CLUTs may provide the closest output value based upon the 3×9×9 entries. However, this value may be linearly interpolated (block 1556), thus providing a more accurate recovery value. The linearly interpolated output, in some embodiments, may be represented by 14 fractional bits. To obtain the linear interpolation, one or more divide procedures may be implemented. However, because the minimum and maximum values are constant for a given frame, in some embodiments, software may program a reciprocal value for the differences between the maximum and minimum values, thus avoiding the divide (e.g., through multiplication of the reciprocal).

In alternative embodiments, the CLUTs used to determine the recovery values may not be 3-d, but instead, 4-d, 5-d, 6-d, etc. For example, in some embodiments, the green-blue and green-red values may not be merged as discussed in block 1512 of FIG. 119. Instead, the blue-green and blue-red values may be passed to the highlight recovery logic 1038. In such embodiments, the CLUTs may be 4-d CLUTs indexed by the four color pixel values (red, green-red, green-blue, and blue). Such embodiments may provide increased color accuracy, however, may be more expensive (e.g., use more storage) than 3-d CLUTs. Further, as discussed above, in embodiments that do not conform to a Bayer pattern (e.g., red, green, blue, and white pixel arrangements), 4-d CLUTs may be indexed by the individual color channels (red, green, blue, and white). In alternative embodiments, the 4-d CLUTs may be indexed by red, green, and blue values as well as a threshold value. In another alternative, in some embodiments, the CLUTs may be 5-d or 6-d. For example, a 5-d CLUT may be indexed based upon color pixel values (red, green, and blue) as well as coordinates for a particular pixel (e.g., X-coordinates and Y-coordinates). In 6-d CLUT embodiments, the CLUTs may be indexed based upon the color pixel values (red, green, and blue) as well as ceiling levels, or clip values, of the red, green, and blue color channels.

Once the normalized recovery value is determined, a final recovery value may be determined by multiplying the normalized recovery value by the clip level for the pixel discussed above. The final recovery value may be higher than the sensor clipping value. The only CLUT that may need to be accessed by highlight recovery for an individual pixel is the CLUT associated with Bayer color of the pixel. For example, a red pixel would access the red CLUT, a green-red pixel would access the green CLUT, and so forth. To further illustrate the portions of the process 1550, an example is provided. In the provided example, the final recovery value for a red pixel may be calculated as follows:

If R_norm < minR_R

R_HR = R;

else

{

G_norm′ = min (maxG_R,max(minG_R, G_norm′));

B_norm′= min (maxB_R, max(minB_R, B_norm′));

R_HR = interp3 (

RLUT

R_norm, minR_R, maxR_R, RecipR_R

G_norm′, minG_R, maxG_R, RecipG_R

B_norm′, minB_R, maxB_R, RecipB_R

) * Cliplevel_R;

}

Interp3 may represent the computation of the output values via tri-linear interpolation based on the normalized pixel values (represented by R_norm, G_norm′, and B_norm′). RLUT represents the red CLUT that takes in normalized RGB triplet values and returns the closet output value based upon the 3×9×9 entries in the red CLUT. Cliplevel_R represents the calculated clip level for the red pixels, as discussed above.

Once the final recovery value is determined, post-processing may occur (block 1560). The post-processing logic may ensure that the final recovery value is not higher than the maximum value at the pixel, thus preventing excessive gains from being applied to the pixel. For example, for a red pixel, the pixel may be limited by a maximum threshold maxRGB_R. The post-processing logic may ensure that the final highlight recovery value of the pixel will not exceed this maximum threshold. In instances where the highlight recovery value of the pixel would exceed the maximum threshold, the highlight recovery value may be set to the maximum threshold. When the highlight recovery value does not exceed the maximum threshold, the highlight recovery value is set to the final recovery value. Once post-processing is complete, the highlight recovery logic 1038 may replace the value of clipped pixels with the highlight recovery value (block 1562), thereby applying the highlight recovery values for clipped pixels. Note that while in some embodiments the highlight recovery value may be representative of a replacement value for a clipped pixel value, in alternative embodiments, the highlight recovery logic may determine gains to be applied or added to the clipped pixel values rather than replacing the clipped pixel values.

Raw Scaler (RSCL)

The outputs of the highlight recovery logic 1038 may be passed to the raw scaler logic 1040. The raw scaler logic 1040 performs down-scaling in the RAW domain. Further, this logic may be used as a binning compensation filter, which may be configured to process the image pixels to compensate for non-linear placement (e.g., uneven spatial distribution) of the color samples due to binning by the image sensor(s) 90, such that subsequent image processing operations in the ISP pipe logic 82 (e.g., demosaicing, etc.) that depend on linear placement of the color samples can operate correctly. For example, referring now to FIG. 121, a full resolution sample 1693 of Bayer image data is depicted. This may represent a full resolution sample raw image data captured by the image sensor(s) 90.

As will be appreciated, under certain image capture conditions, it may be not be practical to send the full resolution image data captured by the image sensor 90a to the ISP circuitry 32 for processing. For instance, when capturing video data, in order to preserve the appearance of a fluid moving image from the perspective of the human eye, a frame rate of at least approximately 30 frames per second may be desired. However, if the amount of pixel data contained in each frame of a full resolution sample exceeds the processing capabilities of the ISP circuitry 32 when sampled at 30 frames per second, binning compensation filtering may be applied in conjunction with binning by the image sensor 90a to reduce the resolution of the image signal while also improving signal-to-noise ratio. For instance, various binning techniques, such as 2×2 binning, may be applied to produce a “binned” raw image pixel by averaging the values of surrounding pixels in the active region 312 of the raw frame 310.

Raw scaler logic 1040 may be configured to apply binning to the full resolution raw image data to produce the binned raw image data, which may be provided to the ISP front-end processing logic 80 using the sensor interface 94a which, as discussed above, may be an SMIA interface or any other suitable parallel or serial camera interfaces. Further, the raw scaler logic 1040 may correct chromatic aberrations in the capture raw image data.

As illustrated in FIG. 122, the raw scaler logic 1040 may apply 2×2 binning to the full resolution raw image data. For example, with regard to the binned image data 700, the pixels 1695, 1696, 1697, and 1698 may form a Bayer pattern and may be determined by averaging the values of the pixels from the full resolution raw image data. For instance, referring to both FIGS. 121 and 122, the binned Gr pixel 1695 may be determined as the average or mean of the full resolution Gr pixels 1695a-1695d. Similarly, the binned R pixel 1696 may be determined as the average of the full resolution R pixels 1696a-1695d, the binned B pixel 1697 may be determined as the average of the full resolution B pixels 1697a-1697d, and the binned Gb pixel 1698 may be determined as the average of the full resolution Gb pixels 1698a-1698d. Thus, in the present embodiment, 2×2 binning may provide a set of four full resolution pixels including an upper left (e.g., 1695a), upper right (e.g., 1695b), lower left (e.g., 1695c), and lower right (e.g., 1695d) pixel that are averaged to derive a binned pixel located at the center of a square formed by the set of four full resolution pixels. Accordingly, the binned Bayer block 1694 shown in FIG. 122 contains four “superpixels” that represent the 16 pixels contained in the Bayer blocks 1694a-1694d of FIG. 121.

In addition to reducing spatial resolution, binning also offers the added advantage of reducing noise in the image signal. For instance, whenever an image sensor (e.g., 90a) is exposed to a light signal, there may be a certain amount of noise, such as photon noise, associated with the image. This noise may be random or systematic and it also may come from multiple sources. Thus, the amount of information contained in an image captured by the image sensor may be expressed in terms of a signal-to-noise ratio. For example, every time an image is captured by an image sensor 90a and transferred to a processing circuit, such as the ISP circuitry 32, there may be some degree of noise in the pixels values because the process of reading and transferring the image data inherently introduces “read noise” into the image signal. This “read noise” may be random and is generally unavoidable. By using the average of four pixels, noise, (e.g., photon noise) may generally be reduced irrespective of the source of the noise.

Thus, when considering the full resolution image data 1693 of FIG. 28, each Bayer pattern (2×2 block) 1694a-1694d contains 4 pixels, each of which contains a signal and noise component. If each pixel in, for example, the Bayer block 1694a, is read separately, then four signal components and four noise components are present. However, by applying binning, as shown in FIGS. 121 and 122, such that four pixels (e.g., 1695a, 1695b, 1695c, 1695d) may be represented by a single pixel (e.g., 1695) in the binned image data, the same area occupied by the four pixels in the full resolution image data 1693 may be read as a single pixel with only one instance of a noise component, thus improving signal-to-noise ratio.

Further, while the present embodiment depicts the raw scaler logic 1040 as being configured to apply a 2×2 binning process, it should be appreciated that the raw scaler logic 1040 may be configured to apply any suitable type of binning process, such as 3×3 binning, vertical binning, horizontal binning, and so forth. In some embodiments, the image sensor 90a may be configured to select between different binning modes during the image capture process. Additionally, in further embodiments, the image sensor 90a may also be configured to apply a technique that may be referred to as “skipping,” wherein instead of average pixel samples, the raw scaler logic 1040 selects only certain pixels from the full resolution data 1693 (e.g., every other pixel, every 3 pixels, etc.) to output to the ISP front-end 80 for processing.

As also depicted in FIG. 122, one effect of the binning process is that the spatial sampling of the binned pixels may not be equally spaced. This spatial distortion may, in some systems, result in aliasing (e.g., jagged edges), which is generally not desirable. Further, because certain image processing steps in the ISP pipe logic 82 may depend upon on the linear placement of the color samples in order to operate correctly, the raw scaler logic 1040 may be applied to perform re-sampling and re-positioning of the binned pixels such that the binned pixels are spatially evenly distributed. That is, the raw scaler logic 1040 essentially compensates for the uneven spatial distribution (e.g., shown in FIG. 122) by re-sampling the position of the samples (e.g., pixels). For instance, FIG. 123 illustrates a re-sampled portion of binned image data 360 after being processed by the raw scaler circuitry 1652, wherein the Bayer block 1703 containing the evenly distributed re-sampled pixels 1704, 1705, 1706, and 1707 correspond to the binned pixels 1695, 1696, 1697, and 1698, respectively, of the binned image data 1700 from FIG. 122. Additionally, in an embodiment that utilizes skipping (e.g., instead of binning), as mentioned above, the spatial distortion shown in FIG. 122 may not be present. In this case, the raw scaler circuitry 1652 may function as a low pass filter to reduce artifacts (e.g., aliasing) that may result when skipping is employed by the image sensor 90a.

FIG. 124 shows a block diagram of the raw scaler circuitry 1652 in accordance with one embodiment. The raw scaler circuitry 1652 may include binning compensation logic 1708 and chromatic aberration correction logic 1737. The binning compensation logic 1708 may process binned pixels 1700 to apply horizontal and vertical scaling using horizontal scaling logic 1709 and vertical scaling logic 1710, respectively, to re-sample and re-position the binned pixels 1700 so that they are arranged in a spatially even distribution, as shown in FIG. 123. In one embodiment, the scaling operation(s) performed by the raw scaler circuitry 1652 may be performed using horizontal and vertical multi-tap polyphase filtering. For instance, the filtering process may include selecting the appropriate pixels from the input source image data (e.g., the binned image data 1700 provided by the image sensor 90a), multiplying each of the selected pixels by a filtering coefficient, and summing up the resulting values to form an output pixel at a desired destination.

The selection of the pixels used in the scaling operations, which may include a center pixel and surrounding neighbor pixels of the same color, may be determined using separate differential analyzers 1711, one for vertical scaling and one for horizontal scaling. In the depicted embodiment, the differential analyzers 1711 may be digital differential analyzers (DDAs) and may be configured to control the current output pixel position during the scaling operations in the vertical and horizontal directions. In the present embodiment, a first DDA (referred to as 1711a) is used for all color components during horizontal scaling, and a second DDA (referred to as 1711b) is used for all color components during vertical scaling. By way of example only, the DDA 1711 may be provided as a 32-bit data register that contains a 2's-complement fixed-point number having 16 bits in the integer portion and 16 bits in the fraction. The 16-bit integer portion may be used to determine the current position for an output pixel. The fractional portion of the DDA 1711 may be used to determine a current index or phase, which may be based the between-pixel fractional position of the current DDA position (e.g., corresponding to the spatial location of the output pixel). The index or phase may be used to select an appropriate set of coefficients from a set of filter coefficient tables 1712. Additionally, the filtering may be done per color component using same colored pixels. Thus, the filtering coefficients may be selected based not only on the phase of the current DDA position, but also the color of the current pixel. In one embodiment, 8 phases may be present between each input pixel and, thus, the vertical and horizontal scaling components may utilize 8-deep coefficient tables, such that the high-order 3 bits of the 16-bit fraction portion are used to express the current phase or index. Thus, as used herein, the term “raw image” data or the like shall be understood to refer to multi-color image data that is acquired by a single sensor with a color filter array pattern (e.g., Bayer) overlaying it, those providing multiple color components in one plane. In another embodiment, separate DDAs may be used for each color component. For instance, in such embodiments, the raw scaler circuitry 1652 may extract the R, B, Gr, and Gb components from the raw image data and process each component as a separate plane.

In operation, horizontal and vertical scaling may include initializing the DDA 1711 and performing the multi-tap polyphase filtering using the integer and fractional portions of the DDA 1711. While performed separately and with separate DDAs, the horizontal and vertical scaling operations are carried out in a similar manner. A step value or step size (DDAStepX for horizontal scaling and DDAStepY for vertical scaling) determines how much the DDA value (currDDA) is incremented after each output pixel is determined, and multi-tap polyphase filtering is repeated using the next currDDA value. For instance, if the step value is less than 1, then the image is up-scaled, and if the step value is greater than 1, the image is downscaled. If the step value is equal to 1, then no scaling occurs. Further, it should be noted that same or different step sizes may be used for horizontal and vertical scaling.

Output pixels are generated by the raw scaler circuitry 1652 in the same order as input pixels (e.g., using the Bayer pattern). In the present embodiment, the input pixels may be classified as being even or odd based on their ordering. For instance, referring to FIG. 125, a graphical depiction of input pixel locations (row 1713) and corresponding output pixel locations based on various DDAStep values (rows 1714-1718) are illustrated. In this example, the depicted row represents a row of red (R) and green (Gr) pixels in the raw Bayer image data. For horizontal filtering purposes, the red pixel at position 0.0 in the row 1713 may be considered an even pixel, the green pixel at position 1.0 in the row 1713 may be considered an odd pixel, and so forth. For the output pixel locations, even and odd pixels may be determined based on the least significant bit in the fraction portion (lower 16 bits) of the DDA 1711. For instance, assuming a DDAStep of 1.25, as shown in row 1715, the least significant bit corresponds to the bit 14 of the DDA, as this bit gives a resolution of 0.25. Thus, the red output pixel at the DDA position (currDDA) 0.0 may be considered an even pixel (the least significant bit, bit 14, is 0), the green output pixel at currDDA 1.0 (bit 14 is 1), and so forth. Further, while FIG. 125 is discussed with respect to filtering in the horizontal direction (using DDAStepX), it should be understood that the determination of even and odd input and output pixels may be applied in the same manner with respect to vertical filtering (using DDAStepY). In other embodiments, the DDAs 1711 may also be used to track locations of the input pixels (e.g., rather than track the desired output pixel locations). Further, it should be appreciated that DDAStepX and DDAStepY may be set to the same or different values. Further, assuming a Bayer pattern is used, it should be noted that the starting pixel used by the raw scaler circuitry 1652 could be any one of a Gr, Gb, R, or B pixel depending, for instance, on which pixel is located at a corner within the active region 312.

With this in mind, the even/odd input pixels are used to generate the even/odd output pixels, respectively. Given an output pixel location alternating between even and odd position, a center source input pixel location (referred to herein as “currPixel”) for filtering purposes is determined by the rounding the DDA to the closest even or odd input pixel location for even or odd output pixel locations (based on DDAStepX), respectively. In an embodiment where the DDA 1711a is configured to use 16 bits to represent an integer and 16 bits to represent a fraction, currPixel may be determined for even and odd currDDA positions using Equations 6a and 6b below:

Even output pixel locations may be determined based on bits [31:16] of:
(currDDA+1.0)&0xFFFE.0000

Odd output pixel locations may be determined based on bits [31:16] of:
(currDDA)|0x0001.0000 (6b)
Essentially, the above equations present a rounding operation, whereby the even and odd output pixel positions, as determined by currDDA, are rounded to the nearest even and odd input pixel positions, respectively, for the selection of currPixel.

Additionally, a current index or phase (currIndex) may also be determined at each currDDA position. As discussed above, the index or phase values represent the fractional between-pixel position of the output pixel position relative to the input pixel positions. For instance, in one embodiment, 8 phases may be defined between each input pixel position. For instance, referring again to FIG. 125, 8 index values 0-7 are provided between the first red input pixel at position 0.0 and the next red input pixel at position 2.0. Similarly, 8 index values 0-7 are provided between the first green input pixel at position 1.0 and the next green input pixel at position 3.0. In one embodiment, the currIndex values may be determined in accordance with Equations 7a and 7b below for even and odd output pixel locations, respectively:

Even output pixel locations may be determined based on bits [16:14] of:
(currDDA+0.125)

Odd output pixel locations may be determined based on bits [16:14] of:
(currDDA+1.125)
For the odd positions, the additional 1 pixel shift is equivalent to adding an offset of four to the coefficient index for odd output pixel locations to account for the index offset between different color components with respect to the DDA 1711.

Once currPixel and currIndex have been determined at a particular currDDA location, the filtering process may select one or more neighboring same-colored pixels based on currPixel (the selected center input pixel). By way of example, in an embodiment where the horizontal scaling logic 368 includes a 5-tap polyphase filter and the vertical scaling logic 1710 includes a 3-tap polyphase filter, two same-colored pixels on each side of currPixel in the horizontal direction may be selected for horizontal filtering (e.g., −2, −1, 0, +1, +2), and one same-colored pixel on each side of currPixel in the vertical direction may be selected for vertical filtering (e.g., −1, 0, +1). Further, currIndex may be used as a selection index to select the appropriate filtering coefficients from the filter coefficients table 1712 to apply to the selected pixels. For instance, using the 5-tap horizontal/3-tap vertical filtering embodiment, five 8-deep tables may be provided for horizontal filtering, and three 8-deep tables may be provided for vertical filtering. Though illustrated as part of the raw scaler circuitry 1652, it should be appreciated that the filter coefficient tables 1712 may, in certain embodiments, be stored in a memory that is physically separate from the raw scaler circuitry 1652, such as the memory 108.

Before discussing the horizontal and vertical scaling operations in further detail, Table 6 below shows examples of how currPixel and currIndex values, as determined based on various DDA positions using different DDAStep values (e.g., could apply to DDAStepX or DDAStepY).

To provide an example, let us assume that a DDA step size (DDAStep) of 1.5 is selected (row 1716 of FIG. 125), with the current DDA position (currDDA) beginning at 0, indicating an even output pixel position. To determine currPixel, the following equation may be applied, as shown below:

currDDA=0.0⁢⁢(even)0000⁢⁢0000⁢⁢0000⁢⁢0001.0000⁢⁢0000⁢⁢0000⁢⁢0000(currDDA+1.0)(AND)1111⁢⁢1111⁢⁢1111⁢⁢1110.0000⁢⁢0000⁢⁢0000⁢⁢0000(0×FFFE⁢.0000)=0000⁢⁢0000⁢⁢0000⁢⁢0000_⁢.0000⁢⁢0000⁢⁢0000⁢⁢0000currPixel⁢⁢(determined⁢⁢as⁢⁢bits⁢[31⁢:⁢16]⁢⁢of⁢⁢the⁢⁢result)=0;
Thus, at the currDDA position 0.0 (row 1716), the source input center pixel for filtering corresponds to the red input pixel at position 0.0 of row 1713.

To determine currIndex at the even currDDA 0.0, the following equation may be applied, as shown below:

currDDA=0.0⁢⁢(even)0000⁢⁢0000⁢⁢0000⁢⁢0000.0000⁢⁢0000⁢⁢0000⁢⁢0000(currDDA)+0000⁢⁢0000⁢⁢0000⁢⁢0000⁢⁢.0010⁢⁢0000⁢⁢0000⁢⁢0000(0.125)=0000⁢⁢0000⁢⁢0000⁢⁢000⁢0.00_⁢10⁢⁢0000⁢⁢0000⁢⁢0000currIndex⁢⁢(determined⁢⁢as⁢⁢bits⁢[16⁢:⁢14]⁢⁢of⁢⁢the⁢⁢result)=[000]=0;
Thus, at the currDDA position 0.0 (row 1716), a currIndex value of 0 may be used to select filtering coefficients from the filter coefficients table 1712.

Accordingly, filtering (which may be vertical or horizontal depending on whether DDAStep is in the X (horizontal) or Y (vertical) direction) may applied based on the determined currPixel and currIndex values at currDDA 0.0, and the DDA 1711 is incremented by DDAStep (1.5), and the next currPixel and currIndex values are determined. For instance, at the next currDDA position 1.5 (an odd position), currPixel may be determined using Equation 6b as follows:

currDDA=0.0⁢⁢(odd)0000⁢⁢0000⁢⁢0000⁢⁢0001.1000⁢⁢0000⁢⁢0000⁢⁢0000(curr⁢⁢DDA)(OR)0000⁢⁢0000⁢⁢0000⁢⁢0001.0000⁢⁢0000⁢⁢0000⁢⁢0000(0×0001.000)=0000⁢⁢0000⁢⁢0000⁢⁢00001_⁢.1000⁢⁢0000⁢⁢0000⁢⁢0000currPixel⁢⁢(determined⁢⁢as⁢⁢bits⁢[31⁢:⁢16]⁢⁢of⁢⁢the⁢⁢results)=1;
Thus, at the currDDA position 1.5 (row 1716), the source input center pixel for filtering corresponds to the green input pixel at position 1.0 of row 1713.

Further, currIndex at the odd currDDA 1.5 may be determined using Equation 7b, as shown below:

currDDA=1.5⁢⁢(odd)0000⁢⁢0000⁢⁢0000⁢⁢0000.1000⁢⁢0000⁢⁢0000⁢⁢0000(currDDA)+0000⁢⁢0000⁢⁢0000⁢⁢0000⁢⁢.0010⁢⁢0000⁢⁢0000⁢⁢0000(1.125)=0000⁢⁢0000⁢⁢0000⁢⁢000⁢0.10_⁢10⁢⁢0000⁢⁢0000⁢⁢0000currIndex⁢⁢(determined⁢⁢as⁢⁢bits⁢[16⁢:⁢14]⁢⁢of⁢⁢the⁢⁢result)=[010]=2;
Thus, at the currDDA position 1.5 (row 1716), a currIndex value of 2 may be used to select the appropriate filtering coefficients from the filter coefficients table 1712. Filtering (which may be vertical or horizontal depending on whether DDAStep is in the X (horizontal) or Y (vertical) direction) may thus be applied using these currPixel and currIndex values.

Next, the DDA 1711 is incremented again by DDAStep (1.5), resulting in a currDDA value of 3.0. The currPixel corresponding to currDDA 3.0 may be determined using Equation 6a, as shown below:

currDDA=3.0⁢⁢(even)0000⁢⁢0000⁢⁢0000⁢⁢0100.0000⁢⁢0000⁢⁢0000⁢⁢0000(currDDA+1.0)(AND)1111⁢⁢1111⁢⁢1111⁢⁢1110.0000⁢⁢0000⁢⁢0000⁢⁢0000(0×FFFE⁢.0000)=0000⁢⁢0000⁢⁢0000⁢⁢0100_⁢.0000⁢⁢0000⁢⁢0000⁢⁢0000currPixel⁢⁢(determined⁢⁢as⁢⁢bits⁢[31⁢:⁢16]⁢⁢of⁢⁢the⁢⁢result)=4;
Thus, at the currDDA position 3.0 (row 1716), the source input center pixel for filtering corresponds to the red input pixel at position 4.0 of row 1713.

Next, currIndex at the even currDDA 3.0 may be determined using the following equation, as shown below:

currDDA=3.0⁢⁢(even)0000⁢⁢0000⁢⁢0000⁢⁢0011.000⁢⁢0⁢⁢0000⁢⁢0000⁢⁢0000(currDDA)+0000⁢⁢0000⁢⁢0000⁢⁢0000⁢⁢.0010⁢⁢0000⁢⁢0000⁢⁢0000(0.125)=0000⁢⁢0000⁢⁢0000⁢⁢001⁢1.0⁢0_⁢10⁢⁢0000⁢⁢0000⁢⁢0000currIndex⁢⁢(determined⁢⁢as⁢⁢bits⁢[16⁢:⁢14]⁢⁢of⁢⁢the⁢⁢result)=[100]=4;
Thus, at the currDDA position 3.0 (row 1716), a currIndex value of 4 may be used to select the appropriate filtering coefficients from the filter coefficients table 1712. As will be appreciated, the DDA 1711 may continue to be incremented by DDAStep for each output pixel, and filtering (which may be vertical or horizontal depending on whether DDAStep is in the X (horizontal) or Y (vertical) direction) may be applied using the currPixel and currIndex determined for each currDDA value.

As discussed above, currIndex may be used as a selection index to select the appropriate filtering coefficients from the filter coefficients table 1712 to apply to the selected pixels. The filtering process may include obtaining the source pixel values around the center pixel (currPixel), multiplying each of the selected pixels by the appropriate filtering coefficients selected from the filter coefficients table 1712 based on currIndex, and summing the results to obtain a value of the output pixel at the location corresponding to currDDA. Further, because the present embodiment utilizes 8 phases between same colored pixels, using the 5-tap horizontal/3-tap vertical filtering embodiment, five 8-deep tables may be provided for horizontal filtering, and three 8-deep tables may be provided for vertical filtering. In one embodiment, each of the coefficient table entries may include a 16-bit 2's complement fixed point number with 3 integer bits and 13 fraction bits.

Further, assuming a Bayer image pattern, in one embodiment, the vertical scaling component may include four separate 3-tap polyphase filters, one for each color component: Gr, R, B, and Gb. Each of the 3-tap filters may use the DDA 1711 to control the stepping of the current center pixel and the index for the coefficients, as described above. Similarly, the horizontal scaling components may include four separate 5-tap polyphase filters, one for each color component: Gr, R, B, and Gb. Each of the 5-tap filters may use the DDA 1711 to control the stepping (e.g., via DDAStep) of the current center pixel and the index for the coefficients. It should be understood however, that fewer or more taps could be utilized by the horizontal and vertical scalers in other embodiments.

For boundary cases, the pixels used in the horizontal and vertical filtering process may depend upon the relationship of the current DDA position (currDDA) relative to a frame border (e.g., border defined by the active region 312 in FIG. 21). For instance, in horizontal filtering, if the currDDA position, when compared to the position of the center input pixel (SrcX) and the width (SrcWidth) of the frame (e.g., width 290 of the active region 312 of FIG. 21) indicates that the DDA 1711 is close to the border such that there are not enough pixels to perform the 5-tap filtering, then the same-colored input border pixels may be repeated. For instance, if the selected center input pixel is at the left edge of the frame, then the center pixel may be replicated twice for horizontal filtering. If the center input pixel is near the left edge of the frame such that only one pixel is available between the center input pixel and the left edge, then, for horizontal filtering purposes, the one available pixel is replicated in order to provide two pixel values to the left of the center input pixel. Further, the horizontal scaling logic 368 may be configured such that the number of input pixels (including original and replicated pixels) cannot exceed the input width. This may be expressed as follows:

StartX = (((DDAInitX + 0x0001.0000) & 0xFFFE.0000)>>16)

EndX = (((DDAInitX + DDAStepX * (BCFOutWidth − 1)) |

0x0001.0000)>>16)

EndX − StartX <= SrcWidth − 1

wherein, DDAInitX represents the initial position of the DDA 1711, DDAStepX represents the DDA step value in the horizontal direction, and BCFOutWidth represents the width of the frame output by the raw scaler circuitry 1652.

For vertical filtering, if the currDDA position, when compared to the position of the center input pixel (SrcY) and the width (SrcHeight) of the frame (e.g., width 290 of the active region 312 of FIG. 21) indicates that the DDA 1711 is close to the border such that there are not enough pixels to perform the 3-tap filtering, then the input border pixels may be repeated. Further, the vertical scaling logic 1710 may be configured such that the number of input pixels (including original and replicated pixels) cannot exceed the input height. This may be expressed as follows:

StartY = (((DDAInitY + 0x0001.0000) & 0xFFFE.0000)>>16)

EndY = (((DDAInitY + DDAStepY * (BCFOutHeight − 1)) |

0x0001.0000)>>16)

EndY − StartY <= SrcHeight − 1

wherein, DDAInitY represents the initial position of the DDA 1711, DDAStepY represents the DDA step value in the vertical direction, and BCFOutHeight represents the width of the frame output by the raw scaler circuitry 1652.

Referring now to FIG. 126, a flow chart depicting a method 1720 for applying binning compensation filtering to image data received by the front-end pixel processing unit 130 in accordance with an embodiment. It will be appreciated that the method 1720 illustrated in FIG. 126 may apply to both vertical and horizontal scaling. Beginning at step 1721 the DDA 1711 is initialized and a DDA step value (which may correspond to DDAStepX for horizontal scaling and DDAStepY for vertical scaling) is determined. Next, at step 1722, a current DDA position (currDDA), based on DDAStep, is determined. As discussed above, currDDA may correspond to an output pixel location. Using currDDA, the method 1720 may determine a center pixel (currPixel) from the input pixel data that may be used for binning compensation filtering to determine a corresponding output value at currDDA, as indicated at step 1723. Subsequently, at step 1724, an index corresponding to currDDA (currIndex) may be determined based on the fractional between-pixel position of currDDA relative to the input pixels (e.g., row 1713 of FIG. 125). By way of example, in an embodiment where the DDA includes 16 integer bits and 16 fraction bits, currPixel may be determined in accordance with the equations discussed above, and currIndex may be determined in accordance with the equations discussed above. While the 16 bit integer/16 bit fraction configuration is described herein as one example, it should be appreciated that other configurations of the DDA 1711 may be utilized in accordance with the present technique. By way of example, other embodiments of the DDA 1711 may be configured to include a 12 bit integer portion and 20 bit fraction portion, a 14 bit integer portion and 18 bit fraction portion, and so forth.

Once currPixel and currIndex are determined, same-colored source pixels around currPixel may be selected for multi-tap filtering, as indicated by step 1725. For instance, as discussed above, one embodiment may utilize 5-tap polyphase filtering in the horizontal direction (e.g., selecting 2 same-colored pixels on each side of currPixel) and may utilize 3-tap polyphase filtering in the vertical direction (e.g., selecting 1 same-colored pixel on each side of currPixel). Next, at step 1726, once the source pixels are selected, filtering coefficients may be selected from the filter coefficients table 1712 of the raw scaler circuitry 1708 based upon currIndex.

Thereafter, at step 1727, filtering may be applied to the source pixels to determine the value of an output pixel corresponding to the position represented by currDDA. For instance, in one embodiment, the source pixels may be multiplied by their respective filtering coefficients, and the results may be summed to obtain the output pixel value. The direction in which filtering is applied at step 1727 may be vertical or horizontal depending on whether DDAStep is in the X (horizontal) or Y (vertical) direction. Finally, at step 263, the DDA 1711 is incremented by DDAStep at step 1728, and the method 1720 returns to step 1722, whereby the next output pixel value is determined using the binning compensation filtering techniques discussed herein.

Referring to FIG. 127, the step 1723 for determining currPixel from the method 1720 is illustrated in more detail in accordance with one embodiment. For instance, step 1723 may include the sub-step 1729 of determining whether the output pixel location corresponding to currDDA (from step 1722) is even or odd. As discussed above, an even or odd output pixel may be determined based on the least significant bit of currDDA based on DDAStep. For instance, given a DDAStep of 1.25, a currDDA value of 1.25 may be determined as odd, since the least significant bit (corresponding to bit 14 of the fractional portion of the DDA 1711) has a value of 1. For a currDDA value of 2.5, bit 14 is 0, thus indicating an even output pixel location.

At decision logic 1730, a determination is made as to whether the output pixel location corresponding to currDDA is even or odd. If the output pixel is even, decision logic 1730 continues to sub-step 1731, wherein currPixel is determined by incrementing the currDDA value by 1 and rounding the result to the nearest even input pixel location, as represented by Equation 6a above. If the output pixel is odd, then decision logic 1730 continues to sub-step 1732, wherein currPixel is determined by rounding the currDDA value to the nearest odd input pixel location, as represented by Equation 6b above. The currPixel value may then be applied to step 1725 of the method 1720 to select source pixels for filtering, as discussed above.

Referring also to FIG. 128, the step 1724 for determining currindex from the method 1720 is illustrated in more detail in accordance with one embodiment. For instance, step 1724 may include the sub-step 1733 of determining whether the output pixel location corresponding to currDDA (from step 1722) is even or odd. This determination may be performed in a similar manner as step 1729 of FIG. 127. At decision logic 1734, a determination is made as to whether the output pixel location corresponding to currDDA is even or odd. If the output pixel is even, decision logic 1734 continues to sub-step 1735, wherein currindex is determined by incrementing the currDDA value by one index step determining currindex based on the lowest order integer bit and the two highest order fraction bits of the DDA 1711. For instance, in an embodiment wherein 8 phases are provided between each same-colored pixel, and wherein the DDA includes 16 integer bits and 16 fraction bits, one index step may correspond to 0.125, and currindex may be determined based on bits [16:14] of the currDDA value incremented by 0.125 (e.g., Equation 7a). If the output pixel is odd, decision logic 1734 continues to sub-step 1736, wherein currindex is determined by incrementing the currDDA value by one index step and one pixel shift, and determining currindex based on the lowest order integer bit and the two highest order fraction bits of the DDA 1711. Thus, in an embodiment wherein 8 phases are provided between each same-colored pixel, and wherein the DDA includes 16 integer bits and 16 fraction bits, one index step may correspond to 0.125, one pixel shift may correspond to 1.0 (a shift of 8 index steps to the next same colored pixel), and currindex may be determined based on bits [16:14] of the currDDA value incremented by 1.125 (e.g., Equation 7b).

As discussed above, the raw scaler circuitry 1652 may also provide chromatic aberration correction logic 1737. Chromatic aberration refers generally to the spatial shift of blue and red components with respect to green components. These shifts may be caused by the chromatic aberration of the lens used to capture the image data. As lenses become smaller and the price constraints dictate cheaper leans construction, these defects may become a barrier to further size and cost reduction, even for lenses with a normal focal length. Chromatic aberration is generally a result of the dependency of a lens' refractive index on wavelength. This dependency results in differing geometric distortion for red, green, and blue color components. Longitudinal chromatic aberration causes different colors of light to focus on different planes. Lateral chromatic aberration results in a radial shift between the red, green, and blue wavelengths.

Geometric distortion manifests as a radial variation in the magnification of the lens, resulting in barrel distortion if the magnification decreases radially or pincushion distortion if the magnification increases radially. Under certain circumstances, it may be possible for a lens to exhibit both barrel and pincushion distortion at the same time. For example, the magnification may first decrease radially and then increase near the edge of the lens. Such distortion may be referred to a moustache distortion. Both the geometric distortion and the chromatic aberrations may degrade the quality of the resultant image provided by the ISP. Thus, by either fully or partially correcting the geometric distortion, the chromatic aberration, or both, smaller, thinner, and cheaper lenses may be used while maintain sufficient visual quality in the video and still frames produced by the camera.

FIG. 129 illustrates typical distortion curves for red, green, and blue color channels 1738, 1739, and 1740, respectively. As illustrated, the graph plots the distortion, sometimes referred to as displacement, versus an ideal undistorted radius. The distortion, as a percentage of the maximum radius, may be represented by the following equation:
Distortion=(Distorted Radius−Ideal Radius)*100/Maximum Radius
Because the green wavelength is between the red and blue wavelengths, the green channel 1 739 distortion may be approximated as the mean distortion between the red channel 1 738 and blue channel 1 740 distortions. Thus, chromatic aberrations may be reduced by warping the red channel 1 738 and blue channel 1 740 distortions inward towards the green channel 1 739 distortions.

FIG. 130 illustrates a 1920×1080 resolution RAW frame that simulates the lens distortion of FIG. 129. For example, as illustrated, the RAW frame may present red or blue hues in certain locations. By using the chromatic aberration correction logic 1737, these red or blue hues may be reduced. As will be discussed in more detail below, one primary function of the ISP pipe logic 82 is to convert Bayer CFA frames to RGB frames using a process known as “demosaicing.” To obtain missing samples for each color channel, the demosaicing process uses the data from all channels in order to recover high-frequency detail and reduce aliasing in the resultant RGB frame. The demosaicing process may rely heavily on the correlation between the red, green, and blue channels. Chromatic aberration may disrupt these cross-color correlations, thus causing the demosaic procedure to generated less than optimal results. For example, FIG. 131 is an image, illustrating the results of applying demosaic logic to a frame with chromatic aberrations. As illustrated, portions 1741 of the image may present some “speckling” introduced by the demosaic logic due to the chromatic aberrations. In order to provide more optimal results, the chromatic aberration correction logic 1737 may be applied prior to the demosaic logic. Thus, the chromatic aberrations may be reduced, leading to more accurate demosaic logic results. The relative distortion for chromatic aberration correction may be more clearly illustrated by the graph 1750 of FIG. 132. This graph illustrates the relative distortion for the lens characteristics shown in FIG. 129 in relation to the green channel 1 739 distorted radius. By warping the blue and red channel distortions towards the green channel 1 739 distortion, the image quality may be greatly improved. For example, FIG. 133 illustrates a simulated image where the chromatic aberrations are removed prior to demosaicing the image. As may be appreciated, there may be significantly less “speckling” when the demosaicing occurs after the chromatic aberration correction logic 1737.

In embodiments where the aforementioned defective pixel detection/correction logic, gain/offset/compensation blocks, noise reduction logic, lens shading correction logic do not rely upon the linear placement of the pixels, the raw scaler circuitry 1652 may be incorporated with the demosaicing logic to perform binning compensation filtering and reposition the pixels prior to demosaicing, as demosaicing generally does rely upon the even spatial positioning of the pixels. Further, to provide a more accurate demosaicing, the chromatic aberration may be removed from the raw Bayer CFA frame before it reaches the demosaic logic. For instance, in one embodiment, the raw scaler circuitry 1652 may be incorporated anywhere between the sensor input and the demosaicing logic, with temporal filtering and/or defective pixel detection/correction being applied to the raw image data prior to the raw scaler logic 1040.

Having now discussed the optimal timing for the chromatic aberration correction logic, the discussion now turns to a detailed discussion of the process for removing the chromatic aberrations. Chromatic aberration removal involves relatively small radial displacements in the red and blue components where the benefits of removing the chromatic aberration outweigh any artifacts introduced by warping the red and blue components of the raw frame at their lower resolution. Generally speaking, the chromatic aberrations may be removed by warping the red and blue components of the raw frame to have the same geometric distortion as the green frame, thus aligning the colors. The green wavelength may remain unaltered by the chromatic aberration correction logic. First, as described above, the green wavelength is between the red and blue wavelengths, so the green distortions typically may be assumed to approximate the “mean” distortion. Further, the green component contributes most to the perceived brightness of the frame, Thus, artifacts from warping the green channel in the raw domain may be much more likely visible than artifacts caused by warping the red and blue channels.

As discussed previously, the raw scaler circuitry 1652 may be responsible for coordinate generation and image resampling. For example, for each output sample position, a coordinate generator of the raw scaler circuitry 1652 may produce an X/Y coordinate pair defining the source of the output sample within a specific color of the input frame. Further, for each output sample, a resampler of the raw scaler circuitry 1652 may use the X/Y coordinates within an input color frame to generate the output sample using multiphase finite impulse response (FIR) filters.

The raw scaling and binning correction functions will produce an input to output mapping which is separable, and thus may be performed independently in the horizontal and vertical dimensions. However, when the chromatic aberration correction function is added, the result is a function which is not strictly separable because the distortion (displacement) is a function of radius, thus utilizing both vertical and horizontal resampling. However, the chromatic aberration correction may be implemented as a separable function with little or no degradation in visual quality of the resultant raw image. In the separable implementation, vertical and horizontal resampling is performed independently for the chromatic aberration correction.

FIG. 134 is a block diagram of the raw scaler circuitry 1652, in accordance with an embodiment. As illustrated, the raw scaler circuitry 1652 may include a vertical resampler 1772 and a horizontal resampler 1774. The vertical resampler 1772 may include configurable line buffers 1780, a barrel shifter 1782, and a line buffer controller 1784 working with a coordinate generator 1776 to provide inputs for a 5-tap 8-phase filter 1786. The outputs from the 5-tap 8-phase filter 1786 may be fed as an input to the horizontal resampler 1774, which may include shift registers 1788 and one or multiplexers 1790 working together with a horizontal resampler coordinate generator 1792 to provide inputs for a 9-tap 8-phase filter 1794. The output of the 9-tap 8-phase filter 1794 may provide the resultant raw data output for the raw scaler circuitry 1652.

Having now summarized the components of the raw scaler circuitry 1652, the discussion now turns to a more detailed discussion of the individual components of the raw scaler circuitry 1652. FIG. 135 is a block diagram illustrating the vertical resampler coordinate generator 1776. The vertical resampler coordinate generator 1776 may include a vertical coordinate generator 1810, vertical displacement computation logic 1812, and vertical sensor to component coordinate translation logic 1816.

The vertical coordinate generator 1810 may compute the coordinates on the sensor for every output sample of the vertical resampler. This may be done, for example, through use of a Y digital differential analyzer (DDA) along with X and Y counters, as follows:

// Block Primary Inputs

int YDDAInit;

// Initial value for the YDDA (at the start of the frame) 16.16 fp 2's comp

The vertical displacement computation logic 1812 may compute the X and Y displacements (e.g., distortions) for the current vertical resampler output sample. This logic may take the XCount and SensorY coordinates produced by the coordinate generator 1810, computes the radius, uses the radius to address one of a pair of lookup tables (one each for red and blue), retrieves the radial displacement from the look-up table and uses it to compute the vertical (Y) displacement. FIG. 136 illustrates the vertical displacement computation 1812, which may be implemented as follows:

// Block Primary Inputs

int XCount;

// Sensor X coordinate 13-bit comp

int SensorY;

// Sensor Y coordinate 16.16 fp 2's comp

int Color;

// Color of current sample

int OptCenterX;

// X coordinate of the optical center of the sensor 13-bit

int OptCenterY;

// Y coordinate of the optical center of the sensor 13-bit

int RadScale;

// X and Y coordinates are scaled by 2{circumflex over ( )}RadScale before being

// used to compute radius. Maintains constant precision at

// output of radius computation for varying sensor sizes. 2-bit

int CACLut[2][256];

// Chromatic Aberration correction LUTs

// Block Primary Outputs

int YDispl;

// Y Displacement. 6.8 fp 2's compl

// Internal Variables

int radX;

// X coordinate relative to optical center. 16.16 fp 2's comp

int radY;

// Y coordinate relative to optical center. 16.16 fp 2's comp

int sclX;

// X coordinate scaled prior to radius comp. 19.16 fp 2's comp

int sclY;

// Y coordinate scaled prior to radius comp. 19.16 fp 2's comp

int radsq;

// square of the radius

int radrecip;

// reciprocal of the radius 1.21 fp

int rad;

// radius. 13.3 fp

int cos;

// cosine of the angle between the line from the

//optical center to the sample and the vertical (Y axis)

int displ;

// radial displacement. 6.8 fp 2's comp

// Pseudo-code

radX = XCount − OptCenterX;

radY = SensorY − (OptCenterY << 16);

sclX = radX * (2{circumflex over ( )}RadScale);

sclY = radY * (2{circumflex over ( )}RadScale);

radsq = (sclX{circumflex over ( )}2) + (sclY{circumflex over ( )}2);

radrecip = 1/sqrt(radsq);

rad = radsq * radrecip;

cos = sclY * radrecip;

lut_index = rad[14:7]; // integer bits [11:4]

lut_frac = rad[6:3]; // least significant 4 integer bits

lut_sel = color >> 1; // MSB of color

displ = ((16-lut_frac)*CACLut[lut_sel][lut_index] +

lut_frac*CACLut[lut_sel][lut_index+1] + 8) >> 4;

YDispl = cos * displ;

FIG. 137 is a block diagram illustrating the vertical sensor to component coordinate translation logic 1816. The vertical sensor to component coordinate translation logic 1816 may translate the corrected sensor Y coordinate to the Y coordinate within the appropriate input color frame. The YDispl values are added to the Sensor Y coordinates to produce a corrected coordinate that specifies the vertical position on the sensor corresponding to the output sample. These coordinates are at the sensor “raw” resolution and are relative to the top of the sensor. Thus, the vertical sensor to component coordinate translation logic 1816 may convert the coordinates to the resolution of the color components of the sensor output, where the coordinates are relative to the top of the appropriate color component. This functionality may be implemented as follows:

// Block Primary Inputs

int CorrSensorYCoord;

// Corrected sensor Y coordinate. 16.3 fp 2's comp

int Color;

// Color of current sample

int VertBinning;

// Amount of Vertical binning in the sensor 2-bit

int YDDAOffsetGr;

// Vertical offset from top edge for Gr 1.4 fp 2's comp

int YDDAOffsetR;

// Vertical offset from top edge for R 1.4 fp 2's comp

int YDDAOffsetB;

// Vertical offset from top edge for B 1.4 fp 2's comp

int YDDAOffsetGb;

// Vertical offset from top edge for Gb 1.4 fp 2's comp

// Block Primary outputs

int YCoord;

// Y Coordinate within color component specified by Color.

//16.3 fp 2's comp

// Local Variables

int ScaledY;

// Scaled Y coordinate

// Pseudo-Code

ScaledY = CorrSensorYCoord >> VertBinning;

switch(Color)

{

case 0: ComponentY = (ScaledY + YDDAOffsetGr + 1) >> 1;

break;

case 1: ComponentY = (ScaledY + YDDAOffsetR + 1) >> 1;

break;

case 2: ComponentY = (ScaledY + YDDAOffsetB + 1) >> 1;

break;

default: ComponentY = (ScaledY + YDDAOffsetGb + 1) >> 1;

}

Referring back to FIG. 134, as discussed above, the vertical resampler 1772 includes line buffers 1780, a line buffer controller 1784, a barrel shifter 1782 and a vertical filter 1786 (e.g., a 5-tap 8-phase filter). For each sample of each output line, the line buffers 1780 and the line buffer controller 1784 may provide up to five vertically adjacent samples from the appropriate color component of the input frame, depending on the vertical filter size. For example, if the raw scaler circuitry 1652 is producing Gr/R output lines and the vertical filter is five taps, the line buffers will provide five vertically adjacent samples from the Gr input color component followed by five vertically adjacent samples from the R input color component, etc. At each output sample position, the samples required at the input to vertical filter 1786 may be determined by: 1) the color of the sample being generated, 2) the value of the Y coordinate, 3) the horizontal position, and 4) the number of vertical filter taps. In one embodiment, this functionality may be implemented as follows:

// Block Primary Inputs

int YCoord;

// Y coordinate within the component defined by Color

16.3

// fp 2's comp

int XCount;

// Horizontal position counter

int Color;

// The color of the current sample. Same encoding as in

//coordinate generator

int VertNumTap;

// Number of vertical taps = VertNumTap+1. Field has

//three bits.

int inframe[inHeight][inWidth];

// input Bayer frame

int inHeight;

// Input Height

// Block Primary Outputs

int vtap0;

// Tap holding oldest line

int vtap1;

// Tap holding older line

int vtap2;

// Tap holding current line

int vtap3;

// Tap holding newer line

int vtap4;

// Tap holding newest line

// Local varaibles

int line[5];

// line number for tap

int tapnum

// Pseudo-code

// If number of taps is odd, lines switch when ycoord is at at mid-point

if(!(VertNumTap&0x1))

YCoord += 4;

// Center tap is at closest integer line number

YCoord >>= 3;

// Throw away fractional part

// taps are centered on YCoord. Limit them to active area of component

As illustrated in the preceding pseudo-code, during vertical resampling, the vertical coordinate of the center tap of the vertical filter 1786 is given by floor(ycoord+0.5). When performing downscaling, binning compensation, or both, the vertical coordinate will be constant during each output line and will step by >=1 between lines. If chromatic aberration correction is being performed, the y coordinate for the red (and blue) output samples may be different from that of the green sample, and the y coordinate of the red (or blue) samples may vary across the line. The difference between the red and green or blue and green coordinates may be more pronounced at the edges of the frame and may be very small, or zero towards the center of the frame. FIG. 138 illustrates an example of the Y coordinates of the center tap of the vertical filter 1786 for the first four output lines from the vertical resampler in a case with no vertical scaling or binning correction, and having a particularly bad case of chromatic aberration.

As illustrated in FIG. 138, since there is no vertical scaling or binning compensation, the green output samples are aligned with the green input samples. However, there is a large vertical offset (−4) between the red input and red output and between the blue input and the blue output (4). If a 5-tap vertical filter were to be used, in order to generate output line 0, the filter may access green lines (−4) to (4) and red lines (−8) to (0), which imply that input lines (−8) to (4) may be stored. In order to generate output line 1, the filter may access blue lines (1) to (9) and green lines (−3) to (5), which implies that input lines (−3) to (9) may be stored.

However, as illustrated in FIG. 139, if the Chromatic Aberration were a linear function of the radius, the offsets between red and green and between blue and green would be constant for each output line, but decreasing to zero near the vertical center of the frame. Since the Chromatic Aberration is not a linear function of the radius, variations in vertical offset can occur during a line.

As illustrated in FIG. 139, the red vertical offset for output line 0 decreases to (2) at output sample 140 and the vertical offset for line 2 decreases to (2) at output sample 140. In general the offsets will decrease as radius decreases. This will tend to reduce line storage requirements towards the vertical center of the frame. FIG. 140 illustrates the offset between the vertical position of the center tap on the red (and blue) component and the corresponding green component. Note that this example is for a 1920×1080 frame with approximately 1% chromatic distortion.

FIG. 140 illustrates vertical offsets from the green channel. As illustrated, a decrease in the magnitude of a positive offset or an increase in the magnitude of a negative offset may indicate that more than one poutput line is generated for each input line, thus indicating that the same input lines are used when generating a pair of vertically adjacent output samples of the same color component (e.g., up-scaling).

Moving now to a more detailed discussion of the vertical filter 1786, the vertical filter 1786 may produce a weighted sum of the five input taps. The weights of these taps may be dependant on the phase input (e.g., the most significant three fractional bits of the Y coordinate). In some embodiments, the operation of the vertical filter may be implemented as follows:

// Block Primary Inputs

int vtap0;

// 16-bit sample value

int vtap1;

// 16-bit sample value

int vtap2;

// 16-bit sample value

int vtap3;

// 16-bit sample value

int vtap4;

// 16-bit sample value

int phase;

// 3-bit filter phase

int vfilter[8][5];

// 8×5 array of 3.13 2's comp filter coefficients

// Block Primary Outputs

int vfilt;

// 16-bit sample output

// Local variables

int accum;

// 35-bit accumulator

// Pseudo-Code

accum = (vtap0*vfilter[phase][0]);

accum += (vtap1*vfilter[phase][1]);

accum += (vtap2*vfilter[phase][2]);

accum += (vtap3*vfilter[phase][3]);

accum += (vtap4*vfilter[phase][4]);

// round

accum += 0x1000;

accum >>= 13;

// limit to 16-bit unsigned output

if(accum < 0)

vfilt = 0;

else if(accum > 65535)

vfilt = 65536;

else

vfilt = accum;

Having discussed the vertical resampler 1772 in depth, the discussion now turns to the horizontal resampler 1774. As discussed above, the horizontal resampler 1774 includes a horizontal resampler coordinate generator 1792. FIG. 141 is a block diagram illustrating one embodiment of the horizontal resampler coordinate generator 1792. Similar to the vertical coordinate generator 1776, the horizontal resampler coordinate generator 1792 may include a coordinate generator 1952, a displacement computation logic 1954, and sensor to component coordinate translation logic 1958.

The horizontal coordinate generator 1952 may compute the coordinates on the sensor for every output sample by using X and Y DDAs and the horizontal and vertical output sample/line counter. In one embodiment, the horizontal coordinate generator 1952 may be implemented according to:

// Block Primary Inputs

int XDDAInit;

// Initial value for the XDDA (at the start of the frame) 16.16 fp 2's comp

int XDDAStep;

// Step in XDDA value for each output sample. 16.16 fp

int YDDAInit;

// Initial value for the YDDA (at the start of the frame) 16.16 fp 2's comp

FIG. 142 is a block diagram illustrating the horizontal displacement computation logic 1954. The horizontal displacement computation logic 1954 may computer the X displacement (e.g., distortion) for each output sample. The horizontal displacement computation logic 1954 takes the sensor X and Y coordinates produced by the sensor coordinate generator, computes the radius, uses the radius to address one of a pair of lookup tables (one each for red and blue), retrieves the radial displacement from the look-up table and uses it to compute the horizontal displacement. In one embodiment, the horizontal displacement computation logic 1954 may be implemented according to:

// Block Primary Inputs

int SensorX;

// Sensor X coordinate 16.16 fp 2's comp

int SensorY;

// Sensor Y coordinate 16.16 fp 2's comp

int Color;

// Color of current sample

int OptCenterX;

// X coordinate of the optical center of the sensor 13-bit

int OptCenterY;

// Y coordinate of the optical center of the sensor 13-bit

int RadScale;

// X and Y coordinates are scaled by 2{circumflex over ( )}RadScale before being

// used to compute radius. Maintains constant precision at

// output of radius computation for varying sensor sizes. 2-bit

int CACLut[2][256];

// Chromatic Aberration correction LUTs

// Block Primary Outputs

int XDispl;

// Y Displacement. 6.8 fp 2's compl

// Internal Variables

int radX;

// X coordinate relative to optical center. 16.16 fp 2's comp

int radY;

// Y coordinate relative to optical center. 16.16 fp 2's comp

int sclX;

// X coordinate scaled prior to radius computation. 19.16 fp 2's comp

int sclY;

// Y coordinate scaled prior to radius computation. 19.16 fp 2's comp

int radsq;

// square of the radius

int radrecip;

// reciprocal of the radius 1.21 fp

int rad;

// radius. 13.3 fp

int sin;

// sine of the angle between the line from the optical center to the sample

The horizontal sensor to component coordinate translation logic 1958 may translate the corrected sensor X coordinate to the X coordinate within the appropriate color frame. The XDispl values are added to the Sensor X coordinate to produce a corrected coordinate that specifies the horizontal position o n the sensor corresponding to the output sample. These coordinates are at sensor “raw” resolution and may be relative to the left side of the sensor. The horizontal sensor to component translation logic 1958 may convert the coordinates to the resolution of the color components of the sensor output, which may be relative to the left side of the appropriate color component. FIG. 143 is a block diagram illustrating the horizontal sensor to component coordinate translation logic 1958. In some embodiments, the horizontal sensor to component coordinate translation logic 1958 may be implemented according to the following pseudo-code:

// Block Primary Inputs

int CorrSensorXCoord;

// Corrected sensor X coordinate. 16.3 fp 2's comp

int Color;

// Color of current sample

int HorzBinning;

// Amount of Horizontal binning in the sensor 2-bit

int XDDAOffsetGr;

// Horizontal offset from left edge for Gr 1.4 fp 2's comp

int XDDAOffsetR;

// Horizontal offset from left edge for R 1.4 fp 2's comp

int XDDAOffsetB;

// Horizontal offset from left edge for B 1.4 fp 2's comp

int XDDAOffsetGb;

// Horizontal offset from left edge for Gb 1.4 fp 2's comp

// Block Primary outputs

int XCoord;

// X Coordinate within color component specified by Color. 16.3 fp

//2's comp

// Local Variables

int ScaledX;

// Scaled X coordinate

// Pseudo-Code

ScaledX = CorrSensorXCoord >> HorzBinning;

switch(Color)

{

case 0: ComponentX = (ScaledX + XDDAOffsetGr + 1) >> 1;

break;

case 1: ComponentX = (ScaledX + XDDAOffsetR + 1) >> 1;

break;

case 2: ComponentX = (ScaledX + XDDAOffsetB + 1) >> 1;

break;

default: ComponentX = (ScaledX + XDDAOffsetGb + 1) >> 1;

}

As discussed above, the horizontal resampler 1774 may include shift registers 1788, one or more multiplexers 1790, and a horizontal filter 1794 (e.g., a 9-tap 8-phase filter). For each sample of each output line, the shift registers 1788 and multiplexers 1790 provide nine horizontally adjacent samples from the appropriate color component of the vertically resampled frame. For example, if the raw scaler circuitry 1652 is producing a Gr/R output line, the shift registers 1788 and multiplexers 1790 will provide nine horizontally adjacent samples from the Gr input color component followed by nine horizontally adjacent samples from the R input color component, etc. At each output sample position, the samples required at the input to the horizontal filter may be determined by: 1) the color of the sample being generated, 2) the value of the X coordinate, 3) the vertical position, and 4) the number of horizontal filter taps. In certain embodiments, this functionality may be implemented according to:

// Block Primary Inputs

int XCoord;

// X coordinate within the component defined by Color 16.3

//fp 2's comp

int YCount;

// Vertical position counter

int Color;

// The color of the current sample. Same encoding as in

//coordinate generator

int yresframe[OutHeight][InWidth];

// vertically resampled frame

int InWidth;

// Input Width

// Block Primary Outputs

int htap0;

// Tap holding sample (n−4)

int htap1;

// Tap holding sample (n−3)

int htap2;

// Tap holding sample (n−2)

int htap3;

// Tap holding sample (n−1)

int htap4;

// Tap holding sample (n)

int htap5;

// Tap holding sample (n+1)

int htap6;

// Tap holding sample (n+2)

int htap7;

// Tap holding sample (n+3)

int htap8;

// Tap holding sample (n+4)

// Local varaibles

int sample[9];

// sample number for tap

int tapnum

// Pseudo-code

XCoord += 4; // Center tap is at closest integer line number, round

XCoord >>= 3;

// Throw away fractional part

// taps are centered on XCoord. Limit them to active area of component

As illustrated above, during horizontal resampling, the horizontal coordinate of the center tap of the horizontal filter is given by floor(xcoord+0.5). When performing downscaling, binning compensation, or both, the horizontal coordinate of the red (or blue) sample will be numerically between the horizontal coordinates of the green samples on either side. If chromatic aberration correction is being performed, the x coordinates for the red (and blue) output samples may be offset from that of the green samples, and the offset may vary across the line. This offset may be more pronounced at the edges of the frame and may be very small, or zero towards the center of the frame. FIG. 144 illustrates the position of the center tap of the horizontal filter for the first four output lines from the horizontal resampler for a case with no vertical scaling or binning correction, but a particularly bad case of chromatic aberration.

As illustrated in FIG. 144, since there is no horizontal scaling or binning compensation, the green output samples are aligned with the green input samples. However, there is a large horizontal offset (−6) between the red input and red output and between the blue input and the blue output (8). If a 9-tap vertical filter were to be used, in order to generate output sample 0 on line 0, the filter may access samples (−8) to (8), sample 1 requires input samples (−13) to (3), sample 2 requires input samples (−6) to 10). The shift register may hold at least approximately 24 input samples in order to generate output line 0. In order to generate output line 1, the filter may access samples (0) to (16) for sample 0, (−7) to (9) for sample 1, (2) to (18) for sample 2 etc. In order to produce lines 1, the shift register may hold about 26 samples.

The horizontal offsets between input and output may decrease to zero at the vertical center of the frame (half way across). FIG. 145 illustrates the offset for the blue channel decreasing by 2. Input sample 53 is the center tap for blue output sample 23 and blue output sample 24. This indicates that the same set of input samples are used to generate two output samples.

FIG. 146 illustrates the maximum offset between the vertical position of the center tap on the red (and blue) component and the corresponding green component. Note that this example is for a 1920×1080 frame with approximately 1% chromatic distortion. Further, a decrease in the magnitude of a positive offset or an increase in the magnitude of a negative offset indicates that more than one output sample is generated for each input sample, indicating that the same input samples are used when generating a pair of horizontally adjacent output samples of the same color component (e.g., up-scaling).

Turning now to a discussion of the horizontal filter 1794, the horizontal filter 1794 may produce a weighted sum of the nine input taps. The weights of the taps may be dependent on the phase input (e.g., the most significant three fractional bits of the X coordinate). For example, in certain embodiments, the operation of the horizontal filter may be implemented according to:

// Block Primary Inputs

int htap0;

// 16-bit sample value

int htap1;

// 16-bit sample value

int htap2;

// 16-bit sample value

int htap3;

// 16-bit sample value

int htap4;

// 16-bit sample value

int htap5;

// 16-bit sample value

int htap6;

// 16-bit sample value

int htap7;

// 16-bit sample value

int htap8;

// 16-bit sample value

int phase;

// 3-bit filter phase

int hfilter[8][9]; // 8x9 array of 3.13 2's comp filter coefficients

// Block Primary Outputs

int hfilt;

// 16-bit sample output

// Local variables

int accum;

// 37-bit accumulator

// Pseudo-Code

accum = (htap0*hfilter[phase][0]);

accum += (htap1*hfilter[phase][1]);

accum += (htap2*hfilter[phase][2]);

accum += (htap3*hfilter[phase][3]);

accum += (htap4*hfilter[phase][4]);

accum += (htap5*hfilter[phase][5]);

accum += (htap6*hfilter[phase][6]);

accum += (htap7*hfilter[phase][7]);

accum += (htap8*hfilter[phase][8]);

// round

accum += 0x1000;

accum >>= 13;

// limit to 16-bit unsigned output

if(accum < 0)

hfilt = 0;

else if(accum > 0xffff)

hfilt = 0xffff;

else

hfilt = accum;

As discussed above, the output of the horizontal filter 1794 may be the chromatic aberration corrected raw data, which may be scaled to a desired size. When the image data is downscaled before exiting the raw processing logic 150, bandwidth can be preserved between the raw processing logic 150 and the memory 100 and/or the RGB processing logic 160.

RGB Processing Logic

Referring again briefly to FIG. 8, the RGB processing logic 160 may perform additional image processing after processing in the raw processing logic (RAWProc) 160 and before the image data is sent to the YCC processing logic 170. One example of the RGB processing logic 160 is shown in greater detail in FIG. 147. As seen in FIG. 147, the RGB processing logic 160 may receive image data from the raw processing block 154 or from the memory 100. When supplied by the DMA source S5 in the memory 100, the image data may be in Bayer raw or RGB format (e.g., raw8, raw10, raw12, raw14, raw16, RGB565, RGB888, or RGB16). When supplied by the raw processing logic 150, the image data may be in the raw format. Selection logic 162 may select the input to the RGB processing logic 160 as image data from the raw processing block 150 or from the memory 100.

The selected image data signal may enter selection logic 3000 and/or the demosaic (DEM) logic 3002, which may convert raw image data into RGB format. The selection logic 3000 may cause image data already in the RGB format to bypass the demosaic (DEM) logic 3002. Thus, the example of the RGB processing logic 160 shown in FIG. 147 can receive and process image data in either the raw or RGB format. Because the RGB processing logic 160 can receive either raw or RGB image data, the RGB processing logic 160 may be able to process the same image data in multiple passes, storing and retrieving the image data from the memory 100 any suitable number of times. In addition, the RGB processing logic 160 may be able to receive a raw or RGB image signal obtained from another source (e.g., a third-party camera or rgb image data generated by software running on the processor(s) 16). In this way, the RGB processing logic 160 may process RGB image data to be displayed on the display 28, which may include photo data, video data, or any other RGB-format image data deriving from a source other than the sensor(s) 90.

Before continuing further, it should be noted that the input image data in the RGB or raw formats may be signed image data. The scale and offset logic 82 (not shown in FIG. 147) may be implemented as a function of the direct memory access (DMA) input and output logic, and may convert unsigned image data in the memory 100 into signed 17-bit image data. The scaling and offsetting process to obtain signed 17-bit data is discussed in greater detail above with reference to FIGS. 40-43. In general, as mentioned above, the scale and offset logic 82 provides a programmable zero bias at the input and output of the RGB processing logic 160. The programmable zero bias may set the zero level in the 17-bit signed range. Namely, the DMA input source to the RGB processing logic 160 may subtract the zero bias to create negative inputs, and the zero bias may be added back at the output DMA destination (e.g., the memory 100) to bring the pixel data back into a positive form, before the pixel data is clipped to an unsigned 16-bit range. Since the range of the signed 17-bit pixel data on the negative side is anticipated to be much smaller than the range on the positive side, the zero bias approach used in generating the signed 17-bit image data allows for a greater range of the pixel data for processing through the RGB processing logic 160, as compared to using signed 16-bit pixels. Internally, the interface between various functional blocks of the RGB processing logic 160 is signed 17-bit. When line buffers are used by a functional block of the RGB processing logic 160, the zero bias may be temporarily subtracted from the input line buffers and added to the output line buffers after the pixel data has been clipped to a 16-bit unsigned range.

The RGB image data output by the demosaic (DEM) logic 3002 or provided by the memory 100 may be processed by several functional blocks of the RGB processing logic 160. These may include local tone mapping (LTM) logic 3004, first offset, gain, and clip (GOC1) logic 3006, RGB color correction matrix (CCM) logic 3008, color correction in a 3-D color lookup table (CLUT) 3010, second offset, gain, and clip (GOC2) logic 3012, RGB gamma logic 3014, and/or color space conversion (CSC) logic 3018. The RGB processing logic 160 may also generate histograms using data that can be selected via selection logic 3016 as image data before or after being processed in the RGB gamma logic 3014 using histogram generation logic 3018. The histograms generated by the histogram generation logic 3018 may be output to the memory 100. Although the 3D CLUT 3010 is shown as located before the RGB gamma logic 3014, in other embodiments these may be reversed.

Note also that the LTM logic 3004 occurs immediately after the demosaic (DEM) logic 3002 in the example of FIG. 147. The LTM logic 3004 may be more effective the closer it occurs to highlight recovery (HR) 1038. Moreover, the LTM logic 3004 may occur before the CCM logic 3008 because handling clipped pixels before the CCM logic 3008 may preserve more image information. Additionally, it may be recalled that the statistics logic 140a and 140b essentially calculate the image statistics in the raw domain. As discussed below, the local tone curves of the LTM logic 3004 is programmed using these statistics. Thus, if the LTM logic 3004 were placed after the CCM logic 3008, the local tone curves of the LTM logic 3004 would need to have been generated using in a manner that also accounted for (e.g., simulated) the effect of passing the pixels through the CCM logic 3008.

The color space conversion (CSC) logic 3020 may selectively convert the image data from the RGB gamma logic 3014 into the YCbCr format before the image data is saved to the memory 100 or output to the YCC processing logic 170. In some embodiments, the RGB image data may not be converted into the YCbCr format in the CSC logic 3020, but instead may be saved to memory in the RGB format. This image data may be reprocessed by the RGB processing logic 160 any suitable number of times. For example, software controlling the ISP pipe processing logic 80 may send the RGB image data through the RGB processing logic 160 multiple times with the same or variations of the control parameters. Under certain conditions (e.g., low-light conditions, high-noise conditions, or images with high dynamic ranges), reprocessing image data through the RGB processing logic 160 may produce more pleasing images. When the output pixels are sent to memory, a 16-bit-per-component image data can be sent in an 8-bit format by truncating the lower 8-bits, or the 16-bit image data can be written in 16-bit format.

Demosaicing (DEM) Logic and Green Non-Uniformity (GNU) Correction

Referring now to FIG. 148, a graphical process flow 3030 that provides a general overview as to how demosaicing may be applied to a raw Bayer image pattern 3032 to produce a full color RGB is illustrated. As shown, a 4×4 portion 3034 of the raw Bayer image 3032 may include separate channels for each color component, including a green channel 3036, a red channel 3038, and a blue channel 3040. Because each imaging pixel in a Bayer sensor only acquires data for one color, the color data for each color channel 3036, 3038, and 3040 may be incomplete, as indicated by the “?” symbols. By applying a demosaicing technique 3042, the missing color samples from each channel may be interpolated. For instance, as shown by reference number 3044, interpolated data G′ may be used to fill the missing samples on the green color channel. Similarly, interpolated data R′ may (in combination with the interpolated data G′ 3044) be used to fill the missing samples on the red color channel 3046, and interpolated data B′ may (in combination with the interpolated data G′ 3044) be used to fill the missing samples on the blue color channel 3048. Thus, as a result of the demosaicing process, each color channel (R, G, B) will have a full set of color data, which may then be used to reconstruct a full color RGB image 3050.

Before demosaicing, however, it may be beneficial to correct any green non-uniformity (GNU). GNU may be characterized as a brightness difference between the Gr and Gb pixels over a uniformly illuminated and flat surface. When GNU is not corrected, it may lead to ‘maze’ artifacts upon applying the demosaic process 3042. Thus, GNU correction may be performed before the demosaic process 3042 on Green pixels only. A variety of GNU compensation modes may be supported. In the first mode, a simple thresholded average of green pixels may replace an original green value. In the second mode, a more advanced low pass filter with a high-frequency recovery filter may be used to correct the GNU. The second GNU mode may be include as part of the green interpolation filter that will be discussed in more detail below.

Referring now to the first GNU correction mode, FIG. 149 illustrates a 2×2 pixel grid configured in a Bayer CFA pattern. At each green pixel in the Bayer pattern, the absolute difference between the current green pixel, G1, and the green pixel to the right and below the current pixel, G2, is determined. If the determined value is smaller than a pre-determined threshold (e.g., pre-programmed by software and defined as gnu_thd below), the green sample G1 is replaced by the average of G1 and G2. By using the thresholded average replacement method, averaging of pixel values for G1 and G2 across edges may be avoided. Thus, the current mode may result in a preserved sharpness of the resultant image (e.g., Full RGB image 3050). Accordingly, GNU mode one may be implemented according to the following:

if (abs(G1−G2)<=gnu_thd)

G1=(G1+G2+1)>>1

The second GNU correction mode may apply varying green pixel values on the green pixels as the red and blue pixel values are being interpolated through the demosaic process 3042. Thus, this second mode of GNU may make use of the demosaicing logic 404 and, thus, will be discussed in conjunction with the demosaicing process described below. While the current discussion illustrates the GNU correction integrated with the demosaicing logic 404 for a more efficient use of hardware (e.g., using the same line buffers as the demosaicing logic 404), in some embodiments, the GNU correction may be completely segregated from the demosaicing logic 404, and may be implemented in a stand-alone fashion, independent from the demosaicing logic 404.

A demosaicing technique that may be implemented by the demosaicing logic 404 will now be described in accordance with one embodiment. On the green color channel, missing color samples may be interpolated using a low pass directional filter on known green samples and a high pass (or gradient) filter on the adjacent color channels (e.g., red and blue). For the red and blue color channels, the missing color samples may be interpolated in a similar manner, but by using low pass filtering on known red or blue values and high pass filtering on co-located interpolated green values. Further, in one embodiment, demosaicing on the green color channel may utilize a 5×5 pixel block edge-adaptive filter based on the original Bayer color data. As will be discussed further below, the use of an edge-adaptive filter may provide for the continuous weighting based on gradients of horizontal and vertical filtered values, which reduce the appearance of certain artifacts, such as aliasing, “checkerboard,” or “rainbow” artifacts, commonly seen in conventional demosaicing techniques.

During demosaicing on the green channel, the original values for the green pixels (Gr and Gb pixels) of the Bayer image pattern are used unless the GNU correction mode two is enabled. However, to obtain a full set of data for the green channel, green pixel values may be interpolated at the red and blue pixels of the Bayer image pattern. In accordance with the present technique, horizontal and vertical energy components, respectively referred to as Eh and Ev, are first calculated at red and blue pixels based on the above-mentioned 5×5 pixel block. The values of Eh and Ev may be used to obtain an edge-weighted filtered value from the horizontal and vertical filtering steps, as discussed further below.

By way of example, FIG. 150 illustrates the computation of the Eh and Ev values for a red pixel centered in the 5×5 pixel block at location (j, i), wherein j corresponds to a row and i corresponds to a column. As shown, the calculation of Eh considers the middle three rows (j−1, j, j+1) of the 5×5 pixel block, and the calculation of Ev considers the middle three columns (i−1, i, i+1) of the 5×5 pixel block. To compute Eh, the absolute value of the sum of each of the pixels in the red columns (i−2, i, i+2) multiplied by a corresponding coefficient (e.g., −1 for columns i−2 and i+2; 2 for column i) is summed with the absolute value of the sum of each of the pixels in the blue columns (i−1, i+1) multiplied by a corresponding coefficient (e.g., 1 for column i−1; −1 for column i+1). To compute Ev, the absolute value of the sum of each of the pixels in the red rows (j−2, j, j+2) multiplied by a corresponding coefficient (e.g., −1 for rows j−2 and j+2; 2 for row j) is summed with the absolute value of the sum of each of the pixels in the blue rows (j−1, j+1) multiplied by a corresponding coefficient (e.g., 1 for row j−1; −1 for row j+1). These computations are illustrated by the equations below:

In some embodiments, the cross-color gradients or energies may be useful in the demosaic logic 404. When cross-color energy is enabled, horizontal and vertical cross-color energies, CEh and CEv, respectively, may be added to the Eh and Ev values. CEh and CEv may be calculated as follows:

A confidence coefficient may be calculated based upon the CEh and CEv values. The confidence coefficient may provide a weighting coefficient for the CEh or CEv values based upon which value (CEh or CEv) is lower. When CEh and CEv are equal, no confidence coefficient may be necessary. However, when CEh and CEv are not equal, the confidence coefficient may be determined as follows:

These confidence coefficients may be used to weigh the horizontal and vertical cross-color energies before applying the horizontal and vertical cross-color energies to the horizontal and vertical energies, respectively, as follows:

Eh=Eh+w*CEh;

Ev=Ev+w*CEv;

The total energy sum may be expressed as: Eh+Ev. Further, while the example shown in FIG. 150 illustrates the computation of Eh and Ev for a red center pixel at (j, i), it should be understood that the Eh and Ev values may be determined in a similar manner for blue center pixels.

Horizontal and vertical energies may also be computed on the Green pixels. These energies may be useful to disable the high frequency filter when interpolating the red and blue color channels. When interpolating red or blue values, a 3×3 filter is used. For simplicity, the same filter kernel size may be used. Thus, Eh and Ev calculations for the green samples may be performed with a 3×3 kernel. FIG. 151 illustrates the computation of Eh and Ev values for a Gr pixel, however, the same filter may be applied on any interpolated red or blue pixel. As illustrated, given a 5×5 array of CFA patterns with the center pixel P at row=j and column=i, the horizontal and vertical energies Eh and Ev, respectively, on interpolated red and blue positions may be computed as follows:

Ev=abs((P(j−1, i−1)+P(j−1, i)+P(j−1, i+1))−(P(j+1, i−1)+P(j+1, i)+P(j+1, i+1))
Further, as discussed above, the total energy may be the summation of Eh and Ev.

Next, horizontal and vertical filtering may be applied to the Bayer pattern to obtain the vertical and horizontal filtered values Gh and Gv, which may represent interpolated green values in the horizontal and vertical directions, respectively. The filtered values Gh and Gv may be determined using a low pass filter on known neighboring green samples in addition to using directional gradients of the adjacent color (R or B) to obtain a high frequency signal at the locations of the missing green samples. For instance, with reference to