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DUBLIN, Calif., July 04, 2016 – FinScale Incorporated, the semiconductor device and process innovation company, today announced the formation of its pre-competitive industrial and academic partner program aimed at accelerating development and adoption of its Vertical Super-Thin Body (VSTB) family of 3D, non-planar electron devices that offers unique technology scaling benefits for 75% of semiconductor market applications.

“FinScale is now offering cost- and risk-shared, off-site access for semiconductor and equipment manufacturers to the qFinFET™ and other VSTB technologies, while preserving their opportunities to differentiate and add unique value to these breakthrough devices and processes in the future,” said Jeffrey Wolf, president and CEO of FinScale. “Through partnerships with independent research fabrication facilities and academia, FinScale is promoting rapid development of a broad technology platform offering performance, scaling, power-efficiency, cost-reduction and unprecedented heterogeneous integration advantages for the semiconductor industry, including: HP to ULP logic, SRAM, DRAM, flash, BiCMOS, analog/mixed-signal, image sensors, and electrostatic discharge protection.”

Projects within the program are being defined and staffed on a first-come, first-served basis, with scheduled kick-off in October, 2016. Interested parties may contact FinScale to request a briefing or more information.

About FinScale

FinScale Inc. invents, develops and licenses advanced technologies for the semiconductor industry that extend the life of Moore’s Law. Inventors of the VSTB, Quantum FinFET and qFinFET™ technologies, FinScale is a San Francisco Bay area startup founded in 2014 by semiconductor scientists and engineers with decades of global experience in advanced technologies, process integration, device design and optimization for performance and yield. Visit www.finscale.com.

DUBLIN, Calif., August 21, 2015 – FinScale Incorporated, the semiconductor device and process innovation company, today announced that it has received a Small Business Innovation Research (SBIR) award from the National Science Foundation (NSF). The Phase I grant funds development of in silico proofs-of-concept and performance validations of FinScale’s breakthrough qFinFET™ nanodevice architecture and manufacturing process at the 10nm, 7nm and 5nm semiconductor manufacturing technology nodes. This NSF-funded commercialization project, which began on July 1, directly addresses current obstacles to technology scaling to enable higher performance, denser and more power-efficient chips and systems that will advance future computing, storage, memory, mobile, sensor and Internet-of-Things (IoT) applications.

“The general challenge in developing nanoscale transistors is that device sizes are comparable to critical quantum physics material parameters,” said Dr. Victor Koldyaev, FinScale’s CTO, chief scientist and the principal investigator on this NSF-funded project. “To validate qFinFET’s performance we will expand the capabilities of industry-standard Technology Computer Aided Design (TCAD) modeling and simulation tools to identify and quantify the effects of 2D quantum screening and other quantum phenomena on MOSFET operation in the quasi-ballistic regime.”

FinScale’s goal for the Phase I work is to produce the compelling data set needed by semiconductor manufacturers to confidently move forward with commercialization of qFinFET technology at the 10 nm, 7 nm and 5 nm technology nodes, including optimized three-dimensional transistor specifications, fabrication process sequences, test structure designs and design-of-experiment tables to support accelerated silicon validations and ramps to mass production.

“FinScale appreciates the vision and support of the National Science Foundation for commercialization of breakthrough technologies for the semiconductor industry,” said Jeffrey Wolf, president and CEO of FinScale. “We are also proud of our qFinFET inventors, Dr. Victor Koldyaev and Dr. Rimma Pirogova, for their outstanding contributions to advancements in semiconductor manufacturing technology, science and the continuation of Moore’s Law.”

About the National Science Foundation (NSF)

The NSF Small Business Innovation Research / Small Business Technology Transfer (SBIR/STTR) program seeks to transform scientific discovery into societal and economic benefit by catalyzing private sector commercialization of technological innovations. The program increases the incentive and opportunity for startups and small businesses to undertake cutting-edge, high-quality scientific research and development. NSF makes supplemental funding opportunities available to extend and accelerate Phase I projects to the commercialization stage through matching third party investments in Phase IB awards and through Phase II commercialization awards.

About FinScale Inc.

FinScale invents, develops and licenses advanced technologies for the semiconductor industry that extend the life of Moore’s Law. Inventors of the patented Quantum FinFET and qFinFET™ technologies, the company provides device and process solutions for high performance (HP) to ultra-low power (ULP) logic, SRAM, DRAM, NAND and NOR flash memory, and system-on-chip (SoC) fabrication that are supported by technology transfer, commercialization and expert consulting services. FinScale, a San Francisco Bay area startup founded in 2014 by semiconductor scientists and engineers with decades of global experience in advanced technology development and commercialization, is headquartered in Dublin, CA with technology development in Morgan Hill, CA. Find more information or request a briefing at www.finscale.com.

LIVERMORE, Calif., July 03, 2014 – FinScale Incorporated, the semiconductor device and process innovation company, today announced immediate availability of its qFinFET™ technology, a next generation 3D MOSFET architecture and manufacturable process readily transferable to foundries and integrated device manufacturers. Crafted from the combination of many unique device and process innovations by FinScale’s scientists, the qFinFET technology offers significant improvements in performance, power efficiency and circuit density, along with substantially lower leakage, parametric variability and manufacturing costs than available advanced node FinFET and planar technology alternatives. From a device design optimized for quantum effects, ballistic transport and the nano-material properties of silicon, this quantum FinFET device architecture will scale to the end of the silicon MOSFET era.

“The technology shift from planar to 3D device architectures has opened new degrees of freedom and opportunities for new innovations,” said George Cheroff, a prominent IBM Research manager and semiconductor pioneer who envisioned and developed the first n-channel planar MOSFET process used for memory and logic circuits in computers. “The qFinFET technology elegantly combines the advantages of current FinFET and planar FD-SOI technologies, and mitigates their inherent weaknesses to provide a unifying platform that will put the semiconductor industry back on track with Moore’s Law.”

"FinScale’s qFinFET offers manufacturers a high-yield 3D process for building scalable aspect-ratio fins that can be formed without double patterning down to the 14/16 nm node, providing increased performance and transistor width (W) per unit area,” said Jeffrey Wolf, president and chief executive officer at FinScale. Resulting fin transistor topologies deliver additional area reductions, and provide designers with further area-saving and performance-boosting opportunities to differentiate at the cell library and circuit level when integrated with leading middle-of-line (MOL) technologies.

“We conceived the Quantum FinFET by pushing silicon to its quantum scaling limits, while seeking tomaximize carrier mobility, electrostatic gate control, yield and reliability,” said Dr. Victor Koldyaev, Finscale’s chief technology officer. “Using this approach we designed the qFinFET front-end-of-line (FEOL) device and process solution for the 7 and 10nm generations, and were pleased that the same device concept would significantly boost parametric performance and economic returns for manufacturers back to the 28/32nm node. We then laid out standard cells, SRAMs, eDRAMs and 2-bit/cell non-volatile memories using industry standard design rules and realized that we could readily exceed the best published results at those nodes and give manufacturers and designers opportunities for further improvement.”

The qFinFET technology offers unique benefits for foundries and integrated device manufacturers. The included high density and high performance logic and memory configurations, along with inherent low-noise analog/RF device characteristics, make qFinFET a robust SoC platform, either on bulk or SOI substrates. Standalone DRAM, flash and SRAM memory designers and manufacturers can configure the included bit cells into dense arrays, and build dense, highly reliable sense amplifiers and low-leakage pass transistors.

FinScale will be presenting its qFinFET technology at the Silicon Innovation Forum (www.semiconwest.org/SIF) at the SemiconWest conference on July 8, 2014 in San Francisco at the Moscone Center. CEO Jeffrey Wolf will present FinScale’s investor pitch at 10:15am in the North Hall, room 134. Then from 4:00pm to 6:00pm Mr. Wolf and Dr. Victor Koldyaev will be presenting posters at the Silicon Innovation Forum Showcase and Reception.

For more information or to request a briefing on qFinFET technology, click here.