The software does not impose any limits; however, developers need to be sure the chipset’s design specs are not violated. The minimum pixel clock frequency supported and validated on the Intel® System Controller Hub US15W chipset is 20 MHz. The minimum standard active resolution is therefore 640x480 @ 50 Hz vertical refresh, which equates to ~20 MHz pixel clock. It may be possible to pad the horizontal and vertical blanking and adjust the refresh rate higher to get a lower resolution at the minimum 20 MHz pixel clock, but that is something that needs to be explored with the LCD panel manufacturer.

2. What is the minimum and maximum custom active resolution supported by the integrated LVDS display controller on the Intel® System Controller Hub (Intel® SCH) US15W chipset and the Configuration EDitor (CED)?

Theoretically, any timing mode that yields a pixel clock frequency between 20 MHz and 112 MHz (maximum allowable pixel clock frequency for the Intel SCH US15W chipset internal LVDS controller) can be supported by Intel® Embedded Graphics Driversand the Intel SCH US15W chipset. To determine if a particular timing mode can be supported, use the following formula to determine the pixel clock frequency, and then determine if it is between 20 MHz and 112 MHz:

The maximum pixel clock frequency supported by the Intel SCH US15W chipset SDVO interface is 160 MHz. The maximum standard active resolution is therefore 1920x1080 @ 60 Hz vertical refresh, which equates to ~148.5 MHz pixel clock. Common high resolutions, such as 1600x1200 and 1280x1024, are also supported since they possess pixel clock rates less than 160 MHz.