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AR# 33874

Aurora 8B10B v5.1 - Timing simulation issues

Description

Either No CHANNEL_UP or a Data integrity check failure is observed during timing simulation.

Solution

1. Comment the following line in the UCF.

NET frame_check_i/* TIG;

Data integrity check feature is implemented in FRAME_CHECK module. Ignoring this module for timing (i.e. TIG) contributes signals timing mismatch. Uncommenting the FRAME_CHECK module TIG in UCF will assist the PAR to include for timing analysis.

2. GT REFCLK period in UCF differs with GT REFCLK period of DEMO_TB because of rounding of digits. This results in a HARD_ERROR in timing simulation which eventually leads to reinitializing the design repeatedly.

To work around this issue, use the GT REFCLK value period from UCF for CLOCKPERIOD_1 and CLOCKPERIOD_1 parameters/constants in DEMO_TB.

3. Make sure all the transceivers are placed continuously in multi-lane design. This helps ISE software tools meet timing easily.