This is huge. (And it's a huge cost-saver -- IBS estimates per-die FD-SOI cost is about half that of bulk - see...
Intel looked at both...SOI and bulk...
Immersion lithography and double patterning will be used where necessary, and no extra mask layers are needed so the additional cost is only 2 - 3%. And apparently it's scalable to 14 nm!
This story is 18 months and you keep repeating the same thing (significantly lower cost) over and over again -
any real data - like comparison in $/Euro and cent?
http://www.electroiq.com/blogs/chipworks_real_chips_blog/2011/05.html
Intel details 22nm trigate SoC process at IEDM
December 11, 2012 12:23 PM by Dick James
http://www.electroiq.com/blogs/chipworks_real_chips_blog.html

If more IEDM attendees had the opportunity to view the concurrent FD-SOI conference papers, acceptance would definitely have been faster. The IEDM people won't advertise the FD-SOI meeting, so unless you were already in the FD-SOI community, you'd never know. You wouldn't be able to "convert" supporters from outside, who had been attending IEDM without knowledge of FD-SOI. So, this low profile has been deliberate, for so long?

it looks like everbody's discovering now fdsoi qualities in cost saving, higher speed and power improvements. funny !
this discovery was under your eyes guys but you just didn't see it, growing for years...
Now the choice seems clear, and even bohr at the end of his career should recognise its mistake : he should have chosen fdsoi at 22nm in 2011 indeed.

ST also said of FD-SOI: Silicon-verified process technology delivers 30% higher speed and up to 50% improvement in power. This is huge. (And it's a huge cost-saver -- IBS estimates per-die FD-SOI cost is about half that of bulk - see http://www.advancedsubstratenews.com/2012/11/ibs-study-concludes-fd-soi-most-cost-effective-technology-choice-at-28nm-and-20nm/)
re: timing. Also note that the SOI Consortium as been running these symposia around major conferences for going on 4 yrs now. They are alway lively and well-attended. The papers are typically posted on fully-depleted section of their website (www.soiconsortium.org) shortly after.

No mystery or politics. Peter's analysis--that the key folks are at IEDM--is correct, as usual. His follow-on question is also easy to answer: the results presented by ST were hot off the presses (and testers). ST wasn't in position to respond to the Call for Papers early this year, when the call went out.
(Full Disclosure: I am ST's director of technical media relations)

I would take it to be not a political statement but a practical move. Many of the key engineers and engineering managers that can shape the adoption of FDSOI would be present at IEDM.
Of course you could ask why the four papers presented at the FDSOI meeting were'nt just offered up to IEDM for inclusion that meeting.
That said, the four 30-minute papers presented yesterday evening did look interesting to judge by the titles. They included one on FD 14-nm for FPGAs from Jeff Watt of Altera

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