Torben Ęgidius Mogensen wrote:
[snip]>> An approach using a JIT compiler that collects profiling information> before compiling could work. This way, you can use an intermediate> form that has little or no scheduling information and let the JIT> compiler schedule for the actual VLIW parameters and profile. If you> regularly reprofile and recompile code, you can reschedule a program> while it runs. I believe the Transmeta processors use something like> this internally.>> Torben