Improved Productivity

Customers can continue taking advantage of Altera’s proven software tools, which deliver industry-leading compile times. As part of the Spectra-Q engine, the TimeQuest Timing Analyzer has been upgraded with new algorithms that result in a 2x speed up in timing analysis.

In this release, Altera continues to expand its optimized IP offering with the latest standard-based cores to enable maximum design productivity. The Quartus II software v15.0 introduces new the Hybrid Memory Cube and HDMI 2.0 MegaCore® functions for the company’s Arria® 10 FPGAs and SoCs. The portfolio also includes an upgrade in features and device support for the company’s popular JESD204B core to update Arria V support to 9.225 Gbps as well as Cyclone® V support up to 5 Gbps. IP debug toolkits for external memory interfaces (EMIF) and PCI Express are also available to help designers rapidly prototype and expedite qualifications with additional access points to perform test and debug on IP cores. For more details, visit the What’s New in IP page.

Improved Performance

The Spectra-Q engine also enables a Hybrid Placement feature that uses advanced placement algorithms for more predictable timing closure. The Hybrid Placer combines analytical and advanced annealing techniques for higher performance at high logic utilization and routing congestion.

The Quartus II software v15.0 includes the next-generation Design Space Explorer (DSE), an easy-to-use design optimization tool. It has an updated flow-oriented user interface that guides users through the tool. DSE automates the process of finding the optimal collection of Quartus II software settings for a design to help you achieve timing closure, optimize area, and reduce power consumption. This updated tool also allows users to customize the Quality of Fit metric, which can be used to judge which exploration points are better.