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Abstract:

The invention discloses a fabrication method for a surrounding gate
silicon nanowire transistor with air as spacers. The method comprises:
performing isolation, and depositing a material A which has a higher etch
selectivity ratio with respect to Si; performing photolithography to
define a Fin hard mask; etching the material A to form the Fin hard mask;
performing source and drain implantation; performing photolithography to
define a channel region and large source/drain regions; forming the Si
Fin and the large source/drains; removing the hard mask of the material
A; forming a nanowire; etching the SiO2 to form a floating nanowire;
forming a gate oxide layer; depositing a polysilicon; performing
polysilicon injection; performing annealing to activate dopants; etching
the polysilicon; depositing SiN; performing photolithography to define a
gate pattern; etching the SiN and the polysilicon to form the gate
pattern; separating the gate and the source/drain with a space in between
filled with air; depositing SiO2 to form air sidewalls; performing
annealing to densify the SiO2 layer; using subsequent processes to
complete the device fabrication. The invention is compatible with the
CMOS process flow. The introduction of the air sidewalls can effectively
reduce the parasitic capacitance of the device, and improve the transient
response of the device, so that the method is applicable for a logic
circuit with high performance.

Claims:

1. A fabrication method for a surrounding gate silicon nanowire
transistor with air as spacers, characterized in that, the transistor is
fabricated on a SOI substrate, and the method comprises the following
steps: 1) performing an isolation process; 2) depositing a material A
having a relatively high etching selectivity ratio with respect to Si; 3)
performing photolithography to define a Fin hard mask; 4) etching the
material A and transferring a pattern of photoresist onto the material A
to form the Fin hard mask; 5) performing source and drain implantation;
6) performing photolithography to define a channel region and
source/drain large regions; 7) etching the silicon by using the
photoresist and the Fin hard mask of the material A as barriers, so as to
form the Fin and the large source/drains; 8) removing the hard mask of
the material A; 9) performing oxidization to form a nanowire; 10) etching
the SiO2 through isotropic wet etching to form a floating nanowire;
11) forming a gate oxide layer; 12) depositing a polysilicon; 13)
performing polysilicon implantation; 14) performing annealing to activate
dopants; 15) etching the polysilicon until the polysilicon thickness on
the source/drain is around 30 to 50 nm; 16) depositing SiN; 17)
performing photolithography to define a gate pattern; 18) etching the SiN
and the polysilicon and transferring the pattern of the photoresist onto
the polysilicon to form the gate pattern; 19) etching the polysilicon
through isotropic dry etching or isotropic wet etching, to separate the
gate and the source/drain with a space in between filled with air; 20)
depositing SiO2 to form air sidewalls; 21) performing annealing to
densify the SiO2 layer; 22) using CMOS backend processes to complete
the device fabrication.

2. The fabrication method of claim 1, characterized in that, in the step
1), the isolation is a silicon island isolation or a local oxidation of
silicon.

3. The fabrication method of claim 1, characterized in that, in the steps
4), 7), 15) and 18), an anisotropic dry etching technology is adopted.

4. The fabrication method of claim 1, characterized in that, in the step
5), an implantation with an angle of 0 degree is used.

5. The fabrication method of claim 1, characterized in that, in the step
8), the SiN is removed by a concentrated phosphoric acid at 170.degree.
C.

6. The fabrication method of claim 1, characterized in that, in the step
9), a dry oxidation or a wet oxidation is adopted.

7. The fabrication method of claim 1, characterized in that, in the step
10), the SiO2 is removed by using a hydrofluoric acid.

8. The fabrication method as in claim 1, characterized in that, in the
step 11), the SiO2 dielectric layer is formed by a dry oxidation, or
other dielectric layer with a high dielectric constant.

9. The fabrication method as in claim 1, characterized in that, in the
steps 2), 12), 16) and 20), a chemical vapor deposition method is
adopted.

Description:

FIELD OF THE INVENTION

[0001] The invention refers to a field of ultra large scale integrated
(ULSI) circuit fabrication technology, particularly relates to a
fabrication method for a surrounding gate silicon nanowire transistor
with air as spacers.

BACKGROUND OF THE INVENTION

[0002] As the feature size of a CMOS device gradually shrinks, it enters
into a deep submicron and a nanometer regime. However, its parasitic
capacitance, especially a fringing parasitic capacitance between a gate
and a source/drain (FIG. 1), may not shrink correspondingly, which
accounts for an increasing proportion in the total capacitance, resulting
in a severe influence on the transient response of the device.

[0003] On the other hand, short channel effect (SCE), which manifest
itself as the threshold voltage roll-off, increased subthreshold slope
and subthreshold leakage current etc., has become an important issue,
when the device enters into a deep submicron regime In order to mitigate
SCE, a conventional planar transistor can be reformed by a novel
structure. Due to a surrounding gate structure and a channel diameter in
nanometer regime, a surrounding gate silicon nanowire transistor has a
very excellent capability in controlling the short channel effect, which
is a promising novel device structure to replace the conventional planar
transistor in the case of a very short channel. Since the channel
diameter of the surrounding gate nanowire transistor is in a nanometer
regime, its intrinsic capacitance is very small, however, the fringing
capacitance from the gate to the source/drain is comparatively large
(FIG. 2). As a result, the parasitic capacitance has more significant
influence on the transient response compared with that of the planar
transistor.

[0004] The fringing capacitance between the gate and the source/drain
region can be reduced by using material with a low dielectric constant as
spacers. Since the air has a very low dielectric constant, it can be
perceived that the surrounding gate nanowire transistor using air as
sidewalls will has smaller parasitic capacitance. FIG. 3 is a schematic
diagram of a surrounding gate nanowire transistor using conventional
SiO2 spacers and air spacers. FIGS. 4 and 5 are the cross section
views of the device taken along the line AA' and line BB'. FIGS. 6(a) and
6(b) are the schematic diagrams of the surrounding gate nanowire
transistor with a channel length of 20 nm, a nanowire diameter of 10 nm,
and a spacer thickness of 10 nm using conventional SiO2 spacers and
air spacers, respectively. FIG. 6(c) is the comparison of their gate
capacitances, and it is shown that the parasitic capacitance is largely
reduced by using air spacers.

[0005] So far, the experiment research on the surrounding gate nanowire
transistor is mainly focused on the process integration, electrical
characterization, and device optimization to reduce parasitic resistance.
However, there is no report on the optimization for parasitic capacitance
in this device. Furthermore, due to a special three dimensional structure
of the nanowire, how to form air sidewalls needs a special design of
process flow. And this has not been reported by now.

SUMMARY OF THE INVENTION

[0006] A purpose of the present invention is to provide a fabrication
method for a surrounding gate silicon nanowire transistor with air as
spacers, the transistor is fabricated on a SOI (silicon-on-insulator)
substrate.

[0007] A technical solution proposed by the present invention is as
follows:

[0008] A fabrication method for a surrounding gate silicon nanowire
transistor with air as spacers is characterized in that, the transistor
is fabricated on a SOI (silicon-on-insulator) substrate, and the method
comprises the following steps:

[0009] 1) Performing an isolation process;

[0010] 2) Depositing a material A (such as, SiN, SiO2, etc), which
has a high etching selectivity ratio with respect to Si;

[0011] 3) Performing photolithography to define a Fin hard mask;

[0012] 4) Etching the material A, transferring a pattern of photoresist
onto the material A to form the Fin bar hard mask;

[0013] 5) Performing source and drain implantation;

[0014] 6) Performing photolithography to define a channel region and large
source/drain regions;

[0015] 7) Etching the silicon using the photoresist and the Fin hard mask
of the material A as barriers, so as to form the Si Fin and the large
source/drains;

[0016] 8) Removing the hard mask of the material A;

[0017] 9) Performing oxidization to form a nanowire;

[0018] 10) Etching the SiO2 through isotropic wet etching to form a
floating nanowire;

[0019] 11) Forming a gate oxide;

[0020] 12) Depositing a polysilicon;

[0021] 13) Performing polysilicon implantation;

[0022] 14) Performing annealing to activate the dopants;

[0023] 15) Etching the polysilicon until the polysilicon thickness on the
source/drain is around 30 to 50 nm;

[0024] 16) Depositing SiN;

[0025] 17) Performing photolithography to define a gate pattern;

[0026] 18) Etching the SiN and the polysilicon, transferring the pattern
of the photoresist onto the polysilicon to form the gate pattern;

[0027] 19) etching the polysilicon through isotropic dry etching or
isotropic wet etching, to separate the gate and the source/drain with a
space filled with air therein;

[0031] In the step 1), the isolation is a silicon island isolation or a
local oxidation of silicon. In the steps 4), 7), 15) and 18), an
anisotropic dry etching technology is adopted. In the step 5), an
implantation with an angle of 0 degree is adopted. In the step 8), the
SiN is removed by a concentrated phosphoric acid at 170° C. In the
step 9), a dry oxidation or a wet oxidation is adopted.

[0032] In the step 10), the SiO2 is removed by using a hydrofluoric
acid.

[0033] In the step 11), the SiO2 dielectric layer is formed by a
dry-oxygen oxidation, or other dielectric layer with a high dielectric
constant.

[0034] In the steps 2), 12), 16) and 20), a chemical vapor deposition
method is adopted.

[0035] In the step 19), an isotropic dry etching or an isotropic wet
etching is adopted.

[0036] The invention has the following advantageous effects in that, the
fabrication method for a surrounding gate silicon nanowire transistor
with air as spacers according to the invention is compatible with the
CMOS process flow. The introduction of the air spacers can effectively
reduce the parasitic capacitance of the device, and improve the transient
response of the device, so that the method is applicable for a logic
circuit with high performance.

BRIEF DESCRIPTION OF THE DRAWINGS

[0037] FIG. 1 is a schematic diagram of a fringing capacitance between a
gate and a source/drain.

[0038] FIG. 2 is a schematic diagram of a fringing capacitance of a
surrounding gate silicon nanowire device.

[0039] FIG. 3 is a surrounding gate silicon nanowire device with SiO2
and air as spacers. FIG. 4 is a cross section view of a surrounding gate
silicon nanowire device with SiO2 and air as spacers taken along the
line AA'.

[0040] FIG. 5 is a cross section view of a surrounding gate silicon
nanowire device with SiO2 and air as spacers taken along the line
BB'.

[0041] FIGS. 6(a) and 6(b) are the schematic diagrams of the surrounding
gate nanowire using SiO2 spacers and air spacers, respectively. FIG.
6(c) is a graph showing their gate capacitance.

[0042] FIGS. 7 to 16 are process flow diagrams of an embodiment, in which
reference numbers of the respective material layer are as follows:

[0044] The invention is further described with reference to the accompany
drawings and specific embodiments.

Embodiment 1

[0045] Starting from a SOI substrate (Si having a thickness of 2500 Å
on a buried oxide layer), sequentially performing the following steps:

[0046] 1. A silicon island isolation method is adopted;

[0047] 2. A SiN with a thickness of 1500 Å is deposited by using a low
pressure chemical vapor deposition (LPCVD);

[0048] 3. Photolithography is performed to define a Fin hard mask;

[0049] 4. The SiN is etched by 1500 Å through a reactive ion etching
(RIE) technology, and then the photoresist is removed by cleaning, as
shown in FIG. 7;

[0050] 5. An As implantation is performed with a 0° angle, an
energy of 50 KeV, and a dosage of 4×1015 cm-2, as shown
in FIG. 8;

[0051] 6. A photolithography is performed to define a channel region and
large source/drain regions;

[0052] 7. The Si is etched by 2500 Å through inductively coupled
plasma (ICP), by using the photoresist and the SiN Fin hard mask as
barriers, so that the Fin and the large source/drain are formed, and is
then cleaned to remove the photoresist, as shown in FIG. 9;

[0053] 8. The SiN is selectively etched by a concentrated phosphoric acid
at 170° C., and the SiN hard mask is completely removed;

[0054] 9. A dry-oxygen oxidation is performed to form a silicon nanowire;

[0055] 10. The SiO2 formed by the dry oxidation is etched by a
buffering hydrofluoric acid, to form floating silicon nanowires;

[0056] 11. The gate is oxidized to form a gate oxide layer with a
thickness of 5 nm;

[0057] 12. A polysilicon with a thickness of 4000 Å is deposited by
using a low pressure chemical vapor deposition (LPCVD), as shown in FIG.
11;

[0058] 13. An As implantation is performed with an energy of 80 KeV and a
dosage of 8×1015 cm-2;

[0059] 14. A rapid thermal processing (RTP) is performed for 10 s in
nitrogen, at a temperature of 1050° C., to activate dopants;

[0060] 15. The polysilicon is etched by a reactive ion etching (RIE) by a
thickness of 3700 Å-3500 Å, as shown in FIG. 12;

[0061] 16. A SiN with a thickness of 500A is deposited by using a low
pressure chemical vapor deposition (LPCVD);

[0062] 17. Photolithography is performed to define a gate pattern;

[0063] 18. The SiN is etched by 500 Å through a reactive ion etching
(RIE), and the polysilicon is etched through inductively coupled plasma
(ICP) until the polysilicon over the source/drain is etched and cleaned,
as shown in FIG. 14;

[0064] 19. The polysilicon is etched through isotropic etching by a HNA
solution to separate the gate and the source/drain with a space in
between filled with air;

[0065] 20. A SiO2 with a thickness of 4000 Å is deposited by
using a low pressure chemical vapor deposition (LPCVD) to form air
spacers;

[0066] 21. A rapid thermal processing (RTP) is performed for 5 s in
nitrogen, at the temperature of 1050° C., to densify the oxide
layer;

[0067] 22. Photolithography is performed to define a metal contact hole;

[0068] 23. The SiO2 is etched by 4000 Å through a reactive ion
etching (RIE), the SiO2 remained in the hole is etched by a
buffering hydrofluoric acid, and the phoresist is cleaned;

[0072] 27. An annealing is performed for 30 minutes in N2+H2, at
a temperature of 430° C., and an alloying is performed to
accomplish the device fabrication.

Embodiment 2

[0073] As compared with embodiment 1, the difference is in the following
steps:

[0074] 1. A LOCOS isolation method is used;

[0075] 2. A SiO2 with a thickness of 1500 Å is deposited by using
a low pressure chemical vapor deposition (LPCVD);

[0076] 4. The SiO2 is etched by 1500 Å through a reactive ion
etching (RIE) technology, and the photoresist is removed by cleaning;

[0077] 7. The Si is etched by 2500 Å through inductively coupled
plasma (ICP), using the photoresist and the SiO2 Fin hard mask as
barriers, so that the Fin and the large source/drain are formed, and then
the photoresist is removed by cleaning;

[0078] 8. The SiO2 is selectively etched by a buffered hydrofluoric
acid (BHF) at 170° C., and the SiO2 hard mask is completely
removed;

[0079] 9. A wet oxidation is performed to form a silicon nanowire;

[0080] 10. The SiO2 formed by wet oxidation is etched by a buffered
hydrofluoric acid (BHF) to form a floating silicon nanowire.