RNET has proposed the development of technologies that can be utilized to determine whether a particular electronic component is counterfeit, defective, or non-conforming. The purpose is to develop a set of methods to identify affected electronics whether they have recently entered the supply chain or have been integrated as part of a system. RNET is planning to utilize unique signatures obtained through the manipulation of device parameters to identify whether a device is acceptable or not. Approved for Public Release 14-MDA-8047 (14 Nov 14)

A major limiting factor in HPC growth is the requirement to parallelize codes to leverage emerging architectures, especially as single core performance has plateaued and architectures like short vector units (e.g., AVX), Intel Xeon Phi, and GPUs are embraced by hardware manufactures. The proposed SIMD/SIMT vectorization tools for emerging accelerator-based compute architectures will impact a world-wide range of academic, government, and commercial researchers.
The Geant4 toolkit enables the simulations of the passage of particles through matter. As with many scientific codes, it was originally developed for single processor compute nodes using compute clusters, and has not been optimized for SIMD/SIMT architectures (e.g., many-core nodes, GPUs, short vector units, and other Application Processing Units, e.g., Intel Xeon Phi. Therefore, optimizations and code rewrites are required to target each new architecture.
This project will develop two tools to aid in the parallelization of compute applications for SIMD/SIMT architectures. The first tool will perform a dynamic analysis to determine the potential to extract SIMD/SIMT parallelization from an application. The second tool will be a Domain Specific Language (DSL) designed to aid in the SIMDization of control dependent application components. The DSL compiler will automatically generate a SIMD/SIMT optimized code version targeted at the compute architecture of interest (e.g., GPU, SIMD Vector Units like AVX, or Intel Xeon Phi). Initial development and experiments will be developed for Geant4.

MapReduce is a very popular data analytic framework that is widely used in both industry and scientific research. Despite the popularity of MapReduce, there are several obstacles to applying it for developing some commercial and scientific data analysis applications. The project will develop a Native data FOrmat MapREDuce-like framework, iNFORMER, based on OSUs SciMate architecture. The framework allows MapReduce-like applications to be executed over data stored in a native data format, without first loading the data into the framework. This addresses a major limitation of existing MapReduce-like implementations that they require that data be loaded into specialized file systems, e.g., like the Hadoop Distributed File System (HDFS). The overheads and additional data management processes required for this translation can prevent MapReduce from being used in many commercial and scientific environments. Commercial Applications and Other Benefits: There are two large classes of users will benefit from the iNFORMER product. The first are current users of MapReduce-like frameworks. MapReduce is used extensively in commercial applications and is a major component of many Cloud infrastructures. As an example of the extensive use of MapReduce, the linkedin group Hadoop Users currently has more than 30,000 members. The second class of customers that will benefit from iNFORMER includes users who currently use alternative data layouts and desire to use a MapReduce-like framework. These users are likely to currently process this data using alternative frameworks, as the overhead to convert the data into a format suitable format for MapReduce processing is too expensive. Therefore, we expect a subset of these users to be interested in iNFORMER. There are extensive users of these low-level data formats who will be potential customers. For instance, users of HDF and NetCDF users including groups from academia, industry, and national laboratories who could potentially benefit from iNFORMER. HDF is used by over 600 organizations, with over 200 different data types, and millions of users.

Current ground penetrating radar based root analysis techniques have been mainly targeted for coarse root analysis. In order to extend the GPR technology to fine root analysis, it is necessary to design an unconventional GPR system that provides root information in the entire area under observation with greater accuracy and penetration depth. Specialized signal/image processing algorithms applicable to fine root analysis need to be devised. In addition, a compact hardware system consisting of the GPR system integrated with the algorithms that can be readily deployed on the field is required. The proposed work will develop a GPR-based system with the accuracy and penetration depth necessary for fine root analysis. The system will be mountable on a push cart in order to collect information about root structure in an area of interest. The root analysis capabilities of the system shall include 1) real- time visualization to quickly inform the operator about the conditions of the soil 2) state-of-the-art post processing to provide the user with detailed 3D image reconstructions, root distribution information, and statistical analysis. Commercial Applications and Other Benefits: The proposed GPR system offers the potential to be easily deployed by domain non-specialist with any RADAR background or expertise. As such, biologist, horticulturist, and life scientist will benefit from the successful commercialization of this technology for a variety of scientific studies and assessments, as well as a planning tool prior to development of an area.

A circuit monitors an electronic circuit for the effects of extreme temperatures, high Total Ionizing Dose (TID), very low (down to sub-threshold) supply voltages, process variations, and other performance altering phenomena. The circuit then generates signals that are applied to the electronic circuit to compensate for these effects. The design generates voltages that are applied to either body terminals of semiconductor technologies (e.g. MOSFET, CMOS, SOI, and others) or bottom gates of independently double gated technologies to provide compensation. The design includes a reference circuit that is adjusted until its performance is restored. The signals found that compensate the reference circuit are applied throughout the IC.