byucc.jhdl.DRC.Rules
Class ClockWires

This class implements a DesignRule for checking that implicit and explicit
clocks are not being mixed.
We differentiate in this manner:
A part that uses a clock that is not passed a clock wire explicitely
will have the following trait(s):
- The clock that it uses will be the same as what the "getDefaultClock()" returns
A part that uses a clock that is passed a clock wire explicitely will have
the following trait(s):
- One of the cell_interface ports will be a "clock" port
-OR-
- One of the cell_interface ports will be an "input" port AND the wire
going into that port will be a clock wire.
-OR-
**- The wire coming in the cell's port of type "clk" will be different than the getDefaultClock() wire
A clock wire is distinguishable in the following way(s):
- It is used in a "setClockDriver()" call
-OR-
- It ever goes into a clock port in *any* cell
-OR-
- It is assigned a location property that is the clock pin on the target architecture (this can be a difficult thing to track)
This rule fails under one of the following conditions:
- An explicit clock wire exists, and one or more parts use the implicit global clock
-OR-
- There exists a part that uses a clock that is not explicitely passed a clock wire -AND- there exists a part that uses a clock that is explicitely passed a clock wire
-OR-

sortCell

This method is called by the DesignRuleChecker for each
descendant of the top-level cell.
This sorting is done right before the doCheck method is called.
This method will only look at the cell to see if it has a clock
port. If the cell has a clock port, this method will store the
clock wire connected to it in the WireList clockWires. This
method also indirectly places all of the Cells with clock ports
connected to a clock wire in cellsWithClockPorts.