FDSOI gains three design wins

LONDON  STMicroelectronics has three design wins for its 28-nm fully-depleted silicon on insulator (FDSOI) manufacturing process.

Carlo Bozotti, CEO, told financial analysts here that in the first quarter ST has signed up two customers for digital ASICs for communications networking using the process and has a third customer that plans to address high volume consumer electronics. Bozotti did not provide the names of the customers but said that Globalfoundries Inc. (Milpitas, Calif.) has signed an agreement to bring up the process and act as a second source.

The ultra-thin body and buried oxide (UTBB) FDSOI planar process is claimed to have advantages over other manufacturing process variants, such as bulk planar CMOS and FinFET CMOS in terms of trade-offs between performance, power consumption and manufacturability. One concern has been the cost and availability of the specialized SOI wafers but ST claims that the simple nature of the process compared with FinFETs makes the total cost of production advantageous. ST has pioneered the process, although major semiconductor IDMs and foundries are working on the premise that bulk CMOS at 20-nm will be quickly followed by FinFET manufacturing at about 16- or 14-nm. Intel introduced the first FinFET process at 22-nm.

FDSOI was available for pre-production from its Crolles 300-mm wafer facility in December 2012. However, the company has been faced by a potential chicken-or-egg problem. Concern was expressed that some customers would hold off from signing up for the process until they saw evidence of a supporting ecosystem and foundries and EDA and software IP providers  such as Cadence, Synopsys and ARM  declining to commit until they could see ST had customers for the process.

"We now formally have a second source available to us and to a number of our competitors, but not all," said Bozotti.

Jean-Marc Chery, chief manufacturing and technology officer, told the analysts that ST products based on FDSOI will have an advantage over products produced in either bulk CMOS or FinFET process. "And we are winning ASIC business thanks to the performance-power and because its a simpler process than FinFET. The yield learning curve is the equal of bulk CMOS," he said.

Chery said ST would be able to meet customer ramp up of FDSOI products from its Crolles 300-mm wafer fab near Grenoble, France and that Globalfoundries would be in position to help with volume production at its Dresden fab in 2014. Chery showed the audience that the next node  14-nm UTBB FDSOI  will start prototyping in 2014 or 2015 to be followed by 10-nm UTBB FDSOI in 2016 or 2017.

The relatively lower drive current of 28FD has nothing to do with thin Si channel. It's the lack of strain elements that hurts the device. Strain elements are part of 14FD and impressive HW data is already shown (at VLSI and IEDM last year), with AC performance surpassing 22nm FinFET. There is no barrier in adding such elements in a 28nm FDSOI technology, the same way there are 3 versions of 28nm bulk technology.

ST (not TS) seems to be betting the digital part of the house on FDSOI. For BigD, paricularly low power, it may actually work, as long as you don't need exotic analog IP - FDSOI gets kinky with analog.

Yes the thin silicon in FDSOI results in very very low transistor current compared to bulk transistors. The ST 28nm FDSOI current is about 50% lower compared to 28HPM.
That is a fundamental issue for circuit blocks

IBM invented PDSOI, FDSOI, ET(extremely thin) SOI technologies. The PDSOI was very successful, but FDSOI including UTBB and ETSOI are not in manufacturing at any technology node today. This is because one of the critical issues with FDSOI is its scalerability. For the 28nm FDSOI a very thin SOI thickness or transistor channel thickness of 7nm is required to suppress its transistor leakage current, while for the 28nm planer bulk the transistor channel thickness is controlled by a combination of halo and retrograded implants, providing a fully depleted and significantly deeper than 7nm. That is why the planer bulk 28nm has been in high volume manufacturing by Intel, and major foundries for over two years. ST claimed last year that its 28nm FDSOI was ready for manufacturing, but is not yet. ST's 28nm FDSOI seems to be too late to inter the 28nm node market unless its 28nm FDSOI is superier to the planer bulk 28nm. Intel's 22nm FinFETs are in high Volume manufacturing over a year. But Chery dosn't say when ST will manufacture the 22nm FDSOI even though he has claimed on FDSOI having advantage over bulk CMOS or FinFET process. For the 22nm FDSOI the SOI thickness even thinner 4.5nm is required to suppress the transistor leakage current. Comparatively, for the 22nnm FinFET the Fin widh of 22nm that is equivalent to the FDSOI thicknesses of 4.5nm is required. What a big difference! That is why Intel's 22nm FinFETs are in high volume manufacturing over a year, but not 22nm FDSOI, and having difficulties in manufacturing even 28nm FDSOI. Skim

The reason SOI is looking more attractive is the lack of value for Taiwan Semi 16. From 20 to 16 die size does not shrink (even slightly bigger for many blocks) I just don't see who is going to pay more for a wafer if die size does not shrink. By definition...there is no Moore's Law from 20 to 16.
I don't get Taiwan semi's road map anymore