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SUB

Syntax

is an optional suffix. If S is specified, the condition flags are updated on
the result of the operation.

cond

is an optional condition code.

Rd

is the destination register.

Rn

is the register holding the first operand.

Operand2

is a flexible second operand.

imm12

is any value in the range 0-4095.

Operation

The SUB instruction subtracts the
value of Operand2 or imm12 from
the value in Rn.

In certain circumstances, the assembler can substitute one
instruction for another. Be aware of this when reading disassembly
listings.

Use of PC and SP in T32 instructions

In general, you cannot use PC (R15) for Rd, or any operand.
The exception is you can use PC for Rn in 32-bit T32 SUB
instructions, with a constant Operand2 value in the range 0-4095, and no S suffix. These instructions are useful for generating
PC-relative addresses. Bit[1] of the PC value reads as 0 in this case, so that the
base address for the calculation is always word-aligned.

Generally, you cannot use SP (R13) for Rd,
or any operand, except that you can use SP for
Rn.

Use of PC and SP in A32 instructions

You cannot use PC for Rd or
any operand in a SUB instruction that
has a register-controlled shift.

In SUB instructions without register-controlled
shift, use of PC is deprecated except for the following cases:

Use of PC for Rd.

Use of PC for Rn in the instruction SUB{cond} Rd, Rn,
#Constant.

If you use PC (R15) as Rn or Rm,
the value used is the address of the instruction plus 8.

If you use PC as Rd:

Execution branches to the
address corresponding to the result.

If you use the S suffix,
see the SUBS pc,lr instruction.

You can use SP for Rn in SUB instructions,
however, SUBS PC, SP, #Constant is deprecated.

You can use SP in SUB (register)
if Rn is SP and shift is
omitted or LSL #1, LSL #2,
or LSL #3.

Other uses of SP in A32 SUB instructions are
deprecated.

Note

Use of SP and PC is deprecated in A32 instructions.

Condition flags

If S is specified, the SUB instruction
updates the N, Z, C and V flags according to the result.

16-bit instructions

The following forms of this instruction are available in T32 code, and are
16-bit instructions:

SUBS Rd, Rn, Rm

Rd, Rn and Rm must
all be Lo registers. This form can only be used outside an IT block.

SUB{cond} Rd, Rn, Rm

Rd, Rn and Rm must
all be Lo registers. This form can only be used inside an IT block.

SUBS Rd, Rn,
#imm

imm range 0-7. Rd and Rn must
both be Lo registers. This form can only be used outside an IT block.

SUB{cond} Rd, Rn,
#imm

imm range 0-7. Rd and Rn must
both be Lo registers. This form can only be used inside an IT block.

SUBS Rd, Rd,
#imm

imm range 0-255. Rd must
be a Lo register. This form can only be used outside an IT block.

SUB{cond} Rd, Rd,
#imm

imm range 0-255. Rd must
be a Lo register. This form can only be used inside an IT block.

SUB{cond} SP, SP, #imm

imm range 0-508,
word aligned.

Example

SUBS r8, r6, #240 ; sets the flags based on the result

Multiword arithmetic examples

These instructions subtract one 96-bit integer contained in R9, R10,
and R11 from another 96-bit integer contained
in R6, R7, and R8,
and place the result in R3, R4,
and R5:

SUBS r3, r6, r9
SBCS r4, r7, r10
SBC r5, r8, r11

For clarity, the above examples use consecutive registers
for multiword values. There is no requirement to do this. The following,
for example, is perfectly valid:

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