Flash memory 101: An Introduction to NAND flash

For many consumer audio and video products, NAND flash memory is a better storage choice than a hard drive, especially in low-capacity applications (4 Gbytes or less). As the quest continues for lower power, lighter, more robust products, NAND is proving to be very attractive.

The NAND flash array is grouped into a series of 128-kbyte blocks, which are the smallest erasable entity in a NAND device. Erasing a block sets all bits to "1" (all bytes to FFh). Programming is necessary to change erased bits from a 1 to a 0. The smallest entity that can be programmed is a byte. Some NOR Flash memory can perform read-while-write operations (Fig. 1). Although NAND can't perform read and write simultaneously, it can accomplish this at a system level using a method called shadowing, which has been used on PCs for years by loading the BIOS from the slower ROM into the higher-speed RAM.

NAND efficiencies are due to the lack of metal contacts in the NAND string. NAND flash cell size is smaller than NOR, 4F2 verses 10F2, due to the fact that NOR cells require a separate metal contact for each cell.

NAND is similar to a hard-disk drive. It's sector-based (page-based) and suited for storing sequential data such as pictures, audio, or PC data. Although random access can be accomplished at the system level by shadowing the data to RAM, doing so requires additional RAM storage. Also, like a hard disk, NAND devices have bad blocks, and require error-correcting code (ECC) to maintain data integrity.

Due to the decrease in die area resulting from the small cell size, NAND provides the larger capacities required for today's low-cost consumer market. NAND flash is used in almost all removable memory cards. NAND's multiplexed interface provides a similar pin-out for all recent devices and densities. This pin-out lets designers use small densities and migrate to larger densities without any hardware changes to the pcb.

Fig. 1. The figure shows a comparison of various flash cells.

NAND vs. NOR
NAND's advantages are fast write (program) and erase operations, while NOR's advantages are random access and byte write capability (Fig. 2). NOR's random access ability allows for execute in place (XiP) capability, which is often a requirement in embedded applications. The disadvantages for NAND are slow random access, while NOR is hampered by are slow write and erase performance. NAND is better suited for file applications. However, more processors include a direct NAND interface and can boot directly from NAND (without NOR).

Fig. 2. The random access time for NOR flash is specified at 0.12 ?s, whereas NAND random access is significantly slower for the first byte. Once the initial access is made, however, the remaining 2111 bytes are shifted out of NAND at only 0.03 ?s/byte.

The real benefits for NAND are faster program and erase times, as NAND provides over 5 Mbytes/s of sustained write performance. The block erase times are an impressive 2 ms for NAND versus 750 ms for NOR. Clearly, NAND has several significant positive attributes. However, it's not well-suited for direct random access.

NOR flash requires around 41 I/O pins for a 16-bit device, while NAND devices requires only 24 pins for a comparable interface. This pin savings comes from NAND's multiplexed command, address, and data bus. A benefit of the multiplexed interface is that larger NAND devices can be supported using the same hardware design and pcb. Because the common TSOP-1 package has been used for many years, this feature lets customers migrate to higher-density NAND devices on the same pcb. Another advantage of NAND is evident in its packaging options: NAND offers a monolithic 2-Gbit die or can support up to four stacked die, allowing an 8-Gbit device in the same TSOP-1 package. This enables one package and interface to support higher densities in the future.

Nice article, later I found yours slice presentation at FlashMemorySummit (2008) that give rich complementary information. However, I'm interested in Flash energy consumption to complete a fair comparison between different technologies. This parameter is normally disregarded in books and so on. Please could you (or anybody) give any clue on orders of magnitude of the static consumption (specified as current/power leakage) and dynamic consumption during random read operation.

Hi,
We need to store ECC information while writing data to NAND.
My understanding is we are doing so because, some errors might occur while reading DATA from NAND.
What will happen if error occurs while reading NAND Spare Area. Is it guaranteed that no errors occur when we read from the Spare Area?
Thank You & Regards,
GSR