Last week at the 2014 ISC (International Supercomputing Conference) it was announced that the Intel Xenon Phi processor “Knights Landing” would debut in 2015. [link] It will be manufactured by Intel using 14nm FinFET process technology and will include up to 72 processor cores that can work on up to four threads per core. It will support for up to 384 GB of on board DDR4 RAM and 16GB of Micron HMC stacked DRAM on-package, providing up to 500GB/sec of memory bandwidth. It will be the first Intel processor to use this new high performance on package memory.

The Micron 3D stacked memory which we have know as the hybrid memory cube for several years is being called “multichannel memory or MCDRAM. Micron reports that having such memory in the CPU package is expected to deliver 5X the sustained memory bandwidth versus GDDR5 with one-third the energy per bit in half the footprint.

Knights Landing is expected to be deployed in various high performance computing solutions such a as the Cray “Cori” at National Energy Research Scientific Computing (NERSC) Center.

Long time IFTLE readers recall that Intel was involved from the beginning with the concept of HMC [ see IFTLE 74, “The Memory Cube Consortium” ] and in fact shared a glimpse of the memory cube technology at their developers forum in June of 2011.[link]

So it was interesting to see the logic layer on display recently in the IBM booth at ECTC. I’m pretty sure this is it (before the memory layers are attached).

While the excitement level around this announcement will be high, we should all understand that as described this is a high end HPC application, not the high volume driver that the 3DIC world has been awaiting. The question for intel is will Intel use this as a platform to compete with nVidia and AMD/ATI on graphics, or will this be just a niche HPC product?

We should also note that although Intel has numerous patents in the area, there is no current indication that this will be a 2.5D solution. Intel has thus far only said “it will be high bandwidth.”

GS Nanotech

Anyone else surprised by the recent announcement that GS Nanotech (Kaliningrad, Russia) “plans to launch mass assembly of 3D stacked TSV microcircuits in the next few years”? I must admit I had never heard of them. A quick look at their web page indicates that they manufacture chips for General satellite set-top-boxes and have ST Micro, Nanium, Toshiba and Winbond listed as customers.

FYI – we are in the process of inviting them to speak at the RTI ASIP conference in December to see exactly what they have and what their plans are.

Updating STATSChipPAC

From our friends at Digitimes: “STATS ChipPAC, the world’s fourth-largest IC backend service company, has put itself up for sale with ASE, Changjiang Electronics Technology, Samsung and Huatian Technology (Xian) likely to compete for the sale… STATS ChipPAC has been holding talks with potential buyers since mid-May, with ASE and Changjiang being the first two contenders… Changjiang aims to enhance its manufacturing technology and patent portfolio, and to ramp up total capacity by acquiring STATS ChipPAC, noted the sources… ASE’s bid for STATS ChipPac is more likely to prevent other potential competitors from taking over STATS ChipPAC to build up capacity against ASE…” Samsung, Huatian, Foxconn, UTAC and GlobalFoundries have also been rumored to be potential acquirers. [link]

For all the latest on 3DIC and other advanced packaging solutions, stay linked to IFTLE…

Although both IBM and GF are refusing to address “rumors and speculation,” the rumors and speculation persist that the sale of IBMs semiconductor business to GlobalFoundries is imminent. The latest to comment on the expected deal is Businessweek / Bloomberg [link]

Most experts feel that GlobalFoundries is primarily interested in acquiring IBM’s engineers and intellectual property rather than the manufacturing facilities (200mm facility in Burlington VT and 300mm line in East Fishkill NY) since GF has its own state of the at capacity. GF would act as a supplier for IBM’s semiconductor needs.

Reading the Vermont Free Press articles on the subject, it is clear that IBM employees expect GF to mothball the facility. For those of you wondering why there is a semiconductor facility in VT at all I offer you the following interesting comment “IBM opened its plant in Essex Junction in 1957, largely because the late Thomas Watson Jr., former IBM chairman and CEO, liked to ski.”

Vol 3 focuses on 3D Process technology, updating the original two volumes in 2008 with all new chapters on all the relevant process steps. We have gathered many of the worlds experts to give you their insights on 2.5 / 3DIC processing and an especially strong chapter on metrology from the staff at Sematech. The bond/debond section includes chapters by Brewer, EVG, Suss, TOK , 3M and RTI. Most areas are covered by at least two different authors to give the reader a more complete perspective of what is possible. Of special interest should be the chapters “Bonding and Assembly at TSMC” by Doug Yu, “Cu TSV Stress: Avoiding Cu Protrusion and Impact on Devices” and “Implications of Stress/Strain and Metal Contamination on Thinned Die” by Kangwook Lee.

Paul Franzon of NC State, Eric Jan Marinissen and Muhannad Bakir will be editing Volume 4 which will focus on Design, Test and Thermal. We hope these volumes prove to be of value to the community.

2014 iTherm

iTherm is the Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems. The 2014 iTherm was held concurrent with the ECTC in Orlando, FL. This years General Chair was Mehdi Basheghi of Stanford and program chair was Madhusudan of Google. Attendance this year was up 50% to ~ 400.

HP

Kumari and co-workers at HP addressed “Air Cooling Limits of 3D Stacked Logic Processor and Memory Dies.” Their goal was to determine how many memory die can be integrated into a package with logic before exceeding the temp limitations of the memory die. Modeling was done for 10nm technology with 24 cores as shown below. Core power is varied from 1.5 to 3 W (red cores). Sacked memory are 0.5W DRAM.

Thermal results are shown below.

IMEC

Oprins and Beyne discussed the “Thermal Modeling of the Impact of 3D Interposer Materials and Thickness on Thermal Performance and Die-to-die Thermal Coupling.” For the test vehicle shown, they observe reducing the thermal conductivity from Si to glass results in an increase in the logic temperature and consequently a lower maximum logic power. The memory temperature at the other hand decreases for decreasing values of the conductivity since the in plane thermal coupling is reduced. This results in an increase of the allowable logic temperature. If the memory heating is included, an increase of the memory temperature can be observed for very low conductivity values.

Most applications for interposers combine high power components (logic) and temperature sensitive components (memory). Since the components are thermally coupled in the package, the logic power will be limited by either the temperature limit of the logic or memory, whichever is reached first. This means there is a trade-off between the logic self-heating and the thermal coupling which are impacted differently by the interposer material and thickness choice. It is shown that the Si interposer has a better thermal performance than the glass interposer in case only the logic temperature limit is taken into account and that the Si interposer package thermally outperforms the single chip package, the package-on-package configuration (PoP) and the 3D stacked configuration. In case the memory temperature limit and self-heating are taken into account as well, the glass interposer package has a better thermal performance for cases where the memory temperature limit memory is sufficiently lower than logic temperature limit.

For all the latest in 3DIC integration and other advanced packaging, stay linked to IFTLE…

The 16th biennial Symposium on Polymers was held this May in Wilmington DE. Keynote speakers included Steve Bezuk, Qualcomm, James Lee, Strategic Foresight Investments, John Hunt, ASE and Mark Poliks SUNY Binghamton.

In the 1990s, photo materials won out over dry etch materials because of lower COO. The processes are compared below.

The question now is – Can we do even better with laser processing ? Laser is compared to photo processing below:

High absorption of UV radiation by polymers and poor thermal conductivity of the polymer result in etch depths per pulse in the 100 nm range with little thermal diffusion. Scanning ablating allows for ablation of areas of 50 x 50mm at a time.

Materials suitable for Excimer ablation include:

Much finer vias can be produced with laser ablation, i.e 5um vias in 5um dielectric. Also since the ablation is done after cure, no polymer shrinkage occurs after the via is formed. A low cost polymeric cover layer is applied to catch debris during processing and is dissolved away after ablation.

With laser ablation non photo polymers which exhibit better thermal, mechanical and electrical characteristics than photo polymers can be used and such materials can use high loadings of nano-fillers which cannot be made photo-imageable.

ASE

John Hunt of ASE detailed “Polymer Innovations for Advanced Packaging Applications.” John pointed out that every component and interface in the package must be carefully engineered. The variety of interfaces are shown below.

Multiple disciplines are necessary to develop materials for advanced packaging as shown below for underfills:

Many polymers are required for a single application for instance for 2.5D interposers:

There is still significant room for improvement as shown below:

Hitachi Chemical / HD Microsystems

Daisaku Matsukawa of Hitachi Chemical described their attempts to produce a low temp curable, positive tone photo PI. For many years PI has been known to have excellent mechanical properties but very high curing temperatures. In the 1990s, curing temperatures of the most popular grades were 350˚C+ .

While x-linking with aliphatic and aromatic di-epoxides resulted in poor films, they found that heterocyclic epoxides resulted in materials with good PCT resistance and adhesion at low cure temperatures, i.e. 150 – 200˚C. Material properties are shown below:

IFTLE notes: while the curing temperature has gone down into todays preferred range of less than 200˚C the mechanical properties, once the main PI benefit, now look a lot like BCB and the Tg of the material now more resembles low Tg epoxy than PI or BCB. It will be interesting to see if such a material gains acceptance in the marketplace.

For all the latest on 3DIC and advanced packaging, stay linked to IFTLE…

The hottest rumor at the 2014 ECTC in Orlando was that STATSChipPAC (SCP) was “in play” (about to be acquired). One version of the rumor had at least 3 bids on the company including GlobalFoundries (IFTLE finds it hard to imaging GF could swallow both IBM and SCP at the same time), ASE and “a group of un-named mainland China companies.” Inquiries to SCP contacts substantiated the rumors although they had no knowledge of the details.

Sure enough the Wall Street Journal on May 16th indicated that SCP was “considering an offer for all its shares.”

When I went straight to the source and asked for a response, SCP sent me a copy of the response they sent to the Singapore stock exchange (the rumors evidently caused the stock shares to jump.

“STATS ChipPAC Ltd (the “Company”) refers to the questions from Singapore Exchange

Securities Trading Limited (the “SGX-ST”) dated 15 May 2014, regarding the unusual price and volume movements in the shares of the Company.

The Company has received a non-binding expression of interest from a third party, with a view to a possible acquisition of all the shares in the Company subject to a number of conditions. The Company regularly conducts strategic reviews of, and considers various proposals in relation to, its business and operations with a view to maximizing shareholder value. The Company is accordingly considering this approach. There is no assurance that this approach will result in any definitive agreement or transaction. Save as set out above, the Company is not aware of any other possible explanation for the trading and the Company confirms its compliance with the listing rules, in particular, Rule 703 of the SGXST Listing Manual.

The Company will make an appropriate announcement in the event that there are any material developments on this matter. Shareholders of the Company and investors are therefore advised to exercise caution when dealing in shares in and other securities of the Company. “

CONSOLIDATION

IFTLE has written many blogs detailing how we are in a period of consolidation and how Economics 101 tells us that there is no way to stop it. Let’s take a look at what this really means. I watched this occur in the chemical industry, and I am now watching it again in the electronics industry. For those of you that are business majors, I forgive you if you skip this and go on to something else. For those of you that are “techies” working for IDMs, foundries, material or equipment suppliers, pay attention please because this concerns you.

The 4 stages of a Business Cycle (extracted from GK Deans “The Consolidation Curve,” Harvard Business Rev., 2002.):

Stage 1: In stage 1, the combined market share of the three largest companies is between 10 percent and 30 percent. Companies in stage 1 industries aggressively defend their first-in advantage by building scale, creating a global footprint and establishing barriers to entry, i.e. protecting proprietary technology or ideas. Stage 1 companies focus more on revenue than profit, working to amass market share.

Stage 2: Stage 2 is all about scaling. Major players begin to emerge, buying up competitors. The top three players in a stage 2 industry will own 15 percent – 45 percent of their market, as the industry consolidates. The companies that reach stage 3 must be among the first players in the industry to capture the most important markets and expand their global reach.

Stage 3: Stage 3 companies focus on expanding core business and continuing to aggressively outgrow the competition. The top three industry players will control between 35 percent and 70 percent of the market with five to 12 major players remaining. This is a period of large-scale consolidation plays. Companies in stage 3 industries focus on profitability and pare weak businesses units. The well-entrenched in this phase will attack underperformers. Recognizing start-up competitors early on allows market leaders to decide whether to crush or acquire them. Stage 3 companies should also identify other major players that will likely survive into the next, and final, stage and avoid all-out assaults on them which could leave both players injured.

Stage 4: In stage 4,the top three companies claim as much as 70 percent to 90 percent of the market. Large companies may form alliances with their peers because growth is now more challenging. Companies in stage 4 must defend their leading positions. They must be alert to the danger of being lulled into complacency by their own dominance.

Stage 4 companies must create growth by spinning off new businesses or buying into aligned fields to broaden their market presence.

Let’s take a look at a few examples to bring this closer to home. First, let’s look at DRAM memory consolidation. In 1980, there were 41 listed suppliers [1] whereas after the recent acquisition of Elpida by Micron we are left with 3 suppliers having > 90 percent of the market [2].

How many foundries do we expect to see moving past 22nm? TSMC, GF, Samsung and maybe. That’s it.

Some front-end IC equipment markets have recently been examined. [3] Each color below represents a different vendor and the dark grey area represents multiple small suppliers. Many of the market segments already have one to three suppliers with combined > 80 percent market share; several segments have 2 suppliers with > 90 percent market share and two segments have 1 supplier with > 75 percent share. All signs of a mature market.

So, the front end is nearing full consolidation. With 450mm stalled and scaling coming to an end this means fewer and fewer fabs moving forward with the latest equipment. What’s a front-end equipment supplier to do?

“Stage 4 companies must create growth by buying into aligned fields to broaden their market presence”

We have all watched as Applied Materials has made their move into the backend equipment sector and even tried to spread their wings a little further into the PV market (ouch!)

Will anyone be surprised as we see LAM and KLA Tencor attempting to do the same? Since the front end suppliers have the deeper pockets IFTLE has expected for a long time that they will eventually buy out back end suppliers as consolidation continues.

Lastly, let’s look at some breakouts of market share in the back end equipment space. Below I am showing a Yole look at equipment market shares in 2011 with names and percentages removed (sorry but they sell this info). We can see consolidation has already begun there as well. As stated above IFTLE expects many of these players to be bought out by the front end players over the next few years.

So whether we find out next week that SCP has been acquired, or not, my message is the same: CONSOLIDATION is underway and will likely affect you and your current employer.

Micron and TSMC?

Josephine Lien at Digitimes is reporting that “TSMC reportedly to tie up with Micron to develop 3D ICs” According to these reports, TSC will integrate Micron’s hybrid memory cube-based DRAM chips with TSMC’s logic chips “through TSV technology.” Lien continues “A successful development of the chip stack technology between DRAM and logic chips will enable TSMC to extend this technology to integrate mobile application processors and DRAM chips, and therefore will help TSMC further expand its client base.”

During the summer months ahead, IFTLE will be giving you full coverage of: