In late April, a wealth of information on IC functional verification became available at the DVCon web site. Both papers and slides are now available for dozens of high-quality presentations given at the DVCon 2012 conference, which was held Feb. 27-March 1, 2012 in Santa Clara, California. You can view the list of sessions here.

Cadence contributed heavily to DVCon this year, and what follows is a listing of Cadence-authored or co-authored papers now available for viewing and downloading. Happy reading!

Summary: I attended this paper, and found it to be a good summary that shows how equivalence checking fits into the low-power verification flow. While power formats unify intent, the paper notes, implementation and verification tools may interpret the information differently. Equivalence checking can formally prove that simulation matches the original power intent and RTL.

Summary: Mixed-signal blocks with advanced power management techniques can pass simulation but fail in silicon. This paper proposes that a static verification methodology can help catch electrical failures.

Summary: Controlling and monitoring registers and memories comprises a large part of typical functional verification projects. This paper shows how the Accellera UVM-REG register and memory package can help, and provides some practical guidelines for register management gleaned from real project experience.

Summary: This presentation provides tips and best practices using specific pointers and code examples, gathered from live projects worldwide. Topics include configuration, the objection mechanism, the register package, and transaction level modeling (TLM).

Summary: This paper shows why metric-driven verification and UVM are needed for mixed-signal verification, and presents an example based on a noise cancelling receiver block within a mixed-signal SoC. I attended and wrote a blog post about this paper.

Summary: This paper proposes a set of requirements for specifying functional coverage in an analog or mixed-signal block. It explains how the real number data type can be introduced into a SystemVerilog coverpoint specification, enabling a complete coverage specification for a mixed-signal verification environment.

Note: An audio archive of the DVCon 2012 panel, "The Resurgence of Chip Design," is available here. You can listen to individual sections of the panel or download the full MP3 file. My blog summary of the panel is located here.