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Michael (Mac) McNamara, Gen Chair 54th DAC; Pres & CEO Adapt-IPMac is the General Chair for the 54th DAC; and is President & CEO of Adapt-IP, a semiconductor IP company that is focused on wired and wireless communication IP, with an emphasis on security.
Previously, he was Cadence's VP/GM for System Level Design, which developed SystemC based Simulation, Synthesis and Virtual Platform solutions.
Mac's holds a BS’84 and ME’85 in Computer Architecture from the Electrical Engineering School at Cornell University, and his early experiences as a computer architect and chip designer in the 80’s (TRW, Cydrome, Ardent, Kubota) prepared him to develop tools for chip design. He ran the RnD team at Chronologic that delivered VCS in early 90’s, then helped bring better verification technology to the market in the late 90’s as CEO at SureFire and SVP Technology & Board member at Verisity Design. Mac is the holder of 5 patents in EDA « Less

Michael (Mac) McNamara, Gen Chair 54th DAC; Pres & CEO Adapt-IPMac is the General Chair for the 54th DAC; and is President & CEO of Adapt-IP, a semiconductor IP company that is focused on wired and wireless communication IP, with an emphasis on security.
Previously, he was Cadence's VP/GM for System Level Design, which developed SystemC based Simulation, … More »

Designer and IP track submissions are due Tuesday, January 24. These sessions have been among the most vibrant DAC elements in recent years based on attendance and anecdotal feedback. Chuck Alpert, my predecessor as DAC chair, explained why in a post last year: “Many of these technologists come for the Designer/IP track, a marketing-free zone aimed squarely at practitioners.”

The good news is that submitting is easy. All you need to do is bang out 100 words and six slides. You can do this, people!

More good news is the excellent industry pros in charge of these tracks.

Like many things, DAC looks decidedly different depending on where you sit, and how you experience it. As an attendee, it’s mostly a few days at the start of every summer where you can sample some of the best technical content on the design of circuits and systems, plus get the chance to network and have some fun with a worldwide audience that spans execs to undergrads. In contrast, as a member of the executive committee, DAC is the finish line for a year-long marathon effort to bring the best content, speakers and papers all together in one place and time, building on what works and improving where we can.

Now is the time for a reminder that if you want present a paper at DAC (especially a research paper), the 12-month calendar matters for you as well. Abstracts are due Nov. 15; manuscripts, Nov. 22! ­

I’ve been attending DAC as an exhibitor since 1992, and serving on the executive committee since 2012. I am thrilled to serve as General Chair for the 54th iteration of this grand conference. (And no it’s not too early to think about DAC; the call for contributions is open now.) Through the years I have seen some big industry changes, most driven by the increasingly powerful tools and automation that this conference has been about — growth that fueled my career, as well!

My first job was as a chip designer at TRW, Sunnyvale back in the 1980s, and we had our own fab in Virginia, and my officemate wrote and maintained our chip design tools, as was pretty typical in those days. I worked at a series of hardware startups after that; and then took all that experience in hand to build better chip design tools. At Chronologic I led the engineering team that built the VCS simulator; then I started Surefire, where we built the SureCov and SureLint verification tools; we merged with Verisity and then into Cadence, where my team developed C-to-Silicon synthesis tools. If you’re curious, LinkedIn has most of the rest of the story, including the patents I’ve been issued.

All of a sudden it’s nearly the end of April, high time to switch from months to weeks (just six to go now!) in the countdown to DAC, which I can guarantee is going to be a great conference. One big reason I’m confident is that, as always, we have an excellent lineup of keynoters as worthy of a stage at TED or SxSW as at the world’s premier design automation conference. See my past posts on Peter Stone (Thursday keynote) and Lars Reger (Monday) for a refresher. And don’t forget the luminaries sandwiched between the two of them:

Tuesday back-to-back big thinkers will take the main stage. One is Louis Scheffer, a researcher at Howard Hughes Medical Institute. Shcheffer has spent a lifetime studying whether it might be possible to reconstruct the nervous system, a challenge given the boggling complexity in even the simplest animals. The humble fly brain that Scheffer studies has about 100 million connections. The success of Scheffer and his colleagues in mapping a small fraction of those connections, the region of the fly’s brain that processes vision, warranted a 2013 publication in Nature, likely the world’s most prestigious scientific journal.Read the rest of #53DAC, 7: Fly brains, trillion-transistor devices and tales from a Steve Jobs alum

NXP Automotive CTO Lars Reger to open DAC Monday; time to register and book your hotel | There is no hotter topic in tech than self-driving cars. How else to explain the worldwide headlines after what can only be described as a modest little fender-bender last month in Mountain View. The culprit was one of Alphabet, Inc.’s autonomous Lexus 450hs, by now a media darling/goat. Despite the apparent and very prosaic facts — the Lexus was traveling 2 miles per hour, nobody was hurt, it was the first at-fault incident in more than 1.5 million miles of autonomous driving, etc. — the event was and remains a modest sensation, online and otherwise.

“Google was dealing with a pronounced shadow hanging over its presence at SXSW this week,” wrote Nick Statt last week in The Verge. “Now the fallout [from the accident] has found its way into nearly every transportation-focused panel discussion here in Austin.”

Autonomous bidding agents to robo-soccer | What good luck that Peter Stone, one of the world leaders in artificial intelligence (AI), is right here at UT Austin. Stone will give the Thursday keynote, an excellent reason for you to make sure to stay through the final day of the conference.

Every year DAC features something new. For the general chair, balancing tried and true conference elements with infusions of change is part of the art of putting on DAC and keeping it fresh. This year one change has to do with art itself — #53DAC features what I believe to be the first art show in the conference’s long history.

No, I’m not asking you to submit that painting you’ve been laboring over, perhaps with the help of last fall’s Bob Ross marathon on Twitch. Rather, this is a call for you to send in the best, most aesthetically interesting images associated with design automation today.

Examples include die photoshots of silicon designs, design floorplans and placemats, 3-D wiring or clock visualizations, lithographic images and thermal maps. But that list is just the starting point. Really, any image associated with how our community is helping to create the world’s astonishing array of electronic devices is welcome.

DAC stands for Design Automation Conference. Everyone: please stop saying “the DAC conference”. This may not be as widespread as folks calling an automated teller machine an ATM machine, but it’s still odd. But I digress…

This year, the 53rd DAC will be held in Austin, Texas starting June 5. I’ve been going to DAC for more years than I will ever put in writing. I’ve seen some marvelous things unveiled at this show. Innovations that impact IC design and manufacturing typically. This year will be different though.

The CC-100 PowerOp IP harvests waste energy (logic overlap current) in digital and mixed signal SOC’s, and recycles a portion of it back into the system for an overall lower system power profile. This IP allows users to save watts of power, depending on how much digital or dynamic power is being consumed in a given SOC, and can fit in the left-over “white space” of most SOC or processor designs.

In short, this IP turns the standard power saving techniques around, saving power when circuits turn on, thus complimenting, not competing with, standard industry techniques normally used to save power.

The CC-100 PowerOp IP has been realized in Proof-of-Concept silicon and has been produced and characterized on the IBM CM018RF RF manufacturing process.

The CC-100 PowerOp IP import is scalable to any IC process ranging from .6um to 28nm, available on request from CurrentRF Proof-of-concept, characterization, and design aid documents and boards for the CC-100 IP are also available on request.

Most associate USB and it’s hardware as a digital and system data transfer protocol only. Thinking of USB in terms of Analog and RF has only recently been a subject of interest in USB design, a necessity with the advent of USB 3 speeds and protocols. In fact, RF effects become dominant in the data transfer speeds involved with in USB 3. CurrentRF has developed a methodologies and technologies that allow server and network device USB ports, normally thought as digital and system data transfer ports, to be used as Analog/RF pickup ports for system noise and power reduction.

If one opens and ignores the data lines used for any flavor of USB, and focuses only on the resident +5V power and ground lines, one will see a rich source of RF frequencies of significant magnitude, that would enable energy harvesting techniques to be employed to recover this resident, generated energy. In fact, if one utilizes an ac coupled spectrum analyzer of sufficient bandwidth, one will not only see frequency spikes and noise related to USB data transfers, but “coupled in” frequencies and noise energies related to other aspects of servers and network devices.