2.8 Cell Compilers

The process of hand
crafting circuits and layout for a full-custom IC is a tedious, time-consuming,
and error-prone task. There are two types of automated layout assembly tools,
often known as a silicon compilers . The first type produces a specific
kind of circuit, a RAM compiler or multiplier compiler , for
example. The second type of compiler is more flexible, usually providing
a programming language that assembles or tiles layout from an input command
file, but this is full-custom IC design.

We can build a register file
from latches or flip-flops, but, at 4.5–6.5 gates (18–26 transistors) per
bit, this is an expensive way to build memory. Dynamic RAM (DRAM) can use
a cell with only one transistor, storing charge on a capacitor that has
to be periodically refreshed as the charge leaks away. ASIC RAM is invariably
static (SRAM), so we do not need to refresh the bits. When we refer to RAM
in an ASIC environment we almost always mean SRAM. Most ASIC RAMs use a
six-transistor cell (four transistors to form two cross-coupled inverters
that form the storage loop, and two more transistors to allow us to read
from and write to the cell). RAM compilers are available that produce single-port
RAM (a single shared bus for read and write) as well as dual-port
RAMs , and multiport RAMs . In a multi-port RAM the compiler
may or may not handle the problem of address contention (attempts
to read and write to the same RAM address simultaneously). RAM can be asynchronous
(the read and write cycles are triggered by control and/or address transitions
asynchronous to a clock) or synchronous (using the system clock).

In addition to producing layout
we also need a model compiler so that we can verify the circuit at
the behavioral level, and we need a netlist from a netlist compiler
so that we can simulate the circuit and verify that it works correctly at
the structural level. Silicon compilers are thus complex pieces of software.
We assume that a silicon compiler will produce working silicon even if every
configuration has not been tested. This is still ASIC design, but now we
are relying on the fact that the tool works correctly and therefore the
compiled blocks are correct by construction .