Intel has said on multiple occasions that its 45nm process
is on track for
production 2007. In fact, Intel began sampling its Penryn
45nm chips just several weeks ago. At the IEDM, IBM and AMD described three
technologies that hope to compete with Intel’s 45nm development: the use of
immersion lithography, which AMD says will “deliver enhanced microprocessor
design definition and manufacturing consistency,” ultra-low-K interconnect
dielectrics to enhance performance-per-watt ratio and multiple enhanced
transistor strain techniques.

Current process technologies use conventional lithography,
which has significant limitations in defining microprocessor designs beyond the
65nm process
technology generation. Immersion lithography uses a projection lens filled with
purified water as part of the step-and-repeat lithography -- think of the same
principles applied to immersion microscopy.

Immersion lithography provides increased flow of light, depth of focus and improved image
fidelity that can improve chip-level performance and manufacturing efficiency. For
example, the performance of an SRAM cell shows improvements of approximately 15
percent due to this enhanced process capability, without resorting to more
costly double-exposure techniques.

In addition, AMD and IBM say that the use of porous,
ultra-low-K dielectrics reduces interconnect capacitance, wiring delay, as well
as lowering power dissipation. This advance is enabled through the development
of an ultra-low-K process integration that reduces the dielectric constant of
the interconnect dielectric while maintaining the mechanical strength. The
addition of ultra-low-K interconnect provides a 15 percent reduction in
wiring-related delay as compared to conventional low-K dielectrics.

In spite of the increased packing density of the 45nm
generation transistors, IBM and AMD demonstrated multiple enhanced transistor
strain techniques that give an 80 per cent increase in p-channel transistor
drive current and a 24 per cent increase in n-channel transistor drive current
compared to unstrained transistors. The companies claim that their achievement
results in the highest CMOS performance reported to date in a 45nm process
technology.

In November 2005, AMD and IBM announced an extension of
their joint development efforts until 2011 covering 32nm and 22nm process
technology generations. AMD and IBM expect the first 45nm products using
immersion lithography and ultra-low-K interconnect dielectrics to be available
in mid-2008.

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It's going to be really interesting in a few years when we hit that 22nm mark. That's approaching the size of individual atoms. I hope there's a new technology around by that time that can be used in place of conventional transistors or we're going to hit a brick wall in terms of performance enhancements.

> "Are you saying 90, 65, and 45nm processes are not "nanotechnology?"...

Well, the original definition of nanotech was manipulation of material on or about the nanometer scale (1-10nm). However, the marketing value of the buzzword took hold, people used the term loosely, and now it encompasses anything at the 100nm scale, or even larger.

"Researchers at IBM have overcome an important obstacle to building computers based on carbon nanotubes, by developing a way to selectively arrange transistors that were made using the carbon molecules. The achievement, described in the current issue of Nano Letters, could help make large-scale integrated circuits built out of carbon nanotubes possible, leading to ultrafast, low-power processors...
According to estimates, carbon nanotubes have the potential to produce transistors that run 10 times faster than even anticipated future generations of silicon-based devices, while at the same time using less power"

As to the actual size, I'm sorry I wasn't more specific (though masher is 100% correct), the reason is that nobody knows the actual size yet...

What factory will it be? The NY factory aint even under construction. Its just an option they got with NY willing to pay some of the funds. So I think a factory ready in 2012 is something you have in your dreams.

quote: The AMD New York plant isn't a done deal. AMD has signed a nonbinding agreement while it hashes out final details with the state.

AMD Chief Executive Hector Ruiz says it would be only the company's second new plant that uses the newest wafers, which are 300 millimeters in diameter. Companies cut chips from silicon disks, or wafers. Chip companies can get 2.25 times as many chips from 300 mm wafers as they can from the earlier standard, 200 mm.

No. Atoms in a bound state typically are _smaller_ than those in a free state. Spacing of atoms in a silicon crystal is very tight, usually less than 1A. Compared to the 650A size of the current process node, we still have a long ways to go before we start building features the size of a single atom.

And yes, you need more than one atom to build transistors...but that wasn't the point the OP was making.

What's more important than this, though, is that once you get to a certain size, you can no longer distinguish between an open gate and a closed gate...they simply all allow current to flow. That is the true boundry for how small we can go. If I remember correctly, it's something like 12nm, but I could be wrong.

Well, considering the fact that the electron cloud surrounding most atoms has a diameter of about 0.3nm (read 3 Angstroms), having atoms in a crystalline structure spaced at a distance of only 1 Angstrom would be a bit difficult. I was just saying that 22nm is about the same order of magnitude as the size of the atom. You're not going to achieve many more, if any, process shrinks after that.

> "Well, considering the fact that the electron cloud surrounding most atoms has a diameter of about 0.3nm (read 3 Angstroms), having atoms in a crystalline structure spaced at a distance of only 1 Angstrom would be a bit difficult"

Not difficult at all. As I said earlier, atomic spacing in crystalline silicon is ~1 angstrom. Here's a link since you refuse to believe:

22nm is not "the same order of magnitude as the size of the atom". Its more than 200 times larger.

> "You're not going to achieve many more, if any, process shrinks after [22nm]."

I think otherwise. There is already research proceeding on single-atom transistors, with some rather stunning advances having been made recently. That would equate to the 0.1 nm lithography node. And even that isn't a hard stop, as there's no theoretical reason to prevent switching behavior at the subatomic level.

Nice selective quoting there. I said about the same order, not exaclty the same. Two orders of magnitude is not that much on this scale. The wave functions of these atoms easily extend out into the nm scale under the right conditions.

About the same order means within one order of magnitude, not 2.5 orders. And your original quote was, to be precise, "that's approaching the size of individual atoms".

> "wave functions of these atoms easily extend out into the nm scale under the right conditions..."

The wave function of an atom can extend across the entire universe under the right conditions. However, the conditions which concern us here are the bound state, within a crystalline matrix. In this particular case, its less than 1/10 of a nm.

"If you look at the last five years, if you look at what major innovations have occurred in computing technology, every single one of them came from AMD. Not a single innovation came from Intel." -- AMD CEO Hector Ruiz in 2007