Generic width CORDIC unit for Xilinx XC4000. The CORDIC is parameterized
with respect to wordsize, number of iterations, pipeline depth, angle
type, and CORDIC function.
Hardware to extend the domain of the CORDIC to +/-180 degrees can also
be generated.

Implementation

All Technologies

CORDIC units can have a maximum wordsize of 32 bits, and a maximum number
of iterations = 31.
All the input x,y,z and output x,y,z must be the same wordsize.

Selecting Cordic function and angle type

The function and angle type of the CORDIC is selected by passing
predefined constants from the Cordic class to the constructor. These
constants are listed below.

Modes:

Cordic.UNIFIED: Unified mode CORDIC

Cordic.ROTATIONAL: Rotational mode CORDIC

Cordic.VECTOR: Vector mode CORDIC

Angle types:

Cordic.DEGREE: Degrees

Cordic.RADIANS: Radians

Cordic.FRACTIONS: Fractions of rotation. .25 = 90 degrees.

Pipelining

Pipelining is enabled by setting the registered parameter true and
selecting a pipe_depth. The pipe_depth of the CORDIC determines how many
stages of the CORDIC are paired with a pipeline register.
In order to determine the latency of the pipe, find the number of stages
in the CORDIC and divide that number by the pipe_depth. If there is a
remainder, add 1. The short pipe stage resulting from a remainder in this
computation is always placed at the inputs of the CORDIC.
The number of stages in the CORDIC can be determined by the following
method:
First, take the number of iterations.
For UNIFIED and VECTOR mode, add two stages if initial rotations are
enabled (see below for explanation of initial rotations).
For ROTATIONAL mode with a degree type other than FRACTION, add two stages
if initial rotations is enabled, but small initial rotations is not
(see below for explanation of initial rotations).
For ROTATIONAL mode with a degree type of FRACTION add one stage if
initial rotations is enabled and small initial rotations is not.
ROTATIONAL mode with a degree type of FRACTIONS and both initial rotations
and small initial rotations enabled is identical to a ROTATIONAL CORDIC
without any initial rotations, so add 0 in that case.

The registers in the pipe can be stalled using a clk_en signal.
clk_en can be passed in null for a perpetually enabled design. An
exception will be thrown if clk_en is present when the CORDIC is
unregistered.

Initial Rotations

Because the CORDIC algorithm is based on a tangent function, the domain
and range of the input and output angles is restricted to +/- 90 degrees.
This can be extended by enabling initial rotations hardware. Initial
rotations hardware adds 1-2 extra computational stages to the CORDIC to
correct inputs and outputs.

There are two types of initial rotations hardware. The first is normal
initial rotations, which takes operands in any quadrant of the Cartesian
plane and returns the correct outputs. The second is small initial
rotations. This mode allows inputs from any quadrant, but restricts the
range of input and output angles to +/- 90 degrees. Positions in the
left half of the Cartesian plane are represented with a negative magnitude
for polar notation (output of VECTOR mode, input of ROTATIONAL mode).
Rectangular inputs and outputs are unchanged in their representation.

Operand Format

CORDIC processors have a growth factor of approximately 1.647 associated
with their computation on x,y operands. For this reason, all x,y inputs
must allow both a sign bit and growth bit at the most significant
positions of the input words.

Angles are formatted in fixed point notation according to the following
table:

FRACTION

DEGREE

RADIAN

Normal

.sxxxx...

sxxxxxxx.xxxx...

sx.xxxx...

Initial Rotations

s.xxxx...

sxxxxxxxx.xxxx...

sxx.xxxx...

Small Initial Rotations

.sxxxx...

sxxxxxxx.xxxx...

sx.xxxx...

s=sign bit x=normal bit

Xilinx XC4K

Calculating CORDIC size

To find the CLB count for a CORDIC processor, take the wordsize of the
operands, divide by two and add the remainder. Add one to that number,
multiply by three. This is the number of CLBs per stage in the CORDIC.
Multiply by the number of stages in the CORDIC (a method for computing this
number can be found under pipelining above).
In summary:
Number of CLBs = (((wordsize/2)+(wordsize%2)+1)* 3)* number of stages

cellInterfaceDeterminesUniqueNetlistStructure()
When false, the default behavior of this method, each cell will list itself
separately in a netlist, guaranteeing that the netlist will not have invalid
data at the expense of a larger file-size.

cordicmode - Cordic.UNIFIED,Cordic.ROTATIONAL, or Cordic.VECTOR. UNIFIED will do both
modes of operation, with the control signal passed on the vec wire
(1 for vector mode, 0 for rotational mode). Vector mode will do
rectangular to polar conversions, Rotational mode does polar to
rectangular conversions.

angletype - Cordic.FRACTION, Cordic.DEGREE, or Cordic.RADIAN to select which type of
angles to use in the CORDIC

registered - True to add registers to the CORDIC

num_iter - Number of iterations to build. The maximum is wordsize-1

pipe_depth - Number of iterations per pipeline register. 1 for
fully pipelined. This parameter has no meaning if registered = false.

init_rots - True to add initial rotation hardware to the CORDIC to
extend the domain to +/-180 degrees.

small_ir - True to constrain input and output angles to +/-90
degress when using initial rotations. Points in the left half plane
are represented with a negative magnitude.

clk_en - Clock enable wire for the registers.

vec - Control wire for Unified mode CORDIC

xin - X input

yin - Y input

zin - Angle input

xout - X output

yout - Y output

zout - Angle output

Method Detail

cellInterfaceDeterminesUniqueNetlistStructure

When false, the default behavior of this method, each cell will list itself
separately in a netlist, guaranteeing that the netlist will not have invalid
data at the expense of a larger file-size. Overriding this method to return true
allows JHDL to save memory and netlists to be smaller by sharing the netlist
structures that are guaranteed to be identical.
NOTE: Do not override this unless every possible condition responsible for structural
differences in a class (types and amount of children cells created, and arrangements
of wires connected to ports) is included in the cellInterface[] of that class.

clock

Users define synchronous behavior in this method using standard JHDL constructs.
The simulator detects whether clock() has been implemented by calling this
function directly and checking for an exception.