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Abstract:

In a semiconductor integrated circuit, an internal circuit is capable of
executing a first operation and a second operation concurrently, and an
output circuit outputs to the outside of the semiconductor integrated
circuit information indicating whether or not the first operation is
being executed and information indicating whether or not the second
operation is executable.

Claims:

1. A nonvolatile semiconductor memory device comprising: a plurality of
memory cells or a plurality of memory cell units each including a
plurality of memory cells; and a memory cell array including the
plurality of memory cells or the plurality of memory cell units, being
arranged to form an array; wherein a first operation is performed in
response to an input of a first command or an input of a first command
sequence, and after the input of the first command or the input of the
first command sequence, a first ready/busy signal goes from a ready state
to a busy state in a first timing, and then the first ready/busy signal
goes from a busy state to a ready state in a second timing before the
first operation is completed, and the first operation includes an
operation in which data stored in a selected memory cell included in the
plurality of memory cells or the plurality of memory cell units is
changed from first data to second data; wherein a second operation is
performed in response to an input of a second command or an input of a
second command sequence, and after the input of the second command or the
input of the second command sequence, the first ready/busy signal goes
from a ready state to a busy state in a third timing, and then the first
ready/busy signal is kept to a busy state until the first operation is
completed, and the second operation includes an operation in which data
stored in a selected memory cell included in the plurality of memory
cells or the plurality of memory cell units is changed from the first
data to the second data; and wherein the first command is different from
the second command, the first command sequence is different from the
second command sequence, and the first data is different from the second
data.

2. The nonvolatile semiconductor memory device according to claim 1,
wherein a period between the first timing and a timing of the input of
the first command or the input of the first command sequence is the same
as a period between the third timing and a timing of the input of the
second command or the input of the second command sequence.

3. The nonvolatile semiconductor memory device according to claim 1,
wherein the input of the first command sequence includes command input,
address input, and data input, and the input of the second command
sequence includes command input, address input, and data input.

4. The nonvolatile semiconductor memory device according to claim 1,
wherein after the input of the first command or the input of the first
command sequence, a second ready/busy signal goes from a ready state to a
busy state, and then the second ready/busy signal is kept to a busy state
until the first operation is completed; wherein after the input of the
second command or the input of the second command sequence, the second
ready/busy signal goes from a ready state to a busy state, and then the
second ready/busy signal is kept to a busy state until the second
operation is completed; and wherein the second ready/busy signal is
different from the first ready/busy signal.

5. The nonvolatile semiconductor memory device according to claim 4,
wherein when the first operation is performed, the first ready/busy
signal and the second ready/busy signal change from a busy state to a
ready state in different timings; and wherein when the second operation
is performed, the first ready/busy signal and the second ready/busy
signal change from a busy state to a ready state in the same timing.

6. The nonvolatile semiconductor memory device according to claim 4,
wherein when the first operation is performed, the first ready/busy
signal and the second ready/busy signal change from a ready state to a
busy state in the same timing; and wherein when the second operation is
performed, the first ready/busy signal and the second ready/busy signal
change from a ready state to a busy state in the same timing.

7. The nonvolatile semiconductor memory device according to claim 4,
further comprising an output circuit, wherein the output circuit is
capable of outputting both the first ready/busy signal and the second
ready/busy signal to outside of the nonvolatile semiconductor memory
device.

8. The nonvolatile semiconductor memory device according to claim 4,
further comprising an output circuit, wherein the output circuit is
capable of outputting both the first ready/busy signal and the second
ready/busy signal simultaneously to outside of the nonvolatile
semiconductor memory device.

9. The nonvolatile semiconductor memory device according to claim 8,
wherein the output circuit is capable of outputting both the first
ready/busy signal and the second ready/busy signal simultaneously from
I/O pads to outside of the nonvolatile semiconductor memory device.

10. The nonvolatile semiconductor memory device according to claim 1,
wherein the output circuit is capable of outputting the first ready/busy
signal from a ready/busy state output pad other than an I/O pad to
outside of the nonvolatile semiconductor memory device.

11. The nonvolatile semiconductor memory device according to claim 1,
wherein the first operation is performed in response to the input of the
first command or the input of the first command sequence, and after the
input of the first command or the input of the first command sequence,
the first ready/busy signal goes from a ready state to a busy state, and
then the first ready/busy signal goes from a busy state to a ready state
before the first operation is completed, and after the first ready/busy
signal goes from a busy state to a ready state, the second command or the
second command sequence is input, and then the second operation is
performed in response to the input of the second command or the input of
the second command sequence, and after the input of the second command or
the input of the second command sequence, the first ready/busy signal
goes from a ready state to a busy state, and then the first ready/busy
signal is kept to a busy state until the second operation is completed.

12. The nonvolatile semiconductor memory device according to claim 1,
wherein a plurality of the first operations are performed successively in
response to a plurality of inputs of the first command or the input of
the first command sequence, and after a last input of the first command
or the input of the first command sequence, the first ready/busy signal
goes from a ready state to a busy state, and then the first ready/busy
signal goes from a busy state to a ready state before the first operation
is completed, and after the first ready/busy signal goes from a busy
state to a ready state, the second command or the second command sequence
is input, and then the second operation is performed in response to the
input of the second command or the input of the second command sequence,
and after the input of the second command or the input of the second
command sequence, the first ready/busy signal goes from a ready state to
a busy state, and then the first ready/busy signal is kept to a busy
state until the second operation is completed.

13. The nonvolatile semiconductor memory device according to claim 1,
further comprising: a plurality of data cache circuits; and a plurality
of first latch circuits connected to the plurality of data cache
circuits, the plurality of first latch circuits configured to latch data
to be programmed to the memory cells; wherein third data are input to the
plurality of data cache circuits before the first operation, and the
third data are transferred from the plurality of data cache circuits to
the plurality of first latch circuits in the first operation and then the
third data are stored in at least a portion of the plurality of memory
cells or the plurality of memory cell units before the first operation is
completed.

14. The nonvolatile semiconductor memory device according to claim 13,
wherein the third data are transferred from the plurality of data cache
circuits to the plurality of first latch circuits between the first
timing and the second timing.

15. The nonvolatile semiconductor memory device according to claim 1,
wherein data stored in the selected memory cell included in the plurality
of memory cells or the plurality of memory cell units is changed after
the second timing and before the first operation is completed.

16. The nonvolatile semiconductor memory device according to claim 1,
wherein the memory cell array includes the plurality of memory cell units
being arranged to form an array, the memory cell unit includes a
plurality of memory cells connected in series, a first select gate
transistor and a second select gate transistor, the plurality of memory
cells connected in series is located between a source or a drain of the
first select gate transistor and a source or a drain of the second select
gate transistor.

17. The nonvolatile semiconductor memory device according to claim 1,
wherein when data stored in a selected memory cell included in the
plurality of memory cells or the plurality of memory cell units is
changed from the first data to the second data, a threshold voltage of
the selected memory cell is caused to shift in the positive direction

18. A nonvolatile semiconductor memory device comprising: a plurality of
memory cells or a plurality of memory cell units each including a
plurality of memory cells; and a memory cell array including the
plurality of memory cells or the plurality of memory cell units, being
arranged to form an array; wherein a first operation including a first
program operation is performed in response to an input of a first
command, address input, data input, and an input of a second command, and
after the input of the first command, the address input, the data input,
and the input of the second command, a first ready/busy signal goes from
a ready state to a busy state in a first timing, and then the first
ready/busy signal goes from a busy state to a ready state in a second
timing before the first operation is completed; wherein a second
operation including a second program operation is performed in response
to an input of a first command, address input, data input, and an input
of a third command, and after the input of the first command, the address
input, the data input, and the input of the third command, the first
ready/busy signal goes from a ready state to a busy state in a third
timing, and then the first ready/busy signal is kept to a busy state
until the first operation is completed; and wherein the second command is
different from the third command.

19. The nonvolatile semiconductor memory device according to claim 18,
wherein a period between the first timing and a timing of the input of
the first command or the input of the first command sequence is the same
as a period between the third timing and a timing of the input of the
second command or the input of the second command sequence.

20. The nonvolatile semiconductor memory device according to claim 18,
wherein after the input of the first command, the address input, the data
input, and the input of the second command, a second ready/busy signal
goes from a ready state to a busy state, and then the second ready/busy
signal is kept to a busy state until the first operation is completed;
wherein after the input of the first command, the address input, the data
input, and the input of the third command, the second ready/busy signal
goes from a ready state to a busy state, and then the second ready/busy
signal is kept to a busy state until the second operation is completed;
and wherein the second ready/busy signal is different from the first
ready/busy signal.

21. The nonvolatile semiconductor memory device according to claim 20,
wherein when the first operation is performed, the first ready/busy
signal and the second ready/busy signal change from a busy state to a
ready state in different timings; and wherein when the second operation
is performed, the first ready/busy signal and the second ready/busy
signal change from a busy state to a ready state in the same timing.

22. The nonvolatile semiconductor memory device according to claim 20,
wherein when the first operation is performed, the first ready/busy
signal and the second ready/busy signal change from a ready state to a
busy state in the same timing; and wherein when the second operation is
performed, the first ready/busy signal and the second ready/busy signal
change from a ready state to a busy state in the same timing.

23. The nonvolatile semiconductor memory device according to claim 20,
further comprising an output circuit, wherein the output circuit is
capable of outputting both the first ready/busy signal and the second
ready/busy signal to outside of the nonvolatile semiconductor memory
device.

24. The nonvolatile semiconductor memory device according to claim 20,
further comprising an output circuit, wherein the output circuit is
capable of outputting both the first ready/busy signal and the second
ready/busy signal simultaneously to outside of the nonvolatile
semiconductor memory device.

25. The nonvolatile semiconductor memory device according to claim 24,
wherein the output circuit is capable of outputting both the first
ready/busy signal and the second ready/busy signal simultaneously from
I/O pads to outside of the nonvolatile semiconductor memory device.

26. The nonvolatile semiconductor memory device according to claim 18,
wherein the output circuit is capable of outputting the first ready/busy
signal from a ready/busy state output pad other than an I/O pad to
outside of the nonvolatile semiconductor memory device.

27. The nonvolatile semiconductor memory device according to claim 18,
wherein the first operation is performed in response to the input of the
first command, the address input, the data input, and the input of the
second command, and after the input of the first command, the address
input, the data input, and the input of the second command, the first
ready/busy signal goes from a ready state to a busy state, and then the
first ready/busy signal goes from a busy state to a ready state before
the first operation is completed, and after the first ready/busy signal
goes from a busy state to a ready state, the input of the first command,
the address input, the data input, and the input of the third command are
performed, and then the second operation is performed in response to the
input of the first command, the address input, the data input, and the
input of the third command, and after the input of the first command, the
address input, the data input, and the input of the third command, the
first ready/busy signal goes from a ready state to a busy state, and then
the first ready/busy signal is kept to a busy state until the second
operation is completed.

28. The nonvolatile semiconductor memory device according to claim 18,
wherein a plurality of the first operations are performed successively in
response to a plurality of inputs of the first command, the address
inputs, the data inputs, and the inputs of the second command, and after
last input of the first command, last address input, last data input, and
last input of the second command, the first ready/busy signal goes from a
ready state to a busy state, and then the first ready/busy signal goes
from a busy state to a ready state before the first operation is
completed, and after the first ready/busy signal goes from a busy state
to a ready state, the input of the first command, the address input, the
data input, and the input of the third command are performed, and then
the second operation is performed in response to the input of the first
command, the address input, the data input, and the input of the third
command, and after the input of the first command, the address input, the
data input, and the input of the third command, the first ready/busy
signal goes from a ready state to a busy state, and then the first
ready/busy signal is kept to a busy state until the second operation is
completed.

29. The nonvolatile semiconductor memory device according to claim 18,
further comprising: a plurality of data cache circuits; and a plurality
of first latch circuits connected to the plurality of data cache
circuits, the plurality of first latch circuits configured to latch data
to be programmed to the memory cells; wherein first data are input to the
plurality of data cache circuits before the first operation, and the
first data are transferred from the plurality of data cache circuits to
the plurality of first latch circuits in the first operation and then the
first data are programmed in at least a portion of the plurality of
memory cells or the plurality of memory cell units before the first
operation is completed.

30. The nonvolatile semiconductor memory device according to claim 29,
wherein the first data are transferred from the plurality of data cache
circuits to the plurality of first latch circuits between the first
timing and the second timing.

31. The nonvolatile semiconductor memory device according to claim 18,
wherein data stored in the memory cells programmed in the first operation
are changed after the second timing and before the first operation is
completed.

32. The nonvolatile semiconductor memory device according to claim 18,
wherein the memory cell array includes the plurality of memory cell units
being arranged to form an array, the memory cell unit includes a
plurality of memory cells connected in series, a first select gate
transistor and a second select gate transistor, the plurality of memory
cells connected in series is located between a source or a drain of the
first select gate transistor and a source or a drain of the second select
gate transistor.

Description:

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation of, and claims the benefit of
priority under 35 USC §120 from, U.S. application Ser. No.
12/981,063 filed Dec. 29, 2010, which is a continuation of U.S.
application Ser. No. 12/252,896, filed Oct. 16, 2008, which is a
continuation of U.S. application Ser. No. 11/742,600, filed May 1, 2007
(now U.S. Pat. No. 7,453,739), which is a continuation of U.S.
application Ser. No. 11/515,005, filed Sep. 5, 2006 (now U.S. Pat. No.
7,224,621), which is a continuation of U.S. application Ser. No.
11/119,744, filed May 3, 2005 (now U.S. Pat. No. 7,123,515B2), which is a
divisional of U.S. application Ser. No. 10/318,167, filed Dec. 13, 2002
(now U.S. Pat. No. 7,023,741B2), and is based upon and claims the benefit
of priority under 35 USC §119 from the Japanese Patent Applications
No. 2001-386596, filed Dec. 19, 2001, and No. 2002-311475, filed Oct. 25,
2002, the entire contents of all of which are incorporated herein by
reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor integrated circuit
adapted to output the PASS/FAIL results of internal operations to the
outside of the semiconductor chip. Specifically, the present invention
relates to a nonvolatile semiconductor storage device, such as a
NAND-cell EEPROM, a NOR-cell EEPROM, a DINOR-cell EEPROM, or an AND-cell
EEPROM.

[0004] 2. Description of the Related Art

[0005] An electrically rewritable EEPROM is known as one type of
semiconductor storage device. In particular, a NAND-cell-based EEPROM in
which a plurality of memory cells are connected in series to form a NAND
cell block has attracted a great deal of attention because of its
adaptability for high packing densities.

[0006] One memory cell in the NAND-cell-based EEPROM has an FET-MOS
structure in which a floating gate (charge storage layer) and a control
gate are formed over the semiconductor substrate such that the former is
located below the latter with an insulating film interposed therebetween.
A plurality of memory cells are connected in series such that the source
of each cell is common to the drain of the adjacent cell, thereby forming
a NAND cell. The NAND cell is connected as a unit to a corresponding bit
line.

[0007] Such NAND cells are arranged in a matrix form to constitute a
memory cell array. The memory cell array is manufactured into a p-type
well (or a p-type substrate). NAND cells arranged in the column direction
of the memory cell array have their respective drains at their one end
connected together through select gate transistors to a corresponding bit
line and their respective sources at their other end connected together
through select gate transistors to a common source line.

[0008] The control gates of memory cell transistors arranged in the row
direction of the memory cell array are connected together to form a
control gate line (word line). Likewise, the gates of the select gate
transistors arranged in the row direction are connected together to form
a select gate line.

[0009] The NAND-cell EEPROM operates in the following manner:

[0010] Data program operation begins with the memory cell located furthest
from a bit line contact. The control gate of the selected memory cell is
supplied with a high voltage Vpgm of about 18V. The control gates of the
memory cells located nearer the bit line contact and the select gates are
supplied with an intermediate voltage Vmw of about 10V. The bit line is
supplied with 0V or an intermediate voltage of about 8V according to
data.

[0011] When the bit line is supplied with 0V, the voltage is transferred
to the drain of the selected memory cell, so that tunneling of electrons
from the drain into the floating gate occurs. Thereby, the threshold
voltage of the selected memory cell is caused to shift in the positive
direction. This state is assumed to be "0" by way of example.

[0012] When the intermediate voltage Vmb is applied to the bit line, no
tunneling of electrons occurs and hence the threshold voltage of the
memory cell is not changed and remains negative. This state corresponds
to "1".

[0013] Data erasing is performed simultaneously on all the memory cells in
a selected NAND cell block. That is, all the control gates in the
selected NAND cell block are set at 0V, a high voltage Vera of about 22V
is applied to the p-type well (or the p-type substrate). The bit and
source lines and the control gates in nonselected NAND cell blocks and
all the select gate lines are rendered floating.

[0014] Thereby, in all the memory cells in the selected NAND cell block,
electrons in the floating gates due to the tunnel effect are released
into the p-type well (or the p-type substrate). Thereby, after erasing,
the threshold voltage is shifted in the negative direction.

[0015] To read data, the control gate of the selected memory cell is set
at 0V with the control gates of other memory cells and the select gates
supplied with the supply voltage Vcc or a read voltage VH higher than
Vcc. This read voltage VH is normally less than twice the supply voltage
Vcc, say, less than 5V. In this state, data is sensed by detecting
whether or not a current is flowing in the selected memory cell.

[0016] FIG. 1 shows example arrangements of the memory cell array and the
bit line control circuit of a conventional NAND-cell EEPROM.

[0017] In FIG. 1, the memory cell array has 33,792 bit lines BL0 to
BL33791 and 1,024 blocks Block0 to Block1023 and row decoders are placed
on opposite sides of the array in the row direction.

[0018] A sense latch circuit 31 is connected between a pair of bit lines
BLi and BLi+1 (i=0, 1, . . . ) and a pair of input/output lines IO and
/IO over which data is transferred between the memory array and the data
input/output buffer. That is, a single sense latch is connected between
the paired input/output lines IO and /IO and each pair of odd- and
even-numbered bit lines.

[0019] FIG. 2 shows an algorithm for the data program sequence in the NAND
cell EEPROM of FIG. 1.

[0020] According to this algorithm, data is programmed into each of two or
more pages in sequence. While data is being programmed in, that is, when
the sense latch circuit 31 is in operation, it cannot be used for another
operation, such as data entry.

[0021] That is, the data program sequence involves an operation of
entering data to be programmed (program data) and an operation of
programming data for one page. These operations are performed alternately
for each page. That is, the data entry operation cannot be performed
concurrently with the data program operation.

[0022] Thus, the data entry operation and the data program operation are
repeated alternately during the data program sequence. The overall time
of the data program sequence is defined mainly by the sum of the time
required to enter data and the time required to program data and will
therefore become considerably long.

[0023] FIG. 3 shows an algorithm for the data read sequence in the
NAND-cell EEPROM of FIG. 1.

[0024] In this algorithm, each of pages is subjected in sequence to a data
read operation. While data is being read, the sense latch circuit 31 is
in operation (i.e., in use); thus, it cannot be used for another
operation (such as outputting data).

[0025] With the algorithm of FIG. 3, the overall time of the data read
sequence is determined by the sum of the time required to read data and
the time required to output data and will therefore become considerably
long.

[0026] With a conventional nonvolatile semiconductor storage device such
as of the NAND cell type, as described above, it is impossible to perform
a data entry operation concurrently with a data program operation and a
problem therefore arises in that the overall time of the data program
sequence becomes long.

[0027] Likewise, it is also impossible to perform a data output operation
concurrently with a data read operation and a problem therefore arises in
that the overall time of the data read sequence becomes long.

BRIEF SUMMARY OF THE INVENTION

[0028] According to an aspect of the present invention there is provided a
semiconductor integrated circuit comprises: an internal circuit
configured to execute a first operation and a second operation
concurrently; and an output circuit connected to the internal circuit,
the output circuit configured to output to the outside of the
semiconductor integrated circuit information indicating whether or not
the first operation is being executed and information indicating whether
or not the second operation is executable.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

[0029] FIG. 1 shows example arrangements of the memory cell array, the bit
line control circuit and the data input/output control circuit of a
conventional NAND cell EEPROM;

[0030] FIG. 2 is a flowchart illustrating an algorithm for a data program
sequence in the memory of FIG. 1;

[0031] FIG. 3 is a flowchart illustrating an algorithm for the data read
sequence in the memory of FIG. 1;

[0032]FIG. 4 is a block diagram of a NAND-cell EEPROM according to a
first embodiment of the present invention;

[0033] FIG. 5A is a plan view of a NAND cell portion in the memory cell
array of FIG. 4;

[0055] FIG. 25 shows an equivalent circuit of a portion of the memory cell
array of a NOR cell EEPROM;

[0056] FIG. 26 shows an equivalent circuit of a portion of the memory cell
array of a DINOR cell EEPROM;

[0057] FIG. 27 shows an equivalent circuit of a portion of the memory cell
array of an AND cell EEPROM;

[0058] FIG. 28 shows an equivalent circuit of a portion of the memory cell
array of an example of a NOR cell EEPROM with select transistors; and

[0059] FIG. 29 shows an equivalent circuit of a portion of the memory cell
array of another example of a NOR cell EEPROM with select transistors.

DETAILED DESCRIPTION OF THE INVENTION

[0060] Referring now to FIG. 4, there is illustrated, in block diagram
form, an arrangement of a NAND-cell EEPROM according to a first
embodiment of the present invention.

[0061] A memory cell array 1 is formed, as will be described later, with a
number of memory cells each of which has a control gate and a floating
gate and is associated with a bit line and a word line. The memory cells
are divided into a number of blocks. In operation, one of the blocks is
selected.

[0062] Connected with the memory cell array 1 is a bit line control
circuit 2 which is adapted to read data from the memory cells in the
array. Also, it performs a data program operation on each memory cell.

[0063] To this end, the bit line control circuit 2 includes a plurality of
sense latch circuits (sense amplifier/data latch circuits) that acts as a
sense amplifier for sensing and amplifying potentials on the bit lines in
the cell array and data latch circuits for latching program data to be
programmed. The bit line control circuit 2 receives program data from or
sends read data to a data input/output control circuit 3.

[0064] As will be described later, the data input/output control circuit 3
includes a plurality of data cache circuits that holds program data or
read data and performs input/output control of internal or external data.
A data input/output buffer (I/O buffer) 4 is connected with the data
input/output control circuit 3.

[0065] The data input/output control circuit 3 is controlled by a column
decoder 6 that receives an address information from an address buffer
(address latch) 5 which receives an address information input.

[0066] Connected with the memory cell array 1 is a row decoder 7 that
controls the control gates of the memory cells and the select gates.
Further, connected with the memory cell array 1 is a well potential
control circuit 8 that controls the potential of the p-type well or
p-type substrate in which the memory cell array 1 is manufactured.
Moreover, connected with the memory cell array 1 is a source line control
circuit 9 that controls the source line voltage.

[0067] Also, a word line control circuit 10 is provided to control the
potentials on the word lines, or the control gate lines, in the selected
block. A row decoder power supply control circuit 11 is provided which
controls the supply voltage of the row decoder circuit 7. The word line
control circuit 10 and the row decoder power supply control circuit 11
are both connected to the row decoder circuit 7.

[0068] Furthermore, a high voltage/intermediate voltage generating circuit
12 is provided which generates high and intermediate program voltages, a
high erase voltage and a high read voltage. The erase voltage is applied
to the p-type well or p-type substrate during an erase operation. The
program voltages are applied to the word line, the bit lines, the row
decoder 7, etc., during a program operation. The voltage generating
circuit 12 is connected to the memory cell array 1, the bit line control
circuit 2, the word line control circuit 10, and the row decoder power
supply control circuit 11.

[0069] The data input/output buffer 4 sends data to or receives data from
the outside. For example, eight I/O pads I/O-1 to I/O-8 are connected to
the data input/output buffer 4. Through these I/O pads the buffer 4
receives program data, address information, commands, etc., from the
outside and outputs read data and various signals to the outside.

[0070] The data input/output buffer 4 is further connected to the address
buffer 5 and a command decoder 13.

[0071] When a command is input to the data input/output buffer 4 through
the I/O pads I/O-1 to I/O-8, the command decoder 13 receives and latches
the command through the buffer 4 and then outputs control signals to
control various operations such as read, program, and erase operations.

[0072] A PASS/FAIL decision circuit 14 and a PASS/FAIL holding circuit 15
are also provided. The PASS/FAIL decision circuit 14 is connected to the
bit line control circuit 2 and the PASS/FAIL holding circuit 15 is
connected to the PASS/FAIL decision circuit 14. The PASS/FAIL hold
circuit 15 includes, for example, shift registers.

[0073] The PASS/FAIL decision circuit 14 decides whether or not the cell
programming or erasing has been performed correctly. When the cell
programming or erasing has been performed correctly, it is defined as the
PASS status; otherwise, it is defined as the FAIL status.

[0074] After the cell programming or erasing, the result of the PASS/FAIL
decision by the PASS/FAIL decision circuit 14 is sent to a PASS/FAIL
holding circuit 15 and held therein. In examining the PASS/FAIL status is
externally applied through the data input/output buffer 4 to the command
decoder 13, which accordingly produces control signals to cause the
result of the PASS/FAIL decision is then output through at least one of
the I/O pads I/O-1 to I/O-8 to the outside of the chip.

[0075] Connected to the data input/output control circuit 3 and the data
input/output buffer 4 is a Ready/Busy (R/B) control circuit 16, which is
responsive to the data input/output control circuit 3 to produce a
plurality of Ready/Busy signals indicating the current operating state of
the chip. The plurality of Ready/Busy signals are output through the I/O
pads I/O-1 to I/O-8 to the outside of the chip.

[0076] FIGS. 5A and 5B show a plan view of a NAND-cell portion in the
memory cell array 1 of FIG. 4 and its equivalent circuit diagram,
respectively. FIGS. 6A and 6B are sectional views taken along line
XIA-XIA and line XIB-XIB, respectively, of FIG. 5A.

[0077] In the memory cell array, a large number of NAND cells (each of a
plurality of memory cells) are formed in a p-type silicon substrate (or
p-type well) 22 in such a way that they are isolated from one another by
a device isolation oxide film 21. One NAND cell includes a plurality of
memory cells (in this example, eight memory cells M1 to M8) which are
connected in series so that adjacent ones share n-type diffused regions
23 (230, 231, . . . , 2310) serving as their source/drain
regions.

[0078] On the drain and source sides of the NAND cell, select gates
249, 259 and 2410 and 2510 are placed which are
formed simultaneously with the floating and control gates of the
respective memory cell transistors.

[0079] Each memory cell has a stacked-gate MOSFET structure such that a
floating gate 24 (241, 242, . . . , 248) is formed over
the semiconductor substrate 22 with a gate insulating film 26 interposed
therebetween and a control gate 26 (261, 262, . . . , 268)
is formed over the floating gate 24 with a gate insulating film 27
interposed therebetween.

[0080] The substrate thus formed with the elements is covered with a CVD
oxide layer 28. which is formed on top with bit lines 29. Each bit line
is contact with the diffused region 230 on the drain side of a
corresponding NAND cell.

[0081] Such NAND cells as described above are arranged in a matrix form.
The select gate transistor on the drain side of each NAND cell is
connected to a corresponding bit line and the select gate transistor on
the source side is connected to a common source line (cell-source
voltage).

[0082] The control gates 25 of the respective memory cells M1 to M8 are
respectively connected with select gate lines (word lines) CG1, CG2, . .
. CG8 that extend in the row direction of the memory cell array.

[0083] The gates of the respective select gates 249, 259 and
2410, 2510 are also connected to select gate lines SG1 and SG2,
respectively, which extend in the row direction of the memory cell array.

[0084] FIG. 7 shows a portion of the equivalent circuit of the memory cell
array 1 in which such NAND cells as shown in FIGS. 5A and 5B are arrayed
in a matrix form.

[0085] A group of NAND cells that share the same word lines and select
gate lines is referred to as a block. For example, NAND cells within a
region enclosed with dotted lines form one block. A read/program
operation is performed on a selected one of the blocks.

[0086] FIG. 8 shows example circuit arrangements of the memory cell array
1, the bit line control circuit 2, and the data input/output control
circuit 3.

[0087] As shown in FIG. 8, a pair of IO and /IO lines over which data is
sent to or from the data input/output buffer 4 is coupled through data
cache circuits 31 in the data input/output control circuit 3 to sense
latch circuits 32 in the bit line control circuit 2. The data cache
circuits 31 and the sense latch circuits 32 are each included of two
inverters. More specifically, each data cache circuit 31 includes a latch
circuit 33 which has two inverters, a switching transistor 34 connected
between the IO line and one data storage node N1 of the latch circuit 33,
a switching transistor 35 connected between the /IO line and the other
data storage node N2 of that latch circuit 33, and a switching transistor
36 connected between the data storage node N2 and the corresponding sense
latch circuit 32.

[0088] Each sense latch circuit 32 includes of a latch circuit 37
consisting of two inverters and a switching transistor 38 having its one
end connected to a data storage node N3 of that latch circuit 37. The bit
line control circuit 2 is provided with two switching transistors 39 and
40 for each sense latch circuit 32. The transistor 39 is connected
between the other end of the transistor 38 and one of the even-numbered
bit lines in the memory cell array 1, while the transistor is connected
between the other end of the transistor 38 and one of the odd-numbered
bit lines in the memory cell array 1. The switching transistors 39 and 40
have their gates controlled by bit line select signals BLT0 and BLT1,
respectively.

[0089] That is, only the data cache circuit 31 is directly connected to
the paired IO and /IO lines. The sense latch circuit 32 is connected
through the data cache circuit 31 to the IO and /IO lines.

[0090] The memory cell array 1 in FIG. 8 has 33,792 bit lines BL0 to
BL33791 and 1,024 blocks Block0 to Block1023. Row decoders are placed on
opposite sides in the row direction of the memory cell array.

[0091] In the circuit of FIG. 8, between two odd- and even-numbered bit
lines and the paired IO and /IO lines are connected two types of latch
circuits: one sense latch circuit 32 and one data cache circuit 31. Thus,
in program or read operation, only one of the two bit lines connected to
the sense latch circuit 32 is selected and only the memory cells
connected to the selected bit line can be programmed into or read from.

[0092] It is only the sense latch circuit 32 that is used in data program
operation; thus, the data cache circuit 31 can be used for an operation
independent of the data program operation. For example, the data cache
circuit 31 can be used to input the next program data, i.e., program data
to the next page.

[0093] FIG. 9 is a flowchart illustrating an algorithm for a data program
sequence in the circuit of FIG. 8.

[0094] This algorithm indicates the manner in which the operation of
programming data to one page and the operation of inputting data to be
programmed to the next page are performed concurrently in the data
program sequence in which data is programmed to each of the pages in
sequence. In the first step, an operation of inputting program data to
the data cache circuit 31 (to Data Cache) (PROGRAM DATA ENTRY) is
performed. In the next step, an operation of transferring the program
data from the data cache circuit 31 to the sense latch circuit 32 (Data
Cache→Sense Latch) is performed. In the subsequent step, an
operation of programming data latched in the sense latch circuit 32 into
a memory cell is performed (Use Sense Latch). Concurrently with this data
program operation, an operation of inputting the next program data to the
data cache circuit 31 is performed (to Data Cache).

[0095] As in the case of the previous data, the next program data is
transferred from the data cache circuit 31 to the sense latch circuit 32
and then programmed into a memory cell.

[0096] The algorithm of FIG. 9 requires transfer of data from the data
cache circuit 31 to the sense latch circuit 32. However, compared with
the time required by a data program operation (usually of the order of
200 μs) or a data entry operation (usually of the order of tens of
μs to hundreds of μs), the time required by a data transfer is very
short, usually of the order of 2 to 3 μs. Thus, the data transfer time
has little influence on the overall time of the data program sequence.

[0097] Here, the advantages of the algorithm of FIG. 9 over the
conventional algorithm of FIG. 2 will be described in terms of the data
program time per page.

[0098] The data program time per page required by the algorithm of FIG. 9
is the sum of the time required by the longer one of the data program and
entry operations which are performed concurrently and the data transfer
time. In contrast to this, the data program time per page required by the
algorithm of FIG. 2 is the sum of the data program time and the data
entry time.

[0099] In view of the fact that usually the data program time is, at most,
of the order of 200 μs and the data input time is of the order of 200
μs, the data program time and the data input time are of substantially
the same order. Therefore, the use of the algorithm of FIG. 9 results in
a data program time per page of the order of 200 μs.

[0100] In contrast, in the case of the algorithm of FIG. 2, the data
program time per page becomes 200 μs plus 200 μs. Therefore, the
use of the algorithm of FIG. 9 allows the overall time of the data
program sequence to be made much shorter than does the algorithm of FIG.
2.

[0101] FIGS. 10A through 10F schematically illustrate the operation of the
circuit of FIG. 8 when the algorithm of FIG. 9 is used.

[0102] In FIGS. 10A through 10F, a data program operation which is
concurrent with a data input operation is labeled "Background" and an
independent data program operation is labeled "Foreground". The data
program operation is labeled "Data Prog.". The data program operation is
performed by repeating an operation of applying the data programming
voltage to a memory cell (programming) and a program verification
operation (verification).

[0103] In the data program operation to the final page, there is no need
to input data to be programmed to the next page; thus, an independent
program operation is performed as shown in FIGS. 9 and 10A through 10F.
No background operation is therefore required in the data program
operation to the final page. That is, since there is no need to perform
an operation concurrently with another operation, and use of a foreground
operation, the overall time of the data programming sequence is not
change.

[0104] FIG. 11 shows an example of a data program sequence control method
for a semiconductor chip formed with the NAND cell EEPROM of FIG. 4. The
operations in intervals Ta through Tf in FIG. 11 correspond to those in
FIGS. 10A through 10F.

[0105] A general control method for implementing a program operation
involves a sequence of entry of an address/data inputting command (COM1),
entry of an address to which data is to be programmed, entry of program
data, entry of a command to initiate the data program operation, and
initiation of the data program operation. There are two commands to
initiate the data program operation: a command (COM2) for a background
program operation which can be performed concurrently with a program data
input operation, and a command (COM3) for a foreground program operation
that cannot be performed concurrently with another operation.

[0106] When the command COM3 is input, the busy interval in the ready/busy
state indicating the chip operating state becomes long and the busy state
lasts until the COM3-based program operation is completed. The ready/busy
state is detected by the R/B control circuit 17 through the operation of
the data input/output control circuit 3 in FIG. 4, whereby a plurality of
ready/busy signals is produced.

[0107] When the command COM2 is input, on the other hand, the busy
interval in the ready/busy state becomes short. A return is made from the
busy state to the ready state immediately after program data input
immediately prior to entry of the command COM2 has been transferred from
the data cache circuit 31 to the sense latch circuit 32.

[0108] Usually use is made of the command COM2 for pages other than the
final page in the data program sequence, thereby allowing a data program
operation and a data input operation to be performed concurrently to
reduce the time required. The command COM3 is used for the final page to
facilitate the detection of completion of the data program sequence. That
is, the use of a method that enables the completion of the sequence to be
detected through examination of the ready/busy state is particularly
effective.

[0109] FIG. 11 shows the case where data is programmed into each page in
the order of page 1, page 2, . . . , page N and the times indicated by
numerical values correspond to the case where the amount of input data is
assumed to be 2,112 bytes per page, the data input cycle to be 50 ns, the
time required to transfer data from the data cache circuit 31 to the
sense latch circuit 32 to be 3 μs, and the time required to program
data to be 200 μs.

[0110] In the method shown in FIG. 11, the quasi-ready state is output
during the background program operation as in the Tc and Td intervals.
During the quasi-ready state, the entry of commands other than commands
such as COM1, COM2 and COM3, which are associated with data program
operations, is inhibited. Such commands are associated with, for example,
data read and erase operations. Usually, the entry of these inhibit
commands will be described in chip specifications.

[0111] It is effective to design a chip in such a way as to, when an
inhibit command is entered, ignore the command and continue the
background operation. Such a chip will prevent malfunctions.

[0112] Specifically, valid commands include programming-related commands,
such as COM1, COM2 and COM3, a reset command, and commands to output
signals indicating the Ready/Busy state and the PASS/FAIL status.
Commands to be inhibited or ignored are commands other than the above
valid commands and include reading-related commands and erasing-related
commands.

[0113] Like a chip ID output command, some of commands may be classified
under either of valid and inhibit commands. In order to make circuit
arrangements straightforward, they should preferably be taken into the
inhibit commands.

[0114] Although the first embodiment has been described in terms of the
circuit arrangement of FIG. 8, this is merely an example.

[0115] FIG. 12 shows a first modification of the first embodiment.

[0116] As shown in FIG. 12, the memory cell array 1 is divided in the word
line direction into two memory cell arrays 1-1 and 1-2 and one block is
halved between the two memory cell arrays. The present invention is also
effective in such a configuration.

[0117] In the configuration of FIG. 12, memory cells corresponding to one
page may be placed halved between the two memory cell arrays 1-1 and 1-2.
The present invention is also effective in performing such operations as
described above on the memory cells for one page placed in the right and
left memory cell arrays.

[0118] In the configuration of FIG. 12, memory cells for one page may be
placed in only one of the memory cell arrays 1-1 and 1-2. The present
invention is also effective in performing such operations as described
above on memory cells for two different pages which are placed in the
right and left memory cell arrays which are selected simultaneously.

[0119] FIG. 13 shows a second modification of the first embodiment.

[0120] As shown in FIG. 13, the memory cell array 1 is divided in the word
line direction into two memory cell arrays 1-1 and 1-2 and one block is
placed only in one of the two memory cell arrays. The present invention
is also effective in such a configuration.

[0121] The present invention is also effective in performing the
aforementioned operations on memory cells for two different pages which
are placed in the right and left memory cell arrays in the configuration
of FIG. 13. In this case, memory cells for two pages in different blocks
can be programmed into at the same time.

[0122] In addition, the memory cell array may be divided into three or
more. In this case as well, the present invention is effective and such
operations as described above can be implemented.

[0123] A comparison is next made between a control method of the present
invention and a conventional control method for data programming.

[0124] FIG. 14A is a schematic representation of the conventional data
programming control method and FIG. 14B is a schematic representation of
the control method for the data program sequence shown in FIG. 11.

[0125] In the conventional method shown in FIG. 14A, the data program
operations for all pages are performed by foreground processing. In the
method shown in FIG. 14B, on the other hand, on pages other than the
final page the program operations are performed by background processing.

[0126] FIG. 14C shows another control method of the present invention.

[0127] According to this method, the data program operations are performed
on all pages by background processing. In this case as well, the first
embodiment is effective.

[0128] FIGS. 15A through 15F illustrate the manner in which busy signals
are output in data program operations when the control method of FIGS.
14A through 14C are used. In these figures, address/data inputs are
omitted in portions in which command inputs are described only for the
purpose of simplifying illustration.

[0129] The signal "Cache-R/B" in FIGS. 15A through 15F indicates the
read/busy states, for example, the ready/busy states in FIG. 11 and
usually corresponds to the chip ready/busy states output from the I/O
pads I/O-1 to I/O-8 in FIG. 4. A pad may be provided to indicate the chip
ready/busy state. In this case, the pad indicates a ready/busy state that
usually corresponds to Cache-R/B. The signal "True-R/B" represents the
in-chip operating states including background operations and always
assumes the busy state during a background operation.

[0130] FIG. 15A shows a case where conventional data program operations
are performed independently, which correspond to foreground operations.
In this case, the two signals Cache-R/B and True/R/B are coincident in
state with each other in the data program operation interval tPROG.

[0131] FIGS. 15B and 15D illustrate program operation intervals tPROG and
busy signal states when two data program operations are performed
successively and a second-operation start command is input after the
termination of the first operation.

[0132] FIGS. 15C and 15E illustrate program operation intervals tPROG and
busy signal states when two data program operations are performed
successively and a second-operation start command is input during the
first program operation.

[0133] FIG. 15F illustrates a program operation interval tPROG and busy
signal states when a data program operation start command is input after
the termination of a busy signal being output through an operation other
than a program operation.

[0134] From FIGS. 15A through 15F it can be seen that, when the background
operations are involved, the ready/busy state varies variously with the
input timing of the operation start command.

[0135] To examine the PASS/FAIL status after the termination of a certain
operation, a chip status output command COMS is simply input to the I/O
pads I/O-1 to I/O-8. The chip status output command is sent through the
data input/output buffer 4 to the command decoder 13 in FIG. 4, which in
turn produces control signals used to output the PASS/FAIL status.

[0136] As described previously, after the termination of a data program
operation, the PASS/FAIL status is holding by the PASS/FAIL holding
circuit 15. To examine the PASS/FAIL status, a chip status output command
COMS is input to the I/O pads I/O-1 to I/O-8. The PASS/FAIL status held
by the PASS/FAIL holding circuit 15 is then output from the I/O pads
I/O-1 to I/O-8 via the data input/output buffer 4.

[0137] In general, the operation of outputting the chip status containing
the PASS/FAIL status after entry of the chip status command COMS is
called "status read".

[0138] FIGS. 16A through 16F illustrate the time dependence of the
PASS/FAIL output results at the status read time when program operations
are performed in succession.

[0139] FIGS. 16G through 16K illustrate the time dependence of the
PASS/FAIL output results at the status read time when an operation other
than a program operation and a program operation are performed in
succession.

[0142] As shown in FIGS. 16A through 16F, in view of the PASS/FAIL outputs
when background operations are involved, it is very important to make
clear which program operation a PASS/FAIL output by the status read
corresponds to, i.e., which page the corresponding program operation
corresponds to. If this is possible, in the event of programming
failures, pages containing faulty data can be identified.

[0143] To make clear the correspondence between PASS/FAIL outputs and
pages, in the case of successive program operations, PASS/FAIL outputs
for two past program operations are obtained simultaneously or
sequentially as indicated in tables 1A through 1I. That is, after entry
of the chip status command COMS, signals representing the PASS/FAIL
status are output from the two I/O pads I/O-1 and I/O-2 as shown. The
expression "invalid" in each table represents data that does not reflect
the PASS/FAIL status. This data need not be monitored.

[0144] Table 2 below indicates example data contents output from the eight
I/O pads I/O-1 to I/O-8 at state read time in the first embodiment.

[0145] The I/O pad I/O-1 outputs the chip status (Chip Status-I) for an
immediately preceding operation. The I/O pad I/O-2 outputs the chip
status (Chip Status-II) corresponding to a program operation immediately
prior to the immediately preceding operation. The chip status is "0" in
the case of PASS and "1" in the case of FAIL.

[0146] When the system of FIGS. 16A through 16F is used, the PASS/FAIL
status contents vary with the times of Cache-R/B, True-R/B and status
read. It is therefore desired that Cache-R/B and True-R/B be contained in
the status read output data. In this case, such outputs as indicated in
Table 3 below will result.

[0150] The expression "(A1+A2)-status" in Table 4A indicates the result of
accumulation of the PASS/FAIL status of the A1 and A2 operations, namely,
that, in the event of a failure in either of the A1 or A2 operation, the
fail status is maintained.

[0151] In actual operation, data is frequently programmed over a
continuous range of several pages to tens of pages. In such a case, the
cumulative PASS/FAIL status for program operations corresponding to
several pages to tens of pages is output.

[0152] With the cumulative status, there are two systems: one that enables
that status to be reset by the usual RESET command and one that enables
the status to be reset only by a dedicated RESET command.

[0153] Cumulative status systems include one that accumulates the
PASS/FAIL status of operations from an operation immediately after the
status has been reset to the last operation and one that accumulates the
PASS/FAIL status only for particular operations or commands, for example,
program operations or programming-related commands.

[0156] That is, when first and second operations for which PASS/FAIL
results are held in the chip are performed in succession, the NAND-cell
EEPROM of the first embodiment allows the PASS/FAIL results to be output
to the outside of the chip, which increases the convenience of control
outside the chip.

[0157] In addition, the NAND-cell EEPROM described above allows a first
operation of, say, programming data and a second operation of, say,
inputting program data to be performed concurrently. To this end, the
EEPROM is adapted to output data representing whether or not the first
operation is being executed, e.g., True-R/B, and data representing
whether or not the second operation is executable when the first
operation is in execution, e.g., Cache-R/B.

[0158] Thus, a program data input operation can be performed concurrently
with a data program operation. Thereby, the time required by the entire
data program sequence is determined by the longer one of the time
required by data input operations and the time required by data program
operations. The operations shorter in required time have no influence on
the time required by the entire sequence. Thus, the time required by the
entire data program sequence can be reduced, allowing a fast data
programming function to be implemented.

[0159] To perform first and second operations whose PASS/FAIL results are
held in the chip after the termination thereof and, when the first and
second operations are performed in succession, to output both of the
PASS/FAIL results of the first and second operations to the outside of
the chip, a semiconductor integrated circuit is simply required to have
the following circuits:

[0160] a PASS/FAIL decision circuit (14) that decides the result of an
immediately preceding operation in the integrated circuit and produces a
PASS/FAIL signal;

[0161] a PASS/FAIL holding circuit (15) that is responsive to the
PASS/FAIL decision circuit to separately hold the PASS/FAIL result of
each of the first and second operations performed successively in the
integrated circuit; and

[0162] a data input/output buffer (4) that outputs the PASS/FAIL results
of the first and second operations held in the PASS/FAIL result holding
circuit to the outside of the chip.

[0163] Further, a cumulative PASS/FAIL result holding circuit may be
provided which cumulatively holds the PASS/FAIL results of the first and
second successive operations. In this case, The cumulative PASS/FAIL
result of the two operations held in the cumulative PASS/FAIL result
holding circuit and/or the PASS/FAIL result of each of the two operations
held in the PASS/FAIL holding circuit can be output to the outside of the
chip via the output circuit.

[0164] FIG. 18 is a block diagram of a NAND-cell EEPROM which is equipped
with the aforementioned cumulative PASS/FAIL result holding circuit in
accordance with the a second embodiment of the present invention.

[0165] This EEPROM differs from the EEPROM of FIG. 4 only in that the
cumulative PASS/FAIL result holding circuit 17 is added. This circuit,
which is connected to the PASS/FAIL decision circuit 14 and the data
input/output buffer 4, accumulates the PASS/FAIL results for more than
one operation produced by the PASS/FAIL decision circuit 14. The
cumulative PASS/FAIL result is sent to the data input/output buffer 4 and
then output to the outside of the chip through the I/O pad I/O-3 as
indicated in Table 5.

[0166] Further, a cumulative data holding circuit which separately holds
more than one cumulative PASS/FAIL result output from the cumulative
PASS/FAIL result holding circuit 17 may be provided. In such a case, the
cumulative data held in the cumulative data holding circuit and/or the
PASS/FAIL result of each of the two operations held in the PASS/FAIL
holding circuit can be output to the outside of the chip via the output
circuit.

[0167] FIG. 19 is a block diagram of a NAND-cell EEPROM which is equipped
with the aforementioned cumulative data holding circuit in accordance
with the a third embodiment of the present invention.

[0168] This EEPROM has the cumulative data holding circuit 18 added to the
EEPROM of FIG. 18. This circuit, which is connected to the cumulative
PASS/FAIL result holding circuit 17 and the data input/output buffer 4,
separately accumulates each of the cumulative PASS/FAIL results output
from the cumulative PASS/FAIL result holding circuit 17. The cumulative
PASS/FAIL results are sent to the data input/output buffer 4 and then
output to the outside of the chip through one of the I/O pads I/O-1
through I/O-8.

[0169] Although the embodiments have been described as using background
operations to program data, the present invention is effective in using
background operations to read data.

[0170] FIG. 20 is a flowchart illustrating an algorithm for a data read
sequence when the present invention is applied to a data read operation
in the circuit of FIG. 8.

[0171] Here, when two or more pages are read in succession, a cell data
read operation and a read data output operation are performed
concurrently.

[0172] When each of the second page and later is read, a cell data read
operation is performed concurrently with a data output operation for the
immediately preceding page.

[0173] Thus, the time required by the entire data read sequence is
determined only by the longer one of the time required by data read
operations and the time required by data output operations. The
operations shorter in required time have no influence on the time
required by the entire sequence.

[0174] In FIG. 20, the time required by each read data transfer operation
is of the order of 2 to 3 μs, the time required by each cell data read
operation is of the order of 25 to 50 μs, and the time required by
each read data output operation is of the order of to 100 μs. Thus,
the time required by the data read sequence is determined by the time
required to read cell data or the time required to output the data read,
whichever the longer.

[0175] In contrast, with the conventional algorithm shown in FIG. 3, the
time required by the entire data read sequence is determined by the sum
of the time required by cell data read operations and the time required
by read data output operations. The algorithm of FIG. 20 can therefore
implement a faster data read sequence than the conventional algorithm.

[0176] FIGS. 21A through 21F schematically show the data read operation by
the circuit of FIG. 8 when the algorithm of FIG. 20 is used.

[0177] FIG. 22A schematically shows a conventional data read operation
control method. In this case, a data read operation is performed in the
foreground on each of the pages.

[0178] FIG. 22B schematically shows a control method for the data read
operation shown in FIGS. 21A through 21F. The operations in intervals
{circle around (1)} to {circle around (6)} in FIG. 22B corresponds to the
operations of FIGS. 21 to 21F, respectively.

[0179] As can be seen from FIGS. 21A through 21F and 22B, the data read
operation for the first page (the operation in interval {circle around
(1)}) uses the same commands COM4 and COM5 as in the conventional data
read operation and is performed in the foreground.

[0180] Each of the cell data read operations (in intervals {circle around
(2)} to {circle around (6)}) subsequent to the first entry of command
COM6 is a background operation and is performed concurrently with a data
output operation.

[0181] The initiation command for a background read operation is COM6.
After entry of this command, a read data transfer (sense
latch→data cache) is first performed with the busy status output,
then a data read operation for the next page is started and the ready
status is output.

[0182] The read data are output in sequence starting with the column 0
address. A specific column address, if desired, can be designated during
read data output operation by inputting it between commands COM8 and COM9
as shown in FIG. 22C.

[0183] For the last page in the data read sequence, there is no need to
reading cell data in the next page at the time the last page data is
output; thus, it is effective to use a command COM7 dedicated to read
data transfer which involves no cell data read operation. The use of the
command COM7 involves no extra cell data read operation, allowing the
operation-required time, i.e., the busy state time, to be reduced.

[0184] FIGS. 23A through 23F shows the ready/busy states for data read
operations when the control method of FIG. 22B is used. In these figures,
address/data inputs are omitted in portions in which command inputs are
described only for the purpose of simplifying illustration.

[0185] The signal "Cache-R/B" in FIGS. 23A through 23F indicates the
aforementioned read/busy states, for example, the ready/busy states in
FIG. 22B and usually corresponds to the chip ready/busy states output
from one of the I/O pads I/O-1 to I/O-8 in FIG. 4. The signal "True-R/B"
represents the in-chip operating states including the background
operations and always assumes the busy state during each background
operation.

[0186] Usually, no PASS/FAIL status is output for data read operations;
thus, data outputs at status read time become as shown in Table 6.

[0187] In the L1 interval in FIG. 23A, a data read operation is performed
independently, which corresponds to a foreground operation. In this case,
the two signals Cache-R/B and True/R/B are coincident in state with each
other.

[0188] FIGS. 23B, 23D and 23E illustrate the read operation intervals and
the busy signal states when two data read operations are performed
successively and a second-operation start command is input after the
termination of the first operation.

[0189] FIGS. 23C and 23F illustrate the read operation intervals and the
busy signal states when two data read operations are performed
successively and a second-operation start command is input during the
first program operation.

[0190] From FIGS. 23A through 23F it can be seen that, when background
operations are involved, the ready/busy states vary with the input times
of operation start commands.

[0191] Valid commands, inhibit commands and ignore commands at the time of
data read background operation execution (when the Cache R/B is at "1"
(ready) and the True R/B is at "0" (busy)) are as follows: The valid
commands include reading-related commands, such as COM6, COM8 and COM9, a
reset command, and status read commands to output the ready/busy state
and the PASS/FAIL state. The inhibit commands and ignore commands, which
are other than the valid commands, include programming-related commands
and erasing-related commands.

[0192] A chip ID output command may be classified under either of valid or
inhibit commands. In order to make circuit arrangements straightforward,
it should preferably be taken into the inhibit commands.

[0193] FIGS. 24A and 24B show the times of inputting valid and inhibit
commands while the NAND-cell EEPROM is in background operation.

[0194] As shown in FIG. 24A, in data program operation, valid commands in
the interval T between the signal Cache R/B changing from the busy state
to the ready state and the signal True R/B changing from the busy state
to the ready state are programming-related commands, such as COM1, COM2
and COM3, status read commands COMS, and reset commands. Other commands
are inhibited or ignored.

[0195] As shown in FIG. 24B, at data read time, valid commands in the
interval T between the signal Cache R/B changing from the busy state to
the ready state and the signal True R/B changing from the busy state to
the ready state are reading-related commands, such as COM1, COM2 and
COM3, status read commands COMS, and reset commands. Other commands are
inhibited or ignored.

[0196] When the last page is read from in the operation of FIG. 24B, a
single read operation is enough for the last page even if the read
command COM6 is input in succession because there is no page to be read
next.

[0197] Thus, when the read command COM6 is input successively for the last
page, an approach can be adopted by which read operations are omitted
when the command is input on and after a second time and the busy state
is output during a short time of, say, 2 to 3 μs or only a read data
transfer operation is performed. In this case, the data read operation
can be omitted, allowing the operation time, i.e., the busy interval to
be reduced.

[0198] The present invention is not restricted to the embodiments
described so far and may be embodied or practiced in still other ways.

[0199] For example, although the embodiments have been described as the
number of series-connected memory cells in each NAND cell being eight,
the principles of the present invention is also applicable to the case
where the number of memory cells is 1, 2, 4, 16, 32, or 64.

[0200] In the embodiment descried above, the data cache circuits and sense
latch circuits are provided, each for two bit lines. Nonetheless, each
data cache and each sense latch circuit may be provided for one bit line,
four bit lines, eight bit lines or 16 bit lines. In this case, too, the
present invention is useful and advantageous.

[0201] Although the embodiments have been described in terms of a
NAND-cell EEPROM, the principles of the present invention are also
applicable to other devices, such as a NOR-cell EEPROM, a DINOR-cell
EEPROM, an AND-cell EEPROM, a NOR-cell EEPROM with select transistors,
etc.

[0202] For example, an equivalent circuit of part of the memory cell array
of a NOR-cell EEPROM is illustrated in FIG. 25. An equivalent circuit of
part of the memory cell array of a DINOR-cell EEPROM is illustrated in
FIG. 26. An equivalent circuit of part of the memory cell array of an
AND-cell EEPROM is illustrated in FIG. 27. And an equivalent circuit of
part of the memory cell array of a NOR-cell EEPROM with select
transistors is illustrated in FIGS. 28 and 29.

[0204] Although the embodiments have been described in terms of a
semiconductor storage device having an electrically rewritable
nonvolatile memory cell array. The principles of the present invention
are also applicable to other semiconductor storage devices and other
semiconductor integrated circuits.

[0205] The present invention may be practiced or embodied in still other
ways without departing from the scope and spirit thereof.

[0206] Additional advantages and modifications will readily occur to those
skilled in the art. Therefore, the invention in its broader aspect is not
limited to the specific details and representative embodiments shown and
described herein. Accordingly, further various modifications may be made
without departing from the spirit or scope of the general inventive
concept as defined by the appended claims and their equivalents.