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Digital ICs: Standard Logic

Commodity Logic: The Jellybeans Of The Digital World
The variety of transistors born in the '50s foreshadowed the logic industry of the '60s and '70s. As transistors entered the digital world by forming discrete component flip-flops and gates in the mid-'50s, the necessity of standardized building blocks became apparent. In the late '50s, IBM (www.ibm.com), Digital Equipment, and others created families of small plug-in boards or modules based on discrete bipolar transistors. Each board or module contained the equivalent of a few gates, a flip-flop, a decoder, and so on. And then in 1958, Texas Instruments (www.ti.com) invented the IC, which was a logic circuit.

Integration improved, and in 1960 Fairchild Semiconductor (www.fairchildsemi.com) released its Micrologic resistor-transistor logic (RTL) family. By 1961, both Fairchild and TI were making available off-the-shelf logic circuits. By 1964, a higher-speed logic structure, diode-transistor logic (DTL), was created to build a wide array of logic functions.

Meanwhile, other companies developed a form of transistor-coupled logic. Better known as transistor-transistor logic (TTL), it first commercially appeared in 1963 in the form of a logic building-block family developed by Sylvania—SUHL for Sylvania universal high-level logic. Many companies jumped on the bandwagon. Over the next decade and a half, they created thousands of industry-standard circuits based on TTL. For the highest-performance applications, Fairchild, Motorola (www.motorola.com), and others also developed families of emitter-coupled logic (ECL) circuits that reached multihundred-megahertz speeds.

While work in bipolar technology moved forward, researchers experimented with metal-oxide structures. In the late '50s, the MOSFET was born. With the development of MOS transistors, researchers took about five years to create proof-of-concept logic circuits. In 1962, RCA crafted a 16-transistor multipurpose logic circuit. By 1965, companies could turn p-channel MOS technology into a production technology that could integrate about 1000 elements on a chip.

Not until the development of complementary metal-gate MOS technology in the late '60s did generic standard logic circuits start to appear. The RCA CD4000 series was among the first standard logic families based on CMOS. It offered functional equivalents to many popular TTL functions at power-consumption levels of about one-fifth to one-tenth those of the TTL parts, albeit at slightly lower operating frequencies.

But bipolar TTL still ruled the roost. Through the '70s, TTL variations came at a fast and furious pace. A high-noise-immunity version (HNIL) was developed, such as TI's 54/74 H series. Faster versions of TTL using Schottky diodes then emerged. Called the 54/74 S series, these let the logic operate at speeds of well over 100 MHz. By the early '80s, a veritable alphabet soup of logic family variants had been released, and designers needed a scorecard to help determine which family best fit each application. Operating voltage levels also started to shrink in the mid-'80s, with a 3.3-V standard starting to build some momentum.

Despite all this diversity, a "subversive" trend began appearing in the form of programmable logic arrays. User programmable, the first generations of these chips replaced five to 10 logic gates. As logic integration improved, these PLDs and gate arrays were able to replace more and more standard logic functions. The logic families had begun to turn into logic configuration patterns for PLDs or cell libraries for gate arrays.

The overwhelming progression by ASICs to usurp commodity logic continued to the point that by the mid-'90s, no new generic logic functions were being introduced. A packaging option called single-gate logic then appeared. In the TTL days, designers typically purchased devices that actually contained multiple instances of the desired function. For example, the 7400 was a quadruple two-input NAND gate. Single-gate devices, housed in ultra-small surface-mount packages, provided the perfect solution when only one of something was needed.

The shrinking feature sizes used in higher-performance processes let circuits operate at higher clock frequencies,which in turn increased circuit power demands. This forced IC designers to further reduce operating voltages.

Designers then faced the challenge of working with multiple signal levels in a system—some 5-V legacy circuits, some 3.3-V logic, some 2.5-V, and now 1.8-V ASICs, and soon the 1.2-V parts. The need had arisen for circuit families that could provide level translation, bus latching, and buffering. Other support functions for the complex microprocessors and system buses that evolved in the late '80s and '90s created a need for level translators, bus drivers, latches, and so forth. PLDs and ASICs were basically overkill for these applications.

Today, bus-interface logic is the "TTL" of the new millennium. Device propagation delays have shrunk from the 8 to 10 ns of the TTL days to the sub-3 ns required by the 100-MHz and faster buses used in today's systems. Future systems will have faster buses with even lower voltages of as little as 0.9 V. This will demand another generation of bus-interface circuits. Some of those buses, though, will be serial rather than parallel, giving rise to another class of commodity circuit, the serializer/deserializer (SERDES). It takes in parallel data on one end and delivers a 2.5-Gbit/s data stream on the other end, or vice versa. Low-voltage differential signaling (LVDS) has been employed for several years as a point-to-point connection, permitting data-transfer rates of up to 600 Mbits/s. Higher-speed and multidrop bus-oriented versions of LVDS are starting to appear.

Shorter propagation delays are in the wings for bus-interface circuits. Today's 2- to 3-ns delays will shrink by close to 50% over the next 12 to 24 months, making possible buffers and translators that operate at speeds exceeding 400 MHz.

Lower standby power levels will become critical as more systems go portable. New circuits will employ clock-gating and signal-sensing schemes to minimize power drain.

Higher-density interface circuits will pack more buffers and latches on a chip to reduce package count on boards.

As operating voltages go down, signal swings get smaller and there's a greater need for LVDS schemes that can handle data rates of 600 Mbits/s and higher.

Expect programmable logic devices and ASICs to continue replacing most general logic functions.

Serial backplane drivers will become more popular as designers try to minimize bus widths and chip pin counts. Today's 2.5-Gbit/s SERDES chips will give way to chips that can operate at 5 Gbits/s.

Expect a wider variety of clock buffering and distribution chips to reduce signal skews and improve system performance.

More high-speed standard serial interface choices will appear—infiniband, hypertransport, and others to meet the need for higher I/O bandwidth.

A continued interest in single-gate packaged logic elements will extend into this decade because these devices provide point solutions to designers in need of a gate here, a flip-flop there, an inverter somewhere else, and so on.

Look also for LVDS to work in multidrop bus structures as opposed to point-to-point connections.