Cavium Debuts 48-Core ARM Server Chip

Back in June, silicon vendor Cavium first announced its ThunderX System-on-a-Chip (SoC) lineup. Today Cavium announced that the ThunderX chips are now available, including an industry first — a 48-core ARMv8 processor.

The four ThunderX product families include ThunderX_CP for Cloud compute workloads, ThunderX_ST for Cloud storage, ThunderX_NT for networking applications and ThunderX_SC for secure computing.

Rishi Chugh, Director, Product Marketing in the Data Center Processor Group at Cavium, told ServerWatch that all four families within ThunderX are enabled with a 48-core SKU.

"In all of them the dual-socket configuration for a 96-core sever will mandate both the socket SKUs to be a 48-core part," Chugh said.

In a dual-socket deployment, the ThunderX platform can support up to 1 TB of DDR4 server memory running at up to 2400MHz. The dual-socket server configuration also benefits from Cavium's Coherent Processor Interconnect (CCPI) technology, making a a dual-socket system fully cache coherent.

From an operating system perspective, Cavium's MontaVista software division worked on optimizing its Linux distribution for the new ThunderX SoC. Chugh also noted that Cavium's other distribution partners, including Canonical and Red Hat, have been working on enabling Linux on ThunderX.

In addition to the SoCs, Cavium has also announced new reference platforms for1U and 2U servers using the ThunderX. The ThunderX 2K is the dual-socket reference platform and can accommodate up to 4 sleds of ThunderX SoCs.

The 1U ThunderX 1K server reference architecture is a single-socket configuration for the ThunderX SoCs.

"ThunderX is our flagship ARMv8 multi-core processor family with the highest core counts and the most comprehensive set of I/O and accelerators in the market," Gopal Hegde, VP/GM of Data Center Processor Group at Cavium, said in a statement. "ThunderX is a disruptive technology that enables our customers to deliver highly integrated, high performance, best-in-class platforms."