SPIE Advanced Lithography is known for featuring up-to-the minute news on key lithography issues, and this year’s event certainly didn’t disappoint. The so-called “battle” between immersion extension and EUV solutions featured heavily during the conference, as well as in the press. In case you weren’t able to attend this year’s conference or were merely overwhelmed by the number of technical sessions and subject areas being featured, we’ve compiled an overview of the “hot topics” around the annual lithography convention as reported through various media channels.

The extremely full week kicked off with a number of expert discussions on immersion extension capabilities at the Nikon LithoVision symposium on Sunday. Dan Hutcheson of VLSIresearch discussed the LithoVision presentations in the March 21st edition of The Chip Insider®, and excerpts of his comments are included below.

Chris Bencher of Applied Materials believes there is a long way to go before EUV will be essential. He pointed out that SADP (Self-Aligned-Double-Patterning) with immersion took us from 40nm to 20 between 2008 to 2010. There is lots of headroom, because a lot of process related improvements that we know work today have yet to be implemented. As he put it, we are only “about halfway through immersion’s lifecycle.”

Yuichi Shibazaki of Nikon discussed the performance of the coming S630D…Nikon is quoting mix-and-match overlay of <2.50 nm and single machine of <1.70 nm … phenomenal! Focus uniformity of 6.7 nm (3-sigma) has been achieved. All this with a 5000 wafer-per-day productivity.

Stephen Renwick of Nikon then concluded things with an all-out assault on EUV economics, showing graphs demonstrating that 193i can do better than EUV until EUV can do >100 wph.

LithoVision was followed by a myriad of invaluable SPIE technical presentations that continued through late in the day on Thursday. Ongoing challenges with EUV development featured prominently throughout SPIE and surrounding media. The Semiconductor Engineering website (semiengineering.com) included several postings on this subject, as did Semiconductor Manufacturing & Design (semimd.com).

2/24/14: Mark LaPedus reported that “During the trial run at TSMC, the EUV source crashed due to a misalignment of the laser mechanism within the EUV source itself. This, in turn, caused the EUV scanner to go down.” It was further explained that “…the disclosure represents the latest in a series of setbacks for the problem-plagued EUV. Many of the problems with EUV can be traced to the power source. In fact, EUV continues to get pushed out amid a myriad of technical problems, such as the power source, EUV masks and resists.” Additionally, he noted that “A 55 Watt source translates to an EUV throughput of 43 wafers an hour. However, the industry is looking for an 80 Watt source, which could make EUV somewhat viable in chip production.” (semiengineering.com)

3/4/2014: In a SPIE summary, Vivek Bakshi commented that “IMEC presented a preliminary cost of ownership (COO) study that concluded that at the 7 nm node, 75 wafers per hour (WPH) throughput will be needed for EUVL to show better COO than ArF immersion (ArFi) multiple patterning (MP). This throughput corresponds to 100 W of source power at the intermediate focus. In addition, “Starting at 7 nm, a decision has to be made on going with either high NA of 0.5, or with EUV at 0.33 NA and double patterning. At < 7 nm, scanners with >0.33 NA will be needed. High NA will increase the incident angle on mask, resulting in excessive H-V bias and poor image quality. So the industry has to decide on various potential options, which include going from six to eight mirrors in scanners, mask size change from current 6 to 12 inches, and quarter- to full-field exposure options.” (semimd.com)

3/20/14: Marc Levenson separately commented “…unfortunately, during the low-power exposures, a bit of dust fell on the reticle surface, resulting in a new repeating defect, according to Jack Chen of TSMC. That one wafer illustrated the need for EUV pellicles in addition to some means to find and hide — or correct — 2nm to 3nm mask phase defects. So, more innovations are needed before EUVL can be used in high-volume production. If they came in time for the 11nm node, Chen predicted that 13.5nm EUVL would have to be used in a double patterning mode anyway!” (semiengineering.com)

3/20/14: A follow-up article by Mark LaPedus highlighted a growing pessimism about EUV. “We think customers have become increasingly frustrated with the slow rate of EUV progress,” said Weston Twigg, an analyst with Pacific Crest Securities. “Chipmakers appear resigned to the fact that EUV is late, and understand that it may not ever be fully ready for mass production. So, there is an intensifying focus on how to extend immersion lithography.” LaPedus further reported that “… EUV would require a multiple patterning scheme at 7nm. EUV with double patterning is 2.5 times the cost per wafer, as compared to 193nm immersion with double patterning, according to Nikon. Meanwhile, in one cost-of-ownership model, Imec compared the processing costs in ideal conditions between single-exposure EUV versus 193nm immersion and multiple patterning at 7nm. In one application, Imec looked at gate patterning. Surprisingly, an EUV tool with a throughput of 50 wafers per hour (wph) increased gate module processing costs by almost 120%, as compared to 193nm immersion with multiple exposures, according to Imec.” (semiengineering.com)

Directed Self-Assembly (DSA) and its immersion extension capabilities also garnered a great deal of focus in the conference again this year. The Semiconductor Engineering website (semiengineering.com) featured the post below on this subject.

3/20/14: Mark LaPedus reported that “DSA is making remarkable progress and is gaining momentum in the market. At SPIE, for example, Intel and others formed a new DSA consortium. In addition, GLOBALFOUNDRIES, IBM, Samsung and TSMC are still working on DSA in R&D, but vendors are keeping their cards close to the vest. Still, the consensus among chipmakers is that DSA could be ready for high-volume manufacturing at 7nm or 5nm. ’Intel is talking about an introduction at the 5nm node. I have the feeling that the memory people could introduce it sooner, maybe in 2015 to 2016,’ said Serge Tedesco, lithography program manager at CEA-Leti, which is also part of the new DSA consortium with Intel.” In addition, LaPedus highlighted that “DSA is also disruptive and threatens the status quo, because the process isn’t dependent on costly lithography. In fact, DSA makes use of existing lithography tools. All the key processing steps are conducted in a wafer track system. Using 193nm immersion lithography, DSA has demonstrated the ability to pattern structures down to 12.5nm. The industry also is working on next-generation, high chi materials, which could extend the technology beyond 12.5nm, thereby pushing out the need for extreme ultraviolet (EUV) lithography. By most accounts, though, DSA will not appear until 7nm.”

450 mm tooling development also continues to be a key topic for lithographers and was discussed in Nikon LithoVision presentations. Dan Hutcheson commented on this in The Chip Insider®.

3/21/14: Dan Hutcheson reported that “Nikon simply does not believe that lithography will take a throughput hit in the move to 450mm wafers, as they will continue to push the speed envelope. One thing for sure, Nikon is committed to 450mm cost effectiveness. If you doubt this consider that Nikon will deliver a 450mm pilot litho tool to Albany in the first half of 2015.” He also explained “As for 450 mm, Nikon believes it will need a revolutionary new platform and they will design it. Several years ago they started to form a concept, and then commenced to building a 450mm platform the next year. So far, they’ve built five machines and they are in the process of debugging them. They will begin patterning 450 mm wafers in the factory for the G450C in the coming months.”

SPIE Advanced Lithography week is definitely one of the annual highlights in our industry. There were many impressive findings and advancements reported this year, in addition to lingering technical challenges. As Ed Sperling emphasized in a March 20th Semiconductor Engineering website (semiengineering.com) posting “The bottom line is that lithography has shaken up the entire industry, and good things usually come out of that kind of disruption.” The industry must strive for continued innovation and cooperation in order to enable timely, cost-effective, next-generation manufacturing.