Because they aren't really "buses" in the traditional sense? They are direct links to on-chip memory. The diagram is posted shows this as "channel", as far as I understand, so personally, I didn't think it actually had a name.

And it's not one way or another..it's both. FCL for cache hits, RMB for system-memory access.

Because they aren't really "buses" in the traditional sense? They are direct links to on-chip memory. The diagram is posted shows this as "channel", as far as I understand, so personally, I didn't think it actually had a name.

Yeah, they're tightly integrated between the CPU and GPU parts of the chip hence "Fusion" and are likely to be physically very short too, but they're still there. That's all I'm saying. How else could the GPU push data and address memory?

There is definitely an interface with a well defined protocol. The CPU and GPU cores are simply tightly integrated, hence the name "Fusion" - AMD even named them as I pointed out above.

My point might seem pedantic* but it's good practice to call things by their proper names, especially in a utility that is distributed widely. The fact it isn't is what caused the OP to feel confused about it in the first place. He would not have been with the correct names.

There is definitely an interface with a well defined protocol. The CPU and GPU cores are simply tightly integrated, hence the name "Fusion" - AMD even named them as I pointed out above.

My point might seem pedantic* but it's good practice to call things by their proper names, especially in a utility that is distributed widely. The fact it isn't is what caused the OP to feel confused about it in the first place. He would not have been with the correct names.