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2. The method of claim 1, wherein applying a bit-based conditional coding comprises coding using one or more binary-valued variables, the value depending on whether one or more conditions applied to the coefficient being coded is true or false.

3. The method of claim 2, wherein at least one of the one or more conditions relates to the magnitude of the coefficient being coded relative to a threshold.

4. The method of claim 1, wherein the DWT coefficients are coded using multiple passes, and wherein the threshold of the next successive pass from a particular pass is a multiplicative factor greater than one times the threshold of the
particular pass.

8. The integrated circuit of claim 7, wherein the architecture comprises at least one of the following: hardware, software, firmware, and any combination thereof.

9. The integrated circuit of claim 7, wherein the architecture is adapted to apply a bit-based conditional coding comprising coding using one or more binary-valued variables, the value depending on whether one or more conditions applied to the
coefficient being coded is true or false.

10. The integrated circuit of claim 9, wherein at least one of the one or more conditions that the architecture is adapted to apply relates to the magnitude of the coefficient being coded relative to a threshold.

11. The integrated circuit of claim 7, wherein the architecture is adapted to code the DWT coefficients in multiple passes, and wherein the threshold of the next successive pass from a particular pass is a multiplicative factor greater than one
times the threshold of the particular pass.

12. The integrated circuit of claim 11, wherein the multiplicative factor is two.

13. A method of embedded zero tree decoding discrete wavelet transform (DWT) coefficients that have been encoded, said method comprising: applying a bit-based conditional decoding to the encoded DWT coefficients, including checking zero tree
root for each coefficient.

14. The method of claim 13, wherein applying a bit-based conditional decoding comprises decoding using one or more binary-valued variables, the value depending on whether one or more conditions was true or false when applied during encoding to
the coefficient being decoded.

15. The method of claim 14, wherein at least one of the one or more conditions relates to the magnitude relative to a threshold, during encoding, of the coefficient being decoded.

17. An integrated circuit comprising: an architecture to apply a bit-based conditional embedded zero tree decoding to discrete wavelet transform (DWT) coefficients that have been encoded, including checking zero tree root for each coefficient.

18. The integrated circuit of claim 17, wherein the architecture comprises at least one of the following: hardware, software, firmware, and any combination thereof.

19. The integrated circuit of claim 17, wherein the architecture is adapted to apply a bit-based conditional decoding comprising decoding using one or more binary-valued variables, the value depending on whether one or more conditions was true
or false when applied during encoding to the coefficient being decoded.

20. The integrated circuit of claim 19, wherein at least one of the one or more conditions relates to the magnitude relative to a threshold, during encoding, of the coefficient being decoded.

21. An article comprising: a storage medium having stored thereon instructions that, when executed by a computing platform, result in a method of embedded zero tree coding discrete wavelet transform (DVVT) coefficients being preformed by:
applying a bit-based conditional coding to the DWT coefficients, including checking zero tree root for each coefficient.

22. The article of claim 21, wherein said instructions, when executed, further result in applying a bit-based conditional coding comprises coding using one or more binary-valued variables, the value depending on whether one or more conditions
applied to the coefficient being coded is true or false.

23. The article of claim 22, wherein said instructions, when executed, further result in at least one of the one or more conditions relating to the magnitude of the coefficient being coded relative to a threshold.

24. An article comprising: a storage medium having stored thereon instructions that, when executed by a computing platform, result in a method of embedded zero tree decoding discrete wavelet transform (DWT) coefficients that have been encoded
by: applying a bit-based conditional decoding to the encoded DWT coefficients, including checking zero tree root for each coefficient.

25. The article of claim 24, wherein said instructions, when executed, further result in applying a bit-based conditional decoding comprises decoding using one or more binary-valued variables, the value depending on whether one or more
conditions was true or false when applied during encoding to the coefficient being decoded.

26. The article of claim 25, wherein said instructions, when executed, further result in at least one of the one or more conditions relating to the magnitude relative to a threshold, during encoding, of the coefficient being decoded.

27. A system comprising: a computing platform; said computing platform including a processor, a memory, and a bus for communication to occur between said processor and memory; said computing platform including an architecture adapted to,
during operation, perform a method of embedded zero tree coding discrete wavelet transform (DWT) coefficients by applying a bit-based conditional coding to the DWT coefficients, including checking zero tree root for each coefficient.

28. The system of claim 27, wherein the architecture comprises at least one of the following: hardware, software, firmware, and any combination thereof.

29. The system of claim 27, wherein the architecture is adapted to, during operation, apply a bit-based conditional coding comprising coding using one or more binary-valued variables, the value depending on whether one or more conditions applied
to the coefficient being coded is true or false.

30. A system comprising: a computing platform; said computing platform including a processor, a memory, and a bus for communication to occur between said processor and memory; said computing platform including an architecture adapted to,
during operation, perform a method of embedded zero tree decoding encoded discrete wavelet transform (DWT) coefficients by applying a bit-based conditional decoding to the encoded DWT coefficients, including checking zero tree root for each coefficient.

31. The system of claim 30, wherein the architecture comprises at least one of the following: hardware, software, firmware, and any combination thereof.

32. The system of claim 30, wherein the architecture is adapted to, during operation, apply a bit-based conditional decoding comprising decoding using one or more binary-valued variables, the value depending on whether one or more conditions
applied to the coefficient being decoded was true or false when applied during encoding to the coefficient being decoded.

Description

BACKGROUND

This disclosure is related to image compression and/or decompression.

As is well-known, discrete wavelet transform (DWT) approaches have been employed in compression and decompression of images and video. One aspect of these approaches frequently employs a process often referred to as embedded zerotree (EZT)
coding or encoding. Some of the drawbacks of the existing embedded zero tree coding process include two passes for each level of coding, ie, a dominant pass and a subordinate pass, and, high computational complexity not suitable for interactive video
compression. A need, therefore, exists for an approach to EZT coding that addresses these issues.

BRIEF DESCRIPTION OF THE DRAWINGS

Subject matter is particularly pointed out and distinctly claimed in the concluding portion of the specification. The claimed subject matter, however, both as to organization and method of operation, together with objects, features, and
advantages thereof, may best be understood by reference of the following detailed description when read with the accompanying drawings in which:

FIG. 1 is a schematic diagram illustrating an order for scanning coefficients of a transformed image;

FIG. 2 is a schematic diagram illustrating subbands formed in a transformed image; and

FIG. 3 is a schematic diagram illustrating an order for scanning coefficients of a transformed image for an embodiment;

FIG. 4 is a schematic diagram illustrating a typical parent-child relationship for subbands in a transformed image;

FIG. 5 is a flowchart illustrating an embodiment to be applied to code wavelet transformed coefficients;

FIG. 6 is a sample portion of a transformed image to be coded;

FIG. 7 is the sample portion of FIG. 6 at a point in a process of applying the embodiment of FIG. 5;

FIG. 8 is the sample portion of FIG. 6 at a point in a process of applying the embodiment of FIG. 5;

FIG. 9 is the sample portion of FIG. 6 at a point in a process of applying the embodiment of FIG. 5;

FIG. 10 is the sample portion of FIG. 6 at a point in a process of applying the embodiment of FIG. 5;

FIG. 11 is the sample portion of FIG. 6 at a point in a process of applying the embodiment of FIG. 5;

FIG. 12 is the encoded sample portion of FIG. 11 at a point in a process of applying an embodiment to decode the encoded sample portion;

FIG. 13 is the encoded sample portion of FIG. 11 at a point in a process of applying an embodiment to decode the encoded sample portion;

FIG. 14 is the encoded sample portion of FIG. 11 at a point in a process of applying an embodiment to decode the encoded sample portion;

FIG. 15 is the encoded sample portion of FIG. 11 at a point in a process of applying an embodiment to decode the encoded sample portion;

FIG. 16 is the encoded sample portion of FIG. 11 at a point in a process of applying an embodiment to decode the encoded sample portion;

FIG. 17 is the encoded sample portion of FIG. 11 at a point in a process of applying an embodiment to decode the encoded sample portion; and

FIG. 18 is the encoded sample portion of FIG. 11 at a point in a process of applying an embodiment to decode the encoded sample portion.

DETAILED DESCRIPTION

In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the claimed subject matter. However, it will be understood by those skilled in the art that the claimed subject matter
may be practiced without the se specific details. In other instances, well-known methods, procedures, components and circuits have not been described in detail in order so as not to obscure the claimed subject matter.

An embodiment of a method and apparatus for coding wavelet transformed coefficients is provided that provides an improvement over current EZT coding approaches in terms of computational complexity and compression performance. One aspect of this
improvement, for this particular embodiment, although, of course, the claimed subject matter is not limited in scope to this particular embodiment, is a reduction in computational complexity by reducing the number of scans performed during the EZT coding
process, as described in more detail hereinafter.

As shall also be described in greater detail infra., for this embodiment, a bit-based conditional coding is applied to the DWT coefficients. For example, during coding, one or more binary-valued variables, eg, a bit, is employed, where the value
of the variable depends on whether one or more conditions applied to the coefficient being coded is true or false. As just one example, a condition may relate to the absolute value of the coefficient compared relative to a threshold. Likewise,
typically, DWT coefficients have multiple levels. In this particular embodiment, the threshold of the next sequentially increasing level from a particular level of DWT coefficients is a multiplicative factor greater than one times the threshold of the
particular level. For example, the embodiment described infra. employs a multiplicative factor of two, although, again, the claimed subject matter is not limited in scope in this respect. Typically, although not necessarily, such an embodiment
provides improved results when applied to low energy DWT coefficients, that is, where several of the coefficients are zero or near zero.

In this embodiment, the discrete wavelet transform (DWT) decomposes an image into four subbands, one low frequency subband (LL) and three high frequency subbands (LH, HL, HH). The LL subband has the characteristics of the original image and may
be decomposed in multiple levels as shown in FIG. 1.

Again, for this particular embodiment, when applying embedded coding of the wavelet coefficients, a particular order of scanning is employed. The coefficients are scanned in the order as shown by the arrows in FIG. 1, so that a child coefficient
is not scanned before its parent is scanned. The scan starts from the lowest frequency subband (LL3), and does not move to another subband until the coefficients of the present subband are scanned. Once the scanning of the subbands of one level of
transform is complete, the scan moves to the next level of subbands. The scanning inside a subband is done row-wise in this particular embodiment.

In this embodiment, improved efficiency may result from the following approach. If the magnitude of a coefficient (c) is not significant with respect to a certain threshold (T.sub.0), i.e., .vertline.c.vertline..ltoreq.T.sub.0, then it is also
not significant for the remaining levels. In this embodiment, the threshold values for subsequent passes are larger in magnitude than T.sub.0.

As shown in FIG. 2, the DWT matrices are discrete wavelet transformed (DWT) with the resultant subbands of the form illustrated. The labels (1, 2, 3) indicate the level number of the subbands.

In this embodiment, the starting threshold is taken as 1, although, of course, the claimed subject matter is not limited to a particular starting threshold. In each successive pass, the threshold is doubled, although, again, as previously
indicated, the thresholds are not limited to being doubled. The total number of such passes for this embodiment is .left brkt-bot.log.sub.2 (max).right brkt-bot.+1, where "max" denotes the maximum value among the magnitudes of the coefficients to be
encoded, again, for this particular embodiment. The scanning pattern for the coefficients employed in this embodiment is shown in FIG. 3.

A parent-child relation for DWT coded frames is shown in FIG. 4. The four pixels at level 2 are the children of the pixel marked in level 1. The sixteen pixels at level 3 are also the descendants of marked pixel in the 1.sup.st level. As
previously indicated, in this embodiment, the coefficients are scanned in such a way so that no finer level coefficient is scanned before the coarser ones, as indicated in FIG. 4.

As previously indicated, here bit-based conditional coding approach is employed. In standard EZT coding processes, for every condition, a symbol, eg, P, N, R, IZ, each taking 2 bits to code, is generated. In this particular embodiment, instead,
a bit 1 or 0 may be coded, depending on whether the particular condition is true or false.

Here, the LL subband is not included in the bit-plane coding. The LL subband is directly stored or transmitted, instead. One may, therefore, independently encode the wavelet coefficients in the LL subband using any coding technique, such as a
lossless variable-length encoding technique, including, for example, arithmetic coding, Huffman coding, Lempel-Ziv coding, etc.

A flowchart to illustrate one embodiment is shown in FIG. 5.

The following example will assist in the understanding of the coding scheme, although, of course, this example in no way limits the scope of the claimed subject matter. This example is provided merely for illustration. For example, while this
example is applied to wavelet coefficients with low energy content in two dimensions (2D), this approach is extendable to three dimensional (3D) wavelet transforms.

The coefficients shown in FIG. 6 are provided in binary representation. The maximum value of the coefficients is max=4 (100). Hence, the total number of passes, applying the previous embodiment, is 3. Therefore, pass_index varies from 1 to 3.

Below, notation is employed to designate representation which bit is being coded in the matrix of FIG. 6. In this example, one matrix of 2.times.2 size at level 1 (subband #1) and one matrix of size 4.times.4 at level 0 (subband #2) is provided. The pass index varies from 1 to 3. Here, counting is done in reverse order, e.g., for the coefficient 001, if the pass index is 3, we are coding the most significant bit (MSB) of the coefficient and so on, although, of course, other conventions may
alternatively be used.

The coefficient which is coding is represented here as C.sub.Li (x,y). "Li" represents the level in which the coefficient is coded, where "i" varies from 0 to number of levels. In this example, "i" takes 0 and 1. Likewise, "x,y" denotes the
array location. The bit coded is represented by B.sub.Pj.sup.Li (x, y) where "Li" represents the level in which it is coded, and "Pj" represents the pass index. An illustrative example of this notation is as follows:

C.sup.L0 (4,4) represents the coefficent in level 0 (subband #2) which is in the 4.sup.th row and 4.sup.th column.

B.sub.P2.sup.L1 (2,2) represents the bit `1` in the level 1 (subband #1) and in the second pass (middle bit) of the 2.sup.nd row and 2.sup.nd column.

For coding the above mentioned example, three passes, designated p1, p2, and p3, are employed, and the pass index will decide the threshold to employ to determine the significance of the coefficient. In this context, `significance of the
coefficient` means comparing the whole value of the coefficient with respect to the appropriate threshold and, in this context, `significance of the bit` refers to comparing the value of the bit in that plane.

Below, this particular embodiment is applied to the example from FIG. 6. Initially, the pass_index is one and the threshold (T.sub.0) is one, although, again, the claimed subject matter is not limited to this example. For these values, the
conditions indicated below in the left hand column are evaluated. If the condition is true, a "1" bit is generated. If the condition is false, a "0" bit is generated

For Pass_Index=1, T.sub.0 (Threshold)=1;

Subband #1: Bits Generated For the bit B.sub.P1.sup.L1 (1,1) of the coefficient C.sup.L1 (1,1) Is the bit significant ? yes :1 Is the sign bit recorded? no Is the symbol +ve ? yes :1 Is the .vertline.C.sup.L1 (1,1).vertline. > T.sub.o ?
no :0 Is the bit in level 0 ? no Is .vertline.C.sup.L1 (1,1).vertline..sub.children >= T.sub.o ? yes :1 Is the bit form ZTR ? no :0 For the bit B.sub.P1.sup.L1 (1,2) of the coefficient C.sup.L1 (1,2) Is the bit significant ? yes :1 Is the sign
bit recorded? no Is the symbol +ve ? yes :1 Is the .vertline.C.sup.L1 (1,2).vertline. > T.sub.o ? no :0 Is the bit in level 0 ? no Is .vertline.C.sup.L1 (1,2).vertline..sub.children >= T.sub.o ? yes :1 Is the bit form ZTR ? no :0 For the bit
B.sub.P1.sup.L1 (2,1) of the coefficient C.sup.L1 (2,1) Is the bit significant ? no :0 Is the .vertline.C.sup.L1 (2,1).vertline. > T.sub.o ? no :0 Is the bit in level 0 ? no Is .vertline.C.sup.L1 (2,1).vertline..sub.children >=0 T.sub.o ? yes
:1 Is the bit form ZTR ? yes :1 For the bit B.sub.P1.sup.L1 (2,2) of the coefficient C.sup.L1 (2,2) Is the bit significant ? no :0 Is the .vertline.C.sup.L1 (2,2).vertline. > T.sub.o ? yes :1 Is the bit in level 0 ? no Is .vertline.C.sup.L1
(2,2).vertline..sub.children >= T.sub.o ? yes :1 Is the bit form ZTR ? no 0

Therefore, in this example of application of one possible embodiment, for subband #1 the following 18 bits are generated: 1, 1, 0, 1, 0; 1, 1, 0, 1, 0; 0, 0, 1, 1; 0, 1, 1, 0. The marked-matrix after this stage of processing is illustrated in
FIG. 7. In this example, bits marked with an underline are not to be traversed or coded in later passes.

Subband #2 Bits Generated For the bit B.sub.P1.sup.L0 (1,1) of the coefficient C.sup.L0 (1,1) Is the bit significant ? no :0 Is the .vertline.C.sup.L0 (1,1).vertline. > T.sub.o ? yes :1 Is the bit in level 0 ? yes For the bit
B.sub.P1.sup.L0 (1,2) of the coefficient C.sup.L0 (1,2) Is the bit significant ? yes :1 Is the sign bit recorded ? no Is the symbol +ve ? yes :1 Is the .vertline.C.sup.L0 (1,2).vertline. > T.sub.o ? no :0 Is the bit in level 0 ? yes For the bit
B.sub.P1.sup.L0 (2,1) of the coefficient C.sup.L0 (2,1) Is the bit significant ? yes :1 Is the sign bit recorded ? no Is the symbol +ve ? no :0 Is the .vertline.C.sup.L0 (2,1).vertline. > T.sub.o ? no :0 Is the bit in level 0 ? yes For the bit
B.sub.P1.sup.L0 (2,2) of the coefficient C.sup.L0 (2,2) Is the bit significant ? no :0 Is the .vertline.C.sup.L0 (2,2).vertline. > T.sub.o ? no :0 Is the bit in level 0 ? yes For the bit B.sub.P1.sup.L0 (1,3) of the coefficient C.sup.L0 (1,3) Is
the bit significant ? no :0 Is the .vertline.C.sup.L0 (1,3).vertline. > T.sub.o ? no :0 Is the bit in level 0 ? yes For the bit B.sub.P1.sup.L0 (1,4) of the coefficient C.sup.L0 (1,4) Is the bit significant ? no :0 Is the .vertline.C.sup.L0
(1,4).vertline. > T.sub.o ? no :0 Is the bit in level 0 ? yes For the bit B.sub.P1.sup.L0 (2,3) of the coefficient C.sup.L0 (2,3) Is the bit significant ? no :0 Is the .vertline.C.sup.L0 (2,3).vertline. > T.sub.o ? yes :1 Is the bit in level 0
? yes For the bit B.sub.P1.sup.L0 (2,4) of the coefficient C.sup.L0 (2,4) Is the bit significant ? yes :1 Is the sign bit recorded ? no Is the symbol +ve ? yes 1 Is the .vertline.C.sup.L0 (2,4).vertline. > T.sub.o ? yes :1 Is the bit in level 0
? yes For the bit B.sub.P1.sup.L0 (3,3) of the coefficient C.sup.L0 (3,3) Is the bit significant ? no :0 Is the .vertline.C.sup.L0 (3,3).vertline. > T.sub.o ? no :0 Is the bit in level 0 ? yes For the bit B.sub.P1.sup.L0 (3,4) of the coefficient
C.sup.L0 (3,4) Is the bit significant ? yes :1 Is the sign bit recorded? no Is the symbol +ve ? no 0 Is the .vertline.C.sup.L0 (3,4).vertline. > T.sub.o ? no :0 Is the bit in level 0 ? yes For the bit B.sub.P1.sup.L0 (4,3) of the coefficient
C.sup.L0 (4,3) Is the bit significant ? yes :1 Is the sign bit recorded ? no Is the symbol +ve ? yes 1 Is the .vertline.C.sup.L0 (4,3).vertline. > T.sub.o ? no :0 Is the bit in level 0 ? yes For the bit B.sub.P1.sup.L0 (4,4) of the coefficient
C.sup.L0 (4,4) Is the bit significant ? no :0 Is the .vertline.C.sup.L0 (4,4).vertline. > T.sub.o ? no :0 Is the bit in level 0 ? yes

Subband #1: Bits Generated For the bit B.sub.P2.sup.L1 (2,2) of the coefficient C.sup.L1 (2,2) Is the bit significant ? yes :1 Is the sign bit recorded? yes Is the symbol +ve ? no :1 Is the .vertline.C.sup.L1 (2,2).vertline. > T.sub.o ?
no :0 Is the bit in level 0 ? no Is .vertline.C.sup.L1 (2,2).vertline..sub.children >= T.sub.o ? no :0

The following four bits are generated for subband #1: 1, 1, 0, 0. The marked-matrix is illustrated in FIG. 9.

Subband #2: Bits Generated For the bit B.sub.P2.sup.L0 (1,1) of the coefficient C.sup.L0 (1,1) Is the bit significant ? no :0 Is the .vertline.C.sup.L0 (1,1).vertline. > T.sub.o ? yes :1 Is the bit in level 0 ? yes For the bit
B.sub.P2.sup.L0 (2,3) of the coefficient C.sup.L0 (2,3) Is the bit significant ? no :0 Is the .vertline.C.sup.L0 (2,3).vertline. > T.sub.o ? yes :1 Is the bit in level 0 ? yes For the bit B.sub.P2.sup.L0 (2,4) of the coefficient C.sup.L0 (2,4) Is
the bit significant ? yes :1 Is the sign bit recorded? yes Is the .vertline.C.sup.L0 (2,4).vertline. > T.sub.o ? no :0 Is the bit in level 0 ? yes For the bit B.sub.P2.sup.L0 (3,1) of the coefficient C.sup.L0 (3,1) Is the bit significant ? no :0
Is the .vertline.C.sup.L0 (3,1).vertline. > T.sub.o ? no :0 Is the bit in level 0 ? yes For the bit B.sub.P2.sup.L0 (3,2) of the coefficient C.sup.L0 (3,2) Is the bit significant ? yes :1 Is the sign bit recorded? no Is the symbol +ve ? yes :1
Is the .vertline.C.sup.L0 (3,2).vertline. > T.sub.o ? no :0 Is the bit in level 0 ? yes For the bit B.sub.P2.sup.L0 (4,1) of the coefficient C.sup.L0 (4,1) Is the bit significant ? no :0 Is the .vertline.C.sup.L0 (4,1).vertline. > T.sub.o ? no
:0 Is the bit in level 0 ? yes For the bit B.sub.P2.sup.L0 (4,2) of the coefficient C.sup.L0 (4,2) Is the bit significant ? no :0 Is the .vertline.C.sup.L0 (4,2).vertline. > T.sub.o ? no :0 Is the bit in level 0 ? yes

Subband #2 For the bit B.sub.P3.sup.L0 (1,1) of the coefficient C.sup.L0 (1,1) Is the bit significant ? yes :1 Is the sign bit recorded? no Is the symbol +ve ? yes :1 Is the .vertline.C.sup.L0 (1,1).vertline. > T.sub.o ? no :0 Is the
bit in level 0 ? yes For the bit B.sub.P3.sup.L0 (2,3) of the coefficient C.sup.L0 (2,3) Is the bit significant ? yes :1 Is the sign bit recorded? no Is the symbol +ve ? yes :1 Is the .vertline.C.sup.L0 (2,3).vertline. > T.sub.o ? no :0 Is the
bit in level 0 ? yes

The following 6 bits are generated for subband #2: 1, 1, 0; 1, 1, 0. The marked-matrix is illustrated in FIG. 11. In this example, for the final plane of coding, the proposed scheme is so efficient that the left over bits need not be coded,
because the bits remaining to be coded are the most significant bits in that plane, so whether the coefficient is positive or negative may, instead, be recorded. In the above example, if this latter approach is employed, the number of symbols needed to
code in the last stage is 2 bits, rather than 6 bits.

The total number of bits to code the above matrix, then, is 68 bits in this example Although the claimed subject matter is not limited in scope in this respect, this stream of symbols may subsequently be encoded. Any encoding scheme may be
employed, such as entropy-coding schemes, like huffman coding, arithmetic coding (AC), etc. This stream may be preceded by a header block, which may contains the number of planes coded, such as 3 in this case, along with the information of the transform,
e.g., dimensions of the image, the number of levels of transform applied, etc. Again, this is just one example of a possible implementation and the claimed subject matter is not limited in scope to this example. An embodiment of a process to decode a
bit or symbol stream is described as follows, although, again, the claimed subject matter is not limited in scope to this example. This is just one possible embodiment provided for purposes of illustration.

Such as embodiment of a method of embedded zero tree decoding discrete wavelet transform (DWT) coefficients that have been encoded may include applying a bit-based conditional decoding to the encoded DWT coefficients. For example, this may
include decoding by using one or more binary-valued variables, the value depending on whether one or more conditions was true or false when applied during encoding to the coefficient being decoded. At least one of the one or more conditions may relate
to the magnitude relative to a threshold, during encoding, of the coefficient being decoded. Furthermore, as previously described in connection with encoding, although the subject matter is not limited in scope in this respect, applying a bit-based
conditional decoding to encoded DWT coefficients having relatively low energy may produce good results.

In this embodiment, a decoder receiving the bit stream generated by an encoder that applies the approach described above reconstructs the coefficient matrix. This particular approach to decoding is illustrated by the state diagram shown in FIG.
12.

The initial state is S.sub.0. The decoder starts decoding the n.sup.th bit of a coefficient, following the coding order of coefficients, as previously described, for this particular embodiment. In this embodiment, decoding starts from the least
significant bit (LSB) plane and proceeds towards the most significant bit (MSB) plane, although alternative approaches, such as MSB to LSB may be employed in different embodiments.

Following bits in the input bit stream, the process moves from one state to another. The symbols marked with an asterisk (*) in FIG. 12 are generated by the decoder depending upon the partial decoding result at that point in the process.
Operation of the decoder is further explained by decoding the bit stream generated above. Again, this example is not limited and is provided simply for illustration purposes.

From the header, the following information may be decoded in this particular embodiment, although, again, the claimed subject matter is not limited in scope in this respect:

maximum number of passes; dimension of the matrix; number of levels of transform.

The decoding scheme is illustrated below applying the previous example. As noted previously, for this particular embodiment, for the nth pass, the nth bits of the coefficients are being decoded.

The claimed subject matter, such as the embodiments previously described, provide several potential advantages. For example, such an approach may be computationally faster and may code wavelet coefficients while employing fewer bits. For
example, bits that are not significant may not be coded in some embodiments. Likewise, for Shapiro's embedded zero-tree wavelet coding approach, the ZTR (zero tree root) is checked only if the bit is not significant. Therefore, in at least some
embodiments of the claimed subject matter, more ZTR may be exploited in the subband decomposition by checking more coefficients. Furthermore, passing over the smaller or not significant coefficients is not done in every pass. For example, in some
embodiments, these coefficients are encoded in the course of initial passes. Likewise, the two passes of the classical scheme has been reduced to a single pass, such as for the embodiments previously described. Furthermore, it is desirable to stop
coding when the significance of the coefficient is lost. Such an approach was illustrated in the previously described embodiment. In addition, parallel execution of coding operations may be employed in some embodiments due at least in part to applying
a coding bit plane wise approach, such as was illustrated previously, although, again, the subject matter is not limited to this embodiment or to this aspect of this embodiment.

It will, of course, be understood that, although particular embodiments have just been described, the claimed subject matter is not limited in scope to a particular embodiment or implementation. For example, one embodiment may be in hardware,
whereas another embodiment may be in software. Likewise, an embodiment may be in firmware, or any combination of hardware, software, or firmware, for example. Likewise, although the claimed subject matter is not limited in scope in this respect, one
embodiment may comprise an article, such as a storage medium. Such a storage medium, such as, for example, a CD-ROM, or a disk, may have stored thereon instructions, which when executed by a system, such as a computer system or platform, or an imaging
or video system, for example, may result in an embodiment of a method in accordance with the claimed subject matter being executed, such as an embodiment of a method of coding or decoding wavelet transformed coefficients, for example, as previously
described. For example, an image processing platform or an image processing system may include an image or video processing unit, an image or video input/output device and/or memory.

While certain features of the claimed subject matter have been illustrated and described herein, many modifications, substitutions, changes and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the
appended claims are intended to cover all such modifications and changes as fall within the true spirit of the claimed subject matter.