As a synthesizable core the 460S provides the flexibility of fabrication in multiple foundries. The 460S core allows the SoC designer to select the size cache and Processor Local Bus (PLB) version necessary to optimize single processor and cache coherent multi-processor SoC designs. The 460S design flexibility and scalability will meet the performance and power demands of today’s communications, consumer electronics and storage embedded applications.

The 460S contains a dual-issue, superscalar, pipelined processing unit. The core includes memory management, cache control, timers and debug facilities. Interfaces for custom co-processors and floating point functions are provided, along with separate instruction and data cache array interfaces which can be configured to various sizes.