Continuous improvement methodology; new materials; and innovations in device, process, and equipment designs have stretched the limits of silicon-based devices into the 2010s. New device technologies springing from these breakthroughs bring along more stringent requirements for contamination levels and thermal budgets. The new surface preparation criteria challenge state-of-the-art wet cleaning technologies developed at world-renowned institutions like IMEC and Tohoku University (Dr Ohmi’s facility). Similar to the era when their ingenious cleans replaced the long-running RCA cleans in the 1990s, significant changes may be required again to meet these tougher specifications in the silicon wafer and device manufacturing arena.

New challenges for silicon device wafer wet cleaning

For over 20 years, the leading-edge wet cleaning experts at the Ohmi and IMEC technology centers have continued to pave the way for achieving the surface preparation specifications required to keep pace with advancing silicon-based device technologies. Current device technologies demand surface contamination tolerances in the parts per trillion (ppt) regime, lower thermal budgets for processes like silicon epitaxy require bake temperatures to be < 800°C, and for silicon consumption per clean to be <0.1nm.

The best manufacturing cleaning sequences may fail under these heightened constraints. The cleaning efficiency of their dilute chemistries, even combined with the use of tera-bit chemicals, may not be able to meet the ppt contamination requirements. A pristine and stable H-terminated silicon surface termination is required to enable the low thermal budget requirements for many thermal processes. Peroxide and ozone-based chemistries inherently consume more than the 0.1nm of silicon per clean as defined in the ITRS roadmap.

Cleaning efficiency

Most of the current wet cleaning processes used in manufacturing environments still terminate the silicon with a native/chemical oxide layer. This native or chemical oxide harbors a dominant portion of post-clean contamination. Efforts have been mad to purify traditional wet cleaning chemicals such as ammonium hydroxide, hydrochloric acid, sulfuric acid, hydrofluoric acid and hydrogen peroxide. Tera-bit grade chemicals are now readily available. Chelating agents and additives, like EDTA and TMAH, as well as surfactants, are commonly used to reduce contamination in wet cleaning chemistries. H2O2, HCl, and alcohols are also commonly added in dHF mixtures to suppress contamination. While these can be somewhat effective, the main ingredient in these mixtures, ultra-pure water (UPW), still contains dissolved impurities that impregnate the chemical oxides or terminate on the silicon surfaces following cleaning sequences. These contaminants negatively affect oxide (ozone or peroxide-based mixtures) and non-oxide (dilute HF) terminating wet cleaning sequences.

Oxide and hydride silicon surface termination

Oxide-terminating cleans suffice for processes that don’t restrict a subsequent high-temperature process and are tolerant to silicon loss, but this tolerance is becoming very limited. Even in processes where it is still acceptable, dissolved impurities like oxygen (DO), carbon dioxide, total organic carbon (TOC), and silica in standard UPW can have a detrimental effect on the oxide integrity and other electrical properties. Interstitial carbon can also be diffused into the silicon when thermally processed. Dissolved organics in UPW must be dramatically reduced to improve the purity of these chemically grown oxides.

Hydrogen-terminating cleans, which are now in higher demand, are far more challenging due to the difficulty in creating a pristine and stable H-terminated silicon surface. Three primary hydride structures formed on the silicon surface (mono- , di- , tri-) all have different binding energies and are mostly controlled by the silicon’s crystalline orientation. SiHx terminations suit many processes due to their ability to be dissociated at low temperatures (500° to 550°C), accomodating thermal budgeting. A HF last process is currently the only viable method to achieving this with wet cleaning. The Ohmi and IMEC institutions each defined what they believe to be the best wet cleaning sequences [1] to achieve all of the silicon surface criteria, both of which are short sequence (2-4 steps) using ultra-dilute chemistries and terminating with a dHF-based mixture. Both of these well-developed and characterized process sequences work well in a controlled laboratory environment, but there are severe challenges when trying to implement these into a manufacturing mode. Achieving 100% SiHx terminations using a dHF wet cleaning process is virtually impossible. Minimizing the queue time between the wet clean and the subsequent process is critical due to the inherent reoxidation of the silicon surface when exposed to air. Exposure of the SiHx surface to air also permits organic contaminants to adhere.

Similar to oxide-terminating cleans; the dissolved impurities in UPW have a dramatic influence on the dHF process’ ability to provide a pristine, stable H-terminated silicon surface.

Silicon consumption

Meeting the ITRS surface preparation requirement of consuming less than 1A of silicon per clean poses the most difficult challenge for wet-clean gurus. A single monolayer of oxide growth triples this criterion. To remove metals, organics, and particles without using either H2O2 or O3 based chemistries defies the current wet cleaning protocols. Even the best IMEC and Ohmi cleans require these oxidizers. Aside from something completely new in wet cleaning chemistries, the only practical panacea seems to be to assure near 100% photoresist removal in the plasma ashing process and depend on a very pure and effective dHF mixture (with non-oxidizing additives) to remove all contaminants.

Silicon wafer drying methods: additional challenges

Along with the wet-clean and rinse challenges, there is evidence that silicon wafer drying methods that use IPA are creating unacceptable organic contamination levels. Detailed studies qualitatively and quantitatively assess this [2]. Residues following Marangoni and IPA vapor drying have shown to severely affect electrical performance for gate oxides <5nm [3]. Residues can blanket the wafer surface after H-terminated cleaning, bearing a negative impact on critical front-end processes like low-temperature Si and SiGe-based epitaxy, poly-Si stacks, and metal deposition.

With lower surface contamination tolerance, IPA-assisted drying’s benefits are outweighed by the contamination post-drying residues cause. Other non-chemical drying methods need to be enhanced or developed.

Figure 1 is from reference 4 and represents native oxide growth as a function of time in room temperature air and ultrapure water with different dissolved oxygen levels.

Achieving those demanding surface preparation goals

With the key issues with newer surface preparation criteria identified, we can discuss simple enhancements to existing leading-edge wet cleaning technologies can will overcome them. The core process engineering work and recipes that the Ohmi and IMEC camps have developed offer a great basis, but are not a complete set of instructions for use in a device manufacturing facility.

Thorough investigations have been undertaken on native oxide growth on silicon wafers [4,5] immersed in DI water with various dissolved oxygen levels and air (Figure 1); and on the benefits of functional H2 water on particle removal efficiency and hydrogen-terminating surfaces [6]. Degassing and regassing UPW can help meet new contamination criteria. Integrating this with a dHF cleaning process has a dramatic effect on its capabilities. HF last wet cleaning processes, single and two step, have been patented [7, 8], which provide a pristine and stable H-terminated silicon surface with an extensive queue time accommodated in various wet processing equipment. Some of the key components to making this novel technology work are:

XPS studies show that this process [7] can produce non-detectable oxide (<0.1A) for up to 3 days. Encapsulated SIMS is another extremely sensitive method to quantify the lack of C and O on the surface after the dHF process. The lack of oxygen and carbon for these two characterization methods indirectly indicates the degree of SiHx on the surface after the wet cleaning processes (Figure 2). Depending on the DO of the UPW, this process can yield aerial oxide densities <3E12 at/cm2 (Figure 3). This capability has allowed for sub-800°C thermal budgeting for low-temperature Si and SiGe epi processes (Figure 4). This process has also proven to allow for a queue time in excess of 8 hours without the use of special handling between the clean and the epi process.

There is evidence that dHF is very effective at removing organic residues — like BHT and DBP — that outgas from plastic wafer shipping/storage boxes [12]. It also is especially good at removing oxidized polymers following plasma etch processes. In many, if not most cases, it is now possible that a single step dHF wet process can minimize silicon loss and lower COO and environmental issues.

To address the organic residue issue with IPA for wafer drying, enhancing less-effective methods like conventional spin rinse drying (SRD) could be an acceptable option to replace the existing process of record IPA drying technologies. Methods are under investigation. Two enhancements to a SRD tool that could allow SRD to resurface as effective drying tools include complementing the drying step with vacuum to reduce water micro-droplets and using low DO (degassed) UPW for the rinse to eliminate water marks [13]. The reduction of micro-droplets and watermarks could enable an equivalent drying capability to IPA-based dryers without the drawbacks of organic residues.

A brief, low-temperature treatment could be used to remove IPA residues and airborne organic contaminants that accumulate on the wafer surface between wet cleaning and the subsequent FEOL or BEOL process. It has been demonstrated that a 300° to 400°C bake via IR lamp heating for less than 2 minutes in an oxidizing environment effectively removes both organic contamination types [14]. A method has been developed that combines vacuum and IR lamp heating to ensure the most effective decomposition and desorption of the organic species and moisture.

Conclusion

Although complex issues arise with tightening surface preparation specifications for emerging device technologies, solutions can be simple in nature. A single step dHF clean could accomplish overcoming the three identified hurdles associated with the new surface preparation criteria. Degassing the DO and the other dissolved species in UPW and chemicals has shown to be a valuable technique for dramatically reducing contamination levels in the cleaning, rinsing and drying steps of a wet cleaning process. SRDs could be enhanced for effective wafer drying, replacing IPA-based methods. Unavoidable airborne organic contamination and IPA drying residues can be nearly eliminated with a fast, reduced-pressure, low-temperature treatment. These simple approaches to achieve the challenging surface preparation criteria can be found on commercially available equipment.

FEATURED PRODUCTS

TECHNOLOGY PAPERS

As IP and IC designers and verification teams tackle increased complexity and expectations, reliability verification has become a necessary ingredient for success. Automotive, always-on mobile devices, IOT and other platforms require increasingly lower power envelopes and reduced device leakage while maintaining overall device performance. Foundries have also created new process nodes targeted for these applications. Having the ability to establish baseline checks for design and reliability requirements is critical to first pass success. January 08, 2018Sponsored by Mentor Graphics

The power amplifier (PA) – as either a discrete component or part of an integrated front end module (FEM) – is one of the most integral RF integrated circuits (RFICs) in the modern radio. In Part 2 of this white paper series, you will learn different techniques for testing PAs via an interactive white paper with multiple how-to videos.September 06, 2017Sponsored by National Instruments

WEBCASTS

Since 2006, many of new 3D NAND Flash cells have been proposed and commercialized on the market. Already, we have seen 3D NAND cell structure up to 64L/72L with single or multi-stack NAND string architecture. The memory density on Micron/Intel’s 64L 3D NAND 256 Gb/die reached 4.40 Gb/mm2 (256 Gb/die). In this session, we’ll overview 3D NAND Flash roadmap, products, cell design, structure, materials and process integration. The 3D NAND cell architecture from major NAND manufacturers including Samsung TCAT V-NAND, Toshiba/Western Digital BiCS, SK Hynix P-BiCS and Micron/Intel FG CuA will be reviewed and compared. Current and future technology challenges on 3D NAND will be discussed as well.

MEMS have quite different process and material requirements compared to mainstream microprocessor and memory types of devices. We will explore the latest trends in MEMS devices – including sensor fusion, biosensors, energy harvesting – new manufacturing challenges and potential equipment and materials solutions to those challenges.