Monday, June 16, 2014

Welcome to the twenty-fourth issue of LLVM Weekly, a weekly newsletter
(published every Monday) covering developments in LLVM, Clang, and related
projects.
LLVM Weekly is brought to you by Alex Bradbury.
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LLVM commits

A weak variant of cmpxchg has been added to the LLVM IR, as has been argued
for on the
mailing list. Weak cmpxchg allows failure and the operation returns {iN, i1}
(in fact, for uniformity all cmpxchg instructions do this now). According to
the commit message, this change will mean legacy assembly IR files will be
invalid but legacy bitcode files will be upgraded during read.
r210903.

X86 FastISel gained support for handling a bunch more intrinsics.
r210709,
r210720 and more. FastISel also saw some
target-independent improvements r210742.

This week there were many updates to the MIPS backend for mips32r6/mips64r6.
e.g. r210899,
r210784 and many more.

NoSignedWrap, NoUnsignedWrap and Exact flags are now exposed to the
SelectionDAG. r210467.

Support has been added for variable length arrays on the Windows on ARM
Itanium ABI. r201489.

Some simple reordering of fields in Value and User saves 8 bytes of padding
on 64-bit. r210501.

FastISel will now collect statistics on when it fails with intrinsics.
r210556.

The MIPS backend gained support for jr.hb and jalr.hb (jump register with
hazard barrier, jump and link register with hazard barrier).
r210654.