1.1 About the Advanced SIMD and floating-point support

The Cortex®‑A35 processor supports the Advanced SIMD and scalar floating-point instructions in the A64 instruction set and the Advanced SIMD and floating-point instructions in the A32 and T32 instruction sets.

The Cortex‑A35 floating-point implementation:

Does not support floating-point exception trapping.

Implements all scalar operations in hardware with support for all combinations
of:

Rounding
modes.

Flush-to-zero.

Default Not a Number (NaN) modes.

The ARMv8 architecture eliminates the concept of version numbers for its
Advanced SIMD and floating-point support in the AArch64 execution state.