Those who funded will know by now that they met their 750K goal, so I'm looking forward to receiving my dev boards. It's a fascinating project, and it was partly the idea of these guys designing cutting-edge silicon in their basement that encouraged me to put in a few $. As someone said back there, it takes you back to the good old days!

Big processing power at 5watts power consumption. Initially there will be lot of requirement for the applications in the mobile plate form. Later on desk top systems also.Probably after its launch this will be tuned up further with feed back from the users.

Thanks for the explanation, I will try to understand it as a layman of Computer engineeing: are you saying that some commercial simulation tools still can't run on this supercomputer? Such as Ansys, Silvaco...these are popular simulation tools for semicopnductor.Is it possible to make them run in the near future?

This is very interesting. I have an assortment of platforms: Arduino Uno, Raspberry Pi, Altium NanoBoard and have just ordered an Arduino Due.
To me this is just as exciting as the January '75 Popular Electronics article introducing the Altair 8800. I ordered one right away and nothings been the same since.
My interests have included machine vision and the platforms I have now, except maybe the NanoBoard, are totally inadequate.
As soon as I figure out how I will cough up the $99 donation.

Thank you. Yes, we got lucky with our choice of the Zynq, it has generated an incredible amount of really positive interest.(not even related to the goal of this project:-)) I guess that's what they call "fortuitous serendipity".

With the right software, we numerical simulations could be a great fit. The challenge right now is that the software infrastructure for parallel programming still needs a lot of work. That's one of the driving reasons for starting this project. Ironically, the challenge of boot strapping ubiquitous parallel programming is a serial process.

This is very interesting.
I myself have just finished developing a 64-processor chip targeted at Ethernet packet inspection and filtering.
The processor cores are optimised hardware implementations of the "Berkeley Packet Filter" processor.
Ref:
http://en.wikipedia.org/wiki/Berkeley_Packet_Filter
http://www.tcpdump.org/papers/bpf-usenix93.pdf
The 64-processor cores are implemented on a Xilinx Virtex-6 FPGA and makes good use of its DSP48E1 primitives and on-chip block-rams to achieve single-cycle operation for most instruction op-codes.
This allows 4x10Gbps of Ethernet packets to be inspected, analysed and filtered at full-line rate on the chip.
This means you can now replace a full rack of servers with a single PCIe card.
Here is the finished product:
http://www.telesoft-technologies.com/images/docs/DX-OEM-GEN-MK-DS-33862-02-MPAC-IP-6010-4x10GbE.pdf
This product has applications in:
Cyber security
Network intrusion detection (IDS)
Lawful intercept
Virus Signature Detection
etc.