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Method for an integrated solution to reliability and coplanarity issues on BGA packages with small pitch, large package, large die, and high-speed chips

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for an integrated solution to reliability and coplanarity issues on ball-grid array (BGA) packages with small pitch, large package, large die, and high-speed chips. Benefits include improved prevention of defects, improved functionality, and improved design flexibility.

Country

United States

Language

English (United States)

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Method for an integrated solution to reliability and
coplanarity issues on BGA packages with small pitch, large package, large die,
and high-speed chips

Disclosed is a method
for an integrated solution to reliability and coplanarity issues on ball-grid array
(BGA) packages with small pitch, large package, large die, and high-speed
chips. Benefits include improved prevention of defects, improved functionality,
and improved design flexibility.

Conventionally, the brittle fracture
is handled as a substrate plating-related issue. Multiple changes in the
substrate have solved the issue for FCBGA1 packages, but the root cause remains
unknown, which means the issue will recur. Another solution is to eliminate
board deflection. For example, the wave solder heatsink (WSHS, see Figure 1) is
faced with the issues of cracking at the through-hole joint and WSHS tilt.
These conditions lead to a weaker joints and uneven thermal interface material
(TIM) on the die and impact heat dissipation.

Note: Heatsink force on a package is formed during wave solder and is not
controllable. If force on the package is required for thermal and mechanical
reasons, a design with a spring or a spring plate on the topside of the PCB,
such as z-clip assembly, must be used.

Fatigue failure due to coefficient for
thermal expansion (CTE) mismatch between the die and substrate is solved by
removing stress concentration on the joint level through an optimized package
solder resist opening and board-pad size (see Figure 2). However, this method
narrows the process margin. Another solution is to create a keep-out zone (KOZ)
(see Figure 3), removing solder balls, or putting sacrificial balls in a
high-fatigue stress region. However, this approach reduces the I/O count.

Package coplanarity is conventionally
solved by using an integrated heat spreader (IHS, Figure 4). IHSs were
originally designed for thermal performance but aid in controlling package coplanarity
with its rigidity. However, this method creates another issue in the board
assembly. A peak-temperature delta as high as 15°C can occur between the
package center and the package corner i...