[SI-LIST] Re: Trace Width @ 3Gb/s

You are definately going to have loss associated
with skin effect, but I suspect that what you are
going to find is that dielectric loss is your
principal loss contributor at the rates that you
are talking about. The fine folks at Nesa.com have
a paper on this very subject that shows that above
the break frequency where skin effect loss and
dielectric loss are equal, dielectric will become the
predominant contributor. You should also be able to
model this in your sims to prove to yourself that
this is indeed the case.
Just my 0.02
Best Regards,
Michael C. Greim
Michael_Greim@xxxxxxxx
(512) 728-3933, Voice
And all this science I don't understand
It's just my job six days a week........
The time is gone, the email's over
thought I'd something more to say.....
-----Original Message-----
From: Mustansir Fanaswalla [mailto:mustansi@xxxxxxxx]
Sent: Monday, June 10, 2002 11:19 AM
To: hassan@xxxxxxxx; Rudy Sterner; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Trace Width @ 3Gb/s
Hi,
There is significant attenuation of the signal, consequently leading to bit
errors.
Your comments indicate that the narrow traces very well could be the cause.
Thanks
Mustansir
-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-
Mustansir Fanaswalla
LSI Logic Corporation
-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-x-
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Hassan O. Ali
Sent: Monday, June 10, 2002 9:01 AM
To: Rudy Sterner; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Trace Width @ 3Gb/s
Rudy,
Could you be specific on the kind of issues you have with the SerDes link?
That way you
can receive suggestions that are more specific to your situation.
Yes, 4-mil tracks can be a problem. With those tracks, in a microstrip
format you need
less than 3-mil height to achieve close to 50-ohm single-ended line
impedance (which
might be your goal). With that small height and at that data rate, component
pads
(especially AC-coupling cap pads, if you have any) start to dominate heavily
causing
tremendous impedance discontinuities.
In addition, narrow tracks give rise to higher loss - both line-loss and
reflection loss
due to pronounced discontinuities at various locations (the connector
launch-point is
one of the most important ones).
Regards.
Hassan.
On Jun 10, "Rudy Sterner" <rsterner@xxxxxxxx> wrote:
>
> Hello,
>
> We have some issues with a SerDes which we think
> may be related to the trace width on the serial line. The
> serial port is a differential pair passing data at 3 Gb/s.
> The trace width is 4 mils. Length is approximately 5 inches.
> The differential impedance is 100 Ohms. Other information
> which may be of use is the board material is FR-4 with an
> Er of 3.9. It is specified at this data rate.
>
> My question is: Are the traces too narrow? Should I
> expect better performance with 8-mil traces?
>
> Thank You
>
> Rudy Sterner
> LSI Logic
>
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