1. All the peripherals are accessible to both CM4 and CM0+, as both share the same MMIO and Memory address space. That said, you cannot access any of these peripherals in DeepSleep and Hibernate modes from the CPU, as your CPU will be powered-off in these modes These peripherals can generate interrupt and wakeup the CPU (either M4 or M0+ or both) in DeepSleep and the system in hibernate (as wakeup from hibernate mode is a system reset event not CPU wakeup).

2. No. Both the cores can see the entire register space. That said both CM0+ and CM4 have their own ARM defined system space registers (includes interrupt priority, enable/disable etc. registers). These registers are visible only to the core that access it.