Chip design solutions, Magma (Magma?) Design Automation Inc. (Nasdaq: LAVA) today introduced a next-generation integrated circuit (IC) implementation solution - Talus? 1.2, it can significantly reduce the chip System (SoC) design cycles. This new combination of Talus system allows engineers to avoid the use of cross-talk, high-chip variation (AOCV) and multi-mode multi-corner (MMMC) analysis in a large design or with 200-500 units of circuit blocks to achieve 100-150 million per day unit design. Talus has passed the authentication chip 40 nanometer node, the current applied to the complex 28-nanometer design. With these latest enhancements, Talus for 20 and 20 nanometer processing technology node design has a completely prepared.
Talus 1.2 more quickly and accurately through the use of the route, timing and extraction technology and advanced features to provide 5-6 times faster design cycle, including:
? Talus MX router (Talus MX Router): to provide enhanced global, track and detailed routing capabilities, and integration throughout the entire process of timing, in addition to the DRC violations.
? Talus MX timing device (Talus MX Timer): Magma-based next-generation timing analysis sign-technology, more fast and accurate timing analysis.
? Talus MX extractor (Talus MX Extractor): Magma Based on the latest high-speed, multi-corner extraction technology to provide faster and accurate extraction.
? Concurrent multi-corner multi-mode optimization (Concurrent MMMC optimization): management solutions for more than 5 times the traditional timing scenarios, providing 10 times the run time improvement.
? Advanced on-chip variation (AOCV): throughout the entire process to ensure that the close temporal association.
? Crosstalk avoidance (Crosstalk Avoidance) - In the optimization, and implementation and correct crosstalk avoidance during the test.
"We Magma Talus 1.2 platform has achieved fruitful results, which once again proved this tool we have chosen to support our project requirements of complex chips correctness of this decision," Exar Corporation executive vice president of engineering operations and chief technology officer George Apostol said. "For our customers, is vital to our device must support the premise of non-bottleneck a high level of data traffic, which requires a valid routing. Talus 1.2 has addressed many of the physical design and layout of the wiring running time than the previous version has been greatly improved, which enables us to shorten the development cycle and accelerate the next generation of devices to provide customers with shipping time to meet dynamic market needs. "
"As the design of set size and complexity are increased, the chip design team faced the pressure to improve productivity is increasing," Magma's Design Implementation Business Unit Premal Buch, general manager, said. "It is economics that the design team can design size growth ratio by expanding the scale of the design cycle can not increase in size according to the proportion of design extension of time. In order to improve productivity, tools must provide greater capacity and shorter design cycles, At the same time also allows designers to improve performance in the SoC design and lower power consumption. Talus 1.2 is such a tool, it can be for the next generation of 28 and 28 nanometer process node design provides the shortest IC design cycle, the highest capacity and The best quality of results. "
Talus 1.2: More shrinking design cycles, superior design results
Talus 1.2 The key technologies include a new Talus MX timing and extraction engines. The analysis engine to Magma's next-generation timing sign-off device - Tekton? And sign extractor - QCP? The underlying technology, both quickly and accurately and with significantly increased capacity, can be applied throughout the entire Talus 1.2 The RTL-to-GDSII flow; them by providing AOCV, MMMC analysis, new features throughout the entire process to ensure that when a close temporal association. When used in conjunction with the Tekton and QCP when, Talus 1.2 design implementation can be provided during the sign-level analysis of the accuracy, remove the timing ECO, to achieve faster design closure.
For the 28 and 28 nanometer design implementation, the design requires a variety of different timing scenarios are common. Magma that the timing process corner scenario is equal to the number of x number of timing patterns. Most solutions are designed to achieve only 5-8 during the processing power of timing scenarios. Talus 1.2 on a single device can perform concurrent MM / MC, able to manage more than 5 times the traditional solutions scene, and also provides 10 times the run time improvement.
Talus 1.2 new routing technology can handle a variety of 28 and 28 nanometer routing problems, especially in this type of technology node crosstalk management more difficult. If the process is over, the best case (best case), at a higher unit area and higher crosstalk when leakage repair, then the time is too late; if the worst-case (worst case) when, it may be convergence led to the design can not be completed. Talus1.2 can be identified throughout the implementation process and control crosstalk, timing is much less and provide more integration of unforeseen circumstances the process, which can prevent this from happening. Unlike other programs, Talus1.2 can not increase the size and leakage under the premise of providing a much shorter running time and more robust design.
Talus 1.2 the integration of new technology allows designers to quickly provide high-performance design. For example: an Internet company that in just two days, the combined application of a comprehensive transportation CCS, MMMC, and crosstalk analysis capabilities to achieve a 2 million unit level circuit, the 10 signed 40-nanometer design of nuclear scenarios.
For more information, please visit the Magma website to download the White Paper "to Talus Vortex and Talus Vortex FX settlement 32/38 nm IC implementation issues": www.magma-da.com/resources (must be registered.)