The TSMC 28 nm HPM (high performance for mobile applications) process technology that achieved these results addresses applications requiring both high speed and low leakage power. Using various design signoff conditions, ARM A9 at TSMC 28HPM delivers performance speed range from 1.5 GHz to 2.0 GHz, suitable for mobile computing, and up to 3.1 GHz for high-performance uses. With its wide performance-to-leakage coverage, the 28 nm HPM process was developed for devices targeting networking, tablet and mobile consumer product applications.

The ARM Cortex-A9 silicon implementation and validation is part of TSMC's ongoing technology benchmarking effort to demonstrate performance, power and area (PPA) capabilities at the system-on-chip (SoC) level for each process technology node.

"At 3.1 GHz this 28HPM dual-core processor implementation is twice as fast as its counterpart at TSMC 40 nm under the same operating conditions," said Cliff Hou, TSMC Vice President, Research & Development. "This work demonstrates how ARM and TSMC can satisfy high performance market demands. With other implementation options, 28HPM is also highly suited for a wide range of markets that prize performance and power efficiency."

"TSMC's high performance 28HPM process is suitable for a wide range of advanced ARM-processor based applications, extending from high-frequency, performance-orientated computing devices to power sensitive applications," said Jim Nicholas, Vice President of Marketing, Processor Division, ARM. "The collaboration between ARM, TSMC and our ecosystem partners has delivered an extensible implementation platform that enables flexibility in performance and power management tradeoffs for next generation products."

The Cortex-A9 processor is available for license from ARM and is aimed at mobile, high-performance consumer, and enterprise SoC requiring high performance and low power.

The test chip results demonstrate that the combination of the most advanced process technology, best-practices circuit design techniques, and proven chip implementation methodology lead to the highest PPA landmark in an SoC. The results confirm the benefits of TSMC's Open Innovation Platform (OIP) design ecosystem that promotes innovation for the semiconductor design community, ecosystem partners and TSMC's complete technology portfolio.

Overstating. The fact is it cannot be tested until maybe Tegra 3+. A 1.5 Ghz/2 Ghz 28nm dual A15 beating a 40nm 1.3 Ghz quad A9 on same TDP does not equal what is being stated above. Apples to oranges, you can't compare two architectures until you compare them at the same process. You can't on desktop CPU/GPU and much less on a mobile CPU, where perf/watt is of maximum importance and improvements from new processes are generally huge. That's what OP is all about, on 40 nm we see 1.3 Ghz (1.2-1.5 Ghz) A9's, on 28 nm we might see 2 Ghz A9's with same TDP as 1.5 Ghz A15's and in that form the natural architecture advantage of the A15 would be mitigated.

A15 is better, much better, but it's not twice as fast on equal terms.

Yeah and I was just pointing out that such claim is not something we can know for sure.

What I was talking about is that A9's might clock much better, and no a 3 Ghz A9 would not loose against a 1.5 Ghz A15 if what I've seen is anything to go by. Like I said A15 is much better but not twice as fast (per-clock-per-watt). There's instances where it is 2x as fast, there's others where a 3 Ghz A9 would crush a 1.5 Ghz A15, by it's pure clock advantage and there's probably a multitude of use scenarios where high clocked A9's would be better.

We don't know the exact size comparison between a A9 core and A15 core, and we don't know their relative perf/watt on the same process.

So we don't know maximum clocks when on same process, we don't know perf/watt on same process and we don't know relative size in same process, so how do we know how they compare in reality?