Gems of Verilog Programming

The conventional high level language (like Java, C, C#) programmers, diving into RTL programming needs to keep in mind, that though the programs are apparently written sequentially, when synthesized into silicon (or FPGA), they execute in parallel. So, to save power and speed up your designs get as much done in a clock cycle as possible. For example, use non-blocking assignment '<=' rather than blocking assignment '=', unless you actually intend to synthesize a sequential assignment logic.

So, to transition from high level application programming to RTL designing, we need to reprogram our minds, from the sequential thought process to parallel process thinking.

Delay Operator

In many places of the OpenSPARC source the delay operator is used. Which has a syntax of :

#(rise)

#(rise,fall)

#(rise, fall, off) // off equals high impedance state Z, of the tri-state logic.