With advances in the semiconductor industry and technology scaling, integrated circuits are becoming smaller and require a high speed of operation.
Higher speed implies faster data and clock rates in the order of GHz. These
demands cannot be met with parallel communication due to issues such as
crosstalk and data skew to name a few. Serial communication facilitates high
speed of operation with use of fewer pins and less interference between links.
With increasingly higher data rates, clock-frequencies have reached the order
of GHz making the use of phase locked loops imperative in links. Many
a times, high-speed serial data streams are sent without an accompanying
clock signal. The receiver generates a clock from an approximate frequency
reference, and then phase-aligns to the transitions in the data stream with a
phase-locked loop (PLL). This is called clock and data recovery (CDR) and
is the process used to recover the data sent at the transmitter. This thesis
will discuss the working of a Clock and Data Recovery circuit (CDR). The
fundamental blocks of the CDR will be discussed in detail giving an insight
to the working of this block in high-speed links.