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Appeared on: Monday, June 20, 2011
Intel Equipped to Lead Industry to Era of Exascale Computing

During the International Supercomputing Conference (ISC), Intel discussed its strategy to lead the industry in the era of Exascale computing, and the role that the Intel Many Integrated Core (MIC) architecture will play.

Kirk Skaugen, Intel Corporation vice president and general manager of the Data
Center Group, outlined Intel's vision to achieve ExaFLOP/s performance by the
end of this decade. An ExaFLOP/s is quintillion computer operations per second,
hundreds times more than today's fastest supercomputers.

Reaching exascale levels of performance in the future will not only require the
combined efforts of industry and governments, but also approaches being
pioneered by the Intel Many Integrated Core (Intel MIC) Architecture, according
to Skaugen.

"While Intel Xeon processors are the clear architecture of choice for the
current TOP500 list of supercomputers, Intel is further expanding its focus on
high-performance computing by enabling the industry for the next frontier with
our Many Integrated Core architecture for petascale and future exascale
workloads," said Skaugen.

Intel's pursuit of Moore's Law -- doubling the transistor density on
microprocessors roughly every 2 years to increase functionality and performance
while decreasing costs -- combined with an efficient software programming model
and extreme system scalability were noted by Skaugen as key ingredients for
crossing the threshold of petascale computing into a new era of exascale
computing. With this increase in performance, though, comes a significant
increase in power consumption.

As an example, for today's fastest supercomputer in China, the Tianhe-1A, to
achieve exascale performance, it would require more than 1.6 GW of power - an
amount large enough to supply electricity to 2 million homes ? thus presenting
an energy efficiency challenge.

To address this challenge, Intel and European researchers have established three
European labs with three main goals: to create a sustained partner presence in
Europe; take advantage of the growing relevance of European high-performance
computing (HPC) research; and exponentially grow capabilities in computational
science, engineering and strategic computing. One of the technical goals of
these labs is to create simulation applications that begin to address the energy
efficiency challenges of moving to exascale performance.

Skaugen said there is the potential for tremendous growth of the HPC market.
While supercomputers from the 1980s delivered GigaFLOP/s (billions of floating
point operations per second) performance, today's most powerful machines have
increased this value by several million times. This, in turn, has increased the
demand for processors used in supercomputing. By 2013 Intel expects the top 100
supercomputers in the world to use one million processors. By 2015 this number
is expected to double, and is forecasted to reach 8 million units by the end of
the decade. The performance of the TOP500 #1 system is estimated to reach 100
PetaFLOP/s in 2015 and break the barrier of 1 ExaFLOP/s in 2018. By the end of
the decade the fastest system on Earth is forecasted to be able to provide
performance of more than 4 ExaFLOP/s.

Intel MIC Architecture Software Development

Relative to the multi-core Intel Xeon processors, Intel MIC Architecture has
many more smaller cores, many more hardware threads, and wider vector
units. This is ideal for achieving higher aggregate performance for highly
parallel applications.

The Intel MIC architecture is a key addition to the company's existing products,
including Intel Xeon processors, and expected to help lead the industry into the
era of exascale computing. The first Intel MIC product, codenamed "Knights
Corner," is planned for production on Intel's 22-nanometer technology that
featuring 3-D Tri-Gate transistors. Intel is currently shipping Intel MIC
software development platforms, codenamed '"Knights Ferry," to select
development partners.

As developers embrace high degrees of parallelism (instruction, data, task,
vector, thread, cluster, etc.), important and popular programming models for
Intel Architecture processors extend to Intel MIC Architecture without
rethinking the entire problem. The same techniques that deliver performance on
Intel processors - scaling applications to cores and threads, blocking data for
hierarchical memory and caches, and effective use of
SIMD - also apply to maximizing performance on Intel MIC Architecture.
With greater reuse of parallel CPU code, software companies and IT departments
benefit from creating and maintaining a single code base binary and not having
to re-train developers on proprietary programming models associated with
accelerators.

At ISC, Intel and some of its partners including Forschungszentrum Juelich,
Leibniz Supercomputing Centre (LRZ), CERN and Korea Institute of Science and
Technology Information (KISTI) showed early results of their work with the
"Knights Ferry" platform. The demonstrations showed how Intel MIC architecture
delivers both performance and software programmability advantages.

"The programming model advantage of Intel MIC architecture enabled us to quickly
scale our applications running on Intel Xeon processors to the Knights Ferry
Software Development Platform," said Prof. Arndt Bode of the Leibniz
Supercomputing Centre. "This workload was originally developed and optimized for
Intel Xeon processors but due to the familiarity of the programming model we
could optimize the code for the Intel MIC architecture within hours and also
achieved over 650 GFLOPS of performance."

Intel also showed server and workstation platforms from SGI, Dell, HP, IBM,
Colfax and Supermicro, all of which are working with Intel to plan products
based on "Knights Corner."