===============================================================================
SIGDA -- The Resource for EDA Professionals http://www.sigda.org
This newsletter is a free service for current SIGDA members
and is added automatically with a new SIGDA membersip.
Circulation: 2,700
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15 December 2006 ACM/SIGDA E-NEWSLETTER Vol. 36, No. 24
Online archive: http://www.sigda.org/newsletter
===============================================================================
Contents of this E-NEWSLETTER:
(1) SIGDA News
Contributing author: Tony Givargis
Contributing author: Michael Orshansky
Contributing author: Marc Riedel
Contributing author: Igor Markov
(2) What is SMT? (Reprinted from December 1 issue)
Contributing author: Karem Sakallah
University of Michigan
Igor Markov
(3) Paper Submission Deadlines
Hai Zhou
(4) Upcoming Conferences and Symposia
Hai Zhou
(5) Call for Participation - SELSE-3 Workshop
Silicon Errors in Logic - System Effects
Cristian Constantinescu
(6) Upcoming Funding Opportunities
Qinru Qiu
===============================================================================
Dear ACM/SIGDA members,
Happy Holidays!
In this issue, we have reprinted the "What is SMT (Satisfiability Modulo
Theories)?" column. The "SIGDA News" column contains a number of fresh
headlines. We have also updated the contents of other regular columns.
As always, we welcome your comments and suggestions. If you would like to
participate or contribute to the content of the E-Newsletter, please feel free
to contact any of us.
Igor Markov and Qing Wu, E-Newsletter Editors;
Tony Givargis, E-Newsletter Associate Editor;
Michael Orshansky, E-Newsletter Associate Editor;
Marc Riedel, E-Newsletter Associate Editor;
Qinru Qiu, E-Newsletter Associate Editor;
Hai Zhou, E-Newsletter Associate Editor;
===============================================================================
SIGDA News
-----------------------
"Standards Open Up EDA Arena?"
http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=194400734
A growing movement to bring some standardization to foundry process design
kits may crack open an analog and custom IC design market long dominated by
Cadence Design Systems. But much more remains to be done, say representatives
of EDA providers and foundries.
"Chip sales to hit $400B in 2011"
http://www.eetimes.com/showArticle.jhtml?articleID=196700009
The semiconductor market will top a dizzying $400 billion in 2011, according
to a recent report by IC Insights. From now till then, the annual growth will
stay just the right side of respectable, maintaining double-digit average
increases of 10.1 percent. Along the way, IC Insights believes the $300
billion mile marker will be reached in 2008, eight years after the industry
passed $200 billion. The $100 billion marker came in 1994. Since 1990, when
sales first tipped $50 billion, and stuff like the iPod was only a gadget
geek's dream, the semiconductor industry has clocked compound annual growth of
10.4 percent.
"Revival of the Supercomputer"
http://www.eetimes.com/showArticle.jhtml?articleID=196600979
Mentor and Mercury announced last week that they will roll out the first Cell
BE processor-based acceleration platform for the EDA market. It's a different
direction for an EDA industry that thus far, except for simulation
accelerators and emulators, has relied on software that runs on
general-purpose CPUs and servers. In particular, optical proximity correction
(OPC) can best be performed by hardware acceleration based on the Cell
Broadband Engine processor, the companies claim. At the same time, DARPA is
working with IBM's X10, Cray's Chapel, and Sun's Fortress languages in order
to find an ideal language to simplify the increasingly intricate task of
developing software for supercomputers. Sources indicate that one language
could be picked outright, or a hybrid could be developed, but the decision
should be made within 18 months. University of Tennessee supercomputer
researcher Jack Dongarra says the Message Passing Interface (MPI) currently
used on supercomputers "has just too much programming complexity to get it all
right." The three languages submitted are intended to provide an enhanced view
of complex systems to allow more efficient communication between diverse
processors.
"IBM Promises New Memory Chip Technology"
http://www.playfuls.com/news_05488_IBM_Promises_New_Memory_Chip_Technology.html
Scientists from IBM, Macronix and Qimonda announced joint research results
that give a major boost to a new type of computer memory with the potential to
be the successor to flash memory chips, which are widely used in computers and
consumer electronics like digital cameras and portable music players. Working
together at IBM Research labs on both U.S. coasts, the scientists designed,
built and demonstrated a prototype phase-change memory device that switched
more than 500 times faster than flash while using less than one-half the power
to write data into a cell. The device's cross-section is a minuscule 3 by 20
nanometers in size, far smaller than flash can be built today and equivalent
to the industry's chip-making capabilities targeted for 2015.
"New Transistor Switches at 0.845 TeraHertz"
http://www.news.uiuc.edu/news/06/1211transistor.html
Scientists at the University of Illinois at Urbana-Champaign have again broken
their own speed record for the world's fastest transistor. With a frequency
of 845 gigahertz, their latest device is approximately 300 gigahertz faster
than transistors built by other research groups, and approaches the goal of a
terahertz device. Made from indium phosphide and indium gallium arsenide, "the
new transistor utilizes a pseudomorphic grading of the base and collector
regions," said Milton Feng, the Holonyak Chair Professor of Electrical and
Computer Engineering at Illinois. "The compositional grading of these
components enhances the electron velocity, hence, reduces both current density
and charging time." The new device will be described at the International
Electronics Device Meeting in San Francisco, Dec. 11-13.
"Flexible Electronics Advance Boosts Performance, Manufacturing"
http://www.sciencedaily.com/releases/2006/12/061213175213.htm
Flexible electronics made with organic, or carbon-based, transistors could
enable technologies such as low-cost sensors on product packaging and
''electronic paper'' displays as thin and floppy as a placemat. But the best
mass-producible organic transistors have been slow, and products using them
have yet to come to market. In a study published in the Dec. 14 issue of the
journal Nature, researchers at Stanford and the University of California-Los
Angeles point the way toward manufacturing truly useful flexible electronics
with high-performance organic transistors. ''This work demonstrates for the
first time that organic single crystals can be patterned over a large area
without the need to laboriously handpick and fabricate transistors one at a
time,'' says Stanford chemical engineering Associate Professor Zhenan Bao.
"AMD Rolls First 65nm CPUs, Sees Fast Shift to 45nm"
http://www.eetimes.com/showArticle.jhtml?articleID=196601437
Executing on its goal of keeping pace with archrival Intel Corp., Advanced
Micro Devices rolled out its first 65-nm x86 CPUs Dec. 5. The new Athlon 64
X2 cuts die size in half and power by a third in existing 90-nm desktop
processors.
"Shorten EDA Cycles With Storage Acceleration"
http://www.elecdesign.com/Articles/Index.cfm?AD=1&ArticleID=14251
EDA users face a number of challenging constraints when designing products and
the process can stress their underlying corporate information-technology (IT)
infrastructure. In particular, the data-storage foundation is susceptible to
limitations in a number of common scenarios.
"EDA Vendor Rivalry Bogs Single Power Spec"
http://www.eetasia.com/ART_8800444108_480100_cf1a1e78200612.HTM
IC designers want one standard way to represent power intent throughout the
design and verification flow, according to presentations at a Low Power
Workshop in California. Standards organizations say they're taking note, but
EDA vendor rivalry continues to fuel two separate efforts to develop a
low-power description standard.
"Startup Weaves 'Fabric' for IC Design"
http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=196603234
Fabbrix Inc., a startup that aims to reshape IC design through the use of
regular design patterns or "fabrics," has stepped into public view this week
(Dec. 11) by announcing a collaboration with PDF Solutions Inc. Through a
joint development project with PDF, Fabbrix hopes to further refine technology
that it claims can substantially boost yields at 65 nm and below.
"ASML to buy Brion"
http://www.eetimes.com/showArticle.jhtml?articleID=196700734
In a major expansion into the design-for-manufacturing (DFM) arena, ASML
announced plans to acquire Brion Technologies, a provider of semiconductor
design and wafer production technology. Brion is a player in the growing field
of computational lithography, which encompasses design verification, reticle
enhancement technologies and optical proximity correction. Brion's
computational lithography technology enables semiconductor manufacturers to
simulate the realized pattern of integrated circuits and to correct the mask
pattern to optimize the manufacturing process and yield, the company said.
"Verification Tools Bring ESL to Enterprise"
http://eetimes.com/news/design/showArticle.jhtml?articleID=196600328
Changing the definition of ESL from electronic system-level design to
"enterprise system-level" design, Cadence Design Systems Inc. advocates a new
approach to IC functional verification that encompasses hardware, embedded
software and system-level interactions. New offerings include an ESL option
for the Incisive Enterprise Simulator, a revamped Incisive Enterprise Manager
and the Palladium III acceleration and emulation system.
"Sony PlayStation 3 Review"
http://www.pcworld.com/article/id,127868-page,1-c,gameconsoles/article.html
Weighing about 11 pounds and measuring 12.8 inches wide by 3.86 inches high by
10.89 inches long, the PlayStation 3 is larger than the PlayStation 2, the
diminutive Nintendo Wii, or the Microsoft Xbox 360. Like those consoles, it
can be oriented vertically or horizontally. Either way, the PS3's striking
design looks right at home in the living room
"Xilinx Launches Spartan-3A FPGAs for I/O Intensive Applications"
http://www.eeproductcenter.com/showArticle.jhtml?articleID=196602002
Built on 90-nm process technology, Xilinx's Spartan-3A FPGA family is the
third platform in the Spartan-3 FPGA generation. It is suitable for bridging,
differential signaling and memory interfacing applications that require wide
or multiple interfaces and modest processing.
"Sony Blu-ray Getting Cool Reception"
http://www.eetimes.com/showArticle.jhtml?articleID=196602842
Internet discussions on Sony's Blu-ray show a general dislike for the
high-definition format that's a key component in the company's overall
strategy for grabbing a big share of the high-definition consumer electronics
market, a research firm says. A Cymfony Inc. analysis of comments on 323
blogs, discussion boards and other social media show that positive comments on
Blu-ray's rival HD DVD, backed by Toshiba and other tech companies, are 46
percent higher. In addition, 2.5 times more posts discussed being impressed
with HD DVD than with Blu-ray.
"DFM Start-up Aprio Reduces Staff"
http://www.eetimes.com/showArticle.jhtml?articleID=196602854
Acknowledging a difficult market for design for manufacturability (DFM)
startups, Aprio Technologies has laid off several members of its
administrative staff, including Mike Gianfagna, president and CEO. Gianfagna
remains an advisor to co-founder Clive Wu, who has reclaimed his old position
as Aprio CEO and CTO. "The whole DFM market is not growing as fast as we had
initially hoped, and adoption is slower than expected," said Wu. "There are
harder times ahead for startups like us. We made some adjustments to make sure
our current cash will last over difficult times."
"Material With Negative Refractive Index Created"
http://www.newscientisttech.com/article/dn10816.html
The race to build an exotic material with a negative refractive index for
visible light has been won by a team of researchers in Germany. The
demonstration could open the door to a new generation of optical devices such
as superlenses able to see details finer then the wavelength of visible light.
It may also lead to further breakthroughs in "invisibility cloaks" which could
hide objects from the human eye.
==============================================================================
What is SMT (Satisfiability Modulo Theories)?
---------------------------------------------
Karem Sakallah
University of Michigan
Before answering this question it seems appropriate to seek an answer to the
simpler question "What is Satisfiability?"
Satisfiability is the problem of determining if the variables of a given
Boolean function can be assigned in such a way as to make the function
evaluate to 1. Equally important is to determine that no such assignments
exist, implying that the function is identically 0 for all possible variable
assignments. In this latter case, we would say that the function is
unsatisfiable; otherwise it is satisfiable. To emphasize the binary nature of
this problem, it is frequently referred to as Boolean or propositional
satisfiability. The shorthand "SAT" is also commonly used to denote it, with
the implicit understanding that the function and its variables are all
binary-valued. The formal definition of SAT actually requires the function to
be expressed in the so-called conjunctive normal form (CNF), i.e., as an AND
of ORs.
In this form, each OR term is called a clause and acts as a constraint on the
possible values of its variables. For example the clause (A OR ~B OR C) is
satisfied by all 0-1 value assignments to A, B, and C except A = C = 0 and B
=1. A formula in CNF can, therefore, be viewed as a system of simultaneous
constraints in the space of binary assignments to its variables. To put this
in a broader context, it is useful to note the existence of other types of
"systems of simultaneous constraints," such as systems of linear inequalities
over real or integer variables which are used to model the set of feasible
assignments (a.k.a. the feasible region) in linear and integer linear
programs. The feasible region of a CNF formula contains precisely those
variable assignments that make the formula evaluate to 1.
SAT holds the distinction of being the first decision problem proved to be
NP-complete [1, 2]. But beyond this theoretical significance, efficient and
scalable algorithms for SAT that were developed over the last decade have
contributed to dramatic advances in our ability to automatically solve problem
instances involving tens of thousands of variables and millions of
constraints. Examples of such problems in EDA include routing of FPGAs [3],
combinational equivalence checking [4], model checking [5], verification of
pipelined microprocessors [6], logic synthesis [7], etc. In fact, a SAT
solving engine is now considered to be an essential component in the EDA
toolbox and all EDA vendors provide such a capability (usually behind the
scenes.) A SAT solver employs a systematic backtracking search procedure to
explore the (exponentially-sized) space of variable assignments looking for
satisfying assignments. The basic search procedure was proposed in two seminal
papers in the early 60s [8, 9] and is now commonly referred to as the
Davis-Putnam-Logemann-Loveland (DPLL) algorithm. Modern SAT solvers (developed
in the last ten years) augment the basic DPLL search algorithm with efficient
conflict analysis, clause learning, non-choronological backtracking (aka
backjumping), as well as "two-watched-literals" unit propagation, adaptive
branching, and random restarts [10-12]. These "extras" to the basic systematic
search have been empirically shown to be essential for handling the large SAT
instances that arise in EDA. Modern SAT solvers are also having significant
impact on the fields of software verification, constraint solving in
artificial intelligence, and operations research, among others.
Which brings us to SMT! Formally speaking, an SMT instance is a formula in
quantifier-free first-order logic, and SMT is the problem of determining
whether such a formula is satisfiable. But let's not get too carried away with
formalism! Imagine a Boolean SAT instance in which some of the binary
variables are replaced by "predicates" over a suitable set of non-binary
variables. A predicate is basically a binary-valued function of non-binary
variables. Example predicates include (integer) linear inequalities (e.g., 3x
+ 2y . z >= 4) or equalities involving so-called uninterpreted terms and
function symbols (e.g., f(f(u, v), v) = f(u, v) where f is some unspecified
function of two unspecified arguments.) We are still dealing with a
satisfiability problem, except that its solution now depends on our ability to
determine the satisfiability of the underlying predicates.
These predicates are classified according to the "theory" they belong to. For
instance, linear inequalities over real variables are evaluated using the
rules of the theory of linear real arithmetic, whereas predicates involving
uninterpreted terms and function symbols are evaluated using the rules of the
theory of uninterpreted functions with equality (sometimes referred to as the
empty theory). Other commonly-encountered theories include the theories of
arrays and list structures (useful for modeling and verifying software
programs), and the theory of bit vectors (useful in modeling and verifying
hardware designs). Subtheories are also possible: for example, difference
logic is a subtheory of linear arithmetic in which each inequality is
restricted to have the form x . y <= c for variables x and y and constant c.
In summary, then, an SMT instance is a generalization of a Boolean SAT
instance in which various sets of variables are replaced by predicates from a
variety of underlying theories. Obviously, SMT formulas provide a much richer
modeling language than is possible with Boolean SAT formulas. For example, an
SMT formula allows us to model the datapath operations of a microprocessor at
the word rather than the bit level.
Still, early attempts for solving SMT instances involved translating them to
Boolean SAT instances (e.g., a 32-bit integer variable would be encoded by 32
bit variables with appropriate weights and word-level operations such as
'plus' would be replaced by lower-level logic operations on the bits) and
passing this (much larger) formula to a Boolean SAT solver. This approach has
its merits: by pre-processing the SMT formula into an equivalent Boolean SAT
formula we can use existing Boolean SAT solvers "as-is" and leverage their
performance and capacity improvements over time. On the other hand, the loss
of the high-level semantics of the underlying theories means that the Boolean
SAT solver has to work a lot harder than necessary to discover "obvious" facts
(such as x + y = y + x for integer addition.) This observation was the impetus
behind the development, over the last couple of years, of a number of SMT
solvers that tightly integrate the Boolean reasoning of a DPLL-style search
with theory-specific solvers that handle conjunctions (ANDs) of predicates
from a given theory.
Dubbed DPLL(T) [13], this architecture gives the responsibility of Boolean
reasoning to the DPLL-based SAT solver which, in turn, interacts with a solver
for theory T through a well-defined interface.
The theory solver need only worry about checking the feasibility of
conjunctions of theory predicates passed on to it from the SAT solver as it
explores the Boolean search space of the formula. For this integration to work
well, however, the theory solver must be able to participate in propagation
and conflict analysis, i.e., it must be able to infer new facts from already
established facts, as well as to supply succinct explanations of infeasibility
when theory conflicts arise. In other words, the theory solver must be
incremental and backtrackable. An annual SMT solver competition was initiated
last year and has sparked a great deal of interest among developers and users
from a wide range of disciplines. Yices, the winner of this year's SMT
competition (held in August at the Computer-Aided Verification conference) has
all of these features, including a clever incremental Simplex algorithm for
the theory of linear arithmetic that integrated quite well within the DPLL
framework.
As an EDA professional, consider adding SAT and SMT solvers to your arsenal of
tools, and think of innovative ways of applying them in the design and
verification flow. They are readily available in the public domain, and are
remarkably easy to use (e.g., MiniSAT which won this year's SAT competition is
roughly 600 lines of C++!).
Useful Links:
SAT 2007: Tenth International Conference on Theory and Applications of
Satisfiability Testing (http://sat07.ecs.soton.ac.uk/)
MiniSAT Page
(http://www.cs.chalmers.se/Cs/Research/FormalMethods/MiniSat/MiniSat.html)
SMT-LIB: The Satisfiability Module Theories Library
(http://combination.cs.uiowa.edu/smtlib/)
Yices: An SMT Solver (http://yices.csl.sri.com/)
Selected References
[1] M. R. Garey and D. S. Johnson, Computers and Intractability: A Guide to
the Theory of NP-Completeness: W. H. Freeman and Company, 1979.
[2] S. A. Cook, "The Complexity of Theorem Proving Procedures," in Proc. 3rd
Ann. ACM Symp. on Theory of Computing, pp. 151-158, Association for Computing
Machinery, 1971.
[3] G.-J. Nam, K. A. Sakallah, and R. Rutenbar, "A New FPGA Detailed Routing
Approach via Search-Based Boolean Satisfiability," IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 6, pp.
674-684, 2002.
[4] J.-P. Marques-Silva and T. Glass, "Combinational Equivalence Checking
Using Satisfiability and Recursive Learning," in Proc.
Design, Automation and Test in Europe Conference, pp. 145-149, 1999.
[5] E. Clarke, A. Biere, R. Raimi, and Y. Zhu, "Bounded Model Checking Using
Satisfiability Solving," Formal Methods in System Design, vol.
19, no. 1, 2001.
[6] R. E. Bryant, S. M. German, and M. N. Velev, "Microprocessor Verification
Using Efficient Decision Procedures for a Logic of Equality with Uninterpreted
Functions," in Analytic Tableaux and Related Methods, pp. 1-13, 1999.
[7] M. Perkowski and A. Mishchenko, "Logic Synthesis for Regular Layout using
Satisfiability," in Proc. Intl Workshop on Boolean Problems, 2002.
[8] M. Davis and H. Putnam, "A Computing Procedure for Quantification Theory,"
Journal of the Association for Computing Machinery, vol. 7, no., pp. 201-215,
1960.
[9] M. Davis, G. Logemann, and D. Loveland, "A Machine Program for
Theorem-Proving," Communications of the ACM, vol. 5, no. 7, pp.
394-397, 1962.
[10] J. P. Marques-Silva and K. A. Sakallah, "GRASP: A Search Algorithm for
Propositional Satisfiability," IEEE Transactions on Computers, vol. 48, no. 5,
pp. 506-521, 1999.
[11] M. W. Moskewicz, C. F. Madigan, Y. Zhao, L. Zhang, and S. Malik,
"Chaff: engineering an efficient SAT solver," in Proc. 38th ACM/IEEE Design
Automation Conference, pp. 530-535, Las Vegas, Nevada, 2001.
[12] N. Een and N. Sorensson, "An Extensible SAT-solver," in Satisfiability
Workshop, 2003.
[13] C. Tinelli, "A DPLL-based Calculus for Ground Satisfiability Modulo
Theories," in Europ. Conf. on Logic in AI (JELIA), pp., 2002.
==============================================================================
Submission deadlines:
---------------------
IESS'07 - Int'l Embedded Systems Symposium
Irvine, CA
May 29-Jun 1, 2007
Deadline: Dec 20, 2006
http://www.iess.org/
ISVLSI'07 - Annual Symposium on VLSI
Porto Allegre, Brazil
May 9-11, 2007
Deadline: Jan 3, 2006 (extended)
http://www.inf.ufrgs.br/isvlsi2007/
RSP'07 - Int'l Workshop on Rapid System Prototyping
Porto Alegre, Brazil
May 28-30, 2007
Deadline: Jan 7,2007
http://www.rsp-workshop.org/
MSE'07 - Int'l Conference on Microelectronic Systems Education
San Diego, CA
Jun 3-4, 2007
Deadline: Jan 15, 2007
http://www.mseconference.org/
CAV'07 - Int'l Conference on Computer Aided Verification
Berlin, Germany
Jul 3-7, 2007
Deadline: Jan 28, 2007
http://www.cav2007.org/
ICICDT'07 - Int'l Conference on IC Design & Technology
Austin, TX
May 30-Jun 1, 2007
Deadline: Feb 15, 2007
http://www.icicdt.org/
MWSCAS/NEWCAS'07 - Int'l Midwest Symposium on Circuits and Systems/
Int'l NEWCAS Conference
Montreal, Canada
Aug 5-8, 2007
Deadline: Feb 20, 2007
http://newcas.grm.polymtl.ca/
IWLS'07 - Int'l Workshop on Logic & Synthesis
San Diego, CA
May 30-Jun 1, 2007
Deadline: Mar 2, 2007
http://www.iwls.org/
FPL'07 - Int'l Conference on Field-Programmable Logic and Applications
Amsterdam, Holland
Aug 27-29, 2007
Deadline: Mar 18, 2007
http://www.fpl.uni-kl.de/fpl/
PACT'07 - Int'l Conference on Parallel Architectures and Compilation
Techniques
Brasov, Romania
Sep 15-19, 2007
Deadline: Mar 26, 2006
http://www.pactconf.org
ICCAD'07 - Int'l Conference on Computer-Aided Design
San Jose, CA
Nov 4-8, 2007
Deadline: Apr 11, 2007
http://www.iccad.com/
==============================================================================
Upcoming symposia, conferences and workshops:
---------------------------------------------
ThETA'07 - Int'l Conference on Thermal Issues in Emerging Technologies:
Theory and Applications
Cairo, Egypt
Jan 3-6, 2007
http://www.thetaconf.org
VLSI'07 - Int'l Conference on VLSI Design
Bangalore, India
Jan 6-10, 2007
http://www.vlsiconference.com/2007/
ASPDAC'07 - Asia and South Pacific Design Automation Conference
Yokohama, Japan
Jan 23-26, 2007
http://www.aspdac.com/aspdac2007/
FPGA'07 -Int'l Symposium on Field-Programmable Gate Arrays
Monterey, CA
Feb 18-20, 2007
http://conferences.ece.ubc.ca/isfpga2007/
TAU'07 - Int'l Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems
Austin, TX
Feb 26-27, 2007
http://www.tauworkshop.com/
SPL'07 - Southern Conference on Programmable Logic
Mar del Plata, Argentina
Feb 26-28, 2007
http://www.splconf.org/
GLSVLSI'07 - Great Lakes Symposium on VLSI
Stresa-Largo Maggiore, Italy
Mar 11-13, 2007
http://www.glsvlsi.org/
LATW'07 - Latin-American Test Workshop
Peru
Mar 11-14, 2007
http://www.latw.net/
ASYNC'07: Int'l Symposium on Asynchronous Circuits and Systems
Berkeley, CA
Mar 12-14, 2007
http://conferences.computer.org/async2007/
SLIP'07 - System Level Interconnect Prediction Workshop
Austin, TX
Mar 17-18, 2007
http://www.sliponline.org/
ISPD'07 - Int'l Symposium on Physical Design
Austin, TX
Mar 18-21, 2007
http://www.ispd.cc/
DATE'07 - Design, Automation, and Test in Europe
Nice, France
Apr 16-20
http://www.date-conference.com/
NOCS'07 - Int'l Symposium on Networks-on-Chips
Princeton, New Jersey
May 7-9, 2007
http://www.nocsymposium.org/
ISVLSI'07 - Annual Symposium on VLSI
Porto Allegre, Brazil
May 9-11, 2007
http://www.inf.ufrgs.br/isvlsi2007/
IESS'07 - Int'l Embedded Systems Symposium
Irvine, CA
May 29-Jun 1, 2007
http://www.iess.org/
ICICDT'07 - Int'l Conference on IC Design & Technology
Austin, TX
May 30-Jun 1, 2007
http://www.icicdt.org/
IWLS'07 - Int'l Workshop on Logic & Synthesis
San Diego, CA
May 30-Jun 1, 2007
Deadline: Mar 2, 2007
http://www.iwls.org/
MSE'07 - Int'l Conference on Microelectronic Systems Education
San Diego, CA
Jun 3-4, 2007
http://www.mseconference.org/
DAC'07 - Design Automation Conference
San Diego, CA
Jun 4-8, 2007
http://www.dac.com/
==============================================================================
Call for Participation
------------------------
SELSE-3 Workshop, Silicon Errors in Logic - System Effects April 3rd & 4th,
2007 Austin, Texas
The growing complexity and shrinking geometries of modern device technologies
are making these high-density, low-voltage devices increasingly susceptible to
influences from electrical noise, process variation, and natural radiation
interference. System-level effects of these errors can be far reaching.
Growing concern about intermittent errors, erratic storage cells, and the
effects of aging are influencing system design. This workshop provides a forum
for discussing current research and practices in system-level error
management. Participants from industry and academia explore both current
technologies and future research direction (including nanotechnology). We are
interested in soliciting papers that cover system-level effects of errors from
a variety of perspectives: architectural, logical and circuit-level, and
semiconductor processes. Case studies are also solicited.
Key areas of interest are (but not limited to):
* Technology trends and the impact on error rates.
* New error mitigation techniques.
* Characterizing the overhead and design complexity of error mitigation
* techniques.
* Case studies describing the engineering tradeoffs necessary to decide what
* mitigation technique to apply.
* Experimental data.
* System-level models: derating factors and validation of error models.
* Error handling protocols (higher-level protocols for robust system design).
Authors are requested to submit their extended abstracts for review before
December 20, 2006. Guidelines for submission are available at www.selse.org.
Submissions should be PDF or Microsoft Word files that do not exceed four
printed pages. Customary terms for copyright agreement and non-confidentiality
will apply. Authors will be notified of paper outcome by March 2, 2007. The
camera-ready formatted papers are due on March 23, 2007.
Registration information is posted on the workshop website:
www.selse.org
Organizing committee:
Workshop Co-chairs
Wendy Bartlett (HP)
Pia Sanda (IBM)
Program Co-chairs
Dennis Abts (Cray)
Subhasish Mitra (Stanford)
Web Chair
Jeff Wilkinson (Medtronic)
Publications Chair
Norbert Seifert (Intel)
Publicity Co-Chairs
Cristian Constantinescu (Intel)
Babak Falsafi (CMU)
Local Arrangements Chair
Nur Touba (UT Austin)
Finance Co-chairs
Nhon Quach (AMD)
Vivian Zhu (Texas Instr)
Panel Co-Chairs
Ishwar Parulkar (Sun)
Josep Torrellas (Univ Illinois)
Advisory Committee
Sarita Adve (Univ Illinois)
Ravi Iyer (Univ Illinois)
Chuck Moore (AMD)
Lisa Spainhower (IBM)
==============================================================================
Upcoming funding opportunities
-------------------------------
DOD
High Density Optical Memory
Deadline: Continuous
http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf
Quantum Electronic Solids
Deadline: Continuous
http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf
Distributed Intelligence
Deadline: Continuous
http://www.afosr.af.mil/pdfs/afosr_baa_2007_1.pdf
Young Faculty Award
Deadline: December 5, 2006
http://www.grants.gov/search/search.do?oppId=10908&mode=VIEW
Experimental and Theoretical Development of Quantum Information Science
Deadline: December 11, 2006
http://www.arl.army.mil/main/Main/DownloadedInternetPages/CurrentPages/DoingBusinesswithARL/research/QC06Final6Jul06.pdf
Enabling Technologies for Modeling and Simulation (BAA-03-12-IFKA)
Deadline: September 30, 2008
http://www.fbo.gov/spg/USAF/AFMC/AFRLRRS/BAA-03-12-IFKA/Modification%2005.html
Joint National Training Capability Broad Agency Announcement
Deadline: May 14, 2009
http://www.ntsc.navy.mil/Ebusiness/BusOps/Acquisitions/Index.cfm?RND=220990
BAA for Simulation and Training Technology R&D
Deadline: Continuous until December 31, 2010
http://www.ntsc.navy.mil/EBusiness/BusOps/Acquisitions/Index.cfm?RND=868451
NSF
Theoretical Foundations 2007 (TF07) (NSF 07-525)
Deadline: January 19, 2007 - February 19, 2007
http://www.nsf.gov/pubs/2007/nsf07525/nsf07525.htm
Emerging Models and Technologies for Computation (EMT) (NSF 07-523)
Deadline: February 14, 2007
http://www.nsf.gov/pubs/2007/nsf07523/nsf07523.htm
Engineering Design (ED)
Deadline: January 15, 2007 - February 15, 2007
September 1, 2007 - October 1, 2007
http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=13340
Computer Systems Research (CSR) (NSF 07-504)
Deadline: January 17, 2007
http://www.nsf.gov/pubs/2007/nsf07504/nsf07504.htm
Strategic Technologies for Cyberinfrastructure (STCI)
Deadline: February 8, 2007
http://www.nsf.gov/funding/pgm_summ.jsp?pims_id=500066&org=NSF&sel_org=NSF&from=fund
Software Development for Cyberinfrastructure (SDCI) (NSF 07-503)
Deadline: January 22, 2007
http://www.nsf.gov/pubs/2007/nsf07503/nsf07503.htm
Cyber Trust (CT) (NSF 07-500)
Deadline:
January 8, 2007
http://www.nsf.gov/pubs/2007/nsf07500/nsf07500.htm
Information and Intelligent Systems: Advancing Human-Centered Computing,
Information Integration and Informatics, and Robust Intelligence (NSF
06-572)
Deadline:
October 19, 2006 for Large Projects
November 02, 2006 for Medium Projects
December 06, 2006 for Small Projects
http://www.nsf.gov/pubs/2006/nsf06572/nsf06572.htm
Advanced Learning Technologies (ALT) (NSF 06-535)
Deadline: April 25, 2007
http://www.nsf.gov/pubs/2006/nsf06535/nsf06535.htm
DARPA
Cognitive Information Processing Technology (BAA02-21)
Deadline: June 5, 2007
http://www.darpa.mil/ipto/Solicitations/open/02-21_PIP.htm
NASA
Applied Information Systems Research
Deadline: January 30, 2007
http://nspires.nasaprs.com/external/solicitations/summary.do?method=init&solId={0B64DB41-8F7D-C949-44CD-9D04A484B653}&path=open
==============================================================================
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