Workshop on Exploiting Parallelism with Transactional Memory
and other Hardware Assisted Methods

to be held in conjunction with CGO 2008
April 6, 2008, Boston, MA

EPHAM 2008 will provide a forum for compiler and processor
architecture researchers to exchange ideas for leveraging hardware
assistance to break down traditional barriers to exploiting
parallelism. The workshop will focus on compilation techniques for
exploiting parallelism in emerging multi-core and multi-threaded
architectures with a particular focus on the use of transactional
memory to overcome traditional barriers to parallelization. Current
trends in micro-processor architecture clearly point to a tapering off
of clock frequencies, and a shift toward supporting many cores and
threads. This change makes the compiler's task of extracting and
exploiting parallelism in applications even more
important. Recognizing various difficulties in parallelization,
implementations are emerging that attempt to provide various forms of
hardware assist for the same. One of these techniques, transactional
memory, has drawn significant interest in both industry and
academia. Transactional memory will be a focus, but other techniques
to solve this problem are also of interest. Topics of interest
include, but are not limited to the following.

Extended abstracts of 6-10 pages may be submitted using any format.
The abstract should clearly state the problem being studied, the
methods used, and the results. If the results are preliminary, the
authors should state their expectation for the final results. To
submit, please send a pdf of your submission to epham@acm.org Final
submissions should use the standard ACM conference format (two columns
with 9 pt Times Roman font, etc.).