Intel prepares for optical-interconnect future

AUSTIN, Texas  Intel Corp. has developed an optical interconnect architecture that over the next decade could form the basis for chip-to-chip interconnects, linking a microprocessor with its logic chip set, for example.

Serial point-to-point links, based on copper interconnects inlaid to printed-circuit boards, may be able to support chip-to-chip interconnect speeds as high as 15 Gbits/second. That is roughly double the 6- to 8-Gbit/s chip-to-chip interconnect speeds seen today, said Ian Young, director of advanced circuits and technology at Intel's logic technology development group in Hillsboro, Ore. After copper hits its physical limits, however, optical will be needed to take the industry to 20 Gbits/s and beyond, he said.

"We want to use copper traces on FR4 [boards] as long as possible," said Young. As the frequency increases over copper wires, attenuation quickly becomes a limiting factor, one that is largely avoided with optical links.

Some companies are using optical links now to connect servers within a data center. Extending optical to work at the short chip-to-chip distances of perhaps 10 inches or so involves certain technical challenges. But the main issues are related to cost and manufacturing concerns, Young said.

Some optical components are not only expensive (thus the push to CMOS for the transceiver), but also alignment and special packaging quickly add costs that may be acceptable for long-haul links but are much too pricey for personal computers.

"We are taking a pragmatic approach to optical, getting ready for that day in the 2010 to 2015 time frame" when copper traces no longer can keep up with tomorrow's MPUs, Young said.

By then, CMOS-based transistors will be fast enough for transceivers to operate at clock speeds of roughly 14 GHz, fast enough to support data transfer rates of 20 Gbits/s. With huge transistor budgets at the 32-nanometer node, at some point the CMOS transceiver could be integrated onto a microprocessor die, Young said.

For now, Intel has developed a three-chip solution that is packaged in the same type of flip-chip pin-grid-array package used now for Intel's MPUs. The goal of the project is to develop a low-cost form of CMOS-based optical interconnect that can be integrated with a microprocessor substrate.

The Intel group developed a 12-channel optical link, with eight data, two clock and two alignment channels, delivering an 8-Gbit/s aggregated data rate. Besides the CMOS transceiver, the package incorporates vertical-cavity surface-emitting lasers (VCSELs), positive-intrinsic-negative (PIN) photodetectors and polymer waveguides.

The CMOS transceiver was made with 0.18-micron design rules and contains the VCSEL drivers, transimpedance and limiting amplifiers, and on-chip self-test circuits. By the time the optical approach is used for chip-to-chip interconnects, CMOS "will be competitive with any III-V-based components," Young said.

For now, Intel intends to stick with a planar package, in which the components are positioned side-by-side.

The CMOS-based transceiver must be fast enough to feed a microprocessor with data. But that is only part of the solution. Creating a cost-effective manufacturing flow that allows the waveguides, PIN and VCSEL parts, and the transceiver to be packaged without heat-related damage to the optical components is another challenge. For example, the waveguides are thicker than the solder balls of the other components, which means that a trench must be fabricated in the substrate to provide enough clearance for the optoelectronic components.