Profilul candidatului:

Requirements:Bachelor or Master of Automatic Control and Computer Engineering / Computer Science with strong OOP skills and 3+ years of verification experience (Masters preferred)-Software development proficiency required in C++ and OOP and familiar with at least one of the following: SystemVerilog; Vera; Specman-E. (SystemVerilog preferred).- Experience required in development and execution of pre-silicon test plans and in development of verification environment components and infrastructure- Strong communication skills and fluency in verbal and written English required- Experience with industry standard verification tools required (VCS simulator and Verdi debug system preferred)- Knowledge and verification-experience with JTAG and DFT/DFD/DFY logic features preferred (not required)- UVM