I was motivated by the discussion on EASy68K-compatible, 68000 computer (viewtopic.php?f=10&t=829) and my recent great experience with a 68302- based single board computer to think seriously about a bare-bone 68302 homebrew. The 68302 is effectively a 68000 (or 68008) integrated with a very powerful I/O processor. Most the features people wanted are inside the 68302 such as timers (3), multiple serial ports (3), SPI master, interrupt controller, discrete I/O, programmable chip selects (which can function as memory remap). The 68302 can be configured like 68008 with byte-wide external memories. So a minimum system can be just a CPU, a RAM and a flash plus an 16MHz oscillator. A quick hand sketched schematic shows there are only about 60 address/data/control connections, 25 power/ground, and about 15 hardware configuration connections. The address/data/control connections can be cut to 30 if the RAM and flash are stacked together, piggy-back fashion, since so many RAM and flash signals have the same pin assignment. All devices are available in DIP and PGA package, so hand wiring 70 or so connections can be done easily in a evening (theoretically speaking ).

I have 128K RAM and flash in DIP package, but I don't have 68302 in PGA. You can buy them on eBay for under $20, but I thought I'll try with a quad flat pack 68302 that I removed from a 68302 SBC. (I removed all components so I can reverse engineer the pc board connections). The lead spacing of the QFP is 25 mil, so I have to work under a microscope and it will take more than an evening to wire 60 or so connections to the QFP.

I want to have a solid digital ground, so all components will be mounted on a single-sided copper board, roughly 2"x5". Most of the copper foil is digital ground except areas carved out for other signals such as pads for the piggy-back RAM and flash. The piggy-back RAM/flash is soldered to the board because I need solid mechanical support to insert and remove the flash many times (picture 1).

The QFP 68302 was glue to the board, dead-bug fashion. Ground leads are bend down toward the copper foil for short ground connections and Vcc leads bend toward the center where a 5V ring will be constructed. A third of way into wiring, after ground/power were connected and all hardware configuration finished, I connected the 16MHz oscillator and power up the CPU with oscillator. I can see chip select 0 puts out 8 successive pulses to fetch reset vector and system stack and repeat every 1 millisecond. That means the CPU is probably OK, even though I'd treated it rather badly when removing with a heat gun. Soldering 60 or so connection to the QFP 68302 was challenging and it did take more than an evening. I know I can do it 10 years ago and I'm glad I still can do it. Nevertheless I'll stick with the PGA package on the next iteration!

Photo 2 shows the finished board. It can fetch reset vector and execute an endless loop of NOP so flash is working. I'll need to test the RAM next and then bring up a simple bootloader and then the EASy68K compatible monitor!

An update of Tiny302: The board is a bit larger because I added a 5V power plane to beef up the 5V power. Initially it is because I've had memory diagnostic errors and I thought it may due to noisy 5V. It turned out it was due to a faulty documentation of the 128K static RAM. Two of the pin assignments were incorrect! Once that was corrected, the memory diagnostic passed. I also added a RS232 tranceivers to interface with the serial port--the funny looking connector at the right edge of the board mates with pin 2, 3, and 7 of a serial cable.

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The software development went well. It currently is running a monitor/debugger of my own design. It does the basic file load, memory read & write, breakpoint and trace functions. It also has a RAM/Flash remap command so Flash is mapped to high memory while RAM mapped to $0. With that I'm able to load a modified Tutor v1.3 and see it running. So I guess I'm done with the board. I'll pour epoxy over the surface mount parts to keep them from shorting.

Below is a screen shot of Tiny302 booting up; a help menu of the monitor/debugger; remap command ('sw') to swap RAM and Flash; load the modified Tutor; and Tutor help output. That was fun.

I found a couple MC68302 in PGA package buried in my junk piles. So I constructed a more rugged Tiny302 prototype to experiment with. It is certainly a better looking prototype. It is the same design with 8-bit wide data bus using 128Kx8 Flash and 128Kx8 RAM so the existing monitor/debugger runs on it as is. Running at 16MHz with zero-wait memory, it's performance is roughly that of a 8MHz 68K with 16-bit wide bus. Except for a few SMT bypass caps, this is a thru-hole design, down to a dozen or so of discrete carbon resistors. I plan to build EASy68K's 7-segment/LED/push button hardware on the remaining prototype area using the same thru-hole component technology.

The schematic of the prototype is done using a very old tool, IVEX's Windraft. IVEX is no longer in business, but I've purchased the license for both schematic and board layout tools a long time ago. Windraft seems to run OK in Windows Vista, but the version of Winboard I have needs to run on older WIndows operating system. If anyone knows how to get Winboard to run in newer Windows, please let me know.

Here is a picture of Tiny302 posted earlier with the addition of a seven-segment/LED/switch display. The display is compatible with the simulated hardware display in Sim68K so the software that runs in simulation will run on this hardware. It is a memory-map implementation so there are actual 8-bit latches resides in memory locations as documented in the EASy68K Help. The LED and 7-seg displays are power hogs, drawing about 15-20mA per segment so it consumes over an amp @5V when it is fully lit. The challenges are using drivers that can source the required current, yet not too powerful to require current limiting resistors everywhere. I used a stack of 3 silicon diodes to raise the output voltage of HC drivers (74HC273 & 74HC240) to over 3V which begins to limit its output currents--it is not a textbook design, but does work.

This design is probably meant for pc board. It is pretty tedious to hand wire all these connections. I thought about using Altera's 7128S CPLD, but there are more connections than can be fitted in a 84PLCC and current drive capability is an issue, so discrete TTLs on pc board is probably the right implementation.

Half way into wiring the board, I thought of another way of doing this that's quite a bit simpler in logics and interconnects. It requires the CPU to drive each 7-segment display in rapid succession and relies on persistence of vision to blend them into one solid image of eight 7-segment display. It does not need connection into actual address & data buses so I can use the 82C55 peripheral chip on the repurposed 68302 SBC to drive the simplified hardware display. That should be an interesting project next.

I tried to upload the schematic, but it is too large and a reduced-resolution schematic is not very readable. Can the forum software accept PDF file or larger jpeg file (1 megabyte)?

I sent out two 100mm x 100mm designs so to reduce the shipping cost per board. The Tiny302 pc board is one of the designs. I uploaded both designs to SeeedStudio in Shenzhen China Sunday night, they started production Tuesday and ship out the boards Thursday and I received both boards last night, 8 days later. Once again, these boards are very well made. This is very impressive.

The Tiny302 pcb design is similar to the prototype shown in the earlier posts of this thread. It is consists of the core 68302/RAM/Flash/oscillator plus the hardware display & switches. I assembled the core this morning and populated it with the boot flash removed from the prototype board. Powered it up and it worked! Way cool!

Here is the fully assembled board. The board is tightly packed. The eight 7-seg displays barely fit in the 3.9" wide pc board. I also have to put a component under the boot flash and resistors/FET drivers on the solder side of the board. The display works except for one digit that is wired incorrectly at the schematic level. The mistake can be easily corrected before the board is populated, but now I have to fix it in the trap #15 routine which is undesirable as the software for this board would be different than all others.

The design also has a different configuration where 4 of the 7-seg displays are replaced with a 4-line LCD display, but first I'll tackle my 2nd pc board design which is a 68030 with 16 megabyte DRAM.

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