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This is another favourite topic for the examiner to set a question questions. So students need prepare it strongly. In the coming B.Tech 5th semester examination, you will definitely find one question on the this topic i.e. 8085 microprocessor interrupts. As MDU university used to held semester examination in December. The concept of 8085 microprocessor interrupts is very easy to prepare for the examination and its a very scoring topic in the subject of Microprocessor and interfacing.

Discuss in detail 8085 interrupts.

8085 Interrupts : The interrupt driven I/O is one of the data transfer techniques used in the microprocessor systems. By using this techniques, the external device or a peripheral can inform the microprocessor that it is ready for communication.

In 8085 microprocessor there are two types of interrupts : Hardware and software interrupts.

TRAP : It is non-maskable edge and level triggered interrupt, request input line. It is used for emergency purpose like power failure, parity error checker, smoke detector etc. The microprocessor does not execute any interrupt acknowledge cycle to read interrupt information from the interrupting device. The interrupt information is provided by control section of microprocessor internally. But microprocessor executes ideal machine cycle to acknowledge this interrupt. To generate starting address of TRAP interrupt service routine. The TRAP signal must make low to high transition and remain high until acknowledged that means this interrupt is triggered only at the rising edge of the signal. This avoids false triggering due to noise or glitches. It is not affected by any instruction. It has the highest priority among all interrupt. It is always enabled. This interrupt transfers microprocessors control to location 0024 H. User cannot rest TRAP flip-flops that means we cannot cancel this interrupt.

RST 7.5 : It is maskable edge triggered interrupt request input line. The microprocessor does not execute any interrupt acknowledge cycle to read interrupt information from the interrupting device. The interrupt is provided by control selection of microprocessor internally. Instead of interrupt acknowledge cycle, the microprocessor executes ideal machine cycle (6T) to acknowledge this interrupt. During this cycle it executes RST 7.5. Instruction to generate starting address of interrupt service routine. This interrupt is triggered at the rising edge of the signal. Its priority among all maskable interrupt. This interrupt to location 003ch. User can reset RST 7.5 flip-flop that means we can cancel this interrupt by SIM instruction.

RST 6.5 and RST 5.5 : These are level triggered maskable interrupt request input lines. The microprocessor does not execute any interrupt acknowledge cycle to read interrupt information from the interrupting device. The microprocessor executes idle machine cycle (6T) to acknowledge these interrupts. During this cycle it executes RST 6.5 and RST 5.5 instructions to generate address of ISR 6.5 and ISR 5.5 respectively. They can be disabled by executing SIM or EI instruction. RST 6.5 transfers microprocessor's control to location 0034 H while RST 5.5 transfers microprocessor's control to location 002 CH.