High-Performance Memory System for Network Applications

In a modern chip-multiprocessor system, memory is a shared resource among multiple concurrently executing programs. Multiple programs executing on different cores can interfere with each other upon memory access requests, thereby adversely affecting each other’s performance. Earlier approaches to alleviate these interference include designing new memory scheduling algorithms or thread partitioning algorithms. However there are limitations of using software method alone to solve the problem. Our research goal is to design a new DRAM architecture and software technology to achieve best system throughput and fairness in multi-core and many-core environments.