<p>The basic features of a content-addressable processor/register array (CAPRA) are discussed. The features are the inclusion of logic elements directly within the word cells or bit cells of memory, use of a maskable decoder to enable multiaccess to the memory and computing devices of the array, activity flags within the cells of the array to enable flexible definition of activity patterns, and integration of sensor elements for the direct parallel input of optical data. The architecture's potential applications in database support, basic numerical tasks, and image processing are discussed.</p>