What are the IA-32 and Intel® 64 processor targeting options in the Intel® compilers?
There are three main types of processor-specific optimization options:

Processor-specific options of the form /arch:<code> on Windows* ( -m<code> on Linux* or Mac OS* X) generate specialized code for processors specified by <code>. The resulting executables from these processor-specific options can be run on the specified or later Intel® and compatible, non-Intel® processors that support the instruction set. The executable may incorporate optimizations specific to those processors and use a specific version of the Intel® Streaming SIMD Extensions (Intel® SSE) instruction set and/or the Intel® Advanced Vector Extensions (Intel® AVX) instruction set; on older processors without support for the corresponding instruction set, an illegal instruction or similar error may occur.

The value for <code> can be one of the following (note that <code> must be lower case on Linux or OS X, but may be either case on Windows) :

May generate Intel® SSE2 and SSE instructions. /arch:SSE2 is the default on Windows and -msse2 is the default on Linux.

ia32

Generates generic IA-32 compatible code. Can only be used with the /arch: or -m switches. (IA-32 compiler only).

Processor-specific options of the form /Qx<code> on Windows*( -x<code> on Linux* or OS X*) generate specialized code for processors specified by <code>. The resulting executables from these processor-specific options can only be run on the specified or later Intel® processors, as they incorporate optimizations specific to those processors and use a specific version of the Intel Streaming SIMD Extensions (Intel SSE) instruction set and/or the Intel® Advanced Vector Extensions (Intel® AVX) instruction set. This switch enables some optimizations not enabled with the corresponding switches /arch:x<code> or -m<code>. A run-time check is inserted in the resulting executable that will halt the application if run on an incompatible processor. This is intended to help you quickly find out that the program was not intended for the processor it is running on and potentially avoids an illegal instruction error. For this check to be effective, the source file containing the main program or the dynamic library main function should be compiled with this option enabled.

The value for <code> can be (in upper or lower case):

KNM

May generate Quad Fused Multiply Add (QFMA) and Quad Virtual Neural Network Instruction (QVNNI) and the instructions enabled with MIC-AVX512. Optimizes for the Intel® Xeon Phi™ product family processor code name Knights Mill. Available in compiler version 18 and later for Windows and Linux only.

May generate Intel® SSSE3, SSE3, SSE2 and SSE instructions for Intel® processors. Optimizes for Intel® Core™ microarchitecture. -xssse3 is the default for the Intel® 64 architecture compiler on OS X*.

ATOM_SSSE3

May generate SSSE3, Intel® SSE3, SSE2 and SSE instructions for Intel® processors. May also generate MOVBE instructions if the option /Qinstruction:movbe (-minstruction=movbe) is set. Optimizes for Intel® Atom™ processors that support SSSE3 and MOVBE instructions.

SSE3

May generate Intel® SSE3, SSE2 and SSE instructions. Optimizes for the enhanced Intel® Pentium® M processor microarchitecture and Intel® Netburst microarchitecture. -xsse3 is the default for the IA-32 compiler on OS X*.

SSE2

May generate Intel® SSE2 and SSE instructions. Optimizes for the Intel® Netburst microarchitecture.

HOST

May generate instructions from any of the above instruction sets that are supported by the compilation host processor. See the Intel® Compiler User and Reference Guide for further information, including behavior on compatible, non-Intel processors.

Processor-dispatch options of the form /Qax<code> on Windows* ( -ax<code> on Linux* or OS X*) allow the generation of multiple code paths for Intel® processors. Processor dispatch technology performs a check at execution time to determine which processor the application is running on and use the most suitable code path for that processor. Compatible, non-Intel processors will take the default optimized code path. The switches described in 1. and 2. above can be used to modify the default optimized code path.

You can use two of the feature values by combining them. For example, you can specify -axSSE4.1,SSSE3 (Linux OS and OS X) or /QaxSSE4.1,SSSE3 (Windows OS). In this example, an Intel® SSE4.1-optimized sequence will be used on Intel processors that support it, an Intel® SSSE3-optimized sequence on Intel processors that support SSSE3 but not SSE4.1, and a default path on all other processors.

Where the value for <code> can be:

KNM

May generate Quad Fused Multiply Add (QFMA) and Quad Virtual Neural Network Instruction (QVNNI) and the instructions enabled with MIC-AVX512. Available in compiler version 18 and later for Windows and Linux only.

When compiling for the IA-32 architecture or the Intel® 64 architecture on Windows* or Linux*, /arch:SSE2 (Windows*) or -msse2 (Linux*) is the default. The resulting code path should run on the Intel Pentium 4 and Intel Xeon processors with SSE2 support and other later Intel processors or compatible non-Intel processors with SSE2 support.

When compiling for the IA-32 architecture on OS X*, -xSSE3 is the default. The compiler may generate SSE3, SSE2 and SSE instructions and the code is optimized for enhanced Pentium M processor microarchitecture.

When compiling for the Intel® 64 architecture on OS X* , -xSSSE3 is the default. The compiler may generate SSSE3, SSE3, SSE2 and SSE instructions and the code is optimized for the Intel® Core™ microarchitecture.

To target older IA-32 systems without support for SSE2 instructions, such as systems based on the Intel® Pentium® III Processor, use the switch /arch:ia32 (Windows*) or -mia32 (Linux*).