I used to have anxiety about this as well. We have a very similar situation
for a switch design in which we distribute the clock (PECL) to the switch
ASIC then the ASIC drives the SERDES ref clock and data using LVTTL, a
source synchronous design. Using a state-of-art TIA to measure jitter, we
can keep the PECL clock going into the ASIC very clean, like < 100psec pk-pk
jitter. But the jitter on the output clock coming out of the ASIC is like
250psec pk-pk. Doing a FFT of the jitter shows this jitter - termed buffer
jitter - is very high frequency in nature, actually harmonics of the ASIC
clocks. Fortunately, the SERDES filters this jitter out and the link is
extremely reliably running copper.

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