The ZX Spectrum SE is a second generation [[:category:clones|Spectrum clone]] created by Andrew Owen and Jarek Adamski in the final year of the twentieth century. Although only a single prototype was created, it is supported by a number of [[emulators]] on various platforms. It should not be confused with the [[SE Basic]] [[:category:ROMs|ROM]]. The [[Chloe 280SE]] specification is based on this machine.

The SE combines the RAM paging systems of the [[Timex 2000 series|Timex TS2068]] with the ZX Spectrum 128 and then adds another 16K to that. This means it uses two different systems to access its full 272K 272kB of RAM. Jarek installed his 128 compatibility upgrade to take the RAM to 144K 144kB and then installed a 128K 128kB SRAM connected to the Timex memory management unit.

The Timex Horizontal MMU sees the RAM as three banks of memory; HOME, DOCK, and EX banks.

The HOME bank is the normal Spectrum memory area. The top 32K 32kB is uncontended but the 16K 16kB screen area below that is contended. DOCK and EX banks are overlaid on this bank, but paging over the screen area does not change the RAM used by the ULA. This does mean it is possible to set up a screen and page it out.

Memory is paged in 8K 8kB banks from either the DOCK or the EX bank, but these banks are mutually exclusive - you cannot page in a bank from both simultaneously. Bit 7 of port 0xff determines which bank to use (0=DOCK, 1=EX-ROM). Port 0xf4 determines which banks are to be paged in with each bit referring to the relevant bank (0-7 or 0'-7'). When memory is being paged, interrupts should be disabled and the stack should be in an area which is not going to change.

On a [[Timex 2000 series|TC2048]], BASIC is contained in the 16K ROM area and banks 0-7 and 0'-7' are not normally available, while on a TS2068 part of the BASIC is stored in an 8K 8kB ROM in bank 0' and cartridges plugged into the dock use banks 0-7. On the SE each of these banks is connected to 64K 64kB of RAM, providing an additional 128K 128kB in addition to the base RAM.

The contended memory timings for the SE are unknown but should be similar to that for the 48K machine, except that the pattern starts at a different number of T-states after the interrupt, than the usual 14335. Odd banks in the 128 scheme are contended.

Reading this port returns the last byte sent to it.

The TS2068 only has 48K 48kB of base RAM, but the SE has also been expanded to use a variation of the ZX Spectrum 128 paging system to increase the base RAM to 144K144kB. This means that the HOME bank is paged like a normal Spectrum 128, except that there is an additional bank at 0x8000 where you would expect to find Bank 2. This does not appear to cause any problems with existing commercial software, although some demos (such as 'Real Action') are affected, but it provides some more memory.

The HOME bank is paged in the same way as the Spectrum 128, using port 0x7ffd.

== ROM ==

The standard ROM is replaced with a 64K 64kB EPROM. Only two pages are visible to the hardware;

The first is a modified version of the ZX Spectrum 128 editor. A call to the TEST routine in ROM-1 is replaced with code to reset the Timex ULA.

The second is an exact copy of the original ZX Spectrum BASIC but has TR-DOS traps in place of the character set (0x3c00..to 0x3fff is filled with PUSH AF: RST 8: NOP: NOP).

This makes the machine more compatible with existing software titles than the original ZX Spectrum 128. A third page is exactly as the same as the first and a fourth page is exactly the same as second, but without TR-DOS traps (it has the character set). The A15 line of EPROM is connected to /M1 of Z80, while the A14 is connected to bit 3 of the 0x7ffd port latch. The TR-DOS traps allow emulation of TR-DOS by the ZXVGS operating system. Custom ROMs can be loaded into memory and paged into place using the DOCK or EX banks. Jarek has fitted an external NMI button for ROMs with a working NMI routine.

== Sound chip ==

The [[AY-3-8912]] sound chip has an added 8K 8kB serial EEPROM. Port 14 of the AY is used as an IIC I²C driver (must work as output). Bit 0 is the SDA (data) line, bit 1 is SCL (clock) of the IICI²C. The chip mapped to four I/O ports:

OUT (0xfffd) - Select a register 0-14.

IN (0xfffd) - Read the value of the selected register.

Screen 0 is the normal screen at the start of video memory. Screen 1 uses the same format but is offset by 8K.

The hi-res screen uses the data area of screen 0 and screen 1 to create a 512x192 512×192 pixel screen. Columns are taken alternately from screen 0 and screen 1. The attribute area is not used. In this mode all colours, including the BORDER, are BRIGHT, and the BORDER colour is the same as the PAPER colour.

The hi-colour screen uses the data area of screen 0 for its data and the data area of screen 1 for its attributes, giving 2 colours per 8x1 pixel block. The attribute area is in the same byte order as the data area, which means MLT files, which have the attribute area in series, must be converted to be displayed.

With careful timing it is possible to mix screen modes so you could have a screen where the top half is hi-colour and the bottom half is hi-res - perfect for text adventures with graphics. Using a similar technique it is also possible to have more than two colours on a hi-res screen. No commercial software ever did this though.

In addition to these screen modes the ULA can access two separate video areas, just like a Spectrum 128. This is done by using bit 3 of port 0x7ffd. This gives the ULA a total of 27K 27kB of RAM which can be used for up to four standard screen areas or two hi-res or hi-colour screens.

Port 0xfe deals with basic I/O. As mentioned before addresses are fully decoded, so whereas on a normal Spectrum every even I/O address will address the ULA, the SE will only respond to the correct port. The port is decoded as follows: