Title (de)

Title (fr)

Publication

Application

Priority

JP 9700325 W 19970207

Abstract (en)

There is disclosed a bus control device which reduces the data traffic amount of a parallel bus to enhance the performance of the bus control device. A local CPU (111) controls a serial bus transmission/reception controller (113) to give a transmission timing to a transmission interface (120). The bus transmission/reception controller (113) transmits to a serial bus a transmission frame formed by reading predetermined transmission data from a memory (112) storing addresses of a plurality of units (4) connected to the serial bus (51) and transmission/reception data to be transferred to the plurality of units. As a result, transmission/reception is performed with units connected to the serial bus (51) out of the plurality of units via the serial bus, the destination address and transmission data are read from the memory during transmission, and reception data is written to the memory during reception. <IMAGE>