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CS152 Lec15.13 Software Pipelining Observation: if iterations from loops are independent, then can get more ILP by taking instructions from different iterations Software pipelining: reorganizes loops so that each iteration is made from instructions chosen from different iterations of the original loop (­ Tomasulo in SW)

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CS152 Lec15.16 Can we use HW to get CPI closer to 1? Why in HW at run time? –Works when can’t know real dependence at compile time –Compiler simpler –Code for one machine runs well on another Key idea: Allow instructions behind stall to proceed: DIVDF0,F2,F4 ADDDF10,F0,F8 SUBDF12,F8,F14 Out-of-order execution => out-of-order completion. Disadvantages? –Complexity –Precise interrupts harder! (Talk about this next time)

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CS152 Lec15.17 Problems? How do we prevent WAR and WAW hazards? How do we deal with variable latency? –Forwarding for RAW hazards harder. RAW WAR

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CS152 Lec15.18 Summary Precise interrupts are easy to implement in a 5-stage pipeline: –Mark exception on pipeline state rather than acting on it –Handle exceptions at one place in pipeline (memory-stage/beginning of writeback) Loop unrolling  Multiple iterations of loop in software: –Amortizes loop overhead over several iterations –Gives more opportunity for scheduling around stalls Software Pipelining  take one instruction from each of several iterations of the loop –Software overlapping of loop iterations Very Long Instruction Word machines (VLIW)  Multiple operations coded in single, long instruction –Requires compiler to decide which ops can be done in parallel –Trace scheduling  find common path and schedule code as if branches didn’t exist (+ add “fixup code”)