Into the Itanium, Part 3

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Today on Dev Hardware, we're taking yet another look at the chip known as Itanium. We've covered the general history of the design, and the architecture from a programmer's view. Now it's time to get deep into the hardware itself.

With the removal of complicated performance enhancing hardware such as the out of order execution engine you might be tempted to believe that Itanium is simple from a hardware point of view. While peeking at it without looking too hard it does seem like a glorified playback device, simple it is not.

Just producing a die this large is no laughing matter. Itanium is a veritable mass of transistors. In terms of general physical size, there aren't any integrated circuits made bigger than the 410 million transistors and 374mm square die found on the "Madison" core with 6MB of cache. That is, until the coming of the mind blowing "9M" version, which is even larger still. Realistically, Intel is one of the very few companies worldwide with the manufacturing capabilities to even dream of pulling off such a feat, let alone actually accomplishing it with enough confidence to retail them in volume (or what passes for volume with respect to Itanium sales). It's a testament to their process technology that they can even create something this large.

One part that does not come easily, at least relative to the rest of the chip, is cache. While simulating and designing it in the first place (coherency, blocks, replacement, routing, etc) isn't the most trivial of tasks, reproducing scores of identical transistors over and over again is. Even when errors do occur, in cache they can be routed around, and a certain amount of duplication and "fudge factor" is built in to accommodate that. Itanium still doesn't make the cache part of the chip as easy as most desktop designs, because of both the sheer size and the addition of ECC (error checking code). One causes the global communication to be carefully accounted for, the other adds complexity in the form of more transistors.