In this laboratory you are requested to write a DMC8
assembly program that emulates a Universal Shift Register. A register of this kind can operate either in parallel or serial mode, depending on the mode inputs. In the following d-DcS schematic we use the Univ4 and Univ8 devices, available in the component library. The two components are connected together to obtain a 12-bits register. The operational mode of the register is controlled by a FSM-based sequencer; the mode changes when the STEP push-button is pressed (click on the figure to open the schematic in the editor).

Univ4 and Univ8 universal register mode setting depends on inputs S1 and S0, according to the following table:

S1

S0

Mode(all the described operations are synchronized by the clock rising edge)

0

0

Memo

Internal state and outputs unchanged

0

1

Right Shift Register

The register shifts its outputs one step to the right.
The previous right-most bit is lost, the left-most bit is loaded from the InR input

1

0

Left Shift Register

The register shifts its outputs one step to the left.
The previous left-most bit is lost, the right-most bit is loaded from the InL input

1

1

Parallel Register

The register loadsPn inputs into Qn outputs.

The controller functionality is described by the following ASM chart (click on the figure to open it in the d-FsM):

At the reset, the controller forces the parallel mode (S1='1', S0='1'): on the clock rising edge, the value of the inputs P11..P0 is loaded into the 12-bits register (Q11..Q0). By pressing and releasing the STEP push-button, the controller changes the register mode, in a cyclic order: right shift mode, memo mode, left shift mode, parallel mode, and so on.

In the schematic, Univ4 and Univ8 registers are connected in a circular mode. In the next figure, the serial data paths are highlighted, for the left and right shift cases:

When the register shifts to the left (path highlighted blue), the left-most Q3 bit of the Univ4 is fed back to the right-most bit of the Univ8 (through its InL input), while the Q7 output of the Univ8 is moved to the right-most bit of the Univ4. In a specular way, when the register shifts to the right (path highlighted red), the right-most output bits are used, connected through InR inputs.

You can test the circuit using the d-DcS simulator, in Animation Mode and in Timing Mode (a proper test sequence is available in the timing simulation window).

Open the "Test on FPGA" dialog window of the d-DcS. Note that all the needed associations between the d-DcS schematic and the FPGA board input/outputs are already set in the given schematic: it is not necessary to modify them. In the next figure the clock setup is highlighted.

Instead of 10 KHz, as during simulation, in this case the clock frequency is set to 10 Hz, to allow a visual control of the circuit behavior. The “Slow Clock Mode” has been enabled, assigning to the switch Sw[17] the task to activate it at runtime. It has been selected a LED, LEDR[17], to visualize the clock pulses being sent to the circuit. Finally, the pushbutton Key[03] has been chosen to control the manual generation of clock pulses. All defined associations are highlighted also in the next figure, useful for testing the physical system:

When finished, consider the new circuit, shown in the following figure, where the Univ8 has been substituted, pin by pin, by a microcomputer that emulates the Univ8 behavior (we left in place the original Univ4 register). You are asked to write a DMC8 assembly program that will emulate the Univ8 component (click on the figure to open the schematic in the d-DcS).

As described in the figure, we use the port IC to connect the P7..P0 lines, the port OA to generate the Q7..Q0 outputs, and the port IB for all the other input controls (S0, S1, CK, InR, InL). The microcomputer clock frequency is 10 MHz; to obtain a reasonable emulation of the register, its CK clock frequency needs to be much slower. So, in the proposed schematic the CK frequency is set to 10 KHz (the same used during the simulation of the previous circuit). We recommend to avoid any change on the schematic about the input/output terminations, which have been setup for the export on the FPGA board.

Click here to load a trace of a possible solution. When finished to write and test the program in the d-McE, you would load it in the microcomputer ROM. Than, simulate the circuit in the d-DcS, in Animation Mode and in Timing Mode (a proper test sequence, the same used for the previous circuit, is available in the timing simulation window).

Now we'll prototype this circuit on the FPGA board. Open the "Test on FPGA" dialog window. In the next figure the microcomputer clock and debugger setup is shown:

The microcomputer clock frequency is set to 10 MHz. The “Step by Step Mode” has been enabled, assigning to the switch Sw[16] the task to activate it at runtime. It has been selected a LED, LEDR[16], to visualize the clock pulses being sent to the microcomputer. Finally, the pushbutton Key[02] has been chosen to control the manual execution of the instructions. If Sw[16] is at '0', the debug system is not active and the microcomputer works with the "normal" clock (10 MHz). If Sw[16] is turned on at '1', the system stops the microcomputer clock generation and the debugger waits for the user to press Key[02] (each activation of the push-button executes one instruction).

Note that the microcomputer clock setup does not substitute the circuit clock setup, that continue to be set as in the previous circuit, since they are two separate definitions. So, also in this case, the circuit clock frequency has been set to 10 Hz (to allow a visual control of the circuit). As before, the “Slow Clock Mode” has been enabled, assigning to it the switch Sw[17], the LED LEDR[17] and the pushbutton Key[03] for the manual generation of circuit clock pulses.

We report in the next figure all the actual associations, useful for testing the physical system: