VERILOG PACKET INTERFACE Product MODULE TO INTERFACE IDT Brief HIGH PERFORMANCE NSE TO 75HKD0X2100A01 75HKD0X2100A01 ALTERA FPGA Introduction Background IDT provides proven, industry-leading network search engines (NSEs) and a comprehensive suite of software that enable and accelerate the intelligent processing of network services in communications equipment. As a part of the complete IDT classification subsystem that includes content inspection engines, the IDT family of NSEs delivers highperformance, feature-rich, easy-to-use, integrated search accelerators. To further accelerate time to market, IDT provides a Verilog Packet Interface Module (PIM) that can be integrated within a user's Altera FPGA. It has been designed to interface with an IDT High Performance NSE device (75P42100 75P42100, 75P52100 75P52100, 75K62100 75K62100, and 75K72100 75K72100) and the user's Verilog code through a simple packet-based interface. Two interfaces are defined between the PIM and the user's logic within the FPGA: 1. Control Packet Interface 2. Search Interface DO N OT Control Packet Interface The Control Packet Interface is used for Control Plane functions. It interfaces the PIM with the user's Packet Decode/Encode block (see Figure 2). The control plane functions (management, diagnostic, and test software) use this interface when communicating with the NSE device or the PIM. The Control Packet Interface is further divided into two interfaces ­ the TX Control Packet Interface (ingress path into the NSE device and PIM) and the RX Control Packet Interface (egress path out of the NSE device and PIM). Figure 1.0 PIM Top-Level Block Diagram Packet Interface Module (PIM) Tx Control Packet Interface The Search Interface is the primary path for the user's Data Plane code to request searches to be performed by the NSE device to accelerate the identification of each packet received on the line interface. It is located between the PIM and the user's Search Key Formation block and the user's Search Results block (see Figure 2). The Search Key Formation block creates the search key from each incoming packet. The output of this block is the ingress path into the NSE device via the PIM. After performing the table lookup, the NSE returns the result through the Search Results interface. The Search Results block is the egress path from the NSE device (via the PIM) that receives the result information about the type of packet being processed. The returned result, which can be in the form of an index or associated data, is used by the user's data plane code to further process the received packet. Control Packet Interface Rx Control Packet Interface NSE DU PL IC AT E Search Interface CAM Interface Search Key Interface Search Interface Search Results Interface 6463d00 1 MAY 2004 Copyright Integrated Device Technology, Inc. (IDT) All rights reserved. This document contains information that is proprietary to IDT Inc. Use, transfer, or other duplication without the expressed written consent of IDT, Inc. is strictly prohibited. DSC-6463/00 DSC-6463/00 IDT75HKD0X2100A01 IDT75HKD0X2100A01 Verilog Packet Interface Module to Interface IDT High Performance NSE to Altera FPGA Product Brief Figure 2.0 FPGA Block Diagram Altera FPGA Packet Interface Module (PIM) Tx Control Packet Interface Rx Control Packet Interface IDT NSE DO Packet Decode/ Encode Control Packet Interface Control Packets RX MAC Control Plane Processor TX User's Control Plane Code CAM Interface N OT Search Key Interface Search Key Formation Search Interface Search Results Interface Line Interface User's Data Plane Code Search Results DU PL IC AT E Packet Processing Code 6463d01 Available Technical Documentation Verilog Packet Interface Module for IDT NSE - User Guide (IDT P/N: 60-0044-02) Verilog Packet Interface Module for IDT NSE ­ Getting Started Guide (IDT P/N: 60-0043-02) 2 COMPANY CONFIDENTIAL Line Interface