EDA Tools in Custom IC Design Services

PDK Development Service Deliverables

Schematic Symbols – for the Gateway Schematic Editor to invoke Parameterized Cells in the Expert Layout design tool that are DRC and LVS correct. These parameterized symbols and respective subcircuits are integrated and tested with the SPICE models to assure a standard convention for transistor level simulation. PCells are written in the JavaScript/Lisa Scripting Language.

SPICE Models – SPICE model (optional) files, verified with the SmartSpice Circuit Simulator, at the foundry-supplied process corners (temperature, voltage, process). Silvaco will extract one set of models from a wafer or measured data and produce a complete measured vs. simulation report for each device.

Technology Files – layer files that correlate the legal GDSII layers for each of the process layers for layout and verification tools. Display files to customize the layout and schematic tools for GDS layers, display colors and user-customizable hot keys.

Rule Decks –contain the layout rules encoded into the format used by the Expert Layout Editor, Guardian DRC /LVS/LPE tools, and the Hipex Full-chip Parasitic Extractor.