Banks

CPU $8000-$BFFF: 16 KB PRG ROM bank, either switchable or fixed to the first bank

CPU $C000-$FFFF: 16 KB PRG ROM bank, either fixed to the last bank or switchable

PPU $0000-$0FFF: 4 KB switchable CHR bank

PPU $1000-$1FFF: 4 KB switchable CHR bank

Through writes to the MMC1 control register, it is possible for the program to swap the fixed and switchable PRG ROM banks or to set up 32 KB PRG bankswitching (like BNROM), but most games use the default setup, which is similar to that of UxROM.

Registers

Unlike almost all other mappers, the MMC1 is configured through a serial port in order to reduce pin count. CPU $8000-$FFFF is connected to a common shift register.
Writing a value with bit 7 set ($80 through $FF) to any address in $8000-$FFFF clears the shift register to its initial state.
To change a register's value, the CPU writes five times with bit 7 clear and a bit of the desired value in bit 0.
On the first four writes, the MMC1 shifts bit 0 into a shift register.
On the fifth write, the MMC1 copies bit 0 and the shift register contents into an internal register selected by bits 14 and 13 of the address, and then it clears the shift register.
Only on the fifth write does the address matter, and even then, only bits 14 and 13 of the address matter because the mapper registers are incompletely decoded like the PPU registers. After the fifth write, the shift register is cleared automatically, so a write to the shift register with bit 7 on to reset it is not needed.

When the CPU writes to the serial port on consecutive cycles, the MMC1 ignores all writes but the first.
This happens when the 6502 executes read-modify-write (RMW) instructions, such as DEC and ROR, by writing back the old value and then writing the new value on the next cycle. At least Bill & Ted's Excellent Adventure resets the MMC1 by doing INC on a ROM location containing $FF; the MMC1 sees the $FF written back and ignores the $00 written on the next cycle.[1] The reason for this is that the MMC1 has explicit logic to disregard any write cycle following another write cycle. The location of the writes is not relevant, for example even a write to $8000 happening one cycle after a write to $7fff will be ignored by the MMC1, in practice such a thing cannot be made with a 6502 processor.[2]

To switch a bank, a program will execute code similar to the following:

CHR bank 0 (internal, $A000-$BFFF)

MMC1 can do CHR banking in 4KB chunks. Known carts with CHR RAM have 8 KiB, so that makes 2 banks. RAM vs ROM doesn't make any difference for address lines. For carts with 8 KiB of CHR (be it ROM or RAM), MMC1 follows the common behavior of using only the low-order bits: the bank number is in effect ANDed with 1.

Boards using an MMC1 may contain a battery connected to the PRG RAM's power line to preserve the data.
Boards doing so will allow extra circuitry to be used, with 2 diodes and 2 resistors.
A diode is needed from both voltage sources: The battery and the NES 5V, so that one cannot supply current to the other, and there is a resistor in series with the battery so that no current is drained from the battery when 5V is present. A pull-down resistor is needed on the CE line so that the SRAM is disabled when the MMC1 isn't powered. Finally, the battery powered SRAMs have an additional larger decoupling capacitor to make sure voltage transitions are smooth. Very early NES-SNROM-03 and lower revisions lacks that capcity, and saves are lost much more easily on those boards.

Nintendo transitioned from the original MMC1 (manufactured by ROHM) to the MMC1A (manufactured probably by Ricoh) around the 39th week of 1988. (Based on comparison of otherwise identical SMB/DH/WCTM carts from 38th and 39th weeks of '88)

Variants

Because the higher CHR lines aren't used when the MMC1 mapper is used with a 8KB CHR RAM, those lines are sometimes put to other uses depending on the board :

CHR bank 1 (internal, $C000-$DFFF)

Both the E bit and the R bit (in standard MMC1 registers) should be clear in order for the PRG RAM to be writable or readable. This bit is more "reliable" on authentic hardware as it is implemented even in older boards with older MMC1's, while the R bit was only introduced later.
But because the E bit wasn't confirmed by the homebrew community until October 2010[3], emulators tend not to implement it.

The SOROM board only implements the upper S bit, while the SUROM board only implements the P bit. For SXROM, the upper S (bit 3) selects the SRAM's A14, and the lower S (bit 2) selects A13[4].

The 256 KB PRG bank selection applies to all the PRG area, including the supposedly "fixed" bank.

In 4KB CHR bank mode, SNROM's E bit and SO/U/XROM's P and S bits in both CHR bank registers must be set to the same values, or the PRG ROM and/or RAM will be bankswitched/enabled as the PPU renders, in a similar fashion as MMC3's scanline counter. As there is not much of a reason to use 4 KB bankswitching with CHR RAM, it is wise for programs to just set 8 KB bankswitching mode in the Control register.

iNES Mapper 001

iNES Mapper 001 is used to designate the SxROM boardset, all of which use Nintendo's MMC1.

The E bit also acts as a PRG RAM disable for SNROM (PRG ROM <= 256k, CHR RAM = 8k, PRG RAM = 8k), though this is merely for write protection and not strictly required for compatible emulation.

The D and C lines are swapped for SXROM (32k PRG RAM) here; the D line actually selects the upper SRAM address line, though this reversal might be irrelevant to an emulator's implementation.

NES 2.0 is required to specify PRG-RAM size. Without NES 2.0 the PRG-RAM size has to be assumed (32k may be sufficient for compatibility).

Boards designed for 32k PRG-ROM (SEROM, SHROM, and SH1ROM) do not connect PRG A14 to the MMC1, disabling PRG banking. For compatibility with these, the emulator may switch to PRG bank 0 at power-on. SIROM supports banked 32k PRG, however.