Each DAC is matched to an FPGA, leaving the third FPGA available for additional channel processing or system control functions. Through a combination of hardware and firmware, Tekmicro has achieved sample-accurate synchronization for multiple channels across an entire chassis. The sample accurate synchronization provides unprecedented accuracy for multi-channel signal generation applications such as threat simulation or beam steering.

The two analog output channels and three Xilinx Virtex-5 FPGAs deliver up to 2,336 DSP slices and 1.3 TeraMAC/s of signal processing.

The Triton-V5 is available for a wide range of operating environments including commercial grade, rugged air, and conduction cooled to support deployed applications such as unmanned airborne, naval and ground vehicles. For more details see Tekmicro’s Rugged Data Sheet.

In addition to Orion-V5, Tekmicro offers a broad range of Xilinx Virtex-5 based streaming I/O and FPGA processing solutions for both analog and digital I/O in a range of form factors. For example, Orion-V5 paired with our 2.2 GSPS dual channel ADC Neptune-V5 board offers developers unique solutions.

Two Channels: Two 12-bit DACs Output at up to 4.0 GSPS Each

First COTS Product to Achieve This Level of Performance.

Sample Accurate Synchronization Across Multiple Boards.

Enables Solutions for New Multi-channel Applications

Phase-matched DAC Outputs

Waveform Generation

Six Digital IO Channels Running at Up to 3.75 Gb/s Using One QSFP and Two SFP+ Front Panel Connections

Flexible Data Movement Across the Front Panel For Use in Standard VME64 Environments

DAC

Each of the two channels of up to 3.0 GSPS, 12-bit resolution digital to analog conversion use the non-interpolating Euvis MD653D which has a bandwidth of 4 GHz.

The output is AC coupled and may be single-ended or differential (factory build option). The full scale output is -4 dBm (0.4V p-p) into 50 ohms. The DAC may be operated in normal-hold mode, or for extended operation into the 2nd Nyquist band, in Return to Zero (RZ) mode.

Virtex-5 FPGAs

Xilinx Virtex-5 FPGAs are the heart of the Orion-V5. The FPGAs interface between the DAC’s, memory and I/O resources to provide a platform for implementing high performance real time processing. The Orion-V5 is configured with two SX95T FPGAs and one LX110T FPGA. An LX220T, SX240T, or FX100T FPGA can be selected to match resources to the application. All FPGAs are interconnected by wide parallel LVDS busses and also via high speed serial links using the Xilinx Rocket IO MGTs.

Front Panel High Speed Serial IO

Two SFP+ sites and one QSFP site are provided on the front panel which utilize standard fiber optic or 1000BaseT modules providing physical layer support for standard protocols such as Gigabit Ethernet, Serial FPDP (ANSI VITA 17.1 & 17.2), and Fibre Channel.

VXS Backplane High Speed Serial IO

The Orion-V5 can be used as a VITA 41.0 payload card. Up to eight high speed serial links of up to 3.125 Gb/s full duplex data rates are supported via VITA 41.0 MultiGig RT2 P0 connector. Custom or standard communication protocols can be run over these links by providing appropriate firmware in the FPGA.

QuiXstart FPGA Configuration

A number of options are available for configuring the FPGA on the Orion-V5. A JTAG connection is available to allow users to configure the FPGA via standard Xilinx development tools. On board flash is available and can configure the FPGA on power up. Tekmicro’s QuiXstart tool supports flexible configuration of the FPGA through a Gigabit Ethernet link from a remote server after a power up or reset event

Trigger

Trigger input connections are provided on the front panel to allow the hardware to be employed in a variety of radar and EW scenarios. The trigger input is LVDS (LVPECL is a factory build option). The DACs may use independent front panel triggers, or may use a single trigger source for synchronization of the two channels. Multiple Orion-V5 boards may be synchronized using the trigger input.

Clock

The DACs are clocked from separate or combined clock inputs (factory build option). The minimum input clock level is 6.0 dBm into 50 ohms. When using a single, combined clock, the two DACs receive a phase-aligned clock.

Memory

The Orion-V5 has two independent banks of on board double data rate (DDR3) SDRAM for each FPGA, providing a capacity of 512 MB in each bank, 1 GB total per FPGA. The on board memory can be clocked at rates up to 400 MHz, 800 MHz double data rate.

System Monitoring

The Orion-V5 board includes facilities to monitor current and temperature at various points on the board. Current monitoring of all main power rails is available. Die temperature monitoring of the three FPGAs and temperature monitoring of three locations on the PCB is also available. This allows a first level of protection when the Orion-V5 is operating in different environmental scenarios. The output from the sensors is available to users’ FPGA firmware applications, to allow the user application to adapt to changes in environmental conditions. The Orion-V5 also uses the system monitoring sensors to implement a system protection mechanism which will, independently of the users’ application, prevent excessive current or temperature from damaging the board.