Yeah so far I have seen mostly concerns with increased leakage and the presence of floating nodes in these capacitor-less DRAMs. It would be interesting to see if non-volatility becomes a requirement or at least a target.

Resistion:- Your support for SIO-DRAM or Thyristor as one of the potential DRAM replacements is interesting; the key question is will it be possible for another volatile memory to be the successor to DRAM or will non-volatility be mandatory. If the need for stand-by power dissipation is acceptable would for example the factor of 10 reduction claimed by Kilopass on a like-for-like basis for their thyristor stack be enough to win the game.I think there might be a possible scaling problem with the thyristor. In the stacked structure* the length of the edges of the pnpn junctions directly in contact with oxide, reducing its quality, does not scale linearly with area. Which I think might mean the leakage will increase with scaling. I doubt if that possibility would show up on first order simulations.

MRAM is currently actually STT-MRAM as you point out; it is pretty much only dependent on the current to drive the spin flips over the barrier. So a higher current will give higher performance (speed, lower write error). If this is ok in the product design, it should work. It might be a large footprint consequently, and that's another reason it sort of naturally fits between DRAM and SRAM. It would be interesting to compare the STT-MRAM cache versus the e-DRAM cache, for example.

MRAM has been an impressively evolving field, so I would look forward to the next phase after STT (SOT or magnetoelectric?).

The 3D NAND architecture is much denser than XPoint, so the XPoint is only worth it if it is faster than the NAND flash, which it is expected to be. It would also be better if emerging memories can port over to the 3D NAND style architecture.

It is possible that the real threats to emerging memories come from "silicon-only" memories such as floating body DRAMs (SOI or thyristor type) or the transistor-only flash gate. The reason is of course, their entry barrier is much lower than others where new materials need to be incorporated. Of course, we know, flash is too slow and floating body is scary to many designers and also has more chance of leakage to substrate.

As I recall reading years ago, silicon-only CMOS synapse elements are also possible.

Hahaha, I don't know if I would consider MRAM to be in its infancy. It has definitely seen its share of sensationalism and disillusionment over the years, though perpendicular STT MRAM does actually seem to have hope.

I happen to be a really large proponent of MRAM, though I am not so optimistic about it breaking through in the SCM market (I assume SCM is somewhere between DRAM memory and Flash storage in terms of speed/density/cost). The densest STT-MRAM design I have seen still uses a 1T1MTJ cell design which doesn't give it a significant advantage over existing DRAM. The MTJ of MRAM uses a stack of many different metals/materials of which the thickness, interface quality can have drastic effects on the magnetic and device properties. These fairly strict structural requirements of an MTJ make me think that it MTJ cells may be limited to a 2D planar array which doesn't make it competitive in terms of density when comparing to what density 3D VNAND can achieve with fewer materials but allowing for a more complex structure. Having said all that though, I still do believe that MRAM's significant speed/nonvolatility over DRAM and greater density over SRAM can make a breakthrough in embedded memory and possibly standalone memory.

I am probably wrong about the diode and PCM in 3Dxpoint so I will acquiesce to your point on that one. However 3D xpoint has another fairly large challenge in my opinion. To get that memory cell sandwiched between criss cross bit/word line wires would probably require a lithography step for every single layer. 64 layers of memory cells sandwiched between 65 layers of criss cross wires would require 129 lithography steps. Lithography is extremely time consuming and expensive to perform. In contrast, to get an equivalent 64 layers of flash cells in 3DVNAND would require 64 alternating CVD depositions of Ox/Poly Si, followed by 1 lithography/hard mask formation, a hole etch and a final insertion of the charge trap layer/floating gate, channel and erase gate by ALD (probably). Adding more layers to 3DVNAND would require overcoming the technical challenge of getting a good high aspect ratio hole etch, but at least it wouldn't require more lithography steps which is a huge time saver (and no where in the world is it more apparent than in a semiconductor fab that time is money). From what I can see now, more layers in 3D xpoint means more lithography which means the time to make it doesn't scale well with trying to increase its density (adding more layers).

Thank you for your discussion and I will point out that I am just one engineer so it is not impossible that my opinions are partially biased or wrong.

I doubt the universal memory; if the data is to be moved easily, it can't be trapped or stored easily. MRAM is more suited for moving the data frequently as in cache, not so much for nonvolatile storage. To target nonvolatility, an MRAM cell would be too big and power-consuming due to the need for a large current to take data "out of storage" so to speak.

Shinobee and Resistion;- I am not comparing MRAM and PCM I am merely expressing an opinion as to which technology is more likely to become the memory of choice for SCM applications. Taking into account MRAM is still in its infancy compared with the 50 or so years of PCM development. So far PCM has little to show for those 50 years other than a list of failed products without any significant design wins. My real point was I think there might be a new direction for PCM/ReRAM in a brain-gate role, where they have properties and characteristics which make them ideally suited. Where even some of the normally undesirable characteristics, randomness, drift etc might allow them to used not just in cognitive and learning roles but in creative machines.

Your own and Resistion's comment here below, appear to suggesting MRAM as a cache, or DRAM replacement or as an embedded memory would appear to be support for MRAM in a universal memory role not just SCM.

Until we have more clarity on 3DXpoint ™ it is difficult to make a comment on the its likelihood of success. So far it is some clever lithography, packaging exercises, computer architects dreams and a good dose of hype. I think Optane ™ has to be considered as not uniquely linked to PCM as the memory element.

You mentioned in your comment the matrix isolation device as a diode for PCM and, vis-a-vis the ReRAM, the merit of the operation of a PCM as a unidirectional component. In the stacked 3DXPoint ™ structure as far as we know the matrix isolation device is not a diode it is a bi-directional threshold switch. Which means it would not be too difficult to employ a memory element requiring bi-directional write/erase current. In the 3DXpoint ™ saga any claims for the development of a highly reliable threshold switch matrix isolation device are as important as those for the memory device. The matrix isolation device will need to a level of reliability which will make it capable of switching on every read cycle, not just write/erase.Without disclosing any secrets we have at EETimes an inter-office generated list of 3DXPoint ™ questions which do not require propriety information and if answered would allow us to offer you a better gauge of the likely success of that endeavour. Some of those questions focus on the mechanism of the matrix isolation device.

It also pets me the wrong way when people compare MRAM to PCRAM and RRAM.

I am also thinking that MRAM could be best suited towards some kind of L3 cache memory. The read/write time (while slower) is comparable to SRAM but offers much higher density. I think Samsung is probably the closest to putting out any kind of MRAM device. IIRC they are currently focused on using MRAM as an embedded memory, not standalone like DRAM.

I have no hard evidence of this but I was also led to believe that 3D Xpoint uses PCM (or some variation of it). This is because there needs to be a diode on the memory cell sandwiched between the criss cross wires to limit the current going top to bottom only, otherwise the sneak current path problem will occur. Only PCM can function with unidirectional currents; RRAM and MRAM require bi-directional currents to write/erase.

It will, however, be difficult to arrive at the conclusions of the article for the current generation of engineers.

They will still be trying to employ the technology under the premises of an education which sets apart the storage and the processing of information in the way that von Neumann archtiectures require. As well, the current set of corporations based on the current technology will not be able to agree that their products and accumulated know-how will become outdated quickly.

We will need a completely new generation of engineers for this technology in order to fully grasp its potential. In the meantime, we will see the advent of hybrid approaches, where "classically programmed" devices will interact with the devices outlined in the article, just like the different types of "Brain" we see in their biological counterparts:-).