Intel previews server and Thunderbolt chips

SAN JOSE, Calif. Ė Intel will refresh its line of server processors this year, adding three Atom-based chips to the mix. At its annual event in Beijing this week, the company will reveal a few details of the chips and its work defining a reference design for server racks that includes its silicon photonics.

Separately, Intel and Pericom talked about new chips for Thunderbolt, a fast peripheral interface initially defined by Intel and used in Apple Macs.

In Beijing, Intel announced two Atom-based SoCs -- Briarwood for storage systems and Rangely for networking. Briarwood, aka the Atom S12x9, is a 32-nm part that is shipping now and supports up to 40 PCI Express Gen 2 lanes, non-transparent bridging and hardware acceleration for RAID.

Intel would only say Rangely is a 22-nm SoC that will ship in the second half of 2013. At the Beijing event, Intel showed a working demo of Avoton, itís 22-nm Atom SoC for microservers. Both Rangely and Avoton use a new Atom core called Silvermont, expected to support out-of-order execution.

As for its Xeon server chips, Intel announced it will ship in the middle of this year a 22-nm E3-class Xeon for low-end single-socket servers. The chip is part of its Haswell generation and consumes just 13 W, down from 17 W for its current lowest power Xeon today.

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Intel claims its 2013 Atom and Xeon chips will span the server waterfront.

The Haswell Xeon will include embedded graphics. Intel will roll a developerís kit for running video streaming applications using the graphics core on the processor.

In its middle market E5-class, Intel will ship in the third quarter a 22-nm Ivy Bridge EP chip for dual-socket systems. By the end of the year, it will ship Ivy Bridge EX processors for systems with eight or more processors, presumably made in its 32-nm process. They will handle up to 12 terabytes of DRAM in an eight-socket node.

Separately, Intel said it is working on a reference architecture for a rack-level server design that it will publish in 2014. The architecture will specify the silicon photonics interconnects Intel announced last year, at least as one design option.

Last year, Intel worked with Chinaís Alibaba, Baidu, Ten Cent and China Mobile on Project Scorpio, a custom rack design. Intelís Beijing office is also developing its own cloud computing system it will let China customers access.

The lowest TDP Sandy bridge and corresponding performance is about same as lowest TDP of haswell and its corresponding performance. It can be found in published data that the 22 nm finfet transition took more of a performance hit in order to reduce power.

The current one is 17W. The new one is down to 13W. More interesting will be the E5 10 core chips at 70W. It will be possible to get 4 of these in a 1U chassis. That's 40 2.5+ GHz cores, 80 hyper-threads, with at least Ivy Bridge performance levels, and at least half a TB of DRAM in a 1U. It is interesting. It is not clear to me that the ARM and Atom server chips will win here. Better performance per Watt is important, but only as long as it can maintain the same or better performance per volume unit. If a 2U space of ARM or Atom chips is needed to run as many VMs as a 1U of E5s, then which really costs less?

It is interesting that the new E3 power ranges from 17W, 45W to 87W. They must be really hand-picking the 17W parts because the true power seems to be in the 60W range. Wonder how much yield they can get for the low power part.