On Monday, Intel introduced its Many Integrated Core (MIC) architecture for massively parallel processors, which is scheduled to first appear in the upcoming Knights Ferry and Knights Corner platforms.

The Knights Ferry chip, code-named Aubrey Isle, is a 32-core derivative of Larrabee. Each core on the die shot (above) is a vertical strip with a white blob halfway up its right-hand side. The remainder of the chip is cache, interface and control logic. With Intel's ability to run a subset of cores at faster than normal speeds if the thermal envelope allows, even chips with one or two faulty cores could produce high performance.

Published: June 1, 2010 -- 14:11 GMT (07:11 PDT)

Photo by: Intel

Caption by: Rupert Goodwins

Intel's Kirk Skaugen holds up a 22nm wafer. Due in 2011 and 2012, the next two waves of processor design will be in this new process. That leaves just five or six more iterations of shrinking until, at around 7nm, physics says that silicon cannot support anything smaller.

Published: June 1, 2010 -- 14:11 GMT (07:11 PDT)

Photo by: Intel

Caption by: Rupert Goodwins

The first Knights product is Knights Ferry. At its heart is the Aubrey Isle chip, which is packaged as a co-processor in a PCIe card. With 32 cores running four threads apiece, this can process 128 threads at 1.2GHz. This is the hardware being evaluated in Cern; it will never be a commercial product.

Published: June 1, 2010 -- 14:11 GMT (07:11 PDT)

Photo by: Intel

Caption by: Rupert Goodwins

Intel is at pains to demonstrate that programming the MIC architecture will be via a natural extension of its mainstream x86/x64 development tools. This diagram emphasises the co-processor nature of MIC. The system reflects aspects of traditional mainframe design where control and management takes place in a separate system to the main computational mill.

Published: June 1, 2010 -- 14:11 GMT (07:11 PDT)

Photo by: Intel

Caption by: Rupert Goodwins

This is Knights Ferry, demonstrating the relationship between the way the cores talk to each other and the way they talk to the cache. A very close merging of those two functions is essential to let the cores run at speed without waiting too long for data or other cores.

Published: June 1, 2010 -- 14:11 GMT (07:11 PDT)

Photo by: Intel

Caption by: Rupert Goodwins

As the deadline for silicon's ability to shrink approaches, Intel is being more open about what happens next. In particular, carbon nanotubes show future promise: they produce high performance devices, and look good for high-volume, low-cost fabrication.

A close-up on Intel's Knights Ferry platform

The Many Integrated Core architecture will be used in the new Knights Ferry and Knights Corner platforms, aimed at supercomputing tasks

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On Monday, Intel introduced its Many Integrated Core (MIC) architecture for massively parallel processors, which is scheduled to first appear in the upcoming Knights Ferry and Knights Corner platforms.

The Knights Ferry chip, code-named Aubrey Isle, is a 32-core derivative of Larrabee. Each core on the die shot (above) is a vertical strip with a white blob halfway up its right-hand side. The remainder of the chip is cache, interface and control logic. With Intel's ability to run a subset of cores at faster than normal speeds if the thermal envelope allows, even chips with one or two faulty cores could produce high performance.