The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.

A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.

Course Description

This is an Engineer Explorer course which covers advanced topics that are not suitable for beginners. The course is the next level after the Specman® for Block-Level Environment Developers course. This course covers the more advanced e language and Incisive® Specman tool features.

The advanced e language and Specman features are described in the wider context of scaling and reusing verification environments from the block level through large system-level environments. These environments are typically constructed from many different languages, such as e, SystemVerilog, and SystemC. This course follows and describes the recommendations of the Cadence® UVM e methodology. The course provides essential hands-on experience, with a 50-50 combination of lecture and labs.

The course covers a variety of advanced topics including:

Comprehensive functional coverage

Module-to-system reuse

Macros

Automated checking concepts and features

UVM Multi-language Open Architecture library

Reflection API for the e language

Specman Memory Analysis

Advanced sequences

Register and memory modeling

Optimizing regression times using the Specman Advanced Option (SAO)

Learning Objectives

After completing this course, you will be able to:

Scale verification environments from a block to the system level

Maximize reuse of your verification environments

Use the UVM Multi-language Open Architecture library to achieve multi-language communication, synchronization and configuration

Implement and manipulate virtual and layered sequences

Implement Advanced sequence use models using the UVM-e sequence API

Extend the e language with macros

Utilize the powerful combination of Reflection and Macros

Optimize for performance and productivity

Implement an instance based coverage model and using a combination of procedural code and coverage

Model registers and memories effectively using the vr_ad package

Software Used in This Course

Incisive Enterprise Simulator

Software Release(s)

INCISIVE 15.1

Modules in this Course

Reference models

Interfacing to other languages with UVM e TLM connections

Defining and extendingetemplate types

Comprehensive Instance Based Functional Coverage

Specman Memory Analysis – Understanding how Specman uses memory and how to optimally configure that

Reflection facility – Introspection in the e language and its application

Efficient use models for the Specman tool (optimizing performance and productivity with SAO)

"The advanced course touched some high end topics which contributed to my work. (...) These topics were not in my everyday use and I intend to use them more thoroughly. This course can contribute even to the expert user."

Yagel Mishni, Ceragon Networks

"An enjoyable training course!"

Gabriel Duffy, STMicroelectronics

"Worth going to. The teacher was very competent and capable to understand the questions and needs that sometimes have been asked in a very fuzzy way."

Michael Sommer, Infineon Technologies

"I liked the time that I spent in the course. It was useful although not all topics were new to me. The instructor was very nice, I liked his way of presenting."

Sandra Schuetz, Bosch Sensortec

"A lot of energy spent by the instructor to help us understanding the training.Always available and always ready to change the way to explain for our understanding."

Yanick Paviot, STMicroelectronics

"I had a very good experience in this course, it exceeded my expectations(...)enriching and interesting."