tag:blogger.com,1999:blog-4597498589834570435.post1214005786851276612..comments2020-06-05T17:08:30.171+05:30Comments on VLSI Concepts: 10 Ways to fix SETUP and HOLD violation: Static Timing Analysis (STA) Basic (Part-8)VLSI Experthttp://www.blogger.com/profile/01205530113106138349noreply@blogger.comBlogger40125tag:blogger.com,1999:blog-4597498589834570435.post-8840825500463203122019-11-02T14:00:29.291+05:302019-11-02T14:00:29.291+05:30Please explain me about hold analysis...and how ex...Please explain me about hold analysis...and how exactly the uncertainty effect the timing analysisAnonymoushttps://www.blogger.com/profile/01462459911244366373noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-81840881434616078582019-09-06T11:20:28.991+05:302019-09-06T11:20:28.991+05:30Thanks expert !! For clear explanation for setup a...Thanks expert !! For clear explanation for setup and hold fixing<br />if we decrease the supply voltage, delay will increase<br />why we dump chip after fabrication for hold violation??Aravind SShttps://www.blogger.com/profile/06935017758287436321noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-9084670856555517052019-09-06T11:18:14.559+05:302019-09-06T11:18:14.559+05:30Thanks expert !! For clear explanation for solving...Thanks expert !! For clear explanation for solving setup and hold violation.<br />if the supply voltage reduces delay will increase and hold violation clear.<br />so why we can dump chip after fabrication?? Aravind SShttps://www.blogger.com/profile/06935017758287436321noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-30018611832286877242018-10-23T01:15:33.042+05:302018-10-23T01:15:33.042+05:30It looks like all the methods described here are f...It looks like all the methods described here are for fixing setup and hold violations during the backend stage (placement and routing) of the design. Methods like buffering in a path, inserting repeaters, HVT swap, driver size adjustment, cell position adjustment all comes in backend only. What are the possible solutions to setup and hold violations in early stage of the design, say during RTL Bijeshhttps://www.blogger.com/profile/14747161141059408114noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-20632737683781303232018-02-09T19:03:01.097+05:302018-02-09T19:03:01.097+05:30Thanks,,. will tool(cadence encounter) take cares ...Thanks,,. will tool(cadence encounter) take cares above steps in its algorithm else we have to specify at each stage??<br />If yes help me with the commands for various steps you mentioned above .<br />Thank youAnonymousnoreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-78476095689438170812017-11-23T13:12:34.232+05:302017-11-23T13:12:34.232+05:30Can we Change the setup and hold violations after ...Can we Change the setup and hold violations after the chip is manufactured?Anonymoushttps://www.blogger.com/profile/07141591030046233474noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-72572682355187040592017-11-16T11:58:49.295+05:302017-11-16T11:58:49.295+05:30wat is the relation between violations and crossta...wat is the relation between violations and crosstalk.and also how do v relate delay with crosstalk<br />SRIDEVIhttps://www.blogger.com/profile/16637093756382217971noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-30268146174668774222017-11-13T09:07:24.370+05:302017-11-13T09:07:24.370+05:30So stage delay (cell delay + wire delay) in case o...So stage delay (cell delay + wire delay) in case of single buffer &lt; stage delay in case of 2 inverter in the same path. I think here stage delay of buffer is &gt; stage delay of 2inverters...also can you please explain why transition time of inverter is low..thank youAnonymousnoreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-46107001451360411682017-10-11T13:57:13.941+05:302017-10-11T13:57:13.941+05:30hi expert
what about pipeline technique?
if the ti...hi expert<br />what about pipeline technique?<br />if the timing is not meeting b/wn two flops by regular methods .we can insert flop to meet timing is it correct or not? please reply meAnonymousnoreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-48890274843477502262017-05-31T17:33:49.076+05:302017-05-31T17:33:49.076+05:30Hi,
I am using Vivado design suite from Xilinx. A...Hi,<br /><br />I am using Vivado design suite from Xilinx. After synthesis, in timing summary, I got a some setup time violations. There was an option to maximize the delay from start point to end point. After following that step, the setup time violation issue was solved.<br /><br />The above condition contradicts the fact that &quot;decreasing the delay&quot; fixes the setup time violation. Srinivasannoreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-73048024839505289982016-08-27T22:03:58.528+05:302016-08-27T22:03:58.528+05:30Is it possible to fix the hold violation of a manu...Is it possible to fix the hold violation of a manufactured chip by tweaking operating condition, e.g., decreasing supply voltage or increasing temperature?pramhttps://www.blogger.com/profile/07062894828810634504noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-12718448245918948262016-06-20T11:33:12.919+05:302016-06-20T11:33:12.919+05:30You are right .. If you will add more buffer , it ...You are right .. If you will add more buffer , it will increase the delay. There are lot of ways to find the optimum number of buffers. Basically there are algorithm for that. but this post is just to provide a insight about the methods which can help you in the field or during design. <br />Other Algorithm I will try to cover in some other post. VLSI Experthttps://www.blogger.com/profile/01205530113106138349noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-65905996851331603782016-06-20T01:00:51.600+05:302016-06-20T01:00:51.600+05:30If there is a long wire between cells then adding ...If there is a long wire between cells then adding buffers will reduces the delay through decrease in transition time. So, my question is, how is optimum number of buffers are determined? I hope adding in more numbers will increase delay than reducing it!! Adarshhttps://www.blogger.com/profile/10490164198370196478noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-88626192196050667322016-06-19T10:09:30.903+05:302016-06-19T10:09:30.903+05:30Thanks a lot for information...............Thanks a lot for information...............Anonymoushttps://www.blogger.com/profile/17283874110351423109noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-28749550027430082302016-05-26T12:18:13.982+05:302016-05-26T12:18:13.982+05:30Hi, thanks for the reply.. I read through the blog...Hi, thanks for the reply.. I read through the blogs; still I think there is a dependence ie If I reduce the combinational path delay to a very low value (~0) then there would be hold violation; hence &quot;max freq period&quot; = Tsetup + Tcombdelay. Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-60449648706298157362016-04-18T08:59:53.150+05:302016-04-18T08:59:53.150+05:30links are:
Advance Setup and Hold Check
Advance...links are:<br /><br /><a href="http://www.vlsi-expert.com/2016/02/setup-and-hold-check.html" rel="nofollow"> Advance Setup and Hold Check</a><br /><a href="http://www.vlsi-expert.com/2016/02/setup-and-hold-violation.html" rel="nofollow"> Advance Setup and Hold Violation </a><br />VLSI Experthttps://www.blogger.com/profile/01205530113106138349noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-10896835219597853622016-04-18T08:54:55.175+05:302016-04-18T08:54:55.175+05:30I can reply you .. but best is you check these 2 A...I can reply you .. but best is you check these 2 Articles<br /><br />http://www.vlsi-expert.com/2016/02/setup-and-hold-check.html<br />http://www.vlsi-expert.com/2016/02/setup-and-hold-violation.html<br /><br />At the end of these 2, I am sure you can yourself figure out whether it has dependency or not. If Not - Ping me again - I will explain you.<br />VLSI Experthttps://www.blogger.com/profile/01205530113106138349noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-7640963196561814722016-04-16T22:02:24.468+05:302016-04-16T22:02:24.468+05:30Thanks for the blog post . Quick query : Hold time...Thanks for the blog post . Quick query : Hold time of a flop dictates that logic delay of the combinational path be more than a given value ( Tdelay &gt; Thold ) . So can we say that Thold puts a limit on the max frequency of operation since 1/ (max freq) &gt; Tsetup + Tdelay ( I am ignoring c2q delays and clk skews for simplicity ) Anonymoushttps://www.blogger.com/profile/05259142040195907188noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-57813372388242470362016-03-17T01:29:15.445+05:302016-03-17T01:29:15.445+05:30sir ur saying like first go for setup violation th...sir ur saying like first go for setup violation then after for hold ..but after CTS also preference only for setup first and then for hold ???...plz clearifyAnonymousnoreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-90996893085157146272016-01-18T16:46:52.271+05:302016-01-18T16:46:52.271+05:30Before I can help you with the Answer - you have t...Before I can help you with the Answer - you have to differentiate the work of Designer and backend Team? What do you mean by Backend team ?VLSI Experthttps://www.blogger.com/profile/01205530113106138349noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-74307582658865451562016-01-14T08:45:20.159+05:302016-01-14T08:45:20.159+05:30Who fix these setup and hold violation?
Whether th...Who fix these setup and hold violation?<br />Whether the designer or backend team?Anonymoushttps://www.blogger.com/profile/05150792972767378915noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-55108145272668483082015-12-15T19:15:01.269+05:302015-12-15T19:15:01.269+05:30You got to efficiently explain what Synopsys and C...You got to efficiently explain what Synopsys and Cadence manuals don&#39;t do. Thanks a mill.kiteloophttps://www.blogger.com/profile/12206298603086242913noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-45015356392022522212015-12-12T19:25:08.247+05:302015-12-12T19:25:08.247+05:30Hi,
You have said, &quot;hold violation happens wh...Hi,<br />You have said, &quot;hold violation happens when data is too fast compared to clock speed&quot;. But how can hold violation be related to clock speed? Here with clock speed do you mean delay in capture path or clock frequency?Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-67092180759577321002015-11-20T15:43:15.922+05:302015-11-20T15:43:15.922+05:30Thanks a lot!!! learnt a lot from this blogThanks a lot!!! learnt a lot from this bloganonymoushttps://www.blogger.com/profile/00899011281394368587noreply@blogger.comtag:blogger.com,1999:blog-4597498589834570435.post-52986450215704979372015-10-30T10:30:04.352+05:302015-10-30T10:30:04.352+05:30wow super pakka very good explanationwow super pakka very good explanationAnonymoushttps://www.blogger.com/profile/05347246802791347236noreply@blogger.com