Mixed-signal SOC verification using analog behavioral models

The era of “Internet everywhere” is creating a spectrum of applications
targeted toward low-power and mixed-signal design,
in segments ranging from health care to automotive to
communications. Meanwhile, design challenges such as
intellectual-property selection and integration as well
as SOC- and system-level verification are spawning
a whole new class of problems for EDA tools.

Mixed-signal design engineers face increasing difficulties
in design and verification of complex mixed-signal
SOCs. In a survey of mixed-signal design engineers
during the 2011 Mixed-Signal Tech on Tour,
a worldwide series presented by Cadence
Design Systems Inc, the 561 respondents
identified mixed-signal verification as
a top customer challenge.

The performance of Spice simulation
is prominent in the difficulties being
reported (Figure 1). Analog Spice and
Fast-Spice simulators are orders of magnitude
slower than digital simulators
and are slower still when compared
with emulators and hardware accelerators.
A June 2011 Design Automation
Conference panel discussed the need
for analog design and verification to
become more like digital—that is, to
become more structured and more
top-down (Reference 1). Verification
planning tools are required, and debug
methodologies such as ABV (assertion-based
verification), MDV (metric-driven
verification), and UVM (universal
verification methodology)-like self-checking
test benches must be created
for analog/mixed-signal.

Click to enlarge

To tackle simulation-throughput
issues, designers are turning to behavioral-modeling techniques, which can
increase simulation speed. Such techniques
include event-driven simulation
based on Verilog-A, Verilog-AMS, and
RNM (real-number modeling).

Analog behavioral models are typically
written in Verilog-AMS, Verilog-A,
VHDL-AMS, or SystemVerilog.

Verilog-A is a pure-analog subset
of Verilog-AMS and is mainly used for
detailed analog models for performance
verification. The language is quite
simple, but it is challenging to write a
good behavioral model with Verilog-A
that provides significant performance
gains while retaining the right level of
accuracy. The advantage of Verilog-A is
the ability to use models in pure-analog
simulations as well as in the mixed-signal
environment. The models are too
low-level, however, to enable efficient
SOC-level verification of mixed-signal
designs.

The RNM technique models electrical
signals by representing them as real
values. Provided that the modules are
at a sufficiently high level of abstraction,
the interfaces can be described by
passing real numbers between blocks to
represent the voltage, or current, signal
being transferred. This is a powerful
way to simulate complex systems rapidly.
Traditionally, iterating to a solution
involving feedback would require
an analog solver (see sidebar, “Analog
versus digital solvers”).

RNM is available in the Verilog-AMS, SystemVerilog, and VHDL-AMS
languages. A commonly used
RNM approach is the wreal data type
in Verilog-AMS. RNM uses a discrete
event solver—without an analog solver—and can be used to simulate mixed-signal
systems at incredible speeds. It is
primarily limited to modeling at a high
enough level of abstraction that bidirectional
analog interactions between
blocks are not significant. In other
words, typical RNM defines blocks in
terms of input/output transfer characteristics,
with no strong direct feedback
present among the blocks. Logic can be
modeled naturally in these languages,
so RNM is also a good choice for systems
with only a small amount of analog
content.

Top-down or bottom-up

Designers use two principal methodologies
based on the creation of behavioral
models for mixed-signal design.
In a top-down methodology, models
are developed before the circuits are
designed. The behavioral models can
be simpler ones that are sufficient for
functional verification at the system
level. In a bottom-up methodology, the
models are written to match an already
implemented block for performance
verification and usually result in a more
accurate but slower-running model.

The creation of analog behavioral
models can be challenging. Analog
designers are in the best position to
create such models because they are
familiar with their own circuits. Many
analog designers lack the programming
skills and knowledge required to construct
behavioral models, however, and
few are familiar with Verilog or VHDL.
Digital designers, conversely, have
expertise with behavioral models but
know less about analog circuits.

That dichotomy creates an opportunity
for tool vendors to offer an
automated or semi-automated solution
for generating analog behavioral models.
For example, automated, netlist-driven
model-generation technologies
can create a fairly accurate parametric
behavioral model that considers PVT
(process, voltage, and temperature)
and loading variations for functional
verification. Such an approach has
shown some limited success on a subset
of analog-circuit architectures under
specific contexts, but there is still much
work to be done to develop a general
model-generation methodology with
high accuracy that can be applied to any
analog or mixed-signal design.

Creating behavioral models is only
one part of the process of using those
models in a mixed-signal verification flow.
If the model and implementation do not
match, the effort is worthless; worse, it
can damage the entire design process. As
a result, there is a need for a methodology
to validate the accuracy of a behavioral
model automatically against the corresponding
design. The model also must
be updated to keep it in sync with any
changes made in the implementation.