In the above code, lines in green are comments, and blue are keywords in E language, "sys" is the top most module. Like in Verilog we have top module. run() is a method, which is executed at the start of simulation. out is same as printf in C language or $display in verilog.

Line number 2, 11 mark the code segement, anything outside this is ignored by Specman, so this can be used for writing comments. Line 5 is extend, which extends the "sys" to tell specman to include the code below it into simulator. run() is also method is extended to have out statement.

Simulating Hello World

Hello World example can be simulating with following command

$specman -c "load hello.e; test;"

Output of specman is as given below.

Hello World

Simple Random Generator

To demonstrate a random generator of Specman, lets consider a simple memory, which needs address, data and read/write command to access memory.