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AR# 4689

Description

Keywords: bus slice, sensitivity list, support, warning

Urgency: Standard

General Description:In FPGA Express 2.1, if a bus slice is being read within a process, a warning reports that a signal is being read, but is not part of the sensitivity list. However, if the bus slice (e.g., bob(2 downto 1)) is placed in the sensitivity list, FPGA Express produces the following warning:

Warning L69/C0 : #0 Warning: Only simple variables are checked in the sensitivity list. The variable in the sensitivity list on line 69 will be ignored. (HDL-178)

Solution

1

Bus slices are not allowed in sensitivity lists. To properly code the design, you must assign a dummy signal to the bus slice (combinatorially), then replace the bus slice in the process and sensitivity list with the dummy signal.

The work-around is to:

1. Create dummy signals for each bit of the bus slice in question.2. Assign the bus slice bits to these dummy signals with combinatorial logic.3. Within the sensitivity list and process in question, replace any references to the bus slice with the dummy signals (only in the processes in which you are trying to read from the bus slice).