Imperas Applications at DATE 2018 in Germany

DATE Features Presentations Focused on Virtual Platforms for Non-intrusive Fault Injection and Power Management

Imperas will participate in DATE (Design, Automation & Test in Europe) 2018, a leading international event for design, engineering, automation, and test of microelectronics systems-on-chip, systems-on-board, embedded systems and software for both academic and commercial communities.

DATE 2018 will feature two presentations based on Imperas virtual platform technology:

The increasing computing capacity of multicore components like processors and graphics processing unit (GPUs) offer new opportunities and challenges in embedded and high-performance computing (HPC) domains. Large-scale HPC systems already employ over a million cores, while thousand-core on-chip platforms are available to the embedded community. This massive number of cores, the increasing computing capacity, and the number of internal memory cells (e.g., registers, internal memory) inherent to emerging processor architectures is making large-scale systems more vulnerable to both hard and soft errors. Aggressive performance, clock frequencies, and multiple voltage domains to meet power requirements, processors have increased susceptibility to soft errors, such as those caused by radiation effects. These soft errors may cause critical failures of system behavior with potential financial or human losses. A rate of 280 soft errors per day has been observed during spacecraft flight, while other ground-level multicore electronic systems are expected to experience at least one soft error per day. This susceptibility calls for innovative, cost-effective tools to assess the soft error resilience of multicore systems with complex software stacks (OS, drivers) at the early design phase. This paper proposes and develops a fault injection framework using a state-of-the-art virtual platform, with a set of novel fault injection techniques to direct fault campaigns according to software stack characteristics, and extensive validation with over a million simulation hours.

This work analyzes the correct usage of power management techniques, as well as the analysis of extra-functional properties, including power and timing properties, in multiprocessor system-on-chips (MPSoC). Especially in safety-critical environments, the power management becomes safety-critical too, since it influences the overall system behavior. The developed methodologies are demonstrated by a mixed-criticality multi-rotor system and its corresponding fully-functional virtual prototype.

This presentation runs daily March 20, 21, and 22, 2018 starting at 10AM in booth 1 of the exhibition area.