Startup Slashes SRAM Power With Standard Logic Process

A UK startup has developed an entirely new way of building static memory on a standard logic process that cuts the power in half without paying a penalty in area or speed.

"Fundamentally memory has some real problems everyone does it the same way," said Mark de Souza, chief executive at Silicon Basis in Bristol and formerly at the memory IP supplier Virage Logic. "They all take the TSMC arrays and put them together."

Silicon Basis sees two key advantages for its technology: It can save up to 50% of the power consumption, and it can go below the bit cell voltage of the foundry memories. This allows the memories to be powered by the same voltage source as the logic and so eliminates the need for a second DC-DC converter. It also makes the technology foundry independent and scalable to new technologies such as FinFet, says de Souza. The company, based in the SETsquared center in Brunel's EngineShed in Bristol, has produced all the models needed and is now working on 28nm silicon to prove the implementation.

"We use our own bit cell, so we are not restricted to the foundry's Vmin, which is a huge advantage," said de Souza. "Dropping the voltage makes a huge difference."

All this comes from a new way of looking at the design of the cell, which is currently being patented.

"No one has seen this way of designing SRAM before," de Souza said. "We are talking to the experts in memory design, and no one has seen this way of putting memory together. It's all using standard rules and standard CMOS. It's an architectural difference that means we don't need to use sense amps, and because we are using logic rules, we can go down to the logic voltage floor and possibly below that."

"Our cell size is about the same as the high-speed cell from the foundry," said Rob Beat, founder and chief technology officer of Silicon Basis and designer of the new cell. "There's a compromise on area in the array, but because the periphery is more efficient, we are competitive in area, especially on the smaller RAMs."

The architecture brings advantages with the compiler that are not to be underestimated, he says.

"Our single-port compiler also outputs a one-port register file," Basis said. "Because of the way the bit cell is designed, we can use the same bit cell for dual port, so the dual-port compiler will do the dual-port register file and asynchronous dual-port memory."

This avoids the problems of having up to five different compilers for each process technology with a significant support burden, he says.

The technology has been characterized on the TSMC 40nm node and outperforms the high-speed bit cell, says de Souza.

"This took us a little bit by surprise, as we didn't design for speed," he said. "We did a lot of work at 40nm, but what we are seeing from customers is that 28nm HPM is going to be a major node, and we think there will be more new designs starting on 28nm than on 40nm."

The technology is also fully compatible with FinFet vertical structures being used in TSMCs 16nm process node. "Our technology will work very nicely with FinFet right out of the box," he said.

The technology has previously been used by Beat to develop low-power FPGA fabric but has attracted more interest for the SRAM compiler. "For me, Silicon Basis starts here," said de Souza.

anyone from the company would be interested in giving a talk on this topic at CMOS emerging technology sympsoium in Grenoble? preliminary program at www.cmosetr.com, if interested pls contact kris.iniewski@gmail.com

Indeed - a telling point is that Rob Beat doesn't want to talk about what the cell structure is yet (whether its 4T or 5T is not the best way to talk about it, he says). Patents have been applied for in the UK but are in process for the rest of the world, hence the reluctance. But removing the sense amps give you more room for optimization. An interesting story to watch.