Pipeline and Reorder Buffer on Cortex A9

For research reasons, I'm looking for information about the Cortex A9 out-of-order pipeline and the renaming of registries and any other data structures, if any, such as the reorder buffer (ROB).

The Technical Reference Manual only names the presence of the unit that renames the registers, but usually, the reorder buffer is used before commit.

I have read about the Cortex A73 and A75 processors (both out of order like A9):

"The A75’s Rename and Dispatch stages are similar to the A73’s. Like the A73 and other Sophia CPUs, there’s no reorder buffer or architectural register file in the A75. Instead it uses a physical register file for storing µop operands, reducing power by limiting the amount of data moving around the CPU and eliminating some instruction window bottlenecks that arise from using a reorder buffer."

Does the A9 behave in the same way as these processors (absence of ROB) or does it have the ROB?