Abstract:

A multi-channel decoding method includes: receiving an input signal to
generate a first channel output signal and a second channel output
signal, wherein the input signal is mixed with a specific clock signal;
and gradually changing an amplitude of the specific clock signal from a
first value to a second value when switching from a first mode
corresponding to a first number of channels to a second mode
corresponding to a second number of channels. Systems utilizing the
method and another method further comprising calibration are also
disclosed.

Claims:

1. A multi-channel decoding system, comprising:a decoding circuit, for
receiving an input signal to generate a first channel output signal and a
second channel output signal, wherein the decoding circuit has:a mixer,
for mixing the input signal with a specific clock signal; anda clock
generating circuit, for generating the specific clock signal, wherein the
clock generating circuit is arranged to gradually change an amplitude of
the specific clock signal from a first value to a second value when
receiving a mode switching signal instructing a switching from a first
mode corresponding to a first number of channels to a second mode
corresponding to a second number of channels.

2. The multi-channel decoding system of claim 1, wherein the input signal
is an audio signal, one of the first mode and the second mode is a mono
mode, and one of the first value and the second value is substantially
zero.

3. The multi-channel decoding system of claim 1, wherein the clock
generating circuit comprises:a signal processing unit, for generating a
control signal according to the mode switching signal, wherein when the
mode switching signal instructs the switching from the first mode to the
second mode, the signal processing unit generates the control signal
having a gradual transition from a first level to a second level; anda
clock signal generator, for generating the specific clock signal
according to a predetermined reference clock signal and the control
signal.

4. The multi-channel decoding system of claim 3, wherein the clock signal
generator comprises a multiplier for combining the predetermined
reference clock signal and the control signal to generate the specific
clock signal.

5. A multi-channel decoding system, comprising:a decoding circuit, for
receiving an input signal to generate a channel output signal;a test
signal generating circuit, for providing a first test signal serving as
the input signal in a first calibration mode; anda calibration circuit,
for adjusting a DC voltage level of the channel output signal outputted
by the decoding circuit with a first calibration signal by reducing a
difference between a first predetermined reference signal level and a DC
voltage level of the channel output signal generated from the first test
signal.

6. The multi-channel decoding system of claim 5, wherein the calibration
circuit comprises:a comparison module, for comparing the DC voltage level
of the channel output signal generated from the first test signal with
the first predetermined reference signal level to output a first
comparison result of the first calibration mode; anda decision module,
for adjusting the first calibration signal according to the first
comparison result.

7. The multi-channel decoding system of claim 6, wherein the decision
module comprises:a decision unit, for determining a first digital code
according to the first comparison result; anda digital-to-analog
converter, for converting the first digital code into a first voltage
serving as the first calibration signal.

8. The multi-channel decoding system of claim 7, wherein the decision unit
utilizes a digital successive-approximation algorithm to determine the
first digital code.

9. The multi-channel decoding system of claim 5, wherein the test signal
generating circuit is arranged to provide a second test signal serving as
the input signal in a second calibration mode; the calibration circuit is
arranged to adjust the DC voltage level of the channel output signal
outputted by the decoding circuit with a second calibration signal by
reducing a difference between a second predetermined reference signal
level and a DC voltage level of the channel output signal generated from
the second test signal; and one of the first calibration mode and the
second calibration mode is a mono calibration mode and the other of the
first calibration mode and the second calibration mode is a stereo
calibration mode.

10. The multi-channel decoding system of claim 9, wherein the first test
signal is identical to the second test signal.

11. The multi-channel decoding system of claim 5, wherein the first test
signal is a square wave signal; and the decoding circuit comprises:a
demodulator, for demodulating the square wave signal into a DC signal;
anda signal processing module, for generating the channel output signal
according to the DC signal.

12. A multi-channel decoding method, comprising:receiving an input signal
to generate a first channel output signal and a second channel output
signal, wherein the input signal is mixed with a specific clock signal;
andgradually changing an amplitude of the specific clock signal from a
first value to a second value when switching from a first mode
corresponding to a first number of channels to a second mode
corresponding to a second number of channels.

13. The multi-channel decoding method of claim 12, wherein the input
signal is an audio signal, one of the first mode and the second mode is a
mono mode, and one of the first value and the second value is
substantially zero.

14. The multi-channel decoding method of claim 12, wherein the step of
gradually changing the amplitude of the specific clock signal
comprises:generating a control signal having a gradual transition from a
first level to a second level when switching from the first mode to the
second mode; andgenerating the specific clock signal according to a
predetermined reference clock signal and the control signal.

15. The multi-channel decoding method of claim 14, wherein the step of
generating the specific clock signal comprises:multiplying the
predetermined reference clock signal by the control signal to generate
the specific clock signal.

16. A multi-channel decoding method, comprising:receiving an input signal
to generate a channel output signal;providing a first test signal serving
as the input signal in a first calibration mode; andadjusting a DC
voltage level of the channel output signal with a first calibration
signal by reducing a difference between a first predetermined reference
signal level and a DC voltage level of the channel output signal
generated from the first test signal.

17. The multi-channel decoding method of claim 16, wherein the step of
adjusting the DC voltage level of the channel output signal
comprises:comparing the DC voltage level of the channel output signal
generated from the first test signal with the first predetermined
reference signal level to output a first comparison result of the first
calibration mode; andadjusting the first calibration signal according to
the first comparison result.

18. The multi-channel decoding method of claim 17, wherein the step of
adjusting the first calibration signal according to the first comparison
result comprises:determining a first digital code according to the first
comparison result; andconverting the first digital code into a first
voltage serving as the first calibration signal.

19. The multi-channel decoding method of claim 18, wherein the step of
determining the first digital code according to the first comparison
result comprises:utilizing a digital successive-approximation algorithm
to determine the first digital code.

20. The multi-channel decoding method of claim 16, further
comprising:generating a second test signal serving as the input signal in
a second calibration mode; andadjusting the DC voltage level of the
channel output signal with a second calibration signal by reducing a
difference between a second predetermined reference signal level and a DC
voltage level of the channel output signal generated from the second test
signal;wherein one of the first calibration mode and the second
calibration mode is a mono calibration mode and the other of the first
calibration mode and the second calibration mode is a stereo calibration
mode.

21. The multi-channel decoding method of claim 20, wherein the first test
signal is identical to the second test signal.

22. The multi-channel decoding method of claim 16, wherein the first test
signal is a square wave signal; and the step of receiving the input
signal to generate the channel output signal comprises:demodulating the
square wave signal into a DC signal; andgenerating the channel output
signal according to the DC signal.

Description:

BACKGROUND

[0001]The present invention relates to a multi-channel decoding scheme,
and more particularly to a multi-channel decoding system capable of
reducing noise when switching between different channel modes, and method
thereof.

[0002]Generally speaking, when a multi-channel decoding system switches
from a multi-channel mode to a single-channel mode or from the
single-channel mode to the multi-channel mode, users often hear a "pop"
noise from their earphones or speakers. This is primarily because the
output DC voltage levels of a channel output signal in the multi-channel
and single-channel modes, which is generated from the multi-channel
decoding system, are different. Another reason may result from the Glitch
phenomenon during switching between the multi-channel and single-channel
modes. Taking a stereo decoding system as an example, the pop noise is
usually heard by human when the stereo decoding system switches between
stereo and mono modes.

[0003]Please refer to FIG. 1 in conjunction with FIG. 2. FIG. 1 is a
diagram of a related art stereo decoding system 100, and FIG. 2 is a
timing diagram illustrating a clock signal SCLK having a frequency
38 KHz, a mode switching signal SMODE, and a clock signal
SCLK'. As shown in FIG. 1, the stereo decoding system 100 comprises
a decoding circuit 105 and a clock generating circuit 110, where the
decoding circuit 105 further includes a mixer 115, voltage-to-current
(V/I) converters 120a and 120b, a separation module 125, operational
amplifiers OP1 and OP2, resistor units 130a and 130b, and low
pass filters (LPFs) 135a and 135b. The decoding circuit 105 is utilized
for receiving an input audio signal Sin to generate a left channel
output signal LOUT and a right channel output signal ROUT according to
the clock signal SCLK'. When the mode switching signal SMODE is
at a high logic level, it indicates that the stereo decoding system 100
is in the stereo mode; when the mode switching signal SMODE is at a
low logic level, this indicates that the stereo decoding system 100 is in
the mono mode.

[0004]Ideally, the DC voltage level of the channel output signal LOUT or
ROUT should be identical whether the stereo decoding system 100 is in the
stereo mode or the mono mode. Practically, however, an equivalent offset
voltage source Vos exists within the decoding circuit 105 and the DC
voltage level of the channel output signal LOUT/ROUT in the stereo and
mono modes are different due to the offset voltage source Vos. For
example, in stereo mode, a voltage of the offset voltage source Vos
is equal to V1; in mono mode, the voltage of the offset voltage
source Vos will become V2. Consequently, the DC voltage level
of the channel output signal LOUT/ROUT is changed while the stereo
decoding system 100 switches from mono mode to stereo mode and the
above-mentioned pop noise is thus introduced.

SUMMARY

[0005]It is therefore one of the objectives of the present invention to
provide a multi-channel decoding system and related method capable of
reducing the noise, to solve the above-mentioned problems.

[0006]According to an embodiment of the present invention, a multi-channel
decoding system is disclosed. The multi-channel decoding system comprises
a decoding circuit and a clock generating circuit. The decoding circuit
is utilized for receiving an input signal to generate a first channel
output signal and a second channel output signal. The decoding circuit
has a mixer used for mixing the input signal with a specific clock
signal. The clock generating circuit is utilized for generating the
specific clock signal and arranged to gradually change an amplitude of
the specific clock signal from a first value to a second value when
receiving a mode switching signal instructing a switching from a first
mode corresponding to a first number of channels to a second mode
corresponding to a second number of channels.

[0007]According to the embodiment of the present invention, a
multi-channel decoding method is disclosed. The multi-channel decoding
method comprises the following steps: receiving an input signal to
generate a first channel output signal and a second channel output
signal, wherein the input signal is mixed with a specific clock signal;
and gradually changing an amplitude of the specific clock signal from a
first value to a second value when switching from a first mode
corresponding to a first number of channels to a second mode
corresponding to a second number of channels.

[0008]According to another embodiment of the present invention, a
multi-channel decoding system is disclosed. The multi-channel decoding
system comprises a decoding circuit, a test signal generating circuit,
and a calibration circuit. The decoding circuit is utilized for receiving
an input signal to generate a channel output signal, and the test signal
generating circuit is utilized for providing a first test signal serving
as the input signal in a first calibration mode. The calibration circuit
is utilized for adjusting a DC voltage level of the channel output signal
outputted by the decoding circuit with a first calibration signal by
reducing a difference between a first predetermined reference signal
level and a DC voltage level of the channel output signal generated from
the first test signal.

[0009]According to the embodiment of the present invention, a
multi-channel decoding method is disclosed. The multi-channel decoding
method comprises the following steps: receiving an input signal to
generate a channel output signal; providing a first test signal serving
as the input signal in a first calibration mode; and adjusting a DC
voltage level of the channel output signal outputted by the decoding
circuit with a first calibration signal by reducing a difference between
a first predetermined reference signal level and a DC voltage level of
the channel output signal generated from the first test signal.

[0010]These and other objectives of the present invention will no doubt
become obvious to those of ordinary skill in the art after reading the
following detailed description of the preferred embodiment that is
illustrated in the various figures and drawings.

[0013]FIG. 3 is a diagram of a multi-channel decoding system according to
a first embodiment of the present invention.

[0014]FIG. 4 is a timing diagram illustrating an example of a
predetermined reference clock signal SCLK, a mode switching signal
SMODE, a control signal Sc, and a specific clock signal
SCLK' shown in FIG. 3.

[0015]FIG. 5 is a diagram of a particular example of a clock signal
generator shown in FIG. 3.

[0016]FIG. 6 is a schematic diagram of a multi-channel decoding system
according to a second embodiment of the present invention.

[0017]FIG. 7 is a timing diagram illustrating an example of a calibration
process for the DC voltage level of the channel output signal LOUT in the
mono mode according to the second embodiment of the present invention.

[0018]FIG. 8 is a timing diagram showing calibration processes for the DC
voltage level of the channel output signals LOUT and ROUT in the mono and
stereo modes, respectively.

DETAILED DESCRIPTION

[0019]Certain terms are used throughout the description and following
claims to refer to particular components. As one skilled in the art will
appreciate, electronic equipment manufacturers may refer to a component
by different names. This document does not intend to distinguish between
components that differ in name but not function. In the following
description and in the claims, the terms "include" and "comprise" are
used in an open-ended fashion, and thus should be interpreted to mean
"include, but not limited to . . . ". Also, the term "couple" is intended
to mean either an indirect or direct electrical connection. Accordingly,
if one device is coupled to another device, that connection may be
through a direct electrical connection, or through an indirect electrical
connection via other devices and connections.

[0020]FIG. 3 is a diagram of a multi-channel decoding system 300 according
to a first embodiment of the present invention. The multi-channel
decoding system 300 includes a decoding circuit 305 and a clock
generating circuit 310. The decoding circuit 305 is utilized for
receiving an input signal Sin to generate at least a first channel
output signal (e.g. a left channel output signal LOUT) and a second
channel output signal (e.g. a right channel output signal ROUT); other
operations and functions of decoding circuit 305 are similar to those of
the decoding circuit 105 and not detailed for brevity. The clock
generating circuit 310 is utilized for generating a specific clock signal
SCLK' and for gradually changing the amplitude of the specific clock
signal SCLK' from a first value to a second value when switching
from a first mode to a second mode, such as receiving a mode switching
signal SMODE instructing a switching from the first mode
corresponding to a first number of channels to the second mode
corresponding to a second number of channels. For instance, the clock
generating circuit 310 gradually changes the amplitude of the specific
clock signal SCLK' from a specific value to substantially zero or
from substantially zero to the specific value when switching happens. In
this embodiment, the multi-channel decoding system 300 is a stereo
decoding system; the first mode and the second mode are respectively
meant to be a stereo mode and a mono mode. More specifically, the clock
generating circuit 310 further includes a signal processing unit 3101 and
a clock signal generator 3103. The signal processing unit 3101 generates
a control signal Sc according to the mode switching signal
SMODE. Particularly, when the mode switching signal SMODE
instructs the switching between the stereo and mono modes, the signal
processing unit 3101 generates the control signal Sc having a
gradual transition from a first level to a second level, where one of the
first and second levels is a low level (e.g. zero) and the other is a
high level. The clock signal generator 3103 is utilized for generating
the specific clock signal SCLK' according to a predetermined
reference clock signal SCLK and the control signal Sc. In
practice, the clock signal generator 3103 can be implemented by a
multiplier used for combining the predetermined reference clock signal
SCLK and the control signal Sc to generate the specific clock
signal SCLK'.

[0021]As mentioned above, the noise resulting from the equivalent offset
voltage source Vos is easily heard if a conventional multi-channel
decoding system, such as the system 100 of FIG. 1, abruptly switches from
stereo mode to mono mode or vice versa. In the first embodiment, the mode
switching signal SMODE originally having sharp transitions is
processed by the signal processing unit 3101, such that the control
signal Sc having gradual transitions is generated. The clock signal
generator 3103 then generates the specific clock signal SCLK' which
also has gradual transitions according to the predetermined reference
clock signal SCLK (usually has a frequency 38 KHz) and the control
signal Sc. Taking an example of the multi-channel decoding system
300 switching from the stereo mode to the mono mode, a timing diagram
regarding the control signal Sc and specific clock signal SCLK'
is illustrated in FIG. 4. As shown in FIG. 4, when the mode switching
signal SMODE instructs a switching from the mono mode (MN) to the
stereo mode (ST) at timing T1, the control signal Sc gradually
transits from a low level to a high level before timing T2; in this
example, the waveform of the control signal Sc during timing T1
to T2 looks substantially linear. However, gradually linear
transition is not intended to be a limitation of the present invention.
The clock signal generator 3103 then multiplies the predetermined
reference clock signal SCLK by the control signal Sc to
generate the specific clock signal SCLK'. Obviously, it is shown
that the amplitude of the specific clock signal SCLK' is increased
(from zero to A1) gradually during timing T1 to T2.
Accordingly, although the DC voltage level of the channel output signal
LOUT or ROUT is different in the stereo mode and mono mode, the noise is
not easily perceived by human since the multi-channel decoding system 300
does not switch rapidly from the mono mode to stereo mode. Similarly,
when the mode switching signal SMODE instructs a switching from the
stereo mode (ST) to the mono mode (MN), the control signal Sc also
gradually transits from the high level to the low level and therefore the
amplitude of the specific clock signal SCLK' is not rapidly
decreased (from A1 to substantially zero). A detailed description is
not explained for brevity.

[0022]Moreover, another example of the clock signal generator 3103 is
shown in FIG. 5. A signal SCLK1 is meant to be an inverse signal of
the predetermined reference clock signal SCLK and a voltage VCM is a
common mode voltage. The specific clock signal SCLK' shown in FIG. 3
comprises output signals Sout and Sout1. For those skilled in
this art, it should be well-known to appreciate the operation of the
circuit (i.e. the clock signal generator 3103) shown in FIG. 5 and it is
not illustrated for simplicity.

[0023]Please refer to FIG. 6. FIG. 6 is a schematic diagram of a
multi-channel decoding system 600 according to a second embodiment of the
present invention. As shown in FIG. 6, the multi-channel decoding system
600 comprises a decoding circuit 605, a clock generating circuit 610, a
test signal generating circuit 640, and a calibration circuit 645, where
the decoding circuit 605 further comprises a signal processing module 606
and a demodulator 608. The test signal generating circuit 640 is utilized
for providing a first test signal in a first calibration mode and
providing a second test signal in a second calibration mode. In this
embodiment, the first and second test signals are identical square wave
signals and are both called Stest. The test signal Stest is
served as an input signal for the decoding circuit 605 in the first and
second calibration modes. However, providing the same test signal
Stest for two different calibration modes is not intended to be a
limitation of the present invention. Moreover, the first and second
calibration modes are respectively meant to be a stereo mode and a mono
mode when calibrating DC voltage levels of channel output signals LOUT
and ROUT. The demodulator 608 demodulates the test signal Stest into
a DC signal Sin', and then the signal processing module 606
generates the channel output signals LOUT and ROUT. Since operation and
function of the signal processing module 606 are respectively similar to
those of the decoding circuit 105, these are not detailed for brevity.
Moreover, the clock generating circuit 610 can be the conventional clock
generating circuit 110 in FIG. 1 whose specific clock signal SCLK'
has sharp transitions, or the clock generating circuit 310 in FIG. 3
whose specific clock signal SCLK' has gradual transitions. Of
course, it is assumed that an equivalent offset voltage source Vos
also exists within the decoding circuit 605.

[0024]After the decoding circuit 605 outputs the channel output signals
LOUT and ROUT generated from the test signal Stest, the calibration
circuit 645 outputs a first calibration signal Scal and a second
calibration signal Scal'into the decoding circuit 605 according to
the channel output signals LOUT and ROUT, so as to respectively adjust DC
voltage levels of the channel output signals LOUT and ROUT in the stereo
and mono modes, for example, by separately reducing the difference
between the DC voltage level of the channel output signal LOUT generated
from the first test signal Stest and a first predetermined reference
signal level Sref (e.g. ground level) with the first calibration
signal Scal and reducing a difference between the DC voltage level
of the channel output signal ROUT generated from the second test signal
Stest and a second predetermined reference signal level Sref'
(e.g. ground level) with the second calibration signal Scal'. In
this embodiment, the first and second predetermined reference signal
level Sref and Sref' inputted into a comparison module 6451 are
designed to become identical. That is, the DC voltage levels of the
channel output signals LOUT and ROUT are adjusted to be close to the same
predetermined reference signal level whether in stereo or mono mode. In
the following description, for simplicity, the first predetermined
reference signal level Sref is used for illustrative purposes. Even
though the multi-channel decoding system 600 suddenly switches between
the stereo mode and mono mode, the noise due to the equivalent offset
voltage source Vos can be therefore reduced and not easily perceived
by human.

[0025]The calibration circuit 645 comprises a comparison module 6451 and a
decision module 6453. The comparison module 6451 is used for comparing
the DC voltage level of the channel output signal LOUT/ROUT with the
predetermined reference signal level Sref, to output a first
comparison result in the stereo mode and a second comparison result in
the mono mode, respectively. In this embodiment, the comparison module
6451 is implemented by a comparator COMP, where an inverting input
terminal of the comparator COMP is coupled to the predetermined reference
signal level Sref while a non-inverting input terminal of the
comparator COMP is coupled to the channel output signal LOUT/ROUT
switched by switches SW2 and SW3, as shown in FIG. 6. The
decision module 6453 is utilized for separately adjusting the first
calibration signal Scal and the second calibration signal
Scal'according to the first comparison result and the second
comparison result. In this embodiment, the decision module 6453 comprises
a decision unit 64531 and a digital-to-analog converter (DAC) 64535. The
decision unit 64531 is utilized for determining a first adjusting signal
Sadj and a second adjusting signal Sadj' according to the first
and second comparison results respectively, and the DAC 64535 is used for
converting the first and second adjusting signals Sadj and
Sadj' into a first voltage VL and a second voltage VR
serving as the first and second calibration signals Scal and
Scal'respectively. More specifically, the first and second adjusting
signals Sadj and Sadj' can be digital codes, and the DAC 64535
converts the digital codes, e.g. first and second adjusting signals
Sadj and Sadj', into the first voltage VL and the second
voltage VR.

[0026]Furthermore, the decision unit 64531 may utilize a digital
successive-approximation algorithm to determine the first and second
adjusting signals Sadj and Sadj'; of course, other
approximation algorithms can also be applied to the embodiments of the
present invention. In this embodiment, the values of the resistors
RS, RS', RF, and RF' are designed carefully so that
the voltage levels of the channel output signals LOUT and ROUT are
compensated. For example, in order to compensate the voltage level of the
channel output signal LOUT, the values of the resistors RS and
RF are designed such that the value of the first voltage VL
equals a specific value associated with the equivalent offset voltage of
the channel output signal LOUT, which is illustrated in Equation (1):

V L = ( 1 + R F R S ) × V os 1 ,
Equation ( 1 ) ##EQU00001##

[0027]where the value Vosl is indicative of the voltage level of the
channel output signal LOUT before calibrated, i.e. the equivalent offset
voltage. Through the calibration, the voltage level (DC voltage) of the
channel output signal LOUT is therefore adjusted to become almost zero.

[0028]Similarly, for compensating the voltage level of the channel output
signal ROUT, the values of the resistors RS' and RF' are
designed such that the value of the first voltage VR equals a
specific value associated with the equivalent offset voltage of the
channel output signal ROUT, which is illustrated in Equation (2):

V R = ( 1 + R F ' R S ' ) × V osr ,
Equation ( 2 ) ##EQU00002##

[0029]where the value Vosr is indicative of the voltage level of the
channel output signal ROUT before calibrated, i.e. the equivalent offset
voltage. Through the calibration, the voltage level (DC voltage) of the
channel output signal ROUT is also adjusted to become almost zero.

[0030]Please refer to FIG. 7. FIG. 7 is a timing diagram illustrating an
example of a calibration process for the DC voltage level of the channel
output signal LOUT in mono mode according to the second embodiment of the
present invention. A control signal Sc1 is utilized for controlling
a status of a switch SW1 shown in FIG. 6; when the control signal
Sc1 transits from a low level to a high level at timing T0, the
switch SW1 is turned on. Next, at timing T1, a control signal
Sc2 for switch SW2 of FIG. 6 also transits from a low level to
a high level and the calibration process for the channel output signal
LOUT in the mono mode is enabled. Initially, the first adjusting signal
Sadj equaling a code `10000` corresponds to the first voltage
V1 equaling zero. When the DC voltage level of the channel output
signal LOUT is higher than the predetermined reference signal level
Sref, such as in a time period from T2 to T3, the first adjusting
signal Sadj is to be another code `11000` to raise the first voltage
V1 for decreasing the DC voltage level of the channel output signal
LOUT (e.g. during timing T3 to T4). Otherwise, if the DC voltage level of
the channel output signal LOUT is lower than the predetermined reference
signal level Sref, the first adjusting signal Sadj will be
adjusted to lower the first voltage V1 for increasing the DC voltage
level of the channel output signal LOUT. In this example, the DC voltage
level of the channel output signal LOUT is gradually decreased and
finally is close to the predetermined reference signal level Sref.
The decision unit 64531 then records the first adjusting signal Sadj
finally determined (e.g. the code `11111` in this example). The first
adjusting signal Sadj is then applied in the signal processing
module 606 when the multi-channel decoding system 600 receives an input
audio signal instead of the test signal Stest to generate the
channel output signal in the mono mode. A detailed procedure of how the
first and second calibration signals Scal and Scal'change the
DC voltage levels of the channel output signals LOUT and ROUT is
well-known to those skilled in this art, and further description is
omitted for simplicity.

[0031]A calibration process for the DC voltage level of the channel output
signal LOUT in stereo mode or for the DC voltage level of the channel
output signal ROUT in mono/stereo mode is similar to the above-mentioned
calibration process shown in FIG. 7. Please refer to FIG. 8. FIG. 8 is a
timing diagram showing the calibration processes for the DC voltage level
of the channel output signals LOUT and ROUT in mono and stereo modes,
respectively. Codes C1 and C2 are in the first adjusting signal
Sadj finally determined by the decision unit 64531 for the mono mode
and stereo mode, respectively. Codes C3 and C4 are in the
second adjusting signal Sadj' finally determined by the decision
unit 64531 for the mono mode and stereo mode, respectively. Further
description is not detailed here for brevity. Obviously, through the
calibration processes, the DC voltage level of the channel output signal
LOUT whether in mono or stereo mode is very close to the predetermined
reference signal level Sref, and the DC voltage level of the channel
output signal ROUT is also close to the predetermined reference signal
level Sref whether in mono or stereo mode. Consequently, the problem
caused by the pop noise due to the equivalent offset voltage source
Vos can be solved.

[0032]Additionally, in another embodiment, if calibrating only the DC
voltage level of the channel output signal LOUT or ROUT is considered,
then the calibration circuit 645 can only output the first calibration
signal Scal or the second calibration signal Scal'into the
decoding circuit 605 according to the channel output signal LOUT or ROUT
to adjust the DC voltage level of the channel output signal LOUT or ROUT
in the mono and stereo modes. This also helps to reduce the pop noise
caused by the equivalent offset voltage source Vos.

[0033]Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made while
retaining the teachings of the invention.