SiC MESFET with a Double Gate Recess

Abstract:

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In order to increase the output power and drain efficiency, MESFETs in SiC have been
made with a double gate recess technique. Typical device characteristics of the MESFETs are drain
currents of 380mA/mm, breakdown voltages of 80V and ft/fmax of 10/25 GHz respectively. These
transistors exhibit power densities of 3W/mm@3GHz in class AB operation and drain efficiencies
of 60%. Packaged devices with 3 mm gate periphery of this type, with via-hole grounding, gave
power densities of 1.2 W/mm@6GHz at 50 V drain bias.

Abstract: Lateral MOSFET devices with varying size from a single unit cell to 3x3 mm2 containing 1980 unit cells have been realised using two basic technologies; lateral trench MOSFET (LTMOS) with epitaxially grown source and drain, and lateral MOSFET with lightly doped drain (LDDMOS) having implanted source and drain regions. The LDDMOS devices had blocking capability of 100 V and the channel mobility in the range of 10 cm2/Vs in {-110} current flow direction and of
5 cm2/Vs in {110} current flow direction. The properties of both fabricated MOSFET types, LTMOS and LDDMOS, are dominated by a high density of interface states of the order of 1×1013 cm-2eV-1. Both the drain current and the leakage current scale linearly with the device size up to the maximum investigated device size of 3x3 mm2. No size limiting defects have been observed
contrary to what is often the case in 4H-SiC material.

Abstract: Trenched, vertical SiC static induction transistors (SIT) for L-band power amplification
were fabricated with implanted p-n junction gates on conducting n-type 4H-SiC substrates using a
self-aligned fabrication process. The self-aligned fabrication process required no critical alignments
and allowed for high channel packing densities ranging from 2.9x103 to 5x103 cm/cm2. Devices
were fabricated with a range of finger widths. Devices with the narrowest fingers were able to block
up to 450 V with VGS = -3 V. Devices with wider fingers required higher gate voltages ranging
from -10 V to -25 V to achieve similar blocking. Devices were packaged and small-signal and loadpull
measurements were taken with the devices externally matched. Devices having the narrowest
finger design had a small-signal power gain of over 9 dB at around 1.3 GHz. Load-pull
measurements of packaged SITs with 1 cm gate periphery yielded a maximum power gain of ~ 8.2
dB at 1 GHz, VDD = 100 V, and VGS = 1.2 V. Due to the high packing density, these results translate
to power densities of 22 kW/cm2.

Abstract: Low frequency noise on 4H-SiC low-level signal-lateral JFETs was systematically investigated. In contrast to previous studies, which are based upon high power vertical structures, this work investigates the low-frequency noise behaviour of low-level signal-lateral devices which are more relevant to the realisation of small signal amplifiers.The JFETs studied share an identical cross section, with different gate lengths and widths. For high temperature operation between 300K and 700K at VGS = 0V, the Normalised Power Spectral Density (NPSD) of the JFETs is proportional to ƒ-1. The NPSD increases monotonically with temperature until a critical temperature, where it starts to decline. Two unique noise origins, fluctuation from bulk and SiO2-SiC interface traps were observed across all the devices investigated. Low frequency noise for devices with a 50μm gate width is localised at the SiO2-SiC interface, whereas for wider devices the noise is seen to be of bulk/substrate origin, which follows Hooge’s model.