Penryn Update

The deep power down state (aka C6) is another interesting and unique feature. We save away the entire processor state for the cores and turn off the caches and put the cores in an extremely low power state. This significantly reduces processor power consumed in idle mode and extends battery life. The OS initiates this with an MWAIT instruction and the CPU works with the chipset VRM to enter the deep power down state. On a wake up event (interrupt), voltage is increased, clocks and CPU state restored and execution begins.

Too frequent transitions to deep power down state can result in energy loss and reduced battery life. The Penryn processor supports intelligent heuristics to recognize when Deep Power Down energy cost is greater than the idle period savings and it demotes OS Deep Power Down requests to C4 state.

2 Responses to Penryn Update

This is probably off topic, I intended on asking this question on the micro-architecture of processors in the slashdot article, but its closed, and well I’m having trouble finding a real email address for any of you big brained people.. Seriously though I think its a good question …
Email me directly if its off topic, I’ve just always wanted this answered.
I’ve always been perplexed at how you can increase pipelining and shrink the core die size at the same, when you just shrink the core, you are reducing the overall area of the circuit, but doesn’t the actually density of electrons increase? Then you add in features like pipelineing and now you have a processor that was 50% full of electrons 100% of the time and now its 90% full 100% of the time, so my question (assuming my hypothesis is correct) How does one actually regulate the instruction set/pipelining to reduce the amount/density of electrons for a set average over time? (for heat control) Or has this become an issue yet?
On a more anecdotal thought, when does the die size shrink so far, that you start employing quantum tunneling to transfer electrons ?