4096 times the input frequency PWM clock signal, counts up (Q three ), until the base is full ICi-IC3 (sweet day), the output point d a MAX clock signal, which on the one hand

the voltage data loaded into IClr rIC3, leaving the other dare steady Ics flip, Q ugly, namely, the number is in the state count down, and then began to count down until the point a fork outputs a MIN the clock signal period, the signal voltage on the one hand the data reloaded ICi ~ ICz, on the one hand to the bistable flip IC5 original state, and counts up, and thereafter repeat the above process. voltage data values and subtraction of the pulse count port number is the same liquid on PWM demodulation, the smoothing filter Ri, Rz and cl, C2 turn into a DC voltage, high input impedance amplifier OP is also magnified by 2 times and then converted into o ~ + iov voltage.