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Solution

1

After running the design through FPGA Express an error similar to the following may appear:

ERROR:basmm:227 - LUT4 symbol "ct_top_logic/y_side_macro/u_SLV3232/C4393" (output signal=ct_top_logic/y_side_macro/u_SLV3232/C3451) has an equation that uses an input pin connected to a trimmed signal. Make sure that all the pins used in the equation for this LUT have signals that are not trimmed (see trim report for details on which signals were trimmed).

This is a bug in FPGA Express v3.3 and below. While this is supposed to be updated in Express v3.4, it is possible to get around this problem. This error is typically caused by FPGA Express trimming part of the code but not all of it. A common cause for this problem is a signal that is defined, but is not driven. This signal would then be passed through components. FPGA Express trims the signal but keeps the equations in which the signal is supposed to be.

To get around this, the netlist must be traced by identifying the LUT in question (C4393 in the above case). If you trace this LUT back to find all its source nets and see what equations are going into that LUT and the corresponding LUT before, you can gain a lot of insight to the code that needs to be fixed. Once the code is identified, verify that all signals in the equation in question have been assigned a value.

2

This error is caused when some driver-less signals are trimmed away by MAP, which leaves the LUT inputs un-driven.

Run the design through MAP again with trimming disabled (-u switch); then, examine the result in FPGA Editor to determine the cause of the sourceless nets that are the root of the problem.