A bidirectional transient voltage suppression (TVS) diode consisting of specially designed multi-junctions was developed using low temperature (LT) epitaxy and fabrication processes. Its electrostatic discharge (ESD) performance was investigated using I-V, C-V, and various ESD tests including the human body model (HBM), machine model (MM) and IEC 61000-4-2 (IEC) analysis. The symmetrical structure with very sharp and uniform bidirectional multi-junctions yields good symmetrical I-V behavior over a wide range of operating temperature of 300 K-450 K and low capacitance as 6.9 pF at 1 MHz. In addition, a very thin and heavily doped layer enabled I-V curves steep rise after breakdown without snapback phenomenon, then resulted in small dynamic resistance as , and leakage current completely suppressed down to pA. Manufactured bidirectional TVS diodes were capable of withstanding kV of MM and kV of IEC, and exceeding kV of HBM, while maintaining reliable I-V characteristics. Such an excellent ESD performance of low capacitance and dynamic resistance is attributed to the abruptness and very unique profiles designed very precisely in multi-junctions.

In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (VTH) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted silicon-on-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmented-channel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

In this paper, we discuss on the optimal design scheme of the bilayer OLED (Organic Light Emitting Diodes) with micro-cavity structure. We carried out the optical simulation on the OLED device and calculated optimal scale of devices with taking the micro-cavity effect into account. Our emission model is based upon an ensemble of radiating dipole antennas. Consequently, we applied Maxwell`s equation to this sequence, followed by the analysis on the electrical behaviors of OLED device using Poisson`s equation. It contains carrier injection and transportation mechanism. In this process, we found out the thickness of each layer can affect the recombination rate at the emission layer. Therefore, we optimized the thickness of each layer to improve the efficiency of the device.

In this paper, we report our numerical simulation on the electronic-optical properties of the phosphorescent organic light emitting diodes (PHOLEDs) devices. In order to calculate the electrical and optical characteristics such as the transport behavior of carriers, recombination kinetics, and emission property, we undertake the finite element method (FEM). Our model includes Poisson`s equation, continuity equation to account for behavior of electrons and holes and the exciton continuity/transfer equation. We demonstrate that the refractive indexes of each material affect the emission property and the barrier height of the interface influences the behavior of charges and the generation of exciton.

This paper discusses the 3-level charge pumping (CP) method in planar-type Silicon-Oxide-High-k-Oxide-Silicon (SOHOS) and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) devices to find out the reason of the degradation of data retention properties. In the CP technique, pulses are applied to the gate of the MOSFET which alternately fill the traps with electrons and holes, thereby causing a recombination current Icp to flow in the substrate. The 3-level charge pumping method may be used to determine not only interface trap densities but also capture cross sections as a function of trap energy. By applying this method, SOHOS device found to have a higher interface trap density than SONOS device. Therefore, degradation of data retention characteristics is attributed to the many interface trap sites.

In this paper, film deposited by thermal atomic layer deposition (ALD) with diluted instead of was suggested for passivation layer and anti-reflection (AR) coating of the p-type crystalline Si (c-Si) solar cell application. It was confirmed that the deposition rate and refractive index of film was proportional to the concentration. film deposited with 5 % has the greatest negative fixed oxide charge density (), which can be explained by aluminum vacancies () or oxygen interstitials () under O-rich condition. film deposited with 5 % condition also shows lower interface trap density () distribution than those of other conditions. At 5 % condition, moreover, film shows the highest excess carrier lifetime () and the lowest surface recombination velocity (), which are linked with its passivation properties. The proposed film deposited with diluted is very promising for passivation layer and AR coating of the p-type c-Si solar cell.

In this paper, scaling down characteristics of vertical channel phase random access memory are investigated with device simulator and finite element analysis simulator. Electrical properties of select transistor are obtained by device simulator and those of phase change material are obtained by finite element analysis simulator. From the fusion of both data, scaling properties of vertical channel phase change random access memory (VPCRAM) are considered with ITRS roadmap. Simulation of set reset current are carried out to analyze the feasibility of scaling down and compared with values in ITRS roadmap. Simulation results show that width and length ratio of the phase change material (PCM) is key parameter of scaling down in VPCRAM. Thermal simulation results provide the design guideline of VPCRAM. Optimization of phase change material in VPCRAM can be achieved by oxide sidewall process optimization.

Different kinds of post-deposition annealing (PDA) by a rapid thermal process (RTP) are used to enhance the field-effect passivation of film in crystal Si solar cells. To characterize the effects of PDA on and the interface, metal-insulator semiconductor (MIS) devices were fabricated. The effects of PDA were characterized as functions of RTP temperature from and RTP time from 30~120 s. A high temperature PDA can retard the passivation of thin film in c-Si solar cells. PDA by RTP at results in better passivation than a PDA at in forming gas ( 4% in ) for 30 minutes. A high thermal budget causes blistering on film, which degrades its thermal stability and effective lifetime. It is related to the film structure, deposition temperature, thickness of the film, and annealing temperature. RTP shows the possibility of being applied to the PDA of film. Optimal PDA conditions should be studied for specific films, considering blistering.

With the extreme ultraviolet (EUV) lithography, the performance limit of chemically amplified resists has recently been extended to 16- and 11-nm nodes. However, the line edge roughness (LER) and the line width roughness (LWR) are not reduced automatically with this performance extension. In this paper, to investigate the impacts of the EUVL mask and the EUVL exposure process on LER, EUVL is modeled using multilayer-thin-film theory for the mask structure and the Monte Carlo (MC) method for the exposure process. Simulation results demonstrate how LERs of the mask transfer to the resist and the exposure process develops the resist LERs.

A nano-power CMOS voltage reference is proposed in this paper. Through a combination of switched-capacitor technology with the body effect in MOSFETs, the output voltage is defined as the difference between two gate-source voltages using only a single PMOS transistor operated in the subthreshold region, which has low sensitivity to the temperature and supply voltage. A low output, which breaks the threshold restriction, is produced without any subdivision of the components, and flexible trimming capability can be achieved with a composite transistor, such that the chip area is saved. The chip is implemented in standard CMOS technology. Measurements show that the output voltage is approximately 123.3 mV, the temperature coefficient is , and the line sensitivity is 0.15 %/V. When the supply voltage is 1 V, the supply current is less than 90 nA at room temperature. The area occupation is approximately .

This paper presents a capacitive readout circuit for tri-axes microaccelerometer with sub-fF offset calibration capability. A charge sensitive amplifier (CSA) with correlated double sampling (CDS) and digital to equivalent capacitance converter (DECC) is proposed. The DECC is implemented using 10-bit DAC, charge transfer switches, and a charge-storing capacitor. The DECC circuit can realize the equivalent capacitance of sub-fF range with a smaller area and higher accuracy than previous offset cancelling circuit using series-connected capacitor arrays. The readout circuit and MEMS sensing element are integrated in a single package. The supply voltage and the current consumption of analog blocks are 3.3 V and , respectively. The sensitivities of tri-axes are measured to be 3.87 mg/LSB, 3.87 mg/LSB and 3.90 mg/LSB, respectively. The offset calibration which is controlled by 10-bit DECC has a resolution of 12.4 LSB per step with high linearity. The noise levels of tri-axes are /Hz, /Hz and /Hz, respectively.

In this work we have synthesized ZnS:Mn nanocrystals (NCs) using a simple one step thermochemical method. and were used as the precursors and was the source of impurity. Thioglycolic acid (TGA) was used as the capping agent and the catalyst of the reaction. The structure and optical property of the NCs were characterized by means of X- ray diffraction (XRD), HRTEM, UV-visible optical spectroscopy and photoluminescence (PL). X-ray diffraction (XRD) and transmission electron microscopy (TEM) analyses demonstrated cubic phase ZnS:Mn NCs with an average size around 3 nm. Synthesized NCs exhibited band gap of about 4 eV. Photoluminescence spectra showed a yellow-orange emission with a peak located at 585 nm, demonstrating the Mn incorporation inside the ZnS particles.

In high-/metal-gate (HK/MG) metal-oxide-semiconductor field-effect transistors (MOSFETs) at 45-nm and below, the metal-gate material consists of a number of grains with different grain orientations. Thus, Monte Carlo (MC) simulation of the threshold voltage () variation caused by the workfunction variation (WFV) using a limited number of samples (i.e., approximately a few hundreds of samples) would be misleading. It is ideal to run the MC simulation using a statistically significant number of samples (>~); however, it is expensive in terms of the computing requirement for reasonably estimating the WFV-induced variation in the HK/MG MOSFETs. In this work, a simple matrix model is suggested to implement a computing-inexpensive approach to estimate the WFV-induced variation. The suggested model has been verified by experimental data, and the amount of WFV-induced variation, as well as the lowering is revealed.

Low noise amplifier (LNA) is an integral component of RF receiver and frequently required to operate at wide frequency bands for various wireless system applications. For wideband operation, important performance metrics such as voltage gain, return loss, noise figure and linearity have been carefully investigated and characterized for the proposed LNA. An inductive shunt feedback configuration is successfully employed in the input stage of the proposed LNA which incorporates cascaded networks with a peaking inductor in the buffer stage. Design equations for obtaining low and high impedance-matching frequencies are easily derived, leading to a relatively simple method for circuit implementation. Careful theoretical analysis explains that input impedance can be described in the form of second-order frequency response, where poles and zeros are characterized and utilized for realizing the wideband response. Linearity is significantly improved because the inductor located between the gate and the drain decreases the third-order harmonics at the output. Fabricated in CMOS process, the chip area of this wideband LNA is , including pads. Measurement results illustrate that the input return loss shows less than -7 dB, voltage gain greater than 8 dB, and a little high noise figure around 6-8 dB over 1.5 - 13 GHz. In addition, good linearity (IIP3) of 2.5 dBm is achieved at 8 GHz and 14 mA of current is consumed from a 1.8 V supply.

This paper presents a high-efficiency digital class-D audio amplifier using a composite interpolation filter for portable audio devices. The proposed audio amplifier is composed of an interpolation filter, a delta-sigma modulator, and a class-D output stage. To reduce power consumption, the designed interpolation filter has an optimized composite structure that uses a direct-form symmetric and Lagrange FIR filters. Compared to the filters with homogeneous structures, the hardware cost and complexity are reduced by about half by the optimization. The coefficients of the digital delta-sigma modulator are also optimized for low power consumption. The class-D output stage has gate driver circuits to reduce shoot-through current. The implemented class-D audio amplifier exhibited a high efficiency of 87.8 % with an output power of 57 mW at a load impedance of and a power supply voltage of 1.8 V. An outstanding signal-to-noise ratio of 90 dB and a total harmonic distortion plus noise of 0.03 % are achieved for a single-tone input signal with a frequency of 1 kHz.

The fabrication and characterization of a Si/ZnO thin film heterojunction ultraviolet photodiode has been presented in this paper. ZnO thin film of ~100 nm thick was deposited on <100> Silicon (Si) wafer by atomic layer deposition (ALD) technique. The Photoluminescence spectroscopy confirms that as-deposited ZnO thin film has excellent visible-blind UV response with almost no defects in the visible region. The room temperature current-voltage characteristics of the n-ZnO thin film/p-Si photodiodes are measured under an UV illumination of at 365 nm in the applied voltage range of . The current-voltage characteristics demonstrate an excellent UV photoresponse of the device in its reverse bias operation with a contrast ratio of ~ 1115 and responsivity of ~0.075 A/W at 2 V reverse bias voltage.

In highly reliable and durable systems, failures due to aging might result in catastrophes. Aging monitoring techniques to prevent catastrophes by predicting such a failure are required. This paper presents a scan-based on-line aging monitoring scheme which monitors aging during normal operation and gives an alarm if aging is detected so that the system users take action before a failure occurs. We illustrate our modified scan chain architecture and aging monitoring control method. Experimental results show our simulation results to verify the functions of the proposed scheme.

A 120 GHz voltage controlled oscillator (VCO) with a divider chain including an injection locked frequency divider (ILFD) and six static frequency dividers is demonstrated using 65-nm CMOS technology. The VCO is designed based on the LC cross-coupled push-push structure and operates around 120 GHz. The 60 GHz ILFD at the first stage of the frequency divider chain is based on a similar topology as the core of the VCO to ensure the frequency alignment between the two circuit blocks. The static divider chain is composed of D-flip flops, providing a 64 division ratio. The entire circuit consumes a DC power of 68.5 mW with the chip size of .