First of all I would like to thank almighty GOD who has given this wonderful gift of life to us. He is the one who is guiding us in right direction to follow noble path of humanity. In my six months industrial training it is a wonderful experience to be a part of NETMAX TECHNOLOGIES. Where I have opportunity to work under brilliant minds. I owe my deep regards for the supporting and kind staff authorities who are helping me in my lean patches during these six months. The knowledge I am gaining throughout my studies have the practical implementation during this period. I am grateful to all the staff of NETMAX and for their timely support and sharing of their experience with me. I would like to express my heartiest concern for Er.ROHIT KHOSLA & Er.Harmesh lal for able guidance and for inspiring attitude, praiseworthy attitude and honest support. Not to forget the pain staking efforts of our college training and placement cell and specially my training and placement officer Mr. NAVEEN GARG. Last but not the least I would express my utmost regards for the electronics and communication department of our Institute.

COMPANY PROFILE Netmax Technologies is an organization which is established in the field of Network Support, Network training and Embedded systems. We provide Support and training in the field of networking solutions (CISCO, LINUX) and embedded systems (Micro controller based design, Electronics system design). In Education we have strategic alliance with REDHAT Inc. We are also NOVELL EDUCATION PARTNER with which we provide NOVELL and SUSE LINUX courses. Netmax technologies also conduct courses in CADENCE based design tools. Netmax Technologies also provide Technical Research & Development support and consultancy to some Electronics companies. Our clients for R&D support in field of embedded systems. 1) 2) 3) 4) 5) Recorders and Medicare ltd Chandigarh. TELEBOX India ltd. Lotus Machines Pvt. Ltd. Chandigarh. Impearl Electronics Pvt. Ltd. Chandigarh. KANTA Electrical Ltd. Mohali.

14) 15) 16) 17)

BBMB The Tribune Quark Ind Swift

OUR TEAM Presently we have a strong technical team of certified professionals for catering to these solutions and have presence in Chandigarh and Punjab. We have skilled team of engineers who are experienced in design, programming. We are having more than 10 engineers who are having prestigious certifications like ccna, ccnp, ccse, mcse and RHCE. Support Area (network solutions) a) LINUX / UNIX networks b) SUN networks c) CISCO devices (Routers, Switches, Firewalls, Cache Engine, RAS etc) d) Bandwidth Manager software and hardware e) Radio Links f) Security Solutions

Netmax Technologies is a leader in education services and developer of innovative embedded solutions. To meet the demands of Post PC era Netmax provides complete solutions as well as design-to-order services to satisfy our customers. For Netmax Technologies

Rohit khosla

PCB DESINING PCB stands for PRINTED CIRCUIT BOARD. Printed circuit board (PCB) provides both the physical structure for mounting and holding the components as well as the electrical interconnection between the components. That means a PCB = PWB (printed wiring board) is the platform upon which electronic components such as integrated circuit chips and other components are mounted. A PCB consists of a non-conducting substrate (typically fiber glass with epoxy as resin) upon which the conductive pattern or circuitry is formed. Copper is the most prevalent conductor although nickel, silver and tin are also used in some cases. Types of PCB PCB may be of different types:1) Single-sided 2) Double-sided 3) Multilayer Single sided PCBs: - As the name suggest in these designs the conductive pattern is only at in one side. And also the size is large in these case but these are cheap. Double sided PCBs: - These are the PCBs on which the conductive pattern is in on both sides. The size of board is small in this case but it is costlier than that of above. Multilayer PCBs: - In this case the board consists of alternating layers of conducting pattern and insulating material. The conductive material is connected across the layers through plated through holes. The size of this PCB is smaller than that of double sided PCB but it is very costly.

PCBs may also be either rigid, flexible, or the combination of two (rigid-flex). When the electronic components have been mounted on the PCB, the combination of PCB and components is an electronic assembly, also called PRINTED CIRCUIT ASSEMBLY. This assembly is the basic building block for all the electronic appliances such as television, computer and other goods.

FUNCTIONS OF PCB Printed circuited boards are dielectric substrates with metallic circuitry formed on that. They are some times referred to as the base line in electronic packaging. Electronic packaging is fundamentally an inter connection technology and the PCB is the baseline building block of this technology.

TECHNIQUE USED FOR PCB DESIGN There mainly two techniques which are use for the PCB designs. 1. Hand Taping2. Computer Aided Design

1) PCBs using Hand Taping: o PCB design using hand taping is the process of technical drawing. o In hand taping method layout should be prepared on grid paper. o In hand taping, components pads can be prepared by using black pads. o Routing of the board can be done by tapes with different widths.

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Each layer (top, bottom) has to prepare separately. DISADVANTAGS OF HAND-TAPING FOR PCB DESINING: o Each layer has to be designed separately. o We cannot generate NCD files for CNC drilling. o Difficult to modify the design in the designing process or after designing. o Difficult to get good design overview. 2) PCB DESIGNING USING CAD All the above difficulties can be removed by using CAB system. CAD system for PCB designing requires following: o A computer system. o PCB design software like OrCad, CADSTAR, Protel, TANGO, Mentor etc. o A photo plotter for art work generation. There are many enhanced features in electronics design automation tools which not possible in the hand taping. The main advantages are given below: o Auto placement o Auto routing o After routing, optimization of tracks can be done. o Provides physical design reuse modules o Electrical rule check (ERC) o All the layers are generated from the same design by giving different options.

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o Bill of material can be generated which contains number of different components used. o We can draw conductors as an arc, semi-circular at different angles. o Design Rule Check o Advanced CAD systems have high speed analysis. o CAD system provides all NCD files and Gerber data files for photo plotting.

BASIC DESIGN STEPS IN CAD- SYSTEM The following design steps are very common while designing a PCD in CAD: Entry the schematic diagram. Net list file creation. Placement of components manually or automatically. Routing of the board using manual routing tools or auto router Design rule check physical and electrical. Artwork generation.

A TRADITIONAL DESIGN FLOW IN CAD- SYSTEM

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Capture

Gerber tools

Gerber and plotter drawing

Libraries Layout Footprint libraries

Gerber and drill files

PCB Design Softwares There many soft wares which are used for PCB designs. Some of them are given below: OrCad CADSTAR Protel TANGO Mentor

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The most commonly software which are used for PCB design in India are Protel and OrCad

OrCad Design Environment OrCad has a long history of providing individuals and teams with a complete set of technologies that offer unprecedented productivity, seamless tool integration, and exceptional value. New 10.5 release continues that tradition. Today's lower cost and yet highly sophisticated electronic design automation systems have created a unique challenge to nearly every engineering department. Therefore the use of EDA tools has become increasingly important as product lifecycles have become shorter and shorter. Modern electronic design automation (EDA) tools are beginning to support a more efficient and integrated approach to electronic.OrCad Capture design entry is the most widely used schematic entry system in electronic design today for one simple reason: fast and universal design entry. Whether you're designing a new analog circuit, revising schematic diagram for an existing PCB, or designing a digital block diagram with an HDL module, OrCad Capture provides simple schematic commands you need to enter, modify and verify the design for PCB. OrCad Layout offers PCB designers and PCB design teams the power and flexibility to create and share PCB data and constraints across the design flow. OrCad Layout delivers all the capabilities to designers need from netlist to place and route, to final output. The ease-of use and intuitive capabilities of OrCad Layout provides for quick startup and rapid learning right out of the box.

The Schematic Page Editor: The schematic page editor is used to display and edit schematic pages. So that one can parts; wires; buses and draw graphics. The schematic page editor has a tool palette that you can use to draw and place everything you need to create a schematic page. One can print from within the schematic page editor, or from the project window.

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The Part editor: The part editor is used to create and edit parts. From the view menu of the part editor you can choose either part or package. In part view one can: Create and edit parts and symbols, then store in new or existing libraries. Create and edit power and ground symbols, off-page connector symbols, and title block Use the tool palettes electrical tools to place pins on parts, and its drawing tools to draw parts and symbols. The Session Log: The session log lists the events that have occurred during the current Capture session, includes message resulting from using captures tools. To display context-sensitive help for an error message, put the cursor in the error message line in the session log press F1.16

The ruler along the top appears in either inches or mill meters, depending on which measurement system is selected in the window panel. Your tab setting are saved and used each time you start capture.

One can search for information in the session log using the find command on the Edit menu. You can also save the contents of the of the session log to a file, which is useful when working with Orcads technical support to solve technical problems. The default filename is SESSION.TXT. The Toolbar: Captures toolbar is dock able (that means you can select and drag the toolbar to new location) as well as resizable, and displays tool tips for each tool; by choosing a tool button you can quickly perform a task. If tool button is dimmed, you cant perform that task in the current situation.

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Some of the tools operate only on what you have selected, while others give you a choice of either operating on what is selected or expanding the scope to entire project. You can hide the toolbar, then display it again when u need it. For hiding select from the schematic page editors view menu, choose TOOLBAR.

The Tool Palette: Capture has two tool palettes: one for the schematic page editor and one for the part editor. Both tool palettes are dock able and resizable. They can also display tool tips that identify each tool. The drawing tools on the two tool palettes are identical, however, each tool palette has different electrical tools after you choose a tool, and you press the right mouse button to display a context- sensitive pop-up menu. The schematic page editor tool palette: The first group of tools on the tool palette is electrical tools, used to place electrical connectivity objects. The second group of tools is Drawing tools, used to create graphical objects without electrical connectivity.

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The part editor tool palette: The first group of tools on the part palette is electrical tools, used to place pins and symbols. They have been already explained above within the schematic page editor tools. The second group of tools is drawing tools, used to create graphical objects without objects any electrical connectivity and is described: Pin Tools: Place pins on part Pin Array: Place multiple pins on part Selecting and deselecting of objects Once one selects an object, one can perform operations on it, include moving, copying, cutting, mirroring, rotating, resizing, or editing. One can also select multiple, objects and edit them, or group them in to a single object. Grouping objects maintain relation ship among them while one moves them to another location.

Creating Net list File Net-list file is a document file which contains information about the logical interconnections between signals and pins. Before one create a net list file, be sure ones project is completed, annotated and it is free from electrical rule violations. A net list file consists of nets, components, connectors, junctions, no connection symbol, power and ground symbols.

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Creation of net list in capture: Select your design in the project manager. From the tools, choose create net list. The net list dialog box displays. Choose a net list format tab. If necessary, set the part value and PCB foot print combined property strings to reflect the information you want in the net list. Click ok to create the net list. In the net list file text box, enter a name for the output file. If the selected format creates an additional file, enter its file name in the second text box.

PLACEMENT OF LAYOUT PLUS What is Layout Plus? Layout plus is one part for the PCB design in which we place as well as route the components an set unit of measurement, grids, and spacing in OrCad. Within other soft wares you also have to place and route the components in similar way. For the placement and routing of the components we normally use auto-placement and auto-routing. Unfortunately, in a lot of soft wares some critical signals have to be routed manually before auto-routing. In layout plus we also define the layer stacks, pad stacks and via's.

Steps for board design: At first, we have created a net list from our schematic diagram by using capture.

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Layout plus includes design rules in order to guide logical placement and routing. That means, load the net list into layout to create the board. At the same time you have to specify the board parameters. Specify board parameters: Specifying global setting for the board, including nits of measurements, grid, and spacing Place components: Use the components tool in order to place manually the components which are fixed by the system designer on the board or otherwise use auto-placement. Route the board: Use different routing technologies to route the board and take advantage of push and shove (a routing technology), which moves track you are currently routing as well as you can also auto route the board. Provide finishing of the board: Layout supplies an ordered progression of commands on the auto menu for finishing your design. These commands include design rule check, cleanup design, rename components, back annotate, run post processor, and create reports. The design window: The design window provides a graphical display of printed circuit board, it is primary window you use when designing your board. It also provides tools to facilitate the design process such as to update components and design rule violation.

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Main window

Method to create a board with Layout Plus: Ensure that net list with all footprints and necessary information has been created. Create a directory in which the schematic design, net list, and boar will co-exit and put the schematic design and net list. OrCad provides a directory for this purpose. From the layout session frames file menu, choose New. The load template file in the dialog box displayed.

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Design window Select the technology template (.TCH), then choose the open button and load the net list in other box. Then apply the auto ECO. If necessary, respond to link footprints to component dialog. Draw the board outline by using the obstacle tool in the tool bar. Setting board parameters: There is some parameter which should be set before placing the components on board. They are as follows: Set Datum Create a board outline23

Set units of measurements Set system grid Add mount holes Creating of board outline: Board outline is the graphical representation of the size of the actual PCB board. So it is the main step in layout, to draw the board outline of the actual size of PCB board. Placement of components: Placement of components means that to place the components in designed box. A designer should follow the following steps before going for it: Optimize the board for component placement. Load the placement strategy file. Place components on the board. Optimize placement using various placements Components can be placed by using two techniques:1) Manual placement of components 2) Auto placement of components Choose the components tool bar button. From the pop up men, choose the queue for placement. The components selection criteria dialog box appears. Enter the reference designator of the components that you want to place in the appropriate text box, and click ok. Drag the components to desired location, place it there.

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Conductor Routing in Layout:After placing all the components the other main step is to route the board from the electrical connections between the components. One may route board manually or automatically by auto router. 100% auto routing can be achieved only when components are placed in the order of functional flow of electronic circuit. The main routing tool available in OrCad is as flow: Add/edit route mode Edit segment mode Shove track mode Auto path route mode

Design Rule Check:In manual designs every thing was checked as a possible source of error. Components sizes, hole sizes, conductor widths and clearance, land-to-hole-ratio, board areas to be free of components, clearance to the edges, positional accuracy and of course electrical interconnections had tad to be personally reviewed with a great deal of care. After completing the design of printed circuit board with the help of an EDA-Tool, a designer has again to verify the PCB in order to find out errors. Such type of verifications/design rule check contains beside the general verifications commonly two types: Physical verification Electrical verification

Post processing:Post processing can be done once the design is completed in all aspects. The common way is still a process to generate GERBER data and NCD files which can be used for photo plotting and for steps of CNC manufacturing and PCB- drilling.25

POWER SYSTEM DESIGN First part of electronics ckts. is power. The main power supply is in AC but mostly electronic ckts. work with DC. So a system is required to convert ac to dc and these sources should able to produce stable supplies. Power supplies may be used in. may be of different types such as regulated, unregulated, smps etc. Unregulated power supplies These are the power supplies in which the out put is not constant. That it is varies with input voltage, load, and also effected by the environment conditions such as temperature, etc. so these are the variable supplies. Commonly these supplies are not employed as there efficiency is very less. The unregulated power can be obtained using rectifying circuit after AC supply. Regulated power supplies These are the power supplies in which the output voltage is constant, i.e. the out put voltage is independent of the input voltage, load and other external conditions. So to obtain the regulated voltage using different regulators. The regulator voltage is mainly the DC voltage, it may AC to or DC to DC voltage. A better approach to power supply design is to use enough capacitance to reduce ripple to low level, then use an active feedback circuit to eliminate the remaining ripple and dependence of output voltage on input, load and environment conditions. These active devices are known as Regulators. These regulators can be used to produce negative and positive voltage of required value. The voltage regulators are of three types:1) Constant positive voltage regulators 2) Constant negative voltage regulators

3) Variable voltage regulators

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Constant positive voltage regulators:-

These are the regulators which are able to

produce positive and constant voltage. Some of them are given below:S. no. Name of regulator Output voltage 1 LM 7805 5v 2 LM 7810 10v 3 LM 7812 12v 4 LM 7815 15v These regulators are used according to the required voltage need. Constant negative voltage regulators:- These are also the constant output voltage regulator but there output is negative in polarity. These regulators are also employed according to voltage requirements. Some of them are given below with there outputs:S. no 1 2 3 4 Name of regulator LM7905 LM7910 LM7912 LM7915 Output voltage -5v -10v -12v -15v

Variable voltage regulators:- These are the regulator whose output voltage can be varied according to the desired need. These regulators again of two types i.e.: Positive Negative The output of these regulators can be varied by varying the resistance of the variable resistance which is connected to the adjustable pin the regulators. So these are the most commonly used regulators in the electronic industry as wide range of stable voltage can be obtained from single chip by varying the resistance connected to the adjustable pin of the regulators. The most commonly variable regulators are:-

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LM317 (it is positive regulator) LM 337(it is negative regulator) There description is given below:LM317 3-Terminal Adjustable Regulator:General Description: The LM317 series of adjustable 3-terminal positive voltage regulators is capable of supplying in excess of 1.5A over a 1.2V to 37V output range. They are exceptionally easy to use and require only two external resistors to set the output voltage. Further, both line and load regulation is better than standard fixed regulators. Also, the LM117 is packaged in standard transistor packages which are easily mounted and handled. In addition to higher performance than fixed regulators, theLM317 series offers full overload protection available only in ICs. Included on the chip are current limit, thermal overload protection and safe area protection. All overload protection circuitry remains fully functional even if the adjustment terminal is disconnected. Normally, no capacitors are needed unless the device is situated more than 6 inches from the input filter capacitors in which case an input bypass is needed. An optional output capacitor can be added to improve transient response. The adjustment terminal can be bypassed to achieve very high ripple rejection ratios which are difficult to achieve with standard voltage, supplies of several hundred volts can be regulated as long as the maximum input to output differential is not exceeded, i.e., avoid short-circuiting the output. Also, it makes an especially simple adjustable switching regulator, a programmable output regulator, or by connecting a fixed resistor between the adjustment pin and output, theLM317 can be used as a precision current regulator. Supplies with electronic shutdown

Application Hints: In operation, the LM317 develops a nominal 1.25V reference voltage, VREF, between the output and adjustment terminal. The reference voltage is impressed across program resistor R1 and, since the voltage is constant, constant current I1 then flows through the output set resistor R2, giving an output voltage of

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Since the 100A current from the adjustment terminal represents an error term, the LM317 was designed to minimize IADJ and make it very constant with line and load changes. To do this, all quiescent operating current is returned to the output establishing a minimum load current requirement. If there is insufficient load on the output, the output will rise.

PROTECTION DIODES:When external capacitors are used with any IC regulator it is sometimes necessary to add protection diodes to prevent the capacitors from discharging through low current points into the regulator. Most 10F capacitors have low enough internal series resistance to deliver 20A spikes when shorted. Although the surge is short, there is enough energy to damage parts of the IC. When an output capacitor is connected to a regulator and the input is shorted, the output capacitor will discharge into the output of the regulator. The discharge current depends on the value of the capacitor, the output voltage of the regulator, and the rate of decrease of VIN. In the LM317, this discharge path is through a large junction that is able to sustain 15A surge with no problem. This is not true of other types of

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positive regulators. For output capacitors of 25F or less, there is no need to use diodes.

The bypass capacitor on the adjustment terminal can discharge through a low current junction. Discharge occurs when either the input or output is shorted. Internal to the LM317 is a 50 esistor which limits the peak discharge current. No protection is needed r for output voltages of 25V or less and 10F capacitance. Figure 3 shows an LM317 with protection diodes included for use with outputs greater than 25V and high values of output capacitance.32

LM337

3-Terminal Adjustable Regulator:-

General Description: The LM337 is adjustable 3-terminal negative voltage regulators capable of supplying in excess of 1.5A over an output voltage range of 1.2V to 37V. These regulators are exceptionally easy to apply, requiring only 2 external resistors to set the output voltage and 1 output capacitor for frequency compensation. The circuit design has been optimized for excellent regulation and low thermal transients. Further, the LM337 series features internal current limiting, thermal shutdown and safe-area compensation, making them virtually blowout-proof against overloads. The LM337 serves a wide variety of applications including local on-card regulation, programmable-output voltage regulation or precision current regulation. The LM337 are ideal complements to the LM317 adjustable positive regulators.

These two Ic's i.e. LM337and LM317are mainly used in the regulated power supplies because using these regulator a wide range of output can be obtain which can be varied from 0v to 30v, which is much sufficient to drive any electronic circuit. On next page there is diagram of the bench supply which is generally used to test the instrument in the labs. This circuit is capable of producing positive and negative output voltage.

SWITCH MODE POWER SUPPLY The switch mode regulated power supply is increasing in popularity because it offers the advantages of higher power conversion efficiency and increased design flexibility (multiple output voltages of different polarities can be generated from a single input voltage). This paper will detail the operating principles of the four most commonly used switching converter types: Buck: used to reduce a DC voltage to a lower DC voltage. Boost: provides an output voltage that is higher than the input. Buck-Boost (invert): an output voltage is generated opposite in polarity to the input. Flyback: an output voltage that is less than or greater than the input can be generated, as well as multiple outputs. Switching Fundamentals: Before beginning explanations of converter theory, some basic elements of power conversion will be presented:

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TRANSFORMER OPERATION: A transformer is a device that has two or more magnetically-coupled windings. The action of a transformer is such that a time-varying (AC) voltage or current is transformed to a higher or lower value, as set by the transformer turns ratio The basic operation is shown in Figure:-

. The transformer does not add power, so it follows that the power (V X I) on either side must be constant. That is the reason that the winding with more turns has higher voltage but lower current, while the winding with less turns has lower voltage but higher current. The dot on a transformer winding identifies its polarity with respect to another winding, and reversing the dot results in inverting the polarity. Example of Transformer Operation: An excellent example of how a transformer works can be found under the hood of your car, where a transformer is used to generate the 40 kV that fires your cars spark plugs as in fig.

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The "coil" used to generate the spark voltage is actually a transformer, with a very high secondary-to-primary turns ratio. When the points first close, current starts to flow in the primary winding and eventually reaches the final value set by the 12V battery and the current limiting resistor. At this time, the current flow is a fixed DC value, which means no voltage is generated across either winding of the transformer. When the points open, the current in the primary winding collapses very quickly, causing a large voltage to appear across this winding. This voltage on the primary is magnetically coupled to (and stepped up by) the secondary winding, generating a voltage of 30 kV - 40 kV on the secondary side. As explained previously, the law of inductance says that it is not possible to instantly break the current flowing in an inductor (because an infinite voltage would be required to make it happen). This principle is what causes the arcing across the contacts used in switches that are in circuits with highly inductive loads. When the switch just begins to open, the high voltage generated allows electrons to jump the air gap so that the current flow does not actually stop instantly. Placing a capacitor across the contacts helps to reduce this arcing effect. In the automobile ignition, a capacitor is placed across the points to minimize damage due to arcing when the points "break" the current flowing in the low-voltage coil winding

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PULSE WIDTH MODULATION (PWM):All of the switching converters that will be covered in this paper use a form of output voltage regulation known as Pulse Width Modulation (PWM). Put simply, the feedback loop adjusts (corrects) the output voltage by changing the ON time of the switching element in the converter. As an example of how PWM works, we will examine the result of applying a series of square wave pulses to an L-C filter (see Figure).

The series of square wave pulses is filtered and provides a DC output voltage that is equal to the peak pulse amplitude multiplied times the duty cycle (duty cycle is defined as the switch ON time divided by the total period). This relationship explains how the output voltage can be directly controlled by changing the ON time of the switch. Switching Converter Topologies The most commonly used DC-DC converter circuits will now be presented along with the basic principles of operation.

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BUCK REGULATOR: The most commonly used switching converter is the Buck, which is used to down-convert a DC voltage to a lower DC voltage of the same polarity. This is essential in systems that use distributed power rails (like 24V to 48V), which must be locally converted to 15V, 12V or 5V with very little power loss. The Buck converter uses a transistor as a switch that alternately connects and disconnects the input voltage to an inductor (see Figure).

Buck regulator The lower diagrams show the current flow paths (shown as the heavy lines) when the switch is on and off. When the switch turns on, the input voltage is connected to the inductor. The difference between the input and output voltages is then forced across the inductor, causing current through the inductor to increase. During the on time, the inductor current flows into both the load and the output capacitor (the capacitor charges during this time). When the switch is turned off, the input voltage applied to the inductor is removed.

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However, since the current in an inductor can not change instantly, the voltage across the inductor will adjust to hold the current constant. The input end of the inductor is forced negative in voltage by the decreasing current, eventually reaching the point where the diode is turned on. The inductor current then flows through the load and back through the diode. The capacitor discharges into the load during the off time, contributing to the total current being supplied to the load (the total load current during the switch off time is the sum of the inductor and capacitor current). The shape of the current flowing in the inductor is similar to Figure:-

As explained, the current through the inductor ramps up when the switch is on, and ramps down when the switch is off. The DC load current from the regulated output is the average value of the inductor current. The peak-to-peak difference in the inductor current waveform is referred to as the inductor ripple current, and the inductor is typically selected large enough to keep this ripple current less than 20% to 30% of the rated DC current.

CONTINUOUS vs. DISCONTINUOUS OPERATION In most Buck regulator applications, the inductor current never drops to zero during fullload operation (this is defined as continuous mode operation). Overall performance is usually better using continuous mode, and it allows maximum output power to be obtained from a given input voltage and switch current rating. In applications where the maximum43

load current is fairly low, it can be advantageous to design for discontinuous mode operation. In these cases, operating in discontinuous mode can result in a smaller overall converter size (because a smaller inductor can be used). Discontinuous mode operation at lower load current values is generally harmless, and even converters designed for continuous mode operation at full load will become discontinuous as the load current is decreased

BOOST REGULATOR The Boost regulator takes a DC input voltage and produces a DC output voltage that is higher in value than the input (but of the same polarity). The Boost regulator is shown in Figure, along with details showing the path of current flow during the switch on and off time.

Boost regulator Whenever the switch is on, the input voltage is forced across the inductor which causes the current through it to increase (ramp up). When the switch is off, the decreasing inductor current forces the "switch" end of the inductor to swing positive. This forward biases the diode, allowing the capacitor to charge up to a voltage that is higher than the input voltage. During steady-state operation, the

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inductor current flows into both the output capacitor and the load during the switch off time. When the switch is on, the load current is supplied only by the capacitor. OUTPUT CURRENT AND LOAD POWER An important design consideration in the Boost regulator is that the output load current and the switch current are not equal, and the maximum available load current is always less than the current rating of the switch transistor. It should be noted that the maximum total power available for conversion in any regulator is equal to the input voltage multiplied times the maximum average input current (which is less than the current rating of the switch transistor). Since the output voltage of the Boost is higher than the input voltage, it follows that the output current must be lower than the input current.

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BUCK-BOOST (INVERTING) REGULATOR The Buck-Boost or Inverting regulator takes a DC input voltage and produces a DC output voltage that is opposite in polarity to the input. The negative output voltage can be either larger or smaller in magnitude than the input voltage.

Buck- boost regulator When the switch is on, the input voltage is forced across the inductor, causing an increasing current flow through it. During the on time, the discharge of the output capacitor is the only source of load current. This requires that the charge lost from the output capacitor during the on time be replenished during the off time. When the switch turns off, the decreasing current flow in the inductor causes the voltage at the diode end to swing negative. This action turns on the diode, allowing the current in the inductor to supply both the output capacitor and the load. As shown, the load current is supplied by inductor when the switch is off, and by the output capacitor when the switch is on.

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in

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4 D U C T O RC 1 1 0 0 3 2 1 4 5 6 T 1 0 L 2 6 1 I N S 1 5 7 4 7 6 3

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Buck- Boost regulator

FLYBACK REGULATOR

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The Flyback is the most versatile of all the topologies, allowing the designer to create one or more output voltages, some of which may be opposite in polarity. Flyback converters have gained popularity in battery-powered systems, where a single voltage must be converted into the required system voltages (for example,+5V, +12V and -12V) with very high power conversion efficiency. The basic single-output flyback converter is shown in Figure:-

The most important feature of the Flyback regulator is the transformer phasing, as shown by the dots on the primary and secondary windings. current When the switch is on, the input voltage is forced across the transformer primary which causes an increasing flow of

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through it. Note that the polarity of the voltage on the primary is dot-negative (more negative at the dotted end), causing a voltage with the same polarity to appear at the transformer secondary (the magnitude of the secondary voltage is set by the transformer secondary-to-primary turns ratio). The dot-negative voltage appearing across the secondary winding turns off the diode, preventing current flow in the secondary winding during the switch on time. During this time, the load current must be supplied by the output capacitor alone. When the switch turns off, the decreasing current flow in the primary causes the voltage at the dot end to swing positive. At the same time, the primary voltage is reflected to the secondary with the same polarity. The dot-positive voltage occurring across the secondary winding turns on the diode, allowing current to flow into both the load and the output capacitor. The output capacitor charge lost to the load during the switch on time is replenished during the switch off time. Flyback converters operate in either continuous mode (where the secondary current is always >0) or discontinuous mode.L 3 2 1 1 0 T R A 1 SC 1 20 13 8 1 9 1 0 0 0 u F 5 0 V 3 6 3 M B R 1 0 C 1 4 0 2 5 0 2 NT 1_ 4 H M 1 2 3 2 1 0 u F / T O 5 3 1

GENERATING MULTIPLE OUTPUTS Another big advantage of a Flyback is the capability of providing multiple outputs (see Figure). In such applications, one of the outputs (usually the highest current) is selected to provide PWM feedback to the control loop, which means this output is directly regulated. The other secondary winding(s) are indirectly regulated, as their pulse widths will follow the regulated winding. The load regulation on the unregulated secondary is not great (typically 5 - 10%), but is adequate for many applications. If tighter regulation is needed on the lower current secondary, an LDO post-regulator is an excellent solution. The secondary voltage is set about 1V above the desired output voltage, and the LDO provides excellent output regulation with very little loss of efficiency.

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Typical multiple output fly back ANALOG SYSTEM:OP-AMP The op-amp was originally designed to carry out mathematical operations in analogue computers, such as bombsights, but was soon recognized as having many other applications.

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The op-amp usually comes in the form of an 8 pin integrated circuit, the most common one being the type 741. It has two inputs and one output. The input marked with a - sign produces an amplified inverted output. The input marked with a + sign produces an amplified but non inverted output. The op-amp requires positive and negative power supplies, together with a common ground. Some circuits can be designed to work from a single supply. If the two inputs are joined together, then the output voltage should be midway between the two supply rails, i.e. zero volts

If the input voltage is higher than the reference voltage, then the output is negative. If the input voltage is lower than the reference, then the output is positive. The gain can be set by negative feedback.

OP 07 GENERAL DESCRIPTION The OP07 has very low input offset voltage (75 max for OP07E) which is obtained by V trimming at the wafer stage. These low offset voltages generally eliminate any need for external nulling. The OP07 also features low input bias current (4 nA for OP07E) and high open-loop gain (200 V/mV for OP07E). The low offsets and high open-loop gain make the OP07 particularly useful for high-gain instrumentation applications. The wide input voltage range of 13 V minimum combined with high CMRR of 106 dB (OP07E) and high input impedance provides high accuracy in the non-inverting circuit configuration. Excellent linearity and gain accuracy can be maintained even at high closed-loop gains. Stability of offsets and gain with time or variations in temperature is excellent. The accuracy and stability of the OP07, even at high gain, combined with the freedom from external nulling have made the OP07 an industry standard for instrumentation applications. The OP07 is available in two standard performance grades. The OP07E is specified for operation over the 0C to 70C range, and OP07C over the 40C to +85C temperature range. The OP07 is available in epoxy 8-lead Mini-DIP and 8-lead SOIC. It is a direct replacement for 725,108A, and OP05 amplifiers; 741-types may be directly replaced by removing the 741s nulling potentiometer.

Two op-amp design Three op- amp design AD620 AD620 is an instrumentation amplifier with three OP-amp designs. The AD620 is a low cost, high accuracy instrumentation amplifier that requires only one external resistor to set gains of 1 to 1000. Furthermore, the AD620 features 8-lead SOIC and DIP packaging that is smaller than discrete designs, and offers lower power (only 1.3 mA max supply current), making it a good fit for battery powered, portable PIN DIAGRAM:

(Or remote) applications. The AD620, with its high accuracy of 40 ppm maximum nonlinearity, low offset voltage of 50 max and offset drift of 0.6 max, is V V/ C ideal for use in precision data acquisition systems, such as weigh scales and transducer interfaces. Furthermore, the low noise, low input bias current, and low power of the AD620 make it well suited for medical applications such as ECG and noninvasive blood pressure monitors. The low input bias current of 1.0 nA max is made possible with the use of Superbeta processing in the input stage. The AD620 works well as a preamplifier due to its low input voltage noise of 9 nV/ Hz at 1 kHz, 0.28 V p-p in the 0.1 Hz to 10 Hz band, 0.1 pA/Hz input current noise. Also, the AD620 is well suited for multiplexed applications with its settling time of 15 s to 0.01% and its cost is low enough to enable designs with one inamp per channel.

EXCELLENT AC SPECIFICATIONS: 120 kHz Bandwidth (G = 100) 15 ms Settling Time to 0.01% THEORY OF OPERATION: The AD620 is a monolithic instrumentation amplifier based on a modification of the classic three op amp approach. Absolute value trimming allows the user to program gain accurately (to 0.15% at G = 100) with only one resistor. Monolithic construction and laser wafer trimming allow the tight matching and tracking of circuit components, thus ensuring the high level of performance inherent in this circuit. The input transistors Q1 and Q2 provide a single differential pair bipolar input for high precision (Figure 33), yet offer 10 lower Input Bias Current thanks to Superbeta processing. Feedback through the Q1-A1-R1 loop and the Q2-A2-R2 loop maintains constant collector current of the input devices Q1, Q2 thereby impressing the input voltage across the external gain setting resistor RG. This57

creates a differential gain from the inputs to the A1/A2 outputs given by G = (R1 + R2)/RG + 1. The unity-gain subtracter A3 removes any common-mode signal, yielding a single-ended output referred to the REF pin potential. The value of RG also determines the transconductance of the preamp stage. As RG is reduced for larger gains, the transconductance increases asymptotically to that of the input transistors. This has three important advantages: (a) Open-loop gain is boosted for increasing programmed gain, thus reducing gain related errors. (b) The gain-bandwidth product (determined by C1, C2 and the preamp transconductance) increases with programmed gain, thus optimizing frequency response. (c) The input voltage noise is reduced to a value of 9 nV/Hz, determined mainly by the collector current and base resistance of the input devices. The internal gain resistors, R1 and R2, are trimmed to an absolute value of 24.7 k , allowing the gain to be programmed accurately with a single external resistor. The gain equation is then

The thyristor is also known as the silicon controlled rectifier (S.C.R.). It has the same characteristics as the diode, current flowing from cathode to anode, when the anode is positive with respect to the cathode

. However, it will only do this when the gate is also positive with respect to the cathode. In the circuit, with the switch open as shown, no current flows. When the switch is closed, the diode begins to conduct and current flows from cathode to anode. There is a problem. If the switch is now opened, current continues to flow. Conduction can be stopped by removing the cathode/anode voltage. Another method of stopping current flow is to reverse the polarity of the cathode/anode voltage. If the thruster is used with an ac supply then it will conduct on the positive half cycles and automatically switch off during the negative half cycles. The resistor in series with the gate connection limits the gate current to a safe value.

TRIAC AND DIAC:

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The triac conducts in both directions and provides full wave control of power. Variable phase trigger pulses are provided by the pulse generator and are positive with respect b1. The diac is high resistance below a certain voltage, say 30 volts, but when the applied voltage exceeds this value, it goes low resistance and conducts, applying a pulse to the gate. It gives more reliable triggering of the triac. Control of the Thyristor

To obtain full wave operation, so that the lamp can be provided with the full ac supply voltage, two thyristors are required as shown. Th1 is triggered during the positive half cycles of the ac supply, and Th2 during the negative half cycles. The waveforms show the thyristors being triggered halfway through each half cycle and the current through the lamp would be the sum of the two currents. The lamp will be at about half brightness

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A pulse generator and a phase shift circuit is necessary to provide gate pulses which can adjust the power from minimum to maximum. Since the gate voltages have to be positive with respect to the cathodes, attention must be paid to the polarity of the gating pulses with respect each other. The high power ac circuit can be isolated from the control circuits by means of transformers or opto isolators.

Multivibrators: Multivibrators (sometimes called FLIP-FLOPS) have two "cross coupled" transistors, say TR1 and TR2. This causes TR1 to be on (conducting) and TR2 off. They can be made to reverse states, with TR1 turning off and TR2 turning on. Multivibrators are of mainly two types Astable multivibrator Monostable multivibrator

555 timer DESCRIPTION The 555 monolithic timing circuit is a highly stable controller capable of producing accurate time delays, or oscillation. In the time delay mode of operation, the time is precisely controlled by one external resistor and capacitor. For a stable operation as an oscillator, the free running frequency and the duty cycle are both accurately controlled with two external resistors and one capacitor. The circuit may be triggered and reset on falling waveforms, and the output structure can source or sink up to 200 mA. PIN DIAGRAM

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FEATURES Turn-off time less than 2 s Max. operating frequency greater than 500 kHz Timing from microseconds to hours Operates in both astable and monostable modes Operates in both astable and monostable modes High output current Adjustable duty cycle TTL compatible Temperature stability of 0.005% per C APPLICATIONS Precision timing Pulse generation Sequential timing Time delay generation Pulse width modulationEMBEDDED SYSTEM

What is Embedded System? Embedded system employs a combination of software & hardware to perform a specific function. It is a part of a larger system which may not be a computerWorks in a reactive & time constrained environment. Any electronic system that uses a CPU chip, but that is not a general-purpose workstation, desktop or laptop computer is known as embedded system. Such systems generally use microprocessors; microcontroller or they may use custom-designed chips or both. They are used in automobiles, planes, trains, space vehicles, machine tools,

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cameras, consumer and office appliances, cell phones, PDAs and other handhelds as well as robots and toys. The uses are endless, and billions of microprocessors are shipped every year for a myriad of applications. In embedded systems, the software is permanently set into a read-only memory such as a ROM or flash memory chip, in contrast to a general-purpose computer that loads its programs into RAM each time. Sometimes, single board and rack mounted generalpurpose computers are called "embedded computers" if used to cont Embedded System Applications : Consumer electronics, e.g., cameras, cell phones etc. Consumer products, e.g. washers, microwave ovens etc. Automobiles (anti-lock braking, engine control etc.) Industrial process controller & defense applications. Computer/Communication products, e.g. printers, FAX machines etc. Medical Equipments. ATMs Aircrafts

DIFFERENCE BETWEEN MICROPROCESSORS AND MICROCONTROLLERS: A Microprocessor is a general purpose digital computer central processing unit(C.P.U) popularly known as CPU on the chip. The Microprocessors contain no RAM, no ROM, and no I/P O/P ports on the chip itself. On the other hand a Microcontroller has a C.P.U(microprocessor) in addition to a fixed amount of RAM, ROM, I/O ports and a timer all on a single chip.

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In order to make a Microprocessor functional we must add RAM, ROM, I/O Ports and timers externally to them,i.e any amount of external memory can be added to it.

But in controllers there is a fixed amount of memory which makes them ideal for many applications. The Microprocessors have many operational codes(opcodes) for moving data from external memory to the C.P.U Whereas Microcontrollers may have one or two operational codes.

DISADVANTAGES OF MICROPROCESSORS OVER MICROCONTROLLERS System designed using Microprocessors are bulky They are expensive than Microcontrollers We need to add some external devices such as PPI chip, Memory, Timer/counter chip, Interrupt controller chip,etc. to make it functional.

Types of microcontroller architecture: There are two types of Microcontroller architecture designed for embedded system development. These are: 1)RISC- Reduced instruction set computer 2)CISC- Complex instruction set computer Difference between CISC and RISC: CISC stands for Complex Instruction Set Computer. Most PC's use CPU based on this architecture. For instance Intel and AMD CPU's are based on CISC architectures.64

Typically CISC chips have a large amount of different and complex instructions. In common CISC chips are relatively slow (compared to RISC chips) per instruction, but use little (less than RISC) instructions. MCS-51 family microcontrollers based on CISC architecture. RICS stands for Reduced Instruction Set Computer. The philosophy behind it is that almost no one uses complex assembly language instructions as used by CISC, and people mostly use compilers which never use complex instructions. Therefore fewer, simpler and faster instructions would be better, than the large, complex and slower CISC instructions. However, more instructions are needed to accomplish a task. Atmells AVR microcontroller based on RISC architecture. History of 8051 Intel Corporation introduced an 8-bit microcontroller called 8051 in 1981 this controller had 128 bytes of RAM, 4k bytes of on chip ROM, two timers, one serial port, and four ports all are on single chip. The 8051 is an 8 bit processor, meaning that the CPU can work on only 8 bit data at a time. Data larger than 8 bits broken into 8 bit pieces to be processed by CPU. It has for I/O 8 bit wide. Features of the 8051:Feature ROM RAM Timer I/O pins Serial port Interrupt sources 8051 Architecture Overview The 8051 family is one of the most common microcontroller architectures used worldwide. 8051 based microcontrollers are offered in hundreds of variants from many different silicon manufacturers. The 8051 is based on an 8-bit CISC core with Harvard architecture. It's an 8-bit CPU, optimized for control applications with extensive Boolean processing (single-bit logic Quantity 4K bytes 128 bytes 2 32 1 6

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capabilities), 64K program and data memory address space and various on-chip peripherals. The 8051 microcontroller family offers developers a wide variety of high-integration and cost-effective solutions for virtually every basic embedded control application. From traffic control equipment to input devices and computer networking products, 8051 microcontrollers deliver high performance together with a choice of configurations and options matched to the special needs of each application. Whether it's low power operation, higher frequency performance, expanded on-chip RAM, or an application-specific requirement, there's a version of the 8051 microcontroller that's right for the job. When it's time to upgrade product features and functionality, the 8051 architecture puts you on the first step of a smooth and cost-effective upgrade path - to the enhanced performance of the 151 and 251 microcontrollers

Block diagram of 8051

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Internal Architecture of 8051

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Pin configuration of 8051

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There are four ports P0, P1, P2 and P3 each use 8 pins, making them 8-bit ports. All the ports upon RESET are configured as output, ready to be used as output ports. To use any of these ports as an input port, it must be programmed. Port 0:- Port 0 occupies a total of 8 pins (pins 32-39) .It can be used for input or output. To use the pins of port 0 as both input and output ports, each pin must be connected externally to a 10K ohm pull-up resistor. This is due to the fact that P0 is an open drain, unlike P1, P2, and P3.Open drain is a term used for MOS chips in the same way that open collector is used for TTL chips. With external pull-up resistors connected upon reset, port 0 is configured as an output port. For example, the following code will continuously send out to port 0 the alternating values 55H and AAH MOV A,#55H BACK: MOV P0,A ACALL DELAY CAPL A SJMP BACK Port 0 as input:- With resistors connected to port 0, in order to make it an input, the port must be programmed by writing 1 to all the bits. In the following code, port 0 is configured first as an input port by writing 1's to it, and then data is received from the port and sent to P1.

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MOV A,#0FFH MOV P0,A BACK: MOV A,P0 MOV P1,A SJMP BACK

; A = FF hex ; make P0 an input port ;get data from P0 ;send it to port 1

Dual Role of Port 0 :-Port 0 is also designated as AD0-AD7, allowing it to be used for both address and data. When connecting an 8051/31 to an external memory, port 0 provides both address and data. The 8051 multiplexes address and data through port 0 to save pins. ALE indicates if P0 has address or data. When ALE = 0, it provides data D0-D7, but when ALE =1 it has address and data with the help of a 74LS373 latch. Port 1:- Port 1 occupies a total of 8 pins (pins 1 through 8). It can be used as input or output. In contrast to port 0, this port does not need any pull-up resistors since it already has pull-up resistors internally. Upon reset, Port 1 is configured as an output port. For example, the following code will continuously send out to port1 the alternating values 55h

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& AAh

MOV A,#55H BACK: MOV P1,A

; A = 55 hex ;send it to Port 1 ;call delay routine

ACALL DELAY CPL A SJMP BACK ;make A=0

Port 1 as input:-To make port1 an input port, it must be programmed as such by writing 1 to all its bits. In the following code port1 is configured first as an input port by writing 1s to it, then data is received from the port and saved in R7 ,R6 & R5. MOV A,#0FFH ;A=FF HEX MOV P1,A MOV A,P1 MOV R7,A ACALL DELAY MOV A,P1 MOV R6,A ACALL DELAY MOV A,P1 MOV R5,A ;make P1 an input port by writing all 1s to it

;get data from P1 ;save it in register R7 ;wait ;get another data from P1 ;save it in register R6 ;wait ;get another data from P1 ;save it in register R5

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Port 2 :-Port 2 occupies a total of 8 pins (pins 21- 28). It can be used as input or output. Just like P1, P2 does not need any pull-up resistors since it already has pull-up resistors internally. Upon reset,Port 2 is configured as an output port. For example, the following code will send out continuously to port 2 the alternating values 55h and AAH. That is all the bits of port 2 toggle continuously. MOV A,#55H BACK: MOV P2,A ACALL DELAY CPL A SJMP BACK Port 2 as input:- To make port 2 an input, it must programmed as such by writing 1 to all its bits. In the following code, port 2 is configured first as an input port by writing 1s to it. Then data is received from that port and is sent to P1 continuously. MOV A,#0FFH MOV P2,A BACK: MOV A,P2 MOV P1,A SJMP BACK ;A=FF hex ;make P2 an input port by writing all 1s to it ;get data from P2 ;send it to Port1 ;keep doing that ; A = 55 hex ;send it to Port ;call delay routine ;make A=0

Dual role of port 2:- In systems based on the 8751, 8951, and DS5000, P2 is used as simple I/O. However, in 8031-based systems, port 2 must be used along with P0 to provide the 16-bit address for the external memory. As shown in pin configuration 8051, port 2 is also designed as A8-A15, indicating the dual function. Since an 8031 is capable of accessing 64K bytes of external memory, it needs a path for the 16 bits of the address.73

While P0 provides the lower 8 bits via A0-A7, it is the job of P2 to provide bits A8-A15 of the address. In other words, when 8031 is connected to external memory, P2 is used for the upper 8 bits of the 16 bit address, and it cannot be used for I/O. Port 3:- port 3 occupies a total of 8 pins, pins 10 through 17. It can be used as input or output. P3 does not need any pull-up resistors, the same as P1 and P2 did not. Although port 3 is configured as an output port upon reset. Port 3 has the additional function of providing some extremely important signals such as interrupts. This information applies both 8051 and 8031 chips. There functions are as follows:PORT 3 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Function RxD TxD ___ Int0 ___ Int1 T0 T1 ___ WR ___ RD pin 10 11 12 13 14 15 16 17

P3.0 and P3.1 are used for the RxD and TxD serial communications signals. Bits P3.2 and P3.3 are set aside for external interrupts. Bits P3.4 and P3.5 are used for timers

0 and 1. Finally P3.6 and P3.7 are used to provide the WR and RD signals of external memories connected in 8031 based systems. Read modify write features:The ports in the 8051 can be accessed by the read-modify-write technique. This feature saves many lines of code by combining in a single instruction all three action of (1) reading the port, (2) modifying it, and (3) writing to the port. The following code first places 01010101 (binary) into port 1. Next, the instruction XLR P1,#0FFH performs an XOR logic operation on P1 with 1111 1111 (binary), and then writes the result back into P1. MOV P1,#55H

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AGAIN: XLR P1,#0FFH ACALL DELAY SJMP AGAIN Notice that XOR of 55H and FFH gives AAH. Likewise, the XOR of AAH and FFH gives 55H. Single bit addressability of ports:There are times that we need to access only 1 or 2 bits of the port instead of the entire 8 bits. A powerful feature of 8051 I/O ports is their capability to access individual bits of the port without altering the rest of the bits in that port. For example, the following code toggles the bit p1.2 continuously. BACK: CPL P1.2 ACALL DELAY SJMP BACK Notice that P1.2 is the third bit of P1, since the first bit is P1.0, the second bit is P1.1, and so on. Notices in example of those unused portions of port1 are undisturbed. Table bellow shows the bits of 8051 I/O ports. This single bit addressability of I/O ports is one of the features of the 8051 microcontroller. ; complement p1.2 only

Single bit addressability of ports:

PORT 0

PORT 1

PORT 275

PORT 3

PORT BIT

P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7

P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7

P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7

P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7

D0 D1 D2 D3 D4 D5 D6 D7

AT89s52 AT89S8252 is an ATMEL controller with the core of intel MCS-51. It has same pin configuration as give above. The AT89S8252 is a low-power, high-performance CMOS 8-bit microcomputer with 8K bytes of Downloadable Flash programmable and erasable read only memory and 2K bytes of EEPROM. The device is manufactured using Atmels high density nonvolatile memory technology and is compatible with the industry standard 80C51 instruction set and pinout. The on-chip Downloadable Flash allows the program memory to be reprogrammed insystem through an SPI serial interface or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Downloadable Flash on a monolithic chip, the Atmel AT89S8252 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. The AT89S8252 provides the following standard features: 8K bytes of Downloadable Flash, 2K bytes of EEPROM, 256 bytes of RAM, 32 I/O lines, programmable watchdog timer, two Data Pointers, three 16-bit timer/counters, a six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89S8252 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. The Downloadable Flash can be changed a single byte at a time and is accessible through the SPI serial interface. Holding RESET active forces the SPI bus into a serial programming interface and allows the program memory to be written to or read from unless Lock Bit 2 has been activated.

Low Power Idle and Power Down Modes Interrupt Recovery From Power Down Programmable Watchdog Timer Dual Data Pointer Power Off Flag

Pin Description Furthermore, P1.4, P1.5, P1.6, and P1.7 can be configured as the SPI slave port select, data input/output and shift clock input/output pins as shown in the following table.

Port 1 also receives the low-order address bytes during Flash programming and verification.

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by78

the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that uses 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during Flash programming and verification. Port 3 Port 3 is an 8 bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various special features of the AT89S8252, as shown in the following table. Port 3 also receives some control signals for Flash programming and verification.

RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. ALE/PROG

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Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In normal operation, ALE is emitted at a constant rate of 1/ 6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. PSEN Program Store Enable is the read strobe to external program memory. When the AT89S8252 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12volt programming enable voltage (VPP) during Flash programming when 12-volt programming is selected. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier.

Hardware interfacings and programming There are two types of programming language used for microcontroller programming:80

1)Low Level Language(Assembly Language) 2) High Level Language(C Language)_ We have used high level language for microcontroller programming due to its given advantages over assembly: Advantages of C over Assembly language programming:

Knowledge of the processor instruction set is not required.

Details like register allocation and addressing of memory and data is managed by the compiler.

Programs get a formal structure and can be divided into separate functions.

Programming and program test time is drastically reduced, this increases efficiency. Keywords and operational functions can be used that come closer to how humans think. The supplied and supported C libraries contain many standard routines such as numeric conversions. Reusable code: Existing program parts can be more easily included into new programs, because of the comfortable modular program construction techniques. The C language based on the ANSI standard is very portable. Existing programs can be quickly adapted to other processors as needed.

2)Hardware interfacing of LCD(JHD162A): On most displays, the pins are numbered on the LCDs printed circuit board, but if not, it is quit easy to locate pin1. Since the pin is connected to ground, it often has a thicker PCB track connected to it, and it is generally connected to the metal work at some point.

The function of each of the connections is shown in the table below:Pins 1 & 2 are the power supply lines, Vss & Vdd. The Vdd pin should be connected to the positive supply & Vss to the 0V supply or ground. Although the LCD module data sheets specify 5V D.C. supply (at only a few milliamps), supplies of 6V & 4.5V both work well, and even 3V is sufficient for some modules. Consequently, these modules can be effectively and economically powered by batteries. Pin 3 is a control pin, Vee, which is used to alter the contrast of the display. Ideally, these pin should be connected to a variable voltage supply. A preset potentiometer connected between the power supply lines, with its wiper connected to the contrast pin is suitable in many cases, but be aware that some modules may require a negative potential; as low as 7V in some cases. For absolute simplicity, connecting this pin to 0V will often suffice.

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Pin 4 is register select (RS) line.

PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14

NAME Vss Vdd Vee RS R/W E D0 D1 D2 D3 D4 D5 D6 D7

Three command control inputs. When this line is low, data bytes transferred to the display are treated as commands, and data bytes read from the display indicate its status. By setting the RS line high, character data can be transferred to and from the module. Pin 5 is (R/W) line. This line is pulled low in order to write commands or character data to the module, or pulled high to read character data or status information from its registers. Pin 6 is Enable (E) line. This input is used to initiate the actual transfer of commands or character data between the module and the data lines. When writing to the display, data is transferred only on the high to low transition of this signal. However, when reading from the display, data will become available shortly after the low to high transition and remain available until the signal falls low again. Pins 7 to 14 are the eight data bus lines (D0 to D7). Data can be transferred to and from the display, either as a single 8-bit byte or as two 4-bit nibbles. In the latter case, only86

the upper four data lines (D4 to D7) are used. This $-bit mode is beneficial when using a microcontroller, as fewer I/O lines are required.

3) ADC-0804 interfacing with AT89s52: The ADC0804 family is CMOS 8-Bit, successive-approximation A/D converters which use a modified potentiometer ladder and are designed to operate with the 8080A control bus via three-state outputs. These converters appear to the processor as memory locations or I/O ports, and hence no interfacing logic is required. The differential analog voltage input has good common mode- rejection and permits offsetting the analog zero-input voltage value. In addition, the voltage

4) Interfacing of Real time clock-DS12887 The DS12887 is real-time clocks (RTCs). The devices provide a real-time clock/calendar, one time-of-day alarm, three maskable interrupts with a common interrupt output, a programmable square wave, and 114 bytes of battery backed static. The DS12887 integrates a quartz crystal and lithium energy source into a 24-pin encapsulated DIP package. The DS12C887 adds a century byte at address 32h. For all devices, the date at the end of the month is automatically adjusted for

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months with fewer than 31 days, including correction for leap years. The devices also operate in either 24-hour or 12-hour format with an AM/PM indicator. A precision temperature-compensated circuit monitors the status of Vcc. If a primary power failure is detected, the device automatically switches to a backup supply. A lithium coin-cell battery can be connected to the VBAT input pin on the DS12885 to maintain time and date operation when primary power is absent. The device is accessed through a multiplexed byte-wide interface, which supports both Intel and Motorola mode Pin diagram

ADDRESS MAP The address map of the DS12887 is shown in Figure 2. The address map consists of 114 bytes of user RAM, 10 bytes of RAM that contain the RTC time, calendar, and alarm data, and 4 bytes which are used for control and status. All 128 bytes can be directly written or read except for the following: 1. Registers C and D are readonly.99

2. Bit 7 of Register A is readonly. 3. The high order bit of the seconds byte is readonly. The contents of four registers (A,B,C, and D) are described in the Registers section. ADDRESS MAP DS12887

Register A:UIP 0 DV2 0 DV1 1 DV0 0 RS3 0 RS2 0 RS1 0 RS0 0

UIP The Update In Progress (UIP) bit is a status flag that can be monitored. When the UIP bit is a 1, the update transfer will soon occur. When UIP is a 0, the update transfer will not occur for at least 244 . s The time, calendar, and alarm information in RAM is fully available for access when the UIP bit is 0. The UIP bit is read only and is not affected by RESET . Writing the SET bit in Register B to a 1 inhibits any update transfer and clears the UIP status bit. DV0, DV1, DV2 These 3 bits are used to turn the oscillator on or off and to reset the countdown chain. A pattern of 010 is the only combination of bits that will turn the oscillator on

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and allow the RTC to keep time. A pattern of 11X will enable the oscillator but holds the countdown chain in reset. The next update will occur at 500 ms after a pattern of 010 is written to DV0, DV1, and DV2. RS3, RS2, RS1, RS0 These four rateselection bits select one of the 13 taps on the 15stage divider or disable the divider output. The tap selected can be used to generate an output square wave (SQW pin) and/or a periodic interrupt. The user can do one of the following: 1. Enable the interrupt with the PIE bit; 2. Enable the SQW output pin with the SQWE bit; 3. Enable both at the same time and the same rate; Register B:SET PIE AIE UIE SQWE DM 24/12 DSE

SET When the SET bit is a 0, the update transfer functions normally by advancing the counts once per second. When the SET bit is written to a 1, any update transfer is inhibited and the program can initialize the time and calendar bytes without an update occurring in the midst of initializing. Read cycles can be executed in a similar manner. SET is a read/write bit that is not modified by RESET or internal functions of the DS12887. PIE The periodic interrupt enable PIE bit is a read/write bit which allows the Periodic Interrupt Flag (PF) bit in Register C to drive the IRQ pin low. When the PIE bit is set to 1, periodic interrupts are generated by driving the IRQ pin low at a rate specified by the RS3RS0 bits of Register A. A 0 in the PIE bit blocks the IRQ output from being driven by a periodic interrupt, but the Periodic Flag (PF) bit is still set at the periodic rate. PIE is not modified by any internal DS12887 functions, but is cleared to 0 on RESET . AIE

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The Alarm Interrupt Enable (AIE) bit is a read/write bit which, when set to a 1, permits the Alarm Flag (AF) bit in Register C to assert IRQ . An alarm interrupt occurs for each second that the three time bytes equal the three alarm bytes including a dont care alarm code of binary 11XXXXXX. When the AIE bit is set to 0, the AF bit does not initiate the IRQ signal. The RESET pin clears AIE to 0. The internal functions of the DS12887 do not affect the AIE bit. UIE The Update Ended Interrupt Enable (UIE) bit is a read/ write that enables the Update End Flag (UF) bit in Register C to assert IRQ . The RESET pin going low or the SET bit going high clears to UIE bit. SQWE When the Square Wave Enable (SQWE) bit is set to a 1, a square wave signal at the frequency set by the rateselection bits RS3 through RS0 is driven out on a SQW pin. When the SQWE bit is set to z0, the SQW pin is held low; the state of SQWE is cleared by the RESET pin. SQWE is a read/write bit. DM The Data Mode (DM) bit indicates whether time and calendar information is in binary or BCD format. The DM bit is set by the program to the appropriate format and can be read as required. This bit is not modified by internal functions or RESET . A 1 in DM signifies binary data while a 0 in DM specifies Binary Coded Decimal (BCD) data. 24/12 The 24/12 control bit establishes the format of the hours byte. A 1 indicates the 24hour mode and a 0 indicates the 12hour mode. This bit is read/write and is not affected by internal functions of RESET . DS12887 11 of 19 DSE The Daylight Savings Enable (DSE) bit is a read/write bit which enables two special updates when DSE is set to 1. On the first Sunday in April the time increments from 1:59:59 AM to 3:00:00 AM. On the lastSunday in October when the time first reaches 1:59:59 AM102

6) Interfacing of 8255 PPI chip 82C55A FUNCTIONAL DESCRIPTION The 82C55A is a programmable peripheral interface device designed for use in Intel microcomputer systems. Its function is that of a general purpose I/O component to interface peripheral equipment to the microcomputer system bus. The functional configuration of the 82C55A is programmed by the system software so that normally no external logic is necessary to interface peripheral devices or structures

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Pin Diagram Data Bus Buffer This 3-state bidirectional 8-bit buffer is used to interface the 82C55A to the system data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer. Read/Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups. Ports A, B, and C The 82C55A contains three 8-bit ports (A, B, and C). All can be configured in a wide variety of functional characteristics by the system software but each has its Port A: One 8-bit data output latch/buffer and one 8-bit input latch buffer. Both pull-up'' and pull down'' buses hold devices are present on Port A.116

Port B: One 8-bit data input/output latch/buffer. Only pull-up'' bus hold devices are present on Port B. Port C: One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B. Only ``pull-up'' bus hold devices are present

{ if(INT0==0) { while(1) { P1_0=1; delay(0xffff); P1_0=0; delay(0xffff); } } } void delay(unsigned int i) { while(i!=0) { i--; } } AVR Why the Atmels AVR Microcontroller? Whether a particular requirement needs to be implemented using discrete ICs or PLDs or a microprocessor must be determined by the designer.However, many applications could be suitably implemented using microcontrollers, and a great many of them would benefit from using the AVR as outlined briefly below. We will discuss the AVR features in detail in later chapters, but at this point it may be useful to outline the salient features: 1) RISC architecture with mostly fixed length instructions,load-store memory access and 32 general-purpose registers.120

Pin Descriptions VCC- pin 40Digital supply voltage. GND pin 20 RESET- pin 9 Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 18 on page 45. Shorter pulses are not guaranteed to generate a reset. XTAL1-pin 19 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. XTAL2- pin 20 Output from the inverting Oscillator amplifier. Port A (PA7(32)..PA0(39) ) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega8515 as listed Below: Alternate Functions of Port A Port A has an alternate function as the address low byte and data lines for the ExternalMemory Interface. Port Pin Alternate Function PA7 AD7 (External memory interface address and data bit 7) PA6 AD6 (External memory interface address and data bit 6) PA5 AD5 (External memory interface address and data bit 5) PA4 AD4 (External memory interface address and data bit 4) PA3 AD3 (External memory interface address and data bit 3) PA2 AD2 (External memory interface address and data bit 2) PA1 AD1 (External memory interface address and data bit 1) PA0 AD0 (External memory interface address and data bit 0) Port B (PB7(8)..PB0(1)) Port B is an 8-bit bi-directional I/O port with internal pullup resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink123

and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega8515 as listed Below: Port B Pin Alternate Functions PB7- SCK (SPI Bus Serial Clock) PB6- MISO (SPI Bus Master Input/Slave Output) PB5 -MOSI (SPI Bus Master Output/Slave Input) PB4- SS (SPI Slave Select Input) PB3- AIN1 (Analog Comparator Negative Input) PB2- AIN0 (Analog Comparator Positive Input) PB1 -T1 (Timer/Counter1 External Counter Input) PB0T0- (Timer/Counter0 External Counter Input) OC0 (Timer/Counter0 Output Compare Match Output) SCK Port B, Bit 7 SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB7. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB7. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB7 bit. MISO Port B, Bit 6 MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a Master, this pin is configured as an input regardless of the setting of DDB6. When the SPI is enabled as a Slave, the data direction of this pin is controlled by DDB6. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB6 bit. MOSI Port B, Bit 5 MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a Master, the data direction of this pin is controlled by124

DDB5. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB5 bit. SS Port B, Bit 4 SS: Slave Select input. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB4. As a Slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB4. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB4 bit. AIN1 Port B, Bit 3 AIN1, Analog Comparator Negative input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. AIN0 Port B, Bit 2 AIN0, Analog Comparator Positive input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. T1 Port B, Bit 1 T1, Timer/Counter1 Counter Source. T0/OC0 Port B, Bit 0 T0, Timer/Counter0 Counter Source. OC0, Output Compare Match output: The PB0 pin can serve as an external output for the Timer/Counter0 Compare Match. The PB0 pin has to be configured as an output (DDB0 set (one)) to serve this function. The OC0 pin is also the output pin for the PWM mode timer function. Port C (PC7(28)..PC0(21)) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source

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current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D (PD7(17)..PD0(10)) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega8515 as listed Below: Port D Pin Alternate Function PD7- RD (Read Strobe to External Memory) PD6 -WR (Write Strobe to External Memory) PD5 -OC1A (Timer/Counter1 Output Compare A Match Output) PD4 -XCK (USART External Clock Input/Output) PD3- INT1 (External Interrupt 1 Input) PD2- INT0 (External Interrupt 0 Input) PD1 -TXD (USART Output Pin) PD0 -RXD (USART Input Pin) RD Port D, Bit 7 RD is the External Data memory read control strobe. WR Port D, Bit 6 WR is the External Data memory write control strobe. OC1A Port D, Bit 5 OC1A, Output Compare Match A output: The PD5 pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDD5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. XCK Port D, Bit 4 XCK, USART External Clock. The Data Direction Register (DDD4) controls whether the clock is output (DDD4 set) or input (DDD4 cleared). The XCK pin is active only when USART operates in Synchronous mode.

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INT1 Port D, Bit 3 INT1, External Interrupt source 1: The PD3 pin can serve as an external interrupt source. INT0/XCK1 Port D, Bit 2 INT0, External Interrupt Source 0: The PD2 pin can serve as an external interrupt source. XCK1, External Clock. The Data Direction Register (DDD2) controls whether the clock is output (DDD2 set) or input (DDD2 cleared). TXD Port D, Bit 1 TXD, Transmit Data (Data output pin for USART). When the USART Transmitter is enabled, this pin is configured as an output regardless of the value of DDD1. RXD Port D, Bit 0 RXD, Receive Data (Data input pin for USART). When the USART Receiver is enabled this pin is configured as an input regardless of the value of DDD0. When USART forces this pin to be an input, the pull-up can still be controlled by the PORTD0 bit. Port E(PE2(29)..PE0(31)) Port E is an 3-bit bi-directional I/O port with internal pullup resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega8515 as listed Below: Port E Pin Alternate Function PE2-OC1B (Timer/Counter1 Output Compare B Match Output) PE1 -ALE (Address Latch Enable to External Memory) PE0-ICP (Timer/Counter1 Input Capture Pin) INT2 (External Interrupt 2 Input) Input-output Ports registers: All AVR ports have Read-modify-write functionality when used as genera I/O ports. Direction of separate port pin can be changed. Each pin buffer has symmetric capability to drive and sink source. Pin driver is strong enough to drive LED directly , but it is not recommended. All port pins have selectable pull-up resistors.127

All pins have protection diodes to both VCC and GND. Each port consists of three registers DDRx, PORTx and PINx (where x means port letter). DDRx register selects direction of port pins. If logic one is written to DDRx then port is configured to be as output. Zero means that port is configured as input. If DDRx is written zero and PORTx is written logic 1 then port is configured as input with internal pull-up resistor. Otherwise if PORTx is written to zero, then port is configured as input but pins are set to tri-state and you might need to connect external pull-up resistors.

8-bit Timer/Counter Register Description 1)Timer/Counter Control Register TCCR0 7 6 5 4 3 2 1 0 FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 Bit 7 FOC0: Force Output Compare The FOC0 bit is only active when the WGM00 bit specifies a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is written when operating in PWM mode. When writing a logical one to the FOC0 bit, an immediate Compare Match is forced on the waveform generation unit. The OC0 output is changed according to its COM01:0 bits setting. Note that the FOC0 bit is implemented as a strobe. Therefore it is the value present in the COM01:0 bits that determines the effect of the forced compare. A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0 as TOP. The FOC0 bit is always read as zero. Bit 6, 3 WGM01:0: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes.

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Table 44. Waveform Generation Mode Bit Description(1) Mode WGM01 WGM00 Timer/Counter Mode of Operation TOP of counter 0 0 0 Normal 0xFF Immediate MAX 1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 1 0 CTC OCR0 Immediate MAX 3 1 1 Fast PWM 0xFF TOP MAX Normal Mode The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime. The output compare unit can be used to generate interrupts at some given time. Using the output compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. Clear Timer on Compare Match (CTC) Mode In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0 Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT0) matches the OCR0. The OCR0 defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare

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Match output frequency. It also simplifies the operation of counting external events. For generating a waveform output in CTC mode, the OC0 output can be set to toggle its logical level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM01:0 = 1). The OC0 value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of fOC0 = fclk_I/O/2 when OCR0 is set to zero (0x00). The waveform frequency is defined by the following equation: focn= fclk_i/o 2.N.(1+ocrn) The N variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM01:0 = 3) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0) is cleared on the Compare Match between TCNT0 and OCR0, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that use dualslope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost.131

In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure 39. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0 and TCNT0. The PWM frequency for the output can be calculated by the following equation: fOCnPWM=fclk_i/o N.256 The N variable represents the prescale factor (1, 8, 64, 256, or 1024). Phase Correct PWM Mode The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dualslope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0) is cleared on the Compare Match between TCNT0 and OCR0 while upcounting, and set on the Compare Match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dualslope PWM modes, these modes are preferred for motor control applications. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: fOCnPCPWM= fclk_i/0 N.510 Bit 5:4 COM01:0: Compare Match Output Mode These bits control the Output Compare pin (OC0) behavior. If one or both of the132

7 6 5 4 3 2 1 0 COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 WGM10 Bit 7:6 COM1A1:0: Compare Output Mode for Channel A Bit 5:4 COM1B1:0: Compare Output Mode for Channel B The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respectively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC1A or OC1B pin must be set in order to enable the output driver. When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is dependent of the WGM13:0 bits setting. Table 50 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to a normal or a CTC mode (non-PWM). Compare Output Mode, non-PWM COM1A1/ COM1A0/ 0 disconnected. 0 1 output to 1 to high level). COM1B0 / COM1B1 0 1 0 1 Description Normal port operation, OC1A/OC1B Toggle OC1A/OC1B on Compare Match. Clear OC1A/OC1B on Compare Match (Set low level). Set OC1A/OC1B on Compare Match (Set output

1 counting. Clear downcounting.

Set OC1A/OC1B on Compare Match when upOC1A/OC1B on Compare Match when

Bit 3 FOC1A: Force Output Compare for Channel A Bit 2 FOC1B: Force Output Compare for Channel B The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a nonPWM mode. However, for ensuring compatibility with future devices, these bits must be set to zero when TCCR1A is written when operating in a PWM mode. When writing a logical one to the FOC1A/FOC1B bit, an immediate Compare Match is forced on the waveform

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generation unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare Match (CTC) mode using OCR1A as TOP. Bit 1:0 WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, . Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes.

OCR1A 10 1 ICR1 11 1 OCR1A 12 1 ICR1 13 1 14 1 ICR1 15 1 OCR1A

Bit 7 ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is activated, the input from the Input Capture Pin (ICP1) is filtered. The filter function requires four successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the noise canceler is enabled. Bit 6 ICES1: Input Capture Edge Select This bit selects which edge on the Input Capture Pin (ICP1) that is used to trigger a capture139

event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture. When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled. Bit 5: Reserved Bit This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero when TCCR1B is written. Bit 4:3 WGM13:2: Waveform Generation Mode See TCCR1A Register description. Bit 2:0 CS12:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter,

c)Output Compare Register 1 A OCR1AH and OCR1AL OCR1A[15:8] OCR1AH OCR1A[7:0] OCR1AL d)Output Compare Register 1 B OCR1BH and OCR1BL OCR1B[15:8] OCR1BH OCR1B[7:0] OCR1BL The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC1x pin. The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers Analog Comparator: The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparators output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle. Analog Comparator Control and Status Register ACSR141

7 6 5 4 3 2 1 0 ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 Bit 7 ACD: Analog Comparator Disable When this bit is written a logic one, the power to the Analog Comparator is switched off. This bit can be set at any time to turn off the Analog Comparator. This will reduce power consumption in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. Bit 6 ACBG: Analog Comparator Bandgap Select When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Comparator. See Internal Voltage Reference on page 49. Bit 5 ACO: Analog Comparator Output The output of the Analog Comparator is synchronized and then directly connected to ACO. The synchronization introduces a delay of 1 - 2 clock cycles. Bit 4 ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing Bit 3 ACIE: Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator interrupt is activated. When written logic zero, the interrupt is disabled. Bit 2 ACIC: Analog Comparator Input Capture Enable142

When written logic one, this bit enables the Input Capture function in Timer/Counter1 to be triggered by the Analog Comparator. The comparator output is in this case directly connected to the Input Capture front-end logic, making the comparator utilize the noise canceler and edge select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection between the Analog Comparator and the Input Capture function exists. To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set. Bits 1, 0 ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 72. When changing the ACIS1/ACIS0 bits, the Analog Comparator interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the bits are changed. . ACIS1/ACIS0 Settings ACIS1 ACIS0 Interrupt Mode 0 0 Comparator Interrupt on Output Toggle 0 1 Reserved 1 0 Comparator Interrupt on Falling Output Edge 1 1 Comparator Interrupt on Rising Output Edge Hardware Interfacing & Programming Tool used for AVR microcontroller programming : Compiler-winAVR Hex code downloader-ISP programmer Simulator-AVR studio(pony prog) Port programming Port as output: C code for blinking LED connected on PORTB