Hardware Description Language : Structure and Simulation

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Hardware Description Language is a formal language for the operations of integrated circuits, their design and software based simulations. Hardware description languages ??express a temporal behavior and/or a (spatial) Circuit structure in normal text. Unlike software programming languages ??HDLs include syntax and semantics in their notation to express temporal sequences and co-existences. Languages, whose sole characteristic is to reproduce compounds of circuits are referred to as net list languages. Netlists can be either physical or logical; either instance-based or net-based; and flat or hierarchical. The latter can be either folded or unfolded.

An HDL is grossly similar to a software programming language, but there are major differences. Many programming languages are inherently procedural (single-threaded), with limited syntactical and semantic support to handle concurrency. HDLs, on the other hand, resemble concurrent programming languages in their ability to model multiple parallel processes (such as flipflops and adders) that automatically execute independently of one another.

Hardware Description Language : Structure

Regular (and incorrectly) the term programming is used synonymously for writing a hardware description. This results from the fact that HDLs represent an executable specification of a particular hardware. A simulation program that provides the basic semantics of the language and the passage of time, gives the hardware designer the ability to model a piece of hardware before being physically prepared. This possibility of execution makes it look as if to use this language to program something. There are Hardware Description Languages and simulators for modeling in digital and analog technology.

One reason for the use of a general Hardware Description Language is the possibility of automatic generation of net lists for integrated circuits by a tool. Programmable devices such as Field Programmable Gate Arrays (FPGAs) or application specific integrated circuits (ASICs) can realize. For the synthesis of the circuit , the generation of a netlist, typically only a part, based on the syntax and semantic, are suitable. In the field of digital circuit preferably logic synthesis is applied. The remaining parts of the language are suitable for simpler modeling a test environment for verification of the functionality in simulation programs. In the early days of logic synthesis digital multiplications were not directly synthesized. The available tools started to dominate from 2008.

The following levels of abstraction are used:

Behavioral model, partly has no synthesis capability

Register Transfer Level ( RTL model, synthesis capability)

Gate level model (netlist)

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VHDL was based on the Ada programming language, as well as on the experience gained with the earlier development of ISPS. Initially, Verilog and VHDL were used to document and simulate circuit designs already captured and described in another form (such as schematic files). HDL simulation enabled engineers to work at a higher level of abstraction than simulation at the schematic level, and thus increased design capacity from hundreds of transistors to thousands.

Hardware Description Language : Simulation

Using the proper subset of hardware description language, a program called a synthesizer, or logic synthesis tool, can infer hardware logic operations from the language statements and produce an equivalent net list of generic hardware primitives to implement the specified behavior. Synthesizers generally ignore the expression of any timing constructs in the text. Digital logic synthesizers, for example, generally use clock edges as the way to time the circuit, ignoring any timing constructs. The ability to have a synthesizable subset of the language, does not itself make a hardware description language.

Essential to HDL design is the ability to simulate HDL programs. Simulation allows an HDL description of a design (called a model) to pass design verification, an important milestone that validates the design’s intended function (specification) against the code implementation in the HDL description. It also permits architectural exploration. The engineer can experiment with design choices by writing multiple variations of a base design, then comparing their behavior in simulation. Thus, simulation is critical for successful HDL design.

Modern HDL simulators have full-featured graphical user interfaces, complete with a suite of debug tools. These allow the user to stop and restart the simulation at any time, insert simulator breakpoints (independent of the HDL code), and monitor or modify any element in the HDL model hierarchy. Modern simulators can also link the HDL environment to user-compiled libraries, through a defined PLI/VHPI interface. Linking is system-dependent (Win32/Linux/SPARC), as the HDL simulator and user libraries are compiled and linked outside the HDL environment.