2) Memory address decoding
Design a decoding circuit for a 2048x4 memory system. One K of the 4-bit words is at hex addresses 1800-1bFF. The other half of the memory is at locations 6800-6bff. Assume the system has 16 address bits (A15..A0).

The answer to the first question is easy. Just parallel the address inputs, the /WE and the /CE. One memory handles the lower 4 data bits, the other chip handles the higher 4 data bits.

To answer the second question requires a simple truth table. As before, the address inputs and the /WE are paralleled. The /CE (chip enable) inputs are controlled from an address decoder so that the correct memory chip is enabled when the address range is correct.

The truth table makes this easier to understand.

As the second question asks for a 2028x4 bit memory the data I/O lines are paralleled. When one chip is enabled, the other chip's I/O will be open circuit (high impedance).

Edit:- The address decoder needs another A15 input to correctly answer the question. But the outputs are correct:- /6 (low when input = 06h) and /1A (low when input = 1Ah).