High-level synthesis (HLS) promises high-quality hardware with minimal develop-
ment e ort. In this thesis, we evaluate the current state-of-the-art HLS engine VAST
and propose a method to generate clock-gating-friendly RTL code for downstream
logic synthesis tools. We use one-hot-key encoding method to build the state tran-
sition in hardware, and we use the state registers along with main clock signal to
generate subclock signals. By analyzing the usage of each register when the nite
state machine is in di erent states, we assign the corresponding subclock signals to
the register and reduce the unnecessary toggle of the registers when they are not in
use. CHStone benchmarks in di erent application categories are used to verify the
functionality and test the performance of the designs. The area and power data are
measured using downstream commercial state-of-the-art tools during logic synthesis.
We gain 5% to 20% dynamic power saving with -6% to 2% area increase.