VirtualMemory/Problem 3

Consider the following three hypothetical, but not atypical, processors, which we run with the SPEC gcc benchmark.

A simple MIPS two-issue static pipe running at a clock rate of 4 GHz and achieving a pipeline CPI of 0.8. This processor has a cache system that yields 0.005 misses per instruction.

A deeply pipelined version of a two-issue MIP processor with slightly smaller caches and a 5 GHz clock rate. The pipeline CPI of the processor is 1.0, and the smaller caches yield 0.0055 misses per instruction on average.

A speculative MIPS, superscalar with a 64-entry window. It achieves one-half of the ideal issue rate measured for this window size (9 instruction issues per cycle). This processor has the smallest caches, which leads to 0.01 misses per instruction, but hides scheduling. This processor has a 2.5 GHz clock.

Assume that the main memory time (which sets the miss penalty) is 50 ns. Determine the relative performance of these three processors.

Solution

First, we use the miss penalty and miss rate information to compute the contribution to CPI from cache misses for each configuration. We do this with the formula:

Cache CPI = Misses per instruction * Miss Penalty

We need to compute the miss penalties for each system:

Miss Penalty = Memory Access Time / Clock Cycle

The clock cycle times for the processors are 250 ps, 200 ps, and 400 ps, respectively. Hence, the
miss penalties are