Slower Esthers to meet earlier H1 2005 deadline?

VIA's next-generation x86-compatible processor, 'Esther', which has been designed to take the chip family beyond 2GHz, will ship in Q4, online reports suggest.

That's two quarters later than anticipated.

The company announced Esther some time ago, most recently - September 2004 - saying the chip would ship as the C7, when both desktop and mobile versions of the part will go on sale.

To date, VIA has said that the chips will operate using an 800MHz frontside bus clock. It will sport the fourth generation of VIA's PowerSaver energy conservation technology and provide RSA encryption (with Montgomery Multiplier support) and Secure Hashing (SHA-1 and SHA-256) acceleration to the hardwired security-oriented functionality the current C3 chips already provide. C7 will also support Intel's SSE 2 and 3 multimedia-oriented instruction sets and the 'no-execute bit' support. It will feature a larger L2 cache than the C3's 64KB.

VIA has already said that the C7 will be fabbed by IBM using a 90nm silicon-on-insulator, low-k dielectric process and 300mm wafers. The C7 is expected to consume 3.5W at 1GHz, but be capable of being clocked to 2GHz and beyond.

But in an email reportedly issued by VIA it's claimed that the chip will consume 25W at 2GHz, with 1.5, 1.6, 1.7 and 1.8GHz versions consuming 12-22W.

According to the email, the C7 won't hit 2GHz until Q4 2005. In the past, VIA has said the chip will ship sometime during H1 2005. So either it won't launch at 2GHz or the part's release has been put back. ®