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3.1i Virtex-E BitGen - A greater than .3 ns discrepancy is seen between the input clock of a DLL and the feedback path.

Description

General Description:When probing the input of a global clock and its feedback pin on a clock DLL,a discrepancy of over .3 ns has been seen between the two clock signals.

Solution

There is a problem in the Virtex-E BitGen equations. BitGen determined that if a signal went from the DLLFB pin of a DLLIOB directly to the CLKFB pin ofa DLL, the DLL feedback connection was "on-chip" instead of "off-chip". This created an improper clock de-skew of approximately 250 ps.