The Perfect (Silicon) Marriage… Yes, It Exists

Nope, this is not Dr. Phil masquerading as a tech blogger, trying to penetrate the semiconductor market. I am no Dr. Phil, but today, rather than expound on interconnect IP and how it relates to the various trends, applications, markets, etc., I would like to tell you a story about a relationship and share an experience with one of our customers, a leading manufacturer of autonomous systems.

Recently, as part of a customer visit, the agenda was to kickstart the initial architecture planning phase of a state-of-the-art autopilot SoC. Remember, this is just an initial architecture planning meeting, so we were expecting the room to be filled with the top architects from the customers, wanting to make sure the overall use case, requirements, and structure were nailed down.

Well, there were indeed a couple of them. But those two were completely outnumbered by the big guns from the physical design domain. We knew right off the bat where this meeting was going. And fortunately, we were well prepared on our end too.

There was a time when physical awareness was not even a consideration in front end design and, honestly, not really that critical to the success of a device execution. But this was back in the days when we used to talk in terms of microns. Oops, maybe I am dating myself by saying that! In all seriousness, back then, silicon area was not as expensive as it is now. Likewise, neither was wire cost. Back then, architects had a field day planning the next chip, and the PD guys were pulled in at the later part of the project. The typical silicon development flow would look like Architecture –> Design/Design Verification –> Physical Design (PD).

Not anymore! Today’s complex chips with numerous integrated IPs, along with physical constraints imposed by Moore’s law, have made physical design an art. An art that is not trivial. It requires people with extensive domain knowledge, or simply put, who really know their stuff.

We keep referring to Moore’s law as being a curse for PD, but I would argue that Moore has single-handedly shined the light on PD, putting it at the forefront of any silicon project execution and, more often than not, giving it a key role to play in the cost and quality of the product. So, I say to all my PD colleagues, bask in it. And I don’t see this changing in the foreseeable future.

Back to the customer. This was one of the most challenging customer designs we had faced. The high level goals were to go from architecture to tape-out in 9 months, with a continued roadmap of 50% performance increases every 2 years.

The dating scene (finding the ideal match)
Similar to the real world of dating—speed dating, just lunches, etc.—the “check compatibility” phase came with two main challenges. One was the coherency complexity of the SoC, and the other was driven purely by the physical size and constraints. You must be thinking, how did we even win this deal? We were up against a gargantuan IP company that has been around for ages. But even the great Pete Sampras had to step aside and make way for the young and ferocious Roger Federer. You can’t ignore the new blood.

The commitment
The clear advantage we brought to the table was proven expertise in the coherency domain combined with state-of-the-art and sophisticated physical awareness methodology, and as a result, we were able to show 20% higher bandwidth at 30% lower latency. And this is how we won over the customer!

From there on, what ensued was just pure seamless collaboration.

The honeymoon period
The initial honeymoon phase was basically a feasibility study planned around two specific requirements:

Hard constraint on die size

Superfast feedback loop between architecture and physical design

This needed to happen while the architecture was still evolving. Hence, it was that much more important to have a well-thought-out and customized plan. So basically, this honeymoon was not at a cheap one-size-fits-all all-inclusive resort with mediocre liquor and stale buffets, but at a charming boutique retreat with cocktail caviar and epicurean fare.

Physical floorplan-aware interconnect

As is the case with most silicon projects, the device floorplan and cost structure were already in place as part of the commissioning phase. Hard constraints on the die size and, more importantly, the locations and aspect ratios of IPs were standard requirements to be solved. Many already hardened IPs are reused, while some others need specific aspect ratios to make them buildable. And the locations of the ports and interfaces ended up being in the proximity of the associated logic. We worked with those constraints and incorporated quick architecture updates with physical awareness to assess feasibility. Also, part of this key effort was to have the right “grouping” of modules to partition the design and make it easier for the physical design to assign locations for those using DEF (Design Exchange Format). From the integration point of view, IPXACT was the standard conformed to. The fast turnaround time— made possible by machine learning combined with physical awareness—helped us confirm feasibility in a couple of months, start to finish. For a project this humongous, two months was a short time, but we believe this can be cut even short for a follow-up next-gen design.

The in-laws (blessing in disguise)
As sometimes happens, one complication in this marriage was the involvement of the in-laws. In this case, the in-laws were the customer’s design services company. But what we assumed to be a complication turned out to be of great help. The expertise they brought to the table played very well with the complexity of the project. Also, having a third-party design service meant that they were involved in the design much sooner in the process. And all three of us kept each other honest in our efforts to reach the common goal.

Post-honeymoon (the real marriage)
After having spent some time together during the honeymoon discussing what both of us are looking for in this marriage, came the reality. Just like in a real honeymoon, no realistic rules were set yet, only thoughts of happy endings. The transition from the pristine white sandy beaches into the real world was defined by a stable floorplan that could be used as the basis for further architecture and design optimizations. And reality came with its own challenges.

Architectural optimizations

Topological effects

Microarchitectural fine tuning

Performance validation

Architectural Optimizations – Now that the floorplan was stable and known, we started working on exploring the architecture while staying within the bounds of the floorplan. If it was the other way around and architecture was completed first, then physical closure would have been a long, drawn-out affair. PD always has to work within much tighter constraints than architecture exploration, and hence having a stable floorplan was ideal. This gave us a good foundation and basis to constrain our experiments without disturbing the PD team, who welcomed this with open arms. The idea was to make the architecture more practical, but flexible enough to be able to withstand various workloads and goals. We provided the customer with a software tools platform that enabled them to specify system level requirements and utilize machine learning methodology to dramatically reduce the time for these explorations.

Topological and Microarchitectural Fine-tuning – These architectural experiments also included analyzing various topologies and fine-tuning microarchitectural features based on the traffic patterns defined by the user. The tools platform automatically identified the optimum topology and routing techniques, and the user then made tactical changes based on expert knowledge of their system. This division of labor was very efficient since both parties focused on their strengths without stepping over each other. While NetSpeed strategically evaluated the system level requirements, the customer made tactical decisions based on application scenarios. Buffer sizing, layer optimization, coherency, flop vs wire count tradeoff, and virtual channels, amongst other options, were taken into consideration during this phase.

Performance Validation – For every experiment, there is a result, and the key was the speed at which these experiments can be run and the data collected and analyzed. This was accomplished at various levels, starting off with high-precision simulation data from the NocStudio architecture exploration platform followed by validation using a combination of RTL and transactors. Was it a smooth ride from start to end? Of course not. But just like any marriage, clear and open communication was vital. Anytime the customer came across mismatches, NetSpeed would supply the knowledge and likewise the customer would help when NetSpeed was unaware of the system intent. Turnaround time was on the order of 20 minutes compared to the usual 1 day turnaround time in the industry. The superfast turnaround time also meant that we could try a lot more experiments in the given schedule to optimize the design. We experimented with data from almost 5,000 NoC topologies. Imagine if these had to be handcrafted; only be a handful could be explored. Often in a marriage, it takes a few “situations” to realize what the partner brings to the table. Similarly, after a few weeks into the performance validation and getting their hands dirty, the customer realized the real benefits of the in-built simulator. The aspects that really caught the customer’s attention were correlation accuracy with RTL numbers, matching structural latency and ease of analyzing active simulation latency.

Schedule-wise, we were able to go from concept to close out in 4-5 months. Included in this is the initial 1-2 months to finalize the PD floorplan followed by 2-3 months of architecture optimization and design closure. One of the key things we learned is that by involving PD from the initial phases of this project we were able to save a lot of time.

I hope this marriage beats the 7-year itch and stays happily together ever after.

Details of NetSpeed’s Coherency IP can be found here; Physical Awareness is here.

Rajesh Ramanujam

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Rajesh Ramanujam is responsible for product marketing at NetSpeed Systems. He has 15 years of experience in hands-on SoC development. He was an SoC system architect at Altera (acquired by Intel) and Huawei and a senior processor architect at Texas Instruments. He received an MS, Electrical and Computer Engineering from Iowa State University and a BS, ECE from the University of Mumbai.