eDRAM or stacked DRAM?

Eric Bron (eric.bron.delete@this.zvisuel.privatefortest.com) on June 24, 2014 5:37 am wrote:
> > Looks like this rumor was true. Micron and Intel announced
> > today that KL will be using HMC for on package memory.
>
> "To the programmer, the Micron memory will be transparent to the outside world--almost
> like a layer three cache inside the package with the processor," Black said.
>
> so it looks like there is no on chip L3 cache, unlike David's hypothesis in is KNL article

I don't know about that. That quote is from Micron, who may be just using L3 cache as a synonym for LLC and may not be yet privy to detailed internal specs of KNL or simply doesn't care enough about those specs to speak accurately. (Obviously they're more interested in marketing HMC memory than dicussing KNL architecture.) I found some other slides (which admittedly may or may not be real; however the other info in those slides seem to match up well with the more recently released official slides from Intel) from some time ago that seem to schematically indicate some sort or global cache on die, which would presumably be an L3 cache of some sort given that the Silvermont cores have self-contained L1/L2 caches.