Figure 1.

A schematic diagram of the flexible ZnO/Al-NPs memory TFT and the cross-sectional
device structure (inset) (a), and a cross-sectional TEM image of the stacked gate layer (b). The left inset is a planar HRTEM image of Al NPs on the SiO2 layer, and the right inset shows the EDX elemental mapping of Al (cyan), Si (red), and O (blue). A photographic image showing the ZnO/Al-NPs memory TFTs on a flexible plastic substrate
(c).