6.1 AM6x Flash Subsystem (FSS) Overview

Hi. I'm Mark McCown with Texas Instruments. This is a three part training on the Flash Subsystem of the TI AM65x processor, which is used to interface to Octal SPI and Hyperbus devices. This training provides an overview of the Flash Subsystem, and its two components, OSPI and Hyperbus. We will walk through the block diagrams, features, modes, and signals of each component, including their initialization, interoperability, similarities, and differences.
The training is broken into three parts-- FSS, OSPI, and Hyperbus. Over the years, flash memories have trended away from parallel towards serial interfaces. This decreases the PCB congestion without having to route data lines around the board, but to meet the increasing bandwidth requirements, these serial memories had to increase their clock frequencies, which also increases PCB layout complexity.
So to meet the increasing bandwidth requirements, these serial memories have been adding parallel data interfaces back. Dual SPI came first with two, then Quad SPI had four. They're also utilizing both clock edges to get twice the bandwidth out of the same clock frequency.
So it's a natural progression for Octal SPI to have eight parallel IOs. It's also backwards compatible with other SPI devices, because it uses the same SPI protocol, but it has special octal commands to utilize those eight IOs and get the bandwidth out of them.
There's also Hyperbus, which includes HyperFlash and HyperRAM, which is another serial flash memory interface that uses eight parallel IOs and clocks on both edges. It supports a similar bandwidth, but it's slightly different in that it uses the flash protocol instead of the SPI protocol. Both interfaces support eXecute in Place, which reduces boot time and gets your application running faster. It also reduces the RAM requirements of the device, since the RAM no longer has to contain the program data. On the AM65x processor, both interfaces are supported and pin muxed together, so you can have different combinations of OSPI and Hyperbus, which I'll get into in the next sections.
In this block diagram, we see a typical application of the FSS interfacing to both Hyperbus and OSPI. On the AM65x processor, there's only one flash subsystem integrated on the MCU island but accessible by the full system. Hyperbus and OSPI0 are pin muxed. Both have eight IOs. Hyperbus has two chip selects, while OSPI0 has four chip selects, and both support ECC and on the fly authentication. OSPI1 has four IOs and two chip selects and also supports ECC.
Data interface S1, another 64-bit data 32-bit address with access to OSPI1, the config interface, which has access to the FSS memory map to registers, reset and the interface clock, memory mapped registers for FSS, ECC, mux, and the dynamic fragmentor blocks, the flash security authentication and safety block that consists of on the fly authentication and error correction code sub blocks. The FSAS is muxed either OSPI 0 or Hyperbus 0. Within that block, the OTFA performs encryption, decryption, and authentication, supporting four programmable regions for encryption and authentication. Also, ECC. Data within the OSPIs or Hyperbus interface can be in-band ECC protected with single error correction and double error detection. Each 32 byte block is protected by four [INAUDIBLE] bytes. ECC can be used with OSPI 0 or Hyperbus, whichever is selected by the primary SO interface.
The secondary S1 interface includes a standalone ECC module for OSPI 1 only. The mux that allows FSS 0 to map either to OSPI 0 or Hyperbus, the dynamic fragmentor, which is responsible for fragmenting right data to the flash regions so that all rights to the flash region are done in 16-bit chunks. This is a requirement for Hyperbus. The Hyperbus interface, HPB 0, part of the primary FSS interface. It can be configured to use ECC and or OTFA. OSPI 0, also part of the primary FSS interface. It can also be configured to use ECC and or OTFA. And, finally, OSPI 1, part of the secondary FSS interface. It can be configured to use ECC only.
There are give valid combinations of Hyperbus and OSPI. You can have two simultaneous flash interfaces, two OSPI, with OSPI 0 and OSPI 1, or one Hyperbus interface and one OSPI. The primary FSS interface for OSPI 0 and Hyperbus supports execute in place, 32 byte block copy operations, ECC, and or OTFA. The secondary FSS interface for OSPI 1 supprots 32 byte block copy operations and ECC.
The mux configuration maps the package signals to their various modes. OSPI 0 is pin muxed when in mode 0, with the exception for chip select 2 and 3, which are in mode 1. OSPI 1 is also in mode 0 but uses different pins. You can see the Hyperbus pins are pin muxed with OSPI 0 and selected in mode 1. Mode 2 selects the reset and interrupt pin, while mode 1 and mode 3 chooses between the right protect and chip select 1.
Here, we can see that OSPI 1 and Hyperbus can be pin muxed at the same time. This table presents the various possible combinations of FSS interfaces. Both primary and secondary paths support x IP and block copy modes. The OTFA for safety and security is applicable in x IP mode only. Read and write modes can bypass ECC and OTFA in a pure bypass mode, but whenever ECC is used, the rights are only supported for 32 byte aligned data.
A four byte ECC is calculated on either 32 bytes or 36 bytes, which would include a 4 byte message authentication code from the OTFA. ECC increases system reliability by reducing memory errors. Single bit errors can be detected and corrected, while double bit errors can only be detected. The ECC module can read any byte or block of bytes. If the region is ECC protected, the ECC module reads the block and returns the appropriate bytes requested. If not in an ECC protected region, only the requested bytes are read.
So for the S0 path, which supports OTFA and ECC, the input for the OTFA module is a 32 byte data block. The output is a 32 byte data block plus a 4 byte MAC. The ECC module generates ECC codes for the 32 byte data block, and the ECC module packs the MAC data and ECC, then reformats the address and sends this to the flash controller.
For the S1 path, which supports only ECC, the input is a 32 byte data block. The ECC module generates ECC codes for the 32 byte data block, then packs the data plus ECC and reformats the address before sending it to the flash controller. If the memory contains just ECC, 11% of the memory is reserved for ECC. If the memory supports just OTFA, 11% is reserved for OTFA. But if the memory supports both authentication and ECC, two words will be reserved, resulting in 20% of the memory used for authentication and ECC.
Both FSS interfaces have three regions. Region 0, the external memory space of four gigabytes, is used for eXecute in Place, DMA read, or DMA write, and can contain authentication and or ECC protected data. Region 1, the boot space, is a smaller boot region of 64 megabytes or 128 megabytes. It's similar to region 0, but can select only these sizes. And region, 3 another external memory space of four gigabytes, is used to bypass the address translation so that programming sequences of particular key address data pairs can be issued to the flash. Both region zero and region 1 have address translation to make room for authentication and ECC words.
Since these words can only be written by the OTFA and ECC, region 0 and 1 do not have the ability to write flash key patterns to enable Hyperbus programming. Therefore, region 3 is used for these sequences. Region 3 can also be used to program the flash with authenticated and ECC protected data, which is useful when scrubbing ECC errors in the event a flash takes a big hit.
The FSS can be initialized in 10 steps. First, configure the main boot parameters for S0 or S1. Then enable FSS in the Power Sleep Controller. Configure the interface which will be used, OSPI 0 or Hyperbus for S0, or OSPI 1 for S1. Then enable the selected FSS interface in the Power Sleep Controller. Configure the FSS interface, which will be covered in later sections. Then configure the ECC region start address and size. Enable the ECC option if the target flash device has ECC encoded within. For S0, the OTFA option can be enabled. If the target device is a HyperFlash or SRAM, configure the fragmentation address boundary. And, lastly, enable error interrupts.
Regarding real time operation, the CPU or DMA can read any location in the memory map, and ECC authentication or decryption will occur based on the region selection and the size configuration. In the event of a single error detection, the 32 byte block address and associated error bits are stored, and an interrupt is generated. The CPU can then service the interrupt to determine the error type.
If a single error occurs, the CPU can scrub the flash block to determine if the error is permanent and requires reprogramming. In the event of a double error detection, the 32 byte block address and associated error bits are again stored, and an interrupt is generated. The CPU can service to interrupt to determine the error type. If the double error detect is within the flash, the region is corrupt and must be treated as unused. For both ECC double error detect and authentication error, the bus status will also be set, which prevents the CPU from executing the erroneous data.
The Power Sleep Controller has four controls for the FSS. These are used for power up and power down sequencing. They control the FSS, OSPI 0, Hyperbus, and OSPI 1. The CPU must enable the appropriate interface before using it.
Since the S0 can only use either Hyperbus or OSPI 0, only one of them needs to be enabled. S1 can only be used to access OSPI 1, so any S1 transaction will be blocked based on the power state of OSPI 1.
To perform a normal power down sequence, first, block any new transaction on the particular interface, then power down the target FSS interface. And when they're all powered down, the FSS can also be powered down.
The FSS includes features that can help you reach end product safety goals. These include memory protection with ECC, data path and address parity protection, fatal false detection, reporting and recovery mechanisms, and ISO 26262 ASIL readiness.
For further reading, check out the following links.

Description

November 12, 2018

This is the first of three training modules that provides an introduction to the Sitara AM6x processor Flash Subsystem (FSS), which is used to interface to Octal SPI (OSPI) and HyperBus devices. This FSS overview takes a look at the basic building blocks of the FSS, including the OSPI and HyperBus interfaces, as well as the various features, modes, and signals.