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AR# 36932

12.1 EDK - My EDK simulations are not working

Description

When I run through a simulation for my PowerPC embedded project, the software never gets past the initialization of the processor. Why does this occur?

Solution

This problemoccurs mainly with PowerPC simulations, but the potential is also there for MicroBlaze. In the case of the PowerPC simulation, the processor continues to pre-fetch instructions when not needed.Not all contents in the block RAM are initialized with the processor data which means that the processor can step into a memory location that is empty.By default, the block RAM Unisim model takes on the default VHDL initialization which is 'U'.The processor model goes into an unknown state when it starts reading 'U' values.

To work around thisissue,manually modify the Unisim and Simprim block RAM models found in the following locations:

Modelsim To get the newly changed primitive into your ModelSim library, use the following command at the VSIM prompt: vcom -work unisim C:/Xilinx/12.2/ISE_DS/ISE/vhdl/src/unisims/primitive/ARAMB36_INTERNAL.vhd A similar commandmustbe used for the simprim models as well.

ISimTo get the newly changed primitive into your ISim library, open an ISE Design Suite prompt and run the following command: compxlib.exe -s xil_isim -lib unisim -l vhdl -dir C:\Xilinx\12.2\ISE_DS\ISE\vhdl\hdp\[nt|nt64|lin|lin64] A similar command must be used for the simprim models as well.

Modelsim To get the newly changed primitive into your ModelSim library, use the following command at the VSIM prompt: vlog -work unisims_ver C:\Xilinx\12.2\ISE_DS\ISE\verilog\src\unisims\ARAMB36_INTERNAL.v A similar commandmustbe used for the simprim models as well.

ISimTo get the newly changed primitive into your ISim library, use the following command: compxlib.exe -s xil_isim -lib unisim -l verilog -dir C:\Xilinx\12.2\ISE_DS\ISE\verilog\hdp\[nt|nt64|lin|lin64] A similar command will have to be used for the simprim models as well. This problem is scheduled to be fixed in ISE Design Suite 12.3. For other potential simulation issues, refer to (Xilinx Answer 36026)