Fingerprint Sensing

Designed a small area, noise-optimized current-mode front-end which helped reduce die cost by nearly 50%

Designed an innovative multi-level mixing topology to improve SNR

Drove circuit and system implementation of a small area current-mode front-end in order to prove ability of the new technology to sense a fingerprint (stepping-stone for fingerprint sensor cost reduction)

Led efforts to evaluate, track, and debug new silicon for any potential issues that could require a metal or all-layer revision, allowing for efficient evaluation of benefits/risks of a potential spin

Designed a capacitive background cancellation circuit with sub-femtofarad resolution

Touch Sensing

Designed a small-area current-mode baseline correction circuit for TDDI (Touch and Display Driver IC) in order to reduce die cost and maintain competitive edge in TDDI market

Low Power and Reference Circuits

Architected and led the implementation of an experimental small area, nano-Amp reference architecture (current mirrors, oscillators, etc) with the goal of reducing standby power without sacrificing performance

Designed a sub 1-V bandgap reference with innovative base-cancellation circuit for TDDI chips

Aided in development of a top-level mixed-signal verification flow for capacitive fingerprint sensors, allowing teams to efficiently catch system-level bugs before tapeout

Display Drivers

Experience with MIPI DSI from transistor-level design through top-level verification and production test

Experience designing high-voltage gate-line drivers

General

Experience working closely and effectively with multidisciplinary teams to ensure smooth silicon design and bring-up all the way through to production

Have designed circuits in 130nm and 55nm technologies

Very familiar and comfortable with Cadence design flow for IC design

Experience using MATLAB for both system design and for testing of ASICs

Focus on fundamental understanding of circuits for architectural comparisons is a strength (i.e. pencil-and-paper analysis)

Investigated small-signal modeling and stability requirements for boost converters, as well as a variety of OTA-based controller topologies, in order to aid in the design and measurement of boost converter stability on an ASIC. Also investigated use of genetic algorithms as a way to optimize controller design.