We hope to see you March 6-9, 2017 for this year’s Device Packaging Conference!
**2016 Conference presentations available at WWW.IMAPSOURCE.ORG** The 12th International Conference and Exhibition on Device Packaging welcomed 526 total participants from 19 countries, sold out an 11th consecutive exhibit hall, and enjoyed a successful technical program! The conference also proudly welcomed: • A 10% increase in full conference attendees • 15% international attendees • 3 new sponsoring companies • Standing room only in the brand new SiP Sessions • Plus, much more!

Thank you to our Premier PLATINUM Sponsor:

Thank you to our Premier GOLD Sponsors:

2017 Conference Overview:

The 13th Annual Device Packaging Conference (DPC 2017) will be held in Fountain Hills, Arizona, on March 6-9, 2017. It is an international event organized by the International Microelectronics Assembly and Packaging Society (IMAPS).

The conference is a major forum for the exchange of knowledge and provides numerous technical, social and networking opportunities for meeting leading experts in these fields. The conference will attract a diverse group of people within industry and academia. It provides a chance for educational interactions across many different functional groups and experience levels. People who will benefit from this conference include: scientists, process engineers, product engineers, manufacturing engineers, professors, students, business managers, and sales & marketing professionals.

KEYNOTE 1:Heterogeneous Integration: Packaging the FutureTechnology innovation in the semiconductor industry continues to march forward at an incredible pace, with advancements in new silicon node technology continuing on one end of the spectrum with innovation in packaging solutions coming forward at the other in a complementary fashion. As the pace of innovation has quickened, so has the investments required to bring such technologies to production. At the packaging level, the investments required to support the advancements in silicon miniaturization and heterogeneous integration have now reached well beyond $500M USD per year. One needs to look no further than the complexity of the most advanced package technologies being used today and coming into production over the next year to understand why.

Advanced packaging technologies have increased in complexity over the years, transitioning from single to multi-die packaging, enabled by 3-dimensional integration, system-in-package (SiP), wafer-level packaging (WLP) and creative approaches to embedding die. These new innovative packaging technologies enable more functionality and offer higher levels of integration within the same package footprint, or even more so, in an intensely reduced footprint. Today, the latest in advancements in heterogeneous integrated semiconductor packaging is able to provide reduced form-factor, increased data transfer rate, improved signal integrity and memory bandwidth, all with reduced power and improved thermal performance. As we truly live in a connected world and the proliferation of connected devices is forcing continually higher system level performance, not surprisingly, it is semiconductor packaging that has stepped up to play a pivotal role in providing the solutions to the new system level requirements.

Ron Huemoeller, AmkorRon is Corporate Vice President, Worldwide R&D, at Amkor Technology. Ron joined Amkor in 1995 and has since served in multiple senior to executive level roles. Currently, Ron is responsible for global R&D and technology strategy.

Prior to joining Amkor, Ron was Director of Engineering at Cray Computer Corp. in Colorado Springs for 5 years, leading the facilitation, startup and development of state of the art motherboards for the world’s fastest supercomputer. Ron has authored numerous technical publications, co-authored a chapter in the Handbook of 3D Stacking (McGraw Hill) and has been granted more than 100 U.S. patents. Ron holds a B.S. in Chemistry from Augsburg College with highest honors, a MBA in Business Management from Arizona State University and a Masters in Technology Management from the University of Phoenix.

9:10 am -
9:55 am

KEYNOTE 2:Neither IoT nor 5G without new Technology!5G networks are expected to unleash solutions that will help overcome barriers to widespread IoT adoption, such as technology hurdles leading to high connectivity costs, limited impact on user experience as well as security and privacy concerns.

Beyond the 28-nm node, new design costs increase exponentially. We cannot continue focusing on tinier transistors in the More-than-Moore era, when technology roadmaps call for heterogeneous integration, 3D and advanced packaging. Microelectronics is now led by system-driven roadmaps, and new drivers for 5G systems are diverging IoT services that require innovative flexibility and scalability from the technology. There is a new complexity in the drive of the technology roadmap since the transistor takes part of advanced system architectures where the software part is increasing.

The next step along the path of the digital era is a leap as roadmapping should be re-invented. Trends and examples of new integrated systems for IoT and 5G will be discussed in this presentation.

Lionel Rudant, CEA-LetiLionel Rudant is currently Strategic Marketing Manager at Leti. He draws up innovation strategies for conquering IoT markets through key enabling technologies that unleash innovative business. He has successfully transferred Leti wireless technologies to automotive, aeronautics, and industrial and consumer electronics industries, among others. He works on projects in France, Europe and the USA, and regularly presents technologies and system roadmaps at conferences and workshops.

He was awarded a postgraduate degree in electronics and digital technology by Nantes University (France) and a technology research degree by Grenoble Institute of Technology in 2003 and 2004 respectively. He then managed antenna projects for Radiall automotive and military systems. He joined Leti in 2006 and has since undertaken electromagnetics and antenna and propagation research, prompting publications on compact smart and disruptive super-directivity antennas.

In this session we will have an opportunity to review the latest technical advancements in fan-out wafer level packaging (FOWLP) and the market forces driving the rapid adoption of fan-out wafer level packaging.

TA3:
SENSORS
Chairs: Robert Weikle II, University of Virginia; Chase Harrison, Auburn University

In this session we will focus on identifying some of the key design attributes and challenges associated with the implementation of Fan-out WLP packaging design into various integration schemes and industrial application space as the use of organic substrate platforms continue to take hold in the industry.

Fan-Out is the most dynamic solution in the Advanced Packaging playground at the moment. All attendees are welcome to attend and interact in the panel discussion organized by Yole Développement. It will be the opportunity to learn and debate with key industrial players willing to share their different points-of-view and visions on Fan-Out, related strategy, business, and technology trends.

Since the Great Recession, the global economy has definitely had its tumultuous times. Financial and political instability along with low interest rates have resulted in “muddle through” worldwide growth. For the semiconductor industry, smartphone growth has somewhat peaked. Many are hoping that the IoT is the next growth driver, but it hasn’t blossomed yet.

The last two years have seen practically no growth in the semiconductor marketplace. What about 2017? Will it be any better? How will the semiconductor industry relate now to the “Make America Great Again” movement?

To understand this key issue, an overview analysis of the semiconductor market will be presented and its relationship to worldwide GDP, electronic products, capital spending, Foundry, and the SATS/OSAT markets.

Jim Walker, WLP Concepts Jim Walker is the recent President of World Level Packaging Concepts (WLP). Previously, he conducted research of semiconductor packaging and test, printed circuit board manufacturing and assembly, MEMS, and related outsourcing services assembly and test (OSAT) markets for Gartner, Inc. Mr. Walker is a founding member and past national president of the Surface Mount Technology Association (SMTA), and has served on the advisory boards of Advanced Packaging Magazine, MEPTEC, Bridgewave Communications and Surfect Technologies, a MEMS and nanotech materials/equipment company.

Prior industry experience further includes co-founder and vice president of marketing for Hana USA, serving as the surface mount (SMT) packaging marketing manager at National Semiconductor (now part of Texas Instruments), and performing research, development, and quality assurance of polymeric materials for adhesive, composite, electronic, and semiconductor applications at Dexter Electronic Materials and E.I. DuPont.

Mr. Walker holds a Bachelor of Science degree in chemistry from California State Polytechnic University with postgraduate work at California State University Los Angeles.

9:00am – 9:30am

Market Drivers and Packaging Trends for Automotive ElectronicsJan Vardaman, TechSearch InternationalElectronic content in automotive applications has increased dramatically over the past few years. Automobiles are on the threshold of a radical change in technology. Vehicles have increased connectivity, improved self-diagnostics, a greater number of safety features including crash avoidance technology and advanced driver assistance. What type of semiconductor packages are used in automotive electronics and what are the future challenges as new package types are adopted?

9:30am – 10:00am

What’s Happening in China Advanced Semiconductor Packaging Landscape?
Santosh Kumar, Yole DeveloppementThis talk will discuss about the advanced packaging market in China including forecast by the packaging technology, key Chinese & global player’s activities and government IC policy / initiatives. Further it will include the supply chain evolution and analysis about the strategy / direction of OSATs as well as the opportunities/ challenges of both local and global players in China advanced packaging space.

Integrated Packaging and Substrate Technologies for Next-Generation Smart DevicesEric Huenger, Rozalia Beica – Dow Electronic MaterialsThe presentation will provide an overview of the global trends driving the growth of Advanced Packaging, highlighting the trends of packaging platforms and substrates seen today in mobile applications. An overview of the various materials and interconnect processes required at both wafer and PCB/Substrate level, across various packaging platforms (WLP, SiP, 3DIC) will be included, highlighting current industry challenges and the solutions that Dow Electronic Materials are bringing to enable current and future development of smart devices.

11:15am – 11:45am

The Changing Landscape in the Back End
Brandon Prior, PrismarkThe last several years have seen notable changes in the supply chain of electronics hardware as well as significant consolidation of semiconductor players. Separately, the landscape of package assembly for both captive and merchant players has also evolved. Much of this change is due to growth in package platforms such as SiP and FO-WLP. How will these new platforms impact the role of semiconductor companies, wafer foundries, and OSATs? What , if any impact, will the re-integration of component and hardware suppliers have on the back end?

(additional abstracts in regular session will also be invited to participate)
In event of inclement weather, the poster session will be held in the foyer of the conference center

THURSDAY, MARCH 9, 2017 -- Keynote Presentations

7:00 am –
11:30 am

Registration

7:00 am –
8:00 am

Continental Breakfast Sponsored by:

8:00 am -
8:45 am

Keynote Sessions Sponsored by:

KEYNOTE 3:Trends in MEMS and Sensor IntegrationThe recent years have seen an exponential proliferation in the use of sensors, especially the image, motion, environmental and acoustic types. The smartphone is the best example of this phenomenon, integrating all of the above into what was once a humble phone. In its turn, the IoT revolution promises to drastically increase the usage of both smart and passive sensors as they get adopted into the personal and commercial aspects of our lives.

With the current and anticipated growth, the sensors themselves have become more sophisticated. Their performance and functionality have increased, while ASPs and power consumption have dropped. This evolution has been driven by the basic building blocks of 3D interconnects - stacking, bonding and TSVs. While TSV technology has matured considerably over the last few years, the industry relies on a variety of wafer and die bonding options, each with its own pros and cons. The goal is an optimum combination of high throughput, high accuracy and low temperature bonding for cost, performance and reliability reasons. This presentation will assess current and promising wafer and die bond technologies, while also examining the overall trends in MEMS and sensor technology.

Sitaram Arkalgud, XperiSitaram Arkalgud is driving the utilization of Ziptronix bonding technologies (ZiBond® and DBI ®) in 3D applications since January 2016. Prior to this role, he led the 3D group as VP, 3D Technology and Portfolio at Invensas. Before joining Invensas, he started and led 3D-IC development at SEMATECH, where the focus was on delivering manufacturable process technologies for TSV, wafer/die bonding and wafer thinning for 3D IC. Previously, Sitaram worked in a variety of roles spanning R&D and manufacturing in memory and logic technologies at Infineon/Qimonda and Motorola. He is the author of several publications and holds 24 U.S. patents. Sitaram holds a master’s degree and a Ph.D. in materials engineering from Rensselaer Polytechnic Institute in Troy, N.Y., and a bachelor’s degree in metallurgical engineering from Karnataka Regional Engineering College (NIT-K), Surathkal, India.

8:45 am -
9:30 am

KEYNOTE 4:Embedded Components in PCB – the Most Important Step Towards Modularization in the Last Decade?The continuing digitalization of the world will change this decade and define the growth of the electronics industry. The driving forces behind these trends are the nearly ubiquitous access to the Internet and the continuous price pressure for electronic devices, data transmission and sensors. Today’s, society is at the start of the Internet of Things (IoT) and has already evolved much broader than just an idea. It has morphed to ”Internet of Everything“ (IoE).The majority of the 50 billion connected devices, machines, vehicles, etc. in 2020 will be used to link and direct systems in a variety of areas such as industry, smart homes, smart cities, smart energy, smart mobility, smart healthcare, wearables and much more. This trend will have significant influence on the future growth in all segments of the entire electronics industry.

In order to offer solutions from electronics industry for these we have to realize and understand that the systems of the future require a more holistic “interconnection technology”. We have to form electronic modules at a minimum consumption of speed, space and energy. Over the last years embedding of components in PCBs has offered some answers for these modules of the future already. Now it is time to reflect the first experiences and check what is feasible in the up-coming years.

Markus Leitgeb, AT & S Austria Technologie & Systemtechnik AktiengesellschaftMarkus Leitgeb studied Polymer Engineering at the University of Leoben, Austria. He joined AT&S in December 2000 and was responsible for the screening, evaluation and qualification of base materials with improved reliability performance as well as for the implementation of new measurement technologies and testing methodologies (e.g. Drop Test). Out of this experience, he started to work on alternative concepts for flexible interconnections and mechanical miniaturization within the PCB, which succeeded in the 2.5D® Technology to enable cavities and advanced Rigid-flex solutions. Markus supported the roll out of the 2.5D® Technology to the plants in Leoben (Austria) and Shanghai and was responsible for the Product Development.

In 2012, Markus took over the Mechanical Integration Team within the R&D department of AT&S, which is developing alternative concepts for miniaturization and integration of additional functions such as Thermal Management and High Frequency into electronic devices. Markus holds 24 patents and published several papers. He is member of IPC, SMTA, iMAPS and the Advanced Packaging Committee of ECTC.

This session focuses on advanced flip chip packaging Advancements in underfill technology are explored, and the growing capabilities of flip chip designs to meet more stringent requirements are evaluated.

Member, Non-member, Speaker/Chair, Student and Chapter Officer registration
fees include: access to all technical sessions, exhibits, meals, refreshment breaks, and one (1) DOWNLOAD of presentations; DOWNLOAD will contain the extended abstract and presentation as submitted by the presenter. DOWNLOAD will be emailed 15 approximately business days after the event.
Also includes a one-year IMAPS individual membership or membership renewal at no additional charge which does not apply to corporate or affiliate memberships. All prices below are subject to change.

Type

Early FeeThrough 2/17/17

Advance/Onsite FeeAfter 2/17/17

IMAPS Member

$800

$900

Non-Member

$900

$1000

Speaker

$550

$650

Chair

$550

$650

Student

$300

$400

Chapter Officer

$550

$650

Exhibits Only Pass w/ Lunch Included

$30

$30

Exhibits Only Pass NO Lunch Included

$0

$0

8x10 Exhibit (Member)

$1600

$1900

8x10 Exhibit (Non-Member)

$2300

$2600

Professional Development Course: Each Course Registration is additional to the conference registration. Maximum of 1 morning course and one afternoon course can be selected. Attendees can opt for $0 exhibits only pass if they wish to take a PDC but NOT attend the conference/sessions.

Presentation Format/Template:
IMAPS does not require you to use a conference powerpoint template.
You are able to use your regular company/preferred powerpoint templates.
Please include the IMAPS show name and dates on your template and/or an IMAPS logo.

Poster Session/Information
The poster session is planned to be an INTERACTIVE presentation. This means you do not start and complete a scheduled talk without interruption like in a regular/oral session. Speakers should have talking points and be at their poster throughout the entire session (Wednesday, March 8 from 5:30pm-6:30pm). You can "present" your scheduled materials, but more often the attendees will review your slides and ask questions. Or you can watch them and talk to them depending on which slide they are on. Authors may either print out each of their powerpoint slides on regular paper and tack them up in order, or prepare a large poster (or 2 even). Recommended poster size is typically 3x4 feet, with the max space on the board being 4 ft high x 8 ft wide. IMAPS staff will provide tacks to secure your print outs. The session is first-come-first-serve so there are not assigned poster boards/locations. POSTER SETUP FROM 4PM UNTIL 5:00PM on Wednesday, March 8.

Dress Code:
There is no officially "dress code" for IMAPS Conferences. We ask you to be BUSINESS CASUAL or whatever more you prefer. Most speakers tend to be in business pants and button down/company logo shirts (Women in dresses or the same). Suits, sport coats and ties are common as well. We do not recommend casual attire.

All session presentations are 25 minutes followed by 5 minutes for QuestionsYou are required to load your powerpoint/presentation onto the session laptop yourself using your USB drive.
Speak with your session chair if you need assistance.

About the Session:
Sessions begin with Session Chairs making general announcements. Session Chairs will then introduce speakers by reading BIOs. Speaker will present for 25 minutes, followed by 5 minutes for questions. Session Chairs will thank the speakers. This process is repeated for each speaker in the session. Many sessions will take refreshment breaks (see program).

Book your hotel reservation today! We have reserved a block of rooms at the host hotel to accommodate our attendees. The discounted room rates are only available until the hotel deadline listed above, or until the room block sells out (and they often sell out early - before the expire dates). Reservations received after the noted deadline or after the room block has been filled may be subject to significantly higher rates. IMAPS room blocks at most hotels historically sell out ahead of the discount deadline, so we encourage you to make your hotel reservations quickly for the best price and availability.

Hotel Scams Alert!
All reservations should be made directly with the hotel and within the IMAPS room block. We are not using a housing company. If any person or firm contacts you and offers to handle your reservations, please beware. They are completely unauthorized and possibly fraudulent. The convention industry is currently plagued by such groups. If you use one of them and experience any problems, including lost deposits and no reservation when you arrive, IMAPS may not be able to assist you. Please be aware in particular of one of these unauthorized firms – Exhibition Housing Services – whose salespeople have falsely claimed to be calling from IMAPS.

The only way to book a room in the official IMAPS Housing Block using the reservations information above.

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