Effective address operand calculation

This table lists the number of clock periods required to compute an instruction's effective address. It includes fetching of any extension words, the address computation, and fetching of the memory operand.

Syntax

Adressing mode

B,W

L

Dn

Data register direct

0(0/0)

0(0/0)

An

Address register direct

0(0/0)

0(0/0)

(An)

Address register indirect

4(1/0)

8(2/0)

(An)+

Address register indirect, post inc.

4(1/0)

8(2/0)

-(An)

Address register indirect, pre dec.

6(1/0)

10(2/0)

d(An)

Address register indirect, displacement

8(2/0)

12(3/0)

d(An,ix)

Address register indirect, index

10(2/0)

14(3/0)

xxx.w

Absolute short

8(2/0)

12(3/0)

xxx.l

Absolute long

12(3/0)

16(4/0)

d(PC)

PC with displacement

8(2/0)

12(3/0)

d(PC,ix)

PC with index

10(2/0)

14(3/0)

#xxx

Immediate

4(1/0)

8(2/0)

Notes:

Pre-dec is slower than post-inc

There are no write cycles involved in processing the effective address

The size of the index register (ix) does not affect execution time

Move instructions

These following two tables indicate the number of clock periods for the move instruction. This data includes instruction fetch, operand reads, and operand writes.

Standard instructions

Example: add.w d3,a7 (Word ea Dn + An) takes 8 cycles.

The number of clock periods shown in this table indicates the time required to perform the operations, store the results and read the next instruction. The total number of clock periods must be added respectively to those of the effective address calculation where indicated (+).

Size

<ea>,An *

<ea>,Dn

Dn,<M>

ADD

B,W

8(1/0)+

4(1/0)+

8(1/1)+

L

6(1/0)+**

6(1/0)+**

12(1/2)+

AND

B,W

-

4(1/0)+

8(1/1)+

L

-

6(1/0)+**

12(1/2)+

CMP

B,W

6(1/0)+

4(1/0)+

-

L

6(1/0)+

6(1/0)+

-

DIVS

-

-

158(1/0)+

-

DIVU

-

-

140(1/0)+

-

EOR

B,W

-

4(1/0) ***

8(1/1) +

L

-

8(1/0) ***

12(1/2) +

MULS

-

-

70(1/0)+*

-

MULU

-

-

70(1/0)+*

-

OR

B,W

-

4(1/0) +**

8(1/1) +

L

-

6(1/0) +**

12(1/2) +

SUB

B,W

8(1/0)+

4(1/0)+

8(1/1)+

L

6(1/0)+**

6(1/0)+**

12(1/2)+

notes: + Add effective address calculation time
^ Word or long only
* Indicates maximum value
** The base time of six clock periods is increased to eight
if the effective address mode is register direct or
immediate (effective address time should also be added)
*** Only available effective address mode is data register direct
DIVS,DIVU - The divide algorithm used by the MC68000 provides less
than 10% difference between the best and the worst case
timings.
MULS,MULU - The multiply algorithm requires 38+2n clocks where
n is defined as:
MULU: n = the number of ones in the <ea>
MULS: n = concatenate the <ea> with a zero as the LSB;
n is the resultant number of 10 or 01 patterns
in the 17-bit source; i.e., worst case happens
when the source is $5555

Immediate instructions

The number of clock periods periods shown in this table includes the time to fetch immediate operands, perform the operations, store the results and read the next operation. The total number of clock periods must be added respectively to those of the effective address calculation where indicated (+).

Size

#,Dn

#,An

#,M

ADDI

B,W

8(2/0)

-

12(2/1)+

L

16(3/0)

-

20(3/2)+

ADDQ

B,W

4(1/0)

8(1/0)*

12(1/2)+

L

8(1/0)

8(1/0)

12(1/2)+

ANDI

B,W

8(2/0)

-

12(1/2)+

L

16(3/0)

-

20(3/1)+

CMPI

B,W

8(2/0)

-

8(2/0)+

L

14(3/0)

-

12(3/1)+

EORI

B,W

8(2/0)

-

12(2/1)+

L

16(3/0)

-

20(3/2)+

MOVEQ

L

4(1/0)

-

-

ORI

B,W

8(2/0)

-

12(2/1)+

L

16(3/0)

-

20(3/2)+

SUBI

B,W

8(2/0)

-

12(2/1)+

L

16(3/0)

-

20(3/2)+

SUBQ

B,W

4(1/0)

8(1/0)*

8(1/1)+

L

8(1/0)

8(1/0)

12(1/2)+

+ Add effective address calculation time
* word only

Single operand instructions

This table indicates the number of clock periods for the single operand
instructions. The number of clock periods and the number of read and write cycles
must be added respectively to those of the effective address calculation
where indicated.
instruction size register memory
CLR byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NBCD byte 6(1/0) 8(1/1) +
NEG byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NEGX byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
NOT byte,word 4(1/0) 8(1/1) +
long 6(1/0) 12(1/2) +
Scc byte,false 4(1/0) 8(1/1) +
byte,true 6(1/0) 8(1/1) +
TAS # byte 4(1/0) 10(1/1) +
TST byte,word 4(1/0) 4(1/0) +
long 4(1/0) 4(1/0) +
+ add effective address calculation time
# This instruction should never be used on the Amiga as its invisiable
read/write cycle can disrupt system DMA.

Shift and rotate instructions

This table indicates the number of clock periods for the shift and rotate
instructions. The number of clock periods and the number of read and write
cycles must be added respectively to those of the effective address
calculation where indicated.
instruction size register memory
ASR,ASL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
LSR,LSL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
ROR,ROL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
ROXR,ROXL byte,word 6+2n(1/0) 8(1/1) +
long 8+2n(1/0) -
+ add effective address calculation time
n is the shift or rotate count

Move Peripheral instructions

Exception processing

This table indicates the number of clock periods for exception processing.
The number of clock periods includes the time for all stacking, the vector
fetch and the fetch of the first two instruction words of the handler routine.
exception periods
address error 50(4/7)
bus error 50(4/7)
CHK instruction (trap taken) 44(5/3)+
Divide by Zero 42(5/3)
illegal instruction 34(4/3)
interrupt 44(5/3)*
privilege violation 34(4/3)
_____
RESET ** 40(6/0)
trace 34(4/3)
TRAP instruction 38(4/3)
TRAPV instruction (trap taken) 34(4/3)
+ add effective address calculation time
* the interrupt acknowledge cycle is assumed to take four
clock periods
_____ ____
** indicates the time from when RESET and HALT are first
sampled as negated to when instruction execution starts