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Samsung Electronics Monday said it is now mass-producing chips that stack layers of data-storing silicon like a microscopic skyscraper, creating what will undeniably be the NAND flash technology for the immediate future.

Once used to create embedded memory and solid-state drives, Samsung's V-NAND will boast capacities ranging from 128GB to 1TB, depending on customer demand. "In the future, they could go considerably higher than that," said Steve Weinger, director of NAND Marketing for Samsung Semiconductor.

The most-dense process for creating cells to store data on current planar NAND is between 10 nanometers and 19nm in size. To give some idea of how small that is, a nanometer is one-billionth of a meter -- a human hair is 3,000 times thicker than NAND flash made with 25nm process technology. There are 25 million nanometers in an inch.

Samsung's 3D NAND technology achieves gains in both area ratio and performance, the company said. The new 3D V-NAND will be used for a wide range of consumer electronics and enterprise applications, including embedded NAND storage and solid-state drives (SSDs).

Samsung's new V-NAND offers a 128-bit density in a single chip, the same as that now produced by planar NAND technology companies such as Intel and Micron.

One of the most important technological achievements of the new Samsung V-NAND announcement is that the proprietary vertical interconnect process technology can stack as many as 24 cell layers vertically, using special etching technology that connects the layers electronically by punching holes from the highest layer to the bottom.

It's not yet known what the limits will be for stacking cell layers in 3D NAND memory, analysts said. "Right now it's 24. The next generation, it may be 32. Then that'll increase," said Gregory Wong, principal analyst at research firm Forward Insights. "The real estate stays the same, but you can keep adding levels. And, by adding levels, you can reduce the cost per bit because there are more memory cells, but the real estate to store them does not increase."

With the new vertical structure, Samsung can enable higher density NAND flash memory products by increasing the 3D cell layers without having to continue planar scaling, which has become incredibly difficult to achieve. As the process becomes smaller and smaller in planar NAND flash technology, electrons more and more often leak through thinner cell walls creating data errors, requiring ever increasingly sophisticated error-correction code.

But 3D NAND also has its limits, and it's expected to reach those by the end of this decade, according to Wong. "For 3D NAND, like a skyscraper, once you reach a certain level it becomes too expensive. There's no cost benefit after a while. You can only build a skyscraper so high," he said.

Currently, other technologies, such as resistive random-access memory (RRAM), Racetrack Memory, Graphene Memory, and Phase-Change Memory are being viewed as future contenders to NAND flash. In 3D NAND flash, each layer of substrate requires a dielectric or electrical insulator. Currently, the dielectric material is 50nm. Making it thicker could slow the flow of electrons causing the memory's performance to falter. Making it too thin could cause electrical loss, just like in planar flash, thereby introducing data errors.

"It's very difficult to shrink dialetrics, so there's a tradeoff with reliability," Wong said. "It's a balance between all the materials in the device. You need to find right balance between performance and reliability."

Samsung said it has spent nearly 10 years of research and development on 3D Vertical NAND, and it now has more than 300 patent-pending 3D memory technologies worldwide. The company said its 3D technology has set the foundation for more advanced products including one terabit (Tb) NAND flash chips.

For the past 40 years, conventional flash memory has been based on planar structures that make use of floating gates. As manufacturing process technology proceeded to the 10nm-class and beyond, concern for a scaling limit arose, due to the cell-to-cell interference that causes a trade-off in the reliability of NAND flash products. This also led to added development time and cost.

Samsung's new V-NAND solves such technical challenges by achieving new levels of innovation in circuits, structure and manufacturing processes through which vertical stacking of planar cell layers for a new 3D structure has been successfully developed.

To do this, Samsung revamped its CTF architecture, which was first developed in 2006. Samsung's CTF-based NAND flash architecture temporarily places an electric charge in a holding chamber of the non-conductive layer of flash that is composed of silicon nitride (SiN), instead of using a floating gate to prevent interference between neighboring cells.

By making this CTF layer three-dimensional, the reliability and speed of the NAND memory have improved sharply. The new 3D V-NAND shows not only an increase of a minimum of 2X to a maximum 10X higher reliability, but also twice the write performance over conventional 10nm-class floating gate NAND flash memory.

According to IHS iSuppli, the global NAND flash memory market is expected to reach approximately $30.8 billion in revenues by the end of 2016, from about $23.6 billion in 2013, with a annual growth rate of 11 percent.