250 MSPS acquisition board

The ALPHA250 is a programmable board built around a Zynq 7020 SoC.
It features a 100 MHz RF front end with dual 14-bit ADC 250 MSPS and dual 16-bit DAC 250 MSPS. Analog input to output latency is less than 90 ns.
The RF ADC and DAC are clocked by a dual PLL, ultra-low jitter clock generator.
It includes a 4 channel 24-bit ADC and 4 channel 16-bit DAC.
The board comes with a comprehensive, open source, FPGA / Linux reference design.

Characterization

Noise floor

The RF ADC and DAC noise floors were characterized with this script available on GitHub.
The input referred voltage noise density of the ADC is about 13 nV/√Hz.
DAC voltage noise density is about 23 nV/√Hz (19 nV/√Hz after subtraction of the ADC noise floor).

Distortion

A 1 Vpp sine wave between 100 kHz and 40 MHz was send by DAC0 and measured by ADC0 (see script).
The figure below shows the amplitude of the second and third harmonic, relative to the fundamental frequency:

Distortion performance is limited by the DAC. ADC distortion (HD2 and HD3) stays under -80 dB up to 40 MHz.

Crosstalk

The crosstalk between the 2 ADC channels was characterized with the following script.
Crosstalk is under -95 dB up to 120 MHz.