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Abstract

A reoccurring design consideration for VLSI chips is the definition of the Power On Reset (POR) function. To insure accuracy of chip simulation and system power-on sequence design, it is desirable to have the entire chip in a known state after the power is applied to the system. The design problem is complicated in that many VLSI latch designs do not provide a discrete reset/set input. This article will outline a method to reset LSSD chips that have been successfully implemented.

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United States

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English (United States)

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This is the abbreviated version, containing approximately
48% of the total text.

Asynchronous Reset Control of LSSD Parts

A reoccurring
design consideration for VLSI chips is the
definition of the Power On Reset (POR) function. To insure accuracy
of chip simulation and system power-on sequence design, it is
desirable to have the entire chip in a known state after the power is
applied to the system. The design
problem is complicated in that
many VLSI latch designs do not provide a discrete reset/set input.
This article will outline a method to reset LSSD chips that have been
successfully implemented.

Proper reset
of a chip is fundamental to successfully running
power-on and system applications software.
As the chip may be
included in a variety of systems, the POR function must be
self-contained to minimize system support requirements (i.e., board
level components and system software).
This problem is twofold:
single chip reset and system reset. The
goal is to set all (or
critical subset) of the latches in the chip/system to a known state
and to have the chip/system begin to function in a coherent manner
avoiding first cycle exceptions. Due to
the size and complexity of
VHSIC chips, a conventional system reset is too cumbersome and has a
significant impact on sizing and timing.
A typical chip contains in
excess of 1,000 latches. To discretely reset even 10 percent of these
latches becomes an unacceptable impact to silicon use and wiring
complexity. Wiring complexity is of great concern since one reset
signal would have to be routed and buffered to many parts of the
chip. Discrete reset is not an efficient
solution.

The disclosed
solution is to flush every functional latch with
zeros by exploiting existing chip Level-Sensitive Scan Design (LSSD)
architecture inherently necessary for manufacturing test. See (*)
for a complete discussion of LSSD. The
LSSD scan structure is
utilized since all latches are serially interconnected and have a
separate clock control. Flushing a latch
is performed by
simultaneously activating both the A and B clocks of a latch while
applying known scan data. Fig. 1
illustrates this concept. Forcing
the scan data input to zero and initiating a chip-wide flush for a
sufficient length of time will ensure all LSSD latches are brought to
a known state. The scan and clock
control structures are already in
place for manufacturing test of the VLSI part and need only minor
modifications to allow chip control of clocks and scan path data
during functional mode.

The chip
reset function is realized through the MASTER Reset
Control Logic (RCL) which is placed on the chip to be reset or on a
member of the chip set. The MASTER RCL
circuit, shown in Fig. 2,
reduces dependency on external hardware by maintaining a reset
sufficiently long to reset...