Synchronising the AD9910

The big challenge is to set up a synchronisation environment that allows me to trigger the waveform with the lowest possible trigger jitter. Thereby I mean that that the time from trigger pulse (e.g. established by an I/O_Update) to the moment the waveform appears at the output should always be the same and vary by not more than 1 ps.

I understand that I need to synchronise the trigger pulse to the SYNC_CLK of the DDS to achieve this. I'm using 1GHz as the master clock, hence my SYNC_CLK has a frequency of 250MHz.

It's not that easy to establish a sync environment like that in the lab but in my final application I will use an FPGA for this task so this should be no problem.

Now comes the challenge:

I have another aux signal in my system that runs on a frequency of ~117.2 MHz. The FMCW waveform has to be coherent with this aux signal, too. That means, a rising edge of aux and the start of the fmcw waveform must always have the same delay. But a FMCW waveform start has to be synchronised to the internal 1GHz / 4 SYNC_CLK. To clarify that I attached a jpg file.

The problem is, that the aux rfequency of ~117.2MHz and the SYNC_CLK of 250MHz have nothing in common.

Sadly, I can't use another master clock than 1GHz (a master clock with a multiple of 117.2 would generate a SYNC_CLK frequency that is coherent to 117.2 MHz - but thats not possible in my system).

Do you have any suggestions? Is there a possibility to asynchronously trigger the DDS so that I don't have to wait for a rising edge of SYNC_CLK?

Any help or ideas are very much appreciated ... maybe anyone has a similar problem and found a solution to it

In my post I mentioned that I'm not able to use another Master clock than 1 GHz. As it turns out, this might be wrong: today I found out that it *might* be able to use another clock than 1GHz so that I will analyse the approach you suggested (feeding 117.2 MHz to the Ref clk and using the internal PLL).

Is the AD9910 somehow limited to a certain ref clock frequency range? I'm using the Evluation board by the way ....

Up to now I always used a 1GHz ref clock frequency. Now I try to get the AD9910 to work with a much lower frequency - e.g. 500MHz. I'm simply trying to output a 100MHz sine wave. With this setting I'm not able to generate any sine wave at the output of the AD9910. Instead my waveform looks somewhat like the picture attached.

Is this because of the harmonics appearing at the output additionally to the basis frequency of - in my case - 100MHz? I would expect a more or less clean 100MHz signal.

By the way: up to know I'm not using any PLL or multiplication. I'm directly using the 500MHz as my internal DDS frequency.

Can anyone give me some advice?

thanks in advance.

Attachments

Per the AD9910 evaluation board schematic, there's an 400MHz low pass filter for the DAC reconstruction filter. At 500MHz, your not filtering out the image frequency, so that's why the waveform looks distorted. So, you need to go back to 1GHz or change the corner frequency of

the filter on the evaluation board. Note, you probably could add another filter in series to the one on the evaluation board.

thanks DSB - again - for your confirmation of what I was thinking was is problem. So, what I'm about to do is to multiply the reference clock signal with the internal PLL to ~937MHz (what was my intention right from the start).

I think the trickiest part will be the design of a PLL loop filter. At first it took me some time to finally recognise that there are no PLL filter components soldered onto the board, so I have to design my own PLL filter (based on the equations given in the AD9910 datasheet of course).

Since I'm not so much into designing PLLs (up to now) I hope that I can get some help here - again - since I have to get a setup working for demonstration very quickly ...

So I want to tell you what I'm about to do:

I want to take a frequency of 468MHz as my reference clock input for the AD9910 eval board. Alternatively I could also choose this reference frequency to be 117MHz but I think the smaller my PLL multiplication factor is, the better its performance will be - am I right with this assumption?

So I have my 468 MHz ref clock thich I want to double to 936MHz using the internal AD9910 PLL. Since I'm using the eval board GUI I choose the following settings in the clock section:

These settings result in a System clock of 936 MHz, what is exactly my intention. Now I would expect the PLL lock indicator to flash or light - but that won't happen. I set up my PLL loop filter according to the following values (based on the equations from the AD9910 datasheet, p. 27):

N = 2

fOL = 50 * E3 Hz (50 kHz I took this value from the datasheet example. I've got no idea how this influences my PLL - should I choose another value?)

phi = 45° (I also have no idea what to consider for this value ...)

KD = 287 * E-6 A (287 µA)

KV = 850,000,000 Hz / V (850MHz/V)

these values yield the following values for the loop filter: R1=3Ohm, C1=~2.2 µF, C2=~470nF

With these values I can't get the PLL to lock (also the PLL lock pin on the eval board stays low). Can anyone give me any help on that topic?

I'm gussing you found out the evaluaiton software is pretty straightforward. Putting a check in the 'Enable PFD Input Doubler' box does double the system clock frequency. You are correct about the PLL needing a multiplication factor greater than 2. The evaluation software is fine with a factor of at least 8, while the datasheet says min is 12. Perhaps DSB can comment on why they say differently? If any settings won't work, that section will have a red or yellow border around it. You can also see how the changing the various settings affects the register values by selecting 'Register Map Values' from the View menu.

Attached is a spreadhseet I received from DSB a while ago that I tweaked to be just a little bit better. Even though it says AD9957, I believe the AD9910 and the AD9957 have the same PLL section so this can be also used for the AD9910. As far as I know, the spreadhseet uses the same equations given in the datasheet, but it also calculates and plots a few extra things for you.

Message was edited by: Kevin.G - I'm removing the attachment because it had errors. This way nobody else will download it and wonder why it doesn't work.

1.) since the pll does work with a factor of x8 (at least in my configuration), you should allow to enter a value of 8 in the multiplication field

2.) somehow, in each field (e.g. phase margin) if i enter a valid value - for example 45 - an error pops up saying "Enter a value between 40 and 89" (although i entered 45. Based on my calculations that *is* between 40 and 89)

But since I just recognized that you didn't "hide" the calculations behind each field, I should be able to do make these changes by myself .. somehow.

Attached is the original tool DSB gave me. None of the changes I made should have affected how it function, but I could have been wrong. There are some hidden rows on Sheet1 which which I moved to different worksheets in my revision. These sheets are also hidden. I also increased the range of resistor and capacitor values.

I'll see if I can look into the issues you're seeing and make some changes.

Attachments

I know what the issue is with the edited tool I posted earlier. There were broken references in some of the data validations from when I moved stuff around. I've correct those in the new version attached. I also found a few other things to simplify as well as discovered that some of the hidden equations and cell values were not used by the rest of the workbook so I removed them. Hopefully everything is still functionally equivalent to the original tool, but I won't know until it's tested.

I am using AD9910 evaluation kit. when I use PLL multiplication block and try to generate a single tone frequency. Initially there was no wave at the output but when I check the "PFD X reset" block then the output appears. But the output frequency is about 1.55 times greater then the desired frequency. for e.g 10 MHz comes out to be 15.5 MHz and 70 MHz comes out to be 108.5 MHz etc.

Thanks mikael... any idea of what if the high-limit for REFCLK when using the internal PLL. why is this restriction in the datasheet? hopefully someone from analog can explain.

My application is a bit similar, the DDS needs to be synchronized to the rest of the system, so I had though about the solution proposed in this thread. However, for me is also critical that the data update to the DDS has a constant delay, after each power cycle.

I will try to explain it better... I am feeding the data via parallel-port, which is SYS-CLK/4.

When REFCLK is feed as reference to the DDS-PLL, we get the SYS-CLK locked to the REF-CLK, but what is the phase of the "/4" signal? how can I make sure that I have the same phase on this signal after each power cycle with respect to the REF_CLK?