Other characteristics from this technology include high density and low VCC_min 6-T SRAM cells, low leakage transistors, proven conventional analog/RF/electrical fuse components, and low-RC Cu-low-k interconnect. TSMC presented the development in a technical paper at the Symposia on VLSI Technology and Circuits in Kyoto, Japan.

The paper reported good 64Mb SRAM functional yield with a competitive cell size of 0.127μm(2), and a raw gate density as high as 3900kGate/mm(2) in this 28nm dual/triple gate oxide SoC technology. Good SRAM VCC_min, electrical fuse, and analog performance have also been achieved, thus proving the manufacturability of this technology.