Chen, Zhubei City

Ben Chen, Zhubei City TW

Patent application number

Description

Published

20130206070

DEPOSITION RING - A deposition ring is used on thin film deposition equipment which includes a chuck to hold a wafer. The deposition ring is arranged on the circumferential wall of the chuck and includes an inner ring and a protective member. The inner ring is adjacent to the circumferential wall. The protective member is jutting from the inner ring and has a circumferential surface, a barrier surface and a tip edge. The circumferential surface opposes the circumferential wall. The barrier surface and circumferential surface form an acute angle between them. The tip edge is formed between the circumferential surface and barrier surface. Through the protective member, the probability of adhering deposition particles to the back of the wafer is greatly reduced. The protective member is formed in a structure with a gradually increasing bottom, hence can provide higher stress resistant capability and overcome the easy fracturing problem in the conventional techniques.

08-15-2013

Benior Chen, Zhubei City TW

Patent application number

Description

Published

20140186986

HYBRID MEMS BUMP DESIGN TO PREVENT IN-PROCESS AND IN-USE STICTION - A micro-electro-mechanical systems (MEMS) device and method for forming a MEMS device is provided. A proof mass is suspended a distance above a surface of a substrate by a fulcrum. A pair of sensing plates are positioned on the substrate on opposing sides of the fulcrum. Metal bumps are associated with each sensing plate and positioned near a respective distal end of the proof mass. Each metal bump extends from the surface of the substrate and generally inhibits charge-induced stiction associated with the proof mass. Oxide bumps are associated with each of the pair of sensing plates and positioned between the respective sensing plate and the fulcrum. Each oxide bump extends from the first surface of the substrate a greater distance than the metal bumps and acts as a shock absorber by preventing the distal ends of the proof mass from contacting the metal bumps during shock loading.

07-03-2014

Cheng-Hung Chen, Zhubei City TW

Patent application number

Description

Published

20140023972

Data Process for E-Beam Lithography - The present disclosure provides a dithering method of increasing wafer throughput by an electron beam lithography system. The dithering method generates an edge map from a vertex map. The vertex map is generated from an integrated circuit design layout (such as an original pattern bitmap). A gray map (also referred to as a pattern gray map) is also generated from the integrated circuit design layout. By combining the edge map with the gray map, a modified integrated circuit design layout (modified pattern bitmap) is generated for use by the electron beam lithography system.

01-23-2014

20140099582

Smart Subfield Method For E-Beam Lithographny - The present disclosure provides a method of improving a layer to layer overlay error by an electron beam lithography system. The method includes generating a smart boundary of two subfields at the first pattern layer and obeying the smart boundary at all consecutive pattern layers. The same subfield is exposed by the same electron beam writer at all pattern layers. The overlay error caused by the different electron beam at different layer is improved.

04-10-2014

20150035851

Method for Image Dithering - The present disclosure provides a method for image dithering. The method includes providing a polygon related to an integrated circuit (IC) layout design in a graphic database system (GDS) grid; converting the polygon to an intensity map in the GDS grid, the intensity map including a group of partial pixels and a group of full pixels; performing a first quantization process to a partial pixel to determine a first error; applying the first error to one or more full pixels; performing a second quantization process to a full pixel to determine a second error; and distributing the second error to one or more full pixels. The partial pixels correspond to pixels partially covered by the polygon, and the full pixels correspond to pixels fully covered by the polygon.

02-05-2015

20150040079

Method for Electron Beam Proximity Correction with Improved Critical Dimension Accuracy - The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a feature; fracturing the feature into a plurality of polygons that includes a first polygon; assigning target points to edges of the first polygon; calculating corrected exposure doses to the first polygon, wherein each of the correct exposure doses is determined based on a respective one of the target points by simulation; determining a polygon exposure dose to the first polygon based on the corrected exposure doses; and preparing a tape-out data for lithography patterning, wherein the tape-out data defines the plurality of polygons and a plurality of polygon exposure doses paired with the plurality of polygons.

02-05-2015

20150052489

LONG-RANGE LITHOGRAPHIC DOSE CORRECTION - A method of quantifying a lithographic proximity effect and determining a lithographic exposure dosage is disclosed. In an exemplary embodiment, the method for determining an exposure dosage comprises receiving a design database including a plurality of features intended to be formed on a workpiece. A target region of the design database is defined such that the target region includes a target feature. A region of the design database proximate to the target region is also defined. An approximation for the region is determined, where the approximation represents an exposed area within the region. A proximity effect of the region upon the target feature is determined based on the approximation for the region. A total proximity effect for the target feature is determined based on the determined proximity effect of the region upon the target feature.

02-19-2015

Chern-Lin Chen, Zhubei City TW

Patent application number

Description

Published

20140140107

ISOLATED POWER CONVERTER, INVERTING TYPE SHUNT REGULATOR, AND OPERATING METHOD THEREOF - An isolated power converter, an inverting type shunt regulator, and an operating method thereof are disclosed. The isolated power converter includes a transformer, an inverting type shunt regulator, a controller, and an optocoupler. The inverting type shunt regulator is located on the secondary side of the transformer. The inverting type shunt regulator includes an error amplifier and a MOSFET. The controller is located on the primary side of the transformer. The controller includes an inverting unit cooperated with the MOSFET. The controller receives a feedback voltage. The optocoupler is coupled to the inverting type shunt regulator and the controller to provide an opto-coupling current to the controller.

05-22-2014

Chia-Chan Chen, Zhubei City TW

Patent application number

Description

Published

20130320418

Self-Aligned Implantation Process for Forming Junction Isolation Regions - A device includes a semiconductor substrate, a well region in the semiconductor substrate, and a Metal-Oxide-Semiconductor (MOS) device. The MOS device includes a gate dielectric overlapping the well region, a gate electrode over the gate dielectric, and a source/drain region in the well region. The source/drain region and the well region are of opposite conductivity types. An edge of the first source drain region facing away from the gate electrode is in contact with the well region to form a junction isolation.

12-05-2013

Chia-Ho Chen, Zhubei City TW

Patent application number

Description

Published

20120001337

Alignment Mark and Method of Formation - In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.

01-05-2012

20130149871

CHEMICAL VAPOR DEPOSITION FILM PROFILE UNIFORMITY CONTROL - The present disclosure provides for methods and systems for controlling profile uniformity of a chemical vapor deposition (CVD) film. A method includes depositing a first layer on a substrate by CVD with a first shower head, the first layer having a first profile, and depositing a second layer over the first layer by CVD with a second shower head, the second layer having a second profile. The combined first layer and second layer have a third profile, and the first profile, the second profile, and the third profile are different from one another.

06-13-2013

20130187546

Novel Coherent Multiple Side Electromagnets - In some embodiments, the present disclosure relates to a plasma processing system that generates a magnetic field having a maximum strength that is independent of workpiece size. The plasma processing system has a plurality of side electromagnets that have a size which is independent of the workpiece size. The side electromagnets are located around a perimeter of a processing chamber configured to house a semiconductor workpiece. When a current is provided to the side electromagnets, separate magnetic fields emanate from separate positions around the workpiece. The separate magnetic fields contribute to the formation of an overall magnetic field that controls the distribution of plasma within the processing chamber. Because the size of the plurality of separate side magnets is independent of the workpiece size, the plurality of side magnets can generate a magnetic field having a maximum field strength that is independent of workpiece size.

07-25-2013

20130189851

CVD Conformal Vacuum/Pumping Guiding Design - The present disclosure relates to a guiding element for guiding gas flow within a chamber. The guiding element includes a structure, one or more inlets, an outlet, and a transportation region. The one or more inlets are formed on a first side of the structure. The inlets have inlet sizes selected according to a removal rate and to mitigate gas flow variations within the chamber. The outlet is on a second side of the structure, opposite the first side of the structure. The outlet has an outlet size selected according to the removal rate. The transportation region is within the structure and couples or connects the inlets to the outlet.

07-25-2013

20130201596

Electrostatic Chuck with Multi-Zone Control - An electrostatic chuck for clamping a warped workpiece has a clamping surface comprising a dielectric layer. The dielectric layer has a field and one or more zones formed of differing dielectric materials. One or more electrodes are coupled to a power supply, and a controller controls a clamping voltage supplied to the one or more electrodes via the power supply. An electrostatic attraction force associated with each of the field and one or more zones of the dielectric layer of the electrostatic chuck is induced, wherein the electrostatic attraction force varies based on the dielectric material of each of the field and one or more zones. The electrostatic attraction force is greater in the one or more zones than in the field, therein attracting warped regions of the workpiece to the clamping surface and clamping the warped workpiece to the clamping surface across a surface of the warped workpiece.

08-08-2013

20130239889

VALVE PURGE ASSEMBLY FOR SEMICONDUCTOR MANUFACTURING TOOLS - A semiconductor manufacturing tool and method for operating the tool are provided. The semiconductor manufacturing tool includes a process chamber in which plasma operations or ion etching operations are carried out and a valve assembly for opening and closing a valve that provides for loading and unloading substrates into and out of, the semiconductor manufacturing tool. While a processing operation is being carried out in the chamber, a valve assembly purge operation also takes place. The valve assembly purge operation involves inert gases being directed to the valve assembly area to prevent the buildup of particles and contaminating films in the valve assembly. Because the valve assembly is maintained in a clean condition, particle contamination is reduced or eliminated.

09-19-2013

20130320235

UV CURING SYSTEM FOR SEMICONDUCTORS - Embodiments of an ultraviolet (UV) curing system for treating a semiconductor substrate such as a wafer are disclosed. The curing system generally includes a processing chamber, a wafer support for holding a wafer in the chamber, a UV radiation source disposed above the chamber, and a UV transparent window interspersed between the radiation source and wafer support. In one embodiment, the wafer support is provided by a belt conveyor operable to transport wafers through the chamber during UV curing. In another embodiment, the UV radiation source is a movable lamp unit that travels across the top of the chamber for irradiating the wafer. In another embodiment, the UV transparent window includes a UV radiation modifier that reduces the intensity of UV radiation on portions of the wafer positioned below the modifier. Various embodiments enhance wafer curing uniformity by normalizing UV intensity levels on the wafer.

12-05-2013

20140264874

Electro-Migration Barrier for Cu Interconnect - Integrated circuit devices and method of forming them. The devices include a dielectric barrier layer formed over a copper-containing metal interconnect structure. The dielectric barrier layer inhibits electro-migration of Cu. The dielectric barrier layer includes a metal-containing layer that forms an interface with the interconnect structure. Incorporating metal within the interfacial layer improves adhesion of the dielectric barrier layer to copper lines and the like and provides superior electro-migration resistance over the operating lifetime of the devices.

09-18-2014

20140272193

DIRECTING PLASMA DISTRIBUTION IN PLASMA-ENHANCED CHEMICAL VAPOR DEPOSITION - Plasma-enhanced chemical vapor deposition (PECVD) devices enable the generation of a plasma in a plasma zone of a deposition chamber, which reacts with a surface of a substrate to form a deposited film in the fabrication of a semiconductor component. The plasma generator is often positioned over the center of the substrate, and the generated plasma often remains in the vicinity of the plasma generator, resulting in a thicker deposition near the center than at the edges of the substrate. Tighter process control is achievable by positioning one or more electromagnets in a periphery of the plasma zone and supplying power to generate a magnetic field, thereby inducing the charged plasma to achieve a more consistent distribution within the plasma zone and more uniform deposition on the substrate. Variations in the number, configuration, and powering of the electromagnets enable various redistributive effects on the plasma within the plasma zone.

09-18-2014

20150016011

Electrostatic Check with Multi-Zone Control - An electrostatic chuck for clamping a warped workpiece has a clamping surface comprising a dielectric layer. The dielectric layer has a field and one or more zones formed of differing dielectric materials. One or more electrodes are coupled to a power supply, and a controller controls a clamping voltage supplied to the one or more electrodes via the power supply. An electrostatic attraction force associated with each of the field and one or more zones of the dielectric layer of the electrostatic chuck is induced, wherein the electrostatic attraction force varies based on the dielectric material of each of the field and one or more zones. The electrostatic attraction force is greater in the one or more zones than in the field, therein attracting warped regions of the workpiece to the clamping surface and clamping the warped workpiece to the clamping surface across a surface of the warped workpiece.

01-15-2015

20150069580

Alignment Mark and Method of Formation - In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.

03-12-2015

Patent applications by Chia-Ho Chen, Zhubei City TW

Chia-Jung Chen, Zhubei City TW

Patent application number

Description

Published

20090147591

MEMORY CIRCUIT WITH HIGH READING SPEED AND LOW SWITCHING NOISE - A memory circuit with relatively high reading speed and relatively low switching noise is provided. The memory circuit includes an output buffer device having a first input receiving a data signal having a first voltage level, a second input receiving a pre-set voltage having a second voltage level and an output outputting the data signal, and a pre-set circuit constructed by a pair of MOSFETs and providing the pre-set voltage to the second input before the output buffer device receives the data signal. The pre-set circuit receives a control signal activating the pair of MOSFETs at the same time, and when the output buffer device receives the data signal, a voltage level of the second input is swung from the second level to the first voltage level.

06-11-2009

20120075943

Method and Apparatus for Memory Repair With Redundant Columns - A first redundant column is used to repair multiple defects in an array of memory cells. The defects include at least a first defect and a second defect in different main columns of a plurality of main columns in the array. However, all of the multiple defects repaired by the first redundant column are not required to be in different main columns. The array is arranged into a plurality of rows accessed by row addresses and the plurality of main columns accessed by column addresses.

03-29-2012

20120092940

Memory Device and Read Operation Method Thereof - A read operation for a memory device. In response to an input address indicating to read data from a different page, a selected word line, first and second global bit lines and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit lines are kept precharged. A second cell current flowing through the selected word line is generated. A second reference current is generated. A second half page data is read based on the second cell current and the second reference current.

04-19-2012

20150023120

MEMORY DEVICE AND READ OPERATION METHOD THEREOF - A read operation for a memory device is provided. A selected word line, first and second global bit line groups and a selected first bit line group are precharged. A first cell current flowing through the selected word line, the first and the selected first bit line groups is generated. A first reference current flowing through the second global bit line group is generated. A first half page data is read based on the first cell current and the first reference current. The selected word line, the first and the second global bit line groups are kept precharged.

01-22-2015

Patent applications by Chia-Jung Chen, Zhubei City TW

Chia-Nan Chen, Zhubei City TW

Patent application number

Description

Published

20130161667

PATTERNED REFLECTIVE LAYER ON DIELECTRIC LAYER FOR LED ARRAY - A light emitting diode array includes a first light emitting diode with a first electrode and a second light emitting diode with a second electrode. A first dielectric layer is positioned between the light emitting diodes. A first portion of the first dielectric layer at least partially covers the first light emitting diode and a second portion of the first dielectric layer at least partially covers the second light emitting diode. An interconnect is located at least partially on the first dielectric layer. The interconnect connects the first electrode to the second electrode. A reflective layer is formed over at least the first and second portions of the first dielectric layer. A permanent substrate is coupled to a side of the light emitting diodes having the reflective layer.

06-27-2013

Chi-Chang Chen, Zhubei City TW

Patent application number

Description

Published

20130175938

LIGHT SOURCE APPARATUS - A light source apparatus is provided. The light source apparatus comprises an electric-conductive terminal, a control circuit, a first light source device, and a second light source device. The electric-conductive terminal defines a receiving space. The control circuit is disposed within the receiving space of the electric-conductive terminal and is electrically connected to the electric-conductive terminal. The first light source device and the second light source device are both electrically connected to the control circuit. When the control circuit detects a switching signal, the control circuit enables the first light source device to change from a first brightness to a second brightness and enables the second light source device to change from a third brightness to a fourth brightness.

07-11-2013

Chi-Chung Chen, Zhubei City TW

Patent application number

Description

Published

20110047382

FAST AUTHENTICATION BETWEEN HETEROGENEOUS WIRELESS NETWORKS - A method for preparing for handover of an apparatus from a first wireless network to a second, different wireless network, a master session key (MSK) having been generated during establishment of a connectivity of the apparatus to the first wireless network includes detecting signals of the second wireless network. In response thereto, establishing a connectivity of the apparatus to the second wireless network, using a pairwise master key (PMK) derived from the MSK generated during establishment of the connectivity to the first wireless network, one or more encryption keys being derivable from the PMK to support secure communication over the second wireless network.

02-24-2011

Chien-Chon Chen, Zhubei City TW

Patent application number

Description

Published

20100065113

Grooved dye-sensitized solar cell structure and method for fabricating the same - The present invention discloses a grooved dye-sensitized solar cell structure and a method for fabricating the same. The method of the present invention comprises providing a titanium plate having at least one groove; forming insulation layers on the grooves; forming a plurality of titanium dioxide units on the titanium plate each containing a plurality of titanium dioxide nanotubes, wherein each groove is arranged in between two adjacent titanium dioxide units; making the titanium dioxide units absorb a photosensitive dye; forming a transparent conductive film over the insulation layers and the titanium dioxide units; and filling an electrolyte into spaces each enclosed by the transparent conductive film, the titanium dioxide unit, the insulation layers. The present invention not only increases the electron transmission efficiency and photoelectric conversion efficiency but also promote the uniformity of the semiconductor layer.

03-18-2010

20100065114

Dye-sensitized solar cell structure and method for fabricating the same - The present invention discloses a dye-sensitized solar cell structure and a method for fabricating the same. The method of the present invention comprises forming insulation layers on a titanium plate; forming a plurality of titanium dioxide units on the titanium plate each containing a plurality of titanium dioxide nanotubes, wherein each insulation layer is arranged in between two adjacent titanium dioxide units; making the titanium dioxide units absorb a photosensitive dye; forming a transparent conductive film over the insulation layers and the titanium dioxide units; and filling an electrolyte into spaces each enclosed by the transparent conductive film, the titanium dioxide unit, the insulation layers. The present invention not only increases the electron transmission efficiency and photoelectric conversion efficiency but also promote the uniformity of the semiconductor layer.

03-18-2010

Chien-Mao Chen, Zhubei City TW

Patent application number

Description

Published

20140234772

PHOTO RESIST (PR) PROFILE CONTROL - One or more techniques or systems for controlling a profile for photo resist (PR) are provided herein. In some embodiments, a first shield layer is formed on a first PR layer and a second PR layer is formed on the first shield layer. A first window is formed within the second PR layer during a first exposure with a mask. A second window is formed within the first shield layer based on the first window. A third window is formed within the first PR layer during a second exposure without a mask. Because, the third window is formed while the first shield layer and the second PR layer are on the first PR layer, a profile associated with the first PR layer is controlled. Contamination during ion bombardment is mitigated due to the controlled profile.

08-21-2014

20150021700

SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a shallow trench isolation (STI) structure. The semiconductor structure includes a substrate having a first surface. A STI structure extends from the first surface into the substrate. The STI structure includes a first portion and a second portion. The first portion extends from the first surface into the substrate, and has an intersection with the first surface. The second portion extends away from the first portion, and has a tip at a distance away from the intersection in a direction parallel to the first surface. The first portion and the second portion are filled with a dielectric material.

01-22-2015

Chihchung (gary) Chen, Zhubei City TW

Patent application number

Description

Published

20140043775

Compliable Units and Compliable Network Having the Same - A compliable unit in an compliable network comprises a first layer including at least one device component at a first region of the first layer, and a second layer including at least one compliable element at a first region of the second layer to transfer the at least one device component to a desired location. The first layer and the second layer are arranged in a stack.

02-13-2014

20140241845

Apparatus and Method of Batch Assembly - The present disclosure is directed to an apparatus and method of batch assembly. The apparatus for batch assembly may include a plurality of spring units, a plurality of handling units, and a control unit. The method of batch assembly may include aligning an array of devices with a plurality of handling units, attaching the array of devices onto the handling units, expanding the handling units so as to expand the array of devices from a first area to a second area, and transferring the array of devices to a destination.

08-28-2014

Chin-Hsing Chen, Zhubei City TW

Patent application number

Description

Published

20100065113

Grooved dye-sensitized solar cell structure and method for fabricating the same - The present invention discloses a grooved dye-sensitized solar cell structure and a method for fabricating the same. The method of the present invention comprises providing a titanium plate having at least one groove; forming insulation layers on the grooves; forming a plurality of titanium dioxide units on the titanium plate each containing a plurality of titanium dioxide nanotubes, wherein each groove is arranged in between two adjacent titanium dioxide units; making the titanium dioxide units absorb a photosensitive dye; forming a transparent conductive film over the insulation layers and the titanium dioxide units; and filling an electrolyte into spaces each enclosed by the transparent conductive film, the titanium dioxide unit, the insulation layers. The present invention not only increases the electron transmission efficiency and photoelectric conversion efficiency but also promote the uniformity of the semiconductor layer.

03-18-2010

20100065114

Dye-sensitized solar cell structure and method for fabricating the same - The present invention discloses a dye-sensitized solar cell structure and a method for fabricating the same. The method of the present invention comprises forming insulation layers on a titanium plate; forming a plurality of titanium dioxide units on the titanium plate each containing a plurality of titanium dioxide nanotubes, wherein each insulation layer is arranged in between two adjacent titanium dioxide units; making the titanium dioxide units absorb a photosensitive dye; forming a transparent conductive film over the insulation layers and the titanium dioxide units; and filling an electrolyte into spaces each enclosed by the transparent conductive film, the titanium dioxide unit, the insulation layers. The present invention not only increases the electron transmission efficiency and photoelectric conversion efficiency but also promote the uniformity of the semiconductor layer.

03-18-2010

Chu-Fu Chen, Zhubei City TW

Patent application number

Description

Published

20120084033

Method for Measuring Capacitances of Capacitors - A capacitor measurement circuit for measuring a capacitance of a test capacitor includes a first transistor with a first source-drain path coupled between a first capacitor plate of the test capacitor and a ground; a second transistor with a second source-drain path coupled between a second capacitor plate of the test capacitor and the ground; and a current-measuring device configured to measure a first charging current and a second charging current of the test capacitors. The first and the second charging currents flow to the test capacitor in opposite directions.

04-05-2012

20130299919

MOS Devices with Mask Layers and Methods for Forming the Same - A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask.

11-14-2013

Chung-Ching Chen, Zhubei City TW

Patent application number

Description

Published

20120272080

Multi-Core Electronic System and Associated Rate Adjustment Device - A multi-core electronic system for accessing a data storage device includes a plurality of processors, a data transmission interface and a rate adjustment module. The processors respectively provide a bandwidth requirement, and communicate with the data storage device via the shared data transmission interface. The rate adjustment module receives the bandwidth requirements, and determines a transmission rate of the data transmission interface according to the bandwidth requirements.

10-25-2012

20140293726

MEMORY CONTROLLER AND ASSOCIATED METHOD FOR GENERATING MEMORY ADDRESS - A memory controller is connected to a double-data-rate dynamic random access memory (DDR DRAM) and an accessing unit. The memory controller includes: a processing unit, configured to receive a system address generated by the accessing unit; and a mapping unit, located in the processing unit, configured to convert the system address to a memory address and transmitting the memory address to the DDR DRAM. When a burst length of the DDR DRAM is L and L=2

10-02-2014

20140325465

CHIP WITH FLEXIBLE PAD SEQUENCE MANIPULATION AND ASSOCIATED METHOD - A chip with flexible pad sequence manipulation is provided. The chip can be a memory controller, and includes a hub unit. The hub unit, formed by a gate array, is placed in a hub region predetermined during placing and routing procedures, and is capable of supporting re-placing and re-routing for changing interior interconnections and a pad sequence of the chip.

10-30-2014

20140379976

MEMORY CONTROLLER AND ASSOCIATED SIGNAL GENERATING METHOD - A memory controller and an associated signal generating method are provided. A generating sequence of commands is properly arranged to enlarge latching intervals of an address signal and a bank signal for stable access of a DDR memory module.

12-25-2014

20150062138

TIMING CONTROLLER FOR IMAGE DISPLAY AND ASSOCIATED CONTROL METHOD - A timing controller for a panel display system includes: an image signal receiver that receives an image signal; an overdrive circuit that receives and converts the image signal from the image signal receiver according to successive first frame data and second frame data in the image signal; an image signal transmitter that receives the converted image signal from the overdrive circuit and transmits the same to a display panel; a memory; and a memory interface unit. In a normal read/write period, the memory interface unit receives the first frame data from the overdrive circuit and stores the same in the memory, and fetches the first frame data from the memory when the overdrive circuit receives the second frame data in the image signal and transmits the same to the overdrive circuit. The memory interface unit further obtains sampling results to generate a preferred delay phase.

03-05-2015

Patent applications by Chung-Ching Chen, Zhubei City TW

Chung-Nan Chen, Zhubei City TW

Patent application number

Description

Published

20140273459

Systems and Methods for a Narrow Band High Transmittance Interference Filter - The present disclosure provides an interference filter, a lithography system incorporating an interference filter, and a method of fabricating an interference filter. The interference filter includes a transparent substrate having a front surface and a back surface, a plurality of alternating material layers formed over the front surface of the transparent substrate that form a bandpass filter, and an anti-reflective structure formed over the back surface of the transparent substrate. The alternating material layers alternate between a relatively high refractive index material and a relatively low refractive index material.

09-18-2014

20140340665

ULTRAVIOLET LIGHT EMITTING DIODE ARRAY LIGHT SOURCE FOR PHOTOLITHOGRAPHY AND METHOD - A light source includes a plurality of ultraviolet (UV) light emitting diodes (LEDs) and an LED phase shift controller coupled to the plurality of UV LEDs adapted to control the phase shift of each UV LED in the plurality of UV LEDs. The plurality of UV LEDs forms a UV LED array. An ultraviolet lithography system can include a light source as described above. The system can further include a mirror assembly in a light path of the light source, the mirror assembly having a polarization mirror with an interference coating. A method provides a light source for an ultraviolet lithography system including the element of providing an plurality of UV LEDs that emit UV light and the element of controlling a phase shift of the plurality of UV LEDs with an LED phase shift controller coupled to each UV LED or arrays of the UV LEDs in the plurality of UV LEDs.

11-20-2014

Chun-Jen Chen, Zhubei City TW

Patent application number

Description

Published

20130241755

TIMING CALIBRATION CIRCUIT FOR TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER AND ASSOCIATED METHOD - A timing calibration circuit for a time-interleaved analog-to-digital converter (ADC) is provided. The timing calibration circuit includes a correlation unit, an adaptive filter and a delay cell. The correlation unit generates a first correlation coefficient according to a first zero-crossing possibility distribution between a first digital data and a second digital data, and generates a second correlation coefficient according to a second zero-crossing possibility distribution between the second digital data and a third digital data. The adaptive filter generates a predicted time skew according to a difference between the first correlation coefficient and the second correlation coefficient. The delay cell calibrates a clock signal of the ADC according to the predicted time skew.

09-19-2013

Frederick T. Chen, Zhubei City TW

Patent application number

Description

Published

20120243346

Control Method for Memory Cell - A control method for at least one memory cell. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor in series between a first node and a second node. In a programming mode, the memory cell is programmed. When it is determined that the memory cell has been successfully programmed, impedance of the memory cell is in a first state. When it is determined that the memory cell has not been successfully programmed, a specific action is executed to reset the memory cell. The impedance of the memory cell is in a second state after the step resetting the memory cell. The impedance of the memory cell in the second state is higher than that of the memory cell in the first state.

09-27-2012

20130001494

Memory Cell - A memory cell includes a memory element, a current-limiting element electrically coupled to the memory element, and a high-selection-ratio element electrically coupled to the current-limiting element. The memory element is configured to store data as a resistance state. The current-limiting element is a voltage-controlled resistor (VCR) having a resistance that decreases when a voltage applied thereto increases. The high-selection-ratio element has a first resistance that is small when a voltage applied to the memory cell is approximately equal to a selection voltage of the memory cell, and has a second resistance that is substantially larger than the first resistance when the voltage applied to the memory cell is approximately equal to one-half of the selection voltage.

01-03-2013

Han Ying Chen, Zhubei City TW

Patent application number

Description

Published

20130206357

Cooling Apparatus and Method - A cooling apparatus includes a shell adapted to hermetically store liquid water, a heat exchanging structure adapted to receive a substance to cool down, and a vacuum pump. The heat exchanging structure has one or more heat transfer walls, each of the heat transfer walls having a first surface in contact with the liquid water stored in the shell, and a second surface in contact with the substance to cool down. The vacuum pump is operable to create a partial vacuum on a surface of the liquid water, whereby causing a decrease in a temperature of the liquid water in the shell. In other embodiments, methods of cooling a substance are also described.

08-15-2013

Heng-Yin Chen, Zhubei City TW

Patent application number

Description

Published

20140062856

FOLDABLE DISPLAY AND IMAGE PROCESSING METHOD THEREOF - A foldable display and an image processing method thereof are disclosed. The foldable display comprises a display module, a memory, a sensor module, and a processing unit. The sensor module senses a bending state of the display module. The processing unit generates adjusted images according to an image signal, and stores those adjusted images to a plurality of memory addresses of the memory. The processing unit selects a reading address from those memory addresses according the bending state. The processing unit selects a corresponding adjusted image from the memory according to the reading address and outputs the corresponding adjusted image to the display module.

03-06-2014

Hou-Yu Chen, Zhubei City TW

Patent application number

Description

Published

20130193446

FINFET AND METHOD OF FABRICATING THE SAME - The disclosure relates to a fin field effect transistor (FinFET). An exemplary structure for a FinFET comprises a substrate comprising a major surface; a first fin and a second fin extending upward from the substrate major surface to a first height; an insulation layer comprising a top surface extending upward from the substrate major surface to a second height less than the first height, whereby portions of the fins extend beyond the top surface of the insulation layer; each fin covered by a bulbous epitaxial layer defining an hourglass shaped cavity between adjacent fins, the cavity comprising upper and lower portions, wherein the epitaxial layer bordering the lower portion of the cavity is converted to silicide.

08-01-2013

20130285141

Multi-Gate Devices with Replaced-Channels and Methods for Forming the Same - A device includes a semiconductor substrate, isolation regions in the semiconductor substrate, and a Fin Field-Effect Transistor (FinFET). The FinFET includes a channel region over the semiconductor substrate, a gate dielectric on a top surface and sidewalls of the channel region, a gate electrode over the gate dielectric, a source/drain region, and an additional semiconductor region between the source/drain region and the channel region. The channel region and the additional semiconductor region are formed of different semiconductor materials, and are at substantially level with each other.

10-31-2013

20140134831

FINFET AND METHOD OF FABRICATING THE SAME - A method of fabricating a fin field effect transistor (FinFET) comprises providing a substrate comprising a major surface, forming a first and second fin extending upward from the substrate major surface to a first height, forming an insulation layer comprising a top surface extending upward from the substrate major surface to a second height less than the first height, wherein a portion of the first and second fin extend beyond the top surface of the insulation layer. The method also includes selectively growing an epitaxial layer covering each fin, annealing the substrate to have each fin covered by a bulbous epitaxial layer defining an hourglass shaped cavity between adjacent fins, wherein the cavity comprises an upper and lower portion. The method includes forming a metal material over the bulbous epitaxial layer and annealing the substrate to convert the bulbous epitaxial layer bordering the lower portion of the cavity to silicide.

05-15-2014

20140231924

Method For Fabricating A Multi-Gate Device - A device includes a wafer substrate including an isolation feature, at least two fin structures embedded in the isolation feature, and at least two gate stacks disposed around the two fin structures respectively. A first inter-layer dielectric (ILD) layer is disposed between the two gate stacks, with a dish-shaped recess formed therebetween, such that a bottom surface of the recess is below the top surface of the adjacent two gate stacks. A second ILD layer is disposed over the first ILD layer, including in the dish-shaped recess. The second ILD includes nitride material; the first ILD includes oxide material.

08-21-2014

Hsiang-Fu Chen, Zhubei City TW

Patent application number

Description

Published

20140035072

HYBRID MEMS BUMP DESIGN TO PREVENT IN-PROCESS AND IN-USE STICTION - A micro-electro-mechanical systems (MEMS) device and method for forming a MEMS device is provided. A proof mass is suspended a distance above a surface of a substrate by a fulcrum. A pair of sensing plates are positioned on the substrate on opposing sides of the fulcrum. Metal bumps are associated with each sensing plate and positioned near a respective distal end of the proof mass. Each metal bump extends from the surface of the substrate and generally inhibits charge-induced stiction associated with the proof mass. Oxide bumps are associated with each of the pair of sensing plates and positioned between the respective sensing plate and the fulcrum. Each oxide bump extends from the first surface of the substrate a greater distance than the metal bumps and acts as a shock absorber by preventing the distal ends of the proof mass from contacting the metal bumps during shock loading.

02-06-2014

Hsien-Te Chen, Zhubei City TW

Patent application number

Description

Published

20110303446

EPOXY RESIN COMPOSITION, AND PREPREG AND PRINTED CIRCUIT BOARD USING THE SAME - Disclosed is an epoxy resin composition for printed circuit board, which includes (A) an epoxy resin; (B) a composite curing agent, including amino-triazine-novolac resin, diaminodiphenylsulfone, and dicyandiamide mixed in a certain proportion; (C) a curing accelerator; and (D) an optional inorganic filler.

12-15-2011

Hsin-Hung Chen, Zhubei City TW

Patent application number

Description

Published

20120328041

DEVICES OF IQ MISMATCH CALIBRATION, AND METHODS THEREOF - The device with IQ mismatch compensation includes a transmitter oscillator, a transmitter module, and a loop-back module. The transmitter module is arranged to up-convert a transmitter signal with the oscillator signal to generate an RF signal. The loop-back module is arranged to down-convert the RF signal with the oscillator signal to determine a transmitter IQ mismatch parameter, and effects of IQ mismatch of the loop-back module are calibrated by inputting a test signal and the oscillator signal before the down-converting of the RF signal. The transmitter module is arranged to reduce effects of IQ mismatch of a transmitter path in the transmitter module according to the transmitter IQ mismatch parameter.

METHOD FOR COMPENSATING THE FREQUENCY DEPENDENT PHASE IMBALANCE - A method for compensating the frequency dependent phase imbalance in a transmitter is provided. The transmitter processes a baseband signal. The method includes the following steps: (a) compensating the baseband signal with a predetermined delay amounts; (b) inputting the compensated baseband signal to an upconversion circuit to generate a radio frequency (RF) signal; (c) inputting the RF signal to a delay information extractor to obtain a correlation value related to the information of the predetermined delay amount; (d) changing the predetermined delay amount and compensating the baseband signal again with the changed predetermined delay amount, and performing steps (b) and (c) again to update the correlation value; and (e) selecting a candidate delay amount from the predetermined delay amount according to the correlation value, and compensating the transmitter by using the candidate delay amount.

10-09-2014

20140376660

DEVICES OF IQ MISMATCH CALIBRATION, AND METHODS THEREOF - A device with IQ mismatch compensation, having a transmitter oscillator, for providing an oscillator signal, a transmitter module, for up-converting a transmitter signal with the oscillator signal to generate an RF signal, and a loop-back module, for down-converting the RF signal with the oscillator signal to determine a transmitter IQ mismatch parameter, wherein effects of IQ mismatch of the loop-back module are calibrated by inputting a test signal and the oscillator signal before the down-converting of the RF signal. The transmitter module is arranged to reduce effects of IQ mismatch of a transmitter path in the transmitter module according to the determined transmitter IQ mismatch parameter.

12-25-2014

Patent applications by Hsin-Hung Chen, Zhubei City TW

Huang-Ming Chen, Zhubei City TW

Patent application number

Description

Published

20120289731

PHOTO-CROSSLINKABLE LIQUID CRYSTAL MONOMERS WITH OPTICAL ACTIVITY - The present invention relates to photo-crosslinkable liquid crystal monomers with optical activity. The liquid crystal monomers contains one chiral center with an acrylate group or terminal diacrylate groups, and terminal dibenzene rings are introduced in order to extend its hard segment for the purpose of getting a wider liquid crystalline phase. By introducing the liquid crystal monomers, the room temperature nematic liquid crystal or the cholesteric liquid crystal may have a better mutual solubility and a wider, steadier structure of liquid crystal. The liquid crystal monomers have the following formula structure:

11-15-2012

Hung-Yueh Chen, Zhubei City TW

Patent application number

Description

Published

20130313626

Methods and Apparatus for Non-Volatile Memory Cells - Methods and apparatus for non-volatile memory cells. A memory cell includes a floating gate formed over a substrate with a tunneling dielectric over an upper surface of the floating gate and an erase gate over the tunneling dielectric. Sidewall dielectrics enclose the tunneling dielectric. Assist gates and coupling gates are formed on either side of the memory cell and are spaced from the floating gate of the memory cell by the sidewall dielectrics. Methods for forming memory cells include depositing a floating gate over a dielectric layer over a semiconductor substrate, depositing a tunneling dielectric over the floating gate, depositing an erase gate over the tunneling dielectric, patterning the erase gate, tunneling dielectric and floating gate to form memory cells having vertical sides, and depositing sidewall dielectrics on the vertical sides of the memory cells to seal the tunneling dielectrics. Additional steps are performed to complete the cells.

11-28-2013

Isaac Chen, Zhubei City TW

Patent application number

Description

Published

20110109238

Digital dimming device and digital dimming method - The present invention discloses a digital dimming device and a digital dimming method, for controlling a plurality of light emitting device channels. The method comprises: generating a corresponding plurality of driving signals to control the plurality of light emitting device channels; receiving a PWM input signal having a duty ratio, and phase shifting the PWM input signal to generate multiple PWM output signals with about the same duty ratio as the PWM input signal, but with respectively shifted phases; and enabling or disabling corresponding driving signals by the multiple PWM output signals, respectively.

05-12-2011

20140055178

ADAPTIVE PHASE-SHIFTED SYNCHRONIZATION CLOCK GENERATION CIRCUIT AND METHOD FOR GENERATING PHASE-SHIFTED SYNCHRONIZATION CLOCK - The present invention discloses an adaptive phase-shifted synchronization clock generation circuit and a method for generating phase-shifted synchronization clock. The adaptive phase-shifted synchronization clock generation circuit includes: a current source generating a current which flows through a node to generate a node voltage on the node; a reverse-proportional voltage generator coupled to the node for generating a voltage which is reverse-proportional to the node voltage; a ramp generator receiving a synchronization input signal and generating a ramp signal; a comparator comparing the reverse-proportional voltage to the ramp signal; and a pulse generator for generating a clock signal according to an output from the comparator.

02-27-2014

Issac Y. Chen, Zhubei City TW

Patent application number

Description

Published

20140042515

HIGH VOLTAGE DEVICE - The present invention provides a high voltage device including a shielding metal layer to reduce the noise interference from a high voltage source. The high voltage device includes a substrate, a field oxide layer, a gate layer, a shielding metal layer, and a high voltage interconnection line. The substrate includes a first doped region and a second doped region separated from each other. The field oxide layer is disposed on the substrate. The gate layer is disposed above the field oxide layer. The high voltage interconnection line is coupled to the first doped region and passes above but not below the first shielding metal layer.

02-13-2014

Jia-Liang Chen, Zhubei City TW

Patent application number

Description

Published

20110279175

SYSTEM AND METHOD FOR RC CALIBRATION USING PHASE AND FREQUENCY - An RC filter is calibrated to a desired cutoff frequency by initializing the filter with a cutoff frequency. An input signal is filtered by the RC filter to provide a filter output signal having phase and frequency values. The cutoff frequency of the RC filter is adjusted based on the phase and frequency values of the filter output signal if the phase and frequency values do not satisfy a predetermined condition. The filtering and adjusting are repeated until the phase and frequency values of the filter output signal satisfy the predetermined condition. A calibration apparatus has a frequency generator, a resistor-capacitor (RC) filter, a phase comparator, a frequency detector, and a state machine. The phase comparator, frequency detector, and state machine are configured to calibrate the RC filter to a cutoff frequency specified by the reference signal based on a filter output signal of the RC filter.

11-17-2011

20120098592

FILTER AUTO-CALIBRATION USING MULTI-CLOCK GENERATOR - A filter auto-calibration system includes a multi-clock module. The multi-clock module includes a multi-clock generator that is configured to generate a clock signal with a variable frequency based on a channel setting. There is at least one filter to be calibrated. An auto-calibration control module is configured to control calibration of the at least one filter based on the channel setting. The multi-clock module is configured to supply the variable frequency clock signal to the at least one filter and to the auto-calibration control module, and the at least one filter is coupled to the auto-calibration control module.

04-26-2012

20140292400

FILTER AUTO-CALIBRATION USING MULTI-CLOCK GENERATOR - A filter auto-calibration system comprises a multi-clock module that includes a multi-clock generator configured to generate a first variable frequency signal based on a channel setting, the multi-clock generator comprising a quadrature signal generator configured to generate an in-phase component and a quadrature component of the first variable frequency signal; and a mixer configured to generate an in-phase component and a quadrature component of a quadrature signal from a received signal other than the first variable frequency signal. The system also comprises at least one filter to be calibrated, and an auto-calibration control module coupled to the multi-clock module and the at least one filter, the auto-calibration control module configured to receive the in-phase component and quadrature component of the first variable frequency signal from the multi-clock module, and configured to control calibration of the at least one filter based on the channel setting.

10-02-2014

Patent applications by Jia-Liang Chen, Zhubei City TW

Jian-Yuan Chen, Zhubei City TW

Patent application number

Description

Published

20130064973

Chamber Conditioning Method - A system and method for conditioning a chamber is disclosed. An embodiment comprises utilizing the deposition chamber to deposit a first layer and conditioning the deposition chamber. The conditioning the deposition chamber can be performed by depositing a heterogeneous material over the first layer. The heterogeneous material can cover and encapsulate the first layer, thereby preventing particles of the first layer from breaking off and potentially landing on a substrate during a subsequent processing run.

03-14-2013

Ji-Huei Chen, Zhubei City TW

Patent application number

Description

Published

20110315608

SURFACE MOUNT PROCESS, SURFACE MOUNT SYSTEM, AND FEEDING APPARATUS THEREOF - A surface mount process, a surface mount system, and a feeding apparatus thereof are provided. The surface mount system includes a feeding apparatus and a surface mount apparatus. The feeding apparatus includes a vibrating tray feeder module, a vibrating linear feeder module, and a component recycling module. The vibrating tray feeder module has a circular vibrating conveyer belt with a vibrating tray output end. The vibrating linear feeder module has a linear vibrating conveyer belt connected to the vibrating tray output end and has a linear vibrating output end opposite the vibrating tray feeder module. The component recycling module is disposed under the vibrating tray feeder module to recycle the rejected components. The surface mount apparatus has a component receiving unit corresponding to the linear vibrating output end of the vibrating linear feeder module.

12-29-2011

Jun-Chen Chen, Zhubei City TW

Patent application number

Description

Published

20110062996

POWER ON DETECTION CIRCUIT - A power-on-detection (POD) circuit includes first and second comparators, a voltage divider, a detection circuit coupled to a first voltage source node and the voltage divider, and logic circuitry coupled to outputs of the first and second comparators. The detection circuit outputs a control signal identifying if a first voltage source node has a voltage potential that is higher than ground. The control signal turns on and off the first and second comparators, which are respectively coupled to first and second nodes of the voltage divider and to a reference voltage node. The logic circuitry outputs a power identification signal based on the signals received from the outputs of the first and second comparators.

03-17-2011

20140354306

POWER ON DETECTION CIRCUIT - A power-on-detection (POD) circuit includes a detection circuit, first and second comparison circuits, and logic circuitry. The detection circuit includes a capacitor configured to charge from a first voltage level to a second voltage level. The first comparison circuit is configured to compare a third voltage level to a reference voltage level, and the second comparison circuit is configured to compare a fourth voltage level to the reference voltage level. The third and fourth levels are based on the second voltage level. The logic circuitry is coupled to an output of the first comparison circuit and to an output of the second comparison circuit and is configured to output a power identification signal based on the outputs of the first and second comparison circuits. The detection circuit is configured to turn on the first and second comparison circuits based on a voltage level of the capacitor.

12-04-2014

Jyehong Chen, Zhubei City TW

Patent application number

Description

Published

20110170876

SYSTEM AND METHOD FOR TRANSMITTING SIGNALS - A signal-transmitting system includes a digital-to-analog converter, an optical modulator, first and second electrodes, an optical phase shifter, and an optical coupler. The digital-to-analog converter converts digital data into an electrical analog signal. The optical modulator includes a first optical waveguide configured to transmit a first optical carrier, a second optical waveguide configured to transmit a second optical carrier, a first electrode positioned on the first optical waveguide, and a second electrode positioned on the second optical waveguide. The first and second electrical couplers are configured to couple respective electrical analog signals and electrical carriers to electrodes to generate modulation waves. The modulation waves are different in phase. The optical phase shifter is configured to shift the second modulation wave by a predetermined phase, and the optical coupler is configured to couple the first and second modulation waves to generate an optical output signal.

07-14-2011

20110170879

FREQUENCY UP-CONVERSION SYSTEM AND METHOD FOR THE SAME - A frequency up-conversion system includes an optical splitter, an optical modulator, an optical phase-shifter, and an optical coupler. In one embodiment of the present disclosure, the optical splitter is configured to split an optical wave into a first optical wave and a second optical wave, the optical modulator is configured to modulate the first optical wave to form a modulation wave, the optical phase-shifter is configured to shift the phase of the second optical wave by a predetermined phase to form a shifting wave, and the optical coupler is configured to couple the modulation wave and the shifting wave. In one embodiment of the present disclosure, the optical modulator and the optical phase-shifter are connected in a parallel manner.

07-14-2011

Kuang-Jung Chen, Zhubei City TW

Patent application number

Description

Published

20130187135

LIGHT EMITTING DEVICE - A light emitting device includes a substrate, and a plurality of light emitting structures disposed thereon. Each of the light emitting structures includes an auxiliary electrode disposed on the substrate, a first insulating layer disposed on the substrate and covering the auxiliary electrode, an electrode disposed on the first insulating layer, a second insulating layer disposed on the first insulating layer and having a first opening exposing the electrode, an organic light emitting layer disposed in the first opening, a cathode disposed on the organic light emitting layer, at least a conductive structure penetrating through the first insulating layer and the second insulating layer, and a closed ring structure disposed on the second insulating layer and around the cathode, wherein a thickness of the closed ring structure is larger than that of the cathode.

07-25-2013

20140268606

PACKAGE OF ENVIRONMENTALLY SENSITIVE ELECTRONIC DEVICE AND FABRICATING METHOD THEREOF - A package of an environmentally sensitive electronic device and a fabricating method thereof are provided, wherein the package may include a first substrate, a second substrate, the environmentally sensitive electronic device, a packaging body, and a filler. In one or more embodiments, the environmentally sensitive electronic device may be disposed on the first substrate and located between the first substrate and the second substrate. The filler is disposed between the first substrate and the second substrate and covers the environmentally sensitive electronic device. The packaging body is sandwiched between the first substrate and the second substrate and encloses the environmentally sensitive electronic device and the filler. A material for the packaging body may include a bonding of transition metal and metalloid.

09-18-2014

Kuo-Chang Chen, Zhubei City TW

Patent application number

Description

Published

20120262603

Image Capturing Device and Image Processing Method Thereof - An image capturing device and an image processing method thereof are disclosed. The image capturing device comprises an image capturing module, a storage module and a processing module. The processing module, comprising a plurality of buffers, controls the image capturing module to capture the first image data, saves the first image data in the plurality of buffers sequentially, conducts image processing correspondingly, and generates processed data. Soon, the processing module conducts an image compression on the processed data and saves the processed data in the storage module. In addition, while conducting the image compression, the processing module controls the image capturing module to capture the second image data, saves the first image data in the plurality of buffers sequentially, and conducts image processing correspondingly.

10-18-2012

Kuo-Chou Chen, Zhubei City TW

Patent application number

Description

Published

20130043120

SPUTTERING TARGET WITH REVERSE EROSION PROFILE SURFACE AND SPUTTERING SYSTEM AND METHOD USING THE SAME - A sputtering target is provided that includes a planar backing plate and a target material formed over the planar backing plate and including an uneven sputtering surface including thick portions and thin portions and configured in conjunction with a sputtering apparatus such as a magnetron sputtering tool with a fixed magnet arrangement. The uneven surface is designed in conjunction with the magnetic fields that will be produced by the magnet arrangement such that the thicker target portions are positioned at locations where target erosion occurs at a high rate. Also provided is the magnetron sputtering system and a method for utilizing the target with uneven sputtering surface such that the thickness across the target to become more uniform in time as the target is used.

02-21-2013

Liang-Jung Chen, Zhubei City TW

Patent application number

Description

Published

20130257836

DISPLAY DEVICE WITH SCAN DRIVER - A display device includes a plurality of pixel circuits arranged in a plurality of rows and columns, a plurality of scan lines, a plurality of data lines, a scan driver operable to drive the rows of the pixel circuits in sequence via the scan lines, and a data driver coupled to the columns of the pixel circuits via the data lines. The scan lines include first and second sets of scan lines alternately disposed with each other. For each of the first and second sets of the scan lines, adjacent scan lines have different circuit properties. The scan driver activates each of the scan lines for a respective activation time period according to the circuit property thereof.

10-03-2013

Lin-Chien Chen, Zhubei City TW

Patent application number

Description

Published

20110156930

Capacitive Touch Panel with High Touching Sensitivity - A capacitive touch panel has a plurality of first conductor lines and a plurality of second conductor lines. The first conductor lines are disposed in a first direction for sensing a contact with an object. The second conductor lines are disposed in a second direction to be intersected insulatively with the first conductor lines so as to define an overlapping region at each intersection of a first conductor line and a second conductor line. As a driving signal is applied to one of the second conductor lines, the overlapping region defined at the intersection forms a capacitance. Each of the first conductor lines defines at least one opening in each of the overlapping regions.

06-30-2011

Lung-Pao Chen, Zhubei City TW

Patent application number

Description

Published

20120261154

STRUCTURE FOR ADJUSTING POSITIVE OR REVERSE ROTATION OF PNEUMATIC TOOL - A structure for adjusting positive or reverse rotation of a pneumatic tool is proposed to be mainly composed of an outer casing, a driving device and a knob. An air controlling part arranged on the outer casing leads air to be transmitted from an air incoming chamber in the outer casing to the driving device through a reducing air intake. A bearing seat is arranged in the driving device. The knob arranged on the outer casing extends with an annular wall for separating air incoming from air discharging. An armature slot formed at the annular wall connects to and communicates with the bearing seat. The annular wall has a protrusion formed with a first air intake allowed to communicate with a positive or reverse air intake. Thereby, the first air intake can adjusted to be aligned with the positive or reverse air intake by rotation of the knob.

AIRTIGHT GASKET FOR PNEUMATIC TOOL - An airtight gasket for a pneumatic tool including an airflow regulation portion, an air intake passage to direct high pressure air into the airflow regulation portion and a pneumatic motor to receive the high pressure air from the airflow regulation portion and generate spinning. The airflow regulation portion includes a regulation valve which contains a flow directing vent corresponding to the air intake passage and a recess surrounding the flow directing vent. The airtight to gasket is clamped between the regulation valve and air intake passage, and includes a base located in the recess, a through-hole located on the base to channel the high pressure air into the flow directing vent, and an airtight convex ring surrounded the through-hole and extended integrally from the base towards to air intake passage.

07-31-2014

20140209342

PNEUMATIC HAND TOOL - A pneumatic hand tool comprises a housing, a pneumatic motor held in the housing and an airflow regulation valve to control spinning direction of the pneumatic motor. The housing includes a handgrip and a holding portion connected to the handgrip. The handgrip has an airflow passage to receive driving airflow. The holding portion has a housing chamber to house the pneumatic motor and airflow regulation valve, and also has a first wall opposing the handgrip and a flow channeling chamber integrally extended from the first wall towards the housing chamber. The flow channeling chamber has a first directing vent located on the first wall and communicated with the airflow passage to receive the driving airflow and a second directing vent communicated with the airflow regulation valve to output the driving airflow to drive the pneumatic motor.

07-31-2014

Mars Chen, Zhubei City TW

Patent application number

Description

Published

20120134209

Single-Transistor EEPROM Array and Operation Methods - A method includes performing an operation on an electrically erasable programmable read-only memory (EEPROM) array. The operation is selected from a program operation and an erase operation. The EEPROM array includes EEPROM cells arranged in rows and columns, and a plurality of word-lines extending in a column direction. Each of the plurality of word-lines is connected to control gates of the EEPROM cells in a same column. The EEPROM array further includes a plurality of source-lines extending in a row direction. Each of the plurality of source-lines is connected to sources of the EEPROM cells in a same row. During the operation, a first source-line in the plurality of source-lines is applied with a first source-line voltage, and a second source-line in the plurality of source-lines is applied with a second source-line voltage different from the first source-line voltage.

05-31-2012

Mei Lan Chen, Zhubei City TW

Patent application number

Description

Published

20120280432

METHOD FOR MANUFACTURING BIOABSORBABLE STENTS - A method for manufacturing a bioabsorbable stent and an apparatus for doing the same are disclosed. The method includes providing a polymer resin, melting the polymer resin to form a molten hollow parison, cooling the molten hollow parison to form a hot hollow parison, elongating the hot hollow parison, expanding the hot hollow parison by feeding a compressed gas into the hot hollow parison to form a stent preform, and patterning the stent preform to form a bioabsorbable stent.

11-08-2012

Ming-Chou Chen, Zhubei City TW

Patent application number

Description

Published

20100166966

SULFONATED POLYETHER ETHER KETONE KETONE, FILM UTILIZING THE SAME, AND METHOD FOR MANUFACTURING THE SAME - A series of crosslinkable sulfonated poly(ether ketone)s containing cycloalkenyl groups were synthesized by aromatic nucleophilic substitution reaction. To decrease the swelling of fuel cell membranes, crosslinking of theses polymers by radical polymerization has been explored. These polymeric films exhibit good thermal and oxidative stability, and good dimensional stability in hot water. The proton conductivity of one example at room temperature is 7.52*10

07-01-2010

P.c. Chen, Zhubei City TW

Patent application number

Description

Published

20080277785

PACKAGE STRUCTURE FOR INTEGRATED CIRCUIT DEVICE AND METHOD OF THE SAME - A package structure for packaging at least one of a plurality of integrated circuit devices of a wafer is provided. The package structure includes an extension metal pad, a first conductive bump and an insulator layer. The extension metal pad electrically contacts the at least one of the plurality of integrated circuit devices. The first conductive bump is located on the extension metal pad. The insulator layer is located over the at least one of the plurality of integrated circuit devices and on a sidewall of it.

11-13-2008

20100229375

METHOD FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE HAVING ANTENNA CONDUCTORS - A method for manufacturing an integrated circuit device having antenna conductors is provided. The method includes the steps of providing a wafer with a plurality of integrated circuit components; forming a first antenna conductor on the surface of each integrated circuit component; forming a plurality of metal bumps above the first antenna conductor; coating an insulating layer to encapsulate the plurality of integrated circuit components and to cover the plurality of metal bumps; removing a portion of the insulating layer to expose a top portion of each metal bump; and forming a second antenna conductor on the insulating layer by screen printing.

09-16-2010

20100267204

PACKAGE STRUCTURE FOR INTEGRATED CIRCUIT DEVICE AND METHOD OF THE SAME - A package structure for packaging at least one of a plurality of intergraded circuit devices of a wafer is provided. The package structure includes an extension metal pad, a first conductive bump and an insulator layer. The extension metal pad electrically contacts the at least one of the plurality of intergraded circuit devices. The first conductive bump is located on the extension metal pad. The insulator layer is located over the at least one of the plurality of intergraded circuit devices and on a sidewall of it.

10-21-2010

Pei-Shin Chen, Zhubei City TW

Patent application number

Description

Published

20130082665

Charger Calibrating Device and Calibrating Method Thereof - A charger calibrating device and a calibrating method thereof. The device comprises a control module and a processing module. The control module controls a charger to be calibrated to perform a first stage charging and a second stage charging on an electronic device. The processing module performs an adjusting process according to the second stage charging time for adjusting the high level period of the PWM signal in the charging circuit of the charger. In the adjusting process, generating an updated high level period by adding or decreasing a preset adjusting amplitude, and decrease the preset adjusting amplitude by half to generate an updated adjusting amplitude. The processing module terminates the calibrating process after repeating the aforementioned calibrating loop a preset number of times.

04-04-2013

Pei-Yuan Chen, Zhubei City TW

Patent application number

Description

Published

20140203730

LIGHT EMITTING DEVICE POWER SUPPLY CIRCUIT, LIGHT EMITTING DEVICE CONTROL CIRCUIT AND IDENTIFIABLE LIGHT EMITTING DEVICE CIRCUIT THEREFOR AND IDENTIFICATION METHOD THEREOF - The present invention discloses a light emitting device power supply circuit, a light emitting device control circuit and an identifiable light emitting device circuit therefor, and an identification method thereof. The light emitting device control circuit includes an operation signal generation circuit and an identification circuit. The operation signal generation circuit determines whether the light emitting device control circuit operates in an identified mode or amiss mode according to an enable signal. In the identified mode, the light emitting device control circuit operates a power stage circuit to supply an output current to an identifiable light emitting device circuit. In the miss mode, an output voltage is maintained at a predetermined level. The identification circuit determines whether the light emitting device control circuit switches from the miss mode to the identified mode according to whether the output voltage meets a condition.

07-24-2014

20140320099

SWITCHING REGULATOR COMPATIBLE WITH ELECTRONIC TRANSFORMER AND CONTROL METHOD THEREOF - The present invention discloses a switching regulator compatible with an electronic transformer and a control method thereof. The switching regulator includes: a power stage circuit, a control circuit, and an input current peak & valley setting circuit. The control circuit is coupled to the power stage circuit, for generating an operation signal according to a feedback signal and a peak & valley setting signal, to operate at least one power switch in the power stage circuit, so as to convert a rectified input voltage to an output voltage. The input current peak & valley setting circuit is coupled to the control circuit, for generating the peak & valley setting signal such that in one cycle period, the input current has multiple valleys forming a semi-sinusoidal contour.

10-30-2014

Peng-Sen Chen, Zhubei City TW

Patent application number

Description

Published

20120075757

CIRCUIT WITH ESD PROTECTION FOR A SWITCHING REGULATOR - The present invention discloses a circuit with ESD protection and high voltage conversion for a switching regulator. It mainly comprises a non-overlap circuit, a power P-type MOS device, a parasitic diode, a digital logic AND gate, a pair of resistance and capacitance, a power N-type MOS device, an ESD N-type MOS device, a Lx pin and an ESD protection cell. The present invention can effectively decrease the on-resistance of MOS device and then improve the circuit efficiency.

03-29-2012

20140016489

WIRELESS COMMUNICATION CIRCUIT WITH A WIDEBAND RECEIVED SIGNAL STRENGTH INDICATOR - It is an objective of the present invention to provide a circuit with a wideband received signal strength indicator, used for multiple systems. By using the switches and the analog-to-digital converter and the demodulator, the circuit of the present invention has the advantages of auto gain control, circuit size reduction and power-saving.

01-16-2014

20140018011

DIRECT-CONVERSION TRANSCEIVER WITH DC OFFSET COMPENSATION AND THE OPERATION METHOD USING THE SAME - The present invention discloses a direct-conversion transceiver with dc offset compensation, and method using the same. The transceiver mainly comprises an antenna, a first filter, a second filter, a third filter, a first variable gain amplifier with multi-stages, a second variable gain amplifier with multi-stages, a first analog-to-digital converter, a second analog-to-digital converter, a first dc offset loop, a second dc offset loop, a first digital-to-analog converter, a second digital-to-analog converter, a third digital-to-analog converter, a fourth digital-to-analog converter, a third mixer, a fourth mixer, a power amplifier, a local oscillator, and a baseband circuit. By using the second filters, the third filter, the first digital-to-analog converter and the second digital-to-analog converter for both in transmitting mode or receiving mode, the numbers of the filter and digital-to-analog converter can be reduced and thus the circuit area of the transceiver can be further miniaturized.

01-16-2014

Pi-Tsung Chen, Zhubei City TW

Patent application number

Description

Published

20110197168

DECOMPOSING INTEGRATED CIRCUIT LAYOUT - Various embodiments of the invention provide techniques to ensure a layout for an integrated circuit is split-able. In a method embodiment, a layout is generated in a customer site having a layout library as inputs wherein the library provides exemplary layouts that have been verified to be spit-able and that can be used and layouts that can cause conflicts to avoid. A real-time odd cycle checker is also provided in which the checker identifies in real time conflict areas and odd cycles as they arise during layout generation. To reduce memory usage layouts of various devices may be separated so that each individual layout or a small number of layouts, rather than a large layout for the whole application circuit, can be checked against conflicts. Once the layout is ready at the customer site, it is sent to the foundry site to be decomposed into two masks and taped-out. Other embodiments are also disclosed.

08-11-2011

20130292841

SEMICONDUCTOR INTERCONNECT STRUCTURE - The present disclosure provides an interconnect structure for a semiconductor device. The interconnect structure includes a first metal layer that contains a first metal line. The interconnect structure includes a dielectric layer located over the first metal layer. The dielectric layer contains a first sub-via electrically coupled to the first metal line and a second sub-via electrically coupled to the first sub-via. The second sub-via is different from the first sub-via. The interconnect structure includes a second metal layer located over the dielectric layer. The second metal layer contains a second metal line electrically coupled to the second sub-via. No other metal layer is located between the first metal layer and the second metal layer.

Po-Hung Chen, Zhubei City TW

Patent application number

Description

Published

20120073284

HOT ZONE HEAT TRANSFER STRUCTURE OF A STIRLING ENGINE - A hot zone heat transfer structure of a Stirling engine is provided. One end of a cylinder includes a heated head, with its end wall connected with a hot air pipe. The cylinder accommodates a piston. The piston has an end surface corresponding to the end wall, between which a hot zone is defined. The end wall is fitted with a protruding heat conductor towards the piston, and the end surface is fitted with a concave heat-conducting portion, enabling normal overlapping of the ends of both the heat conductor and the heat-conducting portion. The overlapping may vary with the changing locations of the piston. A flanged section is set externally onto said heat conductor towards the exterior of the end wall. The heat from the head can be transferred to the central area of the hot zone via the help of the heat conductor and heat-conducting portion.

03-29-2012

Roy Chen, Zhubei City TW

Patent application number

Description

Published

20100212100

Cleaning Apparatus for Sophisticated Electric Device - A cleaning apparatus is provided to clean a sophisticated electric device. The apparatus has cleaning units and each of the cleaning units has a cambered top. Thus, coordinated with an actuating device, a sophisticated electric device can be cleaned by using the cleaning apparatus with cleaning units having cambered tops.

08-26-2010

Shih-Chin Chen, Zhubei City TW

Patent application number

Description

Published

20130341747

CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a chip including: a semiconductor substrate having a first surface; a device region formed in the semiconductor substrate; and a plurality of micro-lenses on the first surface and the device region; a cover substrate disposed on the chip, wherein the cover substrate is a transparent substrate; a spacer layer disposed between the chip and the cover substrate, wherein the spacer layer, the chip, and the cover substrate collectively surround a cavity in the device region; and at least one main lens on the cover substrate and in the cavity, wherein a width of the main lens is greater than that of each of the micro-lenses.

12-26-2013

20140015111

CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and an opposite second surface; a device region disposed in the substrate; a dielectric layer located on the first surface of the semiconductor substrate; a plurality of conducting pads located in the dielectric layer and electrically connected to the device region; at least one alignment mark disposed in the semiconductor substrate and extending from the second surface towards the first surface.

Shu-Chin Chen, Zhubei City TW

Patent application number

Description

Published

20100295658

INTELLIGENT LOCK - The present invention provides an intelligent lock including an image recognition system, a voiceprint recognition system and a fingerprint recognition system. These recognition systems can recognize a built-in recognition data of the lock. If the built-in recognition data of the lock is matched, then the lock can be opened immediately, or else an alarm will be triggered.

11-25-2010

Tsan Lin Chen, Zhubei City TW

Patent application number

Description

Published

20130124931

TRANSMISSION ERROR DETECTOR FOR FLASH MEMORY CONTROLLER - In one aspect, the present disclosure provides a storage device for accounting for transmission errors to improve a usable life span of memory blocks. In some embodiments, the storage device includes: a memory array including a plurality of memory blocks; and a memory controller in communication with the memory array via an interface, wherein the memory controller is configured to detect an error event associated with data from one of the plurality of memory blocks; determine an origin of the error event; increment an error count if the origin of the error event indicates a data error in the one of the plurality of memory blocks and not if the origin of the error event indicates a transmission error; compare the error count to a threshold value; and mark the one of the plurality of memory blocks as bad when the error count exceeds the threshold value.

05-16-2013

20130191581

MULTI-LAYER INPUT/OUTPUT PAD RING FOR SOLID STATE DEVICE CONTROLLER - Some embodiments of the disclosed subject matter include an integrated circuit. The integrated circuit includes a solid state device controller configured to control a plurality of flash memory devices, a first set of input output IO pads, coupled to the solid state device controller, arranged as a first pad ring around a perimeter of the integrated circuit, and a second set of IO pads arranged adjacent to at least one side of the first pad ring, wherein one of the second set of IO pads includes a power source node configured to receive a power supply voltage for the solid state device controller, a ground node, and a bond pad configured to receive an external signal.

07-25-2013

20130194873

SYSTEMS AND METHODS FOR AUTO-CALIBRATION OF A STORAGE MEMORY CONTROLLER - Systems and methods for auto-calibrating a storage memory controller are disclosed. In some embodiments, the systems and methods may be realized as a method for auto-calibrating a storage memory controller including instructing a controllable delay circuit to delay a read strobe signal at one of a plurality of delay settings, receiving data captured at a data latch using the delayed read strobe signal, selecting an adjustment factor from the plurality of delay settings using a multi-scale approach, based on an accuracy of the data captured at the data latch, and instructing the controllable delay circuit to delay the read strobe signal by the adjustment factor.

08-01-2013

Tsung-Ming Chen, Zhubei City TW

Patent application number

Description

Published

20130114172

ESD PROTECTION CIRCUIT - An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes an impedance device coupled between a pad and a power line and a clamp unit coupled between the pad and a ground line.

05-09-2013

Wei-Li Chen, Zhubei City TW

Patent application number

Description

Published

20120131523

METHOD OF GENERATING AN INTELLECTUAL PROPERTY BLOCK DESIGN KIT, METHOD OF GENERATING AN INTEGRATED CIRCUIT DESIGN, AND SIMULATION SYSTEM FOR THE INTEGRATED CIRCUIT DESIGN - The present application discloses a method of generating an intellectual property (IP) block design kit including an IP block circuit design and a system-level characteristics table for manufacturing an integrated circuit. According at least one embodiment, the IP block circuit design is generated. The IP block circuit design is simulated based on predetermined configuration sets, and each configuration set has manufacturing options and/or operating conditions. A plurality of system-level models for the predetermined configuration sets are generated based on the simulation of the IP block circuit design. The system-level characteristics table is generated by arranging the predetermined configuration sets and the system-level models in compliance with a system-level characteristics table template of a system-level characteristics modeling device. Then the IP block circuit design and the system-level characteristics table are stored as the IP block design kit.

05-24-2012

Wei-Ling Chen, Zhubei City TW

Patent application number

Description

Published

20140055106

Control Circuit, Time Calculating Unit, and Operating Method for Control Circuit - A control circuit, a time calculating unit, and operating method for control circuit are disclosed. The control circuit is operated in a power converter and coupled to a load. The control circuit includes an output stage and a time calculating unit. The time calculating unit receives a control signal and a reference voltage and provides a switch conducting signal to the output stage. The generation of the control signal is related to an output voltage of the power converter. When the difference between the control signal and the reference voltage becomes larger due to the change of the load, the time calculating unit dynamically increases an on-time of the switch conducting signal.

02-27-2014

20140167716

DC-DC Converter, Timing Signal Generating Circuit, and Operating Method Thereof - A DC-DC converter including an output stage, a feedback loop, a pulse-width modulation (PWM) generating circuit, and a driving circuit is disclosed. The output stage is coupled to an input voltage and an output inductor to provide an output voltage. The feedback loop is coupled to the output inductor and receives the output voltage to generate a control signal. The PWM generating circuit is coupled to the feedback loop and receives the control signal. The PWM generating circuit also includes a timing signal generating unit which makes the PWM generating circuit to generate a PWM signal according to a correction voltage. The correction voltage is reacted in the output voltage and a first current source related to the input voltage.

06-19-2014

Wei-Zen Chen, Zhubei City TW

Patent application number

Description

Published

20100060370

VOLTAGE-CONTROLLED OSCILLATOR - A voltage-controlled oscillator comprises a variable inductor, a negative impedance circuit, an operating voltage source and a ground point. The variable inductor comprises a transformer and a transistor switch, the transformer comprising a primary side coil and a secondary side coil, the primary side coil comprising a first coil and a second coil, and the secondary side coil comprising a third coil and a fourth coil. The transistor switch is connected in parallel with the primary side coil to adjust an inductance value of the variable inductor based on a gate voltage. The negative impedance circuit is connected in parallel with the secondary side coil to compensate the power consumption of the voltage-controlled oscillator during oscillation. The operating voltage source is electrically connected between the third coil and the fourth coil, and the ground point is electrically connected between the first coil and the second coil.

03-11-2010

20130033319

AMPLIFIER CIRCUITS AND MODULATION SIGNAL GENERATING CIRCUITS THEREIN - An amplifier circuit includes a modulation signal generating circuit, a driving stage circuit and an output stage circuit. The modulation signal generating circuit generates a pair of modulation signals according to a pair of differential input signals and a pair of clock signals. The pair of clock signals includes a first clock signal and a second clock signal having a phase difference therebetween. The driving stage circuit generates a pair of driving signals according to the pair of modulation signals. The output stage circuit generates a pair of amplified output signals according to the pair of driving signals.

02-07-2013

Yang Cheng Chen, Zhubei City TW

Patent application number

Description

Published

20110224559

HIGH-ACCURACY HEMADYNAMOMETER AND METHOD OF USING THE SAME - The invention provides a high-accuracy hemadynamometer and method of using the same. A main air tank imposes pressure upon a wrist or an arm of a user. There is a valve between an auxiliary air tank and the main air tank to release air in the auxiliary air tank to the main air tank. A pressurized device increases pressure of the main air tank and the auxiliary air tank to impose pressure upon the wrist or the arm of the user. A pressure release device is set on the main air tank. A pressure detector detects pressure of the main air tank and outputs a pressure value. A heartbeat detector detects the oppression of the blood of the artery of the user and outputs a pulsation signal. A controller controls the pressure release device to release air in the main air tank and activates the valve based on the pulsation signal for releasing air in the auxiliary air tank to the main air tank.

09-15-2011

Yao-Jen Chen, Zhubei City TW

Patent application number

Description

Published

20130241760

OBJECT DETECTION DEVICE AND METHOD THEREOF - An object detection device includes a RF emitter composed of a RF emitting module and an emitter antenna for emitting an EM wave, a RF receiver composed of a RF receiving module and a RF antenna for receiving a reflected EM wave by a predetermined object and a processor connected to the RF emitter and the RF receiver to process the received reflected EM wave so as to obtain a received signal strength indicator (RSSI) such that existence of the object is determined based on fluctuation of the RSSI when compared with a predetermined threshold value.

09-19-2013

Yi-Hsi Chen, Zhubei City TW

Patent application number

Description

Published

20140103419

NON-VOLATILE MEMORY DEVICE AND METHOD FOR FORMING THE SAME - A method for forming a non-volatile memory device includes: (a) forming an isolation structure on a circuit-forming surface of a semiconductor substrate to define an array of cell forming regions; (b) forming a gate structure array including a plurality of gate structures disposed above the cell forming regions and each having a first side and a second side; (c) performing ion implantation to form drain regions and a common source region; and (d) forming drain contacts to the drain regions, and a common source contact to the common source region.

04-17-2014

Yi-Ling Chen, Zhubei City TW

Patent application number

Description

Published

20100101651

POLYMER SOLAR CELLS - A polymer solar cell is provided. The polymer solar cell includes a cathode and an anode, an active layer having a first surface and a second surface disposed between the cathode and the anode, and a titanium dioxide layer formed on one of the first and second surfaces of the active layer.

04-29-2010

Yi-Ming Chen, Zhubei City TW

Patent application number

Description

Published

20130258474

OPTOELECTRONIC DEVICE WITH IMPROVED LENS CAP - An optoelectronic device includes a base part and a lens cap. The base part has an optoelectronic chip mounted thereon. The lens cap is mounted over the optoelectronic chip and includes a metallic hollow cylindrical part and a plastic inner cylindrical part. The hollow cylindrical part has an opening on a top thereof. The inner cylindrical part is firmly coupled within the hollow cylindrical part, and the inner cylindrical part has a lens part located within the opening and at least three aligning members in contact with an upper circumference of the base part so as to align the lens part with the optoelectronic chip.

10-03-2013

Yi-Ming Chen, Zhubei City US

Patent application number

Description

Published

20140061708

LIGHT-EMITTING DEVICE - A light-emitting device includes a first electrode; a light-emitting stacked layer on the first electrode; a first contact layer on the light-emitting stacked layer, wherein the first contact layer includes a first contact link and a plurality of first contact lines connected to the first contact link; a first conductive post in the light-emitting stacked layer and electrically connecting the first electrode and the first contact layer; and a passivation layer between the first conductive post and the light-emitting stacked layer.

03-06-2014

Yu-Hsun Chen, Zhubei City TW

Patent application number

Description

Published

20130326091

USB HOST CONTROLLER AND SCHEDULING METHODS THEREOF - A USB host controller is provided. The USB host controller includes an endpoint management unit, a transfer management unit, and a schedule management unit. The endpoint management unit manages endpoint configurations of a USB device, wherein the USB device includes a plurality of endpoints and the endpoint configurations include a plurality of statuses of the endpoints of the USB device. The transfer management unit transfers data regarding transfer information of the endpoints of the USB device between a system memory and the USB host controller. The schedule management unit simultaneously manages packet transfer of at least two endpoints of the USB device.