When we applied the clock and data as described in the timing diagram in page#12, the image displayed by the LCD was distorted in some regions(see DISTORTED.JPEG ).The data change is in the rising edge of the clock as required.See tek00087.png of the pixel clock and a signal below(Dark blue:Clock, Light Blue:Data)

After several debugging steps, when the clock was inverted using a NOT Gate externally and applied to LCD, the image was displayed fine ( see OK.JPEG ).The pixel clock and a data line in this case is shown in tek00088.png. You can see the data transition occurring in falling edge of clock.

Also, the minimum setup time and hold time is specified as 8ns in Page#10.Based on the given data, we could infer that the data is sampled on the falling clock edge.

This required setup time and hold time are properly followed in the first case where we got distorted image.

In the PCLK inverted case, this setup time and hold time seem to be improper, but we got clear image.

Please advise us wrt setup and hold time times described in your datasheet and what we observed in LCD.