Wednesday, 24 July 2013

Timing Analysis:
Timing Analysis is a method of validating the timing performance of a design. i.e. How fast the design is going to operate.Timing Analysis can be done in 2 ways
1. Static Timing Analysis (STA)
2. Dynamic Timing Analysis (DTA)STA:Static timing analysis is a method of validating the timing performance of a design by checking all possible paths for timing violations. PrimeTime(PT) checks for these violations.

To check a design for violations, STA tool breaks the design down into a set of timing paths, calculates the signal propagation delay along each path, and checks for violations of timing constraints inside the design and at the input/output interface.

DTA:

Another way to perform timing analysis is to use Dynamic Timing Analysis (DTA). It checks the functionality of design as well as timing. Dynamic simulation determines the full behavior of the circuit for a given set of input stimulus vectors. Compared with dynamic simulation, static timing analysis is much faster because it is not necessary to simulate the logical operation of the circuit.

Why STA is preferred over the DTA?

DTA requires a set of input stimulus vectors to check the timing characteristics of all paths in the design. So DTA makes the timing analysis very slow (Time taken for analyzing the design is very high because of the generation of test vectors for functionality check) when compared with STA. STA is faster than DTA beacuse there is no need to generate any kind of test vectors during STA. Static Timing Analysis is much faster because it is not necessary to simulate the logical operation of the circuit. That's why, STA is most popular way of doing timing analysis.

Timing Violations:STA tool determines the timing paths and calculates the path delays, it can check for violations of timing constraints, such as setup and hold constraints.Setup Constraint:

A setup constraint specifies how much time is necessary for data to be available at the input of a sequential device before the clock edge that captures the data in the device. This constraint enforces a maximum delay on the data path relative to the clock path.

Hold Constraint:

A hold constraint specifies how much time is necessary for data to be stable at the input of a sequential device after the clock edge that captures the data in the device. This constraint enforces a minimum delay on the data path relative to the clock path.

The amount of time by which a violation is avoided is called the slack. For example, for a setup constraint, if a signal must reach a cell input at no later than 10 ns and is determined to arrive at 6 ns, the slack is 4 ns. A slack of 0 means that the constraint is just barely satisfied.

A negative slack indicates a timing violation.

Slack = Required Arrival Time - Actual Arrival Time

If Slack = 0, The design is critically working at the desired frequency

If Slack >0, The design is meeting the timing requirements and still it can be improved

If Slack<0, The design is not meeting the timing constraints, It has timing violations to be fixed.

Timing Violations:

1. Setup Time violation

2. Hold Time violation

Setup Time Violation:

Setup time is the amount of time before the clock edge that the input signal needs to stable to guarantee it is properly accepted on the clock edge. If the data input is not constant the output of sequential element (FF) goes unpredictable state. The data can't propagated properly. So there is violation in the design. This violation is called as setup time violation.

Hold Time Violation:

Hold time is the amount of time after the clock edge that the input should be stable to guarantee it is properly accepted on the clock edge. If the data input is not constant the output of sequential element (FF) goes unpredictable state. The data (D) can't propagated properly. So there is violation in the design. This violation is called as Hold time violation.