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Abstract

The circuit is used to delay the closing edge of the write clock for a static memory using a saturating Harper-PNP cell. The delay circuit contains a saturating HPNP cell identical to the cells within the memory. The time required to write a saturating cell is highly variable depending greatly on hard-to-control process parameters, thus requiring a tracking delay to guarantee stable writing of the memory elements.

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United States

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English (United States)

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Time Delay Circuit for Harper PNP Array Clock Chopper

The circuit is used to delay the closing edge of the write clock for a static
memory using a saturating Harper-PNP cell. The delay circuit contains a
saturating HPNP cell identical to the cells within the memory. The time required
to write a saturating cell is highly variable depending greatly on hard-to-control
process parameters, thus requiring a tracking delay to guarantee stable writing of
the memory elements.

Time delays are typically obtained by stringing a series of basic logic circuits
with added parasitic elements where the total delay is proportional to the RC time
constants provided by parasitic elements (Fig. 1). The number of stages would
be minimized by increasing capacitances on the switching nodes and reducing
the switching currents. Such timing chains will not yield a delay that would track
the writing of a saturating memory cell.

(Image Omitted)

Saturated transistors have also been used to increase the individual block
delays and minimize the number of stages required in timing chains. Here, the
discharging of saturated NPN transistors would track with the initial third of the
write time of a HPNP memory cell, leaving the trailing two thirds of the write time
which is dominated by the lateral PNP time constants unaccounted.

The delay circuit disclosed here (Fig. 2) uses a cell in the delay block which
provides good tracking of the supplied write clock to the writing of the memory
elements over variations in processing and environmental conditions. The delay
circuit features a split current source (T4 and T6) which allows for adjustment of
the "WRITE" and "READ" time constants. The cell is initially driven by the
"READ" current source (through T7) when the CLKIN input is high. Current from
the "WRITE" current source is diverted to the VCC power supply rail through T8.
The "READ" current is applied to the load CELL through its left side bit line
connection "BL". This holds the left internal collector node "CL" at a low level
one Vbe below VCC. No current flows through the right bit line connection "BR",
...