Nvidia: Power Efficiency of Kepler - Result of Close Collaboration with TSMC

It is not a secret that performance, cost and power efficiency of chips depend on actual design as well as on process technology. A good chip design and advanced process technology almost always result in a proper product. But to make the best chip, its design has to be tailored for process technology and vice versa. Apparently, this is exactly what Nvidia and TSMC have done to make Kepler architecture exceptionally power-efficient.

"Today, the primary constraint on processor performance is the power consumption budget. So our goal is always to develop solutions that deliver the highest performance within a fixed power budget. Having a more efficient process enabled us to add more processing cores, thus increasing performance. Put simply, greater efficiency equals greater performance and optimal performance per watt," said Joe Greco, senior vice president of the advanced technology group at Nvidia.

Kepler was in many ways an ambitious project because it introduced a new architecture at the same time as a new silicon process technology node. To maximize the efficiency of Kepler architecture, which Nvidia needed not only to sustain leading positions on the market of computer graphics, but also to continue its progress on the market of high-performance computing, Nvidia had tochange our silicon process development model with TSMC.

Back in the days Nvidia and Taiwan Semiconductor Manufacturing Company worked independently: TSMC prepared the process technology, Nvidia worked on the design. For Kepler, Nvidia began working with TSMC three years before our product tape-out (when the processor design is complete and ready for manufacturing). Working in tandem, the two companies created a production qualification vehicle (PQV) to allow the TSMC process engineers and Nvidia design engineers to optimize the process before the product tape-out. Through repeated prototyping, the companies were able to optimize both the process and design, creating a more efficient Kepler design rather than simply a chip in a standard 28nm process.

This is not the first time when TSMC collaborates with its major customers to tailor process technology for their needs and also not the first time when chip designs are optimized for a process technology still in development. As chips get more complex and manufacturing technologies get thinner, even closer collaboration between chip designers and contract makers of semiconductors will be needed to create great products.

TSMC’s 28nm high performance (HP) process, the foundry’s most advanced 28nm process which uses high-K metal gate (HKMG) technology and SiGe (Silicon Germanium) straining. HKMG is a process that uses a gate insulator film with a high dielectric constant which reduces power by reducing gate leakage compared to the previous generation SiON gate. SiGe straining is a chemical process to stretch the silicon atoms to improve the mobility or the effective frequency of the transistor. Both technical advances improve the performance per watt of the transistor translating to a more power efficient system.

TSMC’s 28nm HP process, seen under an electron microscope, is 30% smaller than 40nm and about 35% more energy efficient.

"We are extremely proud of what we accomplished with Kepler. It combines Nvidia’s world-class GPU engineering with TSMC’s very best 28nm process. But while Kepler was a key milestone, it is one point in a continuum. We continue to improve on what we developed and continue our collaboration with TSMC. In fact, we recently received our first version of an enhanced PQV for 20nm from TSMC. That process will yield even greater efficiency for Nvidia’s next next-generation GPUs," said Mr. Greco.