ESP_Sprite wrote:Huh, you're right - seems I skipped over pin 7. Thanks for noticing, will fix it as soon as I have time. Same with the code/documentation discrepancy - those should match up, will see which one is wrong.

I can't easily check the code now, but my guess is that WP and HOLD aren't mentioned anywhere in the PSRAM code because they're already set up correctly for the SPI flash. On a flash chip, in the right mode (quad I/O) they *are* actually used as data pins; it's just that quad I/O is a relatively new development, and seemingly the chip manufacturers still only use the old pin names. (See e.g. here, last sentence of 7.3 on page 8.)

hi jeroen, only for the protocol please add GND pin too

and btw,ESP32 rev0 pSRAM - done!

@John Leesry - but i could not wait - now i have it manage by self.we have events on june 6. and we want show on the education board the pSRAMwe are ready on one weekend - how long pycom have played? 1/2 year? ......done on one weekend!now its time to go few hours sleeping.best wishesrudi

ESP_Sprite wrote:TL;DR: We just released a *beta version* of esp-idf with support for external PSRAM. If you hook up the correct chip, it should give you 4MiB more RAM than a plain ESP32 has....

thank you Jeroen!

now after 42 h - pSRAM runs here on wrover with ESP32 rev0

cause have learn many things in datasheet and other by searching mistakes, studdy code and other.....but I will never be able to give water you and ivan,you are the best. worldwide!

hope espressif knows about your 1000 procent knowledge, this can nobody take from your head.

think we can go on here now too - hey - keep smile! i like you@ivan and you too!

sory for the pressure making - but we all work better under pressure i am too.

best wishesrudi

before i forget:

ESP_Sprite wrote:You can download the beta esp-idf and the toolchain from the usual spots .........Note that there are no binaries available for the toolchain, you will need to build it from source. ....(Sorry, no Windows support for this yet.)....

sry - only for the protocol,i develop here under windows in eclipse neon3 and sure - linux too.

ok ivan, will check it. ( we have on monday holiday here ) can you perhabs say, where the 16 byte are reserved,i search just in time -

just one word:i am happy now with this what here works and how it works - now i try to combine it step by step with the application code will see/test where and how the limits then are in rev0 / rev1

WiFive wrote:

rudi wrote:we have now 4096 KiB in ESP32 rev0 available

So how to trigger the bug on rev0?

what was done:toolchain like jeroen describedone step more after check out future/psram_malloc, update libs

the boot check on 4096 was ok.the demo/compare code was okthe 1 MB MallocCaps worksthe 2 MB MallocCaps worksthe 3 MB MallocCaps workson 4 MB MallocCaps i work just in time - i look how much is reserved for something, in menuconfig there are some parameter

i was gone simple steps,

final_check_reserved_16Byte.png (20.42 KiB) Viewed 1776 times

final i found out, there are 16 Byte reserved - or i do a mistake with my code:

there is named, that GPIO16, GPIO17 is used for the eMbeddedFlashthere comes now confused question/thinking:

With regards to using D2WD with PSRAM: it is possible, as the extra CS and CLK signals to PSRAM are routed via the GPIO matrix. But depending on the pins chosen, it may not be possible to achieve 80MHz clock due to timing differences between various pads. 40MHz clock should still be possible.

- this two pins comes from the GPIO Pad and can not so fast (40) / ( 80 ) - the SD_DATA2 and SD_DATA3 are in VDD_SDIO ( VSDIO ) Domain and can fast but not used?

are the pins "named" swapped perhabs?if not, in which mode is the eMbeddedFlash then run, there is only 2 DATA Pins, it looks then like not quad mode?

how we connect the external SRAM to the ESP32-D2WD in this steps of pin notes? we have then no CLK and CS for external SRAM from the VDD_SDIO ( 1.8 )

can it be, cause the note talk from GPIO16 and GPIO17, ( GPIO PAD PINS ) , that we drive the eMbeddedFlash and the external SRAM with the same (slower ) CLK ( btw which pin is used? - there is given SD_CLK from VDD_SDIO domain ) and use we GPIO20 ( was in the VDD_SDIO domain ) then as CS for the external SRAM ?

short:in which mode we connect which pins to external SRAM on ESP32-D2WD ?

EMAC_CLK_OUT ( GPIO16 ) then is not more existent in ESP32-D2WD, cause is used for the eMbeddedFlash, right?( is this then on other pin or completly not more possible? )

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