The 'HC594 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks and direct overriding clear (RCLR, SRCLR) inputs are provided on both the shift and storage registers. A serial (QH) output is provided for cascading purposes. Both the shift register (SRCLK) and storage register (RCLK) clocks are positive edge triggered. If both clocks are connected together, the shift register always is one count pulse ahead of the storage register. The parallel (QA-QH) outputs have high-current capability. is a standard output. ORDERING INFORMATION

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FUNCTION TABLE INPUTS SER SRCLK SRCLR RCLK RCLR Shift register is cleared. First stage of shift register goes low. Other stages store the data of previous stage, respectively. First stage of shift register goes high. Other stages store the data of previous stage, respectively. Shift register state is not changed. Storage register is cleared. Shift register data is stored in the storage register. Storage register state is not changed. FUNCTION