Meeting the challenge of advanced nodes

Advanced FinFET devices and planar devices with FD-SOI technology improve power, performance, and area (PPA), but create additional design challenges. Cadence developed its revolutionary full-flow digital toolset to address these design challenges at the design creation, implementation, and signoff stages. Here are just some of the issues designers can run into with these transistors:

Leakage power is reduced, but now dynamic power becomes more significant

Double patterning is used to enhance feature density as single-pass lithography falls short

Placement and optimization must consider new advanced-node base-layer constraints

Electromigration and IR become a bigger concern with increased drive strength and high-resistance wires

On-chip variation plays a bigger role and must be mitigated through correct statistical algorithms

Transistor self-heating effects can affect signal RMS current

The Cadence® Full-Flow Digital Implementation and Signoff tools can handle and support all the special requirements of today’s FinFET and advanced-node FD-SOI designs. These tools prevent and correct harmful lithography hotspots, random defects, on-chip variation, and variation due to chemical-mechanical polishing. Using rule- and model-based in-design analysis (pre-qualified and closely related with foundry process simulation), the Cadence Innovus™ Implementation System minimizes risk upfront and prevents unexpected design re-spins and late-stage iterations.

Designing for double patterning and beyond

As design is moving below 20nm, fabs are employing double patterning to enhance the feature density, as single lithographic exposure generally is not enough to provide sufficient resolution. At 16nm and 14nm, shapes are so close that single-pass lithography has many interference effects, and multi-pass lithography is required. With two-pass lithography, each pass prints one mask of double-pitch wires. When both passes are complete, a single layout with minimum spacing wires is created.

At 7nm, explicit full-flow coloring is required during design. RC characteristics are color dependent, even on the same metal layer. Older software for IC design can’t handle the double patterning or explicit coloring required. But Cadence’s implementation and signoff tools were designed, from the start, to help designers deal with these and other effects of very small geometries.

Digital toolset optimized for advanced nodes

Cadence completely re-invented its digital tool set for advanced nodes, starting with a unified software architecture. This integrated digital architecture is based on a foundation of core common engines and full-flow optimizations. When new features are added in one place, multiple applications benefit. This enables smarter software, with fewer bugs, rapid feature deployment for newer nodes, accurate early prediction, and convergent correlation.

Unified Software Architecture

The Cadence full-flow digital solution offers massive parallelization that works to your advantage. Other point-tool-oriented flows create inefficiencies due to parallelism, with multiple bottlenecks between synthesis and implementation and between optimization and signoff. By using full-flow parallelism, Cadence avoids those bottlenecks and provides a much faster turnaround time.

The Cadence Innovus Implementation System provides full support for coloring, double patterning and a unique via pillar methodology for high-performance computing requirements. The GigaPlace™ Engine, which uses a look-ahead placement approach, includes features that are useful for advanced-node designs, including activity-driven placement, slack- and power-driven placement, pin-access-aware placement, and IR-driven placement. The NanoRoute™ Advanced Digital Router is optimized for highly complex designs that include multiple CPUs and other complex logic. The GigaOpt™ Optimizer considers advanced-node characteristics such as correct layer selection for optimal buffering. Layer-aware route-driven optimization technology provides huge improvements in timing closure.

Signoff speed and efficiency

Over the past few years, Cadence has introduced totally revamped tools to facilitate advanced-node signoff. These tools are all integrated, and include our Quantus™ Extraction Solution; the Liberate™ Characterization portfolio providing robust solutions for the characterization, variation modeling, and validation of foundation IP, from standard cells, I/Os, and complex multi-bit cells to memories and mixed-signal blocks; the Tempus™ Timing Signoff Solution for signoff static timing analysis; the Voltus™ IC Power Integrity Solution; and the Pegasus™ Verification System for massively parallel physical signoff and DRC, LVS, and DFM.

These sophisticated signoff tools are fully integrated with the Cadence synthesis and implementation tool sets to provide designers with one integrated tool flow for the entire design process.