PDP-1 Manual 1960 - Microsoft Research

6
6
PROGRAMMED
DATA
PROCESSOR-l
PROGRAMMED
DATA
digital
PROCESSOR-l
equipment
MAYNARD,
corporation
MASSACHUSETTS
Copyright
1960 by Digital
Equipment
Corporation
TABLE
OF CONTENTS
I. INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Central
Processor
Memory
System
5
Input-Output
II. PROGRAMMING PDP-1
Number
Format
Addressing
Operating
Manual
Speeds
Controls
Instruction
III.
9
System
Instruction
Indirect
. .. . .. .. . .. . .. . . .. .. . . .. .
List
INPUT-OUTPUT EQUIPMENT . . . . . . . . . . . . . . . . . . . . 21
Standard
Equipment
Optional
Equipment
IV. UTILITY PROGRAMS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
V. APPENDIX.....................................
Abbreviated
Numerical
Instruction
Instruction
Alphanumeric
Codes
List
List
27
I.
INTRODUCTION
The Programmed
Data Processor (PDP-1) is a high speed, solid
state digital computer designed to operate with several types of
input-output
devices, with no internal machine changes. It is a
single address, single instruction,
stored program computer with
powerful
program features. Five-megacycle
circuits, a magnetic
core memory, and fully parallel processing make possible a computation rate of 100,000 additions per second (about 2.5 times the
speed of most large computers in use today, and more than 100 times
the speed of magnetic drum computers). The PDP-1 is unusually
versatile. It is easy to install, operate and maintain.
Conventional
llO-volt power is used, neither air conditioning
nor floor reinforcement is necessary, and preventive maintenance
is provided for by
built-in marginal checking circuits.
PDP-1 circuits are based on the designs of DEC’s highly successful and reliable System Building
Blocks. Flip-flops
and most
switches use saturating
transistors.
Primary active elements are
Micro-Alloy
and Micro-Alloy-Diffused
transistors.
The entire computer occupies only 32 square feet of floor space.
It consists of a seven-foot console-desk and three equipment frames.
CENTRAL
PROCESSOR
The Central Processor contains the control, arithmetic and memory addressing elements and the memory buffer register. The word
length is 18 binary digits. Instructions
are carried out in multiples
of the memory cycle time of five microseconds.
Add, subtract,
deposit, and load, for example, are two-cycle instructions
requiring
10 microseconds. Multiplication,
by subroutine, requires 350 microseconds on the average. Program features include: single address
instructions,
multiple
step indirect addressing and logical arithmetic commands.
Console features include:
flip-flop
indicators
grouped for convenient octal reading, six program flags for automatic setting and computer sensing and six sense switches for manual setting and computer sensing.
MEMORY
SYSTEM
The coincident-current,
magnetic core memory holds 4096 words
of 18 bits each. Additional
memory units of the same capacity may
be readily added to the machine; a memory field switch instruction
built into PDP-1 will then select the correct memory module. The
5
6
read-rewrite
time of the memory is five microseconds,
the basic
computer
rate. Driving
currents are automatically
adjusted
to
compensate for temperature
variations between 55 and 100 degrees
fahrenheit.
The core memory storage may be supplemented
by up
to 64 magnetic tape transports and a tape control unit that serves
them all.
INPUT-OUTPUT
PDP-1 is designed to operate a variety of input-output
devices.
Standard equipment
consists of a paper tape reader with a read
speed of 300 lines (100 M-bit words) per second, a typewriter
for
on-line operation in both input and output and a paper-tape punch
(alphanumeric
or binary) with a nominal speed of 20 characters
per second. Optional external equipment includes: compatible magnetic tape (75 inches per second, alphanumeric
or binary); 16-inch
cathode ray tube for graphic or tabular displays; light pen input;
line printer (600 lines per minute); analog to digital and digital to
analog converters; and a real time clock. All in-out operations are
performed through the In-Out Register.
Of particular
interest is the ease with which new, and perhaps
unusual, external equipment can be added to PDP-1. Space is provided for additional gates to, and buffers from, the In-Out Register.
The in-out system is sufficiently simple so that little control circuitry is needed for additional
devices.
-The
PDP-1 is also available with the optional Sequence Break
System. This is a 16-channel
(or more, when needed) automatic
interrupt
feature which permits concurrent operation of several inout devices.
MEMORY
i
-r
7-r
CONTROL
1
MEYORY
b
BUFFER
4
9
ACCUMULATOR
r-
IN -OUT
1 CONTROL
PDP-1
SYSTEMBLOCK
8
DIAGRAM
I
II.
PROGRAMMING
PDP-1
The Central Processor of PDP-1 contains the Control Element,
the Memory
Buffer Register, the Arithmetic
Element,
and the
Memory Addressing Element. The Control Element governs the
complete operation of the computer including memory timing, instruction performance and the initiation of input-output
commands.
The Arithmetic
Element, which includes the Accumulator
and the
In-Out Register, performs the arithmetic operations. The Memory
Addressing Element, which includes the Program Counter and the
Memory
Address Register,
performs
address bookkeeping
and
modification.
The powerful program features of PDP-1 include multiple step
indirect addressing, Boolean operations, twelve variations of arithmetic and logical shifting, and ten conditional instructions.
Six independent flip-flops, called “program flags,” are available for use as
program switches or special in-out synchronizers. Two special instructions,
Multiply
Step and Divide Step, are included in the
Instruction
List. Multiply
and divide subroutines using these instructions operate in about 350 and 600 microseconds respectively.
NUMBER
The PDP-1 is a
Negative numbers
positive numbers.
numbers. Bits 1 to
significant and Bit
SYSTEM
“fixed point” machine using binary arithmetic.
are represented as the l’s complement
of the
Bit 0 is the sign bit which is ZERO for positive
17 are magnitude bits, with Bit 1 being the most
17 being the least significant.
The actual position of the binary point may be arbitrarily
assigned to best suit the problem in hand. Two common conventions
in the placement of the binary point are:
The binary point is to the right of the least significant
digit; thus, numbers represent integers.
The binary point is to the right of the sign digit; thus, the
numbers represent a fraction which lies between *I.
The conversion of decimal numbers into the binary system for use
by the machine may be performed
automatically
by subroutines.
Similarly the output conversion of binary numbers into decimals is
done by subroutine.
Operations
for floating point numbers are
handled by interpretive
programming.
The utility program system
provides for automatic insertion of the routines required to perform
floating point operations and number base conversion.
9
INSTRUCTION
FORMAT
MEMORY
PDP-1
ADDRESS,
Y
INSTRUCTION FORMAT
The Bits 0 through 4 define the instruction
code; thus there are
32 possible instruction codes, not all of which are used. The instructions may be divided into two classes:
Memory
reference instructions
Augmented
instructions
In the memory reference instructions,
Bit 5 is the indirect address
bit. The instruction
memory address, Y, is in Bits 6 through 17.
These digits are sufficient to address 4096 words of memory.
The augmented
instructions
use Bits 5 through 17, to specify
variations of the basic instruction.
For example, in the shift instruction, Bit 5 specifies direction of shift, Bit 6 specifies the character
of the shift (arithmetic or logical), Bits 7 and 8 enable the registers
(01 = AC, 10 = IO, and 11 = both) and Bits 9 through 17 specify
the number of steps.
INDIRECT
ADDRESSING
A memory reference instruction
which is to use an indirect address will have a ONE in Bit 5 of the instruction
word. The original
address, Y, of the instruction will not be used to locate the operand,
jump location, etc., of the instruction,
as is the normal case. Instead,
it is used to locate a memory register whose contents in Bits 6
through 17 will be used as the address of the original instruction.
Thus, Y is not the location of the operand but the location of the
location of the operand. If the memory register containing the indirect address also has a ONE in Bit 5, the indirect addressing procedure is repeated and a third address is located. There is no limit
to the number of times this process can be repeated.
OPERATING
Operating times of PDP-1
ory cycle of 5 microseconds.
SPEEDS
instructions
Two-cycle
10
are multiples of the meminstructions
refer twice to
memory and thus require 10 microseconds for completion. Examples
of this are add, subtract, deposit, load, etc. The jump instruction
and the augmented instructions
need only one call on memory and
are performed in 5 microseconds.
In-Out Transfer instructions
that do not include the optional
wait function require 5 microseconds. If the in-out device requires
a wait time for completion,
the operating time depends upon the
device being used.
Each step of indirect
seconds.
addressing
MANUAL
requires
an additional
5 micro-
CONTROLS
The Console of PDP-1 has controls and indicators for the use of
the operator. All computer flip-flops have indicator lights on the
Console. These indicators are primarily for use when the machine
has stopped or when the machine is being operated one step at a
time. While the machine is running, the brightness of an indicator
bears some relationship
to the relative duty factor of that particular flip-flop.
Three registers of toggle switches are available on the Console.
These are the Test Address (12 bits), the Test Word (18 bits), and
the Sense Switches (6 bits). The first two are used in conjunction
with the operating push buttons. The Sense Switches are present
for manual intervention.
The use of these switches is determined
by the program.
Operating Push Buttons
START
The computer will start. The first instruction
comes from the memory location indicated in
the Test Address Switches.
STOP
The computer will come to a halt at the completion of the current memory cycle.
CONTINUE
The computer will resume operation
at the state indicated by the lights.
EXAMINE
The contents of the memory register indicated
in the Test Address will be displayed in the
Accumulator
and the Memory Buffer lights.
DEPOSIT
The word selected by the Test Word Switches
will be put in the memory location indicated
by the Test Address Switches.
READ-IN
The photoelectric
paper tape reader will start
operating in the Read-In mode.
11
starting
12
Toggle Switches
SINGLE
SWITCH
TEST
CYCLE
When the Single Cycle Switch is on, the computer will halt at the completion
of each
memory cycle. This switch is particularly
useful in debugging programs. Repeated operation of the Continue Switch Button will step
the program one cycle at a time. The programmer is thus able to examine the state of
the machine at each step.
When the Test Switch is on, the computer
will perform the instruction
indicated in the
Test Address location, repeating this instruction at either the normal or single cycle rate,
if the Single Cycle Switch is up. This switch
is primarily useful in maintenance.
SWITCH
INSTRUCTION
LIST
This list includes the title of the instruction,
the normal execution
time of the instruction,
i.e., the time with no indirect address, the
mnemonic code of the instruction,
and the operation code number.
In the following list, the contents of a register are indicated by C ( ) .
Thus C(Y) means the contents of memory at Address Y; C(AC)
means the contents of the accumulator;
C(I0) means the contents
of the in-out register. An alphabetical
and numerical listing of the
instructions
is contained on Pages 27 to 29.
Memory Reference Instructions
ARITHMETIC INSTRUCTIONS
Add
add Y
(10 lsec)
Operation
Code 40
The new C(AC) are the sum of C(Y) and the original
C(AC).
The C(Y)
are unchanged.
The addition
is performed
with l’s complement
arithmetic. If the sum exceeds the capacity
of the Accumulator
Register, the
overflow
flip-flop
will be set (see Skip Group instructions).
Subtract
sub Y
(10 psec)
Operation
Code 42
The new C(AC)
are the original
C(AC) minus the C(Y). The C(Y) are
unchanged.
The subtraction
is performed
using l’s complement
arithmetic. If the difference exceeds the capacity of the Accumulator,
the overflow flip-flop
will be set (see Skip Group instructions).
13
Multiply
mus Y
Step
(10 psec)
Operation Code 54
If Bit 17 of the In-Out
Register is
If IO Bit 17 is a ZERO, the addition
C(AC) and C(I0)
are shifted right
this shift. This instruction
is used
Divide
dis Y
a ONE, the C(Y) are added to C(AC).
does not take place. In either case, the
one place. AC Bit 0 is made ZERO by
in the multiply
subroutine.
Step
(10 psec)
Operation Code 56
The Accumulator
and the In-Out
Register
are rotated
left one place.
IO Bit 17 receives the complement
of AC Bit 0. If IO Bit 17 is ONE, the
C(Y) are subtracted
from C(AC).
If IO Bit 17 is ZERO, C(Y) + 1 are
added to C(AC). This instruction
is used in the divide subroutine.
Index
idx Y
The C(Y)
cumulator.
(10 ksec)
Operation Code 44
are replaced
by C(Y)
The previous C (AC)
Index and Skip if Positive
isp Y Operation Code 46
+ 1. The C(Y) + 1 are left in the Acare lost. Overflow
is not indicated.
(10 psec)
The C(Y) are replaced
by C(Y) + 1. The
cumulator.
The previous
C(AC)
are lost.
+ 1 are positive,
the Program
Counter
is
and the next instruction
in the sequence
indicated.
C(Y) + 1 are left in the AcIf, after the addition,
C(Y)
advanced
one extra position
is skipped.
Overflow
is not
LOGICAL INSTRUCTIONS
Logical
and Y
AND
(10 ,usec)
Operation Code 02
The bits of C(Y) operate on the corresponding
bits of the Accumulator
to form the logical AND. The result is left in the Accumulator.
The C(Y)
are unaffected
by this instruction.
LOGICAL
AC
Bit
AND TABI.E
Y Bit
0
i
1
1
(:
1
Result
0
,"
1
Exclusive OR
(10 psec)
xor Y Operation Code 06
The bits of C(Y) operate on the corresponding
bits of the Accumulator
to form the exclusive OR. The result is left in the Accumulator.
The C(Y)
are unaffected
by this order.
EXCLUSIVE OR TABLE
AC
Bit
:
1
1
Y Bit
0
A
1
14
Result
0
1
:
Inclusive OR
(10 psec)
ior Y Operation Code 04
The bits of C(Y) operate on the corresponding
bits of the Accumulator
to form the inclusive
OR. The result is left in the Accumulator.
The C(Y)
are unaffected
by this order.
INCLUSIVE OR TABLE
ACOBit
Y Bit
0
Result
0
1
1
1
1
0
0
1
1
1
GENERAL INSTRUCTIONS
Load Accumulator
(10 ksec)
lac Y Operation Code 20
The C(Y) are placed in the Accumulator.
original
C(AC) are lost.
The C(Y)
are unchanged.
The
Deposit Accumulator
(10 psec)
due Y Operation Code 24
The C(AC)
replace the C(Y) in the memory.
changed by this instruction.
The original
C(Y)
Deposit
dap Y
The C(AC)
are lost.
are left
un-
Address Part
(10 psec)
Operation Code 26
Bits 6 through
17 of the Accumulator
replace the corresponding
digits
of memory register Y. C (AC) are unchanged
as are the contents of Bits 0
through
5 of Y. The original
contents of Bits 6 through
17 of Y are lost.
Deposit Instruction
Part
(10 psec)
dip Y Operation Code 30
Bits 0 through
5 of the Accumulator
replace the corresponding
digits of
memory register Y. The Accumulator
is unchanged
as are Bits 6 through
17 of Y. The original
contents of Bits 0 through
5 of Y are lost.
Load In-Out Register
(10 psec)
lie Y Operation Code 22
The C(Y) are placed in the In-Out
original
C(I0)
are lost.
Register.
C(Y)
are unchanged.
The
Deposit In-Out Register
(10 psec)
dio Y Operation Code 32
The C (IO) replace the C (Y) in memory. The C (IO) are unaffected
instruction.
The original
C(Y) are lost.
Jump
jmp Y
(5 ,usec)
Operation
by this
Code 60
The Program
Counter
is reset to Address Y. The next
will be executed
will be taken from Memory
Register
contents of the Program
Counter
are lost.
15
instruction
that
Y. The original
Jump and Save Program
jsp Y
Operation
Counter
(5 psec)
Code 62
The contents of the Program
Counter are transferred
to the Accumulator.
When the transfer takes place, the Program
Counter holds the address of
the instruction
following
the jsp. The Program
Counter
is then reset to
Address Y. The next instruction
that will be executed will be taken from
l%Iemory Register Y. The original
C(AC) are lost.
Skip if Accumulator
sad Y
Operation
and Y differ
(10 psec)
Code 50
The C(Y) are compared
with the C(AC). If the two numbers
are different, the Program
Counter is indexed one extra position
and the next instruction
in the sequence is skipped.
The C(AC) and the C(Y) are unaffected by this operation.
Skip if Accumulator
sas Y
Operation
and Y are the same
(10 psec)
Code 52
The C(Y) are compared
with the C(AC). If the two numbers are identical, the Program
Counter
is indexed one extra position
and the next instruction
in the sequence is skipped. The C (AC) and C(Y) are unaffected
by this operation.
Augmented Instructions
Load Accumulator
law N
Operation
with N
(5 psec)
Code 70
The number in the memory address bits of the instruction
word is placed
in the Accumulator.
If the indirect
address bit is ONE, the complement
of
N (- N) is put in the Accumulator.
Shift Group
(5 psec)
sft Operation Code 66
This group of instructions
will rotate or shift the Accumulator
and/or
the In-Out
Register.
When the two registers operate combined,
the InOut Register
is considered
to be an @-bit magnitude
extension
of the
right end of the Accumulator.
Rotate is a non-arithmetic
cyclic shift. That is, the two ends of the
register are logically
tied together
and information
is rotated
as though
the register were a ring.
Shift is an arithmetic
operation
and is, in effect, multiplication
of the
number
in the register by 2 fN, where N is the number
of shifts; plus is
left and minus is right.
The number
of shift or rotate steps to be performed
(N) is indicated
by the number of ONES in Bits 9 thru 17 of the instruction
word. Thus,
Rotate Accumulator
Right nine times is 671777. A shift or rotate of one
place can be indicated
nine different
ways. The usual convention
is to
use the right end of the instruction
word (rar 1 = 671001).
Rotate
Accumulator
rar N
Operation
Right
(5 psec)
Rotates
number
the bits of the Accumulator
right N positions,
of ONES in Bits 9-17 of the instruction
word.
Code 671
16
where
N is the
Rotate
ral N
Accumulator
Left
(5 psec)
Operation Code 661
Rotates
number
the bits of the Accumulator
left N positions,
of ONES in Bits 9-17 of the instruction
word.
Shift Accumulator
sar N Operation
where
(5 psec)
Right
Code 675
Shifts the contents of the Accumulator
right N positions,
the number
of ONES in Bits 9-17 of the instruction
word.
Shift Accumulator
sal N Operation
where
In-Out Register Right
Operation Code 672
where
Rotate In-Out Register Left
ril N Operation Code 662
where
N is
where
N is
(5 psec)
Rotates the bits of the In-Out
Register left N positions,
the number
of ONES in Bits 9-17 of the instruction
word.
Shift In-Out Register Right
sir N Operation Code 676
(5 psec)
Shifts the contents of the In-Out
Register right N positions,
is the number
of ONES in Bits 9-17 of the instruction
word.
Shift In-Out Register Left
sil N Operation Code 666
N is the
(5 psec)
Rotates the bits of the In-Out
Register right N positions,
the number
of ONES in Bits 9-17 of the instruction
word.
where
N
(5 psec)
Shifts the contents of the In-Out
Register left N positions,
the number
of ONES in Bits 9-17 of the instruction
word.
Rotate
rcr N
N is
Left
(5 psec)
Code 665
Shifts the contents of the Accumulator
left N positions,
number
of ONES in Bits 9-17 of the instruction
word.
Rotate
rir N
N is the
where
N is
AC and IO Right
(5 psec)
Operation Code 673
Rotates the bits of the combined
registers right in a single ring N positions, where N is the number
of ONES in bits 9-17 of the instruction
word.
Rotate
rcl N
AC and IO Left
(5 psec)
Operation Code 663
Rotates the bits of the combined
registers left in a single ring N positions, where N is the number
of ONES in Bits 9-17 of the instruction
word.
.
(5 psec)
Shift AC and IO Right
scr N Operation Code 677
Shifts the contents of the combined
registers right N positions,
N is the number
of ONES in Bits 9-17 of the instruction
word.
17
where
Shift AC and IO Left
(5 wsec)
scl N Operation Code 667
Shifts the contents of the combined
registers left N positions,
N is the number
of ONES in Bits 9-17 of the instruction word.
where
Skip Group
(5 psec)
skp Operation Code 64
This group of instructions
senses the state of various
flip-flops
and
switches in the machine.
The address portion
of the instruction
selects
the particular
function
to be sensed. All members of this group have the
same operation
code.
The instructions
in the Skip Group may be combined
to form the inclusive OR of the separate skips. Thus, if Address 3000 is selected, the
skip would occur if the overflow
flip-flop
equals ZERO or if the In-Out
Register is positive.
The combined
instruction
would still take 5 microseconds.
Skip on ZERO Accumulator
sza Address 100
(5 psec)
If the Accumulator
is equal to plus ZERO (all bits are ZERO), the Program Counter
is advanced
one extra position
and the next instruction
in the sequence is skipped.
Skip on Plus Accumulator
spa Address 200
(5 psec)
If the sign bit of the Accumulator
is ZERO, the Program
Counter is advanced one extra position and the next instruction
in the sequence is
skipped.
Skip on Minus Accumulator
sma Address 400
(5 psec)
If the sign bit of the Accumulator
is ONE, the Program
Counter is advanced one extra position
and the next instruction
in the sequence is
skipped.
Skip on ZERO Overflow
szo Address 1000
(5 psec)
If the overflow flip-flop
is a ZERO, the Program
Counter is advanced one
extra position and the next instruction
in the sequence will be skipped.
The overflow
flip-flop
is cleared by the instruction.
This flip-flop
is set
by an addition
or subtration
that exceeds the capacity of the Accumulator. The overflow
flip-flop
is not cleared by arithmetic
operations
which do not cause an overflow.
Thus, a whole series of arithmetic
operations
can be checked for correctness by a single szo. The overflow
flip-flop
is cleared by the “Start”
Switch.
Skip on Plus In-Out
spi Address 2000
Register
If the sign digit of the In-Out
is indexed
one extra position
skipped.
(5 psec)
Register is ZERO, the Program
Counter
and the next instruction
in sequence is
18
Skip on ZERO Switch
szs Addresses 10, 20.
(5 psec)
.70
If the selected Sense Switch is ZERO, the Program
Counter is advanced
one extra position
and the next instruction
in the sequence
will be
skipped. Address 10 senses the position
of Sense Switch 1, Address 20
Switch 2, etc. Address 70 senses all the switches. If 70 is selected all 6
switches must be ZER@ to cause the skip.
Skip on ZERO Program Flag
szf Addresses 0 to 7 inclusive
(5 psec)
If the selected program
flag is a ZERO, the Program
Counter
is advanced one extra position and the next instruction
in the sequence will
be skipped. Address 0 is no selection. Address 1 selects Program
Flag 1,
etc. Address 7 selects all program
flags. All flags must be ZERO to cause
the skip.
Operate Group
(5 psec)
opr Operation Code 76
This instruction
group performs
miscellaneous
operations
on various
Central Processor Registers. The address portion of the instruction
specifies the action to be performed.
The instructions
in the Operate Group can be combined
to give the
union of the functions.
The instruction
opr 3200 will clear the AC, put
TW to AC, and complement
AC. If the number minus zero is interpreted
as an instruction,
the IO is cleared, AC gets the complement
of the TW
switches, all program
flags are set and the computer
halts.
Clear In-Out Register
cli Address 4000
Clears
(sets equal
(5 psec)
to plus zero)
Load Accumulator
lat Address 2000
the In-Out
from Test Word
Register.
(5 usec)
Forms the inclusive
OR of the C(AC)
and the contents
of the Test
Word. This instruction
is usually
combined
with address 200 (clear
Accumulator),
so that C (AC) will equal the contents of the Test Word
Switches.
Complement
Accumulator
cma Address 1000
Complements
(makes
negative)
(5 psec)
the contents
of the Accumulator.
Halt
hlt Address 400
Stops
the computer.
Clear Accumulator
cla Address 200
Clears
(sets equal
(5 psec)
to plus zero)
the contents
19
of the Accumulator.
Clear
elf
Selected
Program
Flag
(5 psec)
Address 01 to 07 inclusive
Clears the selected program
flag. Address 01 clears Program
02 clears Program
Flag 2, etc. Address 07 clears all program
Set Selected
stf
Program
Flag
iot
1,
(5 psec)
Addresses 11 to 17 inclusive
Sets the selected program
flag. Address 11 sets Program
Flag
Program
Flag 2, etc. Address 17 sets all program
flags.
In-Out
Flag
flags.
Transfer
Operation
Group
(5 psec without
1; 12 sets
in-out wait)
Code 72
The variations
within this group of instructions
perform all the in-out
control
and information
transfer
functions.
_If Bit 5 (normally
the Indirect Address bit) is a ONE, the computer
will ha-d
wait for the completion
pulse from the device activated.
When this device delivers
its
completion,
the computer
will resume operation
of the instruction
sequence.
An incidental
fact which may be of importance
in certain scientific or
real time control applications
is that the time origin of operations
following an in-out completion
pulse is identical
with the time of that pulse.
Most in-out operations
require a known minimum
time before completion.
This time may be utilized
for programming.
The appropriate
In-Out Transfer
is given with no in-out wait (Bit 5 a ZERO). The instruction sequence then continues.
This sequence must include an iot instruction which performs nothing but the in-out wait, and the instruction
must
occur before the safe minimum
time. A table of minimum
times for all
in-out devices is delivered
with the computer:
it lists minimum
time before completion
pulse and minimum
In-Out
Register free time.
20
III.
INPUT-OUT
EQUIPMENT
STANDARD
EQUIPMENT
PAPER TAPE READER
The paper tape reader of the PDP-1 is a photoelectric device capable of
reading 300 lines per second. Three lines form the standard
B-bit
word
when reading binary
punched
eight-hole
tape. Five, six, and seven-hole
tape may also be read.
Read Paper Tape, Alphanumeric
rpa
iot 1
In this mode, one line of tape is read for each In-Out
Transfer.
All
eight holes of the line are read. The information
is left in the right
eight bits of the In-Out
Register,
the remainder
of the register being
left clear.
The code of the off-line tape preparation
typewriter
(Friden
FPC-8
” Flexowriter”)
contains an odd parity bit. This bit may be checked by
the read-in program.
The Friden Code is then converted
to a concise
six-bit code. This conversion
squeezes out the fifth bit (parity)
and
drops the eighth bit. The carriage return character
(Friden 200) is con-
verted to 77.
The more concise code is used by the on-line
magnetic
tape. A list of characters
and their
typewriter,
printer,
and
codes is found on Pages
30 and 31.
Read Paper Tape Binary
rpb iot 2
For each In-Out
Transfer
instruction,
three lines of paper tape are
read and assembled
in the In-Out
Register
to form a full computer
word. For a line to be recognized
in this mode, the eighth hole must be
punched;
i.e., lines with no eighth hole will be skipped
over. The
seventh hole is ignored. The pattern
of holes in the binary tape is arranged so as to be easily interpreted
visually
in terms of machine
instruction.
Read-In
Mode
This is a special mode activated
by the “Read-In”
switch on the console. It provides
a means of entering
programs
which neither
rely on
programs
in memory
nor require a plug board. Pushing
the “ReadIn” switch starts the reader in the binary
mode. The first group of
three lines, and alternate
succeeding
groups of three lines, are interpreted as “‘Read-In”
mode instructions.
Even-numbered
groups of
three lines are data. The “Read-In”
mode instructions
must be either
“deposit
in-out”
(dio Y) or “jump”
(jmp Y). If the instruction
is dio
Y, the next group of three binary lines will be stored in memory
location Y and the reader continues
moving.
If the instruction
is jmp Y,
the “‘Read-In”
mode is terminated
and the computer
will commence
operation
at the address of the jump instruction.
21
PAPER TAPE PUNCH
The standard PDP-1 paper tape punch has a nominal speed of 20 lines
per second. It can operate in either the alphanumeric mode or the binary
mode.
Punch Paper Tape, Alphanumeric
ppa
iot 5
For each In-Out Transfer instruction one line of tape is punched. InOut Register Bit 17 conditions Hole 1. Bit 16 conditions Hole 2, etc.
Bit 10 conditions Hole 8.
Punch Paper Tape, Binary
ppb
iot 6
For each In-Out Transfer instruction one line of tape is punched. InOut Register Bit 5 conditions Hole 1. Bit 4 conditions Hole 2, etc. Bit
0 conditions Hole 6. Hole 7 is left blank. Hole 8 is always punched in
this mode.
TYPEWRITER
The typewriter
will operate in the input mode or the output
mode.
Type Out
tyo iot 3
For each In-Out Transfer instruction one character is typed. The
character is specified by the right six bits of the In-Out Register.
Type In
tyi iot 4
This operation is completely asynchronous and is therefore handled
differently than any of the preceding in-out operations.
When a typewriter key is struck, Program Flag 1 is set. At the same
time the code for the struck key is presented to gates connected to the
right six bits of the In-Out Register. This information will remain at
the gate for a relatively long time by virtue of the slow mechanical
action. A program designed to accept typed-in data would periodically
check the status of Program Flag 1. If at any time Program Flag 1 is
found to be set, an In-Out Transfer instruction with Address 4 must
be executed for information to be transferred. This In-Out Transfer
should not use the optional in-out halt. The information contained in
the typewriter’s coder is then read into the right six bits of the In-Out
Register. tyi does not clear the IO. The tyi is usually preceded by cli
and elf-1.
OPTIONAL
EQUIPMENT
MAGNETIC TAPE
The magnetic tape system consists of the magnetic tape control
unit and one or more tape transport units which contain the read
and write circuits. The tape control unit contains the equipment to
select the active transport
and the logic necessary to control the
system.
22
The method of recording is non-return-to-zero.
Each flux change
represents a binary ONE. The reading is done at two levels of sensitivity. A check is performed at each level. Thus the high level of
sensitivity detects the presence of excessive noise and the low sensitivity detects weak ONES.
The transports operate at 75 inches per second with a recording
density of 200 bits to the inch. The format is the same as for the
IBM 729 I. Seven tracks are written:
six are binary or alphanumeric bits, and a seventh is used as a lateral parity. At the completion of a record, which may be of arbitrary length, a longitudinal
parity is written.
REALTIME
CLOCK
A special input register may be connected to operate as a real
time clock. This is a counting register operated by a crystal controlled oscillator.
The state of this counter may be read at any time by the‘appropriate In-Out Transfer instruction.
The computer stops only long
enough to provide synchronization
with the clock oscillator, then
resumes operation in phase with it.
CATHODE RAYTUBE
DISPLAY
The PDP-1 cathode ray tube display is useful for presentation
of
graphical or tabular data to the operator. For each In-Out Transfer
instruction,
one point is displayed. The first 10 bits of the In-Out
Register, Bits O-9, are the X’coordinate
of the point. Bits O-9 of the
Accumulator
are the Y coordinate of the point.
23
24
An additional display option is
the computer is signaled that the
point displayed. Thus the program
as changing the display or shifting
a light pen. By use of this device
operator is interested in the last
can take appropriate
action such
operation to another program.
LINE PRINTER
A 72-column line printer is available as an on-line printing station.
The operating speed is 450 lines per minute. A simple one-line buffer
is part of this equipment.
The appropriate
In-Out Transfer instruction is repeated to fill the buffer. The order to print is then
given. Following the completion of the line print, the printer returns
a completion pulse and spaces the paper.
ANALOG EQUIPMENT
Equipment
providing analog input to and output from the computer can be provided. This equipment
can take the form either of
high speed electronic equipment or shaft position conversion equipment. In either case, multiplexing
can be provided.
OTHER OPTIONAL EQUIPMENT
Additional
in-out devices may be added to PDP-1 with, at most,
a few hour’s work on the machine. Sockets for several In-Out Transfer variation pulse commands are prewired. Space is provided for
additional
gates to and buffers from the In-Out Register. The inout system is sufficiently simple so that the control circuitry needed
for any additional
device is minimal.
Sequence Break System
An optional in-out control is available for PDP-1. This control,
termed the Sequence Break System, allows concurrent operation of
several in-out devices and the main sequence. The system has, nominally, 16 automatic interrupt
channels arranged in a priority chain.
A break to a particular
sequence may be initiated by the completion of an in-out device, the program, or any external signal. If
this sequence has priority, the C (AC), C (IO), C (PC), and the contents of the memory field flip-flops (if present) are stored in adjacent
fixed locations unique to that sequence. The Program Counter is
reset to the address contained in a fourth fixed location. The program is now operating in the new sequence. This new sequence may
be broken by a higher priority sequence. A typical program loop
for handling an in-out sequence would contain 3 to 5 instructions,
including the appropriate
iot. These are followed by load AC and
load IO from the fixed locations and an indirect jump to location of
the previous C (PC). This last instruction
terminates the sequence.
The Sequence Break System provides PDP-1 with much of the
power of a multiple sequence machine or of a computer having inout synchronizers or automatic
trunks.
25
IV.
UTILITY
PROGRAMS
The Utility
Programs for PDP-1 are designed to provide the
nucleus of a growing system of programs. Programs available upon
delivery of the machine are:
SYMBOLIC ADDRESS ASSEMBLY PROGRAM is the basic element in
the utility system. It is designed for maximum
flexibility
consistent with adequate indication
of program errors. Numerous
macro instructions
are included such as floating point add, subtract, multiply, divide, decimal-to-binary
conversion, and binaryto-decimal
conversion.
MEMORY PRINT-OUT can appear
the line printer, if connected.
either on the typewriter
or on
BINARY PUNCH will punch out a specified region of memory.
Check characters are included on the tape. The program is available in both the binary read-in format and the read-in mode
format.
BINARY READ-IN reads the tapes prepared by the Binary Punch
Program. Several versions of this program are available. They
differ in the region of memory in which the read-in program is
written. Thus, various read-in programs are available in both the
binary read-in format and the read-in mode format.
MAINTENANCE PROGRAMS include programs for checking memories, input-output
equipment,
and operation
of the Central
Processor.
26
V.
APPENDIX
ABBREVIATED
INSTRUCTION
BASIC
Instruction
Code #
add
and
Y
Y
40
02
dac
dap
Y
Y
24
26
dio
dip
Y
Y
32
30
dis
idx
Y
Y
56
44
ior
Y
04
iot
isp
Y
Y
72
46
jmp
Y
60
jw
Y
62
lac
law
Y
N
20
70
law-N
71
lio
Y
mus Y
opr
sad Y
22
54
76
50
sas
Y
52
skp
sub
Y
66
64
42
xor
Y
06
shift
LIST
INSTRUCTIONS
Explanation
Add C(Y) to C(AC)
Logical AND C(Y) with
C(AC)
Put C(AC) in Y
Put contents of address
part of AC in Y
Put C(I0)
in Y
Put contents of instruction part of AC in Y
Divide step
Index (add one) C(Y),
leave in Y & AC
Inclusive
OR C(Y)
with
c(AC)
In-out transfer,
see below
Index and skip if result
is positive
Take next instruction
from Y
Jump to Y and save
program
counter in AC
Load the AC with C(Y)
Load the AC with the
number
N
Load the AC with the
number
-N
Load IO with C(Y)
Multiply
step
Operate,
see below
Skip next instruction
if C(AC)
# C(Y)
Skip next instruction
if C(AC)
= C(Y)
See below
Skip, see below
Subtract
C(Y) from
c(AC)
Exclusive
OR C(Y)
with C(AC)
27
Oper. Time
b--c)
10
Page Ref.
10
10
14
15
10
10
15
15
10
10
15
14
10
14
10
15
20
10
14
5
15
5
10
16
14
5
16
5
10
10
5
16
15
14
19
10
16
10
5
5
16
16
18
10
13
10
14
13
instruction
cla
elf
Code #
760200
760001-7
cli
cma
hlt
lat
764000
761000
760400
762200
stf
760011-7
OPERATE
GROUP
Explanation
Clear AC
Clear selected Program
Flag
Clear IO
Complement
AC
Halt
Load AC from Test
Word switches
Set selected Program
Flag
IN-OUT
ma
730005
rwb
rpa
730006
730001
wb
tyi
730002
720004
tYo
730003
TRANSFER
sma
spa
spi
sza
szf
640400
640200
642000
640100
64000f
szo
641000
szs
6400S0
ral
rar
rcl
661
671
663
rcr
673
ril
rir
sal
662
672
665
Page Ref.
5
5
5
5
20
19
19
19
5
5
19
20
19
GROUP
Punch paper tape
alphanumeric
Punch paper tape binary
Read paper tape
alphanumeric
Read paper tape binary
Read typewriter
input
switches
Type out
SKIP
Oper. Time
(b4sec)
5
22
22
21
21
5
22
22
5
5
5
5
18
18
18
18
5
19
5
18
5
19
5
5
17
16
5
17
5
5
5
5
17
17
17
17
GROUP
Skip on minus AC
Skip on plus AC
Skip on plus.10
Skip on ZERO (SO) AC
Skip on ZERO flag
(f = flag ii)
Skip on ZERO overflow
(and clear overflow)
Skip on ZERO sense
switch (S = switch #)
SHIFT/ROTATE
Rotate AC left
Rotate AC right
Rotate combined
IO left
Rotate combined
IO right
Rotate IO left
Rotate IO right
Shift AC left
28
GROUP
AC &
AC &
SHIFT/ROTATE
Instruction
GROUP (Continued)
Explanation
Code #
Oper. Time
(wet)
5
675
667
Shift
tltft
AC right
combined
AC & IO
scr
677
combined
AC & IO
sil
sir
666
676
Shift
right
Shift
Shift
sar
SC1
NUMERICAL
Code
00
02
04
06
10
12
14
16
20
22
24
26
30
32
34
36
IO left
IO right
INSTRUCTION
lac
lio
dac
dap
dip
dio
*
*
* spare
code, computer
29
will
18
5
5
5
17
17
17
Instruction
add
sub
idx
isp
sad
sas
mus
dis
jmp
jw
skp
shift
law
iot
*
40
42
44
46
50
52
54
56
60
62
64
66
70
72
74
76
and
ior
x01‘
*
*
*
*
halt
17
5
LIST
Code
Instruction
*
Page Ref.
ALPHANUMERIC
CODES
TABLE I
Character
Friden
Code
Concise
Code
Character
Friden
Code
Concise
Code
aA
bB
c c
dD
eE
fF
gG
hH
i I
141
142
163
144
165
166
147
150
171
121
122
103
124
105
106
127
130
111
062
043
064
045
046
067
61
62
63
64
65
66
67
70
71
41
42
43
44
45
46
47
50
51
22
23
24
25
26
27
YY
070
051
040
001
002
023
004
025
026
007
010
031
020
073
153
061
160
133
100
174
172
076
200
177
30
31
20
01
02
03
04
05
06
07
10
11
00
33
73
21
60
53
40
74
72
36
77
j J
kK
1L
mM
nN
00
PP
qQ
rR
s s
tT
uu
vv
WW
xx
ZZ
0)
1'
2@
3#
4=
5 %
6#
7?
8*
9 (
Space
, ,
il
&;
$- "
Upper Case
Lower Case
Tab.
Can-. Ret.
Tape Feed
TABLE II
Friden
001
002
004
007
010
020
023
025
026
031
040
Character
1'
2@
4=
7?
8*
Space
3#
5 %
6$
9 (
0 .I
30
Friden
Character
043
045
046
051
061
062
064
067
070
073
076
tT
vv
ww
zz
/ :
ss
uu
xx
YY
&b.
TABLE II (Continued)
Friden
100
103
105
106
111
121
122
124
127
130
133
141
142
Character
- ”
1L
Friden
144
147
150
153
160
163
165
166
171
172
174
177
200
nN
00
rR
j J
kK
mM
PP
sQ
$aA
bB
Character
dD
gG
hH
.
&;
c
eE
f
i
Lower
.
c
F
I
Case
Upper Case
Tape Feed
Carr. Ret.
TABLE III
Concise Code
00
01
02
03
04
05
06
07
10
11
20
21
22
23
24
25
26
27
30
31
33
36
40
41
Character
Concise Code
Character
Space
1 ’
42
43
44
45
46
47
50
51
53
60
61
62
63
64
65
66
67
70
71
72
73
74
77
kK
1 L
mM
nN
00
PP
2@
3#
4=
5%
6#
7?
8 *
9 (
0 1
/ :
s s
tT
uu
vv
WW
xx
YY
zz
k:b.
- JI
j J
31
sQ
rR
$a;
aA
bB
c
dD
e
f
gG
hH
i
Lower
.
c
E
F
I
Case
.
Upper Case
Carr. Ret.