Abstract: The manufacturing supply chain ecosystem is facing some unique challenges in addressing the memory requirements for emerging applications where high bandwidth and density, based on real-time random operations are required. High Bandwidth Memory (HBM2) meets these requirements and delivers unprecedented bandwidth, power efficiency and small form factor for applications such as high performance computing, networking, deep learning, virtual reality, gaming and cloud computing. The adoption of 2.5D technology presents a multitude of game-changing advantages for chip designers facing the complexity and cost of smaller geometries. Adding interposer into the design increases the complexity of package design, assembly and testing, both at the wafer level and the SiP level. A comprehensive understanding of the total 2.5D HBM2 ASIC SiP manufacturing supply chain ecosystem, and the unique set of requirements that each of its stakeholders encounter, is necessary for the successful ramping of HBM2 ASIC SiP designs into volume production.

Panel Discussion:

Who: Dan Leung, Director of Packaging and Assembly, Open-SiliconPanel Title: “EDA and IC Design and Manufacturing and Test”When: Friday, September 22, 2017, Afternoon SessionWhere: SEMI, 673 S. Milpitas Blvd, Milpitas, CAFocus: This panel, moderated by Herb Reiter, President of eda 2 asic Consulting, and Ron Leckie, President of INFRASTRUCTURE Advisors, will address the evolution of the semiconductor supply chain and the major improvements that have been made to integrate the various functional groups into the design-to-manufacturing flow, even in the face of increased outsourcing. While manufacturing data flows reasonably well in a forward direction between several functional groups, it could be improved by going in the reverse direction, where there are many opportunities to improve feedback for enhanced quality, reliability and yields. There is a lot of talk about “Big Data”, but what should the industry be doing to apply it to improve the links from EDA/Design to Fab to Assembly/Test to the Customer/Consumer? This panel will feature panelists from Open-Silicon, Cisco, NVIDIA, Invensas, PDF Solutions and Advantest.

About EDPS

The Electronic Design Process Symposium has fostered the free exchange of ideas among the top thinkers, movers and shakers who focus on how chips and systems are designed in the electronics industry. It provides a forum for this cross-section of the design community to discuss state-or-the-art improvements to electronics design processes and CAD methodologies, rather than on the functions of the individual tools themselves. To register for the event, please visit the EDPS registration page.

About Open-Silicon

Open-Silicon transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers’ products by innovating at every stage of design – architecture, logic, physical, system, software and IP – and then continues to partner to deliver fully tested silicon and platforms. Open-Silicon applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing and test capabilities. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed 300+ designs and shipped over 130 million ASICs to date. Privately held, Open-Silicon employs over 250 people in Silicon Valley and around the world. To learn more, visit www.open-silicon.com

Open-Silicon is a trademark and service mark of Open-Silicon, Inc. registered in the United States and other jurisdictions. All other trademarks are the property of their respective holders.