Ok, I think it's about time we tried to put all known Wii U specification things into its own thread and try to have a civil discussion.

Hard facts (either publicly disclosed, or a non-public leak which can be vouched by somebody trustworthy on this very forum):

MCM design: GPU+eDRAM die and CPU die on the same substrate.

2 GB of DDR3 memory @800MHz (DDR3-1600), organized in 4x 4Gb (256Mx16) modules, sitting on a 64bit bus (@800MHz). That gives a net BW of 12800MB/s (12.5GB/s). We can conveniently refer to this pool as 'MEM2'. Currently 1GB of that pool is reserved for the OS.

32 MB of unknown organisation, unknown specs eDRAM, sitting with the GPU. We can conveniently refer to this pool as 'MEM1'

Memory access specifics: both MEM1 and MEM2 are read/write accessible by the CPU, both subject to caching. GPU in its turn also has access to both pools, and is likely serving as the north bridge in the system (an educated guess, subject to calling out).

System is equipped with extra co-processors in the shape of an ARM (unknown architecture) and a DSP core (again of unknown architecture) primarily for sounds workloads.

BluRay-based optical drive, 22.5MB/s, 25GB media.

Immediate logical implications from the above (i.e. implications not requiring large leaps of logic):

Not all WiiU CPU cores are equal - one of them is meant to do things the other two are not. Whether that is related to BC, OS tasks, both, or neither, is unclear.

The shared access to MEM1 pool by the GPU and CPU alike indicated the two units are meant to interact at low latency, not normally seen in previous console generations. Definitely a subject for interesting debates this one is.