Learn how new investments in IP help improve system power usage and energy efficiency and enable added functionality for IoT applications including wearable and machine-to-machine devices.Ron Lowman, Strategic Marketing Manager for IoT, SynopsysJan 27, 2015

Learn about the benefits and challenges of moving from a planar CMOS process to FinFET and how DesignWare embedded memory and logic library IP can enable this move.Xueheng Ren, Senior Field Application Engineer, SynopsysJan 15, 2015

Learn how increasing system complexity as sensor fusion functions in IoT apps expand to include biometric control features can be addressed with a tightly integrated sensor and control IP subsystem.Rich Collins, Product Marketing Manager, Synopsys
Nov 12, 2014

Learn about the benefits and challenges of moving from a planar CMOS process to FinFET and how DesignWare embedded memory and logic library IP can enable this move.Prasad Saggurti, Product Marketing Manager for Embedded Memory IP, Synopsys Jul 22, 2014

Learn about the new HDMI 2.0 specification and how it changes the landscape for multimedia SoCs and devices. Get an overview of Synopsys' HDMI 2.0 IP solution and the implementation choices available.Tina Hu, Interface IP FAE, SynopsysApr 15, 2014

In this webinar we will use several real-world examples to highlight why ASIPs can offer computational performance close to fixed-function hardware blocks, providing instruction-level and data-level parallelism, as well as by introducing specialized hardware operators.Markus Willems, Product Marketing Manager, SynopsysApr 15, 2014

A complete, standalone platform with all the hardware and software needed for software development, debugging, and profiling will significantly accelerate code development for SoC designs.Allen Watson, Product Marketing Manager for ARC Development Tools, Systems and Ecosystem, SynopsysApr 08, 2014

Learn about the new HDMI 2.0 specification and how it offers consumers the ultimate home theater experience. This webinar describes the HDMI 2.0 specification, compares it to previous version, and details its new audio, video, and security features.Manmeet Walia, Senior Product Marketing Manager for DesignWare HDMI IP, SynopsysJan 30, 2014

Learn about the main analog-to-digital converter (ADC) architectures, how the Successive-Approximation Register (SAR)-based ADC architecture is ideal for ADC implementation in 28nm process nodes and beyond and how it exploits the high speed and high processing power offered by these advanced process technologies.Ming Han, FAE for Analog IP, Synopsys Jan 14, 2014

Learn about the new DesignWare ARC HS Family of high-end embedded processors and how the processors can be quickly optimized to maximize performance and minimize power.Mike Thompson, Sr. Product Marketing Manager, SynopsysDec 12, 2013

Learn what performance trends to consider, where in the system to integrate audio, what challenges are associated with integrating audio in advanced nodes and who to consider in a make vs buy decision.Ben U, Senior Manager of Analog Design, SynopsysApr 10, 2013

Learn about ways to maximize system performance while managing power budgets of CPU, GPU, and other SoC blocks, each with different performance/power/area targets.Ken Brock, Product Marketing Manager, Logic Libraries, SynopsysApr 02, 2013

Learn how Synopsys optimized its DesignWare® ARC™ processor to run Linux and what open source tools and software are available to support the processor.Allen Watson, Product Marketing Manager for DesignWare ARC Tools, OS and Ecosystem, SynopsysJan 15, 2013

Learn about the major features of DDR4 SDRAM as they apply to embedded applications, including key areas for SoC designers to note to take advantage of DDR4’s enhancements over previous generations.Graham Allan, Senior Product Marketing Manager for Memory Interface IP, SynopsysNov 13, 2012

Learn what performance trends to consider, where in the system to integrate audio, what challenges are associated with integrating audio in advanced nodes and who to consider in a make vs buy decisions.Craig Zajac, Senior Product Marketing Manager, SynopsysSep 25, 2012

Learn about the ARC processor architecture in the DesignWare ARC Android solution which enables performance optimizations for the most power and cost sensitive market segments.Chris Wu, Staff FAE, SynopsysMay 09, 2012

Learn how the new ARC EM processor family enables development of advanced processors with optimum balance of performance, power and area; performance exceeding 1.5 DMPS/MHz; and power-efficiency of less than 2uW/DMIPS at 28-nm.Steve Tateosian, Product Marketing Manager ARC Processors, SynopsysOct 25, 2011

The Webinar will explore trade-offs and implementation issues through lessons learned from the development of Synopsys DesignWare IP for PCI Express solutions and the customers that have used them.Frank Kavanagh, Senior Engineering Manager, DesignWare Digital Controllers for PCI Express, Synopsys Oct 20, 2011

The IEEE IP-XACT specification is a valuable format that can help solve IP integration challenges when combined with quality tools designed for an IP-based design and verification flow.John A. Swanson, Senior Manager, SynopsysMar 17, 2011