Your trust is our top concern, so companies can't alter or remove reviews.

Apr 3, 2015

ASIC Design Engineer Interview

Anonymous Employee in Santa Clara, CA

No Offer

Positive Experience

Average Interview

Application

I applied through an employee referral. The process took a week – interviewed at Marvell Technology (Santa Clara, CA) in December 2014.

Interview

phone interview -- just general question because i got refer from my friends onsite interview -- got me email from HR to arrange my interview date and time i had 5 people for interview most of them were nice, but one guy was very annoying. i coudn't understand his question, so i asked again. but he was angry because i asked again. had a lunch with them and talk about general question

Other Interview Reviews for Marvell Technology

ASIC Design Engineer Interview

I applied online. The process took 2 weeks – interviewed at Marvell Technology (Santa Clara, CA) in November 2014.

Interview

apply online and after several weeks, I got phone interview. It is about ASIC design/verification. My background is more focus on Verification of microprofessor, FPGA. Not very familiar with ASIC flow.so it is very important for background match.

ASIC Design Engineer Interview

I applied online. The process took 3+ months – interviewed at Marvell Technology (Santa Clara, CA) in November 2014.

Interview

I received a call for an onsite interview as I was in Santa Clara itself. I gave first onsite with 3 engineers. After 15-20 days I received call for another onsite with 4 engineers. The interviews were pretty basic stuff related to Verilog basics, FSM Design, FIFO related questions as well as on the resume. After 2nd onsite I waited for 2 months but I did not get any reply from HR or recruiter. Finally when I contacted manager, I was told that they had already selected some other candidate. They seriously should learn some professionalism and have the courtesy to give an update to someone who gave 2 onsite interviews. Totally disappointed with the process speed as well communication.

ASIC Design Engineer Interview

I applied through a recruiter. The process took 2+ weeks – interviewed at Marvell Technology (Santa Clara, CA) in March 2014.

Interview

one phone interview, asked about projects on the resume. Then asked about MESI protocol. Then Onsite interview. There are 5 people. First one asked basic CPU questions, such as 5 stage pipelined CPU. Second one asked me about reorder buffer in the out of order processor and load store queue. Third one asked about waveform questions. The last two asked me about some verilog questions.

ASIC Design Engineer Interview

I applied online. The process took 1 day – interviewed at Marvell Technology (Santa Clara, CA) in December 2012.

Interview

Online applications and call within 2-4 weeks. Strange thing manager called directly without scheduling an interview and started asking all sorts of questions. He was so impressed that towards the end he said the next round might be bypassed and HR might send the on-site invitation. Till date, I haven't heard back from them neither the HR nor the manager who called.

ASIC Design Engineer Interview

I was called for a phone interview first, talk about my previous experience, mainly about my resume, and ask some simple digital circuit question. One week after, I was scheduled for a screen interview, with 5 interviewers, last more than 3 hours. They asked some small questions, one guy still focus on the resume, some others ask some verilog question, some design question, quite straight-forward.

Interview Questions

All the questions are clear and normal. eg. write FSM in verilog, some DFT related questions. Answer Question

ASIC Design Engineer Interview

Interview process was straightforward. Phone interview followed by onsite with 6 1:1: interviews. All basic design question from VLSI, datapath design and bus architectures. The interview went well, but they have a simple policy of not responding to any emails under any pretext. I am under the assumption that I was not selected due to their strong inkling to be completely ignorant to my emails. At this point I have no regard for a company that treats candidates so poorly; it just shows the amount of respect (or lack of) that they have for people in general.

ASIC Design Engineer Interview

I applied through college or university. The process took 1+ week – interviewed at Marvell Technology (Santa Clara, CA) in September 2010.

Interview

Had a phone call with manager and later interviewed for multiple positions.... 1:1 and group/panel interview was all about the resume and small design questions and comp arch questions. They were looking for answers but never looked at the approach.....that was really bad....and I was not comfortable with interviewers except for couple of people

Glassdoor has 12 interview reports and interview questions from people who interviewed for ASIC Design Engineer jobs at Marvell Technology in San Jose, CA. Interview reviews are posted anonymously by Marvell Technology San Jose, CA interview candidates and employees.