Reclaiming lost yield through methodical power integrity optimization

As designs are moving to 28nm and beyond, designers fully experience the effects of the much higher power density and diminishing effectiveness of decoupling capacitances at these geometries: failures due to dynamic power noise integrity issues is a significant contributor to yield loss in many designs. Synchronous switching and increasing di/dt at advanced process nodes (Figure 1) makes it increasingly challenging for designers to deal with on-chip dynamic voltage drop (DVD) and high frequency electromagnetic interference (EMI). And neither is to be taken lightly; studies have shown DVD fluctuations introduce sizable gate delays causing timing-related yield loss, and EMI from digital switching similarly cause mixed-signal yield loss due to compromised noise integrity.

Designers already deal with a DVD ‘budget’. In a study done by Mentor Graphics and company SMIC, measuring failures across 25 designs, 49% of the yield loss was attributed to SCAN/ATPG/function fail defects (Figure 2).

To save cost of implementation, an on-chip Power Delivery Network (PDN) is often dimensioned for functional modes; not the worst-case test mode. As the scan test mode results in a higher dynamic power density than functional modes, chips that would work properly in functional mode actually fail in scan test due to the increased DVD. It is somewhat ironic that design methods and tests, which should guarantee more good products and higher profit, themselves contribute to an increasing yield loss