Xilinx’s Programmable Imperative

Look for news about Xilinx’s technology roadmap in the near future. What I can say is that they are posed to reap the following benefits:
> Lower chip process nodes means lower power, better performance, smaller size. This is a no-brainer.
> Continued – perhaps even accelerated – growth into traditional ASIC markets, including standard ASIC products thanks to increase lower-node manufacturing ASIC costs; consolidation of semi industry; and niche, fast appearing consumer niche markets.

This is the first time that I’ve heard Moshi Gavrielov, Xilinx CEO, speak before an audience. Impressive, especially since he’s an engineer as well, with a background in semiconductor world and EDA.

Presentation almost done. Soon is will be time for the “cool apps” portion of the event. But here is a teaser: Air graffitti light imaging in real-time through the video camera.

BTW: Great to see that Michael Santarini – formerly with EETimes – is doing well as Editor in Chief of Xilinx’s XCell Journal.

Hi Niall. Bit of a shameless plug for eASIC, isn’t it? Instead for pushing the company, you should push the technology.

Yes, there are good reasons to consider the use of other programmable fabrics, tho volume, IP and development tools become major considerations in addition to power consumption and cost. If you don’t that, just talk with the folks are MathLab and Ambric – now defunct.