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A CONTROL DATA 6000 SERIES COMPUTER SYSTEM

Display console (foreground) - includes a keyboard for manual input and
operator control and two 10-inch display tubes for display of problem status and
operator directives.

Mainframe (center) - contains 10 Peripheral and Control Processors, Central
Processor, Central Memory, some 1/O synchronizers. The main frame in this photo
is that of the 6600 Computer System; the mainframesfor the 6400 and 6500 systems
differ in physical appearance, depending on options included in the systems.

Handles operations basic to shifting. This includes left (circular)
and right (end-off sign extension) shifting, and Normalize, Pack, and
Unpack floating point operations. The unit also provides a mask generator.

Add

Performs floating point addition and subtraction on floating point
numbers or their rounded representation.

Performs floating point multiplication on floating point numbers or
their rounded representation.

Divide

Performs floating point division of floating point quantities or their
rounded representation. Also sums the number of "1's" in a 60-bit word.

Increment

Performs one's complement addition and subtraction of 18-bit numbers.

Instruction Formats

Groups of bits in an instruction are identified by the letters f, m, i, j, k,
and K (Figure 3-1). All letters represent octal digits except K,which is an
18-bit constant. The f and m digits are the operation code and identify the type
of instruction. In a few instructions the i designator becomes a part of the
operation code.

RNI to an address that is out-of bounds (occurs when an instr. is
located in absolute address (RA + FL) - 1).

Detect error condition

Clear P

Stop by reading(RA)

Write EM and (P) + 1 into RA

Detect error condition

Stop by reading (RA)

Nothing stored in RA

(P) = out of range P or (P) + 1

Branch to an address that is out-of-bounds.

Detect error condition

Clear P

Stop by reading (RA)

Write EM and jump address + 1 in RA

Detect error condition

Stop by reading (RA)

Nothing stored in RA

(P) = out of range P or (P)+1

Read Operand

Detect error condition

Clear P

Stop by reading (RA)

Write EM and (P) + 1 into RA

(Xi) = (AAZ)

Detect error condition

Read (RA) into Xi

Continue program

Write Operand

Detect error condition

Clear P

Stop by reading (RA)

Write EM and (P) + 1 into RA

Detect error condition

Read ( RA ) , but (Xi) not stored; (Xi) and (Ai) unchanged.

Continue program

Action After Exit Mode or Normal StopTypically, a
Peripheral and Control Processor periodically searches for an unchanging Central
Processor Program Address register (any value) to determine if the Central
Processor has stopped. Once it has been determined that the Central Processor
has stopped, the examining Peripheral and Control Processor can transfer control
to an error routine to determine the nature of the condition causing the Stop.
Figure 3-4 illustrates sample steps for processing Central Processor stops
(either Exit mode or normal).

These
instructions perform one's complement addition and subtraction of 18-bit
operands and store an 18-bit result in increment register Bi. An overflow
condition is ignored.

Operands are obtained from address (A), increment (B), and operand (X)
registers as well as the instruction itself (K = 18-bit signed constant).
Operands obtained from an Xj operand register are the truncated lower 18 bits of
the 60-bit word.

70

Six

Aj + K

Set Xi to Aj + K

(30 Bits)

71

SXi

Bj + K

Set Xi to Bj + K

(30 Bits)

72

SXi

Xj + K

Set Xi to Xj + K

(30 Bits)

73

SXi

Xj + Bk

Set Xi to Xj + Bk

(15 Bits)

74

SXi

Aj + Bk

Set Xi to Aj + Bk

(15 Bits)

75

SXi

Aj - Bk

Set Xi to Aj - Bk

(15 Bits)

76

SXi

Bj + Bk

Set Xi to Bj + Bk

(15 Bits)

77

SXi

Bj - Bk

Set Xi to Bj - Bk

(15 Bits)

These instructions perform one's complement addition and subtraction of
18-bit operands and store an 18-bit result into the lower 18 bits of operand
register Xi. The sign of the result is extended to the upper 42 bits of operand
register Xi. An overflow condition is ignored.

Operands are obtained from address (A), increment (B), and operand (X)
registers as well as the instruction itself (K = 18-bit signed constant).
Operands obtained from an Xj operand register are the truncated lower 18 bits of
the 60-bit word. EXAMPLE:

This
instruction forms a 60-bit one's complement sum of the quantities from operand
registers Xj and Xk and stores the result in operand register Xi. An overflow
condition is ignored.

37

IXi

Xi - Xk

Integer difference of Xj and Xk to Xi

(15 Bits)

This
instruction forms the 60-bit one's complement difference of the quantities from
operand registers Xj (minuend) and Xk (subtrahend) and stores the result in
operand register Xi. An overflow condition is ignored.

47

CXi

Xk

Count the number of "1's" in Xk to Xi

(15 Bits)

This
instruction counts the number of "1 's" in operand register Xk and stores the
count in the lower order 6 bits of operand register Xi. Bits 6 through 59 are
cleared to zero.