The bus frequency is only of relevance when acting as a master. The bus frequency should not be set higher than the max frequency accepted by the slowest device on the bus.

Notice that due to asymmetric requirements on low and high I2C clock cycles by the I2C specification, the actual max frequency allowed in order to comply with the specification may be somewhat lower than expected.

Please refer to the reference manual, details on I2C clock generation, for max allowed theoretical frequencies for different modes.

Parameters

[in]

i2c

Pointer to I2C peripheral register block.

[in]

freqRef

I2C reference clock frequency in Hz that will be used. If set to 0, then HFPER clock is used. Setting it to a higher than actual configured value only has the consequence of reducing the real I2C frequency.

[in]

freqScl

Bus frequency to set (actual bus speed may be lower due to integer prescaling). Safe (according to I2C specification) max frequencies for standard, fast and fast+ modes are available using I2C_FREQ_ defines. (Using I2C_FREQ_ defines requires corresponding setting of type.) Slowest slave device on bus must always be considered.

[in]

i2cMode

Clock low to high ratio type to use. If not using i2cClockHLRStandard, make sure all devices on the bus support the specified mode. Using a non-standard ratio is useful to achieve higher bus clock in fast and fast+ modes.

Get slave address used for I2C peripheral (when operating in slave mode).

For 10 bit addressing mode, the address is split in two bytes, and only the first byte setting is fetched, effectively only controlling the 2 most significant bits of the 10 bit address. Full handling of 10 bit addressing in slave mode requires additional SW handling.

Parameters

[in]

i2c

Pointer to I2C peripheral register block.

Returns

I2C slave address in use. The 7 most significant bits define the actual address, the least significant bit is reserved and always returned as 0.

Get slave address mask used for I2C peripheral (when operating in slave mode).

The address mask defines how the comparator works. A bit position with value 0 means that the corresponding slave address bit is ignored during comparison (don't care). A bit position with value 1 means that the corresponding slave address bit must match.

For 10 bit addressing mode, the address is split in two bytes, and only the mask for the first address byte is fetched, effectively only controlling the 2 most significant bits of the 10 bit address.

Parameters

[in]

i2c

Pointer to I2C peripheral register block.

Returns

I2C slave address mask in use. The 7 most significant bits define the actual address mask, the least significant bit is reserved and always returned as 0.

Set slave address mask used for I2C peripheral (when operating in slave mode).

The address mask defines how the comparator works. A bit position with value 0 means that the corresponding slave address bit is ignored during comparison (don't care). A bit position with value 1 means that the corresponding slave address bit must match.

For 10 bit addressing mode, the address is split in two bytes, and only the mask for the first address byte is set, effectively only controlling the 2 most significant bits of the 10 bit address.

Parameters

[in]

i2c

Pointer to I2C peripheral register block.

[in]

mask

I2C slave address mask to use. The 7 most significant bits define the actual address mask, the least significant bit is reserved and should be 0.

Set slave address to use for I2C peripheral (when operating in slave mode).

For 10 bit addressing mode, the address is split in two bytes, and only the first byte is set, effectively only controlling the 2 most significant bits of the 10 bit address. Full handling of 10 bit addressing in slave mode requires additional SW handling.

Parameters

[in]

i2c

Pointer to I2C peripheral register block.

[in]

addr

I2C slave address to use. The 7 most significant bits define the actual address, the least significant bit is reserved and always set to 0.

It may also be used in interrupt driven mode, where this function is invoked from the interrupt handler. Notice that if used in interrupt mode, NVIC interrupts must be configured and enabled for the I2C bus used. I2C peripheral specific interrupts are managed by this SW.

This function must be invoked in order to start an I2C transfer sequence. In order to actually complete the transfer, I2C_Transfer() must be used either in polled mode or by adding a small driver wrapper utilizing interrupts.

Note

Only single master mode is supported.

Parameters

[in]

i2c

Pointer to I2C peripheral register block.

[in]

seq

Pointer to sequence structure defining the I2C transfer to take place. The referenced structure must exist until the transfer has fully completed.