Variance FX™ is the leading commercial solution for generating timing derates for use with static timing analysis and physical IC design. Variance FX has made derate table characterization practical and effective. Variance FX™ can generate a SPICE accurate table for 1000 cells in a few hours per corner, where other solutions require weeks to generate tables for a few simple cells.

Variance FX supports all the major derate formats and works with all of the leading STA and PD tools (AOCV, POCV, Liberty Variance Format - LVF). It has the ability to handle process, voltage and temperature derate contributors, as well as constraint uncertainty. The Variance FX Database allows customization of the derate tables based on design specific requirements, and design margin methodology practices.

These advances in derate table generation are made possible by FX. FX is a trusted transistor model, circuit simulator and variance solver that sits at the heart of CLKDA’s margin analysis applications. FX has been validated at all of the major foundries, at 28nm, 20nm, 16nm and 14nm, on all of the major models (BSIM4, BSIMSOI, PSP, BSIMCMG, etc.), and on multiple proprietary and all third party libraries. It is currently in production at the most advanced process nodes in use today. The FX Variance Platform provides 3σ statistical accuracy 300,000 to 500,000 times faster than Monte Carlo SPICE.

Today’s Advanced SoC’s require new Margining Approaches

Today’s advanced SoC’s require a new approach to margining. There are too many corners, too much process variation, demanding power and performance requirements to use basic guardbands and over-margining. The single value OCV derate to protect against hold violations has become overly pessimistic in most cases, and dangerously optimistic in others. As the picture on the right illustrates, paths that have higher logic depths are treated pessimistically making it very difficult to close timing. Short paths can be optimistic, mask timing violations and cause defective parts.

Process Variance Impact on Delay

At small geometries, process variance can cause a 50% or more swing in delay. The graphic to the right shows the sensitivity of delay of a 28nm inverter to path depth. On shallow critical paths (which are very typical on the hold side), process variance contributes a major portion of the total delay.

Process Variance Impact on Constraints

Process variance also has a huge impact on timing constraints. Traditional corner based constraints may be significantly optimistic relative to process variance. Timing constraints, e.g. set up and hold checks, are used to determine the “slack” on each specific path in a design.

The graph to the right shows the set-up constraint for a flip-flop at 20nm. The line marked SS is the traditional corner timing constraint. The line marked SSG + 3 sigma is the statistical corner plus 3 sigma of variance. As can be clearly seen, the SS constraint could be very optimistic in extreme cases of process variance.

Ultra-Low Voltage Operation

The adoption of ultra-low voltage operation for power conservation puts even more stress on margin methodologies. Low voltage operation dramatically increases the impact of process variation. Not only is delay much more sensitive to process variation, but the sensitivity is non-Gaussian. When a distribution is non-Gaussian (non-normal), the variance is skewed, and can have a much higher than expected impact.

The figures to the right illustrate the sensitivity of delay of a 20nm inverter from 1V to .6V, and the skewed or non-Gaussian distribution at 1 and .65V. The voltage sweep shows how wide a swing process variance can cause. The distribution graph shows the asymmetric/non-Gaussian nature of variance at ultra-low voltage. This makes application of simplistic OCV numbers even more risky.

Major Obstacles in Adoption of Advanced Derates

There have been two major obstacles users have had to address as they adopted advanced derates: the cost of creating tables using SPICE, and table design to avoid excessive pessimism or optimism.

The first obstacle is the prohibitive cost of generating tables using SPICE. The current methodology requires thousands of SPICE or Fast SPICE Monte Carlo runs. Reducing the number of cells or only using clock cells in the table, dramatically reduce the overall benefits of applying derates. Shortcuts that attempt to estimate the values can be very risky and cause defective parts.

The second is designing ‘safe’ tables to match the margining strategy. Until full arc/load/slew tables are supported in STA and optimization tools, both of the current formats, AOCV and POCV, have limitations that force trade-offs. Only one arc/load/slew point can be used for each timing condition (early clock, late data, etc.). These trade-offs can either impose unnecessary pessimism, that reduces margin, or excessive optimism that can mask violations and cause defective chips.

Variance FX: Production Proven Performance, Accuracy, Functionality

Variance FX has made generating timing derates for use with static timing analysis and physical IC design a practical reality. It has the performance to generate derates for entire libraries in days instead of weeks or months; production proven accuracy to tackle the most advanced manufacturing processes; and the functionality to design and analyze tables for safety and effectiveness.

Performance: Variance FX can generate a complete variance database of every arc/load/slew point in a 1000 cell library in 1 hour per corner with 200 processors. Extracting a derate table from that database takes seconds. By way of comparison, SPICE Fast SPICE solutions take hours to generate single load/slew point derates for a handful of clock cells. Generating an accurate, complete table for a full library (combinational, registers, latches) with all arcs/loads/slews would literally take months with 100’s of SPICE licenses.

NOTE: commercial, SPICE or FAST SPICE based derate solutions are usually limited in at least one of three ways, all of which seriously compromise accuracy and table safety. (1) They require the end user to specify the target arc/load/slew table. This is inherently risky. Selecting a point in the middle of the table will be optimistic and dangerous. (2) They characterize a few sample cells, arc/load/slew points, and then infer the rest of the library. This will result in significant accuracy errors that can result incorrect derates or sigmas. (3) They limit the cells to be characterized to clock side or simple combinational only. This materially limits the value of derates with respect to recapturing margin for power optimization.

Production Proven Accuracy: Variance FX has been proven in production on more designs and libraries than any other commercial solution in the market today. Variance FX has been validated at all of the major foundries, at 28nm, 20nm, 16nm and 14nm, on all of the major models (BSIM4, BSIMSOI, PSP, BSIMCMG, etc.), and on multiple proprietary and all major third party libraries. It is currently in production at the most advanced process nodes on some of the leading SoC designs. Variance FX results are typically within 2% of mean ±3σ of the leading commercial SPICE results.

Support for all derate formats: AOCV, POCV and full arc/load/slew sigma Liberty tables.

Support for all cells, including all combinational logic, registers, latches, and level shifters.

Fully distributed derate calculation. Users have literally deployed over 1000 processors to simultaneously calculate variance. Distribution is fine grained – meaning work can be distributed down to the individual arc/load/slew.

Incremental operation. New cells can be added or updated.

Constraint uncertainty. Determines the sensitivity of set-up and hold constraints to process.

Voltage and temperature flat derates. Process, voltage and temperature variation can be combined into a single derate (typically applied to clock cells).

Derate impact validation. CLKDA can provide tools which enable users to assess the impact of different derate table designs on slack and violations without having to rerun STA. Path FX can also be used to verify how close the derates bring STA to SPICE accuracy.

Design Specific Derates and Hierarchical Design Specific Derates. Variance FX can adjust the derate tables to align with the actual load slew points in the design. This can either be at the full design level, or hierarchically which designs the optimal tables for up to 50 unique tables (limit is determined by STA not CLKDA).

The Variance FX Database

The Variance Database contains all of the variance data for every cell/arc/load/slew point in a library. This data can be used to generate tables, design specific tables, analyze cells or libraries for sensitivity to process variance, and to visualize the behavior of derates. The picture to the right shows one of the heatmaps that can be generated from the database. It shows the sensitivity of a cell’s delay at the corner, at a global corner/nominal, sigma and derate to load and slew. Information from the Variance Database can be exported directly to MATLAB, Excel, or other analysis tools.

Generating Tables with Variance FX

Variance FX makes generating derates a simple as possible. Variance FX reads in your libraries (the Liberty Library/.lib and the extracted/LPE netlists), and the SPICE model from the foundry. This is all of the input data required to extract the FX models. Variance FX then builds the Variance Database which contains all of the sensitivity information for each cell in the library. Variance FX then reads the database to deliver derate tables in whatever format is required. The database can also be used to cell and library analysis.

Variance FX: Derate Table Generation Made Practical

Variance FX makes derate table generation a practical reality for systematic margining for SoC designs. It is fast, production proven at the most advanced process nodes, and functionally robust. It works with all of today’s derate formats, and is ready to deliver the next generation of 3D tables now.