KSJ EtherCAT Master based on ARM CPU

KSJ EtherCAT master stack is developed for the purpose of industrial embeded systems. This master stack works on ARM CPU core with Ethernet MAC, and support ETG1500.classB standard, cable redundancy, DC function.

For fast cyclic master stack, DMA and EthernetMAC can be designed in FPGA area when using FPGA SoC.

As real-time OS on ARM CPU, FreeRTOS, Xenomai, eT-Kernel, Nucleus can be supported. (Other OS can be negociatable to implement) .

KSJ original LZ201 master board equipped with Xilinx Zynq SoC is helpful for evaluation. When this master stack using LZ201 board can achieved 60 μsec cyclic PDO communication, and about 500 nsec jitter with 3 slaves which has 32bit data for each.