Penryn

It wasnâ€™t too long ago that Intel announced its next generation processors based on the 45nm process back at the end of January. Now, just two months later weâ€™ve managed to secure an update on how this new process will feature in Intelâ€™s future Penryn and Nehalem CPUs, while Intel also let slip some future developments in its architecture that surprised even us.

Penryn: More than a die shrink.

If you missed Timâ€™s article about how Intel has conquered current leakage with its new Hafnium based High-K di-electric insulating and metal gate technology, the main benefits are 20 per cent faster transistor switching at the same power usage and an overall 30 per cent power reduction at the transistor level. What Intel told us today builds on that base technology.

Due in Q207, Penryn is going to carry on the Core micro architecture, continuing the rigorous two year cycle of new processes Intel has stuck to for the last ten years. 65nm was first introduced with Presler, Yonah and Dempsey, then later used with the Core 2 family which was launched in the middle of last year. Later this year Intel will launch its 45nm processors, starting with Penryn.

Itâ€™s easier to apply a new optical process to an existing architecture rather than something new, as you know where to look for defects. Rather than try to achieve too much at once, itâ€™s easier to keep things simple and do one change at a time.

Although, with the move to 45nm Intel has taken the time to implement some tweaks and improvements, higher core frequencies and increased IPC (instructions per clock cycle). We will be back into the 3GHz+ region, although there was no mention of where the frequency ceiling would be on the new platform. In addition thereâ€™s a new Fast Radix-16 Divider, which is essentially an improved division engine that can divide four bits at once instead of two. This can be used on both floating point and integer divide function, as well as square root calculations providing an average of 2x increase in performance in this sector. This may seem unimportant, but geometric and physics calculations in games, 3D rendering and many scientific applications inherently rely on math functions.

As Tim mentioned in his previous article, there will be 50 new SSE4 instructions specifically to further optimise media, RAID, gaming and graphics. In addition there will be better power management from an increased quantity of sleep states and increased cache sizes of 50 per cent - this means up to 6MB and 12MB for dual and quad core chips respectively. The front side bus (FSB) will increase in speed first on 65nm Core 2 to 1,333MHz, then later to 1,600MHz after the move to 45nm, before being lost almost entirely with Nehalem.