International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS)

書籍・会議録表題(英文)

巻数 (volume)

号数 (number)

ページ範囲 (pages)

257-262

組織名 (organization)

出版元 (publisher)

出版元 (英文)

出版社住所 (address)

刊行月 (month)

November

出版年 (year)

2015

付加情報 (note)

注釈 (annote)

内容梗概 (abstract)

Support Vector Machine is renowned as a powerful machine learning algorithm for many classification problems. However, among all the works proposed for SVM hardware implementation, a lot of them are designed with predefined settings for specific objective, rendering them usable only for single or few purposes. This paper presents an SVM hardware architecture capable of classifying input data with arbitrary vector dimensionality and arbitrary precision, resulting in a generic support vector machine capable of classifying various targets. The proposed architecture also employs a speed-up method called soft cascade algorithm to enhance its performance. To assess its hardware implementation, it is synthesized in twostyles using Xilinx FPGA and NanGate Open Cell Library. The results show a feasible circuit scale implementation, and when used for CoHOG pedestrian detection, the proposed hardware architecture is estimated to be capable of classifying up to 79 VGA images per second on FPGA and up to 35 HD images per second on 45nm process technology circuit, even under the condition that the architecture is not designed specifically for the aforementioned purpose.