Pete Hardee Bloghttps://community.cadence.com/search?q=*%3A*&category=blog&users=148438&sort=date%20descSearch results for '*:*' by user ID 148438en-USZimbra Community 8New Incisive Verification App and Papers at DVCon by Marvell and TIhttp://feedproxy.google.com/~r/cadence/community/blogs/148438/~3/S3P6MOxdLzI/new-incisive-verification-app-and-papers-at-dvcon-by-marvell-and-tiThu, 27 Feb 2014 21:57:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1331610Pete Hardee/cadence_blogs_8/b/fv/archive/2014/02/28/new-incisive-verification-app-and-papers-at-dvcon-by-marvell-and-ti0If you&#39;re an avid reader of Cadence press releases (and what self-respecting verification engineer isn&#39;t?), you will have noticed in our Incisive 13.2 platform announcement back on January 13 th that Incisive Formal technology, with our new Trident cooperating multi-core engine, took top billing. But you would have needed to be very diligent to have followed the link in the press release to the Top 10 Ways to Automate Verification document that explained some other aspects of the Incisive 13.2 Platform. There, weighing in at number 6, was a short description of our latest verification app, for register map validation. Verification apps apply combinations of formal, simulation and metric-driven technologies to mainstream verification problems. This approach puts the focus on the verification problem to be solved, rather than the attributes of the technology used to solve it. The Incisive verification apps approach is defined by the following principles: Supplement a well-documented methodology with dedicated tool capabilities focused on a high-value solution to a specific verification problem Use the appropriate combination of formal, simulation, and metric-driven technologies, aimed at solving the given problem with the highest efficiency Provide significant automation for creating the properties necessary to solve the given problem, reducing the need for deep formal expertise Provide customized debug capabilities specific to the given problem, saving considerable time and effort Verification App for Register Map Validation The new Register Map Validation app generates properties automatically from an IP-XACT register specification. You can exhaustively check a multitude of common register use cases like value after reset, register access policies (RW, RO, WO), and write-read sequences with front-door and back-door access. All these sequences are shown in clear, easy-to-use debug views. Correct register map access and absence of corruption is difficult and time-consuming to check sufficiently in simulation. The result is a reduction of verification set-up times and, combined with the Trident engine we mentioned before, huge reduction in execution times, reducing register map validation from weeks to days or even hours. But don&#39;t take my word for it - come to DVCon next week and hear Abdul Elaydi of Marvell, who will be presenting &quot;Leve raging Formal to Verify SoC Register Map&quot;, and Rajesh Kedia of TI, who will be presenting &quot;Accelerated, High-Quality SoC Memory Map Verification Using Formal Techniques&quot;, both on Wednesday, March 5. Pete Hardeehttps://community.cadence.com/cadence_blogs_8/b/fv/archive/2014/02/28/new-incisive-verification-app-and-papers-at-dvcon-by-marvell-and-tiUltra Low Power Benchmarking: Is Apples-to-Apples Feasible?http://feedproxy.google.com/~r/cadence/community/blogs/148438/~3/diheDAfizvg/ultra-low-power-benchmarking-is-apples-to-apples-feasibleTue, 12 Feb 2013 13:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1319707Pete Hardee/cadence_blogs_8/b/lp/archive/2013/02/12/ultra-low-power-benchmarking-is-apples-to-apples-feasible0I noticed some very interesting news last week, widely reported in the technical press, and you can find the source press release here . In a nutshell, the Embedded Microprocessor Benchmark Consortium (EEMBC) has formed a group to look at benchmarks for ultra low power microcontrollers. Initially chaired by Horst Diewald, chief architect of MSP430 TM microcontrollers at Texas Instruments, the group&#39;s line-up is an impressive &quot;who&#39;s who&quot; of the microcontroller space, including Analog Devices, ARM, Atmel, Cypress, Energy Micro, Freescale, Fujitsu, Microchip, Renesas, Silicon Labs, STMicro, and TI. As the press release explains, unlike usual processor benchmark suites which focus on performance, the ULP benchmark will focus on measuring the energy consumed by microcontrollers running various computational workloads over an extended time period. The benchmarking methodology will allow the microcontrollers to enter into their idle or sleep modes during the majority of time when they are not executing code, thereby simulating a real-world environment where products must support battery life measured in months, years, and even decades. Processor performance benchmarks seem to be as widely criticized as EPA fuel consumption figures for cars - and the criticism is somewhat related. There is a suspicion that manufacturers can tune the performance for better test results, rather than better real-world performance. On the face of it, the task to produce meaningful ultra low power benchmarks seems even more fraught with difficulties. For a start, there is a vast range of possible energy profiles - different ways that computing is spread over time - and a plethora of low power design techniques available to optimize the system for the set of profiles that particular embedded system is likely to experience. Furthermore, you could argue that, compared with performance in a computer system, energy consumption in an ultra low power embedded system has less to do with the controller itself and more to do with other parts of the system like the memories and mixed-signal real-world interfaces. EEMBC cites that common methods to gauge energy efficiency are lacking in growth applications such as portable medical devices, security systems, building automation, smart metering, and also applications using energy harvesting devices. At Cadence, we are seeing huge growth in these areas which, along with intelligence being introduced into all kinds of previously &quot;dumb&quot; appliances, is becoming known as the &quot;Internet of Things.&quot; Despite the difficulties, with which the parties involved are all deeply familiar, I applaud this initiative. While it may be difficult to get to apples-to-apples comparisons for energy consumption in these applications, most of the time today we don&#39;t even know where the grocery store is. If the EEMBC effort at least gets us to the produce department, we&#39;re going to be better off. Pete Hardeehttps://community.cadence.com/cadence_blogs_8/b/lp/archive/2013/02/12/ultra-low-power-benchmarking-is-apples-to-apples-feasibleLow-Power Technology Summit Proceedings Now Availablehttp://feedproxy.google.com/~r/cadence/community/blogs/148438/~3/Cg-Il1ET4UQ/low-power-technology-summit-proceedings-now-availableWed, 05 Dec 2012 21:09:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1317409Pete Hardee/cadence_blogs_8/b/lp/archive/2012/12/05/low-power-technology-summit-proceedings-now-available0On October 18, 2012 Cadence held a Low-Power Technology Summit at our San Jose, California headquarters. Experts from Cadence and other leading companies presented the latest low-power design methodologies. Well, it took us a while but you can now view the material via the Low-Power Technology Summit Proceedings archive, which just went live. We&#39;ve put both video and PDF versions of the presentations there. Obviously the PDFs give you the quickest access to the material, but you&#39;d be missing a lot to just grab those. Seeing and hearing the presenter in action is important, especially when one of the keynotes, entitled &quot; The power wall - are we scaling it or is it just getting higher? &quot;, is delivered by a noted expert like Professor Jan Rabaey of the University of California at Berkeley. The videos also have the Q&amp;A sessions at the end of each presentation -- there were lots of good questions, and good interaction. You do need a &quot;Cadence Community&quot; login to access those, so there will be a quick one-time registration for the login if you don&#39;t already have it. Prof. Jan Rabaey presents at the Low Power Technology Summit As well as the keynote from Professor Rabaey (which Richard Goering also covered in a blog here ), there were also presentations from Sathya Subramanian of ARM on Low-Power Design with ARM&#174; Physical IP and POP TM IP , and technical updates from the Cadence team. My personal highlight from the day was the presentation by Anis Jarrar of Freescale. Anis talked about all the measures they took to meet the aggressive power specifications on the Kinetis family of chips. Kinetis has been highly successful for Freescale, and they really are using all the tricks in the book (and then a few that aren&#39;t) to minimize power on these designs. You can also find more about Kinetis here . As well as the usual techniques (clock-gating, multi-Vt, Multi-Supply Voltage, Power Shut-off) they were also an early user of multi-bit register mapping in RTL Compiler. Further, they found a novel way to apply body bias that avoided the need for that inefficient, tricky way to generate a negative bias supply -- the charge pump. The audience was very happy to learn more about Anis&#39;s experiences, and the Q&amp;A session for this one was lively and informative. Finally, the presenters were joined by representatives of Broadcom and Berkeley Wireless Research Center for a panel session moderated by Richard Goering. Panelists provided a great low-power design-related discussion. You can also read Richard&#39;s blog on that, for a summary. Enjoy! Pete Hardeehttps://community.cadence.com/cadence_blogs_8/b/lp/archive/2012/12/05/low-power-technology-summit-proceedings-now-availablePerspective on Power: 2012 Survey Predicts 2013 as the Year of DVFShttp://feedproxy.google.com/~r/cadence/community/blogs/148438/~3/9SdXdfOPVv4/perspective-on-power-2012-survey-predicts-2013-as-the-year-of-dvfsThu, 29 Nov 2012 13:30:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1317151Pete Hardee/cadence_blogs_8/b/lp/archive/2012/11/29/perspective-on-power-2012-survey-predicts-2013-as-the-year-of-dvfs0The recent Low-Power Technology Summit held at Cadence headquarters in San Jose gave us a great opportunity to take the pulse of low-power design by surveying the attendees. Some of the data we got was expected, but there were a couple of surprises. First, some of the expected stuff. We&#39;d noticed in the last major surveys done almost two years ago (see the Perspective on Power blog from December 2010) that advanced low-power design techniques were starting to be applied outside of mobile (battery-operated) devices, and this trend has increased. 49% of the attendees surveyed worked on non-mobile end-applications. As in 2010, very nearly 100% were already using basic low-power techniques like clock gating and multi-Vt optimization. But the people using advanced techniques &quot;currently&quot; increased from 60% to 70% (see figure below). As before, we define advanced low power techniques as the ones that apply to power domains - splitting the design into separately-powered areas where the voltage can be shut off to reduce leakage (Power Shut-Off - PSO, aka State Retention Power Gating - SRPG) or supplied with different voltage levels (permanently in the case of Multi-Supply Voltage - MSV, or dynamically in the case of Dynamic Voltage and Frequency Scaling - DVFS). As in 2010, PSO was the most popular of the advanced techniques, followed by MSV, then DVFS. What was less expected was that, in contrast to 2010 where the &quot;future&quot; use of advanced techniques increased all of them proportionately, in the 2012 results, the designers surveyed were expecting to use a lot more DVFS in their next designs, pushing it into second place in front of MSV. So why might DVFS become more popular than MSV? Both use different supply voltages for domains that have different performance needs. The difference is that DVFS allows the voltage level, or more usually a combination of voltage and clock speed, to be selected on the fly based on current performance demand. It is therefore a more complex technique to implement and verify, meaning that the designer has to achieve sign-off for power domain to which it applies at multiple modes and corners. Also, opportunities to apply MSV may have already been fully exploited and designers are looking for more. Recently, design tools such as the Cadence Encounter RTL-to-GDSII flow support design closure for multi-mode multi-corner (MMMC) simulations, which is an important enabler for an increase in the use of DVFS on the next generation of designs. Pete Hardeehttps://community.cadence.com/cadence_blogs_8/b/lp/archive/2012/11/29/perspective-on-power-2012-survey-predicts-2013-as-the-year-of-dvfsPacked House Expected for Cadence Low-Power Technology Summithttp://feedproxy.google.com/~r/cadence/community/blogs/148438/~3/Xqysq9z6MJg/packed-house-expected-for-cadence-low-power-technology-summitTue, 16 Oct 2012 14:28:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1315813Pete Hardee/cadence_blogs_8/b/lp/archive/2012/10/16/packed-house-expected-for-cadence-low-power-technology-summit0It looks like it might be standing room only for latecomers to the Low-Power Technology Summit at Cadence headquarters building 10 auditorium this Thursday (18 October). Registration has been very strong. I&#39;m expecting a great day -- we have a full agenda covering multiple aspects of low-power design. No longer the sole preserve of designers needing to extend battery life, low-power design has become ubiquitous in many different applications from mobile devices to datacenters. We have recently seen a bifurcation in the needs of our customers --- on the one hand, for power optimization in high-performance digital design, and on the other hand, ultra-low-power design techniques in a myriad of smaller, lower performance but none-the-less challenging mixed-signal devices. There will be technology updates from Cadence focusing in each of these areas. We also expect the audience to be given plenty to think about from our keynote speaker, Professor Jan Rabaey, of U.C. Berkeley. I just wanted to highlight a few of my favorites that I&#39;m really looking forward to from the agenda. Keynote speech by Professor Jan Rabaey - see Richard Goering&#39;s blog from a couple of weeks ago for more information on Professor Rabaey Sathya Subramanian of ARM will talk about low-power support in ARM&#39;s physical libraries, memories, and also optimization of processor implementation with POP TM IP and ARM-Cadence collaboration on design flows Anis Jarrar of Freescale will talk about low-power design experiences on the latest Kinetis series of ARM Cortex&#174;M-powered mixed-signal chips Panel discussion moderated by Richard Goering with interesting diverse and experienced panelists: Sathya Subramanian of ARM Qi Wang of Cadence Anis Jarrar of Freescale Sushma Honnavara-Prasad of Broadcom Gary Kelson of the Berkeley Wireless Research Center For more details on the agenda, times and logistics, please see the Cadence event page . See you on Thursday! Pete Hardee Pete Hardeehttps://community.cadence.com/cadence_blogs_8/b/lp/archive/2012/10/16/packed-house-expected-for-cadence-low-power-technology-summitLow-Power Design Case Studies: 15 CDNLive! Papers So Far This Yearhttp://feedproxy.google.com/~r/cadence/community/blogs/148438/~3/q-zny9m2ybo/low-power-design-case-studies-15-cdnlive-papers-so-far-this-yearMon, 17 Sep 2012 10:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1314942Pete Hardee/cadence_blogs_8/b/lp/archive/2012/09/17/low-power-design-case-studies-15-cdnlive-papers-so-far-this-year0CDNLive! is back with a bang in 2012, with very strong support from the Cadence user community worldwide. We&#39;re three-quarters the way through the events at the time of writing -- you can see the whole program on www.cadence.com at the CDNLive! 2012 Worldwide page. Proceedings are published so far from San Jose, USA; Munich, Germany; and Hsinchu, Taiwan. If you click on those proceedings links, you get to a multitude of different tracks and, for those interested in everything low-power, it can be quite challenging to find all the relevant presentations. So I&#39;ve saved you the trouble of hunting through by gathering them all here - 12 so far from Cadence customers plus 3 useful presentations from Cadence&#39;s own technologists. Note: you will need to log in with your cadence.com user account to access the papers. If you don&#39;t have one, create a Cadence.com User Account now . A Comprehensive Approach to Verifying Low Power Mixed Signal Design using Conformal LP Norman Chan, Rambus Conformal Low Power - Complex Low Power Design Verification Sorin Dobre, Qualcomm CPF in AMS Simulation and Macro IP Qingyu Lin, Cadence Low Power Implementation on Freescale Kinetis Family Anis Jarrar, Freescale Semiconductor Techtorial: Low Power Failures--What not to Plan John Decker, Cadence Low-power Verification using UVM SystemVerilog John Decker, Cadence Automation of Switch Insertion and Power Network Generation in 28nm PSO Designs Shane Stelmach et al, Texas Instruments Multi Voltage Domain, Multi VT Low power physical implementation with Cadence tool suite Harald Hopperdietzel &amp; Uwe Ratzmann, Texas Instruments Power Calculation From Early Estimation to Silicon Correlation Johannes Bruecker, Renesas Electronics Implementation of a Flexible, Low Power and High Performance 4G Baseband Processor Peter Debacker et al, imec Hierarchical CPF Usage in ST-HED Low Power Flow Sylvie Pierunek, STMicroelectronics Early, Functional Unit-Based, Power Estimation for Wireless Baseband Processors Peter Debacker et al, imec Challenging Verification for Complex Low-Power Design without Always-Power-On Domain Zhaohui Hu, ST-Ericsson Effective GPU platform verification and power estimation solutions with Palladium Kaowen Liu, MediaTek Design Closure in 28nm Low-Power Design with EDI Jurcy Huang, Socle Huge thanks to all who contributed these presentations! Pete Hardeehttps://community.cadence.com/cadence_blogs_8/b/lp/archive/2012/09/17/low-power-design-case-studies-15-cdnlive-papers-so-far-this-yearMixed Signals from European Low-Power Designershttp://feedproxy.google.com/~r/cadence/community/blogs/148438/~3/30kAnOgHhLM/mixed-signals-from-european-low-power-designersWed, 25 Jul 2012 18:47:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1313319Pete Hardee/cadence_blogs_8/b/lp/archive/2012/07/25/mixed-signals-from-european-low-power-designers0Early summer is a good time to visit Europe. I was there for the first couple of weeks in July, before most of Europe disappears on vacation. I spent my time mainly with customers in Germany, Ireland and the UK. It&#39;s not the weather that makes it a good time to visit - while it was nice in Germany the Northern European summer has been a disappointment so far, although the two days I spent in Scotland were, I&#39;m told, the first two rain-free days since April. It was a good time because our customers were keen to get a mid-year update, especially since so few make the trip over to DAC nowadays. And we had plenty of interesting stuff to share. But the value for me is not really the communication of our latest stuff to our customers; it&#39;s more listening to what their changing needs are. More than I&#39;d ever experienced before, the needs stem from the confluence of low-power and mixed-signal design challenges. While much of the semiconductor industry globally seems preoccupied with digital design in advanced nodes like 28nm, and starting to think about 20nm and beyond, you can practically count the companies in Europe involved with such designs on the fingers of one hand. However, if I try to count the companies involved with mixed-signal designs, combined with the need to meet stringent power specifications, I fast run out of digits. The European chip design scene is all about mixed-signal and low-power in a wide range of mobile, automotive, industrial and medical applications. While designs tend to be implemented in less advanced process nodes - in companies I visited many new designs are moving to the 65nm node and designs at 90nm, 130nm and even 180nm are still commonplace - the designs are every bit as challenging. The challenges are just different. In the pure digital world, unless you&#39;ve been living under a rock for the past couple of decades, you probably know that CMOS process technology has been able to follow Moore&#39;s Law - the approximate doubling of transistor count every two years. Try doing that with RF devices, passives, power management components, MEMS, or in short, all of those components you need to interface with the (analog) real world. Fabs specializing in mixed-signal technologies have recently coined the phrase &quot;More than Moore&quot; to describe this challenge. Power-wise, these mixed-signal designs are no less challenging. Medical devices and smart card applications in particular have pushed back the state-of-the-art in ultra-low-power design. Power specifications in the automotive world have become tighter and tighter as the rapidly-growing electronics content adds up to significant power demand, and power densities are strictly controlled to avoid temperature-related reliability issues in an already pretty hostile environment. Depending on the application, and given the process nodes in use, most emphasis so far has been on reduction of dynamic power. Aggressive techniques including multi-supply voltages, and dynamic voltage and frequency scaling are commonplace. But with the move to 65nm and beyond, and especially if the application involves extended idle periods, controlling leakage is becoming more important and power gating is starting to be more widely deployed. While the complexity of power architectures may not seem to be as great as the latest mobile multimedia platform, nonetheless it&#39;s introducing multiple power domains and multiple power modes on top of the existing complexities of mixed signal design. This is critical, especially since verification complexity increases exponentially with complexity of the power architecture, and mixed-signal verification is already considerably more challenging than digital verification. Why? Continuous waveforms simulate slower than discrete, and techniques from the digital world like formal verification and hardware acceleration are almost impossible to apply, if the conventional mixed-signal verification methodology continues. So, many customers were interested in recent developments at Cadence that bring our mixed-signal and low-power solutions closer together. This inlcudes capabilities like power-aware mixed signal simulation with real number modeling (i.e. wreal ). Here, signals crossing the analog and digital domains are not just modeled abstractly for speed, but electrical-to-logical and logical-to-electrical conversion is power-aware, meaning all the logic states and their equivalent voltages are derived automatically from the Common Power Format (CPF) file. Also important is the ability to generate CPF from the analog circuitry in the Virtuoso schematic view, which makes a block that would be functionally a &quot;black box&quot; in digital formal verification tools like Conformal Low Power, look like a &quot;white box&quot; from the power intent point of view, enabling rigorous chip-level functional and structural checks of the integrated design&#39;s power intent. Mixed-signal and low-power design challenges seem daunting enough individually, but we&#39;re really starting to see what happens when they coincide. And hopefully, we&#39;re doing something useful about it. Pete Hardeehttps://community.cadence.com/cadence_blogs_8/b/lp/archive/2012/07/25/mixed-signals-from-european-low-power-designersWhat’s Cool for Low-Power at DAC?http://feedproxy.google.com/~r/cadence/community/blogs/148438/~3/Aa7YsWaO2E4/what-s-cool-for-low-power-at-dacWed, 30 May 2012 22:29:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1311481Pete Hardee/cadence_blogs_8/b/lp/archive/2012/05/30/what-s-cool-for-low-power-at-dac0Low-power design promises to be a key theme of the Design Automation Conference once again! At DAC 2012 at San Francisco&#39;s Moscone Center next week (June 4-7), if you need to cover design, implementation and verification of this important subject, there&#39;s a lot to choose from at Cadence&#39;s booth #1930. Here is a quick guide to presentations, demos and other events Cadence is involved with for low-power, as well as the latest updates on tools and flows support. 1. Luncheon on Overcoming the Challenges of Embedding Ultra Low-Power, ARM 32-bit Processors into Analog/Mixed-Signal Designs . Time: Tuesday June 5 th . 12:00PM - 1:00PM (doors open and food is served at 11:30 AM). Location: 270-276 (Moscone Convention Center). Register here . 2. Three exciting customer presentations on low-power design in the Cadence EDA360 Theater at Booth 1930: o Marvell on accelerating low-power implementation using CPF, Monday June 4 th at 12:30PM o Maxim on designing their ADCs with the Cadence low-power/mixed signal flow, Monday June 4 th at 3:00PM o Broadcom on a designer&#39;s perspective on power formats, Tuesday June 5 th at 4:30PM 3. A demo of applying the latest mixed-signal verification methodology on a mixed-signal design using Cortex-M0 in ultra low power application. Time: Monday June 4 th - Wednesday June 6 th . Location: ARM Booth #1414, #802. 4. Cadence booth demo pods - Monday June 4 th - Wednesday June 6 th 9:00AM-6:00PM, at Booth #1930: o Low-Power Verification in Mixed-Signal Design o Incisive Low-Power Verification with UVM SystemVerilog and e 5. Optimizing Power, Reducing Energy, and Meeting Schedule using an Advanced Low-Power Solution . Time: Monday Jun 4 th 5:00PM-6:00PM, Tuesday June 5 th 10:00AM-11:00AM, Wednesday June 6 th 3:00PM-4:00PM. Location Cadence Demo Suite #2 at Booth 1930. 6. Meeting Power Targets using a Digital Front-End Design and Verification Solution . Time: Monday June 4 th 9:00AM-10:00AM, Tuesday June 5 th 1:00PM-2:00PM. Location Cadence Demo Suite #3 at Booth 1930. 7. Implementing Low-Power and High-Performance ARM&#174; Cortex TM Processor-Based SoCs . Time: Monday Jun 4 th 11:00AM-1:00PM, Tuesday June 5 th 2:00PM-4:00PM, Wednesday June 6 th 11:00AM-1:00PM. Location Cadence Demo Suite #3 at Booth 1930. 8. Achieving Faster Timing and Power Closure using an Advanced Digital Signoff Analysis Solution . Time: Monday June 4 th 3:00PM-4:00PM, Tuesday June 5 th 10:00AM-11:00AM, Wednesday June 6 th 11:00AM-1:00PM. Location Cadence Demo Suite #3 at Booth 1930. 9. Improving Verification Coverage and Reducing Silicon Re-Spins for Functional and Low-Power Verification of Mixed-Signal Designs. Time: Monday June 4 th 3:00PM-4:00PM, Wednesday June 6 th 4:00PM-5:00PM. Location Cadence Demo Suite #2 &amp; #3 at Booth 1930. Not forgetting of course the Denali Party by Cadence . See you at DAC! Pete Hardeehttps://community.cadence.com/cadence_blogs_8/b/lp/archive/2012/05/30/what-s-cool-for-low-power-at-dacComment on Low-Power Design? Brian Bailey Gets Ithttp://feedproxy.google.com/~r/cadence/community/blogs/148438/~3/htwWv5oq65w/low-power-design-brian-gets-itThu, 03 May 2012 17:19:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:2688Pete Hardee/cadence_blogs_8/b/lp/archive/2012/05/02/low-power-design-brian-gets-itThanks Brian,You can bank on our continued help!https://community.cadence.com/cadence_blogs_8/b/lp/archive/2012/05/02/low-power-design-brian-gets-itLow-Power Design? Brian Bailey Gets Ithttp://feedproxy.google.com/~r/cadence/community/blogs/148438/~3/htwWv5oq65w/low-power-design-brian-gets-itWed, 02 May 2012 17:23:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1310673Pete Hardee/cadence_blogs_8/b/lp/archive/2012/05/02/low-power-design-brian-gets-it2Hats off to Brian Bailey! If you haven&#39;t been following his EDA Designline Power Series on eetimes.com you have been missing out. Throughout April, he&#39;s been running a pretty comprehensive series of editorials, opinion pieces and contributed articles on the subject of low power design. As he put it: &quot;I doubt if the EDA Designline, or in fact any Designline in the history of EE Times has ever had anything close to the concentration of design articles, opinions, book excerpts that I will be putting up this month - and all of them will be on the subject of power.&quot; And I agree. Contributions have come predominantly from EDA, and from pretty much all the players with any kind of power analysis, verification or optimization offering. There&#39;s good stuff from a lot of different companies, but since this is a Cadence blog, I make no apologies for highlighting the Cadence content here. In his opinion piece What Comes After Power Formats , Qi Wang elaborates on future developments we may see after the current focus on design automation for today&#39;s advanced low-power techniques. He touches on system level and software, novel clock tree methods, mixed-signal designs especially digitally-assisted analog, future process technologies, and 3D-IC. Next up, Buda Leung and I wrote a detailed case study of power analysis in Building predictability into your low-power design flow . We looked at the power savings achieved with multi-supply voltage domains, power shut-off, and multi-voltage threshold techniques, showing that RTL power estimation gets you early feedback on the benefit of these techniques, and could get pretty good correlation to sign-off analysis provided you use realistic activity vectors. We deservedly credited Paul Weil, John Decker and Mickey Rodriguez for the design work they did that made the article possible. Another major design article came from Luke Lang, who contributed Hierarchical methods for power intent specification . This article takes a comprehensive look at power intent specification for hierarchical designs, giving an in-depth &quot;how to&quot; on both top-down and bottom-up techniques, and pointing out that real-world design of any complexity is invariably a combination of both. Somewhere in the EDA Designline series, you can find an article on hierarchy management in UPF. Compare the two, and see which one makes more sense to you for real design. Maybe you will see why we&#39;re putting a lot of effort into driving methodology convergence with IEEE 1801 with broad industry backing, which is more fully explained in another EE Times article, co-written by ARM, Cadence, Qualcomm and TI, called Power Intent Formats: Light at the End of the Tunnel? In Brian&#39;s editorial Power 107: Power Delivery Networks , Brad Griffin is quoted extolling the benefits of full chip-package-board PDN modeling solutions. Finally, in Brian&#39;s latest editorial Power 108: Powering forward , I make some future predictions for 3 years and 10 years out. It&#39;s always difficult to know how far out on a limb to go on that kind of question, but all I ask is that, before you ridicule my predictions, let&#39;s see yours! However, I did note with a chuckle that, out of a list of 7 items predicted by a competitor for 10 years out, I believe Cadence customers already benefit today from 6 of them, with the remaining one on the roadmap slated for a release considerably sooner than a decade! Brian quite rightly pointed out that, 10 years out, you have to think a little outside the box. Pete Hardeehttps://community.cadence.com/cadence_blogs_8/b/lp/archive/2012/05/02/low-power-design-brian-gets-itCadence Customers to Showcase Advanced Low-Power Designs at CDNLive!http://feedproxy.google.com/~r/cadence/community/blogs/148438/~3/-V_vku8a6Pg/cadence-customers-to-showcase-advanced-low-power-designs-at-cdnliveThu, 08 Mar 2012 02:22:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1308762Pete Hardee/cadence_blogs_8/b/lp/archive/2012/03/07/cadence-customers-to-showcase-advanced-low-power-designs-at-cdnlive0CDNLive! Silicon Valley, taking place at the DoubleTree Hotel in San Jose, CA next week from March 13-14, 2012, brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs, and systems. This year&#39;s theme is Connect, Share and Inspire. There&#39;s a particularly strong showing this year for low power designs and techniques, with many user papers in Track 2, a shared track featuring Low Power and Mixed Signal. Track 2 low power papers are: 9:00 Tuesday: A Comprehensive Approach to Verifying Low Power Mixed Signal Design using Conformal LP; Rambus Inc. 9:00 Wednesday: Conformal Low Power - Complex Low Power Design Verification; Qualcomm Inc. 10:00 Wednesday: Low Power Implementation on Freescale Kinetis Family; Freescale 11:00 Wednesday: Low-Power Format CPF in Analog and Mixed-Signal Simulation and Macro IP Verification; Cadence Those interested in mixed signal designs will benefit by staying with Track 2 for the duration, while for those interested in low power design and power optimization for purely digital designs could check out my personal picks from these other tracks: Track 8 - High Performance 1:30 Tuesday: Being Green - what Good Design and ccopt (formerly Azuro) can do to Reduce Power; Netronome Systems Inc. 2:30 Tuesday: Mali-T604 Embedded General Purpose Computing for GPU implementation in CMOS32LP using Cadence Reference Methodology; ARM 3:45 Tuesday: Implementation strategies for a high performance and low-power ARM&#174; Cortex TM -A15 processor: Methodology and tools usage best practices; Texas Instruments 4:45 Tuesday: Improving Performance, Power and Area of a High Speed Dual-core ARM Cortex-A9 Processor with Clock Concurrent Optimization Technology; Broadcom Track 4 - Verification 3:45 Wednesday: Techtorial: Low Power Failures - What not to Plan; Cadence 4:45 Wednesday: Low-power Verification using UVM SystemVerilog; Cadence Of course, don&#39;t miss the keynote speeches from executives from ARM, TSMC and Cadence on Tuesday morning, and the Partner Expo on Tuesday evening. Go to CDNLive SV 2012 for more information. See you there next week! Pete Hardeehttps://community.cadence.com/cadence_blogs_8/b/lp/archive/2012/03/07/cadence-customers-to-showcase-advanced-low-power-designs-at-cdnliveDoes Substrate Biasing Have a Future?http://feedproxy.google.com/~r/cadence/community/blogs/148438/~3/aQu_r67jq5A/does-substrate-bias-have-a-futureMon, 06 Feb 2012 20:06:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1307751Pete Hardee/cadence_blogs_8/b/lp/archive/2012/02/06/does-substrate-bias-have-a-future0At Cadence, we often get asked about various low-power design techniques: how well they work, what are the implementation and verification issues associated with them, and how effective they are at various process nodes. As a general trend we see aggressive power reduction techniques being adopted more widely as many designs, and by no means only mobile designs, become increasingly power-sensitive. But while many advanced techniques (which we take to be the ones applied to power domains, such as power shut-off, as opposed to well-established optimizations like clock gating) are clearly growing rapidly in adoption, some less well-known techniques only seem to find favor with a few, and it&#39;s less clear whether adoption is increasing. In particular, it&#39;s widely believed that substrate biasing (AKA body biasing) gives a lesser return in more advanced process nodes (45/40, 32/28 and beyond). What&#39;s the latest we&#39;re hearing about this? First the stats... When we delivered live full-day low-power &quot;Tech on Tour&quot; symposiums around the world in late 2010 and early 2011, we met with over 500 designers interested in low power design. That gave us a great opportunity to survey them. Here&#39;s what we found for the adoption of low power technqiues: Biasing is currently used by 5% of our sample of designers, and expected near-future use is 17%. In comparison, for power shut-off, we found the technique in use by 51% currently and 68% in the near future. That would certainly imply the technique&#39;s adoption is growing. Now the anecdotal evidence... Here&#39;s what has been heard by a few of our low power experts worldwide when discussing biasing with customers: The top two reasons against using substrate biasing are bias supply routing congestion (which increases at more advanced nodes); and difficulty of generating all the bias supplies. Mobile device SoC&#39;s at advanced nodes need all the low-power techniques at the designer&#39;s disposal, including biasing, according to one major mobile SoC platform provider. Another provider sees their ability to widely-apply substrate biasing in their libraries and process as a significant differentiator. Some customers who do not apply biasing to the whole chip below 45/40nm instead apply the technique in conjunction with low voltage standby modes, especially in memories. At least one customer who used biasing successfully in a 90nm chip is applying biasing successfully to their next generation at 45nm, while another company using forward and reverse biasing in volume at 90nm struggled to meet timing in the next generation at 65nm. Future of substrate biasing: Substrate biasing is useful primarily to control leakage at near-threshold voltage in planar CMOS. When FinFET becomes the norm (already used in some 22/20nm processes and will become commonplace for the 14nm node), leakage is better controlled by the gate&#39;s 3-D topology and many experts believe use of substrate biasing is unlikely to offer further benefit. Current support for substrate biasing in the Cadence Low-Power Solution: Regardless of whether you believe substrate biasing is worth the effort, be assured that the technique is fully supported in Encounter Digital Implementation System and Conformal Low Power. However, please ensure it is also supported by your library provider and foundry. If you have any experiences to share about substrate biasing or any thoughts on its future, we&#39;d be happy to hear them! Pete Hardeehttps://community.cadence.com/cadence_blogs_8/b/lp/archive/2012/02/06/does-substrate-bias-have-a-futureLow Power Design in 2011 and Predictions for 2012http://feedproxy.google.com/~r/cadence/community/blogs/148438/~3/u26eRcTT5iA/low-power-design-in-2011-and-predictions-for-2012Thu, 22 Dec 2011 14:12:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1306548Pete Hardee/cadence_blogs_8/b/lp/archive/2011/12/22/low-power-design-in-2011-and-predictions-for-20120It&#39;s that time of year again - winding down towards the end of the year, taking some time with the family, and looking forward to returning refreshed for a new year. So what was the big news for low power in 2011 and what do we have to look forward to in 2012? It&#39;s sometimes humbling to look at one&#39;s own technology predictions and see how things fared a year or so further on. Sometime in 2010, I forget exactly when, I was on a &quot;virtual panel&quot; on an on-line technology conference. One of the questions was to comment on developments for future technologies in low power design. I offered the following three points: 20nm node probably marks the end for continuing Moore&#39;s law on planar CMOS because process variability and leakage gets further out of control. What will emerge to enable 16/14nm node and keep Moore going? Will it be 3-D transistors, will SOI finally become economically viable, or will something else emerge? Software is more and more influential on system power and we&#39;ve got to move up the abstraction level to cope with that. New techniques in ESL power estimation and modeling will emerge As application demands increase for mobile devices, and leakage becomes more of an issue even in standby modes, we will see the emergence of some energy harvesting techniques to compensate Note that I was not necessarily saying we&#39;d see all these within a year, but none-the-less, how did these predictions fare? The end-of-the-line prediction for planar CMOS beyond 20nm was pretty good, as it turns out. What&#39;s even better news is that the leading emergent technology, fabricating transistors in 3-D which seems to be most popularly named FinFETs, looks like being very workable. So much so that Intel didn&#39;t wait for the 14/16nm node, but is already deploying the technology at 22nm (ref: http://www.nytimes.com/2011/05/05/science/05chip.html ). Expected to be widely used at 14nm, FinFETs increase switching performance at reduced leakage, compared with planar CMOS, in a marvel of process technology engineering. This looks like it will have relatively little disruption on the current design tool flow, or current low power design techniques. Moore&#39;s Law looks good for a while yet. As far as software&#39;s influence on power is concerned, real developments in ESL tools seemed few and far between. That&#39;s yet to happen and maybe we&#39;ll see progress in 2012. However, here at Cadence, we are witnessing greatly increasing usage of our Palladium Verification Computing Platform, with CPF support and the Dynamic Power Analysis (DPA) option, for executing the complete chip pre-silicon with software to both test the correct execution of power management (CPF) and estimate power in various real system modes (DPA). Not truly ESL you may argue, but getting the job done. For energy harvesting, I thought we&#39;d see much cleverer application of solar, thermal and mechanical harvesting in a wider range of mobile devices by now. Maybe we have been too good at deploying existing power management techniques to stretch battery life to at least a full day, to make the inclusion of such technologies in the device economically viable. We should start to see these emerging in the next few years, if not 2012, surely. There you have it -- for what it&#39;s worth. I should mention that these predictions come with a money-back guarantee. If they fail to emerge as stated, I will happily refund exactly what you paid for them! Best wishes to you and yours for the Holidays and a happy and prosperous 2012. Pete Hardeehttps://community.cadence.com/cadence_blogs_8/b/lp/archive/2011/12/22/low-power-design-in-2011-and-predictions-for-2012Low Power Marketing Hype – And What They Don’t Tell Youhttp://feedproxy.google.com/~r/cadence/community/blogs/148438/~3/dECf328ufcA/low-power-marketing-hype-and-what-they-don-t-tell-youWed, 30 Nov 2011 15:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1305872Pete Hardee/cadence_blogs_8/b/lp/archive/2011/11/30/low-power-marketing-hype-and-what-they-don-t-tell-you0Here in the USA, we&#39;re just back from the Thanksgiving holiday. This year, I got caught up in &quot;Black Friday,&quot; which is the day after Thanksgiving, and one of the biggest shopping days of the year, especially for consumer electronics. I&#39;m afraid to say I was convinced enough by some compelling advertising for Black Friday sales to brave the crowds to get a new large-screen HDTV. Doing some minimal research, I had decided I wanted a new &quot;LED&quot; TV -- which is a term that causes some confusion, leading some to think that the LCD screen has somehow been replaced by an array of tiny LEDs. Not the case -- it&#39;s an LCD screen with LEDs used for backlighting in place of the older Cold Cathode (CCFL) method. The claims of greater contrast and more even screen were borne out by what I measured in the store with my carefully calibrated instrumentation (mark 1 eyeball). But since this is a low power blog, what I found really interesting was the degree to which the leading manufacturers marketed the low power aspects of their products. LED TVs do indeed have better power consumption than CCFL LCD. But the &quot;SmartPower&quot; technologies and comparisons of annual electricity costs for the models were prominently touted, with both green and economic benefits stressed. However, it occurred to me that maybe the largest benefit of low power in consumer electronics is not marketed. Lower power means lower operating temperature which means typically much greater reliability. Engineers who have ever been involved with burn-in testing (or at least those who know what a bath-tub curve is) know this to be true, and probably, we&#39;ve all had equipment fail at home. I still regularly find the need to clear out DVD covers and other stuff the kids have left that blocks the airflow to my DVR before that fails - again! Why isn&#39;t this marketed as an advantage? Maybe because that would involve admitting how poor the failure rates are on so many other models that don&#39;t have these smart power features. I&#39;d be interested to hear about any experiences out there with your electronics! Pete Hardeehttps://community.cadence.com/cadence_blogs_8/b/lp/archive/2011/11/30/low-power-marketing-hype-and-what-they-don-t-tell-youCadence Low Power Guru Wins Si2’s Distinguished Service Awardhttp://feedproxy.google.com/~r/cadence/community/blogs/148438/~3/LYg3GdExxtw/cadence-low-power-guru-wins-si2-s-distinguished-service-awardFri, 21 Oct 2011 18:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1304690Pete Hardee/cadence_blogs_8/b/lp/archive/2011/10/21/cadence-low-power-guru-wins-si2-s-distinguished-service-award0Normal 0 false false false EN-US X-NONE X-NONE MicrosoftInternetExplorer4 /* Style Definitions */ table.MsoNormalTable {mso-style-name:&quot;Table Normal&quot;; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:&quot;&quot;; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin-top:0in; mso-para-margin-right:0in; mso-para-margin-bottom:10.0pt; mso-para-margin-left:0in; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:&quot;Calibri&quot;,&quot;sans-serif&quot;; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:&quot;Times New Roman&quot;; mso-fareast-theme-font:minor-fareast; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin;} At the Si2 Conference held this week at Santa Clara, it was particularly pleasing to see Cadence&#39;s Qi Wang honored with a Distinguished Service Award. As stated in Si2&#39;s announcement : &quot;The Distinguished Service Award to Qi Wang is based on his many years of successfully guiding the Low Power Coalition Format Working Group through the release of the Common Power Format (CPF) 1.0, CPF 1.1, and CPF 2.0.&quot; The announcement continues: &quot;As an example of Qi&#39;s leadership, under his guidance the format working group has developed two Interoperability Guides to explain to the industry how to work with both CPF and 1801-2009.&quot; As attendees of the recent IEEE-1801 committee&#39;s face-to-face meeting in Cambridge can testify, Qi&#39;s enthusiasm and leadership are now extending beyond the confines of Si2&#39;s Low Power Coalition. Aided by Si2&#39;s contribution of CPF to IEEE, he&#39;s now addressing interoperability, or more to the point, methodology convergence, directly with IEEE-1801. It would be remiss of me not to also acknowledge the work of the other Si2 Distinguished Award Winner, David Hathaway of IBM. David&#39;s great work has led to great progress with power closure flows and power modeling. Congratulations to Qi and David! Pete Hardeehttps://community.cadence.com/cadence_blogs_8/b/lp/archive/2011/10/21/cadence-low-power-guru-wins-si2-s-distinguished-service-awardAnother Expert’s View on Power Intent and Hierarchyhttp://feedproxy.google.com/~r/cadence/community/blogs/148438/~3/mPjVFWB0pQY/another-expert-s-view-on-power-intent-and-hierarchyWed, 21 Sep 2011 17:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1301147Pete Hardee/cadence_blogs_8/b/lp/archive/2011/09/21/another-expert-s-view-on-power-intent-and-hierarchy0Normal 0 false false false EN-US X-NONE X-NONE /* Style Definitions */ table.MsoNormalTable {mso-style-name:&quot;Table Normal&quot;; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:&quot;&quot;; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin-top:0in; mso-para-margin-right:0in; mso-para-margin-bottom:10.0pt; mso-para-margin-left:0in; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:&quot;Calibri&quot;,&quot;sans-serif&quot;; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:&quot;Times New Roman&quot;; mso-fareast-theme-font:minor-fareast; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin;} In last month&#39;s blog entry &quot;An Expert&#39;s View on Power Formats and Methodology&quot;, I highlighted a recent interview by Ed Sperling with Sorin Dobre of Qualcomm, posted on the Low Power Engineering Community . Amongst other things, Sorin explained how Qualcomm takes advantage of the hierarchical methodology in the Common Power Format (CPF). This month, my good friend and Cadence colleague, Luke Lang, penned his third entry in a series of methodology articles, Hierarchical LP Design 3 in his &quot;Everything Low Power&quot; blog in the same on-line community. When taken with the other two ( Hierarchical LP Design and Hierarchical LP Design 2 ) the series adds up to a comprehensive tutorial on both the value and the &quot;how to&quot; of hierarchical methodology in a power format, and the tools that support the format. Luke first covers how macro modeling can capture power intent for IP blocks. Then he describes the capability to express power intent top-down, which can set rules abstractly without worrying about the details of all the power domain crossings lower in the design hierarchy. In his third entry, he elaborates on the bottom-up approach, and the ability to integrate the same block, in multiple situations requiring different use of the block&#39;s internal power intent capabilities. Finally he describes how to use virtual ports and virtual power domains to simplify specification of rules for design objects that will later appear lower in the hierarchy, as the design implementation refines. Not all these hierarchical capabilities are truly unique to CPF. In fact, there is hierarchy support in the IEEE 1801 standard for soft IP blocks, although it remains limited by Liberty in terms of the power intent that can be described for a macro IP block. Another big problem is the inclusion of Unified Power Format (UPF) 1.0 in 1801, which is still the subset of 1801 supported by most UPF-based low power tools, and has only limited and incomplete semantics in terms of hierarchy. So for now, these hierarchical capabilities are unique to the Cadence CPF-enabled low power solution. However, with our participation in IEEE 1801 and Si2&#39;s contribution of the CPF Open Low Power Methodology to IEEE 1801, we&#39;re rapidly progressing towards making these capabilities available to those who favor UPF too. Pete Hardeehttps://community.cadence.com/cadence_blogs_8/b/lp/archive/2011/09/21/another-expert-s-view-on-power-intent-and-hierarchyAn Expert’s View on Power Formats and Methodologyhttp://feedproxy.google.com/~r/cadence/community/blogs/148438/~3/TOqVRR6Q3LY/an-expert-s-view-on-power-formats-and-methodologyWed, 24 Aug 2011 15:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1293542Pete Hardee/cadence_blogs_8/b/lp/archive/2011/08/24/an-expert-s-view-on-power-formats-and-methodology0In the last five years since the introduction of power formats, using a side file to describe power intent such as power domains, power modes and associated interface logic has become the mainstream low power design methodology. This marks great progress toward automating complex low power design techniques, but our job is not done. A recent interview by Ed Sperling with Sorin Dobre of Qualcomm, posted on the Low Power Engineering Community , highlighted some typical challenges faced by designers when using power formats. If you were at DAC earlier this year in San Diego, you may have heard Sorin presenting his thoughts on this at the Cadence booth theater, too. The foremost problem highlighted by Sorin is the methodology inconsistency. As he points out, the methodology difference is not simply between CPF and IEEE 1801-2009, the two leading open power format standards, but within IEEE 1801 itself. 1801, also known as UPF 2.0, includes every feature of UPF 1.0, which was the Accellera version of the Unified Power Format (UPF) published in 2007. Because &quot;there are many inconsistencies between UPF 1.0 and IEEE 1801,&quot; as Sorin states, there are conflicting methodologies within 1801 itself. On the other hand, Sorin pin-pointed the hierarchical methodology and macro modeling for custom IP as &quot;well-defined in CPF&quot; and would like to see them ported to 1801 to improve low power design verification and implementation. Sorin goes on to explain that Qualcomm uses tools from multiple vendors which requires an interoperable power format flow between CPF and UPF. However, current methodology differences make the interoperable flow very difficult. In addition, because CPF can describe more power intent information than the UPF they are using, Sorin emphasized that &quot;you need to make sure you do all the checks with CPF so you have complete information.&quot; There is clear demand from user companies to have a converged power format. Here at Cadence, we agree that the first step toward convergence is methodology convergence. Sorin also mentioned Si2&#39;s role in this effort. In fact, Si2 contributed the Open Low Power Methodology (OpenLPM) to IEEE to facilitate this process. We are happy to see the industry converging on a unified low power methodology. While working with the industry, Si2 and IEEE to drive in this direction, Cadence remains committed to improving our CPF support and solidifying our low power solution to meet all of our customers&#39; needs. Pete Hardeehttps://community.cadence.com/cadence_blogs_8/b/lp/archive/2011/08/24/an-expert-s-view-on-power-formats-and-methodologyLow Power Design -- Alive and Well at DAChttp://feedproxy.google.com/~r/cadence/community/blogs/148438/~3/PTnW_FmiYC8/low-power-design-s-alive-and-well-at-dacTue, 14 Jun 2011 21:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1277893Pete Hardee/cadence_blogs_8/b/lp/archive/2011/06/14/low-power-design-s-alive-and-well-at-dac0Low power design was undoubtedly one of the themes of DAC this year -- especially at the Cadence booth. We drew lively interest on the DAC floor with our low power demo station, which was continuously busy especially on the free Monday. We were showing a new demo explaining how advanced low power techniques (&quot;advanced&quot; means the kind of techniques you need a power intent format to describe -- more on this later) tends to introduce two kinds of problems we see people struggle with: How can I get predictability early in the flow to decide which low power techniques will actually meet the power specification? Low power techniques introduce a whole new level of complexity, so how can I implement those techniques and verify that I did them correctly, ensuring no bug escapes? The demo neatly showed how a comprehensive Cadence solution, in this case highlighting Incisive Enterprise Simulator, RTL Compiler, Conformal Low Power and Encounter Power System, solves these twin issues. The demo sparked lively conversations with a good sample of San Diego and Southern California&#39;s rich population of power-aware designers, as well as dedicated travelers from further afield. Meanwhile, in the suites, I asked the attendees in each low power session how many were already using a power intent format, either UPF (Unified Power Format) or CPF (Common Power Format), as a gauge of who was already using advanced low power techniques. Typically, about half the room would put their hands up. This led to two further trends: On asking those with their hands up how many were using both UPF and CPF, almost all the hands stayed up! Strong confirmation of the need for format interoperability and methodology convergence, which just happened to be one of the subjects on which we presented. For those that didn&#39;t put their hands up, I confirmed the trend that many designers not in the traditional mobile applications are realizing that their next designs are likely to need advanced low power techniques anyway, either because they are moving to latest process nodes where leakage is an issue, or because they need to control the thermal profile for cost and reliability reasons, in the face of increasing performance of their devices. In the Cadence Theater on Tuesday, one low-power related presentation drew great interest - Sorin Dobre of Qualcomm presented his thoughts on power formats entitled &quot;Power Intent Methodology Convergence: A Case Study of Hierarchical Flow&quot;. Sorin is one of the engineers who would raise his hand to using both CPF and UPF, and his presentation described the need for methodology convergence for power intent formats, and especially the need to extend IEEE 1801 (UPF 2.0) with CPF&#39;s hierarchy capabilities. Which is quite fitting, since one week earlier, Si2 announced the contribution of relevant parts of the CPF specification to IEEE 1801 with a view to achieve exactly that. On Wednesday, the final day for the exhibition floor, with the agreement of Texas Instruments India, I presented a paper in the Cadence Theater on their behalf, first presented at CDNLive! India , detailing the work of Rakesh Hariharan, Prabhu Bhairi, and Nithin Maiya, in using Palladium to speed up RTL power-aware verification by up to 1000x. That also drew a sizable, engaged crowd. In these busy three days, San Diego lived up to its reputation as a hot-bed of advanced low power design. In forthcoming blogs, look for further explanation of the need for, and issues with, methodology convergence as we drive that issue forward with the standards groups. Pete Hardeehttps://community.cadence.com/cadence_blogs_8/b/lp/archive/2011/06/14/low-power-design-s-alive-and-well-at-dacReport from Japan – Quake Brings New Perspective on “Power”http://feedproxy.google.com/~r/cadence/community/blogs/148438/~3/YUbvpRa_drc/perspective-on-power-in-electronics-and-mother-natureTue, 15 Mar 2011 15:00:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1261057Pete Hardee/cadence_blogs_8/b/lp/archive/2011/03/15/perspective-on-power-in-electronics-and-mother-nature0Back in December, I wrote a blog entry entitled &quot; Perspective on Power - 300 Designers and 20,000 Miles Later... &quot;. After the latest leg of my travels last week, taking our EDA360 Tech on Tour Low Power Symposium on the road to Taiwan and Japan, I intended to write an update to that blog article. Clearly, the trip was overshadowed by recent events in Japan. The week started great -- I arrived at Taipei Airport on Sunday evening and went to the Cadence office in Hsinchu Monday morning and met up with my colleagues. The day was part customer visits and part preparation for the seminar the following day. The low power seminar in Hsinchu on Tuesday was very successful -- about 110 folks registered and over 100 actually attended. Customer feedback was very good. Wednesday was our travel day, leaving Taipei mid-morning and arriving at Narita in the afternoon, making it to the hotel very close to the Cadence office in Shin-Yokohama by early evening. Thursday was set aside for preparation for Friday&#39;s seminar, and some local editor meetings. On Friday 11 th March, our low power symposium started in the Innotech building in Shin-Yokohama at 10 a.m., and seemed to be going well. At 2:46 p.m. local time, our seminar was about three-quarters through, when it ended abruptly for reasons you must have been living under a rock these past few days if you haven&#39;t heard. It&#39;s strange -- as a long-time Bay Area resident, I&#39;ve experienced a few earthquakes, but when they first start, it takes a little while to realize what&#39;s happening. My first thought was to wonder who was kicking the back of my chair. Then, probably only a second later, I realized what it was. As the room started to rock more and more vigorously, everyone started to get up and evacuate. There were some announcements in Japanese confirming that&#39;s exactly what we should be doing. We were rocking the whole time as we evacuated the building (we were only on the 2 nd floor) and continued rocking outside at ground level. The movement was like a large ship on a rough sea -- we had guessed by now the quake was big, but also fairly distant. The high-rise buildings were visibly moving. The initial series lasted 2 to 3 minutes, and aftershocks were frequent and noticeable. After one particularly strong aftershock, we looked up at the plate glass windows of the Innotech building and decided to move away to find some open ground. I should stress that there was no visible damage in our vicinity and no real panic -- it&#39;s incredible how buildings and people alike stood up to this quake -- although we were by now hearing many emergency sirens. In other blogs, I&#39;ve written about cell phone technology from the point of view of power management. Here&#39;s how cellphone technology held up in this event -- there were no cellular voice channels available at all (that continued through Saturday) and even SMS texting was unavailable. Data on 3G phones worked, however. I made a mental note of that for my own family&#39;s emergency plans back home. I was already on the usgs.gov website finding out where and how strong the quake was. At first, they pegged it at 7.9. That later got increased to 8.8, then 8.9, and finally 9.0. One of my Cadence Japan colleagues was now tuning into digital TV on his cellphone. We watched in horror -- maybe 30 minutes after the main quake, maybe a little longer -- as live pictures showed the first tsunami waves hit land and destroy everything in their path. The whole experience has certainly put power in perspective for me, and reminded me, and the world I guess, of Mother Nature&#39;s awesome power. As I write, Japanese engineers are struggling to control one of the very few man-made phenomena that may begin to rival that power. Let&#39;s all hope and pray that the nuclear reactors are made safe without further incident. Japan will need a lot of help and support to recover. Let me encourage anyone who&#39;s reading to give what they can afford somewhere suitable like http://www.jrc.or.jp or www.american.redcross.org . Thanks. Pete Hardeehttps://community.cadence.com/cadence_blogs_8/b/lp/archive/2011/03/15/perspective-on-power-in-electronics-and-mother-natureComment on A Look Behind the Si2 CPF 2.0 Releasehttp://feedproxy.google.com/~r/cadence/community/blogs/148438/~3/2DMSIg2n4Ro/a-look-behind-si2-s-cpf-2-0-releaseThu, 17 Feb 2011 21:22:00 GMT75bcbcf9-38a3-4e2e-b84b-26c8c46a9500:1963Pete Hardee/cadence_blogs_8/b/lp/archive/2011/02/15/a-look-behind-si2-s-cpf-2-0-releaseYou&#39;re welcome Karen, pleased we got that straight! Petehttps://community.cadence.com/cadence_blogs_8/b/lp/archive/2011/02/15/a-look-behind-si2-s-cpf-2-0-release