ISP1583ETUM Summary of contents

IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - NXP ...

NXP Semiconductors 8.8 SoftConnect The USB connection is established by pulling pin DP (for full-speed devices) to HIGH through a 1.5 k pull-up resistor. In the ISP1583, an external 1.5 k pull-up resistor must be connected between pin RPU and ...

NXP Semiconductors 8.13 Interrupt 8.13.1 Interrupt output pin The Interrupt Conﬁguration register of the ISP1583 controls the behavior of the INT output pin. The polarity and signaling mode of the INT pin can be programmed by setting bits INTPOL and ...

NXP Semiconductors 8.13.2 Interrupt control Bit GLINTENA in the Mode register is a global interrupt enable or disable bit. The behavior of this bit is given in The following illustrations are only applicable for level trigger. Event A: When an ...

NXP Semiconductors 8.15 Power-on reset The ISP1583 requires a minimum pulse width of 500 s. The RESET_N pin can either be connected to V externally controlled (by the microcontroller, ASIC, and so on). When V connected to the RESET_N pin, ...

NXP Semiconductors 8.16.1 Power-sharing mode Fig 13. Power-sharing mode As can be seen in the 5 V-to-3.3 V voltage regulator. The input to the regulator is from V supplied through the power source of the system. When the USB cable ...

NXP Semiconductors Table 9. ISP1583 operation Normal bus operation Core power is lost Table 10. ISP1583 operation Clock will wake up: After a resume and After a bus reset Core power is lost Table 11. ISP1583 operation Back voltage is ...

NXP Semiconductors Table 19. ISP1583 operation Back voltage is not measured in this mode Power is lost Table 20. ISP1583 operation SRP is not applicable Power is lost ISP1583_7 Product data sheet Operation truth table for back voltage compliance V ...

NXP Semiconductors 9.2.4.1 Session Request Protocol (SRP) The ISP1583 can initiate an SRP. The B-device initiates SRP by data-line pulsing, followed by V pulsing. The ISP1583 can initiate the B-device SRP by performing the following steps: 1. Set the OTG ...

NXP Semiconductors Table 35. Bit Table 36. Buffer name SETUP Control OUT Control IN Data OUT Data IN 9.3.2 Control Function register (address: 28h) The Control Function register performs the buffer management ...

NXP Semiconductors buffer is automatically validated. The data packet will then be sent on the next IN token. When it is necessary to validate the endpoint whose byte count is less than MaxPacketSize, it can be done using the Control ...

NXP Semiconductors Example 1: Consider that the transfer size is 512 bytes and the MaxPacketSize is programmed as 64 bytes, the Buffer Length register need not be ﬁlled. This is because the transfer size is a multiple of MaxPacketSize, and ...

NXP Semiconductors Table 46. Bit The ISP1583 supports all the transfers given in Rev. 2.0”. Each programmable FIFO can be independently conﬁgured using its Endpoint MaxPacketSize register (R/W: 04h), but the ...

NXP Semiconductors In EOT-only mode, DIS_XFER_CNT must be set to logic 1. Although the DMA transfer counter can still be programmed, it will not have any effect on the DMA transfer. The DMA transfer will start once the DMA command ...

NXP Semiconductors Each interrupt bit can individually be cleared by writing logic 1. The DMA Interrupt bit can be cleared by writing logic 1 to the related interrupt source bit in the DMA Interrupt Reason register, followed by writing logic ...