May 19, 2013

PCI-X, short for Peripheral Component Interconnect eXtended, is a computer bus and expansion card standard that enhances the 32-bit PCI Local Bus for higher bandwidth demanded by servers. It is a double-wide version of PCI, running at up to four times the clock speed, but is otherwise similar in electrical implementation and uses the same protocol. It has been replaced in modern designs by the similar-sounding PCI Express (officially abbreviated as PCIe), with a completely different connector and a very different logical design, being a single narrow but fast serial connection instead of a number of slower connections in parallel.

Background

PCI-X was developed jointly by IBM, HP, and Compaq and submitted for approval in 1998. It was an effort to codify proprietary server extensions to the PCI local bus to address several shortcomings in PCI, and increase performance of high bandwidth devices, such as Gigabit Ethernet, Fibre Channel, and Ultra3 SCSI cards, and allow processors to be interconnected in clusters.

In PCI, a transaction that cannot be completed immediately is postponed by either the target or the initiator issuing retry-cycles, during which no other agents can use the PCI bus. Since PCI lacks a split-response mechanism to permit the target to return data at a later time, the bus remains occupied by the target issuing retry-cycles until the read data is ready. In PCI-X, after the master issues the request, it disconnects from the PCI bus, allowing other agents to use the bus. The split-response containing the requested data is generated only when the target is ready to return all of the requested data. Split-responses increase bus efficiency by eliminating retry-cycles, during which no data can be transferred across the bus.

PCI also suffered from the relative scarcity of unique interrupt lines. With only 4 interrupt lines (INTA/B/C/D), systems with many PCI devices require multiple functions to share an interrupt line, complicating host-side interrupt-handling. PCI-X added Message Signaled Interrupts, an interrupt system using writes to host-memory. In MSI-mode, the function's interrupt is not signaled by asserting an INTx line. Instead, the function performs a memory-write to a system-configured region in host-memory. Since the content and address are configured on a per-function basis, MSI-mode interrupts are dedicated instead of shared. A PCI-X system allows both MSI-mode interrupts and legacy INTx interrupts to be used simultaneously (though not by the same function.)

The lack of registered I/Os limited PCI to a maximum frequency of 66 MHz. PCI-X I/Os are registered to the PCI clock, usually through means of a PLL to actively control I/O delay the bus pins. The improvement in setup time allows an increase in frequency to 133 MHz.

Some devices, most notably Gigabit Ethernet cards, SCSI controllers (Fibre Channel and Ultra320), and cluster interconnects could by themselves saturate the PCI bus's 133 MB/s bandwidth. Ports using a bus speed doubled to 66 MHz and a bus width doubled to 64 bits (with the pin count increased to 184 from 124), in combination or not, have been implemented. These extensions were loosely supported as optional parts of the PCI 2.x standards, but device compatibility beyond the basic 133 MB/s continued to be difficult.

Developers eventually used the combined 64-bit and 66-MHz extension as a foundation, and, anticipating future needs, established 66-MHz and 133-MHz variants with a maximum bandwidth of 532 MB/s and 1064 MB/s respectively. The joint result was submitted as PCI-X to the PCI Special Interest Group (Special Interest Group of the Association for Computing Machinery). Subsequent approval made it an open standard adoptable by all computer developers. The PCI SIG controls technical support, training, and compliance testing for PCI-X. IBM, Intel, Microelectronics, and Mylex were to develop supporting chipsets. 3Com and Adaptec were to develop compatible peripherals. To accelerate PCI-X adoption by the industry, Compaq offered PCI-X development tools at their Web site. All major chip makers generally now have or have had some variant of PCI-X in their product lines.

Technical description

Dual Port Network Card for Single PCI-X slot to save on PCI-X slots and use the full potential of the PCI-X 64-bit bus

PCI-X revised the conventional PCI standard by doubling the maximum clock speed (from 66 MHz to 133 MHz)[1] and hence the amount of data exchanged between the computer processor and peripherals. Conventional PCI supports up to 64 bits at 66 MHz (though anything above 32 bits at 33 MHz is seen only in high-end systems) and additional bus standards move 32 bits at 66 MHz or 64 bits at 33 MHz. The theoretical maximum amount of data exchanged between the processor and peripherals with PCI-X is 1.06 GB/s, compared to 133 MB/s with standard PCI. PCI-X also improves the fault tolerance of PCI, allowing, for example, faulty cards to be reinitialized or taken offline.

The two most fundamental changes are:

The shortest time between a signal appearing on the PCI bus and a response to that signal occurring on the bus has been extended to 2 cycles, rather than 1. This allows much faster clock rates, but causes many protocol changes:

The ability of the conventional PCI bus protocol to insert wait states on any cycle based on the IRDY# and TRDY# signals has been deleted; PCI-X only allows bursts to be interrupted at 128-byte boundaries.

The initiator must deassert FRAME# two cycles before the end of the transaction.

The initiator may not insert wait states. The target may, but only before any data is transferred, and wait states for writes are limited to multiples of 2 clock cycles.

Likewise, the length of a burst is decided before it begins; it may not be halted on an arbitrary cycle using the FRAME# and STOP# signals.

Subtractive decode DEVSEL# takes place two cycles after the "slow DEVSEL#" cycle rather than on the next cycle.

After the address phase (and before any device has responded with DEVSEL#), there is an additional 1-cycle "attribute phase", during which 36 additional bits (both AD and C/BE# lines are used) of information about the operation are transmitted. These include 16 bits of requester identification (PCI bus, device and function number), 12 bits of burst length, 5 bits of tag (for associating split transactions), and 3 bits of additional status.

Versions

3.3v and 5v keying of 64-bit PCI cards (both PCI and PCI-X). While most 64-bit PCI-X slots are 5v and are backward compatible with common 32-bit 5v PCI cards, a number of 64-bit PCI-X slots are 3.3v and will not accept 5v cards, by far the most common voltage for 32-bit PCI cards

All PCI-X cards or slots have a 64-bit implementation and vary as follows:

Cards

66 MHz (added in Rev. 1.0)

100 MHz (implemented by a 133 MHz adapter on some servers)

133 MHz (added in Rev. 1.0)

266 MHz (added in Rev. 2.0)

533 MHz (added in Rev. 2.0)

Slots

66 MHz (can be found on older servers)

133 MHz (most common on modern servers)

266 MHz (rare, being replaced by PCI-e)

533 MHz (rare, being replaced by PCI-e)

Mixing of 32-bit and 64-bit PCI cards in different width slots

Most 32-bit PCI cards will function properly in 64-bit PCI-X slots, but the bus speed will be limited to the clock frequency of the slowest card, an inherent limitation of PCI's shared bus topology. For example, when a PCI 2.3, 66-MHz peripheral is installed into a PCI-X bus capable of 133 MHz, the entire bus backplane will be limited to 66 MHz. To get around this limitation, many motherboards have multiple PCI/PCI-X buses, with one bus intended for use with high-speed PCI-X peripherals, and the other bus intended for general-purpose peripherals.

Many 64-bit PCI-X cards are designed to work in 32-bit mode if inserted in shorter 32-bit connectors, with some loss of speed. An example of this is the Adaptec 29160 64-bit SCSI interface card. However some 64-bit PCI-X cards do not work in standard 32-bit PCI slots.

Installing a 64-bit PCI-X card in a 32-bit slot will leave the 64-bit portion of the card edge connector not connected and overhanging, which requires that there be no motherboard components positioned so as to mechanically obstruct the overhanging portion of the card edge connector.

PCI-X 2.0

In 2003, the PCI SIG ratified PCI-X 2.0. It adds 266-MHz and 533-MHz variants, yielding roughly 2.15 GB/s and 4.3 GB/s throughput, respectively. PCI-X 2.0 makes additional protocol revisions that are designed to help system reliability and add Error-correcting codes to the bus to avoid re-sends. To deal with one of the most common complaints of the PCI-X form factor, the 184-pin connector, 16-bit ports were developed to allow PCI-X to be used in devices with tight space constraints. Similar to PCI-Express, PtP functions were added to allow for devices on the bus to talk to each other without burdening the CPU or bus controller.

Despite the various theoretical advantages of PCI-X 2.0 and its backward compatibility with PCI-X and PCI devices, it has not been implemented on a large scale (as of 2008). This lack of implementation primarily is because hardware vendors have chosen to integrate PCI Express instead.

Confusion with PCI-Express

PCI-X is often confused by name with similar-sounding PCI Express, commonly abbreviated as PCI-E or PCIe, although the cards themselves are totally incompatible and look different. While they are both high-speed computer buses for internal peripherals, they differ in many ways. The first is that PCI-X is a 64-bit parallel interface that is backward compatible with 32-bit PCI devices. PCIe is a serial point-to-point connection with a different physical interface that was designed to supersede both PCI and PCI-X.

PCI-X and standard PCI buses may run on a PCIe bridge, similar to the way ISA buses ran on standard PCI buses in some computers. PCIe also matches PCI-X and even PCI-X 2.0 in maximum bandwidth. PCIe 1.0 x1 offers 250 MB/s in each direction, and up to 32 lanes (x32) is currently supported, giving a maximum of 8 GB/s in each direction.

PCI-X has technological and economical disadvantages compared to PCI Express. The 64-bit parallel interface requires difficult trace routing, because, as with all parallel interfaces, the signals from the bus must arrive simultaneously or within a very short window, and noise from adjacent slots may cause interference. The serial interface of PCIe suffers fewer such problems and therefore does not require such complex and expensive designs. PCI-X buses, like standard PCI, are half-duplex bidirectional, whereas PCIe buses are full-duplex bidirectional. PCI-X buses run only as fast as the slowest device, whereas PCIe devices are able to independently negotiate the bus speed. Also, PCI-X slots are longer than PCIe 1x through PCIe 16x, which makes it impossible to make short cards for PCI-X. PCI-X slots take quite a bit of space on motherboards, which can be a problem for ATX and smaller form factors. -Wikipedia