The TAP controller is a finite state machine that responds to changes at the TMS and TCK signals of the TAP and controls the sequence of operations of the circuitry defined by standard. It also controls the scanning of data into the various registers of the JTAG architecture. Two state transition paths for scanning the signal at TDI, one for shifting to the instruction register and one for shifting data into the active data register. The state diagram is shown in figure below. All state transitions of the TAP controller shall occur based on the value of TMS at the time of a rising edge of TCK. Actions of the test logic shall occur on either the rising or the falling edge of TCK in each controller state. The behavior of the TAP controller and other test logic in each of the controller states is briefly described as follows.

Fig. JTAG TAP controller states flow

Test-Logic-Reset : This state is entered on power-up of the device.

Run-Test-Idle : This state allows certain operations to occur depending on the current instruction.

Select-DR-Scan : This state is entered prior to performing a scan operation on a data register.

Select-IR-Scan : This state is entered prior to performing a scan operation on the instruction register.

Capture-DR : This state allows data register selected by the current instruction on the rising edge of TCK.

Shift-DR : This state shifts the data, in the currently selected register.

Exit1-DR : This state allows the option of passing on to the Pause-DR state.

Pause-DR : This wait state allows shifting of data to be temporarily halted.

Exit2-DR : This state allows the option of passing on to the Update-DR state.

Update-DR : This state causes data contained in the currently selected data register to be loaded into a latched parallel output.

Capture-IR : This state allows data to be loaded from parallel inputs into the instruction register.

Shift-IR : This shifts the values in the instruction register towards TDO.

Exit1-IR : This state allows the option of passing on to the Pause-IR state.

Pause-IR : This wait state that allows shifting of the instruction to be halted.

Exit2-IR : This state allows the option of passing on to the Update-IR state.

Update-IR : This state causes the values contained in the instruction register to be loaded into a latched parallel output on the falling edge of TCK after entering this state.