Technologist sketches IBM's silicon road map

HONOLULU  As chip makers find it increasingly difficult to wring higher performance from silicon while maintaining acceptable power consumption levels, IBM Corp. plans several major changes to its CMOS recipe over the next five years, said Bijan Davari, vice president of technology development at IBM Microelectronics.

Speaking prior to the start of the 2002 Symposium on VLSI Technology here, Davari said IBM plans to be aggressive about the introduction of strained silicon, and to build upon that foundation to later introduce a high-k gate dielectric and vertical dual-gate transistors.

With its internal server division and external ASIC customers hungry for the highest performance devices, IBM technologists have made advances in several key areas over the past decade, including utilization of copper interconnects, silicon-on-insulator (SOI), silicon germanium BiCMOS, and low-k dielectrics.

Not all of the company's initiatives have paid off. IBM invested billions of dollars in X-ray lithography before abandoning those efforts. But IBM has been right often enough for Davari to claim that competitors have "followed our road map to a T."

Davari said IBM plans to introduce strained silicon technology at the 65-nm technology node, which is expected to see its first introduction in 2005. Strained silicon takes advantage of the phenomenon that electrons have higher mobility when a thin layer of silicon is deposited on top of a thicker, graded layer of silicon germanium (SiGe). The larger crystalline lattice of SiGe exerts a strain on the thinner top silicon layer, stretching the silicon lattice slightly. IBM plans to create the graded SiGe layer, and the top active layer of silicon, on an SOI substrate.

Strained silicon will improve electron and hole mobility significantly, but adds complexity to CMOS processing. One challenge is avoiding damage to the top silicon layer, which is 400 to 500 Angstroms thick. Another is grading the SiGe layer with the right mix of germanium atoms.

"We have some advantages in SOI and silicon germanium, and so we are out in front when it comes to marrying those two," Davari said. "We have the fundamental material capabilities, we understand the deposition and thermal mixing requirements to form a very thin strained silicon layer on an SOI wafer. How to maintain the crystal integrity when you build strained silicon on SOI, that's going to be key."

When IBM researchers presented the company's strained silicon work at last year's VLSI Symposium, some predicted it would be used at some far distant point in IBM's road map, well after the shift to a high-k gate dielectric.

Not so, Davari told EE Times.

Strained silicon must be brought to manufacturing first, because the high-k insulators studied thus far create a drag on electron mobility. A shift to a high-k insulator without the prior introduction of strained silicon would result in a device with less performance than transistors that use silicon dioxide as the gate insulator.

For that reason, IBM plans to introduce strained silicon at the 65-nm node, though Davari voiced a small possibility that it would come later.

Major challenge

A major challenge with strained silicon is that while electron mobility in the n-FET is greatly improved in a strained silicon layer, to achieve a corresponding improvement in the hole mobility in the p-FET requires a much higher level of germanium in the graded SiGe layer.

Davari said that challenge can be met, and laid down what amounts to an ultimatum to companies pondering how to keep CMOS performance improvements on track while preventing current leakage through the increasingly thin SiO2 gate insulation layer.

"High-k is a very tough problem," he said. "People have started working on it, but not enough attention has been paid to it. Silicon dioxide is this amazing material, the interface with silicon is so good, it will take more time to develop alternatives. For high-k to be effective, it almost certainly needs some other gate material than the polysilicon electrode, otherwise the poly depletion will kill it. For the electrode function, we may need to go to dual metal gate electrodes at the same time we introduce a high-k gate.

"In my opinion, this road map strained silicon before, or at the same time, as a high-k gate dielectric must be followed. If you don't have SOI and strained silicon, if you don't have a high-k gate material to prevent leakage, then you can't get any benefits from shrinking" other than higher transistor densities. To get the current leakage benefits of a high-k material, "the new high-k must be enabled by SOI and strained silicon," he said.

Davari said the high-k insulator challenge is so thorny that it may even come later than the introduction of a vertical, dual-gate transistor structure  another means of improving current drive. The vertical dual-gate structures are difficult to fabricate, however, and have been seen as a radical departure from today's horizontally planar CMOS structures.

"The jury is out whether high-k or dual-gate structures will come first. Dual-gate structures may be easier to build than the problems associated with a high-k, but the benefits may be less than a high-k material if we can come with a truly high-k insulator that has good electrical properties and also reduces leakage," Davari said.

"These changes are inevitable, and we have to do them and solve the cost questions. This road map must be followed, and it is just a matter of time before all companies go down this path if they care about scaling. It is going to happen, because it follows the laws of physics," he said.