Module documentation for 0.7

clash-vhdl - VHDL backend for the CλaSH compiler

See the LICENSE file for license and copyright details

CλaSH - A functional hardware description language

CλaSH (pronounced ‘clash’) is a functional hardware description language that
borrows both its syntax and semantics from the functional programming language
Haskell. The CλaSH compiler transforms these high-level descriptions to
low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of CλaSH:

Strongly typed (like VHDL), yet with a very high degree of type inference,
enabling both safe and fast prototying using consise descriptions (like
Verilog).

Interactive REPL: load your designs in an interpreter and easily test all
your component without needing to setup a test bench.

Higher-order functions, with type inference, result in designs that are
fully parametric by default.

Synchronous sequential circuit design based on streams of values, called
Signals, lead to natural descriptions of feedback loops.

0.6.6 January 29th 2016

0.6.5 January 13th 2016

New features:
Support for Haskell's: Char, Int8, Int16, Int32, Int64, Word, Word8, Word16, Word32, Word64.
Int/Word/Integer bitwidth for generated VHDL is configurable using the -clash-intwidth=N flag, where N can be either 32 or 64.

0.6.4 November 17th 2015

Fixes bugs:
* Integer literals should only be capped to 32-bit when used in assignments.