tag: near-threshold computing

Everything related to power in chip design today is a big deal—and it’s just getting bigger.
Meeting the power budget is becoming harder at each new node, but it's also becoming difficult in a number of new application areas at existing nodes. That's a big problem because [getkc id="108" kc_name="power"] is now considered a competitive advantage in many markets. It's also one of the most... » read more

The emergence of the Internet of Things (IoT) has brought a lot of attention to the need for extremely low-power design, and this in turn has increased the pressure for voltage reduction. In the past, each new process node shrunk the feature size and lowered the nominal operating voltage. This resulted in a drop in power consumption.
However, the situation changed at about 90nm in two ways. ... » read more

While Moore's Law continues to drive feature size reduction and complexity, a whole separate part of the industry is growing up around vertical markets in the IoT. While these two worlds may be different in many respects, they share one thing in common—low power design is critical to success.
How engineering teams minimize power in each of these markets, and even within the same market, ca... » read more

Greek mythology and Roman history are replete with soothsayers, some of whom got it right and others wrong. Cassandra was cursed that her predictions wouldn’t be believed, even though she predicted the Trojan horse. Caesar’s soothsayer predicted the demise of Julius Caesar during the Ides of March, which Caesar himself was skeptical about, but indeed he was murdered before the Ides passed. ... » read more

Memory is becoming one of the starting points for SoC architectures, evolving from a basic checklist item that was almost always in the shadow of improving processor performance or lowering the overall power budget. In conjunction with that shift, chipmakers must now grapple with many more front-end decisions about placement, memory type and access prioritization.
There are plenty of rules ... » read more

The emphasis on lowering power in everything from wearable electronics to data centers is turning into a perfect storm for the semiconductor ecosystem. Existing methodologies need to be fixed, techniques need to be improved, and expectations need to be adjusted. And even then the problems won't go away.
In the past, most issues involving power—notably current leakage, physical effects such... » read more

As the price of shrinking features increases below 28nm, there has been a corresponding push to create new designs at established nodes using everything from near-threshold computing to back biasing and mostly accurate analog sensors.
The goals of power, performance and cost haven’t changed, but there is a growing realization among many chipmakers that the formula can be improved upon with... » read more

ARM fellow Rob Aitken talks about what is NTC, why it has taken so long to catch on, and the enormous energy savings possible using this technique at established process nodes.
[youtube vid=Ersdl81yTnM] » read more