Abstract:

Semiconductor structure formed on a substrate and process of forming the
semiconductor. The semiconductor includes a plurality of field effect
transistors having a first portion of field effect transistors (FETS) and
a second portion of field effect transistors. A first stress layer has a
first thickness and is configured to impart a first determined stress to
the first portion of the plurality of field effect transistors. A second
stress layer has a second thickness and is configured to impart a second
determined stress to the second portion of the plurality of field effect
transistors.

Claims:

1. A semiconductor circuit comprising a substrate;a plurality of field
effect transistors formed on the substrate, the plurality of field effect
transistors including a first portion of field effect transistors and a
second position of filed effect transistors;a first stress layer having a
first thickness and being configured to impart a first determined stress
to the first portion of the plurality of field effect transistors; anda
second stress layer having a second thickness and being configured to
impart a second determined stress to the second portion of the plurality
of field effect transistors.

2. The semiconductor circuit according to claim 1, wherein:the first
portion of the plurality of field effect transistors have spacings
between adjacent field effect transistors that fall within a first
defined spacing range; andthe second portion of the plurality of field
effect transistors have spacings between adjacent field effect
transistors that fall within a second defined spacing range.

3. The semiconductor circuit according to claim 2, wherein:the first
defined spacing range is less than the second defined spacing range;
andthe first thickness is less than the second thickness.

Description:

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001]The present application is a continuation of U.S. application Ser.
No. 11/244,291, filed on Oct. 6, 2005, which is a continuation of U.S.
application Ser. No. 10/701,526, filed Nov. 6, 2003, the disclosures of
which are expressly incorporated by reference herein in its entirety.

BACKGROUND OF INVENTION

[0002]1. Field of the Invention

[0003]The invention generally relates to a semiconductor device and method
of manufacture and, more particularly, to a complementary
metal-oxide-semiconductor (CMOS) device that includes an etch stop layer
with a selectively varying thickness.

[0006]Another approach for achieving performance enhancement involves
imparting local mechanical stresses. Electron mobility and, thus,
n-channel field effect transistor (nFET) performance may be improved by
imparting tensile stress either along (i.e., parallel to) the direction
of a current flow and/or orthogonal to the direction of current flow.
Additionally, hole mobility and, thus, p-channel field effect transistor
(PFET) performance, may be enhanced by imparting compressive stress
parallel to the direction of current flow and tensile stress
perpendicular to the direction of current flow.

[0007]Etch stop films may be applied to impart tensile and compressive
stresses. For example, a tensile stress may be imparted to an NFET
channel by applying a tensile etch stop film. A compressive stress may be
imparted to a pFET channel by applying a compressive etch stop film.
However, such an approach has drawbacks. In particular, the compressive
film degrades NFET performance, while the tensile film degrades pFET
performance.

[0008]Furthermore, although etch stop films may be configured to impart
significant stresses, relatively thick films are required as the stress
transferred is proportional to film thickness. Problematically, as film
thickness increases, voids are likely to form in the film. This is
especially true in dense structures, such as cache or SRAM cells, where
gates are very closely spaced, e.g., at a minimum pitch. During contact
etching, such voids may open and fill with contact metal. As the voids
run parallel to the gates, the voids filled with contact metal may cause
contact shorts, thereby preventing proper circuit functionality.

[0009]The invention is directed to overcoming one or more of the problems
as set forth above.

SUMMARY OF THE INVENTION

[0010]In a first aspect of the invention, a semiconductor structure is
provided. The structure includes a plurality of field effect transistors
and first and second stress layers deposited on portions of the field
effect transistors. The plurality of field effect transistors include a
first portion of field effect transistors and a second portion of field
effect transistors. A first stress layer has a first thickness and is
configured to impart a first determined stress to the first portion of
the plurality of field effect transistors. A second stress has a second
thickness and is configured to impart a second determined stress to the
second portion of the plurality of field effect transistors.

[0011]Furthermore, in an exemplary embodiment, areas of the semiconductor
that would not experience performance enhancement due to the stress
imparted by the first stress layer are devoid of the first stress layer.
Likewise, areas of the semiconductor that would not experience
performance enhancement due to the stress imparted by the second stress
layer are devoid of the second stress layer. The imparted stresses may be
compressive and/or tensile. Additionally, the first and second stress
layers may have the same or different thicknesses.

[0012]In another aspect of the invention a semiconductor structure formed
on a substrate includes a first plurality of n-channel field effect
transistors having a first range of spacings between adjacent n-channel
field effect transistors that fall within a first defined spacing range.
The structure also includes a second plurality of n-channel field effect
transistors having a second range of spacings between adjacent n-channel
field effect transistors that fall within a second defined spacing range.
Additionally, the structure includes a first plurality of p-channel field
effect transistors having a first range of spacings between adjacent
p-channel field effect transistors that fall within a first defined
spacing range. Furthermore, the structure includes a second plurality of
p-channel field effect transistors having a second range of spacings
between adjacent p-channel field effect transistors that fall within a
second defined spacing range.

[0013]A first tensile layer having a first tensile layer thickness and
being configured to impart a first determined tensile stress is applied
to the first plurality of n-channel field effect transistors. A second
tensile layer having a second tensile layer thickness and being
configured to impart a second determined tensile stress is applied to the
second plurality of n-channel field effect transistors. A first
compressive layer having a first compressive layer thickness and being
configured to impart a first determined compressive stress is applied to
the first plurality of p-channel field effect transistors. A second
compressive layer having a second compressive layer thickness and being
configured to impart a second determined compressive stress is applied to
the second plurality of p-channel field effect transistors.

[0014]In a further aspect of the invention, a process of forming a
semiconductor structure is provided. The process entails forming a
semiconductor substrate. Next, a plurality of field effect transistors
are formed on the semiconductor substrate. The plurality of field effect
transistors includes a first portion of field effect transistors and a
second portion of field effect transistors. Subsequently, a first stress
layer is deposited. The first stress layer has a first thickness and is
configured to impart a first determined stress to the first portion of
the plurality of field effect transistors. A second stress layer is also
deposited. The second stress layer has a second thickness and is
configured to impart a second determined stress to the second portion of
the plurality of field effect transistors.

[0015]Furthermore, in an exemplary implementation, portions of the first
stress layer may be removed from areas of the semiconductor that would
not experience performance enhancement due to the stress imparted by the
first stress layer. Likewise, portions of the second stress layer may be
removed from areas of the semiconductor that would not experience
performance enhancement due to the stress imparted by the second stress
layer. The imparted stresses may be compressive and/or tensile.
Additionally, the first and second stress layers may have the same or
different thicknesses.

[0018]FIG. 2 shows a plurality of FETs, including a dense group of (i.e.,
a group of closely spaced) nFETs, on a semiconductor device;

[0019]FIG. 3 shows a thin tensile stress layer applied to the plurality of
FETs from FIG. 2, including the dense group of nFETs;

[0020]FIG. 4 shows the thin tensile stress layer removed from all areas
except the dense group of nFETs;

[0021]FIG. 5 shows the thin tensile stress layer on a dense group of nFETs
and an isolated NFET, and a thick tensile layer on the isolated NFET;

[0022]FIG. 6 shows a plurality of FETs, including a dense group of (i.e.,
a group of closely spaced) pFETs, on a semiconductor device;

[0023]FIG. 7 shows a thin compressive stress layer applied to the
plurality of FETs from FIG. 5, including the dense group of pFETs;

[0024]FIG. 8 shows the thin compressive stress layer removed from all
areas except the dense group of pFETs;

[0025]FIG. 9 shows a plurality of FETs, including a group of distantly
spaced nFETs, on a semiconductor device;

[0026]FIG. 10 shows a thick tensile stress layer applied to the plurality
of FETs from FIG. 9, including the group of distantly spaced nFETs;

[0027]FIG. 11 shows the thick tensile stress layer removed from all areas
except the group of distantly spaced nFETs;

[0028]FIG. 12 shows a plurality of FETs, including a group of distantly
spaced pFETs, on a semiconductor device;

[0029]FIG. 13 shows a thick compressive stress layer applied to the
plurality of FETs from FIG. 12, including the group of distantly spaced
pFETs; and

[0030]FIG. 14 shows the thick compressive stress layer removed from all
areas except the group of distantly spaced pFETs.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

[0031]The invention employs selectively applied thin stressed films, such
as tensile films, thin compressive films, and thick tensile films, to
enhance electron and hole mobility in CMOS circuits. An exemplary process
in accordance with the invention entails steps of applying each film, and
patterning for selectively removing the applied film from areas that
would not experience performance benefit from the applied stressed film.

[0032]Referring now to FIG. 1, a substrate 100 having a plurality of FETS
(i.e., NFETS and/or PFETS) 105-125 is shown. The substrate 100 includes
areas of different densities of nFETS and pFETs, including areas of high
concentration or density 130 and areas of low concentration or density
140. Typically, similar devices are clustered; though the invention is
applicable to devices having nFETs interspersed with pFETs, and vice
versa.

[0033]The high density area 130 exhibits closely spaced FETs. In such an
area, the distance from gate to gate may, for example, be 130 nanometers
(nanometers). As used herein, a high density area refers to an area with
closely spaced FETs, even if there are only two FETs in the area. The low
density or isolated area 140 exhibits FETs with a relatively substantial
distance from gate to gate. In such an area, the distance from gate to
gate may, for example, be 200 nanometers or greater. The substrate 100,
including the FETs 105-125, may be fabricated in a conventional manner.
While FIGS. 1 through 14 illustrate principles of exemplary
implementations of the invention, they are not drawn to scale. Thus, the
dimensions, proportions and spacings of device elements may differ from
those depicted in the Figures.

[0034]The stress layer influences what is considered a dense or isolated
area. A dense area would not be able to accommodate a thick stress layer
without a substantial likelihood of void formation. The thicker the
layer, the more space it requires to avoid undesirable void formation.
Additionally, some stress layer materials and depositing parameters may
be more conducive to void formation than others. Conversely, an isolated
area is able to accommodate a thick stress layer without a substantial
likelihood of void formation. While layer thicknesses and distances
between FETs are provided herein for illustrative purposes, those skilled
in the art should appreciate that the invention is not limited to the
specifically provided thicknesses and distances.

[0035]Etch stop films (or layers) applied as stress layers in accordance
with the invention may include refractory insulating material or
materials with selective etch and physical properties. By way of example,
silicon nitride Si3N4 or SixNy, and/or silicon
oxynitride SixONy, may be used for stress films. These
materials may be grown or blanket deposited in a conventional manner,
such as by chemical vapor deposition (CVD), plasma enhanced CVD or
physical vapor deposition (PVD). Such films can be made with a well
controlled thickness. Illustratively, the thickness range may be between
50 to 300 nanometers for a thick film, and 20 to 50 nanometers for a thin
film. Etch stop films applied in accordance with the principles of the
invention act primarily as stress inducing layers.

[0036]Stress in applied films may be controlled in a conventional manner.
For example, to control the stress qualities of the film, the deposition
pressure and/or plasma power and/or other deposition process parameters
may be varied illustratively, without limiting the scope of the
invention, to achieve a tensile film exhibiting a tensile stress of
approximately 700 MPa, the following CVD parameters may be used: a
temperature of approximately 480° C., a pressure of approiximately
6.25 Torr, a spacing between the wafer and the electrode of 490 mils, a
flow of 300 sccm of 2% dilute SiH4 gas, 15 sccm NH3 gas and
1060 sccm N2 gas using RF power of 340 watts. Likewise, without
limiting the scope of the invention, to achieve a compressive film
exhibiting a compressive stress of approximately -1400 MPa, the following
CVD parameters may be used: a temperature of approximately 480°
C., a pressure of approximately 5.75 Torr, a spacing between the wafer
and the electrode of 395 mils, a flow of 3000 sccm of 2% dilute SiH4
gas, 15 sccm NH3 gas and 1060 sccm N2 gas using RF power of 900
watts. Adjusting the deposition process parameters allows control over
properties of the deposited material, including physical properties such
as stress properties.

[0037]In accordance with the invention, FETs of different spacings (i.e.,
densities or concentrations) may have stressed films of different
thicknesses. In an exemplary implementation, closely spaced nFETs may
have a thin tensile film to enhance electron mobility and, thus, NFET
performance, while avoiding formation of undesirable voids. Likewise,
closely spaced pFETs may have a thin compressive film to enhance hole
mobility and, thus, pFET performance, again while avoiding formation of
undesirable voids. Similarly, pFETs closely spaced to nFETs would also
have thin stressed films. Furthermore, nFETs having a minimum spacing
large enough to avoid void formation when a thick film is applied, may
have a thick tensile film, while similarly spaced pFETs may have a thick
compressive film. Of course, nFETs and pFETs may each be further divided
into more than two categories, with each category exhibiting a range of
distances between FETs, and each category capable of accommodating a
stressed film layer of a determined thickness without substantial risk of
undesirable void formation. A stressed etch stop film of a determined
thickness or range of thicknesses will apply to each category.

[0038]In one implementation, nFETs and pFETs may each be divided into two
categories, i.e., a dense category of closely spaced FETs 130 and an
isolated category of distantly spaced FETs 140, as shown in FIG. 1.
Referring now to FIG. 2, a dense group of (i.e., a group of closely
spaced) nFETs 205-220 and an isolated FET 225 are shown. In this
implementation, the dense group is spaced at about 130 nanometers or
less, while the isolated FET 225 may exhibit a spacing of greater than
130 nanometers.

[0039]To impart a tensile stress to the nFETs 205-220, particularly the
channel region of the nFETs 205-220, in accordance with the principles of
the invention, a tensile stress layer 305 is applied over the entire
surface of the semiconductor device, as shown in FIG. 3 and discussed
more fully below. Because the nFETs 205-220 are closely spaced, a thin
tensile layer is applied. The applied tensile layer 305 is then removed,
such as by masking and etching, from areas of the device that do not
benefit from the imparted tensile stress as well as from areas that may
benefit from an alternative stress layer, such as the isolated FET 225.

[0040]A thin oxide (e.g., SiO2) liner (not shown) may be applied, to
serve as an etch stop, before the tensile stress layer 305 is applied.
The oxide liner may be approximately 1 to 10 nanometers in thickness. The
oxide liner guards against unintended etching of the structure and
elements beneath the applied liner and stress layers. Alternatively, a
timed etch, such as a timed dry etch, may be used to remove only the
applied tensile layer from those areas of the substrate 100 that do not
benefit from the imparted tensile stress.

[0041]Referring still to FIG. 3, the thin stressed film 305 may be
comprised of, for example, Si3N4. The thin stressed film may
also be, for example, SixNy, and/or silicon oxynitride
SixONy. The film 305 may be blanket deposited over the entire
surface of the substrate 100 in a conventional manner, such as by CVD,
plasma enhanced CVD or PVD. In one implementation, the thin stressed film
may have a thickness between 20 to 50 nanometers. The spacing of the
closely packed nFETs is about 130 nanometers or less. The film 305 may
exhibit a tensile stress of approximately 600 to 1500 MPa (Mega-pascals).
The film 305 is thus configured to impart a tensile stress to the
underlying areas.

[0042]Next, the thin tensile film 305 is masked on locations where the
dense nFETs 205-220 are present, and possibly where isolated nFETs are
present, to allow removal from all other areas (e.g., FET 225) of the
substrate 100. For example, the desired pattern of nFETs may be
transferred to an optical mask, as is well known in the art. The surface
of the substrate 100 may then be covered with photoresist. The resist may
then be exposed through the mask to radiation that changes its structure,
polymerizing (i.e., cross linking) determined areas. Unpolymerzied
regions may then be removed using a solvent, leaving the polymerized
portions in tact. Subsequent process steps (e.g., etching) will affect
only the areas without polymerized photoresist. Thus, the thin tensile
film may be removed by etching (e.g., by reactive ion etching using the
patterned photoresist as a mask) from all areas (e.g., FET 225) except
where the patterned nFETs (e.g., nFETs 205-220) are present, as shown in
FIG. 4. Subsequently, any remaining polymerized photoresist may be
removed using a wet process, such as sulfuric acid, or a dry process,
such as O2 plasma.

[0043]As discussed above, the thin tensile layer 305 may be left on
isolated NFETS as shown in FIG. 5. Additional thin (e.g., 20 to 50
nanometers) tensile layers and/or a thick (e.g., 50 to 500 nanometers)
tensile layer 510 may subsequently be added to the isolated nFETs, such
as in a manner described more fully below, to impart greater tensile
stress and thereby achieve further enhancement of electron mobility.
Alternatively, the thin tensile layer 305 may be removed from the
isolated NFETS; in which case, the isolated nFETs may subsequently
receive a thick (e.g., 50 to 500 nanometers) tensile layer to enhance
electron mobility, as discussed more fully below. Similarly, thin and
thick compressive stress layers may be applied to isolated pFETs, as
discussed more fully below.

[0044]Subsequently, another oxide liner layer (not shown) may be deposited
over the top surface of the entire device to serve as an etch stop,
before the next stress layer is applied, as discussed below. The oxide
liner guards against unintended etching of elements beneath it, including
thin tensile stress layer 305. Alternatively, a timed etch, such as a
timed dry etch, may be used to remove only the next layer from those
areas of the substrate 100 that do not benefit from the imparted stress.

[0045]Referring now to FIG. 6, a dense group of (i.e., a group of closely
spaced) pFETs 605-620 and an isolated FET 625 are shown. In one
implementation, the dense group of pFETs 605-620 is spaced at about 130
nanometers or less. To impart a compressive stress to the dense group of
pFETs 605-620, particularly the channel region of the pFETs 605-620, in
accordance with the principles of the invention, a thin compressive
stress layer 705 is applied to the surface of the entire device, as shown
in FIG. 7.

[0046]The thin compressive layer 705 may be comprised of, for example,
Si3N4. Alternatively, the thin compressive film may be
SixNy, and/or silicon oxynitride SixONy. The film 705
may be blanket deposited over the entire surface of the substrate 100 in
a conventional manner, such as by CVD, plasma enhanced CVD or PVD. In one
implementation, the thin compressive film may have a thickness between 20
to 50 nanometers. The thin compressive film 705 may exhibit a compressive
stress of approximately -600 to -1500 MPa (Mega-pascals). The film 705 is
thus configured to impart a compressive stress to underlying areas.

[0047]Next, the thin compressive film 705 may be masked on locations where
the dense pFETs 605-620 are present, and possibly where isolated pFETs
are present, to allow removal from all other areas of the substrate 100.
For example, the desired pattern of pFETs may be transferred to an
optical mask in a conventional manner. The surface of the substrate 100
may then be covered with photoresist. The resist may then be exposed
through the mask to radiation that changes its structure, polymerizing
(i.e., cross linking) determined areas. Unpolymerzied regions may then be
removed using a solvent, leaving the polymerized portions in tact.
Subsequent process steps (e.g., etching) will affect only the areas
without polymerized photoresist. Thus, the thin compressive film 705 may
be removed by etching (e.g., by reactive ion etching using the patterned
photoresist as a mask) from all areas (e.g., FET 625) except where the
patterned pFETs (e.g., nFETs 605-620) are present, as shown in FIG. 8.
Subsequently, the polymerized photoresist may be removed using a wet
process, such as sulfuric acid, or a dry process, such as O2 plasma.

[0048]As discussed above, the thin compressive layer 705 may be left on
isolated pFETS. Additional thin (e.g., 20 to 50 nanometers) compressive
layers and/or a thick (e.g., 50 to 500 nanometers) compressive layer may
subsequently be added to isolated pFETs in a manner described above to
impart greater compressive stress (e.g., -600 to -1500 MPa) and thereby
achieve further enhancement of hole mobility. Alternatively, the thin
compressive layer 705 may be removed from the isolated pFETS 625 as shown
in FIG. 8; in which case, the isolated pFETs 625 may subsequently receive
a thick compressive layer to enhance hole mobility, as discussed more
fully below.

[0049]Subsequently, another oxide liner layer (not shown) may be deposited
over the top surface of the entire device to serve as an etch stop,
before the next stress layer is applied, as discussed below. The oxide
liner thus guards against unintended etching of elements beneath it,
including thin compressive stress layer 705. Alternatively, a timed etch,
such as a timed dry etch, may be used to remove only the next layer from
those areas of the substrate 100 that do not benefit from the stress
imparted by the next layer.

[0050]Referring now to FIG. 9, a sparsely populated group of (i.e., a
group of distantly spaced) nFETs 915, 920 and a dense group of FETs 905,
910 are shown. The sparsely populated group of nFETs is spaced at about
130 nanometers or greater. To impart a tensile stress to the nFETs 915,
920, particularly the channel region of the nFETs 915, 920, in accordance
with the principles of the invention, a tensile stress layer 1005 is
applied to the surface of the entire substrate 100, as shown in FIG. 10.
Because the nFETs 915, 920 are separated by a relatively substantial
distance, a thick stress layer 1005 may be applied without substantial
risk of void formation. Those skilled in the art will appreciate that,
depending upon the order in which stress layers are added, and depending
upon the type of FETs, FETs 905 and 910 may have stress layer (not shown
in FIG. 10) beneath layer 1005. Alternatively, a stress layer suitable
for FETs 905 and 910 may be added after stress layer 1005 is added.

[0051]The thick tensile film 1005 may be comprised of, for example,
Si3N4. The thick tensile film may also be, for example,
SixNy, and/or silicon oxynitride SixONy. The film
1005 may be blanket deposited over the entire surface of the substrate
100 in a conventional manner, such as by CVD, plasma enhanced CVD or PVD.
In one implementation, the thick tensile film may have a thickness
between 50 to 300 nanometers. The thick tensile film 1005 may exhibit a
tensile stress of approximately 600 to 1500 MPa (Mega-pascals). The film
1005 is thus configured to impart a tensile stress to underlying areas.

[0052]Next, the thick tensile film 1005 is masked on locations where the
isolated nFETs 915, 920 are present, to allow removal from all other
areas of the substrate 100. For example, the desired pattern of nFETs
915, 920 may be transferred to an optical mask in a conventional manner.
The surface of the substrate 100 may then be covered with photoresist.
The resist may then be exposed through the mask to radiation that changes
its structure, polymerizing (i.e., cross linking) determined areas.
Unpolymerized regions may then be removed using a solvent, leaving the
polymerized portions in tact. Subsequent process steps (e.g., etching)
will affect only the areas without polymerized photoresist. Thus, the
thick tensile film 1005 may be removed by etching (e.g., by reactive ion
etching using the patterned photoresist as a mask) from all areas (e.g.,
905, 910) except where the patterned nFETs 915, 920 are present, as shown
in FIG. 11. Subsequently, the polymerized photoresist may be removed
using a wet process, such as sulfuric acid, or a dry process, such as
O2 plasma.

[0053]Subsequently, another oxide liner layer (not shown) may be deposited
over the top surface of the entire device to serve as an etch stop,
before the next stress layer is applied, as discussed below. The oxide
liner guards against unintended etching of elements beneath it, including
thick tensile stress layer 1005. Alternatively, a timed etch, such as a
timed dry etch, may be used to remove only the next layer from those
areas of the substrate 100 that do not benefit from the stress imparted
by the next layer.

[0054]Referring now to FIG. 12, a sparsely populated group of (i.e., a
group of distantly spaced) pFETs 1215, 1220 and a dense group of pFETs
1205, 1210 are shown. The distantly spaced pFETs may have spacings of
greater than 130 nanometers, while the closely spaced FETs 1205, 1210 may
have spacings of less than 130 nanometers. To impart a compressive stress
to the pFETs 1215, 1220, particularly the channel region of the pFETs
1215, 1220, in accordance with the principles of the invention, a
compressive stress layer 1305 is applied to the surface of the entire
substrate 100, as shown in FIG. 13. Because the pFETs 1215, 1220 are
separated by a relatively substantial distance, a thick stress layer 1305
of about 50 to 500 nanometers in thickness may be applied without
substantial risk of void formation.

[0055]The thick compressive film 1305 may be comprised of, for example,
Si3N4. The thick compressive film may also be, for example,
SixNy, and/or silicon oxynitride SixONy. The film
1305 may be blanket deposited over the entire surface of the substrate
100 in a conventional manner, such as by CVD, plasma enhanced CVD or PVD.
In one implementation, the thick compressive film may have a thickness
between 50 to 300 nanometers. The thick compressive film 1305 may exhibit
a compressive stress of approximately -600 to -1500 MPa (Mega-pascals).
The film 1305 is thus configured to impart a compressive stress to
underlying areas.

[0056]Next, the thick compressive film 1305 is masked on locations where
the isolated pFETs 1215, 1220 are present, to allow removal from all
other areas (e.g., 1205, 1210) of the substrate 100. For example, the
desired pattern of pFETs 1215, 1220 may be transferred to an optical mask
in a conventional manner. The surface of the substrate 100 may then be
covered with photoresist. The resist may then be exposed through the mask
to radiation that changes its structure, polymerizing (i.e., cross
linking) determined areas. Unpolymerized regions may then be removed
using a solvent, leaving the polymerized portions in tact. Subsequent
process steps (e.g., etching) will affect only the areas without
polymerized photoresist. Thus, the thick compressive film 1305 may be
removed by etching from all areas except where the patterned pFETs 1215,
1220 are present, as shown in FIG. 14. Subsequently, the polymerized
photoresist may be removed using a wet process, such as sulfuric acid, or
a dry process, such as O2 plasma.

[0057]The order of applying the various stress layers is not critical.
Compressive layers may be applied before or after tensile layers. Thick
layers may be applied before or after thin layers.

[0058]In an alternative implementation, thick layers may be reduced via
timed etching to produce thin stress layers over a densely populated
areas. Thus, for example, a thick compressive layer may be applied for
all pFETs. The compressive layer may then be removed from all areas that
do not benefit from compressive stress such as, for example, areas
populated with nFETs. Such removal may be carried out in the manner
described above. In areas densely populated with pFETs, the compressive
layer may be reduced in thickness through a wet or dry timed etch. The
reduced thickness may be, for example, 20 to 50 nanometers. Isolated pFET
areas may be protected with a photoresist or etch stop to avoid undesired
removal and thinning of the compressive layer.

[0059]In another alternative implementation, thin compressive layers may
be applied and built-up in successive layers to achieve desired
thicknesses. Thus, for example, a thin tensile layer of approximately 20
to 50 nanometers may be applied for all nFETs. Subsequently, one or more
additional thin tensile layers, each of approximately 20 to 50
nanometers, may be applied for isolated nFETs. The additional thin
tensile layers may be removed from all areas that would be susceptible to
void formation or that do not benefit from tensile stress, such as areas
populated by pFETs. Such removal may be carried out in the manner
described above.

[0060]While the invention has been described in terms of exemplary
embodiments, those skilled in the art will recognize that the invention
can be practiced with modifications and in the spirit and scope of the
appended claims.