SDMA transfer between EIM and memory problem

We have a board using IMX6UL. It is needed to transfer data between CPU and FPGA via EIM interface, and with DMA mode. The kernel version we used is 3.14.38. Because the weim.DATA pin is used for lcdif.data, I configure the EIM interface to multiplexed mode(MUM=1), 16-bit datawidth(DSZ=001), and synchronous read/write(SRD=1, SWR=1), BCLK divide EIM clock by 1(BCD=1) . The EIM register is configured as follow: EIM_CSnGCR1：0x7111019F EIM_CSnGCR2：0x00000808 EIM_CSnRCR1：0x03000000 EIM_CSnRCR2：0x00000000 EIM_CSnWCR1：0x01012480 EIM_CSnWCR2：0x00000000 EIM_WCR：0x00000028

I modified the test module (mxc_sdma_memcopy_test) which get from community.(See attach) Now I can capture singnal on EIM interface from FPGA. And the timing is basically my expected. Now I have two problem: 1、There is a interval every 32 bytes data when transfer data between memory and EIM with SDMA. No matter I configure the burst length to 4/8/16/32 words, it is a interval erery 32-byte transfer. For my configure， 32-byte is 16 words（DSZ=001， 1 word is 2 byte），so when I configure the burst length to 32 words，one burst read or write is also only 16 words. What is the reason of this interval? How can I eliminate or shorten this interval? 2、The timing of EIM interface when transfer from EIM to memory with SDMA is as my expected， but when I check the data in rbuf after transfer , the read data is error: some data is read twice and some data is lost. As follow is the timing I capture at FPGA:

The expected read data is:

dst data_0 : 00070006

dst data_1 : 00090008

dst data_2 : 000b000a

dst data_3 : 000d000c

dst data_4 : 00150014

dst data_5 : 00170016

dst data_6 : 00190018

dst data_7 : 001b001a

But the print result is:

dst data_0 : 00070006

dst data_1 : 00080007

dst data_2 : 00090008

dst data_3 : 000a0009

dst data_4 : 000c000c

dst data_5 : 000d000d

dst data_6 : 0000000e

dst data_7 : 000f0000

The second burst transfer data is almost lost. Is there something wrong with my configure for EIM? Or there is something I

I will tell you my view on this. Most likely it will not help you to improve the performance, but at least you will understand where the limitations are coming from.

The static memory interface IP block from ARM is intended to work as an interface to NOR flash memory or to SRAM. The access of this memory is done through a memory controller and through bridges which synchronize the two worlds to each other. To optimize the read access, the memory controller performs burst reads and stores the values in buffers. In case you read one byte from the ARM side, you will get it. But when reading this byte, the memory controller in fact reads more ( = the burst). And if you now read with the ARM from subsequent addresses, the memory controller can just take it from the buffer. Let's call it a very simple small cache.

For an SRAM or NOR flash these additional read cycles have no meaning, you can only profit from it. For an FPGA interface this means that you need to design it in such a way that additional reads have no effect, neither for the FPGA (auto increment for example) nor for the result you may get when you read two subsequent address locations on the FPGA..

I can't provide you with any timing behavior, burst length etc, but maybe you find some information on the ARM website when you go to these respective IP blocks.

I have solved the question 2 above, after I set the EIM_clk to 66MHz, other clk frequence is not ok. Then wen can transfer data between IMX6UL and FPGA. Finally, the EIM interface is configured multiplexed mode(MUM=1), 16-bit datawidth(DSZ=001), synchronous read and write, we used the BCLK for FPGA to capture the data, the burst length is still 8 words(16 byte). Burst read is monitored WAIT signal to start, burst write is fix latency So, the EIM register is finally configured as follow: EIM_CSnGCR1：0x0111019F EIM_CSnGCR2：0x00001010 EIM_CSnRCR1：0x02000000 EIM_CSnRCR2：0x00000000 EIM_CSnWCR1：0x01008280 EIM_CSnWCR2：0x00000000

The question 1 above is still exist.

Recently we found another data error promble while reading some address. For example, we first write 128 byte increasing num to the address begin from 0x21d00, then read back, there will be error data every 8 words(16 byte),it's a burst length. The following is the contrast data printed by the software. The value after "error" is the word number, the value after "w=" is the written data, and the value after "r=" is the readout data.

From the above error, in the 8 error words, the last 7 data error is like that be delay one clk cycle. And only some address segment have such read error.

Follow is the timing wave captured at FPGA.

On the data_from_fpga bus, the data in the blue box is the 8 words expected to be read one burst read. The timing wave is normal, the bus is not be delay and there's no a "0807" word before the "0008" words.The words "0807" can be seen from wr_data bus(wr_data is EIM_AD[15:0] input to FPGA and latch). But it appears on the bus 2 clk cycle before the word "0008", I can't understand why the word is sampled by the burst read.