Responsible for entering, layout, routing, and simulation of two Fairchild ECL gate array designs used in an internal research and development project to design a high speed digital modem to transmit data over fiber optic cables at a 225MHz rate.

Wrote a software package to simulate the operation of an internally developed array processor. The simulator was written in C on a VAX.

Image processing software (edge detection).

ACE - Automated testing hardware

CAE equipment operation, and a staff member assisting in operations of the companies' VAX computers.