Flash Annealing to Enable Formation of Ultra-Shallow Junctions and Its Integration with High-k/Metal-Gate MOSFETs

The formation of ultra-shallow junctions (USJs) with sub-15 nm depth and sheet resistance below 1000 ohm/sq. is a critical front-end processing challenge for sub-45 nm CMOS technology generations. Flash annealing and laser annealing are two candidate processes to replace conventional spike annealing, because they provide for higher dopant activation (peak temperature in the range 1300°C - 1400°C) and minimal dopant diffusion (annealing time in the range ~ms down to ns). However, very little has been reported on the effects of ms annealing on the performance and reliability of MOSFETs with metal-gate/high-k stacks.

P+ USJ studies were first done on blanket wafers with various combinations of low-energy boron implants, pre-amorphization implants, co-implants, and post-implant annealing conditions. Figure 1 summarizes the experimental results, which shows that spike annealing results in junctions that are too deep for sub-45 nm CMOS, even with co-implantation, due to transient enhanced diffusion. On the other hand, it is possible to achieve Xj in the range ~12-15 nm with Rs ~1 k ohm/sq. via flash annealing, which is adequate for 32 nm technology.