1. NAND FLIP-FLOP
The problem with NAND FLIP-FLOP is, you just cannot let it take any state. In order to start a NAND
FLIP-FLOP, you need to
set HIGH both the SET and the RESET pins. The principle is better exemplified if you replace the NAND
gate with
its equivalent, two OR gates having negated inputs.

The outputs of a NAND Flip-Flop are Q and Q and they complement each other.

NAND GATES
FLIP-FLOP

Schematic

Timing Diagram

Truth Table

Description

SET

RESET

Q

Q

1

1

0

1

0

1

1

0

1

0

0

1

0

0

0

1

Fig 1: NAND
FLIP-FLOP

2. NOR FLIP-FLOP
NOR Flip-Flop is more "user friendly", meaning, you can start it with both
the SET and RESET pins
being LOW.

NOR FLIP-FLOP

Schematic

Timing Diagram

Truth Table

Description

SET

RESET

Q

Q

0

0

0

1

1

0

1

0

0

1

0

1

0

0

1

0

Fig 2: NOR gates Flip-Flop

3. SR FLIP-FLOPS
SR Flip-Flop works similar to the NOR Gate Flip-Flop, only it is more complex. First, let's take a look at
the SR
Flip-Flop truth table.

SR FLIP-FLOP

Schematic

Timing Diagram

Truth Table

Description

#

SET

RESET

Q

Q

Allowed

1

0

0

0

1

yes

2

0

0

1

0

yes

3

0

1

0

1

yes

4

0

1

1

0

unstable

5

1

0

0

1

yes

6

1

0

1

0

yes

7

1

1

0

0

no

8

1

1

0

0

no

Fig 3: SR Flip-Flop

Note positions #7 and #8 in the truth table above: both of them are forbidden, because the outputs
do not complement each other. In addition position 8 is unstable,
therefore Q will change its
state from 0 to 1 and backwards continuously.

State #4 it is also unstable; in this case Q may be 0, although it shouldn't--in the
Truth Table Q is marked as 1.

The point to note is, SR Flip-Flops require a certain sequence of operation, and they need to be protected against
accidental situations as are #4, #7, and #8.

4. J-K FLIP-FLOPS
J-K Flip-Flop has a few notable advantages over the SR one. There are no forbidden or indeterminate states, and it
complements perfectly well. In addition, J-K Flip-Flops are used in Master-Slave constructions--this topic is explained
further in this page.

J-K FLIP-FLOP

Schematic

Timing Diagram

Truth Table

Description

#

SET

RESET

Q

Q

Allowed

1

0

0

0

1

yes

2

0

0

1

0

yes

3

0

1

0

1

yes

4

0

1

1

0

yes

5

1

0

0

1

yes

6

1

0

1

0

yes

7

1

1

0

1

yes

8

1

1

1

0

yes

Fig 4: J-K Flip-Flop

The outputs change their state when: 1. the input conditions are met, and
2. on the next falling edge of the clock

5. D FLIP-FLOPS
Undeniably, "D" Flip-Flop it is the easiest one to work with. The name
"D" comes from
"Data". This Flip-Flop is
perfectly stable, and very easy to control. Fact is, D Flip-Flop is just the best!

D FLIP-FLOP

Schematic

Timing Diagram

Truth Table

Description

D

Q

Q

0

0

1

1

1

0

Fig 5: D Flip-Flop
Q takes the value of D on the next falling clock edge

6. T FLIP-FLOPS
Some applications require that we change Q on each input toggle, without any clock, therefore we can use
"T"
Flip-Flops for that. However, there are T Flip-Flops built with a clock, and in that case the T Flip-Flop behaves
exactly like the D one. Particular to the T
Flip-Flop is, it triggers the outputs only when T changes states from
0 to 1.