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IDF Like a psychiatric patient experiencing a breakthrough, Intel has opened up in a big way, allowing third parties to plug into its processor architectures on two new fronts. Most immediately, Xilinx and Altera will start crafting FPGAs (field programmable gate arrays) that connect to the front side bus on Intel's server chips. Later, more partners will be able to provide a performance boost for Intel systems via an extension to PCI Express.

As we predicted, Intel used its IDF stage to disclose the new openness policy. The company has been forced to respond to the partner interest AMD has garnered around Hypertransport and the press AMD received for its more recent move to license specifications for its Opteron socket. In short, AMD has been able to tempt partners into developing co-processors that can speed specific tasks to go along with its server chips.

The server industry has particularly latched onto the idea of combining FPGAs tuned to crank through floating point operations with standard processors. Companies such as XtremeData and DRC have teamed with the likes of Xilinx and Altera to make FPGAs today that fit right into Opteron processor sockets. That means that a customer can mix and match the FPGAs and Opteron chips on a multi-socket board.

While these efforts have been underway for a couple years, they've yet to result in volume products. DRC is still testing its FPGAs for older Opteron systems, for example, and XtremeData plans to release an FPGA for Socket F Opteron boards in the next six months.

Intel is even further behind, although Intel server chief Pat Gelsinger said today that the company has been working on FPGA projects "in the labs for several years." It's now up to Xilinx, Altera and likely other partners to begin the march toward shipping usable products.

It's somewhat surprising that Intel opened up its front side bus to these folks. It will likely take one to two years to see viable product. By that time, Intel should be nearing the release of chips based on its CSI or Common System Interconnect technology, which will require the partners to rework their products for a new interface.

The Register, however, has learned that Intel is already talking to some of the smaller companies working on accelerators about plugging into CSI and offering them a chance to play outside of the Opteron-only realm.

"There are a number of partners around CSI which we will talk about when we talk about CSI next year," Gelsinger said.

Beyond the FPGA action, Intel also started pushing something code-named Geneseo, which is the extension to PCI Express.

The company lured the likes of IBM's CTO Tom Bradicich and Sun co-founder Andy Bechtolsheim - gasp - to IDF to talk up the new effort. A healthy list of other vendors, including Dell, ClearSpeed, Broadcom, Xilinx, XtremeData, Cisco and Novell, have also jumped behind the project.

At IDF, Bradicich described Geneseo as an "open standard for attaching accelerators and co-processors to server platforms." Once again, companies will look to build add-on components that speed up things such as mathematical calculations, XML, encryption and visualization.

The Geneseo backers hope to push the specification through the PCI Special Interest Group at a quick clip, although Bradicich admitted that some companies will "hedge the spec" and release product before final ratification.

"An FPGA will almost certainly be the first major product released for this," added Bechtolsheim.

The Sun executive described Geneseo to us as a relatively simple but necessary addition to PCI Express that will help extend the technology for years to come, while opening it up at the same time to new accelerator products.

Sun has declined to release Opteron-based servers with competing HTX slots thus far, while IBM has shipped such boxes, and HP is expected to do so. AMD has tried and succeeded to some extent to cultivate interest around HTX, which lets partners tap into its Hypertransport connections. Bechtolsheim, however, sees more volume and interest with PCI Express.

"Right now, cards that sit on PCI Express do so at a distance with a logical separation between the processor and what happens on the card," said Illuminata analyst Jonathan Eunice. "This tends to introduce some latency issues and a master-slave type of relationship.

"With Geneseo, they seem to be trying to introduce some of the functions that you would like to see more tightly coupled and to create a tighter link between the system buses and improve signaling."

Companies will be working to refine the Geneseo specification over the next year with the hopes of releasing product using it the year after that, Gelsinger said.

Even beyond all of this openness, Intel announced that it has already started revealing instruction set extensions for its 45nm products to partners. Intel has released a host of information about the instruction set push here.

While Intel's moves are to be applauded, the chip maker once again finds itself following AMD on the marketing front. Intel's focus on PCI Express and pure muscle could help it win this openness battle against AMD in the long-run. That said, AMD has framed the discussion around both accelerators and opening up it sockets. Intel once owned similar conversations. ®