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Ken Brock is the Product Marketing Manager for DesignWare Logic Libraries at Synopsys. Ken shared with us here his view of the trends he sees for the future of semiconductor IP.

What Does the Future Hold for Semiconductor IP?

The marketplace for semiconductor IP (SIP) continues to grow at double digit rates. According to Gartner Dataquest, the number of third-party semiconductor design IP blocks in an average chip design will double from the current level and the SIP market will reach $2.3B in 2014. IBS and Semico believe the SIP market will be greater than $3 billion in 2014.

We see six major trends in IP:

Convergence: The increased demand for “Smart” consumer electronics is driving more features and functionality into a single device such as the latest craze in tablets shown at this year’s Consumer Electronics Show (CES). This trend is causing significant changes in SoC designs in areas such as power and performance requirements that drive technology node migrations, and in increased clock frequencies to keep up with bandwidth needs.

Core versus Context: Does this function differentiate the SoC? Interfaces like PCI Express® and USB have to work but they don’t generally differentiate the SoC. As an IP vendor, we see many different applications spaces for our IP and we have to ensure that IP works over a broad range of configurations and products.

Fab-outsourcing: More outsourcing of manufacturing means more opportunity for customers to use off-the-shelf IP to meet their design requirements, and more demand for IP vendors to create high-quality IP on the most advanced process nodes.

Power, Performance, Area: As many semiconductor designs compete for the key sockets, having the fastest performance, lowest power and smallest area is often a key differentiator of the design with respect to processor performance, battery life, packaging cost and silicon cost. Choices of foundation IP (memory and logic) providers make a big difference between winners and also-rans.

Consumer-driven schedules: Shorter time-to-market and more features means that designers need to de-risk schedules by using high-quality IP solutions that have been proven time and time again in the market place.

Expense control: It is often less expensive for companies to buy third-party IP than to develop it themselves. This is particularly true in advanced nodes where the complexity of IP development increases rapidly with increasing data rates, restricted design rules and increasing variability. As an example, our estimate is that a 28nm standard cell and memory IP platform is at least five to 10 times as complex to design and verify as compared to a similar platform at 40nm.

With these trends as the backdrop, we see significant shifts in the SIP market as it continues to evolve during the next five years:

Most SoCs will have about 70 to 80 percent of their functionality in reused IP (internal and/or 3rd party). The majority of these IP blocks will be memories with thousands of instances per chip all connected with a variety of standard cell configurations. Optimized standard cells and memories can significantly impact the performance, power and area of a SoC.

Individual IP products will yield to more complex IP subsystems. These subsystems will include application-specific blocks and software. IP integration services will become increasingly important to validate the IP in the system context.

Multi-core designs will drive increasingly complex architectures. A virtual prototype of the IP and the larger SoC will enable earlier and more efficient development of application software and middleware.

This is a pivotal time for the semiconductor IP industry as companies strive to develop the best solutions to help designers accelerate their time from concept to implementation. These solutions generate value throughout the design chain by accelerating hardware/software integration and systems validation, allowing efficient SoC architecture exploration and optimization, creating and optimizing functional blocks, and using high-quality semiconductor IP. Designers are turning to trusted third-party SIP solutions to help integrate advanced functionality with the least amount of risk. Winners will choose wisely.

(EDA blogger Dan Nenni talks with Liz Massingill about how he approaches his blogging. First of two parts.)

Liz: Welcome, Dan. Thanks for coming down to chat with me today. I’d like to start by asking….Why do you blog?

Dan: I started my Social Media experience on LinkedIn a few years ago and blogging was the natural next step. I also use Twitter. Right now the three are integrated, with LinkedIn and Twitter being the delivery systems for my blog. Since I own my blog domain (http://danielnenni.com/) I get to see search terms, views, what is popular and what is not, where people come from and what links they click on. If they come from LinkedIn I get to see what they have done professionally. You are a LinkedIn fan I believe?

Liz: Yes.

Dan: A LinkedIn profile is a great source of information and hopefully it is up to date since it is transparent and seen by all. I’m also a member of LinkedIn groups for semiconductor design enablement. Once you join a group you can profile other members and see who your audience really is.

Liz: What topics interest your readers most and least?

Dan: Semiconductor topics are interesting, EDA topics are not. Financial/Economic topics are interesting, Social Media is not. Semiconductor yield is a VERY interesting topic, my blogs on TSMC 40nm yield get lots of views. Blogs on Global foundries are also popular, my TSMC vs Global Foundries is the most viewed blog to date. My blog on ICCAD was not so popular and got very few clicks. The most popular EDA blog I have done is EDA is DEAD, probably because of the word “dead.” Dead things get clicks.

What I have learned blogging directly correlates to my professional experience: Foundries are the center of the semiconductor universe and will continue to gain strength in driving EDA, IP, and Design Services. The best example is the TSMC Open Innovation Platform forum where TSMC clearly spelled out the future of EDA.

Liz: Who is your audience?

Dan: Friends and family mostly! ☺ I get the majority of my views from fabless semiconductor companies around the world, EDA and IP people, TSMC and the other foundries. More than half of my blog views come through LinkedIn and the people I am connected to. There are 50M+ people on LinkedIn and my connections link me to “5,422,800+ professionals”.

Liz: Let’s talk about “Social Media.”

Dan: The big EDA companies are already into Social Media, Synopsys, Cadence, and Mentor all have corporate bloggers and thousands of employees on LinkedIn. Blogs are now featured on the front of all three corporate websites. Synopsys had a nice social media program at the last Design Automation Conference. I blogged about it in “Twitter #SNPS #TSMC #46DAC” I’ve pushed Social Media to quite a few small and medium sized companies in the semiconductor design enablement business, with little success however. ☹

Liz: Well, it’s like Twitter. Not everybody is ready for it. It’s new, and takes a person out of her comfort zone.

Dan: People are scared because of the transparency, the same thing with blogging, fear-uncertainty-doubt. It concerned me as well but I think the rewards by far outweigh the risk. Blogging has many side benefits: My IQ has probably doubled as has my ego. If I ever take another VP of Sales and Marketing job I would only hire sales people with a LinkedIn profile and 500+ connections. My product marketing people would be required to blog and participate in LinkedIn groups. It keeps them close to customers and the market segment they serve.