Technically Speaking, Inc

Designing with IEEE-1076 VHDL - Xilinx Vivado DS - Las Vegas, NV

This comprehensive course is a thorough introduction to both the IEEE-1076 VHDL language and the Xilinx Vivado Design Suite. The emphasis is on writing solid synthesizable code and enough simulation code to write a viable testbench. Structural, register transfer level (RTL), and behavioral coding styles are covered. This class addresses targeting Xilinx devices specifically and FPGA devices in general. Beyond that, the class covers Vivado DS specific topics using either the Project or Non-Project Design flows. The information gained can be applied to any digital design by using a top-down synthesis design approach. This course combines insightful lectures with practical lab exercises to reinforce key concepts. You will also learn best HDL coding practices and how to maximize FPGA device reliability.

In this three-day course, you will gain valuable hands-on experience. Incoming students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations, all while utilizing the optimization, reporting and analysis features of the Xilinx Vivado DS.

Course Outline

Day 1

HDL Design Flow Overview

Hardware Modeling Concepts

VHDL Design Units

Introduction to Vivado & Project Design Flow

Lab 1: Creating Hierarchy

Introduction to Testbenches & Vivado Simulation

Lab 2: Build Testbench, Run Simulation

VHDL Signals & Datatypes

Operators and Expressions

Lab 3: Build RAM / ROM Module

Day 2

Concurrent & Sequential Statements

Vivado Reporting Features

Lab 4: Build Clock Divider – Address Counter

Controlled Operation Statements, If/else – Case -LoopsLab 5:

Using VITAL

Behavioral to RTL Coding

Day 3

Coding FSMs in VHDL

Lab 7: Modify & Test Existing FSM Source Code

Targeting Xilinx FPGAs

Tcl Scripting in Vivado

Lab 8: Xilinx Tool Flow, Download to Demo Board

VHDL Subprograms, Functions and Procedures

Advanced Process Statements

Lab 9: Simulation with VHDL Text I/O

Lab Descriptions

The labs for this course provide a practical foundation for creating synthesizable RTL code. All aspects of the design flow are covered in the labs. You will write, synthesize, simulate, and implement all the labs. The focus of the labs is to write code that will optimally infer reliable and high-performance circuits.

* This course does not focus on any particular architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

After completing this comprehensive training, you will have the necessary skills to:

Write effective RTL code for high QoR synthesis

Identify the differences between behavioral, RTL and structural coding styles

Distinguish constructs for synthesis versus simulation

Use scalar and composite data types to represent information

Use concurrent and sequential control structure to regulate information flow