Fan-Out Packaging Gains Steam

Fan-outs are creating a buzz and gaining steam in the market at a pace far beyond what anyone would have expected even at the start of the year.

The approach, which has been around for several years, is a wafer-level packaging process that enables ultra-thin, high-density packages.

So why the buzz? Apple is apparently moving to fan-out packaging, according to analysts. Previously, to house its application processors for the iPhone, Apple has used the more traditional package-on-package (PoP) technology.

For the next-generation iPhone7, though, TSMC is believed to be making Apple’s A10 application processor on a foundry basis for Apple, according to a report from Yole Développement. Based on a 16nm finFET process, Apple’s A10 will be housed in TSMC’s fan-out technology, dubbed InFO, according to the research firm.

Apple, of course, could change its mind and move in a different direction. But Apple’s reported move is prompting other outsourced semiconductor assembly and test (OSAT) houses, such as Amkor, ASE, SPIL, STATS and others, to step up their efforts in fan-out. Indeed, driven by Apple and perhaps others, the fan-out packaging market is projected to reach $2.4 billion by 2020, up from $174 million in 2014, according to Yole.

“The discussion about Apple using TSMC’s InFO is creating a lot of buzz,” said Jan Vardaman, president of TechSearch International. “If you think about the fact that there is no substrate (in fan-out), you can make this package very thin, and it has electrical advantages. So it makes sense for Apple and probably Samsung smartphones. Apple also has a major impact on our industry. Everyone follows. That does not mean that every package is going to use fan-out, just as not all packages are flip-chip, let alone copper pillar.”

Other OEMs and chipmakers are also taking a hard look at fan-out, but moving to this package type presents some challenges. For example, customers face some difficult, if not confusing, choices. Each fan-out provider offers a slightly different flavor of the technology. Some are working on six different fan-out types at once.

To complicate matters, fan-out comes in 2D, 2.5D and 3D IC configurations. In addition, fan-out is being produced on 300mm wafers. But eventually, the industry wants fan-out on a panel format, which will require the equipment industry to develop new tools.

On the technical front, fan-out has some issues in the production flow, namely wafer warpage and yield. Cost will also play a role.

All told, fan-out involves a complex set of issues. To help the industry get ahead of the curve, Semiconductor Engineering has taken a look at some of the bigger issues with fan-out.

Why fan-out?
The shift toward next-generation mobile products and other systems have driven the need for thinner packages. One ultra-thin package type is called a wafer-level chip-scale package (CSP). “Wafer-level CSP is fan-in,” said William Chen, a fellow at Advanced Semiconductor Engineering (ASE). “Wafer-level CSP is one of the smallest packages that is available. So, smartphones have adopted wafer-level CSP.”

Fan-in, according to Yole, runs out of steam at about 200 I/Os and 0.6mm profiles. “You have a wafer-level CSP and then you do a chip shrink. It’s the same product, but you produced it in a smaller die. If you do that, then the space that you have for the ball-grid array is no longer sufficient to provide the number of I/Os,” Chen said.

For more I/Os, chipmakers could use another wafer-level package called flip-chip. But flip-chip is a higher-end package for processors and graphics chips.

So, fan-out fills the gap between fan-in and flip-chip. Unlike fan-in, fan-out allows for the redistribution of the I/Os beyond the chip footprint, enabling packages with profiles at ≤0.4mm, according to TechSearch.

In some respects, 2.5D/3D-like fan-out packages compete against 2.5D/3D stacked die using TSVs. Some, however, argue the two technologies are targeted for different markets. “2.5D and 3D are separate from fan-out,” ASE’s Chen said. “They are used for different applications.”

Generally, fan-out packages are targeted for automotive, mobile products and RF. “There is a lot of momentum with fan-out,” said Scott Sikorski, vice president of product technology marketing at STATS ChipPAC. “It won’t necessarily be the right solution for every single application and every customer.”

Meanwhile, in the fan-out flow, the process starts with a carrier and double-sided tape. The tape sits on the carrier. Then, individual die are placed on the tape. A mold compound covers the die and one side of the tape. The carrier and tape subsequently are removed, leaving the die embedded in the mold. Then, the so-called reconstituted wafer is flipped upside. The die are exposed at the top. Then, redistribution lines (RDLs) are formed at the top. Solder balls are attached, and the dies are singulated.

“Fan-out is not a new technology,” said Ramakanth Alapati, director of packaging strategy and marketing at GlobalFoundries. “If you look at traditional fan-out, Infineon developed the technology some time ago. A lot of OSATs have licensed that technology and put it into production. There are multiple versions of it.”

Generally, the design rules for today’s fan-out are 10-micron line and space. “What is different now, versus the existing technologies, is what we call the high-density version of fan-out,” Alapati said. “A lot of the focus has been below 3- by 3-micron line/space. That has not caught everybody by surprise, but I would say it intrigues everybody because it can play a significant part in a lot of product roadmaps. It brings a lot of form-factor advantages. It has cost advantages in some cases. It brings a lot of things to the table like complex integration.”

Fan-out based on 3-micron line/space and below is not in production yet. “It is in qualification. The ramp may be next year or the following year. That depends on customer demand,” Alapati said.

Vendor selection and formats
In any case, OEMs and chipmakers face some tough choices if or when they move to fan-out. One of the obvious choices is vendor selection. On one front, for example, Infineon and a few other chipmakers have their own, internal fan-out packaging capabilities.

In addition, the traditional OSATs, such as Amkor, ASE, Nanium, SPIL, STATS and others, are also developing fan-out packages. And TSMC recently entered the fan-out packaging market, a move that puts the company in competition with the OSATs.

While selecting a vendor is a difficult task, there are a multitude of other considerations as well. For example, fan-out is manufactured in an OSAT using 300mm wafers. For this, OSATs use traditional wafer-level processing equipment.

In R&D, the industry is working on fan-out based on a panel or square format. The panel format enables more die, thereby lowering costs. For example, a 300mm wafer enables 616 packages at 10- x 10-mm, while an 18- x 24-inch panel produces 1,911 packages, according to Qualcomm.

“To me, 300mm (round) is not sufficient. It doesn’t give us the cost reduction to really engage in fan-out fully,” said Beth Keser, a principal engineer for advanced packaging at Qualcomm. “When you go from 300mm to a panel that’s 18 x 24 inches, that’s a serious cost reduction.”

The problem? It’s akin to the great 450mm fab debate. OSATs will require many new types of equipment for the panel format. But it’s unclear if equipment makers are willing to take the risk and develop new panel-based gear. Only a few OSATs and foundries can afford to set up panel lines.

Plus, there are no standards for the panel size itself. “We have to decide what size will be our panel standard,” Keser said. “That’s where we are struggling now.”

Equipment makers are lukewarm about developing new tools for the panel format. “From an equipment supplier view, you would have to be rather reluctant to jump into this panel-size development,” said Thomas Uhrmann, director of business development at EV Group. “It’s a huge effort to scale up the equipment. It’s going to be costly as well.”

There are other issues. “Panels may happen, but panels may happen in places where you don’t need a very fine-pitch line-space,” GlobalFoundries Alapati said. “If you are doing 5- by 5-micron today, panel might make sense, because you are not gated by alignment. But if you are at 2- by 2-micron, then panel becomes a challenge.”

For the next two years, the 300mm format is sufficient for fan-out, experts say. But soon, the industry may demand panel-level processing. This, of course, depends on whether the industry can agree on a standard format. And it also depends on cost and demand.

Fan-out galore
The next big challenge is to decide what fan-out technology to adopt. In basic terms, there are several ways to do high-density fan-out, such as chips first, chips last, face up and face down.

TSMC, for one, is implementing the “chips first” process with its InFO fan-out technology. In contrast, a group last year formed a fan-out consortium, which is developing competitive packages. Led by A*Star, a Singaporean R&D organization, the High-Density Fan-Out Wafer Level Packaging (FOWLP) consortium includes Amkor, Nanium, STATS, NXP, GlobalFoundries, K&S, Applied Materials, Dipsol, JSR, KLA-Tencor, Kingyoup, Orbotech and TOK.

The consortium is developing two types of high-density fan-out packages—mold-first and RDL- first/chips-last. In some respects, mold-first resembles a traditional fan-out flow.

“Chips first is a process whereby the die is attached to a temporary or permanent material structure prior to creating the RDL that will extend from the die to BGA/LGA interface. In this manner, the yield loss associated with creating the RDL occurs after the die is mounted, subjecting the die to potential loss,” said Ron Huemoeller, vice president of R&D at Amkor.

“The reverse is true for a chips last process. RDL is created first. The die is then mounted. In this flow, the RDL structures can either be electrically tested or visually inspected for yield loss, thereby avoiding placing good die on bad sites. For low I/O die, where RDL is minimal and yields are very high (>99%), a dies-first flow is preferred. However, for high value die (large I/O), a dies-last process is preferred,” Huemoeller said.

Indeed, the success or failure with fan-out depends on several factors, including yield. But there are challenges in terms of producing fan-out in the factory with high yields. “There are warpage issues with the wafers,” said Prashant Aji, senior technical director at KLA-Tencor. “In addition, the RDLs are becoming smaller. There are breakages of these metal lines, creating stress.

“You also have fully processed dies. But if your packaging is killing that die, then you are throwing away good die. That is why process control for packaging is becoming more important,” Aji said.

2D vs. 3D
Fan-out enables 2D packages, which can house one die or multiple chips. In addition, fan-out can extend in a vertical direction, enabling 2.5D- or 3D-like packages.

For example, Amkor recently introduced a technology called Swift, which enables 2D and 3D fan-out packages. For 3D-like packages, Swift makes use of tall copper pillars or through-mold via (TMV) solder balls to form the vertical interconnects.

Other technologies, such as TSV bars and PCB bars, can also be used to form vertical interconnects. So far, though, the industry is still sorting out the various technologies. “Each one has different advantages,” Qualcomm’s Keser said. “We’re still wondering what’s really going to be the final solution.”