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Abstract

This article describes a device which is in a chip that resides on an I/O processor (IOP) card and is responsible for direct memory access (DMA) between IOP storage and host storage elements. (Image Omitted)

Country

United States

Language

English (United States)

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Page 1 of 5

Ping-Pong Buffer Controller for DMA Transfers

This article describes a device which is in a chip that resides on an I/O
processor (IOP) card and is responsible for direct memory access (DMA)
between IOP storage and host storage elements.

(Image Omitted)

Fig. 1 shows the relationship between the various hardware elements in the
overall IOP design. The IOP uses a synchronous bus as the main
communication vehicle between the on-board microprocessor and the various
functional elements. A ping-pong buffer and controller reside on the system
processor bus (SPB) chip and are responsible for DMA between the IOP storage
and host storage elements. In order to accomplish this, the data transfer must
incur the use of both the synchronous intercommunication (IC) bus and the
asynchronous host processor bus. The ping-pong buffer also provides the
capability to DMA data between I/O Adapter (IOA) hardware and host storage. In
this case, the IOA bus, the bypass (BP) bus and the host bus are used for the
data transfer. Both the IOA and BP buses are synchronous. The data path
switching from IOA and host storage or IOP storage and host storage data
transfers is the responsibility of the ping-pong controller. This switching can be
accomplished by either a memory mapped switch or by a status bit loaded by
microcode into the SPB chip. The ping-pong buffer controller also provides byte
alignment between IOP storage and host storage, or the IOA buffers and host
storage. The ping-pong buffer controller is designed so that it provides a simple
interface to bus tag controllers. The tag controllers are state machines that do
the handshaking on the host, IC and BP buses. The ping-pong controller notifies
the bus tag controllers when buffers are available for the DMA operation, and
supplies the correct address information. Packet Buffers

The ping-pong logic consists of two RAM buffers, input and output byte
alignment logic, input and output data multiplexers, and buffer control logic. Fig.
2 shows the relationship of these components in block diagram. During the first
packet data transfer into the ping- pong buffers, the buffer controller always
chooses buffer 1 as the first input buffer. This is done by use of the read/write
(R/W) 1 line set to write and the activation of the SEL 1 line. Buffer 2 is not used.
Therefore, the SEL 2 line is inactive. After the packet to buffer 1 is complete,
buffer 1 is switched to the output mode and buffer 2 is switched to the input mode
by use of the R/W 1 and R/W 2 lines. Buffer 1 can now output its data and a new
data packet can be loaded into buffer 2 concurrently. At this point, both buffer
operations must be complete before another buffer swap can occur. The buffer
controller will continue this ping-pong operation until the last packet of the data
block is complete. The DMA operation will then be terminated by the controller.
The controller logic accesses a transfer count register (TCR) to determine when
the last packet is...