Regarding your question, I think 3.2us delay is understandable. As you said you set up 10MHz for the ADC12 clock, in parallel mode, the first conversion takes 10 ADC clock cycles or 1uS, the second conversion takes 8 ADC clock cycles or 0.8us, the ADC conversions need total 1.8uS. But you have to consider software latency, especially, when you develop application code based on PE. I suppose you develop code based on PE, you use interrupt mechanism, in the ISR of ADC end of scan interrupt, you toggle a GPIO, then compare the delay between PWM signal and the GPIOs. The function calling takes a lot of time, saving register takes time.

In order to reduce the latency, I suggest you develop code without PE, even you can use polling mode, after checking the EOSI in ADC_STAT register, once it is set, toggle GPIO immediately, you will see the latency.

Regarding your question, I think 3.2us delay is understandable. As you said you set up 10MHz for the ADC12 clock, in parallel mode, the first conversion takes 10 ADC clock cycles or 1uS, the second conversion takes 8 ADC clock cycles or 0.8us, the ADC conversions need total 1.8uS. But you have to consider software latency, especially, when you develop application code based on PE. I suppose you develop code based on PE, you use interrupt mechanism, in the ISR of ADC end of scan interrupt, you toggle a GPIO, then compare the delay between PWM signal and the GPIOs. The function calling takes a lot of time, saving register takes time.

In order to reduce the latency, I suggest you develop code without PE, even you can use polling mode, after checking the EOSI in ADC_STAT register, once it is set, toggle GPIO immediately, you will see the latency.