Smart ways to write System Verilog Assertions

The lack of an "efficient assertion coding methodology" imprints Assertion Based Verification (ABV) adoption as a colossal task in some minds. The foremost challenge in terms of adopting an assertion methodology is the time spent on the "learning curve" of an assertion language. This article describes a few of the rules/guidelines focusing on System verilog assertions (since this standard has gained wide acceptance) which would help in writing effective assertion code enabling a robust ABV environment.

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"6. Avoid use of open ended delays ## in the antecedent ...
Need to constraint the open ended range by making use of sequence operators"
A better approach is to use the first_match operator.
Ex : @(posedeg clk) disable iff (reset)
first_match(siga ##[1:$] sigb) ...
Ben Cohen SystemVerilog.us

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