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Abstract:

A memory cell including two transistors and one capacitor, which is known
as a gain cell, is improved. One electrode of the capacitor is connected
to a bit line, and the other electrode thereof is connected to a drain of
a write transistor. A source of the write transistor is connected to a
source line. As a result, for example, in the case where a stacked
capacitor is used, the one electrode of the capacitor can be part of the
bit line. Only one specific write transistor is turned on when a
potential of the source line and a potential of the write bit line are
set; thus, only one memory cell can be rewritten.

Claims:

1. A semiconductor device comprising: a write bit line; a write word
line; a read line; a source line; and a memory cell, wherein the memory
cell comprises a write transistor, a read transistor, and a capacitor,
wherein a gate, a drain, and a source of the write transistor are
connected to the write word line, one electrode of the capacitor, and the
source line, respectively, and wherein the read line is intersecting with
the source line.

2. The semiconductor device according to claim 1, wherein the source line
is formed in parallel to the write word line.

3. The semiconductor device according to claim 1, wherein the source line
is formed in parallel to the write bit line.

4. The semiconductor device according to claim 1, wherein a conductivity
type of the write transistor is different from a conductivity type of the
read transistor.

5. The semiconductor device according to claim 1, wherein off-state
resistance of the write transistor is higher than or equal to
1.times.10.sup.18.OMEGA..

6. A semiconductor device comprising: a write bit line; a write word
line; a read line; a source line; and a memory cell, wherein the memory
cell comprises a write transistor, a read transistor, and a capacitor,
wherein a gate of the write transistor is connected to the write word
line, wherein one electrode of the capacitor is connected to a drain of
the write transistor, wherein the other electrode of the capacitor is
connected to the write bit line, and wherein the read line is
intersecting with the source line.

7. The semiconductor device according to claim 6, wherein the source line
is formed in parallel to the write word line.

8. The semiconductor device according to claim 6, wherein the source line
is formed in parallel to the write bit line.

9. The semiconductor device according to claim 6, wherein a conductivity
type of the write transistor is different from a conductivity type of the
read transistor.

10. The semiconductor device according to claim 6, wherein off-state
resistance of the write transistor is higher than or equal to
1.times.10.sup.18.OMEGA..

11. A method for driving a semiconductor device, the semiconductor device
comprising: a write bit line; a write word line; a read line; a source
line; and a memory cell, wherein the memory cell comprises a write
transistor, a read transistor, and a capacitor, wherein a gate, a drain,
and a source of the write transistor are connected to the write word
line, one electrode of the capacitor, and the source line, respectively,
wherein the read line is intersecting with the source line, and wherein a
potential of the source line is kept constant during data reading and
data writing.

12. The method for driving the semiconductor device according to claim
11, wherein the source line is formed in parallel to the write word line.

13. The method for driving the semiconductor device according to claim
11, wherein the source line is formed in parallel to the write bit line.

14. The method for driving the semiconductor device according to claim
11, wherein a conductivity type of the write transistor is different from
a conductivity type of the read transistor.

15. The method for driving the semiconductor device according to claim
11, wherein off-state resistance of the write transistor is higher than
or equal to 1.times.10.sup.18.OMEGA..

16. A method for driving a semiconductor device, the semiconductor device
comprising: a write bit line; a write word line; a read line; a source
line; and a memory cell, wherein the memory cell comprises a write
transistor, a read transistor, and a capacitor, wherein a gate, a drain,
and a source of the write transistor are connected to the write word
line, one electrode of the capacitor, and the source line, respectively,
wherein the read line is intersecting with the source line, and wherein
potentials of the drain and the source of the write transistor
immediately after writing of a piece of data are equal to potentials of
the drain and the source of the write transistor immediately after
writing of another piece of data.

17. The method for driving the semiconductor device according to claim
16, wherein the source line is formed in parallel to the write word line.

18. The method for driving the semiconductor device according to claim
16, wherein the source line is formed in parallel to the write bit line.

19. The method for driving the semiconductor device according to claim
16, wherein a conductivity type of the write transistor is different from
a conductivity type of the read transistor.

20. The method for driving the semiconductor device according to claim
16, wherein off-state resistance of the write transistor is higher than
or equal to 1.times.10.sup.18.OMEGA..

21. A method for driving a semiconductor device, the semiconductor device
comprising: a write bit line; a write word line; a read line; a source
line; and a memory cell, wherein the memory cell comprises a write
transistor, a read transistor, and a capacitor, wherein a gate of the
write transistor is connected to the write word line, wherein one
electrode of the capacitor is connected to a drain of the write
transistor, wherein the other electrode of the capacitor is connected to
the write bit line, wherein the read line is intersecting with the source
line, and wherein a potential of the source line is kept constant during
data reading and data writing.

22. The method for driving the semiconductor device according to claim
21, wherein the source line is formed in parallel to the write word line.

23. The method for driving the semiconductor device according to claim
21, wherein the source line is formed in parallel to the write bit line.

24. The method for driving the semiconductor device according to claim
21, wherein a conductivity type of the write transistor is different from
a conductivity type of the read transistor.

25. The method for driving the semiconductor device according to claim
21, wherein off-state resistance of the write transistor is higher than
or equal to 1.times.10.sup.18.OMEGA..

26. A method for driving a semiconductor device, the semiconductor device
comprising: a write bit line; a write word line; a read line; a source
line; and a memory cell, wherein the memory cell comprises a write
transistor, a read transistor, and a capacitor, wherein a gate of the
write transistor is connected to the write word line, wherein one
electrode of the capacitor is connected to a drain of the write
transistor, wherein the other electrode of the capacitor is connected to
the write bit line, wherein the read line is intersecting with the source
line, and wherein potentials of the drain and a source of the write
transistor immediately after writing of a piece of data are equal to
potentials of the drain and the source of the write transistor
immediately after writing of another piece of data.

27. The method for driving the semiconductor device according to claim
26, wherein the source line is formed in parallel to the write word line.

28. The method for driving the semiconductor device according to claim
26, wherein the source line is formed in parallel to the write bit line.

29. The method for driving the semiconductor device according to claim
26, wherein a conductivity type of the write transistor is different from
a conductivity type of the read transistor.

30. The method for driving the semiconductor device according to claim
26, wherein off-state resistance of the write transistor is higher than
or equal to 1.times.10.sup.18.OMEGA..

Description:

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a memory device including a
semiconductor.

[0003] 2. Description of the Related Art

[0004] A 1T1C DRAM which includes a memory cell including one transistor
and one capacitor has no limit on the number of times of writing in
principle, and can perform writing and reading at relatively high speed,
thereby used in many kinds of electronic appliances (see Patent Document
1 and Patent Document 4). The 1T1C DRAM performs data reading in such a
manner that accumulated charge is released to a bit line and a change in
a potential is measured; therefore, the capacitance of the capacitor
needs to be at a certain value or more. As a result, it becomes more and
more difficult to keep necessary capacitance because of miniaturization
of a circuit.

[0005] In contrast, in a gain cell DRAM which includes a memory cell
including two transistors and one capacitor, an amount of charge can be
amplified by a read transistor and the charge can be supplied to a bit
line even when the capacitance of the capacitor is small; therefore, it
is assumed that the capacitor can be made small (see Patent Document 2
and Patent Document 3).

[0006]FIG. 2 is a circuit diagram of a memory cell of a conventional gain
cell DRAM. A memory cell 201 includes a write transistor 202 and a
capacitor 203. A gate of the write transistor 202 is connected to a write
word line 204. A drain of the write transistor 202 is connected to a bit
line 205, a source of the write transistor 202 is connected to a first
electrode (capacitor electrode) of the capacitor 203, and a second
electrode of the capacitor 203 is connected to a read word line 208.

[0007] The source of the write transistor 202 and the first electrode of
the capacitor 203 are connected to a gate of a read transistor 207.
Further, a drain of the read transistor 207 is connected to the bit line
205 and a source of the read transistor 207 is connected to a source line
206.

[0008] In order that data is written in the memory cell 201, while a
potential of the bit line 205 is at a value corresponding to the data, a
potential of the write word line 204 is controlled so that the write
transistor 202 is turned on; thus, the capacitor 203 is charged. Then,
the potential of the write word line 204 is controlled, so that the write
transistor 202 is turned off. At this time, a potential of a connection
point (storage node SN) between the source of the write transistor 202
and the first electrode of the capacitor 203 has the value corresponding
to the data.

[0009] In order that data is read from the memory cell 201, the bit line
205 is set to be in a floating state at a certain potential and a
potential of the read word line 208 is controlled, so that the potential
of the storage node SN is adjusted; thus, the state of the read
transistor 207 is changed. At this time, when the read transistor 207 is
on, the amount of charge accumulated in the bit line 205 is changed and
the change in the potential of the bit line 205 is measured.

[0014] An object of an embodiment of the present invention is to provide a
semiconductor memory device and another semiconductor device each of
which has a structure simpler than that of a conventional one, driving
methods thereof, or manufacturing methods thereof. Further, an object of
an embodiment of the present invention is to provide a semiconductor
memory device and another semiconductor device each of which has
integration degree higher than that of a conventional one, driving
methods thereof, or manufacturing methods thereof.

[0015] Further, an object of an embodiment of the present invention is to
provide a semiconductor memory device and another semiconductor device
each with power consumption lower than that of a conventional one,
driving methods thereof, or manufacturing methods thereof. Furthermore,
an object of an embodiment of the present invention is to provide a
semiconductor memory device and another semiconductor device each of
which can be manufactured through steps fewer than those of a
conventional one, driving methods thereof, and manufacturing methods
thereof.

[0016] Further, an object of an embodiment of the present invention is to
provide a memory device having a novel structure or a method for driving
the memory device. In particular, it is an object of an embodiment of the
present invention to provide a memory device in which power consumption
can be reduced and a driving method in which power consumption can be
reduced.

[0017] The present invention will be described below; terms used in this
specification are briefly described. First, when one of a source and a
drain of a transistor is called a drain, the other is called a source in
this specification. That is, they are not distinguished depending on the
potential level. Therefore, a portion called a source in this
specification can be alternatively referred to as a drain.

[0018] Further, when the expression "to be connected" is used in this
specification, there is a case in which no physical connection is made in
an actual circuit and a wiring is only extended. For example, in the case
of a circuit including an insulated-gate field-effect transistor
(MISFET), one wiring functions as gates of a plurality of MISFETs in some
cases. In that case, one wiring which branches into gates may be
illustrated in a circuit diagram. Even in such a case, the expression "a
wiring is connected to a gate" may be used in this specification.

[0019] Note that the terms "equal", "same", and "identical" mean not only
the state where the amounts, the shapes, or the like exactly match, but
practically also means the state where the amounts, the shapes, or the
like have allowable differences. For example, when a potential of a
source is 0.1 V lower than a potential of a drain, this state is
expressed as "the potential of the source and the potential of the drain
are equal" as long as the difference in the potentials does not
significantly disturb operation.

[0020] An embodiment of the present invention is a semiconductor memory
device including a write bit line, a write word line, and memory cells.
Each of the memory cells includes a write transistor, a read transistor,
and a capacitor. In each of the memory cells, a gate, a drain, and a
source of the write transistor are connected to the write word line, one
electrode of the capacitor, and a source line, respectively.

[0021] Further, an embodiment of the present invention is a semiconductor
memory device including a write bit line, a write word line, and memory
cells. Each of the memory cells includes a write transistor, a read
transistor, and a capacitor. In each of the memory cells, a gate of the
write transistor is connected to the write word line, one electrode of
the capacitor is connected to a drain of the write transistor, and the
other electrode of the capacitor is connected to the write bit line.

[0022] The source line may be formed in parallel to the write bit line.
Further, the capacitance of the capacitor of the memory cell may be one
time to ten times the gate capacitance of the write transistor. In that
case, the off-state resistance of the write transistor is preferably
greater than or equal to 1×1018Ω.

[0023] An embodiment of the present invention is a method for driving
either of the above-described semiconductor memory devices, in which
potentials of the drain and the source of the write transistor
immediately after one data (e.g., data "1") is written are equal to those
immediately after another data (e.g., data "0") is written.

[0024] With the above structure, a semiconductor memory device and another
semiconductor device each of which has a structure simpler than that of a
conventional one, and driving methods thereof can be provided. Further, a
semiconductor memory device and another semiconductor device each of
which has integration degree higher than that of a conventional one, and
driving methods thereof can be provided. A semiconductor memory device
and another semiconductor device each with power consumption lower than
that of a conventional one, driving methods thereof, and manufacturing
methods thereof can be provided. Furthermore, a semiconductor memory
device and another semiconductor device each of which can be manufactured
through fewer steps than those of a conventional one, and driving methods
thereof can be provided. Note that the effect of the present invention
will be described in detail in the following embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In the accompanying drawings:

[0026]FIG. 1 is a circuit diagram illustrating an example of a
semiconductor memory device of the present invention;

[0028] FIGS. 3A and 3B illustrate an example of a method for driving a
semiconductor memory device of the present invention;

[0029] FIGS. 4A and 4B illustrate an example of a method for driving a
semiconductor memory device of the present invention;

[0030] FIGS. 5A and 5B illustrate an example of a method for driving a
semiconductor memory device of the present invention;

[0031] FIGS. 6A to 6C illustrate an example of a method for driving a
semiconductor memory device of the present invention;

[0032] FIGS. 7A to 7C illustrate an example of a method for driving a
semiconductor memory device of the present invention;

[0033] FIGS. 8A and 8B illustrate an example of steps of manufacturing a
semiconductor memory device of the present invention;

[0034] FIGS. 9A and 9B illustrate an example of steps of manufacturing a
semiconductor memory device of the present invention; and

[0035] FIGS. 10A to 10C illustrate a structure of a semiconductor memory
device of the present invention and manufacturing steps thereof.

DETAILED DESCRIPTION OF THE INVENTION

[0036] Hereinafter, embodiments will be described with reference to
drawings. Note that the embodiments can be implemented with various
modes, and it is easily understood by those skilled in the art that modes
and details can be changed in various ways without departing from the
spirit and scope of the present invention. Therefore, the present
invention should not be interpreted as being limited to the following
description of the embodiments.

[0037] In the accompanying drawings, a circle on a transistor indicates
that the transistor is in an on state, and a cross on a transistor
indicates that the transistor is in an off state. As for a read
transistor, the state where a potential of a source and a potential of a
drain are equal and thus current does not flow therebetween is also
regarded as an off state in some cases.

[0038] Note that ones that have the same function, ones that are formed
using the same material, or ones that are formed simultaneously are
denoted by the same reference numerals in some cases. In the case where
the ones denoted by the same reference numerals needs to be
distinguished, "--1", "--2", and the like are added to the
reference numerals in some cases. For example, when a plurality of read
gates 112 is formed using the same material, the respective read gates
are denoted by "112_1", "112_2", and the like in a drawing. In this
specification, in some cases, the read gates are collectively denoted by
a "read gate 112", while one of the read gates is denoted by a "read gate
112_1" in order that the one of the read gates is distinguished from the
others.

Embodiment 1

[0039]FIG. 1 is a circuit diagram of a memory cell of a semiconductor
memory device of this embodiment. A memory cell 101 includes one write
transistor 102, one read transistor 107, and one capacitor 103. A gate of
the write transistor 102 is connected to a write word line 104, and a
source of the write transistor 102 is connected to a source line 106.

[0040] A first electrode of the capacitor 103 is connected to a drain of
the write transistor 102. This node is referred to as a storage node SN.
A second electrode of the capacitor 103 is connected to a write bit line
105.

[0041] A gate of the read transistor 107 is connected to the storage node
SN, a drain of the read transistor 107 is connected to a read line 108,
and a source of the read transistor 107 is connected to the source line
106. Note that the read line 108 is preferably arranged to be orthogonal
to (intersecting with) the source line 106.

[0042] In FIG. 1, the source line 106 is provided in parallel to the write
bit line 105; however, there is no limitation thereon, and the source
line 106 may be provided in parallel to the write word line 104. When the
source line 106 is provided in parallel to the write word line 104,
wirings are effectively integrated. On the other hand, when the source
line 106 is provided in parallel to the write bit line 105, on and off of
the write transistor in every memory cell can be controlled independently
for the reason described later.

[0043] Note that a method disclosed in Patent Document 1 can be used for
providing the source line 106 in parallel to the write bit line 105, for
example.

[0044] Next, examples of methods for writing data to and reading data from
the memory cell 101 having the circuit configuration in FIG. 1 will be
briefly described with reference to FIGS. 3A and 3B, FIGS. 4A and 4B, and
FIGS. 5A and 5B. Note that although a specific value is given for a
potential or the like in the following description for easy
understanding, the present invention is not limited to such a value.

[0045] Here, a potential of the write bit line 105 is +1 V in the case of
data "1", and the potential of the write bit line 105 is 0 V in the case
of data "0". The write transistor 102 and the read transistor 107 are
n-channel transistors. The threshold voltage of the write transistor 102
is +0.5 V and the threshold voltage of the read transistor 107 is +1 V.
Note that the conductivity types of the write transistor 102 and the read
transistor 107 can be set as appropriate. Here, the capacitance of the
capacitor 103 is sufficiently larger than the gate capacitance of the
read transistor 107. Parasitic capacitance or the like which is not
illustrated is ignored.

[0046] A potential of the write word line 104 is sufficiently low (here,
-1 V) so that the write transistor 102 is not turned on except in the
case where writing is performed. First, the potential of the write bit
line 105 is set to 0 V. At this time, a potential of the storage node SN
is +1 V or 0 V, which is determined in accordance with (the potential of)
written data. A potential of the source line 106 is set to +1 V and a
potential of the read line 108 is set to +2 V.

[0047] In this state, the potential of the write word line 104 is
increased to +2 V, so that the write transistor 102 is turned on. Then,
the potential of the storage node SN becomes +1 V. At this time, the read
transistor 107 is off (see FIG. 3A).

[0048] Next, the potential of the write bit line 105 is set to +1 V or 0 V
in accordance with the data to be written. In this case, the potential of
the storage node SN remains +1 V. However, since a potential difference
between the electrodes of the capacitor 103 in accordance with the
potential of the write bit line 105 is generated, charge in accordance
with the potential difference is held in the first electrode of the
capacitor 103 (see FIG. 3B).

[0049] After that, the potential of the write word line 104 is reduced to
-1 V, so that the write transistor 102 is turned off. The charge held in
the first electrode of the capacitor 103 is held in the storage node SN.
This is the end of the write operation.

[0050] When the potential of the write bit line 105 is set to +2 V, the
potential of the storage node SN is +2 V or +3 V. Then, the potential of
the source line 106 is increased to +2 V, and the potential of the write
word line 104 is increased from -1 V to +2 V (see FIG. 4A). Since the
potential of the gate of the write transistor 102 (+2 V) is not higher
than either the potential of the source or the potential of the drain,
the write transistor 102 remains off. In other words, when both the
potential of the write bit line 105 and the potential of the source line
106 are high, such as the case where the potential of the write bit line
105 and the potential of the source line 106 are +2 V, data cannot be
written.

[0051] In the conventional gain cell memory, for rewriting data in one
memory cell, when a potential of a write word line to which the memory
cell is connected is increased, a write transistor in a different memory
cell which is connected to the write word line is also turned on;
therefore, these is a problem in that data held in the different memory
cell is erased. This problem is difficult to be solved in the gain cell
memory having the conventional structure. However, as is clear from the
above description, in an embodiment of the present invention, unnecessary
erasure of data in a memory cell can be prevented in such a manner that
the potential of the write bit line 105 and the potential of the source
line 106 provided in parallel to the write bit line 105 are set as
appropriate.

[0052] In other words, the potentials of the write bit line and the source
line which are connected to the memory cell in which data is to be
written are set low (the potential of the write bit line is 0 V and the
potential of the source line is +1 V in the case of FIG. 3A), the
potential of the write word line is set to a predetermined value (+2 V in
the case of FIG. 3A), and then, the potential of the write bit line is
set to the potential of the data; thus, data can be written.

[0053] On the other hand, when potentials of a write bit line and a source
line which are connected to another memory cell are kept high (+2 V in
the case of FIG. 4A), a write transistor is kept in an off state even in
the case where the potential of the write word line becomes a specific
value (+2 V); therefore, data is not erased in the memory cell.

[0054] The above is preferable in terms of reduction in power consumption.
If data in a memory cell on which writing operation is not performed is
erased, such as the case of the conventional method, the data needs to be
restored; therefore, a potential of a bit line connected to the memory
cell needs to be changed, which consumes power. However, as described
above, only a potential of a write bit line to which a memory cell on
which data rewriting is performed is connected is changed, so that power
consumption can be significantly reduced.

[0055] When data writing is finished, the potential of the write word line
104 is kept at a sufficiently low potential (-1 V), as described above.
In this state, the potential of the write bit line 105 changes in the
range of 0 V to +2 V. For example, when the potential of the write bit
line 105 is 0 V, since the write bit line 105 is capacitively coupled
with the capacitor 103, the potential of the storage node SN is 0 V in
the case where data "1" is written, and the potential of the storage node
SN is +1 V in the case where data "0" is written. For this reason, the
potential of the storage node SN is 0 V or +1 V when the potential of the
write bit line 105 is 0 V in FIG. 3A.

[0056] Note that as the potential of the write bit line 105 is increased
more, the potential of the storage node SN is increased accordingly. For
example, when the potential of the write bit line 105 is +2 V, the
potential of the storage node SN is +2 V or +3 V.

[0057] In other words, the potential of the storage node SN changes in the
range of 0 V to +3 V. Further, the potential of the source line 106 is +1
V or +2 V. The potential of the read line 108 is kept at +2 V (see FIG.
4B). The potential of the storage node SN becomes +3 V only in the case
where the potential of the write bit line 105 is +2 V. At this time, the
potentials of the source line 106 and the write line 108 are +2 V;
therefore, current does not flow between the source and the drain of the
read transistor 107.

[0058] When the potential of the storage node SN is 0 V or +1 V, the read
transistor 107 is off. When the potential of the storage node SN is +2 V
and the potential of the source line 106 is +2 V, the read transistor 107
is also off. However, there is a case where the potential of the storage
node SN is +2 V and the potential of the source line 106 is +1 V. In this
case, the write transistor 107 is turned on, while the potential (+1 V),
which is obtained by reducing the potential of the read bit line 108
having high potential (+2 V) by the threshold voltage, is output to the
source line 106; therefore, current does not practically flow between the
source and the drain of the read transistor 107.

[0059] Next, a method for reading data will be described. First, the
potential of the write bit line 105 is set to a low potential (here, 0
V). Then, the potential of the storage node SN becomes 0 V or +1 V in
accordance with the written data. The potential of the source line 106 is
set to +1 V.

[0060] Next, either the read line 108 or the source line 106 is set to be
in a floating state. Here, the read line 108 is set to be in a floating
state and the potential thereof is +2 V. In this state, the read
transistor 107 is in an off state (see FIG. 5A).

[0061] Further, the potential of the write bit line 105 is controlled, so
that the state of the read transistor 107 is changed. Here, the potential
of the write bit line 105 is set to +1 V. Then, the potential of the
storage node SN becomes either +1 V or +2 V in accordance with the
written potential.

[0062] In the case where the potential of the storage node SN is +1 V, the
potential of the read line 108 remains +2 V. On the other hand, in the
case where the potential of the storage node SN is +2 V, the potential of
the read line 108 is reduced to +1 V. In other words, the potential of
the read line 108 is +2 V in the case where data "1" has been written,
and the potential of the read line 108 is +1 V in the case where data "0"
has been written (see FIG. 5B). Thus, data can be read. Note that data
cannot be erased in the above steps of data reading.

[0063] In the above example, although it is assumed that the capacitance
of the capacitor 103 is sufficiently larger than the gate capacitance of
the read transistor 107, as in the conventional gain cell memory, a
semiconductor memory device of an embodiment of the present invention can
perform a writing operation at higher speed by reducing the capacitance
of the capacitor 103.

[0064] Note that in the case where the capacitance of the capacitor 103 is
one time to ten times the gate capacitance of the read transistor 107,
the potential of the storage node SN is affected by the state (on or off)
of the read transistor 107 to be fluctuated, thereby not taking the above
simple value.

[0065] Note that time until charge accumulated in the capacitor 103 (or
the storage node SN) is released is proportional to the capacitance and
the off-state resistance of the write transistor 102. Accordingly, in the
case where the capacitance of the capacitor 103 is small, the off-state
resistance of the write transistor 102 is increased accordingly,
preferably increased to higher than or equal to 1×1018Ω.

Embodiment 2

[0066] In a memory cell of a semiconductor memory device of this
embodiment, the conductivity type of the read transistor 107 in FIG. 1 is
different from the conductivity type of the write transistor 102. For
example, when the write transistor 102 is an n-channel transistor, the
read transistor 107 is a p-channel transistor.

[0067] Examples of methods for writing data to and reading data from the
semiconductor memory device of this embodiment will be briefly described
with reference to FIGS. 6A to 6C and FIGS. 7A to 7C. Two memory cells
101_1 and 101_2 are illustrated in each of FIGS. 6A to 6C and FIGS. 7A to
7C. Data is input to the memory cell 101_1 through a write bit line
105_1, and data is input to the memory cell 101_2 through a write bit
line 105_2. In an example described below, after data is written to the
memory cell 101_1, the data is read from the memory cell 101_1 while data
in the memory cell 101_2 is retained and is not read.

[0068] Specific values are given below as potentials and the like for easy
understanding, but the present invention is not limited to the values.
Here, a potential of the write bit line 105 in the case of data of "1" is
+1 V, and the potential of the write bit line 105 in the case of data "0"
is 0 V.

[0069] The threshold voltage of the write transistor 102 and that of the
read transistor 107 are +0.5 V and -0.5 V, respectively. The capacitance
of the capacitor 103 is sufficiently larger than the gate capacitance of
the read transistor 107. In the example described below, data is written
only to the memory cell 101_1 (the left memory cell) and data is not
written to the memory cell 101_2 (the right memory cell).

[0070] A potential of the write word line 104 is sufficiently low (here,
-1 V) so that the write transistor 102 is not turned on except in the
case where writing is performed. First, a potential of the write bit line
105_1 is set to +1 V. A potential of the source line 106_1 is set to +1
V. At this time, as described in Embodiment 1, a potential of a storage
node SN of the memory cell 101_1 is +2 V or +1 V, which is determined in
accordance with (the potential of) written data.

[0071] A potential of the write bit line 105_2 is set to +2 V, and a
potential of a source line 106_2 is set to +2 V. As described in
Embodiment 1, a potential of a storage node SN of the memory cell 101_2
is +2 V or +3 V. A potential of the read line 108 is set to +1 V.

[0072] At this time, the read transistor of the memory cell 101_1 and the
read transistor of the memory cell 101_2 are off because the gate
potential is higher than or equal to the potential of a source or a drain
in each of the read transistors (see FIG. 6A).

[0073] In this state, when the potential of the write word line 104 is
increased to +2 V, the write transistor of the memory cell 101_1 is
turned on while the write transistor of the memory cell 101_2 remains
off. The potential of the storage node SN of the memory cell 101_1 is +1
V.

[0074] Next, the potential of the write bit line 105_1 is set to +1 V or 0
V depending on data to be written. In either case, the potential of the
storage node SN of the memory cell 101_1 remains +1 V. However, a
potential difference between electrodes of the capacitor in the memory
cell 101_1 in accordance with the potential of the write bit line 105_1
is generated; therefore, charge based on the potential difference is held
in the first electrode of the capacitor. The potential of the write bit
line 105_2 connected to the memory cell 101_2 to which data is not
written remains +2 V (see FIG. 6B).

[0075] After that, the potential of the write word line 104 is reduced to
-1 V, so that the write transistor of the memory cell 101_1 is turned
off. The charge held in the first electrode of the capacitor of the
memory cell 101_1 is held in the storage node SN of the memory cell
101_1. This is the end of the writing operation.

[0076] Note that each of the potentials of the write bit lines 105_1 and
105_2 changes between 0 V and +2 V because data is written to other
memory cells connected to the write bit lines 105_1 and 105_2.
Accordingly, each of the potentials of the storage nodes SNs of the
memory cells 101_1 and 101_2 changes between 0 V and +3 V.

[0077] However, as is clear from the above description, there is a rule
because the potential of the write bit line 105 and the potential of the
source line 106 are closely linked in data writing. In other words, when
the potential of the source line 106 is +2 V, the potential of the write
bit line 105 is +2 V and the potential of the storage node SN is
accordingly +2 V or +3 V. In this case, as in the memory cell 101_1 in
FIG. 6c, the read transistor is off because the gate potential of the
read transistor is higher than or equal to the potential of the source or
the drain.

[0078] On the other hand, when the potential of the source line 106 is +1
V, the potential of the write bit line 105 is 0 V or +1 V and the
potential of the storage node SN is accordingly 0 V or +2 V. However, in
this case, since the potential of the source line 106 and the potential
of the read line 108 are equal (+1 V), current does not flow between the
source and the drain of the read transistor, as in the memory cell 101_2
in FIG. 6c.

[0079] Next, a method for reading data will be described. First, the
potentials of the write bit lines 105_1 and 105_2 are each set to +2 V,
and the potentials of the source lines 106_1 and 106_2 are each set to +2
V. The potentials of the storage nodes SNs of the memory cells 101_1 and
101_2 are each +2 V or +3 V depending on the written data.

[0080] The potential of the storage node SN is higher than or equal to +2
V when the potential of the source line 106 is +2 V, and 0 V or +1 V when
the potential of the source line 106 is +1 V. Accordingly, the read
transistors of the memory cells 101_1 and 101_2 are off (including the
state where current does not flow between a source and a drain which have
the same potential) regardless of the potentials of the storage nodes SNs
when the potential of the read line 108 is lower than or equal to +1 V.

[0081] Here, the potential of the source line 106 and that of the write
bit line 105 are each +2 V; therefore, the read transistors of the memory
cells 101_1 and 101_2 are off. The potential of the read line 108 is set
to 0 V, so that the read line 108 is brought into a floating state (see
FIG. 7A).

[0082] In Embodiment 1, the potentials of all the bit lines 105 need to be
once reduced to 0 V in order that the read line 108 is brought into a
floating state; however, such operation is not needed in this embodiment,
resulting in reduction in power consumption.

[0083] For example, if data does not need to be written to or read from a
memory cell connected to a bit line in a certain period, the power
consumption can be lowest when potentials of a write bit line and a
source line are each kept at +2 V.

[0084] In Embodiment 1, in order that the potential of the read line 108
is set to a certain potential (0 V), even a potential of a write bit line
connected to a memory cell on which rewriting or reading of data does not
need to be performed needs to be set to 0 V (or lower) once; thus,
unnecessary power is consumed.

[0085] In contrast, since the potential of the read line 108 can be set to
0 V even with the potential of the write bit line 105_2 kept at +2 V in
this embodiment, power consumption can be reduced.

[0086] Next, the potential of the write bit line 105_1 is set to 0 V and
the potential of the source line 106_1 is set to +1 V. The potential of
the storage node SN of the memory cell 101_1 is 0 V or +1 V. Accordingly,
the read transistor of the memory cell 101_1 is in a different state
depending on the potential of the storage node SN.

[0087] In the case where the potential of the storage node SN of the
memory cell 101_1 is +1 V, the read transistor is off; thus, the
potential of the read line 108 remains 0 V. On the other hand, in the
case where the potential of the storage node SN is 0 V, the potential of
the read line 108 is increased to +1 V. In other words, the potential of
the read line 108 is +1 V in the case where data "1" has been written
while the potential of the read line 108 is 0 V in the case where data
"0" has been written.

[0088] In contrast, the potentials of the write bit line 105_2 and the
source line 106_2 each remain +2 V. The potential of the storage node SN
of the memory cell 101_2 is +2 V or +3 V. Accordingly, the read
transistor of the memory cell 101_2 is off (see FIG. 7B).

[0089] Thus, data can be read. Note that data is not erased in the above
steps of data reading. The potential of the read line is set to +1 V
after data is read.

[0090] The reading operation is performed under the condition that the
potential of the source line 106_1 is +1 V and that the potential of the
read line 108 is 0 V in the above; however, the reading operation can
also be performed under the condition that the potential of the source
line 106_1 is 0 V and that the potential of the read line 108 is +1 V.
Such an example is described below.

[0091] At the beginning of the reading operation, the potentials of the
write bit line 105 and the source line 106 are each set to +2 V and the
potential of the read line 108 is set to 0 V. Then, the potential of the
read line 108 is set to +1 V. Further, the source line 106 is brought
into a floating state. At this time, the read transistors of the memory
cells 101_1 and 101_2 are off because the gate potential is higher than
or equal to the potential of the source or the drain in each of the read
transistors.

[0092] Next, the potentials of the bit line 105_1 and the source line
106_1 both connected to the memory cell 101_1 from which data is read are
each set to 0 V. At this time, the potential of the storage node SN of
the memory cell 101_1 is +1 V or 0 V depending on the written data.

[0093] In the case where the potential of the storage node SN is +1 V, the
read transistor of the memory cell 101_1 is off; thus, the potential of
the source line 106_1 remains 0 V. In contrast, in the case where the
potential of the storage node SN is 0 V, the read transistor of the
memory cell 101_1 is turned on; thus, the potential of the source line
106_1 is increased to +1 V (see FIG. 7c).

[0094] Thus, data can be read. Note that data is not erased in the above
steps of data reading. The potential of the read line is set to 0 V after
data is read.

Embodiment 3

[0095] In this embodiment, steps of manufacturing the semiconductor memory
device described in the above embodiment will be briefly described with
reference to FIGS. 8A and 8B, FIGS. 9A and 9B, and FIGS. 10A to 10C.
FIGS. 8A and 8B and FIGS. 9A and 9B are schematic cross-sectional views,
and FIGS. 10A to 10C are schematic views of some of components seen from
the above. Note that FIGS. 8A and 8B and FIGS. 9A and 9B are the
cross-sectional views taken along dashed-dotted lines A-B in FIGS. 10A to
10C. Note that a known semiconductor manufacturing technique or Patent
Document 2 can be referred to for the detail of some of the steps.

[0096] An element separation region 111 and the like are formed at a
substrate 110 formed using a semiconductor such as silicon, gallium
arsenide, gallium phosphide, or germanium. Further, read gates 112_1 and
112_2 which are gates of read transistors are formed, and impurity
regions 113_1 to 113_4 are formed.

[0097] The impurity regions 113_1 and 113_3 serve as the source lines
described in Embodiment 1 or 2. These regions are preferably formed in
parallel to a write bit line to be described later. In other words, these
regions preferably extend from the front in the depth direction in the
drawing.

[0098] In the case where the impurity regions 113_1 to 113_4 are used as
the source lines or the read lines, it is preferable that the resistance
thereof be low; therefore, a silicide layer is preferably provided on a
surface of the impurity regions 113_1 to 113_4 by a known self-aligned
silicide (salicide) technique or the like.

[0099] Further, after formation of a first interlayer insulator 115, first
connection electrodes 114_1 and 114_2 are formed. Then, the first
connection electrodes 114_1 and 114_2 are planarized by etching until top
surfaces of the read gates 112_1 and 112_2 are exposed. FIG. 10A is a
view at this stage, which is seen from the above. In FIG. 10A, the
element separation region 111, the read gate 112, the impurity region
113, and the first connection electrode 114 are shown.

[0100] Semiconductor layers 116_1 and 116_2 and a gate insulator 117
thereover are formed. A variety of semiconductors can be used as
semiconductors for the semiconductor layers 116_1 and 116_2. It is
preferable to use a semiconductor having a band gap of greater than or
equal to 2.5 eV and a carrier concentration of lower than or equal to
1014 cm-3. Therefore, it is preferable to use an oxide
semiconductor for the semiconductor layers.

[0101] An oxide semiconductor preferably contains at least indium (In) or
zinc (Zn). In particular, In and Zn are preferably contained. As a
stabilizer for reducing change in characteristics of a transistor formed
using the oxide semiconductor, the oxide semiconductor preferably
contains gallium (Ga) in addition to In and Zn. Tin (Sn) is preferably
contained as a stabilizer. Hafnium (Hf) is preferably contained as a
stabilizer. Aluminum (Al) is preferably contained as a stabilizer.

[0103] As the oxide semiconductor, for example, any of the following can
be used: indium oxide; tin oxide; zinc oxide; a two-component metal oxide
such as an In--Zn-based oxide, a Sn--Zn-based oxide, an Al--Zn-based
oxide, a Zn--Mg-based oxide, a Sn--Mg-based oxide, an In--Mg-based oxide,
or an In--Ga-based oxide; a three-component metal oxide such as a
Sn--Ga--Zn-based oxide, an Al--Ga--Zn-based oxide, a Sn--Al--Zn-based
oxide, an In--Ga--Zn-based oxide (also referred to as IGZO), an
In--Al--Zn-based oxide, an In--Sn--Zn-based oxide, an In--Hf--Zn-based
oxide, an In--La--Zn-based oxide, an In--Ce--Zn-based oxide, an
In--Pr--Zn-based oxide, an In--Nd--Zn-based oxide, an In--Sm--Zn-based
oxide, an In--Eu--Zn-based oxide, an In--Gd--Zn-based oxide, an
In--Tb--Zn-based oxide, an In--Dy--Zn-based oxide, an In--Ho--Zn-based
oxide, an In--Er--Zn-based oxide, an In--Tm--Zn-based oxide, an
In--Yb--Zn-based oxide, or an In--Lu--Zn-based oxide; and a
four-component metal oxide such as an In--Sn--Ga--Zn-based oxide, an
In--Hf--Ga--Zn-based oxide, an In--Al--Ga--Zn-based oxide, an
In--Sn--Al--Zn-based oxide, an In--Sn--Hf--Zn-based oxide, or an
In--Hf--Al--Zn-based oxide.

[0104] Note that here, for example, an "In--Ga--Zn-based oxide" means an
oxide containing In, Ga, and Zn as its main components and there is no
particular limitation on the ratio of In:Ga:Zn. The In--Ga--Zn-based
oxide may contain a metal element other than In, Ga, and Zn.

[0105] For example, an In--Ga--Zn-based oxide with an atomic ratio of
In:Ga:Zn=1:1:1 (=1/3:1/3:1/3) or In:Ga:Zn=2:2:1 (= : :1/5), or an oxide
with an atomic ratio close to the above atomic ratios can be used.
Alternatively, an In--Sn--Zn-based oxide with an atomic ratio of
In:Sn:Zn=1:1:1 (=1/3:1/3:1/3), In:Sn:Zn=2:1:3 (=1/3:1/6:1/2), or
In:Sn:Zn=2:1:5 (=1/4:1/8:5/8), or an oxide with an atomic ratio close to
the above atomic ratios may be used.

[0106] However, without limitation to the materials given above, a
material with an appropriate composition may be used depending on needed
semiconductor characteristics (e.g., mobility, threshold voltage, and
variation). In order to obtain the needed semiconductor characteristics,
it is preferable that the carrier density, the impurity concentration,
the defect density, the atomic ratio between a metal element and oxygen,
the interatomic distance, the density, and the like be set to appropriate
values. Patent Document 2 can be referred to for the detail.

[0107] Note that for example, the expression "the composition of an oxide
including In, Ga, and Zn at the atomic ratio, In:Ga:Zn=a:b:c (a+b+c=1),
is in the neighborhood of the composition of an oxide including In, Ga,
and Zn at the atomic ratio, In:Ga:Zn=A:B:C (A+B+C=1)" means that a, b,
and c satisfy the following relation:
(a-A)2+(b-B)2+(c-C)2≦r2, and r may be 0.05,
for example. The same applies to other oxides.

[0108] The oxide semiconductor may be either single crystal or
non-single-crystal. In the latter case, the oxide semiconductor may be
either amorphous or polycrystal. Further, the oxide semiconductor may
have either an amorphous structure including a portion having
crystallinity or a non-amorphous structure.

[0109] In an oxide semiconductor in an amorphous state, a flat surface can
be obtained with relative ease, so that when a transistor is manufactured
with the use of the oxide semiconductor, interface scattering can be
reduced, and relatively high mobility can be obtained with relative ease.

[0110] In an oxide semiconductor having crystallinity, defects in the bulk
can be further reduced and when a surface flatness is improved, mobility
higher than that of an oxide semiconductor in an amorphous state can be
obtained. In order to improve the surface flatness, the oxide
semiconductor is preferably formed on a flat surface. Specifically, it is
preferable that the oxide semiconductor be formed on a surface with an
average surface roughness (Ra) of 1 nm or less, preferably 0.3 nm or
less.

[0111] Here, the semiconductor layer 116_1 is in contact with the read
gate 112_1 and the first connection electrode 114_1, and the
semiconductor layer 116_2 is in contact with the read gate 112_2 and the
first connection electrode 114_2. In other words, the read gate 112_1
serves as a drain electrode of a first transistor including the
semiconductor layer 116_1 as a channel, the read gate 112_2 serves as a
drain electrode of a second transistor including the semiconductor layer
116_2 as a channel, the first connection electrode 114_1 serves as a
source of the first transistor, and the first connection electrode 114_2
serves as a source of the second transistor.

[0112] Further, a write word line 104_1 and a write word line 104_2 are
formed. It is effective in preventing short circuit between wirings to
form an etching stopper 118 of an insulating material over each of top
surfaces of the write word lines 104_1 and 104_2. Providing a sidewall on
a side surface of the write word line 104 is also effective in preventing
short circuit between wirings. Note that conductivity of the
semiconductor layer 116 may be selectively increased by addition of an
impurity with the use of the write word line 104 or the sidewall as a
mask. FIG. 10B is a view at this stage, which is seen from the above. The
semiconductor layer 116 and the write word line 104 are illustrated in
FIG. 10B.

[0113] A second interlayer insulator 120 is formed. Then, contact holes
reaching the semiconductor layers 116_1 and 116_2 are formed in the
second interlayer insulator 120, and second connection electrodes 119_1
to 119_4 are formed. Further, the source line 106 is formed over the
second interlayer insulator 120. FIG. 10c is a view at this stage, which
is seen from the above. The source line 106 is illustrated in FIG. 10c.
As is clear from FIG. 10c, the source line 106 intersects with the write
word line 104.

[0114] Third connection electrodes 121_1 and 121_2, capacitor electrodes
122_1 and 122_2, and the like are formed in a third interlayer insulator
123, and a write bit line 105 and the like are formed over the third
interlayer insulator 123. A known method for manufacturing a stacked
capacitor can be referred to for the manufacturing steps. The write bit
line 105 is formed in parallel to the source line 106.

[0115] Through the above steps, the memory cells 101_1 and 101_2 can be
formed. The memory cells 101_1 and 101_2 are connected to the same source
line. This application is based on Japanese Patent Application serial No.
2011-105132 filed with Japan Patent Office on May 10, 2011, the entire
contents of which are hereby incorporated by reference.