Message from the Chair

As I look back over the course of 2015, Accellera has enjoyed an exciting, productive year with many notable accomplishments:

We've added 12 new members this year — a warm welcome to our newest members Infineon, National Instruments, OneSpin, Vtool and XtremeEDA. We continue to grow our membership worldwide with 13 countries currently represented.

We are very proud to have delivered UVM 1.2 to the IEEE Standards Association for further standardization and ongoing maintenance.

Later this month we will be releasing an early UVM-SystemC Language Reference Manual (LRM) accompanied by a Proof-of-Concept (PoC) implementation for public review.

Our two additional Design & Verification Conferences (DVCon), DVCon India and DVCon Europe, had very successful sophomore events. We are excited about the growth and global reach of these annual events.

As we look toward 2016, there will be significant activity in many areas. As we continue to evolve the EDA and IP standards incubating in Accellera, the Portable Stimulus Working Group will be very active as it works diligently to define a Portable Test and Stimulus Standard. Accellera will also continue to work closely with the IEEE working groups to support those standards that have moved to the IEEE such as UVM (P1800.2), IP-XACT (IEEE Std. 1685-2014), and SystemVerilog (IEEE Std. 1800-2012).

As we close on another year I'd like to thank our members, and especially our Global Sponsors ARM, Cadence, Intel, Mentor Graphics and Synopsys, for helping to make 2015 a tremendous success.

All of us at Accellera would like to wish you a very happy holiday season!

Sincerely, Shishpal Rawat, Accellera Systems Initiative Chair

DVCon Europe 2015 a Great Success!

The second DVCon Europe, held last month in Munich, demonstrated significant growth over last year's inaugural event. There were 280 registered attendees from 105 companies, an increase of approximately 30%. The conference attracted 25 exhibitors, up from 19 last year.

Hans Adlkofer, Vice President of the Automotive System Group for Infineon Technologies, provided a well-received talk to a packed auditorium on the vision and reality of driverless cars, aligning to the conference theme of Safety Critical Automotive Design and Verification. A panel session titled "Functional Safety in Automotive" took the theme further and analyzed the impact of automotive standards on the industry at large.

A series of 16 tutorials and 36 papers and posters on subjects such as UVM-based Verification, SystemC System Level Verification, Safety-Critical Verification, Analog/Mixed-Signal Design and others provided a rich technical program for the attendees. The day was finished with a well-attended gala dinner at which sponsors Accellera and Synopsys discussed their latest advances. For more conference results, read the press release.

DVCon India 2015 Celebrates Record Growth

The second DVCon India attracted nearly 600 attendees, a record number that includes both exhibit-only and technical conference attendees. At a gala dinner, the conference celebrated the 10-year anniversary of SystemVerilog as well as the release of UVM 1.2 to the IEEE P1800.2 Working Group. Exhibitors included start-ups from India exhibiting for the first time. The conference was divided into two technical tracks: ESL and Design and Verification. The high number of valuable technical papers accepted by the Program Committee required running concurrent tracks for both paper and panel discussions.

Save the date! DVCon India 2016 will be held September 15-16 in Bangalore, Karnataka.

Looking Toward DVCon US 2016 to be Held February 29 to March 3

Mark your calendar for December 10th! DVCon US opens Early Bird registration and announces its advance program that day. The industry’s premier conference on design and verification will provide attendees with a highly technical selection of 39 papers, 12 tutorials and approximately 35 posters. The number of abstracts submitted are higher this year, and as a result we are excited to add a couple of new session areas to the program.

For you, our Accellera Newsletter readers, we have a sneak peek at the annual Accellera Day. On Monday, February 29, 2015 we will bring together technologies that you’ll be able to use immediately and those that will define the future. You’ll get new Tips and Tricks for UVM and advanced SVA verification as well as general approaches for formal analysis. Looking to the future, you’ll be the first to hear about the UVM changes coming in the IEEE standard and how to prepare for it, you’ll get an insider’s view into Portable Stimulus, and you’ll learn about the future of analog modeling. While these tutorials will be more than enough to feed your hunger for knowledge, tutorial attendees will also get lunch along with the presentation of Accellera’s annual Technical Excellence Award and a panel discussion on SystemC.

So mark your calendar for December 10th to be among the first to register for DVCon US. Visit www.dvcon.org for more information.

Technical Spotlight — UVM-SystemC Public Review

The SystemC Verification Working Group (VWG) will soon make available an early UVM-SystemC Language Reference Manual (LRM) accompanied by a Proof-of-Concept (PoC) implementation for public review. The purpose of this public review is to obtain feedback on the LRM and PoC distribution. The working group is looking for discrepancies versus the standard and simple install/documentation issues against the supported platforms. More details to be announced >

Technical Excellence Award — Call for Nominations

Accellera is now accepting nominations for its 2016 Technical Excellence Award. This annual award was established to recognize the important achievements of our working group members and their significant contributions to the development of Accellera standards. The award will be presented to the recipient at DVCon US 2016. Any member of an Accellera working group is eligible for the award. Nominations are due January 4, 2016. Interested in making a nomination? Contact your working group chair. Find out more about Accellera’s awards program and past recipients.

Watch Tutorials from DVCon US

With the recent addition of the tutorial "SystemVerilog Design: User Experience Defines Multi-Tool, Multi-Vendor Language Working Set," the complete set of technical tutorials from Accellera Day at the 2015 DVCon US is now available at videos.accellera.org. Additional tutorials from the series are:

UVM User’s Guide 1.2 Now Available

The UVM User’s Guide has been updated to align with the UVM 1.2 Class Reference. The User’s Guide describes a way to apply the UVM 1.2 Class Reference by offering a set of instructions to perform one or more specific verification tasks. The User’s Guide as well as the Class Reference is available here.