.I thought it would be good to share the results of some experiments hoglet did, using the xilinx tools to implement our OPC5 core with a small code cache and an 8 bit memory controller.

The overall lesson is that both the size and speed of an implementation can vary a lot depending on the tactics used to build it, and so the quick default synthesis result should not be used to rule out any particular idea as being too large or too slow, unless it is a long way off.

Dave used SmartExplorer to run 7 tactics for place and route, in combination with either Speed or Area tactics for synthesis, in combination with two different clock speed targets. (Sometimes a mild overconstraint on timing can give better results.)

There are more choices possible for synthesis, and more for smartexplorer too. It's relatively easy to get smartexplorer to run 4 P&R jobs in parallel, which helps a lot on a modern multicore computer.

From memory, build times are a couple of minutes for each pass. So normally smartexplorer would be about 14 mins, but using 4 threads it's down below 5 mins.

I'm not too surprised that the fastest are the largest, because it allows for more redundancy - instead of one adder and some muxing, you have two dedicated adders. It's interesting that the not-quite-so-fast are sometimes a reasonable size.

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