The Frontier of Electronics Research

by Michael Mayberry

Monday, May 13, 2013 | Toronto, Ontario, Canada

The current era of semiconductor research is heavily dependent on the incorporation of new materials into structures measured in nanometers. For the next decade, these trends are expected to continue and will suffice to improve the traditional metrics of performance-power and costs. Nevertheless there are inflection points coming, both for technology and for products which will require advanced research to deliver solutions in time. Traditional computation is morphing and novel technologies under investigation will require a more interdisciplinary approach. There are many choices to be made but a rich future lies ahead of us.

Michael C. Mayberry is director of Components Research which is the research arm for the Technology and Manufacturing Group of Intel. He is responsible for ongoing research to enable future process options for Intel's technology development organizations. This scope includes internal research, external university research, and other external collaborations.

Since joining Intel in 1984 as a process integration engineer, Mayberry has held a variety of positions. As part of the California Technology Development team, he developed EPROM, flash and logic wafer fabrication processes. In 1994 he moved to Sort Test Technology Development, most recently as director, responsible for roadmaps and development of test processes for Intel microprocessors. In 2005, he moved to Components Research.

Mayberry received his Ph.D. in physical chemistry from the University of California, Berkeley in 1983 and his bachelor's degree in chemistry and mathematics from Midland College in 1978.

Summary of the Lecture

As Corporate VP of the Technology and Manufacturing Group and Director of Components Research at Intel, Michael is responsible for coordinating research to enable future process options for Intelís technology development units. As part of Intelís California Technology Development team he was involved in EPROM, flash, and logic wafer fabrication innovation. Mayberry received his PhD in physical chemistry from the University of California, Berkeley in 1983.

The entire talk was sprinkled with interesting quotes from Arthur C. Clark.

Beyond the 22 nm node he noted that carrier scattering from grains and sidewalls becomes dominant. Dr. Mayberry pointed out that interconnects become the limiter in device performance. Thus current research on aspects related to new interconnect materials (e.g., carbon nanotubes, CuAu alloys) were discussed along with the cost limitations associated with the use of elements such as gold. To continue to deliver the expected gains beyond the 22 nm node, Dr. Mayberry noted that several things need to happen congruently. First, the leakage current has to be managed, which means a change in structure to multi-gate configurations; and managing tunneling currents and scattering would be another challenge.

The talk then turned futuristic, looking at possibilities of shrinking feature sizes down to 10 nm and then even to 1.5 nm. At this juncture we reach the space of chemistry where you build individual molecules. The 10 nm-5 nm roadmap would involve further advances in lithography, materials, interconnects, and more. At the end of scaling, which Dr. Mayberry predicted would occur in about 10 years, one could even envision a post-Si nanoelectronics future. The speaker alluded to a device future beyond CMOS and into the realm of spintronics, and the search for the next switch. He then addressed non-Boolean logic possibilities and underlined that fabricating a spintronic circuit would require precise metrology and new strategies for measuring logic states.