Can you explain more about SXGA standard (1280 × 1024 pixels) TFT-LCD ?

Question:

The uPD160061A Data Sheet says that this driver is applicable to SXGA-standard (1280 × 1024 pixels) TFT-LCD panels.
Does this mean that 60 frames can be displayed in one second even when VDD1 = 2.3 V and the data transfer clock is at 40 MHz?

Answer:

Yes.
Because two pixels (× 6 bits × 3 (RGB)) can be input in one clock, the number of display clocks of one horizontal period is 1280/2 = 640.
It takes at least five clocks after inputting data of one horizontal period has been completed until the next data can be input (until STB rises and the start pulse rises).
Therefore, the minimum data transfer clock frequency is (640 + 5) × 1024 × 60 = 39.6 (MHz).