We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Firefox,
Internet Explorer 11,
Safari. Thank you!

AR# 3258

M1 TRACE: Internal-- Slow Exceptions are not always honored if they overlap

Description

Description:

In some circumstances, users attempting to create more than one slow exception off a given timespec will find that one of them is not honored. A "slow exception" is a timing constraint that specifies slower (or different) timing for a subset of a given timing constraint (i.e., if you have a PERIOD constraint that applies to flops A,B,C,D,E, and

you want the path B->C to be slower than the general PERIOD constraint, then you could add a higher-priority FROM:TO constraint that would control only the B->C path).

This diagram represents three constraints; two of which are supposed to be slow exeptions of the PERIOD constraint. Notice each slow exception will cover a seperate subset of the PERIOD constraint, with no overlap. This should not cause problems.

-----------------------------------------------

| PERIOD constraint |

| |

| /----------------\ /----------------\ |

| | slow exception | | slow exception | |

| | #1 | | #2 | |

| | | | | |

| \----------------/ \----------------/ |

|_____________________________________________|

If the two slow exceptions overlap, then a problem can occur. If slow exception #1 appears in the PCF followed by slow exception #2, then the paths supposedly covered by slow exception #2 will not be removed from the PERIOD constraint

-----------------------------------------------

| PERIOD constraint |

| |

| /---------------------\ |

| | slow exception | |

| | #1 | |

| | /------------------------\ |

| | |\\\\\\\| slow exception | |

| | |\\\\\\\| #2 | |

| \-------------|-------/ | |

| | ^ | |

| \---|--------------------/ |

|______________________|______________________|

|

Intersection!

The circumstances in which this will occur is not easy to identify in a given design, but the following will discuss the cause in the context of an example.

Suppose a design has a PERIOD constraint, and two subsequent FROM:TO specs, where each FROM:TO spec is a slow exception.

NET myclock PERIOD = 50 ;

TIMEGRP "ioregs" = FFS(a) : FFS(b) ;

TIMESPEC ts02 = FROM "ioregs" TO FFS 75 ;

TIMEGRP "myregs" = FFS(a) : FFS(b) : FFS(c) ;

TIMESPEC ts03 = FROM "myregs" TO FFS 100 ;

Let us suppose that the timegrp FFS contains the register bels "a", "b", "c", "d", and "e". Let us also suppose that there are paths from "a", "b", "c" and "d" to register "e", and that the circuit described by the PERIOD constraint looks like:

a

\

b-\

--e

c-/

/

d

Here the set of paths described by the period specification is:

{ (a,e), (b,e), (c,e), (d,e) }

Okay, now consider the specification ts02, which specifies a subset of the period specification (ts01) covering the paths from "a" and "b" to "e":

a

\

b-\

--e

Here the set of paths described by the ts02 is:

{ (a,e), (b,e) }

Now consider the maxdelay specification ts03, which is also a subset of the period specification (ts01) covering the paths from "a", "b", and "c" to "e":

a

\

b-\

--e

c-/

Here the set of paths described by the ts03 is:

{ (a,e), (b,e), (c,e) }

The problem is that the path (c,e) described in the maxdelay specification ts03 is not being removed from the period specification (ts01), and therefore the requested slow exception is not being honored. This is a reasonable request, since the specification ts03 asks that the path from "c" to "e" be relaxed.

The problem occurs because the previous specification ts02 has actually modified the period specification (ts01) before ts03 is checked against ts01. First the paths specified in ts02 are removed from ts01, yielding the following circuit:

--e

c-/

/

d

with the path set { (c,e), (d,e) }. Subsequently ts03 is checked against ts01 for slow exceptions, and unfortunately ts03 specifies paths (a,e) and (b,e) which are no longer in ts01! Because of this, ts03 is no longer a subset of ts01 (nor is it a superset), and the slow execption is not honored. There is an intersection between the two sets (c,e), but the Timing Wizard does not operate on circuit intersections (only subsets).

Solution

There is no simple workaround. The timespecs would have to be adjusted so there is no overlap between the slow exceptions.