Hard to believe but the first full year of EDA360 Insider is now put to bed. I wrote more than 500 posts and several proved extremely popular, with thousands of readers. With so many posts during the year (more than one per day, on average), it’s possible you might have missed one or two important ones. So here’s a baker’s dozen of the top posts. All but one got more than 1000 readers:

Today, in the middle of the announcement onslaught from wireless communications vendors coming out of the Mobile World Congress (MWC) in Barcelona, Agilent rolled out a blockbuster announcement of its own that’s not part of the MWC milieu: the InfiniiVision 2000 and 3000 X-Series of low-end, digital sampling oscilloscopes (DSOs). There are no fewer than 26 DSO models in these two new Agilent DSO families, selling for $1230 to $11,590. That’s a huge product range covering a broad set of features that sells for a wide range of prices, all based essentially on one hardware DSO platform. Now EDA360 Insider isn’t a blog about DSOs, but it’s very much a blog about the design of electronic products and Agilent’s marketing team has done such a good job of getting coverage for this announcement that we can get an excellent feel for how this product was designed to compete nose to nose with established vendors in the low-end DSO space, where Agilent admits it had not had much of a presence.

Want an advanced course in low-power design alternatives for advanced-process SoC design? Xilinx wants you to have one… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This White Paper is an authoritative guide to the many ways you can cut static and dynamic power in nearly any chip design that will be manufactured at advanced process nodes like 28nm or 20nm. This White Paper is so comprehensive that I simply cannot summarize it in one blog entry, so I plan to chip it up into relevant pieces and will discuss the topics over several blog entries. Frankly, I cannot believe that Xilinx is giving this much hard-won information away, for free no less, so I strongly recommend that you go a get a copy of this White Paper before Xilinx CEO Moshe Gavrielov comes to his senses.

Last month, STMicroelectronics introduced the latest in its line of SPEAr (Structured Processor Enhanced Architecture) application processors and Microprocessor Report has just published a very interesting article about the new products (paid subscription required). The SPEAr-1300 series is based on two 600MHz ARM Cortex-A9 microprocessor cores (upgraded from the 333MHz ARM9 cores used in the earlier SPEAr parts). Each ARM processor core in the SPEAr-1300 embedded application processor has two 32-kbyte L1 caches and the two processor cores share a 512-kbyte L2 cache. The SPEAr-1300 application processor also includes a number of hard-core IP peripherals including a Gigabit Ethernet port, a PCIe/SATA port, and two USB 2.0 ports. In addition, there are 1.3 million uncommitted ASIC gates that can be configured for specific applications and, in a throwback to the disco days of the 1980s, these ASIC gates are configured as a metal-defined gate array so the wafers can be stockpiled awaiting final metal designs.

Last week, I quoted Ann Steffora Mutschler’s article about the information that Micron has revealed about it’s 3D Hybrid Memory Cube. Now that I’ve got the paper Micron presented at last week’s Hot Chips 23 conference, I’d like to explain how the company plans to explode memory bandwidth using this 3D design approach. You see, there’s been a DRAM-bandwidth bottleneck building for a long, long time. DRAMs have gotten far bigger with huge parallel arrays of DRAM cells on chip, but DRAMs are essentially still limited to the bandwidth supported by their package. That’s why we’ve gone from asynchronous DRAMs with RAS and CAS signals to more structured DRAMs with synchronous interfaces that support ever-increasing memory bandwidths.

Want to know how to get a serious calculator collector salivating? Bring back a favorite design from 1982, re-engineer the design so that the old code runs on top of an emulation layer that allows the use of a “modern” 32-bit RISC processor (which makes some functions run 100x faster), and then price the new product at half the going rate for the old ones selling on eBay. Hoo boy! You’ll get a sellout.

Earlier this month, Intel announced that it will be using Tri-Gate transistors (FinFETs) to build microprocessors at the 22nm process node. The microprocessor is code-named “Ivy Bridge.” It will be a 22nm version of the company’s Sandy Bridge processor and will be the first high-volume chip to use such “3D” transistors. Intel is calling this FET structure the “Tri-Gate” transistor because the gate wraps three-quarters of the way around an elevated gate. Others have called this structure a FinFET for several years, but FinFETs haven’t gone into production before this.

No matter how many times I’ve toured a fab in a bunny suit, I continue to be fascinated with the advances in mass production that allow our industry to ruthlessly drive cost/performance down and to the right over time in accordance with Moore’s Law. Combine these advances with a well-shot video and some unobjectionable, easy-listening rock and roll music and you get Lexar’s six-minute video of the process from the Micron fabs in Idaho that make Lexar’s chips to the dicing, packaging, and testing operations in Asia. It’s only six minutes, but fun to watch.

DDR4 SDRAM is coming. JEDEC may not have released the final spec yet but Samsung made the first DDR4 memory chip announcement in January of this year—a 2133MHz device built with a 30nm process technology—and Hynix followed suit in April by announcing a 2400MHz device, also built with a 30nm process technology. Cadence announced a complete DDR4 IP package for SoC designers the same month. (See: “Memory to processors: ‘Without me, you’re nothing.’ DDR4 is on the way.”) Nanya “sort of announced” a DDR4 memory device when it appeared in their most recent quarterly report. So there’s visible momentum for the DDR4 specification already even if JEDEC has yet to roll it out.

One of the most anticipated product rollouts of the year is already happening this week—the Verizon CDMA version of the Apple iPhone—and two organizations have already done us the great favor of tearing a sample phone apart and enumerating the significant chips found inside. The two organizations are UBM TechInsights (affiliated with EE Times) and ifixit.com. And you know what? They seem to have torn apart slightly different versions.

Intel announced in early May that it would be using “Tri-Gate” FETs to build microprocessors at the 22nm node. (See the previous EDA360 Insider post “3D Thursday: Intel and FinFETs (Tri-Gate transistors)—a different kind of 3D”). Intel’s Tri-Gate transistor structures closely resemble what the rest of the semiconductor industry calls “FinFETs” and I was fascinated by the topic while listening to a crystal-clear talk about FinFETs given last Friday at Cadence’s Building 10 auditorium by Chenming Hu, TSMC Distinguished Chair Professor of Microelectronics at University of California at Berkeley. Hu coined the term FinFET ten years ago when he and his team built the first FinFETs and described them in a 1999 IEDM paper. FinFETs combat short-channel leakage effects that are poisoning bulk planar FET (aka “the good old MOSFET”) performance in advanced-process technology nodes—which is why they’re getting so much attention right now—but there is a competitor to FinFETs called UTBSOI (Ultra Thin Body Silicon on Insulator). Hu’s team developed the first UTBSOI FETs under the same 1996 DARPA contract that funded the first FinFET developments. For more of the story, read on.

Apple introduced the iPad 2 yesterday and revealed that there was a new processor inside, the A5, to power the iPad 2’s new features including the two cameras and the FaceTime video chat feature. The A5 processor is the successor to the A4 found in the original iPad and the latest incarnations of Apple’s iPhone. We don’t yet know much about Apple’s A5 processor, but there are some things we do know.

After telegraphing its punch at ESC last spring, Xilinx has now introduced the first four members of its EPP product line, which is based on a dual-core ARM Cortex-A9 processor complex, and has named them Zynq to differentiate them from the company’s FPGAs. (See “Xilinx redefines the high-end microcontroller with its ARM-based Extensible Processing Platform – Part 1” and “Xilinx redefines the high-end microcontroller with its ARM-based Extensible Processing Platform – Case Studies – Part 2”.) Two of the four Zynq family members are designed for low-power applications and the other two emphasize performance over power. “What’s an EPP?” you might ask. It’s an “Extensible Processing Platform,” a new IC category Xilinx hopes to create. Think of an EPP as an embedded processor with an attached FPGA fabric. “Haven’t they tried this before?” you’re now asking. Yes, they have. This time, the difference is that Xilinx is emphasizing the “processor” aspect of the device over the FPGA aspect—and you can expect that change in emphasis to make all the difference…

After weeks of teasing, ARM unveiled a pile of technical details including pipeline details today at the ARM Technology conference in Santa Clara about its new flagship multiple-processor core called the ARM Cortex-A15 MPCore. Clearly aimed at high-end applications up to and including servers and networking gear, the ARM Cortex-A15 spans a wide performance range, as you can see in this graph…

One Response to The top EDA360 Insider blogs of 2011. A Baker’s Dozen in case you missed them

Steve, Your blog posts have the unique knack of disseminating technical information in a fun-to-read manner. I really enjoyed reading your blog in 2011 and look forward to actively following it in 2012. Happy new year!

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About the author:

Steve Leibson has appeared on television with Leonard Nimoy (Star Trek's Mr. Spock), however he's not a TV star (although he's always open to offers). He is the Cadence EDA360 Evangelist and a Marketing Director at Cadence Design Systems, the leading EDA vendor for system and chip-level design tools, design IP and IP design platforms, and verification IP. Steve’s written some of the key books about IP-based SOC design including “Designing SOCs with Configured Cores,” published in 2006 and “Engineering the Complex SOC,” co-authored with Dr. Chris Rowen and published in 2004. An experienced design engineer, Steve has been evangelizing advanced, IP-centric SOC design since 2001.