CMPXCHG16B. CMPXCHG16B allows for atomic operations on 128-bit double quadword (or oword) data types. This is useful for high resolution counters that could be updated by multiple processors (or cores). Without CMPXCHG16B the only way to perform such an operation is by using a critical section.

Streaming SIMD Extentions 4. Introduced with “Nehalem” processor in 2008. Also known as “Nehalem New Instructions (NNI)“

sse4_1

Streaming SIMD Extentions 4.1

sse4_2

Streaming SIMD Extentions 4.2

x2apic

x2APIC

movbe

MOVBE instruction

popcnt

POPCNT instruction (Hamming weight, i.e. bit count)

tsc_deadline_timer

Tsc deadline timer

aes

AES instructions: AES-NI

xsave

XSAVE/XRSTOR/XSETBV/XGETBV

avx

Advanced Vector Extensions

f16c

16-bit fp conversions (CVT16)

rdrand

The RDRAND instruction (hardware random number generator)

hypervisor

Running on a hypervisor

VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001

rng

RNG present (xstore)

rng_en

RNG enabled

ace

on-CPU crypto (xcrypt)

ace_en

on-CPU crypto enabled

ace2

Advanced Cryptography Engine v2

ace2_en

ACE v2 enabled

phe

PadLock Hash Engine

phe_en

PHE enabled

pmm

PadLock Montgomery Multiplier

pmm_en

PMM enabled

Intel-defined CPU features, CPUID level 0x00000007:0 (ebx)

Flag

Description

fsgsbase

{RD/WR}{FS/GS}BASE instructions

bmi1

1st group bit manipulation extensions

hle

Hardware Lock Elision

avx2

AVX2 instructions

smep

Supervisor Mode Execution Protection

bmi2

2nd group bit manipulation extensions

erms

Enhanced REP MOVSB/STOSB

invpcid

Invalidate Processor Context ID

rtm

Restricted Transactional Memory

Intel-defined CPU features, CPUID level 0x00000001 (edx)

Flag

Description

fpu

Onboard FPU (floating point support)

vme

Virtual Mode Extensions (8086 mode)

de

Debugging Extensions (CR4.DE)

pse

Page Size Extensions (4MB pages)

tsc

Time Stamp Counter (RDTSC)

msr

Model-Specific Registers (RDMSR, WRMSR)

pae

Physical Address Extensions (support for more than 4GB of RAM). PAE is the added ability of the IA32 processor to address more than 4 GB of physical memory using Intel’s 36bit page addresses instead of the standard 32bit page addresses to access a total of 64GB of RAM. Also supported by many AMD chips.

mce

Machine Check Exception

cx8

CMPXCHG8 instruction (64-bit compare-and-swap). Compare and exchange 8 bytes. Also known as F00F, which is an abbreviation of the hexadecimal encoding of an instruction that exhibits a design flaw in the majority of older Intel Pentium CPU.