JavaScript is disabled for your browser. Some features of this site may not work without it.

A superconducting software defined radio frontend with application to the Square Kilometre Array

Volkmann, Mark Hans (2013-12)

Thesis (PhD)-- Stellenbosch University, 2013.

Thesis

ENGLISH ABSTRACT: Superconducting electronics can make the Square Kilometre Array (SKA) a
better instrument. The largest radio telescope in the world will consist of
several arrays, the largest of which, consisting of more than 3000 dishes, will
be situated primarily in South Africa. The ambitions of the SKA are grand
and their realisation requires technology that does not exist today.
Current plans see signals in the band of interest ampli ed, channelised,
mixed down and then digitised. An all-digital frontend could simplify receiver
structure and improve its performance. Semiconductor (analog-to-digital converters)
ADCs continue to make great progress and will likely nd applications
in the SKA, but superconductor ADCs bene t from higher clock speeds
and quantum accurate quantisation. We propose a superconducting softwarede
ned radio frontend.
The key component of such a frontend is a superconducting
ash ADC.
We show that employing such an ADC, even a small- to moderately-sized one,
will signi cantly improve the instantaneous bandwidth observable by the SKA,
yet retain adequate signal-to-noise ratio so as to achieve a net improvement
in sensitivity. This improvement could approach factor 2 when compared to
conventional technologies (at least for continuum observations). We analyse
key components of such an ADC analytically, numerically and experimentally
and conclude that fabrication of such an ADC for SKA purposes is certainly
possible and useful.
Simultaneously, we address the power requirements of high-performance
computing (HPC). HPC on a hitherto unprecedented scale is a necessity for
processing the vast raw data output of the SKA. Utilising the ultra-low-energy
switching events of superconducting switches (certain Josephson junctions),
we develop rst demonstrators of the promising eSFQ logic family, achieving
experimentally veri ed shift-registers and deserialisers with sub-aJ/bit energy requirements. We also propose and show by simulation how to expand the
applicability of the eSFQ design concept to arbitrary (unclocked) gates.