MoSys said it took less than six months from the time it successfully demonstrated the 1T-SRAM technology in silicon for TSMC's 0.25-micron standard logic process. MoSys plans to move aggressively to 0.15-micron standard logic processes.

"Embedded memory is the most pervasive silicon intellectual-property block on our customers' designs and has the largest economic and performance impact," said Roger Fisher, TSMC's senior director of strategic marketing. " We are very encouraged by this progress in making 1T-SRAM technology available."

"The 1T-SRAM silicon validation data provides additional assurance for its worldwide semiconductor and system customers," added Mark-Eric Jones, vice president and general manager of intellectual property at MoSys.

With 1T-SRAM memories, foundry customers can integrate multi-megabit blocks of high-performance, high-density memory into their system-on-chip (SoC) designs. 1T-SRAM macros are available to be integrated in TSMC's 0.25- and 0.18-micron standard logic processes.

In a related announcement today, MoSys said that NEC Corp. of Tokyo has licensed the 1T-SRAM technology (see today's story ).