Fast algorithms for high-speed divider design in finite fields GF(2m) are very crucial
in applications like cryptosystems. In this paper, we reformulated the conventional iterative
division algorithm by changing the pre-defined variable and then updating its initial value
accordingly. The reformulated division algorithm allows a restructuring of the divider architecture
to further improve its operating speed without increasing latency or area cost.
Using the proposed fast algorithm, we developed two high-speed iterative dividers based
on the semi-systolic and bit-serial systolic architectures. Analytical results show that the
cost of the initial value update and variable transformation in the reformulated algorithm is
almost negligible in the hardware implementation. Our divider designs improve the critical
path delay. Compared with related divider designs, the proposed designs have time and
area advantages.

Received October 6, 2009; revised February 26, 2010; accepted April 20, 2010.
Communicated by Chung-Ping Chung.
* This work was supported in part by the National Science Council of Taiwan, R.O.C. under contract No. NSC
96-2220-E-006-008.