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TECHNICAL LIBRARY

Modern integrated circuit technology has arrived
at a point where parasitic effects are simply no longer negligible.
IC designers start spending more time on parasitics modeling than
on the actual circuit design. Among the most important parasitic
effects limiting the chip performance are interconnect related problems
like extensive signal delays and crosstalk.

In order to model interconnect layout information
is absolutely necessary. Resistances can be extracted fairly accurately
by "counting squares", i.e. summing up the total mask
area of a conductor and multiplying this with a specific resistance.
For capacitance extraction a model of the 3D geometry has to be
derived. After the extraction of the interconnect parameters the
original netlist has to be back-annotated in order to allow SPICE
modeling under the influence of the interconnect parasitics.

Traditional Interconnect Modeling Approaches

The simplest model for an approximation of the
3D structure is shown in Figure 1. It splits the layout in very
small pieces that can be approximated with fast empirical formulas
[1,2,3]. These simple pieces are then patched together using heuristic
algorithms. The advantage of methods like the one described is that
they can handle complete IC's in a reasonable amount of time. The
main disadvantage becomes obvious when shrinking device dimensions
are considered. While the patching error stays constant, the range
of validity of the formulas is shrinking. For today's 0.35 mm technologies
the error can easily be in the order of 100%.

Figure 1. Approximation of true capacitances by empirical formulas
for C1-C5. Formulas are parameterized only by geometrical constants
like w1, w2, w3 and h1, h2.

Another approach is based on an explicit discretization of
the 3D geometries. Such as the simple cubic structures such as those
shown in Figure 2a. The capacitance between these structures is
then typically modeled using approximate boundary element methods[4].
Obviously, this is not an accurate description of the true 3D geometries.

Figure 2. Different order approximation of 3D interconnect structures.
a) is a first order cubic approach, b) more rigorous, but only
c) is correct.

A more accurate approximation is shown in Figure
2b. The Figure has been generated by using a solid modeling approach.
In [5] the approximations shown in Figure 2a and 2b were compared
and a capacitance error of 30% was reported. The structure used
here is assuming a 0.35 mm technology.

However none of the traditional approaches is
able to model geometries such as the one shown in Figure 2c with
a vertical variation of the metalization. This figure was generated
with SILVACO's 3D Back-End Process Simulation approach.

3D Back-End Process Simulation

The conclusion has to be that for accurate interconnect
parasitics modeling true 3D process simulation is mandatory. SILVACO's
3D Back-End Process Simulator, HIPEX, generates fully automatically
3D structures from arbitrary layout information. For a given layout
it models lithography, deposition and etching process steps with
precise physical models. The discretization is done by tetrahedra
to enable the generation of arbitrary 3D structures.

As a next step HIPEX provides a 3D field solver
for extracting the parasitic information. This field solver is based
on finite element techniques. Experiments with boundary element
methods for the resulting triangular surface grids have been disappointingly
slow. In order to speed up the simulation further, SILVACO is currently
parallelizing the field solver using domain decomposition methods.

As output HIPEX provides an equivalent SPICE netlist
of the interconnect parasitics. If a netlist of the active devices
is provided, it is also back-annotated.

Figures 3a-3f show an example of a HIPEX 3D Back-End
Process Simulation. Figure 3a shows the layout of a sample cell.
Oxide and Polysilicon are deposited and the photoresist is structured
(Figure 3b). Figure 3c shows the structure after etching of the
polysilicon. After oxide and aluminum deposit (Figures 3d and 3e)
the next layer of photoresist is defined (Figure 3f).

Cell Level Parasitics Extraction

Based on this 3D Back-End Process Simulation SILVACO
has developed a new parasitic extraction methodology. This new methodology
characterizes the interconnect parasitics at the cell level by solving
the complete cell numerically. This way all patching is avoided
and the most accurate solution obtained. The cell characterization
can be performed by cell library vendors as well as internal cell
characterization groups. This characterization will be based on
technology files provided by the Wafer Fab. The chip level integration
of these accurate cell parasitics is done with major EDA vendors.

An example of the cell level parasitics approach
is shown in Figures 4a-4d. The schematics of this XNOR cell is shown
in Figure 4a and the layout in Figure 4b. Figure 4c shows the complete
3D process simulation result. The oxide has been removed for better
visibility. Color coding has been done by conductor. In Figure 4d
some of the equivalent RC models for the ground coupling networks
are presented.

Figure 3. 3D Back-End Process simulation example.

The user specifies an error tolerance for the
final capacitance. HIPEX then adaptively meshes the structure to
ensure consistent results. For a 5% tolerance the structure in Figure
4c uses only 1500 tetrahedra. The complete simulation takes approximately
10 minutes on a SPARC20.

Figure 4. Cell level parasitics extraction for an XNOR cell.

Conclusion

As shown above an accurate solution to the Interconnect
problem must be technology based. SILVACO has developed a novel
3D Back-End Process Simulation based parasitics extraction methodology.
This method supports all common layout and schematics formats through
an interface to MaskViews. The first release of HIPEX is planned
for Q1 1997.