Selective Huffman coding has recently been proposed for efficient test- data compression with low hardware overhead. In this paper, we show that the already proposed encoding scheme is not optimal… (More)

Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well-suited for VLSI implementations. A novel framework is introduced, which allows the design of… (More)

ÐA novel parallel-prefix architecture for high speed modulo 2 ÿ 1 adders is presented. The proposed architecture is based on the idea of recirculating the generate and propagate signals, instead of… (More)

Modulo 2/sup n/+1 adders find great applicability in several applications including RNS implementations and cryptography. In this paper, we present two novel architectures for designing modulo 2/sup… (More)

In this work, we propose a new algorithm for designing diminished-1 modulo 2/sup n/+1multipliers. The implementation of the proposed algorithm requires n + 3 partial products that are reduced by a… (More)

In this paper, we present new design methods for modulo 2 1 adders. We use the same select-prefix addition block for both modulo 2 1 and diminished-one modulo 2 þ 1 adder design. VLSI implementations… (More)