Liberate is an ultra-fast standard cell and I/O library creator. Altos explained that it generates electrical cell views for timing, power and signal integrity including advanced current source models (CCS and ECSM). It uses an “inside view” approach where each cell undergoes a pre-characterization circuit analysis that determines all the necessary stimulus and internal logic states to ensure a complete, accurate and highly efficient characterization of that cell.

Liberate supports complex cells including those required for low power design such as state retention flip-flops, level shifters, power switches and MTCMOS cells with sleep modes, Altos said.

“We are using Liberate to fully re-characterize the TSMC 65 nm cell library and to create consistent library views for our internally designed IP,” stated Samir Mitra, VP of Corporate Development for MoSys. “We are pleased with the performance and ease-of-use we’ve experienced with Liberate, especially in automatically modeling our complex, high-speed I/Os.”