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AR# 30520

LogiCORE RapidIO - How do I move MGT/GTP/GTX locations of the SRIO Core?

Description

This Answer Record describes how you can swap the lanes in the MGT/GTP/GTX tiles to ease the board layout or to fix an inadvertently swapped board layout. The example below uses SRIO v4.3 in x4 configuration and assumes the lane swapping is necessary in both TILE0 and TILE1.

Solution

================= To SWAP Lanes Within Tiles ==============

To swap the lanes in GTP_DUAL, you must swap the attributes in each of the GTP_DUAL instantiations. You must modify the following two files:

- rocketio_wrapper.v

- gtp_wrapper file

Specifically, you must swap each of the "0" attributes and ports with "1" for each of the GTP_DUAL instantiations. Most attributes are the same for both, but some of them around channel bonding are not, and must be swapped. For example, CHAN_BOND_MODE must be changed to make sure that Lane 0 is the channel bond master. All of the ports must be swapped. Not only does this affect the channel bonding logic, but also how the interface from the core to the GTP is constructed.

1. Open "rocketio_wrapper_v5_4x.v" file in the text editor, and go to the "gtp_wrapper" section.

2. Swap ALL the lane #s for each tile in the gtp_wrapper instantiation. For example, in the TILE0 section of the gtp_wrapper instantiation...

the following:

.TILE0_RXCHARISK0_OUT (RXCHARISK2_swap[1:0]),

.TILE0_RXCHARISK1_OUT (RXCHARISK3_swap[1:0]),

becomes:

.TILE0_RXCHARISK1_OUT (RXCHARISK2_swap[1:0]),

.TILE0_RXCHARISK0_OUT (RXCHARISK3_swap[1:0]),

If necessary, repeat this for other ports and attributes for TILE 0 and TILE1.

3. Open the "gtp_wrapper.v file" in the text editor.

4. Swap the numbers on the TILE_CHAN_BOND attributes...

the following:

.TILE_CHAN_BOND_MODE_0 ("MASTER"),

.TILE_CHAN_BOND_LEVEL_0 (2),

.TILE_CHAN_BOND_MODE_1 ("SLAVE"),

.TILE_CHAN_BOND_LEVEL_1 (1)

becomes:

.TILE_CHAN_BOND_MODE_1 ("MASTER"),

.TILE_CHAN_BOND_LEVEL_1 (2),

.TILE_CHAN_BOND_MODE_0 ("SLAVE"),

.TILE_CHAN_BOND_LEVEL_0 (1)

5. Re-connect the channel bonding chain. For the TILE in which you have swapped the Master and Slave attribute...

the following:

.RXCHBONDI0_IN (tied_to_ground_vec_i[2:0]),

.RXCHBONDI1_IN (tile1_rxchbondo0_i),

.RXCHBONDO0_OUT (tile1_rxchbondo0_i),

.RXCHBONDO1_OUT (tile1_rxchbondo1_i),

becomes:

.RXCHBONDI0_IN (tile1_rxchbondo0_i),

.RXCHBONDI1_IN (tied_to_ground_vec_i[2:0]),

.RXCHBONDO0_OUT (tile1_rxchbondo1_i),

.RXCHBONDO1_OUT (tile1_rxchbondo0_i),

To verify the modifications, run functional simulation and check for the following: