How do you know when your IC design is done? When can you declare verification victory? These are the questions thatcoverage is supposed to help with. When your verification has covered the entire circuit, for lack of a more precise way of articulating it, then you’re done. (At least, with that part of the … Read More → "Formal and Simulation Covered Together"

In this week’s episode of Fish Fry, we investigate the changing role of NAND flash in safety-based systems. Dave Hughes (CEO – HCC Embedded) joins us to discuss HCC’s “Safety Element out of Context” embedded software approach and how HCC helping engineers better use NAND flash in safety systems. Also this week, we give everyone another chance to win a “Hitchhiker’s Guide … Read More → "When Safety is King, NAND Reigns Supreme"

Processors and FPGAs go together like chocolate and peanut butter, but it took a few years to get the recipe just right. Early turn-of-the-millennium attempts included the Xilinx Virtex II Pro with an on-chip PowerPC processor core and Altera’s Excalibur device with an ARM922T processor core. These early products are considered market failures. Actually, Kevin Morris called the Altera Excalibur “a monumental flop” in his article titled “< … Read More → "Microsemi Joins RISC-V Love Fest with SoC FPGA"

“Faith is taking the first step even when you don’t see the whole staircase.” – Martin Luther King, Jr.

It’s interesting to attend a religious revival meeting when you’re not a member of that particular denomination. It’s a bit like attending a political rally as an outsider, or buying tickets to a live concert even though you hate the band but your … Read More → "RISC-V: The Groundswell Continues"

Kev, It is the user community that has been so brain washed that new ideas are not welcome.
I think "RTL" means that the only choices for design entry are VHDL and Verilog. RISC V is ancient and just one more that loads each operand, fetches an instruction that does ...

There would be somewhat more value in RISC-V if it was something more than just the latest rev of an old idea, but done cheaper.
In the pictures above it could be a number of CPUs in the "RISC-V" boxes, and it would work just the same - most of ...

Yes indeed, there is not a dimes worth of difference between ALL of the RISC ISAs.
There is a load instruction for each operand, a store for the result, and a fetch of the instruction that does the operation.
The actual performance is determined by the memory system. Caches supposedly ...

The Load/Store times are somewhat misleading, high-density memories on the end of serial links (PCIe) are not that fast on small transfers. If you want that speed you'll have to do PiM - die-stacking the memory with CPU. Likewise using a single cache-coherent data-bus becomes the throttle on the ...

I'm on the other side of this. For example, if I'm using a $5 IoT device to do something important, and that device has $40M worth of cloud data center support required to make it work properly, I'd rather be paying for the service than the object. I want the supplier ...

[cranky mode /on]
Personally, I don't like subscriptions *at all.* When I buy something, I want to buy it, not keep paying for it. I pay cash for cars. I'd pay cash for my house if I could. I bought a cable modem rather than rent one from my ISP. ...

Cadence was recently named number 15 on the 2018 list of the World's Best Multinational Workplaces, according to global research and consulting firm Great Place to Work® and Fortune Magazine....
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Building on their existing partnership, Avnet, a leading global technology solutions provider, and Samtec, today announced an extension of their distribution agreement. Avnet customers in Asia Pacific and Japan now have access to Samtec's full product portfolio....

People of a certain age, who mindfully lived through the early microcomputer revolution during the first half of the 1970s, know about Bill Godbout. He was that guy who sent out crudely photocopied parts catalogs for all kinds of electronic components, sold from a Quon...