Posted
by
ScuttleMonkey
on Monday June 12, 2006 @05:15PM
from the closing-your-leaks dept.

An anonymous reader writes "Reducing power consumption is the name of the game in today's semiconductors and Intel today described its tri-gate transistor technology as one of the key technologies that could free the company from the trap of thinner gate insulators and increasing current leakage. Tri-gate (three gates instead of only one) could reduce the power consumption of transistors by 35% right now and drops off-voltage - one of the main sources of current leakage - by 50%. These results are the good news. The bad news is that tri-gate won't be available until 2009."

They could tell you, but then they'd have to kill you. Seriously, AMD doesn't like to trumpet things that are years away from production or otherwise give Intel unnecessary clues about what they're up to. Intel... well, we were supposed to have 10GHz P4's by now...

Sure, they are the favorite this year, but do they have the R&D budget Intel has to remain competative in the long term?

Is the same management in charge of Intel's R&D budget? Looks that way. Besides, there's the law of diminishing returns at work. Plus AMD trades technology with IBM. Working with clueful partners is a heck of a lot more efficient than trying to do everything yourself (and pushing those potential partners into the AMD camp).

AUSTIN, Texas -- Advanced Micro Devices researchers have developed a low aspect ratio Finfet-like transistor the company may begin producing as early as 2007 at the 45-nm node.

Zoran Krivokapic, the lead researcher on the multigate project, based at the company's technology research group in Sunnyvale, Calif., reported that the transistor switching speed -- expressed as CV/I, a measure of capacitance, voltage and current -- was 0.26 picoseconds for the NMOS devices and 0.45 ps for the PMOS transistors. AMD said those are the fastest transistors reported to date for 20-nm gate length structures.

The multigate device was introduced by AMD at the International Conference on Solid State Devices and Materials (SSDM) in Tokyo on Thursday (Sept. 18).

The gate surrounds a vertical channel, rather than the planer structure which stacks the channel, gate oxide and electrodes between the source and drain. The AMD structure has a lower aspect ratio than conventional FinFETs, which eases the burden on the lithographic tool and its depth of field.

AMD combined several process technology advances in the multigate structure. It used fully silicided (FUSI) metal gates, instead of electrodes made of polysilicon. Rather than depositing the nickel material, the AMD approach uses a silicidation process to gradually replace polysilicon with nickel silicide to form the metal gate electrodes.

Also, AMD employed fully depleted SOI (silicon on insulator). The fully depleted SOI combined with the metal gate creates a strain on the silicon in the channel, delivering higher-mobility electrons and holes.

Craig Sander, AMD vice president of process technology, said the multigate transistor will allow AMD to maintain roughly 20- percent per annum improvements in performance that has been standard for the semiconductor industry.

The stage delay, for example, exceeds the specifications set out by the 2003 International Technology Roadmap for Semiconductors for devices coming to market in the 2009 timeframe.

Sander said the multigate transistor delivers higher performance while keeping additional process complexity to a minimum. He said the multigate structure "is a prime candidate for the 45-nm node," expected to enter manufacturing as early as 2007.

AMD's multigate transistor is one of several recent announcements indicating that the vertical structures could replace planar CMOS transistors in high-performance devices much earlier than expected a few years ago. Intel Corp. executives, speaking at the Intel Developer Forum this week, indicated they expect some form of a multigate transistor to be introduced at the 45-nm node. Motorola, Taiwan Semiconductor Manufacturing Co. Ltd. and others also are pursuing the technology.

...all that AMD info sort of makes the whole article stale, no?
Especially concerning the timeline, AMD introduced the technology AND will have it available 2 years sooner than Intel.
I'm pretty sure that AMD knows their processors run kind of hot, and probably have the R&D guys working on it, even if they aren't making as much noise as Intel is about it.

also, good point Spy der Mann: combining resources with other companies - which Intel tends not to do - for example, the INVENT Lithography Consortium, a co-op R&D effort between AMD, IBM, Infineon Technologies, and Micron Technology.

that's funny - several Japanese semiconductor companies have decided to collaborate on the next generation 45nm and beyond CMOS - Renesas, NEC, Toshiba, and Fujitsu.
The Japanese also already have a semiconductor consortium called SELETE.
I guess they don't always practice what they preach!

As I am reading it this really isn't a 3D technology at all, it's more like three normal planes of circuitry stacked on top of each other. Of course I know why they haven't been working on a truly "3D" implementation: even though it would cut down the distance on average between any two gates moving heat away from the inside of the structure would be exceedingly difficult, while on a 2D chip getting rid of heat from anywhere is relatively easy (large surface area / volume).

It is not true that they aren't working on 3D technology. It is just that they haven't figured out a mature manufacturable process. In the end, Intel is not there to push Moore's law if it doesn't have economic benefits.

In real estate business there are 3 important factors: Location, Location , Location

In semiconductor industry (which is becoming a commodity), there are 3 factors as well: Cost, Cost, Cost

You mentioned about the heat issue. Yes it is important. But no one said you can't solve it. You can have structures which can distribute heat out (e.g. heat pipes). You can also have circuit techniques which are by default more process tolerant as well as low power (eg. asynchronous circuits). Both solutions wouldn't solve the problem completely, but yes it will be a step ahead. Then why don't do it. Industry still hasn't figured out if the cost to develop these techniques will harness them enough profit as compared to pushing the conventional techniques.

Also know one said that you can't extract 1000 W/cm^2 in ICs. It will just cost quite a bit.

So yes your point is well taken, but don't undermine the industrial goals. Profit comes first.

It's 3D no matter how you look at it; it's just at an incredibly microscopic scale. If you can say there are three circuits on top of each other, then they must logically be occupying a vertical dimension.

You must have been one of those children who objected to a piece of paper being called a plane (it has a very small vertical dimension too!). Making points such as this simply demonstrate that you don't understand how language is used. Generally if two dimensions of an object dwarf the remaining dimension we are inclined to call that object 2d, especially if the smallest dimension is microscopic. Likewise we call surfaces such as the top of a table "flat" even though on the microscopic scale they are act

First off, these are field effect transistors, which they don't specifically mention (although they do use the correct terminology for FET's.)

Secondly, it's not really that they have three gates. It's that they have a block of silicon that can conduct from source to drain, and a gate in the middle of it that can deplete/enrich the adjacent silicon to change its conductivity. Where most FETs have the gate on one surface, or 1/4 of the conduction channel's surface area, this one has a gate that stretches around 3/4 of the channel's surface area. Instead of gating like stepping on a hose, this gates like clamping the hose with pliers (for analogy = depletion-mode). Pretty cool, but that should come with a 3x increase in the gate's capacitance, shouldn't it? and fighting capacitance is one of the major struggles of increased speed, right? People doing very low-power stuff should love this. People doing high-speed design, maybe not so much.

Pretty cool, but that should come with a 3x increase in the gate's capacitance, shouldn't it? and fighting capacitance is one of the major struggles of increased speed, right? People doing very low-power stuff should love this. People doing high-speed design, maybe not so much.

Not really a problem. The transconductance of a transistor is actually proportional to the charge induced in the channel, which in turn is proportional to the gate voltage (limited) and the capacitance. In other words, you aren't going to get more gain without also getting more capacitance. In other words, for a given gain the capacitance is the same, but the leakage is less. [1]

The other reason this isn't a problem for low power is that interconnect capacitance is much greater than gate capacitance for practical circuits.

[1] Size isn't much affected, because so many other features are much larger than the channel. Contacts and required spacings, for instance.

You're implicitly assuming that these transistors will be on the same scale as current transistors. In reality, these will come in at the 30-40nm technology node, which means the transistor lengths and widths will already be 1/3 the size they currently are (presumably). Hence, the oxide capacitance shouldn't be more than it is today. If building a conventional MOSFET at 30-40nm results in massive leakage and whatnot, there may not be a choice, anyway (well, until someone comes up with another design).

Interconnect capacitance generally dominates gate capacitance. And since this type of gate will improve the signal to noise ratio, the device doesn't need to be as large, which would mitigate the increased gate cap.

You know, I used to get excited by cool new techs like that. Then I talked to someone who works closely with the process design engineers at Intel and other people who actually produce silicon based chips in mass. While those new discovers are very interesting, they usually don't lend themselves to mass production easily, if at all. Some of those new processes take huge, expensive machines and techniques and even then only produce a couple of workable prototypes. It is pure research at it's best. The issue is adapting that to producing millions of these on thousands of wafers every day with a high level of success (90%+ if not higher).

When a semiconducter producer like Intel announces stuff like in the article, it usually means they have a process that will work in mass production and can be available soon. Same goes for announcements from companies like IBM and AMD. So while they may be "obsolete" compared to what the cutting edge researchers are doing, they are definatly cutting edge for what can actually be used to make products actual people will use.

People get confused with just how damn long it can take to turn the first development of a new idea in to an actual product.

Look at Nanotubes. We STILL don't have any commercial produciton using Nanotubes going on and it's been about 15-20 YEARS in the making (depending on which start point you take). It started in 1985 with the discovery of fullerenes, the carbon buckyballs you hear about. Nanotubes themselves were orignally discovered in 1991. Since then there's been a lot of development in their uses and in their production, but still we do not see products on the market with them. I've a feeling we are getting close, but it's still years off.

That's just how it goes. There's a long time between something first being mesed with in a highly theoritical research context and it being something that we are all buying. It can be decades, hell it can be longer. How long have we been after fusion as a power source? 40 years? Maybe, MAYBE in another 20 we have it? Research is often not a fast process, it just takes lots of time trying things, learning, trying again, etc. It's not always osmething money can accelerate, sometimes it just takes a lot of time to do everything you need, sometimes you have to wait for development in other areas to make yours practical.

Either way, Intel's announcement is exciting for consumers because it's approaching the consumer level. Sounds like in 3-5 years we will be using thigns based on this. The GP's technology is neat, but nothing consumers should care about since at this point there's no prospect of consumer application. Perhaps in 10-30 years it'll be something to look at, but not now.

I'm not in R&D, but I think the way it works is that the stuff you find in academic publications is produced by research institutions like university labs. The researchers there are funded by government grants, corporate sponsorship, and student tuition(?). The kind of patents coming out of Intel and other big corps have a different purpose (mostly to develop the mass production processes).

Yup, there is a big difference between acedemic research and industry research. Acedamia can announce ideas that could not be made into useable products for 10-30 years because they don't really care. They are in it for the research. But in industry, you are usually working on a shorter time frame. Sure there are people working on ideas that may not work for decades, but they are the minority and usually the grayed haired geniuses that did things like create the transistor or the Internet. They already

Tri-gate electronics do, in fact, exist. They predate the transistor by several decades. Thermionic valves were capable of this very early on. I'm assuming that the problem is related to the fact that the medium used is not inherently 3D, making it hard to stack the gates in the way illustrated in the article, but the article itself doesn't say.

Tunnels sound very interesting. Leakage presumably has many causes, but would boil down to electrons leaving the desired path and going elsewhere. There MAY be ways of replacing the interconnects (which are usually just regular conductors) with superconductors, as superconductors should leak a lot less. (Resistance is a function of leakage, and superconductors have zero resistance.) This won't fix links on the silicon itself, but any improvement would be a good thing.

Tunnels sound very interesting. Leakage presumably has many causes, but would boil down to electrons leaving the desired path and going elsewhere. There MAY be ways of replacing the interconnects (which are usually just regular conductors) with superconductors, as superconductors should leak a lot less. (Resistance is a function of leakage, and superconductors have zero resistance.) This won't fix links on the silicon itself, but any improvement would be a good thing.

Leakage in this context is actually either:

Current that flows in the channel of an OFF transistor (this helps with that) or,

Current that flows through the gate dielectric (this doesn't help, you need high-K dielectrics for that)

Superconductors don't leak, dielectrics do. You may be thinking of losses.

Resistance isn't a function of leakage. Don't know where you got that one.

Actually, the described improvement will "fix links (sic) on the silicon itself"

The additional grids added to tubes serve a different purpose then the "triple gate" Intel is testing. Tetrodes add a screen grid which acts to lower Miller capacitance (the capacitance between the control grid and plate multiplied by the voltage gain) as well as lowering space charge. Both bipolar transistors and field effect transisters suffer from Miller capacitance and in the case of dual gate MOSFETs the second gate can be used in a similar way or a cascode configuration can be used. The third grid

I am not an electronic engineer, but surely having three gates in a FET doesn't qualify a transistor as Three-Dimensional. If Intel had created a cube chip with connections along all the three dimensional axes, we could call the transistor 3D, and that's not the case here.

No, it doesn't.Both FinFETs and Trigates are built on an SOI substrate ( silicon -oxide -silicon) whereas planar MOSFETs are built 'into' a silicon substrate; their channel is in the substrate, whereas the FinFETs' and trigates' is in the top layer of silicon. Trigate FETs are 3-D because the Si channel is 3-D with the gate wrapped around it on the top, front and back. Because it is 3D, it does not suffer from the short channel effects that planar MOSFETs do (due to an intrinsic channel ie no doping requ

I don't why we should refer to a tri-gate transistor as a "3D transistor".
Truely three dimensional integrated circuits have multiple layers on the silicon substrate, so as the laying extends vertically as well. I know only one company that was doing this, Matrix Semiconductor, Inc, and they claim to be the pioneers of the 3-D integrated circuits. http://www.matrixsemi.com/ [matrixsemi.com]. They are now acquired by SanDisk, Inc.