is an optional offset applied to the value in Rn. offset is
permitted only in 32-bit Thumb instructions. If offset is
omitted, an offset of 0 is assumed.

LDREX

LDREX loads data from memory.

If the physical address has the Shared TLB attribute, LDREX tags
the physical address as exclusive access for the current processor,
and clears any exclusive access tag for this processor for any other
physical address.

Otherwise, it tags the fact that the executing processor
has an outstanding tagged physical address.

STREX

STREX performs a conditional store to memory.
The conditions are as follows:

If the
physical address does not have the Shared TLB attribute, and the
executing processor has an outstanding tagged physical address,
the store takes place, the tag is cleared, and the value 0 is returned
in Rd.

If the physical address does not have the Shared
TLB attribute, and the executing processor does not have an outstanding
tagged physical address, the store does not take place, and the
value 1 is returned in Rd.

If the physical address has the Shared TLB attribute,
and the physical address is tagged as exclusive access for the executing
processor, the store takes place, the tag is cleared, and the value
0 is returned in Rd.

If the physical address has the Shared TLB attribute,
and the physical address is not tagged as exclusive access for the
executing processor, the store does not take place, and the value 1
is returned in Rd.

Restrictions

PC must not be used for any of Rd, Rt, Rt2,
or Rn.

For STREX, Rd must
not be the same register as Rt, Rt2,
or Rn.

For ARM instructions:

SP can be used
but use of SP for any of Rd, Rt,
or Rt2 is deprecated
in ARMv6T2 and above

For LDREXD and STREXD, Rt must
be an even numbered register, and not LR

Rt2 must
be R(t+1)

offset is
not permitted.

For Thumb instructions:

SP can be used for Rn,
but must not be used for any of Rd, Rt,
or Rt2

for LDREXD, Rt and Rt2 must
not be the same register

the value of offset can
be any multiple of four in the range 0-1020.

Usage

Use LDREX and STREX to implement
interprocess communication in multiple-processor and shared-memory
systems.

For reasons of performance, keep the number of instructions
between corresponding LDREX and STREX instruction
to a minimum.

Note

The address used in a STREX instruction must
be the same as the address in the most recently executed LDREX instruction.
The result of executing a STREX instruction to a different
address is unpredictable.

Architectures

ARM LDREX and STREX are available
in ARMv6 and above.

ARM LDREXB, LDREXH, LDREXD, STREXB, STREXD,
and STREXH are available in ARMv6K and above.

All these 32-bit Thumb instructions are available in ARMv6T2
and above, except that LDREXD and STREXD are
not available in the ARMv7-M architecture.