Thoughts on TSV Technology

The ink was almost dry on the TSV etching chapter I am contributing to a project called 3D Technology Platforms when I opened the newspaper today to read about very interesting news from Elpida regarding TSV-stacked DRAM (here: http://www.i-micronews.com/lectureArticle.asp?id=3448 ).

It’s some kind of harmonic convergence for me, as I sit here thinking about everything I wrote over the last month on TSV etching (which already becomes dated with today’s news), as I sit, thinking, about the nascent DRAM recovery, sit, thinking, about the magnificent Elpida site in the green wooded hills outside Hiroshima, hills set with large farming houses sporting freshly tiled roofs last time I visited, sit thinking about 300mm TSV processing challenges, sit, thinking, about the novel (and movie) Black Rain, and sit, remembering, how I would change trains at the Shin-Hiroshima station in order to reach the Hitachi factory in Kudamatsu after a long day of travel from San Francisco.

You had to be quick: Shin-Hiroshima to Tokuyama (Kudamatsu) could be a tough connection to make, and you would be stuck for the night if you didn’t.

Through-silicon via technology for 3D IC applications has deep roots in other commercial through-substrate via processing, most notably in compound semiconductor fabrication for components found in your friendly cell- and smart-phone handsets. And we all recognize how much TSV processing owes to MEMS fabrication, where deep structures in silicon are the name of the game.

Many eyes are now watching for the commercial launch of TSV technology beyond its use today in CMOS image sensors. DRAM, NAND Flash, memory stacked onto processor chips, all seem fair game for 3D integration, but, with recent and all-too-painful revenue woes being felt from Boise to Seoul, the investment budgets for TSV in memory applications just haven’t been there much this year.

Encouraging, then, to catch a pale view of recovery and progress today over Hiroshima hills.