Number of words of length width in the RAM array. Must be a power of 2.

byte_select = true/false

optional

When set to true, RAM will be byte-addressable using byte select lines (wb_sel_i from the WB bus and ram_bwsel_i from the peripheral). Default value is false (no byte addressing)

wrap_bits = num

optional

Number of extra bits allocated from the address bus. Used for mirroring the memory block multiple times (if wrap_bits > 0, the memory will be mirrored 2^wrap_bits times in the Wishbone address space. Useful for implementing circular buffers.

clock = clock signal

optional

Clock for the peripheral port of memory block. If it isn't specified, wbgen2 will assume the peripheral-side port works in WB bus clock domain)

access_bus, access_dev

mandatory

Specify how the memory block can be accessed from the bus and the peripheral. All combinations of READ_ONLY, READ_WRITE and WRITE_ONLY are supported (except for the nonsense ones: RO/RO or WO/WO).

Wbgen2 doesn't pack memory words - it places each memory word at different address, even if the memory width is smaller than the Wishbone bus width and several words could be packed into same address. In order to generate a memory which is seen by the WB master as a continuous block, declare it with the same width as the Wishbone data bus width and eventually enable byte_select for byte-wise access from the peripheral (see figure 1).