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Publishing Venue

IBM

Abstract

Presented here is a method for generation of test-programs for functional verification of VLIW processor architectures. The test-program is required to include VLIWs that conform to constraints coming from the architecture and from user requirements. The test-programs are also required to include intrinsic verification value targeted at testing the VLIW aspects of a processor design.

Country

Undisclosed

Language

English (United States)

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Very Large Instruction Word (VLIW) processors execute, in parallel, short sequences
of basic instructions. VLIW architectures consider a short sequence of instructions as
a single "large-word" instruction and execute the constituent instructions
concurrently. VLIW architectures often impose restrictions on the allowed
combinations of instructions that can be packed into a single VLIW. The number of
instructions in a VLIW, also referred to as the number of VLIW slot positions, can be
either fixed or variable, depending on the architecture. Further restrictions are on
data and resource dependencies within the single VLIW.

Presented here is a method for generation of test-programs for functional
verification of VLIW processor architectures. The test-program is required to include
VLIWs that conform to constraints coming from the architecture and from user
requirements. The test-programs are also required to include intrinsic verification
value targeted at testing the VLIW aspects of a processor design.

The only known solution to the problem the authors are aware of is the one
implemented in Genesys* -- a model-based test generation tool. Test generation is
done in a generation-simulation cycle where each VLIW generation is followed by
the VLIW execution on the reference model. Genesys took a sequential approach,
which consists of generating the instructions of the program one-by-one. After all the
constituent instructions are generated, they are packed into a single VLIW and
simulated on a behavioral reference model.

This method's sequential nature is myopic and frequently fails with
inter-instruction constraints inside a VLIW, resulting in exceptions, generation retries,
or poor test-program quality. For example, an illegal instruction combination may
occur if a specific instruction is requested for the final slot, because the generator is
not aware of the request while selecting instructions of the early slots. Similarly, if a
specific target register is required by the user for the last VLIW slot, the generator
may select the same register as a source in an earlier slot, failing the instruction of
the final-slot on an illegal source-target VLIW dependency.