Advanced Programmable Interrupt Controller (I/O APIC) provides multi-processor interrupt management. This chipset will allow static and dynamic symmetric interrupt distribution across all processors. In systems with multiple I/O subsystems, each subsystem can have its own set of interrupts and every interrupt pin is individually programmable.

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Advanced Programmable Interrupt Controller (I/O '''APIC''') provides multi-processor interrupt management. This chipset will allow static and dynamic symmetric interrupt distribution across all processors. In systems with multiple I/O subsystems, each subsystem can have its own set of interrupts and every interrupt pin is individually programmable.

The APIC just like it's ancestor is infamous for being a problematic bit of silicon. If fortunately has no relevance for MIPS systems as MIPS systems don't use it - even though it may be physically present in some systems.

Latest revision as of 16:29, 13 August 2012

Advanced Programmable Interrupt Controller (I/O APIC) provides multi-processor interrupt management. This chipset will allow static and dynamic symmetric interrupt distribution across all processors. In systems with multiple I/O subsystems, each subsystem can have its own set of interrupts and every interrupt pin is individually programmable.

APIC-free zone

The APIC just like it's ancestor is infamous for being a problematic bit of silicon. If fortunately has no relevance for MIPS systems as MIPS systems don't use it - even though it may be physically present in some systems.