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Abstract

This article describes a process for fabricating an FET gate protection diode with asymmetric dual polarity voltage capability. Such a device can be used in an electrically erasable/programmable read only memory or a non volatile random access memory where a gate potential that is more negative than the substrate potential is required. The disclosed process requires the addition of one mask and two ion-implant steps to an N-MOS FET process.

Country

United States

Language

English (United States)

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This article describes a process for fabricating an FET gate protection diode
with asymmetric dual polarity voltage capability. Such a device can be used in
an electrically erasable/programmable read only memory or a non volatile
random access memory where a gate potential that is more negative than the
substrate potential is required. The disclosed process requires the addition of
one mask and two ion-implant steps to an N-MOS FET process.

Referring to Fig. 1. an N region 1 is formed around a recessed oxide region
2 by ion implanting phosphorous through a photoresist mask 3. The
phosphorous implant compensates the previously implanted P-region.

Fig. 2 shows a later step in the process where the surface portion 4 of the N
region is doped by the normal source/drain ion implant to prevent the inversion of
the surface during negative voltage excursions.

Fig. 3 shows a later step in the process where the substrate contact mask 5
is used to open a region 6 in the recessed oxide (ROX). A low-energy boron ion
implant is then used to form the P-region 7.

Fig. 4 shows a later step in the process where the top P-region is contacted
by the metal electrode which may have both positive and negative biases
applied.

By proper selection of the phosphorous ion implant energy and dose, a back
to back PNP diode is achieved without changing or affecting the remainder of the
process steps for the N-MOS FET pr...