Putting Design Back Into DFT

Test always has been a delicate balance between cost and quality, but there are several changes happening in the industry that might cause a significant alteration in strategy.

Part one of this two part series about Design for Test (DFT) looked at changes in areas such as automotive, where built in self-test is becoming a mandated part of the design process. This could fundamentally change the way in which test is thought about.

In the past designers didn’t have to worry about test because it was not part of the functional specification, but some industry insiders believe it’s time for a new approach. “DFT is expensive in terms of area, it is expensive in terms of test time and it has undesirable physics,” said Jeff Rearick, senior fellow at Advanced Micro Devices. “What is the alternative to structured DFT? D is for Design. It is not for EDA. EDA wants to insert scan chains.”

By making test part of the functional specification, Rearick believes that engineers will start to get more creative and find more cost-effective ways to do it. Others believe that yield also will put pressure on finding better test solutions, some of which increasingly will deploy big data techniques.
Internet of Things (IoT)
While automotive is causing people to look at self-test, the IoT has a myopic focus on cost. “Cheap chips in the IoT domain still means you don’t want failures even in a 30-cent part,” says Joe Sawicki, vice president and general manager of the Design-to-Silicon Division of Mentor Graphics. “Large-scale diagnostics with sophisticated statistical analysis allows you to find yield failures that let you drive up the overall margins. Some people run production diagnostics on thousands of CPUs ever day to bring about changes that can improve the economics of wafer production.”

Rob Knoth, product management director at Cadence, agrees: “The margins on those chips are incredibly low, the cost of manufacturing is low, but the criticality of the devices is high.” Knoth lists four important attributes of IoT test—low cost, very high volume, cannot afford complex packages, cannot waste pins. The last two point to some necessary changes.

This is not just about IoT. “There are many automotive parts with very few pins, and the desire is to not increase the area with additional DFT,” says Robert Ruiz, senior director of marketing at Synopsys. “Instead, they would rather use functional patterns, and therefore the issue for test is what technologies exist for customers to build the functional pattern set. This means there is increasing interest in fault simulation.”

One test technique that can lower the cost of test for these devices is multi-site testing. “Multi-site testing is a strategy where you take the wafer and you connect to the test pins on the die itself,” explains Knoth. “The tester can do this to multiple chips at the same time because you don’t need as many pins on them. This enables a 32X or 64X improvement using as few as 4 or 8 test pins per die in high-volume mode. These pins do not need to be connected into the final package.”

Knoths’ final point is also of increasing concern for security reasons. Exposed test pins can enable hackers to get into your device and compromise its functionality. “We have to be able to test devices, and yet we have to trade that off to make sure you cannot use those test capabilities for the wrong reasons,” says Rearick.

2.5D integration
Another fabrication technique that is gaining traction is 2.5D integration, and this presents some new test challenges. “The biggest challenge is the sequence of testing,” says Knoth. “You have to start looking at the problem hierarchically. You have a pre-bond test where you look at the die itself using wafer probe. Then you have mid or post bond test where you want to examine the interconnect, and then the final test where you access things via the socket and ask if the whole system works.”

As with many things, the devil can hide in the details. “In the context of 2.5D programs, the importance of high-quality test is significant,” points out Bill Isaacson, senior director for ASIC product marketing at eSilicon. “These are relatively expensive devices, and once components are mounted on the interposer they cannot be reworked. The implication of missing a defect is a significant financial penalty, which is why we have robust wafer sort requirements for these programs.”

Post-bond testing also may require some changes in design. “The added complication is access,” says Steve Pateras, product marketing director at Mentor. “When you get into packaging you may not have access to the chip pins at the package level, so you need to provide some form of access and delivery mechanism for test to the outside world. This means that architectures are needed for transport mechanisms. We are also finding that in-chip resources become more desirable because of the access constraint. There are also some new test requirements such as through-silicon vias (TSV) test.”

Today, most people are relying on existing tools to help with these problems. “The methodologies in use today are just using standard board-level techniques – specifically boundary scan,” says Ruiz. “It’s treating the dies as chips on a board and adding an access mechanism. What is not standard today is the access mechanism to something other than the base die. Those are in development and that would be beneficial to users.”

Knoth agrees. “It is very similar to board design, but we are inserting a lot of test logic to try and automate this in the die themselves. So the complexity of the system goes up.”

Knoth points to IEEE std 1500 as one example of progress in this area, but he adds that some other issues are not covered by the standard. “The general problem is made more difficult by the heterogeneous nature of it. You could be integrating raw die from many different sources, and understanding what test was done is important. There is a chain of custody problem and data management here is difficult.”

Advances in DFT tools
The EDA industry has not been standing still, of course. There has been a string of improvements in DFT tools suites.

“Until recently, you would do test on a flat design and put the whole design into some number of scan chains,” says Pateras. “Now, we are going to hierarchical solutions where scan chains are accessed locally at a core or block level, and that helps in a number of ways. Distribution of the scan chains is better, power management capabilities are improved, and it enables reuse of resources. So if you have multiple instances of the same block, you generate the patterns for one of them. That can be broadcast to multiple cores and only one copy has to be stored in the tester. This is becoming critical as the designs get larger.”

Synopsys is also going in similar directions. “As complexity goes up, customers are increasingly looking at hierarchical compression,” says Ruiz. “In the past a typical ratio of scan input pins to scan chains in the design was about 1 to 50. That is going closer to 1 to 100 or more today. There are two other methodologies that are being explored. The first is that additional DFT hardware can be added that will limit the activity of test. If the customer wants to test multiple parts on a single load board, typically around 4 to 8, there are hardware techniques to reduce activity. And then there is the hierarchical approach, which is seeing recent interest. Here, a block or sub-system is completely tested and the other parts of the design remain off. That helps control overall chip-level power.”

As with many other areas of design, several tools appear to be merging or at least having increasing dependence on each other. “One area in which things are getting harder is delay modeling,” says Knoth. “Statistical delay quality level (SDQL) is about trying to predict the defects, but high-delay coverage does not necessarily correlate with low defect rates, and so you have to have better heuristics and better analysis of the effectiveness of the transition fault testing. It requires doing things such as defect probability distribution and then estimating the quality of the testing you are doing. This blurs the lines between STA and testing.”

Timing also has seen increased attention because of finFETs and as a way to help ramp yield. “There is an interest in using a smarter transition test, an at-speed test such as slack-based testing for this,” says Ruiz. “Slack information is driving the ATPG tool to generate a test, perhaps not on the longest path, but on some of the longer paths. With the adoption of finFET, we are seeing customers add more patterns. This is driven by two things. One is at the most advanced nodes, where the yield is still ramping and they want to capture all of the defects, including those on the margin. They need more sophisticated tests that can capture things that are breaking things, even by a fraction of a picosecond or some other subtle defect.”

As mentioned in the previous article, test has to be power aware. Otherwise, significant problems can appear. “There is a need to reduce the amount of activity to prevent IR drop problems,” explains Ruiz. “We made our ATPG tool power aware by being able to dial-in a switching budget, such as 15% or 20%. 25% appears to be the default that most customers use. The tool then does not exceed that much activity. It has been shown by ARM that there is a good correlation by just taking this into account.”

While the EDA industry looks to improve the existing structured test capabilities, the ideas for a rethink of the fundamental nature of test are still bubbling under the surface. Automotive, IoT and 2.5D may all add pressure for new approaches, but so far there are no better alternatives on the horizon.