Answer:

This is because the interrupt request flag, mask flag, and priority level settings are all assigned to the PIC1 register, and whenever a write operation occurs in the PIC1 register, the PIF1 bit (interrupt request flag) is also overwritten (cleared to zero).
Consequently, any interrupt request that was held pending (i.e., set to "1") is cleared during this write operation and the corresponding interrupt does not occur.

To avoid this, use timing for manipulating the PIC1 register that is not synchronized with interrupt timing (such as immediately after an INTP1 interrupt occurs).

Also, use a bit manipulation instruction that changes only one bit at a time.