Abstract: A trend in component testing has been developing
in recent years. Vendors of system components are being required by their
customers, equipment manufacturers, to apply inappropriate system level tests
to system components such as chips or modules. One such case of misapplication
of a system test to IC chips is explored and implications discussed.

Discussion: Vendors of system components, such as integrated circuits,
are being asked by equipment manufacturers to apply system level tests to
system components where the test does not apply and often yields useless
results. Misapplying test standards can lead to extra cost being built into
a product with little or no benefit to the customer. In addition, misunderstandings
between vendors and manufacturers can arise because a system level standard
likely gives no guidance as to how the test should be conducted for IC chips
or modules. In the absense of a well thought out written test procedure,
the person running the test must essentially invent, on the spot, a test
procedure that would normally be part of the standard governing the test
and take years to develop. Unless the test procedure is carefully documented
and made public, the results of the test are of little value as the results
are strongly affected by the test method used.

In addition to the test procedure specification, one must logically ask if
the test makes sense for a particular case. For instance, an IC whose connections
appear on a system connector may already be covered by IEC 61000-4-2 for
ESD immunity depending on the design of the connector. The test may make
no sense for an IC buried deep within a system with no external connections.
Even if an IC has such connections, if there are other components (an ethernet
transformer, for instance) between the IC and the external world, IEC 61000-4-2
may not apply for that IC.

Let's explore further the misapplication of a system level ESD test
to IC chips. IEC 61000-4-2 is an international standard intended to model the discharge from a person holding
a metallic object in a hand to an electronic system. The defined waveshape
of the discharge current into a 1 meter square metal plane is shown in Figure
1. The risetime to the first peak (700ps-1ns), the values at the first peak
and at 30 and 60 ns are specified. Although intended as an average
of a hand-metal discharge to an electronic system, the actual current will vary considerably in practice.

If IEC 61000-4-2 were applied to an IC chip, the current waveform delivered
to an IC would be strongly dependent on how the IC was connected. If floating
as shown in Figure 1, only a remnant of the initial peak would be observed
since the IC has only a small free space capacitance to charge and no
DC/low frequency connections. If one or more of the pins were connected to "ground," much
more current would flow, but the current would be dependent on the inductance and capacitance
of the connections (which need to be specified).

Figure 2. Waveform Specification of an IEC 61000-4-2 ESD Simulator

In addition to current waveform differences, system design will often
dominate differences in IC design with respect to ESD performance of the
chip in the system. For instance, an IC chip in the middle of a board with no
connections off the board would be likely be somewhat protected.
Whereas, if some of an IC's pins connect to a board edge connector, any discharge
to those pins would result in significantly more current as the board would be charged
through the IC. The stress on the
chip would be more severe than a chip internal to the board. Other layout issues
on the board, such as allowing signal traces to cross ground plane breaks
can also significantly increase the stress on an IC from an applied ESD
pulse.

Figure 2 shows a test example for a piece of tabletop equipment (some
details have been removed, see the original standard for the exact test setup)
in IEC 61000-4-2. The standard carefully describes how the discharges are
to be applied to the external enclosure of the equipment as well as the metal
tabletop and the vertical coupling plane, VCP (a metal plane held close to
the system which radiates EMI into the system when the plane is subjected
to a discharge). Criteria for system operation that passes or fails the
test is given. Both equipment damage and soft errors are addressed. But, nothing in the test procedure even hints as to how the discharge would be applied to internal system components.

Figure 3. Tabletop Equipment Test Setup for IEC 61000-4-2

Figure 4 shows an air discharge tip (upper) and a contact discharge tip (designed
for discharge to metal surfaces) with some details removed. These tips are
on the order of 50 mm long. The standard requires the use of these tips,
but how could these be used for IC chip testing? Can you imagine testing
a 1200 pin ball grid array package with one of these tips?

Figure 4. ESD Simulator Tips Used in IEC 61000-4-2

Summary:
In general, if a system level ESD test (such as IEC 61000-4-2) is applied
to individual IC chips, test results will be determined by the (often unspecified)
procedure used to test the IC chip. In addition, system and board design
will likely be much more important to IC chip survival in the field than
whether the IC chip survives a misapplied system test. There may be a few
cases where IEC 61000-4-2 can be adapted to limited cases of IC testing,
but such cases would be rare, include connections between the chip and outside
world, and require the IEC test be supplemented with a completely new test
procedure.

Applying
an ESD system level test to IC chips and modules adds cost and usually very
little value to a product. The results of such a test are generally not useful
unless an appropriate test method is specified to adapt the standard to the
new application and a solid technical justification for doing the test exists.

Additional information on this site regarding ESD effects on systems include: