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DDR3’s Impact on Signal Integrity

John Nieto | Apr 23, 2008

Applications demanding higher system bandwidth and lower power, such as converged notebooks, desktop PCs, and servers, continue to drive the evolution of industry standards, including DDR3 as defined by JEDEC. The latest DDR3 memory standard, JEDEC JESD79-3A, specifically supports these needs and the requirements of emerging dual and multicore processor systems. DDR3 differs from the well-established DDR2 standard in several areas, such as data rate, operating voltage, and logic.

For example, DDR3 supports data rates up to 1600 Mbits/s per pin with an operating voltage of 1.5 V—a 17% reduction from the previous generation of DDR2, which operated at 1.8 V (see the table). DDR3’s built-in power-conservation features, like partial refresh, can be particularly important in mobile applications where battery power will no longer be needed just to refresh an inactive portion of the DRAM.

DDR3 also has a specification for an optional thermal sensor that could enable mobile engineers to save further power by providing minimum refresh cycles when the system isn’t in high performance mode. Furthermore, DDR3 uses more internal banks—eight instead of the four used by DDR2—to further speed up systems by allowing advance prefetch, which provides the speed boost by reducing access latency. This should become more apparent as the size of the DRAM increases in the future.

The I/Os for DDR3 are designed to use the JEDEC standard SSTL15, which is based on 1.5-V logic, while DDR2 uses JEDEC standard SSTL18 that’s based on 1.8-V logic. Finally, the DDR3 architecture fully utilizes on-die termination (ODT), ZQ calibration, and a fly-topology for improved signal integrity.

Optimizing Signal Integrity
Since DDR3 is designed to run at higher memory speeds, the signal integrity of signals traveling through the memory module becomes more important. DDR3 uses a “fly-by” topology instead of the “T branches” seen on DDR2 module designs. This means the address and control lines in DDR3 are a single path chaining from one DRAM to another, where DDR2 uses a T topology that branches on the modules.

Fly-by topology takes away the mechanical line-balancing requirement and uses an automatic signal time delay generated by the controller fixed at the memory system training. Each DDR3 DRAM chip has an automatic leveling circuit for calibration and to memorize the calibration data.

Several impedance calibration sequences implemented for DDR3 optimize signal integrity. The Long ZQ calibration is used after power-up, while the Short ZQ calibration is used periodically during normal operation to compensate for voltage and temperature drift. These calibration sequences vastly improve the connectivity between the output driver of the SDRAM and the printed-circuit-board (PCB) trace.

A ZQ pin on the SDRAM is connected to an external precision resistor that adjusts the output driver impedance as well as the on-die termination (ODT) to match the trace impedance. This reduces impedance discontinuity and minimizes reflection on the signals.

Use of external precision resistors reduces the effect of variation due to process, voltage, and temperature, and maintains a tight tolerance for better controlled impedance values. DDR2, on the other hand, employs on-chip resistors, which can exhibit larger variations. The system and DRAMs also utilize dynamic ODT. The ODT can be switched off and on and value-selected from a few fixed values (Fig. 1).

To further improve signal integrity, DDR3’s fly-by topology is also used for command/address and clock signals (Fig. 2). The signals are routed to the DRAMs in a linear fashion and to the edge of the card where the bus termination is located. This helps reduce the number of stubs and stub lengths that normally would be present in DDR2’s T-topology.

However, this introduces flight time skew between the clocks and data/strobes at the DRAMs. Designers can compensate for the flight time skew, though, from the controller side on the motherboard by performing a leveling technique for deskew, which puts the DRAMs through a training sequence for tuning the DRAM clock.

The DRAM’s internal core speed basically remains unchanged in the transition from DDR2 to DDR3. DDR2 currently has a maximum bandwidth of 800 Mbits/s per pin, but can extend to 1066 Mbits/s. To meet DDR3 bandwidths of up to 1600 Mbits/s, an eight-word prefetch is used as opposed to the DDR2’s four-word prefetch. As a result, for every read or write operation, eight words within the core of the DRAM are accessed.

This integrated part features programmable drive strength, input bus termination, and output inversion, effectively reducing simultaneous switching noise. For power savings, the device includes output inversion and the ability to float the outputs. It also can completely power down the chips via input logic states. More power can be saved by programming the output drivers’ impedance.

With enhanced termination techniques and impedance matching, the signal integrity of the data eye is vastly improved using an integrated device, which in turn increases the margin in the timing budget. When employing the optimal termination, driver impedance, and output inversion enabled, the data eye should look relatively clean (Fig. 3).

From mobile applications to notebooks to enterprise servers, there’s a constant demand for higher bandwidth, lower power, and improved throughput efficiency. The onus is on DDR chip vendors to adapt and provide IC chips such as the DDR DRAM, register, and PLL with improved signal performance.
Through JEDEC, new and innovative methods to improve signal integrity from one generation of DDR to the next have been defined to facilitate memory-driven application requirements. The DDR memory interface technology will be continually pushed to its maximum limits and enhanced to meet industry needs.