Materials Improvements Boosting IC Performance

SAN FRANCISCO — Improvements in semiconductor materials are now responsible for about 90 percent of the performance improvement of ICs at each node, significantly more than the roughly 15 percent they contributed in 2000, according to Schubert Chu, head of Applied Materials Inc.'s epitaxy unit.

In an interview at the Semicon West fab tool tradeshow here Wednesday, July 11, Chu said that in the "mobility era" -- where smartphones and tablets are driving much of the electronics supply chain -- the focus is on increasing transistor performance while at the same time reducing power consumption. This differs vastly from the focus during the PC era, when power consumption was practically a non-issue, Chu said.

"As each generation of devices comes out, the story that doesn't get told enough is the need to improve performance without increasing power consumption," Chu said.

Applied Materials of Santa Clara, Calif., announced this week a newly developed NMOS transistor application for its Applied Centura RP epitaxial (epi) system. An NMOS transistor is a MOS transistor where the active carriers are electrons flowing between n-type source and drain regions in an electrostatically formed n-channel in a p-type silicon substrate, according to the company.

Chu says epitaxial deposition has come a long way in the past 10 years. Ten years ago, Applied -- the leader in the market with an estimated 80 percent market share -- sold epi systems mostly to wafer suppliers. But today, because of the technology's ability to improve mobile processor performance, Applied sells far more systems, and foundries are the largest customer segment.

Today, there are several epi steps in the semiconductor manufacturing process, Chu said. More are on the way, he told us, as chip vendors see the potential to improve the performance of their devices using this technology. Applied defines epitaxy as a method of depositing or growing a monocrystalline film where the deposited film takes on a lattice structure and orientation identical to those of the substrate.

Chu says implementing an NMOS epi process in addition to PMOS epi enables foundry customers to further improve the performance of next-generation devices. The new process is already in use at several customer sites.

The use of strained selective epi films with in-situ doping have improved mobility and reduced electrical resistance in PMOS transistors since the 90nm node, increasing the speed of chips, according to Chu. He says applying selective epi in NMOS transistors delivers a similar boost, which enhances overall chip performance.

"People are looking for the next area that will give them an advantage," Chu said, noting that new epi materials will be key driver for transistor speed beyond 20nm.

If your focus is strictly at the transistor level and improving transistor performance, then maybe you can claim a figure like 90%. But at the SoC level, the system architecture, algorithms, etc. -- the design, not the devices -- has far more impact on power and performance than any transistor-level improvements.