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P.Peˇcar,M.Janeˇz,N.Zimic,M.Mraz,I.Lebar Bajec.The Ternary Quantum-dot Cellular Automata Memorizing Cell.In Proc.of ISVLSI 2009,Tampa,FL,pg.223–228.doi:10.1109/ISVLSI.2009.32c°2009 IEEEThe Ternary Quantum-dot Cellular Automata Memorizing CellPrimoˇz Peˇcar Miha Janeˇz Nikolaj Zimic Miha MrazIztok Lebar BajecUniversity of Ljubljana,Faculty of Computer and Information Science,Ljubljana,Sloveniaprimoz.pecar@fri.uni-lj.siAbstractQuantum-dot Cellular Automata (QCA) were demon-strated to be a possible candidate for the implementationof a future multi-valued processing platform.Recent papersshowthat the introduction of adiabatic switching and the el-egant application of the adiabatic pipelining concept in theQCA logic design can be used to efﬁciently solve the issuesof the elementary ternary QCA logic primitives.The ar-chitectures of the resulting ternary QCAs become similar totheir binary counterparts and thus the design rules for largecircuit design remain similar to those developed for the bi-nary QCA domain.In spite of this the design of the binaryQCA SR memorizing cell cannot be directly transferred tothe ternary domain,mostly because the control logic cannotproperly handle the third value.We here propose a ternaryQCA memorizing cell that efﬁciently exploits the pipeliningmechanism at a wire level.It is centered on the circulatingmemory model (i.e.the memory in motion concept),whichproved to be an efﬁcient concept in memorizing cell designin the binary QCA domain.The proposed memorizing cellis capable of serving as one trit (ternary digit) of memoryand represents a step forward to the ternary register,one ofthe basic building blocks of a ternary processor.1.IntroductionThe theoretical advantages of ternary logic based pro-cessing have been extensively researched over the past ﬁvedecades [17,5,8,18,7,3,4].Unfortunately the actual work-able platform designs are unable to keep up with the the-oretical advancement.The main obstacle is the shortageof building blocks that could offer native ternary support.Currently known solutions are built mostly on CMOS tech-nology,which is in itself based on a two state device,thetransistor.Hence even simple ternary logic gates and mem-orizing elements use complex designs,which in a way at-tenuates the efﬁciency of a ternary processing platform im-plementation.The new,emerging processing platforms,alternative toCMOS,should not explicitly impose limits to only twostates.One such possible future processing platform is thequantum-dot cellular automaton (QCA).The concept wasintroduced in the early 1990s by Lent et.al [13,21] anddemonstrated in a laboratory environment in the followingyears by Bernstein et.al [1].What followed was an ex-hilarating period with the development of the functionallycomplete set of logic functions,as well as more complexprocessing structures,however all in the realm of binarylogic.The ﬁrst advancement of QCAs to native ternary pro-cessing was performed by Lebar Bajec et.al [9,10,11].The authors have redesigned the fundamental unit,a binaryQCA (bQCA) cell,to allow for the representation of threelogic values and named it simply the ternary QCA (tQCA)cell.The subsequent research preformed by Peˇcar et.al[15,16] shows that the introduction of adiabatic pipeliningis essential for an elegant implementation of basic ternarylogic gates.The similarity of the architecture of the tQCAlogic gates proposed by Peˇcar et.al to the architecture of thecorresponding bQCAlogic gates opens up the possibility touse design rules similar to those developed for the binarydomain.The initial results are encouraging but the design of com-plex processing elements is still at its ﬁrst steps.Indeed,although the approach was fruitful for the design of basiclogic gates,one can not simply replicate (or translate) thedesigns proposed for the bQCA platform.The designs pro-posed for the ternary CMOS platformcan not be relied uponas well.These typically employ primitives,like the TXORgate,for which there are no current tQCAequivalents,or donot rely on logic but represent ad-hoc solutions exploitingphysical effects.Here we present the design of one of the most ba-sic ternary processing elements,which can store one trit(ternary digit) of data,the ternary memorizing cell.It re-lies on proven approaches from bQCA design and efﬁcientuse of the currently available tQCA primitives (ternary in-verter,ternary majority voting gate,ternary wire).Its core1is centered on the memory in motion concept,which hasproved to be effective at the design of the bQCA memo-rizing cell [6,22].The control logic is,on the other hand,designed to promote an efﬁcient implementation of an n-tritregister that is based on an array of n ternary memorizingcells.In section 2 we present a brief overview of the principalternary building blocks.In section 3 we describe the designof the tQCA memorizing cell.Section 4 concludes with theanalysis of its behavior.2.Building blocks overviewIn general,a QCA is a planar array of quantum-dot(QCA) cells [13].The fundamental unit of a ternary QCA,is a tQCAcell [9].It comprises eight quantumdots arrangedin a circular pattern and two mobile electrons.The Coulombinteraction between the electrons causes themto localize inquantum dots that ensure their maximal separation (ener-getic minimal state).The four arrangements,which cor-respond to energetic minimal states (ground states),aremarked as A,B,C and D (see Fig.1).Relying on the prin-Figure 1.The four possible arrangementsthat ensure maximal separation of electronsare mapped to balanced ternary values -1,0and 1.ciple of ground state computing,the four states can be inter-preted as logic values.We here employ the balanced ternarylogic,so A is interpreted as logic value ¡1,B as logic value1 and C and D as 0.The arrangement D is typically not al-lowed (desired) for input or output cells [10,11,15].Placingone or more cells in the observed cell’s neighborhood,usu-ally causes one of the arrangements to become the favoredground state.The cell to cell interaction is strictly Coulom-bic and involves only rearrangements of electrons withinindividual cells,thus it enables computation.With speciﬁcplanar arrangements of cells it is possible to mimic the be-havior of interconnecting wires as well as logic gates [20].By interconnecting such building blocks more complex de-vices capable of processing can be constructed.The reliability of the behavior of a QCA device dependsforemost on the reliability of the switching process,i.e.the transition of a cell’s state that corresponds to one logicvalue to a state that corresponds another and vice versa.Itis achieved by means of the adiabatic switching concept,where a cyclic signal,namely adiabatic clock,is used tocontrol the cells’ switching dynamic [19,15].The signalcomprises four phases.The switch phase serves the cells’gradual update of the state with respect to their neighbors.The hold phase is intended for the stabilization of the cells’states when they are to be accessed by the neighbors that arein the switch phase.The release phase and the relax phasesupport the cells’ gradual preparation for a new switch.Research by Peˇcar et.al [16] shows that the correct be-havior of tQCA logic gates requires a synchronized datatransfer,which can be achieved with a pipelined architec-ture.The four phased nature of the adiabatic clock en-ables the desired architecture.Indeed,this property of theclock signal allows any tQCA to be decomposed to smallerstages,or subsystems,controlled by phase shifted signals,each deﬁning its own clocking zone.Let 0 denote the clock-ing zone controlled by the base signal (usually the clockingzone of the input cells) and i = f0;1;2;3g the clockingzone controlled by the base signal phase shifted by i phases.Subsystems that are in the hold phase act as inputs for sub-systems that are in the switch phase.A subsystem,afterperforming its computation,can thus be designed to lockits state and act as the input for another subsystem.As thetransaction is ﬁnished the second subsystem can start pro-cessing while the ﬁrst is ready for processing on newinputs.With the correct assignment of cells to clocking zones,thedirection of data ﬂow can be controlled.Large regions ofnearby cells are usually assigned to the same clocking zonein order to eliminate the challenges that would be caused byattempting to deliver a separate clock signal to every cell.The latency of a QCA circuit is determined by the num-ber of clocking zones along its critical path.A sequence offour clocking zones causes the delay of one clock cycle.Consequently minimizing the number of clocking zonesleads to better designs [14].The tQCA memorizing cell,to be presented in the nextsection,is based on currently available primitives:theternary wire,the ternary inverter and the ternary majorityvoting gate.The ternary wire is a sequence of tQCA cellsthat enables propagation of data from the input cell to theoutput cell (see Fig.2).When the input cell’s state is A(logic value ¡1) or B (logic value 1) all cells propagatethe same state.However,when the input cell’s state is C(logic value0) the cells propagate the state in an alternat-ing fashion.This effectively means that wires have to be ofodd lengths [11].Having that in mind the tQCA wire canbe described as a processing element performing the logicfunction:y = w(x) = x;(1)where x 2 f¡1;0;1g corresponds to the state of cell Xandy 2 f¡1;0;1g corresponds to the state of cell Y.The cor-rect behavior of the corner wire and fan-out is ensured by2Figure 2.Efﬁcient use of clocking zones fora robust tQCA wire:straight wire (a),cornerwire (b) and fan-out (c).means of a pipeline of two stages,as presented on Figs.2band2c.The ﬁrst stage ensures the propagation of the inputvalue to the corner,and the second stage ensures its propa-gation towards the output cell.Currently there exist two implementations of the ternaryinverter [16],both relying on the fact that two cells arrangeddiagonally assume alternate states when one is in state Aor B and the same state when one is in state C or D.Wehere use the basic implementation presented in Fig.3.Itis a two staged pipeline,where the input ternary wire andthe inverting core (the two cells arranged diagonally) areassigned to one clocking zone and the output ternary wireto another clocking zone.The given structure evaluates theFigure 3.The ternary inverter.logic functiony = i(x) =x ´ ¡x;(2)where x 2 f¡1;0;1g corresponds to the state of cell Xandy 2 f¡1;0;1g corresponds to the state of cell Y.The ternary majority voting gate is currently,due to thelack of implementations of other multi-input ternary logicfunctions,the fundamental building block in tQCA design.It is constructed as a crossing of three ternary wires andcan be implemented in two possible ways [16].We hereuse the diagonal ternary majority voting gate presented inFig.4.The structure has three input cells denoted X1,X2and X3,a device cell in the center and an output cell Y.Itacts as majority voting logic;the output reﬂects either theFigure 4.A pipeline implementation of the di-agonal ternary majority voting gate.logic value that has been present at the majority of the inputsor logic value 0 if the majority can not be determined (e.g.in the case of the input combination x1= ¡1,x2= 1,x3=0).The described behavior can only be achieved through anelegant assignment of clocking zones.The one employedin this work,designates the input cells to clocking zone 0,but designates the device cell and output cells to clockingzone 1.The gate’s behavior can be described with the logicfunction:y = m(x1;x2;x3) = x1x2_ x2x3_ x1x3;(3)where x1;x2;x32 f¡1;0;1g correspond to the states ofinput cells X1,X2,X3and y 2 f¡1;0;1g corresponds tothe state of the output cell Y.The ternary AND and ORlogic functions can be expressed asx1x2´ min(x1;x2);x1_ x2´ max(x1;x2);(4)where x1;x2;y 2 f¡1;0;1g.A closer look at equation (3)reveals that the ternary AND logic function can be imple-mented by ﬁxing one input logic value of the ternary major-ity voting gate to ¡1,and the ternary OR logic function canbe implemented by ﬁxing one input logic value to 1.3.Design of the ternary QCA memorizing cellThe adiabatic pipelining mechanism,described in sec-tion2,when used at the wire level,allows for the con-struction of a delay (latch) wire.The ‘memory in motion’concept takes advantage of this property in order to con-struct a memorizing element.The basis of this concept is apipelined delay loop consisting of four successive clockingzones,as proposed in the design of the H-memory mod-ule [2,6,22].Each individual clocking zone represents adelay of one quarter of the clocking signal cycle,hence thecomplete pipelined delay loop serves for a delay of one fullcycle.The memorized data remains circulating the loop upuntil a data write instruction has been carried out and newdata enters the loop.The data read instruction,on the otherhand,does not alter the data that is circulating the loop.3Atypical example of the application of the pipelined de-lay loop is the bQCAimplementation of the SRmemorizingcell.The control logic consists of an inverter and two ma-jority voting gates.The latter two are used to implement thebinary AND(middle input ﬁxed to the binary logic value 0)and OR(middle input ﬁxed to the binary logic value 1) logicfunctions.The behavior of the binary SR memorizing cellis described by the logic functionD1q =rq _s;(5)where s;r 2 f0;1g are the inputs and q 2 f0;1g is the out-put of the memorizing cell.In the bQCA implementationthe condition rs = 0,known fromthe CMOS domain,is nolonger applicable,as it does not lead to a conﬂicting situa-tion,but serves as a redundant input combination for settingthe memorizing cell (memorizing the logic value 1).Unfortunately the promotion of the SR memorizing cellto the ternary domain by the simple substitution of thebQCAdelay loop and the bQCAmajority voting gates withthe tQCA delay loop and tQCA majority voting gates re-spectively,would prove to be unproductive.Indeed,as-suming that s;r;q 2 f¡1;0;1g and evaluating equation(5) one obtains table1.As it can be noticed the promo-Table 1.Behavior of the SR memorizing cellin the ternary domain.s rD1q-1 -1q-1 00q-1 1-10 -10 _q0 000 101 -111 011 11tion to the ternary domain leads to ‘problematic’ input com-binations.These combinations are those,where one of theinput variables s;r 2 f¡1;0;1g is 0.The reason whysuch combinations can be termed as ‘problematic’ is dueto the fact that the design of the set and reset operationsof the binary SR memorizing cell,eq.(5),exploits twofundamental laws of binary logic;the law of contradiction(xx = 0;x 2 f0;1g) and the law of excluded middle(x_x = 1;x 2 f0;1g).As these two laws are not availablein the ternary domain (xx = 0 and x_x = 0;when x = 0)this has undesirable effects on the set and reset operations.We bypassed this issue with a different interpretation ofthe memorizing cell’s control logic.Instead of using twocontrol inputs,set and reset,we voted for one control andone data input.The control input speciﬁes if a write orread operation is to be executed,hence only two (¡1 and1) of the three logic values are allowed.The data input,on the other hand,accepts all three logic values (¡1,0 and1).By employing this approach we were able to design aternary memorizing cell capable of all classical data opera-tions:reading,writing and arbitrarily long memorizing.Figure5presents the schematics of the ternary memo-rizing cell.Data memorizing has been achieved by meansFigure 5.The schematics of the tQCA im-plementation of the ternary memorizing cell.The symbol Ddenotes where the actual delayis achieved (the pipelined delay loop).of a pipelined delay loop,where a trit (ternary digit) of datais kept circulating as long as the control input,w,and datainput,x,remain ¡1.During all this time the lower ternarymajority voting gate,designed to execute a ternary AND ofthe inverted control input (in this case 1) and the delayedlogic value q,only transmits the delayed logic value q to itsoutput.The upper ternary majority voting gate,designedto execute a ternary OR of the data input (in this case ¡1)and the output of the lower ternary majority voting gate (inthis case the delayed logic value q),again only transmit thedelayed logic value q to its output (the output of the mem-orizing cell).This way it is ensured that the logic value qenters the delay loop one more time,from where it shallreturn to the lower ternary majority voting gate.From the point of view of the control input readingequals memorizing,after all the memorizing cell’s outputlogic value q is the logic value that is kept circulating in-side the delay loop.Writing is,on the other hand,executedwhen the control input is applied the logic value ¡1.Inthis case the lower ternary majority voting gate clears thedelayed logic value and transmits the logic value ¡1 to itsoutput.This enables the upper ternary majority voting gate,designed to execute a ternary OR of the data input (in thiscase x) and the output of the lower ternary majority votinggate (in this case ¡1),to transmit the new data value,x,to its output (the output of the memorizing cell),and fromthere into the delay loop.The memorizing cell’s logic func-tion can be described asD1q = m(x;1;m(w;¡1;q)) = x _wq;(6)where x 2 f¡1;0;1g is the data input logic value,w 24f¡1;1g is the control input logic value,x = ¡1 wheneverw = ¡1 and q 2 f¡1;0;1g is the output logic value of theternary memorizing cell.One can easily notice that equa-tion (6) is identical to equation (5) with the exception thatthe variables assume different roles.By taking advantage of the adiabatic pipeline concept theschematics presented in Fig.5can be directly translated tothe tQCA platform.The pipelined delay loop is a bit harderFigure 6.The layout of the ternary QCA mem-orizing cell.to spot in the layout presented in Fig.6,mostly due to itsextreme compactness.Its most prominent element (servingalso as its input) is the memorizing cell’s output cell,Q,which is actually also the output cell of the upper ternarymajority voting gate.The loop continues diagonally down-wards towards the input of the lower ternary majority vot-ing gate.The complete pipelined delay loop (the delay of acomplete clock cycle),is thus constructed from:the deviceand output cells of the upper ternary majority voting gate;one cell providing a delay of a quarter of a cycle;and theinput,device and output cells of the lower ternary majorityvoting gate.As the output cell of the lower ternary majorityvoting gate serves also as the input of the upper ternary ma-jority voting gate this closes the loop.The clocking zones(marked in the lower right corner of each tQCA cell) areassigned so as to achieve the necessary data ﬂow,as wellas to keep as many cells in the same clocking zone in orderto avoid the challenges that would be caused by attemptingto deliver a separate clock signal to every cell.The controland data signals arrive at the memorizing cell from the leftthrough tQCA cells marked X and W,respectively.Thetwo cells,that are not assigned to a clocking zone are ﬁxedto speciﬁc states corresponding to logic values ¡1 and 1and serve only as selectors of the logic function performedby the ternary majority voting gates (i.e.AND and OR re-spectively).The layout of the memorizing cell allows it tobe easily placed inside an array of other equivalent memo-rizing cells.Due to the fact,that the proposed memorizingcell is capable of serving as one trit of memory,an array ofn such cells forms an n-trit register.4.Analysis of the ternary QCA memorizingcellThe analysis was carried out using the ICHA simulationapproach [12,16].It was based on the following param-eters:quantum dots have a diameter of 10 nm,distancebetween adjacent quantum dots is 20 nm,cell centers areplaced on a 110 nm grid.All other relevant parameterswere evaluated for a GaAs/AlGaAs material system.Theresults presented on Fig.7have been obtained with the fol-Figure 7.The ternary memorizing cell tQCAsimulation results.The grey strip marks anexample of writing the logic value ¡1.lowing sequence of read/write operations:read,write (-1),write (-1),read,write (1),read,write (0),write (1),read,write (0),read,read.The ﬁrst curve,marked ‘Clock’,isthe waveform of the adiabatic clock signal,which is usedto control the tQCA cells assigned to clocking zone 0,andthus speciﬁes the start of the read/write operation.The cellscontain valid data only when the correspondingly shiftedclock signal is in the hold phase (H).As the adiabatic clockstarts with a switch phase,this means that at this instantonly cells assigned to clocking zone 3 contain valid data.The second and third curve represent the waveforms of the5control,w,and data,x,input signals,respectively.The last,fourth,curve,on the other hand,corresponds to the mem-orizing cell’s output q (only intervals with valid data aredisplayed).One can notice that the presented memorizingcell provides a delay of exactly one clock cycle fromthe in-stant at which data is input into the memorizing cell (cells Xand W) to the instant at which it appears at the memorizingcell’s output (cell Q).The memorized logic value circulatesthe pipelined delay loop and keeps appearing at the outputcell Qup until the moment when newdata is written into thememorizing cell.The behavior of the ternary memorizingcell is thus comparable to its binary counterpart.5.ConclusionThe paper presents a novel design of a ternary QCAmemorizing cell that is capable of storing one trit of data.The proposed design exploits the well known approach usedfor the design of memorizing cells in the binary QCA do-main,but solves the binary to ternary transition problemswith a reinterpretation of the input signals.Its compact im-plementation places it into the set of basic ternary buildingblocks that could be used to build complex processing plat-forms of the future.AcknowledgmentThe work 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