Chip packaging problems getting worse

By 12.21.2004 :: 9:29AM EST12.21.2004

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with modern fpgas and other ics running at hundreds of megahertz or more, the problem of package parasitics has become extraordinary. as the clock speed of the signals on inter-chip transmission lines increases, the noise generated by parasitic capacitance and inductance between pins on the ic package becomes more difficult to manage, and if not properly designed, then the interference will result in bouncing. nearly half of the pins on a modern ic are power and ground lines. if any power or ground lines bounce, then the ic will likely fail. this problem is particularly pronounced in fpgas, which must be designed for a broad range of applications, and may have in upwards of 800 user programmable i/o pins. it is extremely difficult for fpga designers to model and test and compensate for worst-case implementations. on the other hand, it seems that asics, although they tend to run at higher clock speeds, tend to suffer less from these problems, as they have a much more specific operation and can therefore be properly optimized. but, even asics are not immune. to help alleviate the problems, engineers are calling for ic designers to thoroughly test their designs for worst-case usage with 3d electrical simulation tools, and to provide better documentation of the electrical characteristics of their packages, so that board-level designers will know more about what they are getting themselves into. both altera and xilinx, the two largest fpga vendors, promise to improve the situation through 3d simulation, and provide model files for implementers to analyze independently for their particular needs. others will undoubtedly catch on as the pressure from board-makers increases.

user comments 3 comment(s)

ok u lost me on that one(10:37am est tue dec 21 2004)naaa, cant be that important…. or? – by bouncing is bad

programmable io levels(11:57am est tue dec 21 2004)i wonder if the programmable io levels for each pin are adding to the extra capacitance… with asics you can make tollerant pins, but most times i use pins designed for a specific level (non-tollerant).