SAN JOSE, Calif. — May 1, 2018 — eSilicon, an independent provider of FinFET-class ASICs, custom IP, and advanced 2.5D packaging solutions, today announced that the deep learning ASIC that taped out last September has moved to production qualification.

The CoWoS interposer is over 1,000 square mm and contains over 170,000 microbumps. The design has successfully passed test bring-up and is in final qualification. Four-high and eight-high HBM stack versions are in qualification. This design is in the industry vanguard of ASICs targeting deep learning applications.

The 2.5D/HBM2 single package implementation gives the ASIC many advantages:

Orders of magnitude higher total bandwidth in a much smaller board footprint

“This design greatly expands the possibilities for deep learning, and we are delighted to enter final qualification,” said Ajay Lalwani, vice president, global manufacturing operations at eSilicon. “TSMC’s 2.5D CoWoS packaging technology has been a key differentiator for this advanced design.”