MILPITAS, Calif., May 26, 2015 — (PRNewswire) — Sonics, Inc., the world's foremost supplier of on-chip network (NoC) technologies and services, is participating in the
Design Automation Conference (DAC) 2015. The Design Automation Conference (DAC) is recognized as the premier conference for design and automation of electronic systems. Sonics will be showing its cool new ICE-Grain™ Power Architecture and participating in the Heart of Technology (HOT) fund raiser among other activities.

Here's the rundown on where to find Sonics at DAC.

DAC Exhibit Floor

Dates:

June 8 – 10

Location:

ARM Connected Community, Booth #2414

Constellations IP Community, Booth #3501

Visit Sonics in one of these locations to learn why we are the Trusted Leader in On-Chip Networks. We'll be showing demos of SonicsGN® and SonicsStudio® Director. We'll also be talking about the IP industry's first complete power management subsystem solution, our new ICE-Grain Power Architecture.

Many of today's SoCs, ASICs, and ASSPs contain multiple digital, analog, and subsystem IPs. In the majority of cases for such ICs, the dynamic power and static power play key roles in the differentiation and viability of complex chips. In this session, implementation techniques, selection tradeoffs, and optimization for ultra-low power IC will be presented. This is greatly beneficial for designers in applications such as: IOT, automotive, imaging, wireless, networking, portable multimedia, medical, gaming, video, and MEM applications.

In this panel, implementation techniques and tradeoffs for designing ultra Low-power SOCs, ASSPs, and ASICs will be presented. These techniques are critical for battery-powered devices, and other devices that are sensitive to thermal management as well as reduction of packaging cost. IP suppliers and EDA vendors now offer low-power IPs as well as optimization tools.

Topics such as FinFet and FDSOI devices will be compared with planar CMOS, power harvesting, and using UPF for low power implementation. Designers also apply reduced voltage or Dynamic Voltage & Frequency Scaling (DVFS), power shutdown, and retention logic. Typical low-power designs could have over 30 different power modes and power domains. Dual-rail memory IPs operate in full power, partial power, or shutoff modes. Designs include isolation cells, level shifters, and retention cells with multiple modules in each power domain.

Optimization of these advance techniques for various applications such as portable Gaming, IOT, Automotive, Wireless, Networking, Portable Multimedia, wearable computing, and low power techniques are paramount for gaining and keeping market share.

ARM Connected Community Pavilion Presentation

Dates:

June 8th at 2:45 pm

June 9th at 1:15 pm

Location:

Booth #2414

IP Talks, ChipEstimate Booth

Dates:

June 8th at 4:00 pm

June 9th at 1:30 pm

June 10th at 5:00 pm

Location:

Booth #2433

Power is on everyone's mind whether you're creating an application processor for mobile phones or an SoC for IoT or Wearable applications. Conventional software-based power management approaches don't save enough power. This presentation will cover the need for a hardware-based power management solution for mainstream SoC designs. It will introduce Sonics' ICE-Grain Power Architecture, which is the semiconductor IP industry's first complete power management subsystem. It will discuss the key capabilities and benefits of the ICE-Grain Power Architecture and explain how the solution makes sophisticated power management and control techniques available to a broader audience.

Sonics is sponsoring Heart of Technology's must-attend groovy event. Embodying the spirit of San Francisco's Summer of Love, the Love IP Party is the social celebrates the creative thinkers, the IP revolution, and brotherly love to support the Guardian Scholars Program at San Jose State University. It's going to be far out, man! So get your best flower child outfit together and join us on June 8 at Jillian's SF.