Yesterday we added a new firmware, rev 9, to nature.atari.org. You need a JTAG cable to upgrade. The new FW contains a FIFO port register for queuing up to 56 blitter operations. The memory map has also been updated to reflect this.

Yesterday we added a new firmware, rev 9, to nature.atari.org. You need a JTAG cable to upgrade. The new FW contains a FIFO port register for queuing up to 56 blitter operations. The memory map has also been updated to reflect this.

That's great news. Can you explain what the advantage of this FIFO port register is?

And do you plan to provide an ATARI installation program for this firmware?

I assume its to improve the speed at which blits are processed.The way it was done before was to either poll the blitter to see if it was finished or to respond to an interrupt triggered when the blitter is finished.Both ways introduce latency/overhead. The interrupt way I guess is the preferred way but it involves responding to the interrupt so if you have many blits a lot of time would be spent in the interrupt code just dealing with the interrupt itself, not only writing new blitter commands. This cost can now (if I understand this correctly) be spread across multiple (up to 9) blitter operations instead of being a cost per single blitter operation.

The amount of blitter operations that can be queued is 56 (and 9 registers for each operation is written). The FIFO helps us get away from using interupts, because they were freezing the machine too often, and we couldn't find the problem despite extensive searching using oscilloscope etc. And as deez points out, the FIFO solution also is a slightly faster way to handle things, because the CPU isn't interrupted all the time.

There is a very limited amount of block RAMs in the FPGA, which are used for this FIFO. Each BRAM is 2KB in size. With a 32bit data bus that gives us 512 longwords per BRAM. We would like to save the remaining BRAMs for other stuff.

instream wrote:There is a very limited amount of block RAMs in the FPGA, which are used for this FIFO. Each BRAM is 2KB in size. With a 32bit data bus that gives us 512 longwords per BRAM. We would like to save the remaining BRAMs for other stuff.

instream wrote:There is a very limited amount of block RAMs in the FPGA, which are used for this FIFO. Each BRAM is 2KB in size. With a 32bit data bus that gives us 512 longwords per BRAM. We would like to save the remaining BRAMs for other stuff.

Why not use SV Ram for that?

Well, that is of course possible, but then we would need to redesign the blitter much more.