--------------------------------------------------------------------------------------------------------------------------For any new CBDB orders/requests please feel free to use as usual: tech at esp8266-projects.com.

(**)
- Actually you have there 2 Boards for the price of one, a ESP8266 nEXT
Evo together with a AN1 nEXT Analog Extension Board that brings you a
18Bit ADC (autoscale 0-40V input!), 4x12Bit DAC, Precison Temperature
measurement, 8bit I/O port, etc. -------------------------------------------------------------------------------------------------------------------------

The devices consist of eight quasi-bidirectional ports, 100 kHz I2C-bus interface, threehardware address inputs and interrupt output operating between 2.5 V and 6 V. Thequasi-bidirectional port can be independently assigned as an input to monitor interruptstatus or keypads, or as an output to activate indicator devices such as LEDs. Systemmaster can read from the input port or write to the output port through a single register.

The active LOW open-drain interrupt output (INT) can be connected to the interrupt logicof the microcontroller and is activated when any input state differs from its correspondinginput port register state. It is used to indicate to the microcontroller that an input state haschanged and the device needs to be interrogated without the microcontroller continuouslypolling the input register via the I2C-bus.

Features :

I2C-bus to parallel port expander

100 kHz I2C-bus interface (Standard-mode I2C-bus)

Operating supply voltage 2.5 V to 6 V with non-overvoltage tolerant I/O held to VDD with 100uA current source

A first step in testing the AN-1 available functions and devices will
be to scan the nEXT I²C Bus and see if all the existing ones are alive
and responding to the I²C Master requests. Also will list any new added devices, if alive.

Using the SCANBUS program described in the Part 2 of the AN-1 Series, you can find very easy if your PCF8574 8Bit I/O Extension port is available on the nEXT Bus :

Software implementation

PCF8574 8Bit I/O port is a quasi-bidirectional I/O Port, same as Port 1,2,3 on the 8051 MCU, if you like.

A quasi-bidirectional I/O is an input or output port without using a direction control register.
Whenever the master reads the register, the value returned to master depends on the
actual voltage or status of the pin. At power on, all the ports are HIGH with a weak 100 uA
internal pull-up to VDD, but can be driven LOW by an internal transistor, or an external
signal. The I/O ports are entirely independent of each other, but each I/O octal is controlled by the same read or write data byte.

Advantages of the quasi-bidirectional I/O over totem pole I/O include:

Better for driving LEDs since the p-channel (transistor to VDD) is small, which saves die size and therefore cost. LED drive only requires an internal transistor to ground, while the LED is connected to VDD through a current-limiting resistor. Totem pole I/O have both n-channel and p-channel transistors, which allow solid HIGH and LOW output levels without a pull-up resistor — good for logic levels.

Simpler architecture — only a single register and the I/O can be both input and output at the same time. Totem pole I/O have a direction register that specifies the port pin direction and it is always in that configuration unless the direction is explicitlychanged.

Does not require a command byte. The simplicity of one register (no need for the pointer register or, technically, the command byte) is an advantage in some embedded systems where every byte counts because of memory or bandwidth limitations.

Testing I/O Port Output

There is only one register to control four possibilities of the port pin: Input HIGH, input
LOW, output HIGH, or output LOW.

Input HIGH: The master needs to write 1 to the register to set the port as an input mode if the device is not in the default power-on condition. The master reads the register to check the input status. If the external source pulls the port pin up to VDD or drives logic 1, then the master will read the value of 1.

Input LOW: The master needs to write 1 to the register to set the port to input mode if the device is not in the default power-on condition. The master reads the register to check the input status. If the external source pulls the port pin down to VSS or drives logic 0, which sinks the weak 100uA current source, then the master will read the value of 0.

Output HIGH: The master writes 1 to the register. There is an additional ‘accelerator’ or strong pull-up current when the master sets the port HIGH. The additional strong pull-up is only active during the HIGH time of the acknowledge clock cycle. This accelerator current helps the port’s 100uA current source make a faster rising edge into a heavily loaded output, but only at the start of the acknowledge clock cycle to avoid bus contention if an external signal is pulling the port LOW to VSS/driving the port with logic 0 at the same time. After the half clock cycle there is only the 100uA current source to hold the port HIGH.

Output LOW: The master writes 0 to the register. There is a strong current sink transistor that holds the port pin LOW. A large current may flow into the port, which could potentially damage the part if the master writes a 0 to the register and an external source is pulling the port HIGH at the same time.

Simple quasi-bidirectional I/O example

In our case, to light-up our LED's we will use the last option, Output LOW!