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Digital Implementation Forums

Nanoroute stops at Placement blockage

Started by schnufff on 18 Apr 2013 3:38 AM. Topic has 7 replies and 34910 views.
Last post on 24 Apr 2013 5:08 AM by Kari.

In my design with 5 cores I have a Placement blockage around each core. This was suggested by Kari to stop sroute from connecting all follow pins together. But now CTS and also nanoroute stops routing all signal that run from the cores trough the blockage to the IO pads.

I though its a placement blockage and not a routing blockage. Trial route works fine, but produces a lot of violations. What can I do to

The placement blockage won't block routing. Something else is going on here. Can you turn on the routing grids to make sure they cover the area between the core and I/O? (they're called Pref Track, you can check layer by layer). If those look good, can you complete one of these routes by hand? Trying that may show error markers or something that leads you to the cause. Are the nets in question marked SPECIAL, or do they have a skip_routing attribute on them?

after reading the manual, I am able to route the wires manually without problems. I also can see the pins of the IOs at layer M2 and M3.

There is no attribute like special/power/whatever set to the wires. The lef files of the cells have CLASS PAD INOUT, the Pins have USE SIGNAL, and a PORT definition with the metal layers. In the def file, in SPECIALNETS are only the power nets and in NETS are all the signal as expected.I am unshure if tis an error within the lef files are some tool set these "fully connected" attribute wrong. Trial route is connecting the IO-wires correct! So the physical pins seem to be there.

Well, at least now we know the net CAN be connected, so that's good. Try using nanoroute for selected nets only, and just select ONE of these nets. Maybe the messasges will give more info about why it can't route.

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