A semiconductor device includes conductive features within a gate electrode level region that are each fabricated from respective originating rectangular-shaped layout features having its centerline aligned parallel to a first direction. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along second and third gate electrode tracks, respectively. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device.

Claim:

What is claimed is:

1. An integrated circuit, comprising: a gate electrode level region having at least six adjacently positioned gate electrode feature layout channels, each gate electrodefeature layout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, each gate electrode feature layout channel having a substantially equal length in the first direction, wherein eachof the at least six adjacently positioned gate electrode feature layout channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a first line end spacing and a second end located adjacent to asecond line end spacing, wherein each gate level feature forms an electrically conductive path extending between its first and second ends, wherein the gate electrode level region includes a first gate level feature that forms a gate electrode of a firsttransistor of a first transistor type and a gate electrode of a first transistor of a second transistor type, wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of a second transistor of the firsttransistor type, wherein any transistor having its gate electrode formed by the second gate level feature is of the first transistor type, wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of a secondtransistor of the second transistor type, wherein any transistor having its gate electrode formed by the third gate level feature is of the second transistor type, wherein the gate electrode level region includes a fourth gate level feature that forms agate electrode of a third transistor of the first transistor type, wherein any transistor having its gate electrode formed by the fourth gate level feature is of the first transistor type, wherein the gate electrode level region includes a fifth gatelevel feature that forms a gate electrode of a third transistor of the second transistor type, wherein any transistor having its gate electrode formed by the fifth gate level feature is of the second transistor type, wherein the gate electrode levelregion includes a sixth gate level feature that forms a gate electrode of a fourth transistor of the first transistor type and a gate electrode of a fourth transistor of the second transistor type, wherein the gate electrode of the second transistor ofthe first transistor type is substantially co-aligned with the gate electrode of the second transistor of the second transistor type along a first common line of extent in the first direction, and wherein the second gate level feature is separated fromthe third gate level feature by a first line end spacing as measured in the first direction, wherein the gate electrode of the third transistor of the first transistor type is substantially co-aligned with the gate electrode of the third transistor ofthe second transistor type along a second common line of extent in the first direction, and wherein the fourth gate level feature is separated from the fifth gate level feature by a second line end spacing as measured in the first direction, wherein thegate electrodes of the second and third transistors of the first transistor type are positioned between the gate electrodes of the first and fourth transistors of the first transistor type in the second direction, and wherein the gate electrodes of thesecond and third transistors of the second transistor type are positioned between the gate electrodes of the first and fourth transistors of the second transistor type in the second direction; a first gate contact defined to physically contact the firstgate level feature; a second gate contact defined to physically contact the second gate level feature; a third gate contact defined to physically contact the third gate level feature; a fourth gate contact defined to physically contact the fourth gatelevel feature; a fifth gate contact defined to physically contact the fifth gate level feature; a sixth gate contact defined to physically contact the sixth gate level feature, wherein the first, second, third, and fourth transistors of the firsttransistor type are collectively separated from the first, second, third, and fourth transistors of the second transistor type by an inner portion of the gate electrode level region, wherein each of the second, third, fourth, and fifth gate contacts islocated over the inner portion of the gate electrode level region, wherein the third gate contact is offset in the first direction from the fourth gate contact, and wherein either a) the second gate contact is offset in the first direction from thefourth gate contact, or b) the third gate contact is offset in the first direction from the fifth gate contact; and a plurality of interconnect level regions formed above the gate electrode level region; and a first electrical connection defined toelectrically connect the second gate level feature to the fifth gate level feature, the first electrical connection defined to extend through only one interconnect level region of the plurality of interconnect level regions, the first electricalconnection including one or more interconnect conductors located within the one interconnect level region, wherein each of the one or more interconnect conductors of the first electrical connection within the one interconnect level region islinear-shaped.

2. An integrated circuit as recited in claim 1, wherein the gate electrodes of the first, second, third, and fourth transistors of the first transistor type are positioned according to a gate pitch such that a distance measured in the seconddirection between first-direction-oriented centerlines of any two of the gate electrodes of the first, second, third, and fourth transistors of the first transistor type is substantially equal to an integer multiple of the gate pitch, and wherein thegate electrodes of the first, second, third, and fourth transistors of the second transistor type are positioned according to the gate pitch such that a distance measured in the second direction between first-direction-oriented centerlines of any two ofthe gate electrodes of the first, second, third, and fourth transistors of the second transistor type is substantially equal to an integer multiple of the gate pitch.

3. An integrated circuit as recited in claim 2, wherein the gate electrode level region includes a seventh gate level feature that forms a gate electrode of a fifth transistor of the first transistor type and a gate electrode of a fifthtransistor of the second transistor type.

4. An integrated circuit as recited in claim 3, wherein all gate level features within the gate electrode level region are linear shaped and extend lengthwise in the first direction.

5. An integrated circuit as recited in claim 4, wherein the gate electrode level region includes an eighth gate level feature that does not form a gate electrode of a transistor, the eighth gate level feature positioned such that a distance asmeasured in the second direction between a first-direction-oriented centerline of the eighth gate level feature and a first-direction-oriented centerline of a gate electrode of a transistor within the gate electrode level region is substantially equal toan integer multiple of the gate pitch.

6. An integrated circuit as recited in claim 5, wherein the third and fourth gate level features are electrically connected to each other through a second electrical connection that extends in part through the one interconnect level regionthrough which the first electrical connection extends, the second electrical connection including one or more interconnect conductors located within the one interconnect level region, wherein each of the one or more interconnect conductors of the secondelectrical connection within the one interconnect level region is linear-shaped.

7. An integrated circuit as recited in claim 1, wherein the second gate level feature has an extension distance extending away from the second gate contact in the first direction away from the gate electrode of the second transistor of thefirst transistor type, wherein the third gate level feature has an extension distance extending away from the third gate contact in the first direction away from the gate electrode of the second transistor of the second transistor type, wherein thefourth gate level feature has an extension distance extending away from the fourth gate contact in the first direction away from the gate electrode of the third transistor of the first transistor type, wherein the fifth gate level feature has anextension distance extending away from the fifth gate contact in the first direction away from the gate electrode of the third transistor of the second transistor type, and wherein at least two of the extension distances of the second, third, fourth, andfifth gate level features are different.

8. An integrated circuit as recited in claim 7, wherein two of the second, third, fourth, and fifth gate level features has a different length as measured in the first direction.

9. An integrated circuit as recited in claim 8, wherein all gate electrodes within the gate electrode level region are positioned according to a gate pitch such that a distance measured in the second direction between first-direction-orientedcenterlines of any two gate electrodes within the gate electrode level region is substantially equal to an integer multiple of the gate pitch.

10. An integrated circuit as recited in claim 9, wherein each gate level feature within the gate electrode level region is linear-shaped.

11. An integrated circuit as recited in claim 10, wherein the gate electrodes of the first and second transistors of the first transistor type are separated by the gate pitch as measured in the second direction between their respectivelengthwise centerlines, and wherein the gate electrodes of the second and third transistors of the first transistor type are separated by the gate pitch as measured in the second direction between their respective lengthwise centerlines, and wherein thegate electrodes of the third and fourth transistors of the first transistor type are separated by the gate pitch as measured in the second direction between their respective lengthwise centerlines, and wherein the gate electrodes of the first and secondtransistors of the second transistor type are separated by the gate pitch as measured in the second direction between their respective lengthwise centerlines, and wherein the gate electrodes of the second and third transistors of the second transistortype are separated by the gate pitch as measured in the second direction between their respective lengthwise centerlines, and wherein the gate electrodes of the third and fourth transistors of the second transistor type are separated by the gate pitch asmeasured in the second direction between their respective lengthwise centerlines.

12. An integrated circuit as recited in claim 10, wherein the third and fourth gate level features are electrically connected to each other through a second electrical connection that extends in part through the one interconnect level regionthrough which the first electrical connection extends, the second electrical connection including one or more interconnect conductors located within the one interconnect level region, wherein each of the one or more interconnect conductors of the secondelectrical connection within the one interconnect level region is linear-shaped.

13. An integrated circuit as recited in claim 1, wherein each gate level feature within the gate electrode level region is linear-shaped.

14. An integrated circuit as recited in claim 13, wherein the gate electrodes of the first and second transistors of the first transistor type are separated by a gate pitch as measured in the second direction between their respective lengthwisecenterlines, and wherein the gate electrodes of the second and third transistors of the first transistor type are separated by the gate pitch as measured in the second direction between their respective lengthwise centerlines, and wherein the gateelectrodes of the third and fourth transistors of the first transistor type are separated by the gate pitch as measured in the second direction between their respective lengthwise centerlines, and wherein the gate electrodes of the first and secondtransistors of the second transistor type are separated by the gate pitch as measured in the second direction between their respective lengthwise centerlines, and wherein the gate electrodes of the second and third transistors of the second transistortype are separated by the gate pitch as measured in the second direction between their respective lengthwise centerlines, and wherein the gate electrodes of the third and fourth transistors of the second transistor type are separated by the gate pitch asmeasured in the second direction between their respective lengthwise centerlines.

15. An integrated circuit as recited in claim 14, wherein all gate level features within the gate electrode level region are positioned according to the gate pitch such that a distance measured in the second direction betweenfirst-direction-oriented centerlines of two adjacently placed gate level features within the gate electrode level region is substantially equal to the gate pitch.

16. An integrated circuit as recited in claim 15, wherein the second gate level feature has an extension distance extending away from the second gate contact in the first direction away from the gate electrode of the second transistor of thefirst transistor type, wherein the third gate level feature has an extension distance extending away from the third gate contact in the first direction away from the gate electrode of the second transistor of the second transistor type, wherein thefourth gate level feature has an extension distance extending away from the fourth gate contact in the first direction away from the gate electrode of the third transistor of the first transistor type, wherein the fifth gate level feature has anextension distance extending away from the fifth gate contact in the first direction away from the gate electrode of the third transistor of the second transistor type, and wherein at least two of the extension distances of the second, third, fourth, andfifth gate level features are different.

17. An integrated circuit as recited in claim 13, wherein the third and fourth gate level features are electrically connected to each other through a second electrical connection that extends in part through the one interconnect level regionthrough which the first electrical connection extends, the second electrical connection including one or more interconnect conductors located within the one interconnect level region, wherein each of the one or more interconnect conductors of the secondelectrical connection within the one interconnect level region is linear-shaped.

18. An integrated circuit as recited in claim 17, wherein all gate level features within the gate electrode level region are positioned according to a gate pitch such that a distance measured in the second direction betweenfirst-direction-oriented centerlines of two adjacently placed gate level features within the gate electrode level region is substantially equal to the gate pitch.

19. An integrated circuit as recited in claim 1, wherein a length of the second gate level feature as measured in the first direction is different than a length of the fourth gate level feature as measured in the first direction.

20. An integrated circuit as recited in claim 19, wherein a length of the third gate level feature as measured in the first direction is different than a length of the fifth gate level feature as measured in the first direction.

21. An integrated circuit as recited in claim 20, wherein all gate electrodes within the gate electrode level region are positioned according to a gate pitch such that a distance measured in the second direction between first-direction-orientedcenterlines of any two gate electrodes within the gate electrode level region is substantially equal to an integer multiple of the gate pitch.

22. An integrated circuit as recited in claim 21, wherein each gate level feature within the gate electrode level region is linear-shaped.

23. An integrated circuit as recited in claim 22, wherein the gate electrode level region includes a seventh gate level feature that does not form a gate electrode of a transistor.

24. An integrated circuit as recited in claim 23, wherein the second and third transistors of the first transistor type share a first diffusion region of a first diffusion type, wherein the second and third transistors of the second transistortype share a first diffusion region of a second diffusion type, and wherein the first diffusion region of the first diffusion type is electrically connected to the first diffusion region of the second diffusion type.

25. An integrated circuit as recited in claim 24, wherein the third and fourth gate level features are electrically connected to each other through a second electrical connection that extends in part through the one interconnect level regionthrough which the first electrical connection extends, the second electrical connection including one or more interconnect conductors located within the one interconnect level region, wherein each of the one or more interconnect conductors of the secondelectrical connection within the one interconnect level region is linear-shaped.

26. A method for creating a layout of an integrated circuit, comprising: operating a computer to define a gate electrode level region having at least six adjacently positioned gate electrode feature layout channels, each gate electrode featurelayout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, each gate electrode feature layout channel having a substantially equal length in the first direction, wherein each of theat least six adjacently positioned gate electrode feature layout channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a first line end spacing and a second end located adjacent to a second lineend spacing, wherein each gate level feature forms an electrically conductive path extending between its first and second ends, wherein the gate electrode level region includes a first gate level feature that forms a gate electrode of a first transistorof a first transistor type and a gate electrode of a first transistor of a second transistor type, wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of a second transistor of the first transistortype, wherein any transistor having its gate electrode formed by the second gate level feature is of the first transistor type, wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of a second transistorof the second transistor type, wherein any transistor having its gate electrode formed by the third gate level feature is of the second transistor type, wherein the gate electrode level region includes a fourth gate level feature that forms a gateelectrode of a third transistor of the first transistor type, wherein any transistor having its gate electrode formed by the fourth gate level feature is of the first transistor type, wherein the gate electrode level region includes a fifth gate levelfeature that forms a gate electrode of a third transistor of the second transistor type, wherein any transistor having its gate electrode formed by the fifth gate level feature is of the second transistor type, wherein the gate electrode level regionincludes a sixth gate level feature that forms a gate electrode of a fourth transistor of the first transistor type and a gate electrode of a fourth transistor of the second transistor type, wherein the gate electrode of the second transistor of thefirst transistor type is substantially co-aligned with the gate electrode of the second transistor of the second transistor type along a first common line of extent in the first direction, and wherein the second gate level feature is separated from thethird gate level feature by a first line end spacing as measured in the first direction, wherein the gate electrode of the third transistor of the first transistor type is substantially co-aligned with the gate electrode of the third transistor of thesecond transistor type along a second common line of extent in the first direction, and wherein the fourth gate level feature is separated from the fifth gate level feature by a second line end spacing as measured in the first direction, wherein the gateelectrodes of the second and third transistors of the first transistor type are positioned between the gate electrodes of the first and fourth transistors of the first transistor type in the second direction, and wherein the gate electrodes of the secondand third transistors of the second transistor type are positioned between the gate electrodes of the first and fourth transistors of the second transistor type in the second direction; operating a computer to define a first gate contact defined tophysically contact the first gate level feature; operating a computer to define a second gate contact defined to physically contact the second gate level feature; operating a computer to define a third gate contact defined to physically contact thethird gate level feature; operating a computer to define a fourth gate contact defined to physically contact the fourth gate level feature; operating a computer to define a fifth gate contact defined to physically contact the fifth gate level feature; operating a computer to define a sixth gate contact defined to physically contact the sixth gate level feature, wherein the first, second, third, and fourth transistors of the first transistor type are collectively separated from the first, second,third, and fourth transistors of the second transistor type by an inner portion of the gate electrode level region, wherein each of the second, third, fourth, and fifth gate contacts is located over the inner portion of the gate electrode level region,wherein the third gate contact is offset in the first direction from the fourth gate contact, and wherein either a) the second gate contact is offset in the first direction from the fourth gate contact, or b) the third gate contact is offset in the firstdirection from the fifth gate contact; and operating a computer to define a plurality of interconnect level regions formed above the gate electrode level region; and operating a computer to define a first electrical connection to electrically connectthe second gate level feature to the fifth gate level feature, the first electrical connection defined to extend through only one interconnect level region of the plurality of interconnect level regions, the first electrical connection including one ormore interconnect conductors located within the one interconnect level region, wherein each of the one or more interconnect conductors of the first electrical connection within the one interconnect level region is linear-shaped.

27. A computer readable medium having program instructions stored thereon for generating a layout of an integrated circuit, comprising: program instructions for defining a gate electrode level region having at least six adjacently positionedgate electrode feature layout channels, each gate electrode feature layout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, each gate electrode feature layout channel having asubstantially equal length in the first direction, wherein each of the at least six adjacently positioned gate electrode feature layout channels includes at least one gate level feature, each gate level feature having a first end located adjacent to afirst line end spacing and a second end located adjacent to a second line end spacing, wherein each gate level feature forms an electrically conductive path extending between its first and second ends, wherein the gate electrode level region includes afirst gate level feature that forms a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type, wherein the gate electrode level region includes a second gate level featurethat forms a gate electrode of a second transistor of the first transistor type, wherein any transistor having its gate electrode formed by the second gate level feature is of the first transistor type, wherein the gate electrode level region includes athird gate level feature that forms a gate electrode of a second transistor of the second transistor type, wherein any transistor having its gate electrode formed by the third gate level feature is of the second transistor type, wherein the gateelectrode level region includes a fourth gate level feature that forms a gate electrode of a third transistor of the first transistor type, wherein any transistor having its gate electrode formed by the fourth gate level feature is of the firsttransistor type, wherein the gate electrode level region includes a fifth gate level feature that forms a gate electrode of a third transistor of the second transistor type, wherein any transistor having its gate electrode formed by the fifth gate levelfeature is of the second transistor type, wherein the gate electrode level region includes a sixth gate level feature that forms a gate electrode of a fourth transistor of the first transistor type and a gate electrode of a fourth transistor of thesecond transistor type, wherein the gate electrode of the second transistor of the first transistor type is substantially co-aligned with the gate electrode of the second transistor of the second transistor type along a first common line of extent in thefirst direction, and wherein the second gate level feature is separated from the third gate level feature by a first line end spacing as measured in the first direction, wherein the gate electrode of the third transistor of the first transistor type issubstantially co-aligned with the gate electrode of the third transistor of the second transistor type along a second common line of extent in the first direction, and wherein the fourth gate level feature is separated from the fifth gate level featureby a second line end spacing as measured in the first direction, wherein the gate electrodes of the second and third transistors of the first transistor type are positioned between the gate electrodes of the first and fourth transistors of the firsttransistor type in the second direction, and wherein the gate electrodes of the second and third transistors of the second transistor type are positioned between the gate electrodes of the first and fourth transistors of the second transistor type in thesecond direction; program instructions for defining a first gate contact defined to physically contact the first gate level feature; program instructions for defining a second gate contact defined to physically contact the second gate level feature; program instructions for defining a third gate contact defined to physically contact the third gate level feature; program instructions for defining a fourth gate contact defined to physically contact the fourth gate level feature; program instructionsfor defining a fifth gate contact defined to physically contact the fifth gate level feature; program instructions for defining a sixth gate contact defined to physically contact the sixth gate level feature, wherein the first, second, third, and fourthtransistors of the first transistor type are collectively separated from the first, second, third, and fourth transistors of the second transistor type by an inner portion of the gate electrode level region, wherein each of the second, third, fourth, andfifth gate contacts is located over the inner portion of the gate electrode level region, wherein the third gate contact is offset in the first direction from the fourth gate contact, and wherein either a) the second gate contact is offset in the firstdirection from the fourth gate contact, or b) the third gate contact is offset in the first direction from the fifth gate contact; and program instructions for defining a plurality of interconnect level regions formed above the gate electrode levelregion; and program instructions for defining a first electrical connection to electrically connect the second gate level feature to the fifth gate level feature, the first electrical connection defined to extend through only one interconnect levelregion of the plurality of interconnect level regions, the first electrical connection including one or more interconnect conductors located within the one interconnect level region, wherein each of the one or more interconnect conductors of the firstelectrical connection within the one interconnect level region is linear-shaped.