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Abstract

Disclosed is a device which prevents charge sharing in dynamic circuits. A typical dynamic circuit includes an "N-stack" which connects the dynamic node to ground and is where the majority of the logic function is carried out. The "N-stack" is built up from nfet devices and generally includes a number of internal nodes and capacitances which may be charged to the opposite state of the primary dynamic node. When an input switches, the primary dynamic node capacitance is connected to the internal node capacitances and a charge sharing noise error may result.

Country

United States

Language

English (United States)

This text was extracted from an ASCII text file.

This is the abbreviated version, containing approximately
53% of the total text.

A Method for Preventing Charge Sharing Noise in Dynamic
Circuits

Disclosed is a
device which prevents charge sharing in
dynamic circuits. A typical dynamic
circuit includes an "N-stack"
which connects the dynamic node to ground and is where the majority
of the logic function is carried out.
The "N-stack" is built up from
nfet devices and generally includes a number of internal nodes and
capacitances which may be charged to the opposite state of the
primary dynamic node. When an input
switches, the primary dynamic
node capacitance is connected to the internal node capacitances and a
charge sharing noise error may result.

One way to avoid
charge sharing is to ensure that the
internal nodes are charged toward the same polarity voltage as the
primary dynamic node (typically VDD) before any inputs evaluate.
There must be a path between the internal node and the appropriate
supply when the circuit is in the standby state (to counteract
leakage), but no path between VDD and GND when the circuit has
evaluated.

This invention
shows how to charge the internal nodes
towards VDD, thus preventing charge sharing within the constraints
identified above. The basic idea is to
insert an NMOS device with
the source connected to the protected node (to be charged), the drain
connected to VDD, and the gate connected to an additional logic
circuit. The additional logic circuit
has the same (or subset)
inputs as the original circuit (and may include its output) and will
pro...