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The following options can be used for clocking IDDR2 and ODDR2 primitives.

When performance is not critical, use a single DCM output to drive both clock (C0) and the inverted clock (C1) using local inversion. Works with or without IODELAY2.

For the highest performance, use two DCM outputs with separate BUFGs with 180 phase difference. Works with or without IODELAY2. See Figure 1-18.

If not using a DCM, then the GCLK input should directly drive two BUFIO2s. Use two BUFIO2s with the first BUFIO2 (USE_DOUBLER) for C0 and an inverted clock using BUFIO2 (I_INVERT = TRUE) for C1 connected to the same GCLK. FPGA logic is driven by BUFG (C0 BUFIO2-DIVCLK). There is a routing delay through the BUFG.