Comments

The write recovery time of both registers should match. Since mode register
doesn't support cycles of 9,11,13,15, we should use next higher number for
both registers.
Signed-off-by: York Sun <yorksun@freescale.com>
---
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 28 ++++++++++++++++++++++++----
1 files changed, 24 insertions(+), 4 deletions(-)