Under the Hood: Uncovering hidden chip costs

The proportion of semiconductor content is increasing in almost everything we own. For some large manufacturers of consumer electronics, semiconductors are the single largest contributor to finished-goods costs. A clear understanding of the chip supplier's cost structures can bolster the OEM's negotiating position.

All chips are not created equal, and even devices that look markedly similar can have dramatically different pricing. This statement is perhaps obvious, but the realities of chip pricing are often overlooked during price negotiations.

For example, the device shown in the accompanying images may look like a simple 16-lead SOIC and would therefore intuitively be priced at perhaps a few dimes in high volumes. In reality, it incorporates a rather complex BiCMOS die with a second MEMS accelerometer device and is priced at more than three times that amount. None of this is obvious until a qualified analyst starts to take a good, close look under the hood.

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There are several fundamental rules that must be considered when determining the cost of an integrated circuit.

Die area does not follow Moore's LawA great many factors conspire to prevent die area from scaling as quickly as the transistor count per unit area of silicon. Analog, RF and power circuits do not scale at the same rate as logic.

Another major factor that contributes to chip price is wafer volume. The raw die count per wafer on various process nodes, beginning with a fictitious 8 x 8-mm die, is shown in the top graph below. The expected die count is shown as the blue line for 200-mm and 300-mm wafers. A more realistic view is shown by the red line, which assumes the I/O circuitry and analog circuitry, about 40 percent of the original fictional device, only scales at about half the rate of the digital logic. The graph shows we lose an order of magnitude in dice/wafer over several process generations because of the things on the dice that do not scale as quickly as digital transistors.

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The leading edge is an expensive place to beA 300-mm, 45-nm wafer is nominally 10 times more expensive than a 200-mm, 250-nanometer wafer. Further, defect densities are much higher, as the process has not yet matured. The bottom graph shows the "known-good die" cost of the same fictitious die, ported to various processes.

There are a couple of interesting conclusions to draw. First, the yielded-dice cost on 200-mm fabs, at all four of the process nodes from 250 nm down to 110 nm, really does not vary much. This indicates that the gain in raw dice per wafer is offset by the penalties in analog scaling factors as discussed, as well as wafer price and defect density. Second, die costs at 130 nm and 110 nm are greater on 300-mm wafers (blue squares) than on 200-mm wafers.

Semiconductor test is becoming the biggest contributor to cost of manufacture Capital equipment costs for standard digital testers are very low, and with test standards such as JTAG, test costs/hour for digital devices are a small proportion of the overall device cost, typically less than 5 percent. As devices become more integrated, they can become dramatically more expensive. A high-speed analog tester can cost hundreds of dollars per hour, and the proportion of the overall device cost attributed to final test can be as high as 30 percent.

Chip companies need to recoup development costsA recent Frost & Sullivan report tracking mask cost trends shows mask costs at 90 nm are about $800,000, while they are $1.2 million at the 65-nm node. Of course, mask costs, like wafer prices, drop over time. By comparison, a mask set at 0.35 µm is almost freein the ballpark of tens of thousands of dollarsand 0.35µm is still a very attractive process for small-volume, mixed-signal devices. Most chip developments require at least two mask sets to get to production. For a 45-nm node, the mask costs alone for chip development will be several million dollars. A spin is relatively inexpensive in terms of engineering costs, but a "ground up chip" design, especially in an advanced process node, is a multimillion-dollar proposition. One reason chip startups have waned in recent years is the "time to money" associated with a system-on-chip development. Unless a chip sells in very high volumes (sometimes many millions), the amortization of nonrecurring development costs and mask expenses can overshadow the marginal costs of manufacturing, assembly and test.

Knowing the subtleties of a chip's cost structure can help large chip consumers understand what a fair market price is for the part. In the end, the give-and-take game of price negotiation is much more equitable if all the players have a better understanding of all the rules.

Rob Hilkes(robh@semiconductor.com) is technology manager, analog and mixed signal, at Semiconductor Insights, a CMP Technology company specializing in in-depth technical investigation of ICs and electronic systems.