From grupp at snowmass.Stanford.EDU Tue Apr 1 12:52:54 2003
From: grupp at snowmass.Stanford.EDU (Dan Grupp)
Date: Tue, 1 Apr 2003 12:52:54 -0800 (PST)
Subject: Wet etching of Si (110)
In-Reply-To:
Message-ID:
My favorite paper is:
"Micromachining of Silicon Mechanical Structures", G. Kaminsky, Mat. Res.
Soc. Symp. Proc. Vol. 76, p. 111 (1987).
Has etch rate tables of different Si orientations and etchants. beautiful
SEM of trenches 8 um deep, 0.2 um wide!
If you want, you can xerox my copy.
-dan
On Mon, 31 Mar 2003, Yahong Yao wrote:
> Dear Labmembers,
>
> I want to make a through hole (500um*500um) in Si substrate with wet etching
> (KOH or TMAH). I have done a lot of experiments with Si (100). As we all
> know, for Si (100), we need to open the mask much larger than the dimensions
> we need on the other side. Now I don't have the extra areas to waste on the
> wafer. I am thinking of using Si (110) which should give a straight
> profile, but don't have much experience with that. Can anyone share some
> insights, for example, etching rates, possible pitfalls? Most literatures
> also talk about Si(100) instead of Si(110), why? Thank you very much.
>
> Best Regards,
> Yahong
>
> _________________________________________________________________
> Add photos to your e-mail with MSN 8. Get 2 months FREE*.
> http://join.msn.com/?page=features/featuredemail
>
>
---------------------------------------------------------------------------
Dr. Daniel Grupp, Visiting Scholar
Center for Integrated Systems
Stanford University
Stanford, CA 94305
(650) 724-6911
FAX: 723-4659
---------------------------------------------------------------------------
From shiwei20012002 at yahoo.com Tue Apr 1 13:06:49 2003
From: shiwei20012002 at yahoo.com (Wei Shi)
Date: Tue, 1 Apr 2003 13:06:49 -0800 (PST)
Subject: Big Trench on Cu
In-Reply-To:
Message-ID: <20030401210649.36071.qmail@web21205.mail.yahoo.com>
Hi,
I want to make 2 trenches on copper substrate, the sizes are:
(1). 100 micron deep and 100 micron wide.
(2). 50 micron deep and 50 micron wide.
Dose anyone have any good solution to it?
Thanks,
Wei
---------------------------------
Do you Yahoo!?
Yahoo! Tax Center - File online, calculators, forms, and more
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From rcrane at snf.stanford.edu Tue Apr 1 15:47:54 2003
From: rcrane at snf.stanford.edu (Dick Crane)
Date: Tue, 01 Apr 2003 15:47:54 -0800
Subject: brief gas shutdown Monday 4/7 0630-0730
Message-ID: <3E8A252A.A6C1F556@snf.stanford.edu>
Etch, furnace, and RTA users,
There will be a brief shutdown of all process gases (excluding the
freons) and oxygen and hydrogen on Monday, April 7, from 0630 to 0730,
to allow new gas monitor circuits to be connected and tested. This work
supports the Thermco furnace project. I have made reservations on all
affected tools. The work should require a 15 minute interruption.
Sorry for any inconvenience and thanks for your continued support,
Dick
From grupp at snowmass.Stanford.EDU Tue Apr 1 21:00:14 2003
From: grupp at snowmass.Stanford.EDU (Dan Grupp)
Date: Tue, 1 Apr 2003 21:00:14 -0800 (PST)
Subject: need an SOI wafer
Message-ID:
Hello,
Does anyone haev an SOI wafer with n-type Si?
Thanks much,
Dan
---------------------------------------------------------------------------
Dr. Daniel Grupp, Visiting Scholar
Center for Integrated Systems
Stanford University
Stanford, CA 94305
(650) 724-6911
FAX: 723-4659
---------------------------------------------------------------------------
From mail4estrada at netscape.net Wed Apr 2 14:05:12 2003
From: mail4estrada at netscape.net (mail4estrada at netscape.net)
Date: Thu, 3 Apr 2003 00:05:12 +0200
Subject: PRIVATE EMAIL CONTACT
Message-ID:
Greetings to you Dear Prospective Friend & Partner,
With warm heart I offer my friendship, and I hope this mail meets you in good time. However strange or surprising this contact might seem to you as we have not met personally or had any dealings in the past, I humbly ask that you take due consideration of its importance and the immense benefit it will be to you.
May I properly introduce my humble self to you. I am Dr. Mrs. Luisa Ejercito Estrada, wife of ousted President Joseph Ejercito Estrada of the Philippines. After careful consideration based on my instincts, I have resolved to contact you for your most needed assistance in this manner. I duly apologize for infringing on your privacy, if this contact is not acceptable to you, as I make this proposal to you as a person of integrity. The confidentiality of my contact with you is of absolute importance due to my present political status as a senator.
You may not be very conversant with proceedings of the political turmoil in my country which led to my husband?s depose from power. Expressing this from my point of view may be biased in your opinion, hence you may read the following articles to have your assertion from a neutral point of view.
http://www.angelfire.com/il/saintjareth/erap.html
http://www.time.com/time/asia/magazine/2001/0129/cover1.html
http://www.cnn.com/2001/WORLD/asiapcf/southeast/02/13/bc.philippines.loiestrada/
http://news.bbc.co.uk/1/hi/world/asia-pacific/1063976.stm
To the point. The pressure on my family is overwhelming, and we desire to safeguard our future through investments in commercial and residential properties abroad as well as profitable ventures. Hence my proposal to you to render me your most needed assistance in this regard.
The fund to be invested is in currently in a safety deposit trunk with a private security firm in Europe lodged in my name. The trunk is stocked with hard currency (US Dollars) totalling $18,500,000. Due to the embarrassing surveillance on my family?s activities, the need to contact a capable and trustworthy foreigner without a trace to our family handle this investment arose, and I hope we have found such a person in you.
If you are willing and able to render me your most needed assistance, your role in this project will be to act on my behalf as a trustee to receive the safety deposit containing the funds from the Security firm and proceed with the investments on our behalf immediately.
I want to assure you that this transaction is completely safe and risk free. The reason for having a cash safety deposit was a fallback plan of my family, as we envisaged this situation we are in today. At the moment, all my husband?s accounts have been frozen, and mine under investigation.
At this point, I want to reemphasise the need for utmost confidentiality and secrecy for the safety of this transaction and our investments you will be handling.
For your reliable assistance, I am offering you 15 %($2,775,000) of the funds.
I thank you in advance as I anticipate your assistance in enabling me achieve this goal. On hearing from you, I will be contacting you further with details of the mutual conclusion of the transaction. As you may understand, due to the possibility of bugging, it is not safe to communicate with me via phone or fax. This is why I have communicated with you with my private email address, and I like us to keep this way, for the safety of this transaction, until we meet in the near future.
Please contact me whether or not you are interested in assisting me. This will enable me make alternative plans, in the event of non-interest on your part.
With warm regards,
Dr. Mrs. L. Estrada.
From grupp at snowmass.Stanford.EDU Thu Apr 3 18:52:50 2003
From: grupp at snowmass.Stanford.EDU (Dan Grupp)
Date: Thu, 3 Apr 2003 18:52:50 -0800 (PST)
Subject: paper available Re: Wet etching of Si (110)
In-Reply-To: <3E8B542D.8CFC1F4D@stanford.edu>
Message-ID:
A number of people expressed interest in the paper below, so i've xeroxed
a copy and hung it on the board in the hallway next to the SNF papers
board. feel free to xerox it and rehang for others. hope it is of use.
-dan
> Dan Grupp wrote:
>
> > My favorite paper is:
> > "Micromachining of Silicon Mechanical Structures", G. Kaminsky, Mat. Res.
> > Soc. Symp. Proc. Vol. 76, p. 111 (1987).
> >
> > Has etch rate tables of different Si orientations and etchants. beautiful
> > SEM of trenches 8 um deep, 0.2 um wide!
> >
> > If you want, you can xerox my copy.
> > -dan
> >
> > On Mon, 31 Mar 2003, Yahong Yao wrote:
> >
> > > Dear Labmembers,
> > >
> > > I want to make a through hole (500um*500um) in Si substrate with wet etching
> > > (KOH or TMAH). I have done a lot of experiments with Si (100). As we all
> > > know, for Si (100), we need to open the mask much larger than the dimensions
> > > we need on the other side. Now I don't have the extra areas to waste on the
> > > wafer. I am thinking of using Si (110) which should give a straight
> > > profile, but don't have much experience with that. Can anyone share some
> > > insights, for example, etching rates, possible pitfalls? Most literatures
> > > also talk about Si(100) instead of Si(110), why? Thank you very much.
> > >
> > > Best Regards,
> > > Yahong
> > >
> > > _________________________________________________________________
> > > Add photos to your e-mail with MSN 8. Get 2 months FREE*.
> > > http://join.msn.com/?page=features/featuredemail
> > >
> > >
> >
> > ---------------------------------------------------------------------------
> > Dr. Daniel Grupp, Visiting Scholar
> > Center for Integrated Systems
> > Stanford University
> > Stanford, CA 94305
> > (650) 724-6911
> > FAX: 723-4659
> > ---------------------------------------------------------------------------
>
---------------------------------------------------------------------------
Dr. Daniel Grupp, Visiting Scholar
Center for Integrated Systems
Stanford University
Stanford, CA 94305
(650) 724-6911
FAX: 723-4659
---------------------------------------------------------------------------
From hsubkim at stanford.edu Fri Apr 4 00:50:42 2003
From: hsubkim at stanford.edu (Hyoungsub Kim)
Date: Fri, 4 Apr 2003 00:50:42 -0800
Subject: Etching mask for TMAH
References:
Message-ID: <003301c2fa87$4664b810$21970c80@HyoungsubKim>
Dear lab members.
These days, I'm trying to etch a small piece of Si (dia. 3mm) from the
backside using TMAH at my lab w/o patterning.
I want to make a small hole in the center to make TEM sample, however, it is
hard to find a suitable mask (like wax type) to cover unwanted area.
I tried several waxes but all are easily soluble in TMAH. It should be
easily removed after Si etching.
I would appreciate if anybody can let me know possible material.
Thanks a lot.
======================================================
Hyoungsub Kim
Ph.D Student
Materials Science and Engineering, Stanford
E-mail : hsubkim at stanford.edu
Phone : (O) 650-725-2616
(H) 650-497-3516
(FAX) 650-725-4034
Address : (O) Rm 203 McCullough Bldg, Stanford, CA94305
=======================================================
From rcrane at snf.stanford.edu Fri Apr 4 10:01:08 2003
From: rcrane at snf.stanford.edu (Dick Crane)
Date: Fri, 04 Apr 2003 10:01:08 -0800
Subject: [Fwd: Building open April 6, lock up valuables]
Message-ID: <3E8DC863.225B8BF7@snf.stanford.edu>
Dick Crane wrote:
> CIS/CISX building people,
>
> Sunday, April 6, is Stanford Community Day. CIS/CISX will be open for
> public access from 10:00 to 4:00. Although Stanford personnel will be
> present, I would advise you to lock offices, drawers, cabinets or remove
> valuables if you are not present during the open time. Cell phones, PDAs
> and laptops make inviting targets. We have not had problems during past
> Community Days, but there has been a few thefts from cubes/offices in
> the building last year.
>
> Thanks,
>
> Dick Crane
From hjkim at exch.hpl.hp.com Fri Apr 4 11:38:31 2003
From: hjkim at exch.hpl.hp.com (Kim, Han-jun)
Date: Fri, 4 Apr 2003 11:38:31 -0800
Subject: Etching mask for TMAH
Message-ID: <40700B4C02ABD5119F0000902787664404161A04@hplex1.hpl.hp.com>
Hi, Mr. Kim
I don't know if there's any wax, or polymer, withstanding
the base. In my experience, most of them didn't. Both oxide
and nitride work great, as you may know, except that a
long-time etch leaves some unwanted hillocks behind.
Some metals - like Au - are known to work also. But I don't
have much experience in this domain.
If making a mask hinders you from working on Si-materials,
you may use so called "soft lithography" with transparency
films, a laser printer and an old-fashioned contact printer
which doesn't care too much about the size and dimension of
the substrate.
Thanks!
Hanjun
===========================================
Han-Jun Kim Hewlett-Packard Lab.
(650) 857-8525 1501 Page Mill Rd.
(650) 857-8948 FAX MS 1198
hjkim at hpl.hp.com Palo Alto, CA 94304
===========================================
-----Original Message-----
From: Hyoungsub Kim [mailto:hsubkim at stanford.edu]
Sent: Friday, April 04, 2003 12:51 AM
To: labmembers at snf.stanford.edu
Subject: Etching mask for TMAH
Dear lab members.
These days, I'm trying to etch a small piece of Si (dia. 3mm) from the
backside using TMAH at my lab w/o patterning.
I want to make a small hole in the center to make TEM sample, however, it is
hard to find a suitable mask (like wax type) to cover unwanted area.
I tried several waxes but all are easily soluble in TMAH. It should be
easily removed after Si etching.
I would appreciate if anybody can let me know possible material.
Thanks a lot.
======================================================
Hyoungsub Kim
Ph.D Student
Materials Science and Engineering, Stanford
E-mail : hsubkim at stanford.edu
Phone : (O) 650-725-2616
(H) 650-497-3516
(FAX) 650-725-4034
Address : (O) Rm 203 McCullough Bldg, Stanford, CA94305
=======================================================
From mahnaz at snf.stanford.edu Mon Apr 7 11:17:48 2003
From: mahnaz at snf.stanford.edu (Mahnaz)
Date: Mon, 07 Apr 2003 11:17:48 -0700
Subject: Singe oven
Message-ID: <3E91C0CC.656BDAFC@snf.stanford.edu>
Hello all,
Since last week, we found the singe oven in the litho area off --3
times. This is totally unacceptable if you have a need or have any
questions please come and see me.
No one is allowed to change the temperatures of any of the ovens in the
litho area with the exception of one oven. Too many members relay on the
oven and is very disruptive when it changed or is off.
On the singe oven: Do not put the switch (right upper corner) on
timer it should stay on manual. That top portion is not a timer, by
putting it on a timer you actually turning the oven off.
mahnaz
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From xianliu at stanford.edu Mon Apr 7 14:31:47 2003
From: xianliu at stanford.edu (Xian Liu)
Date: Mon, 07 Apr 2003 14:31:47 -0700
Subject: Special University Ph. D. Oral Examination
Message-ID: <5.1.0.14.2.20030407143002.00a69830@xianliu.pobox.stanford.edu>
>Special University Ph. D. Oral Examination
>
>Arsenic-Doped Silicon by Molecular Beam Epitaxy
>
>Xian Liu
>Department of Materials Science and Engineering
>Stanford University
>
>Thursday, April 10th, 2003; 3pm
>Center for Integrated Systems Extension (CISX) Auditorium
>(Refreshments will be served at 2:45pm)
>
>
>Abstract
>
>
>As MOSFETs scale to the deep-submicron regime, the need for ultra-shallow
>junctions and modulation-doped channel structures has brought an
>increasing demand for silicon epitaxial layers with abrupt doping
>profiles. For these devices, arsenic is an attractive N-type dopant
>because of its high solubility and low diffusion rate, but suffers from
>severe surface segregation during epitaxy, making high-concentration
>incorporation with abrupt transitions difficult.
>
>This talk describes arsenic surface segregation and incorporation during
>Si molecular beam epitaxy (MBE) using a unique combination of solid and
>gas sources. Using disilane gas for silicon and dimer molecules for
>arsenic sources, it is shown that relatively high substrate temperatures
>are needed to activate surface reactions during growth. Surface
>segregation of arsenic under these conditions is investigated and a new
>segregation energy model is proposed based on surface 2-D islanding of
>arsenic. Replacing disilane with an elemental silicon source, on the other
>hand, eliminates surface reaction steps and enables deposition at lower
>temperatures, where surface segregation becomes kinetically suppressed.
>Under these conditions extremely high arsenic concentrations can be
>achieved with relatively low surface coverage. In this work, we
>demonstrated Si (100) epilayers with As concentrations up to 4 x 1021 cm-3
>and doping transitions better than 3 and 2 nm/dec at the start and end of
>arsenic-doped growth, respectively. Electrical properties of heavily doped
>as-grown and annealed materials are discussed and correlated to
>atomic-scale defects. While electrical properties in thicker epilayers are
>limited by bulk values, confining dopants to a thin sheet a few nanometers
>thick leads to significant improvements in both dopant activation and
>carrier mobility. The former is correlated to suppressed arsenic
>clustering and the latter to quantum confinement. Effects of doping layer
>thickness and spacing are also discussed.
From alan.m.myers at intel.com Tue Apr 8 15:21:15 2003
From: alan.m.myers at intel.com (Myers, Alan M)
Date: Tue, 8 Apr 2003 15:21:15 -0700
Subject: Job openings at Intel Oregon
Message-ID: <8EF5A5A8A6DD6341BF5A9BBE81DA743295361F@orsmsx403.jf.intel.com>
Feel free to pass this on to your friends and colleagues who are not
affiliated with CIS but would be interested in this type of job. Please
send all correspondence to the person listed on the attached flier.
Alan
<>
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From jerabek at snf.stanford.edu Tue Apr 15 08:35:30 2003
From: jerabek at snf.stanford.edu (Paul Jerabek)
Date: Tue, 15 Apr 2003 08:35:30 -0700 (PDT)
Subject: LRS-18
Message-ID:
To whom it may concern,
LRS-18 mask writer has been down since Friday 4/11/03 with a serious
problem of stage interferometer. It's randomly quiting during a write
operation.Micronic field service is working to correct the problem.
At this time I have a backlog of about 60 masks.
-Paul
From sylviajs at stanford.edu Tue Apr 15 12:27:03 2003
From: sylviajs at stanford.edu (S. J. Smullin)
Date: Tue, 15 Apr 2003 12:27:03 -0700 (PDT)
Subject: weighing 1ug
Message-ID:
hi.
I want to determine the mass of small pieces of gold that are on the order
of a microgram. Does anyone know a way to determine the mass of such small
things? (or even how to weight 10 ug)
-Sylvia
From jerabek at snf.stanford.edu Wed Apr 16 12:02:50 2003
From: jerabek at snf.stanford.edu (Paul Jerabek)
Date: Wed, 16 Apr 2003 12:02:50 -0700 (PDT)
Subject: LRS-18 update
Message-ID:
Micronic field service found one of a guide rails on the system stage
unglued.This is not field repairable item since position of the rail is
extremaly precise.They have removed the stage and a granite base the stage
rides on and send it to Micronic-Sweden for factory repair.It will take
approximately 2 weeks to repair and reinstall.
People who have mask jobs in pipeline might consider sending their jobs to
an outside vendor such as:
-Compugraphics USA
141A Albright Way
Los Gatos, CA 95032
(408) 341-1606 tel.
(408) 866-2248 fax
-Image Technology,Inc.
821 San Antonio Rd.
Palo Alto,CA 94303
(650)494-3113 tel.
(650)494-2971 fax
www.image-tec.com
Their pricing per mask is comparable.People who used Image Tech. tell me
that their delivery time is shorter.
-Paul
From rcrane at snf.stanford.edu Thu Apr 17 08:58:11 2003
From: rcrane at snf.stanford.edu (Dick Crane)
Date: Thu, 17 Apr 2003 08:58:11 -0700
Subject: Possible brief gas shutdown Monday, 4/21 0630-0900
Message-ID: <3E9ECF13.8EA666ED@snf.stanford.edu>
Etch, furnace, and RTA users,
There is the possibility of a brief shutdown of all process gases
(excluding the freons) and oxygen and hydrogen on Monday, April 21, from
0630 to 0800, to allow new gas monitor circuits to be connected and
tested. The shutdown may occur only if there is an unanticipated
problem.
How does this affect your process? Maintenance staff will be standing by
to restart the gases within minutes of shutdown. Almost all gas lines
have sufficient pressure such that the gas user will not lose gas flow
for 5-45 minutes. The exemptions are the high flow gases such as H2 and
HCl to the EPI. The LP furnaces will be down at this time for the gas
tie-in work. If a shutdown does occur, it, most likely, will pass
unnoticed by the tools.
This work supports the Thermco furnace project.
Sorry for any inconvenience and thanks for your continued support,
Dick
From rajesh at t-ram.com Fri Apr 18 10:12:19 2003
From: rajesh at t-ram.com (Rajesh Gupta)
Date: Fri, 18 Apr 2003 10:12:19 -0700
Subject: Metal dep help
Message-ID: <40F9C31A3EE27D459370EFA2DD3194EA0901B1@exchange1.t-ram.com>
Hello
I am having step coverage issues for my metal deposition (Al-Si) over contact openings 0.4um width and height.(vertical side-walls). Resulting in open contacts.
Does anyone know of an outside source that can do some CVD type of metal deposition on 4inch wafers(Ex. Ti, TiW, or W)?
Any suggestions on how I could resolve this problem, either with SNF equipment or outside vendor?
I will verymuch appreciate your help/suggestions. Thanks in advance.
Rajesh
From afflannery at attbi.com Fri Apr 18 10:57:40 2003
From: afflannery at attbi.com (Anthony Flannery)
Date: Fri, 18 Apr 2003 10:57:40 -0700
Subject: Metal dep help
References: <40F9C31A3EE27D459370EFA2DD3194EA0901B1@exchange1.t-ram.com>
Message-ID: <001101c305d4$011e6280$4201a8c0@transparentnetworks.com>
Rajesh,
I had good step coverage results with Al using a heavy DC bias sputter
deposition at Lance Goddard. If you mention me he will remember what he did.
They have to reconfigure a machine to do the dep so the turnaround can take
a week to 10 days based on their current work flow. In order to prevent
surface damage, I had him hold the DC bias until the first 50 nm had been
deposited.
http://www.lgafilms.com/
Good luck
Tony Flannery
----- Original Message -----
From: "Rajesh Gupta"
To:
Sent: Friday, April 18, 2003 10:12 AM
Subject: Metal dep help
Hello
I am having step coverage issues for my metal deposition (Al-Si) over
contact openings 0.4um width and height.(vertical side-walls). Resulting in
open contacts.
Does anyone know of an outside source that can do some CVD type of metal
deposition on 4inch wafers(Ex. Ti, TiW, or W)?
Any suggestions on how I could resolve this problem, either with SNF
equipment or outside vendor?
I will verymuch appreciate your help/suggestions. Thanks in advance.
Rajesh
From sanli at piezo.Stanford.EDU Fri Apr 18 12:19:36 2003
From: sanli at piezo.Stanford.EDU (Sanli Ergun)
Date: Fri, 18 Apr 2003 12:19:36 -0700 (PDT)
Subject: cell phones
Message-ID:
This discussion had been made before, but I was not interested at the
time. Those who have experience, can you please let me know which cell
phones and networks work best inside the clean room. Please reply to me
rather than replying to the whole list.
Thanks,
Sanli
From LCascao at genencor.com Fri Apr 18 12:26:28 2003
From: LCascao at genencor.com (Luis Cascao-Pereira)
Date: Fri, 18 Apr 2003 12:26:28 -0700
Subject: HELP: cleaning gold surfaces prior to lipid monolayer addition
Message-ID:
Fellow Labmembers,
I am trying to deposit a tethered lipid monolayer on a gold sputtered
surface. The longer I wait after removing the samples from
the sputterer, the worse monolayer addition I get. I suspect an oxide
forms on top of the gold layer and therefore the sulphur-gold bond
chemistry is not as good.
Does anybody know of a way to clean/regenerate the state of the gold
surface by either a wet or dry method? I suspect using a highly reductive
solution or some sort of etching might help.
Many thanks,
Luis Cascao
-------------------------------------------------------
Luis G. Casc?o Pereira, Ph.D.
Group Leader
Materials Science and Technology
Genencor International
925 Page Mill Road
Palo Alto, CA 94304-1013
Tel: 650-846-7685
Fax: 650-621-8186
Mailto:Lcascao at genencor.com
-------------------------------------------------------
--------------------------------------------------------------------------
This message (including any attachments) may contain information
which is confidential or privileged. Use, dissemination, distribution,
or reproduction of this message by unintended recipients is not
authorized and may be unlawful. If you are not the intended
recipient, please advise the sender immediately by reply e-mail and
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From ethrush at stanford.edu Fri Apr 18 16:23:24 2003
From: ethrush at stanford.edu (Evan Thrush)
Date: Fri, 18 Apr 2003 16:23:24 -0700
Subject: Quartz Bonding
Message-ID: <5.2.0.9.2.20030418161752.025913b0@snow.stanford.edu>
Hello Everyone,
I am interested in bonding Quartz to Quartz or Quartz to Glass. Please let
me know if you done this process here at Stanford because we are thinking
about developing this process and we are trying to figure the easiest ways
to do this given our laboratory capabilities. I look forward to hearing
from you!
Thanks,
Evan
------------------------------------------------------------------------------------------------------
Evan Thrush
Stanford University; E.E. PhD Candidate
CIS-X Rm. B113-21, Stanford, CA 94305-4075
Phone: (650)725-2774 E-mail: ethrush at stanford.edu
Fax: (650)723-4659 Homepage: http://snow.stanford.edu/~ethrush
From jreid at silecs.com Fri Apr 18 16:41:25 2003
From: jreid at silecs.com (Jason Reid)
Date: Fri, 18 Apr 2003 16:41:25 -0700
Subject: Metal dep help
In-Reply-To: <001101c305d4$011e6280$4201a8c0@transparentnetworks.com>
Message-ID:
Rajesh,
Other options:
1) Going with a low pressure deposition with high power may at least
get you a decent contact for your geometry (1.8-2.0 mTorr). Keep
the power high.
2) Al reflow during dep above 400C. Ti wetting layer helps.
3) Bias sputtering at Seaway Semiconductor in Livermore (www.seawaysemi.com)
or UHV Sputtering in San Jose.
4) If you want to go the CVD route, Seaway can again help. Go with
a sputtered TiN or Ti/TiN liner followed by CVD W deposition.
Good luck,
Jason
> From: "Anthony Flannery"
> Reply-To: "Anthony Flannery"
> Date: Fri, 18 Apr 2003 10:57:40 -0700
> To: "Rajesh Gupta" ,
> Subject: Re: Metal dep help
>
> Rajesh,
>
> I had good step coverage results with Al using a heavy DC bias sputter
> deposition at Lance Goddard. If you mention me he will remember what he did.
> They have to reconfigure a machine to do the dep so the turnaround can take
> a week to 10 days based on their current work flow. In order to prevent
> surface damage, I had him hold the DC bias until the first 50 nm had been
> deposited.
> http://www.lgafilms.com/
>
>
> Good luck
> Tony Flannery
>
>
> ----- Original Message -----
> From: "Rajesh Gupta"
> To:
> Sent: Friday, April 18, 2003 10:12 AM
> Subject: Metal dep help
>
>
> Hello
>
> I am having step coverage issues for my metal deposition (Al-Si) over
> contact openings 0.4um width and height.(vertical side-walls). Resulting in
> open contacts.
>
> Does anyone know of an outside source that can do some CVD type of metal
> deposition on 4inch wafers(Ex. Ti, TiW, or W)?
>
> Any suggestions on how I could resolve this problem, either with SNF
> equipment or outside vendor?
>
> I will verymuch appreciate your help/suggestions. Thanks in advance.
>
> Rajesh
>
From margo20 at fromru.com Mon Apr 21 09:14:05 2003
From: margo20 at fromru.com (Margo)
Date: Mon, 21 Apr 2003 20:14:05 +0400
Subject: I VERY MUCH WANT TO IMMIGRATE FROM RUSSIA!!!
Message-ID: <200304211613.h3LFpqtf029959@msk.internet2.ru>
I VERY MUCH WANT TO IMMIGRATE FROM RUSSIA!!!
HELLO! MY NAME IS MARGO AND I VERY MUCH WANT TO IMMIGRATE FROM RUSSIA IN ANY OF THE COUNTRIES OF EUROPE OR IN THE USA, PLEASE, I BEG YOU HELP ME IN IT! I THINK TO YOU IT IS POSSIBLE WILL BE REDUCED TO ME ON 1 DOLLAR! SIMPLY I VERY MUCH WANT TO LEAVE FROM RUSSIA AND FOR ME ARE NECESSARY MONEY! I WORK, BUT THAT MONEY WHICH TO ME PAY CATASTROPHICALLY DOES NOT SUFFICE! PLEASE HELP! 50000 DOLLARS TO LEAVE FROM THE COUNTRY ARE NECESSARY FOR ME AT LEAST AND TO LOCATE IN THE NEW COUNTRY! IF 50 THOUSAND PERSON WILL BE REDUCED ON 1 DOLLAR IT BECOMES THE REALITY AND IF YOU VERY GENEROUS PERSON YOU WILL NOT REGRET 2 OR 5 DOLLARS!
IF AT YOU IS WM THE PURSE I THINK YOU CAN SEND ME EVEN 1 DOLLAR
NUMBER OF MY WEBMONEY-PURSE: Z462586896018
P.S. PLEASE HELP ME, I ASK YOU, IT IS LAST OPPORTUNITY
BEFOREHAND THANKS.
IF THIS LETTER HAS TAKEN AWAY FROM YOU TIME THAT I ASK ME TO EXCUSE
From sanli at piezo.Stanford.EDU Mon Apr 21 15:33:39 2003
From: sanli at piezo.Stanford.EDU (Sanli Ergun)
Date: Mon, 21 Apr 2003 15:33:39 -0700 (PDT)
Subject: cell phones
Message-ID:
Thanks for the replies. Out of 10 people, 7 is happy with AT&T, 2 is happy
with Cingular and 1 is happy with T-mobil.
Sanli
From cshen at briontech.com Mon Apr 21 17:58:23 2003
From: cshen at briontech.com (Chongfei Shen)
Date: Mon, 21 Apr 2003 17:58:23 -0700
Subject: CMP
In-Reply-To: <001101c305d4$011e6280$4201a8c0@transparentnetworks.com>
Message-ID:
Dear labmembers,
I want to CMP the front side of a chip.
Does anyone know if there's any company that can do this?
Thanks a lot for any information.
Chongfei
From grupp at snowmass.Stanford.EDU Mon Apr 21 21:48:11 2003
From: grupp at snowmass.Stanford.EDU (Dan Grupp)
Date: Mon, 21 Apr 2003 21:48:11 -0700 (PDT)
Subject: cell phones
In-Reply-To:
Message-ID:
Be carefuL: it's not just the company, but the technology within that
company. That is, Cingular runs GSM and CDMA networks, and one may be
better than the other! Bottom line: if you get a recommendation, make sure
you get the same phone.
-dan
ps - i've been very happy wiht GSM from Cingular with an ericsson T28
World. Europe is GSM, too, so your phone works when you get off the plane.
COol.
On Mon, 21 Apr 2003, Sanli Ergun wrote:
>
> Thanks for the replies. Out of 10 people, 7 is happy with AT&T, 2 is happy
> with Cingular and 1 is happy with T-mobil.
>
> Sanli
>
>
---------------------------------------------------------------------------
Dr. Daniel Grupp, Visiting Scholar
Center for Integrated Systems
Stanford University
Stanford, CA 94305
(650) 724-6911
FAX: 723-4659
---------------------------------------------------------------------------
From jules83 at stanford.edu Tue Apr 22 10:42:46 2003
From: jules83 at stanford.edu (jules83 at stanford.edu)
Date: Tue, 22 Apr 2003 10:42:46 -0700
Subject: Planarization of the films...
Message-ID: <1051033366.3ea57f166bbcc@webmail.stanford.edu>
All of you experts out there...
I have an electroplated annealed Gold film, and I was wondering if
there is a way to planarize the surface. It's rather rough (about
100nm for a 3um film), and it's critical that we get it as flat as
possible.
Is there anything out that like electropolishing or something that
could do that?
Thank you!
--Julia
From dirk.lange at stanford.edu Tue Apr 22 13:25:27 2003
From: dirk.lange at stanford.edu (Dirk Lange)
Date: Tue, 22 Apr 2003 13:25:27 -0700
Subject: Lithography using Transparencies?
Message-ID: <000a01c3090d$50339b10$bc6240ab@DIRK>
Hi all,
Is there anyone out there having experience with lithography at SNF
using high resolution
transparencies?
thanks,
Dirk Lange 725-6139
From acremann at SLAC.Stanford.EDU Tue Apr 22 13:24:46 2003
From: acremann at SLAC.Stanford.EDU (Yves Acremann)
Date: Tue, 22 Apr 2003 13:24:46 -0700
Subject: 100nm Polymer film
Message-ID: <3EA5A50E.3070205@ssrl.slac.stanford.edu>
Hi
I am looking for a polymer film (i.e. Polyimid) which can be spun on
with a thickness of
approx. 100nm. Does anyone have experience with something like that? Is
there a material
which is approved for the Headway spinner?
Thanks
Yves
From tkramer at stanford.edu Tue Apr 22 15:14:21 2003
From: tkramer at stanford.edu (Theresa Kramer)
Date: Tue, 22 Apr 2003 15:14:21 -0700 (PDT)
Subject: Theresa Kramer - Ph.D. Dissertation Defense, Thursday 3PM
Message-ID:
Department of Applied Physics - University Ph.D. Dissertation Defense
Low Frequency Noise in Sub-100nm Silicon Structures
Theresa A. Kramer
Advisor: Prof. R. F. W. Pease
3:00 PM
Thursday, April 24, 2003
Center for Integrated Systems Extension Auditorium (CIS-101X)
Refreshments at 2:45 PM
Abstract
Low frequency noise in bulk MOSFETs is worse than in bipolar and JFET
devices due to the effect of traps near the silicon/silicon dioxide
interface. As device dimensions scale into the nanometer regime,
deviations from constant-field scaling cause an increase in the
average trap-induced noise. Novel device configurations may allow us
to reduce this noise and can be used to explore its lower limits.
Physical separation of electrons and traps should reduce low
frequency noise in MOSFETs by reducing electron/trap interactions. We
have built depletion-mode surrounding-gate transistors that operate
with the surface in accumulation or depletion and have simulated 1/f
noise as a function of gate voltage. Simulations that include
fluctuations in electron number and mobility and only consider
electrons within one mean free path of the interface correctly
predict the experimentally observed noise. Simulations that include
all electrons or do not include both types of fluctuations do not.
Experimentally we observed not only 1/f noise, but also excess
Lorentzian noise near threshold; we attributed this to single
electron trapping. This is consistent with our observation of random
telegraph signals in the time domain.
Nanometer-scale MOSFETs should exhibit very low trap populations,
even zero in some cases, which should significantly affect the noise.
We have built cylindrical surrounding-gate transistors with 0.018
square micron channel area, which is smaller than the size in which,
on average, one trap would be active at typical trap densities. We
observed a reduction in noise by two orders of magnitude when a trap
is rendered inactive by biasing. In six of seven devices, the
measured power spectral density of the drain current is more than an
order of magnitude lower than that predicted using typical trap
densities but still has regions of Lorentzian and 1/f shape. The
near-1/f shape and presence of random telegraph signals in the drain
current indicate at least five active traps. This larger than
expected number of active traps but lower than expected power
spectral density means the devices must be populated by many traps
which have much smaller effect on drain current than predicted.
From rcrane at snf.stanford.edu Thu Apr 24 10:36:15 2003
From: rcrane at snf.stanford.edu (Dick Crane)
Date: Thu, 24 Apr 2003 10:36:15 -0700
Subject: Possible fire alarm test and gas interruption tomorrow
Message-ID: <3EA8208F.36E7B23A@snf.stanford.edu>
Building dwellers and fab users,
The CIS/CISX buildings may have fire and/or toxic gas alarms being
tested tomorrow, Friday, April 25, between the hours of 1:00pm to
2:00pm. The test may be required by the county building inspector as
part of the new, 6" furnace installation toxic gas monitoring
inspection. Silent testing may satisfy the inspector, if not, then the
alarms may be activated for a minute or so. Please disregard alarms
during this time window.
Possible process gas interruption:
Fab and CISX lab users: We may experience a very brief interruption of
process gas services during this test. CDA and N2 will be unaffected.
Maintenance will be standing by to reset the gas cabinets. With the
exception of EPI (H2 and HCl gases), the major of tools will not see
this interruption thanks to residual gas pressure in the lines
continuing to supply the necessary gas flow to the tools.
Thanks for your cooperation and sorry for the inconvenience,
Dick Crane
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From mbai at stanford.edu Fri Apr 25 16:59:12 2003
From: mbai at stanford.edu (Min Bai)
Date: Fri, 25 Apr 2003 16:59:12 -0700 (PDT)
Subject: PhD Dissertation Defense, Min Bai, Monday 3:00pm
Message-ID:
DEPARTMENT OF APPLIED PHYSICS
UNIVERSITY PhD DISSERTATION DEFENSE
Speaker: Min Bai
Advisor: Professor R.F.W. Pease
Title: Insulator Charging in Electron Beam Lithography
Date: April 28, 2003
Time: 3:00 P.M.
Place: Center for Integrated Systems Extension (CIS-X) Auditorium
ABSTRACT
Electron beam lithography (EBL) of masks and wafers results in
charging of the insulating resist films; the charging can deflect the
incoming electron beam, leading to pattern placement errors. This
error has been believed to be increasingly significant as the design
rules for integrated circuit manufacturing progress to 100 nm and
below.
Models have been developed to understand the mechanism by which
charging occurs during electron beam lithography and to determine
beam placement errors. First a one-dimensional analytic model was
developed to predict surface potential on electron beam irradiated
resist films. One sensitive parameter involved in this model was the
electron beam induced conductivity (EBIC). Secondly an image charge
method was used to predict the beam deflection caused by a specified
voltage distribution on the sample surface. The results suggested
that under the usual conditions of EBL for mask manufacture the beam
displacement should be negligible. This is contrary to several
previous reports.
Three independent sets of experiments were employed to quantify the
charging effects. First a Kelvin probe electrometer was used to
monitor surface potential in resist films immediately following
exposure with electrons. The results corroborated an earlier
(disputed) observation that the resist could charge either positively
or negatively depending on the film thickness and/or beam energy.
Secondly the pattern displacement induced by charging was directly
measured in an electron beam lithography tool based on a Leica S440
SEM. The observed pattern positioning error in PMMA resists due to
charging was significantly smaller (< 20 nm) than had been previously
reported. Thirdly we designed and built a simple secondary electron
collector to monitor the change in specimen surface potential during
electron beam exposure. These in situ measurements show that
charging doesn't become a significant problem until the resist
thickness is comparable, or larger than the maximum beam penetration
depth.
In a fourth set of experiments we measured EBIC in PMMA and SiO2 thin
films. The SiO2 is almost 100 times more conductive than PMMA under
the same exposure condition. However, the limited EBIC in PMMA is
yet sufficient to limit the charging of this material. This is
consistent with the charging experimental results.
>From the results of our modeling and experiment we conclude that
under typical mask making conditions (e.g. 400 nm of resist on
conducting substrate, exposed with > 10 keV electrons), resist
charging is much less serious in EBL than had been previously
reported. We believe that those earlier beam displacement results
may have been due to other factors. However, in other scanning
electron beam applications such as inspection, the charging problem
could still be significant because the low energy secondary electrons
used as the signal are much more sensitive to spurious fields and the
samples may include insulating films thicker than the primary
electron range.
From kjliu at san.rr.com Wed Apr 30 13:52:44 2003
From: kjliu at san.rr.com (Kelvin Liu)
Date: Wed, 30 Apr 2003 13:52:44 -0700
Subject: SOI vendors
In-Reply-To: <000a01c3090d$50339b10$bc6240ab@DIRK>
Message-ID: <001201c30f5a$736889d0$6601a8c0@ekr>
Hi,
I'm looking to get some SOI wafers. In the past, I've used SOITEC with
good luck but now I'm looking for thicker device layers (~10 um). Which SOI
vendors/manufacturers have you guys had luck with? I'm looking at SEH and
Ultrasil specifically. Any feedback would be appreciated.
- Kelvin
From jazz9152 at SLAC.Stanford.EDU Wed Apr 30 14:13:11 2003
From: jazz9152 at SLAC.Stanford.EDU (Jasmine Hasi)
Date: Wed, 30 Apr 2003 14:13:11 -0700 (PDT)
Subject: SOI vendors
In-Reply-To: <001201c30f5a$736889d0$6601a8c0@ekr>
References: <001201c30f5a$736889d0$6601a8c0@ekr>
Message-ID:
Dear Kelvin,
How are you??..Say Hi to Wayne.
I have to say I really miss you guys loads...Hope to hear from you soon
Jasmine
p.s I am back in the UK now
From sandrew at stanford.edu Wed Apr 30 17:48:49 2003
From: sandrew at stanford.edu (Scott D. Andrews)
Date: Wed, 30 Apr 2003 17:48:49 -0700 (PDT)
Subject: SiN on 5" wafers
Message-ID:
Hello,
Does anyone know where I can purchase 5 inch Si wafers with low-stress SiN
grown on both sides?
Thanks,
Scott Andrews
From afflannery at attbi.com Wed Apr 30 22:30:29 2003
From: afflannery at attbi.com (Anthony Flannery)
Date: Wed, 30 Apr 2003 22:30:29 -0700
Subject: SiN on 5" wafers
References:
Message-ID: <005001c30fa2$c7094d20$6501a8c0@home>
Quicksil. They process 5" and have a nitride process.
----- Original Message -----
From: "Scott D. Andrews"
To:
Sent: Wednesday, April 30, 2003 5:48 PM
Subject: SiN on 5" wafers
> Hello,
>
> Does anyone know where I can purchase 5 inch Si wafers with low-stress SiN
> grown on both sides?
>
> Thanks,
> Scott Andrews
>
>