Résumé:Indianapolis International Airport (IND) lost its Registered Traveler programme when Verified Identity Pass went bankrupt and took Clear with it. Now the programme is up and running again - but not using Clear's service.

Résumé:Piezoelectric materials constitute a class of intelligent materials that are helpful for monitoring the structural integrity. The principle of the piezoelectric impedance-based structural health monitoring technique is to measure the electrical impedance of a piezoelectric patch attached to a structure in a certain frequency range. Electrical impedance variations indicate physical changes in the structure due to the coupling between the electrical impedance and the mechanical impedance. Traditional methods use an impedance analyser that increases the inspection cost. The objective of this work is to introduce an electronic circuit for the piezoelectric impedance-based structural health monitoring. The circuit can monitor the electrical impedance variations of a piezoelectric patch attached to a structure. The frequency range is from 7.47 to 277.29 kHz. This frequency range covers the sensitive range of the piezoelectric structural integrity. The power consumption of the circuit is 18.15 mW. The chip area is 1.03 mm x 2.30 mm. The cost of the final design will be much lower than that of an impedance analyser. Using a wireless communication circuit, a sensor network might be established in the future.

Résumé:We developed an optical input module with a superconducting single-flux-quantum (SFQ) circuit for application of ultrafast photonic networks in the near future. The optical input module, consisting of a built-in photodiode (PD) with a coplanar waveguide transmission line, was fabricated on an InP substrate and flip-chip bonded with the SFQ circuit on a Si substrate. The fabricated PD showed photosensitivities of more than 0.2 A/W for the wavelength range 1480 to 1530 nm at 4.2 K. SFQ pulses were generated by less than 1 mW optical pulse input.

Résumé:AT THE DAWN OF THE LAST century, electric power was widely recognized as having the potential to significantly improve the quality of life and the productivity of the American economy. As power systems began being installed, power companies soon encountered the situation where sources of generation were located long distances from where the power was needed. The need to transmit power over longer distances was the key factor that resulted in alternating current (ac) prevailing over direct current (dc) in the famous Edison versus Westinghouse “Battle of the Currents.”

Résumé:Green's functions play an important role in electroelastic analyses of piezoelectric media. However, most works available on the topic are for the case of uniform temperature. Based on the compact 2-D general solution of orthotropic piezothermoelectric material, which is expressed in harmonic functions, and employing the trial-and-error method, the 2-D Green's function for a steady line heat source in a semi-infinite piezothermoelectric plane is presented by four newly induced harmonic functions. All components of the coupled field are expressed in terms of elementary functions and are convenient to use. Numerical results are given graphically by contours.

Auteurs: Su-Ming Xiong;Peng-Fei Hou;Shi-You Yang;

Apparue dans: IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control

Résumé: This paper presents a 24-bit 5.0 GHz ultrahigh-speed direct digital synthesizer (DDS) with direct digital modulation capabilities used in a pulse compression radar. This design represents the first DDS RFIC in over-GHz output frequency range with direct digital modulation capabilities. It adopts a ROM-less architecture and has the capabilities for direct digital frequency and phase modulation with 24 bit and 12 bit resolution, respectively. The DDS includes a 24-bit ripple carry adder (RCA) accumulator for phase accumulation, a 12-bit RCA for phase modulation and a 10-bit segmented sine-weighted digital-to-analog converter (DAC) for phase-to-amplitude conversion (PAC) as well as digital-to-analog conversion. The DDS core occupies and consumes 4.7 W of power with a single 3.3 V power supply. This 24-bit DDS has more than 20,000 transistors and achieves a maximum clock frequency of 5.0 GHz. The measured worst case SFDR is 45 dBc under a 5.0 GHz clock frequency and within a 50 MHz bandwidth. At 1.246258914 GHz output frequency, the 50 MHz narrowband SFDR is measured as 82 dBc. The best Nyquist band SFDR is 38 dBc with a 469.360351 MHz output using a 5.0 GHz clock frequency. This DDS was developed in a 0.13 SiGe BiCMOS technology with and tested in a CLCC-68 package.

Résumé: This paper presents a 24-bit 5.0 GHz ultrahigh-speed direct digital synthesizer (DDS) with direct digital modulation capabilities used in a pulse compression radar. This design represents the first DDS RFIC in over-GHz output frequency range with direct digital modulation capabilities. It adopts a ROM-less architecture and has the capabilities for direct digital frequency and phase modulation with 24 bit and 12 bit resolution, respectively. The DDS includes a 24-bit ripple carry adder (RCA) accumulator for phase accumulation, a 12-bit RCA for phase modulation and a 10-bit segmented sine-weighted digital-to-analog converter (DAC) for phase-to-amplitude conversion (PAC) as well as digital-to-analog conversion. The DDS core occupies and consumes 4.7 W of power with a single 3.3 V power supply. This 24-bit DDS has more than 20,000 transistors and achieves a maximum clock frequency of 5.0 GHz. The measured worst case SFDR is 45 dBc under a 5.0 GHz clock frequency and within a 50 MHz bandwidth. At 1.246258914 GHz output frequency, the 50 MHz narrowband SFDR is measured as 82 dBc. The best Nyquist band SFDR is 38 dBc with a 469.360351 MHz output using a 5.0 GHz clock frequency. This DDS was developed in a 0.13 SiGe BiCMOS technology with and tested in a CLCC-68 package.

Résumé: This paper presents a 24-bit 5.0 GHz ultrahigh-speed direct digital synthesizer (DDS) with direct digital modulation capabilities used in a pulse compression radar. This design represents the first DDS RFIC in over-GHz output frequency range with direct digital modulation capabilities. It adopts a ROM-less architecture and has the capabilities for direct digital frequency and phase modulation with 24 bit and 12 bit resolution, respectively. The DDS includes a 24-bit ripple carry adder (RCA) accumulator for phase accumulation, a 12-bit RCA for phase modulation and a 10-bit segmented sine-weighted digital-to-analog converter (DAC) for phase-to-amplitude conversion (PAC) as well as digital-to-analog conversion. The DDS core occupies and consumes 4.7 W of power with a single 3.3 V power supply. This 24-bit DDS has more than 20,000 transistors and achieves a maximum clock frequency of 5.0 GHz. The measured worst case SFDR is 45 dBc under a 5.0 GHz clock frequency and within a 50 MHz bandwidth. At 1.246258914 GHz output frequency, the 50 MHz narrowband SFDR is measured as 82 dBc. The best Nyquist band SFDR is 38 dBc with a 469.360351 MHz output using a 5.0 GHz clock frequency. This DDS was developed in a 0.13 SiGe BiCMOS technology with and tested in a CLCC-68 package.

Résumé: This paper presents a 24-bit 5.0 GHz ultrahigh-speed direct digital synthesizer (DDS) with direct digital modulation capabilities used in a pulse compression radar. This design represents the first DDS RFIC in over-GHz output frequency range with direct digital modulation capabilities. It adopts a ROM-less architecture and has the capabilities for direct digital frequency and phase modulation with 24 bit and 12 bit resolution, respectively. The DDS includes a 24-bit ripple carry adder (RCA) accumulator for phase accumulation, a 12-bit RCA for phase modulation and a 10-bit segmented sine-weighted digital-to-analog converter (DAC) for phase-to-amplitude conversion (PAC) as well as digital-to-analog conversion. The DDS core occupies and consumes 4.7 W of power with a single 3.3 V power supply. This 24-bit DDS has more than 20,000 transistors and achieves a maximum clock frequency of 5.0 GHz. The measured worst case SFDR is 45 dBc under a 5.0 GHz clock frequency and within a 50 MHz bandwidth. At 1.246258914 GHz output frequency, the 50 MHz narrowband SFDR is measured as 82 dBc. The best Nyquist band SFDR is 38 dBc with a 469.360351 MHz output using a 5.0 GHz clock frequency. This DDS was developed in a 0.13 SiGe BiCMOS technology with and tested in a CLCC-68 package.

Résumé: This paper presents a 24-bit 5.0 GHz ultrahigh-speed direct digital synthesizer (DDS) with direct digital modulation capabilities used in a pulse compression radar. This design represents the first DDS RFIC in over-GHz output frequency range with direct digital modulation capabilities. It adopts a ROM-less architecture and has the capabilities for direct digital frequency and phase modulation with 24 bit and 12 bit resolution, respectively. The DDS includes a 24-bit ripple carry adder (RCA) accumulator for phase accumulation, a 12-bit RCA for phase modulation and a 10-bit segmented sine-weighted digital-to-analog converter (DAC) for phase-to-amplitude conversion (PAC) as well as digital-to-analog conversion. The DDS core occupies and consumes 4.7 W of power with a single 3.3 V power supply. This 24-bit DDS has more than 20,000 transistors and achieves a maximum clock frequency of 5.0 GHz. The measured worst case SFDR is 45 dBc under a 5.0 GHz clock frequency and within a 50 MHz bandwidth. At 1.246258914 GHz output frequency, the 50 MHz narrowband SFDR is measured as 82 dBc. The best Nyquist band SFDR is 38 dBc with a 469.360351 MHz output using a 5.0 GHz clock frequency. This DDS was developed in a 0.13 SiGe BiCMOS technology with and tested in a CLCC-68 package.

Résumé: This paper presents a 24-bit 5.0 GHz ultrahigh-speed direct digital synthesizer (DDS) with direct digital modulation capabilities used in a pulse compression radar. This design represents the first DDS RFIC in over-GHz output frequency range with direct digital modulation capabilities. It adopts a ROM-less architecture and has the capabilities for direct digital frequency and phase modulation with 24 bit and 12 bit resolution, respectively. The DDS includes a 24-bit ripple carry adder (RCA) accumulator for phase accumulation, a 12-bit RCA for phase modulation and a 10-bit segmented sine-weighted digital-to-analog converter (DAC) for phase-to-amplitude conversion (PAC) as well as digital-to-analog conversion. The DDS core occupies and consumes 4.7 W of power with a single 3.3 V power supply. This 24-bit DDS has more than 20,000 transistors and achieves a maximum clock frequency of 5.0 GHz. The measured worst case SFDR is 45 dBc under a 5.0 GHz clock frequency and within a 50 MHz bandwidth. At 1.246258914 GHz output frequency, the 50 MHz narrowband SFDR is measured as 82 dBc. The best Nyquist band SFDR is 38 dBc with a 469.360351 MHz output using a 5.0 GHz clock frequency. This DDS was developed in a 0.13 SiGe BiCMOS technology with and tested in a CLCC-68 package.

Résumé:This paper presents a 24-bit 5.0 GHz ultrahigh-speed direct digital synthesizer (DDS) with direct digital modulation capabilities used in a pulse compression radar. This design represents the first DDS RFIC in over-GHz output frequency range with direct digital modulation capabilities. It adopts a ROM-less architecture and has the capabilities for direct digital frequency and phase modulation with 24 bit and 12 bit resolution, respectively. The DDS includes a 24-bit ripple carry adder (RCA) accumulator for phase accumulation, a 12-bit RCA for phase modulation and a 10-bit segmented sine-weighted digital-to-analog converter (DAC) for phase-to-amplitude conversion (PAC) as well as digital-to-analog conversion. The DDS core occupies 3.0 Ã¿ 2.5 mm2 and consumes 4.7 W of power with a single 3.3 V power supply. This 24-bit DDS has more than 20,000 transistors and achieves a maximum clock frequency of 5.0 GHz. The measured worst case SFDR is 45 dBc under a 5.0 GHz clock frequency and within a 50 MHz bandwidth. At 1.246258914 GHz output frequency, the 50 MHz narrowband SFDR is measured as 82 dBc. The best Nyquist band SFDR is 38 dBc with a 469.360351 MHz output using a 5.0 GHz clock frequency. This DDS was developed in a 0.13 Â¿m SiGe BiCMOS technology with fT/fMAX = 200/250 GHz and tested in a CLCC-68 package.

Résumé:The transient analysis of piezoelectric transducers is often performed using finite-element or finite-difference time-domain methods, which efficiently calculate the vibration of the structure but whose numerical dispersion prevents the modeling of waves propagating over large distances. A second analytical or numerical simulation is therefore often required to calculate the pressure field in the propagating medium (typically water) to deduce many important characteristics of the transducer, such as spatial resolutions and side lobe levels. This is why a hybrid algorithm was developed, combining finite- difference and pseudo-spectral methods in the case of 2-D configurations to simulate accurately both the generation of acoustic waves by the piezoelectric transducer and their propagation in the surrounding media using a single model. The algorithm was redefined in this study to take all three dimensions into account and to model single-element transducers, which usually present axisymmetrical geometry. This method was validated through comparison of its results with those of finite-element software, and was used to simulate the behavior of planar and lens-focused transducers. A high-frequency (30 MHz) transducer based on a screen-printed piezoelectric thick film was fabricated and characterized. The numerical results of the hybrid algorithm were found to be in good agreement with the experimental measurements of displacements at the surface of the transducer and of pressure radiated in water in front of the transducer.

Résumé: We report a process development route toward 300-mm production-worthy non-Bosch through-silicon-via (TSV) etch with critical dimensions between 1–5 and aspect ratios up to 20:1 for 3-D logic applications. The etch development was performed on an experimental alpha-tool: a magnetically enhanced capacitively coupled plasma etcher with a dipole ring magnet that aims to capture the strengths (anisotropicity, profile uniformity) while eliminating the weaknesses (scalloping, undercut, residues) of a nominal Bosch process. Key factors contributing to the control of sidewall taper and roughness, etched TSV volume and depth, mask undercut, local bowing effects, and within wafer (WIW) center-to-edge depth and profile uniformity were evaluated. TSVs with nominal sizes of , and with less than 1% WIW nonuniformity, negligible silicon scalloping/mask undercut, and good profile anisotropicity were developed. Up to and void-free Cu-filled TSVs were demonstrated with both vertical TSVs and tapered TSVs.

Résumé:This study presents a high-throughput deblocking filter accelerator with 48 cycles-per-macro-block processing capability for H.264. This innovation is achieved by considering both luminance data and chrominance data at the same time in arranging the filtering schedule. Cooperating with the filtering schedule, the proposed quadruple-filter-based architecture can simultaneously compute filtering of four edges. Besides, interleaved memory organisation is adopted to eliminate all the data conflicts. This design keeps the data scanning order compliant with that recommended for data communication between modules in H.264 systems. Hence, no interfacing overhead is required for reordering the input and output data. After being implemented by using a 0.18-mm CMOS technology, this work can achieve the real-time performance requirement of 6 K (6000 x 4000@30 fps) application when operated at 135MHz frequency at a cost of 41.6 K gates along with 640 bytes single-port SRAM. Compared with previous works, the proposed design not only achieves higher real-time performance requirements but also possesses higher hardware computing efficiency.

Résumé:A bilayered chiral metamaterial is proposed to realize a 90° polarization rotator, whose giant optical activity is due to the transverse magnetic dipole coupling among the metallic wire pairs of enantiomeric patterns. By transmission through this thin bilayered structure of less than λ/30 thick, a linearly polarized wave is converted to its cross polarization with a resonant polarization conversion efficiency of over 90%. It is demonstrated that the chirality in the propagation direction makes this efficient cross-polarization conversion possible.

Résumé:This paper deals with the metrological management of an acquisition system that has been developed for monitoring an experimental photovoltaic (PV) plant. The acquisition system has been conceived for comparing the performance of different PV technologies and for verifying the nominal specifications of the PV modules. For these reasons, the traceability of the monitoring system has to be ensured, and therefore, it must be periodically calibrated. A remotely exercised procedure is proposed for the calibration of the acquisition system, which is based on a calibrator specifically designed for this application. This calibrator has the capability to act as a reference for heterogeneous quantities, including electrical quantities, temperature, and solar irradiance. The architecture of this calibrator is described, and experimental results for the preliminary characterization of the prototype are described.

Résumé:Red (Ho3+:5F5→5I8), green (Ho3+:5S2,5F4→5I8), and blue (Tm3+:1D2→3F4 and 1G4→3H6) upconversion emissions were simultaneously generated in the transparent glass ceramics containing Nd3+/Yb3+/Tm3+/Ho3+:β-YF3 nanocrystals under 796 nm excitation. It was experimentally evidenced that Yb3+ ions acted as the bridging centers to prompt energy transfer from Nd3+ to Tm3+ and Ho3+. With appropriately optimizing the contents and relative ratios of the doped rare earth species, luminescence of various colors, including bright white light, was easily tuned in the glass ceramics. The related upconversion mechanisms were proposed.

Résumé:33S nuclear magnetic resonance (NMR) spectroscopy is limited by inherently low NMR sensitivity because of the quadrupolar moment and low gyromagnetic ratio of the 33S nucleus. We have developed a 10 mm 33S cryogenic NMR probe, which is operated at 9–26 K with a cold preamplifier and a cold rf switch operated at 60 K. The 33S NMR sensitivity of the cryogenic probe is as large as 9.8 times that of a conventional 5 mm broadband NMR probe. The 33S cryogenic probe was applied to biological samples such as human urine, bile, chondroitin sulfate, and scallop tissue. We demonstrated that the system can detect and determine sulfur compounds having SO42- anions and –SO3- groups using the 33S cryogenic probe, as the 33S nuclei in these groups are in highly symmetric environments. The NMR signals for other common sulfur compounds such as cysteine are still undetectable by the 33S cryogenic probe, as the 33S nuclei in these compounds are in asymmetric environments. If we shorten the rf pulse width or decrease the rf coil diameter, we should be able to detect the NMR signals for these compounds.

Résumé:The c-axis transport properties of a high-pressure synthesized PrFeAsO0.7 single crystal are studied using s-shaped junctions. Resistivity anisotropy of about 120 detected at 50 K shows the presence of strong anisotropy in the electronic states. The obtained critical current density for the c-axis of 2.9×105A/cm2 is two orders of magnitude larger than that in Bi2Sr1.6La0.4CuO6+δ. The appearance of a hysteresis in the current-voltage curve below Tc is the manifestation of the intrinsic Josephson effect similar to that in cuprate superconductors. The suppression of the critical current-normal resistance (IcRn) product is explained by an inspecular transport in s±-wave pair potential.

Résumé: We report on the band alignment of and the dc characteristics of heterojunction bipolar transistors (HBTs). By comparing the forward and reverse Gummel plot, we found a potential spike existing at the InGaPSb/GaAs interface. Through a flatband extrapolation from the currents of the forward and reverse Gummel plot and the energy gap determined from photoluminescence, we concluded that is in a type-I band alignment. The conduction-band offset and valence-band offset are 0.12 and 0.35 eV, respectively. As a result of the type-I band alignment, the InGaPSb/GaAs HBTs showed a more significant thermal degradation of the current gain than the control InGaP/GaAs HBT. The thermal behavior is beneficial to ruggedness.

Résumé: We report on the band alignment of and the dc characteristics of heterojunction bipolar transistors (HBTs). By comparing the forward and reverse Gummel plot, we found a potential spike existing at the InGaPSb/GaAs interface. Through a flatband extrapolation from the currents of the forward and reverse Gummel plot and the energy gap determined from photoluminescence, we concluded that is in a type-I band alignment. The conduction-band offset and valence-band offset are 0.12 and 0.35 eV, respectively. As a result of the type-I band alignment, the InGaPSb/GaAs HBTs showed a more significant thermal degradation of the current gain than the control InGaP/GaAs HBT. The thermal behavior is beneficial to ruggedness.

Résumé: We report on the band alignment of and the dc characteristics of heterojunction bipolar transistors (HBTs). By comparing the forward and reverse Gummel plot, we found a potential spike existing at the InGaPSb/GaAs interface. Through a flatband extrapolation from the currents of the forward and reverse Gummel plot and the energy gap determined from photoluminescence, we concluded that is in a type-I band alignment. The conduction-band offset and valence-band offset are 0.12 and 0.35 eV, respectively. As a result of the type-I band alignment, the InGaPSb/GaAs HBTs showed a more significant thermal degradation of the current gain than the control InGaP/GaAs HBT. The thermal behavior is beneficial to ruggedness.

Résumé: We report on the band alignment of and the dc characteristics of heterojunction bipolar transistors (HBTs). By comparing the forward and reverse Gummel plot, we found a potential spike existing at the InGaPSb/GaAs interface. Through a flatband extrapolation from the currents of the forward and reverse Gummel plot and the energy gap determined from photoluminescence, we concluded that is in a type-I band alignment. The conduction-band offset and valence-band offset are 0.12 and 0.35 eV, respectively. As a result of the type-I band alignment, the InGaPSb/GaAs HBTs showed a more significant thermal degradation of the current gain than the control InGaP/GaAs HBT. The thermal behavior is beneficial to ruggedness.

Résumé: We report on the band alignment of and the dc characteristics of heterojunction bipolar transistors (HBTs). By comparing the forward and reverse Gummel plot, we found a potential spike existing at the InGaPSb/GaAs interface. Through a flatband extrapolation from the currents of the forward and reverse Gummel plot and the energy gap determined from photoluminescence, we concluded that is in a type-I band alignment. The conduction-band offset and valence-band offset are 0.12 and 0.35 eV, respectively. As a result of the type-I band alignment, the InGaPSb/GaAs HBTs showed a more significant thermal degradation of the current gain than the control InGaP/GaAs HBT. The thermal behavior is beneficial to ruggedness.

Résumé: We report on the band alignment of and the dc characteristics of heterojunction bipolar transistors (HBTs). By comparing the forward and reverse Gummel plot, we found a potential spike existing at the InGaPSb/GaAs interface. Through a flatband extrapolation from the currents of the forward and reverse Gummel plot and the energy gap determined from photoluminescence, we concluded that is in a type-I band alignment. The conduction-band offset and valence-band offset are 0.12 and 0.35 eV, respectively. As a result of the type-I band alignment, the InGaPSb/GaAs HBTs showed a more significant thermal degradation of the current gain than the control InGaP/GaAs HBT. The thermal behavior is beneficial to ruggedness.

Résumé: An RF front-end transceiver is implemented in standard 0.18- m CMOS for V2.1 Bluetooth applications. All signal detection and gain calibrations are realized without the need of baseband control, but using an incoming Gaussian frequency-shift keying signal detection mechanism, auto low-noise amplifier gain mode selection, and autogain calibration with a combined programmable gain amplifier/received-signal-strength indicator function. Moreover, a simple control interface between transceiver and baseband is designed. The differential error vector magnitude performance of the transmitter is less than 6%, and a less than 7.5-dB system noise figure is achieved in the receiver. Continuous current consumptions in receiver and transmitter are 32 and 42 mA, respectively, with a 1.8-V internal regulator voltage.

Résumé: An RF front-end transceiver is implemented in standard 0.18- m CMOS for V2.1 Bluetooth applications. All signal detection and gain calibrations are realized without the need of baseband control, but using an incoming Gaussian frequency-shift keying signal detection mechanism, auto low-noise amplifier gain mode selection, and autogain calibration with a combined programmable gain amplifier/received-signal-strength indicator function. Moreover, a simple control interface between transceiver and baseband is designed. The differential error vector magnitude performance of the transmitter is less than 6%, and a less than 7.5-dB system noise figure is achieved in the receiver. Continuous current consumptions in receiver and transmitter are 32 and 42 mA, respectively, with a 1.8-V internal regulator voltage.

Résumé: An RF front-end transceiver is implemented in standard 0.18- m CMOS for V2.1 Bluetooth applications. All signal detection and gain calibrations are realized without the need of baseband control, but using an incoming Gaussian frequency-shift keying signal detection mechanism, auto low-noise amplifier gain mode selection, and autogain calibration with a combined programmable gain amplifier/received-signal-strength indicator function. Moreover, a simple control interface between transceiver and baseband is designed. The differential error vector magnitude performance of the transmitter is less than 6%, and a less than 7.5-dB system noise figure is achieved in the receiver. Continuous current consumptions in receiver and transmitter are 32 and 42 mA, respectively, with a 1.8-V internal regulator voltage.

Résumé: An RF front-end transceiver is implemented in standard 0.18- m CMOS for V2.1 Bluetooth applications. All signal detection and gain calibrations are realized without the need of baseband control, but using an incoming Gaussian frequency-shift keying signal detection mechanism, auto low-noise amplifier gain mode selection, and autogain calibration with a combined programmable gain amplifier/received-signal-strength indicator function. Moreover, a simple control interface between transceiver and baseband is designed. The differential error vector magnitude performance of the transmitter is less than 6%, and a less than 7.5-dB system noise figure is achieved in the receiver. Continuous current consumptions in receiver and transmitter are 32 and 42 mA, respectively, with a 1.8-V internal regulator voltage.

Résumé: A 0.5–11 GHz CMOS low noise amplifier (LNA) is proposed, with a new dual-channel shunt technique implemented, where one channel uses inductive-series peaking to provide flat gain over 0.5 to 11 GHz, and another channel adopts resistive feedback to realize wideband input impedance matching. The LNA was fabricated using the TSMC 0.18 CMOS process, achieving a maximum power gain of 10.2 dB. Its input return loss is better than 9 dB over a 3 dB bandwidth of 0.5–11 GHz at a power consumption of 14.4 mW. The measured noise figure is from 3.9 to 4.5 dB, and the IIP3 is 9.1 dBm at 6 GHz. The overall chip size is about 0.54 .

Résumé: Spread spectrum clocking is an effective solution to reduce the electromagnetic interference produced by digital chips, using a clock signal with a frequency that is intentionally swept (frequency modulated) within a certain frequency range, with a predefined modulation profile.

Résumé: A sixth-order low-pass - filter for fiber-optic electrical dispersion compensation receivers cascades three biquads permitting a reduction of group delay variation down to 10 ps. A cutoff frequency is tuned from 1.6 to 3.2 GHz by using two methods, namely, changing and switching a CMOS varactor's polarity. Output third-order intercept point reaches 13.1 dBm and total harmonic distortion is below 40 dB at 0.9 output. The continuous time filter is implemented in a 0.18- m SiGe process, it occupies 0.17 mm on a 3.2 3.7 mm test chip and consumes 0.3 W from a 3.3-V supply.

Résumé: This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately . At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 and achieves an energy efficiency of 4.4 fJ/conversion-step.

Résumé: This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately . At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 and achieves an energy efficiency of 4.4 fJ/conversion-step.

Résumé: This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately . At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 and achieves an energy efficiency of 4.4 fJ/conversion-step.

Résumé: This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately . At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 and achieves an energy efficiency of 4.4 fJ/conversion-step.

Résumé: This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately . At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 and achieves an energy efficiency of 4.4 fJ/conversion-step.

Résumé: This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately . At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 and achieves an energy efficiency of 4.4 fJ/conversion-step.

Résumé:This paper presents a 10 bit successive approximation ADC in 65 nm CMOS that benefits from technology scaling. It meets extremely low power requirements by using a charge-redistribution DAC that uses step-wise charging, a dynamic two-stage comparator and a delay-line-based controller. The ADC requires no external reference current and uses only one external supply voltage of 1.0 V to 1.3 V. Its supply current is proportional to the sample rate (only dynamic power consumption). The ADC uses a chip area of approximately 115Ã¿225 Â¿m2. At a sample rate of 1 MS/s and a supply voltage of 1.0 V, the 10 bit ADC consumes 1.9 Â¿W and achieves an energy efficiency of 4.4 fJ/conversion-step.

Résumé: This paper describes the first phase of a Mechatronics Curriculum Development effort—the design of an “Introduction to Mechatronics” course, the infusion of mechatronics activities throughout the curriculum and in outreach activities, and assessment results. In addition, the relevance and impact of such a curriculum on the education of engineers in relation to the evolving global economy is discussed. The second and third phases of this effort included development of two advanced mechatronics courses and the formulation of a mechatronics curriculum, which will be addressed in a companion paper, “A 10-Year Mechatronics Curriculum Development Initiative: Relevance, Content, and Results—Part II” (IEEE Transactions on Education, vol. 53, no. 2, May 2010).

Résumé: This paper describes the second and third phases of a comprehensive mechatronics curriculum development effort. They encompass the development of two advanced mechatronics courses (“Simulation and Modeling of Mechatronic Systems” and “Sensors and Actuators for Mechatronic Systems”), the formulation of a Mechatronics concentration, and offshoot research activities in the mechatronics area. The first phase involved the design of an “Introduction to Mechatronics” course and the infusion of mechatronic activities throughout the curriculum and in outreach activities and has been described in a companion paper “A 10-Year Mechatronics Curriculum Development Initiative: Relevance, Content, and Results—Part I” (IEEE Transactions on Education, vol. 53, no. 2, May 2010).

Résumé: A Q-band, Class-E power amplifier has been designed and fabricated in a 0.12 SiGe BiCMOS technology. The amplifier was designed for high output power using on-chip power combining networks. It operates respectively from a 1.2 V supply for peak efficiency and a 2.4 V supply for maximum power and occupies an area of 0.801 . A peak PAE of 18% is measured for an output power of 11.3 dBm at 45 GHz and a maximum of 19.4 dBm is measured at 42 GHz with a PAE of 14.4%. The power amplifier operates from 42 to 50 GHz.

Résumé: A Q-band, Class-E power amplifier has been designed and fabricated in a 0.12 SiGe BiCMOS technology. The amplifier was designed for high output power using on-chip power combining networks. It operates respectively from a 1.2 V supply for peak efficiency and a 2.4 V supply for maximum power and occupies an area of 0.801 . A peak PAE of 18% is measured for an output power of 11.3 dBm at 45 GHz and a maximum of 19.4 dBm is measured at 42 GHz with a PAE of 14.4%. The power amplifier operates from 42 to 50 GHz.

Résumé: A Q-band, Class-E power amplifier has been designed and fabricated in a 0.12 SiGe BiCMOS technology. The amplifier was designed for high output power using on-chip power combining networks. It operates respectively from a 1.2 V supply for peak efficiency and a 2.4 V supply for maximum power and occupies an area of 0.801 . A peak PAE of 18% is measured for an output power of 11.3 dBm at 45 GHz and a maximum of 19.4 dBm is measured at 42 GHz with a PAE of 14.4%. The power amplifier operates from 42 to 50 GHz.

Résumé: A Q-band, Class-E power amplifier has been designed and fabricated in a 0.12 SiGe BiCMOS technology. The amplifier was designed for high output power using on-chip power combining networks. It operates respectively from a 1.2 V supply for peak efficiency and a 2.4 V supply for maximum power and occupies an area of 0.801 . A peak PAE of 18% is measured for an output power of 11.3 dBm at 45 GHz and a maximum of 19.4 dBm is measured at 42 GHz with a PAE of 14.4%. The power amplifier operates from 42 to 50 GHz.

Résumé: Two- and three- stage high voltage/high power (HiVP) amplifiers have been designed, implemented, and measured using a 0.12 SiGe HBT process. The HiVP is a circuit configuration that allows for very large output voltage swings, leading to high output power when used in a power amplifier. This letter describes the first implementation of a HiVP circuit using Silicon Germanium (SiGe) Heterojunction Bipolar Transistors (HBTs). The intent of this letter is 1) to illustrate practical design steps for implementing a HiVP circuit in silicon-based technologies and 2) to report measurements of this HiVP implementation in 0.12 SiGe. At 2.4 GHz, and are achieved for the two- and three-stage SiGe-HBT HiVP amplifiers, respectively.

Résumé: A 20-Gb/s current-mode optical receiver is realized in a 0.13- CMOS process, which consists of a common-gate transimpedance amplifier (TIA) with on-chip transformers, a six-stage postamplifier (PA) with an offset cancellation network, and an output buffer. The transformer-based inductive peaking technique is exploited in the TIA to isolate the parasitic capacitances at high-impedance nodes and, hence, to enlarge the bandwidth. The PA incorporates source degeneration and interleaving active feedback techniques to achieve wide bandwidth and flat frequency response so as not to degrade the operation speed of the whole optical receiver. Measured results demonstrate 60- transimpedance gain, 12.6-GHz bandwidth even with 0.4-pF large input parasitic capacitance, 13-dBm sensitivity for a bit error rate, and 38.3-mW power consumption from a single 1.2-V supply.

Résumé: A 20-Gb/s transmitter with two-tap adaptive preemphasis is presented. For the channels with different lengths, the tap coefficients are adjusted by detecting the propagation time through a channel. This adaptive transmitter is fabricated in 65-nm CMOS technology. The maximum power consumption from a 1.2-V supply is 58.8 mW, and the chip area occupies . For a 2-m coaxial copper cable with a 12.78-dB loss, the measured root mean square and peak-to-peak jitter of the recovered data are 2.56 and 18.67 ps, respectively, for a 20-Gb/s pseudorandom binary sequence of . The measured bit error rate is less than .

Résumé: A multiband flexible RF-sampling receiver aimed at software-defined radio is presented. The wideband RF sampling function is enabled by a recently proposed discrete-time mixing downconverter. This work exploits a voltage-sensing LNA preceded by a tunable LC pre-filter with one external coil to demonstrate an RF-sampling receiver with low noise figure (NF) and high harmonic rejection (HR). The second-order LC filter provides voltage pre-gain and attenuates the source noise aliasing, and it also improves the HR ratio of the sampling downconverter. The LNA consists of a simple amplifier topology built from inverters and resistors to improve the third-order nonlinearity via an enhanced voltage mirror technique. The RF-sampling receiver employs 8 times oversampling covering 300 to 800 MHz in two RF sub-bands. The chip is realized in 65 nm CMOS and the measured gain across the band is between 22 and 28 dB, while achieving a NF between 0.8 to 4.3 dB. The IIP2 varies between 38 and 49 dBm and the IIP3 between 14 dBm and 9 dBm, and the third and fifth order HR ratios are more than 60 dB. The LNA and downconverter consumes 6 mW, and the clock generator takes 12 mW at 800 MHz RF.

Résumé: This brief presents a differentially terminated CML transmitter with a self-calibration scheme based on time-domain reflectometry for preemphasis strength control. Without any handshaking or receiver mode control, the transmitter measures the time of flight by applying the same step input on the two transmission lines of the differential link. Since the receiver does not change its configuration, the proposed scheme greatly simplifies the preemphasis adaptation. To verify the calibration scheme, the proposed transmitter is fabricated in a 0.18- CMOS. For various lengths of the microstrip line on the printed circuit board up to 80 cm, the tested transmitter greatly improves signal integrity and shows clear eye diagrams at 5 Gb/s.

Résumé: This brief presents a 5-Gb/s adaptive equalizer that compensates for the PCI Express channel loss of 14 dB at 2.5 GHz. This equalizing filter uses low-voltage zero generators (LVZGs) to generate high-frequency gain boosting without inductors. The spectrum-balancing technique eliminates the need for a slicer. The power detector combines current steering techniques and a preamplifier circuit to enhance the voltage swing. This design consumes 17.6 mW (excluding the output buffers) at a 1.6-V supply voltage with an output swing of 560 mV (p-p). The area occupied is 0.1 (including output buffers), and the output peak-to-peak jitter is 0.28 UI. The equalizer achieves high-frequency compensation, small area, and low power consumption.

Résumé: A voltage-controlled oscillator (VCO) with a central frequency of 56 GHz and a 17% tuning range is presented. The oscillation frequency is tuned both by an analog input and by a 3-bit digital control bus using the same type of differential varactors. It achieves a record figure of merit, considering tuning range of 186.8 dBc/Hz and is able to address the full wireless high-definition multimedia interface band . The VCO is implemented in a 65-nm bulk CMOS process and dissipates 15 mW from a 1.2-V supply. Both fixed and parameterized electromagnetic models for inductors, interconnection structures, and transmission lines have been embedded in the classical design flow including layout verification and extraction, resulting in a very high level of simulation accuracy.

Résumé: A normally-on 9-kV (at 0.1- drain leakage) active-area vertical-channel SiC JFET (VJFET) is fabricated with no e-beam lithography, no epitaxial regrowth, and a three-step junction-termination-extension edge termination, which is connected to the gate bus through an ion-implanted sloped extension. The VJFET exhibits low leakage currents and a sharp onset of gate-voltage breakdown occurring at 80 V. To lower resistance, the VJFET is designed to be very normally-on, which minimizes the channel resistance contribution. At a gate bias of 0 V, the VJFET's drain current is 73 mA with a forward drain voltage drop of 5 V (240 ), a specific on-state resistance of 104 , and a current gain of . Operating at a unipolar gate bias of 2.5 V lowers the on-state resistance to 96 and raises the drain-current output to 79.3 mA, with the current gain being relatively high at . Thus, this 9-kV VJFET is capable of efficient power switching operation with high current gain at a low unipolar resistance.

Résumé: In this paper, we demonstrate a single-stage 90-nm CMOS power amplifier (PA) for 2.3–2.7-GHz WiMAX (802.16e) band applications. An integrated balun is used to match the output to 50- load. The PA gain and saturated power are 18 and 32 dBm, respectively, working from a 3.3-V supply, with a peak power-added efficiency of 48%. A digital-predistortion technique is used to enhance the PA linearity. The measured error vector magnitude for a 64 quadrature amplitude modulation orthogonal frequency-division multiplexing signal is improved from 24 to 30 dB at 25-dBm output power. Compliance with the 802.16e standard 10-MHz WiMAX mask and Federal Communications Commission regulations is demonstrated at 25 dBm of output power with power efficiency of 25% and with a measured second harmonic level of 31 dBm/MHz. Using a crest factor reduction technique, mask compliance is achieved at 27 dBm with tradeoff on dB, sufficient for quadrature phase-shift keying.

Résumé: A 60-GHz four-element bidirectional phased-array transmitter/receiver (TX/RX) chip with a two bit phase shifter (PS) and IF converter to/from 12 GHz, using a 90-nm CMOS process, is described. The array features 7-dB gain, measured noise figure of 9 dB, IP1dB of 19 dBm for RX, and output of 3.5 dBm for TX, drawing 60 mA from a 1.3-V supply. The rms amplitude and phase error of the PS is 0.7 dB and 2 max, respectively, from 57 to 66 GHz. This new architecture, together with the compact layout, decreases chip size by a factor of 2, compared to a separate TX and RX design. The use of passive PSs and combiners reduces the current consumption and minimizes temperature variation. An additional rms error of 0.3° and 0.07 dB was measured from 0 C to 80 C. Total die area is 1.6 1 mm and 1.6 0.65 mm with and without an IF converter block, respectively. First pass success was achieved by the closed ground environment design methodology of the passive structures and by proper layout. To our knowledge, this is the first report on a bidirectional 60-GHz array with the lowest reported chip power consumption and size.

Résumé:Wireless sensor networks have emerged in strategic applications such as target detection, localization, and tracking, where the large scale renders centralized control prohibitive. In addition, the finite batteries of the nodes demand energyaware network control. In this article we propose an energy-efficient topology management model inspired by biological intercell signaling schemes, which allows sensor nodes to form clusters around imminent targets in a purely distributed and autonomous fashion. In particular, nodes in the target vicinity collaborate to form a cluster according to their relative observation quality values, based on a bioinspired lateral induction process. Subsequently, the clustered nodes compete according to their energy levels until some of them gain active status while the rest remain idle, based on a bio-inspired lateral inhibition process. A final phase of the model has the active cluster members compete until one of them becomes the clusterhead, again based on the lateral inhibition process. We examine the behavior of such a network control flow in both finite-size and infinite-size networks. Specifically, we show that the proposed model is inherently stable and discuss its convergence for networks of finite size. Furthermore, we discuss the asymptotic behavior when the number of nodes goes to infinity, where we study the average number of active cluster members.

Résumé: We denote the set of binary words of length . A partition of with quotient matrix is equitable if for all and , any word in has exactly neighbors in . The equitable partitions of can be obtained from completely regular codes. We derive a bound on equitable partitions of that does not depend on the size of the partition.

Résumé:A mobility model for high-k gate-dielectric Ge pMOSFET with metal gate electrode is proposed by considering the scattering of channel carriers by surface-optical phonons in the high-k gate dielectric. The effects of structural and physical parameters (e.g. gate dielectric thickness, electron density, effective electron mass and permittivity of gate electrode) on the carrier mobility are investigated. The carrier mobility of Ge pMOSFET with metal gate electrode is compared to that with poly-Si gate electrode. It is theoretically shown that the carrier mobility can be largely enhanced when poly-Si gate electrode is replaced by metal gate electrode. This is because metal...

Résumé: A filterless class-AB/D audio power amplifier integrated into a feature-rich 2.5G/3G baseband processor in standard 65-nm CMOS technology is designed for direct battery hookup in mobile phone applications. Circuit techniques are used to overcome the voltage limitations of standard MOS transistors for operation at voltage levels of 2.5–4.8 V. Both amplifiers can drive more than 650 mW into an 8- load with maximum distortion levels of 1% and 5% for class-D and class-AB, respectively, all from a 3.6-V power supply. The achieved power-supply-rejection ratios are 72 and 84 dB, respectively. The mono implementation of both amplifiers together is 0.44 .

Résumé: A hybrid CMOS/thin-film microsystem for fluorescence contact imaging is presented. The microsystem integrates a high-performance optical interference filter and a 128 128 pixel active pixel sensor fabricated in a standard 0.35- CMOS technology. The thin-film filter has an optical density greater than 6.0 at the wavelength of interest, providing adequate excitation rejection to the 532-nm solid-state laser. Microsystem performance is experimentally validated by imaging spots of Cyanine-3 fluorophore, conventionally used in DNA detection. The emission intensity as a function of fluorophore concentration is measured with an estimated sensitivity of 5000 . A human DNA microarray has been imaged with the sensor prototype.

Résumé: This paper presents a simple and efficient seat occupancy detector. A seat occupancy detector is an integral part of the airbag safety system and, in its simplest form, provides the (occupied or vacant) status of the seat to the airbag control unit. Although the occupancy sensing methods based on a capacitive principle are efficient, they typically require electrodes to be placed in the surface layer of the sitting and backrest areas of the seat. The proposed sensor uses a simple electrode structure, and it is placed below the seat foam in the sitting area of the seat. These features promise a less-expensive sensor as it can be easily manufactured and installed in a seat. The new sensor combines inductive and capacitive proximity sensing principles. The sensor detects the presence of an occupant exploiting the shielding effect of the electric field while its inductive proximity feature senses the presence of conductive objects (e.g., laptop) that may be placed in the seat and helps to achieve reliable occupancy sensing. The measurement system uses a signal conditioning unit based on a carrier frequency principle. A prototype sensing system has been built, and its application as a seat occupancy sensing system in a vehicle has been verified. The developed system successfully senses human proximity and distinguishes it from other conductive objects.

Résumé: This paper presents a method for fast and comprehensive simulation of signal propagation, power/ground noise, and radiated emissions by combining the merits of the physics-based via model, the modal decomposition technique, the contour integral method (CIM), and the equivalence principle. The physics-based via model combined with the modal decomposition technique is an efficient technique for signal integrity analysis of multilayer PCBs and packages. The CIM can be used to calculate the voltage distribution between arbitrarily shaped power planes. Far-field radiation can be obtained by applying the field equivalence principle. In this paper, we integrate the four techniques to analyze all the three effects in a fast, concurrent, and holistic manner. To the best knowledge of the authors, the four techniques are integrated here for the first time. Various structures are simulated and validated with full-wave simulations up to 20 GHz. It is shown that a reduction in simulation time of more than two orders of magnitude is achieved in comparison to a standard full-wave electromagnetic solver.

Résumé: A compact wide-band passive equalization design using a stub with defected ground structure is proposed. The proposed design, based on reflections under a slow wave effect, compensates for inter-symbol interference with wide bandwidth, compact size, remarkable compensation capability with few manufacturing limitations, and high design flexibility, compared to previous equalization design. Significant improvements in eye-opening and timing jitter are successfully demonstrated for a data rate of 8 Gbps for a 60 cm transmission line on a printed circuit board.

Résumé: This paper presents a comparison of Markov load models for composite reliability evaluation by nonsequential Monte Carlo simulation. The proposed models represent the whole system load curve. The first model (M1) is an aggregated Markov model that represents all different states present in the load curve, without using any clustering technique. The second model (M2) consists of a hybrid Markov model, where all different levels of the load curve are also represented but it tries to preserve some chronology of the load curve. The third model (M3) consists of a non-aggregated Markov model. The frequency and duration (F&D) indices are calculated by the conditional probability method for all models. The indices calculated using these models are compared with the indices obtained when the usual clustered aggregated Markov model (M0) is used. The indices obtained by sequential Monte Carlo simulation with a chronological system load curve are used as comparison reference in order to validate the presented models.

Résumé: The IEEE 802.16 standard is considered to be one of the most promising technologies. Bandwidth reservation is employed to provide quality of service (QoS)-guaranteeing services. A request/grant scheme is defined in the IEEE 802.16 standard. There are two types of bandwidth request (BR) mechanisms, i.e., unicast polling and contention resolution, which are defined in the standard. As specified, connections belonging to scheduling classes of extended real-time polling service, non-real-time polling service, and best effort have options to make BRs via both mechanisms, depending on the scheduling decision made by the base station (BS). However, most research assumes that only one of them is available and do not take both of them into account. A comprehensive study of both mechanisms is critical for the BS to make an appropriate decision for those connections to achieve better system performance. To the best of our knowledge, this is the first attempt to analyze this issue. There are two major contributions presented in this paper. First, a comprehensive study of both BR mechanisms in terms of bandwidth utilization and delay is provided. Additionally, we propose two practical performance objectives: When the expected delay or target bandwidth utilization is given, how does the BS make a scheduling decision such that the performance of the other metric (either delay or bandwidth utilization) is optimized? As our second contribution, we proposed two scheduling algorithms to find the combination of both mechanisms to meet our objectives. The simulation results show that our scheduling algorithms can always help the BS make a scheduling decision to reach better system performance.

Résumé:This letter presents a computationally efficient joint transmit and receive antenna selection (EJTRAS) algorithm based on a modification of the selection criterion in [1]. We show that the modification allows us to reduce the algorithmÂ¿s computational complexity by a factor of L, where L is the number of selected antennas without sacrificing the performance. Nearoptimal outage and ergodic capacity can therefore be attained with significantly lower complexity as verified by the extensive computer simulations.

Résumé: ac-powered contactors are extensively used in industry in applications such as automatic electrical devices, motor starters, and heaters. In this work, a practical session that allows students to model and simulate the dynamic behavior of ac-powered electromechanical contactors is presented. Simulation is carried out using a rigorous parametric model of the ac contactor that avoids simplification assumptions and is thoroughly explained. The goal of this practical is to introduce students to the topic of dynamic simulation of real devices. It covers both the transient and the steady-state response of the electromechanical system under study. The proposed methodology is flexible and not particularly time-consuming, and it allows the students easily to change the electromechanical constants of the contactor they are studying. The results of the simulations were compared with experimental data acquired by the students; a close similarity between real and simulated data was observed. The Technical University of Catalonia (UPC), Spain, has incorporated the simulation methodology proposed in this paper in a practical session of an electrical engineering course.

Résumé:This paper presents a methodology to synthesize MPEG-4 video traffic traces with hierarchical levels of compression. In real-time video streaming applications, scalable video transmission is employed to adjust quality of service (QoS) requirements to the available channel bandwidth. The proposed model is a very simple tool to simulate scalable video traffic transmission, in order to evaluate the performance of computer networks under different traffic loads and transport protocols. The MPEG-4 streaming is classically modeled as a self-similar random process, due to the long range dependence of the autocorrelation function. The presented model is based on statistical analysis collected from real...

Auteurs: Marcelo Eduardo, Pellenz , Richard Demo, Souza

Apparue dans: AEU - International Journal of Electronics and Communications

Résumé:Direct certainty equivalence results for output feedback stabilization of nonlinear systems are proposed. The first result is a simple extension of the indirect approach used in a paper by Praly and Arcak. The second result allows to deal with observers yielding nonuniformly converging estimates with respect to the norm of (a subset of) the system state. Application of these results with the reduced-order observer of Karagiannis are discussed.

Résumé:Identifying the trap configuration is essential for understanding non-volatile memory device performance and reliability. In this paper, an accurate approach to determine the trap distribution in the charged layer is presented. The analysis is done by Trap Spectroscopy by Charge Injection and Sensing (TSCIS) technique [1] varying charge injection time and gate voltage independently. Varying time determines the physical charge injection distance. The conversion of time into distance is done based on theoretical modeling simplified to only electron capturing from Shockley-Read-Hall (SRH) statistics. Direct tunneling of the electrons from quantized energy levels in inverted Si channels to the oxide traps...

Résumé: Both direct and indirect methods exist for identifying continuous-time linear systems. A direct method estimates continuous-time input and output signals from their samples and then use them to obtain a continuous-time model, whereas an indirect method estimates a discrete-time model first. Both methods rely on fast sampling to ensure good accuracy. In this paper, we propose a more direct method where a continuous-time linear model is directly fitted to the available samples. This method produces an exact model asymptotically, modulo some possible aliasing ambiguity, even when the sampling rate is relatively slow. We also state conditions under which the aliasing ambiguity can be resolved, and we provide experiments showing that the proposed method is a valid option when a slow sampling frequency must be used but a large number of samples is available.

Résumé: This brief deals with the problem of blind source separation (BSS) via independent component analysis (ICA). We prove that a linear combination of the separator output fourth-order marginal cumulants (kurtoses) is a valid contrast function for ICA under prewhitening if the weights have the same sign as the source kurtoses. If, in addition, the source kurtoses are different and so are the linear combination weights, the contrast eliminates the permutation ambiguity typical to ICA, as the estimated sources are sorted at the separator output according to their kurtosis values in the same order as the weights. If the weights equal the source kurtoses, the contrast is a cumulant matching criterion based on the maximum-likelihood principle. The contrast can be maximized by means of a cost-efficient Jacobi-type pairwise iteration. In the real-valued two-signal case, the asymptotic variance of the resulting Givens angle estimator is determined in closed form, leading to the contrast weights with optimal finite-sample performance. A fully blind solution can be implemented by computing the optimum weights from the initial source estimates obtained by a classical ICA stage. An experimental study validates the features of the proposed technique and shows its superior performance compared to related previous methods.

Résumé:A simple method to prepare large-scale graphene sponges and free-standing graphene films using a speed vacuum concentrator is presented. During the centrifugal evaporation process, the graphene oxide (GO) sheets in the aqueous suspension are assembled to generate network-linked GO sponges or a series of multilayer GO films, depending on the temperature of a centrifugal vacuum chamber. While sponge-like bulk GO materials (GO sponges) are produced at 40 °C, uniform free-standing GO films of size up to 9 cm2 are generated at 80 °C. The thickness of GO films can be controlled from 200 nm to 1 µm based on the concentration of the GO colloidal suspension and evaporation temperature. The synthesized GO films exhibit excellent transparency, typical fluorescent emission signal, and high flexibility with a smooth surface and condensed density. Reduced GO sponges and films with less than 5 wt% oxygen are produced through a thermal annealing process at 800 °C with H2/Ar flow. The structural flexibility of the reduced GO sponges, which have a highly porous, interconnected, 3D network, as well as excellent electrochemical properties of the reduced GO film with respect to electrode kinetics for the [Fe(CN)6]3-/4- redox system, are demonstrated.

Résumé: In this brief, a convolutional learning system for classification of segmented objects represented in 3-D as point clouds of laser reflections is proposed. Several novelties are discussed: 1) extension of the existing convolutional neural network (CNN) framework to direct processing of 3-D data in a multiview setting which may be helpful for rotation-invariant consideration, 2) improvement of CNN training effectiveness by employing a stochastic meta-descent (SMD) method, and 3) combination of unsupervised and supervised training for enhanced performance of CNN. CNN performance is illustrated on a two-class data set of objects in a segmented outdoor environment.

Résumé: This paper investigates the use of logic implication checkers for the online detection of errors. A logic implication, or invariant relationship, must hold for all valid input conditions; therefore, any violation of this implication will indicate an error due to an intermittent fault. Techniques are presented to efficiently identify the most useful logic implications to include in checker hardware such that the probability of error detection is maximized while minimizing the additional hardware and delay overhead. Results show that significant error detection is possible—even with only a 10% area overhead—while minimizing impact on delay and power.

Résumé: This paper presents a simple, cost-effective and robust atomic force microscope (AFM), which has been purposely designed and built for use as a teaching aid in undergraduate controls labs. The guiding design principle is to have all components be open and visible to the students, so the inner functioning of the microscope has been made clear to see. All of the parts but one are off the shelf, and assembly time is generally less than two days, which makes the microscope a robust instrument that is readily handled by the students with little chance of damage. While the scanning resolution is nowhere near that of a commercial instrument, it is more than sufficient to take interesting scans of micrometer-scale objects. A survey of students after their having used the AFM resulted in a generally good response, with 80% agreeing that they had a positive learning experience.

Résumé:We report on the realization and operation of a fast ion beam trap of the linear electrostatic type employing liquid helium cooling to reach extremely low blackbody radiation temperature and residual gas density and, hence, long storage times of more than 5 min which are unprecedented for keV ion beams. Inside a beam pipe that can be cooled to temperatures <15K, with 1.8 K reached in some locations, an ion beam pulse can be stored at kinetic energies of 2–20 keV between two electrostatic mirrors. Along with an overview of the cryogenic trap design, we present a measurement of the residual gas density inside the trap resulting in only 2×103cm-3, which for a room temperature environment corresponds to a pressure in the 10-14mbar range. The device, called the cryogenic trap for fast ion beams, is now being used to investigate molecules and clusters at low temperatures, but has also served as a design prototype for the cryogenic heavy-ion storage ring currently under construction at the Max-Planck Institute for Nuclear Physics.

Résumé:In this paper, the authors propose and analyze a network-based control architecture for power-electronics-building-block-based converters. The objective of the proposed approach is to distribute the control system to guarantee maximum flexibility in the control of power distribution. In the proposed control system, controller and controlled devices are connected through the network, which affects the measurement and control signals mostly due to delays. The main goal of this work is to outline a design methodology for controllers operating with measurements coming from a network. The approach proposed here assesses the robustness of the control system in the presence of delay and aims to design an optimal controller for robustness against network delays. This methodology is based on uncertainty analysis and assumes that the delays are the main element of uncertainty in the system. The theoretical foundations of this approach are discussed, together with the simulation and implementation of a physical laboratory prototype.

Résumé: This paper presents a low-power, high-speed direct digital synthesizer monolithic microwave integrated circuit in a SiGe bipolar technology with 8-bit phase and 6-bit amplitude resolution. The phase-to-amplitude mapping circuit is implemented as a differential pair in saturation. The use of a modern SiGe bipolar technology enables both a low power consumption of 488 mW at a 3.3-V supply and a high clock frequency of 16.8 GHz; here, the maximum output frequency is 8.3344 GHz and the frequency resolution is 65.625 MHz. A spurious-free dynamic range (SFDR) between 47–20 dBc is achieved. First Nyquist zone SFDR, narrowband SFDR, and frequency-modulation measurements of the signal are shown and discussed. The chip is fabricated in a 0.35- m 200-GHz SiGe bipolar technology and occupies only 1128 1028 m . The chip is mounted on a printed circuit board for measurement.

Résumé: This paper presents a wideband digital frequency synthesizer architecture targeted for spectrum sensing applications. The proposed frequency synthesizer architecture is based on digital period synthesis (DPS), which inherently can achieve a wide operational bandwidth, extremely high-frequency resolution, and an instantaneous settling time with low power and area consumption. The performance of DPS and its fundamental limitations are analyzed in this paper. The frequency synthesizer was implemented in a 65-nm CMOS process and it occupies an active area of 0.12 mm . The frequency range of the synthesizer is from 0.1 to 4.267 GHz with a frequency resolution of 0.025–5.38 Hz. In this frequency range, the power consumption is between 3.6–8.4 mW.

Résumé: This paper compares area scaling capabilities of many kinds of SRAM margin-assist solutions for variability issues, which are based on various efforts by not only the cell topology changes from 6T to 8T and 10T but also incorporation of multiple voltage supply for cell terminal biasing and timing sequence controls of read and write. The various SRAM solutions are analyzed in light of an impact on the required area overhead for each design solution given by ever-increasing random variation , resulting in a slowdown in the SRAM scaling pace. In order to predict the area scaling trends among various SRAM solutions, two different -increasing scenarios of being pessimistic and optimistic are assumed, where becomes mV and suppressed to mV at the 15-nm process node, respectively. As a result, it has been shown that the 6T SRAM cell will be allowed long reign, even in the 15-nm process node, if can be suppressed to mV thanks to effective oxide thickness scaling for the low-standby-power process; otherwise, 10T and 8T with read–modify–write will be needed after becomes and 75 mV, respec-
tively.

Auteurs: Yamauchi, H.;

Apparue dans: IEEE Transactions on Very Large Scale Integration Systems

Résumé:The goal of applying collaborative product development in industry has raised the need to develop software tools supporting system integration and group collaboration. Current methods and tools mainly focus on the collaborative creation of design components and assemblies. However, few of them support the collaborative work in developing simulation models so that proposed design concepts and solutions can be evaluated by integrating expertise from several disciplines. The purpose of this research is to develop a distributed and interactive system on which designers and experts can work together to create, integrate and run simulations for engineering design. To develop such a...

Résumé: A versatile electromagnetic modeling methodology is presented that is most suitable for use in the computer-aided design of the power distribution network (PDN) of packaged electronics. The method is characterized by modeling flexibility and computational efficiency. These attributes stem from the adoption of a modular approach for the development of the model, where the fine-feature, geometric discontinuities in the network, such as pins, vias, and splits in metallization layers, are modeled separately from the solid planar ground and power metallization portions. In this manner, multiport network models of these discontinuities are developed, making possible their expedient insertion in a discrete electromagnetic model for the solid portions of the metallization. The latter is based on a 2-D integral equation model for the cylindrical transverse electromagnetic field behavior between the metallization planes, for which only electrically important features are preserved and modeled. The utilization of a systematic decomposition approach further enhances the modeling versatility of the proposed method and enables the development of a modeling methodology that is suitable for computer-aided iteration in the electromagnetic performance-aware design of multilayer PDNs. Validation studies are used to demonstrate the efficiency of the proposed methodology and assess its accuracy as a computer-aided tool for PDN predesign.

Résumé:In this paper, the optimum design of a factorable Nyquist filter with the intersymbol interference (ISI) being exactly zero is formulated as a nonlinear optimization problem with continuous inequality constraints. An iterative scheme is developed for solving this semi-infinite optimization problem, where an improved dual parametrization method is utilized in each iteration of the iterative scheme. Trade-off between robustness against timing jitter and small stopband attenuation is achieved via an adjustment of a parameter. Some examples are solved using the proposed iterative method.

Résumé: A SAW-less dual-band I/Q transmitter without a driver amplifier is designed for dual-band (personal communication system (PCS)/International Mobile Telecommunications (IMT) and cellular) code division multiple access applications. The receive band noise is less than 159 dBc/Hz. It can provide up to 5-dBm output power and meets the adjacent channel power ratio and dynamic range requirements of both PCS/IMT and cellular CDMA. The measured is better than 10 dB for both bands and it requires no external matching components. The transmitter is implemented in a 65-nm digital CMOS technology and is packaged using flip-chip technology. The transmitter signal path (RF portion) occupies 1.0 mm .

Résumé: A new technique using a left-handed (LH) resonator to generate a multiband millimeter-wave carrier signal is proposed in this paper. The LH resonator exhibits nonlinear dispersion characteristic, which enables uneven spacing between resonant frequencies. With stages of the LH unit cell, there are resonant frequencies from the nonlinear dispersion curve. Moreover, the band selection switches are not located in the signal path, which can, therefore, dramatically reduce the size of switches and improve the overall quality factor of the resonator. A dual-band millimeter-wave oscillator in digital 90-nm CMOS technology is implemented to demonstrate this new technique. Using a mode selection switch, the proposed oscillator operates at 21.3 and 55.3 GHz, respectively, with a total power consumption of 14 mW.

Résumé: This paper presents the design of a new ADDLL for clock synchronization in a SoC, regardless if the clock duty cycle is seriously distorted from 50%. A half-delay-line circuit and an improved successive-approximation-register controller are developed on top of the coarse-fine architecture for fast lock-in, high duty-cycle-distortion tolerant, and low power. Difference-type circuits and the design techniques for reducing the number of active delay cells and suppressing the dithering effect are developed for low jitter. Measurement results show that when operated at 1.0 V, the 55 nm ADDLL has a maximal frequency of 850 MHz with 1.19 power index, 2 ps p-p jitter, and 6 lock-in cycles. The minimal operation frequency is 200 MHz and 60 MHz when the input duty cycle is 50% and 85%, respectively.

Résumé:A Fabry–Pérot enhanced electro-optic sensing system that utilizes a drive-current-tuned wavelength laser diode is presented. An electro-optic prober made of LiNbO3 crystal with an asymmetric Fabry–Pérot cavity is used in this system. To lock the wavelength of the laser diode at resonant condition, a closed-loop power control scheme is proposed. Experiment results show that the system can keep the electro-optic prober at high sensitivity for a long working time when the closed-loop control function is on. If this function is off, the sensitivity may be fluctuated and only one-third of the best level in the worst case.

Résumé: This paper investigates a factorization approach to sensitivity loop shaping for disturbance rejection in hard disk drives (HDDs). The advantage of the factorization approach is that the system sensitivity function can be expressed explicitly in terms of a unique design parameter. This greatly simplifies the control design process to make the system sensitivity function match a chosen target sensitivity function with guaranteed stability. By decomposing the controller structure, the design parameter is revealed to behave as a plug-in disturbance filter, the design of which is then presented to suppress the dominant disturbances at some specific frequencies. It is also shown that based on the nominal control system the proposed disturbance filter can reduce the sensitivity gains at specific frequencies without worsening the neighbouring sensitivity gains. Simulation together with implementation results demonstrate that the proposed method can effectively suppress the disturbances around the servo bandwidth and accordingly offers a superior tracking accuracy in comparison with other existing filters.

Résumé: We propose a family of nonlinear state feedback global stabilizers for all planar linear systems which are globally stabilizable by bounded inputs (namely, all non exponentially unstable linear systems). This family is parametrized by a nonlinear function whose selection can yield quasi time-optimal responses, where the “quasi” is required to achieve local exponential stability of the closed loop. The arising trajectories are quasi-time-optimal for arbitrarily large initial conditions; so, we expect the very simple proposed nonlinear control law to be very useful for embedded control applications with strong computational constraints.

Résumé:It was the first US election of a new millennium, a golden era of technological innovation and white-hot Internet stocks. It should have been a celebration of the democratic might of the world's only remaining superpower. Instead, the decision of who should lead the most powerful country on the planet was made by bewildered lawyers poring over tiny scraps of cardboard.

Résumé: The magnetic induction tomography (MIT) image reconstruction is a distributed parameter estimation problem normally solved iteratively, where each iteration engages several 3-D harmonic eddy-current problems. These calculations are the main time-consuming process in the MIT reconstruction. In this paper, an approach to accelerate the resolution of a set of similar eddy-current problems to be used in the reconstruction process is presented. Each eddy-current problem is described by a reduced magnetic vector potential eddy-current formulation using the finite integration technique (FIT) framework defined over an octree based subgridding scheme with several performance precautions. The solver accuracy is compared with analytical solutions of appropriate geometrical scenarios. A performance assessment is presented for a full set of eddy-current problems that constitutes a forward problem. The new method reduced the computing time approximately to 11% of a similar problem without performance concerns maintaining a relative mean error inferior to 1.5% relatively to analytical simulations.

Résumé: With the advent of wireless microsensors and other microscale applications, switching supplies fully integrated on chip or into the package are desirable and often necessary. The problem with small inductors is that they exhibit low inductance and larger equivalent series resistance (ESR); in other words, they induce larger ripples in the output and higher conduction power losses. This brief presents and verifies a current-ripple suppression technique in which a discrete 4.7- inductor is effectively multiplied by subtracting a replica of the inductor's ac ripple current, allowing only a residual ripple to reach the output. Experimental results from a complementary metal–oxide–semiconductor integrated circuit prototype demonstrate a current- and output-ripple reduction of and , respectively. The ESR power savings in the smaller inductor favorably offset the quiescent power lost in the multiplier (128 mW), outperforming its higher nonmultiplied 47- counterpart at high loads (above 250 mA).

Résumé: In this paper, a novel device for sensing perturbations imposed to liquid media contained in a disposable housing is addressed. The device consists of a glass beaker filled with deionized water surrounding a small volume of ferrofluid; a permanent magnet is used to fix the position of the ferrofluidic mass in a compliant position and to generate spikes due to the Rosensweig effect. The effect of external stimuli on the beaker can be estimated by measuring the perturbation produced on the ferrofluidic mass. The latter strategy allows reducing drawbacks related to static friction of conventional inertial devices. The ferrofluid perturbations are monitored by two external planar coils in a differential configuration. The main features of the proposed strategy are structural decoupling between the electric read-out system and beaker housing, which allows both implementing noninvasive measurement in liquid media and making the architecture partially disposable, of low cost, and suitable for real applications.

Résumé:This paper describes a flexible microplasma jet device using a Tygon® S-54-HL tube as a biocompatible tube and its potential in developing cancer therapies. The optical and physical properties of the plasma jets and preliminary apoptosis data of cultured murine tumor cells and nontumor fibroblast cells treated with these plasma jets are presented. Microplasma jets were observed to induce apoptosis in cultured murine cells in a dose-dependent manner. The murine melanoma tumor cells were more sensitive to plasma treatment than fibroblast cells. These features allow the direct and precise application of this microplasma jet device to tumor cells.

Résumé: The specific problems encountered in the design of near-field focused planar microstrip arrays for RFID (Radio Frequency IDentification) readers are described. In particular, the paper analyzes the case of a prototype operating at 2.4 GHz, which has been designed and characterized. Improvements with respect to conventional far-field focused arrays (equal phase arrays) are discussed and quantified.

Résumé: This paper presents a fully integrated transmitter with embedded on-chip antennas to demonstrate on-wafer wireless testing. First, on-chip antenna characterization methods based on the measured transmission link gain are described. From the measured transmission link gain, the on-chip antenna gain is determined using the known transmitter gain, a path loss, and an off-chip antenna gain. The proposed two-step method utilizes a high-gain off-chip antenna transmission link for base line calibration data to obtain better gain accuracy. For wireless testing, a fully integrated a 1.2-GHz Hartley image-reject transmitter is implemented in an 40-GHz InGaP/GaAs HBT process. The image rejection (IR) ratio is measured to demonstrate process control monitoring of device mismatches. Both dipole and loop antennas are integrated to study their radiation efficiency as their dimensions are much less than the wavelength. The loop antenna provides about 7 dB better transmission gain. The IR ratio is measured wirelessly from a number of samples to monitor the die-to-die variations in the in-phase/quadrature mismatch. Monte Carlo simulations are used to aid the analysis of the sources of amplitude and phase mismatches.

Résumé: The paper deals with the problem of blind source extraction from a multiple-input/multiple-output (MIMO) convolutive mixture. We define a new criterion for source extraction which uses higher-order contrast functions based on so called reference signals. It generalizes existing reference-based contrasts. In order to optimize the new criterion, we propose a general algebraic algorithm based on best rank-1 tensor approximation. Computer simulations illustrate the good behavior and the interest of our algorithm in comparison with other approaches.

Résumé: This paper discusses a general model of differential power analysis (DPA) attacks to static logic circuits. Focusing on symmetric-key cryptographic algorithms, the proposed analysis provides a deeper insight into the vulnerability of cryptographic circuits. The main parameters that are of interest in practical DPA attacks are derived under suitable approximations, and a new figure of merit to measure the DPA effectiveness is proposed. Worst case conditions under which a cryptographic circuit should be tested to evaluate its robustness against DPA attacks are identified and analyzed. Several interesting properties of DPA attacks are also derived from the proposed model, whose fundamental expressions are compared with the counterparts of correlation power analysis attacks. The model was validated by means of DPA attacks on an FPGA implementation of the advanced encryption standard algorithm. Experimental results show that the model has a good accuracy, as its error is always lower than 2%.

Auteurs: Alioto, M.;Poli, M.;Rocchi, S.;

Apparue dans: IEEE Transactions on Very Large Scale Integration Systems

Résumé: Quantized consensus assumes that the state of each node may only take nonnegative integer values. Reaching consensus under quantization is equivalent to determining a balanced assignment of identical tasks to nodes. In this note, we generalize this problem in two ways and denote the resulting framework discrete consensus. First, we consider tasks that are not identical: each one is characterized by its own weight. Secondly, we assume that nodes are not identical as well. As an example, in the case of task assignment, that we consider as a reference problem in this framework, nodes may have different speeds and should be assigned a total weight proportional to their speed. We provide a gossip-based distributed algorithm that aims to minimize the maximum execution time over nodes, whose convergence to a bounded set is guaranteed. We show that the convergence time of the proposed algorithm relies ultimately on the average meeting time between two agents performing a random walk on a graph.

Résumé:Hybrid parallel kinematic machines (HPKM) are prone to structural deflection under the influence of gravity, both in the serial wrist joints and in the upper tripod structure. The deflection results in errors at the tool tip, leading to manufacturing inaccuracies and performance outside the manufacturer's quoted accuracy. To further increase the take-up of HPKMs robust online compensation strategies are required that return and maintain the HPKM to the quoted accuracy level under production conditions.This paper addresses the problem of mass-induced errors in the positional accuracy of hybrid parallel kinematic machines (HPKMs) and describes the development of a novel robust polar...

Résumé:Highly turbulent environment of dynamic job-shop operations affects shop floor layout as well as manufacturing operations. Due to the dynamic nature of layout changes, essential requirements such as adaptability and responsiveness to the changes need to be considered in addition to the cost issues of material handling and machine relocation when reconfiguring a shop floor's layout. Here, based on the source of uncertainty, the shop floor layout problem is split into two sub-problems and dealt with by two modules: re-layout and find-route. GA is used where changes cause the entire shop re-layout, while function blocks are utilised to find the...

Résumé: Forward error correction (FEC) is the preferred way of coping with the error-prone nature of wireless links in broadcasting systems, because it can provide a bounded delay, which is a particular consideration for real-time multimedia applications. Additionally, controlling the variability of the delay, or jitter, is important in achieving seamless multimedia services. We show that error control using Reed–Solomon (RS) FEC in the medium-access control (MAC) layer can be a major source of jitter. We predict the expected delay incurred by RS decoding for varying levels of block interleaving in a mobile, under a range of channel conditions, using a hybrid simulation and analytic approach, which is based on the error statistics of data transmission over fading channels. The results allow us to determine the size of the buffer required to avoid frequent service interruptions.

Résumé: This letter presents a hybrid error control and artifact detection (HECAD) mechanism which can be used to enhance the error resilient capabilities of the standard H.264/advanced video coding (AVC) codec. The proposed solution first exploits the residual source redundancy to recover the most likelihood H.264/AVC bitstream. If error recovery is unsuccessful, the residual corrupted slices are then passed through a pixel-level artifact detection mechanism to detect the visually impaired macroblocks to be concealed. The proposed HECAD algorithm achieves overall peak signal-to-noise ratio gains between 0.4 dB and 4.5 dB relative to the standard with no additional bandwidth requirement. The cost of this solution translates in a marginal increase in the complexity of the decoder. In addition, this method can be applied in conjunction with other error resilient strategies and scales well with different encoding configurations.

Résumé:The performance of trees as windbreaks is principally determined by their geometric characteristics. This paper reports the development of a laser scanning system to measure tree geometric characteristics on-the-go and its use to estimate percent wind velocity reduction in a windbreak. The laser scanning system was built by mounting a laser sensor, a global positioning system (GPS) receiver, and a notebook computer on a test vehicle. A windbreak was established by arranging a set of large potted trees in a pattern that provided two porosities for wind velocity measurements (windbreaks I and II). Winds generated by a blower at low...

Résumé: In this paper, we propose an alternative efficient method to calculate the Gabor coefficients of a signal given a synthesis window with a support of size much lesser than the length of the signal. The algorithm uses the canonical dual of the window (which does not need to be calculated beforehand) and achieves a computational cost that is linear with the signal length in both analysis and synthesis. This is done by exploiting the block structure of the matrices and using an ad hoc Cholesky decomposition of the Gabor frame matrix.

Résumé: Using a complementary spiral resonator mounted on the power plane, simultaneous switching noise and ground bouncing noise can be suppressed over a very wideband from 0.22 to 12.5 GHz under a noise suppression margin of −25 dB. Not only the suppression characteristic under 12.5 GHz is possible, but also over the higher frequency band, because the proposed structure operates like an RF choke. Therefore, the proposed structure can satisfy the 10% noise margin for the voltage swing ratio for both periodic and random clock signals. A size of 3.2 mm is necessary for the diameter of the resonator on the power plane, and is comparable to a clearance pad size with diameter of 3.0 mm in a ground plane. Hence, the small size helps to reduce the discontinuity of the return current path; therefore, signal integrity problems and the degrees of freedom for power plane design of an electromagnetic bandgap structure are enhanced. Moreover, the effects of inductance and capacitance in the spiral resonator are analyzed for modeling. As a result, the suppression bandwidth and resonance frequency are controlled by the arm length and gap of spiral resonator. In addition, by applying two different sizes of resonators, it is shown that a multiresonance effect is also obtained.

Résumé:In this paper we describe our low temperature scanning tunneling microscopy system with ultrahigh vacuum sample preparation capabilities. The main focus lies on the specialized silicon preparation facility which is the most unusual part. Other special solutions such as sample transport will also be described in detail. Finally, we demonstrate the ability to prepare high quality silicon (111) and (100) surfaces.

Résumé: An architectural solution for designing and implementing low THD oscillators is presented. A digital harmonic-cancellation-block is used to suppress the low-frequency harmonics while a passive, inherently linear, filter is used to suppress the high-frequency ones. The proposed technique eliminates the need for typical high-Q BPF to suppress the harmonics. Thus, eradicates the effect of increasing device nonlinearities in the nanometric technologies by having pure digital solution. In addition, eliminating the need for high-Q band-pass-filter (BPF) releases the output swing from the constraints imposed by the linearity of the filter. The prototype is fabricated in 0.13 m CMOS technology. Measurement results show 72 dB THD at 10 MHz along with a differential output swing of 228 mV . The oscillator prototype can be tuned from 5 MHz to 11 MHz with less than 4.5 dB variations in the THD. The circuit consumes 3.37 mA from 1.2 V supply at 10 MHz and occupies an area of 0.186 mm . As the performance depends solely on the timing precision of digital signals, the proposed oscillator is considered the best time-mode-based oscillator in literature.

Résumé: A new inter-processor communication architecture for chip multiprocessors is proposed which has a low area cost, flexible routing capability, and supports globally asynchronous locally synchronous (GALS) clocking styles. To achieve a low area cost, the proposed statically-configurable asymmetric architecture assigns large buffer resources to only the nearest neighbor interconnect and much smaller buffer resources for long distance interconnect. To maintain flexible routing capability, each neighboring processor pair has multiple connecting links. The architecture supports long distance communication in GALS systems by transferring the source clock with the data signals along the entire path for write synchronization. Compared to a traditional dynamically-configurable interconnect architecture with symmetric buffer allocation and single-links between neighboring processor pairs, this implementation has approximately two times smaller communication circuitry area with a similar routing capability. Area and speed estimates are obtained with the physical design of seven chips in 0.18- m CMOS.

Auteurs: Yu, Z.;Baas, B. M.;

Apparue dans: IEEE Transactions on Very Large Scale Integration Systems

Résumé:This letter aims to design a low-complexity subcarrier-power allocation scheme to improve the communication reliability of various types of frequency-division multipleaccess (FDMA) systems. Both uplink and downlink are considered. Specifically, a low-complexity worst subcarrier avoiding (WSA) subcarrier-allocation scheme is proposed, in order to avoid assigning users the subcarriers experiencing severe fading. After the subcarrier-allocation, channel-inversion assisted powerallocation is employed to assign the subcarriers the corresponding power. Our studies and simulation results show that the achievable error performance of the FDMA systems employing the proposed subcarrier-power allocation algorithm is independent of the multiplexing method. The proposed algorithm outperforms the existing subcarrier-power allocation algorithms that have a similar complexity as the proposed one.

Résumé: A passive resonance mitigation technique is proposed for multidrop memory interfaces. In this method, coupled transmission lines are used to prevent destructive signal resonance caused by signal reflection from the capacitive loads and mismatches in the channel. The proposed idea is verified in a simple experimental setup that roughly models a multi-Dual In-Line Memory Module system, and measurement results are provided.

Résumé: A low-power pipelined ADC topology is presented which uses capacitive charge pumps, source-followers, and digital calibration to eliminate the need for power-hungry opamps to achieve good linearity in a pipelined ADC. The differential charge pump technique achieves 10-bit linearity, and does not require an explicit common-mode-feedback circuit. The ADC was designed to operate at 50 MS/s in a 1.8 V, 0.18 CMOS process, where measured results show the peak SNDR and SFDR of the ADC to be 58.2 dB (9.4 ENOB), and 66 dB respectively. The ADC consumes 3.9 mW for all active circuitry and 6 mW for all clocking and digital circuits.

Résumé:In the paper, a vibration damping system powered by harvested energy with implementation of the so called SSDV (Synchronized Switch Damping on Voltage Source) technique is designed and investigated. In the semi-passive approach, the piezoelectric element is intermittently switched from open circuit to specific impedance synchronously with the structural vibration. Due to this switching procedure, a phase difference appears between the strain induced by vibration and the resulting voltage, thus creating energy dissipation. By supplying the energy collected from the piezoelectric materials to the switching circuit, a new low-power device using the SSDV technique is proposed. Compared with the original...

Résumé:Lyapunov stability of Fractional Differential Equations is addressed in this paper. The key concept is the frequency distributed fractional integrator model, which is the basis for a global state space model of FDEs. Two approaches are presented : the direct one is intuitive but it leads to a large dimension parametric problem while the indirect one, which is based on the continuous frequency distribution, leads to a parsimonious solution. Two examples, with linear and non linear FDEs, exhibit the main features of this new methodology.

Résumé:Experimental results show that material component and loading modes may affect the properties of shape-memory alloys (SMAs) markedly. In order to investigate the influence of loading modes on pseudoelasticity behaviors fully, some experiments of NiTi specimens under pure tension, compression and torsion with the same material component are investigated. In terms of the phenomena observed in experiments, a macro-constitutive model is presented for considering the tension-compression asymmetry of polycrystalline NiTi SMAs. In this study, the macroscopic strain is taken account of elastic strain, macro-transformation strain and macro-temperature strain. The volume fraction of martensite is governed by the reduction in Gibbs'...

Résumé:Traditionally, Paschen’s curve has been used to describe the breakdown voltage for gaseous ionization between two electrodes. However, experiments have shown that Paschen’s curve, which is based on Townsend effects, is not necessarily accurate in describing breakdown between electrodes spaced less than 15μm apart. In this regime, electron field emission plays a significant role in the breakdown phenomenon, and recently an alternative mathematical description that accounts for ion-enhanced field emission was proposed to describe the breakdown voltage in small gaps. However, both Paschen’s curve and the small gap equation only work in certain regimes, and neither predicts the transition that occurs between Townsend and field emission effects—the so-called modified Paschen’s curve. In this work, a single, consistent mathematical description of the breakdown voltage is proposed that accounts for both Townsend ionization and ion-enhanced field emission mechanisms. Additionally, microscale breakdown experiments have been conducted in atmospheric air. The proposed formulation is compared to the present experiments and other atmospheric air experiments in the literature and describes the transition region in the breakdown curve. The proposed formulation represents a mathematical model for the modified Paschen’s curve.

Résumé: This paper presents an interactive module for learning both the fundamental and practical issues of servo systems. This module, developed using Simulink in conjunction with the Matlab graphical user interface (Matlab-GUI) tool, is used to supplement conventional lectures in control engineering and robotics subjects. First, the paper introduces the theoretical background of servo systems. Then, the interactive module is presented, with a description of its main features as well some hints on how to integrate Simulink models within Matlab-GUI. Some of the module's capabilities are illustrated through classroom examples. Finally, the experience of putting this into use and student assessment of the tool are also addressed.

Résumé: IP security (IPsec) protocols are widely used to protect sensitive data over the Internet. For equipment linked by high-bandwidth optical fibers, the throughput requirement usually results in the adoption of high-performance network security processors. In this paper, we propose a parallel mesh-structured IPsec (MIPsec) processor, which executes the IPsec protocols for Internet security gateway applications. We have developed several area-efficient cryptographic IPs embedded in MIPsec to lower silicon cost. Thanks to structural regularity, the simple deterministic programming of MIPsec guarantees high utilization of the hardware. Also, both handshake and contention issues are solved in the scheme, such that performance can be scaled up. Specifically, the 6.23-million-gate MIPsec achieves 10-Gb/s wire speed for each routing direction. The proposed MIPsec is suitable for transport mode or other crypto mix as well.

Auteurs: Wang, M.-Y.;Wu, C.-W.;

Apparue dans: IEEE Transactions on Very Large Scale Integration Systems

Résumé: The authors have proposed Flexible, Reliable and Intelligent ENergy Delivery System (FRIENDS) as a future power distribution system. In the FRIENDS, new facilities called quality control centers (QCCs), which consist of power electronics devices, distributed generators (DGs), energy storage systems (ESSs), etc., are installed between distribution substations and customers. By controlling and operating those devices in QCCs adequately, various functions can be realized. Particularly, when a power supply from the transmission network is interrupted, isolated local networks which consist of some QCCs are composed in order to realize uninterruptible power supply. In the isolated local network, the DG and ESS in QCCs are employed as backup generators. This paper proposes a novel distributed and autonomous method for balancing the supply and demand during isolated operation. This paper also investigates the effectiveness of the proposed method through some computational simulations using PSCAD/EMTDC.

Résumé: This letter presents a simple criterion for reviewing balanced three-phase fault and unbalanced ground-fault current using the ratio of zero sequence impedance to positive sequence impedance as seen from the fault location, which can be employed to enhance the power system design and protection. The method has been verified by real power systems in Taiwan with satisfactory results.

Résumé:Quite a few MEMS devices need vacuum packaging technology to guarantee the desirable performance. Developing an absolute vacuum environment for those devices is indispensable. However, it is difficult to monitor the pressure change in vacuum chamber in on-line and real-time mode. A surface micro-machined Pirani gauge for measuring vacuum pressure inside vacuum packaging in wafer level was presented in this paper. It was designed with a simplified structure and did not need complex circuit. Only a simple Wheatstone bridge circuit is needed, which could be manufactured by conventional CMOS processes. Preliminary tests on this device were conducted. The experimental results...

Résumé:A micromachined pressure sensor based on an array of microswitches is presented. The pressure sensor consists of a silicon substrate that has a thin metal-deposited diaphragm and indium tin oxide (ITO)-based switch arrays patterned on a Pyrex glass. When pressure is applied to the thin diaphragm through a small tube, the diaphragm starts to deform and contact the array of switches at a certain pressure level. The increase in the contact area due to the diaphragm deformation causes the change in electrical resistance between two terminals of the ITO resistor. The change in resistance that corresponds to electrical output in the pressure sensor is measured by the use of a simple circuit. We also describe the results of numerical simulations that are carried out to find a suitable range of the pressure. The simulation results are in good agreement with the experimental results.

Résumé: A novel millimeter-wave 35-GHz bandpass filter using coplanar waveguide structure is fabricated in a 0.18- standard complimentary metal oxide semiconductor process. The conductor-backed half-wavelength resonators are utilized to realize stopband characteristics at desired frequencies. A series resonant circuit can generate one transmission zero located at 58 GHz. It is also observed that the parasitic effect can create another transmission zero at 80 GHz. Furthermore, the transmission zero at 66 GHz is designed with the use of a shorter conductor-backed resonator. The selectivity of the proposed filter is much improved. Without including the dummy metal, the chip size of the proposed filter is . The good agreement between simulation and measurement is obtained.

Résumé: This paper presents a real-time piano synthesizer where both the transverse and longitudinal motion of the string is modeled by modal synthesis, resulting in a coherent and highly parallel model structure. The paper applies recent developments in piano modeling and focuses on the issues related to practical implementation (e.g., numerical stability, aliasing, and efficiency). A strong emphasis is given to modeling nonlinear string vibrations, and a new variation of earlier synthesis techniques is proposed which is particularly well suited for modal synthesis. For soundboard modeling, the possibilities of using fast Fourier transform-based fast convolution and parallel second-order filters are discussed. Additionally, the paper describes the details of the software implementation and discusses the computational complexity of each model block. The piano model runs on current computer hardware with full polyphony in real time.

Résumé:The evolution of mobile computing devices and wireless networks has created a new mobile computing environment. Users equipped with a mobile host can access, retrieve, and process information while in mobility. Laptops become more powerful data processing elements. Traditional transaction model has moved forwarding to mobile transaction. This paper proposed the model with the aims at solving the stated issues. A key requirement in such an environment is to support frequent disconnection of mobile database. We present a model that implements this framework in an asynchronous and synchronous system.