ANALOG RAILS BASIC

Complete OA Analog IC platform. Better than VXL. Far less cost.

SYNCHRONIZED, CORRECT

BY CONSTRUCTION™

Built on OA from scratch without legacy code, Analog Rails Basic uses the same database as Virtuoso. Never have a DRC nor LVS violation. Crossprobing and backannotation at all times. Infinite supply of multithreaded co-simulation licenses.

OA native database. Plays with Virtuoso

Built-in abutable backannotating Pcells

Graphical pcell generator

Built-in stdcells with behavioral views

Over 100 behavioral symbols

Infinite AMS and HB simulator licenses

Multithreaded transistor simulator

Cosimulates with digital behavioral

Synchronized schematic, layout, wave

DRC/LVS correct by construction

Crossprobes at all times

Highly accurate parasitic extraction

Built in analog and RF measurements

Backannotate waveform's transient point

Corners built in

Infinite number of simulator licenses

Cosimulation and multithreaded, users can run millions of fets alongside both digital and analog behavioral simulations on a single engine simulator. No need to klunk away with an analog and digital simulator on a backplane, our XMS simulator/environment is way superior to AMS Designer. Included is Harmonic Balance and built-in RF measurements, such as transient noise. Never again pay for a simulator, XMS is the best simulator in the business. Works with BSIM3, BSIM4, BSIM6, etc. Users can also optionally simulate with 3rd party Hspice compatible simulators just in case they want to double verify. The netlister is customizable. Hundreds of behavioral models, both analog and digital are also included.

Measurements and analysis components in the schematic

Place settling time, overshoot, bandwidth, phase margin, risetime, and etc. components into the schematic, along with multiple analysis components (ac, dc, tran, pss, etc). Corner setups are included in the analysis components.

Sensitivity Analysis

All measurements receive the variation and the largest culprits, both the devices and their parameters, causing the variation.

Manual DRC/LVS correct by construction™ layout

Much more powerful than DRC and LVS, the users cannot make a DRC or LVS violation. Primitives (fets, caps, resistors, bipolars, and differential structures) are generated automatically based on the technology file. No CAD scripts required. Structures snap/repel/permute based on schematic connectivity. Collision avoidance on wiring. Once again, it is impossible for users to make violations.

Never lose crossprobing

Even when flattening the layout, Analog Rails continues to crossprobe the schematic and layout. The circuit designer can always follow the signal...even in 3D!

Simulate layout parasitics at all times

Why wait months to get layout parasitics, such as STI Stress Effects, length of diffusion, and well proximity? DC Currents can be off by 20% without knowing these layout generated values. Now setting reltol has more meaning.

Synthesis with a press of a button

Users can automatically generate the gate level netlist and schematic based on their RTL code with a simple graphical interface in the same design environment as Analog Rails. It's so easy, an analog circuit designer can do it.

Digital Place and Route

Digital Rails makes digital place and route trivial to run due to built in logic cells, synthesis, timing characterization, RCx, static timing tools, clock trees, and automatic flight line based pin generators. The Digital Rails place and route tool automatically runs timing feedback loops and adjusts the layout, allowing users to click onto the PNR button and not require any manual intervention in order to come up with the fastest clock frequencies possible for the given RTL code being processed. The parasitics will always be backannotated into the schematic. The resuting block will instantiate perfectly onto the analog grid system for use at the higher level of the design.

Huge built-in logic library

A vast set of process independent parameterized (w_pmos, w_nmos, L) digital library topologies ships with Analog Rails. Standard cell layouts will be automatically generated. We don't need your digital layouts. Works in both the analog editor and digital P&R. The substrate (sub) terminal is isolated from the vssd terminal, where the users can optionally tie the substrate to the digital ground or isolate the supply from touching the main substrate. All logic cells contain behavioral views for XMS and SystemVerilog. Rise/fall times based on Cload, W, L, Cx.

Automatic Cell Characterization

Characterization is automatically done in Digital Rails. Upon PDK creation, merely define the corners, the slope steps, and the capacitor loads. The liberty formats will be automatically generated and will be used by our built-in static timing tool.

System Verilog Included

An infinite number of System Verilog simulator licenses are included in Digital Rails. The built-in logic cells contain Verilog views that allow users to run system simulations easily. Just add the top level stimulus.

Behavioral views included

All logic cells contain both analog and digital behavioral views for XMS and SystemVerilog. The output slopes are a function of the supply, widths, lengths, and capacitive loads. This is especially important after post layout (RCx) extraction. The full chip simulation can be run with the included digital and mixed signal simulators.

ANALOG RAILS PREMIUM

Basic + Digital + Automatic Analog. A disruptive IC design platform

REDUCE DESIGN TIME BY 50x WITH AUTOMATION

Reduce the former “full custom” IC design cycle from months down to hours. The Analog Rails mixed signal platform is built around the automation tools. With the ability to go bottom to top to bottom to top quickly, do not fear last minute changes...embrace them.

Automatic migration tool

Optimizer runs dc, ac, tran over corners

Automatic differential structures

Automatic electrically aware router

Differential route with shields

Differential aware density filler

Automatic power supply mesh

Automatic compactor

Delete autoroutes, update, re-autoroute

EM diagnostics. See EM% on the layout

Click onto 2 points. Get IR drop

Cx and RCx wiring extraction

Includes Basic and Digital Rails

Sensitivity pinpoints measurement's culprit

Monte Carlo runs on infinite licenses

Optimization made easy

Place your measurements and analysis components in our OA based schematic, choose properties (including transistor operating regions) to optimize, go to lunch. Return to see the final circuit sized according to spec over all corners. Runs AC, DC, and transients at the same time on multiple machines.

Automatic analog routing

Our best feature. Low capacitive routes. Our multi-block and Transistor-level router also handles differential signals, with wire extensions and shields. We route 100% of the signals and ensure they are DRC correct. Routes are EM friendly. Also includes a power supply mesh. Well taps are automatically generated. Preroutes optional.

Automatic analog placement and differential structures

Set automatch on, press the "P" button, and enjoy the show. We know analog, and you can expect to see common centroid structures with guard rings, multiple dummies, and extended wells to reduce the STI stress and well proximity effects. Don't trust our layouts? Our name begins with "analog"

Advanced Layout Diagnostics

Cx backannotated into the schematic, RCx, selected net RCx, EM, IR drop, resistance between 2 points in the layout...we do it all!

Differential aware density fill

Because of our focus on differential signals, we provide density fill that is aware of your sensitive routes and differential structures/wires.