Can you remove the 100nf cap off the NCP301 and test again ? Looking for pin # 1 to be LOW before and during the 1v0 rail ramp up. After the 1v0 rail reaches the NCP301 threshold, then pin # 1 will float via the PU to 3v3.

If you wish to incorporate a pushbutton reset into this design, there are better suited parts that will then remove the mechanical bounce of the PB from the equation. Consider to use a reset supervisor which offers an internal delay after the voltage rail threshold is reached + can usually support a mechanical PB as well. The delay after the voltage rails are confirmed to be stable are in your favor. Start with removing the 100nf cap -> what is the result ? If still no go, keep the pushbutton pressed during power up -> wait a second or more -> release the PB -> what is the result ?

I am investigatin exactly about this matter since this afternoon.discovered that NCP301 isn't working properly.Why? ... I don't know. Sometimes something very strange comes.And this is the case.

And worse, if I press the PB the NCP301 releases a pulse only and doesn't stay in conduction till I release the PB.And this is not as per the datasheet.

I am happy that you pointed out the same thing because I am still studying the NCP301 saying "this On Semi is not the right schematic, the IC doesn't work in this way, why On Semi releases wrong information ... in the middle of a tunnel ... "So I have to solve another mystery, what the IC is the "NCP301"; I had this doubt yesterday ... but on the case of the IC the suffix is SFF ... like the right NCP301 ... so no way to discover.

About the suggestion for the RST circuit mine doesn't use really the PB. Only left thereto have the opportunity to use in the debug.In the final board will disappear. For this the debounce wasn't kept in mind and it is so basic.

Thank you for the suggestion. Now seems clear the RST circuit doesn't work properly.There is something reasonable to investigate about.

Remove the 100nf cap that is shown in your NCP301 schematic (between pins 2 & 3). Does the NCP301 work ok without this 100nf capacitor ? This cap should not be present from what we see in the datasheet.

believe me or not believe me I have in hands another board with the RST an Power schematic I posted.Exactly the same, with the 100nF debouce cap in that "wrong" position.And it starts up, I can flash, and everything is OK.Unfortunately for me that board was made by an external consultant of the company where I work.

I have ordered all the chips ex/novo.I will receive immediately after Eastern.

And I will populate again the existing board.

On the other hands I have updated the board and I abandon the NCP301 towards the ADM1085.xCORE200 is the schematic I was inspired to. With the ADM1085 I have more flexibility, changing the 15p cap I can manage the length of the RST.New boards will be available within the end of the month.

... even if the power on sequence and RST on my implementation defers only in the RST signal:1) in the xCORE200 the RST is kept low till 3V3 and 1V0 are stable .2) in my board RST goes up when 3V3 is stable, and then there is a pulse Low after 1V0 is stable.

The 3V3 > 1V0 sequence is the same.

I don't think my RST is the cause of the trouble even because I have a working board with my implementation and it works well.

... damaged the XMOS ... this is realistic event.I have double checked almost everything.