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An isolated epitaxial modulation device comprises a substrate; a barrier
structure formed on the substrate; an isolated epitaxial region formed
above the substrate and electrically isolated from the substrate by the
barrier structure; a semiconductor device, the semiconductor device
located in the isolated epitaxial region; and a modulation network formed
on the substrate and electrically coupled to the semiconductor device.
The device also comprises a bond pad and a ground pad. The isolated
epitaxial region is electrically coupled to at least one of the bond pad
and the ground pad. The semiconductor device and the epitaxial modulation
network are configured to modulate an input voltage.

1. An isolated epitaxial modulation device comprising: a substrate; a
barrier structure formed on the substrate; an isolated epitaxial region
formed above the substrate and electrically isolated from the substrate
by the barrier structure; a semiconductor device, the semiconductor
device located in the isolated epitaxial region; a modulation network
formed on the substrate and electrically coupled to the semiconductor
device; a bond pad; and a ground pad; wherein the isolated epitaxial
region is electrically coupled to at least one of the bond pad and the
ground pad; and wherein the semiconductor device and the epitaxial
modulation network are configured to modulate an input voltage.

4. The isolated epitaxial modulation device of claim 1 wherein the
semiconductor device comprises: a plurality of parallel transistors
configured to shunt electrostatic discharge (ESD) current, each
transistor having a gate, a drain region, and a source region; wherein
the isolated epitaxial modulation device further comprises: a conductive
body ring located in the isolated epitaxial region and surrounding the
plurality of fingers, the conductive body ring having one or more body
ties, wherein each body tie is located between adjacent source regions of
the plurality of fingers; and a ground ring surrounding and coupled to
the body ring.

5. The isolated epitaxial modulation device of claim 4, wherein the
ground ring and the ground pad are coupled to the same ground potential.

6. The isolated epitaxial modulation device of claim 1, wherein the bond
pad is implemented as one of an input pad, an output pad, an input/output
(I/O) pad, or a power pad.

7. The isolated epitaxial modulation device of claim 1, wherein the
semiconductor device is implemented in one of a complementary metal oxide
semiconductor (CMOS) technology, a bipolar junction transistor-CMOS
(BiCMOS) technology, a silicon on insulator (SOI) technology, silicon on
diamond (SOD), silicon on sapphire (SOS) or a bipolar-CMOS-DMOS (BCD)
technology.

8. The isolated epitaxial modulation device of claim 1, wherein the
barrier structure comprises: a buried layer; and a well coupled to the
buried layer to enclose the isolated epitaxial region.

10. An integrated circuit comprising: a substrate; processing circuitry
formed on the substrate; a barrier structure formed on the substrate; an
isolated epitaxial region formed above the substrate and electrically
isolated from the substrate by the barrier structure; a semiconductor
device, the semiconductor device located in the isolated epitaxial
region; a modulation network formed on the substrate and electrically
coupled to the semiconductor device; and a signal pad electrically
coupled to the isolated epitaxial region; wherein the semiconductor
device and the epitaxial modulation network are configured to protect the
processing circuitry from current spikes.

11. The integrated circuit of claim 10, wherein the semiconductor device
includes a multi-finger n-channel metal oxide semiconductor (NMOS), each
of the fingers comprising a gate, a drain region and a source region.

12. The integrated circuit of claim 11, further comprising a conductive
structure located in the isolated epitaxial region, the conductive
structure coupled to a ground potential and comprising: a conductive ring
surrounding the semiconductor device; and a plurality of conductive
strips coupled to the conductive ring, each conductive strip located
between adjacent source regions of the plurality of fingers.

13. The integrated circuit of claim 10, wherein the modulation network
comprises a resistor, a capacitor and a transistor.

14. The integrated circuit of claim 10, further comprising a ground pad,
the ground pad electrically coupled to the isolated epitaxial region.

15. The integrated circuit of claim 10, further comprising a power pad,
the power pad electrically coupled to the isolated epitaxial region.

17. A system comprising: processing circuitry; a power converter coupled
to a power source and configured to convert power from the power source
to a power level or a polarity usable by the processing circuitry; and
one or more isolated epitaxial modulation devices configured to modulate
an input voltage, each of the one or more isolated epitaxial modulation
devices coupled to a respective one of the processing circuitry and the
power converter; wherein each of the one or more isolated epitaxial
modulation devices comprises: a substrate; a barrier structure formed on
the substrate; an isolated epitaxial region formed above the substrate
and electrically isolated from the substrate by the barrier structure; a
semiconductor device, the semiconductor device located in the isolated
epitaxial region; a modulation network formed on the substrate and
electrically coupled to the semiconductor device; and a bond pad coupled
to the isolated epitaxial region; wherein the semiconductor device and
the epitaxial modulation network are configured to modulate the input
voltage.

19. The system of claim 17, wherein the modulation network comprises a
transistor coupled between the bond pad and a ground potential.

20. The system of claim 17, wherein the semiconductor device comprises: a
plurality of parallel transistors, each transistor having a gate, a drain
region, and a source region; wherein each of the isolated epitaxial
modulation devices further comprises a conductive structure located in
the isolated epitaxial region, the conductive structure comprising: a
conductive ring surrounding the plurality of parallel transistors; and a
plurality of conductive strips coupled to the conductive ring, each
conductive strip located between adjacent source regions of the plurality
of parallel transistors.

21. The system of claim 17, wherein the one or more isolated epitaxial
modulation devices comprises a first isolated epitaxial modulation device
coupled to the power converter and a second isolated epitaxial modulation
device coupled to the processing circuitry; wherein the bond pad in the
first isolated epitaxial modulation device comprises a power pad and the
bond pad in the second isolated epitaxial modulation device comprises a
signal pad.

22. The system of claim 17, wherein the power source comprises a battery.

23. A method of manufacturing an isolated epitaxial modulation device,
the method comprising: forming a barrier structure on a substrate;
forming an epitaxial region on the barrier structure; forming a
semiconductor device in the isolated epitaxial region; forming a
modulation network on the substrate, the modulation network coupled to
the semiconductor device; forming a bond pad, the bond pad electrically
coupled to the semiconductor device in the isolated epitaxial region.

24. The method of claim 23, wherein forming a bond pad comprises forming
one of a signal pad and a power pad.

25. The method of claim 23, wherein forming a barrier structure
comprises; forming a biased buried layer; and forming a biased well
coupled to the biased buried layer.

26. The method of claim 23, wherein forming a semiconductor device in the
isolated epitaxial region comprises forming a plurality of parallel
transistors.

27. The method of claim 26, the method further comprising: forming a
conductive ring in the isolated epitaxial region, the conductive ring
surrounding the plurality of parallel transistors; and forming a
plurality of conductive strips coupled to the conductive ring, each
conductive strip formed between adjacent source regions of the plurality
of parallel transistors.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is related to the following co-pending U.S. patent
applications, all of which are hereby incorporated herein by reference:

[0004] Understanding that the drawings depict only exemplary embodiments
and are not therefore to be considered limiting in scope, the exemplary
embodiments will be described with additional specificity and detail
through the use of the accompanying drawings, in which:

[0005] FIG. 1 is a block diagram of one embodiment of an isolated
epitaxial modulation device.

[0006] FIG. 2 is a simplified circuit diagram of one embodiment of an
isolated epitaxial modulation device.

[0007] FIG. 3 is a top view of an exemplary isolated epitaxial modulation
device.

[0008] FIG. 4 is a simplified cross section of one embodiment of an
isolated epitaxial modulation device.

[0009] FIG. 5 is a high level block diagram depicting one embodiment of a
system comprising at least one exemplary isolated epitaxial modulation
device.

[0010] FIG. 6 is a flow chart depicting one embodiment of a method of
manufacturing an isolated epitaxial modulation device.

[0011] In accordance with common practice, the various described features
are not drawn to scale but are drawn to emphasize specific features
relevant to the exemplary embodiments.

DETAILED DESCRIPTION

[0012] In the following detailed description, reference is made to the
accompanying drawings that form a part hereof, and in which is shown by
way of illustration specific illustrative embodiments. However, it is to
be understood that other embodiments may be utilized and that logical,
mechanical, and electrical changes may be made. Furthermore, the method
presented in the drawing figures and the specification is not to be
construed as limiting the order in which the individual acts may be
performed. The following detailed description is, therefore, not to be
taken in a limiting sense.

[0013] FIG. 1 is a block diagram of one embodiment of an isolated
epitaxial modulation device 100. The modulation device 100 includes an
isolated epitaxial region 102 coupled to a bond pad 104, an epitaxial
modulation network 106 and ground pad 108. In the exemplary embodiments
described herein, the bond pad 104 is implemented as an input/output
(I/O) pad. However, it is to be understood that the bond pad 104 can be
implemented differently in other embodiments. For example, the bond pad
104 can be implemented as an input pad, output pad, input/output (I/O)
pad, signal pad, test pad, programmable pad, or a power pad (e.g. coupled
to Vdd, Vcc, Vee, Vss, etc).

[0015] The semiconductor device 110 and the epitaxial modulation network
106 together modulate an input voltage. Thus, when the bond pad 104 is
implemented as a signal pad (e.g. input pad, output pad, or input/output
pad) the isolated epitaxial modulation device 100 can be used, for
example, to protect an electrical circuit from voltage transients, or
current spikes, such as electrostatic discharge (ESD) current, and
Electrical overstress (EOS). However, it is to be understood that other
uses for the modulation device 100 are also contemplated. For example,
when the bond pad 104 is implemented as a power pad, the isolated
epitaxial modulation device 100 can be implemented as an ESD power clamp
network (e.g. an ESD network between two power pins)

[0016] Also included in the modulation device 100 is a substrate 122 and a
barrier structure 124. The substrate can be comprised of any suitable
material known to one of skill in the art, such as silicon, quartz or
other materials. The barrier structure 124 electrically isolates the
epitaxial region 102 from the substrate 122. Thus, the electrical
potential of the isolated epitaxial region 102 can be modified
independently of the substrate 122. For example, in some embodiments, the
barrier structure 124 is implemented as a biased buried layer which
separates the region 102 from the substrate 122. However, it is to be
understood that the barrier structure 124 can implemented differently in
other embodiments. For example, in some implementations, the barrier
structure 124 is an oxide insulating material. The sides of the barrier
structure can be silicon metallurgical junction structure, shallow trench
isolation (STI) structure, deep trench (DT) structure, through wafer via
(TWV) structure, or through silicon vias (TSV) structure. The shallow
trench isolation and deep trench (DT) isolation structure can be filled
with an oxide, polyimide, or polysilicon material. In addition, the
substrate 122 and the ground pad 108 are not necessarily coupled to the
same electrical potential. However, in some embodiments, the substrate
122 is coupled to the same electrical potential as the ground pad 108.

[0017] FIG. 2 is a circuit diagram of one embodiment of an isolated
epitaxial modulation device 200. In the embodiment shown in FIG. 2, the
modulation device 200 is implemented as a protection device to shunt ESD
current. The semiconductor device 210 is implemented as an n-channel
metal-oxide semiconductor (NMOS) that is the primary protection device
that shunts ESD current. In particular, in this particular embodiment,
the NMOS is a multi-finger NMOS. That is, the NMOS is comprised of a
plurality of parallel transistors as shown in FIG. 3 and described below.

[0018] In addition, in the embodiment shown in FIG. 2, the epitaxial
modulation network 206 includes a resistance 212 and a capacitance 214
that form a resistor-capacitor (RC) discriminator. The epitaxial
modulation network 206 also includes one or more transistors 216. The one
or more transistors 216 are also implemented as an NMOS in this example.
The capacitance 214 represents the capacitance between I/O pad 204 and
the gate node of semiconductor device 210 and transistor 216. The
resistance 212 represents the resistance from the gate of the
semiconductor device 210 and transistor 216 to ground (GND) 208. The
resistor element can be a silicon resistor, metal resistor, or
polysilicon resistor. The capacitor element can be a silicon
metallurgical junction, metal-insulator-metal (MIM) capacitor, MOS
capacitor, vertical parallel plate (VPP) capacitor, or a vertical natural
plate capacitor (VNP).

[0019] The isolated epitaxial region 202 is electrically separated from
the substrate 222 by the barrier structure 224. The isolated epitaxial
region 102 also includes a body ring 218 which is depicted in FIG. 2 as a
node. However, the body ring 218 surrounds the semiconductor device 210
as described in more detail below. The body ring 218 also includes ties
located between fingers of the semiconductor device 210 having adjacent
source regions, as described in more detail below. The effective
resistance between the body ring 218 and a P+ ring 220 is labeled as Rb
in FIG. 2.

[0020] At the onset of an ESD event, the gate potential of the NMOS
semiconductor device 210 and the gate potential of transistor 216 rise
due to the resistance/capacitance (RC) coupling between I/O pad 204 and
GND pad 208. The current conducted by transistor 216 flows through Rb and
drives up the potential of the body ring 218. The source of NMOS
semiconductor device 210 is tied to GND pad 208 so the body to source
junction is forward biased. As a result, the fingers of NMOS
semiconductor device 210 are triggered at a relatively lower voltage. In
other words, the fingers of NMOS semiconductor device 210 are turned on
or begin to shunt current at a relatively lower voltage. The forward bias
of the source body junction of NMOS semiconductor device 210 also helps
promote uniform turn on of the NMOS fingers. The body potential of NMOS
semiconductor device 210 is controlled by the body ring 218 surrounding
NMOS semiconductor device 210. Once the fingers are turned on, they begin
to shunt the ESD current to protect other components from the ESD
current. With the rising of the body region, the current drive of the
transistor increases. MOSFET current drive is proportional to the (VG-VT)
where VG is the gate voltage, and VT is the threshold voltage. As the
body rise, the MOSFET body effect is reduced, leading to a lower
threshold voltage. This effect is also referred to as the MOSFET reverse
body effect or dynamic threshold MOSFET effect. As the VT is reduced, the
current drive, Ids, of the transistor increases, leading to an
improvement in the ability to discharge the ESD event.

[0021] FIG. 3 is a simplified cross section of the modulation device 200.
The isolated modulation device 200 includes a P+ substrate 322, an N+
buried layer 324 overlaying the P+ substrate 322 and an isolated
epitaxial region 202 (also labeled and referred to as P-body region)
overlaying the N+ buried layer 324. The modulation device 200 also
includes an N+ well 328 coupled to the N+ buried layer 324 and enclosing
the isolated epitaxial region 202. The N+ buried layer 324 and the N+
well 328 function as the barrier structure in this embodiment to
electrically isolate the isolated epitaxial region 202 from the substrate
222. The buried layer 324 is coupled to the ground pad 208, in some
embodiments, via the well 328 and NTUB 330. In other embodiments, the
buried layer 324 is floated, biased or coupled to a power supply or
reference voltage. In the case that the buried layer 324 and N+ well or
edge 328 are an insulator structure, biasing can occur if the material in
the buried layer 324 is polysilicon. In the case when the buried layer
324 and well 328 are insulators, no bias condition is established when
the material in the buried layer 324 is silicon dioxide, diamond, or
quartz. In some embodiments, the well 328 can abut or extend beyond the
buried layer 324. Well 328 can be deep trench (DT), or through silicon
via (TSV) that extend to the buried layer 324, or extends below the lower
edge of the buried layer 324.

[0022] In this example, dedicated P+ body ties 301 are added between each
pair of adjacent source N+ fingers 303 as discussed above. The P+body
ties 301 and the N+fingers 303 are formed in the isolated epitaxial
region 202. In addition, the N+well 328 is electrically coupled to the
NTUB 330 which is electrically coupled to the bond pad 304 or the ground
pad 308.

[0023] The body ties 301 are separate from source N+fingers 303. Each
finger 303 includes a gate 315, a source region 317, and a drain region
319 tied to a pad (i.e. I/O pad 204). Thus, the body ties 301 are located
between adjacent source regions 317. In this example, the body ties 301
are connected to a body ring 318 using a metallic material. The effective
body resistance between each source edge on gate side and the body ring
318 is approximately equal to the effective body resistance between
another source edge on gate side and the body ring 318. This effective
body resistance is referred to herein and labeled in FIG. 3 as Rf. Thus,
the effective resistance between any source edge on gate side and the GND
P+ ring 320 is Rb+Rf, where Rb is the resistance between the body ring
318 and the GND P+ ring 320. The GND P+ ring 320 can be coupled to the
ground pad 208 in some embodiments. In other embodiments, the GND P+ ring
320 is coupled to a separate ground potential.

[0024] The body resistance is, thus, uniformly distributed across
different fingers 303 within NMOS semiconductor device 210 and within
each individual finger 303. That is, the body resistance is not location
dependent. Furthermore, all of the fingers 303 are triggered
approximately simultaneously and are turned on with an approximately
equal strength due to the uniform distribution of the body resistance.

[0025] In addition, all of the fingers 203 reach a failure threshold at
approximately the same time due to the uniform distribution of the body
resistance. The failure threshold is the point of maximum current that
can be shunted without failing. Hence, the modulation device 200 is able
to achieve a failure threshold approximately equal to a theoretical
maximum failure threshold. The improved failure threshold is due to the
fact that the modulation device 200 is not limited to the lower failure
threshold of a finger 203 that reaches the failure threshold quicker. In
other words, if the body resistance were not distributed uniformly, some
fingers would reach a failure threshold quicker. Thus, the failure
threshold of the modulation device 200 would be limited by the early
failure threshold of one of the fingers 203. However, by distributing the
body resistance approximately uniformly, all of the fingers 203 share the
load approximately evenly and reach the failure threshold at
approximately the same point in time which in turn increases the total
failure threshold of the modulation device 200.

[0026] Furthermore, due to uniform body current flow, the effective body
resistance of MO 202 is reduced, as compared to a modulation device
without uniform body current flow, and the holding voltage, Vsp, is
raised which enables more operation head room. The trigger voltage Vt1
can be separately tuned with Rtrig and Ctrig with minimal to no impact on
Vsp.

[0027] FIG. 4 is a top view of the exemplary isolated epitaxial modulation
device 200. As can be seen in FIG. 4, the body ring 418 includes a
plurality of body ties 401 located between adjacent source regions of
fingers 403. As further shown in FIG. 4, the effective body resistance
between each source edge on gate side and the body ring 418 is
approximately equal to the effective body resistance between another
source edge on gate side and the body ring 418.

[0028] The embodiments of an isolated epitaxial modulation device
described herein can be used in any integrated circuit or device, for
example, to protect the input/output pins from ESD current. For example,
FIG. 5 is a high level block diagram depicting an exemplary system 505
comprising at least one isolated epitaxial modulation device 500. The
system 505 comprises a power converter 509 coupled to a power source 511
and processing circuitry 513.

[0029] In the exemplary embodiment shown in FIG. 5, the power converter
509 incorporates at least one isolated epitaxial modulation device 500-1
as described above. The power converter 509 is coupled to the power
source 511 and is configured to convert the power received from the power
source to a level and polarity usable by the processing circuitry 513.
For example, the power converter 509 can be implemented as a direct
current (DC) to direct current converter to lower or raise the voltage
level of the power received from the power source 511 to a level required
by the processing circuitry 513. Alternatively, the power converter 509
can be implemented as an alternating current (AC) to direct current (DC)
converter.

[0030] Additionally, in some embodiments, the power converter 509 is a
high-current and high-voltage power converter. However, embodiments of
the isolated epitaxial modulation devices described herein can be
implemented in other power devices, high-power density and
high-efficiency DC power converters, and high voltage AC/DC power
converters. For example, the isolated epitaxial modulation device can be
implemented in an off-chip driver.

[0031] In one embodiment, the power source 511 is external to the device
505. For example, the power source 511 can be mains power coupled to the
device 505 via an electrical socket. In other embodiments, the power
source 511 can be internal to the device 505, such as a battery.

[0032] In addition, in this embodiment, the processing circuitry 513 also
includes at least one isolated epitaxial modulation device 500-2 which
protects the input/output pins of circuits in the processing circuitry
513. The processing circuitry 513 and the isolated epitaxial modulation
device 500-2 can be implemented in a single monolithic integrated circuit
or in co-packaged devices containing separate die.

[0033] The device 505 can be implemented as any electronic device, such as
a cell phone, computer, navigation device, microprocessor, a high
frequency device, etc. Hence, the implementation of the processing
circuitry is dependent on the particular device. For example, when device
505 is implemented as a cell phone, the processing circuitry 513 can
include a digital signal processor (DSP), analog-to-digital (ADC)
converters, radio frequency transmission and reception amplifiers, memory
circuits, and a microprocessor, as known to one of skill in the art. The
isolated epitaxial modulation device 500-2 is configured to protect the
processing circuitry 513 from voltage and/or current spikes, such as
electrostatic discharge (ESD) current.

[0034] FIG. 6 is a flow chart depicting an exemplary method of
manufacturing an isolated epitaxial modulation device, such as the
exemplary isolated epitaxial modulation devices described above. At block
602, a barrier structure is formed on a substrate. For example, in some
embodiments, a biased buried layer is formed on the substrate. At block
604, an epitaxial region is formed on the barrier structure using
techniques know to one of skill in the art. The barrier structure
encloses and electrically isolates the epitaxial region from the
substrate.

[0035] At block 606, a modulation network is formed on the substrate. For
example, a resistor, capacitor, and transistor can be formed using
techniques known to one of skill in the art. At block 608, a
semiconductor device, such as the exemplary semiconductor devices having
a plurality of parallel transistors discussed above, is formed in the
isolated epitaxial region using techniques known to one of skill in the
art. The semiconductor device is coupled to the modulation network. In
embodiments implementing a semiconductor device that has a plurality of
parallel transistors, the method 600 optionally includes forming a
conductive ring in the isolated epitaxial region at block 610. The
conductive ring surrounds the plurality of parallel transistors. In such
embodiments, method 600 also optionally includes forming a plurality of
conductive strips coupled to the conductive ring at block 612. Each of
the plurality of conductive strips is formed between adjacent source
regions of the plurality of parallel transistors. At block 614, a bond
pad is formed on the device. The bond pad can be a signal pad or a power
pad. The bond pad is electrically coupled to the semiconductor device in
the isolated epitaxial region.

[0036] Although specific embodiments have been illustrated and described
herein, it will be appreciated by those of ordinary skill in the art that
any arrangement, which is calculated to achieve the same purpose, may be
substituted for the specific embodiments shown. Therefore, it is
manifestly intended that this invention be limited only by the claims and
the equivalents thereof.