Introduction

During debugging or repair phase you will likely use JTAGTest
to watch signals or force pin states in order to test other circuits.
JTAGTest normally shows only pin numbers and their names. Unlike other
boundary scan tools, you can load so-called UCF file and give each pin
net name. This will make debugging much easier and faster as you don't
have to look into schematics for net names.

UCF files are natively used by Xilinx, however you can
create such file for any JTAG device with text editor such as notepad,
or you can use our ULP script for Cadsoft Eagle to export automatically UCF
file from your board (.BRD file).

JTAGTest in action

Boundary scan window with loaded UCF file

What is UCF File

The UCF file is an ASCII file specifying constraints on the logical design. You create this file and enter your constraints in the file with a text editor.
You can also use the Xilinx Constraints Editor to create
constraints within a UCF file.
These constraints affect how the logical design is implemented in
the target device. You can use the file to override constraints
specified during design entry.