Next-generation microvia and global wiring technologies for SOP

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Abstract

As microsystems continue to move toward higher
speed and microminiaturization, the demand for interconnection
density both on the IC and the package levels increases tremendously.
The 2002 ITRS roadmap update identifies the need for
sub-100-µm area array pitch and data rates of 10 Gb/s in the
package or board by the year 2010, requiring much finer lines
and vias than the current microvias of 50 µm diameter and lines
and spaces of 25 µm. After a brief description of the future need
for high-density substrates, the historical evolution of microvia
technologies worldwide is summarized. With the move toward
highly integrated and higher performance system-on-a-package
(SOP) technology, the demand for microvia wiring density in the
package is increasing dramatically requiring new innovations in
fine line, ultralow-loss, and ultrathin-film dielectrics. The low-cost
needs of this technology are driving research in high throughput
and large area processes in dielectric and conductor deposition.
The third section of this paper describes in detail some of the
key emerging global microvia research and development in the
fabrication of microminiaturized, multifunction SOP packages
including rapid curing of low-loss dielectric thin films on organic
substrates, environmentally friendly high-speed electroless copper
plating, ultrafine lines, and spaces down to 5 µm and low-cost
stacked via structures without chemical-mechanical polishing.
This paper concludes with a perspective on future directions
in dielectrics and conductor materials and processes leading to
ultrahigh-density and low-cost microvia technologies for build-up
SOP implementation.