This work focuses on the interconnect infrastructure, functionality, and capability of a heterogeneous reconfigurable SoC. This SoC integrates reconfigurable units of various granularity used as stream-processing elements. A network-on-chip (NoC) approach demonstrates benefits in scalability, flexibility, and runtime adaptivity for actual and future SoC designs. On a reference CMOS090 implementation, the described interconnect system works at the system frequency of 200 MHZ, sustaining the required runtime bandwidth for several application domains.