Simulink Design Verifier

Simulink Design Verifier

Simulink Design Verifier™ uses formal methods to identify hidden design errors in models. It detects blocks in the model that result in integer overflow, dead logic, array access violations, and division by zero. It can formally verify that the design meets functional requirements. For each design error or requirements violation, it generates a simulation test case for debugging.

Design Error Detection

Run-Time and Diagnostic Errors

Before you run simulations, you can detect run-time and modeling errors, including integer overflow, division by zero, array out of bounds, subnormal values, and floating-point errors as well as data validity errors.

Simplification of Variant Models

Use the Variant Reducer to generate a reduced model for a subset of valid configurations.

Simplify Models for Deployment

After you have fully validated your master variants model, use Variant Reducer to generate a reduced model for a subset of valid configurations. All related files and variable dependencies are also reduced. The reduced artifacts are packaged in a separate folder to enable easy deployment and sharing with customers and partners.