DSP
Designer is a revolutionary breakthrough to DSP design using Intusoft's
ICAP/4 tool suite to simulate digital control algorithms and other aspects
of DSP design. Special device models provide a visual means to simulate
transfer functions and equivalent assembly code instructions for programming
DSP digital control. Corresponding waveforms for the design including
Bode plots of hidden parameters within Z-transformations can be viewed.
The product is also valuable for verifying DSP assembly language programming
entered through a development board interface running as a DSP idle process.
For more information on DSP Designer, go to
www.intusoft.com.

Problem
Coding
for real-time signal processing is tedious and error prone. Even when you
seemingly get it "right," errors typically creep in. Clearly there
is a need for computer automation to free the engineer from detailed micro-code
book keeping required by DSP so that better algorithms can be implemented.
Simulation using SPICE partially solves the problem. Substituting a SPICE
delay line for the z transform, z-1, is the usual approach. But as complexity
increases the substitution breaks down, with instabilities above the sampling
frequency that are clearly impossible. Even more troublesome is the increased
complexity when algebraic "feedback" occurs.

Take,
for example, a simple Buck regulator plant model. The output voltage feeds
back to the input, making the current through the inductor proportional
to the difference in output and input voltage.
But the output voltage is proportionate to this difference. The simplest
approximation is to selectively use backward Euler integration to break
this nasty feedback,
though a better solution solves the algebraic equations. At that, the
detailed implementation is so error prone that the designer accepts loss
in performance, just to get the job done. Moreover, most DSP variables
are hidden in the code, so the simulation predictions cannot be validated.

SolutionDSP Designer is a software/firmware suite based on Intusoft's ICAP/4
SPICE toolset. Simulation models have been added that make z-transform
based modeling fast and easy. This starts with a z-delay
to get a more perfect delay model, then adds in a good Analog-to-Digital
converter model,
which replicates quantizing errors in both frequency and time domain.
The continuous conduction mode PWM
model is also employed for the fastestsimulations
ever. Building on the SpiceNet configurable schematic, multiple control
loops are broken and simulated
in seconds to measure the stability parameters, plus gain and phase margins.
The IsSpice4 matrix solution is used to extract the set of difference
equations that describe the DSP
control system. These equations are re-arranged for optimal multiply-accumulate
(MAC) instruction execution. Special plug-ins for different vendors' DSPs
generate C and assembly level code that can be added to a software project.
A unified scaling approach is
documented that shows how to scale the simulation and calculate the correct
DSP coefficients for integer, mixed or fractional scaling.

Example circuits are given for target designs that include a modified
proportional- integral-differential MPID,
design. A novel concept for current feedback the Virtual Current Controlleris also developed. Both of these controllers are implemented
in hardware using Microchip and Texas Instruments test beds.

Simulations are normally
performed for AC, DC and TRAN cases. In order to provide the same capability
in the DSP, Real Time (RT) code
is provided. This links with a serial interface to the DSP to provide
this capability. The most challenging part is the incorporation of a transfer
function analyzer, TFA, inside the DSP. The
TFA uses the single injection modeling
technique inside the ICAP/4 software. IntuScope scripts are used to control
the DSP serial interface, and using the RT code, the automated scripts
make and display the measurement results.

Not all DSPs have a SMPS
power stage. Intusoft provides a schematic of the required circuitry that
needs to be breadboarded for cases where it is not available.

A new data acquisition
plugin has been added to IntuScope so
that lab oscilloscope measurements can be transferred by a serial link
into an IntuScope waveform for viewing.

It's
a well-known fact that traditional programming of assembly instructions
using a DSP development board is very tedious and error prone. Mistakes
in coding are common and often passed through the digital control process
without being detected. Also, hidden variables inside transfer functions
are impossible to analyze. But by simulating the microinstructions
using special device models provided by DSP Designer, the engineer gains
the convenience of a visual approach to the design, is able to view waveforms
of the digital control process, and easily debug this and other aspects
of the design. Once satisfied, the schematic can be used to ascribe
the correct assembly code instructions to be automatically written into
the development board's memory. The automated version of this process
is currently being developed and scheduled for completion in Q1/2009.

If a designer wishes to initially code the DSP manually, he or she can
afterwards use DSP Designer to validate the assembly language by simulating
the code via device models and waveforms. The toolset also simulates other
aspects of DSP such as the power section, filtering and A/D-D/A conversions.

Increased Reliability

Coding
errors are eliminated by visually simulating the DSP's digital-control
algorithms, and viewing corresponding waveforms. "Hidden"
variables normally latent in DSP coding of transfer function analysis
are exposed in DSP Designer, using familiar IsSpice4 AC, OP and TRAN analysis,
using test code in the DSP, and viewing waveforms with automated communication
between the DSP and IntuScope.

Saved Time

A
visual design approach using IsSpice4 simulation saves time and tedious
error-prone programming of assembly instructions. Soon DSP Designer’s
automated programming of the DSP’s CPU from IsSpice4 will save even more
time.

Reduced Parts

Parts
can be reduced by building their function into the digital control process;
for example, using
a DSP plant model
to obtain switched inductor current without sensing current directly.

Improved Time to Market

Turnkey Simulation Tool Suite

DSP
Designer is but part of today's most advanced and easy to use analog,
mixed-signal, and mixed systems simulation toolset, including magnetic
design and synthesis software and test synthesis software in select packages.
Intusoft's scalable ICAP/4 software offerings and Test Designer
are beneficial for any type of design simulation, verification, test and
documentation.

Initial
capability of DSP Designer will be included in the next ICAP/4 and Test
Designer release in December, 2008 for select packages. This will include
an oscilloscope plug-in for firmware importation of lab waveforms
into IntuScope. It will not yet include automated IsSpice4 communication
to the DSP development board's memory to program assembly instructions
through the IDE. DSP Designer will be included in Intusoft's ICAP/4 Windows
Power Deluxe, ICAP/4 Windows Power/RF Deluxe, Power Supply Designer, ICAP/4
Professional and Test Designer products at no additional cost. A new Magnetics
Designer release is also scheduled for December.

What
DSP Development Boards and Lab Equipment does DSP Designer Interface
to?

Intusoft
is examining a custom DSP Development board of their own. This will be
comprised of a Dual Buck/Boost synchronus SMPS with Hi voltage inputs
from 12 to 30 VDC, output from 0 to 30 VDC, with a maximum average power
of 200 watts. If approved, it will be targeted for release in January,
2009.

The
MicroChip dsPICDEM SMPS Buck Development Board was originally used for
Intusoft's DSP Designer work, but it did require a number of modifications.
A new board from MicroChip is used now, but is not yet released to the
public. It is scheduled for a release in January of 2009.

The Texas Instruments/Spectrum
Digital Board 2812eZdsp kit was also used with DSP Designer. However,
there was a piggy-back board that Intusoft attached to it for DSP development.
Intusoft is examining a custom DSP Development board of their own. This
will be comprised of a Dual Buck/Boost synchronus SPMS with Hi voltage
inputs from 12 to 30 VDC, output from 0 to 30 VDC, with a maximum average
power of 200 watts. If approved, it will be targeted for release in January,
2009.

The Tektronix TDS1012B
oscilloscope with USB interface and the Tektronix TPS2014 with RS232 serial
interface will be supported for waveform importation. Other series 1000
and 2000 scopes should work with the communication interface.

sign
up as a reference account for designing a DSP using this revolutionary
product. We're looking for a few accounts to work closely with.Receive
the software for free, or at a reduced upgrade cost if you have less than
a “Power Supply Designer” offering.
Call us at 1-310-952-0657 or,E-mail.

The
serial interface that connects DSP Designer to an oscilloscope uses the
RS232C connection that's included with the MicroChip SMPS Buck evaluation
board. Texas Instruments has a similar interface, but uses a different
protocol. The objective is to have a low overhead background process that
can read and write (peak/poke) into memory. Intusoft's code generator
associates symbol name (node names) to DSP memory locations. With the
DSP turned on and running at steady state, reading the memory values at
these locations and scaling them back into the floating point representation
used by IsSpice4, the IsSpice4 OP (operating point values) are acquired.
If the code was generated using DSP Designer the scale factor is known,
otherwise the user must enter an integer value that DSP uses to represent
"one." The signed integer values will be divided by "one"
to get the IsSpice4 floating point values. These values need a further
conversion by the A/D scale factor to convert the floating-point values
into IsSpice4 node voltages. A DSP button will be added to IntuScope's
"Add Waveforms" dialog to initialize these values. This information
is stored in the registry for each project (SpiceNet drawing name). The
DSP will use the IntuScope "Browse" button to access these values.
IntuScope gets a new capability to look at vector length 1 variables by
loading them into a "plot" data structure that's viewed as a
list in the output window. A script is then made to compare the active
simulation's OP plot values with the DSP OP values.

For
transient analysis the DSP is set up for a step load test. That's part
of the existing code and hardware built into the DSP SMPS evaluation board.
This requires some extra test hardware for a user-designed board. The
hardware can be part of an external test setup, but requires a repetitive
signal to be sent from a DSP digital port to activate the load switching.
The transient vector is built by adding one point per load switching period.
The first point is taken just before the load switch. Subsequent points
are delayed by the PWM sample, Tsample, so that the entire waveform is
collected in (Switch period)/Tsample. For load switching running at 100Hz
(Tswperiod = 10ms), and a computation cycle at 100kHz (Tsample=10us),
the waveform is 1000 points long and takes 10 seconds to acquire. The
DSP background load is small compared to its overall capability. Running
the RS232 at 19,200 Baud allows up to 10 test points to be monitored.

For AC analysis, a
sine-cosine generator is programmed into the DSP firmware. This requires
about 15 instructions or about .5 usec for a 30mip instruction rate. Additionally,
there are:

4 coefficients that
must be set to determine the frequency

4 data words holding
sine, cosine, prevous_sine and previous_cosine

1 data word, TFAtime, to
control the process and

1 data word, Vsig, to
scale the signal level.

The memory word, TFAtime,
is used as a timer register in the DSP. It is initialized to zero. The
DSP doesn't enter the TFA (Transfer Function Analysis) code section until
the TFAtime word is set to 0x1 using the serial interface. When the DSP
sees this condition in the idle loop, it initializes and starts the sine-cosine
generator. The generator will run forever in this state. When TFAtime
>= 0x2, the data accumulation phase starts. Then at the end of each
Tsample interrupt, the sum of Vout*sine and Vout*cosine is accumulated
and TFAtime is incremented. This computation is done after setting the
PWM duty ratio so that it doesn't add to the computational delay; it just
uses some of the "spare" time at the end of the A/D interrupt.
When TFAtime =TFAperiod, the data accumulation stops. When the idle loop
sees TFAtime==TFAperiod, it sets TFAtime=0 and sends the accumulated data
(Vout) back to IntuScope using the RS232 interface. Scope then scales
the data and computes Vin=Vout+Vsig for the TFA frequency that was previously
initialized. Scope proceeds to the next frequency and repeats the process.
This is all done in a new IntuScope script, so when its finished a Bode
Plot will be automatically generated. The user will be required to insert
the Vout test point by adding Vsig=Ksig*sine to the data at Vout and placing
it a Vin, just as it's done in SpiceNet to set up a single voltage injection
GFT. But it is not necessary to measure Vin because it can be computed
using IntuScope as Vout+Vsig. For the default using DSP Designer as the
code generator, Vout will be the computed PWM duty ratio before limiting,
and Vin will be presented to the PWM limiter.

There are a few fine
points that must be understood when programming the TFA.
First, (TFAperiod-2)*Tsample must contain an integer number of test frequency
periods. That will cause the test signal to begin and end at the same
time. That condition is computed in the TFA script, causing the actual
test frequency to be slightly altered from its desired value. Restricting
the exact TFA frequency to meet this condition eliminates artifacts from
the Fourier coefficients commonly done using windowing in DFT (Discrete
Fourier Transform) analysis.

Second, it's necessary
to let the transient residues settle out after changing the frequency.
The default is to use 50ms for settling, and 50ms for data accumulation.

Third, Vsig must be
small enough to prevent Duty Ratio limiting. If Vsig is made constant
for the entire frequency sweep, it may be too small to get accurate data
at lower frequencies. Good control system design has a loop gain that
decreases 6dB per octave, so that the Vin signal strength can be estimated
for the "best" deadbeat controller. The following calculations
show how to make the duty ratio signal constant at about .1 p-p for this
case:

First, sine is scaled
2.14 and the controller is scaled 8.8 so the sine needs to be scaled 2^8/2^14
= 2^-6

Design
and analysis of control system are usually performed in the frequency
domain, whereby the time domain process of convolution is replaced by
a simple multiplication in frequency domain. In DSP design sampled data
systems use a similar concept using a unit delay as the basic building
block. The s-plane mapping into discrete z-plane is achieved by:

=

where
in general represents a unit delay of nT
seconds. S-domain transfer functions are then transformed into ratios
of polynomials

=

The
equation can be re-arranged to solve for Vout and is implemented using
the direct programming method as shown in the following block diagram
with the unit time delay (UTD) implemented using a IsSpice4 transmission
line. This implementation allows for IsSpice4 analysis of the time domain
difference equations, including both transient and ac analysis, and of
course Bode plots.

A
new model, Zdelay, has been developed, which has superior convergence
and memory usage performance over the traditional UTD transmission line
IsSpice4 model. This new model is implemented with Intusoft's Code Model
SDK tool. The model is highly customizable with several user specified
parameters. These parameters include start up delay, sampling time, propagation
time, initial condition, and high and low output limits. For DSP and general
sample and hold applications, Zdelay becomes the model of choice due to
its customizability and superior performance over transmission line based
models.

As
an example, consider the following sine-cosine waveform generator in Figure
1, which is implemented with the new Zdelay model. Note that the initial
conditions are necessary to kick-start the circuit. This is easily achieved
by specifying the necessary initial condition (IC) values on the delay
models.

Consider
a Buck regulator operating in Continuous Conduction Mode(CCM) with common
input and output grounds as shown below in Figure 3. Note that the schematic
is shown with UTD models, which are eventually replaced by Zdelay models
described earlier. IsSpice4 is capable of modeling continuous time functions
by using a variable time step. That capability will be used to make a
continuous time analog model. The continuous time model is then transformed
to a z-domain based model by the zero order hold. The z-domain equations
are then re-arranged into the familiar Infinite Impulse Response (IIR)
DSP equations.

IsSpice4 constructs a matrix to solve these simultaneous equations. Since
these equations are linear there is no need to reformulate the matrix
for each step. Using IsSpice4 to solve these equations also eliminates
the delays that are usually inserted to break feedback paths. The matrix
order is also conditioned to provide the best results for a finite word
length system.

Coding a DSP manually is extremely error prone, even passing through errors
that appear to work. The design complexity level makes the decision to
use DSPs in new designs very difficult. The engineering effort is higher
than for a comparable analog design. However by formulating the DSP design
in such a way to be solved by IsSpice4 (i.e., using special schematic
models, simulation waveform views, etc., as found in DSP Designer), the
programming of a DSP is made much easier, automated, and with increased
design quality.

The actual solution in IsSpice4 is calculated by LU decomposition. But
the right hand side, RHS, of the matrix is zero for the non-trivial part
of the matrix, which results in constant coefficients for the final backward
substitution. The matrix solution is obtained by a properly sequenced
series of multiply-accumulate (MAC) instructions, in which matrix coefficients
are stored in a constant array, and state variables are accessed in the
order corresponding to their associated coefficients. MAC instructions
vary for different DSPs so the code generator algorithm is tailored to
the target DSP.