This patch adds SDHCI_QUIRK_FSL quirk. The quirk is used to instructthe sdhci driver about various FSL eSDHC host incompatibilities:

1) FSL eSDHC controllers can support maximum block size up to 4096 bytes. The MBL (Maximum Block Length) field in the capabilities register extended by one bit.

(Should we implement a dedicated quirk for this? I.e. SDHCI_QUIRK_MAX_BLK_SZ_4096?)

2) sdhci_init() is needed after error conditions.

(Can we safely do this for all controllers?)

3) Small udelay is needed to make eSDHC work in PIO mode. Without the delay reading causes endless interrupt storm, and writing corrupts data. The first guess would be that we must wait for some bit in some register, but I didn't find any reliable bits that changes before and after the delay. Though, more investigation on this is in my todo list.