Datasheets

SY10E167SY100E167 SY10E167SY100E167 6-BIT 2:1 MUX-REGISTER SYNERGY SEMICONDUCTOR FEATURES The SY10/100E167 offer six 2:1 multiplexers followedby D flip-flops with single-ended outputs, designed for usein new, high-performance ECL systems. The Select (SEL)control allows one of the two data inputs to the multiplexerto pass through. The two external clock signals (CLK1,CLK2) are gated through a logical OR operation before useas control for the six flip-flops. The selected data aretransferred to the flip-flops on the rising edge of CLK1 orCLK2 (or both).The multiplexer operation is controlled by the Select(SEL) signal which selects one of the two bits of input dataat each mux to be passed through.When a logic HIGH is applied to the Master Reset (MR)signal, it operates asychronously to take all outputs Q to alogic LOW. BLOCK DIAGRAM MUXD0b Q D SEL Q0 D5a D0a PIN CONFIGURATIOND3bD3aNCVCCO в– в– …