Future Architectures for CMOS Image Sensors

December 12, 2016 – Twenty sixteen was yet another outstanding year to be a participant and spectator in the CMOS image sensor (CIS) marketplace – with significant advancements in devices and architectures. Viability of stacked CIS in high-volume applications has been proven, and is expected to dominate CIS advances for the next 3-5 years.

Stacking delivers a smaller footprint for the CIS and processor combo and overall lower power consumption due to more efficient partitioning of processing functions between the two die. A smaller footprint has advantages in many markets, and is absolutely critical in applications such as endoscopy. In addition, the CIS die can be fabricated in a simplified process that’s optimized solely around the pixel performance and yield, resulting in significantly lower noise, defect densities, and non-uniformities. An ultimate goal is to create more advanced pixels by local high density interconnects. This allows the pixel to be split between the upper and lower die – for example, to allow global shutter pixels with excellent parasitic light (in)sensitivity.