- external accelerometer configured to generate an interrupt @2khz each new data ready (interrupt data ready pin is configured as wakeup source). Accelerometer data ready interrupt is enabled after 5 seconds that program is running

- low power timer (LPTMR) configured as wakeup source @1khz. Within LPTMR interrupt, a counter is incremented. When the timer reachs 1000 (1 second elapsed), a flag is set in order to signal that the watchdog should be cleared

- two led used as debug

- MCU used in stop mode (LLS) after the initial configuration

Problem:

- as soon as the accelerometer data ready interrupt is enabled, watchdog resets the MCU

Using an oscilloscope to check the toggle of LED1 (which is done before the clear of the WD), the reset occurs before the timeout period elapses (resets at ~750ms), as you can see from this image (channel 2 is the LED1, channel 1 is the acceleromeer interrupt data ready pin at 2khz).

The strange thing is that If I change the data ready interrupt frequency of the acceloremeter from 2khz to 250hz, the program is working correctly w/o resetting, as you can see from the next image.

It seems that the MCU doesn't like waking up from LLS too fast (is really 2khz too fast, compared with the core clock running at 96mhz?) when the WD is enabled.

So, till the 2khz interrupt is not enabled, all is working fine (rtc diffs log and 'before' values are always ~1000ms).

As soon as the interrupt generation is enabled (after 5 seconds), the board resets due to the internal watchdog. As you can see, 19785 32khz ticks (~603ms) are elapsed since the last watchdog refresh, but the watchdog timer (isrWd) says 1201ms (0x4b1), even if log[4] -> after was 0 (meaning the watchdog was refreshed correctly).

I'm a bit worried about this problem: watchdog is very important in our application, and we must use LLS power mode.

I did some other tests, and the output of the 'datalogger' is very alarming.

I changed the interrupt frequency from 2khz to 125hz (enabled after 5 seconds). Program is not resetting, but here's the output:

log[0] -> { rtc = 0x80FF, before = 0x3DC, after = 0x0}

log[1] -> { rtc = 0x1020D, before = 0x3E5, after = 0x0}

log[2] -> { rtc = 0x1831A, before = 0x3E5, after = 0x0}

log[3] -> { rtc = 0x20429, before = 0x3E5, after = 0x0}

log[4] -> { rtc = 0x28535, before = 0x3E5, after = 0x0}

--- interrupt enabled @ 125hz ---

log[5] -> { rtc = 0x3063F, before = 0x464, after = 0x0}

log[6] -> { rtc = 0x38749, before = 0x465, after = 0x0}

log[7] -> { rtc = 0x40854, before = 0x464, after = 0x0}

log[8] -> { rtc = 0x48961, before = 0x461, after = 0x0}

log[9] -> { rtc = 0x50A71, before = 0x462, after = 0x0}

As you can see, rtc time diffs between log(n+1) and log(n) are ok (~1000ms), but WDOG counter ('before' values) are not 'synced', reporting that ~1124ms elapsed since last refresh. It seems that waking up from LLS mode, WDOG counter increments faster than it's source clock (LPO).

Scenario1, LPTMR wakeup @1khz and interrupt frequency @125hz. Prior to refresh the watchdog, system is waking up from LLS 1000times because of the LPTMR (1ms period) and 125 times because of the interrupt (8ms period). 'before' values are 1124ms.

--- interrupt enabled @ 125hz ---

log[5] -> { rtc = 0x3063F, before = 0x464, after = 0x0}

log[6] -> { rtc = 0x38749, before = 0x465, after = 0x0}

log[7] -> { rtc = 0x40854, before = 0x464, after = 0x0}

log[8] -> { rtc = 0x48961, before = 0x461, after = 0x0}

log[9] -> { rtc = 0x50A71, before = 0x462, after = 0x0}

Scenario2, LPTMR wakeup @20hz, and interrupt disabled. Prior to refresh the watchdog, system is waking up from LLS 20times because of the LPTMR (50ms period) and 0 times because of the interrupt. 'before' values are 20ms.

log[0] -> { rtc = 0x07A78, before = 0x1B, after = 0x0}

log[1] -> { rtc = 0x0FB4F, before = 0x14, after = 0x0}

log[2] -> { rtc = 0x17C28, before = 0x14, after = 0x0}

log[3] -> { rtc = 0x1FD00, before = 0x14, after = 0x0}

log[4] -> { rtc = 0x22DD8, before = 0x14, after = 0x0}

Scenario3, LPTMR wakeup @20hz and interrupt frequency @125hz. Prior to refresh the watchdog, system is waking up from LLS 20times because of the LPTMR (1ms period) and 125 times because of the interrupt (8 period). 'before' values are 20ms with interrupt disabled, and ~145ms with interrupt enabled.

log[0] -> { rtc = 0x20353, before = 0x1C, after = 0x0}

log[1] -> { rtc = 0x28423, before = 0x14, after = 0x0}

log[2] -> { rtc = 0x3052F, before = 0x14, after = 0x0}

log[3] -> { rtc = 0x3863B, before = 0x14, after = 0x0}

log[4] -> { rtc = 0x40747, before = 0x14, after = 0x0}

--- interrupt enabled @ 125hz ---

log[5] -> { rtc = 0x0003052F, before = 0x99, after = 0x0}

log[6] -> { rtc = 0x0003863B, before = 0x98, after = 0x0}

log[7] -> { rtc = 0x00040747, before = 0x96, after = 0x0}

log[8] -> { rtc = 0x00048854, before = 0x9A, after = 0x0}

log[9] -> { rtc = 0x00050961, before = 0x98, after = 0x0}

From what I'm seeing, it's like that WDOG counter is not incrementing while the CPU is in LLS, but it increments of 1 unit each wakeup from LLS.