"3D-IC Supply Chain Readiness" Forum at SEMICON Taiwan 2012

"3D-IC
Supply Chain Readiness" Forum at
SEMICON Taiwan 2012

European 3D TSV Summit“On
the Road towards TSV Manufacturing”

Join us in
Grenoble on January 22-23 as we
discuss the critical issues as device designers and manufacturers increasingly
cross into the third dimension — due to the industry’s pursuit of building more
functionality into shrinking silicon “real estate.”

This year's 3D-IC
forum at SEMICON Taiwan was entitled “3D-IC Supply Chain Readiness.” With most
industry leaders who are currently involved in 3D development believing that
the realization of 3D-IC technology into high-volume manufacturing is not a
question of “if” but rather only a question of “when,” this year's forum was
focused on industrial readiness and infrastructure maturity. Representatives
from manufacturing supply chains, ranging from EDA to foundry/OSAT, shared
their views through presentations and an open panel.

Kurt Huang of UMC gave a
presentation entitled “Foundry TSV Enablement For 2.5D/3D Chip Stacking” —
making it clear that they will be ready to compete with TSMC in the foundry
interposer and 3D stacking business.

UMC envisions several work flow models (shown below) and concludes that each
OSAT/foundry will have their own capabilities and preferences.

Various Work Models

Source: UMC

UMC indicates that their foundry design rules for interposer fabrication are
ready to go, with product level packaging & testing and reliability
assessment scheduled for completion in 4Q 2012.

Foundry
TSV Design Collaterals

Source: UMC

Typical 3D TSVs are 6 x 50 and for interposer are 10 x 100μm. KOZ have been
determined to be 5μm for 28nm HKMG core device with TSV pitch: JESD229 50/40μm.

Amkor

Min Yoo of Amkor Taiwan gave a
presentation entitled “3D IC Technology: The OSAT Perspective.” Amkor sees: (1)
partitioning logic blocks into higher-yielding sub-blocks as is being done by
Xilinx and others in the FPGA arena -- this results in lower cost 28nm products
as well as chips that are less sensitive to 28nm processing issues; and (2)
repartitioning SoC devices into separate functions which allows for using the
latest node (i.e. 28nm) only where it is required. The latter has been
discussed previously by Bryan Black of AMD [see IFTLE 80, “GIT@GIT”].

Source: Amkor

Also of interest is the Amkor roadmap showing Application processors + DDR for
smartphones and tablets being scheduled for 2014.

Source: Amkor

Amkor, as expected, is in favor of a supply chain where the TSV are fabricated
by the fab/foundry and then shipped to the OSAT for subsequent processing.

They highlight the fact that they are involved with the current Xilinx FPGA
product. Their copper pillar μbump technology is commercial at 40μm,
demonstrated at 30μm, and in development at 20μm.

Source: Amkor

For all the latest in
3D-IC and advanced packaging stay linked to IFTLE.

This article was originally published
in Solid State Technology. Part 2 of Dr. Garrou’s SEMICON Taiwan coverage
will be on www.electroiq.com soon.

European 3D TSV Summit“On the Road towards TSV Manufacturing”

Join us in
Grenoble on January 22-23 as we
discuss the critical issues as device designers and manufacturers increasingly
cross into the third dimension — due to the industry’s pursuit of building more
functionality into shrinking silicon “real estate.”