Group III-V compound (e.g., InP)

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20140339680

III-V Device and Method for Manufacturing Thereof - The disclosure relates to a method for manufacturing a III-V device and the III-V device obtained therefrom. The method comprises providing a semiconductor substrate including at least a recess area and forming a buffer layer overlying the semiconductor substrate in the recess area. The buffer layer includes a binary III-V compound formed at a first growth temperature by selective epitaxial growth from a group III precursor and a group V precursor in the presence of a carrier gas. The first growth temperature is equal or slightly higher than a cracking temperature of each of the group III precursor and of the group V precursor.

NITRIDE SEMICONDUCTOR SUBSTRATE - A nitride semiconductor substrate suitable for a high withstand voltage power device is provided in which current collapse is controlled, while reducing leakage current. In a nitride semiconductor substrate, wherein a buffer layer, an active layer, and an electron supply layer, each comprising a group 13 nitride, are stacked one by one on a silicon single crystal substrate, the buffer layer has a structure where a multilayer stack in which a pair of nitride layers having different concentrations of Al or Ga are repeatedly deposited a plurality of times on an initial layer of Al

11-20-2014

20100013055

METHOD FOR PRODUCING TRIALKYL GALLIUM - The present invention provides a method for producing a trialkyl gallium comprising the steps of reacting gallium, magnesium, and an alkyl halide in an ether, and diluting during the reaction the reaction system with an ether; a method for producing a trialkyl gallium comprising the steps of heating in a vacuum a mixture of magnesium and molten gallium, and reacting the mixture with an alkyl halide in a solvent; and a method for producing a trialkyl gallium comprising the step of reacting an alkyl metal with an alkylgallium halide compound represented by the formula

01-21-2010

20100013052

DUAL CHAMBER SYSTEM PROVIDING SIMULTANEOUS ETCH AND DEPOSITION ON OPPOSING SUBSTRATE SIDES FOR GROWING LOW DEFECT DENSITY EPITAXIAL LAYERS - A dual-chamber reactor can include a housing enclosing a volume having a divider therein, where the divider defines a first chamber and a second chamber. The divider can include a substrate holder that supports at least one substrate and exposes a first side of the substrate to the first chamber and a second side of the substrate to the second chamber. The first chamber can include an inlet for delivering at least one reagent to the first chamber for forming a film on the first side of the substrate, and the second chamber can include a removal device for removing material from the second side of the substrate.

(Al, Ga, In)N-BASED COMPOUND SEMICONDUCTOR AND METHOD OF FABRICATING THE SAME - Disclosed are a (Al, Ga, In)N-based compound semiconductor device and a method of fabricating the same. The (Al, Ga, In)N-based compound semiconductor device of the present invention comprises a substrate; a (Al, Ga, In)N-based compound semiconductor layer grown on the substrate; and an electrode formed of at least one material or an alloy thereof selected from the group consisting of Pt, Pd and Au on the (Al, Ga, In)N-based compound semiconductor layer. Further, the method of fabricating the (Al, Ga, In)N-based compound semiconductor device comprises the steps of growing a P layer including P type impurities in a growth chamber; discharging hydrogen and a hydrogen source gas in the growth chamber; lowering the temperature of the (Al, Ga, In)N-based compound semiconductor with the P layer formed thereon to such an extent that it can be withdrawn to the outside from the growth chamber; withdrawing the (Al, Ga, In)N-based compound semiconductor from the growth chamber; and forming an electrode of at least one material or an alloy thereof selected from the group consisting of Pt, Pd and Au on the p layer. According to the present invention, it is possible to sufficiently secure P type conductivity and obtain good ohmic contact characteristics without performing an annealing process. And, no further annealing is necessary when Pt, Pd, Au electrode are used.

11-12-2009

20090278233

BONDED INTERMEDIATE SUBSTRATE AND METHOD OF MAKING SAME - A method includes growing a first epitaxial layer of III-nitride material, forming a damaged region by implanting ions into an exposed surface of the first epitaxial layer, and growing a second epitaxial layer of III-nitride material on the exposed surface of the first epitaxial layer. A level of defects present in the second epitaxial layer is less than a level of defects present in the first epitaxial layer.

11-12-2009

20150035123

CURVATURE COMPENSATED SUBSTRATE AND METHOD OF FORMING SAME - A curvature-control-material (CCM) is formed on one side of a substrate prior to forming a Group III nitride material on the other side of the substrate. The CCM possess a thermal expansion coefficient (TEC) that is lower than the TEC of the substrate and is stable at elevated growth temperatures required for formation of a Group III nitride material. In some embodiments, the deposition conditions of the CCM enable a flat-wafer condition for the Group III nitride material maximizing the emission wavelength uniformity of the Group III nitride material. Employment of the CCM also reduces the final structure bowing during cool down leading to reduced convex substrate curvatures. In some embodiments, the final structure curvature can further be engineered to be concave by proper selection of CCM properties, and via controlled selective etching of the CCM, this method enables the final structure to be flat.

METHOD FOR MANUFACTURING SEMICONDUCTOR LAYER, METHOD FOR MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE, AND SEMICONDUCTOR LAYER FORMING SOLUTION - A method for manufacturing a semiconductor layer according to an embodiment of the present invention comprises preparing a first compound, preparing a second compound, making a semiconductor layer forming solution, and forming a semiconductor layer including a group compound by using this semiconductor layer forming solution. The first compound contains a first chalcogen-element-containing organic compound, a first Lewis base, a I-B group element, and a first III-B group element. The second compound contains an organic ligand and a second III-B group element. The semiconductor layer forming solution contains the first compound, the second compound, and an organic solvent.

12-20-2012

20110108954

Growth of Planar Non-Polar M-Plane Gallium Nitride With Hydride Vapor Phase Epitaxy (HVPE) - A method of growing planar non-polar m-plane III-Nitride material, such as an m-plane gallium nitride (GaN) epitaxial layer, wherein the III-Nitride material is grown on a suitable substrate, such as an m-plane Sapphire substrate, using hydride vapor phase epitaxy (HVPE). The method includes in-situ pretreatment of the substrate at elevated temperatures in the ambient of ammonia and argon, growing an intermediate layer such as an aluminum nitride (AlN) or aluminum-gallium nitride (AlGaN) on the annealed substrate, and growing the non-polar m-plane III-Nitride epitaxial layer on the intermediate layer using HVPE. Various alternative methods are disclosed.

METHOD FOR GROWTH OF SEMIPOLAR (AL,IN,GA,B)N OPTOELECTRONIC DEVICES - A method of fabricating an optoelectronic device, comprising growing an active layer of the device on an oblique surface of a suitable material, wherein the oblique surface comprises a facetted surface. The present invention also discloses a method of fabricating the facetted surfaces. One fabrication process comprises growing an epitaxial layer on a suitable material, etching the epitaxial layer through a mask to form the facets having a specific crystal orientation, and depositing one or more active layers on the facets. Another method comprises growing a layer of material using a lateral overgrowth technique to produce a facetted surface, and depositing one or more active layers on the facetted surfaces. The facetted surfaces are typically semipolar planes.

01-20-2011

20090302425

CARBON RIBBON TO BE COVERED WITH A THIN LAYER MADE OF SEMICONDUCTOR MATERIAL AND METHOD FOR DEPOSITING A LAYER OF THIS TYPE - The present invention relates to a carbon ribbon for covering in a thin layer of semiconductor material, and to a method of deposited such a layer on a substrate constituted by a carbon ribbon. At least one of the two faces of the carbon ribbon is for covering in a layer of semiconductor material by causing the ribbon to pass substantially vertically upwards through a bath of molten semiconductor material. According to the invention, the two edges of at least one of the two faces of the carbon ribbon project so as to form respective rims.

BUFFER LAYER STRUCTURES SUITED FOR III-NITRIDE DEVICES WITH FOREIGN SUBSTRATES - Embodiments of the present disclosure include a buffer structure suited for III-N device having a foreign substrate. The buffer structure can include a first buffer layer having a first aluminum composition and a second buffer layer formed on the first buffer layer, the second buffer layer having a second aluminum composition. The buffer structure further includes a third buffer layer formed on the second buffer layer at a second interface, the third buffer layer having a third aluminum composition. The first aluminum composition decreases in the first buffer layer towards the interface and the second aluminum composition throughout the second buffer layer is greater than the first aluminum composition at the interface.

08-08-2013

20110042787

SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD - To suppress adverse affect caused by dopant in a conductive semiconductor layer in a GaN-based device having a structure in which the conductive semiconductor layer is inserted between a substrate and an active layer.

02-24-2011

20100090311

Growth of low dislocation density group-III nitrides and related thin-film structures - Methods of growing Group-III nitride thin-film structures having reduced dislocation density are provided. Methods in accordance with the present invention comprise growing a Group-III nitride thin-film material while applying an ion flux and preferably while the substrate is stationary or non-rotating substrate. The ion flux is preferably applied as an ion beam at a glancing angle of incidence. Growth under these conditions creates a nanoscale surface corrugation having a characteristic features size, such as can be measured as a wavelength or surface roughness. After the surface corrugation is created, and preferably in the same growth reactor, the substrate is rotated in an ion flux which cause the surface corrugation to be reduced. The result of forming a surface corrugation and then subsequently reducing or removing the surface corrugation is the formation of a nanosculpted region and polished transition region that effectively filter dislocations. Repeating such nanosculpted and polished regions advantageously provide significant reduction in dislocation density in thin-film structures.

04-15-2010

20100090313

III-V Compound Crystal and Semiconductor Electronic Circuit Element - Favorable-quality III-V crystals are easily obtained at low cost without causing cracks, even when using a variety of substrates, and can be used to manufacture semiconductor devices with good quality and at high yields. The III-V crystals are characterized by the following properties: the carrier concentration, resistivity, and dislocation density of the III-V compound crystal are uniform to within ±30% variation along the surface; the III-V compound crystal is misoriented from the c-plane such that the crystal surface does not include any region where its off-axis angle with the c-plane is 0°; and the full width at half-maximum in XRD at the crystal center of the III-V compound is not greater than 150 arcsec.

04-15-2010

20100213577

SEMICONDUCTOR ELECTRONIC DEVICE AND PROCESS OF MANUFACTURING THE SAME - A semiconductor electronic device comprises a substrate; a buffer layer that comprises composite laminations of which a first semiconductor layer, that is formed of a compound semiconductor of a nitride system, that has a lattice constant to be as smaller than that of such the substrate, and that has a coefficient of thermal expansion to be as larger than that of such the substrate, and a second semiconductor layer that is formed of a compound semiconductor of a nitride system are formed as alternately on to such the substrate; a semiconductor operation layer that is formed of a compound semiconductor of a nitride system and that is formed on to such the buffer layer; and a dislocation reduction layer, which comprises a lower layer region and an upper layer region that are formed at any location at an inner side of such the buffer layer and that comprise an interface of a concave and convex shape therebetween, at which a threading dislocation that draws from such the lower layer region toward such the upper layer region is bending at such the interface, wherein such the second semiconductor layer is comprised of a laminated layers as alternately of a third semiconductor layer that has a lattice constant to be as smaller than that of such the substrate and that has a coefficient of thermal expansion to be as larger than that of such the substrate, and of a fourth semiconductor layer that has a lattice constant to be as smaller than that of such the third semiconductor layer and that has a coefficient of thermal expansion to be as larger than that of such the substrate, and an average of such the lattice constants in the second semiconductor layer is to be smaller than that of such the first semiconductor layer, and an average of such the coefficients of thermal expansion in the second semiconductor layer is to be as larger than that of such the substrate.

NITRIDE CRYSTAL WITH REMOVABLE SURFACE LAYER AND METHODS OF MANUFACTURE - A nitride crystal or wafer with a removable surface layer comprises a high quality nitride base crystal, a release layer, and a high quality epitaxial layer. The release layer has a large optical absorption coefficient at wavelengths where the base crystal is substantially transparent and may be etched under conditions where the nitride base crystal and the high quality epitaxial layer are not. The high quality epitaxial layer may be removed from the nitride base crystal by laser liftoff or by chemical etching after deposition of at least one epitaxial device layer. The nitride crystal with a removable surface layer is useful as a substrate for a light emitting diode, a laser diode, a transistor, a photodetector, a solar cell, or for photoelectrochemical water splitting for hydrogen generation.

09-02-2010

20110068434

NITRIDE SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHODS FOR MANUFACTURING NITRIDE SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE - A nitride semiconductor substrate having a main surface serving as a semipolar plane and provided with a chamfered portion capable of effectively preventing cracking and chipping, a semiconductor device fabricated using the nitride semiconductor substrate, and a method for manufacturing the nitride semiconductor substrate and the semiconductor device are provided. The nitride semiconductor substrate includes a main surface inclined at an angle of 71° or more and 79° or less with respect to the (0001) plane toward the [1-100] direction or inclined at an angle of 71° or more and 79° or less with respect to the (000-1) plane toward the [−1100] direction; and a chamfered portion located at an edge of an outer periphery of the main surface. The chamfered portion is inclined at an angle θ

03-24-2011

20150137318

SEMICONDUCTOR WAFER, METHOD OF PRODUCING A SEMICONDUCTOR WAFER AND METHOD OF PRODUCING A COMPOSITE WAFER - A semiconductor wafer is provided. The semiconductor wafer comprises a sacrificial layer, a first semiconductor crystal layer, and a second semiconductor crystal layer above a semiconductor crystal layer forming wafer, wherein the semiconductor crystal layer forming wafer, the sacrificial layer, the first semiconductor crystal layer and the second semiconductor crystal layer are arranged in the order of the semiconductor crystal layer forming wafer, the sacrificial layer, the first semiconductor crystal layer and the second semiconductor crystal layer, a first atom of one type selected from a plurality of types of atoms constituting the semiconductor crystal layer forming wafer or the sacrificial layer is contained in the first semiconductor crystal layer and the second semiconductor crystal layer as an impurity, and the concentration of the first atom in the second semiconductor crystal layer is lower than the concentration of the first atom in the first semiconductor crystal layer.

COMPOUND SEMICONDUCTOR SUBSTRATE - A compound semiconductor substrate which inhibits the generation of a crack or a warp and is preferable for a normally-off type high breakdown voltage device, arranged that a multilayer buffer layer

03-17-2011

20120175740

BASE SUBSTRATE, GROUP 3B NITRIDE CRYSTAL, AND METHOD FOR MANUFACTURING THE SAME - Regarding a base substrate, a plurality of steps are formed stepwise on the principal surface (c-face). Each step has a height difference of 10 to 40 μm, and an edge is formed parallel to an a-face of a hexagonal crystal of GaN. Meanwhile, the terrace width of each step is set at a predetermined width. The predetermined width is set in such a way that after a GaN crystal is grown on the principal surface of the base substrate, the principal surface is covered up with grain boundaries when the grown GaN crystal is observed from the surface side. The plurality of steps can be formed through, for example, dry etching, sand blasting, lasing, and dicing.

07-12-2012

20110095401

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - In a method for manufacturing a semiconductor device, the method includes the step of growing a nitride-based III-V compound semiconductor layer, which forms a device structure, directly on a substrate without growing a buffer layer, the substrate being made of a material with a hexagonal crystal structure and having a principal surface that is oriented off at an angle of not less than −0.5° and not more than 0° from an R-plane with respect to a direction of a C-axis.

CONDUCTIVE NITRIDE SEMICONDUCTOR SUBSTRATE AND METHOD FOR PRODUCING THE SAME - A method for producing a conductive nitride semiconductor substrate circuit includes the steps of forming, on an underlying substrate, a mask including dot or stripe masking portions having a width or diameter of 10 to 100 μm and arranged at a spacing of 250 to 10,000 μm; growing a nitride semiconductor crystal on the underlying substrate by hydride vapor phase epitaxy (HVPE) at a growth temperature of 1,040° C. to 1,150° C. by supplying a group III source gas, a group V source gas, and a silicon-containing gas in a V/III ratio of 1 to 10; and removing the underlying substrate, thus forming a free-standing conductive nitride semiconductor crystal substrate having a resistivity r of 0.0015 Ωcm≦r≦0.01 Ωcm, a thickness of 100 μm or more, and a radius of bow curvature U of 3.5 m≦U≦8 m.

GROUP III NITRIDE SEMICONDUCTOR SINGLE CRYSTAL, METHOD FOR PRODUCING THE SAME, SELF-STANDING SUBSTRATE, AND SEMICONDUCTOR DEVICE - Objects of the present invention are to provide a method for producing a Group III nitride semiconductor single crystal, which method enables production of a Group III nitride semiconductor single crystal having a flat surface by means of a crucible having any inside diameter; to provide a self-standing substrate obtained from the Group III nitride semiconductor single crystal; and to provide a semiconductor device employing the self-standing substrate. The production method includes adding the template, a flux, and semiconductor raw materials to a crucible and growing a Group III nitride semiconductor single crystal while the crucible is rotated. In the growth of the semiconductor single crystal, the crucible having an inside diameter R (mm) is rotated at a maximum rotation speed ω (rpm) satisfying the following conditions:

METHOD FOR PRODUCING III-N LAYERS, AND III-N LAYERS OR III-N SUBSTRATES, AND DEVICES BASED THEREON - An epitaxial growth process for producing a thick III-N layer, wherein III denotes at least one element of group III of the periodic table of elements, is disclosed, wherein a thick III-N layer is deposited above a foreign substrate. The epitaxial growth process preferably is carried out by HVPE. The substrate can also be a template comprising the foreign substrate and at least one thin III-N intermediate layer. The surface quality is improved by providing a slight intentional misorientation of the substrate, and/or a reduction of the N/III ratio and/or the reactor pressure towards the end of the epitaxial growth process. Substrates and semiconductor devices with such improved III-N layers are also disclosed.

01-27-2011

20110018105

NITRIDE-BASED COMPOUND SEMICONDUCTOR DEVICE, COMPOUND SEMICONDUCTOR DEVICE, AND METHOD OF PRODUCING THE DEVICES - There is provided a method of producing a nitride-based compound semiconductor device that suppresses the adhesion of foreign matters including impurity, fine particles and the like on a surface of a compound semiconductor. The method of producing a nitride-based compound semiconductor device in accordance with the present invention includes the steps of: preparing a nitride-based compound semiconductor (or a substrate preparation step); and cleaning. In the step of cleaning, the nitride-based compound semiconductor is cleaned with a cleaning liquid having a pH of 7.1 or higher ultrasonically.

GROWING PROCESS FOR GROUP III NITRIDE ELEMENTS - The disclosure relates to a method for growing an element III nitride, wherein the growth is carried out on a substrate made of a material capable of maintaining the same crystalline structure from the element III nitride growth temperature to room temperature, the substrate being an M-V—O

04-21-2011

20110089536

ORIENTATION OF ELECTRONIC DEVICES ON MIS-CUT SUBSTRATES - A microelectronic assembly in which a semiconductor device structure is directionally positioned on an off-axis substrate. In an illustrative implementation, a laser diode is oriented on a GaN substrate wherein the GaN substrate includes a GaN (0001) surface off-cut from the <0001> direction predominantly towards either the <11

POWER DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present power device includes a metal-made support substrate, and a group III nitride conductive layer, a group III nitride active layer and an electrode successively formed on one main surface side of the metal-made support substrate. In addition, the present method for manufacturing a power device includes the steps of preparing a conductive-layer-joined metal-made support substrate in which a group III nitride conductive layer is joined to a metal-made support substrate, forming a group III nitride active layer on the group III nitride conductive layer, and forming an electrode on the group III nitride active layer. Thus, an inexpensive power device low in on-resistance and a method for manufacturing the same can be provided.

05-03-2012

20150048484

Passivation for Group III-V Semiconductor Devices Having a Plated Metal Layer over an Interlayer Dielectric Layer - A semiconductor device that includes a Group III-V semiconductor substrate, circuit elements in and on the substrate, a first metal layer over the substrate, and an interlayer dielectric (ILD) layer. The ILD layer defines a via that extends through it to the first metal layer. Over the ILD layer is thick second metal layer and a passivation layer. The second metal layer includes an interconnect that extends through the via into contact with the first metal layer. The second metal layer is patterned to define at least one conductor. The passivation layer covers the second metal layer and the interlayer dielectric layer, and includes stacked regions of dielectric material. Ones of the regions under tensile stress alternate with ones of the regions under compressive stress, such that the passivation layer is subject to net compressive stress.

02-19-2015

20140091433

METHOD OF PRODUCING SEMICONDUCTOR WAFER, AND SEMICONDUCTOR WAFER - There is provided a method of producing a semiconductor wafer, including: forming a compound semiconductor layer on a base wafer by epitaxial growth; cleansing a surface of the compound semiconductor layer by means of a cleansing agent containing a selenium compound; and forming an insulating layer on the surface of the compound semiconductor layer. Examples of the selenium compound include a selenium oxide. Examples of the selenium oxide include H

04-03-2014

20140015105

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - The purpose of the present invention is to provide a good ohmic contact for an n-type Group-III nitride semiconductor. An n-type GaN layer and a p-type GaN layer are aequentially formed on a lift-off layer (growth step). A p-side electrode is formed on the top face of the p-type GaN layer. A copper block is formed over the entire area of the top face through a cap metal. Then, the lift-off layer is removed by making a chemical treatment (lift-off step). Then, a laminate structure constituted by the n-type GaN layer, with which the surface of the N polar plane has been exposed, and the p-type GaN layer is subjected to anisotropic wet etching (surface etching step). The N-polar surface after the etching has irregularities constituted by {10-1-1} planes. Then, an n-side electrode is formed on the bottom face of the n-type GaN layer (electrode formation step).

FORMATION OF SUBSTANTIALLY PIT FREE INDIUM GALLIUM NITRIDE - A method of fabricating a device layer structure includes providing a III-nitride semiconductor layer which is bonded to a bonding substrate. A device layer structure is formed on a nitrogen polar surface of the III-nitride semiconductor layer. The device layer structure includes an indium gallium nitride layer with a metal polar surface adjacent to the nitrogen polar surface of the III-nitride semiconductor layer.

03-10-2011

20110057295

EPITAXIAL SUBSTRATE COMPONENT MADE THEREWITH AND CORRESPONDING PRODUCTION METHOD - Proposed is a III-V-semiconductor-containing epitaxial substrate comprising at least one layer of porous III-V semiconductor material, together with a corresponding production method. Also specified is a component, particularly an LED, produced on the proposed epitaxial substrate, and a corresponding production method.

NITRIDE SEMICONDUCTOR COMPONENT LAYER STRUCTURE ON A GROUP IV SUBSTRATE SURFACE - The invention relates to nitride semiconductor component having a Group III nitride layer structure which is deposited on a substrate having a Group IV substrate surface made of a Group IV substrate material with a cubical crystal structure. The Group IV substrate surface has an elementary cell with C2 symmetry, but not with a higher rotational symmetry than C2 symmetry, when any surface reconstruction is ignored. The Group III nitride layer structure has a seeding layer of ternary or quaternary Al

06-03-2010

20150076662

COMPOSITE SUBSTRATE MANUFACTURING METHOD, SEMICONDUCTOR ELEMENT MANUFACTURING METHOD, COMPOSITE SUBSTRATE, AND SEMICONDUCTOR ELEMENT - Provided is a composite substrate manufacturing method, including at least: a first raw board deforming step of preparing a first substrate by deforming a first raw board having at least one surface as a minor surface into a state in which the minor surface warps outward; and a joining step of joining, after the first raw board deforming step, a protruding surface of the first substrate and one surface of a second substrate to each other, thereby manufacturing a composite substrate including the first substrate and the second substrate, in which the second substrate is any one substrate selected from a substrate having both surfaces as substantially flat surfaces and a substrate that warps so that a surface thereof to be joined to the first substrate warps outward. Also provided are a semiconductor element manufacturing method, a composite substrate and a semiconductor element manufactured.

03-19-2015

20090294909

N-type group III nitride-based compound semiconductor and production method therefor - An object of the present invention is to realize, by the flux process, the production of a high-quality n-type semiconductor crystal having high concentration of electrons. The method of the invention for producing an n-type Group III nitride-based compound semiconductor by the flux process, the method including preparing a melt by melting at least a Group III element by use of a flux; supplying a nitrogen-containing gas to the melt; and growing an n-type Group III nitride-based compound semiconductor crystal on a seed crystal from the melt. In the method, carbon and germanium are dissolved in the melt, and germanium is incorporated as a donor into the semiconductor crystal, to thereby produce an n-type semiconductor crystal.

N-TYPE III-V SEMICONDUCTOR STRUCTURES HAVING ULTRA-SHALLOW JUNCTIONS AND METHODS OF FORMING SAME - Provided are methods of fabricating a semiconductor structure. The methods include providing a III-V semiconductor substrate selected from InGaAs and InAs, introducing an n-type dopant selected from S, Se, and Te directly onto a surface of the III-V semiconductor substrate, introducing a co-dopant selected from N and P directly onto a surface of the III-V semiconductor substrate, and diffusing the n-type and co-dopant into the III-V semiconductor substrate, thereby forming an n-doped III-V semiconductor substrate containing the n-type dopant and the co-dopant. The methods produce inventive semiconductor structures, and devices that include the semiconductor structure.

Semiconductor substrate, semiconductor device, and manufacturing methods thereof - The present invention provides a method of manufacturing a semiconductor substrate that includes a substrate, a first semiconductor layer arranged on the substrate, a metallic material layer arranged on the first semiconductor layer, a second semiconductor layer arranged on the first semiconductor layer and the metallic material layer, and a cavity formed in the first semiconductor layer under the metallic material layer.

12-16-2010

20100258911

NITRIDE SEMICONDUCTOR SUBSTRATE - A nitride semiconductor substrate is provided, having a concave or convex warpage on a front surface side, wherein when a rear surface side is placed on a flat surface, an average roughness of the rear surface at a part not in contact with the flat surface and at a part where a height from the flat surface to the rear surface is a prescribed value or more is set to be greater than an average roughness of the rear surface at a part where the height from the flat surface including a part in contact with the flat surface to the rear surface is less than the prescribed value.

10-14-2010

20100289122

III-V NITRIDE SUBSTRATE BOULE AND METHOD OF MAKING AND USING THE SAME - A boule formed by high rate vapor phase growth of Group III-V nitride boules (ingots) on native nitride seeds, from which wafers may be derived for fabrication of microelectronic device structures. The boule is of microelectronic device quality, e.g., having a transverse dimension greater than 1 centimeter, a length greater than 1 millimeter, and a top surface defect density of less than 10

EPITAXIAL METHODS AND STRUCTURES FOR REDUCING SURFACE DISLOCATION DENSITY IN SEMICONDUCTOR MATERIALS - The invention provides methods and structures for reducing surface dislocations of a semiconductor layer, and can be employed during the epitaxial growth of semiconductor structures and layers comprising III-nitride materials. Embodiments involve the formation of a plurality of dislocation pit plugs to prevent propagation of dislocations from an underlying layer of material into a following semiconductor layer of material.

09-30-2010

20100244195

HOST SUBSTRATE FOR NITRIDE BASED LIGHT EMITTING DEVICES - A host substrate and method of making a host substrate for nitride based thin-film semiconductor devices are provided. According to one embodiment, the method includes the steps of providing a silicon layer; etching a pattern of holes in the silicon layer; plating the silicon layer with copper to fill the holes etched in the silicon layer; bonding the silicon layer to a gallium nitride (GaN) layer, the GaN layer attached to a sapphire substrate; and removing the sapphire substrate. The host substrate is configured to address the coefficient of thermal expansion (CTE) mismatch problem and reduce the amount of stress resulting from such CTE mismatch. A combination of metal and semiconductor materials provide for the desired thermal and electrical conductivity while providing for subsequent dicing and incorporation of the finished semiconductor devices into other circuits.

09-30-2010

20110254134

Method of Group III Metal - Nitride Material Growth Using Metal Organic Vapor Phase Epitaxy - The non-polar or semi-polar Nitride film is grown using Metal Organic Vapor Phase Epitaxy over a substrate. The in-situ grown seed layer comprising Magnesium and Nitrogen is deposited prior to the Nitride film growth. The said seed layer enhances the crystal growth of the Nitride material and makes it suitable for electronics and optoelectronics applications. The use of non-polar and/or semi-polar epitaxial films of the Nitride materials allows avoiding the unwanted effects related to polarization fields and associated interface and surface charges, thus significantly improving the semiconductor device performance and efficiency. In addition, the said seed layer is also easily destroyable by physical or chemical stress, including the ability to dissolve in water or acid, which makes the substrate removal process available and easy. The substrate removal provides the possibility to achieve exceptional thermal conductivity and application flexibility, such as additional contact formation, electromagnetic radiation extraction, packaging or other purposes suggested or discovered by the skilled artisan.

GAAS INTEGRATED CIRCUIT DEVICE AND METHOD OF ATTACHING SAME - A gallium arsenide (GaAs) integrated circuit device is provided. The GaAs circuit device has a GaAs substrate with a copper contact layer for making electrical ground contact with a pad of a target device. Although copper is known to detrimentally affect GaAs devices, the copper contact layer is isolated from the GaAs substrate using a barrier layer. The barrier layer may be, for example, a layer of nickel vanadium (NiV). This nickel vanadium (NiV) barrier protects the gallium arsenide substrate from the diffusion effects of the copper contact layer. An organic solder preservative may coat the exposed copper to reduce oxidation effects. In some cases, a gold or copper seed layer may be deposited on the GaAs substrate prior to depositing the copper contact layer.

08-04-2011

20110073995

SEMICONDUCTOR DEVICE, FABRICATION METHOD OF THE SEMICONDUCTOR DEVICES - In a semiconductor device, a YAG substrate is formed as a single-crystal substrate of any of surface orientations (100), (110), and (111). In the fabrication of the semiconductor device, a TMAl gas is first fed onto the YAG substrate so as to form a nucleation layer made of aluminum, which is a group-III element. Then, an NH

DOPANT DIFFUSION MODULATION IN GaN BUFFER LAYERS - A semi-conductor crystal and method of forming the same. The method includes providing a flow of dopant and column III element containing gases, then stopping flow of dopant and column III element containing gases, reducing the temperature, restarting flow of column III containing gases and then elevating the temperature.

10-14-2010

20140291810

METHODS FOR GROWING III-V MATERIALS ON A NON III-V MATERIAL SUBSTRATE - The present invention relates to a method for manufacturing semiconductor materials comprising epitaxial growing of group III-V materials, for example gallium arsenide (GaAs), on for example a non III-V group material like silicon (Si) substrates (wafers), and especially to pre-processing steps providing a location stabilisation of dislocation faults in a surface layer of the non III-V material wafer in an orientation relative to an epitaxial material growing direction during growing of the III-V materials, wherein the location stabilised dislocation fault orientations provides a barrier against threading dislocations (stacking of faults) from being formed in the growing direction of the III-V materials during the epitaxial growth process.

10-02-2014

20140312463

SEMICONDUCTOR STRUCTURES, DEVICES AND ENGINEERED SUBSTRATES INCLUDING LAYERS OF SEMICONDUCTOR MATERIAL HAVING REDUCED LATTICE STRAIN - Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure.

10-23-2014

20120098102

DEFECT REDUCTION OF NON-POLAR AND SEMI-POLAR III-NITRIDES WITH SIDEWALL LATERAL EPITAXIAL OVERGROWTH (SLEO) - A method of reducing threading dislocation densities in non-polar such as a-{11-20} plane and m-{1-100} plane or semi-polar such as {10-1n} plane III-Nitrides by employing lateral epitaxial overgrowth from sidewalls of etched template material through a patterned mask. The method includes depositing a patterned mask on a template material such as a non-polar or semi polar GaN template, etching the template material down to various depths through openings in the mask, and growing non-polar or semi-polar III-Nitride by coalescing laterally from the tops of the sidewalls before the vertically growing material from the trench bottoms reaches the tops of the sidewalls. The coalesced features grow through the openings of the mask, and grow laterally over the dielectric mask until a fully coalesced continuous film is achieved.

SEMICONDUCTOR SUBSTRATE AND METHOD OF FORMING - A method of forming a semiconductive substrate material for an electronic device including forming a plurality of semiconductive layers on a substrate during a continuous growth process in a reaction chamber, wherein during the continuous growth process, a release layer is formed between a base layer and an epitaxial layer by altering at least one growth process parameter during the continuous growth process. The method also including separating the plurality of semiconductive layers from the substrate.

01-03-2013

20110101502

COMPOSITE WAFERS AND SUBSTRATES FOR III-NITRIDE EPITAXY AND DEVICES AND METHODS THEREFOR - A composite wafer comprises a single crystal substrate having first and second sides; a first III-nitride single crystal layer disposed on the first side of the substrate and being defined by a thickness; and a second III-nitride single crystal layer disposed on the second side of the single crystal substrate and being defined by a thickness. The thickness of each III-nitride single crystal layer is substantially the same. The composite wafer may be used in the manufacture of a semiconductor device or a freestanding wafer.

05-05-2011

20100025823

PASSIVATION OF ALUMINUM NITRIDE SUBSTRATES - The present invention provides methods of protecting a surface of an aluminum nitride substrate. The substrate with the protected surface can be stored for a period of time and easily activated to be in a condition ready for thin film growth or other processing. In certain embodiments, the method of protecting the substrate surface comprises forming a passivating layer on at least a portion of the substrate surface by performing a wet etch, which can comprise the use of one or more organic compounds and one or more acids. The invention also provides aluminum nitride substrates having passivated surfaces.

02-04-2010

20140306320

METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES OR DEVICES USING LAYERS OF SEMICONDUCTOR MATERIAL HAVING SELECTED OR CONTROLLED LATTICE PARAMETERS - Methods of fabricating semiconductor devices or structures include bonding a layer of semiconductor material to another material at a temperature, and subsequently changing the temperature of the layer of semiconductor material. The another material may be selected to exhibit a coefficient of thermal expansion such that, as the temperature of the layer of semiconductor material is changed, a controlled and/or selected lattice parameter is imparted to or retained in the layer of semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a layer of semiconductor material having an average lattice parameter at room temperature proximate an average lattice parameter of the layer of semiconductor material previously attained at an elevated temperature.

10-16-2014

20100013054

COMPOSITE MATERIAL SUBSTRATE - A composite material substrate having patterned structure includes a substrate, a first dielectric layer, a second dielectric layer, and a nitride semiconductor material. Herein, the first dielectric layer is stacked on the substrate, the second dielectric layer is stacked on the first dielectric layer, and the nitride semiconductor material is stacked on the second dielectric layer and is characterized by a plurality of patterns thereon.

01-21-2010

20100013053

METHOD FOR MANUFACTURING III-V COMPOUND SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING EPITAXIAL WAFER, III-V COMPOUND SEMICONDUCTOR SUBSTRATE, AND EPITAXIAL WAFER - The present invention provides a method for manufacturing a III-V compound semiconductor substrate, a method for manufacturing an epitaxial wafer, a III-V compound semiconductor substrate, and an epitaxial wafer, wherein the thickness of an oxide film formed on the substrate or in the wafer is controlled with high precision, and surface of the epitaxial wafer is prevented from getting rough,. The method for manufacturing a III-V compound semiconductor substrate according to the present invention includes the following steps. Initially, a substrate composed of a III-V compound semiconductor is provided. Thereafter, the resulting substrate is cleaned with an acidic solution. Subsequently, an oxide film is formed on the substrate by a wet method after the cleaning.

METHOD FOR GROWING GROUP 13 NITRIDE CRYSTAL AND GROUP 13 NITRIDE CRYSTAL - To grow a gallium nitride crystal, a seed-crystal substrate is first immersed in a melt mixture containing gallium and sodium. Then, a gallium nitride crystal is grown on the seed-crystal substrate under heating the melt mixture in a pressurized atmosphere containing nitrogen gas and not containing oxygen. At this time, the gallium nitride crystal is grown on the seed-crystal substrate under a first stirring condition of stirring the melt mixture, the first stirring condition being set for providing a rough growth surface, and the gallium nitride crystal is subsequently grown on the seed-crystal substrate under a second stirring condition of stirring the melt mixture, the second stirring condition being set for providing a smooth growth surface.

01-19-2012

20100001376

METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR SELF-SUPPORTING SUBSTRATE AND NITRIDE SEMICONDUCTOR SELF-SUPPORTING SUBSTRATE - The present invention provides a method for manufacturing a nitride semiconductor self-supporting substrate and a nitride semiconductor self-supporting substrate manufactured by this manufacturing method, the method including at least: a step of preparing a nitride semiconductor self-supporting substrate serving as a seed substrate; a step of epitaxially growing the same type of nitride semiconductor as the seed substrate on the seed substrate; and a step of slicing an epitaxially grown substrate subjected to the epitaxial growth into two pieces in parallel to an epitaxial growth surface. As a result, there is provided a method for manufacturing a large-diameter nitride semiconductor self-supporting substrate having an excellent crystal quality and small warp with good productivity at a low cost, etc.

01-07-2010

20100001375

Patterned Substrate for Hetero-epitaxial Growth of Group-III Nitride Film - A circuit structure includes a substrate and a film over the substrate and including a plurality of portions allocated as a plurality of rows. Each of the plurality of rows of the plurality of portions includes a plurality of convex portions and a plurality of concave portions. In each of the plurality of rows, the plurality of convex portions and the plurality of concave portions are allocated in an alternating pattern.

01-07-2010

20150137317

SEMICONDUCTOR WAFER, METHOD OF PRODUCING A SEMICONDUCTOR WAFER AND METHOD OF PRODUCING A COMPOSITE WAFER - A semiconductor wafer is provided. The semiconductor wafer comprises a sacrificial layer and a semiconductor crystal layer above a semiconductor crystal layer forming wafer, the semiconductor crystal layer forming wafer, the sacrificial layer and the semiconductor crystal layer being arranged in the order of the semiconductor crystal layer forming wafer, the sacrificial layer and the semiconductor crystal layer, wherein the semiconductor wafer comprises a diffusion inhibiting layer that inhibits diffusion of a first atom of one type selected from a plurality of types of atoms constituting the semiconductor crystal layer forming wafer or the sacrificial layer, at any cross-sectional position between (a) the interface of the semiconductor crystal layer forming wafer that faces the sacrificial layer and (b) a middle of the semiconductor crystal layer.

METHODS AND STRUCTURES FOR RELAXATION OF STRAINED LAYERS - The present invention provides methods for relaxing a strained-material layer and structures produced by the methods. Briefly, the methods include depositing a first low-viscosity layer that includes a first compliant material on the strained-material layer, depositing a second low-viscosity layer that includes a second compliant material on the strained-material layer to form a first sandwiched structure and subjecting the first sandwiched structure to a heat treatment such that the reflow of the first and the second low-viscosity layers permits the strained-material layer to at least partly relax.

02-11-2010

20130062734

CRYSTALLINE FILM, DEVICE, AND MANUFACTURING METHODS FOR CRYSTALLINE FILM AND DEVICE - Provided are a crystalline film in which variations in the crystal axis angle after separation from a substrate for epitaxial growth have been eliminated, and various devices in which the properties thereof have been improved by including the crystalline film. And the crystalline film has a thickness of 300 μm or more and 10 mm or less and reformed region pattern is formed in an internal portion of the crystalline film.

03-14-2013

20140217553

TEMPLATE LAYERS FOR HETEROEPITAXIAL DEPOSITION OF III NITRIDE SEMICONDUCTOR MATERIALS USING HVPE PROCESSES - Methods of depositing III-nitride semiconductor materials on substrates include depositing a layer of III-nitride semiconductor material on a surface of a substrate in a nucleation HVPE process stage to form a nucleation layer having a microstructure comprising at least some amorphous III-nitride semiconductor material. The nucleation layer may be annealed to form crystalline islands of epitaxial nucleation material on the surface of the substrate. The islands of epitaxial nucleation material may be grown and coalesced in a coalescence HVPE process stage to form a nucleation template layer of the epitaxial nucleation material. The nucleation template layer may at least substantially cover the surface of the substrate. Additional III-nitride semiconductor material may be deposited over the nucleation template layer of the epitaxial nucleation material in an additional HVPE process stage. Final and intermediate structures comprising III-nitride semiconductor material are formed by such methods.

08-07-2014

20100140745

PULSED SELECTIVE AREA LATERAL EPITAXY FOR GROWTH OF III-NITRIDE MATERIALS OVER NON-POLAR AND SEMI-POLAR SUBSTRATES - An epitaxy procedure for growing extremely low defect density non-polar and semi-polar III-nitride layers over a base layer, and the resulting structures, is generally described. In particular, a pulsed selective area lateral overgrowth of a group III nitride layer can be achieved on a non-polar and semi-polar base layer. By utilizing the novel P-MOCVD or PALE and lateral over growth over selected area, very high lateral growth conditions can be achieved at relatively lower growth temperature which does not affect the III-N surfaces.

MISCUT SEMIPOLAR OPTOELECTRONIC DEVICE - A method for improved growth of a semipolar (Al,In,Ga,B)N semiconductor thin film using an intentionally miscut substrate. Specifically, the method comprises intentionally miscutting a substrate, loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an In

ETCHING METHOD, ETCHING MASK AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - An etching method forms a metal-fluoride layer at a temperature of 150° C. or higher at least as a part of an etching mask formed over a semiconductor layer; patterns the metal-fluoride layer; and etches the semiconductor layer using the patterned metal-fluoride layer as a mask. According to the etching method, an etching-resistant semiconductor layer such as a Group III-V nitride semiconductor can be easily etched by a relatively simpler process.

06-24-2010

20100127353

STRAIN ENGINEERED COMPOSITE SEMICONDUCTOR SUBSTRATES AND METHODS OF FORMING SAME - Composite substrates are produced that include a strained III-nitride material seed layer on a support substrate. Methods of producing the composite substrate include developing a desired lattice strain in the III-nitride material to produce a lattice parameter substantially matching a lattice parameter of a device structure to be formed on the composite substrate. The III-nitride material may be formed with a Ga polarity or a N polarity. The desired lattice strain may be developed by forming a buffer layer between the III-nitride material and a growth substrate, implanting a dopant in the III-nitride material to modify its lattice parameter, or forming the III-nitride material with a coefficient of thermal expansion (CTE) on a growth substrate with a different CTE.

Release Strategies for Making Transferable Semiconductor Structures, Devices and Device Components - Provided are methods for making a device or device component by providing a multi layer structure having a plurality of functional layers and a plurality of release layers and releasing the functional layers from the multilayer structure by separating one or more of the release layers to generate a plurality of transferable structures. The transferable structures are printed onto a device substrate or device component supported by a device substrate. The methods and systems provide means for making high-quality and low-cost photovoltaic devices, transferable semiconductor structures, (opto-)electronic devices and device components.

12-11-2014

20100155900

FABRICATING A GALLIUM NITRIDE DEVICE WITH A DIAMOND LAYER - In one aspect, a method includes fabricating a device. The device includes a gallium nitride (GaN) layer, a diamond layer disposed on the GaN layer and a gate structure disposed in contact with the GaN layer and the diamond layer.

06-24-2010

20100155901

FABRICATING A GALLIUM NITRIDE LAYER WITH DIAMOND LAYERS - In one aspect, a method includes fabricating a gallium nitride (GaN) layer with a first diamond layer having a first thermal conductivity and a second diamond layer having a second thermal conductivity greater than the first thermal conductivity. The fabricating includes using a microwave plasma chemical vapor deposition (CVD) process to deposit the second diamond layer onto the first diamond layer.

06-24-2010

20100109126

METHODS OF FORMING LAYERS OF SEMICONDUCTOR MATERIAL HAVING REDUCED LATTICE STRAIN, SEMICONDUCTOR STRUCTURES, DEVICES AND ENGINEERED SUBSTRATES INCLUDING SAME - Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - There is provided a method for manufacturing a semiconductor device in which a selective growth mask for partially covering a growth substrate is formed on a growth substrate; a buffer layer that is thicker than the mask is formed on a non-mask part not covered by the mask on the growth substrate, and a predetermined facet is exposed on the surface of the buffer layer; a semiconductor film is laterally grown using the buffer layer as a starting point, and a lateral growth layer for covering the mask is formed while cavities are formed on the upper part of the mask; and a device function layer is epitaxially grown on the lateral growth layer. The cavity formation step includes a first step for growing a semiconductor film at a growth rate and a second step for growing another semiconductor film at another growth rate mutually different from the first growth rate, wherein the first and second steps are carried out a plurality of times in alternating fashion.

Method Using Multiple Layer Annealing Cap for Fabricating Group III-Nitride Semiconductor Device Structures and Devices Formed Thereby - A method of preventing the escape of nitrogen during the activation of ion implanted dopants in a Group III-nitride semiconductor compound without damaging the Group III-nitride semiconductor comprising: depositing a first layer of another Group III-nitride that acts as an adhesion layer; depositing a second layer of a Group III-nitride that acts as a mechanical supporting layer; said first and second layers forming an annealing cap to prevent the escape of the nitrogen component of the Group III-nitride semiconductor; annealing the Group III-nitride semiconductor at a temperature in the range of approximately 1100-1250° C.; and removing the first and second layers from the Group III-nitride semiconductor.

06-03-2010

20130221490

METHOD FOR GROWING GROUP 13 NITRIDE CRYSTAL AND GROUP 13 NITRIDE CRYSTAL - To grow a gallium nitride crystal, a seed-crystal substrate is first immersed in a melt mixture containing gallium and sodium. Then, a gallium nitride crystal is grown on the seed-crystal substrate under heating the melt mixture in a pressurized atmosphere containing nitrogen gas and not containing oxygen. At this time, the gallium nitride crystal is grown on the seed-crystal substrate under a first stirring condition of stirring the melt mixture, the first stirring condition being set for providing a rough growth surface, and the gallium nitride crystal is subsequently grown on the seed-crystal substrate under a second stirring condition of stirring the melt mixture, the second stirring condition being set for providing a smooth growth surface.

SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME - Provided is a semiconductor substrate and a method for manufacturing the same. The semiconductor substrate includes a substrate, a discontinuously formed hemispheric metal layer on the substrate, and a semiconductor layer on the hemispheric metal layer. A plurality of voids on the interface of the substrate and discontinuous hemisphere are formed to absorb or relax the stain of interface. Accordingly, even if a subsequent layer is relatively thickly formed on the substrate, substrate bow or warpage can be minimized.

02-03-2011

20140167222

METHOD FOR PRODUCING GROUP III NITRIDE SEMICONDUCTOR AND TEMPLATE SUBSTRATE - A semiconductor substrate includes a sapphire substrate including an a-plane main surface and a groove in a surface thereof, the groove includes side surfaces and a bottom surface, and a Group III nitride semiconductor layer formed on the sapphire substrate. Both side surfaces of the groove assume a c-plane of sapphire. An axis perpendicular to one of the side surfaces of the groove of the Group III nitride semiconductor layer assumes a c-axis of Group III nitride semiconductor. A plane parallel to the main surface of the sapphire substrate of the Group III nitride semiconductor layer assumes an m-plane of Group III nitride semiconductor.

06-19-2014

20100072576

METHODS AND STRUCTURES FOR ALTERING STRAIN IN III-NITRIDE MATERIALS - Methods and structures for producing semiconductor materials, substrates and devices with improved characteristics are disclosed. Structures and methods for forming reduced strain structures include forming an interface between a support structure surface and a strained semiconductor layer. The support structure is selectively etched to form a plurality of semiconductor islands with reduced levels of strain.

03-25-2010

20100176490

METHODS OF FORMING RELAXED LAYERS OF SEMICONDUCTOR MATERIALS, SEMICONDUCTOR STRUCTURES, DEVICES AND ENGINEERED SUBSTRATES INCLUDING SAME - Methods of fabricating relaxed layers of semiconductor materials include forming structures of a semiconductor material overlying a layer of a compliant material, and subsequently altering a viscosity of the compliant material to reduce strain within the semiconductor material. The compliant material may be reflowed during deposition of a second layer of semiconductor material. The compliant material may be selected so that, as the second layer of semiconductor material is deposited, a viscosity of the compliant material is altered imparting relaxation of the structures. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Methods of fabricating semiconductor structures and devices are also disclosed. Novel intermediate structures are formed during such methods. Engineered substrates include a plurality of structures comprising a semiconductor material disposed on a layer of material exhibiting a changeable viscosity.

07-15-2010

20130020681

PROCESS FOR PREPARING A BONDING TYPE SEMICONDUCTOR SUBSTRATE - Provided is a laminate comprising a first compound semiconductor layer; and a second compound semiconductor layer integrally bonded to the first compound semiconductor layer via a bonding layer. A plane A is in the second compound semiconductor layer bonded to a surface where a plane B is in the first compound semiconductor layer, or a surface where a plane B is in the second compound semiconductor layer bonded to a surface where a plane A in the first compound semiconductor layer. The impurity concentration of the bonding layer is 2×10″ cm or more.

01-24-2013

20140191369

NITRIDE SEMICONDUTOR DEVICE - A nitride semiconductor device includes a first nitride semiconductor layer, and an npn junction structure including a second nitride semiconductor layer of an n-type conductivity, a third nitride semiconductor layer of a p-type conductivity, and a fourth nitride semiconductor layer of an n-type conductivity layered in this order on the first nitride semiconductor layer. The third nitride semiconductor layer includes two or more uncovered regions which are uncovered with the fourth nitride semiconductor layer.

07-10-2014

20130082356

HIGH THROUGHPUT EPITAXIAL LIFTOFF FOR RELEASING MULTIPLE SEMICONDUCTOR DEVICE LAYERS FROM A SINGLE BASE SUBSTRATE - In one embodiment, a semiconductor structure is provided which includes a base substrate, and a multilayered stack located on the base substrate. The multilayered stack includes, from bottom to top, a first sacrificial material layer having a first thickness, a first semiconductor device layer, a second sacrificial material layer having a second thickness, and a second semiconductor device layer, wherein the first thickness is less than the second thickness.

04-04-2013

20120153440

EPITAXIAL SUBSTRATE FOR ELECTRONIC DEVICE AND METHOD OF PRODUCING THE SAME - An epitaxial substrate for electronic devices, in which current flows in a lateral direction and of which warpage configuration is properly controlled, and a method of producing the same. The epitaxial substrate for electronic devices is produced by forming a bonded substrate by bonding a low-resistance Si single crystal substrate and a high-resistance Si single crystal substrate together; forming a buffer as an insulating layer on a surface of the bonded substrate on the high-resistance Si single crystal substrate side; and producing an epitaxial substrate by epitaxially growing a plurality of III-nitride layers on the buffer to form a main laminate. The resistivity of the low-resistance Si single crystal substrate is 100 Ω·cm or less, and the resistivity of the high-resistance Si single crystal substrate is 1000 Ω·cm or more.

06-21-2012

20140319656

METHOD AND SYSTEM FOR HEIGHT REGISTRATION DURING CHIP BONDING - A method of fabricating a composite semiconductor structure is provided. Pedestals are formed in a recess of a first substrate. A second substrate is then placed within the recess in contact with the pedestals. The pedestals have a predetermined height so that a device layer within the second substrate aligns with a waveguide of the first substrate, where the waveguide extends from an inner wall of the recess.

Epitaxial Growth of III-V Compound Semiconductors on Silicon Surfaces - A device includes a silicon substrate, and a III-V compound semiconductor region over and contacting the silicon substrate. The III-V compound semiconductor region has a U shaped interface with the silicon substrate, with radii of the U shaped interface being smaller than about 1,000 nm.

12-15-2011

20130075867

METHOD OF PROCESSING A SURFACE OF GROUP III NITRIDE CRYSTAL AND GROUP III NITRIDE CRYSTAL SUBSTRATE - There is provided a method of processing a surface of a group III nitride crystal, that includes the steps of: polishing a surface of a group III nitride crystal with a polishing slurry containing abrasive grains; and thereafter polishing the surface of the group III nitride crystal with a polishing liquid at least once, and each step of polishing with the polishing liquid employs a basic polishing liquid or an acidic polishing liquid as the polishing liquid. The step of polishing with the basic or acidic polishing liquid allows removal of impurity such as abrasive grains remaining on the surface of the group III nitride crystal after it is polished with the slurry containing the abrasive grains.

03-28-2013

20090256240

METHOD FOR PRODUCING GROUP III-NITRIDE WAFERS AND GROUP III-NITRIDE WAFERS - The present invention discloses a production method for group III nitride ingots or pieces such as wafers. To solve the coloration problem in the wafers grown by the ammonothermal method, the present invention composed of the following steps; growth of group III nitride ingots by the ammonothermal method, slicing of the ingots into wafers, annealing of the wafers in a manner that avoids dissociation or decomposition of the wafers. This annealing process is effective to improve transparency of the wafers and/or otherwise remove contaminants from wafers.

10-15-2009

20140070372

SEMICONDUCTOR THIN FILM STRUCTURE AND METHOD OF FORMING THE SAME - A method of forming a semiconductor thin film structure and a semiconductor thin film structure formed using the same is provided. A sacrificial layer is formed on a substrate and then patterned through various methods, an inorganic thin film is formed on the sacrificial layer and then the sacrificial layer is selectively removed to form a cavity defined by the substrate and the inorganic thin film on the substrate.

03-13-2014

20150069575

NITRIDE SEMICONDUCTOR GROWTH APPARATUS, AND EPITAXIAL WAFER FOR NITRIDE SEMICONDUCTOR POWER DEVICE - A nitride semiconductor growth apparatus of the present invention comprises a chamber into which a reactive gas containing nitrogen is to be introduced as a material gas and a reaction part which is placed in the chamber and in which the material gas is brought into reaction to grow a nitride semiconductor. In the nitride semiconductor growth apparatus, in a region which includes a reaction part and part of an upstream side from a reaction part with respect to a flow of a material gas, portions to be in contact with the material gas (a gas introducing part, a current introducing part and a view port part and the like) are made from non-copper material (i.e., material containing no copper).

03-12-2015

20090309189

METHOD FOR THE GROWTH OF INDIUM NITRIDE - The present application relates to a method for the growth of indium nitride on a substrate by means of MOVPE in the presence of a noble gas as growth vector.

12-17-2009

20100090312

Nitride semiconductor structure and method for manufacturing the same - A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes an epitaxy substrate, a nitride pillar layer, a nitride semiconductor layer, and a mask layer. The nitride pillar layer includes a plurality of first patterned arranged pillars and a plurality of second patterned arranged pillars. The nitride pillar layer is formed on the epitaxy substrate. A width of a cross-section of each of the second patterned arranged pillars is smaller than a width of a cross-section of each of the first patterned arranged pillars, and a distance among each of the second patterned arranged pillars is longer than a distance among each of the first patterned arranged pillars. Surfaces of the epitaxy substrate, the first patterned arranged pillars, and the second patterned arranged pillars are covered by the mask layer. The nitride semiconductor layer is formed on the nitride pillar layer.

04-15-2010

20090321882

EPITAZIAL GROWTH OF CRYSTALLINE MATERIAL - A device includes an epitaxially grown crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by creating process parameters which result in the dominant growth component of the crystal to be supplied laterally from side walls of the insulator. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.

12-31-2009

20090315151

Method for testing group III-nitride wafers and group III-nitride wafers with test data - The present invention discloses a new testing method of group III-nitride wafers. By utilizing the ammonothermal method, GaN or other Group III-nitride wafers can be obtained by slicing the bulk GaN ingots. Since these wafers originate from the same ingot, these wafers have similar properties/qualities. Therefore, properties of wafers sliced from an ingot can be estimated from measurement data obtained from selected number of wafers sliced from the same ingot or an ingot before slicing. These estimated properties can be used for product certificate of untested wafers. This scheme can reduce a significant amount of time, labor and cost related to quality control.

Method for manufacturing semiconductor epitaxial crystal substrate - The present invention provides a method for manufacturing a gallium nitride semiconductor epitaxial crystal substrate with a dielectric film which has a low gate leak current and negligibly low gate lag, drain lag, and current collapse characteristics. The method for manufacturing a semiconductor epitaxial crystal substrate is a method for manufacturing a semiconductor epitaxial crystal substrate in which a dielectric layer of a nitride dielectric material or an oxide dielectric material in an amorphous form functioning as a passivation film or a gate insulator is provided on a surface of a nitride semiconductor crystal layer grown by metal organic chemical vapor deposition. In the method, after the nitride semiconductor crystal layer is grown in an epitaxial growth chamber, the dielectric layer is grown on the nitride semiconductor crystal layer in the epitaxial growth chamber.

04-08-2010

20090250790

NITRIDE SEMICONDUCTOR WAFER AND METHOD OF PROCESSING NITRIDE SEMICONDUCTOR WAFER - Nitride semiconductor wafers which are produced by epitaxially grown nitride films on a foreign undersubstrate in vapor phase have strong inner stress due to misfit between the nitride and the undersubstrate material. A GaN wafer which has made by piling GaN films upon a GaAs undersubstrate in vapor phase and eliminating the GaAs undersubstrate bends upward due to the inner stress owing to the misfit of lattice constants between GaN and GaAs. Ordinary one-surface polishing having the steps of gluing a wafer with a surface on a flat disc, bringing another surface in contact with a lower turntable, pressing the disc, rotating the disc, revolving the turntable and whetting the lower surface, cannot remedy the inherent distortion. The Distortion worsens morphology of epitaxial wafers, lowers yield of via-mask exposure and invites cracks on surfaces. Nitride crystals are rigid but fragile. Chemical/mechanical polishing has been requested in vain. Current GaN wafers have roughened bottom surfaces, which induce contamination of particles and fluctuation of thickness.

10-08-2009

20100133657

GROUP III NITRIDE SEMICONDUCTOR SUBSTRATE PRODUCTION METHOD, AND GROUP III NITRIDE SEMICONDUCTOR SUBSTRATE - A group III nitride semiconductor substrate production method includes preparing a bulk crystal formed of a group III nitride semiconductor single crystal. The group III nitride semiconductor single crystal has one crystalline plane and an other crystalline plane. Hardness of the other crystalline plane is smaller than hardness of the one crystalline plane. The prepared bulk crystal is cut from the other crystalline plane to the one crystalline plane of the bulk crystal.

06-03-2010

20090294908

Diluted magnetic semiconductor nanowires exhibiting magnetoresistance - A method for is disclosed for fabricating diluted magnetic semiconductor (DMS) nanowires by providing a catalyst-coated substrate and subjecting at least a portion of the substrate to a semiconductor, and dopant via chloride-based vapor transport to synthesize the nanowires. Using this novel chloride-based chemical vapor transport process, single crystalline diluted magnetic semiconductor nanowires Ga

Integration structure of semiconductor circuit and microprobe sensing elements and method for fabricating the same - The present invention discloses an integration structure of a semiconductor circuit and microprobe sensing elements and a method for fabricating the same. In the method of the present invention, a semiconductor circuit is fabricated on one surface of a semiconductor substrate, and the other surface of the semiconductor substrate is etched to form a microprobe structure for detect physiological signals. Next, a deposition method is used to sequentially form an electrical isolated layer and an electrical conductive layer on the microprobes. Then, an electrical conductive material is used to electrically connect the electrical conductive layer with the electrical pads of the semiconductor circuit. Thus is achieved the integration of a semiconductor circuit and microprobe sensing elements in an identical semiconductor substrate with the problem of electric electrical isolated being solved simultaneously. Thereby, the voltage level detected by the microprobes will not interfere with the operation of the semiconductor circuit.

11-19-2009

20130093059

Bonded Substrate And Method Of Manufacturing The Same - A bonded substrate, the surface roughness of which is reduced, and a method of manufacturing the same. The bonded substrate includes a base substrate and an intermediate layer disposed on the base substrate. The intermediate layer has a greater bubble diffusivity than the base substrate. A thin film layer is bonded onto the intermediate layer, and has a different chemical composition from the base substrate.

04-18-2013

20150292111

METHOD FOR PRODUCING III-N SINGLE CRYSTALS, AND III-N SINGLE CRYSTAL - The present invention relates to the production of III-N templates and also the production of III-N single crystals, III signifying at least one element of the third main group of the periodic table, selected from the group of Al, Ga and In. By adjusting specific parameters during crystal growth, III-N templates can be obtained that bestow properties on the crystal layer that has grown on the foreign substrate which enable flawless III-N single crystals to be obtained in the form of templates or even with large III-N layer thickness.

METHOD FOR MANUFACTURING A GROUP III NITRIDE SUBSTRATE USING A CHEMICAL LIFT-OFF PROCESS - The non-polar or semi-polar group III nitride layer disclosed in a specific example of the present invention can be used for substrates for various electronic devices, wherein problems of conventional polar group III nitride substrates are mitigated or solved by using the nitride substrate of the invention, and further the nitride substrate can be manufactured by a chemical lift-off process.

08-01-2013

20130099357

STRAIN COMPENSATED REO BUFFER FOR III-N ON SILICON - A method of fabricating a rare earth oxide buffered III-N on silicon wafer including providing a crystalline silicon substrate, depositing a rare earth oxide structure on the silicon substrate including one or more layers of single crystal rare earth oxide, and depositing a layer of single crystal III-N material on the rare earth oxide structure so as to form an interface between the rare earth oxide structure and the layer of single crystal III-N material. The layer of single crystal III-N material produces a tensile stress at the interface and the rare earth oxide structure has a compressive stress at the interface dependent upon a thickness of the rare earth oxide structure. The rare earth oxide structure is grown with a thickness sufficient to provide a compressive stress offsetting at least a portion of the tensile stress at the interface to substantially reduce bowing in the wafer.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF - The method for manufacturing a semiconductor device comprises steps of: forming a growth mask with a plurality of openings directly or indirectly upon a substrate that comprises a material differing from GaN-based semiconductor; and growing a plurality of island-like GaN-based semiconductor layers upon the substrate using the growth mask in the (0001) plane orientation in a manner such that the

NITRIDE SEMICONDUCTOR TEMPLATE AND FABRICATING METHOD THEREOF - A nitride semiconductor template including a substrate, a mask layer, a first nitride semiconductor layer and a second nitride semiconductor is provided. The substrate has a plurality of trenches, each of the trenches has a bottom surface, a first inclined sidewall and a second inclined sidewall. The mask layer covers the second inclined sidewall and exposes the first inclined sidewall. The first nitride semiconductor layer is disposed over the substrate and the mask layer. The first nitride semiconductor layer fills the trenches and in contact with the first inclined sidewall. The first nitride semiconductor layer has voids located outside the trenches and parts of the mask layer are exposed by the voids. The first nitride semiconductor layer has a plurality of nano-rods. The second nitride semiconductor layer covers the nano-rods. The spaces between the nano-rods are not entirely filled by the second nitride semiconductor layer.

06-14-2012

20150295155

Structured Substrate - A structured substrate configured for epitaxial growth of a semiconductor layer thereon is provided. Structures can be formed on a side of the structured substrate opposite that of the growth surface for the semiconductor layer. The structures can include cavities and/or pillars, which can be patterned, randomly distributed, and/or the like. The structures can be configured to modify one or more properties of the substrate material such that growth of a higher quality semiconductor layer can be obtained.

10-15-2015

20130032928

GROUP III NITRIDE COMPOSITE SUBSTRATE - A group III nitride composite substrate includes a support substrate, an oxide film formed on the support substrate, and a group III nitride layer formed on the oxide film. The oxide film may be a film selected from the group consisting of a TiO

METHOD OF FABRICATING A NITRIDE SUBSTRATE - A method of fabricating a nitride substrate including preparing a growth substrate and disposing a sacrificial layer on the growth substrate. The sacrificial layer includes a nitride horizontal etching layer including an indium-based nitride and an upper nitride sacrificial layer formed on the nitride horizontal etching layer. The method of fabricating the nitride substrate also includes horizontally etching the nitride horizontal etching layer, forming at least one etching hole at least partially through the upper nitride sacrificial layer such that the at least one etching hole expands in the nitride horizontal etching layer in a horizontal direction during horizontal etching of the nitride horizontal etching layer, forming a nitride epitaxial layer on the upper nitride sacrificial layer by hydride vapor phase epitaxy (HVPE) and separating the nitride epitaxial layer from the growth substrate at the nitride horizontal etching layer.

12-17-2015

20120161289

STRAIN RELAXATION USING METAL MATERIALS AND RELATED STRUCTURES - Methods of fabricating semiconductor structures include forming a plurality of openings extending through a semiconductor material and at least partially through a metal material and deforming the metal material to relax a remaining portion of the semiconductor material. The metal material may be deformed exposing the metal material to a temperature sufficient it to alter (i.e., increase) its ductility. The metal material may be formed from one or more of hafnium, zirconium, yttrium and a metallic glass. Another semiconductor material may be deposited over the remaining portions of the semiconductor material, and a portion the metal material may be removed from between each of the remaining portions of the semiconductor material. Semiconductor structures may be formed using such methods.

06-28-2012

20120161288

THERMAL OXIDATION OF SINGLE CRYSTAL ALUMINUM ANTIMONIDE AND MATERIALS HAVING THE SAME - In one embodiment, a method for forming a non-conductive crystalline oxide layer on an AlSb crystal includes heat treating an AlSb crystal in a partial vacuum atmosphere at a temperature conducive for air adsorbed molecules to desorb, surface molecule groups to decompose, and elemental Sb to evaporate from a surface of the AlSb crystal and exposing the AlSb crystal to an atmosphere comprising oxygen to form a crystalline oxide layer on the surface of the AlSb crystal. In another embodiment, a method for forming a non-conductive crystalline oxide layer on an AlSb crystal includes heat treating an AlSb crystal in a non-oxidizing atmosphere at a temperature conducive for decomposition of an amorphous oxidized surface layer and evaporation of elemental Sb from the AlSb crystal surface and forming stable oxides of Al and Sb from residual surface oxygen to form a crystalline oxide layer on the surface of the AlSb crystal.

METHODS FOR PROCESSING A SEMICONDUCTOR WAFER, A SEMICONDUCTOR WAFER AND A SEMICONDUCTOR DEVICE - A semiconductor wafer, comprising multiple active areas suitable for providing semiconductor devices or circuits. Inactive areas separate the active areas from each other. The wafer has a stressed layer with a first surface, and another layer which is in contact with the stressed layer along a second surface of the stressed layer, opposite to the first surface. Multiple trench lines, extend in parallel to the first surface of the stressed layer in an inactive area and have a depth less than the thickness of the semiconductor wafer.

07-11-2013

20120018847

GALLIUM NITRIDE-BASED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A gallium nitride-based semiconductor device includes a composite substrate and a gallium nitride layer. The composite substrate includes a silicon substrate and a filler. The silicon substrate includes a first surface and a second surface opposite to the first surface, and the first surface defines a number of grooves therein. The filler is filled into the number of grooves on the first surface of the silicon substrate. A thermal expansion coefficient of the filler is bigger than that of the silicon substrate. The gallium nitride layer is formed on the second surface of the silicon substrate.

01-26-2012

20120074524

LATERAL GROWTH METHOD FOR DEFECT REDUCTION OF SEMIPOLAR NITRIDE FILMS - A lateral growth method for defect reduction of semipolar nitride films. The process steps include selecting a semipolar nitride plane and composition, selecting a suitable substrate for growth of the semipolar nitride plane and composition, and applying a selective growth process in which the semipolar nitride nucleates on some areas of the substrate at the exclusion of other areas of the substrate, wherein the selective growth process includes lateral growth of nitride material by a lateral epitaxial overgrowth (LEO), sidewall lateral epitaxial overgrowth (SLEO), cantilever epitaxy or nanomasking.

03-29-2012

20120146191

APPARATUS AND METHOD FOR MANUFACTURING COMPOUND SEMICONDUCTOR, AND COMPOUND SEMICONDUCTOR MANUFACTURED THEREBY - Provided is an apparatus for manufacturing a compound semiconductor by use of metal organic chemical vapor deposition including: a reaction container; a holder on which a formed body is to be placed so that a formed surface of the formed body on which layers of a compound semiconductor are to be formed faces upward, the holder being arranged in the reaction container; and a material supply port supplying a material gas of the compound semiconductor into the reaction container from outside, wherein the holder includes a support member supporting the formed body so that an undersurface of the formed body and a top surface of the holder on which the formed body is to be placed keep a predetermined distance.

06-14-2012

20140138796

STRAIN RELAXATION USING METAL MATERIALS AND RELATED STRUCTURES - Methods of fabricating semiconductor structures include forming a plurality of openings extending through a semiconductor material and at least partially through a metal material and deforming the metal material to relax a remaining portion of the semiconductor material. The metal material may be deformed by exposing the metal material to a temperature sufficient to alter (i.e., increase) its ductility. The metal material may be formed from one or more of hafnium, zirconium, yttrium, and a metallic glass. Another semiconductor material may be deposited over the remaining portions of the semiconductor material, and a portion of the metal material may be removed from between each of the remaining portions of the semiconductor material. Semiconductor structures may be formed using such methods.

05-22-2014

20120168911

SILICON WAFER STRENGTH ENHANCEMENT - Provided is a method of fabricating a semiconductor device. The method includes: receiving a silicon wafer that contains oxygen; forming a zone in the silicon wafer, the zone being substantially depleted of oxygen; causing a nucleation process to take place in the silicon wafer to form oxygen nuclei in a region of the silicon wafer outside the zone; and growing the oxygen nuclei into defects. Also provided is an apparatus that includes a silicon wafer. The silicon wafer includes: a first portion that is substantially free of oxygen, the first portion being disposed near a surface of the silicon wafer; and a second portion that contains oxygen; wherein the second portion is at least partially surrounded by the first portion.

07-05-2012

20120153439

STACKED LAYERS OF NITRIDE SEMICONDUCTOR AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, stacked layers of a nitride semiconductor include a substrate, a single crystal layer and a nitride semiconductor layer. The substrate does not include a nitride semiconductor and has a protrusion on a major surface. The single crystal layer is provided directly on the major surface of the substrate to cover the protrusion, and includes a crack therein. The nitride semiconductor layer is provided on the single crystal layer.

06-21-2012

20120112320

NITRIDE SEMICONDUCTOR CRYSTAL AND PRODUCTION PROCESS THEREOF - A production process for a nitride semiconductor crystal, comprising growing a semiconductor layer on a seed substrate to obtain a nitride semiconductor crystal, wherein the seed substrate comprises a plurality of seed substrates made of the same material, at least one of the plurality of seed substrates differs in the off-angle from the other seed substrates, and a single semiconductor layer is grown by disposing the plurality of seed substrates in a semiconductor crystal production apparatus, such that when the single semiconductor layer is grown on the plurality of seed substrates, the off-angle distribution in the single semiconductor layer becomes smaller than the off-angle distribution in the plurality of seed substrates.

05-10-2012

20110316120

Release Strategies for Making Transferable Semiconductor Structures, Devices and Device Components - Provided are methods for making a device or device component by providing a multilayer structure having a plurality of functional layers and a plurality of release layers and releasing the functional layers from the multilayer structure by separating one or more of the release layers to generate a plurality of transferable structures. The transferable structures are printed onto a device substrate or device component supported by a device substrate. The methods and systems provide means for making high-quality and low-cost photovoltaic devices, transferable semiconductor structures, (opto-)electronic devices and device components.

12-29-2011

20130207237

METHOD FOR PRODUCING GALLIUM NITRIDE SUBSTRATES FOR ELECTRONIC AND OPTOELECTRONIC DEVICES - A method for separating a III-nitride layer from a substrate. This is done by fabricating a detachment porous region between the III-nitride layer and the substrate through etching. The porous region allows for easy detachment of the III-nitride layer from the substrate. Active layers for electronic and optoelectronic devices can then be grown on the III-nitride layer.

08-15-2013

20120217617

Semi-Polar Wurtzite Group III Nitride Based Semiconductor Layers and Semiconductor Components Based Thereon - Semipolar wurtzite Group III nitride-based semiconductor layers and semiconductor components based thereon are described. Group III nitride layers have a broad range of applications in electronics and optoelectronics. Such layers are generally grown on substrates such as sapphire, SiC and, more recently, Si(111). The layers obtained are generally polar or have c-axis orientation in the direction of growth. For many applications in the field of optoelectronics, as well as acoustic applications in SAWs, the growth of non-polar or semipolar Group III nitride layers is interesting or necessary. The process according to the invention permits simple and inexpensive growth of polarisation-reduced Group III nitride layers without prior structuring of the substrate.

08-30-2012

20150311388

NITRIDE SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING THE SAME - A method of manufacturing a nitride semiconductor element includes dry etching a main surface of a sapphire substrate at a c-plane side thereof, using a mask provided on the main surface, to form a plurality of projections, each having a circular bottom surface; wet etching the sapphire substrate to form an upper part of each projection into a triangular pyramid shape while maintaining the circular bottom surface of the projection; and growing a semiconductor layer made of a nitride semiconductor on a dry etched surface and a wet etched surface of the sapphire substrate.

Virtual substrates for epitaxial growth and methods of making the same - A virtual substrate includes a handle support and a strain-relieved single crystalline layer on the handle support. A method of making the virtual substrate includes growing a coherently-strained single crystalline layer on an initial growth substrate, removing the initial growth substrate to relieve the strain on the single crystalline layer, and applying the strain-relieved single crystalline layer on a handle support.

08-11-2011

20120211870

III-V SEMICONDUCTOR STRUCTURES WITH DIMINISHED PIT DEFECTS AND METHODS FOR FORMING THE SAME - Embodiments relate to semiconductor structures and methods of forming them. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. An In-III-V semiconductor layer is grown with an Indium concentration above a saturation regime by adjusting growth conditions such as a temperature of a growth surface to create a super-saturation regime wherein the In-III-V semiconductor layer will grow with a diminished density of V-pits relative to the saturation regime.

08-23-2012

20110284993

COMPOSITE GROWTH SUBSTRATE FOR GROWING SIMICONDUCTOR DEVICE - A method according to embodiments of the invention includes providing an epitaxial structure comprising a donor layer and a strained layer. The epitaxial structure is treated to cause the strained layer to relax. Relaxation of the strained layer causes an in-plane lattice constant of the donor layer to change.

11-24-2011

20120199952

Method for Growth of Indium-Containing Nitride Films - A method for growth of indium-containing nitride films is described, particularly a method for fabricating a gallium, indium, and nitrogen containing material. On a substrate having a surface region a material having a first indium-rich concentration is formed, followed by a second thickness of material having a first indium-poor concentration. Then a third thickness of material having a second indium-rich concentration is added to form a sandwiched structure which is thermally processed to cause formation of well-crystallized, relaxed material within a vicinity of a surface region of the sandwich structure.

PLANAR NONPOLAR GROUP-III NITRIDE FILMS GROWN ON MISCUT SUBSTRATES - A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an α-axis direction comprising a 0.15° or greater miscut angle towards the α-axis direction and a less than 30° miscut angle towards the α-axis direction.

07-12-2012

20120256297

METHOD FOR PRODUCING NITRIDE COMPOUND SEMICONDUCTOR SUBSTRATE, AND NITRIDE COMPOUND SEMICONDUCTOR FREE-STANDING SUBSTRATE - Disclosed is a technique capable of preventing occurrence of warping in a nitride compound semiconductor layer, and by which a nitride compound semiconductor layer having small variations in the in-plane off angle can be grown with good reproducibility. Specifically disclosed is a method for producing a nitride compound semiconductor substrate using an HVPE process, wherein a low-temperature protective layer is formed on a rare earth perovskite substrate at a first growth temperature (a first step), and a thick layer composed of a nitride compound semiconductor is formed on the low-temperature protective layer at a second growth temperature that is higher than the first growth temperature (a second step). In the first step, the supply amounts of HCl and NH

EPITAXIAL METHODS FOR REDUCING SURFACE DISLOCATION DENSITY IN SEMICONDUCTOR MATERIALS - The invention provides methods and structures for reducing surface dislocations of a semiconductor layer, and can be employed during the epitaxial growth of semiconductor structures and layers comprising III-nitride materials. Embodiments involve the formation of a plurality of dislocation pit plugs to prevent propagation of dislocations from an underlying layer of material into a following semiconductor layer of material.

07-26-2012

20150318352

NANOSCALE CHEMICAL TEMPLATING WITH OXYGEN REACTIVE MATERIALS - A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided. The method includes controlling the spatial placement of the semiconductor nanowires by using an oxygen reactive seed material. The present invention also provides semiconductor structures including semiconductor nanowires. In yet another embodiment, patterning of a compound semiconductor substrate or other like substrate which is capable of forming a compound semiconductor alloy with an oxygen reactive element during a subsequent annealing step is provided. This embodiment provides a patterned substrate that can be used in various applications including, for example, in semiconductor device manufacturing, optoelectronic device manufacturing and solar cell device manufacturing.

PLANARIZATION OF GaN BY PHOTORESIST TECHNIQUE USING AN INDUCTIVELY COUPLEDPLASMA - Films of III-nitride for semiconductor device growth are planarized using an etch-back method. The method includes coating a III-nitride surface having surface roughness features in the micron range with a sacrificial planarization material such as an appropriately chosen photoresist. The sacrificial planarization material is then etched together with the III-nitride roughness features using dry etch methods such as inductively coupled plasma reactive ion etching. By closely matching the etch rates of the sacrificial planarization material and the III-nitride material, a planarized III-nitride surface is achieved. The etch-back process together with a high temperature annealing process yields a planarized III-nitride surface with surface roughness features reduced to the nm range. Planarized III-nitride, e.g., GaN, substrates and devices containing them are also provided.

GROUP III NITRIDE CRYSTAL PRODUCTION METHOD AND GROUP III NITRIDE CRYSTAL - Provided is a high-quality Group III nitride crystal of excellent processability. A Group III nitride crystal is produced by forming a film is composed of an oxide, hydroxide and/or oxyhydroxide containing a Group III element by heat-treating a Group III nitride single crystal at 1000° C. or above, and removing the film.

02-06-2014

20120248577

Controlled Doping in III-V Materials - A method according to embodiments of the invention includes epitaxially growing a III-nitride semiconductor layer from a gas containing gallium, a gas containing nitrogen, and a gas containing indium. The concentration of indium in the III-nitride semiconductor structure is greater than zero and less than 10

DEFECT CAPPING FOR REDUCED DEFECT DENSITY EPITAXIAL ARTICLES - An epitaxial article includes a substrate having a substrate surface having a substrate surface composition including crystalline defect or amorphous regions and crystalline non-defect regions. The crystalline defect or amorphous regions are recessed from the substrate surface by surface recess regions. A capping material fills the surface recess regions to provide capped defects that extend from a top of the defect regions to the substrate surface. The capping material is compositionally different from the substrate surface composition. An epitaxial layer over the substrate surface provides an average crystalline defect density in at least one area having a size ≧0.5 μm

09-15-2011

20110127640

STIFFENING LAYERS FOR THE RELAXATION OF STRAINED LAYERS - The present invention relates to a method for relaxing a strained material layer by providing a strained material layer and a low-viscosity layer formed on a first face of the strained material layer; forming a stiffening layer on at least one part of a second face of the strained material layer opposite to the first face thereby forming a multilayer stack; and subjecting the multilayer stack to a heat treatment thereby at least partially relaxing the strained material layer.

METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES OR DEVICES USING LAYERS OF SEMICONDUCTOR MATERIAL HAVING SELECTED OR CONTROLLED LATTICE PARAMETERS - Methods of fabricating semiconductor devices or structures include bonding a layer of semiconductor material to another material at a temperature, and subsequently changing the temperature of the layer of semiconductor material. The another material may be selected to exhibit a coefficient of thermal expansion such that, as the temperature of the layer of semiconductor material is changed, a controlled and/or selected lattice parameter is imparted to or retained in the layer of semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a layer of semiconductor material having an average lattice parameter at room temperature proximate an average lattice parameter of the layer of semiconductor material previously attained at an elevated temperature.

06-30-2011

20110156214

STRUCTURE OF THIN NITRIDE FILM AND FORMATION METHOD THEREOF - Provided are a nitride thin film structure and a method of forming the same. If a nitride thin film is formed on a substrate that is not a nitride, many defects are generated by a difference in lattice constants between the substrate and the nitride thin film. Also, there is a problem of warping the substrate by a difference in thermal expansion coefficients between the substrate and the nitride thin film. In order to solve the problems, the present invention suggests a thin film structure in which after coating hollow particles, i.e. hollow structures on the substrate, the nitride thin film is grown thereon and the method of forming the thin film structure. According to the present invention, since an epitaxial lateral overgrowth (ELO) effect can be obtained by the hollow structures, high-quality nitride thin film can be formed. Since a refractive index in the thin film structure is adjusted, there is an effect of increasing light extraction efficiency during manufacturing the thin film structure into a light emitting device such as a light emitting diode (LED). Also, when thermal expansion coefficient of the substrate is greater than that of the nitride thin film, total stress of the nitride thin film is decreased according to the compression of the hollow structures in the nitride thin film such that there is also an effect of preventing warpage of the substrate.

06-30-2011

20110156213

METHOD OF MANUFACTURING NITRIDE SUBSTRATE, AND NITRIDE SUBSTRATE - A method of manufacturing a nitride substrate includes the following steps. Firstly, a nitride crystal is grown. Then, the nitride substrate including a front surface is cut from the nitride crystal. In the step of cutting, the nitride substrate is cut such that an off angle formed between an axis orthogonal to the front surface and an m-axis or an a-axis is greater than zero. When the nitride crystal is grown in a c-axis direction, in the step of cutting, the nitride substrate is cut from the nitride crystal along a flat plane which passes through a front surface and a rear surface of the nitride crystal and does not pass through a line segment connecting a center of a radius of curvature of the front surface with a center of a radius of curvature of the rear surface of the nitride crystal.

06-30-2011

20110140242

Stress compensation for large area gallium nitride or other nitride-based structures on semiconductor substrates - A method includes forming a stress compensating stack over a substrate, where the stress compensating stack has compressive stress on the substrate. The method also includes forming one or more Group III-nitride islands over the substrate, where the one or more Group III-nitride islands have tensile stress on the substrate. The method further includes at least partially counteracting the tensile stress from the one or more Group III-nitride islands using the compressive stress from the stress compensating stack. Forming the stress compensating stack could include forming one or more oxide layers and one or more nitride layers over the substrate. The one or more oxide layers can have compressive stress, the one or more nitride layers can have tensile stress, and the oxide and nitride layers could collectively have compressive stress. Thicknesses of the oxide and nitride layers can be selected to provide the desired amount of stress compensation.

06-16-2011

20110233730

REACTIVE CODOPING OF GaAlInP COMPOUND SEMICONDUCTORS - A GaAlInP compound semiconductor and a method of producing a GaAlInP compound semiconductor are provided. The apparatus and method comprises a GaAs crystal substrate in a metal organic vapor deposition reactor. Al, Ga, In vapors are prepared by thermally decomposing organometallic compounds. P vapors are prepared by thermally decomposing phosphine gas, Zn vapors are prepared by thermally decomposing an organometallic group IIA or IIB compound. Group VIB vapors are prepared by thermally decomposing a gaseous compound of group VIB. The Al, Ga, In, P, group II, and group VIB vapors grow a GaAlInP crystal doped with group IIA or IIB and group VIB elements on the substrate wherein the group IIA or IIB and group VIB vapors produce a codoped GaAlInP compound semiconductor with a group IIA or IIB element serving as a p-type dopant having low group II atomic diffusion.

09-29-2011

20110175201

GROUP III NITRIDE SEMICONDUCTOR DEVICE - A Group III nitride semiconductor device has a semiconductor region, a metal electrode, and a transition layer. The semiconductor region has a surface comprised of a Group III nitride crystal. The semiconductor region is doped with a p-type dopant. The surface is one of a semipolar surface and a nonpolar surface. The metal electrode is provided on the surface. The transition layer is formed between the Group III nitride crystal of the semiconductor region and the metal electrode. The transition layer is made by interdiffusion of a metal of the metal electrode and a Group III nitride of the semiconductor region.

TECHNIQUES FOR ACHIEVING LOW RESISTANCE CONTACTS TO NONPOLAR AND SEMIPOLAR P-TYPE (Al,Ga,In)N - A method of fabricating a p-type contact on a nonpolar or semipolar (Al,Ga,In)N device, includes the steps of growing a p-type layer on an (Al,Ga,In)N device, wherein the (Al,Ga,In)N device is a nonpolar or semipolar (Al,Ga,In)N device, and the p-type layer is a nonpolar or semipolar (Al,Ga,In)N layer; and cooling the p-type layer down, in the presence of Bis(Cyclopentadienyl)Magnesium (Cp2Mg), to form a magnesium-nitride (Mg

NON-POLAR III-V NITRIDE MATERIAL AND PRODUCTION METHOD - A method for growing flat, low defect density, and strain-free thick non-polar III-V nitride materials and devices on any suitable foreign substrates using a fabricated nano-pores and nano-network compliant layer with an HVPE, MOCVD, and integrated HVPE/MOCVD growth process in a manner that minimum growth will occur in the nano-pores is provided. The method produces nano-networks made of the non-polar III-V nitride material and the substrate used to grow it where the network is continuous along the surface of the template, and where the nano-pores can be of any shape.

Semiconductor device having electrode film in which film thickness of periphery is thinner than film thickness of center - A semiconductor device includes a substrate having first main face having rectangular shape, a first electrode provided at the center on first main face of substrate, first electrode is made of conducting material harder than substrate, and a second electrode provided along at least a part of the periphery on first main face so as to surround first electrode, second electrode is integrated with first electrode by the same conducting material as that of the first electrode, and second electrode has a thinner film thickness than that of the first electrode.

03-05-2009

20090236693

Planarization of Gan by Photoresist Technique Using an Inductively Coupled Plasma - Films of III-nitride for semiconductor device growth are planarized using an etch-back method. The method includes coating a III-nitride surface having surface roughness features in the micron range with a sacrificial planarization material such as an appropriately chose photoresist. The sacrificial planarization material is then etched together with the III-nitride roughness features using dry etch methods such as inductivel coupled plasma reactive ion etching. By closely matching the etch rates of the sacrificial planarization material and the III-nitride material, a planarized III-nitride surface is achieved. The etch-back process together with a high temperature annealing process yields a planarize III-nitride surface with surface roughness features reduced to the nm range. Planarized III-nitride, e.g., GaN, substrates and devices containing them are also provided.

09-24-2009

20080211062

NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided which enable reduction and enhanced stability of contact resistance between the back surface of a nitride substrate and an electrode formed thereover. A nitride semiconductor device includes an n-type GaN substrate (

PROCESS FOR FABRICATING A STRUCTURE FOR EPITAXY WITHOUT AN EXCLUSION ZONE - A process for fabricating a composite structure for epitaxy, including at least one crystalline growth seed layer of semiconductor material on a support substrate, with the support substrate and the crystalline growth seed layer each having, on the periphery of their bonding face, a chamfer or an edge rounding zone. The process includes at least one step of wafer bonding the crystalline growth seed layer directly onto the support substrate and at least one step of thinning the crystalline growth seed layer. After thinning, the crystalline growth seed layer has a diameter identical to its initial diameter.

12-11-2008

20080308907

PLANAR NONPOLAR m-PLANE GROUP III NITRIDE FILMS GROWN ON MISCUT SUBSTRATES - A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an a-axis direction comprising a 0.15° or greater miscut angle towards the a-axis direction and a less than 30° miscut angle towards the a-axis direction.

GALLIUM NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A gallium nitride semiconductor device is disclosed that can be made by an easy manufacturing method. The device includes a silicon substrate, buffer layers formed on the top surface of the silicon substrate, and gallium nitride grown layers formed thereon. The silicon substrate has trenches

04-02-2009

20090057835

Group III nitride semiconductor and a manufacturing method thereof - A manufacturing method of a group III nitride semiconductor includes the steps of: depositing a metal layer on an AlN template substrate or an AlN single crystal substrate formed by depositing an AlN single crystal layer with a thickness of not less than 0.1 μm nor more than 10 μm on a substrate made of either one of sapphire, SiC, and Si; forming a metal nitride layer having a plurality of substantially triangular-pyramid-shaped or triangular-trapezoid-shaped microcrystals by performing a heating nitridation process on the metal layer under a mixed gas atmosphere of ammonia; and depositing a group III nitride semiconductor layer on the metal nitride layer.

03-05-2009

20090200645

SEMICONDUCTOR ELECTRONIC DEVICE - A semiconductor electronic device comprises a substrate; a buffer layer formed on the substrate, the buffer layer including not less than two layers of composite layer in which a first semiconductor layer formed of a nitride-based compound semiconductor layer having a lattice constant smaller than a lattice constant of the substrate and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate and a second semiconductor layer formed of a nitride-based compound semiconductor having a lattice constant smaller than a lattice constant of the first semiconductor layer and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate are alternately laminated; an intermediate layer provided between the substrate and the buffer layer, the intermediate layer being formed of a nitride-based compound semiconductor having a lattice constant smaller than a lattice constant of the first semiconductor layer and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate; and a semiconductor active layer formed on the buffer layer, the semiconductor active layer being formed of a nitride-based compound semiconductor, wherein: thicknesses of the first semiconductor layers in the buffer layer are non-uniform thereamong, and at least one of the first semiconductor layer has a thickness greater than a critical thickness, the critical thickness being a thickness above which a direction of warp caused by the first semiconductor layer to the substrate is inverted.

08-13-2009

20080265374

(Al, Ga, In)N-BASED COMPOUND SEMICONDUCTOR AND METHOD OF FABRICATING THE SAME - Disclosed are a (Al, Ga, In)N-based compound semiconductor device and a method of fabricating the same. The (Al, Ga, In)N-based compound semiconductor device of the present invention comprises a substrate; a (Al, Ga, In)N-based compound semiconductor layer grown on the substrate; and an electrode formed of at least one material or an alloy thereof selected from the group consisting of Pt, Pd and Au on the (Al, Ga, In)N-based compound semiconductor layer. Further, the method of fabricating the (Al, Ga, In)N-based compound semiconductor device comprises the steps of growing a P layer including P type impurities in a growth chamber; discharging hydrogen and a hydrogen source gas in the growth chamber; lowering the temperature of the (Al, Ga, In)N-based compound semiconductor with the P layer formed thereon to such an extent that it can be withdrawn to the outside from the growth chamber; withdrawing the (Al, Ga, In)N-based compound semiconductor from the growth chamber; and forming an electrode of at least one material or an alloy thereof selected from the group consisting of Pt, Pd and Au on the p layer. According to the present invention, it is possible to sufficiently secure P type conductivity and obtain good ohmic contact characteristics without performing an annealing process. And, no further annealing is necessary when Pt, Pd, Au electrode are used.

CHAMFERED FREESTANDING NITRIDE SEMICONDUCTOR WAFER AND METHOD OF CHAMFERING NITRIDE SEMICONDUCTOR WAFER - Technology of making freestanding gallium nitride (GaN) wafers has been matured at length. Gallium nitride is rigid but fragile. Chamfering of a periphery of a GaN wafer is difficult. At present edges are chamfered by a rotary whetstone of gross granules with weak pressure. Minimum roughness of the chamfered edges is still about Ra 10 μm to Ra 6 μm. The large edge roughness causes scratches, cracks, splits or breaks in transferring process or wafer process. A wafer of the present invention is bevelled by fixing the wafer to a chuck of a rotor, bringing an edge of the wafer into contact with an elastic whetting material having a soft matrix and granules implanted on the soft matrix, rotating the wafer and feeding the whetting material. Favorably, several times of chamfering edges by changing the whetting materials of smaller granules are given to the wafer. The chamfering can realize small roughness of Ra 10 nm and Ra 5 μm at edges of wafers.

09-03-2009

20090230514

Method of manufacturing nitride semiconductor device - A method of manufacturing a nitride semiconductor device includes the steps of: growing a group III nitride semiconductor layer on a substrate; forming a processed region in the substrate with a laser beam; and reducing the thickness of the substrate thereby spontaneously dividing the substrate from the processed region by the internal stress of the substrate. The substrate may be a sapphire substrate or an SiC substrate.

09-17-2009

20080308908

Nitride semiconductor device and method for producing nitride semiconductor device - A nitride semiconductor device of the present invention includes: a nitride semiconductor laminated structure comprising an n type first layer, a second layer containing a p type dopant laminated on the first layer, and an n type third layer laminated on the second layer, each layer of the nitride semiconductor laminated structure made of a group III nitride semiconductor, and the nitride semiconductor laminated structure formed with a first trench and a second trench, the first trench penetrating the second layer from the third layer and reaching at least the first layer, and the second trench having a side wall extending from the first, second, to third layers and being different from the first trench; a surface insulating film containing at least silicon nitride formed such that the surface insulating film covers the surface of the first trench; a gate insulating film formed on the side wall of the second trench such that the gate insulating film extends over the first, second, and third layers; and a gate electrode formed such that the gate electrode is opposed to the side wall of the second trench with the gate insulating film sandwiched between the gate electrode and the side wall.

GROUP III NITRIDE COMPOUND SEMICONDUCTOR DEVICE - Disclosed is a group III nitride compound semiconductor device having a substrate, buffer layers on the substrate, and a group III nitride compound semiconductor layer on the top layer of the buffer layers. The buffer layers comprises a first buffer layer formed on the substrate and a second buffer layer formed on the first buffer layer. The first buffer layer is made of transition metal nitride, and the second buffer layer is made of nitride of gallium and a transition metal.

Semiconductor Device - A semiconductor device includes a semiconductor substrate formed of at least two kinds of group III elements and nitrogen, an active layer formed on the semiconductor substrate, and a nitride semiconductor layer formed on a surface of the semiconductor substrate and formed between the semiconductor substrate and the active layer. The nitride semiconductor layer is formed of the same constituent elements of the semiconductor substrate. A composition ratio of the lightest element among the group III elements of the nitride semiconductor layer is higher than a composition ratio of the corresponding element of the semiconductor substrate.

07-09-2009

20080211061

Method For the Fabrication of GaAs/Si and Related Wafer Bonded Virtual Substrates - A method of making a virtual substrate includes providing a device substrate of a first material containing a device layer of a second material different from the first material located over a first side of the device substrate, implanting ions into the device substrate such that a damaged region is formed in the device substrate below the device layer, bonding the device layer to a handle substrate, and separating at least a portion of the device substrate from the device layer bonded to the handle substrate along the damaged region to form a virtual substrate comprising the device layer bonded to the handle substrate.

NON-POLAR III-V NITRIDE SEMICONDUCTOR AND GROWTH METHOD - A method for growing flat, low defect density, and strain-free thick non-polar III-V nitride materials and devices on any suitable foreign substrates using a fabricated nanocolumns compliant layer with an HVPE growth process is provided. The method uses a combination of dry and wet etching to create nanocolumns consisting of layers of non-polar III nitride material and other insulating materials or materials used to grow the non-polar III-V nitride materials.

03-26-2009

20090194848

METHOD FOR MANUFACTURING GALLIUM NITRIDE CRYSTAL AND GALLIUM NITRIDE WAFER - There is provided a method for fabricating a gallium nitride crystal with low dislocation density, high crystallinity, and resistance to cracking during polishing of sliced pieces by growing the gallium nitride crystal using a gallium nitride substrate including dislocation-concentrated regions or inverted-polarity regions as a seed crystal substrate. Growing a gallium nitride crystal

INTEGRATED SEMICONDUCTOR OPTICAL DEVICE - A semiconductor laser (a first semiconductor optical device) and an optical modulator (a second semiconductor optical device) are integrated on the same n-type InP substrate. The semiconductor laser butt-joined to the optical modulator. Each of the semiconductor laser and the optical modulator has a Be-doped p-type InGaAs contact layer. The p-type InGaAs contact layers have a Be-doping concentration of 7×10

Method of manufacturing nitride semiconductor device - A method of manufacturing a nitride semiconductor device includes the steps of: forming a mask of a pattern selectively covering a cutting line on a first major surface of a substrate; forming group III nitride semiconductor layers exposing the mask provided on the cutting line by selectively growing a group III nitride semiconductor from exposed portions of the first major surface of the substrate; forming a division guide groove on the substrate along the cutting line; and dividing the substrate along the division guide groove. The step of forming the division guide groove may be a step of forming the division guide groove by laser processing.

02-19-2009

20080308906

GaN SUBSTRATE, SUBSTRATE WITH EPITAXIAL LAYER, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING GaN SUBSTRATE - A GaN substrate having a large diameter of two inches or more by which a semiconductor device such as a light emitting element with improved characteristics such as luminance efficiency, an operating life and the like can be obtained at low cost industrially, a substrate having an epitaxial layer formed on the GaN substrate, a semiconductor device, and a method of manufacturing the GaN substrate are provided. A GaN substrate has a main surface and contains a low-defect crystal region and a defect concentrated region adjacent to low-defect crystal region. Low-defect crystal region and defect concentrated region extend from the main surface to a back surface positioned on the opposite side of the main surface. A plane direction [0001] is inclined in an off-angle direction with respect to a normal vector of the main surface.

12-18-2008

20080283968

Group III-Nitride Semiconductor Crystal and Manufacturing Method Thereof, and Group III-Nitride Semiconductor Device - A method of manufacturing group III-nitride semiconductor crystal includes the steps of accommodating an alloy containing at least a group III-metal element and an alkali metal element in a reactor, introducing a nitrogen-containing substance in the reactor, dissolving the nitrogen-containing substance in an alloy melt in which the alloy has been melted, and growing group III-nitride semiconductor crystal is provided. The group III-nitride semiconductor crystal attaining a small absorption coefficient and an efficient method of manufacturing the same, as well as a group III-nitride semiconductor device attaining high light emission intensity can thus be provided.

11-20-2008

20080224268

NITRIDE SEMICONDUCTOR SINGLE CRYSTAL SUBSTRATE - To provide a nitride semiconductor single crystal substrate comprising a Si substrate and a nitride semiconductor film which has semi-polar (10-1m) plane (m: natural number) and a thickness of 1 μm or more, the nitride semiconductor single crystal substrate being suitably used for a light-emitting device, the nitride semiconductor single crystal substrate being suitably used for a light-emitting device, this invention provides a nitride semiconductor single crystal substrate comprising a Si substrate having an off-cut angle of 1 to 35° in the <110> direction from the <100> direction, a buffer layer

Method and Apparatus for Growing a Group (III) Metal Nitride Film and a Group (III) Metal Nitride Film - A process and apparatus for growing a group (III) metal nitride film by remote plasma enhanced chemical vapour deposition are described. The process comprises heating an object selected from the group consisting of a substrate and a substrate comprising a buffer layer in a growth chamber to a temperature in the range of from about 400° C. to o about 750° C., producing active neutral nitrogen species in a nitrogen plasma remotely located from the growth chamber and transferring the active neutral nitrogen species to the growth chamber. A reaction mixture is formed in the growth chamber, the reaction mixture containing a species of a group (III) metal that is capable of reacting with the nitrogen species so as to form a group (III) metal nitride film and a film of group (III) s metal nitride is formed on the heated object under conditions whereby the film is suitable for device purposes. Also described is a group (III) metal nitride film which exhibits an oxygen concentration below 1.6 atomic %.

11-06-2008

20090065900

Group III nitride-based compound semiconductor device - A characteristic feature of the invention is to form, in a Group III nitride-based compound semiconductor device, a negative electrode on a surface other than a Ga-polar C-plane. In a Group III nitride-based compound semiconductor light-emitting device, there are formed, on an R-plane sapphire substrate, an n-contact layer, a layer for improving static breakdown voltage, an n-cladding layer made of a multi-layer structure having ten stacked sets of an undoped In

03-12-2009

20080197453

Semiconductor device and manufacturing method of the same - In an MIS-type GaN-FET, a base layer made of a conductive nitride including no oxygen, here, TaN, is provided on a surface layer as a nitride semiconductor layer to cover at least an area of a lower face of a gate insulation film made of Ta

08-21-2008

20080197452

Group III nitride semiconductor substrate - A Group III nitride semiconductor substrate is formed of a Group III nitride single crystal, and has a diameter of not less than 25.4 mm and a thickness of not less than 150 μm. The substrate satisfies that a ratio of Δα/α is not more than 0.1, where α is a thermal expansion coefficient calculated from a temperature change in outside dimension of the substrate, and Δα is a difference (α−αL) between the thermal expansion coefficient α and a thermal expansion coefficient αL calculated from a temperature change in lattice constant of the substrate.