The use of computer-aided prototyping (CAP) with the RPM Emulation System is described. RPM creates a hardware functional prototype from an ASIC or full-custom chip netlist. It reads the chip netlist and then converts the chip design gates into a prototype design. It then synthesizes the prototype design, obtaining the information it needs to configure the reprogrammable hardware, primarily with p...
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A description is given of the Diodes system, a complete rapid prototyping, debugging, and test environment including both hardware and software, for the design of digital-signal-processing chips. The test circuitry in Diodes differs from that in many systems, including those based on boundary scan, by offering full-speed circuit testing and the observation of internal nodes during real time. Diode...
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A description is given of the Mulga symbolic design system, which is based on the virtual-grid concept, a structural approach to symbolic design that extends naturally to a hierarchical design. The relative placement of the circuit elements is determined by their location on the input grid. This grid serves only to delineate the relative topology of the circuit elements and does not correspond to ...
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A description is given of Hyper, a synthesis environment for real-time systems with datapath-intensive architectures. Hyper uses a single, global quality measure throughout the system to drive the exploration of the design space. This approach effectively merges the allocation of hardware, the application of transformations, and the handling of hierarchy in a consistent way. Hyper's modular organi...
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The authors describe the hardware and software of a system for prototyping digital-signal-processing applications by using commercially available digital-signal processors linked to form multiprocessors. The graphical programming environment makes it easier to program, compile, debug, and test DSP algorithms. The system reduces the cost of application prototyping, making it a feasible step at earl...
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A method for testing the interconnections of ordinary static RAMs with a processor that has a boundary-scan register and an IEEE 1149.1 test-access port is described. The method uses an enhanced boundary-scan-register design that manipulates the test-access-port controller states to meet the static RAM's timing constraints. The implementation is more economical than a boundary-scan register that s...
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A deterministic test-pattern-generation algorithm for synchronous sequential circuits is presented. The algorithm, called Essential, takes advantage of a procedure for learning global implications. It uses static and dynamic dominance relationships among signals, the concept of the potential propagation path, and intelligent heuristics to guide and accelerate the decision-making process for determ...
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