bit vectors that represent bytes and words will be of a
type such as std_logic_vector ( 7 down to 0).

Just as in software programming languages, comments
can be included in VHDL code. These are preceded by
two dashes, after which the rest of that line is treated as a
comment line.

The inner workings of the system are given in the
architecture design unit. The architecture is given its own
name (design, here) of the coder’s choice. The
architecture is bracketed between its begin and end
keywords. Before begin, any number of variables and/or
signals can be declared for local use inside the
architecture body (such as the temp_clock signal).

Inside the main architecture body, a special VHDL
construct called process has been used. It can have its
own local variables such as the variable count integer seen
here. A process is essentially a block of code that gets
activated whenever the signal (or signals) that appears in
the bracket after the keyword process change in value
(say, from 0 to 1 or 1 to 0).

These signals are called the sensitivity list of the
process. Here, there is only one signal clock in the
sensitivity list of our process. Each time the clock
transitions from 0 to 1 or vice versa, the code in the
process block operates. If the clock transition is from 0 to
1 (a rising edge), then the lines underneath are executed.

In this part, the value of the variable count is checked.
If it is less than 500, then it is incremented by 1. This
happens for 500 consecutive process activations (500
rising edges of the clock). After 500 times, the else part is
executed once, where the count is reset to 0 and the
value of the signal temp_clock is toggled (1 becomes 0; 0
becomes 1). For 500 rising clock edges of the input clock,
the temp_clock signal remains 0 or 1 and then toggles to
the opposite state for the next 500 time periods of the
clock input. This way, temp_clock becomes a ÷1000
version of clock.

Toward the very end of the process, the
value of temp_clock is assigned to the output
signal new_clock which — from the outside — is
seen as toggling at 1/1000 of the rate of the
input signal clock.

An architecture can have any number of
process blocks — each with its own sensitivity
list of signals. All processes operate in parallel
(concurrently) with each other and thus can be
regarded as separate small components. They
can communicate with each other if needed,
using signals declared in the declarative part of
the architecture (before the architecture’s begin
keyword).

These signals are visible throughout the
architecture (as are signals that appear in the
port list). Note that new signals cannot be
declared inside processes, but variables can be
declared in the declarative part of any process (before the
process begin keyword). Such variables can be used inside
that process alone. These variables retain their values
between process executions and thus can be used for
counting, etc., as illustrated above.

Short and Sweet

Although short, this example shows what VHDL code
looks like, how it is structured, and how it works. Note
that we did not actually describe a conventional counter
based digital design. The VHDL compiler will infer a
counter from this description and implement the net list
for a logic element based counter circuit with signal input
and output called clock and new_clock, respectively. This
code can be compiled by any VHDL compiler to produce
an FPGA configuration file.

It is also possible to actually see the circuit
configuration that will be implemented inside an FPGA. To
do this, one can invoke the schematic viewer built into
HDL compilers. A part of such a schematic layout (not for
the code illustrated here) is shown in Figure 2.

One last thing that needs to be done before the
configuration file is downloaded to the FPGA is to assign
physical pins to the signals declared in the entity’s port. In
the example above, both signals are one bit and thus will
need one I/O pin assigned to each.

The compiler assigns arbitrary pins to port signals
during the compilation process. These can be changed to
the user’s chosen pins after compilation. The code is then
compiled once again so that the new pin assignments get
embedded in the output file. After that, it is a simple
matter of downloading the configuration file over a USB
or Ethernet interface to an FPGA through a JTAG interface.

Once that is done, the FPGA assumes the personality
ascribed to it through the user’s configuration code. From
that point on — unless its configuration is altered — it is