It was only a proof of concept project, you can do nothing really useful with 2MB ram, but it's quite possible to run noMMU linux on this CPU.
It's booting under 1 sec to console.

I wrote a very small bootloader (3kb), the kernel is running XIP from the CPU's internal 2MB flash. DTB is in flash too. Filesystem is
in RAM, it's about 150KB, really just a "one man army" busybox .

It was a fun learning experience (and a few JTAG days).
I'll make a new PCB based on this CPU (the 512KB flash part), with more SDRAM, and serial NOR or serial NAND flash connected to QSPI.
Will be an all TQFP, easy to solder/home made cheap IoT Linux board.
(Also with good documentation of the cpu internals...khm)

I don't suppose you have this code somewhere available on GitHub? I'm having instability problems with SDRAM settings, was wondering what timings and initialization procedure did you use? In the datasheet doesn't say which clock is assigned to SDRAMC.
Best regards,
David.

No, I don't uploaded it to github yet, but if you need I can send my bootloader in PM.
I have a version with a ported memtester linux application also.

There is indeed a 'feature'/bug/etc in the SoC MCK/PLL clock system.
My board is running linux fine for >3 weeks, or running memtester for days without a single failure with 300MHz CPU and 150MHz SDRAM clock, so my SDRAM setup, PCB routing is OK.

But for this, I had to use 150MHz MCK, 300MHz HCLK, AND 600MHz PLL clock.
If I try to generate the MCK and CPU clock from 300MHz PLL, it will generate SDRAM failures
under load withing a few minutes.