Fab Issues At 7nm And 5nm

The race toward the 7nm logic node officially kicked off in July, when IBM Research, GlobalFoundries and Samsung jointly rolled out what the companies claim are the industry’s first 7nm test chips with functional transistors.

They’re not alone, of course. Intel and TSMC also are racing separately to develop 7nm technology. And in the R&D labs, chipmakers also are working on technologies for 5nm and beyond. Needless to say, the timing and certainty of 7nm and 5nm remain unclear.

In any case, there are two basic transistor candidates at 7nm—the finFET and the lateral gate-all-around nanowire FET, sometimes called the lateral nanowire FET. And at 5nm, the industry is leaning towards the lateral nanowire FET.

For 7nm finFETs, chipmakers will need to make the fins taller to boost the drive current. FinFETs will also have new channel materials to boost the mobility.

The second option, the lateral nanowire FET, is basically an evolutionary step from the finFET. “Think of it as finFETs turned on their sides with a gate wrapped all the way around it,” said Michael Chudzik, senior director of strategic planning at Applied Materials. “It increases the gate area, so that you are more effective at turning off the device.”

Nanowire FETs provide better electrostatics than finFETs, but the nanowire FET is more difficult to make in the fab. Still, the finFET and nanowire FET use many of the same process steps. One of the main differences is that nanowire FETs require complex processes on the bottom of the device.

To scale devices down to 7nm and 5nm, the industry will require new breakthroughs. “If you look at the roadmaps, there are so many small and big innovations that are needed,” said An Steegen, senior vice president of process technology at IMEC. “You cannot pin it to one. The fact that EUV is needed is clear. We also need the right ALD materials. The dimensions are so small. So how you basically build the stacks on top of each other is critical. And when you are in the nanometer-scale, you need to have the right metrology.”

To help the industry get ahead of the curve, Semiconductor Engineering has assembled a list of some of the more challenging process steps at 7nm and 5nm.

Patterning and mask making
For 7nm and beyond, patterning is the biggest challenge. ASML Holding, as well as chipmakers, are crossing their fingers, hoping that extreme ultraviolet (EUV) lithography is finally ready by 7nm.

“All of us are waiting for the delivery of EUV,” said Kelvin Low, senior director of foundry marketing at Samsung Semiconductor. “This technology has to be production worthy, with the right uptime of the tools and an economic throughput per day.”

In theory, EUV will simplify the patterning process. With 193nm immersion and multiple patterning, there are 34 lithography steps and 60 metrology steps at 7nm, according to Peter Wennink, president and chief executive of ASML. This compares to just 6 lithography steps and 7 metrology steps for 28nm.

With EUV, there are just 9 lithography steps and 12 metrology steps at 7nm, Wennink said. Even so, chipmakers still will require both EUV and multiple patterning at 7nm and beyond. And ultimately, the decision to put EUV into production depends on the maturity of the power source, mask infrastructure and resists.

Today, the oft-delayed EUV source can generate 80 watts of power. But chipmakers want 250 Watts to bring EUV into mass production. “The source power is there, but it needs to improve,” said Pawitter Mangat, senior manager and deputy director for EUV lithography at GlobalFoundries. “It has to show reliability and availability.”

There are other issues. As the lines become narrower at each node, the industry faces a growing, and problematic, issue called line-edge roughness (LER). Basically, LER is a deviation on the edge of a line. “LER is a linewidth variation,” said Dave Hemker, senior vice president and chief technology officer at Lam Research. “It doesn’t scale with the feature size.”

Meanwhile, as before, lithography is tied to the photomask. At 7nm, photomask makers may need to prepare for both traditional optical and EUV masks.

Optical masks will be complex, and expensive, at 7nm. “Because of the increased demand on the process window for the wafer, the shapes drawn on the masks are becoming smaller and smaller,” said Aki Fujimura, chief executive at D2S. “EUV mask shapes are less complex than ArFi (193nm ArF immersion) at those nodes. But EUV brings other issues on the mask. For example, correction for shadowing and other effects at the wafer level has the potential to explode the mask data volumes. Another example is the mid-range correction that becomes necessary for EUV masks because of the wider dispersion of electrons during the mask-making process as they hit the multi-layer reflective mask.”

Fab flow and variation
Patterning, CMP, deposition, etch and other process steps will be challenging at 7nm and 5nm. Future devices will require structures with thin, precise and conformal films. And chipmakers will continue to grapple with structures that consist of only a finite number of atoms.

“It almost seems like a lot of the technologies are all being worked on in parallel,” said Bob Hollands, director of technical marketing at ASM International (ASMI). “Doing manufacturing with yield, and having reliable devices, will be difficult to do.”

With those factors in mind, chipmakers face a sometimes-overlooked challenge, namely process variation. Variation can be defined as any deviation from an intended goal.

There are various sources of variation in the fab, including within the die, within the wafer, and between one tool chamber and another chamber, according to Harmeet Singh, corporate vice president of dielectric etch products at Lam Research.

“Variation control is really dropping down to the atomic scale,” said Amulya Athayde, senior director of global product management at Applied Materials. “Gate CDU uniformity requirements are in angstroms not nanometers.”

“Basically, most of our processing today is done based on a line-of-sight capability,” said Aaron Thean, vice president of process technologies and director of the logic devices R&D program at Imec. “But soon, you will begin to tunnel through structures and build structures that you can’t see through from the top. So the industry needs to find a way to do selective deposition. Those techniques are somewhat there, but they are not mature enough.”

Chipmakers, R&D organizations and universities are all working on selective deposition. “It’s still in the R&D stage, but it’s approaching reality,” ASMI’s Hollands said.

Materials must also be removed using a related technology called selective removal or atomic layer etch (ALE). ALE is a next-generation plasma etch technology that enables layer-by-layer, or atom-by-atom, etching. “Atomic layer processing is the norm now for many applications,” Lam’s Singh said. “(ALE) allows us to extend the logic roadmap.”

Interconnects
In chip production, the backend-of-the-line (BEOL) is where the Interconnects are formed within a device. Interconnects—those tiny wiring schemes in devices—are becoming more compact at each node, thereby causing a resistance-capacitance (RC) delay in chips.

The BEOL will require new tools and materials. “How can you get more performance out of finFETs? You can make it taller, so that you can get more current through it. But if you make it taller, you may have more resistance-capacitance. The question is can you overcome it,” Imec’s Steegan said.

At 5nm, the problems become worse. “The problem comes in the way the wiring is done in the interconnect. It’s not just in the resistance and capacitance, but how you wire up the transistor. We are seeing a lot of congestion,” Imec’s Thean said.

For that reason, the industry may need to consider an alternative path. “That argument pushes us into doing 3D stacking,” Thean added.

Inspection and metrology
Wafer inspection, the science of finding killer defects in chips, is being stretched to the limit. Optical inspection, the workhorse technology in the fab, is struggling to detect defects at 20nm and below. And e-beam inspection can find tiny defects, but the technology is slow.

So what will happen beyond 10nm? “We still believe (optical inspection) is the way to go,” said Keith Wells, senior vice president and general manager for the WIN Division at KLA-Tencor, in a recent presentation. KLA-Tencor’s optical inspection tools operate at wavelengths down to 190nm. Seeking to capture more defects, the company is working on a sub-190nm wavelength technology, Wells said.

In addition, the industry is working on a next-generation technology called multi-beam e-beam inspection. But this technology might not be ready until 2020. “The exact timing will depend on how quickly the core technology can be scaled in terms of the number of beams and beam current,” said Matt Malloy, a senior technologist at Sematech. Sematech/Zeiss and others are developing multi-beam e-beam inspection technology.

Meanwhile, metrology, the science of measuring structures and films, is another concern. Today’s metrology tools are capable of measuring structures in two dimensions, and in three dimensions to some degree, but that’s not nearly enough for the complexity of current and future devices.

In fact, there is no single metrology system that can measure everything. So, chipmakers must use several different metrology tools in the flow. “As the industry moves to 7nm and 5nm, there will be a drastic decline in the signal-to-noise ratio of the metrology tools. To compensate this uncertainty of measurements from each tool, there will be an even greater need for a multiple metrology approach. This means hybrid metrology is inevitable,” said Keibock Lee, president of Park Systems, a supplier of atomic force microscopy (AFM) tools.

In hybrid metrology, chipmakers use a mix-and-match of several different tool technologies and then combine the data from each. “Hybrid metrology, however, is still in the developing stage,” Lee said.

Mark LaPedus

6 lithography steps and 7 metrology steps for 28nm with 193 nm immersion but 9 lithography steps and 12 metrology steps at 7nm with EUV. Indeed it looks like EUV has already entered the multiple patterning spiral, so it will not present any real benefit for scaling. It would be more practical to make multiple patterning more cost-effective, independent of wavelength.

Scott

The ALE Plasma must be done in batches though, or is there an inline system?