Ferrari, D., and R. Stefanelli. 1969. “Some new schemes for parallel multipliers.”
Alta Frequenza,
vol. 38, pp. 843–852. The original reference for the Ferrari–Stefanelli multiplier. Describes the use of 2-bit and 3-bit submultipliers to generate the product array. Contains tables showing the number of stages and delay for different configurations. [p. 93]

Keutzer, K., S. Malik, and A. Saldanha. 1991. “Is redundancy necessary to reduce delay?”
IEEE Transactions on Computer-Aided Design,
vol. 10, no. 4, pp. 427–435. Describes the carry-skip adder. The paper describes the redundant logic that is added in a carry-skip adder and how to remove it without changing the function or delay of the circuit. [p. 83]