Design and Simulation

PA Core DC Bias

The basic amplifier schematic is shown below and can be found in the circuit design template as BJT Biased for PA.

Component operation:

R1, 2 – base bias current. (Minor collector feedback via R1, but this is only at DC due to C3). Base current is approx. Ib(9-.7)/75k.

C1,C3 – decoupling capacitors

S5 – decoupling inductor (choke) for base

S1 – BFG520 BJT transistor

S2 – Inductor – RF choke

C2, C4 are DC blocking capacitors

V2,3 are vias for our substrate.

PORT 1 – input of amplifier core

PORT 2 – output of oscillator core.

The DC bias conditions for the ampilfier core are shown below:

Collector current is 13.1 mA (not shown) and base current is 100 A.

Note that the voltage on R2 is reduced by approximately 1.3V due to the collector current through R1. This is due to feedback of the bias circuit which reduces the base drive as the collector current increases, thus ensuring that the DC bias current is not too large.

PA Core AC Gain

The following are the components we will use from the template. They have been enabled (Right-mouse Click->Enable) to be visible.

The first step is to measure the linear gain of the PA core.

Create a new schematic, Project -> Add Schematic. Name it “PA Linear.”

Insert the BJTBiased for PA by copying it from the “Components for design” schematic. Make sure it is enabled (right mouse click, then enable). The components on the design schematic are by default disabled (grayed out). Go back to the components schematic and disable the BJT biased for PA to ensure there are no problems during simulation.

Configure as below for AC testing.

Components can be added as follows:

PORT and GND can be added directly from the tool bar at the top of the software (labeled “PORT” and “GND”)

All other elements can be added by Ctrl+L then type the name of the element, e.g. RES or CAP, and you will find it in the list that appears.

You may rotate and flip components by selecting them, then Right-mouse Click->Rotate or Flip

Special components: MVIA1P (special via to ground) must be copied from the Design for Components Schematic in the template provided.

Setup the simulation by going to Options->Project Options->Frequencies and setting the range from 0.5 to 2 GHz in 0.01Ghz steps. Hit Apply and make sure replace is selected.

The measure the gain (S21), both in magnitude and phase. Click Project->Add Graph. Name is something useful, e.g. PA Linear Gain, and make sure Rectangular is selected for the plot type. Once the graph is created, Right Mouse Click->Add New Measurement. The following window will appear:

Ensure that the Data Source Name is the design you want (not All Sources), then select Port Parameters->S then select 2 and 1 from the port indices. Select Mag and dB. Hit Apply.

Also at Gmax which represents the maximum linear gain possible if the core was complex-conjugate matched.

You can simulate your design by clicking the lightening bolt on the top menu (Go to Simulate->Analyze to simulate and see an image of the lightening bolt that also appears on the top menu).

The results are below. You can add a marker by Right Mouse Click->Add Marker.

This shows the gain with 50 Ohm ports at the input/output and also the potential gain (Gmax) if the input/output were bi-conjugate matched. These are for small signal only, however. As soon as we increase the output power, and the amplifier moves into a non-linear regime, the gain and power will be very different.

Performing Load Pull

Unlike small signal (linear) conjugate matching, when the amplifier is operated in a non-linear regime, e.g. Class-AB, the definition of a small signal impedance becomes ill-defined. We no longer ask “what is the output impedance of the amplifier” in order to find a conjugate match (as we would do for a linear amplifier), but rather ask the question: “What load impedance maximizes the output power and/or PAE.”

To answer this question, we run a Load-Pull simulation, which basically tries, systematically, different impedances on the amplifier output and calculates the resulting output power and efficiency. From microwave theory, we find that the output powers and efficiencies will appear on circiles of impedance, such that any impedance on that circle would produce the same power or efficiency. This will become clear when we perform load pull on our circuit.

There is nothing for you to modify or change on the Load Pull Template.

For reference (do not do this step) – the template was created by going to; Scripts->Load Pull->Create Load Pull Template. After this was done, the transistor was changed to the one used in our workshop and the bias current set to the DC currents for our core and supply voltage of 9V.

The load pull template consists of an input and output network with the same functionality. They provide the DC bias points (voltage and current) and then an impedance “tuner”, HBTUNER, that will step through impedance both on the input and output of the transistor. By setting the correct bias condition, we will ensure the transistor is operating in the correct mode, i.e. Class-AB.

The procedure is as follows:

Assume a 50 Ohm source impedance.

Sweep output loads to find optimal power and efficiency

Set output impedance to optimal value.

Measure input impedance

Provide a conjugate input match.

Re-run load pull

Iterate as desired (once is usually enough.)

Run the load pull from the top menu: Scripts->Load Pull->Load_Pull.

The following appears.

Leave selected that it will sweep only the first harmonic of the load and no harmonic of the source. Click the >> to advance the menus.

The following window(s) will appear:

You can select the space over which to sweep the load impedance. It should be set to sweep in Quadrant 2 of the Smith Chart (this quadrant is chosen based on design history with the part). The LP_Gamma_Points shows the impedances that will be swept. Click >> to advance the menus.

The following will appear:

You do not need to make any changes. Click Simulate. Click OK to overwrite any files. Load pull will complete and the following should appear. If not, you can open both from the Project tab on the left. Use View->Tile Vertically to arrange.

Now Analyze (lightening bolt). The Smith Chart on the right will be populated (it was pre-setup in the template file to save you time and errors in setting up).

We can see the constant power and efficiency circles. The markers show the maximum for both efficiency and power. The crosses show the load-pull points. Maximize the Smith Chart window, then double click on the cursor. The following should appear:

Make sure that Denormalized, Impedance and Real/Imaginary are selected. This will give you the real and imaginary impedances in absolute terms. Note r is the real part and x is the imaginary part in the marker label.

The marker label will show you the impedance at the maker. It is not shown here as it is your design choice/goal. The maximum power at this point is approximately 14 dBm (dBm is dB relative to 1 milliWatt.)

You will note in the legend that it says “G_LPCMMAX(Pload,50,0)[m1@Input Power vs. Index,1]. This indicates that the plot is for the input power at power input=index 1. To find out what that power is, simple return to the Load_Pull_Template and look at the input port, PORT_PS1. It sweeps from -10 dBm to 0 dBm in steps of 1 dB. The plot is setup to use the input power marked by a marker on a hidden graph. We have provided an easy way to see this. Go to Project Tab->Graphs-> Input Power vs. Index. The following should appear (we have closed the Load_Pull_Template schematic and tiled the windows vertically).

You can see the cursor M1 on the right. As you move the cursor, you will see the load pull on the left change. This means that the optimal load impedance is dependent on the input power. The loadpull template us set to -5 dBm as the default input power, use this value as your point to optimize.

Return to the PA Linear schematic (not in the load pull template, but rather the first schematic you made). Trick: You can double click the “50 Ohms” in the output port of your AC simulation and enter in the impedance that you found in load pull. Here is an example of entering 100+90*j (not the optimal point).

Also shown is a Smith chart plotting the input impedance (S11). This graph can be added by Project->Add Graph->Smith. You can name it “PA Linear Smith”, then Right-mouse Click->Add Measurement and add an S parameter measurement as before, but select complex on the lower left.

You can now measure the input impedance. For this workshop, we will use a simple conjugate match for the input. In an optimal design, we could reiterate with the new source impedance to find a slightly better load impedance. Or we could do a full source-pull with out load-pull, searching for the best source and load impedance.

We now have a desired load impedance (from load pull) and source impedance (from a linear Smith chart measurement you just did above with the output terminated with the desired load).

Write down now the desired load and source impedance. There is no more optimization of the PA from this point forward, simple creating the desired load and source impedance.

Synthesizing Impedances

Switch to the AWR instance that has the template (not load pull), as it will have the correct layout symbols. This was where you designed PA_Linear.

The next step is to synthesize the desired source and load impedances you determined from above. You should have a number written down from Load Pull for the drain/load impedance and then one for the linear input impedance from the Smith chart for the source.

You want to create these impedances. AWR does not have an imedance synthesis tool/Wizard. It does have a matching wizard, which we can “trick” into synthesizing impedances.

Let us assume you need 100+90j as your load impedance. If you use the AWR Impedance Matching tool (below) it will synthesize a network that is 100-90j if you enter 100+90j as the input. The “trick” is to simply tell it you want the complex conjugate of your target, i.e. use 100-90j (the conjugate of the what you want) as the input to the Impedance Matching tool and it will give you 100+90j as an output network, which is your desired impedance.

AWR has a very easy tool to do this with. Under the Projects tab on the left, find Wizards->iFilter Synthesis. In AWR 13, follow the same direction to the iFilter tool and simply select Matching when offered what type of iFilter you would like to do. In AWR 12, a window will appear to select the filter type. Choose Bandpass and Microstrip (click buttom), then you should see on the left Impedance Matching Network. Click Ok. Both lead to the same dialog box.

This tool synthesizes and impedance matching network, it does not synthesize an impedance, however we can have it do that with a small trick.

We will tell it the complex conjugate of the impedance that we want and then ask it to make an impedance match to 50 Ohms. The input impedance to that network will then be the target impedance we want.

Let’s do an example, as it will make it easier to understand. In our load pull, we found our target impedance for maximum power. For this example, let us use 100+90*j Ohms.

Ensure that the frequency range is 850 to 1050. If not, deselect Auto Freq Range and set those values.

The left side is fixed at 50 Ohms (this is due to the software and our choice of microstrip as our media).

The conjugate of what we want, is 100-90*j, so we will tell the iFilter tool to impedance match to “test load” of 100-90*j.

We will select an SRC load for Z2, since our “test load” is capacitive (negative reactance). You would choose SRL if it was positive positive (inductance).

The real part can be set by inserting the resistance directly.

The imaginary part cannot be set directly, but can be set by adjusting the capacitance (C2) in the window until jXin2 in the table on the right is equal to -90.

See the window below.

Now click Ok.

The following window appears.

If you don’t see this image, check the 4 red boxes and ensure the settings are correct. The red box one on the Smith Chart sub-window shows the layout in the upper right sub-window.

If the layout in the upper left does not look like the image, do the following;.

Click OK on lower left and the following will appear

Click on Design Options and the following should appear

Please make sure that your parameters match the Design Options (including units). Click OK. You are now back in the window before. Click Matching Network on the upper left, and you should see the correct layout in your matching window

The iFilter tool has generated a transmission line and stub (open) impedance transformer that will match our “target” impedance of 100-90*j to 50 Ohms. To do this, it must present 100+90*j Ohm to our “target load”. I have added the impedance as seen looking into the network on both sides (assuming a “target load” of 100-90*j Ohms is connected on the right side). Note that the spatial context, i.e. 50 Ohms on left, “target impedance” on right, is implicit in the layout. The red arrows simply make it explicit for our tutorial.

The bottom red box highlights that the tool will generate the network out of 50 Ohm transmission lines. This is useful, as your feedlines and interconnect for RF signals will be 50 Ohms, so will connect directly to the network.

Now click Ok.

The following window appears. We have selected the layout view on the bottom sub-window by clicking the same button icon as above.

You must also click on the Real button to ensure that it will generate a microstrip design (as opposed to a transmission line electrical equivalent).

Click Generate Design

The following window will appear. Unselect all check boxes except those noted. You should also enter a name for your synthesis network.

Click Ok.

A schematic will appear as shown below.

The tool has synthesized a microstrip design with all dimensions for you. You need to make two changes before continuing.

Change the PORT_TN to PORT

Disable the MSUB block (Right-mouse Click->enable/disable).

We will now test our synthesized network and illustrate its final function. Create a new schematic called “Test Zsynth_one_network.” Add the network you just created by navigating to the following Subcircuits window in the Elements tab on the left.

You will see that your network has been added as “Zsynth_one_network” (Hint: call your Zsynth_Load or Zsynth_Source, to remind you which network it is for future). A good feature of AWR is it automatically creates a subcircuit symbol for every schematic. You can simply drag and drop it into your new schematic. Add 50 Ohm ports to the left and right.

Now, if you recall, Port 1, the left side was always the 50 Ohm. The right side, Port 2, was the one connected to the “test load”. Plot the S11 and S22 of the network on a Smith Chart.

You will note that S22, looking into the port we are trying to synthesize the impedance of 100+90*j, we see 113+58*j. This is very close (on the Smith Chart) to our desired impedance (in this region of the Smith chart it is difficult to get an exact match). This is the desired impedance synthesis looking into Port 2.

You should also note that the input impedance, S11, is not 50 Ohms. Why? Recall, the iFilter is trying to impedance match 50 Ohms to the “target load”. In the test schematic above, both ports are 50 Ohm. If you change Port 2 to 100=90*j, you will see S11 is a close match to 50 Ohms (42.7 Ohms).

Finally, click on your schematic, and View->View Layout. The tool has laidout your network for you.

Repeat this procedure for your specific source and load impedances you wrote down earlier. Load was found from loadpull and source impedance from a linear S11 measurement with the PA terminated by the Load-Pull optimal impedance.

The left side is always 50 Ohm, and the right side is the synthesized impedance, due to the convention of iFilter.

Make sure to test in simulation both the source and load impedances to see they are correct.

Remember:

Port 1, Pin 1 set to 50 Ohms

Port 2, Pin 2 is synthesized impedance

Amplifier Design

Assemble the following schematic. Note that we have named the source and load networks by name for ease of reference. Also, note that Port 2 is the synthesized impedance for both the source and load. The load network needs to be flipped (Right-mouse Click->flip) so that Port 2 faces the PA.

You can plot the gain (S21) and Gmax.

We can see that for small signals we are also well matched. To measure the output power, create a new schematic (call it Nonlinear PA 2) as below:

We have just changed the input port to PORT_PS1 and set the input power sweep to -20 dBm to 10 dBm. From the top menu, Options->Project Options->Frequency set to a single point at 0.95 Mhz.

Insert a graph with the following measurement. Ensure that the Data Source Name is correct and the Sweep Freq and PORT_1 setting (you may need to scroll up to see Use for x-axis).

Simulate using the lightening bolt. The following is an example of the ouput.

At -5 dBm input power, the output is around 12 dBm, as expected from our load pull. In addition, we can see that the power amplifier saturates much above 12 dBm output power.

To prepare for layout, add 10mm long lines to the 50 Ohm ports, using MLIN components (Ctr+L, MLIN). These are used to extend the circuit to the board edge and to allow your connectors to be soldered on. The length is 10 mm and the width is equal to the width of the 50 Ohm lines in your impedance synthesis networks. You can see the networks through the Project Tab on the left or Right-mouse Click-> Edit Subcircuit. A blue arrows shows you will descend. That same arrow is on the top menu for future use.

Layout

While in the schematic you just added the 10 mm MLIN to, go to View-View Layout. The following will appear.

You will see that the BJT core is already laidout and so are the impedance synthesis network. To complete the layout, Ctrl+A, to select all, then Edit-> Snap Together. Since there is only one logical arrangement of the subcicuits, AWR is able to assemble the layout for you, see below.

It is desirable to have both stubbs point in the same direction (for space savings). You can flip the output impedance synthesis network and use the Snap Together sequence and you will have your final layout.

Fabrication

To prepare your design for fabrication, please follow the following steps:

Add your name or initials to the design. Ctrl+T, enter text, then hit return. Make sure they are away from the circuit, but do not increase the area of the design (find an empty spot to put them in).

Right mouse click on the letters and Shape Properties -> Layout->Draw Layers select Copper Top. This will add it to the copper layer.

You can adjust the shape in the properties windows of each piece of text. We have added VDD and GND for reference.

Go to the Layout tab on the left. On the bottom are radio buttons to turn on/off visibility of layers. Turn off everything, except top copper.

Go to the Layout tab again, under Layout Setup->Default, the following window will appear

You will need to double click the Line and Fill for CopperTop and change the color to black. This is so when we print the layout, we get the darkest toner/color for our etching mask. Note the top of the pop-up box is for the line type or pattern, the bottom is the color. In the below “Solid” is selected as the pattern and the color “Black” at the bottom is selected.

The layout now looks like this

Now hit Ctrl+A to select all, then Ctrl-F (Also found in Edit menu) to flip. The cursor will change to ask you around which axis to flip. Left mouse click then move mouse up and you will see the layout flip around the vertical axis. It should look like this.

You will know its correct if the words are backwards! The amplifier will not work if you do not flip it (the fabrication process will flip it back to its original layout).

Now export the file, Layout->Export-> set save as type as (DXF, Flat,*.dxf)

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Go to the section/booklet on Fabrication

Assembly

The layout with components values is shown below. You can find the components from the color-coded sheet in your kit. Note there is a unique identified for each component, which includes a combination of: Number of components in kit, package style, number of pins, shape of pins, and finally color on packaging.

The assembly of the ports is easy, just solder on an SMA connector. For the amplifier core, the following will assist assembly.