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Abstract

Scalability of bus-based Symmetrical MultiProcessor (SMP) systems is often limited by the electrical characteristics of the bus itself. As the number of CPUs which attach to the bus grow, so does the loading and wire lengths, degrading the maximum frequency of operation. One solution is to convert to a switch-based system. Typically, the advantage of this approach is higher frequency operation due to electrically superior interconnection. This approach however often results in larger latencies and higher cost. This disclosure describes a method to improve the electrical characteristics of a SMP data bus with a relatively low latency solution.

Country

United States

Language

English (United States)

This text was extracted from an ASCII text file.

This is the abbreviated version, containing approximately
52% of the total text.

Scalability
of bus-based Symmetrical MultiProcessor (SMP)
systems is often limited by the electrical characteristics of the bus
itself. As the number of CPUs which
attach to the bus grow, so does
the loading and wire lengths, degrading the maximum frequency of
operation. One solution is to convert to
a switch-based system.
Typically, the advantage of this approach is higher frequency
operation due to electrically superior interconnection. This
approach however often results in larger latencies and higher cost.
This disclosure describes a method to improve the electrical
characteristics of a SMP data bus with a relatively low latency
solution.

A data re-broadcast
approach is used to allow the addition
of processors and/or memory without degrading the bus frequency. The
data bus is split electrically into two buses via one or more Data
reBroadcast Chips (DCB). These are
essentially latching transceiver
chips with finite state machines to control the tristate drivers.
Each half of the data bus can support some maximum number of CPUS,
operating at the desired frequency, which is higher than that which
could otherwise be attained with all CPUs residing on the same bus.
The two buses behave logically as one, except there is a one cycle
delay between them. Additional bandwidth
is attained at the expense
of one additional cycle of latency.

Though the
solution is given for a SMP system comprised of
PowerPC CPUs connected via the 6XX system bus, the concept can be
applied to other bus based SMP systems as well.

Fig. 1 shows
an 8-way PowerPC SMP system. It is
comprised of
two CPU cards, each with 2 PowerPC CPUs with L2 cache, 4 memory
cards, a memory/bus controller, and the DCB.
The DCB chip splits the
data bus into two physical buses, bus a and bus b. Each bus supports
2 CPU cards. Data transfers on bus a
appear on bus b one cycle
later, and vice-versa. Transfers
initiated and serviced on the same
bus pay no latency and bandwidth penalty.
However, transfers
initiated from one bus and serviced from another pay a 1 cycle
latency penalty. Additionally, there is
a bandwidth penalty when the
bus direction swi...