Here is the abstract you requested from the IMAPS_2012 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Silicon interposer minimizes CTE mismatch between the chip and copper filled TSV interposer resulting in high reliability micro bumps. Furthermore, providing high wiring density interconnections and improved electrical performance are the reasons TSV interposer has emerged as a good solution and getting too much industry attention.
Several DOEs and design/material optimizations were performed in order to yield high aspect ratio void-free TSV copper via and reliable micro-bumps. This paper presents the package overview of multiple 28nm chips stacked on a TSV interposer in addition to a SERDES die. In addition, pre-conditioning, EM, u-HAST, HTS and thermal-cycling measurements are presented to insure reliability of the design and the material selected for the 28nm technology TSV interposer FPGA/SERDES system.
Several DOEs have been constructed to optimize thermal interface material selection, underfill material selection and to confirm that the FPGA/SERDES package is thermally reliable.