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 AM LaCASALaCASA 3 Shift in Applications Area Desktop Computing – emphasizes performance of programs with integer and floating point data types; little regard for program size or processor power Servers - used primarily for database, file server, and web applications; FP performance is much less important for performance than integers and strings Embedded applications value cost and power, so code size is important because less memory is both cheaper and lower power DSPs and media processors, which can be used in embedded applications, emphasize real-time performance and often deal with infinite, continuous streams of data Architects of these machines traditionally identify a small number of key kernels that are critical to success, and hence are often supplied by the manufacturer.

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 AM LaCASALaCASA 5 Classifying ISA Stack Architectures - operands are implicitly on the top of the stack Accumulator Architectures - one operand is implicitly accumulator General-Purpose Register Architectures - only explicit operands, either registers or memory locations register-memory: access memory as part of any instruction register-register: access memory only with load and store instructions

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 AM LaCASALaCASA 8 Development of ISA Early computers used stack or accumulator architectures accumulator architecture easy to build stack architecture closely matches expression evaluation algorithms (without optimisations!) GPR architectures dominate from 1975 registers are faster than memory registers are easier for a compiler to use hold variables memory traffic is reduced, and the program speedups code density is increased (registers are named with fewer bits than memory locations)

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 AM LaCASALaCASA 9 Programming Registers Ideally, use of GPRs should be orthogonal; i.e., any register can be used as any operand with any instruction May be difficult to implement; some CPUs compromise by limiting use of some registers How many registers? PDP-11: 8; some reserved (e.g., PC, SP); only a few left, typically used for expression evaluation VAX 11/780: 16; some reserved (e.g., PC, SP, FP); enough left to keep some variables in registers RISC: 32; can keep many variables in registers

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 AM LaCASALaCASA 10 Operand Access Number of operands 3; instruction specifies result and 2 source operands 2; one of the operands is both a source and a result How many of the operands may be memory addresses in ALU instructions? Number of memory addresses Maximum number of operands Examples 03SPARC, MIPS, HP-PA, PowerPC, Alpha, ARM, Trimedia 12Intel 80x86, Motorola 68000, TI TMS320C54 2/3 VAX

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 AM LaCASALaCASA 11 Operand Access: Comparison TypeAdvantagesDisadvantages Reg-Reg (0-3) Simple, fixed length instruction encoding. Simple code generation. Instructions take similar number of clocks to execute. Higher inst. count. Some instructions are short and bit encoding may be wasteful. Reg-Mem (1,2) Data can be accessed without loading first. Instruction format tends to be easy to decode and yields good density. Source operand is destroyed in a binary operation. Clocks per instruction varies by operand location. Mem- Mem (3,3) Most compact.Large variation in instruction size and clocks per instructions. Memory bottleneck.

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 AM LaCASALaCASA 23 Operations for Media and Signal Processing Multimedia processing and limits of human perception use narrower data words (don’t need 64b fp) => wide ALU’s operate on several data items at the same time partition add – e.g., perform four 16-bit adds on a 64-bit ALU SIMD – Single instruction Multiple Data or vector instructions (see Appendix F) Figure 2.17 (page 110) DSP processors algorithms often need saturating arithmetic if result too large to be represented, it is set to the largest representable number often need several rounding modes MAC (Multiply and Accumulate) instructions

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 AM LaCASALaCASA 26 Encoding an Instruction Set Instruction set architect must choose how to represent instructions in machine code Operation is specified in one field called Opcode Each operand is specified by a separate Address specifier (tells which addressing modes is used) Balance among Many registers and addressing modes adds to richness Many registers and addressing modes increase code size Lengths of code objects should "match" architecture; e.g., 16 or 32 bits