I checked a MOSFET data sheet and it seemed like the rise and fall times were included in the turn-on and turn-off times. There was a diagram which showed the turn-on, turn-off times clearly overlapping the rise time and fall time.

So, you would not have to include these.
On your figures, I get about 41.66 MHz.

Doing this would result in seriously degraded pulses.

This calculation does not give you an ultimate upper frequency of the FET, though.
If the FET was used for small signals, the full rise or fall times would not be used like they are for pulse switching

Switching time of MOSFET are based on the drive condition SPECIFIED in the data sheet, nothing more. The major problem with driving MOSFET is the input capacitance and the Miller capacitance you have to overcome. If you have a stronger, lower impedance driver than the specification, you CAN make it faster. I did so many of the MOSFET pulsing circuit with sub nano second rise time and fall time and various delays. It is all about the drivers. I designed a very precise turn on time of a N-MOSFET by using a P-MOSFET to pull the gate up STRONG and I get such a fast rise time and short propagation delay it's incredible. It was way less than 1nS transition time using a medium size MOSFET that can pulse like an amp or more for 100V......Yes, no typo 100V. To do that, I used a strong MOS driver......Two in parallel to drive the P-MOSFET....to drive the N-MOSFET!!!! All the speed concentrated on that one edge, the rise time.

It is all about the drive.

This is true inside a CMOS IC. That's the reason people get processor speed to 3 or 4 GHz speed. The FETs inside are very very tiny, gate capacitance is so low. They don't take much drive to switch the gate, that's the reason they achieve the fast switching time and short prop delay. But why are the external I/O pins so slow? Because in order to have any drive to drive the external circuits with parasitic capacitance, they need strong drivers at the I/O pins. Most end up doing multiple stages of what I did..........a small FET drive a little bigger FET, then the little bigger FET drive the intermediate FET......so on and the last stage have big enough FET to drive the I/O.

This is the name of the game. At least this is absolute true at the time I was in the field.