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Dave KelfDave Kelf heads OneSpin’s marketing efforts and services as vice president of marketing. Previously, he was president and CEO of Sigmatix, Inc. He worked in sales and marketing at Cadence Design Systems, and was responsible for the Verilog and VHDL verification product line. As vice president of marketing at Co-Design Automation and then Synopsys, Kelf oversaw the successful introduction and growth of the SystemVerilog language, before running marketing for Novas Software, which became Springsoft (now Synopsys). He holds a Master of Science degree in Microelectronics and an MBA from Boston University. « Less

Dave KelfDave Kelf heads OneSpin’s marketing efforts and services as vice president of marketing. Previously, he was president and CEO of Sigmatix, Inc. He worked in sales and marketing at Cadence Design Systems, and was responsible for the Verilog and VHDL verification product line. As vice president of … More »

DVCon Europe: European Practicality With International Relevance

On November 11th and 12th, DVCon Europe will once again take place in the lovely city of Munich. The inaugural event last year demonstrated a clear need for this event in Europe, with a focus on practical information that allowed the attendees to get a rapid, all-encompassing update on a broad range of design and verification techniques. Furthermore, it also showed the international audience those areas where Europe leads, influencing EDA development and thinking on a global basis.

This year’s show promises an even bigger and better program. It is expected to grow significantly, and indeed, early registrations, the size of the exhibit, and the number of papers and tutorials all bear this out. The theme of the conference, focused on the predominantly European automotive semiconductor segment, acts as a driver for next-generation design and verification across the entire industry, given the absolute reliability requirements of these devices. Subject areas, including system-level abstraction, analog/mixed-signal devices, UVM and other advanced verification, will all be discussed during a number of networking opportunities including a Gala dinner, included as part of the registration.

On the tutorial-focused first day, attendees can chose from fifteen 90-minute lectures and a panel, with time allowed to attend four informative sessions back to back. Delivered by world-class speakers, the tutorials cover such topics as:

Basic UVM, advanced UVM, UVM reuse, all things UVM

Safety-critical and security design & verification

Communication protocol development

Analog/mixed–signal systems

The latest assertion-based verification techniques

Advanced debug

FPGA debug and rapid prototyping

System-level design techniques, including SystemC

The latest work on standards from Accellera

A panel of experts in different verification areas discussing the next advances

Whether you are trying to advance your UVM or formal verification environments, learn the latest design techniques for high reliability devices, leverage various system abstractions, or simply improve overall skills and understanding, this is the practical show for you. A note to managers: in one day your engineers can get an update on the latest techniques that are hard to cover in even multiple training courses.

Building on the success of last year’s inaugural conference, the sessions this year are impressive. Twenty-six papers and ten posters on the second day cover a full range of subjects, hitting on the major challenges facing many development teams. As the General Chair for the conference, Martin Barnasconi of NXP noted, “The reason we hold DVCon in Europe is because of the differences in the local community to other regions. We have our own competence areas and application domains. We are quite strong in the system-level space and in mixed-signal. And we are reflecting that back on issues in verification.”

One addition to the program this year is a gala dinner on Wednesday evening. Included as part of the standard registration, this event will provide an international networking opportunity over a delightful European menu. Meet your peers in companies across Europe and enjoy a relaxed evening of good food and fine wine.

The technical sessions at DVCon Europe will present dozens of new ideas, applications and methodologies to help design and verification engineers do their jobs better and faster. In many cases, commercial solutions can help accelerate the adoption of these new approaches. DVCon Europe 2015 features a 25-company exhibition with knowledgeable staff, from EDA companies, consulting and training partners, and IP vendors large and small:

DVCon US, India and Europe are known for the valuable and meaningful insights they provide for real engineers and real projects. This conference has excelled in providing the right information in a practical manner, while still retaining that European flavor and flair. Stay up-to-date with the latest techniques, tools, and advances in modern EDA. Registration options are flexible, so you can take a quick peek on one day or take in the whole conference and dinner — it’s up to you. In the words of the conference chair “if you are keen on networking, learning and sharing design and verification practices, then DVCon Europe is the place-to-be.” Space is filling up, so please register now.