With these points in mind CPLD is normally good for control applications and
logic soaking, FPGA is good for complex designs rich in register
utilisation.

<> wrote in message
news:...
> Hi i am new VLSI technology.
> can anybody suggest me the criteria for choosing FPGA/CPLD for design.
> which parameters play imp role in distingwishing them?
> any guidline for that.
>

CPLD can be used in low gate count designs and FPGAs for more complex
ones. CPLD is mainly for Glue logic small controllers and others that
does not require much gates. FPGA can be used for complex algorithm
implementation and we can even implements RAMs. And more over FPGAs are
available with different cores now-a-days.

wrote:
> Hi i am new VLSI technology.
> can anybody suggest me the criteria for choosing FPGA/CPLD for design.
> which parameters play imp role in distingwishing them?
> any guidline for that.
>
Most CPLDs have one flipflop per package signal pin.
So if your design needs more flipflops than there are signal pins in the
package, it's a done deal: FPGA.

Matt North schrieb:
> They way i distinguish between the two is:
>
> CPLD
> -Instant On
> -Non-volatile

Also valid for some FPGA famillies.
> -Reconfigurable*

? Same as FPGA ?
> -Fixed Path Delays
> -Low/Medium size.

Also true for small FPGAs *g*
> FPGA
> -Setup Time
> -Volatile

Only true for some FPGAs
> -Reconfigurable
> -Good for large designs.
>
> With these points in mind CPLD is normally good for control applications and
> logic soaking, FPGA is good for complex designs rich in register
> utilisation.

Nowadays its hard to distinguish between CPLD and FPGA because naming a
device CPLD or FPGA is more marketing than anything else.

Traditional CPLDs have siginifcant less registers and are very limited
in routing pathes, but provide a good timing for each path. FPGAs
provide more registers and are totaly flexible in interconnecting logic
and registers while having longer routing delays [1].

bye Thomas

[1] for compareable technology. Don't expect a 0.5um CPLD to reach the
timing of a Virtex4.

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