Question

I needed help with 5.13.3

Show transcribed image textUnder what scenarios would entry 2s valid bit be set to zero? What happens when an instruction writes to VA page 30? When would a software managed TLB be faster than a hardware managed TLB? What happens when an instruction writes to VA page 200? In this exercise, we will examine how replacement policies impact miss rate. Assume a 2-way set associative cache with 4 blocks. To solve the problems in this exercise, you may find it helpful to draw a table like the one below, as demonstrated for the address sequence "o, 1, 2, 3, 4." Consider the following address sequence: o, 2, 4, 8,10,12,14,16, o Assuming an LRU replacement policy, how many hits does this address sequence exhibit? Assuming an MRU (most recently used) replacement policy, how many hits does this address sequence exhibit? Simulate a random replacement policy by flipping a coin. For example, "heads" means to evict the first block in a set and "tails" means to evict the second block in a set. How many hits does this address sequence exhibit? Which address should be evicted at each