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XC4000E and XC4000X Series Field

Programmable Gate Arrays

May 14, 1999 (Version 1.6)

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XC4000E and XC4000X Series

FeaturesNote: Information in this data sheet covers the XC4000E,XC4000EX, and XC4000XL families. A separate data sheetcovers the XC4000XLA and XC4000XV families. ElectricalSpecifications and package/pin information are covered inseparate sections for each family to make the informationeasier to access, review, and print. For access to these sections, see the Xilinx web site athttp://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000E and XC4000X Series

Compared to the XC4000For readers already familiar with the XC4000 family of Xilinx Field Programmable Gate Arrays, the major new features in the XC4000 Series devices are listed in thissection. The biggest advantages of XC4000E andXC4000X devices are significantly increased systemspeed, greater capacity, and new architectural features,particularly Select-RAM memory. The XC4000X devicesalso offer many new routing features, including specialhigh-speed clock buffers that can be used to capture inputdata with minimal delay.Any XC4000E device is pinout- and bitstream-compatiblewith the corresponding XC4000 device. An existingXC4000 bitstream can be used to program an XC4000Edevice. However, since the XC4000E includes many newfeatures, an XC4000E bitstream cannot be loaded into anXC4000 device.XC4000X Series devices are not bitstream-compatible withequivalent array size devices in the XC4000 or XC4000Efamilies. However, equivalent array size devices, such asthe XC4025, XC4025E, XC4028EX, and XC4028XL, arepinout-compatible.

Improvements in XC4000E and XC4000X

Increased System SpeedXC4000E and XC4000X devices can run at synchronoussystem clock rates of up to 80 MHz, and internal performance can exceed 150 MHz. This increase in performanceover the previous families stems from improvements in bothdevice processing and system architecture.XC4000Series devices use a sub-micron multi-layer metal process.In addition, many architectural improvements have beenmade, as described below.The XC4000XL family is a high performance 3.3V familybased on 0.35 SRAM technology and supports systemspeeds to 80 MHz.

PCI ComplianceXC4000 Series -2 and faster speed grades are fully PCIcompliant. XC4000E and XC4000X devices can be used toimplement a one-chip PCI solution.

Carry LogicThe speed of the carry logic chain has increased dramatically. Some parameters, such as the delay on the carrychain through a single CLB (TBYP), have improved by as

May 14, 1999 (Version 1.6)

much as 50% from XC4000 values. See Fast Carry Logic

on page 18 for more information.

Select-RAM Memory: Edge-Triggered, Synchronous RAM Modes

The RAM in any CLB can be configured for synchronous,edge-triggered, write operation. The read operation is notaffected by this change to an edge-triggered write.

Configurable RAM Content

The RAM content can now be loaded at configuration time,so that the RAM starts up with user-defined data.

H Function GeneratorIn current XC4000 Series devices, the H function generatoris more versatile than in the original XC4000. Its inputs cancome not only from the F and G function generators butalso from up to three of the four control input lines. The Hfunction generator can thus be totally or partially independent of the other two function generators, increasing themaximum capacity of the device.

IOB Clock Enable

The two flip-flops in each IOB have a common clock enableinput, which through configuration can be activated individually for the input or output flip-flop or both. This clockenable operates exactly like the EC pin on the XC4000CLB. This new feature makes the IOBs more versatile, andavoids the need for clock gating.

Output DriversThe output pull-up structure defaults to a TTL-liketotem-pole. This driver is an n-channel pull-up transistor,pulling to a voltage one transistor threshold below Vcc, justlike the XC4000 family outputs. Alternatively, XC4000Series devices can be globally configured with CMOS outputs, with p-channel pull-up transistors pulling to Vcc. Also,the configurable pull-up resistor in the XC4000 Series is ap-channel transistor that pulls to Vcc, whereas in the original XC4000 family it is an n-channel transistor that pulls toa voltage one transistor threshold below Vcc.

* Max values of Typical Gate Range include 20-30% of CLBs used as RAM.

Note: All functionality in low-voltage families is the same as

in the corresponding 5-Volt family, except where numericalreferences are made to timing or power.

DescriptionXC4000 Series devices are implemented with a regular,flexible, programmable architecture of Configurable LogicBlocks (CLBs), interconnected by a powerful hierarchy ofversatile routing resources, and surrounded by a perimeterof programmable Input/Output Blocks (IOBs). They havegenerous routing resources to accommodate the mostcomplex interconnect patterns.The devices are customized by loading configuration datainto internal memory cells. The FPGA can either activelyread its configuration data from an external serial orbyte-parallel PROM (master modes), or the configurationdata can be written into the FPGA from an external device(slave and peripheral modes).XC4000 Series FPGAs are supported by powerful andsophisticated software, covering every aspect of designfrom schematic or behavioral entry, floor planning, simulation, automatic block placement and routing of interconnects, to the creation, downloading, and readback of theconfiguration bit stream.Because Xilinx FPGAs can be reprogrammed an unlimitednumber of times, they can be used in innovative designs

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where hardware is changed dynamically, or where hardware must be adapted to different user applications.FPGAs are ideal for shortening design and developmentcycles, and also offer a cost-effective solution for production rates well beyond 5,000 systems per month.n

Taking Advantage of Re-configuration

FPGA devices can be re-configured to change logic function while resident in the system. This capability gives thesystem designer a new degree of freedom not availablewith any other type of logic.Hardware can be changed as easily as software. Designupdates or modifications are easy, and can be made toproducts already in the field. An FPGA can even be re-configured dynamically to perform different functions at different times.Re-configurable logic can be used to implement systemself-diagnostics, create systems capable of being re-configured for different environments or operations, or implement multi-purpose hardware for a given application. As anadded benefit, using re-configurable FPGA devices simplifies hardware design and debugging and shortens producttime-to-market.

May 14, 1999 (Version 1.6)

XC4000E and XC4000X Series Field Programmable Gate Arrays

Input Thresholds

Additional Improvements in XC4000X Only

The input thresholds of 5V devices can be globally configured for either TTL (1.2 V threshold) or CMOS (2.5 Vthreshold), just like XC2000 and XC3000 inputs. The twoglobal adjustments of input threshold and output level areindependent of each other. The XC4000XL family has aninput threshold of 1.6V, compatible with both 3.3V CMOSand TTL levels.

Increased Routing

Global Signal Access to Logic

There is additional access from global clocks to the F andG function generator inputs.

Configuration Pin Pull-Up Resistors

During configuration, these pins have weak pull-up resistors. For the most popular configuration mode, SlaveSerial, the mode pins can thus be left unconnected. Thethree mode inputs can be individually configured with orwithout weak pull-up or pull-down resistors. A pull-downresistor value of 4.7 k is recommended.The three mode inputs can be individually configured withor without weak pull-up or pull-down resistors after configuration.

New interconnect in the XC4000X includes twenty-two

additional vertical lines in each column of CLBs and twelvenew horizontal lines in each row of CLBs. The twelve QuadLines in each CLB row and column include optional repowering buffers for maximum speed. Additional high-performance routing near the IOBs enhances pin flexibility.

Faster Input and Output

A fast, dedicated early clock sourced by global clock buffersis available for the IOBs. To ensure synchronization with theregular global clocks, a Fast Capture latch driven by theearly clock is available. The input data can be initiallyloaded into the Fast Capture latch with the early clock, thentransferred to the input flip-flop or latch with the low-skewglobal clock. A programmable delay on the input can beused to avoid hold-time requirements. See IOB Input Signals on page 20 for more information.

Latch Capability in CLBs

The PROGRAM input pin has a permanent weak pull-up.

Storage elements in the XC4000X CLB can be configured

as either flip-flops or latches. This capability makes theFPGA highly synthesis-compatible.

Soft Start-up

IOB Output MUX From Output Clock

Like the XC3000A, XC4000 Series devices have Soft

Start-up. When the configuration process is finished andthe device starts up, the first activation of the outputs isautomatically slew-rate limited. This feature avoids potential ground bounce when all outputs are turned on simultaneously. Immediately after start-up, the slew rate of theindividual outputs is, as in the XC4000 family, determinedby the individual configuration option.

A multiplexer in the IOB allows the output clock to select

either the output data or the IOB clock enable as the outputto the pad. Thus, two different data signals can share a single output pad, effectively doubling the number of deviceoutputs without requiring a larger, more expensive package. This multiplexer can also be configured as anAND-gate to implement a very fast pin-to-pin path. SeeIOB Output Signals on page 23 for more information.

XC4000 and XC4000A Compatibility

Additional Address Bits

Existing XC4000 bitstreams can be used to configure an

XC4000E device. XC4000A bitstreams must be recompiledfor use with the XC4000E due to improved routingresources, although the devices are pin-for-pin compatible.

Larger devices require more bits of configuration data. A

daisy chain of several large XC4000X devices may requirea PROM that cannot be addressed by the eighteen addressbits supported in the XC4000E. The XC4000X Seriestherefore extends the addressing in Master Parallel configuration mode to 22 bits.

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May 14, 1999 (Version 1.6)

XC4000E and XC4000X Series Field Programmable Gate Arrays

Detailed Functional Description

XC4000 Series devices achieve high speed throughadvanced semiconductor technology and improved architecture. The XC4000E and XC4000X support system clockrates of up to 80 MHz and internal performance in excessof 150 MHz. Compared to older Xilinx FPGA families,XC4000 Series devices are more powerful. They offeron-chip edge-triggered and dual-port RAM, clock enableson I/O flip-flops, and wide-input decoders. They are moreversatile in many applications, especially those involvingRAM. Design cycles are faster due to a combination ofincreased routing resources and more sophisticated software.

Basic Building Blocks

CLBs provide the functional elements for constructing

the users logic.IOBs provide the interface between the package pinsand internal signal lines.

Three other types of circuits are also available:

3-State buffers (TBUFs) driving horizontal longlines are

associated with each CLB.Wide edge decoders are available around the peripheryof each device.An on-chip oscillator is provided.

Programmable interconnect resources provide routing

paths to connect the inputs and outputs of these configurable elements to the appropriate networks.The functionality of each circuit block is customized duringconfiguration by programming internal static memory cells.The values stored in these memory cells determine thelogic functions and interconnections implemented in theFPGA. Each of these available circuits is described in thissection.

Configurable Logic Blocks (CLBs)

Configurable Logic Blocks implement most of the logic inan FPGA. The principal CLB elements are shown inFigure 1. Two 4-input function generators (F and G) offerunrestricted versatility. Most combinatorial logic functionsneed four or fewer inputs. However, a third function generator (H) is provided. The H function generator has threeinputs. Either zero, one, or two of these inputs can be theoutputs of F and G; the other input(s) are from outside theCLB. The CLB can, therefore, implement certain functionsof up to nine variables, like parity check or expandable-identity comparison of two sets of four inputs.

Each CLB contains two storage elements that can be used

to store the function generator outputs. However, the storage elements and function generators can also be usedindependently. These storage elements can be configuredas flip-flops in both XC4000E and XC4000X devices; in theXC4000X they can optionally be configured as latches. DINcan be used as a direct input to either of the two storageelements. H1 can drive the other through the H functiongenerator. Function generator outputs can also drive twooutputs independent of the storage element outputs. Thisversatility increases logic capacity and simplifies routing.Thirteen CLB inputs and four CLB outputs provide accessto the function generators and storage elements. Theseinputs and outputs connect to the programmable interconnect resources outside the block.

Function GeneratorsFour independent inputs are provided to each of two function generators (F1 - F4 and G1 - G4). These function generators, with outputs labeled F and G, are each capable ofimplementing any arbitrarily defined Boolean function offour inputs. The function generators are implemented asmemory look-up tables. The propagation delay is thereforeindependent of the function implemented.A third function generator, labeled H, can implement anyBoolean function of its three inputs. Two of these inputs canoptionally be the F and G functional generator outputs.Alternatively, one or both of these inputs can come fromoutside the CLB (H2, H0). The third input must come fromoutside the block (H1).Signals from the function generators can exit the CLB ontwo outputs. F or H can be connected to the X output. G orH can be connected to the Y output.A CLB can be used to implement any of the following functions:

any function of up to four variables, plus any second

function of up to four unrelated variables, plus any thirdfunction of up to three unrelated variables1any single function of five variablesany function of four variables together with somefunctions of six variablessome functions of up to nine variables.

Implementing wide functions in a single block reduces both

the number of blocks required and the delay in the signalpath, achieving both increased capacity and speed.The versatility of the CLB function generators significantlyimproves system speed. In addition, the design-softwaretools can deal with each function generator independently.This flexibility improves cell usage.

1. When three separate functions are generated, one of the function outputs must be captured in a flip-flop internal to the CLB. Only twounregistered function generator outputs are available from the CLB.

The CLB can pass the combinatorial output(s) to the interconnect network, but can also store the combinatorialresults or other incoming data in one or two flip-flops, andconnect their outputs to the interconnect network as well.

The clock enable signal (EC) is active High. The EC pin is

shared by both storage elements. If left unconnected foreither, the clock enable for that storage element defaults tothe active state. EC is not invertible within the CLB.

The two edge-triggered D-type flip-flops have common

clock (K) and clock enable (EC) inputs. Either or both clockinputs can also be permanently enabled. Storage elementfunctionality is described in Table 2.

Table 2: CLB Storage Element Functionality

(active rising edge is shown)

Latches (XC4000X only)

The CLB storage elements can also be configured aslatches. The two latches have common clock (K) and clockenable (EC) inputs. Storage element functionality isdescribed in Table 2.

Clock InputEach flip-flop can be triggered on either the rising or fallingclock edge. The clock pin is shared by both storage elements. However, the clock is individually invertible for eachstorage element. Any inverter placed on the clock input isautomatically absorbed into the CLB.

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ModePower-Up orGSRFlip-Flop

LatchBothLegend:X__/SR0*1*

EC

SR

SR

X__/010X

X1*X1*1*0

10*0*0*0*0*

XDXXDX

SRDQQDQ

Dont careRising edgeSet or Reset value. Reset is default.Input is Low or unconnected (default value)Input is High or unconnected (default value)

May 14, 1999 (Version 1.6)

XC4000E and XC4000X Series Field Programmable Gate Arrays

Set/ResetAn asynchronous storage element input (SR) can be configured as either set or reset. This configuration optiondetermines the state in which each flip-flop becomes operational after configuration. It also determines the effect of aGlobal Set/Reset pulse during normal operation, and theeffect of a pulse on the SR pin of the CLB. All threeset/reset functions for any single flip-flop are controlled bythe same configuration data bit.The set/reset state can be independently specified for eachflip-flop. This input can also be independently disabled foreither flip-flop.The set/reset state is specified by using the INIT attribute,or by placing the appropriate set or reset flip-flop librarysymbol.

Two fast feed-through paths are available, as shown in

Figure 1. A two-to-one multiplexer on each of the XQ andYQ outputs selects between a storage element output andany of the control inputs. This bypass is sometimes used bythe automated router to repower internal signals.

Control SignalsMultiplexers in the CLB map the four control inputs (C1 - C4in Figure 1) into the four internal control signals (H1,DIN/H2, SR/H0, and EC). Any of these inputs can drive anyof the four internal control signals.When the logic function is enabled, the four inputs are:

SR is active High. It is not invertible within the CLB.

Global Set/Reset

When the memory function is enabled, the four inputs are:

A separate Global Set/Reset line (not shown in Figure 1)

sets or clears each storage element during power-up,re-configuration, or when a dedicated Reset net is drivenactive. This global net (GSR) does not compete with otherrouting resources; it uses a dedicated distribution network.

Each flip-flop is configured as either globally set or reset in

the same way that the local set/reset (SR) is specified.Therefore, if a flip-flop is set by SR, it is also set by GSR.Similarly, a reset flip-flop is reset by both SR and GSR.

Using FPGA Flip-Flops and Latches

STARTUPPADIBUF

GSRGTS

Q2Q3Q1Q4CLK DONEINX5260

Figure 2: Schematic Symbols for Global Set/Reset

GSR can be driven from any user-programmable pin as aglobal reset input. To use this global net, place an input padand input buffer in the schematic or HDL code, driving theGSR pin of the STARTUP symbol. (See Figure 2.) A specific pin location can be assigned to this input using a LOCattribute or property, just as with any other user-programmable pad. An inverter can optionally be inserted after theinput buffer to invert the sense of the Global Set/Reset signal.Alternatively, GSR can be driven from any internal node.

Data Inputs and Outputs

The source of a storage element data input is programmable. It is driven by any of the functions F, G, and H, or bythe Direct In (DIN) block input. The flip-flops or latches drivethe XQ and YQ CLB outputs.

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The abundance of flip-flops in the XC4000 Series invites

pipelined designs. This is a powerful way of increasing performance by breaking the function into smaller subfunctions and executing them in parallel, passing on the resultsthrough pipeline flip-flops. This method should be seriouslyconsidered wherever throughput is more important thanlatency.To include a CLB flip-flop, place the appropriate librarysymbol. For example, FDCE is a D-type flip-flop with clockenable and asynchronous clear. The corresponding latchsymbol (for the XC4000X only) is called LDCE.In XC4000 Series devices, the flip flops can be used as registers or shift registers without blocking the function generators from performing a different, perhaps unrelated task.This ability increases the functional capacity of the devices.The CLB setup time is specified between the function generator inputs and the clock input K. Therefore, the specifiedCLB flip-flop setup time includes the delay through thefunction generator.

Using Function Generators as RAM

Optional modes for each CLB make the memory look-uptables in the F and G function generators usable as anarray of Read/Write memory cells. Available modes arelevel-sensitive (similar to the XC4000/A/H families),edge-triggered, and dual-port edge-triggered. Dependingon the selected mode, a single CLB can be configured aseither a 16x2, 32x1, or 16x1 bit array.

XC4000E and XC4000X Series Field Programmable Gate Arrays

The selected timing mode applies to both function generators within a CLB when both are configured as RAM.

XC4000 Series devices are the first programmable logic

devices with edge-triggered (synchronous) and dual-portRAM accessible to the user. Edge-triggered RAM simplifies system timing. Dual-port RAM doubles the effectivethroughput of FIFO applications. These features can beindividually programmed in any XC4000 Series CLB.

The number of read ports is also programmable:

Advantages of On-Chip and Edge-Triggered RAM

The on-chip RAM is extremely fast. The read access time isthe same as the logic delay. The write access time isslightly slower. Both access times are much faster thanany off-chip solution, because they avoid I/O delays.Edge-triggered RAM, also called synchronous RAM, is afeature never before available in a Field ProgrammableGate Array. The simplicity of designing with edge-triggeredRAM, and the markedly higher achievable performance,add up to a significant improvement over existing deviceswith on-chip RAM.Three application notes are available from Xilinx that discuss edge-triggered RAM: XC4000E Edge-Triggered andDual-Port RAM Capability, Implementing FIFOs inXC4000E RAM, and Synchronous and AsynchronousFIFO Designs. All three application notes apply to bothXC4000E and XC4000X RAM.Table 3: Supported RAM Modes

Single-PortDual-Port

16x1

16x2

32x1

EdgeTriggeredTiming

LevelSensitiveTiming

RAM Configuration Options

The function generators in any CLB can be configured asRAM arrays in the following sizes:

Single Port: each function generator has a common

read and write portDual Port: both function generators are configuredtogether as a single 16x1 dual-port RAM with one writeport and two read ports. Simultaneous read and writeoperations to the same or different addresses aresupported.

RAM configuration options are selected by placing the

appropriate library symbol.Choosing a RAM Configuration ModeThe appropriate choice of RAM mode for a given designshould be based on timing and resource requirements,desired functionality, and the simplicity of the design process. Recommended usage is shown in Table 4.The difference between level-sensitive, edge-triggered,and dual-port RAM is only in the write operation. Readoperation and timing is identical for all modes of operation.Table 4: RAM Mode SelectionDual-PortLevel-Sens Edge-Trigg Edge-TriggitiveerederedUse for NewDesigns?Size (16x1,Registered)SimultaneousRead/WriteRelativePerformance

RAM Inputs and Outputs

The F1-F4 and G1-G4 inputs to the function generators act

One F or G function generator can be configured as a 16x1

RAM while the other function generators are used to implement any function of up to 5 inputs.

The functionality of the CLB control signals changes when

the function generators are configured as RAM. TheDIN/H2, H1, and SR/H0 lines become the two data inputs(D0, D1) and the Write Enable (WE) input for the 16x2memory. When the 32x1 configuration is selected, D1 actsas the fifth address bit and D0 is the data input.

Two 16x1 RAMs: two data inputs and two data outputswith identical or, if preferred, different addressing foreach RAM One 32x1 RAM: one data input and one data output.

Additionally, the XC4000 Series RAM may have either of

two timing modes:

Edge-Triggered (Synchronous): data written by the

designated edge of the CLB clock. WE acts as a trueclock enable. Level-Sensitive (Asynchronous): an external WE signalacts as the write strobe.

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The contents of the memory cell(s) being addressed are

available at the F and G function-generator outputs. Theycan exit the CLB through its X and Y outputs, or can be captured in the CLB flip-flop(s).Configuring the CLB function generators as Read/Writememory does not affect the functionality of the other por-

May 14, 1999 (Version 1.6)

XC4000E and XC4000X Series Field Programmable Gate Arrays

tions of the CLB, with the exception of the redefinition of thecontrol signals. In 16x2 and 16x1 modes, the H functiongenerator can be used to implement Boolean functions ofF, G, and D1, and the D flip-flops can latch the F, G, H, orD0 signals.Single-Port Edge-Triggered ModeEdge-triggered (synchronous) RAM simplifies timingrequirements. XC4000 Series edge-triggered RAM timingoperates like writing to a data register. Data and addressare presented. The register is enabled for writing by a logicHigh on the write enable input, WE. Then a rising or fallingclock edge loads the data into the register, as shown inFigure 3.TWPSWCLK (K)

WE

DATA INTASS

The Write Clock input (WCLK) can be configured as active

on either the rising edge (default) or the falling edge. It usesthe same CLB pin (K) used to clock the CLB flip-flops, but itcan be independently inverted. Consequently, the RAMoutput can optionally be registered within the same CLBeither by the same clock edge as the RAM, or by the opposite edge of this clock. The sense of WCLK applies to bothfunction generators in the CLB when both are configuredas RAM.

Note: The pulse following the active edge of WCLK (TWPS

in Figure 3) must be less than one millisecond wide. Formost applications, this requirement is not overly restrictive;however, it must not be forgotten. Stopping WCLK at thispoint in the write cycle could result in excessive current andeven damage to the larger devices if many CLBs are configured as edge-triggered RAM.

TDHS

TDSS

The relationships between CLB pins and RAM inputs and

outputs for single-port, edge-triggered mode are shown inTable 5.

The WE pin is active-High and is not invertible within the

CLB.

TWHS

TWSS

nals. An internal write pulse is generated that performs the

write. See Figure 4 and Figure 5 for block diagrams of aCLB configured as 16x2 and 32x1 edge-triggered, single-port RAM.

TAHS

ADDRESS

Table 5: Single-Port Edge-Triggered RAM Signals

TILO

TWOS

TILO

RAM SignalD

DATA OUT

OLD

NEWX6461

Figure 3:

Edge-Triggered RAM Write Timing

Complex timing relationships between address, data, and

write enable signals are not required, and the external writeenable pulse becomes a simple clock enable. The activeedge of WCLK latches the address, input data, and WE sig-

May 14, 1999 (Version 1.6)

XC4000E and XC4000X Series Field Programmable Gate Arrays

Dual-Port Edge-Triggered Mode

Table 6: Dual-Port Edge-Triggered RAM Signals

In dual-port mode, both the F and G function generators

are used to create a single 16x1 RAM array with one writeport and two read ports. The resulting RAM array can beread and written simultaneously at two independentaddresses. Simultaneous read and write operations at thesame address are also supported.Dual-port mode always has edge-triggered write timing, asshown in Figure 3.Figure 6 shows a simple model of an XC4000 Series CLBconfigured as dual-port RAM. One address port, labeledA[3:0], supplies both the read and write address for the Ffunction generator. This function generator behaves thesame as a 16x1 single-port edge-triggered RAM array. TheRAM output, Single Port Out (SPO), appears at the F function generator output. SPO, therefore, reflects the data ataddress A[3:0].The other address port, labeled DPRA[3:0] for Dual PortRead Address, supplies the read address for the G functiongenerator. The write address for the G function generator,however, comes from the address A[3:0]. The output fromthis 16x1 RAM array, Dual Port Out (DPO), appears at theG function generator output. DPO, therefore, reflects thedata at address DPRA[3:0].Therefore, by using A[3:0] for the write address andDPRA[3:0] for the read address, and reading only the DPOoutput, a FIFO that can read and write simultaneously iseasily generated. Simultaneous access doubles the effective throughput of the FIFO.The relationships between CLB pins and RAM inputs andoutputs for dual-port, edge-triggered mode are shown inTable 6. See Figure 7 on page 16 for a block diagram of aCLB configured in this mode.RAM16X1D PrimitiveDPO (Dual Port Out)WEDDPRA[3:0]

Note: The pulse following the active edge of WCLK (TWPS

in Figure 3) must be less than one millisecond wide. Formost applications, this requirement is not overly restrictive;however, it must not be forgotten. Stopping WCLK at thispoint in the write cycle could result in excessive current andeven damage to the larger devices if many CLBs are configured as edge-triggered RAM.Single-Port Level-Sensitive Timing ModeNote: Edge-triggered mode is recommended for all newdesigns. Level-sensitive mode, also called asynchronousmode, is still supported for XC4000 Series backward-compatibility with the XC4000 family.Level-sensitive RAM timing is simple in concept but can becomplicated in execution. Data and address signals arepresented, then a positive pulse on the write enable pin(WE) performs a write into the RAM at the designatedaddress. As indicated by the level-sensitive label, thisRAM acts like a latch. During the WE High pulse, changingthe data lines results in new data written to the old address.Changing the address lines while WE is High results in spurious data written to the new addressand possibly atother addresses as well, as the address lines inevitably donot all change simultaneously.The user must generate a carefully timed WE signal. Thedelay on the WE signal and the address lines must be carefully verified to ensure that WE does not become activeuntil after the address lines have settled, and that WE goesinactive before the address lines change again. The datamust be stable before and after the falling edge of WE.

SPO (Single Port Out)

WEDA[3:0]

Registered SPO

AR[3:0]AW[3:0]

F Function Generator

WCLK

In practical terms, WE is usually generated by a 2X clock. If

a 2X clock is not available, the falling edge of the systemclock can be used. However, there are inherent risks in thisapproach, since the WE pulse must be guaranteed inactivebefore the next rising edge of the system clock. Severalolder application notes are available from Xilinx that discuss the design of level-sensitive RAMs.

X6755

Figure 6: XC4000 Series Dual-Port RAM, Simple

Model

May 14, 1999 (Version 1.6)

However, the edge-triggered RAM available in the XC4000

Series is superior to level-sensitive RAM for almost everyapplication.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

C1 C4

D1

WE

EC

D0

DIN

WRITEDECODER

16-LATCHARRAY

G'

MUX

41 of 16LATCHENABLE

G1 G4

WRITE PULSE

READADDRESS

DIN

16-LATCHARRAY

WRITEDECODER

F1 F4

F'

MUX

1 of 16LATCHENABLE

K(CLOCK)

WRITE PULSE

READADDRESS

X6748

Figure 7: 16x1 Edge-Triggered Dual-Port RAM

Figure 8 shows the write timing for level-sensitive, single-port RAM.The relationships between CLB pins and RAM inputs andoutputs for single-port level-sensitive mode are shown inTable 7.Figure 9 and Figure 10 show block diagrams of a CLB configured as 16x2 and 32x1 level-sensitive, single-port RAM.Initializing RAM at ConfigurationBoth RAM and ROM implementations of the XC4000Series devices are initialized during configuration. The initial contents are defined via an INIT attribute or property

attached to the RAM or ROM symbol, as described in the

schematic library guide. If not defined, all RAM contentsare initialized to all zeros, by default.RAM initialization occurs only during configuration. TheRAM content is not affected by Global Set/Reset.Table 7: Single-Port Level-Sensitive RAM SignalsRAM SignalDA[3:0]WEO

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Fast Carry LogicEach CLB F and G function generator contains dedicatedarithmetic logic for the fast generation of carry and borrowsignals. This extra output is passed on to the function generator in the adjacent CLB. The carry chain is independentof normal routing resources.Dedicated fast carry logic greatly increases the efficiencyand performance of adders, subtractors, accumulators,comparators and counters. It also opens the door to manynew applications involving arithmetic operation, where theprevious generations of FPGAs were not fast enough or tooinefficient. High-speed address offset calculations in microprocessor or graphics systems, and high-speed addition indigital signal processing are two typical applications.

XC4000. This discussion also applies to XC4000E

devices, and to XC4000X devices when the minor logicchanges are taken into account.The fast carry logic can be accessed by placing speciallibrary symbols, or by using Xilinx Relationally Placed Macros (RPMs) that already include these symbols.

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

The two 4-input function generators can be configured as a

2-bit adder with built-in hidden carry that can be expandedto any length. This dedicated carry circuitry is so fast andefficient that conventional speed-up methods like carrygenerate/propagate are meaningless even at the 16-bitlevel, and of marginal benefit at the 32-bit level.

CLB

CLB

CLB

CLB

This fast carry logic is one of the more significant features

of the XC4000 Series, speeding up arithmetic and countinginto the 70 MHz range.

CLB

CLB

CLB

CLB

The carry chain in XC4000E devices can run either up or

down. At the top and bottom of the columns where thereare no CLBs above or below, the carry is propagated to theright. (See Figure 11.) In order to improve speed in thehigh-capacity XC4000X devices, which can potentiallyhave very long carry chains, the carry chain travels upwardonly, as shown in Figure 12. Additionally, standard interconnect can be used to route a carry signal in the downwarddirection.Figure 13 on page 19 shows an XC4000E CLB with dedicated fast carry logic. The carry logic in the XC4000X issimilar, except that COUT exits at the top only, and the signal CINDOWN does not exist. As shown in Figure 13, thecarry logic shares operand and control inputs with the function generators. The carry outputs connect to the functiongenerators, where they are combined with the operands toform the sums.Figure 14 on page 20 shows the details of the carry logicfor the XC4000E. This diagram shows the contents of thebox labeled CARRY LOGIC in Figure 13. The XC4000Xcarry logic is very similar, but a multiplexer on thepass-through carry chain has been eliminated to reducedelay. Additionally, in the XC4000X the multiplexer on theG4 path has a memory-programmable 0 input, which permits G4 to directly connect to COUT. G4 thus becomes anadditional high-speed initialization path for carry-in.The dedicated carry logic is discussed in detail in Xilinxdocument XAPP 013: Using the Dedicated Carry Logic in

May 14, 1999 (Version 1.6)

XC4000E and XC4000X Series Field Programmable Gate Arrays

C OUTMG1M

10I

G2

G4

G3C OUT0

TOFUNCTIONGENERATORS

MF2M10

F1

MM

F4

31

F3

MM

X2000

C IN UPC IN DOWN

Figure 14: Detail of XC4000E Dedicated Carry Logic

Input/Output Blocks (IOBs)

User-configurable input/output blocks (IOBs) provide theinterface between external package pins and the internallogic. Each IOB controls one package pin and can be configured for input, output, or bidirectional signals.Figure 15 shows a simplified block diagram of theXC4000E IOB. A more complete diagram which includesthe boundary scan logic of the XC4000E IOB can be foundin Figure 40 on page 43, in the Boundary Scan section.The XC4000X IOB contains some special features notincluded in the XC4000E IOB. These features are highlighted in a simplified block diagram found in Figure 16, anddiscussed throughout this section. When XC4000X specialfeatures are discussed, they are clearly identified in thetext. Any feature not so identified is present in bothXC4000E and XC4000X devices.

IOB Input Signals

Two paths, labeled I1 and I2 in Figure 15 and Figure 16,bring input signals into the array. Inputs also connect to aninput register that can be programmed as either anedge-triggered flip-flop or a level-sensitive latch.

6-20

The choice is made by placing the appropriate library symbol. For example, IFD is the basic input flip-flop (rising edgetriggered), and ILD is the basic input latch (transparent-High). Variations with inverted clocks are available, andsome combinations of latches and flip-flops can be implemented in a single IOB, as described in the XACT LibrariesGuide.The XC4000E inputs can be globally configured for eitherTTL (1.2V) or 5.0 volt CMOS thresholds, using an option inthe bitstream generation software. There is a slight inputhysteresis of about 300mV. The XC4000E output levels arealso configurable; the two global adjustments of inputthreshold and output level are independent.Inputs on the XC4000XL are TTL compatible and 3.3VCMOS compatible. Outputs on the XC4000XL are pulled tothe 3.3V positive supply.The inputs of XC4000 Series 5-Volt devices can be drivenby the outputs of any 3.3-Volt device, if the 5-Volt inputs arein TTL mode.Supported sources for XC4000 Series device inputs areshown in Table 8.

XC4000XL 5-Volt Tolerant I/Os

The I/Os on the XC4000XL are fully 5-volt tolerant eventhough the VCC is 3.3 volts. This allows 5 V signals todirectly connect to the XC4000XL inputs without damage,as shown in Table 8. In addition, the 3.3 volt VCC can beapplied before or after 5 volt signals are applied to the I/Os.This makes the XC4000XL immune to power supplysequencing problems.Registered InputsThe I1 and I2 signals that exit the block can each carryeither the direct or registered input signal.The input and output storage elements in each IOB have acommon clock enable input, which, through configuration,can be activated individually for the input or output flip-flop,or both. This clock enable operates exactly like the EC pinon the XC4000 Series CLB. It cannot be inverted within theIOB.The storage element behavior is shown in Table 9.Table 9: Input Register Functionality(active rising edge is shown)Mode

Clock

Power-Up orGSRFlip-Flop

ClockEnableX

__/010X

1*X1*1*0

LatchBothLegend:X__/SR0*1*

6-22

The data input to the register can optionally be delayed by

several nanoseconds. With the delay enabled, the setuptime of the input flip-flop is increased so that normal clockrouting does not result in a positive hold-time requirement.A positive hold time requirement can lead to unreliable,temperature- or processing-dependent operation.The input flip-flop setup time is defined between the datameasured at the device I/O pin and the clock input at theIOB (not at the clock pin). Any routing delay from the deviceclock pin to the clock input of the IOB must, therefore, besubtracted from this setup time to arrive at the real setuptime requirement relative to the device pins. A short specified setup time might, therefore, result in a negative setuptime at the device pins, i.e., a positive hold-time requirement.

Optional Delay Guarantees Zero Hold Time

SR

DXXDX

DQQDQ

Dont careRising edgeSet or Reset value. Reset is default.Input is Low or unconnected (default value)Input is High or unconnected (default value)

When a delay is inserted on the data line, more clock delay

can be tolerated without causing a positive hold-timerequirement. Sufficient delay eliminates the possibility of adata hold-time requirement at the external pin. The maximum delay is therefore inserted as the default.The XC4000E IOB has a one-tap delay element: either thedelay is inserted (default), or it is not. The delay guaranteesa zero hold time with respect to clocks routed through anyof the XC4000E global clock buffers. (See Global Nets andBuffers (XC4000E only) on page 35 for a description of theglobal clock buffers in the XC4000E.) For a shorter inputregister setup time, with non-zero hold, attach a NODELAYattribute or property to the flip-flop.The XC4000X IOB has a two-tap delay element, withchoices of a full delay, a partial delay, or no delay. Theattributes or properties used to select the desired delay areshown in Table 10. The choices are no added attribute,MEDDELAY, and NODELAY. The default setting, with noadded attribute, ensures no hold time with respect to any ofthe XC4000X clock buffers, including the Global Low-Skewbuffers. MEDDELAY ensures no hold time with respect tothe Global Early buffers. Inputs with NODELAY may have apositive hold time with respect to all clock buffers. For adescription of each of these buffers, see Global Nets andBuffers (XC4000X only) on page 37.Table 10: XC4000X IOB Input Delay ElementValuefull delay(default, noattribute added)MEDDELAYNODELAY

When to UseZero Hold with respect to GlobalLow-Skew Buffer, Global Early BufferZero Hold with respect to Global EarlyBufferShort Setup, positive Hold time

May 14, 1999 (Version 1.6)

XC4000E and XC4000X Series Field Programmable Gate Arrays

Additional Input Latch for Fast Capture (XC4000X only)The XC4000X IOB has an additional optional latch on theinput. This latch, as shown in Figure 16, is clocked by theoutput clock the clock used for the output flip-flop rather than the input clock. Therefore, two different clockscan be used to clock the two input storage elements. Thisadditional latch allows the very fast capture of input data,which is then synchronized to the internal clock by the IOBflip-flop or latch.To use this Fast Capture technique, drive the output clockpin (the Fast Capture latching signal) from the output of oneof the Global Early buffers supplied in the XC4000X. Thesecond storage element should be clocked by a GlobalLow-Skew buffer, to synchronize the incoming data to theinternal logic. (See Figure 17.) These special buffers aredescribed in Global Nets and Buffers (XC4000X only) onpage 37.The Fast Capture latch (FCL) is designed primarily for usewith a Global Early buffer. For Fast Capture, a single clocksignal is routed through both a Global Early buffer and aGlobal Low-Skew buffer. (The two buffers share an inputpad.) The Fast Capture latch is clocked by the Global Earlybuffer, and the standard IOB flip-flop or latch is clocked bythe Global Low-Skew buffer. This mode is the safest way touse the Fast Capture latch, because the clock buffers onboth storage elements are driven by the same pad. There isno external skew between clock pads to create potentialproblems.To place the Fast Capture latch in a design, use one of thespecial library symbols, ILFFX or ILFLX. ILFFX is a transparent-Low Fast Capture latch followed by an active-Highinput flip-flop. ILFLX is a transparent-Low Fast Capturelatch followed by a transparent-High input latch. Any of theclock inputs can be inverted before driving the library element, and the inverter is absorbed into the IOB. If a singleBUFG output is used to drive both clock inputs, the software automatically runs the clock through both a GlobalLow-Skew buffer and a Global Early buffer, and clocks theFast Capture latch appropriately.Figure 16 on page 21 also shows a two-tap delay on theinput. By default, if the Fast Capture latch is used, the Xilinxsoftware assumes a Global Early buffer is driving the clock,and selects MEDDELAY to ensure a zero hold time. Select

ILFFXIPAD

to internallogic

GFBUFGE

CE

the desired delay based on the discussion in the previous

subsection.

IOB Output Signals

Output signals can be optionally inverted within the IOB,and can pass directly to the pad or be stored in anedge-triggered flip-flop. The functionality of this flip-flop isshown in Table 11.An active-High 3-state signal can be used to place the output buffer in a high-impedance state, implementing 3-stateoutputs or bidirectional I/O. Under configuration control, theoutput (OUT) and output 3-state (T) signals can beinverted. The polarity of these signals is independently configured for each IOB.The 4-mA maximum output current specification of manyFPGAs often forces the user to add external buffers, whichare especially cumbersome on bidirectional I/O lines. TheXC4000E and XC4000EX/XL devices solve many of theseproblems by providing a guaranteed output sink current of12 mA. Two adjacent outputs can be interconnected externally to sink up to 24 mA. The XC4000E and XC4000EX/XLFPGAs can thus directly drive buses on a printed circuitboard.By default, the output pull-up structure is configured as aTTL-like totem-pole. The High driver is an n-channel pull-uptransistor, pulling to a voltage one transistor thresholdbelow Vcc. Alternatively, the outputs can be globally configured as CMOS drivers, with p-channel pull-up transistorspulling to Vcc. This option, applied using the bitstream generation software, applies to all outputs on the device. It isnot individually programmable. In the XC4000XL, all outputs are pulled to the positive supply rail.Table 11: Output Flip-Flop Functionality (active risingedge is shown)ModePower-Upor GSRFlip-Flop

Legend:X__/SR0*1*Z

ClockX

ClockEnableX

T0*

DX

QSR

X__/X0

01*XX

0*0*10*

XDXX

QDZQ

Dont careRising edgeSet or Reset value. Reset is default.Input is Low or unconnected (default value)Input is High or unconnected (default value)3-state

IPADBUFGLS

X9013

Figure 17: Examples Using XC4000X FCL

May 14, 1999 (Version 1.6)

6-23

XC4000E and XC4000X Series Field Programmable Gate Arrays

Any XC4000 Series 5-Volt device with its outputs configured in TTL mode can drive the inputs of any typical3.3-Volt device. (For a detailed discussion of how to interface between 5 V and 3.3 V devices, see the 3V Productssection of The Programmable Logic Data Book.)

Power/Ground pin pairs are connected to special Power

and Ground planes within the packages, to reduce groundbounce. Therefore, the maximum total capacitive load is300 pF between each external Power/Ground pin pair.Maximum loading may vary for the low-voltage devices.

Supported destinations for XC4000 Series device outputs

are shown in Table 12.

For slew-rate limited outputs this total is two times larger foreach device type: 400 pF for XC4000E devices and 600 pFfor XC4000X devices. This maximum capacitive loadshould not be exceeded, as it can result in ground bounceof greater than 1.5 V amplitude and more than 5 ns duration. This level of ground bounce may cause undesiredtransient behavior on an output, or in the internal logic. Thisrestriction is common to all high-speed digital ICs, and isnot particular to Xilinx or the XC4000 Series.

XC4000 Series devices have a feature called Soft

Start-up, designed to reduce ground bounce when all outputs are turned on simultaneously at the end of configuration. When the configuration process is finished and thedevice starts up, the first activation of the outputs is automatically slew-rate limited. Immediately following the initialactivation of the I/O, the slew rate of the individual outputsis determined by the individual configuration option for eachIOB.Global Three-StateA separate Global 3-State line (not shown in Figure 15 orFigure 16) forces all FPGA outputs to the high-impedancestate, unless boundary scan is enabled and is executing anEXTEST instruction. This global net (GTS) does not compete with other routing resources; it uses a dedicated distribution network.GTS can be driven from any user-programmable pin as aglobal 3-state input. To use this global net, place an inputpad and input buffer in the schematic or HDL code, drivingthe GTS pin of the STARTUP symbol. A specific pin location can be assigned to this input using a LOC attribute orproperty, just as with any other user-programmable pad. Aninverter can optionally be inserted after the input buffer toinvert the sense of the Global 3-State signal. Using GTS issimilar to GSR. See Figure 2 on page 11 for details.Alternatively, GTS can be driven from any internal node.

May 14, 1999 (Version 1.6)

XC4000E and XC4000X Series Field Programmable Gate Arrays

Other IOB Options

Output Multiplexer/2-Input Function Generator

(XC4000X only)As shown in Figure 16 on page 21, the output path in theXC4000X IOB contains an additional multiplexer not available in the XC4000E IOB. The multiplexer can also be configured as a 2-input function generator, implementing apass-gate, AND-gate, OR-gate, or XOR-gate, with 0, 1, or 2inverted inputs. The logic used to implement these functions is shown in the upper gray area of Figure 16.When configured as a multiplexer, this feature allows twooutput signals to time-share the same output pad; effectively doubling the number of device outputs without requiring a larger, more expensive package.When the MUX is configured as a 2-input function generator, logic can be implemented within the IOB itself. Combined with a Global Early buffer, this arrangement allowsvery high-speed gating of a single signal. For example, awide decoder can be implemented in CLBs, and its outputgated with a Read or Write Strobe Driven by a BUFGEbuffer, as shown in Figure 19. The critical-path pin-to-pindelay of this circuit is less than 6 nanoseconds.As shown in Figure 16, the IOB input pins Out, OutputClock, and Clock Enable have different delays and differentflexibilities regarding polarity. Additionally, Output Clocksources are more limited than the other inputs. Therefore,the Xilinx software does not move logic into the IOB function generators unless explicitly directed to do so.The user can specify that the IOB function generator beused, by placing special library symbols beginning with theletter O. For example, a 2-input AND-gate in the IOB function generator is called OAND2. Use the symbol input pinlabelled F for the signal on the critical path. This signal isplaced on the OK pin the IOB input with the shortestdelay to the function generator. Two examples are shown inFigure 20.IPADF

OPADFAST

OAND2

X9019

Figure 19: Fast Pin-to-Pin Path in XC4000X

D0

OMUX2

Programmable pull-up and pull-down resistors are useful

for tying unused pins to Vcc or Ground to minimize powerconsumption and reduce noise sensitivity. The configurablepull-up resistor is a p-channel transistor that pulls to Vcc.The configurable pull-down resistor is an n-channel transistor that pulls to Ground.The value of these resistors is 50 k 100 k. This highvalue makes them unsuitable as wired-AND pull-up resistors.The pull-up resistors for most user-programmable IOBs areactive during the configuration process. See Table 22 onpage 58 for a list of pins with pull-ups active before and during configuration.After configuration, voltage levels of unused pads, bondedor un-bonded, must be valid logic levels, to reduce noisesensitivity and avoid excess current. Therefore, by default,unused pads are configured with the internal pull-up resistor active. Alternatively, they can be individually configuredwith the pull-down resistor, or as a driven output, or to bedriven by an external source. To activate the internalpull-up, attach the PULLUP library component to the netattached to the pad. To activate the internal pull-down,attach the PULLDOWN library component to the netattached to the pad.Independent ClocksSeparate clock signals are provided for the input and outputflip-flops. The clock can be independently inverted for eachflip-flop within the IOB, generating either falling-edge or rising-edge triggered flip-flops. The clock inputs for each IOBare independent, except that in the XC4000X, the FastCapture latch shares an IOB input with the output clock pin.

Special early clocks are available for IOBs. These clocks

are sourced by the same sources as the Global Low-Skewbuffers, but are separately buffered. They have fewer loadsand therefore less delay. The early clock can drive eitherthe IOB output clock or the IOB input clock, or both. Theearly clock allows fast capture of input data, and fastclock-to-output on output data. The Global Early buffersthat drive these clocks are described in Global Nets andBuffers (XC4000X only) on page 37.

Global Set/Reset

D1

OAND2

Pull-up and Pull-down Resistors

Early Clock for IOBs (XC4000X only)

BUFGEfrominternallogic

There are a number of other programmable options in the

XC4000 Series IOB.

X6598

S0X6599

Figure 20: AND & MUX Symbols in XC4000X IOB

May 14, 1999 (Version 1.6)

As with the CLB registers, the Global Set/Reset signal

(GSR) can be used to set or clear the input and output registers, depending on the value of the INIT attribute or property. The two flip-flops can be individually configured to set

6-25

XC4000E and XC4000X Series Field Programmable Gate Arrays

or clear on reset and after configuration. Other than the global GSR net, no user-controlled set/reset signal is availableto the I/O flip-flops. The choice of set or clear applies toboth the initial state of the flip-flop and the response to theGlobal Set/Reset pulse. See Global Set/Reset onpage 11 for a description of how to use GSR.

The buffer can be used as a Wired-AND. Use the WAND1

library symbol, which is essentially an open-drain buffer.WAND4, WAND8, and WAND16 are also available. See theXACT Libraries Guide for further information.

Three-State Buffers

The T pin is internally tied to the I pin. Connect the input to

the I pin and the output to the O pin. Connect the outputs ofall the WAND1s together and attach a PULLUP symbol.

All three pins are used. Place the library element BUFT.Connect the input to the I pin and the output to the O pin.The T pin is an active-High 3-state (i.e. an active-Lowenable). Tie the T pin to Ground to implement a standardbuffer.

A pair of 3-state buffers is associated with each CLB in the

array. (See Figure 27 on page 30.) These 3-state bufferscan be used to drive signals onto the nearest horizontallonglines above and below the CLB. They can therefore beused to implement multiplexed or bidirectional buses on thehorizontal longlines, saving logic resources. Programmablepull-up resistors attached to these longlines help to implement a wide wired-AND function.

Wired OR-ANDThe buffer can be configured as a Wired OR-AND. A Highlevel on either input turns off the output. Use theWOR2AND library symbol, which is essentially anopen-drain 2-input OR gate. The two input pins are functionally equivalent. Attach the two inputs to the I0 and I1pins and tie the output to the O pin. Tie the outputs of all theWOR2ANDs together and attach a PULLUP symbol.

The buffer enable is an active-High 3-state (i.e. an

active-Low enable), as shown in Table 13.

Three-State Buffer Examples

Another 3-state buffer with similar access is located near

each I/O block along the right and left edges of the array.(See Figure 33 on page 34.)

Figure 21 shows how to use the 3-state buffers to implement a wired-AND function. When all the buffer inputs areHigh, the pull-up resistor(s) provide the High output.

The horizontal longlines driven by the 3-state buffers have

a weak keeper at each end. This circuit prevents undefinedfloating levels. However, it is overridden by any driver, evena pull-up resistor.

Figure 22 shows how to use the 3-state buffers to implement a multiplexer. The selection is accomplished by thebuffer 3-state signal.Pay particular attention to the polarity of the T pin whenusing these buffers in a design. Active-High 3-state (T) isidentical to an active-Low output enable, as shown inTable 13.

Special longlines running along the perimeter of the array

can be used to wire-AND signals coming from nearby IOBsor from internal longlines. These longlines form the wideedge decoders discussed in Wide Edge Decoders onpage 27.

Table 13: Three-State Buffer Functionality

Three-State Buffer Modes

INXIN

The 3-state buffers can be configured in three modes:

Standard 3-state buffer

Wired-AND with input on the I pinWired OR-AND

Z=D

WAND1

(D

WAND1

OUTZIN

PULL

+D ) (D +D )

UP

DED

DCD

T10

WOR2AND

WOR2ANDX6465

Figure 21: Open-Drain Buffers Implement a Wired-AND Function

6-26

May 14, 1999 (Version 1.6)

XC4000E and XC4000X Series Field Programmable Gate Arrays

Z = DA A + D B B + D C C + D N N

~100 k

DA

DBBUFT

DCBUFT

DNBUFT

BUFT

NX6466

"Weak Keeper"

Figure 22: 3-State Buffers Implement a Multiplexer

Wide Edge Decoders

Dedicated decoder circuitry boosts the performance ofwide decoding functions. When the address or data field iswider than the function generator inputs, FPGAs needmulti-level decoding and are thus slower than PALs.XC4000 Series CLBs have nine inputs. Any decoder of upto nine inputs is, therefore, compact and fast. However,there is also a need for much wider decoders, especially foraddress decoding in large microprocessor systems.An XC4000 Series FPGA has four programmable decoderslocated on each edge of the device. The inputs to eachdecoder are any of the IOB I1 signals on that edge plus onelocal interconnect per CLB row or column. Each row or column of CLBs provides up to three variables or their compliments., as shown in Figure 23. Each decoder generates aHigh output (resistor pull-up) when the AND condition ofthe selected inputs, or their complements, is true. This isanalogous to a product term in typical PAL devices.Each of these wired-AND gates is capable of accepting upto 42 inputs on the XC4005E and 72 on the XC4013E.There are up to 96 inputs for each decoder on theXC4028X and 132 on the XC4052X. The decoders mayalso be split in two when a larger number of narrowerdecoders are required, for a maximum of 32 decoders perdevice.The decoder outputs can drive CLB inputs, so they can becombined with other logic to form a PAL-like AND/OR structure. The decoder outputs can also be routed directly to thechip outputs. For fastest speed, the output should be on thesame chip edge as the decoder. Very large PALs can beemulated by ORing the decoder outputs in a CLB. Thisdecoding feature covers what has long been considered aweakness of older FPGAs. Users often resorted to externalPALs for simple but fast decoding functions. Now, the dedicated decoders in the XC4000 Series device can implement these functions fast and efficiently.To use the wide edge decoders, place one or more of theWAND library symbols (WAND1, WAND4, WAND8,WAND16). Attach a DECODE attribute or property to eachWAND symbol. Tie the outputs together and attach a PUL-

May 14, 1999 (Version 1.6)

LUP symbol. Location attributes or properties such as L

(left edge) or TR (right half of top edge) should also be usedto ensure the correct placement of the decoder inputs.INTERCONNECT

IOB

IOB

.I1A

.I1C

6(

C) .....

(A B C) .....(A B C) .....(A B C) .....X2627

Figure 23: XC4000 Series Edge Decoding Example

OSC4F8MF500KF16KF490F15X6703

Figure 24: XC4000 Series Oscillator Symbol

On-Chip OscillatorXC4000 Series devices include an internal oscillator. Thisoscillator is used to clock the power-on time-out, for configuration memory clearing, and as the source of CCLK inMaster configuration modes. The oscillator runs at a nominal 8 MHz frequency that varies with process, Vcc, andtemperature. The output frequency falls between 4 and 10MHz.

6-27

XC4000E and XC4000X Series Field Programmable Gate Arrays

The oscillator output is optionally available after configuration. Any two of four resynchronized taps of a built-in dividerare also available. These taps are at the fourth, ninth, fourteenth and nineteenth bits of the divider. Therefore, if theprimary oscillator output is running at the nominal 8 MHz,the user has access to an 8 MHz clock, plus any two of 500kHz, 16kHz, 490Hz and 15Hz (up to 10% lower for low-voltage devices). These frequencies can vary by as much as-50% or +25%.

These signals can be accessed by placing the OSC4

library element in a schematic or in HDL code (seeFigure 24).

Extra routing is included in the IOB pad ring. The XC4000X

also includes a ring of octal interconnect lines near theIOBs to improve pin-swapping and routing to locked pins.

The oscillator is automatically disabled after configuration if

the OSC4 symbol is not used in the design.

XC4000E/X devices include two types of global buffers.

These global buffers have different properties, and areintended for different purposes. They are discussed indetail later in this section.

Programmable InterconnectAll internal connections are composed of metal segmentswith programmable switching points and switching matricesto implement the desired routing. A structured, hierarchicalmatrix of routing resources is provided to achieve efficientautomated routing.The XC4000E and XC4000X share a basic interconnectstructure. XC4000X devices, however, have additional routing not available in the XC4000E. The extra routingresources allow high utilization in high-capacity devices. AllXC4000X-specific routing resources are clearly identifiedthroughout this section. Any resources not identified asXC4000X-specific are present in all XC4000 Seriesdevices.This section describes the varied routing resources available in XC4000 Series devices. The implementation software automatically assigns the appropriate resourcesbased on the density and timing requirements of thedesign.

Interconnect OverviewThere are several types of interconnect.

CLB routing is associated with each row and column of

the CLB array.IOB routing forms a ring (called a VersaRing) aroundthe outside of the CLB array. It connects the I/O with theinternal logic blocks.

6-28

Global routing consists of dedicated networks primarily

designed to distribute clocks throughout the device withminimum delay and skew. Global routing can also beused for other high-fanout signals.

CLB Routing Connections

A high-level diagram of the routing resources associatedwith one CLB is shown in Figure 25. The shaded arrowsrepresent routing present only in XC4000X devices.Table 14 shows how much routing of each type is availablein XC4000E and XC4000X CLB arrays. Clearly, very largedesigns, or designs with a great deal of interconnect, willroute more easily in the XC4000X. Smaller XC4000Edesigns, typically requiring significantly less interconnect,do not require the additional routing.Figure 27 on page 30 is a detailed diagram of both theXC4000E and the XC4000X CLB, with associated routing.The shaded square is the programmable switch matrix,present in both the XC4000E and the XC4000X. TheL-shaped shaded area is present only in XC4000X devices.As shown in the figure, the XC4000X block is essentially anXC4000E block with additional routing.CLB inputs and outputs are distributed on all four sides,providing maximum routing flexibility. In general, the entirearchitecture is symmetrical and regular. It is well suited toestablished placement and routing algorithms. Inputs, outputs, and function generators can freely swap positionswithin a CLB to avoid routing congestion during the placement and routing operation.

Table 14: Routing per CLB in XC4000 Series Devices

Six Pass Transistors

Figure 26: Programmable Switch Matrix (PSM)

Programmable Switch Matrices

The horizontal and vertical single- and double-length lines

intersect at a box called a programmable switch matrix(PSM). Each switch matrix consists of programmable passtransistors used to establish connections between the lines(see Figure 26).

Single-length lines provide the greatest interconnect flexibility and offer fast routing between adjacent blocks. Thereare eight vertical and eight horizontal single-length linesassociated with each CLB. These lines connect the switching matrices that are located in every row and a column ofCLBs.

For example, a single-length signal entering on the right

side of the switch matrix can be routed to a single-lengthline on the top, left, or bottom sides, or any combinationthereof, if multiple branches are required. Similarly, a double-length signal can be routed to a double-length line onany or all of the other three edges of the programmableswitch matrix.

May 14, 1999 (Version 1.6)

Single-length lines are connected by way of the programmable switch matrices, as shown in Figure 28. Routingconnectivity is shown in Figure 27.Single-length lines incur a delay whenever they go througha switching matrix. Therefore, they are not suitable for routing signals for long distances. They are normally used toconduct signals within a localized area and to provide thebranching for nets with fanout greater than one.

Common to XC4000E and XC4000X

May 14, 1999 (Version 1.6)

XC4000E and XC4000X Series Field Programmable Gate Arrays

CLB

CLB

CLB

DoublesPSM

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

CLB

Singles

PSM

Doubles

CLB

CLB

PSM

CLB

CLB

PSM

CLB

CLBX6601

Figure 28: Single- and Double-Length Lines, with

Programmable Switch Matrices (PSMs)

Double-Length LinesThe double-length lines consist of a grid of metal segments,each twice as long as the single-length lines: they run pasttwo CLBs before entering a switch matrix. Double-lengthlines are grouped in pairs with the switch matrices staggered, so that each line goes through a switch matrix atevery other row or column of CLBs (see Figure 28).There are four vertical and four horizontal double-lengthlines associated with each CLB. These lines provide fastersignal routing over intermediate distances, while retainingrouting flexibility. Double-length lines are connected by wayof the programmable switch matrices. Routing connectivityis shown in Figure 27.

Quad Lines (XC4000X only)

XC4000X devices also include twelve vertical and twelvehorizontal quad lines per CLB row and column. Quad linesare four times as long as the single-length lines. They areinterconnected via buffered switch matrices (shown as diamonds in Figure 27 on page 30). Quad lines run past fourCLBs before entering a buffered switch matrix. They aregrouped in fours, with the buffered switch matrices staggered, so that each line goes through a buffered switchmatrix at every fourth CLB location in that row or column.(See Figure 29.)The buffered switch matrixes have four pins, one on eachedge. All of the pins are bidirectional. Any pin can drive anyor all of the other pins.Each buffered switch matrix contains one buffer and sixpass transistors. It resembles the programmable switchmatrix shown in Figure 26, with the addition of a programmable buffer. There can be up to two independent inputs

May 14, 1999 (Version 1.6)

X9014

Figure 29: Quad Lines (XC4000X only)

and up to two independent outputs. Only one of the independent inputs can be buffered.The place and route software automatically uses the timingrequirements of the design to determine whether or not aquad line signal should be buffered. A heavily loaded signalis typically buffered, while a lightly loaded one is not. Onescenario is to alternate buffers and pass transistors. Thisallows both vertical and horizontal quad lines to be bufferedat alternating buffered switch matrices.Due to the buffered switch matrices, quad lines are veryfast. They provide the fastest available method of routingheavily loaded signals for long distances across the device.

LonglinesLonglines form a grid of metal interconnect segments thatrun the entire length or width of the array. Longlines areintended for high fan-out, time-critical signal nets, or netsthat are distributed over long distances. In XC4000Xdevices, quad lines are preferred for critical nets, becausethe buffered switch matrices make them faster for highfan-out nets.Two horizontal longlines per CLB can be driven by 3-stateor open-drain drivers (TBUFs). They can therefore implement unidirectional or bidirectional buses, wide multiplexers, or wired-AND functions. (See Three-State Buffers onpage 26 for more details.)Each horizontal longline driven by TBUFs has either two(XC4000E) or eight (XC4000X) pull-up resistors. To activate these resistors, attach a PULLUP symbol to thelong-line net. The software automatically activates theappropriate number of pull-ups. There is also a weakkeeper at each end of these two horizontal longlines. This

6-31

XC4000E and XC4000X Series Field Programmable Gate Arrays

circuit prevents undefined floating levels. However, it isoverridden by any driver, even a pull-up resistor.Each XC4000E longline has a programmable splitter switchat its center, as does each XC4000X longline driven byTBUFs. This switch can separate the line into two independent routing channels, each running half the width or heightof the array.Each XC4000X longline not driven by TBUFs has a buffered programmable splitter switch at the 1/4, 1/2, and 3/4points of the array. Due to the buffering, XC4000X longlineperformance does not deteriorate with the larger arraysizes. If the longline is split, the resulting partial longlinesare independent.Routing connectivity of the longlines is shown in Figure 27on page 30.

Direct Interconnect (XC4000X only)

The XC4000X offers two direct, efficient and fast connections between adjacent CLBs. These nets facilitate a dataflow from the left to the right side of the device, or from thetop to the bottom, as shown in Figure 30. Signals routed onthe direct interconnect exhibit minimum interconnect propagation delay and use no general routing resources.The direct interconnect is also present between CLBs andadjacent IOBs. Each IOB on the left and top device edgeshas a direct path to the nearest CLB. Each CLB on the rightand bottom edges of the array has a direct path to the nearest two IOBs, since there are two IOBs for each row or column of CLBs.The place and route software uses direct interconnectwhenever possible, to maximize routing resources and minimize interconnect delays.

XC4000 Series devices have additional routing around the

IOB ring. This routing is called a VersaRing. The VersaRingfacilitates pin-swapping and redesign without affectingboard layout. Included are eight double-length lines spanning two CLBs (four IOBs), and four longlines. Global linesand Wide Edge Decoder lines are provided. XC4000Xdevices also include eight octal lines.A high-level diagram of the VersaRing is shown inFigure 31. The shaded arrows represent routing presentonly in XC4000X devices.Figure 33 on page 34 is a detailed diagram of the XC4000Eand XC4000X VersaRing. The area shown includes twoIOBs. There are two IOBs per CLB row or column, therefore this diagram corresponds to the CLB routing diagramshown in Figure 27 on page 30. The shaded areas represent routing and routing connections present only inXC4000X devices.

Octal I/O Routing (XC4000X only)

Between the XC4000X CLB array and the pad ring, eightinterconnect tracks provide for versatility in pin assignmentand fixed pinout flexibility. (See Figure 32 on page 33.)These routing tracks are called octals, because they can bebroken every eight CLBs (sixteen IOBs) by a programmable buffer that also functions as a splitter switch. The buffersare staggered, so each line goes through a buffer at everyeighth CLB location around the device edge.The octal lines bend around the corners of the device. Thelines cross at the corners in such a way that the segmentmost recently buffered before the turn has the farthest distance to travel before the next buffer, as shown inFigure 32.

Common to XC4000E and XC4000X

May 14, 1999 (Version 1.6)

XC4000E and XC4000X Series Field Programmable Gate Arrays

IOB inputs and outputs interface with the octal lines via thesingle-length interconnect lines. Single-length lines arealso used for communication between the octals and double-length lines, quads, and longlines within the CLB array.

Global Nets and Buffers

Both the XC4000E and the XC4000X have dedicated global networks. These networks are designed to distributeclocks and other high fanout control signals throughout thedevices with minimal skew. The global buffers aredescribed in detail in the following sections. The textdescriptions and diagrams are summarized in Table 15.The table shows which CLB and IOB clock pins can besourced by which global buffers.

Primary Global Buffers (BUFGP)

Secondary Global Buffers (BUFGS)

The Primary Global buffers must be driven by the

semi-dedicated pads. The Secondary Global buffers canbe sourced by either semi-dedicated pads or internal nets.Each CLB column has four dedicated vertical Global lines.Each of these lines can be accessed by one particular Primary Global buffer, or by any of the Secondary Global buffers, as shown in Figure 34. Each corner of the device hasone Primary buffer and one Secondary buffer.

In both XC4000E and XC4000X devices, placement of a

library symbol called BUFG results in the software choosing the appropriate clock buffer, based on the timingrequirements of the design. The detailed information inthese sections is included only for reference.

IOBs along the left and right edges have four vertical globallonglines. Top and bottom IOBs can be clocked from theglobal lines in the adjacent CLB column.A global buffer should be specified for all timing-sensitiveglobal signal distribution. To use a global buffer, place aBUFGP (primary buffer), BUFGS (secondary buffer), orBUFG (either primary or secondary buffer) element in aschematic or in HDL code. If desired, attach a LOCattribute or property to direct placement to the designatedlocation. For example, attach a LOC=L attribute or propertyto a BUFGS symbol to direct that a buffer be placed in oneof the two Secondary Global buffers on the left edge of thedevice, or a LOC=BL to indicate the Secondary Globalbuffer on the bottom edge of the device, on the left.

Global Nets and Buffers (XC4000E only)

Four vertical longlines in each CLB column are drivenexclusively by special global buffers. These longlines arein addition to the vertical longlines used for standard interconnect. The four global lines can be driven by either of twotypes of global buffers. The clock pins of every CLB andIOB can also be sourced from local interconnect.

Figure 35: XC4000X Global Net Distribution

6-36

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Global Nets and Buffers (XC4000X only)Eight vertical longlines in each CLB column are driven byspecial global buffers. These longlines are in addition to thevertical longlines used for standard interconnect. The global lines are broken in the center of the array, to allow fasterdistribution and to minimize skew across the whole array.Each half-column global line has its own buffered multiplexer, as shown in Figure 35. The top and bottom globallines cannot be connected across the center of the device,as this connection might introduce unacceptable skew. Thetop and bottom halves of the global lines must be separately driven although they can be driven by the sameglobal buffer.The eight global lines in each CLB column can be driven byeither of two types of global buffers. They can also bedriven by internal logic, because they can be accessed bysingle, double, and quad lines at the top, bottom, half, andquarter points. Consequently, the number of differentclocks that can be used simultaneously in an XC4000Xdevice is very large.There are four global lines feeding the IOBs at the left edgeof the device. IOBs along the right edge have eight globallines. There is a single global line along the top and bottomedges with access to the IOBs. All IOB global lines are broken at the center. They cannot be connected across thecenter of the device, as this connection might introduceunacceptable skew.IOB global lines can be driven from two types of global buffers, or from local interconnect. Alternatively, top and bottomIOBs can be clocked from the global lines in the adjacentCLB column.Two different types of clock buffers are available in theXC4000X:

Global Low-Skew Buffers (BUFGLS)

Global Early Buffers (BUFGE)

Global Low-Skew Buffers are the standard clock buffers.

They should be used for most internal clocking, whenever alarge portion of the device must be driven.Global Early Buffers are designed to provide a faster clockaccess, but CLB access is limited to one-fourth of thedevice. They also facilitate a faster I/O interface.Figure 35 is a conceptual diagram of the global net structure in the XC4000X.Global Early buffers and Global Low-Skew buffers share asingle pad. Therefore, the same IPAD symbol can drive onebuffer of each type, in parallel. This configuration is particularly useful when using the Fast Capture latches, asdescribed in IOB Input Signals on page 20. Paired Global

May 14, 1999 (Version 1.6)

Early and Global Low-Skew buffers share a common input;

they cannot be driven by two different signals.Choosing an XC4000X Clock BufferThe clocking structure of the XC4000X provides a largevariety of features. However, it can be simple to use, without understanding all the details. The software automatically handles clocks, along with all other routing, when theappropriate clock buffer is placed in the design. In fact, if abuffer symbol called BUFG is placed, rather than a specifictype of buffer, the software even chooses the buffer mostappropriate for the design. The detailed information in thissection is provided for those users who want a finer level ofcontrol over their designs.If fine control is desired, use the following summary andTable 15 on page 35 to choose an appropriate clock buffer.

The simplest thing to do is to use a Global Low-Skew

buffer.If a faster clock path is needed, try a BUFG. Thesoftware will first try to use a Global Low-Skew Buffer. Iftiming requirements are not met, a faster buffer willautomatically be used.If a single quadrant of the chip is sufficient for theclocked logic, and the timing requires a faster clock thanthe Global Low-Skew buffer, use a Global Early buffer.

Global Low-Skew Buffers

Each corner of the XC4000X device has two GlobalLow-Skew buffers. Any of the eight Global Low-Skew buffers can drive any of the eight vertical Global lines in a column of CLBs. In addition, any of the buffers can drive any ofthe four vertical lines accessing the IOBs on the left edge ofthe device, and any of the eight vertical lines accessing theIOBs on the right edge of the device. (See Figure 36 onpage 38.)IOBs at the top and bottom edges of the device areaccessed through the vertical Global lines in the CLB array,as in the XC4000E. Any Global Low-Skew buffer can,therefore, access every IOB and CLB in the device.The Global Low-Skew buffers can be driven by eithersemi-dedicated pads or internal logic.To use a Global Low-Skew buffer, instantiate a BUFGLSelement in a schematic or in HDL code. If desired, attach aLOC attribute or property to direct placement to the designated location. For example, attach a LOC=T attribute orproperty to direct that a BUFGLS be placed in one of thetwo Global Low-Skew buffers on the top edge of the device,or a LOC=TR to indicate the Global Low-Skew buffer on thetop edge of the device, on the right.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

8

7IOB

IOB

6IOB

IOB

CLB

IOB

IOB

CLB

CLB

IOB

CLB

CLB

IOB

IOB

CLB

CLB

IOB

IOB

IOB

IOB

IOB

CLB

IOB

7IOB

4X6751

X6753

Figure 36: Any BUFGLS (GCK1 - GCK8) Can

Drive Any or All Clock Inputs on the Device

Figure 37: Left and Right BUFGEs Can Drive Any or

All Clock Inputs in Same Quadrant or Edge (GCK1 isshown. GCK2, GCK5 and GCK6 are similar.)

Global Early Buffers

Each corner of the XC4000X device has two Global Earlybuffers. The primary purpose of the Global Early buffers isto provide an earlier clock access than the potentiallyheavily-loaded Global Low-Skew buffers. A clock sourceapplied to both buffers will result in the Global Early clockedge occurring several nanoseconds earlier than the Global Low-Skew buffer clock edge, due to the lighter loading.Global Early buffers also facilitate the fast capture of deviceinputs, using the Fast Capture latches described in IOBInput Signals on page 20. For Fast Capture, take a singleclock signal, and route it through both a Global Early bufferand a Global Low-Skew buffer. (The two buffers share aninput pad.) Use the Global Early buffer to clock the FastCapture latch, and the Global Low-Skew buffer to clock thenormal input flip-flop or latch, as shown in Figure 17 onpage 23.The Global Early buffers can also be used to provide a fastClock-to-Out on device output pins. However, an early clockin the output flip-flop IOB must be taken into considerationwhen calculating the internal clock speed for the design.

The left-side Global Early buffers can each drive two of thefour vertical lines accessing the IOBs on the entire left edgeof the device. The right-side Global Early buffers can eachdrive two of the eight vertical lines accessing the IOBs onthe entire right edge of the device. (See Figure 37.)Each left and right Global Early buffer can also drive half ofthe IOBs along either the top or bottom edge of the device,using a dedicated line that can only be accessed throughthe Global Early buffers.The top and bottom Global Early buffers can drive half ofthe IOBs along either the left or right edge of the device, asshown in Figure 38. They can only access the top and bottom IOBs via the CLB global lines.

6-38

IOB

The Global Early buffers at the left and right edges of thechip have slightly different capabilities than the ones at thetop and bottom. Refer to Figure 37, Figure 38, andFigure 35 on page 36 while reading the following explanation.Each Global Early buffer can access the eight vertical Global lines for all CLBs in the quadrant. Therefore, onlyone-fourth of the CLB clock pins can be accessed. Thisrestriction is in large part responsible for the faster speed ofthe buffers, relative to the Global Low-Skew buffers.

7IOB

6IOB

CLB

CLB

IOB

IOB

CLB

CLB

IOB

IOB

IOB

23

54X6747

Figure 38: Top and Bottom BUFGEs Can Drive Any

or All Clock Inputs in Same Quadrant (GCK8 isshown. GCK3, GCK4 and GCK7 are similar.)

May 14, 1999 (Version 1.6)

XC4000E and XC4000X Series Field Programmable Gate Arrays

The top and bottom Global Early buffers are about 1 nsslower clock to out than the left and right Global Early buffers.

GNDGround andVcc Ring forI/O Drivers

The Global Early buffers can be driven by either semi-dedicated pads or internal logic. They share pads with the Global Low-Skew buffers, so a single net can drive both globalbuffers, as described above.To use a Global Early buffer, place a BUFGE element in aschematic or in HDL code. If desired, attach a LOCattribute or property to direct placement to the designatedlocation. For example, attach a LOC=T attribute or propertyto direct that a BUFGE be placed in one of the two GlobalEarly buffers on the top edge of the device, or a LOC=TR toindicate the Global Early buffer on the top edge of thedevice, on the right.

LogicPower Grid

GND

This power distribution grid provides a stable supply and

ground for all internal logic, providing the external packagepower pins are all connected and appropriately de-coupled.Typically, a 0.1 F capacitor connected between each Vccpin and the boards Ground plane will provide adequatede-coupling.Output buffers capable of driving/sinking the specified 12mA loads under specified worst-case conditions may becapable of driving/sinking up to 10 times as much currentunder best case conditions.Noise can be reduced by minimizing external load capacitance and reducing simultaneous output transitions in thesame direction. It may also be beneficial to locate heavilyloaded output buffers near the Ground pads. The I/O Blockoutput buffers have a slew-rate limited mode (default) whichshould be used where output rise and fall times are notspeed-critical.

X5422

Figure 39: XC4000 Series Power Distribution

Power DistributionPower for the FPGA is distributed through a grid to achievehigh noise immunity and isolation between logic and I/O.Inside the FPGA, a dedicated Vcc and Ground ring surrounding the logic array provides power to the I/O drivers,as shown in Figure 39. An independent matrix of Vcc andGround lines supplies the interior logic of the device.

Vcc

Vcc

Pin DescriptionsThere are three types of pins in the XC4000 Seriesdevices:

Permanently dedicated pins

User I/O pins that can have special functionsUnrestricted user-programmable I/O pins.

Before and during configuration, all outputs not used for theconfiguration process are 3-stated with a 50 k - 100 kpull-up resistor.After configuration, if an IOB is unused it is configured asan input with a 50 k - 100 k pull-up resistor.XC4000 Series devices have no dedicated Reset input.Any user I/O can be configured to drive the GlobalSet/Reset net, GSR. See Global Set/Reset on page 11for more information on GSR.XC4000 Series devices have no Powerdown control input,as the XC3000 and XC2000 families do. TheXC3000/XC2000 Powerdown control also 3-stated all of thedeviceI/O pins. For XC4000 Series devices, use the global 3-statenet, GTS, instead. This net 3-states all outputs, but doesnot place the device in low-power mode. See IOB OutputSignals on page 23 for more information on GTS.Device pins for XC4000 Series devices are described inTable 16. Pin functions during configuration for each of theseven configuration modes are summarized in Table 22 onpage 58, in the Configuration Timing section.

May 14, 1999 (Version 1.6)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Eight or more (depending on package) connections to the nominal +5 V supply voltage

(+3.3 V for low-voltage devices). All must be connected, and each must be decoupledwith a 0.01 - 0.1 F capacitor to Ground.Eight or more (depending on package type) connections to Ground. All must be conGNDIInected.During configuration, Configuration Clock (CCLK) is an output in Master modes or Asynchronous Peripheral mode, but is an input in Slave mode and Synchronous Peripheralmode. After configuration, CCLK has a weak pull-up resistor and can be selected as theCCLKI or OIReadback Clock. There is no CCLK High or Low time restriction on XC4000 Series devices, except during Readback. See Violating the Maximum High and Low Time Specification for the Readback Clock on page 56 for an explanation of this exception.DONE is a bidirectional signal with an optional internal pull-up resistor. As an output, itindicates the completion of the configuration process. As an input, a Low level on DONEDONEI/OOcan be configured to delay the global logic initialization and the enabling of outputs.The optional pull-up resistor is selected as an option in the XACTstep program that creates the configuration bitstream. The resistor is included by default.PROGRAM is an active Low input that forces the FPGA to clear its configuration memory. It is used to initiate a configuration cycle. When PROGRAM goes High, the FPGAfinishes the current clear cycle and executes another complete clear cycle, before itPROGRAMIIgoes into a WAIT state and releases INIT.The PROGRAM pin has a permanent weak pull-up, so it need not be externally pulledup to Vcc.User I/O Pins That Can Have Special FunctionsDuring Peripheral mode configuration, this pin indicates when it is appropriate to writeanother byte of data into the FPGA. The same status is also available on D7 in AsynOI/Ochronous Peripheral mode, if a read operation is performed when the device is selected.RDY/BUSYAfter configuration, RDY/BUSY is a user-programmable I/O pin.RDY/BUSY is pulled High with a high-impedance pull-up prior to INIT going High.During Master Parallel configuration, each change on the A0-A17 outputs (A0 - A21 forXC4000X) is preceded by a rising edge on RCLK, a redundant output signal. RCLK isRCLKOI/Ouseful for clocked PROMs. It is rarely used during configuration. After configuration,RCLK is a user-programmable I/O pin.As Mode inputs, these pins are sampled after INIT goes High to determine the configuration mode to be used. After configuration, M0 and M2 can be used as inputs, and M1can be used as a 3-state output. These three pins have no associated input or outputregisters.I (M0), During configuration, these pins have weak pull-up resistors. For the most popular conM0, M1, M2IO (M1), figuration mode, Slave Serial, the mode pins can thus be left unconnected. The threeI (M2) mode inputs can be individually configured with or without weak pull-up or pull-down resistors. A pull-down resistor value of 4.7 k is recommended.These pins can only be used as inputs or outputs when called out by special schematicdefinitions. To use these pins, place the library components MD0, MD1, and MD2 instead of the usual pad symbols. Input or output buffers must still be used.If boundary scan is used, this pin is the Test Data Output. If boundary scan is not used,this pin is a 3-state output without a register, after configuration is completed.TDOOOThis pin can be user output only when called out by special schematic definitions. Touse this pin, place the library component TDO instead of the usual pad symbol. An output buffer must still be used.VCC

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Table 16: Pin Descriptions (Continued)

Pin Name

I/OI/ODuringAfterConfig. Config.

TDI, TCK,TMS

I/Oor I(JTAG)

HDC

I/O

LDC

I/O

INIT

I/O

I/O

PGCK1 PGCK4(XC4000Eonly)

WeakPull-up

I or I/O

SGCK1 SGCK4(XC4000Eonly)

WeakPull-up

I or I/O

GCK1 GCK8(XC4000Xonly)

WeakPull-up

I or I/O

FCLK1 FCLK4(XC4000XLAandXC4000XVonly)

WeakPull-up

I or I/O

May 14, 1999 (Version 1.6)

Pin DescriptionIf boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Selectinputs respectively. They come directly from the pads, bypassing the IOBs. These pinscan also be used as inputs to the CLB logic after configuration is completed.If the BSCAN symbol is not placed in the design, all boundary scan functions are inhibited once configuration is completed, and these pins become user-programmable I/O.The pins can be used automatically or user-constrained. To use them, use "LOC=" orplace the library components TDI, TCK, and TMS instead of the usual pad symbols. Input or output buffers must still be used.High During Configuration (HDC) is driven High until the I/O go active. It is available asa control output indicating that configuration is not yet completed. After configuration,HDC is a user-programmable I/O pin.Low During Configuration (LDC) is driven Low until the I/O go active. It is available as acontrol output indicating that configuration is not yet completed. After configuration,LDC is a user-programmable I/O pin.Before and during configuration, INIT is a bidirectional signal. A 1 k - 10 k externalpull-up resistor is recommended.As an active-Low open-drain output, INIT is held Low during the power stabilization andinternal clearing of the configuration memory. As an active-Low input, it can be usedto hold the FPGA in the internal WAIT state before the start of configuration. Mastermode devices stay in a WAIT state an additional 30 to 300 s after INIT has gone High.During configuration, a Low on this output indicates that a configuration data error hasoccurred. After the I/O go active, INIT is a user-programmable I/O pin.Four Primary Global inputs each drive a dedicated internal global net with short delayand minimal skew. If not used to drive a global buffer, any of these pins is a user-programmable I/O.The PGCK1-PGCK4 pins drive the four Primary Global Buffers. Any input pad symbolconnected directly to the input of a BUFGP symbol is automatically placed on one ofthese pins.Four Secondary Global inputs each drive a dedicated internal global net with short delayand minimal skew. These internal global nets can also be driven from internal logic. Ifnot used to drive a global net, any of these pins is a user-programmable I/O pin.The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global Buffers. Any input pad symbol connected directly to the input of a BUFGS symbol is automatically placed on one of these pins.Eight inputs can each drive a Global Low-Skew buffer. In addition, each can drive a Global Early buffer. Each pair of global buffers can also be driven from internal logic, butmust share an input signal. If not used to drive a global buffer, any of these pins is auser-programmable I/O.Any input pad symbol connected directly to the input of a BUFGLS or BUFGE symbolis automatically placed on one of these pins.Four inputs can each drive a Fast Clock (FCLK) buffer which can deliver a clock signalto any IOB clock input in the octant of the die served by the Fast Clock buffer. Two FastClock buffers serve the two IOB octants on the left side of the die and the other two FastClock buffers serve the two IOB octants on the right side of the die. On each side of thedie, one Fast Clock buffer serves the upper octant and the other serves the lower octant.If not used to drive a Fast Clock buffer, any of these pins is a user-programmable I/O.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Table 16: Pin Descriptions (Continued)

Pin Name

I/OI/ODuringAfterConfig. Config.

Pin DescriptionThese four inputs are used in Asynchronous Peripheral mode. The chip is selectedwhen CS0 is Low and CS1 is High. While the chip is selected, a Low on Write Strobe(WS) loads the data present on the D0 - D7 inputs into the internal data buffer. A LowCS0, CS1,on Read Strobe (RS) changes D7 into a status output High if Ready, Low if Busy II/OWS, RSand drives D0 - D6 High.In Express mode, CS1 is used as a serial-enable signal for daisy-chaining.WS and RS should be mutually exclusive, but if both are Low simultaneously, the WriteStrobe overrides. After configuration, these are user-programmable I/O pins.During Master Parallel configuration, these 18 output pins address the configurationA0 - A17OI/OEPROM. After configuration, they are user-programmable I/O pins.A18 - A21During Master Parallel configuration with an XC4000X master, these 4 output pins add(XC4003XL toOI/O4 more bits to address the configuration EPROM. After configuration, they are user-proXC4085XL)grammable I/O pins. (See Master Parallel Configuration section for additional details.)During Master Parallel and Peripheral configuration, these eight input pins receive conD0 - D7II/Ofiguration data. After configuration, they are user-programmable I/O pins.During Slave Serial or Master Serial configuration, DIN is the serial configuration dataDINII/Oinput receiving data on the rising edge of CCLK. During Parallel configuration, DIN isthe D0 input. After configuration, DIN is a user-programmable I/O pin.During configuration in any mode but Express mode, DOUT is the serial configurationdata output that can drive the DIN of daisy-chained slave FPGAs. DOUT data changeson the falling edge of CCLK, one-and-a-half CCLK periods after it was received at theDOUTOI/ODIN input.In Express modefor XC4000E and XC4000X only, DOUT is the status output that candrive the CS1 of daisy-chained FPGAs, to enable and disable downstream devices.After configuration, DOUT is a user-programmable I/O pin.Unrestricted User-Programmable I/O PinsThese pins can be configured to be input and/or output after configuration is completed.WeakI/OI/OBefore configuration is completed, these pins have an internal high-value pull-up resisPull-uptor (25 k - 100 k) that defines the logic level as High.

Boundary ScanThe bed of nails has been the traditional method of testingelectronic assemblies. This approach has become lessappropriate, due to closer pin spacing and more sophisticated assembly methods like surface-mount technologyand multi-layer boards. The IEEE Boundary Scan Standard1149.1 was developed to facilitate board-level testing ofelectronic assemblies. Design and test engineers canimbed a standard test logic structure in their device toachieve high fault coverage for I/O and internal logic. Thisstructure is easily implemented with a four-pin interface onany boundary scan-compatible IC. IEEE 1149.1-compatible devices may be serial daisy-chained together, connected in parallel, or a combination of the two.The XC4000 Series implements IEEE 1149.1-compatibleBYPASS, PRELOAD/SAMPLE and EXTEST boundaryscan instructions. When the boundary scan configurationoption is selected, three normal user I/O pins become dedicated inputs for these functions. Another user output pinbecomes the dedicated boundary scan output. The details6-42

of how to enable this circuitry are covered later in this section.

By exercising these input signals, the user can serially loadcommands and data into these devices to control the driving of their outputs and to examine their inputs. Thismethod is an improvement over bed-of-nails testing. Itavoids the need to over-drive device outputs, and it reducesthe user interface to four pins. An optional fifth pin, a resetfor the control logic, is described in the standard but is notimplemented in Xilinx devices.The dedicated on-chip logic implementing the IEEE 1149.1functions includes a 16-state machine, an instruction register and a number of data registers. The functional detailscan be found in the IEEE 1149.1 specification and are alsodiscussed in the Xilinx application note XAPP 017: Boundary Scan in XC4000 Devices.Figure 40 on page 43 shows a simplified block diagram ofthe XC4000E Input/Output Block with boundary scanimplemented. XC4000X boundary scan logic is identical.

May 14, 1999 (Version 1.6)

XC4000E and XC4000X Series Field Programmable Gate Arrays

Figure 41 on page 44 is a diagram of the XC4000 Seriesboundary scan logic. It includes three bits of Data Registerper IOB, the IEEE 1149.1 Test Access Port controller, andthe Instruction Register with decodes.XC4000 Series devices can also be configured through theboundary scan logic. See Readback on page 55.

Data RegistersThe primary data register is the boundary scan register. Foreach IOB pin in the FPGA, bonded or not, it includes threebits for In, Out and 3-State Control. Non-IOB pins haveappropriate partial bit population for In or Out only. PROGRAM, CCLK and DONE are not included in the boundaryscan register. Each EXTEST CAPTURE-DR state capturesall In, Out, and 3-state pins.The data register also includes the following non-pin bits:TDO.T, and TDO.O, which are always bits 0 and 1 of the

data register, respectively, and BSCANT.UPD, which is

always the last bit of the data register. These three boundary scan bits are special-purpose Xilinx test signals.The other standard data register is the single flip-flopBYPASS register. It synchronizes data being passedthrough the FPGA to the next downstream boundary scandevice.The FPGA provides two additional data registers that canbe specified using the BSCAN macro. The FPGA providestwo user pins (BSCAN.SEL1 and BSCAN.SEL2) which arethe decodes of two user instructions. For these instructions,twocorrespondingpins(BSCAN.TDO1andBSCAN.TDO2) allow user scan data to be shifted out onTDO. The data register clock (BSCAN.DRCK) is availablefor control of test logic which the user may wish to implement with CLBs. The NAND of TCK and RUN-TEST-IDLEis also provided (BSCAN.IDLE).

Figure 41: XC4000 Series Boundary Scan Logic

Instruction SetThe XC4000 Series boundary scan instruction set alsoincludes instructions to configure the device and read backthe configuration data. The instruction set is coded asshown in Table 17.

Bit SequenceThe bit sequence within each IOB is: In, Out, 3-State. Theinput-only M0 and M2 mode pins contribute only the In bitto the boundary scan I/O data register, while the output-only M1 pin contributes all three bits.The first two bits in the I/O data register are TDO.T andTDO.O, which can be used for the capture of internal signals. The final bit is BSCANT.UPD, which can be used todrive an internal net. These locations are primarily used byXilinx for internal testing.From a cavity-up view of the chip (as shown in XDE orEpic), starting in the upper right chip corner, the boundaryscan data-register bits are ordered as shown in Figure 42.The device-specific pinout tables for the XC4000 Seriesinclude the boundary scan locations for each IOB pin.

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BSDL (Boundary Scan Description Language) files for

XC4000 Series devices are available on the Xilinx FTP site.

Including Boundary Scan in a Schematic

If boundary scan is only to be used during configuration, nospecial schematic elements need be included in the schematic or HDL code. In this case, the special boundary scanpins TDI, TMS, TCK and TDO can be used for user functions after configuration.To indicate that boundary scan remain enabled after configuration, place the BSCAN library symbol and connect theTDI, TMS, TCK and TDO pad symbols to the appropriatepins, as shown in Figure 43.Even if the boundary scan symbol is used in a schematic,the input pins TMS, TCK, and TDI can still be used asinputs to be routed to internal logic. Care must be taken notto force the chip into an undesired boundary scan state byinadvertently applying boundary scan input patterns tothese pins. The simplest way to prevent this is to keep TMSHigh, and then apply whatever signal is desired to TDI andTCK.

Left-edge IOBs (Top to Bottom)

MD1.TMD1.OMD1.IMD0.IMD2.IBottom-edge IOBs (Left to Right)

Right-edge IOBs (Bottom to Top)

B SCANT.UPDX6075

Figure 42:

Boundary Scan Bit Sequence

Avoiding Inadvertent Boundary Scan

If TMS or TCK is used as user I/O, care must be taken toensure that at least one of these pins is held constant during configuration. In some applications, a situation mayoccur where TMS or TCK is driven during configuration.This may cause the device to go into boundary scan modeand disrupt the configuration process.To prevent activation of boundary scan during configuration, do either of the following:

TMS: Tie High to put the Test Access Port controller

in a benign RESET stateTCK: Tie High or Lowdon't toggle this clock input.

For more information regarding boundary scan, refer to the

May 14, 1999 (Version 1.6)

BSCANTDI

TDI

TMS

TMS

TCK

TCK

IDLE

TDO1

SEL1

TDO2

SEL2

User Logic

Top-edge IOBs (Right to Left)

(TDI end)

IBUF

FromUser Logic

Pin/Logic

To UserLogic

TDO

TDO

DRCK

To UserLogic

X2675

Figure 43: Boundary Scan Schematic Example

ConfigurationConfiguration is the process of loading design-specific programming data into one or more FPGAs to define the functional operation of the internal blocks and theirinterconnections. This is somewhat like loading the command registers of a programmable peripheral chip. XC4000Series devices use several hundred bits of configurationdata per CLB and its associated interconnects. Each configuration bit defines the state of a static memory cell thatcontrols either a function look-up table bit, a multiplexerinput, or an interconnect pass transistor. The XACTstepdevelopment system translates the design into a netlist file.It automatically partitions, places and routes the logic andgenerates the configuration data in PROM format.

Special Purpose Pins

Three configuration mode pins (M2, M1, M0) are sampledprior to configuration to determine the configuration mode.After configuration, these pins can be used as auxiliaryconnections. M2 and M0 can be used as inputs, and M1can be used as an output. The XACTstep development system does not use these resources unless they are explicitlyspecified in the design entry. This is done by placing a special pad symbol called MD2, MD1, or MD0 instead of theinput or output pad symbol.In XC4000 Series devices, the mode pins have weakpull-up resistors during configuration. With all three modepins High, Slave Serial mode is selected, which is the mostpopular configuration mode. Therefore, for the most common configuration mode, the mode pins can be left unconnected. (Note, however, that the internal pull-up resistorvalue can be as high as 100 k.) After configuration, thesepins can individually have weak pull-up or pull-down resistors, as specified in the design. A pull-down resistor valueof 4.7 k is recommended.These pins are located in the lower left chip corner and arenear the readback nets. This location allows convenientrouting if compatibility with the XC2000 and XC3000 familyconventions of M0/RT, M1/RD is desired.

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Configuration Modes

Additional Address lines in XC4000 devices

XC4000E devices have six configuration modes. XC4000X

devices have the same six modes, plus an additional configuration mode. These modes are selected by a 3-bit inputcode applied to the M2, M1, and M0 inputs. There are threeself-loading Master modes, two Peripheral modes, and aSerial Slave mode, which is used primarily fordaisy-chained devices. The coding for mode selection isshown in Table 18.

The extra address lines are programmable in XC4000EX

devices. By default these address lines are not activated. Inthe default mode, the devices are compatible with existingXC4000 and XC4000E products. If desired, the extraaddress lines can be used by specifying the address linesoption in bitgen as 22 (bitgen -g AddressLines:22). Thelines (A18-A21) are driven when a master device detects,via the bitstream, that it should be using all 22 addresslines. Because these pins will initially be pulled high byinternal pull-ups, designers using Master Parallel Up modeshould use external pull down resistors on pins A18-A21. IfMaster Parallel Down mode is used external resistors arenot necessary.All 22 address lines are always active in Master Parallelmodes with XC4000XL devices. The additional addresslines behave identically to the lower order address lines. Ifthe Address Lines option in bitgen is set to 18, it will beignored by the XC4000XL device.The additional address lines (A18-A21) are not available inthe PC84 package.

Peripheral Modes

A detailed description of each configuration mode, with timing information, is included later in this data sheet. Duringconfiguration, some of the I/O pins are used temporarily forthe configuration process. All pins used during configuration are shown in Table 22 on page 58.

The two Peripheral modes accept byte-wide data from a

bus. A RDY/BUSY status is available as a handshake signal. In Asynchronous Peripheral mode, the internal oscillator generates a CCLK burst signal that serializes thebyte-wide data. CCLK can also drive slave devices. In thesynchronous mode, an externally supplied clock input toCCLK serializes the data.

Master Modes

Slave Serial Mode

The three Master modes use an internal oscillator to generate a Configuration Clock (CCLK) for driving potential slavedevices. They also generate address and timing for external PROM(s) containing the configuration data.

Master Parallel (Up or Down) modes generate the CCLK

signal and PROM addresses and receive byte parallel data.The data is internally serialized into the FPGA data-frameformat. The up and down selection generates startingaddresses at either zero or 3FFFF (3FFFFF when 22address lines are used), for compatibility with differentmicroprocessor addressing conventions. The Master Serialmode generates CCLK and receives the configuration datain serial form from a Xilinx serial-configuration PROM.

Multiple slave devices with identical configurations can be

wired with parallel DIN inputs. In this way, multiple devicescan be configured simultaneously.

* Can be considered byte-wide Slave Parallel

CCLK speed is selectable as either 1 MHz (default) or 8

MHz. Configuration always starts at the default slow frequency, then can switch to the higher frequency during thefirst frame. Frequency tolerance is -50% to +25%.

6-46

Serial Daisy Chain

Multiple devices with different configurations can be connected together in a daisy chain, and a single combinedbitstream used to configure the chain of slave devices.To configure a daisy chain of devices, wire the CCLK pinsof all devices in parallel, as shown in Figure 51 on page60. Connect the DOUT of each device to the DIN of thenext. The lead or master FPGA and following slaves eachpasses resynchronized configuration data coming from asingle source. The header data, including the length count,

May 14, 1999 (Version 1.6)

XC4000E and XC4000X Series Field Programmable Gate Arrays

is passed through and is captured by each FPGA when itrecognizes the 0010 preamble. Following the length-countdata, each FPGA outputs a High on DOUT until it hasreceived its required number of data frames.After an FPGA has received its configuration data, itpasses on any additional frame start bits and configurationdata on DOUT. When the total number of configurationclocks applied after memory initialization equals the valueof the 24-bit length count, the FPGAs begin the start-upsequence and become operational together. FPGA I/O arenormally released two CCLK cycles after the last configuration bit is received. Figure 47 on page 53 shows thestart-up timing for an XC4000 Series device.The daisy-chained bitstream is not simply a concatenationof the individual bitstreams. The PROM file formatter mustbe used to combine the bitstreams for a daisy-chained configuration.Multi-Family Daisy ChainAll Xilinx FPGAs of the XC2000, XC3000, and XC4000Series use a compatible bitstream format and can, therefore, be connected in a daisy chain in an arbitrarysequence. There is, however, one limitation. The leaddevice must belong to the highest family in the chain. If thechain contains XC4000 Series devices, the master normally cannot be an XC2000 or XC3000 device.The reason for this rule is shown in Figure 47 on page 53.Since all devices in the chain store the same length countvalue and generate or receive one common sequence ofCCLK pulses, they all recognize length-count match on thesame CCLK edge, as indicated on the left edge ofFigure 47. The master device then generates additionalCCLK pulses until it reaches its finish point F. The differentfamilies generate or require different numbers of additionalCCLK pulses until they reach F. Not reaching F means thatthe device does not really finish its configuration, althoughDONE may have gone High, the outputs became active,and the internal reset was released. For the XC4000 Seriesdevice, not reaching F means that readback cannot be ini-

May 14, 1999 (Version 1.6)

tiated and most boundary scan instructions cannot be

used.The user has some control over the relative timing of theseevents and can, therefore, make sure that they occur at theproper time and the finish point F is reached. Timing is controlled using options in the bitstream generation software.XC3000 Master with an XC4000 Series SlaveSome designers want to use an inexpensive lead device inperipheral mode and have the more precious I/O pins of theXC4000 Series devices all available for user I/O. Figure 44provides a solution for that case.This solution requires one CLB, one IOB and pin, and aninternal oscillator with a frequency of up to 5 MHz as aclock source. The XC3000 master device must be configured with late Internal Reset, which is the default option.One CLB and one IOB in the lead XC3000-family deviceare used to generate the additional CCLK pulse required bythe XC4000 Series devices. When the lead device removesthe internal RESET signal, the 2-bit shift register respondsto its clock input and generates an active Low output signalfor the duration of the subsequent clock period. An externalconnection between this output and CCLK thus creates theextra CCLK pulse.

OE/TReset0010110101etc. .

OutputConnectedto CCLK

Active Low Output

Active High Output

X5223

Figure 44: CCLK Generation for XC3000 Master

Driving an XC4000 Series Slave

6-47

XC4000E and XC4000X Series Field Programmable Gate Arrays

Setting CCLK Frequency

Data Stream Format

For Master modes, CCLK can be generated in either of two

frequencies. In the default slow mode, the frequencyranges from 0.5 MHz to 1.25 MHz for XC4000E andXC4000EX devices and from 0.6 MHz to 1.8 MHz forXC4000XL devices. In fast CCLK mode, the frequencyranges from 4 MHz to 10 MHz for XC4000E/EX devices andfrom 5 MHz to 15 MHz for XC4000XL devices. The frequency is selected by an option when running the bitstreamgeneration software. If an XC4000 Series Master is drivingan XC3000- or XC2000-family slave, slow CCLK modemust be used. In addition, an XC4000XL device driving aXC4000E or XC4000EX should use slow mode. Slow modeis the default.

The data stream (bitstream) format is identical for all configuration modes.

The data stream formats are shown in Table 19. Bit-serial

data is read from left to right, and byte-parallel data is effectively assembled from this serial bitstream, with the first bitin each byte assigned to D0.The configuration data stream begins with a string of eightones, a preamble code, followed by a 24-bit length countand a separator field of ones. This header is followed by theactual configuration data in frames. The length and numberof frames depends on the device type (see Table 20 andTable 21). Each frame begins with a start field and endswith an error check. A postamble code is required to signalthe end of data for a single device. In all cases, additionalstart-up bytes of data are required to provide four clocks forthe startup sequence at the end of configuration. Longdaisy chains require additional startup bytes to shift the lastdata through the chain. All startup bytes are dont-cares;these bytes are not included in bitstreams created by theXilinx software.A selection of CRC or non-CRC error checking is allowedby the bitstream generation software. The non-CRC errorchecking tests for a designated end-of-frame field for eachframe. For CRC error checking, the software calculates arunning CRC and inserts a unique four-bit partial check atthe end of each frame. The 11-bit CRC check of the lastframe of an FPGA includes the last seven data bits.Detection of an error results in the suspension of data loading and the pulling down of the INIT pin. In Master modes,CCLK and address signals continue to operate externally.The user must detect INIT and initialize a new configurationby pulsing the PROGRAM pin Low or cycling Vcc.

Notes: 1. Bits per Frame = (10 x number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bitsNumber of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1Program Data = (Bits per Frame x Number of Frames) + 8 postamble bitsPROM Size = Program Data + 40 (header) + 82. The user can add more one bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end ofany frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra onebits, even for extra leading ones at the beginning of the header.

Cyclic Redundancy Check (CRC) for

Configuration and ReadbackThe Cyclic Redundancy Check is a method of error detection in data transmission applications. Generally, the transmitting system performs a calculation on the serialbitstream. The result of this calculation is tagged onto thedata stream as additional check bits. The receiving systemperforms an identical calculation on the bitstream and compares the result with the received checksum.Each data frame of the configuration bitstream has fourerror bits at the end, as shown in Table 19. If a frame dataerror is detected during the loading of the FPGA, the con-

May 14, 1999 (Version 1.6)

figuration process with a potentially corrupted bitstream is

terminated. The FPGA pulls the INIT pin Low and goes intoa Wait state.During Readback, 11 bits of the 16-bit checksum are addedto the end of the Readback data stream. The checksum iscomputed using the CRC-16 CCITT polynomial, as shownin Figure 45. The checksum consists of the 11 most significant bits of the 16-bit code. A change in the checksum indicates a change in the Readback bitstream. A comparisonto a previous checksum is meaningful only if the readbackdata is independent of the current device state. CLB outputs should not be included (Read Capture option not

6-49

XC4000E and XC4000X Series Field Programmable Gate Arrays

used), and if RAM is present, the RAM content must beunchanged.Statistically, one error out of 2048 might go undetected.

Configuration Sequence

VCC>3.5 V

Boundary ScanInstructionsAvailable:

Yes

There are four major steps in the XC4000 Series power-up

configuration sequence.

Test M0 GenerateOne Time-Out Pulseof 16 or 64 ms

Configuration Memory Clear

InitializationConfigurationStart-Up

YesKeep ClearingConfiguration Memory

The full process is illustrated in Figure 46.

Configuration Memory Clear

When power is first applied or is reapplied to an FPGA, aninternal circuit forces initialization of the configuration logic.When Vcc reaches an operational level, and the circuitpasses the write and read test of a sample pair of configuration bits, a time delay is started. This time delay is nominally 16 ms, and up to 10% longer in the low-voltagedevices. The delay is four times as long when in MasterModes (M0 Low), to allow ample time for all slaves to reacha stable Vcc. When all INIT pins are tied together, as recommended, the longest delay takes precedence. Therefore, devices with different time delays can easily be mixedand matched in a daisy chain.

Figure 45: Circuit for Generating CRC-16

Figure 46: Power-up Configuration Sequence

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Low. During this time delay, or as long as the PROGRAMinput is asserted, the configuration logic is held in a Configuration Memory Clear state. The configuration-memoryframes are consecutively initialized, using the internal oscillator.At the end of each complete pass through the frameaddressing, the power-on time-out delay circuitry and thelevel of the PROGRAM pin are tested. If neither is asserted,the logic initiates one additional clearing of the configuration frames and then tests the INIT input.

InitializationDuring initialization and configuration, user pins HDC, LDC,INIT and DONE provide status outputs for the system interface. The outputs LDC, INIT and DONE are held Low andHDC is held High starting at the initial application of power.The open drain INIT pin is released after the final initialization pass through the frame addresses. There is a deliberate delay of 50 to 250 s (up to 10% longer for low-voltagedevices) before a Master-mode device recognizes an inactive INIT. Two internal clocks after the INIT pin is recognizedas High, the FPGA samples the three mode lines to determine the configuration mode. The appropriate interfacelines become active and the configuration preamble anddata can be loaded.ConfigurationThe 0010 preamble code indicates that the following 24 bitsrepresent the length count. The length count is the totalnumber of configuration clocks needed to load the complete configuration data. (Four additional configurationclocks are required to complete the configuration process,as discussed below.) After the preamble and the lengthcount have been passed through to all devices in the daisychain, DOUT is held High to prevent frame start bits fromreaching any daisy-chained devices.A specific configuration bit, early in the first frame of a master device, controls the configuration-clock rate and canincrease it by a factor of eight. Therefore, if a fast configuration clock is selected by the bitstream, the slower clockrate is used until this configuration bit is detected.Each frame has a start field followed by the frame-configuration data bits and a frame error field. If a frame data erroris detected, the FPGA halts loading, and signals the errorby pulling the open-drain INIT pin Low. After all configuration frames have been loaded into an FPGA, DOUT againfollows the input data so that the remaining data is passedon to the next device.

Delaying Configuration After Power-Up

There are two methods of delaying configuration afterpower-up: put a logic Low on the PROGRAM input, or pullthe bidirectional INIT pin Low, using an open-collector(open-drain) driver. (See Figure 46 on page 50.)

rise time is excessive or poorly defined. As long as PROGRAM is Low, the FPGA keeps clearing its configurationmemory. When PROGRAM goes High, the configurationmemory is cleared one more time, followed by the beginning of configuration, provided the INIT input is not externally held Low. Note that a Low on the PROGRAM inputautomatically forces a Low on the INIT output. The XC4000Series PROGRAM pin has a permanent weak pull-up.Using an open-collector or open-drain driver to hold INITLow before the beginning of configuration causes theFPGA to wait after completing the configuration memoryclear operation. When INIT is no longer held Low externally, the device determines its configuration mode by capturing its mode pins, and is ready to start the configurationprocess. A master device waits up to an additional 250 sto make sure that any slaves in the optional daisy chainhave seen that INIT is High.

Start-UpStart-up is the transition from the configuration process tothe intended user operation. This transition involves achange from one clock source to another, and a changefrom interfacing parallel or serial configuration data wheremost outputs are 3-stated, to normal operation with I/O pinsactive in the user-system. Start-up must make sure that theuser-logic wakes up gracefully, that the outputs becomeactive without causing contention with the configuration signals, and that the internal flip-flops are released from theglobal Reset or Set at the right time.Figure 47 describes start-up timing for the three Xilinx families in detail. The configuration modes can use any of thefour timing sequences.To access the internal start-up signals, place the STARTUPlibrary symbol.Start-up TimingDifferent FPGA families have different start-up sequences.The XC2000 family goes through a fixed sequence. DONEgoes High and the internal global Reset is de-activated oneCCLK period after the I/O become active.The XC3000A family offers some flexibility. DONE can beprogrammed to go High one CCLK period before or afterthe I/O become active. Independent of DONE, the internalglobal Reset is de-activated one CCLK period before orafter the I/O become active.The XC4000 Series offers additional flexibility. The threeevents DONE going High, the internal Set/Reset beingde-activated, and the user I/O going active can all occurin any arbitrary sequence. Each of them can occur oneCCLK period before or after, or simultaneous with, any ofthe others. This relative timing is selected by means of software options in the bitstream generation software.

A Low on the PROGRAM input is the more radical

approach, and is recommended when the power-supplyMay 14, 1999 (Version 1.6)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

The default option, and the most practical one, is for DONEto go High first, disconnecting the configuration data sourceand avoiding any contention when the I/Os become activeone clock later. Reset/Set is then released another clockperiod later to make sure that user-operation starts fromstable internal conditions. This is the most commonsequence, shown with heavy lines in Figure 47, but thedesigner can modify it to meet particular requirements.Normally, the start-up sequence is controlled by the internaldevice oscillator output (CCLK), which is asynchronous tothe system clock.

received since INIT went High equals the loaded value of

the length count.The next rising clock edge sets a flip-flop Q0, shown inFigure 48. Q0 is the leading bit of a 5-bit shift register. Theoutputs of this register can be programmed to control threeevents.

The release of the open-drain DONE output

The change of configuration-related pins to the userfunction, activating all IOBs.The termination of the global Set/Reset initialization ofall CLB and IOB storage elements.

XC4000 Series offers another start-up clocking option,

UCLK_NOSYNC. The three events described above neednot be triggered by CCLK. They can, as a configurationoption, be triggered by a user clock. This means that thedevice can wake up in synchronism with the user system.

The DONE pin can also be wire-ANDed with DONE pins of

other FPGAs or with other external signals, and can thenbe used as input to bit Q3 of the start-up register. This iscalled Start-up Timing Synchronous to Done In and isselected by either CCLK_SYNC or UCLK_SYNC.

When the UCLK_SYNC option is enabled, the user can

externally hold the open-drain DONE output Low, and thusstall all further progress in the start-up sequence untilDONE is released and has gone High. This option can beused to force synchronization of several FPGAs to a common user clock, or to guarantee that all devices are successfully configured before any I/Os go active.

When DONE is not used as an input, the operation is called

Start-up Timing Not Synchronous to DONE In, and isselected by either CCLK_NOSYNC or UCLK_NOSYNC.

If either of these two options is selected, and no user clock

is specified in the design or attached to the device, the chipcould reach a point where the configuration of the device iscomplete and the Done pin is asserted, but the outputs donot become active. The solution is either to recreate the bitstream specifying the start-up clock as CCLK, or to supplythe appropriate user clock.Start-up Sequence

As a configuration option, the start-up control register

beyond Q0 can be clocked either by subsequent CCLKpulses or from an on-chip user net called STARTUP.CLK.These signals can be accessed by placing the STARTUPlibrary symbol.Start-up from CCLKIf CCLK is used to drive the start-up, Q0 through Q3 provide the timing. Heavy lines in Figure 47 show the defaulttiming, which is compatible with XC2000 and XC3000devices using early DONE and late Reset. The thin linesindicate all other possible timing options.

Figure 47: Start-up Timing

May 14, 1999 (Version 1.6)

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XC4000E and XC4000X Series Field Programmable Gate Arrays

Start-up from a User Clock (STARTUP.CLK)

Release of User I/O After DONE Goes High

When, instead of CCLK, a user-supplied start-up clock is

selected, Q1 is used to bridge the unknown phase relationship between CCLK and the user clock. This arbitrationcauses an unavoidable one-cycle uncertainty in the timingof the rest of the start-up sequence.

By default, the user I/O are released one CCLK cycle afterthe DONE pin goes High. If CCLK is not clocked afterDONE goes High, the outputs remain in their initial state 3-stated, with a 50 k - 100 k pull-up. The delay fromDONE High to active user I/O is controlled by an option tothe bitstream generation software.

DONE Goes High to Signal End of Configuration

XC4000 Series devices read the expected length countfrom the bitstream and store it in an internal register. Thelength count varies according to the number of devices andthe composition of the daisy chain. Each device also countsthe number of CCLKs during configuration.Two conditions have to be met in order for the DONE pin togo high:

the chip's internal memory must be full, and

the configuration length count must be met, exactly.

This is important because the counter that determines

when the length count is met begins with the very firstCCLK, not the first one after the preamble.Therefore, if a stray bit is inserted before the preamble, orthe data source is not ready at the time of the first CCLK,the internal counter that holds the number of CCLKs will beone ahead of the actual number of data bits read. At theend of configuration, the configuration memory will be full,but the number of bits in the internal counter will not matchthe expected length count.As a consequence, a Master mode device will continue tosend out CCLKs until the internal counter turns over tozero, and then reaches the correct length count a secondtime. This will take several seconds [224 CCLK period] which is sometimes interpreted as the device not configuring at all.If it is not possible to have the data ready at the time of thefirst CCLK, the problem can be avoided by increasing thenumber in the length count by the appropriate value. TheXACT User Guide includes detailed information about manually altering the length count.Note that DONE is an open-drain output and does not goHigh unless an internal pull-up is activated or an externalpull-up is attached. The internal pull-up is activated as thedefault by the bitstream generation software.

6-54

Release of Global Set/Reset After DONE Goes

HighBy default, Global Set/Reset (GSR) is released two CCLKcycles after the DONE pin goes High. If CCLK is notclocked twice after DONE goes High, all flip-flops are heldin their initial set or reset state. The delay from DONE Highto GSR inactive is controlled by an option to the bitstreamgeneration software.

Configuration Complete After DONE Goes High

Three full CCLK cycles are required after the DONE pingoes High, as shown in Figure 47 on page 53. If CCLK isnot clocked three times after DONE goes High, readbackcannot be initiated and most boundary scan instructionscannot be used.

Configuration Through the Boundary Scan

PinsXC4000 Series devices can be configured through theboundary scan pins. The basic procedure is as follows:

Power up the FPGA with INIT held Low (or drive thePROGRAM pin Low for more than 300 ns followed by aHigh while holding INIT Low). Holding INIT Low allowsenough time to issue the CONFIG command to theFPGA. The pin can be used as I/O after configuration ifa resistor is used to hold INIT Low. Issue the CONFIG command to the TMS input Wait for INIT to go High Sequence the boundary scan Test Access Port to theSHIFT-DR state Toggle TCK to clock data into TDI pin.The user must account for all TCK clock cycles after INITgoes High, as all of these cycles affect the Length Countcompare.For more detailed information, refer to the Xilinx applicationnote XAPP017, Boundary Scan in XC4000 Devices. Thisapplication note also applies to XC4000E and XC4000Xdevices.

CONTROLLED BY STARTUP SYMBOL

GLOBAL 3-STATE OF ALL IOBs

" FINISHED "

ENABLES BOUNDARYSCAN, READBACK ANDCONTROLS THE OSCILLATOR

Q4

1S

MK

CLEAR MEMORYCCLK

STARTUP.CLKUSER NET

CONFIGURATION BIT OPTIONS SELECTED BY USER IN "MAKEBITS"

X1528

Figure 48: Start-up Logic

ReadbackThe user can read back the content of configuration memory and the level of certain internal nodes without interfering with the normal operation of the device.Readback not only reports the downloaded configurationbits, but can also include the present state of the device,represented by the content of all flip-flops and latches inCLBs and IOBs, as well as the content of function generators used as RAMs.Note that in XC4000 Series devices, configuration data isnot inverted with respect to configuration as it is in XC2000and XC3000 families.XC4000 Series Readback does not use any dedicatedpins, but uses four internal nets (RDBK.TRIG, RDBK.DATA,RDBK.RIP and RDBK.CLK) that can be routed to any IOB.To access the internal Readback signals, place the READ-

May 14, 1999 (Version 1.6)

BACK library symbol and attach the appropriate pad symbols, as shown in Figure 49.After Readback has been initiated by a High level onRDBK.TRIG after configuration, the RDBK.RIP (Read InProgress) output goes High on the next rising edge ofRDBK.CLK. Subsequent rising edges of this clock shift outReadback data on the RDBK.DATA net.Readback data does not include the preamble, but startswith five dummy bits (all High) followed by the Start bit(Low) of the first frame. The first two data bits of the firstframe are always High.Each frame ends with four error check bits. They are readback as High. The last seven bits of the last frame are alsoread back as High. An additional Start bit (Low) and an11-bit Cyclic Redundancy Check (CRC) signature follow,before RDBK.RIP returns Low.

6-55

XC4000E and XC4000X Series Field Programmable Gate Arrays

IF UNCONNECTED,DEFAULT IS CCLK

DATA

CLKMD0

READ_TRIGGER

TRIG

READBACK

RIP

READ_DATA

MD1

OBUF

IBUF

X1786

Figure 49: Readback Schematic Example

Readback Options

When the Read Capture option is selected, the readback

data stream includes sampled values of CLB and IOB signals. The rising edge of RDBK.TRIG latches the invertedvalues of the four CLB outputs, the IOB output flip-flops andthe input signals I1 and I2. Note that while the bits describing configuration (interconnect, function generators, andRAM content) are not inverted, the CLB and IOB output signals are inverted.When the Read Capture option is not selected, the valuesof the capture bits reflect the configuration data originallywritten to those memory locations.If the RAM capability of the CLBs is used, RAM data areavailable in readback, since they directly overwrite the Fand G function-table configuration of the CLB.RDBK.TRIG is located in the lower-left corner of the device,as shown in Figure 50.

Read AbortWhen the Read Abort option is selected, a High-to-Lowtransition on RDBK.TRIG terminates the readback operation and prepares the logic to accept another trigger.After an aborted readback, additional clocks (up to onereadback clock per configuration frame) may be required tore-initialize the control logic. The status of readback is indicated by the output control net RDBK.RIP. RDBK.RIP isHigh whenever a readback is in progress.

Clock SelectCCLK is the default clock. However, the user can insertanother clock on RDBK.CLK. Readback control and dataare clocked on rising edges of RDBK.CLK. If readbackmust be inhibited for security reasons, the readback controlnets are simply not connected.RDBK.CLK is located in the lower right chip corner, asshown in Figure 50.

6-56

I/OPROGRAMMABLEINTERCONNECT

rdbk

Read Capture

I/O

TRIGDATARIP

Readback options are: Read Capture, Read Abort, and

Clock Select. They are set with the bitstream generationsoftware.

I/O

I/O

I/O

rdclk

X1787

Figure 50: READBACK Symbol in Graphical Editor

Violating the Maximum High and Low Time

Specification for the Readback ClockThe readback clock has a maximum High and Low timespecification. In some cases, this specification cannot bemet. For example, if a processor is controlling readback, aninterrupt may force it to stop in the middle of a readback.This necessitates stopping the clock, and thus violating thespecification.The specification is mandatory only on clocking data at theend of a frame prior to the next start bit. The transfer mechanism will load the data to a shift register during the last sixclock cycles of the frame, prior to the start bit of the following frame. This loading process is dynamic, and is thesource of the maximum High and Low time requirements.Therefore, the specification only applies to the six clockcycles prior to and including any start bit, including theclocks before the first start bit in the readback data stream.At other times, the frame data is already in the register andthe register is not dynamic. Thus, it can be shifted out justlike a regular shift register.The user must precisely calculate the location of the readback data relative to the frame. The system must keep trackof the position within a data frame, and disable interruptsbefore frame boundaries. Frame lengths and data formatsare listed in Table 19, Table 20 and Table 21.

Readback with the XChecker Cable

The XChecker Universal Download/Readback Cable andLogic Probe uses the readback feature for bitstream verification. It can also display selected internal signals on thePC or workstation screen, functioning as a low-cost in-circuit emulator.

May 14, 1999 (Version 1.6)

XC4000E and XC4000X Series Field Programmable Gate Arrays

XC4000E/EX/XL Program Readback Switching Characteristic GuidelinesTesting of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patternsthat are taken at device introduction, prior to any process improvements.The following guidelines reflect worst-case values over the recommended operating conditions.

May 14, 1999 (Version 1.6)

XC4000E and XC4000X Series Field Programmable Gate Arrays

Slave Serial Mode

In Slave Serial mode, an external signal drives the CCLKinput of the FPGA. The serial configuration bitstream mustbe available at the DIN input of the lead FPGA a shortsetup time before each rising CCLK edge.The lead FPGA then presents the preamble dataand alldata that overflows the lead deviceon its DOUT pin.

There is an internal delay of 0.5 CCLK periods, which

means that DOUT changes on the falling CCLK edge, andthe next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge.Figure 51 shows a full master/slave system. An XC4000Series device in Slave Serial mode should be connected asshown in the third device from the left.Slave Serial mode is selected by a <111> on the mode pins(M2, M1, M0). Slave Serial is the default mode if the modepins are left unconnected, as they have weak pull-up resistors during configuration.

NOTE:M2, M1, M0 can be shortedto VCC if not used as I/O

NOTE:M2, M1, M0 can be shortedto Ground if not used as I/OVCCN/C4.7 K

4.7 K

4.7 K

4.7 K

4.7 K

4.7 KM0 M1M2

N/CDOUT

M0 M1M2

DIN

MASTERSERIAL

XC1700D

+5 V

4.7 K

CCLK

DOUT

CCLK

VCC

XC4000E/X

M0 M1M2

CLKDATA

PROGRAM

LDC

CE

DONE

INIT

RESET/OE

CEO

DIN

DOUT

CCLK

XC4000E/X,XC5200

XC3100A

SLAVE

SLAVE

VPP

DIN

PWRDN

PROGRAM

RESET

DONE

INIT

D/P

INIT

(Low Reset Option Used)

PROGRAM

X9025

Figure 51: Master/Slave Serial Mode Circuit Diagram

DIN

Bit n1 TDCC

Bit n + 12 TCCD

5 TCCL

CCLK4 TCCHDOUT(Output)

3 TCCO

Bit n - 1

Bit nX5379

CCLK

DescriptionDIN setupDIN holdDIN to DOUTHigh timeLow timeFrequency

12345

SymbolTDCCTCCDTCCOTCCHTCCLFCC

Min200

Max

30454510

UnitsnsnsnsnsnsMHz

Note: Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.

Figure 52: Slave Serial Mode Programming Switching Characteristics

6-60

May 14, 1999 (Version 1.6)

XC4000E and XC4000X Series Field Programmable Gate Arrays

Master Serial Mode

For actual timing values please refer to Configuration

Switching Characteristics on page 68. Be sure that theserial PROM and slaves are fast enough to support thisdata rate. XC2000, XC3000/A, and XC3100A devices donot support the Fast ConfigRate option.

In Master Serial mode, the CCLK output of the lead FPGA

drives a Xilinx Serial PROM that feeds the FPGA DIN input.Each rising edge of the CCLK output increments the SerialPROM internal address counter. The next data bit is put onthe SPROM data output, connected to the FPGA DIN pin.The lead FPGA accepts this data on the subsequent risingCCLK edge.

The SPROM CE input can be driven from either LDC or

DONE. Using LDC avoids potential contention on the DINpin, if this pin is configured as user-I/O, but LDC is thenrestricted to be a permanently High user output after configuration. Using DONE can also avoid contention on DIN,provided the early DONE option is invoked.

The lead FPGA then presents the preamble dataand all

data that overflows the lead deviceon its DOUT pin.There is an internal pipeline delay of 1.5 CCLK periods,which means that DOUT changes on the falling CCLKedge, and the next FPGA in the daisy chain accepts dataon the subsequent rising CCLK edge.

Figure 51 on page 60 shows a full master/slave system.

The leftmost device is in Master Serial mode.Master Serial mode is selected by a <000> on the modepins (M2, M1, M0).

In the bitstream generation software, the user can specify

Fast ConfigRate, which, starting several bits into the firstframe, increases the CCLK frequency by a factor of eight.CCLK(Output)2 TCKDS1Serial Data In

TDSCKn

Serial DOUT(Output)

n3

n+1

n2

n+2

n1

nX3223

CCLK

DescriptionDIN setupDIN hold

Symbol1TDSCK2TCKDS

Min200

Max

Unitsnsns

Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PROGRAMLow until Vcc is valid.2. Master Serial mode timing is based on testing in slave mode.

Additional Address lines in XC4000 devices

The eight data bits are serialized in the lead FPGA, whichthen presents the preamble dataand all data that overflows the lead deviceon its DOUT pin. There is an internal delay of 1.5 CCLK periods, after the rising CCLK edgethat accepts a byte of data (and also changes the EPROMaddress) until the falling CCLK edge that makes the LSB(D0) of this byte appear at DOUT. This means that DOUTchanges on the falling CCLK edge, and the next FPGA inthe daisy chain accepts data on the subsequent risingCCLK edge.

The extra address lines are programmable in XC4000EX

devices. By default these address lines are not activated. Inthe default mode, the devices are compatible with existingXC4000 and XC4000E products. If desired, the extraaddress lines can be used by specifying the address linesoption in bitgen as 22 (bitgen -g AddressLines:22). Thelines (A18-A21) are driven when a master device detects,via the bitstream, that it should be using all 22 addresslines. Because these pins will initially be pulled high byinternal pull-ups, designers using Master Parallel Up modeshould use external pull down resistors on pins A18-A21. IfMaster Parallel Down mode is used external resistors arenot necessary.

The PROM address pins can be incremented or decremented, depending on the mode pin settings. This optionallows the FPGA to share the PROM with a wide variety ofmicroprocessors and micro controllers. Some processorsmust boot from the bottom of memory (all zeros) while others must boot from the top. The FPGA is flexible and canload its configuration bitstream from either end of the memory.

All 22 address lines are always active in Master Parallel

modes with XC4000XL devices. The additional addresslines behave identically to the lower order address lines. Ifthe Address Lines option in bitgen is set to 18, it will beignored by the XC4000XL device.

CCLKUSER CONTROL OF HIGHERORDER PROM ADDRESS BITSCAN BE USED TO SELECT BETWEENALTERNATIVE CONFIGURATIONS

XC4000E/XSLAVE

PROGRAM

PROGRAM

A9

A9

D7

A8

A8

D6

A7

A7

D7

D5

A6

A6

D6

D4

A5

A5

D5

D3

A4

A4

D4

D2

A3

A3

D3

D1

A2

A2

D2

D0

A1

A1

D1

A0

A0

D0

DONE

OE

DONE

INIT

CE

DATA BUS

PROGRAMX9026

Figure 54: Master Parallel Mode Circuit Diagram

6-62

May 14, 1999 (Version 1.6)

XC4000E and XC4000X Series Field Programmable Gate Arrays

A0-A17(output)

Address for Byte n

Address for Byte n + 1

1 TRAC

D0-D7

Byte3 TRCD

2 TDRCRCLK(output)7 CCLKs

CCLK

CCLK(output)

DOUT(output)

D6

D7

Byte n - 1

RCLK

DescriptionDelay to Address validData setup timeData hold time

123

SymbolTRACTDRCTRCD

Min0600

X6078

Max200

Unitsnsnsns

Notes: 1. At power-up, Vcc must rise from 2.0 V to Vcc min in less than 25 ms, otherwise delay configuration by pulling PROGRAMLow until Vcc is valid.2. The first Data byte is loaded and CCLK starts at the end of the first RCLK active cycle (rising edge).

May 14, 1999 (Version 1.6)

6-63

XC4000E and XC4000X Series Field Programmable Gate Arrays

Synchronous Peripheral ModeSynchronous Peripheral mode can also be consideredSlave Parallel mode. An external signal drives the CCLKinput(s) of the FPGA(s). The first byte of parallel configuration data must be available at the Data inputs of the leadFPGA a short setup time before the rising CCLK edge.Subsequent data bytes are clocked in on every eighth consecutive rising CCLK edge.The same CCLK edge that accepts data, also causes theRDY/BUSY output to go High for one CCLK period. The pinname is a misnomer. In Synchronous Peripheral mode it isreally an ACKNOWLEDGE signal. Synchronous operationdoes not require this response, but it is a meaningful signalfor test purposes. Note that RDY/BUSY is pulled High witha high-impedance pullup prior to INIT going High.

The lead FPGA serializes the data and presents the preamble data (and all data that overflows the lead device) onits DOUT pin. There is an internal delay of 1.5 CCLK periods, which means that DOUT changes on the falling CCLKedge, and the next FPGA in the daisy chain accepts dataon the subsequent rising CCLK edge.In order to complete the serial shift operation, 10 additionalCCLK rising edges are required after the last data byte hasbeen loaded, plus one more CCLK cycle for eachdaisy-chained device.Synchronous Peripheral mode is selected by a <011> onthe mode pins (M2, M1, M0).

Notes: 1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in thefirst data byte on the second rising edge of CCLK after INIT goes High. Subsequent data bytes are clocked in on everyeighth consecutive rising edge of CCLK.2. The RDY/BUSY line goes High for one CCLK period after data has been clocked in, although synchronous operation doesnot require such a response.3. The pin name RDY/BUSY is a misnomer. In Synchronous Peripheral mode this is really an ACKNOWLEDGE signal.4. Note that data starts to shift out serially on the DOUT pin 0.5 CCLK periods after it was loaded in parallel. Therefore,additional CCLK pulses are clearly required after the last byte has been loaded.

May 14, 1999 (Version 1.6)

XC4000E and XC4000X Series Field Programmable Gate Arrays

Asynchronous Peripheral Mode

The READY/BUSY handshake can be ignored if the delay

from any one Write to the end of the next Write is guaranteed to be longer than 10 CCLK periods.

Write to FPGAAsynchronous Peripheral mode uses the trailing edge ofthe logic AND condition of WS and CS0 being Low and RSand CS1 being High to accept byte-wide data from a microprocessor bus. In the lead FPGA, this data is loaded into adouble-buffered UART-like parallel-to-serial converter andis serially shifted into the internal logic.

Status ReadThe logic AND condition of the CS0, CS1and RS inputsputs the device status on the Data bus.

The lead FPGA presents the preamble data (and all datathat overflows the lead device) on its DOUT pin. TheRDY/BUSY output from the lead FPGA acts as a handshake signal to the microprocessor. RDY/BUSY goes Lowwhen a byte has been received, and goes High again whenthe byte-wide input buffer has transferred its informationinto the shift register, and the buffer is ready to receive newdata. A new write may be started immediately, as soon asthe RDY/BUSY output has gone Low, acknowledgingreceipt of the previous data. Write may not be terminateduntil RDY/BUSY is High again for one CCLK period. Notethat RDY/BUSY is pulled High with a high-impedancepull-up prior to INIT going High.

D7 High indicates Ready

D7 Low indicates BusyD0 through D6 go unconditionally High

It is mandatory that the whole start-up sequence be started

and completed by one byte-wide input. Otherwise, the pinsused as Write Strobe or Chip Enable might become activeoutputs and interfere with the final byte transfer. If thistransfer does not occur, the start-up sequence is not completed all the way to the finish (point F in Figure 47 on page53).In this case, at worst, the internal reset is not released. Atbest, Readback and Boundary Scan are inhibited. Thelength-count value, as generated by the XACTstep software, ensures that these problems never occur.Although RDY/BUSY is brought out as a separate signal,microprocessors can more easily read this information onone of the data lines. For this purpose, D7 represents theRDY/BUSY status when RS is Low, WS is High, and thetwo chip select lines are both active.

The length of the BUSY signal depends on the activity in

the UART. If the shift register was empty when the new bytewas received, the BUSY signal lasts for only two CCLKperiods. If the shift register was still full when the new bytewas received, the BUSY signal can be as long as nineCCLK periods.

Asynchronous Peripheral mode is selected by a <101> on

the mode pins (M2, M1, M0).

Note that after the last byte has been entered, only seven ofits bits are shifted out. CCLK remains High with DOUTequal to bit 6 (the next-to-last bit) of the last byte entered.

Notes: 1. Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous byteprocessing and the phase of the internal timing generator for CCLK.3. CCLK and DOUT timing is tested in slave mode.4. TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortestTBUSY occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new wordis loaded into the input register before the second-level buffer has started shifting out data

This timing diagram shows very relaxed requirements. Data need not be held beyond the rising edge of WS. RDY/BUSY willgo active within 60 ns after the end of WS. A new write may be asserted immediately after RDY/BUSY goes Low, but writemay not be terminated until RDY/BUSY has been High for one CCLK period.Figure 59: Asynchronous Peripheral Mode Programming Switching Characteristics

Slave and Peripheral Modes (All)

May 14, 1999 (Version 1.6)

XC4000E and XC4000X Series Field Programmable Gate Arrays

Product AvailabilityTable 24, Table 25, and Table 26 show the planned packages and speed grades for XC4000-Series devices. Call your localsales office for the latest availability information, or see the Xilinx website at http://www.xilinx.com for the latest revision ofthe specifications.

PINS

84

100

100

144

144

160

160

176

176

208

208

240

240

256

299

304

352

411

432

475

559

560

TYPE

Plast.PLCC

Plast.PQFP

Plast.VQFP

Plast.TQFP

High-Perf.TQFP

High-Perf.QFP

Plast.PQFP

Plast.TQFP

High-Perf.TQFP

High-Perf.QFP

Plast.PQFP

High-Perf.QFP

Plast.PQFP

Plast.BGA

Ceram.PGA

High-Perf.QFP

Plast.BGA

Ceram.PGA

Plast.BGA

Ceram.PGA

Ceram.PGA

Plast.BGA

CODE

PC84

PQ100

VQ100

TQ144

HT144

HQ160

PQ160

TQ176

HT176

HQ208

PQ208

HQ240

PQ240

BG256

PG299

HQ304

BG352

PG411

BG432

PG475

PG559

BG560

Table 24: Component Availability Chart for XC4000XL FPGAs

-3

CI

CI

CI

-2

CI

CI

CI

-1

CI

CI

CI

-09C

-3

CI

CI

CI

CI

CI

CI

-2

CI

CI

CI

CI

CI

-1

CI

CI

CI

CI

CI

CI

-09C

-3

CI

CI

CI

CI

CI

CI

CI

-2

CI

CI

CI

CI

CI

CI

CI

-1

CI

CI

CI

CI

CI

CI

CI

-09C

XC4002XL

XC4005XL

XC4010XL

XC4013XL

XC4020XL

XC4028XL

XC4036XL

XC4044XL

XC4052XL

XC4062XL

XC4085XL

-3

CI

CI

CI

CI

CI

CI

-2

CI

CI

CI

CI

CI

CI

-1

CI

CI

CI

CI

CI

CI

-09C

-08C

-3

CI

CI

CI

CI

CI

CI

-2

CI

CI

CI

CI

CI

CI

-1

CI

CI

CI

CI

CI

CI

-09C

-3

CI

CI

CI

CI

CI

CI

CI

-2

CI

CI

CI

CI

CI

CI

CI

-1

CI

CI

CI

CI

CI

CI

CI

-09C

-3

CI

CI

CI

CI

CI

CI

CI

-2

CI

CI

CI

CI

CI

CI

-1

CI

CI

CI

CI

CI

CI

CI

-09C

-08C

-3

CI

CI

CI

CI

CI

CI

CI

-2

CI

CI

CI

CI

CI

CI

CI

-1

CI

CI

CI

CI

CI

CI

CI

-09C

-3

CI

CI

CI

CI

CI

-2

CI

CI

CI

CI

CI

-1

CI

CI

CI

CI

CI

-09C

-3

CI

CI

CI

CI

CI

-2

CI

CI

CI

CI

CI

-1

CI

CI

CI

CI

CI

-09C

-08C

-3

CI

CI

CI

-2

CI

CI

CI

-1

CI

CI

CI

-09C

1/29/99

C = Commercial TJ = 0 to +85CI= Industrial TJ = -40C to +100C

May 14, 1999 (Version 1.6)

6-69

XC4000E and XC4000X Series Field Programmable Gate Arrays

191

208

208

223

225

240

240

299

304

TYPE

Plast.PLCC

Plast.PQFP

Plast.VQFP

Ceram.PGA

Plast.TQFP

Ceram.PGA

Plast.PQFP

Ceram.PGA

High-Perf.QFP

Plast.PQFP

Ceram.PGA

Plast.BGA

CODE

PQ100

VQ100

PG120

TQ144

PG156

PQ160

PG191

HQ208

PQ208

PG223

BG225

-4

CI

CI

CI

CI

-3

CI

CI

CI

CI

-2

CI

CI

CI

CI

-1

-4

CI

CI

CI

CI

CI

CI

-3

CI

CI

CI

CI

CI

CI

-2

CI

CI

CI

CI

CI

CI

-1

-4

CI

CI

CI

CI

CI

-3

CI

CI

CI

CI

CI

-2

CI

CI

CI

CI

CI

-1

-4

CI

CI

CI

CI

-3

CI

CI

CI

CI

-2

CI

CI

CI

CI

-1

-4

CI

CI

CI

CI

CI

CI

-3

CI

CI

CI

CI

CI

CI

-2

CI

CI

CI

CI

CI

CI

-1

XC4003E

XC4005E

XC4006E

XC4008E

XC4010E

XC4013E

XC4020E

XC4025E

High-Perf.QF

160

HQ304

156

Ceram.PGA

144

PG299

120

Plast.PQFP

100

PQ240

100

High-Perf.QFP

84

HQ240

PINS

PC84

Table 25: Component Availability Chart for XC4000E FPGAs

-4

CI

CI

CI

CI

CI

CI

CI

-3

CI

CI

CI

CI

CI

CI

CI

-2

CI

CI

CI

CI

CI

CI

CI

-1

-4

CI

CI

CI

-3

CI

CI

CI

-2

CI

CI

CI

-1

-4

CI

CI

CI

CI

-3

CI

CI

CI

CI

-2

1/29/99

C = Commercial TJ = 0 to +85CI= Industrial TJ = -40C to +100C

Table 26: Component Availability Chart for XC4000EX FPGAs

PINS

208

240

299

304

352

411

432

TYPE

High-Perf.QFP

High-Perf.QFP

Ceram.PGA

High-Perf.QFP

Plast.BGA

Ceram.PGA

Plast.BGA

CODE

PG411

BG432

XC4028EXXC4036EX

HQ208

HQ240

PG299

HQ304

BG352

-4

CI

CI

CI

CI

CI

-3

CI

CI

CI

CI

CI

-2

-4

CI

CI

CI

CI

CI

-3

CI

CI

CI

CI

CI

-2

1/29/99

C = Commercial TJ = 0 to +85CI= Industrial TJ = -40C to +100C

6-70

May 14, 1999 (Version 1.6)

XC4000E and XC4000X Series Field Programmable Gate Arrays

User I/O Per Package

Table 27, Table 28, and Table 29 show the number of user I/Os available in each package for XC4000-Series devices. Callyour local sales office for the latest availability information, or see the Xilinx website at http://www.xilinx.com for the latestrevision of the specifications.Table 27: User I/O Chart for XC4000XL FPGAs