Low and High pass filter designer for implementation in VHDL

Working with radio communication or audio signals sooner or later filters are needed. These can be build in the analog domain but depending on the application also in the digital domain.

This project is about designing a high or low pass filter in the digital domain and the implementation as a FIR (Finite Impulse Response) Filter in VHDL.

The aim was to have a design tool where one can specify the cutoff frequency, the bandwidth of the transition zone and gets back the filter coefficients which one can copy in a VHDL template, to get the filter into an FPGA.
A VHDL test bench was developed in order to be able to do tests on the VHDL filter implementation.

The filter is processed with the signal by using convolution.

For a theoretical explanation I suggest the book “The Scientist and Engineer’s Guide to
Digital Signal Processing” [1].

The filter designer is written in the MATLAB clone OCTAVE [2] a powerful open source project which has more or less the same syntax as the original MATLAB.

In order to calculate the filter coefficients the first step is to specify the cutoff frequency, the sample rate of the signal to be filtered and the band width, how fast the filter is falling from pass-band to stop-band.
It can also be decided if the filter is supposed to be a low pass filter (LPF) or a high pass filter (HPF).

From these information the code determines how long the filter kernel needs to be, generates a sinc functions and windows the function with the Blackman window to make it smooth going down to zero at the etches.
The filter kernel is normalized to one in order to not manipulate the amplitudes of the pass band frequencies.

The last part produces a plot showing the filter in the time and the frequency domain.
The frequency domain is shown in linear and in logarithmic form.
The filter coefficients are printed out in the following form:
0 =>to_sfixed (0.000000, g_fixInt-1,-1*g_fixDec),

This form of code can be directly copied into the VHDL code template explained later on.

An example of a low pass filter design (left) and a high pass filter (right) design is given in the following:

In order to apply the code by convolution on the signal some VHDL code was developed:

The VHDL code has some generic variable which give some flexibility for example in the bit length of the in and outputs, as well as the filter kernel coefficients.
The in- and outputs are signed integer numbers which are handed in as std_logic_vectors.
In order to increase the precision of the calculations the filter kernel is saved in fixed point form.
The convolution process is performed using fixed point numbers as well.

In order to be able to test the code and also in order to be able to study the effect of the fixed point rounding and integer conversion a test bench was developed. The test bench is used together with Model Sim to test the VHDL filter implementation.
The Modelsim scripts can be found on GITHub (see below).

The test bench connects a lookup table, containing 50 cos(x) waves spaced by 0.01 normalized frequencies, with the filter.
The input signal from the lookup table as well as the filtered signal is written into a file for further analysis.
This has the advantage that the input signal is is already limited by its bit resolution and the output signal as well.
The calculations are performed in fixed point notation, so the behavior should be the same as later on the FPGA.

The test signal looks the following:

as can be seen equally spaced amplitudes in the frequency spectrum. A piece of OCTAVE code to analyze the output from te test bench can also be found in GITHub.

The input signal filtered with 21 coefficient long low pass filter kernel is looks the following. The design fall off bandwidth (BW) of the design was 0.2.

The output signal filtered with a 201 long low pass filter kernel. The design fall off bandwidth (BW) of the design was 0.02.

It can be seen that by increasing the amount of coefficients the falloff between pass band and stop band gets much narrower.
This can be specified in the filter design as the bandwidth. The disadvantage is the longer the kernel gets the more computations have to be performed in order to get the signal corrected. Also on the FPGA this means that the design gets bigger and bigger. At some point more advanced convolution using FFT should be considered.

For a high pass filter with a BW of 0.05 results in 81 poles the design cutoff frequency was 0.2.