Jazyky

Stav zakázky

I want to implement the Ethernet connection.
The deliverables are as follows
-Verilog code to run on a Spartan 6 Board - (xc6slx100)
-simulation time diagrams (more details will be given to the winner)
- The code should be able to transmit and receive data at 1000mbs.

I need someone to write verilog code and also test .do files for a maze game. The program should output to vga. The rules of the game are simple. You start at a point and have to figure out how to get to the exit just like an actual maze. However, there is a monster chasing you and if he catches you, you are dead. The player's movement should not be

I need someone to write verilog code and also test .do files for a simplified board game. The program should output to vga. the game is quite simple ;2 players roll dice and move x amount of squares according to the number rolled. first to the end of the board wins. We can discuss the details. The vga display should be very simple and custom made --

...with MAX10 10M50DAF484C7G FPGA *
____________
Final Products:
____________
-A software-level block diagram showing the connections between the System Verilog modules described in pdf
-System Verilog implementations of the modules described in pdf.
-Valid hardware output.
Final Note: Please attach any necessary files with a brief description of the

Need someone who has the tools and/or ability to convert a relatively simple verilog (.v) file to liberty timing (.lib) format, and who can verify the resulting .lib file. If successful and painless, there will be more such projects.

I work in the Electrical Engineering Field. The project is to create a distance measuring program using verilog. I will be using Basys 3 ( FPGA) and an Ultrasonic sensor ( HC-SR04). The idea is to measure the gap between two vehicles. The sensor will be placed in the front of a toy car and used to measure the gap instantaneously and also save that data

Hi guys, I've done a simple design to test the SRAM of Digilent Cmod A7 FPGA board.
This is how it works: Using a terminal through UART, I send the input data and address to the SRAM. Then I send address where to read, and I get back the data previously written.
Everything works OK except the controller.
I need someone to review my design and fix it.

...the tests we are going to do and why its beneficial.
The tests we will be doing are Blood Pressure, Body Mass Index, Height, Weight, Waist Circumference, Total Cholesterol, HDL, LDL, Triglycerides, Cardiac Risk Ratio, Blood Glucose. A brief list of benefits include: a snap shot of your current health, the ability to detect early disease processes

Please refer the att...the attached document. This is the base paper of my project. I want to do my project on 64 bit square root carry select adder. I request you to help me with the coding in Verilog using Xilinx in gate level or switch level modelling. Can you please share the cost and the time line for the code. I will need it as soon as possible.

The aim of the project is to design a BIST controller to insert and detect the faults (defect) like ...Read disturbance, Erase disturbance, Program disturbance, SAF, TF, ADF, CFs, TF, NPSF, Retention fault in FLASH memory by using BIST algorithm like March algorithm using verilog or VHDL in Xilinx or Modelsim.
Need Simulation waveforms for the same.

...i am looking for
Electrical & Electronics engineer
Mechanical Engineer
Civil Engineer
Engineers should be expert in following fields
Arduino
Matlab
Raspberry Pi
FPGA
Verilog/VHDL
Python
PCB Design (Eagle/Altium)
Solidworks
AutoCAD
if you are expert in any of above mentioned fields then you can place a bid.
We will prefer fresh Freelancers but