Andy "Krazy" Glew is a computer architect, a long time poster on comp.arch ... and an evangelist of collaboration tools such as wikis, calendars, blogs, etc. Plus an occasional commentator on politics, taxes, and policy. Particularly the politics of multi-ethnic societies such as Quebec, my birthplace.

The content of this blog is my personal opinion. It is not that of my employer. See Disclaimer.

Photo credit: http://docs.google.com/View?id=dcxddbtr_23cg5thdfj

Disclaimer

The content of this blog is my personal opinion only. Although I am an employee - currently of Nvidia, in the past of other companies such as Iagination Technologies, MIPS, Intellectual Ventures, Intel, AMD, Motorola, and Gould - I reveal this only so that the reader may account for any possible bias I may have towards my employer's products. The statements I make here in no way represent my employer's position, nor am I authorized to speak on behalf of my employer. In fact, this posting may not even represent my personal opinion, since occasionally I play devil's advocate.

See http://docs.google.com/View?id=dcxddbtr_23cg5thdfj for photo credits.

Thursday, September 04, 2014

Stupid quote: "LL, SC ... Unlike the RMW instructions, there is no need to lock the bus, yet it implements an atomic operation".

Apparently does not know that most advanced microprocessors have not "locked the bus" to implement atomic RMW instructions for decades.

Also does not know that a smart implementation of an atomic RMW is guaranteed to make forward progress - at ;east, the RMW instruction itself will complete - whereas LL/SC implementations are plagued by forward progress problems.

Instruction like this is one of the big reasons parallel programming advances so slowly.