Toshiba Ups Ante in 3D NAND Fray

TORONTO — The transition to 3D NAND is picking up speed as Toshiba announced in late March it was shipping samples of its 48-layer 3D Bit Cost Scalable (BiCS) stacked cell structure flash.

The news comes on the heels of Intel and Micron announcing their joint 3D NAND flash technology that stacks flash cells vertically in 32 layers to achieve 256-Gbit multilevel cell (MLC) and 384-Gbit triple-level cell (TLC) die that fit within a standard package.

Toshiba’s BiCS 3D technology dates back to the early 2000s, according to Scott Nelson, senior VP of the company’s memory business unit, in an interview with EE Times; it first presented the concept at the VLSI Symposium in 2007. This second generation of 3D BiCS flash comes in 128-Gbit die with 2-bits-per-cell—the same number of bits-per-cell compared with standard 2D planar MLC NAND.

Nelson told us that Toshiba’s 3D NAND strategy recognized it would take time for the technology to mature, so the company has continued to invest in its floating-gate technology, having announced a 15nm process technology to produce NAND flash last year.

“Floating gate is not necessarily going away,” Nelson said. 3D is targeting higher density applications, such as SSDS, although "lots of applications still require lower densities.” Toshiba’s 3D memory will allow for a smooth transition from floating gate, but the two will exist in parallel for some time, although floating-gate planar technology “has hit the wall” in terms of further shrinking and achieving greater density.

Nelson said the challenge with its 48-layer BiCS flash has been going vertical and being able to connect all of the layers because it is a precise operation to connect everything in the manufacturing process. He said as manufacturing ramps up in 2016 Toshiba will be able to cost-effectively provide the technology.

Toshiba will support initial sampling and production of its 3D technology from its Fab 5 at the company’s Yokkaichi Operations in Japan. Mass production will take place at its new Fab 2 at Yokkaichi, which is now under construction and set to be completed in the first half of 2016.

Gregory Wong, principal analyst with Forward Insights, noted the Intel / Micron collaboration has leveraged floating-gate technology to support 3D NAND flash, whereas others are focused on charge trap technology. “The technology is a little different,” he said in an interview with EE Times. But while each vendor is using different concepts to develop 3D, ultimately they are all scalable, although scaling will depend on the capability of tools and digging holes in the substrate. “Those are the main issues.”

Wong told us that Toshiba has had the highest array efficiency in the 2D era. “If they can bring that to bear in the 3D era, Toshiba will be in good condition from a cost perspective.” Other than Samsung, everyone is in pilot production or just sampling. Wong expects volume to ramp up next year. Samsung’s memory fab line in China began full-scale manufacturing of its 3D V-NAND flash memory chips last May, after announcing it had begun mass production of its 3D 128 Gbit/s NAND flash memory.

The ecosystem to support 3D NAND also needs to mature, said Wong, including controller technology, and for the near future, there are still plenty of 2D alternatives for customers. “There has to be a cost benefit. In general, people don’t want to be the first guinea pig.”

Jim Handy, principal analyst with Objective Analysis, told EE TImes that the move to 3D NAND is going to be most complex transition in the world of semiconductors. He expects everyone will have challenges as they take different approaches with the ultimate goal of getting the best yield and lowest wafer cost. “Once one company gets into cost effective volume production it allows them to be more profitable than others," he said.

Thanks for an excellent article. I did not know that Intel/Micron were using floating gate in 3D NAND, which recalls Intel presentations about how FG was doomed because so few electrons would be used in a single bit, and thus vulnerable to disturbs. My question is about the promise that 3D NAND would use relaxed design rules, and be able to avoid the lithography expense of double and triple patterning. Is it fair to say the equipment cost will only partially shift to deposition and etch, with a net savings due to the lower litho expenses? Thanks again.