As Intel plans for Pentium 4 .09 micron production (code-named Prescott), some things are becoming clearer. The Inquirer notes that Intel's Yamhill project (Intel's 64-bit x86 extensions) may not be x86-64 compatible after all. Will AMD's x86-64 become the next 3DNow, destined to be a standard that, even though supported at the OS level, is unsupported by applications? AMD will have to keep heavy momentum going for x86-64 to keep people interested if that's the case. On top of that, there's another article at The Inquirer about the Prescott New Instructions (PNI), which I would hesitantly call SSE-III. The PNIs will possibly be instructions having to do with Hyper-Threading. So far, we haven't seen an AMD answer to Hyper-Threading in the works, but do they need one? Consider this: Hyper-Threading is designed to fill big pipelines with instructions, making a chip run hotter. AMD's smaller pipelines are probably already fairly full, running hot enough as it is. Is the barrier to going faster the heat, or is it just the pipeline? I'd say it's both. Hyper-Threading, or SMT, or whatever you want to call it, seems like a logical next step to the growing pipeline sizes, but it may not come into its own until we shrink down to .09 microns. I also have a feeling that AMD will be able to remain competitive for a while, even with Hyper-Threading solutions from Intel, but that will not last forever. Someday AMD will have to investigate SMT as their pipelines get bigger and start to have more empty spaces. Right now, the P4 has a 20-stage pipeline and the Athlon has a 10-stage integer pipeline (15-stage FP). That 10-stage pipeline will go up to 12 stages with Hammer, and it may very well be that you get no real SMT/Hyper-Threading boost until you get to the 20 stage ballpark.

USER COMMENTS 13 comment(s)

I doubt…(3:04pm EST Mon Apr 22 2002)…that even the operating systems will persistently support AMD's off brand 64 bit architecture. A year or two after release when none of the major business customers have bought significant loads of amd's 64 bit based systems, and Intel is selling them like hotcakes, count on the time/dollar expenditures on AMD architecture compatibility to dry up. - by Mr. DH

FSB(3:11pm EST Mon Apr 22 2002)Any idea what future FSB we will see from both?

Someone was hinting towards an 800MHz FSB with prescott…Thats insane!

I heard rumors that AMD may not CAN Barton so they can get Hammer out for a November 02 release…any news on this? - by Manu

Stages??(4:23pm EST Mon Apr 22 2002)What does the number of pipeline stages have to do with hyperthreading performance? It's the total throughput that matters. - by by by by

Hyperhtreading and pipeline lentgh have quite a lot to do with one another.

A PIV can zip along at 2.4 ghz ONLY BY HAVING A LONG PIPELINE (20 STAGES)by definition this requires a lot of empty registers and and also cache misses, incorrect branch predictions, etc. This is not a “bad” thing it just is. Athlons on the other hand have fewer of the “problems” beacuse of a shorter pipeline, they just can “rev” as high. To the degree that Intel, and likley soon AMD, can issue more instructions to the pipeline and get a performance boost.

To use a very simple example, the old 8086 chip had a “half” stage pipeline (took two or more clock cycles) All the registers were full so there would have been ZERO point in “hyperthreading” – even additional instructions could have been issued, there was no place to put them.

- by kgb

It's about balance(6:21pm EST Mon Apr 22 2002)Kgb, you gain little by doing half the work at double frequency, maybe you cut some latency in a few places.

Actually 8086 was microcoded and the only pipeline equivalent was a small instruction que.

P4 traded performance for frequency. The IPC on real apps is around 1, so P4 should have doubled performance on most codes using hyperthreading. Why didn't it? Because there are other bottlenecks. It has too few resources for multiple threads. Athlon has more resources but lower frequency. It's really hard to tell the right balance.

P4 will have to be improved for better HT performance, the pipeline length itself is not HT performance guarantee. P4 is even slower on some apps with HT enabled! - by by by by

by by by by(11:45pm EST Mon Apr 22 2002)that is due to dual 16 bit alu's. That limits it to 1 32 bit thread in the AlU so current HT(or smt) is almost usless unless its one thread for the FPU and one for the ALU, Prescott will have dual 32 bit Alus allowing them to run 2 32 bit threads in the ALU's, now if they add a second FPU that will make it almost impossible for HT to flop. - by Nataku

Re: Nataku(6:24am EST Tue Apr 23 2002)Was that pun intentional?

If they add a seconde FPU then it won't FLOP! - by MDguy

robgeek!! comment please.(8:18am EST Tue Apr 23 2002)

- by dx2

how they do that(8:19am EST Tue Apr 23 2002)is that even possible?oh which mother board?how. can i do the same to my Pentium 200Mhz, hehe j.k - by dx2

here url again(8:50am EST Tue Apr 23 2002)- by dx2

MDguy(1:57pm EST Tue Apr 23 2002)No it wasnt, i didnt even think about it that way til you said something.

Manu Prescott will be a quad pumped 200Mhz bus or an 800 mhz bus for marketing. - by Nataku

dx2(2:01pm EST Tue Apr 23 2002)The colder the chip is the faster it can run. Heat is the limiting factor in PC's processor today, if it wasnt a problem Intel and AMD would be at 10Ghz(well AMD at 7Ghz but rated at 10000+) - by Nataku