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AR# 14853

Description

The SPI4.2 interface requires global clock buffers on the Sink core and Source core. Additionally, global clock buffers might be needed for the user interfaces of the following clock inputs:

SrcFFClk

SnkFFClk

SnkCalClk

SrcCalClk

SrcStatClk

SnkStatClk

These input clocks are independent, and there is no phase nor frequency dependency of each other.

Solution

For many applications, if you use both the Receiver (Sink) core and the Transmitter (Source) core of a SPI 4.2 (PL4) in a single FPGA device, shared clock resources can drive these six clock inputs. The following clocks are natural pairs, and in most typical applications, they can share a common clock domain:

- SrcFFClk and SnkFFClk

- SrcCalClk and SnkCalClk

- SrcStatClk and SnkStatClk

Additionally, the core provides access to its internal clocks through the following user interface outputs:

SPI 4.2 (PL4) Source Core:

SysClk0_GP: Generated by SysClk (used to clock the DDR FFs for the outputs "TDat" and "TCtl")

SysClk180_GP: The inverted version of SysClk0_GP

SysClkDiv_GP: 1/2 the rate of SysClk

TSClk_GP: Generated by the PL4 bus input TSClk (1/4 or 1/8 the rate of TDClk)

SPI 4.2 (PL4) Sink Core:

RDClk0_GP: Generated by RDClk (used to clock the DDR FFs for the inputs "RDat" and "RCtl")

RDClk180_GP: Inverted version of RDClk0_GP

RDClkDiv_GP: 1/2 the rate of RDClk

Each of these clock outputs is driven by a global clock buffer, and they can be connected to user logic or driven back into the core as clock inputs without using additional clock resources. Please note that the other signals of the FIFO interface, both the inputs and outputs, should be synchronized and sampled (respectively) with their associated clocks. For example: all signals names SnkFF* are synchronized to SnkFFClk.