Event Qualifiers

Event specifiers for these PMCs support the following common qualifiers:

rsp=value

Configure the Off-core Response bits.

DMND_DATA_RD

Counts the number of demand and DCU prefetch data reads of full and partial cachelines as well as demand data page table entry cacheline reads. Does not count L2 data read prefetches or instruction fetches.

DMND_RFO

Counts the number of demand and DCU prefetch reads for ownership (RFO) requests generated by a write to data cacheline. Does not count L2 RFO.

DMND_IFETCH

Counts the number of demand and DCU prefetch instruction cacheline reads. Does not count L2 code read prefetches. WB Counts the number of writeback (modified to exclusive) transactions.

PF_DATA_RD

Counts the number of data cacheline reads generated by L2 prefetchers.

PF_RFO

Counts the number of RFO requests generated by L2 prefetchers.

PF_IFETCH

Counts the number of code reads generated by L2 prefetchers.

OTHER

Counts one of the following transaction types, including L3 invalidate, I/O, full or partial writes, WC or non-temporal stores, CLFLUSH, Fences, lock, unlock, split lock.

UNCORE_HIT

L3 Hit: local or remote home requests that hit L3 cache in the uncore with no coherency actions required (snooping).

OTHER_CORE_HIT_SNP

L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where no modified copies were found (clean).

OTHER_CORE_HITM

L3 Hit: local or remote home requests that hit L3 cache in the uncore and was serviced by another core with a cross core snoop where modified copies were found (HITM).

REMOTE_CACHE_FWD

L3 Miss: local homed requests that missed the L3 cache and was serviced by forwarded data following a cross package snoop where no modified copies found. (Remote home requests are not counted)

REMOTE_DRAM

L3 Miss: remote home requests that missed the L3 cache and were serviced by remote DRAM.

LOCAL_DRAM

L3 Miss: local home requests that missed the L3 cache and were serviced by local DRAM.

NON_DRAM

Non-DRAM requests that were serviced by IOH.

cmask=value

Configure the PMC to increment only if the number of configured events measured in a cycle is greater than or equal to
value.

edge

Configure the PMC to count the number of de-asserted to asserted transitions of the conditions expressed by the other qualifiers. If specified, the counter will increment only once whenever a condition becomes true, irrespective of the number of clocks during which the condition remains true.

inv

Invert the sense of comparison when the “
cmask” qualifier is present, making the counter increment when the number of events per cycle is less than the value specified by the “
cmask” qualifier.

If neither of the “ os” or “ usr” qualifiers are specified, the default is to enable both.

Event Specifiers (Programmable PMCs)

Westmere programmable PMCs support the following events:

LOAD_BLOCK.OVERLAP_STORE

(Event 03H, Umask 02H) Loads that partially overlap an earlier store

SB_DRAIN.ANY

(Event 04H, Umask 07H) All Store buffer stall cycles

MISALIGN_MEMORY.STORE

(Event 05H, Umask 02H) All store referenced with misaligned address

STORE_BLOCKS.AT_RET

(Event 06H, Umask 04H) Counts number of loads delayed with at-Retirement block code. The following loads need to be executed at retirement and wait for all senior stores on the same thread to be drained: load splitting across 4K boundary (page split), load accessing uncacheable (UC or USWC) memory, load lock, and load with page table in UC or USWC memory region.

(Event 08H, Umask 02H) Counts number of completed page walks due to load miss in the STLB.

DTLB_LOAD_MISSES.WALK_CYCLES

(Event 08H, Umask 04H) Cycles PMH is busy with a page walk due to a load miss in the STLB.

DTLB_LOAD_MISSES.STLB_HIT

(Event 08H, Umask 10H) Number of cache load STLB hits

DTLB_LOAD_MISSES.PDE_MISS

(Event 08H, Umask 20H) Number of DTLB cache load misses where the low part of the linear to physical address translation was missed.

MEM_INST_RETIRED.LOADS

(Event 0BH, Umask 01H) Counts the number of instructions with an architecturally-visible store retired on the architected path. In conjunction with ld_lat facility

MEM_INST_RETIRED.STORES

(Event 0BH, Umask 02H) Counts the number of instructions with an architecturally-visible store retired on the architected path. In conjunction with ld_lat facility

MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD

(Event 0BH, Umask 10H) Counts the number of instructions exceeding the latency specified with ld_lat facility. In conjunction with ld_lat facility

MEM_STORE_RETIRED.DTLB_MISS

(Event 0CH, Umask 01H) The event counts the number of retired stores that missed the DTLB. The DTLB miss is not counted if the store operation causes a fault. Does not counter prefetches. Counts both primary and secondary misses to the TLB

UOPS_ISSUED.ANY

(Event 0EH, Umask 01H) Counts the number of Uops issued by the Register Allocation Table to the Reservation Station, i.e. the UOPs issued from the front end to the back end.

UOPS_ISSUED.STALLED_CYCLES

(Event 0EH, Umask 01H) Counts the number of cycles no Uops issued by the Register Allocation Table to the Reservation Station, i.e. the UOPs issued from the front end to the back end. set invert=1, cmask = 1

UOPS_ISSUED.FUSED

(Event 0EH, Umask 02H) Counts the number of fused Uops that were issued from the Register Allocation Table to the Reservation Station.

(Event 10H, Umask 01H) Counts the number of FP Computational Uops Executed. The number of FADD, FSUB, FCOM, FMULs, integer MULsand IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a separate FADD instruction.

(Event 13H, Umask 01H) Counts number of loads dispatched from the Reservation Station that bypass the Memory Order Buffer.

LOAD_DISPATCH.RS_DELAYED

(Event 13H, Umask 02H) Counts the number of delayed RS dispatches at the stage latch. If an RS dispatch can not bypass to LB, it has another chance to dispatch from the one-cycle delayed staging latch before it is written into the LB.

LOAD_DISPATCH.MOB

(Event 13H, Umask 04H) Counts the number of loads dispatched from the Reservation Station to the Memory Order Buffer.

(Event 14H, Umask 01H) Counts the number of cycles the divider is busy executing divide or square root operations. The divide can be integer, X87 or Streaming SIMD Extensions (SSE). The square root operation can be either X87 or SSE. Set 'edge =1, invert=1, cmask=1' to count the number of divides. Count may be incorrect When SMT is on

ARITH.MUL

(Event 14H, Umask 02H) Counts the number of multiply operations executed. This includes integer as well as floating point multiply operations but excludes DPPS mul and MPSAD. Count may be incorrect When SMT is on

INST_QUEUE_WRITES

(Event 17H, Umask 01H) Counts the number of instructions written into the instruction queue every cycle.

INST_DECODED.DEC0

(Event 18H, Umask 01H) Counts number of instructions that require decoder 0 to be decoded. Usually, this means that the instruction maps to more than 1 uop

TWO_UOP_INSTS_DECODED

(Event 19H, Umask 01H) An instruction that generates two uops was decoded

INST_QUEUE_WRITE_CYCLES

(Event 1EH, Umask 01H) This event counts the number of cycles during which instructions are written to the instruction queue. Dividing this counter by the number of instructions written to the instruction queue (INST_QUEUE_WRITES) yields the average number of instructions decoded each cycle. If this number is less than four and the pipe stalls, this indicates that the decoder is failing to decode enough instructions per cycle to sustain the 4-wide pipeline. If SSE* instructions that are 6 bytes or longer arrive one after another, then front end throughput may limit execution speed. In such case,

LSD_OVERFLOW

(Event 20H, Umask 01H) Number of loops that can not stream from the instruction queue.

L2_RQSTS.LD_HIT

(Event 24H, Umask 01H) Counts number of loads that hit the L2 cache. L2 loads include both L1D demand misses as well as L1D prefetches. L2 loads can be rejected for various reasons. Only non rejected loads are counted.

L2_RQSTS.LD_MISS

(Event 24H, Umask 02H) Counts the number of loads that miss the L2 cache. L2 loads include both L1D demand misses as well as L1D prefetches.

(Event 24H, Umask 04H) Counts the number of store RFO requests that hit the L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches. Count includes WC memory requests, where the data is not fetched but the permission to write the line is required.

L2_RQSTS.RFO_MISS

(Event 24H, Umask 08H) Counts the number of store RFO requests that miss the L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.

(Event 24H, Umask C0H) Counts all L2 prefetches for both code and data.

L2_RQSTS.MISS

(Event 24H, Umask AAH) Counts all L2 misses for both code and data.

L2_RQSTS.REFERENCES

(Event 24H, Umask FFH) Counts all L2 requests for both code and data.

L2_DATA_RQSTS.DEMAND.I_STATE

(Event 26H, Umask 01H) Counts number of L2 data demand loads where the cache line to be loaded is in the I (invalid) state, i.e. a cache miss. L2 demand loads are both L1D demand misses and L1D prefetches.

L2_DATA_RQSTS.DEMAND.S_STATE

(Event 26H, Umask 02H) Counts number of L2 data demand loads where the cache line to be loaded is in the S (shared) state. L2 demand loads are both L1D demand misses and L1D prefetches.

L2_DATA_RQSTS.DEMAND.E_STATE

(Event 26H, Umask 04H) Counts number of L2 data demand loads where the cache line to be loaded is in the E (exclusive) state. L2 demand loads are both L1D demand misses and L1D prefetches.

L2_DATA_RQSTS.DEMAND.M_STATE

(Event 26H, Umask 08H) Counts number of L2 data demand loads where the cache line to be loaded is in the M (modified) state. L2 demand loads are both L1D demand misses and L1D prefetches.

(Event 26H, Umask 10H) Counts number of L2 prefetch data loads where the cache line to be loaded is in the I (invalid) state, i.e. a cache miss.

L2_DATA_RQSTS.PREFETCH.S_STATE

(Event 26H, Umask 20H) Counts number of L2 prefetch data loads where the cache line to be loaded is in the S (shared) state. A prefetch RFO will miss on an S state line, while a prefetch read will hit on an S state line.

L2_DATA_RQSTS.PREFETCH.E_STATE

(Event 26H, Umask 40H) Counts number of L2 prefetch data loads where the cache line to be loaded is in the E (exclusive) state.

L2_DATA_RQSTS.PREFETCH.M_STATE

(Event 26H, Umask 80H) Counts number of L2 prefetch data loads where the cache line to be loaded is in the M (modified) state.

L2_DATA_RQSTS.PREFETCH.MESI

(Event 26H, Umask F0H) Counts all L2 prefetch requests.

L2_DATA_RQSTS.ANY

(Event 26H, Umask FFH) Counts all L2 data requests.

L2_WRITE.RFO.I_STATE

(Event 27H, Umask 01H) Counts number of L2 demand store RFO requests where the cache line to be loaded is in the I (invalid) state, i.e, a cache miss. The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request

L2_WRITE.RFO.S_STATE

(Event 27H, Umask 02H) Counts number of L2 store RFO requests where the cache line to be loaded is in the S (shared) state. The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request.

L2_WRITE.RFO.M_STATE

(Event 27H, Umask 08H) Counts number of L2 store RFO requests where the cache line to be loaded is in the M (modified) state. The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request.

L2_WRITE.RFO.HIT

(Event 27H, Umask 0EH) Counts number of L2 store RFO requests where the cache line to be loaded is in either the S, E or M states. The L1D prefetcher does not issue a RFO prefetch. This is a demand RFO request

(Event 3CH, Umask 00H) Counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. see Table A-1

CPU_CLK_UNHALTED.REF_P

(Event 3CH, Umask 01H) Increments at the frequency of TSC when not halted. see Table A-1

DTLB_MISSES.ANY

(Event 49H, Umask 01H) Counts the number of misses in the STLB which causes a page walk.

DTLB_MISSES.WALK_COMPLETED

(Event 49H, Umask 02H) Counts number of misses in the STLB which resulted in a completed page walk.

DTLB_MISSES.WALK_CYCLES

(Event 49H, Umask 04H) Counts cycles of page walk due to misses in the STLB.

DTLB_MISSES.STLB_HIT

(Event 49H, Umask 10H) Counts the number of DTLB first level misses that hit in the second level TLB. This event is only relevant if the core contains multiple DTLB levels.

DTLB_MISSES.LARGE_WALK_COMPLETED

(Event 49H, Umask 80H) Counts number of completed large page walks due to misses in the STLB.

LOAD_HIT_PRE

(Event 4CH, Umask 01H) Counts load operations sent to the L1 data cache while a previous SSE prefetch instruction to the same cache line has started prefetching but has not yet finished.

L1D_PREFETCH.REQUESTS

(Event 4EH, Umask 01H) Counts number of hardware prefetch requests dispatched out of the prefetch FIFO.

L1D_PREFETCH.MISS

(Event 4EH, Umask 02H) Counts number of hardware prefetch requests that miss the L1D. There are two prefetchers in the L1D. A streamer, which predicts lines sequentially after this one should be fetched, and the IP prefetcher that remembers access patterns for the current instruction. The streamer prefetcher stops on an L1D hit, while the IP prefetcher does not.

L1D_PREFETCH.TRIGGERS

(Event 4EH, Umask 04H) Counts number of prefetch requests triggered by the Finite State Machine and pushed into the prefetch FIFO. Some of the prefetch requests are dropped due to overwrites or competition between the IP index prefetcher and streamer prefetcher. The prefetch FIFO contains 4 entries.

(Event 63H, Umask 01H) Cycle count during which the L1D and L2 are locked. A lock is asserted when there is a locked memory access, due to uncacheable memory, a locked operation that spans two cache lines, or a page walk from an uncacheable page table. Counter 0, 1 only. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such accesses.

CACHE_LOCK_CYCLES.L1D

(Event 63H, Umask 02H) Counts the number of cycles that cacheline in the L1 data cache unit is locked. Counter 0, 1 only.

(Event 80H, Umask 02H) Counts all instruction fetches that miss the L1I cache. This includes instruction cache misses, streaming buffer misses, victim cache misses and uncacheable fetches. An instruction fetch miss is counted only once and not once for every cycle it is outstanding.

(Event 88H, Umask 40H) Counts taken near branches executed, but not necessarily retired.

BR_INST_EXEC.ANY

(Event 88H, Umask 7FH) Counts all near executed branches (not necessarily retired). This includes only instructions and not micro-op branches. Frequent branching is not necessarily a major performance issue. However frequent branch mispredictions may be a problem.

BR_MISP_EXEC.COND

(Event 89H, Umask 01H) Counts the number of mispredicted conditional near branch instructions executed, but not necessarily retired.

(Event 89H, Umask 40H) Counts executed mispredicted near branches that are taken, but not necessarily retired.

BR_MISP_EXEC.ANY

(Event 89H, Umask 7FH) Counts the number of mispredicted near branch instructions that were executed, but not necessarily retired.

RESOURCE_STALLS.ANY

(Event A2H, Umask 01H) Counts the number of Allocator resource related stalls. Includes register renaming buffer entries, memory buffer entries. In addition to resource related stalls, this event counts some other events. Includes stalls arising during branch misprediction recovery, such as if retirement of the mispredicted branch is delayed and stalls arising while store buffer is draining from synchronizing operations. Does not include stalls due to SuperQ (off core) queue full, too many cache misses, etc.

RESOURCE_STALLS.LOAD

(Event A2H, Umask 02H) Counts the cycles of stall due to lack of load buffer for load operation.

RESOURCE_STALLS.RS_FULL

(Event A2H, Umask 04H) This event counts the number of cycles when the number of instructions in the pipeline waiting for execution reaches the limit the processor can handle. A high count of this event indicates that there are long latency operations in the pipe (possibly load and store operations that miss the L2 cache, or instructions dependent upon instructions further down the pipeline that have yet to retire. When RS is full, new instructions can not enter the reservation station and start execution.

RESOURCE_STALLS.STORE

(Event A2H, Umask 08H) This event counts the number of cycles that a resource related stall will occur due to the number of store instructions reaching the limit of the pipeline, (i.e. all store buffers are used). The stall ends when a store instruction commits its data to the cache or memory.

RESOURCE_STALLS.ROB_FULL

(Event A2H, Umask 10H) Counts the cycles of stall due to re- order buffer full.

RESOURCE_STALLS.FPCW

(Event A2H, Umask 20H) Counts the number of cycles while execution was stalled due to writing the floating-point unit (FPU) control word.

RESOURCE_STALLS.MXCSR

(Event A2H, Umask 40H) Stalls due to the MXCSR register rename occurring to close to a previous MXCSR rename. The MXCSR provides control and status for the MMX registers.

RESOURCE_STALLS.OTHER

(Event A2H, Umask 80H) Counts the number of cycles while execution was stalled due to other resource issues.

MACRO_INSTS.FUSIONS_DECODED

(Event A6H, Umask 01H) Counts the number of instructions decoded that are macro-fused but not necessarily executed or retired.

BACLEAR_FORCE_IQ

(Event A7H, Umask 01H) Counts number of times a BACLEAR was forced by the Instruction Queue. The IQ is also responsible for providing conditional branch prediction direction based on a static scheme and dynamic data provided by the L2 Branch Prediction Unit. If the conditional branch target is not found in the Target Array and the IQ predicts that the branch is taken, then the IQ will force the Branch Address Calculator to issue a BACLEAR. Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble in the instruction fetch pipeline.

LSD.UOPS

(Event A8H, Umask 01H) Counts the number of micro-ops delivered by loop stream detector Use cmask=1 and invert to count cycles

(Event B1H, Umask 04H) Counts number of Uops executed that were issued on port 2. Port 2 handles the load Uops. This is a core count only and can not be collected per thread.

UOPS_EXECUTED.PORT3_CORE

(Event B1H, Umask 08H) Counts number of Uops executed that were issued on port 3. Port 3 handles store Uops. This is a core count only and can not be collected per thread.

UOPS_EXECUTED.PORT4_CORE

(Event B1H, Umask 10H) Counts number of Uops executed that where issued on port 4. Port 4 handles the value to be stored for the store Uops issued on port 3. This is a core count only and can not be collected per thread.

UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5

(Event B1H, Umask 1FH) Counts number of cycles there are one or more uops being executed and were issued on ports 0-4. This is a core count only and can not be collected per thread.

UOPS_EXECUTED.PORT5

(Event B1H, Umask 20H) Counts number of Uops executed that where issued on port 5.

UOPS_EXECUTED.CORE_ACTIVE_CYCLES

(Event B1H, Umask 3FH) Counts number of cycles there are one or more uops being executed on any ports. This is a core count only and can not be collected per thread.

UOPS_EXECUTED.PORT015

(Event B1H, Umask 40H) Counts number of Uops executed that where issued on port 0, 1, or 5. Use cmask=1, invert=1 to count stall cycles.

UOPS_EXECUTED.PORT234

(Event B1H, Umask 80H) Counts number of Uops executed that where issued on port 2, 3, or 4.

OFFCORE_REQUESTS_SQ_FULL

(Event B2H, Umask 01H) Counts number of cycles the SQ is full to handle off-core requests.

(Event C0H, Umask 01H) See Table A-1 Notes: INST_RETIRED.ANY is counted by a designated fixed counter. INST_RETIRED.ANY_P is counted by a programmable counter and is an architectural performance event. Event is supported if CPUID.A.EBX[1] = 0. Counting: Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.

INST_RETIRED.X87

(Event C0H, Umask 02H) Counts the number of floating point computational operations retired floating point computational operations executed by the assist handler and sub-operations of complex floating point instructions like transcendental instructions.

(Event C2H, Umask 01H) Counts the number of micro-ops retired, (macro-fused=1, micro- fused=2, others=1; maximum count of 8 per cycle). Most instructions are composed of one or two micro-ops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists. Use cmask=1 and invert to count active cycles or stalled cycles

UOPS_RETIRED.RETIRE_SLOTS

(Event C2H, Umask 02H) Counts the number of retirement slots used each cycle

UOPS_RETIRED.MACRO_FUSED

(Event C2H, Umask 04H) Counts number of macro-fused uops retired.

MACHINE_CLEARS.CYCLES

(Event C3H, Umask 01H) Counts the cycles machine clear is asserted.

MACHINE_CLEARS.MEM_ORDER

(Event C3H, Umask 02H) Counts the number of machine clears due to memory order conflicts.

MACHINE_CLEARS.SMC

(Event C3H, Umask 04H) Counts the number of times that a program writes to a code section. Self-modifying code causes a sever penalty in all Intel 64 and IA-32 processors. The modified cache line is written back to the L2 and L3caches.

(Event CBH, Umask 04H) Counts number of retired loads that hit their own, unshared lines in the L3 cache.

MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM

(Event CBH, Umask 08H) Counts number of retired loads that hit in a sibling core's L2 (on die core). Since the L3 is inclusive of all cores on the package, this is an L3 hit. This counts both clean or modified hits.

MEM_LOAD_RETIRED.L3_MISS

(Event CBH, Umask 10H) Counts number of retired loads that miss the L3 cache. The load was satisfied by a remote socket, local memory or an IOH.

MEM_LOAD_RETIRED.HIT_LFB

(Event CBH, Umask 40H) Counts number of retired loads that miss the L1D and the address is located in an allocated line fill buffer and will soon be committed to cache. This is counting secondary L1D misses.

MEM_LOAD_RETIRED.DTLB_MISS

(Event CBH, Umask 80H) Counts the number of retired loads that missed the DTLB. The DTLB miss is not counted if the load operation causes a fault. This event counts loads from cacheable memory only. The event does not count loads by software prefetches. Counts both primary and secondary misses to the TLB.

FP_MMX_TRANS.TO_FP

(Event CCH, Umask 01H) Counts the first floating-point instruction following any MMX instruction. You can use this event to estimate the penalties for the transitions between floating-point and MMX technology states.

FP_MMX_TRANS.TO_MMX

(Event CCH, Umask 02H) Counts the first MMX instruction following a floating-point instruction. You can use this event to estimate the penalties for the transitions between floating-point and MMX technology states.

FP_MMX_TRANS.ANY

(Event CCH, Umask 03H) Counts all transitions from floating point to MMX instructions and from MMX instructions to floating point instructions. You can use this event to estimate the penalties for the transitions between floating-point and MMX technology states.

MACRO_INSTS.DECODED

(Event D0H, Umask 01H) Counts the number of instructions decoded, (but not necessarily executed or retired).

UOPS_DECODED.STALL_CYCLES

(Event D1H, Umask 01H) Counts the cycles of decoder stalls.

UOPS_DECODED.MS

(Event D1H, Umask 02H) Counts the number of Uops decoded by the Microcode Sequencer, MS. The MS delivers uops when the instruction is more than 4 uops long or a microcode assist is occurring.

UOPS_DECODED.ESP_FOLDING

(Event D1H, Umask 04H) Counts number of stack pointer (ESP) instructions decoded: push , pop , call , ret, etc. ESP instructions do not generate a Uop to increment or decrement ESP. Instead, they update an ESP_Offset register that keeps track of the delta to the current value of the ESP register.

UOPS_DECODED.ESP_SYNC

(Event D1H, Umask 08H) Counts number of stack pointer (ESP) sync operations where an ESP instruction is corrected by adding the ESP offset register to the current value of the ESP register.

RAT_STALLS.FLAGS

(Event D2H, Umask 01H) Counts the number of cycles during which execution stalled due to several reasons, one of which is a partial flag register stall. A partial register stall may occur when two conditions are met: 1) an instruction modifies some, but not all, of the flags in the flag register and 2) the next instruction, which depends on flags, depends on flags that were not modified by this instruction.

RAT_STALLS.REGISTERS

(Event D2H, Umask 02H) This event counts the number of cycles instruction execution latency became longer than the defined latency because the instruction used a register that was partially written by previous instruction.

RAT_STALLS.ROB_READ_PORT

(Event D2H, Umask 04H) Counts the number of cycles when ROB read port stalls occurred, which did not allow new micro-ops to enter the out-of-order pipeline. Note that, at this stage in the pipeline, additional stalls may occur at the same cycle and prevent the stalled micro-ops from entering the pipe. In such a case, micro-ops retry entering the execution pipe in the next cycle and the ROB-read port stall is counted again.

(Event D4H, Umask 01H) Counts the number of stall cycles due to the lack of renaming resources for the ES, DS, FS, and GS segment registers. If a segment is renamed but not retired and a second update to the same segment occurs, a stall occurs in the front- end of the pipeline until the renamed segment retires.

ES_REG_RENAMES

(Event D5H, Umask 01H) Counts the number of times the ES segment register is renamed.

UOP_UNFUSION

(Event DBH, Umask 01H) Counts unfusion events due to floating point exception to a fused uop.

(Event E5H, Umask 01H) Counts number of times the Branch Prediction Unit missed predicting a call or return branch.

BACLEAR.CLEAR

(Event E6H, Umask 01H) Counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end. This can occur if the code has many branches such that they cannot be consumed by the BPU. Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble in the instruction fetch pipeline. The effect on total execution time depends on the surrounding code.

BACLEAR.BAD_TARGET

(Event E6H, Umask 02H) Counts number of Branch Address Calculator clears (BACLEAR) asserted due to conditional branch instructions in which there was a target hit but the direction was wrong. Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble in the instruction fetch pipeline.

BPU_CLEARS.EARLY

(Event E8H, Umask 01H) Counts early (normal) Branch Prediction Unit clears: BPU predicted a taken branch after incorrectly assuming that it was not taken. The BPU clear leads to 2 cycle bubble in the Front End.

BPU_CLEARS.LATE

(Event E8H, Umask 02H) Counts late Branch Prediction Unit clears due to Most Recently Used conflicts. The PBU clear leads to a 3 cycle bubble in the Front End.

(Event F4H, Umask 10H) Counts the number of SQ lock splits across a cache line.

SQ_FULL_STALL_CYCLES

(Event F6H, Umask 01H) Counts cycles the Super Queue is full. Neither of the threads on this core will be able to access the uncore.

FP_ASSIST.ALL

(Event F7H, Umask 01H) Counts the number of floating point operations executed that required micro-code assist intervention. Assists are required in the following cases: SSE instructions, (Denormal input when the DAZ flag is off or Underflow result when the FTZ flag is off): x87 instructions, (NaN or denormal are loaded to a register or used as input from memory, Division by 0 or Underflow output).

FP_ASSIST.OUTPUT

(Event F7H, Umask 02H) Counts number of floating point micro-code assist when the output value (destination register) is invalid.

FP_ASSIST.INPUT

(Event F7H, Umask 04H) Counts number of floating point micro-code assist when the input value (one of the source operands to an FP instruction) is invalid.