Intel kicked off IDF today by talking up a trio of technologies that are aimed …

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In a presentation at the Intel Developer Forum today, Intel CTO Justin Rattner described three major innovations that Intel has been working on, the first of which is what the company calls a "terascale research chip"—a processor with 80 cores on one piece of silicon that can deliver up to a teraflop (1 trillion floating-point operations per second) of computing power. The other two innovations had been previously announced: a technology called through silicon vias (TSVs), and an optical interconnect technology.

The 80-core processor consists of eight simple floating-point cores that each implement a small, stripped-down, non-x86 ISA. These cores are arranged in a tile pattern and connected to each other by means of an on-chip network. Note that these cores are almost certainly in-order, and are certainly less complex than the Cell processor's SPEs. The whole thing is very reminiscent of Sun's Niagara, and in fact I've heard that internally Intel uses their own little water-based metaphor for it; they call it the "sea of cores" approach.

From what I can tell, the cores' connection to memory is a bit odd, and involves a combination of the aforementioned on-chip network and a new technology called through silicon vias.

Like a Dagwood sandwich with multiple toothpicks

The TSVs are a kind of 3D interconnect technology that involves stacking chips directly on top of each other. There contacts on the adjacent faces of each chip that act as vertical wires, or "vias," and that connect the two chips together. To get a mental picture of what I'm describing, just think of a Dagwood sandwich with toothpicks sticking in it, such that the different layers of the sandwich are connected via the toothpicks. The layers of the sandwich (bread, meat, lettuce, etc.) would be the silicon chips, and the toothpicks would be the wires that the chips use to talk to each other. Now, imagine a side of chips with the sandwich...

Anyway, by stacking memory directly on top of a massively multicore processor and then having wires come up through the different points of the processor and connect directly to the memory chip, Intel claims that they can get transfer rates between the processor and memory of up to a terabyte per second.

Though it's not spelled out in the press release and I haven't seen it described this way elsewhere, here's how I imagine that it works. The 80 cores are arranged in a tile configuration and are connected by an on-chip network, as described above. Then, Intel places a via (or a bundle of vias) on the network at intervals across the chip, so that the few tiles sitting near each via can have a fast connection to whatever part of memory that that via connects to. Of course, the tiles in one region of the chip would have a slower connection to the more distant regions of memory through other vias that are further away than they would to the via that's nearby.

Silicon "laser device"

It's one thing to move data at a terabyte/second in between a CPU and a pool of closely coupled RAM, but it's another trick entirely to get such a package to talk to the rest of a computer system at a fast enough rate. This chip and memory combination could starve conventional socket and interconnect technology pretty quickly, which is why Intel is working on using lasers to connect the silicon sandwiches together at very high bandwidths.

What's the point of an 80-core processor?

You're probably wondering what the point of an 80-core processor is, when PS3 programmers are moaning about having to code for a chip with a mere seven small, in-order floating-point cores. This question has few answers, depending on how you approach it.

In the near-term, the point of this terascale chip is that it's a research project. The individual cores are very simplified, and they don't implement a standard ISA, because right now they're there for research purposes. (I'd expect the cores to get more complex, and maybe to offer more than just floating-point, in a production model.) So the chip as a whole provides a platform for tooling around with massively multicore architectures, and figuring how to organize them, connect them to memory, program them, and generally bring ideas from the drawing board into the lab. In other words, this chip is a prototype, and it points in a direction that Intel thinks they'll eventually take.

From a manufacturing and hardware design standpoint, the main problems that go with making use of an 80-core processor are interconnect- and memory latency-related. So Intel is clearly trying to solve those with TSVs and the laser interconnect technology, so that they can make usable systems built around such massively multicore chips.

This brings me to the long-term part of the question about the point of an 80-core processor. Software developers will point out that the only computing problems that could use the muscle of an 80-core chip like this exist in the rarified realm of high-performance computing, where programmers simulate weather patterns and nuclear blasts and whatnot. In the consumer software market, software architects are struggling to make use of the embarrassment of computational riches provided by dual-core processors, quad-core processors, and (most recently) GPUs.

All of this is true, as far as it goes, but I can't help but think that if such systems are widely available in the next decade, entrepreneurs will come up with a ways to make money from them. The nagging issue here is that I have no idea what a mass-market 80-core software application looks like, and neither does Intel (or Microsoft, or Sun, or IBM, etc.).

So to sum up, in the short-term, the terascale chip is a research platform for working out the kinks of massively multicore system and software design. In the long-term, this endeavor definitely has an air of "if we build it, will they come?" about it. But too many hardware makers are moving in this direction for the rest of the industry not to follow them. So even though Intel is forging ahead into uncharted territory with this "sea of cores" initiative, they're not doing so alone.