The dsp processor hwmod device (dsp_c0) is defined primarily as
a pseudo-hwmod device with only reset control. This shares the
same functional clock along with the dsp hwmod device that is
mainly used for controlling the MMU. This clock name is added to
this pseudo-hwmod device, as it enables the power domain lookup.
This is required to be able to put any latency constraints on
the dsp using the dev_pm_qos_update_request api.

There is no major effect on the clock framework itself due to
this change, as the clock enable & disable will simply be
reference counted and the functionality would be identical as
before.