Presentations at VLSI Highlight New Materials for nMOS Metal Gate Electrodes and a New Approach for Low Standby Power 45nm Transistors

HONOLULU, HI -- (MARKET WIRE) -- June 13, 2006 -- In two key presentations at the 2006 Symposium
on VLSI Technology, SEMATECH engineers today shared technical details on
metal electrode materials that can be used to build low threshold voltage
(Vt) nMOS transistors with high-k dielectric, and also unveiled a new
approach for creating advanced, low standby power transistors for the 45nm
technology generation.

Husam Alshareef, project engineer in SEMATECH's Advanced Gate Stack program
and a TI assignee, outlined the details of the first achievement,
previously announced this spring, involving nMOSFETs with metal electrodes
showing an effective workfunction of ~4.0eV. Capping a three-year project
involving nearly 40 engineers at SEMATECH and collaborating universities
and suppliers, the identification of nMOS metal gate electrode materials --
through the systematic screening of more than 250 material systems on
various dielectrics -- represents a major milestone in the quest to
fabricate working CMOS devices using metal gate and high-k dielectric
stacks.

"From this work, we developed an understanding of how metal electrode
materials and high-k dielectrics react, and how the effective workfunction
of metal electrodes can be controlled to yield an effective workfunction
close to that of doped polysilicon gates," said Byoung Hun Lee, manager of
SEMATECH's Advanced Gate Stack program. "Our approach will enable the
industry to implement metal electrodes with minimum modifications to
current CMOS flow."

In a second VLSI presentation, S.C. Song, Material Evaluation Test
Structure project manager at SEMATECH, unveiled a new approach and
processes for creating advanced, low-power transistors that can be used for
the 45 nm technology generation. Song described a dual high-k, dual metal
gate (DHDMG) process for CMOS field-effect transistors (FETs) that was
demonstrated by SEMATECH engineers earlier this year, which offers several
advantages over previously reported dual metal gate integration approaches.
The result is a highly manufacturable flow that can meet industry and ITRS
targets for low stand-by power (LSTP) 45 nm technology generation.

"As CMOS devices continue to shrink, SiO2/polysilicon-based transistor
structures have become increasingly difficult to scale," said Raj Jammy,
director of SEMATECH's Front End Processes (FEP) Division. "For the 45 nm
technology generation, high-k dielectrics and metal gate electrodes have
become very attractive, especially for low-power technologies. But until
now, there have been no practical approaches to dual metal gate
integration."

The DHDMG process, developed by SEMATECH engineers in ATDF, SEMATECH's R&D
wafer fab, allows high-k dielectric materials and their associated metal
gates to be optimized in separate processing steps, eliminating the
difficult integration problems that have plagued more conventional
methodologies.

The new process is a flexible scheme that uses two different high-k films
-- if needed -- and dual metal electrodes for nMOSFETs and pMOSFETs,
respectively. This allows nMOSFETs and pMOSFETs to be optimized
independently, thus avoiding the deleterious inter-mixing of gate stack
materials that typically degrades threshold voltage and other performance
characteristics. DHDMG is also more controllable, resulting in
better-defined gate profiles. Ultimately, the process is relatively easy
to implement, without the need for additional critical lithography levels
or any significant increase in the number of additional steps.

"We have demonstrated a manufacturable solution for one of the most vexing
problems facing advanced transistor development," Song stated. "The
process details have been transferred to SEMATECH's member companies for
their consideration and we will be working with their engineers on
implementation."

SEMATECH's progress on both leading-edge nMOSFET metal electrode technology
and the novel DHDMG process comes on the heels of last year's related
breakthroughs in channel mobility and reliability of high-k metal gate
transistors. "We've come a long way in our efforts to bring high-k metal
gate technology into the practical realm," said Jammy, "and we're pleased
to be able to share some of our results today with our industry
colleagues."

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