Intelligent Symbol Building Tool With Support for FPGAs and Other High Pin Count Devices

Press Release (ePRNews.com) - SANTA ROSA, California - Sep 12, 2017 - Elgris Technologies, the leading provider of schematic/netlist visualization and schematic/netlist translation solutionshas announced today a new addition to its EDA software family with the recent release of the new version of E-Builder – a Vendor independent Symbol Builder and FPGA to PCB verification tool. Igor Luvishis, President of Elgris said, “Since we support generation of schematic designs from PCB netlists, we felt that we should be offering a product that allows intelligent symbol building targeted to high pin count devices which are found more and more in the designs our Users work on.” The new E-Builder tool is table-driven and supports templates and multiple Vendor styles when it builds schematic symbols. It has an extensive set of features that allow to put pins in groups, put pins into sections and arrange pins by a selected criteria. The tool comes with Symbol Editor that works with two symbols simultaneously allowing to quickly move pins between them. Generated symbols can be saved to popular Vendor formats: Cadence OrCAD, Cadence ConceptHDL, Mentor PADS Powerlogic, Mentor DxDesigner, EAGLE, EDIF and internal binary format. The symbols can also be automatically placed on a page with proper wiring and decoupling capacitors added for FPGAs and similar.

In addition, the tool helps to address the issue on how to match FPGA signals to nets on a PCB board where an FPGA device is placed. This is a common problem when an FPGA Designer and PCB Designer are working together on a design. To help with the solution, E-Builder supports all major FPGA device families, FPGA constraints formats and rules-driven comparison wizard. The combined functionality allows FPGA symbols to be built with pins having signal names correspondent to PCB net names on a board.

Now CAD Librarians, Engineers in the front end as well as FPGA Designers will have an easy to use tool that will allow them to generate intelligent high pin count symbols in a matter of minutes with automatic placement on a page when needed. The tool supports TCL scripting to allow the building of symbols to be even more efficient.

Since we support generation of schematic designs from PCB netlists, we felt that we should be offering a product that allows intelligent symbol building targeted to high pin count devices which are found more and more in the designs our users work on.

DISCLAIMER : If you have any concerns regarding this press release, please contact the Author / Media Contact / Business of this press release. ePRNews is not resposible for the accuracy of the news posted and do not endorse, support any product/services/business mentioned and hereby disclaims any content contained in this press release.