Real Machines with 24-bit and 48-bit words

Many computers have instruction formats that are
complicated to explain, because instructions that refer
to memory do not contain complete memory addresses.
Instead, a short address is included in the instruction,
referring to a memory location within a small area of
memory, and another field in the instruction allows that
small area to be chosen from among a number of choices;
perhaps two, as on a PDP-8, or sixteen, as on an IBM 360.

One type of computer that generally avoided this issue
were computers with 24-bit word lengths, as that gave enough
room for a 15-bit address, a 6-bit opcode, and three additional
bits for such things as indexing and indirect addressing.
Although only a few computers were made with 24-bit
word lengths, for that reason,
that particular word length lends itself well
to very straightforward versions of old-style computer
architecture.

Even though computers with a 24-bit word length
were less common than those with other word lengths,
still, if one looks hard enough, one can find quite
a few. Among those examined here are the A/S Regencentralen RC4000,
the Control Data 924, the ICL 1900, and the Foxboro FOX-1.

The classic group of 24 bit computers, however, consists of
such machines as the Harris Series 500 and SLASH 6/7
(and their progenitor, the Datacraft 6024),
the Scientific Data Systems 920/930/940 and also the 9300,
the Honeywell (or Computer Controls Corporation)
DDP-24, DDP-124 and DDP-224,
the SCC 660, the ASI 6020 and 6040, and finally
the SEL 840, 840A, and 840 MP.
These machines share many architectural similarities, and
all date from the latter part of the discrete transistor era (although
the SEL 840 was one of the earliest machines to be made from monolithic
integrated circuits instead).

In addition to having the potential to simplify the layout of
instruction words, by allowing at least a modest memory to be fully
addressed within each instruction, this length has two other potential benefits.

It lends itself to the use of floating-point variables that are 48
bits long. For a great many scientific purposes, 32-bit floating-point
numbers, with a precision of 6 or 7 decimal digits, are not quite
precise enough, due to the accumulation of error during calculations. But
a 64-bit floating-point number, with a precision of 15 or 16 decimal digits,
is usually far in excess of any practical requirement. 48-bit floating-point
numbers have a precision of 10 decimal digits, as is provided by typical
scientific calculators, which is just about right.

The ability to pack either three 8-bit bytes, or four 6-bit characters,
in a 24-bit word, is attractive, since many computer applications don't need
to bother with such extravagances as lower-case letters. In general,
however, most computers with a 24-bit word did not take advantage of this,
but simply used 6-bit characters.

There are also two microprogrammable machines with a 24-bit
word length that particularly deserve a special
mention: the Burroughs B1700, which hid its
word length from the programmer, and the Packard Bell 440, which
was perhaps one of the very earliest user-microprogrammable
machines.

Incidentally,
a somewhat larger number of computers had a 48-bit word length;
some of them had 24-bit instructions, others 48-bit instructions, and
some had variable-length instructions:
the Control Data 1604 and 3600,
the Honeywell 400, 800 and 1800 (and their progenitor,
the Datamatic D1000),
the Philco 2000 (whose central processor could have been the
Philco 210, 211, or 212, and which was therefore sometimes
referred to as the Philco 2000 Model 212 with a Philco 212
central processor), the Maniac II,
the AN/FSQ-31 and AN/FSQ-32, which were both made by IBM
for the U.S. government, the Elliot 4130 (later the I.C.L. 4130), the FACOM 202,
the University of Manchester Atlas, and the I.C.T. Orion
are computers with that word length.
As is the BESM-6 from the Soviet Union, and several computers from
the People's Republic of China: the Model 109C, the DJS-6 (also known
as the Model 108B), the DJS-8 (also known as the Model 320), and an
early prototype machine based on integrated circuits, the Model 111.
A later 48-bit integrated circuit machine, the Model 013, was also referred
to as a prototype in one source I believe I saw, but more than one of this
computer was produced.
Photographs of some of those computers are visible
here;
a larger picture of the Model 013 front panel appeared in an issue
of Datamation magazine.

Because the Burroughs B5500 and B6700 computers used a word containing
48 bits of data, but also extra bits that described the type of the data
which played an important role in programming the machine, I would consider
that series sufficiently out-of-the-ordinary not to attempt to discuss it here;
the same applies to the English Electric KDF9 computer, which was stack-oriented
like the Burroughs machine.

On the other hand, the Telefunken TR440 computer also added two
descriptor bits to each word with 48 bits of data, but these seem to only
serve to protect the machine against accidentally interpreting instructions as
data, or integers as floating-point quantities: its instructions were 24
bits long, with an 8-bit opcode and either a 16-bit address or two 8-bit
items, which could be string lengths, program-relative addresses, index
specifications, or secondary opcodes, among other things.

The Telefunken TR-440 is notable because a terminal for it, the SIG-100,
came with a mouse, called a "Rollkugel",... before Douglas Engelbart's famous demonstration...
as noted on this
site.

The indicator bits were: 00 for floating-point numbers, 01 for integers, 10 for
instructions, and 11 for character data.

The RCA 601 also used a word containing 48 bits of data. Each 24-bit halfword had three
tag bits associated with it. An additional parity
bit was also associated with each halfword, leading to the machine as sometimes being described
as having a 56-bit word length.

So far, I have only seen limited information on that computer, but from what I have seen,
a typical memory-reference instruction would be a three-address instruction, with flag bits
in the instruction to indicate that any of the instruction's three operands could be the
accumulator instead of a memory location.

The computer had a three-bit "tag register", and for each operand in memory, the instruction
could optionally specify that an exception would be taken if the tag of the halfword containing
the operand did not match the contents of the tag register. Thus, presumably, the tag
mechanism was used under control for such purposes as array bounds checking.

Instructions would normally be 24 bits long, plus 24 bits for each memory address to be
specified in the instruction.

The instruction formats of some of these computers
are shown in the diagram below:

On the SDS 920, 930, and 940, half the opcode
space was given over to user-defined instructions, and the first
bit of the word was unused in the machine (except in some
operating modes of the 940), although the object
program format used it to indicate relocatable addresses.
The SDS 9300, on the other hand,
had a two-bit indexing field to indicate
either that no indexing was taking place, or which of three
index registers would be used with an instruction.

Although the SDS 9300, the SEL 840, and the DDP-224 used the
same general instruction format, they were not compatible: the
SDS 9300 and the SEL 840 used two's complement arithmetic, while the DDP-224
represented numbers in sign-magnitude form, for
example; the SDS 9300 and the SEL 840 were distinct from each other
in other ways, one of which was that in the SEL 840, the shift
instructions had a special format. Similarly, the ASI 6020
computer had the same general instruction format as the Datacraft
6024 computer and its compatible successors by Harris while having
a different floating-point format, and being incompatible in other
ways, one of which was that instead of having three index registers,
it used memory locations 1 through 3 for this purpose. (The UNIVAC
9140 computer was also envisaged as having the same general
instruction format as the Harris computers, but I am not yet certain
if that computer had actually existed.)

The Datacraft 6024 had some additional instruction formats. An optional
unit provided the ability to operate on single bits in memory; since a five-bit
field in the instruction was required to indicate which bit of a word was being
accessed, addresses were only eight bits long, and were offsets from the address
contained in a special base register. Also, there were some floating-point instructions
with an eight-bit immediate operand; in these instructions, one bit between the opcode
and the immediate operand was ignored.

It could have up to 256K words of memory, and so address constants referenced by
indirect addressing contained 18 address bits. But the program counter was only 16 bits
long. As a result, some branch instructions were available in a format which could not be
indexed so that the address field in the word could be made one bit longer.

The registers used to indicate the upper and lower bounds of memory available to a
program running in restricted mode were also only 16 bits long.

The 15 bit address in a normal memory-reference instruction always referred to
an address on the current page, thus, the most significant bit of the Program Counter
was referred to as the "Map bit"; since program code could only be located in the first
64K words of memory, only the first two 32K word pages could ever be current. Any
address longer than 15 bits, whether 16 bits long or 18 bits long, was an absolute
address instead.

In the SDS 9300, index registers were 24 bits in length, but
addresses were only 15 bits wide; the index registers
contained both a nine bit signed increment field and a 15 bit
address.

The P bit also stoood for a programmed operation on the SCC 655, 660 and 670
computers as well, making them very similar to the SDS 920, 930, and 940
except for also using an indirect bit and having a different instruction
set. Another similarity is that just as the SDS 9300 computer was similar, but
not fully compatible, to the SDS 920, 930,and 940, there was also the SCC 6700
computer, a larger scale time-sharing computer in which the size of the address
field was reduced from 15 bits to 14 bits, so that the P bit could be moved, and
another modifier bit, shown here as the S bit, could be added to indicate instruction
words that functioned as system calls.

Just as the SDS 92 had a 12-bit instruction word, so did the SCC 650.

The ICL 1900 had a similar feature; however, when an instruction
addressed 6-bit characters, the increment field was shortened, and its
first two bits were instead used to indicate which of the four characters in
a word was pointed to by the effective address. It also had a 22-bit
addressing mode, in which the first two bits of a word could still
serve this purpose, but the increment field was not used. Since addresses
in instructions were only 12 bits long, the index registers actually
functioned either as base registers, or, when access to arrays was desired,
or when their values were being constantly changed thanks to the
increment field, as pointer registers. Since the address could never be
longer than 12 bits, unlike the case with the Philco 2000 computers, they
were needed as base registers.

The Four-Phase Systems IV/70 had some interesting peculiarities.

Index register 3 could not be used with indirect addressing; instead, if the
X and I bits were all ones, this indicated an instruction that worked on character
strings.

Also, single-precision floating point numbers consisted of a one-word mantissa
followed by a one-word exponent, which had to be aligned on a 48-bit boundary.
Double-precision floating-point numbers had the additional least significant word
of the mantissa preceding a single-precision floating-point number; thus, they
had to be aligned so that they began on an odd word address; thus, arrays of these
numbers would contain empty space.

The Elliott 4120 and 4130 could have instructions that were 12 or 24 bits long,
but it is listed here instead of among the 12-bit computers since it is generally
considered to have a 24-bit word length.

Instructions could have a 12-bit long format which used the first 64 words of memory
as a scratchpad.

In the 24-bit format, the mode bits indicated the following addressing modes:

00 - Immediate
01 - Direct
10 - Indexed
11 - Indirect

The bit marked E indicated an Extracode instruction, which was similar to a
Programmed Operation on the SDS 920/930/940. However, it did have one interesting
peculiarity.

While the instruction had six opcode bits, there were 128 entries in the branch
table for Extracode instructions. If the two addressing bits had 1, 2, or 3 as their
value, the effective address of the instruction was placed in memory location 2, and
the return address was placed in memory location 3. If the addressing bits were zero,
the immediate operand was placed in memory location 2, the same action as for
addressing mode 1, but a different entry in the branch table was used. Therefore,
the immediate mode version of an Extracode instruction could be a completely different
instruction.

The A/S Regencentralen RC4000 computer from Denmark allowed itself a mere 12-bit
address field, like an IBM 360. Addresses could be program-relative,
and if indirect they were pre-indexed. This machine is remembered for
being used by Per Brinch Hansen, himself famous for the language
Concurrent Pascal, for some of his early work on operating
systems. Also, it is unusual in that its addresses were based on
dividing memory into areas 12 bits in length.

The 12-bit address field of the RCA 110 had a simpler explanation;
it had only a 4K-word core memory, but this was supplemented
by a drum which could store 32K words of data.

The Packard-Bell 440 was one of the earliest machines that
was user-microprogrammable. Microprograms were contained in a
memory of up to 4,096 words in length made of special fast
biaxial core. Microcode instructions were 12 bits long, two to
a 24-bit word.

Although microprogrammable, the design favored the format
shown above for regular instructions, in which the opcode came
at the beginning of the word, followed by a field indicating
an index register; and the machine came with
normal software (such as a FORTRAN compiler) which worked
under a standard instruction set.
It could have up to 32,768 24-bit words of normal
memory (2 usec access, 5 usec cycle), and was made from
discrete transistors.

Possibly it could only have had up to 28,670 words of conventional
memory, since apparently the regular memory and the biaxial
shared the same address space, unless biaxial memory was not used
in a given configuration.

Its microprogram instructions had the following format:

The second field could indicate the source for the second operand
in an operation, or it could indicate the source of a memory
address. The destination to which results from the operation would
be sent is implicit in the opcode.

It had four 24-bit registers, A, B, C, and D, and two 15-bit
registers, P and L. P was the microprogram counter, and L was usually
used as the program counter. An eight-bit register, N, was also present,
to which the exponent part of a 24-bit register could be sent; the
exponent part consisted of the second through ninth bits from
the left, and so the floating-point format was also determined.

The Control Data 1604 also
began the instruction with a 6-bit opcode field, and used the
following 3 bits to indicate indexing; but it had six instead
of seven index registers: a value of 7 in this field indicated
indirect addressing.

The Control Data 3600 was largely compatible with the
1604, but two unused opcodes (00 and 77), and three other
opcodes used for the operations input, output, and external
function were used to add new capabilities to the machine. One
new capability was an instruction format in which the 15-bit
address field was divided into three 5-bit register addresses;
this allowed eight instructions which acted on data in the machine's
various registers; these instructions allowed ease in exchanging
information between the accumulator, the Q register (equivalent
to the multiplier-quotient register), the six index registers,
and the like.

Thus, the 3600 was not a machine that did the
majority of its arithmetic using three-address instructions
involving a set of 32 general registers or a set of
32 floating-point registers, although its instruction formats
might suggest the idea of designing such a machine.

As well, the 3600 extended the 1604 architecture by allowing
up to eight banks of 32,768 words of memory; two three-bit
registers indicated the current bank used for instructions and
data respectively. And among the new instructions were some
which were 48 bits in length, not shown in the diagram above.

The 24-bit Control Data 924 also used the same general
instruction format as the 1604, a six-bit opcode field followed
by a three-bit index field, which in the case of
the 924 as well as the 1604 and 3600, selected one of six index
registers if it indicated that indexing was to be performed,
followed by a 15-bit address.

On the other hand, the Control Data 3300 was a machine with a 24-bit
word that had a somewhat different instruction format than that of the
Control Data 3600. It only had three index registers, making available
an extra bit for indirect addressing. Floating-point was an option on
this machine, and character string manipulation instructions were also
optional for it. These included BCD addition instructions on unpacked BCD
numbers, six bits per digit, although there were also instructions to
convert to and from packed BCD. The format of this type of instruction,
which was three words long, is shown following that of the normal memory
reference instruction.

The Honeywell 300 also used the same instruction format as the CDC 1604 and 924;
it even had six index registers, and used a 7 in the index register field to
indicate indirect addressing, just as those machines did, even though this 24-bit
machine was not compatible with the CDC 924 or any other Control Data machine.
Several instructions had other formats such as shift instructions, or
instructions to transfer data between registers.

On the Honeywell 300, the address word that indirect addressing
would point to consisted of a three-bit index register field followed by a 21-bit
address field. This was used to address larger memories. Note that this format
for address constants did not lead to the instruction format being rearranged to put
the index register field first, although several other computers (including the
Honeywell 316) did just that.

The General Electric 400 series of computers also had this general instruction
format, and they also treated the case where a 7 was in the index register field
as a special case. However, they did so in a different and more complicated
manner.

If the index register field contains a 7, then the instruction is 48 bits
long, and the contents of the address part of the second word of the instruction
may be used as an index to be added to the address field of the instruction in
the first word - if the mode bits are 00. If they are 01 or 10, then they are
instead a pointer to a word containing a value to be added to the address (the
two different values indicate a different format for the other bits of that word).

In addition to the index value being a pointer, the I bit in the second word
indicates that the address as a whole is indirect, as computed using the address
field in the first word and whatever indexing may be specified.

When I originally heard of the instruction format of the Philco 212
computer, it seemed to me that with a 32,768-word memory, and a 12-bit
address field, the index register field in the instruction should more
properly be referred to as a base register field. I subsequently learned,
from a private communication, that the selector bit was used to choose
between a 15-bit address, and a 12-bit address with a 3-bit index register
field.

In this case, although it took some reflection for me to realize this,
the index registers are properly named. A normal memory access would use a
15-bit address, but when an array is referenced, then an index register would
need to be specified. Since the address field is short in that case, the
index register would have to be loaded with a pointer to the target array,
although the displacement field could be used when one is dealing with two
or more arrays which all fit in the same 4,096-word area of memory.

The addressing modes of the 68000 microprocessor, before the 68020 added
additional addressing modes to that architecture, had a similar limitation,
so this was not unique. Using a pointer register instead of indexing has the
advantage that the addition of the location of an array to a displacement is done
once at the beginning of a loop instead of with every instruction; even
if one has to increment multiple pointers with each loop iteration, there is still
a net savings; but this seems to be lost when one has a short displacement field
anyways. It had occurred to me that if one were to put the optional index register
field at the end, instead of the beginning, of the address field, one
could locate arrays anywhere in memory, subject only to an eight-word or eight-byte
alignment restriction. However, this wouldn't have been practical on the Philco 2000
computers for another reason, of which I learned when the Philco 212 manual became
available online, thanks to the tireless work of Al Kossow.

In the case of the Transac S-2000 computer at least, the number of
index registers was variable; a machine could have 4, 8, 16, and perhaps 32
index registers, and the index register field would be only as large as
required for the number of index registers a particular machine had, leaving
the remaining bits for the displacement.

The first bit of the opcode field was called the F bit. For arithmetic instructions,
it was used to indicate floating-point instructions. For jump instructions, it
indicated branches to the second 24-bit instruction in a 48-bit word in memory.
To simplify how the assembler worked, branches to the right-half instruction were
given separate mnemonics, even though, in effect, the F bit was really extending the
length of the address field by one bit.

The bit marked P in the instruction layout of the BESM-6
is used to indicate whether an instruction refers to an address on
the current page, or on page zero of the current half of memory.
This is not entirely unlike the similar bit on a PDP-8, as when
the memory on that computer exceeded 4K words, with the aid of
its memory extension feature, page zero was in the current 4K
words, not the first page of the entire potential 32K address
space.

Some of the computers listed here are old enough that their
data formats departed from some conventions now in universal use.

The SCC 660, as well as the SDS 900 and SDS 9300, used two's
complement notation for negative numbers, as is the modern practice,
but the multiplication instruction treated numbers as fixed-point
fractions in [0,1) rather than integers.

The DDP 24 and the ASI 6020 both used sign-magnitude notation,
and a multiply instruction placed the sign of the result in the
sign position of both halves, so that the result was aligned for
use as either the product of integers or the product of fractions.

The Datacraft 6024 and its successors from Harris used
two's complement notation, and the result of a multiply also
skipped the first bit of the second word of a result, but
this bit was always filled with a zero, even if the result was
negative.

The CDC 924 computer used one's complement notation.
Multiplication produced a 48-bit integer result. (The CDC 1604
was also a one's complement machine.)

Thus, of the 24-bit machines that had a 15-bit address
(rather than a 12-bit address) in the instruction word, none
followed the modern convention of both two's complement
arithmetic and an integer multiplication result with no
skipped bit.

I find this a pity because a 24-bit word with
a 15-bit address allows the use of a reasonably-sized memory
without complications such as a page bit or base registers,
and I was looking for a machine with the smallest possible
word length (rather than 32 or 36 bits) to provide this,
but not a smaller word length that was harder to program
(such as 12 or 16 bits), but which was a real historically-used
architecture as being suitable to a project for a modern "toy"
computer with front panel lights and switches.

It might be noted that the University of Manchester Atlas was
significant as the first computer to embody what we now refer
to as "virtual memory", although it was called a "single-level
store" in connection with that computer.

The instruction format for the Philips PR8000 computer is also
shown. The destination register and index register fields, if not
applicable to a given instruction, instead serve to lengthen the
opcode field.

Here are the instruction formats of some computers that
used 48-bit instructions:

The Datamatic 1000, and the Honeywell 400, 1400, 800
and 1800 computers used a 48-bit instruction
word with a three-address format.

The Datamatic 1000 was a vacuum-tube computer, and the
others were solid-state. The Honeywell 400 had the 1400 as
its fully compatible and faster successor, and the Honeywell
800 was succeeded by the 1800. The 400 and 1400 had three
index registers, and the 800 and 1800 had eight, and so the
800 was a computer with added features.

The Honeywell 800 and 1800 in particular
had some unusual and advanced architectural
features.

It could operate both on binary and packed decimal numbers.
Because it used sign-magnitude notation, and it used the
same four-bit
sign symbols for binary and decimal numbers, it had the one
peculiar weakness that a signed
binary number consisted of four bits of sign plus 44 bits of
precision, but it could also handle 48-bit unsigned binary
integers.

The computer had eight complete sets of registers, so that
up to eight tasks could be processed concurrently without
context-switching overhead. Each task had 32 registers; only
eight of them were general registers, although another eight
were usually available as general registers as well.

Register indirect addressing was possible, and instructions
that used it also provided for a five-bit increment field in
the instruction, so that a pointer in a register could be
advanced after use. (When a register was used as a direct
source or operand
location, the increment field was also applied to its value
after use if that value was nonzero, but in that case,
the increment could not be used if the register was the
destination of the instruction.)

As the diagram above illustrates, an indexed memory address
includes a three-bit field indicating the index register, and
a displacement field of eight bits. When a field indicating
a register address was indexed, the index register contained
an increment field and a register field instead of a memory
displacement, allowing a type of indirect indexing.

But the most unique aspect of the H800 architecture is that
each process had two program counters, the main one called the
Sequence Counter, and an auxilliary one, called the Cosequence
Counter. The first bit of each instruction indicated which
program counter would be used to locate the next instruction to
be executed. This unusual feature may have only been used for
some quite specialized applications, and the number of programmers
who understood its implications and effective use may have
been limited. When used, it would have avoided branching
and context-switching overheads. One possible use,
perhaps even the most likely, would be
in code that made frequent calls to a subroutine that behaved
like a state machine. Switching to the cosequence counter
could then plunge directly into the code for the current
state; on a conventional architecture, first there would
be a subroutine call, and then the subroutine would begin
by doing a computed go to (or a pre-indexed indirect branch)
to the code applicable to the current state, and so both
these overheads would be avoided with this feature.

Upon reflection, it seems to me that the practical
use to which this feature could be put, in order to
explain its existence, is most likely something to do
with optimizing merge sort routines.

Considerably more information about the Honeywell 800
computer is available at
this
site.

The next instruction format shown is that of the I.C.T. Atlas computer,
famous for introducing the concept of virtual memory under the name "single-level store".

Next is shown the instruction formats of the NCR 315 computer.
This commercial computer is notable for having a memory addressable
in units of 12 bits, which it called slabs, that could contain either
two six-bit characters or four binary-coded decimal digits, and for
a large-capacity random-access storage system, providing rapid selection
of a strip of magnetic tape, known as CRAM, for card random-access
memory. IBM's Data Cell is another example of a storage device in this
class. Since other computers with 24-bit instructions did not also have
a two-word instruction format, its instructions are shown in this diagram
rather than in the preceding one.

The instruction format of the AN/FSQ-32 computer is described
as well. The first of the five lines giving its instruction formats
shows those for ordinary integer arithmetic instructions as well as
load and store instructions. The bit marked as K indicates an
immediate operand (in a floating-point instruction, this bit is instead
used to indicate an unnormalized operation). The displacement field
is used to indicate that the source operand will be shifted by the
multiple of six bits indicated prior to the operation. The mode field
indicates whether 48-bit arithmetic is performed, or 24-bit arithmetic
on both halves of the accumulator, and in addition indicates in the latter
case if only one half of the accumulator is used to perform arithmetic, or
if the least significant 24 bits of the source operand will be duplicated
prior to the operation, called twinning. The activity field enables or
disables individual six-bit areas of the accumulator. Character displacement,
twinning, and the effects of the activity field are performed in that order.
The S bit is used for sign extension (the AN/FSQ-32 performed one's complement
arithmetic).

The I bit indicated indirect addressing, and the D bit indicated
something called double indexing: a special register indicated which
register could be used as a second index register in an instruction.
The sX field indicated either one of eight possible index registers, or
program-counter relative addressing, or using the accumulator as an
index.

In the second line, we see the format of logical instructions.
The four-bit field marked connective gives the different bit values
to be placed in the result for each of the four combinations of an 0
or 1 bit respectively in the source and destination operands. The
activity field, indicating which six-bit characters are affected,
is also present, but if the M bit is set, the B register is used
as a mask for the operation instead.

In the third line, we see the format of the convert instructions,
which perform character translation. The dXR field indicates an
index register that can be changed by the instruction, and the R bit
will cause one of the convert instructions to proceed from right to
left.

In the fourth line, we see the format of a shift instruction.
The K bit allows the index registers to modify the shift count,
the S bit indicates the direction of the shift, and the R bit
indicates rounding for left shifts.

The fifth line indicates the formats of the instructions of the
branch decrement type, reminiscent of the IBM 704 architecture,
but offering a more complete set of instructions.

Not shown are the instruction formats of the Philco 213 computer,
although they were described in a supplement to the proceedings of a
Fall Joint Computer Conference with papers on large computers, also
including the Control Data 6600 and the IBM System/360 model 92 (which,
of course, became the model 91 before becoming available for sale), as
this computer did not reach the stage of manufacture.

The English Electric KDF9 is also significant in the history
of computing, playing a significant role in the development of
the computer language Algol. Its instructions were composed of
from one to three 'instruction syllables', eight bits in length.
Such short instructions were possible because the machine was
stack-oriented, like a series of Burroughs machines whose
first member was released almost contemporaneously with the
KDF9. (During its lifetime, it became the English Electric Leo
KDF9 and then the English Electric Leo Marconi KDF9!)

The ICL 1900 computer was previously the ICT 1900 computer;
behind the Iron Curtain, the ODRA 1304 computer was made in
imitation of it, but, according to at least one web site, under
license.

It may also be noted that the Philco 2000 computer was
advertised as the first commercially-available computer made with
transistors instead of vacuum tubes, and it was closely followed
by the Control Data 1604 computer. However, they both appear to
have been preceded by the Metro-Vick
(or Metropolitan-Vickers) MV950 computer in Britain.

I remember, long ago, reading about how an Armenian in the
U.S., despite feeling no sympathy for the Soviet system, felt a
twinge of pride at reading a news item about a computer being
designed and built in Soviet Armenia. I had imagined, as I read
this, that the computer he was reading of would likely have had
a 24-bit word length.

In a web search, I had found "Nairi" as the name of an older
Soviet computer produced in Armenia. Other references stated that
this computer was an imitation of the PDP-11.

I have since learned, however, that this may have been true of
a later computer for which that name was used, but the original
Nairi dates from 1964, and it had a 36-bit word. One unique feature
is that in addition to the exponent part of floating point numbers
having a sign bit, the sign of the mantissa occupied two bits at the
start of the word. A later computer in that series, the Nairi-3,
is famous for being the first Soviet computer made from integrated
circuits; the circuits are described as "hybrid" integrated circuits,
and so they may be similar to the Solid Logic Technology (SLT) used
with the original IBM System/360.

Afterwards, Armenia produced several of
the EC series of computers, compatible with the IBM System/360.
But then, there was the Hrazdan-3 and its predecessors; perhaps
they had a 24-bit word length, but I have not been able to determine
this. In any event, I have found the possible reason why,
subconsciously, I associate 24-bit architectures with small,
obscure countries.

The ICL 1900 was
closely derived from the Ferranti-Packard 6000 computer, which was
designed in... Canada! (It apparently has, from the Web, ancestors
in both a Canadian military computer, the DATAR, and an Australian
computer called the Cirrus.) Its instructions were composed of
a 3-bit destination register field, followed by a 7-bit opcode,
and then a 2-bit index register field, with 12 bits left at the end
for the address.

One notable thing about the DATAR that I discovered in my web
surfing for more information on 24-bit computers in general, and
then the ICL 1900 in particular, was that it
came equipped with an early trackball... which used, for the
ball itself, a bowling ball! It was, however, the
slightly smaller bowling ball used for five-pin bowling, which
is also better suited for trackball use in that it does not
have the three finger holes of ordinary 10-pin bowling balls.
(Sorry to disappoint you!)