Parallel random access machines, Computer Networking

PRAM is one of the models used for designing the parallel algorithm as given in Figure. The PRAM models have the following components:

A set of identical type of processors state P1, P2, P3 ...Pn.

It contains a single shared memory module being shared by all the N processors. As the processors can't communicate with each other directly, shared memory acts as a communication medium for the processors.

In direct to connect the N processor with the single shared memory, a component called Memory Access Unit (MAU) is used for accessing the shared memory.

PRAM Model

The Following steps are followed by a PRAM model while implementing an algorithm:

i) Read phase: Firstly, the N processors concurrently read data from N different memory locations of the shared memory and subsequently save the read data into its local registers.

ii) Compute phase: After that, these N processors perform the logical or arithmetic operation on the data stored in their local registers.

iii) Write phase: Lastly, the N processors parallel write the computed values from their local registers into the N memory locations of the shared memory.