Yeah. Supposedly the idea was low power, tons of threads. No L2 cache, but who cares about high latency when you’ve got high throughput. Etc, etc.

It’s hard to know what low power means here since they don’t give out numbers. For example, the T1 was “high efficiency” 72W at a time when a quad core xeon was 150W. Today, that 150W gets your xeon 18 cores (and 36 threads, 4 more than the T1).