A vertical PNP structure for use in a merged bipolar/CMOS technology has a P+ buried layer (84) as a collector region, which is isolated from the P substrate (48) by an N- buried layer (82). The P+ buried layer (84) diffuses downwards into the N- buried layer (82) and upwards into a P- epitaxy layer ...

A Schottky diode circuit 20 is formed on a semiconductor layer 24. A conductive contact 36 on the surface of the semiconductor layer 24 forms a Schottky barrier 40 at the junction of the conductive contact 36 and the semiconductor layer 24. A guard ring 26 in the semiconductor layer 24 is adjacent t ...

The present invention relates to a method of manufacturing a semiconductor integrated device and, more particularly, to a semiconductor integrated device having NPN and PNP power and logic devices combined with complementary MOS and DMOS devices. The present invention is a multipitaxial process for ...

A unified process flow for the fabrication of an isolated vertical PNP (VPNP) transistor, a junction field effect transistor (JFET) and a metal/nitride/polysilicon capacitor includes the simultaneous fabrication of deep junction isolation regions (36, 121) and a VPNP buried collector (28). Junction ...

A buried n-channel junction field-effect transistor (JFET) fabricated in standard bipolar integrated circuit starting material. The transistor has a deep p-well as the bottom gate formed in an n-type body. The source is surrounded by the p-well while the drain is the epitaxial layer near the surface ...

A vertical PNP structure for use in a merged bipolar/CMOS technology has a P+ buried layer (84) as a collector region, which is isolated from the P substrate (48) by an N- buried layer (82). The P+ buried layer (84) diffuses downwards into the N- buried layer (82) and upwards into a P- epitaxy layer ...

A Schottky diode circuit 20 is formed on a semiconductor layer 24. A conductive contact 36 on the surface of the semiconductor layer 24 forms a Schottky barrier 40 at the junction of the conductive contact 36 and the semiconductor layer 24. A guard ring 26 in the semiconductor layer 24 is adjacent t ...

An integrated circuit device of a first N-type epitaxial layer over a substrate, a second P-type epitaxial layer over the first epitaxial layer, and a third N-type epitaxial layer over the second epitaxial layer, with a P-type buried ground region formed in a portion of the substrate, the ground reg ...

A semiconductor Hall effect device having a stable and more controllable offset voltage is formed, in one embodiment, of an N-type silicon epitaxial layer overlying a P-type silicon substrate, and a P+-type region is formed, for example, by ion implantation, in the surface of the epitaxial layer ove ...