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High Yield, Near Void-Free Assembly Process of a Flip Chip in Package Using No-Flow Underfill

Keywords: flip chip, yield, reliability

The advanced assembly process for a flip chip in package (FCIP) using no-flow underfill material presents challenges with high I/O density (over 3000 I/O) and fine-pitch (down to 150 µm) interconnect applications because it has narrowed the feasible assembly process of high electrical interconnect yield.
In spite of such challenges, a high (>99.99%), reliable (sample size: 30) yield and nearly void-free (≈ 7.0%) assembly process has been achieved using commercial no-flow underfill material with a high I/O, fine pitch FCIP in our past research. The existing 7% void area could cause early failures such solders fatigue cracking or solder bridge in thermal reliability. Therefore, this study reviewed a classical bubble nucleation theory to predict the conditions of voids nucleation in assembly process. On the models prediction, systematic experiments were designed to eliminate underfill voiding using parametric studies. First, a void formation study investigated the effect of reflow parameter on underfill voiding and found process conditions of void-free assembly with robust interconnections. Second, a void formation characterization validated the determined reflow conditions to achieve a high yield and void-free assembly process, and the stability of assembly process using a large scale of assemblies respectively.
Thus, this paper presents systematic studies into void formation study and void formation characterization through the use of structured experimentation which was designed to achieve a high, stable yield and void-free assembly process on the classical bubble nucleation. Indeed, the theoretical models were a good agreement in experimental results with a small discrepancy.