Lab 5: Implementing Arrays as RTL Interfaces – Analyze the impact of manipulating arrays. Utilize directives to choose the type of memories to be implemented for the arrays.

Lab 6: Improving Area and Resource Utilization – Observe the impact of various directives on resource utilization and performance.

Lab 7: HLx Flow - System Integration – Set up an embedded design, create an HLS IP with the AXI Lite interface, import the IP into the embedded design, and validate the system on the demo board.

* This course focuses on the Zynq-7000 All Programmable SoC and 7 series FPGA architectures. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

After completing this comprehensive training, you will have the necessary skills to:

Enhance productivity using the Vivado HLS tool

Describe the high-level synthesis flow

Use the Vivado HLS tool for a first project

Identify the importance of the testbench

Use directives to improve performance and area and select RTL interfaces

Identify common coding pitfalls as well as methods for improving code for RTL/hardware