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Abstract:

In one embodiment, an apparatus can include a trench extending into a
semiconductor region of a first conductivity type, an electrode disposed
in the trench, and a source region of the first conductivity type
abutting a sidewall of the trench. The apparatus can include a first well
region of a second conductivity type disposed in the semiconductor region
below the source region and abutting the sidewall of the trench lateral
to the electrode where the second conductivity type is opposite the first
conductivity type. The apparatus can also include a second well region of
the second conductivity type disposed in the semiconductor region and
abutting the sidewall of the trench, and a third well region of the first
conductivity type disposed between the first well region and the second
well region.

Claims:

1. An apparatus, comprising: a pair of trenches extending into a
semiconductor region of a first conductivity type; a shield electrode
disposed in a trench from the pair of trenches; a gate electrode disposed
above and insulated from the shield electrode; a source region of the
first conductivity type associated with the trench; a first well region
of a second conductivity type disposed in the semiconductor region
between the pair of trenches and below the source region, the first well
region abutting a sidewall of the trench from the pair of trenches, the
second conductivity type being opposite the first conductivity type; a
second well region of the second conductivity type disposed in the
semiconductor region between the pair of trenches; and a third well
region of the first conductivity type disposed between the first well
region and the second well region.

2. The apparatus of claim 1, wherein the first well region, the second
well region, and the third well region are associated with the shield
electrode.

3. The apparatus of claim 1, wherein the first well region, the second
well region, and the third well region are disposed lateral to the shield
electrode.

4. The apparatus of claim 1, wherein the shield electrode is formed
relative to the first well region and the second well region such that a
channel is formed in each of the first well region and the second well
region when a voltage is applied to the shield electrode.

5. The apparatus of claim 1, wherein the shield electrode is a first
shield electrode, the apparatus further comprising: a second shield
electrode electrically insulated from the first shield electrode.

6. The apparatus of claim 1, wherein the shield electrode is a first
shield electrode, the first well region, the second well region, and the
third well region are disposed lateral to the first shield electrode, the
apparatus further comprising: a second shield electrode electrically
insulated from the first shield electrode.

7. The apparatus of claim 1, wherein the shield electrode is a first
shield electrode, the apparatus further comprising: a second shield
electrode; a dielectric disposed in the trench between the first shield
electrode and the second shield electrode, the second shield electrode is
electrically coupled to the first shield electrode.

8. An apparatus, comprising: a trench extending into a semiconductor
region of a first conductivity type; an electrode disposed in the trench;
a source region of the first conductivity type abutting a sidewall of the
trench; a first well region of a second conductivity type disposed in the
semiconductor region below the source region and abutting the sidewall of
the trench lateral to the electrode, the second conductivity type being
opposite the first conductivity type; a second well region of the second
conductivity type disposed in the semiconductor region and abutting the
sidewall of the trench; and a third well region of the first conductivity
type disposed between the first well region and the second well region.

9. The apparatus of claim 8, wherein the first well region, the second
well region, and the third well region are associated with the electrode.

10. The apparatus of claim 8, wherein the electrode is a shield
electrode, the shield electrode is formed relative to the first well
region and the second well region such that a channel is formed in each
of the first well region and the second well region when a voltage is
applied to the shield electrode.

11. The apparatus of claim 8, wherein the electrode is a shield
electrode, the apparatus further comprising: a gate electrode disposed
above and insulated from at least a portion of the shield electrode; and
a fourth well region disposed between the first well region and source
well region, the fourth well region being disposed lateral to the gate
electrode.

12. The apparatus of claim 8, wherein the electrode is a gate electrode,
the apparatus further comprising: a shield electrode disposed below and
insulated from at least a portion of the gate electrode, the second well
region being disposed lateral to the shield electrode.

13. The apparatus of claim 8, wherein the electrode is a first shield
electrode, the apparatus further comprising: a second shield electrode
electrically insulated from the first shield electrode.

14. The apparatus of claim 8, wherein the electrode is a first shield
electrode, the first well region, the second well region, and the third
well region are disposed lateral to the first shield electrode, the
apparatus further comprising: a second shield electrode electrically
insulated from the first shield electrode.

15. The apparatus of claim 8, wherein the electrode is a first shield
electrode, the apparatus further comprising: a second shield electrode; a
dielectric disposed in the trench between the first shield electrode and
the second shield electrode, the second shield electrode is electrically
coupled to the first shield electrode.

16. An apparatus, comprising: a trench extending into a semiconductor
region of a first conductivity type; a shield electrode disposed in the
trench; a gate electrode disposed above and insulated from the shield
electrode; a source region of the first conductivity type abutting a
sidewall of the trench; a first well region of a second conductivity type
disposed in the semiconductor region below the source region and abutting
the sidewall of the trench, the second conductivity type being opposite
the first conductivity type; a second well region of the second
conductivity type disposed in the semiconductor region; and a third well
region of the first conductivity type disposed between the first well
region and the second well region.

17. The apparatus of claim 16, wherein the first well region, the second
well region, and the third well region are disposed lateral to the shield
electrode.

18. The apparatus of claim 16, wherein the shield electrode is formed
relative to the first well region and the second well region such that a
channel is formed in each of the first well region and the second well
region when a voltage is applied to the shield electrode.

19. The apparatus of claim 16, further comprising: a heavy body region of
the second conductivity type in contact with the source region.

20. The apparatus of claim 16, wherein the gate electrode and the shield
electrode are positioned relative to the first well region and second
well region such that a channel is formed in each of the first well
region and the second well regions when the apparatus is biased in the on
state.

Description:

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation of U.S. Non-Provisional patent
application Ser. No. 12/823,037, filed Jun. 24, 2010, entitled, "METHOD
FOR FORMING SHIELDED GATE TRENCH FET WITH MULTIPLE CHANNELS," which
claims priority to and is a divisional of U.S. Non-Provisional patent
application Ser. No. 11/964,283, filed Dec. 26, 2007, entitled, "SHIELDED
GATE TRENCH FET WITH MULTIPLE CHANNELS," (Now U.S. Pat. No. 7,772,668),
both of which are incorporated by reference herein in their entireties.

TECHNICAL FIELD

[0002] The present disclosure relates in general to semiconductor
technology, and more particularly to structures and methods for forming
shielded gate trench FETs having multiple channels along each trench
sidewall.

BACKGROUND

[0003] Shielded gate trench field effect transistors (FETs) are
advantageous over conventional FETs in that the shield electrode reduces
the gate-drain capacitance (Cgd) and improves the breakdown voltage of
the transistor without sacrificing the transistor on-resistance. FIG. 1
is a simplified cross-sectional view of a conventional shielded gate
trench MOSFET 100. N-type epitaxial layer 102 extends over highly doped
n-type substrate 101. Substrate 101 serves as the drain contact region.
Highly doped n-type source regions 108 and highly doped p-type heavy body
regions 106 are formed in p-type well region 104 which is in turn formed
in epitaxial layer 102. Trench 110 extends through well region 104 and
terminates in the portion of epitaxial layer 102 bounded by well region
104 and substrate 101, which is commonly referred to as the drift region.

[0005] While inclusion of shield electrode 114 under gate electrode 122
has improved certain performance characteristics of the transistor (such
as the breakdown voltage and Cgd), further improvements in these and
other electrical and structural characteristics (such as the transistor
on-resistance Rdson and unclamped inductive switching UIS characteristic)
have been difficult to achieve. This is because, most known techniques
for improving certain electrical characteristics of the FET often
adversely impact other electrical characteristics or require significant
changes to the process technology.

[0006] Thus, there is a need for cost effective techniques where various
electrical characteristics of a trench gate FET can be improved without
compromising other electrical characteristics.

BRIEF SUMMARY

[0007] In one embodiment, an apparatus can include a trench extending into
a semiconductor region of a first conductivity type, an electrode
disposed in the trench, and a source region of the first conductivity
type abutting a sidewall of the trench. The apparatus can include a first
well region of a second conductivity type disposed in the semiconductor
region below the source region and abutting the sidewall of the trench
lateral to the electrode where the second conductivity type is opposite
the first conductivity type. The apparatus can also include a second well
region of the second conductivity type disposed in the semiconductor
region and abutting the sidewall of the trench, and a third well region
of the first conductivity type disposed between the first well region and
the second well region.

[0008] In another embodiment, an apparatus can include a pair of trenches
extending into a semiconductor region of a first conductivity type, a
shield electrode disposed in a trench from the pair of trenches, and a
gate electrode disposed above and insulated from the shield electrode.
The apparatus can include a source region of the first conductivity type
associated with the trench, and a first well region of a second
conductivity type disposed in the semiconductor region between the pair
of trenches and below the source region. The first well region can abut a
sidewall of the trench from the pair of trenches, and the second
conductivity type can be opposite the first conductivity type. The
apparatus can include a second well region of the second conductivity
type disposed in the semiconductor region between the pair of trenches,
and a third well region of the first conductivity type disposed between
the first well region and the second well region.

[0009] In another embodiment, an apparatus can include a trench extending
into a semiconductor region of a first conductivity type, an electrode
disposed in the trench, and a source region of the first conductivity
type abutting a sidewall of the trench. The apparatus can include a first
well region of a second conductivity type disposed in the semiconductor
region below the source region and abutting the sidewall of the trench
lateral to the electrode where the second conductivity type is opposite
the first conductivity type. The apparatus can include a second well
region of the second conductivity type disposed in the semiconductor
region and abutting the sidewall of the trench, and a third well region
of the first conductivity type disposed between the first well region and
the second well region.

[0010] Further features of the invention, its nature and various
advantages will be more apparent from the accompanying drawings and the
following detailed description of embodiments of the invention.

[0021] In accordance with embodiments of the present invention, shielded
gate trench FETs having multiple channels along each trench sidewall and
methods of manufacturing the same are described. As will be seen, such
FETs substantially improve upon certain performance characteristics of
prior art FET structures without sacrificing other performance
characteristics of the transistor. These improvements include higher
BVdss, lower Rdson, lower gate charge, and improved UIS and snap back
characteristic. A first exemplary embodiment of the invention will be
described with reference to FIG. 2A.

[0026] As can be seen, shielded gate FET 200 is structurally similar in
many respects to conventional shielded gate FETs except that an
additional well region 215 is embedded in the drift region adjacent to
shield electrode 235a. Because of the proximity of well region 215 to
shield electrode 235a, well region 215 is herein referred to as "shield
well region," and because of the proximity of well region 225 to gate
electrode 240a, well region 225 is herein referred to as the "gate well
region." Shield well region 215 laterally extends the full width of the
mesa region and abuts sidewalls of two adjacent trenches, thus breaking
up the drift region into an upper drift region 220 and a lower drift
region 210.

[0027] During operation, with source regions 245a and drain region 205a
biased to proper voltages, upon applying an appropriate positive voltage
to each of gate electrode 240a ad shield electrode 235a, channels 244 and
217 are respectively formed in gate well region 225 and shield well
region 215 along the trench sidewalls. Thus, a current path is formed
between source regions 245a and drain region 205a through gate well
region 227, upper drift region 220, shield well region 215 and lower
drift region 210. By embedding shield well region 215 in the drift region
directly next to shield electrode 235a, in effect, two transistors
serially connected between the drain and source regions are formed. This
is more clearly shown in the equivalent circuit diagram in FIG. 2B. In
FIG. 2B, gate terminal 240b of upper transistor 260, shield terminal 235b
of lower transistor 270, source terminal 245b, and drain terminal 205b
correspond to gate electrode 240a, shield electrode 235a, source regions
245a and drain region 205a in FIG. 2A, respectively.

[0028] FIGS. 3A-3C are cross section views of three exemplary variations
of the dual channel shielded gate FET in FIG. 2A. FET 300a in FIG. 3A is
similar to FET 200 in FIG. 2A except that two shield well regions 315a1,
315a2 are embedded in the drift region instead of one. Both shield well
regions 315a1, 315a2 are directly next to shield electrode 335a and thus,
a channel is formed in each of shield well regions 315a1 and 315a2 when
FET 300 is turned with a positive voltage applied to shield electrode
335a. Accordingly, a total of three channels 317a1, 317a2, 327 are formed
along each trench sidewall when FET 300a is turned on. Note that the two
shield well regions 315a1, 315a2 breakup the drift region into three
regions: upper drift region 320a, middle drift region 313a, and lower
drift region 310.

[0029] FET 300b in FIG. 3B is similar to FET 300a in FIG. 3A except that
two shield electrodes 335b1, 335b2 are disposed in trench 330b instead of
one. Each of the shield electrodes 335b1 and 335b2 has a corresponding
shield well region 315b1, 315b2 adjacent thereto. Thus, to form a channel
in each shield well region 315b1 and 315b2, an appropriate positive
voltage needs to be applied to each shield electrode 335b1 and 335b2,
respectively. While shield electrodes 335b1 and 335b2 are shown being
insulated form one another, they can be extended in a dimension into the
page and routed up and out of the trench where they can be electrically
tied together. Alternatively, shield electrodes 335b1 and 335b2 can be
tied to two different voltage sources.

[0030] FET 300C in FIG. 3c is similar to FET 300b in FIG. 2C except that a
total of four shield well regions 315c11, 315c12, 315c21, 315c22 are
embedded in the drift region, two for each of two shield electrodes
335c1, 335c2. A total of five channels 317c11, 317c12, 317c21, 317c22,
327 are thus formed when FET 300C is turned on with proper positive
voltages applied to each of the three electrodes 340, 335c2 and 335c1. As
can be seen from the exemplary variations in FIGS. 3A-3C, many
combinations and permutations of shield electrodes and shield well
regions are possible, and as such the invention is not limited to the
particular combinations shown and described herein.

[0031] Next, two exemplary process techniques for forming the FET
structure similar to that in FIG. 2A will be described. Modifying these
process techniques to arrive at the FET structure variations in FIGS.
3A-3C or other permutations and combinations of shield well regions and
shield electrodes would be obvious to one skilled in the art in view of
this disclosure.

[0032] FIGS. 4A-4E are cross section views at various stages of a process
for forming a dual channel shielded gate trench FET in accordance with an
exemplary embodiment of the invention. In FIG. 4A, epitaxial region 410a
is formed over semiconductor substrate 405 using known techniques.
Epitaxial region 410a and semiconductor substrate 405 may be doped with
an n-type dopant, such as, arsenic or phosphorous. In one embodiment,
semiconductor substrate 405 is doped to a concentration in the range of
1×1019-1×1021 cm-3, and epitaxial region 410a
is doped to a concentration in the range of
1×1018-1×1019 cm-3.

[0033] In FIG. 4B, trenches 430 are formed in epitaxial region 410a using
known silicon etch techniques. In an alternate embodiment, trenches 430
are etched deeper to terminate within substrate 405. In FIG. 4c, the
various regions and layers in trenches 430 are formed using conventional
techniques. Shield dielectric 442 (e.g., comprising one or both oxide and
nitride layers) lining lower sidewalls and bottom of trenches 430 is
formed using such known techniques as chemical vapor deposition (CVD) of
silicon nitride, CVD oxide, or thermal oxidation of silicon. Shield
electrode 435 (e.g., comprising doped or undoped polysilicon) is formed
in a lower portion of each trench 430 using, for example, conventional
polysilicon deposition and etch back techniques.

[0034] IED 438 (e.g., comprising thermal oxide and/or deposited oxide) is
formed over shield electrode 435 using, for example, conventional thermal
oxidation and/or oxide deposition techniques. Gate dielectric 444 (e.g.,
comprising oxide) lining upper trench sidewalls is formed using, for
example, known thermal oxidation methods. Recessed gate electrode 440 is
formed over IED 438 using, for example, conventional polysilicon
deposition and etch back methods. While IED 438 is shown to be thicker
than gate dielectric 444, in an alternate embodiment, they are formed
simultaneously and thus have the same thickness. If additional shield
electrodes are to be formed in trenches 430 (as in FIGS. 3B and 3C), the
above process steps for forming the shield electrode and the IED can be
repeated the requisite number of times.

[0035] In FIG. 4D, a first p-type well region 425 (gate well region) is
formed in epitaxial layer 410a by implanting and driving in p-type
dopants in accordance with known techniques. In one embodiment, gate well
region 425 may be doped with dopants, such as, Boron to a concentration
in the range of 1×1017-1×1018 cm-3. A high
energy implant of p-type dopants is then carried out to form a second
p-type well region 415 (shield well region) deeper in epitaxial layer
410a directly next to shield electrode 435 using known techniques. In one
embodiment, shield well region 415 may be doped with dopants, such as,
Boron to a concentration in the range of
1×1016-1×1018cm-3.

[0036] The implant parameters for shield well region 435 need to be
carefully selected to ensure that shield well region 415, upon completion
of processing, is properly aligned with shield electrode 435 so that a
channel can be formed therein when shield electrode 435 is biased in the
on state. In the embodiments where multiple shield electrodes are formed
in each trench, multiple shield well implants with different implant
energies may be carried out to form multiple shield well regions, each
being directly next to a corresponding shield electrode. Note that the
implant for forming shield well region 415 is carried out after the
implant for gate well region 425 in order to avoid out-diffusion of
shield well region 415 during the gate well region 425 drive-in. However,
with carefully controlled implant and drive-in processes, the order of
the two implants may be reversed.

[0037] In FIG. 4E, a conventional source implant is carried out to form a
highly doped n-type region laterally extending through an upper portion
of gate well region 425 and abutting trenches 430. None of the implants
up to this point in the process requires a mask layer, at least in the
active region of the die. In one embodiment, a dielectric layer is formed
over gate electrodes 440 prior to the three implants.

[0038] Dielectric caps 446 (e.g., comprising BPSG) extending over gate
electrodes 440 and laterally overlapping the mesa regions adjacent
trenches 430 are formed using known methods. Dielectric caps 446 thus
form an opening over a middle portion of the mesa region between adjacent
trenches. A conventional silicon etch is carried out to form a recess in
the n-type region through the opening formed by dielectric caps 446. The
recess extends to below a bottom surface of the n-type region and into
gate well region 425. The recess thus breaks up the n-type region into
two regions, forming source regions 445.

[0039] A conventional heavy body implant is carried out to form heavy body
region 449 in body region 425 through the recess. A topside interconnect
layer 448 is then formed over the structure using known techniques.
Topside interconnect layer 448 extends into the recess to electrically
contact source regions 445 and heavy body region 449. A backside
interconnect layer 402 is formed on the backside of the wafer to
electrically contact substrate 405. Note that the cell structure in FIG.
4E is typically repeated many times in a die in a closed cell or an open
cell configuration.

[0040] FIGS. 5A-5F depict an alternate process for forming a dual channel
shielded gate trench FET in accordance with another exemplary embodiment
of the invention. In FIG. 5A, similar to FIG. 4A, n-type epitaxial layer
510a is formed over substrate 505 using known techniques. In FIG. 5B,
p-type shield well region 515 is formed either by forming a p-type
epitaxial layer over n-type epitaxial layer 510a or by implanting p-type
dopants into n-type epitaxial layer 510a to convert an upper layer of
epitaxial layer 510a to p-type. Shield well region 515 may be capped with
a thin layer of arsenic doped epi (not shown) to prevent up-diffusion of
the dopants in shield well region 514 during subsequent heat cycles.

[0041] In FIG. 5C, n-type drift region 520 is formed by forming an n-type
epitaxial layer over shield well region 510a. In FIG. 5D, using
conventional techniques, trenches 530 are formed extending through the
various semiconductor layers and terminating within bottom-most drift
region 510b. Alternatively, trenches 530 may be extended deeper to
terminate within substrate 505. In FIG. 5E, shield dielectric layer 442,
shield electrode 435, IED 438, gate dielectric 444, and gate electrode
440 may be formed in trenches 530 in a similar manner to those described
above in reference to FIG. 4c, and thus will not be described.

[0042] P-type gate well region 525 is formed next by implanting p-type
dopants into n-type drift region 520 to thereby convert an upper layer of
drift region 520 to p-type. In FIG. 5F, dielectric cap 546, source
regions 545, heavy body region 549, topside interconnect layer 548 and
backside interconnect layer 502 are all formed in a similar manner to
those described above in reference to FIG. 4E and thus will be not
described.

[0043] In accordance with embodiments of the invention, the one or more
shield electrodes in the trenches may be biased in a number of different
ways. For example, the one or more shield electrodes may be biased to a
constant positive voltage, may be tied to the gate electrode (so that the
shield and gate electrodes switch together), or may be tied to a
switching voltage independent of the gate voltage. The means for biasing
of the one or more shield electrodes may be provided externally or
generated internally, for example, from available supply voltages. In the
embodiments where the shield electrode is biased independent of the gate
electrode biasing, some flexibility is obtained in terms of optimizing
various structural and electrical features of the FET.

[0044] In one embodiment where the gate electrode is switched between 20V
(on) and 0V (off), the shield electrode is switched between 20V (on) and
10V (off). This limits the maximum voltage across IED 238 (FIG. 2A) to
10V, thus allowing a relatively thin IED to be formed. Simulation results
for this embodiment show a 45% improvement in Rdson, a BVdss of about
30V, and a substantially low gate charge Qg. In another embodiment where
gate electrode 240a is switched between 20V (on) and 0V (off), shield
electrode 235a is biased to 20V during both the on and off states.
Simulation results for this embodiment have shown a 25% improvement in
Rdson, a BVdss of about 30V, and a substantially low Qg.

[0045] Thus, the desired operational voltages to be applied to gate
electrode 240a and shield electrode 235a determine the thickness and
quality of IED 238. In the embodiments where a smaller voltage
differential appears across IED 238 (FIG. 2A), a thinner IED 238 may be
formed which advantageously enables forming a thinner upper drift region
220 thus obtaining a lower Rdson. A further reduction in Rdson is
obtained by the virtue of forming a second channel along each trench
sidewall. These and other advantages and features of the various
embodiments of the invention are described more fully with reference to
the simulation results shown in FIGS. 6-9.

[0046]FIG. 6 is a plot of simulation results showing the electric field
profile along the depth a dual channel shielded gate FET 600. As shown,
two electric field peaks occur at locations 617 and 627 corresponding to
the pn junctions formed by each of well regions 625 and 615 and their
underlying drift regions 620 and 604, respectively. In contrast, in
conventional single channel shielded gate FETs such as FET 100 in FIG. 1,
only one peak occurs at the pn junction between well region 104 and its
underlying drift region. Thus, the dual channel FET structure 600
advantageously increases the area under the electric field curve which
increases the transistor breakdown voltage. It can be seen that upon
embedding additional shield well regions in the drift region, additional
peaks would be induced in the electric field profile thus further
increasing the transistor breakdown voltage. The improvement in breakdown
voltage enables increasing the doping concentration in drift regions 604
and 620 thereby reducing the Rdson. That is, for the same breakdown
voltage as the prior art FET, a higher Rdson can be obtained.

[0047]FIG. 7 is a plot of simulation results showing the drain current
versus the drain voltage for each of a conventional shielded gate FET
(curve 610 marked as "control") and a dual channel shielded gate FET
(curve 620 marked as "improved"). As is readily apparent, a significant
increase in the drain current is realized by the dual channel shielded
gate FET.

[0048] In the conventional shielded gate FETs, the depletion charges in
the lightly doped drift region is a significant contributor to Qgd.
However, in the multi-channel shielded gate FET in accordance with the
invention, the impact of charges in the drift region on Qgd is
substantially minimized because the positive charges in the multiple
drift regions are compensated by the negative charges in their adjacent
multiple well regions. FIG. 8 is plot of simulation results showing the
gate-drain charge Qgd versus the voltage on the shield electrode for each
of a conventional shielded gate FET (curve 810) versus a dual channel
shielded gate FET (curve 820). A bias voltage applied to shield electrode
235a (FIG. 2A) is varied from about 6-20V and Qgd is measured. As is
apparent, a significant reduction in the gate-drain capacitance Cgd
(approximately 40% reduction at low shield bias) is realized by the dual
channel shielded gate FET.

[0049]FIG. 9 is another plot of simulation results showing the
drain-source breakdown voltage BVdss for each of a conventional
shielded gate FET (curve 910) and a dual channel shielded gate FET (curve
920). As can be seen, a significant increase in BVdss is realized by
the dual channel shielded gate FET. This provides additional flexibility
in adjusting the thickness of various dielectric layers in the trench to
improve other characteristics of the FET.

[0050] A further feature of the multiple well shielded gate FETs is the
improved UIS and snap back characteristics. The multiple well regions
result in formation of a number of back to back connected pn diodes which
function similar to the well-known multiple ring zener structure that
provides superior UIS and snap back characteristics.

[0051] Thus, as can be seen, with relatively minimal changes to the
manufacturing process (e.g., adding s shield well implant), the multiple
channel shielded gate FET in accordance with embodiments of the invention
improves various performance characteristics of the transistor without
adversely impacting its other characteristics. As set forth above, the
improvements that are achieved include lower Rdson, lower gate charge,
higher BVdss, and improved UIS and snap back characteristic.

[0052] While the above provides a complete description of various
embodiments of the invention, many alternatives, modifications, and
equivalents are possible. For example, various embodiments of the
invention have been described in the context of n-channel shielded gate
MOSFETs, however the invention is not limited only to such FETs. For
example, p-channel counterparts of the various shielded gate MOSFETs
shown and described herein may be formed by merely reversing the
conductivity type of the various semiconductor regions. As another
example, n-channel IGBT counterparts of the MOSFETs described herein may
be formed by merely reversing the conductivity type of the substrate, and
p-channel IGBT counterparts may be formed by reversing the conductivity
type of the various semiconductor regions except for the substrate.
Further, although implantation has generally been used in the exemplary
embodiments to form doped regions, one skilled in the art would recognize
that other means for forming doping regions, such as diffusion, could be
substituted or combined with the implantation steps described herein.
Therefore, the above description should not be taken as limiting the
scope of the invention, which is defined by the appended claims.