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A Verilog parser

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Overview

The Verilog parser is a program that to extracts information from multi-level combinational logic circuits written in Verilog.
This parser is developed in C, tokenizes a Verilog file, and invoke various callback methods.
The information that the parser extracts include:

The module name

The list of instantiations in the module

The list of inputs

The list of outputs

The list of internal wires

The list of logic gates

Highlights

Parses structural subset of Verilog-95, Verilog-2001 and Verilog 2005

Only applies to combinational logic circuits

What is a Verilog parser?

Parsing is the process of analyzing text made of a sequence of tokens to determine its grammatical structure on a given formal grammar.
In computing, a parser is a program which analyses files to identify the parts.
In this application to Verilog, the parser then builds a data structure based on the tokens and keywords in the netlist.

How does the parser works

The parser traverses the Verilog file line by line and stores all the lines starting with a Verilog keyword such as input, output, wire, reg, XOR, AND etc.
The parser skips comment lines, empty lines or spaces.
The parser tokenizes the valid lines and extracts all the data