Microcontroller and SRAM memory devices based upon VORAGO’s HARDSIL technology will be used in the second phase of an important science study, sponsored by Air Force Research Laboratory and hosted on the STPSat-5 experiment payload by the Air Force Space and Missile System Center Space Test Payload group and NASA. The electronics module was developed by the Air Force Research Laboratory (AFRL) and built by the COSMIAC Research Center at the University of New Mexico.

In the first phase of the experiment, the same nine HARDSIL CMOS die were sent to the International Space Station where they have been operating flawlessly since February 2016. The experiment is now being repeated in SSO. The purpose of the mission is to study the frequency and effect of high energy particle strikes on CMOS memory devices in space. An array of HARDSIL based memory chips is monitored and controlled by a VORAGO Technologies ARM® Corex®-M0 based microcontroller.

A third phase of the experiment is planned with a mission to geosynchronous orbit based upon the same HARDSIL-enabled chipset.