Abstract

In semiconductor manufacturing, finding needles in haystacks is easy compared with finding sub micron defects in modern ICs like complex microprocessors. The problem is likely to grow much worse as the relative complexity of chips (number of transistors and total wiring length) increases as the size of the smallest defects that can cause failures decreases. The use of unsupervised learning is a promising strategy towards the development of fully automated classification tools. This research intends to develop an automatic defect classification system for electrical test analysis of semiconductor wafer using an adaptive resonance theory network as a classifier. As a primary input source to the network, the system employs ebinmaps obtained from the test stage of the manufacturing process. To accomplish this task, a filtering algorithm is also implemented able to discard those wafermaps without pattern. This paper reports satisfactory results showing that the proposed system can recognised defect spatial patterns with a 82% correct e-binmap classification rate.