The ZRAM secret in the AMD Bulldoter (FX-8150/opteron62xx) and the transistor count.

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The ZRAM secret in the AMD Bulldoter (FX-8150/opteron62xx) and the transistor count.

now amd point out there are only 1.2 billion transistors in use for the bulldozer CPU.
but if so there is no space for the L3 cache.
because if you calculate the L3 cache with 8 transistors per bit it used the hole space.
if you calculate with 4 transistors per bit it it highly impossible.

the only possible workaround for this problem is "ZRAM"
right now its still a secret but maybe the bulldozer is the first cpu in the world using ZRAM.
the impact of ZRAM in the die size is bigger than a die shrink to the next level.
thats because cache makes the biggest part of a modern cpu.

maybe because of this the opteron 6200 16core is selled so cheap only 500dollars-

now amd point out there are only 1.2 billion transistors in use for the bulldozer CPU.
but if so there is no space for the L3 cache.
because if you calculate the L3 cache with 8 transistors per bit it used the hole space.
if you calculate with 4 transistors per bit it it highly impossible.

8 transistors/bit * 8 bits/byte * 8388608 bytes = 536870912 (= 536.9 million = 0.536 billion) transistors, i.e. a bit under half of the die if we take AMD's number at face value. Isn't that a fairly typical proportion for the largest cache level on modern CPUs? Also, there is a 6-transistor-per-bit SRAM cell design, though I'm not sure it would be used for cache as there are some design tradeoffs in using it.

you calculate with 8mb cache but the bulldozer do have 16mb cache.
this means 1,072 billion transistors cache....
but the hole cpu do only have 1,2 billion transistors.
do you think you can build 4 modules/8cores and the ram interface with only 0,128 billion transistors ?

Originally Posted by Ex-Cyber

i.e. a bit under half of the die if we take AMD's number at face value. Isn't that a fairly typical proportion for the largest cache level on modern CPUs? Also, there is a 6-transistor-per-bit SRAM cell design, though I'm not sure it would be used for cache as there are some design tradeoffs in using it.

i don't think they use sram at all.

with 6 transistors per bit you do have 0,804billion transistors only for cache.