Timebase Clock—The Timebase Clock is routed to the ADC and the DAC, and is used as a Sample Clock. The Timebase Clock can be provided from the onboard oscillator (which always runs at 1 GHz), the DStarA line, or the CLK IN connector. The Sample Clock is routed to the DAC regardless of the timebase class selected. The timebase is routed to the ADC after being divided down by 4, 2, or 1, depending on whether you select the 1 GHz, 500 MHz, or 250 MHz timebase class, respectively. Select the class that delivers a timebase between 150 MHz and 250 MHz to the ADC.

Samples per Channel per Clock Tick)—The samples per channel per clock tick are defined by the rate in MS/s that must be provided to the DAC. For example, if you are using the 1 GHz onboard oscillator and you need to provide 250 MS/s to the DAC, then you must provide two samples per channel per clock tick to the CLIP if you are using the Data Clock, which runs at 125 MHz.

Interpolation Factor—Interpolate the data provided to the DAC to smooth the waveform output. Choose the interpolation factor that matches your needs, as long as the update rate does not exceed 1 GHz. For example, if your data rate is 250 MS/s after configuring the samples per channel per clock tick, an interpolation factor of 4x updates the output of the DAC at a rate of 1 GHz.

DAC Clock Divider—The update rate of the DAC's output should match the divided down sample clock that the DAC uses to output the waveform. Since the timebase is routed undivided to the DAC, the DAC Clock Divider configures the clock divider on the DAC to divide the timebase down to the desired Sample Clock rate. For example, if you use the 1 GHz onboard oscillator and the desired update rate is 500 MHz, you must use a DAC clock divider of /2.

User Data 1—Once the correct entry for each column has been determined, specify the appropriate value in the User Data 1 column to the User Data 1 signal in the CLIP. If you provide a non-valid value for the User Data 1 signal, the User Command Valid signal returns an error.