Your model has possible overflow, and you want explicit
saturation protection in the generated code.

Overflows saturate to either the minimum or maximum value that
the data type can represent.

The maximum value that the int8 (signed,
8-bit integer) data type can represent is 127. Any block
operation result greater than this maximum value causes overflow
of the 8-bit integer. With the check box selected, the block
output saturates at 127. Similarly, the block output saturates
at a minimum output value of -128.

Overflows wrap to the appropriate value that is representable
by the data type.

The maximum value that the int8 (signed,
8-bit integer) data type can represent is 127. Any block
operation result greater than this maximum value causes overflow
of the 8-bit integer. With the check box cleared, the software
interprets the overflow-causing value as
int8, which can produce an unintended result.
For example, a block result of 130 (binary 1000 0010) expressed
as int8, is -126.

When you select this check box, saturation applies to every internal operation on the
block, not just the output or result. Usually, the code generation process can detect
when overflow is not possible. In this case, the code generator does not produce
saturation code.

C/C++ Code GenerationGenerate C and C++ code using Simulink® Coder™.

HDL Architecture

This block has a single, default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline

Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is
0. For more details, see ConstrainedOutputPipeline (HDL Coder).

InputPipeline

Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
0. For more details, see InputPipeline (HDL Coder).

OutputPipeline

Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
0. For more details, see OutputPipeline (HDL Coder).