IEDM goes deep on 3-D circuits

The development and implementation of 3-D circuit technology will again be thoroughly explored at this year's International Electron Devices Meeting.

Continuing on the theme of 3-D circuit technology addressed in an earlier post about this year’s International Electron Device Meeting, Rambus, Stanford University and an interesting company called Monolithic 3D will address issues related to cooling 3-D circuits. One approach compares heat extraction techniques in through-silicon vias (TSVs) to alternative technologies for stacking active layers.

Perhaps feeling the pull of futuristic sounding technologies, presentations related to silicon replacement materials attract attention based on the sheer number talks scheduled. The first of these non-silicon MOSFET papers is “Towards High Mobility GeSn Channel nMOSFETs: Improved Surface Passivation Using Novel Ozone Oxidation Method,” by Stanford University in collaboration with IMEC and GlobalFoundries.

How far into the future some of the advanced technologies may be is unclear and perhaps confused with Intel’s TriGate process already in production at 22 nm and GlobalFoundries announcements for 14 nm. A session titled “Process Technology - FinFET, ETSOI and Advanced Process Technologies” is the place to compare the competition for upcoming process nodes.

Much has been made of the timing of high-volume TSV manufacturing, but there are several technical challenges to be solved. Eric Beyne co-authored “Impact of Through-Silicon Via-Induced Mechanical Stress on Fully Depleted Bulk FinFET Technology.” Beyne is one of the best sources of information regarding TSVs.

Another paper that may help to address questions related to changing design flows for the TSV rollout can be found in Session 30. “Hybrid Modeling and Analysis of Different Through-Silicon-Via (TSV)-Based 3D Power Distribution Networks,” is a joint offering from IBM Microelectronics and Rensselaer Polytechnic Institute.

Will noise be a show-stopper for advanced technologies, particularly for low-power mobile SoCs? To get closer to an answer, peruse the abstracts in Session 19 and attend IBM’s presentation, “Statistical Measurement of Random Telegraph Noise and Its Impact in Scaled-Down High-k/Metal-Gate MOSFETs.”

Intel’s Al Fazio will moderate a panel, “Will Future Non-Volatile-Memory Contenders Disrupt NAND?" The question has persisted for decades as predicted flash scaling has failed to pan out. Alternative approaches are likely to be considered during this panel session.

It's interesting that Intel is not participating in this although perhaps not since they answered these questions for themselves a long time ago. As everyone knows, Intel is already in production with its TriGate flavor of FinFET, but in the modern CMOS era, few expect any revolutionary technologies to last more than a few nodes. SuVolta generated a lot of buzz earlier this year, so it would be quite interesting to hear Thompson's take on where things stand.

I am somewhat uncomfortable pointing this out, but the Stanford/Monolithic3D/Rambus IEDM paper (14.2) about heat extraction has absolutely nothing to do with TSVs. It talks about heat removal using inter-layer-vias of the Power Delivery Networks in monolithic 3D devices that have no TSVs. Just sayin'

The paper on reliability discussing the "Effect of Local Deformation Caused by Cu-TSVs..." has important implications to the placement of TSV's and the keep-out rules. This is something that is still developing and has many process-dependent influences (via middle or via last etc.) as well as type of stacking (die to die vs. wafer to wafer) and the die thickness.
Regrettably I could not attend IEDM this year but would be great to see more review articles as Kris also comments above.
MP Divakar