This paper describes the design of a delta-sigma (Δ-Σ)based Digital-to-Analog Converter (DAC) for a TETRA-2transmitter along with the on-chip analog filtering to meetadjacent channel specifications. The proposed design meets theadjacent channel requirements with a margin of over 10 dBwhich is adequate to cater for hardware implementation. As thedesign specifications are in process of being finalised forTETRA-2, this paper will provide a valuable reference fordesigners involved with development of TETRA-2 radioequipment.