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G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION

G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators

G09G5/18—Timing circuits for raster scan displays

Abstract

A display drive integrated circuit is for driving a display panel. The display drive integrated circuit includes a division rate output unit which outputs as a division rate corresponding to a quotient obtained by dividing by M a total number of clock cycles of a dot clock signal corresponding to a clock cycle of a horizontal synchronization signal, where M is a natural number, and a system clock generating unit which generates a system clock signal by dividing the dot clock signal using the division rate.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a display drive integrated circuit for driving a display panel, and more particularly, the present invention relates to a display drive integrated circuit and method for generating a system clock signal.

A claim of priority is made to Korean Patent Application No. 10-2006-0020395, filed Mar. 3, 2006, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

As shown in FIG. 1, the timing controller 130 includes a memory 131, and outputs control signals for controlling the timing of the gate driver circuit 140 and the source driver circuit 150. The memory 131 stores display data, and outputs display data (or image data) to the source driver circuit 150 under the control of the timing controller 130.

The gate driver circuit 140 includes a plurality of gate drivers (not shown), and continuously drives scan lines G1 through GM of the display panel 110, based on the control signals received from the timing controller 130.

The source driver circuit 150 includes a plurality of source drivers (not shown), and drives data lines S1 through SN of the display panel 110, based on the display data received from the memory 131 and the control signals received from the timing controller 130.

The display panel 110 displays the display data based on signals received from the gate driver circuit 140 and signals received from the source driver circuit 150.

The timing controller 130 receives various display data and control signals from the processor 170 via an interface 160, and updates the display data stored in the memory 131.

Examples of the processor 170 include a baseband processor and a graphics processor. When the display device 100 is configured with a baseband processor, a CPU interface establishes an interface between the display device 100 and the baseband processor. When the display device 100 is configured with a graphics processor, an RGB interface (video interface) establishes an interface between the display device 100 and the graphics processor.

In the case where an RGB interface is utilized, the display device 100 receives a vertical synchronization signal, a horizontal synchronization signal, and a dot clock signal from an external source, and generates a corresponding system clock signal. The system clock signal is used to control the display data.

However, when the frequency of the dot clock signal received from the external source changes, the frequency of the system clock signal also changes, thereby degrading the display quality of the display device 100 or increasing its power consumption.

SUMMARY OF THE INVENTION

According to an aspect of the present invention, a display drive integrated circuit for driving a display panel is provided. The display drive integrated circuit includes a division rate output unit which outputs as a division rate corresponding to a quotient obtained by dividing by M a total number of clock cycles of a dot clock signal corresponding to a clock cycle of a horizontal synchronization signal, where M is a natural number, and a system clock generating unit which generates a system clock signal by dividing the dot clock signal using the division rate.

According to another aspect of the present invention, a method of generating a system clock signal for a display drive integrated circuit which drives a display panel is provided. The method includes outputting a division rate corresponding to a quotient obtained by dividing by M a total number of clock cycles of a dot clock signal corresponding to a clock cycle of a horizontal synchronization signal, where M is a natural number, and generating the system clock signal by dividing the dot clock signal using the division rate.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects and advantages of the present invention will become readily apparent from the detailed description that follows, with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram of a conventional display device;

FIG. 2 is a block diagram of a display drive integrated circuit for generating a system clock signal according to an embodiment of the present invention;

FIG. 3A is a timing diagram for describing the counting of clock cycles of a dot clock signal corresponding to a clock cycle of a horizontal synchronization signal;

FIG. 3B is a table illustrating examples of a division rate corresponding to the bit value of a total number of clock cycles of a dot clock signal, excluding the lower K bits thereof;

FIG. 4 is a timing diagram for describing a process of generating system clock signals having various frequencies by using various division rates, according to an embodiment of the present invention;

FIG. 5 is a flowchart for describing a method of generating a system clock signal according to an embodiment of the present invention; and

FIG. 6 is a table illustrating division rates obtained by dividing by 16 the total number of clock cycles of dot clock signals having various frequencies.

DETAILED DESCRIPTION OF THE INVENTION

Exemplary but non-limiting embodiments of the present invention will now be described in detail with reference to the accompanying drawings. Like reference numerals denote like elements throughout the drawings.

FIG. 2 is a block diagram of a display drive integrated circuit 200 for generating a system clock signal according to an embodiment of the present invention. As explained below, the system clock signal may be generated at a constant frequency regardless of frequency changes of a dot clock signal.

Referring to FIG. 2, the display drive integrated circuit 200 includes a division rate output unit 210 and a system clock generating unit 270. The division rate output unit 210 outputs a division rate DIV according to a quotient obtained by dividing by M (M is a natural number) a total number of clock cycles CNT_DOTCLK of a dot clock signal DOTCLK, which correspond to a clock cycle of a horizontal synchronization signal HSYNC. The system clock generating unit 270 generates a system clock signal SYSCLK by dividing the dot clock signal DOTCLK using the division rate DIV.

The division rate output unit 210 may, for example, include a counter 220 and a division rate output device 250. The counter 220 counts the clock cycles CNT_DOTCLK of the dot clock signal DOTCLK which occur during a clock cycle of the horizontal synchronization signal HSYNC. The division rate output device 250 outputs the division rate DIV corresponding to the quotient obtained by dividing by M the total number of clock cycles CNT_DOTCLK of the dot clock signal DOTCLK. Here, M may be 2K (where K is a natural number).

According to an embodiment of the present invention, in the display drive integrated circuit 200, the horizontal synchronization signal HSYNC may have a constant frequency. Also, according to an embodiment of the present invention, in the display drive integrated circuit 200, a vertical synchronization signal VSYNC may have a constant frequency.

FIG. 3A is a timing diagram for describing the counting the number of clock cycles of a dot clock signal during a clock cycle of a horizontal synchronization signal.

FIG. 3B is a table illustrating examples of a division rate obtained by excluding the lower K bits of a binary number representing the number clock cycles of a dot clock signal during a clock cycle of a horizontal synchronization signal.

FIG. 6 is a table illustrating division rates obtained by dividing by 16 the total number of clock cycles of dot clock signals having various frequencies.

The operation of the division rate output unit 210 will now be described with reference to FIGS. 2, 3A, 3B and 6.

The counter 220 receives a horizontal synchronization signal HSYNC and a dot clock signal DOTCLK. The counter 220 counts the number of clock cycles of the dot clock signal DOTCLK which occur during a clock cycle of the horizontal synchronization signal HSYNC. FIG. 3A illustrates a dot clock signal DOTCLK whose clock cycles total n (where n is a natural number). In this case, a clock cycle THSYNC of the horizontal synchronization signal HSYNC is n times longer than a clock cycle TDOTCLK of the dot clock signal DOTCLK.

The division rate output device 250 outputs the division rate DIV according to the quotient obtained by dividing by M the total number (n) of clock cycles CNT_DOTCLK of the dot clock signal DOTCLK. FIG. 6 illustrates division rates DIV obtained by dividing by 16 the total number of clock cycles CNT_DOTCLK of different dot clock signals DOTCLKs. For example, if the total number of clock cycles CNT_DOTCLK of the dot clock signal DOTCLK, which corresponds to a clock cycle of the horizontal synchronization signal HSYNC, ranges from 256 to 271, the value obtained by dividing the clock cycles CNT_DOTCLK of the dot clock signal DOTCLK by 16 ranges from 16 to 16.94, and thus, the division rate DIV is 16. If the total number of clock cycles CNT_DOTCLK of the dot clock signal DOTCLK ranges from 272 to 287, the value obtained by dividing the clock cycles CNT_DOTCLK of the dot clock signal DOTCLK by 16 ranges from 17 to 17.94, and therefore, the division rate DIV is 17.

The division rate output device 250 may utilize only a certain number of the total number of division rates. For example, when the quotient obtained by dividing by M the total number of clock cycles CNT_DOTCLK of the dot clock signal DOTCLK is an odd number, the division rate output device 250 may output as the division rate DIV the value obtained by adding 1 to the quotient or subtracting 1 from the quotient. When the quotient obtained by dividing by M the total number of clock cycles CNT_DOTCLK of the dot clock signal DOTCLK is an even number, the division rate output device 250 may output the quotient as the division rate DIV. For example, referring to FIG. 6, the division rate output device 250 outputs 16 as the division rate DIV when the total number of clock cycles CNT_DOTCLK of the dot clock signal DOTCLK ranges from 256 to 287 (when the value obtained by dividing by 16 the total number of clock cycles CNT_DOTCLK ranges from 16 to 17.94). That is, the division rate output device 250 outputs only even-numbered division rates, thereby halving the total number of division rates DIVs output from the division rate output device 250.

Alternatively, if the quotient obtained by dividing by M the total number of clock cycles CNT_DOTCLK of the dot clock signal DOTCLK is an even number, the division rate output device 250 may output as the division rate DIV the value obtained by adding 1 to the quotient or subtracting 1 from the quotient. Also, when the quotient obtained by dividing by M the total number of clock cycles CNT_DOTCLK of the dot clock signal DOTCLK is an odd number, the quotient may be output as the division rate DIV. That is, the division rate output device 250 outputs only odd-numbered division rates, thereby halving the total number of division rates DIV output from the division rate output device 250.

The division rate output device 250 may output as the division rate DIV by excluding the lower K bits (i.e., by output the higher L−K bits) from the total number of clock cycles CNT_DOTCLK of the dot clock signal DOTCLK, which is expressed with L bits (L is a natural number, and K is a natural number less than L). More specifically, in this case, the division rate output device 250 expresses the total number of clock cycles CNT_DOTCLK of the dot clock signal DOTCLK with L bits, and outputs as the division rate DIV the bit value of the upper L−K bits. In this case, the division rate output device 250 outputs as the division rate DIV the quotient obtained by dividing by 2K the total number of clock cycles CNT_DOTCLK of the dot clock signal DOTCLK.

FIG. 3B is a table illustrating examples where L=10 and K=4. As shown, the division rate DIV is composed of the upper 6 bits of the 10 bit binary number representing the total number of clock cycles CNT_DOTCLK of a dot clock signal DOTCLK.

FIG. 4 is a timing diagram illustrating a process of generating system clock signals having various frequencies by using various division rates, according to an embodiment of the present invention. Referring also to FIG. 2, the system clock generating unit 270 receives a division rate DIV from the division rate output unit 210. The system clock generating unit 270 divides a dot clock signal DOTCLK by a value obtained by multiplying the division rate DIV by a predetermined value so as to generate system clock signals SYSCLK16, SYSCLK24, SYSCLK32, and SYSCLK48 having various frequencies. FIG. 4 illustrates the system clock signals SYSCLK16, SYSCLK24, SYSCLK32, and SYSCLK48 that are obtained by dividing the dot clock signal DOTCLK by various values.

Referring to the table of FIG. 6, the total number of clock cycles of a system clock signal SYSCLK, which correspond to a clock cycle of the horizontal synchronization signal HSYNC, is calculated by dividing the total number of clock cycles CNT_DOTCLK of a dot clock signal DOTCLK by the division rate DIV. That is, referring to FIG. 6, a first minimum number of clock cycles (SYSCLK) and a first maximum number of clock cycles (SYSCLK) are obtained by respectively dividing the minimum number of clock cycles (DOTCLK) and the maximum number of clock cycles (DOTCLK) by the division rate DIV. For example, when a dot clock signal DOTCLK, whose number of the clock cycles CNT_DOTCLK corresponding to a clock cycle of the horizontal synchronization signal HSYNC is 256 (or 271), is divided by the division rate DIV of 16, the number of the clock cycles of the system clock signal SYSCLK, which correspond to a clock cycle of the horizontal synchronization signal HSYNC, is 16 (or 16.94). Also, when the total number of clock cycles CNT_DOTCLK of the dot clock signal DOTCLK is 272 (or 287), the total number of clock cycles of the system clock signal SYSCLK is 16 (or 16.88).

Accordingly, the total number of clock cycles of the system clock signal SYSCLK has a constant value regardless of the total number of clock cycles of the dot clock signal DOTCLK. However, the total number of clock cycles of the system clock signal SYSCLK may have an error. The error is calculated by subtracting the first minimum number of clock cycles (SYSCLK) from the first maximum number of clock cycles (SYSCLK), which are listed in the table of FIG. 6.

According to an embodiment of the present invention, the display drive integrated circuit 200 changes the division rate DIV when the total number of clock cycles CNT_DOTCLK of the dot clock signal DOTCLK changes. Thus, even if the total number of clock cycles CNT_DOTCLK of the dot clock signal DOTCLK changes, the total number of clock cycles of the system clock signal SYSCLK can be maintained at a constant level. That is, according to an embodiment of the present invention, the display drive integrated circuit 200 is capable of outputting the system clock signal SYSCLK at a constant frequency regardless of the frequency of the dot clock signal DOTCLK.

As listed in FIG. 6, when the division rate output device 250 outputs only even-numbered division rates (or odd-numbered division rates), the total number of clock cycles of the system clock signal SYSCLK is a second minimum number of clock cycles or a second maximum number of clock cycles. For example, when the division rate output device 250 outputs only even-numbered division rates, if the total number of clock cycles CNT_DOTCLK of the dot clock signal DOTCLK is 256 (or 271), the total number of clock cycles of the system clock signal SYSCLK is 16 (or 16.94) and the division rate DIV is 16. Also, when the total number of clock cycles CNT_DOTCLK of the dot clock signal DOTCLK is 272 (or 287), the total number of clock cycles of the system clock signal SYSCLK is 17 (or 17.94) and the division rate DIV is 16.

Accordingly, the error of the total number of clock cycles of the system clock signal SYSCLK when the division rate output from the division rate output device 250 is limited to only odd numbers (or only even numbers) is approximately twice the error of the total number of clock cycles of the system clock signal SYSCLK when the division rate output from the division rate output device 250 may be even and odd numbers. That is, in the above case, the total number of clock cycles of the system clock signal SYSCLK has an error of 1.94 (17.94-16).

FIG. 5 is a flowchart for describing a method 500 of generating a system clock signal having a constant frequency regardless of the frequency of a dot clock signal, according to an embodiment of the present invention. Referring to FIG. 5, the method 500 is related to generating a system clock signal for a display drive integrated circuit that drives a display panel. According to an embodiment of the present invention, the method 500 includes outputting a division rate, and generating a system clock signal (S550). The outputting of the division rate includes outputting as a division rate the quotient obtained by dividing by M (M is a natural number) the total number of clock cycles of a dot clock signal, which correspond to a clock cycle of a horizontal synchronization signal HSYNC. The generating of the system clock signal (S550) includes generating the system clock signal by dividing the dot clock signal using the division rate.

The outputting of the division rate may include counting the clock cycles of the dot clock signal, which correspond to a clock cycle of the horizontal synchronization signal HSYNC (S510), and outputting as the division rate the quotient obtained by dividing by M the total number of clock cycles of the dot clock signal (S530).

In the method 500, M may be 2K (where K is a natural number). The outputting as the division rate (S530) may include outputting as the division rate the upper L−K bits obtained by excluding the lower K bits from the total number of clock cycles of the dot clock signal, which is expressed with L bits (L is a natural number and K is less than L).

As described above, in a display drive integrated circuit and a method for generating a system clock signal according to the present invention, the system clock signal is generated by dividing a dot clock signal by the quotient that is obtained by dividing the total number of clock cycles of the dot clock signal by a predetermined number. Therefore, it is possible to generate a system clock signal having a constant frequency even if the frequency of the dot clock signal changes.

While this invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (18)

a counter which receives a dot clock signal and a horizontal synchronization signal from an external source via an interface, and which outputs a count value equaling a total number of clock cycles of the dot clock signal corresponding to one cycle of the horizontal synchronization signal, and

a division rate output device which receives the count value and outputs a division rate value corresponding to an integer portion of a quotient obtained by dividing the count value by M where M is a natural number greater than one; and

a system clock generating unit which receives the dot clock signal and the division rate value and in response thereto generates a system clock signal by dividing a frequency of the dot clock signal by a divisor obtained by multiplying the division rate value by a fixed value.

3. The display drive integrated circuit of claim 1, wherein the count value output by the counter has L bits, and wherein the division rate output device outputs L−K bits as the division rate value by excluding lower K bits from the L bits output by the counter, where L and K are natural numbers, and K is less than L.

4. The display drive integrated circuit of any one of claims 2 and 3, wherein M=16 and K=4.

5. The display drive integrated circuit of claim 1, wherein, when the quotient obtained by dividing the count value by M is an odd number, the division rate output device outputs as the division rate value a value obtained by adding 1 to the quotient or subtracting 1 from the quotient, and when the quotient obtained by dividing the count value by M is an even number, the division rate output device outputs the quotient as the division rate value.

6. The display drive integrated circuit of claim 1, wherein, when the quotient obtained by dividing the count value by M is an even number, the division rate output device outputs as the division rate value a value obtained by adding 1 to the quotient or subtracting 1 from the quotient, and when the quotient obtained by dividing the count value by M is an odd number, the division rate output device outputs the quotient as the division rate value.

7. The display drive integrated circuit of claim 1, wherein the system clock generating unit generates system clock signals having various frequencies by dividing the frequency of the dot clock signal by an integral multiple of the division rate value.

10. A method of generating a system clock signal for a display drive integrated circuit which drives a display panel, the method comprising:

receiving a dot clock signal and a horizontal synchronization signal from an external source via an interface;

counting a number of cycles of the dot clock signal corresponding to one cycle of the horizontal synchronization signal and outputting a count value equaling a total number of clock cycles of the dot clock signal corresponding to one cycle of the horizontal synchronization signal;

dividing the count value by M to produce a quotient, where M is a natural number;

outputting a division rate value corresponding to an integer portion of the quotient; and

generating the system clock signal by dividing a frequency of the dot clock signal by a divisor obtained by multiplying the division rate value by a fixed value.

11. The method of claim 10, wherein M=2K, where K is a natural number.

12. The method of claim 10, wherein the count value has L bits, and wherein L−K bits are output as the division rate value by excluding lower K bits from the L bits, where L and K are natural numbers, and K is less than L.

13. The method of any one of claims 11 and 12, wherein M=16 and K=4.

14. The method of claim 10, wherein, when the quotient obtained by dividing the count value by M is an odd number, the division rate value is output as a value obtained by adding 1 to the quotient or subtracting 1 from the quotient, and when the quotient obtained by dividing the count value by M is an even number, the quotient is output as the division rate value.

15. The method of claim 10, wherein, when the quotient obtained by dividing the count value by M is an even number, the division rate value is output as a value obtained by adding 1 to the quotient or subtracting 1 from the quotient, and when the quotient obtained by dividing the count value by M is an odd number, the quotient is output as the division rate value.

16. The method of claim 10, wherein the generating of the system clock signal comprises generating system clock signals having various frequencies by dividing the frequency of the dot clock signal using integral multiples of the division rate value.

17. The method of claim 10, wherein the horizontal synchronization signal has a constant frequency.