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Introduction

To offer maximum flexibility in each design, the ARIA board combines
the MPC5121e with a powerful FPGA, which which allows for adaptable
I/O expansion as well as complete for adding IP-cores for additonal
customized interfaces.

To make use of this flexibility, it may be necessary to install new
versions of the FPGA code. Also, sometimes updated versions of the
FPGA code become available that fix problems and/or add new features.

In some hardware configurations the required JTAG pins of the FPGA
are connected to GPIO ports, so updates of the FPGA code can be done
in software, without using external tools like a dedicated JTAG
programmer.

Instead of writing custom software for this purpose, we decided to use the
standard !UrJTAG Universal JTAG tool.

WARNING and LEGAL DISCLAIMER

Updating the FPGA code is a very critical operation. First of
all, any attempts to meddle with the FPGA code will void any warranty you might have. And if
anything goes wrong your board will be broken, and you will not be
able to fix it.

There is absolutely, positively NO WARRANTY, neither express or
implied, offered with this documentation and software. You use this
documentation and software at your own risk. In case of loss, no
person or entity owes you anything whatsoever. You have been warned.