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Abstract

This simplified trench planarization process (STPP) is a process for VLSI chip packaging. It provides a simple and clean process for fabrication of planar structures for thin film packaging. The STPP is described as follows:

Country

United States

Language

English (United States)

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Simplified Trench Planarization Process

This simplified trench planarization process (STPP) is a
process for VLSI chip packaging. It provides a simple and clean
process for fabrication of planar structures for thin film packaging.
The STPP is described as follows:

(1) Spin and cure polyimide P onto a substrate S

coated with metal M1 (Fig. 1). (2) Deposit a second dielectric D,
e.g., SiOx, SiNx, etc.,
which also serves as an etching mask for the polyimide

(Fig. 1). (3) Form a pattern on a resist layer R1 by standard

lithographical resist patterning, leaving opening U

(Fig. 1). (4) Open features through opening U in dielectric D and

polyimide P by ion beam etching (or reactive ion

etching) to make a trench T (Fig. 2). (5) Employ in situ ion beam
cleaning (ion milling) of the
features by tilting (to change the angle of ion

incidence) and rotating the sample. (6) Deposit metallurgy (M2),
e.g., Cr-Cu-Cr, by E-beam
evaporation (Fig. 3). (7) Employ a short etch (dry or wet) to
remove possible
sidewall coverage which can also separate the metal in