We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Firefox,
Internet Explorer 11,
Safari. Thank you!

AR# 23710

13.1 TRCE/Timing Analyzer - How is clock uncertainty being calculated now that DCM jitter and phase error have been characterized for Virtex-4 (and newer) devices?

Description

How is clock uncertainty calculated for Virtex-4 and newer families?

Prior to the Virtex-4 family release, Timing Analyzer did not take into account DCM jitter and phase error automatically. Now that DCM characterization is available for Virtex-4 and newer devices, jitter and phase error values have been added to Timing Analyzer, and thus clock uncertainty is calculated using a different equation.

Solution

The following equation shows how clock uncertainty is calculated with DCM jitter and phase error:

Use Input Jitter to specify random, peak-to-peak jitter of an input clock. Specify this value by using the INPUT_JITTER keyword in a PERIOD constraint.

Use System Jitter to specify jitter caused by design conditions (toggling rate of flip-flops, I/Os, etc.) as well as board-level conditions (VCC/GND noise, outside jitter, etc.). Specify this value by adding "SYSTEM_JITTER = <value> ns; --value is in nanoseconds" to the UCF file:

DCM Jitter and Phase Error values are automatically added by the tool.

Use Input Jitter to specify random, peak-to-peak jitter of an input clock. Specify this value by using the INPUT_JITTER keyword in a PERIOD constraint.

Use System Jitter to specify jitter caused by design conditions (toggling rate of flip-flops, I/Os, etc.) as well as board-level conditions (VCC/GND noise, outside jitter, etc.). Specify this value by adding "SYSTEM_JITTER = <value> ns; --value is in nanoseconds" to the UCF file:

DCM Jitter and Phase Error values are automatically added by the tool.