DesignWare IP Videos

See how the Synopsys DDR4/3 PHY IP can program and train a wide variety of UDIMMs, RDIMMs, LRDIMMs and 3DS-DIMMs with excellent signal integrity. You’ll also see the results from a shared AC system and when reflection is introduced to the system. Marc Greenberg, Director of Product Marketing, Synopsys
Brett Murdock, Solutions Architect, Synopsys

Reduce USB 3.1 Type-C IP prototyping and integration effort using DesignWare IP Prototyping Kits. The kits provide the essential hardware and software elements needed to start implementing the certified USB 3.1 IP in an SoC in minutes. The included simulation testbench, reference drivers, and application examples enable designers to start their own IP software development right out of the box.Hugo Neto, Technical Marketing Manager, Synopsys

Learn how DesignWare ARC Processors help secure your IoT design without an extra security core, keeping area and power consumption to a minimum.Synopsys

Designing 7-nm IP, Bring It On Moore!

In keeping with Moore’s Law, discover how Synopsys is developing 10nm/7nm IP for SoC designs. Learn how tradeoffs are made in electrostatics, leakage, pattern, manufacturability and transistor performance to meet PPA requirements. See how quantum effects impact FinFET designs in terms of fin width, fin height and anything that impacts bandgap. Technology can be scaled to 7nm, bringing performance and power improvements.Navraj Nandra, Sr. Director of Marketing, Synopsys

Featured Bluetooth Video: A Complete Bluetooth® IP Solution Developed by Synopsys and Mindtree

This demonstration shows how you can enable wireless connectivity for energy-efficient IoT SoCs with Synopsys’ DesignWare Bluetooth® PHY IP on 55-nm process and Mindtree’s software stack and link layer IP. Each IP is qualified by the Bluetooth Special Interest Group and compliant with the latest specification. Manuel Mota, Technical Marketing Manager, Synopsys

What is ASIP Designer?

See how Synopsys’ ASIP Designer tool suite uses a single input specification to generate an SDK featuring a highly optimizing C compiler, instruction-set simulator, assembler, linker and debugger, and synthesizable RTL. The tool’s rapid architectural exploration capability and the ability to make rapid changes in your processor model make it easy to optimize the processor for your specific requirements. Bo Wu, Technical Marketing Manager and Steve Cox, Sr. Manager, Business Development, Synopsys

Learn about Synopsys' DesignWare® ARC® EM DSP Family, consisting of the ARC EM5D, EM7D, EM9D, and EM11D processors that are specifically designed for ultra-low power embedded DSP applications. The processors are ideally suited for DSP-intensive functions such as sensor fusion, voice detection, speech recognition and audio processing that are common in Internet of Things (IoT) and other embedded applications.Angela Raucher, Product Line Manager, ARC EM Processors, Synopsys

Object Detection Demo with DesignWare EV Family of Vision Processors

In this speed sign detection demo, see how the DesignWare EV vision processors offer high accuracy and performance for embedded vision applications. The EV vision processors are built on a multicore architecture that is optimized for vision applications, and implement a convolutional neural network (CNN) that can operate at more than 1000 GOPS/Watt.Speaker: Mike Thompson, Sr. Product Marketing Manager, ARC & Embedded Vision Processors, Synopsys

Today’s IoT devices require components such as sensors and implanted medical devices to be autonomous and have life-long renewable sources of energy. This session describes the IoT market trends, SoC components required for the IoT such as sensors and implantable devices, and energy harvesting methods. Jamil Kawa, Scientist, Synopsys

Learn about Synopsys’ embARC Open Software Platform, an easily accessible and productive solution for developing ARC processor-based embedded software. It gives software developers online access to a comprehensive suite of free and open-source software that eases the development of code for IoT and other embedded applications. Device drivers, operating systems and middleware ported to and optimized for ARC processors are available for download free of cost from the embARC.org website.Allen Watson, Product Marketing Manager, Synopsys

This video discusses the FinFET characteristics of physical IP design and how they differ from planar devices. It will describe the impact FinFETs have on existing circuit designs and layout topologies for widely used IP such as DDR, USB, PCI Express, embedded memories and logic libraries.Navraj Nandra, Sr. Director of Marketing for the DesignWare Analog/Mixed Signal IP, Embedded Memories and Logic Libraries, Synopsys

Join us in the Synopsys HDMI lab to see a demo of our HDMI 2.0 transmitter and receiver performance and features such as 4K video, YCbCr 4:2:0 colorimetry, and the HDCP 2.2 content protection standard.Luis Laranjeira, R&D Manager, Synopsys

FinFETs are emerging as the device technology of choice at advanced nodes. This introduces new design challenges for IP development, which require knowledge of and experience in designing with FinFETs to ensure design success. This video describes the benefits and challenges of transitioning from planar to FinFET technologies and how IP plays a significant role in this transition.Jamil Kawa, R&D Director, Synopsys