8 TYPICAL PERFORMANCE CHARACTERISTICS W Small-Signal Response Small-Signal Response Large-Signal Response V S = ±5V C L = pf A V = 5 V S = 5V C L = pf A V = 5 V S = 5V C L = pf A V = 5 672/3/4 G9 672/3/4 G2 672/3/4 G2 APPLICATIO S I FOR ATIO Start-p Characteristics Micropower op amps are sometimes not micropower during start-up, wreaking havoc on low current supplies. In the worst case, there may not be enough supply current available to take the system up to nominal voltages. Figure is a graph of LT673 supply current vs supply voltage for the three limit cases of input offset that could occur during start-up. The circuits are shown in Figure 2. One circuit creates a positive offset, forcing the output to come up saturated high. Another circuit creates a negative offset, forcing the output to come up saturated low, while the last brings up the output at half supply. In all cases, the supply current is well behaved. Supply current is highest with the output forced high, so if one amplifier is unused, it is best to force the output low or at half supply. SPPLY CRRENT PER AMPLIFIER (µa) W OTPT HIGH OTPT LOW OTPT V S / TOTAL SPPLY VOLTAGE (V) 672/3/4 FO Figure. Start-p Characteristics V V V 2k V OTPT HIGH Reverse Battery V V OTPT LOW 2k OTPT AT V S /2 Figure 2. Circuits for Start-p Characteristics 6/2/3/4 F2 The LT672/LT673/LT674 are protected against reverse battery voltages up to V. In the event a reverse battery condition occurs, the supply current is typically less than na (inputs grounded and outputs open). For typical single supply applications with ground referred loads and feedback networks, no other precautions are required. If the reverse battery condition results in a negative voltage at either the input pins or output pin, the current into the pin should be limited by an external resistor to less than ma. Inputs While the LT672/LT673/LT674 will function normally with its inputs taken above the positive supply, the common mode range does not extend beyond approximately 3mV below the negative supply at room temperature.

9 APPLICATIO S I FOR ATIO W The device will not be damaged if the inputs are taken lower than 3mV below the negative supply as long as the current out of the pin is limited to less than ma. However, the output phase is not guaranteed and the supply current will increase. Output The graph, Capacitive Load Handling, shows amplifier stability with the output biased at half supply. If the output is to be operated within about mv of the positive rail, the allowable load capacitance is less. With this output voltage, the worst case occurs at A V = 5 and light loads, where the load capacitance should be less than 5pF with a 5V supply and less than pf with a 3V supply. Rail-to-Rail Operation The simplified schematic, Figure 3, details the circuit design approach of the LT672/LT673/LT674. The amplifier topology is a three-stage design consisting of a rail-to-rail input stage, that continues to operate with the inputs above the positive rail, a folded cascode second stage that develops most of the voltage gain, and a rail-torail common emitter stage that provides the current gain. The input stage is formed by two diff amps Q-Q2 and Q3- Q6. For signals with a common mode voltage between V EE and (V CC.V), Q and Q2 are active. When the input common mode exceeds (V CC.V), Q7 turns on, diverting the current from diff amp Q-Q2 to current mirror Q-Q9. The current from Q biases on the other diff amp consisting of PNP s Q5-Q6 and NPN s Q3-Q4. Though Q5-Q6 are driven from the emitters rather than the base, the basic diff amp action is the same. When the common mode voltage is between (V CC.V) and V CC, devices Q3 and Q4 act as followers, forming a buffer between the amplifier inputs and the emitters of the Q5- Q6. If the common mode voltage is taken above V CC, Schottky diodes D and D2 reverse bias and devices Q3 and Q4 then act as diodes. The diff amp formed by Q5-Q6 operates normally, however, the input bias current increases to the emitter current of Q5-Q6, which is typically na. The graph, Input Bias Current vs Common Mode Voltage found in the Typical Performance Characteristics section, shows these transitions at three temperatures. The collector currents of the two-input pairs are combined in the second stage consisting of Q to Q6, which furnishes most of the voltage gain. Capacitor C sets the amplifier bandwidth. The output stage is configured for maximum swing by the use of common emitter output devices Q2 and Q22. Diodes D4 to D6 and current source Q5 set the output quiescent current. IN Q D D2 D3 Q3 Q4 C Q5 D7 I Q2 Q2 OT IN Q Q2 Q3 Q4 Q7 (V ).V Q6 Q7 Q9 Q5 Q6 Q Q2 D4 D5 D6 Q Q22 Q9 Q R R2 I 2 672/3/4 F3 Figure 3. Simplified Schematic 9

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