Andrew Ingraham wrote:> > > > what is the relevant frequency w of j*w*c?> > > I would guess, the main harmonic of the clock, as it is at this> frequency that you will get the most amplitude loss.> > How about the whole range of frequencies over which you have significant> signals reaching this IC?> > If you choose any one frequency, your results will only be good for that> frequency as a narrowband solution. If your circuit is wideband or> digital, the narrowband analysis won't do.> > Regards,> Andy> > **** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at

Your trying to analyze the circuit statically and it won't work. This is
not a resistive network. As poined out there is a wide frequency range
where the capacitive effects dominate. Xc the capacitive reactance will
will change the computed reflection coef. over frequency. As a first
approximation you can guess that the reflection coef. is infinite or
very large. The input capacitance of a cmos even with parasitic and all
is still in the 10's of pf range or smaller. This makes the reactance
quite large even at high frequencies like 100Mhz.

What you really need is SI tools that can easily model the interconnects
and the IC. This gives you the dynamic answer to your question. There
are plenty of good tools out there, some are cheap, some very expensive.
Check out one of these that fits your budget and needs.

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