Hi, and welcome to this part two of our training, You Can Have Both Low Noise and High Efficiency. In this section, we're going to do a deep dive into the reference design TIDA01566, which is a light load efficient low noise power supply for wearables and IoT. In this design, we're going to achieve very small size as well as very high efficiency at light loads and at full loads as well as low noise needed to power sensitive analog circuits.
Some of our design goals for this power supply are to have the smallest size so that it can fit in the wearable. As well, the height-- the profile-- is going to be important, too. We need a low quiescent current for high efficiency at light loads when the system is in standby. We also need a high full load efficiency to not affect the user from excessive temperature rise in the device. And you can think of fitness trackers and patient monitors which are worn on or in the body. You just cannot have a high hot spot in those devices.
We also need a low enough noise for powering sensitive sensors and other analog circuits. But not the lowest possible noise, such as 10 micro volts RMS or even nanovolts RMS, which requires very high bias currents, and this contradicts our low IQ need. And we want this solution to be adaptable to different output voltages, which will then support different systems, different sensors, different MCUs, different radios. Small, efficient, quiet, flexible.
This reference design is a two stage approach where a DC-DC converts the input voltage to an intermediate rail-- in this case 1.4 volts-- and then an LDO cleans up that voltage to create the desired 1.2 volts at the load. Such an LDO with a 1.4 volt input and 1.2 volt output is known as a low input low output LDO. And this is a trend we see in electronics with lower bus voltages and compressed voltage conversions to increase the efficiency of the LDO. Because the efficiency is directly proportional to the voltage difference across the LDO, a lower drop on the LDO will be a more efficient solution.
And these LDOs are also designed with lower quiescent currents to be optimized for such systems. In the conventional approach on the left, the LDO is given a higher 2.5 volt input voltage. This is because these circuits in the LDO require a minimum voltage to operate at all, and this leads to a lower drop-- 0.7 volts-- across the LDO. In addition, the higher bias current is not helping things either.
Moving to the right, we reduce the bias current and also make a low input low output LDO to convert the 1.2 volts to 1 volt. We choose to use the battery voltage-- 3.6 volts, in this case-- as the bias or power for the LDO. Therefore, the LDO does not need that voltage on its input. It can run from the 3.6 volts and convert the 1.2 volts to one volt. This leads to a 72% reduction in power loss.
Looking at the past device used in the LDO-- that's the main MOSFET that all the current goes through-- we can choose an N type or a P type. The P type-- the PMOS in MOSFETs-- is most cost effective and very simple. However, compared to an in-channel FET it requires about three times higher die area for the same RDS on, so it's a less effective transistor in the silicon.
Finally, because the gate voltage has to be below the source voltage to turn on a PMOS FET, to turn on this FET is going to limit the minimum input voltage that we can run on because the threshold voltage of most transistors is around 1.4 volts worst case. Look, using an NMOS transistor as the pass device is more effective, more efficient from our die area per an RDS on perspective, as well it reduces or eliminates the Vn dependency because the gate is controlled from a separate V bias net.
This flattens out the PSRR performance to be less dependent on the voltage converted on the end here, and using an N channel FET instead of a P channel allows us to have a wider range of output capacitors supported and a lower output impedance. However, the higher gate voltage required-- remember, we need a gate to source positive threshold voltage above 1.4 volts in this case-- will require the user to either add a V bias voltage externally or the LDO may create one with a charge bump internally. Now, the charge bump is adding noise to the output and increasing the quiescant current, so it will not be used in our system. As well, we do have the higher bias voltage with the battery.
Lets start looking at the actual references and focus in on the size and height first. This is a photo of the real PCV quite zoomed in to show the entire design, DC-DC plus LDO. Overall dimensions, if you draw a rectangle around it around 4 millimeters by 2.7 millimeters. But not all of that space is filled in with required components.
And for reference in this figure, this resistor down here-- which is not populated-- is an 0603 size, so quite large. Much larger than anything else in the circuit. The blue shaded areas are the LDO and its passives, the capacitors-- the input cap, the output cap, and the V bias cap. The red shaded areas are the DC-DC and its passes-- input cap, the output cap, the inductor, and a resistor to set the output voltage.
Those areas that are a mix between red and blue are capacitors that are shared between the LDO and the DC-DC. Because these solutions are so small, we can share the capacitors between the circuits, the input gap and the output gap. This reduces the BOM count, BOM cost, and overall solution size.
And finally, this hatched resistor down here on the bottom is to set the DC-DC's output voltage. Depending on which output voltage you need, you may be able to remove that resistor altogether. Looking at height, the inductor is the tallest component, as usual, at 0.65 millimeters tall. There are lower height options available at 0.6 millimeters and 0.55 millimeters, and those would require growing the solution size in the x and y dimensions. Next on the list, the 0201 capacitors used are 0.55 millimeters tall maximum, and then the ICs are 0.4 millimeters maximum. And overall, this occupies about 8 and 1/2 square millimeters for all the components.
Moving to the next critical parameter for this design, the no low input current, or switching IQ, is measured. The DC-DC has the lowest IQ, or switching IQ, at two and half microamps, followed by the LDO at about six, and the entire design has just over eight microamps, so no low input current. This is a very good trade-off of noise to no-load input current and lightweight efficiency, as we'll see in the following slides.
Before going further, let me ask you if the IQ matters in your application. If this particular rail is turned on and off, or if there is never a very, very light load, IQ may not be relevant. You can read my paper slyt412, IQ, what it is, what it isn't, and how to use it for more information.
The IQ affects the efficiency, but the efficiency is also affected by the RDS on of the power transistors, especially at full loads. Moving from just the LDO solution to the DC-DC plus LDO solution boosts the efficiency by 32% at heavier loads. Viewed another way, the DC-DC plus LDO solution decreases the efficiency by only 10% compared to the DC-DC only solution. So this is the trade-off for a lower noise is about a 10% efficiency hit at higher currents.
At lower currents, we have similar numbers. And finally, let me note that all this data was taken with an input voltage of 3 volts due to the LDO's input range being limited to 3.3 volts. As the input voltage increases with fully charged batteries, the LDO's efficiency will drop linearly with input voltage while the efficiency of the DC-DC and DC-DC plus LDO circuits will drop only slightly. This is very important to consider if your application in the input voltage that these circuits will be running at.
Now, the efficiency at higher loads affects the temperature rise, which can be uncomfortable for the user of a wearable. And see here we're taking worst case conditions at 300 milliamps load, but only a 3 volt input voltage. And again, your system will likely have a higher input voltage for much of the battery runtime.
The DC-DC plus LDO circuit achieves a temperature rise of under 10 degrees C-- so this will probably be not felt by the user-- while the LDO-only circuit, of course, achieves a very high temperature rise of about 40 degrees C, which will definitely affect the user. So the higher efficiency and lower power loss using the DC-DC converter on the front end equates to a lower temperature rise, which makes a better experience for the user.
Moving on from size, height, IQ, and efficiency, noise is the next parameter to tackle for this reference design. There are various types of noise. The first is output voltage ripple. That's the standard one we take with an oscilloscope in the lab. That is measuring the change in voltage due to the switching action of the DC-DC converter in the time domain.
Output voltage noise density and output voltage spurious noise are measured in the frequency domain and tell you the noise amplitude, noise magnitude at various frequencies or frequency bands. The load transient response is another time domain measurement made with the oscilloscope and reflects changes in the output voltage due to a changing load. This isn't really a noise source, but it is critical to monitor for the radios and other devices that click on and off from a light load to a heavy load very fast in the applications.
This is our first wave form of alpha voltage ripple at light loads, say a milliamp. And because we're using such small K size capacitors with very little effective capacitance, the ripple is rather high. It's about 40 millivolts on the DC-DC, but you can see that the audio cleans this up nicely to almost nothing.
This is because in power save mode, the DC-DC is switching at a very low frequency, say 14.3 kilohertz in this case, where the LDO's PSRR-- power supply ripple rejection-- is very high. This is the primary use of the LDO in these applications to clean up this low frequency power save mode ripple content from the DC-DC.
At lower loads, the operating frequency will reduce further from 14.3 kilohertz and definitely enter the audible range. However, audible noise is typically not an issue in these applications due to the overall low ripple magnitude not being high enough to excite the piezoelectric effect in ceramic capacitors as well as the very, very small K size capacitors used in these designs. And small K sized ceramic capacitors are more immune to the piezoelectric effect being triggered.
To understand exactly how the LDO takes a 40 millivolt signal and reduces it to almost nothing, we can look at the PSRR graph in the datasheet. At 1 milliamp, which is our condition, at 14.3 kilohertz we're getting about 45 dB of PSRR. With the 40 millivolts of switching ripple from the DC-DC we can apply this formula and get us down to a couple of hundred microvolts peak to peak ripple, which is barely readable on the oscilloscope.
Now, this low frequency high ripple noise content can be an issue for radio. On the left here, we have a BLE SOC, the CC2540 powered directly from a 3 volt coin cell battery with a perfect output signal spectrum. Powering the same device with our TPO62730, we get the same noise performance. This is a switching DC-DC converter with a higher switching frequency in power save mode and a lower output voltage ripple.
Powering the same radio with a different DC-DC which is non-RF friendly having a lower switching frequency and high ripple. And we see some side bands that affect the output power and noise performance of the radio. We can either use a proper DC-DC with sufficient output capacitance to get lower ripple or use an LDO to clean up the noise.
Looking at the higher loads, this is full power 300 milliamps. We see the DC-DC ripple is reduced to about 20 millivolts. The ripple is always lower in PW mode and higher currents rather than PFO mode at lower currents, and this 20 millivolts is still reduced to almost 0 by the LDO. And the switching frequency is much higher at 2.86 megahertz. So this will change the LDO's PSRR dramatically because 2.86 megahertz is outside of the LDO's bandwidth.
We confirm this on the PSRR graph, and over here on the right where the curves start increasing again is past the LDO's bandwidth. Now, there is still some PSRR here even though it's outside of the LDO's bandwidth due to the resistance of the power transistor, and the output capacitance, and parasitics on the board creating a filter. So here at 2.86 megahertz, we get about 33 dB of PSRR. Apply that to 20 millivolts and we get about a 450 microvolts ripple signal at the output of the LDO. Still very low, very clean.
Looking at the output noise in terms of frequency domain, we have the output of this noise density first. Now, this is integrating the noise over a given frequency band such as 10 hertz to 100 kilohertz to get a sum total RMS value for the noise. Over here in the low frequency region, we can see the one over F noise primarily from the band gap. And the DC-DC has a higher one over F noise, which strongly contributes to the higher noise performance figure.
The DC-DC plus LDO and LDO have the same one over F noise performance because they use the same band gap on the final stage with the LDO, and the only differences become at high frequency above 100 kilohertz where the DC-DC inverter is switching. We can see the LDO's PSRR again in effect here, reducing the noise at the higher frequencies where the switching is occurring by several orders of magnitude. Even though the DC-DC plus LDO circuit in this reference design still has some noise at this frequency this is much lower and usually not an issue.
Looking at these spurious noise of our frequency, we can see that, again, the LDO-only design is free of noise whereas the other two have these switching spurs at the switching frequency. In the red with the LDO after the DC-DC the noise is clearly reduced, and the shift in frequency between these two circuits is merely due to the slightly different switching frequency of the DC-DC at its different upper voltages. In the TIDA reference design circuit, the DC-DC is operating at a 1.4 volt output, whereas in the DC-DC standalone circuit it is operating with the 1.2 volts required by the load directly.
This is a typical wave form of load transient response from a radio switching between a standby load current of, say, 10 microamps and a transmit load current of around 50 milliamps. And this load step will cause a voltage drop in the LDO, which will also cause a voltage drop from the DC-DC. We need to control the magnitude of this voltage drop to make sure it is sufficiently small for our radio. And here before the load transient, we can see the light load ripple of the DC-DC which is, again, the rather high 40 millivolts, 10 microamps load. And you'll see that as the load current increases to 50 milliamps, we are still in power save mode but the ripple has gone down due to the higher load current.
The final design goal for this light load and efficient power supply for wearables is adaptability. How can we change the output voltage for different loads or different applications, different sensors, different MCUs, different radios? Or how can we adjust the trade off between efficiency and noise for different applications by adjusting the voltage across the LDO?
The TPS 6280 family using this design allows for 48 different output voltages selectable with a different resistor and/or different IC part number. So you can have the same circuit and just change the BOM to get a different output voltage within one of 48 set points. The TPS 7A10 family of LDOs currently contains about 11 fixed output voltage part numbers. So just pick a different part number for the LDO and you can have a different output voltage for a different system.
Summarizing the key performance metrics of TIDA01566, we can see it is the largest size but this is done to achieve a lower noise than any of the smaller circuits can achieve while achieving similar efficiency. All designs are low profile. All designs have low IQ. The lowest is just with the DC-DC by itself. Only the LDO contains a detectable high temperature rise. The TIDA circuit maintains the low noise performance of this design while keeping the efficiency reasonably high, and all designs are adaptable through different BOM part members.
Here is the overview of this design which uses the TPS62801 to create the 1/4 volt intermediate rail followed by the TPS7A1012P to down convert to 1.2 volts for the load. All the key performance criteria we just discussed are summarized here and some of the key applications are shown over here. This does give a greater than 30% efficiency boost compared to LDO only implementations while decreasing the efficiency from DC-DC only implementations by about 10%.
So going back to our design goals, this is the smallest size with a low height. This does maintain low IQ and good full load efficiency to not have a temperature rise. We do have the low enough noise to power sensors and other sensitive electronic devices, and we are adaptable to different output voltages and systems. This design meets the goals. Thank you for watching this part two of three of You Can Have Both Low Noise and High Efficiency where we discussed the deep dive of TIDA01566. 大家好，欢迎来到 我们培训的第二部分， 你可以同时拥有低噪音和高效率。 在本节中，我们将深入研究 参考设计TIDA1566， 这是一种用于可穿戴设备 和物联网的 低负载高效低噪声电源。 在这个设计中，我们将实现 非常小的尺寸 和非常高效的光负载和满载 以及低噪声所需的 电源敏感模拟电路。 我们的一些设计目标是 这种电源的最小尺寸， 使它可以适应可穿戴设备。 同样，高度--简介-- 也很重要。 当系统处于待机状态时， 我们需要一个低的静止电流， 以便在轻负荷下高效工作。 我们还需要一个高的满载效率， 以不影响用户 从过度温升的设备。 你可以想到健身追踪器 和病人监视器， 它们戴在身体上或身体里。 你不能在这些设备中 有一个高的热点。
我们还需要一个足够低的噪音 为敏感传感器 和其他模拟电路供电。 但不是最低可能的噪声， 如10微伏RMS， 甚至是纳伏RMS，这需要 非常高的偏置电流， 这与我们的低IQ需求相矛盾。 我们希望这个解决方案 能适应不同的输出电压， 这样就能支持 不同的系统，不同的传感器， 不同的MCU， 不同的无线电。 小巧、高效、安静、灵活。
这种参考设计是一种两级方法， DC-DC将输入电压转换为中间轨-- 在本例中电压1.4-- LDO清除该电压，在负载时 产生所需的1.2伏特。 这种具有1.4伏特输入 和1.2伏特输出的LDO 称为低输入低输出LDO。 这是一个趋势，我们看到 在电子与较低的总线电压 和压缩电压转换， 以提高LDO的效率。 由于效率 与整个LDO上的电压差成正比， 所以在LDO上降低电压降将 是一个更有效的解决方案。 这些LDOs还设计了 较低的静态电流， 以优化这类系统。 在左边的常规方法中， LDO的值更高，输入电压为2.5伏。 这是因为LDO中的这些电路 需要最低电压才能工作， 这就导致了更低的电压降-- 0.7伏--穿过LDO。 此外，更高的偏置电流 也没有帮助。
看看右边，我们减小了偏置电流， 也使低输入低输出的LDO 将1.2伏 转换为1伏。我们选择 使用电池电压-- 3.6伏，在这种情况下-- 作为偏置或LDO的功率。 因此，LDO不需要输入电压。 它可以运行从3.6伏 和转换1.2伏到1伏。 这将减少72%的电力损耗。
看看过去在LDO中使用的设备-- 这是所有电流通过的 主要MOSFET-- 我们可以选择N型或P型。 P型-- mosfet中的PMOS-- 是最经济、最简单的。 然而，与通道内场效应管相比， 在相同的RDS上， 它需要大约三倍高的 模具面积， 因此它是一个 硅中效率较低的晶体管。
最后，因为门极电压 必须低于源极电压 才能打开PMOS场效应管， 要打开这个场效应管 就必须限制我们 可以运行的最小输入电压 因为大多数晶体管的阈值电压 都在1.4伏特左右， 这是最坏情况。 看，使用一个NMOS晶体管 作为通过器件 是更有效的，从我们的 模具面积上更有效， 从RDS的角度来看， 它也减少或消除了Vn依赖， 因为门是由一个单独的 V偏置网络控制的。
这将使PSRR性能变平， 从而更少地依赖于 端部转换的电压， 并且使用N通道FET 而不是P通道 允许我们支持 更大范围的输出电容 和更低的输出阻抗。 然而，需要更高的门电压--记住， 我们需要一个门来源正阈值 在这种情况下高于1.4伏-- 将要求用户要么 在外部添加一个V偏置电压， 要么LDO可能在内部创建一个 带有电荷凸点的电压。 现在，电荷冲击给输出增加了噪音， 增加了静压电流， 所以它不会在我们的系统中使用。 而且，我们的电池 有更高的偏置电压。 让我们开始查看实际的引用， 首先关注大小和高度。 这是一张真实的PCV的照片， 放大显示了整个设计， DC-DC加LDO。 整体尺寸，如果你 在它周围画一个 大约4毫米乘2.7毫米的矩形。 但并不是所有的空间 都被所需的组件填满。 在这张图中作为参考， 下面这个电阻-- 它没有被填充-- 是一个0603的尺寸，非常大。 比电路中的任何东西都要大得多。 蓝色阴影区域是LDO及其无源器件， 电容--输入上限、输出上限 和V偏置上限。 红色阴影区域是DC-DC及其通道-- 输入上限、输出上线、电感器 和用于设置输出电压的电阻。 红色和蓝色混合的区域 是LDO和DC-DC之间 共享的电容器。 因为这些解是如此之小， 我们可以在电路之间共享电容， 输入间隙和输出间隙。 这减少了BOM数量、BOM成本 和整个解决方案的大小。
最后，下面这个阴影电阻 是用来设置DC-DC的输出电压的。 根据您需要的输出电压， 您可以完全移除该电阻。 从高度上看，电感器 是最高的元件， 和往常一样，0.65毫米高。 有较低的高度选项在0.6毫米 和0.55毫米，这需要 在x和y维度上 增加解决方案的大小。 接下来，使用的0201电容器的 最大高度为0.55毫米，其次是 集成电路的最大高度为0.4毫米。 总的来说，对于所有的部件， 它占据了8和12平方毫米。 进入下一个关键参数， 针对该设计， 没有低输入电流， 或切换IQ，进行测量。 DC-DC的IQ最低， 或者说切换IQ最低， 为2.5微安，其次是LDO， 约为6微安，整个设计 只有8微安多一点， 所以没有低输入电流。 这是一种很好的平衡噪声 与空载输入电流 和轻量级效率的方法， 我们将在下面的幻灯片中看到。
在进一步讨论之前， 让我来问问您， IQ是否在您的应用程序中。 如果这个特定的轨道 是打开和关闭的， 或者从来没有一个非常， 非常轻的负载， IQ可能不想关。 你可以阅读 我的论文slyt412， IQ， 它是什么，它不是什么， 以及如何使用它 来获得更多的信息。
IQ影响效率，但效率 也受到功率晶体管的RDS的影响， 尤其是在满载时。 从LDO解决方案 转移到DC-DC + LDO解决方案 可以在较重的负载下 提高32%的效率。 从另一个角度来看， DC-DC + LDO方案的效率 仅比DC-DC方案低10%。 所以这就是低噪音的代价 在更高的电流下 大约有10%的效率。
在较低的电流下， 我们有相似的数值。 最后，我要指出的是 所有这些数据都是在 输入电压为3伏特的情况下得到的 因为LDO的输入范围 被限制在3.3伏特。 当充满电的电池的 输入电压增加时， LDO的效率会随 输入电压线性下降， 而DC-DC 和DC-DC+LDO电路的效率 只会略有下降。 这是非常重要的考虑， 如果您的应用程序 在这些电路 将运行的电压输入中。 现在，更高负载下的效率 会影响温升， 这对穿戴式设备的用户来说 是不舒服的。 这里我们考虑的是最坏的情况 300毫安的负载，但只有 3伏的输入电压。 同样，你的系统 在大部分电池运行时 可能会有更高的输入电压。
DC-DC + LDO电路 实现了10℃以下的温升-- 所以这可能不会被用户感觉到-- 而单一LDO电路，当然， 达到了一个非常高的温升 约40摄氏度， 这肯定会影响用户。 因此，在前端使用DC-DC变换器， 效率更高，功耗更低， 就等于温升更低， 这给用户带来更好的体验。
从尺寸、身高、IQ和效率开始， 噪音是这个参考设计 要处理的下一个参数。 有各种各样的噪音。 首先是输出电压纹波。 这是我们实验室里 用示波器测量的 标准仪器。 它是测量由于DC-DC变换器 在频域的开关动作 而引起的电压变化。
输出电压噪声密度 和输出电压杂散噪声 在频域内进行测量， 并告诉你各种频率或频段的 噪声幅值、或噪声幅度。 负载瞬态响应 是用示波器进行的另一种时域测量， 它反映了由于负载变化 而引起的输出电压的变化。 这并不是一个真正的噪声源， 但对于无线电 和其他设备的监控是至关重要的， 这些设备在应用中 可以非常快速地 从轻负荷切换到重负荷。 这是我们的第一波a电压纹波 以光负载的形式出现， 比如说毫安。 因为我们用的是 K大小的电容， 有效电容很小， 所以纹波很大。 它在DC-DC上大约是40毫伏， 但是你可以看到音频很好地 把这个清除到几乎没有。
这是因为在节电模式下， DC-DC开关的频率非常低， 在本例中，假设为14.3千赫兹， LDO的PSRR(电源纹波抑制) 非常高。 这是这些应用程序中 LDO的主要用途， 用于清除DC-DC中的 这种低频省电模式波纹内容。
在较低的负载下，工作频率 将进一步降低。 将进一步降低， 从14.3千赫兹， 并绝对进入可听到的范围。 然而，在这些应用中， 可听到的噪声 通常不是一个问题， 因为整体的低纹波幅度 不够高，不足以激发 陶瓷电容器中的 压电效应，以及 在这些设计中使用的 非常非常小的K尺寸电容器。 小型K型陶瓷电容器 对触发的压电效应 具有较强的免疫力。
为了准确地理解LDO 是如何接收40毫伏信号 并将其减少到几乎为零的， 我们可以查看数据表中的 PSRR图。 在1毫安，这是我们的条件， 在14.3千赫兹， 我们得到大约45分贝的PSRR。 在DC-DC的开关纹波 为40毫伏的情况下， 我们可以应用这个公式， 使我们得到 几百毫伏的 峰值到峰值的纹波， 这在示波器上 几乎无法读取。
现在，这种低频高纹波噪声含量 可能成为无线电的一个问题。 在左边，我们有一个BLE SOC， CC2540直接从一个 3伏电压硬币电池供电， 具有完美的输出信号频谱。 用我们的TPO62730 驱动相同的设备， 我们得到了相同的噪声性能。 这是一种调节DC-DC变换器， 具有较高的开关频率， 在省电模式 和较低的输出电压纹波。
使用不同的DC-DC 为同一台收音机供电， 这是非射频友好的，具有较低的 开关频率和高纹波。 我们看到一些边带 会影响收音机的 输出功率和噪声性能。 我们可以使用适当的DC-DC 与足够的输出电容， 以获得较低的纹波 或使用LDO清理噪声。 来看看更高的负载， 这是300毫安的全功率。 我们看到DC-DC纹波 减小到大约20毫伏。 在PW模式下，纹波总是较低， 而在低电流下，纹波总是 比PFO模式下的纹波大， 这20毫伏仍然被LDO降低到0。 开关频率要高得多， 在2.86兆赫。 这将极大地改变LDO的PSRR， 因为2.86兆赫 不在LDO的带宽之内。
我们在PSRR图上 确认了这一点， 在右边这里曲线 开始再次增加的地方 超过了LDO的带宽。 现在，这里仍然有一些PSRR， 尽管它超出了LDO的带宽， 因为功率晶体管的电阻， 输出电容，和寄生在板上的 滤波器。 所以在2.86兆赫，我们得到 大约33分贝的PSRR。 将其应用于20毫伏， 我们得到了450毫伏的 纹波信号 在LDO的输出端。 还是很低，很干净。
从频域的角度来看输出噪声， 我们先得到这个 噪声密度的输出。 现在，这是在给定的频带上 对噪声进行整合， 比如10赫兹到100千赫兹， 得到噪声的总RMS值。 在这里的低频区域， 我们可以看到1/F噪声 主要来自于带隙。 而DC-DC具有高于F的噪声， 这是其具有较高噪声性能的 重要原因。
DC-DC加LDO和LDO 具有相同的 1/F噪声性能，因为它们 在最后阶段 使用了与LDO相同的带隙， 唯一的区别是 当DC-DC逆变器开关时， 频率超过100千赫兹。 我们可以看到 LDO的PSRR在这里 再次发挥作用， 在开关发生几个数量级的 高频率处降低了噪声。 即使这个参考设计中的 DC-DC + LDO电路 在这个频率上仍然有一些噪声， 但这个频率要低得多， 通常不是一个问题。
看看我们频率的这些杂散噪声， 我们可以看到，同样的， LDO专用设计 是没有噪声的，而其他两个 在开关频率有这些切换杂散。 红色的是DC-DC之后的LDO， 噪声明显降低， 这两个电路之间的频率偏移 仅仅是由于DC-DC 在不同的上电压下的 开关频率略有不同。 在TIDA基准设计电路中， DC-DC的工作电压为1.4伏， 而在DC-DC单机电路中， 它的工作电压为 负载所需的1.2伏。
这是一种典型的 负载瞬态响应波形， 来自于备用负载电流， (如10微安培) 和传输负载电流(约50毫安) 之间的无线电切换。 这个负载步骤 会导致LDO中的 电压下降，这也会导致 DC-DC中的电压下降。 我们需要控制电压降的大小， 以确保它足够小， 对于我们的无线电。 在负载暂态之前， 我们可以看到 DC-DC的轻负载脉动， 也就是非常高的40毫伏， 10微安培负载。 你会看到，当负载电流 增加到50毫安时，我们仍然 处于省电模式， 但是由于负载电流增加， 波纹已经减小了。
这种轻负荷高效的 可穿戴设备电源的 最终设计目标是适应性。 我们如何改变输出电压 来适应不同的负载 或是不同的应用， 不同的传感器， 不同的MCU， 不同的无线电？ 或者我们如何通过 调整LDO上的电压 来调整不同应用的效率 和噪音之间的平衡？
采用这种设计的TPS 6280系列 允许使用48种不同的电阻 和/或不同的IC部件号 选择不同的输出电压。 所以你可以有相同的电路， 只是改变BOM得到不同的输出电压 在48个设定点之一。 TPS 7A10系列的LDOs目前 包含大约11个固定的 输出电压部件号。 所以只要为LDO 选择一个不同的零件号 你就可以为不同的系统 选择不同的输出电压。
总结TIDA01566的 关键性能指标， 我们可以看到它是最大的尺寸， 但这样做是为了获得 比任何较小的电路 所能达到的噪音更低， 同时达到类似的效率。 同时达到类似的效率。 所有的设计都是低调的。 所有的设计都有低IQ。 最低的是DC-DC本身。 只有LDO含有可检测到的 高温上升。 TIDA电路保持了本设计的 低噪声性能，同时保持了 较高的效率， 所有的设计都可以通过 不同的BOM部件进行调整。
以下是本设计的概述， 它使用TPS62801 创建了1/4伏的中间轨道， 然后TPS7A1012P向下转换为 1.2伏的负载。 我们刚才讨论的 所有关键性能标准 都总结在这里， 一些关键的应用程序 在这里显示。 与只使用LDO实现相比， 这确实提高了 30%以上的效率， 同时将只使用DC-DC实现的效率 降低了约10%。
回到我们的设计目标， 这是最小的尺寸和较低的高度。 这确实保持低IQ 和良好的满载效率， 没有温度上升。 我们确实有足够低的 噪音功率传感器 和其他敏感的电子设备， 我们可以适应不同的 输出电压和系统。 这个设计达到了目标。 感谢大家观看第二部分， 在我们讨论 TIDA01566深潜的地方， 你们三个人都可以 有低噪音和高效率。

Description

March 26, 2019

Understand the performance and tradeoffs of the traditional low noise and high efficiency approach of using a DC/DC followed by an LDO, through a deep dive into TIDA-01566. The size, quiescent current, efficiency, temperature rise, noise, and adaptability of three different approaches are compared: DC/DC + LDO, DC/DC only, and LDO only.