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Archive for June, 2016

At this writing, midnight is approaching here in California, it’s June 23rd, and highly anticipated news is arriving out of the UK. It’s Friday morning there and the results of the Should I stay or Should I go referendum have been announced. To the astonishment of some subset of the world, and undoubtedly their stock markets, the UK is leaving the European Union.

And so a page turns, another chapter begins, and now there’s a twist in the plot line that few saw coming. Although it’s a dark and starry night here, the sun is up in the UK and the future looks suddenly different, no matter if you’re standing on the streets of London, York, Edinburgh – or Cambridge.

Menta is a French startup, founded in 2007, that provides embedded FPGA IP for SoCs, ASICs and ASSPs. The company exhibited last week at the Design Automation Conference in Austin and will exhibit next week at the TSMC Technology Workshop in Herzliya.

This month is clearly a busy one for Menta, and for more reasons than just exhibiting in conference venues 7000 miles apart. On June 6th, the company announced its “next generation of embedded programmable logic IP cores for SoCs.”

When SRC’s Bill Joyner took the podium this past Sunday evening at the 53rd DAC in Austin, he did something that’s never been done before: Present a panel about careers that wasn’t part of a Workshop for Women in EDA.

Up until 7 o’clock on June 5, 2016, a conversation about career perspectives was such a non-technical topic, it could only be found in Marie Pistilli’s beloved workshop, a venue where work/life balance, Academia vs. Industry, and how to promote your brand within the organization were thoroughly discussed every year for 15 years at DAC.

Now IEEE’s Council on EDA, CEDA, has made the bold decision to pick up where Marie’s workshop left off, sponsoring this week’s event and broadening the audience and the appeal.

Joyner had four people on his panel, a generous two hours to hash out various universal questions, and enough of a sense of humor to offer to wear the necktie he’d brought with him to add gravitas, or not to wear the tie to appear hipster and cool. He quickly decided to go without the tie, and the ensuing conversation went something like this.

The first thing to do on Wednesday at DAC 2016 in Austin is take in an hour of the Exhibit Hall. This is the last day for the booths, people are zippy in the morning like horses sensing the stable at the end of their journey, and conversations on the floor are still about the technology. By the end of the afternoon, it’ll be about wistful goodbyes and, “Will we even be here next year when DAC again returns to the Lone Star State?”

Then from 10:30 to noon genuflect to Academia and check out ‘Accelerated Simulation for Circuit Reliability and Stability’. With speakers from Texas A&M, USC, Brown, and Michigan Tech. If you attend, you’ll learn what the future holds for simulation: power supply stability, soft error in logic circuits, thermal noise in ultra-low voltage designs, and the sparsification of spectral graphs used in various design problems. Nobody from industry is speaking, so if you want to get in on the ground floor commercializing some of this stuff, sit in the front row.