Meta

Posts Tagged ‘Synopsys’

Synopsys has a problem. Per Norm Kelly, speaking at the ESD Alliance panel on September 14th in Silicon Valley, Synopsys loses fully a third of the revenue they’re owed each year for their vast catalog of IP because it’s stolen by Cheaters and used without paying any licensing or royalty fees.

Kelly said Synopsys earns about $200 million per year selling IP, and loses another $100 million to theft. Cheaters are a real problem, he lamented, and as Director of License Compliance for Synopsys he should know. Kelly did not have the floor to share these laments, however, until Warren Savage, GM of IP at Silvaco, opened the meeting.

Speaking from the podium as moderator of the evening’s discussion, Savage said the real problem is the bumblers, those designers and companies who lose track of licensing obligations for IP that was either purchased some time ago, or was brought into the design effort on a data stick fished out of the pocket of someone who’s joined the organization through a poorly managed M&A.

In other words, when Chuckles the Clown uses IP, often as not he doesn’t realize some monies are owed to the third-party IP vendor who created it in the first place. Savage offered this statistic: On an average SoC today, there are 150 to 200 blocks of IP, but only a small percentage of those blocks are actually paid for.

IP will be well represented at DAC according to Adapt IP Michael “Mac” McNamara, and he should know. He’s helped build the IP Track at the show and is concerned that everyone understand the IP-related content in Austin this year will be deep and wide.

Mac and I spoke by phone recently. He’d read a blog a posted here in April expressing skepticism about IP coverage at DAC. Therein, I suggested the content set for Austin in June was inadequate, given the important role IP plays in chip design today.

A thoughtful McNamara wanted to respond to this critique; he wanted to evangelize for the quality of the content at DAC – particularly as he is Vice Chair of the conference this year and will be General Chair in 2017. [Cadence’s Chuck Alpert is General Chair here in 2016.]

“This tool is definitely needed by designers,” Dave said, “and is motivated by the increasing use of FinFET devices. Here at Synopsys we have 1300 engineers in our IP team, with lots of these people turning to FinFETs in their design.”

Not an easy transition, he noted: “A single transistor exists in a planer mode, but it becomes a much more complex device in a FinFET. The layout becomes more complex, and so does the approach to design.”

There have been some developments with respect to custom design, Dave acknowledged: “Most recently, you could actually automate your layout with constraints. However, typing in those constraints is so time-consuming.

“With Custom Compiler, we have moved instead to a visually constrained layout, which allows you to re-apply what you’ve already done – both to your current work and to your future work as well.

The folks at DVCon have done a brilliant thing. They’ve invited Lauro Rizzatti to present at their upcoming conference on a topic that Rizzatti knows better than anybody, emulation. Last year alone, he wrote 40 articles on the subject.

More importantly, of course, Rizzatti helped guide EVE, the high-flying European EDA company that led the field in emulation from their base in France before being acquired by Synopsys in 2012. I spoke with Rizzatti this week about emulation, his talk at DVCon, and his recent endeavors writing about a technology that’s taking the world of verification by storm.

He started by establishing the importance of emulation today: “This technology is here to stay. It’s been around for 30 years, and [historically] was something only the big companies could afford to buy and use. They needed an army of engineers. Today it’s no longer a niche technology, however; it’s mainstream.”

This week Synopsys announced “unauthorized third-party access to Synopsys EDA, IP and optical products and product license files through its customer-facing license and product delivery system. The unauthorized access, which began in July 2015, was discovered by Synopsys in October 2015.”

The fact that the company needs to make this announcement is indicative of a new attitude towards an old problem: Software companies who lose their products to theft and piracy no longer want to just buck up and get past it, particularly in EDA. Instead, they want tools and strategies to go after their adversaries. The newly launched startup SmartFlow Compliance Solutions, just announced last week, is planning to offer such tools.

Launched by Ted Miracco – one of the founders of EDA vendor AWR Corp. – SmartFlow is based on his experience dealing with pirated AWR product software, including tracking down and forcing restitution from companies who were proven culpable. In a phone call last week discussing his new company, Miracco said pirated software is more than just an occasional nuisance, it’s resulting in billions of dollars in lost revenue to the companies whose products are being used without licenses.

More profound than lost profits, however, is the ’tilting’ of the playing field. When companies who use pirated software to design chips or systems are able to undercut their competition by underpaying for the tools they need, or by not paying at all, the competition is hobbled.

In response, SmartFlow has engineered a complex set of tools and protocols that will allow companies to unearth pirated instantiations of their software across a variety of customer profiles. To begin their effort to build those tools, Miracco and his team looked closely at software non-compliance around the globe, parsed the different types of pirates and examined their principal strategies.

ARM must be doing something right when among the eight corporate sponsors for their upcoming Silicon Valley users conference in November, the top three companies in EDA are listed as Diamond or Platinum.

Cadence is Diamond, undoubtedly, because company President & CEO Lip-Bu Tan is co-chair of EDAC, and ARM CEO Simon Segars is on the EDAC Board. But why would Mentor and Synposys spend good money being Platinum sponsors of ARM’s show when they could put that particular chunk of disposable income into their own user conferences, or even DAC? Particularly since Mentor and Synopsys sell IP, as does Cadence, so in some ways the three EDA companies may actually be competing with ARM.

There are three possible answers: A) Mentor, Synopsys, and Cadence serve as channels for ARM products. B) Mentor, Synopsys, and Cadence want to see, and be seen by, ARM’s enormous worldwide customer base. C) ARM has the winning hand in today’s semiconductor supply chain, so either the Big Three in EDA pony up to help sponsor ARM TechCon, or the UK-based IP behemoth won’t cooperate in the EDA world; they won’t offer pointers or tool-development advice for the third-party design software that EDA vendors sell and ARM customers [might] buy.

Autumn used to start in September, but now classes and conferences commence in August and vacation ends just that much sooner. Here’s a list of various events you should consider attending between now and the end of the year, with thanks to conference organizers for the associated descriptions.

Scanning the range of topics, it’s clear the combined IP and EDA industries have an increasingly broad range of interests: IoT, autos, wearables, software security, verifying/integrating IP, power, device physics, memory, embedded processors and software, sensors, MEMS, a range of standards, networking, both the professional and technical kinds, and “synergistic collaborative design” both up in the cloud and down below on solid ground.

Early Monday morning, Synopsys announced several new bits have been added to their impressive bucket of IP blocks, a new family of DesignWare processors targeted at vision applications. With an honorable pedigree – descent from the ARC technology that came to Synopsys via the 2010 acquisition of Virage Logic – the processors announced on March 30th are designed to be embedded in SoCs, specifically to meet a growing need to digitally “distinguish smiles from frowns, faces from cars, baby carriages from trees or dogs, and even sky from ground.”

These needs were articulated in a March 26th phone call with Synopsys Senior Manager of Product Marketing Mike Thompson, who enthusiastically explained, “The vision market will grow dramatically over the next several years. The next 10-to-15 years will be seen as a paradigm-shift period in how we interact with technology.”

That’s why he’s delighted Synopsys will surpass other players in driving that shift: “There are already a few vision processors available [on the market], and they are largely programmable. We took a slightly different approach, however, with the new DesignWare EV Processors we’ve developed.

We’re only gifted with so many hours of life here on earth, so why would anyone waste them listening to the same lengthy keynote twice in one month? That was the thought that raced through my mind when Synopsys’ Aart de Geus stepped up onto the stage in front of 500+ SNUG attendees at the Santa Clara Convention Center yesterday morning and clicked on his title foil.

“Shift Left,” it said.

“Oh no,” I said. For pity’s sake, this was the exact same talk co-CEO de Geus offered up less than three weeks ago on March 3rd at DVCon in San Jose. I looked around for the nearest exit.

Then, cooler heads prevailed. Mine.

Wait a minute, I said. Three weeks ago I sat in the back of a ballroom at the DoubleTree, listening over the heads of 350 people at DVCon, and typed everything the good doctor said into my tablet, verbatim. I’ve already done the heavy lifting here, I thought. I’ve got his script on my tablet, I’ve seen the slides, and I’ve heard the jokes.

Does Synopsys believe an entirely different audience attends DVCon than that which attends SNUG? Why else would they present the exact same talk at the two venues? Perhaps no one at SNUG actually does verification? Why not compare the SNUG talk to the one at DVCon?

So, with that much entertainment guaranteed I sat back and enjoyed the show.

DVCon is coming up in early March in San Jose and if you’re into IP, you should be there. That was the surprising take-away I stumbled upon this week while interviewing DVCon General Chair Yatin Trivedi and Technical Program Chair Ambar Sarkar. As many of you know, Yatin is Director of Standards and Interoperability Programs at Synopsys and Ambar is Chief Verification Technologist at Paradigm Works, both men throwing long shadows in the deeply technical world of design and verification.

Our interview was taped on the sound stage in the glam new Synopsys building on Middlefield in Mountain View. Yatin works in the just-opened building, but Ambar flew in from his offices in Andover, Massachusetts, for our chat and was lucky enough to get out of Boston before Juno blew in and shut down all flights out of New England.

The three of us sat on director chairs on Monday morning and chatted on film for well over 30 minutes. Pretty darn fun, but also pretty darn informative. Who knew that Yatin and Ambar were so interested in IP, and we’re not just talking here about Verification IP. When I mentioned I’d seen that IP was one of the topic areas set to be showcased at the upcoming DVCon in March, Yatin launched into an enthusiastic endorsement of all things IP.