DESIGN, MANUFACTURABILITY AND COST CONSIDERATIONS FOR BASEBAND AND MEMORY STACKED DIE SYSTEM IN PACKAGE SOLUTIONS

Abstract: The use of large blocks of embedded memory on base band processors has been constrained by long design cycles, low fabrication yields and high costs associated with larger die sizes and extra wafer processing steps. In an effort to obtain a faster time to market, many consumer products companies are considering the combination of multiple semiconductor devices in one package. Since package size is a major factor in the wireless market, the optimal space saving solution for the packaging of these devices is stacking them in a vertical assembly. The assembly of multiple memory devices within a single package has been in production for several years at most major assembly contractors.

This packaging technique has not presented a large number of challenges due to the memory dies having similar geometries, low pin counts, and functional requirements being similar. This report will discuss multiple challenges associated with combining high pin count semiconductor devices in a single package, specifically one base band ASIC processor with one or more memory devices. In addition, this paper will focus on four key multi-die packaging feasibility areas including early design, manufacturing, and cost considerations. It will also discuss future trends.

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