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SPRING 2013
CSEE E6861: COMPUTER-AIDED DESIGN OF DIGITAL SYSTEMS
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Instructor: Prof. Steven Nowick
Class Time: Thursday, 4:10-6:00pm
Place: TBA
Credits: 3 points
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PREREQUISITES:
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(i) one semester of basic digital logic
(CSEE4823, CSEE3827 [if you are solid on the digital
logic material], or another course equivalent,
or permission of the instructor)
(ii) some basic course in data structures and algorithms
(CS 3133/3134/3137/3139, or 3157, or the equivalent).
You *must* have familiarity with programming and basic data structures
NOTE: *NO VLSI or EE circuits background is required!*
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COURSE DESCRIPTION:
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An introduction to modern CAD tools and algorithms for the design of
digital systems. The course is a nice blend of three areas:
(i) digital design, (ii) optimization algorithms, and (iii) software tools
and applications. It is suitable for students with a range of interests:
from those more interested in applied theory and algorithms, to those more
interested in digital design and optimization.
The course systematically covers the various automated synthesis steps
used in modern CAD tools: starting from a high-level specification of
an entire digital system down to optimized low-level digital hardware,
and considering "design-space tradeoffs" under user-specified cost
targets. Many of the techniques presented have been incorporated into
state-of-the-art commercial tools.
These techniques will be applied to optimize circuits and systems
for a variety of key cost functions (power, delay, area, throughput),
at a variety of levels in the design flow (register-transfer level
[high-level structural view of complex sequential subsystems],
controllers, combinational 'netlists' [gate-level interconnection],
technology mapped implementations [interconnection of VLSI cells]).
One of the key themes of the course is handling
large complex designs (entire subsystems or combinational blocks
with 1000's or tens of thousands of gates) with very efficient and
powerful automated techniques. You will be learning and using a
variety of heuristic and exact optimization techniques, including:
dynamic programming, iterative improvement, hill climbing, unate
and binate covering, greedy algorithms, and physics-based modelling
(e.g. force-directed scheduling).
When you have completed the course, you will have a good handle
on modern research aspects of digital CAD (i.e., the underlying
optimization algorithms used to automatically design systems), as
well as gain some practical hands-on experience in using existing
CAD packages.
The course will include assignments that involve programming, as
well as use of CAD tools. You should have at least a solid basic
background in programming for this course, though you do not need
to be a highly-fluent programmer. If you have questions about your
background, feel free to contact me by email (nowick@cs.columbia.edu)
or set up an appointment.
NOTE: This is *not* primarily a project/lab course; while you will
use real CAD tools, the focus will be on the optimization algorithms and
digital design techniques behind them. Also, you do *not* need to
be an experienced digital designer to take this course: you should
simply have a basic background in digital logic.
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SYLLABUS:
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Introduction to modern digital CAD synthesis and optimization techniques.
Topics include:
- modern system-level design and optimization (high-level synthesis):
register-transfer level (RTL) modeling; optimal scheduling: area-oriented
vs. latency-oriented approaches, list-based and force-directed
scheduling (FDS) methods; optimal resource sharing (i.e. reusing function units,
registers): lifetime analysis, def-use chains.
- sequential logic optimization: retiming
optimizing area and clock cycle time by repositioning registers.
Leiserson/Saxe's method.
- combinational logic optimization:
advanced techniques for exact and heuristic two-level logic minimization
(espresso, mincov); state-of-art techniques for large-scale multi-level
logic optimization: basic transforms (collapse, extraction, substitution,
simplify, decomposition), logic optimization scripts, advanced Boolean
optimizations (exploiting don't-cares with ODC's/CDC's), iterative improvement
using redundancy addition and removal; combining optimization targets of
cycle time and area/power;
- technology mapping:
optimal binding of gates to VLSI cell layouts in a commercial "library";
optimizing for delay, power and area; load-independent vs.
load-dependent delay models; approximating capacitive loads; recent
techniques targeted to FPGA's.
- physical design basics:
overview of mapping large-scale circuits to optimized VLSI layout level;
circuit partitioning: Kernighan-Lin method;
place-and-route: problem overview, introduction to simulated annealing.
- other advanced techniques:
verifying equivalence of large combinational circuits
and FSM's; advanced compact Boolean data structures (ordered binary
decision diagrams [OBDD's]); SAT solvers and their applications;
static timing analysis; low-power design; and synthesis-for-testability.
Includes written and hands-on assignments using and creating CAD tools.
A project is included, involving software development of a sophisticated
CAD tool.
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REQUIRED TEXTBOOK:
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Giovanni De Micheli, "Synthesis and Optimization of Digital
Circuits", McGraw-Hill (1994).
[NOTE: currently out of print, but it can be purchased online,
in new, used and international editions.]
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OTHER READING:
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A number of research and industrial articles will be provided
as supplemental material.
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URL:
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http://www.cs.columbia.edu/~cs6861
(under construction for Spring-13)
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