3D TSV: Ready for Manufacturing?

3D
TSV: Ready for Manufacturing?

By Yann Guillou, SEMI
Europe

In 2012, 3D TSV is one of the hottest technologies, along with
450mm and EUV, in the semiconductor industry due to the technology’s huge
potential. Depending on the type of application and timeframe, gains in
bandwidth, power reduction, thermal budget, footprint, height, cost and even “time
to market” and product portfolio scalability might be expected. In the last five
years, major progress has been made. Driven by the application requirements, the
technology scope is narrowing and technology options are being eliminated. A few applications — including Camera Image
Sensors (CIS), power amplifiers, memory stacks, memory and logic stacks with a
wide and parallel bus interface, and side-by-side integration on a 2.5D
interposer—
emerged as the drivers. Standards defined through a pre competitive
consensus-based agreement have been created by Standard Developing Organizations
such as SEMI and Jedec. SEMI recently published SEMI 3D1-0912 - Terminology for
Through Silicon via Geometrical Metrology, an important starting point in
the move forward volume production. In addition, the recent Yole Developpement
report “Equipment and Materials for 3DIC & Wafer Level Packaging,” forecasts a material market growth from $590
million in 2012 to over $2 billion in 2017 with a 24 percent CAGR. On the
Equipment side, the market reached $870 million in 2011 with 28 percent CAGR, still
mainly driven by 3D-IC and TSV Interconnect.

Europe: Important Role
in 3D TSV Technology

European companies continue to be at the forefront of 3D TSV
technology. R&D organizations such as CEA-LETI, Fraunhofer-IZM and imec are
among the pioneers to develop state-of-the-art technology to their global
partners. On the IDM and foundry side, STMicroelectronics was one of the first
companies worldwide to manufacture CIS with via last. Starting with 200mm
wafers with a backside via and a conformal copper filling, they quickly evolved
to 300mm wafers. Similarly, ams AG industrialized a highly innovative TSV
architecture for a demanding medical image sensor solution. These products
could be manufactured because the appropriate toolset was available. In effect,
equipment and materials suppliers achieved important developments in the last few
years; much progress has been made in via etching, isolation and filling, carrier
temporary bonding/debonding, wafer backside processing, fine pitch bumping and
die stacking. European leaders such as BESI, EV Group, Oerlikon, Suss MicroTec and
SPTS are among the players that invested
significant R&D efforts to make this happen. Still, on the road toward high-volume
manufacturing, some key challenges remain.

On October 11 during SEMICON Europa 2012, Georg Kimmich from
ST-Ericsson reviewed their progress on wide I/O application processors, stating
that ST-Ericsson achieved a wide I/O demonstrator product with advanced CMOS
technology using via middle type of TSV and Jedec JC42.6 compliant memory
interface. However, Kimmich explained that low power wide I/O processors with
TSV technology are not currently available on the market and why their introduction
was postponed.

Kimmich noted that the reasons are not just technical but
linked to a set of different parameters:

Business model: A new and complex business model
that needs to be defined and agreed upon between partners.

Memory evolution: Bandwidth performance of
LPDDR3 in a PoP configuration reached an acceptable performance level at better
cost. In addition, new memory hierarchy architecture improvement requiring less
bandwidth than initially planned was made possible.

Thermal constraints: Thermal constraints of wide
I/O, due to tight thermal coupling between the processor and the memory die.

However, Kimmich insisted that wide I/O was not a bad idea and
that it helps clear the path for technologists to develop the elementary
enabling technology “bricks” required for future use in mobile products. He also
shared some insights about new smart chipset partitioning that ST-Ericsson is
investigating.

New SEMI Event to
Convene 3D TSV Leaders

To solve the remaining technical and business challenges
that require coordination and cooperation along the supply chain, SEMI is launching
a new event to foster a comprehensive analysis of “pain points” with top notch
speakers. All the companies and organizations mentioned above will present
their latest achievements at a new SEMI event called the European 3D TSV Summit in
Grenoble in January 22-23, 2013. At this global event, which will have a strong
focus on the manufacturing aspect of 3D TSV technology, the speakers will share
their latest company achievements and perspectives. The event will as well
feature international leaders from the U.S. and Asia such as Xilinx, Amkor and
many more. A broad and deep market overview of 2.5D interposer, 3D-IC and TSV
Interconnects will be covered, coordinated by Yole Developpement that will
manage a unique market briefing session.

Collective Progress

As 3D TSV technology is now close to volume production, the various
stakeholders need to make sure all aspects are covered: design tools and
methodology, test solutions from the design and equipment aspect, and inspection
and metrology tools developed and evaluated by the customers.

Nevertheless, some technical and business-oriented challenges
still remain and need to be collectively tackled. To address them and progress,
in addition to the regular plenary talks, the European 3D TSV Summit will allow
attendees to interact via a software platform — allowing them to schedule
meetings with each other in advance.