Power Reductions by Controlling the Clock with Clustering Technique

In VLSI circuits, peak power and RMS current reduction are the challenging tasks. Both power density and peak power are proportional to each other. If these parameters are reduced, it may lead to a timing violation and logic failures. In order to overcome these failures, Clock Control Strategy based Clustering Method (CCSCM) is proposed. In the proposed clustering method, the authors design to reduce the path delays, to find the inequality paths and to make it equality through a slack values using slack variables.