The Power Blues

When it comes to power in SoC designs, most engineers will agree that the easy stuff is already done. What’s interesting, though, is they’ve been saying that for several process nodes, and the complaint has been roughly the same no matter what node they’re actually working at. It’s as true today for engineers working at 180nm with analog chips as at 28nm with the latest digital process technology. And it’s one of the biggest concerns among those working at 20nm and beyond.

The reality is that everyone is now thinking about power, and they’re coming to the realization that they need to deal with it sooner rather than later—meaning further up in the flow rather than at the back-end of designs. But no matter where design engineers are on the Moore’s Law road map, power affects everyone and everything—and there is no single solution at any node.

Current consensus is that most of the chip needs to be in the “off” state or seriously powered down most of the time any device is turned on. Beyond that, however, there are myriad choices to make up front, and all of them become far more important as we move into 2.5D stacked die connected with transposers and 3D stacks connected with through-silicon vias. (There probably will be a 2.75D stack, as well, which will be the first mass adoption of TSVs without stacked logic.)

There are a number of approaches being taken that will become almost universal over the next couple of years. One involves power islands, which isn’t exactly new. What is new is that most designers have never really worked with them. While the communications chip vendors have been wrestling with power islands since 45nm, most digital designers are just getting to that node. When they do, getting power models correct at the front end can save an enormous amount of pain at the verification and yield stages. But the learning curve, particularly at the verification stage, is like scaling a cliff.

A second approach involves new materials, which have been talked about for the better part of a decade. For high-performance chips, silicon-on-insulator has been popular since 45nm. That technology will likely grow even more popular as standard CMOS begins to give out at 20nm and beyond, particularly with full-depleted SoI. This material makes it far easier to shrink geometrieswhile dealing with issues such as electromagnetic interference, electrostatic discharge and electromagnetic compatibility.

A third technique is to lower the voltage across the chip, which is a lot harder than it sounds. Not all components can operate at lower voltages, and not all IP was designed to work at those voltages. That means the number of voltage islands increases dramatically, again raising verification issues as well as signal integrity issues and timing closure problems.
Fourth, the quest for better connectivity has added a slew of new standards that devices need to support, and all of them take additional power. For example, a device that needs to connect to WiFi, LTE and various baseband frequencies uses power just searching for signals, which is why a phone battery lasts longer in strong signal areas than in places where signals are weak. There is no simple solution for this problem, and connectivity issues will likely get worse before they get better because of the number of devices that will be connected to the Internet over the next decade.

And finally, there are software engineering issues that need to be dealt with more from an energy standpoint than a functionality standpoint. Software that is inefficient can use up a lot of energy, both in terms of the processor cores that are on and in terms of the number of cycles needed for a particular process. Just throwing cores at a problem doesn’t make it better, and frequently it makes it worse because those cores don’t actually add efficiency or even performance.

None of these approaches alone will make batteries last longer or devices run cooler. Taken together they can have an effect, but only if these kinds of issues are dealt with across an increasingly disaggregated ecosystem. Lowering power is no longer just an issue for the makers of communications chips and advanced processors. It’s now a universal issue, and one that commands the same kind of attention across all designs.

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Ed Sperling

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Ed Sperling is the editor in chief of Semiconductor Engineering.