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AR# 32801: 10.1.03, System Generator for DSP - Why does my System Generator generated PCORE not work as expected in EDK, or why does my System Generator for DSP pcore hang my processor when attempting to read or write to it?

AR# 32801

10.1.03, System Generator for DSP - Why does my System Generator generated PCORE not work as expected in EDK, or why does my System Generator for DSP pcore hang my processor when attempting to read or write to it?

Description

My System Generator generated PCORE does not seem to work as expected in my EDK MicroBlaze system or seems to hang the processor when accessed. Why?

Solution

This may be due to a known issue with the System Generator PCORE output in the 10.1.03 release. This issue only affects "dual clock" enabled PCOREs.

To check if the behavior is due to the known issue, open the PCORE's .MPD file in a text editor and look for the following line:

PORT splb_clk = "", DIR = I, SIGIS = clk, BUS = SPLB

If this line is not present, you will see the above issues and this answer record applies. To work around this issue, add a Gateway Out block which can be driven by a constant System Generator block, at the same level of hierarchy as the EDK Processor block. This Gateway Out block can be disabled for generation so it does not use any hardware. To disable the Gateway Out block, uncheck "Translate into output port" in the Gateway Out block parameter GUI.