EUV Results Bogus, Says Analyst

SAN JOSE, Calif. — IBM's latest test of its extreme ultraviolet lithography (EUV) scanner was met with skepticism from one industry watcher, who suggested the results were deliberately misleading. IBM called the results as a breakthrough but admitted the test was limited to certain aspects of the EUV system.

IBM announced this week that the ASML NXE3300B scanner installed at its facility in Albany, N.Y., produced 637 wafers in 24 hours at a steady rate of 34 wafers/hour with a light source delivering 44 W. Dan Corliss, IBM's EUV development program manager, said the system had a 77% uptime and delivered a 20mJ dose across 83 image fields/wafer with full wafer coverage, including partial die.

But Robert Maire, president of Semiconductor Advisors LLC, took issue with the findings. "It wasn't a real test of EUV printing," Maire said in an email exchange with EE Times.

The facts are that they used blank wafers with no resist, therefore no images were ever printed. Nothing was processed, nothing was printed and nothing was produced. All that happened was that wafers were moved from the input FOUP to the output FOUP.

In fact IBM in New York didn't even have 637 wafers so they just recycled the same blank wafers through the machine taking them from the output and feeding them back in… The only thing that was proven was that the tool could mechanically move 637 wafers in a day which even a 30 year old stepper can easily do. The other problem conveniently left out is that the quoted "exposure" level of 20mJ is not adequate with current resist technology to actually produce a usable image.

Maire also said the 14% increase in ASML's stock price after the news was the motivation for the announcement. "Both IBM and ASML are obviously desperate for some good news."

In a blog, IBM's Corliss responded to criticism of the test.

One of the primary challenges holding back the insertion of EUV is the source's power and reliability. Imaging performance is not a primary concern as it is well characterized, robust and operational on IBM's NXE3300.

The upgrade to our EUV source was intended to improve its power level and reliability. The 24 hour performance test was intended to stress those two parameters. It was never the intent of the test to generate 637 wafer exposures. That result was a by-product of the source operating correctly, at the increased power and reliably during the test period.

Putting resist on the wafers would have had no value whatsoever, other than to test how well our rework process was working.

It was unintended output that our source performed so well.

However, the result did provide the first data point in the industry that demonstrates that the current source technology does have the capability to achieve near term performance goals (wafer exposures per day). Since this result was significantly better than previously reported performance, IBM decided to share this with the semiconductor industry so that all could understand the significance and adjust their EUV activities accordingly. For IBM and our Alliance partners, this secured the EUV capability to support our 7nm technology node development.

In a separate email exchange, an IBM representative provided more details of the company's test.

"The parameter settings used for the 24-hour EUV test were established for imaging 22nm dense lines (horizontal and vertical) with a single mask and single exposure," the representative said. "We used 20 mJ/cm2 dose and conventional illumination shape. We did not break the imaging level into multiple masks nor did we employ SMO solutions."

EUV is the leading candidate for printing fine patterns needed for next-generation chips. But the complex technology has been in the lab for more than a decade. Most chip makers, including IBM, say they do not expect EUV to be ready for the 10nm chips that could start production within two years.

In an email exchange, Intel fellow Mark Bohr said his company is already exploring ways to make 7nm chips without EUV. "Intel has a way to achieve good density and good cost-per-transistor on our 10 nm technology without the use of EUV. We are continuing to explore EUV and non-EUV options for our 7nm technology."

@Rick: You may have been to Nikon's Lithovision (held adjacent to SPIE's Lithography conference) in the past on this EUV topic. As far back as 5 years (I have not been there in the last two years), attendees were told EUV is almost here and migrating to the next tech node is guaranteed to work! I am sure you heard about this proclamation for 28nm onward to what is now 7/9nm nodes. Yet EUV still remains a mirage!

IBM did indeed have a minor breakthrough exposing 637 wafers at 20mJ/cm2 in 24 hours with a machine running at 77% uptime. IBM admited from the outset this was NOT enough to make EUV viable for the 10nm node. Everyone, IBM included, is still HOPING EUV will be ready for 7nm node at the earliest.

The real breakthoughs will be getting 100+ wafers/HOUR out at something more like 50mJ/cm2 with good, useable wafers patterned at the dimensions needed for10-7nm node work.

Let's cross our fingers some brilliant engineers can make that happen in the next 12 months!

In the absence of published data, I would have to concur with Mr. Robert Maire's observations, including his point on using wafers with resists. But I wouldn't go as far as saying "All that happened was that wafers were moved from the input FOUP to the output FOUP!" I think there was more accomplished here than that!

IBM did admit that the testing scope was limited to "power level and reliability" studies of the EUV source. How ever, I disagree with the statement "Putting resist on the wafers would have had no value whatsoever", the EUV study would have gone much further using wafers with resists.

I am not sure if the announcement warranted the run up in stock prices!