This paper proposes a new low-complexity, near-lossless image compression method and its application-specific integrated circuit (ASIC) design for low power and high frame rate in the wireless endoscopy capsule system. Assuring high image quality (PSNR larger than 46.37 dB and pixel error less than 2), the proposed method can provide low complexity, low storage overhead, as well as excellent compression performance compared with other conventional interpolation-first methods and other existing similar compression-first methods. The VLSI implementation functionally consists of two pipelined parts: the preprocessor and the JPEG-LS engine. A parallel, fully pipelined VLSI architecture with a clock management mechanism is proposed for the JPEG-LS engine, which ensures a low power application and real-time data processing. The hardware implement has been verified on FPGA and implemented in 0.18-µm CMOS technology.