This patch fix the PHY poller, which can block the whole system. On aFreescale PPC 834x this result in a delay of 450 us due the slowcommunication with the PHY chip.

For PHY chips without interrupts, the status of the ethernet will bepolled every 2 sec. The poll function will read some register of the MIIPHY. The time between the sending the MII_READ_COMMAND and receiving theresult is more the 100 us on a PPC 834x.

The patch modifies the poller a lit bit. Only a link status state changewill result in a successive detection of the connection type. The pollcycle on the other hand will be increased to every seconds.

Together this patch will prevent a blocking of nearly 400 us every twoseconds of the whole system on a PPC 834x.