... NXP Semiconductors 6. Functional description 6.1 Special function registers Remark: SFR accesses are restricted in the following ways: • User must not attempt to access any SFR locations not deﬁned. • Accesses to any deﬁned SFR locations must be strictly for the functions for the SFRs. ...

... NXP Semiconductors 6.2 Memory organization The device has separate address spaces for program and data memory. 6.2.1 Flash program memory bank selection There are two internal ﬂash memory blocks in the device. Block 0 has 16/32/64 kB and is organized as 128/256/512 sectors, each sector consists of 128 B. Block 1 contains the IAP/ISP routines and may be enabled such that it overlays the ﬁ ...

... NXP Semiconductors to work during initial power up, before the voltage reaches the brownout detection level. The POF ﬂag in the PCON register is set to indicate an initial power up condition. The POF ﬂag will remain active until cleared by software. Following a power-on or external reset the P89V51RB2/RC2/RD2 will force the SWR and BSEL bits (FCF[1:0 ...

... NXP Semiconductors V must stay below V DD detection circuit will respond. Brownout interrupt can be enabled by setting the EBO bit (IEA.3). If EBO bit is set and a brownout condition occurs, a brownout interrupt will be generated to execute the program at location 004BH required that the EBO bit be cleared by software after the brownout interrupt is serviced ...

... NXP Semiconductors Table 7. Not bit addressable; Reset value 00H Bit Symbol Table 8. Bit When instructions access addresses in the upper 128 B (above 7FH), the MCU determines whether to access the SFRs or RAM by the type of instruction given indirect, then RAM is accessed direct, then an SFR is accessed. See the examples below ...

... NXP Semiconductors DPTR points to 0A0H and data in ‘A’ is written to address 0A0H of the expanded RAM rather than external memory. Access to external memory higher than 2FFH using the MOVX instruction will access external memory (0300H to FFFFH) and will perform in the same way as the standard 8051, with P0 and P2 as data/address bus, and P3.6 and P3.7 as write and read timing signals ...

... NXP Semiconductors A chip-erase operation can be performed using a commercially available parallel programer. This operation will erase the contents of this boot block and it will be necessary for the user to reprogram this boot block (block 1) with the NXP-provided ISP/IAP code in order to use the ISP or IAP capabilities of this device http://www ...

... NXP Semiconductors Table 12. Record type 6.3.5 Using the serial number This device has the option of storing serial number along with the length of the serial number (for a total non-volatile memory space. When ISP mode is entered, the serial number length is evaluated to determine if the serial number is in use. ...

... NXP Semiconductors Table 18. Bit 6.4.1 Mode 0 Putting either Timer into mode 0 makes it look like an 8048 Timer, which is an 8-bit Counter with a ﬁxed divide-by-32 prescaler. osc/6 Tn pin TnGate INTn pin Fig 8. Timer/counter mode 0 (13-bit counter) In this mode, the Timer register is conﬁgured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the Timer interrupt ﬂ ...

... NXP Semiconductors OSC 6 T2 pin transition detector T2EX pin Fig 12. Timer 2 in Capture mode This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the IEN0 register). If EXEN2 = 1, Timer 2 operates as described above, but with the added feature that a 1-to-0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2 captured into registers RCAP2L and RCAP2H, respectively ...

... NXP Semiconductors OSC pin Fig 14. Timer 2 in Auto Reload mode (DCEN = 1) When a logic 0 is applied at pin T2EX this causes Timer 2 to count down. The timer will underﬂow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. Timer 2 underﬂow sets the TF2 ﬂag and causes 0FFFFH to be reloaded into the timer registers TL2 and TH2. The external ﬂ ...

... NXP Semiconductors TCLK = 1, Timer 2 is used as the UART transmit baud rate generator. RCLK has the same effect for the UART receive baud rate. With these two bits, the serial port can have different receive and transmit baud rates – Timer 1 or Timer 2. ...

... NXP Semiconductors not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). Therefore when Timer use as a baud rate generator, T2EX can be used as an additional external interrupt, if needed. When Timer the baud rate generator mode, one should not try to read or write TH2 and TL2. Under these conditions, a read or write of TH2 or TL2 may not be accurate. The RCAP2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors ...

... NXP Semiconductors Table 26. Bit Table 27. SM0, SM1 6.6.5 Framing error Framing error (FE) is reported in the SCON.7 bit if SMOD0 (PCON. SMOD0 = 0, SCON.7 is the SM0 bit for the UART recommended that SM0 is set up before SMOD0 is set to ‘1’. 6.6.6 More about UART mode 1 Reception is initiated by a detected 1-to-0 transition at RXD ...

... NXP Semiconductors The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the ﬁnal shift pulse is generated: ( and (b) either SM2 = 0, or the received 9th data bit = 1. If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the ﬁ ...

... NXP Semiconductors clock output and input for the master and slave modes, respectively. The SPI clock generator will start following a write to the master devices SPI data register. The written data is then shifted out of the MOSI pin on the master device into the MOSI pin of the slave device. Following a complete transmission of one byte of data, the SPI clock generator is stopped and the SPIF ﬂ ...

... NXP Semiconductors In the CMOD SFR there are three additional bits associated with the PCA. They are CIDL which allows the PCA to stop during Idle mode, WDTE which enables or disables the Watchdog function on module 4, and ECF which when set causes an interrupt and the PCA overﬂ ...

... NXP Semiconductors Table 41. Bit Table 42. PCA module modes (CCAPMn register) ECOMn CAPPn CAPNn 6.9.1 PCA capture mode To use one of the PCA modules in the capture mode CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module’ ...

... NXP Semiconductors CF CR CEXn - ECOMn 0 Fig 23. PCA capture mode If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated. 6.9.2 16-bit software timer mode The PCA modules can be used as software timers and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module’ ...

... NXP Semiconductors write to CCAPnH reset write to CCAPnL enable 0 1 Fig 24. PCA compare mode 6.9.3 High-speed output mode In this mode toggle each time a match occurs between the PCA counter and the module’s capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR must be set ...

... NXP Semiconductors write to reset CCAPnH write to CCAPnL enable 0 1 Fig 25. PCA high-speed output mode 6.9.4 PWM mode All of the PCA modules can be used as PWM outputs depends on the source for the PCA timer. enable - ECOMn CAPPn 1 Fig 26. PCA PWM mode All of the modules will have the same frequency of output because they all share one and only PCA timer. The duty cycle of each module is independently variable using the module’ ...

... NXP Semiconductors value in the module’s CCAPnL SFR the output will be low, when it is equal to or greater than the output will be high. When CL overﬂows from FF to 00, CCAPnL is reloaded with the value in CCAPnH. This allows updating the PWM without glitches. The PWM and ECOM bits in the module’ ...

... NXP Semiconductors 6.10 Security bit The Security Bit protects against software piracy and prevents the contents of the ﬂash from being read by unauthorized parties in Parallel Programmer mode. It also protects against code corruption resulting from accidental erasing and programming to the internal ﬂash memory. ...

... NXP Semiconductors The device exits Idle mode through either a system interrupt or a hardware reset. Exiting Idle mode via system interrupt, the start of the interrupt clears the IDL bit and exits Idle mode. After exit the Interrupt Service Routine, the interrupted program resumes execution beginning at the instruction immediately following the instruction which invoked the Idle mode ...

... NXP Semiconductors 6.13 System clock and clock options 6.13.1 Clock input options and recommended capacitor values for oscillator Shown in ampliﬁer (XTAL1, XTAL2), which can be conﬁgured for use as an on-chip oscillator. When driving the device from an external clock source, XTAL2 should be left disconnected and XTAL1 should be driven ...

... NXP Semiconductors 9.1 Explanation of symbols Each timing symbol has 5 characters. The ﬁrst character is always a ‘T’ (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A — ...

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation speciﬁcations and product descriptions, at any time and without notice ...