2.5-D Stacks Pile Up at Event

More than a dozen companies presented results of test chips or support capabilities for 2.5-D and 3-D chip stacks at a recent event.

Most speakers at the recent 3D Architectures for Semiconductor Integration and Packaging (3-D ASIP) event expressed optimism that materials, equipment, and manufacturing flows are ready for interposer-based 2.5-D designs. Many prototypes and evaluation units are in progress, with very positive reliability test results shown in a number of presentations. In addition, Hynix and Tezzaron presented their memory stacks using through silicon vias for boosting memory access by mounting these devices side-by-side with CPUs on an interposer.

Only a few presenters attached specific dates to their roadmaps -- a clear sign that the market pull for this technology is not in full swing yet. Most likely customers are still analyzing 2.5-D benefits and cost savings on the system-level before engaging on a broader scale. In private discussions, last week’s presenters labeled 2014 as the year of many design-ins and 2015 as the year of production ramps for interposer-based designs with 3-D memory stacks. These predictions may prove to be too conservative considering Samsung’s successful Exynos processor is already using Wide I/O technology in production.

In one of the more interesting talks, Joseph Maurer outlined a variety of ongoing DARPA-funded programs working with several partners in industry and academia to enhance intra- and inter-chip cooling, one of the chief hurdles of 3-D stacks. Separately, Georgia Tech outlined efforts to enhance cooling for and reliability of vertically stacked dies in chip stacks.

Robert Patti described Tezzaron’s 3D-RAM architecture. It implements I/O circuits, sense amps, and the actual memory cells with access transistors in separate, vertically stacked dies. The architecture introduces new levels of modularity and flexibility. It improves performance, power dissipation, redundancy, management, and testability.

AMD’s Bryan Black explained from a system-level and cost perspective why chip stacks will replace continued feature-size shrinking in the next several years. He also described the benefits of SK Hynix's High-Bandwidth Memory (HBM) for graphics applications.

Semtech’s Craig Hornbuckle reported on a joint development project with IBM for a high-speed networking application. The companies integrated a 45-nm CMOS logic die with two SiGe dies, coming from different fabs, on an interposer. He described the high bandwidth between the three dies, the low insertion loss and the excellent SNR, and other benefits of the device.

Kazuki Fukuoka from Renesas described work on a 3-D test vehicle, combining a logic die and a 4 Gbit Wide I/O DRAM using through silicon vias. The device reduced I/O power 89 percent compared to discrete chips.

In other talks, Arif Rahman stated that Altera will use die stacking in its Stratix 10 products, manufactured in Intel’s 14-nm technology. Teledyne’s Miguel Urteaga said chip stacks integrating III-V materials with silicon will offer performance and power benefits in very high frequency applications.

Yervant Zorian, a test expert at Synopsys, showed how the company's design tools enable testing of chip stacks. They use boundary-scan and test-wrappers -- as suggested in IEEE P1838 -- to access digital circuitry in every die of a stack and deploy BIST engines to test analog blocks.

Minsuk did not quote specific power savings in his SK Hynix presentation this time.

Depending on what you use to compare it (interconnect power only / interconnects and I/Os / Chip-level comparison / sub-system comparison) you get different ratios. Based on what I learned in other presentations, I can assure you that Wide I/O 1 beats LPDDR3 and Wide I/O 2 beats LPDDR4 in regards to Bandwidth per mWatt.

FYI: Samsung is calling the WideI/O standard internally "Widcon" (for WIDe CONnection) and it utiling it in the Exynos 5 volume production. See more about it at:

Herb, SK Hynix's reliability highlight is great to know, thanks! I hope at some point the data including Weibull / FITs will be published in technical journals. I assume SK also achieved significant savings in IO power consumption in the WideIO designs.

Herb, thanks as always for continuing to be a 3D/2.5D evangelist. I am a bit surprised that the 2.5D stacks are still more than an year away from production ramps and that too from a limited numbrer of players. Could it be that there are many more that are actively developing and perhaps chosen not to publicize their projects?

Can you write more on the reliability studies of SK Hynix HBM devices? This would be very valuable for us 3D enthusiasts since that data is hard to come by for products already in the market (like those of Samsung!).