Logic Analyzer

Description

The Logic Analyzer is a tool for visualizing and inspecting
signals in your Simulink® model. Using the Logic Analyzer, you can:

Debug and analyze models

Trace and correlate many signals simultaneously

Detect and analyze timing violations

Trace system execution

Detect signal changes using triggers

For keyboard shortcuts, click
More.

More

Keyboard Shortcuts

Actions

Description

Applicable When

Ctrl+X

Cut

Wave is selected

Ctrl+C

Copy

Wave is selected

Ctrl+V

Paste

Wave is selected

Delete

Delete

Wave is selected

Ctrl+-

Zoom out

Always

Shift+Ctrl+-

Zoom out around active cursor

Always

Ctrl++

Zoom in

Always

Shift+Ctrl++

Zoom out around active cursor

Always

Shift+Ctrl+C

Move display to active cursor

When cursor is not in the display range

Space

Zoom out full

Always

Tab, Right Arrow

Next transition

Digital format wave is selected

Shift+Tab, Left Arrow

Previous transition

Digital format wave is selected

Ctrl+A

Select all waves

Always

Up Arrow

Select wave above selected

Wave is selected

Down Arrow

Select wave below selection

Wave is selected

Ctrl+Up Arrow

Move selected waves up

Wave is selected

Ctrl+Down Arrow

Move selected waves down

Wave is selected

Escape

Unselect all signals

Wave is selected

Page Up

Scroll up

Always

Page Down

Scroll down

Always

Open the Logic Analyzer App

On the Simulink toolstrip Simulation tab, click the Logic Analyzer app
button. If the button is not displayed, expand the review results app gallery. Your most
recent choice for data visualization is saved across Simulink sessions.

To visualize referenced models, you must open the Logic Analyzer from the referenced
model. You should see the name of the referenced model in the Logic Analyzer
toolbar.

Examples

Select Signals to Analyze

The Logic Analyzer supports several methods for
selecting data to visualize.

Select a signal in your model. When you select a signal, an
ellipsis appears above the signal line. Hover over the ellipsis to
view options and then select the Enable Data
Logging option.

Right-click a signal in your model to open an options dialog box.
Select the Log Selected Signals option.

Use any method to select multiple signal lines in your model. For
example, use Shift+click to select multiple
lines individually or CTRL+A to select all
lines at once. Then click the Logic Analyzer button
arrow and select Log Selected Signals.

To visualize data in the Logic Analyzer, you must enable signal logging
for the model. (Logging is on by default.) To enable signal logging, open
Model Settings from the toolstrip, navigate to the
Data Import/Export pane, and select
Signal logging.

When you open the Logic Analyzer, all signals marked for
logging are listed. You can add and delete waves from your Logic
Analyzer while it is open. Adding and deleting signals does not
disable logging, only removes the signal from the Logic Analyzer.

Modify Global Settings

Open the Logic Analyzer and select Settings from the
toolstrip. A global settings dialog box opens. Any setting you change for an individual
signal supersedes the global setting. The Logic Analyzer saves any setting changes with the
model (Simulink) or System
object™ (MATLAB®).

Set the display Radix of your signals as one of the following:

Hexadecimal — Displays values as symbols from zero to nine and A to F

Octal — Displays values as numbers from zero to seven

Binary — Displays values as zeros and ones

Signed decimal — Displays the signed, stored integer value

Unsigned decimal — Displays the stored integer value

Set the display Format as one of the following:

Automatic — Displays floating point signals in Analog
format and integer and fixed-point signals in Digital format. Boolean signals are
displayed as zero or one.

Analog — Displays values as an analog plot

Digital — Displays values as digital transitions

Set the display Time Units to one of the following:

Automatic — Uses a time scale appropriate to the time range shown in the current
plot

Gradient— Adds color highlighting to Boolean signals based on value. If the signal
value is true, the highlight fades out below. If the signal value is false,
the signal fades out above. With this option, you can visually deduce the value of the signal.

Inspect the graphic for an explanation of the global settings: Wave Color, Axes
Color, Height, Font Size, and
Spacing. Font Size applies only to the text within the axes.

By default, when your simulation stops, the Logic Analyzer shows all the data for the simulation time on one screen. If
you do not want this behavior, clear Fit to view at Stop. This option is disabled for long simulation
times.

To display the short names of waves without path information, select Display short wave
names.

You can expand fixed-point and integer signals and view individual bits. The Display Least Significant bit
first option enables you to reverse the order of the displayed bits.

If you stream logged bus signals to the Logic Analyzer, you can display the names of the
signals inside the bus using the Display bus element names option. To
show bus element names:

If the bus contains an array of buses, the Logic Analyzer prepends the element name with the bus array index.

Modify Individual Wave Settings

Open the Logic Analyzer and select a wave by double-clicking
the wave name. Then from the Wave tab, set parameters
specific to the individual wave you selected. Any setting made on individual
signals supersedes the global setting. To return individual wave parameters
to the global settings, click Reset.

Delete and Restore Waves

Open the Logic Analyzer and select a wave by clicking the
wave name.

From the Logic Analyzer toolstrip, click . The wave is removed from the Logic
Analyzer.

To restore the wave, from the Logic Analyzer toolstrip,
click .

A divider named Restored Waves is added to the
bottom of your channels, with all deleted waves placed below it.

Add Trigger

The Logic Analyzer trigger allows you to find data points based on
certain conditions. This feature is useful for debugging or testing when you need to
find a specific signal change.

Open the Logic Analyzer and select the
Trigger tab.

To attach a signal to the trigger, select Attach
Signals, then select the signal you want to trigger on. You
can attach up to 20 signals to the trigger. Each signal can have only one
triggering condition.

By default, the trigger looks for rising edges in the attached signals.
You can set the trigger to look for rising or falling edges, bit sequences,
or a comparison value. To change the triggering conditions, select
Set Conditions.

If you add multiple signals to the trigger, control the trigger logic
using the Operator option:

AND - match all conditions.

OR - match any condition.

To control how many samples you see before triggering, set the
Display Samples option. For example, if you set
this option to 500, the Logic Analyzer tries
to give you 500 samples before the trigger. Depending on the simulation, the
Logic Analyzer may show more or fewer than 500 samples
before the trigger. However, if the trigger is found before the 500th
sample, the Logic Analyzer still shows the trigger.

Control the trigger mode using Display Mode.

Once - The Logic
Analyzer marks only the first location matching the
trigger conditions and stops showing updates to the Logic
Analyzer. If you want to reset the trigger, select
Rearm Trigger. Relative to the
current simulation time, the Logic Analyzer shows
the next matching trigger event.

Before running the simulation, select Enable
Trigger. A blue cursor appears as time 0. Then, run the
simulation. When a trigger is found, the Logic Analyzer marks
the location with a locked blue cursor.

Choose Visible Instance of Multi-Reference Model Block

The Logic Analyzer can stream only a single instance of a multi-instance Model block. If the same model is opened across different windows, those models will share the same Logic Analyzer. This example shows how to select an instance of a multi-instance Model block for logging on the Logic Analyzer.

Open the multipleModelInstances.

open_system('multipleModelInstances')

The model contains three intances of the referencedModel model.

Double-click any of the Model blocsk to open the model referenced by all three Model blocks.

open_system('referencedModel')

Open the Logic Analyzer in the referenced model by double-clicking the logging symbol next to the MovignAverage block. You should see referencedModel - [multipleModelInstances] in the toolbar of the Logic Analyzer.

From the Logic Analyzer window, run the model. By running the simulation from a referenced version of referencedModel, Simulink runs the top model (multipleModelInstances) and referenced models (referencedModel). The Logic Analyzer displays a single instance of a multi-instance Model block.

When you run a simulation, the logic analyzer runs the model listed in the Logic Analyzer toolbar. If this model is a referenced model, the toolbar also lists the top model and you will see results from running the top model. To view results from the referenced model in isolation, you must open the referenced model as a top model.

Add Triggers to Verify Write Operation

To add a trigger, in the toolstrip, select Attach
Signals and attach the write enable Write
En signal. An icon appears in front of the signal name to
indicate it is attached to a trigger. The icon changes depending on the type
of trigger.

Select Set Conditions and change the trigger
condition for the Write En signal to Falling
Edge. The trigger will show when the write enable signal was
sent.

Attach the Write Done signal to the trigger. Keep the
trigger condition for this signal as the default, Rising
Edge. Now, the trigger will also show when the write was
completed.

If you open the Set Conditions drop down, you see an
Operator field. This field appears when multiple
signals are attached to the trigger. Change the operator to
OR so that the trigger will show instances
where a write was started or completed.

Set the Display Mode to
Auto. With this setting, the Logic
Analyzer marks all locations where the trigger conditions are
met.

Select Enable Trigger and run the
simulation.

Each time the trigger conditions are met, the Logic Analyzer
marks the time with a locked blue cursor. At each marked location,
Write En is 0 and Write
Done is 1. If you examine each location
marked by a trigger, you can verify that each time a write is sent, it is
also completed.