Kickstarter

The initial run of Parallella computers is being funded via a Kickstarter campaign, which on 27th October 2012 had succeeded in raising $898,921 via 4,965 backers, and with those pledging $99 or more receiving at least one board.

Thanks to generous support from Xilinx, the Kickstarter boards will be upgraded to use a Zynq-7020 SoC instead of a Zynq-7010.

General availability

Pre-orders sold out and ordering is currently expected to reopen in January 2013.

Revisions

A 66-Core Parallella Prototype

Prototype

The first Parallella prototypes shipped in late December 2012 and comprise of a ZedBoard plus a 16 or 64-core Epiphany FMC.

From a software perspective the prototypes are virtually identical to the final form factor boards.

Beta (Gen0)

The first 10 Parallella beta boards came back from assembly on 11th April 2013 and were unveiled four days later at the Linux Foundation Collaboration Summit.

In July 2013 22 Gen0 boards went out Kickstarter backers, and a further 18 to key project contributors.

Backers who were due to receive a board but who opted to wait a little longer will receive a Gen1 board upgraded with a 64-core Epiphany co-processor.

Beta (Gen1)

Gen1 boards were manufactured in August 2013 and these were given to certain backers, key members of the community and some people who won them as prizes at the CodeMesh conference.

includes 48 bidirectional signals that can be configured within the Zynq device to support a number of different signal standards. When configured as LVDS signals, each differential signal pair provides a maximum bandwidth of 950Mbps. In aggregate, the PEC_FPGA connections can provide 22Gbps of total I/O bandwidth.

PEC_NORTH/PEC_SOUTH expansion:

3.2GB/s total I/O bandwidth via 2.5V LVDS

2.8GB/s total I/O bandwidth via 1.8V subLVDS

Real-time clock:

None

Power source:

5 V (DC) at 1A

Size:

3.4" x 2.15"

Documentation

Parallella

The Parallella computer is open source hardware: the board design files are published under the Creative Commons Attribution-ShareAlike 3.0 license, and the FPGA HDL sources under the GPL.