Reading Richard Goering’s blog about the Cadence-Imec collaboration on 3D-IC design for test architecture—How Imec and Cadence “Wrapped Up” 3D-IC Test—gave me a strong sense of déjà vu all over again. (Never pass up a chance to quote the great Yogi Berra.) Goering’s blog entry discusses the difficulties of testing pre-bonded die and post-bonded 3D assemblies and the use of the IEEE 1500 standard to overcome these difficulties. Here’s what Goering writes about pre-bond testing:

“[Brion] Keller [senior architect at Cadence] noted that pre-bond testing is difficult for any die that is not intended to be the bottom die in a stack. Such dies only connect to the dies above or below through TSVs (where the TSVs touch down on micro-bumps on the neighboring die), and the resulting pins and micro-bumps are too small for current probe technology to handle.”

Here’s what Goering wrote about testing post-bonded 3D IC assemblies:

“During post-bond testing, the only contact you have with the package is through the package pins, and to access those you have to go through the bottom die.”

These factors are driving the quest to develop early standards for 3D IC die and assembly testing. All of this—especially the problems with probe access—seemed very, very familiar to me so I used Google to quickly find an editorial that I wrote and published in EDN back in early 1996, more than 15 years ago, when the IEEE 1149.1 test standard was still being adopted for board-level assemblies to combat the probe-access problems associated with surface-mount technology:

Design for test—or else. . .

Recently, I moderated an all-day design-for-test (DFT) seminar sponsored by Asset Intertech, National Semiconductor, and Synopsys. Odds are, you weren’t there. What follows are my opening remarks from the seminar, for your thoughtful consideration. If you have not looked at DFT methods in a while, this is a good time to do so. Design teams must use DFT methods, or they will quickly fall behind in today’s competitive markets.

“November 1995 marked the 10th anniversary of the development of boundary-scan standards. Back in 1985, Alcatel started the test-bus study group that became JTAG, or the Joint Test Action Group. Philips quickly took over the JTAG bandwagon and started driving it. JTAG hooked up with the IEEE’s P1149 serial-test-standard working group and the combined efforts eventually resulted in the 1149.1 standard.

“Surface-mount technology, with its fine component lead pitches and reduced pc-board geometries, has accelerated the problems of testability. Here’s what I wrote about testability in my Decade 90 series published seven years ago in EDN:

‘Many design engineers’ and managers’ attitudes about product testability seem to have frozen during an earlier era in electronics, when a technician could troubleshoot almost any problem in 20 minutes with a scope and a little savvy. For products designed without the design-for-testability philosophy, today’s most advanced in-circuit ATE testers can do no more than automate the time-honored tradition of sticking a test probe into a failing test node to find the problem. But as electronic systems grow in complexity, this approach grows less and less effective and increasingly costly.’

“In an epoch of world-shattering upheavals in electronic technology, it’s amazing how slowly some things change. Here’s what EDN’s test-and-measurement editor Dan Strassberg wrote about boundary-scan testing in his cover story published in October 1993:

‘As boards become increasingly dense, nodal-access problems of the kind once thought to be unique to multichip modules are affecting more and more boards. Boundary-scan testing is about the only game in town for overcoming these problems. But, like nearly every new technology, its acceptance has been hindered by a poorly developed infrastructure and, possibly, by a bit too much early optimism from partisans.’

“Our mission today is to convince you that much of that missing infrastructure is now developed, in the form of silicon, EDA tools, and test systems. You can and you should now be designing your products for testing.”

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About the author:

Steve Leibson has appeared on television with Leonard Nimoy (Star Trek's Mr. Spock), however he's not a TV star (although he's always open to offers). He is the Cadence EDA360 Evangelist and a Marketing Director at Cadence Design Systems, the leading EDA vendor for system and chip-level design tools, design IP and IP design platforms, and verification IP. Steve’s written some of the key books about IP-based SOC design including “Designing SOCs with Configured Cores,” published in 2006 and “Engineering the Complex SOC,” co-authored with Dr. Chris Rowen and published in 2004. An experienced design engineer, Steve has been evangelizing advanced, IP-centric SOC design since 2001.