We've heard a lot about Moore's Law slowing lately, and while that does seem to be true in some cases, in other parts of the semiconductor business, there is ongoing progress. At last week's International Solid-State Circuits Conference (ISSCC), the big chip trends seemed to be around deploying new materials, new techniques, and new ideas to keep pushing transistor density higher and improving on power efficiency. Of course, that isn't really news. We saw this reflected in talks about producing logic chips on new 7nm processes, on creating 512Gb 3D NAND chips, and on a variety of new processors.

Chip designers are considering new structures and materials for transistors, as shown in the slide above from TSMC. There were also plenty of discussions of new tools for making the transistors, including lithography advances such as EUV and directed self-assembly, and new ways of packaging multiple die together.

Before digging into the details, it remains pretty amazing to me just how far the chip industry has come and just how pervasive chips have become in our daily lives. Texas Instruments CTO Ahmad Bahai noted in his presentation that in 2015, the industry sold an average of 109 chips for every person on the planet. His talk focused on how instead of markets dominated by a single application—first PCs, then cell phones –the industry now needs to be more focused on "making everything smarter," as different kinds of chips find their way into a huge number of applications.

The industry faces big challenges, though. The number of companies that can afford to build leading-edge logic fabrication plants has shrunk from twenty-two at the 130nm node to just four companies today at the 16/14nm node (Intel, Samsung, TSMC, and GlobalFoundries), with new process technology costing billions to develop, and new plants costing even more. Indeed, last week Intel said it would spend $7 billion to develop 7nm at a shell of a fab it built a few years ago in Arizona.

Still, there were a number of presentations on various companies' plans to move to 10nm and 7nm processes.

TSMC has rolled out its 10nm process, and the first chip announced was the Qualcomm Snapdragon 835, which is due out shortly. TSMC may be the farthest along at actually commercializing what it calls a 7nm process, and at ISSCC, it described a functional 7nm SRAM test chip. This will use the now-standard FinFET transistor concept, but with some circuit techniques to make it work reliably and efficiently at the smaller size. Notably, TSMC says it will produce the first version of its 7nm chips using immersion lithography, rather than waiting for EUV like most of its competitors.

Recall that what each of the major manufacturers calls 7nm varies tremendously, so in terms of density, it's possible that the TSMC 7nm process will be similar to Intel's forthcoming 10nm process.

Samsung is also working on 7nm, and the company has made it clear that it plans to wait for EUV. At the show, Samsung talked about the advantages of EUV lithography as well as the progress it has made in using the technology.

3D NAND

Some of the more interesting announcements covered 512Gb 3D NAND flash, and showed just how quickly NAND flash density is growing.

Western Digital (which has acquired SanDisk) talked about a 512Gb 3D NAND flash device that it announced prior to the show, and explained how this device continues to increase the density of such chips.

This particular chip uses 64 layers of memory cells and three-bits-per-cell to reach 512Gb on a die that measures 132 square millimeters. It's not quite as dense as the Micron/Intel 3D NAND design, which uses a different architecture with the peripheral circuitry under the array (CuA) to reach 768Gb on a 179 square millimeter die, but it's a nice step forward. WD and Toshiba said it was able to improve reliability and to speed up read times by 20 percent and reach write throughput speeds of 55 Megabytes per second (MBps). This is in pilot production, and due to be in volume production in the second half of 2017.

Not to be outdone, Samsung showed off its new 64-layer 512Gb 3D NAND chip, one year after it showed a 48-layer 256Gb device. The company made a big point to demonstrate that while the areal density of 2D NAND flash grew 26 percent per year from 2011 to 2016, it has been able to increase the areal density of 3D NAND flash by 50 percent per year since introducing it three years ago.

Samsung's 512Gb chip, which also uses three-bits-per-cell technology, has a die size of 128.5 square millimeters, making it slightly denser than the WD/Toshiba design, though not quite as good as the Micron/Intel design. Samsung spent much of its talk describing how using thinner layers has presented challenges and how it has created new techniques to address reliability and power challenges created by using these thinner layers. It said read time is 60 microseconds (149MBps sequential reads) and write throughput is 51MBps.

It's clear all three of the big NAND flash camps are making good process, and the result should be denser and eventually less expensive memory from all of them.

New Connections

One of the topics I have found most interesting lately is the concept of an embedded multi-die interconnect bridge (EMIB), an alternative to other so-called 2.5D technologies that combine multiple die in a single chip package that is less expensive because it doesn't require a silicon interposer or through-silicon vias. At the show, Intel talked about this when describing a 14nm 1GHz FPGA that will have a die size of 560mm2 surrounded by six 20nm die transceivers that are manufactured separately, even possibly on other technologies. (This is presumably the Stratix 10 SoC.) But it became more interesting later in the week, as Intel described how it would use this technique to create Xeon server chips at 7nm and the third generation of 10nm.

Processors at ISSCC

ISSCC saw a number of announcements about new processors, but rather than chip announcements, the focus was on the technology that goes into actually making the chips work as well as possible. I was interested to see new details for a number of highly anticipated chips.

I'm expecting the new Ryzen chips using AMD's new ZEN architecture to ship shortly, and AMD gave a lot more technical details about the design of the Zen core and the various caches.

This is a 14nm FinFET chip based on a basic design consisting of a core complex with 4 cores, a 2MB level 2 cache, and 8MB of 16-way associative level 3 cache. The company says the base frequency for an 8-core, 16-thread version will be 3.4GHz or higher, and said the chip offers a greater than 40 percent improvement in instructions per cycle (IPC) than the previous AMD design.

The result is a new core that AMD claims is more efficient than Intel's current 14nm design, though, of course, we'll have to wait for final chips to see the real performance.

As described before, this will be available initially in desktop chips known as Summit Ridge and is slated to be out within weeks. A server version known as Naples is due out in the second quarter and an APU with integrated graphics primarily for laptops is due to appear later this year.

IBM gave more detail on the Power9 chips it debuted at Hot Chips, designed for high-end servers, and now described as being "optimized for cognitive computing." These are 14nm chips that will be available in versions for both scale out (with 24 cores that can handle 4 simultaneous threads) or scale up (with 12 cores that can handle 8 simultaneous threads.) The chips will support the CAPI (Coherent Accelerator Processor Interface) including CAPI 2.0 using PCIe Gen 4 links at 16 gigabits per second (Gbps); and OpenCAPI 3.0, designed to work at up to 25Gbps. In addition, it will work with NVLink 2.0 for connections to Nvidia's GPU accelerators.

MediaTek gave an overview of its forthcoming Helio X30, a 2.8GHz 10-core mobile processor, notable for being the company's first to be produced on a 10nm process (presumably at TSMC).

This is interesting because it has three different core complexes: the first has two ARM Cortex-A73 cores running at 2.8GHz, designed to handle heavy-duty tasks quickly; the second has four 2.5GHz A53 cores, designed for most typical tasks; and the third has four 2.0GHz A35 cores, which are used when the phone is idle or for very light tasks. MediaTek says the low-power A53 cluster is 40 percent more power efficient than the high-power A73 cluster, and that the ultra-low-power A35 cluster is 44 percent more power efficient than the low-power cluster.

At the show, there were a lot of academic papers on topics like chips specially designed for machine learning. I'm sure we'll see much more emphasis on this going forward, from GPUs to passively parallel processors designed to handle 8-bit computing, to neuromorphic chips and custom ASICs. It's a nascent field, but one that is getting an amazing amount of attention right now.

Even further out, the biggest challenge may be moving to quantum computing, which is a whole different way of doing computing. While we are seeing more investments, it still seems a long way from becoming a mainstream technology.

In the meantime, though, we can look forward to a lot of cool new chips.

Michael J. Miller is chief information officer at Ziff Brothers Investments, a private investment firm. Miller, who was editor-in-chief of PC Magazine from 1991 to 2005, authors this blog for PCMag.com to share his thoughts on PC-related products. No investment advice is offered in this blog. All duties are disclaimed. Miller works separately for a private investment firm which may at any time invest in companies whose products are discussed in this blog, and no disclosure of securities transactions will be made.

Michael J. Miller's Forward Thinking Blog: forwardthinking.pcmag.com
Michael J. Miller is chief information officer at Ziff Brothers Investments, a private investment firm. From 1991 to 2005, Miller was editor-in-chief of PC Magazine, responsible for the editorial direction, quality, and presentation of the world's largest computer publication.
No investment advice is offered in this blog. All duties are disclaimed. Miller works separately for a private investment firm which may at any time invest in companies whose products are discussed in this blog, and no disclosure of securities transactions...
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