This paper presents a new algorithm on low power survivor path memory implementation of the trace-back systolic array Viterbi algorithm. A novel idea is to reuse the already-generated trace-back routes to reduce the number of trace-back operations. And the spurious switching activity of the trace-back unit is reduced by making use of a clock gating method. Using the SYNOPSYS power estimation tool, DesignPower, our experimental result shows the average power reduction and area increase against the trace-back unit introduced in [1].

Scattered look-ahead(SLA) pipelining method can be efficiently used for high-speed or low-power applications of digital II R filters. Although the pipelined filters are guaranteed to be stable by this method, these filters suffer from large roundoff noise when the poles are crowded within some critical regions. An angle and radius constrained II R fille. design approach using modified Remez exchange algorithm and least squares algorithm is proposed to avoid tight pole-crowding in pipelined filters, resulting in improved frequency responses and reduced coefficient sensitivities. Experimental results demonstrate that our proposed method leads to chip area reduction by and low power by against the conventional method.

Similarly to the edges defined in a 2D image, we can define the geometric features representing the boundary of the distinctive parts appearing on 3D meshes. The geometric features have been used as basic primitives in several applications such as mesh simplification, mesh deformation, and mesh editing. In this paper, we propose geometric livewire and geometric livelane for extracting geometric features in a 3D mesh, which are the extentions of livewire and livelane methods in images. In these methods, approximate curvatures are adopted to represent the geometric features in a 3D mesh and the 3D mesh itself is represented as a weighted directed graph in which cost functions are defined for the weights of edges. Using a well-known shortest path finding algorithm in the weighted directed graph, we extracted geometric features in the 3D mesh among points selected by a user. In this paper, we also visualize the results obtained from applying the techniques to extracting geometric features in the general meshes modeled after human faces, cows, shoes, and single teeth.

Causal order of message delivery algorithm ensures that every transmitted message is delivered in causal order. It should be noted that control information should be transmitted with each message in order to enforce causal order. Hence, it is important to reduce this communication overhead because the impact of the overhead increases proportionally with the number of related processes. In this paper we propose and evaluate effective a order algorithm for multimedia data which have real-time property. To reduce transmission overhead, proposed algorithm eliminates redundant information as early as possible which is not explicitly required for preserving causal order. Average communication overhead of our algorithm is much smaller than other existing algorithms.

In this paper, we propose XMDR(XML Metadata Registry) to guarantee the interoperability of data in distributed database, and describe a data synchronizing agent system using it. The proposal of XMDR is to solve the data heterogeneity problem in the sharing and exchanging data. Data heterogeneity problem is generated by different definition or mismatching expression of the same information. Therefore, we define XMDR with XML document by analyzing data elements based on MDR specification. The proposed synchronizing agent system using XMDR not only solves data heterogeneity for data interoperability in synchronizing data but also provides more efficient the agent system by offering errors of low frequency in the number of systems and requests of synchronizing data.

Memory reference instruction caused by cache miss is the critical factor that limits the processing power of processor. Cache prefetching technique is an effective way to reduce the latency due to memory access. However, excessively aggressive prefetch leads to cache pollution and finally to cancel out the advantage of prefetch. In this study, an active prefetch filtering scheme is introduced which dynamically decides whether to commence prefetching after referring a filtering table to reduce the cache pollution due to unnecessary prefetches. For the precision filtering, an evicted address referencing scheme has been proposed where the filter directly compares the current prefetch address with previous unnecessary prefetch addresses stored in filtering table. Moreover, a small sized exclusive prefetch cache has been introduced to increase the amount of eviction of unnecessarily prefetched addresses to enhance the accuracy of dynamic filtering. The exclusive prefetch cache also prevents useful demand data from being pushed out by prefetched data, while the evicted address direct referencing scheme enables the prefetch cache to keep most of useful prefetch data within its small size. Experimental results from commonly used general and multimedia benchmarks show that the average cache miss ratio has been decreased by by virtue of enhanced filtering accuracy compared with conventional schemes.

The use of computers for control and monitoring of industrial process has expanded greatly in recent years. The computer used in such applications is shared between a certain number of time-critical control and monitor function and non time-critical batch processing job stream. Embedded systems encompass a variety of hardware and software components which perform specific function in host computer. Many embedded system must respond to external events under certain timing constraints. Failure to respond to certain events on time may either seriously degrade system performance or even result in a catastrophe. In the design of real-time embedded system, decisions made at the architectural design phase greatly affect the final implementation and performance of the system. Flexibility indicates how well a particular system architecture can tolerate with respect to satisfying real-time requirements. The degree of flexibility of real-time system architecture indicates the capability of the system to tolerate perturbations in timing related specifications. Given degree of flexibility, one may compare and rank different implementations. A system with a higher degree of flexibility is more desirable. Flexibility is also an important factor in the trade-off studies between cost and performance. In this paper, it is identified the need for flexibility function and shows that the existing real-time analysis result can be effective. This paper motivated the need for a flexibility for the efficient analysis of potential design candidates in the architectural design exploration or real time embedded system.

In this paper, we propose a method of generating a JIT compiler using JBURG. JBURG is a tool of generating the code generator using bottom-up tree pattern matching for Java. Our method can be derived from some relations over tree patterns. The proposed scheme is more efficient than JBURG because we can avoid unfruitful tests with the smaller site of the scheme. Furthermore, the relevant analyses needed for this proposal are largely achieved at non- compile time, which secures actual efficiency at compilation time.

The elevator system which is operated nowadays at skyscrapers, apartments and enterprises does not offer standby passengers any information of which floor the elevator is going to stop or skip. This study will introduce the system that shows the Passengers a running schedule of the elevator. If this system is utilized for current systems, it will bring so much benefit such as shortening waiting time or choosing alternatives for the passengers. Furthermore, this system will be set up not stopping the floor for the passengers who choose alternatives like using stairs or escalators with using toggle switches. This will be efficient to save the electric power.

With the growth of the Internet, web-based cyber education is progressing from the text-based to the hyper-based including multimedia, and from one way of simply giving the contents to the learner to another way of providing mutual interaction between the instructor and the learner. For this, there uses the RIA-based dynamic application and multimedia. RIA, which is the new paradigm on the web, provides the learners with more effective and rich contents. For developing a cyber education system, if we use the existing web languages, a large amount of effort is needed. But if we use the RIA-based paradigm, we can remarkably reduce the effort. Also, in developing a new web-based cyber education system the RIA paradigm makes the learners to satisfy their demands, and in developing the system providing the interaction the paradigm gives us the way minimizing the time and effort. In this paper, we compare and evaluate the efforts in developing the RIA based education system with the Non-RIA based education system.

This paper suggests that sparse code motion algorithm should be used to make the code optimal in the respect of computation and lifetime. This algorithm Is SpCM algorithm, which expand BCM and LCM algorithm. BCM algorithm carries out the optimal code motion computationally and LCM algorithm reduces the register pressure in SpCM algorithm. Generally, code motion algorithm accomplishes the run-time optimal connected with the optimum of computation and the register pressure. Computational cost and consideration of the code size in the register pressure are also added in the paper. The optimum of code motion could be obtained through SpCM algorithm, which considers the code size, in audition to computational optimal and lifetime optimal. The algorithm presented in this paper is the most optimal algorithm in the respect of computation and lifetime, as all the unnecessary code motions are restrained.