AD2S1205/AD2S1210 Common-Mode Voltage

As of AD2S1205, the datasheet features norminal 1.25V offset on SIN/COS pins, but in my customer application, they have 2.5V offset on SIN/COS pins by using external buffer, and looks it is workable for long time withou fault.

My question is that it is really correct for 1.25V+/-100mV offset on SIN/COS pins as AD2S1205 datasheet? and if it is 2.5V offset on SIN/COS pins, what will happen over long time?

On AD2S1210 datasheet, the spec of 1.25V nonimal offset on SIN/COS pins has been deleted, does it means AD2S1210 SIN/COS input signal common mode voltage could be varing flexibly?

Please refer to Table 1 of the data sheet in Page 3 for the requirement of SIN/COS inputs. The input signal range is 2.3 Vpp to 4.0 Vpp differential and SIN/COS inputs must be always between 0.15 V and AVDD - 0.2 V with respect to AGND.

As long as the input signals will not go below or over the requirements, any bias is allowed. The selection of the 2.5 V bias (mid-scale) is the safest location to prevent violation on the input requirements since this gives the most headroom.

Your follow-up question is referring to common-mode voltage and not related to your original post, so I have "branched" it to track your threads easily. Anyway, I'll get back to your query with a reply.

The AD2S1205 sine and cosine inputs are biased to Vref/2 and the spec 1.25 V +/- 100 mV refers to this bias voltage. Signals are biased to ensure the sine and cosine signals are within the operating range of the AD2S1205 as the resolver removes any dc component from the signals. The internal bias is a weak bias and is easily over driven. So setting a 2.5 V bias is not an issue.

Sorry I have additonal question about the external 2.5V bias, that is what is allowed varing range of this bias voltage. As datasheet, if internal 1.25V bias, the limit range is +/-100mV, but not sure what is the variation range of external bias.

And if external bias variation is over this limitation range, whether or not AD2S1205 or AD2S1210 is available to report fault, and what is the fault?

I make this question is because the customer is using external buffer to drive SIN/COS signals, so it is important to know spec of bias & bias variation limit, we can't find it on datasheet.

It is helpful if internal circuit diagram about SIN & CON input stage is available to provide.

Please refer to Table 1 of the data sheet in Page 3 for the requirement of SIN/COS inputs. The input signal range is 2.3 Vpp to 4.0 Vpp differential and SIN/COS inputs must be always between 0.15 V and AVDD - 0.2 V with respect to AGND.

As long as the input signals will not go below or over the requirements, any bias is allowed. The selection of the 2.5 V bias (mid-scale) is the safest location to prevent violation on the input requirements since this gives the most headroom.