VHDL constants are objects whose values do not change. The value of a constant, however, does not need to be assigned at the time the constant is declared; it can be assigned later in a package body if necessary, for example.

The syntax of the constant declaration statement is shown above. The constant declaration includes the name of the constant, its type, and, optionally, its value.

Constants

Name assigned to a specific value of a type

Allow for easy update and readability

Declaration of constant may omit value so that the value assignment may be deferred