A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are...http://www.google.com/patents/US7948496?utm_source=gb-gplus-sharePatent US7948496 - Processor architecture with wide operand cache

A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

Images(509)

Claims(30)

1. A processor comprising:

a first data path having a first bit width;

a bus interface unit;

a first cache memory coupled to the first data path and to the bus interface unit;

a second data path having a second bit width greater than the first bit width;

a plurality of third data paths having a combined bit width less than the second bit width;

a first wide operand storage coupled to the first data path and to the second data path for storing a first wide operand received over the first data path, the first wide operand having a size with a number of bits greater than the first bit width;

a register file including registers having the first bit width, the register file being connected to the first data path and the third data paths, and including storage for a wide operand specifier which specifies an address of the first wide operand;

an access unit, including an instruction fetch queue, coupled to the register file;

an execute instruction queue coupled to the access unit and to the first cache memory for presenting to the register file instructions and data; and

a first functional unit capable of initiating instructions, the first functional unit coupled by the second data path to the first wide operand storage and coupled by the third data paths to the register file.

2. A processor as in claim 1 further comprising:

a second wide operand storage coupled to the first data path for storing a second wide operand received over the first data path, the second wide operand having a size with a number of bits greater than the first bit width; and

a second functional unit capable of initiating instructions, the second functional unit coupled by a fourth data path to the second wide operand storage, and coupled by the third data paths to the register file.

3. A processor as in claim 2 further comprising an arbitration unit coupled to the execute instruction queue, the arbitration unit for selecting which instructions are routed to the first functional unit and which instructions are routed to the second functional unit.

4. A processor as in claim 3 wherein the second functional unit comprises a crossbar switch for performing data handling operations on data received from the second wide operand storage.

5. A processor as in claim 4 wherein the crossbar switch is also coupled to the arbitration unit.

6. A processor as in claim 3 wherein the second functional unit comprises a translate unit for performing table look up operations on data received from the second wide operand storage.

7. A processor as in claim 6 wherein the translate unit is also coupled to the arbitration unit.

8. A processor as in claim 3 further comprising a group arithmetic unit coupled to the third data paths and to the arbitration unit, the group arithmetic unit performing group arithmetic operations on operands representing a group of values which are partitioned and operated on separately with results catenated and stored in a results register.

9. A processor as in claim 3 further comprising a group logical unit coupled to the third data paths and to the arbitration unit, the group logical unit performing group logical operations on operands representing a group of values which are partitioned and operated on separately with results catenated and stored in a results register.

10. A processor as in claim 3 wherein the processor is provided on a single integrated circuit and is coupled through the bus interface unit to a data bus, the data bus also being coupled to a main memory.

11. A processor as in claim 10 wherein the data bus is also coupled to a second cache memory.

12. A processor as in claim 2 wherein the first wide operand storage comprises a first memory embedded in the first functional unit, and the second wide operand storage comprises a second memory embedded in the second functional unit.

13. A processor as in claim 2 wherein the first cache memory is shared by the first functional unit and the second functional unit.

14. A processor as claim 2 wherein the first wide operand has a bit width which is at least twice the first bit width.

15. A processor as in claim 2 wherein the first functional unit after execution of an instruction requiring information from the first wide operand storage checks the register file when a subsequent instruction requires a wide operand to determine if the wide operand required is already stored in the first wide operand storage.

16. A processor as in claim 1 wherein the access unit further comprises an access functional unit coupled to the first data path and the third data paths, the access functional unit performing arithmetic instructions, branch instructions, load instructions and store instructions.

17. A processor as in claim 16 wherein the access functional unit produces results for storage in the register file.

19. A processor as in claim 18 wherein the wide operand specifier also includes information about the size of the first wide operand.

20. A processor as in claim 1 wherein data and instructions fetched from the first cache memory are stored in the execute instruction queue before being executed by the first functional unit.

21. A processor comprising:

a first data path having a first bit width;

a second data path having a second bit width greater than the first bit width;

a plurality of third data paths having a combined bit width less than the second bit width;

a first wide operand storage coupled to the first data path and to the second data path for storing a first wide operand received over the first data path, the first wide operand having a size with a number of bits greater than the first bit width;

a first functional unit capable of initiating instructions, the first functional unit coupled by the second data path to the first wide operand storage and coupled by the third data paths to a register file;

a second wide operand storage coupled to the first data path and to the second data path for storing a second wide operand received over the first data path, the second wide operand having a size with a number of bits greater than the first bit width;

a second functional unit capable of initiating instructions, the second functional unit coupled by a fourth data path to the second wide operand storage and coupled by the third data paths to the register file;

the register file including registers having the first bit width, the register file being connected to the first data path and the third data paths, and including storage for at least a first wide operand specifier which specifies an address of the first wide operand, and a second wide operand specifier which specifies an address of the second wide operand;

an arbitration unit coupled to each of the first wide operand storage, the first functional unit, the second wide operand storage, and the second functional unit for selecting which instructions are routed to the first functional unit or the second functional unit.

22. A processor as in claim 21 further comprising a crossbar switch coupled to the arbitration unit and to a third wide operand storage, the crossbar switch performing data handling operations on data stored in the third wide operand storage.

23. A processor as in claim 22 further comprising a translate unit coupled to the arbitration unit and to a fourth wide operand storage, the translate unit for performing table look up operations on data received from the fourth wide operand storage.

24. A processor as in claim 23 further comprising a group arithmetic unit coupled to the third data paths and to the arbitration unit, the group arithmetic unit performing group arithmetic operations on operands representing a group of values which are partitioned and operated on separately with results catenated and stored in a results register.

25. A processor as in claim 24 further comprising a group logical unit coupled to the third data paths and to the arbitration unit, the group logical unit performing group logical operations on operands representing a group of values which are partitioned and operated on separately with results catenated and stored in a results register.

26. A processor as in claim 21 further comprising:

a first execution queue coupled to the arbitration unit;

a first instruction fetch queue coupled to the first execution queue

a second execution queue coupled to the arbitration unit; and

a second instruction fetch queue coupled to the second execution queue.

27. A processor as in claim 26 further comprising a cache memory coupled to each of the first execution queue, the first instruction fetch queue, the second execution queue, and the second instruction fetch queue.

28. A processor as in claim 27 wherein data and instructions fetched from the cache memory are stored in the first and second execution queues before being executed by the first and second functional units.

29. A processor as in claim 21 wherein each of the first wide operand and the second wide operand have bit widths which are at least twice the first bit width.

30. A processor as in claim 21 wherein the first functional unit, in executing an instruction requiring a wide operand, first checks to determine if the wide operand is already stored in the first wide operand storage.

Description

RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 11/346,213 filed Feb. 3, 2006, which is a continuation of U.S. patent application Ser. No. 10/616,303, now U.S. Pat. No. 7,301,541, which is a continuation-in-part of U.S. patent application Ser. No. 09/922,319, filed Aug. 2, 2001, now U.S. Pat. No. 6,725,356 which is a continuation of U.S. patent application Ser. No. 09/382,402, filed Aug. 24, 1999, now U.S. Pat. No. 6,295,599, which claims the benefit of priority to Provisional Application No. 60/097,635 filed on Aug. 24, 1998. Each of the above applications and/or patents are herein incorporated by reference in their entirety.

FIELD OF THE INVENTION

The present invention relates to general purpose processor architectures, and particularly relates to wide operand architectures.

BACKGROUND OF THE INVENTION

Communications products require increased computational performance to process digital signals in software on a real time basis. Increases in performance have come through improvements in process technology and by improvements in microprocessor design. Increased parallelism, higher clock rates, increased densities, coupled with improved design tools and compilers have made this more practical. However, many of these improvements cost additional overhead in memory and latency due to a lack of the necessary bandwidth that is closely coupled to the computational units.

The performance level of a processor, and particularly a general purpose processor, can be estimated from the multiple of a plurality of interdependent factors: clock rate, gates per clock, number of operands, operand and data path width, and operand and data path partitioning. Clock rate is largely influenced by the choice of circuit and logic technology, but is also influenced by the number of gates per clock. Gates per clock is how many gates in a pipeline may change state in a single clock cycle. This can be reduced by inserting latches into the data path: when the number of gates between latches is reduced, a higher clock is possible. However, the additional latches produce a longer pipeline length, and thus come at a cost of increased instruction latency. The number of operands is straightforward; for example, by adding with carry-save techniques, three values may be added together with little more delay than is required for adding two values. Operand and data path width defines how much data can be processed at once; wider data paths can perform more complex functions, but generally this comes at a higher implementation cost. Operand and data path partitioning refers to the efficient use of the data path as width is increased, with the objective of maintaining substantially peak usage.

The last factor, operand and data path partitioning, is treated extensively in commonly-assigned U.S. Pat. Nos. 5,742,840, 5,794,060, 5,794,061, 5,809,321, and 5,822,603, herein incorporated by reference in their entirety, which describe systems and methods for enhancing the utilization of a general purpose processor by adding classes of instructions. These classes of instructions use the contents of general purpose registers as data path sources, partition the operands into symbols of a specified size, perform operations in parallel, catenate the results and place the catenated results into a general-purpose register. These patents, all of which are assigned to the same assignee as the present invention, teach a general purpose microprocessor which has been optimized for processing and transmitting media data streams through significant parallelism.

While the foregoing patents offered significant improvements in utilization and performance of a general purpose microprocessor, particularly for handling broadband communications such as media data streams, other improvements are possible.

Many general purpose processors have general registers to store operands for instructions, with the register width matched to the size of the data path. Processor designs generally limit the number of accessible registers per instruction because the hardware to access these registers is relatively expensive in power and area. While the number of accessible registers varies among processor designs, it is often limited to two, three or four registers per instruction when such instructions are designed to operate in a single processor clock cycle or a single pipeline flow. Some processors, such as the Motorola 68000 have instructions to save and restore an unlimited number of registers, but require multiple cycles to perform such an instruction.

The Motorola 68000 also attempts to overcome a narrow data path combined with a narrow register file by taking multiple cycles or pipeline flows to perform an instruction, and thus emulating a wider data path. However, such multiple precision techniques offer only marginal improvement in view of the additional clock cycles required. The width and accessible number of the general purpose registers thus fundamentally limits the amount of processing that can be performed by a single instruction in a register-based machine.

Existing processors may provide instructions that accept operands for which one or more operands are read from a general purpose processor's memory system. However, as these memory operands are generally specified by register operands, and the memory system data path is no wider than the processor data path, the width and accessible number of general purpose operands per instruction per cycle or pipeline flow is not enhanced.

The number of general purpose register operands accessible per instruction is generally limited by logical complexity and instruction size. For example, it might be possible to implement certain desirable but complex functions by specifying a large number of general purpose registers, but substantial additional logic would have to be added to a conventional design to permit simultaneous reading and bypassing of the register values. While dedicated registers have been used in some prior art designs to increase the number or size of source operands or results, explicit instructions load or store values into these dedicated registers, and additional instructions are required to save and restore these registers upon a change of processor context.

The size of an execution unit result may be constrained to that of a general register so that no dedicated or other special storage is required for the result. Specifying a large number of general purpose registers as a result would similarly require substantial additional logic to be added to a conventional design to permit simultaneous writing and bypassing of the register values.

When the size of an execution unit result is constrained, it can limit the amount of computation which can reasonably be handled by a single instruction. As a consequence, algorithms must be implemented in a series of single instruction steps in which all intermediate results can be represented within the constraints. By eliminating this constraint, instruction sets can be developed in which a larger component of an algorithm is implemented as a single instruction, and the representation of intermediate results are no longer limited in size. Further, some of these intermediate results are not required to be retained upon completion of the larger component of an algorithm, so a processor freed of these constraints can improve performance and reduce operating power by not storing and retrieving these results from the general register file. When the intermediate results are not retained in the general register file, processor instruction sets and implemented algorithms are also not constrained by the size of the general register file.

There has therefore been a need for a processor system capable of efficient handling of operands and results of greater width than either the memory system or any accessible general purpose register. There is also a need for a processor system capable of efficient handling of operands and results of greater overall size than the entire general register file.

SUMMARY OF THE INVENTION

Commonly-assigned and related U.S. Pat. No. 6,295,599, describes in detail a method and system for improving the performance of general-purpose processors by expanding at least one source operand to a width greater than the width of either the general purpose register or the data path width. Further improvements in performance may be achieved by allowing a plurality of source operands to be expanded to a greater width than either the memory system or any accessible general purpose register, and by allowing the at least one result operand to be expanded to a greater width than either the memory system or any accessible general purpose register.

The present invention provides a system and method for improving the performance of general purpose processors by expanding at least one source operand or at least one result operand to a width greater than the width of either the general purpose register or the data path width. In addition, several classes of instructions will be provided which cannot be performed efficiently if the source operands or the at least one result operand are limited to the width and accessible number of general purpose registers.

In the present invention, source and result operands are provided which are substantially larger than the data path width of the processor. This is achieved, in part, by using a general purpose register to specify at least one memory address from which at least more than one, but typically several data path widths of data can be read. To permit such a wide operand to be performed in a single cycle, a data path functional unit is augmented with dedicated storage to which the memory operand is copied on an initial execution of the instruction. Further execution of the instruction or other similar instructions that specify the same memory address can read the dedicated storage to obtain the operand value. However, such reads are subject to conditions to verify that the memory operand has not been altered by intervening instructions. If the memory operand remains current—that is, the conditions are met—the memory operand fetch can be combined with one or more register operands in the functional unit, producing a result. The size of the result may be constrained to that of a general register so that no dedicated or other special storage is required for the result. The size of the result for additional instructions may not be so constrained, and so utilize dedicated storage to which the result operand is placed on execution of the instruction. The dedicated storage may be implemented in a local memory tightly coupled to the logic circuits that comprise the functional unit.

The present invention extends the previous embodiments to include methods and apparatus for performing operations that both receive operands from wide embedded memories and also deposit results in wide embedded memories. The present invention includes operations that autonomously read and update the wide embedded memories in multiple successive cycles of access and computation. The present invention also describes operations that employ simultaneously two or more independently addressed wide embedded memories.

Another aspect of the present invention addresses efficient usage of a multiplier array that is fully used for high precision arithmetic, but is only partly used for other, lower precision operations. This can be accomplished by extracting the high-order portion of the multiplier product or sum of products, adjusted by a dynamic shift amount from a general register or an adjustment specified as part of the instruction, and rounded by a control value from a register or instruction portion. The rounding may be any of several types, including round-to-nearest/even, toward zero, floor, or ceiling. Overflows are typically handled by limiting the result to the largest and smallest values that can be accurately represented in the output result.

When an extract is controlled by a register, the size of the result can be specified, allowing rounding and limiting to a smaller number of bits than can fit in the result. This permits the result to be scaled for use in subsequent operations without concern of overflow or rounding. As a result, performance is enhanced. In those instances where the extract is controlled by a register, a single register value defines the size of the operands, the shift amount and size of the result, and the rounding control. By placing such control information in a single register, the size of the instruction is reduced over the number of bits that such an instruction would otherwise require, again improving performance and enhancing processor flexibility. Exemplary instructions are Ensemble Convolve Extract, Ensemble Multiply Extract, Ensemble Multiply Add Extract, and Ensemble Scale Add Extract. With particular regard to the Ensemble Scale Add Extract Instruction, the extract control information is combined in a register with two values used as scalar multipliers to the contents of two vector multiplicands. This combination reduces the number of registers otherwise required, thus reducing the number of bits required for the instruction.

A method of performing a computation in a programmable processor, the programmable processor having a first memory system having a first data path width, and a second memory system and a third memory system each of the second memory system and the third memory system having a data path width which is greater than the first data path width, may comprise the steps of: copying a first memory operand portion from the first memory system to the second memory system, the first memory operand portion having the first data path width; copying a second memory operand portion from the first memory system to the second memory system, the second memory operand portion having the first data path width and being catenated in the second memory system with the first memory operand portion, thereby forming first catenated data; copying a third memory operand portion from the first memory system to the third memory system, the third memory operand portion having the first data path width; copying a fourth memory operand portion from the first memory system to the third memory system, the fourth memory operand portion having the first data path width and being catenated in the third memory system with the third memory operand portion, thereby forming second catenated data; and performing a computation of a single instruction using the first catenated data and the second catenated data.

In the method of performing a computation in a programmable processor, the step of performing a computation may further comprise reading a portion of the first catenated data and a portion of the second catenated data each of which is greater in width than the first data path width and using the portion of the first catenated data and the portion of the second catenated data to perform the computation.

The method of performing a computation in a programmable processor may further comprise the step of specifying a memory address of each of the first catenated data and of the second catenated data within the first memory system.

The method of performing a computation in a programmable processor may further comprise the step of specifying a memory operand size and a memory operand shape of each of the first catenated data and the second catenated data.

The method of performing a computation in a programmable processor may further comprise the step of checking the validity of each of the first catenated data in the second memory system and the second catenated data in the third memory system, and, if valid, permitting a subsequent instruction to use the first and second catenated data without copying from the first memory system.

The method of performing a computation in a programmable processor may further comprise performing a transform of partitioned elements contained in the first catenated data using coefficients contained in the second catenated data, thereby forming a transform data, extracting a specified subfield of the transform data, thereby forming an extracted data and catenating the extracted data.

An alternative method of performing a computation in a programmable processor, the programmable processor having a first memory system having a first data path width, and a second and a third memory system having a data path width which is greater than the first data path width, may comprising the steps of: copying a first memory operand portion from the first memory system to the second memory system, the first memory operand portion having the first data path width; copying a second memory operand portion from the first memory system to the second memory system, the second memory operand portion having the first data path width and being catenated in the second memory system with the first memory operand portion, thereby forming first catenated data; performing a computation of a single instruction using the first catenated data and producing a second catenated data; copying a third memory operand portion from the third memory system to the first memory system, the third memory operand portion having the first data path width and containing a portion of the second catenated data; and copying a fourth memory operand portion from the third memory system to the first memory system, the fourth memory operand portion having the first data path width and containing a portion of the second catenated data, wherein the fourth memory operand portion is catenated in the third memory system with the third memory operand portion.

In the alternative method of performing a computation in a programmable processor the step of performing a computation may further comprise the step of reading a portion of the first catenated data which is greater in width than the first data path width and using the portion of the first catenated data to perform the computation.

The alternative method of performing a computation in a programmable processor may further comprise the step of specifying a memory address of each of the first catenated data and of the second catenated data within the first memory system.

The alternative method of performing a computation in a programmable processor may further comprise the step of specifying a memory operand size and a memory operand shape of each of the first catenated data and the second catenated data.

The alternative method of performing a computation in a programmable processor may further comprise the step of checking the validity of each of the first catenated data in the second memory system and the second catenated data in the third memory system, and, if valid, permitting a subsequent instruction to use the first catenated data without copying from the first memory system.

In the alternative method of performing a computation, the step of performing a computation may further comprise the step of performing a transform of partitioned elements contained in the first catenated data, thereby forming a transform data, extracting a specified subfield of the transform data, thereby forming an extracted data and catenating the extracted data, forming the second catenated data.

In the alternative method of performing a computation, the step of performing a computation may further comprise the step of combining using Boolean arithmetic a portion of the extracted data with an accumulated Boolean data, combining partitioned elements of the accumulated Boolean data using Boolean arithmetic, forming combined Boolean data, determining the most significant bit of the extracted data from the combined Boolean data, and returning a result comprising the position of the most significant bit to a register.

The alternative method of performing a computation in a programmable processor may further comprise manipulating a first and a second validity information corresponding to first and second catenated data, wherein after completion of an instruction specifying a memory address of first catenated data, the contents of second catenated data are provided to the first memory system in place of first catenated data.

A programmable processor according to the present invention may comprise: a first memory system having a first data path width; a second memory system and a third memory system, wherein each of the second memory system and the third memory system have a data path width which is greater than the first data path width; a first copying module configured to copy a first memory operand portion from the first memory system to the second memory system, the first memory operand portion having the first data path width, and configured to copy a second memory operand portion from the first memory system to the second memory system, the second memory operand portion having the first data path width and being catenated in the second memory system with the first memory operand portion, thereby forming first catenated data; a second copying module configured to copy a third memory operand portion from the first memory system to the third memory system, the third memory operand portion having the first data path width, and configured to copy a fourth memory operand portion from the first memory system to the third memory system, the fourth memory operand portion having the first data path width and being catenated in the third memory system with the third memory operand portion, thereby forming second catenated data; and a functional unit configured to perform computations using the first catenated data and the second catenated data.

In the programmable processor, the functional unit may be further configured to read a portion of each of the first catenated data and the second catenated data which is greater in width than the first data path width and use the portion of each of the first catenated data and the second catenated data to perform the computation.

In the programmable processor, the functional unit may be further configured to specify a memory address of each of the first catenated data and of the second catenated data within the first memory system.

In the programmable processor, the functional unit may be further configured to specify a memory operand size and a memory operand shape of each of the first catenated data and the second catenated data.

The programmable processor may further comprise a control unit configured to check the validity of each of the first catenated data in the second memory system and the second catenated data in the third memory system, and, if valid, permitting a subsequent instruction to use each of the first catenated data and the second catenated data without copying from the first memory system.

In the programmable processor, the functional unit may be further configured to convolve partitioned elements contained in the first catenated data with partitioned elements contained in the second catenated data, forming a convolution data, extract a specified subfield of the convolution data and catenate extracted data, forming a catenated result having a size equal to that of the functional unit data path width.

In the programmable processor, the functional unit may be further configured to perform a transform of partitioned elements contained in the first catenated data using coefficients contained in the second catenated data, thereby forming a transform data, extract a specified subfield of the transform data, thereby forming an extracted data and catenate the extracted data.

An alternative programmable processor according to the present invention may comprise: a first memory system having a first data path width; a second memory system and a third memory system each of the second memory system and the third memory system having a data path width which is greater than the first data path width; a first copying module configured to copy a first memory operand portion from the first memory system to the second memory system, the first memory operand portion having the first data path width, and configured to copy a second memory operand portion from the first memory system to the second memory system, the second memory operand portion having the first data path width and being catenated in the second memory system with the first memory operand portion, thereby forming first catenated data; a second copying module configured to copy a third memory operand portion from the third memory system to the first memory system, the third memory operand portion having the first data path width and containing a portion of a second catenated data, and copy a fourth memory operand portion from the third memory system to the first memory system, the fourth memory operand portion having the first data path width and containing a portion of the second catenated data, wherein the fourth memory operand portion is catenated in the third memory system with the third memory operand portion; and a functional unit configured to perform computations using the first catenated data and the second catenated data.

In the alternative programmable processor the functional unit may be further configured to read a portion of the first catenated data which is greater in width than the first data path width and use the portion of the first catenated data to perform the computation.

In the alternative programmable processor the functional unit may be further configured to specify a memory address of each of the first catenated data and of the second catenated data within the first memory system.

In the alternative programmable processor the functional unit may be further configured to specify a memory operand size and a memory operand shape of each of the first catenated data and the second catenated data.

The alternative programmable processor may further comprise a control unit configured to check the validity of the first catenated data in the second memory system, and, if valid, permitting a subsequent instruction to use the first catenated data without copying from the first memory system.

In the alternative programmable processor the functional unit may be further configured to transform partitioned elements contained in the first catenated data, thereby forming a transform data, extract a specified subfield of the transform data, thereby forming an extracted data and catenate the extracted data, forming the second catenated data.

In the alternative programmable processor the functional unit may be further configured to combine using Boolean arithmetic a portion of the extracted data with an accumulated Boolean data, combine partitioned elements of the accumulated Boolean data using Boolean arithmetic, forming combined Boolean data, determine the most significant bit of the extracted data from the combined Boolean data, and provide a result comprising the position of the most significant bit.

The alternative programmable processor may further comprise a control unit configured to manipulate a first and a second validity information corresponding to first and second catenated data, wherein after completion of an instruction specifying a memory address of first catenated data, the contents of second catenated data are provided to the first memory system in place of first catenated data.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a system level diagram showing the functional blocks of a system in accordance with an exemplary embodiment of the present invention.

FIG. 2 is a matrix representation of a wide matrix multiply in accordance with an exemplary embodiment of the present invention.

FIG. 3 is a further representation of a wide matrix multiple in accordance with an exemplary embodiment of the present invention.

FIG. 4 is a system level diagram showing the functional blocks of a system incorporating a combined Simultaneous Multi Threading and Decoupled Access from Execution processor in accordance with an exemplary embodiment of the present invention.

FIG. 5 illustrates a wide operand in accordance with an exemplary embodiment of the present invention.

FIG. 6 illustrates an approach to specifier decoding in accordance with an exemplary embodiment of the present invention.

FIG. 7 illustrates in operational block form a Wide Function Unit in accordance with an exemplary embodiment of the present invention.

FIG. 8 illustrates in flow diagram form the Wide Microcache control function in accordance with an exemplary embodiment of the present invention.

FIG. 100 is a block diagram showing the organization of the memory management system in accordance with an exemplary embodiment of the present invention.

FIG. 101 illustrates a pipeline organization in accordance with an exemplary embodiment of the present invention.

FIG. 102 is a system-level diagram showing a memory pipeline in accordance with an exemplary embodiment of the present invention.

FIG. 103 illustrates an expected rate at which memory requests are serviced in accordance with an exemplary embodiment of the present invention.

FIG. 104 illustrates an expected rate at which memory requests are serviced in accordance with an exemplary embodiment of the present invention.

FIG. 105 is a pinout diagram in accordance with an exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Introduction

In various embodiments of the invention, a computer processor architecture, referred to here as Micro Unity's Zeus Architecture is presented. MicroUnity's Zeus Architecture describes general-purpose processor, memory, and interface subsystems, organized to operate at the enormously high bandwidth rates required for broadband applications.

The Zeus processor performs integer, floating point, signal processing and non-linear operations such as Galois field, table lookup and bit switching on data sizes from 1 bit to 128 bits. Group or SIMD (single instruction multiple data) operations sustain external operand bandwidth rates up to 512 bits (i.e., up to four 128-bit operand groups) per instruction even on data items of small size. The processor performs ensemble operations such as convolution that maintain full intermediate precision with aggregate internal operand bandwidth rates up to 20,000 bits per instruction. The processor performs wide operations such as crossbar switch, matrix multiply and table lookup that use caches embedded in the execution units themselves to extend operands to as much as 32768 bits. All instructions produce at most a single 128-bit general register result, source at most three 128-bit general registers and are free of side effects such as the setting of condition codes and flags. The instruction set design carries the concept of streamlining beyond Reduced Instruction Set Computer (RISC) architectures, to simplify implementations that issue several instructions per machine cycle.

The Zeus memory subsystem provides 64-bit virtual and physical addressing for UNIX, Mach, and other advanced OS environments. Separate address instructions enable the division of the processor into decoupled access and execution units, to reduce the effective latency of memory to the pipeline. The Zeus cache supplies the high data and instruction issue rates of the processor, and supports coherency primitives for scaleable multiprocessors. The memory subsystem includes mechanisms for sustaining high data rates not only in block transfer modes, but also in non-unit stride and scatterred access patterns.

The Zeus interface subsystem is designed to match industry-standard protocols and pin-outs. In this way, Zeus can make use of existing infrastructure for building low-cost systems. The interface subsystem is modular, and can be replaced with appropriate protocols and pin-outs for lower-cost and higher-performance systems.

The goal of the Zeus architecture is to integrate these processor, memory, and interface capabilities with optimal simplicity and generality. From the software perspective, the entire machine state consists of a program counter, a single bank of 64 general-purpose 128-bit general registers, and a linear byte-addressed shared memory space with mapped interface registers. All interrupts and exceptions are precise, and occur with low overhead.

Examples discussed herein are intended for Zeus software and hardware developers alike, and defines the interface at which their designs must meet. Zeus pursues the most efficient tradeoffs between hardware and software complexity by making all processor, memory, and interface resources directly accessible to high-level language programs.

Common Elements

Notation

The descriptive notation used in this document is summarized in the table below:

x + y

two's complement addition of x and y. Result is the same size as

the operands, and operands must be of equal size.

x − y

two's complement subtraction of y from x. Result is the same

size as the operands, and operands must be of equal size.

x * y

two's complement multiplication of x and y. Result is the same

size as the operands, and operands must be of equal size.

x/y

two's complement division of x by y. Result is the same size as

the operands, and operands must be of equal size.

x & y

bitwise and of x and y. Result is same size as the operands, and

operands must be of equal size.

x|y

bitwise or of x and y. Result is same size as the operands, and

operands must be of equal size.

x {circumflex over ( )} y

bitwise exclusive-

of x and y. Result is same size as the

operands, and operands must be of equal size.

~x

bitwise inversion of x. Result is same size as the operand.

x = y

two's complement equality comparison between x and y. Result

is a single bit, and operands must be of equal size.

x ≠ y

two's complement inequality comparison between x and y.

Result is a single bit, and operands must be of equal size.

x < y

two's complement less than comparison between x and y. Result

is a single bit, and operands must be of equal size.

x ≧ y

two's complement greater than or equal comparison between x

and y. Result is a single bit, and operands must be of equal size.

{square root over (x)}

floating-point square root of x

x || y

concatenation of bit field x to left of bit field y

xy

binary digit x repeated, concatenated y times. Size of result is y.

xy

extraction of bit y (using little-endian bit numbering) from value

x. Result is a single bit.

xy..z

extraction of bit field formed from bits y through z of value x.

Size of result is y − z + 1; if z > y, result is an empty string,

x?y:z

value of y, if x is true, otherwise value of z. Value of x is a

single bit.

x □ y

bitwise assignment of x to value of y

Sn

signed, two's complement, binary data format of n bytes

Un

unsigned binary data format of n bytes

Fn

floating-point data format of n bytes

Bit Ordering

The ordering of bits in this document is always little-endian, regardless of the ordering of bytes within larger data structures. Thus, the least-significant bit of a data structure is always labeled 0 (zero), and the most-significant bit is labeled as the data structure size (in bits) minus one.

Memory

Zeus memory is an array of 264 bytes, without a specified byte ordering, which is physically distributed among various components.

Byte

A byte is a single element of the memory array, consisting of 8 bits:

Byte Ordering

Larger data structures are constructed from the concatenation of bytes in either little-endian or big-endian byte ordering. A memory access of a data structure of size s at address i is formed from memory bytes at addresses i through i+s−1. Unless otherwise specified, there is no specific requirement of alignment: it is not generally required that i be a multiple of s. Aligned accesses are preferred whenever possible, however, as they will often require one fewer processor or memory clock cycle than unaligned accesses.

With little-endian byte ordering, the bytes are arranged as:

With big-endian byte ordering, the bytes are arranged as:

Zeus memory is byte-addressed, using either little-endian or big-endian byte ordering. For consistency with the bit ordering, and for compatibility with x86 processors, Zeus uses little-endian byte ordering when an ordering must be selected. Zeus load and store instructions are available for both little-endian and big-endian byte ordering. The selection of byte ordering is dynamic, so that little-endian and big-endian processes, and even data structures within a process, can be intermixed on the processor.

Memory Read/Load Semantics

Zeus memory, including memory-mapped registers, must conform to the following requirements regarding side-effects of read or load operations:

A memory read must have no side-effects on the contents of the addressed memory nor on the contents of any other memory.

Memory Write/Store Semantics

Zeus memory, including memory-mapped registers, must conform to the following requirements regarding side-effects of read or load operations:

A memory write must affect the contents of the addressed memory so that a memory read of the addressed memory returns the value written, and so that a memory read of a portion of the addressed memory returns the appropriate portion of the value written.

A memory write may affect or cause side-effects on the contents of memory not addressed by the write operation, however, a second memory write of the same value to the same address must have no side-effects on any memory; memory write operations must be idempotent.

Zeus store instructions that are weakly ordered may have side-effects on the contents of memory not addressed by the store itself; subsequent load instructions which are also weakly ordered may or may not return values which reflect the side-effects.

Quiet NaN values are denoted by any sign bit value, an exponent field of all one bits, and a non-zero fraction with the most significant bit set. Quiet NaN values generated by default exception handling of standard operations have a zero sign bit, an exponent field of all one bits, a fraction field with the most significant bit set, and all other bits cleared.

Signaling NaN values are denoted by any sign bit value, an exponent field of all one bits, and a non-zero fraction with the most significant bit cleared.

Infinite values are denoted by any sign bit value, an exponent field of all one bits, and a zero fraction field.

Normalized number values are denoted by any sign bit value, an exponent field that is not all one bits or all zero bits, and any fraction field value. The numeric value encoded is (−1)^s2^e-bias(1.f). The bias is equal the value resulting from setting all but the most significant bit of the exponent field, half: 15, single: 127, double: 1023, and quad: 16383.

Denormalized number values are denoted by any sign bit value, an exponent field that is all zero bits, and a non-zero fraction field value. The numeric value encoded is (−1)^s2^1-bias(0.f).

Zero values are denoted by any sign bit value, and exponent field that is all zero bits, and a fraction field that is all zero bits. The numeric value encoded is (−1)^s0. The distinction between +0 and −0 is significant in some operations.

Half-Precision Floating-Point

Zeus half precision uses a format similar to standard 754's requirements, reduced to a 16-bit overall format. The format contains sufficient precision and exponent range to hold a 12-bit signed integer.

Zeus instructions include operations on pairs of data values that represent complex numerical values of the form (a+b i). When contained in general registers, the paired values are always arranged with the real part (a) in a less-significant location (to the right) and the imaginary part (b i) in a more-significant location (to the left).

When these paired values are contained in memory, a little-endian load or store transfers these values to memory in a form where the real part is at a lower address and the imaginary part is at a higher address. A big-endian load or store transfers these values to memory in a form where the real part is at a higher address and the imaginary part is at a lower address, which is different from the little-endian case and may be considered unusual.

The ordering of real and imaginary parts is usually of no consequence when performing addition or subtraction operations, and in fact, the Zeus instruction set has no special facilities for addition or subtraction of complex data. If the arrangement of real and imaginary parts does not match the desired format in memory, an X.SWIZZLE instruction can swap the positions of the real and imaginary values in a general register for the operands and the results.

A shortcut for a complex multiply operation can be observed: if the position of the real and imaginary parts are reversed in both operands, the result that is computed will have the imaginary part of the result to the left (more significant) and the negative of the real part to the right (less significant). A G.XOR can invert the sign bit (for complex floating-point), or the real part of the result (for complex integer). For the complex integer a G.ADD then transforms the ones-complement to a twos-complement. An X.SWIZZLE instruction can swap the result into the reversed order matching the operand order. The results transformed by the above is then in condition to be written back to memory in the reversed fashion.

Zeus instructions have no direct support for complex values in a polar (r, θ) representation.

Additional devices and interfaces, not covered by this standard may be added in specified regions of the physical memory space, provided that system reset places these devices and interfaces in an inactive state that does not interfere with the operation of software that runs in any conformant system. The software interface requirements of any such additional devices and interfaces must be made as widely available as this architecture specification.

Unrestricted Physical Implementation

Nothing in this specification should be construed to limit the implementation choices of the conforming system beyond the specific requirements stated herein. In particular, a computer system may conform to the Zeus System Architecture while employing any number of components, dissipate any amount of heat, require any special environmental facilities, or be of any physical size.

Zeus Processor

MicroUnity's Zeus processor provides the general-purpose, high-bandwidth computation capability of the Zeus system. Zeus includes high-bandwidth data paths, general register files, and a memory hierarchy. Zeus's memory hierarchy includes on-chip instruction and data memories, instruction and data caches, a virtual memory facility, and interfaces to external devices. Zeus's interfaces in the initial implementation are solely the “Super Socket 7” bus, but other implementations may have different or additional interfaces.

Architectural Framework

The Zeus architecture defines a compatible framework for a family of implementations with a range of capabilities. The following implementation-defined parameters are used in the rest of the document in boldface. The value indicated is for one implementation.

Parameter

Interpretation

Value

Range of legal values

T

number of execution threads

4

1 ≦ T ≦ 31

CE

log2 cache blocks in first-level

9

0 ≦ CE ≦ 31

cache

CS

log2 cache blocks in first-level

2

0 ≦ CS ≦ 4

cache set

CT

existence of dedicated tags

1

0 ≦ CT ≦ 1

in first-level cache

LE

log2 entries in local TB

0

0 ≦ LE ≦ 3

LB

Local TB based on base

1

0 ≦ LB ≦ 1

register

GE

log2 entries in global TB

7

0 ≦ GE ≦ 15

GT

log2 threads which share a

1

0 ≦ GT ≦ 3

global TB

Interfaces and Block Diagram

The first implementation of Zeus uses “socket 7” protocols and pinouts.

Instruction

Assembler Syntax

Instructions are specified to Zeus assemblers and other code tools (assemblers) in the syntax of an instruction mnemonic (operation code), then optionally white space (blanks or tabs) followed by a list of operands.

The instruction mnemonics listed in this specification are in upper case (capital) letters, assemblers accept either upper case or lower case letters in the instruction mnemonics. In this specification, instruction mnemonics contain periods (“.”) to separate elements to make them easier to understand; assemblers ignore periods within instruction mnemonics. The instruction mnemonics are designed to be parsed uniquely without the separating periods.

If the instruction produces a general register result, this operand is listed first. Following this operand, if there are one or more source operands, is a separator which may be a comma (“,”), equal (“=”), or at-sign (“@”). The equal separates the result operand from the source operands, and may optionally be expressed as a comma in assembler code. The at-sign indicates that the result operand is also a source operand, and may optionally be expressed as a comma in assembler code. If the instruction specification has an equal-sign, an at-sign in assembler code indicates that the result operand should be repeated as the first source operand (for example, “A.ADD.I r4@5” is equivalent to “A.ADD.I r4=r4,5”). Commas always separate the remaining source operands.

The result and source operands are case-sensitive; upper case and lower case letters are distinct. General register operands are specified by the names r0 (or r00) through r63 (a lower case “r” immediately followed by a one or two digit number from 0 to 63), or by the special designations of “lp” for “r0,” “dp” for “r1,” “fp” for “r62,” and “sp” for “r63.” Integer-valued operands are specified by an optional sign (−) or (+) followed by a number, and assemblers generally accept a variety of integer-valued expressions.

Instruction Structure

A Zeus instruction is specifically defined as a four-byte structure with the little-endian ordering shown below. It is different from the quadlet defined above because the placement of instructions into memory must be independent of the byte ordering used for data structures. Instructions must be aligned on four-byte boundaries; in the diagram below, i must be a multiple of 4.

Gateway

A Zeus gateway is specifically defined as an 8-byte structure with the little-endian ordering shown below. A gateway contains a code address used to securely invoke a system call or procedure at a higher privilege level. Gateways are marked by protection information specified in the TB. Gateways must be aligned on 8-byte boundaries; in the diagram below, i must be a multiple of 8.

The gateway contains two data items within its structure, a code address and a new privilege level:

The virtual memory system can be used to designate a region of memory as containing gateways. Other data may be placed within the gateway region, provided that if an attempt is made to use the additional data as a gateway, that security cannot be violated. For example, 64-bit data or stack pointers which are aligned to at least 4 bytes and are in little-endian byte order have pl=0, so that the privilege level cannot be raised by attempting to use the additional data as a gateway.

User State

The user state consists of hardware data structures that are accessible to all conventional compiled code. The Zeus user state is designed to be as regular as possible, and consists only of the general registers, the program counter, and virtual memory. There are no specialized registers for condition codes, operating modes, rounding modes, integer multiply/divide, or floating-point values.

General Registers

Zeus user state includes 64 general registers. All are identical; there is no dedicated zero-valued general register, and there are no dedicated floating-point general registers.

Some Zeus instructions have 32-bit or 64-bit general register operands. These operands are sign-extended to 128 bits when written to the general register file, and the low-order bits are chosen when read from the general register file.

Definition

def val ← RegRead(rn, size)

val ← REG[rn]size-1..0

enddef

def RegWrite(rn, size, val)

REG[rn] ← valsize-1128-size || valsize-1..0

enddef

Program Counter

The program counter contains the address of the currently executing instruction. This register is implicitly manipulated by branch instructions, and read by branch instructions that save a return address in a general register.

Privilege Level

The privilege level register contains the privilege level of the currently executing instruction. This register is implicitly manipulated by branch gateway and branch down instructions, and read by branch gateway instructions that save a return address in a general register.

Program Counter and Privilege Level

The program counter and privilege level may be packed into a single octlet. This combined data structure is saved by the Branch Gateway instruction and restored by the Branch Down instruction.

System State

The system state consists of the facilities not normally used by conventional compiled code. These facilities provide mechanisms to execute such code in a fully virtual environment. All system state is memory mapped, so that it can be manipulated by compiled code.

Fixed-Point

Zeus provides load and store instructions to move data between memory and the general registers, branch instructions to compare the contents of general registers and to transfer control from one code address to another, and arithmetic operations to perform computation on the contents of general registers, returning the result to general registers.

Load and Store

The load and store instructions move data between memory and the general registers. When loading data from memory into a general register, values are zero-extended or sign-extended to fill the general register. When storing data from a general register into memory, values are truncated on the left to fit the specified memory region.

Load and store instructions that specify a memory region of more than one byte may use either little-endian or big-endian byte ordering: the size and ordering are explicitly specified in the instruction. Regions larger than one byte may be either aligned to addresses that are an even multiple of the size of the region or of unspecified alignment: alignment checking is also explicitly specified in the instruction.

Load and store instructions specify memory addresses as the sum of a base general register and the product of the size of the memory region and either an immediate value or another general register. Scaling maximizes the memory space which can be reached by immediate offsets from a single base general register, and assists in generating memory addresses within iterative loops. Alignment of the address can be reduced to checking the alignment of the first general register.

The load and store instructions are used for fixed-point data as well as floating-point and digital signal processing data; Zeus has a single bank of general registers for all data types.

Swap instructions provide multithread and multiprocessor synchronization, using indivisible operations: add-swap, compare-swap, multiplex-swap, and double-compare-swap. A store-multiplex operation provides the ability to indivisibly write to a portion of an octlet. These instructions always operate on aligned octlet data, using either little-endian or big-endian byte ordering.

Branch

The fixed-point compare-and-branch instructions provide all arithmetic tests for equality and inequality of signed and unsigned fixed-point values. Tests are performed either between two operands contained in general registers, or on the bitwise and of two operands. Depending on the result of the compare, either a branch is taken, or not taken. A taken branch causes an immediate transfer of the program counter to the target of the branch, specified by a 12-bit signed offset from the location of the branch instruction. A non-taken branch causes no transfer; execution continues with the following instruction.

Other branch instructions provide for unconditional transfer of control to addresses too distant to be reached by a 12-bit offset, and to transfer to a target while placing the location following the branch into a general register. The branch through gateway instruction provides a secure means to access code at a higher privilege level, in a form similar to a normal procedure call.

Addressing Operations

A subset of general fixed-point arithmetic operations is available as addressing operations. These include add, subtract, Boolean, and simple shift operations. These addressing operations may be performed at a point in the Zeus processor pipeline so that they may be completed prior to or in conjunction with the execution of load and store operations in a “superspring” pipeline in which other arithmetic operations are deferred until the completion of load and store operations.

Execution Operations

Many of the operations used for Digital Signal Processing (DSP), which are described in greater detail below, are also used for performing simple scalar operations. These operations perform arithmetic operations on values of 8-, 16-, 32-, 64-, or 128-bit sizes, which are right-aligned in general registers. These execution operations include the add, subtract, boolean and simple shift operations which are also available as addressing operations, but further extend the available set to include three-operand add/subtract, three-operand boolean, dynamic shifts, and bit-field operations.

Floating-Point

Zeus provides all the facilities mandated and recommended by ANSI/IEEE standard 754-1985: Binary Floating-point Arithmetic, with the use of supporting software.

Branch Conditionally

The floating-point compare-and-branch instructions provide all the comparison types required and suggested by the IEEE floating-point standard. These floating-point comparisons augment the usual types of numeric value comparisons with special handling for NaN (not-a-number) values. A NaN value compares as “unordered” with respect to any other value, even that of an identical NaN value.

Zeus floating-point compare-branch instructions do not generate an exception on comparisons involving quiet or signaling NaN values. If such exceptions are desired, they can be obtained by combining the use of a floating-point compare-set instruction, with either a floating-point compare-branch instruction on the floating-point operands or a fixed-point compare-branch on the set result.

Because the less and greater relations are anti-commutative, one of each relation that differs from another only by the replacement of an L with a G in the code can be removed by reversing the order of the operands and using the other code. Thus, an L relation can be used in place of a G relation by swapping the operands to the compare-branch or compare-set instruction.

No instructions are provided that branch when the values are unordered. To accomplish such an operation, use the reverse condition to branch over an immediately following unconditional branch, or in the case of an if-then-else clause, reverse the clauses and use the reverse condition.

The E relation can be used to determine the unordered condition of a single operand by comparing the operand with itself.

The following floating-point compare-branch relations are provided as instructions:

The operations explicitly specify the precision of the operation, and round the result (or check that the result is exact) to the specified precision at the conclusion of each operation. Each of the basic operations splits operand general registers into symbols of the specified precision and performs the same operation on corresponding symbols.

In addition to the basic operations, Zeus performs a variety of operations in which one or more products are summed to each other and/or to an additional operand. The instructions include a fused multiply-add (E.MUL.ADD.F), convolve (E.CON.F), matrix multiply (E.MUL.MAT.F), and scale-add (E.SCAL.ADD.F).

The results of these operations are computed as if the multiplies are performed to infinite precision, added as if in infinite precision, then rounded only once. Consequently, these operations perform these operations with no rounding of intermediate results that would have limited the accuracy of the result.

Rounding and Exceptions

Rounding is specified within the instructions explicitly, to avoid explicit state registers for a rounding mode. Similarly, the instructions explicitly specify how standard exceptions (invalid operation, division by zero, overflow, underflow and inexact) are to be handled (U.S. Pat. No. 5,812,439 describes this “Technique of incorporating floating point information into processor instructions.”).

When no rounding is explicitly named by the instruction (default), round to nearest rounding is performed, and all floating-point exception signals cause the standard-specified default result, rather than a trap. When rounding is explicity named by the instruction (N: nearest, Z: zero, F: floor, C: ceiling), the specified rounding is performed, and floating-point exception signals other than inexact cause a floating-point exception trap. When X (exact, or exception) is specified, all floating-point exception signals cause a floating-point exception trap, including inexact.

This technique assists the Zeus processor in executing floating-point operations with greater parallelism. When default rounding and exception handling control is specified in floating-point instructions, Zeus may safely retire instructions following them, as they are guaranteed not to cause data-dependent exceptions. Similarly, floating-point instructions with N, Z, F, or C control can be guaranteed not to cause data-dependent exceptions once the operands have been examined to rule out invalid operations, division by zero, overflow or underflow exceptions. Only floating-point instructions with X control, or when exceptions cannot be ruled out with N, Z, F, or C control need to avoid retiring following instructions until the final result is generated.

ANSI/IEEE standard 754-1985 specifies information to be given to trap handlers for the five floating-point exceptions. The Zeus architecture produces a precise exception, (The program counter points to the instruction that caused the exception and all general register state is present) from which all the required information can be produced in software, as all source operand values and the specified operation are available.

ANSI/IEEE standard 754-1985 specifies a set of five “sticky-exception” bits, for recording the occurrence of exceptions that are handled by default. The Zeus architecture produces a precise exception for instructions with N, Z, F, or C control for invalid operation, division by zero, overflow or underflow exceptions and with X control for all floating-point exceptions, from which software may arrange that corresponding sticky-exception bits can be set. Execution of the same instruction with default control will compute the default result with round-to-nearest rounding. Most compound operations not specified by the standard are not available with rounding and exception controls. These compound operations provide round-to-nearest rounding and default exception handling.

NaN Handling

ANSI/IEEE standard 754-1985 specifies that operations involving a signaling NaN or invalid operation shall, if no trap occurs and if a floating-point result is to be delivered, deliver a quiet NaN as its result. However, it fails to specify what quiet NaN value to deliver.

Zeus operations that produce a floating-point result and do not trap on invalid operations propagate signaling NaN values from operands to results, changing the signaling NaN values to quiet NaN values by setting the most significant fraction bit and leaving the remaining bits unchanged. Other causes of invalid operations produce the default quiet NaN value, where the sign bit is zero, the exponent field is all one bits, the most significant fraction bit is set and the remaining fraction bits are zero bits. For Zeus operations that produce multiple results catenated together, signaling NaN propagation or quiet NaN production is handled separately and independently for each result symbol.

ANSI/IEEE standard 754-1985 specifies that quiet NaN values should be propagated from operand to result by the basic operations. However, it fails to specify which of several quiet NaN values to propagate when more than one operand is a quiet NaN. In addition, the standard does not clearly specify how quiet NaN should be propagated for the multiple-operation instructions provided in Zeus. The standard does not specify the quiet NaN produced as a result of an operand being a signaling NaN when invalid operation exceptions are handled by default. The standard leaves unspecified how quiet and signaling NaN values are propagated though format conversions and the absolute-value, negate and copy operations. This section specifies these aspects left unspecified by the standard.

First of all, for Zeus operations that produce multiple results catenated together, quiet and signaling NaN propagation is handled separately and independently for each result symbol. A quiet or signaling NaN value in a single symbol of an operand causes only those result symbols that are dependent on that operand symbol's value to be propagated as that quiet NaN. Multiple quiet or signaling NaN values in symbols of an operand which influence separate symbols of the result are propagated independently of each other. Any signaling NaN that is propagated has the high-order fraction bit set to convert it to a quiet NaN.

For Zeus operations in which multiple symbols among operands upon which a result symbol is dependent are quiet or signaling NaNs, a priority rule will determine which NaN is propagated. Priority shall be given to the operand that is specified by a general register definition at a lower-numbered (little-endian) bit position within the instruction (rb has priority over rc, which has priority over rd). In the case of operands which are catenated from two general registers, priority shall be assigned based on the general register which has highest priority (lower-numbered bit position within the instruction). In the case of tie (as when the E.SCAL.ADD scaling operand has two corresponding NaN values, or when a E.MUL.CF operand has NaN values for both real and imaginary components of a value), the value which is located at a lower-numbered (little-endian) bit position within the operand is to receive priority. The identification of a NaN as quiet or signaling shall not confer any priority for selection—only the operand position, though a signaling NaN will cause an invalid operand exception.

The sign bit of NaN values propagated shall be complemented if the instruction subtracts or negates the corresponding operand or (but not and) multiplies it by or divides it by or divides it into an operand which has the sign bit set, even if that operand is another NaN. If a NaN is both subtracted and multiplied by a negative value, the sign bit shall be propagated unchanged.

For Zeus operations that convert between two floating-point formats (INFLATE and DEFLATE), NaN values are propagated by preserving the sign and the most-significant fraction bits, except that the most-significant bit of a signalling NaN is set and (for DEFLATE) the least-significant fraction bit preserved is combined, via a logical-or of all fraction bits not preserved. All additional fraction bits (for INFLATE) are set to zero.

For Zeus operations that convert from a floating-point format to a fixed-point format (SINK), NaN values produce zero values (maximum-likelihood estimate). Infinity values produce the largest representable positive or negative fixed-point value that fits in the destination field. When exception traps are enabled, NaN or Infinity values produce a floating-point exception. Underflows do not occur in the SINK operation, they produce −1, 0 or +1, depending on rounding controls.

For absolute-value, negate, or copy operations, NaN values are propagated with the sign bit cleared, complemented, or copied, respectively. Signalling NaN values cause the Invalid operation exception, propagating a quieted NaN in corresponding symbol locations (default) or an exception, as specified by the instruction.

Invalid Operation

ANSI/IEEE standard 754-1985 specifies that invalid operation shall be signaled if an operand is invalid for the operation to be performed. Zeus operations that specify a rounding mode trap on invalid operation. Zeus operations that default the rounding mode (to round to nearest) do not trap on invalid operation and produce a quiet NaN result as described above.

Standard compliant software produces the required result to a trap handler by following the requirements of the standard. Software may simulate untrapped invalid operation for other specified rounding modes by following the requirements of the standard for the result.

Division by Zero

ANSI/IEEE standard 754-1985 specifies that division by zero shall be signaled the divisor is zero and the dividend is a finite non zero number. Zeus operations that specify a rounding mode trap on division by zero. Zeus operations that default the rounding mode (to round to nearest) do not trap on division by zero and produce a signed infinity result.

Standard compliant software produces the required result to a trap handler by following the requirements of the standard. Software may simulate untrapped division by zero for other specified rounding modes by following the requirements of the standard for the result.

Overflow

ANSI/IEEE standard 754-1985 specifies that overflow shall be signaled whenever the destination format's largest finite number is exceeded in magnitude by what would have been the rounded floating-point result were the exponent range unbounded. Zeus operations that specify a rounding mode trap on overflow. Zeus operations that default the rounding mode (to round to nearest) do not trap on overflow and produce a result that carries all overflows to infinity with the sign of the intermediate result.

Standard compliant software produces the required result to a trap handler by following the requirements of the standard. Software may simulate untrapped overflow for other specified rounding modes by following the requirements of the standard for the result. The standard specifies a value with the sign of the intermediate result and specifies the largest finite number when the overflow is in the direction away from rounding or infinity otherwise.

Underflow

ANSI/IEEE standard 754-1985 specifies that underflow is dependent on two correlated events: tininess and loss of accuracy, but allows some latitute in the definition of these conditions. For Zeus operations, tininess is detected “after rounding,” that is when a non zero result computed as though the exponent range were unbounded would lie between the smallest normalized number for the format of the result. Zeus hardware does not produce sticky exception bits, so a notion of loss of accuracy does not apply.

Zeus operations that specify a rounding mode trap on underflow, which is to be signaled whenever tininess occurs. Zeus operations that default the rounding mode (to round to nearest) do not trap on underflow and produce a result that is zero or a denormalized number.

Standard compliant software produces the required result to a trap handler by following the requirements of the standard. Software may simulate untrapped underflow sticky exceptions by using the trapping operations and simulating a result, applying whatever definition of loss of accuracy is desired.

Inexact

ANSI/IEEE standard 754-1985 specifies that inexact shall be signaled whenever the rounded result of an operation is not exact or if it overflows without an overflow trap. Zeus operations that specify “exact” rounding trap on inexact. Zeus operations that default the rounding mode (to round to nearest) or specify a rounding mode do not trap on inexact and produce a rounded or overflowed result.

Standard compliant software produces the required result to a trap handler by following the requirements of the standard, delivering a rounded result.

Floating-Point Functions

Referring to FIG. 39A, functions are defined for use within the detailed instruction definitions in the following section. In these functions an internal format represents infinite-precision floating-point values as a four-element structure consisting of (1) s (sign bit): 0 for positive, 1 for negative, (2) t (type): NORM, ZERO, SNAN, QNAN, INFINITY, (3) e (exponent), and (4) f: (fraction). The mathematical interpretation of a normal value places the binary point at the units of the fraction, adjusted by the exponent: (−1)^s*(2^e)*f. The function F converts a packed IEEE floating-point value into internal format. The function PackF converts an internal format back into IEEE floating-point format, with rounding and exception control.

Digital Signal Processing

The Zeus processor provides a set of operations that maintain the fullest possible use of 128-bit data paths when operating on lower-precision fixed-point or floating-point vector values. These operations are useful for several application areas, including digital signal processing, image processing and synthetic graphics. The basic goal of these operations is to accelerate the performance of algorithms that exhibit the following characteristics:

Low-Precision Arithmetic

The operands and intermediate results are fixed-point values represented in no greater than 64 bit precision. For floating-point arithmetic, operands and intermediate results are of 16, 32, or 64 bit precision.

The fixed-point arithmetic operations include add, subtract, multiply, divide, shifts, and set on compare.

The use of fixed-point arithmetic permits various forms of operation reordering that are not permitted in floating-point arithmetic. Specifically, commutativity and associativity, and distribution identities can be used to reorder operations. Compilers can evaluate operations to determine what intermediate precision is required to get the specified arithmetic result.

Zeus supports several levels of precision, as well as operations to convert between these different levels. These precision levels are always powers of two, and are explicitly specified in the operation code.

When specified, add, subtract, and shift operations may cause a fixed-point arithmetic exception to occur on resulting conditions such as signed or unsigned overflow. The fixed-point arithmetic exception may also be invoked upon a signed or unsigned comparison.

Sequential Access to Data

The algorithms are or can be expressed as operations on sequentially ordered items in memory. Scatter-gather memory access or sparse-matrix techniques are not required.

Where an index variable is used with a multiplier, such multipliers must be powers of two. When the index is of the form: nx+k, the value of n must be a power of two, and the values referenced should have k include the majority of values in the range 0 . . . n−1. A negative multiplier may also be used.

Vectorizable Operations

The operations performed on these sequentially ordered items are identical and independent. Conditional operations are either rewritten to use Boolean variables or masking, or the compiler is permitted to convert the code into such a form.

Data-Handling Operations

The characteristics of these algorithms include sequential access to data, which permit the use of the normal load and store operations to reference the data. Octlet and hexlet loads and stores reference several sequential items of data, the number depending on the operand precision.

The discussion of these operations is independent of byte ordering, though the ordering of bit fields within octlets and hexlets must be consistent with the ordering used for bytes. Specifically, if big-endian byte ordering is used for the loads and stores, the figures below should assume that index values increase from left to right, and for little-endian byte ordering, the index values increase from right to left. For this reason, the figures indicate different index values with different shades, rather than numbering.

When an index of the nx+k form is used in array operands, where n is a power of 2, data memory sequentially loaded contains elements useful for separate operands. The “shuffle” instruction divides a triclet of data up into two hexlets, with alternate bit fields of the source triclet grouped together into the two results. An immediate field, h, in the instruction specifies which of the two regrouped hexlets to select for the result. For example, two X.SHUFFLE.PAIR rd=rc,rb,32,128,h operations rearrange the source triclet (c,b) into two hexlets as in FIG. 39B.

In the shuffle operation, two hexlet general registers specify the source triclet, and one of the two result hexlets are specified as hexlet general register.

The example above directly applies to the case where n is 2. When n is larger, shuffle operations can be used to further subdivide the sequential stream. For example, when n is 4, we need to deal out 4 sets of doublet operands, as shown in FIG. 39C. (An example of the use of a four-way deal is a digital signal processing application such as conversion of color to monochrome.)

When an array result of computation is accessed with an index of the form nx+k, for n a power of 2, the reverse of the “deal” operation needs to be performed on vectors of results to interleave them for storage in sequential order. The “shuffle” operation interleaves the bit fields of two octlets of results into a single hexlet. For example a X.SHUFFLE.16 operation combines two octlets of doublet fields into a hexlet as in FIG. 39D.

For larger values of n, a series of shuffle operations can be used to combine additional sets of fields, similarly to the mechanism used for the deal operations. For example, when n is 4, we need to shuffle up 4 sets of doublet operands, as shown in FIG. 39E. (An example of a four-way shuffle is a digital signal processing application such as conversion of monochrome to color.)

When the index of a source array operand or a destination array result is negated, or in other words, if of the form nx+k where n is negative, the elements of the array must be arranged in reverse order. The “swizzle” operation can reverse the order of the bit fields in a hexlet. For example, a X.SWIZZLE rd=rc,127,112 operation reverses the doublets within a hexlet as shown in FIG. 39F.

In some cases, it is desirable to use a group instruction in which one or more operands is a single value, not an array. The “swizzle” operation can also copy operands to multiple locations within a hexlet. For example, a X.SWIZZLE 15,0 operation copies the low-order 16 bits to each double within a hexlet.

Variations of the deal and shuffle operations are also useful for converting from one precision to another. This may be required if one operand is represented in a different precision than another operand or the result, or if computation must be performed with intermediate precision greater than that of the operands, such as when using an integer multiply.

When converting from a higher precision to a lower precision, specifically when halving the precision of a hexlet of bit fields, half of the data must be discarded, and the bit fields packed together. The “compress” operation is a variant of the “deal” operation, in which the operand is a hexlet, and the result is an octlet. An arbitrary half-sized sub-field of each bit field can be selected to appear in the result. For example, a selection of bits 19 . . . 4 of each quadlet in a hexlet is performed by the X.COMPRESS rd=rc,16,4 operation as shown in FIG. 39G.

When converting from lower-precision to higher-precision, specifically when doubling the precision of an octlet of bit fields, one of several techniques can be used, either multiply, expand, or shuffle. Each has certain useful properties. In the discussion below, m is the precision of the source operand.

The multiply operation, described in detail below, automatically doubles the precision of the result, so multiplication by a constant vector will simultaneously double the precision of the operand and multiply by a constant that can be represented in m bits.

An operand can be doubled in precision and shifted left with the “expand” operation, which is essentially the reverse of the “compress” operation. For example the X.EXPAND rd=rc,16,4 expands from 16 bits to 32, and shifts 4 bits left as shown in FIG. 39H

The “shuffle” operation can double the precision of an operand and multiply it by 1 (unsigned only), 2m or 2m+1, by specifying the sources of the shuffle operation to be a zeroed general register and the source operand, the source operand and zero, or both to be the source operand. When multiplying by 2m, a constant can be freely added to the source operand by specifying the constant as the right operand to the shuffle.

Arithmetic Operations

The characteristics of the algorithms that affect the arithmetic operations most directly are low-precision arithmetic, and vectorizable operations. The fixed-point arithmetic operations provided are most of the functions provided in the standard integer unit, except for those that check conditions. These functions include add, subtract, bitwise Boolean operations, shift, set on condition, and multiply, in forms that take packed sets of bit fields of a specified size as operands. The floating-point arithmetic operations provided are as complete as the scalar floating-point arithmetic set. The result is generally a packed set of bit fields of the same size as the operands, except that the fixed-point multiply function intrinsically doubles the precision of the bit field.

Conditional operations are provided only in the sense that the set on condition operations can be used to construct bit masks that can select between alternate vector expressions, using the bitwise Boolean operations. All instructions operate over the entire octlet or hexlet operands, and produce a hexlet result. The sizes of the bit fields supported are always powers of two.

Galois Field Operations

Zeus provides a general software solution to the most common operations required for Galois Field arithmetic. The instructions provided include a polynomial multiply, with the polynomial specified as one general register operand. This instruction can be used to perform CRC generation and checking, Reed-Solomon code generation and checking, and spread-spectrum encoding and decoding.

Software Conventions

The following section describes software conventions that are to be employed at software module boundaries, in order to permit the combination of separately compiled code and to provide standard interfaces between application, library and system software. General register usage and procedure call conventions may be modified, simplified or optimized when a single compilation encloses procedures within a compilation unit so that the procedures have no external interfaces. For example, internal procedures may permit a greater number of general register-passed parameters, or have general registers allocated to avoid the need to save general registers at procedure boundaries, or may use a single stack or data pointer allocation to suffice for more than one level of procedure call.

General Register Usage

All Zeus general registers are identical and general-purpose; there is no dedicated zero-valued general register, and there are no dedicated floating-point general registers. However, some procedure-call-oriented instructions imply usage of general registers zero (0) and one (1) in a manner consistent with the conventions described below. By software convention, the non-specific general registers are used in more specific ways.

general

register

assembler

how

number

names

usage

saved

0

lp, r0

link pointer

caller

1

dp, r1

data pointer

caller

2-9

r2-r9

parameters

caller

10-31

r10-r31

temporary

caller

32-61

r32-r61

saved

callee

62

fp, r62

frame pointer

callee

63

sp, r63

stack pointer

callee

At a procedure call boundary, general registers are saved either by the caller or callee procedure, which provides a mechanism for leaf procedures to avoid needing to save general registers. Compilers may choose to allocate variables into caller or callee saved general registers depending on how their lifetimes overlap with procedure calls.

Procedure Calling Conventions

Procedure parameters are normally allocated in general registers, starting from general register 2 up to general register 9. These general registers hold up to 8 parameters, which may each be of any size from one byte to sixteen bytes (hexlet), including floating-point and small structure parameters. Additional parameters are passed in memory, allocated on the stack. For C procedures which use varargs.h or stdarg.h and pass parameters to further procedures, the compilers must leave room in the stack memory allocation to save general registers 2 through 9 into memory contiguously with the additional stack memory parameters, so that procedures such as _doprnt can refer to the parameters as an array.

Procedure return values are also allocated in general registers, starting from general register 2 up to general register 9. Larger values are passed in memory, allocated on the stack.

There are several pointers maintained in general registers for the procedure calling conventions: lp, sp, dp, fp.

The lp general register contains the address to which the callee should return to at the conclusion of the procedure. If the procedure is also a caller, the lp general register will need to be saved on the stack, once, before any procedure call, and restored, once, after all procedure calls. The procedure returns with a branch instruction, specifying the lp general register.

The sp general register is used to form addresses to save parameter and other general registers, maintain local variables, i.e., data that is allocated as a LIFO stack. For procedures that require a stack, normally a single allocation is performed, which allocates space for input parameters, local variables, saved general registers, and output parameters all at once. The sp general register is always hexlet aligned.

The dp general register is used to address pointers, literals and static variables for the procedure. The dp general register points to a small (approximately 4096-entry) array of pointers, literals, and statically-allocated variables, which is used locally to the procedure. The uses of the dp general register are similar to the use of the gp general register on a Mips R-series processor, except that each procedure may have a different value, which expands the space addressable by small offsets from this pointer. This is an important distinction, as the offset field of Zeus load and store instructions are only 12 bits. The compiler may use additional general registers and/or indirect pointers to address larger regions for a single procedure. The compiler may also share a single dp general register value between procedures which are compiled as a single unit (including procedures which are externally callable), eliminating the need to save, modify and restore the dp general register for calls between procedures which share the same dp general register value.

Load- and store-immediate-aligned instructions, specifying the dp general register as the base general register, are generally used to obtain values from the dp region. These instructions shift the immediate value by the logarithm of the size of the operand, so loads and stores of large operands may reach farther from the dp general register than of small operands. Referring to FIG. 39I, the size of the addressable region is maximized if the elements to be placed in the dp region are sorted according to size, with the smallest elements placed closest to the dp base. At points where the size changes, appropriate padding is added to keep elements aligned to memory boundaries matching the size of the elements. Using this technique, the maximum size of the dp region is always at least 4096 items, and may be larger when the dp area is composed of a mixture of data sizes.

The dp general register mechanism also permits code to be shared, with each static instance of the dp region assigned to a different address in memory. In conjunction with position-independent or pc-relative branches, this allows library code to be dynamically relocated and shared between processes.

To implement an inter-module (separately compiled) procedure call, the lp general register is loaded with the entry point of the procedure, and the dp general register is loaded with the value of the dp general register required for the procedure. These two values are located adjacent to each other as a pair of octlet quantities in the dp region for the calling procedure. For a statically-linked inter-module procedure call, the linker fills in the values at link time. However, this mechanism also provides for dynamic linking, by initially filling in the lp and dp fields in the data structure to invoke the dynamic linker. The dynamic linker can use the contents of the lp and/or dp general registers to determine the identity of the caller and callee, to find the location to fill in the pointers and resume execution. Specifically, the lp value is initially set to point to an entry point in the dynamic linker, and the dp value is set to point to itself: the location of the lp and dp values in the dp region of the calling procedure. The identity of the procedure can be discovered from a string following the dp pointer, or a separate table, indexed by the dp pointer.

The fp general register is used to address the stack frame when the stack size varies during execution of a procedure, such as when using the GNU C alloca function. When the stack size can be determined at compile time, the sp general register is used to address the stack frame and the fp general register may be used for any other general purpose as a callee-saved general register.

Typical static-linked, intra-module calling sequence:

caller (non-leaf):

caller:

A.ADDI

sp@-size

// allocate caller stack frame

S.I.64.A

lp,sp,off

// save original lp general register

... (callee using same dp as caller)

B.LINK.I

callee

...

... (callee using same dp as caller)

B.LINK.I

callee

...

L.I.64.A

lp=sp,off

// restore original lp general register

A.ADDI

sp@size

// deallocate caller stack frame

B

lp

// return

callee (leaf):

callee:

... (code using dp)

B

lp

// return

Procedures that are compiled together may share a common data region, in which case there is no need to save, load, and restore the dp region in the callee, assuming that the callee does not modify the dp general register. The pc-relative addressing of the B.LINK.I instruction permits the code region to be position-independent.

Minimum static-linked, intra-module calling sequence:

caller (non-leaf):

caller:

A.COPY

r31=lp

// save original lp general register

... (callee using same dp as caller)

B.LINK.I

callee

...

... (callee using same dp as caller)

B.LINK.I

callee

...

B

r31

// return

callee (leaf):

callee:

... (code using dp, r31 unused)

B

lp

// return

When all the callee procedures are intra-module, the stack frame may also be eliminated from the caller procedure by using “temporary” caller save general registers not utilized by the callee leaf procedures. In addition to the lp value indicated above, this usage may include other values and variables that live in the caller procedure across callee procedure calls.

Typical dynamic-linked, inter-module calling sequence:

caller (non-leaf):

caller:

A.ADDI

sp@-size

// allocate caller stack frame

S.I.64.A

lp,sp,off

// save original lp general register

S.I.64.A

dp,sp,off

// save original dp general register

... (code using dp)

L.I.64.A

lp=dp.off

// load lp

L.I.64.A

dp=dp,off

// load dp

B.LINK

lp=lp

// invoke callee procedure

L.I.64.A

dp=sp,off

// restore dp general register from stack

... (code using dp)

L.I.64.A

lp=sp,off

// restore original lp general register

A.ADDI

sp=size

// deallocate caller stack frame

B

lp

// return

callee (leaf):

callee:

... (code using dp)

B

lp

// return

The load instruction is required in the caller following the procedure call to restore the dp general register. A second load instruction also restores the lp general register, which may be located at any point between the last procedure call and the branch instruction which returns from the procedure.

System and Privileged Library Calls

It is an objective to make calls to system facilities and privileged libraries as similar as possible to normal procedure calls as described above. Rather than invoke system calls as an exception, which involves significant latency and complication, we prefer to use a modified procedure call in which the process privilege level is quietly raised to the required level. To provide this mechanism safely, interaction with the virtual memory system is required.

Such a procedure must not be entered from anywhere other than its legitimate entry point, to prohibit entering a procedure after the point at which security checks are performed or with invalid general register contents, otherwise the access to a higher privilege level can lead to a security violation. In addition, the procedure generally must have access to memory data, for which addresses must be produced by the privileged code. To facilitate generating these addresses, the branch-gateway instruction allows the privileged code procedure to rely the fact that a single general register has been verified to contain a pointer to a valid memory region.

The branch-gateway instruction ensures both that the procedure is invoked at a proper entry point, and that other general registers such as the data pointer and stack pointer can be properly set. To ensure this, the branch-gateway instruction retrieves a “gateway” directly from the protected virtual memory space. The gateway contains the virtual address of the entry point of the procedure and the target privilege level. A gateway can only exist in regions of the virtual address space designated to contain them, and can only be used to access privilege levels at or below the privilege level at which the memory region can be written to ensure that a gateway cannot be forged.

The branch-gateway instruction ensures that general register 1 (dp) contains a valid pointer to the gateway for this target code address by comparing the contents of general register 0 (lp) against the gateway retrieved from memory and causing an exception trap if they do not match. By ensuring that general register 1 points to the gateway, auxiliary information, such as the data pointer and stack pointer can be set by loading values located by the contents of general register 1. For example, the eight bytes following the gateway may be used as a pointer to a data region for the procedure.

Referring to FIG. 39J before executing the branch-gateway instruction, general register 1 must be set to point at the gateway, and general register 0 must be set to the address of the target code address plus the desired privilege level. A “L.I.64.L.A r0=r1,0” instruction is one way to set general register 0, if general register 1 has already been set, but any means of getting the correct value into general register 0 is permissible.

Similarly, a return from a system or privileged routine involves a reduction of privilege. This need not be carefully controlled by architectural facilities, so a procedure may freely branch to a less-privileged code address. Normally, such a procedure restores the stack frame, then uses the branch-down instruction to return.

Typical dynamic-linked, inter-gateway calling sequence:

caller:

caller:

A.ADDI

sp@-size

// allocate caller stack frame

S.I.64.A

lp,sp,off

S.I.64.A

dp,sp,off

...

L.I.64.A

lp=dp.off

// load lp

L.I.64.A

dp=dp,off

// load dp

B.GATE

L.I.64.A

dp,sp,off

... (code using dp)

L.I.64.A

lp=sp,off

// restore original lp general register

A.ADDI

sp=size

// deallocate caller stack frame

B

lp

// return

callee (non-leaf):

calee:

L.I.64.A

dp=dp,off

// load dp with data pointer

S.I.64.A

sp,dp,off

L.I.64.A

sp=dp,off

// new stack pointer

S.I.64.A

lp,sp,off

S.I.64.A

dp,sp,off

... (using dp)

L.I.64.A

dp,sp,off

... (code using dp)

L.I.64.A

lp=sp,off

// restore original lp general register

L.I.64.A

sp=sp,off

// restore original sp general register

B.DOWN

lp

callee (leaf, no stack):

callee:

... (using dp)

B.DOWN

lp

It can be observed that the calling sequence is identical to that of the inter-module calling sequence shown above, except for the use of the B.GATE instruction instead of a B.LINK instruction. Indeed, if a B.GATE instruction is used when the privilege level in the lp general register is not higher than the current privilege level, the B.GATE instruction performs an identical function to a B.LINK.

The callee, if it uses a stack for local variable allocation, cannot necessarily trust the value of the sp passed to it, as it can be forged. Similarly, any pointers which the callee provides should not be used directly unless it they are verified to point to regions which the callee should be permitted to address. This can be avoided by defining application programming interfaces (APIs) in which all values are passed and returned in general registers, or by using a trusted, intermediate privilege wrapper routine to pass and return parameters. The method described below can also be used.

It can be useful to have highly privileged code call less-privileged routines. For example, a user may request that errors in a privileged routine be reported by invoking a user-supplied error-logging routine. To invoke the procedure, the privilege can be reduced via the branch-down instruction. The return from the procedure actually requires an increase in privilege, which must be carefully controlled. This is dealt with by placing the procedure call within a lower-privilege procedure wrapper, which uses the branch-gateway instruction to return to the higher privilege region after the call through a secure re-entry point. Special care must be taken to ensure that the less-privileged routine is not permitted to gain unauthorized access by corruption of the stack or saved general registers, such as by saving all general registers and setting up a new stack frame (or restoring the original lower-privilege stack) that may be manipulated by the less-privileged routine. Finally, such a technique is vulnerable to an unprivileged routine attempting to use the re-entry point directly, so it may be appropriate to keep a privileged state variable which controls permission to enter at the re-entry point.

Processor Layout

Referring first to FIG. 1, a general purpose processor is illustrated therein in block diagram form. In FIG. 1, four copies of an access unit are shown, each with an access instruction fetch queue A-Queue 101-104. Each access instruction fetch queue A-Queue 101-104 is coupled to an access register file AR 105-108, which are each coupled to two access functional units A 109-116. In a typical embodiment, each thread of the processor may have on the order of sixty-four general purpose registers (e.g., the AR's 105-108 and ER's 125-128). The access units function independently for four simultaneous threads of execution, and each compute program control flow by performing arithmetic and branch instructions and access memory by performing load and store instructions. These access units also provide wide operand specifiers for wide operand instructions. These eight access functional units A 109-116 produce results for access register files AR 105-108 and memory addresses to a shared memory system 117-120.

In one embodiment, the memory hierarchy includes on-chip instruction and data memories, instruction and data caches, a virtual memory facility, and interfaces to external devices. In FIG. 1, the memory system is comprised of a combined cache and niche memory 117, an external bus interface 118, and, externally to the device, a secondary cache 119 and main memory system with I/O devices 120. The memory contents fetched from memory system 117-120 are combined with execute instructions not performed by the access unit, and entered into the four execute instruction queues E-Queue 121-124. For wide instructions, memory contents fetched from memory system 117-120 are also provided to wide operand microcaches 132-136 by bus 137. Instructions and memory data from E-queue 121-124 are presented to execution register files 125-128, which fetch execution register file source operands. The instructions are coupled to the execution unit arbitration unit Arbitration 131, that selects which instructions from the four threads are to be routed to the available execution functional units E 141 and 149, X 142 and 148, G 143-144 and 146-147, and T 145. The execution functional units E 141 and 149, the execution functional units X 142 and 148, and the execution functional unit T 145 each contain a wide operand microcache 132-136, which are each coupled to the memory system 117 by bus 137.

The execution functional units G 143-144 and 146-147 are group arithmetic and logical units that perform simple arithmetic and logical instructions, including group operations wherein the source and result operands represent a group of values of a specified symbol size, which are partitioned and operated on separately, with results catenated together. In a presently preferred embodiment the data path is 128 bits wide, although the present invention is not intended to be limited to any specific size of data path.

The execution functional units X 142 and 148 are crossbar switch units that perform crossbar switch instructions. The crossbar switch units 142 and 148 perform data handling operations on the data stream provided over the data path source operand buses 151-158, including deals, shuffles, shifts, expands, compresses, swizzles, permutes and reverses, plus the wide operations discussed hereinafter. In a key element of a first aspect of the invention, at least one such operation will be expanded to a width greater than the general register and data path width.

The execution functional units E 141 and 149 are ensemble units that perform ensemble instructions using a large array multiplier, including group or vector multiply and matrix multiply of operands partitioned from data path source operand buses 151-158 and treated as integer, floating point, polynomial or Galois field values. Matrix multiply instructions and other operations utilize a wide operand loaded into the wide operand microcache 132 and 136.

The execution functional unit T 145 is a translate unit that performs table-look-up operations on a group of operands partitioned from a register operand, and catenates the result. The Wide Translate instruction utilizes a wide operand loaded into the wide operand microcache 134.

The execution functional units E 141, 149, execution functional units X—142, 148, and execution functional unit T each contain dedicated storage to permit storage of source operands including wide operands as discussed hereinafter. The dedicated storage 132-136, which may be thought of as a wide microcache, typically has a width which is a multiple of the width of the data path operands related to the data path source operand buses 151-158. Thus, if the width of the data path 151-158 is 128 bits, the dedicated storage 132-136 may have a width of 256, 512, 1024 or 2048 bits. Operands which utilize the full width of the dedicated storage are referred to herein as wide operands, although it is not necessary in all instances that a wide operand use the entirety of the width of the dedicated storage; it is sufficient that the wide operand use a portion greater than the width of the memory data path of the output of the memory system 117-120 and the functional unit data path of the input of the execution functional units 141-149, though not necessarily greater than the width of the two combined. Because the width of the dedicated storage 132-136 is greater than the width of the memory operand bus 137, portions of wide operands are loaded sequentially into the dedicated storage 132-136. However, once loaded, the wide operands may then be used at substantially the same time. It can be seen that functional units 141-149 and associated execution registers 125-128 form a data functional unit, the exact elements of which may vary with implementation.

The execution register file ER 125-128 source operands are coupled to the execution units 141-145 using source operand buses 151-154 and to the execution units 145-149 using source operand buses 155-158. The function unit result operands from execution units 141-145 are coupled to the execution register file ER 125-128 using result bus 161 and the function units result operands from execution units 145-149 are coupled to the execution register file using result bus 162.

Wide Multiply Matrix

The wide operands of the present invention provide the ability to execute complex instructions such as the wide multiply matrix instruction shown in FIG. 2, which can be appreciated in an alternative form, as well, from FIG. 3. As can be appreciated from FIGS. 2 and 3, a wide operand permits, for example, the matrix multiplication of various sizes and shapes which exceed the data path width. The example of FIG. 2 involves a matrix specified by register rc having 128*64/size bits (512 bits for this example) multiplied by a vector contained in register rb having 128 bits, to yield a result, placed in register rd, of 128 bits.

The notation used in FIG. 2 and following similar figures illustrates a multiplication as a shaded area at the intersection of two operands projected in the horizontal and vertical dimensions. A summing node is illustrated as a line segment connecting a darkened dots at the location of multiplier products that are summed. Products that are subtracted at the summing node are indicated with a minus symbol within the shaded area.

When the instruction operates on floating-point values, the multiplications and summations illustrated are floating point multiplications and summations. An exemplary embodiment may perform these operations without rounding the intermediate results, thus computing the final result as if computed to infinite precision and then rounded only once.

It can be appreciated that an exemplary embodiment of the multipliers may compute the product in carry-save form and may encode the multiplier rb using Booth encoding to minimize circuit area and delay. It can be appreciated that an exemplary embodiment of such summing nodes may perform the summation of the products in any order, with particular attention to minimizing computation delay, such as by performing the additions in a binary or higher-radix tree, and may use carry-save adders to perform the addition to minimize the summation delay. It can also be appreciated that an exemplary embodiment may perform the summation using sufficient intermediate precision that no fixed-point or floating-point overflows occur on intermediate results.

A comparison of FIGS. 2 and 3 can be used to clarify the relation between the notation used in FIG. 2 and the more conventional schematic notation in FIG. 3, as the same operation is illustrated in these two figures.

Wide Operand

The operands that are substantially larger than the data path width of the processor are provided by using a general-purpose register to specify a memory specifier from which more than one but in some embodiments several data path widths of data can be read into the dedicated storage. The memory specifier typically includes the memory address together with the size and shape of the matrix of data being operated on. The memory specifier or wide operand specifier can be better appreciated from FIG. 5, in which a specifier 500 is seen to be an address, plus a field representative of the size/2 and a further field representative of width/2, where size is the product of the depth and width of the data. The address is aligned to a specified size, for example sixty four bytes, so that a plurality of low order bits (for example, six bits) are zero. The specifier 500 can thus be seen to comprise a first field 505 for the address, plus two field indicia 510 within the low order six bits to indicate size and width.

Specifier Decoding

The decoding of the specifier 500 may be further appreciated from FIG. 6 where, for a given specifier 600 made up of an address field 605 together with a field 610 comprising plurality of low order bits. By a series of arithmetic operations shown at steps 615 and 620, the portion of the field 610 representative of width/2 is developed. In a similar series of steps shown at 625 and 630, the value of t is decoded, which can then be used to decode both size and address. The portion of the field 610 representative of size/2 is decoded as shown at steps 635 and 640, while the address is decoded in a similar way at steps 645 and 650.

Wide Function Unit

The wide function unit may be better appreciated from FIG. 7, in which a register number 700 is provided to an operand checker 705. Wide operand specifier 710 communicates with the operand checker 705 and also addresses memory 715 having a defined memory width. The memory address includes a plurality of register operands 720A n, which are accumulated in a dedicated storage portion 714 of a data functional unit 725. In the exemplary embodiment shown in FIG. 7, the dedicated storage 71.4 can be seen to have a width equal to eight data path widths, such that eight wide operand portions 730A-H are sequentially loaded into the dedicated storage to form the wide operand. Although eight portions are shown in FIG. 7, the present invention is not limited to eight or any other specific multiple of data path widths. Once the wide operand portions 730A-H are sequentially loaded, they may be used as a single wide operand 735 by the functional element 740, which may be any element(s) from FIG. 1 connected thereto. The result of the wide operand is then provided to a result register 745, which in a presently preferred embodiment is of the same width as the memory width.

Once the wide operand is successfully loaded into the dedicated storage 714, a second aspect of the present invention may be appreciated. Further execution of this instruction or other similar instructions that specify the same memory address can read the dedicated storage to obtain the operand value under specific conditions that determine whether the memory operand has been altered by intervening instructions. Assuming that these conditions are met, the memory operand fetch from the dedicated storage is combined with one or more register operands in the functional unit, producing a result. In some embodiments, the size of the result is limited to that of a general register, so that no similar dedicated storage is required for the result. However, in some different embodiments, the result may be a wide operand, to further enhance performance.

To permit the wide operand value to be addressed by subsequent instructions specifying the same memory address, various conditions must be checked and confirmed:

Those Conditions Include:

Each memory store instruction checks the memory address against the memory addresses recorded for the dedicated storage. Any match causes the storage to be marked invalid, since a memory store instruction directed to any of the memory addresses stored in dedicated storage 714 means that data has been overwritten.

The register number used to address the storage is recorded. If no intervening instructions have written to the register, and the same register is used on the subsequent instruction, the storage is valid (unless marked invalid by rule #1).

If the register has been modified or a different register number is used, the value of the register is read and compared against the address recorded for the dedicated storage. This uses more resources than #1 because of the need to fetch the register contents and because the width of the register is greater than that of the register number itself. If the address matches, the storage is valid. The new register number is recorded for the dedicated storage.

If conditions #2 or #3 are not met, the register contents are used to address the general-purpose processor's memory and load the dedicated storage. If dedicated storage is already fully loaded, a portion of the dedicated storage must be discarded (victimized) to make room for the new value. The instruction is then performed using the newly updated dedicated storage. The address and register number is recorded for the dedicated storage.

By checking the above conditions, the need for saving and restoring the dedicated storage is eliminated. In addition, if the context of the processor is changed and the new context does not employ Wide instructions that reference the same dedicated storage, when the original context is restored, the contents of the dedicated storage are allowed to be used without refreshing the value from memory, using checking rule #3. Because the values in the dedicated storage are read from memory and not modified directly by performing wide operations, the values can be discarded at any time without saving the results into general memory. This property simplifies the implementation of rule #4 above.

An alternate embodiment of the present invention can replace rule #1 above with the following rule:

1a. Each memory store instruction checks the memory address against the memory addresses recorded for the dedicated storage. Any match causes the dedicated storage to be updated, as well as the general memory.

By use of the above rule 1.a, memory store instructions can modify the dedicated storage, updating just the piece of the dedicated storage that has been changed, leaving the remainder intact. By continuing to update the general memory, it is still true that the contents of the dedicated memory can be discarded at any time without saving the results into general memory. Thus rule #4 is not made more complicated by this choice. The advantage of this alternate embodiment is that the dedicated storage need not be discarded (invalidated) by memory store operations.

Wide Microcache Data Structures

Referring next to FIG. 9, an exemplary arrangement of the data structures of the wide microcache or dedicated storage 114 may be better appreciated. The wide microcache contents, wmc.c, can be seen to form a plurality of data path widths 900A-n, although in the example shown the number is eight. The physical address, wmc.pa, is shown as 64 bits in the example shown, although the invention is not limited to a specific width. The size of the contents, wmc.size, is also provided in a field which is shown as 10 bits in an exemplary embodiment. A “contents valid” flag, wmc.cv, of one bit is also included in the data structure, together with a two bit field for thread last used, or wmc.th. In addition, a six bit field for register last used, wmc.reg, is provided in an exemplary embodiment. Further, a one bit flag for register and thread valid, or wmc.rtv, may be provided.

Wide Microcache Control—Software

The process by which the microcache is initially written with a wide operand, and thereafter verified as valid for fast subsequent operations, may be better appreciated from FIG. 8. The process begins at 800, and progresses to step 805 where a check of the register contents is made against the stored value wmc.rc. If true, a check is made at step 810 to verify the thread. If true, the process then advances to step 815 to verify whether the register and thread are valid. If step 815 reports as true, a check is made at step 820 to verify whether the contents are valid. If all of steps 805 through 820 return as true, the subsequent instruction is able to utilize the existing wide operand as shown at step 825, after which the process ends. However, if any of steps 805 through 820 return as false, the process branches to step 830, where content, physical address and size are set. Because steps 805 through 820 all lead to either step 825 or 830, steps 805 through 820 may be performed in any order or simultaneously without altering the process. The process then advances to step 835 where size is checked. This check basically ensures that the size of the translation unit is greater than or equal to the size of the wide operand, so that a physical address can directly replace the use of a virtual address. The concern is that, in some embodiments, the wide operands may be larger than the minimum region that the virtual memory system is capable of mapping. As a result, it would be possible for a single contiguous virtual address range to be mapped into multiple, disjoint physical address ranges, complicating the task of comparing physical addresses. By determining the size of the wide operand and comparing that size against the size of the virtual address mapping region which is referenced, the instruction is aborted with an exception trap if the wide operand is larger than the mapping region. This ensures secure operation of the processor. Software can then re-map the region using a larger size map to continue execution if desired. Thus, if size is reported as unacceptable at step 835, an exception is generated at step 840. If size is acceptable, the process advances to step 845 where physical address is checked. If the check reports as met, the process advances to step 850, where a check of the contents valid flag is made. If either check at step 845 or 850 reports as false, the process branches and new content is written into the dedicated storage 114, with the fields thereof being set accordingly. Whether the check at step 850 reported true, or whether new content was written at step 855, the process advances to step 860 where appropriate fields are set to indicate the validity of the data, after which the requested function can be performed at step 825. The process then ends.

Wide Microcache Control—Hardware

Referring next to FIGS. 10 and 11, which together show the operation of the microcache controller from a hardware standpoint, the operation of the microcache controller may be better understood. In the hardware implementation, it is clear that conditions which are indicated as sequential steps in FIGS. 8 and 9 above can be performed in parallel, reducing the delay for such wide operand checking. Further, a copy of the indicated hardware may be included for each wide microcache, and thereby all such microcaches as may be alternatively referenced by an instruction can be tested in parallel. It is believed that no further discussion of FIGS. 10 and 11 is required in view of the extensive discussion of FIGS. 8 and 9, above.

Various alternatives to the foregoing approach do exist for the use of wide operands, including an implementation in which a single instruction can accept two wide operands, partition the operands into symbols, multiply corresponding symbols together, and add the products to produce a single scalar value or a vector of partitioned values of width of the register file, possibly after extraction of a portion of the sums. Such an instruction can be valuable for detection of motion or estimation of motion in video compression. A further enhancement of such an instruction can incrementally update the dedicated storage if the address of one wide operand is within the range of previously specified wide operands in the dedicated storage, by loading only the portion not already within the range and shifting the in-range portion as required. Such an enhancement allows the operation to be performed over a “sliding window” of possible values. In such an instruction, one wide operand is aligned and supplies the size and shape information, while the second wide operand, updated incrementally, is not aligned.

The Wide Convolve Extract instruction and Wide Convolve Floating-point instruction described below is one alternative embodiment of an instruction that accepts two wide operands.

Another alternative embodiment of the present invention can define additional instructions where the result operand is a wide operand. Such an enhancement removes the limit that a result can be no larger than the size of a general register, further enhancing performance. These wide results can be cached locally to the functional unit that created them, but must be copied to the general memory system before the storage can be reused and before the virtual memory system alters the mapping of the address of the wide result. Data paths must be added so that load operations and other wide operations can read these wide results—forwarding of a wide result from the output of a functional unit back to its input is relatively easy, but additional data paths may have to be introduced if it is desired to forward wide results back to other functional units as wide operands.

As previously discussed, a specification of the size and shape of the memory operand is included with the low-order bits of the address. In a presently preferred implementation, such memory operands are typically a power of two in size and aligned to that size. Generally, one half the total size is added (or inclusively or'ed, or exclusively or'ed) to the memory address, and one half of the data width is added (or inclusively or'ed, or exclusively or'ed) to the memory address. These bits can be decoded and stripped from the memory address, so that the controller is made to step through all the required addresses. The number of distinct operands required for these instructions is hereby decreased, as the size, shape and address of the memory operand are combined into a single register operand value.

In an alternative exemplary embodiment described below in the Wide Switch instruction and others below, the wide operand specifier is described as containing optional size and shape specifiers. As such, the omission of the specifier value obtains a default size or shape defined from attributes of the specified instruction.

In an alternative exemplary embodiment described below in the Wide Convolve Extract instruction below, the wide operand specifier contains mandatory size and shape specifier. The omission of the specifier value obtains an exception which aborts the operation. Notably, the specification of a larger size or shape than an implementation may permit due to limited resources, such as the limited size of a wide operand memory, may result in a similar exception when the size or shape descriptor is searched for only in the limited bit range in which a valid specifier value may be located. This can be utilized to ensure that software that requires a larger specifier value than the implementation can provide results in a detected exception condition, when for example, a plurality of implementations of the same instruction set of a processor differ in capabilities. This also allows for an upward-compatible extension of wide operand sizes and shapes to larger values in extended implementations of the same instruction set.

In an alternative exemplary embodiment, the wide operand specifier contains size and shape specifiers in an alternative representation other than linearly related to the value of the size and shape parameters. For example, low-order bits of the specifier may contain a fixed-size binary value which is logarithmically related to the value, such as a two-bit field where 00 conveys a value of 128, 01 a value of 256, 10 a value of 512, and 11 a value of 1024. The use of a fixed-size field limits the maximum value which can be specified in, for example, a later upward-compatible implementation of a processor.

Instruction Set

This section describes the instruction set in complete architectural detail. Operation codes are numerically defined by their position in the following operation code tables, and are referred to symbolically in the detailed instruction definitions. Entries that span more than one location in the table define the operation code identifier as the smallest value of all the locations spanned. The value of the symbol can be calculated from the sum of the legend values to the left and above the identifier.

Instructions that have great similarity and identical formats are grouped together. Starting on a new page, each category of instructions is named and introduced.

The Operation codes section lists each instruction by mnemonic that is defined on that page. A textual interpretation of each instruction is shown beside each mnemonic.

The Equivalences section lists additional instructions known to assemblers that are equivalent or special cases of base instructions, again with a textual interpretation of each instruction beside each mnemonic. Below the list, each equivalent instruction is defined, either in terms of a base instruction or another equivalent instruction. The symbol between the instruction and the definition has a particular meaning. If it is an arrow (← or →), it connects two mathematicaly equivalent operations, and the arrow direction indicates which form is preferred and produced in a reverse assembly. If the symbol is a

the form on the left is assembled into the form on the right solely for encoding purposes, and the form on the right is otherwise illegal in the assembler. The parameters in these definitions are formal; the names are solely for pattern-matching purposes, even though they may be suggestive of a particular meaning.

The Redundancies section lists instructions and operand values that may also be performed by other instructions in the instruction set. The symbol connecting the two forms is a

which indicates that the two forms are mathematically equivalent, both are legal, but the assembler does not transform one into the other.

The Selection section lists instructions and equivalences together in a tabular form that highlights the structure of the instruction mnemonics.

The Format section lists (1) the assembler format, (2) the C intrinsics format, (3) the bit-level instruction format, and (4) a definition of bit-level instruction format fields that are not a one-for-one match with named fields in the assembler format.

The Definition section gives a precise definition of each basic instruction.

The Exceptions section lists exceptions that may be caused by the execution of the instructions in this category.

Cross Reference

Mul-

Com-

Un-

Mixed

Floating-

ti-

Instruction Class

Page

Add

Subtract

Multiply

Divide

Shift

pare

Copy

Boolean

Signed

signed

sign

point

Set

plex

Always Reserved

150

Address

150

x

x

x

x

Address Compare

151

x

x

x

Address Compare

151

x

x

x

Floating-point

Address Copy

151

x

Immediate

Address Immediate

152

x

x

x

Address Immediate

152

x

x

x

Reversed

Address Immediate

152

x

x

x

Set

Address Reversed

153

x

x

x

Address Set

153

x

x

x

Address Set

153

x

x

x

Floating-point

Address Shift Left

154

x

x

Immediate Add

Address Shift Left

154

x

x

Immediate Subtract

Address Shift

154

x

x

x

Immediate

Address Ternary

155

x

x

Branch

155

Branch Back

155

Branch Barrier

156

Branch Conditional

156

x

Branch Conditional

157

x

Floating-Point

Branch Conditional

157

x

Visibility Floating-

Point

Branch Down

157

Branch Gateway

121

Branch Halt

158

Branch Hint

132

Branch Hint

158

Immediate

Branch Immediate

158

Branch Immediate

159

Link

Branch Link

159

Load

159

Load Immediate

160

Store

161

Store Double

162

Compare Swap

Store Immediate

163

Store Immediate

163

Inplace

Store Inplace

165

Group Add

123

x

Group Add Halve

167

x

Group Boolean

129

x

Group Compare

167

x

x

x

Group Compare

168

x

x

Floating-point

Group Copy

168

x

Immediate

Group Immediate

168

x

Group Immediate

169

x

x

Reversed

Group Inplace

169

Group Reversed

124

x

x

Group Reversed

169

x

x

x

Floating-point

Group Shift Left

170

x

x

Immediate Add

Group Shift Left

170

x

x

Immediate Subtract

Group Subtract

171

x

x

Halve

Group Ternary

171

x

x

Crossbar

134

Crossbar Extract

135

Crossbar Field

171

Crossbar Field

172

Inplace

Crossbar Inplace

173

Crossbar Short

173

Immediate

Crossbar Short

174

Immediate Inplace

Crossbar Shuffle

137

Crossbar Swizzle

174

Crossbar Ternary

174

Ensemble

124

x

x

x

x

Ensemble Extract

110

x

Ensemble Extract

106

x

Inplace

Ensemble Extract

175

x

Immediate

Ensemble Extract

176

x

x

Immediate Inplace

Ensemble

126

x

x

x

x

Floating-point

Ensemble Inplace

178

x

x

x

x

x

x

Ensemble Inplace

178

x

x

x

x

Floating-point

Ensemble Reversed

126

x

x

x

Floating-point

Ensemble Ternary

180

x

Ensemble Ternary

128

x

Floating-point

Ensemble Unary

181

x

x

x

Ensemble Unary

181

x

x

Floating-point

Wide Convolve

143

x

Extract

Wide Multiply

94

x

Matrix Extract

Wide Multiply

98

x

Matrix Extract

Immediate

Wide Multiply

100

x

x

Matrix Floating-

point

Wide Multiply

102

x

Matrix Galois

Wide Switch

85

Wide Translate

87

Syn-

Ex-

Priv-

chro-

Optimi-

Imme-

Round-

Galois/

Con-

Ex-

Com-

Log

Con-

Over-

cep-

Instruction Class

Page

ilege

nizati

zation

Link

diate

ing

Polyno

volve

tract

Merge

plex

Most

vert

flow

tion

Always Reserved

150

x

Address

150

x

Address Compare

151

x

Address Compare

151

x

Floating-point

Address Copy

151

x

Immediate

Address Immediate

152

x

x

Address Immediate

152

x

Reversed

Address Immediate

152

x

Set

Address Reversed

153

x

Address Set

153

x

Address Set

153

x

Floating-point

Address Shift Left

154

x

Immediate Add

Address Shift Left

154

x

Immediate Subtract

Address Shift

154

x

x

Immediate

Address Ternary

155

Branch

155

Branch Back

155

x

x

Branch Barrier

156

x

Branch Conditional

156

Branch Conditional

157

Floating-Point

Branch Conditional

157

Visibility Floating-

157

Point

Branch Down

157

x

Branch Gateway

121

x

Branch Halt

158

x

Branch Hint

132

x

Branch Hint

158

x

x

Immediate

Branch Immediate

158

x

Branch Immediate

159

x

x

Link

Branch Link

159

x

Load

159

Load Immediate

160

x

Store

161

x

Store Double

162

x

Compare Swap

Store Immediate

163

x

x

Store Immediate

163

x

Inplace

Store Inplace

165

Group Add

123

Group Add Halve

167

x

Group Boolean

129

Group Compare

167

x

Group Compare

168

x

Floating-point

Group Copy

168

x

Immediate

Group Immediate

168

x

Group Immediate

169

x

Reversed

Group Inplace

169

Group Reversed

124

Group Reversed

169

Floating-point

Group Shift Left

170

x

Immediate Add

Group Shift Left

170

x

Immediate Subtract

Group Subtract

171

x

Halve

Group Ternary

171

x

Crossbar

134

x

Crossbar Extract

135

Crossbar Field

171

Crossbar Field

172

Inplace

Crossbar Inplace

173

Crossbar Short

173

x

Immediate

Crossbar Short

174

x

Immediate Inplace

Crossbar Shuffle

137

Crossbar Swizzle

174

Crossbar Ternary

174

Ensemble

124

x

x

x

Ensemble Extract

110

x

x

Ensemble Extract

106

x

x

x

x

Inplace

Ensemble Extract

175

x

x

x

Immediate

Ensemble Extract

176

x

x

x

x

Immediate Inplace

Ensemble

126

x

x

Floating-point

Ensemble Inplace

178

x

Ensemble Inplace

178

x

x

Floating-point

Ensemble Reversed

126

x

Floating-point

Ensemble Ternary

180

x

Ensemble Ternary

128

x

Floating-point

Ensemble Unary

181

x

Ensemble Unary

181

x

x

Floating-point

Wide Convolve

143

Extract

Wide Multiply

93

x

x

Matrix Extract

Wide Multiply

97

x

x

x

Matrix Extract

Immediate

Wide Multiply

100

x

Matrix Floating-

point

Wide Multiply

102

x

Matrix Galois

Wide Switch

85

Wide Translate

87

Format Reference

Instruction Class

Page

Assembler Format

31

30

29

28

27

26

25

24

23

22

21

20

19

18

Always Reserved

150

A.RES imm

A.RES

imm

Address

150

op rd=rc,r

A.MINOR

rd

Address Compare

151

op rd,rc

A.MINOR

rd

Address Compare Floating-point

151

op rd,rc

A.MINOR

rd

Address Copy Immediate

151

A.COPY.I rd=imm

A.COPY.I

rd

Address Immediate

152

op rd=rc,imm

op

rd

Address Immediate Reversed

152

op rd=imm,rc

op

rd

Address Immediate Set

152

op rd=imm,rc

op

rd

Address Reversed

153

op rd=rb,rc

A.MINOR

rd

Address Set

153

op rd=rb,rc

A.MINOR

rd

Address Set Floating-point

153

op rd=rb,rc

A.MINOR

rd

Address Shift Left Immediate Add

154

op rd=rc,rb,i

A.MINOR

rd

Address Shift Left Immediate Subtract

154

op rd=rb,i,rc

A.MINOR

rd

Address Shift Immediate

154

op rd=rc,simm

A.MINOR

rd

Address Ternary

155

A.MUX ra=rd,rc,rb

A.MUX

rd

Branch

155

B rd

B.MINOR

rd

Branch Back

155

B.BACK

B.MINOR

0

Branch Barrier

156

B.BARRIER rd

B.MINOR

rd

Branch Conditional

156

op rd,rc,target

op

rd

Branch Conditional Floating-Point

157

op rd,rc,target

op

rd

Branch Conditional Visibility

157

op rc,rd,target

op

rd

Floating-Point

Branch Down

157

B.DOWN rd

B.MINOR

rd

Branch Gateway

121

B.GATE rb

B.MINOR

0

Branch Halt

158

B.HALT

B.MINOR

0

Branch Hint

132

B.HINT badd,count,rd

B.MINOR

rd

Branch Hint Immediate

158

B.HINT.I badd,count,target

B.HINT.I

simm

Branch Immediate

158

B.I target

B.I

offset

Branch Immediate Link

159

B.LINK.I target

B.LINK.I

offset

Branch Link

159

B.LINK rd=rc

B.MINOR

rd

Load

159

op rd=rc,rb

L.MINOR

rd

Load Immediate

160

op rd=rc,offset

op

rd

Store

161

op rd,rc,rb

S.MINOR

rd

Store Double Compare Swap

162

op rd@rc,rb

S.MINOR

rd

Store Immediate

163

op rd,rc,offset

op

rd

Store Immediate Inplace

163

op rd@rc,offset

op

rd

Store Inplace

165

op rd@rc,rb

S.MINOR

rd

Group Add

123

G.op.size rd=rc,rb

G.size

rd

Group Add Halve

167

G.op.size.rnd rd=rc,rb

G.size

rd

Group Boolean

129

G.BOOLEAN rd@trc,trb,f

G.BOOLEAN

ih

rd

Group Compare

167

G.COM.op.size rd,rc

G.size

rd

Group Compare Floating-point

168

G.COM.op.prec.rnd rd,rc

G.prec

rd

Group Copy Immediate

168

G.COPY.I.size rd=i

G.COPY.I

s

rd

Group Immediate

168

op.size rd=rc,imm

G.op

rd

Group Immediate Reversed

169

op.size rd=imm,rc

G.op

rd

Group Inplace

169

G.op.size rd@rc,rb

G.size

rd

Group Reversed

124

G.op.size rd=rb,rc

G.size

rd

Group Reversed Floating-point

169

G.op.prec.rnd rd=rb,rc

G.prec

rd

Group Shift Left Immediate Add

170

G.op.size rd=rc,rb,i

G.size

rd

Group Shift Left Immediate Subtract

170

G.op.size rd=rb,i,rc

G.size

rd

Group Subtract Halve

171

G.op.size.rnd rd=rb,rc

G.size

rd

Group Ternary

171

G.MUX ra=rd,rc,rb

G.MUX

rd

Crossbar

134

X.op.size rd=rc,rb

X.SHIFT

s

rd

Crossbar Extract

135

X.EXTRACT ra=rd,rc,rb

X.EXTRACT

rd

Crossbar Field

171

X.op.gsize rd=rc,isize,ishift

X.op

ih

rd

Crossbar Field Inplace

172

X.op.gsize rd@rc,isize,ishift

X.op

ih

rd

Crossbar Inplace

173

X.op.size rd@rc,rb

X.SHIFT

s

rd

Crossbar Short Immediate

173

X.op.size rd=rc,shift

X.SHIFTI

rd

Crossbar Short Immediate Inplace

174

X.op.size rd@rc.shift

X.SHIFTI

rd

Crossbar Shuffle

137

X.SHUFFLE.256 rd=rc,rb,v,w,h

X.SHUFFLE

rd

Crossbar Swizzle

174

X.SWIZZLE rd=rc,icopy,iswap

X.SWIZZLE

ih

rd

Crossbar Ternary

174

X.SELECT.8 ra=rd,rc,rb

X.SELECT.8

rd

Ensemble

124

E.op.size rd=rc,rb

E.size

rd

Ensemble Extract

110

E.op ra=rd,rc,rb

E.op

rd

Ensemble Extract Inplace

106

E.op rd@rc,rb,ra

E.op

rd

Ensemble Extract Immediate

175

E.op.size.rnd rd=rc,rb,i

E.op

rd

Ensemble Extract Immediate Inplace

176

E.op.size.rnd rd@rc,rb,i

E.op

Rd

Ensemble Floating-point

126

E.op.prec.rnd rd=rc,rb

E.prec

rd

Ensemble Inplace

178

E.op.size rd@rc,rb

E.size

rd

Ensemble Inplace Floating-point

178

E.op.prec rd@rc,rb

E.prec

rd

Ensemble Reversed Floating-point

126

E.op.prec.rnd rd=rb,rc

E.prec

rd

Ensemble Ternary

180

E.op.G8 ra=rd,rc,rb

E.op

rd

Ensemble Ternary Floating-point

128

E.op.prec ra=rd,rc,rb

E.op.prec

rd

Ensemble Unary

181

E.op.size rd=rc

E.size

rd

Ensemble Unary Floating-point

181

E.op.prec.rnd rd=rc

E.prec

rd

Wide Convolve Extract

143

W.op.size.order rd=rc,rb

W.MINOR.order

rd

Wide Multiply Matrix Extract

93

W.op.order ra=rc,rd,rb

W.op.order

rd

Wide Multiply Matrix Extract Immediate

97

W.op.tsize.order rd=rc,rb,i

W.op.order

rd

Wide Multiply Matrix Floating-point

100

W.op.prec.order rd=rc,rb

W.MINOR.order

rd

Wide Multiply Matrix Galois

102

W.op.order ra=rc,rd,rb

W.op.order

rd

Wide Switch

85

W.op.order ra=rc,rd,rb

W.op.order

rd

Wide Translate

87

W.op.size.order rd=rc,rb

W.op.order

rd

Instruction Class

Page

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Always Reserved

150

imm

Address

150

rc

rb

op

Address Compare

151

rc

op

A.COM

Address Compare Floating-point

151

rc

op

A.COM

Address Copy Immediate

151

imm

Address Immediate

152

rc

imm

Address Immediate Reversed

152

rc

imm

Address Immediate Set

152

rc

imm

Address Reversed

153

rc

rb

op

Address Set

153

rc

rb

op

Address Set Floating-point

153

rc

rb

op

Address Shift Left Immediate Add

154

rc

rb

op

sh

Address Shift Left Immediate Subtract

154

rc

rb

op

sh

Address Shift Immediate

154

rc

simm

op

Address Ternary

155

rc

rb

ra

Branch

155

0

0

B

Branch Back

155

0

0

B.BACK

Branch Barrier

156

0

0

B.BARRIER

Branch Conditional

156

rc

offset

Branch Conditional Floating-Point

157

rc

offset

Branch Conditional Visibility

157

rc

offset

Floating-Point

Branch Down

157

0

0

B.DOWN

Branch Gateway

121

1

rb

B.GATE

Branch Halt

158

0

0

B.BACK

Branch Hint

132

count

simm

B.HINT

Branch Hint Immediate

158

count

offset

Branch Immediate

158

offset

Branch Immediate Link

159

offset

Branch Link

159

rc

0

B.LINK

Load

159

rc

rb

i

op

Load Immediate

160

rc

offset

Store

161

rc

rb

i

op

Store Double Compare Swap

162

rc

rb

0

op

Store Immediate

163

rc

offset

Store Immediate Inplace

163

rc

offset

Store Inplace

165

rc

rb

i

op

Group Add

123

rc

rb

op

Group Add Halve

167

rc

rb

op

rnd

Group Boolean

129

rc

rb

il

Group Compare

167

rc

op

GCOM

Group Compare Floating-point

168

rc

op.rnd

GCOM

Group Copy Immediate

168

sz

imm

Group Immediate

168

rc

sz

imm

Group Immediate Reversed

169

rc

sz

imm

Group Inplace

169

rc

rb

op

Group Reversed

124

rc

rb

op

Group Reversed Floating-point

169

rc

rb

op.rnd

Group Shift Left Immediate Add

170

rc

rb

op

sh

Group Shift Left Immediate Subtract

170

rc

rb

op

sh

Group Subtract Halve

171

rc

rb

op

rnd

Group Ternary

171

rc

rb

ra

Crossbar

134

rc

rb

op

sz

Crossbar Extract

135

rc

rb

ra

Crossbar Field

171

rc

gsfp

gsfs

Crossbar Field Inplace

172

rc

gsfp

gsfs

Crossbar Inplace

173

rc

rb

op

sz

Crossbar Short Immediate

173

rc

simm

op

sz

Crossbar Short Immediate Inplace

174

rc

simm

op

sz

Crossbar Shuffle

137

rc

rb

op

Crossbar Swizzle

174

rc

icopva

iswapa

Crossbar Ternary

174

rc

rb

ra

Ensemble

124

rc

rb

E.op

Ensemble Extract

110

rc

rb

ra

Ensemble Extract Inplace

106

rc

rb

ra

Ensemble Extract Immediate

175

rc

rb

t

sz

sh

Ensemble Extract Immediate Inplace

176

Rc

rb

t

sz

sh

Ensemble Floating-point

126

rc

rb

E.op.rnd

Ensemble Inplace

178

rc

rb

E.op

Ensemble Inplace Floating-point

178

rc

rb

E.op.rnd

Ensemble Reversed Floating-point

126

rc

rb

E.op.rnd

Ensemble Ternary

180

rc

rb

ra

Ensemble Ternary Floating-point

128

rc

rb

ra

Ensemble Unary

181

rc

op

E.UNARY

Ensemble Unary Floating-point

181

rc

op.rnd

E.UNARY

Wide Convolve Extract

143

rc

rb

W.op

sz

Wide Multiply Matrix Extract

93

rc

rb

ra

Wide Multiply Matrix Extract Immediate

97

rc

rb

t

sz

sh

Wide Multiply Matrix Floating-point

100

rc

rb

W.op

pr

Wide Multiply Matrix Galois

102

rc

rb

ra

Wide Switch

85

rc

rb

ra

Wide Translate

87

rc

rb

0

sz

Major Operation Codes

All instructions are 32 bits in size, and use the high order 8 bits to specify a major operation code.

The major field is filled with a value specified by the following table (Blank table entries cause the Reserved Instruction exception to occur.):

The minor field is filled with a value from one of the following tables:

minor operation code field values for A.MINOR

A.MINOR

0

8

16

24

32

40

48

56

0

AAND

ASETE

ASETEF16

ASHLI

ASHLIADD

ASETEF64

1

AADD

AXOR

ASETNE

ASETLGF16

ASETLGF64

2

AADDO

AOR

ASETANDE

ASETLF16

ASHLIO

ASETLF64

3

AADDUO

AANDN

ASETANDNE

ASETGEF16

ASHLIUO

ASETGEF64

4

AORN

ASETL/LZ

ASETEF32

ASHLISUB

5

ASUB

AXNOR

ASETGE/GEZ

ASETLGF32

6

ASUBO

ANOR

ASETLU/GZ

ASETLF32

ASHRI

7

ASUBUO

ANAND

ASETGEU/LEZ

ASETGEF32

ASHRIU

ACOM

minor operation code field values for B.MINOR

B.MINOR

0

8

16

24

32

40

48

56

0

B

1

BLINK

2

BHINT

3

BDOWN

4

BGATE

5

BBACK

6

BHALT

7

BBARRIER

minor operation code field values for L.MINOR

L.

MINOR

0

8

16

24

32

40

48

56

0

L16L

L64L

LU16L

LU64L

1

L16B

L64B

LU16B

LU64B

2

L16AL

L64AL

LU16AL

LU64AL

3

L16AB

L64AB

LU16AB

LU64AB

4

L32L

L128L

LU32L

L8

5

L32B

L128B

LU32B

LU8

6

L32AL

L128AL

LU32AL

7

L32AB

L128AB

LU32AB

minor operation code field values for S.MINOR

S.

MINOR

0

8

16

24

32 40 48 56

0

S16L

S64L

SAS64AL

1

S16B

S64B

SAS64AB

2

S16AL

S64AL

SCS64AL

SDCS64AL

3

S16AB

S64AB

SCS64AB

SDCS64AB

4

S32L

S128L

SMS64AL

S8

5

S32B

S128B

SMS64AB

6

S32AL

S128AL

SMUX64AL

7

S32AB

S128AB

SMUX64AB

minor operation code field values for

G.size

G.size

0

8

16

24

32

40

48

56

0

GSETE

GSETEF

GADDHN

GSUBHN

GSHLIADD

GADDL

1

GADD

GSETNE

GSETLGF

GADDHZ

GSUBHZ

GADDLU

2

GADDO

GSETANDE

GSETLF

GADDHF

GSUBHF

GAAA

3

GADDUO

GSETANDNE

GSETGEF

GADDHC

GSUBHC

4

GSETL/LZ

GSETEF.X

GADDHUN

GSUBHUN

0GSHLISUB

GSUBL

5

GSUB

GSETGE/GEZ

GSETLGF.X

GADDHUZ

GSUBHUZ

GSUBLU

6

GSUBO

GSETLU/GZ

GSETLF.X

GADDHUF

GSUBHUF

GASA

7

GSUBUO

GSETGEU/LEZ

GSETGEF.X

GADDHUC

GSUBHUC

GCOM

minor operation code field values for

XSHIFTI

XSHIFTI

0

8

16

24

32

40

48

56

0

XSHLI

XSHLIO

XSHRI

XEXPANDI

XCOMPRESSI

1

2

3

4

XSHLMI

XSHLIOU

XSHRMI

XSHRIU

XROTLI

XEXPANDIU

XROTRI

XCOMPRESSIU

5

6

7

minor operation code field values for

XSHIFT

XSHIFT

0

8

16

24

32

40

48

56

0

XSHL

XSHLO

XSHR

XEXPAND

XCOMPRESS

1

2

3

4

XSHLM

XSHLOU

XSHRM

XSHRU

XROTL

XEXPANDU

XROTR

XCOMPRESSU

5

6

7

minor operation code field values for

E.size or E.prec

E.size

0

8

16

24

32

40

48

56

0

EMULFN

EMULADDFN

EADDFN

ESUBFN

EMUL

EMULADD

EDIVFN

ECON

1

EMULFZ

EMULADDFZ

EADDFZ

ESUBFZ

EMULU

EMULADDU

EDIVFZ

ECONU

2

EMULFF

EMULADDFF

EADDFF

ESUBFF

EMULM

EMULADDM

EDIVFF

ECONM

3

EMULFC

EMULADDFC

EADDFC

ESUBFC

EMULC

EMULADDC

EDIVFC

ECONC

4

EMULFX

EMULADDFX

EADDFX

ESUBFX

EMULSUM

EMULSUB

EDIVFX

EDIV

5

EMULF

EMULADDF

EADDF

ESUBF

EMULSUMU

EMULSUBU

EDIVF

EDIVU

6

EMULCF

EMULADDCF

ECONF

ECONCF

EMULSUMM

EMULSUBM

EMULSUMF

EMULP

7

EMULSUMCF

EMULSUBCF

EMULSUMC

EMULSUBC

EMULSUBF

EUNARY

minor operation code field values for

W.MINOR.L or W.MINOR.B

W.MINOR.order

0

8

16

24

32

40

48

56

0

WMULMAT8

WMULMATM8

1

WMULMAT16

WMULMATM16

WMULMATF16

2

WMULMAT32

WMULMATM32

WMULMATF32

3

WMULMATF64

4

WMULMATU8

WMULMATC8

WMULMATP8

5

WMULMATU16

WMULMATC16

WMULMATCF16

WMULMATP16

6

WMULMATU32

WMULMATCF32

WMULMATP32

7

For the major operation field values E.MUL.X.I, E.MUL.ADD.X.I, E.CON.X.I, E.EXTRACT.I, W.MUL.MAT.X.I.L, W.MUL.MAT.X.I.B, another six bits in the instruction specify a minor operation code, which indicates operand size, rounding, and shift amount:

The minor field is filled with a value from the following table, where the values are a tuple of the operand format (S [default], U or C) and group (symbol) size (8, 16, 32, 64), and shift amount (0, 1, 2, 3, −4, −5, −6, −7 plus group size). The E.EXTRACT.I instruction provides for signed or unsigned formats, while the other instructions provide for signed or complex formats. The shift amount field value shown below is the “i” value, which is the immediate field in the assembler format.

minor operation code field values for

EMULXI, EMULADDXI, ECONXI,

EEXTRACTI, WMULMATXIL,

WMULMATXIB,

XI

0

8

16

24

32

40

48

56

0

8, 8

16, 16

32, 32

64, 64

U/C 8, 8

U/C 16, 16

U/C 32, 32

U/C 64, 64

1

8, 9

16, 17

32, 33

64, 65

U/C 8, 9

U/C 16, 17

U/C 32, 33

U/C 64, 65

2

8, 10

16, 18

32, 34

64, 66

U/C 8, 10

U/C 16, 18

U/C 32, 34

U/C 64, 66

3

8, 11

16, 19

32, 35

64, 67

U/C 8, 11

U/C 16, 19

U/C 32, 35

U/C 64, 67

4

8, 4

16, 12

32, 28

64, 60

U/C 8, 4

U/C 16, 12

U/C 32, 28

U/C 64, 60

5

8, 5

16, 13

32, 29

64, 61

U/C 8, 5

U/C 16, 13

U/C 32, 29

U/C 64, 61

6

8, 6

16, 14

32, 30

64, 62

U/C 8, 6

U/C 16, 14

U/C 32, 30

U/C 64, 62

7

8, 7

16, 15

32, 31

64, 63

U/C 8, 7

U/C 16, 15

U/C 32, 31

U/C 64, 63

For the major operation field values GCOPYI, two bits in the instruction specify an operand size:

For the major operation field values E.8, E.16, E.32, E.64, E.128, with minor operation field value E.UNARY, another six bits in the instruction specify a unary operation code:

The unary field is filled with a value from the following table:

unary operation code field values for

E.UNARY.size

E.UNARY

0

8

16

24

32

40

48

56

0

ESQRFN

ESUMFN

ESINKFN

EFLOATFN

EDEFLATEFN

ESUM

1

ESQRFZ

ESUMFZ

ESINKFZ

EFLOATFZ

EDEFLATEFZ

ESUMU

ESINKFZD

2

ESQRFF

ESUMFF

ESINKFF

EFLOATFF

EDEFLATEFF

ELOGMOST

ESINKFFD

3

ESQRFC

ESUMFC

ESINKFC

EFLOATFC

EDEFLATEFC

ELOGMOSTU

ESINKFCD

4

ESQRFX

ESUMFX

ESINKFX

EFLOATFX

EDEFLATEFX

ESUMC

5

ESQRF

ESUMF

ESINKF

EFLOATF

EDEFLATEF

ESUMCF

6

ERSQRESTFX

ERECESTFX

EABSFX

ENEGFX

EINFLATEFX

ESUMP

ECOPYFX

7

ERSQRESTF

ERECESTF

EABSF

ENEGF

EINFLATEF

ECOPYF

For the major operation field values A.MINOR and G.MINOR, with minor operation field values A.COM and G.COM, another six bits in the instruction specify a comparison operation code:

The compare field for A.COM is filled with a value from the following table:

compare operation code field values

for A.COM.op.size

A.COM

0

8

16

24

32

40

48

56

0

ACOME

ACOMEF16

ACOMEF64

1

ACOMNE

ACOMLGF16

ACOMLGF64

2

ACOMANDE

ACOMLF16

ACOMLF64

3

ACOMANDNE

ACOMGEF16

ACOMGEF64

4

ACOML

ACOMEF32

5

ACOMGE

ACOMLGF32

6

ACOMLU

ACOMLF32

7

AxCOMGEU

ACOMGEF32

The compare field for G.COM is filled with a value from the following table:

compare operation code field values

for G.COM.op.size

G.COM

0

8

16

24

32

40

48

56

0

GCOME

GCOMEF

1

GCOMNE

GCOMLGF

2

GCOMANDE

GCOMLF

3

GCOMANDNE

GCOMGEF

4

GCOML

GCOMEF.X

5

GCOMGE

GCOMLGF.X

6

GCOMLU

GCOMLF.X

7

GCOMGEU

GCOMGEF.X

General Forms

The general forms of the instructions coded by a major operation code are one of the following:

The general forms of the instructions coded by major and minor operation codes are one of the following:

The general form of the instructions coded by major, minor, and unary operation codes is the following:

General register rd is either a source general register or destination general register, or both. General registers rc and rb are always source general registers. General register ra is either a source general register or a destination general register.

Instruction Fetch

An exemplary embodiment of Instruction Fetch is shown in FIG. 40A.

Perform Exception

An exemplary embodiment of Perform Exception is shown in FIG. 40B.

Instruction Decode

An exemplary embodiment of Instruction Decode is shown in FIG. 40C.

Wide Operations

Particular examples of wide operations which are defined by the present invention include the Wide Switch instruction that performs bit-level switching; the Wide Translate instruction which performs byte (or larger) table lookup; Wide Multiply Matrix; Wide Multiply Matrix Extract and Wide Multiply Matrix Extract Immediate (discussed below), Wide Multiply Matrix Floating-point, and Wide Multiply Matrix Galois (also discussed below). While the discussion below focuses on particular sizes for the exemplary instructions, it will be appreciated that the invention is not limited to a particular width.

Wide Switch

An exemplary embodiment of the Wide Switch instruction is shown in FIGS. 12A-12F. In an exemplary embodiment, the Wide Switch instruction rearranges the contents of up to two registers (256 bits) at the bit level, producing a full-width (128 bits) register result. To control the rearrangement, a wide operand specified by a single register, consisting of eight bits per bit position is used. For each result bit position, eight wide operand bits for each bit position select which of the 256 possible source register bits to place in the result. When a wide operand size smaller than 128 bytes is specified, the high order bits of the memory operand are replaced with values corresponding to the result bit position, so that the memory operand specifies a bit selection within symbols of the operand size, performing the same operation on each symbol.

In an exemplary embodiment, these instructions take an specifier from a general register to fetch a large operand from memory, a second operand from a general register, perform a group of operations on partitions of bits in the operands, and catenate the results together, placing the result in a general register. An exemplary embodiment of the format 1210 of the Wide Switch instruction is shown in FIG. 12A.

An exemplary embodiment of a schematic 1230 of the Wide Switch instruction is shown in FIG. 12B. In an exemplary embodiment, the contents of register rc specifies a virtual address apd optionally an operand size, and a value of specified size is loaded from memory.

The contents of general register rc are used as a wide operand specifier. This specifier determines the virtual address, wide operand size and shape for a wide operand. Using the virtual address and operand size, a value of specified size is loaded from memory.

A second value is the catenated contents of registers rd and rb. Eight corresponding bits from the memory value are used to select a single result bit from the second value, for each corresponding bit position. The group of results is catenated and placed in register ra.

In an exemplary embodiment, the virtual address must either be aligned to 128 bytes, or must be the sum of an aligned address and one-half of the size of the memory operand in bytes. An aligned address must be an exact multiple of the size expressed in bytes. The size of the memory operand must be 8, 16, 32, 64, or 128 bytes. If the address is not valid an “access disallowed by virtual address” exception occurs.

The wide-switch instructions (W.SWITCH.B, W.SWITCH.L) perform a crossbar switch selection of a maximum size limited by the extent of the memory operands, and by the size of the data path. The extent of the memory operands is always specified as powers of two.

Referring to FIG. 12E, the wide operand specifier specifies a memory operand extent (msize) by adding one-half the desired memory operand extent in bytes to the specifier. Valid specifiers for these instructions must specify msize bounded by 64≦msize≦1024. The vertical size for the wide-switch instruction is always 8, so wsize can be inferred to be wsize=msize/8, bounded by 8≦wsize≦128. Exceeding these bounds raises the OperandBoundary exception.

The virtual addresses of the wide operands must be aligned, that is, the byte addresses must be an exact multiple of the operand extent expressed in bytes. If the addresses are not aligned the virtual address cannot be encoded into a valid specifier. Some invalid specifiers cause an “Operand Boundary” exception.

When a size smaller than 128 bits is specified, the high order bits of the memory operand are replaced with values corresponding to the bit position, so that the same memory operand specifies a bit selection within symbols of the operand size, and the same operation is performed on each symbol.

In an exemplary embodiment, a wide switch (W.SWITCH.L or W.SWITCH.B) instruction specifies an 8-bit location for each result bit from the memory operand, that selects one of the 256 bits represented by the catenated contents of registers rd and rb.

An exemplary embodiment of the pseudocode 1250 of the Wide Switch instruction is shown in FIG. 12C. An alternative embodiment of the pseudocode of the Wide Switch instruction is shown in FIG. 12F. An exemplary embodiment of the exceptions 1280 of the Wide Switch instruction is shown in FIG. 12D.

Wide Translate

An exemplary embodiment of the Wide Translate instruction is shown in FIGS. 13A-13G. In an exemplary embodiment, the Wide Translate instructions use a wide operand to specify a table of depth up to 256 entries and width of up to 128 bits. The contents of a register is partitioned into operands of one, two, four, or eight bytes, and the partitions are used to select values from the table in parallel. The depth and width of the table can be selected by specifying the size and shape of the wide operand as described above.

In an exemplary embodiment, these instructions take an specifier from a general register to fetch a large operand from memory, a second operand from a general register, perform a group of operations on partitions of bits in the operands, and catenate the results together, placing the result in a general register. An exemplary embodiment of the format 1310 of the Wide Translate instruction is shown in FIG. 13A.

An exemplary embodiment of the schematic 1330 of the Wide Translate instruction is shown in FIG. 13B. In an exemplary embodiment, the contents of register rc is used as a virtual address, and a value of specified size is loaded from memory.

The contents of general register rc are used as a wide operand specifier. This specifier determines the virtual address, wide operand size and shape for a wide operand. Using the virtual address and operand size, a value of specified size is loaded from memory.

A second value is the contents of register rb. The values are partitioned into groups of operands of a size specified. The low-order bytes of the second group of values are used as addresses to choose entries from one or more tables constructed from the first value, producing a group of values. The group of results is catenated and placed in register rd.

In an exemplary embodiment, by default, the total width of tables is 128 bits, and a total table width of 128, 64, 32, 16 or 8 bits, but not less than the group size may be specified by adding the desired total table width in bytes to the specified address: 16, 8, 4, 2, or 1. When fewer than 128 bits are specified, the tables repeat to fill the 128 bit width.

In an exemplary embodiment, the default depth of each table is 256 entries, or in bytes is 32 times the group size in bits. An operation may specify 4, 8, 16, 32, 64, 128 or 256 entry tables, by adding one half of the memory operand size to the address.

The wide-translate instructions (W.TRANSLATE.L, W.TRANSLATE.B) perform a partitioned vector translation of a maximum size limited by the extent of the memory operands, and by the size of the data path. The extent, size and shape parameters of the memory operands are always specified as powers of two.

Referring to FIG. 13E, the wide operand specifier specifies a memory operand extent (msize) by adding one-half the desired memory operand extent in bytes to the specifier. The wide operand specifier specifies a memory operand shape by adding the desired width in bytes to the specifier. The height of the memory operand (vsize) can be inferred by dividing the operand extent (msize) by the operand width (wsize). Valid specifiers for these instructions must specify wsize bounded by gsize≦wsize≦128, and vsize bounded by 4≦vsize≦2gsize, so msize=wsize*vsize is bounded by 4*wsize≦msize≦2gsize*wsize. Exceeding these bounds raises the OperandBoundary exception.

The virtual addresses of the wide operands must be aligned, that is, the byte addresses must be an exact multiple of the operand extent expressed in bytes. If the addresses are not aligned the virtual address cannot be encoded into a valid specifier. Some invalid specifiers cause an “Operand Boundary” exception.

Table index values are masked to ensure that only the specified portion of the table is used. Tables with just 2 entries cannot be specified; if 2-entry tables are desired, it is recommended to load the entries into registers and use G.MUX to select the table entries.

In an exemplary embodiment, failing to initialize the entire table is a potential security hole, as an instruction in with a small-depth table could access table entries previously initialized by an instruction with a large-depth table. This security hole may be closed either by initializing the entire table, even if extra cycles are required, or by masking the index bits so that only the initialized portion of the table is used. An exemplary embodiment may initialize the entire table with no penalty in cycles by writing to as many as 128 table entries at once. Initializing the entire table with writes to only one entry at a time requires writing 256 cycles, even when the table is smaller. Masking the index bits is the preferred solution.

In an exemplary embodiment, masking the index bits suggests that this instruction, for tables larger than 256 entries, may be extended to a general-purpose memory translate function where the processor performs enough independent load operations to fill the 128 bits. Thus, the 16, 32, and 64 bit versions of this function perform equivalent of 8, 4, 2 withdraw, 8, 4, or 2 load-indexed and 7, 3, or 1 group-extract instructions. In other words, this instruction can be as powerful as 23, 11, or 5 previously existing instructions. The 8-bit version is a single cycle operation replacing 47 existing instructions, so these extensions are not as powerful, but nonetheless, this is at least a 50% improvement on a 2-issue processor, even with one cycle per load timing. To make this possible, the default table size becomes 65536, 2^32 and 2^64 for 16, 32 and 64-bit versions of the instruction.

In an exemplary embodiment, for the big-endian version of this instruction, in the definition below, the contents of register rb is complemented. This reflects a desire to organize the table so that the lowest addressed table entries are selected when the index is zero. In the logical implementation, complementing the index can be avoided by loading the table memory differently for big-endian and little-endian versions; specifically by loading the table into memory so that the highest-addressed table entries are selected when the index is zero for a big-endian version of the instruction. In an exemplary embodiment of the logical implementation, complementing the index can be avoided by loading the table memory differently for big endian and little endian versions. In order to avoid complementing the index, the table memory is loaded differently for big-endian versions of the instruction by complementing the addresses at which table entries are written into the table for a big-endian version of the instruction.

This instruction can perform translations for tables larger than 256 entries when the group size is greater than 8. For tables of this size, copying the wide operand into separate memories to allow simultaneous access at differing addresses is likely to be prohibitive. However, this operation can be performed by producing a stream of addresses in serial fashion to the main memory system, or with whatever degree of parallelism the memory system can provide, such as by interleaving, pipelining, or multiple-porting. To make this possible, the maximum table size becomes 65536, 232 and 264 for 16, 32 and 64-bit versions of the instruction.

An implementation may limit the extent, width or depth of operands due to limits on the operand memory or cache, and thereby cause a ReservedInstruction exception. For example, it may limit the depth of translation tables to 256.

In an exemplary embodiment, the virtual address must either be aligned to 4096 bytes, or must be the sum of an aligned address and one-half of the size of the memory operand in bytes and/or the desired total table width in bytes. An aligned address must be an exact multiple of the size expressed in bytes. The size of the memory operand must be a power of two from 4 to 4096 bytes, but must be at least 4 times the group size and 4 times the total table width. If the address is not valid an “access disallowed by virtual address” exception occurs.

In an exemplary embodiment, a wide translate (W.TRANSLATE.8.L or W.TRANSLATE.8.B) instruction specifies a translation table of 16 entries (vsize=16) in depth, a group size of 1 byte (gsize=8 bits), and a width of 8 bytes (wsize=64 bits) as shown in FIG. 13F. The wide operand specifier specifies a total table size (msize=1024 bits=vsize*wsize) and a table width (wsize=64 bits) by adding one half of the size in bytes of the table (64) and adding the size in bytes of the table width (8) to the table address in the wide operand specifier The operation will create duplicates of this table in the upper and lower 64 bits of the data path, so that 128 bits of operand are processed at once, yielding a 128 bit result. The operation uses the low-order 4 bits of each byte of the contents of general register rb as an address into memory containing byte-wide slices of the wide operand, producing byte results, which are catenated and placed into register rd.

An exemplary embodiment of the pseudocode 1350 of the Wide Translate instruction is shown in FIG. 13C. An alternative embodiment of the pseudocode of the Wide Translate instruction is shown in FIG. 13G. An exemplary embodiment of the exceptions 1380 of the Wide Translate instruction is shown in FIG. 13D.

Wide Multiply Matrix

An exemplary embodiment of the Wide Multiply Matrix instruction is shown in FIGS. 14A-14G. In an exemplary embodiment, the Wide Multiply Matrix instructions use a wide operand to specify a matrix of values of width up to 64 bits (one half of register file and data path width) and depth of up to 128 bits/symbol size. The contents of a general register (128 bits) is used as a source operand, partitioned into a vector of symbols, and multiplied with the matrix, producing a vector of width up to 128 bits of symbols of twice the size of the source operand symbols. The width and depth of the matrix can be selected by specifying the size and shape of the wide operand as described above. Controls within the instruction allow specification of signed, mixed signed, unsigned, complex, or polynomial operands.

In an exemplary embodiment, these instructions take a specifier from a general register to fetch a large operand from memory, a second operand from a general register, perform a group of operations on partitions of bits in the operands, and catenate the results together, placing the result in a general register. An exemplary embodiment of the format 1410 of the Wide Multiply Matrix instruction is shown in FIG. 14A.

An exemplary embodiment of the schematics 1430 and 1460 of the Wide Multiply Matrix instruction is shown in FIGS. 14B and 14C. In an exemplary embodiment, the contents of register rc is used as a virtual address, and a value of specified size is loaded from memory.

The contents of general register rc are used as a wide operand specifier. This specifier determines the virtual address, wide operand size and shape for a wide operand. Using the virtual address and operand size a value of specified size is loaded from memory.

A second value is the contents of register rb. The values are partitioned into groups of operands of the size specified. The second values are multiplied with the first values, then summed in columns, producing a group of result values, each of which is twice the size specified. The group of result values is catenated and placed in register rd.

In an exemplary embodiment, the wide-multiply-matrix instructions (W.MUL.MAT, W.MUL.MAT.C, W.MUL.MAT.M, W.MUL.MAT.P, W.MUL.MAT.U) perform a partitioned array multiply of up to 8192 bits, that is 64×128 bits. The width of the array can be limited to 64, 32, or 16 bits, but not smaller than twice the group size, by adding one half the desired size in bytes to the virtual address operand: 4, 2, or 1. The array can be limited vertically to 128, 64, 32, or 16 bits, but not smaller than twice the group size, by adding one-half the desired memory operand size in bytes to the virtual address operand.

The wide-multiply-matrix instructions (W.MUL.MAT, W.MUL.MAT.C, W.MUL.MAT.M, W.MUL.MAT.P, W.MUL.MAT.U) perform a partitioned array multiply of a maximum size limited by the extent of the memory operands, and by the size of the data path. The extent, size and shape parameters of the memory operands are always specified as powers of two.

Referring to FIG. 14F, the wide operand specifier specifies a memory operand extent (msize) by adding one-half the desired memory operand extent in bytes to the specifier. The wide operand specifier specifies a memory operand shape by adding one-half the desired width in bytes to the specifier. The height of the memory operand (vsize) can be inferred by dividing the operand extent (msize) by the operand width (wsize). Valid specifiers for these instructions must specify wsize bounded by max(16,gsize*(1+n))≦wsize≦64, and msize bounded by 2*wsize≦msize≦(128/(gsize*(1+n))*wsize, where n=0 for real operands (W.MUL.MAT, W.MUL.MAT.M, W.MUL.MAT.P, W.MUL.MAT.U) and n=1 for complex operands (W.MUL.MAT.C). Exceeding these bounds raises the OperandBoundary exception.

In an exemplary embodiment, the virtual address must either be aligned to 1024/gsize bytes (or 512/gsize for W.MUL.MAT.C) (with gsize measured in bits), or must be the sum of an aligned address and one half of the size of the memory operand in bytes and/or one quarter of the size of the result in bytes. An aligned address must be an exact multiple of the size expressed in bytes. If the address is not valid an “access disallowed by virtual address” exception occurs.

The virtual addresses of the wide operands must be aligned, that is, the byte addresses must be an exact multiple of the operand extent expressed in bytes. If the addresses are not aligned the virtual address cannot be encoded into a valid specifier. Some invalid specifiers cause an “Operand Boundary” exception

In an exemplary embodiment, a wide multiply octlets instruction (W.MUL.MAT.type.64, type=NONE M U P) is not implemented and causes a reserved instruction exception, as an ensemble-multiply-sum-octlets instruction (E.MUL.SUM.type.64) performs the same operation except that the multiplier is sourced from a 128-bit register rather than memory. Similarly, instead of wide-multiply-complex-quadlets instruction (W.MUL.MAT.C.32), one should use an ensemble-multiply-complex-quadlets instruction (E.MUL.SUM.C.32).

An exemplary embodiment of the pseudocode 1480 of the Wide Multiply Matrix instruction is shown in FIG. 14D. An alternative embodiment of the pseudocode of the Wide Multiply Matrix instruction is shown in FIG. 14G. An exemplary embodiment of the exceptions 1490 of the Wide Multiply Matrix instruction is shown in FIG. 14E.

Wide Multiply Matrix Extract

An exemplary embodiment of the Wide Multiply Matrix Extract instruction is shown in FIGS. 15A-15H. In an exemplary embodiment, the Wide Multiply Matrix Extract instructions use a wide operand to specify a matrix of value of width up to 128 bits (full width of register file and data path) and depth of up to 128 bits/symbol size. The contents of a general register (128 bits) is used as a source operand, partitioned into a vector of symbols, and multiplied with the matrix, producing a vector of width up to 256 bits of symbols of twice the size of the source operand symbols plus additional bits to represent the sums of products without overflow. The results are then extracted in a manner described below (Enhanced Multiply Bandwidth by Result Extraction), as controlled by the contents of a general register specified by the instruction. The general register also specifies the format of the operands: signed, mixed-signed, unsigned, and complex as well as the size of the operands, byte (8 bit), doublet (16 bit), quadlet (32 bit), or hexlet (64 bit).

In an exemplary embodiment, these instructions take an specifier from a general register to fetch a large operand from memory, a second operand from a general register, perform a group of operations on partitions of bits in the operands, and catenate the results together, placing the result in a general register. An exemplary embodiment of the format 1510 of the Wide Multiply Matrix Extract instruction is shown in FIG. 15A.

An exemplary embodiment of the schematics 1530 and 1560 of the Wide Multiply Matrix Extract instruction is shown in FIGS. 15C and 14D. In an exemplary embodiment, the contents of register rc is used as a virtual address, and a value of specified size is loaded from memory.

The contents of general register rc are used as a wide operand specifier. This specifier determines the virtual address, wide operand size and shape for a wide operands. Using the virtual address and operand size a value of specified size is loaded from memory.

A second value is the contents of register rd. The group size and other parameters are specified from the contents of register rb. The values are partitioned into groups of operands of the size specified and are multiplied and summed, producing a group of values. The group of values is rounded, and limited, and extracted as specified, yielding a group of results which is the size specified. The group of results is catenated and placed in register ra.

In an exemplary embodiment, the size of this operation is determined from the contents of register rb. The multiplier usage is constant, but the memory operand size is inversely related to the group size. Presumably this can be checked for cache validity.

In an exemplary embodiment, low order bits of re are used to designate a size, which must be consistent with the group size. Because the memory operand is cached, the size can also be cached, thus eliminating the time required to decode the size, whether from rb or from rc.

In an exemplary embodiment, the wide multiply matrix extract instructions (W.MUL.MAT.X.B, W.MUL.MAT.X.L) perform a partitioned array multiply of up to 16384 bits, that is 128×128 bits. The width of the array can be limited to 128, 64, 32, or 16 bits, but not smaller than twice the group size, by adding one half the desired size in bytes to the virtual address operand: 8, 4, 2, or 1. The array can be limited vertically to 128, 64, 32, or 16 bits, but not smaller than twice the group size, by adding one half the desired memory operand size in bytes to the virtual address operand.

The size of partitioned operands or group size (gsize) for this operation is determined from the contents of general register rb. We also use low order bits of rc to designate a memory operand width (wsize), which must be consistent with the group size. When the memory operand is cached, the group size and other parameters can also be cached, thus eliminating decode time in critical paths from rb or rc.

The wide-multiply-matrix-extract instructions (W.MUL.MAT.X.B, W.MUL.MAT.X.L) perform a partitioned array multiply of a maximum size limited by the extent of the memory operands, and by the size of the data path. The extent, size and shape parameters of the memory operands are always specified as powers of two.

Referring to FIG. 15G, the wide operand specifier specifies a memory operand extent (msize) by adding one-half the desired memory operand extent in bytes to the specifier. The wide operand specifier specifies a memory operand shape by adding one-half the desired width in bytes to the specifier. The height of the memory operand (vsize) can be inferred by dividing the operand extent (msize) by the operand width. (wsize). Valid specifiers for these instructions must specify wsize bounded by 16≦wsize≦128, and msize bounded by 2*wsize≦msize≦16*wsize. Exceeding these bounds raises the OperandBoundary exception.

As shown in FIG. 15B, in an exemplary embodiment, bits 31 . . . 0 of the contents of register rb specifies several parameters which control the manner in which data is extracted. The position and default values of the control fields allows for the source position to be added to a fixed control value for dynamic computation, and allows for the lower 16 bits of the control field to be set for some of the simpler extract cases by a single GCOPYI instruction.

In an exemplary embodiment, the table below describes the meaning of each label:

label

bits

meaning

fsize

8

field size

dpos

8

destination position

x

1

reserved

s

1

signed vs. unsigned

n

1

complex vs. real multiplication

m

1

mixed-sign vs. same-sign multiplication

l

1

saturation vs. truncation

rnd

2

rounding

gssp

9

group size and source position

In an exemplary embodiment, the 9 bit gssp field encodes both the group size, gsize, and source position, spos, according to the formula gssp=512−4*gsize+spos. The group size, gsize, is a power of two in the range 1 . . . 128. The source position, spos, is in the range 0 . . . (2*gsize)−1.

In an exemplary embodiment, the values in the s, n, m, t, and rnd fields have the following meaning:

values

s

n

m

I

rnd

0

unsigned

real

same-sign

truncate

F

1

signed

complex

mixed-sign

saturate

Z

2

N

3

C

The specified group size (gsize) and type (n: real versus complex) are limited to valid values, but invalid values are silently mapped to valid ones. The group size (gsize) is itself limited by 8≦gsize≦128/vsize and gsize≦wsize. The type specifier (n) is ignored and a real type is assumed if the wsize is not at least twice gsize, or if the vsize is greater than 64/gsize.

In an exemplary embodiment, the virtual address of the wide operands must be aligned, that is, the byte address must be an exact multiple of the operand extent expressed in bytes. If the addresses are not aligned the virtual address cannot be encoded into a valid specifier. Some invalid specifiers cause an “Operand Boundary” exception.

In an exemplary embodiment, Z (zero) rounding is not defined for unsigned extract operations, so F (floor) rounding is substituted, which will properly round unsigned results downward and a ReservedInstruction exception is raised if attempted.

An exemplary embodiment of the pseudocode 1580 of the Wide Multiply Matrix Extract instruction is shown in FIG. 15E. An alternative embodiment of the pseudocode of the Wide Multiply Matrix Extract instruction is shown in FIG. 15H. An exemplary embodiment of the exceptions 1590 of the Wide Multiply Matrix Extract instruction is shown in FIG. 15F.

Wide Multiply Matrix Extract Immediate

An exemplary embodiment of the Wide Multiply Matrix Extract Immediate instruction is shown in FIGS. 16A-16G. In an exemplary embodiment, the Wide Multiply Matrix Extract Immediate instructions perform the same function as above, except that the extraction, operand format and size is controlled by fields in the instruction. This form encodes common forms of the above instruction without the need to initialize a register with the required control information. Controls within the instruction allow specification of signed, mixed signed, unsigned, and complex operands.

In an exemplary embodiment, these instructions take a-specifier from a general register to fetch a large operand from memory, a second operand from a general register, perform a group of operations on partitions of bits in the operands, and catenate the results together, placing the result in a general register. An exemplary embodiment of the format 1610 of the Wide Multiply Matrix Extract Immediate instruction is shown in FIG. 16A.

An exemplary embodiment of the schematics 1630 and 1660 of the Wide Multiply Matrix Extract Immediate instruction is shown in FIGS. 16B and 16C. In an exemplary embodiment, the contents of register rc is used as a virtual address, and a value of specified size is loaded from memory.

The contents of general register rc are used as a wide operand specifier. This specifier determines the virtual address, wide operand size and shape for a wide operand. Using the virtual address and operand size, a value of specified size is loaded from memory

A second value is the contents of register rb. The values are partitioned into groups of operands of the size specified and are multiplied and summed in columns, producing a group of sums. The group of sums is rounded, limited, and extracted as specified, yielding a group of results, each of which is the size specified. The group of results is catenated and placed in register rd. All results are signed, N (nearest) rounding is used, and all results are limited to maximum representable signed values.

In an exemplary embodiment, the wide-multiply-extract-immediate-matrix instructions (W.MUL.MAT.X.I, W.MUL.MAT.X.I.C) perform a partitioned array multiply of up to 16384 bits, that is 128×128 bits. The width of the array can be limited to 128, 64, 32, or 16 bits, but not smaller than twice the group size, by adding one-half the desired size in bytes to the virtual address operand: 8, 4, 2, or 1. The array can be limited vertically to 128, 64, 32, or 16 bits, but not smaller than twice the group size, by adding one half the desired memory operand size in bytes to the virtual address operand.

The wide-multiply-matrix-extract-immediate instructions (W.MUL.MAT.X.I, W.MUL.MAT.X.I.C) perform a partitioned array multiply of a maximum size limited by the extent of the memory operands, and by the size of the data path. The extent, size and shape parameters of the memory operands are always specified as powers of two.

Referring to FIG. 16F, the wide operand specifier specifies a memory operand extent (msize) by adding one-half the desired memory operand extent in bytes to the specifier. The wide operand specifier specifies a memory operand shape by adding one-half the desired width in bytes to the specifier. The height of the memory operand (vsize) can be inferred by dividing the operand extent (msize) by the operand width (wsize). Valid specifiers for these instructions must specify wsize bounded by max(16,gsize*(1+n)≦wsize≦128, and msize bounded by 2*wsize≦msize≦(128/gsize*(1+n))*wsize, where n=0 for real operands (W.MUL.MAT.X.I) and n=1 for complex operands (W.MUL.MAT.X.I.C). Exceeding these bounds raises the OperandBoundary exception.

In an exemplary embodiment, the virtual address must either be aligned to 2048/gsize bytes (or 1024/gsize for W.MUL.MAT.X.I.C), or must be the sum of an aligned address and one-half of the size of the memory operand in bytes and/or one half of the size of the result in bytes. An aligned address must be an exact multiple of the size expressed in bytes. If the address is not valid an “access disallowed by virtual address” exception occurs.

The virtual addresses of the wide operands must be aligned, that is, the byte addresses must be an exact multiple of the operand extent expressed in bytes. If the addresses are not aligned the virtual address cannot be encoded into a valid specifier. Some invalid specifiers cause an “Operand Boundary” exception.

An exemplary embodiment of the pseudocode 1680 of the Wide Multiply Matrix Extract Immediate instruction is shown in FIG. 16D. An exemplary embodiment of the exceptions 1590 of the Wide Multiply Matrix Extract Immediate instruction is shown in FIG. 16E.

Wide Multiply Matrix Floating-Point

An exemplary embodiment of the Wide Multiply Matrix Floating-point instruction is shown in FIGS. 17A-17G. In an exemplary embodiment, the Wide Multiply Matrix Floating-point instructions perform a matrix multiply in the same form as above, except that the multiplies and additions are performed in floating-point arithmetic. Sizes of half (16-bit), single (32-bit), double (64-bit), and complex sizes of half, single and double can be specified within the instruction.

In an exemplary embodiment, these instructions take an specifier from a general register to fetch a large operand from memory, a second operand from a general register, perform a group of operations on partitions of bits in the operands, and catenate the results together, placing the result in a general register. An exemplary embodiment of the format 1710 of the Wide Multiply Matrix Floating point instruction is shown in FIG. 17A.

An exemplary embodiment of the schematics 1730 and 1760 of the Wide Multiply Matrix Floating-point instruction is shown in FIGS. 17B and 17C. In an exemplary embodiment, the contents of register rc is used as a virtual address, and a value of specified size is loaded from memory.

The contents of general register rc are used as a wide operand specifier. This specifier determines the virtual address, wide operand size and shape for a wide operand. Using the virtual address and operand size, a value of specified size is loaded from memory.

A second value is the contents of register rb. The values are partitioned into groups of operands of the size specified. The values are partitioned into groups of operands of the size specified and are multiplied and summed in columns, producing a group of results, each of which is the size specified. The group of result values is catenated and placed in register rd.

In an exemplary embodiment, the wide-multiply-matrix-floating-point instructions (W.MUL.MAT.F, W.MUL.MAT.C.F) perform a partitioned array multiply of up to 16384 bits, that is 128×128 bits. The width of the array can be limited to 128, 64, 32 bits, but not smaller than twice the group size, by adding one-half the desired size in bytes to the virtual address operand: 8, 4, or 2. The array can be limited vertically to 128, 64, 32, or 16 bits, but not smaller than twice the group size, by adding one-half the desired memory operand size in bytes to the virtual address operand.

The wide-multiply-matrix-floating-point instructions (W.MUL.MAT.F, W.MUL.MAT.C.F) perform a partitioned array multiply of a maximum size limited by the extent of the memory operands, and by the size of the data path. The extent, size and shape parameters of the memory operands are always specified as powers of two.

Referring to FIG. 17F, the wide operand specifier specifies a memory operand extent (msize) by adding one-half the desired memory operand extent in bytes to the specifier. The wide operand specifier specifies a memory operand shape by adding one-half the desired width in bytes to the specifier. The height of the memory operand (vsize) can be inferred by dividing the operand extent (msize) by the operand width (wsize). Valid specifiers for these instructions must specify wsize bounded by max(16,gsize*(1+n))≦wsize≦128, and msize bounded by 2*wsize≦msize≦(128/gsize*(1+n))*wsize, where n=0 for real operands (W.MUL.MAT.F) and n=1 for complex operands (W.MUL.MAT.C.F). Exceeding these bounds raises the OperandBoundary exception.

In an exemplary embodiment, the virtual address must either be aligned to 2048/gsize bytes (or 1024/gsize for W.MUL.MAT.C.F), or must be the sum of an aligned address and one half of the size of the memory operand in bytes and/or one-half of the size of the result in bytes. An aligned address must be an exact multiple of the size expressed in bytes. If the address is not valid an “access disallowed by virtual address” exception occurs.

The virtual addresses of the wide operands must be aligned, that is, the byte addresses must be an exact multiple of the operand extent expressed in bytes. If the addresses are not aligned the virtual address cannot be encoded into a valid specifier. Some invalid specifiers cause an “Operand Boundary” exception.

An exemplary embodiment of the pseudocode 1780 of the Wide Multiply Matrix Floating-point instruction is shown in FIG. 17D. Additional pseudocode functions used by this and other floating point instructions is shown elsewhere in this specification. An alternative embodiment of the pseudocode of the Wide Multiply Matrix Floating-point instruction is shown in FIG. 17G. An exemplary embodiment of the exceptions 1790 of the Wide Multiply Matrix Floating-point instruction is shown in FIG. 17E.

Wide Multiply Matrix Galois

An exemplary embodiment of the Wide Multiply Matrix Galois instruction is shown in FIGS. 18A-18F. In an exemplary embodiment, the Wide Multiply Matrix Galois instructions perform a matrix multiply in the same form as above, except that the multiples and additions are performed in Galois field arithmetic. A size of 8 bits can be specified within the instruction. The contents of a general register specify the polynomial with which to perform the Galois field remainder operation. The nature of the matrix multiplication is novel and described in detail below.

In an exemplary embodiment, these instructions take an specifier from a general register to fetch a large operand from memory, second and third operands from general registers, perform a group of operations on partitions of bits in the operands, and catenate the results together, placing the result in a general register. An exemplary embodiment of the format 1810 of the Wide Multiply Matrix Galois instruction is shown in FIG. 18A.

An exemplary embodiment of the schematic 1830 of the Wide Multiply Matrix Galois instruction is shown in FIG. 18B. In an exemplary embodiment, the contents of register re is used as a virtual address, and a value of specified size is loaded from memory.

The contents of general register rc are used as a wide operand specifier. This specifier determines the virtual address, wide operand size and shape for a wide operand. Using the virtual address and operand size, a value of specified size is loaded from memory.

Second and third values are the contents of registers rd and rb. The values are partitioned into groups of operands of the size specified. The second values are multiplied as polynomials with the first value, and summed in columns, producing a group of sums which are reduced to the Galois field specified by the third value, producing a group of result values. The group of result values is catenated and placed in register ra.

In an exemplary embodiment, the wide-multiply-matrix-Galois-bytes instruction (W.MUL.MAT.G.8) performs a partitioned array multiply of up to 16384 bits, that is 128×128 bits. The width of the array can be limited to 128, 64, 32, or 16 bits, but not smaller than twice the group size of 8 bits, by adding one-half the desired size in bytes to the virtual address operand: 8, 4, 2, or 1. The array can be limited vertically to 128, 64, 32, or 16 bits, but not smaller than twice the group size of 8 bits, by adding one-half the desired memory operand size in bytes to the virtual address operand.

The wide-multiply-matrix-Galois-bytes instructgrion (W.MUL.MAT.G.8) performs a partitioned array multiply of a maximum size limited by the extent of the memory operands, and by the size of the data path. The extent, size and shape parameters of the memory operands are always specified as powers of two.

Referring to FIG. 18E, the wide operand specifier specifies a memory operand extent (msize) by adding one-half the desired memory operand extent in bytes to the specifier. The wide operand specifier specifies a memory operand shape by adding one-half the desired width in bytes to the specifier. The height of the memory operand (vsize) can be inferred by dividing the operand extent (msize) by the operand width (wsize). Valid specifiers for these instructions must specify wsize bounded by 16≦wsize≦128, and msize bounded by 2*wsize≦msize≦16*wsize. Exceeding these bounds raises the OperandBoundary exception.

In an exemplary embodiment, the virtual address must either be aligned to 256 bytes, or must be the sum of an aligned address and one-half of the size of the memory operand in bytes and/or one-half of the size of the result in bytes. An aligned address must be an exact multiple of the size expressed in bytes. If the address is not valid an “access disallowed by virtual address” exception occurs.

The virtual addresses of the wide operands must be aligned, that is, the byte addresses must be an exact multiple of the operand extent expressed in bytes. If the addresses are not aligned the virtual address cannot be encoded into a valid specifier. Some invalid specifiers cause an “Operand Boundary” exception

An exemplary embodiment of the pseudocode 1860 of the Wide Multiply Matrix Galois instruction is shown in FIG. 18C. An alternative embodiment of the pseudocode of the Wide Multiply Matrix Galois instruction is shown in FIG. 18F. An exemplary embodiment of the exceptions 1890 of the Wide Multiply Matrix Galois instruction is shown in FIG. 18D.

Memory Operands of Either Little-Endian or Big-Endian Conventional Byte Ordering

In another aspect of the invention, memory operands of either little-endian or big-endian conventional byte ordering are facilitated. Consequently, all Wide operand instructions are specified in two forms, one for little-endian byte ordering and one for big-endian byte ordering, as specified by a portion of the instruction. The byte order specifies to the memory system the order in which to deliver the bytes within units of the data path width (128 bits), as well as the order to place multiple memory words (128 bits) within a larger Wide operand.

Extraction of a High Order Portion of a Multiplier Product or Sum of Products

Another aspect of the present invention addresses extraction of a high order portion of a multiplier product or sum of products, as a way of efficiently utilizing a large multiplier array. Related U.S. Pat. No. 5,742,840 and U.S. Pat. No. 5,953,241 describe a system and method for enhancing the utilization of a multiplier array by adding specific classes of instructions to a general-purpose processor. This addresses the problem of making the most use of a large multiplier array that is fully used for high-precision arithmetic—for example a 64×64 bit multiplier is fully used by a 64-bit by 64-bit multiply, but only one quarter used for a 32-bit by 32-bit multiply) for (relative to the multiplier data width and registers) low-precision arithmetic operations. In particular, operations that perform a great many low-precision multiplies which are combined (added) together in various ways are specified. One of the overriding considerations in selecting the set of operations is a limitation on the size of the result operand. In an exemplary embodiment, for example, this size might be limited to on the order of 128 bits, or a single register, although no specific size limitation need exist.

The size of a multiply result, a product, is generally the sum of the sizes of the operands, multiplicands and multiplier. Consequently, multiply instructions specify operations in which the size of the result is twice the size of identically-sized input operands. For our prior art design, for example, a multiply instruction accepted two 64-bit register sources and produces a single 128-bit register-pair result, using an entire 64×64 multiplier array for 64-bit symbols, or half the multiplier array for pairs of 32-bit symbols, or one quarter the multiplier array for quads of 16-bit symbols. For all of these cases, note that two register sources of 64 bits are combined, yielding a 128-bit result.

In several of the operations, including complex multiplies, convolve, and matrix multiplication, low-precision multiplier products are added together. The additions further increase the required precision. The sum of two products requires one additional bit of precision; adding four products requires two, adding eight products requires three, adding sixteen products requires four. In some prior designs, some of this precision is lost, requiring scaling of the multiplier operands to avoid overflow, further reducing accuracy of the result.

The use of register pairs creates an undesirable complexity, in that both the register pair and individual register values must be bypassed to subsequent instructions. As a result, with prior art techniques only half of the source operand 128-bit register values could be employed toward producing a single-register 128-bit result.

In the present invention, a high-order portion of the multiplier product or sum of products is extracted, adjusted by a dynamic shift amount from a general register or an adjustment specified as part of the instruction, and rounded by a control value from a register or instruction portion as round-to-nearest/even, toward zero, floor, or ceiling. Overflows are handled by limiting the result to the largest and smallest values that can be accurately represented in the output result.

Extract Controlled by a Register

In the present invention, when the extract is controlled by a register, the size of the result can be specified, allowing rounding and limiting to a smaller number of bits than can fit in the result. This permits the result to be scaled to be used in subsequent operations without concern of overflow or rounding, enhancing performance.

Also in the present invention, when the extract is controlled by a register, a single register value defines the size of the operands, the shift amount and size of the result, and the rounding control. By placing all this control information in a single register, the size of the instruction is reduced over the number of bits that such a instruction would otherwise require, improving performance and enhancing flexibility of the processor.

An exemplary embodiment of the Ensemble Extract Inplace instruction is shown in FIGS. 19A-19H. In an exemplary embodiment, several of these instructions (Ensemble Convolve Extract, Ensemble Multiply Add Extract) are typically available only in forms where the extract is specified as part of the instruction. An alternative embodiment can incorporate forms of the operations in which the size of the operand, the shift amount and the rounding can be controlled by the contents of a general register (as they are in the Ensemble Multiply Extract instruction). The definition of this kind of instruction for Ensemble Convolve Extract, and Ensemble Multiply Add Extract would require four source registers, which increases complexity by requiring additional general-register read ports.

In an exemplary embodiment, these operations take operands from four general registers, perform operations on partitions of bits in the operands, and place the concatenated results in a fourth general register. An exemplary embodiment of the format and operation codes 1910 of the Ensemble Extract Inplace instruction is shown in FIG. 19A.

An exemplary embodiment of the schematics 1930, 1945, 1960, and 1975 of the Ensemble Extract Inplace instruction is shown in FIGS. 19C, 19D, 19E, and 19F. In an exemplary embodiment, the contents of registers rd, rc, rb, and ra are fetched. The specified operation is performed on these operands. The result is placed into register rd.

In an exemplary embodiment, for the E.CON.X instruction, the contents of general registers rd and rc are catenated, as c∥d, and used as a first value. A second value is the contents of register rb. The values are partitioned into groups of operands of the size specified and are convolved, producing a group of values. The group of values is rounded, limited and extracted as specified, yielding a group of results that is the size specified. The group of results is catenated and placed in register rd.

In an exemplary embodiment, for the E.MUL.ADD.X instruction, the contents of general registers rc and rb are partitioned into groups of operands of the size specified and are multiplied, producing a group of values to which are added the partitioned and extended contents of general register rd. The group of values is rounded, limited and extracted as specified, yielding a group of results that is the size specified. The group of results is catenated and placed in register rd.

As shown in FIG. 19B, in an exemplary embodiment, bits 31 . . . 0 of the contents of register ra specifies several parameters that control the manner in which data is extracted, and for certain operations, the manner in which the operation is performed. The position of the control fields allows for the source position to be added to a fixed control value for dynamic computation, and allows for the lower 16 bits of the control field to be set for some of the simpler extract cases by a single GCOPYI.128 instruction. The control fields are further arranged so that if only the low order 8 bits are non-zero, a 128-bit extraction with truncation and no rounding is performed.

In an exemplary embodiment, the table below describes the meaning of each label:

label

bits

meaning

fsize

8

field size

dpos

8

destination position

x

1

extended vs. group size result

s

1

signed vs. unsigned

n

1

complex vs. real multiplication

m

1

mixed-sign vs. same-sign multiplication

l

1

limit: saturation vs. truncation

rnd

2

rounding

gssp

9

group size and source position

In an exemplary embodiment, the 9-bit gssp field encodes both the group size, gsize, and source position, spos, according to the formula gssp=512−4*gsize+spos. The group size, gsize, is a power of two in the range 1 . . . 128. The source position, spos, is in the range 0 . . . (2*gsize)−1.

In an exemplary embodiment, the values in the x, s, n, m, l, and rnd fields have the following meaning:

values

x

s

n

m

l

rnd

0

group

unsigned

real

same-sign

truncate

F

1

extended

signed

complex

mixed-sign

saturate

Z

2

N

3

C

These instructions are undefined and cause a reserved instruction exception if the specified group size is less than 8, or larger than 64 when complex or extended, or larger than 32 when complex and extended.

Ensemble Multiply Add Extract

The ensemble-multiply-add-extract instructions (E.MUL.ADD.X), when the x bit is set, multiply the low-order 64 bits of each of the rc and rb general registers and produce extended (double-size) results.

Note that because the contents of general register rd are overwritten by the result vector, that the input vector rc∥rd is catenated with the contents of general register rd on the right, which is a form that is favorable for performing a small convolution (FIR) filter (only 128 bits of filter coefficients) on a little-endian data structure. (The contents of general register rc can be reused by a second E.CON.X instruction that produces the next sequential result.)

Note that general register rd is overwritten, which favors a little-endian data representation as above. Further, the operation expects that the complex values are paired so that the real part is located in a less-significant (to the right of) position and the imaginary part is located in a more-significant (to the left of) position, which is also consistent with conventional little-endian data representation.

An exemplary embodiment of the pseudocode 1990 of Ensemble Extract Inplace instruction is shown in FIG. 19G. Referring to FIG. 19H, in an exemplary embodiment, there are no exceptions for the Ensemble Extract Inplace instruction.

Ensemble Extract

An exemplary embodiment of the Ensemble Extract instruction is shown in FIGS. 20A-20L. In an exemplary embodiment, these operations take operands from three general registers, perform operations on partitions of bits in the operands, and place the catenated results in a fourth register. An exemplary embodiment of the format and operation codes 2010 of the Ensemble Extract instruction is shown in FIG. 20A.

An exemplary embodiment of the schematics 2020, 2030, 2040, 2050, 2060, 2070, and 2080 of the Ensemble Extract Inplace instruction is shown in FIGS. 20C, 20D, 20E, 20F, 20G, 20H, and 20I. In an exemplary embodiment, the contents of general registers rd, rc, and rb are fetched. The specified operation is performed on these operands. The result is placed into register ra.

As shown in FIG. 20B, in an exemplary embodiment, bits 31 . . . 0 of the contents of general register rb specifies several parameters that control the manner in which data is extracted, and for certain operations, the manner in which the operation is performed. The position of the control fields allows for the source position to be added to a fixed control value for dynamic computation, and allows for the lower 16 bits of the control field to be set for some of the simpler extract cases by a single GCOPYI.128 instruction. The control fields are further arranged so that if only the low order 8 bits are non-zero, a 128-bit extraction with truncation and no rounding is performed.

In an exemplary embodiment, the table below describes the meaning of each label:

label

bits

meaning

fsize

8

field size

dpos

8

destination position

x

1

extended vs. group size result

s

1

signed vs. unsigned

n

1

complex vs. real multiplication

m

1

merge vs. extract or mixed-sign vs.

same-sign multiplication

l

1

limit: saturation vs. truncation

rnd

2

rounding

gssp

9

group size and source position

In an exemplary embodiment, the 9-bit gssp field encodes both the group size, gsize, and source position, spos, according to the formula gssp=512 4*gsize+spos. The group size, gsize, is a power of two in the range 1 . . . 128. The source position, spos, is in the range 0 . . . (2*gsize)−1.

In an exemplary embodiment, the values in the x, s, n, m, l, and rnd fields have the following meaning:

values

x

s

n

m

l

rnd

0

group

unsigned

real

extract/

truncate

F

same-sign

1

extended

signed

complex

merge/

saturate

Z

mixed-sign

2

N

3

C

These instructions are undefined and cause a reserved instruction exception if, for E.SCAL.ADD.X instruction, the specified group size is less than 8 or larger than 32, or larger than 16 when complex, or for the E.MUL.X instruction, the specified group size is less than 8 or larger than 64 when complex or extended, or larger than 32 when complex and extended.

In an exemplary embodiment, for the E.SCAL.ADD.X instruction, bits 127 . . . 64 of the contents of register rb specifies the multipliers for the multiplicands in registers rd and rc. Specifically, bits 64+2*gsize−1 . . . 64+gsize is the multiplier for the contents of general register rc, and bits 64+gsize−1 . . . 64 is the multiplier for the contents of general register rd.

Ensemble Multiply Extract

The ensemble-multiply-extract instructions (E.MUL.X), when the x bit is set, multiply the low-order 64 bits of each of the rd and rc general registers and produce extended (double-size) results.

As shown in FIG. 20D, an exemplary embodiment of an ensemble-multiply-extract-doublets-complex instruction (E.MUL.X with n set) multiplies vector rd [h g f e d c b a] by vector rc [p o n m l k j i], yielding the result vector ra [gp+ho go−hp en+fm em−fn cl+dk ck−dl aj+bi ai−bj], rounded and limited as specified by rb31 . . . 0. Note that this instruction prefers an organization of complex numbers in which the real part is located to the right (lower precision) of the imaginary part.

Ensemble Scale Add Extract

An aspect of the present invention defines the Ensemble Scale Add Extract instruction, that combines the extract control information in a register along with two values that are used as scalar multipliers to the contents of two vector multiplicands.

This combination reduces the number of registers that would otherwise be required, or the number of bits that the instruction would otherwise require, improving performance. Another advantage of the present invention is that the combined operation may be performed by an exemplary embodiment with sufficient internal precision on the summation node that no intermediate rounding or overflow occurs, improving the accuracy over prior art operation in which more than one instruction is required to perform this computation.

The ensemble-scale-add-extract instructions (E.SCALADD.X), when the x bit is set, multiply the low-order 64 bits of each of the rd and rc general registers by the rb general register fields and produce extended (double-size) results.

As shown in FIG. 20G, in an exemplary embodiment, for the E.EXTRACT instruction, when m=0 and x=0, the parameters specified by the contents of general register rb are interpreted to select fields from double size symbols of the catenated contents of general registers rd and rc, extracting values which are catenated and placed in general register ra.

As shown in FIG. 20H, in an exemplary embodiment, for an ensemble-merge-extract (E.EXTRACT when m=1), the parameters specified by the contents of general register rb are interpreted to merge fields from symbols of the contents of general register rc with the contents of register rd. The results are catenated and placed in register ra. The x field has no effect when m=1.

As shown in FIG. 20I, in an exemplary embodiment, for an ensemble-expand-extract (E.EXTRACT when m=0 and x=1), the parameters specified by the contents of general register rb are interpreted to extract fields from symbols of the contents of register rc. The results are catenated and placed in general register ra. Note that the value of rd is not used.

An exemplary embodiment of the pseudocode 2090 of Ensemble Extract instruction is shown in FIG. 20J. An alternative embodiment of the pseudocode of Ensemble Extract instruction is shown in FIG. 20L. Referring to FIG. 20K, in an exemplary embodiment, there are no exceptions for the Ensemble Extract instruction.

Reduction of Register Read Ports

Another alternative embodiment can reduce the number of register read ports required for implementation of instructions in which the size, shift and rounding of operands is controlled by a register. The value of the extract control register can be fetched using an additional cycle on an initial execution and retained within or near the functional unit for subsequent executions, thus reducing the amount of hardware required for implementation with a small additional performance penalty. The value retained would be marked invalid, causing a re-fetch of the extract control register, by instructions that modify the register, or alternatively, the retained value can be updated by such an operation. A re-fetch of the extract control register would also be required if a different register number were specified on a subsequent execution. It should be clear that the properties of the above two alternative embodiments can be combined.

Galois Field Arithmetic

Another aspect of the invention includes Galois field arithmetic, where multiplies are performed by an initial binary polynomial multiplication (unsigned binary multiplication with carries suppressed), followed by a polynomial modulo/remainder operation (unsigned binary division with carries suppressed). The remainder operation is relatively expensive in area and delay. In Galois field arithmetic, additions are performed by binary addition with carries suppressed, or equivalently, a bitwise exclusive or operation. In this aspect of the present invention, a matrix multiplication is performed using Galois field arithmetic, where the multiplies and additions are Galois field multiples and additions.

Using prior art methods, a 16 byte vector multiplied by a 16×16 byte matrix can be performed as 256 8-bit Galois field multiplies and 16*15=240 8-bit Galois field additions. Included in the 256 Galois field multiplies are 256 polynomial multiplies and 256 polynomial remainder operations.

By use of the present invention, the total computation is reduced significantly by performing 256 polynomial multiplies, 240 16-bit polynomial additions, and 16 polynomial remainder operations. Note that the cost of the polynomial additions has been doubled compared with the Galois field additions, as these are now 16-bit operations rather than 8-bit operations, but the cost of the polynomial remainder functions has been reduced by a factor of 16. Overall, this is a favorable tradeoff, as the cost of addition is much lower than the cost of remainder.

In yet another aspect of the present invention, best shown in FIG. 4, the present invention employs both decoupled access from execution pipelines and simultaneous multithreading in a unique way. Simultaneous Multithreaded pipelines have been employed in prior art to enhance the utilization of data path units by allowing instructions to be issued from one of several execution threads to each functional unit (e.g. Dean M. Tullsen, Susan J. Eggers, and Henry M. Levy, “Simultaneous Multithreading: Maximizing On Chip Parallelism,” Proceedings of the 22nd Annual International Symposium on Computer Architecture, Santa Margherita Ligure, Italy, June, 1995).

Decoupled access from execution pipelines have been employed in prior art to enhance the utilization of execution data path units by buffering results from an access unit, which computes addresses to a memory unit that in turn fetches the requested items from memory, and then presenting them to an execution unit (e.g. J. E. Smith, “Decoupled Access/Execute Computer Architectures”, Proceedings of the Ninth Annual International Symposium on Computer Architecture, Austin, Tex. (Apr. 26 29, 1982), pp. 112-119).

Compared to conventional pipelines, the Eggers prior art used an additional pipeline cycle before instructions could be issued to functional units, the additional cycle needed to determine which threads should be permitted to issue instructions. Consequently, relative to conventional pipelines, the prior art design had additional delay, including dependent branch delay.

The present invention contains individual access data path units, with associated register files, for each execution thread. These access units produce addresses, which are aggregated together to a common memory unit, which fetches all the addresses and places the memory contents in one or more buffers. Instructions for execution units, which are shared to varying degrees among the threads are also buffered for later execution. The execution units then perform operations from all active threads using functional data path units that are shared.

For instructions performed by the execution units, the extra cycle required for prior art simultaneous multithreading designs is overlapped with the memory data access time from prior art decoupled access from execution cycles, so that no additional delay is incurred by the execution functional units for scheduling resources. For instructions performed by the access units, by employing individual access units for each thread the additional cycle for scheduling shared resources is also eliminated.

This is a favorable tradeoff because, while threads do not share the access functional units, these units are relatively small compared to the execution functional units, which are shared by threads.

With regard to the sharing of execution units, the present invention employs several different classes of functional units for the execution unit, with varying cost, utilization, and performance. In particular, the G units, which perform simple addition and bitwise operations is relatively inexpensive (in area and power) compared to the other units, and its utilization is relatively high. Consequently, the design employs four such units, where each unit can be shared between two threads. The X unit, which performs a broad class of data switching functions is more expensive and less used, so two units are provided that are each shared among two threads. The T unit, which performs the Wide Translate instruction, is expensive and utilization is low, so the single unit is shared among all four threads. The E unit, which performs the class of Ensemble instructions, is very expensive in area and power compared to the other functional units, but utilization is relatively high, so we provide two such units, each unit shared by two threads.

In FIG. 4, four copies of an access unit are shown, each with an access instruction fetch queue A-Queue 401-404, coupled to an access register file AR 405-408, each of which is, in turn, coupled to two access functional units A 409-416. The access units function independently for four simultaneous threads of execution. These eight access functional units A 409-416 produce results for access register files AR 405-408 and addresses to a shared memory system 417. The memory contents fetched from memory system 417 are combined with execute instructions not performed by the access unit and entered into the four execute instruction queues E-Queue 421-424. Instructions and memory data from E-queue 421-424 are presented to execution register files 425-428, which fetches execution register file source operands. The instructions are coupled to the execution unit arbitration unit Arbitration 431, that selects which instructions from the four threads are to be routed to the available execution units E 441 and 449, X 442 and 448, G 443-444 and 446-447, and T 445. The execution register file source operands ER 425-428 are coupled to the execution units 441-445 using source operand buses 451-454 and to the execution units 445-449 using source operand buses 455-458. The function unit result operands from execution units 441-445 are coupled to the execution register file using result bus 461 and the function units result operands from execution units 445-449 are coupled to the execution register file using result bus 462.

Improved Interprivilege Gateway

In a still further aspect of the present invention, an improved interprivilege gateway is described which involves increased parallelism and leads to enhanced performance. In related U.S. patent application Ser. No. 08/541,416, a system and method is described for implementing an instruction that, in a controlled fashion, allows the transfer of control (branch) from a lower privilege level to a higher privilege level. The present invention is an improved system and method for a modified instruction that accomplishes the same purpose but with specific advantages.

Many processor resources, such as control of the virtual memory system itself, input and output operations, and system control functions are protected from accidental or malicious misuse by enclosing them in a protective, privileged region. Entry to this region must be established only though particular entry points, called gateways, to maintain the integrity of these protected regions.

Prior art versions of this operation generally load an address from a region of memory using a protected virtual memory attribute that is only set for data regions that contain valid gateway entry points, then perform a branch to an address contained in the contents of memory. Basically, three steps were involved: load, then branch and check. Compared to other instructions, such as register to register computation instructions and memory loads and stores, and register based branches, this is a substantially longer operation, which introduces delays and complexity to a pipelined implementation.

In the present invention, the branch-gateway instruction performs two operations in parallel: 1) a branch is performed to the Contents of register 0 and 2) a load is performed using the contents of register 1, using a specified byte order (little-endian) and a specified size (64 bits). If the value loaded from memory does not equal the contents of register 0, the instruction is aborted due to an exception. In addition, 3) a return address (the next sequential instruction address following the branch-gateway instruction) is written into register 0, provided the instruction is not aborted. This approach essentially uses a first instruction to establish the requisite permission to allow user code to access privileged code, and then a second instruction is permitted to branch directly to the privileged code because of the permissions issued for the first instruction.

In the present invention, the new privilege level is also contained in register 0, and the second parallel operation does not need to be performed if the new privilege level is not greater than the old privilege level. When this second operation is suppressed, the remainder of the instruction performs an identical function to a branch-link instruction, which is used for invoking procedures that do not require an increase in privilege. The advantage that this feature brings is that the branch-gateway instruction can be used to call a procedure that may or may not require an increase in privilege.

The memory load operation verifies with the virtual memory system that the region that is loaded has been tagged as containing valid gateway data. A further advantage of the present invention is that the called procedure may rely on the fact that register 1 contains the address that the gateway data was loaded from, and can use the contents of register 1 to locate additional data or addresses that the procedure may require. Prior art versions of this instruction required that an additional address be loaded from the gateway region of memory in order to initialize that address in a protected manner—the present invention allows the address itself to be loaded with a “normal” load operation that does not require special protection.

The present invention allows a “normal” load operation to also load the contents of register 0 prior to issuing the branch-gateway instruction. The value may be loaded from the same memory address that is loaded by the branch-gateway instruction, because the present invention contains a virtual memory system in which the region may be enabled for normal load operations as well as the special “gateway” load operation performed by the branch-gateway instruction.

Improved Interprivilege Gateway—System and Privileged Library Calls

An exemplary embodiment of the System and Privileged Library Calls is shown in FIGS. 21A-21 B. An exemplary embodiment of the schematic 2110 of System and Privileged Library Calls is shown in FIG. 21A. In an exemplary embodiment, it is an objective to make calls to system facilities and privileged libraries as similar as possible to normal procedure calls as described above. Rather than invoke system calls as an exception, which involves significant latency and complication, a modified procedure call in which the process privilege level is quietly raised to the required level is used. To provide this mechanism safely, interaction with the virtual memory system is required.

In an exemplary embodiment, such a procedure must not be entered from anywhere other than its legitimate entry point, to prohibit entering a procedure after the point at which security checks are performed or with invalid register contents, otherwise the access to a higher privilege level can lead to a security violation. In addition, the procedure generally must have access to memory data, for which addresses must be produced by the privileged code. To facilitate generating these addresses, the branch-gateway instruction allows the privileged code procedure to rely on the fact that a single register has been verified to contain a pointer to a valid memory region.

In an exemplary embodiment, the branch-gateway instruction ensures both that the procedure is invoked at a proper entry point, and that other registers such as the data pointer and stack pointer can be properly set. To ensure this, the branch-gateway instruction retrieves a “gateway” directly from the protected virtual memory space. The gateway contains the virtual address of the entry point of the procedure and the target privilege level. A gateway can only exist in regions of the virtual address space designated to contain them, and can only be used to access privilege levels at or below the privilege level at which the memory region can be written to ensure that a gateway cannot be forged.

In an exemplary embodiment, the branch-gateway instruction ensures that register 1 (dp) contains a valid pointer to the gateway for this target code address by comparing the contents of register 0 (lp) against the gateway retrieved from memory and causing an exception trap if they do not match. By ensuring that register 1 points to the gateway, auxiliary information, such as the data pointer and stack pointer can be set by loading values located by the contents of register 1. For example, the eight bytes following the gateway may be used as a pointer to a data region for the procedure.

In an exemplary embodiment, before executing the branch-gateway instruction, register 1 must be set to point at the gateway, and register 0 must be set to the address of the target code address plus the desired privilege level. A “L.I.64.L.A r0=r1,0” instruction is one way to set register 0, if register 1 has already been set, but any means of getting the correct value into register 0 is permissible.

In an exemplary embodiment, similarly, a return from a system or privileged routine involves a reduction of privilege. This need not be carefully controlled by architectural facilities, so a procedure may freely branch to a less-privileged code address. Normally, such a procedure restores the stack frame, then uses the branch-down instruction to return.

An exemplary embodiment of the typical dynamic-linked, inter-gateway calling sequence 2130 is shown in FIG. 21B. In an exemplary embodiment, the calling sequence is identical to that of the inter-module calling sequence shown above, except for the use of the B.GATE instruction instead of a B.LINK instruction. Indeed, if a B.GATE instruction is used when the privilege level in the lp register is not higher than the current privilege level, the B.GATE instruction performs an identical function to a B.LINK.

In an exemplary embodiment, the callee, if it uses a stack for local variable allocation, cannot necessarily trust the value of the sp passed to it, as it can be forged. Similarly, any pointers which the callee provides should not be used directly unless it they are verified to point to regions which the callee should be permitted to address. This can be avoided by defining application programming interfaces (APIs) in which all values are passed and returned in registers, or by using a trusted, intermediate privilege wrapper routine to pass and return parameters. The method described below can also be used.

In an exemplary embodiment, it can be useful to have highly privileged code call less-privileged routines. For example, a user may request that errors in a privileged routine be reported by invoking a user-supplied error-logging routine. To invoke the procedure, the privilege can be reduced via the branch-down instruction. The return from the procedure actually requires an increase in privilege, which must be carefully controlled. This is dealt with by placing the procedure call within a lower-privilege procedure wrapper, which uses the branch-gateway instruction to return to the higher privilege region after the call through a secure re-entry point. Special care must be taken to ensure that the less-privileged routine is not permitted to gain unauthorized access by corruption of the stack or saved registers, such as by saving all registers and setting up a new stack frame (or restoring the original lower-privilege stack) that may be manipulated by the less-privileged routine. Finally, such a technique is vulnerable to an unprivileged routine attempting to use the re-entry point directly, so it may be appropriate to keep a privileged state variable which controls permission to enter at the re-entry point.

Improved Interprivilege Gateway—Branch Gateway

An exemplary embodiment of the Branch Gateway instruction is shown in FIGS. 21C-21H. In an exemplary embodiment, this operation provides a secure means to call a procedure, including those at a higher privilege level. An exemplary embodiment of the format and operation codes 2160 of the Branch Gateway instruction is shown in FIG. 21C.

An exemplary embodiment of the schematic 2170 of the Branch Gateway instruction is shown in FIG. 21D. In an exemplary embodiment, the contents of register rb are a branch address in the high-order 62 bits and a new privilege level in the low-order 2 bits. A branch and link occurs to the branch address, and the privilege level is raised to the new privilege level. The high-order. 62 bits of the successor to the current program counter is catenated with the 2-bit current execution privilege and placed in register 0.

In an exemplary embodiment, if the new privilege level is greater than the current privilege level, an octlet of memory data is fetched from the address specified by register 1, using the little-endian byte order and a gateway access type. A GatewayDisallowed exception occurs if the original contents of register 0 do not equal the memory data.

In an exemplary embodiment, if the new privilege level is the same as the current privilege level, no checking of register 1 is performed.

In an exemplary embodiment, an AccessDisallowed exception occurs if the new privilege level is greater than the privilege level required to write the memory data, or if the old privilege level is lower than the privilege required to access the memory data as a gateway, or if the access is not aligned on an 8-byte boundary.

In an exemplary embodiment, a ReservedInstruction exception occurs if the rc field is not one or the rd field is not zero.

In an exemplary embodiment, in the example in FIG. 21 D, a gateway from level 0 to level 2 is illustrated. The gateway pointer, located by the contents of general register rc (1), is fetched from memory and compared against the contents of general register rb (0). The instruction may only complete if these values are equal. Concurrently, the contents of general register rb (0) is placed in the program counter and privilege level, and the address of the next sequential address and privilege level is placed into register rd (0). Code at the target of the gateway locates the data pointer at an offset from the gateway pointer (register 1), and fetches it into general register 1, making a data region available. A stack pointer may be saved and fetched using the data region, another region located from the data region, or a data region located as an offset from the original gateway pointer.

For additional information on the branch-gateway instruction, see the System and Privileged Library Calls section herein.

In an exemplary embodiment, this instruction gives the target procedure the assurances that general register 0 contains a valid return address and privilege level, that general register 1 points to the gateway location, and that the gateway location is octlet aligned. General register 1 can then be used to securely reach values in memory. If no sharing of literal pools is desired, register 1 may be used as a literal pool pointer directly. If sharing of literal pools is desired, general register 1 may be used with an appropriate offset to load a new literal pool pointer; for example, with a one cache line offset from the register 1. Note that because the virtual memory system operates with cache line granularity, that several gateway locations must be created together.

In an exemplary embodiment, software must ensure that an attempt to use any octlet within the region designated by virtual memory as gateway either functions properly or causes a legitimate exception. For example, if the adjacent octlets contain pointers to literal pool locations, software should ensure that these literal pools are not executable, or that by virtue of being aligned addresses, cannot raise the execution privilege level. If general register 1 is used directly as a literal pool location, software must ensure that the literal pool locations that are accessible as a gateway do not lead to a security violation.

In an exemplary embodiment, general register 0 contains a valid return address and privilege level, the value is suitable for use directly in the Branch down (B.DOWN) instruction to return to the gateway callee.

An exemplary embodiment of the pseudocode 2190 of the Branch Gateway instruction is shown in FIG. 21E. An alternative embodiment of the pseudocode of the Branch Gateway instruction is shown in FIG. 21G. An exemplary embodiment of the exceptions 2199 of the Branch Gateway instruction is shown in FIG. 21F.

Group Add

These operations take operands from two general registers, perform operations on partitions of bits in the operands, and place the concatenated results in a third general register.

In accordance with one embodiment of the invention, the processor handles a variety fix-point, or integer, group operations. For example, FIG. 26A presents various examples of Group Add instructions accommodating different operand sizes, such as a byte (8 bits), doublet (16 bits), quadlet (32 bits), octlet (64 bits), and hexlet (128 bits). FIGS. 26B and 26C illustrate an exemplary embodiment of a format and operation codes that can be used to perform the various Group Add instructions shown in FIG. 26A. As shown in FIGS. 26B and 26C, in this exemplary embodiment, the contents of general registers rc and rb are partitioned into groups of operands of the size specified and added, and if specified, checked for overflow or limited, yielding a group of results, each of which is the size specified. The group of results is catenated and placed in register rd. While the use of two operand registers and a different result register is described here and elsewhere in the present specification, other arrangements, such as the use of immediate values, may also be implemented. An alternative embodiment of the pseudocode of the Group Add instruction is shown in FIG. 26D.

In the present embodiment, for example, if the operand size specified is a byte (8 bits), and each register is 128-bit wide, then the content of each register may be partitioned into 16 individual operands, and 16 different individual add operations may take place as the result of a single Group Add instruction. Other instructions involving groups of operands may perform group operations in a similar fashion.

An exemplary embodiment of the exceptions of the Group Add instructions is shown in FIG. 26E.

Group Set and Group Subtract

These operations take two values from general registers, perform operations on partitions of bits in the operands, and place the concatenated results in a general register. Two values are taken from the contents of general registers rc and rb. The specified operation is performed, and the result is placed in general register rd.

Similarly, FIG. 27A presents various examples of Group Set instructions and Group Subtract instructions accommodating different operand sizes. FIGS. 27B and 27C illustrate an exemplary embodiment of a format and operation codes that can be used to perform the various Group Set instructions and Group Subtract instructions. As shown in FIGS. 27B and 27C, in this exemplary embodiment, the contents of registers rc and rb are partitioned into groups of operands of the size specified and for Group Set instructions are compared for a specified arithmetic condition or for Group Subtract instructions are subtracted, and if specified, checked for overflow or limited, yielding a group of results, each of which is the size specified. The group of results is catenated and placed in register rd. An alternative embodiment of the pseudocode of the Group Reversed instructions is shown in FIG. 27D. An exemplary embodiment of the exceptions of the Group Reversed instructions is shown in FIG. 27E.

Ensemble Convolve, Divide, Multiply, Multiply Sum

These operations take operands from two general registers, perform operations on partitions of bits in the operands, and place the concatenated results in a third general register. Two values are taken from the contents of general registers rc and rb. The specified operation is performed, and the result is placed in general register rd.

In the present embodiment, other fix-point group operations are also available. FIG. 28A presents various examples of Ensemble Convolve, Ensemble Divide, Ensemble Multiply, and Ensemble Multiply Sum instructions accommodating different operand sizes. FIGS. 28B and 28C illustrate an exemplary embodiment of a format and operation codes that can be used to perform the various Ensemble Convolve, Ensemble Divide, Ensemble Multiply and Ensemble Multiply Sum instructions. As shown in FIGS. 28B, 28C, and 28J in these exemplary and alternative embodiments, the contents of registers rc and rb are partitioned into groups of operands of the size specified and convolved or divided or multiplied, yielding a group of results, or multiplied and summed to a single result. The group of results is catenated and placed, or the single result is placed, in register rd. An exemplary embodiment of the exceptions of the Ensemble Convolve, Ensemble Divide, Ensemble Multiply, and Ensemble Multiply Sum instructions is shown in FIG. 13K.

An ensemble-multiply (E.MUL) instruction partitions the low-order 64 bits of the contents of general registers rc and rb into elements of the specified format and size, multiplies corresponding elements together and catenates the products, yielding a 128-bit result that is placed in general register rd.

An ensemble-multiply-sum (E.MUL.SUM) instruction partitions the 128 bits of the contents of general registers rc and rb into elements of the specified format and size, multiplies corresponding elements together and sums the products, yielding a 128-bit result that is placed in general register rd.

An ensemble-convolve (E.CON) instruction partitions the contents of general register rc, with the least-significant element ignored, and the low-order 64 bits of the contents of general register rb into elements of the specified format and size, convolves corresponding elements together and catenates the products, yielding a 128-bit result that is placed in general register rd.

An ensemble-divide (E.DIV) instruction divides the low-order 64 bits of contents of general register rc by the low-order 64 bits of the contents of general register rb. The 64-bit quotient and 64-bit remainder are catenated, yielding a 128-bit result that is placed in general register rd.

Ensemble Floating-Point Add, Divide, Multiply, and Subtract

These operations take two values from general registers, perform a group of floating-point arithmetic operations on partitions of bits in the operands, and place the catenated results in a general register.

The contents of general registers rc and rb are combined using the specified floating-point operation. The result is placed in general register rd. The operation is rounded using the specified rounding option or using round-to-nearest if not specified. If a rounding option is specified, the operation raises a floating-point exception if a floating-point invalid operation, divide by zero, overflow, or underflow occurs, or when specified, if the result is inexact. If a rounding option is not specified, floating-point exceptions are not raised, and are handled according to the default rules of IEEE 754.

In accordance with one embodiment of the invention, the processor also handles a variety floating-point group operations accommodating different operand sizes. Here, the different operand sizes may represent floating point operands of different precisions, such as half-precision (16 bits), single-precision (32 bits), double-precision (64 bits), and quad-precision (128 bits). FIG. 29 illustrates exemplary functions that are defined for use within the detailed instruction definitions in other sections and figures. In the functions set forth in FIG. 29, an internal format represents infinite-precision floating-point values as a four-element structure consisting of (1) s (sign bit): 0 for positive, 1 for negative, (2) t (type): NORM, ZERO, SNAN, QNAN, INFINITY, (3) e (exponent), and (4) f: (fraction). The mathematical interpretation of a normal value places the binary point at the units of the fraction, adjusted by the exponent: (−1)^s*(2^e)*f. The function F converts a packed IEEE floating-point value into internal format. The function PackF converts an internal format back into IEEE floating-point format, with rounding and exception control.

FIGS. 30A and 31A present various examples of Ensemble Floating Point Add, Divide, Multiply, and Subtract instructions. FIGS. 30B-C and 31B-C illustrate an exemplary embodiment of formats and operation codes that can be used to perform the various Ensemble Floating Point Add, Divide, Multiply, and Subtract instructions. In these examples, Ensemble Floating Point Add, Divide, and Multiply instructions have been labeled as “EnsembleFloatingPoint.” Also, Ensemble Floating-Point Subtract instructions have been labeled as “EnsembleReversedFloatingPoint.” As shown in FIGS. 30B-C, 31B-C, and 30D in these exemplary and alternative embodiments, the contents of registers rc and rb are partitioned into groups of operands of the size specified, and the specified group operation is performed, yielding a group of results. The group of results is catenated and placed in register rd.

In the present embodiment, the operation is rounded using the specified rounding option or using round-to-nearest if not specified. If a rounding option is specified, the operation raises a floating-point exception if a floating-point invalid operation, divide by zero, overflow, or underflow occurs, or when specified, if the result is inexact. If a rounding option is not specified, floating-point exceptions are not raised, and are handled according to the default rules of IEEE 754.

An exemplary embodiment of the exceptions of the Ensemble Floating Point instructions is shown in FIG. 30E.

Ensemble Scale-Add Floating-Point

A novel instruction, Ensemble-Scale-Add improves processor performance by performing two sets of parallel multiplications and pairwise summing the products. This improves performance for operations in which two vectors must be scaled by two independent values and then summed, providing two advantages over nearest prior art operations of a fused-multiply-add. To perform this operation using prior art instructions, two instructions would be needed, an ensemble-multiply for one vector and one scaling value, and an ensemble-multiply-add for the second vector and second scaling value, and these operations are clearly dependent. In contrast, the present invention fuses both the two multiplies and the addition for each corresponding elements of the vectors into a single operation. The first advantage achieved is improved performance, as in an exemplary embodiment the combined operation performs a greater number of multiplies in a single operation, thus improving utilization of the partitioned multiplier unit. The second advantage achieved is improved accuracy, as an exemplary embodiment may compute the fused operation with sufficient intermediate precision so that no intermediate rounding the products is required.

An exemplary embodiment of the Ensemble Scale-Add Floating-point instruction is shown in FIGS. 22A-22B. In an exemplary embodiment, these operations take three values from general registers, perform a group of floating-point arithmetic operations on partitions of bits in the operands, and place the concatenated results in a general register. An exemplary embodiment of the format 2210 of the Ensemble Scale-Add Floating-point instruction is shown in FIG. 22A. An exemplary embodiment of the exceptions of the Ensemble Scale-Add Floating-point instruction is shown in FIG. 22C.

In an exemplary embodiment, the contents of general registers rd and rc are taken to represent a group of floating-point operands. Operands from general register rd are multiplied with a floating-point operand taken from the least-significant bits of the contents of general register rb and added to operands from general register rc multiplied with a floating-point operand taken from the next least-significant bits of the contents of general register rb. The results are rounded to the nearest representable floating-point value in a single floating-point operation. Floating-point exceptions are not raised, and are handled according to the default rules of IEEE 754. The results are catenated and placed in general register ra.

An exemplary embodiment of the pseudocode 2230 of the Ensemble Scale-Add Floating-point instruction is shown in FIG. 22B. In an exemplary embodiment, there are no exceptions for the Ensemble Scale-Add Floating-point instruction.

Performing a Three-Input Bitwise Boolean Operation in a Single Instruction (Group Boolean)

In a further aspect of the present invention, a system and method is provided for performing a three-input bitwise Boolean operation in a single instruction. A novel method is used to encode the eight possible output states of such an operation into only seven bits, and decoding these seven bits back into the eight states.

An exemplary embodiment of the Group Boolean instruction is shown in FIGS. 23A-23C. In an exemplary embodiment, these operations take operands from three registers, perform boolean operations on corresponding bits in the operands, and place the concatenated results in the third register. An exemplary embodiment of the format 2310 of the Group Boolean instruction is shown in FIG. 23A.

An exemplary embodiment of a procedure 2320 of Group Boolean instruction is shown in FIG. 23B. In an exemplary embodiment, three values are taken from the contents of registers rd, rc and rb. The ih and il fields specify a function of three bits, producing a single bit result. The specified function is evaluated for each bit position, and the results are catenated and placed in register rd. In an exemplary embodiment, register rd is both a source and destination of this instruction.

In an exemplary embodiment, the function is specified by eight bits, which give the result for each possible value of the three source bits in each bit position:

d

1

1

1

1

0

0

0

0

c

1

1

0

0

1

1

0

0

b

1

0

1

0

1

0

1

0

f(d, c, b)

f7

f6

f5

f4

f3

f2

f1

f0

In an exemplary embodiment, a function can be modified by rearranging the bits of the immediate value. The table below shows how rearrangement of immediate value f7 . . . 0 can reorder the operands d,c,b for the same function.

operation

immediate

ƒ(d, c, b)

f7

f6

f5

f4

f3

f2

f1

f0

ƒ(c, d, b)

f7

f6

ƒ3

ƒ2

ƒ5

ƒ4

f1

f0

ƒ(d, b, c)

f7

ƒ5

ƒ6

f4

f3

ƒ1

ƒ2

f0

ƒ(b, c, d)

f7

ƒ3

f5

ƒ1

ƒ6

f2

ƒ4

f0

ƒ(c, b, d)

f7

ƒ5

ƒ3

ƒ1

ƒ6

ƒ4

ƒ2

f0

ƒ(b, d, c)

f7

ƒ3

ƒ6

ƒ2

ƒ5

ƒ1

ƒ4

f0

In an exemplary embodiment, by using such a rearrangement, an operation of the form: b=f(d,c,b) can be recoded into a legal form: b=f(b,d,c). For example, the function: b=f(d,c,b)=d?c:b cannot be coded, but the equivalent function: d=c?b:d can be determined by rearranging the code for d=f(d,c,b)=d?c: b, which is 1001010, according to the rule for f(d,c,b)

f(c,b,d), to the code 11011000.

Encoding

In an exemplary embodiment, some special characteristics of this rearrangement is the basis of the manner in which the eight function specification bits are compressed to seven immediate bits in this instruction. As seen in the table above, in the general case, a rearrangement of operands from f(d,c,b) to f(d,b,c).(interchanging rc and rb) requires interchanging the values of f6 and f5 and the values of f2 and f1.

In an exemplary embodiment, among the 256 possible functions which this instruction can perform, one quarter of them (64 functions) are unchanged by this rearrangement. These functions have the property that f6=f5 and f2=f1. The values of rc and rb (Note that rc and rb are the register specifiers, not the register contents) can be freely interchanged, and so are sorted into rising or falling order to indicate the value of f2. (A special case arises when rc=rb, so the sorting of rc and rb cannot convey information. However, as only the values f7, f4, f3, and f0 can ever result in this case, f6, f5, f2, and f1 need not be coded for this case, so no special handling is required.) These functions are encoded by the values of f7, f6, f4, f3, and f0 in the immediate field and f2 by whether rc>rb, thus using 32 immediate values for 64 functions.

In an exemplary embodiment, another quarter of the functions have f6=1 and f5=0. These functions are recoded by interchanging rc and rb, f6 and f5, f2 and f1. They then share the same encoding as the quarter of the functions where f6=0 and f5=1, and are encoded by the values of f7, f4, f3, f2, f1, and f0 in the immediate field, thus using 64 immediate values for 128 functions.

In an exemplary embodiment, the remaining quarter of the functions have f6=f5 and f2≠f1. The half of these in which f2=1 and f1=0 are recoded by interchanging rc and rb, f6 and f5, f2 and f1. They then share the same encoding as the eighth of the functions where f2=0 and f1=1, and are encoded by the values of f7, f6, f4, f3, and f0 in the immediate field, thus using 32 immediate values for 64 functions.

In an exemplary embodiment, the function encoding is summarized by the table:

f7

f6

f5

f4

f3

f2

f1

f0

trc > trb

ih

il5

il4

il3

il2

il1

il0

rc

rb

f6

f2

f2

0

0

f6

f7

f4

f3

f0

trc

trb

f6

f2

~f2

0

0

f6

f7

f4

f3

f0

trb

trc

f6

0

1

0

1

f6

f7

f4

f3

f0

trc

trb

f6

1

0

0

1

f6

f7

f4

f3

f0

trb

trc

0

1

1

f2

f1

f7

f4

f3

f0

trc

trb

1

0

1

f1

f2

f7

f4

f3

f0

trb

trc

In an exemplary embodiment, the function decoding is summarized by the table:

ih

il5

il4

il3

il2

il1

il0

rc > rb

f7

f6

f5

f4

f3

f2

f1

f0

0

0

0

il3

il4

il4

il2

il1

0

0

il0

0

0

1

il3

il4

il4

il2

il1

1

1

il0

0

1

il3

il4

il4

il2

il1

0

1

il0

1

il3

0

1

il2

il1

il5

il4

il0

From the foregoing discussion, it can be appreciated that an exemplary embodiment of a compiler or assembler producing the encoded instruction performs the steps above to encode the instruction, comparing the f6 and f5 values and the f2 and f1 values of the immediate field to determine which one of several means of encoding the immediate field is to be employed, and that the placement of the trb and trc register specifiers into the encoded instruction depends on the values of f2 (or f1) and f6 (or f5).

An exemplary embodiment of the pseudocode 2330 of the Group Boolean instruction is shown in FIG. 23C. It can be appreciated from the code that an exemplary embodiment of a circuit that decodes this instruction produces the f2 and f1 values, when the immediate bits ih and il5 are zero, by an arithmetic comparison of the register specifiers rc and rb, producing a one (1) value for f2 and f1 when rc>rb. In an exemplary embodiment, there are no exceptions for the Group Boolean instruction. An alternative embodiment of the pseudocode of the Branch Gateway instruction is shown in FIG. 23D. An exemplary embodiment of the exceptions of the instruction is shown in FIG. 23E.

Improving the Branch Prediction of Simple Repetitive Loops of Code

In yet a further aspect to the present invention, a system and method is described for improving the branch prediction of simple repetitive loops of code. In such a simple loop, the end of the loop is indicated by a conditional branch backward to the beginning of the loop. The condition branch of such a loop is taken for each iteration of the loop except the final iteration, when it is not taken. Prior art branch prediction systems have employed finite state machine operations to attempt to properly predict a majority of such conditional branches, but without specific information as to the number of times the loop iterates, will make an error in prediction when the loop terminates.

The system and method of the present invention includes providing a count field for indicating how many times a branch is likely to be taken before it is not taken, which enhances the ability to properly predict both the initial and final branches of simple loops when a compiler can determine the number of iterations that the loop will be performed. This improves performance by avoiding misprediction of the branch at the end of a loop when the loop terminates and instruction execution is to continue beyond the loop, as occurs in prior art branch prediction hardware.

Branch Hint

An exemplary embodiment of the Branch Hint instruction is shown in FIGS. 24A-24C. In an exemplary embodiment, this operation indicates a future branch location specified by a general register value.

In an exemplary embodiment, this instruction directs the instruction fetch unit of the processor that a branch is likely to occur count times at simm instructions following the current successor instruction to the address specified by the contents of general register rd. An exemplary embodiment of the format 2410 of the Branch Hint instruction is shown in FIG. 24A.

In an exemplary embodiment, after branching count times, the instruction fetch unit should presume that the branch at simm instructions following the current successor instruction is not likely to occur. If count is zero, this hint directs the instruction fetch unit that the branch is likely to occur more than 63 times.

In an exemplary embodiment, an Access disallowed exception occurs if the contents of general register rd is not aligned on a quadlet boundary.

An exemplary embodiment of the pseudocode 2430 of the Branch Hint instruction is shown in FIG. 24B. An exemplary embodiment of the exceptions 2460 of the Branch Hint instruction is shown in FIG. 24C.

Incorporating Floating Point Information into Processor Instructions

In a still further aspect of the present invention, a technique is provided for incorporating floating point information into processor instructions. In related U.S. Pat. No. 5,812,439, a system and method are described for incorporating control of rounding and exceptions for floating-point instructions into the instruction itself. The present invention extends this invention to include separate instructions in which rounding is specified, but default handling of exceptions is also specified, for a particular class of floating-point instructions.

Ensemble Sink Floating-Point

In an exemplary embodiment, a Ensemble Sink Floating-point instruction, which converts floating-point values to integral values, is available with control in the instruction that include all previously specified combinations (default-near rounding and default exceptions, Z—round-toward-zero and trap on exceptions, N—round to nearest and trap on exceptions, F—floor rounding (toward minus infinity) and trap on exceptions, C—ceiling rounding (toward plus infinity) and trap on exceptions, and X—trap on inexact and other exceptions), as well as three new combinations (Z.D—round toward zero and default exception handling, F.D—floor rounding and default exception handling, and C.D—ceiling rounding and default exception handling). (The other combinations: N.D is equivalent to the default, and X.D—trap on inexact but default handling for other exceptions is possible but not particularly valuable).

An exemplary embodiment of the Ensemble Sink Floating-point instruction is shown in FIGS. 25A-25C. In an exemplary embodiment, these operations take one value from a register, perform a group of floating-point arithmetic conversions to integer on partitions of bits in the operands, and place the concatenated results in a register. An exemplary embodiment of the operation codes, selection, and format 2510 of Ensemble Sink Floating-point instruction is shown in FIG. 25A.

In an exemplary embodiment, the contents of register rc is partitioned into floating-point operands of the precision specified and converted to integer values. The results are catenated and placed in register rd.

In an exemplary embodiment, the operation is rounded using the specified rounding option or using round-to-nearest if not specified. If a rounding option is specified, unless default exception handling is specified, the operation raises a floating-point exception if a floating-point invalid operation, divide by zero, overflow, or underflow occurs, or when specified, if the result is inexact. If a rounding option is not specified or if default exception handling is specified, floating-point exceptions are not raised, and are handled according to the default rules of IEEE 754.

An exemplary embodiment of the pseudocode 2530 of the Ensemble Sink Floating-point instruction is shown in FIG. 25B. An exemplary embodiment of the exceptions 2560 of the Ensemble Sink Floating-point instruction is shown in FIG. 25C.

An exemplary embodiment of the pseudocode 2570 of the Floating-point instructions is shown in FIG. 25D.

Crossbar Compress, Expand, Rotate, and Shift

These operations take operands from two general registers, perform operations on partitions of bits in the operands, and place the concatenated results in a third general register. Two values are taken from the contents of general registers rc and rb. The specified operation is performed, and the result is placed in general register rd.

In one embodiment of the invention, crossbar switch units such as units 142 and 148 perform data handling operations, as previously discussed. As shown in FIG. 32A, such data handling operations may include various examples of Crossbar Compress, Crossbar Expand, Crossbar Rotate, and Crossbar Shift operations. FIGS. 32B and 32C illustrate an exemplary embodiment of a format and operation codes that can be used to perform the various Crossbar Compress, Crossbar Rotate, Crossbar Expand, and Crossbar Shift instructions. As shown in FIGS. 32B and 32C, in this exemplary embodiment, the contents of register rc are partitioned into groups of operands of the size specified, and compressed, expanded, rotated or shifted by an amount specified by a portion of the contents of register rb, yielding a group of results. The group of results is catenated and placed in register rd.

Various Group Compress operations may convert groups of operands from higher precision data to lower precision data. An arbitrary half-sized sub-field of each bit field can be selected to appear in the result. For example, FIG. 32D shows an X.COMPRESS rd=rc,16,4 operation, which performs a selection of bits 19 . . . 4 of each quadlet in a hexlet. Various Group Shift operations may allow shifting of groups of operands by a specified number of bits, in a specified direction, such as shift right or shift left. As can be seen in FIG. 32C, certain Group Shift Left instructions may also involve clearing (to zero) empty low order bits associated with the shift, for each operand. Certain Group Shift Right instructions may involve clearing (to zero) empty high order bits associated with the shift, for each operand. Further, certain Group Shift Right instructions may involve filling empty high order bits associated with the shift with copies of the sign bit, for each operand.

Extract

In one embodiment of the invention, data handling operations may also include a Crossbar Extract instruction. FIGS. 33A and 33B illustrate an exemplary embodiment of a format and operation codes that can be used to perform the Crossbar Extract instruction. As shown in FIGS. 33A and 33B, in this exemplary embodiment, the contents of general registers rd, rc, and rb are fetched. The specified operation is performed on these operands. The result is placed into general register ra. An alternative embodiment of the pseudocode of the Crossbar Extract instruction is shown in FIG. 33F. An exemplary embodiment of the exceptions of the Crossbar Extract instruction is shown in FIG. 33G.

The Crossbar Extract instruction allows bits to be extracted from different operands in various ways. Specifically, bits 31 . . . 0 of the contents of general register rb specifies several parameters that control the manner in which data is extracted, and for certain operations, the manner in which the operation is performed. The position of the control fields allows for the source position to be added to a fixed control value for dynamic computation, and allows for the lower 16 bits of the control field to be set for some of the simpler extract cases by a single GCOPYI.128 instruction. The control fields are further arranged so that if only the low order 8 bits are non-zero, a 128-bit extraction with truncation and no rounding is performed.

The table below describes the meaning of each label:

label

bits

meaning

fsize

8

field size

dpos

8

destination position

x

1

reserved

s

1

signed vs. unsigned

n

1

reserved

m

1

merge vs. extract

l

1

reserved

rnd

2

reserved

gssp

9

group size and source position

The 9-bit gssp field encodes both the group size, gsize, and source position, spos, according to the formula gssp=512−4*gsize+spos. The group size, gsize, is a power of two in the range 1 . . . 128. The source position, spos, is in the range 0 . . . (2*gsize)−1.

The values in the s, n, m, l, and rnd fields have the following meaning:

values

x

s

n

m

l

rnd

0

group

unsigned

extract

1

extended

signed

merge

2

3

As shown in FIG. 33C, for the X.EXTRACT instruction, when m=0, the parameters are interpreted to select a fields from the catenated contents of registers rd and rc, extracting values which are catenated and placed in register ra. As shown in FIG. 33D, for a crossbar-merge-extract (X.EXTRACT when m=1), the parameters are interpreted to merge a fields from the contents of register rd with the contents of register rc. The results are catenated and placed in register ra.

As shown in FIG. 33C, for the X.EXTRACT instruction, when m=0 and x=0, the parameters specified by the contents of general register rb are interpreted to select a fields from double-size symbols of the catenated contents of general registers rd and rc (as c d), extracting values which are catenated and placed in general register ra

As shown in FIG. 33D, for a crossbar-merge-extract (X.EXTRACT when m=1), the parameters specified by the contents of general register rb are interpreted to merge a fields from symbols of the contents of general register rc with the contents of general register rd. The results are catenated and placed in general register ra. The x field has no effect when m=1.

As shown in FIG. 33E, for an crossbar-expand-extract (X.EXTRACT when m=0 and x=1), the parameters specified by the contents of general register rb are interpreted to extract fields from symbols of the contents of general register rc. The results are catenated and placed in general register ra. Note that the value of rd is not used

Shuffle

As shown in FIG. 34A, in one embodiment of the invention, data handling operations may also include various Shuffle instructions, which allow the contents of registers to be partitioned into groups of operands and interleaved in a variety of ways. FIGS. 34B and 34C illustrate an exemplary embodiment of a format and operation codes that can be used to perform the various Shuffle instructions. As shown in FIGS. 34B and 34C, in this exemplary embodiment, one of two operations is performed, depending on whether the rc and rb fields are equal. Also, FIG. 34B and the description below illustrate the format of and relationship of the rd, rc, rb, op, v, w, h, and size fields. An alternative embodiment is illustrated in FIGS. 34F and 34G. An exemplary embodiment of the exceptions of the Shuffle instructions is shown in FIG. 34H.

In the present embodiment, if the rc and rb fields are equal, a 128-bit operand is taken from the contents of general register rc. Items of size v are divided into w piles and shuffled together, within groups of size bits, according to the value of op. The result is placed in general register rd.

Further, if the rc and rb fields are not equal, the contents of registers rc and rb are catenated into a 256-bit operand as (b∥c). Items of size v are divided into w piles and shuffled together, according to the value of op. Depending on the value of h, a sub-field of op, the low 128 bits (h=0), or the high 128 bits (h=1) of the 256-bit shuffled contents are selected as the result. The result is placed in register rd.

This instruction is undefined and causes a reserved instruction exception if rc and rb are not equal and the op field is greater or equal to 56, or if rc and rb are equal and op4 . . . 0 is greater or equal to 28.

As shown in FIG. 34D, an example of a crossbar 4-way shuffle of bytes within hexlet instruction (X.SHUFFLE.128 rd=rcb,8,4) may divide the 128-bit operand into 16 bytes and partitions the bytes 4 ways (indicated by varying shade in the diagram below). The 4 partitions are perfectly shuffled, producing a 128-bit result. As shown in FIG. 33E, an example of a crossbar 4-way shuffle of bytes within triclet instruction (X.SHUFFLE.256 rd=rc,rb,8,4,0) may catenate the contents of rc and rb, then divides the 256-bit content into 32 bytes and partitions the bytes 4 ways (indicated by varying shade in the diagram below). The low-order halves of the 4 partitions are perfectly shuffled, producing a 128-bit result.

Referring again to FIG. 34D, an alternative embodiment of a crossbar 4-way shuffle of bytes within hexlet instruction (X.SHUFFLE rd=rcb,128,8,4) divides the 128-bit operand into 16 bytes and partitions the bytes 4 ways (indicated by varying shade in the diagram below). The 4 partitions are perfectly shuffled, producing a 128-bit result. Referring again to FIG. 34E, an alternative embodiment of a crossbar 4-way shuffle of bytes within triclet instruction (X.SHUFFLE.PAIR rd=rc,rb,8,4,0) catenates the contents of rc and rb, then divides the 256-bit content into 32 bytes and partitions the bytes 4 ways (indicated by varying shade in the diagram below). The low-order halves of the 4 partitions are perfectly shuffled, producing a 128-bit result.

Changing the last immediate value h to 1 (X.SHUFFLE.256 rd=rc,rb,8,4,1) may modify the operation to perform the same function on the high-order halves of the 4 partitions. Alternatively, changing the last immediate value h to 1 (X.SHUFFLE.PAIR rd=rc,rb,8,4,1) modifies the operation to perform the same function on the high-order halves of the 4 partitions. When rc and rb are equal, the table below shows the value of the op field and associated values for size, v, and w.