The present invention relates to an output buffer device, and more particularly to an output buffer device for temporarily shifting the output voltage level in order to speed up the operation speed.

An example of a typical output buffer device embedded in a semiconductor memory device is shown in FIG. 1, which mainly consists of a control circuit 1 and a drive circuit 2. The control circuit 1 is composed of two NAND gates 1a and 1b, an inverting circuit 1c and a NOR gate 1d. The chip select signal CS of the active high voltage level and the write enable signal WE of the active low voltage level are supplied to the two-input NAND gate 1a, and the semiconductor memory device reads the two-input NAND gate 1a. Generates a strobe signal at the active low voltage level when entering the stage. The NAND gate 1b and the NOR gate 1d have the form of two input nodes, and the internal read data signal DB is distributed to the NAND gate and the NOR gates 1b and 1d. The strobe signal is supplied directly to the NOR gate 1d and is supplied to the NAND gate 1b through the inverting circuit 1c. For this reason, the NOR gate 1d and the NAND gate 1b operate simultaneously when a strobe signal of an active low voltage level is provided and respond to the internal read data signal DB. In other words, when the internal read data signal DB is at the high voltage level corresponding to the logic # 1 level, both the NAND gate 1b and the NOR gate 1d generate output signals of the low voltage level, respectively. However, the NAND gate 1b and the NOR gate 1d shift each output signal to a high voltage level when an internal read data signal DB of a low voltage level or a logic '0' level is provided.

The drive circuit 2 consists of a p-channel increasing field effect transistor 2a and an n-channel increasing field effect transistor 2b of series coupling connected between a source Vcc of a positive voltage level and a ground node. . The common drain node 2c is connected to the inverting circuits 4a, 4b and 4c of the series coupling and the output pin 3. The output signal is supplied from the NAND gate 1b and the NOR gate 1d to the p-channel increased field effect transistor 2a and the n-channel increased field effect transistor 2b, respectively, and the p-channel increased field effect transistor ( 2a), and the n-channel increased field effect transistor 2b are complementarily turned on and off to change the voltage level of the common drain node 2c. Since the driving circuit 2 is required to drive a large amount of parasitic capacitance connected to the output pin 3, the size of the p-channel increased field effect transistor 2a and the n-channel increased field effect transistor 2b is increased. Becomes loud.

If the address signal changes the address at time t1 during the read operation step, the semiconductor memory device allows the data bit of the logic '0' level to be read from the memory cell indicated by the new address, and the internal read data signal. (DB) is attenuated at time t2. As described above, since the strobe signal is supplied to the NAND gate 1b and the NOR gate 1d in advance, the NAND gate 1b and the NOR gate 1d generate output signals of high voltage levels, respectively. The output signal of the high voltage level shifts the n-channel increase type field effect transistor 2b to the on state and the p-channel increase type field effect transistor 2a to the off state. Since a large capacitance parasitic capacitance is connected to the respective gate electrodes of the large component transistors 2a and 2b of the drive circuit 2, the switching speed is relatively slow, and the common drain node 2c has an identification voltage level, for example, For the TTL interface, it takes a long time to reach 0.8V at time t3. Therefore, the conventional output buffer device has a problem that the operation speed is slow.

Another problem inherent in conventional output buffer devices is that noise is generated at the source Vcc and the ground node at a constant voltage level. This is because the large component transistors 2a and 2b allow a large amount of current to flow between the source Vcc of the constant voltage level and the ground node. Such a large amount of current causes undesirable noise.

Therefore, it is an object of the present invention to provide an output buffer device which eliminates the inherent problems of conventional output buffer devices.

In order to achieve this object, the present invention proposes to temporarily shift the voltage level of the common drain node of the driving circuit.

According to the invention, a) a control circuit which forms a first control signal in response to an input signal, b) is complementarily shifted in an on and off state to generate an output signal at an output node between the first and second transistors. A drive circuit consisting of a series combination of a first transistor of a first channel conductivity type and a second transistor of a second channel conductivity type opposite to the first channel conductivity type, c) temporarily storing a previous output signal supplied from an output node And a latching circuit for generating a second control signal, and d) a first input port connected to the control circuit, a second input port connected to the latching circuit, and an output port connected to the first and second transistors. Transmit a second control signal to the first and second transistors in a first stage of operation in response to a timing signal to set an intermediate voltage level between high and low voltage levels at the output node of An output buffer device having a gating circuit for supplying a first control signal to the first and second transistors in a second step operation following a first step is provided. Hereinafter, with reference to the accompanying drawings will be described in detail the features and advantages of the output circuit according to the present invention.

[First Embodiment]

Referring to FIG. 3, a semiconductor memory device having an output buffer device 31 according to the present invention is manufactured on a semiconductor chip 32, and also has an address change identification circuit 33, an addressing device 34, and a memory cell array. (35). The address change identification circuit 33 generally triggers a timing signal generation circuit (not shown), the configuration of which is well known to those skilled in the art. Also, while other peripheral devices are embedded in the semiconductor memory device, they are not shown in FIG. 3 because they are not important for understanding the gist of the present invention. In the following description, logic # 1 'and logic # 0' correspond to a high voltage level and a ground voltage level of about 5V, respectively.

The output buffer device 31 according to the first embodiment mainly controls the control circuit 31a, the drive circuit 31b, the inverting circuit 31c in series coupling, the latching circuit 31d and the catering circuit 31e. Include. But. Since the control circuit 31a, the drive circuit 31b, and the inverting circuit 31c of the series coupling are similar to those of the conventional output buffer device, the same circuit component elements are referred to the same as those in FIG. 1 without detailed description. Add a sign. In this case, the output signal of the NAND gate 1b and the output signal of the NOR gate 1d are combined to form a first control signal, and the p-channel increased field effect transistor 2a and the n-channel increased field effect transistor. 2b acts as a first and a second transistor, respectively. Since the NAND gate and the NOR gate act as inverting circuits when the strobe signal is provided, the first control signal represents the complementary bit of the data bits represented by the internal read data signal DB supplied from the memory cell array 35.

The latching circuit 31d includes two inverting circuits 31da and 31db, and an input node of one of the inverting circuits 31da and 31db forms another flipping circuit 31db to form a flip-flop structure. , 31da). The output node of the inverting circuit 4d is connected to the input node of the inverting circuit 31da, and the output data signal at the common drain node 2c is stored in the latching circuit 31d. In addition, the output node of the inverting circuit 31da is connected in parallel to the input node of the inverting circuits 31dc and 31dd, and the output signal of the inverting circuits 31dc and 31dd serves as the second control signal. The second control signal corresponds to the output data signal supplied from the common drain node 2c.

The gating circuit 31e includes first transfer gates 31ea and 31eb connected between the control circuit 31a and the driving circuit 31b, and a second transfer gate connected between the latching circuit 31d and the driving circuit 31b. 31ec, 31ed). Each of the first and second transfer gates 31ea to 31ed is formed by a parallel combination of a p-channel increasing field effect transistor and an n-channel increasing field effect transistor, and each of the first transfer gates 31ea and 31eb and the second transfer gate. Gates 31ec and 31ed provide a first input port connected to the control circuit 31a and a second input port connected to the latching circuit 31d, respectively. The address change identification circuit 33 generates the timing pulse signal PS at the address change indicated by the address signal, and the timing pulse signal PS is maintained at a high voltage level for a predetermined time period. While the timing pulse signal PS is maintained at the high voltage level, the output buffer device 31 still maintains the first stage of operation. When the timing pulse signal PS is restored from the high voltage level to the voltage level, the output buffer device 31 enters the second stage of operation. The inverting circuit 31ec generates a complementary signal of the timing pulse signal PS, and the first and second transfer gates 31ea to 31ed respond to the timing pulse signal PS and its complementary signal. That is, while the timing pulse signal PS maintains the high voltage level, the second transmission gates 31ec and 31ed are turned on to transmit the second control signal to the driving circuit 31b, and the first transmission gate ( 31ea, 31eb) are db off. However, when the timing pulse signal PS is attenuated to a low voltage level, the first transmission gates 31ea and 31eb are turned on to transmit the first control signal to the driving circuit 31b, and the second transmission gate 31ec is provided. , 31ed) is turned off. Therefore, the gating circuit 31e connects the latching circuit 31d to the drive circuit 31b in the first step operation, and then connects the control circuit 31a to the drive circuit 31b in the second step operation.

The circuit operation of the semiconductor memory device will now be described with reference to FIG. When the address signal is converted from the previous address assigned to the memory cell storing the logical '1' level data bit at time t11 to the new address assigned to the memory cell storing the logical '0' level data bit, Since the latching circuit 31d previously stores an output data signal representing the logic # 1 level, the inverting circuits 31dc and 31dd generate a second control signal of a high voltage level.

At time t12, the address change identification circuit 33 raises the timing pulse signal PS to a high voltage level, and the inverting circuit 31ee generates a complementary signal of the timing pulse signal PS. However, the internal read data signal DB representing the new data bit of the logic '0' level does not reach the control circuit 31a at time t12.

The timing pulse signal PS of the high voltage level and its complementary signal may turn off the first transfer gates 31ea and 31eb and turn on the second transfer gates 31ec and 31ed. The second transfer gates 31ec and 31ed then transfer the second control signal to the gate electrodes of the p-channel increased field effect transistor 2a and the n-channel increased field effect transistor 2b. Due to the second control signal of the high voltage level, the n-channel increase type field effect transistor 2b is shifted to the on state, and the p-channel increase type field effect transistor 2a is shifted to the off state. Then, the common drain node 2c and thus the output pin 3 drop down to about 1.5V. Therefore, the output pin 3 is an internal read data signal DB representing a new data bit at the logic '0' level. Is temporarily shifted to the intermediate voltage level before reaching. After the output pin 3 is attenuated to an intermediate voltage level of about 1.5V, the internal read data signal DB reaches the control circuit 31a, and the NAND gate 1b and the NOR gate 1d are at high voltage levels. Generate a first control signal.

At time t13, the timing pulse signal PS is restored from the high voltage level to the low voltage level, and the timing pulse signal and its complement signal at the low voltage level turn off the second transfer gates 31ec and 41ed. However, the first transfer gates 31ea and 31eb are turned on, and the first control signal of the high voltage level is the gate electrode of the p-channel increased field effect transistor 2a and the gate of the n-channel increased field effect transistor 2b. Supplied to the electrode. Then, the p-channel increased field effect transistor 2a is turned off completely, and the n-channel increased field effect transistor 2b is turned on completely. For this reason, the common drain node 2b and thus the output pin 3 drop from the intermediate voltage level of about 1.5V to the ground voltage level. The common drain node 2c and the output pin 3 pass through the identification level of the TTL interface at time t14, and time period T11 from the arrival of the internal read data signal DB to the 0.8 V awareness level. Is significantly reduced compared to the period T1 (see also FIG. 2) of the conventional output buffer device. The intermediate voltage level can be controlled by adjusting the pulse width of the timing pulse signal PS, and the reason why the intermediate voltage level is adjusted to about 1.5V is that 1.5V is between the identification levels of the TTL interface, that is, between 2.2V and 0.8V. Because it is the emphasis.

When the internal read data signal DB is changed from the logic '0' level to the logic '1' level, the common drain node 2c and thus the output pin 3 are also temporarily shifted to the intermediate voltage level, and then 5V. Rises to the high voltage level. Since the intermediate voltage level is adjusted to the midpoint between two identification levels of the TTL interface, the above-mentioned advantages are also achieved.

As can be seen from the above description, the output data signal representing the new data bit passes quickly through the identification level, and the output buffer device according to the present invention improves the access speed of the external electronic device. Moreover, since the voltage level at the output pin 3 varies step by step between the high voltage level and the battery voltage level through the intermediate voltage level, the amount of current flowing to the ground node at the unit time stage is certainly reduced. This protects the source Vcc and ground node of constant voltage level from undesirable noise.

Second Embodiment

Referring to FIG. 5, another output buffer circuit according to the present invention mainly comprises a control circuit 41a, a driving circuit 41b, an inverting circuit 41c in series coupling, a latching circuit 41d and a gating circuit 41e. It includes. A part of the gating circuit 41e of the second embodiment is composed of a NAND gate 41aa and a NOR gate 41ab of the control circuit 41a, and part of the gating circuit 41e is an inching circuit 41da, 41db of the latching circuit 41d. It is composed. However, since other circuit component elements are similar to those of the first embodiment, the corresponding elements of the second embodiment are given the same reference numerals as in the first embodiment.

In detail, the shape of the NAND gate 41aa is tri-state, as shown in FIG. 6, and two p-channel increasing field effects of series coupling connected between the ground nodes of the source Vcc of the constant voltage level. P-channel increasing field effect transistors Qp2 and Qp6 connected in parallel with transistors Qp1 and Qp2 and three n-channel increasing field effect transistors Qn3, Qn4 and Qn5 and p-channel increasing field effect transistors Qp2. And two n-channel increased field effect transistors Qn3 and Qn4 perform NAND operation, and the p-channel increased field effect transistor Qp1 and the n-channel increased type effect transistor Qp5 have high impedance at the NAND gate 41aa. Let it be. In the high impedance state, the NAND gate 41aa cannot respond to the internal read data signal DB, because the p-channel increased field effect transistor Qp1 and the n-channel increased field effect transistor Qp5 are high voltage. This is because the field effect transistors Qp2, 2n3, Qn4 and Qp6 are separated from the source Vcc and the ground node of the constant voltage level when the timing pulse signal PS of the level is provided. The p-channel increased field effect transistor Qp1, the n-channel increased field effect transistor Qn5 and the inverting circuit IN61 form part of the gating circuit 41e.

Similarly, the shape of the NOR gate 41ab is tri-state, as shown in FIG. 7, and has three p-channel incremental field effect transistors in series coupled between a source of constant voltage level (Vcc) and a ground node. (Qp11, Qp12 and Qp13) and two n-channel increased field effect transistors Qn4 and Qn5, n-channel increased field effect transistor Qn16 connected in parallel with the n-channel increased field effect transistor Qn4, and phosphorus Butting circuit IN71 is included. The p-channel increased field effect transistors Qp12 and Qp13 and the n-channel increased field effect transistors Qn4 and Qn6 perform NOR operation, and the p-channel increased field effect transistor Qp11 and the n-channel increased field effect transistor ( Qn15 separates the NOR gate 41ab from the source Vcc of the constant voltage level and the ground node when the timing pulse signal of the high voltage level is provided. For this reason, the p-channel increased field effect transistor Qn1 and the n-channel increased field effect transistor Qn5 also form part of the gating circuit 41e.

As shown in FIG. 8, each of the inverting circuits 41da and 41db is tri-state, and two p-channel incremental field effect transistors Qp21 and Qp22 and two n-channels in series are combined. Incremental field effect transistors Qn23, Qn24, and inverting circuit IN81. The p-channel increased field effect transistor Qn22 and the n-channel increased field effect transistor Qn23 perform an inverting operation, and the p-channel increased field effect transistor Qp21 and the n-channel increased field effect transistor Qn24 In the absence of the timing pulse signal PS at the high voltage level, the field effect transistors Qp22 and Qn23 are separated from the source Vcc and the ground node at the constant voltage level. In other words, the p-channel increased field effect transistor Qp21 and the n-channel increased field effect transistor Qn24 bring the inverting circuit 41da or 41db into a high impedance state, thus forming a part of the gating circuit 41e. do.

In operation, while the timing pulse signal PS maintains the high voltage level, the NAND gate 41aa and the NOR gate 41ab are brought into a high impedance state, and the inverting circuits 41da and 41db receive the second control signal. Is supplied to the drive circuit 41b. Due to the second control signal, the common drain node 2c and the output node 3 are temporarily shifted to the intermediate voltage level. However, when the timing pulse signal PS recovers from the high voltage level to the low voltage level, the inverting circuits 41da and 41db enter the high impedance state, and the NAND gate 41aa and the NOR gate 41ab receive the first control signal. It is operated to supply to the drive circuit 41b. Therefore, the common drain node 2c and the output node 3 pass quickly through one of the identification levels, and the operation speed is improved as in the first embodiment. The gating circuit 41e is composed of three-state circuits 41aa, 41ab, 41da, 41db, and no transmission gate is connected between the control circuit 41a, the latching circuit 41d, and the driving circuit 41b. This speeds up the transmission of the first and second control signals, and the operation speed is further improved.

While specific embodiments of the invention have been described, those skilled in the art can make various changes and modifications to the invention without departing from the spirit and scope of the invention.

Claims (5)

a) control circuits 31a; 41a for forming a first control signal in response to an input signal DB, b) an on state and an off state for generating an output signal at an output node 2c between the first and second transistors; Drive circuit 31b composed of a series combination of a first channel conductive type first transistor 2a shifted complementarily between states and a second transistor type 2b transistor type 2b conductive type opposite to the first channel conductive type. 41b), c) latching circuits 31d and 41d for temporarily storing a previous output signal supplied from said output node 2c to generate a second control signal, and d) a first input connected to said control circuit Port, a second input port connected to the latching circuit and an output port connected to the first and second transistors, the timing signal for setting an intermediate voltage level between a high and a low voltage level at the output node of the driving circuit. PS, in response to the first stage A gating circuit for transmitting the second control signal to the first and second transistors during a system operation, and for supplying the first control signal to the first and second transistors during a second step operation following a first step. And output buffer devices 31e and 41e.

The output buffer device of claim 1, wherein the first control signal is opposite to the logic level of the input signal, but is the same as the logic level of the second control signal.

3. The latch circuit 31d of claim 2, wherein the latching circuit 31d includes a first inverting circuit 31da / 31db arranged in a flip-flop structure, and a second inverting circuit connected in parallel with an output node of the flip-flop structure. 31dc / 31dd) output buffer device, characterized in that generated at the output node.

4. The gating circuit (31e) according to claim 3, wherein the gating circuit (31e) comprises: first transfer gate means (31ea, 31eb) connected between the control circuit (31a) and the drive circuit (31b), and the latching circuit (31d) and the drive. Second transmission gate means 31ec and 31ed connected between the circuit 31b, wherein the timing signal PS complementarily shifts the first and second transfer gate means between an on state and an off state. Output buffer device, characterized in that.

3. The control circuit 41a of claim 2, wherein the control circuit 41a is configured to provide a NAND gate 41aa in three states responsive to the input signal DB, and a NOR gate 41ab in three states in response to the input signal DB. And the NAND gate of the three states and the NOR gate of the three states generate the first control signal in an active state, and the latching circuit 41d has a fourth inverting circuit 31da arranged in a flip-flop structure. / 31db), and the output node of the fifth inverting circuit of the three state connected in parallel with the output node of the flip-flop structure, the gating circuit 41e is the NAND gate of the three state, And a fifth inverting circuit of the three states selectively controlled between the active state and the high impedance by the NOR gate and the timing signal.