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AR# 64743

UltraScale IODELAY - What is the clock alignment delay

Description

If I read the CNTVALUEOUT of an IDELAYE3 or an ODELAYE3, in either component or native mode with DELAY_FORMAT = TIME and DELAY_VALUE = 0, the value read out is a non zero value.

Why does this occur?

Solution

During calibration, the IDELAYCTRL / BITSLICE_CONTROL will measure the clock alignment delay.

This is the difference in the delays between the data path and the clock path to the capture flip-flop (IDDR, ISERDES, RX_BITSLICE).

The clock alignment delay should be between 50 and 60 Taps with an average of 54 Taps.

The IDELAY applies this clock alignment delay to the delay so that the paths are balanced. If you set your DELAY_VALUE = 500ps, the total amount of TAPs used will also include the clock alignment delay.

If you are calculating the Tap size, remove the clock alignment portion of the delay. You can either measure the clock alignment by having a DELAY_VALUE = 0 during calibration and reading out the resulting CNTVALUEOUT, or use the average of 54 Taps.

For example:

DELAY_VALUE = 500ps and CNTVALUEOUT = 160.

Tap size = 500 / (160-54) = 4.72ps

Note: The clock alignment delay is not included in simulation. If you simulate a component mode IDELAY with DELAY_VALUE = 0, the CNTVALUEOUT will be 0.

If you simulate a native mode IDELAY, for example RX_BITSLICE or RXTX_BITSLICE with DELAY_VALUE = 0, the CNTVALUEOUT will be 8. The 8 taps models the intrinsic delay of the IDELAY not the clock alignment delay.