Suppose you have a 100 MHz CPU and a A/D converter with an 8 kHz sampling rate. Samples of the A/D converter are 32-bits.
What is the sampling rate? and how do I get the formula for the sampling rate?...

As far as I know a 2-way set-associative cache works better than a one-way one considerably but going to 4 and 8-way caches leads to a marginal improvement. My question is: does increasing K (going ...

I am not a computer scientist or even a student of CS. I just want to find more information and would like if someone could put if in right direction about how actually computer works. I understand ...

When I power on my PC it first waits for the Power Good signal, if I understand correctly this works without the CPU and RAM. Then it loads from the ROM into the RAM and executes the BIOS. If either ...

I see in AVX2 instruction set, Intel distinguishes the XOR operations of integer, double and float with different instructions. For Integer there's "VPXORD", and for double "VXORPD", for float "VXORPS"...

A link of capacity 100 Mbps is carrying traffic from a number of sources. Each source generates an on-off traffic stream;when the source is on, the rate of traffic is 10 Mbps, and when the source is ...

If I have a base-10 machine, Do I need a implicit bit or all numbers for mantissa take all bits? When I say bits, I mean digits. Since in a base-2 machine, You have a implicit bit. My question is if ...

My understanding is that computers are basically made of nand gates, and that all other gates, such as and, or, etc, can be made from nand gates.
So far so good, but how do we get from nand gates to ...

Me and a friend were discussing how programming languages can perform asynchronous tasks, like waiting 15 seconds before performing another task, and we started a debate.
I know that computers have ...

To find the meaning of computer architecture terms in Computer Science do I need to use a Computer Science book? Do I need to find the computer architecture terms in a Computer Science Dictionary or ...

Typically, add/subtract/multiply/divide are primitive operations in an Instruction Set Architecture (ISA). I am interested to know if they can instead be implemented efficiently using only bitshift ...

In the ARM architecture, what happens on executing a jump instruction whose jump target address is an MMIO address (or in paging mode, a virtual address that is mapped to an MMIO address)?
Would this ...

An associative cache has a block size of 16 words. The capacity of the cache is 32 Kbytes and main memory can store 4 Mbytes. The word (the addressable unit) size is 2 bytes.
I'm unsure how to find ...

I was tutoring a grade 4 student about CPU and I got confused as there are also the other units of a cpu like arithmetic and logic unit and memory unit. So, is the above statement actually true even ...

I have read that the number of multiplexers required is equal to the number of bits in the TAG field. Is it true? If yes then why?
I know that the size of each multiplexer has to be S to 1, where S ...

I wonder how does particular process gets CPU time or resources whenever it's
required to execute some instructions? When a process is in the idle state or waiting for input, it's not occupying the ...

Assume that a file is written using write(fd, buf, K) system calls, where fd is the file descriptor, and K, the number of files to be written to the current file offset which is a multiple of the disk ...

In which of the following cases a process executing in user model is required to enter into the OS mode?
(a) Decreasing the value of unsigned integer value in a register to less than 0
(b) Accessing ...