190 VLSI Test Principles and Architectures c = 1 f = 1 g = 1 k = 1 e = 1 d = 1 j = 100000 –10 ± FIGURE 4.23 Portion of implication graph for f = 1. 2. Indirect implications : Note that neither j = 1 nor k = 1 implies a logic value on gate x individually. However, if they are taken collectively, they imply x = 1. Thus, indirectly, f = 1 would imply x = 1. This is an indirect implication of f = 1, and it can be computed by performing a logic simulation on the current set of implications of the root node on the circuit. In this example, by inserting the implications of f = 1 into the circuit, followed by a run of logic simulation, x = 1 would be obtained as a result. This new implication is then added as an additional outgoing dashed edge from f = 1 in the implication graph as shown in Figure 4.24. Another nontrivial implication that can be inferred from each indirect implication is based on the contrapositive law. According to the contrapositive law, if ±N²v³ → ±M²w²t

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