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Mentor Graphics{reg} 0-In CDC technology was critical to Sun's overall verification methodology. The processor design maximizes performance and lowers power consumption through an innovative multi-clock architecture in which relatively slow cores share an onboard memory controller and I/O subsystem through a high speed crossbar switch. The result is high throughput with low memory latency and low power. Sun selected the 0-In CDC technology because of its unique ability to thoroughly check ratioed synchronous clocks and lock-up latches as well as asynchronous clocks.

Sun looked at a variety of options to address metastability and other CDC-related issues and decided to use formal verification techniques. After evaluating available technologies, they selected the Mentor Graphics 0-In CDC solution. Close collaboration between Mentor and Sun ensured that the design was free of CDC problems and reached verification closure on schedule.

"We had two or three months to formally verify the crossings," stated Eugena Talvola, senior verification engineer for the Formal Technologies Group at Sun. "Adding to the pressure was the fact that CDC verification was a new area for us. We needed certain features that nobody had. The 0-In CDC product implemented checking for ratioed synchronous clocks and lock-up latches for us. The Mentor team worked with our R&D staff to implement it on a fairly short notice, in time to check the chip."

The UltraSPARC T1 processor had a few hundred ratioed synchronous clocks--synchronous clocks with different frequencies. Ratioed synchronous clocks allow the cores to be much more portable because the memory controller and the I/O subsystem can be quickly modified to meet new requirements or standards without changing the core. The 0-In CDC tool checked lock-up latches used for production testing. Lock-up latches were inserted to delay certain branches of the clock tree by half a cycle. Clock domains can be defined by the user, so clock A and clock B may be branches of the same clock tree if necessary. This is usually used to make sure that a scan chain does not pass through more than one bit per shift cycle due to clock skew. Because the 0-In CDC tool could detect where the clock domain crossings were, it was able to check whether the lock-up latches were in place.

"Sun and Mentor's 0-In team have had a solid working relationship and we are proud of being a vital contributor to the UltraSPARC T1 processor," said Steve White, general manager of Mentor Graphics 0-In functional verification business unit. "We foresee further collaborations with Sun and its OpenSPARC initiative as they continue to deliver innovative open-source multi-threading technologies to the industry."

About Mentor Graphics

Mentor Graphics Corporation (Nasdaq: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world's most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $700 million and employs approximately 4,000 people worldwide. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777; Silicon Valley headquarters are located at 1001 Ridder Park Drive, San Jose, California 95131-2314. World Wide Web site: http://www.mentor.com/.

Mentor Graphics and 0-In are registered trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.

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