Impacts of the Mobile Market Revolution on Process Control in the Semiconductor Industry

Impacts
of the Mobile Market Revolution on Process Control in the Semiconductor
Industry

It
is clear that the accelerating pace of growth and the propensity for rapid
change in the mobility market has fundamentally transformed the semiconductor
industry. Strong consumer demand for smartphones, tablets and other mobile
devices is fueling significant growth within the semiconductor industry, and
the rush to develop differentiated and powerful mobile solutions is driving
rapid change within the entire ecosystem.

More
functionality, higher integration at the chip level, smaller product form
factors, lower power requirements, downward cost pressures and bigger, brighter
screens are just some of the more obvious trends that are driving capital
investment, process technologies and operations methods in the semiconductor
industry. At the same time, new advances
in semiconductor technology are driving an increased pace of innovation within the
mobile device market.

At
the macro level, mobility market requirements are also driving a shift toward
the fab-less design model that uses semiconductor foundries for production. Faster innovation cycles and the growing use
of licensed IP content, such as ARM processor cores, are making it more
advantageous in many cases to separate design from production. Fabless companies such as Apple, Qualcomm,
Nvidia, Broadcom, SanDisk and Mediatek are at the center of these changes. While this is a positive trend for the
industry and innovation, it also presents some additional challenges in terms
of unifying end-to-end processes and ensuring optimal yields that conform to
the design intent.

From
a process control and yield management perspective, the mobility revolution has
some very significant implications, regardless of whether the design and fab processes
are in-house or separated. Accelerated
design, introduction and ramp-to-revenue schedules require process control
solutions that can lead the way to deliver yield targets, even as new
semiconductor technologies are being introduced in parallel with new mobile
product generations. Missed yield
targets can result in a significant increase in costs, lost revenue and future
business opportunities for semiconductor manufacturers.

Mobility
demands are driving increased complexity throughout the semiconductor
ecosystem, which results in more difficulty in achieving yield ramps. Smaller feature sizes require better defect
detection and more accurate metrology and new materials used in processing
create new defects and measurement challenges.
On the process side, complex lithography (multiple patterning and the future
implementation of EUV), more critical interconnect layers, and the move from 2D
to 3D gate and memory structures are simultaneously complicating the process
control challenges and adding an additional level of complexity.

Figure 1 - Mobility Driving Increased
Complexity

Defect
detection and metrology control amid these rising levels of design and process
complexity is critical for achieving yield targets, which means that process
control tool performance needs to actually improve faster than the underlying
semiconductor technologies.

Figure 2 - Defect and Yield Targets Driving
Metrology Performance

Another
major factor that can impact process control requirements is the increase or maintenance
of a larger die size for the semiconductor devices that form the heart of
new-generation Smartphones and tablets. When
die sizes increase, it means that simply maintaining the same defect density
will no longer be sufficient. For every
doubling of the die size, the number of die on a given wafer size is cut in
half. Therefore, merely maintaining the
same defect density and yielded die level will necessitate a doubling of the
number of wafer starts to achieve the same production output.

For
example, the evolution of a popular mobile device processor shows that even
though design rules are shrinking, the need to increase processor performance
drives a larger die size. The second
generation of this processor was built with a 45nm design rule and was approximately
70mm2, while subsequent generations of the processor increased in size to
~100mm2 and ~125mm2, even when moving to a smaller design rule (32nm). An increase in die size from 70mm2 to 125mm2
means that the die per wafer would drop from approximately 810 to 465. Assuming the same defect density, for a
production output objective of 100 million good parts, this would mean
approximately 214 thousand additional wafer starts would be required for the
larger die size (See figure 3). At a
cost of ~$3,000 to $4,000 per wafer, the impact of lower yields can drive
manufacturing costs into the hundreds of millions -to billions of dollars.

Figure 3 - Larger Die Sizes Require Lower
Defect Densities

While
many in the semiconductor industry would point to larger 450mm wafer sizes as a
partial solution to addressing these cost/yield challenges, the reality is that
transitioning to 450mm wafers presents a whole new set of metrology, inspection
and process control challenges as well.
In order to achieve 450mm productivity projections, M&I equipment
will need to lead by maintaining wafer flatness, surface roughness, and other
key factors at incoming, as well as providing larger stages for full-wafer
pattern inspection throughput and driving down defect densities to improve die
yields per wafer. With more cost at
stake per 450mm wafer, the role of process control will become even more
critical.

The
shift toward fab-less design and licensed IP has also opened opportunities for
new process control solutions that include built-in design-awareness
capabilities to help smooth the transition to the foundry and to support a
faster yield ramp.

All
of these challenges need to be addressed within the context of ever-shortening
product life cycles within the consumer marketplace. Time to market has become a make-or-break
factor for mobile device makers. Being
late to the market window not only can significantly impact profitability, in
some cases missing market expectations can irreparably harm a company’s
reputation.

While
these market expectation pressures get a lot of press coverage and buzz in the
end-product arena, the actual pressures to perform ripple all the way down the
semiconductor ecosystem. If suppliers
are not able to meet the higher complexities, faster introductions, yield ramps
and cost targets required for each new generation of mobile devices, they will
be out of the game – and out of business.
With the pace of change only getting faster and the stakes higher,
process control providers actually must stay ahead of the game to assure that
their customers can stay in it.

Brian Trafas serves as
the chief marketing officer of KLA-Tencor, where he is responsible for
overseeing marketing initiatives, product development, marketing
communications, market research, and the development of marketing talent. With
two decades of experience in the semiconductor capital equipment industry, with
an emphasis on process control, Trafas is a sought-after author having
contributed more than 30 technical papers. He has written extensively about CD
process control, advanced patterned wafer inspection methodologies and the
application of scanning probe microscopes. Currently, Trafas is the
chairman of the SEMI North America Advisory Board, leading multiple
constituencies in the advancement of semiconductor technology.