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Abstract

This arbitration scheme establishes a sequence to handle changes in real time demands for bus traffic. This scheme allows subunits with lower priority a guaranteed percentage of high priority and also prevents dead cycles of arbitration associated with simple rotating high priority arbiters. The standard arbiter 6 has a fixed priority in descending order and has been improved so that devices with lower priority, with critical time dependencies, may have highest priority a certain percentage of the time, when arbitration is possible. In this example, there are eight subunits that would be requesting access to the bus. Some of these subunits may need to have highest priority at least part of the time. The new arbiter circuit achieves this rotating priority in the following manner.

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Bus Arbiter With Selectable Rotating Highest Priority

This arbitration scheme establishes a sequence to handle changes in real time
demands for bus traffic. This scheme allows subunits with lower priority a
guaranteed percentage of high priority and also prevents dead cycles of
arbitration associated with simple rotating high priority arbiters. The standard
arbiter 6 has a fixed priority in descending order and has been improved so that
devices with lower priority, with critical time dependencies, may have highest
priority a certain percentage of the time, when arbitration is possible. In this
example, there are eight subunits that would be requesting access to the bus.
Some of these subunits may need to have highest priority at least part of the
time. The new arbiter circuit achieves this rotating priority in the following
manner. The three-bit priority registers 1 are loaded with addresses
corresponding to the subunits requiring highest priority part of the time. The
percentage of top priority grants is established by the number of times an
address appears in the bank of priority registers 1. The granularity of the
percentage of highest priority is inversely proportional to the number of priority
registers used. For example, if there is a total of eight priority registers, two
which contain address "3", four which contain address "1", with the remaining two
containing address "7", then subunit "1" will have top priority 50% of the time,
while subunits "3" and "...