but when i run simulation the output result is not synced at all!
I know i am not considering something here, but what is that?
I need HELP ASAP, please :(
What is it that i am doing wrong!?
I have posted the *.vwf and the simulation result as attachments
Thanks in advace

Do you perform a timing simulation?
If yes: try it with a functional simulation.
It will be much, much faster...
> but when i run simulation the output result is not synced at all!
Why do you expect something to be sync'ed to something else?
In your design theres no clock, so all of it is completely asynchronous.
BTW: Your design is completely in VHDL. So, why don't you simply use a
VHDL testbench instead of that manual vector wave drawing?

thanks for ur answer.
First off i am totally newB in VHDL programming so my questions may seem
silly:)
> Do you perform a timing simulation?
I dont know if i am performing a timing simulation or not! how can i
know that?
> VHDL testbench instead of that manual vector wave drawing?
I have no idea how can i write a testbeanch for this and how i can run
that! :(
How can i do testbench and how i can get visual resualts?

Dariush H. wrote:> I have no idea how can i write a testbeanch for this and how i can run> that! :(> How can i do testbench and how i can get visual resualts?
A testbench is just a VHDL entity without ports. In this entity you
place your desgins top level entity as a component.
So it will look somehow like this: