My DSP application is implemented on a FPGA using VHDL. Basically there are four 16-Bit PCM audio signals with 48k sample rate. After processing each audio signal separately (one multiplication with a factor that depends on a sensor) i add those four audio signals to get a unified signal.So the question is now, when i add those four audio signals i get a 18 bit result, but i must reduce the bit depth back to 16 bit to hand it to the audio codec chip (DAC).Should i dither in this case? Or what is the typical approach when adding PCM audio signals and then want to go back to the original bit depth?All calculation is done in fixed point.

Thanks for the answers. So each time i drop bits e.g rounding after mult or add i have to dither because i will do a new quantization.If the difference is audible or not is not really important because its a university project