Paging modes for the x86 32-bits architectures

The paging-mode is used in most of the Operating Systems, with this feature you can customize the size of a virtual memory page, we'll discuss the different layouts usable in this short note.

All the pages that composed your virtual address space have the same size, and you can choose this size among those different modes: 4KB, 4MB and 2MB. Also in order to increase the size of the virtual address space x86 32-bits architecture has a feature called "Page Address Extension (PAE)" mode. When this mode is enabled, you can access more than four gigabytes of physical memory. With this feature the page size max is 2MB not 4MB. For more information about the Intel page size, see the following table.

On the following schema you can see the translation from a linear virtual address to a physical address without PAE paging, with 4KB pages. In this configuration the CR3 register holds the physical address of the page directory, then the virtual address is splitted in 3 parts:

The 10 most significant bits are an index in the page directory.

The next 10 bits are an index in the page table.

And the last 12 bits are an offset in the physical memory page.

In the next schema, you can find how to translate a linear virtual address into a physical address with PAE paging enabled (always with 4KB page size). This time the CR3 registers contains the physical address of the PDPT and the virtual address is splitted in 4 parts:

2 bits for an index in the PDPT.

9 bits for an index in the PD.

9 other bits who are an index in the PT for the base address in the physical memory.

And the last 12 bits are an offset in the physical memory page.

This is now how you translate a linear virtual address into a physical address with 4MB pages and PAE paging disabled. In this configuration the CR3 register holds the physical address of the page directory, and the virtual address is splitted in 2 parts:

10 bits who are an index in the PD for the base address in the physical memory.

The last 22 bits are an offset in the physical page.

In the last schema you can find how to translate a linear virtual address into a physical address with 2MB pages and PAE paging enabled. In this configuration the CR3 register holds the physical address of the page directory, and the virtual address is splitted in 3 parts:

2 bits for an index in the PDPT.

9 other bits who are an index in the PD for the base address in the physical memory.