Intel's Embedded DRAM: New Era of Cache Memory

With SRAM so costly to make, Intel's Embedded DRAM is an intriguing option. Techinsights examines eDRAM and its potential.

Two industry giants -- Intel and Samsung -- expressed their frustration with SRAM scaling at this year's International Solid-State Circuits Conference (ISSCC) in February.

In the paper Song et. al. from Samsung[1] argued that SRAM not only occupied too much real estate, but the operating voltage did not scale in the same proportion as the logic devices on the same die. Cache size in megabytes was also increasing on the die; so there were more devices on the die that required higher voltages than the main logic part. Hamzaoglu in a paper from Intel[2], revealed that SRAM scaling was not satisfying their requirements and that the majority of the die area was taken by SRAM cell area. The question arose; was it worth continuing to invest in SRAM, especially in 22nm nodes and below, where manufacturing costs were astronomical and could only continue to increase for future technology nodes?

Using fabrication cost and performance data, Intel concluded that an alternative configuration was needed, and therefore opted for an external high-density bandwidth cache memory in the same package. An external memory was easier to fabricate than an embedded SRAM, in an advanced technology process where real-estate was becoming scarce on the die. The DRAM cell was also much smaller than the six transistor SRAM cell layout made at the same lithography node. Moreover, having a separate DRAM die in the same package as the processor reduced chip interface delay, compared with external DRAM in a different package. The eDRAM also required 1/5 of the keep-alive power compared with an SRAM device. This analysis led Intel to release their Haswell processor with an external eDRAM.

The Intel Haswell GT3e G82494 processor came out in the market in October 2013 and was analyzed in our laboratories as part of our TechInsights Award program[3]. Our analysis of the GT3e revealed the general philosophy behind this innovative product -- to solve for frustrations experienced with SRAM scaling.

PackageFigure 1, is the package cross-section which shows the processor and the embedded DRAM side by side. The Intel CT3e graphics and GT3e graphics processing unit (GPU) were packaged in a multichip (MCP) process. There were two dice placed side by side and flip-chip bumped to a FR4 type package substrate. One was the eDRAM and the other was the Haswell processor. The eDRAM die area was one third the size of the processor die area. Both dice were flip chip bumped to the package substrate. The die and the package substrate were connected together by Cu-pillars. The same packaging process was used by Intel 32nm and 22nm logic processes.

[3] The Insight Awards, presented by TechInsights, showcase advancements in engineering innovations in the electronics and semiconductor technology. The 2014 winner for Logic is the Intel Haswell GT3e G82494

I myself have worked in DRAM foundry and I know that 1 transistor and 1 capacitor is always smaller than 6 Transistor SRAM for a given technology node.

So I am not making that mistake at all.

What I am saying is that this eDRAM cell size would correspond to 1x SRAM cell size and the point is that SRAM is taking lot of real estate and is not shrinking well and does not provide enough bandwidth.

So by switching to external DRAM from SRAM, INTEL is having lot of advantage.

Probably IBM came to the same conclusion as Intel and made eDRAM since many years.

@AD2010 by using my elite Googling skills, it appears that Power8 has been available since June 10 2014.

eDRAM cells are much smaller than SRAM cells in the same technology, regardless of Intel, IBM, NEC or whomever is making it. Hopefully you aren't under the misapprehension that Intel is the first IDM to make DRAM cells smaller than SRAM.

IBM latest eDRAM is 22 nm on SOI with trench technology (for instance on POWER 8). This doesn't mean that the half pitch on the eDRAM macro is 22 nm , but the logic besides the eDRAM macro on the same chip is a 22 nm technology.

Yes IBM was a pioneer in eDRAM and particularly TRENCH capacitor technology, which was later used by Infineon-Qimonda. I do not know who has older patents on eDRAM, is it IBM or INTEL? And MIM Capacitor can be formed regardless of capacitor frame structure (stack or trench).

Regarding this eDRAM device from Intel, the concept of using stacked capacitors is not new, also the idea of placing the stacked capacitor between the interconnects is not novel;

however, we are forgetting the most interesting point in this device and that is the eDRAM cell size is way smaller than the most advanced SRAM cell and there is plenty of room to extend the memory size without changing the technology node. Also Intel claims very good retention properties of this device, which they attribute to the trigate structure of the access transistors.

I am sure Power 8 processor of IBM with 22 nm node process would be a milestone in technology but I do not know if this product is already available in the market?