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AR# 52759

Description

I added an AXI BFM core to my project and synthesize. Vivado issues an error for synth_design similar to the following example log:

Starting synthesis...

Using part: xc7vx485tffg1157-1WARNING: [IP_Flow 19-1100] IP 'my_cdn_axi4_slave_bfm_wrap' does not match the current project part 'xc7vx485tffg1157-1'. You may continue to use existing outputs but part differences may result in undefined behavior. Please review your project settings if this is unexpected.INFO: [Common 17-78] Attempting to get a license: SynthesisINFO: [Common 17-290] Got license for SynthesisINFO: [Common 17-291] Device 'xc7vx485t' license available: SynthesisINFO: [Common 17-83] Releasing license: SynthesisERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified

Solution

The error message is correct; there are no RTL files (from the IP) for synthesis.

If you look at the supported targets for this IP via the GUI, right-click on IP -> Generate Output Products, or via TCL, list_targets [get_files my_cdn_axi4_slave_bfm_wrap.xci], you will notice no synthesis target. In addition, the IP Sources tab for the IP shows no synthesis files.

Although the message is correct when synthesizing an IP core with Synthesis sources, in the Vivado 2012.3 tools, the message has been changed to be more helpful as shown below:

WARNING: [#UNDEF] 'Synthesis' target generation is not supported for the IP ( my_cdn_axi4_slave_bfm_wrap.xci ). No files will be delivered for this target.