DesignCon 2013 keeps the focus on memory

Chipheads unite—DesignCon 2013 (January 28-31; Santa Clara, CA) kicks off in just two weeks. Created by engineers for engineers, the meeting features more than 100 technical presentations spread across 14 tracks covering all aspects of chip, board, and system design.

Technical tracks include:

Chip-Level Design for Signal/Power Integrity

Analog, Mixed-Signal, and RF Design and Verification

Designing with Programmable Architectures

System Co-Design: Chip/Package/Board

PCB Materials, Processing and Characterization

PCB Design Tools and Methodologies

Parallel and Memory Interface Design

High-Speed Serial Design

Jitter, Crosstalk, and Noise Analysis

High-Speed Signal Processing, Equalization and Coding

Power Integrity and Power Distribution Network Design

Electromagnetic Compatibility and Interference

Test and Measurement Methodology

Signal Propagation Analysis Techniques

The exposition showcases over 130 exhibitors displaying the latest tools and products, as well as the Chiphead Theater, where you can view present product teardowns, prize drawings, and more.

The meeting includes plenty of memory offerings. Making DDR4 Work For You (AEF-02), a special forum on the JEDEC standard, is aimed at designers who want to understand the challenges of DDR4 designs compared to DDR3. Agilent experts, including JEDEC board member Perry Keller, will review of the key provisions of DDR4, with a particular focus on modeling, timing specifications, separating reads and writes, accurately capturing a DDR4 signal, and the best probing techniques. Attend this forum and learn everything you needed to know for DDR4 design and test, but were afraid to ask.

No matter how much memory your system has, if you can’t get data on and off of your processor in a timely fashion, your application won’t succeed. That’s why DesignCon has an entire track on parallel-and-memory-interface-design. Key presentations include:

A 256-GB/s Memory Subsystem Built Using a Double-Sided IC Package with a Memory Controller and 3D-Stacked DRAM ( 7-WA3)As the memory wall looms ever closer, 3D processor/memory integration is the solution on everyone’s lips. In this presentation, Rambus engineers present a processor and DRAM memory subsystem built using a double-sided, flip-chip substrate with a processor die on one side of the package and a thermally isolated, disaggregated memory chip on the other side. The team used and organic substrate, redistribution layers, and chip metal layers to achieve 16 independent memory channels. Find out more about the full details of system, which is expected to operate at a per-pin data rate of 4 Gbps with a memory power consumption of 40 W or less. That leaves more than 60 W of power available for computation without exceeding the 85C temperature limit of the co-packaged DRAM.DDR Memory Channel Design from Passive Stub Equalizer Perspective ( 7-WA1)Intel staffers present a new design concept for the DDR memory channel from the passive stub equalizer perspective to help engineers optimize the high-speed multi-drop memory channel. They’ll illustrate the basics of the stub equalizer in the frequency and time domains through both simulation and measurement. More important, they’ll show how the technology can be used to optimize the multi-rank DDR memory channel to enhance signal integrity. The presentation will include design examples of two- and four-rank DDR3/4 DQ channels using on-die termination as well as a 2-rank LPDDR2/3 CA channel using on-board termination.Robust I/O Circuit Scheme for World's First over-1.6-Gbps LPDDR3 ( 7-WA2)In a pair of related papers, Samsung engineers discuss LPDDR3 designs. In the first, they discuss the design process leading to a WQXGA display mobile AP chip fabricated with a 28-nm low-power CMOS process. The device delivers a 30% reduction in power consumption versus their previous 45-nm AP chip. The team used chip-to-chip SI/PI analysis to investigate the speed limiters in a conventional DRAM interface system and identify the speed enablers in the areas of chip I/O, package, board, and LPDDR3 memory devices. This facilitated the development of robust I/O signaling solutions for a1.6-Gb LPDDR3 interface without pseudo-open-drain (POD) termination, which allowed them to develop their AP chip.World's First LPDDR3 for enabling mobile application processor systems ( 7-WP6)In the second Samsung paper, the author focuses on robust platform I/O signaling solutions, especially a point-of-view channel between the AP and the LPDDR3. When the first sample chip was powered on in the mobile AP platform, it initially operated LPDDR3 at 533 MHz in the single-chip package type and 66 7MHz in the package-on-package type. The presenter will discuss how the team analyzed the signaling phenomenon at the failure to identify the key speed limiters and enablers from the chip I/O, package, board, and DRAM design, respectively. Applying proven package/board reference design solutions improved SI and PI for LPDDR3 and ensured sufficient signaling margins.

Pushing Mobile Memories Beyond the Smartphone Envelope ( 7-WP5)Any time a new standard comes out, the first question people ask is, “What are the parameters?” The second question they ask is, “How can I exceed them?” Now that LPDDR3 has been released, the next step is LPDDR3E, targeted for operation at a data rate of 2133 Mbps with loading up to two ranks of devices. Ideally, this will be operated without any parallel termination at the far end of the net. Even in electrically short implementations, such as package-on-package, managing transmission-line effects will be critical to successful execution of these challenging interfaces. If you’re one of those who will be tempted to implement the SDRAM devices in interconnect environments that exceed the original intentions of the standard. In this paper, Synopsys engineers will describe the use of simulation results to explore the critical signal-integrity effects that impact performance, and outline the interconnect limitations for the target frequency. Understanding these constraints will increase the likelihood of first-pass success.

This is just a small sample of what you can find at the meeting. Interested? Be sure to register by January 18 to get the early-bird discount.

After attending several sessions and seeing the demonstrations in the show floor, I still stand firm with my belief system that:
(DDR4 + SoC) = RIP
There is no more room for DDR4 into SoC market, it will continue to be standard memory for Server and PCs in multi-drop buses for 2 or 3 chipsets. But the level of expertise require to design, bring up and validate DDR4 memory interface it far more complicated that any SoC interface out there (even harder than 10G-KR).
I said this back in 2009 and I continue to stay firm on this matter. There is really no life for DDR4 in SoC other than Hype!
This brings us to the key questions, what would all the Next Gen SoC use for external Memory interface?
(reply if you think u know the answer!!)