NVIDIA CUDA™

NVIDIA CUDA C Programming Guide

Version 3.1.1
7/21/2010

Changes from Version 3.1

Removed from Sections 3.1.6 and 5.2.3 the paragraph about loading 32-bit device code from 64-bit host code as this capability will no longer be supported in the next toolkit release.  In Section 3.2.6.3, removed the reference to the canMapHostMemory property and mentioned that all devices of compute capability greater than 1.0 now support mapped page-locked host memory.


Mentioned in Section 3.2.7.1 that host device memory copies of a memory block of 64 KB or less are asynchronous.  Fixed the maximum size of a 3D texture reference for devices of compute capability 2.0 (2048 instead of 4096) in Section G.1.  Updated the paragraph about __fdividef(x,y) in Section C.2.1 to clarify behavior depending on compute capability and compilation flag.


Because the same program is executed for each data element. the memory access latency can be hidden with calculations instead of big data caches. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. stereo vision. many algorithms outside the field of image rendering and processing are accelerated by data-parallel processing. there is a lower requirement for sophisticated flow control. NVIDIA introduced CUDA™. a general purpose parallel computing architecture – with a new parallel programming model and instruction set architecture – that leverages the parallel compute engine in NVIDIA GPUs to
CUDA C Programming Guide Version 3. video encoding and decoding. Similarly. highly parallel computation – exactly what graphics rendering is about – and therefore designed such that more transistors are devoted to data processing rather than data caching and flow control. The GPU Devotes More Transistors to Data Processing
More specifically. the GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. from general signal processing or physics simulation to computational finance or computational biology. image and media processing applications such as post-processing of rendered images. large sets of pixels and vertices are mapped to parallel threads. Data-parallel processing maps data elements to parallel processing threads.1. image scaling.
1.1
3
. Introduction
The reason behind the discrepancy in floating-point capability between the CPU and the GPU is that the GPU is specialized for compute-intensive. In 3D rendering. and pattern recognition can map image blocks and pixels to parallel processing threads.
Control
ALU ALU
ALU ALU
Cache
DRAM
DRAM
CPU
GPU
Figure 1-2. and because it is executed on many data elements and has high arithmetic intensity.Chapter 1. as schematically illustrated by Figure 1-2.2
CUDA™: a General-Purpose Parallel Computing Architecture
In November 2006. In fact.

other languages or application programming interfaces are supported. their parallelism continues to scale with Moore‟s law. The CUDA parallel programming model is designed to overcome this challenge while maintaining a low learning curve for programmers familiar with standard programming languages such as C. Furthermore.1. As illustrated by Figure 1-3. CUDA is Designed to Support Various Languages or Application Programming Interfaces
1. and barrier synchronization – that are simply exposed to the programmer as a minimal set of language extensions.Chapter 1.
Figure 1-3.1
. much as 3D graphics applications transparently scale their parallelism to manycore GPUs with widely varying numbers of cores. CUDA comes with a software environment that allows developers to use C as a high-level programming language. shared memories. and each sub-problem into finer pieces that can be solved cooperatively in parallel by all threads within the block. At its core are three key abstractions – a hierarchy of thread groups. and DirectCompute. They guide the programmer to partition the problem into coarse sub-problems that can be solved independently in parallel by blocks of threads. This decomposition preserves language expressivity by allowing threads to
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CUDA C Programming Guide Version 3. The challenge is to develop application software that transparently scales its parallelism to leverage the increasing number of processor cores. These abstractions provide fine-grained data parallelism and thread parallelism. such as CUDA FORTRAN. Introduction
solve many complex computational problems in a more efficient way than on a CPU. OpenCL.3
A Scalable Programming Model
The advent of multicore CPUs and manycore GPUs means that mainstream processor chips are now parallel systems. nested within coarse-grained data parallelism and task parallelism.

This scalable programming model allows the CUDA architecture to span a wide market range by simply scaling the number of processors and memory partitions: from the high-performance enthusiast GeForce GPUs and professional Quadro and Tesla computing products to a variety of inexpensive.
Figure 1-4. concurrently or sequentially. mainstream GeForce GPUs (see Appendix A for a list of all CUDA-enabled GPUs).Chapter 1. and only the runtime system needs to know the physical processor count. each block of threads can be scheduled on any of the available processor cores. in any order. and at the same time enables automatic scalability.
Multithreaded CUDA Program Block 0 Block 4 Block 1 Block 5 Block 5 Block 2 Block 6 Block 6 Block 3 Block 7
GPU with 2 Cores
Core 0 Core 1
GPU with 4 Cores
Core 0 Core 1 Core 2 Core 3
Block 0
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Block 0
Block 1
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Block 2
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A multithreaded program is partitioned into blocks of threads that execute independently from each other.1. so that a GPU with more cores will automatically execute the program in less time than a GPU with fewer cores. Automatic Scalability
CUDA C Programming Guide Version 3. Indeed. Introduction
cooperate when solving each sub-problem. so that a compiled CUDA program can execute on any number of processor cores as illustrated by Figure 1-4.1
5
.

This chapter introduces the main concepts behind the CUDA programming model by outlining how they are exposed in C. An extensive description of CUDA C is given in Section 3.2. Full code for the vector addition example used in this chapter and the next can be found in the vectorAdd SDK code sample.

2.1

Kernels
CUDA C extends C by allowing the programmer to define C functions, called kernels, that, when called, are executed N times in parallel by N different CUDA threads, as opposed to only once like regular C functions. A kernel is defined using the __global__ declaration specifier and the number of CUDA threads that execute that kernel for a given kernel call is specified using a new <<<…>>> execution configuration syntax (see Appendix B.15). Each thread that executes the kernel is given a unique thread ID that is accessible within the kernel through the built-in threadIdx variable. As an illustration, the following sample code adds two vectors A and B of size N and stores the result into vector C:
// Kernel definition __global__ void VecAdd(float* A, float* B, float* C) { int i = threadIdx.x; C[i] = A[i] + B[i]; } int main() { ... // Kernel invocation with N threads VecAdd<<<1, N>>>(A, B, C); }

Here, each of the N threads that execute VecAdd() performs one pair-wise addition.

CUDA C Programming Guide Version 3.1

7

Chapter 2. Programming Model

2.2

Thread Hierarchy
For convenience, threadIdx is a 3-component vector, so that threads can be identified using a one-dimensional, two-dimensional, or three-dimensional thread index, forming a one-dimensional, two-dimensional, or three-dimensional thread block. This provides a natural way to invoke computation across the elements in a domain such as a vector, matrix, or volume. The index of a thread and its thread ID relate to each other in a straightforward way: For a one-dimensional block, they are the same; for a two-dimensional block of size (Dx, Dy), the thread ID of a thread of index (x, y) is (x + y Dx); for a threedimensional block of size (Dx, Dy, Dz), the thread ID of a thread of index (x, y, z) is (x + y Dx + z Dx Dy). As an example, the following code adds two matrices A and B of size NxN and stores the result into matrix C:
// Kernel definition __global__ void MatAdd(float A[N][N], float B[N][N], float C[N][N]) { int i = threadIdx.x; int j = threadIdx.y; C[i][j] = A[i][j] + B[i][j]; } int main() { ... // Kernel invocation with one block of N * N * 1 threads int numBlocks = 1; dim3 threadsPerBlock(N, N); MatAdd<<<numBlocks, threadsPerBlock>>>(A, B, C); }

There is a limit to the number of threads per block, since all threads of a block are expected to reside on the same processor core and must share the limited memory resources of that core. On current GPUs, a thread block may contain up to 1024 threads. However, a kernel can be executed by multiple equally-shaped thread blocks, so that the total number of threads is equal to the number of threads per block times the number of blocks. Blocks are organized into a one-dimensional or two-dimensional grid of thread blocks as illustrated by Figure 2-1. The number of thread blocks in a grid is usually dictated by the size of the data being processed or the number of processors in the system, which it can greatly exceed.

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CUDA C Programming Guide Version 3.1.1

Chapter 2: Programming Model

Grid Block (0, 0) Block (1, 0) Block (2, 0)

Block (0, 1)

Block (1, 1)

Block (2, 1)

Block (1, 1) Thread (0, 0) Thread (1, 0) Thread (2, 0) Thread (3, 0)

Thread (0, 1) Thread (1, 1) Thread (2, 1) Thread (3, 1)

Thread (0, 2) Thread (1, 2) Thread (2, 2) Thread (3, 2)

Figure 2-1. Grid of Thread Blocks
The number of threads per block and the number of blocks per grid specified in the <<<…>>> syntax can be of type int or dim3. Two-dimensional blocks or grids can be specified as in the example above. Each block within the grid can be identified by a one-dimensional or twodimensional index accessible within the kernel through the built-in blockIdx variable. The dimension of the thread block is accessible within the kernel through the built-in blockDim variable. Extending the previous MatAdd() example to handle multiple blocks, the code becomes as follows.
// Kernel definition __global__ void MatAdd(float A[N][N], float B[N][N], float C[N][N]) { int i = blockIdx.x * blockDim.x + threadIdx.x; int j = blockIdx.y * blockDim.y + threadIdx.y; if (i < N && j < N) C[i][j] = A[i][j] + B[i][j];

CUDA C Programming Guide Version 3.1.1

9

The grid is created with enough blocks to have one thread per matrix element as before. Each thread has private local memory.2 gives an example of using shared memory.2. For simplicity. MatAdd<<<numBlocks.4. is a common choice.y).3. __syncthreads() acts as a barrier at which all threads in the block must wait before any is allowed to proceed. B. }
A thread block size of 16x16 (256 threads).3.2. constant.1.Chapter 2.1. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. For efficient cooperation. Each thread block has shared memory visible to all threads of the block and with the same lifetime as the block.2. The global. C). // Kernel invocation dim3 threadsPerBlock(16. the shared memory is expected to be a low-latency memory near each processor core (much like an L1 cache) and __syncthreads() is expected to be lightweight. in parallel or in series. constant.2.. 5. Thread blocks are required to execute independently: It must be possible to execute them in any order. although that need not be the case. The global. N / threadsPerBlock. Threads within a block can cooperate by sharing data through some shared memory and by synchronizing their execution to coordinate memory accesses.
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CUDA C Programming Guide Version 3. dim3 numBlocks(N / threadsPerBlock.2.
2.3. All threads have access to the same global memory.. threadsPerBlock>>>(A. Section 3. This independence requirement allows thread blocks to be scheduled in any order across any number of cores as illustrated by Figure 1-4. and texture memory spaces are optimized for different memory usages (see Sections 5. 16). More precisely. Programming Model
} int main() { . for some specific data formats (see Section 3.5). although arbitrary in this case.x. Texture memory also offers different addressing modes. and 5.4).3
Memory Hierarchy
CUDA threads may access data from multiple memory spaces during their execution as illustrated by Figure 2-2. enabling programmers to write code that scales with the number of cores. one can specify synchronization points in the kernel by calling the __syncthreads() intrinsic function. and texture memory spaces are persistent across kernel launches by the same application. as well as data filtering. this example assumes that the number of threads per grid in each dimension is evenly divisible by the number of threads per block in that dimension.1
.

1. respectively.Chapter 2. This includes device memory allocation and deallocation as well as data transfer between host and device memory. Programming Model
The CUDA programming model also assumes that both the host and the device maintain their own separate memory spaces in DRAM. and texture memory spaces visible to kernels through calls to the CUDA runtime (described in Chapter 3).1
. referred to as host memory and device memory. a program manages the global. constant. Therefore.
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CUDA C Programming Guide Version 3.

possibly including new features.x (Their major revision number is 1). The major revision number of devices based on the Fermi architecture is 2. Programming Model
2.5
Compute Capability
The compute capability of a device is defined by a major revision number and a minor revision number. Appendix G gives the technical specifications of each compute capability. Appendix A lists of all CUDA-enabled devices along with their compute capability. The minor revision number corresponds to an incremental improvement to the core architecture.1.1
.Chapter 2. Prior devices are all of compute capability 1.
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CUDA C Programming Guide Version 3. Devices with the same major revision number are of the same core architecture.

but it can use both as described in Section 3. Section 3. Initialization. In contrast. but offers a better level of control and is language-independent since it handles binary or assembly code.1. The CUDA driver API is a lower-level C API that provides functions to load kernels as modules of CUDA binary or assembly code.1
Compilation with NVCC
Kernels can be written using the CUDA instruction set architecture.2 continues the description of CUDA C started in Chapter 2. and module management are all implicit and resulting code is more concise. It is however usually more
CUDA C Programming Guide Version 3.1
15
. Binary and assembly codes are usually obtained by compiling kernels written in C. is harder to program and debug. device enumeration. Section 3. etc. context. It also introduces concepts that are common to both CUDA C and the driver API: linear memory. These extensions allow programmers to define a kernel as a C function and use some new syntax to specify the grid and block dimension each time the function is called. and to launch them. which is described in the PTX reference manual. An application typically uses either one or the other. texture memory.
3. Programming Interface
Two interfaces are currently supported to write CUDA programs: CUDA C and the CUDA driver API. shared memory. to inspect their parameters. called PTX. Any source file that contains some of these extensions must be compiled with nvcc as outlined in Section 3. manage systems with multiple devices. CUDA arrays.Chapter 3. page-locked host memory. asynchronous execution. The runtime API is built on top of the CUDA driver API. CUDA C comes with a runtime API and both the runtime API and the driver API provide functions to allocate and deallocate device memory.4. CUDA C exposes the CUDA programming model as a minimal set of extensions to the C language.3 assumes knowledge of these concepts and describes how they are exposed by the driver API. interoperability with graphics APIs. transfer data between host memory and device memory. the CUDA driver API requires more code.

3. compiling with –code=sm_13 produces binary code for devices of compute capability 1.  Or link to the generated host code. Binary compatibility is guaranteed from one minor revision to the next one. For example.z where z≥y. In both cases. but allow applications to benefit from latest compiler improvements. but not from one minor revision to the previous one or across major revisions. This is called just-in-time compilation.

3.1
. The generated host code is output either as C code that is left to be compiled using another tool or as object code directly by letting nvcc invoke the host compiler during the last compilation stage. nvcc‟s basic workflow consists in separating device code from host code and compiling the device code into an assembly form (PTX code) and/or binary form (cubin object).
nvcc is a compiler driver that simplifies the process of compiling C or PTX code: It
provides simple and familiar command line options and executes them by invoking the collection of tools that implement the different compilation stages. Programming Interface
effective to use a high-level programming language such as C.e. Applications can then: Either load and execute the PTX code or cubin object on the device using the CUDA driver API (see Section 3.1.1. atomic instructions on global memory are only supported
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CUDA C Programming Guide Version 3. A complete description can be found in the nvcc user manual.1. A cubin object is generated using the compiler option –code that specifies the targeted architecture: For example. In other words.15) into the necessary CUDA C runtime function calls to load and launch each compiled kernel.1.3.3
PTX Compatibility
Some PTX instructions are only supported on devices of higher compute capabilities. code that executes on the host) and device code (i. code that executes on the device). the generated host code includes the PTX code and/or cubin object as a global initialized data array and a translation of the <<<…>>> syntax introduced in Section 2.2
Binary Compatibility
Binary code is architecture-specific.1.1 (and described in more details in Section B. a cubin object generated for compute capability X.4.Chapter 3.1
Compilation Workflow
Source files compiled with nvcc can include a mix of host code (i. Just-in-time compilation increases application load time. as detailed in Section 3.3) and ignore the generated host code (if any). Any PTX code loaded by an application at runtime is compiled further to binary code by the device driver.e. It is also the only way for applications to run on devices that did not exist at the time the application was compiled. This section gives an overview of nvcc workflow and command options.
3. kernels must be compiled into binary code by nvcc to execute on the device.y is only guaranteed to execute on devices of compute capability X.

For example.4
Application Compatibility
To execute code on devices of specific compute capability.1.1. double-precision instructions are only supported on devices of compute capability 1. Which PTX and binary code gets embedded in a CUDA C application is controlled by the –arch and –code compiler options or the –gencode compiler option as detailed in the nvcc user manual. The –arch compiler option specifies the compute capability that is assumed when compiling C to PTX code.sm_13” (which is the same as “ gencode arch=compute_13.
CUDA C Programming Guide Version 3. Programming Interface
on devices of compute capability 1.1 PTX code for devices with compute capabilities 2.3. for example.0 binary code for devices with compute capability 1. PTX code produced for some specific compute capability can always be compiled to binary code of greater or equal compute capability.0.1 and above.code=\’compute_13. code that contains double-precision arithmetic. otherwise double-precision arithmetic will get demoted to single-precision arithmetic.
3.code=\’compute_11. and gencode compiler options. The nvcc user manual lists various shorthands for the –arch. __CUDA_ARCH__ is equal to 110. in the above example.3. In particular. must be compiled with “-arch=sm_13” (or higher compute capability). an application must load PTX code that will be compiled just-intime for these devices.1. which.cu can have an optimized code path that uses atomic operations. When compiling with “arch=compute_11” for example. 1. will be: 1.Chapter 3. to be able to execute code on future architectures with higher compute capability – for which no binary code can be generated yet –.1 (second -gencode option).3 and above.  binary code obtained by compiling 1. It is only defined for device code.2. For example.2 and 3. which are only supported in devices of compute capability 1. So.0 or higher.sm_13\’”). “ arch=sm_13” is a shorthand for “ arch=compute_13 code=compute_13. The __CUDA_ARCH__ macro can be used to differentiate various code paths based on compute capability.1. for example.1 binary code for devices with compute capability 1.1
17
. 1.sm_11\’
embeds binary code compatible with compute capability 1.
nvcc x.0 (first –gencode option) and PTX and binary code compatible with compute capability 1.

Applications using the driver API must compile code to separate files and explicitly load and execute the most appropriate file at runtime.code=sm_10 –gencode arch=compute_11. Host code is generated to automatically select at runtime the most appropriate code to load and execute. x.cu –gencode arch=compute_10.1 and higher. an application must load binary or PTX code that is compatible with this compute capability as described in Sections 3.  1.1. –code.

There is no explicit initialization function for the runtime. However. The core language extensions have been introduced in Chapter 2.6
64-Bit Compatibility
The 64-bit version of nvcc compiles device code in 64-bit mode (i. stream..1) is created under
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CUDA C Programming Guide Version 3.e. kernel launches.1. it initializes the first time a runtime function is called (more specifically any function other than functions from the device and version management sections of the reference manual). This section continues with an introduction to the runtime.Chapter 3.1
. This is because a CUDA context (see Section 3. the 32-bit version of nvcc compiles device code in 32-bit mode and device code compiled in 32-bit mode is only supported with host code compiled in 32-bit mode. event. only a subset of C++ is fully supported for the device code as described in detail in Appendix D. pointers are 64-bit). Full C++ is supported for the host code.1.2
CUDA C
CUDA C provides a simple path for users familiar with the C programming language to easily write programs for execution by the device.1. Programming Interface
3.
3. Similarly. The 32-bit version of nvcc can compile device code in 64-bit mode also using the m64 compiler option. A complete description of all extensions can be found in Appendix B and a complete description of the runtime in the CUDA reference manual. As a consequence of the use of C++ syntax rules. etc.
3. any resource (memory. void pointers (e. Device code compiled in 64-bit mode is only supported with host code compiled in 64-bit mode. Once the runtime has been initialized in a host thread. It consists of a minimal set of extensions to the C language and a runtime library. Therefore only runtime functions calls made by the host thread (memory copies. …) can operate on these resources. returned by malloc()) cannot be assigned to non-void pointers without a typecast.
nvcc also support specific keywords and directives detailed in Appendix E.g. One needs to keep this in mind when timing runtime function calls and when interpreting the error code from the first call into the runtime. The 64-bit version of nvcc can compile device code in 32-bit mode also using the m32 compiler option.5
C/C++ Compatibility
The front end of the compiler processes CUDA source files according to C++ syntax rules. The runtime is implemented in the cudart dynamic library and all its entry points are prefixed with cuda.3.) allocated via some runtime function call in the host thread is only valid within the context of the host thread.

size). float* d_C. and copy device memory. float* B. deallocate.x and 40-bit address space of devices of compute capability 2. so the runtime provides functions to allocate. Linear memory exists on the device in a 32-bit address space for devices of compute capability 1. so separately allocated entities can reference one another via pointers.0. In the vector addition code sample of Section 2. size). They are described in Section 3.2.. each with their own separate memory. Linear memory is typically allocated using cudaMalloc() and freed using cudaFree() and data transfer between host memory and device memory are typically done using cudaMemcpy(). in a binary tree. if (i < N) C[i] = A[i] + B[i].3. kernels are executed on device 0 by default as detailed in Section 3. } // Host code int main() { int N = .1. int N) { int i = blockDim.x. // Allocate input vectors h_A and h_B in host memory float* h_A = (float*)malloc(size).4.1.2. Kernels can only operate out of device memory.2. float* h_B = (float*)malloc(size).. // Initialize input vectors .
3. size_t size = N * sizeof(float). Programming Interface
the hood as part of initialization and made current to the host thread.. as well as transfer data between host memory and device memory. the CUDA programming model assumes a system composed of a host and a device. the vectors need to be copied from host memory to device memory:
// Device code __global__ void VecAdd(float* A.1
19
.x * blockIdx. float* C.Chapter 3. // Allocate vectors in device memory float* d_A. and it cannot be made current to any other host thread. cudaMalloc(&d_A.x + threadIdx.1
Device Memory
As mentioned in Section 2. cudaMalloc(&d_B. CUDA arrays are opaque memory layouts optimized for texture fetching. float* d_B.
CUDA C Programming Guide Version 3. for example..4. On system with multiple devices. Device memory can be allocated either as linear memory or as CUDA arrays..

Figure 3-1. Matrix Multiplication without Shared Memory
The following code sample is an implementation of matrix multiplication that does take advantage of shared memory. In this implementation, each thread block is responsible for computing one square sub-matrix Csub of C and each thread within the block is responsible for computing one element of Csub. As illustrated in Figure 3-2, Csub is equal to the product of two rectangular matrices: the sub-matrix of A of dimension (A.width, block_size) that has the same line indices as Csub, and the submatrix of B of dimension (block_size, A.width) that has the same column indices as Csub. In order to fit into the device‟s resources, these two rectangular matrices are divided into as many square matrices of dimension block_size as necessary and Csub is computed as the sum of the products of these square matrices. Each of these products is performed by first loading the two corresponding square matrices from global memory to shared memory with one thread loading one element of each matrix, and then by having each thread compute one element of the product. Each thread accumulates the result of each of these products into a register and once done writes the result to global memory.

Also. device < deviceCount. Matrix Multiplication with Shared Memory
3. multiple host threads are required to execute device code on multiple devices. The following code sample enumerates all devices in the system and retrieves their properties.height
B. cudaGetDeviceProperties(&deviceProp.
int deviceCount.1. but by design. for (device = 0. These devices can be enumerated. ++device) { cudaDeviceProp deviceProp. As a consequence. Several host threads can execute device code on the same device.1
A.width
A. any CUDA resources created through the runtime in one host thread cannot be used by the runtime from another host thread.3
Multiple Devices
A host system can have multiple devices. their properties can be queried. and one of them can be selected for kernel executions. device).width
Figure 3-2. cudaGetDeviceCount(&deviceCount).height
.2.Chapter 3. a host thread can execute device code on only one device at any given time. if (dev == 0) {
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CUDA C Programming Guide Version 3. It also determines the number of CUDA-enabled devices. Programming Interface
blockCol B
BLOCK_SIZE 0 0
A
C
col Csub
BLOCK_SIZE-1
BLOCK_SIZE
blockRow
BLOCK_SIZE
row
BLOCK_SIZE-1
BLOCK_SIZE
BLOCK_SIZE
BLOCK_SIZE B. int device.

4
Texture Memory
CUDA supports a subset of the texturing hardware that the GPU uses for graphics to access texture memory. else if (deviceCount == 1) printf("There is 1 device supporting CUDA\n").4.6 for exceptions). They are one-dimensional.
3. two-dimensional. each of which has 1.8. before it can be used by a kernel.2. After a device has been selected. or three-dimensional and composed of elements.2.minor == 9999) printf("There is no device supporting CUDA. A texture can be any region of linear memory or a CUDA array. any subsequent explicit call to cudaSetDevice() will fail up until cudaThreadExit() is called. The first parameter of a texture fetch specifies an object called a texture reference. CUDA arrays are only readable by kernels through texture fetching and may only be bound to texture references with the same number of packed components. deviceCount).1.3. as well as how the input coordinates are interpreted and what processing should be done. } }
By default. Several distinct texture references might be bound to the same texture or to textures that overlap in memory. As detailed in Section 3. described in Section B.
CUDA C Programming Guide Version 3. the device associated to the host thread is implicitly selected as device 0 as soon as a non-device management runtime function is called (see Section 3. else printf("There are %d devices supporting CUDA\n". One of them is its dimensionality that specifies whether the texture is addressed as a one-dimensional array using one texture coordinate. either implicitly or explicitly. a two-dimensional array using two texture coordinates. A texture reference defines which part of texture memory is fetched. or a threedimensional array using three texture coordinates. Programming Interface
if (deviceProp.3.Chapter 3. A texture reference has several attributes.1
29
. Any subsequent API call reinitializes the runtime. Reading data from texture memory instead of global memory can have several performance benefits as described in Section 5. it must be bound through runtime functions to some region of memory.\n").or 32-bit integers. Elements of the array are called texels. called a texture. Texture memory is read from kernels using device functions called texture fetches. 16.” Other attributes define the input and output data types of the texture fetch.5. or 32-bit floats. CUDA arrays are opaque memory layouts optimized for texture fetching. cudaThreadExit() cleans up all runtime-related resources associated with the calling host thread. 2 or 4 components that may be signed or unsigned 8-. short for “texture elements. 16-bit floats.major == 9999 && deviceProp. Any other device can be selected by calling cudaSetDevice() first.2.

They specify whether texture coordinates are normalized or not. Linear texture filtering may be done only for textures that are configured to return floating-point data. the value is actually returned as floating-point type and the full range of the integer type is mapped to [0. Programming Interface
3. 2. Normalized texture coordinates are a natural fit to some applications‟ requirements. for example.25 and -1. When using unnormalized texture coordinates. as detailed below. the addressing mode.0). Wrap addressing is usually used when the texture contains a periodic signal.0.75.  ReadMode is equal to cudaReadModeNormalizedFloat or cudaReadModeElementType. N) are clamped: Values below 0 are set to 0 and values greater or equal to N are set to N-1. for example. 31] for the x and y dimensions. 63] and [0. It performs low-precision interpolation between neighboring texels. Normalized texture coordinates cause the coordinates to be specified in the range [0.0] for unsigned integer type and [-1. 2-. For example.4.1. ReadMode> texRef. the texels surrounding a texture fetch location are read and
CUDA C Programming Guide Version 3.3.0) instead of [0.4. N) where N is the size of the texture in the dimension corresponding to the coordinate. 1.1
30
. if it is preferable for the texture coordinates to be independent of the texture size. textures are referenced using floating-point coordinates in the range [0.2.  Dim specifies the dimensionality of the texture reference and is equal to 1.0] for signed integer type. A texture reference can only be declared as a static global variable and cannot be passed as an argument to a function.0. 1. The addressing mode defines what happens when texture coordinates are out of range.Chapter 3. they are specified when declaring the texture reference.0. When enabled.0 are clamped to the range [0. It uses only the fractional part of the texture coordinate. or 3.25 is treated the same as 0. no conversion is performed. Dim is an optional argument which defaults to 1. By default. Type
is restricted to the basic integer and single-precision floating-point types and any of the 1-.
where:

Type specifies the type of data that is returned when fetching the texture. a texture that is 64 32 in size will be referenced with coordinates in the range [0. and texture filtering.1
Texture Reference Declaration
Some of the attributes of a texture reference are immutable and must be known at compile time.2.0. N). For normalized coordinates. an unsigned 8-bit texture element with the value 0xff reads as 1. and 4-component vector types defined in Section B. Dim. 1) in both the x and y dimensions.
3. ReadMode is an optional argument which defaults to cudaReadModeElementType. 1. texture coordinates outside the range [0.2
Runtime Texture Reference Attributes
The other attributes of a texture reference are mutable and can be changed at runtime through the host runtime. A texture reference is declared at file scope as a variable of type texture:
texture<Type.1. 1. Clamping is also the default addressing mode when using normalized texture coordinates: Values below 0. if it is cudaReadModeElementType. if it is cudaReadModeNormalizedFloat and Type is a 16-bit or 8-bit integer type. so the same 64 32 texture would be addressed by normalized coordinates in the range [0.0 or above 1. 1. the “wrap” addressing mode also may be specified. respectively.25 is treated the same as 0.

height. filterMode.1. second. Appendix F gives more details on texture fetching.height-1]. enum cudaChannelFormatKind f. cudaFilterModeLinear is only valid for returned values of floating-point type. y.depth-1] where width.
normalized specifies whether texture coordinates are normalized or not. and depth are the texture sizes. second. channelDesc.4. and third elements specify the addressing mode for the first. y. if it is cudaFilterModeLinear. filterMode is equal to cudaFilterModePoint or cudaFilterModeLinear.1] rather than in the range [0. in which case out-of-range texture coordinates are clamped to the valid range. the addressing mode is equal to either cudaAddressModeClamp. all elements in the texture are addressed with texture coordinates in the range [0. and third texture coordinates. z. Programming Interface
the return value of the texture fetch is interpolated based on where the texture coordinates fell between the texels.3
Texture Binding
As explained in the reference manual. }.1
31
.width-1]. w.  channelDesc describes the format of the value that is returned when fetching the texture. z. four (for a two-dimensional texture). the runtime API has a low-level C-style interface and a high-level C++-style interface. channelDesc is of the following type:
struct cudaChannelFormatDesc { int x. [0. Simple linear interpolation is performed for onedimensional textures and bilinear interpolation is performed for two-dimensional textures. addressMode is an array of size three whose first. respectively. or eight (for a three-dimensional texture) texels whose texture coordinates are the closest to the input texture coordinates. The texture type is defined in the high-level API as a structure publicly derived from the textureReference type defined in the low-level API as such:
struct textureReference { int enum cudaTextureFilterMode enum cudaTextureAddressMode struct cudaChannelFormatDesc }  normalized. addressMode[3]. that is how out-of-range texture coordinates are handled. if it
is non-zero. in which case out-of-range texture coordinates are wrapped to the valid range.
where x.2. that is how the value returned when fetching the texture is computed based on the input texture coordinates.
3.Chapter 3. the returned value is the texel whose texture coordinates are the closest to the input texture coordinates. and w are equal to the number of bits of each component of the returned value and f is:
CUDA C Programming Guide Version 3. or cudaAddressModeWrap. if it is cudaFilterModePoint. or [0. the returned value is the linear interpolation of the two (for a one-dimensional texture).  addressMode specifies the addressing mode. cudaAddressModeWrap is only supported for normalized texture coordinates.  filterMode specifies the filtering mode.

write-after-read. Reading from write-combining memory from the host is prohibitively slow.2
Write-Combining Memory
By default page-locked host memory is allocated as cacheable. Such a block has therefore two addresses: one in host memory and one in device memory.7) to avoid any potential read-after-write.1
.2.4) to overlap data transfers with kernel execution. or write-afterwrite hazards. the kernel-originated data transfers automatically overlap with kernel execution.0.6.2.Chapter 3. but by default. the benefits of using page-locked memory described above are only available for the thread that allocates it. data transfers are implicitly performed as needed by the kernel.
3.2.6.  There is no need to use streams (see Section 3. The simple zero-copy SDK sample comes with a detailed document on the pagelocked memory APIs.1). It can optionally be allocated as write-combining instead by passing flag cudaHostAllocWriteCombined to cudaHostAlloc(). In addition. making more cache available to the rest of the application.2.
3.6.2. write-combining memory is not snooped during transfers across the PCI Express bus.7.3
Mapped Memory
On devices of compute capability greater than 1. so write-combining memory should in general be used for memory that the host only writes to.2.

A block of page-locked host memory can be allocated as both mapped and portable (see Section 3. as device pointers will generally differ from one host thread to the other. Accessing host memory directly from within a kernel has several advantages: There is no need to allocate a block in device memory and copy data between this block and the block in host memory. Programming Interface
system for paging. a block of page-locked host memory can also be mapped into the address space of the device by passing flag cudaHostAllocMapped to cudaHostAlloc(). which can improve transfer performance by up to 40%. Write-combining memory frees up L1 and L2 cache resources. it needs to be allocated by passing flag cudaHostAllocPortable to cudaHostAlloc().1
Portable Memory
A block of page-locked memory can be used by any host threads.1.6.
3. the application must synchronize memory accesses using streams or events (see Section 3. in which case each host thread that needs to map the block to its device address space must call cudaHostGetDevicePointer() to retrieve a device pointer. The host memory pointer is returned by cudaHostAlloc() and the device memory pointer can be retrieved using cudaHostGetDevicePointer()and then used to access the block from within a kernel. allocating too much page-locked memory reduces overall system performance. Since mapped page-locked memory is shared between host and device however. To make these advantages available to all threads.
36
CUDA C Programming Guide Version 3.

cudaHostGetDevicePointer() will return an error.2.
3.  Memory set function calls.7. This feature is provided for debugging purposes only and should never be used as a way to make production software run reliably.
3. Device device memory copies.1
37
. Note that atomic functions (Section B.7.1. The maximum number of kernel launches that a device can execute concurrently is sixteen.Chapter 3. Applications may query whether a device supports mapped page-locked host memory or not by calling cudaGetDeviceProperties() and checking the canMapHostMemory property.11) operating on mapped page-locked memory are not atomic from the point of view of the host or other devices. page-locked memory mapping must be enabled by calling cudaSetDeviceFlags() with the cudaDeviceMapHost flag before any other CUDA calls is performed by the thread.3
Concurrent Kernel Execution
Some devices of compute capability 2. These are:
  
Kernel launches.2.7.  Memory copies performed by functions that are suffixed with Async.
cudaHostGetDevicePointer() also returns an error if the device does not
support mapped page-locked host memory. Applications may query this capability by calling cudaGetDeviceProperties() and checking the deviceOverlap property.
Host device memory copies of a memory block of 64 KB or less.2
Overlap of Data Transfer and Kernel Execution
Some devices of compute capability 1. some function calls are asynchronous: Control is returned to the host thread before the device has completed the requested task.2. Otherwise.2.0 can execute multiple kernels concurrently.
3.
CUDA C Programming Guide Version 3.1
Asynchronous Concurrent Execution
Concurrent Execution between Host and Device
In order to facilitate concurrent execution between host and device.1).7
3. Programming Interface
To be able to retrieve the device pointer to any mapped page-locked memory within a given host thread. When an application is run via the CUDA debugger or the CUDA profiler.1 and higher can perform copies between page-locked host memory and device memory concurrently with kernel execution. Applications may query this capability by calling cudaGetDeviceProperties() and checking the concurrentKernels property. all launches are synchronous.2. This capability is currently supported only for memory copies that do not involve CUDA arrays or 2D arrays allocated through cudaMallocPitch() (see Section 3. Programmers can globally disable asynchronous kernel launches for all CUDA applications running on a system by setting the CUDA_LAUNCH_BLOCKING environment variable to 1.

size. hostPtr must point to page-locked host memory for any overlap to occur. Processing hostPtr using two streams allows for the memory copies of one stream to overlap with the kernel execution of the other stream. inputDevPtr + i * size. size. Programming Interface
A kernel from one CUDA context cannot execute concurrently with a kernel from another CUDA context. ++i) cudaMemcpyAsync(inputDevPtr + i * size.2. cudaMemcpyHostToDevice. 2 * size). It forces the runtime to wait until all preceding device tasks in all streams have completed. inter-kernel communication is undefined).1. one kernel launch. cudaThreadSynchronize(). stream[i]). processes inputDevPtr on the device by calling MyKernel(). may execute their commands out of order with respect to one another or concurrently.7.
cudaStream_t stream[2]. and one memory copy from device to host:
for (int i = 0.2.
Each stream copies its portion of input array hostPtr to array inputDevPtr in device memory. allowing other streams to continue executing on the device. stream[i]). ++i) MyKernel<<<100. It can be used to synchronize the host with a specific stream. outputDevPtr + i * size.5
Stream
Applications manage concurrency through streams. A stream is a sequence of commands that execute in order. for (int i = 0. cudaStreamQuery() provides applications
cudaThreadSynchronize()
38
CUDA C Programming Guide Version 3. hostPtr + i * size. The following code sample creates two streams and allocates an array hostPtr of float in page-locked memory. for (int i = 0. cudaStreamSynchronize() forces the runtime to wait until all preceding commands in a stream have completed. cudaMallocHost(&hostPtr. i < 2. ++i) cudaStreamCreate(&stream[i]).
3. ++i) cudaMemcpyAsync(hostPtr + i * size. is called in the end to make sure all streams are finished before proceeding further. float* hostPtr. A stream is defined by creating a stream object and specifying it as the stream parameter to a sequence of kernel launches and host device memory copies.1
.
3. i < 2.0 can perform a copy from page-locked host memory to device memory concurrently with a copy from device memory to pagelocked host memory. and copies the result outputDevPtr back to the same portion of hostPtr.
Each of these streams is defined by the following code sample as a sequence of one memory copy from host to device.4
Concurrent Data Transfers
Devices of compute capability 2. Different streams.Chapter 3.7. 512. Kernels that use many textures or a large amount of local memory are less likely to execute concurrently with other kernels. stream[i]>>> (outputDevPtr + i * size. size). 0. i < 2.g. this behavior is not guaranteed and should therefore not be relied upon for correctness (e. i < 2. for (int i = 0. cudaMemcpyDeviceToHost. on the other hand.

 Synchronization of any kind should be delayed as long as possible.
cudaStreamDestroy() waits for all preceding tasks in the given stream to
complete before destroying the stream and returning control to the host thread.7.

3. inputHost + i * size. Streams are released by calling cudaStreamDestroy(). 0). by letting the application asynchronously record events at any point in the program and query when these events are actually recorded. cudaMemcpyHostToDevice.6
Event
The runtime also provides a way to closely monitor the device‟s progress. stream[i]>>> (outputDev + i * size. a device memory set.2. The following code sample creates two events:
cudaEvent_t start.
for (int i = 0. ++i) cudaMemcpyAsync(inputDev + i * size.
CUDA C Programming Guide Version 3. 0. size. for (int i = 0. Any operation that requires a dependency check to see if a streamed kernel launch is complete blocks all later kernel launches from any stream in the CUDA context until the launch being checked is complete.Chapter 3. An event is recorded when all tasks – or optionally. Two commands from different streams cannot run concurrently if either a pagelocked host memory allocation. for (int i = 0.
These events can be used to time the code sample of the previous section the following way:
cudaEventRecord(start. size). Programming Interface
with a way to know if all preceding commands in a stream have completed. 512. or any CUDA command to stream 0 (including kernel launches and host device memory copies that do not specify any stream parameter) is called in-between them by the host thread. Switching between the L1/shared memory configurations described in Section G. stream[i]).1 inserts a device-side synchronization barrier for all outstanding kernel launches. ++i) MyKernel<<<100. a device device memory copy. i < 2. Events in stream zero are recorded after all preceding tasks/commands from all streams are completed by the device. i < 2. To avoid unnecessary slowdowns. outputDev + i * size. cudaEventCreate(&stop). i < 2. Operations that require a dependency check include any other commands within the same stream as the launch being checked and any call to cudaStreamQuery() on that stream.4. these functions are best used for timing purposes or to isolate a launch or memory copy that is failing.1. all commands in a given stream – preceding the event have completed. as well as perform accurate timing. stop. ++i) cudaMemcpyAsync(outputHost + i * size. for (int i = 0. ++i) cudaStreamDestroy(stream[i]). i < 2. cudaEventCreate(&start). a device memory allocation.1
39
. applications should follow these guidelines to improve their potential for concurrent kernel execution: All independent operations should be issued before dependent operations. inputDev + i * size. Therefore.

Whether the host thread will then yield. Sections 3.2. it can be mapped and unmapped as many times as necessary using cudaGraphicsMapResources() and cudaGraphicsUnmapResources(). either to enable CUDA to read data written by OpenGL or Direct3D. cudaMemcpyDeviceToHost. Note that cudaSetDevice()and cudaGLSetGLDevice() are mutually exclusive.1.2. cudaEventElapsedTime(&elapsedTime.8
Graphics Interoperability
Some resources from OpenGL and Direct3D may be mapped into the address space of CUDA.
40
CUDA C Programming Guide Version 3. read-only) that the CUDA driver can use to optimize resource management. Once a resource is registered to CUDA. stream[i]).8. cudaEventDestroy(stop).2.1 and 3.
3.2. stop).8.Chapter 3. A CUDA graphics resource is unregistered using cudaGraphicsUnregisterResource().8.
3.1
.2.8.7.2. block. control is not returned to the host thread before the device has completed the requested task. 0).
They are destroyed this way:
cudaEventDestroy(start). cudaEventSynchronize(stop).2.2 give specifics for each graphics API and some code samples. float elapsedTime. Accessing a resource through OpenGL or Direct3D while it is mapped to CUDA produces undefined results.1 and 3.
3. or to enable CUDA to write data for consumption by OpenGL or Direct3D.7
Synchronous Calls
When a synchronous function is called. A resource must be registered to CUDA before it can be mapped using the functions mentioned in Sections 3. A mapped resource can be read from or written to by kernels using the device memory address returned by cudaGraphicsResourceGetMappedPointer() for buffers and cudaGraphicsSubResourceGetMappedArray() for CUDA arrays.8. cudaEventRecord(stop.2.1
OpenGL Interoperability
Interoperability with OpenGL requires that the CUDA device be specified by cudaGLSetGLDevice() before any other runtime calls. Registering a resource is potentially high-overhead and therefore typically called only once per resource. start. Programming Interface
size. or spin can be specified by calling cudaSetDeviceFlags()with some specific flags (see reference manual for details) before any other CUDA calls is performed by the host thread. cudaGraphicsResourceSetMapFlags() can be called to specify usage hints (write-only. These functions return a pointer to a CUDA graphics resource of type struct cudaGraphicsResource.

Chapter 3. // Create buffer object and register it with CUDA glGenBuffers(1.g. Please note that since GL_RGBA8UI is an OpenGL 3. texture. A buffer object is registered using cudaGraphicsGLRegisterBuffer(). GL_RGBA8UI). positionsVBO). 2. The following code sample uses a kernel to dynamically modify a 2D width x height grid of vertices stored in a vertex buffer object:
GLuint positionsVBO. cudaGraphicsGLRegisterBuffer(&positionsVBO_CUDA. A texture or renderbuffer object is registered using cudaGraphicsGLRegisterImage(). or 4 components and an internal type of float (e.g. glBindBuffer(GL_ARRAY_BUFFER. &positionsVBO_CUDA. unsigned int size = width * height * 4 * sizeof(float). not the fixed function pipeline. cudaGraphicsMapResources(1. glBufferData(GL_ARRAY_BUFFER. &num_bytes. positionsVBO_CUDA)). 0).1
41
. In CUDA. it appears as a device pointer and can therefore be read and written by kernels or via cudaMemcpy() calls. positionsVBO.g.1. &vbo). // Launch rendering loop glutMainLoop(). GL_DYNAMIC_DRAW). GL_RGBA8). 0. cudaGraphicsMapFlagsWriteDiscard). GL_RGBA_FLOAT32) and unnormalized integer (e. int main() { // Explicitly set device cudaGLSetGLDevice(0). it appears as a CUDA array and can therefore be bound to a texture reference and be read and written by kernels or via cudaMemcpy2D() calls.0 texture format. // Execute kernel
CUDA C Programming Guide Version 3. } void display() { // Map buffer object for writing from CUDA float4* positions.. struct cudaGraphicsResource* positionsVBO_CUDA.. It does not currently support normalized integer formats (e. glBindBuffer(GL_ARRAY_BUFFER. 0). and renderbuffer objects. cudaGraphicsResourceGetMappedPointer((void**)&positions. size_t num_bytes. size. it can only be written by shaders. Programming Interface
The OpenGL resources that may be mapped into the address space of CUDA are OpenGL buffer. cudaGraphicsGLRegisterImage() supports all texture formats with 1. In CUDA. glutDisplayFunc(display). // Initialize OpenGL and GLUT .

The only way to check for asynchronous errors just after some asynchronous function call is therefore to synchronize just after the call by calling cudaThreadSynchronize() (or by using any other synchronization mechanisms described in Section 3. Kernel launches do not return any error code. the application must synchronize in-between the kernel launch and the call to cudaPeekAtLastError() or cudaGetLastError().0f. // Calculate simple sine wave pattern float freq = 4. so to check for asynchronous errors.2. float w = sinf(u * freq + time) * cosf(v * freq + time) * 0.0f.0f .2.1.0f. Note that cudaErrorNotReady that may be returned by cudaStreamQuery() and cudaEventQuery() is not considered an error and is therefore not reported by cudaPeekAtLastError() or cudaGetLastError(). v. typically related to parameter validation. float v = y / (float)height. The runtime maintains an error variable for each host thread that is initialized to cudaSuccess and is overwritten by the error code every time an error occurs (be it a parameter validation error or an asynchronous error). Kernel launches are asynchronous. To ensure that any error returned by cudaPeekAtLastError() or cudaGetLastError() does not originate from calls prior to the kernel launch. but for an asynchronous function (see Section 3.7) and checking the error code returned by cudaThreadSynchronize().Chapter 3. v = v * 2.7). cudaGetLastError() returns this variable and resets it to cudaSuccess. the error code only reports errors that occur on the host prior to executing the task. one has to make sure that the runtime error variable is set to cudaSuccess just before the kernel launch. this error code cannot possibly report any of the asynchronous errors that could occur on the device since the function returns before the device has completed the task.1. so cudaPeekAtLastError() or cudaGetLastError() must be called just after the kernel launch to retrieve any pre-launch errors. if an asynchronous error occurs. for example. by calling cudaGetLastError() just before the kernel launch.9
Error Handling
All runtime functions return an error code. u = u * 2. w.0f . // Write positions positions[y * width + x] = make_float4(u. cudaPeekAtLastError() returns this variable.1.1
49
. Programming Interface
// Calculate uv coordinates float u = x / (float)width.2.5f. it will be reported by some subsequent unrelated runtime function call.
CUDA C Programming Guide Version 3. }
3. __int_as_float(0xff00ff00)).

3
Driver API
The driver API is a handle-based. The driver API must be initialized with cuInit() before any function from the driver API is called.2. // Initialize input vectors .3.
50
CUDA C Programming Guide Version 3. This is because binary code is architecture-specific and therefore incompatible with future architectures. Any application that wants to run on future device architectures must load PTX.1 written using the driver API:
int main() { int N = . Programming Interface
3.1
.1.3. Kernels written in C must therefore be compiled separately into PTX or binary objects. kernels are explicitly loaded as PTX or binary objects by the host code as described in Section 3. The objects available in the driver API are summarized in Table 3-1.Chapter 3. Kernels are launched using API entry points as described in Section 3.
Table 3-1. float* h_B = (float*)malloc(size). not binary code.. A CUDA context must then be created that is attached to a specific device and made current to the calling host thread as detailed in Section 3. readable via texture or surface references Object that describes how to interpret texture memory data Object that describes how to read or write CUDA arrays
Texture reference Surface reference
CUtexref CUsurfref
The driver API is implemented in the nvcuda dynamic library and all its entry points are prefixed with cu.. whereas PTX code is compiled to binary code at load time by the driver.. Here is the host code of the sample from Section 2. Within a CUDA context.3. imperative API: Most objects are referenced by opaque handles that may be specified to functions to manipulate the objects.1.. Objects Available in the CUDA Driver API
Object
Device Context Module Function Heap memory CUDA array
Handle
CUdevice CUcontext CUmodule CUfunction CUdeviceptr CUarray
Description
CUDA-enabled device Roughly equivalent to a CPU process Roughly equivalent to a dynamic library Kernel Pointer to device memory Opaque container for one-dimensional or two-dimensional data on the device.3. // Initialize cuInit(0). size_t size = N * sizeof(float). // Allocate input vectors h_A and h_B in host memory float* h_A = (float*)malloc(size)..

. cuFuncSetBlockShape(vecAdd. The context is then "floating" and may be pushed as the current context for any host thread. Each host thread has a stack of current contexts. int threadsPerBlock = 256.Chapter 3. cuCtxCreate() creates a context with a usage count of 1.. if any. For example. Besides objects such as modules and texture or surface references. blocksPerGrid. 1).3. it is made current to the calling host thread. When a context is created with cuCtxCreate(). if three libraries are loaded to use the same context. cuCtxPopCurrent() also restores the previous current context. Libraries that wish to create their own contexts – unbeknownst to their API clients who may or may not have created contexts of their own – would use cuCtxPushCurrent() and cuCtxPopCurrent() as illustrated in Figure 3-3. CUDA functions that operate in a context (most functions that do not involve device enumeration or context management) will return CUDA_ERROR_INVALID_CONTEXT if a valid context is not current to the thread. cuLaunchGrid(vecAdd. Programming Interface
cuParamSetSize(vecAdd. and the library simply operates on the context handed to it. A host thread may have only one device context current at a time.
52
CUDA C Programming Guide Version 3. that way.
3. each library would call cuCtxAttach() to increment the usage count and cuCtxDetach() to decrement the usage count when the library is done using the context. CUdeviceptr values from different contexts reference different memory locations. All resources and actions performed within the driver API are encapsulated inside a CUDA context. cuCtxAttach() increments the usage count and cuCtxDetach() decrements it. }
Full code can be found in the vectorAddDrv SDK code sample.1. the application can create the context using its own heuristics. each context has its own distinct 32-bit address space. and the system automatically cleans up these resources when the context is destroyed. For most libraries.1
Context
A CUDA context is analogous to a CPU process. 1.1
. cuCtxCreate() pushes the new context onto the top of the stack. A context is destroyed when the usage count goes to 0 when calling cuCtxDetach() or cuCtxDestroy(). it is expected that the application will have created a context before loading or initializing the library. cuCtxPopCurrent() may be called to detach the context from the host thread. 1). threadsPerBlock. offset). As a result. . Usage count facilitates interoperability between third party authored code operating in the same context. A usage count is also maintained for each context. int blocksPerGrid = (N + threadsPerBlock – 1) / threadsPerBlock.

offset += sizeof(c). __alignof(c)). This offset must match the alignment requirement for the parameter type in device code. &ptr. int i. The second argument of each of the cuParam*() functions specifies the offset of the parameter in the parameter stack. __alignof(ptr)). Programming Interface
cuFuncSetSharedSize() sets the size of shared memory for the function. float f. ALIGN_UP(offset. sizeof(f4)).
#define ALIGN_UP(offset. ALIGN_UP(offset. the alignment requirement in device code matches the alignment requirement in host code and can therefore be obtained using __alignof().
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CUDA C Programming Guide Version 3. &f4.
CUdeviceptr is an integer. cuParamSeti(cuFunction.1
. offset. but represents a pointer. cuParamSetv(cuFunction. so its alignment requirement is __alignof(void*). __alignof(i)).Chapter 3. float2 f2. offset. cuParamSeti(cuFunction. Alignment requirements in device code for the built-in vector types are listed in Table B-1. CUdeviceptr dptr. offset += sizeof(ptr).
The cuParam*() family of functions is used to specify the parameters that will be provided to the kernel the next time cuLaunchGrid() or cuLaunch() is invoked to launch the kernel. 16). float4 f4. The only exception is when the host compiler aligns double and long long (and long on a 64-bit system) on a one-word boundary instead of a two-word boundary (for example. offset += sizeof(i). cuParamSeti(cuFunction. using gcc‟s compilation flag -mno-aligndouble) since in device code these types are always aligned on a two-word boundary. ALIGN_UP(offset. For all other basic types.1. ALIGN_UP(offset.
The following code sample uses a macro to adjust the offset of each parameter to meet its alignment requirement. // void* should be used to determine CUdeviceptr‟s alignment void* ptr = (void*)(size_t)dptr. // float4‟s alignment is 16 cuParamSetv(cuFunction. sizeof(ptr)). offset. offset += sizeof(f4). ALIGN_UP(offset. char c. c). alignment) \ (offset) = ((offset) + (alignment) – 1) & ~((alignment) – 1) int offset = 0. __alignof(f)). offset += sizeof(f). offset. offset. i). f).

These functions return a CUDA graphics resource of type CUgraphicsResource. __alignof(size)). 1). Registering a resource is potentially high-overhead and therefore typically called only once per resource. read-only) that the CUDA driver can use to optimize resource management. size). ALIGN_UP(offset.
3. it can be mapped and unmapped as many times as necessary using cuGraphicsMapResources() and cuGraphicsUnmapResources(). stream[i]). start. float elapsedTime. Once a resource is registered to CUDA. cuEventDestroy(stop).
They are destroyed this way:
cuEventDestroy(start). &ptr.11. A resource must be registered to CUDA before it can be mapped using the functions mentioned in Sections 3.1 and 3. cuParamSeti(cuFunction. cuParamSetSize(cuFunction. cuParamSetv(cuFunction. offset. or spin on a synchronous function call can be specified by calling cuCtxCreate() with some specific flags as described in the reference manual.3.2. } for (int i = 0. block. __alignof(ptr)). A mapped resource can be read from or written to by kernels using the device memory address returned by cuGraphicsResourceGetMappedPointer() for buffers and cuGraphicsSubResourceGetMappedArray() for CUDA arrays. cuEventElapsedTime(&elapsedTime. 0). offset += sizeof(ptr). offset.3. sizeof(ptr)). ALIGN_UP(offset. outputDevPtr + i * size.
CUDA C Programming Guide Version 3. sizeof(ptr)). offset).
3. cuEventRecord(stop.3
Synchronous Calls
Whether the host thread will yield. offset.3. Programming Interface
cuParamSetv(cuFunction.Chapter 3. ptr = (void*)(size_t)inputDevPtr. 512. i < 2.10. stream[i]). offset += sizeof(size). cuGraphicsResourceSetMapFlags() can be called to specify usage hints (write-only.11
Graphics Interoperability
The driver API provides functions similar to the runtime API to manage graphics interoperability. ++i) cuMemcpyDtoHAsync(hostPtr + i * size. Accessing a resource through OpenGL or Direct3D while it is mapped to CUDA produces undefined results. &ptr.1
65
. stop). size. 100.11.3. cuEventSynchronize(stop).1. 1. cuFuncSetBlockShape(cuFunction. offset += sizeof(ptr). A CUDA graphics resource is unregistered using cuGraphicsUnregisterResource(). 1. cuLaunchGridAsync(cuFunction.

If a context is created and made current via the driver API.5
Versioning and Compatibility
There are two version numbers that developers should care about when developing a CUDA application: The compute capability that describes the general specifications and features of the compute device (see Section 2.2). // Allocation using runtime API cudaMalloc(&d_data.
3. …). This context can be used by subsequent driver API calls.1. It allows developers to check whether their application requires a newer driver than the one currently installed. CUdeviceptr can be cast to regular pointers and vice-versa:
CUdeviceptr devPtr.Chapter 3. If the runtime is initialized (implicitly as mentioned in Section 3. size). This is important. plug-ins.5) and the version of the CUDA driver API that describes the features supported by the driver API and runtime. Device memory can be allocated and freed using either API. size). // Allocation using driver API cuMemAlloc(&devPtr. because the driver API is backward compatible.1
75
. subsequent runtime calls will pick up this context instead of creating a new one.
In particular. d_data = (float*)(size_t)devPtr. specifically:
CUDA C Programming Guide Version 3. CUBLAS. and libraries (including the C runtime) compiled against a particular version of the driver API will continue to work on subsequent driver releases as illustrated in Figure 3-4. Programming Interface
3. and libraries (including the C runtime) compiled against a particular version of the driver API will not work on previous versions of the driver. float* d_data. cuCtxAttach() can be used to retrieve the context created during initialization. It is important to note that mixing and matching versions is not supported. The driver API is not forward compatible. plug-ins. All functions from the device and version management sections of the reference manual can be used interchangeably. devPtr = (CUdeviceptr)(size_t)d_data.4
Interoperability between Runtime and Driver APIs
An application can mix runtime API code with driver API code. which means that applications. The version of the driver API is defined in the driver header file as CUDA_VERSION. this means that applications written using the driver API can invoke libraries written using the runtime API (such as CUFFT. meaning that applications.

Libs & Plug-ins
Apps.. one can set any device in a system in one of the three following modes using NVIDIA‟s System Management Interface (nvidia-smi). or by making current a context associated to the device.Chapter 3.. plug-ins.  Prohibited compute mode: No host thread can use the device. but Not Forward Compatible
3. The Driver API is Backward. CUBLAS.1 Driver
Incompatible
2.

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CUDA C Programming Guide Version 3.
Figure 3-4. and libraries on a system must use the same version of the CUDA driver API.1
. …).  All plug-ins and libraries used by an application must use the same version of the runtime. This means.. when using the driver API) at the same time.0 Driver
Compatible
1. Programming Interface
All applications.
1. in particular. which is a tool distributed as part of the Linux driver: Default compute mode: Multiple host threads can use the device (by calling cudaSetDevice() on this device.0 Driver
.6
Compute Modes
On Tesla solutions running Linux.  All plug-ins and libraries used by an application must use the same version of any libraries that use the runtime (such as CUFFT. Libs & Plug-ins .1.  Exclusive compute mode: Only one host thread can use the device at any given time. when using the runtime API.. Libs & Plug-ins
Apps.

Apps. that a host thread using the runtime API without explicitly calling cudaSetDevice() might be associated with a device other than device 0 if device 0 turns out to be in prohibited compute mode or in exclusive compute mode and used by another host thread. since only one version of the CUDA driver can be installed on a system. cudaSetValidDevices() can be used to set a device from a prioritized list of devices.

Programming Interface
Applications may query the compute mode of a device by calling cudaGetDeviceProperties() and checking the computeMode property or checking the CU_DEVICE_COMPUTE_MODE attribute using cuDeviceGetAttribute().68 MB to the primary surface rather than 5.24 MB.1
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. the amount of memory needed for the primary surface changes. a mode switch results in any call to the CUDA runtime to fail and return an invalid context error. Therefore.
CUDA C Programming Guide Version 3. if the user changes the display resolution from 1280x1024x32-bit to 1600x1200x32-bit. If a mode switch increases the amount of memory needed for the primary surface. For example.7
Mode Switches
GPUs dedicate some DRAM memory to the so-called primary surface. When users initiate a mode switch of the display by changing the resolution or bit depth of the display (using NVIDIA control panel or the Display control panel on Windows).
3. other events that may initiate display mode switches include launching a full-screen DirectX application.) On Windows. or hitting Ctrl+Alt+Del to lock the computer. (Fullscreen graphics applications running with anti-aliasing enabled may require much more display memory for the primary surface.Chapter 3. which is used to refresh the display device whose output is viewed by the user.1. the system may have to cannibalize memory allocations dedicated to CUDA applications. hitting Alt+Tab to task switch away from a full-screen DirectX application. the system must dedicate 7.

.

it employs a unique architecture called SIMT (Single-Instruction. each warp contains threads of consecutive. As thread blocks terminate. and multiple thread blocks can execute concurrently on one multiprocessor. more so than instruction-level parallelism within a single thread (instructions are pipelined.0. A multiprocessor is designed to execute hundreds of threads concurrently. The term warp originates from weaving.2. but unlike CPU cores they are executed in order and there is no branch prediction and no speculative execution).1 and G.1 and 4. and executes threads in groups of 32 parallel threads called warps. schedules.
4. When a multiprocessor is given one or more thread blocks to execute.x and 2.1.
CUDA C Programming Guide Version 3. the first parallel thread technology. Sections 4.2 describe the architecture features of the streaming multiprocessor that are common to all devices. The way a block is partitioned into warps is always the same.1
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. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. manages. respectively. second. or fourth quarter of a warp. A half-warp is either the first or second half of a warp. it partitions them into warps that get scheduled by a warp scheduler for execution.3.Chapter 4.1
SIMT Architecture
The multiprocessor creates. To manage such a large amount of threads. but they have their own instruction address counter and register state and are therefore free to branch and execute independently. A quarter-warp is either the first. Section 2. third. When a CUDA program on the host CPU invokes a kernel grid. To maximize utilization of its functional units.4. Individual threads composing a warp start together at the same program address.2 describes how thread IDs relate to thread indices in the block. it leverages thread-level parallelism by using hardware multithreading as detailed in Section 4. Multiple-Thread) that is described in Section 4. Hardware Implementation
The CUDA architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). The threads of a thread block execute concurrently on one multiprocessor. Sections G. new blocks are launched on the vacated multiprocessors. increasing thread IDs with the first warp containing thread 0.1 provide the specifics for devices of compute capabilities 1.

require the software to coalesce loads into vectors and manage divergence manually.11) executed by a warp reads. and at every instruction issue time.3. the warp serially executes each branch path taken. different warps execute independently regardless of whether they are executing common or disjoint code paths.3) and which thread performs the final write is undefined. and a parallel data cache or shared memory that is partitioned among the thread blocks.3. Branch divergence occurs only within a warp. Multiple Data) vector organizations in that a single instruction controls multiple processing elements.2. Switching from one execution context to another therefore has no cost. but the order in which they occur is undefined. etc) for each warp processed by a multiprocessor is maintained on-chip during the entire lifetime of the warp. Vector architectures. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. whereas SIMT instructions specify the execution and branching behavior of a single thread.4.1
.2. modify. scalar threads. each read. and when all paths complete. the number of serialized writes that occur to that location varies depending on the compute capability of the device (see Sections G. In practice. write to that location occurs and they are all serialized. These limits as well the amount of registers and shared memory available on the multiprocessor
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CUDA C Programming Guide Version 3. G. and G.4. If an atomic instruction (see Section B. There are also a maximum number of resident blocks and a maximum number of resident warps per multiprocessor. the programmer can essentially ignore the SIMT behavior. A key difference is that SIMD vector organizations expose the SIMD width to the software. For the purposes of correctness. and writes to the same location in global memory for more than one of the threads of the warp.
4. on the other hand. registers. so full efficiency is realized when all 32 threads of a warp agree on their execution path. however. the threads converge back to the same execution path. disabling threads that are not on that path. Hardware Implementation
A warp executes one common instruction at a time. G. In particular. The SIMT architecture is akin to SIMD (Single Instruction. In contrast with SIMD vector machines. each multiprocessor has a set of 32-bit registers that are partitioned among the warps. SIMT enables programmers to write thread-level parallel code for independent. modifies. as well as data-parallel code for coordinated threads.Chapter 4.3. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. the warp scheduler selects a warp that has threads ready to execute (active threads) and issues the next instruction to those threads. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. If threads of a warp diverge via a data-dependent conditional branch.2
Hardware Multithreading
The execution context (program counters.1. The number of blocks and warps that can reside and be processed together on the multiprocessor for a given kernel depends on the amount of registers and shared memory used by the kernel and the amount of registers and shared memory available on the multiprocessor.

 GT is the thread allocation granularity. GW ) Wsize
Rk . which is equal to 512 for devices of compute capability 1.0:
Rblock

ceil ( Rk Wsize . Second. the Direct3D device(s) created by that application can be used for CUDA-Direct3D interoperability (i. y) is equal to x rounded up to the nearest multiple of y. GS )
Sk is the amount of shared memory used by the kernel in bytes. real interoperability only happens with the copy of a Direct3D resource in that GPU (note: in AFR mode Direct3D resources that must be in GPU memory are duplicated in the GPU memory of each GPU in the SLI
CUDA C Programming Guide Version 3. The total number of registers Rblock allocated for a block is as follows: For devices of compute capability 1.  ceil(x.1
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. passed as a parameter to cudaD3D[9|10]SetDirect3DDevice() when using the runtime API). and 64 for devices of compute capability 2.x and 128 for devices of compute capability 2. GT ) Wblock
GW is the warp allocation granularity. If there are not enough registers or shared memory available per multiprocessor to process at least one block. all CUDA-enabled GPUs are accessible via the CUDA driver and runtime as separate devices.x only).0.. equal to 2 (compute capability 1. The total number of warps Wblock in a block is as follows:
Wblock

ceil(
T .  Wsize is the warp size. allocations may fail earlier than otherwise expected.3
Multiple Devices
In a system with multiple GPUs.0 and 1. Because of this. This CUDA device only executes the CUDA work on one of the GPUs in the SLI configuration.3.
4.x:
Rblock
ceil (ceil (Wblock . an allocation in one CUDA device on one GPU will consume memory on other GPUs. when a Direct3D application runs in SLI Alternate Frame Rendering mode.  GS is the shared memory allocation granularity.e.0. There are however special considerations as described below when the system is in SLI mode. equal to 256 for devices of compute capability 1.1. and 512 for devices of compute capability 1. First.1) Wsize
T is the number of threads per block. the kernel will fail to launch. The total amount of shared memory Sblock in bytes allocated for a block is as follows:
S block

ceil(S k .2 and 1. which is equal to 32.Chapter 4: Hardware Implementation
are a function of the compute capability of the device and are given in Appendix G. GT )
For devices of compute capability 2. As a consequence.1. but only one CUDA device can be created at a time from one of these Direct3D devices.  Rk is the number of registers used by the kernel.

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. Hardware Implementation
configuration). In some cases this is not the desired behavior and an application may need to forfeit use of the CUDA-Direct3D interoperability API and manually copy the output of its CUDA work to Direct3D resources using the existing CUDA and Direct3D API.Chapter 4.1.

and the bus connecting the host to the devices. for example.1
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. at points in the algorithm where parallelism is broken because some threads need to synchronize in order to share data with each other.
5.Chapter 5. optimizing instruction usage of a kernel that is mostly limited by memory accesses will not yield any significant performance gain.2
Maximize Utilization
To maximize utilization the application should be structured in a way that it exposes as much parallelism as possible and efficiently maps this parallelism to the various components of the system to keep them busy most of the time. in which case
CUDA C Programming Guide Version 3.  Optimize memory usage to achieve maximum memory throughput.2.1
Overall Performance Optimization Strategies
Performance optimization revolves around three basic strategies: Maximize parallel execution to achieve maximum utilization. For the parallel workloads. Performance Guidelines
5. there are two cases: Either these threads belong to the same block.

5. Optimization efforts should therefore be constantly directed by measuring and monitoring the performance limiters. Also. Which strategies will yield the best performance gain for a particular portion of an application depends on the performance limiters for that portion. the application should maximize parallel execution between the host.7.2. the devices. It should assign to each processor the type of work it does best: serial workloads to the host. parallel workloads to the devices. comparing the floating-point operation throughput or memory throughput – whichever makes more sense – of a particular kernel to the corresponding peak theoretical throughput of the device indicates how much room for improvement there is for the kernel.  Optimize instruction usage to achieve maximum instruction throughput.1
Application Level
At a high level. by using asynchronous functions calls and streams as described in Section 3. for example using the CUDA profiler.

The number of clock cycles it takes for a warp to be ready to execute its next instruction is called latency. For example. How many instructions are required to hide latency depends on the instruction throughput. a warp scheduler selects a warp that is ready to execute. and full utilization is achieved when the warp scheduler always has some instruction to issue for some warp at every clock cycle during that latency period.3
Multiprocessor Level
At an even lower level. one for writing to and one for reading from global memory. As described in Section 4.2
Device Level
At a lower level.7.0.2. or they belong to different blocks. so the kernel should be launched with at least as many thread blocks as there are multiprocessors in the device. and issues the next instruction to the active threads of the warp.x since a multiprocessor issues one such instruction per warp over 4 clock cycles. as mentioned in Section G. as mentioned in Section G. or in other words. Utilization is therefore directly linked to the number of resident warps.2. For devices of compute capability 2.1
.2. when the latency of each warp is completely “hidden” by other warps. Its occurrence should therefore be minimized by mapping the algorithm to the CUDA programming model in such a way that the computations that require inter-thread communication are performed within a single thread block as much as possible. only one kernel can execute on a device at one time. For devices of compute capability 1. a GPU multiprocessor relies on thread-level parallelism to maximize utilization of its functional units.4. if any. multiple kernels can execute concurrently on a device.Chapter 5. The most common reason a warp is not ready to execute its next instruction is that the instruction‟s input operands are not yet available.3.1.1. in which case they must share data through global memory using two separate kernel invocations.1. the application should maximize parallel execution between the multiprocessors of a device.
5.0 since a multiprocessor issues the two instructions for a pair of warps over 2 clock cycles.
Performance Guidelines they should use __syncthreads() and share data through shared memory within the same kernel invocation.2. so maximum utilization can also be achieved by using streams to enable enough kernels to execute concurrently as described in Section 3. The second case is much less optimal since it adds the overhead of extra kernel invocations and global memory traffic. At every instruction issue time.x. the application should maximize parallel execution between the various functional units within a multiprocessor.  L/2 (rounded up to nearest integer) instructions are required for devices of compute capability 2.
5.

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CUDA C Programming Guide Version 3. to hide a latency of L clock cycles with basic single-precision floating-point arithmetic instructions (scheduled on CUDA cores): L/4 (rounded up to nearest integer) instructions are required for devices of compute capability 1.

The number of warps required to keep the warp scheduler busy during such high latency periods depends on the kernel code.x and 11 warps for devices of compute capability 2. the CUDA Software Development Kit provides a spreadsheet.2.e. the latency is much higher: 400 to 800 clock cycles. shared. for example. and for devices of compute capability 1. Having multiple resident blocks per multiprocessor can help reduce idling in this case.e.e. as warps from different blocks do not need to wait for each other at synchronization points.x. 16 warps) can be resident since two blocks would require 2x512x17 registers. called the CUDA Occupancy Calculator. If this ratio is 10. Another reason a warp is not ready to execute its next instruction is that it is waiting at some memory fence (Section B.1. In the case of a back-to-back register dependency (i.e..6). and the resource requirements of the kernel as described in Section 4. i.2. only one block (i. the amount of dynamically allocated shared memory.
Performance Guidelines
If all input operands are registers. The total amount of shared memory required for a block is equal to the sum of the amount of statically allocated shared memory. the amount of shared memory used to pass the kernel‟s arguments (see Section B.1
85
.15). A synchronization point can force the multiprocessor to idle as more and more warps wait for other warps in the same block to complete execution of instructions prior to the synchronization point. But as soon as the kernel uses one more register... local. Register. which translates to 6 warps for devices of compute capability 1. for devices of compute capability 1. The number of blocks and warps residing on each multiprocessor for a given kernel call depends on the execution configuration of the call (Section B.. the latency is equal to the execution time of the previous instruction and the warp scheduler must schedule instructions for different warps during that time.. then to hide latencies of about 600 clock cycles. in general. if a kernel uses 16 registers and each block has 512 threads and requires very little shared memory. where occupancy is defined as the ratio of the number of resident warps to the maximum number of resident warps (given in Appendix G for various compute capabilities). For example.1. some input operand is written by the previous instruction). Execution time varies depending on the instruction.x and about 30 for devices of compute capability 2. To assist programmers in choosing thread block size based on register and shared memory requirements.e. and constant memory usages are reported by the compiler when compiling with the --ptxas-options=-v option. 32 warps) can reside on the multiprocessor since they require 2x512x16 registers. which exactly matches the number of registers available on the multiprocessor. Therefore. The number of registers used by a kernel can have a significant impact on the number of resident warps. which is more registers than are available on the multiprocessor. arithmetic instructions most of the time) to the number of instructions with off-chip memory operands is low (this ratio is commonly called the arithmetic intensity of the program).5) or synchronization point (Section B. then two blocks (i.0.Chapter 5. latency is caused by register dependencies. more warps are required if the ratio of the number of instructions with no off-chip memory operands (i. some of the input operands are written by some previous instruction(s) whose execution has not completed yet. If some input operand resides in off-chip memory.0. the compiler attempts to minimize register usage while keeping register
CUDA C Programming Guide Version 3. about 15 warps are required for devices of compute capability 1.4). the memory resources of the multiprocessor. but it is typically about 22 clock cycles.

However.2) and the number of instructions to a minimum. for which global memory accesses are data-dependent). devices of compute capability 1.  Synchronize again if necessary to make sure that shared memory has been updated with the results. That means minimizing data transfers between the host and the device.Chapter 5.16. Experimentation is therefore recommended. as detailed in Section 5.3. Applications can also parameterize execution configurations based on register file size and shared memory size.g. As illustrated in Section 3.1. the same on-chip memory is used for both L1 and shared memory.e. Shared memory is equivalent to a user-managed cache: The application explicitly allocates and accesses it. The number of threads per block should be chosen as a multiple of the warp size to avoid wasting computing resources with under-populated warps as much as possible.2.2.1
. That also means minimizing data transfers between global memory and the device by maximizing use of on-chip memory: shared memory and caches (i.0. texture cache and constant cache available on all devices). a traditional hardware-managed cache is more appropriate to exploit data locality.e.  Synchronize with all the other threads of the block so that each thread can safely read shared memory locations that were populated by different threads. As mentioned in Section G. devices of compute capability 1.
Performance Guidelines spilling (see Section 5.2 and higher) and each long long variable uses two registers. Each double variable (on devices that supports native double precision.1. For some applications (e. L1/L2 caches available on devices of compute capability 2. in other words. since these have much lower bandwidth than data transfers between global memory and the device.4. The effect of execution configuration on performance for a given kernel call generally depends on the kernel code.3. all of which can be queried using the runtime or driver API (see reference manual).

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CUDA C Programming Guide Version 3.  Write the results back to device memory.  Process the data in shared memory.3
Maximize Memory Throughput
The first step in maximizing overall memory throughput for the application is to minimize data transfers with low bandwidth.2 and higher have at least twice as many registers per multiprocessor as devices with lower compute capability. to have each thread of a block: Load data from device memory to shared memory.
5. a typical programming pattern is to stage data coming from device memory into shared memory. for devices of compute capability 2. as well as on the number of multiprocessors and memory bandwidth of the device. which depends on the compute capability of the device.2. and how much of it is dedicated to L1 versus shared memory is configurable for each kernel call. Register usage can be controlled using the -maxrregcount compiler option or launch bounds as described in Section B. i.1.0.

5.
Performance Guidelines
The throughput of memory accesses by a kernel can vary by an order of magnitude depending on access pattern for each type of memory.5.3. operated on by the device.2. One way to accomplish this is to move more code from the host to the device.2
Device Memory Accesses
An instruction that accesses addressable memory (i. global.3.3). Also. the more scattered the addresses are. 5.1.3.1
87
. Assuming that they are and that the mapped memory is read or written only once. so non-optimal global memory accesses have a higher impact on performance.
5.1.2. local.3. shared. Data transfers are implicitly performed each time the kernel accesses the mapped memory..
CUDA C Programming Guide Version 3.e. On systems with a front-side bus. even if that means running kernels with low parallelism computations.3. higher performance for data transfers between host and device is achieved by using page-locked host memory as described in Section 3. using mapped page-locked memory instead of explicit copies between device and host memory can be a win for performance.Chapter 5. For example. or texture memory) might need to be re-issued multiple times depending on the distribution of the memory addresses across the threads within the warp. and destroyed without ever being mapped by the host or copied to host memory. these memory accesses must be coalesced as with accesses to global memory (see Section 5. batching many small transfers into a single large transfer always performs better than making each transfer separately. and 5.
5. any copy between host and device memory is superfluous and mapped pagelocked memory should be used instead.2. On integrated systems where device memory and host memory are physically the same. because of the overhead associated with each transfer. How the distribution affects the instruction throughput this way is specific to each type of memory and described in the following sections.6.3.2. the more reduced the throughput is. In addition. for global memory.2. constant. 5. The next step in maximizing memory throughput is therefore to organize memory accesses as optimally as possible based on the optimal memory access patterns described in Sections 5. Applications may query whether a device is integrated or not by calling cudaGetDeviceProperties() and checking the integrated property or checking the CU_DEVICE_ATTRIBUTE_INTEGRATED attribute using cuDeviceGetAttribute(). For maximum performance. Intermediate data structures may be created in device memory. when using mapped page-locked memory (Section 3.3.4.2. there is no need to allocate any device memory and explicitly copy data between device and host memory.3.1
Data Transfer between Host and Device
Applications should strive to minimize data transfer between the host and the device. This optimization is especially important for global memory accesses as global memory bandwidth is low.1).2. as a general rule.

e.3. when accessing a two-dimensional array as described in Section 5.1. The alignment requirement is automatically fulfilled for the built-in types of Section B. These memory transactions must be naturally aligned: Only the 32-. For devices of compute capability 2. How many transactions are necessary and how throughput is ultimately affected varies with the compute capability of the device.1
.1
Global Memory
Global memory resides in device memory and device memory is accessed via 32-. the more transactions are necessary. In general.
Performance Guidelines
5.2 give more details on how global memory accesses are handled for various compute capabilities.3. To maximize global memory throughput.1. for example. They are much more relaxed for devices of higher compute capabilities.3. 2. 8.3.2.2. For structures.1.2. For example. whose first address is a multiple of their size) can be read or written by memory transactions. When a warp executes an instruction that accesses global memory. so data locality is exploited to reduce impact on throughput.4.3. it coalesces the memory accesses of the threads within the warp into one or more of these memory transactions depending on the size of the word accessed by each thread and the distribution of the memory addresses across the threads. reducing the instruction throughput accordingly. It is therefore recommended to use types that meet this requirement for data that resides in global memory.2. the access compiles to multiple instructions with interleaved access patterns that prevent these instructions from fully coalescing. 64-.
 
5. the more unused words are transferred in addition to the words accessed by the threads. or 16 bytes. For devices of compute capability 1. the requirements on the distribution of the addresses across the threads to get any coalescing at all are very strict.2. 4. or 128-byte segments of device memory that are aligned to their size (i.1.e. Sections G.1
Size and Alignment Requirement
Global memory instructions support reading or writing words of size equal to 1.0 and 1. throughput is divided by 8. the memory transactions are cached. 2. Any access (via a variable or a pointer) to data residing in global memory compiles to a single global memory instruction if and only if the size of the data type is 1. such as
struct __align__(8) { float x.3.1 like float2 or float4.  Padding data in some cases.2 and G.0.
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CUDA C Programming Guide Version 3. its address is a multiple of that size).1.3. the size and alignment requirements can be enforced by the compiler using the alignment specifiers __align__(8) or __align__(16). 64-. or 128-byte memory transactions.1.2 and G. if a 32-byte memory transaction is generated for each thread‟s 4-byte access. 4. or 16 bytes and the data is naturally aligned (i. If this size and alignment requirement is not fulfilled.Chapter 5. Using data types that meet the size and alignment requirement detailed in Section 5.4. 8. it is therefore important to maximize coalescing by: Following the most optimal access patterns based on Sections G.2.

Automatic variables that the compiler is likely to place in local memory are: Arrays for which it cannot determine that they are indexed with constant quantities. float z. located at address BaseAddress of type type* (where type meets the requirement described in Section 5.2.
or
struct __align__(16) { float x.2.3. in which case the starting address of each array is offset from the block‟s starting address. so special care must be taken to maintain alignment of the starting address of any value or array of values of these types.2
Two-Dimensional Arrays
A common global memory access pattern is when each thread of index (tx.1
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.
Any address of a variable residing in global memory or returned by one of the memory allocation routines from the driver or runtime API is always aligned to at least 256 bytes.x).
5. In particular. A typical case where this might be easily overlooked is when using some custom global memory allocation scheme. The cudaMallocPitch() and cuMemAllocPitch() functions and associated memory copy functions described in the reference manual enable programmers to write non-hardware-dependent code to allocate arrays that conform to these constraints.2.2
Local Memory
Local memory accesses only occur for some automatic variables as mentioned in Section B. float y.1. }.1.
Performance Guidelines
float y. Reading non-naturally aligned 8-byte or 16-byte words produces incorrect results (off by a few words).1.3. }. this means that an array whose width is not a multiple of this size will be accessed much more efficiently if it is actually allocated with a width rounded up to the closest multiple of this size and its rows padded accordingly.ty) uses the following address to access one element of a 2D array of width width.5.  Large structures or arrays that would consume too much register space.1):
BaseAddress + width * ty + tx
For these accesses to be fully coalesced.3.Chapter 5.  Any variable if the kernel uses more registers than available (this is also known as register spilling). both the width of the thread block and the width of the array must be a multiple of the warp size (or only half the warp size for devices of compute capability 1.
5.2. whereby the allocations of multiple arrays (with multiple calls to cudaMalloc() or cuMemAlloc()) is replaced by the allocation of a single large block of memory partitioned into multiple arrays. Inspection of the PTX assembly code (obtained by compiling with the –ptx or -keep option) will tell if a variable has been placed in local memory during the first

CUDA C Programming Guide Version 3.

Chapter 5.

Performance Guidelines compilation phases as it will be declared using the .local mnemonic and accessed using the ld.local and st.local mnemonics. Even if it has not, subsequent compilation phases might still decide otherwise though if they find it consumes too much register space for the targeted architecture: Inspection of the cubin object using cuobjdump will tell if this is the case. Also, the compiler reports total local memory usage per kernel (lmem) when compiling with the --ptxas-options=-v option. Note that some mathematical functions have implementation paths that might access local memory. The local memory space resides in device memory, so local memory accesses have same high latency and low bandwidth as global memory accesses and are subject to the same requirements for memory coalescing as described in Section 5.3.2.1. Local memory is however organized such that consecutive 32-bit words are accessed by consecutive thread IDs. Accesses are therefore fully coalesced as long as all threads in a warp access the same relative address (e.g. same index in an array variable, same member in a structure variable). On devices of compute capability 2.0, local memory accesses are always cached in L1 and L2 in the same way as global memory accesses (see Section G.4.2).

5.3.2.3

Shared Memory
Because it is on-chip, the shared memory space is much faster than the local and global memory spaces. In fact, for all threads of a warp, accessing shared memory is fast as long as there are no bank conflicts between the threads, as detailed below. To achieve high bandwidth, shared memory is divided into equally-sized memory modules, called banks, which can be accessed simultaneously. Any memory read or write request made of n addresses that fall in n distinct memory banks can therefore be serviced simultaneously, yielding an overall bandwidth that is n times as high as the bandwidth of a single module. However, if two addresses of a memory request fall in the same memory bank, there is a bank conflict and the access has to be serialized. The hardware splits a memory request with bank conflicts into as many separate conflict-free requests as necessary, decreasing throughput by a factor equal to the number of separate memory requests. If the number of separate memory requests is n, the initial memory request is said to cause n-way bank conflicts. To get maximum performance, it is therefore important to understand how memory addresses map to memory banks in order to schedule the memory requests so as to minimize bank conflicts. This is described in Sections G.3.3 and G.4.3 for devices of compute capability 1.x and 2.0, respectively.

5.3.2.4

Constant Memory
The constant memory space resides in device memory and is cached in the constant cache mentioned in Sections G.3.1 and G.4.1. For devices of compute capability 1.x, a constant memory request for a warp is first split into two requests, one for each half-warp, that are issued independently. A request is then split into as many separate requests as there are different memory addresses in the initial request, decreasing throughput by a factor equal to the number of separate requests.

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The resulting requests are then serviced at the throughput of the constant cache in case of a cache hit, or at the throughput of device memory otherwise.

5.3.2.5

Texture Memory
The texture memory space resides in device memory and is cached in texture cache, so a texture fetch costs one memory read from device memory only on a cache miss, otherwise it just costs one read from texture cache. The texture cache is optimized for 2D spatial locality, so threads of the same warp that read texture addresses that are close together in 2D will achieve best performance. Also, it is designed for streaming fetches with a constant latency; a cache hit reduces DRAM bandwidth demand but not fetch latency. Reading device memory through texture fetching present some benefits that can make it an advantageous alternative to reading device memory from global or constant memory: If the memory reads do not follow the access patterns that global or constant memory reads must respect to get good performance (see Sections 5.3.2.1 and 5.3.2.4), higher bandwidth can be achieved providing that there is locality in the texture fetches (this is less likely for devices of compute capability 2.0 given that global memory reads are cached on these devices);  Addressing calculations are performed outside the kernel by dedicated units;  Packed data may be broadcast to separate variables in a single operation;  8-bit and 16-bit integer input data may be optionally converted to 32-bit floating-point values in the range [0.0, 1.0] or [-1.0, 1.0] (see Section 3.2.4.1). However, within the same kernel call, the texture cache is not kept coherent with respect to global memory writes, so that any texture fetch to an address that has been written to via a global write in the same kernel call returns undefined data. In other words, a thread can safely read via texture some memory location only if this memory location has been updated by a previous kernel call or memory copy, but not if it has been previously updated by the same thread or another thread from the same kernel call. This is only relevant when fetching from linear memory as a kernel cannot write to CUDA arrays in any case.


5.4

Maximize Instruction Throughput
To maximize instruction throughput the application should: Minimize the use of arithmetic instructions with low throughput; this includes trading precision for speed when it does not affect the end result, such as using intrinsic instead of regular functions (intrinsic functions are listed in Section C.2), single-precision instead of double-precision, or flushing denormalized numbers to zero;  Minimize divergent warps caused by control flow instructions as detailed in Section 5.4.2;  Reduce the number of instructions, for example, by optimizing out synchronization points whenever possible as described in Section 5.4.3 or by using restricted pointers as described in Section E.3. In this section, throughputs are given in number of operations per clock cycle per multiprocessor. For a warp size of 32, one instruction results in 32 operations.


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Chapter 5.

Performance Guidelines Therefore, if T is the number of operations per clock cycle, the instruction throughput is one instruction every 32/T clock cycles. All throughputs are for one multiprocessor. They must be multiplied by the number of multiprocessors in the device to get throughput for the whole device.

5.4.1

Arithmetic Instructions
Table 5-1 gives the throughputs of the arithmetic instructions that are natively supported in hardware for devices of various compute capabilities. For devices of compute capability 2.0, two different warps execute half of the operations each clock cycle (see Section G.4.1).

Other instructions and functions are implemented on top of the native instructions. The implementation may be different for devices of compute capability 1.x and devices of compute capability 2.0, and the number of native instructions after compilation may fluctuate with every compiler version. For complicated functions, there can be multiple code paths depending on input. cuobjdump can be used to inspect a particular implementation in a cubin object. The implementation of some functions are readily available on the CUDA header files (math_functions.h, device_functions.h, …). In general, code compiled with -ftz=true (denormalized numbers are flushed to zero) tends to have higher performance than code compiled with -ftz=false. Similarly, code compiled with -prec-div=false (less precise division) tends to
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1
93
.
Single-Precision Floating-Point Division
__fdividef(x.3. (i.h for implementation) comprises two code paths referred to as the fast path and the slow path. and 44 bytes are used by doubleprecision functions. with -prec-div=false and -prec-sqrt=false). which may affect performance because of local memory high latency and bandwidth (see Section 5.d.z.0. The fast path is used for arguments sufficiently small in magnitude and essentially consists of a few multiply-add operations.u]. More precisely. the argument reduction code for the trigonometric functions selects the fast path for arguments whose magnitude is less than 48039.0 for the double-precision functions.2). and code compiled with -prec-sqrt=false (less precise square root) tends to have higher performance than code compiled with -prec-sqrt=true. the exact amount is subject to change.
Single-Precision Floating-Point Square Root
Single-precision floating-point square root is implemented as a reciprocal square root followed by a reciprocal instead of a reciprocal square root followed by a multiplication so that it gives correct results for 0 and infinity. At present. and corresponding double-
precision instructions are much more expensive and even more so if the argument x is large in magnitude. The nvcc user manual describes these compilation flags in more details.0/sqrtf() into rsqrtf() only when both reciprocal and square root are approximate.1) compile to tens of instructions for devices of compute capability 1.u].
Sine and Cosine
sinf(x). an attempt has been made to reduce register pressure in the slow path by storing some intermediate variables in local memory. the argument reduction code (see math_functions.u] (see
Section C. its throughput is 1 operation per clock cycle for devices of compute capability 1. y) (see Section C.0f for the singleprecision functions. At present. __fmul_r[d.Chapter 5.
Single-Precision Floating-Point Addition and Multiplication Intrinsics
__fadd_r[d.e. sincosf(x). cosf(x).x.x and 2 operations per clock cycle for devices of compute capability 2.2.0.
Single-Precision Floating-Point Reciprocal Square Root
To preserve IEEE-754 semantics the compiler can optimize 1. However.2. but map to a single native instruction for devices of compute capability 2. As the slow path requires more registers than the fast path. It is therefore recommended to invoke rsqrtf() directly where desired.
Performance Guidelines
have higher performance code than code compiled with -prec-div=true. and __fmaf_r[n. 28 bytes of local memory are used by single-precision functions. Therefore. The slow path is used for arguments large in magnitude and consists of lengthy computations required to achieve correct results over the entire argument range.1) provides faster single-precision floating-
point division than the division operator. tanf(x).
CUDA C Programming Guide Version 3.1. and less than 2147483648. respectively.2.

x.2. while) can significantly impact the effective instruction throughput by causing threads of the same warp to diverge (i. to follow different execution paths). and __ffsll (see Section C. When all the different execution paths have completed.e.2.
Integer Arithmetic
On devices of compute capability 1. the threads converge back to the same execution path. This last case can be avoided by using single-precision floating-point constants. those constants defined without any type suffix) used as input to single-precision floating-point computations (as mandated by C/C++ standards). This is the case for: Functions operating on variables of type char or short whose operands generally need to be converted to int. They can be replaced with bitwise operations in some cases: If n is a power of 2.
Type Conversion
Sometimes.x.

5.1. do.0.x. but __brev and __popc map to a single instruction for devices of compute capability 2.Chapter 5. the compiler will perform these conversions if n is literal.4. On devices of compute capability 2. the different executions paths have to be serialized. Integer division and modulo operation are costly: tens of instructions on devices of compute capability 1. below 20 instructions on devices of compute capability 2. the throughput of these trigonometric functions is lower by one order of magnitude when the slow path reduction is required as opposed to the fast path reduction. __popc.x. switch. (i/n) is equivalent to (i>>log2(n)) and (i%n) is equivalent to (i&(n-1)). and __popcll (see Section C.
__brev. increasing the total number of instructions executed for this warp. the compiler must insert conversion instructions. 32-bit integer multiplication is implemented using multiple instructions as it is not natively supported.0 than for devices of compute capability 1. 1. It can have the opposite effect however in cases where the use of __[u]mul24 inhibits compiler optimizations.0. 0.3) compile to tens of instructions for devices of compute capability 1.  Double-precision floating-point constants (i.0 and __brevll and __popcll to just a few. __ffs. __clz.2. __clzll.3) compile to fewer
instructions for devices of compute capability 2. 24-bit integer multiplication is natively supported however via the __[u]mul24 intrinsic (see Section C.
CUDA C Programming Guide Version 3. for.e.141592653589793f.1
94
. introducing additional execution cycles. If this happens. 32-bit integer multiplication is natively supported. defined with an f suffix such as 3. __brevll. __[u]mul24 is therefore implemented using multiple instructions and should not be used.5f. but 24-bit integer multiplication is not.3). Using __[u]mul24 instead of the 32-bit multiplication operator whenever possible usually improves performance for instruction bound kernels.2
Control Flow Instructions
Any flow control instruction (if.0f.
Performance Guidelines Due to the lengthy computations and use of local memory in the slow path.

. This is possible because the distribution of the warps across the block is deterministic as mentioned in Section 4. this threshold is 7.e.1. Sometimes. __syncthreads(). only the instructions with a true predicate are actually executed. depending on whether the memory read occurs before or after the memory write from myArray[tid + 1] = 2. and also do not evaluate addresses or read operands.1
95
. the controlling condition should be written so as to minimize the number of divergent warps.
// myArray is an array of integers located in global or shared // memory __global__ void MyKernel(int* result) { int tid = threadIdx. result[i] = 2 * myArray[i] for i > 0).
CUDA C Programming Guide Version 3. the compiler may unroll loops or it may optimize out if or switch statements by using branch predication instead. for example.1. . no warp can ever diverge.3
Synchronization Instruction
Throughput for __syncthreads() is 8 operations per clock cycle for devices of compute capability 1. Instead. __syncthreads().2. no warp diverges since the controlling condition is perfectly aligned with the warps.
Performance Guidelines
To obtain best performance in cases where the control flow depends on the thread ID.x. In the following code sample. threads within a warp are implicitly synchronized and this can sometimes be used to omit __syncthreads() for better performance.4. both calls to __syncthreads() are required to get the expected result (i. In this case. Because a warp executes one common instruction at a time. Instructions with a false predicate do not write results.3. as detailed below. The compiler replaces a branch instruction with predicated instructions only if the number of instructions controlled by the branch condition is less or equal to a certain threshold: If the compiler determines that the condition is likely to produce many divergent warps. each of them is associated with a per-thread condition code or predicate that is set to true or false based on the controlling condition and although each of these instructions gets scheduled for execution. Without synchronization. any of the two references to myArray[tid] could return either 2 or the value initially stored in myArray..2). The programmer can also control loop unrolling using the #pragma unroll directive (see Section E. otherwise it is 4. A trivial example is when the controlling condition only depends on (threadIdx / warpSize) where warpSize is the warp size. Note that __syncthreads() can impact performance by forcing the multiprocessor to idle as detailed in Section 5. int ref1 = myArray[tid].x and 16 operations per clock cycle for devices of compute capability 2.
5. myArray[tid + 1] = 2. In these cases.Chapter 5. When using branch predication none of the instructions whose execution depends on the controlling condition gets skipped.0.

Function Type Qualifiers
Function type qualifiers specify whether a function executes on the host or on the device and whether it is callable from the host or from the device.

B.1.1

__device__
The __device__ qualifier declares a function that is: Executed on the device  Callable from the device only.


B.1.2

__global__
The __global__ qualifier declares a function as being a kernel. Such a function is: Executed on the device,  Callable from the host only.


B.1.3

__host__
The __host__ qualifier declares a function that is: Executed on the host,  Callable from the host only. It is equivalent to declare a function with only the __host__ qualifier or to declare it without any of the __host__, __device__, or __global__ qualifier; in either case the function is compiled for the host only.


However, the __host__ qualifier can also be used in combination with the __device__ qualifier, in which case the function is compiled for both the host and the device.

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Appendix B.

C Language Extensions

B.1.4

Restrictions
__global__ functions must have void return type.

Any call to a __global__ function must specify its execution configuration as described in Section B.15. A call to a __global__ function is asynchronous, meaning it returns before the device has completed its execution.
__global__ function parameters are passed to the device:

arguments. Function pointers to __global__ functions are supported, but function pointers to __device__ functions are only supported in device code compiled for devices of compute capability 2.0.
__global__ functions do not support recursion. __device__ functions only support recursion in device code compiled for devices

of compute capability 2.0. In device code compiled for devices of compute capability 1.x, a __device__ function is always inlined by default. The __noinline__ function qualifier however can be used as a hint for the compiler not to inline the function if possible (see Section E.1). On devices of compute capability 2.0, the size of the call stack can be queried using cudaThreadGetLimit() or cuCtxGetLimit(), and set using cudaThreadSetLimit() or cuCtxSetLimit(). The __global__ and __host__ qualifiers cannot be used together. The __device__ and __host__ qualifiers can be used together however and the __CUDA_ARCH__ macro introduced in Section 3.1.4 can be used to differentiate code paths between host and device:
__host__ __device__ func() { #if __CUDA_ARCH__ == 100 // Device code path for compute capability 1.0 #elif __CUDA_ARCH__ == 200 // Device code path for compute capability 2.0 #elif !defined(__CUDA_ARCH__) // Host code path #endif }

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Appendix B.

C Language Extensions

B.2
B.2.1

Variable Type Qualifiers
Variable type qualifiers specify the memory location on the device of a variable.

__device__
The __device__ qualifier declares a variable that resides on the device. At most one of the other type qualifiers defined in the next three sections may be used together with __device__ to further specify which memory space the variable belongs to. If none of them is present, the variable: Resides in global memory space, Has the lifetime of an application,  Is accessible from all the threads within the grid and from the host through the runtime library (cudaGetSymbolAddress() / cudaGetSymbolSize() / cudaMemcpyToSymbol() / cudaMemcpyFromSymbol() for the runtime API and cuModuleGetGlobal() for the driver API).
 

B.2.2

__constant__
The __constant__ qualifier, optionally used together with __device__, declares a variable that: Resides in constant memory space,  Has the lifetime of an application,  Is accessible from all the threads within the grid and from the host through the runtime library (cudaGetSymbolAddress() / cudaGetSymbolSize() / cudaMemcpyToSymbol() / cudaMemcpyFromSymbol() for the runtime API and cuModuleGetGlobal() for the driver API).


B.2.3

__shared__
The __shared__ qualifier, optionally used together with __device__, declares a variable that: Resides in the shared memory space of a thread block,  Has the lifetime of the block,  Is only accessible from all the threads within the block. When declaring a variable in shared memory as an external array such as
 extern __shared__ float shared[];

the size of the array is determined at launch time (see Section B.15). All variables declared in this fashion, start at the same address in memory, so that the layout of the variables in the array must be explicitly managed through offsets. For example, if one wants the equivalent of
short array0[128]; float array1[64];

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or __syncthreads() (Sections B. but the second reference does not as the compiler simply reuses the result of the first read.
104
CUDA C Programming Guide Version 3. int ref1 = myArray[tid] * 1.
B.1
. float* array1 = (float*)&array0[128].3. that ref2 will be equal to 2 in thread tid since thread tid might read myArray[tid] into ref2 before thread tid-1 overwrites its value by 2. the compiler assumes that its value can be changed at any time by another thread and therefore any reference to this variable compiles to an actual memory read instruction.Appendix B. __device__ void func() // __device__ or __global__ function { short* array0 = (short*)array. int* array2 = (int*)&array1[64]. int ref2 = myArray[tid] * 1. Note that even if myArray is declared as volatile in the code sample above. This behavior can be changed using the volatile keyword: If a variable located in global or shared memory is declared as volatile. the first reference to myArray[tid] compiles into a global or shared memory read instruction. in general. result[tid] = ref1 * ref2. the compiler is free to optimize reads and writes to global or shared memory. }
Therefore. there is no guarantee.2. for example.5 and B.1.4
volatile
Only after the execution of a __threadfence_block(). in the code sample below. __threadfence().
in dynamically allocated shared memory. myArray[tid + 1] = 2. Synchronization is required as mentioned in Section 5. ref2 cannot possibly be equal to 2 in thread tid as a result of thread tid-1 overwriting myArray[tid] by 2.x. does not work since array1 is not aligned to 4 bytes. As long as this requirement is met.6) are prior writes to global or shared memory guaranteed to be visible by other threads.
C Language Extensions
int array2[256]. one could declare and initialize the arrays the following way:
extern __shared__ char array[]. For example. so the following code. __device__ void func() // __device__ or __global__ function { short* array0 = (short*)array. }
Note that pointers need to be aligned to the type they point to. }
Alignment requirements for the built-in vector types are listed in Table B-1.
extern __shared__ char array[].4. float* array1 = (float*)&array0[127].
// myArray is an array of non-zero integers // located in global or shared memory __global__ void MyKernel(int* result) { int tid = threadIdx.

4).
__shared__ variables cannot have an initialization as part of their declaration. on formal parameters and on local variables within a function that executes on the host.1 and 3. __device__.2.1
105
. most often in a segmentation fault and application termination. The only exception is for dynamically allocated __shared__ variables as described in Section B.2. which can have adverse performance consequences as detailed in Section 5. For devices of compute capability 1. __shared__ or __constant__ variable can only be used in device code.3.2. pointers are supported without any restriction. only from the
host through host runtime functions (Sections 3. The address of a __device__ or __constant__ variable obtained through cudaGetSymbolAddress() as described in Section 3.
CUDA C Programming Guide Version 3. However in some cases the compiler might choose to place it in local memory. The address obtained by taking the address of a __device__.2. __shared__ and __constant__ variables cannot be defined as external using the extern keyword. pointers in code that is executed on the device are supported as long as the compiler is able to resolve whether they point to either the shared memory space or the global memory space. Dereferencing a pointer either to global or shared memory in code that is executed on the host or to host memory in code that is executed on the device results in an undefined behavior.0.3. otherwise they are restricted to only point to memory allocated or declared in the global memory space. __constant__ variables cannot be assigned to from the device.
An automatic variable declared in device code without any of these qualifiers generally resides in a register.3.
__shared__ and __constant__ variables have implied static storage.
C Language Extensions
B. __device__ and __constant__ variables are only allowed at file scope.4 can only be used in host code. For devices of compute capability 2.x.3.Appendix B.1.5
Restrictions
These qualifiers are not allowed on struct and union members.2.

ulonglong1 longlong2.4
Built-in Variables
Built-in variables specify the grid and block dimensions and the block and thread indices.4.1) and contains the block index within the grid.4.
B.1
107
.2) and contains the dimensions of the block.4
threadIdx
This variable is of type uint3 (see Section B.2
blockIdx
This variable is of type uint3 (see Section B.3.4. ulonglong2 float1 float2 float3 float4 double1 double2
8 16 4 8 4 16 8 16
B. any component left unspecified is initialized to 1.1.
B.2
dim3
This type is an integer vector type based on uint3 that is used to specify dimensions.
C Language Extensions
longlong1.1
gridDim
This variable is of type dim3 (see Section B. They are only valid within functions that are executed on the device.
CUDA C Programming Guide Version 3.3.4.Appendix B.2) and contains the dimensions of the grid.3.3.
B.3
blockDim
This variable is of type dim3 (see Section B.1) and contains the thread index within the block. When defining a variable of type dim3.
B.3.
B.

When all blocks are done.x-1.
C Language Extensions
B. each block atomically increments a counter to signal that it is done with computing and storing its partial sum (see Section B.5
Memory Fence Functions
void __threadfence_block().  It is not allowed to assign values to any of the built-in variables.1 for the definition of a warp).  All threads in the device for global memory accesses.
 void __threadfence_system().  Host threads for page-locked host memory accesses (see Section 3.
waits until all global and shared memory accesses made by the calling thread prior to __threadfence_block() are visible to all threads in the thread block.

In general. In order to determine which block is finished last.6.2. other threads may see the effects of these memory writes in a different order.1. If no fence is placed between storing the partial sum and incrementing the counter. __threadfence_system() is only supported by devices of compute capability 2. the last block done reads each of these partial sums from global memory and sums them to obtain the final result.1
.Appendix B.6
Restrictions
It is not allowed to take the address of any of the built-in variables.4. might reach gridDim.
waits until all global and shared memory accesses made by the calling thread prior to __threadfence_system() are visible to: All threads in the thread block for shared memory accesses.4. __threadfence(). One use case is when threads consume some data produced by other threads as illustrated by the following code sample of a kernel that computes the sum of an array of N numbers in one call. __threadfence_block(). when a thread issues a series of writes to memory in a particular order. The last block is the one that receives the counter value equal to gridDim.0. the counter might increment before the partial sum is stored and therefore.  All threads in the device for global memory accesses.

B.11 about atomic functions).
B.x-1 and let
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waits until all global and shared memory accesses made by the calling thread prior to __threadfence() are visible to: All threads in the thread block for shared memory accesses.3). and __threadfence_system() can be used to enforce some ordering. Each block first sums a subset of the array and stores the result in global memory.5
warpSize
This variable is of type int and contains the warp size in threads (see Section 4.
void __threadfence().

otherwise the code execution is likely to hang or produce unintended side effects.1
.1 contains a comprehensive list of the C/C++ standard library mathematical functions that are currently supported in device code.1.
is identical to __syncthreads() with the additional feature that it evaluates predicate for all threads of the block and returns the number of threads for which predicate evaluates to non-zero. For some of the functions of Section C. there are potential read-after-write. but faster version exists in the device runtime component.
int __syncthreads_and(int predicate). along with their respective error bounds. These intrinsic functions are listed in Section C.0 support three variations of __syncthreads() described below.
int __syncthreads_count(int predicate). When some threads within a block access the same addresses in shared or global memory. The compiler has an option (-use_fast_math) that forces each function in Table B-2 to compile to its intrinsic counterpart. along with their respective error bounds.
is identical to __syncthreads() with the additional feature that it evaluates predicate for all threads of the block and returns non-zero if and only if predicate evaluates to non-zero for any of them. write-after-read. it has the same name prefixed with __ (such as __sinf(x)).
int __syncthreads_or(int predicate).Appendix B.2. Functions Affected by –use_fast_math
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is identical to __syncthreads() with the additional feature that it evaluates predicate for all threads of the block and returns non-zero if and only if predicate evaluates to non-zero for all of them. Devices of compute capability 2. or write-after-write hazards for some of these memory accesses. a given function uses the C runtime implementation if available.
__syncthreads() is used to coordinate communication between the threads of
the same block. it may also cause some differences in special case handling.
B. In addition to reduce accuracy of the affected functions.7
Mathematical Functions
Section C.
__syncthreads() is allowed in conditional code but only if the conditional
evaluates identically across the entire thread block.
C Language Extensions waits until all threads in the thread block have reached this point and all global and shared memory accesses made by these threads prior to __syncthreads() are visible to all threads in the block. a less accurate. A more robust approach is to selectively replace mathematical function calls by calls to intrinsic functions only where it is merited by the performance gains and where changed properties such as reduced accuracy and different special case handling can be tolerated.
Table B-2.

and recording the result per thread provides a measure for each thread of the number of clock cycles taken by the device to completely execute the thread.
CUDA C Programming Guide Version 3.
C Language Extensions
B. boundaryMode = cudaBoundaryModeTrap). The former number is greater that the latter since threads are time sliced. int x. but not of the number of clock cycles the device actually spent executing thread instructions. boundaryMode = cudaBoundaryModeTrap).4
surf2Dwrite()
template<class Type> Type surf2Dwrite(surface<void.9. Sampling this counter at the beginning and at the end of a kernel. int y.
reads the CUDA array bound to surface reference surfRef using coordinates x and y.
B.
B. int x. Type data.1.1
113
. int x. 1> surfRef. 1> surfRef.
writes value data to the CUDA array bound to surface reference surfRef at coordinate x and y.9.9.
B. Type data. int y. 1> surfRef.
B.
reads the CUDA array bound to surface reference surfRef using coordinate x.1
surf1Dread()
template<class Type> Type surf1Dread(surface<void. boundaryMode = cudaBoundaryModeTrap).Appendix B. boundaryMode = cudaBoundaryModeTrap).
when executed in device code. 1> surfRef. taking the difference of the two samples. returns the value of a per-multiprocessor counter that is incremented every clock cycle.10
Time Function
clock_t clock().9.
writes value data to the CUDA array bound to surface reference surfRef at coordinate x.2
surf1Dwrite()
template<class Type> Type surf1Dwrite(surface<void.3
surf2Dread()
template<class Type> Type surf2Dread(surface<void. int x.

reads the 32-bit word old located at the address address in global or shared memory.2 and above.2
atomicSub()
int atomicSub(int* address. adds a number to it. which also work for single-precision floating-point numbers.1
.val).0. Atomic functions operating on mapped page-locked memory (Section 3. In other words. unsigned int val).1
B. int val). The floating-point version of atomicAdd() is only supported by devices of compute capability 2.
B. unsigned int atomicAdd(unsigned int* address.
C Language Extensions
B.11
Atomic Functions
An atomic function performs a read-modify-write atomic operation on one 32-bit or 64-bit word residing in global or shared memory. These three operations are performed in one atomic transaction. no other thread can access this address until the operation is complete. unsigned int val).11.
reads the 32-bit or 64-bit word old located at the address address in global or shared memory.11. The function returns old.
B.
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Arithmetic Functions
atomicAdd()
int atomicAdd(int* address.Appendix B. and stores the result back to memory at the same address. float atomicAdd(float* address. computes (old + val). The function returns old. atomicAdd() reads a 32-bit word at some address in global or shared memory.3) are not atomic from the point of view of the host or other devices.1 and above. unsigned int atomicSub(unsigned int* address. Atomic functions operating on shared memory and atomic functions operating on 64-bit words are only available for devices of compute capability 1. Atomic operations only work with signed and unsigned integers with the exception of atomicAdd() for devices of compute capability 2.6. unsigned long long int val).0 and atomicExch() for all devices. Atomic functions operating on 64-bit words in shared memory are only available for devices of compute capability 2. computes (old .1. unsigned long long int atomicAdd(unsigned long long int* address. and writes the result back to the same address.0 and above. int val).1. Atomic functions can only be used in device functions and are only available for devices of compute capability 1.1. float val). For example.

int val). unsigned int atomicExch(unsigned int* address.8
atomicCAS()
int atomicCAS(int* address. unsigned long long int val).
CUDA C Programming Guide Version 3. computes the minimum of old and val.11. unsigned int compare. These three operations are performed in one atomic transaction. These three operations are performed in one atomic transaction. These three operations are performed in one atomic transaction. These two operations are performed in one atomic transaction.
reads the 32-bit word old located at the address address in global or shared memory. float val).
reads the 32-bit word old located at the address address in global or shared memory.1. The function returns old. unsigned long long int atomicCAS(unsigned long long int* address. int val).Appendix B. The function returns old. The function returns old. unsigned int val).
B. and stores the result back to memory at the same address. computes ((old >= val) ? 0 : (old+1)). unsigned int atomicMax(unsigned int* address.4
atomicMin()
int atomicMin(int* address.
B.
B. unsigned int val).
reads the 32-bit word old located at the address address in global or shared memory.1.7
atomicDec()
unsigned int atomicDec(unsigned int* address.3
atomicExch()
int atomicExch(int* address. computes the maximum of old and val.
reads the 32-bit or 64-bit word old located at the address address in global or shared memory and stores val back to memory at the same address.
B. unsigned int val). and stores the result back to memory at the same address. int val). unsigned int atomicMin(unsigned int* address. unsigned int val). unsigned int atomicCAS(unsigned int* address.11. int compare. These three operations are performed in one atomic transaction.1.1.1.1. and stores the result back to memory at the same address. The function returns old.11.5
atomicMax()
int atomicMax(int* address.11. float atomicExch(float* address. computes (((old == 0) | (old > val)) ? val : (old-1)). unsigned int val).
reads the 32-bit word old located at the address address in global or shared memory.11. unsigned int val).11.
C Language Extensions
B. unsigned long long int atomicExch(unsigned long long int* address. and stores the result back to memory at the same address. The function returns old. int val).6
atomicInc()
unsigned int atomicInc(unsigned int* address.
B.1
115
.1.

2. unsigned int atomicAnd(unsigned int* address. unsigned int val).
reads the 32-bit word old located at the address address in global or shared memory.2. computes (old & val).2. computes (old == compare ? val : old). unsigned int atomicXor(unsigned int* address.
reads the 32-bit or 64-bit word old located at the address address in global or shared memory. and stores the result back to memory at the same address.1. computes (old | val).1
.12
Warp Vote Functions
Warp vote functions are only supported by devices of compute capability 1.
int __all(int predicate). These three operations are performed in one atomic transaction.11. computes (old ^ val). and stores the result back to memory at the same address. int val). The function returns old (Compare And Swap).11.1 for the definition of a warp).2
atomicOr()
int atomicOr(int* address.
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evaluates predicate for all threads of the warp and returns non-zero if and only if predicate evaluates to non-zero for all of them.Appendix B. The function returns old. The function returns old. int val).
B.11.1
Bitwise Functions
atomicAnd()
int atomicAnd(int* address. int val). These three operations are performed in one atomic transaction.2 and higher (see Section 4. These three operations are performed in one atomic transaction.
B.11.3
atomicXor()
int atomicXor(int* address. These three operations are performed in one atomic transaction.
int __any(int predicate).
reads the 32-bit word old located at the address address in global or shared memory. unsigned int val). and stores the result back to memory at the same address.2
B. and stores the result back to memory at the same address. unsigned int atomicOr(unsigned int* address.
reads the 32-bit word old located at the address address in global or shared memory.
C Language Extensions
unsigned long long int compare.
B. The function returns old. unsigned int val). unsigned long long int val).
B.

prints formatted output from a kernel to a host-side output stream.
void __prof_trigger(int counter). in the profiler. Multiple versions of the output string will then appear at the host stream.
int printf(const char *format[. using that thread‟s data as specified. Unlike the C-standard printf(). with substitutions made from the argument list wherever a format specifier is encountered. which returns the number of characters printed.
B.conf file (see the profiler manual for more details). arg. 7 for the first multiprocessor can be obtained via the CUDA profiler by listing prof_trigger_00. If an internal error occurs. If the format string is NULL. once for each thread which encountered the printf(). This function is only supported by devices of compute capability 2.
evaluates predicate for all threads of the warp and returns an integer whose Nth bit is set if and only if predicate evaluates to non-zero for the Nth thread of the warp.
increments by one per warp the per-multiprocessor hardware counter of index counter.13
Profiler Counter Function
Each multiprocessor has a set of sixteen hardware counters that an application can increment with a single instruction by calling the __prof_trigger() function.0. the string passed in as format is output to a stream on the host. In essence. -2 is returned. and in the context of the calling thread.]). . The value of counters 0. The in-kernel printf() function behaves in a similar way to the standard C-library printf() function.1
117
. …. The printf() command is executed as any other device-side function: per-thread.1.14
Formatted Output
Formatted output is only supported by devices of compute capability 2. Supported format specifiers are listed below. etc. and the user is referred to the host system‟s manual pages for a complete description of printf() behavior.
CUDA C Programming Guide Version 3.
C Language Extensions
evaluates predicate for all threads of the warp and returns non-zero if and only if predicate evaluates to non-zero for any of them.4 for an illustrative example).. 0 is returned. all launches are synchronous). prof_trigger_07. All counters are reset before each kernel call (note that when an application is run via the CUDA debugger or the CUDA profiler. prof_trigger_01. CUDA‟s printf() returns the number of arguments parsed.
B. …. Counters 8 to 15 are reserved and should not be used by applications.14. -1 is returned. this means that a straightforward call to printf() will be executed by every thread. From a multi-threaded kernel. It is up to the programmer to limit the output to a single thread if only a single output string is desired (see Section B.Appendix B.. 1. If no arguments follow the format string.0.
unsigned int __ballot(int predicate).

1
Format Specifiers
As for standard printf(). whether or not overall they form a valid format specifier. and is flushed at any host-side synchronisation point and at when the context is explicitly destroyed.1. Owing to the differing size of the long type on 64-bit Windows platforms (four bytes on 64-bit Windows platforms.14. eight bytes on other 64-bit platforms). size and type. The output buffer for printf() is not flushed automatically to the output stream.2
Limitations
Final formatting of the printf() output takes place on the host system. This means that the format string must be understood by the host-system‟s compiler and C library.14. if more output is produced during kernel execution than can fit in the buffer. but exact behavior will be host-O/S-dependent. format specifiers take the form: %[flags][width][. The printf() command can accept at most 32 arguments in addition to the format string. width. The output buffer for printf() is set to a fixed size before kernel launch (see below). In other words.14. Additional arguments beyond this will be ignored. Every effort has been made to ensure that the format specifiers supported by CUDA‟s printf function form a universal subset from the most common host compilers. a kernel which is compiled on a non-Windows 64-bit machine but then run on a win64 machine will see corrupted output for all format strings which include “%ld”. and the format specifier output as-is. This buffer is circular.

B.Appendix B. The effect of this is that output may be undefined if the program emits a format string which contains invalid combinations. precision. printf() will accept all combinations of valid flags and types.
C Language Extensions
B.1
118
.
CUDA C Programming Guide Version 3. This is because it cannot determine what will and will not be valid on the host system where the final output is formatted. older output is overwritten. “%hd” will be accepted and printf will expect a double-precision variable in the corresponding location in the argument list. but instead is flushed only when one of these actions is performed:

Kernel launch via <<<>>> or cuLaunch().1.precision][size]type The following fields are supported (see widely-available documentation for a complete description of all behaviors): Flags: „#‟ „ „ „0‟ „+‟ „-„  Width: „*‟ „0-9‟  Precision: „0-9‟  Size: „h‟ „l‟ „ll‟  Type: „%cdiouxXpeEfgGaAs‟ Note that CUDA‟s printf() will accept any combination of flag. As described in Section B. It is recommended that the compilation platform matches the execution platform to ensure safety.

The arguments to the execution configuration are evaluated before the actual function arguments and like the function arguments.1 for a description of streams). a function declared as
__global__ void Func(float* parameter).3. The execution configuration defines the dimension of the grid and blocks that will be used to execute the function on the device. minus the amount of shared memory required for static allocation. When using the runtime API (Section 3.15
Execution Configuration
Any call to a __global__ function must specify the execution configuration for that call.
B. Db. the execution configuration is specified through a series of driver function calls as detailed in Section 3. Ns. and execution configuration. Ns >>>(parameter). }
will output:
Hello thread 0.3.z must be equal to 1. Db is of type dim3 (see Section B.x).y equals the number of blocks being launched. such that Db.2) and specifies the dimension and size of each block. so that only a single line of output is seen.2. the if() statement limits which threads will call printf. f=1. Db.1
. functions arguments (for devices of compute capability 1. When using the driver API.2) and specifies the dimension and size of the grid.3.10. As an example.2). Dg.Appendix B. Ns is an optional argument which defaults to 0.  S is of type cudaStream_t and specifies the associated stream.
must be called like this:
Func<<< Dg.x * Db.3. where:

Dg is of type dim3 (see Section B.3. the execution configuration is specified by inserting an expression of the form <<< Dg.
C Language Extensions
cudaThreadExit().1. are currently passed via shared memory to the device.2345
Self-evidently. or if Ns is greater than the maximum amount of shared memory available on the device. S >>> between the function name and the parenthesized argument list.x * Dg.3. this dynamically allocated memory is used by any of the variables declared as an external array as mentioned in Section B.
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CUDA C Programming Guide Version 3.z equals the number of threads

per block.y * Db. The function call will fail if Dg or Db are greater than the maximum sizes allowed for the device as specified in Appendix G. as well as the associated stream (see Section 3. such that Dg.  Ns is of type size_t and specifies the number of bytes in shared memory that is dynamically allocated per block for this call in addition to the statically allocated memory. S is an optional argument which defaults to 0.

 If the initial register usage is lower than L.. Therefore.e. If launch bounds are specified.) { . the compiler uses heuristics to minimize register usage while keeping register spilling (see Section 5. it compiles to the . the compiler may increase register usage as high as L to reduce the number of instructions and better hide single thread instruction latency. the compiler first derives from them the upper limit L on the number of registers the kernel should use to ensure that minBlocksPerMultiprocessor blocks (or a single block if minBlocksPerMultiprocessor is not specified) of maxThreadsPerBlock threads can reside on the multiprocessor (see Section 4.3) and then applies similar heuristics as when no launch bounds are specified.

CUDA C Programming Guide Version 3.  If both minBlocksPerMultiprocessor and maxThreadsPerBlock are specified. minBlocksPerMultiprocessor is optional and specifies the desired

minimum number of resident blocks per multiprocessor.3.2 for the relationship between the number of registers used by a kernel and the number of registers allocated per block). the more threads and thread blocks are likely to reside on a multiprocessor. the compiler uses maxThreadsPerBlock to determine the register usage thresholds for the transitions between n and n+1 resident blocks (i..1
121
. when using one less register makes room for an additional resident block as in the example of Section 5. the fewer registers a kernel uses.2. it compiles to the .maxntid PTX directive. An application can optionally aid these heuristics by providing additional information to the compiler in the form of launch bounds that are specified using the __launch_bounds__() qualifier in the definition of a __global__ function:
__global__ void __launch_bounds__(maxThreadsPerBlock.  If maxThreadsPerBlock is specified and minBlocksPerMultiprocessor is not.2..minnctapersm PTX directive. the compiler reduces it further until it becomes less or equal to L. usually at the expense of more local memory usage and/or higher number of instructions.. A kernel will fail to launch if it is executed with more threads per block than its launch bound maxThreadsPerBlock. The compiler then optimizes register usage in the following way: If the initial register usage is higher than L. which can improve performance. minBlocksPerMultiprocessor) MyKernel(.2.Appendix B.2) and instruction count to a minimum.
C Language Extensions
B.3. } 
maxThreadsPerBlock specifies the maximum number of threads per block with which the application will ever launch MyKernel().16
Launch Bounds
As discussed in detail in Section 5.1.

.. Instead the number of threads per block should be determined:

Either at compile time using a macro that does not depend on __CUDA_ARCH__.
This will not work however since __CUDA_ARCH__ is undefined in host code as mentioned in Section 3.4.)..Appendix B. The sample code below shows how this is typically handled in device code using the __CUDA_ARCH__ macro introduced in Section 3... it is tempting to use MY_KERNEL_MAX_THREADS as the number of threads per block in the execution configuration:
// Host code MyKernel<<<blocksPerGrid. for example
// Host code MyKernel<<<blocksPerGrid.)..
#define THREADS_PER_BLOCK #if __CUDA_ARCH__ >= 200 #define MY_KERNEL_MAX_THREADS #define MY_KERNEL_MIN_BLOCKS #else #define MY_KERNEL_MAX_THREADS #define MY_KERNEL_MIN_BLOCKS #endif 256 (2 * THREADS_PER_BLOCK) 3 THREADS_PER_BLOCK 2
// Device code __global__ void __launch_bounds__(MY_KERNEL_MAX_THREADS. Register usage can also be controlled for all __global__ functions in a file using the -maxrregcount compiler option. The value of -maxrregcount is ignored for functions with launch bounds.. int threadsPerBlock = (deviceProp.) { . device)..1. The number of resident blocks can be derived from the occupancy reported by the CUDA profiler (see Section 5..
C Language Extensions Optimal launch bounds for a given kernel will usually differ across major architecture revisions.2.3 for a definition of occupancy).major >= 2 ? 2 * THREADS_PER_BLOCK : THREADS_PER_BLOCK).
Register usage is reported by the --ptxas-options=-v compiler option.4.1
. MY_KERNEL_MIN_BLOCKS) MyKernel(. MY_KERNEL_MAX_THREADS>>>(. so MyKernel will launch with 256 threads per block even when __CUDA_ARCH__ is greater or equal to 200.1.

Or at runtime based on the compute capability
// Host code cudaGetDeviceProperties(&deviceProp. MyKernel<<<blocksPerGrid.. threadsPerBlock>>>(.
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CUDA C Programming Guide Version 3.1. THREADS_PER_BLOCK>>>(.). }
In the common case where MyKernel is invoked with the maximum number of threads per block (specified as the first parameter of __launch_bounds__()).

float log(float) (3) float <func-name>f(float).g.2. so that in general. These error bounds also apply when the function is executed on the host in the case where the host does not supply the function.1
123
.1.
CUDA C Programming Guide Version 3. on the device. whereas rintf() maps to a single instruction.
C. in particular. ceilf(). FMAD truncates the intermediate result of the multiplication as mentioned in Section G. float logf(float) This means. The reason is that roundf() maps to an 8-instruction sequence on the device. with the result being a single-precision floating-point number is rintf(). so they are not guaranteed bounds.1
Single-Precision Floating-Point Functions
Addition and multiplication are IEEE-compliant.g.1 can be used in both host and device code whereas functions from Section C.5 ulp.1
Standard Functions
This section lists all the mathematical standard library functions supported in device code. so have a maximum error of 0. the compiler often combines them into a single multiply-add instruction (FMAD) and for devices of compute capability 1. e. not roundf(). there are three prototypes for a given function <func-name>: (1) double <func-name>(double).Appendix C. They are generated from extensive but not exhaustive tests.g. The recommended way to round a single-precision floating-point operand to an integer. double log(double) (2) float <func-name>(float). e.
C. This combination can be avoided by using the __fadd_rn() and __fmul_rn() intrinsic functions (see Section C.2). It also specifies the error bounds of each function when executed on the device. that passing a float argument always results in a float result (variants (2) and (3) above). e. truncf(). and floorf() each map to a single instruction as well. However. Note that floating-point functions are overloaded. Mathematical Functions
Functions from Section C.2 can only be used in device code.x.

leaving the value unchanged.2
Intrinsic Functions
This section lists the intrinsic functions that are only supported in device code. type casting functions simply perform a type cast on the argument.1.y) fmin(x. Unlike type conversion functions (such as __int2float_rn) that convert from one type to another. The accuracy of floating-point division varies depending on the compute capability of the device and whether the code is compiled with -prec-div=false or -prec-div=true.1.
Mathematical Functions
Function isfinite(x) copysign(x. but faster versions of some of the functions of Section C.3
Integer Functions
Integer min(x. For devices of compute capability 1.x or for devices of compute capability 2.
C. __float_as_int(1.0 when the code is compiled with -prec-div=false. additions and multiplications generated from the '*' and '+' operators will frequently be combined into FMADs.Appendix C.y) and max(x. Functions suffixed with _rz operate using the round-towards-zero rounding mode.2. they have the same name prefixed with __ (such as __sinf(x)).y) fabs(x) nan(cptr) nextafter(x.y)
Maximum ulp error
N/A N/A N/A N/A N/A N/A N/A
C. __int_as_float(0xC0000000) is equal to -2. By contrast.0f) is equal to 0x3f800000. Functions suffixed with _rd operate using the round-down (to negative infinity) rounding mode. For example.y) are supported and map to a single instruction on the device.y) fmax(x. both
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Single-Precision Floating-Point Functions
__fadd_rn() and __fmul_rn() map to addition and multiplication operations
that the compiler never merges into FMADs.
C.1. Functions suffixed with _ru operate using the round-up (to positive infinity) rounding mode. Functions suffixed with _rn operate using the round-to-nearest-even rounding mode. Among these functions are the less accurate.1
.

rz. 2].y) have the same accuracy. IEEE-compliant. and larger otherwise. 2 + floor(abs(2.rd](x.
Single-Precision Floating-Point Intrinsic Functions Supported by the CUDA Runtime Library with Respective Error Bounds
Error bounds
IEEE-compliant. For y in [2-126.rz. For devices of compute capability 2. the maximum absolute error is 2-22. __fdividef(x. the maximum absolute error is 2-21.rd](x)) converts single-precision floating-point parameter x to 64-bit signed (respectively unsigned) integer with specified IEEE-
754 rounding modes. The maximum ulp error is The maximum ulp error is
Function __fadd_[rn.rd](x) (respectively __float2ull_[rn. the maximum ulp error is 2.
__saturate(x) returns 0 if x is less than 0.1. the maximum absolute error is 2-21.y) __fmul_[rn.rd](x.95 * x)).41. IEEE-compliant..rd](x) __fsqrt_[rn.5. if x is infinity. the maximum ulp error is 3.5.19.1.z) __frcp_[rn.ru.
CUDA C Programming Guide Version 3.Appendix C.cptr) __tanf(x) __powf(x. 2126]. __fdividef(x.1
129
. and larger otherwise.1. IEEE-compliant.5.y) delivers a NaN (as a result of multiplying infinity by zero). otherwise.y) __fmaf_[rn.rz.0 when the code is compiled with -prec-div=true.rd](x.y) __fdividef(x. IEEE-compliant. the maximum absolute error is 2-24.ru.y) __expf(x) __exp10f(x) __logf(x)
2 + floor(abs(1. y)
__sinf(x) * (1 / __cosf(x)). 2]. Also.
Mathematical Functions
the regular division “/” operator and __fdividef(x.ru.16 * x)).ru.
__float2ll_[rn.ru.
For x in [0.sptr. 2].rz. ].ru. IEEE-compliant. and x
otherwise.y.rd](x) __fdiv_[rn. but for 2126 < y < 2128. For x in [. Derived from its implementation as Derived from its implementation as exp2f(y * __log2f(x)).ru. the maximum ulp error is 2. For x in [.rz. whereas the “/” operator delivers the correct result to within the accuracy stated in Table C-3.y) delivers a result of zero. otherwise. for 2126 < y < 2128. For x in [0. 1 if x is more than 1. For x in [0. while the “/” operator returns infinity. the maximum absolute error is 2-21. the maximum ulp error is 3.
Table C-3.
__log2f(x) __log10f(x) __sinf(x) __cosf(x) __sincosf(x.ru. the “/” operator is IEEE compliant as mentioned in Section C. otherwise.41.. Same as sinf(x) and cosf(x). ].rz.rz.rz.rd](x.

If x is 0. The least significant bit is position 1.ru. between 0 and 64 inclusive. The 8 most significant bits of x or y are ignored. __ffs() returns 0. __[u]mulhi(x.3
Integer Functions
__[u]mul24(x.rd](x) __dsqrt_[rn.
Mathematical Functions
Requires compute capability ≥ 2. __clzll(x) returns the number.s) returns. The input bytes are indexed as
follows:
input[0] = x<0:7> input[2] = x<16:23> input[4] = y<0:7>
CUDA C Programming Guide Version 3.1.rz. bit 31) of integer parameter x. __popcll(x) returns the number of bits that are set to 1 in the binary representation of 64-bit integer parameter x.y) computes the product of the 64-bit integer parameters x and y and delivers the 64 most significant bits of the 128-bit result.
__drcp_[rn.y) computes the product of the integer parameters x and y and
delivers the 32 most significant bits of the 64-bit result.rz. __ffsll(x) returns the position of the first (least significant) bit set in 64-bit integer parameter x. of consecutive zero bits starting at the most significant bit (i.e. __clz(x) returns the number. __ffsll() returns 0.e. bit 63) of 64-bit integer parameter x.
__[u]mul64hi(x. __ffs(x) returns the position of the first (least significant) bit set in integer parameter x. four bytes from eight input bytes provided in the two input integers x and y. i.Appendix C.y) computes the product of the 24 least significant bits of the integer parameters x and y and delivers the 32 least significant bits of the result. Requires compute capability ≥ 2 IEEE-compliant. bit N of the result corresponds to bit 63-N of x. as a 32-bit integer r. bit N of the result corresponds to bit 31-N of x. The least significant bit is position 1. of consecutive zero bits starting at the most significant bit (i.rd](x) __double2float_[ru. __popc(x) returns the number of bits that are set to 1 in the binary representation of 32-bit integer parameter x. between 0 and 32 inclusive. __[u]sad(x.z) (Sum of Absolute Difference) returns the sum of integer parameter z and the absolute value of the difference between integer parameters x and y.ru.y. Note that this is identical to the Linux function ffs.y. Note that this is identical to the Linux function ffsll. __byte_perm(x. __brevll(x) reverses the bits of 64-bit unsigned long long parameter x.2. i.e.1
input[1] = x<8:15> input[3] = x<24:31> input[5] = y<8:15>
131
. __brev(x) reverses the bits of 32-bit unsigned integer parameter x. Requires compute capability ≥ 2 N/A
C.rd](x)
IEEE-compliant.e. If x is 0.

Example: The following is valid CUDA code:
__device__ void f(float x) {
CUDA C Programming Guide Version 3.1
133
. like the lack of support for recursion. That means that the two functions either consume a different number of parameters or parameters of different types. see below) overloading. still apply. polymorphism is the ability to define that functions or operators behave differently in different contexts. Because of implicit typecasting. When either of the multiple functions gets invoked the compiler resolves to the function‟s implementation that matches the function signature.0 These C++ constructs are implemented as specified in “The C++ Programming Langue” reference. device. It is valid to use any of these constructs in . Any restrictions detailed in previous parts of this programming guide.1
Polymorphism
Generally.cu CUDA files for host. a compiler may encounter multiple potential matches for a function invocation and in that case the matching rules as described in the C++ Language Standard apply. In practice this means that the compiler will pick the closest match in case of multiple potential matches. and kernel (__global__) functions. In practical terms. This is also referred to as function (and operator.Appendix D.
D.

The following subsections provide examples of the various constructs. C++ Language Constructs
CUDA supports the following C++ language constructs for device code: Polymorphism  Default Parameters  Operator Overloading  Namespaces  Function Templates  Classes for devices of compute capability 2. this means that it is permissible to define two different functions within the same scope (namespace) as long as they have a distinguishable function signature.

0f) { // do something with x }
Kernel or other device functions can now invoke this version of f in one of two ways:
f(). b.
Default parameters can only be given for the last n parameters of a function.3
Operator Overloading
Operator overloading allows programmers to define operators for new data-types.
134
CUDA C Programming Guide Version 3. // or float x = /* some value */. Examples of overloadable operators in C++ are: +. f(x).
Example: The following is valid CUDA code.Appendix D. const uchar4 & b) { uchar4 r.. /.x.2
Default Parameters
With support for polymorphism as described in the previous subsection and the function signature matching rules in place it becomes possible to provide support for default values for function parameters..1
.
D.x + b. . implementing the + operation
between two uchar4 vectors:
__device__ uchar4 operator+ (const uchar4 & a. -. a = b = /* some initial value */.1. r. &.
Example:
__device__ void f(float x = 0. *. c. +=.
C++ Language Constructs
// do something with x } __device__ void f(int i) { // do something with i } __device__ void f(double x. }
This new operator can now be used like this:
uchar4 a. etc. return r.x = a. []. double y) { // do something with x and y }
D.

Explicit instantiation.1.1
135
.} }
The functions can now be used anywhere via fully qualified names:
nvidia::f(0.
All the symbols in a namespace can be imported into another namespace (scope) like this:
using namespace nvidia.
C++ Language Constructs
c = a + b. which commonly occurs when using multiple function libraries from different sources.} } namespace other { __device__ void f(float x) { /* do something with x */ .Appendix D.
CUDA C Programming Guide Version 3.5f).
Example: The following code defines two functions “f()” in two separate
namespaces (“nvidia” and “other”):
namespace nvidia { __device__ void f(float x) { /* do something with x */ . All the symbols inside a namespace can be used within this namespaces without additional syntax.4
Namespaces
Namespaces in C++ allow for the creation of a hierarchy of scopes of visibility. The use of namespaces can be used to solve the problem of name-clashes (two different symbols using identical names). f(0.5
Function Templates
Function templates are a form of meta-programming that allows writing a generic function in a data-type independent fashion.
f() can be invoked in two ways:
int x = 1.
D. CUDA supports function templates to the full extent of the C++ standard.  Template specialization.
 
Example:
template <T> __device__ bool f(T x) { return /* some clever code that turns x into a bool here */ }
This function will convert x of any data-type to a bool as long as the code in the function‟s body can be compiled for the actually type (T) of the variable x.
D. including the following concepts: Implicit template parameter deduction.5f).

C++ Language Constructs
bool result = f(x). etc. all other types will be caught by the more general template and return false.6
Classes
Code compiled for devices with compute capability 2.1
136
.

D. There are two common use cases for classes without virtual member functions: Small-data aggregations. } CUDA C Programming Guide Version 3.  Functor classes.0 and greater may make use of C++ classes. E.g. A workaround for this restriction is the use of functor classes (see code sample below). b_(0).5). vectors.
D. a_(0) { . data types like pixels (r. The use of functors is necessitated by the fact that devicefunction pointers are not supported and thus it is not possible to pass functions as template parameters. } template <> __device__ bool f<int>(T x) { return true. g_(0).1
Example 1 Pixel Data Type
The following is an example of a data type for RGBA pixels with 8 bit per channel depth:
class PixelRGBA { public: __device__ PixelRGBA(): r_(0). }
In this case the implementation for T representing the int type are specialized to return true.6. b. 2D and 3D points. as long as none of the member functions are virtual (this restriction will be removed in some future release).Appendix D.
Function templates may be specialized:
template <T> __device__ bool f(T x) { return false. a).1. In this case the compiler would deduce T to be int and instantiate f<int>(x). The complete set of matching rules (for implicitly deducing template parameters) and matching polymorphous functions apply as specified in the C++ standard.
This first type of invocation relies on the compiler‟s ability to implicitly deduce the correct function type for T. g. The second type of invoking the template function is via explicit instantiation like this:
bool result = f<double>(0.

0. the compiler will not honor the __noinline__ qualifier for functions with pointer parameters and for functions with large parameter lists.1
__noinline__ and __forceinline__
When compiling code for devices of compute capability 1. for example).
E. the compiler unrolls small loops with a known trip count. to ensure that there will only be n iterations if n is less than 5. i < n. For devices of compute capability 2.x. For devices of compute capability 1. It is optionally followed by a number that specifies how many times the loop must be unrolled.2
#pragma unroll
By default.Appendix E. in this code sample:
#pragma unroll 5 for (int i = 0. a __device__ function is only inlined when deemed appropriate by the compiler. When compiling code for devices of compute capability 2.
CUDA C Programming Guide Version 3. The __noinline__ function qualifier can be used as a hint for the compiler not to inline the function if possible.
#pragma unroll 1 will prevent the compiler from ever unrolling a loop. The __forceinline__ function qualifier can be used to force the compiler to inline the function. The compiler will also insert code to ensure correctness (in the example above.0.x.1
139
. NVCC Specifics
E. It must be placed immediately before the loop and only applies to that loop. a __device__ function is always inlined by default. the compiler will always honor the __noinline__ qualifier. The function body must still be in the same file where it is called. For example. The #pragma unroll directive however can be used to control unrolling of any given loop. ++i)
the loop will be unrolled 5 times. It is up to the programmer to make sure that the specified unroll number gives the best performance.

the compiler cannot load a[0] and b[0] into registers.. say. This means that to guarantee functional correctness. multiply them. otherwise it is not unrolled at all. By making a. b. because the results would differ from the abstract execution model if. }
In C-type languages.Appendix E. const float* __restrict__ b. float* __restrict__ c) { float t0 = a[0].
Restricted pointers were introduced in C99 to alleviate the aliasing problem that exists in C-type languages. So the compiler cannot take advantage of the common sub-expression. c[2] = a[0] * b[0] * a[1]. the loop is completely unrolled if its trip count is constant. where use of restricted pointer can help the compiler to reduce the number of instructions:
void foo(const float* a. while retaining functionality identical with the abstract execution model:
void foo(const float* __restrict__ a. and c may be aliased.1.
E. c[3] = a[0] * a[1]. const float* __restrict__ b. the pointers a. float* c) { c[0] = a[0] * b[0].1
. c[4] = a[0] * b[0].
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CUDA C Programming Guide Version 3. and c restricted pointers. const float* b.
Note that all pointer arguments need to be made restricted for the compiler optimizer to derive any benefit. b. and store the result to both c[0] and c[1]. float* __restrict__ c). so any write through c could modify elements of a or b.. and which inhibits all kind of optimization from code reordering to common sub-expression elimination. the programmer asserts to the compiler that the pointers are in fact not aliased. c[5] = b[0]. Likewise. . Here is an example subject to the aliasing issue. With the __restrict keywords added. a[0] is really the same location as c[0]. This changes the function prototype as follows:
void foo(const float* __restrict__ a. the compiler can now reorder and do common sub-expression elimination at will. which in this case means writes through c would never overwrite elements of a or b. c[1] = a[0] * b[0].3
__restrict__
nvcc supports restricted pointers via the __restrict__ keyword. the compiler cannot just reorder the computation of c[4] into the proximity of the computation of c[0] and c[1] because the preceding write to c[3] could change the inputs to the computation of c[4].
NVCC Specifics If no number is specified after #pragma unroll.

N M texels for a two-dimensional texture. x .2. y . and z are derived from ˆ ˆ ˆ ˆ ˆ the normalized texture coordinates x . y My .
x
is replaced by 0 if x 0 and 1
1
N
if 1 x . y . only the clamp addressing mode is supported and x is replaced by 0 if x 0 and N 1 if N x . and z as such: x Nx . x is replaced by frac (x) . where frac ( x) x floor( x) and floor(x) is the largest integer not greater than x .Appendix F. If x is non-normalized. and z .
CUDA C Programming Guide Version 3.
In the remaining of the appendix. or N M L texels for a three-dimensional texture. and z are the non-normalized texture coordinates remapped to T ‟s valid addressing range. Texture Fetching
This appendix gives the formula used to compute the value returned by the texture functions of Section B.
In wrap addressing mode. y .8 depending on the various attributes of the texture reference (see Section 3. x . A texture coordinate must fall within T ‟s valid addressing range before it can be used to address T .4). The texture bound to the texture reference is represented as an array T of N texels for a one-dimensional texture. y . The addressing mode specifies how an out-of-range texture coordinate x is remapped to the valid range. and ˆ z Lz . If x is normalized:
 
In clamp addressing mode. It is fetched using texture coordinates x .1
143
.

Appendix G. height.or y-dimension of a grid of thread blocks Maximum number of threads per block Maximum x.3
2.1
1.2
65535
1.0
1024 1024
65536 x 32768
65536 x 65536
2048 x 2048 x 2048 128 8 2 million
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Compute Capabilities
Compute Capability Technical Specifications
Maximum x.1
. and depth for a 3D texture reference bound to linear memory or a CUDA array Maximum number of textures that can be bound to a kernel Maximum number of surfaces that can be bound to a kernel Maximum number of instructions per kernel 24 768 8K 16 KB 16 16 KB 64 KB 8 KB Device dependent. between 6 KB and 8 KB 8192 227 32768 512 512 64 32 8 32 1024 16 K 48 1536 32 K 48 KB 32 512 KB
1.0
1.or y-dimension of a block Maximum z-dimension of a block Warp size Maximum number of resident blocks per multiprocessor Maximum number of resident warps per multiprocessor Maximum number of resident threads per multiprocessor Number of 32-bit registers per multiprocessor Maximum amount of shared memory per multiprocessor Number of shared memory banks Amount of local memory per thread Constant memory size Cache working set per multiprocessor for constant memory Cache working set per multiprocessor for texture memory Maximum width for a 1D texture or surface reference bound to a CUDA array Maximum width for a 1D texture reference bound to linear memory Maximum width and height for a 2D texture reference bound to linear memory or for a 2D texture or surface reference bound to a CUDA array Maximum width.1.

__fadd_r[u. IEEE-compliant software (and therefore slower) implementations are provided through the following intrinsics (c. The result of a single-precision floating-point operation involving one or more input NaNs is the quiet NaN of bit pattern 0x7fffffff. floating-point arithmetic and comparison instructions convert denormalized operands to zero prior to the floating-point operation.d}(float.  Underflowed results are flushed to zero.u.
Compute Capabilities
G. Section C.f.d](float): single-precision square root with IEEE rounding modes.1):     
__fmaf_r{n. __fdiv_r[n.Appendix G.e.
CUDA C Programming Guide Version 3.d](float. For single-precision floating-point numbers on devices of compute capability 1. most of the operations support multiple IEEE rounding modes.z. they are not signaling and are handled as quiet. float): single-precision
fused multiply-add with IEEE rounding modes. float): single-precision addition with IEEE directed rounding.  Division is implemented via the reciprocal in a non-standard-compliant way.  Square root is implemented via the reciprocal square root in a nonstandard-compliant way.z.u. only round-to-nearest-even and round-towards-zero are supported via static rounding modes.z.2. float. which truncates (i. There is no mechanism for detecting that a floating-point exception has occurred and all operations behave as if the IEEE-754 exceptions are always masked. and deliver the masked response as defined by IEEE-754 if there is an exceptional event. float): single-precision division with IEEE rounding modes. Double-precision floating-point absolute value and negation are not compliant with IEEE-754 with respect to NaNs.d](float): single-precision reciprocal with IEEE rounding modes. __frcp_r[n.  Some instructions are not IEEE-compliant:  Addition and multiplication are often combined into a single multiplyadd instruction (FMAD). while SNaN encodings are supported. To mitigate the impact of these restrictions.d](float. directed rounding towards +/.infinity is not supported. without rounding) the intermediate mantissa of the multiplication. these are passed through unchanged.z. __fsqrt_r[n.2
Floating-Point Standard
All compute devices follow the IEEE 754-2008 standard for binary floating-point arithmetic with the following deviations:


  
There is no dynamically configurable rounding mode.  For addition and multiplication.1
149
. however.u.x:  Denormalized numbers are not supported. for the same reason. exposed via device intrinsics.1.u.

the switch from FMAD to FFMA can cause slight changes in numeric results and can in rare circumstances lead to slighty larger error in final results. FFMA. i. but not the other. As mentioned above.2 and lower. -prec-div=true. devices of compute capability 1. the behavior is to clamp to the end of the supported range. and -prec-sqrt=true to ensure IEEE compliance (this is the default setting. is an IEEE-754(2008) compliant fused multiply-add instruction. float): single-precision multiplication
with IEEE directed rounding. and square root. so the full-width product is being used in the addition and a single rounding occurs during generation of the final result. This is unlike the x86 architecture behavior.x:  Round-to-nearest-even is the only supported IEEE rounding mode for reciprocal. While FFMA in general has superior numerical properties compared to FMAD. see the nvcc user manual for description of these compilation flags).
Compute Capabilities 

__fmul_r[u. or fmax() is NaN. code compiled with -ftz=true.e.Appendix G. For devices of compute capability 2. code must be compiled with -ftz=false. and -prec-sqrt=false comes closest to the code generated for devices of compute capability 1.x.1
. each double variable is converted to single-precision floating-point format (but retains its size of 64 bits) and doubleprecision floating-point arithmetic gets demoted to single-precision floating-point arithmetic.  FFMA for single precision on devices of compute capability 2.x. fmaxf().1.
G.0 and higher.x
Architecture
For devices of compute capability 1. When compiling for devices without native double-precision floating-point support. division.x. Addition and multiplication are often combined into a single multiply-add instruction: FMAD for single precision on devices of compute capability 1. FMAD truncates the mantissa prior to use it in the addition.3.3
G. on the other hand. the result is the non-NaN parameter. a multiprocessor consists of:

8 CUDA cores for integer and single-precision floating-point arithmetic operations.
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Compute Capability 1. For compute devices. fmin(). The conversion of a floating-point value to an integer value in the case where the floating-point value falls outside the range of the integer format is left undefined by IEEE-754.

In accordance to the IEEE-754R standard. -prec-div=false.0. if one of the input parameters to fminf().d](float. For double-precision floating-point numbers on devices of compute capability 1.

Appendix G. the warp scheduler must therefore issue the instruction over:

4 clock cycles for an integer or single-precision floating-point arithmetic instruction.3.  8. all 16 words must lie in the same 64-byte segment. Figure G-1 shows some examples of global memory accesses and corresponding memory transactions based on compute capability.2
Global Memory
A global memory request for a warp is split into two memory requests. 8. which resides in device memory.4.1
151
. one for each half-warp.0 and 1.3.1
To coalesce.2 describe how the memory accesses of threads within a half-warp are coalesced into one or more memory transactions depending on the compute capability of the device.
Compute Capabilities
1 double-precision floating-point unit for double-precision floating-point arithmetic operations. Each TPC has a read-only texture cache that is shared by all multiprocessors and speeds up reads from the texture memory space.

The local and global memory spaces reside in device memory and are not cached.  If this size is:  4. The resulting memory transactions are serviced at the throughput of device memory.  16 clock cycles for a single-precision floating-point transcendental instruction.3. that are issued independently.2.1. Sections G.2. To execute an instruction for all threads of a warp. A multiprocessor also has a read-only constant cache that is shared by all functional units and speeds up reads from the constant memory space. which resides in device memory.0 and 1. or 16 bytes. Each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering mentioned in Section 3.

CUDA C Programming Guide Version 3.2.

Multiprocessors are grouped into Texture Processor Clusters (TPCs).2.1 and G.3.3.1.
G. The number of multiprocessors per TPC is: 2 for devices of compute capabilities 1. the memory request for a half-warp must satisfy the following conditions: The size of the words accessed by the threads must be 4.  2 special function units for single-precision floating-point transcendental functions (these units can also handle single-precision floating-point multiplications).  1 warp scheduler.2 and 1.
G.1
Devices of Compute Capability 1.  3 for devices of compute capabilities 1. all 16 words must lie in the same 128-byte segment.  32 clock cycles for a double-precision floating-point arithmetic instruction.

the first 8 words must lie in the same 128-byte segment and the last 8 words in the following 128-byte segment.2
Devices of Compute Capability 1. interleaved.1
.  128 bytes for 4-.and 16-byte words. If the half-warp meets these requirements.  If the transaction size is 64 bytes (originally or after reduction from 128 bytes) and only the lower or upper half is used.2.Appendix G. 8.  64 bytes for 2-byte words.1. a 64-byte memory transaction. More precisely.3. reduce the transaction size to 64 bytes.
Compute Capabilities  16.0 and 1.2 and 1. or 16. Find all other active threads whose requested address lies in the same segment. 16 separate 32-byte memory transactions are issued. including the same words. one for each half-warp. Reduce the transaction size.3
Shared Memory
Shared memory has 16 banks that are organized such that successive 32-bit words are assigned to successive banks.e. Carry out the transaction and mark the serviced threads as inactive.
G.3. the following protocol is used to determine the memory transactions necessary to service all threads in a half-warp:

 
 
Find the memory segment that contains the address requested by the lowest numbered active thread. Repeat until all threads in the half-warp are serviced. i.  Threads must access the words in sequence: The kth thread in the half-warp must access the kth word. i. A shared memory request for a warp is split into two memory requests. respectively. Each bank has a bandwidth of 32 bits per two clock cycles. 8.e. Coalescing is achieved even if the warp is divergent. if possible:  If the transaction size is 128 bytes and only the lower or upper half is used. If the half-warp does not meet these requirements.
G. reduce the transaction size to 32 bytes.
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CUDA C Programming Guide Version 3. This is in contrast with devices of compute capabilities 1.1 where threads need to access words in sequence and coalescing only happens if the half-warp addresses a single segment. and a single memory transaction for each segment addressed by the half-warp is issued. or two 128-byte memory transactions are issued if the size of the words accessed by the threads is 4. a 128-byte memory transaction. The segment size depends on the size of the words accessed by the threads:  32 bytes for 1-byte words.3
Threads can access any words in any order. that are issued independently. there can be no bank conflict between a thread belonging to the first half of a warp and a thread belonging to the second half of the same warp. there are some inactive threads that do not actually access memory. As a consequence.

char data = shared[BaseIndex + tid].e. there will be no bank conflict only if half the warp size (i. 16) is less than or equal to 16/d.
G.
In this case.
Compute Capabilities
If a non-atomic instruction executed by a warp writes to the same location in shared memory for more than one of the threads of the warp.2
32-Bit Broadcast Access
Shared memory features a broadcast mechanism whereby a 32-bit word can be read and broadcast to several threads simultaneously when servicing one memory read request. For example.e. at each step. Figure G-3 shows some examples of memory read accesses that involve the broadcast mechanism.e. float data = shared[BaseIndex + s * tid]. equivalently.0.  Include in the subset:  All addresses that are within the broadcast word.
G. s is odd. As a consequence. a memory read request made of several addresses is serviced in several steps over time by servicing one conflict-free subset of these addresses per step until all addresses have been serviced. The same examples apply for devices of compute capability 1.1
153
.3. the subset is built from the remaining addresses that have yet to be serviced using the following procedure: Select one of the words pointed to by the remaining addresses as the broadcast word. that is only if d is equal to 1. only one thread per halfwarp performs a write and which thread performs the final write is undefined. The same examples apply for devices of compute capability 1. 16) or.3. whenever n is a multiple of 16/d where d is the greatest common divisor of 16 and s. Which word is selected as the broadcast word and which address is picked up for each bank at each cycle are unspecified.1. but with 16 banks instead of 32.3.Appendix G.. More precisely.

A common conflict-free case is when all threads of a half-warp read from an address within the same 32-bit word. there are bank conflicts if an array of char is accessed the following way:
__shared__ char shared[32].3.
CUDA C Programming Guide Version 3. i. threads tid and tid+n access the same bank whenever s*n is a multiple of the number of banks (i.3
8-Bit and 16-Bit Access
8-bit and 16-bit accesses typically generate bank conflicts. Figure G-2 shows some examples of strided access for devices of compute capability 2.3.x.  One address for each bank (other than the broadcasting bank) pointed to by the remaining addresses.1
32-Bit Strided Access
A common access pattern is for each thread to access a 32-bit word from an array indexed by the thread ID tid and with some stride s:
__shared__ float shared[32].x. but with 16 banks instead of 32. This reduces the number of bank conflicts when several threads read from an address within the same 32-bit word.
G.3.

struct type data = shared[BaseIndex + tid].
as the memory request is compiled into two separate 32-bit requests with a stride of two.4
Larger Than 32-Bit Access
Accesses that are larger than 32-bit per thread are split into 32-bit accesses that typically generate bank conflicts.
since each member is accessed with an even stride of two 32-bit words.3. y.Appendix G.
Compute Capabilities because shared[0]. One way to avoid bank conflicts in this case is two split the double operands like in the following sample code:
__shared__ int shared_lo[32]. double dataIn.
since each member is accessed with an odd stride of three 32-bit words. shared_hi[BaseIndex + tid] = __double2hiint(dataIn).
This might not always improve performance however and does perform worse on devices of compute capabilities 2. there are 2-way bank conflicts for arrays of doubles accessed as follows:
__shared__ double shared[32]. shared_lo[BaseIndex + tid] = __double2loint(dataIn).
G. shared_lo[BaseIndex + tid]). shared[1].

Two separate reads with bank conflicts if type is defined as
struct type { float x. y. The following code. For example. __shared__ int shared_hi[32]. shared[2]. double data = shared[BaseIndex + tid]. There are no bank conflicts however.
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CUDA C Programming Guide Version 3. if the same array is accessed the following way:
char data = shared[BaseIndex + 4 * tid]. for example:
__shared__ struct type shared[32]. double dataOut = __hiloint2double(shared_hi[BaseIndex + tid]. The same applies to structure assignments. for example. }.3.1. belong to the same bank.0. and shared[3]. z.1
. }.
results in:

Three separate reads without bank conflicts if type is defined as
struct type { float x.

a multiprocessor consists of: 32 CUDA cores for integer and floating-point arithmetic operations..  2 clock cycles for a double-precision floating-point arithmetic instruction.4
G.g.
Compute Capabilities
G.1
155
.0
Architecture
For devices of compute capability 2. The first scheduler is in charge of the warps with an odd ID and the second scheduler is in charge of the warps with an even ID. A multiprocessor also has a read-only uniform cache that is shared by all functional units and speeds up reads from the constant memory space. The same on-chip memory is used for both L1 and shared memory: It can be configured as 48 KB of shared memory with 16 KB of L1 cache (default setting) or as 16 KB of shared memory with 48 KB of L1 cache using cudaFuncSetCacheConfig() or cuFuncSetCacheConfig():
// Device code __global__ void MyKernel() { . To execute an instruction for all threads of a warp. the other scheduler cannot issue any instruction. whether reads are cached in both L1 and L2 or in L2 only) can be partially configured on a peraccess basis using modifiers to the load or store instruction.  8 clock cycles for a single-precision floating-point transcendental instruction. which resides in device memory.4. each scheduler issues an instruction for some warp that is ready to execute.Appendix G.1
Compute Capability 2.  4 special function units for single-precision floating-point transcendental functions. if any. The cache behavior (e.

There is an L1 cache for each multiprocessor and an L2 cache shared by all multiprocessors.

A warp scheduler can issue an instruction to only half of the CUDA cores. both of which are used to cache accesses to local or global memory. } // Host code // Runtime API // cudaFuncCachePreferShared: shared memory is 48 KB // cudaFuncCachePreferL1: shared memory is 16 KB // cudaFuncCachePreferNone: no preference cudaFuncSetCacheConfig(MyKernel. including temporary register spills. cudaFuncCachePreferShared) // Driver API CUDA C Programming Guide Version 3.. At every instruction issue time.0.1.  2 warp schedulers. a warp scheduler must therefore issue the instruction over: 2 clock cycles for an integer or floating-point arithmetic instruction. Note that when a scheduler issues a double-precision floating-point instruction.

If a non-atomic instruction executed by a warp writes to the same location in global memory for more than one of the threads of the warp. one for each quarter-warp.Appendix G. if the size is 16 bytes.1
. Using the –dlcm compilation flag.
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CUDA C Programming Guide Version 3.  Four memory requests.

Note that threads can access any words in any order.
G. if the size is 8 bytes. only one thread performs a write and which thread does it is undefined.4. A GPC includes four multiprocessors. or at the throughput of device memory.2
Global Memory
Global memory accesses are cached. Each memory request is then broken down into cache line requests that are issued independently.4.1. CU_FUNC_CACHE_PREFER_SHARED)
Multiprocessors are grouped into Graphics Processor Clusters (GPCs).
Compute Capabilities
// CU_FUNC_CACHE_PREFER_SHARED: shared memory is 48 KB // CU_FUNC_CACHE_PREFER_L1: shared memory is 16 KB // CU_FUNC_CACHE_PREFER_NONE: no preference CUfunction myKernel. otherwise. cuFuncSetCacheConfig(myKernel. A cache line in L1 or L2 is 128 bytes and maps to a 128-byte aligned segment in device memory. which resides in device memory. including the same words. It accesses the texture cache via a texture unit that implements the various addressing modes and data filtering mentioned in Section 3. they can be configured at compile time to be cached in both L1 and L2 (-Xptxas -dlcm=ca) (this is the default setting) or in L2 only (-Xptxas -dlcm=cg). If the size of the words accessed by each thread is more than 4 bytes. one for each half-warp. Each multiprocessor has a read-only texture cache to speed up reads from the texture memory space.2. A cache line request is serviced at the throughput of L1 or L2 cache in case of a cache hit. a memory request by a warp is first split into separate 128-byte memory requests that are issued independently: Two memory requests.

64-Bit Accesses
For 64-bit accesses.3
Shared Memory
Shared memory has 32 banks that are organized such that successive 32-bit words are assigned to successive banks.
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In this case. float data = shared[BaseIndex + s * tid]. }.4.e. This means.e. char data = shared[BaseIndex + tid]. i. s is odd.1
32-Bit Strided Access
A common access pattern is for each thread to access a 32-bit word from an array indexed by the thread ID tid and with some stride s:
__shared__ float shared[32]. Figure G-2 shows some examples of strided access.
G. __shared__ struct type shared[32]. each byte is written by only one of the threads (which thread performs the write is undefined). there may be bank conflicts between a thread belonging to the first half of a warp and a thread belonging to the second half of the same warp. equivalently. unlike for devices of lower compute capability.4. If two or more threads access any bytes within the same 32-bit word. i.e. 32) or.2
Larger Than 32-Bit Access
64-bit and 128-bit accesses are specifically handled to minimize bank conflicts as described below. Each bank has a bandwidth of 32 bits per two clock cycles. there is no bank conflict between these threads: For read accesses. there are no bank conflicts if an array of char is accessed as follows. threads tid and tid+n access the same bank whenever s*n is a multiple of the number of banks (i. z. for example:
__shared__ char shared[32]. multiple words can be broadcast in a single transaction). struct type data = shared[BaseIndex + tid]. or 128-bit accesses. a bank conflict only occurs if two or more threads in either of the half-warps access different addresses belonging to the same bank. Therefore. 64-bit.Appendix G.e.1
. for write accesses. interleaved. whenever n is a multiple of 32/d where d is the greatest common divisor of 32 and s.
results in three separate 32-bit reads without bank conflicts since each member is accessed with a stride of three 32-bit words. the word is broadcast to the requesting threads (unlike for devices of compute capability 1.3. The following code. y. that is only if d is equal to 1. As a consequence. that unlike for devices of compute capability 1. there will be no bank conflict only if the warp size (i. for example:
struct type { float x.3.
Compute Capabilities
G. in particular. Other accesses larger than 32-bit are split into 32-bit.
G.x. A bank conflict only occurs if two or more threads access any bytes within different 32-bit words belonging to the same bank.4. 32) is less than or equal to 32/d.x.1.

one must add 1 to the maximum number of threads in a quarter-warp that access different addresses belonging to the same bank. for example:
__shared__ double shared[32].
128-Bit Accesses
The majority of 128-bit accesses will cause 2-way bank conflicts.Appendix G.  not dependent on thread ID.
Compute Capabilities
Unlike for devices of compute capability 1. devices of compute capability 2. even if no two threads in a quarter-warp access different addresses belonging to the same bank.4.4
Constant Memory
In addition to the constant memory space supported by devices of all compute capabilities (where __constant__ variables reside).

CUDA C Programming Guide Version 3. to determine the ways of bank conflicts.
G.  read-only in the kernel (programmer can enforce this using the const keyword).0 support the LDU (LoaD Uniform) instruction that the compiler use to load any variable that is: pointing to global memory. there are no bank conflicts for arrays of doubles accessed as follows. double data = shared[BaseIndex + tid]. Therefore.1
159
.x.1.