The presentation covers key features of the processor and its architecture, physical implementation (key statistics, on-chip L2 caches, crossbar, clocking scheme, SerDes interfaces, and cryptography support), power and power management and DFT features an

Umesh Nawathe is currently a Senior Manager on the Niagara 2 project responsible for global/analog circuits and technology. Umesh has an MS(EE) from University of Michigan, Ann Arbor. He joined SUN about 3 years ago. Prior to that, Umesh held senior technical and management positions working for MIPS/Silicon Graphics designing MIPS processors and Intel before that.

The presentation covers key features of the processor and its architecture, physical implementation (key statistics, on-chip L2 caches, crossbar, clocking scheme, SerDes interfaces, and cryptography support), power and power management and DFT features and test results.

Niagara 2 is the first 64-bit 64-thread SPARC "System on a chip" from Sun based on the power-efficient CMT architecture optimized for Space, Power and Performance (SWaP). It is the successor to Niagara 1, which is known in the market as UltraSPARCR T1. It doubles Niagara 1's throughput performance, significantly improves Floating point throughput performance, has advanced cryptography support and two 10G ethernet ports on chip.

-Niagara 2 Key Features -

Second generation chip multi-threading processor optimized for Space, Power and Performance (SWaP)