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Description

The interconnect frequency might issue one of the following warning or information messages listed below when the axi_aclk_out clock is clocking the interconnect:

INFO:EDK:740 - Cannot determine the input clock associated with port :axi_pcie_0:axi_aclk_out. Clock DRCs will not be performed on this core and cores connected to it.

INFO:EDK:1039 - Did not update the value for parameter:axi_pcie_0:C_AXI_ACLK_FREQ_HZ. Top-level frequency could not be propagated to this IP. Please make sure that you have specified the frequency of the top-level clock port, and that the clocks are properly connected.

WARNING:EDK:3712 - IPNAME: axi_interconnect, INSTANCE:axi_interconnect_0 -Frequency of the interconnect's clock port could not be determined. All IPsin the design will be considered to be asynchronous with respect to the interconnect. This will lead to more resource usage. You can avoid this by specifying the clock frequency on the port that the interconnect's clock is connected to.

Note: The "Version Found" column lists the version that the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Solution

This is a known issue with the AXI Bridge for PCI Express caused by a combination of two known issues:

The util_ds_buf not propagating the reference frequency information to the bridge's refclk port. This is currently still a known restriction and is not planned to be fixed due to restrictions on the util_ds_buf pcore. For this reason, step #1 will need to still be implemented.

The axi_out_clk not containing the correct CLK_FACTOR in the MPD. This issue is fixed according to (Xilinx Answer 44969)