HMC Verification IP

HMC-Xactor is a comprehensive memory VIP solution portfolio for Hybrid Memory Cube (HMC 2.0) targeting a new standard in memory performance, density, power consumption, and cost. HMC-Xactor targets SoC and memory controller designers using external HMC devices and PHY developers to ensure comprehensive verification and protocol and timing compliance. HMC-Xactor implements a complete set of models and timing and protocol checkers utilizing a truly flexible and open architecture based on a 100% native SystemVerilog and UVM

Deliverables

HMC host and device BFMs

User Guide

Tech Specs

Short description:

Hybrid Memory Cube (HMC 2.0) VIP

Provider:

Avery Design Systems

Languages Supported:

SystemVerilog, VHDL

Compliant Standard:

HMC 2.0

Maturity:

Production

Availability:

Now

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Features

HMC device model supports a DUT which is an HMC memory controller and processes all commands, and supports command completion coalescing, randomly delayed and out of order responses (link-vault-RBC addr).

Models support flexible and unencrypted timing class for customization including random constraints for link/vault switch, DRAM access times, and refresh and scrubbing

Supports other features including serial and parallel interfaces, bypass mode to skip power-on reset, lane polarity and reversal, independent link power state management, chaining, and automatic flow control and retry
Inject errors at all layers through callbacks