The 74F113, dual negative edge-triggered JK-type flip-flop, featuresindividual J, K, clock (CP), set (SD) inputs, true and complementaryoutputs. The asynchronous SD input, when low, forces the outputsto the steady state levels as shown in the function table regardlessof the level at the other inputs.

A high level on the clock (CP) input enables the J and K inputs anddata will be accepted. The logic levels at the J and K inputs may beallowed to change while the CP is high and flip-flop will performaccording to the function table as long as minimum setup and holdtimes are observed. Output changes are initiated by the high-to-lowtransition of the CP.

PIN CONFIGURATION

14

13

12

11

10

9

8

7

6

5

4

3

2

1

GND

V

CC

SD1

Q1

Q1

J1

CP1

K1

CP0

K0

Q0

J0

SD0

Q0

SF00140

TYPE

TYPICAL f

max

TYPICAL SUPPLY CURRENT (TOTAL)

74F113

100MHz

15mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

COMMERCIAL RANGE

V

CC

= 5V

±

10%,

T

amb

= 0

°

C to +70

°

C

INDUSTRIAL RANGE

V

CC

= 5V

±

10%,

T

amb

= ­40

°

C to +85

°

C

PKG. DWG. #

14-pin plastic DIP

N74F113N

I74F113N

SOT27­1

14-pin plastic SO

N74F113D

I74F113D

SOT108­1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F (U.L.) HIGH/LOW

LOAD VALUE HIGH/LOW

J0, J1

J inputs

1.0/1.0

20

µ

A/0.6mA

K0, K1

K inputs

1.0/1.0

20

µ

A/0.6mA

CP0, CP1

Clock inputs (active falling edge)

1.0/4.0

20

µ

A/2.4mA

SD0, SD1

Set inputs (active low)

1.0/5.0

20

µ

A/3.0mA

Q0, Q1, Q0, Q1

Data outputs

50/33

1.0mA/20mA

NOTE:One (1.0) FAST unit load is defined as: 20

µ

A in the High state and 0.6mA in the Low state.

LOGIC SYMBOL

Q0

Q0

Q1

Q1

5

6

9

8

V

CC

= Pin 14

GND = Pin 7

1

4

13

10

CP0

SD0

CP1

SD1

J1

K0

2

12

SF00141

K1

J0

3

11

IEC/IEEE SYMBOL

3

1

2

4

11

13

12

10

5

6

9

8

1J

2J

C1

C2

1S

1K

2K

2S

SF00142

Philips Semiconductors

Product specification

74F113

Dual J-K negative edge-triggered flip-flops without reset

1996 Mar 14

3

LOGIC DIAGRAM

VCC =

Pin 14

GND = Pin 7

Q

J

CP

1, 13

K

2, 12

4, 10

5, 9

Q

SD

6, 8

3, 11

SF00143

FUNCTION TABLE

INPUTS

OUTPUTS

OPERATING MODE

SD

CP

J

K

Q

Q

OPERATING MODE

L

X

X

X

H

L

Asynchronous set

H

h

h

q

q

Toggle

H

h

l

H

L

Load "1" (set)

H

l

h

L

H

Load "0" (reset)

H

l

l

q

q

Hold 'no change"

NOTES:H = High-voltage levelh

= High-voltage level one setup time prior to high-to-low

clock transition

L

= Low-voltage level

l

= Low-voltage level one setup time prior to high-to-low clock

transition

q

= Lower case indicate the state of the referenced output

prior to the high-to-low clock transition

X = Don't care

= high-to-low clock transition

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.)

NOTES:1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.2. All typical values are at V

CC

= 5V, T

amb

= 25

°

C.

3. Not more than one output should be shorted at a time. For testing I

OS

, the use of high-speed test apparatus and/or sample-and-hold

techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shortingof a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In anysequence of parameter tests, I

OS

tests should be performed last.

4. Measure I

CC

with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.

AC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL

PARAMETER

TEST

CONDITION

V

CC

= +5.0V

T

amb

= +25

°

C

C

L

= 50pF

R

L

= 500

V

CC

= +5.0V

±

10%

T

amb

= 0

°

C to +70

°

C

C

L

= 50pF

R

L

= 500

V

CC

= +5.0V

±

10%

T

amb

= ­40

°

C to +85

°

C

C

L

= 50pF

R

L

= 500

UNIT

MIN

TYP

MAX

MIN

MAX

MIN

MAX

f

max

Maximum clock frequency

Waveform 1

85

100

80

80

ns

t

PLH

t

PHL

Propagation delayCPn to Qn or Qn

Waveform 1

2.02.0

4.04.0

6.06.0

2.02.0

7.07.0

2.02.0

7.57.0

ns

t

PLH

t

PHL

Propagation delaySDn, to Qn or Qn

Waveform 2

2.02.0

4.54.5

6.56.5

2.02.0

7.57.5

2.02.0

8.07.5

ns

AC SETUP REQUIREMENTS

LIMITS

SYMBOL

PARAMETER

TEST

CONDITION

V

CC

= +5.0V

T

amb

= +25

°

C

C

L

= 50pF

R

L

= 500

V

CC

= +5.0V

±

10%

T

amb

= 0

°

C to +70

°

C

C

L

= 50pF

R

L

= 500

V

CC

= +5.0V

±

10%

T

amb

= ­40

°

C to +85

°

C

C

L

= 50pF

R

L

= 500

UNIT

MIN

TYP

MAX

MIN

MAX

MIN

MAX

t

su

(H)

t

su

(L)

Setup time, high or lowJn, Kn to CPn

Waveform 1

4.03.5

5.04.0

5.04.5

ns

t

h

(H)

t

h

(L)

Hold time, high or lowJn, Kn to CPn

Waveform 1

0.00.0

0.00.0

0.00.0

ns

t

w

(H)

t

w

(L)

CP pulse width,high or low

Waveform 1

4.54.5

5.05.0

5.05.0

ns

t

w

(L)

SDn pulse width, low

Waveform 2

4.5

5.0

5.0

ns

t

rec

Recovery timeSDn to CPn

Waveform 2

4.5

5.0

5.0

ns

Philips Semiconductors

Product specification

74F113

Dual J-K negative edge-triggered flip-flops without reset

1996 Mar 14

5

AC WAVEFORMS

For all waveforms, V

M

= 1.5V.

The shaded areas indicate when the input is permitted to change for predictable output performance.

tPLH

VM

VM

CPn

VM

VM

VM

VM

VM

VM

Jn, Kn

Qn

VM

tw(H)

1/fmax

tsu(L)

th(L) = 0

VM

VM

tPLH

Qn

tw(L)

tPHL

tPHL

tsu(H)

th(H) = 0

SF00144

Kn

Jn

Jn

Kn

Waveform 1.

Propagation Delay for Data to Output, Data Setup Time and Hold Times, and Clock Width,

and Maximum Clock Frequency

VM

CPn

Qn

VM

VM

Qn

tPHL

tPLH

SDn

VM

VM

tw(L)

trec

Jn, Kn

SF00145

Waveform 2.

Propagation Delay for Set to Output, Set Pulse Width, and Recovery Time for Set to Clock

Philips Semiconductors

Product specification

74F113

Dual J-K negative edge-triggered flip-flops without reset

1996 Mar 14

6

TEST CIRCUIT AND WAVEFORMS

tw

90%

VM

10%

90%

VM

10%

90%

VM

10%

90%

VM

10%

NEGATIVEPULSE

POSITIVEPULSE

tw

AMP (V)

0V

0V

tTHL (tf

)

INPUT PULSE REQUIREMENTS

rep. rate

t

w

t

TLH

t

THL

1MHz

500ns

2.5ns

2.5ns

Input Pulse Definition

VCC

family

74F

D.U.T.

PULSE

GENERATOR

RL

CL

RT

VIN

VOUT

Test Circuit for Totem-Pole Outputs

DEFINITIONS:R

L

= Load resistor;

see AC ELECTRICAL CHARACTERISTICS for value.

C

L

= Load capacitance includes jig and probe capacitance;

see AC ELECTRICAL CHARACTERISTICS for value.

R

T

= Termination resistance should be equal to Z

OUT

of

pulse generators.

tTHL (tf

)

tTLH (tr

)

tTLH (tr

)

AMP (V)

amplitude

3.0V

1.5V

V

M

SF00006

Philips Semiconductors

Product specification

74F113

Dual J-K negative edge-triggered flip-flops without reset

1996 Mar 14

7

DIP14:

plastic dual in-line package; 14 leads (300 mil)

SOT27-1

Philips Semiconductors

Product specification

74F113

Dual J-K negative edge-triggered flip-flops without reset

1996 Mar 14

8

SO14:

plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

Philips Semiconductors

Product specification

74F113

Dual J-K negative edge-triggered flip-flops without reset

1996 Mar 14

9

NOTES

Philips Semiconductors

Product specification

74F113

Dual J-K negative edge-triggered flip-flops without reset

yyyy mmm dd

10

Definitions

Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. Fordetailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above oneor more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these orat any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extendedperiods may affect device reliability.

Application information -- Applications that are described herein for any of these products are for illustrative purposes only. PhilipsSemiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing ormodification.

Disclaimers

Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products canreasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applicationsdo so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standardcells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes noresponsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to theseproducts, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unlessotherwise specified.

This data sheet contains the design target or goal specifications for product development.Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.Philips Semiconductors reserves the right to make chages at any time without notice in order toimprove design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to makechanges at any time without notice in order to improve design and supply the best possible product.

Data sheet status

[1]

Please consult the most recently issued datasheet before initiating or completing a design.