Posts Tagged ‘G450C’

Pete Singerreveals the lineup of presenters for Session 1 of The ConFab, to be held June 22-25 in Las Vegas, and provides summaries of their talks. Speakers will be Vijay Ullal, COO, Fairchild Semiconductor; Dave Anderson, President and CEO, Novati Technologies; Gopal Rao, Senior Director Business Development, SEMATECH; Adrian Maynes, Program Manager, F450C; and Bill McClean, President, IC Insights.

Phil Garroublogs about a variety of diverse issues this week, including GLOBALFOUNDRIES’ potential purchase of IBM’s semiconductor business, Altera’s separate deals with Intel and TSMC, why FinFET could be more expensive that more conventional CMOS strategies, as view by Handle Jones of IBS, and a new joint development program between ASE and Inotera focused on 3D IC packaging.

If you’ve ever gone to the grocery store and forgotten that one essential item, the question you face is how quickly can you run back in the store, get that necessary item, and be on your way home? Jeff Wilson of Mentor Graphics says that design teams often feel this way as they approach tapeout, only to be confronted with engineering change orders (ECOs). One major factor—the challenge of re-filling designs.

Phil Garrouprovides his analysis of the presentations given at this year’s ISS meeting, focusing on those from IBM, Linx, imec, IHS and IBS. IBM’s Jon Casey, for example, notes that silicon performance advancement is becoming more challenging as scaling is becoming more costly and that we need to look beyond CMOS for cost effective technology solutions. He proposes integrated co-development of Silicon and packaging solutions to achieve new technologies with superior cost/performance metrics.

Pete Singer hasn’t toasted to cheap silicon for a while. Why? Because that mission has been accomplished. At SEMI’s ISS, Paul Farrar, manager of the G450C consortium put the industry progress over the last 40+ years in perspective. “1 Megabyte of memory in 1970 was $750,000. It was sold as an IBM add-on,” he said. “The great technology was made of 57mm wafers, five masking levels, and one level of metal. Today, it’s is less than a penny. That is a 100 million X improvement.”

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The ConFab is a three-day conference and networking event for the semiconductor manufacturing and design industry decision-makers and influencers. The ConFab brings suppliers together with leaders at IC manufacturing companies, foundries, fabless companies, packaging houses or OSATs, as well as suppliers of MEMS and other types of electronics. Learn more at theconfab.com.

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The increasing demand for wireless data bandwidth and the emergence of LTE and LTE Advanced standards pushes radio-frequency (RF) IC designers to develop devices with higher levels of integrated RF functions, meeting more and more stringent specification levels. The substrates on which those devices are manufactured play a major role in achieving that level of performance.

Everybody’s talking about it, but just what is DFM? According to various EDA company websites, design for manufacturing can be: generation of yield optimized cells; layout compaction; wafer mapping optimization; planarity fill; or, statistical timing among other definitions. Obviously, there is very little consensus. For me, DFM is what makes my job hard: Characterizing it, and developing tools for it, is the most important item on my agenda.

In nanometer designs, the number of single vias, and the number of via transitions with minimal overlap, can contribute significantly to yield loss. Yet doubling every via leads to other yield-related problems and has a huge impact on design size. While there is still concern over of how many vias can be fixed without rerouting and without creating DRC violations, the Calibre via doubling tool can identify via transitions and recommend areas for second via insertion without increasing area.