Driving circuits - A driving circuit comprising an input voltage source set, a reference voltage source, a voltage level shift unit, a logic unit, a safety unit, and an output voltage terminal. The input voltage source set provides an input voltage set. The reference voltage source provides a reference voltage. The voltage level shift unit raises one of levels of the input voltage set to a level of the reference voltage. The logic unit receives the reference voltage and the input voltage set and outputs a control voltage. The safety unit conducts the control voltage to a ground. The output voltage terminal receives the control voltage and outputs an output voltage.

2008-10-30

20080265942

DIFFERENTIAL AMPLIFIER, DIGITAL-TO-ANALOG CONVERTER AND DISPLAY APPARATUS - A differential amplifier includes a first differential pair, a second differential pair, a load circuit, connected in common to the first and second differential pairs, and first and second current sources for supplying the current to the first and second differential pairs, and amplifies a signal responsive to a common output signal of the first and second differential pairs. One of differential inputs of the first differential pair is connected to a reference voltage. A data output period includes a first period and a second period. During the first period, voltages of first and second input terminals are input through first and fourth switches in the on-state to differential inputs of the second differential pair. The other of the differential inputs of the first differential pair is connected through a third switch in the on-state to an output terminal. An output voltage is stored in a capacitor C connected to the other differential input of the first differential pair. The first, third and fourth switches are turned off during the second period. One of the differential inputs of the second differential pair is connected through a second switch to the output terminal. The other differential input of the second differential pair is connected through a fifth switch to a third input terminal.

2008-10-30

20080265943

LINE DRIVING CIRCUIT OF SEMICONDUCTOR DEVICE - Disclosed is a line driving circuit which includes two NMOS transistors in series between a supply voltage and a ground voltage. The output of the line driving circuit is applied to an interior circuit through a transmission line, and a repeater is used when the transmission line is long.

PHASE FREQUENCY DETECTOR WITH LIMITED OUTPUT PULSE WIDTH AND METHOD THEREOF - Phase frequency detectors with limited output pulse width and related methods are provided. On exemplary phase frequency detector includes a first edge detector, a second edge detector, and a pulse reshaping controller. The first edge detector is for detecting first-type edges of a first signal to generate a first detection signal. The second edge detector is for detecting the first-type edges of a second signal to generate a second detection signal. The pulse reshaping controller is for receiving the first detection signal and the second detection signal, and for generating a first control signal to the first edge detector and generating a second control signal to the second edge detector. In addition, the pulse reshaping controller further generates a first output signal and a second output signal, wherein a pulse width of the first output signal is limited by the pulse reshaping controller.

Current mirror circuit and constant current having the same - A current mirror circuit includes a pair of first and second transistors having bases connected together and emitters connected to a power line, a resistor connected between the bases of the first and second transistors and the power line, a third transistor for providing base currents of the first and second transistors and a resistor current flowing through the resistor, and a current compensation circuit that adds a compensation current to an input current to the first transistor. The amount of the compensation current is approximately equal to that of the resistor current divided by a current gain of the third transistor. Thus, the compensation current compensates the difference between a collector current of the first transistor and the input current.

CMOS DRIVING CIRCUIT - A CMOS driving circuit, wherein an output buffer stage with a transistor switch is added to the final buffer stage of a conventional CMOS driving circuit to drive a power transistor. The output buffer stage has two input terminals for DC input voltage, and uses the high voltage of a voltage converting circuit in a multi-voltage system as one DC input voltage. The driving load capacity of the CMOS driving circuit is improved by converting the higher of the two DC input voltages to a modulated driving voltage and outputting it via an output terminal, so that the on-resistance of a power transistor connected with the output buffer stage is lowered, the power consumption of the power transistor is reduced, the output capacity is improved, and the area of the power transistor is lowered with the same output power.

2008-10-30

20080265950

LOW-POWER IMPEDANCE-MATCHED DRIVER - One embodiment of the invention includes a driver circuit. The driver circuit comprises a high-side switch that is activated in response to a positive driver input signal to provide a positive output signal at a driver output. The driver circuit also comprises a low-side switch that is activated in response to a negative driver input signal to provide a negative output signal at the driver output. The positive and negative driver input and output signals can be relative to respective cross-over magnitudes. The driver circuit further comprises at least one impedance-matching device configured to activate the low-side switch in response to a positive signal reflection at the driver output and to activate the high-side switch in response to a negative signal reflection at the driver output.

2008-10-30

20080265951

DRIVER WITH PROGRAMMABLE POWER COMMENSURATE WITH DATA-RATE - One embodiment of the invention includes a driver circuit. The driver circuit comprises an output transistor that is biased to provide an output signal in response to an input signal. The driver circuit also comprises at least one programmable variable resistor configured to provide a bias magnitude of the output transistor that sets a power of the driver circuit to be commensurate with a data-rate of the input signal.

2008-10-30

20080265952

Gate Driver Circuit for Power Transistor - A circuit arrangement with a gate driver circuit for a power transistor is disclosed which is suitable for low voltage applications, permitting a rail-to-rail output without a loss in speed/bandwidth, which is very simple, low cost, low current and area efficient. The gate driver circuit comprises a drain follower with a MOS driver transistor having the gate connected to an interconnection node of a capacitive divider. A first capacitor of the capacitive divider is connected between the drain and the gate and a second capacitor is connected between the gate and an input of the gate driver circuit. The gate driver has the required low impedance for driving the gate of the power transistor.

Reduced Transition Time Ramp Waveform Generator - A system and method for generating a reduced transition time ramp waveform signal are disclosed. Two offset, synchronized ramp waveform signals are generated. Each ramp waveform signal has a repeating sequence including a linear development segment, an upper transition segment, a return segment, and a lower transition segment. The ramp waveform signals are offset synchronized such that the linear development segment of each ramp waveform signal begins before the linear development segment of the other ramp waveform signal ends. Each ramp waveform signal is sampled during its linear development segment to generate a reduced transition time ramp waveform signal.

2008-10-30

20080265955

SYNCHRONIZATION CIRCUIT AND METHOD - An integrated circuit comprises a system clock and an interface clock. A synchronizing circuit is provided for synchronizing a control signal associated with a predetermined command, for example a PENABLE signal associated with a WRITE command, when the system clock of the integrated circuit is present and bypassing the synchronization circuitry when the system clock is not present. Thus, whenever the system clock of the integrated circuit is active, all the control interface write operations are synchronized to the system clock, and hence there are no timing issues due to different clock domains. If the system clock is not present, the asynchronous writes cannot cause any timing problems, and the synchronization circuit is therefore bypassed.

2008-10-30

20080265956

Semiconductor device having input circuits activated by clocks having different phases - Input circuits connected to an external input terminal PAD via resistor elements are activated in response to the level transition of the clock signals supplied thereto for accepting input signals. In order to input signals applied to the external input terminal PAD clock signals having different phases are supplied to the respective input circuits. The cycle time of each one input circuit can be made longer by sequentially assigning the serial data supplied to the external input terminals in response to the clock signals having different clock signals. Since the input circuits are isolated from each other by means of the resistor elements, the influence of the kick back signal which occurs at first stage of each the input circuit upon the other input circuit can be made very small.

2008-10-30

20080265957

Self-Resetting Phase Frequency Detector with Multiple Ranges of Clock Difference - A phase detector which provides a dynamic output signal and which automatically resets if a reference clock signal and a feedback clock signal align after an output pulse is generated. With the phase detector in accordance with the present invention, when there is a difference between the positive clock edges of the reference clock signal and the feedback clock signal, the phase detector generates output pulse. The output is used to correct the feedback clock signal. In the next cycle, if the feedback signal is corrected so that both the reference clock signal and feedback clock signal are aligned, then the output signals are reset to zero. The ability to reset advantageously prevents an unexpected correction that can occur in certain phase detector designs.

2008-10-30

20080265958

Method for Noise Reduction in a Phase Locked Loop and a Device Having Noise Reduction Capabilities - A method for reducing noise in a device that includes at least one phase locked loop (PLL), the method includes: adjusting at least one adjustable component of a PLL such as to determine a time shift; modulating a frequency divider such as to generate a modulation noise within a modulation noise period and to provide a frequency divided signal; introducing the time shift between the modulation noise period and a measurement period; and measuring, during a measurement period a difference between a reference signal and the frequency divided signal. A device that includes a phased locked loop. The phase locked loop (PLL) includes: a frequency divider, adapted to receive an output signal from a controlled oscillator and to provide a divided frequency signal; a modulator, adapted to affect at least one frequency division characteristic and to introduce a modulation noise during a modulation noise period, a phase detector, adapted to measure, during a measurement period, a difference between a reference signal and the frequency divided signal; and an adjustable delay unit adapted to affect an adjustable time shift between the modulation period and the measurement period.

2008-10-30

20080265959

PLL circuit and frequency setting circuit employing the same - Disclosed is a PLL circuit in which an output signal of a frequency oscillator (VCO or ICO), an oscillation frequency of which is controlled by an electrical signal, is supplied via a high pass filter (HPF) to one of input terminals of a phase detector, the other input terminal of which receives a reference frequency. An output signal of the phase detector is supplied to a loop filter which then outputs a DC component of the signal that controls the frequency oscillator as the electrical signal.

2008-10-30

20080265960

Pulse Stream Generator - A system and method for generating a pulse stream are disclosed. A ramp signal is generated. The ramp signal is compared with a Time of Transition signal to produce a result indicative of the comparison. Responsive to the result of the comparison, the pulse stream signal is output. The result of the comparison instructs the selector whether to maintain the current output pulse stream signal or replace the current output pulse stream signal with a Polarity signal.

2008-10-30

20080265961

CLOCK SIGNAL GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE - In a semiconductor device capable of radio communication, a stable clock signal is generated even if a reference clock signal for generating a clock signal has varied frequencies in each cycle. A clock signal generation circuit includes an edge detection circuit that detects an edge of an input signal and generates a synchronization signal, a reference clock signal generation circuit that generates a clock signal which functions as reference, a counter circuit that counts the number of edges of rise of the reference clock signal in accordance with the synchronization signal, a duty ratio selection circuit that selects a duty ratio of a clock signal from a count value, and a frequency division circuit that generates the clock signal having the selected duty ratio.

2008-10-30

20080265962

SCANNABLE FLIP-FLOP WITH NON-VOLATILE STORAGE ELEMENT AND METHOD - A circuit has a master latch having an input for receiving an input data signal, and an output. A slave latch has a first input coupled to the output of the master latch, and an output for providing an output data signal. A non-volatile storage element stores a predetermined value. The non-volatile storage element has an output coupled to the first input of the slave latch. The output data signal corresponds to one of either the input data signal or the predetermined value stored by the non-volatile storage element in response to a control signal.

2008-10-30

20080265963

CASCADED PHASE SHIFTER - The invention relates to a phase shifter which has at least two cascaded delay stages (

2008-10-30

20080265964

SINGLE SIGNAL-TO-DIFFERENTIAL SIGNAL CONVERTER AND CONVERTING METHOD - In an example embodiments, a single signal-to-differential signal converter includes a first inverter for receiving and inverting a single input signal and outputting an inverted single input signal to a first node, and a first differential signal generating portion for generating a first signal and an inverted first signal which have the opposite phases to each other to second and third nodes in response to the single input signal. The single signal-to-differential signal converter further includes a second differential signal generating portion for generating a second signal and an inverted second signal which have the opposite phases to each other to the second and third nodes in response to the inverted single input signal, wherein the single signal-to-differential signal converter outputs differential signals such that the first and second signals applied to the second node are merged by a phase interpolation and the inverted first and second signals applied to the third node are merged by a phase interpolation.

INTEGRATED CIRCUIT WITH A PROGRAMMABLE DELAY AND A METHOD THEREOF - An integrated circuit including a first circuit block having a power supply terminal for receiving a first power supply voltage and an output terminal for providing a first data signal is provided. The integrated circuit further includes a second circuit block having a power supply voltage terminal for receiving a second power supply voltage and an input terminal coupled to the output terminal of the first circuit block for receiving the first data signal. The integrated circuit further includes a first programmable delay block for adding a first delay time to the first data signal when one or both of the first or second power supply voltages is changed.

2008-10-30

20080265967

INTEGRATED CIRCUIT FOR CLOCK GENERATION FOR MEMORY DEVICES - A device for generating clock signals for use with a plurality of DDR memory devices on a dual in-line memory module (DIMM) board is provided that has a data buffer for buffering data. A clock divider divides a first clock signal (CLK

2008-10-30

20080265968

CLOCK FREQUENCY DIFFUSING DEVICE - A clock frequency diffusing device including a multiphase clock signal generator, a random number generator, signal selectors, and a clock signal generator. The multiphase clock signal generator receives an input clock signal and produces a plurality of delayed clock signals that are delayed relative to the input clock signal by various amounts of time. The clock signal selector randomly chooses one of the delayed signals based upon random numbers generated by the random number generator and produces a selector output signal based on its chosen delayed clock signal. A clock signal generator receives the selector output signal and produces an output clock signal.

VOLTAGE LEVEL SHIFTER AND BUFFER USING SAME - A voltage level shifter with an input transistor pair, a cross-coupled load chain transistor pair and a pair of current sources, effects reduced power consumption through the use of the cross-coupled load chain transistor pair to minimize the DC current component present in known voltage level shifters. In specific embodiments, feedback elements may be used to minimize delays in signal transitions. A reference voltage that corresponds to a current capability of the input transistor pair may be used to regulate the current sources in the load chain. Changes in a swing of the input signal voltage received by the input transistor pair may be reflected in corresponding changes to the reference voltage. The voltage level shifter may be of particular use in a buffer.

2008-10-30

20080265971

Voltage level shift circuits - A voltage level shift circuit has a plurality of input voltage sources, a reference voltage source, a voltage level shift unit, a stabilizing unit, a first output voltage terminal, and a second output voltage terminal. The input voltage sources provide a plurality of input voltages. The reference voltage source provides a reference voltage. The voltage level shift unit raises the input voltages to a level of the reference voltage. The stabilizing unit prevents power leakage and resulting abnormal voltage levels in the voltage level shift unit. The first output voltage terminal provides a first output voltage. The second output voltage terminal provides a second output voltage inverse to the first output voltage.

2008-10-30

20080265972

OUTPUT CIRCUIT AND MULTI-OUTPUT CIRCUIT - An output circuit includes a high-side transistor, a low-side transistor, a gate protection circuit, a level shift circuit, and a pre-driver circuit. The level shift circuit interrupts a current path from an output terminal to the level shift circuit after a predetermined time has passed since the high-side transistor was switched OFF.

2008-10-30

20080265973

Semiconductor Device Having Transmitter/Receiver Circuit Between Circuit Blocks - A receiver circuit includes first and second constant current sources respectively connected to a pair of first and second receiving terminals to receive complementary current signals, a first NMOS transistor connected at a source thereof to the first receiving terminal and the first constant current source and connected at a drain thereof to a first power supply via a first output terminal and first load means, and a second NMOS transistor connected at a source thereof to the second receiving terminal and the second constant current source and connected at a drain thereof to the first power supply via a second output terminal and second load means.

Method for controlling vertical type MOSFET in bridge circuit - A method for controlling a vertical type MOSFET in a bridge circuit is provided to reduce diode power loss and improve a reverse recovery characteristic. The method includes controlling a forward voltage of a built-in diode of the vertical type MOSFET to be a first forward voltage by setting a gate voltage of the vertical MOSFET to a first gate voltage, so that the vertical type MOSFET is switched into a first off mode; and controlling the forward voltage of the built-in diode of the vertical type MOSFET to be a second forward voltage by setting the gate voltage of the vertical MOSFET to a second gate voltage, so that the vertical type MOSFET is switched into a second off mode.

2008-10-30

20080265976

COMPUTER APPARATUS AND SWITCH CONTROL METHOD THEREOF - A computer apparatus includes a switch, a signal generating part which generates a signal corresponding to a position of the switch, a system part which receives the generated signal and operates, and a controller to control the signal generating part so that the signal generated in the signal generating part can be prevented from being applied to the system part for a predetermined period of time, if the switch moves from a first position to a second position.

2008-10-30

20080265977

High isolation electronic multiple pole multiple throw switch - A high isolation electronic multiple pole multiple throw (MPNT) switching device is formed as a ring circuit that includes plural poles, plural throws, plural series switches and plural means for shunting. Each series switch receives a control signal, and each means for shunting receives shunt control signals. In one aspect, the shunt control signals include control signals received by distant series switches. In another aspect, the shunt control signals include control signals received by adjacent series switches. In another aspect, the shunt control signals include signals complementary to signals received by adjacent series switches. In another aspect, the shunt control signals include pole DC potentials or throw DC potentials. In another aspect, a switching device may operate in multiple transmission mode or multiple input multiple output (MIMO) mode. The MPNT switching device provides low insertion loss and high isolation at a wide range of frequencies.

2008-10-30

20080265978

Tuning capacitance to enhance FET stack voltage withstand - An RF switch to controllably withstand an applied RF voltage Vsw, or a method of fabricating such a switch, which includes a string of series-connected constituent FETs with a node of the string between each pair of adjacent FETs. The method includes controlling capacitances between different nodes of the string to effectively tune the string capacitively, which will reduce the variance in the RF switch voltage distributed across each constituent FET, thereby enhancing switch breakdown voltage. Capacitances are controlled, for example, by disposing capacitive features between nodes of the string, and/or by varying design parameters of different constituent FETs. For each node, a sum of products of each significant capacitor by a proportion of Vsw appearing across it may be controlled to approximately zero.

2008-10-30

20080265979

Control apparatus - A control apparatus comprises a voltage source, a controlling unit and an enabling unit. The controlling unit is coupled to the voltage source for receiving an input signal and generating an output signal. The enabling unit is coupled to the voltage source, the controlling unit and a ground terminal for controlling whether the controlling unit generates the output signal or not according to an enabling signal. The enabling unit comprises a first switch, a second resistor, a third resistor and a third transistor. The first switch is used for selectively turning on or off according to the enabling signal. A first terminal of the second resistor is coupled to the first switch. A first terminal of the third resistor is coupled to a second terminal of the second resistor and a second terminal of the third resistor is coupled to the ground terminal. A source of the third transistor is coupled to the ground terminal and a gate of the third transistor is coupled between the second and the third resistor.

2008-10-30

20080265980

Gate drive for wide bandgap semiconductor device - A gate drive circuit for a wide bandgap semiconductor junction gated transistor includes a gate current limit resistor. The gate current limit resistor is coupled to a gate input of the wide bandgap semiconductor junction gated transistor when in use and limits a gate current provided to the gate input of the junction gated transistor. An AC-coupled charging capacitor is also included in the gate drive circuit. The AC-coupled charging capacitor is coupled to the gate input of the wide bandgap semiconductor junction gated transistor when in use and is positioned parallel to the gate current limit resistor. A diode is coupled to the gate current limit resistor and the AC-coupled charging capacitor on one end and an output of a gate drive chip on the other end When in use, the diode lowers a gate voltage output from the gate drive chip applied to the gate input of the wide bandgap semiconductor junction gated transistor through the gate current limit resistor. The gate drive circuitry provides a small, efficient, and cost effective control circuitry for a wide bandgap semiconductor junction gated transistor.

METHOD OF IMPROVING FUSE STATE DETECTION AND YIELD IN SEMICONDUCTOR APPLICATIONS - Disclosed are embodiments of an apparatus incorporating a detection circuit adapted for determining the state of selected fuses and a programming circuit for blowing selected fuses on demand. Also, disclosed are embodiments of an associated method. The detection circuit comprises a plurality of fuses in identical signal and reference legs in order to increase the signal margin for detecting blown fuses and/or current sources configured to pass offset currents through the signal and reference legs in order to set the trip point for detecting blown fuses between the un-blown and the minimum blown resistances. Thus, the invention provides the flexibility of single-sided fuse state detection devices with even greater sensitivity than both single-sided and differential fuse state detection device.

2008-10-30

20080265983

METHODS TO REDUCE THRESHOLD VOLTAGE TOLERANCE AND SKEW IN MULTI-THRESHOLD VOLTAGE APPLICATIONS - A circuit and a method for adjusting the performance of an integrated circuit, the method includes: comprising: (a) measuring the performance of a first monitor circuit having at least one field effect transistor (FET) of a first set of FETs, each FET of the first set of FETs having a designed first threshold voltage; (b) measuring the performance of a second monitor circuit having at least one field effect transistor (FET) of a second set of FETs, each FET of the second set of FETs having a designed second threshold voltage, the second threshold voltage different from the first threshold voltage; and (c) applying a bias voltage to wells of the FETs of the second set of FETs based on comparing a measured performance of the first and second monitor circuits to specified performances of the first and second monitor circuits.

2008-10-30

20080265984

OVER-VOLTAGE PROTECTION FOR POWER AND DATA APPLICATIONS - A power supply device is described comprising a DC voltage supply, a power section connected to the DC supply for supplying DC power from the DC voltage supply to first and second outlet ports for connection to a remote device via a cable connection, a voltage boosting circuit for generating a voltage above that of the DC supply, an energy absorbing circuit connected between an output of the voltage boosting circuit and a ground potential, and a diode connection means between the first outlet port and the energy absorbing circuit. The major components of the power supply device may be implemented as an integrated circuit.

High-Speed Receiver Assembly - A high-speed receiver suitable for applications that desire a common-mode voltage range from approximately 0.7V to approximately 0.9V is arranged by coupling first and second differential pair circuit architectures based on first and second current-steering schemes into the same path to generate an output signal. The high-speed receiver includes first and second differential pair circuits. The first differential pair circuit is coupled to a first current-steering path via a first port and a second current-steering path via a second port. The second differential pair circuit is coupled to the first current-steering path via a third port and the second current-steering path via a fourth port. A bridge circuit is interposed between the first and second differential pair circuits. The bridge circuit integrates the first and second current-steering paths in a single-stage of the high-speed receiver assembly.

2008-10-30

20080265987

SIGNAL EXTRACTION CIRCUIT - A shunt regulator performs a control so as to stabilize a voltage obtained by rectifying the radio frequency signal output from an antenna unit at a prescribed voltage value. A signal extraction unit extracts the information signal from a bypass current sent by the shunt regulator for the control when the voltage fluctuates.

Filterless class-D speaker driver with less switching - Methods for designing a filterless class-D amplifier and driver are described herein. In the exemplary embodiment, a feedback loop is used to stabilize the filterless class-D amplifier. A pulse width modulated (PWM) output signal is generated by adding a comparator input signal to a comparative signal, and comparing the sum to a peak voltage, which can be a peak value of the comparative signal. A limit of one PWM sample will be generated half per period of the comparative signal, resulting in lower dynamic switching noise and a decreased sensitivity to jitter noise than conventional filterless class-D amplifiers.

2008-10-30

20080265990

Semiconductor circuit - An amplifier includes differential output and input stages. The differential output stage includes first and second current paths outputting differential signals and connected between first and second power supplies. The first current path includes a first resistance between the first power supply and a first node, first and second transistors between the first node and a second node, and a second resistance between the second node and the second power supply. The second current path includes a third resistance between the first power supply and a third node, third and fourth transistors between the third node and a fourth node, and a fourth resistance between the fourth node and the second power supply. Each gate of the first to fourth transistors is connected to each of the fourth to first nodes, respectively, and output current of the differential input stage is connected to the first and third nodes.

2008-10-30

20080265991

Gain control module and applications thereof - A gain control module includes an amplifier, a least significant bit (LSB) gain stage, and a most significant bit (MSB) gain stage. The amplifier includes a first input, a second input, and an output. The LSB gain stage produces a LSB gain based on an LSB portion of a gain control signal, wherein the LSB gain stage receives an input signal. The MSB gain stage produces an MSB gain based on an MSB portion of the gain control signal, wherein the MSB gain stage is coupled to the LSB gain stage, the first input of the amplifier, and the output of the amplifier, wherein the gain control module amplifies the input signal in accordance with the gain control signal.

2008-10-30

20080265992

Transconductance Stage Arrangement - The present invention relates to a voltage-to-current transconductance stage arrangement comprising a single-ended input, an emitter-coupled pair of transistors, comprising a first transistor and a second transistor, the emitter of a third transistor, being connected to the collector of said first transistor, and differential output. It further comprises at least one common-collector transistor comprising a fourth transistor connected to the base of said second transistor preferably or optionally also and a fifth transistor connected to the base of said third transistor. The size of said fourth, or fourth and fifth transistors considerably exceed the sizes of said second and third transistors. They are biased at ‘off-state’. An extra inductor at the collector of the transistor may be applied to further increase linearity.

2008-10-30

20080265993

Class AB Rail-to-Rail Input and Output Operational Amplifier - An operational amplifier including an input stage. The input stage may include first and second differential input circuits and a first current mirror. When an input terminal of the operational amplifier is at a positive voltage rail, the first differential input circuit may be activated. When the input terminal is at a negative voltage rail, the second differential input circuit may be activated. In either case, this may cause the first current mirror to provide a current of a predetermined value to each of first and second input terminals of a control circuit, and to each of first and second nodes coupled to a rail-to-rail output stage. The input stage may maintain the current provided to each of the input terminals of the control circuit and to each of the nodes coupled to the rail-to-rail output stage constant over the full input voltage range from the negative voltage rail to the positive voltage rail.

2008-10-30

20080265994

VARIABLE GAIN AMPLIFYING APPARATUS AND WIRELESS COMMUNICATION APPARATUS - A variable gain amplifying apparatus has an amplifier, one or more first switching elements connected in parallel to the amplifier, and a phase shifter connected in series to the first switching element. The first switching element is enabled if the level of an input signal or an output signal is higher than a predetermined level, and the first switching element is disabled if the level of the input signal or the output signal is equal to or lower than the predetermined level. The amplifier does not operate when the first switching element is enabled, and the amplifier operates when the first switching element is disabled, and the amount of phase shift when the input signal is passed through the amplifier and phase shifter is substantially equal to the amount of phase shift when the input signal is passed through the first switching element.

2008-10-30

20080265995

AMPLIFIER CIRCUIT AND WIRELESS COMMUNICATION DEVICE - An amplifier circuit has a current conversion circuit that receives a high frequency signal and produces a signal current according to the high frequency signal; a gain control circuit that includes a control signal input for receiving a control signal, a first output, and a second output, and produces the signal current from the first output or the second output according to the control signal; an impedance circuit that includes a first node connected to the first output, a second node connected to the second output, and a third node, the impedance circuit presenting a predetermined impedance between the nodes; a switch circuit that is inserted between the first output and the first node; and a load impedance unit that is connected to the first output and produces a gain signal representing an amplified high frequency signal.

2008-10-30

20080265996

Digital Hybrid Mode Power Amplifier System - A RF-digital hybrid mode power amplifier system for achieving high efficiency and high linearity in wideband communication systems is disclosed. The present invention is based on the method of adaptive digital predistortion to linearize a power amplifier in the RF domain. The power amplifier characteristics such as variation of linearity and asymmetric distortion of the amplifier output signal are monitored by the narrowband feedback path and controlled by the adaptation algorithm in a digital module. Therefore, the present invention could compensate the nonlinearities as well as memory effects of the power amplifier systems and also improve performances, in terms of power added efficiency, adjacent channel leakage ratio and peak-to-average power ratio. The present disclosure enables a power amplifier system to be field reconfigurable and support multi-modulation schemes (modulation agnostic), multi-carriers and multi-channels. As a result, the digital hybrid mode power amplifier system is particularly suitable for wireless transmission systems, such as base-stations, repeaters, and indoor signal coverage systems, where baseband I-Q signal information is not readily available.

DUAL PLL LOOP FOR PHASE NOISE FILTERING - System for filtering an input frequency to produce an output frequency having low phase noise. A first PLL includes, in the feedback path, a frequency translation circuit which translates a frequency from a VCO in the first PLL by an offset frequency provided by the second PLL to provide either a sum or difference frequency. The first PLL locks its VCO to a crystal oscillator input frequency translated by the offset frequency due to the frequency translation circuit. A second PLL compares the input frequency to be filtered to the output of the first PLL VCO. The second PLL causes the first PLL VCO to lock to the input frequency by varying the offset frequency it provides to the frequency translation circuit. The bandwidth of the second PLL is significantly smaller than the bandwidth of the first PLL. The filtered output frequency is available from the first PLL VCO.

2008-10-30

20080265999

RADIATION SOURCE - A source of radiation comprises a first low frequency oscillator

2008-10-30

20080266000

Digital Frequency Multiplier Circuit - A digital frequency multiplier circuit is disclosed. The digital frequency multiplier circuit includes a digitally controlled oscillator (DCO), a phase detector and a control circuit. The DCO generates an internal feedback signal. The phase detector detects a phase difference between the internal feedback signal and an external reference clock signal. Coupled between the phase detector and the DCO, the control circuit adjusts the DCO to align the internal feedback signal with the external reference clock signal after a phase difference between the internal feedback signal and the external reference clock signal has been detected. The control circuit also locks a modulation frequency of the DCO and monitors the state of the digital frequency multiplier circuit in order to maintain the lock.

2008-10-30

20080266001

DUAL REFERENCE PHASE TRACKING PHASE-LOCKED LOOP - A phase-locked loop circuit having a dual-reference input and a phase detector. The dual-reference input is configured to accept both a rising edge of an input clock having a first phase and a falling edge of the input clock having a second phase. The phase detector is coupled to the dual-reference input and is configured to produce a center phase signal based upon and centered in phase between the first and second phases. The phase detector is further configured with a feedback loop to adjust any tracking error and provide a tracking output signal. The phase detector system maintains both a high tracking bandwidth and a bounded jitter amplification based as a result of the dual reference signal. The high tracking bandwidth and the bounded jitter amplification are independent of an applied loop gain.

2008-10-30

20080266002

FREQUENCY SYNTHESIZER - A frequency synthesizer. The frequency synthesizer comprises a harmonic locked phase/frequency detector, a low pass filter, a voltage controlled oscillator, and a frequency divider. The harmonic locked phase/frequency detector receives a reference signal and a divided signal. The low pass filter is coupled to the harmonic locked phase/frequency detector. The voltage controlled oscillator is coupled to the low pass filter and provides an output signal. The frequency divider is coupled between the voltage controlled oscillator and the harmonic locked phase/frequency detector. Frequency of the divided signal is a harmonic frequency of the reference signal.

2008-10-30

20080266003

SURFACE-MOUNTED PIEZOELECTRIC OSCILLATORS AND PIEZOELECTRIC VIBRATORS - Surface-mounted piezoelectric oscillators are disclosed that include a package in which a piezoelectric vibrating piece and an electronic circuit (IC) are mounted. At least two external terminals are formed on the external surface of the package and electrically connected to the piezoelectric vibration piece and the electronic circuit. The front surfaces of the external terminals are recessed inwardly (AZ) from the external surface of the package.

Automatically Tuned Tail Filter - The present invention relates to an oscillating circuit arrangement having a resonating arrangement with a first resonance frequency (coo) comprising a voltage controlled oscillator arrangement. It further comprises a tunable filter arrangement connected to the source node of said voltage controlled oscillator (VCO) arrangement. Said filter arrangement particularly comprises an equivalent current source resonating at a second resonance frequency cθf, the second resonance frequency being a multiple n, n=1 or 2 of said first resonance frequency (α>o), n being equal to the minimum number of switch transistors required for oscillation of said VCO arrangement. The filter arrangement particularly comprises an inductor connected in parallel with a capacitor, said capacitor being adapted to be tunable such that the phase noise of the resonating arrangement can be minimized through tuning of the filter arrangement.

2008-10-30

20080266006

VOLTAGE CONTROLLED OSCILLATOR WITH SWITCHING BIAS - Provided is a voltage controlled oscillator to which a switching bias technique is applied so as to lower flicker noise of a bias circuit and enhance phase noise characteristics, thereby reducing the overall chip area to make it possible to achieve integration. A common mode voltage applied to the bias circuit is negatively fed back to an oscillation waveform. Therefore, it is possible to stabilize the magnitude of the oscillation waveform of the voltage controlled oscillator with respect to a change in an external condition.

2008-10-30

20080266007

OSCILLATING APPARATUS HAVING CURRENT COMPENSATING DEVICE FOR PROVIDING COMPENSATING CURRENT TO COMPENSATE FOR CURRENT REDUCTION OF TRANSCONDUCTIVE DEVICE AND METHOD THEREOF - According to an embodiment of the present invention, an oscillating apparatus is provided. The oscillating apparatus generates an oscillating signal, and the oscillating apparatus includes a resonating device, a transconductive device, a biasing device, and a current compensating device. The resonating device generates the oscillating signal; the transconductive device is coupled to the resonating device for providing the resonating device with a positive feedback loop; the biasing device is coupled to the transconductive device for providing the transconductive device with a biasing current; and the current compensating device is coupled between the resonating device and the biasing device for providing the biasing device with a compensating current to compensate for a current reduction of the transconductive device.

2008-10-30

20080266008

ELECTROMECHANICAL RESONATOR AND MANUFACTURING METHOD THEREOF - An electromechanical resonator includes a resonator portion which includes a fixed electrode and an oscillator formed separately from the fixed electrode with a gap. The gap has a first gap region and a second gap region which are arranged in a thickness direction of the fixed electrode. The first gap region is different in width from the second gap region.

2008-10-30

20080266009

Ultra-low power crystal oscillator - An ultra-low power crystal oscillator architecture that draws less than 2 μA during steady state operation. An amplifier stage is self biased and has input and output clamp circuits that limit its signal swing. Circuit values are selected such that there is sufficient transient load current for the first amplifier stage to oscillate, while at the same time the input and output clamp circuits maintain a sufficiently low swing of the stage such that the steady state average load current is on the order of less than 1 μA.

2008-10-30

20080266010

Semiconductor device and driving method thereof - A low-power-consumption semiconductor device and a driving method thereof where a clock signal generation is controlled. A transmission and reception control circuit to control signal communication with an outside; a ring oscillator control circuit to detect an edge in a receiving signal and control a ring oscillator; a clock generation circuit to generate a clock signal based on the ring oscillator; and a logic circuit to operate based on a clock signal are included. During signal communication between the transmission and reception control circuit and the outside, the ring oscillator operates and a clock signal is output from the clock generation circuit when the ring oscillator control circuit detects an edge in a receiving signal, and the ring oscillator stops and output of the clock signal from the clock generation circuit stops when transmission of a reply signal from the transmission and reception control circuit to the outside is terminated.

2008-10-30

20080266011

Oscillator signal stabilization - An oscillator signal stabilization method is provided for a radio transceiver, for example. In the present stabilization method, amplitude variation of a radio frequency oscillator signal generated by a frequency-adjustable oscillator signal generator is stabilized in an adaptive compensation circuit having adjustable compensation parameters. The stabilized oscillator signal is fed from the compensation circuit to one or more frequency dividers for frequency division. The compensation circuit is configured to stabilize signal variations caused by component non-idealities and, thereby, prevent undesired frequency division errors in the frequency dividers.

2008-10-30

20080266012

METHOD FOR CONTROLLING HIGH-FREQUENCY RADIATOR - A method for controlling a high-frequency radiator includes the steps of: (a) applying a high-frequency radiation through the solid-state oscillator and the antenna; (b) sensing part of the high-frequency radiation returned from the antenna to the solid-state oscillator; (c) adjusting radiation/propagation conditions for the high-frequency radiation on the basis of the sensed results in the step (b), the high-frequency radiation propagating from the solid-state oscillator to the antenna; and (d) after the step (c), applying the high-frequency radiation through the solid-state oscillator and the antenna to a target object. In the step (c), the oscillation frequency of the solid-state oscillator, the power of the high-frequency radiation applied by the solid-state oscillator, the power supply voltage supplied to the solid-state oscillator, the impedance match between the output impedance of the solid-state oscillator and the impedance of the antenna, or any other condition is changed.

ON-OFF KEYING - 7-PHASE SHIFT KEYING MODULATION SYSTEM AND METHOD FOR FIBER COMMUNICATION - A modulation system includes a modulator configured to employ a modulation mechanism on data. The mechanism includes a signal constellation configured to map sub-carriers which include a signal to be modulated. The signal constellation has a plurality of points asymmetrically disposed on a circle about an origin and a point at the origin wherein a number of sub-carriers becomes variable over different symbol intervals. Corresponding demodulators and corresponding methods are also disclosed.

2008-10-30

20080266015

Polar Modulation Apparatus and Method Using Fm Modulation - The present invention relates to a polar modulation apparatus and method, in which an in-phase and a quadrature-phase signal are processed in the analog domain to generate an analog signal corresponding to a derivative of a phase component of said polar-modulated signal. The analog signal is then input to a control input of a controlled oscillator (

2008-10-30

20080266016

Semiconductor Switch with Integrated Delay Circuit - For controlling a multi-stage load with pulsewidth modulation (PWM), the individual stages have normally separately applied thereto load currents which are clocked in a phase-shifted mode so as to avoid load peaks. An output stage for PWM control of a load stage with a delay circuit which, in addition to the load current modulated by a PWM input signal, supplies a PWM output signal that is delayed by a predetermined fraction of the period duration relative to the PWM input signal. The output stage can especially be realized by integrating the delay circuit together with the actual power semiconductor switch and an associated monitoring and control circuit in a single component. By cascading such output stages, a controller for phase-shifted PWM control of multi-stage loads, which is independent of a precise time base, can be realized in a simple manner.

Electromagnetic bandgap structure and printed circuit board - An electromagnetic bandgap structure and a printed circuit board that can solve a mixed signal problem between an analog circuit and a digital circuit are disclosed. In accordance with an embodiment of the present invention, the electromagnetic bandgap structure can include a metal layer; and a plurality of mushroom type structures including a metal plate and a via. Here, the plurality of mushroom type structures can be formed on the metal layer in a stacked structure. With the present invention, the small sized electromagnetic bandgap structure can have a lower bandgap frequency.

2008-10-30

20080266019

DIFFERENTIAL TRANSMISSION LINE - A differential transmission line that has three or more signal lines and with which there is little unwanted radiation noise is provided. The differential transmission line

2008-10-30

20080266020

Balanced Splitter - A balanced splitter has six ¼ strip lines. The first and third strip lines are electromagnetically coupled to each other to form a coupler. The second and fourth strip lines are electromagnetically coupled to each other to form a coupler. The first and fifth strip lines are electromagnetically coupled to each other to form a coupler. The second and sixth strip lines are electromagnetically coupled to each other to form a coupler. The first and second strip lines are connected in series to form an unbalanced line, the third and fourth strip lines form a first balanced line, and the fifth and sixth strip lines form a second balanced line. First and second resistors are electrically connected between a first balanced terminal and a second balanced terminal, and between another first balanced terminal and another second balanced terminal, respectively.

2008-10-30

20080266021

Impedance Detector - The invention relates to an antenna which is coupled to an RF amplifier. Environmental conditions change the impedance of the antenna, which reduces output power, efficiency and linearity. A circuit is provided which is designed to detect the impedance of the antenna. With the measured impedance, impedance matching can be accomplished. The circuit for detecting the impedance detects the signal travelling from the RF amplifier to the antenna, and measures the peak voltage and the peak current of this signal. Furthermore, the phase difference between the voltage and the current is measured. The advantage of the circuit is its compactness allowing for an easy integration on a chip. Furthermore, an impedance matching circuit is suggested which makes use of the above circuit for detecting the impedance.

2008-10-30

20080266022

RF BACKSCATTER TRANSMISSION WITH ZERO DC POWER CONSUMPTION - A method for minimizing power consumption in a wireless device which utilizes backscatter transmission in half-duplex mode, wherein a switching device is interposed between an antenna and a transmitter-receiver, and the switching device is capable of causing the antenna load impedance characteristic to be either a short, a value which substantially matches the antenna impedance, or an open, depending on the portion of the half-duplex mode.

2008-10-30

20080266023

SURFACE ACOUSTIC WAVE DEVICE AND BOUNDARY ACOUSTIC WAVE DEVICE - A piezoelectric substrate is joined to a cover with a support layer disposed therebetween and with a space maintained therebetween. A transmission surface acoustic wave filter and a reception surface acoustic wave filter are disposed on a major surface of the piezoelectric substrate adjacent to the cover and inside the support layer. External electrodes are provided on the side of the cover opposite to the side facing the piezoelectric substrate. The external electrodes include an antenna terminal electrically connected to the transmission surface acoustic wave filter and the reception surface acoustic wave filter, a transmission input terminal electrically connected to the transmission surface acoustic wave filter, and a reception output terminal electrically connected to the reception surface acoustic wave filter. A portion of an interconnection line that electrically connects the reception surface acoustic wave filter to the antenna terminal is disposed on the cover.

2008-10-30

20080266024

Component Operated by Guided Acoustic Waves - A component working with guided acoustic waves includes a layer system configured to guide waves in a lateral plane. The layer system includes a piezoelectric layer, electrodes on the piezoelectric layer for exciting the wave, a dielectric layer with an acoustic impedance, and an adjustment layer with an acoustic impedance. A ratio of the acoustic impedance of the adjustment layer to the acoustic impedance of the dielectric layer is greater than 1.5.

2008-10-30

20080266025

Power line communications device with auxiliary filtered power output - A power line communications device with auxiliary filtered power output is disclosed which permits the coverage of a power line communications, PLC, system to be widely extended by means of using a high-impedance filter integrated into the actual communications equipment, in such a way that avoids the problems inherent to the use of PLC technology in an adverse environment such as that which results from connection of electrical apparatus in the same socket as power line communications equipment.

2008-10-30

20080266026

Electromagnetic bandgap structure and printed circuit board - An electromagnetic bandgap structure and a printed circuit board that can solve a mixed signal problem between an analog circuit and a digital circuit are disclosed. In accordance with an embodiment of the present invention, the electromagnetic bandgap structure can include a first metal layer; a first dielectric layer, stacked in the first metal layer; a metal plate, stacked in the first dielectric layer; a via, connecting the first metal layer to the metal plate; a second dielectric layer, stacked in the metal plate and the first dielectric layer; and a second metal layer, stacked in the second dielectric layer. Here, a hole can be formed on the metal plate. With the present invention, the electromagnetic bandgap structure can lower a noise level more within the same frequency band as compared with other structures having the same size.

2008-10-30

20080266027

LONGITUDINALLY-COUPLED-RESONATOR-TYPE ELASTIC WAVE FILTER DEVICE - In a longitudinally-coupled-resonator-type elastic wave filter device, at least one of two IDTs which are adjacent to each other is provided with a dummy electrode for series weighting in a portion in which the IDTs are adjacent to each other, and at least one of series-weighted portions includes at least one of metallization ratio reducing portion in a first acoustic track and metallization ratio increasing portion in a second acoustic track so as to reduce the difference between the metallization ratio of the first acoustic track passing through a connecting portion of the dummy electrode and the metallization ratio of each of second and third acoustic tracks each placed on either side of the first acoustic track in the direction of propagation of an elastic wave.

2008-10-30

20080266028

Enhanced Substrate Using Metamaterials - In enhancing signal quality through packages, meta-materials may be used. Meta-materials are designed to make the signal act in such a way as to make the shape of the signal behave as though the permittivity and permeability are different than the real permittivity and permeability of the insulator used. In an example embodiment, a substrate (

2008-10-30

20080266029

VARIABLE FILTER ELEMENT, VARIABLE FILTER MODULE AND FABRICATION METHOD THEREOF - A variable filter element and a variable filter module suitable for decreasing the drive voltage are provided. The variable filter element includes a substrate, two ground lines and a signal line between the ground lines, where these lines are disposed to extend in parallel on the substrate. The filter element further includes movable capacitor electrodes which bridge between the ground lines and have portions facing the signal line, drive electrodes which are located between the signal line and the ground lines and generate electrostatic attraction with the movable capacitor electrodes, and a ground line, which is disposed in the substrate, has a portion facing the signal line, and is electrically connected with the ground. The variable capacitor electrodes and the ground line constitute ground interconnection portions, and the signal line and ground interconnection portion constitute a distributed constant transmission line.

2008-10-30

20080266030

Coaxial resonator - A coaxial resonator includes a core of dielectric material. A through-hole defines respective openings in the top and bottom surfaces of the core. The top surface further defines at least first and second metallized regions surrounding the through-hole opening and an unmetallized region therebetween. The first metallized region defines a resonator pad. An isolated metallized region on at least one of the side surfaces defines an input/output electrode. In one embodiment, one of the metallized regions on the top surface and the electrode define interdigitated fingers on the top surface. In another embodiment, the pad defines outwardly projecting corner ears and both the second metallized region and electrode define fingers protruding between the ears. In a further embodiment, the electrode extends across at least two of the side surfaces.

2008-10-30

20080266031

SEMICONDUCTOR DEVICE AND WIRING PART THEREOF - A technique capable of achieving both improvement of mounting density and noise reduction for a semiconductor device is provided. An LSI mounted on a printed wiring board comprises a grounding BGA ball and a power BGA ball to get power supply from the printed wiring board, and the grounding BGA ball and the power BGA ball are arranged closely to each other. A decoupling capacitor is mounted on the printed wiring board and has a first terminal and a second terminal. The grounding BGA ball and the first terminal are connected by a first metal electrode plate, and the power BGA ball and the second terminal are connected by a second metal electrode plate. The first metal electrode plate and the second metal electrode plate interpose a dielectric film having a thickness equal to or smaller than 1 μm therebetween.

LOW-NOISE FINE-FREQUENCY TUNING - Circuits, methods, apparatus, and code that provide low-noise and high-resolution electronic circuit tuning. An exemplary embodiment of the present invention adjusts a capacitance value by pulse-width modulating a control voltage for a switch in series with a capacitor. The pulse-width-modulated control signal can be adjusted using entry values found in a lookup table, by using analog or digital control signals, or by using other appropriate methods. The capacitance value tunes a frequency response or characteristic of an electronic circuit. The response can be made to be insensitive to conditions such as temperature, power supply voltage, or processing.

2008-10-30

20080266035

MAGNETIC PROXIMITY SENSOR - A magnetic proximity sensor includes first and second contacts and a common contact and an actuator shaft, wherein the position of the common contact is determined by the position of the shaft, but the force between the contacts is independent of the position of the shaft.

2008-10-30

20080266036

Magnetostriction aided switching - A method for reducing a temperature rise of a magnetic material is provided. The method includes applying force to the magnetic material to reduce a dimensional change of the magnetic material during a first part of an operation cycle, such as due to magnetostriction. The force is removed from the magnetic material during a second part of an operation cycle, allowing magnetostrictive dimensional changes to occur.

2008-10-30

20080266037

Magnetic Levitation Lithography Apparatus and Method - A magnetic levitation lithography machine having a low spring stiffness to minimize disturbances of the first structure and which is capable of dynamically controlling the first structure in one or more degrees of freedom. The machine includes a radiation source, a patterning element configured to define a pattern, a projection element, the projection element configured to project the pattern onto a substrate when radiation from the radiation source is projected through the projection element; and a substrate take configured to support the substrate. The substrate take includes a second structure, a fine stage, and a magnetic support configured to support the fine stage adjacent the second structure. The magnetic support includes a first magnet element, coupled to the fine stage, having a first magnet polarization, a second magnet element, coupled to the course stage, having a second magnet polarization, the first magnet element being separated from the second magnet element by a gap, and an adjustment mechanism configured to adjust the magnetic force used to support the fine stage by varying the gap between the first magnet element and the second magnet element.

2008-10-30

20080266038

SOLENOID ASSEMBLY - A solenoid assembly for use in connection with a housing and valve body is provided. The assembly includes a magnetic coil, a magnetic pole piece, an operating rod, and a magnetic armature. The operating rod is slidably disposed within a portion of the pole piece and is at least in part centered relative to the pole piece. Activation of the coil provides an attraction between the armature and the pole piece. An embodiment of the assembly may additionally include one or more bearings positioned between the operating rod and the pole piece.

2008-10-30

20080266039

Magnet System for an Electrical Actuator - A magnet system for an electrical actuator includes a substantially U-shaped magnet yoke having substantially parallel first and second pole legs connected by a yoke web. The first pole leg has a longitudinal end section bent out of a plane of the first pole leg. A longitudinal side of the longitudinal end section forms a first magnet pole. The second pole leg has an end face forming a second magnet pole.

2008-10-30

20080266040

Ignition coil - A high-strength ignition coil that can prevent distortion arising from pin marks formed on a surface of a core and makes it less likely for insulating resin to be cracked. The coil assembly is housed in a coil case. A casting material is filled into a gap between the coil case and the coil assembly and gaps which the coil assembly has. The coil assembly is comprised of a coil pair including a cylindrical primary coil and a secondary coil disposed concentrically with the primary coil, and a core. The core is fitted into a central space of the coil pair and forms a magnetic path. The core is coated with mold resin. Concave portions of pin marks formed on a mold resin coating by removal of core fixing pins when the mold resin coating is formed are filled with mold resin.