FPGA are great platform to learn and practice design skills but be fully aware that ASIC requires some extra work that is not exposed to designers in FPGA world

Majority of the design bugs are still functional bugs despite increasing complexity of the CMOS technology

Any software engineer can write verilog (its almost like C anyways) until they hear about CLOCK

8Skills Development (Cont.)

PERL (If you have not heard of it, please google it right away if you ever plan to design chips)

Same for TCL

Some aspects of software development process are relevant to chips as well (Version Control, Build Process, Bug Tracking etc.)

Finally, knowledge of end-user application will make you better architects

9Design Tools

Hammer, Wrench and Pliers

EDA world inhabited by superb software engineers who like to create smart algorithms and innovative UI but they rarely design chips

No set of tools will let you build chips just using the tools alone i.e. it is inevitable that you will need to build some custom scripts, tools to patch together a flow

With evolution of technology, some of the concerns like signal integrity or power grid design etc now require as much attention as gates

10Intellectual Property

Holy Grail of modern chip design is the assembling them like Lego bricks using pre-existing sub modules

In no chip has it worked that way, unless a particular IP has been used and built into working silicon already

Intellectual Property does not equal RTL code!

Despite all these problems, no SoC is ever built from scratch.

11Business model

Section II

12End Markets

3 Cs (Computers, Communications, and Consumer)

Industrial and Automations is also a significant users

Migration to CMOS for digital design as well as for other technologies like RF or Image Sensor

Mixed signal chips in wireless world

More and more applications are implemented using digital (Audio, Video, Motor Control, etc)

13Integrated Device Manufacturer

Chips, screws, boxes and software (IBM, DEC)

Today even design, manufacture and marketing of chips is rarely done by same company (Intel)

Fabless Model is well developed and has proven successful

EDA model is somewhat successful and IP business model is questionable

14ASIC vs FPGA

Number of design starts every year are shrinking, esp in recession

FPGAs are attractive alternative for any markets not requiring strict power, cost and size budgets

High volume markets still require custom ASICs

FPGAs are now able to meet fairly high performance requirements networking gear is an ideal market for them

15Best of both worlds??

How about programmable array on a custom ASIC

May be appropriate for some niche markets

The design starts are decreasing but the design teams needed to execute very large chips (afforded by more available transistors) on latest technology node requires large design teams

16GHz, now it really hurts!

Until the beginning of this decade there was an implicit GHz race among high-performance chip makers but soon the lesson was learned that even if technically feasible it is not the right way to performance

Multi-core is the new new thing, if you have not read any research from 20 yrs ago

In any case, mobile phone processors are not at 1 GHz and possibly 2 or 4 cores on the die

17Memory, IO and Usability

DDR, Flash

USB, PCI Express

Hot plugged, power managed and auto-configured IO

All IO technologies now serial (LVDS) instead of wide parallel CMOS

Still there are too many to choose from

18Semiconductor Market

300bn per year

Majority of it is digital IC

IDMs still sell lot of standard parts like micro-controllers, memories etc but fabless is not becoming larger and larger part of the market

Eventually, standard parts will be needed for specialty markets like industrial, automotive, power, sensors, control etc but rest will be digital CMOS and very likely fabless

19Newer Markets or More Integration?

Health Care, Biomedical, Renewable Energy (Solar Cells etc.)

LCD, LED, OLED displays

Laser projectors

3 Cs will remain significant users of standard CMOS digital semiconductor but may become commoditized

Innovations will be sector(application) specific

20EDA and IP

ARM is the only surviving IP company of significant size

Despite superficial similarities, Software business model does not transplant to chip design

Indian engineers and manufacturers can no longer live in splendid isolation

28To design, to make or to service?

India has sadly missed the boat on manufacturing semiconductors (even if 5 bn fab can erected, it is impossible to keep it fed)

Design Services low margin, cyclical business that does not scale

Design aka fabless is fairly reliable business model (although comparatively costly) Costs can be mitigated by doing all engineering work in India

29Test and Assembly

There is an opportunity here

Lacking manufacturing capability is a bit disadvantage but english-speaking skilled work force is a plus

Maturing industry will fragment further and will look for cheaper destinations

If India can successfully create a fabless industry, it would match chinas manufacturing capability and will be complementary

30Questions

Fabless Semiconductor Association (recently changed name)

Latest scoop on tools deepchip.com (John Cooley)

Eetimes.com, electronicnews.com

CMOS VLSI Design (Neil Weste)

Intel Technology Journal

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