In the old days, TSMC made a big toolflow announcement every year at DAC, and hosted a lively ‘partner pavilion’ where dozens of companies were showcased in small auxiliary booths that stood in addition to their conventional booths elsewhere in the Exhibit Hall.

At DAC 2103 in Austin, however, something different is happening. Hosted by GlobalFoundries, this year’s ‘foundry pavilion’ will showcase countries, not corporations: “The DAC Global Forum celebrates contributions and future plans of nations around the globe to the field of electronic design in past (sic) 50 years.” Should be very interesting; check out Booth #137 in Austin.

In the meanwhile, TSMC’s taking this week prior to DAC 2013 to announce various tool certifications, including FinFET v0.1 design enablement: “The tool certification serves as the foundation of design infrastructure for 16-nanometer FinFET technology.”

It’s always fun to read through these types of joint announcements, at least if you’re easily amused by the exercise of comparing the quotes embedded in dueling Press Releases. TSMC Senior Director Suk Lee, for instance, is quoted in all four press releases paraphrased below, sent out this week from ATopTech, Cadence, Mentor, and Synopsys.

**ATopTech announced that Aprisa and Apogee have been certified by TSMC for 16nm FinFET v0.1 design enablement. Aprisa and Apogee were certified in October 2012 by TSMC for 20nm design enablement with double patterning technology (DPT) routing rule support for TSMC’s 20nm reference flow.

Aprisa and Apogee have subsequently gone through a rigorous 16nm FinFET certification process that includes signoff correlation checking of DRC, LVS, and formal verification to fulfill new process requirements such as new design rules for P-80 layers, 16nm FinFET transistor-related placement rules, and DFM requirements.

Jue-Hsien Chern, CEO of ATopTech, is quoted in the Press Release: “ATopTech’s technologies were purposed for just such advanced process technologies as TSMC 16nm FinFET. This close collaboration with TSMC further enables our joint customers to take full advantage of the TSMC advanced technology for better product competitiveness.”

**Cadence Design Systems announced that several of its SoC development tools have achieved version 0.1 of design rule manual (DRM) and SPICE model tool certification for TSMC’s 16-nanometer FinFET process. The companies say completion of the early stage tool certification milestone means advanced node customers can start developing designs and leveraging the lower power and higher performance benefits required for next-generation mobile platforms.

The certified Cadence tools are Spectre, Liberate, Virtuoso, Encounter Digital Implementation (EDI) System, Encounter Timing System, Virtuoso Power System, Encounter Power System, Physical Verification System and QRC Extraction. Several Cadence design IP offerings are also available for customer test chips at this advanced node. Cadence and TSMC also recently announced their collaboration on 16 nanometers.

Additionally, TSMC has certified the production-ready Cadence design flow for its 20-nanometer manufacturing process. The full tool chain was certified at 20 nanometers through the design of an ARM Cortex-A9 processor, and is the first integrated tool certification for TSMC 20SoC process technology. The Cadence tools used are Virtuoso, EDI System, Encounter Timing System, Encounter Power System, Virtuoso Power System, Physical Verification System and QRC Extraction.

Ping Hsu, SVP of R&D, Silicon Realization Group at Cadence, is quoted in the Press Release: “TSMC’s certification of Cadence tools for 16-nanometer FinFET and 20-nanometer design underscores our joint commitment to working with our customers to help ensure their success.”

Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division, is also quoted: “Our early DRM & SPICE certification, achieved through TSMC’s Open Innovation Platform collaboration model, informs design teams that they can confidently use these Cadence tools for early development of high-performance, low-power 16-nanometer FinFET designs. And the certification of the Cadence tools for 20SoC indicates their readiness for this advanced technology process.”

**Mentor Graphics announced significant achievements in its continued collaboration with TSMC on 20nm physical verification kit optimizations. This joint effort has reduced Calibre nmDRC 20nm signoff run times by at least a factor of 3X and memory requirements by 60% compared to initial design kits released last year.

In addition, Calibre PERC N20 design kits are now available to TSMC customers as part of the companies’ ongoing collaboration for IC reliability improvement. The collaboration will continue as mutual customers ramp their releases of N20 production designs, with the goal of maintaining rapid turnaround on full-chip signoff runs for the largest SoC designs in the industry.

Other ongoing collaboration between TSMC and Mentor is focusing on optimizing the Calibre DFM product family, which incorporates TSMC’s unified DFM (UDFM) engine. Improvements are expected to result in run time reduction in TSMC’s latest DDK release, and customers who use any DFM tools compliant with TSMC UDFM engine will benefit.

Michael Buehler-Garcia, Senior Director of Calibre Design Solutions Marketing at Mentor Graphics, is quoted in the Press Release: “Our work with TSMC demonstrates the advantage of close collaboration among the foundry, EDA vendor and lead customers to bring new process nodes to market more efficiently. Our efforts don’t stop when tools are qualified. We continue to work with TSMC to optimize the design kits as the process matures, resulting in overall shorter design cycle times.”

Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division, is also quoted: “The close working relationship between TSMC and Mentor has existed for many years and continues to result in new solutions and rapid performance optimization. With N20 we have taken our efforts to the next level to deliver optimized Calibre DRC decks, which include multi-patterning, on an even faster timetable than for prior nodes. Building on this success, we have already extended performance improvements to the first-release Calibre N16 decks.”

**Synopsys announced that TSMC has certified a comprehensive list of custom and digital design tools from Synopsys for 16-nm FinFET process Design Rule Manual (DRM) and SPICE V0.1. Certification includes all the relevant 16-nm technology routing rules, verification runsets, extraction rundecks and iPDKs. Results from the collaboration are enabling early adopters of the TSMC 16-nm process to realize the potential of FinFET technology to develop faster and more power-efficient designs.

The certified Synopsys Galaxy Implementation Platform features comprehensive support for TSMC 16-nm V0.1 design rules. TSMC has certified a full suite of Synopsys implementation tools that are FinFET-ready. This includes IC Compiler, IC Validator, PrimeTime, StarRC, FineSim and CustomSIM, Custom Designer and Laker Layout.

Bijan Kiani, VP of Product Marketing, Design & Manufacturing Products at Synopsys, is quoted in the Press Release: “Our collaboration with TSMC highlights our goal to enable transparent adoption of FinFET technology for our mutual customers. To achieve this goal we engaged with TSMC on a comprehensive and deep collaboration spanning digital as well as custom implementation and verification tools.”

Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division, is also quoted: “Certification of Synopsys tools for our 16-nanometer process is a critical milestone in the rollout of our FinFET technology. Our FinFET collaboration started earlier than at previous nodes due to the complexity involved in modeling the 3-D FinFET devices. This certification helps early adopters get trusted access to our advanced process and accelerates deployment of FinFET technology.”