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U.S. Patents Awarded to Inventors in North Carolina (Feb. 8)

(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service
Targeted News Service
ALEXANDRIA, Va., Feb. 8 -- The following federal patents were awarded to inventors in North Carolina.

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Cree Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Cree, Durham, N.C., has been assigned a patent (8,368,100) developed by Matthew Donofrio, Raleigh, N.C., James Ibbetson, Santa Barbara, Calif., and Zhimin Jamie Yao, Goleta, Calif., for a "semiconductor light emitting diodes having reflective structures and methods of fabricating same."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Light emitting diodes include a diode region having first and second opposing faces that include therein an n-type layer and a p-type layer, an anode contact that ohmically contacts the p-type layer and extends on the first face, and a cathode contact that ohmically contacts the n-type layer and also extends on the first face. The anode contact and/or the cathode contact may further provide a hybrid reflective structure on the first face that is configured to reflect substantially all light that emerges from the first face back into the first face. Related fabrication methods are also described."
The patent application was filed on May 11, 2009 (12/463,709). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,100&OS=8,368,100&RS=8,368,100
Written by Arpi Sharma; edited by Anand Kumar.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method for improved growth of a semipolar (Al,In,Ga,B)N semiconductor thin film using an intentionally miscut substrate. Specifically, the method comprises intentionally miscutting a substrate, loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an In.sub.xGa.sub.1-xN nucleation layer on the heated substrate, depositing a semipolar nitride semiconductor thin film on the In.sub.xGa.sub.1-xN nucleation layer, and cooling the substrate under a nitrogen overpressure."
The patent application was filed on Dec. 6, 2011 (13/311,986). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,179&OS=8,368,179&RS=8,368,179
Written by Arpi Sharma; edited by Anand Kumar.

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International Rectifier Assigned Patent for III-nitride Materials Including Low Dislocation Densities and Methods Associated with the Same
ALEXANDRIA, Va., Feb. 8 -- International Rectifier, El Segundo, Calif., has been assigned a patent (8,368,117) developed by Edwin L. Piner, Cary, N.C., John C. Roberts, Hillsborough, N.C., and Pradeep Rajagopal, Raleigh, N.C., for "III-nitride materials including low dislocation densities and methods associated with the same."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Semiconductor structures including one, or more, III-nitride material regions (e.g., gallium nitride material region) and methods associated with such structures are provided. The III-nitride material region(s) advantageously have a low dislocation density and, in particular, a low screw dislocation density. In some embodiments, the presence of screw dislocations in the III-nitride material region(s) may be essentially eliminated. The presence of a strain-absorbing layer underlying the III-nitride material region(s) and/or processing conditions can contribute to achieving the low screw dislocation densities. In some embodiments, the III-nitride material region(s) having low dislocation densities include a gallium nitride material region which functions as the active region of the device. The low screw dislocation densities of the active device region (e.g., gallium nitride material region) can lead to improved properties (e.g., electrical and optical) by increasing electron transport, limiting non-radiative recombination, and increasing compositional/growth uniformity, amongst other effects."
The patent application was filed on March 29, 2010 (12/748,778). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,117&OS=8,368,117&RS=8,368,117
Written by Arpi Sharma; edited by Anand Kumar.

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Cdex Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Cdex, Tucson, Ariz., has been assigned a patent (8,368,034) developed by Wade Poteet, Vail, Ariz., James Ryles, Tucson, Ariz., and Malcolm Philips, Cornelius, N.C., for a "substance detection, inspection and classification system using enhanced photoemission spectroscopy."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A handheld or portable detection system with a high degree of specificity and accuracy, capable of use at small and substantial standoff distances (e.g., greater than 12 inches) is utilized to identify specific substances and mixtures thereof in order to provide information to officials for identification purposes and assists in determinations related to the legality, hazardous nature and/or disposition decision of such substance(s). The system uses a synchronous detector and visible light filter to enhance detection capabilities."
The patent application was filed on April 4, 2011 (13/064,626). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,034&OS=8,368,034&RS=8,368,034
Written by Arpi Sharma; edited by Anand Kumar.

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Micron Technology Assigned Patent for Devices and System Providing Reduced Quantity of Interconnections
ALEXANDRIA, Va., Feb. 8 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,369,168) developed by Robert M. Walker, Raleigh, N.C., for "devices and system providing reduced quantity of interconnections."
The abstract of the patent published by the U.S. Patent and Trademark Office states: " Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an address bus a first portion of an address of a next row of memory cells to be activated. The first portion of the address of the next row of memory cells to be activated is embedded in a command related to the previously activated row of memory cells. The next row of memory cells is subsequently activated according to a concurrently received second portion of the address of the next row of memory cells also received over the address bus. The portioning of the address signals can reduce the width of the address bus and, therefore, the number of required respective external interconnections. "
The patent application was filed on May 27, 2005 (13/279,513). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,369,168&OS=8,369,168&RS=8,369,168
Written by Satyaban Rath; edited by Hemanta Panigrahi.

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QUALCOMM Assigned Patent for Methods and Apparatus for Sum of Address Compare Write Recode and Compare Reduction
ALEXANDRIA, Va., Feb. 8 -- QUALCOMM, San Diego, has been assigned a patent (8,369,120) developed by Timothy Edward Ozimek, Raleigh, N.C., for "methods and apparatus for sum of address compare write recode and compare reduction."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Techniques are described for sum address compare (A+B=K) operation for use in translation lookaside buffers and content addressable memory devices, for example. Address input signals A and B are supplied as input to the A+B=K operation and K is a previous value stored in a plurality of memory cells. In each memory cell, a single logic gate circuit output and its inversion are generated in response to updating the memory cells, wherein each single logic gate circuit has as input an associated memory cell output and a next lowest significant bit adjacent memory cell output. In each of the memory cells, a portion of the A+B=K operation associated with each memory cell is generated in a partial lookup compare circuit wherein the corresponding address input signals A and B are combined with the associated memory cell output and the generated single logic gate circuit output and its inversion during a read lookup compare operation."
The patent application was filed on March 19, 2010 (12/727,623). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,369,120&OS=8,369,120&RS=8,369,120
Written by Satyaban Rath; edited by Hemanta Panigrahi.

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Micron Technology Assigned Patent for Techniques for Reading from and/or Writing to a Semiconductor Memory Device
ALEXANDRIA, Va., Feb. 8 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,369,177) developed by Betina Hold, El Dorado Hills, Calif., and Robert Murray, Matthews, N.C., for "techniques for reading from and/or writing to a semiconductor memory device."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Techniques for reading from and/or writing to a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first memory cell array having a first plurality of memory cells arranged in a matrix of rows and columns and a second memory cell array having a second plurality of memory cells arranged in a matrix of row and columns. The apparatus may also include a data sense amplifier latch circuitry having a first input node and a second input node. The apparatus may further include a first bit line input circuitry configured to couple the first memory cell array to the first input node of the data sense amplifier latch circuitry and a second bit line input circuitry configured to couple the second memory cell array to the second input node of the data sense amplifier latch circuitry."
The patent application was filed on March 5, 2010 (12/718,310). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,369,177&OS=8,369,177&RS=8,369,177
Written by Satyaban Rath; edited by Hemanta Panigrahi.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Systems and methods to forward data frames are described. A particular method may include generating a plurality of management frames at a controlling bridge. The management frames may include routing information. The plurality of management frames may be communicated to a plurality of bridge elements coupled to a plurality of server computers. The plurality of bridge elements are each configured to selectively forward a plurality of data frames according to the routing information."
The patent application was filed on April 26, 2010 (12/767,174). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,369,296.PN.&OS=PN/8,369,296&RS=PN/8,369,296
Written by Amal Ahmed; edited by Jaya Anand.

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Rockstar Consortium U.S. Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Rockstar Consortium U.S., Plano, Texas, has been assigned a patent (8,369,329) developed by Edwin Koehler Jr., Ontario, N.Y., John Yoakum, Cary, N.C., and Cherif Sleiman, East Amherst, N.Y., for a "dynamic hierarchical address resource management architecture, method and apparatus."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A Dynamic Hierarchical Address Resource Management Architecture (DHARMA) coordinates a logical hierarchy of address spaces with a virtual topology of network elements using a manageable database environment. Address spaces are apportioned into hierarchical levels in accordance with a network policy. Network elements may be represented as objects, coupled via the logical address space. Both address space hierarchy definition and virtual topology modelling may occur independent from actual network deployment. As a result, multiple address space hierarchy definitions and virtual topologies can be pre-generated and stored for selective use during network deployment. With such an arrangement, a flexible addressing architecture is provided which may advantageously be used in any network that desires dynamic network configuration. The connection between the logical address hierarchy and the virtual network topology may advantageously be implemented through the use of a logical tag that links a virtual network element to a logical address hierarchy level."
The patent application was filed on Jan. 3, 2006 (11/325,064). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,369,329.PN.&OS=PN/8,369,329&RS=PN/8,369,329
Written by Amal Ahmed; edited by Jaya Anand.

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Elster Electricity Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Elster Electricity, Raleigh, N.C., has been assigned a patent (8,368,554) developed by John R. Holt, Wake Forest, N.C., for a "system and method for collecting information from utility meters."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method of communicating between a collector meter and back haul device is disclosed. The method provides the collector meter, the collector meter has a local communications means for communicating to a plurality of utility metering devices, the collector meter also has having a short haul communications means. The method further provides the back haul device. The back haul device having the short haul communication means and a wireless telephonic communication means. The method communicates information between the collector meter and the back haul device using the short haul communication means. The method further sends data from the back haul device to a utility receiving center using the wireless telephonic means."
The patent application was filed on Dec. 18, 2007 (12/002,644). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,368,554.PN.&OS=PN/8,368,554&RS=PN/8,368,554
Written by Kusum Sangma; edited by Anand Kumar.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "An anti-theft security device is particularly useful with bottles and is typically secured to a bottle neck. The device may carry an onboard alarm. The device typically includes a catch member which engages the bottle neck to secure the device to the bottle and a blocking structure to help block access to the catch member."
The patent application was filed on March 8, 2012 (13/415,093). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,368,537.PN.&OS=PN/8,368,537&RS=PN/8,368,537
Written by Kusum Sangma; edited by Anand Kumar.

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InVue Security Products Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- InVue Security Products, Charlotte, N.C., has been assigned a patent (8,368,536) developed by Christopher J. Fawcett, Charlotte, N.C., and David N. Berglund, Marvin, N.C., for a "merchandise display security devices including anti-theft features."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Exemplary embodiments of merchandise display security devices including anti-theft features for preventing theft of an item of merchandise being displayed in a display area of a retail store are shown and described. The security devices provide a dual alarm merchandise security system including an alarm unit attached to the item of merchandise and electrically and mechanically connected to a fixed unit that is attached to a fixed support within the display area. The alarm unit and the fixed unit each include an alarm that is activated by a control circuit upon predetermined alarm conditions. A breakaway cable interconnects the alarm unit and the fixed unit and defines a sense loop therebetween. In one embodiment, the fixed unit is a display stand and the alarm unit is a sensor configured to be removably supported on the display stand."
The patent application was filed on July 20, 2010 (12/839,500). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,368,536.PN.&OS=PN/8,368,536&RS=PN/8,368,536
Written by Kusum Sangma; edited by Anand Kumar.

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Skyworks Solutions Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Skyworks Solutions, Woburn, Mass., has been assigned a patent (8,368,463) developed by David K. Homol, Kernersville, N.C., Ryan M. Pratt, High Point, N.C., and Hua Wang, High Point, N.C., for a "voltage distribution for controlling CMOS RF switch."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Disclosed are voltage distribution device and method for controlling CMOS-based devices for switching radio frequency (RF) signals. In certain RF devices such as mobile phones, providing different amplification modes can yield performance advantages. For example, a capability to transmit at low and high power modes typically results in an extended battery life, since the high power mode can be activated only when needed. Switching between such amplification modes can be facilitated by one or more switches formed in an integrated circuit and configured to route RF signal to different amplification paths. In certain embodiments, such RF switches can be formed as CMOS devices, and can be based on triple-well structures. In certain embodiments, various bias voltages applied to such a CMOS RF switch can be facilitated by a voltage distribution component."
The patent application was filed on July 27, 2010 (12/844,640). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,368,463.PN.&OS=PN/8,368,463&RS=PN/8,368,463
Written by Kusum Sangma; edited by Anand Kumar.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "An analog-to-digital converter includes a plurality of sequentially cascaded stages, each stage including an amplifier and four copies of a circuit block including a flash and capacitors, in which the four copies of the circuit block operate interleavingly in a respective sample mode, pre-gain mode, gain mode, and reset mode of the circuit block, the copies of the circuit block in the sample mode, pre-gain mode, and reset mode are decoupled from the amplifier, and the copy of the circuit block in the gain mode is coupled to the amplifier to produce an output for a next following stage."
The patent application was filed on April 27, 2011 (13/095,235). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,368,576.PN.&OS=PN/8,368,576&RS=PN/8,368,576
Written by Kusum Sangma; edited by Anand Kumar.

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method is provided for monitoring hygiene compliance."
The patent application was filed on Oct. 11, 2010 (12/901,891). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,368,544.PN.&OS=PN/8,368,544&RS=PN/8,368,544
Written by Kusum Sangma; edited by Anand Kumar.