Catch the unique power management requirements for next-generation PCI backplanes

The need for speed
We need faster buses for many reasons: faster processors, faster and larger disk drives and disk arrays made from these drives, faster display adapters, faster Ethernet and fiber data communications, and for faster memory arrays.

Modern IC processing produces logic that is faster than ever, but faster logic isn’t enough to make faster buses. Bus architects have to deal with bus capacitance, signal skew from different trace lengths, unpredictable bus loading, and tolerances throughout the system. The increases in bus speed come with decreases in voltage swing. These issues are intimately related to the power supply for bus transceivers, called the I/O supply or VIO. Getting optimum performance from modern buses requires careful attention to this supply.

The biggest strength of the PCI bus is backwards compatibility. The PCI SIG devised a way to allow newer boards to work in the same slot as older boards. Most legacy PCI boards and PCI-X 1.0 (also called mode-1) boards require 3.3V VIO while PCI-X 2.0 266MHz and 533MHz (also called mode-2) boards require 1.5V VIO. If 3.3V is applied to a mode-2 board, that board would surely be damaged. Yet if 1.5V is applied to a legacy or mode-1 board, that board would not have enough drive to produce logic "1" signals on the bus.

The original PCI standard allowed 5V and 3.3V cards to co-exist using a special cutout and key in the card edge connector. But cutout and key solutions don’t give backwards compatibility. Instead, PCI-X 2.0 uses a technique borrowed from modern high-performance microprocessors: logic-selectable voltage.

PCI systems determine adapter-card speed by measuring the voltage on the PCI-X capability terminal of the adapter card connector, PCIXCAP using an A/D converter on the system board. Conventional PCI cards ground PCIXCAP, so this signals the slot controller to limit the bus to 33MHz. PCI-X 66MHz cards contain a 10kΩ pull-down resistor on PCIXCAP, enabling PCI-X 66MHz operation. PCI-X 133MHz cards leave PCIXCAP floating, so 133MHz operation is enabled.

This technique has the added advantage of allowing an entire bus to be programmed by the voltage on one shared PCIXCAP wire. If any card inserted into the bus grounds PCIXCAP, then the whole bus will slow down to 33MHz. If PCIXCAP floats high, then all inserted cards must be PCI-X 133MHz cards so operation at 133MHz is enabled. If one or two cards pull PCIXCAP down with 10kΩ resistors, then the voltage on PCIXCAP will be lower than if floating, but still higher than grounded, and the bus will operate at PCI-X 66MHz.

PCI-X 2.0 extends this technique by defining two new pull-down resistors: 3.16kΩ for PCI-X 266MHz and 1.02kΩ for PCI-X 533MHz, giving a total of five different operating speeds. With the information from the PCIXCAP A/D converter, the system decides bus speed and VIO.

There are other challenges to implementing 266MHz 64-bit slots. Bridge technology is fast enough so that one bridge can support up to six 32-bit 66MHz PCI slots. For a 64-bit 133MHz PCI-X 1.0 bus, one bridge can only handle 2 slots. At 266MHz and higher, the high data rate between bridge and slot requires a single, direct connection between the bridge and the slot.