As a personal learning exercise, I've been using Minimig to implement a Mac+ core. It's still a work in progress, it boots to Finder from an emulated SCSI disk, but there's no mouse or keyboard yet

I'll post everything somewhere, maybe along with some kind of blog post explaining what I did, when I'm a little further along, however, being a reasonably n00b when it comes to HW design (I'm a SW person), there are a few things that I haven't managed to get my head around so far.

The main one is timing, as I suppose is to be expected. I don't totally get the meaning of the constraints in the Minimig UCF (and last I tried, recent Xiling ICE didn't like them either). I'm having timing closure errors from Xilinx tools on my video clock and my main 16Mhz clock, mostly on components that cross the clock domains (typically on the first gate of synchronizers), and I'm not sure whether that's just normal or if something needs to be done.

Also, it looks like the crystal used on Minimig (4.7Mhz) is outside of the DCM "happy" ranges. You can't run a DLL with less than 18Mhz on the input source, and in fact, if I use the DCM as a simple FX synthetizer, it also complains that 16Mhz is too slow (too long a period) for it to generate. When I tried to stack a DCM synthetizing a 33Mhz that I then fed into a DCM as a DLL, it spat out various warnings as well (I don't have them right at hand, but I can dig if it's of interest).

But then 33Mhz isn't what I want for a DLL.

What I really want is a 16Mhz all accross my entire design (yeah, my Mac is a bit overclocked except video. I use that same clock to generate the CPU clk (using a trick recommended by Xiling, feeding an OFDDRCPE with clk & ~clk). For video I generate something close to a 25Mhz using another DCM in pure FX mode. My pixel pipe is clocked off that and I have some async signaling to the my memory controller to get the pixels (with synchronizers to cross the clock domains).

Im also not an expert in porting or DCM matter, but perhaps some info may help:(If Im wrong, please correct me!)

You could first generate a high frequence out of the 4.433MHz source clock, then "cut it down" to a desired clock rate. In Minimig core its done the same way, else Spartan3 synthesis will not allow it.

If Im right, memory timimg constants in any core should use same value as in Minimig .UCF file too.Some board use 45 or even 55ns S-RAM chips, those also should work with your design. Therefor try to keep the settings equal, it should work for any porting... if necessary use memory access waitstate or something else to slow the bus down.

Beware that 68SEC000 cpu´s "function control wire" is NOT connected to the FPGA.Means if any (operating)software depend on cpu state, it require a workarround inside the FPGA. Something similar already is done in Minimig core too.

Good luck and Im looking forward t see any result

______________________________________________JMP $00000BED ; will guru-meditation until next morning

Well, it's coming along nicely Because it's really a learning exercise for me I'm not re-using any of Minimig original design, I'm doing everything from scratch so it takes time considering my negative amount of spare time lately (being the Linux powerpc arch maintainer doesn't help). But it's getting there.

SCSI seems to be humming along now, I did some tweaks for blind transfers to work reliably, and I have a low level PS/2 interface that seems to work fine as of yesterday, just need to get the higher level mouse & kbd stuff going before it starts to be really usable.

From there I think Audio will be next, and I'll finish with floppy & serial. The former is "interesting" but I have all the info I need to do it, it's just a lot of work to re-do the track encoding on the fly (I could do it in the PIC but again, the point for me is to learn about HW design so ...). I did a working SW model already anyways. I'll probably post things out before that tho, probably as soon as mouse & kbd work.

I also haven't heard from Farenheit for a while about the ARM controller board I ordered so it' still PIC only.

@boing4000: Yeah I think I have the general memory controller timings within RAM ranges, but I'm not totally sure I got the constraints right for the synthetizer. The recent Xilinx ISE doesn't seem to grok whatever is in the original UCF file. Oh well, it seems to work for now, we can have a closer look later after I publish my stuff.

Regarding the wiring of the m68k, yeah I noticed the missing lines. BERR is missing too, etc... the workarounds aren't hard. In fact the only one I really needed was for interrupts since _AVEC isn't there. So you have to "present" the right vector numbers on the bus on interrup cycles. But it's easy to recognize those just by address. On minimig (maybe on a real Amiga too ?) the ROM contains the right values. On the Mac, the ROM isn't in the right place (it's at 0x4* not 0xF*) so I hacked up a pseudo device on my internal bus that responds to the FFF* addresses and returns the right interrupt vectors. Seems to work fine, the Mac has nothing there anyways.

Ok, here we go. I've called it v0.1 for now, read the README etc... lot of stuff missing, and it requires a 4M minimig, but I did get it to Finder and got to play with a couple of apps.

Help & advice much welcome, especially when it comes to timing and/or the possible cause of the instability / erratic behaviour I can observe sometimes after having used it for a couple of hours in a row. Remember, I'm just a SW guy learning verilog & FPGAs for fun so I'm probably missing something in the big picture.

BTW. I forgot to mention that in the included README (will fix that later), but there's a Xilinx ISE projectfile in there (fpga/xilinx/minimigmax.xise). It's for ISE 13.1 (latest one, I use the WebPack). I can probablydig out one for ISE 12.3 if needed but it shouldn't be hard to re-create.

Im using ISE 12.4 and it works fine for other cores.First synthesis fail due to some error in "sim_pic.v" file:

Code:

ERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 87 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 88 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 89 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 90 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 96 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 97 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 105 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 106 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 119 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 120 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 147 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 148 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 149 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 159 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 160 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 274 'i' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 281 'i' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 282 'i' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 284 'i' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 284 'i' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 285 'i' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 309 'i' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 322 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 324 'i' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 325 'i' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 325 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 329 'i' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 329 'i' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 333 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 336 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 338 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 340 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 342 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 344 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 346 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 352 'i' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 353 'i' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 355 'i' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 355 'i' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 404 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 405 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 427 'val' has not been declaredERROR:HDLCompilers:28 - "../fpga/sim_pic.v" line 428 'val' has not been declared

VHDL remain strange to me!

Its also not clear to me, how to compile PIC .hex file... Im not a C coder at all.Would it be possible to provide pre-compiled FPGA core and PIC firmware file for us to try?

______________________________________________JMP $00000BED ; will guru-meditation until next morning

Who is online

Users browsing this forum: No registered users and 1 guest

You cannot post new topics in this forumYou cannot reply to topics in this forumYou cannot edit your posts in this forumYou cannot delete your posts in this forumYou cannot post attachments in this forum