I. INTRODUCTION Development of the high-speed wireless communication systems puts increasing request on integrated low-cost RF devices with multi-GHz bandwidth operating at the lowest power consumption and supply voltage. Ultra-wideband (IEEE 802.15.3a) appears as a new technology capable for high data transfer rates (up to 1 Gb/s) within short distances (10 m) at low power. This technology uses for some application such as wireless personal area networks (WPANs), providing an environment for transmission of audio, video, and other high-bandwidth data . One of the approach that have been proposed to use the spectrum of 3.1-10.6-GHz allocated for UWB systems, uses Orthogonal Frequency Division Multiplexin OFDM modulation with 14 sub-bands whichever occupies 528-MHz band width and a fast frequency-hopping scheme [1]. In OFDM, the sub-carrier f requencies are perpendicular to each other. This method eliminates the cross-talk between the sub-channels and accordingly inter-carrier guard bands are not necessary. Although the standard has not been perfected, a front-end wideband LNA is absolutely necessary regardless of the receiver architecture. The amplifier must meet several requirements, for example to interface with the preselect filter and antenna, the amplifier input impedance should be close to 50 over the desired UWB band. However sufficient gain with wide band width to overtop the noise of a mixer, low noise figure to improve receiver sensitivity, low power consumption to increase battery life, small die area to reduce the cost, unconditional stability and good linearity are important parameters. There is a close trade-off between them. Generally by improving one of them, the others are ruined.

II. Input stage Common-gate and Cascode configurations are two kinds of methods usually used to design the input stage of LNA in CMOS circuits, while the Common-Gate and Cascode structure provide a wide-band and narrow-band input matching respectively. However Common-gate stage has an intrinsically high noise figure versus Cascode stage and the noise-canceling techniques must be used. However input impedance is set by bias & W/L ratio. In fact this structure considers a degree of freedom for transconductance of transistor and also by choosing an appropriate load (a good combination of inductor and capacitors while considering the effect of parasitic capacitance and body), provides an available broadband input matching. This load must be proportional to r_ds1. Since gm alters, the input impedance and the matching bandwidth are approximately equal to the f_T of the device. The parasitic transistor capacitance C_gs starts playing roles when the operating frequency starts to rise. In the narrow band application, a shunt inductor is added in the input stage to resonate with C_gsto enhance impedance matching at the desired frequency. However in most CMOS narrow band applications, cascode LNA with inductive degeneration is preferable but for isolating from the input to the output and omitting of the C_gd path, the Common-Gate LNA performs better reverse isolation and stability versus Common-Source LNA.

III. CIRCUIT DESIGN AND ANALYSIS The proposed wide-band LNA is shown in Fig. 1. It consists of an input stage and a common source stage. Table 1 shows the design values of the proposed CMOS LNA. An off-chip bias-T provides the gate bias of M_3 and the DC current path of M_1. The series inductor L_4 further resonates with the input gate- source capacitance of M_3, resulting in a larger bandwidth and some residual peaking on the frequency response [17]. The parasitic capacitances of M_2

Fig. 1. Proposed broadband noise-canceling LNA

TABLE I DESIGN VALUES OF THE PROPOSED CMOS LNA L_in 4nH (W/L)3 135/0.18 L_0 0.5nH (W/L)4 37.5/0.18 L_1 4.5nH (W/L)5 45/0.18 L_2 2.5nH C_in,C_(out,) C_3 2PF L_3 0.9nH C_1,C_2 1PF L_4 2.2nH R_1 290Ω L_5 0.8nH R_2 135Ω (W/L)1 18/0.18 R_3 40Ω (W/L)2 30/0.18 and M_3 make an LC ladder structure with inductor L_0. The DC load resistors R_1 and R_2 are combined with shunt peaking inductors L_1 and L_2 respectively to extend circuit bandwidth effectively [10]. The series peaking inductor L_2 also resonate with the total parasitic capacitances C_d2 and C_d3 at the drain of M_2 and M_3. Since the load resistor, R_3, is added to reduce the Q factor of L_3 for flat gain. The minimum channel length of 0.18μm is considered for all the transistors in the proposed circuit to minimize parasitic capacitances and improve frequency performance. The common source stage extends bandwidth, provides better isolation and increases frequency gain. In fact the input stage and the common source stage support low-frequency power gain and high-frequency power gain, respectively. The combination of both frequency responses lead to a broadband power gain. Transistor M5 also helps common source stage to increase and smooth frequency gain. Fig. 2 shows the effect of M5 on the S21 parameter.

Fig. 2 The effect of M5 on the S21 parameter

In Fig. 3 the effects of M1 as input stage are investigated. The simulated NF and S11 parameter is compared to the case with M1 is turned OFF. There is a close tradeoff between NF and S11. When M_1 is turned on, the NF is increased and S21 parameter is decreased with the same power dissipation and a similar bandwidth, but on the contrary an acceptable input matching will be achieved. Extra concentration should be given to the noise characteristics of the Common-Gate structure in the input stage, although transistor M_1 provides a wide-band matching, it has an intrinsically high noise figure.

In order to investigate the noise performance, the MOS transistor noise model with the channel thermal noise is used. As shown in Fig.4, neglecting the gate and flicker noises and assuming a perfect match in this analysis, the PSD of the channel thermal noise (i_(n,d)^2 ) ̅ is given as (i_(n,d)^2 ) ̅=4KTγg_do ∆f=4KT γ/α g_m ∆f (1) Where is the Boltzmann constant, is the absolute temperature in Kelvin, γ is the MOS transistor’s coefficient of channel thermal noise, α is defined as the ratio of the transconductance g_mand the zero-bias drain conductance g_ds and is the bandwidth over which the noise figure is measured respectively. The following equations describe the noise figure by R_1, M_1, M_2 and M_3 that they contribute to the overall noise figure [1]

Fig. 4. Principle of the noise schematic

If the condition (2) is established the noise of M_1 is omitted [1].

g_m2 R_1=g_m3 R_s (2)

The following equations describe the noise figure by R_1, M_2 and M_3 that they contribute to the overall noise figure.

IV.SIMULATION RESULT The circuit was simulated with 0.18μm TSMC library Hspice software. All simulations are done considering 50Ω input and output terminals. In Fig.5(a) gain power and reverse isolation of the LNA are simulated. The average gain power is approximately 14.5 dB with 0.7 dB ripple over the frequency range. The reverse isolation is less than -35dB. Fig.5(b) shows the noise figure, input and output isolation. The NF is less than 2.9 dB ,S11 is less than-14.8db and S22 is approximately less than -10dB.

The results of this work are shown in “TABLE II” and are compared with recently published CMOS LNAs.

TABLE 2 PERFORMANCE SUMMARY VI. CONCLUSION This paper presents a new design of an UWB LNA structure based on a standard RFCMOS technology. Satisfactory input matching and noise performance are obtained after regarding the tradeoffs between the input impedance of the common-gate stage and its. noise performance. The measured noise figure is less than 2.9 dB over 3.1-10.6-GHz. A flat gain is worth mentioning in all LNA design and the simulated power gain is 14.5±0.7 dB.

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