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CS/CoE1541: Intro. to Computer Architecture University of Pittsburgh Analyzing instruction execution  lw (load word) Fetch instruction Read a base register Sign-extend the immediate offset Add the two numbers made available in the above two steps Access data memory with the address computed in the above step Store the value from the memory to the target register specified in the instruction

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CS/CoE1541: Intro. to Computer Architecture University of Pittsburgh Analyzing instruction execution  add (add) Fetch instruction Read from two source registers Add the two numbers made available in the above step Store the result to the target register specified in the instruction

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CS/CoE1541: Intro. to Computer Architecture University of Pittsburgh Analyzing instruction execution  j (jump) Fetch instruction Extend the 26-bit immediate field Shift left by 2 bits (28 bits now) Extract the most significant 4 bits from the current PC and concatenate to form a 32-bit value Assign this value to PC

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CS/CoE1541: Intro. to Computer Architecture University of Pittsburgh Common steps in inst. execution  Fetching the instruction word from the instruction memory  Decoding the instruction and reading from the register file Or prepare a value from the immediate value (and PC)  Performing an ALU operation  Accessing the data memory (if needed)  Making a jump (assigning a computed value to PC) (if needed)  Writing to the register file  Designing a control logic is based on our (more formal) analysis of instruction execution Consider all instructions

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CS/CoE1541: Intro. to Computer Architecture University of Pittsburgh Fetching an instruction Instruction width is 4 bytes! Instruction width is 4 bytes! Instruction memory here is read-only! Instruction memory here is read-only! PC keeps the current memory address from which instruction is fetched PC keeps the current memory address from which instruction is fetched

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CS/CoE1541: Intro. to Computer Architecture University of Pittsburgh Fetching operands For branches! Two reads at a time! Two reads at a time!

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CS/CoE1541: Intro. to Computer Architecture University of Pittsburgh Handling memory access Imm. offset for address Imm. offset for address Data to store! Load data from memory Load data from memory Data to be in a register! Data to be in a register!

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CS/CoE1541: Intro. to Computer Architecture University of Pittsburgh Datapath so far j instruction not considered so far! j instruction not considered so far!

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CS/CoE1541: Intro. to Computer Architecture University of Pittsburgh Single-cycle execution problem  The cycle time depends on the most time-consuming instruction What happens if we implement a more complex instruction, e.g., a floating-point multiplication All resources are simultaneously active – there is no sharing of resources  We’ll adopt a multi-cycle solution which allows us to Use a faster clock; Adopt a different number of clock cycles per instruction; and Reduce physical resources

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CS/CoE1541: Intro. to Computer Architecture University of Pittsburgh Multi-cycle implementation  Reusing functional units Break up instruction execution into smaller steps Each functional unit is used for a specific purpose in any cycle ALU is used for additional functions: calculation and PC increment Memory used for instructions and data  At the end of a cycle, keep results in registers Additional registers  Now, control signals are NOT solely determined by the instruction bits  Controls will be generated by a FSM!

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CS/CoE1541: Intro. to Computer Architecture University of Pittsburgh Step 1: instruction fetch  Access memory w/ PC to fetch instruction and store it in Instruction Register (IR)  Increment PC by 4 using ALU and put the result back in the PC We can do this because ALU is not busy in this cycle Actual PC Update is done at the next clock rising edge

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CS/CoE1541: Intro. to Computer Architecture University of Pittsburgh Step 2: decode & operand fetch  Read registers rs and rt We read both of them regardless of necessity Store two values in temporary register A and B  Compute the branch address using ALU in case the instruction is a branch We can do this because ALU is not busy ALUOut will keep the target address  We have not set any control signals based on the instruction type yet Instruction is being decoded now in the control logic!

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CS/CoE1541: Intro. to Computer Architecture University of Pittsburgh Step 4: memory access  If the instruction is memory reference MDR <= Memory[ALUOut];// if it is a load Memory[ALUOut] <= B;// if it is a store Store is complete!  If the instruction is R-type Reg[IR[15:11]] <= ALUOut; Now the instruction is complete!

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CS/CoE1541: Intro. to Computer Architecture University of Pittsburgh To wrap up  From a number of building blocks, we constructed a datapath for a subset of the MIPS instruction set  First, we analyzed instructions for functional requirements  Second, we connected buildings blocks in a way that accommodates instructions  Third, we kept refining the datapath

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CS/CoE1541: Intro. to Computer Architecture University of Pittsburgh To wrap up  We looked at how an instruction is executed on the datapath in a pictorial way  Control signals were connected to functional blocks in the datapath  How execution sequence of an instruction change the control signals was analyzed  We looked at the multi-cycle control scheme in some detail Multi-cycle control can be implemented using FSM