Shared Caching

Chip multiprocessors often provide at least one
level of on-chip cache that is shared among the multiple cores. This
project is exploring new thread schedulers and architectural
enhancements in order to reduce the number of shared cache misses for
multi-threaded programs. The thread scheduler takes advantage of the
potential overlap in memory references among threads working on the
same program, to keep working set sizes small. This dramatically
decreases the working set size compared with previous scheduling
approaches, potentially reducing the number of misses by orders of
magnitude. Key goals of our approach include (1) existing programs
need not be modified in order to get good many-core cache performance,
and (2) the scheduler provides provably good cache performance for any
program with good single-core cache performance.