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Abstract

In multiple-chip implementation of high-performance systems with very short clock cycle, say below 20 nanoseconds, the design approach to avoid clock skew is crucial. Since the on-chip clock loading can be very heavy in the VLSI environment, the on-chip clock re-drive and distribution are unavoidable. Under this circumstance, clock skew can (Image Omitted) come from two sources. One is intra-chip (local) clock interconnection/distribution and the other is inter-chip (global) clock interconnection/distribution. The intra-chip clock skew can be controlled fairly well by a chip designer by using balanced clock distribution network with matched transmission line interconnection. The clock is distributed within a chip in such a way that at each node of distribution the clock is equally delayed from the clock input.

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United States

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English (United States)

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SCHEME for REDUCING CLOCK SKEW in MULTIPLE-CHIP SYSTEM
DESIGN

In multiple-chip implementation of high-performance systems with very short
clock cycle, say below 20 nanoseconds, the design approach to avoid clock skew
is crucial. Since the on-chip clock loading can be very heavy in the VLSI
environment, the on-chip clock re-drive and distribution are unavoidable. Under
this circumstance, clock skew can

(Image Omitted)

come from two sources. One is intra-chip (local) clock
interconnection/distribution and the other is inter-chip (global) clock
interconnection/distribution. The intra-chip clock skew can be controlled fairly
well by a chip designer by using balanced clock distribution network with
matched transmission line interconnection. The clock is distributed within a chip
in such a way that at each node of distribution the clock is equally delayed from
the clock input. For the whole system, however, it is more difficult to achieve
balanced clock distribution based on the following reasons. First, the on-chip
distribution network can be quite different from chips to chips. The differences
include both topological and loading differences. Secondly, the speed (or gate
delay) of the clock re-drive circuit can be varied from chips to chips due to
process variation. Thirdly, the input clock to each chip can have skew due to
external distribution network. To solve this problem, it is proposed to observe
one of the distributed clocks of each logic chip and adjust system clocks
accordingly. In this scheme, an automatic clock adjusting circuit is designed to
adjust all the system clocks based on the observed distributed clocks. This
automatic adjusting circuit will be on the clock chip. A binary-tree clock
distribution network is shown in Fig. 1. All the distributed clocks are re-driven at
the leaves. No mid-way tapping is allowed. Ideally, if the interconnection is ideal
transmission line, the clock can be distributed with equal delay at all the leaves.
However, the interconnection cannot be simply treated as transmission lines
because there is no lossless ground plane in CMOS II process. Whether it is
necessary to add an extra metal layer for ground plane is not the subject here.
What we are proposing below is how to approximate the transmission line
interconnection with the current technology. There are three layers of metal in
CMOS II. In most of the cases, the

(Image Omitted)

third layer metal is used for connection pads to C4. Only the first and second
layer metal are used for interconnection and power distribution. Furthermore,
most often, the first and second layer metal are used in perpendicular direction,
say the first is used horizontally and the second is used vertically, to facilitate the
routing task. In that case, for the clock distribution network shown in Fig. 1, the
clock distribution line will have to go up and down when it changes the direction.
Our idea is to always have the clock distribution line surrounded by groun...