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Core Testing Circuit

Publishing Venue

IBM

Related People

Smith, FH: AUTHOR

Abstract

Core testing circuit 10 permits the comparison of the amplitude of two pulse outputs occurring at different times from a single ferrite core under test. These two pulses are uV1 or undisturbed one and rV1 or read disturbed one. Although the two pulses are separated in time by as much as two milliseconds, circuit 10 permits their direct comparison.

Country

United States

Language

English (United States)

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Core Testing Circuit

Core testing circuit 10 permits the comparison of the amplitude of two pulse
outputs occurring at different times from a single ferrite core under test. These
two pulses are uV1 or undisturbed one and rV1 or read disturbed one. Although
the two pulses are separated in time by as much as two milliseconds, circuit 10
permits their direct comparison.

Program generator 12 controls current drivers 14 to simulate memory
functions. At a predetermined point in the testing sequence, trigger T1 is set by
generator 12. A uV1 signal is generated from core 18 under test. When T1 is
set, current source transistor Q4 is turned off, allowing capacitor C1 to charge
until transistor Q3 is biased off. The DC level on C1, proportional to the uV1
signal, is amplified in A1. That signal is fed through emitter-follower transistors
Q1, Q2, and Q9 which provide impedance matching and signal isolation.

When the amplified uV1 signal is applied to the base of Q3, Q3 turns on,
further charging C1 to an amplitude proportional to the maximum amplitude of
the uV1 signal. As the uV1 signal amplitude drops, Q3 turns off again. The
charge leaks from C1 into off-biased Q3 and Q4 and into amplifier A2. This
leakage current is replaced by constant current source Q5. In this manner, the
voltage on C1 is maintained at a constant amplitude until T1 is reset, at which
time Q4 is biased on and C1 discharges. The resulting output of A2 is a
stretched DC, proportional to uV1.