Sign up to receive free email alerts when patent applications with chosen keywords are publishedSIGN UP

Abstract:

A semiconductor device includes a buffer layer that is disposed over a
substrate, a high-resistance layer that is disposed over the buffer
layer, the high-resistance layer being doped with a transition metal for
achieving high resistance, a low-resistance region that is disposed in a
portion of the high-resistance layer or over the high-resistance layer,
the low-resistance region being doped with an impurity element for
achieving low resistance, an electron travel layer that is disposed over
the high-resistance layer including the low-resistance region, an
electron supply layer that is disposed over the electron travel layer, a
gate electrode that is disposed over the electron supply layer, and a
source electrode and a drain electrode that are disposed over the
electron supply layer.

Claims:

1. A semiconductor device, comprising: a buffer layer that is disposed
over a substrate; a high-resistance layer that is disposed over the
buffer layer, the high-resistance layer being doped with a transition
metal for achieving high resistance; a low-resistance region that is
disposed in a portion of the high-resistance layer or over the
high-resistance layer, the low-resistance region being doped with an
impurity element for achieving low resistance; an electron travel layer
that is disposed over the high-resistance layer including the
low-resistance region; an electron supply layer that is disposed over the
electron travel layer; a gate electrode that is disposed over the
electron supply layer; and a source electrode and a drain electrode that
are disposed over the electron supply layer.

2. The semiconductor device according to claim 1, wherein the
low-resistance regions are disposed in a portion of the high-resistance
layer or over the high-resistance layer, each of the source electrode and
the drain electrode is disposed over a corresponding one of the
low-resistance regions, and the gate electrode is disposed over a region
other than the low-resistance regions.

3. The semiconductor device according to claim 1, wherein the gate
electrode has a recess structure formed partly without the electron
supply layer.

4. The semiconductor device according to claim 1, wherein the
high-resistance layer, the low-resistance region, the electron travel
layer, and the electron supply layer are made of a nitride semiconductor
material.

5. The semiconductor device according to claim 1, wherein the
high-resistance layer is made of GaN doped with the transition metal that
is any one selected from the group consisting of Fe, Ti, V, Cr, Mn, Co,
Ni, and Cu.

6. The semiconductor device according to claim 1, wherein the impurity
element for achieving low resistance is any one selected from the group
consisting of Si, Ge, and O.

7. The semiconductor device according to claim 1, wherein the
concentration of the impurity element for achieving low resistance in
each low-resistance region is higher than the concentration of the
transition metal in the high-resistance layer.

8. The semiconductor device according to claim 1, wherein the electron
travel layer is made of GaN.

9. The semiconductor device according to claim 1, wherein the electron
supply layer is made of n-type AlGaN.

10. The semiconductor device according to claim 1, further, comprising a
spacer layer disposed between the electron travel layer and the electron
supply layer, wherein the spacer layer is made of AlGaN.

11. The semiconductor device according to claim 1, further, comprising a
capping layer that is disposed over the electron supply layer, wherein
the capping layer is made of n-type GaN.

12. The semiconductor device according to claim 1, wherein the buffer
layer is made of a material including AlN.

13. A method for manufacturing a semiconductor device, comprising:
forming a buffer layer over a substrate and a high-resistance layer over
the buffer layer, the high-resistance layer being doped with a transition
metal; forming low-resistance regions in a portion of the high-resistance
layer or over the high-resistance layer, the low-resistance regions being
doped with an impurity element for achieving low resistance; forming an
electron travel layer over an area including the low-resistance regions
and an electron supply layer over the electron travel layer; and forming
a gate electrode, a source electrode, and a drain electrode over the
electron supply layer.

14. The method according to claim 13, wherein the low-resistance regions
are formed by doping portions of high-resistance layer with the impurity
element for achieving low resistance, each of the source electrode and
the drain electrode is formed over a corresponding one of the
low-resistance regions, and the gate electrode is formed over a region
other than the low-resistance regions.

15. The method according to claim 14, further, comprising forming an
alignment mark in the high-resistance layer subsequently to the formation
of the high-resistance layer, wherein the low-resistance regions are
formed in such a manner that a resist pattern including apertures
corresponding to the low-resistance regions is formed over a surface of
the high-resistance layer with reference to the alignment mark, and the
high-resistance layer is doped with the impurity element for achieving
low resistance subsequently to the formation of the resist pattern, and
the gate electrode, the source electrode, and the drain electrode are
formed in such a manner that a resist pattern including apertures
corresponding to the gate electrode, the source electrode, and the drain
electrode is formed over the electron supply layer with reference to the
alignment mark, and a metal film is formed over the resist pattern and is
then lifted off.

16. The method according to claim 13, wherein the concentration of the
impurity element for achieving low resistance in each low-resistance
region is higher than the concentration of the transition metal in the
high-resistance layer.

17. The method according to claim 13, wherein the impurity element for
achieving low resistance is any one selected from the group consisting of
Si, Ge, and O.

18. A method for manufacturing a semiconductor device, comprising:
forming a buffer layer over a substrate and a high-resistance layer over
the buffer layer in an epitaxial growth apparatus, the high-resistance
layer being doped with a transition metal; taking the substrate including
the high-resistance layer from the epitaxial growth apparatus to provide
the substrate including the high-resistance layer in another epitaxial
growth apparatus; forming an electron travel layer and an electron supply
layer in series over the high-resistance layer in the another epitaxial
growth apparatus; and forming a gate electrode, a source electrode, and a
drain electrode over the electron supply layer.

Description:

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is based upon and claims the benefit of priority
of the prior Japanese Patent Application No. 2011-168781, filed on Aug.
1, 2011, the entire contents of which are incorporated herein by
reference.

FIELD

[0002] The embodiments discussed herein are related to a semiconductor
device and a method for manufacturing the semiconductor device.

BACKGROUND

[0003] Nitride semiconductors such as GaN, AlN, and InN, materials
including mixed crystals thereof, and the like have a wide band gap and
therefore are used in high-power electronic devices, short-wavelength
light-emitting devices, and the like. As for the high-power electronic
devices, techniques related to field-effect transistors (FETs),
particularly high-electron mobility transistors (HEMTs), are under
development. HEMTs including such nitride semiconductors enable
large-current, high-voltage, low-on-resistance operation and therefore
are used in high-power, high-efficiency amplifiers, high-power switching
devices, and the like.

[0004] An HEMT made of GaN or the like is formed in such a manner that a
buffer layer is formed on a substrate of a semiconductor or the like, an
electron travel layer of i-GaN or the like is epitaxially grown on the
buffer layer by metal-organic vapor phase epitaxy (MOVPE) or the like. In
particular, as illustrated in FIG. 1, a buffer layer 921, an electron
travel layer 923 (923a illustrates a two dimensional electron gas.), a
spacer layer 924, an electron supply layer 925, and a capping layer 926
are formed in series on a substrate 910 and a gate electrode 931, a
source electrode 932, and a drain electrode 933 are formed on the capping
layer 926. An HEMT including a configuration illustrated in FIG. 1 has a
problem that since the buffer layer 921 has low resistance, a current
flows through the buffer layer 921 and therefore a leakage current
increases.

[0005] Therefore, an HEMT including a configuration in which a
high-resistance layer 922 is disposed on a buffer layer 921 as
illustrated in FIG. 2A is under investigation. In particular, the buffer
layer 921, the high-resistance layer 922, an electron travel layer 923, a
spacer layer 924, an electron supply layer 925, and a capping layer 926
are arranged in series on a substrate 910 and a gate electrode 931, a
source electrode 932, and a drain electrode 933 are disposed on the
capping layer 926. In the HEMT including the configuration illustrated in
FIG. 2A, the high-resistance layer 922, which has high resistance, can be
formed by doping GaN with a transition metal such as iron (Fe), thereby
enabling increased insulation.

[0006] However, gas including containing the transition metal, such as Fe,
used for doping remains in a growth furnace of an MOVPE system used to
form the high-resistance layer 922 and therefore the transition metal,
such as Fe, enters the electron travel layer 923, which is formed
subsequently to the formation of the high-resistance layer 922. In
particular, Fe enters the electron travel layer 923 to form a high-Fe
concentration region as illustrated in the distribution of Fe in the
high-resistance layer 922 and the electron travel layer 923 in FIG. 2B.
The electron travel layer 923 is made of i-GaN or the like. The entrance
of the transition metal, such as Fe, into the electron travel layer 923
reduces the mobility of electrons in the electron travel layer 923 to
cause an increase in on-resistance. The increase in thickness of the
electron travel layer 923 may be taken to reduce the on-resistance of the
electron travel layer 923. However, the increase in thickness of the
electron travel layer 923 causes an increase in leakage current.

[0007] Japanese Laid-open Patent Publication No. 2002-359256 is an example
of related art.

SUMMARY

[0008] According to an aspect of the embodiments, a semiconductor device
includes a buffer layer that is disposed over a substrate, a
high-resistance layer that is disposed over the buffer layer, the
high-resistance layer being doped with a transition metal for achieving
high resistance, a low-resistance region that is disposed in a portion of
the high-resistance layer or over the high-resistance layer, the
low-resistance region being doped with an impurity element for achieving
low resistance, an electron travel layer that is disposed over the
high-resistance layer including the low-resistance region, an electron
supply layer that is disposed over the electron travel layer, a gate
electrode that is disposed over the electron supply layer, and a source
electrode and a drain electrode that are disposed over the electron
supply layer.

[0009] The object and advantages of the invention will be realized and
attained by means of the elements and combinations particularly pointed
out in the claims.

[0010] It is to be understood that both the foregoing general description
and the following detailed description are exemplary and explanatory and
are not restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF DRAWINGS

[0011]FIG. 1 is an illustration of a conventional semiconductor device;

[0012] FIGS. 2A and 2B are illustrations of another conventional
semiconductor device;

[0013]FIG. 3 is a method for manufacturing a semiconductor device
according to a first embodiment;

[0014] FIGS. 4A to 4C are illustrations of steps of the method for
manufacturing the semiconductor device according to the first embodiment;

[0015] FIGS. 5A and 5B are structural views of the semiconductor device
according to the first embodiment;

[0016] FIGS. 6A to 6C are graphs illustrating properties of the
semiconductor device according to the first embodiment;

[0017] FIGS. 7A to 7C are illustrations of steps of a method for
manufacturing a semiconductor device according to a second embodiment;

[0018] FIGS. 8A and 8B are illustrations of steps of the method for
manufacturing the semiconductor device according to the second
embodiment;

[0019]FIG. 9 is a graph illustrating properties of the semiconductor
device according to the second embodiment;

[0020]FIG. 10 is a structural view of a modification of the semiconductor
device according to the second embodiment;

[0021] FIGS. 11A to 11C are illustrations of steps of a method for
manufacturing a semiconductor device according to a third embodiment;

[0022]FIG. 12 is an illustration of a step of the method for
manufacturing the semiconductor device according to the third embodiment;

[0023]FIG. 13 is a structural view of a modification of the semiconductor
device according to the third embodiment;

[0024]FIG. 14 is an illustration of a discretely packaged semiconductor
device according to a fourth embodiment;

[0025]FIG. 15 is a circuit diagram of a power supply system according to
the fourth embodiment; and

[0026]FIG. 16 is a structural view of a high-frequency amplifier
according to the fourth embodiment.

DESCRIPTION OF EMBODIMENTS

[0027] Hereinafter, embodiments are described. The same members are
denoted by the same reference numerals and will not be described in
detail.

First Embodiment

[0028] A method for manufacturing a semiconductor device according to a
first embodiment is described below with reference to FIGS. 3 and 4A to
4C. In this embodiment, the method uses an MOVPE system including two
growth furnaces for epitaxially growing semiconductor layers.

[0029] First, as illustrated in Step 102 (S102), a substrate 10 made of
SiC or the like is provided in one of the growth furnaces. In this
embodiment, the substrate 10 is made of SiC and may be made of a
semiconductor such as GaN or an insulator such as sapphire.

[0030] Next, as illustrated in Step 104 (S104), in this growth furnace, a
buffer layer 21 and a high-resistance layer 22 are formed. In particular,
as illustrated in FIG. 4A, the buffer layer 21 and the high-resistance
layer 22 are formed in series on the substrate 10 by MOVPE. The buffer
layer 21 and high-resistance layer 22 are formed at a reduced pressure in
such a state that the substrate 10 is heated.

[0031] The buffer layer 21 is made of a material including AlN and is
formed in such a manner that a trimethyl aluminum (TMAl) gas and an
ammonia (NH3) gas are supplied to this growth furnace. The buffer
layer 21 is also referred to as an AlN nucleation layer.

[0032] The high-resistance layer 22 has a thickness of 200 nm and is made
of GaN doped with Fe. The high-resistance layer 22 is formed in such a
manner that a trimethyl gallium (TMGa) gas, an NH3 gas, and a
ferrous chloride (FeCl2) gas for doping GaN with Fe, which acts as
an impurity element, are supplied to this growth furnace. The ferrous
chloride gas is generated by the reaction of iron with hydrochloric acid.
The feed rate of the ferrous chloride gas is controlled such that GaN is
doped with Fe at a given concentration. This allows the high-resistance
layer 22 to be formed on the buffer layer 21 such that the
high-resistance layer 22 is doped with Fe at a concentration of
1×1018 cm-3. In this embodiment, the high-resistance
layer 22 is doped with Fe, which acts as an impurity element, at a
concentration of 1×1017 cm-3 or more so as to have a
desired resistance. Examples of an impurity element used to dope the
high-resistance layer 22 include transition metals such as Ti, V, Cr, Mn,
Co, Ni, and Cu in addition to Fe.

[0033] Next, as illustrated in Step 106 (S106), the substrate 10 including
the high-resistance layer 22 is taken out of this growth furnace and is
then provided in the other growth furnace.

[0034] Next, as illustrated in Step 108 (S108), in the other growth
furnace, an electron travel layer 23 (Here, 23a illustrates a two
dimensional electron gas.), a spacer layer 24, an electron supply layer
25, and a capping layer 26 are formed. In particular, as illustrated in
FIG. 4B, the electron travel layer 23, the spacer layer 24, the electron
supply layer 25, and the capping layer 26 are formed in series on the
high-resistance layer 22. The electron travel layer 23, the spacer layer
24, the electron supply layer 25, and the capping layer 26 are formed at
a reduced pressure in such a state that the substrate 10 is heated.

[0035] The electron travel layer 23 has a thickness of about 100 nm and is
made of i-GaN. The electron travel layer 23 is formed in such a manner
that a TMGa gas and an NH3 gas are supplied to the other growth
furnace.

[0036] The spacer layer 24 has a thickness of about 3 nm and is made of
i-Al0.25Ga0.75N. The spacer layer 24 is formed in such a manner
that a TMAl gas, a TMGa gas, and an NH3 gas are supplied to the
other growth furnace.

[0037] The electron supply layer 25 has a thickness of about 20 nm and is
made of n-Al0.25Ga0.75N. The electron supply layer 25 is formed
in such a manner that a TMAl gas, a TMGa gas, an NH3 gas, and a
silane (SiH4) gas for doping Al0.25Ga0.75N with Si are
supplied to the other growth furnace. This allows the electron supply
layer 25 to be formed such that the concentration of Si, which acts as an
impurity element, in the electron supply layer 25 is 2×1018
cm-3.

[0038] The capping layer 26 has a thickness of about 5 nm and is made of
n-GaN. The capping layer 26 is formed in such a manner that a TMGa gas,
an NH3 gas, and an SiH4 gas for doping GaN with Si, which acts
as an impurity element, are supplied to the other growth furnace. This
allows the capping layer 26 to be formed such that the concentration of
Si in the capping layer 26 is 2×1018 cm-3.

[0039] Next, as illustrated in Step 110 (S110), electrodes are formed on
the capping layer 26. In particular, as illustrated in FIG. 4c, a gate
electrode 31, a source electrode 32, and a drain electrode 33 are formed
on the capping layer 26. A procedure for forming these electrodes is as
described below. A photoresist is applied to the capping layer 26, is
exposed using an exposure system, and is then developed, whereby a resist
pattern, which is not illustrated, including openings corresponding to
regions for forming the gate electrode 31, the source electrode 32, and
the drain electrode 33 is formed. Thereafter, a metal film is formed over
the resist pattern by vacuum vapor deposition or the like and is then
immersed in an organic solvent, whereby a portion of the metal film that
is disposed on the resist pattern is removed together with the resist
pattern. This allows the gate electrode 31, the source electrode 32, and
the drain electrode 33 to be formed.

[0040]FIG. 5A illustrates the semiconductor device according to this
embodiment and FIG. 5B illustrates the distribution of the Fe
concentration thereof. In this embodiment, after the high-resistance
layer 22 is formed, the other growth furnace, which is different from the
growth furnace used to form the high-resistance layer 22, is used to form
the electron travel layer 23 (Here, 23a illustrates a two dimensional
electron gas.) and the like. The other growth furnace is not used to form
any layer or film doped with Fe or the like. Thus, no gas including Fe is
present in the other growth furnace and therefore Fe hardly enters the
electron travel layer 23. This enables low on-resistance without causing
an increase in leakage current.

[0041] This is further described in detail with reference to FIGS. 6A to
6C. In FIGS. 6A to 6C, Curve 6A indicates properties of HEMTs
corresponding to the semiconductor device according to this embodiment,
Curve 6B indicates properties of HEMTs including no high-resistance
layer, and Curve 6C indicates properties of HEMTs each including such a
high-resistance layer as illustrated in FIG. 2A.

[0042] FIG. 6A illustrates the relationship between the thickness of each
electron travel layer made of i-GaN and the on-resistance (Ron). When the
electron travel layers are thin, the HEMTs which are indicated by Curve
6A and which correspond to the semiconductor device according to this
embodiment are lower in on-resistance than the HEMTs which are indicated
by Curve 6C and which include the high-resistance layer and are close in
on-resistance to the HEMTs which are indicated by Curve 6B and which
include no high-resistance layer.

[0043]FIG. 6B illustrates the relationship between the thickness of each
electron travel layer made of i-GaN and the off-current (Ioff). The
off-current is also referred to as leakage current. When the electron
travel layers are thin, the HEMTs which are indicated by Curve 6A and
which correspond to the semiconductor device according to this embodiment
are lower in leakage current than the HEMTs which are indicated by Curve
6B and which include no high-resistance layer and are substantially equal
in leakage current to the HEMTs which are indicated by Curve 6C and which
include the high-resistance layer.

[0044]FIG. 6c illustrates the relationship between the thickness of each
electron travel layer made of i-GaN and the threshold voltage (Vth). When
the electron travel layers are thin, the HEMTs which are indicated by
Curve 6A and which correspond to the semiconductor device according to
this embodiment are higher in threshold voltage than the HEMTs which are
indicated by Curve 6B and which include no high-resistance layer and are
substantially equal in threshold voltage to the HEMTs which are indicated
by Curve 6C and which include the high-resistance layer. An increase in
threshold voltage allows a normally off mode to be readily achieved.
Therefore, the semiconductor device according to this embodiment can be
rendered normally off because the electron travel layer 23 has a reduced
thickness.

[0045] In a step subsequent to the formation of the high-resistance layer
22, Fe or the like may possibly be diffused in the electron travel layer
23 by heat applied to the electron travel layer 23 during formation.
However, the degree of diffusion of Fe or the like in the electron travel
layer 23 in this case is low as compared to the case where Fe enters the
electron travel layer 23 because of an Fe-including gas remaining in the
growth furnace used to form the high-resistance layer 22.

[0046] As described above, the HEMTs corresponding to the semiconductor
device according to this embodiment have advantages similar to those of
the HEMT including the configuration illustrated in FIG. 1 and the HEMT
including the configuration illustrated in FIG. 2A, that is, advantages
that the on-resistance is low, the leakage current is small, and the
threshold voltage is high in the case of forming a thin electron travel
layer.

Second Embodiment

[0047] A method for manufacturing a semiconductor device according to a
second embodiment is described below with reference to FIGS. 7A to 7C,
8A, and 8B.

[0048] First, as illustrated in FIG. 7A, a buffer layer 21 and a
high-resistance layer 22 are formed in series on a substrate 10 by MOVPE.
The buffer layer 21 and the high-resistance layer 22 are formed at a
reduced pressure in such a state that the substrate 10 is heated. In this
embodiment, the substrate 10 is made of SiC and may be made of a
semiconductor such as GaN or an insulator such as sapphire.

[0049] The buffer layer 21 is made of a material including AlN. The buffer
layer 21 is formed in such a manner that a TMAl gas and an NH3 gas
are supplied to a growth furnace of an MOVPE system.

[0050] For example, the high-resistance layer 22 has a thickness of 200 nm
and is made of GaN doped with Fe. The high-resistance layer 22 is formed
in such a manner that a TMGa gas, an NH3 gas, and an FeCl2 gas
for doping GaN with Fe, which acts as an impurity element, are supplied
to the growth furnace. This allows the high-resistance layer 22 to be
formed on the buffer layer 21 such that the high-resistance layer 22 is
doped with Fe at a concentration of 1×1018 cm-3. In this
embodiment, the high-resistance layer 22 is doped with Fe, which acts as
an impurity element, at a concentration of 1×1017 cm-3 or
more so as to have a desired resistance. Examples of an impurity element
used to dope the high-resistance layer 22 include transition metals such
as Ti, V, Cr, Mn, Co, Ni, and Cu other than Fe.

[0051] Next, as illustrated in FIG. 7B, an alignment mark 111 is formed in
a surface portion of the high-resistance layer 22. In particular, after
the substrate 10 is taken out of the MOVPE system, a photoresist is
applied to the high-resistance layer 22, is exposed using an exposure
system, and is then developed, whereby a resist pattern, which is not
illustrated, including an opening corresponding to a region for forming
the alignment mark 111 is formed. Thereafter, the resist pattern is
dry-etched using a Cl2-including gas such that a portion of the
high-resistance layer 22 that is uncovered with the resist pattern is
removed, whereby the alignment mark 111 is formed. Dry-etching conditions
for forming the alignment mark 111 include an RF power of 200 W and a
bias power of 30 W.

[0052] Next, as illustrated in FIG. 7c, low-resistance regions 122 are
each formed in a given area of the high-resistance layer 22. In
particular, a photoresist is applied to the high-resistance layer 22, is
exposed using an exposure system, and is then developed, whereby a resist
pattern, which is not illustrated, including openings corresponding to
regions for forming the low-resistance regions 122 is formed. Thereafter,
Si or the like, which acts as an impurity element, is ion-implanted into
regions of the high-resistance layer 22 that are uncovered with this
resist pattern, whereby the low-resistance regions 122 are formed. In
this operation, Si is ion-implanted at a dose of 1×1013
cm-2 such that the concentration of Si in each low-resistance region
122 is 2×1018 cm-3. That is, the low-resistance regions
122 are formed in such a manner that regions of the high-resistance layer
22 that are used to form the low-resistance regions 122 are doped with Si
such that the concentration of Si in each low-resistance region 122 is
higher than the concentration of Fe, which acts as an impurity element,
in the high-resistance layer 22. The low-resistance regions 122 are not
located directly under a region for forming a gate electrode 31 below but
are each located directly under a region for forming a source electrode
32 or a drain electrode 33. Therefore, this resist pattern is formed in
such a manner that alignment is performed using the alignment mark 111
such that each of the low-resistance regions 122 is formed in a
corresponding one of the given areas. In the above description, Si, which
is an implanted impurity element, is used to form the low-resistance
regions 122. However, an impurity element, such as germanium (Ge) or
oxygen, other than Si may be used to form the low-resistance regions 122.

[0053] Next, as illustrated in FIG. 8A, an electron travel layer 23 (Here,
23a illustrates a two dimensional electron gas.), a spacer layer 24, an
electron supply layer 25, and a capping layer 26 are formed in series on
the high-resistance layer 22 including the low-resistance regions 122 by
MOVPE. In this operation, as described in the first embodiment, these
layers are preferably formed in a growth furnace of the MOVPE system that
is different from the growth furnace used to form the high-resistance
layer 22.

[0054] The electron travel layer 23 has a thickness of about 100 nm and is
made of i-GaN. The electron travel layer 23 is formed in such a manner
that a TMGa gas and an NH3 gas are supplied to this growth furnace.

[0055] The spacer layer 24 has a thickness of about 3 nm and is made of
i-Al0.25Ga0.75N. The spacer layer 24 is formed in such a manner
that a TMAl gas, a TMGa gas, and an NH3 gas are supplied to this
growth furnace.

[0056] The electron supply layer 25 has a thickness of about 20 nm and is
made of n-Al0.25Ga0.75N. The electron supply layer 25 is formed
in such a manner that a TMAl gas, a TMGa gas, an NH3 gas, and a
SiH4 gas for doping Al0.25Ga0.75N with Si, which acts as
an impurity element, are supplied to this growth furnace. This allows the
electron supply layer 25 to be formed such that the concentration of Si
in the electron supply layer 25 is 2×1018 cm-3.

[0057] The capping layer 26 has a thickness of about 5 nm and is made of
n-GaN. The capping layer 26 is formed in such a manner that a TMGa gas,
an NH3 gas, and a SiH4 gas for doping GaN with Si, which acts
as an impurity element, are supplied to this growth furnace. This allows
the capping layer 26 to be formed such that the concentration of Si in
the capping layer 26 is 2×1018 cm-3.

[0058] Next, as illustrated in FIG. 8B, the gate electrode 31, the source
electrode 32, and the drain electrode 33 are formed on the capping layer
26. A procedure for forming these electrodes is as described below. A
photo-resist is applied to the capping layer 26, is exposed using an
exposure system, and is then developed, whereby a resist pattern, which
is not illustrated, including openings corresponding to regions for
forming the gate electrode 31, the source electrode 32, and the drain
electrode 33 is formed. In this operation, this resist pattern is formed
in such a manner that alignment is performed using an alignment mark 111a
such that the gate electrode 31 is not located directly above one of the
low-resistance regions 122 but each of the source electrode 32 and the
drain electrode 33 is located directly above a corresponding one of the
low-resistance regions 122. Thereafter, a metal film is formed over this
resist pattern by vacuum vapor deposition or the like and is then
immersed in an organic solvent or the like, whereby a portion of the
metal film that is disposed on the resist pattern is removed together
with the resist pattern. This allows the gate electrode 31, the source
electrode 32, and the drain electrode 33 to be formed. As described
above, each of the source electrode 32 and the drain electrode 33 is
formed directly above a corresponding one of the low-resistance regions
122 and the gate electrode 31 is formed directly above a region other
than the low-resistance regions 122, that is, a region of the
high-resistance layer 22 that is in contact with the electron travel
layer 23. The electron travel layer 23, the spacer layer 24, the electron
supply layer 25, and the capping layer 26 are arranged in series on the
alignment mark 111, which is disposed in the surface portion of the
high-resistance layer 22. The same shape as the alignment mark 111 is
held in each of these layers, resulting in that the alignment mark 111a
is formed in a surface portion of the capping layer 26.

[0059] The semiconductor device according to this embodiment is an HEMT
and can be manufactured as described above. In this embodiment, a
two-dimensional electron gas (2DEG) 23a is formed in the electron travel
layer 23 and the electron distribution of the 2DEG 23a can be increased
directly under the source electrode 32 and the drain electrode 33.
Therefore, as indicated by the relationship between the thickness of each
electron travel layer and the on-resistance (Ron) illustrated in FIG. 9,
HEMTs which are indicated by Curve 9A and which correspond to the
semiconductor device according to this embodiment are lower in
on-resistance than HEMTs indicated by Curves 6A to 6C. The HEMTs
indicated by Curve 9A are substantially equal in leakage current (Ioff)
and threshold voltage (Vth) to HEMTs corresponding to the semiconductor
device according to the first embodiment. Thus, in the case of forming a
thin electron travel layer, the HEMTs corresponding to the semiconductor
device according to this embodiment have advantages: low on-resistance,
low leakage current, and high threshold voltage. The semiconductor device
according to this embodiment can be rendered normally off because the
electron travel layer 23 has a small thickness. In this embodiment, the
low-resistance regions 122 are formed in the high-resistance layer 22 as
described above. However, the high-resistance layer 22 may be replaced
with a low-resistance layer and a high-resistance region may be formed in
the low-resistance layer.

[0060] In the semiconductor device according to this embodiment, a gate
electrode may have a recess structure. In particular, as illustrated in
FIG. 10, the capping layer 26 and the electron supply layer 25 are partly
removed by etching or the like, whereby an opening is formed. A gate
electrode 131 is formed in the opening. The gate electrode 131 is formed
so as to have a recess structure as described above; hence, the electron
distribution of the 2DEG 23a can be reduced directly under the gate
electrode 131 and the threshold voltage can be rendered positive. This
allows a normally-off HEMT to be readily achieved.

Third Embodiment

[0061] A method for manufacturing a semiconductor device according to a
third embodiment is described below with reference to FIGS. 11A to 11C
and 12.

[0062] First, as illustrated in FIG. 11A, a buffer layer 21 and a
high-resistance layer 22 are formed in series on a substrate 10 by MOVPE.

[0063] The buffer layer 21 is made of a material including AlN. The buffer
layer 21 is formed in such a manner that a TMAl gas and an NH3 gas
are supplied to a growth furnace of an MOVPE system.

[0064] The high-resistance layer 22 has a thickness of 200 nm and is made
of GaN doped with Fe. The high-resistance layer 22 is formed in such a
manner that a TMGa gas, an NH3 gas, and an FeCl2 gas for doping
GaN with Fe, which acts as an impurity element, are supplied to the
growth furnace. This allows the high-resistance layer 22 to be formed on
the buffer layer 21 such that the high-resistance layer 22 is doped with
Fe at a concentration of 1×1018 cm-3.

[0065] Next, as illustrated in FIG. 11B, a low-resistance layer 223 is
formed on the high-resistance layer 22. The low-resistance layer 223 has
a thickness of about 100 nm and is made of n-GaN. The low-resistance
layer 223 is formed in such a manner that a TMGa gas, an NH3 gas,
and a SiH4 gas for doping GaN with Si, which acts as an impurity
element, are supplied to the growth furnace. This allows the
low-resistance layer 223 to be formed such that the concentration of Si
in the low-resistance layer 223 is 2×1018 cm-3. The
concentration of Si, which acts as an impurity element, in the
low-resistance layer 223 is preferably higher than the concentration of
Fe, which acts as an impurity element, in the high-resistance layer 22.
Examples of an impurity element used to dope the low-resistance layer 223
include Ge and oxygen in addition to Si. In this application, the
low-resistance layer 223 is referred to as a low-resistance region in
some cases.

[0066] Next, as illustrated in FIG. 11c, an electron travel layer 23, a
spacer layer 24, an electron supply layer 25, and a capping layer 26 are
formed in series on the low-resistance layer 223 by MOVPE. Here, 23a
illustrates a two dimensional electron gas.

[0067] The electron travel layer 23 has a thickness of about 100 nm and is
made of i-GaN. The electron travel layer 23 is formed in such a manner
that a TMGa gas and an NH3 gas are supplied to the growth furnace.

[0068] The spacer layer 24 has a thickness of about 3 nm and is made of
i-Al0.25Ga0.75N. The spacer layer 24 is formed in such a manner
that a TMAl gas, a TMGa gas, and an NH3 gas are supplied to the
growth furnace.

[0069] The electron supply layer 25 has a thickness of about 20 nm and is
made of n-Al0.25Ga0.75N. The electron supply layer 25 is formed
in such a manner that a TMAl gas, a TMGa gas, an NH3 gas, and an
SiH4 gas for doping Al0.25Ga0.75N with Si, which acts as
an impurity element, are supplied to the other growth furnace. This
allows the electron supply layer 25 to be formed such that the
concentration of Si in the electron supply layer 25 is 2×1018
cm-3.

[0070] The capping layer 26 has a thickness of about 5 nm and is made of
n-GaN. The capping layer 26 is formed in such a manner that a TMGa gas,
an NH3 gas, and a SiH4 gas for doping GaN with Si, which acts
as an impurity element, are supplied to the growth furnace. This allows
the capping layer 26 to be formed such that the concentration of Si in
the capping layer 26 is 2×1018 cm-3.

[0071] Next, as illustrated in FIG. 12, a gate electrode 31, a source
electrode 32, and a drain electrode 33 are formed on the capping layer
26. A procedure for forming these electrodes is as described below. A
photoresist is applied to the capping layer 26, is exposed using an
exposure system, and is then developed, whereby a resist pattern, which
is not illustrated, including openings corresponding to regions for
forming the gate electrode 31, the source electrode 32, and the drain
electrode 33 is formed. Thereafter, a metal film is formed over the
resist pattern by vacuum vapor deposition or the like and is then
immersed in an organic solvent or the like, whereby a portion of the
metal film that is disposed on the resist pattern is removed together
with the resist pattern. This allows the gate electrode 31, the source
electrode 32, and the drain electrode 33 to be formed.

[0072] The semiconductor device according to this embodiment is an HEMT
and can be manufactured as described above. In this embodiment, the
low-resistance layer 223 is formed on the high-resistance layer 22.
Therefore, even in the case where Fe is diffused from the high-resistance
layer 22, an increase in on-resistance can be suppressed. The
semiconductor device according to this embodiment can be rendered
normally off because the electron travel layer 23 has a reduced
thickness.

[0073] In the semiconductor device according to this embodiment, a gate
electrode may have a recess structure. In particular, as illustrated in
FIG. 13, the capping layer 26 and the electron supply layer 25 are partly
removed by etching or the like, whereby an opening is formed. A gate
electrode 131 is formed in the opening. The gate electrode 131 is formed
so as to have a recess structure as described above; hence, the electron
distribution of a 2DEG 23a can be reduced directly under the gate
electrode 131 and the threshold voltage can be rendered positive. This
allows a normally-off HEMT to be readily achieved.

Fourth Embodiment

[0074] A fourth embodiment is described below. This embodiment provides a
semiconductor device, a power supply system, and a high-frequency
amplifier.

[0075] The semiconductor device according to this embodiment is one
obtained by discretely packaging the semiconductor device according to
any one of the first to third embodiments. The semiconductor device
discretely packaged as described above is described with reference to
FIG. 14. FIG. 14 schematically illustrates an inner portion of the
discretely packaged semiconductor device. The arrangement of electrodes
illustrated in FIG. 14 is different from those described in the first to
third embodiments.

[0076] First, the semiconductor device manufactured in any one of the
first to third embodiments is cut by dicing or the like, whereby a
semiconductor chip 410 including a HEMT made of a GaN-based semiconductor
material is prepared. The semiconductor chip 410 is fixed on a lead frame
420 with a die attach adhesive 430 such as solder.

[0077] Next, a gate electrode 441 is connected to a gate lead 421 with a
bonding wire 431, a source electrode 442 is connected to a source lead
422 with a bonding wire 432, and a drain electrode 443 is connected to a
drain lead 423 with a bonding wire 433. The bonding wires 431, 432, and
433 are made of a metal material such as Al. In this embodiment, the gate
electrode 441 is a gate electrode pad and is connected to the gate
electrode 31 described in any one of the first to third embodiments.
Likewise, the source electrode 442 is a source electrode pad and is
connected to the source electrode 32 described in any one of the first to
third embodiments and the drain electrode 443 is a drain electrode pad
and is connected to the drain electrode 33 described in any one of the
first to third embodiments.

[0078] Next, resin sealing is performed by a transfer molding process
using a molding resin 440. This allows the semiconductor device, which
includes the discretely packaged HEMT made of the GaN-based semiconductor
material, to be manufactured.

[0079] The power supply system and high-frequency amplifier according to
this embodiment include the semiconductor device according to any one of
the first to third embodiments.

[0080] The power supply system according to this embodiment is described
below with reference to FIG. 15. The power supply system 460 according to
this embodiment includes a high-voltage primary circuit 461, a
low-voltage secondary circuit 462, and a transformer 463 placed between
the primary circuit 461 and the secondary circuit 462. The primary
circuit 461 includes an alternating-current power supply 464, a so-called
bridge rectifier circuit 465, a plurality of switching elements 466 (the
number thereof is four as illustrated in FIG. 15), and a single switching
element 467. The secondary circuit 462 includes a plurality of switching
elements 468 (the number thereof is three as illustrated in FIG. 15). In
an example illustrated in FIG. 15, the switching elements 466 and 467 of
the primary circuit 461 correspond to the semiconductor device according
to any one of the first to third embodiments. The switching elements 466
and 467 of the primary circuit 461 are preferably normally-off
semiconductor devices. The switching elements 468 used in the secondary
circuit 462 use common metal-insulator-semiconductor field-effect
transistors (MISFETs) made of silicon.

[0081] The high-frequency amplifier according to this embodiment is
described below with reference to FIG. 16. The high-frequency amplifier
470 according to this embodiment may be applied to, for example, a power
amplifier for base stations for mobile phones. The high-frequency
amplifier 470 according to this embodiment includes a digital
pre-distortion circuit 471, a mixer 472, a power amplifier 473, and a
directional coupler 474. The digital pre-distortion circuit 471
compensates for the non-linear distortion of an input signal. The mixer
472 mixes the input signal compensated for non-linear distortion with an
alternating-current signal. The power amplifier 473 amplifies the input
signal mixed with the alternating-current signal. With reference to FIG.
16, the power amplifier 473 includes the semiconductor device according
to any one of the first to third embodiments. The directional coupler 474
monitors the input signal and an output signal. In a circuit illustrated
in FIG. 16, switching allows the output signal to be mixed with the
alternating-current signal by the mixer 472 and to be transmitted to the
digital pre-distortion circuit 471.

[0082] While embodiments have been described above in detail, the
disclosure is not limited to specific embodiments. Various modifications
and variations can be made within the scope of the appended claims.

[0083] All examples and conditional language recited herein are intended
for pedagogical purposes to aid the reader in understanding the invention
and the concepts contributed by the inventor to furthering the art, and
are to be construed as being without limitation to such specifically
recited examples and conditions, nor does the organization of such
examples in the specification relate to a showing of the superiority and
inferiority of the invention. Although the embodiments of the present
invention have been described in detail, it should be understood that the
various changes, substitutions, and alterations could be made hereto
without departing from the spirit and scope of the invention.

Patent applications by Masato Nishimori, Atsugi JP

Patent applications by Toshihide Kikkawa, Machida JP

Patent applications by FUJITSU LIMITED

Patent applications in class SPECIFIED WIDE BAND GAP (1.5EV) SEMICONDUCTOR MATERIAL OTHER THAN GAASP OR GAALAS

Patent applications in all subclasses SPECIFIED WIDE BAND GAP (1.5EV) SEMICONDUCTOR MATERIAL OTHER THAN GAASP OR GAALAS