Stamp9G45

Technical Reference

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1. Introduction

The Stamp9G45 is intended to be used as a small size "intelligent" CPU module
as well as a universal Linux CPU card. It can be used anywhere where restricted
energy and space requirements play a role. The design of the Stamp9G45 is limited
to the processors core needs like DDRAM and Flash, thus giving the customer a
wide-ranged choice of configurations of the peripherals and environment. Featuring
an integrated LCD/TFT and touch controller applications with graphical needs can be
realized cost-efficient and individually.

The Stamp9G45 has all the necessary interfaces to support a huge variety of peripheral
devices. Equipped with a 16-Bit parallel bus it gives fast access to a number of chips
and additional devices.

The ARM architecture as a modern and widely supported processor architecture is currently
the platform of choice for medium performance embedded devices. Almost all major processor
manufacturers have ARM products in their portfolio.

The availability of the widespread operating system "Linux" for the ARM platform opens
access to a broad range of software, including tools, drivers, and software libraries.
Programs written for ARM can easily be employed on the PC platform for testing and debugging.

Examples of actual or potential applications are: protocol converters, measuring and test
equipment, data-logging, as well as simple or more complex control and automation tasks.

2. Scope

This document describes the most important hardware features of the Stamp9G45. It
includes all informations necessary to develop a customer specific hardware for the
Stamp9G45. The Operating System Linux is described in a further document.

The manual comprises only a brief description of the AT91SAM9G45 processor, as this
is already described in depth in the manual of the manufacturer Atmel. Descriptions
of the ARM core ARM926EJ‑S are available from Atmel and also at
http://www.arm.com. It is much recommended to have a look at these
documents for a thorough understanding of the processor and its integrated peripherals.

1. Mechanics

The Stamp9G45 was designed as a flexible CPU-Module, which can be connected to base
boards via 2x 100-pin fine pitch low profile Hirose
® FX8 connectors

The size of the Stamp9G45's PCB is only 53.6x38x6.0 mm fitting it in even the smallest
design. While having implemented the sensible CPU, DDRAM and Flash design it still
exports almost all possible CPU-Pins on it's connectors to allow a flexible design
on base boards

The Stamp9G45 has an on-board Micro SD-Card slot, thus supporting even large memories
needs in its compact design

2. AT91SAM9G45 Processor Core

The AT91SAM9G45 runs at 400 MHz with a memory bus frequency of 132 MHz.

Here are some of the most important features of the SAM9G45 ARM926EJ-S core:

Some of these features - like Jazelle - are currently not supported by the operating system of the product.

3. Memory

The Stamp9G45 is equipped with two 32-Bit external bus interfaces, EBI0 and EBI1. Only a 16-Bit
bus of EBI0 is exported on the interface connectors of the Stamp9G45. The memory
bus voltage is 1.8 V and runs at 133 MHz. The memory bus voltage is different
from normal operating voltage, which is 3.3 V. This has to be considered, when
designing additional peripherals connected to the memory bus. Eventually buffer
chips are necessary.

3.1. NAND Flash

The Stamp9G45 is equipped with a 128 MB NAND flash with 100000 erase and write
cycles.It is organized in 128KB blocks. Customer specific adaptations are
possible up to 1 GB on-board NAND flash. It is connected to chip select three
(NCS3) of the microcontroller.

NAND flash has a different organisation of transistors than the commonly
used NOR flash. While it allows a much higher density and thus an increase
in storage capacity, there are some differences which need to be kept in
mind.

Typically, NAND flash is organized in pages and blocks, similar to hard
disks. Pages are 512, 2048 or 4096 bytes in size, typical block sizes are
16, 128, 256 or 512 KB. Reading and programming are performed on a page
basis. Programming can only be done sequently in one block.

Additionally, NAND flash requires bad block management, either by the
driver software or by a separate controller chip. Most NAND devices are
shipped with bad blocks. These are identified and marked according to a
specified bad block strategy. Further bad blocks may be detected during
runtime. They are detected via an ECC (error correcting code). If a bad
block is detected, the data is written to a different, good block, and the
bad block table is updated. So the overall memory capacity gradually
shrinks as more and more blocks are marked bad.

This error detection is done by software like U-boot and Linux.
Additionally, NAND flash is subject to a limited number of write and erase
cycles. These are typically 100.000 cycles per block. So it is highly
recomended to use wear levelling filesystems.

3.2. LPDDR-SDRAM

The Stamp9G45 is equipped with 128MB LPDDR-SDRAM (Low power DDR-SDRAM). Customer
specific adaptations allow configurations up to 512MB. In 128MB and 256MB
configurations, the LPDDR-SDRAM is connected to EBI0. The external Bus is not
affected. In 512MB configuration 256MB of the LPDDR-SDRAM are
connected to chip select one (NCS1) of the micrcontroller's EBI1.

DDR-SDRAM allows random access to any of its memory area and is volatile memory.
DDR-SDRAM (Double Data Rate) takes over data at the rising and falling edge of
a clock pulse, thus achieving almost twice the bandwidth than a similar connected
SDRAM. It has a synchronous interface, that means it waits for a clock signal before
responding to control inputs and is therefore synchronized with the CPU bus. The
clock is used to drive a final state machine in the chip, which allows to accept
new instructions, before the previous one has finished executing.

3.3. EEPROM

The Stamp9G45 is equipped with a 128 bytes EEPROM, connected to the
Dallas™ 1 wire bus.

EEPROM stands for Electrically Erasable Programmable Read-Only Memory and is non-volatile memory, which is used to store small amounts of data like calibration or configuration data. EEPROMS are byte-wise erasable, thus allowing true random access.

3.4. SRAM

The Stamp9G45's microcontroller is equipped with 64 KB internal SRAM.
The internal SRAM can be accessed in one bus cycle and may be used for
time critical sections of code or interrupt handlers.

4. Bus Matrix

The bus matrix of AT91SAM-controllers allows many master and slave devices
to be connected independently of each other. Each master has a decoder and
can be defined specially for each master. This allows concurrent access of
masters to their slaves (provided the slave is available).

The bus matrix is thus the bridge between external devices connected to the EBI, the microcontroller's embedded peripherals and the CPU core.

Master 0

ARM926™ Instruction

Master 1

ARM926™ Data

Master 2

PDC

Master 3

USB HOST OHCI

Master 4

DMA

Master 5

DMA

Master 6

ISI Controller DMA

Master 7

LCD DMA

Master 8

Ethernet MAC DMA

Master 9

USB Device High Speed DMA

Master 10

USB Host High Speed EHCI DMA

Master 11

Reserved

Table 4.1. Bus Matrix Masters

Slave 0

Internal SRAM

Slave 1

Internal ROM

USB OHCI

USB EHCI

UDP High Speed RAM

LCD User Interface

Reserved

Slave 2

DDR Port 0

Slave 3

DDR Port 1

Slave 4

DDR Port 2

Slave 5

DDR Port 3

Slave 6

External Bus Interface

Slave 7

Internal Peripherals

Table 4.2. Bus Matrix Slaves

5. Advanced Interrupt Controller (AIC)

The core features of the Advanced Interrupt Controller are:

32 Internal or External Interrupt Sources

8-level Priority Controller

Level Sensitive or Edge Triggered

Programmable Polarity for External Sources

Moreover, all PIO lines can be used to generate a PIO interrupt. However, the PIO lines
can only generate level change interrupts, that is, positive as well as negative edges
will generate an interrupt. The PIO interrupt itself (PIO to AIC line) is usually programmed
to be level-sensitive. Otherwise interrupts will be lost if multiple PIO lines source an interrupt
simultaneously.

6. Battery Backup

The following parts of the AT91SAM9G45 Processor can be backed-up by a battery:

Slow Clock Oscillator

Real Time Timer

Reset Controller

Shutdown Controller

RTC

General Purpose Backup Registers

It is recommended to always use a backup power supply (normally a battery) in order
to speed up the boot-up time and to avoid reset problems.

7. Reset Controller (RSTC)

The embedded microcontroller has an integrated Reset Controller which samples the backup and the core voltage. The presence of a backup voltage (VDDBU) when the card is powered down speeds up the boot time of the microcontroller.

8. Serial Number

Every Stamp9G45 has a unique 48-bit hardware serial number chip which can be used by application software.
The chip is a Dallas® one-wire-chip. A Linux driver is provided.
Additionally it functions as the 128 Byte EEPROM.

9. Peripheral Input/Output Controller (PIO)

The Stamp9G45 has a maximum of 105 freely programmable digital I/O ports on its
connectors. These pins are also used by other peripheral devices.

The Parallel Input/Output Controller(PIO) manages up to 32 programmable I/O ports. Each I/O port is associated with a bit number in the 32 bit register of the user interface. Each I/O port may be configured for general purpose I/O or assigned to a function of an integrated peripheral device. In doing so multiplexing with multiple integrated devices is possible. That means a pin may be used as GPIO or only as one of the peripheral functions. The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write operation.

The following characteristics are individually configurable for each PIO pin:

PIO enable

Peripheral enable

Output enable

Output level

Write Enable

Level change interrupt

Glitch filter: pulses that are lower than a half clock cycle are ignored

Open-drain outputs

Pull-up resistor

All configurations as well as the pin status can be read back by using the appropriate status register. Multiple pins of each PIO can also be written simultaneously by using the synchronous output register.

For interrupt handling, the PIO Controllers are considered as user peripherals. This means that the PIO Controller interrupt lines are connected among the interrupt sources 2 to 31. Refer to the PIO Controller peripheral identifier Table B.1, “Peripheral Identifiers” to identify the interrupt sources dedicated to the PIO Controllers. The PIO Controller interrupt can be generated only if the PIO Controller clock is enabled.

A number of the PIO signals might be used internally on the module. Care has to be taken when accessing the PIO registers in order not to change the settings of these internal signals, otherwise a system crash is likely to happen.

10. Clock Generation

10.1. Processor Clocks

The AT91SAM9G45 has no PLLB, but provides the 480 MHz USB Clock via a UPLL.

The CPU generates its clock signals based on two crystal oscillators: One
slow clock (SLCK) oscillator running at 32.768 KHz and one main clock
oscillator running at 18.432 MHz. The slow clock oscillator also serves as
the time base for the real time timer. It draws a minimum of current (a few
micro-Amps) and can therefore be backeded up by a small lithium battery
when the board is powererd down.

From the main clock oscillator, the CPU generates two further clocks by
using two PLLs. PLLA provides the processor clock (PCK) and the master
clock (MCK). PLLB typically provides the 48 MHz USB clock and is normally
used only for this purpose. The clocks of most peripherals are derived from
MCK. These include EBI, USART, SPI, TWI, SSC, PIT and TC.

Some peripherals like the programmable clocks and the timer counters (TC)
can also run on SLCK. The real time timer (RTT) always runs on SLCK.

Clock

Frequency

Source

PCK (Processor Clock)

800 MHz

PLLA

MCK (Master Clock)

133 MHz

PCK/3

USB Clock

480 MHz

UPLL

Slow Clock

32.768 KHz

Slow Clock Oscillator

Table 4.3. AT91SAM9G45 Clocks

10.2. Programmable Clocks

The programmable clocks can be individually programmed to derive their input from SLCK, PLLA, PLLB and Main Clock. Each PCK has a divider of 2, 4, 8, 16, 32 or 64.

The Stamp9G45 features two programmable clocks PCK0, PCK1.

11. Power Management Controller (PMC)

11.1. Function

The PMC has a Peripheral Clock register which allows to individually enable or disable the
clocks of all integrated peripherals by using their "Peripheral Identifier"
(see Table B.1, “Peripheral Identifiers”). The System Clock
register allows to enable or disable each of the following clocks individually:

Processor Clock

ISI Clock

USB Host Clock (common for both channels)

USB Device Clock

Programmable Clocks

The PMC status register provides "Clock Ready" or, respectively, "PLL Lock" status bits
for each of these clocks. An interrupt is generated when any of these bits changes from
0 to 1. The PMC provides status flags for the

Main Oscillator

Master Clock

PLLA

PLLB

Programmable Clocks

The Main Oscillator frequency can be measured by using the PMC Main Clock Frequency register.
The SLCK is used as reference for the measurement.

11.2. Power Management

Using power management can dramatically reduce the power consumption of an Embedded Device.
Via the PMC various clocks can be disabled or their speed can be reduced:

stopping the PLLs (PLLA and / or PLLB)

stopping the clocks of the various peripherals

reducing the clock rates of peripherals, especially by changing MCK.

The PMC supports the following power-saving features: Idle mode and power-down mode. Please
note that not every operating system supports these modes.

Idle Mode. In idle mode, the processor clock will be re-enabled by any interrupt. The peripherals,
however, are only able to generate an interrupt if they still have a clock, so care has to be
taken as to when a peripheral can be powered down.

Power-down Mode.
In many cases a system waits for a user action or some other rare event. In such a case, it
is possible to change MCK to SLCK. Any external event which changes the state on peripheral
pins (not the USB) can then be detected by the PIO controller or the AIC.

It should also be taken into account that when a PLL is stopped it will take some time to
restart it. Changing the PLL frequencies or stopping them can therefore be done only at a
moderate rate. If short reaction times are required, this is not a choice.

Additionally, the following measures can reduce power consumption considerably:

switching off the TFT supply voltage

putting peripheral chips like Ethernet controller and / or PHY or serial driver devices in power down mode

putting the SDRAM into self-refresh mode

12. Real-time Timer (RTT)

The Real-time Timer is a 32-bit counter combined with a 16-bit prescaler running at Slow Clock (SLCK = 32768 Hz). As the RTT keeps running if only the backup supply voltage is available, it is used as a Real-time clock.

The RTT can generate an interrupt every time the prescaler rolls over. Usually the RTT is configured to generate an interrupt every second, so the prescaler will be programmed with the value 7FFFh.

The RTT can also generate an alarm if a preprogrammed 32-bit value is reached by the counter.

13. Timer Counter (TC)

The Stamp9G45 features two blocks of timer counters with three counters each. Due to
multiplexing four timer counters may be used with external signals.

The TC consists of three independent 16-bit Timer/Counter units. They may be cascaded to form a 32-bit or 48-bit timer/counter. The timers can run on the internal clock sources MCK/2, MCK/8, MCK/32, MCK/128, SLCK or the output of another timer channel. External clocks may be used as well as the counters can generate signals on timer events. They also can be used to generate PWM signals.

14. Periodic Interval Timer (PIT)

The PIT consists of a 20-bit counter running on MCK / 16. This counter can be preloaded with any value between 1 and 220. The counter increments until the preloaded value is reached. At this stage it rolls over and generates an interrupt. An additional 12-bit counter counts the interrupts of the 20 bit counter.

The PIT is intended for use as the operating system’s scheduler interrupt.

15. Watchdog Timer

The watchdog timer is a 12-bit timer running at 256 Hz (Slow Clock / 128). The maximum watchdog timeout period is therefore equal to 16 seconds. If enabled, the watchdog timer asserts a hardware reset at the end of the timeout period. The application program must always reset the watchdog timer before the timeout is reached. If an application program has crashed for some reason, the watchdog timer will reset the system, thereby reproducing a well defined state once again.

The Watchdog Mode Register can be written only once. After a processor reset, the watchdog is already activated and running with the maximum timeout period. Once the watchdog has been reconfigured or deactivated by writing to the Watchdog Mode Register, only a processor reset can change its mode once again.

16. Real-time Clock (RTC)

The Real-time clock combines a complete time-of-day clock with alarm, a two-hundred-year Gregorian calendar and a programmable periodic interrupt.
The time and calendar values are coded in BCD format.

17. True Random Number Generator (TRNG)

The True Random Generator (TRNG) passes the American NIST Special Publication 800-22 and the Diehard Random Tests Suites.
It provides a 32-bit value every 84 clock cycles.

18. Peripheral DMA Controller (PDC)

The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals
and the on- and/or off-chip memories. The PDC contains unidirectional and bidirectional
channels. The full-duplex peripherals feature unidirectional channels used in pairs
(transmit only or receive only). The half-duplex peripherals feature one bidirectional
channel. Typically full-duplex peripherals are USARTs, SPI or SSC. The MCI is a half
duplex device.

The user interface of each PDC channel is integrated into the user interface of the peripheral it serves. The user interface of unidirectional channels (receive only or transmit only), contains two 32-bit memory pointers and two 16-bit counters, one set (pointer, counter) for current transfer and one set (pointer, counter) for next transfer. The bidirectional channel user interface contains four 32-bit memory pointers and four 16-bit counters. Each set (pointer, counter) is used by current transmit, next transmit, current receive and next receive.

Using the PDC removes processor overhead by reducing its intervention during the transfer. This significantly reduces the number of clock cycles required for a data transfer, which improves microcontroller performance.
To launch a transfer, the peripheral triggers its associated PDC channels by using transmit and receive signals. When the programmed data is transferred, an end of transfer interrupt is generated by the peripheral itself. There are four kinds of interrupts generated by the PDC:

End of Receive Buffer

End of Transmit Buffer

Receive Buffer Full

Transmit Buffer Empty

The "End of Receive Buffer" / "End of Transmit Buffer" interrupts signify that the DMA counter has reached zero. The DMA pointer and counter register will be reloaded from the reload registers ("DMA new pointer register" and "DMA new counter register") provided that the "DMA new counter register" has a non-zero value. Otherwise a "Receive Buffer Full" or, respectively, a "Transmit Buffer Empty" interrupt is generated, and the DMA transfer terminates. Both reload registers are set to zero automatically after having been copied to the DMA pointer and counter registers.

19. Debug Unit (DBGU)

The Debug Unit is a simple UART which provides only RX/TX lines. It is used as a simple serial console for Firmware and Operating Systems.

20. JTAG Unit

The JTAG unit can be used for hardware diagnostics, hardware initialization, flash memory programming, and debug purposes. The JTAG unit supports two different modes, namely the "ICE Mode", and the "Boundary Scan" mode. It is normally jumpered for "ICE Mode".

JTAG interface devices are available for the unit. However, the use of them is not within the scope of this document.

21. Two-wire Interface (TWI)

The TWI is also known under the expression "I2C-Bus", which is a trademark of Philips and may therefore not be used by other manufacturers. However, interoperability is guaranteed. The TWI supports both master or slave mode.

The TWI uses only two lines, namely serial data (SDA) and serial clock (SCL). According to the standard, the TWI clock rate is limited to 400 kHz in fast mode and 100 kHz in normal mode, but configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies.

22. Multimedia Card Interface (MCI)

The Stamp9G45 features a onboard Micro-SD-Card slot, which is connected to the MCI-B interface of the microcontroller.
The MCI-A interface is provided for external additional use.

The MCI includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead. The MCI supports stream, block and multi-block data read and write, and is compatible with the Peripheral DMA Controller (PDC) channels, minimizing processor intervention for large buffer transfers.

The MCI operates at a rate of up to Master Clock divided by 2 and supports the interfacing of 2 slot(s). Each slot may be used to interface with a MultiMediaCard bus (up to 30 Cards) or with a SD Memory Card. Only one slot can be selected at a time (slots are multiplexed). A bit field in the SD Card Register performs this selection.

The SD Memory Card communication is based on a 9-pin interface (clock, command, four data and three power lines) and the MultiMedia Card on a 7-pin interface (clock, command, one data, three power lines and one reserved for future use).
The SD Memory Card interface also supports MultiMedia Card operations. The main differences between SD and MultiMedia Cards are the initialization process and the bus topology.

23. USB Host Port (UHP)

In the current revision of the AT91SAM9G45 USB High speed is not working. It will work in the processor's next revision, which is expected in august 2011.
The Stamp9G45 integrates two USB host ports supporting speeds up to 480 MBit/s. USB Host Port A is connected
directly to the transceiver, USB Host Port B is multiplexed with the USB device port. Only one of them can be used at a time.

The controller is fully compliant with the Enhanced HCI(EHCI) specification. It supports both High-speed 480 Mbps and Full-speed 12 Mbps devices.

The USB Host Port (UHP) interfaces the USB with the host application. It handles Open HCI protocol (Open Host Controller Interface) as well as USB v2.0 Full-speed and Low-speed protocols.

The USB Host Port integrates a root hub and transceivers on downstream ports. It provides several high-speed half-duplex serial communication ports. Up to 127 USB devices (printer, camera, mouse, keyboard, disk, etc.) and an USB hub can be connected to the USB host in the USB "tiered star" topology.

24. USB Device Port (UDP)

In the current revision of the AT91SAM9G45 USB High speed is not working. It will work in the processor's next revision, which is expected in august 2011.
The Stamp9G45 integrates one USB device port supporting speeds up to 480 MBit/s. It is multiplexed with the USB Host Port B.
Only one of them can be used at a time.

The controller is fully compliant with the Enhanced HCI(EHCI) specification. It supports both High-speed 480 Mbps and Full-speed 12 Mbps devices.

The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification. The USB device port enables the product to act as a device to other host controllers.

The USB device port can also be implemented to power on the board. One I/O line may be used by the application to check that VBUS is still available from the host. Self-powered devices may use this entry to be notified that the host has been powered off. In this case, the pullup on DP must be disabled in order to prevent feeding current to the host. The application should disconnect the transceiver, then remove the pullup.

25. Ethernet MAC (EMAC)

The EMAC module implements a 10/100 MBit/s Ethernet MAC compatible with the IEEE 802.3 standard using an address checker, statistics and control registers, receive and transmit blocks, and a DMA interface.

The address checker recognizes four specific 48-bit addresses and contains a 64-bit hash register for matching multicast and unicast addresses. It can recognize the broadcast address of all ones, copy all frames, and act on an external address match signal.

An individual 48-bit MAC address (ETHERNET hardware address) is allocated to each
product. This number is stored in flash memory. It is recommended not to change
the MAC address in order to comply with IEEE Ethernet standards.

To completely implement ethernet an additional physical layer interface is needed (PHY). A sample implementation is found on the Starterkit Board.

The USART supports the connection to the Peripheral DMA Controller, which enables data transfers to the transmitter and from the receiver. The PDC provides chained buffer management without any intervention of the processor.

Six different modes are implemented within the USARTs:

Normal (standard RS232 mode)

RS485

Hardware Handshaking

ISO7816 Protocol: T=0 or T=1

IrDA

RS485.
In RS485 operating mode the RTS pin is automatically driven high during transmit operations. If RTS is connected to the "enable" line of the RS485 driver, the driver will thus be enabled only during transmit operations.

Hardware Handshaking.
The hardware handshaking feature enables an out-of-band flow control by automatic management of the pins RTS and CTS. The receive DMA channel must be active for this mode. The RTS signal is driven high if the receiver is disabled or if the DMA indicates a buffer full condition. As the RTS signal is connected to the CTS line of the connected device, its transmitter is thus prevented from sending any more characters.

ISO7816.
The USARTs have an ISO7816-compatible mode which permits interfacing with smart cards and Security Access Modules (SAM). Both T=0 and T=1 protocols of the ISO7816 specification are supported.

IrDA.
The USART features an infrared (IrDA) mode supplying half-duplex point-to-point wireless communication. It includes the modulator and demodulator which allows a glueless connection to the infrared transceivers. The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data transfer speeds ranging from 2.4 kb/s to 115.2 kb/s.

Signals of the Serial Interfaces.
All UARTs/USARTs have one receiver and one transmitter data line (full duplex). Not all USARTs are implemented with full modem control lines. Furthermore the available lines depend largely on the used multiplexing.
Most modem control lines can be implemented with standard digital ports.

Hardware Interrupts.
There are several interrupt sources for each USART:

Iteration: the maximum number of repetitions has been reached (ISO7816 mode only)

Please refer to the chapter about the DMA unit (PDC) for a description of the "Buffer Full" and "End of Receive / Transmit Buffer" events.

27. Synchronous Peripheral Interface (SPI)

The Stamp9G45 features two SPI ports, with four respectively one chipselect available.

The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system.

The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the "master" which controls the data flow, while the other devices act as "slaves" which have data shifted into and out by the master.

A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master generates a separate slave select signal for each slave (NPCS). The SPI system consists of two data lines and two control lines:

Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input(s) of the slave(s).

Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. There may be no more than one slave transmitting data during any particular transfer.

Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted. The SPI baudrate is Master Clock (MCK) divided by a value between 1 and 255

Slave Select (NSS): This control line allows slaves to be turned on and off by hardware.

Each SPI Controller has a dedicated receive and transmit DMA channel.

28. Synchronous Serial Controller (SSC)

The Stamp9G45 has one SSC interface available, depending on the multiplexing of the pins.

The SSC supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc.

The SSC has separated receive and transmit channels. Each channel has a data, a clock and a frame synchronization signal (RD, RK, RF, resp. TD, TK, TF).
Both a receive and a transmit DMA channel are assigned to each SSC.

29. AC97 Controller (AC97C)

AC97 Component Specification 2.2 compliant AC97 digital controller. It supports mono or stereo up to 20 bit sample length and features a sampling rate up to 48 KHz.

Pin

Description

Type

AC97CK

12.288-MHz bit-rate clock

Input

AC97RX

SDATA_IN

Input

AC97FS

48-KHz frame indicator

Output

AC97TX

SDATA_OUT

Output

Table 4.4. AC97 I/O Lines

30. Image Sensor Interface (ISI)

The Image Sensor Interface (ISI) supports direct connection to the ITU-R BT. 601/656 8-bit mode compliant sensors and up to 12-bit grayscale sensors. It receives the image data stream from the image sensor on the 12-bit data bus. This module receives up to 12 bits for data, the horizontal and vertical synchronizations and the pixel clock. The reduced pin count alternative for synchronization is supported for sensors that embed SAV (start of active video) and EAV (end of active video) delimiters in the data stream.

The Image Sensor Interface interrupt line is generally connected to the Advanced Interrupt Controller and can trigger an interrupt at the beginning of each frame and at the end of a DMA frame transfer. If the SAV/EAV synchronization is used, an interrupt can be triggered on each delimiter event.

For 8-bit color sensors, the data stream received can be in several possible formats: YCbCr 4:2:2, RGB 8:8:8, RGB 5:6:5 and may be processed before the storage in memory. The data stream may be sent on both preview path and codec path if the bit CODEC_ON in the ISI_CR1 is one. To optimize the bandwidth, the codec path should be enabled only when a capture is required.

In grayscale mode, the input data stream is stored in memory without any processing. The 12-bit data, which represent the grayscale level for the pixel, is stored in memory one or two pixels per word, depending on the GS_MODE bit in the ISI_CR2 register. The codec datapath is not available when grayscale image is selected.

31. LCD controller

The LCD controller supports single and double scan monochrome and color passive STN LCD modules
and single scan active TFT LCD modules with a resolution of up to 2048x2048 with a color depth of
up 24 bits per pixel.

The LCD controller relies on a relatively simple frame buffer concept, which means that all
graphics and character functions have to be implemented in software: character sets and graphic
primitives are not integrated in the controller.

31.1. LCDC Initialisation and LCD Power Sequencing

LCD cells (pixels) should not be subjected to DC power for prolonged periods of time, as
chemical decomposition might take place. The LCD controller therefore provides for a strict
AC control of the LCD pixels. To do so, the LCD controller has to be initialized appropriately.
Switching on the LCD supply voltage therefore has to take place after the LCDC initialization
or shortly before.

Accordingly, the LCDC should not be powered down without deactivating the LCD supply voltage.
The same is true if the LCDC is stopped indirectly by stopping the respective clock source,
namely the PLLA.

The LCD backlight supply is not involved in these considerations. It may switched on or off
at any time independently of the state of the LCDC.

31.2. LCDC Frame Buffer

The LCDC Frame Buffer typically resides in the external RAM.

The LCDC video memory is organized as a frame buffer in a straight forward way. It supports
color depths of 1, 2, 4, 8, 16, or 24 bit per pixel. The video data is stored in a packed form
with no unused bits in the video memory.

The color resolutions of 1, 2, 4, and 8 bpp (bits per pixel) use a palette table which is made
up of 16-bit entries. The value of each pixel in the frame buffer serves as an index into the
palette table. The value of the respective palette table entry is output to the display by the LCDC,
see Table 4.5, “LCDC palette entry”.

Bit[14..10]

Bit[9..5]

Bit[4..0]

Blue[7..3]

Green[7..3]

Red[7..3]

Table 4.5. LCDC palette entry

The bits 2..0 of each color channel are not used in the palettized configuration — they are
set to 0.

The same scheme as above is used in the 16-bit color resolution configuration, although in this case
the frame buffer entry is output directly to the display instead of indexing a palette table.

If the LCD Module has lower color resolution (fewer bits per color component), only the most significant
bits of each component are used.

The Linux frame buffer driver offers a function which returns the information about the frame buffer
structure including the assignment of each frame buffer bit to a color channel bit. It is recommended
that graphics software uses this function in order to achieve a correct color representation.

32. Touch Screen ADC Controller (TSADCC)

The Stamp9G45 has additional to touch panel support three ADC channels available.

The Touch Screen ADC Controller is a 10-bit Analog-to-Digital Converter supporting resistive touch screen panels. It can be used as
Touch Screen Controller, ADC or both supporting eight lines maximum. It integrates a 8-to-1 analog multiplexer for analog to digital
conversions of up to 8 analog lines, four power switches that measure both axis positions and a pen-interrupt and pen-loss switch.

The conversions extend from 0V to TSADVREF, an external voltage reference for better accuracy. It supports 8-bit or 10-bit resolution mode.
Every channel can be enabled and disabled seperately.
It supports 10-bit 384 Ksamples/sec.

1. Ethernet Controller (EMAC)

Please take care of the specific layout requirements of the Ethernet port when
designing a base board. The two signals of the transmitter pair (ETX+ and ETX-)
should be routed in parallel (constant distance, e.g. 0.5mm) with no vias on
their way to the RJ45-jack. The same is true for the receiver pair (ERX+ and ERX-).
No other signals should be crossing or get next to these lines. If a ground plane
is used on the base board, it should be omitted in the vicinity of the Ethernet signals.

A 1nF / 2kV capacitor should be connected between board ground and chassis ground
(which is usually connected to the shield of the RJ45-jack).

2. USB

2.1. USB Host Controller (UHP)

External Parts.
A few external parts are required for the proper operation of the UHP:

No pull-down resistors are needed.

No series resistors are needed.

Small capacitors (e.g. 15pF) to ground on each line (optional).

ESD protection devices are recommended for applications which are subject to external contact. The restrictions with regard to capacitive loading have to be applied when selecting a protection device.

A circuit to generate the 5V VBUS supply voltage.

VBUS considerations for USB Host.
A USB host port has to provide a supply voltage VBUS of 5V +- 5% which has to be able to source a maximum of 500mA, or 100mA in case of battery operation. Please refer to the appropriate rules in the USB specification. A low ESR capacitor of at least 120µF has to be provided on VBUS in order to avoid excessive voltage drops during current spikes.

VBUS has to have an over-current protection. The over-current drawn temporarily on VBUS must not exceed 5A. Polymeric PTCs or solid state switches are recommended by the specification. Suitable PPTCs are "MultiFuse" (Bourns), "PolyFuse" (Wickmann/Littelfuse), "PolySwitch" (Raychem/Tyco).

It is required that the over-current condition can be detected by software, so that VBUS can be switched off or be reduced in power in such a case.

Layout considerations.
If external resistors are needed, they should be placed in the vicinity of the module's connector. The two traces of any of the differential pairs (USB-Host A+ and USB-Host A- , as well as USB-Host B+ and USB-Host B-) should not encircle large areas on the base board, in order to reduce signal distortion and noise. The are preferably routed closely in parallel to the USB connector.

USB High-Speed.
If designing USB High-Speed a wave impedance of 90 Ω on the traces should be respected. The traces shoud be routed as short as possible and in parallel
with as low parallel capacitance as possible.

2.2. USB Device Controller (UDP)

External Parts.
A few external parts are required for the proper operation of the UDP:

ESD protection devices are recommended for applications which are subject to external contact. The restrictions with regard to capacitive loading have to be applied when selecting a protection device.

The USB specification demands a switchable pull-up resistor of 1.5 kΩ on USB-Device+ which identifies the UDP as a full speed device to the attached host controller. On this module, this resistor is integrated on the chip. It can be switched on or off using the "USB Pad Pull-up Control Register", which is part of the "Bus Matrix User Interface" (not the "USB Device Port User Interface", as one might expect). This pull-up resistor is required to be switchable in order not to source current to an attached but powered down host. This would otherwise constitute an irregular condition on the host. The software has to take care of this fact.

The capacitors are intended to improve the signal quality (edge rate
control) depending on the specific design. They are not mandatory. The
total capacitance to ground of each USB pin, the PCB trace to the series
resistor, and the capacitor must not exceed 75pF.

Operation with VBUS as a Supply.
Special care has to be taken if the module is powered by the VBUS supply. Please refer to the appropriate rules in the USB specification with regard to inrush current limiting and power switching. As the module draws more than 100mA in normal mode, it is a "high-power" device according to the specification (<100mA = "low-power", 100..500mA = "high-power"). It therefore requires staged switching which means that at power-up it should draw not more than 100mA on VBUS. The capacitive load of a USB device on VBUS should be not higher than 10µF.

Layout considerations.
The external resistors should be placed in the vicinity of the module's connector. The traces of the differential pair (USB-Device+ and USB-Device- ) should not encircle large areas on the base board, in order to reduce signal distortion and noise. The are preferably routed closely in parallel to the USB connector.

3. Memory Bus

On the Stamp9G45 the memory bus is driven with 1.8V. This affects the voltages of PIOC-controller pins, they are 1.8V as well. Not affected are the ADC-Channels, which have their own ADVREF. The VMEM pins on the module are pin one and two of the bus interface. If pins of PIOC or the memory bus are in use on the customer's design it is highly recommended to implement buffers on both memory bus and PIOC pins.

The memory bus is used inside of the module. It can be either 1.8V or 3.3V. The Vmem pin of the module is powered by the module itself. Do not power this pin externally to maintain inter-product dependencies. A difference between Vmem and VCC may also affect the behaviour of one PIO-controller of the respective module.

To connect 5V chips the same schematics can be used with suitable buffer chips.

Figure 5.1. Buffered Memory Bus (PIOC) 1.8V - 3.3V

Appendix A. Peripheral Color Codes

This table matches the color used to identify various peripherals in tables.

Power Supply/Ground

USART

Debug UART

TWI (I2C-Bus)

SD-Card/MMC

SPI

USB Host

USB Device

Reserved

Synhcronous Serial Controller (SSC)

JTAG

Control

Ethernet

Genral Purpose I/O Port

Programmable Clock Output

Analog-to-digital Converter

Timer Counter

Image Sensor Interface

LCD/TFT Controller Interface

Embedded Trace Macrocell

Static Memory Controller

Compact Flash Interface

Pulse Width Modulator

Touch Controller

Can Controller

AC97 Sound Interface

Encryption Device

Soft Modem

True Random Generator

Appendix B. Peripheral Identifiers

ID

Mnemonic

Peripheral Name

External Interrupt

0

AIC

Advanced Interrupt Controller

FIQ

1

SYSC

System Controller Interrupt

2

PIOA

Parallel I/O Controller A

3

PIOB

Parallel I/O Controller B

4

PIOC

Parallel I/O Controller C

5

PIOD/PIOE

Parallel I/O Controller D/E

6

TRNG

True Random Number Generator

7

US0

USART 0

8

US1

USART 1

9

US2

USART 2

10

US3

USART 3

11

MCI0

High Speed Multi Media Card Interface 0

12

TWI0

Two-Wire Interface 0

13

TWI1

Two-Wire Interface 1

14

SPI0

Serial Peripheral Interface

15

SPI1

Serial Peripheral Interface

16

SSC0

Synchronous Serial Controller 0

17

SSC1

Synchronous Serial Controller 1

18

TC0..TC5

Timer Counter 0,1,2,3,4,5

19

PWM

Pulse Width Modulation Controller

20

TSADCC

Touch Screen ADC Controller

21

DMA

DMA Controller

22

UHPHS

USB Host High Speed

23

LCDC

LCD Controller

24

AC97C

AC97 Controller

25

EMAC

Ethernet MAC

26

ISI

Image Sensor Interface

27

UDPHS

USB Device High Speed

28

Reserved

29

MCI1

High Speed Multi Media Card Interface 1

30

Reserved

31

AIC

Advanced Interrupt Controller

IRQ

Table B.1. Peripheral Identifiers

Appendix C. Address Map (Physical Address Space)

After the execution of the remap command the 4 GB physical address space is separated as shown in the following table. Accessing these addresses directly is only possible if the MMU (memory management unit) is deactivated. As soon as the MMU is activated the visible address space is changed completely.
If absolute memory addresses should be accessed within an application, the corresponding address space has first to be mapped to the virtual address space using mmap or ioremap under Linux.