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SMT memory subsystem dispatch serialization

Publishing Venue

IBM

Abstract

Disclosed is a method for a hard serialization boundary for a
given instruction at Dispatch in an SMT processor core. In particular, the
method ensures that an instruction will not be dispatched until the entire
processor core is idle with respect to that thread's older instructions and
that there are no outstanding instructions in the memory subsystem for that
thread.

Country

Undisclosed

Language

English (United States)

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SMT memory subsystem dispatch serialization

The disclosed invention is an SMT wait-idle/core-idle interface between Dispatch and Pervasive control logic. The goal is to hold up the dispatch of a given instruction until all processor core and memory subsystem activity has ended for previous instructions for the thread in question.

Shown in the Figure are control flows at Dispatch and in the Pervasive logic, which serves as a collection and control point for chip-wide activity. At Dispatch, if it is detected that an instruction needs the degree of serialization addressed by this disclosure, an interface with Pervasive is invoked. A "wait-idle" signal is asserted to Pervasive, and Dispatch must then wait until a "core/memory-subsystem idle" signal is returned. At that point, "wait-idle" will be deasserted and Dispatch of the instruction in question will be allowed to proceed. The interface signals mentioned exist for every thread in the processor, and all activity and status is reported in a thread-specific manner, such that one-thread's activity will not arbitrarily affect another's, with respect to this method of serialization.

In the Pervasive logic, control flow is implemented on a per-thread basis to detect the assertion of "wait-idle" by Dispatch. If detected, Pervasive takes steps to hold instruction fetch, stop prefetch, etc. to bring core/memory-subsystem activity for that thread to a halt. Upon detecting that there are no older instructions still in flight...