For connection using JTAG: USB Blaster I or II cable and driver for Intel FPGA boards. Digilent® JTAG cable and driver for Xilinx FPGA boards.

Prerequisites:

MATLAB® and FPGA design software can either be locally installed on your computer or on a network accessible device. If you use software from the network you will need a second network adapter installed in your computer to provide a private network to the FPGA development board. Consult the hardware and networking guides for your computer to learn how to install the network adapter.

MATLAB Design

The MATLAB code used in this example implements a simple symmetric FIR filter and uses the dsp.Delay System object to model state. This example also shows a MATLAB test bench that exercises the filter.

Define Input Data Types

For this floating point MATLAB System object all inputs are Double Scalar. Specify them as such using the drop-down menus provided for the MATLAB Function.

Run Fixed-Point Conversion and HDL Code Generation

Launch the Workflow Advisor. In the Workflow Advisor, right-click the 'HDL Code Generation' step. Choose the option 'Run to selected task' to run all the steps from the beginning through HDL code generation.

Examine the generated HDL code by clicking the links in the log panel of the Workflow Advisor.

Generate Cosimulation Test Bench and Run HDL Cosimulation

Select the "Verify with Cosimulation" step.

Select the checkbox labelled "Generate cosimulation test bench". That action will enable other choices in the dialog, allowing you to elect to log outputs for comparison, choose your preferred HDL simulator and simulate the generated cosimulation test bench. Check both of the remaining checkboxes and select your preferred HDL simulator.

Select "GUI" as the HDL simulator run mode.

Click "Run" and observe the plots comparing the outputs of the cosimulation to the outputs of the fixed point System object. Also note the signal transitions in the HDL simulator waveform viewer.

Set Up Your FPGA Development Board

Refer to Set Up FPGA Development Board for information on setting up your FPGA board and computer to communicate for FPGA-in-the-Loop simulation.

Generate FPGA-in-the-Loop (FIL) Test Bench and Run FIL Simulation

Select the "Verify with FPGA-in-the-Loop" step in the left side panel of the Workflow Advisor.