This is Volume 2 of the Intel® AtomTM Processor D400
and D500 Series Datasheet, and is intended to be distributed as part of the complete document. This document provides
register information for the processor.

System Address Map

The SoC processor supports 64GB (36 bit) of
addressable memory space and 64 KB+3 of addressable I/O space. There is a programmable memory address space under the 1 MB
region, which is divided into regions, which can be individually controlled with programmable attributes such as Disable,
Read/Write, Write Only, or Read Only. Attribute programming is described in the Register Description section. This section
focuses on how the memory space is partitioned and what the separate memory regions are used. I/O address space has simpler
mapping and is explained near the end of this section.

Addressing of greater than 4 GB is allowed on either the DMI
Interface. The SoC processor supports a maximum of 8GB of DRAM. No DRAM memory will be accessible above 16 GB. DRAM
capacity is limited by the number of address pins available. There is no hardware lock to stop someone from inserting more
memory than is addressable.

When running in internal graphics mode, writes to GMADR range, linear ranges are
supported. Write accesses to linear regions are supported from DMI. Write accesses to tileX and tileY regions (defined via
fence registers) are not supported from DMI. GMADR read accesses are not supported from DMI.

This is Volume 2 of the Intel® AtomTM Processor D400
and D500 Series Datasheet, and is intended to be distributed as part of the complete document. This document provides
register information for the processor.

System Address Map

The SoC processor supports 64GB (36 bit) of
addressable memory space and 64 KB+3 of addressable I/O space. There is a programmable memory address space under the 1 MB
region, which is divided into regions, which can be individually controlled with programmable attributes such as Disable,
Read/Write, Write Only, or Read Only. Attribute programming is described in the Register Description section. This section
focuses on how the memory space is partitioned and what the separate memory regions are used. I/O address space has simpler
mapping and is explained near the end of this section.

Addressing of greater than 4 GB is allowed on either the DMI
Interface. The SoC processor supports a maximum of 8GB of DRAM. No DRAM memory will be accessible above 16 GB. DRAM
capacity is limited by the number of address pins available. There is no hardware lock to stop someone from inserting more
memory than is addressable.

When running in internal graphics mode, writes to GMADR range, linear ranges are
supported. Write accesses to linear regions are supported from DMI. Write accesses to tileX and tileY regions (defined via
fence registers) are not supported from DMI. GMADR read accesses are not supported from DMI.