^^^ we're going to be studying that manual for a LONG time ... gleaning bits of interest.

The description of the MMU and the description of the "processor interconnect bus" are the first NDA'ed descriptions which appear reasonably complete. There is a lot of interesting material in there.

One thing which will no doubt revive old banter is the persistent description of the system as "At the heart of the Interconnect (PI) bus is a set of unidirectional, point-to-point bus segments, a new design
selected to achieve maximum data transfer rates." ... Harking back to all the "ApplePI" banter.

One very significant issue I looked for immediately is here:

Quote

9.5 PLL Design
To support the frequency scaling capability, a new PLL design has been incorporated into the PowerPC 970FX. Both the processor clock and the bus clock are derived from the reference clock input to the chip in the PowerPC 970FX design. For frequency scaling it is assumed that the reference clock, referred to as the sysclk, will run at a constant frequency, as will the related synchronizing clock, Psync. The PLL uses a fixed divider in the feedback path, but a variable, seamlessly switched divider in the forward path. {italics mine} The fixed feedback path allows the PLL to constantly run at a fixed frequency, avoiding the need to relock when switching frequencies. The processor clock (mclk) and bus clock (Bclk) frequencies can be changed seamlessly, while maintaining the ratio between these two clocks at a fixed value. {ditto} This design is shown in Figure 9-4.

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BINGO,BINGO, BINGO ... this is how all the power macs are toggling from 80% to 100% frequency... which we have clear evidence (see the Hot G5 thread) that they are doing.

It goes on with a table (fairly complex) of achievable states wrt /2 and /4 powertuning, and Section 9.8 tells you what is involved in making these transitions in an MP configuration.

It is also possible to dither transitions to reduce dI/dt, and it is interesting that the document shows the northbridge (memory controller) as responsible for controlling any processor voltage slewing, rather than directly controlled by the "service" processor.

And this brings up:

Quote

11.1.2 Power-On Reset SPU Hardware Considerations
It is assumed that 970FX systems will include a service processor (SPU) which generally consists of a low cost microcontroller. This microcontroller is responsible for hardware initialization of the 970FX and the North Bridge and can also be used to manage and supervise other system functions, like fans. At a minimum, the SPU needs to be able to assert HRESET_B and BYPASS_B on the 970FX and should also have either a dedicated I2C bus master to initialize the system, or general purpose I/O pins (GPIO) that can be used to implement an I2C bus master.

Click to expand...

Anybody thinking of "hacking" or "overclocking" this system should be sobered by the complexity of what is required to bring the system up and configure it out of reset. We will be waiting for the "Refer to the IBM PowerPC 970FX Power-On Reset Application Note for details." ... and the details look very detailed. Information from Momentum makes it clear that intializing the bus includes loading pin-pin bus skew parameters (which are PCB design dependent and frequency dependent). These are stated to take roughly a week of detailed testing for each new PCB design to establish (sheesh!).

Doesn't sound like a walk in the park getting the thing powered on and the clock stable.

I sort of like Momentum's comment about it taking 5 months to figure out how to do it, while the G3 was rather simple.

Just adds another layer of complexity to the overclock, not only do you have to figure out the PPC970 -- but you also have to figure out Apple's Power On bootstrap device and how to modify it's ROM programming.

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