I can't find any example in the uvm-systemc preview package which DUT has clock and reset signals.
I tried to create clock with sc_clock in sc_main and connected it my dut's clock signal. But it looks the simulation will never finish.
So would someone let me know what's the right way to handle the clock and reset signals?

Hello All,
I am working on SystemC-UVM based testbench.
I have created UVM based testbench using UVM code generator.
Here I am using three different agents in UVM generator which I have defined as a part of the configuration file which was further being provided to UVM code generator to generate test bench skeleton.
And here, in of the agent driver, the code snippet is as:
// Drive the inputs of the DUT
UVM_INFO(this->name(),"Driving transaction:",0);
req.print();
// TODO put your code here
But when I try to read the value in my test-case, then I see an error as:
And this error is observed inside print() function, once I comment the line "req.print()" from the above snippet the error is no more observed and my test-case runs fine.

Hi ,
To whom may correspond
I think there is some kind of error in the UVM 1.1d register model.
I have been experimenting with the UVM register model and i have seen the following code in uvm_reg_map.svh
task uvm_reg_map::do_bus_write (uvm_reg_item rw,
uvm_sequencer_base sequencer,
uvm_reg_adapter adapter);
uvm_reg_addr_t addrs[$];
uvm_reg_map system_map = get_root_map();
int unsigned bus_width = get_n_bytes();
uvm_reg_byte_en_t byte_en = -1;
uvm_reg_map_info map_info;
int n_bits;
int lsb;
int skip;
int unsigned curr_byte;
int n_access_extra, n_access;
int n_bits_init;
Xget_bus_infoX(rw, map_info, n_bits_init, lsb, skip);
addrs=map_info.addr;
// if a memory, adjust addresses based on offset
if (rw.element_kind == UVM_MEM)
foreach (addrs[i])
addrs[i] = addrs[i] + map_info.mem_range.stride * rw.offset;
foreach (rw.value[val_idx]) begin: foreach_value
uvm_reg_data_t value = rw.value[val_idx];
/* calculate byte_enables */
if (rw.element_kind == UVM_FIELD) begin
int temp_be;
int idx;
n_access_extra = lsb%(bus_width*8);
n_access = n_access_extra + n_bits_init;
temp_be = n_access_extra;
value = value << n_access_extra;
while(temp_be >= 8) begin
byte_en[idx++] = 0;
temp_be -= 8;
end
temp_be += n_bits_init;
while(temp_be > 0) begin
byte_en[idx++] = 1;
temp_be -= 8;
end
byte_en &= (1<<idx)-1;
for (int i=0; i<skip; i++)
void'(addrs.pop_front());
while (addrs.size() > (n_bits_init/(bus_width*8) + 1))
void'(addrs.pop_back());
end
curr_byte=0;
n_bits= n_bits_init;
The code continues but the interesting part is already there.
Lets assume we have a register with 4 bytes and 1byte per address granularity (byte_addressing).
Now, we do a FIELD access of 8bits length (the first byte of a register). The field is configured "individual_accessible, so UVM should only access that FIELD. The reg2bus should generate that byte request to be written.
In other words, the vector "addrs" should have only one byte address.
Going to the code, i see that initially the addrs has the 4 address ( the whole register) and when it comes to the "if (rw.element_kind == UVM_FIELD) begin" and it will pop_back()/remove all the exceeding bytes that doesn't need to complete "n_bits_init" of the field access.
The problem is here:
UVM has
//while (addrs.size() > (n_bits_init/(bus_width*8) + 1))
and i think it should be
while (addrs.size() > ((n_bits_init-1)/(bus_width*8) + 1)) //ejonalv possible error in UVM? check
That is because in case we want to write 8 bits, it will calculate 8/8+1=2 address in the UVM version, but in fact it should require only 1 address.
This is of course applicable for the READ variation.
Did i misunderstand something? It is very hard to go through the register model without proper documentation in the code.
I am looking forward your answer
Best Regards
Jonathan

Hi,
The purpose of this discussion is to understand different possibilities by which the simulation performance, memory usage can be increased.
Scoreboard as we understand needs the data/packets/frames etc to be stored/buffered to do a comparison with the actual data out. This works out fine when we have small sized array ranging from few bytes to few thousands of bytes.. However imagine, if we have 100 thousands of bytes and above and there is a need to store them and lets say multiple of such lanes/flows , then this would take a hit on the simulation performance. And this gets worse if we have to reuse and port it to a subsytem/chip level simulations..
With this as the background, i am looking at alternate approach for scoreboards.. In a way is possible avoid scoreboard and check the data as it comes without the need to store the expected/input data.
Approach that can be thought of :
1. Generating incremental data pattern and check at the output .. (Comes again with issues like aliasing etc.. and hence need to have longer patterns.)
2. Generation of PRBS stream as the payload of the frame.. and then have a PRBS checker at the output.. and see it remains locked.. (Debug would get worse with this.. if there is a mismatch)
3. Having a byte scoreboard.. something like that.. (Not sure how feasible this is).
There are many challenges even with these approach..
I am just wondering if someone has already experienced such cases and what kind of challenges are thrown out..
Appreciate any input on this.
Regards,
svuvmuser !

Hi
why does
phase.find_by_name(.name(uvm_main_phase::get().get_name()), .stay_in_scope(0));
from run_phase and
uvm_pkg::uvm_phase run_phase = phase.find_by_name(.name(uvm_run_phase::get().get_name()), .stay_in_scope(0));
from main_phase return null. Is this intentional?
I have created a sample example to check, or you can use the attached file as well.
https://www.edaplayground.com/x/5Py7
test.svh

The VCS implementation of uvm_reg_bit_bash_seq UVM register bit bash sequence performs a
model.reset()
in the sequence body, before starting the core do_block() task.
Due to this reset, any configurations made to the DUT before starting the bit bash sequence is lost in the mirror model, while the DUT still has the configuration intact. This is causing failures during the bit-bash process, resulting in a test fail. There is no knob to override the reset functionality, nor can I extend the sequence and bypass the reset.
Any thoughts on this? Any work around for this?
~Chethan

I'm trying out the example for UVM-Connect 2.3 and I can't get a successful compile.
The error message is about the "undefined reference to `m__uvm_report_dpi'.
I'm using:
GCC 4.5.2 on CentOS 5.11
VCS 2015.09-SP2-3
SystemC 2.3.1
SCV 2.0.0
UVM 1.2
UVMC 2.3.0
Appreciate all the help!

The cook book from Mentor tells following and in another thread, the moderator also suggested against using the sub phases of run.
However in one of my projects, I do find the need for using them (and infact we had an internal implemention of something similar in our previous OVM version). Are there any thing happening on this front? Is there a risk in using the sub phases if some of that changes in a future version?
"The Accellera UVM committee is still developing the use models and APIs for new UVM phasing as it relates to sequences and transactors. In the mean time, our recommendation is to wait until that work is done and the API is stable. There are a number of future articles in this section which will be available here at that time, and which will describe our recommendations for using this technology. These include:
How to make your testbench phase aware [Not yet available] How to manage sequences in the context of phasing [Not yet available] How to design reusable transactors that work in the context of phasing [Not yet available] "

Let's say I have the following DUT. The UVM environment contains a chain of models/predictors. Input data flows down this chain and generates the expected CHIP output, which is compared to actual. Pros: verifies top-level functionality. Cons: Does not verify block level functionality. A good start, but I'd like to also verify the blocks in a system setting. So, I create block-level environments, then reuse them at the top level. Awesome, but wait a minute. I still need the top-level verification (Input-to-Output) like in the first example. However, all 3 of my block predictors are being used in their corresponding environments' scoreboards, hooked up to the RTL, via agents. How does one do both? Surely I'm not supposed to instantiate duplicate copies of my block level predictors to create the end-to-end model chain...

Hi,
We are using snps ralgen to generate the regmodel.
It appears that the ralgen creates only the default map.
We would like to have 2 maps for 2 separated if masters. Is there an online example for such case?
A post gen script can do one of the following 2 options:
1. add another instance of uvm_reg_map and copy/clone the ready map after finished build
2. add another instance of uvm_reg_map, and duplicate any map1.add_reg and map1.add_submap to map2
Which is preferable?
Thanks!
Elihai

I see uvm_sequencer_base::wait_for_grant (UVM 1.1d) is a virtual task but accesses a local int g_request_id - is this not a bad coding style? If I were to override this virtual method for debug with much of the code intact tool throws an error for his local bar in a derived SQR class. I extended a SQR class and copied all the code for wait_for_grant and started tweaking - couldn't proceed with that debug due to this member being local. Should it be protected instead of local?
Thanks Srini wwww.go2uvm.org

I need to have two uvm_tlm_target_socket in a class and I need to do different set of things with the data received via two sockets. I was thinking if it is possible to have two implementation of b_transport task.
I am aware of how we can have multiple analysis port imp and use uvm_analysis_imp_decl(_something) and we can have a "write_something" implementation. Is something similar available for uvm_tlm_target_socket?
Regards,
Gautam

Is it possible to do a uvm_config_db::set() for an object of derived class type using the base class handle and later do a uvm_config_db::get() of same object using the derived class handle
Since a base class handle can be used to point to a derived class object and later typecase, I thought this would work, but doesn't seem to be so.
Any help will be appreciated?
Here is an example
class BaseA ;
endclass
class DerivedA extends BaseA
endclass
1) Set config_db
DerivedA a1;
a1 = DerivedA::create()
uvm_config_db#(DerivedA)::set(this, "" , "myobj", a1);
2) Get config_db
BaseA a1;
DerivedA a2;
uvm_config_db#(BaseA)::get(this, "" , "myobj", a1);
$cast(a2, a1);

Hi,
I notice something interesting in the build_phase order of uvm_component.
The uvm_component at the same level are build in the alphabetatical order of the instance name.
I expect the build order would be the same as the order I call the factory create function.
I am wondering is the alphabetatical build order an intended feature of UVM or just some artifact of the implementation?
I couldn't find any reference to this behavior in the UVM user guide or the class reference library.
Thanks.
Horace

Hi all,
I'm new with UVM and I came across a problem. I am working on an AXI RD VIP using UVM and I have the following issue.
In the data_phase (the data channel driving) from the MASTER driver, I need to drive the RREADY signal.
There are 3 handshake types described in the protocol specifications: valid before ready, ready before valid and ready and valid at the same time.
In case of valid before ready, I want to wait a certain number of clock cycles ( delay ) from the time that RVALID asserted and then to assert the RREADY signal.
From my understanding, all the delay information should come from the transaction(sequence_item).
The problem is that I generate a new transaction (sequence_item) with get_next_item only when I drive the address channel (in address_phase);
The data_phase works in parallel with the addr_phase and its independent of the address phase.
Also the data_phase needs multiple delay values (one for each data received from DUT, ex. arlen+1) while I only generate one transaction that contains the address channel informations.
Code example:
task run_phase(uvm_phase phase)
fork
forever begin
...
seq_item_port.get_next_item(req);
address_phase(req);
seq_item_port.item_done();
end
forever begin
data_phase();
end
endtask : run_phase
task address_phase(axi_item item);
// Drive the address channel
...
endtask : address_phase
task data_phase();
// Wait for the rvalid signal
while(!vif.rvalid) @(posedge vif.clk);
// Insert delay between rvalid assertion and rready assertion
repeat(<problem!!!!>) @(posedge vif.clk);
rready = 1;
...
endtask : data_phase
I don't know what variable (sequence_item variable) to set in the <problem!!!>
Can anyone give me an advice regarding this problem.
I repeat, I want all timing related data to be set from the sequence_item
Regards,
Adrian

Hello,
I'm trying to implement an AXI Slave VIP and have few questions regarding the implementation.
In this case, the DUT is the master. The AXI Slave checks the interface for valid read /write signals and performs a read/write operation from a memory model. It returns back the write response/read data back to the DUT.
1. Since this is a slave VIP , do I need a slave sequence which runs forever sending transactions to the driver ? This is similar to the UVM example where the monitor and sequencer are connected by an analysis port and the sequence calls the peek function to check if a valid transaction is available from the monitor.
(OR)
2. Can I skip the sequence/sequencer part and just connect my monitor and driver using an analysis port and pass on the observed transaction from the monitor to the driver for further action ?
(OR)
3. Im thinking of a 3rd alternative of just using the monitor to the observe the interface and drive back the write response/ read data back using the monitor itself and leave the driver empty.
Please let me know your valuable thoughts and suggestions.
Thanks,
Madhu

Hi,
As per my understanding, connect_phase does not start until all build_phase do not complete.
How is this mechanism controlled?
I did not find anything in uvm reference manual about this.
Please let me know if there is any.
Thanks.

Hi,
I have a doubt about requirement of raise/drop_objection.
Why does a compiler need objections in run_phase?
Why can it not just wait for time given like 100ns as following example?
Ex.
task run_phase(uvm_phase phase);
//phase.raise_objection(this);
#100ns;
//phase.drop_objection(this);
endtask

This document is a printable version of the Easier UVM Coding Guidelines from Doulos. You are free to use these guidelines directly, to merge them into your own company-specific UVM coding guidelines, or merely to borrow some of the ideas.
These coding guidelines are offered by Doulos for the benefit of the UVM community. They are not officially endorsed by Accellera.

Hi all,
I'm doing verification for an PHY between SPI master and a memory chip. I make two agents one for master to transfer the request, one mimics the memory slave to reply. PHY will be hooked up to two interfaces that of SPI Master and Memory. During sending request and reply data, Chip Select Pin (in SPI interface) must go low to enable the transaction. But I don't know how to control this pin when It sends the reply from memory. Because this pin is not an interface of memory slave agent. Could anyone give me some advice? Could I use phases to control the env that has different agents?
Thank you,
Nhat

To view this announcement on the IEEE web site click here.
Purpose
Verification components and environments are currently created in different forms, making interoperability among verification tools and/or geographically-dispersed design environments both time consuming to develop and error prone. The results of the UVM standardization effort will improve interoperability and reduce the cost of repurchasing and rewriting Intellectual Property (IP) for each new project or electronic design automation tool, as well as make it easier to reuse verification components. Overall, the UVM standardization effort will lower verification costs and improve design quality throughout the industry.
Need for the Project
As the electronics industry builds more complex systems involving large numbers of components, the challenge of verifying such systems multiplies by orders of magnitude. In order to bring costs and time to market down, standardization must happen to enable as much modularity and reuse across verification components as possible. The UVM standard will propagate an API that will manage this explosion in verification complexity, allowing the entire industry to write and reuse verification components both (a) internally in companies having geographically widespread teams, and (externally between vendors and user companies in the electronics industry, who are developing, selling and using verification components
Call for Contribution
Please review the IEEE P1800.2 ™ PAR and, if you are interested in participating, Register for the first working group meeting scheduled to occur on August 6th, 2015 from 12pm – 2pm Eastern Daylight Time (EDT) / 9am – 11am Pacific Daylight Time (PDT).
Please feel free to connect with the Working Group Chair, Thomas Alsop at thomas.r.alsop@intel.com or IEEE-SA staff Jonathan Goldberg at goldberg.j@ieee.org directly for further information.