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Chip Stacks at 30,000 Feet

I’m enjoying a down day in a cool, rainy Brussels awaiting the start tomorrow of Imec’s annual ITF event where I’ll hear an update about extreme ultraviolet lithography, the semiconductor roadmap and more.

The horizon is looking a bit brighter given a recent prediction from Handel Jones that cost per gate will decline again at the 10nm. Nevertheless, we are approaching the last couple nodes of CMOS, so I bring a heightened curiosity about what’s next.

Certainly one of the next big things on the horizon is wider use of chip stacksMultiple capacitor elements stackedMultiple capacitor elements stacked in multi-unit arrangement to provide bulk capacitance and lower ESR. in multi-unit arrangement to provide bulk capacitance and lower ESR.Multiple capacitor elements stackedMultiple capacitor elements stacked in multi-unit arrangement to provide bulk capacitance and lower ESR. in multi-unit arrangement to provide bulk capacitance and lower ESR.. Interestingly, Jen-Hsun Huang, chief executive of Nvidia, was on my flight out of San Francisco, and I had the chance to ask him a couple questions about the technology.

Nvidia came out early saying back at its 2013 GPU Technology Conference that it would use the kind of 2.5-D chip stacksMultiple capacitor elements stackedMultiple capacitor elements stacked in multi-unit arrangement to provide bulk capacitance and lower ESR. in multi-unit arrangement to provide bulk capacitance and lower ESR.Multiple capacitor elements stackedMultiple capacitor elements stacked in multi-unit arrangement to provide bulk capacitance and lower ESR. in multi-unit arrangement to provide bulk capacitance and lower ESR. pioneered by Xilinx and TSMC. At that time it showed a picture that was borrowed from Micron describing its Hybrid Memory Cube as part of a 2015 plan for its Volta chip.

Over time the plans seem to have changed. At GTC this year and the co-located IBM Open Power Summit, Nvidia said Volta is now a 2017 chip and another entry to the road map, Pascal, would be the first of its chips to use a 2.5-D approach in 2016.

Huang’s response was interesting. He claims the 4 Gbyte SK Hynix HBM part is a year late to market and fails to provide enough memory. Indeed, Nvidia’s plan is to use as much as 32 Gbytes memory with its Pascal or Volta chips.

Huang also claimed SK was a year late delivering its 4 GB HBM which he claimed no longer offers as much memory as users need. He said Nvidia will wait to use a next-generation HBM stackMultiple capacitor elements stackedMultiple capacitor elements stacked in multi-unit arrangement to provide bulk capacitance and lower ESR. in multi-unit arrangement to provide bulk capacitance and lower ESR.Multiple capacitor elements stackedMultiple capacitor elements stacked in multi-unit arrangement to provide bulk capacitance and lower ESR.Multiple capacitor elements stackedMultiple capacitor elements stacked in multi-unit arrangement to provide bulk capacitance and lower ESR. in multi-unit arrangement to provide bulk capacitance and lower ESR. in multi-unit arrangement to provide bulk capacitance and lower ESR..

I know these chip stacksMultiple capacitor elements stackedMultiple capacitor elements stacked in multi-unit arrangement to provide bulk capacitance and lower ESR. in multi-unit arrangement to provide bulk capacitance and lower ESR.Multiple capacitor elements stackedMultiple capacitor elements stacked in multi-unit arrangement to provide bulk capacitance and lower ESR. in multi-unit arrangement to provide bulk capacitance and lower ESR. are hard and graphics companies are among the pioneers in figuring out the technology along with FPGA and other high-end processor makers. I’m starting to think they are even harder than Nvidia thought.

My guess is Nvidia had to push out the Volta design in part due to issues with chip stacksMultiple capacitor elements stackedMultiple capacitor elements stacked in multi-unit arrangement to provide bulk capacitance and lower ESR. in multi-unit arrangement to provide bulk capacitance and lower ESR.Multiple capacitor elements stackedMultiple capacitor elements stacked in multi-unit arrangement to provide bulk capacitance and lower ESR. in multi-unit arrangement to provide bulk capacitance and lower ESR.. It also appears to be jumping ship from Micron’s HMC to SK’