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Abstract

Etching parameters are changed three times within a reactive ion etch system to cleanly remove doped polysilicon (Si) without damaging underlying silicon dioxide (SiO2) and without creating a heavy oxide layer on the surface of photoresist which could require excessive hydrofluoric acid (HF) etch removal time before photoresist can be stripped. Though the process is especially useful in defining polysilicon gate conductor patterns, it can be used for etching any Si (doped or pure). The three basic steps are applicable within batch or single wafer systems.

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United States

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English (United States)

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This is the abbreviated version, containing approximately
77% of the total text.

Three-Step Polysilicon Gate Electrode Etch Process

Etching
parameters are changed three times within a reactive
ion etch system to cleanly remove doped polysilicon (Si) without
damaging underlying silicon dioxide (SiO2) and without creating a
heavy oxide layer on the surface of photoresist which could require
excessive hydrofluoric acid (HF) etch removal time before photoresist
can be stripped. Though the process is especially useful in defining
polysilicon gate conductor patterns, it can be used for etching any
Si (doped or pure). The three basic
steps are applicable within
batch or single wafer systems.

A first set
of etching conditions is used to provide etch
chamber conditioning, moisture elimination, and to remove native
oxide (SiO2) from Si surfaces:
Etch gas: BCl3 at an approximate rate of flow of 40 standard
cubic centimeters per second (sccm)
System pressure: approximately
20 mTorr
Substrate bias: -200 volts DC
Time: approximately one minute

A second set
of conditions is used to remove most of the Si:
Etch gas: HCl at 90 sccm + Cl2
at 30 sccm
System pressure: approximately
15 mTorr
RF power: approximately 650
watts, no DC bias

A third set
of conditions is used to assure complete, very
selective, removal of Si, e.g., "stringers", without damage to
exposed SiO2:
Etch gas: O2 at 5 sccm +...