GLOBALFOUNDRIES and SRC announce new scholarship for undergraduate engineering students

GLOBALFOUNDRIES today announced the “GLOBALFOUNDRIES Undergraduate Research Scholarship,” a new scholarship recognizing and rewarding aspiring, leadership-oriented engineering students interested in careers in the semiconductor industry. The GLOBALFOUNDRIES Undergraduate Research Scholarship will fund undergraduate research opportunities (URO) and intern scholars through the Semiconductor Research Corporation’s (SRC) Education Alliance.

Presented at SRC’s annual TECHCON conference in Austin, Texas, the scholarship was created by GLOBALFOUNDRIES in partnership with SRC to recognize and reward science, technology and engineering students who demonstrate promise in their academic and professional efforts. The selected recipients of this scholarship will have the opportunity to interact with GLOBALFOUNDRIES researchers and access the professional resources of SRC and the SRC Education Alliance.

“Building a pipeline of highly skilled talent is essential to our business and to the competitiveness of the entire semiconductor industry,” said Suresh Venkatesan, senior vice president of technology development, GLOBALFOUNDRIES. “SRC connects companies with the top universities, which results in exciting research and educational opportunities for the best and the brightest students. The GLOBALFOUNDRIES Undergraduate Research Scholarship gives us the opportunity to support science, technology, engineering and mathematics education and help develop the technical leaders who will continue to drive innovation in the semiconductor industry in the future.”

Until recently, SRC focused exclusively on students seeking advanced degrees, providing fellowships for them to do university research that had practical applications for corporate members of its unique consortium. The URO is SRC’s innovative program providing undergraduates with valuable research experience and mentoring. The goal of the URO is to empower bright, well-educated, and experienced scientists and engineers for which U.S. high-tech companies are seeking.

“Recognizing the critical importance of a strong pipeline of new talent for the semiconductor industry, the SRC Education Alliance through the URO Program provides financial assistance to undergraduates, allowing students and universities to recognize the connections between the materials they are learning in the classroom and the technological innovations that transform the world,” said SRC President Larry Sumney. “We are thrilled to collaborate with GLOBALFOUNDRIES as we continue to develop our URO program.”

Layered graphene sandwich for next generation electronics

Sandwiching layers of graphene with white graphene could produce designer materials capable of creating high-frequency electronic devices, University of Manchester scientists have found. The researchers have demonstrated how combining the two-dimensional materials in a stack could create perfect crystals capable of being used in next generation transistors.

Hexagonal boron nitride (hBN), otherwise known as white graphene, is one of a family of two-dimension materials discovered in the wake of the isolation of graphene at the University in 2004. Manchester researchers have previously demonstrated how combining 2D materials, in stacks called heterostructures, could lead to materials capable of being designed to meet industrial demands.

Now, for the first time, the team has demonstrated that the electronic behaviour of the heterostructures can be changed enormously by precisely controlling the orientation of the crystalline layers within the stacks.

The researchers, led by University of Manchester Nobel laureate Sir Kostya Novoselov, carefully aligned two graphene electrodes separated by hBN and discovered there was a conservation of electron energy and momentum.

The findings could pave the way for devices with ultra-high frequencies, such as electronic or photovoltaic sensors.

The research was carried out with scientists from Lancaster and Nottingham Universities in the UK, and colleagues in Russia, Seoul and Japan.

Professor Laurence Eaves, a joint academic from the Universities of Manchester and Nottingham, said: “”This research arises from a beautiful combination of classical laws of motion and the quantum wave nature of electrons, which enables them to flow through barriers

“We are optimistic that further improvements to the device design will lead to applications in high-frequency electronics.”

Professor Vladimir Falko, from Lancaster University, added: “Our observation of tunnelling and negative differential conductance in devices made of multilayers of graphene and hexagonal boron nitride demonstrates potential that this system has for electronics applications.

“It is now up to material growers to find ways to produce such multilayer systems using growth techniques rather than mechanical transfer method used in this work.”

Doped graphene nanoribbons with potential

Graphene is a semiconductor when prepared as an ultra-narrow ribbon – although the material is actually a conductive material. Researchers from Empa and the Max Planck Institute for Polymer Research have now developed a new method to selectively dope graphene molecules with nitrogen atoms. By seamlessly stringing together doped and undoped graphene pieces, they were able to form ”heterojunctions” in the nanoribbons, thereby fulfilling a basic requirement for electronic current to flow in only one direction when voltage is applied – the first step towards a graphene transistor. Furthermore, the team has successfully managed to remove graphene nanoribbons from the gold substrate on which they were grown and to transfer them onto a non-conductive material.

Graphene possesses many outstanding properties: it conducts heat and electricity, it is transparent, harder than diamond and extremely strong. But in order to use it to construct electronic switches, a material must not only be an outstanding conductor, it should also be switchable between ”on” and ”off” states. This requires the presence of a so-called bandgap, which enables semiconductors to be in an insulating state. The problem, however, is that the bandgap in graphene is extremely small. Empa researchers from the ”nanotech@surfaces” laboratory thus developed a method some time ago to synthesise a form of graphene with larger bandgaps by allowing ultra-narrow graphene nanoribbons to ”grow” via molecular self-assembly.

The researchers, led by Roman Fasel, have now achieved a new milestone by allowing graphene nanoribbons consisting of differently doped subsegments to grow. Instead of always using the same ”pure” carbon molecules, they used additionally doped molecules – molecules provided with ”foreign atoms” in precisely defined positions, in this case nitrogen. By stringing together ”normal” segments with nitrogen-doped segments on a gold (Au (111)) surface, so-called heterojunctions are created between the individual segments. The researchers have shown that these display similar properties to those of a classic p-n-junction, i.e. a junction featuring both positive and negative charges across different regions of the semiconductor crystal, thereby creating the basic structure allowing the development of many components used in the semiconductor industry. A p-n junction causes current to flow in only one direction. Because of the sharp transition at the heterojunction interface, the new structure also allows electron/hole pairs to be efficiently separated when an external voltage is applied, as demonstrated theoretically by theorists at Empa and collaborators at Rensselaer Polytechnic Institute. The latter has a direct impact on the power yield of solar cells. The researchers describe the corresponding heterojunctions in segmented graphene nanoribbons in the recently published issue of “Nature Nanotechnology.”

In addition, the scientists have solved another key issue for the integration of graphene nanotechnology into conventional semiconductor industry: how to transfer the ultra-narrow graphene ribbons onto another surface? As long as the graphene nanoribbons remain on a metal substrate (such as gold used here) they cannot be used as electronic switches. Gold conducts and thus creates a short-circuit that “sabotages” the appealing semiconducting properties of the graphene ribbon. Fasel’s team and colleagues at the Max-Planck-Institute for Polymer Research in Mainz have succeeded in showing that graphene nanoribbons can be transferred efficiently and intact using a relatively simple etching and cleaning process onto (virtually) any substrate, for example onto sapphire, calcium fluoride or silicon oxide.

SRC and UC Berkeley pursue a more cost effective approach to 3D integration

University of California, Berkeley researchers sponsored by Semiconductor Research Corporation (SRC) are pursuing a novel approach to 3D device integration that promises to lead to advanced mobile devices and wearable electronics featuring increased functionality in more low-profile packages.

The research focuses on integrating extra layers of transistors on a vertically integrated 3D monolithic chip using printing of semiconductor “inks” as compared to the current method of chip-stacking through 3D interconnect solutions.

The new process technology could help semiconductor manufacturers develop smaller and more versatile components that are less expensive and higher performing by enabling cost-effective integration of additional capabilities such as processing, memory, sensing and display. The low-temperature process is also compatible with polymer substrates, enabling potential new applications in wearable electronics and packaging.

To fabricate such devices, new material and process methodologies are needed for depositing nanoparticles for semiconductors, dielectrics and conductors. The research is particularly focused on solution-based processing due its low temperature compatibility with CMOS metallization as well as the potential for lower cost manufacturing.

“Initial results from the Berkeley team show that reasonably high performance can be obtained from ink-jet printed devices with process temperatures that are compatible with post-CMOS metallization, thus enabling a new route to monolithic 3D integration,” said Bob Havemann, Director of Nanomanufacturing Sciences at the SRC.

SEMATECH announced today that researchers have reported progress which could significantly improve resist sensitivity by incorporating metal oxide nanoparticles for extreme ultraviolet (EUV) lithography, bringing the technology another step toward enabling the development of high performance resists required to enable EUV for high-volume manufacturing (HVM).

SEMATECH engineers, in association with scientists from Cornell University, have demonstrated significantly higher dose sensitivity by incorporating metal oxide nanoparticles, with a resolution dose that is less than one fifth of that normally used with EUV scanner throughput calculations. These significant advances are critical in moving forward the infrastructure that will prepare EUV lithography for HVM at 20nm half-pitch.

“These resist platforms have the potential to significantly relax the EUV source power requirements to enable high-throughput EUV lithography—which has been the most critical barrier to enabling EUV to enter high-volume manufacturing,” said Michael Lercel, SEMATECH’s senior director of Technology. “With these disruptive photoresist platforms, SEMATECH is working toward enabling breakthrough high performance resists that move forward the infrastructure that will prepare EUV for cost-effective manufacturing.”

“This is a breakthrough in taking the lead out of a very promising type of solar cell, called a perovskite,” said Mercouri G. Kanatzidis, an inorganic chemist with expertise in dealing with tin. “Tin is a very viable material, and we have shown the material does work as an efficient solar cell.”

Kanatzidis, who led the research, is the Charles E. and Emma H. Morrison Professor of Chemistry in the Weinberg College of Arts and Sciences.

The new solar cell uses a structure called a perovskite but with tin instead of lead as the light-absorbing material. Lead perovskite has achieved 15 percent efficiency, and tin perovskite should be able to match — and possibly surpass — that. Perovskite solar cells are being touted as the “next big thing in photovoltaics” and have reenergized the field.

Kanatzidis developed, synthesized and analyzed the material. He then turned to Northwestern collaborator and nanoscientist Robert P. H. Chang to help him engineer a solar cell that worked well.

“Our tin-based perovskite layer acts as an efficient sunlight absorber that is sandwiched between two electric charge transport layers for conducting electricity to the outside world,” said Chang, a professor of materials science and engineering at the McCormick School of Engineering and Applied Science.

Their solid-state tin solar cell has an efficiency of just below 6 percent, which is a very good starting point, Kanatzidis said. Two things make the material special: it can absorb most of the visible light spectrum, and the perovskite salt can be dissolved, and it will reform upon solvent removal without heating.

“Other scientists will see what we have done and improve on our methods,” Kanatzidis said. “There is no reason this new material can’t reach an efficiency better than 15 percent, which is what the lead perovskite solar cell offers. Tin and lead are in the same group in the periodic table, so we expect similar results.”

Perovskite solar cells have only been around — and only in the lab — since 2008. In 2012, Kanatzidis and Chang reported the new tin perovskite solar cell with promises of higher efficiency and lower fabrication costs while being environmentally safe.

“Solar energy is free and is the only energy that is sustainable forever,” Kanatzidis said. “If we know how to harvest this energy in an efficient way we can raise our standard of living and help preserve the environment.”

The solid-state tin solar cell is a sandwich of five layers, with each layer contributing something important. Being inorganic chemists, Kanatzidis and his postdoctoral fellows Feng Hao and Constantinos Stoumpos knew how to handle troublesome tin, specifically methylammonium tin iodide, which oxidizes when in contact with air.

The first layer is electrically conducting glass, which allows sunlight to enter the cell. Titanium dioxide is the next layer, deposited onto the glass. Together the two act as the electric front contact of the solar cell.

Next, the tin perovskite — the light absorbing layer — is deposited. This is done in a nitrogen glove box — the bench chemistry is done in this protected environment to avoid oxidation.

On top of that is the hole transport layer, which is essential to close the electrical circuit and obtain a functional cell. This required Kanatzidis and his colleagues to find the right chemicals so as not to destroy the tin underneath. They determined what the best chemicals were — a substituted pyridine molecule — by understanding the reactivity of the perovskite structure. This layer also is deposited in the glove box. The solar cell is then sealed and can be taken out into the air.

A thin layer of gold caps off the solar-cell sandwich. This layer is the back contact electrode of the solar cell. The entire device, with all five layers, is about one to two microns thick.

The researchers then tested the device under simulated full sunlight and recorded a power conversion efficiency of 5.73 percent.

SEMATECH announced this week that researchers have reached a significant milestone in reducing tool-generated defects from the multi-layer deposition of mask blanks used for extreme ultraviolet lithography, pushing the technology another significant step toward readiness for high-volume manufacturing.

University of California, Berkeley researchers sponsored by Semiconductor Research Corporation (SRC) are pursuing a novel approach to 3D device integration that promises to lead to advanced mobile devices and wearable electronics featuring increased functionality in more low-profile packages.

Research from University of California, Berkeley scientists sponsored by Semiconductor Research Corporation (SRC) promises to revolutionize portable radio frequency (RF) electronics and communication systems via advancements in on-chip inductors by leveraging embedded nanomagnets. The UC Berkeley research focuses on using insulated nano-composite magnetic materials as the filling material to shrink the size and improve the performance of high frequency on-chip inductors, thereby enabling a new wave of miniaturized electronics and wireless communications devices.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that it has opened a new, wholly owned subsidiary in Shanghai, called EV Group China Ltd., which will serve as regional headquarters for all of EVG’s operations in China. The new subsidiary, which houses a local service center and spare parts management facility, will further strengthen EVG’s presence in the region and support the company’s ongoing efforts to improve service and response times to local customers.

ChaoLogix, Inc., a semiconductor technology provider focused on developing embedded security and low-power design intellectual property, today introduced ChaoSecure technology that deters side channel attacks on semiconductor chips and contributes a superior layer of security compared to existing solutions. ChaoLogix’s ChaoSecure technology is a hardware-based solution designed to provide optimal performance at the nexus of security and power. Proven in silicon and validated by an independent security lab, ChaoSecure is a secure standard cell library that can be easily integrated into an existing integrated circuit (IC) — making it the ideal security solution in terms of cost and performance for designing complex applications ranging from smart cards to smart phones.

Applied Materials, Inc. this week announced that it was named a 2014 World’s Most Ethical Company by the Ethisphere Institute, an independent center of research promoting best practices in corporate ethics and governance. This is the third consecutive year Applied Materials has received the annual award, which recognizes organizations that continue to demonstrate ethical leadership and corporate behavior.

MIT researchers sponsored by Semiconductor Research Corporation have introduced new directed self-assembly (DSA) techniques that promise to help semiconductor manufacturers develop more advanced and less expensive components.

The MIT study demonstrates that complex patterns of lines, bends and junctions with feature sizes below 20nm can be made by block copolymer self-assembly guided by a greatly simplified template. This study explained how to design the template to achieve a desired pattern. Electron-beam lithography was used to produce the template serially, while the block copolymer filled in the rest of the pattern in a parallel process. This hybrid process can be five or more times faster than writing the entire pattern by electron beam lithography.

sembly to produce dense, high resolution patterns was proposed and demonstrated several years ago, but there was no systematic way to design templates to achieve a complex block copolymer pattern. The MIT study developed a simple way to design a template to achieve a specific block copolymer pattern over a large area. Although the work used electron-beam lithography to define the template, other methods such as photolithography with trimming could be used to produce the templates.

Block copolymer lithography is already on the semiconductor industry roadmap as directed self-assembly, but the process is still in its infancy. Although DSA patterning has been demonstrated on 300 millimeter wafers, these early trials used templates fabricated by photolithography with limited resolution and limited control of the feature geometry. The MIT process offers a path to far more complicated geometries using relatively simple templates. Next steps involve the research being shared with semiconductor companies for further studies.

How 19th century physics could change the future of nanotechnology

Researchers at the University of Cincinnati have found that their unique method of light-matter interaction analysis appears to be a good way of helping make better semiconductor nanowires.

“Semiconductor nanowires are one of the hottest topics in the nanoscience research field in the recent decade,” says Yuda Wang, a UC doctoral student. “Due to the unique geometry compared to conventional bulk semiconductors, nanowires have already shown many advantageous properties, particularly in novel applications in such fields as nanoelectronics, nanophotonics, nanobiochemistry and nanoenergy.”

Wang will present the team’s research “Transient Rayleigh Scattering Spectroscopy Measurement of Carrier Dynamics in Zincblende and Wurtzite Indium Phosphide Nanowires” at the American Physical Society (APS) meeting to be held March 3-7 in Denver. Nearly 10,000 professionals, scholars and students will attend the APS meeting to discuss new research from industry, universities and laboratories from around the world.

Key to this research is UC’s new method of Rayleigh scattering, a phenomenon first described in 1871 and the scientific explanation for why the sky is blue in the daytime and turns red at sunset. The researchers’ Rayleigh scattering technique probes the band structures and electron-hole dynamics inside a single indium phosphide nanowire, allowing them to observe the response with a time resolution in the femtosecond range – or one quadrillionth of a second.

JILA physicists discover “quantum droplet” in semiconductor

JILA physicists used an ultrafast laser and help from German theorists to discover a new semiconductor quasiparticle—a handful of smaller particles that briefly condense into a liquid-like droplet.

Quasiparticles are composites of smaller particles that can be created inside solid materials and act together in a predictable way. A simple example is the exciton, a pairing, due to electrostatic forces, of an electron and a so-called “hole,” a place in the material’s energy structure where an electron could be, but isn’t.

The new quasiparticle, described in the Feb. 27, 2014, issue of Nature and featured on the journal’s cover, is a microscopic complex of electrons and holes in a new, unpaired arrangement. The researchers call this a “quantum droplet” because it has quantum characteristics such as well-ordered energy levels, but also has some of the characteristics of a liquid. It can have ripples, for example. It differs from a familiar liquid like water because the quantum droplet has a finite size, beyond which the association between electrons and holes disappears.

Although its lifetime is only a fleeting 25 picoseconds (trillionths of a second), the quantum droplet is stable enough for research on how light interacts with specialized forms of matter.

The JILA team created the new quasiparticle by exciting a gallium-arsenide semiconductor with an ultrafast red laser emitting about 100 million pulses per second. The pulses initially form excitons, which are known to travel around in semiconductors. As laser pulse intensity increases, more electron-hole pairs are created, with quantum droplets developing when the exciton density reaches a certain level. At that point, the pairing disappears and a few electrons take up positions relative to a given hole. The negatively charged electrons and positively charged holes create a neutral droplet. The droplets are like bubbles held together briefly by pressure from the surrounding plasma.

EV Group and Brisbane Materials Technology introduced a new anti-reflective (AR) coating solution based on BMT’s innovative XeroCoat materials. The jointly developed manufacturing solution enables lumen output increases of up to eight percent. The AR coating manufacturing solution can be seamlessly integrated with established production schemes, allowing the coating of LED components at room temperature and atmospheric pressure.

International Rectifier, IR, announced that the company has commenced initial production at its new ultra-thin wafer processing facility in Singapore (IRSG). Wafer thinning, metallization, testing and additional proprietary wafer level processing are undertaken at the new 60,000 square foot manufacturing site which receives processed wafers from IR’s internal fabs and foundry partners. The facility, which will employ approximately 135 people in the initial phase, will process a variety of products, including the company’s latest generation power MOSFETs and IGBTs.

PLACYD, an EU funded consortium of industrial and academic collaborators and led by Arkema will establish a dedicated material manufacturing facility that allows the production of block copolymers meeting the rigorous standards required for their use in industry as nanolithographic templates. PLACYD brings together researchers and industries to allow for the first time the integration of synthesis through to wafer scale production and system/device characterization. Partners include: CEA-Leti, STMicroelectronics, Intel IPLS, Mentor Graphics, ASML and other leading EU companies and research organizations.

JILA physicists used an ultrafast laser and help from German theorists to discover a new semiconductor quasiparticle—a handful of smaller particles that briefly condense into a liquid-like droplet. Quasiparticles are composites of smaller particles that can be created inside solid materials and act together in a predictable way. A simple example is the exciton, a pairing, due to electrostatic forces, of an electron and a so-called “hole,” a place in the material’s energy structure where an electron could be, but isn’t.

Semiconductor Research Corporation, a university-research consortium for semiconductors and related technologies, has launched a significant new initiative on Trustworthy and Secure Semiconductors and Systems. The first major phase of T3S research is a $9 million joint effort over the next three years with the National Science Foundation (NSF) focused on Secure, Trustworthy, Assured and Resilient Semiconductors and Systems (STARSS).

SEMI this week announced that two teams — from the University of Florida and Xilinx — are recipients of the 2013 SEMI Award for North America. The development team at Xilinx was recognized for their commercialization of the silicon interposer and the University of Florida team was recognized for developing a cornerstone of the modern era of computational modeling of CMOS fabrication process with the Florida Object-Oriented Process Simulator, FLOOPS. Liam Madden accepted the award on behalf of the Xilinx team, and Mark Law and Kevin Jones (University of Florida) accepted their awards during a banquet at the 2014 SEMI Industry Strategy Symposium (ISS) yesterday in Half Moon Bay, Calif.

ARM and global semiconductor foundry UMC this week announced an agreement to offer the ARM Artisan physical IP platform along with POP IP for UMC’s 28nm high-performance low-power (HLP) process technology. UMC and ARM will provide an advanced process technology and comprehensive physical IP platform under this agreement, with the goal of supporting customers targeting a wide range of consumer applications such as smartphones, tablets, wireless and digital home services.

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