MACROCYCLIC DERIVATIVE AND ASSEMBLIES FORMED THEREFROM - The present invention is directed to a macrocyclic derivative which is formed by modification of a macrocycle. The invention further relates to assemblies formed by the self-assembly of such macrocyclic derivatives in aqueous solvent, and includes bilayer vesicles, micelles, monolayers, nanoparticles, colloidal assemblies and surface-coated assemblies.

2011-05-26

20110124104

INDUCING CELL DEATH BY INHIBITING ADAPTIVE HEAT SHOCK RESPONSE - Provided herein is a method for inducing cell death by inducing heat shock response in a cell in combination with inhibiting adaptive heat shock response. Also provided are methods for preventing cancer, treating intracellular parasite infections, and inflammation-associated conditions.

2011-05-26

20110124105

Mixed Cell Populations For Tissue Repair And Separation Technique For Cell Processing - The present invention provides a fluid exchange cell culture technique and tissue repair cells (TRCs) made by these methods, as well as methods using these cells. The method includes a new wash step which increases the tissue repair properties of the TRCs of the invention. This wash step allows for the production of TRC populations with greater tissue repair and anti-inflammatory capabilities. Embodiments of the present invention include a post-culture process for cultured cells that preferably includes the steps of: a wash process for removing unwanted residual culture components, a volume reduction process, and a harvesting process to remove cultured cells. Preferably, all these steps are performed within a aseptically closed cell culture chamber by implementing a separation method that minimizes mechanical disruption of the cells and is simple to automate. The harvested cells may then be concentrated to a final volume for the intended use. In such embodiments, the final composition is a substantially purified and concentrated cell mixture suspended in a physiologic solution suitable for immediate use in humans without further washing, volume reduction, or processing. Embodiments are also applicable to harvesting (and/or washing) particles within a liquid or solution within a chamber.

2011-05-26

20110124106

SEPARATION DEVICE - A separation device for separating a wanted end product from a liquid sample comprises a container (

EPIGENETIC ENGINEERING - The invention concerns the field of cell culture technology. It concerns production host cell lines with increased expression of ribosomal RNA (rRNA) achieved through reducing expression of NoCR proteins, especially of TIP-5. Those cell lines have improved secretion and growth characteristics in comparison to control cell lines.

2011-05-26

20110124109

DNA MOLECULES AND METHODS - The present application discloses a DNA molecule comprising a modified Group II intron which does not express the intron-encoded reverse transcriptase but which contains a modified selectable marker gene in the reverse orientation, wherein the marker gene comprises a Group I intron in forward orientation of causing expression in a bacteria cell of the class Clostridia and wherein the DNA molecule comprises sequences that allow for the insertion of the RNA transcript of the Group II intron in the chromosome of a bacterial cell of the class Clostridia. A method of introducing a nucleic acid molecule into a site of a DNA molecule in a bacterial cell of the class Clostridia is also provided. The DNA molecule and the method are useful for making mutations

2011-05-26

20110124110

SYSTEMS AND METHODS FOR BREAST CANCER DETECTION AND RISK ASSESSMENT - The invention relates to a simple screening test for neoplasia, a precancerous condition, or cancer of the breast. A method is described whereby a breast cancer marker is detected in breast fluid. In a particular embodiment, the method involves treating samples of breast fluids with an aldehyde detecting reagent without any prewashing. The appearance in breast fluids of a marker that is detected by an aldehyde detecting reagent, such as a Schiff's reagent, correlates very well with the disease status of the breast cancer subjects from which the fluids were obtained. Screening test kits are also provided.

2011-05-26

20110124111

LOW-VOLUME SEQUENCING SYSTEM AND METHOD OF USE - Various embodiments of a low-volume sequencing system are provided herein. The system can include a low-volume flowcell having at least one reaction chamber of a defined volume (e.g., less than about 100 μl). The system can also include an automated reagent delivery mechanism configured to reversibly couple with the inlet port corresponding to a target reaction chamber thereby placing allowing for reagent to be accurately moved from a storage container to the reaction chamber with minimal reagent waste. The flowcells can include a plurality of reaction chambers (e.g., 6) thereby allowing for parallel analysis of multiple samples. Various methods of analyzing a biomolecule are also provided herein.

METHODS AND DEVICES FOR DETECTING UNSATURATED COMPOUNDS - Embodiments provide a method for detecting an unsaturated compound, the method comprising monitoring change in electrical properties of substances such as halides of copper that reacts or interacts with unsaturated compounds such as acetylene. Other embodiments provide a sensor for detecting acetylene gas comprising a substrate having a surface, electrodes in electrical communication with said surface, and a sensor layer formed of metal halide.

2011-05-26

20110124114

Assays - A method for assaying a sample for each of multiple analytes is described. The method includes contacting an array of spaced-apart test zones with a liquid sample (e.g., whole blood). The test zones disposed within a channel of a microfluidic device. The channel is defined by at least one flexible wall and a second wall which may or may not be flexible. Each test zone comprising a probe compound specific for a respective target analyte. The microfluidic device is compressed to reduce the thickness of the channel, which is the distance between the inner surfaces of the walls within the channel. The presence of each analyte is determined by optically detecting an interaction at each of multiple test zones for which the distance between the inner surfaces at the corresponding location is reduced. The interaction at each test zone is indicative of the presence in the sample of a target analyte. Capillary structures of the devices or used in the methods may comprise a matrix and the devices may comprise control elements and methods for assaying of sample may use corresponding controlling activities.

2011-05-26

20110124115

Indication enhanced colorimetric detector - The present invention pertains generally to colorimetric indicia provided by a primary device, and more particularly, to at least one indicator moiety influenced by changing environments wherein the indicator moiety exhibits a rapid initial response and a protracted transient time for visualization by an operator. As compared to heretofore colorimetric indicator technologies, the present invention allows for improved accuracy of data interpretation by direct visual capture of changing environments with shorter duration transients.

2011-05-26

20110124116

MULTI-ARRAY, MULTI-SPECIFIC ELECTROCHEMILUMINESCENCE TESTING - Materials and methods are provided for producing patterned multi-array, multi-specific surfaces for use in diagnostics. The invention provides for electrochemiluminescence methods for detecting or measuring an analyte of interest. It also provides for novel electrodes for ECL assays. Materials and methods are provided for the chemical and/or physical control of conducting domains and reagent deposition for use multiply specific testing procedures.

2011-05-26

20110124117

SERS NANOTAG ASSAYS WITH ENHANCED ASSAY KINETICS - Methods and systems for the use of surface-enhanced Raman scattering nanotags (SERS nanotags) in various assay platforms which feature accelerated reaction kinetics. One embodiment includes a method detecting a substance of interest by associating a SERS nanotag with the substance of interest while accelerating the reaction kinetics of the association steps. This method also includes detecting a Raman spectrum of a reporter molecule associated with the SERS nanotag. The reaction kinetics of the assay may be accelerated by applying microwave radiation to the sample, heating the sample, agitating the sample, mixing the sample, vibrating the sample or other methods.

METHODS FOR PREDICTING WEIGHT LOSS SUCCESS - Methods and kits for predicting weight loss success are provided. The methods generally include the steps of selecting a patient or other person undergoing or considering undergoing a weight loss therapy, obtaining a measurement of one or more hormone responses of the person to caloric intake, and subsequently predicting success of a weight loss therapy based on the hormone response.

2011-05-26

20110124122

BIOMARKERS AND ASSAYS FOR MYOCARDIAL INFARCTION - Presented herein are novel blood plasma/serum biomarkers related to cardiovascular disease. These newly identified biomarkers create the basis for multiple (single) assays using traditional bioassay technologies and when used in combination yield exceptional clinical sensitivity and specificity in the determination of myocardial infarction (MI). A multiplexed, mass spectrometric immunoassay (MSIA) able to simultaneously assay for the new/novel biomarkers as well other MI markers is also presented. Means and methods for evaluating data generated using multiple biomarkers in order to validate findings and further the use of the multiplexed MI assay in clinical, diagnostic and therapeutic uses is also included.

2011-05-26

20110124123

METHOD FOR EXAMINING WT1-RELATED DISEASE - The invention provides a method for testing a WT1-related disease, such as leukemia, a solid cancer, or an atypia, for diagnosing the disease, evaluating the course of cure and the prognosis of the disease more simply with high reliability, the method comprises measuring the amount of antibody against WT1 in a sample and using the measurement value and the time course of the value as a clinical marker for the testing.

2011-05-26

20110124124

ENHANCED DETECTION SENSITIVITY WITH PIEZOELECTRIC MICROCANTILEVER SENSORS - A method for enhancing the detection sensitivity of a piezoelectric microcantilever sensor. The method may involve providing a piezoelectric microcantilever and inducing a change in the Young's modulus during detection of a species of interest. The change in the Young's modulus may be induced or enhanced by the application of a DC bias electric field to the piezoelectric layer that enhances non-180° polarization domain switching of the piezoelectric layer. The change in the Young's modulus may also result from binding of the species of interest to the piezoelectric microcantilever sensor or a combination of binding and application of a DC bias electric field Significantly enhanced detection sensitivity results from the changed Young's modulus of the piezoelectric layer.

DETECTION OF AN ANALYTE IN AQUEOUS MEDIA - Test kit for the detection of an analyte in an aqueous solution, including chromatographic test strips for a hapten-antihapten complex and first and second standardized vessels for receiving and positioning test strips, which include first and second hapten-coupled receptors against the analyte dried onto the interior wall for the formation of the hapten-antihapten complex, where a portion of the standardized vessels further include a known amount of analyte embedded in a glass-like layer of trehalose, which are dried onto the interior wall of the control vessel so that they dissolve during reaction of the sample with the hapten-coupled receptors. Through this standardization, analytes in unknown samples may be safely detected by immunochromatography within minutes through a hapten-antihapten complex.

2011-05-26

20110124127

METHODS OF QUANTIFICATION FOR LATERAL FLOW DEVICES - The invention concerns methods of quantification of an analyte, A, in a test sample by means of a single immunochromatographic device, such as a lateral flow device (LFD). One method comprises the steps of: a) mixing a determined amount of said test sample with a determined amount of a quantification agent, QA

2011-05-26

20110124128

Centrifugal Force Based Microfluidic System And Method For The Automated Analysis of Samples - Centrifugal force based microfluidic systems for the automated analysis of fluids involving the use of magnetically responsive particles and methods thereof are disclosed. A magnet is fixed to a supporting device of the system in correspondence to a retention zone of the system so as to rotate therewith and to generate a magnetic field which magnetically manipulates the magnetically responsive particles contained in a reaction chamber of the system.

DEVICE AND METHOD FOR ANALYSIS OF SAMPLES WITH DEPLETION OF ANALYTE CONTENT - A system and method for determining the presence and/or concentration of one or more analytes in a sample that comprises a fluid, the system comprising a substrate comprising a sample inlet or inlets and one or more analyte determination flow paths, each analyte determination flow path comprising a defined beginning and a defined terminus and comprising at least one capture zone containing a capture agent for an analyte, the capture agent or agents being immobilized along a portion of the flow path or paths, the flow path or paths being designed so that the one or more analytes are depleted from the sample and bound to the portion of the flow path or paths containing immobilized capture agent or agents, producing an analyte depletion end region for each analyte between the beginning and the terminus of the analyte determination flow path.

2011-05-26

20110124131

METHOD FOR PREPARING METAL NANOPARTICLE USING METAL BINDING PROTEIN - The present invention relates to a method of preparing heavy metal nanoparticles using a heavy metal-binding protein. More specifically, relates to a method for preparing heavy metal structures, comprising the steps of: culturing a microorganism transformed with a gene encoding a heavy metal-binding protein, in a heavy metal ion-containing medium, to produce heavy metal structures in the microorganism; and collecting the produced heavy metal structures, as well as nanoparticles of heavy metal structures prepared according to said method. Unlike prior methods of preparing quantum dots by physically binding metal materials, en the quantum dots disclosed herein can be efficiently produced by expressing the heavy metal-binding protein in cells. In addition, the quantum dots are useful because they can solve an optical stability problem that is the shortcoming of organic fluorophores.

2011-05-26

20110124132

CENTRIFUGAL MICRO-FLUIDIC DEVICE AND METHOD FOR DETECTING TARGET IN FLUID SAMPLE - Disclosed are a centrifugal micro-fluidic device and an immunosorbent assay method using the same. In particular, a centrifugal micro-fluidic device having a plurality of micro-fluidic structures placed in a disc type platform to simultaneously conduct several immunosorbent assays, as well as an immunosorbent assay method using the same are provided.

END-CUT FIRST APPROACH FOR CRITICAL DIMENSION CONTROL - A method for fabricating a semiconductor device is disclosed. The method includes forming at least one material layer over a substrate; performing an end-cut patterning process to form an end-cut pattern overlying the at least one material layer; transferring the end-cut pattern to the at least one material layer; performing a line-cut patterning process after the end-cut patterning process to form a line-cut pattern overlying the at least one material layer; and transferring the line-cut pattern to the at least one material layer.

2011-05-26

20110124135

Solar Cell Module and Method for Assembling a Solar Cell Module - The invention relates to a method for assembly of solar cell modules by arranging a multitude pre-manufactured, individualized solar cells for forming a matrix of solar cells for the solar cell module; depositing a metallization layer at least partially on at least one surface of the matrix of solar cells for forming the solar cell module; testing electrical function at least of the solar cell module; depositing a passivation layer on a surface of the solar cell module. In another aspect the invention relates to a manufacturing system for a solar cell module and a solar cell module (

2011-05-26

20110124136

PROCESS FOR PRODUCING ORGANIC ELECTROLUMINESCENT PANEL - Provided is a process for producing an organic EL panel by using an ultrathin glass plate, in which the ultrathin glass plate is not “fractured” or “cut” in the production process, the organic EL element is formed reliably when formed by vacuum deposition, and recovered without damage after the production process, and there is no need for installing an additional step of cleaning the rear face of the ultrathin glass plate. The process for producing an organic EL panel according to the present invention is a process for producing an organic electroluminescent panel by forming an organic electroluminescent element on an ultrathin glass plate by vacuum deposition method, comprising forming electrodes on the ultrathin glass plate, by temporarily fixing the ultrathin glass plate to a supporting plate via a double-sided adhesive tape having a thermal release adhesive layer formed at least on one face of the base material layer, containing heat-expandable microspheres that start expansion and/or foaming at temperature higher than the vacuum deposition temperature.

2011-05-26

20110124137

ORGANIC ELECTRO-LUMINESCENCE DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is an organic electro-luminescence display device. The organic electro-luminescence display device includes: a first electrode, a first charge transport pattern, an organic emission pattern, a second charge transport pattern, and a second electrode. The first charge transport pattern is formed on the first electrode, and the organic emission pattern is on the first charge transport pattern. The second charge transport pattern is formed on the organic emission pattern, and includes an insoluble material. The second electrode is formed on the second charge transport pattern.

2011-05-26

20110124138

ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE AND METHOD OF PRODUCING THE SAME - An organic electroluminescent display device in which a plurality of light-emitting cells each having an organic electroluminescent portion are arranged on a substrate, wherein, for each of the light-emitting cells, a first transistor which controls energization on the organic electroluminescent portion, and a second transistor which switches a signal to be given to an input of the first transistor are disposed, active layers of the first and second transistors are formed by an amorphous oxide semiconductor, and, the first and second transistors are formed so that, when the first and second transistors are driven under same conditions, an amount of an output current of the first transistor is smaller than an amount of an output current of the second transistor.

2011-05-26

20110124139

METHOD FOR MANUFACTURING FREE-STANDING SUBSTRATE AND FREE-STANDING LIGHT-EMITTING DEVICE - The present invention provides a method for manufacturing a free-standing substrate, comprising: growing a first layer having a sacrificial layer on a growth substrate; patterning the first layer into a patterned first layer having a structure of a plurality of protrusions; growing a second layer on the patterned first layer having a structure of a plurality of protrusions by epitaxial lateral overgrowth; and separating the second layer from the growth substrate by etching away the sacrificial layer, wherein the separated second layer functions as a free-standing substrate for epitaxy. Also, the present invention provides a method for manufacturing a free-standing light-emitting device, comprising: growing a first layer having a sacrificial layer on a growth substrate; patterning the first layer into a patterned first layer having a structure of a plurality of protrusions; growing a second layer on the patterned first layer having a structure of a plurality of protrusions by epitaxy growth; forming a reflecting layer on the second layer; forming a conductive substrate on the reflecting layer; and separating the second layer, the reflecting layer, and the conductive substrate from the growth substrate by etching away the sacrificial layer, so as to form a free-standing light-emitting device.

2011-05-26

20110124140

SEMICONDUCTOR LASER DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor laser device includes a chip obtained from a substrate and a semiconductor multi-layer formed on the substrate. The semiconductor multi-layer is formed from a plurality of semiconductor layers of a semiconductor material having a hexagonal structure, and includes a stripe-shaped wave guide portion. The chip includes two chip end facets that extend in a direction crossing an extending direction of the wave guide portion. Each of regions on both sides of the wave guide portion in at least one of the chip end facets has a notch portion formed by notching a part of the chip, and the notch portion exposes a first wall surface connecting to the chip end facet and a second wall surface connecting to the chip side facet. An angle between an extending direction of the first wall surface in at least one of the two notch portions and an extending direction of the cleavage facet is in a range of about 10 degrees to about 40 degrees.

2011-05-26

20110124141

Method for Producing a Doped Organic Semiconducting Layer - A process is provided for producing a doped organic semiconductive layer, comprising the process steps of A) providing a matrix material, B) providing a dopant complex, and C) simultaneously applying the matrix material and the dopant complex to a substrate by vapor deposition, wherein, in process step C), the dopant complex is decomposed and the pure dopant is intercalated into the matrix material.

PACKAGED DEVICE AND METHOD OF MANUFACTURING THE SAME - A packaged device includes a package having an inner surface defining a closed internal space, a device chip fixed to the package in the internal space, and a parylene film covering at least a part of the inner surface of the package and/or at least a part of a surface of the device chip.

2011-05-26

20110124144

SUBSTRATE PROCESSING SYSTEM AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus includes an evacuatable process chamber configured to receive a substrate carrier having at least one substrate, a plasma generating module, a gas feed, a gas discharge and a vapor etching module provided in the process chamber. A substrate processing method includes introducing a substrate carrier including at least one substrate into an evacuatable process chamber, generating a plasma in a plasma process using a plasma generating module in a gas or a gas mixture, performing a vapor etching of the at least one substrate before, after or alternatingly with the plasma process and performing at least one of a coating, etching, surface modification and cleaning of the substrate.

METHOD FOR SEPARATING SILICON SOLAR CELLS - In a method for separating silicon solar cells, a groove is introduced into a silicon wafer containing the silicon solar cells along a separating line in a front side of the silicon wafer adjacent to a p-n junction in the silicon wafer using a first laser beam. The groove has a depth reaching at least to the p-n junction and extends to a lateral edge of the silicon wafer. In a second work step, the silicon wafer is cut along the separating line starting at the lateral edge using a second laser beam directed into the groove. Wherein the melt arising during the cutting is driven out of the cutting kerf arising during the cutting using a cutting gas flowing at least approximately in the direction of the second laser beam.

Chalcogenide Absorber Layers for Photovoltaic Applications and Methods of Manufacturing the Same - In one example embodiment, a method includes depositing one or more thin-film layers onto a substrate. More particularly, at least one of the thin-film layers comprises at least one electropositive material and at least one of the thin-film layers comprises at least one chalcogen material suitable for forming a chalcogenide material with the electropositive material. The method further includes annealing the one or more deposited thin-film layers at an average heating rate of or exceeding 1 degree Celsius per second. The method may also include cooling the annealed one or more thin-film layers at an average cooling rate of or exceeding 0.1 degrees Celsius per second.

2011-05-26

20110124151

PHOTOVOLTAIC DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is the gist of the present invention to provide a photovoltaic device in which a single crystal semiconductor layer provided over a substrate having an insulating surface or an insulating substrate is used as a photoelectric conversion layer, and the single crystal semiconductor layer is provided with a so-called SOI structure where the single crystal semiconductor layer is bonded to the substrate with an insulating layer interposed therebetween. As the single crystal semiconductor layer having a function as a photoelectric conversion layer, a single crystal semiconductor layer obtained by separation and transfer of an outer layer portion of a single crystal semiconductor substrate is used.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device having stable electric characteristics in which an oxide semiconductor is used. An oxide semiconductor layer is subjected to heat treatment for dehydration or dehydrogenation treatment in a nitrogen gas or an inert gas atmosphere such as a rare gas (e.g., argon or helium) or under reduced pressure and to a cooling step for treatment for supplying oxygen in an atmosphere of oxygen, an atmosphere of oxygen and nitrogen, or the air (having a dew point of preferably lower than or equal to −40° C., still preferably lower than or equal to −50° C.) atmosphere. The oxide semiconductor layer is thus highly purified, whereby an i-type oxide semiconductor layer is formed. A semiconductor device including a thin film transistor having the oxide semiconductor layer is manufactured.

2011-05-26

20110124154

HYBRID STRUCTURE OF MULTI-LAYER SUBSTRATES AND MANUFACTURE METHOD THEREOF - A hybrid structure of multi-layer substrates comprises a first multi-layer substrate and a second multi-layer substrate. The first multi-layer substrate stacks up first metal layers, first dielectric layers alternately and has VIAs. A border district of a first metal layer connects with a border district of the corresponding first dielectric layer. The border districts are separated from adjacent first metal layers and adjacent first dielectric layers. The second multi-layer substrate stacks up second metal layers and second dielectric layers alternately. A border district of a second metal layer connects with a border district of the corresponding second dielectric layer. The border districts are separated from adjacent second metal layers and adjacent second dielectric layers. The VIAs are located at the border districts of the first dielectric layers and each VIA has electric conductor therein to connect one first metal layer with one second metal layer.

2011-05-26

20110124155

HYBRID STRUCTURE OF MULTI-LAYER SUBSTRATES AND MANUFACTURE METHOD THEREOF - A hybrid structure of multi-layer substrates comprises a first multi-layer substrate and a second multi-layer substrate. The first multi-layer substrate stacks up first metal layers, first dielectric layers alternately and has VIAs. A border district of a first metal layer connects with a border district of the corresponding first dielectric layer. The border districts are separated from adjacent first metal layers and adjacent first dielectric layers. The second multi-layer substrate stacks up second metal layers and second dielectric layers alternately. A border district of a second metal layer connects with a border district of the corresponding second dielectric layer. The border districts are separated from adjacent second metal layers and adjacent second dielectric layers. The VIAs are located at the border districts of the first dielectric layers and each VIA has electric conductor therein to connect one first metal layer with one second metal layer.

2011-05-26

20110124156

Method of Fabricating Semiconductor Die with Through-Hole Via on Saw Streets and Through-Hole Via in Active Area of Die - A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. Metal vias are also formed through the contact pads on the active area of the die. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. Repassivation layers are formed between the RDL for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The vias through the saw streets and vias through the active area of the die, as well as the RDL, provide electrical interconnect to the adjacent die.

2011-05-26

20110124157

METHOD FOR ENCAPSULATING ELECTRONIC COMPONENTS ON A WAFER - A method for encapsulating electronic components, including the steps of: forming, in a first surface of a semiconductor wafer, electronic components; forming, on the first surface, an interconnection stack including conductive tracks and vias separated by an insulating material; forming first and second bonding pads on the interconnection stack; thinning down the wafer, except at least on its contour; filling the thinned-down region with a first resin layer; arranging at least one first chip on the first bonding pads and forming solder bumps on the second bonding pads; depositing a second resin layer covering the first chips and partially covering the solder bumps; bonding an adhesive strip on the first resin layer; and scribing the structure into individual chips.

STRUCTURE AND METHOD FOR FABRICATING A MICROELECTRONIC DEVICE PROVIDED WITH ONE OR MORE QUANTUM WIRES ABLE TO FORM ONE OR MORE TRANSISTOR CHANNELS - The disclosure concerns a microelectronic device provided with one or more <>, able to form one or more transistor channels, and optimized in terms of arrangement, shape or/and composition. The invention also uses a method for fabricating said device, comprising the steps of: the forming, in one or more thin layers resting on a support, of a first block and a second block in which at least one transistor drain region and at least one transistor source region are respectively intended to be formed, and of a structure connecting the first block to the second block, and the forming, on the surface of the structure, of wires connecting a first region of the first block with another region of the second block which faces the first region.

2011-05-26

20110124162

METHOD OF FABRICATING ARRAY SUBSTRATE - A method of fabricating an array substrate includes forming a gate line and a gate electrode; forming a gate insulating layer, an intrinsic amorphous silicon layer, an inorganic material insulating layer and a heat transfer layer on the gate line and the gate electrode; irradiating a laser beam onto the heat transfer layer to crystallize the intrinsic amorphous silicon layer into a polycrystalline silicon layer; removing the heat transfer layer; patterning the inorganic insulating material layer using a buffered oxide etchant to form an etch-stopper corresponding to the gate electrode forming an impurity-doped amorphous silicon layer and a metal layer on the etch-stopper and the polycrystalline silicon layer; patterning the metal layer to form a data line, a source electrode and a drain electrode and forming a pixel electrode on the passivation layer.

2011-05-26

20110124163

THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE SAME - A manufacturing method of a thin film transistor (TFT) includes forming a gate electrode including a metal that can be combined with silicon to form silicide on a substrate and forming a gate insulation layer by supplying a gas which includes silicon to the gate electrode at a temperature below about 280° C. The method further includes forming a semiconductor on the gate insulation layer, forming a data line and a drain electrode on the semiconductor and forming a pixel electrode connected to the drain electrode.

2011-05-26

20110124164

METHOD FOR MANUFACTURING SOI SUBSTRATE AND SEMICONDUCTOR DEVICE - An amorphous semiconductor layer is formed over a first single crystal semiconductor layer provided over a glass substrate or a plastic substrate with an insulating layer therebetween. The amorphous semiconductor layer is formed by a CVD method at a deposition temperature of higher than or equal to 100° C. and lower than or equal to 275° C. with use of a silane-based gas not diluted. Heat treatment is performed so that the amorphous semiconductor layer solid-phase epitaxially grows. In such a manner, an SOI substrate including a thick single crystal semiconductor layer is manufactured.

2011-05-26

20110124165

Structure and Method for Manufacturing Device with a V-Shape Channel NMosfet - A CMOS structure includes a v-shape surface in an nMOSFET region. The v-shape surface has an orientation in a (100) plane and extends into a Si layer in the nMOSFET region. The nMOSFET gate dielectric layer is a high-k material, such as Hf02. The nMOSFET has a metal gate layer, such as Ta. Poly-Si is deposited on top of the metal gate layer.

2011-05-26

20110124166

Memory device and method of manufacturing the same - In a memory device and a method of manufacturing the memory device, a source contact connected to a common source line may be formed on a drain region instead of a source region. A transistor having a negative threshold voltage may be formed between the source region and the drain region. A channel of the transistor may be formed. Because the source contact is formed on the drain region, the size of the source region may be reduced. An integration degree of the memory device may be improved. A control gate may linearly extend in a second direction because the source contact is not formed on the source region.

METHODS OF SELECTIVELY DEPOSITING AN EPITAXIAL LAYER - Methods for selectively depositing an epitaxial layer are provided herein. In some embodiments, providing a substrate having a monocrystalline first surface and a non-monocrystalline second surface; exposing the substrate to a deposition gas to deposit a layer on the first and second surfaces, the layer comprising a first portion deposited on the first surfaces and a second portion deposited on the second surfaces; and exposing the substrate to an etching gas comprising a first gas comprising hydrogen and a halogen and a second gas comprising at least one of a Group III, IV, or V element to selectively etch the first portion of the layer at a slower rate than the second portion of the layer. In some embodiments, the etching gas comprises hydrogen chloride (HCl) and germane (GeH

2011-05-26

20110124170

PROCESS FOR FABRICATING A SELF-ALIGNED DEPOSITED SOURCE/DRAIN INSULATED GATE FIELD-EFFECT TRANSISTOR - Processes for forming self-aligned, deposited source/drain, insulated gate, transistors and, in particular, FETs. By depositing a source/drain in a recess such that it remains only in the recess, the source/drain can be formed self-aligned to a gate and/or a channel of such a device. For example, in one such process a gate structure of a transistor may be formed and, in a material surrounding the gate structure, a recess created so as to be aligned to an edge of the gate structure. Subsequently, a source/drain conducting material may be deposited in the recess. Such a source/drain conducting material may be deposited, in some cases, as layers, with one or more such layers being planarized following its deposition. In this way, the conducting material is kept within the boundaries of the recess.

2011-05-26

20110124171

APPLYING EPITAXIAL SILICON IN DISPOSABLE SPACER FLOW - A method of fabricating transistors on a semiconductor substrate includes forming transistor gates of first and second transistors located in first and second areas of the semiconductor substrate, respectively. The transistor gates have generally vertical sidewalls. Source and drain regions are simultaneously formed for the first and second transistors. Temporary spacers are formed on the vertical sidewalls of the first and second transistor gates. The temporary spacers of the first transistor abut a semiconductor structure such that the source and drain regions of the first transistor are vertically covered. The temporary spacers of the second transistor cover a portion of the source and drain regions of the second transistor such that a portion of the source and drain regions remain exposed. The semiconductor substrate is exposed to an implant dopant to change the dopant level of the exposed portions of the source and drain regions of the second transistors.

Method of Manufacturing Semiconductor Device - Methods of manufacturing a semiconductor device include forming a gate electrode on a semiconductor substrate, forming spacers on side walls of the gate electrode, and doping impurities into the semiconductor substrate on both sides of the spacers to form highly doped impurity regions. The spacers are selectively etched to expose portions of the semiconductor substrate, and more lightly doped impurity regions are formed in the semiconductor substrate between the highly doped impurity regions and the gate electrode.

2011-05-26

20110124174

METHOD OF FORMING VARIABLE RESISTANCE MEMORY DEVICE - Provided are a method of forming an electrode of a variable resistance memory device and a variable resistance semiconductor memory device using the method. The method includes: forming a heat electrode; forming a variable resistance material layer on the heat electrode; and forming a top electrode on the variable resistance material layer, wherein the heat electrode includes a nitride of a metal whose atomic radius is greater than that of titanium (Ti) and is formed through a thermal chemical vapor deposition (CVD) method without using plasma.

2011-05-26

20110124175

ALTERATION METHOD AND ALTERATION APPARATUS FOR TITANIUM NITRIDE - An alteration method of a titanium nitride film, comprising exposing a titanium nitride film formed on a semiconductor substrate to plasma obtained by exciting a process gas that includes noble gas or nitrogen and excludes oxygen, thereby increasing a specific resistance of the titanium nitride film.

2011-05-26

20110124176

METHODS OF FORMING A CAPACITOR STRUCTURE AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - In a method of forming a capacitor, a seed stopper and a sacrificial layer is formed on an insulating interlayer having a plug therethrough. An opening is formed through the sacrificial layer and the seed stopper to expose the plug. A seed is formed on an innerwall of the opening. A lower electrode is formed covering the seed on the innerwall of the opening. The sacrificial layer and the seed are removed. A dielectric layer and an upper electrode are sequentially formed on the lower electrode.

2011-05-26

20110124177

SIMULTANEOUSLY FORMED ISOLATION TRENCH AND THROUGH-BOX CONTACT FOR SILICON-ON-INSULATOR TECHNOLOGY - A semiconductor fabrication method comprises providing a structure which includes a semiconductor substrate having a plurality of subsurface layers, the substrate comprising a top surface and the subsurface layers comprising a top subsurface layer below the top surface of the substrate. A protective material is patterned on the top surface of the device and a material removal process is performed to simultaneously form a contact trench and an isolation trench, the material removal process removing at least a portion of the top surface and the top subsurface layer such that the contact trench and the isolation trench are formed within the subsurface layer. An insulator is then formed within the isolation trench and the contact trench is lined with the insulator. The contact trench is then filled with a conductive material such that the conductive material is deposited over the insulator.

2011-05-26

20110124178

STRUCTURE AND METHOD OF FABRICATING A TRANSISTOR HAVING A TRENCH GATE - An integrated circuit transistor is fabricated with a trench gate having nonconductive sidewalls. The transistor is surrounded by an isolation trench filled with a nonconductive material. The sidewalls of the gate trench are formed of the nonconductive material and are substantially free of unetched substrate material. As a result, the sidewalls of the gate trench do not form an undesired conductive path between the source and the drain of the transistor, thereby advantageously reducing the amount of parasitic current that flows between the source and drain during operation.

2011-05-26

20110124179

SOI SUBSTRATE AND MANUFACTURING METHOD THEREOF - The semiconductor substrate provided with a groove portion is irradiated with ions so that an embrittled region is formed in the semiconductor substrate, the semiconductor substrate and a base substrate are bonded to each other with an insulating layer interposed therebetween and a space which is surrounded by the groove portion in the semiconductor substrate and the base substrate is formed, and heat treatment is performed to separate the semiconductor substrate at the embrittled region, so that the semiconductor layer is formed over the base substrate with the insulating layer interposed therebetween.

2011-05-26

20110124180

SEMICONDUCTOR DEVICE MANUFACTURING METHOD COMPRISING A METAL PATTERN AND LASER MODIFIED REGIONS IN A CUTTING REGION - To divide a semiconductor wafer by stealth dicing, a test pad in a cutting region and an alignment target are collectively arranged along one side in a width direction of the cutting region, and a laser beam for forming a modified region is irradiated to a position away in plane from the test pad and the alignment target Am. In this manner, defects in cutting shape in a cutting process of a semiconductor wafer using stealth dicing can be reduced or prevented.

2011-05-26

20110124181

WORKPIECE CUTTING METHOD - A cutting method for cutting a workpiece by using a cutting blade. The cutting method includes the steps of attaching an adhesive sheet to one surface of the workpiece, holding the workpiece through the adhesive sheet on holding means, and feeding the cutting blade into the workpiece until reaching the adhesive sheet as supplying a cutting fluid having a temperature of 10° C. or less, thereby cutting the workpiece.

2011-05-26

20110124182

SYSTEM FOR THE DELIVERY OF GERMANIUM-BASED PRECURSOR - A supply of a germanium precursor such as germanium n-butylamidinate is provided in close proximity to a microelectronic device substrate to be contacted therewith for deposition of germanium-containing material on the substrate. Specific arrangements are described, including tray and reservoir structures from which solid, liquid, suspended or dissolved germanium precursor can be volatilized for transport to the substrate surface together with other precursors, carrier gases, co-reactants or the like. In such manner, the germanium precursor can be activated independently of the activation of other precursors, within the deposition chamber, to achieve highly efficient formation of germanium-containing material on the substrate, e.g., a GST film of a phase change memory device.

Method of forming polysilicon, thin film transistor using the polysilicon, and method of fabricating the thin film transistor - A method of forming polysilicon, a thin film transistor (TFT) using the polysilicon, and a method of fabricating the TFT are disclosed. The method of forming the polysilicon comprises: forming an insulating layer on a substrate; forming a first electrode and a second electrode on the insulating layer; forming at least one heater layer on the insulating layer so as to connect the first electrode and the second electrode; forming an amorphous material layer containing silicon on the heater layer(s); forming a through-hole under the heater layer(s) by etching the insulating layer; and crystallizing the amorphous material layer into a polysilicon layer by applying a voltage between the first electrode and the second electrode so as to heat the heater layer(s).

2011-05-26

20110124185

GRADED CORE/SHELL SEMICONDUCTOR NANORODS AND NANOROD BARCODES - Graded core/shell semiconductor nanorods and shapped nanorods are disclosed comprising Group II-VI, Group III-V and Group IV semiconductors and methods of making the same. Also disclosed are nanorod barcodes using core/shell nanorods where the core is a semiconductor or metal material, and with or without a shell. Methods of labeling analytes using the nanorod barcodes are also disclosed.

2011-05-26

20110124186

APPARATUS AND METHOD FOR CONTROLLABLY IMPLANTING WORKPIECES - A plasma processing apparatus comprises a plasma source configured to produce a plasma in a plasma chamber, such that the plasma contains ions for implantation into a workpiece. The apparatus also includes a focusing plate arrangement having an aperture arrangement configured to modify a shape of a plasma sheath of the plasma proximate the focusing plate such that ions exiting an aperture of the aperture arrangement define focused ions. The apparatus further includes a processing chamber containing a workpiece spaced from the focusing plate such that a stationary implant region of the focused ions at the workpiece is substantially narrower that the aperture. The apparatus is configured to create a plurality of patterned areas in the workpiece by scanning the workpiece during ion implantation.

2011-05-26

20110124187

VAPOR PHASE DEPOSITION PROCESSES FOR DOPING SILICON - A process of doping a silicon layer with dopant atoms generally includes reacting a vapor of a dopant precursor with oxide and/or hydroxide reactive sites present on the silicon layer to form a self assembled monolayer of dopant precursor; hydrolyzing the self assembled monolayer of the dopant precursor with water vapor to form pendant hydroxyl groups on the dopant precursor; capping the self assembled monolayer with an oxide layer; and annealing the silicon layer at a temperature effective to diffuse dopant atoms from the dopant precursor into the silicon layer. Additional monolayers can be formed in a similar manner, thereby providing controlled layer-by-layer vapor phase deposition of the dopant precursor compounds for controlled doping of silicon.

2011-05-26

20110124188

METHODS OF FABRICATING ELECTRODES AND USES THEREOF - The present invention relates to methods for fabricating nanoscale electrodes separated by a nanogap, wherein the gap size may be controlled with high precision using a self-aligning aluminum oxide mask, such that the gap width depends upon the thickness of the aluminum oxide mask. The invention also provides methods for using the nanoscale electrodes.

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, a copper-containing metal interconnect over the semiconductor substrate, and a copper-containing connection plug, and the metal interconnect includes metal elements other than copper, and a concentration of different metal elements in a connection portion between the metal interconnect and the connection plug is higher than a concentration of the different metal elements in a center portion of the metal interconnect, and higher than a concentration of different elements in upper face portion of the metal interconnect other than the connection portion.

2011-05-26

20110124191

COMPOSITIONS FOR THE CURRENTLESS DEPOSITION OF TERNARY MATERIALS FOR USE IN THE SEMICONDUCTOR INDUSTRY - The present invention relates to the use of ternary nickel-containing metal alloys of the NiMR type (where M=Mo, W, Re or Cr, and R=B or P) deposited by an electroless process in semiconductor technology. In particular, the present invention relates to the use of these deposited ternary nickel-containing metal alloys as barrier material or as selective encapsulation material for preventing the diffusion and electromigration of copper in semiconductor components.

2011-05-26

20110124192

PROCESS FOR FORMING COBALT-CONTAINING MATERIALS - Embodiments of the invention described herein generally provide methods and apparatuses for forming cobalt silicide layers, metallic cobalt layers, and other cobalt-containing materials. In one embodiment, a method for forming a cobalt silicide containing material on a substrate is provided which includes exposing a substrate to at least one preclean process to expose a silicon-containing surface, depositing a cobalt silicide material on the silicon-containing surface, depositing a metallic cobalt material on the cobalt silicide material, and depositing a metallic contact material on the substrate. In another embodiment, a method includes exposing a substrate to at least one preclean process to expose a silicon-containing surface, depositing a cobalt silicide material on the silicon-containing surface, expose the substrate to an annealing process, depositing a barrier material on the cobalt silicide material, and depositing a metallic contact material on the barrier material.

2011-05-26

20110124193

CUSTOMIZED PATTERNING MODULATION AND OPTIMIZATION - The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes providing an IC design layout of a circuit; applying an electrical patterning (ePatterning) modification to the IC design layout according to an electrical parameter of the circuit and an optical parameter of IC design layout; and thereafter fabricating a mask according to the IC design layout.

2011-05-26

20110124194

METHODS OF MANUFACTURING SEMICONDUCTORS USING DUMMY PATTERNS - A method of manufacturing a semiconductor device is provided. A pattern layer is formed on a substrate defined to include a main pattern region and a dummy pattern region. A preliminary main pattern and a preliminary dummy pattern may be formed by patterning the pattern layer so that an upper surface area of the preliminary dummy pattern facing away from a surface of the substrate is less than an entire area of the dummy pattern region that is be subjected to subsequent planarization. The preliminary main pattern and the preliminary dummy pattern are partially etched to form a main pattern and a dummy pattern.

2011-05-26

20110124195

Chemical Mechanical Polishing Composition Containing Polysilicon Polish Finisher - Provided are a chemical mechanical polishing (CMP) composition used for polishing a semiconductor device which contains polysilicon film and insulator, and a chemical mechanical polishing method thereof. The CMP composition is especially useful in a isolation CMP process for semiconductor devices. Provided is a highly selective CMP composition containing a polysilicon polish finisher which can selectively polish semiconductor insulators since it uses a polysilicon film as a polish finishing film.

2011-05-26

20110124196

METHOD FOR FORMING FINE PATTERN IN SEMICONDUCTOR DEVICE - A method for forming a contact hole of a semiconductor device according to the present invention forms a contact hole which is defined as a new contact hole region (a second contact hole region), between spacers as well as a contact hole defined within the spacer (a first contact hole region) by a spacer patterning technology (SPT). The present invention with this method can help to form a fine contact hole as a double patterning is used, even with one mask.

METHOD OF MANUFACTURING FINE PATTERNS OF SEMICONDUCTOR DEVICE - A method of forming fine patterns of a semiconductor device comprises forming sacrificial film patterns of a line type in a cell region of a semiconductor substrate and, at the same time, forming pad patterns in a peripheral region of the semiconductor substrate, forming a spacer on sidewalls of each of the sacrificial film patterns and the pad patterns, forming a gap-fill layer on sidewalls of the spacers to thereby form line and space patterns, including the sacrificial film patterns and the gap-fill layers, in the cell region, and separating the line and space patterns of the cell region at regular intervals and, at the same time, etching the pad patterns of the peripheral region to thereby form specific patterns in the peripheral region.

2011-05-26

20110124199

APPARATUS AND METHOD FOR HIGH-THROUGHPUT ATOMIC LAYER DEPOSITION - Atomic layer deposition apparatus for depositing a film in a continuous fashion. The apparatus includes a process tunnel, extending in a transport direction and bounded by at least a first and a second wall. The walls are mutually parallel and allow a flat substrate to be accommodated there between. The apparatus further includes a transport system for moving a train of substrates or a continuous substrate in tape form, through the tunnel. At least the first wall of the process tunnel is provided with a plurality of gas injection channels that, viewed in the transport direction, are connected successively to a first precursor gas source, a purgegas source, a second precursor gas source and a purge gas source respectively, so as to create a tunnel segment that—in use—comprises successive zones containing a first precursor gas, a purge gas, a second precursor gas and a purge gas, respectively.

2011-05-26

20110124200

METHOD AND APPARATUS OF PLASMA TREATMENT - The present invention provides a plasma treatment apparatus and a conditioning method capable of performing a conditioning for the whole vacuum chamber. A plasma treatment apparatus according to an embodiment of the present invention is provided with a moving means for moving a substrate holder (

2011-05-26

20110124201

CHEMICAL VAPORIZER FOR MATERIAL DEPOSITION SYSTEMS AND ASSOCIATED METHODS - System and method for operating a material deposition system are disclosed. In one embodiment, the method can include periodically injecting a precursor into a vaporizer through an injector at the vaporizer, vaporizing the precursor in the vaporizer and supplying the vaporized precursor to a reaction chamber in fluid communication with the vaporizer, and shutting down the vaporizer and the reaction chamber after a period of time. The method can also include conducting maintenance of the injector at the vaporizer by using a vapor solvent rinse.

2011-05-26

20110124202

PLASMA PROCESSING METHOD AND COMPUTER STORAGE MEDIUM - According to the present invention, when a nitridation process by plasma generated by a microwave is applied to a substrate with an oxide film having been formed thereon to form an oxynitride film, the microwave is intermittently supplied. By the intermittent supply of the microwave, ion bombardment is reduced in accordance with a decrease in electron temperature, and a diffusion velocity of nitride species in the oxide film lowers, which as a result makes it possible to prevent nitrogen from concentrating in a substrate-side interface of an oxynitride film to increase the nitrogen concentration therein. Consequently, it is possible to improve quality of the oxynitride film, resulting in a reduced leakage current, an improved operating speed, and improved NBTI resistance.