Dear all,
I'd like to access a register via multiple physical interfaces (bfm).
Is it possible to set 2 different sequencers to the registers with same address?
I have read this is a known issue from this forum.
Could anybody give me a good example?
I'm looking for a solution that there is no problem in prediction as well as write/read of UVM_REG.
Thanks & Regards,

Hi,
I am testing multiple reset.
My testbench is based on UVM_REG and I am using "write()" API to write registers.
If reset is asserted when write() is executed, the next warning occurs.
UVM_WARNING (UVM/FLD/SET/BSY) Setting the value of field "xxx" while containing register "yyy" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
As I debugged, the error is caused by "m_is_busy" variable of uvm_reg.svh.
While write() is executed "m_is_busy" is set to 1 and set to 0.
When reset is asserted, user scenario kills write() operation and reset all registers as calling reg_block.reset().
If reg_block.reset() is executed, mirrored value seems to be reset but desired value does not.
And also, if reset is asserted between the time that "m_is_busy" is set to 1 and the time that "m_is_busy" is set to 0, "m_is_busy" remains "1". The same register is accessed later again, the above warning occurs.
I think this warning is no effect for simulation result. But I want to clear this warning.
Should user control UVM internal variable such as m_is_busy?
When reset is asserted, what is right that which value the desired value of field has?
How can I clear this warning?
Thanks & Regards,
yyn

Dear Karandeep,
Thanks for your reply.
I solved the problem. Your answer is very helpful. Thanks a lot.
I'm developing VIP based on UVM.
This error is related to VIP and user scenario for multiple reset test.
According to the time when reset is started and ended, this error occurs case by case.
Bye.

Hi,
I am implementing multiple reset inside UVC componenets (sequencer, driver, monitor and etc).
When reset is asserted between get_next_item() and item_done(), the following error is issued.
UVM_ERROR (SEQREQZMB) The task responsible for requesting a wait_for_grant on sequencer '....' for sequence '...' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues.
I guess this error is caused that queue for sequence item already gets a item to transfer into driver.
How can I fix this problem?
How can I remove current item from the arbitration queue?
My UVC is using run_phase(). I don't use main_phase().
So, I would like to control it using run_phse().
Thanks & Regards,

Hi,
I have a question when I use uvm_config_db for interface connection.
Generally, I know we use set() and get() function of "uvm_config_db" when we connect interface instance with virtual interface.
As I know, uvm_config_db#(virtual aaa_intf)::set() is described inside top testbench module.
And uvm_config_db#(virtual aaa_intf)::get() is some phase of inside class.
What I want to do is to move set() function into some phase of class.
Is it possible?
If possible, which phase can I use not to be no problem in topology?
Could you give me an example?
I generally descirbes uvm_config_db#(virtual aaa_intf)::get() in connect_phase.
Thanks & Regards,
YYN

Dear,
I am simulating on IES using AXI UVC from Cadence.
And the register is written using "write()" task from UVM.
In this case, "reg2bus()" of register adapter class translates uvm_reg_bus_op into vr_axi_master_burst which is a sequence item of AXI. Also, "bus2reg" function updates bus_item into uvm_reg_bus_op.
But transactions for setting registers are sent as non-blocking way.
I want to implement blocking way.
Blocking operation means that transaction for the next register is sent after transaction of the current register is sent and that transaction is ended.
But, currently the second transaction is started before the previous transaction of AXI interface is ended.
I want to control blocking operation in register adapter.
How can I impelemt register adapter class?
Thanks & Regards,
//yyn

Hello mszabo,
Thanks for reply.
I have a question for your answer.
I am using UVM1.1 and my adapter has only bus2reg() and reg2bus() function.
Where can I add "has_response"?
Can you show me the example?
Thanks & Regards,
yyn

Hello,
My test case reads the register data from DUT using mirror() after reset is ended.
But, the error occurrs like this.
[195] UVM_ERROR (RegModel) Register "xxxx" value read from DUT (0x0000) does not match mirrored value (0x80).
In my testbench, the register is set through AXI interface. The time "195 ns" that the error is reported is the time that read transaction is started. Actually, the readback value from DUT appears in "245 ns".
I think the datas between the DUT readback value and the expected value of register package are compared in end of read transaction. But mirror() function of uvm_reg compares the data at the start of transaction.
How can I fix my problem?
How can I implement that the data can be compared at the end of transaction?
Thanks & Regards,
yyn

Hi uwes,
Error is compilation error of IES.
Actually I already asked to Cadence support center, and I am still waiting for reply. But this is very urgent to me.
Error message is "E, TYCMPAT: formal and actual do not have assignment compatible data types (expecting datatype compatible with 'specialization of class uvm_port_base' but found 'specialization of class uvm_analysis_imp' instead).
I hope to obtain solution anywhere quickly.
Thanks for your interest in advance.

Hello,
I have a question for analysis port connection.
A UVC monitor that I use provides anaylsis port as followings (I provided this monitor from vendor).
**************************************************
uvm_analysis_port #(uvm_sequence_item) monitor_item_done;
**************************************************
I'd like to connect this port to "bus_in" of "uvm_reg_predictor" in my testbench.
"bus_in" is a port that is provided from UVM library.
*****************************************************
uvm_anaylsis_imp #(BUSTYPE, uvm_reg_dredictor #(BUSTYPE)) bus_in;
*****************************************************
In my testbench code, I connected as followings, but this does not work in simulator.
*********************************************************
if_env.master.monitor.monitor_item_done.connect(bus2reg_predictor.bus_in);
*********************************************************
"axi2reg_predictor" is the handler name of "uvm_reg_predictor".
How can I connect "bus_in" with "monitor_item_done"?
Thanks & Regards,

Dear jadec,
Thanks for your answer.
If possible, could you give an example code of your answer?
Is there good example using built-in functions such as get_coverage() and include_coverage() for customized type "UVM_CVR_REG_KIND" ?
I'd like to contorl coverage on or off as below after adding my type :
uvm_reg::include_coverage("*", UVM_CVR_REG_KIND + UVM_CVR_FIELD_VALS);
Thanks a lot.
YYN