Hanyi Ding, Essex Junction US

Hanyi Ding, Essex Junction, VT US

Patent application number

Description

Published

20080277769

Package Integrated Soft Magnetic Film for Improvement In On-Chip Inductor Performance - An integrated circuit package includes an integrated circuit with one or more on-chip inductors. A package cover covers the integrated circuit. A magnetic material is provided between the integrated circuit and the package cover. The magnetic material may be a soft magnetic thin film. The magnetic material may be affixed to the package cover by an adhesive. The magnetic material may be formed directly on the package cover by one of deposition, sputtering or spraying. The magnetic material may be affixed to the integrated circuit.

11-13-2008

20090052153

ON CHIP SHIELDING STRUCTURE FOR INTEGRATED CIRCUITS OR DEVICES ON A SUBSTRATE AND METHOD OF SHIELDING - An electromagnetic shielding structure that includes a conductive structure surrounding and accommodating a circuit or a circuit device arranged on a substrate. At least one feed through device is associated with the conductive structure and provides signals to the circuit or circuit device. The method includes forming a shielding structure so that the shielding structure at least one of is at least partially arranged within the substrate and surrounds the circuit or circuit device and associating at least one feed through device with the shielding structure.

02-26-2009

20090055790

DESIGN STRUCTURE FOR ON CHIP SHIELDING STRUCTURE FOR INTEGRATED CIRCUITS OR DEVICES ON A SUBSTRATE - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure comprises: a conductive structure surrounding and accommodating a circuit or a circuit device arranged on a substrate and at least one feed through capacitor and one transmission line associated with the conductive structure and providing the power supply and signals to the circuit or circuit device respectively. The design structure also comprises a shielding structure surrounding a circuit or a circuit device arranged on a substrate and at least one feed through capacitor or a transmission line arranged on a side of the shielding structure.

METHODS OF FABRICATING COPLANAR WAVEGUIDE STRUCTURES - Methods for fabricating a coplanar waveguide structure. The method may include forming first and second ground conductors and a signal conductor in a coplanar arrangement between the first and second ground conductors, forming a first coplanar array of substantially parallel shield conductors above the signal conductor and the first and second ground conductors, and forming a second coplanar array of substantially parallel shield conductors below the signal conductor and the first and second ground conductors. The method further includes forming a first plurality of conductive bridges located laterally between the signal conductor and the first ground conductor, and forming a second plurality of conductive bridges located laterally between the signal conductor and the second ground conductor. Each of the first plurality of conductive bridges connects one of the shield conductors in the first array with one of the shield conductors in the second array. Each of the second plurality of conductive bridges connects one of the shield conductors in the first array with one of the shield conductors in the second array.

10-08-2009

20090251232

COPLANAR WAVEGUIDE STRUCTURES AND DESIGN STRUCTURES FOR RADIOFREQUENCY AND MICROWAVE INTEGRATED CIRCUITS - Coplanar waveguide structures and design structures for radiofrequency and microwave integrated circuits. The coplanar waveguide structure includes a signal conductor and ground conductors generally coplanar with the signal conductor. The signal conductor is disposed between upper and lower arrays of substantially parallel shield conductors. Conductive bridges, which are electrically isolated from the signal conductor, are located laterally between the signal conductor and each of the ground conductors. Pairs of the conductive bridges connect one of the shield conductors in the first array with one of the shield conductors in the second array to define closed loops encircling the signal line.

10-08-2009

20090309675

Structure for a Through-Silicon-Via On-Chip Passive MMW Bandpass Filter - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a substrate including a silicon layer. Furthermore, the design structure includes a metal layer on a bottom side of the silicon layer and a dielectric layer on a top side of the silicon layer. Additionally, the design structure includes a top-side interconnect of the through-silicon via bandpass filter on a surface of the dielectric layer and a plurality of contacts in the dielectric layer in contact with the top-side interconnect. Further, the design structure includes a plurality of through-silicon vias through the substrate and in contact with the plurality of contacts, respectively, and the metal layer.

12-17-2009

20090311841

Method of Manufacturing a Through-Silicon-Via On-Chip Passive MMW Bandpass Filter - A method for forming a through-silicon via bandpass filter includes forming a substrate comprising a silicon layer and providing a metal layer on a bottom side of the silicon layer. Additionally, the method includes providing a dielectric layer on a top side of the silicon layer and forming a top-side interconnect of the through-silicon via bandpass filter on a surface of the dielectric layer. Further, the method includes forming a plurality of contacts in the dielectric layer in contact with the top-side interconnect and forming a plurality through-silicon vias through the substrate and in contact with the plurality of contacts, respectively, and the metal layer.

12-17-2009

20090315633

Design Structure, Structure and Method for Providing an On-Chip Variable Delay Transmission Line With Fixed Characteristic Impedance - A design structure, structure, and method for providing an on-chip variable delay transmission line with a fixed characteristic impedance. A method of manufacturing a transmission line structure includes forming a signal line of the transmission line structure, forming a first ground return structure that causes a first delay and a first characteristic impedance in the transmission line structure, and forming a second ground return structure that causes a second delay and a second characteristic impedance in the transmission line structure. The first delay is different from the second delay, and the first characteristic impedance is substantially the same as the second characteristic impedance.

12-24-2009

20090315641

Design Structure, Structure and Method for Providing an On-Chip Variable Delay Transmission Line With Fixed Characteristic Impedance - A design structure, structure, and method for providing an on-chip variable delay transmission line with a fixed characteristic impedance. A method of manufacturing a transmission line structure includes forming a signal line of the transmission line structure, forming a first ground return structure that causes a first delay and a first characteristic impedance in the transmission line structure, and forming a second ground return structure that causes a second delay and a second characteristic impedance in the transmission line structure. The first delay is different from the second delay, and the first characteristic impedance is substantially the same as the second characteristic impedance.

12-24-2009

20090316313

DESIGN STRUCTURE FOR AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE - A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge device comprises a substrate and multiple metal level layers disposed on the substrate. Each metal level comprises more than one electrode formed therein and more than one via connecting with some of the electrodes in adjacent metal levels. The device further includes a gap formed about one of the metal level layers, wherein the gap is hermetically sealed to provide electro-static discharge protection for the integrated circuit.

12-24-2009

20100032808

THROUGH WAFER VIA AND METHOD OF MAKING SAME - A through wafer via structure. The structure includes: a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to between greater than halfway to and all the way to the bottom surface of the substrate. Also methods for fabricating the though wafer via structure.

02-11-2010

20100032810

THROUGH WAFER VIAS AND METHOD OF MAKING SAME - A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.

02-11-2010

20100032811

THROUGH WAFER VIAS AND METHOD OF MAKING SAME - A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The structure includes, a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of the array of through wafer vias extending from the top surface of to the bottom surface of the substrate, the at least one electrically conductive via electrically isolated from the substrate.

02-11-2010

20100276809

T-CONNECTIONS, METHODOLOGY FOR DESIGNING T-CONNECTIONS, AND COMPACT MODELING OF T-CONNECTIONS - T-connections, methodology for designing T-connections, and compact modeling of T-connections. The T-connections include an electrically conductive T-junction comprising a body and first, second and third integral arms projecting from mutually perpendicular sides of the body, each arm of the three integral arms having a same first width abutting the body and a same length extending away from the body; an electrically conductive step-junction comprising a first section having the first width and an integral and abutting second section having a second width, the second width different from the first width, the first section smoothly abutting and integral with the first arm of the T-junction; and wherein top surfaces of the T-junction and the step-junction are coplanar.

11-04-2010

20110043299

Compact On-Chip Branchline Coupler Using Slow Wave Transmission Line - Branchline coupler structure using slow wave transmission line effect having both large inductance and large capacitance per unit length. The branchline coupler structure includes a plurality of quarter-wavelength transmission lines, at least one of which includes a high impedance arm and a low impedance arm. The high and low impedances are relative to each other. The high impedance arm includes a plurality of narrow cells and having an inductance of nL and a capacitance of C/n, and the low impedance arm includes a plurality of wide cells and having an inductance of L/n and capacitance of nC. The wide and narrow cells are relative to each other, and the wide and narrow cells are adjacent each other to form a signal layer having step discontinuous alternative widths.

02-24-2011

20110049676

METHOD, STRUCTURE, AND DESIGN STRUCTURE FOR A THROUGH-SILICON-VIA WILKINSON POWER DIVIDER - A method, structure, and design structure for a through-silicon-via Wilkinson power divider. A method includes: forming an input on a first side of a substrate; forming a first leg comprising a first through-silicon-via formed in the substrate, wherein the first leg electrically connects the input and a first output; forming a second leg comprising a second through-silicon-via formed in the substrate, wherein the second leg electrically connects the input and a second output, and forming a resistor electrically connected between the first output and the second output.

03-03-2011

20110073858

Test Structure for Determination of TSV Depth - A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel. A method of determining a depth of a through-silicon-via (TSV) in a semiconductor chip includes etching a first TSV into the semiconductor chip; forming a first channel, the first channel comprising the first TSV, a first contact electrically connected to the first TSV, and a second contact; connecting a current source to the second contact; determining a resistance across the first channel; and determining a depth of the first TSV based on the resistance of the first channel.

03-31-2011

20110132652

STRUCTURE OF VERY HIGH INSERTION LOSS OF THE SUBSTRATE NOISE DECOUPLING - A structure includes a substrate comprising a region having a circuit or device which is sensitive to electrical noise. Additionally, the structure includes a first isolation structure extending through an entire thickness of the substrate and surrounding the region and a second isolation structure extending through the entire thickness of the substrate and surrounding the region.

06-09-2011

20120104546

STRUCTURE AND DESIGN STRUCTURE FOR HIGH-Q VALUE INDUCTOR AND METHOD OF MANUFACTURING THE SAME - Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical.

05-03-2012

20120131776

DESIGN STRUCTURE, STRUCTURE AND METHOD FOR PROVIDING AN ON-CHIP VARIABLE DELAY TRANSMISSION LINE WITH FIXED CHARACTERISTIC IMPEDANCE - A design structure, structure, and method for providing an on-chip variable delay transmission line with a fixed characteristic impedance. A method of manufacturing a transmission line structure includes forming a signal line of the transmission line structure, forming a first ground return structure that causes a first delay and a first characteristic impedance in the transmission line structure, and forming a second ground return structure that causes a second delay and a second characteristic impedance in the transmission line structure. The first delay is different from the second delay, and the first characteristic impedance is substantially the same as the second characteristic impedance.

05-31-2012

20120175612

TEST STRUCTURE FOR DETERMINATION OF TSV DEPTH - A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel.

07-12-2012

20120194302

STRUCTURE, STRUCTURE AND METHOD FOR PROVIDING AN ON-CHIP VARIABLE DELAY TRANSMISSION LINE WITH FIXED CHARACTERISTIC IMPEDANCE - A design structure, structure, and method for providing an on-chip variable delay transmission line with a fixed characteristic impedance. A method of manufacturing a transmission line structure includes forming a signal line of the transmission line structure, forming a first ground return structure that causes a first delay and a first characteristic impedance in the transmission line structure, and forming a second ground return structure that causes a second delay and a second characteristic impedance in the transmission line structure. The first delay is different from the second delay, and the first characteristic impedance is substantially the same as the second characteristic impedance.

08-02-2012

20120212303

METHOD, STRUCTURE, AND DESIGN STRUCTURE FOR A THROUGH-SILICON-VIA WILKINSON POWER DIVIDER - A method, structure, and design structure for a through-silicon-via Wilkinson power divider. A method includes: forming an input on a first side of a substrate; forming a first leg comprising a first through-silicon-via formed in the substrate, wherein the first leg electrically connects the input and a first output; forming a second leg comprising a second through-silicon-via formed in the substrate, wherein the second leg electrically connects the input and a second output, and forming a resistor electrically connected between the first output and the second output.

08-23-2012

20120267794

STRUCTURE AND DESIGN STRUCTURE FOR HIGH-Q VALUE INDUCTOR AND METHOD OF MANUFACTURING THE SAME - Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical.

10-25-2012

20120329219

THROUGH WAFER VIAS AND METHOD OF MAKING SAME - A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The method of forming through wafer vias includes forming an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via through a semiconductor substrate having a top surface and an opposite bottom surface, each through wafer via of the array of through wafer vias extending from the top surface of the substrate to the bottom surface of the substrate.

12-27-2012

20130134566

STRUCTURE OF VERY HIGH INSERTION LOSS OF THE SUBSTRATE NOISE DECOUPLING - A structure includes a substrate comprising a region having a circuit or device which is sensitive to electrical noise. Additionally, the structure includes a first isolation structure extending through an entire thickness of the substrate and surrounding the region and a second isolation structure extending through the entire thickness of the substrate and surrounding the region.

05-30-2013

20130159957

METHOD, STRUCTURE, AND DESIGN STRUCTURE FOR A THROUGH-SILICON-VIA WILKINSON POWER DIVIDER - A method, structure, and design structure for a through-silicon-via Wilkinson power divider. A method includes: forming an input on a first side of a substrate; forming a first leg comprising a first through-silicon-via formed in the substrate, wherein the first leg electrically connects the input and a first output; forming a second leg comprising a second through-silicon-via formed in the substrate, wherein the second leg electrically connects the input and a second output, and forming a resistor electrically connected between the first output and the second output.

06-20-2013

20130189827

THROUGH WAFER VIAS AND METHOD OF MAKING SAME - A method of forming and structure for through wafer vias and signal transmission lines formed of through wafer vias. The structure includes, a semiconductor substrate having a top surface and an opposite bottom surface; and an array of through wafer vias comprising at least one electrically conductive through wafer via and at least one electrically non-conductive through wafer via, each through wafer via of the array of through wafer vias extending from the top surface of to the bottom surface of the substrate, the at least one electrically conductive via electrically isolated from the substrate.