ARM tacks on switch to boost on-chip bus bandwidth

ARM has developed an addon to its current AMBA hardware bus (AHB) specification that lets chip designers multiply the total bandwidth available in a system without changing the bus interface on existing intellectual property (IP) cores.

To boost overall bandwidth, the company has made it possible to interpose a switch matrix between AHB 2.0 masters and slaves that, in effect, puts multiple buses between them.

At the same time, the company has developed a cut-down version of the AHB interface that master cores can use if they do not need to support the full range of transactions.

Jonathan Morris, Micropack product manager for ARM, said: "The way we are packaging this is as an appendix to the AMBA [hardware bus] 2.0 specification. AHB is still central to our interconnect strategy."

ARM is calling the switch matrix-enhanced version of the bus "multilayer AHB" and the slimmed-down version "AHB-Lite". Typically, the company expects AHB-Lite to be used where support for arbitration between multiple masters is not needed.

Both standard and AHB-Lite cores can plug into the switch matrix as bus masters. Standard slaves are also compatible with the matrix. The bus arbiter sits in the matrix and controls the way in which ports are switched to and from masters and slaves.

Designers have control over how often the arbiter switches the matrix to create virtual buses between each master and its target.

Bruce Mathewson, AMBA technical lead at ARM, said: "We would expect people to switch on a burst basis but you can switch on each bus transaction efficiently. It is easier to verify if you switch on each transaction."

Mathewson said multilayer AHB helped avoid the need to work with complex split transactions, where the initial request is a separate bus action from the transfer that returns the required data.

"The aim of the split transaction is to free up bus bandwidth. On multilayer AHB, because you have multiple paths, the need to keep bandwidth free becomes less of an issue. It is easier to use wait states [between a request and the returned data]," said Mathewson.

He added that designers can choose how many switched buses the central matrix supports.

"You don't need to have a full interconnect matrix. You can have a tradeoff between complexity and potential bandwidth."

Morris said cores do not have to connect directly to the switch matrix. A master may have several slaves on a local bus with a further set, accessible by other masters, on the other side of the matrix. It is also possible to have multiple masters sharing a port on the matrix.

He said the company is working with customers in the networking world but other application areas have helped drive the multilayer additions to the AHB specifications.

"Automotive customers helped pull it through, because latency is a big issue there," said Morris.

The next version of the Micropack product, due in April, will support the multilayer AHB as a parameterisable soft core.

"Some of our partners have a beta of this. It is a parameterisable product where they put in the number of masters and slaves and the implementation code will be generated for them," said Morris.

Also in Micropack is a wrapper that gives a core that supports the AHB-Lite specification the extra functions needed to turn it into a full AHB master.