we build up the reference designs for two fpga systems: First redpitaya and a second combination of zynq zc702, ad9739a and ad9467. We also implemented the communication with matlab via libiio for zc702. The communication project(modulation, demodulation) therefor is realized by Simulink.
Now we want to transfer the model to redpitaya and want to program the whole project with vhdl/verilog. So it should completly run on hardware in real-time. It seems that this can be done by a manipulation of the blockdesign.
So we would like to see a similar project, with creation of a new IP block. You shared some projects for redpitaya with instructions on how to build the .bit bitstream. Is it possible to get an example-project (project file) to gain insight how and where to implement own IP-cores. We need especially the look inside your vivado project, to understand the realtions and to realize our own project.

i deal again with this project and checked your links. So i build up the master branch for every four projects (classic, logic, logic_orig, tft). Now i would like to find the user I/O interface to generate an output signal via HDL code by Matlab HDL Coder. So i tried to model an tranceiver and receiver in Simulink and generated the HDL code. But i don't see the connection in red_pitaya_top.sv to connect to DAC ADC ports. Can you help? Can you explain how to insert data to ASG or directly to DAC? I think there must be a 14bit register, which has to be connected to.

In the "classic" project's red_pitaya_top.sv, the "adc_dat" bus carries the incoming samples. The busses "asg_dat" and "pid_dat" are added together and are then converted to produce the DAC sample stream.

You can just connect the adc_dat bus to your module to receive incoming samples. To connect your output to the DAC, I'd recommend to define a new bus like

thanks for that fast response! I insert the new custom_dat bus and the lines for sumation. The matlab code and the hierarchy of inserted code you can see in the appendix. As you can see i connected the matlab-output and the custom_dat bus as the following:

Your ways of instantiating the module did not work. In the "Project Manager Hierarchy", you can see that Sin is not a subnode of red_pitaya_top. This means it will not be included in the generated logic.
In your Sin.txt you put the assignment to the custom_dat bus inside the module, where the bus is not known.

You probably had a number of error messages during synthesis for both of your approaches. You should pay attention to those.

To use a new submodule, you need to do two things:
1. add the source to the project setup, so that it shows up in the project manager
2. instantiate the module somewhere in the hierarchy so that it is downstream of "top"

Your instantiation in red_pitaya_top is correct, I assume the error of trying to use the custom_dat bus inside the module led to the failure.