FPGA Consultant to work closely with the ASIC team. Client wanted to test certain aspects of their design in an Altera Quartus II design, but lacked an understanding of Timing issues in the FPGA. We performed a design review and made appropriate timing changes in less than one month.

Team of ASIC Verification engineers to perform both block and full-chip level functional verification of a NAND Flash Memory USB Stick device using SystemVerilog OVM.

Four (4) Engineers provided to client for Xilinx VirtexV FPGA Verifcation for large network storage chip with high-speed I/O’s such as PCI Express, DDR2/3 memory controllers, using Verilog, SystemVerilog, AVM (Questa) and C.