Hi DrNick,
can you tell me for what reason you want to use that barrel shifter???
and can you give us more details about what you want to do? at least block diagram or why not your planned circuit diagrams, can you?

I think that the barrel shifter actually won't work. What I want to do is be able to buffer audio through the system until a logic signal is set high. Once this signal is set high I want to replay the last few seconds of audio that have been buffered through the system. I am thinking of using a couple of other ADC channels to have voltage controlled sampling rates. If I used a barrel shifter I would need ALOT of bytes in order to store even a second of audio (if it is sampled at a few kHz). I will put together a block diagram later today so you can get a better picture of what I am trying to accomplish.

but can I ask you something, why don't you use FPGA instead of CPLD? wouldn't that be more better? or do you have other reasons for that? But still didn't understand the whole process of your circuit, can you just give me a detailed description for the whole process, I mean how is it working?