View/ Open

Date

Author

Metadata

Abstract

Rapid thermal annealing (RTA) is a low thermal budget high throughput method of crystallizing hydrogenated amorphous (a-Si:H) silicon films. This thesis had three principal goals: 1) to fabricate heterojunction solar cells by PECVD deposition of n-type a-Si:H without using an intrinsic a-Si:H buffer layer, 2) to use low thermal budget RTA to form highly crystalline emitters with sufficient lateral conductivity to eliminate the transparent conducting oxide, and 3) to investigate alternative heterojunction interface passivation layers such as silicon nitride which are suitable for high temperature processing. Thin a-Si:H films deposited on silicon wafer substrates were annealed by RTA at temperatures from 500oC to 1000oC. The crystalline emitter layers were characterized by transmission electron microscopy, Raman, UV-reflectance, ellipsometry, and scanning electron microscopy. Electrical characterization was performed by Hall Effect and temperature dependent current-voltage measurements. The RTA crystallization process was epitaxial, but the resulting films had a large enough defect density that their UV-reflectance and ellipsometry dielectric function curves were very similar to those of nanocrystalline silicon. However, as the RTA temperature was increased the quality of the epitaxial films greatly improved approaching that of bulk crystalline silicon. Preliminary simulations were performed approximating the epitaxial films as nanocrystalline material, and comparison was made with defect-free epitaxial and a-Si:H /c-Si heterojunction cells. Basic solar cells were fabricated on polished silicon wafers. Cells were analyzed by dark current-voltage, external and internal quantum efficiency, solar simulator, and spreading resistance profiling. Phosphorous diffusion at RTA temperatures above 750oC reduced cell photocurrent. A cell efficiency of 15.1 % on a 1 cm2 sample was achieved for RTA at 750oC for 5 minutes. The principal factor limiting the open-circuit voltage of the cells was recombination in the quasi-neutral region of the silicon wafer. Experimental results showed that the recombination velocity at the heterojunction interface was low (between 10 cm/s to 100 cm/s). Advanced simulations focused on quantifying the defect density at the heterojunction interface by capacitance spectroscopy and electroluminescence. Advanced cell architectures were also studied, and several additional processing steps were implemented. Wafers were thinned to reduce recombination losses in the absorber, and pyramid textured to decrease reflectance. A thin passivating layer of silicon nitride was introduced between the emitter and the substrate. A nanocrystalline p+ layer was deposited on the back side to reduce back surface recombination. Although the wide band gap of silicon nitride appeared to hinder charge carrier transport, a preliminary cell efficiency of 11.5% was achieved at an annealing time of 20 minutes at 1000oC.