TSMC taps ARM's V8 on road to 16 nm FinFET

SAN JOSE, Calif. – TSMC laid out roadmaps for 20-nm planar, 16-nm FinFET and 2.5-D stacks at its annual event here on Tuesday (Oct. 16). The Taiwan foundry will use ARM’s first 64-bit processor, the V8, as a test vehicle for the 16-nm FinFET process with the first tape out of a test chip probably within the next year.

The advent of double patterning at 20 nm and FinFETs at 16 nm pose significant challenges to chip designers, based on talks with TSMC and partner companies. TSMC’s roadmap is roughly in line with rival Globalfoundries that also hopes to make 20nm chips next year and 14-nm FinFET chips in 2014.

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TSMC aims to start early or "risk" production of 16 nm FinFETS in Nov. 2013.

One analog IP provider said his first 20 nm designs resulted in bigger blocks, disappointing customers. The company had to completely redesign IP such as USB blocks—a job that took a year--to deal with double patterning and get 25 to 30 percent area reductions.

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The USB redesign also was required because the 20-nm process only supports 1.8V transistors. USB requires legacy support for 5V and 3.3V operations.

Top EDA executives said it’s too early to tell how similar or different TSMC’s 16-nm FinFETs will be compared to those of competitors such as GlobalFoundries. Foundries are just now issuing their first early versions of design rule manuals for their FinFET processes, although some early test structures have been taped out.

TSMC’s 16-nm FinFET process will be substantially similar to its 20-nm high-K metal gate SoC process in the back-end, said Cliff Hou, vice president of R&D at TSMC, in a conversation with EE Times after his talk here. Other companies are expected to take a similar approach of marrying 14- and 16-nm FinFET structures with their back-end 20- and 22-nm processes.

By grafting 14- and 16-nm FinFET structures on a 20- and 22-nm back-end process, foundries can avoid at least for one node the need for complex and costly triple or quadruple patterning lithography.

Cadence is expected to treat FinFETs as transistors, automating the way they are generated in custom design flows in ways suitable for the target foundry. Despite that offering, some designers—especially those working with analog and mixed/signal blocks like USB, expect they will have to redesign their cores for FinFETs.

TSMC aims to have chip design kits for its 16-nm process available in January with the first foundation IP blocks such as standard cells and SRAM blocks ready a month later. It will start limited so-called “risk” production of the 16-nm process in November 2013. Production chip tape outs will follow about four or five quarters later.

The FinFET process will have the same leakage power characteristics as the 20-nm process on which it is based. But it will offer a performance boost up to 35 percent and total power consumption reductions up to 35 percent compared to 20 nm, said Hou.

Intel has used double-exposure techniques for its alternating PSM patterning for the poly gate layer starting at 65 nm. Probably multi-patterning on a few layers should be nothing to them now. The question is if they can handle additional layers such as metal 2/3 requiring double patterning.

Double patterning does add a significant amount of complexity to the entire process. And those companies that can do it well will be rewarded. This is where the more vertically integrated companies like Intel and Samsung have an advantage since they can control everything in house. I'm amazed that the foundries like TSMC can execute as well as they do now. But integrating FinFETs, etc. will only make it even more complex to manage in the future. Getting first pass success will become more difficult, and the number of designs at the leading edge will become fewer. Both of these trends are being acclerated by the requirements (costs) of double patterning.

Rick :
Couple questions about the TSMC 2.5-D Test vehicle you have reported. What was the footprint of the whole thing ( with 4 chips ). Did they give any reason why such a 2.5-D module will be better than current modules / packages used in Smart Phones / Tablets ?
Thx

Rick :
Couple questions about the TSMC 2.5-D Test vehicle you have reported. What was the footprint of the whole thing ( with 4 chips ). Did they give any reason why such a 2.5-D module will be any better than current modules / packages used in Smart Phones / Tablets ?
Thx

Worse yet, at least some expect 10 nm may require double patterning even for EUV.
http://semimd.com/blog/2012/09/17/will-euv-miss-another-node/
And still worse yet, the EUV throughput is still far short of target, so ASML has acquired Cymer. Apparently, they've scuttled their other EUV source vendor options.
http://semimd.com/blog/2012/10/17/asml-to-acquire-cymer/

They did not give size of the chip. But Hou did say the test run with Wide IO was only to test out the various aspects of the process and the Wide IO IP which would actually be used with a through silicon via stack in commercial chips.