TLM basically models memory reads / writes and most of the TLM models
achieve a compromise between performance and accuracy without
considering how block transfers are broken down into word reads & writes

on a bus, so there's no standardization for this level of precision. As
an example we deliver transactors that interface / convert TLM to RTL
buses like AXI & OCP that support burst mode transfers. The transactors
are fully protocol compliant at the cycle-level but the TLM still
operates with a byte array & length payload.

The disadvantage of modeling the individual transfers in TLM is, of
course, performance. Taken to extremes the TLM models are going to
replication what the RTL does to get the accuracy at the word transfer
level (almost cycle-accurate in most cases) but then you lose the
performance advantage from using TLM so why not stick with the RTL and
avoid the cost of creating the second set of models?

Perhaps we can help you better if you can explain your goals in modeling