Server Chips Spotlighted at Hot Chips

This week, vendors including IBM, Fujitsu, and Oracle offered a look at the chips that drive their big-iron workloads.

At the Hot Chips conference, which ran Aug. 27-29 in Cupertino, Calif., IBM discussed its Power 7+ architecture as well as the z12, the chip that debuted inside the new IBM zEnterprise mainframe that debuted this week. Fujitsu and Oracle, for their part, presented their own spins on the rival SPARC architecture.

One of the more ambitious approaches to chip architecture was the AMCC X-Gene, an attempt to push ARM into at least a small portion of the data center. Other vendors took a more traditional approach, largely sacrificing power for raw performance.

(We’ve purposely excluded the Intel Xeon E5 family, only because the family, code-named “Romley,” was formally launched in March and is therefore well-known.)

IBM Power 7+

IBM’s POWER architecture, typically used for ERP, OLTP, and Java, added three major improvements: an enormous 80 Mbyte on-chip shared level-3 cache, support for new accelerator functions, and an ultra-low-power mode for when the chip is not in use.

IBM didn’t disclose the projected clock speed of the Power 7+ architecture, but it did claim a 25 percent frequency increase by moving to 32 nm technology. It also claimed substantial performance improvements over the previous Power7 chip: about 1.7 times OLTP performance of Power 7 using a Power 7+ single-chip module implementation and about 2X using a Power 7+ dual-chip module. ERP performance will be slightly less, or between 1.25 and 1.5 times that of the Power 7. Each module contains 8 cores. The chip weighs in at 567 square millimeters, with 2.1 billion transistors.

Specific accelerator functions will also help the chip perform specialized tasks. The accelerators include asymmetric math functions like RSA cryptography, AES/SHA acceleration, and a true hardware random number generator.

Finally, there’s the new “winkle” low-power mode, which saves 95 percent power with less than 10 ms latency, according to IBM, and powers off the chiplet (the core, level-2 cache, and part of the L3 cache). However, it requires a re-initialization to wake up. (The name is an abbreviated version of “Rip van Winkle,” known for his sleeping habits.)

IBM zNext

The heart of the zEnterprise mainframe is what IBM executives originally dubbed the zNext chip, before calling it the z12. Its most eye-catching specification, as with previous generations, has been its speed: 5.5 GHz. Running on 32-nm SOI, it includes 2.75 billion transistors. New features include 6 new cores (versus 4 on the previous z196), core-dedicated co-processors, and twice the amount of on-chip, shared L3 cache, or 48 Mbytes.

The z12 will be the first general-purpose processor to support transactional memory. Additional improvements include improved out-of-order operations and a streamlined pipeline, as well as improvements in the cache subsystem.

Fujitsu SPARC64 X

While IBM and HP sit at the top of the server world, both Oracle and Fujitsu sit at the bottom of the top five. Both have invested in the SPARC processor architecture, developed by Sun Microsystems and licensed to Fujitsu, which pledged in its presentation to keep supporting the SPARC architecture. Sun, of course, is now part of Oracle.

The SPARC64 X is a 3-GHz, 16-core (2 threads-per-core) chip running on 28-nm CMOS. At peak performance, it puts out 382 GFLOPS or 288 GIPS. Fujitsu executives claimed that the chip was up and running in the lab, and would be used within Fujitsu’s next-generation UNIX server. The processor boasts a deeper pipeline to increase the frequency, but also integrates the memory controller, the CPU-to-CPU interface, and the I/O controller to reduce cost.

Oracle SPARC T5

As you might expect, database acceleration is the modus operandi of the former Sun team at Oracle; Sebastian Turullois, a hardware director in the microelectronics division at Oracle, claimed that the T5 would be the fastest, most optimized processor for driving Oracle databases.

The T5 combines 16 cores running at 3.6 GHz on a 28-nm manufacturing process. Continuing the trend of hardware acceleration of specific functions, Sun executives claimed the chip would lead in on-chip encryption acceleration, with support for asymmetric (public key) encryption, symmetric encryption, hashing up to SHA-512, and with a hardware random number generator.

The T5 achieves power management with dynamic voltage and frequency scaling, with thermal diodes on each chip, carefully monitoring the power. If the chip’s thermal budget allows it, the frequency will be dynamically increased, or lowered if it exceeds the high-water mark.

Author

Mark Hachman is a freelance editor at Slashdot Media. Previously, he served as the West Coast news editor for PC Magazine/PCMag.com, where he covered components, new technology, and the larger Web 2.0 companies such as Facebook and Google. Before that, he worked for eWEEK, TechWeb, and ExtremeTech, which he helped launch.