This article is part 2 in a series about various
microcontroller communication interfaces. In part 1 of the series, I discussed
some typical applications and implementations of the SPI, Microwire and I2C
interfaces. I looked at their general differences, basic features, advantages
and disadvantages. In this part, I'll cover the specifics of their protocol
formats. In Part 3 we will start to take a closer look at asynchronous
interfaces (UART based RS232C/RS485/LIN, CAN, USB and Ethernet).

I2C Bus

I2C is a 2-wire, half-duplex, serial bus,
as shown in Figure 1. The two I2C signals are serial clock (SCL) and
serial data (SDA). Both lines are bidirectional and must be connected to Vcc via
pull-up resistors.

The SCL and SDA pins need to be implemented as an open drain or open collector
type to allow for a wired AND function on the bus ( "0" wins over "1") .

The device initiating data
transfers and providing the clock signal on the bus is called a "master". A
device being addressed by the master is called a "slave".

The addressed I2C
slave can slow down or stop the master by keeping the SCL line pulled low (clock
stretching) until it is ready to continue. This way a slow slave device can
still keep up with a fast master.

I2C supports
multiple masters on the bus through its built in bus arbitration. In case of
multiple masters trying to send data at the same time, priority is given to the
master that first sends a "0" bit.

I2C Communication Protocol

Data can be transferred at rates up to 100kbps in Standard mode, up to
400kbps in Fast mode and up to 3.4Mbps in High-Speed mode (finding peripherals
that are that fast though is a challenge). In Standard mode 7-bit addressing is
used. In the other modes, slaves can either have 7- or 10-bit addresses. The
total capacitive bus load of all devices connected to the bus can not exceed
400pF.

Figure 2 shows the I2C
Communication Protocol. The data transmission format is most significant bit (MSB)
first. I2C is level sensitive; therefore SDA must be stable while SCL
is high. The SDA line can only change when SCL is low, with two exceptions:

Start Condition: The
master signals the beginning of a transfer by sending a 1-to-0 transition
while SCL is high.

Stop Condition: A
0-to-1 transition issued by the master while SCL is high, signals the end of a
transfer.

The start condition is followed by
8-bits of data with the first 7 bits being the unique slave address in standard
mode. 10-bit addressing is indicated by transmitting the bit pattern 11110
followed by address bits A9 and A8. The 7-bit address field is followed by the
read/not-write (R - /W) bit, which tells the slave whether to receive (0) or
transmit (1) data.

This pattern of 8-data bits and 1
acknowledge bit is repeated if more bytes need to be transmitted. The device
that is receiving data asserts the acknowledge signal. In case of the master
transmitting, it monitors the slave's acknowledge after the last byte to be
transmitted and then issues the stop condition. In case of the slave
transmitting, the master acknowledges all bytes but the last one received, to
indicate to the slave that transmission is to be stopped. The master then issues
the stop condition.

SPI and Microwire

Both SPI and Microwire are
full-duplex, (3+n)-wire serial busses. (n= # of slaves). In single master,
multiple slave configurations, as shown in Figure 3, each slave device requires
a dedicated Slave Select (SS)
signal, which is created by the master using standard I/O pins.

A Microwire multiple slave
configuration looks similar, with the difference that the master's SO pin is
connected to the slaves' SI pins and the slaves' SO pins are connected to the
master's SI pin.

SPI Signals

Microwire Signals

SCLK- Serial Shift Clock

SK – Serial Shift Clock

MOSI - Master Out Slave In

SO – Serial Out (both master &
slave)

MISO – Master In Slave Out

SI – Serial In (both master &
slave)

/SS – Slave Select

/CS – Chip Select

Most SPI interfaces have two
configuration bits, called clock polarity (CPOL) and clock phase (CPHA). CPOL
determines whether the shift clock's idle state is low (CPOL=0) or high (CPOL=1).
CPHA determines on which clock edges data is shifted in and out (CPHA=0 MOSI
data is shifted out on falling edge, MISO data is shifted in on rising edge). As
each bit has two states, this allows for four different combinations, all of
which are incompatible with each other. For two SPI devices to talk to each
other, they need to be set to use the same clock polarity and phase settings.

Why would you want 4 different
settings? Two of the four settings allow the SPI interface to talk to different
flavors of Microwire devices and vice versa.

Figure 4 shows the original
Microwire protocol (which is older than SPI) that has fixed clock polarity and
clock phase: SI is latched (data shifted in) on the rising edge of the SK clock
and SO changes (data shifted out) on the falling edge. SK is always low if no
data is transmitted.

Many early SPI devices implemented
only SPI mode 0 that does the opposite of Microwire, namely shift data out on
the rising edge and in on the falling. Therefore Microwire/Plus was created that
allows selecting an alternate shift clock via the SKSEL (shift clock select)
bit. Nowadays Microwire/Plus with alternate shift clock is compatible to SPI
mode 0 and Microwire with standard shift clock is compatible with SPI mode 1.

Both Microwire and SPI do not
explicitly define any maximum data rates. Different peripherals on the market
each have their own maximum speed limit - most of them in the several Mbit
range. There is no means of slaves to slow the master down and also no
acknowledgement on received data, like with I2C. To accommodate a wide range of
SPI/Microwire speeds, microcontrollers usually feature a programmable shift
clock divider.

Conclusions

SPI's and Microwire's full
duplex capability and fast data rates make those interfaces very efficient and
simple for single master - single slave applications. In practical applications,
the requirement for dedicated slave select signals severely limits the number of
slave devices that can be connected to a microcontroller. Multi-master systems
significantly increase complexity and are very rarely used with those two
interfaces.

I2C's lower speed and more
complex protocol put it at a disadvantage in single master-single slave
applications. Its weakness turns into strength if a larger number of slave
devices needs to be connected or a multi-master system is needed.

All three interfaces have
the advantage of being tolerant to large oscillator variations, as all data
transfers are synchronized to the master's shift clock. As synchronous
interfaces they are, however, limited to bridging short distances on a single
PCB or between PCBs within a smaller system. When it comes to bridging larger
distances or connecting external devices, asynchronous interfaces play a
dominant role and we will start looking at some of them in part 3 of this
series.