The GPIOs used for each UART interface can be chosen from any GPIO on the device and are
independently configurable. This enables great flexibility in device pinout and efficient use of
board space and signal routing.

Shared resources

The UARTE shares registers and other resources with other peripherals that have the same
ID as the UARTE.

Therefore, you must disable all peripherals that have the same ID as the UARTE before the UARTE
can be configured and used. Disabling a peripheral that has the same ID as the UARTE will not
reset any of the registers that are shared with the UARTE. It is therefore important to configure
all relevant UARTE registers explicitly to ensure that it operates correctly.

See the Instantiation table in Instantiation for details
on peripherals and their IDs.

EasyDMA

The UARTE implements EasyDMA for reading and writing to and from the RAM.

If the TXD.PTR and the RXD.PTR are not pointing to the Data RAM region, an EasyDMA transfer may
result in a HardFault or RAM corruption. See Memory for
more information about the different memory regions.

The .PTR and .MAXCNT registers are double-buffered. They can be updated and prepared for the
next RX/TX transmission immediately after having received the RXSTARTED/TXSTARTED event.

The ENDRX/ENDTX event indicates that EasyDMA has finished accessing respectively the RX/TX
buffer in RAM.

Transmission

The first step of a DMA transmission is storing bytes in the transmit buffer and
configuring EasyDMA. This is achieved by writing the initial address pointer to TXD.PTR, and the
number of bytes in the RAM buffer to TXD.MAXCNT. The UARTE transmission is started by triggering
the STARTTX task.

After each byte has been sent over the TXD line, a TXDRDY event will be generated.

When all bytes in the TXD buffer, as specified in the TXD.MAXCNT register, have been
transmitted, the UARTE transmission will end automatically and an ENDTX event will be generated.

A UARTE transmission sequence is stopped by triggering the STOPTX task, a TXSTOPPED event will
be generated when the UARTE transmitter has stopped.

If the ENDTX event has not already been generated when the UARTE transmitter has come to a
stop, the UARTE will generate the ENDTX event explicitly even though all bytes in the TXD buffer,
as specified in the TXD.MAXCNT register, have not been transmitted.

If flow control is enabled through the HWFC field in the CONFIG register, a transmission will be automatically suspended when CTS is
deactivated and resumed when CTS is activated again, as illustrated in Figure 2. A byte that is in transmission when CTS is
deactivated will be fully transmitted before the transmission is suspended.

Figure 2. UARTE transmission

The UARTE transmitter will be in its lowest activity level, and consume the least amount of
energy, when it is stopped, i.e. before it is started via STARTTX or after it has been stopped
via STOPTX and the TXSTOPPED event has been generated. See POWER — Power supply for more information about power modes.

Reception

The UARTE receiver is started by triggering the STARTRX task. The UARTE receiver is
using EasyDMA to store incoming data in an RX buffer in RAM.

The RX buffer is located at the address specified in the RXD.PTR register. The RXD.PTR register
is double-buffered and it can be updated and prepared for the next STARTRX task immediately after
the RXSTARTED event is generated. The size of the RX buffer is specified in the RXD.MAXCNT
register and the UARTE will generate an ENDRX event when it has filled up the RX buffer, see
Figure 3.

For each byte received over the RXD line, an RXDRDY event will be generated. This event is likely to occur before the corresponding data has been transferred to Data RAM.

The RXD.AMOUNT register can be queried following an ENDRX event to see how many new bytes have
been transferred to the RX buffer in RAM since the previous ENDRX event.

Figure 3. UARTE reception

The UARTE receiver is stopped by triggering the STOPRX task. An RXTO event is generated when
the UARTE has stopped. The UARTE will make sure that an impending ENDRX event will be generated
before the RXTO event is generated. This means that the UARTE will guarantee that no ENDRX event
will be generated after RXTO, unless the UARTE is restarted or a FLUSHRX command is issued after
the RXTO event is generated.

Important: If the ENDRX event has not already been generated when the UARTE receiver
has come to a stop, which implies that all pending content in the RX FIFO has been moved to the
RX buffer, the UARTE will generate the ENDRX event explicitly even though the RX buffer is not
full. In this scenario the ENDRX event will be generated before the RXTO event is generated.

To be able to know how many bytes have actually been received into the RX buffer, the CPU can
read the RXD.AMOUNT register following the ENDRX event or the RXTO event.

The UARTE is able to receive up to four bytes after the STOPRX task has been triggered as long
as these are sent in succession immediately after the RTS signal is deactivated. This is possible
because after the RTS is deactivated the UARTE is able to receive bytes for an extended period
equal to the time it takes to send 4 bytes on the configured baud rate.

After the RXTO event is generated the internal RX FIFO may still contain data, and to move this
data to RAM the FLUSHRX task must be triggered. To make sure that this data does not overwrite
data in the RX buffer, the RX buffer should be emptied or the RXD.PTR should be updated before
the FLUSHRX task is triggered. To make sure that all data in the RX FIFO is moved to the RX
buffer, the RXD.MAXCNT register must be set to RXD.MAXCNT > 4, see Figure 4. The UARTE will generate the ENDRX event
after completing the FLUSHRX task even if the RX FIFO was empty or if the RX buffer does not get
filled up. To be able to know how many bytes have actually been received into the RX buffer in
this case, the CPU can read the RXD.AMOUNT register following the ENDRX event.

Figure 4. UARTE reception with forced stop via STOPRX

If HW flow control is enabled through the HWFC field in the CONFIG register, the RTS signal will be deactivated when the receiver is stopped
via the STOPRX task or when the UARTE is only able to receive four more bytes in its internal RX
FIFO.

With flow control disabled, the UARTE will function in the same way as when the flow control is
enabled except that the RTS line will not be used. This means that no signal will be generated
when the UARTE has reached the point where it is only able to receive four more bytes in its
internal RX FIFO. Data received when the internal RX FIFO is filled up, will be lost.

The UARTE receiver will be in its lowest activity level, and consume the least amount of
energy, when it is stopped, i.e. before it is started via STARTRX or after it has been stopped
via STOPRX and the RXTO event has been generated. See POWER — Power supply for more information about power modes.

Error conditions

An ERROR event, in the form of a framing error, will be generated if a valid stop bit is
not detected in a frame. Another ERROR event, in the form of a break condition, will be generated
if the RXD line is held active low for longer than the length of a data frame. Effectively, a
framing error is always generated before a break condition occurs.

An ERROR event will not stop reception. If the error was a parity error, the received byte will
still be transferred into Data RAM, and so will following incoming bytes. If there was a framing
error (wrong stop bit), that specific byte will NOT be stored into Data RAM, but following
incoming bytes will.

Using the UARTE without flow control

If flow control is not enabled, the interface will behave as if the CTS and RTS lines
are kept active all the time.

Parity and stop bit configuration

When parity is enabled through the PARITY field in the CONFIG register, the parity will be generated automatically from the even parity
of TXD and RXD for transmission and reception respectively.

The amount of stop bits can be configured through the STOP field in the CONFIG register.

Low power

When putting the system in low power and the peripheral is not needed, lowest possible power consumption is
achieved by stopping, and then disabling the peripheral.

The STOPTX and STOPRX tasks may not be always needed (the peripheral might already be stopped), but if STOPTX and/or
STOPRX is sent, software shall wait until the TXSTOPPED and/or RXTO event is received in response, before disabling
the peripheral through the ENABLE register.

Pin configuration

The different signals RXD, CTS (Clear To Send, active low), RTS (Request To Send, active
low), and TXD associated with the UARTE are mapped to physical pins according to the configuration
specified in the PSEL.RXD, PSEL.CTS, PSEL.RTS, and PSEL.TXD registers respectively.

The PSEL.RXD, PSEL.CTS, PSEL.RTS, and PSEL.TXD registers and their configurations are only used
as long as the UARTE is enabled, and retained only for the duration the device is in ON mode.
PSEL.RXD, PSEL.RTS, PSEL.RTS and PSEL.TXD must only be configured when the UARTE is disabled.

To secure correct signal levels on the pins by the UARTE when the system is in OFF mode, the
pins must be configured in the GPIO peripheral as described in Table 1.

Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so
may result in unpredictable behavior.

Table 1. GPIO configuration before enabling peripheral

UARTE signal

UARTE pin

Direction

Output value

RXD

As specified in PSEL.RXD

Input

Not applicable

CTS

As specified in PSEL.CTS

Input

Not applicable

RTS

As specified in PSEL.RTS

Output

1

TXD

As specified in PSEL.TXD

Output

1

Registers

Table 2.
Instances

Base address

Peripheral

Instance

Description

Configuration

0x40002000

UARTE

UARTE0

Universal asynchronous receiver/transmitter with EasyDMA, unit 0

0x40028000

UARTE

UARTE1

Universal asynchronous receiver/transmitter with EasyDMA, unit 1

Table 3.
Register Overview

Register

Offset

Description

TASKS_STARTRX

0x000

Start UART receiver

TASKS_STOPRX

0x004

Stop UART receiver

TASKS_STARTTX

0x008

Start UART transmitter

TASKS_STOPTX

0x00C

Stop UART transmitter

TASKS_FLUSHRX

0x02C

Flush RX FIFO into RX buffer

EVENTS_CTS

0x100

CTS is activated (set low). Clear To Send.

EVENTS_NCTS

0x104

CTS is deactivated (set high). Not Clear To Send.

EVENTS_RXDRDY

0x108

Data received in RXD (but potentially not yet transferred to Data RAM)