As discussed in class, overflow detection can be accomplished by comparing the sign of the addition inputs to the sign of the output. If the two inputs share the same sign and the output has a different sign, then overflow has occurred.

Further hint: Tie the carry input (C0) of the 4-bit adder to logic zero (or GND) lest you see a lot of unknown values in your output. Ignore the carry out bit (C4).

Test your circuit using a timing file for several different cases (at least 4), which clearly show examples of overflow and non-overflow. For each case explain what is happening in the circuit (i.e. “we are trying to add minus five to minus four and thus overflow because the circuit can only represent down to minus eight”).

I dont really understand what he wants me to do. Do I just build a circuit and the inputs are two 4 bit values and the adder adds the two binary numbers and somehow I detect to see if overflow occured?
I don't understand what the output to the circuit would be? If overflow occurs what will happen? And how do I even detect overflow in my circuit in the first place.

I'm sorry if this is too detailed to answer, but I'm really confused about this whole thing.
Thanks a lot!

I understand the concept of "overflow" but I dont understand how to actually implement it as a circuit. How do I make a circuit that understands how to compare the signs of the two inputs? That's where I'm getting stuck.

In order for overflow to occur the inputs must have the same signs or the last two carries are supposed to be the same. So in order to make this circuit I will need to compare the signs of the inputs since the adder I'm using ties all the internal carries together. Do I just look at the left most bit of the 4 digit value for both inputs and if they are equal then an overflow has occured?

wow, when you say sign do you mean "not vs true"? part numbers seem a little short can you post diagrams?
i am intrigued, and trying to learn something. i have never heard of (or don't recall) anything about 4 bit signed 2's compliment addition for overflow detection with the co (?) input tied to gnd. (is co the trigger?).
please provide the answers when taken up in class.
thanks don

wow, when you say sign do you mean "not vs true"? part numbers seem a little short can you post diagrams?
i am intrigued, and trying to learn something. i have never heard of (or don't recall) anything about 4 bit signed 2's compliment addition for overflow detection with the co (?) input tied to gnd. (is co the trigger?).
please provide the answers when taken up in class.
thanks don

that's the link for the pdf with the part diagrams. The full adder chip is listed on page 9 while the other ones start on page 7. I believe C0 is the initial carry input.

And by sign I mean postive(0) value for negative(1) value. If both inputs are negative or both are postive then there will be a overflow I believe. I'm just confused on how to make the circuit reflect this.

Basically the circuit shown on page 8 is exactly what I need to compare the sign bits, but I'm having trouble understanding how they did this exactly. Like what do the AND and OR gates accomplish and if the output of the overflow is a 0 what does the zero mean?