Benefit from the power of the latest SystemVerilog subset constructs – with confidence

Henderson, NV – August 8th, 2017 – Aldec, Inc., an industry leader in Electronic Design Verification, has expanded the rule-checking capabilities of its popular ALINT-PRO™ tool in response to the design subset constructs that have been recently added to the SystemVerilog language.

The use of the latest subset of SystemVerilog design constructs is not without risk, namely there are now new risks for RTL coding errors/defects to be made and go unobserved. The 2017.07 release of ALINT-PRO™ is able to flag typical issues including 2-valued vs 4-valued data, user-defined types, new kinds of processes and conditional statements, new expression operators, and advanced constructs to model re-usable design hierarchies.

“The need for rapid and informative feedback regarding potentially harmful RTL defects and inconsistencies, and the prevention of them creeping into the design flow, grows in proportion with language complexity,” observes Sergei Zaychenko, Aldec Software Product Manager. “At Aldec we’re committed to ensuring that design engineers can leverage the power of hardware description languages while verifying their designs perform as intended.”

ALINT-PRO™ is a design verification solution for RTL code written in VHDL, Verilog and SystemVerilog, which is focused on verifying coding style and naming conventions, RTL and post-synthesis simulation mismatches, smooth and optimal synthesis, avoiding problems on further design stages, clocks and reset tree issues, CDC, DFT, and coding for portability and reuse. The solution performs static analysis based on RTL and SDC™ source files uncovering critical design issues early in the design cycle, which in turn reduces design signoff time dramatically.