Some people on this forum might find this interesting, as there have been some discussions here about RISC-V, the open instruction set, and possible real (future) processors based on it.

So far there have only been micro-controller type cips that only run bare metal code (no OS). So SiFive have announced that they will be releasing a chip that can run Linux. But if I remember correctly, the Linux port isn't ready yet, but the developers are aiming at 4.15. GCC is already ported. Nevertheless, these chips are appreantly already available, even though they will firstly only be directed at companies that want to use them in products. They claim that a dev board for the general public will be out in 2018. I really wonder if the Raspberry pi foundation will go with this, especially since ARM was sold from their town to owners in was it Japan and I have understood that the new owners want to keep hiking up the license fees.

The lowRISC project claimed that they would come out with a board in 2017, but given that there has been no news from them, I am fairly sure they cannot get anything on the market before this SiFive board. SiFive are also producing their own microcontroller and the Arduino cinque processor, so they are have some real experience under their belt now. Still I think that the lowRISC community is interesting, particularly in that they aim to make a version that is entirely open (as the license allows for partially proprietary design).

This is almost bizarre but the Debian wiki is really up to date on this issue (gotta be a first):

Version 9 of the kernel upstreaming patchset has been posted to LKML on 2017-09-26. As planned after v8, it has been split into an architecture-core and a driver patchset. The RISC-V architecture maintainer has a kernel.org account now, which is a prerequisite for getting the patches into linux-next, but the actual inclusion into linux-next is still pending as the linux-next maintainer has announced that updating the linux-next tree will be on hold during the whole of October 2017.

So, in other words, a linux capable version of the processor is ready, whereas linux for the processor is not and apparently will not be for some time...

I don't have enough experience to say what core IP price should be, but they suggest on their site that it is less expensive than other competitors. But I believe there was a post on this forums where ARM licenses were said to start at 10 million USD... and ARM Holdings also asks for royalties on top!

Considering that their microcontroller board costs €59 and that their Field-programmable gate array board for this is 99, I'd guess that the linux dev board would be in the 50-150 USD price range... but we'll see.

RISC-V is growing massively as many large players like Seagate have started to use it and manucdacture it in the billions. Howver, as far as I know this is the only linux-capable full cpu that exists. That is, not a microcontroller type of thing or a FGPA dev board. linux 4.15 now also supports RISC-V straingt out of the box, although there are basically no kernel modules for peripherals

The SHAKTI project is building a family of 6 processors, based on the RISC-V ISA. We will also develop reference SoCs for each class of processors, which will serve as an exemplar for that family. While the primary focus of the team is architecture research, these SoCs will be competitive with commercial offerings in the market with respect to area, power and performance.

It looks like they are investigating the more powerful (multi-core, high TDP) implementations of the RISC-V ISA, in contrast to the power efficient offerings from SiFive

Interestingly, they suddenly got a lot of criticism for not having free source code for all hardware initialization earlier this year. On one of the threads on this issue we discussed this here, but I forget which one. That is, that even if the ISA is completely open and can be audited (no hardware backdoors for example), many computers and "dev boards" depend on some proprietary, non-free low level hardware initialization software. This is why the raspberry pi is considered "severely flawed" by the FSF (it cannot boot without a blob). It turns out Sifive had a similar problem. Here is the post by Coreboot dev Ron Minnich where he compares it to any ARM board because

So, AFAIK this is the only computer that you can buy and boot with 100% open source code and also have a publically descried instruction set architecture so that you could in theory make the processor your self at home (if that was really something you wanted to do). They still use "closed hardware" parts on the board (like ethernet) but the code appears to be open. The price is a bit steep though. (1000 USD, even though the performance and the 8 GB RAM are on another level compared to most other ARM boards. OK, there is also POWER, but those cost 10x more and probably have all the same problems if not more.

Here are some news from the Debian port

2018-09-13

A fix for the broken initrd handling in the Linux kernel has been committed to the upstream kernel git repository and will be part of the 4.19rc4 release. First versions of a patchset to support the qemu RISC-V "virt" board in u-boot have been posted to the upstream u-boot development list.

2018-08-21

The last driver bits required for booting the mainline kernel to userland on a qemu "virt" machine have been merged during the Linux 4.19 merge window. It is now possible to build a working kernel directly from upstream git without any additional patches. Please note that this currently only works for a "static" kernel, i.e. without initrd. Initrd support requires an additional patch that is planned to go upstream later in the 4.19 development cycle.

2018-08-04

Debian 9.5 has been released on 2018-07-14 and dak now accepts packages with riscv64 in their control file. As a result, a number of essential packages have been moved from the "unreleased" to the "unstable" suite and it is now possible to use debootstrap to create a "minbase" riscv64 chroot.

The U7 Series features SiFive’s highest-performance RISC-V Linux-capable application processor. The U7 core has a superscalar 8-stage pipeline with support for virtual memory, enabling the most demanding 64-bit RISC-V applications such as Edge Compute, Big-Data Analytics and 5G Base Stations.

This is definitely welcome. The RISC-V products to date are low end performancewise (and energy use also). But POWER9 implementations out there are pretty high performance like more for a datacenter. This new Raptor that you mention (didn't know about it, thanks) apparently is attempting to solve the problem by creating a lower performance version that might be in the price range acceptable for a "home users". The prices really need to go down before it starts to get intetesting. RISC-V prices will come down.

Also, this is an interesting development. Once it was announced that RISC-V ISA is going to be under a liberal license allowing proprietary extension to the ISA and hardware designs that are not open, many cynical people claimed that this is what would indeed happen for 100% certainty. However, western digital open's it's own design (SweRV Core and SweRV Instruction set):

To further accelerate open standard interfaces and RISC-V processing architectures, Western Digital offers three open-source innovations designed to support both internal RISC-V development efforts as well as those of the growing RISC-V ecosystem.

Furthermore, many people have noted that it is not possible to make a 100% free and openly described board because the board need other devices than just the CPU like GPU or ethernet controllers and thigns. So, it is itneresting to notice that there is a open gpu project also going on:

The Libre RISC-V M-Class is a RISC-V chip that is libre-licensed to the bedrock. It is a low-power, mobile-class, 64-bit Quad-Core SoC at a minimum 800mhz clock rate, suitable for tablet, netbook, and industrial embedded systems. Full source code and files are available not only for the operating system and bootloader, but also for the processor, its peripherals and its 3D GPU and VPU.