I posted some pictures in the next few posts. Look at the LTSpice simulation to get a better view.

FIND THE ATTACHMENT AT THE BOTTOM (or a little bit better in post 4) AND OPEN IT WITH LTSPICE. IF YOU DON"T HAVE LTSPICE YOU CAN DOWNLOAD IT FOR FREE!

I have created this little power supply schematic just as a learning exercise for myself and want to share it. I want to write up an explanation as part of the learning, and planning to share it means I am less likely to try and fudge. I will be learning more if I can actually explain things, and in case my explanation fails, anyone who reads might be able to help me out with tips on things I have missed.

The listed transient test includes two and half cycles of the load swinging between 250mAmps and 2Amps

The FET averages less than half a watt.

Power Supply Average INPUT Power 9.2W
Load Power OUTPUT Average 8.1W
Efficiency 88%

At the 2Amp output level.

Power Supply Average INPUT Power 15.9W
Load Power OUTPUT Average 14.3W
Efficiency 90%

At the 250 mAmp Output.

Power Supply Average INPUT Power 2.3W
Load Power OUTPUT Average 1.8W
Efficiency 78.3%

This is a very basic SIMULATED switching power supply. This is not a tested design outside of a computer.

It is basic in how it works because when the output voltage gets high the drive to the FET is dropped to zero, which shuts off the input power.

Like many SMPS it is meant to have a load. Dropping the output current below about 250ma will cause oscillations to start feeding out.

Starting from power up.
R3 conducts to the base of the Q1 Q2 follower bridge. This will pull the gate of M1 (the NMOS) high enough for it to work as a linear regulator.
It will only be doing this crude linear regulation for a few milliseconds and it will regulate the voltage, but it would be on the high side hitting almost 9 Volts peak. That still means it is dropping 7 or so of the 16 Volts supply. But to keep that spike out of the startup we have the RC line with C5 of 22uFarads that has to charge first. This means that the linear regulation phase ramps up instead of overshooting.

Once we reach our regulated voltage range of around 6.9 Volts we see something really happening.
The sense circuit starts with the line of Rcurrent and DVoltage a 6.2 Volt Zener Diode. That will turn on Q4 when the total voltage gets above 6.2 + .7 = 6.9V for DVoltage plus the emitter base drop of Q4. When Q4 turns on, our sense feed goes to Q5 which pulls the gate drive bridge low. High Sense signal from a high voltage means that the NMOS M1 stops conducting. Without input power the current and voltage will start to drop.

Other parts are involved. C1, C2, and C3 are different stages of smoothing and timing. I know they are critical but don't ask me how to calculate the values needed for these. I picked and switched until things worked. If somebody can explain a better way I would thank you very much for doing so.
LED D3 is the GoodSense Indicator Light. It is also an important part of the sense feedback loop. It is used to create hysteresis. There won't be small dribbles of sense current. Q4 has to cross the threshold for the voltage drop across the LED. You get a better turn on turn off signal from this.

R10 and CRipple are added for ripple rejection. The Zener line and the Q4 lines to ground controlled by the Zener, with an assist by the CRipple provide some little shunt regulation which helps to smooth the ripples out. If you lower the value of R8 you would get more shunt current, but it also changes the sense, and shunt regulation wastes power. You would also be changing the sense signal and switching frequency. I do know that the value of CRipple needs to be much smaller than C2 so that it has much higher AC impedance and can have more impact on the bias of Q4.

Now comes the transformer action part of this simmed SMPS. L1 was conducting and when the FET turns off, the magnetic field energy that it had built up decays but tells it to try to keep conducting. If it didn't have an easy path for current it would build up crazy voltages, but D1 lets the switching coil conduct from ground. So the coil just uses its stored energy to try and keep adding voltage to the output even though we shut off the main power with the FET. This is okay because if it didn't do this the load would drop the voltage too quickly and cause the sense line to allow the FET back on too soon. This is why you need higher frequency for smaller coil components. Less Magnetic Fields mean they stop conducting faster.

Eventually the coil conduction stops and the load drains the voltage down and our sense signal goes away. We switch the power back on.

We are not switching the FET fully because we don't have 10 volts above the gate. This particular FET will start to conduct with only about 5 Volts which made the startup easier but to make this an efficient switcher we want to get the gate about 10 Volts above the 16 volt input power. We only need to drive the gate with milliamps of curent so we can use a doubler to get a higher voltage. The doubler needs a pulse frequency and I will take it from the collector of Q5 where we convert the sense signal into a gate drive through the bridge follower.

I just use it to drive another bridge made of Q6 and Q3. They draw power through the Capacitor and D2. Then they push up the Capacitor and it conducts through D2 to create a higher level voltage that we can use to drive the gate. To do that we need to reconnect to the PULSE node through a collector resistor. D7 between the collector of Q5 and the R3 collector resistor and input power supply will disconnect them from this higher level power. D8 will do the same for the collector of Q2 at the top of the gate drive bridge.

Other parts that should be mentioned.

D5 and D6 are gate protection. They limit the gate to source voltage to 20 Volts. I think it is more efficient to set that at the max of 20V allowed for the gate instead of just 10Volts. That way the Zeners will shunt off less power, and the Mosfet is minimally more conductive with the higher gate drive. I should upload a 20 volt zener model but 2 x 10 volt in series works.

L2 and C4 are output filtering but they help the regulator. They reduces the strain from changing loads, and even so there is a noticeable glitchiness when the load falls from 2 Amps to only 250 milliAmps in only a few milliseconds.

Interesting look and sees. The node called COILDRIVEakaFETOUTPUT. It swings all the way to 0 Volts even though it has a DC connection to the 6.9 Volts of the output. You can look at the current of the coil and see that it is a triangle wave that varies over a narrow range. One end stays at near 6.9 Volts and the other switches back and forth between 16 Volts and 0 Volts. Anybody still learning about switchers really needs to understand this tendency of the coil to not want to conduct until it builds up its magnetic field and then not want to stop conducting until its magnetic field collapses. It has 6.9 volts across it from ground to the PreReg node that feeds the output filters. The coil does not stop conducting when the NMOS is turned off. It just starts to slow down a little.

This is not a fixed frequency switcher. It operates around 27khz and it tends to be symmetrical meaning 50% duty cycle. It really just keeps turning off the power when the voltage gets too high. That is as basic as a switcher gets.

I meant to post the pictures before now - but I also meant to get them into better shape. The schematic is easier to see in LTSpice where you can poke at it.

The test plot shows the pulsed load current I used as a test. You can see that the regulation tends to overshoot noticeably when it is too quickly unloaded. It takes a while for the coil to lose its magnetic field and drop the higher current level. That translates into some ringing and the overvoltage.