Test TSC synchronization across CPUs. Architecture independant and can thereforebe used on various architectures. Aims at testing the TSC synchronization on arunning system (not only at early boot), with minimal impact on interruptlatency.

I've written this code before x86 tsc_sync.c existed and given it worked wellfor my needs, I never switched to tsc_sync.c. Although it has the same goal, itdoes it a bit differently :

tsc_sync looks at the cycle counters on two CPUs to see if one compared to theother are going backward when read in loop. The LTTng code synchronizes bothcores with a counter used as a memory barrier and then reads the two TSCs at adelta equal to the cache line exchange. Instruction and data caches are primed.This test is repeated in loops to insure we deal with MCE, NMIs which could skewthe results.

The problem I see with tsc_sync.c is that is one of the two CPUs is delayed byan interrupt handler (for way too long) while the other CPU is doing itscheck_tsc_warp() execution, and if the CPU with the lowest TSC values runsfirst, this code will fail to detect unsynchronized CPUs.

This sync test code does not have this problem.

A following patch replaces the x86 tsc_sync.c code by this architectureindependant code.

This code also adds the kernel parameterforce_tsc_sync=1which forces resynchronization of CPU TSCs when a CPU is hotplugged.