The LL (Load Linked) and SC (Store Conditional) instructions are used to atomically update (read-modify-write) locations in memory. When the LL instruction initiates a 32-bit load from memory, an internal CPU status bit is set. A subsequent SC instruction to the same address checks if the read-modify-write begun by the previous LL can complete atomically, and if so, writes the value to memory and sets rt = 1 (true). If the read-modify-write cannot complete atomically, no write to memory is performed and rt is set to 0 (false).