FPGAs are increasingly finding themselves in huge data-centers as well as in the hands of hobbyists. However the wide availability of these high and low cost devices contrasts with the narrow ways in which one can access them -- through proprietary closed-source tools and IP -- which can hamper the realisation and deployment of novel FPGA-based applications and EDA innovations. Open-source is a proven and prevalent success when it comes to CPU and GPU silicon, and there are already efforts to drive reconfigurable silicon towards the same trend.

This one-day workshop aims to bring together industrial, academic, and hobbyist actors to explore, disseminate, and network over ongoing efforts for open design automation, with a view to enabling unfettered research and development, improving EDA quality, and lowering the barriers and risks to entry for industry. These aims are particularly poignant due to the recent efforts across the European Union (and beyond) that mandate "open access" for publicly funded research to both published manuscripts as well as any code necessary for reproducing its conclusions.

Directions on where the open-source FPGA movement should go, current weaknesses in the toolchain, and/or perspectives from industry on how open-source can affect aspects of safety, security, verification, IP protection, time-to-market, datacenter/cloud infrastructure, etc.

Discussions and case studies on how to license, acquire funding, and commercialise technologies surrounding open-source hardware, which may be different to open software.

Important dates

Submission deadline

17 December 2018

Notification of acceptance

14 January 2019

Camera-ready final version

11 February 2019

Workshop

29 March 2019

Submission details and requirements

Prospective authors are invited to submit original contributions (up to six pages), extended abstracts describing work-in-progress or position papers (not exceeding two pages), and demo proposals that would be of general interest. Papers must be submitted as an A4-sized PDF, in the IEEE conference format.

In line with OSDA's mission, we encourage and will favour submissions that make all artifacts used for experimentation (benchmarks, code, etc.) available for private peer-review. Accepted submissions are required to publish these artifacts under an OSI-approved (preferably permissive) license.

The proceedings of this workshop containing all accepted papers will be published on the open-access arXiv repository. Every accepted paper must have at least one author registered to the workshop by 31 January. Selected papers may also be considered for a special-issue journal; student authors may be eligible for travel assistance from our sponsors.

Talk synopsis:The "internet of everything" envisions trillions of connected objects loaded with high- bandwidth sensors requiring massive amounts of local signal processing, fusion, pattern extraction and classification. While silicon access cost is naturally decreasing due to the twilight of the Moore's law, the access to hardware IPs still represents a huge barrier for innovative start-ups and companies approaching the market of IoT. In this context, the recent growth of high-quality open source hardware IPs represents a promising way to surpass this barrier, paving the way for a number of exciting applications of open-source electronics. In this talk, I will describe the evolution of the open-source Parallel-Ultra-Low-Power (PULP) platform as well as opportunities and challenges for next generation open source computing systems.

Speaker biography:Davide Rossi, received the PhD from the University of Bologna, Italy, in 2012. He has been a post doc researcher in the Department of Electrical, Electronic and Information Engineering "Guglielmo Marconi" at the University of Bologna since 2015, where he currently holds an assistant professor position. His research interests focus on energy efficient digital architectures in the domain of heterogeneous and reconfigurable multi and many-core systems on a chip. This includes architectures, design implementation strategies, and runtime support to address performance, energy efficiency, and reliability issues of both high end embedded platforms and ultra-low-power computing platforms targeting the IoT domain. In these fields, he has published more than 80 paper in international peer- reviewed conferences and journals.

Talk synopsis:High-level synthesis (HLS) is the automated synthesis of a hardware circuit from a software program First proposed in the 1980s, and spending decades on the sidelines of mainstream RTL digital design, there has been tremendous buzz around HLS technology in recent years. HLS is on the upswing as a design methodology for field-programmable gate arrays (FPGAs) to improve designer productivity and ultimately, to make FPGA technology accessible to software engineers having limited hardware expertise. The hope is that down the road, software developers can use HLS to realize FPGA-based accelerators customized to applications that work in tandem with standard processors to raise computational throughput and energy efficiency. In this talk, I will overview the trends behind the recent drive towards FPGA HLS and why the need for, and use of, HLS will only become more pronounced in the coming years. The talk will highlight current HLS research directions and expose some of the challenges for HLS that may hinder its update in the digital design community. I will describe work underway in the LegUp HLS project at the University of Toronto -- a publicly available HLS research tool that has been downloaded by over 5000 groups from around the world. LegUp HLS technology is being commercialized in a start-up company, LegUp Computing Inc. (https://www.legupcomputing.com/), which was founded in 2015 and received seed funding from Intel Capital in 2018. A key value proposition of LegUp HLS is FPGA-vendor agnosticism — synthesized circuits can be targeted to any FPGA.

will be discussing whether it is possible to build a (stable!) business or research group around open-source -- when the things that you are building is ostensibly given away for free. Topics explored will be panellist's experiences with doing this, their opinions on the various open-source licenses (copyleft versus permissive) in the context of hardware, their views on whether open and closed-source can co-exist, and the momentum within the EU to mandate "open access" research.

Talk synopsis:ASTRONs mission is to make discoveries in radio astronomy happen. The high performance streaming data systems we build to do that naturally have FPGAs at their hearts. To balance project requirements, cost and availability of FPGA devices, ASTRON uses an approach that is both vendor and application independent. With generic, universal FPGA platforms (UniBoard, UniBoard2, Perentie), new science applications can take advantage of already available hardware. By also having a vendor independent VHDL library and tool flow, new FPGA hardware can also be adopted/developed with minimal firmware rework needed. This talk is about the advantages of vendor independence and how we chose to implement this, covering VHDL source code, vendor IP, library structures and simulation and synthesis tools. Another important aspect is the automated regression testing of the firmware library as it is updated on a daily basis. All this is made possible and structured by ASTRONs scripted tool flow, which is to be released as open source on OpenCores.org. Finally, this talk will cover how and why ASTRON is going to release its firmware library on OpenCores, and the technical challanges in doing so.

Speaker biography:Daniel van der Schuur is a digital designer at the Netherlands Institute for Radio Astronomy (ASTRON). As ASTRON designs, builds and operates complex high performance hybrid (FPGA, GPU, CPU, fiber networks) systems to make new discoveries, Daniel is passionate about reducing the time to science - from streaming system design to VHDL implementation.

Talk synopsis:On average half the development time for an FPGA is spent on verification. It is possible to significantly reduce this time, and major reductions can be accomplished with only minor adjustments and no extra cost. For an FPGA design we all know that the architecture - all the way from the top to the micro architecture - is critical for both the FPGA quality and the development time. It should really be obvious that this also applies to the testbench. UVVM (the open source Universal VHDL Verification Methodology) was developed to solve this and will reduce the verification time significantly while at the same time improving the product quality. UVVM provides a very simple and powerful architecture that allow designers to build their own test harness much faster than ever before - using a mix of their own and open source verification components. UVVM also provides an architecture, methodology and library to allow VHDL verification components to be made extremely efficiently. And maybe the most important feature - UVVM allows the best possible testbench and test case overview using high level commands for both DUT interface control and synchronization. The great overview, maintainability, extensibility, modifiability and reuse has resulted in an extraordinary fast spread of this methodology - and according to the 2018 Wilson Research report UVVM was the by far fastest growing FPGA verification methodology over the last two years. UVVM is the new standardised VHDL testbench architecture, recommended by Doulos and backed by ESA (the European Space Agency) through a contract for further extension of the UVVM functionality. This presentation will show you how simple this is to understand, build and control. It will also show the latest features from the ESA project and further planned extensions.

Talk synopsis:In many ways, HDL developers have been many years behind their counterparts in the software world. One such area is core management. Where the software developers simply specify which libraries they depend on, HDL developers rely on copying around source code. Where software developers can select their build tool with a flick of a switch, HDL developers use tool-specific project files powered by custom makefiles. FuseSoC rectifies this by bringing a modern package manager and a uniform build system to HDL developers, making it easy to reuse existing code, change tools and move projects between FPGAs from different vendors. Having been around for seven years there are now hundreds of FuseSoC-compatible cores and 14 different simulation, synthesis and lint tools supported. This presentation will give an overview of where FuseSoC can help spending less time on the cores, and more time on the core business

Speaker biography:Olof Kindgren is a senior digital design engineer working for Qamcom Research & Technology. He became actively involved with free and open source silicon through the OpenRISC project in 2011 and has since then worked on many FOSSi projects with a special interest in tools and collaborations. Notable work include the FuseSoc IP core package manager; SERV, the award-winning RISC-V CPU and ipyxact, the IP-XACT Python library. In 2015, he also co-founded FOSSi Foundation, a vendor-independent organization with the mission to promote and assist Open Source Silicon in academia, the industry and for hobbyists alike.