EECS 3122Last Time•Unlike inverters, there are multiple charge/discharge paths in complex gates– Must size devices according to worst-case paths, try to balance rise/fall delays– We can “collapse” series and parallel devices into a single effective MOSFET•A number of techniques to speed up gates exist– Re-ordering devices, progressive sizing, a few more shown next– Elmore delay concept helps us model gate delays with internal capacitances considered