POLYSILICON PLUG BIPOLAR TRANSISTOR FOR PHASE CHANGE MEMORY - Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base.

2010-07-15

20100176363

VARIABLE RESISTANCE ELEMENT AND SEMICONDUCTOR DEVICE PROVIDED WITH THE SAME - A variable resistance element includes: a first electrode; a variable resistance material layer formed on the first electrode; and a second electrode formed on this variable resistance material layer. The variable resistance material layer is made of an uncrystallized material including a transition metal oxide, which is an oxide of a transition metal M

RESISTANCE VARIABLE MEMORY DEVICES AND METHODS OF FABRICATING THE SAME - A resistance variable memory device includes at least one bottom electrode, a first insulating layer containing a trench which exposes the at least one bottom electrode, and a resistance variable material layer including respective first and second portions located on opposite sidewalls of the trench, respectively, where the first and second portions of the resistance variable material layer are electrically connected to the at least one bottom electrode. The device further includes a protective layer covering the resistance variable material layer within the trench, and a second insulating layer located within the trench and covering the protective layer within the trench

2010-07-15

20100176366

Nonvolatile memory cell including carbon storage element formed on a silicide layer - A nonvolatile memory cell includes a storage element, the storage element comprising a carbon material, a steering element located in series with the storage element, and a metal silicide layer located adjacent to the carbon material. A method of making a device includes forming a metal silicide over a silicon layer, forming a carbon layer over the metal silicide layer, forming a barrier layer over the carbon layer, and patterning the carbon layer, the metal silicide layer, and the silicon layer to form an array of pillars.

2010-07-15

20100176367

MEMORY CELL HAVING DIELECTRIC MEMORY ELEMENT - Some embodiments include apparatus and methods having a memory cell with a first electrode, a second electrode, and a dielectric located between the first and second electrodes. The dielectric may be configured to allow the memory cell to form a conductive path in the dielectric from a portion of a material of the first electrode to represent a first value of information stored in the memory cell. The dielectric may also be configured to allow the memory cell to break the conductive path to represent a second value of information stored in the memory cell.

2010-07-15

20100176368

METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE, AND SEMICONDUCTOR MEMORY DEVICE - A method of manufacturing semiconductor memory device comprises forming a first wiring layer and a memory cell layer above a semiconductor substrate; forming a plurality of first trenches extending in a first direction in the first wiring layer and the memory cell layer, thereby forming first wirings and separating the memory cell layer; burying a first interlayer film in the first trenches to form a stacked body; forming a second wiring layer above the stacked body; forming a plurality of second trenches, extending in a second direction intersecting the first direction and reaching an upper surface of the first interlayer film in depth, in the first stacked body with the second wiring layer formed thereabove, thereby forming second wirings; removing the first interlayer film isotropically; and digging the second trenches down to an upper surface of the first wirings, thereby forming memory cells.

2010-07-15

20100176369

Metalized Silicon Substrate for Indium Gallium Nitride Light-Emitting Diodes - A light emitting diode having a metallized silicon substrate including a silicon base, a buffer layer disposed on the silicon base, a metal layer disposed on the buffer layer, and light emitting layers disposed on the metal layer. The buffer layer can be AlN, and the metal layer ZrN. The light emitting layers can include GaN and InGaN. The metallized silicon substrate can also include an oxidation prevention layer disposed on the metal layer. The oxidation prevention layer can be AlN. The light emitting diode can be formed using an organometallic vapor phase epitaxy process. The intermediate ZrN/AlN layers enable epitaxial growth of GaN on silicon substrates using conventional organometallic vapor phase epitaxy. The ZrN layer provides an integral back reflector, ohmic contact to n-GaN. The AlN layer provides a reaction barrier, thermally conductive interface layer, and electrical isolation layer.

Semiconductor Diodes Fabricated by Aspect Ratio Trapping with Coalesced Films - A photonic device comprises a substrate and a dielectric material including two or more openings that expose a portion of the substrate, the two or more openings each having an aspect ratio of at least 1. A bottom diode material comprising a compound semiconductor material that is lattice mismatched to the substrate occupies the two or more openings and is coalesced above the two or more openings to form the bottom diode region. The device further includes a top diode material and an active diode region between the top and bottom diode materials.

2010-07-15

20100176372

NITRIDE SEMICONDUCTOR LIGHT EMITTING DIODE - A nitride semiconductor light emitting diode (LED) is disclosed. The nitride semiconductor LED can include an active layer formed between an n-type nitride layer and a p-type nitride layer, where the active layer includes two or more quantum well layers and quantum barrier layers formed in alternation, and the quantum barrier layer formed adjacent to the p-type nitride layer is thinner than the remaining quantum barrier layers. An embodiment of the invention can be used to improve optical efficiency while providing crystallinity in the active layer.

2010-07-15

20100176373

FABRICATION METHOD OF NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE THEREBY - A method for fabricating a nitride semiconductor light emitting device, and a nitride semiconductor light emitting device fabricated thereby are provided. The method includes: forming a first conductive nitride semiconductor layer on a substrate; forming an active layer on the first conductive nitride semiconductor layer; forming a second conductive nitride semiconductor layer on the active layer; and lowering a temperature while adding oxygen to the result by performing a thermal process.

2010-07-15

20100176374

NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device according to an aspect of the invention may include: first and second conductive nitride semiconductor layers; and an active layer having a DH structure located between the first and second conductive nitride semiconductor layers, and including a single quantum well structure active layer having the single quantum well structure includes at least one polarization relaxation layer formed of a nitride single crystal having a higher energy band gap than the quantum well.

2010-07-15

20100176375

Diode-Based Devices and Methods for Making the Same - In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.

Fabrication Method for Organic Light Emitting Device and Organic Light Emitting Device Fabricated by the Same Method - The present invention relates to a method for producing an organic light emitting device, comprising a step of sequentially forming on a substrate a first electrode formed of a metal, one or more organic material layers including a light emitting layer, and a second electrode, which comprises a step of forming a layer on the first electrode using a metal having the higher oxidation rate than the first electrode before forming the organic material layer, and to an organic light emitting device produced by the same.

2010-07-15

20100176379

SELF-ALIGNED ORGANIC THIN FILM TRANSISTOR AND FABRICATION METHOD THEREOF - The present invention relates to a self-aligned organic thin film transistor (TFT) and a fabrication method thereof. According to the present invention, a gate electrode is formed from a first conductive layer patterned on a substrate, a gate dielectric layer is formed on top of the substrate to cover the gate electrode, and a second conductive layer is then formed on the gate dielectric layer. Subsequently, ultraviolet (UV) backside exposure for irradiating the second conductive layer with UV from a bottom side of the substrate using the gate electrode as a mask, and source/drain electrodes self-aligned with the gate electrode is then formed not to overlap with the gate electrode by developing the second conductive electrode. Thereafter, an organic semiconductor layer is formed between and on the source/drain electrodes. In the present invention, an organic TFT can be fabricated using a reel-to-reel process, and therefore, the fabrication process can be simplified.

2010-07-15

20100176380

ORGANIC PHOTOELECTRIC DEVICE AND MATERIAL USED THEREIN - The present invention relates to an organic photoelectric device and a material used therein. The organic photoelectric device includes a substrate, an anode disposed on the substrate, a hole transport layer (HTL) disposed on the anode, an emission layer disposed on the hole transport layer (HTL), and a cathode disposed on the emission layer. The emission layer is characterized in that it includes a host and a phosphorescent dopant, and the host has a difference between the reduction potential or oxidation potential of the host and the reduction potential or oxidation potential of the phosphorescent dopant of less than 0.5 eV. The organic photoelectric device according to the present invention is capable of accomplishing higher efficiency and a lower driving voltage than those of the conventional organic photoelectric device, and has a simplified structure resulting in saving of manufacturing cost.

2010-07-15

20100176381

SEMICONDUCTOR DEVICE AND DISPLAY DEVICE - It is an object to provide a display device in which an operational characteristic in a bottom gate type organic semiconductor thin film transistor can be maintained to a stable characteristic without receiving an influence of an electrode provided on an upper layer thereof, and a display with a high reliability can be realized by using this as a driver element. A bottom gate type thin film transistor Tr provided on a substrate

2010-07-15

20100176382

Organic light emitting diode display - An organic light emitting diode display device constructed with an organic light emitting element including a first electrode, an organic emission layer, and a second electrode sequentially laminated together, a transmittance control layer formed on the organic light emitting element, a selective reflective layer formed on the transmittance control layer, a polarizing plate formed on the selective reflective layer, and a phase retardation plate disposed between the organic light emitting element and the polarizing plate.

2010-07-15

20100176383

Organic light emitting display device and method of manufacturing the same - Disclosed is an organic light emitting display device and a method of manufacturing the same. The organic light emitting display device includes the thin film transistor of the drive unit that has the activation layer formed in a structure where the first oxide semiconductor layer and the second oxide semiconductor layer are stacked, the thin film transistor of the pixel unit that has the activation layer formed of the second oxide semiconductor layer, and the organic light emitting diode coupled to the thin film transistor of the pixel unit. The thin film transistor of the drive unit has channel formed on the first oxide semiconductor layer having a higher carrier concentration than the second oxide semiconductor layer, having a high charge mobility, and the thin film transistor of the pixel unit has a channel formed on the second oxide semiconductor layer, having a stable and uniform functional property.

2010-07-15

20100176384

Organic luminescence transistor device and manufacturing method thereof - The invention is an organic luminescence transistor device including: a substrate; an assistance electrode layer provided on a side of an upper surface of the substrate; an insulation film provided on a side of an upper surface of the assistance electrode layer; a first electrode provided locally on a side of an upper surface of the insulation film, the first electrode covering an area of a predetermined size; an electric-charge-injection inhibiting layer provided on an upper surface of the first electrode, the electric-charge-injection inhibiting layer having a shape larger than that of the first electrode in a plan view; an electric-charge injection layer provided on the side of an upper surface of the insulation film at an area not provided with the first electrode or the electric-charge-injection inhibiting layer and on an upper surface of the electric-charge-injection inhibiting layer; a luminescent layer provided on an upper surface of the electric-charge injection layer; and a second electrode layer provided on a side of an upper surface of the luminescent layer.

LUMINESCENT METAL COMPLEXES FOR ORGANIC ELECTRONIC DEVICES - The present invention relates to auxiliary ligands for luminescent metal complexes, particularly emitter complexes having such auxiliary ligands, and particularly light-emitting devices, and particularly organic light-emitting devices (OLED) having metal complexes, which have the auxiliary ligands according to the invention.

2010-07-15

20100176387

ORGANIC THIN-FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - An organic thin-film transistor of the present invention has a gate electrode, a gate insulating film, a source electrode, a drain electrode, and an organic semiconductor layer provided above a substrate, and further has a thiol compound layer composed of a benzenethiol compound and provided on a surface of the source electrode and a thiol compound layer composed of a benzenethiol compound and provided on a surface of the drain electrode. This makes it possible to provide an organic thin-film transistor whose threshold voltage can be selectively controlled without greatly affecting a current characteristic other than the threshold voltage.

2010-07-15

20100176388

THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME AND FLAT PANEL DISPLAY DEVICE HAVING THE SAME - A thin film transistor which has a compound semiconductor including oxygen as an activation layer, a method of manufacturing the thin film transistor, and a flat panel display device having the thin film transistor, of which the thin film transistor comprises: a gate electrode formed on a substrate; an activation layer formed on the gate electrode, insulated from the gate electrode by a gate insulating film, and formed of a compound semiconductor including oxygen; a passivation layer formed on the activation layer; and source and drain electrodes formed to contact the activation layer, wherein the passivation layer includes titanium oxide (TiO

2010-07-15

20100176389

ORGANIC LIGHT EMITTING DIODE AND METHOD OF MANUFACTURING THE SAME - Provided are an organic light emitting diode and a method of manufacturing the same. The organic light emitting diode adjusts an optical resonance thickness and prevents spectrum distortions without use of an auxiliary layer. The organic light emitting diode includes a first electrode that is optically reflective; a second electrode that is optically transmissible and faces the first electrode; an organic emission layer interposed between the first electrode and the second electrode, the organic emission layer including: a first emission layer including a mixed layer that contains a host material and a dopant material, and a second emission layer comprising only the host material; and a carrier injection transport layer interposed between the organic emission layer and the first electrode or between the organic emission layer and the second electrode.

2010-07-15

20100176390

ELECTROLUMINESCENT EFFICIENCY - An organic light emitting device is provided. The device has an anode, a cathode, and an emissive layer disposed between the anode and the cathode. The emissive layer further includes a molecule of Formula I (shown below) wherein an alkyl substituent at position R′

2010-07-15

20100176391

ORGANIC EL ELEMENT AND A METHOD FOR MANUFACTURING THE ORGANIC EL ELEMENT - A dense cathode electrode layer having a step coverage is to be formed on an electron injection layer. The electron injection layer in which fine particles of an electron injection material is dispersed in an organic thin film having an electron transport property is formed by vapor co-depositing the electron transport material and the electron injection material; and a cathode electrode layer made of an alloy layer of MgAg is formed by a sputtering method. Since lower portions of the fine particles of the electron injection material dispersed in the surface of the organic thin film are buried in the organic thin film, the electron injection particles are not peeled off even if sputtering particles collide with the electron injection particles, and the upper portions are in contact with the cathode electrode layer formed by sputtering particles.

2010-07-15

20100176392

Thin film transistor and method of manufacturing the same - A TFT includes a substrate, a source electrode and a drain electrode on the substrate, the source and drain electrodes separated from each other, an active layer on the substrate between the source electrode and the drain electrode, a cladding unit on side surfaces of the source electrode and the drain electrode, a gate insulating layer on the substrate, the gate insulating layer overlapping the active layer and the cladding unit, and a gate electrode on the gate insulating layer, the gate electrode overlapping the active layer.

Thin film transistor and flat panel display device having the same - An oxide semiconductor thin film transistor and a flat panel display device incorporating the same oxide semiconductor thin film transistor. The thin film transistor includes a gate electrode formed on the substrate, a gate insulating layer formed on the substrate and covering the gate electrode, an oxide semiconductor layer formed on the gate insulating layer and covering the gate electrode, a titanium layer formed in a source region and a drain region of the oxide semiconductor layer, and source and drain electrodes respectively coupled to the source region and the drain region through the titanium layer and made of copper. The titanium layer reduces the contact resistance between the source and drain electrodes made of copper and the oxide semiconductor layer, forms a stable interface junction therebetween, and blocks a diffusion of copper.

PROBE, PROBE CARD, AND METHOD OF PRODUCTION OF PROBE - A probe comprises: a beam part having a Si layer composed of monocrystalline silicon; an interconnect part provided along the longitudinal direction of the beam part on one main surface of the beam part; a contact part provided at a front end part of the interconnect part and to be electrically connected to input/output terminals of an IC device; and a base part supporting a plurality of beam parts all together in a cantilever fashion, and a longitudinal direction of the beam part substantially matches with a crystal orientation <100> of monocrystalline silicon of the Si layer.

ELECTRONIC DEVICE IMPROVED IN HEAT RADIATION PERFORMANCE FOR HEAT GENERATED FROM ACTIVE ELEMENT - An electronic device of the present invention includes a first substrate provided with a thin film active element, having a thickness of 200 μm or lower, and a second substrate formed with a high thermal conductivity portion. The second substrate is applied to one surface of the two surfaces of the first substrate, i.e., the surface being the side other than the side that formed with the thin film active element. The thin film active element has a maximum power consumption of 0.01 to 1 mW. The high thermal conductivity portion is a region that corresponds to the position of the thin film active element and whose thermal conductivity falls within the range from 0.1 to 4 W/cm·deg.

2010-07-15

20100176399

BACK-CHANNEL-ETCH TYPE THIN-FILM TRANSISTOR, SEMICONDUCTOR DEVICE AND MANUFACTURING METHODS THEREOF - A back-channel-etch type TFT includes a gate electrode, an SiN film that is formed on the gate electrode, and an SiO film that is formed and patterned on the SiN film. The TFT further includes an polycrystalline semiconductor film that is formed and patterned on the SiO film in contact with the SiO film in such a way that all pattern ends of the polycrystalline semiconductor film are located in close proximity to pattern ends of the SiO film.

2010-07-15

20100176400

Display device and electronic apparatus - A display device includes: a pixel array unit having pixels including a circuit configuration, in which a first electrode of an electro-optical element and a source electrode of a driving transistor are connected together, a gate electrode of the driving transistor and a source electrode or a drain electrode of a writing transistor are connected together, a holding capacitor is connected between the gate electrode and the source electrode of the driving transistor, and an auxiliary capacitor is connected between the first electrode and a second electrode of the electro-optical element, disposed on a substrate in a matrix shape, wherein, from one pixel of adjacent pixels to an area of the other pixel, the auxiliary capacitor of the one pixel is set to be disposed, and an electrode of the auxiliary capacitor that is disposed on the electro-optical element side is conductive with the second electrode of the electro-optical element.

2010-07-15

20100176401

X-RAY DETECTOR AND MANUFACTURING METHOD OF THE SAME - An X-ray detector includes a gate wire formed on a substrate, the gate wire including a gate line, a gate electrode, and a gate pad, a gate insulating layer formed on the gate wire, a data wire formed on the gate insulating layer, the data wire including a data line intersecting the gate line, a source electrode, a drain electrode, and a data pad, a lower storage electrode formed on the gate insulating layer, the lower storage electrode comprising an opaque conductor material, and an upper storage electrode formed on the lower storage electrode, the upper storage electrode connected to the source electrode.

2010-07-15

20100176402

THIN FILM TRANSISTOR SUBSTRATE, ELECTRONIC APPARATUS, AND METHODS FOR FABRICATING THE SAME - A TFT substrate includes a substrate and at least a TFT disposed thereon. The TFT includes a semiconductor island and at least a gate. The semiconductor island has a source region, a drain region, and a channel region interposed therebetween. The semiconductor island has sub-grain boundaries. The gate corresponds to the channel region. A first included angle between an extending direction of the gate and a line connecting the centroid of the source region with the centroid of the drain region is not substantially equal to 90 degrees. A second included angle between the sub-grain boundaries in the channel region and the line connecting the centroid of the source region with the centroid of the drain region is not substantially equal to 0 degree or 90 degrees. Additionally, a method of fabricating a TFT substrate, an electronic apparatus, and a method of fabricating the electronic apparatus are also provided.

2010-07-15

20100176403

SILICON CARBIDE SUBSTRATE, EPITAXIAL WAFER AND MANUFACTURING METHOD OF SILICON CARBIDE SUBSTRATE - An SiC substrate includes the steps of preparing a base substrate having a main surface and made of SiC, washing the main surface using a first alkaline solution, and washing the main surface using a second alkaline solution after the step of washing with the first alkaline solution. The SiC substrate has the main surface, and an average of residues on the main surface are equal to or larger than 0.2 and smaller than 200 in number.

2010-07-15

20100176404

METHOD FOR FABRICATING HIGH-POWER LIGHT-EMITTING DIODE ARRAYS - One embodiment of the present invention provides a method for fabricating a high-power light-emitting diode (LED). The method includes etching grooves on a growth substrate, thereby forming mesas on the growth substrate. The method further includes fabricating indium gallium aluminum nitride (InGaAlN)-based LED multilayer structures on the mesas on the growth substrate, wherein a respective mesa supports a separate LED structure. In addition, the method includes bonding the multilayer structures to a conductive substrate. The method also includes removing the growth substrate. Furthermore, the method includes depositing a passivation layer and an electrode layer above the InGaAlN multilayer structures, wherein the passivation layer covers the sidewalls and bottom of the grooves. Moreover, the method includes creating conductive paths which couple a predetermined number of adjacent individual LEDs, thereby allowing the LEDs to share a common power supply and be powered simultaneously to form a high-power LED array.

2010-07-15

20100176405

Light Emitting Diode Lighting Package with Improved Heat Sink - Improved lighting packages are described for light emitting diode (LED) lighting solutions having a wide variety of applications which seek to balance criteria such as heat dissipation, brightness, and color uniformity. The present approach includes a backing of thermally conductive material. The backing includes a cell structure. The cell structure comprises a plurality of hollow cells contiguously positioned in a side by side manner. The present approach also includes an array of LEDs. The array of LEDs is mounted to a printed circuit board (PCB). The PCB is attached to the cell structure to balance heat dissipation and color uniformity of the LEDs.

2010-07-15

20100176406

NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A nitride semiconductor light emitting device is provided. The nitride semiconductor light emitting device includes a first nitride layer comprising at least N-type nitride layer. An insulating member is formed on the first nitride layer having a predetermined pattern. An active layer is formed in both sides of the insulating member on the first nitride layer to emit light. A second nitride layer is formed in both sides of the insulating member on the active layer and the second nitride layer comprises at least a P-type nitride layer.

2010-07-15

20100176407

METHOD FOR MANUFACTURING LIGHT EMITTING DIODE PACKAGE AND PACKAGE STRUCTURE THEREOF - The present invention relates to a method for forming a package structure for a light emitting diode (LED) and the LED package structure thereof. By employing the same sawing process to cut through the trenches of the leadframe, the package units are singulated and different lead portions are simultaneously separated from each other in each package unit. Therefore, the overflow issues of the encapsulant can be avoided without using extra taping process.

2010-07-15

20100176408

LIGHT-EMITTING DIODE WITH HIGH LIGHTING EFFICIENCY - The invention discloses a light-emitting diode, including a substrate, a first conductive type semiconductor layer, a second conductive type semiconductor layer, a light-emitting layer and plural laminated structures. The first conductive type semiconductor layer, the light-emitting layer and the second conductive type semiconductor layer are formed on the substrate in sequence. The plural laminated structures are formed on the upper surface of the second conductive type semiconductor layer such that the upper surface is partially exposed. Each laminated structure consists of at least one first insulated layer with a high refractive index and at least one second insulated layer with a low refractive index, where the at least one first insulated layer and the at least one second insulated layer are alternately formed to obtain said each laminated structure. Thereby, light emitted from the light-emitting layer can be reflected by the laminated structures to enhance the light-extraction efficiency.

SEMICONDUCTOR LIGHT EMITTING DEVICE - A wiring electrode is provided on a mount substrate. A light emitting element is provided on the wiring electrode to connect electrically with the wiring electrode and is configured to emit a blue to ultraviolet light. A reflective film is provided above the light emitting element to cover the light emitting element so that a space is interposed between the reflective film and the light emitting element. The reflective film is capable of transmitting the blue to ultraviolet light. A fluorescent material layer is provided above the light emitting element to cover the light emitting element so that the reflective film is located between the fluorescent material layer and the light emitting element. A light from the fluorescent material layer is reflected by the reflective film.

2010-07-15

20100176411

FLUORESCENT-LAMP-TYPE LED LIGHTING DEVICE - To provide a fluorescent-lamp-type LED lighting device that has a large amount of light intensity and that can replace a highly efficient existing lighting device, the fluorescent-lamp-type LED lighting device comprises an LED (

2010-07-15

20100176412

ORGANIC EL DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic EL device includes an insulative film, a first pixel electrode and a second pixel electrode which are disposed on the insulative film, a first light emission layer which is commonly disposed above the first pixel electrode and the second pixel electrode, a second light emission layer which is disposed above the first light emission layer, a counter-electrode which is disposed above the second light emission layer, and an exciton block layer which is disposed between the first light emission layer and the second light emission layer.

2010-07-15

20100176413

LIGHT-EMITTING DIODE DEVICE INCLUDING A MULTI-FUNCTIONAL LAYER - A light-emitting diode device includes: a substrate; a light-emitting layered structure formed on the substrate; a multi-functional layer having a first main portion and formed on the light-emitting layered structure for spreading current laterally and for reflecting light emitted from the light-emitting layered structure; and first and second electrodes electrically coupled to the light-emitting layered structure. The first electrode is formed on the light-emitting layered structure and has a first electrode main part. The first main portion of the multi-functional layer is aligned below and is provided with a size larger than that of the first electrode main part.

2010-07-15

20100176414

PACKAGING STRUCTURE OF LIGHT-EMITTING COMPONENTS - The present invention provides a packaging structure of light-emitting components, comprising at least a light-emitting component, at least a connection wire, a base, at least a reflection surface, and an insulator, and characterized in that: the light-emitting component produces a light source and corresponding heat energy; the connection wire is coupled to the light-emitting component and at least an electrode; the electrode is disposed on the base; the light-emitting component is disposed on the base; the light-emitting component includes a heat-conducting base; the reflection surface reflects the light source produced by the light emitting component; the insulator insulates the electrode from the reflection surface; and the reflection surface is formed integrally with the heat-conducting base.

2010-07-15

20100176415

LIGHT EMITTING DEVICE WITH IMPROVED LIGHT EXTRACTION EFFICIENCY - A light emitting device having a high degree of light extraction efficiency includes a substrate, and a light emitting structure disposed on one surface of the substrate, the substrate having an internal reformed region where the index of refraction differs from the remainder the substrate. The ratio of the depth of the reformed region (distance between the other surface of the substrate and the reformed region) to the thickness of the substrate is in a range of between 1/8 and 9/11.

2010-07-15

20100176416

LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A light emitting device and a method of manufacturing the same are disclosed. The light emitting device includes a buffer layer formed on a substrate, a nitride semiconductor layer including a first semiconductor layer, an active layer, and a second semiconductor layer, which are sequentially stacked on the buffer layer, a portion of the first semiconductor layer being exposed to the outside by performing mesa etching from the second semiconductor layer to the portion of the first semiconductor layer, and at least one nanocone formed on the second semiconductor layer.

2010-07-15

20100176417

LIGHT EMITTING DIODE PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A light emitting diode and method for fabricating the same are provided. The light emitting diode comprises a lead frame. A first material body is formed on the lead frame, wherein the first material body comprises a tip, an inner surface and an outer surface. A second material body is formed on the lead frame to completely cover the outer surface of the first material body. Particularly, the first material body comprises hydrophilic polymer and the second material body comprises hydrophobic polymer.

LIGHT-EMITTING DIODE WITH HIGH LIGHTING EFFICIENCY - The invention discloses a light-emitting diode. In an embodiment, the light-emitting diode includes a substrate, a first doping type semiconductor layer, a second doping type semiconductor layer, a light-emitting layer and plural laminated structures. The first doping type semiconductor layer, the light-emitting layer and the second doping type semiconductor layer are formed on the substrate in sequence. The plural laminated structures are formed on the top surface of the second doping type semiconductor layer such that the top surface is partially exposed. Each laminated structure consists of plural transparent insulating layers which have their respective refractive indices. Additionally, each of the laminated structures is formed in a way of upwardly stacking the transparent insulating layers in sequence with the refractive indices of the transparent insulating layers decreasing gradually, so as to enhance the light-extraction efficiency and the lighting efficiency of the light-emitting diode.

2010-07-15

20100176420

MESA HETEROJUNCTION PHOTOTRANSISTOR AND METHOD FOR MAKING SAME - A two-terminal mesa phototransistor and a method for making it are disclosed. The photo transistor has a mesa structure having a substantially planar semiconductor surface. In the mesa structure is a first semiconductor region of a first doping type, and a second semiconductor region of a second doping type opposite to that of the first semiconductor region, forming a first semiconductor junction with the first region. In addition, a third semiconductor region of the first doping type forms a second semiconductor junction with the second region. The structure also includes a dielectric layer. The second semiconductor region, first semiconductor junction, and second semiconductor junction each has an intersection with the substantially planar semiconductor surface. The dielectric covers, and is in physical contact with, all of the intersections.

2010-07-15

20100176421

DAMASCENE CONTACTS ON III-V CMOS DEVICES - A method for manufacturing a III-V CMOS device is disclosed. The device includes a first and second main contact and a control contact. In one aspect, the method includes providing the control contact by using damascene processing. The method thus allows obtaining a control contact with a length of between about 20 nm and 5 μm and with good Schottky behavior. Using low-resistive materials such as Cu allows reducing the gate resistance thus improving the high-frequency performance of the III-V CMOS device.

2010-07-15

20100176422

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor memory device includes a semiconductor substrate; a memory cell array on the semiconductor substrate, the memory cell array comprising a plurality of memory cells capable of electrically storing data; a sense amplifier configured to detect the data stored in at least one of the memory cells; a cell source driver electrically connected to source side terminals of the memory cells and configured to supply a source potential to at least one of the source side terminals of the memory cells; a first wiring configured to electrically connect between at least one of the source side terminals of the memory cells and the cell source driver; and a second wiring formed in a same wiring layer as the first wiring, the second wiring being insulated from the first wiring and being electrically connected to the sense amplifier, wherein the first wiring and the second wiring have a plurality of through holes provided at a predetermined interval.

Doping of Semiconductor Fin Devices - A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface.

2010-07-15

20100176425

TRANSISTOR WITH WIRE SOURCE AND DRAIN - Field-effect transistor that includes at least a gate, a layer of insulator, a drain, a source, a semi-conductor material connecting the source to the drain, the gate and the layer of insulator each surrounding the assembly constituted by the source, the drain and the semi-conductor material, the layer of insulator being arranged between the gate and said assembly.

HARDMASK MANUFACTURE IN FERROELECTRIC CAPACITORS - A method of manufacturing a semiconductor device. The method comprises fabricating a ferroelectric capacitor. The capacitor's fabrication includes forming conductive and ferroelectric material layers on a semiconductor substrate, forming a hardmask layer on the conductive and ferroelectric material layers, forming an organic bottom antireflective coating layer on the hardmask layer, and, patterning the organic bottom antireflective coating layer. Seasoning in a hardmask etching chamber is substantially unaffected by the patterning.

2010-07-15

20100176428

Spin field effect logic devices - Provided are spin field effect logic devices, the logic devices including: a gate electrode; a channel formed of a magnetic material above the gate electrode to selectively transmit spin-polarized electrons; a source on the channel; and a drain and an output electrode on the channel outputting electrons transmitted from the source. The gate electrode may control a magnetization state of the channel in order to selectively transmit the electrons injected from the source to the channel.

2010-07-15

20100176429

MRAM with storage layer and super-paramagnetic sensing layer - An MRAM is disclosed that has a MTJ comprised of a ferromagnetic layer with a magnetization direction along a first axis, a super-paramagnetic (SP) free layer, and an insulating layer formed therebetween. The SP free layer has a remnant magnetization that is substantially zero in the absence of an external field, and in which magnetization is roughly proportional to an external field until reaching a saturation value. In one embodiment, a separate storage layer is formed above, below, or adjacent to the MTJ and has uniaxial anisotropy with a magnetization direction along its easy axis which parallels the first axis. In a second embodiment, the storage layer is formed on a non-magnetic conducting spacer layer within the MTJ and is patterned simultaneously with the MTJ. The SP free layer may be multiple layers or laminated layers of CoFeB. The storage layer may have a SyAP configuration and a laminated structure.

2010-07-15

20100176430

Semiconductor Device with Reduced Parasitic Inductance - The present invention provides a technology for reducing the parasitic inductance of the main circuit of a power source unit. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETs, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are

2010-07-15

20100176431

CAPACITOR INSULATING FILM, CAPACITOR, AND SEMICONDUCTOR DEVICE - A capacitor insulating film for use as an insulating film sandwiched between two electrodes is made of a crystal containing a hafnium element in a titanium site in place of a part of titanium elements contained in a crystal of a strontium titanate or barium strontium titanate.

2010-07-15

20100176432

Memory Cells, Methods Of Forming Dielectric Materials, And Methods Of Forming Memory Cells - Some embodiments include memory cells. The memory cells may include a tunnel dielectric material, a charge-retaining region over the tunnel dielectric material, crystalline ultra-high k dielectric material over the charge-retaining region, and a control gate material over the crystalline ultra-high k dielectric material. Additionally, the memory cells may include an amorphous region between the charge-retaining region and the crystalline ultra-high k dielectric material, and/or may include an amorphous region between the crystalline ultra-high k dielectric material and the control gate material. Some embodiments include methods of forming memory cells which contain an amorphous region between a charge-retaining region and a crystalline ultra-high k dielectric material, and/or which contain an amorphous region between a crystalline ultra-high k dielectric material and a control gate material.

2010-07-15

20100176433

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a pair of select gate structures which are opposed to each other and which are formed in a select transistor formation area, each of the select gate structures including a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film, and a pair of memory cell gate structure groups which are formed in a pair of memory cell formation areas between which the select transistor formation area is interposed and each of which has a plurality of memory cell gate structures arranged at the same pitch, the pair of select gate structures having sides which are opposed to each other, and at least the upper portion of each of the opposed sides of the select gate structures being inclined.

2010-07-15

20100176434

DATA STORAGE STRUCTURE, MEMORY DEVICE AND PROCESS FOR FABRICATING MEMORY DEVICE - A memory device is described, including a substrate, data storage structures over the substrate, control gates over the data storage structures, and a dielectric layer between the data storage structures and the control gates, wherein each data storage structure includes a lower part and an upper part narrower than the lower part. A process for fabricating the memory device is also described, wherein formation of the data storage structures includes recessing portions of a data storage layer to form respective upper parts of the data storage structures and then dividing the recessed portions of the data storage layer to form respective lower parts of the data storage structures.

2010-07-15

20100176435

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR - First gate electrodes of memory cell transistors are formed in series with each other on a semiconductor substrate. A second gate electrode of a first selection transistor is formed adjacent to one end of the first electrodes. A third gate electrode of a second selection transistor is formed adjacent to the second electrode. A fourth gate electrode of a peripheral transistor is formed on the substrate. First, second, and third sidewall films are formed on side surfaces of the second, third, and fourth gate electrodes, respectively. A film thickness of the third sidewall film is larger than that of the first and second sidewall films. A space between the first electrode and the second electrode is larger than a space between the first electrodes, and a space between the second electrode and the third electrode is larger than a space between the first electrode and the second electrode.

2010-07-15

20100176436

MEMORY DEVICES - A memory device is provided. The memory device includes a first control gate, a second control gate, a plurality of first charge storage elements, a plurality of second charge storage elements and a semiconductor. The plurality of first charge storage elements is beside the first control gate, and each of the first charge storage elements is located on the different side of the first control gate. The plurality of second charge storage elements is beside the second control gate. The semiconductor is located between the first and second control gates.

2010-07-15

20100176437

MEMORY ARRAY AND METHOD FOR MANUFACTURING AND OPERATING THE SAME - The invention provides a memory array. The memory array comprises a substrate, a plurality of word lines, a charge trapping structure, a plurality of trench channels and a plurality of bit lines. The word lines are located over the substrate and the word lines are parallel to each other. The charge trapping structure covers a surface of each of the word lines. The trench channels are located over the substrate and the word lines and the trench channels are alternatively arranged and each trench channel is separated from the adjacent word lines by the charge trapping structure. The bit lines are located over the word lines and each bit line is across over each of the word lines and each trench channel is electrically coupled to the bit lines.

2010-07-15

20100176438

DEPLETION-MODE CHARGE-TRAPPING FLASH DEVICE - A memory device includes a plurality of semiconductor lines, such as body-tied fins, on a substrate. The lines including buried-channel regions doped for depletion mode operation. A storage structure lies on the plurality of lines, including tunnel insulating layer on the channel regions of the fins, a charge storage layer on the tunnel insulating layer, and a blocking insulating layer on the charge storage layer. A plurality of word lines overlie the storage structure and cross over the channel regions of the semiconductor lines, whereby memory cells lie at cross-points of the word lines and the semiconductor lines.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device includes: a first layer; a second layer; a columnar structural unit; and a side portion. The second layer is provided on a major surface of the first layer. The columnar structural unit is conductive and aligned in the first layer and the second layer to pass through the major surface. The side portion is added to a side wall of the columnar structural unit on the second layer side of the major surface.

2010-07-15

20100176441

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREFOR - In a nonvolatile semiconductor memory device of the method which enables a single cell to store more than or equal to 2-bit information, it is possible to prevent wire failure and ensure high operation reliability. The nonvolatile semiconductor memory device

2010-07-15

20100176442

STRUCTURES CONTAINING TITANIUM SILICON OXIDE - A dielectric containing a titanium silicon oxide film disposed in an integrated circuit and a method of fabricating such a dielectric provide a dielectric for use in a variety of electronic devices. Embodiments include a dielectric containing a titanium silicon oxide film arranged as one or more monolayers. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectrics containing a titanium silicon oxide film, and methods for forming such structures.

2010-07-15

20100176443

Semiconductor Device - Provided is a semiconductor device in which on-resistance is largely reduced. In a region (

2010-07-15

20100176444

POWER MOSFET AND METHOD OF FABRICATING THE SAME - A power MOSFET including a substrate of first conductivity type, an epitaxial layer of first conductivity type on the substrate, a body layer of second conductivity type in the epitaxial layer, a first insulating layer, a second insulating layer, a first conductive layer and two source regions of first conductivity type is provided. The body layer has a first trench therein. The epitaxial layer has a second trench therein. The second trench is below the first trench, and the width of the second trench is much smaller than that of the first trench. The first insulating layer is at least in the second trench. The first conductive layer is in the first trench. The second insulating layer is at least between the sidewall of the first trench and the first conductive layer. The source regions are disposed in the body layer beside the first trench respectively.

2010-07-15

20100176445

Metal schemes of trench MOSFET for copper bonding - A trench MOSFET with improved metal schemes is disclosed. The improved contact structure applies a buffer layer to minimize the bonding damage to semiconductor when bonding copper wire upon front source and gate metal without additional cost.

2010-07-15

20100176446

MOSFET with source contact in trench and integrated schottky diode - A trench semiconductor power device with integrated Schottky diode is disclosed. P+ regions and n+ source regions are alternately arranged in mesa and on top of trench sidewall along stripe source-body contact area between two adjacent trenches. By employing this structure, cell density increased remarkably without increasing contact resistance because top portion of gate trench sidewall is provided as source-body contact area.

2010-07-15

20100176447

SEMICONDUCTOR DEVICE - Provided is a semiconductor device in which on-resistance is largely reduced. The semiconductor device includes an n type epitaxial layer (

2010-07-15

20100176448

Intergrated trench mosfet with trench schottky rectifier - An integrated circuit comprising trench MOSFET having trenched source-body contacts and trench Schottky rectifier having trenched anode contacts is disclosed. By employing the trenched contacts in trench MOSFET and trench Schottky rectifier, the integrated circuit is able to be shrunk to achieve low specific on-resistance for trench MOSFET, and low V

2010-07-15

20100176449

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A semiconductor device, includes: a semiconductor layer including a first semiconductor region of a first conductivity type and a second semiconductor region of the first conductivity type, the second semiconductor region having a first conductivity type impurity concentration lower than a first conductivity type impurity concentration of the first semiconductor region; a source region of a second conductivity type provided on the first semiconductor region; a drain region of the second conductivity type provided on the second semiconductor region; an insulating film provided on the semiconductor layer between the source region and the drain region; a gate electrode provided on the insulating film; and a drift region of the second conductivity type provided in a surface side portion of the semiconductor layer between the gate electrode and the drain region, the drift region being in contact with the drain region and having a second conductivity type impurity concentration lower than a second conductivity type impurity concentration of the drain region.

2010-07-15

20100176450

STRUCTURE AND METHOD OF FORMING A TRANSISTOR WITH ASYMMETRIC CHANNEL AND SOURCE/DRAIN REGIONS - A semiconductor structure is described. The structure includes a semiconductor substrate having a conductive gate abutting a gate insulator for controlling conduction of a channel region; and a source region and a drain region associated with the conductive gate, where the source region includes a first material and the drain region includes a second material, and where the conductive gate is self-aligned to the first material and the second material. In one embodiment, the first material includes Si and the second material includes SiGe. A method of forming a semiconductor structure is also described. The method includes forming a pad layer on a top surface of a SOI layer of a semiconductor substrate; patterning the pad layer and a portion of the SOI layer for forming a SiGe layer; epitaxially growing the SOI layer for forming a Si layer and a SiGe layer adjacent to a sidewall of the SOI layer; selectively pulling a portion of the pad layer; forming a gate dielectric of a portion of the SiGe layer and the SOI layer; forming a gate conductor over the gate dielectric; removing the remaining of the pad layer; forming a source region in at least one of the SOI layer and the SiGe layer; and forming a drain region in at least one of the SOI layer and the SiGe layer.

2010-07-15

20100176451

Semiconductor - A memory device includes an insulation layer, an active pattern, a gate insulation layer and a gate electrode. The insulation layer is formed on a substrate. The active pattern is formed on the insulation layer, and includes two protrusions and a recess between the protrusions. The active pattern includes a first impurity region and a second impurity region at upper portions of the protrusions distal from the substrate, respectively, and a base region at the other portions serving as a floating body for storing data. The gate insulation layer is formed on a surface of the active pattern. The gate electrode is formed on the gate insulation layer, and surrounds a lower portion of the active pattern and partially fills the recess.

2010-07-15

20100176452

LATERAL DRAIN MOSFET WITH IMPROVED CLAMPING VOLTAGE CONTROL - A lateral MOSFET having a substrate, first and second epitaxial layers grown on the substrate and a gate electrode formed on a gate dielectric which in turn is formed on a top surface of the second epitaxial layer. The second epitaxial layer comprises a drain region which extends to a top surface of the epitaxial layer and is proximate to a first edge of the gate electrode, a source region which extends to a top surface of the second epitaxial layer and is proximate to a second edge of the gate electrode, a heavily doped body under at least a portion of the source region, and a lightly doped well under the gate dielectric located near the transition region of the first and second epitaxial layers. A PN junction between the heavily doped body and the first epitaxial region under the heavily doped body has an avalanche breakdown voltage that is substantially dependent on the doping concentration in the upper portion of the first epitaxial layer that is beneath the heavily doped body.

2010-07-15

20100176453

LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH BUILT-IN SHALLOW TRENCH ISOLATION IN BACK GATE LAYER - A semiconductor wafer structure for manufacturing integrated circuit devices includes a bulk substrate; a lower insulating layer formed on the bulk substrate, the lower insulating layer formed from a pair of separate insulation layers having a bonding interface therebetween; an electrically conductive layer formed on the lower insulating layer, the electrically conductive layer further having one or more shallow trench isolation (STI) regions formed therein; an etch stop layer formed on the electrically conductive layer and the one or more STI regions; an upper insulating layer formed on the etch stop layer; and a semiconductor layer formed on the upper insulating layer. A subsequent active area level STI scheme, in conjunction with front gate formation over the semiconductor layer, is also disclosed.

SEMICONDUCTOR DEVICE HAVING INSULATED GATE FIELD EFFECT TRANSISTORS AND METHOD OF FABRICATING THE SAME - A CMOSFET is composed of a P-channel MOSFET and an N-channel MOSFET formed on a silicon substrate. The P-channel MOSFET is formed a first gate insulating film, a first hafnium layer and a first gate electrode which are stacked on the silicon substrate. The N-channel MOSFET is formed a second gate insulating film, a second hafnium layer and a second gate electrode which are stacked on the silicon substrate. A surface density of the second hafnium layer is lower than a surface density of the first hafnium layer.

2010-07-15

20100176456

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate including a P-type semiconductor region, and an N channel MOSFET formed in the P-type semiconductor region, the N channel MOSFET including an insulating film of silicon oxide film or silicon oxynitride film formed on the semiconductor substrate, a gate insulating film including hafnium and formed on the insulating film, a lanthanum oxide film having a film thickness not larger than a predetermined value and formed between the gate insulating film and insulating film, and a gate electrode including a titanium nitride film having a N/Ti atomic ratio less than 1.

2010-07-15

20100176457

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first insulated-gate field-effect transistor which is disposed on a semiconductor substrate having an element formation plane in a (110) plane direction, and which has a channel length direction in a direction, a second insulated-gate field-effect transistor which is disposed on the semiconductor substrate, has a channel length direction in the direction, and neighbors the first insulated-gate field-effect transistor in the channel length direction, and a first liner insulation film which is provided in a manner to cover the first and second insulated-gate field-effect transistors, the first liner insulation film including a piezomaterial, having a positive expansion coefficient, and applying a compressive stress by operation heat to the first and second insulated-gate field-effect transistors in the channel length direction.

2010-07-15

20100176458

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A gate insulating film is formed on a main surface of a substrate in which an element isolation region is formed. A metal film is formed on the gate insulating film. A silicon film is formed on the metal film. A gate electrode of a MIS transistor composed of a stacked structure of the silicon film and metal film is formed on an element region and a high-resistance element composed of a stacked structure of the silicon film and metal film is formed on the element isolation region by patterning the silicon film and metal film. An acid-resistant insulating film is formed on the side of the gate electrode. The metal film of the high-resistance element is oxidized. A diffused layer of the MIS transistor is formed in the substrate.

2010-07-15

20100176459

ASSEMBLY OF NANOSCALED FIELD EFFECT TRANSISTORS - The present invention relates to vertical nanowire transistors with a wrap-gated geometry. The threshold voltage of the vertical nanowire transistors is controlled by the diameter of the nanowire, the doping of the nanowire, the introduction of segments of heterostructures in the nanowire, the doping in shell-structures surrounding the nanowire, tailoring the work function of the gate stack, by strain engineering, by control of the dielectrica or the choice of nanowire material. Transistors with varying threshold voltages are provided on the same substrate, which enables the design of advanced circuits utilizing the shifts in the threshold voltages, similar to the directly coupled field logic.

2010-07-15

20100176460

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device according to one embodiment includes: a semiconductor substrate having first and second regions; a first transistor comprising a first gate insulating film and a first gate electrode thereon in the first region on the semiconductor substrate, the first gate insulating film comprising a first interface layer containing nitrogen atoms and a first high dielectric constant layer thereon; a second transistor comprising a second gate insulating film and a second gate electrode thereon in the second region on the semiconductor substrate, the second gate insulating film comprising a second interface layer and a second high dielectric constant layer thereon, the second interface layer containing nitrogen atoms at an average concentration lower than that of the first interface layer or not containing nitrogen atoms, and the second transistor having a threshold voltage different from that of the first transistor; and an element isolation region on the semiconductor substrate, the element isolation region containing oxygen atoms and isolating the first transistor from the second transistor.

2010-07-15

20100176461

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for easily manufacturing a semiconductor device in which variation in thickness or disconnection of a source electrode or a drain electrode is prevented is proposed. A semiconductor device includes a semiconductor layer formed over an insulating substrate; a first insulating layer formed over the semiconductor layer; a gate electrode formed over the first insulating layer; a second insulating layer formed over the gate electrode; an opening which reaches the semiconductor layer and is formed at least in the first insulating layer and the second insulating layer; and a step portion formed at a side surface of the second insulating layer in the opening.