Experts say the new technology, once in the market, could accelerate the growth of connected devices, which are dependent on lower power consumption and faster speeds.

Experts say the new technology, once in the market, could accelerate the growth of connected devices, which are dependent on lower power consumption and faster speeds.

BENGALURU: Scientists at the Indian Institute of Science (IISc) have devised a method to lay circuits in electronic chips that is both cost-effective and energy-efficient, rare in a country known mainly for its software prowess.

A team of three — Ph D candidate Santanu Talukder and his professors Praveen Kumar and Rudra Pratap — found a way to etch nano-circuits on silicon chips at room temperature, which could potentially accelerate research efforts at the fundamental chip level. Talukder began his doctoral research in 2012.

Nano-circuits, several thousand times thinner than a strand of hair, are the basic building blocks of any high-end device — be it mobile phones, television sets or even aircraft.

Experts say the new technology, once in the market, could accelerate the growth of connected devices, which are dependent on lower power consumption and faster speeds.

"This is a game-changer because this makes the whole patterning technique affordable to a larger audience," said Pratap, chairperson of the Centre for Nano Science and Engineering, IISc, Bengaluru. "Most universities cannot even afford the available techniques for the sake of research."

Currently, electric circuits are etched using two methods: Electron-beam lithography and photolithography. But these, which came about during the semiconductor revolution in the 1960s, etch the circuit on polymer. The IISc team has devised a way to do the same on metal, making it easier to etch. The researchers outlined their technology in a paper published online by international scientific journal Nature. com on December 4.

"Patterning is one of the hardest tasks. The method we have developed could bring down the cost by a few millions on a single run. Moreover, it is energy-efficient and reduces the operating cost too," said Pratap.

LOWER PATTERNING COST

The team pegs the current patterning cost at Rs 2.5-3 crore, which they expect could drop to Rs 10-25 lakh with their technology. Pratap estimated that the completed product will be in the market in two years.

"We certainly want to market it," said Kumar. "But before that, we want to make this more user-friendly and develop the technology further. We are also looking for funding from the government."

Currently, companies such as Intel, Qualcomm and MediaTek incorporate nano-circuits in the chips they manufacture. All large companies are researching to pack more capacity into the chips even as they aim to reduce chip size. This new pattern of drawing circuits could give them some time until the former technology matures.

The team filed for a patent in December 2014. "The science is all sorted out, but the tech and engineering needs to be done," said Pratap.

"Nano-electronics is a very promising field," said Chinnu Senthilkumar, chief technology officer at Exfinity Ventures, the venture capital firm floated by ex-Infosys veterans Mohandas Pai and V Balakrishnan. "If this method actually works, it can be a game-changer in the Internet of Things industry due to the industry’s need for low power and small form requirements."

Senthilkumar holds nine patents in the domain of semiconductors and was formerly employed with Intel, Texas Instruments and SanDisk.