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According to Synopsys, IC Compiler
2007.03 can deliver a 35% runtime
improvement over previous editions without trading off quality of results in its
fastest operating mode. Coupled with
improved capacity approaching 10 million
gates on 16-Gbyte platforms, it lets users
take on larger block partitions.

The release adds early access to integrated hierarchical design planning,
enabling users to efficiently tackle
designs in the 100 million-gate range. Its
physical feasibility flow enhances productivity by letting users quickly generate and
analyze multiple trial floorplans to determine the best starting point for detailed
implementation.

These users can't afford the scheduling
impact of sequential optimization or
accept less accurate merging techniques, like those in other place-and-route tools. The advanced designs also
benefit from IC Compiler's signoff-driven
timing closure, which is now available as
a production capability.

For emerging 45-nm designs, IC Compiler now includes 45-nm placement
and routing design rules. It also meets
the new requirements for lithography
compliance and CMP-related (chemical-mechanical polishing) metal uniformity.