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Senior DFT Engineer

Overview

Role :Will be involved in all aspects of ASIC Implementation including low power synthesis, low power back end implementation, design for test (DFT) of complex SOC development flow including DFT architecture, Boundary Scan implementation, Memory BIST insertion, Scan insertion, ATPG pattern generation, verification of patterns and post silicon ATE supportJob Requirements :Knowledge of high speed synthesis preferably (RTL compiler from Cadence).DFT on complex SOC designs using industry standard DFT flows, preferably from Mentor GraphicsHands-on experience on ASIC/SOC design, verification flows and methodologiesKnowledge of Boundary scan/JTAG/BSDLSolid knowledge of Scan and BIST is essentialUnderstanding with Verilog/VHDLFamiliarity with Scan insertion/tracingATPG, stuck-at, at-speed coverage reporting/enhancementPattern/vector generationDebugging skills with timing simulationsFormal verification and Lint tools experience desirableInterface with RTL integration, PD and FV engineers to resolve/debug issuesExpertise in scripting language such as PERL, TCL is highly desirableExperience in silicon bringup on ATEKnowledge of ATE based silicon qualification and characterizationDebugging skills for convergence between DFT/functional vectors and ATE vectorsEssential Requirements:• BTech/MTech/MS in EE or equivalent with 10+ years of experienceVery good communication skillsOutstanding analytical and critical thinking skills.Should lead a minimum of 10-15 team in a positive directionBe a good contributor to the organization & a team player