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Abstract

This invention is used in a processor using cache memory to make it possible to recover from cache data parity errors. For the purpose of this description the processor is using a store through cache which can be invalidated by a store from another processor or from an I/O device.

Country

United States

Language

English (United States)

This text was extracted from an ASCII text file.

This is the abbreviated version, containing approximately
54% of the total text.

Fault-Tolerant Cache

This
invention is used in a processor using cache memory
to make it possible to recover from cache data parity errors. For the
purpose of this description the processor is using a store through
cache which can be invalidated by a store from another processor or
from an I/O device.

During normal
operation all processor fetches are done from the
cache. The data is loaded into the
destination register from the
cache data bus without regard to the data being valid. At the time
data is read from the cache, part of the cache address is used to
access the cache directory contained within the storage control unit.
A compare is done to see if the address fetched actually resides in
the cache. If the address does not
match, a cache miss hold-off line
is raised which is received by all destination registers so the data
is not used. The data is then fetched
from main memory and loaded
into the cache and the destination register.
The cache line is then
marked valid in the cache directory, and the directory data is
updated.

To recover
from cache data errors, the storage control unit
checks parity on all fetches from the cache.
When a parity error is
detected by the storage control unit during a fetch from the cache,
the cache miss hold-off line is again raised.
All destination
registers react to this in the same way as in the previous hold-off
and do not reference the bad data. The
storage control unit will
also raise...