Abstract : The prime concentration was upon both memory and logic subsystem construction. At the present time, nearly 65% of the required wafers for the logic subsystem are co structed and tested; and as normal to worst-case designs, wafer performance is near the minimum side of the specifications. Both logic and memory subsy tems are well underway in construction, and schedules have bee laid out for the peripheral circuitry to be added to the memory. A complete re-scheduling of both the memory and the logic subsystems was done since the original planning periods were essentially completed. (Author)