Measurement methods for characterizing the electrical properties of directly bonded Si/Si n/n-type or p/p-type interfaces are presented. The density of interface states in the bandgap of the semiconductor and the density of interface charges at the bonded interface are determined from measurements of current and capacitance vs applied voltage.
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The propagation loss of single-mode optical waveguides in multiple implant SIMOX wafers has been used to assess the quality of the superficial silicon layer. Increased attenuation can be correlated to the creation of thermal and new donors. Some higher loss wafers also show interfacial roughness which gives rise to additional scattering losses.
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A priori crystalline silicon-on-insulator-on-silicon structures were fabricated with 8 masks. With this three-dimensional CMOS technology, three high-quality transistor channels are stacked vertically. Dual-gate PMOS transistors on top of NMOS transistors deliver the same current for the same channel width. 3D CMOS test circuits have been built with a footprint of one third of their 2D bulk counte...
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Different isolation features have been proposed for SOI: LOCOS, mesa, reoxidized mesa. Mesas allow a low width loss and a high integration density if an anisotropic etch is used. However, some isotropic step is necessary for the gate etch to avoid residues. We present here the Rounded Edge Mesa (REM) which allows an accurate control of the gate dimensions without residues. Characteristics of devic...
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The growth of modulation-doped heterojunction-field effect transistor structures with a pseudomorphic InGaAs quantum well for high frequency device applications is reported. The In-concentrations are varied between 10% and 30%. The quantum well widths range from 8 nm to 16 nm. Depending on the sheet concentration one or two strong photoluminescence transitions with a high-energy cutoff are observe...
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A modelling approach and an experimental characterization of various GaAs/GaAlAs HBT parasitic effects are presented. They include the emitter base offset voltage, resistance effects, recombination currents and the outdiffusion of the p-dopant.
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In this paper we describe the design, simulation and measured performance of high efficiency power HBTs. Devices with emitter lengths of 1.7mm operated under pulse bias (0.2μs, 1% duty cycle) can deliver output powers at 1 dB gain compression of up to 8W at 4GHz. The associated gain is 5dB and the peak power added efficiency around 40%. This represents the highest power reported for a powe...
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A HBT self-aligned technology with a perpendicular side-wall mesa has been adopted in microwave HBT fabrication by virtue of a high selectivity chemical wet etchant. Principal features and technological processes of the method are discussed. The gap of ∼0.1μm between the emitter mesa edge and base contact metallization edge has been formed repeatedly by the method. The experimental...
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In this paper we report on invertible DHBTs fabricated on GaInAsP/InP. Localized Zn diffusion allowed for practically equal active transistor areas in the forward and inverse mode. Transit frequencies up to 6 GHz with collector currents over 100mA could be demonstrated on these devices. As an application, three transistors were monolithically integrated to form a laser driver circuit showing modul...
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Permeable Base Transistors (PBTs) with gate periodicity down to 0.6 μm have been fabricated using a MOS technology process. Both static and microwave measurements have been performed. The results obtained on the smallest structures are presented and compared with two-dimensional simulations.
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For high-speed complementary logic using permeable base transistors (PBTs) p-channel devices are needed. For the first time the simulation and fabrication of this kind of transistors are reported. Two-dimensional computer modeling indicate that in general p-channel PBTs reach up to 75% of the transit frequency of their n-channel counterparts. First experimental devices with 0.3??m finger size exhi...
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A permeable base transistor (PBT) has been fabricated by local implantation of 59Co into Si(100) with subsequent rapid thermal annealing and epitaxial growth of silicon by LPVPE. Transmission electron microscopy shows abrupt interfaces between the buried CoSi2 and the adjacent silicon. Rutherford backscattering and channeling experiments with a minimum yield of 5.3% for the C...
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A new compact model description of reverse-biased diode characteristics is presented. This model includes tunnelling effects and avalanche breakdown. From comparison with both numerical simulations and measurements it is found that the model gives a good description of the I-V characteristics of reverse-biased diodes.
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Shrinking VLSI geometries have resulted in increasingly non-planar structures and current flows, necessitating lateral as well as vertical information on dopant distribution for device design, modelling and optimisation. Continuing demand for improved vertical resolution (1-10nm) has led to improvements in existing 1D dopant profiling techniques: new 2D techniques of reasonable resolution (20-25nm...
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An integrated model for the simulation of the exact thermal behaviour of a silicon wafer during optical rapid thermal processing coupled to the microscopic thermal processing effects of dopant diffusion and oxidation is presented.
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Time resolved reflectivity is first applied to the measurement of the solid phase epitaxial growth rate of As+ (60 keV, 4.1015cm-2) implanted (100) Si wafers and then to the study of platinum silicide formation when samples of platinum films deposited on top of silicon wafers are annealed in a rapid thermal processor. The thermal cycles consist of a fast heating ph...
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