BARCELONA, Spain, Mobile World Congress -- March 2, 2015 – At the Mobile World Congress 2015 today, Altera and China Mobile demonstrated jointly a Centralized/Coordinated/Cloud Radio Access Network (C-RAN) platform targeting the next generation of virtualized 5G wireless networks. This approach will dramatically improve the user experience at the edge of cells, achieving much higher channel capacity and spectrum efficiency, reduce the network power consumption, and support flexible and agile network deployments. C-RAN has the potential to create tremendous new business models for network operators, and numerous new applications for the end users of 5G wireless networks.(more)

Altera today announced Microsoft is using Altera Arria® 10 FPGAs (field programmable gate arrays), to achieve compelling performance-per-Watt in data center acceleration based on CNN (convolutional neural network) algorithms. These algorithms are frequently used for image classification, image recognition, and natural language processing. Altera is presenting how FPGAs are accelerating data center search at two key industry events this week: FPGA 2015ACM/SIGDA in Monterey, California, on February 23 and the Linley Group Data Center Conference in San Jose, California, on February 25.(more)

Altera will showcase at Embedded World 2015 how its SoCs are enabling developers to create highly differentiated, feature-rich embedded systems. Altera SoCs will be featured prominently throughout the exhibit halls both in Altera’s booth and in multiple partner booths. Highlights in Altera’s booth (Hall 5 Stand 277) include the unveiling of Altera’s second-generation SoC family, Arria® 10 SoCs, the industry’s only 20 nm SoC FPGA family. Also on display will be application-specific demonstrations of low-cost, low-power 28 nm Cyclone® V SoCs enabling higher performance, lower power and more secure embedded, automotive and industrial applications.(more)

Altera is demonstrating leading-edge automotive solutions based on its field-programmable gate array (FPGA) technology at CAR-ELE JAPAN, a premier international automotive electronics exposition taking place January 14 to 16, 2014, at the Tokyo Big Sight, in Booth West 8-49. The demonstrations will cover advanced programmable logic solutions for advanced driver assistance systems (ADAS), video scaling and graphic acceleration in car infotainment systems, and use of FPGAs to increase efficiency and performance of electric vehicle powertrains. (more)

Altera today announced that its SoC field-programmable gate arrays (FPGAs) have been selected for use in Audi’s advanced driver assistance system (ADAS) targeted for mass production. Audi, a self-driving car technology leader, and Austrian high-tech company TTTech, the core-development partner for Audi’s central driver assistance control unit zFAS, chose the Altera® Cyclone® V SoC FPGA for its ability to increase system performance and enable the differentiated features Audi requires for piloted driving and parking not available with application specific standard product (ASSP) solutions. (more)

Altera today announced it is demonstrating in silicon DDR4 memory interfaces operating at an industry-leading 2,666 Mbps. Altera’s Arria® 10 FPGAs and SoCs are the industry’s only FPGAs available today that support DDR4 memory at these data rates, delivering a 43 percent improvement in memory performance over previous generation FPGAs and a 10 percent improvement in memory performance over competing 20 nm FPGAs. Hardware designers today can use the latest Quartus® II software v14.1 to enable 2,666 Mbps DDR4 memory data rates in Arria 10 FPGA and SoC designs. A video demonstration showing robust memory interfaces operating at 2,666 Mbps with margin is available for viewing at www.altera.com/arria10. (more)

Altera today released its Quartus® II software v14.1 featuring expanded support for Arria® 10 FPGAs and SoCs, the FPGA industry’s only devices with hardened floating point DSP blocks and the industry’s only 20 nm SoC FPGAs that integrate ARM processors. Altera’s latest software release provides immediate support for the hardened floating point DSP blocks integrated in Arria 10 FPGAs and SoCs. Users can choose between three unique DSP design entry flows and achieve up to an industry-leading 1.5 TFLOPS of DSP performance. The software also includes several optimizations that improve designer productivity by accelerating Arria 10 FPGA and SoC design time. (more)

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