Sign up to receive free email alerts when patent applications with chosen keywords are publishedSIGN UP

Abstract:

A memory device comprises first and second electrodes with a memory
element and a buffer layer located between and electrically coupled to
them. The memory element comprises one or more metal oxygen compounds.
The buffer layer comprises at least one of an oxide and a nitride.
Another memory device comprises first and second electrodes with a memory
element and a buffer layer, having a thickness of less than 50 Å,
located between and electrically coupled to them. The memory comprises
one or more metal oxygen compounds. An example of a method of fabricating
a memory device includes forming first and second electrodes. A memory,
located between and electrically coupled to the first and the second
electrodes, is formed; the memory comprises one or more metal oxygen
compounds and the buffer layer comprises at least one of an oxide and a
nitride.

Claims:

1. A method of fabricating a memory device, comprising: forming a first
electrode and a second electrode; and forming a memory element and a
buffer layer located between and electrically coupled to the first and
the second electrodes, the memory element comprising one or more metal
oxygen compounds, the buffer layer comprising at least one of an oxide
and a nitride.

2. The method according to claim 1, wherein the buffer layer is formed by
down-stream plasma, plasma sputtering or reactive sputtering.

3. The method according to claim 1, wherein the memory element is formed
by plasma oxidation or thermal oxidation.

4. The method according to claim 1, wherein the buffer layer is located
between and electrically coupled to the memory element and the first
electrode.

5. The method according to claim 1, wherein the buffer layer has a
thickness of less than 50 Å.

6. The method according to claim 1, wherein the buffer layer has a
resistivity of about 10.sup.13.about.10.sup.16 ohm-cm.

7. The method according to claim 4, further comprising forming a second
buffer layer located between and electrically coupled to the memory
element and the second electrode, the second buffer layer comprising at
least one of an oxide and a nitride.

8. The method according to claim 7, wherein the second buffer layer has a
thickness of less than 50 Å

9. The method according to claim 1, wherein the memory element has a
thickness, measured between the first and second electrodes, of 50-1000
Å.

11. The method according to claim 1, wherein the buffer layer comprises
at least one of the following: a tungsten oxide, a titanium oxide, an
aluminum oxide, a zirconium oxide and a silicon nitride.

12. The method according to claim 1, wherein the buffer layer comprises
SiO.sub.2.

13. A method for fabricating a memory device comprising: forming a first
electrode and a second electrode; forming a memory element and a buffer
layer located between and electrically coupled to the first and the
second electrodes; selecting the memory element to comprise at least one
of the following: WOx, NiO, Nb2O5, CuO2,
Ta2O5, Al2O3, CoO, Fe2O3, HfO2,
TiO2, GeTi, SnMnTe, SbTe, Pr1-xCaxMnO3, (Te--Cu/GdOX,
GeSb with Ag.sup.+ or Cu).sup.+; and selecting the buffer layer to
comprise at least one of the following: a tungsten oxide, a titanium
oxide, an aluminum oxide, a zirconium oxide and a silicon nitride.

14. The method according to claim 13, wherein the buffer layer is located
between and electrically coupled to the memory element and the first
electrode.

15. The method according to claim 14, further comprising a second buffer
layer located between and electrically coupled to the memory element and
the second electrode, the second buffer layer comprising at least one of
an oxide and a nitride.

16. The memory device according to claim 13, wherein the memory element
is a programmable resistance memory element.

17. A method of fabricating a memory device comprising: forming a first
electrode; forming a metal oxide resistive random access memory element
located over and electrically coupled to the first electrode; the memory
element comprising at least one of the following: WOx, NiO,
Nb2O5, CuO2, Ta2O5, Al2O3, CoO,
Fe2O3, HfO2, TiO2, Pr1-xCaxMnO3,
(Te--Cu/GdOX, GeSb with Ag.sup.+ or Cu.sup.+); forming a buffer layer
located over and electrically coupled to the memory element; and forming
a second electrode located over and contacting the buffer layer.

18. The method according to claim 17, wherein the buffer layer has a
resistivity of about 10.sup.13.about.10.sup.16 ohm-cm.

19. The method according to claim 17, further comprising forming a second
buffer layer located between and electrically coupled to the memory
element and the first electrode, the second buffer layer comprising at
least one of an oxide and a nitride.

20. The method according to claim 19, wherein the second buffer layer has
a thickness of less than 50 Å.

21. The method according to claim 17, wherein the memory element has a
thickness, measured between the first and second electrodes, of 50-1000
Å.

22. The method according to claim 17, further comprising selecting the
buffer layer to comprise at least one of the following: a tungsten oxide,
a titanium oxide, an aluminum oxide, a zirconium oxide, a silicon nitride
and a titanium nitride.

23. The method according to claim 17, further comprising selecting the
buffer layer to comprise SiO.sub.2.

24. The method according to claim 17, wherein the memory element is a
programmable resistance random access memory element.

[0002] The present application is related to the following U.S. patent
applications: Resistance Random Access Memory Structure for Enhanced
Retention, U.S. patent application Ser. No. 11/560,723, filed on 16 Nov.
2006, published on 22 May 2008 as publication number US-2008-0116440-A1,
Attorney Docket MXIC 1741-1; and Resistance Memory with Tungsten Compound
and Manufacturing, U.S. patent application Ser. No. 11/955,137, filed on
12 Dec. 2007, published on 11 Dec. 2008 as publication number
US-2008-0304312-A1, Attorney Docket MXIC 1742-2.

BACKGROUND OF THE INVENTION

[0003] 1. Field of the Invention

[0004] The present invention relates to memory devices and methods for
manufacturing high density memory devices, and more particularly to
memory devices having a data storage material based on tungsten-oxygen
compounds.

[0007] Metal-oxide based RRAM can be caused to change resistance between
two or more stable ranges by application of electrical pulses at levels
suitable for implementation in integrated circuits, and the resistance
can be read and written with random access to indicate stored data.

[0008] NiO, TiO2, HfO2, and ZrO2 based RRAM have been
investigated for use as a memory material in memory cells. See, Baek, et
al., "Highly Scalable Non-Volatile Resistive Memory using Simple Binary
Oxide Driven by Asymmetric Unipolar Voltage Pulses", IEDM Technical
Digest pp. 23.6.1-23.6.4, IEEE International Electron Devices Meeting
2004. These memory cells are formed by a non-self-aligned process in a
M-I-M structure, where M is a noble metal acting as an electrode and I is
one of NiO, TiO2, HfO2, and ZrO2. This MIM structure
requires several additional masks and patterning to form the noble metal
electrodes and the memory material, and results in a relatively large
memory cell size.

[0009] CuxO based RRAM has also been investigated for use as a memory
material in memory cells. See, Chen et al., "Non-Volatile Resistive
Switching for Advanced Memory Applications", IEDM Technical Digest pp.
746-749, IEEE International Electron Devices Meeting 2005. The CuxO
material is formed by thermal oxidation of a copper via which acts as the
bottom electrode for the memory cell, while the top electrode consists of
a bi-layer Ti/TiN film that is deposited and etched. This structure
requires several additional masks to form the top and bottom electrodes,
and results in a relatively large memory cell size. Chen et al. disclose
that having a copper bottom electrode complicates erasing of the memory
cell since the applied field during erasing may push copper ions into the
CuxO. Additionally, CuxO has a relatively small resistance
window of 10×.

[0010] Cu--WO3 based RRAM has also been investigated for use as a
memory material in memory cells. See, Kozicki et al., "A Low-Power
Nonvolatile Switching Element Based on Copper-Tungsten Oxide Solid
Electrolyte", IEEE Transactions on Nanotechnology pp. 535-544, Vol. 5,
No. 5, September 2006. Switching elements fabricated using tungsten
metal, a solid electrolyte based on tungsten-oxide and photodiffused
copper, and a copper top electrode are disclosed. The switching element
is formed by tungsten-oxide grown or deposited on tungsten material, a
layer of Cu formed on the tungsten-oxide and the Cu photodiffused into
the tungsten-oxide to form the solid electrolyte, and a Cu layer is
formed and patterned over the solid electrolyte to act as a top
electrode. The switching element changes resistance by applying a bias
voltage to cause electrodeposition of Cu ions from the top electrode into
the solid electrolyte, and states that "a lack of Cu in the top electrode
results in no measurable switching activity" (see page 539, column 1).
This structure thus needs a Cu top electrode, involves several process
steps to form the solid electrolyte, and necessitates bias voltages of
opposite polarities to cause the injection of Cu ions to program and
erase the solid electrolyte.

SUMMARY OF THE INVENTION

[0011] An example of a memory device comprises first and second electrodes
with a memory element and a buffer layer located between and electrically
coupled to the first and second electrodes. The memory element comprises
one or more metal oxygen compounds. The buffer layer comprises at least
one of an oxide and a nitride. In some example is the buffer layer has a
thickness of less than 50 Å. In some example is the memory element
comprises one or more tungsten oxygen compounds. In some examples the
buffer layer comprises at least one of the following: SiO2, WO, TiO,
NiO, AlO, CuO, ZrO, Si3N4, and TiN. In some examples memory
element comprises one or more of the following: WOx, NiO,
Nb2O5, CuO2, Ta2O5, Al2O3, CoO,
Fe2O3, HfO2, TiO2, SrTiO3, SrZrO3,
(BaSr)TiO3, GeTi, SnMnTe, SbTe, Pr1-xCaxMnO3, (Te--Cu/GdOX,
GeSb with Ag.sup.+ or Cu.sup.+).

[0012] A second example of a memory device comprises a first electrode and
a second electrode with a memory element and a buffer layer located
between and electrically coupled to the first and the second electrodes.
The memory comprises one or more metal oxygen compounds. The buffer layer
has a thickness of less than 50 Å.

[0013] An example of a method of fabricating a memory device is carried
out as follows. A first electrode and a second electrode are formed. A
memory, located between and electrically coupled to the first and the
second electrodes, is formed; the memory comprises one or more metal
oxygen compounds and the buffer layer comprises at least one of an oxide
and a nitride. In some examples the buffer layer is located between and
electrically coupled to the memory element and the first electrode. In
some examples the buffer layer has a thickness of less than 50 Å. In
some examples the buffer layer has a resistivity of about
1013˜1016 ohm-cm. In some examples a second buffer layer
is formed between and electrically coupled to the memory element and the
second electrode, the second buffer layer comprising at least one of an
oxide and a nitride.

[0014] Advantageously, the present invention improves the performance,
including data retention and cycle endurance, of a resistive memory
structure.

[0015] The structures and methods of the present invention are disclosed
in the detailed description below. This summary does not purport to
define the invention. The invention is defined by the claims. These and
other embodiments, features, aspects, and advantages of the technology
can be understood with regard to the following description, appended
claims and accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The invention will be described with respect to specific
embodiments thereof, and reference will be made to the drawings, in
which:

[0017] FIG. 1 is a simplified cross-sectional view of an example of a
resistive memory structure in accordance with the present invention with
a barrier layer between the bottom electrode and the memory cell.

[0018]FIG. 2 is a simplified cross-sectional view of another example of a
resistive memory structure similar to that of FIG. 1 but where the buffer
layer is between the memory cell and the top electrode.

[0019]FIG. 3 is a simplified cross-sectional view of a further example of
a resistive memory structure similar to that of FIG. 1 including a buffer
layer between the bottom electrode and the memory cell as in FIG. 1 and a
buffer layer between the top electrode and the memory cell as in FIG. 2.

[0020]FIG. 4 is a graph of resistivity versus retention time for a
resistive memory structure of the type not including a buffer layer.

[0021] FIG. 5 is a graph of resistivity versus retention time for a
resistive memory structure made according to the invention showing the
improved data retention over the data retention illustrated in FIG. 4.

[0022]FIG. 6 is a graph of resistivity versus cycle time for a memory
structure of the type not including a buffer layer.

[0023]FIG. 7 is a graph of resistivity versus cycle time for a resistive
memory structure made according to the invention showing the improved
cycle endurance over the cycle endurance illustrated in FIG. 6.

[0024] FIG. 8 is a graph of resistivity versus read disturb for a
resistive memory structure made according to the invention showing that
it exhibits very good read disturb characteristics in both the on state
and the off state.

[0025]FIG. 9 is a simplified block diagram of an integrated circuit
including resistive memory structures.

DETAILED DESCRIPTION

[0026] A description of structural embodiments and methods of the present
invention is provided with reference to FIGS. 1-9. It is to be understood
that there is no intention to limit the invention to the specifically
disclosed embodiments but that the invention may be practiced using other
features, elements, methods and embodiments. Like elements in various
embodiments are commonly referred to with like reference numerals.

[0027] FIG. 1 is a simplified cross-sectional view of a first example of a
resistive memory structure 10. Structure 10 includes a substrate 11 upon
which an AlCu stack 12 is formed. A dielectric layer 14, typically
silicon dioxide, is formed over stack 12. A bottom electrode 16 extends
from stack 12 completely through dielectric layer 14. Bottom electrode 16
is an electrically conductive element. For example, bottom electrode 16
may be a drain terminal of an access transistor or a terminal of a diode.
A buffer layer 18 is formed by, for example, down-stream plasma, plasma
sputtering or reactive sputtering onto dielectric layer 14 and bottom
electrode 16. Buffer layer 18 has a thickness of less than 50 Å; the
advantages accruing from the use of buffer layer 18 will be discussed
below. Buffer layer 18 comprises at least one of an oxide and a nitride.
For example, buffer layer 18 may comprise at least one of the following:
SiO2, WO, TiO, NiO, AlO, CuO, ZrO, Si3N4, and TiN. Buffer
layer 18 preferably exhibits a resistivity of about
1013˜1016 ohm-cm and preferably has a thickness of less
than 5 nm (50 Å). Buffer layer 18 may be formed by, for example,
physical vapor deposition or chemical vapor deposition methods.

[0028] A memory element layer 20, having a thickness of 50-1000 Å, is
deposited on buffer layer 18. Memory element layer 20 comprises one or
more metal-oxygen compounds, especially tungsten-oxygen compounds
WxOy, for example one or more of WO3, W2O5,
WO2. In some cases, such as when plasma oxidation or thermal
oxidation is used to form memory element layer 20, the result can be a
number of different tungsten-oxygen compounds. In one example memory
element layer 20 comprises WO3/W2O5/WO2 and has a
thickness of about 140 Å. A top electrode 22 is formed on memory
element layer 20. Electrodes 16, 22 are typically a metal such as
tungsten or AlCu. The portions of the bottom and top electrodes 16, 22
that are aligned define a memory cell region 24 therebetween. The portion
of memory element layer 20 situated within memory cell region 24
constitutes a memory element 26 electrically coupled to bottom and top
electrodes 16, 22. Memory element 26 may comprise one or more of the
following: WOx, NiO, Nb2O5, CuO2, Ta2O5,
Al2O3, CoO, Fe2O3, HfO2, TiO2, SrTiO3,
SrZrO3, (BaSr)TiO3, GeTi, SnMnTe, SbTe,
Pr1-xCaxMnO3, (Te--Cu/GdOX, GeSb with Ag.sup.+ or
Cu.sup.+).

[0029] In operation, voltages applied to the top and bottom electrodes 22,
16 will cause current to flow between the top and bottom electrodes via
memory element 26 and can induce a programmable change in electrical
resistance of the memory element 26, the electrical resistance indicating
a data value stored in the memory element 26. In some embodiments memory
element 26 can store two or more bits of data.

[0030]FIG. 2 is a simplified cross-sectional view of another example of a
resistive memory structure 10 similar to that of FIG. 1 but without
buffer layer 18 but including a buffer layer 19 between memory element 26
and at top electrode 22. FIG. 3 is a simplified cross-sectional view of a
further example of a resistive memory structure 10 including a buffer
layer 18 between bottom electrode 16 and memory element 26 as in FIG. 1
and a buffer layer 19 between top electrode 22 and the memory element 26
as in FIG. 2.

[0031] Resistive memory structure 10 can be manufactured using
conventional back-end-of-line W-plug processing techniques. A single mask
can be used to form both buffer layer 19 and top electrode 22.

[0032] The use of one or both of buffer layers 18, 19 helps to improve the
performance of resistive memory structure 10. This improvement in
performance will be demonstrated with reference to FIGS. 4-8. The
structure of FIG. 1 was used to develop the results seen at FIGS. 5, 7
and 8. The test structure had the following characteristics: bottom
electrode 16 was made of W and had an average diameter of about 200 nm;
top electrode 22 was made of Al and had an average width of about 500 nm;
memory element layer 20 was made of WOx and a thickness of about 140
Å; buffer layer 18 was made of SiO2 and had a thickness of about
2 nm. The results shown at FIGS. 4 and 6 are for a resistive memory
structure substantially identical to the test structure but without any
buffer layers, referred to below as the conventional resistive memory
structure.

[0033]FIG. 4 is a graph of resistivity versus retention time for the
conventional resistive memory structure in both the on state and the off
state. It can be seen that the resistivity, especially in the on state,
increases relatively quickly over time, time being plotted on a
logarithmic scale. In contrast, the plot of resistivity versus retention
time for resistive memory structure 10 is seen in FIG. 5 to be
essentially flat, a substantial improvement over the conventional
resistive memory structure used to create the graph of FIG. 4.

[0034]FIG. 6 is a graph of resistivity versus cycle time for the
conventional resistive memory structure. Graphs for both the on state and
the off state show significant increases in the resistivity over cycle
time. In contrast, the graph of FIG. 7 of resistivity versus cycle time
for resistive memory structure 10 shows a relatively flat resistivity
versus cycle time plots for both the on state and the off state. This
indicates substantially improved cycle endurance for resistive memory
structure 10 over the cycle endurance of the conventional resistive
memory structure used to create the graph in FIG. 6.

[0035] FIG. 8 is a graph of resistivity versus read disturb for resistive
memory structure 10 showing that the resistivity of structure 10 exhibits
very good read disturb characteristics in both the on state and the off
state. Read disturb refers to the gain or loss of resistance of memory
element 26 resulting from reading the state of the memory element 26.

[0036]FIG. 9 is a simplified block diagram of an integrated circuit 110
including a memory array 112 implemented using resistive memory
structures 10. A word line decoder 114 having read, set and reset modes
is coupled to and in electrical communication with a plurality of word
lines 116 arranged along rows in the memory array 112. A bit line
(column) decoder 118 is in electrical communication with a plurality of
bit lines 120 arranged along columns in the array 112 for reading,
setting, and resetting memory element 26 in array 112. Addresses are
supplied on bus 122 to word line decoder and drivers 114 and bit line
decoder 118. Sense amplifiers and data-in structures in block 124,
including voltage and/or current sources for the read, set, and reset
modes are coupled to bit line decoder 118 via data bus 126. Data is
supplied via a data-in line 128 from input/output ports on integrated
circuit 110, or from other data sources internal or external to
integrated circuit 110, to data-in structures in block 124. Other
circuitry 130 may be included on integrated circuit 110, such as a
general purpose processor or special purpose application circuitry, or a
combination of modules providing system-on-a-chip functionality supported
by array 112. Data is supplied via a data-out line 132 from the sense
amplifiers in block 124 to input/output ports on integrated circuit 110,
or to other data destinations internal or external to integrated circuit
110.

[0037] A controller 134 implemented in this example, using a bias
arrangement state machine, controls the application of bias arrangement
supply voltages and current sources 136, such as read, program, erase,
erase verify and program verify voltages and/or currents. Controller 134
may be implemented using special-purpose logic circuitry as known in the
art. In alternative embodiments, controller 134 comprises a
general-purpose processor, which may be implemented on the same
integrated circuit to execute a computer program to control the
operations of the device. In yet other embodiments, a combination of
special-purpose logic circuitry and a general-purpose processor may be
utilized for implementation of controller 134.

[0038] An exemplary formation method for WxOy uses a PVD
sputtering or magnetron-sputtering method with reactive gases of Ar,
N2, O2, and/or He, etc. at a pressure of 1 mTorr˜100
mTorr, using a target of WxOy. The deposition is usually
performed at room temperature. A collimater with an aspect ratio of
1˜5 can be used to improve the fill-in performance. To improve the
fill-in performance, the DC bias of several tens of volts to several
hundreds of volts is also used. If desired, DC bias and the collimater
can be used simultaneously.

[0039] A post-deposition annealing treatment in vacuum or in an N2
ambient or O2/N2 mixed ambient is optionally performed to
improve the oxygen distribution of metal oxide. The annealing temperature
ranges from 400° C. to 600° C. with an annealing time of
less than 2 hours.

[0040] Yet another formation method uses oxidation by a high temperature
oxidation system, such as a furnace or a rapid thermal pulse ("RTP")
system. The temperature ranges from 200° C. to 700° C. with
pure O2 or N2/O2 mixed gas at a pressure of several mTorr
to 1 atm. The time can range several minutes to hours. Another oxidation
method is plasma oxidation. An RF or a DC source plasma with pure O2
or Ar/O2 mixed gas or Ar/N2/O2 mixed gas at a pressure of
1 mTorr to 100 mTorr is used to oxidize the surface of W. The oxidation
time ranges several seconds to several minutes. The oxidation temperature
ranges from room temperature to 300° C., depending on the degree
of plasma oxidation.

[0041] The invention has been described with reference to specific
exemplary embodiments. Various modifications, adaptations, and changes
may be made without departing from the spirit and scope of the invention.
Accordingly, the specification and drawings are to be regarded as
illustrative of the principles of this invention rather than restrictive,
the invention is defined by the following appended claims. For example, a
transition or protective layer of material could be used between the
buffer layer and one or both of the memory element and an electrode.

[0042] Any and all patents, patent applications and printed publications
referred to above are incorporated by reference.