The National Institute of Standards and Technology (NIST) is developing single-crystal reference materials for use as critical dimension (CD) reference materials. In earlier work, the reference features on these reference materials have been patterned in the device layer of a silicon-on-insulator (SOI) wafers, with the buried oxide providing electrical isolation. This paper describes a new method ...
View full abstract»

This paper presents work on the analysis of the effect of Joule heating on sheet resistivity measurements using Greek cross test structures. As part of this work, design rules have been derived to minimize the heating effect associated with currents forced during their measurement. To accomplish this, finite-element (FE) simulations were employed to identify the location of heat generation and coo...
View full abstract»

A novel process is presented which produces platinum features using direct UV exposure of the photosensitive organometallic material. The technique reduces the number of process steps involved when creating a metal pattern on a substrate by not requiring photoresist, solvents, or etch processes. In contrast to processes already reported in the literature, the method is compatible with microelectro...
View full abstract»

A novel nondestructive measurement technique is proposed to electrically monitor the depth of a trench etched in silicon for the purpose of process control in a manufacturing environment. A simple bipolar npn transistor can be constructed, the gain of which is shown to relate to the trench depth. The ratio of the injected emitter current to the captured collector current has demonstrated the abili...
View full abstract»

A new test structure for the detection and localization of short and open defects in large-scale integrated intralayer wiring processes is proposed. In the structure, an open-monitoring element in the first metal layer meanders around lines of short-monitoring elements placed in contact with N-type diffusion regions to make the structure compact. The proposed structure allows defective test struct...
View full abstract»

We have developed the world's first large-scale test element group (TEG) with large-scale elements that accurately evaluate SoC (system on chip)-level yield and variation. To enable quick feedback on processing, address decoders on all four sides of the chip and testing programs were also developed. The TEG has a simple structure to examine pure (i.e., not oriented to products) logic-processes, yi...
View full abstract»

This study aims to provide an integrated infrastructure for electrical-based dimensional process-window checking. The proposed infrastructure is comprised of design tools, testing programs, and analytical tools, providing an automatic and hierarchical test vehicle design flow from the design of the test structure to the analysis of the electrical test data. Symbolic parameter representation is ado...
View full abstract»

Integrated varactors are becoming a common feature for many RF designs and in particular RF voltage controlled oscillators (VCOs). Optimization of the quality of both the inductor and the varactor from the VCO core is essential. This work details the characterization and optimization of a number of varactor types available on a typical submicron BiCMOS process. Engineering of the bottom plate of t...
View full abstract»

We present an MOS capacitance-voltage measurement methodology that, contrary to present methods, is highly robust against gate leakage current densities up to 1000 A/cm2. The methodology features specially designed RF test structures and RF measurement frequencies. It allows MOS parameter extraction in the full range of accumulation, depletion, and inversion.
View full abstract»

In this paper, we provide a detailed analysis of overlay metrology mark and find the mapping between various properties of mark patterns and the expected dynamic precision and fidelity of measurements. We formulate the optimality criteria and suggest an optimal overlay mark design in the sense of minimizing the Cramer-Rao lower bound on the estimation error. Based on the developed theoretical resu...
View full abstract»

As the number of metal levels and the wafer size increase, the global planarity and effective removal of metal overlay across the wafer becomes more crucial. Chemical-mechanical polishing (CMP) has been recognized essential to achieve this goal. Accurate in situ endpoint detection and monitoring method significantly improves the yield and throughput. Previous methods have been proposed, which eith...
View full abstract»

To separate systematic and random yield loss, common implementations of the windowing method use an unweighted fit of the Poisson model. By comparison to a properly weighted fit of the negative binomial model, we show that the unweighted fit of the Poisson model can give highly inaccurate results, especially in the presence of clustering. The unweighted fit of the Poisson model is shown to improve...
View full abstract»

The effects of line edge roughness (LER) of nanometer scale gate pattern on the MOS transistor parameter fluctuations and their technology scaling are investigated using the simplified modeling and statistical analysis based on two-dimensional technology CAD (TCAD) tools. From the simple statistical analysis, it is shown that the gate patterns without appropriate LER may cause severe device parame...
View full abstract»

For robust designs, the influence of process variations has to be considered during circuit simulation. We propose a nonparametric statistical method to find sets of simulation parameters that cover the process spread with a minimum number of simulation runs. Process corners are determined from e-test parameter vectors using a location depth algorithm. The e-test corner vectors are then transforme...
View full abstract»

Cleanroom contamination and its impact on the performance of devices are beginning to be investigated due to the increasing sensitivity of the semiconductor manufacturing process to airborne molecular contamination (AMC). A clean bench was equipped with different filter modules and then most AMC in the cleanroom and in the clean bench was detected through air-sampling and wafer-sampling experiment...
View full abstract»

Thermal processing of photoresist are critical steps in the microlithography sequence. The postexpose bake (PEB) steps for current DUV chemically amplified resists is especially sensitive to temperature variations. The problem is complicated with increasing wafer size and decreasing feature size. Conventional thermal systems are no longer able to meet these stringent requirements. The reason is th...
View full abstract»