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Ball-grid array (BGA) places output pins in a solder ball matrix. Generally, BGA traces are fabricated on laminated (BT-based) substrates or polyimide-based films. Therefore, the entire area of substrates or films can be used to route the interconnection. BGA has another advantage of lower ground or power inductance by assigning ground or power nets via a shorter current path to PCB. Thermally enhanced mechanisms (heat sink, thermal balls, etc.) can be applied to BGA to reduce the thermal resistance. The sophisticated capabilities make BGA the desirable package to implement electrical and thermal enhancement in response to the need for high power and high speed ICs.

Flip chip ball-grid array (FCBGA) uses a combination of flip chip and ball grid array features. FCBGA enables short electrical paths for high frequency applications. The simultaneous soldering of all joints in one pass through a reflow furnace facilitates the mounting of packages with thousands of solder joints.

Plastic ball-grid array (PBGA) is the general terminology for the BGA package adopting plastic (epoxy molding compound) as the encapsulation. According to JEDEC standard, PBGA refers to an overall thickness of over 1.7mm.

Super ball-grid array (SBGA) provides a high-power BGA package with a very low profile. With SBGA, the IC is directly attached to an integrated copper heatsink. Since the IC and I/O are on the same side, signal vias are eliminated, providing a significant improvement in electrical performance (inductance).

Interstitial package grid array (IPGA) carries additional pins on a 0.5" offset pattern in between the pins of a regular PGA pattern. It almost doubles the available pins on the same package size as a standard PGA.

Pin grid array (PGA) is a second generation package that uses through-hole technology (THT). Pins are located on a 0.1" grid in various patterns. Package size is reduced by moving pins to the underside of the package in a grid pattern.

Chip scale package or chip size package (CSP) has an area that is no more than 20% larger than the built-in die. CSP is compact for second level packaging efficiency and encapsulated for second level reliability. CSP is superior to both direct-chip-attach (DCA) and chip-on-board (COB) technologies. CSP is used in a variety of integrated circuits (IC), including radio frequency ICs (RFIC), memory ICs, and communication ICs.

Wafer-level chip-scale package (WLCSP) allows an IC to be attached facedown so that its pads connect to the printed circuit board (PCB) through individual solder balls without any underfill material. WLCSP minimizes IC-to-PCB inductance, features small package size, and provides enhanced thermal conduction.

Quad flat packages (QFP) contain a large number of fine, flexible, gull wing shaped leads. Lead width can be as small as 0.16 mm. Lead pitch is 0.4 mm. QFPs provide good second-level reliability and are used in processors, controllers, ASICs, DSPs, gate arrays, logic, memory ICs, PC chipsets, and other applications.

Mini small outline plastic package (MSOP) products are packed in tape reel assemblies that include a carrier tape with embossed cavities for storing individual components. The carrier tape is made from dissipative polystyrene resin. The cover tape is a multilayer film composed of a polyester film, adhesive layer, heat-activated sealant, and anti-static sprayed agent. The reel is made of polystyrene plastic (anti-static coated or intrinsic) and individually bar coded. Reels are placed inside barcode-labeled boxes for shipping.

Thin small outline package (TSOP) is a type of DRAM package that uses gull wing shaped leads on both sides. TSOP DRAM mounts directly on the surface of the printed circuit board. The advantage of the TSOP package is that it is one-third the thickness of an SOJ package. TSOP components are commonly used in small outline DIMM and credit card memory applications. Thin small outline package may be Type I or Type II.

Thin small outline package (TSOP), Type I is a DRAM package that uses gull wing shaped leads on both sides. TSOP DRAM mounts directly on the surface of the printed circuit board. The advantage of the TSOP package is that it is one-third the thickness of an SOJ package. TSOP components are commonly used in small outline DIMM and credit card memory applications.

Thin small outline package (TSOP), Type I is a DRAM package that uses gull wing shaped leads on both sides. TSOP DRAM mounts directly on the surface of the printed circuit board. The advantage of the TSOP package is that it is one-third the thickness of an SOJ package. TSOP components are commonly used in small outline DIMM and credit card memory applications.

Dual in-line package (DIP) is a type of semiconductor component packaging. DIPs can be installed either in sockets or permanently soldered into holes extending into the surface of the printed circuit board. The pins are distributed into two parallel lines along opposite site of the rectangular package. There are several types of DIP packages, such as Ceramic Dual in-line package (CDIP), Plastic Dual in-line package (PDIP), and Shrink Plastic Dual in-line package (SPDIP).

Thin dual flat no-lead (TDFN) packages are fine-pitch, high-performance replacements for 6-pin SOT23 and SC-70 packages. TDFM offers improved thermal characteristics and reduced parasitic compared to these other packages. With the same footprint as equivalent MLF and Mini-BGA packages, TDFM has a much smaller footprint than SOT23 packages.

SOT23 is a rectangular, surface mounted, small outline transistor (SOT) package with three or more gull wing leads. SOT23 features a very small footprint and is optimized for the highest possible current. Because of its low cost and low profile, SOT23 is used in home appliances, office and industrial equipment, personal computers, printers, and communication equipment.

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Restriction of Hazardous Substances (RoHS) is a European Union (EU) directive that requires all manufacturers of electronic and electrical equipment sold in Europe to demonstrate that their products contain only minimal levels of the following hazardous substances: lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyl and polybrominated diphenyl ether. RoHS became effective on July 1, 2006.

The interface has an embedded, over-thermal protection system which shuts down the chip when a maximum temperature is reached.

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