Coding for Phase Change Memory Performance Optimization

Author

Mirhoseini, Azalia

Date

2012-09-05

Advisor

Koushanfar, Farinaz

Degree

Master of Science

Abstract

Over the past several decades, memory technologies have exploited
continual scaling of CMOS to drastically improve performance and
cost. Unfortunately, charge-based memories become unreliable beyond
20 nm feature sizes. A promising alternative is Phase-Change-Memory
(PCM) which leverages scalable resistive thermal mechanisms. To
realize PCM's potential, a number of challenges, including the
limited wear-endurance and costly writes, need to be addressed. This
thesis introduces novel methodologies for encoding data on PCM which exploit asymmetries in read/write performance to minimize memory's wear/energy consumption. First, we map the problem to a
distance-based graph clustering problem and prove it is NP-hard.
Next, we propose two different approaches: an optimal solution
based on Integer-Linear-Programming, and an approximately-optimal solution based on Dynamic-Programming. Our methods target both single-level and multi-level cell PCM and provide further
optimizations for stochastically-distributed data. We devise a low
overhead hardware architecture for the encoder. Evaluations
demonstrate significant performance gains of our framework.