Abstract

Problem statement: The faults in digital circuit can be classified broadly as single stuck-atfaults,
multiple stuck-ay-faults, stuck-open faults, stuck-on faults, path delay faults, transient faults.
Extensive research had been carried out in the field of testing of digital circuits to limit the number of
input vectors. The cardinality of the test vectors proposed by many authors was quite high for large
number of input variables. In this study a testable circuit with a small test set for detection and
diagnosis of OR-bridging type fault in Reed-Muller canonical Exclusive-OR Sum of Products logic
circuits, independent of the function for a given number of inputs had been proposed. Approach: A
network structure comprising a set of Exclusive-OR gates and gates and a couple of auxiliary outputs
were considered. The circuit as well as the test vectors were simulated by MATLAB coding. The faultfree
and OR-bridging faults involving any two lines of control and data lines were then simulated. The
outputs were represented in a compact decimal form for ease of tabulation. Two quantitative indices
for comparison of results had also been discussed. Simulation and analysis for various random
functions had been presented. Results: From the test results it was found that the identifiability for the
set of random functions tested was more than 90% with just n + 5 test vectors compared to 2n test
vectors required for conventional testing. It was also observed that even though the overall
distinguishabililty factor was in the range of 45-80%, the individual set distinguishability was more
than 90%. Conclusion: The proposed scheme had reduced the possibility of unidentifiable faults for
the specified type of function. The location was also diagnosed through the output set. The analysis
and diagnosis had been done through compact tabulation and two quantification indices.