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UVM Connect 2.2 Supports Open Verification Methodology

Mentor Graphics has extended their Universal Verification Methodology Connect tool for the Open Verification Methodology (OVM) community. UVM Connect 2.2 can now be compiled to run with the OVM. The UVM Connect architecture facilitates easy connection with other environments beyond the initially supported UVM and SystemC. With the updated UVM Connect, teams using OVM can connect with SystemC models and other environments.

UVM Connect v2.2 enables standard TLM connectivity between models written in SystemC and OVM SystemVerilog. This maximizes IP reuse. The tool is designed to work with all simulators that support the IEEE 1800 SystemVerilog and IEEE 1666 SystemC standards. It can also accommodate different inter-language instantiation schemes used in various solutions. Feedback from verification teams with simulators from multiple suppliers was taken into account to provide broad industry support.

UVM Connect facilitates cross-language communication via standard transaction level modeling (TLM) interfaces. It allows for the reuse of SystemC architectural models as reference models in SystemVerilog verification, and expands the inventory of Verification IP (VIP) by making it easier to integrate off-the-shelf VIP. With the latest enhancement, both UVM and OVM verification teams can maximize their productivity in a mixed-language, mixed-tool environment by using either SystemC or SystemVerilog to implement key pieces of their testbench and provides direct access to UVM and OVM state and control flow from outside SystemVerilog.