Recorded at a CAS Santa Clara Valley Chapter local event in San Jose. CAS is aware of the less-than-optimal audio
quality of this recording. Future efforts will ensure clear audio.

An active noise-shaping successive-approximation-register (SAR) analog-to-digital converter is described. Instead of binary-weighted
capacitors, it uses two equal-valued capacitors as the embedded digital-to-analog converter (DAC). Thus, the capacitance spread
in the DAC is much smaller than that of the conventional binary-weighted capacitor array, and the mismatch error can be greatly
reduced. The circuit provides first-order noise shaping, which can improve the ADC's linearity even for a small oversampling
ratio. Also, the proposed architecture uses a monotonic approximation procedure, which requires fewer conversion steps than
for a conventional SAR ADCs. The ADC was fabricated in 0.18 um CMOS technology. For a 2 kHz signal bandwidth, it achieved
a 78.8 dB SNDR. It consumes 74.2 mW power from a 1.5 V power supply. The performance can be drastically improved by introducing
noise mitigation schemes and higher-order noise shaping.