I remember reading in one of the guides there is a way to test but for my Corsair Doms 3200 ver 4.xx is Samsung and 5.xx is Hynix and the 5.xx are hard to get a hold of (but every online reviewer seems to have them).

So it will vary even on a given part number. That's what I was wondering. Basically there's nothing you can to do ensure you get a certain brand of IC. Thanks.

This isn't about ddr4 only. What's written below would apply to any external dram architecture; ddr3, ddr4 or otherwise. I won't go too deep, as it's not required. There's a bit more depth in one of the old articles I wrote on AT back in 2010 on this as well.

The disparity of the values depends on the skew between channels/slots. There will always be some on a board with 8 DIMM slots. The rtl value is based on data arrival time after a request has been sent. The training mechanism values are usually aligned at the most stable/optimal point in the valid timing window.

In an ideal world we would want the values to be as small as possible. However, there are constraints (physical and architectural) that prevent the value being lower or higher than a given range.

If the values are manually set to a lower value than set by training, the stability of the system becomes conditional within 1-2 ticks, and will require judicious over-voltage of associated rails to ensure post and pass just a benchmark. That's because we're setting the IMC schedule to expect the first data "packet" sooner and this eats into the guardband (overhead), within the system (which is reduced as we overclock). The operational margin will run out witha one clock change as the system nears its limit as the valid sampling window is smaller. Hence making a reduction in the RTL value will render the IMC to expect the data back sooner than it does and it will either be misread or cause issues for the gearing of the system ( limited due to buffer stack and subsequent sampling of any upstream domain).

Instability is more likely but will depend on the level of stress the system is subjected to and on how hard the bus and memory is being pushed. The harder the system is pushed, the more conditional the stability will be.

When you move the values you are pulling the sampling forward and at some point it will lose sync. The imc will be set to expect the data before it arrives and the margin for getting away with that depends on how much skew the buffer stack can take before sync is lost.

just wanted to know real quick if it was normal for the bios post to show my cpu @3.5ghz (5930k) and one line under that, it says 4.25ghz... Also in CPU-Z it says "specification Core i7-5930K @ 3.5ghz" and in core speed says 4250.00mhz. Is this normal or i did something wrong with my overclock ?