For the second year in a row, July kicked off on a bit of a chilly note. Last year, executives talked about a “pause” in orders, and, sure enough, July 2011 began what proved to be a poor second half for the semiconductor industry.

This year, a similar story appears to be unfolding, as the otherwise lively Semicon West in San Francisco began with Applied Materials CEO Mike Splinter explaining that “a bit of seasonality” has crept into the industry. Applied’s strong order book for semiconductor equipment, he said, had weakened due to foundry pushouts.

Since then, non-foundry companies have been acting cautiously, with Toshiba cutting NAND production by 30 percent, for example, and Texas Instruments expressing concerns about its order book.

Gartner analyst Dean Freeman said the equipment order pushouts are largely due to a couple of large foundries “overinvesting” in recent quarters. TSMC usually adds about 20,000 wafer starts of leading-edge capacity in one year. This year it is on track to add 50-55k wspm – more than two years worth of new capacity in a single year. Delays in getting TSMC’s new fabs ready are contributing to the equipment order hiccup.

Samsung also is investing, bringing its total capacity add this year up by 65,000 wspm. With Apple due to unveil the iPhone 5 in October, perhaps, and Samsung’s smartphones selling very well, Samsung needs new capacity.

The short-term view must be balanced with a big picture outlook. It was just a couple of months ago that Qualcomm and others were screaming for more 28nm capacity. (Stock analysts use the word “lumpy” to describe foundry investments.)

Bob Johnson

Gartner is predicting that semiconductor industry capex will have a compound annual growth rate (CAGR) of only 0.6 percent between 2011 and 2016. Because 2011 was a fairly strong capex year, the number appears low, but if the time period is shifted to 2010-2016 the semiconductor capex CAGR improves to only 3 percent, said Gartner analyst Bob Johnson, speaking at the SEMI/Gartner market forecast event at Semicon West.

The main problem is the world economy. Instead of the 3.6 percent global GDP growth expected for this year, the world economy will be lucky to eke out 3 percent growth, a huge difference for the chip industry. And while the very largest companies are investing heavily, the much larger number of small- and medium-sized fab owners are investing relatively little.

Splinter looks at the world economy and sees various challenges, including “weaker economies in China and Europe than we saw last year. PC shipments are quite weak, and NAND shipments also are less than what we thought. And there are certain factory operational issues at some customers.”

None of this seemed to dampen the overall mood at Semicon West. Dan Hutcheson of VLSI Research said the activity level at West was among the highest ever. Bob Hollands, the head of U.S. marketing for ASM International, also was upbeat. “Sure, the world economy is shaky now, and there are some customer delays. When demand does pick up, they expect us to be able ship equipment to them quickly – they need it in five minutes.”

Dan Tracy, the SEMI market statistics director, was positive, though he may have tempered his optimism in the weeks since Semicon West. While semiconductor capex will decline slightly this year, Tracy sees a 10 percent gain next year, to $46.7 billion. Korea will be the largest market next year, followed by North America with $10 billion in capital investments, led by Intel’s build out of Fab 42 and D1X. And don’t ignore Japan: it is still at or near the top in terms of materials, with a large number of fabs consuming wafers, chemicals, and other materials.

Christian Dieseldorff

SEMI senior analyst Christian Dieseldorff said at this time last year SEMI was pessimistic about new fab construction. But there are now 26 construction plans underway for next year. TSMC is building four fabs at the same time. Samsung has a “superfab” underway at Line 16 in Korea, as well as the S1c and S1d expansions.

“Things are looking pretty rosy for this year, and we could see 2013 hit an all time record,” Dieseldorff said.

I think the world economy is too shaky to put a “rosy” label on the industry’s prospects. We all remember 2009 after Lehman Bros. went bankrupt and the U.S. housing bubble burst. The possibility of both Europe and China solving their financial issues soon is fairly remote (not to mention Japan’s energy crisis).

One of the great things about going to sunny and cool San Francisco for Semicon West is the chance to meet what we journalists call our “good sources.” I ran into Len Jelinek, the semiconductor manufacturing analyst at IHS iSuppli, and he brought the chip industry’s prospects down to ground level. “Just ask yourself,” Jelinek said, “when was the last time you bought a new laptop, or a new TV?” His point is that people are learning to make do with what they have.

His question brings to mind a quote attributed to the Greek philosopher Epicurus: “Nothing is enough for the man to whom enough is too little.”

With Semicon West just a few weeks away in San Francisco, this is a good time to chew on some of the technical and business challenges facing the semiconductor industry, and ask yourself the question: Are you optimistic, or not?

I ask that question having read of young Ben Franklin, who was planning to open a print shop in colonial Philadelphia. His older acquaintance warned him not to do it, pointing out how many competing printers were struggling to survive, how the moral decay in Philadelphia had reached such alarming proportions, and so on. Franklin mused that his friend had the type of gloomy nature which expressed itself in a certain lack of faith in the future of his fellows, and of course Franklin plowed ahead with his business plan.

Which brings us to the question often mentioned in relation to EUV lithography: The “When/If” question. Asked whether EUV will “make it” in high-volume production, the EUV optimists argue that it is “Not a question of If, but When.” The non-optimists believe EUV will never be used in commercial production, partly for cost reasons, putting themselves in the “Not When, but If” camp.

I bounced the When/If question off of Franklin Kalk, the CTO of Toppan Photomasks, at a recent lunch here in Austin. A few weeks earlier, at the Advanced Semiconductor Manufacturing Conference in Saratoga Springs, New York, Sematech lithography program manager, Stefan Wurm of GlobalFoundries, had suggested that masks, and specifically defect-free mask blanks, were a bigger challenge to EUV than the source power question.

Kalk said the DRAM makers need EUV, and will start using it as early as next year even if the throughput is limited to 30 wafers per hour. From that point, the source power vendors, such as Cymer, “probably can accelerate development.”

Kalk said he does have a lot of concerns about the mask blanks. With today’s masks, it is a matter of “find and fix” the defects. But with EUV, once a defect becomes embedded in the “superlattice” of multiple Mo-Si layers, the challenge becomes “changing the imaging characteristics of the defects rather than removing them.”

The lithography industry will really need EUV at the 14nm node, when the pitch will be in the 60nm range and as many as a dozen layers may require EUV, or failing that, double patterning.

What about e-beam? I asked. “E-beam is not going to happen, mainly because of the data throughput challenge. It might make sense for the military guys, because they only need one or two wafers. There aren’t that many F22’s made every year,” he noted, and E-beam could enhance the security of making those chips. But for volume manufacturing, E-beam direct write is too far behind.

What about imprint? Kalk said imprint will be increasingly challenged by the need to make a perfect reticle, with a 1X approach (i.e, the template patterns are the same size as the patterns on the wafer).

(Kalk and Wurm will be among the seven speakers at a lithography TechXPOT at Semicon West on July 11, starting at 10:30 a.m. in the South Hall. Earlier that morning, track vendor Sokudo will host its lithography breakfast, which this year will focus on directed self assembly.)

The Cost Question

After EUV, my biggest concern is the cost-per-function question. If we assume scaling will be doable, can we so easily assume it will be affordable? Will the 25 percent per-annum cost reduction trend continue? It is worrisome indeed to read that experts such as Handel Jones are predicting that the cost of making a transistor may actually go up soon.

There are other challenges, most of which are yield and cost related. Bringing in through silicon vias is a wonderful idea that will surely be adopted for the high-performance, high-priced solutions. But it will require innovation to keep yields high and costs low for commodity ICs with strict price windows.

How about the new transistor types? FinFETs are doable, but it may take awhile before the process flows are ironed out and yields reach acceptable levels. Perhaps a planar, fully depleted SOI approach could be less expensive for some vendors, providing the IP libraries can be more fully developed by the SOI camp.

How about the heterogeneous transistors, in which a germanium channel is deposited in the PFET and an InGaAs channel in the NFET? This approach uses a silicon wafer as the starting substrate, and requires deft deposition skills for the non-silicon channel materials used to boost mobilities in the critical circuits. In a sense, that path is already being trod by GlobalFoundries and others, which use a germanium-rich channel to boost hole mobilities at the 32/28nm generation. This subject will be taken up at Semicon West during a Tuesday TechXPOT, “Enabling Sub-22nm with New Materials and Processes” featuring Sematech’s Raj Jammy, Intel’s Kaizad Mistry, and Carlos Mazure of Soitec, among others.

450mm Wafer Transition

Semicon West is one of the best places to find out about the 450mm wafer transition. The 450mm Supply Chain Forum will be held on Thursday morning, featuring Michael Liehr, general manager of the Global 450 Consortium at Albany, N.Y., Ron Rinfret, 450mm program director at Intel, and Kirk Hasserjian, a vice president at Applied Materials, among others.

Unfortunately for the industry, the EUV and 450mm wafer transition questions have become co-mingled. ASML has spent roughly $2 billion (€1.5 billion) in development of EUV, and it needs to recoup those investments with the 300mm EUV scanners it is bringing to market starting this year.

Which perhaps creates another If-When question, this time for 450mm: IF EUV arrives on 300mm tools, WHEN will 450mm wafers be widely adopted?

Even good-humored Ben Franklin, I’d wager, would have a tough time figuring that one.

I spent a morning recently at a community college near the GlobalFoundries fab in upstate New York, and learned a lot about the challenges facing students and educators.

Fred Strnisa, instructor, semiconductor and nanotechnology

Fred Strnisa, who teaches semiconductor manufacturing technology (SMT) at the Hudson Valley Community College’s Malta campus, has a mix of students. Of the 13 people in the SMT sequence, only two are recent high school graduates, and four are over 40.

“A lot of the people who come here are in their late 20s and 30s,” said Strnisa. “They are trying to reinvent themselves,” hoping to move on to what they believe will be better careers as operators and technicians at the Malta fab, or at one of the General Electric facilities in the Albany-Schenectady-Troy- area.

With fellow SMT teacher Abe Michelin, Strnisa says his job “is to make my students valuable to employers in the area,” including GlobalFoundries, GE, and the College of Nanoscale Science and Engineering (CNSE) and Sematech research complex in Albany, 20 miles to the south. He plans to increase the number of students in the two-year sequence, providing funding materializes.

The coursework is demanding, including hands-on labs aimed at making working diodes. And almost all of the students have jobs. “One student is the manager at the Advanced Auto Parts store here,” Strnisa said, concerned that some his students might have too much on their young shoulders.

Brett Miller stopped by Strnisa’s lab, and volunteered that of the original 15 who started the two-year SMT sequence with him, only six made it through. “Nine of them couldn’t handle it. Usually it is the older students who take it more seriously,” said Miller, who was laid off after a long stint at a book marketing company in the area. He graduated from the SMT program last May, and is hoping to get a job at GlobalFoundries.

“The economy totally tanked here during the downturn, but I saw more high tech companies coming to the area, so I decided to reeducate myself with the SMT program,” he said, estimating that he spent 70-75 hours a week at the classes or studying on his own. He could do that because he qualified for unemployment insurance and supplemental “599B” money to support his retraining effort.

GlobalFoundries has about 1,300 people on board now, and will hire about 300 more by the end of this year when volume production begins. “I’ve been waiting to be hired, to hear back from the hiring manager,” Miller said. “Eventually, I’d like to be in management, but a technician’s job would be a great start.”

Miller said the labs in the SMT program helped him to understand the chip-making process. “When a lab goes wrong, we learn how to fix it,” Miller said, exuding enthusiasm.

Penny Hill, an associate dean at the college’s Tec-Smart program (Training and Education Center for Semiconductor Manufacturing and Alternative and Renewable Technologies), said the SMT program “is pretty difficult for young kids right out of high school. The requirements are challenging, and oftentimes at their ages they aren’t quite sure what they want to do. And then there often are money issues,” she said.

The HVCC’s Tec-Smart program, located not far from the Malta fab, opened in January 2010. It is a gorgeous place, with a church-like peaked ceiling and huge windows, set amidst a nearly pristine forest. Wind turbines and two large solar panels are outside. Geothermal, HVAC, and solar energy programs complement the SMT sequence, partly supported by a Department of Energy grant.

On a sunny and cool spring morning, it seemed like an idyllic place to be. However, there are several challenges facing the school’s industrial technology programs, said Andrew Matonak, president of the Hudson Valley Community College, based in Troy, N.Y. It costs at least 50 percent more to educate a student in industrial skills or health sciences, compared with a liberal arts program. He estimates a $19,000 cost for an industrial sequence, such as one aimed at teaching students the electrical and mechanical skills needed to repair sophisticated machinery. That falls far short of $3,400 in tuition.

Compared with three years ago, New York state funding is 21 percent less. “The state keeps pushing the funding requirements down to the counties, but these health sciences and industrial technology programs are costing more.” The equipment in the SMT lab costs about $500,000, Strnisa estimated, and adding more students requires buying more workstations and tools.

Phil White, dean of the schools of business and engineering & technical technologies, adds that people are still getting to know what GlobalFoundries is all about, and vice versa. The curriculum in the SMT program is being adjusted, based on discussions with GlobalFoundries people.

Students, Matonak and White said, are discussing among themselves the semiconductor industry’s corporate culture, including what it might be like to wear a bunny suit for 12-hour shifts. “For some students, who like socializing, working in a cleanroom environment might be a challenge,” White said.

Ever since Intel uncloaked its tri-gate transistor a year ago, technology watchers have had to make do with the few images Intel released at that time.

Now, the long-awaited Chipworks images are on-line, following the company’s initial teardown report (Intel’s 22nm tri-gate transistors exposed) posted Monday (April 23). One initial surprise was the shape of the Intel fin, rounded on top and tapered or sloped on the sides.

Dick James

Chipworks senior technology analyst (and chief blogger) Dick James said the 22nm teardown process got started when he saw a review of an Intel 22nm server chip on the Anandtech site, which included a helpful link to a site in Hong Kong which had the server processors for sale, even though the server MPUs are not officially on sale until June.

Chipworks (Ottawa) ordered half a dozen of the Intel Xeon E3-1230V2 Server CPUs, at $300 per processor, and they arrived on April 1. Though Chipworks has been burned before with counterfeit die inside packages with new markings, the 22nm chips from Tao Bao in Hong Kong turned out to be genuine, and Chipworks went back and bought more.

Fortunately, Chipworks had upgraded its transmission electron microscope (TEM) in January, replacing an out-of-date model with an FEI Osiris TEM, a much more automated system. The new TEM pumps down to a vacuum state more quickly, and alignment checking also is automated.

The Osiris TEM can do 400,000-times magnification. However, the microscope requires a sample thickness of about 80nm, which means that the images of the Intel transistors show more than is sometimes optimum: with a fin shown next to a gate, for example. “While the fin may be only 5-15nm wide, the sample has to be 80nm thick to get it in to the TEM. That increases the difficult of imaging. You are always seeing a gate and the fin, for example,” James said.

Looking at finFETs takes some getting used to, compared with planar transistors. “You definitely have got to be able to think in 3D. With a regular transistor I can explain how it works with one cross section. With finFETs, I need one image to show the shape of the fin, and another to show the shape of the gate, in right angles to each other. It is a bit more complicated from that point of view,” said James, who has worked for 17 years at Chipworks after earlier employment at semiconductor fabs in his native England.

Another complication is that the one-to-one ratio between structures and transistors doesn’t apply. One transistor can have multiple fins — six or more — while one fin can have multiple transistors.

Since each fin is a defined height and width, designers use quantized fins to create a wider PMOS, for example. “It is a whole different ballgame. These are quantized transistors, so the designers have to think in multiples of a single unit,” James said.

Designers must learn to use quantized gates with finFETs. The SRAM shown here has s a 6-transistor SRAM cell; the transistors marked T2 and T5 use two fins, while the others have one fin. T2 and T5 have gates twice as wide as T1, T3, T4, and T6. (Source: Chipworks)

The Virtues of a Tapered Fin

The Chipworks images show an Intel transistor with a rounded top and tapered, sloping sides. James said that was an interesting and surprising early observation, because many of the photos of finFETs shown in recent years at IEDM and other conferences — by Sematech, Imec, TSMC, and others — all have shown a vertical fin. Intel’s own schematic diagrams show an idealized structure with straight sides.

James speculated that Intel’s tapered fin is easier to manufacture, and the rounded top evens out the electric field at the top of the fin. “Any pointed surface has a higher electric field than a flat surface, so the rounded structure may even out the electric field between the fin and the gate. Our speculation about why it is rounded relates to the fact that if the transistor had square corners on the fin, it would crank up the electric field and make the device less reliable.”

Also, etching straight walls is difficult, making it likely that the etching steps are probably easier with a tapered fin. James said flash memories also often have rounded corners in order to avoid damaging the gate dielectric on the memory cell.

The gate oxide and metal gate are much the same as Intel’s earlier planar transistor, and the PMOS stressing mechanisms also are similar. Intel appears to have changed the metal fill at the center of the gate, using tungsten instead of aluminum and titanium aluminum. James said they feel fairly confident of that conclusion because the “very dark” area appears to be the same color as the W contacts.

On the other hand, Chipworks at this point has “no idea what the stress mechanisms for NMOS are.” Intel is no longer using the nitride stressors it employed at the 90nm and 65nm nodes, because there is not enough room around the gate. At 45nm, Intel used a mixture of metals on the gate to put tensile stress on the channel. “That may be possible (with tri-gate), but it doesn’t show. If there is stress in the NMOS, it is different from the 32nm approach,” he said.

TEM image shows the transition between PMOS and NMOS gates. The mottled TiN layer is in the PMOS, but not the NMOS. Some epitaxial SiGe can be seen on the source/drain of the PMOS fin. (Source: Chipworks)

I asked James if Intel’s technologists cooperate with Chipworks as it struggles to figure out what the images show. He said he posts the blogs first, and hopes for some reaction steering him in the right direction later, if the initial conclusions are faulty.

“Sometimes one or another person from Intel will get back to me, and say, ‘I can’t tell you where you were wrong, but this is not quite right. And they are fairly cordial when I meet them at IEDM. When I am chatting with them, they might say ‘You are pretty well right 90 percent of the time,’ which I take as a compliment since we are groping in the dark on something like this.”

The quality of life has improved at the GlobalFoundries Fab 8 here in upstate New York. Sure, people here are breathing easier now that yields are up at the company’s fab in Dresden, Germany, and winter has turned to a luscious spring here at Malta, located north of Albany.

The gut-level joy comes because the fab’s new cafeteria opened on Monday, April 16. I arrived the next day to do some interviews about how the fab is staffing up, getting ready for volume production later this year.

When time came for lunch, we made our way down to the spanking-new cafeteria. I saw a sign for sushi, and went over there, thinking there might be some plastic packages of pre-made sushi, the kind you can pick up at the grocery store when you are in a hurry.

Instead, there was a real Japanese sushi chef at work, knife in hand, who began making the two rolls I ordered. Two other customers soon arrived, as I heard a Japanese man and woman behind me speaking in anticipation about the various kinds of sushi available. They were in the fab to install equipment, and had discovered a little island of gastronomic home.

The GlobalFoundries fab, like most semiconductor operations, is an international place, with people from 30 countries among the 1,300 (and growing) employees. Judging by the visitor’s log in the lobby, there is a steady stream of visiting contractors who hail from abroad. Half of the GlobalFoundries employees come from outside the area.

These workers from abroad have raised the standards for the Fab 8 cafeteria, said Angelo Mazzone, the CEO of a company which runs five cafeterias and six restaurants in the area. “We have a lot of people here from Singapore and Dresden, and these people from overseas know so much about food,” Mazzone said.

Each food station has a bona fide chef, and there is a full-time coffee barista who offers drinks made from beans sourced from around the world. “The people from Dresden like real strong coffee,” Mazzone noted.

One of his challenges was to develop a base of suppliers able to supply the variety of foods offered at the cafeteria. One objective is to offer a complete meal for $6, but most people spend between $7 and $10 on lunch.

Travis Bullard, who handles corporate public relations at the Malta site, said GlobalFoundries is part of a bigger trend among high-tech companies offering good food to their workers. Before coming to Malta, Bullard worked in Austin at the new Longhorn campus of AMD, and he said his former employer also has a deluxe cafeteria. Google and Apple apparently are at the forefront of a trend to offer healthy food, either for free or for very low prices.

At Malta, the goal is for the cafeteria to pay for itself, Mazzone said. Right now, the cafeteria is open from 5:30 a.m. to 7 p.m. “It may be open 24/7 at some point, but that comes at a big cost,” he noted. The fab is in the midst of a beautiful forest, well away from any restaurants. A round-the-clock food supply will be a necessity once volume production begins later this year.

GlobalFoundries is ahead of schedule on its hiring plans, Bullard said, and expects to have 1,600 working at the fab in a few months, up from 1,300 now. Before the cafeteria opened, there were more than a thousand construction workers who were fed well from a big tent at the construction site. Mazzone converted a shipping container, the kind which moves cargo on ships, into an outdoor kitchen to supply the fab builders with cooked food. That worked well, but food brought in can’t compete with a real kitchen.

Bullard said the cafeteria is a place where the workers can come together and talk. “People bump into each other in the cafeteria and start talking about things they are working on. We never had that before this place opened. It’s an intangible benefit.”

An army marches on its stomach, and foundries are no different. Packing a lunch day after day can be a drag, and so it is no wonder that the GlobalFoundries workers were smiling broadly last week. The sushi is excellent.

When Robert Preisser was looking for a place to set up an R&D center for the German chemical company he works for, he looked at Imec (Leuven, Belgium) and Leti (Grenoble) in Europe, Albany Nanotech in New York, and the Institute of Microelectronics in Singapore.

Preisser had spent 20 years with IBM in the United States and Germany, most notably working at the IBM-Siemens joint research project for 64-Mbit DRAM development in New York. After IBM shut down its DRAM fab in Sindelfingen, Germany, Preisser took up IBM Germany’s retirement offer and got into the chemical industry. He is now vice president of semiconductor technology at the chemical firm Atotech, a subsidiary of the much larger Total oil, gas, and chemical conglomerate.

Preisser’s mission back in 2007 was to develop semiconductor-use chemicals for copper electroplating. (Atotech, according to its Web site, had absorbed Schering Electroplating, “having a deep history in electroplating dating back to 1920.”)

Robert Preisser

Surprisingly, Preisser said Atotech was not interested in taking incentives or subsidies. “They reduce our speed and give us a lot of paperwork,” he said during a visit to Austin for the Sematech Surface Preparation and Cleaning Conference (SPCC).

If not subsidies, then what was he looking for? Three things, he answered in his definitive-statement style of speech. First, a supply of wafers where a new research group could do “meaningful R&D.” That involved a research center with good patterning capabilities. Secondly, he needed access to diagnostic tools.

And thirdly, “an opportunity to hire talented people.” Atotech could have transferred a core group from Germany, but Preisser said he wanted “to start fresh, with new people.” After selecting Albany Nanotech as the place where Atotech would set up its center, Preisser hired a Ph.D. from CNSE, the College of Nanoscale Science and Engineering at the University of Albany.

He set his sights on two U.S. universities renowned for electrochemistry — Columbia University in New York City and Case Western Reserve in Cleveland – as well as CNSE itself. Very few of the people Preisser sought to hire rejected his offer, and he ended up with nine scientists.

Naturally, being a white guy originally from Ohio, I had to ask Preisser how many of the people he hired were Americans. He laughed, joking that he is now an expert in the art of obtaining U.S. visas, and said that none of his Ph.D. science recruits had a U.S. passport. He hired two Dutch nationals, and an array of Chinese, Japanese, and Singaporeans. They came from graduate programs at CNSE, Case Western, Ohio State, and the University of New Hampshire.

They set to work developing chemistries for defect-free plating, using inorganic base metallization solutions combined with organic polymers. With the exception of one person who became gravely ill and had to return to China, they are still at it.

Preisser said one reason he could hire people fairly easily is because Atotech and Total are large organizations, and the newly hired researchers have opportunities to move back home if they so choose. The company has 1,200 people in China, for example, with plenty of opportunities there.

“Our team has the ability to interact with the very best academics in the field of electrochemistry. Though they all had to go through a very steep learning curve, I am more than happy with the results,” he said.

I asked Preisser if had run into any stumbling blocks. He said because the CNSE operation is basically a university R&D center, the wafers had variabilities of plus or minus 10 percent, rather than the 3 percent variability seen at a leading manufacturing fab. “The supply of wafers, and the diagnostic capabilities, went well up to a certain point. We had to work on the incoming quality levels, but we knew that there would be differences between a college environment versus a manufacturing site.”

For certain projects, Atotech obtained test wafers from prospective customers. And Preisser and his team were able to exchange opinions with IBM technologists working nearby.

After developing a line of wet chemistry products for semiconductor BEOL applications, Preisser set out to hire a sales team. While the R&D team needed to be physically together in Albany, the sales force could live anywhere, as long as they had the requisite industry experience.

“I started reading the industry news, and when I heard that AMAT or KLA or Freescale was laying people off, I looked in my rolodex, found people I knew at those places, and made them offers,” Preisser recalled with a laugh.

“How was the Albany Nanotech experience?” I asked.

He didn’t hesitate, noting that whenever he had a problem he could walk into the office of the right person and get a fast solution. “If I had to do it all over again, I would do much the same. CNSE can talk about what they can do, but from my standpoint, they can do it. Alain Kaloyeros has his critics, but he has a unique vision. And at the end of the day he did it. The result is that they have almost 3,000 people there now.”

Sometimes, you have to hear it from the horse’s mouth. Everyone has heard about the claims of improved 32nm yields at the GlobalFoundries Dresden fab. At the Common Platform Technology Forum, details emerged about how the GlobalFoundries team boosted yields so dramatically.

Mike Noonen, hired away in January from NXP Semiconductors as the sales and marketing senior vice president at GlobalFoundries, started out the Common Platform event by acknowledging that in the third quarter of last year, low yields were “challenging” the volume production of AMD’s Llano processor.

Mike Noonen

“We took a variety of steps in the fab and on the management team,” Noonen said at the Santa Clara event Wednesday (March 14). “The result was that Llano yields doubled in a quarter. We are in a very, very aggressive ramp of Llano,” he told more than a thousand attendees.

Noonen said the foundry achieved an 80% increase in 32nm unit shipments from Q3 to Q4.

How did GlobalFoundries’s Dresden yields improve in such a short time?

An executive gave credit to the “great German engineers” at Dresden, with a key boost from Robert Madge, director of design-enabled manufacturing at GlobalFoundries, who was sent over to Dresden early last year to help fix the yield issues.

Rutger Wijburg, hired last August to run the Dresden campus after working at NXP’s foundry operations, brought an intense focus on yield improvements, this source said. Rather than try to accommodate a dozen new foundry products at the same time — which “sent the Dresden operation into shock, hurting everything” — Wijburg preached “Llano, Llano, Llano” to the Dresden team. “German engineering did the rest,” the executive said.

Single-wafer clean tools from Dai Nippon Screen (DNS) were used much more widely, a key factor in the yield-enhancement campaign. “Getting the particles off the wafers with single-wafer cleans was one of the main things they figured out. We also bought a bunch of brightfield inspection tools. And there were some back-end copper issues that got figured out,” he said.

With 32nm SOI yields now at very respectable levels, “AMD is happy again,” the executive said, with the relationship back on a normal customer-supplier basis. If GlobalFoundries can deliver the goods, they will keep AMD’s business, even in the face of competition from TSMC at 28nm bulk and 28nm HKMG.

AMD has its “Trinity” processor coming along this year, and the expectations are for AMD to account for about $1.5B in business for GlobalFoundries this year, up from $800 million in 2011. JoAnne Feeney, a stock analyst at Longbow Research, said AMD has been gaining market share, with a 17 percent share of the notebook processor market.

Feeney said notebook customers pay a lot of attention to battery life, and the AMD notebook processors are equivalent to what Intel-based systems deliver. Consumers don’t know or care if the processor is 32nm SOI or 22nm Tri-gate, she added, as long as the performance, graphics, and, especially, battery life are competitive.

The AMD-based thin notebooks — which Intel has branded as UltraBooks – may be significantly cheaper than the Intel-based UltraBooks, Feeney added. While Intel has outlined specific guidelines for what UltraBooks must be able to do, thereby jacking up the costs, the AMD customers have a relatively free rein and may be able to undercut the UltraBook retail prices by a couple hundred of dollars, she said.

“I am predicting that AMD will gain share this year,” Feeney said at the Common Platform event.

Another interesting point was raised by a senior marketing manager working at GlobalFoundries. While a year ago some major smartphone IC manufacturers were saying they would mainly use a non-high-k gate stack for 28nm applications processors, the advantages of high-k are now swinging more of their product mix toward a high-k solution. The nitrided polySi gate oxide just can’t keep up in terms of power and performance with the more-complex high-k gate stack. And with mass production of 28nm parts slipping somewhat, customers are tilting toward high-k at 28nm and pushing back tapeouts of 20nm parts by three or four quarters, he added.

With several hundred thousand wafer starts of 32nm high-k/metal gate production behind it for Llano production, the company’s painful yield enhancement process will pay dividends at 28nm HKMG, he said.

Another executive at the Common Platform Forum claimed that through all of the foundry’s 2011 challenges, GlobalFoundries customers have been willing to cut the foundry some slack, largely because they don’t want to be totally dependent on TSMC and thereby vulnerable to wafer price increases as 28nm heads into mass production.

The apparent end of the Semiconductor International Capacity Statistics (SICAS) program is not the end of the world, but it is an indication of the consolidation trend in the semiconductor manufacturing industry.

SICAS’s end was not mourned by Gartner semiconductor manufacturing analyst Bob Johnson or VLSI Research CEO Dan Hutcheson. The message from those two gentlemen: “Don’t worry, we’ve got you covered.” While SICAS was free to all (even journalists), Gartner and VLSI offer their respective data sets for a fee. And Hutcheson said his company’s fab utilization report is better than what SICAS offered, partly because VLSI’s fab utilization data comes out monthly rather than quarterly.

SICAS tracks capacity by technology node. (Source: SICAS)

SICAS, which tracks fab capacity and utilization, is a relatively small program compared with the World Semiconductor Trade Statistics (WSTS), which saw Intel drop out following AMD’s withdrawal in December. IC Insights president Bill McClean said he was trying to get the SICAS board to revise its data categories and revive the SICAS program. And McClean also was contacting his sources to see if Intel could somehow get back in and participate in a revised category within WSTS, without “exposing” its pricing data to customers. If the WSTS would merge MPUs with, say, the SoCs which are used as the application processors in cellphones, it would support the WSTS’s overall goals and allow Intel to “hide its data,” McClean said.

When AMD withdrew from WSTS in December, for reasons yet to be made clear, Intel was “exposed” by being the last participant in the MPU category at WSTS. Knowing that Intel was the only company in the category apparently allowed customers to see Intel’s average selling prices. “Intel was exposed. It is a pricing issue. Customers can look at the WSTS data and are go back to Intel and say, ‘You charged us more’ than the average,” McClean said. UMC (or TSMC) was in a similarly “exposed” position when one or the other of the big Taiwan foundries decided to drop out.

VLSI Research tracks fab utilization on a monthly basis. (Source: VLSI Research Inc)

TSMC apparently withdrew from the SICAS program because SICAS reported foundry capacity data by technology node, allowing others to see how much overall foundry capacity was available at, say, 28nm. Since TSMC discusses sales by technology node on a quarterly basis, the withdrawal had Hutcheson and Johnson theorizing that TSMC and other companies simply didn’t see the added value in dealing with SICAS.

McClean argued that fab utilization data is “the kind of thing that is useful,” noting that in the first quarter of 2009 SICAS was reporting a measly 66.8 percent utilization rate. By the third quarter, utilization had jumped to 87 percent. “That showed everybody how fast the industry was recovering,” McClean said.

Johnson said Gartner arrives at its utilization data by tracking the total silicon consumed and the total wafer capacity by node. Dividing those terms gives Gartner its utilization data. Analysts who don’t own their own utilization data, Johnson said, will have to “scramble around, because their models are based on SICAS.”

Overall, the SICAS demise is part of a larger trend. The large companies, with well-staffed sales and marketing organizations, gather their own data and want to “control the message” going out to the marketplace.

“The big companies don’t want to talk about what they are doing with the smaller companies around. We might as well get used to it. Intel knows who builds wireless devices, and there are only a few companies building smart phones who really matter. Do the big companies really need WSTS? Probably not,” Johnson said.

“With the WSTS, Intel is not controlling the message. The WSTS withdrawal by Intel is symptomatic: companies as big as Intel, Samsung, and TSMC want to control their own messaging to the market,” Johnson said.

If it were a matter of simply merging categories in the WSTS reports to hide Intel’s ASPs, or shrouding the foundry data in SICAS somewhat but keeping the bigger utilization picture intact, these kinds of fixes would be worthwhile. The SIA is studying the issue, a spokeswoman said, while emphasizing that both SICAS and WSTS are independent bodies with their own boards.

“SIA has no decision-making authority regarding SICAS and the administration of the quarterly report. However, we do help sponsor the program, encourage our members to participate, have many common members and republish the SICAS report on our website,” the SIA spokeswoman said.

Once the three companies decided not participate, the SICAS executive committee made the decision to discontinue the report because of the diminished value of the data.

“In speaking with SIA members we understand that the real value of the report is that it provided a global view, and while many of our members are open to continuing to provide this data, the return on investment for them is just not significant enough if the report does not capture a global picture of production capacity,” she added.

That statement suggests that, while the SIA and the SICAS members wish the group had not fallen apart, without data from what she called “a key region” it appears unlikely SICAS will be revived.

Jonathan Davis, president of SEMI’s Global Semiconductor Business operation, said he believes SEMI has the most comprehensive fab capacity information, but it doesn’t monitor utilization levels, as SICAS does. “SICAS reported trend data to the supply chain that was valuable,” Davis said. And while the largest equipment and materials companies may have their own research organizations which can gather and collate data from multiple sources, there are many smaller suppliers which do not have that option.

“The broader supply chain — the long tail of the supplier base — benefits (from SICAS and WSTS), and even the largest companies call us regularly to verify their own data. SICAS was not perfect, and all of these market research tools are imperfect. The data is less valuable when some companies are not participating,” Davis said.

Hutcheson of VLSI Research had an interesting take on SICAS, comparing it to government programs which compete with private businesses. “It costs us to develop the primary (capacity and utilization) data, and with SICAS out there it made it more difficult to convince people to pay for it, even though our reports are on a monthly basis,” he said.

And Hutcheson said capacity or utilization are not the best measures of how the industry is doing, or whether a downturn is on the way. Capacity is an always-evolving number. Since foundries and others need to invest in capacity for leading-edge linewidths ahead of demand, the result can be a lower utilization number. What the IC vendors and systems companies want to know is whether a foundry or IDM has enough leading-edge capacity in place to supply chips which will be needed for future demand, Hutcheson said.

Inventory levels turn out to be a better indicator of when a downturn might be around the corner, Hutcheson added, noting that has called two earlier downturns ahead of other market research firms by watching the rising inventory levels and comparing the inventory data with billing numbers.

In 2000, for example, the industry was in a fab-building boom, but shortly thereafter inventories started scaling up. “It was inventories that gave us the signal (of the 2001 downturn). Capacity utilization was a lagging indicator,” Hutcheson said.

WSTS is a different story, he said. WSTS tracks such a wide variety of chip types — ranging from analog to discretes and power IC — that all companies benefit from the WSTS data.

“If Intel drops out of WSTS, it looks bad. Intel is a company that needs to play a leadership role,” Hutcheson said. And he recalled that the WSTS data collection effort started with Intel, National, AMD and other compies in Silicon Valley, with Texas Instruments joining a few years later. The WSTS data was used as the gold standard during the U.S.-Japan semiconductor trade negotiations in the mid-1980s, with Washington demanding that the Japanese government use WSTS data — rather than MITI or EIAJ numbers —for determining the market share of non-Japanese companies in the Japan semiconductor market.

Having spent so many years of effort to build up the completeness and credibility of the WSTS database, it would be unfortunate to see it diminished by the absences of Intel and AMD.

The larger companies gather different data sets, buying information from VLSI, Gartner, and iSuppli, and then adding in the public data from SICAS, WSTS, and other sources. Fabless IC vendors need to make sure they are ordering enough wafers.

Similarly, chip makers need to watch utilization levels and make sure they are included in the slots allocated for important tools. Hutcheson noted that in 2009 several big IC companies — aware that it takes as two years or longer for Nikon and ASML to build an immersion scanner — gobbled up all the scanner capacity. That left one of the major foundries fourth in line for scanners, which hurt its bottom line when demand bounced back.

The announcement that Elpida Memory Inc. is declaring bankruptcy essentially takes Japan out of the DRAM sector which Japanese companies came to dominate in the mid-1980s.

What happened in Japan that took out all the once-leading DRAM makers over three decades?

Three things come to mind: First, the yen tripled in value vis a vis the dollar. Secondly, Japanese managers lacked strategic direction and became overly cautious. Third, Samsung and others, sensing opportunity, pounced on the opening.

Go back 30 years to the lovely, green island of Kyushu in southern Japan. Toshiba embarked on a gamble there — one that eventually earned the company billions of dollars in profits — moving from NMOS to the more power-efficient CMOS transistor technology. At Toshiba’s Oita Works in the early 1980s, Toshiba DRAM engineers had a single, parts-starved implanter and were staying up all night, starting at 11 pm every night, to boost the single-digit yields of their one megabit CMOS DRAM.

By the mid-1980s, Tsuyoshi Kawanishi, the general manager of Toshiba’s semiconductor operations, and his staff had taken yields for the 1-Mbit CMOS DRAM to respectable levels. Kawanishi was a charismatic manager, confident without being arrogant, who knew that CMOS at the megabit density was a winning combo in a memory IC sector that was growing rapidly as the computer boom got fully underway. His staff idolized him and – similar to the positive momentum built by Jim Morgan at the helm of Applied Materials – the positive wave at Toshiba carried over into successes in notebooks computers, displays, and other products.

An equally talented Toshiba semiconductor division manager, Taizo Nishimuro, was at that time in charge of sales and marketing. He was making sure that Toshiba’s limited supplies of CMOS DRAMs were allocated fairly to the world’s computer makers, which were all were clamoring for parts. “We know where every single one mega DRAM is going. We have to, because of the trade frictions,” Nishimuro told me in an a 1986 interview.

Nishimuro-san was right to be worried. In 1985 the United States Dept. of Commerce had slammed DRAM dumping duties on Japan, setting off a series of events which led to the 1986 U.S.-Japan Semiconductor trade agreement, which formally called for an expectation that U.S. companies would hold a 20 percent share of an open Japan chip market.

It took a year for NEC, Hitachi, Mitsubishi Electric, Fujitsu, Matsushita Electric, Oki Electric, and others to catch up with Toshiba’s lead in CMOS DRAMs. But they did it, and Japanese semiconductor companies came to hold six of the top 10 spots in the world semiconductor rankings. At one point, investments in Japan’s semiconductor fabs were more than half of all Japan’s capital investments – an astounding amount of money was going into memory fab building. It was enough to scare Intel and other U.S.-based DRAM makers out of the memory sector and into MPUs – a fortuitous change in direction for Intel.

As exports of DRAMs and other well-made products soared, Japan’s trade surpluses ballooned. The imbalances were made worse by the country’s shima kuni konjo (literally, island country mentality, which came to mean an arguably insular belief by many Japanese that nearly everything done in Japan, by Japanese people, was more reliable and more valuable than products made outside of the Japanese islands). With an anti-import bias entrenched in the national mentality, Japan’s trade imbalance proved nearly intractable.

The dollar's value has declined against the yen over the past decade. (Source: Forecastchart.com)

Over the past decade, the Korean won has remained stable against the U.S. dollar. (Source: Forecastchart.com)

Thus, just a few years after Toshiba’s success with its CMOS megabit DRAM, Japanese managers had twin headaches: how to deal with the higher yen and the insistent market-opening demands from the U.S. Semiconductor Industry Association, led by Bob Noyce, Gordon Moore, Wilf Corrigan, Jerry Sanders, Charlie Sporck, and other battle-hardened executives.

The persistent trade imbalances which Washington and the SIA railed against led to en daka (too high value of the yen). The yen’s value became a ever-heavier weight bearing down on the Japanese semiconductor industry.

As the yen was rising, the confidence of Japan’s top managers – who had computer and telecom operations as well as semiconductors to deal with– began sagging. The executives leading Japan’s electronics industry moved away from a stance of bold initiative — exemplified by Toshiba’s Kawanishi and the CMOS move – to a more hesitant, bottom-line-driven mentality.

Again, cultural perceptions played a role. During this early 1990s period I interviewed Kazuo Kimbara, who ran Hitachi’s semiconductor operations. He fretted that the United States economy would be dragged down by social challenges such as crime, education, racial conflicts, divorce, and the like. Kimbara-san, and others, couldn’t quite see beyond the headlines to the basic realities of the U.S. economy, which proceeded to do quite well as software, networking, personal computers, and mobile products combined to form the tech-driven economy we have today.

As Japan’s confidence and chip investments faltered, Samsung pounced. Everything broke right for Samsung, as the Korean won remained relatively stable while the yen rose sharply in value. Investments in and revenues from NAND complemented its DRAM base. And Samsung invested during the industry down cycles, and in 200-mm and then 300mm wafer equipment while Japanese companies did not, relatively speaking.

Another point has to do with the sequence of development of Japan’s semiconductor industry. Hajime Sasaki, who ran NEC’s semiconductor operations in its heyday, famously said Japan’s chip industry was “like a dog chasing two rabbits” — logic and memory — ending up with neither. Samsung seemed to uncoil like a baseball slugger, initially seizing the DRAM opportunity, then building into NAND, and – having built a solid base in commodity memory – moving on to the logic and foundry opportunity.

A few words about Elpida. Its president, Yukio Sakamoto, was a vice president at Texas Instruments Japan until 1993. TI operated several fabs in Japan, and Sakamoto moved up the ladder by solving tough problems, recalled Mentor Graphics CEO Wally Rhines, who also worked at TI then.

“When a customer would call up and say it needed a rush shipment by Friday, Sakamoto would tell us, ‘I’ll take care of it.’ And he would. He did that over and over again, saying ‘I’ll take care of it.’ That is how he gained everyone’s respect, by taking care of the tough challenges that come up when you are running a semiconductor operation,” Rhines said.

As talented and committed as Sakamoto-san surely is, he and his colleagues at Elpida ran up against a set of new realities in the DRAM industry. They were among the leaders in the drive to 20nm design rules, to Wide I/O DRAM and Mobile DRAM. Elpida remains a major supplier to Apple. But is it enough? Will the Japanese government move to save Elpida and its jobs, or let it go just as Germany let Qimonda die?

Without NAND and facing a bleak future for DRAMs, Elpida may in fact go bankrupt. Japanese chip manufacturers simply can’t thrive in an era of 78 yen to the dollar.

Barring a phoenix-like miracle by Elpida, it is a sad end to a remarkable run by a long line of Japanese DRAM makers.

Do you remember how you were first exposed to the semiconductor industry, to the idea that the field might be a good place in which to work?

For me, it happened to be in the early 1980s, reading an article in National Geographic magazine while manning the night editing desk at the Associated Press bureau in Tokyo. I remember the author wrote that making semiconductors was “basically a chemical process.” I had enjoyed my chemistry classes and a brief part-time job helping a chemist, cleaning beakers, watching the gas chromatograph, and the like. “Hey, maybe I could write about that,” I thought.

Perhaps a similar confidence-boosting process is underway for some of the 22 boys and 22 girls – high school students from Austin area schools — who attended the SEMI High Tech U program held largely at Samsung Austin Semiconductor recently.

Lisa Anderson manages the High Tech U program, which is part of the SEMI Foundation. In Austin, the students spent three full days rubbing shoulders with technicians from Samsung, listening to volunteer speakers from semiconductor equipment companies, and others. “We seek the good to average students, kids who could be even better. Our goal is to get them excited about math and science, to show them how what they learn in their chemistry classes can be applied. Getting them into an industrial setting can make a huge difference,” Anderson said.

On the day I visited, Samsung engineer Kim Gabor, a chemical engineer by training, was demonstrating what a Samsung technician does. She had several girls and boys working as a team with electronics kits, connecting wires to terminals and the like.

High Tech U includes the “soft skills” students will need when applying for jobs, how to speak clearly, dress properly for a job interview, and the like. Tom Ortman, CEO of Concurrent Design, led a session on critical thinking, for example. As one of the Austin teachers at the event said, “Generally speaking, the students who are good at math and science often are not the most social. They want to learn the soft skills, and this is a place that affords them that opportunity.”

The Austin event was the 25th High Tech U program for students, including a program in Singapore where the students (including a group which traveled from Abu Dhabi) went inside an Applied Materials Singapore cleanroom. Another 103 teacher-training sessions have been held, Anderson said. Programs about LEDs and nanotech are being developed.

About half of the money to put on the Austin event came from the Fab Owners Association. Samsung Austin Semiconductor hosted the students for part of three-day event, and other support came from Applied Materials, Horiba, Microbinc, MKS Instruments, Tokyo Electron, Austin Community College, and Texas State University.

Anderson said in the early going it was fairly easy to get big companies such as Intel and Applied to underwrite most of a High Tech U program. While they continue to provide support, she said that in general “companies are strapped for funds, and it is not that easy anymore.” One solution is to get smaller amounts from a number of companies. It costs about $600-$700 per student to organize and put on the three-day programs.

Much of the organizational work in Austin was done by Judy Andersen, who is the CEO of a company, Microbinc, which provides clean rooms and contamination control supplies to data centers, bio-tech, and semiconductor companies. Andersen told the SEMI Austin committee, “It is never too early to start pulling in funds for the next event. Though we don’t have a date yet, we’d like to roll it out every six months. Samsung probably will want to be involved, but we do want to move it around.”

Catherine Morse, the general counsel at Samsung Austin, said the company had to work hard to recruit 1,400 technically savvy workers over the past couple of years. That awakened Samsung to the need to support career development activities, including bringing busloads of students to tour the Austin site. “During the last hiring cycle we realized we needed a strategy for galvanizing the STEM pipeline in Central Texas,” Morse said.

Who knows? By the time Samsung gets ready to build another fab in Austin, some of the students who took the High Tech U course may be graduated and looking for good jobs.