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Description/Abstract

Behavioural synthesis is the process whereby the description of a system behaviour is automatically translated into a physical implementation of that system. An essential prerequisite of this process is a language in which to express the design. Traditionally, hardware description languages (HDLs) are used for this, but there is currently much interest in the idea of coercing conventional software languages to do the same job (SystemC is the most prominent example of this). The goal of the research described is to increase the synthesisable description space to support the description of systems utilising dynamic allocation. VHDL supports the concepts of dynamic allocation, and is used as the entry language for the system, although without loss of validity SystemC could have been used. How the structures conventionally associated with dynamic description are implemented and supported is described together with a heap management subsystem that is both space and speed-efficient and which communicates with the user's design via an automatically generated interface.