FPGADesignExpert

Course Description

This course is specially designed for designers new to FPGAs design or programmable logic. Build an effective FPGA design using scnchronous design techniques, instantiate appropriate device resources, use proper HDL coding techniques, make good pin assignments, set basic XDC timing constraints, and use the Vivado® Design Suite to build, synthesize, implement, and download a design.

Hands-on Project on the last day allows you to test your knowledge and apply your skills immediately. No documentation, no labs instructions, you will face the real challenge to do a full FPGA design flow project with the guidance of our instructor.

Who Should AttendDigital designers new to FPGA design who need to learn the FPGA design cycle and the major aspects of the Vivado® Design Suite.

Duration3 days

Software Tools

Vivado Design or System Edition

Prerequisites

Basic knowledge of the VHDL or Verilog language

Digital design knowledge

Skills Gained

After completing this comprehensive training, you will have the necessary skills to:

Use the New Project Wizard to create a new Vivado IDE project

Describe the supported design flows of the Vivado IDE

Generate a DRC report to detect and fix design issues early in the flow

Use the Vivado IDE I/O Planning layout to perform pin assignments

Synthesize and implement the HDL design

Apply clock and I/O timing constraints and perform timing analysis

Describe the "baselining" process to gain timing closure on a design

Use the Schematic and Hierarchy viewers to analyze and cross-probe a design