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Feb 24, 2013

DDR4, Signal Integrity, and Power Integrity

One of the biggest design challenges today revolves around
maintaining signal integrity in the presence of power and ground rail
fluctuations due to simultaneously switching signals. This is particularly true
for DDR4 memory.

DDR4 is a big step from DDR3, much bigger than DDR3 was over
DDR2. Speed is going from 2133 Mb/s at the top end to 3200 Mb/s. Vdd
goes from 1.5V to 1.2V. The Unit Interval (UI) shrinks from 469ps to 313ps.
Channel interconnect skew and jitter easily consume 50% of the 2133 Mbps timing
budget. These, combined with other factors, including the effects of DQS
jitter, edge roll-off, impedance discontinuities, pin-to-pin capacitance
variations, crosstalk and inter-symbol interference (ISI), make designs with
DDR4 far more far more challenging to simulate and measure. One must also take
into account variances in the printed circuit board manufacture, as described
here "How to avoid poor serdes performance caused by circuit board manufacturing variances",
as well as variances in silicon manufacture as described here "Platform Validation using Intel® Interconnect Built-In Self Test (Intel® IBIST".

Most importantly, stability of the power distribution
network (PDN) plays a key role in signal integrity and operating margins of the
design. The maximum ripple of the PDN is specified as +/- 60mV for DDR4 as
opposed to +/- 75mV for DDR3. Simultaneous switching noise (SSN) will have a
major effect – in the worst case, for example, all 64 bits of a data bus
transition simultaneously, with large instantaneous changes in current across
the power distribution networks (PDNs) causing fluctuations in voltage levels
that impact the timing margins of the transitioning signals. These
simultaneously switching outputs (SSO) affect memory and other serial I/O data
integrity on the board.

Nowadays, some board designers use power-aware SI simulation
tools to provide some level of assurance that things will work properly. This
involves the modeling of the copper shapes that comprise the power and ground
planes, as well as the vias that run through them, along with the coupling to
the signal traces. These vias essentially act as radial transmission lines that
excite the parallel plate plane structures, perturb the power supplied to the
chips, and couple noise back onto the signals as well.

In addition, decoupling capacitors must also be modeled and
incorporated into the simulation, as does the voltage regulator module (VRM).

Given the complexities of these simulations, design
engineers must be cautious of relying on measurements taken with oscilloscopes
which themselves contain simulations. On-chip embedded instrumentation should
be used to report precisely what is being seen at the device transmit and
receive buffers. Further, measurements using embedded instruments to generate
worst-case bit patterns, causing SSO and the maximum amount of jitter,
crosstalk and ISI, is highly recommended. These are provided by the ScanWorks High-Speed I/O and DDR test software.