According to Synopsys, the new data converter architecture in the 28nm process node resulted in up to 76% reduction in power consumption and up to 86% reduction in area use. This reduces system costs for wireless networking and mobile communications system-on-chips (SoCs). Increasing Synopsys’ 12-bit ADCs’ performance to 320 megasamples per second (MSPS) enables greater flexibility for system definition in communications applications such as those enabled by LTE and WiFi 802.11ac protocols.

Synopsys’ successive approximation register (SAR)-based architecture for its 12-bit high-speed ADCs offers parallel assembly options for improved area, lower power and architectural scalability. The ADCs currently offer conversion rates of up to 320 MSPS with architectural support for rates beyond 1 gigasample per second (GSPS). In addition, the 12-bit high-speed DACs increase conversion rates to 600 MSPS, a 50% increase in speed over the previous generation. Increased conversion rates allow for higher oversampling of the signal, which reduces filtering requirements at the output of the DACs and simplifies the circuit design.