Hold on to your helmets: a wild rumor that Intel may be looking to introduce the same design considerations as they already did with their Lakefield architecture has appeared. According to momomo via Twitter (a user who has already shared many rumors and details in the PC hardware space) as well as some other sources, Intel is looking to bring a Big.Little-like design (which Intel calls Hybrid architecture) to the desktop platform in the form of Alder Lake-S, to be reportedly built on the 10 nm process. While Intel's Lakefield (especially geared for the mobile market) only sported four Atom (Intel's low power) Tremont cores combined with one high-performance Sunny Cove core, Alder Lake-S could sport as many as an 8+8 configuration, with a TDP currently set up to 80 W (and up to 125 W TDP is also set in the revealing slides with a disclosure regarding investigating performance scaling in up to 150 W TDP).

Should this actual Alder Lake-S product materialize in the 10 nm process, this could be a way for Intel to salvage what it can from the 10 nm process for the desktop platform. As we know from multiple reports on the state of Intel's 10 nm, yields and operating frequencies aren't close to what was expected, and Intel's CFO George Davis even said at last week's Morgan Stanley's Analyst Conference that their 10 nm process wouldn't be as profitable as even 22 nm, which does show that Intel is already looking past this process for their 7 nm deployment. A Big.Little design for a desktop architecture does seem like a more plausible design decision for a struggling process than a full 16-core monolithic die such as those Intel currently employs.

The leaked slide also points to a new socket, LGA 1700, which would supersede the LGA 1200 that's being deployed with Comet Lake-S (10th gen) and which could feature support for Intel's Rocket Lake-S family (11th Gen). The leak also plays out a possible PCIe 4.0 support from Alder Lake-S, which could mean this is the first Intel architecture to sport this updated protocol, should it not debut with Rocket Lake-S already. Slightly logic, rational leaps mean that Intel could be looking at leveraging their Golden Cove (high performance) and Gracemont (Atom) CPU cores for this hybrid design.

My dumb question of the day is how is Windows going to handle this? Even on Android getting ARM's implementation of Big.Little needed extensive work to make it possible. Windows doesn't have such process scheduling in its kernel.

My dumb question of the day is how is Windows going to handle this? Even on Android getting ARM's implementation of Big.Little needed extensive work to make it possible. Windows doesn't have such process scheduling in its kernel.

@KarymidoN
I'd look at difference between FM2+ (906) and LGA115x.
Both provide almost the same connectivity - 16 PCIe lanes, 4 lane DMI/UMI, ~3 display outputs and dual channel RAM.
Both platforms had quite similar power ratings, yet PGA manages to do the same with less pins.
Judging by that my (un)educated guess is that PGA pins have better current capabilities.

906*1.27 ~= 1150
1331*1.27 ~= 1690

That also may mean that intel might finally create a proper SoC this time.

Microsoft already has an idea of big.LITTLE due to Windows 10 on Arm. And they'd be happy to implement big.LITTLE scheduling for x86, probably for free, because they want a cut of the ultraportable market just as much as much as Intel does. The s**ty Arm chips that they've been trying to make work with Qualcomm are never going to do it.

We don't know the highest core count, or TDP (not max TDP for the socket), for the final product, nor should we > 18 months away from launch. So, kind of hard to compare with anything. All we know is that it's desktop.

As a comparison, the max core count or Ryzen 3000 wasn't officially revealed until about 9 months before launch or so, IIRC.

Skipping? I doubt it. I've only ever said they won't bring it into the consumer space any time soon. I never mentioned PCIe 5.0 though.
Intel has always had a few reserved pins, as they tend to use at least some of them for more power once they bring out the second generation of a "platform".

The leaked slide mentions high-end CPUs, but that generation will also include models will less cores and much lower power consumption.
The idea of high+low performance cores will be perfect for what I've mentioned.

For HEDT and so on - probably not so much. But I'm sure we'll find a way to use them.
And of course this is a perfect example of an architecture that can utilize OneAPI. So it's all beautifully coherent in the blue camp. We'll see how well this is executed.

Big.Little on desktops is a perplexing idea, no matter what they do Intel somehow always manages to waste silicon for things that are unneeded and unwanted. It looks to me like they are so invested into these new things things they're just going to use them anywhere irrespective on whether or not it makes sense.

I think you misunderstood me. Instead of having HT that hampers the performance in a few cases, you have separate small cores instead that won't affect the performance of the big cores, probably with a performance gain. I'm not saying they should work as threads for the big cores.

I think you misunderstood me. Instead of having HT that hampers the performance in a few cases, you have separate small cores instead that won't affect the performance of the big cores, probably with a performance gain. I'm not saying they should work as threads for the big cores.

The impact SMT has is almost universally beneficial, it's so rare that the performance degrades it's not worth eliminating it. I mean that's the whole point, otherwise this feature would have been canned long ago.

The thing is, the 8 core processor with SMT will be less expensive to manufacturer and actually use less power than an 8+8 processor with no SMT. Big.Little makes no sense whatsoever on a desktop.

And if someone is so hung on not having SMT they can just disable it, no need for an entirely different processor.