The CPU performs a power-on-reset style of operation when the
reset! pin is driven.

Other mode settings may be controlled by pins and/or
attributes: endian-set!/endian
to set endianness, start-pc-set! to set the PC.
These are useful if the standard powerup state of the CPU needs
to be changed for running a program that expects an initialized
environment.

The component executes zero or more instructions when the
step! pin is driven. You can specify the maximum
number of instructions to be executed via the
step-insn-count attribute. If the
yield pin is driven in a reentrant fashion while the
instruction loop is active, the loop will be exited at the next
opportunity. At the end of the loop, the step-cycles
output pin is driven with the number of instructions actually
executed, though this value is clamped to be at least 1. The
insn-count attribute accumulates the
total number of instructions executed since reset.

Each instruction is first fetched from memory via the
insn-memory accessor, and its decoding
traced if the trace-extract? attribute is
set to a true value. The decoded form may be cached
indefinitely afterwards, although this cache is flushed when the
flush-icache pin is driven.

The engine-type attribute specifies
whether the "scache" ("semantic cache") or "pbb" ("pseudo basic
block") dispatching mechanism is used during execution. The
"scache" mode executes each instruction in isolation and checks
all triggerpoints after each. If the
enable-step-trap? attribute is set, after
each instruction, a single-stepping trap is signalled as
described in the exceptions/traps behavior below.

The "pbb" mode executes a series of sequential instructions
in one uninterruptible sequence, and is thus faster. However,
it cannot handle triggerpoints or single-stepping, nor can it
respond to icache flushing as quickly. The "pbb" mode is
temporarily and transparently downgraded to the "scache" mode
when needed.

During the execution of an instruction, this component may
make accesses using the data-memory
accessor, may update its simulated registers, and may trigger an
exception/trap.

The component can be configured to perform certain kinds of
tracing as target programs execute. These are controlled by the
family of trace-* boolean attributes. By default, trace output
is directed to the standard output stream. The
trace-filename attribute allows the user
to specify the name of a file where trace output will be
collected. A special filename of "-" is used to represent
standard output. Trace output files are not appended, but
overwritten each time they are opened.

When encountering exception/trap conditions such as memory
access errors or software interrupts, this component signals the
event using the trap pin. (For some traps, the
trap-code pin is driven with extra information just
beforehand.) An external component may interpret the values in
the table below, and declare a disposition for the condition.
In the absence of input, the condition will be treated as the
hardware would, that is by dispatching to exception vectors,
switching processor modes, etc.

Hardware interrupts are signalled by driving the pins
nfiq or nirq with a zero value. Incoming
interrupts are queued and are processed when the
step! pin is next invoked. Note that this may not be
the next instruction if the
step-insn-count attribute is greater than
one.

All 16 general purpose registers are accessible as attribute
r0 through r15.
pc is an alias of
r15. The CPSR register is accessible as
cpsr, and also as
cpsr-flags for a decoded textual form.
The current endianness is available as attribute
endian. The current cpsr mode is
available as attribute/pin nm. The
current thumb/arm bit is available as attribute/pin
tbit.

This component exports a number of attributes for use by the
sw-debug-gdb component. These are the gdb-* attributes, in
the "debugger" category. The gdb-register-N group access all
registers in gdb's indexing scheme, in raw target byte order.
The gdb-register-pc is a special watchable value with no
associated attribute. The gdb-num-registers attribute provides
the limit for N. The gdb-exp-registers attribute provides a
semicolon-separated list of "expedited" register numbers.

The debugger-bus bus provides access to the target program's
address space, and is used by gdb to access target memory.

Environment:

Related components:

CPUs connect to many components: memory to store data and
instructions, a scheduler to provide step! signals, software
trap emulators, debugger interfaces. The step-cycles output pin
may be used as a N-event-control input for a target scheduler to
track an estimate of consumed target time.

Host system:

Some error conditions are signalled by messages to standard error.
These include some illegal CPU states caused by the simulated
program.