Issue

Package-on-Package Trends and Technology

07/01/2006

Destined for Growth

BY FLYNN CARSON AND MOSHE BUNYAN, STATS ChipPAC Inc.

The stacked-die approach to vertical integration has encountered some problems as the integration of different device technologies, such as digital processor with DRAM memory, becomes a requirement. Known good die (KGD) issues related to memory, final test-yield considerations, ability to access and test the final package on a common platform, and business issues surrounding ownership and liability compensation of the integrated package product are concerns. Package-on-Package (PoP) has come to the fore as a 3-D package solution that addresses the myriad problems associated with integrating varying device types.

PoP Drivers and Market Trends

PoP offers better time-to-market, flexibility for product upgrades, low non-recurring engineering (NRE) and development costs, and the ability to use existing, high-yielding silicon die, which avoids development of a new chip, shortening the design cycle.

While a typical stacked-die package provides the technology needed to integrate multiple ICs in a single package - reducing the complexity of the motherboard and shrinking the overall size and cost of the portable handheld device - the real power of PoP lies in the flexibility it provides by minimizing liabilities and improving logistics.

Figure 1. Package-on-Package stack.

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PoP provides original equipment manufacturers (OEMs) the flexibility to change silicon technologies’ combinations integrated on the board up to the final moment of final assembly. For example, a cell phone manufacturer can plan on integrating a differential signal processing (DSP) chip package with a high-memory chip package. However, if market conditions change and demand shifts to a low-memory chip package, the OEM can change the bill of materials (BOM) at board assembly and replace the high-memory chip package with the low-memory chip package without requiring a new design or board layout.

Figure 2. PoP business model.

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Integration of several ICs in one package requires logistics management of commercial die acquisition. In a typical stacked-die package, one IC manufacturer must take ownership of all the dice to be integrated into the package. This puts the financial and logistical burden on the owner. PoP eliminates the need for the IC manufacturer to manage the supply chain. Instead, the OEM takes ownership of all the dice to be integrated, and will manage the respective suppliers according to their market demands.

As supply chain issues ease, more integrated device manufacturers (IDMs) and fabless companies are adopting this technology. This has accelerated the growth of this package, and is expected to replace some of the typical 2-die stacked packages and outpace the growth of high-end (>3 die) stack packages.

PoP Technology Requirements and Trends

PoP is leveraging many enabling technologies developed and implemented in production for stacked-die packages. Figure 3 compares the technology required to produce a stacked-die package integrating a digital processor with a memory stack vs. a PoP version. The top PoP is an advanced stacked-die package. The need to minimize the overall stacked package mounted height requires this top PoP to be as thin as possible. Die-thinning down to 75 µm and below, and the use of die-attach films is required. The PoP uses the same wire-bond and low-loop technologies developed and implemented for stacked die. In the bottom PoP, control of wire loop is more critical than stacked-die applications because the thinnest possible mold cap and overall stacked package height is required. Aggressive bond finger pitch is required (down to 80-µm bond finger pitch has been developed) to allow for the smallest mold-cap size and package footprint for a given die size. To achieve such bond finger pitch and route all signals from the top PoP to the device(s) packaged in the bottom PoP, the substrate complexity and technology required for the bottom package is usually higher than for an equivalent stacked-die package. Because of overall package height constraints, the thinnest possible substrates are being used for the bottom and top PoP. Encapsulate molding is a key area that differentiates the PoP package from other stacked-die packages. The bottom PoP requires top center mold gate (TCMG) technology to produce a mold cap without interfering with the peripheral lands on the top of the bottom PoP. The top PoP needs the thinnest possible mold body, which requires advanced molding technology (such as vacuum mold) and molding compounds.

Figure 3. Stacked-die vs. PoP assembly technology.

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Typical mobile phone requirement for package height is less than 1.4 mm, which is difficult to achieve with PoP compared to stacked-die packages. Some allowance can be made to accommodate 1.6-mm maximum height packages, but this is not desirable. The need to minimize the substrate, die, and mold cap thickness, and package-to-package gap for the PoP, leads to other concerns and issues such as package warpage. The top and bottom PoP must be placed on top of each other and reflowed simultaneously on the PCB. The use of lead-free solder balls requires reflow profiles up to a peak temperature of 260°C. Excessive package warpage during the reflow process can lead to solder ball bridging, or no connection between solder joints. Surface mount yields related to PoP are a concern that impacts the adoption and success of this package. Focus has been placed on characterizing and optimizing warpage of the PoP, and developing and optimizing the surface mount process. PoP warpage can be controlled by proper materials selection, particularly mold compounds and die-attach materials, as well as optimizing substrate and package design (Figure 4). Collaborative efforts between package assemblers, device manufacturers, surface mount houses, and end customers are underway to validate board mount yields and reliability.

Figure 4. Material impact on bottom PoP warpage trend during reflow.

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Requirements for higher performance and functional density, and smaller footprint, is the future trend. Flip chip interconnect technology is being integrated to address this, especially into the bottom PoP. A bottom PoP with two devices stacked within has been introduced to enable functional integration and performance of bottom PoP. In addition, different types of bottom PoP configurations are being developed to allow for more device integration in the bottom PoP. PoP is expected to evolve into stackable tested system building blocks. Three-tier or layer-stacked packages are being designed to combine RF, digital, and memory devices. The success and adoption of such future packages will hinge on meeting overall cost, thickness, performance, and thermal requirements.

Conclusion

Leveraging many of the enabling technologies developed and implemented in production for stacked-die packages, PoP technology provides flexible, quick time-to-market, no-supply-chain-headache solutions while meeting the performance, size, and cost requirements of the next-generation devices.