Registration and details of the Preliminary Agenda for our 5th RISC-V Workshop hosted at the Google Quad Campus in Mountain View, CA November 29-30, 2016 are available here.

RISC-V: The Free and Open RISC Instruction Set Architecture

RISC-V (pronounced "risk-five") is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. The RISC-V ISA was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.

RISC-V Foundation Appoints Board of DirectorsJune 9, 2016-RISC-V Foundation appoints inaugural Board of Directors Seven Directors Appointed to the BoardBerkeley, CA, June 9, 2016 – Today, the RISC-V Foundation is pleased to announce the Foundation’s inaugural Board of Directors. Seven industry veterans with varied career experience within large multinational companies, smaller startup companies, non-profit organizations and academia have been appointed to serve on the RISC-V Foundation Board of Directors.The inaugural set of Directors include: Krste Asanović as...

RISC-V Offers Simple, Modular ISAApril 1, 2016- The RISC-V ISA has been featured in the latest edition of the Microprocessor Report written by David Kanter of The Linley Group.The RISC-V Foundation has retained distribution rights for this report. The full report is shown below and it can be downloaded and freely distributed.

Charting a New Course for SemiconductorsMarch 3, 2016-The Global Semiconductor Alliance has released a new report “Charting a New Course for Semiconductors” which explores the future of the semiconductor industry and asks “Is RISC-V the new Linux?”. Global Semiconductor Alliance Releases New ReportThe report includes 4 Chapters covering key areas including: Chapter 1 – An Industry in Transition – Rising development costs, decreasing margins and...

5th RISC-V Workshop Proceedings-5th RISC-V Workshop Proceedings November 29-30, 2016 Proceedings for the 5th RISC-V Workshop, hosted at Google’s Quad campus (468 Ellis Street, Mountain View, CA 94043) on November 29-30, 2016 are now available with links to the slide presentations shown in the Agenda below (some slide sets are not yet available from the speakers).The goals of the workshop are to bring the RISC-V community together to share information about recent activity in the...

5th RISC-V Workshop Agenda-5th RISC-V Workshop November 29-30, 2016 Registration remains open and the call for presentations / posters is now closed for the 5th RISC-V Workshop, hosted at Google’s Quad campus (468 Ellis Street, Mountain View, CA 94043) on November 29-30, 2016. The Preliminary Agenda is shown below.The goals of the workshop are to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, and build...

5th RISC-V Workshop Registration and Call for Papers-5th RISC-V Workshop November 29-30, 2016 Call for Papers and Registration Open Registration remains open and the call for presentations / posters is now closed for the 5th RISC-V Workshop, hosted at Google’s Quad campus (468 Ellis Street, Mountain View, CA 94043) on November 29-30, 2016. The goals of the workshop are to bring the RISC-V community together to share information about recent activity in the various RISC-V projects underway around the globe, and...

RISC-V Sessions at DAC 2016-Be sure to join us at the 53rd Design Automation Conference in Austin Texas the week of June 6th, 2016 for some interesting RISC-V sessions.Professor Krste Asanovic, UC Berkeley and Chairman of the RISC-V Foundation will deliver the Tuesday June 7th SKY Talk at 1pm in the DAC Pavilion entitled: “RISC-V: Instruction Sets Want To Be Free”. The most important interface in a computer system is the instruction set architecture...

RISC-V Presentation at ESC Boston- Arun Thomas from BAE Systems was on the agenda at ESC Boston on Wednesday April 13, 2016 presenting an introduction to the RISC-V ISA. His presentation, “Building Open Hardware with RISC-V” is shown below.

5th RISC-V Workshop Proceedings-5th RISC-V Workshop Proceedings November 29-30, 2016 Proceedings for the 5th RISC-V Workshop, hosted at Google’s Quad campus (468 Ellis Street, Mountain View, CA 94043) on November 29-30, 2016 are now available with links to the slide presentations shown in the Agenda below (some slide sets are not yet available from the speakers).The goals of the workshop are to bring the RISC-V community together to share information about recent activity in the...

4th RISC-V Workshop Proceedings-Our 4th RISC-V Workshop was hosted at MIT in Cambridge, MA, this past July 12-13, 2016. The Workshop agenda is shown below together with slides and videos from each of the talks. We had tremendous participation with 266 registered attendees representing 63 companies and 42 universities from around the world. About the WorkshopThe goals for our RISC-V workshops are for the community to share information about recent activity in various RISC-V projects underway around...

3rd RISC-V Workshop Proceedings-Our 3rd RISC-V Workshop was held at the Oracle Conference Center in Redwood Shores, CA January 5-6, 2016. The Workshop agenda is shown below along with the presentation slides and videos from each talk as well as summaries from each of the Breakout Sessions. AboutThe goals of this workshop are for the community to share information about recent activity in the various RISC-V projects underway around the globe, and to build...