The 74F109 is a dual positive edge-triggered JK-type flip-flopfeaturing individual J, K, clock, set, and reset inputs; also true andcomplementary outputs. Set (SD) and reset (RD) are asynchronousactive low inputs and operate independently of the clock (CP) input.The J and K are edge-triggered inputs which control the statechanges of the flip-flops as described in the function table. Clocktriggering occurs at a voltage level and is not directly related to thetransition time of the positive-going pulse. The J and K inputs mustbe stable just one setup time prior to the low-to-high transition of theclock for predictable operation. The JK design allows operation as aD flip-flop by tying J and K inputs together. Although the clock inputis level sensitive, the positive transition of the clock pulse betweenthe 0.8V and 2.0V levels should be equal to or less than the clock tooutput delay time for reliable operation.

PIN CONFIGURATION

16

15

14

13

12

11

10

7

6

5

4

3

2

1

Q0

V

CC

CP1

SD1

Q1

K1

RD1

J1

RD0

J0

Q0

K0

CP0

SD0

9

8

GND

Q1

SF00135

TYPE

TYPICAL f

max

TYPICAL SUPPLY CURRENT

(TOTAL)

74F109

125MHz

12.3mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

COMMERCIAL RANGE

V

CC

= 5V

±

10%, T

amb

= 0

°

C to +70

°

C

INDUSTRIAL RANGE

V

CC

= 5V

±

10%, T

amb

= ­40

°

C to +85

°

C

PKG DWG #

16-pin plastic DIP

N74F109N

I74F109N

SOT38-4

16-pin plastic SO

N74F109D

I74F109D

SOT109-1

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS

DESCRIPTION

74F (U.L.) HIGH/LOW

LOAD VALUE HIGH/LOW

J0, J1

J inputs

1.0/1.0

20

µ

A/0.6mA

K0, K1

K inputs

1.0/1.0

20

µ

A/0.6mA

CP0, CP1

Clock inputs (active rising edge)

1.0/1.0

20

µ

A/0.6mA

SD0, SD1

Set inputs (active Low)

1.0/3.0

20

µ

A/1.8mA

RD0, RD1

Reset inputs (active Low)

1.0/3.0

20

µ

A/1.8mA

Q0, Q1, Q0, Q1

Data outputs

50/33

1.0mA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20

µ

A in the High state and 0.6mA in the Low state.

LOGIC SYMBOL

J1

J0

Q0 Q0 Q1 Q1

V

CC

= Pin 16

GND = Pin 8

K1

K0

2 14 3 13

6 7 10 9

CP0

SD0

RD0

CP1

SD1

RD1

4

5

1

12

11

15

SF00136

IEC/IEEE SYMBOL

SF00137

7

2

4

3

1

5

14

12

13

15

11

6

10

9

1J

C1

1K

R

S

2J

C2

2K

R

S

Philips Semiconductors

Product specification

74F109

Postive J-K positive edge-triggered flip-flops

October 23, 1990

3

LOGIC DIAGRAM

V

CC

= Pin 16

GND = Pin 8

K

Q

Q

CP

4, 12

3, 13

6, 10

7, 9

2, 14

5, 11

1, 15

SD

RD

J

SF00138

FUNCTION TABLE

INPUTS

OUTPUTS

OPERATING MODE

SD

RD

CP

J

K

Q

Q

OPERATING MODE

L

H

X

X

X

H

L

Asynchronous set

H

L

X

X

X

L

H

Asynchronous reset

L

L

X

X

X

H

H

Undetermined*

H

H

X

X

q

q

Hold

H

H

h

l

q

q

Toggle

H

H

h

h

H

L

Load "1" (set)

H

H

l

l

L

H

Load "0" (reset)

H

H

l

h

q

q

Hold 'no change"

NOTES:H = High-voltage levelh

= High-voltage level one setup time prior to low-to-high

clock transition

L

= Low-voltage level

l

= Low-voltage level one setup time prior to low-to-high

clock transition

q

= Lower case indicate the state of the referenced output

prior to the low-to-high clock transition

X = Don't care

= Low-to-high clock transition

= Not low-to-high clock transition

*

= Both outputs will be high if both SD and RD go low

simultaneously

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over theoperating free air temperature range.)

NOTES:1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.2. All typical values are at V

CC

= 5V, T

amb

= 25

°

C.

3. Not more than one output should be shorted at a time. For testing I

OS

, the use of high-speed test apparatus and/or sample-and-hold

techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shortingof a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In anysequence of parameter tests, I

OS

tests should be performed last.

4. Measure I

CC

with the clock input grounded and all outputs open, then with Q and Q outputs high in turn.

AC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL

PARAMETER

TEST

CONDITION

V

CC

= +5.0V

T

amb

= +25

°

C

C

L

= 50pF

R

L

= 500

V

CC

= +5.0V

±

10%

T

amb

= 0

°

C to +70

°

C

C

L

= 50pF

R

L

= 500

V

CC

= +5.0V

±

10%

T

amb

= ­40

°

C to +85

°

C

C

L

= 50pF

R

L

= 500

UNIT

MIN

TYP

MAX

MIN

MAX

MIN

MAX

f

MAX

Maximum clock frequency

Waveform 1

90

125

90

90

MHz

t

PLH

t

PHL

Propagation delayCPn to Qn or Qn

Waveform 1

3.84.4

5.36.2

7.08.0

3.84.4

8.09.2

3.84.4

9.09.2

ns

t

PLH

t

PHL

Propagation delaySDn, RD to Qn or Qn

Waveform 2, 3

3.23.5

5.27.0

7.09.0

3.23.5

8.0

10.5

2.83.5

9.0

10.5

ns

AC SETUP REQUIREMENTS

LIMITS

SYMBOL

PARAMETER

TEST

CONDITION

V

CC

= +5.0V

T

amb

= +25

°

C

C

L

= 50pF

R

L

= 500

V

CC

= +5.0V

±

10%

T

amb

= 0

°

C to +70

°

C

C

L

= 50pF

R

L

= 500

V

CC

= +5.0V

±

10%

T

amb

= ­40

°

C to +85

°

C

C

L

= 50pF

R

L

= 500

UNIT

MIN

TYP

MAX

MIN

MAX

MIN

MAX

t

su

(H)

t

su

(L)

Setup time, high or lowDn to CPn

Waveform 1

3.03.0

3.03.0

3.03.0

ns

t

h

(H)

t

h

(L)

Hold time, high or lowDn to CPn

Waveform 1

1.01.0

1.01.0

1.01.0

ns

t

w

(H)

t

w

(L)

CP pulse width,high or low

Waveform 1

4.05.0

4.05.0

4.05.0

ns

t

w

(L)

SDn or RDn pulse width,low

Waveform 2

4.0

4.0

4.0

ns

t

rec

Recovery timeSDn or RDn to CP

Waveform 3

2.0

2.0

2.0

ns

Philips Semiconductors

Product specification

74F109

Postive J-K positive edge-triggered flip-flops

October 23, 1990

5

AC WAVEFORMS

For all waveforms, V

M

= 1.5V.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Waveform 2. Propagation Delay for Set and Reset to Output, Set and Reset Pulse Width

SDn or RDn

VM

VM

trec

CPn

SF00051

Waveform 3. Recovery Timer for Set or Reset to Clock

Philips Semiconductors

Product specification

74F109

Postive J-K positive edge-triggered flip-flops

October 23, 1990

6

TEST CIRCUIT AND WAVEFORMS

tw

90%

VM

10%

90%

VM

10%

90%

VM

10%

90%

VM

10%

NEGATIVEPULSE

POSITIVEPULSE

tw

AMP (V)

0V

0V

tTHL (tf

)

INPUT PULSE REQUIREMENTS

rep. rate

t

w

t

TLH

t

THL

1MHz

500ns

2.5ns

2.5ns

Input Pulse Definition

VCC

family

74F

D.U.T.

PULSE

GENERATOR

RL

CL

RT

VIN

VOUT

Test Circuit for Totem-Pole Outputs

DEFINITIONS:R

L

= Load resistor;

see AC ELECTRICAL CHARACTERISTICS for value.

C

L

= Load capacitance includes jig and probe capacitance;

see AC ELECTRICAL CHARACTERISTICS for value.

R

T

= Termination resistance should be equal to Z

OUT

of

pulse generators.

tTHL (tf

)

tTLH (tr

)

tTLH (tr

)

AMP (V)

amplitude

3.0V

1.5V

V

M

SF00006

Philips Semiconductors

Product specification

74F109

Positive J-K positive edge-triggered flip-flops

1990 Oct 23

7

DIP16:

plastic dual in-line package; 16 leads (300 mil)

SOT38-4

Philips Semiconductors

Product specification

74F109

Positive J-K positive edge-triggered flip-flops

1990 Oct 23

8

SO16:

plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

Philips Semiconductors

Product specification

74F109

Positive J-K positive edge-triggered flip-flops

1990 Oct 23

9

NOTES

Philips Semiconductors

Product specification

74F109

Positive J-K positive edge-triggered flip-flops

yyyy mmm dd

10

Definitions

Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. Fordetailed information see the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above oneor more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these orat any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extendedperiods may affect device reliability.

Application information -- Applications that are described herein for any of these products are for illustrative purposes only. PhilipsSemiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing ormodification.

Disclaimers

Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products canreasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applicationsdo so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standardcells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes noresponsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to theseproducts, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unlessotherwise specified.

This data sheet contains the design target or goal specifications for product development.Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.Philips Semiconductors reserves the right to make chages at any time without notice in order toimprove design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to makechanges at any time without notice in order to improve design and supply the best possible product.

Data sheet status

[1]

Please consult the most recently issued datasheet before initiating or completing a design.