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Calibre nmDRC

Total cycle time is on the rise due to more complex and larger designs, higher error counts and more verification iterations. Calibre® nmDRC responds to the need for reduced cycle time with revolutionary new capabilities that differentiate Calibre nmDRC substantially from traditional DRC tools.

Pattern Matching

Calibre® Pattern Matching replaces text-based design rule checks with a visual geometry that ensures a precise and accurate implementation of the design specification. Automated pattern capture and search integrated with existing design environments make the process easy to use, reducing rule deck size and verification time while improving product quality and performance.

Equation-Based DRC

Calibre nmDRC's new Equation-Based DRC (eqDRC) capability fills the void between traditional DRC and DFM process simulators, bringing user extensibility and fast runtimes to a whole host of new design and process interactions. Identifying and prioritizing design layout issues that affect yield are a big drag on turnaround time. Some issues are simply too complex to capture with traditional DRC measurements. Equation-based DRC enables precise and accurate characterizations of complex, multi-variable and 2D/3D interactions that have a direct impact on manufacturability. This allows you to make reliable design tradeoffs, and to quickly determine the best fix.

Automated IP Waiver Management

Calibre Auto-Waiver provides automated recognition and removal of waived design rule violations in external intellectual property (IP), eliminating redundant error debugging while ensuring that all waived errors are properly identified during full-chip verification. Because Calibre Auto-Waiver is fully qualified by the foundry as part of Calibre nmDRC, you can be confident that no matter what process you are using, Calibre Auto-Waiver will accurately process all IP waiver information, saving you critical verification time and resources.

Integrated DFM Analysis

Integrated design for manufacturing (DFM) analysis and enhancement enable layout tradeoffs to minimize random, systematic and parametric yield loss. Simultaneous DRC, yield analysis and layout modification decrease the total time required to produce a layout that is not only design rule compliant, but also high yielding.

“I was using a previous version of Calibre. I had a complex lvs problem that I was having difficulty locating where the problem was. A Mentor AE recommended I upgrade to the latest version which had lots of improvements in the GUI and reporting of errors. The new Calibre RVE/LVS took me right to the coordinates of the violating instance, and I was able to see the short right away. And it told me exactly which node it was shorted to. I would certainly encourage Calibre users to look into upgrading to the latest release of the software.”