These modules offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high rate with automatic column-address generation, interleave between internal banks in order to hide precharge time, and the capability to randomly change column address on each clock cycle during burst.

Fully Synchronous ­ all signals registered on positive edge of system clock

Data provided during Reads and Writes at twice the clock frequency

Package Height: 1.20 inches

Kentron Technologies, Inc. (978) 988-9100 Page 2 Rev. (3/02)

64M X 72 REGISTERED DDR DIMM

Operating Features:

The SDRAM DDR DIMM utilizes a differential clock input for the synchronization. Each operation of the SDRAM is determined by commands and all operations are referenced to a positive clock edge. CAS Latency defines the delay from when a Read Command is registered on a rising clock edge to when the data from the Read Command becomes available at the outputs. The CAS latency is expressed in terms of clock cycles. This specific DIMM supports 3 and 2 clock cycles.

The burst mode is a very high-speed access mode utilizing an internal column address generator. Once a column address for the first access is set, following addresses are automatically generated by the internal column address counter.

All control and address signals are registered on-board and hence delayed by one cycle in arriving at the SDRAMs. The clock signal is distributed to all SDRAMs via a zero delay PLL driver. Note that the PLL must be given enough clock cycles to stabilize before any operation can be given (minimum stabilization time equal to 1 ms).

Absolute Maximum Ratings*:

Item

Symbol

Rating

Unit

Supply voltage (V

CC

Relative to V

SS

)

V

dd

-1 ~ 3.6

V

Input/Output Voltage

V

ddq

-1 ~ 3.6

V

Operating temperature

T

opr

70

°C

Storage temperature

T

stg

-55 ~ 150

°C

Short circuit output current

I

out

50

mA

* Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as detailed in the sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.