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AR# 29275

Description

9.2i Service Pack 3 Architecture Wizard ties the reset signals of the DCM and PLL together in the DCM2PLL and PLL2DCM modes. Why does simulation error out for this reset connection? What should the reset connections actually be?

Solution

In 9.2i Service Pack 3 and previous software, Architecture Wizard and the software implementation tools tie the resets of the DCM and PLL together in both DCM2PLL and PLL2DCM modes. This causes an error in simulation because the tools expect the reset of the second component to be tied to the inverted locked signal of the first component, as described in (Xilinx Answer 18181).

Work-around A:

If the simulation is required to pass successfully, modify the output of Architecture Wizard to change the reset structure of the second component in the chain.

For example, in PLL2DCM mode, instead of having the resets of the PLL and DCM tied together in the HDL code, perform the following:

1. Tie the user reset to the PLL only.

2. Drive the reset of the DCM with the inverted LOCKED signal of the PLL, including an SRL module that forces the reset to be held for at least three valid clock cycles of the DCM CLKIN. See (Xilinx Answer 18181).

3. Tie the DCM locked signal to the locked output signal of the module.

Modifying the Architecture Wizard output requires the removal of the "XAW" module from the design, and insertion of the HDL code generated by Architecture Wizard into the user design.

Work-around B:

If simulation verification is not required when using ISE 9.2i Service Pack 3 software to create the design, the reset portion of the PLL2DCM or DCM2PLL will behave correctly in hardware. When the reset signals of the DCM and PLL are tied together, the second component in the chain will automatically wait for the first to lock before starting its own locking cycle.

Work-around C:

For ISE 9.2i Service Pack 4, a tactical patch will be made available so that Architecture Wizard ties the resets of the PLL and DCM in such a way that simulation will not error out and reflects the proper functionality in hardware. Please contact Xilinx Technical Support for more information on the availability of the patch.

This issue will also be fixed in the next major release of the software.