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Stories of data hacking have been dominating the news lately. It seems that hackers are getting smarter and more bold, but what is also making it easier for hackers is that more and more of our everyday devices are connected to the internet making unauthorized access to these devices much easier to achieve and harder to detect. The Internet of Things is giving rise to a whole new set of security concerns.

As consumers and businesses become more vulnerable to attack, they need to feel more confident that the electronic machines they are using are more secure regardless of the ubiquitous nature of an all-connected world.

In order for providers of these devices to achieve this attack-proof status, they need to invest heavily in design and verification solutions that can secure their hardware designs. However, this added investment comes at a cost. That cost is time. We as consumers still want the latest and greatest electronic gadgetry earlier and earlier putting even more pressure on already hyper-stringent time-to-market targets for electronic providers.

Even with these added pressures, current methods for verifying that the hardware can withstand attack are essentially inadequate due to their non-exhaustive nature. Simulation and emulation methods can leave many corner cases left unchecked and thus exposing the hardware to attackers.

This is where formal analysis can come into play. Formal verification is exhaustive and therefore can find every possible scenario that could leave the hardware device open to hackers.

At DVCon 2014 Jasper technical experts Victor Markus Purri and Lawrence Loh are giving a tutorial on “Formally Verifying Security Aspects of SoC Designs” showing how formal analysis can be applied to this area.

This year’s Jasper User Group Meeting was found to be a great melting pot of design and verification experience and knowledge. Users from all over the globe met for the 2 day conference on October 22 and 23 to discuss the innovative ways they are using Jasper Formal solutions to attack their design and verification challenges. What experiences did Jasper users share? The Jasper User Group boasted 14 user presentations from the following companies on the following topics: (more…)

As a society entrenched in connectivity, we put a great deal of pressure on our portable electronic devices to provide us with more and more computing power and capabilities. Take this blog for example. As I’m traveling, I’m actually writing this blog post on my smart phone. To write this effectively, I need to be able to easily flip back and forth between PowerPoint, Word, and the Internet while still answering emails and the occasional phone call. The fact that my mobile device is able to handle all of these requests with no errors is astonishing given that just a few short years ago, this idea was just “pie in the sky”. The computation complexities that make this possible are staggering. But what is also staggering, is that even more complex designs are being created in ever shrinking time-to-market windows. How do system and SOC companies remain competitive with these seemingly unrealistic expectations?

There are, of course, a myriad of answers to that question, but a critical facet is the use of third-party IP. More and more companies must adopt third-party IP so that they can focus their design on their companies’ core competence. Outsourcing other, proven, capabilities to IP providers saves a great deal of time, energy, and money. However, the use of this third-party IP also introduces new challenges for interface specification, integration, and verification of SoCs on a large scale. These challenges, if not addressed properly, can eliminate any of the productivity gains thought to be realized with the use of third-party IP.

At this year’s ChipEx, STMicroelectronics (ST) will discuss how they used formal methods as a means to improve the productivity of their verification. In particular, they had three key aims:

To close verification projects with appreciably less time and effort than that required by a constrained random approach;

To promote a greater use of assertions by encouraging designers to develop formal properties for their blocks;

To augment or replace legacy in-house flows with mature industry tools. This reduces maintenance overhead and promotes a more robust approach.

They applied formal methods at the unit-level, block-level and the system-level of an ARM based CPU sub-system (see Figure 1). Each project gave different insights into the effectiveness of the formal approach. In order to make an effective evaluation, they developed constrained random alternatives. This allowed them to make direct comparisons and reduced the project’s risk.

A paper at ChipEx will be presented that describes the productivity improvements they experienced using formal methods to verify a critical CPU sub-system that is targeted at mobile applications. In particular, they describe the challenges involved and how a formal tool (Jasper) delivered benefits in terms of effort savings, re-use and insight into IP that was not fully characterized in the context of a new design. The full presentation will also describe their experiences using formal in the context of low-power verification, control status register checking and sequential equivalence.

Figure 1: An ST ARM based CPU sub-system. The shaded blocks were verified using Jasper.

We as consumers want more functionality from our electronic devices whether from our smart phones or household appliances. The problem that we create from these functionality demands is not only an increase in power consumption, but also a significant increase in complexity for how the power in these devices is managed. We as consumers don’t often think about these consequences, but your typical electronic design engineer certainly does.

Today’s electronic designs require that power management and reduction be a central concern throughout the chip design flow from architectural design to RTL implementation and physical design. The power verification dilemma is two-fold. Not only must the design and verification engineer address whether or not the inserted power management circuitry functions correctly, but also that the overall chip functionality is not corrupted by the power intent described in the UPF or CPF descriptions.

Jasper’s formal technology has advanced to the point that it can address a broad range of verification and design issues. With a strong foundation in fundamental proof technology and best-in-class capacity and performance, Jasper’s users now apply the tools and technology to address questions of connectivity, x-propagation, clock-glitch detection, protocol cache coherence, deadlock detection, property synthesis and more.

The added scope and breadth of use of Jasper’s tools and technology is leading users to demand a measurable and quantitative approach that will help correlate the results of formal proofs to verification closure, often expressed in terms of verification coverage. What is needed is a methodology that will correlate formal proof results with coverage. A second requirement is for a methodology that can integrate the coverage results from Jasper’s formal technology with other verification tools (simulation). A third requirement is the ability for Jasper tools to use external coverage data to address areas in the design that are not covered by other verification methodologies.

Enough can’t be said about the power to educate based on experience. At this year’s DAC, a few of Jasper’s top users volunteered to give seminars on their best practices for using Jasper Formal technology. If you happened to miss DAC or did attend but didn’t get a chance to visit the Jasper booth, here’s your chance to view the on-line videos from ST, ARM, and NVIDIA on how they utilized Jasper Formal technology to get ahead in their designs.