Micron's 2-gigabyte and 4-gigabyte parts will ship to other customers this year with channel bandwidth of 120 and 160 gigabytes per second, respectively. For Intel, Micron is customizing a 16-gigabyte part to supply channels optimized to the massively parallel processors on the next-generation Knights Landing Xeon Phi.(Source: Micron)

The original interconnect btwn the Processor & the DRAM stack for HMC was supposed to be serial SERDES. This was in the interest of being able to stay with cheap PCBs rather than have to use more expensive fine pitch substrates ( or even pricier Si interposers made in Fabs ) to accomodate many parallel I/O lines,

From this article it spound like that the Xeon Phi will connect to HMC through massively parallel likes. That will mean that I/O in the HMC will become more like newer HBM that has parallel I/O lines to maintain the bandwidth at relatively low clock rates.

If that is indeed so then what is the substrate material for Xeon ? Si Interpisers like in the AMD Radeon Fury game module ? Or even cheaper organic substrate taht are becoming finer pitch and approaching 2 um line and space.

If so then the HMC will become more power efficient at too high an additional cost over its original concept.

@msporer : You have rightly pitched the discussion, very nice explanation. Thanks for the producing explanations using thickness in numbers.I would like to add here, the increasing heat as the size of die increases is due to the bulk of semiconductor itself as it is not a complete conductor, we can say partly resistor and partly conductor. So if the size increases the heat will surely increase. So its again an area of research for semiconductor designers, thermal engineers will be less responsible for it. This is purely my opinion.

True 3D stacking with TSV in active silicon uses a 10um diameter TSV and a 100um thick wafer. Depending on how many layers could result in 500 to 1000 um total thickness for the stack. This is right within the range of a standard non-TSV die. It is possible to thin the non-TSV die to be the same height as the TSV stack to alleviate major height difference issues. Any minor differences in height will be taken up by the Thermal Interface Material.

Until the thermal conductivity in the 3D stack can be improved, it is only suitable for low power (<10W) memories such as DRAM. Stacking on top of a processor will be limited by thermal and should be expected first in the mobile space. There are many thermal issues to be solved before stacking DRAM on top of a high power processor can be considered.

It would be great if there was an equivalent to Moore's Law for mechanical/thermal engineers, but unfortunately advances in those field are not as rapid as with semiconductor manufacturing. If there were we would all have flying cars, etc.

True, the individual layer will be reduced in thickness, but the 3D stack of the thin layers will be increased in the thickness, and this will require different treatment for sinking heat as compared to heat sinking methods in the 2D chips.

TSV interconnect requires the die are significantly thinned, so the stack of DRAM could be possibly thinner than an adjacent non-TSV die. On the other hand, even though silicon has reasonably good thermal conductivity I understand that very high power processors are thinned to improve heat transfer to the heatsink/spreader which has an even better conductivity.

I know they are going after cost-insensitive apps first because the cost is so high, but I'd be interested if anyone knows and can give some HMC cost information, even just relative to an existing Xeo Phi with external memory.