Abstract: A comparator circuit is applied to comparing an input voltage and a reference voltage to generate a comparison result. The comparator circuit includes a resistor circuit, a current source circuit and a transistor switching circuit. The resistor circuit receives first and second input voltages in the input voltage. The current source circuit provides a first current and a second current, and the first current, the second current and the resistor circuit generate the reference voltage. The transistor switching circuit generates the comparison result at its output end according to a first control voltage and a second control voltage at its input end. The current source circuit and the resistor circuit generate the first control voltage according to the first current and the first input voltage, and generate the second control voltage according to the second current and the second input voltage.

Abstract: An integrated circuit includes a digital-to-analog converter (DAC) core including a plurality of thermometric arms and an R-2R ladder, the DAC core to convert a DAC code to an analog signal. The integrated circuit includes additional components as well. A differential non-linearity (DNL) calibration circuit outputs DNL coefficients based on the DAC code. A memory stores a value indicative of a product of a resistor temperature coefficient (TC) and a resistor self-heating coefficient (SHC). A current DAC (IDAC) couples to the R-2R ladder. A self-heating calibration circuit generates a self-heating trim code based on the value from the memory. An adder adds a value indicative of the DNL coefficients with the self-heating trim code to generate an IDAC trim code and provides the IDAC trim code to the IDAC to trim the R-2R ladder.

Abstract: In accordance with an embodiment, a method for calibrating at least two analog-to-digital converters includes feeding an analog predefined signal to the at least two analog-to-digital converters; converting the analog predefined signal into at least two converter-associated digital values using the at least two analog-to-digital converters, wherein the converting is based on a received clock signal; and adapting a converter-specific time delay based on the at least two converter-associated digital values.

Abstract: The invention is for a system and method of constructing an array of fixed antennas to provide coverage for radio communications to multiple mobile aerial vehicles from a terrestrial location. In one embodiment there is provided antenna system providing radio communications to a plurality or moving aerial vehicles, said system comprising an array of fixed antennas; at least one or a plurality of transceivers selectively connected to the array of fixed antennas; and a control unit configured to switch individual antennas from said array to connect with at least one transceiver. The control unit is configured with a switch matrix to control the connections from the antennas to the plurality of transceivers to implement a desired communications protocol, and the system is further configurable to supply exclusion policies to the control unit which identify which antennas are not to be connected to the switch matrix.

Abstract: The present disclosure relates to a radiation-hardened analog-to-digital converter circuit and its digital signal calibration method capable of efficiently compensating for an external influence or a changed semiconductor element performance, and a recording medium for performing the method.

Abstract: A device for decoding input data including first candidate data and second candidate data by using a polar code, the device includes a first path metric processor configured to generate first candidate path metrics based on a first parent path metric by decoding the first candidate data, determine at least one first child path metric among the first candidate path metrics based on first reliability values of the first candidate path metrics; and a second path metric processor configured to generate second candidate path metrics based on a second parent path metric by decoding the second candidate data, and determine at least one second child path metric among the second candidate path metrics based on second reliability values of the second candidate path metrics, a quantity of the at least one first child path metric being different from a quantity of the at least one second child path metric.

Abstract: A system for regulating an output of a switched mode power supply circuit is configured to provide electric power to a load. The system may include a filter circuit. The filter circuit may be configured to suppress ripple signals at the power output. The system may include a feedback sense circuit including at least one feedback input end and at least one feedback output end. The feedback sense circuit may be configured for generating a feedback signal based on an output ripple signal at a filter input end and a DC regulation signal at a filter output end. The at least one feedback output end may be configured to be electrically coupled to the switched mode power supply circuit. Further, a switching of the switched mode power supply circuit may be based on the feedback signal.

Abstract: A method of forming a planar antenna on a first substrate. An antenna feedline is formed on a peelable copper film of a carrier. A dielectric with no internal conductive layer is formed on the feedline. A planar antenna is formed on one of two parallel sides of the dielectric and a feed port is formed adjacent the other parallel side. The feedline connects the antenna with the feed port. One plane of the planar antenna is configured for perpendicular attachment to a second substrate. The feedline is connected to the planar antenna by a via through the dielectric. The peelable copper is removed and the structure is etched to produce the planar antenna on the substrate. Two planar antennas on substrates can be perpendicularly attached to another substrate to form side-firing antennas.

Abstract: A multi-path dual-switch DAC refers to implementing multiple paths in a switch driver and only two switches in a DAC stack of a DAC unit. In addition to multiple paths configured to improve the driving ability of the input signals, the switch driver of a multi-path dual-switch DAC unit includes two or more logic gates configured to act as multiplexers combining some of the output signals from different paths. The use of such logic gates enables using only two switches in the DAC stack unit to receive the data. Furthermore, optionally, additional logic gates may be used to combine some other output signals from different paths to generate dummy signals, thus providing internal dummy logic. The multi-path dual-switch DACs described herein may advantageously use half-clock rate and reduce or eliminate supply modulation issues, while also reducing power consumption and improving linearity compared to traditional DAC architectures.

Abstract: A smart ring (100) provides multi-mode control in a personal area network (PAN). The smart ring has a fingerprint sensor (106) for identifying upon which finger and which finger segment the smart ring is being worn. A controller (902) of the smart ring (100) enables a predetermined PAN device and PAN control function in response to identified finger and finger segment information (1, 2, 3) matching pre-stored fingerprint information. One of the PAN devices is thus selectively enabled and a predetermined function is controlled, based on identification of the finger and finger segment location of the smart ring (100). Several different PAN devices (narrowband radio, body-worn camera, sensors, gun holster, remote speaker microphone, broadband device, to name a few) can be selectively controlled and varied via rotation of the smart ring (100), making the smart ring well suited for public safety applications.

Abstract: A method and apparatus for calibrating a CDAC-based analog-to-digital converter is disclosed. In one aspect, a calibration method includes: applying a predetermined pattern of voltages to first plates of a group of N capacitors, wherein N is an integer greater than 1; applying a zero voltage to the second plates of the group of N capacitors, wherein the second plates of the group of N capacitors are connected in common; removing the zero voltage to the second plates of the group of N capacitors; applying a zero voltage to all of the first plates of the group of N capacitors; quantizing a voltage on the second plates of the group of N capacitors; converting the quantized voltage on the second plates of the group of N capacitors to an adjustment value; and loading the adjustment value into a lookup table.

Abstract: An accelerated compression method and apparatus are provided. The accelerated compression apparatus includes a look-ahead buffer, a string matching processing pipeline and a control circuit. A string to be compressed extracted from the data register is stored to the look-ahead buffer. P instances are issued in parallel from the look-ahead buffer. When P substrings corresponding to the P instances issued in a first issue cycle are identical, the control circuit sends a first instance and a second instance of the P instances to the string matching processing pipeline for a matching operation and does not send the remaining instances of these P instances to the string matching processing pipeline. In consecutive issue cycles after the first issue cycle, the control circuit does not send any of the P instances to the string matching processing pipeline until the P substrings corresponding to the P instances are not identical.

Abstract: A correction method and a correction circuit for a sigma-delta modulator (SDM) are provided. The SDM includes a loop filter, a quantizer, and a digital-to-analog converter (DAC). The correction method includes: generating a test signal for a frequency to be tested; inputting the test signal to a feedforward circuit that includes at least one adjustable impedance circuit, the test signal being inputted to the SDM through the impedance circuit; calculating an output signal of the SDM to obtain a value of a signal transfer function (STF) of the SDM at the frequency to be tested; and adjusting the impedance circuit.

Abstract: Provided is, for example, an arithmetic coding device capable of coding, at high speed, a symbol sequence including a context symbol and a bypass symbol. The arithmetic coding device updates an occurrence probability of a context symbol for a symbol sequence including the context symbol and a bypass symbol; updates a numerical range for the symbol sequence based on the updated occurrence probability; updates the updated numerical range based on a predetermined probability, the numerical range being a basis of an arithmetic code, the numerical range being updated in accordance with the occurrence probability of the context symbol and the predetermined probability for the bypass symbol; and generates an arithmetic code of the symbol sequence based on the updated numerical range in accordance with a procedure of generating the arithmetic code.

Abstract: A Radio Frequency (RF) device may include a plurality of antennas and one or more conductive traces configured to trap a portion of energy transmitted from at least one of the plurality of antennas. The one or more conductive traces are sized and positioned such that undesired coupling between the plurality of antennas may be suppressed while maintaining performance parameters of at least one of the plurality of antennas. The plurality of antennas and the one or more conductive traces may be formed using a redistribution layer coupled to a chip embedded in a molding layer.

Abstract: An AD conversion apparatus includes an AD conversion unit; a reference voltage switching unit that is disposed between an output of a sensor and an analog input terminal of the AD conversion unit and is connectable to the output of the sensor and a plurality of reference voltage lines; and a control unit to control switching the reference voltage input to the AD conversion unit by connecting the reference voltage switching unit to one of the reference voltage lines and to the output of the sensor. An analog output value of the sensor is input to the analog input terminal of the AD conversion unit via the reference voltage switching unit and is converted into a digital value.

Abstract: An A/D converter includes an A/D conversion circuit for converting an analog output signal into a digital signal, and a control circuit for controlling the A/D conversion circuit. The control circuit acquires a digital signal of a first bit indicating which level regions the voltage level of the analog output signal corresponds to in accordance with a first conversion operation by the A/D conversion circuit, sets a reference voltage corresponding to the level region based on the first bit, amplifies the difference voltage between the analog output signal and the reference voltage to correspond to the A/D conversion input range of the A/D conversion circuit, outputs an amplified analog signal, acquires a digital signal of a second bit indicating the voltage level of the amplified analog signal in accordance with a second conversion operation by the A/D conversion circuit, and synthesizes the first bit and the second bit.

Abstract: An antenna device includes a ground member including a plane part and a plurality of extension parts extending from one end of the plane part in a first direction and arranged along a second direction, a plurality of patch-type radiators arranged on the plane part along the second direction and configured to radiate vertical polarization, and a plurality of straight radiators spaced apart from the ground member, respectively arranged to be adjacent to the plurality of extension parts, extending in the first direction, and configured to radiate horizontal polarization.

Abstract: A hybrid digital-to-analog converter (DAC) driver circuit includes a current-mode DAC driver, a voltage-mode DAC driver, and a combination circuit. The current-mode DAC driver may be configured to receive a first set of bits of a digital input signal and to generate a first analog signal. The voltage-mode DAC driver may be configured to receive a second set of bits of the digital input signal and to generate a second analog signal. The combination circuit may be configured to combine the first analog signal and the second analog signal and to generate an analog output signal. The DAC driver circuit may be terminated by adjusting resistor values of the voltage-mode DAC driver. The current-mode DAC driver and the voltage-mode DAC driver are differential drivers, and may be configured to operate with a single clock signal.