Herve Jaouen
(1 - 10 of 23 results)

A invention provides a transformer for use in integrated circuits, comprising four layers of conductive lines, separated from each other by first, second and third insulating layers. First conductive vias traverse the second insulating layer to connect said second and third pluralities of conducting ...

A method of fabricating an integrated circuit including a monocrystalline silicon substrate, a layer of polycrystalline silicon on the top surface of the substrate and doped with at least two dopants with different rates of diffusion, in which method annealing is performed at a temperature and for a ...

The transistor includes an emitter region 17 disposed in a first isolating well 11, 150 formed in a semiconductor bulk. An extrinsic collector region 16 is disposed in a second isolating well 3, 150 formed in the semiconductor bulk SB and separated laterally from the first well by a bulk separator a ...

A semiconductor device includes a chip forming an integrated circuit; a connection substrate; an internal coupling mechanism; and at least one optical communication system. The connection substrate comprises an external coupling mechanism for electrically coupling to a device other than the chip. Th ...

A method of determining the time for polishing the surface of an integrated circuit wafer on a polishing machine. A sample wafer is fabricated to include at least one high plateau and at least one low plateau joined by a sudden transition. At least one initial profile is topographically scanned, and ...

The semiconductor device comprises a semiconductor substrate (SB) having locally at least one zone (ZL) terminating in the surface of the substrate and entirely bordered, along its lateral edges and its bottom, by an insulating material so as to be completely isolated from the rest of the substrate. ...

A process for fabricating a metal-metal capacitor within an integrated circuit comprises the steps of: producing a first metal electrode, a second metal electrode, and a dielectric layer on top of a lower insulating layer; and depositing an upper insulating layer on top of the two metal electrodes a ...

A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a semiconductor carrier; then forming an interface zone on a top side of the first layer, wherein the interface zone has a structure different fro ...

The invention concerns a method comprising: 1) a first phase including steps which consist in forming in the upper part of a first initial semiconductor substrate a first layer of insulating material above a sectional plane of said first substrate, contacting the first layer of insulating material w ...