In my robot's design, I have a couple of daughterboards running PICs (or
maybe other uC's). I want to design a circuit for supplying power to the
daugherboards.

The main power source is a battery pack that supplies 12V. What I'm trying
to decide is whether I design one extra daughterboard for voltage regulation
or if I include voltage regulation in each one of the daughterboards. Here's
what I see as advantages and disadvantes of each method, please critique.

One VReg
========
Advantages:
- savings in real estate
- savings in power consumption
Disadvantages:
- If I install a diode or a bridge rectifier on the
daughterboard, I won't have 5V for the electronics
because of the v.drop of the diodes
- If one of the daughterboards needs 3.3V instead of 5V,
I will need a vreg on the daughterboard anyway

Distributed VRegs
=================
Advantages:
- Each board is encapsulated, which means I can connect
any voltage (in between vreg specified min and max) that it
will work
- I can select a specific vreg for each board according to its
characteristics (current and voltage needs)
- I may choose a vreg with overvoltage and overcurrent features
- I can implement the reverse polarity diode before the vreg,
therefore the diode voltage drop won't affect the voltage
available for the load
Disadvantages
- real estate
- power consumption

>
>
> This is probably a very basic question, but it is troubling me.
>
> In my robot's design, I have a couple of daughterboards
> running PICs (or maybe other uC's). I want to design a
> circuit for supplying power to the daugherboards.
>

Go with a power bus and re-regulate on each daughter card. Consider
using DC/DC converters to reduce your losses to heat. Somewhat more
expensive than a pile of 7805's but you might be happier in the long
run. And you get to learn something too... There is a 12V to 5V low
current, 2 transistor switcher design floating around. Try searching
the piclist, I think it was something Roman Black did or improved or
contributed to. Also I seem to Russell McMahon has had some posts about
cheap switcher designs.

In the past, I would have had a single regulator and supplied the regulated
power to the daughter boards. Now, I would recommend the opposite. At my
job, we just finished a large logic board design, with many power domains.
Instead of sourcing a power supply that had all the required outputs (5V,
3.3V, 3.1V, 1.8V, etc, etc) the designer used a simple supply that provided
lots of 12 V regulated. Then on the logic board, he put separate PWM voltage
converters for each power domain. It's a much better solution. The PWM
converters are small and simple, and very efficient.

You could also do this with linear regulators, if you didn't mind a bit of
extraneous heat. Supply the boards with about 7 Volts, and locate LDO
regulators on the daughter boards as needed. You can also have multiple
voltages on a daughter board if you like. Or even multiple domains of the
same voltage, so you get your regulation closer to the components. It's a
good thing.

>
> This is probably a very basic question, but it is troubling me.
>
> In my robot's design, I have a couple of daughterboards running PICs (or
> maybe other uC's). I want to design a circuit for supplying power to the
> daugherboards.
>
> The main power source is a battery pack that supplies 12V. What I'm trying
> to decide is whether I design one extra daughterboard for voltage
> regulation
> or if I include voltage regulation in each one of the daughterboards.
> Here's
> what I see as advantages and disadvantes of each method, please critique.
>
> One VReg
> ========
> Advantages:
> - savings in real estate
> - savings in power consumption
> Disadvantages:
> - If I install a diode or a bridge rectifier on the
> daughterboard, I won't have 5V for the electronics
> because of the v.drop of the diodes
> - If one of the daughterboards needs 3.3V instead of 5V,
> I will need a vreg on the daughterboard anyway
>
> Distributed VRegs
> =================
> Advantages:
> - Each board is encapsulated, which means I can connect
> any voltage (in between vreg specified min and max) that it
> will work
> - I can select a specific vreg for each board according to its
> characteristics (current and voltage needs)
> - I may choose a vreg with overvoltage and overcurrent features
> - I can implement the reverse polarity diode before the vreg,
> therefore the diode voltage drop won't affect the voltage
> available for the load
> Disadvantages
> - real estate
> - power consumption
>
> (cost is not really a problem... this is not going to production)
>
>
> Cheers
>
> Padu
>
>

Padu wrote:
> In my robot's design, I have a couple of daughterboards running PICs
> (or maybe other uC's). I want to design a circuit for supplying power
> to the daugherboards.
>
> The main power source is a battery pack that supplies 12V. What I'm
> trying to decide is whether I design one extra daughterboard for
> voltage regulation or if I include voltage regulation in each one of
> the daughterboards. Here's what I see as advantages and disadvantes
> of each method, please critique.

I might put a decent buck regulator on the main board that produces about
5.5 volts, then distribute that to each daughter board. Each board would
have its own LDO to make a nice clean 5V from the rough 5.5V in. Check out
the Microchip MCP1700 LDOs, they are very nice chips if you can guarantee
the input won't exceed 6V.

The advantage of this scheme is that it's reasonably efficient, the
regulator on each board is simple, but each board still has its own clean 5V
bus. If you need 3.3V somewhere, you can probably linearly regulate it from
the 5.5V assuming current draw isn't too high.

Padu wrote:
>> I might put a decent buck regulator on the main board that produces
>> about 5.5 volts, then distribute that to each daughter board.
>
> Do you have any suggestions on which one?
>
> I liked the idea, since there is a big step down from 12V to 5V and
> energy is very precious in my application.

> One VReg Advantages:
> - savings in power consumption
>
I don't think it's safe to assume that a single Vreg saves power. First
of all, if you're using linear regulators, you're going to be
dissipating
power proportional to your load current regardless of how many
regulators
you have. Only the "quiescent" power draw of the regulators is going to
add for each additional regulator, and if you're mostly going from 12V
to 5V, the power lost in regulation is going to dwarf Pq. Using an
unregulated rail allows you to pick regulation technology appropriate to
each daughter card. Low current cards can use simple and cheap linear
regulators. A higher current card might opt for a switching regulator
to gain efficiency. And some cards might benefit from having the 12V
available as well...

> You can
> see it on page
> > two of the schematic at
> http://www.embedinc.com/products/qprot01/qprot> 2.pdf.
>
> sheet2/7 from this design it's a very good
> prove about what is
> happening if a good software PIC programmer is designing hardware...
>
> Take a critical look to the Q6, Q4 and Q2 and see the redudancy.

I am probably a programmer, I don't see the redundancy. Q6 brings the
voltage swing up to the 11-38V level, Q4/Q2 give it the muscle to drive
Q3. What is redundant?

>-----Original Message-----
>From: piclist-bouncesKILLspammit.edu [.....piclist-bouncesKILLspam.....mit.edu]
>Sent: 02 November 2005 09:06
>To: Microcontroller discussion list - Public.
>Subject: Re: [EE] Help deciding on voltage regulation
>
>
>On 11/2/05, Olin Lathrop <EraseMEolin_piclistspam_OUTTakeThisOuTembedinc.com> wrote:
>> Padu wrote:
>> >> I might put a decent buck regulator on the main board
>that produces
>> >> about 5.5 volts, then distribute that to each daughter board.
>> >
>> > Do you have any suggestions on which one?
>> >
>> > I liked the idea, since there is a big step down from 12V
>to 5V and
>> > energy is very precious in my application.
>>
>> My knee jerk reaction is something like the 5.5V power supply of the
>> QuickProto-01 (http://www.embedinc.com/products). You can see it on
>> page two of the schematic at
>> http://www.embedinc.com/products/qprot01/qprot2.pdf.
>
>Olin,
>sheet2/7 from this design it's a very good prove about what is
>happening if a good software PIC programmer is designing hardware...
>
>Take a critical look to the Q6, Q4 and Q2 and see the redudancy.
>
>cheers,
>Vasile

Vasile,

I guess you have little experience of driving power MOSFETs in high frequency switching applications?

The driver needs to have a high current capability in order to charge/discharge the (significant) gate capacitance of the MOSFET to minimise the time spent in the linear region. Failure to do this results in poor efficiency and high power dissipation. A single NPN with resistive collector load does not (usualy) satisfy these requirements unless the resistor has a very low value, which again increases power dissipation and reduces efficiency.

Regards

Mike

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> > I might put a decent buck regulator on the main board that produces
> > about
> > 5.5 volts, then distribute that to each daughter board.
> <snip>
>
> Do you have any suggestions on which one?
>
> I liked the idea, since there is a big step down from 12V to
> 5V and energy is very precious in my application.

If energy losses over cable are not an issue for you, you can go with 5,5 master voltage.

But I would take 12V. That means lower current on the connections. On the slave side, I would take a high efficient LT or micrel switcher (80%-90%).
Linear LDO´s are just a waste of energy ...

If you have power-supplies on every slave, and you connect them, please take care about ground and vcc loops between the boards to prevent any kind of self-oscillation.

> I guess you have little experience of driving power MOSFETs in high
> frequency switching applications?
>
> The driver needs to have a high current capability in order to
> charge/discharge the (significant) gate capacitance of the MOSFET to
> minimise the time spent in the linear region. Failure to do this
> results in poor efficiency and high power dissipation. A single NPN
> with resistive collector load does not (usualy) satisfy these
> requirements unless the resistor has a very low value, which again
> increases power dissipation and reduces efficiency.

/>

_____________________

The driver is fairly standard and a good safe bet.

As Vasile intimates, you *MAY* be able to save a few cents by removing
R5, adding a base drive resistor for Q5 (parts neutral), removing C11,
adding a cap across the Q6 base drive resistor as a speed up cap
(still parts neutral so far), remove Q4, place diode across Q2 emitter
to base cathode to emitter. Saves one transistor, costs a diode. Diode
can often be a 1N4148. Diode now provides the low side drive for Q3
via Q6.

R5 is strictly not needed BUT I'd consider adding a small series gate
drive resistor her to limit gate currrent to stop really really hard
switching which can also increase losses.

The reduction by one transistor is unlikely to be worthwhile.
R4 can be increased until speed becomes an issue - which may be at 2K
as that's what Olin's used.

****************** BUT *******************

as shown this circuit has a major problem.

Vgs_max for the IRF7416 is -20 volts and when supply voltage is much
above 20 volts the FET will be driven into a potentially (pun almost
intended) fatal state.
Adding a series resistor Q6_C to Q2/4_B will allow this to be
fixed, but will introduce drive speed issues.

Returning Q4_C to a positive potential less than 20v below Vin with a
suitable reservoir capacitor will fix the overdrive problem. This can
be a resistor/zener/cap supply and needs not supply much current as,
while the FET gate drive should be 100's of mA to 1A ish (as Michael
noted) the mean current is low as the peaks occur only during
switching.

Vasile Surducan wrote:
>> You can see it on page two of the schematic at
>> http://www.embedinc.com/products/qprot01/qprot2.pdf.
>
> sheet2/7 from this design it's a very good prove about what is
> happening if a good software PIC programmer is designing hardware...

Actually I'm a hardware designer that does a lot of software/firmware too.

> Take a critical look to the Q6, Q4 and Q2 and see the redudancy.

I looked at it sideways, upside down, and inside out and I don't see
redundancy. These three transistors together take the ground-referenced GP2
PIC output and cause it to drive the gate of the high side FET Q3. In other
words, they form a high side FET driver.

The 0-5V PIC output drives the base of Q6. R9 on the emitter causes the
collector of Q6 to act like a switchable current sink. Assume Q6 has a
700mV B-E drop, then the emitter current will be (5.0V - 700mv) / 750ohms =
5.7mA. Q6 has pretty decent gain, so this is basically the current that
will be sunk by its collector when the PIC pin is high. This current causes
a voltage accross R4, which is 2Kohms. 5.7mA x 2Kohms = 11.5V. So the
bottom end of R4 will be at the input supply rail when the PIC GP2 output is
low, and 11.5V below that rail when the PIC output is high. Q2 and Q4 are
both emitter followers. These provide much higher current drive for the
signal on the low side of R4. This lower impedence signal drives the gate
of Q3. The reason for lowering the impedence from 2Kohms to about 20-40
ohms is to overcome the considerable effective capacitance of the FET gate
quickly. A little voltage is lost in the process, but the FET gate will
still be driven with about 11V, which is plenty to solidly turn on that FET.
R5 is there to make sure the FET is off on startup and to eventually bring
the FET gate to 0 (with respect to the FET source) when nothing is going on.

C11 on the emitter of Q6 sharpens the edges of the current sink. When the
PIC output goes high, the emitter current is much higher than the 5.7mA
steady state for a short time. This is just enough time at higher current
to overcome the other capacitances on R4 and the bases of Q2 and Q4 and the
wiring to bring the bottom side of R4 to its on level quickly. Once there
the steady state current thru R9 takes over and maintains it there. The
100pF value of C11 was determined experimentally since it is impossible to
calculate all the parasitic capacitance effects. C11 also helps at turn
off. Bipolar transistors are slowest at turning off since charge lingers in
the base until used up by causing collector current. When the PIC output is
brought low, the B-E junction is actually reversed biased for a very short
time causing some of the base charge to be actively sucked out turning the
transistor off quickly.

Do you still think Q6, Q4, and Q2 are redundant? If so, show me an
alternative for a low side PIC to drive a high side P-channel FET gate.

> remove Q4, place diode across Q2 emitter
> to base cathode to emitter. Saves one transistor, costs a diode. Diode
> can often be a 1N4148.

Note that a diode is about the same price as a transistor.

> Diode now provides the low side drive for Q3
> via Q6.
>
> R5 is strictly not needed BUT I'd consider adding a small series gate
> drive resistor her to limit gate currrent to stop really really hard
> switching which can also increase losses.

There is no chance my original circuit can overdrive the gate of Q3. Even
if Q2 and Q4 have infinite gain and therefore they present the R4 voltage to
Q3 with zero impedence, the rise and fall time on R4 just isn't and can't be
fast enough to cause problems.

> The reduction by one transistor is unlikely to be worthwhile.
> R4 can be increased until speed becomes an issue - which may be at 2K
> as that's what Olin's used.
>
> ****************** BUT *******************
>
> as shown this circuit has a major problem.
>
> Vgs_max for the IRF7416 is -20 volts and when supply voltage is much
> above 20 volts the FET will be driven into a potentially (pun almost
> intended) fatal state.

This is a problem only with your altered version. I think you are missing
the big point that Q6 acts as a controlled current sink when the PIC output
is high. This causes a fixed voltage drop accross R4 regardless of the
input supply rail voltage. See my other response to Vasile. The Q3 gate
drive remains about 11V regardless of input supply voltage level.

Russell McMahon <apptechspam_OUTparadise.net.nz> wrote:
> ****************** BUT *******************
> as shown this circuit has a major problem.
>
> Vgs_max for the IRF7416 is -20 volts and when supply voltage is much
> above 20 volts the FET will be driven into a potentially (pun almost
> intended) fatal state.

Don't you see that the Vgs on Q3 is limited by the ratio of R4 to R8?

Q6 is a current sink driven by the regulated 5.0V supply to the
PIC10F204, and the drop across R4 will be controlled by that current.

With the component values shown, the current through Q6 will be
4.3V / 750ohms = 5.733 mA, and this produces a drop across R4 of
5.733 mA * 2000 ohms = 11.5 V, which is replicated by the emitter
follower driver stage. The excess supply voltage, if any, appears
across Q6 and Q4. No problem at all.

Xiaofan Chen wrote:
> Actually I see some problems with the selection of components in Olin's
> schematics. Maybe they are not a big problem for hobbyists though.
>
> 1) Voltage rating of C1/C2/C3 is only 35V. This may be a bit low if the
> input voltage is really 30V with big ripples.

But it's not. The voltage is specified as 30V maximum, including any ripple
from an AC power source. When used with the recommended wall wart in the
US, that rail will be at about 25V.

> 2) I'd like to see a fuse in the input and a zener (over voltage
> protection) after
> the buck converter to protect the other parts.

After the buck converter? I don't see the point since the job of the buck
is to make about 5.5V. Unless it physically breaks, the output won't exceed
6V, which is the maximum input rating for the 5.0V linear regulator IC1.

It is the user's responsibility to ensure the input voltage stays within
specification. Like any specification, you can't violate it and then
complain if the unit breaks. A line has to be drawn somewhere. No amount
of circuitry can guarantee it won't break at all possible voltage levels.
The question is therefore what is a good tradeoff between allowing a wide
input voltage range versus the cost of supporting it while maximizing
lifetime profits for the product. There is no way to know the right answer,
but I do think extra protection circuitry would not be worth the very rare
case when it would be useful. Customers are usually not willing to spend a
lot of money to protect themselves from their own stupidity or from rare
part failures.

One exception is the optional clamp circuit on page 1. This is intended for
automotive 12V supplies where large voltage spikes do occur regularly beyond
the end user's control. To keep the cost reasonable and allow a wider input
voltage range for the normal case, this clamp circuit is unpopulated but the
pads are provided.

> 3) As Russel said, normally there will be a small series gate resistor
> is good to have.

Yes, this is a common religious conviction. Think about *why* such a series
gate resistor is often used and you can see that it's not necessary in this
case. The edges on R4 just can't be that fast, so even if Q2 and Q4 have
infinite gain there won't be a problem.

> Vasile Surducan wrote:
> >> You can see it on page two of the schematic at
> >> www.embedinc.com/products/qprot01/qprot2.pdf.
> >
> > sheet2/7 from this design it's a very good prove about what is
> > happening if a good software PIC programmer is designing hardware...
>
> Actually I'm a hardware designer that does a lot of software/firmware too.
>
> > Take a critical look to the Q6, Q4 and Q2 and see the redudancy.
>
> I looked at it sideways, upside down, and inside out and I don't see
> redundancy. These three transistors together take the ground-referenced GP2
> PIC output and cause it to drive the gate of the high side FET Q3. In other
> words, they form a high side FET driver.
>
> The 0-5V PIC output drives the base of Q6. R9 on the emitter causes the
> collector of Q6 to act like a switchable current sink. Assume Q6 has a
> 700mV B-E drop, then the emitter current will be (5.0V - 700mv) / 750ohms =
> 5.7mA. Q6 has pretty decent gain, so this is basically the current that
> will be sunk by its collector when the PIC pin is high. This current causes
> a voltage accross R4, which is 2Kohms. 5.7mA x 2Kohms = 11.5V. So the
> bottom end of R4 will be at the input supply rail when the PIC GP2 output is
> low, and 11.5V below that rail when the PIC output is high. Q2 and Q4 are
> both emitter followers. These provide much higher current drive for the
> signal on the low side of R4. This lower impedence signal drives the gate
> of Q3. The reason for lowering the impedence from 2Kohms to about 20-40
> ohms is to overcome the considerable effective capacitance of the FET gate
> quickly. A little voltage is lost in the process, but the FET gate will
> still be driven with about 11V, which is plenty to solidly turn on that FET.
> R5 is there to make sure the FET is off on startup and to eventually bring
> the FET gate to 0 (with respect to the FET source) when nothing is going on.
>
> C11 on the emitter of Q6 sharpens the edges of the current sink. When the
> PIC output goes high, the emitter current is much higher than the 5.7mA
> steady state for a short time. This is just enough time at higher current
> to overcome the other capacitances on R4 and the bases of Q2 and Q4 and the
> wiring to bring the bottom side of R4 to its on level quickly. Once there
> the steady state current thru R9 takes over and maintains it there. The
> 100pF value of C11 was determined experimentally since it is impossible to
> calculate all the parasitic capacitance effects. C11 also helps at turn
> off. Bipolar transistors are slowest at turning off since charge lingers in
> the base until used up by causing collector current. When the PIC output is
> brought low, the B-E junction is actually reversed biased for a very short
> time causing some of the base charge to be actively sucked out turning the
> transistor off quickly.
>
> Do you still think Q6, Q4, and Q2 are redundant? If so, show me an
> alternative for a low side PIC to drive a high side P-channel FET gate.

Maybe we should start with naming the most important parameter which
has never been mentioned here: which is the switching frequency and
which is the maximum current load? I can guess is not so high as
Russel believes (see the inductance value which is quite big and
dimensioned at max 1.6A that shows a continous current less than
0.5...0.8A, but also there are two huge capacitors Q9 and Q10 with low
ESR which are drawing a lot of ripple current). I think the schematic
it does not need such big engineering in driving the power FET.
Compute how big is the 2K * Ciss compared with the switching time
(which is producing Q3 dissipation). Ciss is about 2nF at a switching
frequency of about 1MHz and Vgs=0V (I doubt you can switch Q3 from
PIC10F at this frequency, so probably it's less than half). So the
estimated time constant Tau is about 4 microseconds, does the
4microseconds switching delay killing your FET ?
R4 and C11 could dissapears. Instead those two a resistor in the Q6
base. If need a switching acceleration scheme could be there in the
base of Q6. I bet the schematic is working the same without Q2 and Q4
if you choose the correct Vgsoff for the Q3 (maybe you need another
small resistor between the lower end of R4 and the Q6 colector if
indeed you're supplying this at 30V, IRF7416 has an VGS of +/-20V and
an VBRDSS of 30V)
I presume the real supply never excedeed 15-20V. Also if the Q3 it's
packed in SO8 package, than have only 2.5W maximum dissipated power.
So it's not a power supply.

This is not about the schematic's cost, one or two transistors does
not count, it's about the way you've think it.
:)

> On 11/2/05, Olin Lathrop <RemoveMEolin_piclistTakeThisOuTembedinc.com> wrote:
> > Vasile Surducan wrote:
> > >> You can see it on page two of the schematic at
> > >> www.embedinc.com/products/qprot01/qprot2.pdf.
> > >
> > > sheet2/7 from this design it's a very good prove about what is
> > > happening if a good software PIC programmer is designing hardware...
> >
> > Actually I'm a hardware designer that does a lot of software/firmware too.
> >
> > > Take a critical look to the Q6, Q4 and Q2 and see the redudancy.
> >
> > I looked at it sideways, upside down, and inside out and I don't see
> > redundancy. These three transistors together take the ground-referenced GP2
> > PIC output and cause it to drive the gate of the high side FET Q3. In other
> > words, they form a high side FET driver.
> >
> > The 0-5V PIC output drives the base of Q6. R9 on the emitter causes the
> > collector of Q6 to act like a switchable current sink. Assume Q6 has a
> > 700mV B-E drop, then the emitter current will be (5.0V - 700mv) / 750ohms =
> > 5.7mA. Q6 has pretty decent gain, so this is basically the current that
> > will be sunk by its collector when the PIC pin is high. This current causes
> > a voltage accross R4, which is 2Kohms. 5.7mA x 2Kohms = 11.5V. So the
> > bottom end of R4 will be at the input supply rail when the PIC GP2 output is
> > low, and 11.5V below that rail when the PIC output is high. Q2 and Q4 are
> > both emitter followers. These provide much higher current drive for the
> > signal on the low side of R4. This lower impedence signal drives the gate
> > of Q3. The reason for lowering the impedence from 2Kohms to about 20-40
> > ohms is to overcome the considerable effective capacitance of the FET gate
> > quickly. A little voltage is lost in the process, but the FET gate will
> > still be driven with about 11V, which is plenty to solidly turn on that FET.
> > R5 is there to make sure the FET is off on startup and to eventually bring
> > the FET gate to 0 (with respect to the FET source) when nothing is going on.
> >
> > C11 on the emitter of Q6 sharpens the edges of the current sink. When the
> > PIC output goes high, the emitter current is much higher than the 5.7mA
> > steady state for a short time. This is just enough time at higher current
> > to overcome the other capacitances on R4 and the bases of Q2 and Q4 and the
> > wiring to bring the bottom side of R4 to its on level quickly. Once there
> > the steady state current thru R9 takes over and maintains it there. The
> > 100pF value of C11 was determined experimentally since it is impossible to
> > calculate all the parasitic capacitance effects. C11 also helps at turn
> > off. Bipolar transistors are slowest at turning off since charge lingers in
> > the base until used up by causing collector current. When the PIC output is
> > brought low, the B-E junction is actually reversed biased for a very short
> > time causing some of the base charge to be actively sucked out turning the
> > transistor off quickly.
> >
> > Do you still think Q6, Q4, and Q2 are redundant? If so, show me an
> > alternative for a low side PIC to drive a high side P-channel FET gate.
>
> Maybe we should start with naming the most important parameter which
> has never been mentioned here: which is the switching frequency and
> which is the maximum current load? I can guess is not so high as
> Russel believes (see the inductance value which is quite big and
> dimensioned at max 1.6A that shows a continous current less than
> 0.5...0.8A, but also there are two huge capacitors Q9 and Q10 with low
> ESR which are drawing a lot of ripple current). I think the schematic
> it does not need such big engineering in driving the power FET.
> Compute how big is the 2K * Ciss compared with the switching time
> (which is producing Q3 dissipation). Ciss is about 2nF at a switching
> frequency of about 1MHz and Vgs=0V (I doubt you can switch Q3 from
> PIC10F at this frequency, so probably it's less than half). So the
> estimated time constant Tau is about 4 microseconds, does the
> 4microseconds switching delay killing your FET ?
> R4 and C11 could dissapears. Instead those two a resistor in the Q6
> base. If need a switching acceleration scheme could be there in the
> base of Q6. I bet the schematic is working the same without Q2 and Q4
> if you choose the correct Vgsoff for the Q3 (maybe you need another
> small resistor between the lower end of R4 and the Q6 colector if
> indeed you're supplying this at 30V, IRF7416 has an VGS of +/-20V and
> an VBRDSS of 30V)
> I presume the real supply never excedeed 15-20V. Also if the Q3 it's
> packed in SO8 package, than have only 2.5W maximum dissipated power.
> So it's not a power supply.

oops, I mean it's not a high power supply...
>
> This is not about the schematic's cost, one or two transistors does
> not count, it's about the way you've think it.
> :)
>
> cheers,
> Vasile
>

> Compute how big is the 2K * Ciss compared with the switching time
> (which is producing Q3 dissipation). Ciss is about 2nF at a switching
> frequency of about 1MHz and Vgs=0V (I doubt you can switch Q3 from
> PIC10F at this frequency, so probably it's less than half). So the
> estimated time constant Tau is about 4 microseconds, does the
> 4microseconds switching delay killing your FET ?

You are forgetting that the Q2,Q4 emitter followers greatly lower the
apparent impedence of R4 as seen from the gate of Q3, and the time constant
is significantly shorter because of that. This is precisely why Q2,Q4 are
there.

> R4 and C11 could dissapears.

C11 only speeds up the switching edges a bit, and could be deleted resulting
in a small loss of efficiency. However R4 is central to the design. It
converts the current of the current sink Q6 to a voltage, which is then
presented to the gate after buffering by Q2,Q4.

> Instead those two a resistor in the Q6
> base. If need a switching acceleration scheme could be there in the
> base of Q6.

You are missing the same point as Russell. Q6 forms a constant current sink
when on. This allows the switching step size accross R4 to be the same
regardless of input voltage. In other words, the constant current sink
decouples the switching signal from its ground reference.

> I bet the schematic is working the same without Q2 and Q4

The switching edges would be much slower. Too slow for it to even work
properly given the rest of the parameters.

> I presume the real supply never excedeed 15-20V.

Nope. It is about 25V if the recommended wall wart is used, and I've tested
it accross the full range of course.

> Also if the Q3 it's
> packed in SO8 package, than have only 2.5W maximum dissipated power.
> So it's not a power supply.

Huh? The point of a switcher is that the switching element spends most of
its time either full on or full off, thereby dissipating little power. Q3
doesn't dissipate much power and doesn't need to be in a large package. In
practise it's hard to tell it got warm. In fact, the input diodes get
warmer than any part of the switcher.

And Olin has decided to engineer a robust design, rather than trim every last penny out of it.

Regards

Mike

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