The transition from silicon technologies to alternative ones has been touted as an inevitable development that will affect the architectural research agenda for computing. Henceforth, the computing scenario beyond silicon-based electronics is grounded as a technical grand challenge of enormous impact on society, not just as a research topic in Computer Science and Engineering. This paper is a contribution to the establishment of a Grand Challenge research agenda that addresses fundamental challenges in the field of nanoand microelectronics that definitely will impact Computing. This work proposes a likely scenario for hardware technology evolution and challenges for the next 20 years, which were not at all dealt with in the document of the Grand Challenges by Brazilian Computer Science, 2006. In that time frame both radically new and evolutionary technologies will emerge, evolve and will be gradually selected. This paper contends that such selection will occur to make those technologies compatible with nano-scaled CMOS in silicon, not to replace it entirely. We propose that transitional technologies will rather co-exist and be built upon a basic CMOS technology platform. Radically new devices at the 1-10 nm scale will most likely be built on a silicon substrate with the same technical requirements (such as cleanness, lithographic resolution, etc) of current CMOS industry. The authors propose a more concrete scenario for architectural challenges, which dismisses the belief that multidisciplinary research on very diverse technologies (from materials to abstract computing systems) will lead the computer engineering into a post-silicon era. Such multidisciplinary research is even more important today, but it is far from leading to a non-silicon scenario. The grand challenges from the Computer Science point of view are refined into a more realistic transition: total replacement of CMOS will not occur for at least 20 years, instead new forms of integration, hierarchically ordered from the micron-level, to sub-micron level (500nm to 100nm), down to nano-scaled transistors in silicon (further down to 10 nm). In this hierarchy, at the bottom, it is highly possible that disruptive molecular-level devices (self-assembled in the scale of 2 to 10 nanometers) will eventually be production-worthy for Giga- and Terascale devices integration. Structures like graphene-based carbon tubes or planes are the most viable candidates for molecular devices. There is little assurance that overcoming the major technology barriers will happen in the next 10 years for carbon electronics. In this paper the computer-systems relevant issues of systems power dissipation, hardware design complexity, resilience to systems failures and fraud are dealt with as the overwhelming, challenging computing research topics that will guide future research in computing architectures at the giga-scale integration beyond 2020.