The most challenging part of last year's iPhone 5s review was piecing together details about Apple's A7 without any internal Apple assistance. I had less than a week to turn the review around and limited access to tools (much less time to develop them on my own) to figure out what Apple had done to double CPU performance without scaling frequency. The end result was an (incorrect) assumption that Apple had simply evolved its first ARMv7 architecture (codename: Swift). Based on the limited information I had at the time I assumed Apple simply addressed some low hanging fruit (e.g. memory access latency) in building Cyclone, its first 64-bit ARMv8 core. By the time the iPad Air review rolled around, I had more knowledge of what was underneath the hood:

As far as I can tell, peak issue width of Cyclone is 6 instructions. That’s at least 2x the width of Swift and Krait, and at best more than 3x the width depending on instruction mix. Limitations on co-issuing FP and integer math have also been lifted as you can run up to four integer adds and two FP adds in parallel. You can also perform up to two loads or stores per clock.

With Swift, I had the luxury of Apple committing LLVM changes that not only gave me the code name but also confirmed the size of the machine (3-wide OoO core, 2 ALUs, 1 load/store unit). With Cyclone however, Apple held off on any public commits. Figuring out the codename and its architecture required a lot of digging.

Last week, the same reader who pointed me at the Swift details let me know that Apple revealed Cyclone microarchitectural details in LLVM commits made a few days ago (thanks again R!). Although I empirically verified many of Cyclone's features in advance of the iPad Air review last year, today we have some more concrete information on what Apple's first 64-bit ARMv8 architecture looks like.

Note that everything below is based on Apple's LLVM commits (and confirmed by my own testing where possible).

Apple Custom CPU Core Comparison

Apple A6

Apple A7

CPU Codename

Swift

Cyclone

ARM ISA

ARMv7-A (32-bit)

ARMv8-A (32/64-bit)

Issue Width

3 micro-ops

6 micro-ops

Reorder Buffer Size

45 micro-ops

192 micro-ops

Branch Mispredict Penalty

14 cycles

16 cycles (14 - 19)

Integer ALUs

2

4

Load/Store Units

1

2

Load Latency

3 cycles

4 cycles

Branch Units

1

2

Indirect Branch Units

0

1

FP/NEON ALUs

?

3

L1 Cache

32KB I$ + 32KB D$

64KB I$ + 64KB D$

L2 Cache

1MB

1MB

L3 Cache

-

4MB

As I mentioned in the iPad Air review, Cyclone is a wide machine. It can decode, issue, execute and retire up to 6 instructions/micro-ops per clock. I verified this during my iPad Air review by executing four integer adds and two FP adds in parallel. The same test on Swift actually yields fewer than 3 concurrent operations, likely because of an inability to issue to all integer and FP pipes in parallel. Similar limits exist with Krait.

I also noted an increase in overall machine size in my initial tinkering with Cyclone. Apple's LLVM commits indicate a massive 192 entry reorder buffer (coincidentally the same size as Haswell's ROB). Mispredict penalty goes up slightly compared to Swift, but Apple does present a range of values (14 - 19 cycles). This also happens to be the same range as Sandy Bridge and later Intel Core architectures (including Haswell). Given how much larger Cyclone is, a doubling of L1 cache sizes makes a lot of sense.

On the execution side Cyclone doubles the number of integer ALUs, load/store units and branch units. Cyclone also adds a unit for indirect branches and at least one more FP pipe. Cyclone can sustain three FP operations in parallel (including 3 FP/NEON adds). The third FP/NEON pipe is used for div and sqrt operations, the machine can only execute two FP/NEON muls in parallel.

I also found references to buffer sizes for each unit, which I'm assuming are the number of micro-ops that feed each unit. I don't believe Cyclone has a unified scheduler ahead of all of its execution units and instead has statically partitioned buffers in front of each port. I've put all of this information into the crude diagram below:

Unfortunately I don't have enough data on Swift to really produce a decent comparison image. With six decoders and nine ports to execution units, Cyclone is big. As I mentioned before, it's bigger than anything else that goes in a phone. Apple didn't build a Krait/Silvermont competitor, it built something much closer to Intel's big cores. At the launch of the iPhone 5s, Apple referred to the A7 as being "desktop class" - it turns out that wasn't an exaggeration.

Cyclone is a bold move by Apple, but not one that is without its challenges. I still find that there are almost no applications on iOS that really take advantage of the CPU power underneath the hood. More than anything Apple needs first party software that really demonstrates what's possible. The challenge is that at full tilt a pair of Cyclone cores can consume quite a bit of power. So for now, Cyclone's performance is really used to exploit race to sleep and get the device into a low power state as quickly as possible. The other problem I see is that although Cyclone is incredibly forward looking, it launched in devices with only 1GB of RAM. It's very likely that you'll run into memory limits before you hit CPU performance limits if you plan on keeping your device for a long time.

The real question is where does Apple go from here? By now we know to expect an "A8" branded Apple SoC in the iPhone 6 and iPad Air successors later this year. There's little benefit in going substantially wider than Cyclone, but there's still a ton of room to improve performance. One obvious example would be through frequency scaling. Cyclone is clocked very conservatively (1.3GHz in the 5s/iPad mini with Retina Display and 1.4GHz in the iPad Air), assuming Apple moves to a 20nm process later this year it should be possible to get some performance by increasing clock speed scaling without a power penalty. I suspect Apple has more tricks up its sleeve than that however. Swift and Cyclone were two tocks in a row by Intel's definition, a third in 3 years would be unusual but not impossible (Intel sort of committed to doing the same with Saltwell/Silvermont/Airmont in 2012 - 2014).

Looking at Cyclone makes one thing very clear: the rest of the players in the ultra mobile CPU space didn't aim high enough. I wonder what happens next round.

@maysider Apple did create this processor. They have been a involved in ARM since the 1980s, in 2008 Apple purchased P.A. Semi, one of the largest purchases Apple has ever made, and they now have thousands of engineers working full time to design their custom implementation of the ARM specification.Reply

They actually did create ARM through their partnership with Acorn. It was their work to develop and deliver the Newton PDA that caused them to form a joint venture with Acorn and develop the ARM Architecture based on work that started at Acorn. It's the reason why ARM processors always worked so well for the handheld and embedded markets.Reply

Specifically here: The British company Acorn completely designed and produced many generation of ARM chips for their Archimedes RISC Workstation. At the time, ARM stood for "Acorn RISC Machines." When Apple made the Newton, they worked with Acorn to spin off their chip division and set it up as its own company, ARM, changing the acronym to Advanced Risc Machines. So Acorn made the ARM chip, and Apple made the ARM company. At this point, though, Apple COMPLETELY designs the internals of the chip, keeping just the ISA intact.Reply

They've got to be aiming for more than just a good competitor to Qualcomm. Either they literally want to eventually push ARM into the low end of their laptop range, or (much more likely) they see the iPad being able to someday replace desktops for a lot of use cases and are building the chip for it. I'm a little surprised that Samsung so far seems content buying Qualcomm chips in the US and using stock ARM cores in their own chips; in the long run, having one's own chip IP seems valuable.Reply

Apple is an investor in Imagination and so is Intel. Apple uses Rogue and Intel does the same for BT and subsequent SoCs. So if Apple would go with Nvidia and uses the Maxwell mobile core with Cyclone V2, then they could well be untouchable by Qualcomm or anyone else. This move is what I would call "Friends and enemies culling". Apple would kick Intel, QC and other Arm vendors and amass leadership in the SoC business to themselves exclusively, then segment their market into Hi-end, medium and low SoC to target pricepoints for both tablets and phones to match.It is a mean move. But will NV agree to licensing K1/M1 exclusively for 5 years or so ?. Hey, NV has been expanding the IVI market and growing it. This can mutually benefit Apple as well in CarPlay interface etc, so there is synergy in business. The mutual interest matches!.Reply