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AR# 21137

Description

General Description:

Is the SPI4.2 v6.2 Core compatible with ISE7.1i?

Solution

The v6.2 of the SPI4.2 Core is officially supported on the ISE6.3i tool, and the core cannot be generated with the ISE7.1i CORE Generator. If you already have the SPI4.2 v6.2 Core generated using CORE Generator from ISE6.3i, then it is possible to implement (translate, MAP, PAR, BitGen) the design using ISE 7.1i.

If you have SPI4.2 Core configured for Static Alignment Mode, the core will implement fine in ISE7.1i without any issue.

If you have SPI4.2 Core configured for Dynamic Alignment Mode (DPA), then use the work-around mentioned below to avoid the MAP error such as:

"ERROR:MapLib:688 - Pin CATALIN in LOCK_PINS constraint does not exist."

SPI4.2 v6.2 DPA Work-around for ISE7.1i

Unix/Linux

1. Generate the SPI-4.2 v6.2 Core in the 6.3i software (can be skipped if a core has already been generated).