A Practical Approach to Verifying RFICs with Fast Mismatch Analysis

Why this presentation is important:
While there are several approaches for block and functional path level performance verification, most RF designers rely on corner and mismatch analysis as the workhorse for the bulk of their verification. This verification phase still consumes the largest percentage of simulation licenses, puts constraints on compute resource availability, and as the de facto signoff criteria at block and functional path level, is a gating factor in reducing time to tape out. Any technique that can address these issues while achieving the same level of verification quality delivers value to RF design and product managers, IT professionals, and RF design engineers. This webcast introduces a new Fast Mismatch analysis that delivers the same level of accuracy with the benefit of significantly reducing overall cost, verification time, and increased compute resource availability.

Who should attend:
If you will be designing, verifying, supporting or managing the verification of complex RF circuit blocks and RF transmitters and receivers in highly integrated RFICs, this Webcast is dedicated to you. This webcast introduces a new Fast Mismatch analysis that delivers the same level of accuracy as traditional mismatch analysis with the benefit of significantly reducing overall cost, verification time, and increased compute resource availability.