The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.

A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.

Arm utilizes Cadence® tools to develop its IP. We have early access to Arm cores, so we can tune our tool algorithms, features, and options, and can optimize our flow before the official release of the Arm cores. All of this leads to an added PPA and turnaround time (TAT) boost on top of generic EDA reference flow results.

Flows are available for many Arm Cortex®-A, Cortex-R, Cortex-M, and NeoverseTM cores, multimedia products (GPUs, display controllers, video controllers), and interconnect cores. You’ll get an optimized starting point of scripts, floorplans, and documentation for these CPU and GPU configurations as well as for popular foundry process technologies, including FinFET and other advanced nodes.

Fast Turnaround with Predictable PPA

As you implement the Arm cores on Cadence’s RTL-to-signoff flow, we bring in experienced R&D staff and product engineers who have worked closely with Arm to build reference flows. These technical experts also have experience helping with the PPA push on several tapeouts worldwide on advanced Arm designs, spanning a range of technologies from 40nm to 10nm and below.

Cadence’s digital implementation reference flows are supported by our early collaboration with Arm. With our reference flows, you get design techniques, from RTL to GDSII, for Arm processors, reducing time to silicon with predictable PPA results. Contact your Cadence Sales representative for more information. The flows are also optimized with Arm POP™ IP core-hardening acceleration technology. Using these flows, you’ll be equipped to efficiently produce optimized SoCs based on Arm big.LITTLE™ processing systems.

Optimizing for Low Power

Cadence provides a comprehensive solution to design, verify, and optimize power consumption on Arm-based SoCs:

We partnered closely with Cadence to utilize the Innovus Implementation System during the development of our ARM Cortex-A72 processor. This demonstrated a 5X runtime improvement over previous projects and will deliver more than 2.6GHz performance within our area target.