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Recon Industrial Controls has announced LabRecon, a software and hardware product that enables users to create rich graphical interfaces for “remote” IoT or “local” measurement and control applications. A drag-and-drop panel builder and graphical programming environment allows one to easily build an interface and create the operating logic for any project. A USB connected “Breadboard Experimentor” circuit board provides the measurement and control link.The product features a “Measurement Wizard” that lets you choose from a built-in database of over 500 commercially available sensors to automatically configure sensor configurations. The wizard also provides circuits with component values for voltage and current measurements. LabRecon’s “Breadboard Experimentor” incorporates a solder-less breadboard to quickly build interface circuitry to sensors or output devices. The on-board LabRecon chip provides many I/O options including 8 12-bit analog, frequency and digital inputs. Outputs comprise PWM, servo, frequency and stepper motor signals. Pins can also be configured to support 24-bit ADCs, 12 or 16-bit DACs and port expanders. As an alternative to the Breadboard Experimentor, LabRecon chips are available in DIP packages, which provide the same I/O functionality.

The software’s graphical programming feature uses Drag-and-drop functions, which can be wired together, to add analysis and control functionality to a project. Algorithms can be further expanded using the “code link” interface to text-based languages such as Python, Java, C#, Visual Basic and so on. LabRecon also comprises a server to allow access of the created GUI by computers or mobile devices. Furthermore, emails and text messages can be sent periodically or upon events. The server also includes a MQTT broker to allow MQTT clients to share data with the software. Even without Breadboard Experimentor or the LabRecon chip, the software has powerful features that can be used for free. Such features include simulation, the Measurement Wizard and a serial monitor/terminal.

A Kickstarter campaign is underway for the LebRecon product. The Kickstarter link is posted on www.LabRecon.com

Texas Instruments (TI) has introduced two new RF-sampling transceivers that integrate four analog-to-digital converters (ADCs) and four digital-to-analog converters (DACs) in a single chip. TI says the device offers the industry’s widest frequency range, highest instantaneous bandwidth and 75% smaller design footprint than a discrete solution. The quad-channel AFE7444 (shown) and dual-channel AFE7422 transceivers help engineers more easily achieve multiantenna, direct RF sampling for radar, software defined radio and wireless 5G applications.

Offering the highest IBW among radio frequency (RF)-sampling transceivers according to TI, the AFE7444 and AFE7422 enable engineers to achieve up to 600% more data throughput. While sampling up to 9 Gsamples per second (GSPS) per DAC and up to 3 GSPS per ADC, the AFE7444 receives and transmits up to 800 MHz of information from each of the four antennae, and the AFE7422 receives and transmits 1.2 GHz from each of the two antennae. The new RF-sampling wideband transceivers give engineers flexibility to design applications covering any frequency from 10 MHz to 6 GHz.

The AFE7444 and AFE7422 enable engineers to support up to eight antennae and 16 RF bands with only one device. The AFE7444 and AFE7422 also allow engineers to directly sample input frequencies into C-band without the need for additional frequency conversion stages, eliminating local oscillators, mixers, amplifiers and filters in designs. Additionally, the two transceivers’ architecture allows for greater programmability than traditional RF solutions, and flexible decimation options enable optimization of data bandwidth. With four ADCs and four DACs in one chip, the AFE7444 and AFE7422 help engineers significantly reduce design cycles that are associated with the manufacturing and testing phases required when designing with discrete components.

Measuring 17 mm by 17 mm, TI’s RF-sampling transceivers help save engineers 75% of board space when compared to using discrete RF-sampling data converters. The integration and small size of the AFE7444 and AFE7422 enable engineers to optimize transceiver proximity to the antenna, enabling digital beam forming in high-frequency and high-density antenna arrays.

The AFE7444EVM and AFE7422EVM evaluation modules, available today from the TI store and authorized distributors. The evaluation modules are priced at $2,499 and $1,999 respectively. Pricing for the AFE7444 quad-channel, wideband RF-sampling transceiver in 100-unit quantities starts at $1,749.90. That’s for a 17-mm-by-17-mm, FCBGA package. Pricing for the AFE7422 dual-channel, wideband RF-sampling transceiver in a 17-mm-by-17-mm FCBGA package starts at $1,249.90 for 100 units.

For wearable devices, every drop of power is precious. That’s driving designers of these embedded systems to attack the power challenge from multiple angles. Fortunately, a slew of analog, power and system ICs have emerged that address the wearable market’s particular needs.

By Jeff Child, Editor-in-Chief

While power is an important issue in any embedded system design, it’s especially critical in wearable devices. Today’s generation of wearable electronics require longer battery lives, more functionality and better performance—all in extremely small form factors. Wearables comprise a wide variety of products including smartwatches, physical activity monitors, heart rate monitors, smart headphones and more.
Today’s wearable electronic devices share some common design priorities. First, they have an extremely low budget for power consumption. And because they’re not suited to being powered by replaceable batteries, they usually require a way for the unit to be recharged. Meanwhile, most modern wearables require some kind of wireless connectivity.

Feeding those needs, chip vendors—primarily from the microcontroller (MCU) and analog sectors—over the past 12 months have announced a generous mix of solutions to help keep power consumption low, to aid recharging and to enable new capabilities while maintaining narrow power constraints. Chip and platform solutions aimed at wearables span the range from specialized power management ICs (PMICs), data converters and power regulator chips, to wireless charging solutions and even complete reference design platforms specially for wearables.

Wrist-Worn Health Gear

Wearables have evolved from being more than just fun devices for health and fitness. Using sophisticated sensors and other capabilities, devices are being designed to do virtual care monitoring, assess chronic conditions and evaluate overall well-being. Along just those lines, in September Maxim Integrated announced its Health Sensor Platform 2.0 (HSP 2.0) (Figure 1). This wrist-worn platform can be used for rapid prototyping, evaluation and development. It provides the ability to monitor electrocardiogram (ECG), heart rate and body temperature from a wrist-worn wearable, saving up to six months in development time, according to Maxim.

Figure 1The Health Sensor Platform 2.0 is a wrist-worn platform that can be used for rapid prototyping, evaluation and development. It provides the ability to monitor electrocardiogram (ECG), heart rate and body temperature from a wrist-worn wearable.

In the past, system developers have found it challenging to derive precise ECG monitoring from the wrist—most alternatives require a wearable chest strap. Getting accurate body temperature typically requires using a thermometer at another location. Maxim has overcome these challenges in the HSP 2.0. by using its proprietary sensor and health monitoring technology.

Enclosed in a watch casing, the wrist-based form factor enables HSP 2.0 to provide basic functionality out of the box, with body-monitoring measurements starting immediately. Data can be stored on the platform for patient evaluation or streamed to a PC for analysis later. Unlike other wearables, the data measurements collected by the HSP 2.0 can be owned by the wearer. This alleviates data privacy concerns and enables users to conduct their own data analysis. Also, because HSP 2.0 is an open platform, designers can evaluate their own algorithms on the board. In addition, the modular format is future proof to quickly accommodate new sensors over time.

For its part, Renesas Electronics has been working on meeting extreme low power demands by applying innovations in semiconductor process development. In November the company unveiled an innovative energy-harvesting embedded controller that can eliminate the need to use or replace batteries in a device. Developed based on Renesas’ SOTB (silicon-on-thin-buried-oxide) process technology, the new embedded controller achieves extreme reduction in both active and standby current consumption. The extreme low current levels of the SOTB-based embedded controller enables system designers to completely eliminate the need for batteries in some of their products through harvesting ambient energy sources such as light, vibration and flow (Figure 2).

Figure 2The extreme low current levels of the SOTB-based embedded controller enables system designers to completely eliminate the need for batteries in some of their products through harvesting ambient energy sources such as light, vibration and flow.

Although the solution was developed with IoT devices in mind, the controller is more broadly aimed at what they call the new market of maintenance-free, connected IoT sensing devices with endpoint intelligence. This includes health and fitness apparel, shoes, wearables, smart watches and drones. Renesas’ first commercial product using SOTB technology, the R7F0E embedded controller, is a 32-bit, Arm Cortex-based embedded controller. The device is capable of operating up to 64 MHz for rapid local processing of sensor data and execution of complex analysis and control functions.

The R7F0E consumes just 20 μA/MHz active current, and only 150 nA deep standby current, approximately one-tenth that of conventional low-power MCUs. According to the company, samples of the new R7F0E embedded controller are available now for beta customers, and samples are scheduled to be available for general customers from July 2019. Mass production is scheduled to start from October 2019.

LDO Regulator for Wearables

Achieving longer battery lives is a problem that can be attacked from many angles. Power regulator electronics are among those. With that in mind, Microchip Technology in October introduced a linear Low Dropout (LDO) regulator that extends battery life in portable devices up to four times longer than traditional ultra-low quiescent (IQ) LDOs. With an ultra-low IQ of 250 nA versus the approximately 1 µA operation of traditional devices, the MCP1811 LDO reduces quiescent current to save battery life, enabling end users to recharge or replace batteries less often (Figure 3).

Well suited for IoT and battery-operated applications such as wearables, remotes and hearing aids, the LDO reduces power consumption in applications by minimizing standby or shutdown current. Reducing standby power consumption is critical in remote, battery-powered sensor nodes, where battery replacement is difficult and operating life requirements are high. Available in package options as small as 1 mm x 1 mm, the MCP1811 consumes minimal board space to meet the needs of today’s compact portable electronic designs. Depending on the application and number of LDOs, designers can take advantage of the extra board space with a larger battery to further increase battery life.

An additional benefit the MCP1811 offers is faster load line and transient response when compared to other ultra-low IQ LDOs. Faster response times can accelerate wake-up speed in devices such as monitors or sensors that require immediate attention. Faster transient response can help designers avoid undervoltage and overvoltage lockout measures used in sensitive applications where transient spikes can lead to catastrophic results.

Secure Payments with Wearables

An important capability in a certain class of wearables is the ability to support electronic retail transactions directly from the wearable device. While this is arguably a whole separate technology category in itself, we’ll touch on a couple developments here. In November, Infineon Technologies announced an EMV-based payment solution for key chains, rings, wristbands, bracelets and other wearable devices.

The SECORA Pay W for Smart Payment Accessories (SPA) combines an EMV chip with the card operating system, payment applet as well as the antenna directly on the unit. As a turnkey solution it allows card vendors, device manufacturers, financial institutions or event organizers to quickly and cost-efficiently introduce fashion accessories for payment and even access.

Infineon’s SECORA Pay solutions portfolio comprises the SECORA Pay S for standard Visa and MasterCard payment cards, SECORA Pay X for applications with extended features such as multi-application, national debit and white label schemes or access management and SECORA Pay W for payment accessories. All SECORA turn-key solutions are pre-certified by Mastercard and Visa and will accelerate the deployment of contactless payment. The EMV Chip Specifications (www.emvco.com) define globally valid requirements for chip-based payment solutions and acceptance terminals. They enable secure contact- and contactless applications and the use of other emerging payment technologies.

Complete Payment SoC

Likewise a player in the contactless transaction market, STMicroelectronics (ST) back in October announced teaming up with Fidesmo to create a turnkey active solution for secure contactless payments on smart watches and other wearable technology. The complete payment system-on-chip (SoC) is based on ST’s STPay-Boost IC, which combines a hardware secure element to protect transactions and a contactless controller featuring proprietary active-boost technology that maintains reliable NFC connections even in devices made with metallic materials. Its single-chip footprint fits easily within wearable form factors (Figure 4).

Fidesmo’s MasterCard MDES tokenization platform completes the solution by allowing the user to load the personal data needed for payment transactions. Convenient Over-The-Air (OTA) technology makes personalization a simple step for the user without any special equipment. Kronaby, a Sweden-based hybrid smartwatch maker, has embedded the STPay-Boost chip in its portfolio of men’s and women’s smart watches that offer differentiated features such as freedom from charging and filtered notifications. The SoC with Fidesmo tokenization enables Kronaby watches to support a variety of services such as payments, access control, transportation and loyalty rewards.

Data Converters

Data converters also have role to play in efforts to meet the extreme low power needs of wearable devices. Along such lines, in December Texas Instruments (TI) introduced four tiny precision data converters (Figure 5). The new data converters enable designers to add more intelligence and functionality, while shrinking system board space. The DAC80508 and DAC70508 are eight-channel precision digital-to-analog converters (DACs) that provide true 16- and 14-bit resolution, respectively.

The ADS122C04 and ADS122U04 are 24-bit precision analog-to-digital converters (ADCs) that feature a two-wire, I2C-compatible interface and a two-wire, UART-compatible interface, respectively. The devices are optimized for a variety of small-size, high-performance or cost-sensitive electronics applications such as wearables.

Both DACs include a 2.5-V, 5-ppm/°C internal reference, eliminating the need for an external precision reference. Available in a 2.4-mm-by-2.4-mm die-size ball-grid array (DSBGA) package or wafer chip-scale package (WCSP) and a 3-mm-by-3-mm quad flat no-lead (QFN)-16 package, these devices are up to 36% smaller than the competition, says TI. Meanwhile, the tiny, 24-bit precision ADCs are available in 3-mm-by-3-mm very thin QFN (WQFN)-16 and 5-mm-by-4.4-mm thin-shrink small-outline package (TSSOP)-16 options. The two-wire interface requires fewer digital isolation channels than a standard serial peripheral interface (SPI), reducing the overall cost of an isolated system. These precision ADCs eliminate the need for external circuitry by integrating a flexible input multiplexer, a low-noise programmable gain amplifier and other circuitry.

Memory Innovations

Among the latest innovations aimed at wearables from Cypress Semiconductor is an FRAM (ferroelectric random access memory)-based data logging solution. In November, Cypress introduced a nonvolatile data-logging solution with ultra-low power consumption. This solution is well suited for portable medical and wearable devices that demand nonvolatile memories to continuously log an increasing amount of user and sensor data while using as little power as possible.

Cypress’ Excelon LP FRAM is an energy-efficient device that provides instant-write capabilities with virtually unlimited endurance (Figure 6). This enables wearable systems to perform mission-critical data logging requirements while maximizing battery life. The Excelon LP series is available in a low-pin-count, small-footprint package that is suited for space-constrained, wearable applications.

The Excelon LP series offers 4-Mb and 8-Mb industrial and commercial-grade densities with 50 MHz and 20 MHz Serial Peripheral Interface (SPI) performance. The series reduces power consumption with 100 nA hibernate and 1 µA standby modes that greatly improve a battery-powered product’s user experience by extending system operating time. The device’s inherent instant writes also eliminate power failure “data-at-risk” due to volatile data buffers in legacy memories. The family features wide voltage operation from 1.71 V to 3.6 V and is available in RoHS-compliant industry-standard packages that are pin compatible with EEPROMs and other nonvolatile memories. Excelon LP F-RAMs provide 1,000-trillion (1015) read/write cycle endurance with 10 years of data retention at 85°C or 151 years at 65°C.

Charging Wearables

A common aspect of wearable devices is that they tend not to be suited for replaceable batteries. As a result, they typically need to be recharged. Wireless (cordless) battery charging is beginning to take hold as a solution. Feeding such needs, in October Analog Devices announced its Power by Linear LTC4126 as an expansion of its offerings in wireless battery charging. The LTC4126 combines a wireless powered battery charger for Li-Ion cells with a high efficiency multi-mode charge pump DC-DC converter, providing a regulated 1.2 V output at up to 60 mA (Figure 7).

Charging with the LTC4126 allows for a completely sealed end product without wires or connectors and eliminates the need to constantly replace non-rechargeable (primary) batteries. The efficient 1.2 V charge pump output features pushbutton on/off control and can directly power the end product’s ASIC. This greatly simplifies the system solution and reduces the number of necessary external components. The device is ideal for space-constrained low power Li-Ion cell powered wearables such as hearing aids, medical smart patches, wireless headsets and IoT devices.

The LTC4126, with its input power management circuitry, rectifies AC power from a wireless power receiver coil and generates a 2.7 V to 5.5 V input rail to power a full-featured constant-current/constant-voltage battery charger. Features of the battery charger include a pin selectable charge voltage of 4.2 V or 4.35 V, 7.5 mA charge current, automatic recharge, battery temperature monitoring via an NTC pin, and an onboard 6-hour safety charge termination timer. Low battery protection disconnects the battery from all loads when the battery voltage is below 3.0 V. The LTC4126’s charge pump switching frequency is set to 50 kHz/75 kHz to keep switching noise out of the audible range, ideal for audio related applications such as hearing aids and wireless headsets. The IC is housed in a compact, low profile (0.74 mm) 12-lead 2 mm × 2 mm LQFN package. The device is guaranteed for operation from –20°C to 85°C in E-grade.

Kit for Wireless Charging

Also facilitating building wireless chargers for wearables, ST for its part offers a kit-level solution. The ST plug-and-play wireless battery-charger development kit (STEVAL-ISB045V1) lets users quickly build ultra-compact chargers up to 2.5 W with a space-saving 20 mm-diameter coil, for charging small IoT devices and wearables such as smart watches, sports gear or healthcare equipment (Figure 8).

Built around the STWBC-WA wireless charging-transmitter controller, the kit comprises a charging base unit containing a transmitter board with the 20 mm coil already connected and ready to use. Getting started is easy, using the PC-based STSW-STWBCGUI software to configure the STWBC-WA and monitor runtime information such as power delivered, bridge frequency, demodulation quality and protocol status. The kit includes a dongle for running the GUI. The supporting ecosystem includes certified reference boards, software and detailed documentation to help developers quickly design chargers for wearables.

The STWBC-WA controller chip contains integrated drivers and natively supports full-bridge or half-bridge topologies for powering the antenna. The half-bridge option allows charging up to 1 W with a smaller-diameter coil for an even more compact form factor. The chip supports all standard wireless-charging features, including Foreign Object Detection (FOD) and active presence detection for safe charging, and uses digital feedback to adapt the transmitted power for optimum efficiency at all load conditions. Two firmware options give users the choice of a fast turnkey solution or customizing the application using APIs to access on-chip peripherals including an ADC, a UART and GPIOs.

Clearly there are many facets and angles to address the low power needs of wearables. As demands for more functionality rise, system developers will need to remain ever mindful of keeping battery life at the same lengths or longer. Fortunately, there seems to be no stopping the innovation among chip vendors targeting this growing wearables market.

Note: We’ve made the October 2017 issue of Circuit Cellar available as a free sample issue. In it, you’ll find a rich variety of the kinds of articles and information that exemplify a typical issue of the current magazine.

Hardkernel announced an “Odroid-N2” SBC with a Cortex-A73 and -A53 based Amlogic S922X SoC plus 2-4GB DDR4, 4x USB 3.0, HDMI 2.1, an audio DAC, and a 40-pin header.
Hardkernel unveiled its open-spec, Ubuntu-ready Odroid-N1 SBC a year ago with a Rockchip RK3399 SoC. Since it was scheduled for June shipment, we included it our reader survey of 116 hacker boards. Yet, just before we published the results, including a #16 ranking for the N1, Hardkernel announced it was shelving the board due to sourcing problems and switching to a similar new board with an unnamed new SoC. The Odroid-N2 would also switch to DDR4 RAM from the previously announced DDR3, which was in short supply.

Odroid-N1 with heatsink (left) and within black case
(click images to enlarge)

The Odroid-N2 will arrive in April about four months later than intended, but with a much lower $63 (2GB RAM) and $79 (4GB) price compared to the original Odroid-N1 goal of “about $110.” The new model has also advanced to a similarly hexa-core, but much faster Amlogic S922X SoC, which was unveiled in September along with the quad-core -A53 Amlogic S905X2 and S905Y2.

Amlogic has yet to post a product page for the 12nm-fabricated S922X, which integrates 4x Cortex-A73 cores instead of the RK3399’s 2x 2.0GHz -A72 cores. The S922X also has 2x -A53 cores that clock to 1.9GHz instead of 4x 1.5GHz -A53 cores on the high-end version of the RK3399 used by the N1. The N2 also moves up to a Mali-G52 GPU with 6x 846MHz execution engines, which the Odroid project benchmarks as 10 percent faster.

Hardkernel has posted benchmarks that claim around 20 percent faster CPU performance than the RK3399-driven N1. The inclusion of a substantial metal heatsink and the placement of the SoC and RAM on the bottom of the board enable top speeds “without thermal throttling,” says the Odroid project. With the 4GB version (the only configuration announced for the N1), the N2’s 1320MHz DDR4-RAM is claimed to be 35 percent faster than the N1’s 800MHz DDR3.

Although it may not make much sense to compare the Odroid-N2 to a board that never shipped, it should be noted that the Odroid-N1’s PCIe-based SATA connectors (also found on a few other RK3399 boards) have disappeared. However, you get 4x USB 3.0 host ports instead of a split between 3.0 and 2.0.

The USB ports sit next to a faster GbE port (about 1Gbps) and a 4K-ready HDMI port which is variablly listed as 2.0 and 2.1. For wireless, you’ll need to use one of the USB ports.

Legend for detail view above
(click image to enlarge)

The Odroid-N2 is slightly smaller than the N1 at 90 x 90 x 17mm and has a different design. Several ports such as the micro-USB OTG port and new IR sensor and composite A/V jack appear on the opposite coastline. The A/V jack includes a high-quality audio DAC (384Khz/32bit) with dynamic range, near-100dB SNR, and Total-Harmonic-Distortion lower than 0.006 percent, claims the Odroid project.

The 40-pin expansion header provides 25x GPIO, 2x I2C, SPDIF, and other 3.3V interfaces except for the dual 1.8V ADC signals. The pinout is said to be similar to the Amlogic S905 based Odroid-C2. There’s a wide-range 7.5-20V DC jack, and power consumption is listed as 1.8W idle to 5.5W CPU stress. No operating range was listed, but benchmarks suggest it runs run fine at 35°C.

The Odroid-N2 is available with 64-bit Ubuntu 18.04 LTS with Linux 4.9.152 LTS and Android 9 Pie “with full source code BSP and pre-built image together.” There is no X11 GPU driver and the Mali G52 GPU Linux driver currently works only on the framebuffer, but there’s a hardware-accelerated VPU driver. A Linux Wayland driver and Vulkan capable GPU driver for Android are in the works.

The board ships with 8MB SPI along with a boot select switch and a Petitboot app. It requires removal of any bootable eMMC while you’re making the switch.

Odroid boards, such as the ever popular Odroid-XU4 have usually scored high in our reader surveys due to solid HW/SW quality, vigorous open source support, and a devoted community. The Odroid project recently branched into x86 territory with its Intel Gemini Lake based Odroid-H2.

The Odroid-N2 will go on sale in late March with shipments beginning in April. Some engineering samples will head out to a lucky few over the next week. Pricing is $63 (2GB RAM) and $79 (4GB) price. More information may be found on Hardkernel’s Odroid-N1 announcement and product page and wiki.

Doing a signature analysis of a signal used to require an oscilloscope to display your results. In this article, Brian details how to build a free-standing tester using mostly just the internal peripherals of an NXP Arm microcontroller. He describes how the tester operates and how he implemented it.

By Brian Millier

When I was a teenager starting out in electronics, I longed to have as much test equipment as possible. At that stage in life, I couldn’t afford much beyond a multimeter. I remember seeing plans for a component tester in an electronics magazine. There weren’t many hobby electronics magazines back in the ‘60s, so it was probably Popular Electronics. This tester would provide a “signature” of most passive/active components by placing a small AC voltage across the component and measuring the resulting current. My memory of the circuit is hazy after all these years, but it was trivial: a 6.3 V filament transformer, a current sensing resistor and a few other passive components. However, the catch was that it required an oscilloscope to display the resulting voltage vs. current plot—in other words, the component’s signature. By the time I bought an oscilloscope about 10 years later, I had completely forgotten about this testing concept.

Today, test instruments are available that include a dedicated graphics display, instead of relying on an oscilloscope for display purposes. Having worked with Arm microcontrollers over the last few years,
I realized that I could implement such a free-standing tester using, in large part, just the internal MCU peripherals.

In this article I’ll describe how the tester operates, and how I implemented it using a Teensy 3.5 development module (containing an NXP MK64FX512VMD12 MCU) and featuring a FT800-based intelligent 4.3″ TFT touch-screen display.

Basic Theory of Operation

To obtain a signature of a given component, you need to place a variable voltage across it and measure the resulting current through it, at each voltage level. In many cases, the component’s normal operating mode will include both positive and negative voltages across it, so the tester must provide an AC voltage source. For most testing purposes you would use a sine wave voltage source because most AC calculations are done using sine waves. The value of this AC voltage source must be adjustable. I decided on six ranges between 0.5 V peak-peak and 20 V peak-peak. For measuring the voltage across the component, I used an instrumentation amplifier with three hardware gain ranges—plus three additional ranges based upon scaling in software.

To monitor current, it’s easiest to measure the voltage across a small value resistor placed in the ground return path, and then convert that to current using Ohm’s Law. Here too you need a range of current measurements. I chose to provide three hardware ranges—plus four additional ranges based on software scaling—between 1 mA and 100 mA.

You can’t just place an AC voltage of any given value across a component, and hope that the component will be able to handle that current without damage. You must place a resistor in series with the component to limit the current flow. That resistor may need to vary in value over several decades, depending on the component being tested. In my tester, I provide a switchable resistor bank with values covering a 1,000:1 range in decade steps.

Figure 1 is a block diagram of the basic tester circuitry. The user interface, touch-screen display and SD card data storage are not shown here. The MK64FX512VMD12 MCU’s 12-bit DAC A provides a sine wave signal that varies between 0 and 1.2 V over the full AC cycle. The programmable attenuator is an SPI pot device with 12-bit resolution. C1 is a decoupling capacitor, which shifts the (attenuated) unipolar DAC A output signal into a bipolar AC signal. This AC signal is amplified by a factor of 21 by an LM675 power amplifier IC. DAC B, along with some passive components, provide a software-adjustable offset voltage adjustment. The LM675 amplifier is needed to provide enough drive current to handle the higher current ranges—up to 100 mA.

FIGURE 1This is a block diagram of the AC signal generation and Voltage/Current monitoring circuit.

Both the voltage and current are monitored using Texas Instruments (TI)instrumentation amplifier ICs. These contain input protection circuitry good to ±40 V. The various gains needed for both amplifiers are set by 1% resistors, which are switched by miniature reed relays. The instrumentation amplifier output voltages, representing voltage and current through the component under test, are fed to the two 16-bit ADCs present in the NXP MK64FX512VMD12 Arm MCU. The sine wave signal generated by the MCU can be set for frequencies of 20, 50 ,60, 100, 200 or 400 Hz.

Signature Analysis

The basic premise of signature analysis is that you obtain a signature of a component that is of questionable condition, and then compare it with a known-good component of the same value. Alternately, you can do the same comparison on a specific circuit node on two identical circuit boards/assemblies.. …

Note: We’ve made the October 2017 issue of Circuit Cellar available as a free sample issue. In it, you’ll find a rich variety of the kinds of articles and information that exemplify a typical issue of the current magazine.

A new microcontroller that combines specified radiation performance with low-cost development associated with Commercial Off-The-Shelf (COTS) devices is now available from Microchip Technology. Developing radiation-hardened systems for space applications has a history of long lead times and high costs to achieve the highest level of reliability for multi-year missions in a harsh environment. Today, space and other critical aerospace applications require faster development and reduced costs.

The ATmegaS64M1 is the second 8-bit megaAVR MCU from Microchip that uses a development approach called COTS-to-radiation-tolerant. This approach takes a proven automotive-qualified device, the ATmega64M1 in this case, and creates pinout compatible versions in both high-reliability plastic and space-grade ceramic packages. The devices are designed to meet radiation tolerances with the following targeted performances:

The new device joins the ATmegaS128, a radiation-tolerant MCU that has already been designed into several critical space missions including a Mars exploration plus a megaconstellation of several hundred Low Earth Orbit (LEO) satellites.

The ATmega64M1 COTS device, along with its full development toolchain including development kits and code configurator, can be used to begin development of hardware, firmware and software. When the final system is ready for the prototype phase or production, the COTS device can be replaced with a pin-out compatible, radiation-tolerant version in a 32-lead ceramic package (QFP32) with the same functionality as the original device. This leads to significant cost savings while also reducing development time and risk.

The ATmegaS64M1 meets the high operating temperature range of -55°C to +125°C. It is the first COTS-to-radiation-tolerant MCU to combine a Controller Area Network (CAN) bus, Digital-to-Analog Converter (DAC) and motor control capabilities. These features make it ideal for a variety of subsystems like remote terminal controllers and data handling functions for satellites, constellations, launchers or critical avionic applications.

To ease the design process and accelerate time to market, Microchip offers the STK 600 complete development board for the ATmegaS64M1, giving designers a quick start to develop code with advanced features for prototyping and testing new designs. The device is supported by Atmel Studio Integrated Development Environment (IDE) for developing, debugging and software libraries.

While analog ICs are important in a variety of application areas, their place in the industrial market stands out. Industrial applications depend heavily on all kinds of interfacing between real-world analog signals and the digital realm of processing and control. Today’s factory environments are filled with motors to control, sensors to link with and measurements to automate. And as net-connected systems become the norm, analog chip vendors are making advances to serve the new requirements of the Industrial Internet-of-Things (IIoT) and Smart Factories.

It’s noteworthy, for example, that Analog Devices‘ third quarter fiscal year 2017 report this summer cited the “highly diverse and profitable industrial market” as the lead engine of its broad-based year-over-year growth. Taken together, these factors all make industrial applications a significant market for analog IC vendors, and those vendors are keeping pace by rolling out diverse solutions to meet those needs.

Figure 1 This diagram from Texas Instruments illustrates the diverse kinds of analog sub-systems that are common in industrial systems—an industrial drive/control system in this case.

While it’s impossible to generalize about industrial systems, Figure 1 illustrates the diverse kinds of analog sub-systems that are common in industrial systems—industrial drive/control in that case. All throughout 2017, manufacturers of analog ICs have released a rich variety of chips and development solutions to meet a wide range of industrial application needs.

SOLUTIONS FOR PLCs

Programmable Logic Controllers (PLCs) remain a staple in many industrial systems. As communications demands increase and power management gets more difficult, transceiver technologies have evolved to keep up. PLC and IO-Link gateway systems must dissipate large amounts of power depending. That amount of power is often tied to I/O configuration—IO-Link, digital I/O and/or analog I/O. As these PLCs evolve into new Industrial 4.0 smart factories, special attention must be considered to achieve smarter, faster, and lower power solutions. Exemplifying those trends, this summer Maxim Integrated announced the MAX14819, a dual-channel, IO-Link master transceiver.

The architecture of the MAX14819 dissipates 50% less heat compared to other IO-Link Master solutions and is fully compatible in all modes for IO-Link and SIO compliance. It provides robust L+ supply controllers with settable current limiting and reverse voltage/current protection to help ensure robust communications with the lowest power consumption. With just one microcontroller, the integrated framer/UART enables a scalable and cost-effective architecture while enabling very fast cycle times (up to
400 µs) and reducing latency. The MAX14819 is available in a 48-pin (7 mm x 7 mm) TQFN package and operates over a -40°C to +125°C temperature range. …

Note: We’ve made the October 2017 issue of Circuit Cellar available as a free sample issue. In it, you’ll find a rich variety of the kinds of articles and information that exemplify a typical issue of the current magazine.

In the previous parts of this series, Nishant laid the groundwork for getting up and running with the PSoC. Here he tackles the chip’s more complex features like Data Conversion and CapSense.

By Nishant MittalSystems Engineer, Cypress Semiconductor

In the previous two parts of this “Getting started with PSoC” series, I have hopefully provided you with a good base of knowledge about PSoC devices. Here, in this final part it’s time to get more in depth and discuss various data conversion protocols in PSoC and provide some design examples. I’ll also cover interfacing various peripherals with the microcontroller. We’ll also get into how to transition from a bare silicon PSoC chip or PSoC development board to using the chip in your project.

Data conversion with PSoC

Data Conversion is an important block in any kind of instrumentation system or Internet of Things implementation. In fact, any application that uses sensors or interfaces to the external environment is an application in which Data Conversion is an integral part of the system. Although digital sensors are available today, the lower costs of analog sensors shouldn’t be overlooked.

PSoC Creator has a Data Conversion component that enables designers to code efficiently with less effort. The photo above shows the screenshot of the ADC (analog-to-digital conversion) component in PSoC Creator. The photo above also shows the configuration setting for ADC. First off, we need to set the Channel sampling rate (SPS). Second, we need to set the voltage reference which is necessary to do the comparison of analog signals. Here we use VDDA/2 or VDDA which is 5 V. You can select whether you want a single-ended ADC or differential ADC by simply clicking the appropriate tab from the component configuration. Clock source needs to be chosen. If the source is chosen to be internal, the PLL from the internals of chip are used—otherwise you’d have to connect an external crystal to the controller using the development kit CY8CKIT-044. Other advanced settings are available for complex programs—but most of those aren’t needed in most intermediate applications.

Cirrus Logic recently introduced the CS43130 MasterHIFI, which is a low-power, digital-to-analog converter (DAC) featuring a headphone amplifier. Operating at 4× lower power consumption, the CS43130 DAC supports Direct Stream Digital (DSD) formats and includes a NOS Filter and 512 single-bit elements to eliminate unwanted noise from the signal and for best filter response. The IC minimizes board space requirements while enabling performance and features to drive design differentiation.

The CS43130’s features, specs, and benefits:

Supports DSD, DSD DoP (DSD over PCM), up to DSD128 and all PCM high-resolution audio formats up to 32-bit 384 kHz

ESS Technology announced its new flagship ES9038PRO SABRE DAC at CES 2016, generating immediate attention from audio manufacturers looking to raise the standard on new generation high-resolution audio products. The new ESS PRO SABRE 32-bit, 8-channel DAC chip goes the extra mile by offering the industry’s highest dynamic range (DNR) of 140dB with an impressive THD+N at -122dB.

During CES 2016, ESS Technology announced its new professional series of Digital-to-Analog Converters (DAC) targeted at premium high-end consumer and professional recording studio equipment. The flagship offering for this professional series is the ES9038PRO SABRE DAC. This first member of the ESS PRO SABRE series sets a new benchmark in high-end audio by offering the industry’s highest dynamic range (DNR) of 140dB and offers impressively low total harmonic distortion plus noise (THD+N) at -122dB in a 32-bit, 8-channel DAC.

As high resolution content proliferates through new, high-end music download services, users are looking for equipment that delivers the highest quality sound possible, regardless of file format or device. The ES9038PRO SABRE DAC sets a new standard for immersive and high-resolution audio (HRA) experiences.

The ES9038PRO SABRE DAC features ESS’s patented 32-bit HyperStream DAC technology. The HyperStream architecture is responsible for both the outstanding sound quality of ESS PRO SABRE DACs and the extremely low THD+N. Other 32-Bit 8-Channel DACs, using typical delta-sigma architecture, feature –107 dB THD+N (0.0004%), which when subjected to individual listening tests do not equal the clarity and sound stage of the ES9038PRO. This new flagship SABRE DAC was created to integrate seamlessly with both the existing and future portfolio of ESS headphone amplifiers as well as other audio building block technology.

New hardware features include full-scale manual/auto-gain calibration to reduce device-to-device gain error (allowing to configure multiple DACs for high channel count systems), option for programmable volume control ramp-rate with +18 dB, DSD over PCM (DoP) decoder and a total of eight preset filters for maximum design flexibility. Its programmable functions allow customizing outputs to mono, stereo, and 8-channel output in current-mode or voltage-mode based on performance criteria, together with user-programmable filters and programmable THD compensation to minimize THD caused by external components.

For audio designers, the ES9038PRO SABRE DAC includes significant advancements over previous generations, simplifying the implementation of specific software and reducing debugging time. The volume level of all internal DACs can be updated with a single software instruction. Clock gearing reduces MCLK frequency and saves power – the chip has 500 mW power consumption at 192 kHz sampling and 100 MHz MCLK – while advanced power management features enable a low-power idle mode when the audio signal is absent.

According to ESS, the ES9038PRO SABRE DAC was designed for premium home theater equipment including Blu-ray players, preamplifiers, all-in-one A/V receivers, and more. Studio environments can also leverage the ES9038PRO SABRE DAC’s industry-leading performance for professional audio workstations and other equipment. The PRO series enables studio professionals to recreate popular signature sound styles, using external DSP and specialized software packages, while remaining true to the artists’ musical vision.

In addition to the SABRE ES9038PRO, ESS is also announcing other members of the PRO series – the ES9028PRO and ES9026PRO SABRE DACs. These 32-bit, 8-channel PRO series DACs are designed for the audiophile/enthusiast who demands the high quality and performance of a SABRE DAC at a more economical price point. The ES9028PRO and ES9026PRO are pin-compatible upgrades for previous generation ESS products — the ES9018S and ES9016S — and feature 129 dB and 124 dB dynamic range (DNR), and -120 dB and -110 dB total harmonic distortion plus noise (THD+N).

A new series of 2/4/6/8-channel D/A converters from Asahi Kasei Microdevices (AKM) is powering the next generation of high-quality consumer electronic devices, measurement equipment, and control systems. The AK4452/AK4454/AK4456/AK4458 premium 32-bit DAC devices have up to eight channels. The devices are based on AKM’s Velvet Sound architecture. Combining fine sound details with the low-distortion architecture and 32-bit resolution digital filter processing, the new technology is already finding applications in new AV receivers, network audio and USB DACs, USB headphones, audio interfaces, and much more.

The digital input in the new DAC series supports up to 768-kHz PCM and 11.2-MHz Direct Stream Digital (DSD), suitable for high-resolution audio source playback. With up to eight channels and a TDM interface allowing daisy chaining, the series also provides a simple solution to a wide range of applications.

According to AKM, its Velvet Sound core architecture was designed specifically to support the high-resolution audio market and achieves the lowest distortion in the industry with –107 dB in the D/A conversion and 115-dB S/N. Using Over Sampling Ratio Doubler (OSRD), the new chips reduce out of band noise and include Impulse Response Designed (IRD) filters integrated with 32-bit processing. Five different digital filters types are selectable according to the user audio and system preferences.

The AD9144 is a four-channel, 16-bit, 2.8-GSPS DAC that supports high data rates and ultra-wide signal bandwidth to enable wideband and multiband wireless applications. The DAC features 82-dBc spurious-free dynamic range (SFDR) and a 2.8-GSPS maximum sample rate, which permits multicarrier generation up to the Nyquist frequency.

With –164-dBm/Hz noise spectral density, the AD9144 enables higher dynamic range transmitters to be built. Its low SFDR and distortion design techniques provide high-quality synthesis of wideband signals from baseband to high intermediate frequencies. The DAC features a JESD204B eight-lane interface and low inherent latency of fewer than two DAC clock cycles. This simplifies hardware and software system design while permitting multichip synchronization.

The DAC is supported by an evaluation board with an FPGA Mezzanine Card (FMC) connector, software, tools, a SPI controller, and reference designs. Analog Devices’s VisualAnalog software package combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface that enables users to customize their input signal and data analysis.

Jitter is one of the parameters you should consider when designing a project, especially when it involves planning a high-speed digital system. Moreover, jitter investigation—performed either manually or with the help of proper measurement tools—can provide you with a thorough analysis of your product.

There are at least two ways to measure jitter: cycle-to-cycle and time interval error (TIE).

WHAT IS JITTER?
The following is the generic definition offered by The International Telecommunication Union (ITU) in its G.810 recommendation. “Jitter (timing): The short-term variations of the significant instants of a timing signal from their ideal positions in time (where short-term implies that these variations are of frequency greater than or equal to 10 Hz).”

First, jitter refers to timing signals (e.g., a clock or a digital control signal that must be time-correlated to a given clock). Then you only consider “significant instants” of these signals (i.e., signal-useful transitions from one logical state to the other). These events are supposed to happen at a specific time. Jitter is the difference between this expected time and the actual time when the event occurs (see Figure 1).

Figure 1—Jitter includes all phenomena that result in an unwanted shift in timing of some digital signal transitions in comparison to a supposedly “perfect” signal.

CYCLE-TO-CYCLE JITTER
Assume you have a digital signal with transitions that should stay within preset time limits (which are usually calculated based on the receiver’s signal period and timing diagrams, such as setup duration and so forth). You are wondering if it is suffering from any excessive jitter. How do you measure the jitter? First, think about what you actually want to measure: Do you have a single signal (e.g., a clock) that could have jitter in its timing transitions as compared to absolute time? Or, do you have a digital signal that must be time-correlated to an accessible clock that is supposed to be perfect? The measurement methods will be different. For simplicity, I will assume the first scenario: You have a clock signal with rising edges that are supposed to be perfectly stable, and you want to double check it.

My first suggestion is to connect this clock to your best oscilloscope’s input, trigger the oscilloscope on the clock’s rising edge, adjust the time base to get a full period on the screen, and measure the clock edge’s time dispersion of the transition just following the trigger. This method will provide a measurement of the so-called cycle-to-cycle jitter (see Figure 2).

Figure 2—Cycle-to-cycle is the easiest way to measure jitter. You can simply trigger your oscilloscope on a signal transition and measure the dispersion of the following transition’s time.

If you have a dual time base or a digital oscilloscope with zoom features, you could enlarge the time zone around the clock edge you are interested in for more accurate measurements. I used an old Philips PM5786B pulse generator from my lab to perform the test. I configured the pulse generator to generate a 6.6-MHz square signal and connected it to my Teledyne LeCroy WaveRunner 610Zi oscilloscope. I admit this is high-end equipment (1-GHz bandwidth, 20-GSPS sampling rate and an impressive 32-M word memory when using only two of its four channels), but it enabled me to demonstrate some other interesting things about jitter. I could have used an analog oscilloscope to perform the same measurement, as long as the oscilloscope provided enough bandwidth and a dual time base (e.g., an old Tektronix 7904 oscilloscope or something similar). Nevertheless, the result is shown in Figure 3.

Figure 3—This is the result of a cycle-to-cycle jitter measurement of the PM5786A pulse generator. The bottom curve is a zoom of the rising front just following the trigger. The cycle-to-cycle jitter is the horizontal span of this transition over time, here measured at about 620 ps.

This signal generator’s cycle-to-cycle jitter is clearly visible. I measured it around 620 ps. That’s not much, but it can’t be ignored as compared to the signal’s period, which is 151 ns (i.e., 1/6.6 MHz). In fact, 620 ps is ±0.2% of the clock period. Caution: When you are performing this type of measurement, double check the oscilloscope’s intrinsic jitter as you are measuring the sum of the jitter of the clock and the jitter of the oscilloscope. Here, the latter is far smaller.

TIME INTERVAL ERROR
Cycle-to-cycle is not the only way to measure jitter. In fact, this method is not the one stated by the definition of jitter I presented earlier. Cycle-to-cycle jitter is a measurement of the timing variation from one signal cycle to the next one, not between the signal and its “ideal” version. The jitter measurement closest to that definition is called time interval error (TIE). As its name suggests, this is a measure of a signal’s transitions actual time, as compared to its expected time (see Figure 4).

Figure 4—Time interval error (TIE) is another way to measure jitter. Here, the actual transitions are compared to a reference clock, which is supposed to be “perfect,” providing the TIE. This reference can be either another physical signal or it can be generated using a PLL. The measured signal’s accumulated plot, triggered by the reference clock, also provides the so-called eye diagram.

It’s difficult to know these expected times. If you are lucky, you could have a reference clock elsewhere on your circuit, which would supposedly be “perfect.” In that case, you could use this reference as a trigger source, connect the signal to be measured on the oscilloscope’s input channel, and measure its variation from trigger event to trigger event. This would give you a TIE measurement.

But how do you proceed if you don’t have anything other than your signal to be measured? With my previous example, I wanted to measure the jitter of a lab signal generator’s output, which isn’t correlated to any accessible reference clock. In that case, you could still measure a TIE, but first you would have to generate a “perfect” clock. How can this be accomplished? Generating an “ideal” clock, synchronized with a signal, is a perfect job for a phase-locked loop (PLL). The technique is explained my article, “Are You Locked? A PLL Primer” (Circuit Cellar 209, 2007.) You could design a PLL to lock on your signal frequency and it could be as stable as you want (provided you are willing to pay the expense).

Moreover, this PLL’s bandwidth (which is the bandwidth of its feedback filter) would give you an easy way to zoom in on your jitter of interest. For example, if the PLL bandwidth is 100 Hz, the PLL loop will capture any phase variation slower than 100 Hz. Therefore, you can measure the jitter components faster than this limit. This PLL (often called a carrier recovery circuit) can be either an actual hardware circuit or a software-based implementation.

So, there are at least two ways to measure jitter: Cycle-to-cycle and TIE. (As you may have anticipated, many other measurements exist, but I will limit myself to these two for simplicity.) Are these measurement methods related? Yes, of course, but the relationship is not immediate. If the TIE is not null but remains constant, the cycle-to-cycle jitter is null. Similarly, if the cycle-to-cycle jitter is constant but not null, the TIE will increase over time. In fact, the TIE is closely linked to the mathematical integral over time of the cycle-to-cycle jitter, but this is a little more complex, as the jitter’s frequency range must be limited.

Editor’s Note: This is an excerpt from an article written by Robert Lacoste, “Analyzing a Case of the Jitters: Tips for Preventing Digital Design Issues,” Circuit Cellar 273, 2013.

In this final installment of my four-part mini-series about selecting an oscilloscope, I’ll look at triggering, waveform generators, and clock synchronization, and I’ll wrap up with a series summary.

My previous posts have included Part 1, which discusses probes and physical characteristics of stand-alone vs. PC-based oscilloscopes; Part 2, which examines core specifications such as bandwidth, sample rate, and ADC resolution; and Part 3, which focuses on software. My posts are more a “collection of notes” based on my own research rather than a completely thorough guide. But I hope they are useful and cover some points you might not have otherwise considered before choosing an oscilloscope.

Topic 1: Triggering Methods
Triggering your oscilloscope properly can make a huge difference in being able to capture useful waveforms. The most basic triggering method is just a “rising” or “falling” edge, which almost everyone is (or should be) familiar with.

Whether you need a more advanced trigger method will depend greatly on your usage scenario and a bit on other details of your oscilloscope. If you have a very long buffer length or ability to rapid-fire record a number of waveforms, you might be able to live with a simple trigger since you can easily throw away data that isn’t what you are looking for. If your oscilloscope has a more limited buffer length, you’ll need to trigger on the exact moment of interest.

Before I detail some of the other methods, I want to mention that you can sometimes use external instruments for triggering. For example, you might have a logic analyzer with an extremely advanced triggering mechanism. If that logic analyzer has a “trigger out,” you can trigger the oscilloscope from your logic analyzer.

On to the trigger methods! There are a number of them related to finding “odd” pulses: for example, finding glitches shorter or wider than some length or finding a pulse that is lower than the regular height (called a “runt pulse”). By knowing your scope triggers and having a bit of creativity, you can perform some more advanced troubleshooting. For example, when troubleshooting an embedded microcontroller, you can have it toggle an I/O pin when a task runs. Using a trigger to detect a “pulse dropout,” you can trigger your oscilloscope when the system crashes—thus trying to see if the problem is a power supply glitch, for example.

If you are dealing with digital systems, be on the lookout for triggers that can function on serial protocols. For example, the Rigol Technologies stand-alone units have this ability, although you’ll also need an add-on to decode the protocols! In fact, most of the serious stand-alone oscilloscopes seem to have this ability (e.g., those from Agilent, Tektronix, and Teledyne LeCroy); you may just need to pay extra to enable it.

Topic 2: External Trigger Input
Most oscilloscopes also have an “external trigger input.” This external input doesn’t display on the screen but can be used for triggering. Specifically, this means your trigger channel doesn’t count against your “ADC channels.” So if you need the full sample rate on one channel but want to trigger on another, you can use the “ext in” as the trigger.
Oscilloscopes that include this feature on the front panel make it slightly easier to use; otherwise, you’re reaching around behind the instrument to find the trigger input.

Topic 3: Arbitrary Waveform Generator
This isn’t strictly an oscilloscope-related function, but since enough oscilloscopes include some sort of function generator it’s worth mentioning. This may be a standard “signal generator,” which can generate waveforms such as sine, square, triangle, etc. A more advanced feature, called an arbitrary waveform generator (AWG), enables you to generate any waveform you want.

I previously had a (now very old) TiePie engineering HS801 that included an AWG function. The control software made it easy to generate sine, square, triangle, and a few other waveforms. But the only method of generating an arbitrary waveform was to load a file you created in another application, which meant I almost never used the “arbitrary” portion of the AWG. The lesson here is that if you are going to invest in an AWG, make sure the software is reasonable to use.

The AWG may have a few different specifications; look for the maximum analog bandwidth along with the sample rate. Be careful of outlandish claims: a 200 MS/s digital to analog converter (DAC) could hypothetically have a 100-MHz analog bandwidth, but the signal would be almost useless. You could only generate some sort of sine wave at that frequency, which would probably be full of harmonics. Even if you generated a lower-frequency sine wave (e.g., 10 MHz), it would likely contain a fair amount of harmonics since the DAC’s output filter has a roll-off at such a high frequency.

Better systems will have a low-pass analog filter to reduce harmonics, with the DAC’s sample rate being several times higher than the output filter roll-off. The Pico Technology PicoScope 6403D oscilloscope I’m using can generate a 20-MHz signal but has a 200 MS/s sample rate on the DAC. Similarly, the TiePie engineering HS5-530 has a 30-MHz signal bandwidth, and similarly uses a 240 MS/s sample rate. A sample rate of around five to 10 times the analog bandwidth seems about standard.

Having the AWG integrated into the oscilloscope opens up a few useful features. When implementing a serial protocol decoder, you may want to know what happens if the baud rate is slightly off from the expected rate. You can quickly perform this test by recording a serial data packet on the oscilloscope, copying it to the AWG, and adjusting the AWG sample rate to slightly raise or lower the baud rate. I illustrate this in the following video.

Topic 4: Clock Synchronization
One final issue of interest: In certain applications, you may need to synchronize the sample rate to an external device. Oscilloscopes will often have two features for doing this. One will output a clock from the oscilloscope, the other will allow you to feed an external clock into the oscilloscope.

The obvious application is synchronizing a capture between multiple oscilloscopes. You can, however, use this for any application where you wish to use a synchronous capture methodology. For example, if you wish to use the oscilloscope as part of a software-defined radio (SDR), you may want to ensure the sampling happens synchronous to a recovered clock.

The input frequency of this clock is typically 10 MHz, although some devices enable you to select between several allowed frequencies. If the source of this clock is anything besides another instrument, you may have to do some clock conditioning to convert it into one of the valid clock source ranges.

Summary and Closing Comments
That’s it! Over the past four weeks I’ve tried to raise a number of issues to consider when selecting an oscilloscope. As previously mentioned, the examples were often PicoScope-heavy simply because it is the oscilloscope I own. But all the topics have been relevant to any other oscilloscope you may have.

You can check out my YouTube playlist dealing with oscilloscope selection and review. Some topics might suggest further questions to ask.

I’ve probably overlooked a few issues, but I can’t cover every possible oscilloscope and option. When selecting a device, my final piece of advice is to download the user manual and study it carefully, especially for features you find most important. Although the datasheet may gloss over some details, the user manual will typically address the limitations you’ll run into, such as FFT length or the memory depths you can configure.

Author’s note: Every reasonable effort has been made to ensure example specifications are accurate. There may, however, be errors or omissions in this article. Please confirm all referenced specifications with the device vendor.

Are you an analog aficionado? You’re in luck. Two articles, in particular, focus on the November issue’s analog techniques theme. (Look for the issue shortly after mid-October, when it will be available on our website.)

Data from the base adapter is sent by level shifting the RS-232 or CMOS serial data between 9 and 12 V. A voltage comparator at the remote adapter slices the signal to generate a 0-to-5-V logic signal. The voltage on the signal wire never goes low enough for the 5-V regulator to go out of regulation.

These adapters use a combination of tricks. A single pair of wires carries full-duplex serial data and a small amount of power to a remote device for tasks (e.g., continuous remote data collection and control). The digital signals can be simple on/off signals or more complex signals (e.g., RS-232).

Dick Cappels, a consultant who tinkers with analog and mixed-signal projects, presents a design using a pair of cable adapters and simple analog circuits to enable full-duplex, bidirectional communications and power over more than 100 m of paired wires. Why bother when Power Over Ethernet (PoE), Bluetooth, and Wi-Fi approaches are available?

“In some applications, using Ethernet is a disadvantage because of the higher costs and greater interface complexity,” Cappels says. “You can use a microcontroller that costs less than a dollar and a few analog parts described in this article to perform remote data gathering and control.”

The base unit including the 5-to-15-V power supply is simple for its functionality. The two eight-pin DIP ICs are a voltage comparator and the switching regulator.

Cappels’s need for data channels to monitor his inground water tank inspired his design. Because his local municipality did not always keep the tank filled, he needed to know when it was dry so his pumps wouldn’t run without water and possibly become damaged.
“Besides the mundane application of monitoring a water tank, the system would be excellent for other communication uses,” Cappels says, including computer connection to a home weather station and intrusion-detection systems. Bit rates up to 250 kHz also enable the system to be used in two-way voice communication such as intercoms, he says.

Retired engineer David Cass Tyler became interested in writing his series about calibration while working on a consulting project. “I came to realize that some people don’t really know how to approach the issue of taking an analog-to-digital value to actual engineering units, nor how to correct calibration factors after the fact,” Tyler says

In Part 1 of his article series, Tyler notes: “Digital inputs and digital outputs are pretty simple. They are either on or off. However, for ADCs and DACs to be accurate, they must first be calibrated. This article addresses linear ADCs and DACs.” Part 2, appearing in the December issue, will discuss using polynomial curve fitting to convert nonlinear data to real-world engineering values.

In addition to its analog-themed articles, the November issue includes topics ranging from a DIY solar array tracker’s software to power-capped computer systems.

Editor’s Note: Learn more about Circuit Cellar contributors Dick Cappels and David Cass Tyler by reading their posts about their workspaces and favorite DIY tools.