* ''Multiple interchangeable CPU models.'' The gem5 simulator currently provides three interchangeable CPU objects: a simple, functional, one-CPI CPU; a detailed model of an in-order CPU, and a detailed model of an out-of-order SMT-capable CPU. The CPU models use a common high-level ISA description. In addition, a number of random memory-system testers are provided.

* ''Multiple interchangeable CPU models.'' The gem5 simulator currently provides three interchangeable CPU objects: a simple, functional, one-CPI CPU; a detailed model of an in-order CPU, and a detailed model of an out-of-order SMT-capable CPU. The CPU models use a common high-level ISA description. In addition, a number of random memory-system testers are provided.

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* ''Event-driven memory system.'' The gem5 simulator features a detailed, event-driven memory system including non-blocking caches, split-transaction busses/crossbars, and a fast and accurate DRAM controller model, for capturing the impact of current and emerging memories. These components can be arranged flexibly, e.g., to model complex multi-level cache hierarchies. The caches support a separable coherence policy module; gem5 currently includes a simple snooping cache coherence protocol.

+

* ''Event-driven memory system.'' The gem5 simulator features a detailed, event-driven memory system including non-blocking caches, split-transaction busses/crossbars, and a fast and accurate DRAM controller model, for capturing the impact of current and emerging memories, e.g. LPDDR3/4, DDR3/4, HBM, WideIO1/2. These components can be arranged flexibly, e.g., to model complex multi-level cache hierarchies. The caches support a separable coherence policy module; gem5 currently includes a simple snooping cache coherence protocol.

* ''Multiple ISA support.'' The gem5 simulator decouples ISA semantics from its timing CPU models, enabling effective support of multiple ISAs. The gem5 simulator currently supports the Alpha, ARM, SPARC, MIPS, POWER and x86 ISAs. See [[Supported Architectures]] for more information.

* ''Multiple ISA support.'' The gem5 simulator decouples ISA semantics from its timing CPU models, enabling effective support of multiple ISAs. The gem5 simulator currently supports the Alpha, ARM, SPARC, MIPS, POWER and x86 ISAs. See [[Supported Architectures]] for more information.

Revision as of 09:07, 27 November 2014

The gem5 Simulator System

A modular platform for computer system architecture research

About

The gem5 simulator is a modular platform for computer system architecture research, encompassing system-level architecture as well as processor microarchitecture.

Download

The current public release of the gem5 simulator is available at http://repo.gem5.org. (See the Repository page for details.) Auxiliary files are available on on our Download page. Please look at the sidebar for links to file bugs and for mailing list subscription information.

Key features

Pervasive object orientation. Major simulation structures (CPUs, crossbars, caches, etc.) are represented as objects, both externally and internally. The gem5 configuration language allows flexible composition of these objects to describe complex simulation targets, e.g., multi-system networks where each system comprises multiple CPUs and a hierarchy of caches. The simulator's internal object orientation (using C++) provides in addition to the usual software engineering advantages.

Multiple interchangeable CPU models. The gem5 simulator currently provides three interchangeable CPU objects: a simple, functional, one-CPI CPU; a detailed model of an in-order CPU, and a detailed model of an out-of-order SMT-capable CPU. The CPU models use a common high-level ISA description. In addition, a number of random memory-system testers are provided.

Event-driven memory system. The gem5 simulator features a detailed, event-driven memory system including non-blocking caches, split-transaction busses/crossbars, and a fast and accurate DRAM controller model, for capturing the impact of current and emerging memories, e.g. LPDDR3/4, DDR3/4, HBM, WideIO1/2. These components can be arranged flexibly, e.g., to model complex multi-level cache hierarchies. The caches support a separable coherence policy module; gem5 currently includes a simple snooping cache coherence protocol.

Multiple ISA support. The gem5 simulator decouples ISA semantics from its timing CPU models, enabling effective support of multiple ISAs. The gem5 simulator currently supports the Alpha, ARM, SPARC, MIPS, POWER and x86 ISAs. See Supported Architectures for more information.

Full-system capability.

Alpha: The gem5 simulator models a DEC Tsunami system in sufficient detail to boot unmodified Linux 2.4/2.6, FreeBSD, or L4Ka::Pistachio. We have also booted HP/Compaq's Tru64 5.1 operating system in the past, though we no longer actively maintain that capability.

ARM: The gem5 simulator can model up to eight cores of a Realview ARM development board with sufficient detail to boot unmodified Linux 2.6.35+ with a simple, in-order or out-of-order CPU. The ARM implementation supports 32 or 64-bit kernels and applications.

SPARC: The gem5 simulator models a single core of a UltraSPARC T1 processor with sufficient detail to boot Solaris in a similar manner as the Sun T1 Architecture simulator tools (building the hypervisor with specific defines and using the HSMID virtual disk driver).

x86: The gem5 simulator supports a standard PC platform

Multiprocessor / multi-system capability. Thanks to gem5's object orientation, instantiation of multiple CPU objects within a system is trivial. Combined with the snooping coherence protocol supported by the caches, gem5 can model symmetric and asymmetric multiprocessor systems. Because a complete system is just a collection of objects (CPUs, caches, memory, etc.), multiple systems can be instantiated within a single simulation process. In conjunction with full-system modeling, this feature allows simulation of entire client-server networks.

Power and energy. gem5’s objects are arrange in OS-visible power and clock domains, enabling a range of experiments in power- and energy-efficiency. With out-of-the-box support for OS-controller Dynami Voltage and Frequency (DVFS) scaling, gem5 provides a complete platform for research in future energy-efficient systems. See how to run your own DVFS experiments.

Additional details

Platforms. The gem5 simulator runs on most operating systems (Linux, MacOS X, Solaris, OpenBSD, Cygwin) and architectures (x86, x86-64, ARM, SPARC, Alpha, and PPC). However, all guest platforms aren't supported on all host platforms (most notably Alpha requires little-endian hardware). It is readily portable to other hosts and other Unix-like operating systems that are supported by GCC and/or clang.

Licensing. The gem5 simulator is released under a Berkeley-style open source license. Roughly speaking, you are free to use our code however you wish, as long as you leave our copyright on it. For more details, see the LICENSE file included in the source download. Note that the portions of gem5 derived from other sources are also subject to the licensing restrictions of the original sources.

We have archived material from various tutorials, which provide a more organized overview than the wiki, along with some "how to" information not currently found elsewhere.

A higher-level overview of gem5 can be found in our article The gem5 Simulator from the May 2011 issue of ACM SIGARCH Computer Architecture News. If you use gem5 in your research, we would appreciate a citation to this paper in any publications you produce.

The gem5 code is (somewhat sparsely) commented with doxygen comments. You can browse the doxygen-generated documentation here.

Publications

A list of publications using the gem5 simulator is also available. Please append to the list if you publish a paper using gem5.

If you use gem5 in your research, we would appreciate a citation to, The gem5 Simulator, from the May 2011 issue of ACM SIGARCH Computer Architecture News in any publications you produce.

Acknowledgments

The gem5 simulator has been developed with generous support from
several sources, including the National Science Foundation, AMD, ARM,
Hewlett-Packard, IBM, Intel, MIPS, and Sun.
Individuals working on gem5 have also been supported by fellowships from
Intel, Lucent, and the Alfred P. Sloan Foundation.
This material is based upon work supported by the National Science
Foundation under the following grants: CCR-0105503, CCR-0219640,
CCR-0324878, EAI/CNS-0205286, and CCR-0105721.

Any opinions, findings and conclusions or recommendations expressed in
this material are those of the author(s) and do not necessarily
reflect the views of the National Science Foundation (NSF) or any
other sponsor.