Tampakuro/kuroguy discovered the layout of the JTAG Port on LS Pro v1 and an early KuroPro by tracing the wiring. The account of his work and early efforts is here : [http://forum.nas-central.org/viewtopic.php?f=39&t=3001 JTAG for the LS Pro and LS Live]. He found that the v1 had a non-standard pinout. The v2 LS Live has a [http://hri.sourceforge.net/tools/jtag_faq_org.html#_Toc63218717 standard ARM 20 pin layout]. mdfirefighter and others discovered that Dominic Rath's OpenOCD software was the key to opening the LS Pro to JTAG - this is detailed in the same thread linked to above.

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===LS Pro and LS Live===

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===LS Pro/LS Live (arm9)===

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See the article at [http://buffalo.nas-central.org/index.php/JTAG_%26_OpenOCD_for_LS-Pro JTAG & OpenOCD for the LS-Pro] for complete details and instructions.

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====Flash structure====

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For the LSProV2, here is the output of flinfo while in u-boot:

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Marvell>> flinfo

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Bank # 1: SST SST39VF020 (2 Mbit)

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Size: 256 kB,Bus Width: 1, device Width: 1.

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Flash base: 0xfffc0000,Number of Sectors: 64 Type: REGULAR.

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Sector Start Addresses:

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00000000 (RO) 00001000 (RO) 00002000 (RO) 00003000 (RO) 00004000 (RO)

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00005000 (RO) 00006000 (RO) 00007000 (RO) 00008000 (RO) 00009000 (RO)

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0000a000 (RO) 0000b000 (RO) 0000c000 (RO) 0000d000 (RO) 0000e000 (RO)

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0000f000 (RO) 00010000 (RO) 00011000 (RO) 00012000 (RO) 00013000 (RO)

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00014000 (RO) 00015000 (RO) 00016000 (RO) 00017000 (RO) 00018000 (RO)

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00019000 (RO) 0001a000 (RO) 0001b000 (RO) 0001c000 (RO) 0001d000 (RO)

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0001e000 (RO) 0001f000 (RO) 00020000 (RO) 00021000 (RO) 00022000 (RO)

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00023000 (RO) 00024000 (RO) 00025000 (RO) 00026000 (RO) 00027000 (RO)

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00028000 (RO) 00029000 (RO) 0002a000 (RO) 0002b000 (RO) 0002c000 (RO)

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0002d000 (RO) 0002e000 (RO) 0002f000 (RO) 00030000 (RO) 00031000 (RO)

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00032000 (RO) 00033000 (RO) 00034000 (RO) 00035000 (RO) 00036000 (RO)

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00037000 (RO) 00038000 (RO) 00039000 (RO) 0003a000 (RO) 0003b000 (RO)

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0003c000 (RO) 0003d000 (RO) 0003e000 (RO) 0003f000

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====Background and Required Hardware Software====

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CAUTION : USE AT YOUR OWN RISK. IT IS POSSIBLE TO BRICK ONE'S BOX WITH THESE METHODS. UNBRICKING IS NOT GUARANTEED.

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These directions have been tested and checked on a LSProV2. The OCD software we use is [http://openfacts.berlios.de/index-en.phtml?title=Open_On-Chip_Debugger OpenOCD], created by Dominic Rath.

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*[http://openfacts.berlios.de/index-en.phtml?title=Open_On-Chip_Debugger OpenOCD]. You should probably work with the version that most of us here have used - [http://downloads.nas-central.org/ALL_LS_KB_ARM9/openocd-lspro.tgz download it from here].

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*JTAG adapter like the Olimex ARM-USB-TINY (tested) or a Wiggler (Wigglers and other paraport adapters seem slower than USB).

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*an x86 desktop/laptop running Linux (tested w/ Ubuntu 7.10)

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*JTAG headers already attached to your ARM-based LinkStation's board

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====Setting Up OpenOCD====

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*Compiling- See [http://openfacts.berlios.de/index-en.phtml?title=Building_OpenOCD Building OpenOCD] for full details. Some hints are listed below for using it with the Olimex JTAG USB TINY adapter, which is ftdi-based.

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**Install libftdi (http://www.intra2net.com/opensource/ftdi/) or libftd2xx (http://www.ftdichip.com/Drivers/D2XX.htm). Most accounts seem to indicate that more users have better luck with libftdi (which is available as a package for Ubuntu, for instance.)

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**Build and install OpenOCD. Download it from the downloads on our site, or from svn at the OpenOCD site. Then configure, make and make install.

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./configure --enable-ft2232_libftdi

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make

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make install

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Also, '''if you are using libftdi''', you may have to add the following line to your /etc/fstab:

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none /proc/bus/usb usbfs defaults,devmode=0666 0 0

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If you are using a parallel port Wiggler, you should read the literature and docs in the source, as they will guide you on what to do in terms of configuring before building.

*Available Commands in OpenOCD - Listed for reference. While working in the telnet daemon window w/ OpenOCD, entering the command '''help''' will yield a list of available commands and summary of help.

You will need to do both of the following as root (note that some users state that there is an advantage in doing these in rapid succession):

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*In a terminal window, cd to your OpenOCD config file and start it. From this window you will see only diagnostic information, mainly. Change directory to the docs/configs in the openocd directory. Then start openocd, directing it to use the config file that you have set up previously.

The error seems commonplace to most of us that have used it. Until we know otherwise, most of us are assuming it is not a huge problem.

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OpenOCD is now running.

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*In a second terminal window, start telnet pointed to loopback, port 4444. This window is where you will control the communication and commands to your device via the jtag interface. You will have to halt your processor, verify the flash banks, and probe them (so that they are recognized properly).

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root@bitbaker-i686:/usr/src# telnet localhost 4444

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Trying 127.0.0.1...

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Connected to localhost.

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Escape character is '^]'.

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Open On-Chip Debugger

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> halt

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requesting target halt...

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> Target 0 halted

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target halted in ARM state due to debug request, current mode: Abort

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cpsr: 0x600000d7 pc: 0x00000028

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MMU: disabled, D-Cache: disabled, I-Cache: enabled

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> flash banks

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#0: cfi at 0xfffc0000, size 0x00040000, buswidth 1, chipwidth 1

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> flash probe 0

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flash 'cfi' found at 0xfffc0000

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Once this is done, you have verified that you have proper access to the flash. Now erase it, check your erase and then write the u-boot.bin file to flash. This may take anywhere from about an hour up to 5 or 6 hours. Do not interrupt the process.

wrote file /usr/src/openocd-package/doc/configs/lspstock052207.bin to flash bank 0 at offset 0xfffc0000 in 12107s 811284us

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>

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====Verifying Flash and Flashing====

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To check to see if your flashing was successful (that the file you wanted to write to flash was actually written), dump it out and compared:

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dump_image currentcontents.bin 0xfffc0000 0x40000

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diff currentcontents.bin lspstock052207.bin

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The second command should return nothing if the flash contents are identical to the image file.

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====Notes and Special Situations====

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At least a handful of us have flashed once or twice, and then been able to proceed with a third flash. Presumably, the processor was in a state that allowed us to do the first flash(es) but for some unknown reason comes to be in some less manageable state. The difficulty for some of us has been getting the processor halted.

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Also, it is important to note that we are awaiting a possible (but not promised or guaranteed) version of OpenOCD that will work with the Feroceon processor that is in our ARM-based boxes. The processor is not a true ARM926, so we can't count on everything on OpenOCD to work, until some changes are made.