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Fast Data Converters Advance Wireless Systems

This high-speed analog-to-digital converter and digital-to-analog converter help to forge next-generation cellular-base-station receivers and transmitters.

Jack Browne | Feb 28, 2005

Data converters can be thought of as the central cores of wireless-infrastructure systems. Complex signals must be digitized upon reception and converted to analog form for transmission. To meet the needs of present and future-generation wireless-infrastructure systems, analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) must therefore perform at RF rates and with outstanding linearity. The AD9444 ADC and AD9779 DAC from Analog Devices are examples of high-speed data converters that are making both third-generation (3G) wireless systems and future-looking broadband wireless applications possible.

The AD9444 is based on a BiCMOS, monolithic 14-b ADC. It boasts an on-chip track-and-hold (T/H) amplifier, reference, clock/timing-management circuitry, and low-voltage-differential-signal (LVDS) buffering (SEE FIGURE). The device, which is capable of sampling rates up to 80 Msamples/s, has been optimized for low power consumption even when processing multicarrier signals. It is designed for use with voltage supplies of +3.3 and +5 VDC. At the full sampling rate, the ADC consumes 1.2 W or less.

To digitize even complex intermediate-frequency (IF) signals with minimal distortion, the ADC has been designed with an analog bandwidth of 650 MHz. In multicarrier or wideband single-carrier 3G systems like W-CDMA, several ADC specifications are of particular importance. These specifications include spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNR). In a multicarrier or wideband receiver, an ADC must process a large swath of signals that is present at the receive antenna. Much of the channelization and demodulation take place in the digital realm.

The ADC is faced with the desired 3G signals as well as blockers and interfering signals from other wireless systems, such as GSM. As a result, it must digitize a wide bandwidth with a high dynamic range. The SFDR and SNR specifications indicate the dynamic performance in the presence of spurious signals as well as with noise. For example, good SFDR performance translates to improved near/far reception in the presence of a blocker within the spectrum of interest.

For the AD9444, both parameters are impressive. It provides a two-tone SFDR of 100 dB when tested with signals offset by 1 MHz at 69.3 and 70.3 MHz. For system integrators who are more concerned with single-tone wideband performance, the single-tone SFDR is 97 dB at 70 MHz (or about 5 to 7 dB better than the next-nearest competitor). The AD9444 achieves a signal-to-noise ratio (SNR) of 73.1 dB when tested with a 70-MHz input signal.

The static-linearity performance of an ADC is usually characterized in terms of its integral-nonlinearity (INL) and differential-nonlinearity (DNL) errors. Such performance is measured by the amount of deviation in the transfer function in terms of the converter's least significant bits (LSBs). For the AD9444, the INL performance is rated as ±1 LSB. The DNL performance is rated as ±0.3 LSB.

The converter employs LVDS balanced outputs (ANSI-644 compatible) as introduced in the company's earlier AD9430 converter. LVDS data outputs help to isolate the ADC core in order to minimize digital noise and simplify printed-circuit-board (PCB) layouts. The low-voltage outputs minimize electromagnetic interference (EMI) with intrinsically shorter switching times. At the same time, the differential signal paths provide common-mode noise rejection.

The AD9444 works with differential input signals from 1 to 2 V peak to peak. Out-of-range outputs indicate when an input signal is beyond the acceptable operating range. A clock-duty-cycle stabilizer supports a wide range of clock pulse widths. To simplify data capture, the ADC includes data-format function and output-clock-select function. (It is supplied in a lead-free, 100-pin TQFP ePAD housing).

The AD9444's performance is rated for the industrial temperature range from −40° to +85°C. In addition to use in multicarrier, multimode cellular-base-station receivers, the ADC is suited for antenna array positioning, power-amplifier linearization schemes, broadband radar systems, and communications test equipment.

On the other side of the data-converter chain, the model AD9779 is a dual-transmit DAC that's capable of 16-b resolution while supporting signal-generation rates to 1 Gsample/s. Like the AD9444, it is designed for high-linearity performance with wide dynamic range and low power consumption. Geared for voltage supplies of +1.8 and +3.3 VDC, the AD9779 consumes 950 mW of power when operating at a sampling rate of 1 Gsample/s. It consumes only 600 mW when operating at 500 Msamples/s or about 14% lower power than existing 16-b devices at 500 Msamples/s.

The AD9779 is based upon a proven DAC core circuit fabricated in an established 0.18-µm silicon CMOS process. It provides the high performance and features that are required for direct-conversion or IF-synthesis-based 3G cellular transmitters. It boasts a noise spectral density (NSD) of −161 dBm/Hz at 70 MHz with an intermodulation distortion (IMD) of only −92 dBc. The SFDR for a single 70-MHz tone is 88 dB and a still outstanding 82 dB when generating a 100-MHz output signal. The adjacent-channel leakage ratio (ACLR) is 80 dBc when synthesizing an intermediate-frequency (IF) signal of 80 MHz. The INL performance is ±5 LSB while the DNL performance is ±1.5 LSB.

The AD9779 includes selectable 2X, 4X, and 8X halfband interpolation filters. Its single-ended CMOS interface supports a maximum data input rate of 300 Msamples/s with 1× interpolation. The maximum DAC update rate is 1 Gsample/s. Analog output current can be programmed from 10 to 30 mA. It includes an interface to synchronize multiple chips for multicarrier synthesis applications as well as a configurable clock multiplier/divider for use with a wide range of clock sources. The DAC boasts a flexible data interface including twos complement or straight binary with single or dual-port inputs. It has an SPI interface for configuration control and a channel-matching control for optimal local-oscillator/single-sideband (LO/SSB) cancellation.

A built-in synchronization scheme allows multiple DACs to be time aligned with tight precision up to the full 1-Gsample/s sampling rate. Programmable delay lines on the data-clock and synchronization inputs provide flexibility in meeting set-up and hold timing requirements. Together, these features provide 300-ps synchronization accuracy.

The dual DAC is ideal for creating complex modulation formats and executing digital mixing. It can support multiple transmitters, such as UMTS and cdma2000 in a 20-MHz bandwidth. The AD9779 is ideal for communications transmitters as well as communications test equipment. When paired with the company's model AD8349 quadrature-modulator IC, it provides a baseband-to-RF transmit solution while still meeting transmitter spectral-mask requirements. The company offers an evaluation board that contains both the AD9779 and AD8349, providing a simple platform to test direct-conversion transmitter designs.

The AD9779 is priced at $27.95 in quantities of 1000. Contact the company for more pricing information.