READ Operation

READ bursts are initiated
with a READ command. The starting column and bank addresses are provided with
the READ command and auto precharge is either enabled or disabled for that
burst access. If auto precharge is enabled, the row being accessed is
automatically precharged at the completion of the burst. If auto precharge is
disabled, the row will be left open after the completion of the burst.

During READ bursts, the
valid data-out element from the starting column address is available READ
latency (RL) clocks later. RL is defined as the sum of posted CAS additive
latency (AL) and CAS latency (CL) (RL = AL + CL). The value of AL and CL is
programmable in the mode register via the MRS command. Each subsequent data-out
element is valid nominally at the next positive or negative clock edge (that
is, at the next crossing of CK and CK#).
READ
Latency shows an example of
RL based on a CL setting of 8 and an AL setting of 0.

Figure 1. READ
Latency

Notes

DO
n =
data-out from column
n.

Subsequent elements of
data-out appear in the programmed order following DO
n.

DQS, DQS# is driven by the
DRAM along with the output data. The initial LOW state on DQS and HIGH state on
DQS# is known as the READ preamble (tRPRE). The LOW state on DQS and the HIGH state on DQS#,
coincident with the last data-out element, is known as the READ postamble (tRPST). Upon
completion of a burst, assuming no other commands have been initiated, the DQ
goes High-Z. A detailed explanation of
tDQSQ
(valid data-out skew),
tQH
(data-out window hold), and the valid data window are depicted in
Data Strobe
Timing – READs . A detailed explanation of
tDQSCK
(DQS transition skew to CK) is also depicted in
Data Strobe
Timing – READs .

Data from any READ burst
may be concatenated with data from a subsequent READ command to provide a
continuous flow of data. The first data element from the new burst follows the
last element of a completed burst. The new READ command should be issued
tCCD
cycles after the first READ command. This is shown for BL8 in
Consecutive
READ Bursts (BL8) . If BC4 is enabled,
tCCD
must still be met, which will cause a gap in the data output, as shown in
Consecutive
READ Bursts (BC4) . Nonconsecutive READ data is reflected
in
Nonconsecutive READ Bursts . DDR3 SDRAM does not allow interrupting
or truncating any READ burst.

Data from any READ burst
must be completed before a subsequent WRITE burst is allowed. An example of a
READ burst followed by a WRITE burst for BL8 is shown in
READ (BL8)
to WRITE (BL8) (BC4 is shown in
READ (BC4)
to WRITE (BC4) OTF ). To ensure the READ data is completed
before the WRITE data is on the bus, the minimum READ-to-WRITE timing is RL +
tCCD -
WL + 2tCK.

A READ burst may be
followed by a PRECHARGE command to the same bank, provided auto precharge is
not activated. The minimum READ-to-PRECHARGE command spacing to the same bank
is four clocks and must also satisfy a minimum analog time from the READ
command. This time is called
tRTP
(READ-to-PRECHARGE).
tRTP
starts AL cycles later than the READ command. Examples for BL8 are shown in
READ to
PRECHARGE (BL8) and BC4 in
READ to
PRECHARGE (BC4) . Following the PRECHARGE command, a
subsequent command to the same bank cannot be issued until
tRP is
met. The PRECHARGE command followed by another PRECHARGE command to the same
bank is allowed. However, the precharge period will be determined by the last
PRECHARGE command issued to the bank.

If A10 is HIGH when a READ
command is issued, the READ with auto precharge function is engaged. The DRAM
starts an auto precharge operation on the rising edge, which is AL +
tRTP
cycles after the READ command. DRAM support a
tRAS
lockout feature (see
READ with
Auto Precharge (AL = 4, CL = 6) ). If
tRAS
(MIN) is not satisfied at the edge, the starting point of the auto precharge
operation will be delayed until
tRAS
(MIN) is satisfied. If
tRTP
(MIN) is not satisfied at the edge, the starting point of the auto precharge
operation is delayed until
tRTP
(MIN) is satisfied. In case the internal precharge is pushed out by
tRTP,
tRP
starts at the point at which the internal precharge happens (not at the next
rising clock edge after this event). The time from READ with auto precharge to
the next ACTIVATE command to the same bank is AL + (tRTP +
tRP)*,
where * means rounded up to the next integer. In any event, internal precharge
does not start earlier than four clocks after the last 8n-bit prefetch.

Figure 2. Consecutive
READ Bursts (BL8)

Notes

NOP commands are shown for
ease of illustration; other commands may be valid at these times.

The BL8 setting is
activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
command at T0 and T4.

DO
n (or
b) =
data-out from column
n (or
column
b).

BL8, RL = 5 (CL = 5, AL =
0).

Figure 3. Consecutive
READ Bursts (BC4)

Notes

NOP commands are shown for
ease of illustration; other commands may be valid at these times.

The BC4 setting is
activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ
command at T0 and T4.

DO
n (or
b) =
data-out from column
n (or
column
b).

BC4, RL = 5 (CL = 5, AL =
0).

Figure 4. Nonconsecutive READ Bursts

Notes

AL = 0, RL = 8.

DO
n (or
b) =
data-out from column
n (or
column
b).

Seven subsequent elements
of data-out appear in the programmed order following DO
n.

Seven subsequent elements
of data-out appear in the programmed order following DO
b.

Figure 5. READ (BL8)
to WRITE (BL8)

Notes

NOP commands are shown for
ease of illustration; other commands may be valid at these times.

The BL8 setting is
activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the READ
command at T0, and the WRITE command at T6.

DO
n =
data-out from column, DI
b =
data-in for column
b.

BL8, RL = 5 (AL = 0, CL =
5), WL = 5 (AL = 0, CWL = 5).

Figure 6. READ (BC4)
to WRITE (BC4) OTF

Notes

NOP commands are shown for
ease of illustration; other commands may be valid at these times.

The BC4 OTF setting is
activated by MR0[1:0] and A12 = 0 during READ command at T0 and WRITE command
at T4.

DO
n =
data-out from column
n; DI
n =
data-in from column
b.

BC4, RL = 5 (AL - 0, CL =
5), WL = 5 (AL = 0, CWL = 5).

Figure 7. READ to
PRECHARGE (BL8)

Figure 8. READ to
PRECHARGE (BC4)

Figure 9. READ to
PRECHARGE (AL = 5, CL = 6)

Figure 10. READ with
Auto Precharge (AL = 4, CL = 6)

DQS to DQ output timing is
shown in
Data Output
Timing –
tDQSQ
and Data Valid Window . The DQ transitions between valid data
outputs must be within
tDQSQ of
the crossing point of DQS, DQS#. DQS must also maintain a minimum HIGH and LOW
time of
tQSH and
tQSL.
Prior to the READ preamble, the DQ balls will either be floating or terminated,
depending on the status of the ODT signal.

Data Strobe
Timing – READs also shows the READ preamble and
postamble. Typically, both DQS and DQS# are High-Z to save power (VDDQ). Prior to data output from the DRAM, DQS is driven
LOW and DQS# is HIGH for
tRPRE.
This is known as the READ preamble.

The READ postamble,
tRPST,
is one half clock from the last DQS, DQS# transition. During the READ
postamble, DQS is driven LOW and DQS# is HIGH. When complete, the DQ is
disabled or continues terminating, depending on the state of the ODT signal.
demonstrates how to measure
tRPST.

Figure 11. Data Output
Timing –
tDQSQ
and Data Valid Window

Notes

NOP commands are shown for
ease of illustration; other commands may be valid at these times.

tDQSQ defines the
skew between DQS, DQS# to data and does not define DQS, DQS# to CK.

Early data transitions may
not always happen at the same DQ. Data transitions of a DQ can be early or late
within a burst.

tHZ and
tLZ
transitions occur in the same access time as valid data transitions. These
parameters are referenced to a specific voltage level that specifies when the
device output is no longer driving
tHZDQS
and
tHZDQ,
or begins driving
tLZDQS,
tLZDQ.
Method for
Calculating
tLZ and
tHZ shows a method of calculating the point
when the device is no longer driving
tHZDQS
and
tHZDQ,
or begins driving
tLZDQS,
tLZDQ,
by measuring the signal at two different voltages. The actual voltage
measurement points are not critical as long as the calculation is consistent.
The parameters
tLZDQS,
tLZDQ,
tHZDQS,
and
tHZDQ
are defined as single-ended.

Figure 12. Data Strobe
Timing – READs

Figure 13. Method for
Calculating
tLZ and
tHZ

Notes

Within a burst, the rising
strobe edge is not necessarily fixed at
tDQSCK (MIN) or
tDQSCK (MAX). Instead, the rising strobe edge can vary
between
tDQSCK (MIN) and
tDQSCK (MAX).

The DQS HIGH pulse width is
defined by
tQSH, and the DQS LOW pulse width is defined by
tQSL. Likewise,
tLZDQS (MIN) and
tHZDQS (MIN) are not tied to
tDQSCK (MIN) (early strobe case), and
tLZDQS (MAX) and
tHZDQS (MAX) are not tied to
tDQSCK (MAX) (late strobe case); however, they tend to
track one another.

The minimum pulse width of
the READ preamble is defined by
tRPRE (MIN). The minimum pulse width of the READ postamble
is defined by
tRPST (MIN).

Figure 14. tRPRE Timing

Figure 15. tRPST Timing

Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

WRITE Operation

WRITE bursts are initiated
with a WRITE command. The starting column and bank addresses are provided with
the WRITE command, and auto precharge is either enabled or disabled for that
access. If auto precharge is selected, the row being accessed is precharged at
the end of the WRITE burst. If auto precharge is not selected, the row will
remain open for subsequent accesses. After a WRITE command has been issued, the
WRITE burst may not be interrupted. For the generic WRITE commands used in
WRITE
Burst through
WRITE (BC4
Mode Register Setting) to PRECHARGE , auto precharge is disabled.

During WRITE bursts, the
first valid data-in element is registered on a rising edge of DQS following the
WRITE latency (WL) clocks later and subsequent data elements will be registered
on successive edges of DQS. WRITE latency (WL) is defined as the sum of posted
CAS additive latency (AL) and CAS WRITE latency (CWL): WL = AL + CWL. The
values of AL and CWL are programmed in the MR0 and MR2 registers, respectively.
Prior to the first valid DQS edge, a full cycle is needed (including a dummy
crossover of DQS, DQS#) and specified as the WRITE preamble shown in
WRITE
Burst . The half cycle on DQS following the
last data-in element is known as the WRITE postamble.

Data may be masked from
completing a WRITE using data mask. The data mask occurs on the DM ball aligned
to the WRITE data. If DM is LOW, the WRITE completes normally. If DM is HIGH,
that bit of data is masked.

Upon completion of a burst,
assuming no other commands have been initiated, the DQ will remain High-Z, and
any additional input data will be ignored.

Notes

Seven subsequent elements
of data-in are applied in the programmed order following DO
n.

Each WRITE command may be
to any bank.

Shown for WL = 7 (CWL = 7,
AL = 0).

Figure 7. WRITE (BL8)
to READ (BL8)

Notes

NOP commands are shown for
ease of illustration; other commands may be valid at these times.

tWTR controls the
WRITE-to-READ delay to the same device and starts with the first rising clock
edge after the last write data shown at T9.

The BL8 setting is
activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and MR0[12] = 1 during the
WRITE command at T0. The READ command at Ta0 can be either BC4 or BL8,
depending on MR0[1:0] and the A12 status at Ta0.

DI
n =
data-in for column
n.

RL = 5 (AL = 0, CL = 5), WL
= 5 (AL = 0, CWL = 5).

Figure 8. WRITE to
READ (BC4 Mode Register Setting)

Notes

NOP commands are shown for
ease of illustration; other commands may be valid at these times.

tWTR controls the
WRITE-to-READ delay to the same device and starts with the first rising clock
edge after the last write data shown at T7.

The fixed BC4 setting is
activated by MR0[1:0] = 10 during the WRITE command at T0 and the READ command
at Ta0.

DI
n =
data-in for column
n.

BC4 (fixed), WL = 5 (AL =
0, CWL = 5), RL = 5 (AL = 0, CL = 5).

Figure 9. WRITE (BC4
OTF) to READ (BC4 OTF)

Notes

NOP commands are shown for
ease of illustration; other commands may be valid at these times.

tWTR controls the
WRITE-to-READ delay to the same device and starts after
tBL.

The BC4 OTF setting is
activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and the
READ command at Tn.

DI
n =
data-in for column
n.

BC4, RL = 5 (AL = 0, CL =
5), WL = 5 (AL = 0, CWL = 5).

Figure 10. WRITE (BL8)
to PRECHARGE

Notes

DI
n =
data-in from column
n.

Seven subsequent elements
of data-in are applied in the programmed order following DO
n.

Shown for WL = 7 (AL = 0,
CWL = 7).

Figure 11. WRITE (BC4
Mode Register Setting) to PRECHARGE

Notes

NOP commands are shown for
ease of illustration; other commands may be valid at these times.

The write recovery time
(tWR) is
referenced from the first rising clock edge after the last write data is shown
at T7.
tWR specifies the last burst WRITE cycle until the
PRECHARGE command can be issued to the same bank.

The fixed BC4 setting is
activated by MR0[1:0] = 10 during the WRITE command at T0.

DI
n =
data-in for column
n.

BC4 (fixed), WL = 5, RL =
5.

Figure 12. WRITE (BC4
OTF) to PRECHARGE

Notes

NOP commands are shown for
ease of illustration; other commands may be valid at these times.

The write recovery time
(tWR) is
referenced from the rising clock edge at T9.
tWR specifies the last burst WRITE cycle until the
PRECHARGE command can be issued to the same bank.

The BC4 setting is
activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0.

DI
n =
data-in for column
n.

BC4 (OTF), WL = 5, RL = 5.

DQ Input
Timing

WRITE
Burst shows the strobe-to-clock timing during
a WRITE burst. DQS, DQS# must transition within 0.25tCK of the clock
transitions, as limited by
tDQSS.
All data and data mask setup and hold timings are measured relative to the DQS,
DQS# crossing, not the clock crossing.

The WRITE preamble and
postamble are also shown in
WRITE
Burst . One clock prior to data input to the
DRAM, DQS must be HIGH and DQS# must be LOW. Then for a half clock, DQS is
driven LOW (DQS# is driven HIGH) during the WRITE preamble,
tWPRE.
Likewise, DQS must be kept LOW by the controller after the last data is written
to the DRAM during the WRITE postamble,
tWPST.

Data setup and hold times
are also shown in
WRITE
Burst . All setup and hold times are measured
from the crossing points of DQS and DQS#. These setup and hold values pertain
to data input and data mask input.

Additionally, the half
period of the data input strobe is specified by
tDQSH
and
tDQSL.

Figure 13. Data Input
Timing

Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.

PRECHARGE Operation

Input A10 determines whether one bank or all banks are to be precharged and, in the case where only one bank is to be precharged, inputs BA[2:0] select the bank.

When all banks are to be precharged, inputs BA[2:0] are treated as “Don’t Care.” After a bank is precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued.

Products and specifications discussed herein are subject to change by Micron without notice. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.