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Abstract:

A semiconductor memory device includes a block array having an m number
of memory blocks in a row direction and an n number of memory blocks in a
column direction (m being an integer of 2 or more and n being an integer
of 1 or more), a page selection circuit configured to select a row in the
block array as a page to be selected, and a page buffer configured to
store data to be written in a page selected by the page selection circuit
or data read from the page. Each of the memory blocks includes a memory
cell array having a plurality of memory cells, a row selection circuit
configured to select a row of the memory cell array, and a column
selection circuit configured to select a column of the memory cell array.

Claims:

1. A semiconductor memory device comprising: a block array having an m
number of memory blocks in a row direction and an n number of memory
blocks in a column direction (m being an integer of 2 or more and n being
an integer of 1 or more); a page selection circuit configured to select a
row in the block array as a page to be selected; and a page buffer
configured to store data to be written in a page selected by the page
selection circuit or data read from the page, wherein each of the memory
blocks comprising: a memory cell array having a plurality of memory
cells; a row selection circuit configured to select a row of the memory
cell array; and a column selection circuit configured to select a column
of the memory cell array, wherein when a row-specifying command and a row
address are given, a group of memory cells of a specific row
corresponding to the given row address is selected for each of the n
number of memory blocks aligned in the column direction in the block
array, when a column-specifying command and a column address are given, a
group of memory cells of a specific column corresponding to the given
column address is selected for each of the m number of memory blocks
aligned in the row direction in the block array, and when the page
selection circuit is given a per-page read or write command and the
corresponding page address, the page selection circuit simultaneously
selects a plurality of memory cells separated from one another in a page
indicated by the given page address among a group of memory cells
selected by a row-specifying command, a row address, a column-specifying
command and a column address that are given just before the per-page read
or write command and the corresponding page address.

2. The device of claim 1, wherein when the page selection circuit is
given a per-page read command and a page address, the page selection
circuit performs control to simultaneously select data from a plurality
of memory cells separated from one another in a page indicated by the
given page address and to store the data in the page buffer, and when the
page selection circuit is given a per-page write command and a page
address, the page selection circuit writes data stored in the page buffer
in a plurality of memory cells separated from one another in a page
indicated by the given page address.

3. The device of claim 1, wherein each of a plurality of memory cells
separated from one another in a page that are simultaneously selected by
the page selection circuit belong to different one among the memory
blocks.

4. The device of claim 1 further comprising a peripheral control circuit
configured to supply the row- and column-specifying commands and the read
and write commands input from outside in a random input order to the
block array or the page selection circuit in the input order.

5. The device of claim 1 further comprising a plurality of banks each
having the block array, the page selection circuit, and the page buffer,
wherein the row- and column-specifying commands are issued to all of the
banks or some of the banks, and the read and write commands are issued to
a specific bank.

6. The device of claim 1, wherein when issuance of at least either the
row-specifying command or the column-specifying command is omitted,
selection of a group of memory cells is performed based on an immediately
preceding issued command.

7. The device of claim 1, wherein each memory cell is an MRAM cell.

8. A memory system comprising: a semiconductor memory device; and a
controller configured to control the semiconductor memory device, wherein
the semiconductor memory device comprises: a block array having an m
number of memory blocks in a row direction and an n number of memory
blocks in a column direction (m being an integer of 2 or more and n being
an integer of 1 or more); a page selection circuit configured to select a
row in the block array as a page to be selected; and a page buffer
configured to store data to be written in a page selected by the page
selection circuit or data read from the page, wherein each of the memory
blocks comprises: a memory cell array having a plurality of memory cells;
a row selection circuit configured to select a row of the memory cell
array; and a column selection circuit configured to select a column of
the memory cell array, wherein when a row-specifying command and a row
address are given, a group of memory cells of a specific row
corresponding to the given row address is selected for each of the n
number of memory blocks aligned in the column direction in the block
array, when a column-specifying command and a column address are given, a
group of memory cells of a specific column corresponding to the given
column address is selected for each of the m number of memory blocks
aligned in the row direction in the block array, and when the page
selection circuit is given a per-page read or write command and the
corresponding page address, the page selection circuit simultaneously
selects a plurality of memory cells separated from one another in a page
indicated by the given page address among a group of memory cells
selected by a row-specifying command, a row address, a column-specifying
command and a column address that are given just before the per-page read
or write command and the corresponding page address.

9. The system of claim 8, wherein when the page selection circuit is
given a per-page read command and a page address, the page selection
circuit performs control to simultaneously read data from a plurality of
memory cells separated from one another in a page indicated by the given
page address and to store the data in the page buffer, and when the page
selection circuit is given a per-page write command and a page address,
the page selection circuit performs control to write data stored in the
page buffer in a plurality of memory cells separated from one another in
a page indicated by the given page address.

10. The system of claim 8, wherein each of a plurality of memory cells
separated from one another in a page that are simultaneously selected by
the page selection circuit belong to different one among the memory
blocks.

11. The system of claim 8 further comprising a peripheral control circuit
configured to supply the row- and column-specifying commands and the read
and write commands input from outside in a random input order to the
block array or the page selection circuit in the input order.

12. The system of claim 8 further comprising a plurality of banks each
having the block array, the page selection circuit, and the page buffer,
wherein the row- and column-specifying commands are issued to all of the
banks or some of the banks, and the read and write commands are issued to
a specific bank.

13. The system of claim 8, wherein when issuance of at least either the
row-specifying command or the column-specifying command is omitted,
selection of a group of memory cells is performed based on an immediately
preceding issued command.

14. The system of claim 8, wherein each memory cell is an MRAM cell.

15. An access method to a semiconductor memory device that comprises: a
block array having an m number of memory blocks in a row direction and an
n number of memory blocks in a column direction (m being an integer of 2
or more and n being an integer of 1 or more); a page selection circuit
configured to select a row in the block array as a page to be selected;
and a page buffer configured to store data to be written in a page
selected by the page selection circuit or data read from the page,
wherein each of the memory blocks comprises: a memory cell array having a
plurality of memory cells; a row selection circuit configured to select a
row of the memory cell array; and a column selection circuit configured
to select a column of the memory cell array, wherein the method
comprises: when a row-specifying command and a row address are given,
selecting a group of memory cells of a specific row corresponding to the
given row address for each of the n number of memory blocks aligned in
the column direction in the block array, when a column-specifying command
and a column address are given, selecting a group of memory cells of a
specific column corresponding to the given column address for each of the
m number of memory blocks aligned in the row direction in the block
array, and when the page selection circuit is given a per-page read or
write command and the corresponding page address, the page selection
circuit simultaneously selects a plurality of memory cells separated from
one another in a page indicated by the given page address among a group
of memory cells selected by a row-specifying command, a row address, a
column-specifying command and a column address that are given just before
the per-page read or write command and the corresponding page address.

16. The method of claim 15, wherein when the page selection circuit is
given a per-page read command and a page address, the page selection
circuit performs control to simultaneously read data from a plurality of
memory cells separated from one another in a page indicated by the given
page address and to store the data in the page buffer, and when the page
selection circuit is given a per-page write command and a page address,
the page selection circuit performs control to write data stored in the
page buffer in a plurality of memory cells separated from one another in
a page indicated by the given page address.

17. The method of claim 15, wherein each of a plurality of memory cells
separated from one another in a page that are simultaneously selected by
the page selection circuit belong to different one among the memory
blocks.

18. The method of claim 15 further comprising supplying the row- and
column-specifying commands and the read and write commands input from
outside in a random input order to the block array or the page selection
circuit in the input order.

19. The method of claim 15, the semiconductor memory device comprises a
plurality of banks each having the block array, the page selection
circuit, and the page buffer, wherein the row- and column-specifying
commands are issued to all of the banks or some of the banks, and the
read and write commands are issued to a specific bank.

20. The method of claim 15, wherein each memory cell is an MRAM cell.

Description:

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priority
from the prior Japanese Patent Application No. 2011-118310 filed on May
26, 2011 and PCT application No. PCT/W2012/056290 filed on March 12,
2012, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

[0002] Embodiments of the present invention relate to a semiconductor
memory device provided with non-volatile and non-destructively readable
memory cells, a memory system, and an access method to a semiconductor
memory device.

BACKGROUND ART

[0003] An MRAM (Magnetoresistive Random Access Memory) has been developed
as a low-power consuming and high-speed accessible non-volatile memory.
However, in an MRAM, setting (writing) and detection (reading) of a
magnetization direction of an MTJ (Magnetic Tunnel Junction) element are
performed with a current. Therefore, if reading and writing are
simultaneously performed to a plurality of MTJ elements, circuit noises
may be increased, thereby causing simultaneous access to a plurality of
MTJ elements to be difficult.

[0004] LPDDR2 specification defined by JEDEC is known as standard
specification for low-power consuming memories. This specification aims
for optimization in accordance with non-volatility and non-destructive
reading that are features of DRAMs. Therefore, the state transition by
various commands is complex and hence it is not suitable to apply
non-volatile memories such as MRAMs with the specification as it is.

DISCLOSURE OF INVENTION

[0005] A semiconductor memory device according to an embodiment comprises:

[0006] a block array having an m number of memory blocks in a row
direction and an n number of memory blocks in a column direction (m being
an integer of 2 or more and n being an integer of 1 or more);

[0007] a
page selection circuit configured to select a row in the block array as a
page to be selected; and

[0008] a page buffer configured to store data to
be written in a page selected by the page selection circuit or data read
from the page,

[0009] wherein each of the memory blocks comprises:

[0010] a memory cell array having a plurality of memory cells;

[0011] a
row selection circuit configured to select a row of the memory cell
array; and

[0012] a column selection circuit configured to select a
column of the memory cell array,

[0013] wherein when a row-specifying
command and a row address are given, a group of memory cells of a
specific row corresponding to the given row address is selected for each
of the n number of memory blocks aligned in the column direction in the
block array,

[0014] when a column-specifying command and a column address
are given, a group of memory cells of a specific column corresponding to
the given column address is selected for each of the m number of memory
blocks aligned in the row direction in the block array, and

[0015] when
the page selection circuit is given a per-page read or write command and
the corresponding page address, the page selection circuit simultaneously
selects a plurality of memory cells separated from one another in a page
indicated by the given page address among a group of memory cells
selected by a row-specifying command, a row address, a column-specifying
command and a column address that are given just before the per-page read
or write command and the corresponding page address.

BRIEF DESCRIPTION OF DRAWINGS

[0016]FIG. 1 is a block diagram schematically showing the configuration
of a semiconductor memory device 1 according to an embodiment;

[0017]FIG. 2 is a view explaining an operation of a row selection circuit
8 in the case where a row address corresponding to a RAS command is
issued;

[0018]FIG. 3 is a view explaining an operation of a column selection
circuit 9 in the case where a column address corresponding to a CAS
command is issued;

[0019]FIG. 4 is a view explaining an operation of a page selection
circuit 3 in the case where a page address corresponding to a READ
command is issued;

[0020]FIG. 5 is a view explaining an operation of the page selection
circuit 3 in the case where a page address corresponding to a WRITE
command is issued;

[0021]FIG. 6 is a block diagram schematically showing the configuration
of an embodiment of a memory system provided with a semiconductor memory
device 1 having a bank memory configuration;

[0022]FIG. 7 is a view showing an example of address allocation in the
semiconductor memory device 1 of FIG. 6;

[0023] FIG. 8 is a state transition view of semiconductor memory devices 1
according to embodiments shown in FIGS. 1 and 6, respectively;

[0024]FIG. 9 is a view showing an example of a logical value of each
signal in inputting each command in a semiconductor memory device 1
according to an embodiment;

[0025] FIG. 10 is a timing chart showing an example of an operation timing
of a semiconductor memory device 1 according to an embodiment;

[0026] FIG. 11 is a timing chart showing another example of an operation
timing of a semiconductor memory device 1 according to an embodiment;

[0027]FIG. 12 is a timing chart showing another example of an operation
timing of a semiconductor memory device 1 according to an embodiment;

[0028] FIG. 13 is a timing chart showing another example of an operation
timing of a semiconductor memory device 1 according to an embodiment;

[0029] FIG. 14 is a timing chart showing another example of an operation
timing of a semiconductor memory device 1 according to an embodiment;

[0030]FIG. 15 is a timing chart showing another example of an operation
timing of a semiconductor memory device 1 according to an embodiment;

[0031] FIG. 16 is a timing chart showing another example of an operation
timing of a semiconductor memory device 1 according to an embodiment;

[0032]FIG. 17 is a timing chart showing another example of an operation
timing of a semiconductor memory device 1 according to an embodiment;

[0033] FIG. 18 is a timing chart showing another example of an operation
timing of a semiconductor memory device 1 according to an embodiment;

[0034]FIG. 19 is a timing chart showing another example of an operation
timing of a semiconductor memory device 1 according to an embodiment;

[0035] FIG. 20 is a timing chart showing another example of an operation
timing of a semiconductor memory device 1 according to an embodiment;

[0036]FIG. 21 is a timing chart showing another example of an operation
timing of a semiconductor memory device 1 according to an embodiment;

[0037]FIG. 22 is a timing chart showing another example of an operation
timing of a semiconductor memory device 1 according to an embodiment;

[0038]FIG. 23 is a timing chart showing another example of an operation
timing of a semiconductor memory device 1 according to an embodiment;

[0039]FIG. 24 is a timing chart showing another example of an operation
timing of a semiconductor memory device 1 according to an embodiment;

[0040]FIG. 25 is a timing chart showing another example of an operation
timing of a semiconductor memory device 1 according to an embodiment; and

[0041]FIG. 26 is a circuit diagram in the case of using an MRAM cell as a
memory cell in first and second embodiments.

BEST STATE FOR CARRYING OUT THE INVENTION

[0042] Hereinafter, embodiments will be explained with reference to the
drawings.

[0043]FIG. 1 is a block diagram schematically showing the configuration
of a semiconductor memory device 1 according to an embodiment. The
semiconductor memory device 1 of FIG. 1 is provided with a block array 2,
a page selection circuit 3, a page buffer 4, and a peripheral control
circuit 5.

[0044] The block array 2 has an m number of memory blocks 6 in a row
direction and an n number of memory blocks 6 in a column direction (m
being an integer of 2 or more and n being an integer of 1 nor more). Each
memory block 6 has a memory cell array 7 of a plurality of memory cells,
a row selection circuit 8 for selecting a row of the memory cell array 7,
and a column selection circuit 9 for selecting a column of the memory
cell array 7.

[0045] The page selection circuit 3 selects a specific page of the block
array 2. Here, a page indicates a specific row selected from among all
rows (all rows of the m number of memory cell arrays 7) in the block
array 2. The selected specific row includes a group of memory cells for
one row having the n number of memory cell array 7 in the column
direction.

[0046] The page buffer 4 stores data read from a group of memory cells of
the specific row described above or data to be written in the group of
memory cells of the specific row.

[0047] The peripheral control circuit 5 performs control to send various
commands, addresses, and data supplied from a processor or a controller
(both not shown) to the block array 2 and to send data read from a memory
cell to the processor or controller.

[0048] Commands to be supplied from the processor or controller to the
peripheral control circuit 5 include, for example, a RAS command, a CAS
command, a READ command, and a WRITE command.

[0049] The RAS command is a row-specifying command for selecting a
specific row for each of a plurality of memory cell arrays 7 aligned in
the row direction in the block array 2. A row address issued
corresponding to a RAS command is simultaneously input to row selection
circuits 8 of the memory blocks 6. Each row selection circuit 8 selects a
memory cell on the row address in the corresponding memory cell array 7.

[0050]FIG. 2 is a view explaining an operation of the row selection
circuit 8 in the case where a row address corresponding to a RAS command
is issued. A thick solid-line path in FIG. 2 indicates portions selected
by a RAS command and a row address. As shown in FIG. 2, when a RAS
command and a row address are issued, a plurality of memory cells on a
specific row corresponding to the row address are selected for each of
the n number of memory cell arrays 7 aligned in the column direction.

[0051] The CAS command is a column-specifying command for selecting a
specific column for each of a plurality of memory cell arrays 7 aligned
in the column direction in the block array 2. A column address issued
corresponding to a CAS command is simultaneously input to column
selection circuits 9 of the memory blocks 6. Each column selection
circuits 9 selects a memory cell on the column address in the
corresponding memory cell array 7.

[0052]FIG. 3 is a view explaining an operation of the column selection
circuit 9 in the case where a column address corresponding to a CAS
command is issued. A thick solid-line path in FIG. 3 indicates portions
selected by a CAS command and a column address. As shown in FIG. 3, when
a CAS command and a column address are issued, a plurality of memory
cells on a specific column corresponding to the column address are
selected for each of the m number of memory cell arrays aligned in the
row direction.

[0053] The READ command is a read command for reading data from a
plurality of memory cells that correspond to a page address in the block
array 2. A page address issued corresponding to a READ command is input
to the page selection circuit 3. The page selection circuit 3 selects
data at the page address in the block array 2. The selected data is
stored in the page buffer 4. The page address is an address for selecting
data in the n number of memory cell arrays 7 located on a specific row in
the block array 2 for each page described above. Since RAS and CAS
commands are issued before a READ command is issued, data of a plurality
of memory cells selected by the row selection circuit 8, the column
selection circuit 9, and the page selection circuit 3 are stored in the
page buffer 4.

[0054]FIG. 4 is a view explaining an operation of the page selection
circuit 3 in the case where a page address corresponding to a READ
command is issued. A thick line frame in FIG. 4 indicates a page selected
with a page address. Since RAS and CAS commands are issued before a READ
command is issued, data of a plurality of memory cells surrounded by
circles are read and stored in the page buffer 4. As described above,
memory cells to be simultaneously read are distributed to a plurality of
memory cell arrays.

[0055] The WRITE command is a write command for writing data in a
plurality of memory cells corresponding to a page address in the block
array 2. A page address issued corresponding to a WRITE command is input
to the page selection circuit 3. The page selection circuit 3 selects
data of a page address in the block array 2. The selected data is stored
in the page buffer 4. The page address is an address for selecting data
of the n number of memory cell arrays 7 located on a specific row in the
block array 2 for each page described above. Since RAS and CAS commands
are issued before a WRITE command is issued, data of the page buffer 4
are written in a plurality of memory cells selected by the row selection
circuit 8, the column selection circuit 9, and the page selection circuit
3.

[0056]FIG. 5 is a view explaining an operation of the page selection
circuit 3 in the case where a page address corresponding to a WRITE
command is issued. A thick line frame in the block array 2 of FIG. 5 is
selected with a page address. Since RAS and CAS commands are issued
before a WRITE command is issued, data of the page buffer 4 are written
in a plurality of memory cells surrounded by circles. As described above,
memory cells to be simultaneously written are distributed to a plurality
of memory cell arrays.

[0057] The semiconductor memory device 1 of this embodiment may have a
bank memory configuration or not. In the case of a bank memory
configuration, a region including the block array 2, the page selection
circuit 3, and the page buffer 4 in FIG. 1 is put into a bank, so that a
plurality of banks are provided. A semiconductor memory device 1 with a
bank memory configuration will be described later.

[0058] As described above, in the first embodiment, to the entire block
array 2, row selection and column selection are performed with a RAS
command and a CAS command, respectively, and thereafter, reading and
writing are performed per page with a READ command and a WRITE command.
Accordingly, reading and writing can be performed to a plurality of
memory cells at different locations and timings. Thus, even simultaneous
reading from or writing to a plurality of memory cells withstands circuit
noises. Therefore, even for memory cells, like MRAM cells, that require
current flow in reading or writing, simultaneous reading from or writing
to a plurality of memory cells becomes possible without increasing
circuit noises.

[0059] Moreover, as described later, this embodiment has a feature in
that, a RAS command, a CAS command, a READ command, and a WRITE command
can be issued in any order. Therefore, memory-cell reading and writing
control becomes easy, the internal configuration of the row selection
circuit 8, the column selection circuit 9, and the page selection circuit
3 becomes simple, and reading and writing can be done at high speed.

Second Embodiment

[0060] A semiconductor memory device 1 according to a second embodiment
has a feature of having a plurality of banks.

[0061]FIG. 6 is a block diagram schematically showing the configuration
of an embodiment of a memory system provided with a semiconductor memory
device 1 having a plurality of banks. The memory system of FIG. 6 is
provided with a semiconductor memory device 1 having eight banks b0 to b7
and a controller 11 that controls the semiconductor memory device 1.

[0062] The semiconductor memory device 1 of FIG. 6 has eight banks b0 to
b7, a CA buffer 12, and a DQ buffer 13. Each bank is configured in the
same manner as FIG. 1 to have a block array 2, a page selection circuit
3, and a page buffer 4. The block array 2 has the same internal
configuration as FIG. 1.

[0063] To the CA buffer 12, command address signals CA0 to CA9 for
identifying a command type, a clock enable signal CKE, a chip select
signal CS_N, and clock signals CK_t and CK_c are input from the
controller 11.

[0065] The semiconductor memory device 1 of FIG. 6 issues various commands
described above to a selected bank to perform similar operations to FIGS.
2 to 5.

[0066]FIG. 7 is a view showing an example of address allocation in the
semiconductor memory device 1 of FIG. 6.

[0067]FIG. 7 includes, as Items, a prefetch type Prefetch, the total bank
number Number of Banks, a Bank Address, and the number of I/O x8, x16 and
x32. Each of x8, x16 and x32 includes a Row Address, a Column Address, a
Page Address, and a Page Buffer Size.

[0068] In FIG. 7, information of each item described above is written for
each of semiconductor memory devices 1 having a memory capacity of 1
Gbits, 2 Gbits, 4 Gbits, 8 Gbits, 16 Gbits, and 32 Gbits.

[0069] Each item and value in FIG. 7 are just an example. The memory
capacity and the value of each item can take any information other than
those shown therein.

[0070] FIG. 8 is a state transition view of the semiconductor memory
devices 1 according to the first and second embodiments shown in FIGS. 1
and 6. When a power supply voltage is supplied, the semiconductor memory
device 1 changes into a power-on state. When a reset signal is input
during the power-on state, a specific rest process is performed, so that
the semiconductor memory device 1 changes into an Idle state.

[0071] When a RAS command is input during the Idle state, the
semiconductor memory device 1 changes into a RAS state. In the RAS state,
the semiconductor memory device 1 performs a row selection operation such
as shown in FIG. 2. When a CAS command is input during the Idle state,
the semiconductor memory device 1 changes into a CAS state. In the CAS
state, the semiconductor memory device 1 performs a column selection
operation such as shown in FIG. 3.

[0072] When a CAS command is input during the RAS state, the semiconductor
memory device 1 changes into the CAS state. When a RAS command is input
during the CAS state, the semiconductor memory device 1 changes into the
RAS state.

[0073] When a READ command is input during the RAS or CAS state, the
semiconductor memory device 1 changes into a READ state. In the READ
state, as shown in FIG. 4, data read from a plurality of memory cells per
page are stored in the page buffer 4. When a WRITE command is input
during the RAS or CAS state, the semiconductor memory device 1 changes
into a WRITE state. In the WRITE state, as shown in FIG. 5, data in the
page buffer 4 are written in a plurality of memory cells in a selected
page.

[0074] When a WRITE command is input during the READ state, the
semiconductor memory device 1 changes into the WRITE state. When a READ
command is input during the WRITE state, the semiconductor memory device
1 changes into the READ state.

[0075] When a specific time elapses after the semiconductor memory device
1 has changed into the RAS, CAS, READ, or WRITE state, the semiconductor
memory device 1 automatically changes into the Idle state.

[0076] As understood from the state transition view of FIG. 8, in this
embodiment, the semiconductor memory device 1 can change from any command
state into another command state in any order, so that state transition
by each command is very simple. Simple state transition means that the
row selection circuit 8, the column selection circuit 9, and the page
selection circuit 3 in the semiconductor memory devices 1 can have a
simple internal configuration and hence high-speed access to the memory
cells is possible. By contrast, in DRAMs, since a precharge operation is
required and due to other factors, state transition becomes very complex
and the internal configuration of circuits such as the row selection
circuit 8 becomes complex, which restricts high-speed access.

[0077]FIG. 9 is a view showing an example of a logical value of each
signal in inputting each command in the semiconductor memory device 1
according to this embodiment. In FIG. 9, there are two types for each of
RAS and CAS commands. One type is to apply a RAS or CAS command to a
specific bank. The other type is to apply a RAS or CAS command to all
banks.

[0078] In applying a RAS or CAS command to a specific bank, at the rising
timing of a clock signal CK_t, command address signals CA7 to CA9 specify
specific bank addresses BA0 to BA2, and command address signals CA5 and
CA6 specify bits R10 and R11 at the high-order bit side of a row address
or bits C10 and C11 at the high-order bit side of a column address.
Moreover, at the falling timing of the clock signal CK_t, command address
signals CA5 and CA6 specify bits R0 to R9 at the low-order bit side of
the row address or bits C0 to C9 at the low-order bit side of the column
address.

[0079] READ and WRITE commands are not applied to all banks but only to a
specific bank. At the rising timing of the clock signal CK_t, command
address signals CA7 to CA9 specify specific bank addresses BA0 to BA2 and
command address signals CA5 and CA6 specify bits P10 and P11 at the
high-order bit side of a page address. Moreover, at the falling timing of
the clock signal CK_t, command address signals CA5 and CA6 specify bits
PO to P9 at the low-order bit side of the page address.

[0080] FIGS. 10 to 25 are timing charts of the semiconductor memory device
1 according to this embodiment. FIGS. 10 to 14 show examples of a reading
operation to the same bank.

[0081] FIG. 10 shows an example in which a RAS command, a CAS command, and
a READ command are issued in order and, after three cycles since the READ
command has been issued, data strobe signals DQS_c and DQS_t become high
and low, respectively (read latency RL=3), with burst length BL=4 that
indicates a burst data length.

[0082] As understood from FIG. 10, while a RAS command is being issued,
bits of a row address at the high-order bit side thereof and bits of the
row address at the low-order bit side thereof are separately input in
order. Likewise, while a CAS command is being issued, bits of a column
address at the high-order bit side thereof and bits of the column address
at the low-order bit side thereof are separately input in order.
Likewise, while a READ command is being issued, bits of a page address at
the high-order bit side thereof and bits of the page address at the
low-order bit side thereof are separately input in order.

[0083] FIG. 11 shows an example of omitting issuance of a RAS command.
When issuance of a RAS command is omitted, a row address corresponding to
the immediately preceding RAS command is applied as it is. In the case of
FIG. 11, although a CAS command and a READ command are issued in order,
the operation timing after the READ command is issued is the same as FIG.
10.

[0084]FIG. 12 shows an example of omitting issuance of a CAS command.
When issuance of a CAS command is omitted, a column address corresponding
to an immediately preceding CAS command is applied as it is. In the case
of FIG. 12, although a RAS command and a READ command are issued in
order, the operation timing after the READ command is issued is the same
as FIG. 10.

[0085] FIG. 13 shows an example of omitting issuance of RAS and CAS
commands. When issuance of RAS and CAS commands is omitted, row and
column addresses at previous issuance of RAS and CAS commands are applied
as they are. In the case of FIG. 13, only the READ commands are issued,
with the interval between a READ command and the next READ command being
one cycle. Data DQ is read after four cycles since the READ command has
been issued. Therefore, when two READ commands are issued in secession,
burst data of eight pieces in total are read in secession.

[0086] FIG. 14 shows an example of omitting issuance of RAS and CAS
commands, and issuing a WRITE command after a READ command is issued.
Four pieces of burst data are read after four cycles since the READ
command has been issued. Thereafter, the WRITE command is issued around
time T6 and four pieces of burst data for writing are input at write
latency WL=1.

[0087] FIGS. 15 to 19 are timing charts of examples of burst writing to
the same bank. In FIG. 15, a RAS command, a CAS command, and a WRITE
command are issued in order, thereafter, four pieces of burst data are
input at a timing of being latched at a rising or falling edge of strobe
signals DQS_c and DQS_t.

[0088] FIG. 16 shows an example of omitting issuance of a RAS command and
issuing a CAS command and a WRITE command in order. When issuance of a
RAS command is omitted, a row address at previous issuance of a RAS
command is applied as it is.

[0089]FIG. 17 shows an example of omitting issuance of a CAS command and
issuing a RAS command and a WRITE command in order. When issuance of a
CAS command is omitted, a column address at previous issuance of a CAS
command is applied as it is.

[0090] FIG. 18 shows an example of omitting issuance of both of RAS and
CAS commands. When issuance of RAS and CAS commands is omitted, row and
column addresses at previous issuance of RAS and CAS commands are applied
as they are. In the case of FIG. 18, WRITE commands are only issued, with
the interval between a WRITE command and the next WRITE command being one
cycle. Four pieces of burst data each being to be written by a WRITE
command are input in succession.

[0091]FIG. 19 shows an example of omitting issuance of RAS and CAS
commands and issuing a READ command after a WRITE command. In this case,
four pieces of burst data for writing are input after a WRITE command is
issued, thereafter, a READ command is issued after a specific recovery
period, and thereafter, data strobe signals DQS_c and DQS_t vary after
three cycles.

[0092] FIGS. 20 to 22 are timing charts of examples of a burst reading
operation to a plurality of banks. FIG. 20 shows an example in which RAS
and CAS commands are issued in order for all banks, thereafter, a READ
command is issued to a bank A, and next, a READ command is issued to a
bank B. Burst data read in response to these two READ commands are output
in succession after time T6.

[0093]FIG. 21 shows an example in which, after a RAS command is issued to
all banks, CAS and READ commands are issued to a bank A in order, and
next, CAS and READ commands are issued to a bank B in order. The timing
of reading burst data in this case is the same as FIG. 20.

[0094] Contrary to FIG. 21, FIG. 22 shows an example in which, after a CAS
command is issued to all banks, RAS and READ commands are issued to a
bank A in order, and next, RAS and READ commands are issued to a bank B
in order. The timing of reading burst data in this case is the same as
FIGS. 20 and 21.

[0095] FIGS. 23 to 25 are timing charts of examples of a burst writing
operation to a plurality of banks. FIG. 23 shows an example in which RAS
and CAS commands are issued in order for all banks, thereafter, a WRITE
command is issued to a bank A, and next, a WRITE command is issued to a
bank B. Burst data to be written in response to these two WRITE commands
are input in succession after time T4.

[0096]FIG. 24 shows an example in which, after a RAS command is issued
for all banks, CAS and WRITE commands are issued to a bank A in order,
and next, CAS and WRITE commands are issued to a bank B in order. In this
case, the timing at which burst data to be written are input is the same
as FIG. 23.

[0097] Contrary to FIG. 24, FIG. 25 shows an example in which, after a CAS
command is issued for all banks, RAS and WRITE commands are issued to a
bank A in order, and next, RAS and WRITE commands are issued to a bank B
in order. In this case, the timing at which burst data to be written are
input is the same as FIGS. 23 and 24.

[0098] As described above, in this embodiment, when the semiconductor
memory device 1 has a plurality of banks, at least either one of RAS and
CAS commands may be issued for all banks or a RAS or CAS command may be
issued for each bank. Therefore, as shown in FIGS. 10 to 25, for all or
some banks, reading and writing to a plurality of memory cells can be
performed per page after row and column selection for each block array 2.

Other Embodiments

[0099] For the memory cells in the semiconductor memory devices 1 in the
first and second embodiments, there is no limitation on the actual types
as far as the memory cells are non-volatile and non-destructively
readable. Several types of non-volatile and non-destructively readable
memories, such as, MRAM, PRAM (Phase Change RAM), SPRAM (Spin-Transfer
Torque RAM), and ReRAM (Resistance RAM) are applicable.

[0100]FIG. 26 is a circuit diagram in the case of using an MRAM cell as
the memory cells in the first and second embodiments. FIG. 26 shows two
memory cells adjacent to each other. Each memory cell has one transistor
Q1 and one MTJ element 21. A terminal of the MTJ element 21 is connected
to a terminal of a current path of the transistor Q1. The other terminal
of the current path of the transistor Q1 is connected to a first bit line
and to a terminal of a transistor Q1 in the adjacent memory cell. The
gate of the transistor Q1 is connected to a word line WL1. The other
terminal of the MTJ element 21 is connected to a bit line BL2.

[0101] The MTJ element 21 has a structure in which an insulation film is
inserted between a lower fixed layer and an upper fixed layer, both
layers being a ferromagnetic film. In writing, a current is flown to the
MTJ element 21 to change the magnetization direction of the upper fixed
layer. The resistance value of the MTJ element 21 varies depending on the
magnetization direction. In reading, the magnetization direction of the
upper fixed layer is detected according to the resistance value of the
MTJ element 21.

[0102] When the block array 2 is fabricated with MRAM cells such as shown
in FIG. 26, high-speed writing and reading, and higher integration are
possible. In order to perform writing or reading to an MRAM cell, it is
required to make current flow to the MTJ element 21. Therefore, circuit
noises may be generated if simultaneous access is made to a plurality of
MRAM cells. In contrast, in the first and second embodiments described
above, reading and writing are performed to a plurality of memory cells
at different locations and timings, so that generation of circuit noises
can be restricted.

[0103] The present invention is not limited to the embodiments described
above but includes various modifications conceivable by those skilled in
the art. The effects of the present invention are also not limited to
those described above. Namely, various additions, modifications and
partial omissions may be made without departing from the conceptual idea
and gist of present invention derived from those defined in the
accompanying claims and their equivalents.