Universities and other institutions of higher learning play a key role in developing our next generation of semiconductor technologies. Along with the theory of semiconductor technology, our next generation of scientists and engineers must learn about the practical methods used to design and manufacture the latest generation of semiconductor products. Recently, Coventor’s predictive, 3D process modeling platform (SEMulator3D®) has been widely adopted by the commercial semiconductor industry to facilitate process technology innovation and reduce the time and cost of silicon, fab-based learning. As SEMulator3D becomes a mainstream EDA solution for our industry partners, it is only natural that the product should find its way into leading universities to foster semiconductor education, especially in the context of teaching students about advanced 3D process technologies. With this vision in mind, I am part of a team at Coventor that is responsible for initiating university programs and collaborating with our university partners to utilize this powerful platform for use in research and teaching programs. Today, I wanted to share some thoughts about why tools like SEMulator3D should be deployed in a university setting.

Undergraduate and graduate-level semiconductor courses include classes on the principles of semiconductor devices, advanced VLSI devices, fundamentals of semiconductor processing and many more subject areas. These courses cover the fundamental principles of how solid-state devices operate and how they are fabricated. SEMulator3D is a great companion tool for these semiconductor theory courses, since the 3D predictive process models developed in SEMulator3D can demonstrate first principle theories of semiconductor processing in a highly-interactive and visual manner.

Perhaps more importantly, the SEMulator3D platform can be very useful in laboratory courses where students actually fabricate integrated circuits and MEMS devices. These laboratory courses typically involve students physically fabricating a device in a cleanroom, starting with a bare silicon wafer, followed by various process steps to build a finished semiconductor device. SEMulator3D can be used in this setting to help students “virtually” understand the effect of changing a process step in their laboratory device, before committing the time and cost to an actual wafer run.

While these laboratory courses are highly instructive, students must sometimes fabricate their test devices with older process technology that is available in many university cleanrooms. Students can’t always access the latest commercial semiconductor processing equipment, due to the budget constraints at academic cleanroom facilities. Using SEMulator3D, students can model a step-by-step process flow and virtually fabricate devices using the latest, state-of-the-art process technology. They can “fabricate” virtual versions of highly-advanced devices,such as the 14nm FinFETs that are shipped in the latest iPhones. Using this example, students might even make changes in critical process modules to explore the evolution of a FinFET device into a more advanced 3D structure such as a gate-all-around nanowire structure, considered one of the top device candidates at the 7nm technology node. Students can experiment with the latest semiconductor process technologies, without the need to access a multi-billion dollar fabrication facility. This provides students with the ability to learn about the latest commercial technologies and quickly integrate this knowledge into their future jobs in the commercial sector.

Moreover, SEMulator3D can be used in university research to expand the boundaries of current semiconductor knowledge and explore new process integration schemes and device designs. At Coventor, we are constantly adding new features that address the needs of cutting-edge research. For example, we introduced a directed self-assembly (DSA) process modeling module in SEMulator3D earlier this year, so researchers could explore process integration options based upon this advanced patterning technique. If you are interested in directed self-assembly research, I would encourage you to read a prior blog from my colleague Matt Kamon (see: https://www.coventor.com/blog/will-directed-self-assembly-pattern-14nm-dram/). Coventor personnel have also used SEMulator3D to perform research on line edge roughness (LER) and line width roughness (LWR) in lithographic processing, using a new line-edge roughness processing module in SEMulator3D. If you are interested in this area of research, I would encourage you to refer to my previous blog for additional details (see: https://www.coventor.com/blog/advanced-lithography-and-structural-variation-modeling-using-SEMulator3d/). Coventor’s research in DSA and LER/LWR using SEMulator3D has led to publications in leading semiconductor conference proceedings, such as the SPIE Advanced Lithography conference, SISPAD and other respected conferences.

SEMulator3D can also be used to facilitate experiments conducted in university cleanrooms. These experiments might involve proper calibration of process models based upon existing hardware data, such as inline measurement results, AFM, SEM/TEM images and other measurement data. Once the process has been calibrated, researchers can verify their device designs through virtual fabrication without the need to order mask sets. What’s more, 3D structures fabricated using SEMulator3D can be subsequently exported to a mesh structure suitable for use in finite-element analysis tools to simulate electrical, mechanical, or thermal behaviors of a proposed device.

A number of leading universities, such as MIT, Stanford, UC Berkeley and others have now recognized the value of adopting the SEMulator3D virtual fabrication platform in semiconductor research and education. We are expanding our university program worldwide and I am excited to collaborate with our university partners in coming up with even more innovative uses for virtual fabrication using SEMulator3D. Stay tuned.