DCVALID is a program to check validity of
Duration Calculus
Formulae. It can be used as a tool to visualize
DC specification and to check for their consistency. It can
also be used in conjunction with other tools to model check DC
properties of systems. Currently, systems written in SMV, Verilog VIS), ESTEREL
and
SPIN
are supported.

DCVALID is based on an automata
theoretic decision procedure for Quantified
Discrete-time Duration Calculus (QDDC). For every formula D, we
construct
a finite state automaton A(D) precisely accepting the finite state
sequences
satisfying D. The automaton can be used to find models and counter
models,
or as a synchronous observer (or monitor) for model checking. DCVALID
makes
use of MONA which provides efficient multi-terminal BDD based
representation
of automata and has implemented algorithms for operations
on
automata such as product, projection, determinisation and minimisation.
See Technical
Report for details.

Click for a quick
overview of DCVALID. The user
manual gives syntax, semantics and usage.
Click for a paper on QDDC decidability and its implmentation in
DCVALID.

DCVALID was designed and programmed
by Paritosh
K. Pandya at Tata Institute of Fundamental Research, Mumbai,
India.
Some recent extensions were carried out under the aegis of UNU/IIST
offshore R&D project Semantics and Verification of Real-time
programs
using Duration Calculus.

Acknowledgements DCVALID1.4
makes use of the validity checker
for WS1S formulae, MONA 1.4,
developed
within the BRICS project at Aarhus University, Denmark. We are grateful
to its designers for permission to use and distribute it with
DCVALID.
The compiler construction system GENTLE
was used in the implementation.
For model checking, CTLDC makes use of existing model checkers SMV,
VIS, Xeve.

Current Stable Version

DCVALID1.3 allows checking
validity of Quantified Discrete time Duration
Calculus (QDDC) formulae. It also provides support for checking dense
time
DC formulae without lengths or durations. DCVALID1.3 includes:

DCEST
which allows modelchecking of QDDC formulae against ESTEREL programs
using
the Esterel verification tools. See the documentation.

QDDC allows formulation of safety
and bounded-liveness properties of systems.
Support for more general class liveness and branching properties is
provided
using logic CTL[DC] in the Version 1.4 which also allows model checking
SMV, Verilog and Esterel designs.

Installation and Usage

Installation notes are in README
file contained in the distribution.
The documentation is contained in
file dcvalid.txt.
Several example specifications
are including the mine pump, delay insensitive
oscillator and Fischer's mutual exclusion protocol are supplied with
the
distribution.

R. Kazmiakin, P.K. Pandya, M. Pistore, Modelling and Analysis of
Time Related Properties in Web Service Compositions, To appean in
Proc. First International
Workshop on Engineering Service Compositions (WESC 2005),
Affiliated with ICSOC 2005, Amsterdam, (2005)