Most design for testability techniques intrude (modify) the circuitry for ease of testing. The intrusion maybe in the form of scan, built in self test (BIST), test point insertion, etc. However, the ease in testing is achieved at the cost of increased silicon area requirements and performance penalties. In this paper, we develop methods of identifying cost effective intermediate solutions. An algorithm that ranks memory elements is developed. The ranking is used to select the intermediate solution which can be classified as partial scan in the scan design methodology or partial BIST for BIST schemes. A statistical analysis of the ranking mechanism is developed to illustrate the effectiveness of our approach on very large sequential circuits. Experimental results on the use of the presented approach on sequential benchmark circuits are also presented.