Micron Technology's vision is to transform how the world uses information to enrich life and our commitment to people, innovation, tenacity, collaboration, and customer focus allows us to fulfill our mission to be a global leader in memory and storage solutions. This means conducting business with integrity, accountability, and professionalism while supporting our global community.

The TD ESD/Latch-up Design and Characterization team at Micron Technology, Inc. is seeking an experienced ESD Engineer with emphasis conducting ESD/LUP research and experiments to investigate how to design-in the best ESD and latch-up circuit solutions for new memory designs.

An MS/PhD in Electrical Engineering, Microelectronics, or related discipline. BS + minimum of 5 years of experience will also be considered. An ESD Certified Professional Design Certification from the ESD Association would be strongly desired, but is not absolutely required.

About Us:

As the leader in innovative memory solutions, Micron is helping the world make sense of data by delivering technology that is transforming how the world uses information. Through our global brands - Micron, Crucial, and Ballistix - we offer the industry's broadest portfolio. We are the only company manufacturing today's major memory and storage technologies: DRAM, NAND, NOR, and 3D XPoint memory. Our solutions are purpose built to leverage the value of data to unlock financial insights, accelrate scientific breakthroughs and enhance communication around the world.

We recruit, hire, train, promote, discipline and provide other conditions of employment without regard to a person's race, color, religion, sex, age, national origin, disability, sexual orientation, gender identity and expression, pregnancy, veteran’s status, or other classifications protected under law. This includes providing reasonable accommodation for team members' disabilities or religious beliefs and practices.

Each manager, supervisor and team member is responsible for carrying out this policy. The EEO Administrator in Human Resources is responsible for administration of this policy. The administrator will monitor compliance and is available to answer any questions on EEO matters.

1. Background: The NASA Ames Research Center (ARC) SunSat group supports a variety ofinstruments (e.g. see http://www.mdpi.com/2072-4292/5/8/3872) that perform opticalmeasurements of tropospheric aerosols and trace gasses when installed in NASA researchaircraft [1]. The ARC SunSat team is funded to maintain existing instruments (2STAR, 3STAR,4STAR) and develop the next generation instrument (5STAR). This set of instruments(collectively termed nSTAR) depends on precision radiometer and spectrometer detectors andinclude a variety of transmissive, diffractive, and diffusive optical elements, including fiber opticlight path technology. Robotics technology is required for sun tracking and sky scanningfunctionality both on the ground and in flight. During flight missions the detector head isexposed to the free stream environmental conditions up into the stratosphere.

2. Job Description: An instrumentation engineer is required to support the development of thenSTAR instruments and various supporting instrument apparatus. Upper-division majorspursuing degrees in electrical and mechanical engineering and recent graduates that are USCitizens are encouraged to apply for this contractor position. Specific skills include the ability tocreate, read and interpret engineering design drawings and to create the wiring and electronicprinted circuit board components, to NASA aircraft airworthiness standards. Additionally, fieldengineering expertise is required to support existing instruments that are deployed in a series offlight experiments through 2018. If not experienced, willingness to learn and adhere to NASAaircraft airworthiness, assembly, ESD, field operations, QA, safety and other standards arerequired.

3. Schedule: Work may be done independently as the individual's schedule permits. Off-hoursmight actually be preferred for CAD license availability. This position need not be exclusive ofother employment or educational commitments. A desk at the NASA ARC (Mountain View,CA) in building N245 will be provided. A short meeting will be scheduled every week to discussdesign concepts, evaluate approach, and assess progress. Project schedules are expected torequire approximately 10 hours per week beginning in October 1, 2018 and extending throughSeptember 30, 2019. More intensive work schedules up to 28 hours per week during schoolbreaks would be desirable.

5. Performance Standards: Milestones of accomplishment will include design reviews atintermediate and final stages. The engineer will coordinate fabrication of mechanical parts andwiring harness components. The primary success metric will be the successful fabrication of therequired hardware.

Contact:resumes@baeri.org

Position: ESD Contract Auditor for 3rd Party Certification

Location: Global (Asia/Pacific Region Preferred)

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Summary of Position:

DEKRA is seeking an ANSI/ESD S20.20 auditor on a subcontractor basis to support their growing international client base. The position is remote location, from home office. .

Corporate Process Reliability – Electrical Engineer

Job Description:

The Corporate Process Reliability group at Intersil Corporation is looking for a new college graduate in Electrical Engineering with educational experience in analog circuits and semiconductor devices. The chosen candidate will learn three key functions within the Technology Development Group: ESD design and characterization, wearout structure design and characterization, and device layout and modeling. The chosen candidate will support these three functions through design and electrical characterization of test structures and circuits blocks.

Location: Palm Bay, FL

Responsibilities:

1) ESD Development and Testing

ESD test chip design and layout

TLP and vf-TLP setup and testing

HBM/MM ESD testing

2) Electrical Characterization

Leakage and Capacitance Characterization of ESD

Burn-in and radiation effect testing

Programming and automation of lab based instruments and testers

3) Test chip schematic and layout design

4) Compact modeling of semiconductor devices

Skill Set:

1) Bachelors/Masters in EE with emphasis in analog circuits and semiconductor devices

Due to the geometry scaling and specific lithography features, implementing high-voltage (HV) I/O transistors may become a very challenging task in advanced gate-all-around vertically stacked horizontal nanowires (NWs) technologies. Using core transistors for HV I/O circuit design could be an alternative design solution without additional development cost of HV I/O transistors. In this I/O design exploration, the functional performance of I/O circuit will be the first challenge because of the complicated circuit architecture and transistor/circuit reliability concerns. The reliability concerns are not only related to FEOL device reliability, such as TDDB and HC degradation, but also related to Electrostatic discharge (ESD). The later one has become a major reliability concern in advanced CMOS technology and ESD robustness is always a key parameter in I/O circuit specifications. In fact, the technology roadmap has set the stage of the ESD challenges. There are two main technology options in CMOS scaling roadmap. The first one is the device architecture moving from FinFET to GAA NW. The second is the high mobility materials, such as SiGe, and Ge, integrated as the channel of the transistors in either FinFET or GAA NW. However, the technology options and complicated circuit architecture often result in significant impact on ESD robustness of the protection devices.

FEOL device reliability in static/quasi-static stress conditions has been investigated several advanced technologies [1-3]. However, in real circuit applications, the transient overshoot could bring severe overvoltage stresses which can significantly impact transistor performance and finally induce circuit performance degradation. This issue will be more pronounced in HV I/O circuit design with only core transistors. On the other hand, ESD reliability has been investigated in Si FinFET technology [4-9] and Si GAA NW [10] technology. It is strongly impacted by the process options and the specific device architecture [4-12]. Then, ESD characterizations of planar SiGe and FinFET SiGe technologies have been presented in our previous works [11, 12]. The SiGe quantum well channel plays an dominated role in ESD performance and the Si/SiGe heterostructure junction brings an isolation effect on carrier density and current distribution. In addition, the ESD results of the planar Ge technology and the FinFET Ge technology with the strain process option have been also shown in our previous works [13,14]. The non-destructive differential resistance lowering (DRL) was reported in Ge diodes because thermally induced carrier generation in Ge. The Ge/SiGe heterostructure junction not only induces the electrical isolation effect, but also bring the thermal isolation due to the thermal property difference in different materials. In a nutshell, the reliability challenges in I/O circuits of advanced CMOS technologies are directly from the interaction between specific process options, device architectures, the material properties, and even the circuit applications.

In this PhD program, the main tasks will focus on ESD/FEOL reliability of I/O circuit applications in advanced FinFET and GAA NW technologies. Based on the past learning, we will start the exploration of the reliability influenced by specific circuit architectures, materials and the related process and device options, such as the nano-sheet architecture and the vertical GAA NW structure.

Electrostatics Engineer

Job Location: Rochester, NY

Job Description

Provide Electrostatic Discharge (ESD) technical expertise in support of multiple commercial and Aerospace programs. Coordinate Electrostatic Laboratory, and actively engage in all aspects of Electrostatic testing and analysis of materials, electronic hardware and facilities, as well as personnel training and safe practices. Create plans for and provide all necessary ESD control and monitoring of high reliability hardware programs and facilities. Perform periodic audits and quarterly facility inspections

Required Experience:

B.S. degree with 3+ years of experience or equivalent

Desired Experience

Degree in Electrical Engineering or Applied Physics

Expertise in all aspects of hardware protection from ESD, including facility requirements, personnel training programs and triboelectric charging concepts

Ability to work independently as well as in functional team and project team environments

Good verbal and written communication skills

Comfortable making presentations and delivering training sessions

Able to handle multiple tasks and changing priorities to meet challenging schedules

Please be aware that many of our positions require a security clearance, or the ability to obtain one. Security clearances may only be granted to U.S. citizens. In addition, applicants who accept a conditional offer of employment may be subject to government security investigation(s) and must meet eligibility requirements for access to classified information.

ESTATEC USANATIONAL SALES MANAGER

Five years of previous experience as:• Sales or Regional Sales Manager• B2B Sales• Electronics/ESD sales and its dealer network• Knowledge of Electronics Industry•Knowledge of General Management Processes

Main functions: • Assisting the ESTATEC´S General Manager and Corporative CEO to develop the company´s introduction strategy to American market.• Implementing that strategy with distributors.• Planning the annual sales budget.• Developing new customers according to the annual sales budget.• Following up Top customers.• Provide the attraction strategy for new customers• Monitor the business strategy with Distributors Company.• Solve customer complaints.• Monitoring Billing and Collection• Coordination of delivery and goods receipt.• Supervision of warehouse operation and best practices• Administration of the whole company resources.• Resolve customer complaints about service and sales• Solve products and service problems