Thethe L3Miss and the ArchLLCRef are mapped to the same address and L3UnsharedHit/ArchLLCMissare both mapped to a different address. This is done to have the same class namefor objects storing event counts (*CounterState) on independently of the processor architecture and simultaneously save space by reusing the memory. The functions that compute cache metrics are using the ArchLLCRef/ArchLLCMiss names on Atom. In my opiniona different solution withseparate custom implementation classes for each architecture would add more complexity and explode the code size (many architectures have just a small differences that are easy to handle without a code bloat).

Thank you for your correcting.The result that LLC_Miss/LLC_Ref is easy to understand. LLC_Miss/LLC_Ref means LLC miss ratio.The perfevtsel0 is setting LLC_Reference event, while store value which read from pcm0 to cL3Miss, although it mapped to ArchLLCRef field. I'm really puzzled for this.Is there any meaning that put L3Miss and ArchLLCRef to the same union, why not put L3Miss and ArchLLCMiss to the same union?