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Alpha Processor architecture designed by Digital Equipment Corporation (DEC) –Purchased by Compaq –Purchased by HP The alpha is a 64-bit RISC processor similar to quite similar to MIPS The alpha is also dead  The alpha processor handbook is a superb piece of documentation

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Alpha “Alpha AXP is a 64-bit load/store RISC architecture that is designed with particular emphasis on the three elements that most affect performance: clock speed, multiple instruction issue, and multiple processors.” The first implementation issues 2 instructions per cycle.

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Alpha No divide instruction –Compiler must provide divide routines All memory accesses must be on a 64-bit word aligned boundary –Tedious when all you want is a single byte. –BWX extensions added in a later revision

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SPARC Designed at the same time as the MIPS –MIPS was a Stanford project SPARC descended from the RISC project at Berkeley –Scalable Processor ARChitecture –was more successful than the MIPS project. –MIPS (and other processors like it) are known as RISC processors.

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SPARC Concept of register windows –processor has up to 128 registers 32 are visible at any one time 8 global –8 local to current procedure Store temporary variables, intermediate working –16 shared with adjacent procedures Used to pass parameters and return values between functions

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Intel i386 registers are not general purpose –instructions expect their operands in specific registers destination can be either a memory location or a register complex instruction formats –somewhat restrictive too –in arithmetic instructions, the destination has to match one of the sources.