Design of Modified Shannon Based Full Adder Cell Using PTL Logic for Low Power Applications

The proposed full adder cell for low power applications has been implemented using Shannon decomposition based technique for sum and carries operation. By using the Shannon's theorem the transistor count has decreased thereby the total chip area gets minimized; hence the power also gets reduced to a considerable amount. The designs are simulated using SPICE tool which results in 25.6% improvement in power dissipation and 20% improvement in transistor count for the Modified Shannon based full adder cell when compared with MCIT based full adder cell.