SNUG 2016 Custom Compiler Lunch 'n' Learn Videolog

On March 31, 2016, Synopsys hosted a Custom Compiler Lunch ‘n’ Learn at SNUG Silicon Valley. At this event, attendees heard industry leaders from AMD, STMicroelectronics and Synopsys’ IP Group share their experiences using the new Custom Compiler visually-assisted automation to meet the challenges of FinFET custom design, and discuss how it improves their custom design productivity.

Guest Speakers:

Antun Domic

Exec. VP and GM, Design Group, Synopsys

Event Emcee

Antun Domic serves as executive vice president and general manager of the Design Group at Synopsys, Inc., where he is responsible for leading the development of the company’s implementation and analog/mixed-signal product lines. Prior to joining Synopsys in 1997, he worked at Cadence Design Systems; at the Microprocessor Group of Digital Equipment Corp., and at the Massachusetts Institute of Technology (MIT) Lincoln Laboratories. Antun earned a BS degree from the University of Chile in Santiago, and a PhD in Mathematics from MIT.

Eric Picollet

Analog and RF Design Flow Team Manager, STMicroelectronics

STMicroelectronics Adopts Custom Compiler for 28-nm FD-SOI Design

Eric Picollet is an Analog and RF Design Flow Team Manager at STMicroelectronics in Crolles where he collaborates with EDA vendors on analog and RF design flows. Previously, Eric led the Design Verification Flow & Methodology and Passive Devices Modeling teams at ST. He has experience developing software for library characterization, and as a software developer for telecom. Eric earned his PhD in Applied Mathematics and Mechanics from the Ecole Centrale in Paris.

Marc Tareila

Sr. Staff Mask Designer, AMD

Custom Compiler Bring-up at AMD

Marc Tareila is a Senior Staff Mask Designer at AMD tasked with improving the productivity of the global custom layout organization. Prior to AMD, he worked at Bell Labs, Digital Equipment Corporation, and Intel. Marc’s has spent many years in the custom IC design field, where his focus has included full-custom mask layout design, methodology development, physical verification strategies, CAD tool bring-up, and CAD tool development.

Bob Lefferts

Group Director, Mixed-Signal IP, Synopsys

Addressing FinFET IP Layout Challenges with Custom Compiler

Bob Lefferts joined Synopsys in 2004 and led the R&D team that developed Synopsys’ first PCI Express PHY. He is currently the Group Director responsible for all foundry downloads, deploying a unified design flow, managing the compute resources for custom and memory design, and developing common ESD libraries for Synopsys’ Solutions Group. As the liaison between the Solutions Group and the Design Group’s custom design R&D team, Bob is focused on enabling all FinFET technologies from 16nm to below 10nm, and improving layout performance across the organization. Bob earned his PhD from Stanford University in Semiconductor Device Physics.