Abstract

3D integration is a promising advanced manufacturing process offering a variety
of new hardware security protection opportunities. This paper presents a way of
securing 3D ICs using Hamiltonian paths as hardware integrity verification
sensors. As 3D integration consists in the stacking of many metal layers, one
can consider surrounding a security-sensitive circuit part by a wire cage.
After exploring and comparing different cage construction strategies (and
reporting preliminary implementation results on silicon), we introduce
a "hardware canary". The canary is a spatially distributed chain of functions
Fi positioned at the vertices of a 3D cage surrounding a protected circuit.
A correct answer (Fn ∘ … ∘ F1)(m) to a challenge m attests the canary's
integrity.