AMD’s upcoming Picasso APU was recently spotted over at user benchmark and indicates that the company is getting ready to update their Raven Ridge lineup with the new family of APUs. Matisse and Picasso APUs had already been spotted in a leak a while back and this is something that we had been expecting from AMD for quite some time now. The interesting thing is that while the original slides had suggested at Picasso just being a refresh of Raven Ridge, we have been hearing rumors of something a bit more interesting.

AMD Radeon Picasso APU surfaces in benchmark database

The primary difference between the old leaks and the rumors circulating right now is the fact that unlike before Picasso is being slated as a 12nm more power efficient version of the Raven Ridge architecture (in other words, Zen+). This is in sharp contrast to simply being a Raven Ridge refresh on the same node with more optimized architecture and better binning. Picasso APUs just became their very own line of products if this is actually the case.

Unfortunately, the benchmark in question does not provide any numbers and any further details. Another important difference we are hearing is that the Picasso APU will be fabricated in GlobalFoundries on the 12nm process. Once again, keep in mind that this rumor directly contradicts the slides we have seen before – which put Picasso simply as a plain old refresh of Raven Ridge on the same node without any of the interesting stuff (12nm, Zen+ etc). That you should take this with a grain of salt goes without saying.

What we have heard about AMD Starship, Matisse and Picasso so far

The AMD Matisse processor is basically the codename for Zen2, which is thought to be ready sometime in late 2018. This effectively means that if we see further delays, it could very well be pushed into the first half of 2019. In any case, the Zen2 architecture is going to be Spectre 1 hardened and will offer significantly increased IPC, clock and gaming performance over Zen 1. From what we know so far, Matisse is the codename for the desktop variants of Zen (ie Ryzen) that will be succeeding the pioneering generation. Matisse will be based on the 7nm node and work on the AM4 socket.

AMD Starship, on the other hand, is also based on the 7nm process and Zen2 architecture and will be a server CPU to go against Intel’s Xeon Phi series. Considering the fact that Starship will be based on the 7nm process not only will it be more economically viable (in terms of cost effectiveness and $ per transistor) than the 14nm implementation of Zen but it will also be much more power efficient.

If AMD continues its value philosophy forward with Starship, then it can eventually go on to pose a significant challenge to Intel Xeon and Xeon Phi chips. The Xeon Phi co-processors will be the only offerings from Intel which will outstrip Starship in terms of the raw core count. As is usually the case with chips from the blue giant, however, they are very pricey and when it comes down to it, the use cases that these chips are targeting can be achieved just as easily by employing more than one processor as long as it is cost and power effective.

As is usually the case with such large processors, there will be smaller versions of the same (yield theory dictates that) and according to the source the TDP should vary between 35W and 180W for the entire range of servers. It is also not clear at this point whether AMD will be using the Zen architecture for the Starship processor or whether it will be a new revision.

One thing is clear though, the 2018 time frame is probably a best-case scenario. As the process node is shrinking in size – it is getting harder and harder to beat physics. If the 7nm FinFET process is anything like past nodes, it will be based on a 10nm backbone, and EUV lithography (which is technically good till 5nm) should be able to take us that far. Even then, late 2018 is the earliest we can expect any working x86 processor on the 7nm node to materialize, otherwise, we are looking at the same 2019 estimates for 7nm chips.