Toshiba Corporation today announced the development of a high power gain transistor using a CMOS compatible process. The transistor efficiently reduces power consumption in high frequency RF/analog front-end application. Details will be presented on June 12 at the 2013 Symposia on VLSI Technology and Circuits, held in Kyoto, Japan, June 11-14, 2013.

Rapid growth in wireless and mobile devices, including smart phones and tablets, is driving demand for RF/Analog circuits offering low-power consumption and high-performance. However, it is difficult to apply the advanced device and process technologies widely used in digital circuitry to RF/Analog circuits, as transistor scaling results in noise and deterioration in energy gain efficiency.

Toshiba has addressed this problem with a novel device structure using two different materials as the gate electrode of a single MOSFET and a process integration scheme that employs a widely used common semiconductor manufacturing method. This approach has achieved nanometer level gate length control.

Experimental results with the transistor have secured significantly lower power consumption without any slow down in operation speed.

The distinctive characteristic of the device structure is a thin oxide barrier film between the two materials, the n-type Si and p-type Si in the gate electrode, which suppresses impurity inter-diffusion. A high electric field under the gate electrode region can be achieved, enhancing amplifier efficiency. A different gate oxide film thickness is implemented with different gate electrode materials. This structure achieves a well-controlled device property in saturation mode even in low operation voltage.

The new device fabrication process is also applicable to the high-permittivity (high-k) gate insulator used in advanced digital LSI manufacturing.

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