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Abstract:

A quarter-gap p-type field effect transistor (PFET) formed by gate-last
fabrication includes a gate stack formed on a silicon substrate, the gate
stack including: a high-k dielectric layer located on the silicon
substrate; and a gate metal layer located over the high-k dielectric
layer, the gate metal layer including titanium nitride and having a
thickness of about 20 angstroms; and a metal contact formed over the gate
stack. A quarter-gap n-type field effect transistor (NFET) formed by
gate-last fabrication includes a gate stack formed on a silicon
substrate, the gate stack including: a high-k dielectric layer located on
the silicon substrate; and a first gate metal layer located over the
high-k dielectric layer, the first gate metal layer including titanium
nitride; and a metal contact formed over the gate stack.

Claims:

1. A quarter-gap p-type field effect transistor (PFET) formed by
gate-last fabrication, the quarter-gap PFET comprising: a gate stack
formed on a silicon substrate, the gate stack comprising: a high-k
dielectric layer located on the silicon substrate; and a gate metal layer
located over the high-k dielectric layer, the gate metal layer comprising
titanium nitride and having a thickness of about 20 angstroms; and a
metal contact formed over the gate stack.

2. The quarter-gap PFET of claim 1, wherein the high-k dielectric layer
comprises hafnium oxide, and the metal contact includes one of aluminum
and tungsten.

3. A quarter-gap n-type field effect transistor (NFET) formed by
gate-last fabrication, the quarter-gap NFET comprising: a gate stack
formed on a silicon substrate, the gate stack comprising: a high-k
dielectric layer located on the silicon substrate; and a first gate metal
layer located over the high-k dielectric layer, the first gate metal
layer comprising titanium nitride; and a metal contact formed over the
gate stack.

4. The quarter-gap NFET of claim 3, wherein the high-k dielectric layer
comprises hafnium oxide, and the metal contact comprises one of aluminum
and tungsten.

5. The quarter-gap NFET of claim 3, wherein the first gate metal layer
has a thickness of about 35 angstroms.

6. The quarter-gap NFET of claim 3, wherein the gate stack further
comprises a threshold voltage tuning layer located between the high-k
dielectric layer and the first gate metal layer, the threshold voltage
tuning layer comprising a layer of lanthanum having a thickness from
about 4 angstroms to about 100 angstroms, and wherein the first gate
metal layer has a thickness of about 20 angstroms.

7. The quarter-gap NFET of claim 3, wherein the gate stack further
comprises an oxygen barrier layer located over the first gate metal
layer, the oxygen barrier layer including tantalum nitride (TaN) formed
by atomic layer deposition (ALD), and a second gate metal layer located
over the oxygen barrier layer, wherein the first gate metal layer has a
thickness of about 20 angstroms, and the second gate metal layer has a
thickness from about 35 angstroms to about 100 angstroms.

Description:

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is a divisional of U.S. application Ser. No.
12/816,605 (Ando et al.), filed on Jun. 16, 2010 the contents of which
are incorporated herein by reference in their entirety.

FIELD

[0002] This disclosure relates generally to the field of integrated
circuit fabrication, and more particularly to obtaining a desired
workfunction in a metal gate high-k (MGHK) field effect transistor (FET)
using a gate-last fabrication process.

DESCRIPTION OF RELATED ART

[0003] Integrated circuits (ICs) include many types of devices, such as
field effect transistors (FETs), which may include p-type field effect
transistors (PFETs) and n-type field effect transistors (NFETs). The
mainstay material of IC fabrication is silicon (Si) and silicon-based
materials. As device sizes are being scaled down, IC technology becomes
more complex, and changes in device structures and new fabrication
methods are needed to maintain expected performance enhancements from one
generation of devices to the next. Reduction of power consumption in
successive generations of ICs is also important for many applications,
such as use of ICs in mobile, battery-powered devices, allowing for
extended battery life. A FET device may include a MGHK FET, with a gate
including a gate metal layer and a high-k dielectric gate dielectric
layer

[0004] A FET gate may be formed using a gate-first process, or a gate-last
process. Gate-first refers to a fabrication process in which the FET gate
is formed before device activation, which may include a high temperature
anneal (about 1000° C. or higher). In a gate-last fabrication
process, the FET gate is formed after device activation, in order to
avoid heating the gate materials during activation. A gate-last
fabrication process may be used to form quarter-gap MGHK NFETs and PFETs;
however, such a process may require use of different metals for PFET and
NFET gate metal layers, resulting in a relatively complex fabrication
process.

SUMMARY

[0005] In one aspect, a quarter-gap p-type field effect transistor (PFET)
formed by gate-last fabrication includes a gate stack formed on a silicon
substrate, the gate stack including: a high-k dielectric layer located on
the silicon substrate; and a gate metal layer located over the high-k
dielectric layer, the gate metal layer including titanium nitride and
having a thickness of about 20 angstroms; and a metal contact formed over
the gate stack.

[0006] In one aspect, a quarter-gap n-type field effect transistor (NFET)
formed by gate-last fabrication includes a gate stack formed on a silicon
substrate, the gate stack including: a high-k dielectric layer located on
the silicon substrate; and a first gate metal layer located over the
high-k dielectric layer, the first gate metal layer including titanium
nitride; and a metal contact formed over the gate stack.

[0007] Additional features are realized through the techniques of the
present exemplary embodiment. Other embodiments are described in detail
herein and are considered a part of what is claimed. For a better
understanding of the features of the exemplary embodiment, refer to the
description and to the drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0008] Referring now to the drawings wherein like elements are numbered
alike in the several FIGURES:

[0009]FIG. 1 illustrates an embodiment of a method of method of gate-last
fabrication a quarter-gap MGHK FET.

[0010]FIG. 2 illustrates an embodiment of a gate stack formed on a
silicon substrate.

[0011]FIG. 3 illustrates an embodiment of the device of FIG. 2 after
device activation and removal of the top polysilicon layer.

[0012]FIG. 4 illustrates an embodiment of the device of FIG. 3 after
formation of a metal contact.

[0013]FIG. 5 illustrates an embodiment of an activated FET device formed
by the method of FIG. 1.

[0014]FIG. 6 illustrates an embodiment of an activated FET device formed
by the method of FIG. 1.

[0015]FIG. 7 illustrates an embodiment of an activated FET device formed
by the method of FIG. 1.

DETAILED DESCRIPTION

[0016] Embodiments of a method of gate-last fabrication of a quarter-gap
MGHK FET are provided, with exemplary embodiments being discussed below
in detail. A quarter-gap MGHK FET (NFET or PFET) including a titanium
nitride (TiN) gate metal layer of an appropriate thickness may be formed
using a gate-last fabrication process. As the TiN gate metal layer
thickness varies from about 20 angstroms to greater than about 35
angstroms thick, there is a marked change in the FET workfunction after
device activation anneal and removal of the top polysilicon layer. This
allows for gate-last fabrication of a quarter-gap NFET, mid-gap FET, or a
quarter-gap PFET MGHK devices by varying the thickness of the gate metal
layer. The effective work function of a quarter-gap NFET device may be
about 4.325 electron-volts (eV), the effective work function of a midgap
FET device may be about 4.600 eV, and the effective work function of a
quarter-gap PFET may be about 4.875 eV. The desired workfunction for a
finished FET device may be obtained by adjusting the thickness of the TiN
gate metal layer. The gate stack may further include a threshold voltage
(Vt) tuning cap layer, an oxygen barrier layer, and/or an additional
gate metal layer in some embodiments; the presence of such layers may
affect the required thickness of the gate metal layer necessary to obtain
the desired FET workfunction.

[0017]FIG. 1 illustrates an embodiment of a method of gate-last
fabrication a quarter-gap MGHK FET. FIG. 1 is discussed with reference to
FIGS. 2-7. In block 101, a gate stack is formed on a Si substrate 201, as
is shown in device 200 of FIG. 2. In the embodiment of FIG. 2, the gate
stack includes a high-k dielectric layer 202 and a gate metal layer 203;
a top polysilicon layer 204 is formed over the gate stack. The gate stack
is located on Si substrate 201. High-k dielectric layer 202 may include
hafnium oxide in some embodiments. Gate metal layer 203 is TiN. The
thickness of the gate metal layer 203 may vary, based on the type of
device (quarter-gap NFET, mid-gap FET, or quarter-gap PFET) being
fabricated; the gate metal layer 203 may have a thickness ranging from
about 20 angstroms up to greater than 35 angstroms in some embodiments.
The gate stack formed in block 101 may additionally include a threshold
voltage tuning cap layer, one or more oxygen barrier layers, and/or an
additional gate metal layer in some embodiments; such embodiments are
discussed in further detail below with respect to FIGS. 5-7.

[0018] In block 102, device activation is performed by annealing the
device 200. The anneal may have a minimum temperature of about
1000° C. in some embodiments. After the anneal is completed, top
polysilicon layer 204 is removed selective to gate metal layer 202,
resulting in the device 300 shown in FIG. 3, including high-k dielectric
layer 202 and gate metal layer 203 on silicon substrate 201.

[0019] In block 103, a metal contact 401 is formed over the gate stack of
the device of FIG. 3, resulting in MGHK FET 400 as shown in FIG. 4. Metal
contact 401 may include aluminum (Al) or tungsten (W) in some
embodiments. MGHK FET 400 includes silicon substrate 201, high-k
dielectric layer 202, gate metal layer 203, and metal contact 401. MGHK
FET 400 may include a quarter-gap NFET, a quarter-gap PFET, or a mid-gap
FET, depending on the thickness of gate metal layer 203. In embodiments
in which gate metal layer 203 is about 20 angstroms thick, MGHK FET 400
is a quarter-gap PFET. In embodiments in which gate metal layer 203 is
from about 20 angstroms to about 35 angstroms thick, MGHK FET 400 is a
mid-gap FET. In embodiments in which gate metal layer from about 35
angstroms thick to about 100 angstroms thick, MGHK FET 400 is a
quarter-gap NFET.

[0020] In some embodiments, an MGHK FET 500 formed by the gate-last method
of FIG. 1 may include a threshold voltage tuning cap layer 505 formed
between the high-k dielectric layer 502 and the gate metal layer 503, as
is shown in FIG. 5. The gate stack including high-k dielectric layer 502,
threshold voltage tuning cap layer 505, and gate metal layer 503 is
formed with a top polysilicon layer (not shown) on silicon substrate 501
before device activation in block 102 of FIG. 1. MGHK FET 500 further
includes metal contact 504 that is formed over gate metal layer 503 after
device activation and removal of the top polysilicon layer. Metal contact
504 may include Al or W in some embodiments. High-k dielectric layer 502
may include hafnium oxide in some embodiments. Gate metal layer 503 is
TiN. Threshold voltage tuning cap layer 505 may include Al, lanthanum
(La), or magnesium (Mg) in some embodiments. In embodiments in which gate
metal layer 503 is from about 35 angstroms thick to about 100 angstroms
thick, and threshold voltage tuning cap layer 505 includes Al, MGHK FET
500 is a mid-gap FET. In embodiments in which gate metal layer 503 is
about 20 angstroms thick, and threshold voltage tuning cap layer 505
includes a relatively thick La layer (having a thickness from about 4
angstroms to about 100 angstroms), MGHK FET 500 is a quarter-gap NFET. In
embodiments in which gate metal layer 503 is about 20 angstroms thick,
and threshold voltage tuning cap layer 505 includes a relatively thin La
layer (having a thickness from about 1 angstrom to about 4 angstroms in
some embodiments), MGHK FET 500 is a mid-gap FET.

[0021] In some embodiments, an MGHK FET device 600 formed by the gate-last
method of FIG. 1 may include an oxygen barrier layer 604 located between
a first gate metal layer 603 and a second gate metal layer 605, as shown
in FIG. 6. MGHK FET 600 includes a gate stack including high-k dielectric
layer 602, first gate metal layer 603, oxygen barrier layer 604, and
second gate metal layer 605, which is formed with a top polysilicon layer
(not shown) on silicon substrate 601 before device activation in block
102 of FIG. 1. MGHK FET 600 further includes metal contact 606 that is
formed over second gate metal layer 605 after device activation and
removal of the top polysilicon layer. Metal contact 606 may include Al or
W in some embodiments. High-k dielectric layer 602 may include hafnium
oxide in some embodiments. First gate metal layer 603 and second gate
metal layer 605 are TiN. Oxygen barrier layer 604 may include tantalum
nitride (TaN) deposited via atomic layer deposition (ALD) in some
embodiments, or may be deposited by physical vapor deposition (PVD) in
other embodiments. In embodiments in which first gate metal layer 603 is
about 20 angstroms thick, and second gate metal layer 605 is from about
35 angstroms to about 100 angstroms thick, MGHK FET 600 includes a
quarter-gap NFET. In such an embodiment, the second gate metal layer 605
and oxygen barrier layer 604 may be selectively removed before formation
of a metal contact in order to form a quarter-gap PFET device including
high-k dielectric layer 602 and first gate metal layer 603 (which is
about 20 angstroms thick), such as is discussed above with reference to
FIG. 4.

[0022] In some embodiments, an MGHK FET 700 formed by the gate-last method
of FIG. 1 may include a threshold voltage tuning cap layer 703 and an
oxygen barrier layer 705, as shown in FIG. 7. MGHK FET 700 includes a
gate stack including high-k dielectric layer 702, threshold voltage
tuning cap layer 703, first gate metal layer 704, oxygen barrier layer
705, and second gate metal layer 706, which is formed with a top
polysilicon layer (not shown) on silicon substrate 701 before device
activation in block 102 of FIG. 1. MGHK FET 700 further includes metal
contact 707 that is formed over second gate metal layer 706 after device
activation and removal of the top polysilicon layer. Metal contact 707
may include Al or W in some embodiments. High-k dielectric layer 702 may
include hafnium oxide in some embodiments. First gate metal layer 704 and
second gate metal layer 706 are TiN. Oxygen barrier layer 705 may include
tantalum nitride (TaN) deposited via ALD in some embodiments, or may be
deposited by PVD in other embodiments. In embodiments in which first gate
metal layer 704 is about 20 angstroms thick, second gate metal layer 706
is from about 35 angstroms to about 100 angstroms thick, and threshold
voltage tuning cap layer 703 includes Al, MGHK FET 700 includes a mid-gap
FET. In embodiments in which first gate metal layer 704 is about 20
angstroms thick and oxygen barrier layer 705 and second gate metal layer
706 are removed, a threshold voltage tuning cap layer 703 including La or
Mg is employed to obtain a mid-gap FET.

[0023] The technical effects and benefits of exemplary embodiments include
formation of a quarter-gap MGHK NFET and PFET devices using a gate-last
fabrication process.

[0024] The terminology used herein is for the purpose of describing
particular embodiments only and is not intended to be limiting of the
invention. As used herein, the singular forms "a", "an", and the are
intended to include the plural forms as well, unless the context clearly
indicates otherwise. It will be further understood that the terms
"includes" and/or "including," when used in this specification, specify
the presence of stated features, integers, steps, operations, elements,
and/or components, but do not preclude the presence or addition of one or
more other features, integers, steps, operations, elements, components,
and/or groups thereof.

[0025] The corresponding structures, materials, acts, and equivalents of
all means or step plus function elements in the claims below are intended
to include any structure, material, or act for performing the function in
combination with other claimed elements as specifically claimed. The
description of the present invention has been presented for purposes of
illustration and description, but is not intended to be exhaustive or
limited to the invention in the form disclosed. Many modifications and
variations will be apparent to those of ordinary skill in the art without
departing from the scope and spirit of the invention. The embodiment was
chosen and described in order to best explain the principles of the
invention and the practical application, and to enable others of ordinary
skill in the art to understand the invention for various embodiments with
various modifications as are suited to the particular use contemplated.

Patent applications by Junli Wang, Slingerlands, NY US

Patent applications by Kisik Choi, Hopwell Junction, NY US

Patent applications by Takashi Ando, Tuckahoe, NY US

Patent applications by Tenko Yamashita, Schenectady, NY US

Patent applications by Vijay Narayanan, New York, NY US

Patent applications by GLOBALFOUNDRIES INC.

Patent applications by International Business Machines Corporation

Patent applications in class Gate insulator includes material (including air or vacuum) other than SiO 2

Patent applications in all subclasses Gate insulator includes material (including air or vacuum) other than SiO 2