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描述

General Description:Cases have been seen where designs failed during the clock placement phase with an error message indicating that there is a conflict in pin usage between neighboring BUFGMUX's which share a routing resource:

"ERROR:Place:37 - A global clock component <CLK_GEN/PORT12_BUFGMUX> configured asa selectable mux is placed in site BUFGMUX2S. This configuration requires that the global clocksite BUFGMUX2S either be empty or contain a global buffer or mux with the inputs IN0 and IN1either not drive by a signal or driven by the same signals as the original muxes IN1 and IN0 pinsrespectively in order to route up both of the inputs. In other words the input signal for IN0 on onebuffer must be the same as the input signal driving IN1 on the other buffer (or one of them must notbe driven) to place the two buffers in the paired sites. The site BUFGMUX2S has the global buffer<CLK_GEN/PORT12_BUFGMUX> placed there. This design is unroutable. Please correct thisproblem before continuing."

It has been determined that this is an invalid error that occurs when the clock placer attempts to place a design that has an input net driving three or more BUFGMUX IN0/IN1 pins.

解决方案

This problem is scheduled to be fixed in 6.2i. Meanwhile, the work-around is to lock the placement of all BUFGMUX's, DCMs and Clock IO and set the following environment variable to skip the autoplacement of these components: