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Abstract

Disclosed is a control circuit for redundant disk array system (RAID) which has the ATA InterFace (standards of American National Standard) both for the host and for the Hard Disk Drive. This controller circuit enables the MPU on the controller read the multiple HDDs' status concurrently.

Country

United States

Language

English (United States)

This text was extracted from an ASCII text file.

This is the abbreviated version, containing approximately
100% of the total text.

Concurrent Register Read Operation for Redundant Disk
Array System

Disclosed is
a control circuit for redundant disk array system
(RAID) which has the ATA InterFace (standards of American National
Standard) both for the host and for the Hard Disk Drive. This
controller circuit enables the MPU on the controller read the
multiple HDDs' status concurrently.

Fig. 1 shows
the block diagram which constructs RAID level1
system. The host i/f is the ATA i/f and
2 HDDs' i/f are also the ATA
i/f. This controller controles 2
HDDs. When the MPU in the
controller checks 2 HDDs' status, MPU read the status data from HDD1
and HDD2 through HDD1 and HDD2 AT i/f.

Fig. 2 shows
the circuit of this disclosure. The
status of
HDD1 and HDD2 are made from 8 bit data.
Each bit of both drive are
made AND or OR by this circuit.

For example,
bit7 BSY from both HDD are made AND and OR and are
output as bit7 of MIX_STAT reg or bit6 of MIX_STAT reg. When READ
command from the host is active to HDD1 and HDD2, MPU checks bit7 of
MIX_STAT_REG. When bit7 shows NOT BSY,
then MPU knows the one of 2
HDD is ready to respond READ command.
When WRITE command from the
host is active to HDD1 and HDD2, MPU checks bit6 of MIX_STAT_REG.
When bit6 shows NOT BSY, then MPU knows both of the HDDs are ready to
data transfer. Thus, MPU can check HDDs'
status at one time.