Wireless Connectivity IP

ZigBee SoC White Box IP

Description

A low-power, highly-integrated SoC solution, the Zigbee chip is a true 2.4GHz SoC solution with Zigbee compliant platform and supports IEEE 802.15.4 Standard. Combined with the Zigbee stack, the solution can be used for a wide range of applications and is perfect for creating interoperable solution for home or office usage.

Deliverables

ZigBee Sub1 Ghz 802.15.4 RF IP

Description

This IP is a fully integrated system-on-chip radio transceiver targeting Smart Grid applications. The performance is tailored for extremely low power operation to be used in sensor monitoring networks and remote control for wireless networks. Transmitter output power ranges from -8 to +15 dBm, while receiver sensitivity is -110 dBm at 25kbps data rate.
Additional peripherals such as ADC, SPI, I2C, UART, I2S and timers are all included on the same chip, resulting in a compact system solution.This is ideal for portable applications in frequency ranges 863-928 MHz , in particular those needing long battery life and/or signal processing, such as AMR, WSN and medical.

Features

Ultra-low power 863-928 MHz transceiver

Low voltage operation from 3.6 V down to 1.0? V

Minimum current standby mode with RTC based on 32 ?kiHz crystal oscillator: 1? µA at 37?°C

Deliverables

ZigBee Transceiver PHY IP

Description

The modulation and spreading functions for the O-QPSK PHYs are processed through 3 steps. First, each 4 bits are gathered to represent 1 symbol which has a value from 0 to 15. Second, each symbol is used to select among 16 PN sequences called chip. Finally, each chip is modulated using O-QPSK with half-sine pulse shaping.
Once a preamble is detected, the Start of Frame Delimiter (SFD), frame length, and other receiver status information is sent to the upper layer. Additionally, the payload data is written to the received data buffer to create the PSDU packet, which is transferred to the MAC layer when requested. The PHY notifies the MAC layer for arrival of MAC Protocol Data Unit (MPDU) along with the LQI information via an interrupt. If a valid preamble is not detected, it gives feedback to the packet time error detection block to restart the energy detection process. The design includes ED and LQI circuits to support CCA modes by MAC defined in IEEE 802.15.4. The design includes a standard 32-bit AHB-lite, slave interface version 3.0, with registers as defined in the Register Description section of the Datasheet.

Deliverables

DVB S2/S Satellite Tuner SoC White Box IP

Description

This satellite tuner is a direct-conversion (zero IF) receiver for digital TV Broadcasting. On the RF input, there is a variable gain, low-noise amplifier (VGLNA). The RF gain is monitored by an automatic gain control (AGC) circuit to ensure an optimal signal level for the two mixers. Each mixer, which down-converts the signal to the baseband, is followed by an AGCcontrolled VGA, a low-pass filter and a second VGA. The local oscillator (LO) signals are provided by an integrated fractional-N phase locked loop (PLL), which contains an on-chip voltage-controlled oscillator (VCO) meeting stringent phase noise requirements.

The PLL loop filter is partly integrated. The LO frequencies are programmable between 950 MHz and 2150 MHz. The comparison frequency for the phase-frequency detector (PFD) is generated by dividing the crystal oscillator reference frequency. The crystal frequency may be within the range 15 MHz to 31 MHz depending on the application.

DVB T/C Demodulator SoC White Box IP

Description

The V0367 inherits the functionality of the industry-leading enhanced V0362 terrestrial and V0297E cable demodulators in one single advanced combo receiver.

The V0367 COFDM section of the receiver is fully compliant with the DVB-T standard framing structure, channel coding and modulation. The symbol, timing and carrier recovery loops are completely digital and tailored to comply with state-of-the-art RF down-converting tuner devices.

Description

The iD135 has been designed for Satellite Broadband applications, leveraging Ka-band and multi-spot beam technology carried by the latest high-throughput satellites (HTSs).

The iD135 has been designed to enable single-carrier usage of HTS transponders. The device implements two high-symbol-rate (HSR) demodulators compliant with Annex M of the DVB-S2/S2X specification EN 302 307, and provides full HW support for network clock recovery (NCR) in order to enable external return-channel modulators.

The iD135 may be used in standard broadcast environments as an 8-channel DVB-S2/S2X receiver enabling multi-channel distribution and/or fast channel change scenarios.

Features

Two high-symbol-rate (HSR) demodulators:

Maximum baud rate 500 Msymbol/s

Up to two slices each

DVB-S2/S2X and Annex M compliant

Up to 8 multi-standard demodulators:

S/S2/S2X/DTV

Integrated full-band tuners and ADCs

High-speed digital multiplexer to connect any tuner to any demodulator

Bluetooth Dual Mode v4.2 RF Transceiver IP

Description

A low-power, highly-integrated SoC solution, the Zigbee chip is a true 2.4GHz SoC solution with Zigbee compliant platform and supports IEEE 802.15.4 Standard. Combined with the Zigbee stack, the solution can be used for a wide range of applications and is perfect for creating interoperable solution for home or office usage.

Bluetooth Dual Mode v4.2 Baseband IP

This Bluetooth Dual Mode v4.2 Digital Baseband IP is the design data base of a production Bluetooth Dual Mode SoC shipped in smart phones. The Baseband IP is compliant with Bluetooth Classic and Low Energy standards including BT 2.1 + BT 3.0 + EDR + BT 4.2 and BLE. Firmware source code is supplied to enable interface into protocol Stack SW at the HCI layer through UART and I2S.
The A2DP offloading can also be performed with audio data transferred from Host over PCM or I2C of Stereo Audio Data samples (44.1 or 48 Khz) to/from the IP. Data can be transferred in burst mode over the PCM / I2S interface in order to achieve significant host power consumption improvements during A2DP playback. The IP embeds support of modified SBC encoding and decoding for Wideband speech. The Whole processing is performed internally and does not require dedicated processing from Host side.
An optional DSP (CoolFlux) is integrated into the audio path to provide audio processing capabilities from Wide-Band Audio Codec implementation to MP3 and noise cancellation.

Features

High Volume Silicon Proven

Extracted from Design Data Base of production chip

Fully compliant to BT standard

Support of Bluetooth Low energy (BLE)

Support of Basic Rate and Enhanced Data rate (2 and 3 Mb/s)

Supports Scatternet topologies

S(eSCO)/S/S, M(eSCO)/S/S and M/S(eSCO)/S

HCI interface to 3rd party Dual Mode Protocol Stacks

Available integrated with Bluetooth Dual Mode v4.2 RF Transceiver IP

Deliverables

Source Code Delivery with rights to modify

Schematics

Certification Certificates

Chip Test program

KGD

Bluetooth Dual Mode SoC White Box IP

Description

A unique opportunity to licence the "white box source code" design data base of a Tier 1 semiconductor's high volume mass production BT4.0 Dual Mode "SoC" that has been shipped in Tier 1 OEM products.
This IP is delivered as the complete chip design data base enabling internalization, customization and porting of the design to future process nodes.
The IP comes with all certification certificates and SW and the design data base can be TO and in volume production in under 6 months of purchase.
The commercial terms are single NRE payment, no royalties, unlimited usage, making it a very cost effective, low risk, BT Dual Mode technology access.