Intel Opens Door on 7nm, Foundry

SAN FRANCISCO — Intel believes it can drive Moore’s Law down to 7 nm even without long-delayed advances in lithography. It also gave its most detailed look to date at its foundry service for sharing its chipmaking prowess, including a description of a new low-cost alternative to 2.5D chip stacking it has in development.

“My day job is working on [research for a process to make] 7 nm [chips and] I believe there is a way without EUV,” said Intel fellow Mark Bohr, responding to a question after a talk on Intel’s new 14 nm process.

The optimism is significant given the core lithography used for patterning chips hasn’t had an upgrade in more than a decade. Chipmakers generally don’t expect the much-delayed extreme ultraviolet (EUV) lithography in time for 10 nm chips, but many still hold out hopes it could be ready for a 7 nm generation.

“I am very interested in EUV [because it] could really help scaling and perhaps process simplification, reducing three or four masks to one in some cases,” Bohr said. “Unfortunately, it’s not ready yet -- the throughput and reliability are not there.”

Bohr did not give any hints about how Intel will make 7 or even 10 nm chips without EUV. However he did note at 14 nm Intel is using triple patterning on one or more critical layers.

Although wafer costs rose at an accelerating rate for the last two nodes due to the need for more masks, Intel continues to pack more transistors in a given area of silicon. The density offsets wafer costs, leading to the cost-per-transistor decline, Bohr said in his talk on Intel’s 14 nm process.

“One of the fundamental benefits of Moore’s Law is smaller feature sizes, primarily to get lower cost per transistor so we can do more things” in a similarly sized chip, he said.

Intel already announced it has started making in volume chips using a 14 nm process at a lower cost per transistor than its prior 22 nm generation. It also said it is in development of a 10 nm process that it believes will deliver lower cost per transistor.

In a separate talk, Intel said before the end of 2015 it could offer external foundry customers a chance to try out its emerging 10 nm process on shared wafers called shuttles.

Even if Memory suppliers agreed to re-design their die layout, redistribution like that would increase interconnect length, hence RC delays, when one of the key reasons for going to 2.5 d modules is breaking the Memory Wall ( interconnect related limits on Bandwidth, Sp. power for data transfer ).

This is of course assuming that the mechanical issues ( warpage during assembly, fatigue during service ) related to embedding Si Bridge chips in cheaper organic substrates with much higher CTE won't remain a factor.

And finally for a 5 die module the savings in Interposer area with the Bridge chip would be about 50 %. The additional cost of embed etc. will need to be lower than those savings.

>> They say they can keep making the chips at lower cost/transistor per node...but what's the premium foundry customers must pay?

Kudos to Intel for its continuous quest to extend the Moore's law. 7nm could be challenging and many not make lots of business sense except for Intel. I have come to believe that value will come from making smart chips and not higher speed and small size. But Intel is fixated on this down-scaling of feature sizes of transistors. I hope the cost can attract customers to it.

Having the technology is good, but what most people miss is that Intel typically locks down its process and tries to run everything on it. That is fine for your own products, but foundries need to be able to tweek the process to the customer's products. To be a major foundry player, Intel will have to break the "no process modification" mindset and having dedicated fabs may be the first step. But as Rick pointed out, even with the right foundry mindset, the cost of the technology may ultimately be the limiting factor.

Wow! No one commented yet on the 2.5D announcement. This to me is the most significant development of all. Interposer interconnect WITHOUT TSVs! Silicon area a fraction of current interposer solutions. No ultra-thin handling requirements. Available next year. Brilliant! Now all we need are chips with the IO routed to the edge...

US laws prevent (last time I checked) the export of leading edge technology to China, which is why Fab68 at least started up only making chipsets on 65nm when intel was making processors on 32nm. That would suggest 10/7nm foundry in China is a long way off.
Also, EE Times seems even more Intel centric than usual lately. Feels like I'm reading PR news releases from them here every other day or so.

Intel's 10 nm seems pretty much settled now, but it has also been implied pretty often that 7 nm will use the same SAQP methodology as 10 nm. We often hear both nodes talked about in the same breath. Maybe they're looking at DSA as well. In foundry world, only hear TSMC and Intel talk about these nodes. The next few years will be very interesting...