Advantest's newest memory tester doubles DRAM, flash throughput

SANTA CLARA, Calif. -- Advantest Corp. today announced it has begun selling new DRAM and flash memory tester that has the ability to simultaneously test up to 128 devices at a time with speeds of 143 MHz or 286 MHz for double data rate (DDR) chips.

The new T5375 is being aimed at "front-end" testing of DRAMs--when redundancy analysis is first performed--as well as "back-end" testing of nonvolatile flash memories, said the Japanese tester company.

One of the targets of the T5375 test system is to handle the increase in volumes of memory devices that will be fabricated on larger 300-mm wafers. Tokyo-based Advantest said the 300-mm wafers will increase the throughput requirements of testing operations because more devices will be fabricated on each 12-inch diameter substrate.

In DRAM testing, the T5375 system will perform front-end tests for standard synchronous DRAMs, DDR SDRAMs, and Direct Rambus memories. The system is also expected to serve static RAM testing. With the ability to test 128 wide-bit (by-18 and by-20) memories, the T5375 will be capable of providing twice the throughput of its predecessor, according to Advantest.

During front-end testing of random-access memories, the new system will reduce redundancy analysis times by about 30% using its own memory repair analyzer, the MRA4, said Advantest.

In flash testing, the system will handle a range of memory architectures, including NOR and NAND flash chips, said the company. High-speed synchronous flash testing is provided at speeds of 143 MHz or 286 MHz (in DDR mode). This performance level is more than two times that of the T5371 memory tester, said Advantest.

The new tester is also able to simultaneously test up to 128 flash memories (in by-16 and by-18 configurations). The T5375 allows testing of defective blocks on a block-by-block basis and lets each device independently set masks that prevent blocks from being tested, Advantest said. The company said these features play a major role in reducing the testing times for NAND-based flash chips.