Sign up to receive free email alerts when patent applications with chosen keywords are publishedSIGN UP

Abstract:

A precision high-frequency capacitor includes a dielectric layer formed
on the front side surface of a semiconductor substrate and a first
electrode on top of the dielectric layer. The semiconductor substrate is
heavily doped and therefore has a low resistivity. A second electrode,
insulated from the first electrode, is also formed over the front side
surface. In one embodiment, the second electrode is connected by a
metal-filled via to a layer of conductive material on the back side of
the substrate. In alternative embodiments, the via is omitted and the
second electrode is either in electrical contact with the substrate or is
formed on top of the dielectric layer, yielding a pair of
series-connected capacitors. ESD protection for the capacitor can be
provided by a pair of oppositely-directed diodes formed in the substrate
and connected in parallel with the capacitor. To increase the capacitance
of the capacitor while maintaining a low effective series resistance,
each of the electrodes may include a plurality of fingers, which are
interdigitated with the fingers of the other electrode. The capacitor is
preferably fabricated in a wafer-scale process concurrently with numerous
other capacitors on the wafer, and the capacitors are then separated from
each other by a conventional dicing technique.

Claims:

1. A precision high-frequency capacitor comprising: a heavily-doped
semiconductor substrate having a principal surface; a dielectric layer
formed on the principal surface of the substrate; a first electrode layer
formed on the dielectric layer and electrically insulated from the
substrate; and a second electrode layer formed on the dielectric layer
and electrically insulated from the substrate.

2. The capacitor of claim 1 further comprising a first solder bump
electrically connected to the first electrode layer, a second solder bump
electrically connected to the second electrode layer.

3. The capacitor of claim 1 further comprising a passivation layer
overlying the first and second electrodes.

4. The capacitor of claim 1 wherein the doping concentration of the
semiconductor substrate is greater than 1.times.10.sup.19 cm.sup.-3.

5. The capacitor of claim 1 wherein the dielectric layer comprises an
oxide or a nitride.

6. The capacitor of claim 1 wherein the dielectric layer comprises an
oxide and a nitride.

7. The capacitor of claim 1 wherein the semiconductor substrate is a
common terminal between two capacitors connected in series.

8. The capacitor of claim 1 further comprising a pair of
oppositely-directed electrostatic discharge (ESD) protection diodes, the
ESD protection diodes being connected in parallel with the capacitor and
being formed in the substrate.

9. The capacitor of claim 8 wherein the substrate includes N and P
regions configured to form each ESD diode, the N and P regions having
doping concentrations configured to set a reverse breakdown voltage for
each ESD protection diode.

10. A method of forming a precision high-frequency capacitor, the method
comprising: providing a heavily-doped semiconductor substrate having a
principal surface; forming a dielectric layer on the principal surface of
the substrate; forming a first electrode layer on the dielectric layer
and electrically insulated from the substrate; and forming a second
electrode layer on the dielectric layer and electrically insulated from
the substrate.

11. The method of claim 10 further comprising forming a first solder bump
electrically connected to the first electrode layer and forming a second
solder bump electrically connected to the second electrode layer.

12. The method of claim 10 further comprising forming a passivation layer
overlying the first and second electrodes.

13. The method of claim 10 wherein the doping concentration of the
semiconductor substrate is greater than 1.times.10.sup.19 cm.sup.-3.

14. The method of claim 10 further comprising forming the dielectric
layer with an oxide or a nitride.

15. The method of claim 10 further comprising forming the dielectric
layer with an oxide and a nitride.

16. The method of claim 10 wherein the semiconductor substrate is a
common terminal between two capacitors connected in series.

17. The method of claim 10 further comprising forming a pair of
oppositely-directed electrostatic discharge (ESD) protection diodes in
the substrate, the ESD protection diodes being connected in parallel with
the capacitor.

18. The method of claim 17 further comprising forming N and P regions
configured to form each ESD diode, the N and P regions having doping
concentrations configured to set a reverse breakdown voltage for each ESD
protection diode.

19. A precision high-frequency capacitor comprising: a heavily-doped
semiconductor substrate having a principal surface; a dielectric layer
formed of an oxide and a nitride on the principal surface of the
substrate; a first electrode layer formed on the dielectric layer and
electrically insulated from the substrate; and a second electrode layer
formed on the dielectric layer and electrically insulated from the
substrate.

20. The capacitor of claim 19 further comprising a pair of
oppositely-directed electrostatic discharge (ESD) protection diodes, the
ESD protection diodes being connected in parallel with the capacitor and
being formed in the substrate.

Description:

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation of U.S. patent application Ser.
No. 11/601,501, filed Nov. 16, 2006, which is a continuation of U.S.
patent application Ser. No. 10/456,018, filed Jun. 5, 2003, now U.S. Pat.
No. 7,151,036, issued Dec. 19, 2006, which is a Divisional of U.S. patent
application Ser. No. 10/208,599, filed Jul. 29, 2002, now U.S. Pat. No.
6,621,143, issued Sep. 16, 2003, which is a Divisional of U.S. patent
application Ser. No. 09/661,483, filed Sep. 14, 2000, now U.S. Pat. No.
6,538,300, issued Mar. 25, 2003, which are incorporated by reference as
if fully set forth.

[0002] This invention is related to U.S. patent application Ser. No.
09/545,287 by Kasem et al., filed Apr. 7, 2000, entitled, "Vertical
Structure And Process For Semiconductor Wafer-Level Chip Scale Packages,"
which is incorporated herein by reference in its entirety.

FIELD OF INVENTION

[0003] This invention relates to semiconductor technology and in
particular to the formation of a high-frequency capacitor on a
semiconductor substrate.

BACKGROUND

[0004] Higher frequencies are increasingly being used in communications
technology. For example, frequencies in the range of 450 MHz to 3 GHz are
used in cellular communications and frequencies in the range of 10 GHz to
18 GHz are used in satellite video and data transmission.

[0005] These applications require small, precise capacitors. Multi-layer
ceramic capacitors have been employed for this purpose, but they tend to
be lacking in precision and performance. Thin film capacitors have
improved precision and performance but they are expensive.

[0006] Accordingly, there is a need for a precision high-frequency
capacitor that can be manufactured at a reasonable cost.

SUMMARY

[0007] In accordance with this invention, a precision high-frequency
capacitor is formed on a heavily-doped semiconductor substrate having
first and second principal surfaces. The capacitor includes a dielectric
layer on the first principal surface of the substrate and a main
electrode layer on the dielectric layer. A conductive layer is formed on
the second principal surface of the substrate. A via containing a
conductive material extends through the substrate. A second electrode
layer is formed over the first principal surface of the substrate,
adjacent an opening of the via. The second electrode is electrically
connected to the conductive layer by means of the conductive material in
the via. Thus, when a voltage difference is applied to the electrodes,
the main electrode layer and the substrate act as the "plates" of the
capacitor, separated by the dielectric layer.

[0008] In an alternative embodiment, the via is omitted, and the second
electrode layer, electrically insulated from the first electrode layer,
is formed over the first principal surface of the substrate. In one
version, the second electrode is separated from the substrate by the
dielectric layer, creating in effect a pair of series-connected
capacitors, with the substrate representing the common terminal between
the capacitors. In another version, the second electrode is in electrical
contact with the substrate, creating a single capacitor. Each of the
electrode layers may include a plurality of fingers, with the fingers
being interdigitated. The dielectric layer, often an oxide, may be
thinner under the fingers than under the "palm" portions of the electrode
layers from which the fingers protrude.

[0009] Capacitors in accordance with this invention exhibit numerous
advantages as compared with prior art capacitors. They can be fabricated
at a wafer level with a very low effective series resistance (ESR). They
can function at very tight tolerances (e.g., <2%) throughout their
operational range and can operate at very high frequencies (e.g., up to 5
GHz and higher). They can have a quality (Q) factor, for example, that is
much higher than 1000 at 1 MHz.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] This invention will be best understood by reference to the
following drawings, in which like components have the same reference
numeral. The drawings are not necessarily drawn to scale.

[0011]FIG. 1 is a cross-sectional view of a capacitor in accordance with
the invention containing a via through the substrate.

[0012]FIG. 1A is a graph showing the Q of a capacitor in accordance with
this invention, i.e., the ratio of the imaginary part of the impedance to
the real part of the impedance, as a function of frequency.

[0013] FIGS. 2A-2J illustrate the steps of a process that can be used to
fabricate the capacitor of FIG. 1.

[0014]FIG. 3 is a cross-sectional view of a capacitor in accordance with
this invention containing two electrodes on the same surface of the
substrate.

[0015]FIG. 4 is a cross-sectional view of a capacitor with trenches
formed under each of the electrodes.

[0016]FIG. 5 is a cross-sectional view of a capacitor similar to the
capacitor shown in FIG. 3 except that one of the electrodes is
electrically connected to the substrate.

[0017]FIG. 6 is a top view of a capacitor wherein the electrodes have
fingers interdigitated with each other.

[0018] FIG. 7 is a cross-sectional view of the capacitor shown in FIG. 6
showing that the dielectric layer is thinner under the fingers.

[0019] FIG. 8 is a circuit diagram of an ESD-protected capacitor
containing a pair of oppositely-directed diodes.

[0020] FIG. 9 is a cross-sectional view of an ESD-protected capacitor in
accordance with this invention.

[0021] FIGS. 10a and 10b are graphs showing simulated breakdown
characteristics of an ESD-protected capacitor of the kind shown in FIG.
9.

[0022] FIG. 11 is a graph showing the simulated effective capacitance of
the ESD-protected capacitor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] The principles of this invention will be described by reference to
the following embodiments, which are illustrative only.

[0024]FIG. 1 shows a cross-sectional view of a first embodiment according
to the invention. Capacitor 10 is formed on an N+ silicon substrate 102.
Substrate 102 may be doped to a concentration of 3 to 4×1019
cm-3, for example, and may have a resistivity of about 2 mΩ-cm
and as high as about 3 mΩ-cm. A dielectric layer 104 is formed on
the front surface of substrate 102. Dielectric layer 104 is formed of
SiO2, which may be thermally grown or deposited by chemical vapor
deposition (CVD). Alternatively, layer 104 could be formed of another
dielectric such as a nitride or a combination of an oxide and a nitride.
A thermally-grown oxide is reliable and reproducible and can withstand
electric fields up to 4 MV/cm without deterioration. The 3σ
variability of the thickness of a thermally-grown oxide thicker than 0.1
μm is less than 1.5%.

[0025] On top of dielectric layer 104 is a main electrode 106 and a second
electrode 108. Electrodes 106 and 108 can be a single- or multi-layer
structure, and can be made of doped polysilicon, a refractory metal, a
refractory metal silicide, an aluminum-based alloy, copper or combination
of the foregoing materials. If they are formed of metal, electrode 106
may include a "seed" or "barrier" layer of a metal (e.g., Ta/Cu)
deposited on substrate 102 by sputtering or evaporation, overlain by a
plated layer. Electrodes 106 and 108 are covered by an insulating
passivation layer 110. Openings are formed in passivation layer 110, and
solder balls 112 and 114 are deposited the openings to allow electrical
contact to be made to the electrodes 106 and 108.

[0026] Beneath the second electrode 108, a via or through-hole 116 is
formed through N+ substrate 102. A conductive material 118 such as
aluminum or copper fills the via 116. The conductive material 118
contacts a conductive layer 120 which is formed on the back side of
substrate 102. Conductive layer 120 may include a metal seed layer
deposited on substrate 102 by sputtering or evaporation, overlain by a
plated metal layer.

[0027] Capacitor 10 thus includes a first "plate" represented by main
electrode 106, which is contacted via solder ball 112; and a second
"plate" represented by N+ substrate 102, which is contacted via solder
ball 114, second electrode 108, conductive material 118 and conductive
layer 120. The "plates" are separated by dielectric layer 104.

[0028] The thickness of dielectric layer 104 can be in the range of 50 to
2 μm. The thinner dielectric layer 104 is, the higher the capacitance.
On the other hand, the thinner dielectric layer 104 is, the lower the
maximum voltage that capacitor 10 can be exposed to without damaging
dielectric layer 104. For example, if dielectric layer 104 is an oxide
having a thickness of 0.1 μm, capacitor 10 would have a capacitance of
roughly 350 pF/mm2.

[0029] Silicon substrate 102 can have a thickness of 200 μm or less.
Doping substrate 102 to a concentration higher than 1×1019
cm-3 keeps the effective series resistance (ESR) at a low level and
avoids the formation of a depletion layer in the substrate. For example,
the ESR for a silicon substrate doped to a concentration of
2×1019 cm-3 was only 2.4 mΩmm2.

[0030] In addition, it is desirable that the Q factor of the capacitor be
higher than 1000 at 1 MHz. The Q factor is defined by the following
equation:

Q = X C R S ##EQU00001##

[0031] where XC is the impedance and RS is the series resistance
of the capacitor at a particular frequency.

[0032]FIG. 1A is a plot of XC and RS as a function of frequency
for capacitor 10, described above, wherein the thickness of the oxide
dielectric layer 104 is 0.1 μm and the N+ silicon substrate is doped
to 2×1019 cm-3. As shown, the Q factor of the capacitor
is higher than 100 up to a frequency of about 2 GHz and is greater than
1000 at 100 MHz.

[0033] While capacitor 10 can be fabricated by a number of processes,
FIGS. 2A-2J illustrate the steps of one process that may be used.

[0034] As shown in FIG. 2A, the process begins with N+ silicon substrate
102. Preferably, substrate 102 is one die of a wafer that will be
separated from the other dice at the completion of the process. Substrate
102 may or may not include an epitaxial layer.

[0035] Dielectric layer 104 is formed by growing an oxide (SiO2)
layer thermally on the front (top) surface of substrate 102. For example,
a 0.2 μm thick oxide layer can be grown by heating the substrate to
1100° C. for 6 minutes in a wet atmosphere.

[0036] Referring to FIG. 2B, a barrier layer 202 of Ta/Cu is sputtered
over the entire surface of oxide layer 104. Layer 202 can be 0.5 to 1.0
μm thick, for example. A photoresist layer 204 is deposited and
patterned as shown in FIG. 2B to define where the main electrode will be
located.

[0038] The front side of substrate 102 is then taped or otherwise
supported, and substrate 102 is thinned from the back side. Substrate 102
may be thinned by grinding its back side. Alternatively, other thinning
techniques such as wet etching and vacuum plasma etching can be used to
thin substrate 102. Another possibility is the atmospheric downstream
plasma (ADP) plasma etching system available from Tru-Si Technologies,
Inc. of Sunnyvale, Calif. Substrate 102, which can initially be in the
range of 625 μm thick, can be thinned to a thickness of less than 200
μm, for example.

[0039] After the thinning process has been contemplated, the tape or other
support is removed. A layer 208 of Ta/Cu is sputtered or evaporated over
the entire back side surface of substrate 102, and a copper layer 210 is
plated onto Ta/Cu layer 208, leaving the structure shown in FIG. 2D.
Copper layer 210 can be 2-3 μm thick, for example.

[0040] As shown in FIG. 2E, a photoresist layer 212 is deposited on the
front side of silicon substrate 102. Photoresist layer 212 is patterned
and etched to produce an opening 214. A conventional wet etch process can
be used, for example. Silicon substrate 102 is etched through opening 214
to form a via 216 and thereby expose the surface of barrier layer 208. As
shown in FIG. 2E, via 216 is conical in shape because silicon etches
along oblique planes. Depending on the shape of opening 214, via 216
could be any shape.

[0041] As shown in FIG. 2F, photoresist layer 212 is then removed, and a
seed layer 218 of Ta/Cu is sputtered onto the entire front side surface
of the structure. Ta/Cu layer 218 can be 0.5-1.0 μm thick, for
example.

[0042] As shown in FIG. 2G, a photoresist layer 220 is deposited and
patterned, leaving a portion of the Ta/Cu layer 218 in the vicinity of
the via 216 exposed.

[0045] As shown in FIG. 2J, a passivation layer 224 is formed and
patterned over the surface of the structure by screen printing, with
openings that expose portions of copper layers 206 and 222. Solder bumps
226 and 228 are formed on the exposed portions of copper layers 206 and
222. The result is capacitor 10 shown in FIG. 1, which can be mounted on
a printed circuit board (PCB) or other structure, using flip-chip
mounting techniques. Optionally, a second passivation layer 230 can be
formed on the back side of the structure.

[0046] Capacitor 10 is preferably formed along with other similar
capacitors on a single wafer. If so, following the fabrication of the
capacitors, the die which contains capacitor 10 is separated from the
other dice in the wafer by sawing the wafer along the scribe lines.

[0047]FIG. 3 shows a cross-sectional view of an alternative embodiment.
Capacitor 30 is actually a pair of capacitors connected in series. A
dielectric layer 302 is formed on N+ silicon substrate 102. Substrate 102
could have a doping concentration of 2×1019 cm-3, for
example, and layer 302 could be thermally-grown oxide with a thickness of
0.1 μm. A metal layer is deposited on dielectric layer 302 and is
patterned, using normal photolithographic processes, to form a first
electrode 304 and a second electrode 306. A passivation layer 308 is
deposited on the top surface of the structure. Openings are formed in
passivation layer 308, and solder balls 310 and 312 are formed as
described above.

[0048] While capacitor 30 is simpler and less expensive to fabricate than,
for example, capacitor 10 (FIG. 1), its capacitance is lower and its
series resistance is greater. For example, the effective capacitance per
unit area is up to 4 times smaller than that of a vertical structure. The
series resistance increases with the square of the lateral dimension of
the device.

[0049] The capacitance per unit area of capacitor 40, shown in FIG. 4, is
significantly increased by the formulation of trenches 406 under
electrodes 304 and 306. Dielectric layer 402 extends into trenches 304
and 306 and lines the walls thereof in the manner of a normal
trench-gated MOSFET. Trenches 304 and 306 are filled with a conductive
material 404, such as polysilicon, which is in electrical contact with
electrodes 304 and 306. The net result is to increase the effective area
of the interface between the "plates" and the dielectric layer of the
capacitor.

[0050]FIG. 5 shows a cross-sectional view of a capacitor 50 which is
similar to capacitor 30 shown in FIG. 3 except that the electrode 504 is
in electrical contact with the N+ substrate 102. Electrode 502 is
separated from substrate 102 by a dielectric layer 506 having a defined
thickness. Capacitor 50 has a capacitance value per unit area similar to
that of capacitor 10 shown in FIG. 1. However, the lateral placement of
electrodes 502 and 504 leads to a larger effective series resistance
(ESR) which is a function of the lateral dimension of the device.

[0051]FIG. 6 is a top view of a capacitor 60 in which the first electrode
602 has fingers 602a-602c that are interdigitated with fingers 604a-604d
of the second electrode 604. FIG. 7 is a cross-sectional view taken at
cross-section 7-7 shown in FIG. 6 (note that the scales of FIGS. 6 and 7
are not the same). In an active region 606, where the fingers are
interdigitated, a thin dielectric layer 618 is formed over the substrate.
A relatively thick dielectric layer 614 separates the remaining "palm"
portion of electrode 602 from N+ substrate 102, and a relatively thick
dielectric layer 616 separates the palm portion of electrode 604 from
substrate 102.

[0052] The capacitance of capacitor 60 is determined by the number and
dimensions of the fingers. As indicated in FIG. 6, electrode 604 can be
separated from the N+ substrate by a dielectric layer, creating a pair of
capacitors, or it can be in direct electrical contact with the N+
substrate (in the manner of electrode 504 in FIG. 5), creating a single
capacitor. In many embodiments, the pitch "p" of the finger layout will
be less than 300 μm. For example, a capacitor 60 wherein electrode 604
is in direct electrical contact with the substrate and the pitch of the
interdigitated fingers is 250 μm (finger width of 200 μm, spacing
of 50 μm) and the thin dielectric layer 618 is a 0.1 μm-thick oxide
layer, has a capacitance of 150 pF/mm2 and an ESR of 12
mΩmm2.

[0053] The thin dielectric layers used in precision capacitors make these
devices very susceptible to damage from electrostatic discharges (ESDs).
For example, ESDs can be generated by handling during the assembly
process. One way to protect against ESDs is to connect a pair of
oppositely-directed Zener diodes D1, D2 in parallel with the capacitor,
as shown in the circuit diagram of FIG. 8. When an ESD voltage spike
occurs, one of the diodes conducts in the forward direction and the other
diode breaks down at a predetermined voltage and conducts in the reverse
direction, thereby providing a current path around the capacitor. The
voltage at which current flows in the protective path is equal to the
reverse breakdown voltage of one diode plus the voltage at which the
other diode conducts in the forward direction (typically about 0.5 V).
(As used herein, the term "oppositely-directed" means that the diodes are
connected in series with either their anodes facing each other or their
cathodes facing each other, such that any current in the series path
flows through one of the diodes in the forward direction and through the
other diode in the reverse direction.)

[0054] In accordance with an aspect of this invention, the protective
diodes can be formed in the substrate itself, as shown in the
ESD-protected capacitor arrangement of FIG. 9. An N+ region 902, a P
region 904 and an N+ region 906 are formed in substrate 102 beneath
electrode 106. The regions are formed such that there is a first PN
junction between N+ region 902 and P region 904 that represents one of
the diodes and a second PN junction between P region 904 and N+ region
906 that represents the other diode. The doping concentrations of regions
902, 904 and 906 are set such that the PN junctions break down in the
reverse direction at a desired voltage. The breakdown voltage depends on
the doping concentration on the more lightly doped side of the PN
junction and other factors that are well-known in the art. See, for
example, Sze, Physics of Semiconductor Devices, 2nd Ed., John Wiley
& Sons (1981), pp. 99 108, which is incorporated herein by reference.

[0055] The second N+ region 906, which extends into the P region 904 as
well as the N+ substrate, is used to provide a symmetrical breakdown
characteristic of the diode pair. In some embodiments, N+ region 906 may
be omitted.

[0056] To maintain the high RF performance capabilities of the capacitor,
the impedance of the Zener diodes can be set at a level that is higher
than the capacitor by a factor of 1000 or more.

[0057] Processes for forming the diodes in the substrate are well known to
those skilled in the art. One such process is as follows:

[0058] 1. Initially, an N-type epitaxial (epi) layer that is 2.5 μm
thick is formed on the top surface of the substrate. The doping
concentration of the epi layer is 1×1016 cm-3, far less
than that of the underlying portion of the substrate.

[0059] 2. A first photoresist mask with an opening defining the active
area where the capacitor will be located is formed over the epi layer,
and phosphorus is implanted through the opening in the mask at a dose of
8×1015 cm-2 and an energy of 80 keV to set the doping
concentration of the epi layer to approximately the same level as the
rest of the N+ substrate (1019 cm-3). The first mask is then
removed.

[0060] 3. After the phosphorus implant into the active area through the
first mask, another mask is formed over the substrate with an opening
defining where P region 904 will be located. Boron is implanted through
the opening in this mask, for example, at a dose of 2×1013
cm-2 and an energy of 80 keV, to form P region 904.

[0061] 4. The substrate is annealed at 1150° C. for 30 minutes to
drive the phosphorus and boron implants through the epi layer.

[0062] 5. The oxide dielectric layer 104 is thermally grown as described
above.

[0063] 6. After the oxide layer has been grown, a third photoresist mask
is formed on the oxide layer and patterned to create openings which
define the N+ regions 902 and 906.

[0064] 7. The oxide layer is partially etched through the openings in the
third photoresist mask to avoid the need to implant dopant through a
thick oxide film.

[0065] 8. Phosphorus is then implanted through the openings in the third
mask and the thinned oxide layer at, for example, a dose of
3×1015 cm-2 and an energy of 60 keV to form N+ regions
902 and 906.

[0066] 9. The third photoresist mask is removed, and a blanket boron
implant is performed through the oxide layer to set a surface doping of
the P-well. This can be done, for example, at a dose of 3×1012
cm-2 and an energy of 60 keV. The boron dopant can be activated by
annealing at 950° C. for 30 minutes in an oxidizing ambient.

[0067] 10. A fourth photoresist mask is formed and patterned with an
opening over the area where contact is to be made to the N+ region 902.
The oxide layer is etched through the opening to expose N+ region 902.
The fourth mask is then removed.

[0068] Following this, the process described above continues with the
formation of the electrodes 106 and 108.

[0073] FIG. 10a shows the IV characteristic of the structure with
electrode 106 biased positive with respect to electrode 114
("accumulation bias"), and FIG. 10b shows the IV characteristic of the
structure with electrode 106 biased negative with respect to electrode
114 ("depletion bias"). As indicated, the diode pair breaks down in the
range of 16-19 V in either direction. FIG. 11 shows that the effective
capacitance of the combined capacitor and ESD-structure remains quite
constant at about 0.15 pF throughout the frequency range from 0.1 to 10
GHz.

[0074] The embodiments of this invention described above are only
illustrative, and not limiting. Numerous alternative embodiments will be
apparent to persons skilled in the art from the above description.