DDR3L Termination Voltage!

While going through a reference schematic of T1042, i found that some pins of DDR3L have been terminated with a voltage (VTT). I am unable to understand why is this termination needed? Moreover, the datasheet of the SDRAM device also shows a resistor (RTT) attached to the DQS and DQS# pins. Can anybody explain the reason? Thank you!

Roughly the DDR3 input is like half of a differential input, when the second input of differential pair is connected to reference voltage (VREF). So there is VREF pin on DDR3 which requires a voltage level VREF= VDDQ/2. Where VDDQ is DDR3 i/o buffers power voltage. At higher frequencies, PCB traces can no longer be treated as just wires used to connect digital components together— they become radio frequency (RF) transmission lines. Specifically, it is assumed that on-die termination is used for the data groups and that external parallel resistors tied to VTT are used for the address/CMD and control groups, where VTT is the same as VREF. See more details for example in Micron application note “TN-41-13: DDR3 Point-to-Point Design Support Introduction”.