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The Wishbone serializer core helps to solve the problem of accessing a Wishbone slave in one Xilinx Spartan 6 FPGA from a Wishbone master in another Spartan 6 in a transparent way. Both FPGAs are connected by two Xilinx Gb serial links, one in each direction. In order to cope with the high latency and still maintain a good throughput, Wishbone pipelined access mode is used. The main usage would be for use on the VFC VME FMC carrier board.