Hello!
Can you help me please.
I am a student and i have some problems with one task.
I had to write a program for an embedded system which will have 8 buttons and will show on 7-segment display the number of the button pressed last.
I wrote the program but the teacher said that i must use external interrupts and that i can't use polling.I can't quite figure out what should i do next and how to fix my code so that it will fit the teachers demands.
Here is the code that i wrote and the scheme in proteus.
Thanks in advance,hope you can help me.

Tell me how you think an interrupt works on an 8051 architecture part. Then we can talk about how you might use one to solve your problem.

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I think when a specific event happens the interrupt occurs ,executes a subroutine, and then it returns to the main program execution.I also know that an interrupt can be caused by :Timer 0 Overflow,Timer 1 Overflow,Reception/Transmission of Serial Character,External Event 0 or External Event 1.
I just don't understand how to implement this in my task ...

Well that is a start. Look at the description in the datasheet and see if you can understand the difference between an edge-triggered interrupt and a level triggered interrupt. Interrupts have to be configured and they have to be enabled. There is also a global interrupt enable that must be dealt with. In the 8051 architecture there are also two priority levels to deal with.

Lastly you must find and understand the mechanism that connects an absolute address in low program memory to the interrupt subroutine and you have to tell the C compiler to treat the interrupt subroutine differently by using a return from interrupt instead of a standard return instruction. If you have not done so already you need to get your compiler to give you an assembly listing of the compiled code. That way you can check these little details. As you have already noted things are not working and they are not working because you have not dug into the documentation deeply enough. It might help if you did the assignment in assembly language, then you'd know what to look for in the compiler generated code.

What you currently know is obviously not good enough to solve the problem. I've given you a large number of clues. Are you telling me you cannot read the datasheet and the applications notes in such a way as to make progress on the problem? Of course I could do everything for you, but then you wouldn't learn anything. I would rather have you struggle and learn something.

So we have hardware in the 8051 that recognizes the presence of an interrupt. Let's take External Interrupt 0. When the hardware detects External Interrupt 0 it sets a flag (a bit in a register), it saves the program counter on the stack, and the next instruction is fetched from an absolute location in the lowest page of Program Memory.

Q: What absolute location in the lowest page of Program Memory does the processor fetch an instruction from when External Interrupt 0 is recognized? Express the value in hexidecimal notation.
A:

Q: What absolute location in the lowest page of Program Memory does the processor fetch an instruction from when it comes out of RESET? Express the value in hexidecimal notation.
A:

What you currently know is obviously not good enough to solve the problem. I've given you a large number of clues. Are you telling me you cannot read the datasheet and the applications notes in such a way as to make progress on the problem? Of course I could do everything for you, but then you wouldn't learn anything. I would rather have you struggle and learn something.

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Please do it for me! I promise i will learn it after that, i need it for tomorrow, could you please do it for me, if you can. It will take a lot of time to understand this, but i promise to make effort for understanding all what you came up. Thx in advance

Papa I am somewhat curious about the 8 buttons/triggers. I just checked my 8051 textbook (from my uC class) and 8051 has two external hardware interrupts. So, for example, I can use External Hardware Interrupt 1 to with Button 1, I can use External Hardware Interrupt 2 with Button 2. What do I use for Buttons 3-8?

The schematic shows exactly that: it seems that everything hardware is in place.

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I don't think it does. Maybe I'm missing something. Are you talking about the port line that is connected to the diodes and a pulldown resistor? I thought that was to pull up all of the lines except the one that is grounded when the port pin was high. 8051 pins won't source much current, they are not true CMOS outputs. I can't tell from the unreadable diagram which port pin it is connected to. Is it Port 2.2?

Papabravo, bravo on enlightening this soon to be engineer (or not) on the value of hard work and digging in to a problem.

I am currently working with a software engineer that was afraid to dig in and figure out why his software wasn't communicating properly over a USB/RS232... I ended up doing the work for him because I didn't have time to argue with him. I'm smarter now... Turns out his software wasn't sending a 'ready to send' command.

I don't think it does. Maybe I'm missing something. Are you talking about the port line that is connected to the diodes and a pulldown resistor? I thought that was to pull up all of the lines except the one that is grounded when the port pin was high. 8051 pins won't source much current, they are not true CMOS outputs. I can't tell from the unreadable diagram which port pin it is connected to. Is it Port 2.2?

I still want to know where interrupt 0 goes. How's about it.

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Quite true: the schematic is maddeningly indistinct, but the diodes seem to be tied to INT0, and they will pull that pin down via R15? ( assuming the symbol to which R15? connects is VCC.)

Quite true: the schematic is maddeningly indistinct, but the diodes seem to be tied to INT0, and they will pull that pin down via R15? ( assuming the symbol to which R15? connects is VCC.)

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It actually looks like ground, but maybe not. We know that ports 1, 2, and 3 have internal weak pullups due the design of the "quasi-bi-directional" ports of the architecture. In any case one diode drop above ground is not exactly a well defined logic low. As you also know the "quasi-bi-directional" port structure of the 8051 is really really bad at sourcing current into a pulldown. There is also the matter of using a mechanical switch on a negative edge triggered interrupt without some debouncing. You can do it in the firmware but you have to be aware of the problem.

What is the semantic meaning of the trailing 0 in the following declaration?

Code (Text):

void external0_isr(void) interrupt 0

In some compilers (IAR), it should be the address of the interrupt vector. As we know 0 is the RESET Vector.

I still can't see confirmation that the interrupt ISR is correctly linked to the proper location in page 0 of Code Memory.