I'm trying to make a type 2 phase detector for a PLL circuit (see attachment). In this PLL, the VCO is external, and the PSOC will control it by a single control voltage through the VDAC (but it could also be a PWM).

I'm looking for a kind of "accumulator", or up/down counter, that will control the VDAC's output voltage. Normally, lines Qa and Qb are both low (this represents a locked phase condition, which is what we ultimately want).

--> I want a condition, where:

if there are pulses on the Qa line, then VDAC should increase its output.

if there are pulses on the Qb line, then VDAC should decrease its output

if there are no pulses, then VDAC should keep using its "last" value

Is there such an accumulator/counter in PSOC? I see counters, but I don't see an up/down counter.

My frequency range is 59-61Hz (for a standard 60Hz US outlet, which doesn't vary in frequency very much at all).

My VCO is using two Analog Devices multipliers AD633 (in their datasheet, one of the examples is making a voltage controlled quadrature oscillator). This oscillator generates two sinusoidal waveforms that are 90 degrees apart. The control range is something like 0 - 10Vin gives you 0 - 1000Hz frequency in the output, which is WAY more than I need.

--> Ultimately, I'm trying to make a single-phase dq transform circuit (I.E. a park transform circuit), for use in an AC-DC power electronics circuit. Having both in-phase and quadrature sinusoids, both phase-locked to the 60Hz wall frequency, are needed for this d-q transform.

I have 60Hz type-2 analog PLL all made inside PSoC (plus a couple of capacitors and resistors). I believe that generating quadrature sine outputs is also feasible within PSoC chip. Attached are type-II phase-frequency detector (PFD), loaded to RC filter. The output of the filter directed to a VCO (using Delta-Sigma Modulator inside the PSoC). It was tested and locks in approx. 30-150Hz range. I will dust-of the PLL demo project and post it. Meanwhile attached are screenshots from the project. The filter is most tricky part of PLL, as those combinations of Caps and Resistors are designed to provide a "phase margin" (aka friction) in the loop - otherwise loop will not settle and continue to oscillate around lock frequency.

This is a PERFECT solution - thank you odissey1! I never thought to use an IDAC and a capacitor, but it makes perfect sense, as the capacitor will hold the previous value if there is no need for the IDAC to adjust the frequency.

I'm looking into the SC_Modulator component now (I see that it's a shared community component). THANK YOU for sharing a perfect solution!

UPDATE - I think it works! So far, I've used a function generator to sweep ~55Hz to 65Hz, and the waveforms look good!

--> A question: If you look at the two attached waveforms, there is a slight phase offset between the two waveforms that is dependant on frequency. The 57.6Hz waveform has almost none, but the 61.1Hz waveform has a little bit. Theoretically, I'd expect none because this is a type-II PLL. Any ideas as to what could be causing this?

I suggest to add OpAmp buffer between LPF and VCO, it seems that the Modulator has low input impedance, ~20k, which is loading LPF. Also check if LPF is properly tuned by observing output of LPF on scope while jumping input frequency between two adjacent frequencies (e.g. 50Hz - 70Hz). Particularly important R_2, which creates dumping, use ~10k trimpot to find value when transition looks like on screenshot below. Attached are screenshots of the PLL properly tuned, and LPF output shows critically dumped transition (no high frequency oscillations).