Designers can take advantage of high speed, accuracy and capacity for signal integrity, power integrity and EMI concerns – all from within a common interface. The Full-Wave Solver is built from the ground up to exploit multi-core and hybrid architectures, and to utilize the best of fast solver technology to enable fast simulation on a single core or multiple cores.

Power-aware SI trace model extraction can be performed, as well as DC and AC power integrity analysis at the system (package/PCB) level. Designers can benefit from a power delivery network impedance profile, capacitor loop inductance, and combined signal and power broadband S-parameter extraction for use in time-domain simulation – all within a common, easy-to-use interface.

Parallelization Methodology

This paper discusses the parallelization strategy.

Built upon a two-layer foundation, the strategy includes: (a) fine-grained, multi-threaded solver architectures for the multicore environment (b) coarse-grained, distributed architectures for multiple processors connected by high-speed buses is summarized. This parallelization methodology is tuned to simultaneously exploit the proprietary fast solver technology and to take advantage of emerging multicore and many-core processors.