Designing With ARM—The Wrap-up

Last week I co-chaired an EE Times virtual conference Designing with ARM: Engineering an Optimal ARM-Based System along with Rich Nass. This was my first experience with the format, and I went into it skeptical but with an open mind. Is this an effective way to convey information? Can it attract and hold an engineering audience’s attention? Is this the future of trade shows, or will it have the lifespan of a fruit fly? During the show I lost my skepticism and gained some perspective. These things definitely work.

By any measure the conference was a success: 1,304 people attended, with 555 attending the Low-Power Design panel and 447 catching the Software, Tools & Operating Systems panel. This is certainly testimony to the quality of the speakers but more broadly to the breadth of the ARM designer community and their eagerness to hear and share insights that will help with their next ARM-based design. In that regard they weren’t disappointed.

Over a period of several hours the panels, webinars, chats and vendor pavilions delivered, frankly, more information than I could absorb—and all without any of us getting sore feet. [Full disclosure: I did miss the free beer at 5 o’clock.]

The Low-Power Design panelists—from Cadence, Synopsys, National Semiconductor and TI—all agreed with ARM’s CTO Mike Muller’s assertion in his keynote that silicon-on-insulator (SoI) looks very promising, especially now that an ecosystem is forming and the process price is falling. The panelists from Cadence and Synopsys concurred that the differences between CPF and UPF are by now fairly trivial, the remaining challenge being to integrate power awareness farther up the toolchain past RTL. National and TI detailed their different approaches to power management, though both agreed that power-aware software—from the application to the compiler level—are where system designers now need to focus their attention. Synopsys has indicated that they’re taking that tack with their recent acquisition of CoWare, who have long been focused on system-level design.

The New Frontiers for ARM Cores panelists—from ARM, NXP, Cypress and the SoI Consortium—discussed ARM’s forays into both the low-end, 8-bit MCU market and high-end, high-speed 32-bit applications. ARM claims that its 32-bit Thumb-2 compiled code is both smaller and faster than that for 8-bit microcontrollers, most of which are 20-year-old designs; and that working at smaller geometries provides a cost advantage over older processes. On the high end the panelists all expect to see multicore become almost ubiquitous, though the silicon is moving faster than the tools required to program it. They also agreed that programmable hardware has a role to play going forward, whether that includes dropping processors and peripherals into an FPGA for low- to mid-volume production or including a programmable fabric in an SOC.

The Software, Tools and Operating Systems panelists—from ExpressLogic, Mentor Graphics, CoWare, and Green Hills Software—took direct aim at the software part of the design equation. The participants—admittedly all RTOS vendors—insisted that all but the smallest 8-bit applications require an operating system, which relieves the developer of low-level coding, thereby reducing complexity, not adding to it. The panelists took some heat about needing better tools—on which they are diligently working—but they also pointed out that some of the “software problem” is self-inflicted, since designers often don’t consider test and debug until they are too far into the design process. The number of corner cases you need to test and verify in today’s highly complex embedded systems has grown geometrically in recent years, placing a considerable burden on both designers and their tool vendors.

In a separate webinar titled Cracking the Multi-layer Design Code, Sonics detailed how to cost-effectively simplify and optimize an AMBA-based design. Sonics takes an on-chip network approach to solving the knotty problem of communicating between multiple cores in a complex SoC. If your design is still based on the AHB bus, migrating from a multi-layer to a concurrent AHB design can address the routability and scaling issues inherent in the older approach. Sonics also detailed the conversion steps to take if you’re moving up to an AMBA-based design.

Three scheduled chats provided some lively feedback, not to mention entertainment:

Is ARM’s Cortex-A8 an Atom Smasher? dived right into the collision between ARM and Intel in the netbook space and beyond. ARM is the likely winner, but it won’t happen overnight.

Why is One ARM Different from Any Other? sought to sort out the large number of permutations of ARM products and their intended applications. Even developers have trouble keeping up.

Get Ready for SoI highlighted the limitations of bulk CMOS at smaller line widths and the power-saving advantages of SoI. The SoI Consortium is assembling an ecosystem of fabs, hardware and tool vendors to help move SoI into the mainstream.

Finally the vendor booths on the (virtual) pavilion floor provided an opportunity to chat with vendor reps and ask their FAEs to help solve your design problems. I did my usual routine and grabbed all the brochures and white papers in sight, only this time I didn’t have to FedEx them back to my office.

I’d briefly attended one of these virtual conferences before, but this is the first time I’ve been actively involved as a co-chair. Being on a virtual panel felt exactly like being on a live one, I just couldn’t see the panelists’ faces. The volume of information was as high as at any live trade show, but the decibel level was considerably more comfortable. While I still miss the “free beer at 5:00,” from the attendee’s standpoint I think these things are a low-impact (on your time), high-value proposition that nicely supplements—though won’t replace—live trade shows. If you haven’t attended a virtual conference, I recommend you check one out.