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Relationships are shown for a fully interconnect network with as many inputs as neurons, a three layer MLP with a layer ratio of 7:2:1, a three layer MLP with a layer ratio of 45:45:10, a three layer MLP with a layer ratio of 3:3:3, and nlog(n). Assuming that a speed requirement for a computation is specified, and a circuit design for that computation exists, the question then is how to minimise the power consumption. As power is proportional to the square of voltage the obvious strategy is to reduce the power rail as much as possible.

Unfortunately, the result is not an infinite gain, since the devices enter weak inversion mode and the model changes. The gain expression also shows a gain dependence on the W / L ratio, though the dependence is weak. 19) is used. 25) This simple circuit has a useful gain, as the following numerical example shows. The quiescent current in the transition region depends on the supply voltage and the transistor geometry. Let us take (WI L) = 10 for MI and (WI L) = 30 for M 2 . This will match the gm values of the two transistors.

This delay obviously increases with word length, but typically is in the 100 - 200ns range and suits sample rates in the MHz range. The penalty paid is in complexity. A resistor on a chip usually occupies more area than a transistor and area increases with resistance, so that the technique is not suited to micropower design. A final advantage worth noting is that this DAC is inherently monotonic. 19 One-step resistor string DAC. rors in individual levels, the structure guarantees that the output for a code of 100, say, is greater than the voltage for 011.