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- (Xilinx Answer 32316) If 16-bit Device IDs are used, treq_vld_n can assert before treq_sof_n on an SWRITE

- Version to be fixed: Fix Not Scheduled

- CR# 514611

- (Xilinx Answer 30023) Virtex-4, Virtex-5 LXT/SXT, and Virtex-5 FXT core configurations are unable to train down to x1 mode in Lane 2. Traindown in Lane 0 works successfully, but the Virtex-4, Virtex-5 LXT/SXT, and Virtex-5 FXT configurations are unable to Traindown in Lane 2. The RocketIO transceivers only allow Traindown to the channel bonding master.

- Version to be fixed: Fix Not Scheduled

- CR# 457109.

- (Xilinx Answer 30021) Core reinitialization during error recovery causes recoverable protocol error. This is a corner condition that could occur if the core is forced to reinitialize (i.e., - force_reinit) while it is in the process of error recovery. If this condition occurs, packets will be sent during recovery's quiet period. This situation is recoverable.

- (Xilinx Answer 24982) PNA cause field might occasionally reflect a reserved value. The cause field is for debug purposes only and will not affect functionality. Occurrence is rare and requires alignment of multiple control symbols.

- Version to be fixed: Fix Not Scheduled

- CR# 436767

(Xilinx Answer 24970) Control Symbols might be lost on reinit. This is an unusual and ultimately recoverable error. Set the Additional Link Request Before Fatal value on the Physical Configuration page of the GUI to "4" in order to prevent a lost Link Request or Link Response from causing the core to enter the port error state.

- Version to be fixed: Fix Not Scheduled

- CR# 436768

(Xilinx Answer 24968) Logical Rx does not support core side stalls. The Rx buffer must provide packets to the logical layer without buffer induced stall cycles. The buffer reference design provided with the core is a store and forward buffer and complies with this rule.