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AR# 33127

Description

Known Issue: v1.4, v1.3, v1.2, v1.1

When I generate the Virtex-6 FPGA Integrated Block Wrapper for PCI Express, the created UCF is incorrect when the ML605 is selected on Page 9 of the GUI. Specifically, if I target the XC6VLX240T-FF1156-1 part and select a 100 MHz or 250 MHz Reference Clock on Page 11 of the GUI, the clock buffer and pins for sys_clk are incorrectly placed, as follows: