Spi slave mode problem

I have communication problem with the spi bus on IMX6 processor.My goal is to configure a spi line of the IMX6 processor in slave mode.From the tests carried out by me, this configuration only works if the number of bytes to be sent to the slave line is equal to 8.In this case the test involves sending to the slave line a pattern of 8 bytes so preset:byte 1 = 1bytes 2 = 2byte 3 = 3bytes 4 = 4byte 5 = 5bytes 6 = 6bytes 7 = 7bytes 7 = 8The data received on the slave side correspond to those mentioned above.The registers slave side are configured as follows:CONREG register value is 3f03001 slaveCONFIGREG register value is f00055 slave

In the second case with a number of bytes to be sent (from spi master device to spi imx6 slave device) is to equal to 16 with the following pattern,byte 1 = 1bytes 2 = 2byte 3 = 3bytes 4 = 4byte 5 = 5bytes 6 = 6bytes 7 = 7bytes 8 = 8byte 9 = 9bytes 10 = 10bytes 11 = 11byte 12 = 12bytes 13 = 13byte 14 = 14byte 15 = 15bytes 16 = 16The result obtained on the slave side (first run) is as follows:o_rx_data1 of 0 is 0o_rx_data1 of 1 is 0o_rx_data1 of 2 is 0o_rx_data1 of 3 is 0o_rx_data1 of 4 is 0o_rx_data1 of 5 is 2co_rx_data1 of 6 is 3o_rx_data1 of 7 is ffo_rx_data1 of 8 is 1o_rx_data1 of 9 is 2o_rx_data1 of 10 is 3o_rx_data1 of 11 is 4o_rx_data1 of 12 is 5o_rx_data1 of 13 is 6o_rx_data1 of 14 is 7o_rx_data1 of 15 is 8

The registers are configured as follows:CONREG register value is 7f03001 slaveCONFIGREG register value is f00055 slave

The result obtained on the slave side (at second run first run) is as follows:

o_rx_data1 of 0 is 9o_rx_data1 of 1 is 10o_rx_data1 of 2 is 11o_rx_data1 of 3 is 12o_rx_data1 of 4 is 13o_rx_data1 of 5 is 14o_rx_data1 of 6 is 15o_rx_data1 of 7 is 16o_rx_data1 of 8 is 1o_rx_data1 of 9 is 2o_rx_data1 of 10 is 3o_rx_data1 of 11 is 4o_rx_data1 of 12 is 5o_rx_data1 of 13 is 6o_rx_data1 of 14 is 7o_rx_data1 of 15 is 8

The registers are configured as follows:CONREG register value is 7f03001 slaveCONFIGREG register value is f00055 slave

Attached there are also two paint files where the signals of the spi lines are recorded, both in the positive and in the negative case.Thank you for your cooperation,

"Following HW limitation applies:1. ECSPI has a HW issue when works in Slave mode, after 64 words written to TXFIFO, even TXFIFO becomes empty, ECSPI_TXDATA keeps shift out the last word data, so we have to disable ECSPI when in slave mode after the transfer completes2. Due to Freescale errata ERR003775 "eCSPI: Burst completion by Chip Select (SS) signal in Slave mode is not functional" burst size must be set exactly to the size of the transfer. This limit SPI transaction with maximum 2^12 bits."