Have critical functions been identified (by FMECA) which require
monitoring for the system operation and users?

Have interface standards been established that ensure the electronic
transmission of data from monitored systems is compatible with centralized
monitors?

Has the displayed output of the monitoring system received a human
engineering analysis to ensure that the user is supplied with the required
information in the best useable form?

RF Design Checklist

Do transmitter outputs have directional couplers or similar signal
sensing/attenuation techniques employed for BIT or off-line test
monitoring purposes, or both?

Has provision been made in the off-line ATE to provide switching of
all RF stimulus and response signals required to test the subject RF UUT?

Are the RF test input/output access ports of the UUT mechanically
compatible with the off-line ATE I/O ports?

Have adequate testability (controllability/ observability) provisions
for calibrating the UUT been provided?

If an RF transmitter is to be tested utilizing off-line ATE, has
suitable test fixturing (anechoic chamber) been designed to safely test
the subject item over its specified performance range of frequency and
power?

Have all RF testing parameters and quantitative requirements for these
parameters been explicitly stated at the RF UUT interface for each RF
stimulus/ response signal to be tested?

Has the UUT/ATE RF interface been designed so that the system operator
can quickly and easily connect and disconnect the UUT without special
tooling?

Have RF compensation procedures and data bases been established to
provide calibration of all stimulus signals to be applied and all response
signals to be measured by BIT or off-line ATE to the RF UUT interface?

Have suitable termination devices been employed in the off-line ATE or
BIT circuitry to accurately emulate the loading requirements for all RF
signals to be tested?

Does the RF UUT employ signal frequencies or power levels in excess of
the core ATE stimulus/ measurement capability? If so, are signal
converters employed within the ATE to render the ATE/UUT compatible?

Has the RF UUT been designed so that repair or replacement of any
assembly or subassembly can be accomplished without major disassembly of
the unit?

Does the off-line ATE or BIT diagnostic software provide for
compensation of UUT output power and adjustment of input power, so that RF
switching and cable errors are compensated for in the measurement
data?

Electro-optical (EO) Design
Checklist

Have optical splitters/couplers been incorporated to provide signal
accessibility without major disassembly?

Has temperature stability been incorporated into fixture/UUT design to
assure consistent performance over a normal range of operating
environments?

Have optical systems been functionally allocated so that they and
associated drive electronics can be independently tested?

Are the ATE system, light sources, and monitoring systems of
sufficient wave-length to allow operation over a wide range of UUTs?

Does the test fixturing intended for the off-line test present the
required mechanical stability?

Is there sufficient mechanical stability and controllability to obtain
accurate optical registration?

Can requirements for boresighting be automated or
eliminated?

Do monitors possess sufficient sensitivity to accommodate a wide range
of intensities?

Can optical elements be accessed without major disassembly or
realignment?

Do they possess sufficient range of motion to meet a variety of test
applications?

Has adequate filtering been incorporated to provide required light
attenuation?

Can all modulation models be simulated, stimulated, and monitored?

Can targets be automatically controlled for focus and aperture
presentation?

Do light sources provide enough dynamics over the operating range?

Do test routines and internal memories test pixels for shades of gray?

Are optical collimators adjustable over their range of motion via
automation?

Digital Design Checklist

Does the design contain only synchronous logic?

Does the design avoid resistance capacitance oneshots and dependence
upon logic delays to generate timing pulses?

Is the design free of WIRED-ORs?

Will the selection of an unused address result in a well defined error
state?

Are all clocks of differing phases and frequencies derived from a
single master clock?

Is the number of fan-outs for each board output limited to a
predetermined value? Are latches provided at the inputs to a board in
those cases where tester input skew could be a problem?

For multilayer boards, is the layout of each major bus such that
current probes or other techniques may be used for fault isolation beyond
the node?

If the design incorporates a structured testability design technique
(scan path, signature analysis), are all the design rules satisfied?

Is the number of fan-outs for each internal circuit limited to a
predetermined value?

Are all memory elements clocked by a derivative of the master
clock? (Avoid elements clocked by data from other elements.)

Does the design include data wrap-around circuitry at major
interfaces?

Is a known output defined for every word in a read only memory?

Are sockets provided for microprocessors and other complex components?

Does the design support testing of “bit slices”?

Do all buses have a default value when unselected?

Diagnostic Capability
Integration

Have vertical testability concepts been established, employed, and
documented?

Has the diagnostic strategy (dependency charts, logic diagrams) been
documented?

Has a means been established to ensure compatibility of testing
resources with other diagnostic resources at each level of maintenance
(technical information, personnel, and training)?

Mechanical Systems Condition
Monitoring (MSCM) Checklist

Have MSCM and battle damage monitoring functions been integrated with
other performance monitoring functions?

Are pressure sensors placed
very close to pressure sensing points to obtain wideband dynamic
data?

Has the selection of sensors taken
into account the environmental conditions under which they will
operate?

Have procedures for calibration of sensing devices been established?

Has the thermal lag between the test media and sensing elements been
considered?

Test Requirements Checklist

Has a “level of repair analysis” been accomplished?

For each maintenance level, has a decision been made for each item on
how BIT, ATE, and General Purpose Electronic Test Equipment (GPETE), will
support fault detection and isolation?

For each item, does the planned degree of testability design support
the level of repair, test mix, and degree of automation decisions?

Is the planned degree of test automation consistent with the
capabilities of the maintenance technician?

Built-in-Test (BIT) Checklist

Can BIT in each item be exercised under control of the test equipment?

Does the BIT use a building-block approach (all inputs to a function
are verified before that function is tested)?

Does on-board ROM contain self-test routines?

Does BIT include a method of saving on-line test data for the analysis
of intermittent failures and operational failures which are non-repeatable
in the maintenance environment?

Is the additional volume due to BIT within stated constraints?

Does the allocation of BIT capability to each item reflect the
relative failure rate of the items and the criticality of the items’
functions?

Are the data provided by BIT tailored to the differing needs of the
system operator and the system maintainer?

Is sufficient memory allocated for confidence tests and diagnostic
software?

Are BIT threshold limits for each parameter determined as a result of
considering each parameter’s distribution statistics, the BIT measurement
error and the optimum fault detection/false alarm characteristics?

Is BIT optimally allocated in hardware, software, and firmware?

Have means been established to identify whether hardware or software
has caused a failure indication?

Is the failure latency associated with a particular implementation of
BIT consistent with the criticality of the function being monitored?

Is the test program set designed to take advantage of BIT
capabilities?

Does building-block BIT make maximum use of mission circuitry?

Is the self-test circuitry designed to be testable?

Is the predicted failure rate contribution of the BIT circuitry within
stated constraints?

Is the additional power consumption due to BIT within stated
constraints?

Are BIT threshold values, which may require changing as a result of
operational experience, incorporated in software or easily-modified
firmware?

Are on-board BIT indicators used for important functions? Are BIT
indicators designed such that a BIT failure will give a “fail” indication?

Is the additional weight due to BIT within stated constraints?

Is the additional part count due to BIT within stated constraints?

Is processing or filtering of BIT sensor data performed to minimize
BIT false alarms?