Sign up to receive free email alerts when patent applications with chosen keywords are publishedSIGN UP

Abstract:

Described examples include sensing circuits and reference voltage
generators for providing a reference voltage to a sensing circuit. The
sensing circuits may sense a state of a memory cell, which may be a PCM
memory cell. The sensing circuits may include a cascode transistor.
Examples of reference voltage generators may include a global reference
voltage generator coupled to multiple bank reference voltage generators
which may reduce an output resistance of the voltage generator routing.

Claims:

1. A sensing circuit comprising: a pre-sense circuit comprising: a first
leg configured to couple to a memory cell, wherein the first leg includes
a first transistor connected in a cascode configuration and configured to
provide a first current based, at least in part, on a state of the memory
cell; a second leg, wherein the second leg includes a second transistor
connected in a cascode configuration and configured to provide a second
current; a first output coupled to the first leg and configured to
provide a first voltage based, at least in part, on the first current; a
second output coupled to the second leg and configured to provide a
second voltage based, at least in part, on the second current; and a
comparator having inputs coupled to the first and second outputs, wherein
the comparator is configured to provide an output signal based on a
comparison of the first and second voltages.

2. The sensing circuit of claim 1, wherein the pre-sense circuit is
configured for operation in a first power domain, and the comparator is
configured for operation in a second, lower voltage, power domain.

3. The sensing circuit of claim 1, wherein the first and second
transistors are bipolar junction transistors.

4. The sensing circuit of claim 1, wherein the first and second
transistors are configured to receive a reference voltage at their
respective gates.

5. The sensing circuit of claim 1, further comprising respective bias
current sources coupled to the first and second legs and configured to
provide bias currents in the first and second legs.

6. The sensing circuit of claim 1, further comprising a dummy data line
coupled to the second leg, wherein the dummy data line is configured to
match a capacitance provided by the memory cell.

7. The sensing circuit of claim 1, wherein the first and second legs are
configured to ramp up the voltages at the first and second outputs at
substantially a same rate.

9. The sensing circuit of claim 1, further comprising a first capacitive
element coupled between the first output and an input of the comparator
and a second capacitive element coupled between the second output and
another input of the comparator.

10. The sensing circuit of claim 1, wherein the comparator comprises a
pair of cross-coupled inverters.

11. A method for sensing a memory cell, the method comprising: equalizing
a first and second leg of a sensing circuit; ramping up a first output
voltage of the first leg to a voltage based, at least in part, on a state
of the memory cell, wherein said ramping up the first output voltage is
performed, at least in part, by a first transistor in a cascode
configuration; ramping up a second output voltage of the second leg to a
reference voltage, wherein said ramping up the second output voltage is
performed, at least in part, by a second transistor in a cascode
configuration; and comparing the first output voltage and the second
output voltage.

12. The method of claim 11, wherein the first and second transistors
comprise bipolar junction transistors.

13. The method of claim 11, wherein said comparing the first output
voltage and the second output voltage is performed before said ramping up
the first output voltage is finished.

14. The method of claim 11, wherein said comparing the first output
voltage and the second output voltage is performed before said ramping up
the second output voltage is finished.

15. The method of claim 11, wherein said ramping up a first output
voltage and said ramping up a second output voltage occurs at
substantially a same rate.

16. The method of claim 11, wherein said equalizing the first and second
legs comprises closing a switch coupled between the first and second
legs.

17. The method of claim 11, wherein said comparing comprises turning off
switches coupled between the first and second output voltages and a pair
of cross-coupled inverters.

18. A reference voltage generator comprising: a replica circuit
configured to receive a global reference voltage and provide a bank
reference voltage based, at least in part, on the global reference
voltage; and a source follower circuit, wherein the source follower
circuit includes an input coupled to an output of the replica circuit,
and wherein the source follower circuit further includes an output
configured to couple to a sensing circuit.

19. The reference voltage generator of claim 18, further comprising a
resistive element coupled to an input of the replica circuit, wherein the
resistive element is configured to provide the global reference voltage
based, at least in part, on a current received at the resistive element.

20. The reference voltage generator of claim 19, further comprising a
global reference generator configured to provide the current to the
resistive element.

21. The reference voltage generator of claim 19, wherein the sensing
circuit is configured to sense a state of a memory cell, and wherein the
memory cell is configured to be driven by a wordline driver.

22. The reference voltage generator of claim 21, further comprising a
wordline compensation circuit coupled to an input of the replica circuit.

23. The reference voltage generator of claim 22, wherein the wordline
compensation circuit comprises a resistor divider having a resistor ratio
based, at least in part, on resistances of components of the wordline
driver.

24. The reference voltage generator of claim 21, further comprising a
wordline compensation circuit coupled to an output of the replica
circuit.

25. The reference voltage generator of claim 24, wherein the wordline
compensation circuit comprises a capacitive divider having a capacitance
ratio based, at least in part, on resistances of components of the
wordline driver.

26. A memory device comprising: a global reference voltage generator
configured to provide a global reference voltage; a plurality of bank
reference generators, individual ones of the plurality of bank reference
generators positioned proximate a respective bank of memory cells,
wherein the plurality of bank reference generators are coupled to the
global reference voltage generator and configured to provide respective
bank reference voltages; and a respective plurality of driver circuits
coupled to each of the bank reference generators, individual ones of the
plurality of driver circuits configured to provide the bank reference
voltage to a strip of memory cells.

29. The memory device of claim 26, wherein individual ones of the
plurality of driver circuits are configured to provide the bank reference
voltage to sensing circuits in the strip of memory cells.

30. The memory device of claim 26, wherein the plurality of bank
reference generators are distributed throughout the memory device.

Description:

TECHNICAL FIELD

[0001] Embodiments of the invention relate generally to memory, and
include examples of reference voltage generators and circuits and methods
for memory sensing.

BACKGROUND

[0002] Memory devices may be provided as integrated circuits in computers
or other electronic devices. There are many different types of memory
devices, and memory devices may generally be volatile or non-volatile.
Volatile memory may require power to maintain information stored therein,
while non-volatile memory may not lose the stored information in the
absence of power. Examples of volatile memory include DRAM and SDRAM
memory devices. Examples of non-volatile memory include ROM, flash
memory, and resistance variable memory. With increasing popularity of
electronic devices, such as laptop computers, portable digital
assistants, digital cameras, mobile phones, digital audio players, video
game consoles and the like, demand for nonvolatile memories are
considered to be on the rise.

[0003] Examples of resistance variable memory, a type of non-volatile
memory, include phase change memory (PCM) devices. A phase change memory
cell layout may resemble that of a DRAM memory cell, with the DRAM
capacitor being replaced by a phase change material, such as
Germanium-Antimony-Telluride (GST). The phase change material, e.g. GST,
may exist in two states--an amorphous, high resistance state, or a
crystalline, low resistance state. The resistance state of the material
may be altered by applying current pulses to the cell, for example by
heating the material with a programming current. In this manner, a PCM
memory cell may be programmed to a particular resistance state through
use of a programming current. In some examples, the amorphous, high
resistance state of the material in the memory cell may correspond to a
logic state of 1, while the crystalline, low resistance state of the
material in the memory cell may correspond to a logic state of 0. In
other examples, the opposite logic assignments may be used.

[0004] The programmed resistance state of a PCM cell may be determined by
sensing a current and/or voltage associated with the cell. During a
sensing operation, e.g. a read operation, a sensed voltage and/or current
associated with the PCM cell may be compared with one or more reference
voltages and/or currents to determine the particular state of the PCM
cell.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] FIG. 1 is a schematic illustration of a sensing circuit in
accordance with an embodiment of the present invention.

[0006]FIG. 2 is a schematic illustration of a reference voltage generator
scheme in accordance with an embodiment of the present invention.

[0007]FIG. 3 is a schematic illustration of reference voltage routing in
accordance with an embodiment of the present invention.

[0008]FIG. 4 is a schematic illustration of a portion of a memory device
according to an embodiment of the present invention.

DETAILED DESCRIPTION

[0009] Described examples include sensing circuits and reference voltage
generators for providing a reference voltage to a sensing circuit. The
sensing circuits may sense a state of a memory cell, which may be a PCM
memory cell. Certain details are set forth below to provide a sufficient
understanding of embodiments of the invention. However, it will be clear
to one skilled in the art that embodiments of the invention may be
practiced without various of these particular details. In some instances,
well-known circuits, control signals, timing protocols, materials, and
software operations have not been shown in detail in order to avoid
unnecessarily obscuring the described embodiments of the invention.

[0010] Embodiments of the present invention accordingly may provide low
power, fast, and accurate sensing of memory cells. Accurate, fast sensing
may be advantageous in PCM memory devices where sensing may be a limiting
factor in a read path, limiting delay between successive reads. The
available read window may be determined by the PCM technology used, that
is the set and reset capability of the cell itself and the bias voltage
allowed without disturbing the memory cell.

[0011] FIG. 1 is a schematic illustration of a sensing circuit in
accordance with an embodiment of the present invention. The sensing
circuit 100 includes a pre-sense circuit 105 and a comparator 107. The
pre-sense circuit 105 may be in a high voltage power domain, while the
comparator 107 is in a normal Vcc reference voltage domain. The
pre-sense circuit 105 may bias one or more PCM cells 110. The PCM cell
110 is represented by a transistor 102 and variable resistor 103.
Generally, a current based on the state of the one or more memory cells
110 is provided in a leg 111 of the pre-sense circuit 105, while a
reference current is provided in a leg 112 of the pre-sense circuit 105.
A voltage is provided at the nodes 113 and 114 that may be based on the
current in the respective legs. A voltage difference based on the
difference between the current in the legs 111 and 112 is accordingly
provided at an output of the pre-sense circuit 105, e.g. the nodes 113
and 114 in FIG. 1. The nodes 113 and 114 are coupled to inputs of the
comparator 107. The comparator 107 may amplify the voltage difference to
provide (e.g., generate) an output signal SDOUT.

[0012] The pre-sense circuit 105 uses a cascode configuration. The
transistors 120 and 121 are each connected in a cascode configuration to
provide the voltage difference at the nodes 113 and 114. The cascode
configuration generally includes an amplifier stage followed by a current
buffer stage. In FIG. 1, a collector of the cascode transistor 120 is
coupled to a drain of a load transistor 122 to form the cascode
configuration. The emitter of the cascode transistor 120 is coupled to
the memory cell 110 to be sensed. Similarly, a collector of the cascode
transistor 121 is coupled to a drain of a load transistor 123 to form the
cascode configuration. The cascode transistors 120 and 121 receive a
reference voltage, SLVREF at their bases. The cascode transistors 120 and
121 may be implemented as bipolar junction transistors, as shown. The use
of bipolar junction transistors may be advantageous due to the improved
matching characteristics available, such that the transistors 120 and 121
may have improved matching, which may improve the sensing performance of
the sensing circuit 100. For example, because the transistors 120 and 121
are better matched, accurate sensing may be obtained faster in some
examples. Moreover, bipolar junction transistors may generally have a
higher transconductance, Gm, than FETs, which may also improve the
sensing performance of the sensing circuit 100 in some examples. In
particular, the higher Gm may allow for faster settling of a bias to the
PCM memory cells 110.

[0013] Accordingly, bipolar junction transistors may be used in the
cascode configurations described. N-channel BJTs 120 and 121 are shown in
FIG. 1. In other examples, FETs may be used. The load transistors 122 and
123 may be implemented as FET devices. As shown in FIG. 1, p-FETs are
used to implement the load transistors 122 and 123. In other examples,
different configurations of n-channel and p-channel BJTs and FETs may be
used to implement a cascode configuration for use as the pre-sense
amplifier 105.

[0014] The resistance of a PCM cell may change on the order of 100×
between a set and a reset cell. This variation may disrupt the bias
conditions of the pre-sense circuit 105, such as the bias conditions of
the cascode transistors 120 and 121. Accordingly, the pre-sense circuit
105 includes bias current sources 130 and 131. The bias current sources
130 and 131 may be connected to the emitters of the cascode transistors
120 and 121, respectively. The bias current sources 130 and 131 provide a
bias current through the legs 111 and 112 such that the large range of
resistance of the PCM cell 110 may be accommodated. This may enlarge the
available read window in some examples. To illustrate this, in one
example, the PCM cell resistance may change from a resistance in the
kilo-ohm range to a resistance in the mega-ohm range. The resulting
current in the leg 111 may change from nano-amps to micro-amps, 100 nA to
10 μA in one example. If a bias current of 5 μA is provided by the
bias current sources 130 and 131, the difference in voltage at the
emitter of the cascode transistor 120 may be reduced. It may be 5
μA+100 nA in one state and 15 μA in the other state, for example,
only about a 3× variation.

[0015] Isolation transistor 132 may be provided between the memory cell
110 and the cascode transistor 120. A similar isolation transistor 133
may be provided between a dummy bit line 134 and the cascode transistor
121. The isolation transistors 132 and 133 may block the application of
high voltage to the pre-sense circuit during a write operation. The
isolation transistors 132, 133 may generally be thick oxide devices,
while thin oxide devices are used for the sense operation itself.
Decoding transistors 144 are also shown in the leg 111, which may be used
to decode the memory cell 110.

[0016] Transistor 142 has a drain coupled to the drain of the load
transistor 122, and a source coupled to a reference voltage. The
transistor 142 may accordingly serve as a kicker device that may speed up
the settling of the memory cell bias voltage.

[0017] Accordingly, during operation, a current may be developed in the
leg 111 of the pre-sense circuit 105 that corresponds to the state, e.g.
the resistance, of the memory cell 110. The cascode transistor generating
the current receives a reference voltage SLVREF and a bias current 130.
The current corresponding to the state of the memory cell may be
translated into a voltage at the node 113 in part by the transistors 122
and 142. A reference current is provided in the leg 112 for comparison.
The leg 112 accordingly includes components selected to match the
components in the leg 111. A dummy bit line 134 is provided and coupled
to the cascode transistor 121 through other components. The dummy bit
line 134 is provided to match a capacitance provided by the memory cell
110. In this manner, the loading of the lines 111 and 112 may be
substantially equal. The leg 112 further includes transistors 146
configured to match the decoding transistors 144. The leg further
includes an isolation transistor 133 configured to match the isolation
transistor 132. A reference current source 148 is provided and coupled to
the isolation transistor 133. Accordingly, a current will be provided
through the cascode transistor 121 that is based on the current provided
by the reference current source 148. The current through the cascode
transistor 121 may be translated into a voltage at the node 114 in part
by the transistors 123 and 152, which may match the transistors 122 and
142.

[0018] Note that the dummy bit line 134 may allow the leg 112 to be loaded
in substantially the same manner as the leg 111. Accordingly, during a
sensing operation, the voltages at the nodes 113 and 114 may ramp up at
substantially a same rate. In this manner, the comparator 107 may utilize
the voltages at the nodes 113 and 114 at an earlier time than if the
nodes were ramping up at a different rate, and the comparator 107 was
required to wait until the voltages had stabilized. That is, by providing
a same capacitive loading in the leg 112 as the leg 111, a voltage
difference at the nodes 113 and 114 may be reliably sensed earlier. The
two matching legs 111 and 112 may also improve power noise immunity and
reduce an impact of displacement current mismatch in some examples.

[0019] Recall that the pre-sense circuit 105 is provided in a high voltage
power domain. That is, a voltage higher than the reference voltage
Vcc is provided to the legs 111 and 112. In FIG. 1, the higher
reference voltage is shown as VHSENLDR. The higher reference voltage
allows a high bias condition to be provided to the memory cell 110. The
comparator 107, however, operates in a different power domain, with
reference voltage Vcc provided to the comparator 107. In this
manner, thin oxide devices may be used to implement the comparator 107 as
they may not be required to couple to the higher reference voltage. The
lower power supply used by the comparator 107 may also lower the power
consumption of the comparator 107.

[0020] Capacitors 155 and 157 are provided between the outputs of the
pre-sense circuit 105 and the inputs of the comparator 107. The
capacitors 155 and 157 provide isolation from the higher reference
voltage VHSENLDR. The capacitors 155 and 157 may be implemented, for
example, using thick oxide transistors.

[0021] The comparator 107 includes transistors 162 and 164. The
transistors 162 and 164 may be implemented as p-FET transistors having
one source/drain coupled to nodes 113 or 114, respectively through the
capacitors 155, 157. The other source/drain of the transistors 162, 164
are coupled to cross-coupled inverters 166, 168, respectively. The
cross-coupled inventers 166 and 168 are configured to latch a voltage
difference sensed at the nodes 155 and 157 to provide an output signal
SDOUT. The transistors 162, 164 may be turned on by a control signal
SDSINLATB to begin a sensing operation.

[0022] The sensing circuit 100 of FIG. 1 operates in two modes to sense
data stored in the memory cell 110. A first mode is equalization mode.
During equalization mode, the transistors 142 and 152 may be turned on to
provide a fast path to settle a bias voltage of the cell 110. A switch
170 may also be closed. The switch 170 is coupled between the emitters of
the cascode transistors 120 and 121. By connecting the emitters of the
cascode transistors 120 and 121 together, the current in both legs 111
and 112 may be equal. In the comparator 107, the switches 172 and 174 may
be closed during equalization mode. The switches 172 and 174 are each
coupled between a respective input of the comparator 107 and VCC.
When the switches 172 and 174 are closed, both inputs are accordingly
equalized to Vcc. Transistors 162 and 164 may also be turned on
during equalization so the equalized voltage may be provided to the
cross-coupled inverters 164 and 168.

[0023] A second mode is amplification mode. Amplification mode may begin
once a bias voltage to the memory cell 110 has settled. During
amplification mode, the switches 170, 172, and 174 may be opened. The
transistors 142 and 152 may also be turned off. A voltage difference may
begin to develop between the nodes 113 and 114 using the transistors 122
and 123, as described above. Towards the end of amplification mode, the
transistors 162 and 164 may be turned off to hold a voltage difference
sampled and latched by the cross-coupled inverters 164 and 168. The
transistors 162 and 164 may be turned off in accordance with a control
signal, e.g. SDSINLATB. Switches 176 and 178 may also be provided between
the respective inverters 168 and 164 and the power supply. The switches
176 and 178 may be closed responsive to a delayed version of the
SDSINLATB signal. In this manner, the switches 176 and 178 may close at a
time after the transistors 162 and 164 are turned off so that the
cross-coupled inverters 164 and 168 may latch the sensed voltage at a
time after it is sampled by the transistors 162 and 164. The delay may be
on the order of 1 nanosecond in some examples.

[0024] In this manner, the sensing circuit 100 may be used to sense a
state of one or more memory cells, which may be PCM memory cells.

[0025] Embodiments of the invention further include reference voltage
generators that may be used, for example, to provide the SLVREF signal
applied to the gates of cascode transistors 120 and 121 of FIG. 1.
Sensing circuits, such as the sensing circuit 100 of FIG. 1, may be
distributed throughout an array of memory cells, such as an array of PCM
memory cells. Distributing sensing circuits throughout a memory cell
array may allow for faster reading operations. However, it may require
the reference voltage signal to also be routed throughout the array of
memory cells. A long routing of the reference voltage signal may have
disadvantageous consequences in that it may load the sensing circuit,
such as the sensing circuit 100 of FIG. 1. The long routing may be viewed
as presenting an effective output resistance (Rout) to the reference
voltage. The effective transconductance of the cascode transistor 120 of
FIG. 1 may be affected by the output resistance. The effective
transconductance of the cascode transistor may be expressed as:

G m = g m ( 1 + g m R out β ) ##EQU00001##

[0026] Where gm is the transconductance of the transistor and β is
the current gain of the transistor. Generally, a higher Gm may be
desired, and therefore a low Rout. Accordingly, embodiments of the
present invention may provide output drivers for a global reference
generator. That is, a reference voltage generator may be provided for a
number of memory banks. Output drivers may be distributed among the
memory banks to reduce the impact of the resistive routing.

[0027]FIG. 2 is a schematic illustration of a reference voltage generator
scheme in accordance with an embodiment of the present invention. The
reference voltage generator scheme 200 may include a global reference
voltage generator 201, a bank reference voltage generator 202, and
sensing circuits 203.

[0028] The global reference voltage generator 201 may include a bipolar
transistor 205 that may match a bipolar transistor used in the memory
cell, such as the bipolar transistor 226 shown in FIG. 2. A voltage
Vsafe provided by voltage source 207 may be added to an emitter-base
voltage of the transistor 205 at the node 208 to provide a voltage
SL_VREF_GEN through a transistor 260. The transistor 260 may be a bipolar
transistor and may match another bipolar transistor used in the sensing
circuits, such as the bipolar transistor 206 shown in FIG. 2. The
SL_VREF_GEN voltage may then be converted to a current I1 through
the voltage to current converter 209. By converting the global reference
voltage to a current I1, differences in ground or other power supply
voltages which may occur across a die may have less of an effect on the
distribution of a reference voltage. The reference current I1 may be
expressed as:

I 1 = ( V SL_VREF _GEN - VSS global ) R 1 ##EQU00002##

[0029] An output transistor 210 may then provide an output current
I2, which may be a mirrored I1, e.g. may have the same value as
I1. The global reference voltage generator 201 may be provided for
many banks of memory cells. The current I2 may be provided to
multiple bank reference voltage generators, including the bank reference
voltage generator 202.

[0030] The bank reference voltage generator 202 may be provided for a bank
of memory cells. In some examples, the bank reference generator 202 may
also serve multiple banks, but generally fewer banks than are served by
the global reference voltage generator 201. Only one bank reference
voltage generator 202 is shown in FIG. 2, however many may be connected
to the global reference voltage generator 201, as will be described
further below.

[0031] The bank reference voltage generator 202 may include a resistive
element 212 that may be coupled to the output transistor 210 and may
provide a reference voltage SLVREF_BANK from the current I2. The
resistive element 212 is shown as a resistor in FIG. 2, however any
resistive element may be used. The bank reference voltage, e.g.
SLVREF_BANK is accordingly provided based on I2 and R2 and the
local VSS voltage and may be given as:

[0032] VSLVREF--.sub.BANK-VSSlocal=I2*R2 Recall
I1 may equal I2 and R1 may equal R2. Accordingly,
VSL--VREF--.sub.GEN-VSSglobal=VSLREF---
.sub.BANK-VSSlocal. In this manner, the voltage difference between
the VSS supply and the reference voltage is preserved between the global
reference voltage generator 201 and the bank reference voltage generator
202. The scheme 200 may accordingly advantageously compensate for
variations in the VSS or other supply voltage across the memory
device.

[0033] A replica circuit 214 may be coupled to the resistive element 212
and may receive the SLVREF_BANK signal at an input of a comparator 215.
The replica circuit 214 is configured to provide a bias voltage for one
or more source follower circuits, including the source-follower circuits
216, 217 shown in FIG. 2. Any number of source-follower circuits may be
coupled to the bank reference voltage generator 202, as will be described
further below. A switch 213 may be coupled between an output of the
replica circuit 214 and inputs of the source follower circuits 216, 217
so that the replica circuit may operate in a sample-and-hold mode. Each
of the source follower circuits 216, 217 includes a respective transistor
218, 219. Each of the transistors 218, 219 is coupled to an output of the
replica circuit 214 at a gate of the transistor 218, 219. Each of the
transistors 218, 219 has a source coupled to a sensing circuit of the
sensing circuits 201. In this manner, the source follower configurations
216, 217 may provide a small output resistance to the sensing circuits
203. The source follower circuits 216, 217 may be biased in a
sub-threshold region of the transistors 218, 219 to further reduce output
resistance in some examples. The source follower circuits 216, 217 may
also be referred to as drivers herein, as will be described further
below.

[0034] The sensing circuits 203 of FIG. 2 include sensing circuits 220,
221, although any number of sensing circuits may be present. The sensing
circuit 100 of FIG. 1 may be used to implement one or more of the sensing
circuits 220, 221 in some examples. Referring back to FIG. 2, each of the
sensing circuits 220, 221 include a respective bipolar junction
transistor 206, 222. Each of the sensing circuits 220, 221 is configured
to sense a state of a respective memory cell 224, 225, which may be PCM
memory cells. Each PCM memory cell 224, 225 is represented in FIG. 2 as a
bipolar junction transistor 226, 227 and variable resistor 228, 229. Each
of the memory cells 224, 225 are coupled to a respective wordline 230,
231.

[0035] Wordline drivers 232, 233 are provided to drive the wordlines 230,
231. The wordline drivers may utilize a power supply voltage VHH,
which may be provided, for example, by a voltage regulator (not shown in
FIG. 2). The wordline drivers include respective resistors and
transistors, illustrated in FIG. 2 as Rup, and Rdown, where
Rdown represents the resistance of the transistors used in the
wordline drivers. The wordline drivers 232, 233 provide a wordline
voltage on the wordlines 230, 231 which may be given as:

V WL = R down R up + R down * VHH ##EQU00003##

[0036] However, the supply voltage VHH may vary at different sensing
circuits in accordance with different loading conditions. Accordingly,
the reference voltage SLVREF may need to be compensated in anticipation
of differences in the wordline voltage. Embodiments of the present
invention may also include wordline compensation. FIG. 2 illustrates two
wordline compensator circuits 250, 251. The wordline compensator circuit
250 may be implemented as a resistor divider including resistors 252,
253. Although resistors are shown, any resistive elements may be used.
The resistors 252, 253 are selected such that the ratio of their
resistance is equal to the ratio of resistances in the wordline drivers
232, 233. That may be expressed as:

R 4 R 3 = R up R down ##EQU00004##

[0037] Note also that the resistance R2+R3 may be equal to
R1. In this manner, the wordline compensation circuit 250 may
compensate the reference voltage SLVREF_BANK during a sample mode of the
sample-and-hold operation by adjusting the voltage at the node 255.

[0038] A second wordline compensation circuit 251 may be provided for
compensation during the hold mode of the sample-and-hold operation. The
second wordline compensation circuit 251 is coupled to an output of the
replica circuit 214 after the switch 213. The second wordline
compensation circuit is implemented as a capacitance voltage divider
including capacitors C1 and C2. Although capacitors are shown, any
capacitive elements may be used. The capacitances C1 and C2 may be
selected such that:

C 2 C 1 = R up R down ##EQU00005##

[0039] In this manner, the voltage at an input to the source follower
circuits 216, 217, may be compensated for by the wordline compensation
circuit 251.

[0040] Accordingly, embodiments of voltage generators have been described
which may provide a reference voltage to banks of memory by locally
buffering the reference voltage to reduce the output resistance of the
reference voltage generator. Moreover, embodiments of reference voltage
generators have been described that may utilize voltage to current
conversion in part to compensate for variations in power supply voltage.
Still further, embodiments of reference voltage generators have been
described that may compensate for variations in wordline voltage across
memory cells, memory banks, or both.

[0041]FIG. 3 is a schematic illustration of reference voltage routing in
accordance with an embodiment of the present invention. A memory device
300 may include any number of memory banks. The memory device 300 is
shown as including banks 301-304. Each bank may include a number of
memory cells and sense amplifiers. As shown in FIG. 3, the memory bank
301 may include eight strips of memory cells including strips 305, 306,
each of which may have 36 sense amplifiers.

[0042] A global reference voltage generator 310 may be provided on the
memory device 300. The global reference voltage generator 310 may be
implemented, for example, by the global reference voltage generator 201
of FIG. 2. Each bank of memory cells 301-304 may include a bank reference
voltage generator 311-314. One of the bank reference voltage generators
311-314 may be implemented, for example, using the bank reference voltage
generator 202 of FIG. 2. Each strip of memory cells may be provided with
a local driver. For example, the strips 305 and 306 are coupled to the
local drivers 325, 326. The local drivers 325, 326 are coupled to the
bank reference generator 311. The local drivers 325, 326 may be
implemented, for example, by the source follower circuits 216, 217 of
FIG. 2.

[0043] In this manner, a global reference generator 310 may provide a
reference voltage for use in sensing a state of memory cells in the
memory device. The reference voltage may be distributed to bank reference
voltage generators 311-314 which may be distributed across the memory
device. The bank reference voltage provided at each of the memory banks
may then be driven by local drivers to each strip of memory cells. In
this manner, as has been described above, the impact of output resistance
and the deleterious affects of supply voltage variations across a memory
device may be addressed.

[0044]FIG. 4 is a schematic illustration of a portion of a memory device
according to an embodiment of the present invention. The memory 400
includes an array 542 of memory cells, which may be, for example, phase
change memory cells, DRAM memory cells, SRAM memory cells, flash memory
cells, or some other type of memory cells. The memory system 400 includes
a command decoder 406 that may receive memory commands through a command
bus 408 and provide corresponding control signals within the memory
system 400 to carry out various memory operations. The command decoder
406 may respond to memory commands applied to the command bus 408 to
perform various operations on the memory array 402. For example, the
command decoder 406 may be used to provide internal control signals to
read data from and write data to the memory array 402. Row and column
address signals may be applied to the memory system 400 through an
address bus 420 and provided to an address latch 410. The address latch
may then output a separate column address and a separate row address.

[0045] The row and column addresses may be provided by the address latch
410 to a row address decoder 422 and a column address decoder 428,
respectively. The column address decoder 428 may select bit lines
extending through the array 402 corresponding to respective column
addresses. The row address decoder 422 may be connected to word line
driver 424 that may activate respective rows of memory cells in the array
402 corresponding to received row addresses. The selected data line
(e.g., a bit line or bit lines) corresponding to a received column
address may be coupled to read/write circuitry 430 to provide read data
to a data output buffer 434 via an input-output data bus 440. Write data
may be applied to the memory array 402 through a data input buffer 444
and the memory array read/write circuitry 430. Examples of the sense
amplifiers and reference voltage distribution circuitry described above
may be utilized as a portion of the read/write circuitry 430, row decoder
422, column decoder 428, word line driver 424, or combinations thereof.

[0046] The memory device shown in FIG. 4 may be implemented in any of a
variety of products employing processors and memory including for example
cameras, phones, wireless devices, displays, chip sets, set top boxes,
gaming systems, vehicles, and appliances. Resulting devices employing the
memory system may benefit from the embodiments of sensing circuitry
and/or reference voltage generators described above to perform their
ultimate user function.

[0047] From the foregoing it will be appreciated that, although specific
embodiments of the invention have been described herein for purposes of
illustration, various modifications may be made without deviating from
the spirit and scope of the invention.