A computer system having a peripheral controller interconnect (PCI) bus and an industry standard architecture (ISA), with ISA compatible devices coupled to the ISA bus, is provided with a first bridge coupled between the PCI and ISA buses. The first bridge has a first direct memory access (DMA) control circuit for controlling DMA transfers with the ISA devices. In order to achieve expanded compatibility with other types of devices, the system is also provided with an expansion bus, such as a Microchannel bus, with Microchannel compatible devices coupled to the Microchannel bus. A second bridge is coupled between the PCI and the Microchannel buses. This second bridge has a second DMA control circuit that controls DMA transfers with the ISA devices and with the Microchannel devices. Software disables the first DMA control circuit such that only the second DMA control circuit controls DMA transfers within the computer system.