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Clock Driver With Regulated, Differential Outputs

Publishing Venue

IBM

Related People

Freeman, LB: AUTHOR

Abstract

This article concerns a clock driver circuit design whose output signal provides for both latch clocking and current source voltage regulation, thereby enabling more efficient operation and better performance to be obtained from a series-gated current switch emitter-follower cascode latch circuit. Fig. 1 illustrates three stages in the development of currentswitch emitter-follower (CSEF) circuits. Circuit 1A employs a currentswitch emitter resistor R1 for current source current regulation and thereby becomes subject to noise margin problems and greatly increased tolerances in circuit propagation delay. These problems are largely overcome in the generic form of the widely used CSEF logic circuit shown in 1B where the resistor R1 is replaced by the transistor T1 constant current source.

Country

United States

Language

English (United States)

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Clock Driver With Regulated, Differential Outputs

This article concerns a clock driver circuit design whose output signal provides
for both latch clocking and current source voltage regulation, thereby enabling
more efficient operation and better performance to be obtained from a series-
gated current switch emitter-follower cascode latch circuit. Fig. 1 illustrates three
stages in the development of currentswitch emitter-follower (CSEF) circuits.
Circuit 1A employs a currentswitch emitter resistor R1 for current source current
regulation and thereby becomes subject to noise margin problems and greatly
increased tolerances in circuit propagation delay. These problems are largely
overcome in the generic form of the widely used CSEF logic circuit shown in 1B
where the resistor R1 is replaced by the transistor T1 constant current source.
The logic power of this circuit can be further extended, as shown by the series-
gated (cascode) CSEF circuit (without current source) in 1C, where the current
source transistor T1 in 1B has been made logically active, thereby greatly
increasing the logic capability of that circuit without changes in power supply
voltage or signal swing, or with any increases in circuit power dissipation.
However, due to the presence of the emitter resistor R2 in circuit 1C instead of a
constant current source, this design again suffers from reduced circuit noise
margins and increased delay tolerances. By the means here disclosed, signals
may be usefully generated to drive the bottom transistors T2 and T3 so as to
provide logic functionality while still preserving the advantages of the constant
current source identified with the 1B circuit. Fig. 2 shows a three-level differential
cascode latch circuit incorporating multiple data ports, data port gating, scan
clock, system clock and cycle to cycle data hold capability all in one stage. Many
advantages accrue from application of this circuit configuration provided that it
can be integrated into existing circuit technology without loss of its desirable
operating characteristics. The key to successful integration is the generation of
the regulated system clock signal inputs c and - that are applied to the transistors
T4 and T5, providing power supply voltage and temperature compensation of th...