Some old British Machines

What follows is a summary of some British architectures from the 1960's: I give them in
(approximate) chronological order. They share a common philosophy (if not a common architecture),
apparently deriving from the vacuum-tube designs of the early 1950's. None of these machines
used integrated logic in any form: everything was discrete transistors, and in some cases,
ferrite-core logic.

This machine was introduced around 1962. It was also the first machine I myself ever wrote
code for, in 1968!
Built using discrete transistor and ferrite-core technology, and using bit-serial logic. Word
length was 39 bits. This architecture seems to have originated in the Ferranti Pegasus, a
vacuum-tube machine from 1956.

Sizes & weights (inches, pounds)

Central Processor

66x56x16

680

Extra 4096 words store

33x56x16

250

Power Unit

33x56x16

380

19-bit instructions were packed 2 to a word, with the 39th bit acting as a "modifier" on the
second instruction. The effect of this was to add the content of the memory location addressed
in the first instruction to the whole of the second: this was the only computed-address
mechanism available (short of self-modifying code). The modification acted on the opcode bits
as well as the address: this was the basis of many truly incomprehensible coding tricks!
Half-page Algol programs used to take half an hour to compile & execute. Amazingly, the Algol
compiler and run-time package (developed under the direction of
C. A. R. Hoare) would fit in 8192
words of memory. Standard IO was 5-track paper tape, with magnetic tape an option. The mag-tape
was termed "film": the tape format actually being identical to 35mm movie film.

Hardware floating-point was available, with a 39-bit floating-point number, and a (binary)
exponent range of +/-256.
With a maximum memory capacity of 8192 words, 13 address bits were used. The remaining 6 bits
were available for the opcode, and were represented as 2 octal digits.

Instructions

The content of the single 39-bit accumulator is denoted by a, and that of the addressed
location by n. a' and n' denote the values after the operation. N
denotes the address part of the instruction.

Groups 0 - 3 (Arithmetic) 576uS

Group 0

Group 1

Group 2

Group 3

Code

a'

n'

Code

a'

n'

Code

a'

n'

Code

a'

n'

00

a

n

10

n

a

20

a

a

30

n

n

01

-a

n

11

-n

a

21

a

-a

31

n

-n

02

n+1

n

12

n+1

a

22

a

n+1

32

n

n+1

03

a&n

n

13

a&n

a

23

a

a&n

33

n

a&n

04

a+n

n

14

a+n

a

24

a

a+n

34

n

a+n

05

a-n

n

15

a-n

a

25

a

a-n

35

n

a-n

06

0

n

16

0

a

26

a

0

36

n

0

07

n-a

n

17

n-a

a

27

a

n-a

37

n

n-a

Group 4 (Jumps) 288uS

Code

Code

Condition

40

44

Unconditional

41

45

If a negative

42

46

If a zero

43

47

If oflo. (clear flag)

40..43

Jump to 1st half of word

44..47

Jump to 2nd half of word

Group 5 (Shifts)

Double-length shifts use a and ar (the "auxiliary accumulator")

Code

Function

50

Arithmetic right shift N places

51

Logical right shift N places, clear ar

52

Multiply (double-length product)

53

Multiply (single-length product), ar:= 0

54

Shift left, double-length, N places

55

Shift left, single length, ar:= 0

56

Divide a:ar by n, ar:= 0

57

a:= ar

Group 6 (Floating-point & miscellaneous functions)

Code

Function

60

a:= a+n

61

a:= a-n

62

a:= n-a

63

a:= a*n

64

a:= a/n

65

Convert integer in A to floating-point

66

Interrupt return (503 only)

67

Modify next instruction by adding LS 19 bits of n (503 only)

Group 7 (Input/Output)

70

Read panel key-switches to a

71

Read character from device N to a

72

Output 39-bit word from a to device N

73

Write the address of this instruction to location N

74

Output character to device N

75

Input 39-bit word from device N to a

76

Setup hardware for block transfer (503 only)

77

Initiate DMA operation (503 only)

Elliott 503

Introduced in the mid-60s, the 503 was a fully parallel replacement for the 803, running some
60 times faster. Group 0 instructions, for example, took 7.2uS. This machine, fully optioned
up, would have weighed several tons.

Sizes & weights (inches, pounds)

Logic Cabinet

78x38x24

1000

Main Store cabinet

78x38x24

850

Power Cabinet

78x38x24

1350

Full Controller cabinet

78x38x24

1000

Half Full Controller cabinet

78x38x24

750

Peripheral Services cabinet

78x38x24

1200

A little exercise

Just for fun, here's a stock bit of code (a subroutine entry/exit sequence) for these machines.
Do you see what's happening (tip: the "/" operator between the instructions invokes the "modify"
function):

This machine was originally designed for a British military project, and spawned a series of
military and civilian derivatives. The basic machine fitted in a desk 37 x 26 x 43 inches,
weighing 470lb. It could be likened to a 503 cut in half: the word-length is 18 bits, and
accommodates a single instruction. Most instructions executed in around 20uS. The bit
assignment within the word was:

Address

13 bits

Opcode

4 bits

Modifier

1 bit

Like the 503, address space was 8192 words, with extra memory accessible by paging. Being
designed for real-time applications, the 903 featured 4 interrupt priority levels. Separate
S (program counter) and B (modifier) registers for each level were mapped into
the first 8 memory locations. Unlike the 503, the "modifier" did not affect the operand of the
previous instruction, rather the modifier (here designated B) was added to the address
part of the instruction. The B register was loaded by Instruction 0.

Instruction codes (notation as above, with B & Q added)

Code

Function

0

b:= n; q:= n

1

a:= a+n

2

a:= n-a; q:= n

3

n:= q

4

a:= n

5

n:= a

6

a:= a & n

7

Jump to N if a=0

8

Jump to N unconditionally

9

Jump to N if a<0

10

n:= n+1

11

Store program counter in N

12

A:Q:= a*nThis multiply used fractional notation

13

a:= A:Q/nThis divide used fractional notation

14

Shift A:Q left or right N places (N signed)

15

Miscellaneous: I/O, interrupt return, etc.

Singer System-10

Being designed in the US, this machine wouldn't normally rate a place on this page. However
it is so unusual that it deserves mention somewhere on the Web, and no-one else seems to have
done so. So here it is, on its own page. This is put together
from memory, so there may be errors. Corrections & additions are welcome.
Back to Home Page

73 SUBR writes the address of this instruction in SUBR (that's the all-zero
location that starts the subroutine).

40 SUBR+1 now we jump to the (first half of the) instruction following the SUBR
location: this will be the first live instruction of the subroutine.

22 SUBR this is the return instruction. We begin by incrementing the stored value,
so it now points after the 73 instruction that stored its address. That is, it
now points at the instruction we want to return to. We then modify the next instruction.

/ 40 0 this instruction looks like a jump to zero. But it was modified by the previous
instruction, which added the (incremented) content of SUBR to the instruction. Since that
would be a 13-bit memory address, the effect is to change the jump target to the required
return point, as required.

Of course, 00 SUBR / 40 1 would have returned just as well (wouldn't it?)