In general Meitner uses three links between the transport and the DAC, clock out from DAC to Xport, clock into DAC from Xport and data into DAC from Xport. The clock from the DAC to the transport is optional in which case the transport shoves data down the DACs throat :)

The data is simply bytes of samples @ 64Fs (or 128Fs), each bit for a different channel. The clock runs slower and they obviously use a PLL to multiply it up. There are other details but since all I know is by using my scope and FPGA, any more would be speculation :)

I chose to put two HFBR-2416TZ interface modules on my board simply because I have a EMM Labs CDSD transport and it's simpler hooking up a fiber cable (or two) than hooking five clips onto chips in a S9000ES...

The problem is that Sony doesn't like raw DSD bits running around so I wouln't count on anyone supporting this interface.

I'll write ASIO drives first if I write my own USB drivers, but there are now some turnkey USB chip/driver solutions which don't involve licencing issues and support the expected USB modes as well as async.