The abstract of the patent published by the U.S. Patent and Trademark Office states: "An array of nonvolatile memory cells includes a plurality of vertically stacked tiers of nonvolatile memory cells. The tiers individually include a first plurality of horizontally oriented first electrode lines and a second plurality of horizontally oriented second electrode lines crossing relative to the first electrode lines. Individual of the memory cells include a crossing one of the first electrode lines and one of the second electrode lines and material there-between. Specifically, programmable material, a select device in series with the programmable material, and current conductive material in series between and with the programmable material and the select device are provided in series with such crossing ones of the first and second electrode lines. The material and devices may be oriented for predominant current flow in defined horizontal and vertical directions. Method and other implementations and aspects are disclosed."

The patent application was filed on April 15, 2011 (13/088,238).

Solid state lighting devices with reduced dimensions and methods of manufacturing
Micron Technology, Boise, ID, has been assigned a patent (8,536,594) developed by Vladimir Odnoblyudov, Eagle, ID, for "solid state lighting devices with reduced dimensions and methods of manufacturing."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Solid state lighting (SSL) devices (e.g., devices with light emitting diodes) with reduced dimensions (e.g., thicknesses) and methods of manufacturing are disclosed herein. In one embodiment, an SSL device includes an SSL structure having a first region and a second region laterally spaced apart from the first region and an insulating material between and electrically isolating the first and second regions. The SSL device also includes a conductive material between the first and second regions and adjacent the insulating material to electrically couple the first and second regions in series."

The patent application was filed on Jan. 28, 2011 (13/016,183).

Memory cells, non-volatile memory arrays, methods of operating memory cells, methods of reading to and writing from a memory cell, and methods of programming a memory cell
Micron Technology, Boise, ID, has been assigned a patent (8,537,599) developed by Bhaskar Srinivasan, and Gurtej S. Sandhu, Boise, ID, for a "memory cells, non-volatile memory arrays, methods of operating memory cells, methods of reading to and writing from a memory cell, and methods of programming a memory cell."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "In one aspect, a method of operating a memory cell includes using different electrodes to change a programmed state of the memory cell than are used to read the programmed state of the memory cell. In one aspect, a memory cell includes first and second opposing electrodes having material received there-between. The material has first and second lateral regions of different composition relative one another. One of the first and second lateral regions is received along one of two laterally opposing edges of the material. Another of the first and second lateral regions is received along the other of said two laterally opposing edges of the material. At least one of the first and second lateral regions is capable of being repeatedly programmed to at least two different resistance states. Other aspects and implementations are disclosed."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Embodiments of the present disclosure provide methods, devices, modules, and systems for healing non-volatile memory cells. One method includes biasing a first select gate transistor coupled to a string of memory cells at a first voltage, biasing a second select gate transistor coupled to the string at a second voltage, applying a first healing voltage to a first edge word line in order to extract charge accumulated between the first select gate transistor and a first edge memory cell stack of the string, and applying a second healing voltage to a second edge word line in order to extract charge accumulated between the second select gate transistor and a second edge memory cell stack of the string."

The patent application was filed on Aug. 6, 2012 (13/567,729).

Arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiersof non-volatile cross point memory cells
Micron Technology, Boise, ID, has been assigned a patent (8,542,513) developed by Sanh D. Tang, and Gurtej S. Sandhu, Boise, ID, for "arrays of vertically stacked tiers of non-volatile cross point memory cells, methods of forming arrays of vertically stacked tiers of non-volatile cross point memory cells, and methods of reading a data value stored by an array of vertically stacked tiers of non-volatile cross point memory cells."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extensions extend through multiple of the tiers. Individual of the memory cells comprise multi-resistive state material received between one of the horizontally oriented word lines and one of the local vertical bit line extensions where such cross, with such ones comprising opposing conductive electrodes of individual memory cells where such cross. A plurality of bit line select circuits individually electrically and physically connects to individual of the local vertical bit line extensions and are configured to supply a voltage potential to an individual of the global horizontal bit lines. Other embodiments and aspects are disclosed."

The patent application was filed on Feb. 26, 2013 (13/777,083).

Forming non-volatile electron storage memory and resulting device
Micron Technology, Boise, ID, has been assigned a patent (8,541,821) developed by Shubneesh Batra, and Gurtej Sandhu, Boise, ID, for a "method of forming a non-volatile electron storage memory and the resulting device."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "The invention provides a method of forming an electron memory storage device and the resulting device. The device comprises a gate structure which, in form, comprises a first gate insulating layer formed over a semiconductor substrate, a self-forming electron trapping layer of noble metal nano-crystals formed over the first gate insulating layer, a second gate insulating layer formed over the electron trapping layer, a gate electrode formed over the second gate insulating layer, and source and drain regions formed on opposite sides of the gate structure."

The patent application was filed on Sept. 16, 2011 (13/234,836).

Optimized flash memory access method and device
Micron Technnology, Boise, ID, has been assigned a patent (8,539,141) developed by four co-inventors for an "optimized flash memory access method and device."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method for accessing a non volatile memory device including at least one group or sector of memory cells divided into regions programmable with two different storage densities and accessible with at least two reading modes, for example a two-level mode and a multilevel mode. The memory regions are being organized into pages including a sub-group of memory cells for storing ECCs of the data stored in the multilevel mode. The method includes providing at the beginning of each page at least one first cell wherein the information concerning the ECC protection or not of the whole page is to be stored. In the sub-group of cells at least one second cell intended for the storage of information concerning the programmed or erased state of the same page is provided. The content of the first and of the second cell is read before accessing, in programming, the corresponding page of the memory region."

The abstract of the patent published by the U.S. Patent and Trademark Office states: "Some embodiments include memory cells. A memory cell may contain a switching region and an ion source region between a pair of electrodes. The switching region may be configured to reversibly retain a conductive bridge, with the memory cell being in a low resistive state when the conductive bridge is retained within the switching region and being in a high resistive state when the conductive bridge is not within the switching region. The memory cell may contain an ordered framework extending across the switching region to orient the conductive bridge within the switching region, with the framework remaining within the switching region in both the high resistive and low resistive states of the memory cell."

The patent application was filed on Aug. 11, 2011 (13/208,216).

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