Integrated CMP Metrology and Modeling with Respect to Circuit Performance

Runzi Chang
(Professor Costas J. Spanos)
(UC-SMART) SM97-01

As the scaling efforts and complexity of circuit design continue to grow, interconnect variation becomes one of the limiting factors of circuit performance [1]. The systematic nature of the pattern-density dependency in chemical mechanical polishing (CMP) makes previously used approaches to statistical circuit analysis, such as worst-case analysis, insufficient and inaccurate. In this project, we will build models for the oxide and copper CMP process so that the systematic components of the interconnect variation can be decomposed from the total variability. The reduced randomness will enable more aggressive circuit (interconnect) design.

This project has two phases: during the first phase we will use library-based scatterometry as a novel metrology tool to monitor the oxide profile evolution [2,3]. Subsequently, we will use the profiles to build models for oxide CMP. During the second phase, based on the knowledge of oxide polishing processes, we will design test structures, perform characterization experiments, and develop physical or semi-empirical models for copper dishing and oxide erosion in the damascene process [4]. We also plan to integrate the CMP variation model into a circuit performance simulation tool, and study the effects of CMP variation on circuit performance. A long term objective of this project is to provide designers with the tools that will allow design optimization while properly accounting for CMP variability.