This Tutorial is a very simple explanation of the UVM
methodology, taking Specman 'e' as an example language.
The concepts presented here, can easily be ported into System
Verilog.
The object here is to explain why this UVM UVM di :), not have a
discussion over System Verilog Vs Specman 'e'.

Issues addressed by UVM/OVM.

Bugs.

The rapidly growing complexity of SoCs and subsystems
pose a substantial verification challenge. Conventional
way of writing testbenches, which is also termed as directed test
writing approach is proving to be inadequate
to be able to find bugs in these complex systems. "Constrained
Random" Stimulus generation is understood
to be able to address this issue. It is understood that using
constrained random stimulus, it’s easier to find bugs with
less efforts. This is the primary way of generating stimulus in
UVM/OVM methodology.

Reuse

UVM/OVM methodology provides a standard infrastructure
to develop a reuseable testbench.It is understood that an
UVM/OVM compliant test environment can easily be ported across
various projects.

Ease of use

There are two aspects of the UVM/OVM testbench, one is
the development of the testbench/test environment
itself, and the other being its use. The 'ease of use' refers to
the later. Developing the test environment is certainly
a complex task. Once developed, it is understood, that using it is
not only easy, but also it does not require the
test writer to have detailed knowledge of the test environment,
the DUT or even the protocols the DUT uses.

To fully appreciate the need of UVM/OVM type of methodology,
it is recommended that the reader gets familiar with the AHB
protocol specification.
A copy of AHB protocol spec can be found Here.
This tutorial uses AHB as an example Interface to explain how
to develop a UVM compliant test bench.

What we have learnt so far?
UVM/OVM is just a collection of 'rules', which define a standard way
of coding a complex testbench!

Ah! one more thingi: Use UVM/OVM only for complex verification
testbenches.
Write a UVM/OVM testbench for a counter, and you will
immediately
try to hunt down the UVM/OVM inventor for sure :).