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SDNet Development Environment

Expanding Programmabilityfrom the Control to the Data Plane

Enabling Software Defined Hardware Processing

The SDNet™ Development Environment for networking, in conjunction with Xilinx FPGA and SoC devices, allows for the creation of next-generation hardware-accelerated software-defined networks.

SDNet supports packet processing functionality with high throughput and low latency. It allows for game-changing differentiation through software-programmable data plane hardware with content intelligence that dynamically collaborates with control plane software. This addresses the performance, flexibility, and security challenges of modern content-oriented, intent-based, and zero-touch, networking.

Software-Defined Programmability

SDNet enables the development of software-defined data plane hardware, featuring support for the modern P4 packet processing language. It adds some novel generalizations to current P4 that permit effective harnessing of the unique white box hardware capabilities of Xilinx devices. These allow the system architect to define exact fit hardware for particular network requirements, in contrast to potentially wasteful fixed-resource ASIC alternatives. SDNet also creates standard runtime software APIs into the P4-programmed data plane, ensuring that investments in standard software stacks for slow-path packet processing and network operation and management, are protected.

The unique capabilities unleashed by SDNet with its P4 programming model enable carriers and MSOs to dynamically provision unique, differentiated services without any interruption to the existing service or the need for hardware re-qualification or truck roll. This enables service providers to reach higher revenue potential with unprecedented CapEx, OpEx, and time to market savings. Network equipment providers and network-attached server providers realize similar benefits from the feature-rich, flexible hardware platform that allows for extensive differentiation through the deployment of content-aware data plane hardware.

Particular benefits enabled by SDNet include:

Improved, highly flexible quality of service

Flow-and-session-aware capabilities

Fully programmable hardware data plane and input/output

Support for network functions at wire speed including user-defined, custom capabilities

The graphic below demonstrates how system architects can unleash the benefits of Xilinx technologies to realize smarter networks without requiring a detailed knowledge of the underlying device architecture. This implementation flow allows system architects to focus only on the services they are looking to provision without having to focus on exactly how those services are being implemented.

To support programmability for network devices, P4 (www.p4.org) has been developed as a new programming language for describing how network packets should be processed on a variety of targets ranging from general-purpose CPUs to NPUs, FPGAs, and custom ASICs. P4 was designed with three goals in mind:

Protocol independence: devices should not bake in specific protocols

Field reconfigurability: programmers should be able to modify the behavior of devices after they have been deployed

Portability: programs should not be tied to specific hardware targets

P4 is the first widely-adopted domain-specific language for packet processing. Xilinx has adopted P4 as the standard programming language for its SDNet development environment. SDNet uses the latest P4_16 language specification, released in May 2017. It also includes some early-access generalizations of the language, anticipating future standardization, to allow for streamlining packet processing, and to allow packet processing architecture definition. Early use cases for P4-SDNet have included accelerated data center SmartNIC applications in Inband Network Telemetry (INT) and NFV Service Function Chaining (SFC) at line rate.

The P4 community has created and continues to maintain and develop the language specification. This includes a set of open-source tools (compilers, debuggers, code analyzers, libraries, software P4 switches, etc.), and sample P4 programs, that enable P4 users to quickly and correctly author new data plane behavior, and prototype new ideas for networking applications. Xilinx is a founding member of this community, taking a leading role in the P4 language specification development, demonstrating the earliest high-performance implementations of P4 programs, and making P4 available in its SDNet Development Environment.