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By adding trailing edge delay control to a high performance asymmetric
complementary metal oxide silicon (CMOS) driver, applicability of the driver is not
limited by the input pulse signal width.

The driver circuits, Figs. 1 and 2, are asymmetric inverters with a gated
feedback path for the restore operation. Fig. 1 is the active low driver and is
operationally the complement of Fig. 2, the active high driver. Devices T1, T2,
T3, T4, T5, and T6 comprise the asymmetric inverter chain. In both circuits,
devices T10, T11, T12, T13, and T14 comprise a switch which begins the restore
operation once the input to the circuit has returned to an inactive state.

In a typical cycle the circuit of Fig. 1 begins with input IN high, node A low,
node B high, output OUT low, node C low, node E high, and node F low. As IN
goes active low, device T1 quickly brings node A high, which turns on transistor
T4, pulling node B low thus turning transistor T5 on and pulling OUT high. At the
same time, IN going low turns transistor T11 off, output of the inverter T12 and
T13 goes high, thus turning device T10 off and turning device T14 on. Device
T14 is a small device used to clamp node D low while input IN stays active.
Nodes D, E, and F do not change states as the input transistions from high to
low.

Input IN is then brought high again to begin the restore operation. Device
T11 turns on and the output of inver...