Using Perl in your SystemVerilog HDL Design Flow

Anyone who designs with SystemVerilog HDL has probably grown tired of generating module
instantiations in a hierarchical design, or creating a new top level or lower level
SystemVerilog HDL module. I have generated a few Perl Scripts that will automatically
generate the module instantiations, top level module, and lower level module for you.
These Perl Scripts can be invoked from within VI/VIM/GVIM, or a DOS Command Window.
If you invoke them from within VI, the script output will be printed in the current
file. If you invoke them from within a DOS Command Window, then you will have to
either cut and paste into your SystemVerilog HDL file or pipe the output to a new file.
These files are hosted on GitHub at the link below:

The scripts above have been modified to use a Perl Module named SystemVerilogTools, which can be downloaded [here].
Simply unzip the file into a temporary directory, navigate to the directory named ./jwwebbopen-SystemVerilogTools-*/module/ and execute the following commands:

This utility is intended to make creating new SystemVerilog HDL modules easier using
a good editor, such as VI. As long as you set the top line to correctly point to
your perl binary, and place this script in a directory in your path, you can
invoke it from VI. Simply use the !! command and call this script with the
filename you wish to instantiate. This script will create a new text file called
"top.sv" when you type the following command:

!! sv_mod_top.pl -a -f top.sv

The script will generate the empty SystemVerilog HDL template for you in the
file "top.sv". Note: "top.sv" is the name of the new SystemVerilog HDL
file and can be anything you like. The module declaration uses Verilog 2001 ANSI-C style.
You can either use VI or a DOS Command prompt to run this script. If you want to use
a DOS Command prompt, then see the instructions below:

Change directory to the desired directory; if necessary create a directory to store the new module.

This utility is intended to make creating new SystemVerilog HDL modules easier using
a good editor, such as VI. As long as you set the top line to correctly point to
your perl binary, and place this script in a directory in your path, you can
invoke it from VI. Simply use the !! command and call this script with the
filename you wish to instantiate. This script will create a new text file called
"mymodule.sv" when you type the following command:

!! sv_mod_low.pl -z -f mymodule.sv

The script will generate the empty SystemVerilog HDL template for you in the
file "mymodule.sv". Note: "mymodule.sv" is the name of the new SystemVerilog HDL
file and can be anything you like. The module declaration uses Verilog 2001 ANSI-C style.
You can either use VI or a DOS Command prompt to run this script. If you want to use
a DOS Command prompt, then see the instructions below:

Change directory to the desired directory; if necessary create a directory to store the new module.

This utility is intended to make instantiation in SystemVerilog HDL easier using
a good editor, such as VI. As long as you set the top line to correctly
point to your perl binary, and place this script in a directory in your
path, you can invoke it from VI. Simply use the !! command and call
this script with the filename you wish to instantiate.

!! sv_inst.pl -i -f adder.sv

The script will retrieve the module definition from the file you specify and
provide the instantiation for you in the current file at the cursor position.

This utility is intended to make creating new SystemVerilog HDL Test Bench modules easier.
This script will create two new text files called "test_mymodule.sv" and "top.sv" when you
type the following command:

!! sv_tb.pl -t -f mymodule.sv

The script will generate the SystemVerilog HDL test bench template for you with the port
contents of "mymodule.sv". Note: "mymodule.sv" is the name
of the existing SystemVerilog HDL file, "test_mymodule.sv" is the new test bench
file, and "top.sv" is the top level of the simulation test bench that instantiates
the module or unit under test and the stimulus.

The script will retrieve the module definition from the "mymodule.sv"
file you specify and provide the instantiation for you in the new
"top.sv" file along with the instantiation for the stimulus "test_mymodule.sv".

The keyword "module" must be left justified in the SystemVerilog HDL file you are
instantiating to work.

You can either use either a bash terminal or a DOS Command prompt to run this script.
Instructions are provided below:

This utility is intended to make the creation of UCF files for Xilinx
designs easier.

!! sv_ucf -u -f adder.sv

The script will retrieve the input/inout/output definitions from the file
you specify and reformat it into the UCF format. It will then write a
new file called "adder.ucf", which contains the pin assignments. Below
is an example of the UCF file contents: