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Tutorial on Mixed mode simulation and simulation of spice netlists in Cadence

This tutorial will show you how to simulate a mixed-mode circuit, a circuit partly described by verilog and partly by circuit elements such as resistors, capacitors, transistors etc. in Cadence IC5141. It will also show you how to directly simulate a SPICE netlist without having to create schematic and symbol views in Cadence. The demonstration is made by building a window comparator using two discrete op-amps described by a manufacturer provided SPICE macro-model) and an AND gate(described by verilog).

Specify the section "mc" when performing process and mismatch analysis. Also, specify design variable 'sigma' and set it to 3.
Specify section such as "tt" or "ss" or "ff" or "snfp" or "fnsp" for mismatch only simulation (you are fixing the process corner here).