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Abstract

This article shows how to speed the carry generations of a large adder using a standard CMOS library and how to avoid the pseudo end around carry adder loop.

Country

United States

Language

English (United States)

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This is the abbreviated version, containing approximately
52% of the total text.

Fast 80-Bit CMOS Adder

This article
shows how to speed the carry generations of
a large adder using a standard CMOS library and how to avoid the
pseudo end around carry adder loop.

For an 80-bit
carry look ahead adder, it is known that the
adder is composed of:
1. 80 generate blocks Gi= Ai AND Bi
2. 80 propagate blocks Pi= Ai XOR
Bi
Using these equations, the carry
expressions is given by:

(Image Omitted)

Ci+1= Gi +
PiGi-1+ PiPi-1Gi-2+ PiPi-1Pi-2Gi-3 +
PiPi-1Pi-2Pi-3Ci-3
The above expression can be
written:
Ci+1= Gk + PkCi-3
3. 20 generate/propagate group 4
The propagate group 4 is
produced by 1 level AND
gate but the generate group 4 is
produced by 2 levels
of NAND gates in the known carry
lookahead adder.
C4i= G4k + P4kG4k-1 + P4kP4k-1G4k-2
+
P4kP4k-1P4k-2G4k-3
+ P4kP4k-1P4k-2P4k-3C4(i-4) for
O < k < 19,
i = 4, 8, 12, 16
4. 5 generate/propagate GROUP 16
From the above, it can be deduced that:
a) For the generate group 16, it is
worthwhile to use the 2 x 4
AND-OR gate for better area and delay ratio versus two levels of NAND
as explained below.

With the
group propagate being produced 1 logic level before
the group generate, they can be combined by AND gates:
P4k,k-1 = P4kP4k-1
P4k,k-1,k-2 = P4kP4k-1P4k-2
P4k,k-1,k-2,k-3 =
P4kP4k-1P4k-2P4k-3
The carry expression can now be
written:
C4i= G4k + P4kG4k-1 + P4k,k-1G4k-2
+ P4k,k-1,k-2G4k-3
+ P4k,k-1,k-2,k-3C4(i-4)

The four left
terms represent the group generate 16 (2 x 4 way
AND-OR); the...