New AVX-512 Instructions Boost Performance on Intel Xeon Phi

As chip technology advances over time, new instructions can be added to a given architecture. A key is to make sure that these systems are backward compatible, that older applications can still run, while newer applications can take advantage of the new instruction sets. New hardware needs to support previous instruction sets to maintain compatibility and similar programming models.

An example of this are some new instructions for the Intel Knights Landing product , officially known as the Intel Xeon Phi processor. Besides a novel architecture for HPC applications, this product had introduced new instructions known as AVX-512. These new instructions provides 512 bit SIMD support, 32 logical registers as well as other instructions that support HPC applications.

There are four categories of these new instructions which are briefly mentioned here. AVX-512 Foundation instructions, AVX-512 Conflict Detection Instructions, AVX-512 Exponential and Reciprocal Instructions, and AVx-512 Prefetch Instructions. These new instructions provide new and improved performance for a variety of operations.

The new AVX-512 instructions have been designed with developers in mind. High level languages that are used for HPC applications, such as FORTRAN and C/C++, through a compiler will be able to use the new instructions. This can be accomplished through the use of pragmas to direct the compilers to generate the new instructions, or users can use libraries which are tuned to the new technology.

While there have been previous generations of AVX instructions, the AVX-512 instructions can significantly assist the performance of HPC applications. With the wider instruction length, more work can be done per clock tick than before, increasing the throughput by, for example, the ability to perform 8 double precision multiply-add instructions at once.

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