First Carbon Nanotube Computer Integrated With CMOS

PORTLAND, Ore. -- The first working computer using carbon-nanotube transistors on a silicon wafer was recently demonstrated by researchers at Stanford University. Using what is called an "imperfection-immune design," these researchers claim to have overcome the main obstacles facing carbon-based semiconductors, by integrating nanotubes into the complementary metal-oxide semiconductor (CMOS) design process.

Nanometer diameter tubes of pure carbon -- nanotubes -- were heralded as the ideal transistor material a decade ago, because carbon nanotube transistors are higher-speed and lower-power than silicon transistors. Individual carbon nanotube transistors were demonstrated by IBM and others, but two problems plagued full-scale development efforts: the inability to grow them in perfectly straight arrays, and the difficulty of sorting out semiconducting- from metallic-nanotubes. As a result, most researchers today have switched from nanotubes to investigating planar carbon -- graphene -- which can be fabricated using more traditional CMOS techniques.

Now Stanford researchers, led by professors Subhasish Mitra and H.S. Philip Wong, along with doctoral candidate Max Shulaker, hope to revitalize carbon-nanotube development efforts by surmounting its problems with a CMOS compatible process they call "imperfection-immune design."

"Using a combination of imperfection-immune design techniques with processing advances enabled us to overcome the challenges of using carbon nanotubes," said Mitra. "Our entire paradigm is silicon compatible -- both processing and design follow traditional CMOS flows."

Their approach works by first using chemical vapor deposition (CVD) to grow nanotubes side-by-side in precise arrays. Many methods have been tried to do this in the past, but nanotubes are notorious for bending during growth on silicon, thus spoiling the precise arrays needed to create the perfect design features necessary to build high-density transistors. Stanford's new method, however, first fabricates precise arrays on quartz, in which 99.5 percent of the nanotubes lie in straight lines side-by-side, then transferring the arrays to a CMOS wafer.

"If you grow nanotubes on a silicon substrate they looks like spaghetti," said Mitra. "Instead we grow them in straight lines on quartz, then transfer them to silicon on a wafer scale."

Even with 99.5 percent of the nanotubes in parallel arrays, the remaining .5 percent would ordinarily result in an unacceptable number of defects for CMOS chips with billions of carbon nanotube transistors. To solve that problem, the researchers use a circuit layout technique that etches out pre-defined regions for specific functions using a graph-theoretic algorithm that works for any arbitrary alignment of carbon nanotubes. This scalable approach results in imperfection-immune standard cell libraries using the same design infrastructure as is used for CMOS logic synthesis.

The second problem overcome by the imperfection-immune technique was coping with metallic nanotubes. Nanotube manufacturing techniques result in a mixture of semiconducting and metallic nanotubes. The problem is that when using nanotubes as transistor channels, they must be based only on the semiconducting variety, since metallic ones result in transistors that cannot be turned off. To eliminate the metallic nanotubes, the Stanford researchers used an electrical breakdown technique that first switches off all the semiconducting nanotubes, then sends enough current through the remaining metallic ones to vaporize them -- like a fuse -- thus cleansing the circuitry of all but the remaining semiconducting nanotubes.

As a result, the Stanford design team was able to create a working central-processing unit (CPU) using 178 carbon nanotube transistors that execute 20 instructions from the reduced instruction set computer (RISC) originally designed by then Stanford professor John Hennessy, who later became co-founder of MIPS Technologies Inc. of Sunnyvale, Calif. and who is now Stanford's president. The researchers claim their imperfection-immune design technique is scalable, CMOS compatible and was only limited to 178 transistors by Stanford's limited prototyping facilities.

Funding was provided by the National Science Foundation, the Systems On Nanoscale Information fabrics Center (SONIC), the Stanford Graduate Fellowship, and the Hertz Foundation Fellowship.

Carbon melts at approx 3600 C and vaporizes (boils) at 4200 C. They state "..vaporize them -- like a fuse -- thus cleansing the circuitry of all but the remaining semiconducting nanotubes..." It is to be hoped that this operation is carried out in an oxygen rich atmosphere as this will allow lower temperatures with the by- products carbon monoxide or dioxide and avoid, as might be the case with fusing, a field of carbon debris spreading over the rest of the wafer. Is this step carried out a wafer probe test time?

The metallic nanotube removal process is performed before the etching step which defines the standard cells. Here what they told me about VLSI-compatible Metallic CNT Removal (VMR) in an email: "The process begins by depositing a special interdigited layout structure on the wafer containing a mixture of metallic and semiconducting CNTs. These interdigitated fingers are patterned at the minimum lithographic pitch (parts of it will become the final source and drain contacts in the circuit). Electrical breakdown is performed once on the entire VMR structure, removing all metallic CNTs within the entire structure...After breakdown, sections of the VMR structure are etched out, leaving the contacts which will remain for the final circuit."

A single carbon nanotube could form a transistor channel as narrow as a single nanometer, but this technique uses many in parallel to form a single transistor channel by patterning at the lithographic limit of whatever process is being used. The researchers did not speculate on the node at which it would be prudent to implement their technology. Their next step is to characterize the speed and energy efficiency of their technique.

10nm is already well into development at Intel, with all candidate process tools in place or set to be installed before the end of the year and something like this would take many years to become viable. First equipment vendor(s) would have to be working on this for atleast a couple of quarters. There are several steps involved and working with quartz substrates may lead to issues.

Intel seems to think they can extend "traditional" CMOS to the 5nm node which should be ramping up in Hillsboro in 6 years. However this technology may actually qualify as traditional so I cannot really comment on anything that far off. But 10nm is not going to bring CNTs to the desktop.

The part about running 20 instructions from the MIPS instruction set is incorrect, or at least very misleading. This demo runs one and only one instruction, the SUBNEG instruction, from which all other instructions can, in principle, be synthesized. What the Stanford guys have done is really cool, but let's be clear about exactly what it was.

@rpcy "This demo runs one and only one instruction, the SUBNEG instruction, from which all other instructions can, in principle, be synthesized"

Thanks for the clarificaition. I guess we could say this proof of concept demo is the ultimate reduced instruciton set computer. It reminds me of early Cray supercomputers which used NAND gates to synthesize all their instructions.