Thanks Dave, good to know.
Sent from my phone
On Jan 17, 2012 10:35 AM, "David Dice" <david.dice at gmail.com> wrote:
>>> For what it's worth, +1 on the annotation proposal.
>>>> Curious - which i7 arch has 128 byte cache line? I know Netburst used to
>> have 128 as a blocked pair of two 64 byte lines, but didn't see anything
>> on
>> the newer chips.
>>>>> The line size and coherence unit is 64 bytes but adjacent sector prefetch
> when enabled (sometimes a BIOS setting), can make the coherence unit
> effectively 128 bytes, which is why I suggested extra padding to Doug.
> ASP is usually a good bet for single-threaded code, but occasionally it
> can cause destructive interference, and it can be a challenge for MP code.
>>> I think Intel officially recommends 128 bytes in their current
> optimization manuals.
>> Dave
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