DesigningFPGAsUsingtheVivadoDesignSuite3

This course demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, and optimum HDL coding techniques that help with design timing closure. This course also shows you how to debug your design using advanced capabilities of the Vivado logic analyzer.

Training Duration

2 days

Who Should Attend?

FPGA designers with intermediate knowledge of HDL and FPGA architecture and some experience with the Vivado® Design Suite