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IP DevelopereASIC

Principle design engineer with MS in Electrical Engineering/Computer Engineering and at least 10+ years of design experience and has successfully delivered complex designs to production.
Job Summary:

You will be involved in design and verification of 1G 28G protocols including but not limited to PCIe Gen 3.0/2.0/1.0, Gigabit Ethernet, XAUI, CPRI, SRIO, 10G Base-R, Interlaken, etc. You will also need to perform frontend to backend tasks using semi-custom design flow including but not limited to design, floorplanning, verification, synthesis, timing closure, ECO, power analysis, etc. You will be involved in pre-silicon and post-silicon debug and support and you will work independently with local and global counterparts.
Description: