Abstract : The purpose of this project is the design and construction of two advanced development models of a low-speed and a high-speed converter (PCM Buffer), digital-to-digital--each for inserting a number of digital data channels into Data I or Data II of the PCM Multiplexers TD-352()/U or TD-353 ()/U. The High-Speed Buffer must be capable of handling synchronous and asynchronous data; the Low-Speed unit, synchronous data only. Final circuit, logic, and mechanical design of the High-Speed Buffer was completed. A slight modification eliminates a possible lock-up state upon initial power application in the Receiver. Check-out of an assembled Card Nest of the Receiver and Transmitter was started. Printed-circuit harness card layout was completed. Except for the transit case, mechanical design was completed. Preliminary design of the Low-Speed Buffer was completed. Basic logic cards (Bistable, NAND and NOR gates) are undergoing temperature and loading tests. Printed-circuit harness card layout was completed. (Author)