9.7 Junction Field Effect Transistors (JFETs)
JFETs are, almost invariably, depletion mode devices, which means that there will be some drain current at a zero-applied gate-source potential. This current will decrease in a fairly linear manner as the reverse gate-source potential is increased, giving an operating characteristic, which is, in the case of an N-channel JFET, very similar to that of a triode valve, as shown in curve 'c' of Figure 9.3.

Like a thermionic valve, the operation of the device is limited to the range between drain (or anode) current cutoff and gate (or grid) current. In the case of the JFET, this is because the gate-channel junction is effectively a silicon junction diode—normally operated under reverse bias conditions. If the gate source voltage exceeds some 0.6 V in the forward direction, it will conduct, which will prevent gate voltage control of the channel current.

P-channel JFETs are also made, although in a more limited range of types, and these have what is virtually a mirror image of the characteristics of their N-channel equivalents, although in this case the gate-source forward conduction voltage will be of the order of -0.6 V, and drain current cutoff will occur in the gate voltage range of +3 to +8 V. Although Sony did introduce a range of junction FETs for power applications, these are no longer available, and typical contemporary JFETs cover the voltage range (maximum) from 15 to 50 V, mainly limited by the gate-drain reverse breakdown potential, and with permitted dissipations in the range 250"400 mW. Typical values of gm (usually called gfs in the case of JFETs) fall in the range of 2"6 mS.

JFETs mainly have good high-frequency characteristics, particularly the N-channel types, of which there are some designs capable of use up to 500 MHz. Modern types can also offer very low noise characteristics, although their very high input impedance will lead to high values of thermal noise if their input circuitry is also of high impedance; however, this is within the control of the circuit designer. The internal noise resistance of a JFET, R(n), is related to the gfs of the device by

R(n) ohms ≈ 0.67/gfs

and the value of gfs can be made higher by paralleling a number of channels within the chip. The Hitachi 2SK389 dual matched-pair JFET achieves a gfs value of 20 mS by this technique, with an equivalent channel thermal noise resistance of 33 ohms.2

It's lovely to see such extended treatment of JFET amplifiers. How many other people out there get the same rather wistful feeling that I do, though? The big semiconductor manufacturers have culled their JFET ranges to extinction, leaving the market mostly to specialist vendors such as Linear Systems. Depletion-mode FETs have the wonderful characteristic of being conducting when no gate potential is applied; this behaviour is really hard to replicate otherhow. There are a few depletion MOS devices out there; single-source and in quite large packages. I feel rather sad that the JFET is slowly fading from our design consciousness. What do you think?

You need to establish a base bias suffficent to operate the lower device in/near the pinchoff region, i.e., where its output impedance is reasonably high. You do not want the base voltage to (partially) track with the circuit output voltage---this tends to defeat the purpose of the cascade, which is to minimize the voltage swing on the drain of the input device, thus reducing drain-gate capacitance multiplication ("Miller effect"). In some cases it is advantageous to derive the base voltage from a sample of the actual circuit input voltage, reducing the effective FET input capacitance further---however, this will result in negative input impedance at high frequencies and potential instabilities.

I would like to explore the cascode configuration of fig. 9.15 but with Q2 replaced with a BJT. My question concerns biasing of Q2 when it is a BJT in a common base configuration. Does it matter if the base biasing resistor is connected directly to Vcc or the bottom of R2 where the Output is tapped? How do both arrangements affect the overall cascode circuit gain?