The European Spallation Source (ESS) is a Partnership of 17 European Nations committed to the goal of collectively building and operating the world's leading facility for research by use of neutrons by the second quarter of the 21st Century. The strive for innovation and the challenges that need to be overcome in order to achieve the requested performances pushed towards the adoption of one of the newest standards available on the market. ESS has decided to use MicroTCA as standard platform for the systems that require high data throughput and high uptime. The implications of this choice on the architecture of the systems will be described with emphasis on the data acquisition electronics.

The optical-link remote I/O system OPT-VME that consists of a VME master and several kinds of slave boards is widely used in SPring-8 and SACLA. As the next generation low-end platform instead of the outdated VMEbus, a Linux PLC such as Yokogawa e-RT3 has been considered. We have developed an e-RT3-based master module OPT-PLC to fully utilize a large number of existing remote boards. In the original system, low-level communication is performed by FPGA and high-level communication procedures are handled in the Solaris device driver on a VME CPU board. This driver becomes a barrier to port the system to e-RT3 platform. OPT-PLC should be handled by the e-RT3 standard driver in the same manner as other e-RT3 I/O modules. To solve the difficulty, OPT-PLC was equipped with Xilinx SoC and the high-level communication procedures were implemented as application software on ARM Linux in the SoC. As the result, OPT-PLC can be controlled through the standard e-RT3 driver. Furthermore, the system will be ported to other platform like PCI Express by replacing bus interface block in the PL part. This paper reports on our development as an approach to maximize cross-platform portability using SoC.

VME is a standard for modular electronics widely used in research institutes. Slave cards in a VME crate are controlled from a VME master, typically part of a Single Board Computer (SBC). The SBC typically runs an operating system and communicates with the VME bus through a PCI or PCIe-to-VME bridge chip. The de-facto standard bridge, TSI148, has recently been discontinued, and therefore the question arises about what bridging solution to use in new commercial SBC designs. This paper describes our effort to solve the VME bridge availability problem. Together with a commercial company, MEN, we have open-sourced their VHDL implementation of the PCIe-VME64x interface. We have created a new commodity which is free to be used in any SBC having an FPGA, thus avoiding vendor lock-in and providing a fertile ground for collaboration among institutes and companies around the VME platform. The article also describes the internals of the MEN PCIe-VME64x HDL core as well as the software package that comes with it.

Em# project is a collaboration project between MAX IV Laboratory and ALBA Synchrotron to obtain a high performant four-channel electrometer. Besides the objective of accurate current measurements down to the pico-ampere range, the project pursues to establish a reusable instrumentation platform with time stamped data collection able to perform real time calculations for flexible feedback implementations. The platform is based on a FPGA responsible of acquisition and synchronization where a real-time protocol between the modules has been implemented (Harmony) [*]. The data acquired is transmitted via PCIe to a Single Board Computer with an embedded Linux distribution where high level processing and synchronization with upper levels of Control System is executed. In this proceeding, the reasons that lead to start a complex instrument development instead of using a Commercial On the Shelf (COTS) solution will be discussed. The results of the produced units will be analyzed in terms of accuracy and processing capabilities. Finally, different Em# applications in particle accelerators will be described, further widening the functionality of the current state-of-the-art instrumentation.[*] Present and Future of Harmony Bus, a Real-Time High Speed Bus for Data Transfer Between Fpga Cores, these proceedings

PandABox is a development project resulting from a collaboration between Synchrotron SOLEIL and Diamond Light Source started in October 2015. The initial objective driving the project was to provide multi-channel encoder processing for synchronizing data acquisitions with motion systems in experimental continuous scans. The resulting system is a multi-purpose platform well adapted for multi-technique scanning and feedback applications. This flexible and modular platform embeds an industrial electronics board with a powerful Xilinx Zynq 7030 SoC (Avnet PicoZed), FMC slot, SFP module, TTL and LDVS I/Os and removable encoder peripheral modules. In the same manner, the firmware and software framework has been developed in a modular way to be easily configurable and adaptable. The whole system is open and extensible from the hardware level up to integration with control systems like TANGO or EPICS. This paper details the hardware capabilities, platform performance, framework adaptability, and the project status at both sites.szhang@synchrotron-soleil.fr

The Cryomodule-On-Chip (CMOC) simulation engine is a Verilog implementation of a cryomodule model used for Low-Level RF development for superconducting cavities. The model includes a state-space model of the accelerating fields inside a cavity, the mechanical resonances inside a cryomodule as well as their interactions. The implementation of the model along with the LLRF controller in the same FPGA allows for live simulations of an RF system. This allows for an interactive simulation framework, where emulated cavity signals are produced at the same rate as in a real system and therefore providing the opportunity to observe longer time-scale effects than in software simulations as well as a platform for software development and operator training.

A new EPICS/RTEMS IOC based on the Altera System-on-Chip (SoC) FPGA was designed at Jefferson Lab. The Altera SoC FPGA integrates a dual ARM Cortex-A9 hard processor system (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone. The embedded Altera SoC IOC has features of remote network boot via u-boot from SD card or QSPI Flash, 1Gig Ethernet, 1GB DDRs SDRAM on HPS, UART serial ports, and ISA bus interface. RTEMS for the ARM processor BSP were built with CEXP shell, which will dynamically load the EPICS applications at runtime. U-boot is the primary bootloader to remotely load the kernel image into local memory from a DHCP/TFTP server over Ethernet, and automatically run the RTEMS and EPICS. The standard SoC IOC board would be mounted in a chassis and connected to a daughter card via a standard HSMC connector. The first design of the SoC IOC will be compatible with our current PC104 IOCs, which have been running on our accelerator control system for 10 years. Eventually, the standard SOC IOCS would be the next generation of low-level IOC for the Accelerator control at Jefferson Lab.Authored by Jefferson Science Associates, LLC under U.S. DOE Contract No. DE-AC05-06OR23177.

Tokamak using superconducting magnets is becoming more and more important as long pulse operation and the ability to confine high temperature and density plasma to the interlock system to protect the device. KSTAR achieved H-mode operation for 70 seconds in 2016. In this case, it is necessary to have precise and fast operation protection device to protect Plasma Facing Component from high energy and long pulse plasma. The higher the energy of the plasma, the faster the protection device is needed, and the accurate protection logic must be realized through the high-speed operation using signals from various devices. To meet these requirements, KSTAR implemented the Fast Interlock System using Compact RIO. Implementation of protection logic is performed in FPGA, so it can process fast and various input and output. The EPICS IOC performs communication with peripheral devices, CRIO control, and DAQ. The hard-wired signal for high-speed operation from peripheral devices is directly connected to the CRIO. In this paper, we describe the detailed implementation of the FIS and the results of the fast interlock operation in the actual KSTAR operation, as well as future plans.

Particle accelerators are complex machines with fast and high power absorption peaks. Power quality is a critical aspect for correct operation. External and internal disturbances can have significant repercussions causing beam losses or severe perturbations. Mastering the load and understanding how network disturbances propagate across the network is a crucial step for developing the grid model and realizing the limits of the existing installations. Despite the fact that several off-the-shelf solutions for real time data acquisition are available, an in-house FPGA based solution was developed to create a distributed measurement system. The system can measure power and power quality on demand as well as acquire raw current and voltage data on a defined trigger, similar to a distributed oscilloscope. In addition, the system allows recording many digital signals from the high voltage switchgear enabling electrical perturbations to be easily correlated with the state of the network. The result is a scalable system with fully customizable software, written specifically for this purpose. The system prototype has been in service for two years and full-scale deployment is currently ongoing.

In this paper, the prototype of phase and amplitude detector for pulsed-RF measurement is described. The hardware is designed in VHDL and implemented using Field Programmable Gate Array (FPGA) for digital processing. The main phase and amplitude detection algorithm is implemented using state machine in the MicroBlaze soft processor. The detector system is designed to measure the phase and amplitude of a 5-microsecond wide 2,856 MHz pulsed-RF at a repetition rate of 0.5 Hz. The front-end hardware for the pulsed-RF signal acquisition is also described with the interface to the FPGA-based controller part. Initial test results of the prototype are presented.

Linear accelerator technology has been widely applied to radiotherapy machines and there has been an increasing demand of the machines in Thailand over the recent years. An attempt to increase the availability of the low-cost machines has been proposed for the domestic use purposes. Currently, the prototype of the 6 MeV medical linear accelerator is under development at Synchrotron Light Research Institute (SLRI) in Nakorn Ratchasima, Thailand. For beam shaping purposes a so-called secondary collimator is utilized with different size arrangement of the collimator jaws. The collimator motion control is one of the necessary machine subsystems for producing the desired field size of the beam. In this paper, the FPGA-based motion control system of the machine prototype is presented. The programmable logic part of the hardware is designed in VHDL for digital processing. The main motion control algorithm is implemented in the main processor of Zedboard FPGA. Communication between the motion control subsystem and the main control system software of the machine is also described.

The Muon-to-Central Trigger Processor Interface (MUCTPI) of the ATLAS experiment at the Large Hadron Collider (LHC) at CERN will be upgraded to an ATCA blade system for Run 3. The new design requires development of new communication models for control, configuration and monitoring. A System-on-Chip (SoC) with a programmable logic part and a processor part will be used for communication to the run control system and to the MUCTPI processing FPGAs. Different approaches have been compared. First, we tried an available UDP-based implementation in firmware for the programmable logic. Although this approach works as expected, it does not provide any flexibility to extend the functionality to more complex operations, e.g. for serial protocols. Second, we used the SoC processor with an embedded Linux operating system and an application-specific software written in C++ using a TCP remote-procedure-call approach. The software is built and maintained using the Yocto/OpenEmbedded framework. This approach was successfully used to test and validate the MUCTPI prototype. A third approach under investigation is the option of porting the ATLAS run control software directly to the embedded Linux.

In many nuclear applications such as nuclear/high-energy physics and nuclear fusion, sensors are widely used in order to detect high energy particles. One of the available technologies is the scintillator, which is generally coupled with a photomultiplier and pulse amplifier. The detector acquisition chain is not stationary; mainly, it changes its gain as a function of the temperature and the nuclear irradiation on the photomultiplier; therefore it needs to be periodically calibrated during its operation. A calibration method reported in the literature is based on the use of a pulsed LED that flashes on the photomultiplier by generating a train of reference pulses. A new technique may be the use of an LED with continuous sinusoidal intensity emission. This provides as an output of the detector chain a small sinusoidal signal which can be digitally processed in real time, by measuring the gain and the delay time of the detector chain. Moreover, this sinusoidal background signal can be removed in real-time, before any processing or storage of data. This paper presents the technique, reporting its simulation and the main characteristics of the developed firmware and the hardware.

At FAIR the commissioning of the re-assembled CRYRING accelerator, formerly hosted by Manne Siegbahn Laboratory Stockholm, is currently in progress. This compact low energy heavy ion synchrotron and experimental storage ring will be the main instrument for an extensive research programme [1] as well as a testing platform for the future beam instrumentation and control system concepts decided on for FAIR. Besides many other measurement systems CRYRING is equipped with 18 beam position monitors (BPM), for which a new data acquisition system (DAQ) was developed. Based on the upcoming MicroTCA form factor in combination with FPGA mezzanine card (FMC) technology the DAQ system was designed to be state-of-the-art, reliable, modular and of high performance. Testing 'Open Hardware', here the ADC FMCs and FMC carrier boards, was another intention of that concept. The DAQ layout and obstacles that had to be overcome as well as first measurements will be presented.

A prototype of medical linear accelerator is under development at Synchrotron Light Research Institute (SLRI). In order to maintain the proper operation of the machine, the pulse signal is used to synchronize the various subsystems such as electron gun, RF trigger, and magnetron trigger subsystems. In this project, we design the timing system using a XilinxSpartan-3 FPGA development board with VHDL in order to achieve the desired characteristics and sequences of the timing signals for those subsystems. A LabVIEW GUI is designed to interface with the timing system in order to control the time delay and pulse width via RS-232 serial interface. The results of the system design is achieved with the pulse resolution of a 20 nsec per step for four timing channels. The time delay and pulse width for each channel can be set independently based on the SYNC reference signal.

The IMP takes responsibility for the development of Injector II. The target energy index of it is 20-25Mev , which is an intense beam proton accelerator with high operation risk. In order to implement cutting the ion source beam in time when the beam position offset happened, the Injector II Machine Protection System is developed based on FPGA controller and PLC. This system aims to prevent device damage from continuous impact of intense beam, as well as obtains and stores status data of key devices when failures occur to implement failure location and analysis. The whole system is now operating stable in field, and the beam cutting time is less than 10us.

Funding:Work supported by the U.S. Department of Energy, Office of Science, Office of Basic Energy Sciences, under Contract No. DE-AC02-06CH11357.With the success and reliability of the transverse feedback system installed at the Advance Photon Source (APS), a major upgrade to expand the system is under way. The existing system is operating at a third of the storage ring bunch capacity, or 324 of the available 1296 bunches. This upgrade will allow the sampling of all 1296 bunches and make corrections for all selected bunches in a single storage ring turn. To facilitate this upgrade a new analog I/O board capable of 352 MHz operation was developed along with a revolution clock cleaning circuit. A 352MHz clock cleaning circuit was also required for the high-speed analog output circuit to maintain data integrity to the receiving DAC unit that is 61m away. This receiving DAC unit will have its transceiver data rate upgraded from 2.3Gbps to about 7Gbps transmitted over a fiber optic link. This paper discusses some of the challenges in reducing the clock jitter from both the system P0 bunch clock and the 352MHz clock along with the necessary FPGA hardware upgrades and algorithm changes, all of which is required for the success of this upgrade.

For the SPES project at Legnaro National Laboratories (LNL), a Low-Level Radio Frequency (LLRF) has been designed to have flexibility, reusability and an high precision. It is an FPGA-based digital feedback control system using RF ADCs for the direct undersampling and it can control at the same time eight different cavities. The LLRF system was tested on the field with an accelerated beam. In the last year some improvements on the firmware, software and hardware of the control system have been done. In this paper the results carried out in the more recent tests, the future works and the upgrades of the system will be detailed.

A new design of ESRF booster power supply system has been developed and installed. A multiple power supplies control through network including real time control is now operational at ESRF. It manages 4 power supplies to generate 3 waveforms defined with 3x1600 values in a setpoint file. The power supplies states are managed by PLCs. The ramping waveforms are managed by a real time program running on a FPGA board. And a high level control on top of them is assumed by a TANGO multiple classes system. This paper presents how these three levels of controls are interlinked and show the results achieved

When feedback loops latencies shall be lower than milliseconds range the performance of FPGA-based solutions are unrivaled. One of the main difficulties in these solutions is how to make compatible a full custom digital design with a generic interface and the high-level control software. ALBA simplified the development process of electronic instrumentation with the use of Harmony Bus (HB)*. Based on the Self-Describing Bus, developed at CERN/GSI, it creates a bus framework where different modules share timestamped data and generate events. This solution enables the high-level control software in a Single Board Computer or PC, to easily configure the expected functionally in the FPGA and manage the real-time data acquired. This framework has been already used in the new Em# electrometer**, produced within a collaboration between ALBA and MAXIV, that is currently working in both synchrotrons. Future plans include extending the FPGA cores library, high-level functions and the development of a new auto-generation tool able to dynamically create the FPGA configuration file simplifying the development process of new functionalities.* 'A Generic Fpga Based Solution for Flexible Feedback Systems', PCaPAC16, paper FRFMPLCO06 ** 'Em# Electrometer Comes To Light', ICALEPS 2017 Abstract Submitted

Funding:Wassim Mansour acknowledges support from the EUCALL project which has received funding from the European Union's H2020 research and innovation programme under grant agreement No 654220.The ESRF initiated few years ago the development of a novel platform for optimised transfer of 2D detector data based on zero-copy Remote Direct Memory Access techniques. The purpose of this new scheme, under the name of RASHPA, is to efficiently dispatch with no CPU intervention multiple parallel multi-GByte/s data streams produced by modular detectors directly from the detector head to computer clusters for data storage, visualisation and distributed data treatment. The RASHPA platform is designed to be implementable using any data link and transfer protocol that supports RDMA write operations and that can trigger asynchronous events. This paper presents the ongoing work for the first implementation of RASHPA in a real system using the hardware platform of the Medipix3 based SMARTPIX hybrid pixel detector developed at ESRF and relying on switched PCIe over cable network for data transfer. It details the implementation of the RASPHA controller at the detector side and provides input on the software for the management of the overall data acquisition system at the receiver side. The implementation and use of a PCIe switch built with components off-the-shelf is also discussed.

The GigaFRoST (Gigabit Fast Read-out System for Tomography) detector and readout system used at the tomographic microscopy beamline TOMCAT of the Swiss Light Source will be presented. GigaFRoST was built at Paul Scherrer Institute (PSI) and designed to overcome the limitations of existing commercially available high-speed CMOS detectors. It is based on a commercial CMOS fast imaging sensor (pco.dimax) with custom-designed readout electronics and control board. The latter is used for detector configuration, coordination of image readout process and system monitoring. The detector can acquire and stream data continuously at 7.7 GB/s to a dedicated backend server, using two data readout boards, each equipped with two FPGAs, and each directly connected with the server via four 10 Gbit/s fiber optics connections. The paper will focus on the implementation of the EPICS control system, data acquisition (DAQ) system, integration of the detector into the beamline infrastructure and implementation of efficient distribution of TTL triggers between the devices involved in the experiments (i.e. GigaFRoST detector, sample rotation stage, arbitrary external devices).

Funding:Work supported by the US Department of Energy, Office of Science under contract DE-AC02-76SF00515LCLS-II's high beam rate of almost 1MHz and the requirement that several "high-performance" systems (such as MPS, BPM, LLRF, timing etc.) shall resolve individual bunches precludes the use of a traditional software based control system but requires many core services to be implemented in FPGA logic. SLAC has created a comprehensive open-source firmware framework which implements many commonly used blocks (e.g., timing, globally-synchronized fast data buffers, MPS, diagnostic data capture), libraries (Ethernet protocol stack, AXI interconnect, FIFOs, memory etc.) and interfaces (e.g., for timing, diagnostic data etc.) thus providing a versatile platform on top of which powerful high-performance systems can be built and rapidly integrated.

Waveform monitoring system plays a special role in the control system of powerful pulse installations providing the most complete information about the installation functioning and its parameters. The report describes the family of VME modules used in the waveform monitoring system of a linear induction accelerator LIA-20. In order to organize inter-module synchronization the VME-64 bus extension implemented in the VME64-BINP crates is applied in the waveform digitizers.

PandABlocks is the open source firmware and software stack that powers PandABox, a Zynq SoC based "Position and Acquisition" platform for delivering triggers during multi-technique scanning. PandABlocks consists of a number of FPGA functional blocks that can be wired together at run-time according to application specific requirements. Status reporting and high speed data acquisition is handled by the onboard ARM processor and exposed via a TCP server with a protocol suitable for integration into control systems like "EPICS" or "TANGO". Also included in the framework is a webserver and web GUI to visualize and change the wiring of the blocks. The whole system adapts to the functional blocks present in the current FPGA build, allowing different FPGA firmware be created to support new FMC cards without rebuilding the TCP server and webserver. This paper details how the different layers of PandABlocks work together and how the system can be used to implement novel triggering applications.

Controls and data acquisition in accelerators often involve some kind of computing platform (VME, PICMG 1.3, MTCA.4…) connected to Distributed I/O Tier electronics using a fieldbus or another kind of serial link. At CERN, we have started a project to rationalize this tier, providing a modular centrally-supported platform which allows equipment groups to focus on solving their particular problems while benefiting from a set of well-debugged building blocks. The paper describes the strategy, based on 3U Euro crates with a generic FPGA-based board featuring space for FMC mezzanines. Different mezzanines allow communication using different protocols. There are two variants of the electronics, to deploy in environments with and without radiation tolerance requirements. The plans we present are the result of extensive discussion at CERN among all stakeholders. We present them here with the aim of gathering further feedback and potential interest for inter-lab collaborations.

Sub-nsec precision time synchronization is requested for data-acquisition components distributed over up to tens of km2 in modern astroparticle experiments, like upcoming Gamma-Ray and Cosmic-Ray detector arrays, to ensure optimal triggering, pattern recognition and background rejection. The White-Rabbit (WR) standard for precision time and frequency transfer is well suited for this purpose. We present two multi-channel general-purpose TDC units, which are firmware-implemented on two widely used WR-nodes: the SPEC (Spartan 6) and ZEN (Zynq) boards. Their main features: TDCs with 1 nsec resolution (default), running deadtime-free and capable of local buffering and centralized level-2 trigger architectures. The TDC stamps pulses are in absolute TAI. With off-the-shelve mezzanine boards (5ChDIO-FMC-boards), up to 5 TDC channels are available per WR-node. Higher density, customized simple I/O boards allow to turn this into 8 to 32-channel units, with an excellent price to performance ratio. The TDC units have shown excellent long-term performance in a harsh environment application at TAIGA-HiSCORE/Siberia, for the Front-End DAQ and the central GPSDO clock facility.

In addition to the large LHC experiments, CERN hosts a number of other experimental areas with a rich research program ranging from fundamental physics to medical applications. The risk assessments have shown a large palette of potential hazards (radiological, electrical, chemical, laser, etc.) that need to be properly mitigated in order to ensure the safety of personnel working inside these areas. A Personnel Protection System, typically, accomplishes this goal by implementing a certain number of heterogeneous functionalities as interlocks of critical elements, management of a local HMI, data monitoring and interfacing with RFID badge readers. Given those requirements, reducing system complexity and costs are key parameters to be optimized in the solution. This paper is aimed at summarizing the findings, in terms of costs, complexity and maintenance reduction, offered by a technology from National Instruments® based on cRIO controllers and a new series of SIL-2 certified safety I/O modules. A use case based on a service for the protection of Class 4 laser laboratories will be described in detail.

We describe the development of firmware to support Longitudinal Bunch by Bunch Feedback at Diamond Light source. As well as feedback, the system supports complex experiments and the capture of detailed electron beam diagnostics. In this paper we describe the firmware development and some details of the processing chain. We focus on some of the challenges of FPGA development from the perspective of a software engineer.

At the European Spallation Source it is foreseen to use around 120 superconducting cavities operating at 704.42 MHz. Each cavity will require an individual LLRF control system, that needs to be tested before the installation inside the accelerator. Testing of all systems using the real superconducting cavities would be very expensive and in case of a failure can lead to serious damages. To lower the testing cost and avoid potential risks it is planned to design and build a device that simulates the behavior of a superconducting cavity. The cavity simulator will utilize fast data converters equipped with an RF front-end and a digital signal processing unit based on a high performance FPGA. In this paper conceptual design of hardware and firmware will be presented.

The European Spallation Source (ESS) is a collaboration of 17 European countries that is building a leading neutron research center in Lund, Sweden. The ESS facility will have the most powerful neutron source in the world, providing 5 MW of beam power. The Integrated Control Systems Division (ICS) is responsible for all the control systems for the whole facility. For the accelerator control system, ICS will provide different hardware platforms according to the requirements of each specific system. For high performance systems, demanding high data throughput, the hardware platform is the MicroTCA.4 standard. This work presents the software stack that makes the integration of a high-end MicroTCA.4 hardware into the ESS Control System, with the implementation details of the FPGA firmware framework, kernel and userspace drivers, EPICS device support and finally the EPICS IOC that controls the MicroTCA.4 boards.

The Linac Coherent Light Source II (LCLS-II) is a major upgrade of the LCLS facility at SLAC, scheduled to start operations in 2020. The High Performance Systems (HPS) defines a set of LCLS-II controls sub-systems which are directly impacted by its 1 MHz operation. It is formed around a few key concepts: ATCA based packaging, digital and analog application boards, and 10G Ethernet based interconnections for controls. The Common Platform provides the common parts of the HPS in term of hardware, firmware, and software. The Common Platform Software (CPSW) provides a standardized interface to the common platform's FPGA for all high-level software. YAML is used to define the hardware topology and all necessary parameters. YCPSWASYN is an asynPortDriver based EPICS module for FPGA register access and asynchronous messaging using CPSW. YCPSWSYN has two operation modes: an automatic mode where PVs are automatically created for all registers and the record's fields are populated with information found in YAML; and a manual mode where the engineer can choose which register to expose via PVs and freely choose the record's filed information.