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AR# 14669

Virtex-II Pro RocketIO - Why are TX_BUFFER_USE and RX_BUFFER_USE always set to TRUE? Can I change them?

Description

The RocketIO User Guide states that TX_BUFFER_USE and RX_BUFFER_USE are always set to TRUE. Can these FIFOs be bypassed?

Solution

You may change these attributes to FALSE, but the following considerations should first be taken into account:

TX_BUFFER_USE set to FALSE:

- Without TX FIFO, data is clocked directly from the TXUSRCLK domain to the REFCLK domain without any buffering.

- The phase relationship between TXUSRCLK and REFCLK is unpredictable because each is typically distributed by a different means, REFCLK from IBUFG, and TXUSRCLK from DCM + BUFG.

- The phase relationship between transceivers may vary for the same reason.

Because of these factors, reliable operation without the TX FIFO is not guaranteed. For applications that have a higher jitter tolerance, REFCLK and TXUSRCLK may be distributed together (via BUFG), yielding a low skew between them at the MGT. Reliable operation without the TX FIFO may be possible in this situation, but this has not yet been verified in silicon.

RX_BUFFER_USE set to FALSE:

- Without the RX FIFO, RXUSRCLK must be driven from RXRECCLK; however, the phase relationship between the two clocks is unpredictable (after RXRECCLK has been brought out to the fabric, perhaps routed through DCM and/or BUFG, and brought back to the MGT).

- The phase relationship may vary between transceivers if RXRECCLK from one transceiver is delivered as RXUSRCLK to multiple transceivers.

Because of these factors, reliable operation without the RX FIFO is not guaranteed. Sophisticated techniques may establish reliable use of RXRECLK as RXUSRCLK with a bypassed RX FIFO (this would have to be performed separately for each transceiver). Such techniques have not yet been proven, however.