905062018-10-10Radiation Hardened High Speed Integrated Circuits SERDES I/O for Extreme Operating Environments, Phase ICompletedJun 2016Dec 2016Manned and robotic space missions require high-performance electronic control systems capable of operating for extended periods in harsh environments subject to radiation, extreme temperatures, vibration and shock. Semiconductor technologies capable of meeting these demanding requirements tend to have limited capabilities, are expensive, and are not easily configured for specific mission requirements. Leading-edge applications will benefit from the ability to implement high speed interconnect protocols between host processors and system slaves, such as sensors, actuators, power managers, imagers and transceivers. The development of a Radiation Hardened Serializer/Deserializer (SERDES) embedded macro is proposed for insertion into digital integrated circuits (ICs) suitable for scalable single and multi-core processors, special purpose logic functions and scalable memory blocks on a space-qualified, radiation hardened integrated circuit digital fabric. A NASA-funded Structured ASIC architecture is under development at Micro-RDC, capable of meeting space-grade requirements while creating a cost-effective, quick-turn development environment. The SASIC fabric will implement known Radiation-Hardened-By-Design (RHBD) techniques on an advanced 32nm CMOS SOI process, supporting high-density, high-speed low-power implementations. A unique Digital Logic Tile architecture with through-seal-ring connections allows the designer to define single or multi-core processors, dedicated logic functions, scalable memory blocks and user-defined I/Os; all on a single, scalable integrated circuit. The 32nm platform (fabric) development incorporates the RHBD building-blocks (e.g. flip-flops, gates, distributed memory, block memory, I/O) required for the systems designer to implement functional blocks for application-specific requirements. During this project a high speed SERDES physical layer macro will be developed for insertion into more complex digital processing elements.NASA supports various requirements ranging from science missions, space station, and deep space missions requiring high-performance computing and controls. Interplanetary and long term low Earth orbit systems require radiation tolerances capable of ensuring that the on-board electronics outlast the life expectancy of the systems. These demanding requirements of radiation tolerance and harsh operating environments force satellite systems developers to consider capabilities that are uniquely optimized for their applications. The Structured ASIC solves the dilemma of balancing performance, cost, risk and time to deployment against alternative solutions. Scalable, high performance control systems can support a wide range of applications when design flexibility is readily available. The ability to right-size integrated circuits while adding features, such as high speed SERDES communication links, while maintaining performance at low costs enables the use of this technology across a wide range of programs and applications. NASA programs/missions that will benefit include the Thermal Infrared Sensor (TIRS) mission, Climate Absolute Radiance and Refractivity Observatory (CLARREO), BOReal EcosystemAtmosphere Study (BOREAS) and the Methane Trace Gas Sounder. Longer term missions include lunar landers and orbiters, Mars missions (MAVEN), solar system exploration (e.g. Titan, Juno, Europa, comet nucleus return, New Discovery, and Living with a Star (LWS)).<br /><br />Companies that deploy satellites for purposes similar to NASA's Earth-centric applications will greatly benefit from this technology for the same reasons as NASA. There are, however, a number of additional applications that require this kind of performance. Military, intelligence and commercial satellites will show growing demand in units deployed and performance. The 2014 FAA Commercial Space Transportation Forecasts predicts that an average of seventy eight commercial payloads will be launched annually over the next decade. A reasonable estimate of the number of classified military and intelligence payloads at least equals the commercial deployments. Micro-RDC currently offers 90nm, 50MHz RHBD Structured ASICs capable of handling low to mid-range control and compute requirements in space. The 32nm 300MHz capabilities in this proposal greatly improve densities and processing speed, including the ability to add high speed SERDES communication links. These links will enhance multi-processsor, multi-node computing, as well as enable communications to multiple peripheral functions such as sensors, actuators, image capture and processing subsystems and data communications links.233SBIR/STTRSpace Technology Mission DirectorateJet Propulsion LaboratoryJPLNASA CenterPasadenaCAMicroelectronics Research Development CorporationIndustryColorado SpringsCOColoradoTherese GriebelCarlos TorrezGreg Pauls41723Briefing ChartDocumentRadiation Hardened High Speed Integrated Circuits SERDES I/O for Extreme Operating Environments, Phase I Briefing Chart31504https://techport.nasa.gov/file/315046597130972Briefing Chart ImageImageRadiation Hardened High Speed Integrated Circuits SERDES I/O for Extreme Operating Environments, Phase I22677https://techport.nasa.gov/file/2267749116