2016-12-10T01:17:02ZPyramic array: An FPGA based platform for many-channel audio acquisitionhttp://hdl.handle.net/2117/97459
Pyramic array: An FPGA based platform for many-channel audio acquisition
Azcarreta Ortiz, Juan
Microphone arrays techniques present compelling applications for robotic implementations. Those techniques can allow robots to listen to their environment and infer clues from it. Such features might enable capabilities such as natural interaction with humans, interpreting spoken commands or the localization of victims during search and rescue tasks. However, under noisy conditions robotic implementations of microphone arrays might degrade their precision when localizing sound sources. For practical applications, human hearing still leaves behind microphone arrays. Daniel Kisch is an example of how humans are able to efficiently perform echo-localization to recognize their environment, even in noisy and reverberant environments. For ubiquitous computing, another limitation of acoustic localization algorithms is within their capabilities of performing real-time Digital Signal Processing (DSP) operations. To tackle those problems, tradeoffs between size, weight, cost and power consumption compromise the design of acoustic sensors for practical applications. This work presents the design and operation of a large microphone array for DSP applications in realistic environments. To address those problems this project introduces the Pyramic sound capture system designed at LAP in EPFL. Pyramic is a custom hardware which possesses 48 microphones dis- tributed in the edges of a tetrahedron. The microphone arrays interact with a Terasic DE1-SoC board from Altera Cyclone V family devices, which combines a Hard Processor System (HPS) and a Field Programmable Gate Array (FPGA) in the same die. The HPS part integrates a dual- core ARM-based Cortex-A9 processor, which combined with the power of FPGA design suitable for processing multichannel microphone signals. This thesis explains the implementation of the Pyramic array. Moreover, FPGA-based hardware accelerators have been designed to imple- ment a Master SPI communication with the array and a parallel 48 channels FIR filters cascade of the audio data for delay-and-sum beamforming applications. Additionally, the configura- tion of the HPS part allows the Pyramic array to be controlled through a Linux based OS. The main purpose of the project is to develop a flexible platform in which real-time echo-location algorithms can be implemented. The effectiveness of the Pyramic array design is illustrated by testing the recorded data with offline direction of arrival algorithms developed at LCAV in EPFL.
Array processing of audio data has many interesting applications: acoustic beamforming, source separation, indoor localization, room geometry estimation, etc. Recent advances in MEMS has produced tiny microphones, analog or even with digital converter integrated. This opens the door to create arrays with a massive number of microphones. We dub such an array many-channel by analogy to many-core processors.
2016-11-29T16:30:49ZAzcarreta Ortiz, JuanMicrophone arrays techniques present compelling applications for robotic implementations. Those techniques can allow robots to listen to their environment and infer clues from it. Such features might enable capabilities such as natural interaction with humans, interpreting spoken commands or the localization of victims during search and rescue tasks. However, under noisy conditions robotic implementations of microphone arrays might degrade their precision when localizing sound sources. For practical applications, human hearing still leaves behind microphone arrays. Daniel Kisch is an example of how humans are able to efficiently perform echo-localization to recognize their environment, even in noisy and reverberant environments. For ubiquitous computing, another limitation of acoustic localization algorithms is within their capabilities of performing real-time Digital Signal Processing (DSP) operations. To tackle those problems, tradeoffs between size, weight, cost and power consumption compromise the design of acoustic sensors for practical applications. This work presents the design and operation of a large microphone array for DSP applications in realistic environments. To address those problems this project introduces the Pyramic sound capture system designed at LAP in EPFL. Pyramic is a custom hardware which possesses 48 microphones dis- tributed in the edges of a tetrahedron. The microphone arrays interact with a Terasic DE1-SoC board from Altera Cyclone V family devices, which combines a Hard Processor System (HPS) and a Field Programmable Gate Array (FPGA) in the same die. The HPS part integrates a dual- core ARM-based Cortex-A9 processor, which combined with the power of FPGA design suitable for processing multichannel microphone signals. This thesis explains the implementation of the Pyramic array. Moreover, FPGA-based hardware accelerators have been designed to imple- ment a Master SPI communication with the array and a parallel 48 channels FIR filters cascade of the audio data for delay-and-sum beamforming applications. Additionally, the configura- tion of the HPS part allows the Pyramic array to be controlled through a Linux based OS. The main purpose of the project is to develop a flexible platform in which real-time echo-location algorithms can be implemented. The effectiveness of the Pyramic array design is illustrated by testing the recorded data with offline direction of arrival algorithms developed at LCAV in EPFL.Three-axes attitude determination and control system based on magnetorquers for small satelliteshttp://hdl.handle.net/2117/91492
Three-axes attitude determination and control system based on magnetorquers for small satellites
Vidal Mateu, David
This projects takes the desing and implementation of an attitude determination and control subsystem for the 3Cat-2 Mission. The system has to be able to correct the different perturbations and point the satellite to the desired orientation according to the working mode of the satellite. The subsystem has to be able to correct the different sensing perturbations and compute all the different attitude parameters to control the satellite. The design is divided in three different modes: Detumbling, Sun-safe, and Nominal. The Detumbling Mode is in charge of stabilizing the satellite rotation after the launch or when some other of the controllers has had a problem, and it induces a high rotation over the satellite. The Sun-safe is in charge of pointing the largest solar panels to the Sun to charge the batteries. Finally, the Nominal has to point the payload antennas to the Nadir (Earth Center) for performing the mission of the satellite. Each mode will make use of different sensors to save as much energy as possible. The work will be based on the usual algorithms used in different satellite mission and looking for a new and the first complex implementation of an Attitude subsystem for the Nanosatellite Laboratory.
In this TFM the attitude determination and control system for the 3Cat-2 nanosatellite will be implemented, including the sun sensors, 3 axes magnetometers and 3 axes gyroscopes to determine the satellite's attitude, and three axes magnetorquers as actuators. Algorithms will be tested in a Matlab-based simulation environment and then converted into C, to be executed in the Nanomind (on board computer) of 3Cat-2. Algorithm performance should be evaluated in an air bearing in the center of a 3 axes Helmholtz coils.
2016-11-04T14:10:25ZVidal Mateu, DavidThis projects takes the desing and implementation of an attitude determination and control subsystem for the 3Cat-2 Mission. The system has to be able to correct the different perturbations and point the satellite to the desired orientation according to the working mode of the satellite. The subsystem has to be able to correct the different sensing perturbations and compute all the different attitude parameters to control the satellite. The design is divided in three different modes: Detumbling, Sun-safe, and Nominal. The Detumbling Mode is in charge of stabilizing the satellite rotation after the launch or when some other of the controllers has had a problem, and it induces a high rotation over the satellite. The Sun-safe is in charge of pointing the largest solar panels to the Sun to charge the batteries. Finally, the Nominal has to point the payload antennas to the Nadir (Earth Center) for performing the mission of the satellite. Each mode will make use of different sensors to save as much energy as possible. The work will be based on the usual algorithms used in different satellite mission and looking for a new and the first complex implementation of an Attitude subsystem for the Nanosatellite Laboratory.3D bunch-by-bunch feedback system at ANKA to increase storable beam currenthttp://hdl.handle.net/2117/90662
3D bunch-by-bunch feedback system at ANKA to increase storable beam current
Egidos Plaja, Núria
In the ANKA storage ring, a digital state-of-the-art Bunch-By-Bunch (BBB) feedback system provides damping of Coupled-Bunch-Instabilities (CBI) in order to increase the maximum storable beam current and lifetime. Performance of this feedback strongly depends on the phase advance in the digital Finite Impulse Response (FIR) filter. Especially during energy ramping, retuning of FIR filter parameters is required as the electron beam?s tune varies with changing machine optics. With this purpose, an algorithm for the automatic tuning of the filter is proposed. Tests performed during several energy rampings show an improvement in rejection of instabilities, which means robustness of the feedback system against changes in machine settings is enhanced. Beam lifetime is also a critical parameter to evaluate performance of the storage ring. It is related to bunch length in the longitudinal axis, which must not be too short to reduce beamloss. So as to increase bunch length and thus enhance beam lifetime, beam modulation at quadrupole resonance is applied in longitudinal axis. An algorithm for the automatic configuration of this modulation has been implemented and tested during injection. Results show a significant enhancement of beam lifetime, but reproducibility of these results will be discussed.; En el anillo de almacenaje ANKA, un sistema de retroalimentación digital Paquete-Por-Paquete (Bunch-By-Bunch, BBB) de última generación proporciona la atenuación de inestabilidades derivadas del acoplamiento entre paquetes (Coupled-Bunch-Instabilities, CBI), con objeto de incrementar el máximo nivel de corriente almacenable y el tiempo de vida del haz de partículas. Las prestaciones de la retroalimentación dependen fuertemente del avance de fase introducido por el filtro digital de respuesta impulsional finita (Finite Impulse Response, FIR). De manera especial durante la rampa de energía, es necesario reajustar los parámetros del filtro FIR para compensar la variación de la frecuencia característica del haz de electrones, que cambia en relación a la óptica del acelerador (machine optics). Con este objetivo, el presente trabajo propone un algoritmo para la sintonía automática del filtro. En las pruebas llevadas a cabo durante diversas rampas de energía, se ha observado una mejora en el rechazo de las inestabilidades, de forma que se refuerza la robustez del sistema de retroalimentación frente a los cambios en la configuración del acelerador. El tiempo de vida del haz de partículas es otro parámetro crítico a la hora de evaluar las prestaciones del anillo de almacenaje. Está relacionado con la longitud del paquete en el eje longitudinal, que no debe ser demasiado corta para reducir la pérdida de partículas. Con el objetivo de incrementar la longitud del paquete y con ello, el tiempo de vida, se aplica una modulación a la frecuencia de resonancia de cuarto orden en el eje longitudinal. En este trabajo, se ha implementado un algoritmo para la configuración automática de la modulación, que se ha puesto a prueba durante la inyección. Los resultados muestran una mejora significativa en el tiempo de vida, pero se comentará la reproducibilidad de los mismos.; A l’anell d’emmagatzematge ANKA, un sistema de retroalimentació digital Paquet-Per-Paquet (Bunch-By-Bunch, BBB) d’última generació proporciona l’esmorteïment d’inestabilitats derivades de l’acoblament entre paquets (Coupled-Bunch-Instabilities, CBI), per tal d’incrementar el màxim nivell de corrent emmagatzemable i el temps de vida del feix de partícules. Les prestacions de la retroalimentació depenen fortament de l’avançament de fase introduït pel filtre digital de resposta impulsional finita (Finite Impulse Response, FIR). De manera especial durant la rampa d’energia, és necessari reajustar els paràmetres del filtre FIR per tal de compensar la variació de la freqüència característica del feix d’electrons, que canvia amb la configuració de l’òptica de l’accelerador (machine optics). Amb aquest objectiu, en aquest treball es proposa un algorisme per a la sintonia automàtica del filtre. A les proves que s’han dut a terme durant diverses rampes d’energia, s’ha observat una millora en el rebuig de les inestabilitats, de manera que es reforça la robustesa del sistema de retroalimentació enfront als canvis en la configuració de l’accelerador. El temps de vida del feix de partícules és un altre paràmetre crític a l’hora d’avaluar les prestacions de l’anell d’emmagatzematge. Està relacionat amb la longitud del paquet de partícules en l’eix longitudinal, que no ha de ser massa curta per tal de reduir la pèrdua de partícules. Amb l’objectiu d’incrementar la longitud del paquet i amb això, el temps de vida, s’aplica una modulació a la freqüència de ressonància de quart ordre en l’eix longitudinal. En aquest treball, s’ha implementat un algorisme per a la configuració automàtica de la modulació, que s’ha provat durant la injecció. Els resultats mostren una millora significativa en el temps de vida, però es comentarà la reproductibilitat d’aquests resultats.
2016-10-11T08:59:52ZEgidos Plaja, NúriaIn the ANKA storage ring, a digital state-of-the-art Bunch-By-Bunch (BBB) feedback system provides damping of Coupled-Bunch-Instabilities (CBI) in order to increase the maximum storable beam current and lifetime. Performance of this feedback strongly depends on the phase advance in the digital Finite Impulse Response (FIR) filter. Especially during energy ramping, retuning of FIR filter parameters is required as the electron beam?s tune varies with changing machine optics. With this purpose, an algorithm for the automatic tuning of the filter is proposed. Tests performed during several energy rampings show an improvement in rejection of instabilities, which means robustness of the feedback system against changes in machine settings is enhanced. Beam lifetime is also a critical parameter to evaluate performance of the storage ring. It is related to bunch length in the longitudinal axis, which must not be too short to reduce beamloss. So as to increase bunch length and thus enhance beam lifetime, beam modulation at quadrupole resonance is applied in longitudinal axis. An algorithm for the automatic configuration of this modulation has been implemented and tested during injection. Results show a significant enhancement of beam lifetime, but reproducibility of these results will be discussed.
En el anillo de almacenaje ANKA, un sistema de retroalimentación digital Paquete-Por-Paquete (Bunch-By-Bunch, BBB) de última generación proporciona la atenuación de inestabilidades derivadas del acoplamiento entre paquetes (Coupled-Bunch-Instabilities, CBI), con objeto de incrementar el máximo nivel de corriente almacenable y el tiempo de vida del haz de partículas. Las prestaciones de la retroalimentación dependen fuertemente del avance de fase introducido por el filtro digital de respuesta impulsional finita (Finite Impulse Response, FIR). De manera especial durante la rampa de energía, es necesario reajustar los parámetros del filtro FIR para compensar la variación de la frecuencia característica del haz de electrones, que cambia en relación a la óptica del acelerador (machine optics). Con este objetivo, el presente trabajo propone un algoritmo para la sintonía automática del filtro. En las pruebas llevadas a cabo durante diversas rampas de energía, se ha observado una mejora en el rechazo de las inestabilidades, de forma que se refuerza la robustez del sistema de retroalimentación frente a los cambios en la configuración del acelerador. El tiempo de vida del haz de partículas es otro parámetro crítico a la hora de evaluar las prestaciones del anillo de almacenaje. Está relacionado con la longitud del paquete en el eje longitudinal, que no debe ser demasiado corta para reducir la pérdida de partículas. Con el objetivo de incrementar la longitud del paquete y con ello, el tiempo de vida, se aplica una modulación a la frecuencia de resonancia de cuarto orden en el eje longitudinal. En este trabajo, se ha implementado un algoritmo para la configuración automática de la modulación, que se ha puesto a prueba durante la inyección. Los resultados muestran una mejora significativa en el tiempo de vida, pero se comentará la reproducibilidad de los mismos.
A l’anell d’emmagatzematge ANKA, un sistema de retroalimentació digital Paquet-Per-Paquet (Bunch-By-Bunch, BBB) d’última generació proporciona l’esmorteïment d’inestabilitats derivades de l’acoblament entre paquets (Coupled-Bunch-Instabilities, CBI), per tal d’incrementar el màxim nivell de corrent emmagatzemable i el temps de vida del feix de partícules. Les prestacions de la retroalimentació depenen fortament de l’avançament de fase introduït pel filtre digital de resposta impulsional finita (Finite Impulse Response, FIR). De manera especial durant la rampa d’energia, és necessari reajustar els paràmetres del filtre FIR per tal de compensar la variació de la freqüència característica del feix d’electrons, que canvia amb la configuració de l’òptica de l’accelerador (machine optics). Amb aquest objectiu, en aquest treball es proposa un algorisme per a la sintonia automàtica del filtre. A les proves que s’han dut a terme durant diverses rampes d’energia, s’ha observat una millora en el rebuig de les inestabilitats, de manera que es reforça la robustesa del sistema de retroalimentació enfront als canvis en la configuració de l’accelerador. El temps de vida del feix de partícules és un altre paràmetre crític a l’hora d’avaluar les prestacions de l’anell d’emmagatzematge. Està relacionat amb la longitud del paquet de partícules en l’eix longitudinal, que no ha de ser massa curta per tal de reduir la pèrdua de partícules. Amb l’objectiu d’incrementar la longitud del paquet i amb això, el temps de vida, s’aplica una modulació a la freqüència de ressonància de quart ordre en l’eix longitudinal. En aquest treball, s’ha implementat un algorisme per a la configuració automàtica de la modulació, que s’ha provat durant la injecció. Els resultats mostren una millora significativa en el temps de vida, però es comentarà la reproductibilitat d’aquests resultats.Very deep convolutional neural networks for face identificationhttp://hdl.handle.net/2117/90109
Very deep convolutional neural networks for face identification
Vilardi, Alessandro Luca
The goal of this thesis is to evaluate the face identification problem using very deep convolutional neural networks. In recent years, the use of CNN, with a large amount of images in databases, have made the deep learning technique very performant. The problems in training a network from scratch, such as having sufficient hardware resources and large databases, can be overcome using the finetune technique on pretrained models. This thesis evaluate the performance in finetuning for face classification the most recent CNN architectures which have obtained the best results at ImageNet Large-Scale Visual Recognition Challenge (ILSVRC) in the last years, in particular VGG, GoogLeNet and ResNet. All the pre-trained models of the CNNs were downloaded from the MatConvNet website. VGG-16 has shown best results in face classification which was followed with ResNet-101 and GoogLeNet that are the matter of this thesis.
In very recent years, several classification problems in computer vision, have boosted its performance by using Deep Learning techniques, in particular Convolutional Neural Networks (CNNs). The topic of the research project will focus in exploring state of the art deep learning architectures in computer vision applications. Recently architectures like GoogleNet and VGG have shown to perform better than other architectures.
2016-09-21T12:44:42ZVilardi, Alessandro LucaThe goal of this thesis is to evaluate the face identification problem using very deep convolutional neural networks. In recent years, the use of CNN, with a large amount of images in databases, have made the deep learning technique very performant. The problems in training a network from scratch, such as having sufficient hardware resources and large databases, can be overcome using the finetune technique on pretrained models. This thesis evaluate the performance in finetuning for face classification the most recent CNN architectures which have obtained the best results at ImageNet Large-Scale Visual Recognition Challenge (ILSVRC) in the last years, in particular VGG, GoogLeNet and ResNet. All the pre-trained models of the CNNs were downloaded from the MatConvNet website. VGG-16 has shown best results in face classification which was followed with ResNet-101 and GoogLeNet that are the matter of this thesis.Design of a 16-bit 50-kHz low-power SC delta-sigma modulator for ADC in 0.18um CMOS technologyhttp://hdl.handle.net/2117/89800
Design of a 16-bit 50-kHz low-power SC delta-sigma modulator for ADC in 0.18um CMOS technology
Cisneros Fernández, Jose Agustin
A general purpose 16 Bits Sigma-Delta modulator ADC for double precision audio 50 kHz bandwidth, targeted for Low-power operation, involving no additional digital circuit compensation, no bootstrapping techniques and resistor-less topologies, and relaying on Switched Capacitor Sigma-Delta modulator topologies for robust operation and insensitivity to process and temperature variations, is presented in this work. Designed in a commercial 180 nm technology, the whole circuit static current is calculated in 620 uA with a nominal voltage supply of 1.8 V, performing a Schreier FOM of 174.16 dB. This outstanding state-of-the-art forseen FOM is achieved by the use of architectural and circuital Low-power techniques. At the architectural level a single loop Low-distortion topology with the optimum order and coefficients have been chosen, while at circuit level very novel OTA based on Variable Mirror Amplifiers allows an efficient Class-AB operation. Specially optimized switched variable mirror amplifiers with a novel design methodology based on Bottom-up approach, allows faster design stages ensuring feasable circuit performance at architectural level without the need of large iterative simulations of the complete SC Sigma-Delta modulator. Simulation results confirms the complete optimization process and the metioned advantages with respect to the tradicional approach.
This Master Thesis work aims to design a low power high-resolution Delta-Sigma modulator for ADC in a low-cost standard mixed-mode CMOS technology. For this purpose, a single-bit single loop Delta-Sigma architecture will be selected in order to mitigate distortion issues caused by technology mismatching. Also, the switched capacitor (SC) circuit implementation of the Delta-Sigma modulator will avoid the use of any internal voltage supply bootstrapping for biasing critical switches in favor of extending IC lifetime. The designer will take benefit of the low-power Class-AB Op
2016-09-09T13:32:21ZCisneros Fernández, Jose AgustinA general purpose 16 Bits Sigma-Delta modulator ADC for double precision audio 50 kHz bandwidth, targeted for Low-power operation, involving no additional digital circuit compensation, no bootstrapping techniques and resistor-less topologies, and relaying on Switched Capacitor Sigma-Delta modulator topologies for robust operation and insensitivity to process and temperature variations, is presented in this work. Designed in a commercial 180 nm technology, the whole circuit static current is calculated in 620 uA with a nominal voltage supply of 1.8 V, performing a Schreier FOM of 174.16 dB. This outstanding state-of-the-art forseen FOM is achieved by the use of architectural and circuital Low-power techniques. At the architectural level a single loop Low-distortion topology with the optimum order and coefficients have been chosen, while at circuit level very novel OTA based on Variable Mirror Amplifiers allows an efficient Class-AB operation. Specially optimized switched variable mirror amplifiers with a novel design methodology based on Bottom-up approach, allows faster design stages ensuring feasable circuit performance at architectural level without the need of large iterative simulations of the complete SC Sigma-Delta modulator. Simulation results confirms the complete optimization process and the metioned advantages with respect to the tradicional approach.Diseño de interfaz entre una placa Beaglebone y periféricos mediante el bus GPMChttp://hdl.handle.net/2117/88248
Diseño de interfaz entre una placa Beaglebone y periféricos mediante el bus GPMC
Suárez Vicente, Eugenia
Desarrallo de una interfaz funcional entre un periférico de memoria externa y una Beaglebone mediante: Diseño hardware, para el elemento periférico y programación del driver GPMC, en el lado de la CPU para activar protocolos de acceso a periféricos.
2016-06-22T15:21:16ZSuárez Vicente, EugeniaDesarrallo de una interfaz funcional entre un periférico de memoria externa y una Beaglebone mediante: Diseño hardware, para el elemento periférico y programación del driver GPMC, en el lado de la CPU para activar protocolos de acceso a periféricos.Design of low-dropout regulator for ultra low power on-chip applicationshttp://hdl.handle.net/2117/88184
Design of low-dropout regulator for ultra low power on-chip applications
Aymerich Gubern, Joan
Low Drop Out (LDO) voltage regulators are commonly used to supply low-voltage digital circuits such as microprocessor cores. These digital circuits normally are continuously changing from one mode of operation to another. Therefore, the load demand can change rapidly resulting in large voltage transients at the output of the regulator which can adversely affect the digital circuitry. In this Master's Thesis, design topologies and challenges of very low-power fully integrated On-Chip Low-Dropout (LDO) regulators have been analyzed. Instead of conventional LDO which makes use of a large external capacitor to have better dynamic response and stability, a CapacitorLess LDO (CL-LDO) is chosen on considerations of smaller area. The most challenging part of designing this kind of regulator is achieving high current efficiency by reducing the quiescent current while ensuring good stability response as well as good regulation performance. Thus, different circuit techniques must be carefully added in order to balance the lack of the large external capacitor having the minimum impact on system efficiency. This work focuses on designing a fully integrated low-dropout regulator with good dynamic performance, high regulation performance and ultra-low power consumption. The stability is achieved by the use of two pole-splitting techniques, namely Cascode and Nested-Miller compensation. The good dynamic response with low quiescent current are achieved by the use of an adaptive biasing circuit, a gm-boost circuit and adaptive power transistor architecture.
2016-06-21T07:39:55ZAymerich Gubern, JoanLow Drop Out (LDO) voltage regulators are commonly used to supply low-voltage digital circuits such as microprocessor cores. These digital circuits normally are continuously changing from one mode of operation to another. Therefore, the load demand can change rapidly resulting in large voltage transients at the output of the regulator which can adversely affect the digital circuitry. In this Master's Thesis, design topologies and challenges of very low-power fully integrated On-Chip Low-Dropout (LDO) regulators have been analyzed. Instead of conventional LDO which makes use of a large external capacitor to have better dynamic response and stability, a CapacitorLess LDO (CL-LDO) is chosen on considerations of smaller area. The most challenging part of designing this kind of regulator is achieving high current efficiency by reducing the quiescent current while ensuring good stability response as well as good regulation performance. Thus, different circuit techniques must be carefully added in order to balance the lack of the large external capacitor having the minimum impact on system efficiency. This work focuses on designing a fully integrated low-dropout regulator with good dynamic performance, high regulation performance and ultra-low power consumption. The stability is achieved by the use of two pole-splitting techniques, namely Cascode and Nested-Miller compensation. The good dynamic response with low quiescent current are achieved by the use of an adaptive biasing circuit, a gm-boost circuit and adaptive power transistor architecture.Inference of thermal models for sensorshttp://hdl.handle.net/2117/88014
Inference of thermal models for sensors
Novio Vázquez, Santiago
The presence of thermal diffusivity in a spherical thermal anemometer gives it long-memory dependence. The identification problem and state realisation of this model is addressed by using diffusive representation (DR). In order to do that, an ideal thermal sphere quadrupole model and its corresponding finite differences model are proposed and simulated. From those models and the non-rational Cole-Cole transfer function, the identification problem is discussed. PRBS as an input signal is also discussed. The best choice in the number of poles and their position is found by analysing frequency response. For the 5 decades bandwidth used here, it has been found that 8 poles geometrically spaced by a scale factor of 5 is a good choice. Finally, 8 poles DR is verified as a good option to model a complex spherical thermal anemometer prototype which is being developed in Universitat Politècnica de Catalunya, by means of open loop and sigma-delta closed loop control simulations.
2016-06-15T08:16:46ZNovio Vázquez, SantiagoThe presence of thermal diffusivity in a spherical thermal anemometer gives it long-memory dependence. The identification problem and state realisation of this model is addressed by using diffusive representation (DR). In order to do that, an ideal thermal sphere quadrupole model and its corresponding finite differences model are proposed and simulated. From those models and the non-rational Cole-Cole transfer function, the identification problem is discussed. PRBS as an input signal is also discussed. The best choice in the number of poles and their position is found by analysing frequency response. For the 5 decades bandwidth used here, it has been found that 8 poles geometrically spaced by a scale factor of 5 is a good choice. Finally, 8 poles DR is verified as a good option to model a complex spherical thermal anemometer prototype which is being developed in Universitat Politècnica de Catalunya, by means of open loop and sigma-delta closed loop control simulations.Photonic crystals for LEDhttp://hdl.handle.net/2117/87568
Photonic crystals for LED
Godizov, Georgy
The industry of lighting is working hard along the last years to improve the light extraction efficiency of the LEDs. One of the important part of the efficiency study is the software simulation. It allows us to, predict the behaviors of the given LED structure or adjust some parameters before build the real prototype. The traditional way of the simulations consists on using the Finite Elements Method or the Finite Difference Method. But the above methods need a lot of resources regarding to the time and computational memory. To reduce the required resources, the alternative way consists on combining the FEM software with a mathematical model. The objective of the thesis is assembly the mathematical model proposed by Philips Lumileds using MATLAB, by this way we are going to simulate part of LED geometry using a FEM software and after that use the results to post-process and be able to describe the behavior of the whole LED structure. First of all, we are going to study the theory about the LED structure and the physics phenomenon inside of a LED. Afterwards, the proposed numerical model, which is based on the explained theory, will be present. After that, the implementation of the method will be carried out, to do it also a FEM software has to be learned. In our case, we are going to use the JCMwave software. Finally, we are going to validate the model using results of a real photonic crystal simulation.
Photonic crystals for LED
2016-05-31T15:28:54ZGodizov, GeorgyThe industry of lighting is working hard along the last years to improve the light extraction efficiency of the LEDs. One of the important part of the efficiency study is the software simulation. It allows us to, predict the behaviors of the given LED structure or adjust some parameters before build the real prototype. The traditional way of the simulations consists on using the Finite Elements Method or the Finite Difference Method. But the above methods need a lot of resources regarding to the time and computational memory. To reduce the required resources, the alternative way consists on combining the FEM software with a mathematical model. The objective of the thesis is assembly the mathematical model proposed by Philips Lumileds using MATLAB, by this way we are going to simulate part of LED geometry using a FEM software and after that use the results to post-process and be able to describe the behavior of the whole LED structure. First of all, we are going to study the theory about the LED structure and the physics phenomenon inside of a LED. Afterwards, the proposed numerical model, which is based on the explained theory, will be present. After that, the implementation of the method will be carried out, to do it also a FEM software has to be learned. In our case, we are going to use the JCMwave software. Finally, we are going to validate the model using results of a real photonic crystal simulation.Fabricación de estructuras para cristales fotónicos basados en silicio macroporosohttp://hdl.handle.net/2117/87013
Fabricación de estructuras para cristales fotónicos basados en silicio macroporoso
Lange Vega, Diego
Este proyecto tiene como objetivo fabricar estructuras de níquel utilizando
silicio macroporoso como molde. La aplicación inicial de estas estructuras es el diseño
y fabricación de cristales fotónicos de níquel.
Para cumplir con el objetivo, se han caracterizado los procesos de fabricación
de silicio macroporoso 2D, silicio macroporoso modulado en profundidad y silicio
macroporoso 3D.
También se ha realizado la caracterización del crecimiento de níquel en medios
porosos, utilizando alúmina porosa. El proceso elegido para crecer níquel es el
electrodepósito.
En el tratamiento de las estructuras, se han utilizado tecnologías de fabricación
de microsistemas, tales como micromecanizado de superficie (evaporación, oxidación,
RIE), micromecanizado de volumen (ataque isotrópico, HF y anisotrópico, KOH).
Luego se ha rellenado las estructuras de silicio macroporoso con níquel y se ha
demostrado que es posible fabricar estructuras positivas y negativas de níquel en 2D,
moduladas en profundidad y 3D. Para las estructuras positivas se ha utilizado
polydimetilsiloxano (PDMS) como material sacrificial. También se han fabricado
estructuras negativas de polydimetilsiloxano.
Las estructuras de silicio macroporoso se han fabricado utilizando la tecnología
desarrollada en el Grupo de Micro y Nano Tecnologías del Departamento de Ingeniería
Electrónica de la UPC.
Para determinar su comportamiento como cristales fotónicos, se han realizado
medidas de reflexión en las estructuras fabricadas.
2016-05-12T12:09:34ZLange Vega, DiegoEste proyecto tiene como objetivo fabricar estructuras de níquel utilizando
silicio macroporoso como molde. La aplicación inicial de estas estructuras es el diseño
y fabricación de cristales fotónicos de níquel.
Para cumplir con el objetivo, se han caracterizado los procesos de fabricación
de silicio macroporoso 2D, silicio macroporoso modulado en profundidad y silicio
macroporoso 3D.
También se ha realizado la caracterización del crecimiento de níquel en medios
porosos, utilizando alúmina porosa. El proceso elegido para crecer níquel es el
electrodepósito.
En el tratamiento de las estructuras, se han utilizado tecnologías de fabricación
de microsistemas, tales como micromecanizado de superficie (evaporación, oxidación,
RIE), micromecanizado de volumen (ataque isotrópico, HF y anisotrópico, KOH).
Luego se ha rellenado las estructuras de silicio macroporoso con níquel y se ha
demostrado que es posible fabricar estructuras positivas y negativas de níquel en 2D,
moduladas en profundidad y 3D. Para las estructuras positivas se ha utilizado
polydimetilsiloxano (PDMS) como material sacrificial. También se han fabricado
estructuras negativas de polydimetilsiloxano.
Las estructuras de silicio macroporoso se han fabricado utilizando la tecnología
desarrollada en el Grupo de Micro y Nano Tecnologías del Departamento de Ingeniería
Electrónica de la UPC.
Para determinar su comportamiento como cristales fotónicos, se han realizado
medidas de reflexión en las estructuras fabricadas.