AXI-AD9361 core transmit data layout

Please, tell me what it means that in sysfs in scan elements for transmit device in out_voltage0_type I have :

le:s16/16>>0 ??

I suppose that is says little endian byte order and significant 16 bits but 16>>0 means that I have not to shift my samples before I copy then to the iio_buffer? I thought that there will be 16>>4 value.

If you treat it as a 16-bit value you do not have to shift, if you treat it as a 12-bit value you have to shift by 4 to the right left. I'll let mhennerich comment on the specifics of why it is the way it is.

pcercuei but it drop them when sample need to be shifted but when my samples are from range -32768 up to 32767 it need not to do that cause it use 12 -bits (with sign) am I right? Before it shift data it check them if sample require this.

Sorry but why DAC have to ignore 4 low-order bits ? I am telling you that I only use 12 bit from 16 bit aviable in short int. Maybe you are talking about 4 most significant bits (left side) then it have sense. Forgive me but I must have a certainty what I am doing.

Ok, now I understand. But one thing that confused me is that four bits that are ignored. Paul, tell me:

a) Did this lost of 4 bits do not change my signal that I will have problem to detect this signal on the receiver side properly?

b) Maybe I should scale my samples to +/- 2047 then shift to the left to have msb aligned so then DAC will drop 4 bits where will be zero numbers, what do you think?

c) On the transmitter side my samples are float number from approximately from range -3 to +3 value so what is the best way to scale it? Find the highest value, then divive all samples from this max value and then multiply all samples to full scale (32767 or 2047) ?