posted: January 28, 2018 at 3:00am version: 1.2 revision: 19
Update at Sat Jan 27 16:05:13 EST 2018 by tim
Updated with some changes from qflow-1.1 that were not merged into version 1.2. Checked for use with the qflow tutorial, which works.

posted: January 24, 2018 at 5:35pm version: 1.2 revision: 16
Added "distclean" targets to "make" to be compatible with the script on the opencircuitdesign server that builds the tarballs.

posted: January 8, 2018 at 5:35pm version: 1.2 revision: 15
Corrected failure in vesta to handle reference counts when freeing backtraces on clock nets. Same correction as made to qflow-1.1.

posted: January 24, 2018 at 5:35pm version: 1.2 revision: 14
Updated blif2cel.tcl script to correct same errors as qflow-1.1 (pitch of first route layers, handling comment lines). December 4, 2017 at 3:00am version: 1.2 revision: 13
Corrected readliberty and vesta to make bounds checks on the token size and reallocate memory when it gets larger than the original size. Also added the check for "env" in Makefile and substitution of same in spi2xspice.py. All changes were previously made to qflow-1.1.

posted: November 13, 2017 at 3:00am version: 1.2 revision: 12
Corrected an error that could cause yosys to fail on hierarchy missed due to qflow setting a tcsh variable to text from yosys output containing brackets (bad idea). Same correction made to qflow-1.1.

posted: November 9, 2017 at 3:00am version: 1.2 revision: 11
Fixed addspacers, which was generating an error when the specified power stripe pitch was larger than the width of the layout. Same change as made to qflow-1.1. Also added a fix to addspacers that was previously made to qflow-1.1 but not qflow-1.2.

posted: October 27, 2017 at 3:00am version: 1.2 revision: 10
Changed /bin/env to /usr/bin/env, as this seems to be more widely supported. Need better support from the configure script, though.

posted: October 20, 2017 at 3:00am version: 1.2 revision: 8
Same change made to qflow-1.1, simple fix to filtering of the outpus from the router script.
Corrected an error in the place2def script that was introduced by the last commit.

posted: October 19, 2017 at 3:00am version: 1.2 revision: 7
Several important fixes: Corrected DEF file units so that DEF file values are always integer; this does not affect the flow through qflow and magic, but affects results if the DEF file is read by any tool adhering to the integer value requirement. Fixed place2def script to read both technology and macro LEF files if both are specified independently for the technology. Corrected a round-off error affecting the placement of obstruction layers when fill cells are added for power bus stripes. Same changes as made to qflow-1.1.

posted: October 11, 2017 at 3:00am version: 1.2 revision: 6
Added files for FreePDK45 to the set of distributed technologies.

posted: May 1, 2017 at 3:00am version: 1.2 revision: 3
Implemented minimum pad spacing in .par file so that pads are forced by graywolf to be at double pitch spacing, which helps prevent qflow from pushing overlapping pads off the end of the route grid. Added gridX, gridY to the .par file in anticipation of the next graywolf update. Same changes as made to qflow-1.1.

posted: April 26, 2017 at 3:00am version: 1.2 revision: 2
Implemented handling of .include files in blif2BSpice.c; this is particularly useful when the vendor collects individual SPICE files for standard cells in a .lib file with .include statements instead of a single file.
Added code from David Lanzendorfer for hard macro placement and balancing power net resistance.

posted: April 26, 2017 at 3:00am version: 1.2 revision: 1
First commit of qflow development version 1.2

posted: February 3, 2018 at 3:00am version: 1.1 revision: 99
Update at Fri Feb 2 14:16:31 EST 2018 by tim
Made a number of enhancements: Liberty file parser for vesta and for blifFanout now parse according to the newer spec that allows lines to end without a semicolon. Implemented automatic check of standard cell LEF to determine the names of the power and ground pins, and propagate this information to all the scripts, so that it does not have to be specified in the .sh file. This avoids weird problems with the router caused by improperly named power and ground. Also: Added the gscl45nm library to qflow version 1.1, since development of 1.1 got ahead of the 1.2 repository and now version 1.2 is going to be retired.

posted: January 28, 2018 at 3:00am version: 1.1 revision: 97
Update at Sat Jan 27 15:35:24 EST 2018 by tim
Reorganized debug and verbose output modes, and added a debug mode for generating output about liberty file parsing, since this seems to be a perrenial issue, with lots of liberty files here and there that violate the official liberty syntax.

posted: January 27, 2018 at 3:00am version: 1.1 revision: 96
Update at Fri Jan 26 10:37:15 EST 2018 by tim
Changed behavior of vesta to not delete names of cells marked "dont_use" in the liberty file. If a cell gets used anyway in the netlist, it now flags a warning and allows the cell to be used anyway. Also fixed readliberty to not use standard delimiters that it defines for the liberty file format when reading the delay file, which contains net names generated by yosys that may contain ":", which is considered a delimiter in liberty files.

posted: January 26, 2018 at 3:00am version: 1.1 revision: 95
Update at Thu Jan 25 14:45:05 EST 2018 by tim Also: Changed the synthesis script from Staf Verhaegen's patch which moves the check for a custom yosys script up and if found, does not attempt to automatically generate a yosys script. This prevents qflow from overwriting the custom script if they have the same name, and prevents other errors, and fixes the general case where one might use a custom script to avoid errors generated when running the automatic creation.

posted: January 24, 2018 at 5:45pm version: 1.1 revision: 94
Added "distclean" targets to "make" to be compatible with the script on the opencircuitdesign server that builds the tarballs.

posted: January 8, 2018 at 3:00am version: 1.1 revision: 93
Corrected failure in vesta to handle reference counts when freeing backtraces on clock nets.
Changed the same code again to be more flexible with respect to unknown dictionary entries in the timing section. It no longer specifically finds the ecsm_waveform and ecsm_capacitance keywords, but parses through any dictionary-like entry and generates an "unhandled feature" output statement.

posted: December 17, 2017 at 3:00am version: 1.1 revision: 92
Fixed the liberty file read routine for timing sections having ecsm_waveform and/or ecsm_capaticance entries. These values are not handled, but such entries no longer cause parsing to fail.

posted: December 14, 2017 at 3:00am version: 1.1 revision: 91
Corrected blif2cel.tcl in several places, (1) to properly ignore commented lines in LEF, and (2) to use only the pitch of the first route layer(s) to set the pitch of the pads.

posted: December 11, 2017 at 3:00am version: 1.1 revision: 90
Added SDF file output in addition to the vesta format and SPEF format. Both SDF and SPEF are still preliminary, and are not being used by any other tool currently.

posted: December 6, 2017 at 3:00am version: 1.1 revision: 89
Added experimental SPEF file generator.
Also changed vesta to have the same out-of-bounds check on the token size in advancetoken().

posted: December 4, 2017 at 3:00am version: 1.1 revision: 88
Corrected the read_liberty routine to check for token overflow and allocate more memory as needed. Tokens can contain everything between delimiters like { and } for unhandled sections and can be very large.

posted: November 21, 2017 at 3:00am version: 1.1 revision: 87
Added change from Russell Friesenhahn to let the configure script find the "env" tool which is then in turn substituted in to the spi2xspice script. Also fixed the spi2xspice script to read the nominal process voltage from the liberty file and apply appropriately to the D-to-A and A-to-D signal bridges. Added some preliminary support for simplified hard macro integration into the synthesis flow (unfinished, does not affect existing methods).

posted: November 13, 2017 at 3:00am version: 1.1 revision: 86
Corrected an error that could cause yosys to fail on hierarchy missed due to qflow setting a tcsh variable to text from yosys output containing brackets (bad idea).

posted: November 9, 2017 at 3:00am version: 1.1 revision: 85
Fixed addspacers, which was generating an error when the specified power stripe pitch was larger than the width of the layout.

posted: October 27, 2017 at 3:00am version: 1.1 revision: 84
Changed /bin/env to /usr/bin/env, as this seems to be more widely supported. Need better support from the configure script, though.

posted: October 20, 2017 at 3:00am version: 1.1 revision: 82
Simple change to filtering of the router script output so that it catches the number of failed nets at the end (if any) but doesn't also output every failed net along the way.
Corrected an error that was introduced by the last commit.

posted: October 19, 2017 at 3:00am version: 1.1 revision: 81
Several important fixes: Corrected DEF file units so that DEF file values are always integer; this does not affect the flow through qflow and magic, but affects results if the DEF file is read by any tool adhering to the integer value requirement. Fixed place2def script to read both technology and macro LEF files if both are specified independently for the technology. Corrected a round-off error affecting the placement of obstruction layers when fill cells are added for power bus stripes.

posted: September 28, 2017 at 3:00am version: 1.1 revision: 80
Corrected a basic error in the command line parsing in which omitting the project name was not recognized as an error and would cause bad things to happen (rewriting the qflow_exec script with bad syntax). Now it will properly generate a usage message and exit.

posted: September 22, 2017 at 3:00am version: 1.1 revision: 79
A number of housekeeping changes. Added print statements with the command and arguments for every script and executable called from a synthesis flow script. Added more checks for non-zero exit status from scripts, to catch interpreter errors. Also: Corrected blifFanout to generate only unsigned char exit values, and to output the number of gates changed as a print statement on stdout, using grep and cut to identify the number of gates changed. Otherwise, blifFanout can never exit due to failure (because the negative exit values could not be seen), and would end suddenly any time the number of gates changed was a multiple of 256.
Corrected an error in addspacers handling technologies where there are not enough route layers to place a vertical power bus (generally, 4 metals are required to do power buses easily).
Reverted the system of "default" variables back to the way it used to be, which was to set default values in the tech .sh file, except for the change that the defaults from the tech .sh file are written into the project_vars.sh file so that the user can see what the defaults are in order to be better informed about changing them. Also: Changed the behavior of addspacers to ensure that at least one power and one ground bus are generated if the "-stripe" argument is given, as it is better to violate the specified pitch than to generate bad layout.

posted: September 21, 2017 at 3:00am version: 1.1 revision: 78
Made substantial revisions to the code that generates power posts for power striping, to account for via spacing and overlap rules where specified. Also added check for variable "logdir" to avoid errors on projects created with versions of qflow before the individual log files were implemented.
Corrected some typos in the previous commit that prevented addspacers from running. New version is still a work in progress, as it does not correctly find some power buses from the polygon geometry, and it needs to know the via separation to correctly construct the power posts.
Enhanced the addspacers script to deal with USE and DIRECTION values for pins that are not uppercase, and to deal with pins that are listed as POLYGONs instead of RECTs, in particular to parse a power or ground bus polygon to extract a single rectangle spanning the cell. This is an ad hoc solution but works in the cases I've encountered so far.

posted: September 19, 2017 at 3:00am version: 1.1 revision: 76
Modified the main "qflow" launch script to use exec to make it transparent to exit status, and use the :q modifier on $argv to handle arguments with whitespace correctly. Thanks to Risto Bell for the fix.
Corrected handling of quotes in the default values set in the techfile .sh file, so that the quotes end up in project_vars.sh.

posted: September 18, 2017 at 3:00am version: 1.1 revision: 75
Added the ability to declare defaults for entries in project_vars.sh in the technology .sh file, for defaults like "via_use" and "fanout_options" that are process-dependent. Also added "stat" to the end of the standard yosys script so that statistics on the use of standard cells will be written in the log file.

posted: September 13, 2017 at 3:00am version: 1.1 revision: 74
Corrected failure to check for end-of-string terminator that makes parsing segfault in a very flaky and system-dependent way.

posted: August 28, 2017 at 3:00am version: 1.1 revision: 73
Added handling for "via_use" in project_vars.sh to be passed to the .cfg file as "via use", coordinating with the latest commit to qrouter.
Removed swap file that ended up in the distribution.

posted: August 26, 2017 at 3:00am version: 1.1 revision: 72
Corrected vesta to set fsum to NULL if no summary file or directory has been specified on the command line. Otherwise, vesta can lock up trying to access a non-NULL random fsum.
Change to rc2dly to output only the total wire capacitance for each net, so that vesta does not double-count the receiver gate capacitances (or, conversely, ignore the wire capacitance).

posted: August 25, 2017 at 3:00am version: 1.1 revision: 71
Corrected errors in which cell in list was referenced by name, where the name is removed if the cell is marked "dont_use" in the liberty file, causing a crash.

posted: August 24, 2017 at 3:00am version: 1.1 revision: 70
Revised the delay reading in vesta to ignore the capacitance from the delay backannotation file, since it double-counts the terminal pin capacitances. The effect of the wiring capacitance should already be present in the delay values in the file.
Corrected obscure csh issue with using an if ... else if conditional to test for a variable being defined or not and then checking for a specific value.

posted: August 23, 2017 at 3:00am version: 1.1 revision: 69
Corrected the call to qrouter for no graphics mode. This required a correction to qrouter to properly handle no-console and no-graphics modes properly.
Revised the method of logging output so that there is now a directory log/ in the project, and individual log files are created for each step of the process. This makes it easier to track down errors from a specific step, instead of dumping everything into one file.
Added options to vesta to supply a directory or file name to dump output to. If a directory name (as determined by the lack of a file extension), then four separate output files will be made, one for each timing analysis.

posted: August 17, 2017 at 3:00am version: 1.1 revision: 68
Corrected an error in addspacers that causes it to exit with an error condition if there is not enough room in the layout for the power stripes that were requested.

posted: August 12, 2017 at 3:00am version: 1.1 revision: 65
Fixed some major issues with the run-time computation of the clock trees and finding common clock points between two registers. Qflow was scanning the entire clock tree for the analysis of every single register-to-register connection, which was not unreasonable for designs with small clock networks, but quickly reached stupid proportions for microprocessor-sized designs, as the run-time was exponentially related to the number of registers in the design. Everything in qflow is now more or less linear with design size (probably O(N log(N))).

posted: August 7, 2017 at 3:00am version: 1.1 revision: 62
Corrected error in addspacers that (depending on the cell width) would sometimes add one more power bus stripe than expected, while calculations such as where to put pin-protecting obstructions would use the smaller number and therefore end up with conflicting values.

posted: August 6, 2017 at 3:00am version: 1.1 revision: 61
Corrected error in which for reasons that I don't understand, the LEF file DIRECTION value gets an extra space at the end and then fails subsequent comparisons. Although I don't see how the regexp fails, it was easy enough to use the Tcl "string trim" command to remove whitespace.

posted: August 1, 2017 at 3:00am version: 1.1 revision: 60
Modified the primary and synthesis scripts so that the command "qflow" takes the option module_name, NOT source_file, but can have the syntax "qflow module_name source_file" in case the source file does not have the same root name as the module. In all cases, the module name is used for all subsequent file root names (such as the .blif, .spc, .def, and so forth). Alternately, "qflow module_name" will work even if there is no file module_name.v (or .sv), as long as qflow can find some verilog file in the source directory containing the specified module.
Corrected two errors: (1) placement script did not pass the "-techlef" option to addspacers, and (2) addspacers did not check LEF and DEF files for comment lines.
Modified synthesis script so that it checks for python3 before attempting to run the spi2xspice.py tool.

posted: July 22, 2017 at 3:00am version: 1.1 revision: 59
Removed initial tab from verilog output, since it causes problems with OpenTimer (which is OpenTimer's fault, and will be fixed, but might as well accomodate the bug because it's easy to).

posted: July 11, 2017 at 3:00am version: 1.1 revision: 58
Changed a misspelling in the vesta version output, and increased the version number to better track versions out there in the world.

posted: June 19, 2017 at 3:00am version: 1.1 revision: 57
Fixed two errors: One that caused the power or ground posts to be placed on the wrong columns after the first (simple coding error), and one which caused the power and ground bus labels to be offset (failure to match two pieces of code which should have been consolidated into one, anyway).
Corrections to make power and ground pin placement compatible with the position of stripes (one case was missed).

posted: June 14, 2017 at 3:00am version: 1.1 revision: 56
Updated qflow to use the new qrouter "standard" route script. Updated addspacers to automatically add pins for power and ground when it generates the power bus stripes.

posted: June 10, 2017 at 3:00am version: 1.1 revision: 55
Corrections to automatic power striping: Allows posts to be drawn for power buses even if the top level metal cannot be placed due to lack of definition in the technology LEF file (however the better thing to do in that case is pass a different LEF file to addspacers than to qrouter). Also changed the power post to be no wider than the vias, otherwise it just wastes space and interferes with routing.

posted: June 8, 2017 at 3:00am version: 1.1 revision: 53
Expanded on the implementation of power bar stripes. Code now takes "pattern" and generates internal bars of power and ground connections. Many details are not handled, and the specialnets output is not recognized by qrouter, so it is not quite yet usable, but it is much further along than yesterday.
And another correction to prevent errors when used normally. . .
Corrected an error that causes addspacers to fail if the new/ provisional code for adding vertical column spacers is not being used.

posted: June 7, 2017 at 3:00am version: 1.1 revision: 52
Preliminary support for power bus striping, largely nonfunctional so far except for placing columns of spacers throughout the circuit layout.
Correction to spi2xspice.py script, which otherwise does not correctly parse the function expressions in the OSU standard cell sets.

posted: May 17, 2017 at 3:00am version: 1.1 revision: 49
Corrected blif2BSpice to correctly add the ".ends" to the end of the subcircuit. Added "-i" option to blif2BSpice to put an include line for the standard cell definitions instead of dumping them directly into the output. Revised the synthesis and placement scripts to use this option.

posted: May 1, 2017 at 3:00am version: 1.1 revision: 48
Implemented minimum pad spacing in .par file so that pads are forced by graywolf to be at double pitch spacing, which helps prevent qflow from pushing overlapping pads off the end of the route grid. Added gridX, gridY to the .par file in anticipation of the next graywolf update.

posted: March 31, 2017 at 3:00am version: 1.1 revision: 47
Added patch from Jamey Hicks to exit with error code 1 after each qflow script is run if the script returns an error code.
Finished (hopefully) the cleanup of all derived files from the git repository.
Removed Makefiles down in the individual tech directories
Final push of .gitignore after deleting files

posted: March 27, 2017 at 3:00am version: 1.1 revision: 46
Cleaning up after changing .gitignore. . . needed to delete ignored files first. . .
Fixed the placement script call to the qrouter "layers" command. By not placing the whole command after "catch" in braces, the number of layers was being ignored by the Tcl parser.

posted: March 26, 2017 at 3:00am version: 1.1 revision: 45
Corrected placement script with patch from Karl-Filip Faxen to properly compare timestamps on the .acel file. Also updated the .gitignore file to properly reflect the contents of the repository.
Removed backup file.

posted: February 25, 2017 at 3:00am version: 1.1 revision: 43
Set fdly to NULL to avoid a segfault.Also:
Update at Fri Feb 24 12:54:33 EST 2017 by timAlso:
Merge branch 'master' into work

posted: January 12, 2017 at 3:00am version: 1.1 revision: 42
Corrected the previous handling of quoted items in the liberty file, which conflicted with other attempts to handle such outside of the advancetoken() routine.Also:
Update at Wed Jan 11 09:15:44 EST 2017 by timAlso:
Merge branch 'master' into workAlso:
Fixed it the right way, this time.

posted: January 10, 2017 at 3:00am version: 1.1 revision: 41
Tokenizer fixed to not attempt to increment a static array; this is caught by some (most?) compilers and will prevent compilation.Also:
Update at Mon Jan 9 10:05:42 EST 2017 by timAlso:
Merge branch 'master' into work

posted: January 6, 2017 at 3:00am version: 1.1 revision: 40
Corrected problem with liberty files that put quotes around strings. The parser now removes quotes from entries where they are optional.Also:
Update at Thu Jan 5 10:39:53 EST 2017 by timAlso:
Merge branch 'master' into work

posted: December 21, 2016 at 3:00am version: 1.1 revision: 39
Corrected the commented-out setting for vesta that is put by default in project_vars.sh, which was a multi-word option and therefore needs to be in quotes.Also:
Update at Tue Dec 20 15:13:37 EST 2016 by timAlso:
Merge branch 'master' into work

posted: September 19, 2016 at 3:00am version: 1.1 revision: 36
Corrected qflow script to use "tcsh -f" instead of "tcsh" in the first line of scripts generated for use in running qflow (e.g., qflow_exec.sh).Also:
Update at Sun Sep 18 21:45:29 EDT 2016 by timAlso:
Merge branch 'master' into workAlso:
Fixed help text of blifFanout so that MaxFanout, which is integer, is not printed with %g, and so that where values set by the command line were referred to as 'default', these values are now referred to as 'value', and the actual default value is also given.Also:
Swapped the reading of .sh and project_vars.sh, so that values in project_vars.sh may override those in .sh, specifically for option strings passed to applications (like blifFanout).Also:
Corrected error in vesta that causes crash if no delay file is specified.

posted: June 10, 2016 at 3:00am version: 1.1 revision: 34
Corrected typo in display.sh; thanks to Santiago Rubio for pointing it out.Also:
Update at Thu Jun 9 08:55:47 EDT 2016 by timAlso:
Merge branch 'master' into workAlso:
Updated display script to generate a load script and run this from the magic command-line, in conjunction with changes to magic to allow scripts to be specified on the command line.

posted: June 8, 2016 at 3:00am version: 1.1 revision: 33
Corrected display script, as the embedded newline is not interpreted correctly in the "lef read" command, and needs to be split into two separate commands. Thanks to Santiago Rubio for the patch.Also:
Update at Tue Jun 7 08:33:09 EDT 2016 by timAlso:
Merge branch 'master' into work

posted: April 19, 2016 at 3:00am version: 1.1 revision: 32
Modified the osu018 technology to use SCN6M_SUBM.10 instead of SCN6M_DEEP.09; thanks to Shimon for pointing out that the OSU standard cells matched the SUBM tech and not the DEEP. Otherwise, reading the GDS files from the OSU018 standard cell set into magic under SCN6M_DEEP.09 will generate large numbers of DRC errors. Note, however, that the LEF files from OSU018 do not specify metal extensions on the vias, and so stacked vias m1-m3 will cause minimum metal violations on metal2. The way around this is to specify via stacks = 1 to qrouter, so that every metal layer must route for at least 1 track width, which satisfies the minimum metal requirement.Also:
Update at Mon Apr 18 21:24:20 EDT 2016 by timAlso:
Merge branch 'master' into work

posted: March 17, 2016 at 3:00am version: 1.1 revision: 31
Added back parsing of option "buffer" for backwards-comptibility without breaking, although the option is non-functional.Also:
Update at Wed Mar 16 09:21:40 EDT 2016 by timAlso:
Merge branch 'master' into work

posted: March 16, 2016 at 3:00am version: 1.1 revision: 30
Fixed an incorrect parsing of one of the various possible version strings returned by yosys.Also:
Update at Tue Mar 15 16:36:03 EDT 2016 by timAlso:
Merge branch 'master' into work

posted: February 27, 2016 at 3:00am version: 1.1 revision: 29
Added "touch $synthlog" to the top of all the scripts after synthesize.sh so that removing the log file does not generate an error message.Also:
Update at Fri Feb 26 19:03:44 EST 2016 by timAlso:
Merge branch 'master' into work

posted: February 19, 2016 at 3:00am version: 1.1 revision: 28
Corrected a round-off error in the generation of .cel files by the decongest script. This would cause overlap of cells when cells have odd-numbered widths, leading to cell X positions that precess relative to the routing grid along the width of the layout.Also:
Update at Thu Feb 18 22:34:47 EST 2016 by timAlso:
Merge branch 'master' into work

posted: February 17, 2016 at 3:00am version: 1.1 revision: 27
Corrected an error in vesta that would segfault on attempting to deal with a latch that it thought was a flop. Also, modified blifFanout to give more relevant diagnostic information, such as units used for loads and latencies, and showing how "strength" relates to the specified maximum latency. Defaults for blifFanout made more realistic, especially for the default 0.35um technology, so that it doesn't constantly report that gates are too weak and try to change all gates to the maximum size. Option "-f" changed to "-I" ("I" for "Ignore") so that "-f" means do fanout buffering only, and "-L" means do load balancing only.Also:
Update at Tue Feb 16 20:24:17 EST 2016 by timAlso:
Merge branch 'master' into work

posted: February 16, 2016 at 3:00am version: 1.1 revision: 26
Corrected a number of errors in blifFanout that failed to properly handle dont_use type cells and would subsequently corrupt memory. Also corrected several lines that prevented auto-detect of buffer cells in the liberty file.Also:
Update at Mon Feb 15 21:53:50 EST 2016 by timAlso:
Merge branch 'master' into work

posted: February 13, 2016 at 3:00am version: 1.1 revision: 25
Corrected handling of place2def so that it does not exit with an error if a route is given in the info file with a width or pitch of zero. Simultaneous change to qrouter behavior should not let such routes get into the info file, though. This check has been added to qflow as a precautionary measure only.Also:
Update at Fri Feb 12 22:08:27 EST 2016 by timAlso:
Merge branch 'master' into work

posted: January 10, 2016 at 3:00am version: 1.1 revision: 24
Corrected installation and execution for local installations of yosys. Specifically, yosys calls yosys-abc, which if not in the standard search path, must be specified using the "-exe" switch to the "abc" command in yosys.Also:
Update at Sat Jan 9 10:44:42 EST 2016 by timAlso:
Merge branch 'master' into work

posted: November 23, 2015 at 3:00am version: 1.1 revision: 23
Revised the way that the placement and router scripts handle output filenames. Placement now copies the .def solution to _unroute.def (previously done only at the end of the router script). The router script uses the _unroute.def file as input and does not overwrite it. The previous method allowed the _unroute.def file to become out of sync with the rest of the files.Also:
Update at Sun Nov 22 09:41:25 EST 2015 by timAlso:
Merge branch 'master' into workAlso:
Slight modification, as the unroute copy was being made before the addspacers tool was run, leading to different file contents.Also:
Rootname, not project. . .

posted: November 21, 2015 at 3:00am version: 1.1 revision: 22
Added graywolf_options to list of variables defined in project_vars.sh, so that specific arguments can be passed to graywolf. "-n" will disable graphics, allowing a fully graphics-free flow.Also:
Update at Fri Nov 20 13:40:40 EST 2015 by timAlso:
Merge branch 'master' into work

posted: November 14, 2015 at 3:00am version: 1.1 revision: 21
Changed qflow behavior so that option "yosys_nodebug" is now "yosys_debug" and the non-debug behavior is the default (resulting in smaller layouts with fewer unconnected outputs that are useful only for debugging).Also:
Update at Fri Nov 13 13:11:19 EST 2015 by timAlso:
Merge branch 'master' into work

posted: November 13, 2015 at 3:00am version: 1.1 revision: 20
Corrected a problem in the place2def.tcl script that was not properly using the information from the info file to place pins on 1-of-N route tracks when the layer width and spacing rules require it.Also:
Update at Thu Nov 12 20:02:55 EST 2015 by timAlso:
Merge branch 'master' into work

posted: November 12, 2015 at 3:00am version: 1.1 revision: 19
Corrected synthesis script, which had added the line necessary to process RTL in the verilog source, but only added it to the preliminary yosys script, not to the final one.Also:
Update at Wed Nov 11 11:31:46 EST 2015 by timAlso:
Merge branch 'master' into work

posted: October 31, 2015 at 3:00am version: 1.1 revision: 18
Modified scripts so that the .cel file is generated as part of the placement script, not the synthesis script. The change is required due to the introduction of density planning, since the density affects the generation of the .cel file passed to graywolf for placement. If the .cel file is generated as part of the synthesis script, then if the density is modified, the flow has to be re-run from synthesis, not from placement. This update corrects the issue.Also:
Update at Fri Oct 30 09:22:54 EDT 2015 by timAlso:
Merge branch 'master' into work

posted: October 30, 2015 at 3:00am version: 1.1 revision: 17
Corrected one remaining error in the "decongest" density planning script that does not handle the case of zero fill cells, and so was preventing densities above about 0.9 (one fill cell per standard cell).Also:
Update at Thu Oct 29 08:33:10 EDT 2015 by timAlso:
Merge branch 'master' into work

posted: October 29, 2015 at 3:00am version: 1.1 revision: 16
Modified the synthesis script so that the various files (lef, techlef, gds, spice, liberty) can be specified as absolute paths and not have to be symbolic links from the tech directory.Also:
Update at Wed Oct 28 09:43:21 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
Extended the absolute path handling capability to all the major synthesis flow scripts.

posted: October 17, 2015 at 3:00am version: 1.1 revision: 15
Updated readliberty.c to match a change previously made to the same code in vesta.c, underscoring the need to use one single liberty file parsing library for all the tools. . .Also:
Update at Fri Oct 16 11:02:32 EDT 2015 by timAlso:
Merge branch 'master' into work

posted: October 12, 2015 at 3:00am version: 1.1 revision: 14
Corrected two errors with the decongestion routine. One error was an incorrect computation of the number of fill cells to make up the total density, resulting in fill cells being added even if the density was set to 1. The other was a round-off error resulting in an incorrect width value, which tends to cause bad route failures.Also:
Update at Sun Oct 11 11:27:31 EDT 2015 by timAlso:
Merge branch 'master' into work

posted: October 5, 2015 at 3:00am version: 1.1 revision: 13
Added patch by Staf Verhaegen that passes a default script argument to ABC that works much better than the default behavior, expanding the range of cells used (e.g., will use AOI and OAI cells instead of trying to shove everything into NAND/NOR logic). The practical impact appears to be an increase in circuit speed as well as routing efficiency. Added an additional hook from variable "abc_script" in project_vars.sh for manual control over this expression. 'set abc_script = ""' reverts to the original behavior.Also:
Update at Sun Oct 4 11:43:37 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
Modified synthesis script to provide immediate output on the failure to find a verilog source file. Helps to catch and resolve gross errors faster.

posted: September 7, 2015 at 3:00am version: 1.1 revision: 11
Corrected density planning of "decongest" for situations where the number of fill cells is less than the total number of cells, due to having only large filler cells in the standard cell set. Optimized "decongest" to make use of smaller fill cells if available, such that the fill cells will outnumber the standard cells, making the decongestion more evenly spread across the layout. Improved blif2cel.tcl so that cells that only use POLYGON for pins instead of RECT will not lose information in the .cel file.Also:
Update at Sun Sep 6 12:41:16 EDT 2015 by timAlso:
Merge branch 'master' into work

posted: August 4, 2015 at 3:00am version: 1.1 revision: 10
Noted that graywolf produces redundant net entries where it thinks that a route should go from a pin to both top and bottom of a cell, and that putting these redundant net entries into the DEF file output causes qrouter to report false failures. Rewrote the place2def script to avoid generating the redundant entries.Also:
Update at Mon Aug 3 10:01:25 EDT 2015 by timAlso:
Merge branch 'master' into work

posted: July 26, 2015 at 3:00am version: 1.1 revision: 9
Oops, last change defined hash.o and readliberty.o in such a way that the makefile attempts to turn them into executables. Fixed.Also:
Update at Sat Jul 25 09:27:08 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
Once again. . .

posted: July 25, 2015 at 3:00am version: 1.1 revision: 8
Corrected src makefile to clean up hash.o and readliberty.o on a "make clean". Removed the two object files from the git repository, where they don't belong.Also:
Update at Fri Jul 24 10:41:34 EDT 2015 by timAlso:
Merge branch 'master' into work

posted: June 10, 2015 at 3:00am version: 1.1 revision: 7
Added files for support of OSU018 (for TSMC). Also: Corrected the BLIF-to-verilog conversion so that trailing brackets are converted back into verilog syntax square brackets [*] but brackets in the middle created by multi-dimensional arrays are replaced with underscores. The result appears to be compatible with gate-level simulations in Icarus verilog.Also:
Update at Tue Jun 9 11:30:38 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
Added OFFSET lines back into the OSU standard cell LEF files. These are no longer needed now that qrouter has been corrected with respect to the default OFFSET when not specified; however, leaving the OFFSET in does no harm and maintains backwards compatibility with previous versions of qrouter.

posted: June 4, 2015 at 3:00am version: 1.1 revision: 6
Modified scripts such that all TCL scripts are annotated with the correct path to "tclsh" on installation.Also:
Update at Wed Jun 3 17:34:02 EDT 2015 by timAlso:
Merge branch 'master' into work

posted: June 3, 2015 at 3:00am version: 1.1 revision: 5
Modified readliberty.c to ignore cells marked "dont_use". Corrected synthesis script to no longer require a "gate.cfg" file to run blifFanout, since this has been deprecated (and is no longer in the set of installed files). Modified blifFanout to use the first buffer found in the liberty file, so details of the buffer cell do not need to be provided in the tech shell script (although they will be used, if passed to the program).Also:
Update at Tue Jun 2 10:08:55 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
Corrected missing tagging of flop and latch output with an appropriate flag; otherwise, clock source searches don't stop at flop outputs and can get into infinite loops.Also:
Corrected Makefile.in in the src directory, or else vesta won't compile.

posted: June 1, 2015 at 3:00am version: 1.1 revision: 4
Corrected the liberty file reading of scalar values instead of tables for vesta static timing analysis and in the readliberty library. Also, added a hash table for reading and looking up nets in vesta to speed up the verilog file reading, which was a bottleneck for large netlists.Also:
Update at Sun May 31 19:36:05 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
Removed an unused backup file.

posted: May 30, 2015 at 3:00am version: 1.1 revision: 3
Corrected an error in back-annotation of permuted buffer tree nets.Also:
Update at Fri May 29 09:36:47 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
Finally got around to updating the yosys script to use the default "synth -top " command, for yosys versions 0.5 and up.Also:
Added a new option to "project_vars.sh" called "yosys_nodebug". If set to 1, the yosys script uses "clean -purge" after the standard cell mapping. This removes all the buffers that are used to maintain internal signal names, resulting in a smaller but less easily debugged layout.

posted: May 27, 2015 at 3:00am version: 1.1 revision: 2
Corrected code so that it does not segfault on a diagnostic print statement when path starts at an input pin instead of a flop output.Also:
Update at Tue May 26 12:16:13 EDT 2015 by timAlso:
Merge branch 'master' into work

posted: May 18, 2015 at 3:00am version: 1.1 revision: 0
Initial check-in of development version 1.1, an important update with greatly improved clock and buffer tree optimization.

posted: May 19, 2015 at 3:00am version: 1.1 revision: 1
Added a comment, mostly just to jog the system into updating all the files on the server side.

posted: November 16, 2015 at 3:00am version: 1.0 revision: 99
Corrected the direction that pins are offset when avoiding overlaps made by graywolf.Also:
Update at Sun Nov 15 16:55:58 EST 2015 by timAlso:
Merge branch 'master' into work

posted: May 9, 2015 at 3:00am version: 1.0 revision: 96
Corrected calculation for number of fill cells to add, to get the specified density to be interpreted as the fraction of the layout comprising actively routed cells.Also:
Update at Fri May 8 20:08:42 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
Additional correction to clocktree to correctly parse a cellname when fill cells have been merged into cell instances with a specific syntax.Also:
Another correction to prevent the clock tree insertion tool from screwing up when faced with fill cells added for density management.

posted: May 8, 2015 at 3:00am version: 1.0 revision: 95
Changed all tcl scripts to use /bin/tclsh; however, this needs to be set through a substitution, so not yet done. . .Also:
Update at Thu May 7 15:48:59 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
Implemented a variation of "decongest.tcl" that will take a .cel file and insert fill cells uniformly to meet a specific density. Added the placement option "initial_density" indicating the density of actively routed cells (as a fraction of the total layout area). This gives a way to force a density rather than relying on the congestion router solution (or having to wait for an initial router failure to get the congestion router solution).

posted: April 21, 2015 at 3:00am version: 1.0 revision: 94
Modified the blif2Verilog script so that the ".nopwr.v" file adds wire statements for power and ground, assigning 1'b1 and 1'b0 to them, respectively, so that the verilog file becomes simulatible. Also, for the purpose of verilog simulation, added the verilog libraries for the standard cell gates to the qflow distribution/installation.Also:
Update at Mon Apr 20 09:31:37 EDT 2015 by timAlso:
Merge branch 'master' into work

posted: March 31, 2015 at 3:00am version: 1.0 revision: 93
Made a couple of corrections that allows the use of a null string ("") as variable "separator". This was supported by blifFanout but was being bungled by the script calling blifFanout. Because the OSU standard cell sets are more appropriately compatible with the null separator than with the "X" separator (due to a few cells that don't use the "X", like CLKBUF), the standard cell script has been changed to specify a null separator character.Also:
Update at Mon Mar 30 16:42:31 EDT 2015 by timAlso:
Merge branch 'master' into workAlso:
Corrected place2def.tcl, which would greedily take the first underscore and so screw up output on cell names that contain an underscore as part of the name.Also:
Thought better of it and added a $ to the regexp to make sure that the underscore-followed-by-digits is the last part of the instance string.

posted: February 27, 2015 at 3:00am version: 1.0 revision: 92
Corrected a bad error in the ypostproc.tcl script that was deleting the first cell of any netlist that contains the line ".names $undef", a line that has been generated by recent versions of yosys. Naturally, this produces bad output. . .Also:
Update at Thu Feb 26 20:13:15 EST 2015 by timAlso:
Merge branch 'master' into work

posted: February 26, 2015 at 3:00am version: 1.0 revision: 91
Added qflow option "-v" or "--version" to print qflow version number; prevented qflow from printing a message about setup before arguments are parsed, and if either "--version" or "--help" was given.Also:
Update at Wed Feb 25 19:39:23 EST 2015 by timAlso:
Merge branch 'master' into work

posted: November 20, 2014 at 3:00am version: 1.0 revision: 89
Corrected an error that causes synthesize_yosys.sh to fail due to the version number on yosys 0.4 (due to a lack of following a standard syntax for version numbering). Also, blif2cel.tcl modified to accept a LEF syntax variant containing two values for the PITCH statement.Also:
Update at Wed Nov 19 15:52:34 EST 2014 by timAlso:
Merge branch 'master' into work

posted: October 15, 2014 at 3:00am version: 1.0 revision: 88
Removed references to TimberWolf in favor of Ruben Undheim's update called "graywolf", which already has more desirable behavior such as installing into a standard location and not requiring sourcing a script file before running.Also:
Update at Tue Oct 14 20:42:31 EDT 2014 by timAlso:
Merge branch 'master' into work

posted: September 30, 2014 at 3:00am version: 1.0 revision: 87
Corrected an error that prevents qflow from working with qrouter version 1.3.0.Also:
Update at Mon Sep 29 21:05:35 EDT 2014 by timAlso:
Merge branch 'master' into work

April 9, 2013
Qflow converted from a loose set of independent scripts
into a package with an install location. Scripts
greatly revised and extended to fit the new package
format. All scripts extended to use the OSU 0.35um
open-source standard cell set by default. Capability
to split nets with large fanout into trees added.

April 9, 2013 at 5:09pm
Third time's the charm.Also:
Update at Tue Apr 9 17:08:54 EDT 2013 by timAlso:
Merge branch 'master' into work

April 10, 2013 at 3:00am
Various updates, corrections to make the example circuit complete the entire flow without errors. Much more to do, but it's a good start.Also:
Update at Tue Apr 9 19:58:56 EDT 2013 by timAlso:
Merge branch 'master' into work

April 11, 2013 at 3:00am
Added a few scripts for file conversion. These are not yet part of the official flow.Also:
Update at Wed Apr 10 11:44:01 EDT 2013 by timAlso:
Merge branch 'master' into work

April 13, 2013 at 3:00am
Implemented a technology-independent spacer (filler cell) adding routine "addspacers.tcl".Also:
Update at Fri Apr 12 14:04:55 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
Forgot to map the output of addspacers back to the original filename so that the correct file will be used by the router.Also:
Small modification to add output to the log file instead of dumping it to the terminal.

April 15, 2013 at 3:00am
Changed sis input from "rlib" to "read_library", as "rlib" became deprecated at some point, but sis versions from 1.3 should understand the "read_library" command.Also:
Update at Sun Apr 14 19:20:53 EDT 2013 by timAlso:
Merge branch 'master' into work

May 1, 2013 at 3:00am
Corrected an error in the configure script that would prevent setting libdir and other paths to anything other than the default.Also:
Update at Tue Apr 30 17:52:27 EDT 2013 by timAlso:
Merge branch 'master' into work

May 9, 2013 at 3:00am
A number of changes. Most changes involve support of power and ground connections; e.g., unused set or reset pins on flops. Normally direct connections to power and ground are optimized out of verilog logic, but this does not apply to cells added during post-processing. In particular, where a set or reset flop is needed but only a set+reset flop is available, one input will have to be tied. Additional code supports both positive and negative reset inputs to flops. Yet more code cleans up a few places where gate pin names were hard-coded into the scripts. Finally, the technology parameters have been removed from the "qflow_vars.sh" file, as they are technology-dependent but not project-dependent. The end-user should not be modifying these values.Also:
Update at Wed May 8 19:48:28 EDT 2013 by timAlso:
Merge branch 'master' into work

May 10, 2013 at 3:00am
Corrected a minor error preventing BDnetFanout from running.Also:
Update at Thu May 9 14:08:19 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
Corrected the BDnetFanout source as well so that a missing "ignore" file will not crash the program. Also made sure "ignore" file is properly closed after reading.Also:
Put the call to BDnet2BSpice back in the synthesis and resynthesis scripts, to create the netlist-derived SPICE netlist needed for LVS.

May 11, 2013 at 3:00am
Made modifications to BDnet2BSpice to take as an input argument the filename of a SPICE library of subcircuits representing the standard cells. This allows BDnet2BSpice to match the port order of the standard cells, as the BDNET netlist cannot be assumed to have the same port order (especially as the BDNET format does not even refer to the power connections). Also added handling of arguments passed for the name of the power and ground nets. Added the SPICE file for the osu035 technology to the example technology database in qflow, and modified the synthesis scripts to use the new syntax for BDnet2BSpice.Also:
Update at Fri May 10 13:33:32 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
Corrected an error in the core bounding box position calculated by place2def2.tcl, which was causing the tool to sometimes generate obstruction regions over part of the core. When gate pins were far enough to the right to be under that obstruction, qrouter could no longer route to them.

May 12, 2013 at 3:00am
Corrected the unused input to a DFFSR when used as a set-only or reset-only flop, when the set and/or reset pins are inverted.Also:
Update at Sat May 11 09:22:40 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
Expanded the verilog preprocessor to handle "parameter" statements, which VIS does not.

May 14, 2013 at 3:00am
Small modification to vpreproc (nonfunctional)Also:
Update at Mon May 13 11:26:32 EDT 2013 by timAlso:
Merge branch 'master' into work

May 17, 2013 at 3:00am
Modified qflow to add the magic startup script to the layout directory, and to substitute the path to the techfile into the startup script in the install directory.Also:
Update at Thu May 16 10:34:43 EDT 2013 by timAlso:
Merge branch 'master' into work

July 15, 2013 at 3:00am
Accidental commit of object files and other temporary build files. Will be removed.Also:
Update at Sun Jul 14 15:34:16 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
Removed temporary build files from the distribution.

July 16, 2013 at 3:00am
Corrected an error which was setting the current working directory name to lowercase when generating paths, causing errors with directory names having capital letters in them.Also:
Update at Mon Jul 15 15:12:58 EDT 2013 by timAlso:
Merge branch 'master' into work

July 18, 2013 at 3:00am
Changed the flow so that "placement.sh" is always run with the "-d" option. This is unnecessary if the fanout buffer stage is run, but one cannot assume that the end-user will choose to run the fanout buffering, and so the placement stage should ALWAYS prepare all the files needed by the router.Also:
Update at Wed Jul 17 09:05:24 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
Made changes to "vpreproc.c" to ignore "always" blocks that either contain no references to a clock, no references to a reset signal, or both. Also modified the code to handle "always" blocks that contain a single "if" statement and therefore do not have "begin" and "end" statements. All of this just highlights the relative insanity of verilog syntax. . .Also:
Quick correction to the last commit.Also:
Added preliminary support for the Odin-II verilog parser.

July 19, 2013 at 3:00am
Corrections to the preprocessor for VIS, to remove ending semicolon from parameters, and to remove comma characters from register names where there are more than one register name per line.Also:
Update at Thu Jul 18 11:16:04 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
Some extensions to the preprocessor, restoring the ability of the former preprocessor script to handle vector subranges on the right-hand-side. Also, fixed some of the block parsing for multiple clock domains, in preparation for actually handling the multiple clock domains.

July 22, 2013 at 3:00am
Correction to vpreproc.c, which was closing the input file before writing the "endmodule" line. At best, this causes immediate errors with the downstream verilog parser.Also:
Update at Sun Jul 21 13:42:37 EDT 2013 by timAlso:
Merge branch 'master' into work

July 26, 2013 at 3:00am
This is a major update to qflow, replacing the tools "VIS" and "SIS" with "odin_II" and "abc", respectively. The flow can now handle multiple clock domains and a respectably large variety of verilog syntax.Also:
Update at Thu Jul 25 13:24:13 EDT 2013 by timAlso:
Merge branch 'master' into work

July 27, 2013 at 3:00am
Update to vpreproc, still trying to accomodate a whole bunch of random variations people use for verilog syntax.Also:
Update at Fri Jul 26 14:47:22 EDT 2013 by timAlso:
Merge branch 'master' into work

July 30, 2013 at 3:00am
Added the OSU 0.5um standard cell set, with a lot of help from Rodolfo del Valle (thanks!).Also:
Update at Mon Jul 29 18:33:01 EDT 2013 by timAlso:
Merge branch 'master' into work

July 31, 2013 at 3:00am
Modifications to the OSU 0.5um technology files to correct errors and add missing components needed by qflow.Also:
Update at Tue Jul 30 10:12:11 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
One additional modification moves one of the VDD fingers in DFFSR from being marked as an obstruction, to the VDD pin geometry. Technically, ALL of these bits of geometry should be part of the pin geometry, and not part of the obstruction. However, this particular one interferes with qflow by making qrouter believe that VDD is "boxed in" by obstructions, and prevents it from routing static VDD connections from pins to the power bus. Note, however, that one is supposed to connect signals that are tied permanently high or low to a "tiehi" or "tielo" cell, which has a small resistor between the internal connection and the power bus, and prevents potential ESD issues from having a small digital gate connected directly to a chip pin. The real issue is that there are no "tiehi" or "tielo" cells in the OSU standard cell set, and the existing problem only arises as a result of trying to hack in a direct connection to the power bus in order to make the layout match the netlist.Also:
Additional correction to the IRSIM parameter file for OSU050Also:
Update to the configure script and makefiles to correctly support the use of --with-libdir= and --with-bindir= to allow an installation in a non-default location.

August 3, 2013 at 3:00am
Modified the synthesis script to make use of newest Odin-II code, which avoids the need for a custom patch, and also allows latches to be set to 0 in the .blif file to prevent making abc unhappy. Thanks to Ken Kent for the Odin-II updates!Also:
Update at Fri Aug 2 20:05:40 EDT 2013 by timAlso:
Merge branch 'master' into work

August 16, 2013 at 3:00am
Update to vpreproc tool to (1) correctly handle parameters with spaces in the parameter definition, (2) correctly handle parameters with nested parameters in the definition, and (3) handle vector bundles in the assignment of reset values.Also:
Update at Thu Aug 15 08:41:01 EDT 2013 by timAlso:
Merge branch 'master' into work

August 17, 2013 at 3:00am
Correction to a major error that cropped up with the last update to Odin_II and ABC. ABC, unlike sis, buffers the outputs, so it becomes incorrect to remove the trailing _FF_NODE added by Odin_II to buffer outputs. Instead, only those DFF outputs that are not module outputs should have _FF_NODE removed, so that simulators can see the original signal names, and the rest should be left untouched. The synthesis flow is simplified by not requiring the use of AddIO2BDnet, although there need to be some hooks to user-space to allow AddIO2BDnet to latch asynchronous inputs or double-buffer outputs.Also:
Update at Fri Aug 16 09:53:46 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
Corrected an error in vpreproc that would overwrite the reset signal name if the reset was followed immediately by space and the close-parenthesis for the always() statement.

August 18, 2013 at 3:00am
Corrected the so-called "resynthesis" script (clock tree generator), which was still referring to "_buf" names and therefore basically failed to run. Increased the number of I/Os handled by the BDnet2BSpice and BDnet2Verilog tools, although this is a poor substitute for dynamic allocation.Also:
Update at Sat Aug 17 11:15:19 EDT 2013 by timAlso:
Merge branch 'master' into work

August 21, 2013 at 3:00am
Rewrote the clocktree algorithm to limit the number of branches in any one tree to the maximum allowed fanout. This also corrects an error in which some branches of a fanout tree could be driving no gates at all. There was also a minor error causing some buffer outputs to be printed twice in the node list; this has been fixed.Also:
Update at Tue Aug 20 17:50:01 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
Added handling of LOGIC0 and LOGIC1 generic gates for technologies whose standard cell set does not include tie-high and tie-low cells.

August 22, 2013 at 3:00am
Corrected an error in the cleanup script that was still referring to a filename with "_buf".Also:
Update at Wed Aug 21 11:43:57 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
Corrected a minor typo in place2def2.tcl, which was calling itself place2def.tcl.Also:
Implemented what are hopefully some halfway rational ways to deal with the output. Most extraneous output ends up in "synth.log". Information about what's running at what time is also dumped to the screen. Qrouter, because it can take so long to run, is teed to both synth.log and into a grep function that looks for major errors/failures but also ticks out statements every 100 routes so that the user doesn't start thinking that something has gone bye-bye.

August 23, 2013 at 3:00am
Additional work to capture errors. Within a specific qflow master script, each step is checked for one output file that it is supposed to create. If the file does not exist or is older than some key file generated earlier in the same qflow run, then the script stops and exits with an error. Note that this does not capture errors between scripts in qflow_exec.sh, yet.Also:
Update at Thu Aug 22 09:06:28 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
Added options "build" and "all" to "qflow", so that qflow can be run from the command line without remembering all the steps to write in.

August 26, 2013 at 3:00am
Corrected an error preventing use of a locally defined tech directory.Also:
Update at Sun Aug 25 09:48:02 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
Corrected the synthesis script to avoid an undefined variable error if BDnetFanout is not run due to lack of support in the technology files.

August 31, 2013 at 3:00am
Corrected an error in clocktree where an empty cluster can cause a divide-by-zero.Also:
Update at Fri Aug 30 20:16:49 EDT 2013 by timAlso:
Merge branch 'master' into work

September 2, 2013 at 3:00am
Created a new tool called "liberty2tech", that is useful for generating a flow for a new technology. It will parse a standard "Liberty" format timing file, and generate a genlib file for ABC for standard-cell mapping, and a "gate.cfg" file for BDnetFanout for load balancing. Those are the most difficult files to create for the flow.Also:
Update at Sun Sep 1 19:55:46 EDT 2013 by timAlso:
Merge branch 'master' into work

September 3, 2013 at 3:00am
Added liberty2tech compile/install to Makefile.inAlso:
Update at Mon Sep 2 08:27:12 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
Modified liberty2tech to use a simple pattern matching to determing which cells get put in the genlib file.Also:
Made some changes to avoid having scripts hard-code the DFF clock and input pins. Instead, these pin names are specified in the technology .sh script.Also:
Corrected an error preventing the use of set and reset flops.Also:
Corrected an error allowing long input/output lists to overrun memory in BDnetFanout.Also:
Modified the techfiles distributed with the OSU035 and OSU050 technologies to use the better "device" extraction models instead of the old "fet" models. This also allows the default substrate node name to be set by the Tcl variable GND, instead of being hardwired into the techfile.

September 4, 2013 at 3:00am
Added features to liberty2tech to deal with local overrides of template index values, and to handle various differences between the format of the function string. This includes handling implicit ANDs (e.g, "A B") and XOR using "^".Also:
Update at Tue Sep 3 11:42:17 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
Expanded liberty2tech to handle templates in either orientation, and to expand the index and value strings into numerical arrays for easier processing at the end (and for future, more complicated processing).Also:
Updated the genlib and gate.cfg files for osu035 and osu050 from the liberty format files that come with the standard cell distributions.Also:
And additional expansion of the function strings handled by liberty2tech, to accept a single-quote after a pin name or a nested expression, as equivalent to "!" before the pin name or expression (that is, inversion in postfix notation rather than prefix notation). This is specifically to support the pharosc cells from vlsitechnology.org. Also, fixed the tokenizer to remove trailing whitespace.

September 7, 2013 at 3:00am
Qflow corrections: postproc.tcl will not skip parsing a file if nothing is in the .init file: It still needs to replace the default flop names with the general-purpose flop cell for the technology! Also: Checked in new verilog preprocessor "verilogpp", which is a huge improvement over "vpreproc". However, it is not yet used by the synthesis script; awaiting more testing.Also:
Update at Fri Sep 6 20:22:01 EDT 2013 by timAlso:
Merge branch 'master' into work

September 8, 2013 at 3:00am
Replaced the vpreproc tool with the new verilogpp tool. This not only is better at correctly interpreting procedural blocks in verilog. It also handles `ifdef statements, includes files that are specified by `include, and makes a number of replacements of syntax that is not handled by Odin_ii. It also handles instance calls, where the instance names found in a source file are dumped to a dependency list in a file called ".dep". Changes to the synthesis script parse the .dep file and recursively call the preprocessor on the dependent files, and their dependent files, and so on. All files needed to be read by Odin_ii are dumped into an XML configuration file that Odin_ii knows how to read.Also:
Update at Sat Sep 7 14:06:39 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
One additional correction to send stderr output from abc to the log file; otherwise, program crashes cannot be caught.Also:
Using the new "-k" switch on qrouter; some changes to the osu050 tech to see what affect it has on the behavior of ABC. Apparently none. . .Also:
Correction to BDnetFanout, to avoid overwriting the string-terminating NULL when shifting characters to make room for a gate name that is longer than the original.Also:
Slight change to the last modification, nothing important. . .Also:
Removed error message reporting from "qrouter -i", because it appears to always be generating an error return code, for some reason.

September 9, 2013 at 3:00am
Corrected a fairly major error (only off by a factor of 1000!) in which the gate.cfg files for osu035 and osu050 had delay/cap in units of fs/fF, which was read by BDnetFanout as ps/fF. The liberty2tech tool was the root cause of the error. Also cleaned up some incorrect printf statements in BDnetFanout, and removed the "-k" switch for qrouter, which was experimental (and breaks when used with earlier versions of qrouter).Also:
Update at Sun Sep 8 08:49:15 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
Added to qflow the ability to add padding area to the layout with fill cells, using a user-supplied percentage fill amount. To go along with this, added the "project_vars.sh" file to the list of files generated by qflow to go in the project top-level directory. As of now, the user-supplied percentage fill is the only value used in that file, but this will be greatly expanded upon in the near future.Also:
Corrected an unbalanced parenthesis introduced into the osu050.genlib tech file.

September 10, 2013 at 3:00am
Changed the handling of fill cells completely. To get a better result from TimberWolf, each cell is now given implicit feedthrough tracks across the cell. This causes the global router to produce a solution that is much closer to a sea-of-gates router result. Instead of removing explicit feedthroughs placed by TimberWolf, the explicit feedthroughs are turned into fill cells, and retained in the layout. All of this helps to avoid routing congestion and improves the chance of getting a valid routing result.Also:
Update at Mon Sep 9 09:29:26 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
Correction to the ".par" parameter files used by TimberWolf for the two supported technologies. Specifically, correct values were entered for layer resistance and capacitance, correct values for layer width, and layer spacing was adjusted relative to layer width to provide the correct routing track spacing using the formula (track separation = metal width + metal spacing).Also:
One further small correction to a comment line with incorrect information.Also:
And a few more small things. . . added 'random.seed' to the .par file so that runs will be repeatable, and rewrote the grep function for tracking qrouter output so that it only prints every 100 commits, not when the commit is, say, 4004.Also:
Correction to the last update to place2def.

September 12, 2013 at 3:00am
Found that TimberWolf can violate track pitch when placing pins, so it is possible for pins to overlap by occupying the same grid point. Changed place2def.tcl to prevent this from happening. Also, changed the "qflow" script to handle creating the initial ".par" file in the layout directory, instead of the synthesize script. qflow now checks both the ".par" and ".magicrc" files, and in the case of a technology file update or a technology change for the project, will copy the existing file to a backup name, and generate the new file. This will avoid all sorts of weird problems caused by switching to a different technology while having a conflicting .par file or .magicrc file.Also:
Update at Wed Sep 11 12:19:30 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
Modified clocktree to pick up the random seed number (if any) that is in the .par file. Otherwise, clocktree's manipulations will invalidate the reproducibility of results from the other tools (namely TimberWolf, the only other one to use randomization). With this fix, results ARE repeatable from run to run, given the same source file and parameters.Also:
Corrected liberty2tech (once again), where a correction to the slope was not applied to all its dependent calculations. The genlib format was changed from ps to ns, as per genlib documentation, although I don't think the abc calculation are dependent on the absolute value. Still, better to stick with the documentation, to avoid confusion.

September 13, 2013 at 3:00am
Allows the technology script to set variable "resolution", which is passed on to qrouter as the "-r " option, and lets qrouter handle things on the nanometer scale, if necessary. Not used by distributed technologies osu035 and osu050.Also:
Update at Thu Sep 12 13:54:20 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
Corrected two fprintf lines in verilogpp error messages. Fixed a bdnet2cel round-off error in calculating the cell height and width of macros read from the LEF file.

September 14, 2013 at 3:00am
Modified the qflow "configure" script to allow the use of the much simpler "--with-vtr=<DIR>" in place of the separate --with-Odin_II= and --with-abc=, when both programs (or either program) comes as part of the VTR package. The original switches are still valid.Also:
Update at Fri Sep 13 10:42:08 EDT 2013 by timAlso:
Merge branch 'master' into work

September 15, 2013 at 3:00am
Added some option handling. The "project_vars.sh" file is now a place where one can specify options for different tools in the chain. The options can also be set by the technology script, which is parsed first, and overridden from "project_vars.sh", in case a specific technology has a need to specify a certain command-line option for one or more of the tools in the chain. This does not yet deal with all the options that go to the various Timberwolf tools, which are their own headache.Also:
Update at Sat Sep 14 17:11:58 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
Another change: technology is now picked up from the existing "qflow_vars.sh" file if "qflow" is being run again in the same project directory, which avoids the sort of catastrophic consequence of failing to specify "--tech" just to refresh, or just to run again off of the command line.

September 16, 2013 at 3:00am
Removed the hard-coded via stack specifier, and made it settable from the tech or user script. Added a search for a ".cfg2" file that can be appended to the ".cfg" file to add additional information for qrouter.Also:
Update at Sun Sep 15 10:22:17 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
Correction to qflow.sh.in to avoid printing messages about values used for "tech" before the command line has been parsed for a --tech switch.Also:
Corrected a typo. . .Also:
Another slight change, to move some manipulations of the .cfg file out of place2def.tcl and into placement.sh.Also:
One last correction to syntax. . .Also:
A vague attempt to parse and modify verilog statements of the form "wire <name> = <value>", which Odin_II does not like. The procedure is to break the line into two lines, "wire <name>;" and "assign <name> = <value>".

October 1, 2013 at 3:00am
Modified .gitignore for projectAlso:
Merge branch 'master' into workAlso:
Added an important initialization to the state stack pointer that will otherwise cause a crash on systems that don't zero pointers on allocation.Also:
Update at Mon Sep 30 11:47:18 EDT 2013 by timAlso:
Merge branch 'master' into work

October 3, 2013 at 3:00am
Preprocessor correction when popping out of the last "end" statement for an "always" block. I am concerned that there is a counterexample to this. . .Also:
Update at Wed Oct 2 10:12:31 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
Corrected the verilogpp source in the correct way, this time.

October 4, 2013 at 3:00am
Correction to verilogpp.c covering a case where a negative edge reset was not printed to the .init file, causing a cascade of errors downstream.Also:
Update at Thu Oct 3 11:30:57 EDT 2013 by timAlso:
Merge branch 'master' into work

October 5, 2013 at 3:00am
Added code needed to handle resets that are declared to be internal assigned wires. Very similar handling to the clocks that are assigned internal wires. The name of the reset signal is modified to ensure it can be found by the postprocessing step, then added to the modules output signal list. This keeps the synthesis tool from optimizing it out of existance. After synthesis, it is removed from the output list and given its original name. The remainder of the reset signal handling for resetting flip-flops is the same as before.Also:
Update at Fri Oct 4 17:38:59 EDT 2013 by timAlso:
Merge branch 'master' into work

October 9, 2013 at 3:00am
Some modifications to avoid redundant handling of clocks and reset signals by vmunge; correction of verilogpp to clear out tentative subcircuits that were found not to be.Also:
Update at Tue Oct 8 11:28:23 EDT 2013 by timAlso:
Merge branch 'master' into work

October 10, 2013 at 3:00am
Overhaul of qflow to eliminate all uses of the "BDNET" format in favor of the (slightly less obscure) BLIF netlist format. A few scripts that are not part of the main flow (bdnet2sim and rtl2bdnet) have not yet been modified for handling BLIF files. Also, corrected an error in BDnetFanout (now blifFanout) in which a change in units caused a maximum value setting to be in a typical range, causing odd error messages about gate strengths being too low.Also:
Update at Wed Oct 9 12:02:14 EDT 2013 by timAlso:
Merge branch 'master' into work

October 11, 2013 at 3:00am
Rewrote the verilog preprocessing and postprocessing routines to properly record module hierarchies, and track signals, clocks, and resets through the hierarchy when replacing "latch" statements with reset flops.Also:
Update at Thu Oct 10 10:28:15 EDT 2013 by timAlso:
Merge branch 'master' into work

October 12, 2013 at 3:00am
Some more modifications to the new routines, and a correction to vmunge.tcl when replacing clock and reset signals with loopback versions.Also:
Update at Fri Oct 11 09:41:14 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
Found that the substitutions previously done by blifrtl2bdnet were missing, now that BDNET files are no longer used and blifrtl2bdnet has been removed from the flow. Recast the substitutions into sed scripts and put into synthesize.sh.Also:
Further refinement of XML file generation for Odin-II to avoid repeating files that are called multiple times from different sources.

October 20, 2013 at 3:00am
A few corrections to (1) verilogpp.c for parsing "always @(*)" syntax, and (2) liberty2tech.c, to actually read the statements declaring the time and capacitance units used in the file, and to handle all the units accordingly; (3) the gate.cfg files for osu035 and osu050 to correct for errors caused by the previously incorrect liberty2tech, and (4) additions to most of the scripts and tools to use yosys as an alternative synthesis frontend. For now, qflow is not making optimal use of yosys, but will be upgraded soon. Documentation will follow, shortly.Also:
Update at Sat Oct 19 10:49:15 EDT 2013 by timAlso:
Merge branch 'master' into work

October 25, 2013 at 3:00am
Major update to support yosys, following changes made to yosys by Clifford Wolf to support set-reset flops, making yosys useable with the OSU035 standard cell set. Modified a large number of script files to support yosys as the primary synthesis frontend, while keeping Odin_II as an alternative synthesis frontend. Since yosys could synthesize the openMSP430 microcontroller, this forced me to rewrite the old and horrible parsing code in blif2BSpice and blif2Verilog to make better use of allocated memory instead of fixed-size character arrays. Documentation on the opencircuitdesign website will follow shortly.Also:
Update at Thu Oct 24 19:47:28 EDT 2013 by timAlso:
Merge branch 'master' into work

October 26, 2013 at 3:00am
Added script "ybuffer" to add buffers between internal signals and the module output, which is what "AddIO2BDnet" used to do, and what Odin_II does automatically.Also:
Update at Fri Oct 25 13:35:25 EDT 2013 by timAlso:
Merge branch 'master' into work

October 30, 2013 at 3:00am
Update with a reasonably good, working version of the vesta static timing analysis tool.Also:
Update at Tue Oct 29 20:16:05 EDT 2013 by timAlso:
Merge branch 'master' into work

October 31, 2013 at 3:00am
Added setup time calculation at path termination on a flop input. Added path loop identification. Made a few optimizations for speeing up program execution. Worst case can still be very bad, though, for long combinatorial chains with a lot of fanout points.Also:
Update at Wed Oct 30 17:51:18 EDT 2013 by timAlso:
Merge branch 'master' into work

November 1, 2013 at 3:00am
Modifed the STA to use a "--fastmode" that does not attempt to find the worst-case timing, but gets close, and does not get stuck in deep combinatorial hierarchies. The scripts have been updated to use the fast mode, as well as taking user-supplied options from the qflow_vars.sh script. Vesta does clock skew and setup time calculations now, but does not yet use wire load models.Also:
Update at Thu Oct 31 20:41:33 EDT 2013 by timAlso:
Merge branch 'master' into work

November 2, 2013 at 3:00am
A few more minor optimizations. Inverted "fast mode" so that default mode is "fast" and "--exhaustive" forces an exhaustive search. This was precipitated by the realization that the OSU035 liberty file has nonsensical data in places, such as negative propagation delays, and that for normal, sensible data sets, the fast search's greedy algorithm will always produce the correct result.Also:
Update at Fri Nov 1 20:08:35 EDT 2013 by timAlso:
Merge branch 'master' into workAlso:
Removed temporary copies of the vesta source.

November 5, 2013 at 3:00am
Added the remainder of the standard analysis types to vesta, including minimum path delay register-to-register and register-to-output, and maximum and minimum path delays for input-to-register and input-to-output.Also:
Update at Mon Nov 4 13:34:58 EST 2013 by timAlso:
Merge branch 'master' into work

November 27, 2013 at 3:00am
Important update to the clock tree insertion tool, which now iterates to produce hierarchical trees to whatever depth is needed to maintain maximum fanout counts.Also:
Update at Tue Nov 26 19:27:07 EST 2013 by timAlso:
Merge branch 'master' into work

November 28, 2013 at 3:00am
A number of changes to the flow: Mainly, incorporated the "decongest" script into a second round of place and route, that will run if and only if the router failed to route everything the first time. However, this involved other changes, such as moving the number of layers (if not default) declaration into the project_vars.sh file, reworking the way qrouter is called to parse the LEF file for routing information, so that qrouter is called outside of place2def.tcl, using a simple bootstrap configuration file. place2def only generates the "fence" of obstruction layers around the pins, then dumps this information into a file called ".obs" that is used by the placement script to construct the routing configuration file for qrouter. This rearrangement also corrected a problem where several via configuration statements were being executed after the routing, which means they were not being applied to the routing at all. The new flow with the additional decongestion placement and final routing has been run on several test cases. It shows excellent results with the osu035 standard cell set, although it is likely that the decongestion parameters will need to be changed for other technologies.Also:
Update at Wed Nov 27 16:21:48 EST 2013 by timAlso:
Merge branch 'master' into workAlso:
Modified router script to track qrouter's new output messages about "Nets remaining" instead of "TotalRoutes". Yada yada yada. See xkcd 1296.Also:
HAAAAAAAAAAAANDS (xkcd 1296)

November 29, 2013 at 3:00am
Reworked the decongestion script both to match the normalized value now produced by qrouter, and to scale up the amount of fill based on the percentage of route failures on the last qrouter run. Also changed the "fanout" feedback to the log file from the inscrutable "nchanged=" to the more obvious "gates resized:".Also:
Update at Thu Nov 28 12:02:49 EST 2013 by timAlso:
Merge branch 'master' into work

December 2, 2013 at 3:00am
Twiddled with the decongestent parameters again. It is clear that continued twiddling will not greatly improve the flow. It is necessary to do a better sorting and masking in qrouter to improve the routing solution, because there are cases of large designs failing to route in spite of having fill added up the wazoo.Also:
Update at Sun Dec 1 17:17:26 EST 2013 by timAlso:
Merge branch 'master' into work

December 21, 2013 at 3:00am
Changes to deal with problems arising from use of lower case in either the macro cell names or the tech directory name.Also:
Update at Fri Dec 20 13:05:12 EST 2013 by timAlso:
Merge branch 'master' into work

January 17, 2014 at 3:00am
Corrected an error where yosys' use of a backslash before module names would get interpreted by the script as unix escape codes. Synthesis script changed to replace the backslash with a forward slash to avoid the error.Also:
Update at Thu Jan 16 09:14:35 EST 2014 by timAlso:
Merge branch 'master' into work

January 18, 2014 at 3:00am
Modified blif2Verilog so that it changes characters ":" and "." to underscores ("_") in all signal names, because these characters are not legal verilog. Because the original verilog source cannot have such signal names, it is not anticipated that this will cause any problems with matching signal names elsewhere in the flow.Also:
Update at Fri Jan 17 17:05:31 EST 2014 by timAlso:
Merge branch 'master' into work

January 23, 2014 at 3:00am
Modified the yosys synthesis script to make use of the new commands for mapping tiehi and tielo standard cells.Also:
Update at Wed Jan 22 09:56:20 EST 2014 by timAlso:
Merge branch 'master' into work

January 24, 2014 at 3:00am
Added the "tiehipin_out" and "tielopin_out" variables to the osu035.sh and osu050.sh scripts, although there are no tie cells in those standard cell sets, mostly to let people know that the method is available, and how to use it.Also:
Update at Thu Jan 23 21:23:12 EST 2014 by timAlso:
Merge branch 'master' into work

January 26, 2014 at 3:00am
Made changes to the flow scripts so that (1) the flow properly detects when yosys has failed to generate a new output blif file, and will stop; and (2) each script of the flow will fail to run if the previous script has stopped due to a fatal error. The combination of these changes prevents qflow from continuing to run and producing output based on results of some previous run.Also:
Update at Sat Jan 25 12:26:24 EST 2014 by timAlso:
Merge branch 'master' into work

February 7, 2014 at 3:00am
Made a change to the placement script to check if "qrouter -i" generated an output ".info" file and halt if not. This prevents the placement from otherwise proceeding on to the place2def.tcl script and failing with an unhelpful and obscure error message.Also:
Update at Thu Feb 6 12:06:04 EST 2014 by timAlso:
Merge branch 'master' into work

February 8, 2014 at 3:00am
Corrected an error pertaining to the order in which qrouter is told to read the technology and macro LEF files. This was corrected in the section of code that writes the configuration file for the Tcl-based version of qrouter but was not fixed in the section of code that writes a slightly different syntax of configuration file for the non-Tcl-based version of qrouter.Also:
Update at Fri Feb 7 12:38:22 EST 2014 by timAlso:
Merge branch 'master' into work

February 9, 2014 at 3:00am
Corrected an error in vesta that would invert the tables, swapping times with capacitances, with obviously bad results.Also:
Update at Sat Feb 8 11:29:24 EST 2014 by timAlso:
Merge branch 'master' into work

February 16, 2014 at 3:00am
A very quick fix to ybuffer.tcl to correct an error that could produce a bad output netlist when any output name is a substring of another output name. However, this should be replaced shortly with a better implementation within yosys.Also:
Update at Sat Feb 15 15:58:44 EST 2014 by timAlso:
Merge branch 'master' into workAlso:
Updated synthesize_yosys to make use of the "-bits" option to the "iopadmap" command in yosys v.0.2.0. This replaces the use of script "ybuffer.tcl" to insert output buffers, and is more general in that it can also be used to add input buffers or handle bidirectional ports, although anything beyond adding output buffers requires a custom synthesis script.

February 17, 2014 at 3:00am
Corrected Vesta for lookup tables that are 1-dimensional.Also:
Update at Sun Feb 16 17:15:48 EST 2014 by timAlso:
Merge branch 'master' into work

April 9, 2014 at 3:00am
Added routine "getfillcell.tcl" that searches a LEF file for fill cells according to the pattern given in the tech setup shell script, and a .par file with a feedThruWidth definition, and returns the name of the fill cell whose width matches the one used in the .par file.Also:
Update at Tue Apr 8 17:42:20 EDT 2014 by timAlso:
Merge branch 'master' into work

May 27, 2014 at 3:00am
Update at Mon May 26 09:55:12 EDT 2014 by tim

May 28, 2014 at 3:00am
Update at Tue May 27 19:10:21 EDT 2014 by tim

May 30, 2014 at 3:00am
Update at Thu May 29 10:52:52 EDT 2014 by tim

May 31, 2014 at 3:00am
Update at Fri May 30 14:41:25 EDT 2014 by tim

June 1, 2014 at 3:00am
Update at Sat May 31 14:50:58 EDT 2014 by tim

July 10, 2014 at 3:00am
Correction to the clocktree script to handle cells such as tiehi/ tielo that have no inputs, instead of generating an error and exiting.Also:
Update at Wed Jul 9 12:00:47 EDT 2014 by timAlso:
Merge branch 'master' into work

July 13, 2014 at 3:00am
Additional diagnostic statements printed in the STA tool.Also:
Update at Sat Jul 12 14:18:44 EDT 2014 by timAlso:
Merge branch 'master' into workAlso:
Fixed an error that causes vesta to crash if it has bad input and cannot find a valid netlist.Also:
Corrected an error in blifFanout that causes a crash if the gate strength changes from a 1-character suffix (e.g., "1") to a 2-character suffix (e.g., "10").

July 18, 2014 at 3:00am
Added support for structural verilog in-line, pending update of yosys to revision 0.3.1.Also:
Update at Thu Jul 17 08:34:09 EDT 2014 by timAlso:
Merge branch 'master' into work

Date:June 19, 2011
Initial offering of the full digital flow with the new open-source
detail router qrouter.

Date:June 21, 2011
Modified the bdnet2cel.tcl script to do much more thorough
parsing of the LEF file, including ignoring various sections that
are normally found in LEF files (but not needed by the converter
script), and parsing layer information for track pitches. The pins
must be declared with dimensions equal to the route pitches, because
TimberWolf will place pins next to each other, and if they are placed
closer together than the route pitch, they will overlap and not be
routable.

Date:December 6, 2012
Made substantial updates to the place2def2.tcl script. This
corrects for track offset from the origin and also corrects an error
that gave all the pin positions an offset that could potentially
drop the pins outside of the routing track area, making them
unroutable.

Date:December 7, 2012
Added clocktree.tcl to the list of files to download. This
script tool breaks up large fanout nets (like the clock) with
buffer trees. It is not particularly useful without the load
balancing tool that I have not yet converted to a generic process.