Abstract:

The invention is related to a method and a device for encoding of a bit
sequence.
Said method comprises generating, for each run of Ones comprised in the
bit sequence, a unary representation of length of the respective run of
Ones, generating a first sequence by concatenating the generated unary
representations of lengths of runs of Ones, generating, for each run of
Zeroes comprised in the bit sequence, a unary representation of the
length of the respective run of Zeroes, generating a second sequence by
concatenating the generated unary representations of lengths of runs of
Zeroes, and bit plane encoding the generated first and second sequence of
unary representations.
In most cases, overall entropy of bit planes of unary representations of
run lengths is smaller than entropy of the bit sequence. Thus, more
compact encoding can be achieved.

Claims:

1. Method for encoding a bit sequence, said method comprisesgenerating,
for each run of Ones comprised in the bit sequence, a unary
representation of the length of the respective run of Ones,generating a
first sequence by concatenating the generated unary representations of
lengths of runs of Ones,generating, for each run of Zeroes comprised in
the bit sequence, a unary representation of length of the respective run
of Zeroes,generating a second sequence by concatenating the generated
unary representations of lengths of runs of Zeroes andbit plane encoding
the generated first and second sequence.

2. Method of claim 1, whereinbit planes of said first sequence and bit
planes of said second sequence are encoded separately.

3. Method of claim 1, wherein bit plane encoding comprises:generating a
third sequence of unary representations of lengths of runs of Ones in a
bit planegenerating fourth sequence of unary representations of lengths
of runs of Zeroes in said bit plane, andbit plane encoding the generated
third and fourth sequence of unary representations.

4. Method according to claim 1, said method comprises the steps of(a)
receiving a current bit of said sequence of bits,(b) receiving a next bit
of said sequence of bits,(c) outputting a bit having a value different
from the current bit's value if the next bit is of a preferred possible
bit value and outputting a bit having the current bit's value,
otherwise,(d) repeating steps (b) and (c) until the end of the bit
sequence (BS) is reached wherein said next bit is used as current bit
and(e) compressing the outputted bits.

5. Method for forming a sequence of bits from first and second encoded bit
planes, said method comprises the steps ofdecoding the first bit planes
resulting in a first sequence of unary representations,decoding the
second bit planes resulting in a second sequence of unary
representations,using the first sequence for generating runs of Ones
wherein, for each unary representation comprised in the first sequence, a
run of Ones of corresponding length is generated,using the second
sequence for generating runs of Zeroes wherein, for each unary
representation comprised in the second sequence, a run of Zeroes of
corresponding length is generated, andforming the sequence of bits by
alternating the generated runs of Zeroes and the generated runs of Ones.

6. Method according to claim 5, wherein said method comprises the steps
of(a) using a preferred possible bit value as current value,(b) receiving
a current bit of said sequence of bits,(c) outputting a bit of said
current value,(d) changing the current value if the current bit is of
said preferred possible bit value and(e) repeating steps (b)-(d).

7. Device for encoding a bit sequence, said device comprisesgenerating
means for generating, for each run of Ones comprised in the bit sequence,
a unary representations of the length of the respective run of Ones,said
generating means being adapted for generating, for each run of Zeroes
comprised in the bit sequence, a unary representation of the length of
the respective run of Zeroes,concatenating means for generating a first
sequence by concatenating the generated unary representations of lengths
of runs of Ones,said concatenating means being adapted for generating a
second sequence by concatenating the generated unary representations of
lengths of runs of Zeroes andmeans for bit plane encoding the generated
first and second sequence of unary representations.

8. Device for decoding a sequence of bits from first and second encoded
bit planes, said device comprisesdecoding means for decoding the first
bit planes resulting in a first sequence of unary representations,said
decoding means being adapted for decoding the second bit planes resulting
in a second sequence of unary representationsgenerating means for using
the first sequence for generating runs of Ones wherein, for each unary
representation comprised in the first sequence, a run of Ones of
corresponding length is generated,said generating means being adapted for
using the second sequence for generating runs of Zeroes wherein, for each
unary representation comprised in the second sequence, a run of Zeroes of
corresponding length is generated, andmeans for forming the sequence of
bits by alternating the generated runs of Zeroes and the generated runs
of Ones.

Description:

BACKGROUND

[0001]The invention is related to a method and a device for encoding a bit
sequence.

[0002]Bit sequences results, for instance, from encoding digital
multimedia content like audio, video, combinations thereof or side
information accompanying such content. Encoding such bit sequences for
compact representation of at least one of the encoded content and the
side information is crucial for efficient use of storage capacities and
transmission bandwidth.

[0003]Each bit sequence, which is not a trivial bit sequence consisting
either only of Zeroes or only of Ones, may also be understood as
consisting of one or more runs of Zeroes alternating with one or more
runs of Ones wherein each run is a contiguous sub-sequence of one or more
equally valued bits which is immediately followed and immediately
preceded by another run of bits each having a different bit value as long
as the run is neither the very first nor the very last run of the bit
sequence.

[0004]In bit sequences, bits of a first possible bit value and bits of a
different second possible bit value commonly occur with significantly
different frequencies, e.g. Zeroes are more likely than Ones or vice
versa. Then, entropy of the bit sequence is smaller than the number of
bits comprised in the bit sequence.

[0005]If so, there is redundancy in the bit sequence which can be removed
by lossless compression.

[0006]It is known to use an entropy coding method for lossless compression
of bit sequences. Basically, there are three kinds of entropy coding
method: (1) variable length coding (VLC), like Huffman coding, (2)
arithmetic coding, and (3) dictionary-based compression, like Lempel-Ziv
compression or Lempel-Ziv-Welch compression.

[0007]The effect of entropy coding is that, difference between entropy of
the compressed bit sequence and number of bits comprised in the
compressed bit sequence is smaller than difference between entropy of and
number of bits comprised in the bit sequence prior to compression.

[0008]There is ongoing effort in the art for an alternative approaches in
principle adapted for improving encoding.

INVENTION

[0009]In order to achieve such improvement, the invention proposes a
method for encoding a sequence of bits according to claim 1 and a
corresponding device according to claim 7.

[0010]Said method for encoding a sequence of bits comprises generating,
for each run of Ones comprised in the bit sequence, a unary
representations of the length of the respective run of Ones, generating a
first sequence (RLS1) by concatenating the generated unary
representations of lengths of runs of Ones, generating, for each run of
Zeroes comprised in the bit sequence, a second sequence of unary
representations of the length of the respective run of Zeroes, generating
a second sequence (RLS0) by concatenating the generated unary
representations of lengths of runs of Zeroes, and bit plane encoding the
generated first and second sequence.

[0011]In most cases, overall entropy of bit planes of unary
representations of run lengths is smaller than entropy of the bit
sequence. Thus, more compact encoding can be achieved. For sure, overall
entropy of the bit planes will not exceed entropy of the bit sequence.

[0012]In an embodiment bit planes of said first sequence and bit planes of
said second sequence are encoded separately.

[0013]In another embodiment bit plane encoding comprises generating a
third sequence of unary representations of lengths of runs of Ones in a
bit plane generating fourth sequence of unary representations of lengths
of runs of Zeroes in said bit plane, and bit plane encoding the generated
third and fourth sequence of unary representations.

[0014]In yet another embodiment, the method further or solely comprises
the steps of (a) receiving a current bit of said sequence of bits, (b)
receiving a next bit of said sequence of bits, (c) outputting a bit
having a value different from the current bit's value if the next bit is
of a preferred possible bit value and outputting a bit having the current
bit's value, otherwise, (d) repeating steps (b) and (c) until the end of
the bit sequence is reached wherein said next bit is used as current bit
and (e) encoding the outputted bits.

[0015]In said yet another embodiment of the method, the bit may be
outputted to an adjuvant sequence if the current bit is of said preferred
possible bit value and the bit may be outputted to a further adjuvant
sequence, otherwise.

[0016]The adjuvant sequence and the further adjuvant sequence, each, may
comprise sub-sequences corresponding to different possible positions of a
bit in runs. Then, the yet another embodiment of the method may further
comprise outputting the bit to that one of the sub-sequences which
corresponds to the current bit and the current bit's position in a
current run.

[0017]The invention further proposes a method for decoding a sequence of
bits from encoded first and second bit planes according to claim 5 and a
corresponding device according to claim 8.

[0018]Said method for forming a sequence of bits comprises the steps of
decoding the first bit planes resulting in a first sequence of unary
representations, decoding the second bit planes resulting in a second
sequence of unary representations, using the first sequence for
generating runs of Ones wherein, for each unary representation comprised
in the first sequence, a run of Ones of corresponding length is
generated, using the second sequence for generating runs of Zeroes
wherein, for each unary representation comprised in the second sequence,
a run of Zeroes of corresponding length is generated, and forming the
sequence of bits by alternating the generated runs of Zeroes and the
generated runs of Ones.

[0019]In an embodiment, said decoding method comprises the steps of (a)
using a preferred possible bit value as current value, (b) receiving a
current bit of said sequence of bits, (c) outputting a bit of said
current value, (d) changing the current value if the current bit is of
said preferred possible bit value and (e) repeating steps (b)-(d).

DRAWINGS

[0020]Exemplary embodiments of the invention are illustrated in the
drawings and are explained in more detail in the following description.

[0021]In the figures:

[0022]FIG. 1 depicts a first example input sequence, an exemplary run
length sequence, further exemplary run length sequences and a first and a
second set of exemplary bit planes generated in course of application of
an exemplary embodiment of the inventive method,

[0023]FIG. 2 depicts yet further exemplary run length sequences and yet
further exemplary bit plane sequences generated in course of iterative
application of the exemplary embodiment of the inventive method and

[0024]FIG. 3 depicts a second example input sequence as well as another
exemplary run length sequences generated in course of application of an
exemplary embodiment of the inventive method.

EXEMPLARY EMBODIMENTS

[0025]In FIG. 1, a first exemplary input bit sequence BS of 30 bits length
is depicted. In the example of FIG. 1, Zeroes and Ones occur equally
frequent in BS, i.e. there are 15 Zeroes and 15 Ones in BS. The entropy
of the first exemplary input bit sequence BS can be calculated as

H(B)=-15*log2(15/30)-15*log2(15/30)=30

[0026]So it appears as if 30 bits are required for representing BS.

[0027]But, from the first exemplary input bit sequence BS an exemplary run
length sequence RLS can be formed wherein BS can be reconstructed from
RLS.

[0028]RLS is exemplarily formed from outputted bits of the following
method: (a) receiving a current bit of said input bit sequence BS, (b)
receiving a next bit of said input bit sequence BS, (c) outputting a bit
having a value different from the current bit's value if the next bit is
of a preferred possible bit value, which is One in the example, and
outputting a bit having the current bit's value, otherwise, (d) repeating
steps (b) and (c) until the end of the bit sequence is reached wherein
said next bit is used as current bit.

[0029]In RLS, there is a One for each Zero of BS which immediately
precedes a One. Further, for each One of BS which immediately precedes a
One there is Zero in RLS.

[0030]Since BS comprises 8 Zeroes immediately preceding a One and only 7
Ones immediately preceding a One, Zeroes and Ones appear with different
frequencies in BS and in RLS.

[0031]That is, in RLS there are only 14 Zeroes but 16 Ones. Thus, entropy
of RLS is:

H(RLS)=-14*log2(14/30)-16*log2(16/30)=29.90376

[0032]Thus, for representing RLS still 30 bits are required.

[0033]Two further exemplary run length sequences may be formed from RLS if
in step (c) the bit is outputted to a first further run length sequence
if the current bit is of said preferred possible bit value and the bit is
outputted to a second further run length sequence, otherwise.

[0034]The first further run length sequence RLS0 comprises those bits of
RLS for which the corresponding bit of BS is Zero. And a second further
run length sequence RLS1 comprises those bits of RLS for which the
corresponding bit of BS is One.

[0035]From RLS0 a first set of three exemplary bit planes CS01, CS02 and
CS03 is generated.

[0036]CS01 contains those bits of RLS0 which are not immediately preceded
by a Zero-valued bit.

[0037]CS02 contains those bits of RLS0 which are immediately preceded by a
Zero-valued bit in RLS0 which is sorted into CS01. Thus, the number of
bits contained in CS02 equals the number of Zeros comprised in CS01.

[0038]Finally, CS03 contains those bits of RLS0 which are immediately
preceded by a Zero-valued bit in RLS0 which is sorted into CS02. As for
CS02, number of bits contained in CS03 equals the number of Zeros
comprised in CS02.

[0039]As CS03 does not contain any Zeros there is no CSO4.

[0040]CS01, CS02 and CS03 may be sub-sequences of an additional adjuvant
bit sequence consisting of a concatenation of CS01, CS02 and CS03. The
overall entropy of the first set is:

H(CS01)+H(CS02)+H(CS03)=11.2451

[0041]In the same way, a second set of four exemplary bit planes CS11,
CS12, CS13 and CS14 is generated from RLS1.

[0042]The overall entropy of the second set is:

H(CS11)+H(CS12)+H(CS13)+H(CS14)=10.39036

[0043]Thus, overall entropy of the first set and the second set is far
smaller than entropy of BS although BS is still reconstructible from the
first and the second set.

[0044]The principle may be applied in iteration. That is, at least one of
CS01 and CS11 may be taken as input sequences. This is exemplarily
depicted in FIG. 2. From CS01 and CS11, sequences 0RLS and 1RLS are
formed. The bits of 0RLS and 1RLS are separated in two pairs of
sequences, namely 0RLS0, 0RLS1, 1RLS0 and 1RLS1. The bits of 0RLS0,
0RLS1, 1RLS0 and 1RLS1 are sorted into different contexts.

[0045]Bits of 0RLS0 are sorted into the contexts 0CS01, 0CS02 and 0CS03
while bits of 0RLS1 are sorted into the contexts 0CS11 and 0CS12.

[0046]And, bits of 1RLS0 are sorted into the contexts 1CS01 and 1CS02
while bits of 1RLS1 are sorted into the contexts 1CS11, 1CS12 and 1CS13.

[0047]Thus, CS01 is replaced by 0CS01, 0CS02, 0CS03, 0CS11 and 0CS12. And
CS11 is replaced by 1CS01, 1CS02, 1CS11, 1CS12 and 1CS13.

[0048]So, BS is represented by CS02, CS03, CS12, CS13, CS14, 0CS01, 0CS02,
0CS03, 0CS11, 0CS12, 1CS01, 1CS02, 1CS11, 1CS12 and 1CS13. The overall
entropy of the representation of BS by help of these bit plane sequences
is 15.509775 and thus almost half the entropy of BS as is.

[0049]Entropy reduction can be exploited at least to some degree for
instance by using context based entropy coding or bit plane encoding for
further compressing these bit plane sequences. For instance context based
arithmetic coding, context based Huffman-coding or dictionary-based
compression may be used.

[0050]Although entropy is just a rough estimate of coding performance,
arithmetic coding, for instance, can almost achieve entropy especially
when input data size is large enough, e.g., 1024 bits.

[0051]The invention exploits that in most sequences the number of
consecutive Zeros or consecutive Ones is highly correlated.

[0052]The proposed method can be utilized together with any traditional
entropy coding method. Some flag bit(s) can be inserted into the bit
stream to indicate whether the entropy coding method was applied to the
bit sequence, directly, or whether the entropy coding method was used in
course of the proposed method.

[0053]In FIG. 3, a second exemplary input bit sequence BS' of 30 bits
length is depicted. Again, Zeroes and Ones occur equally frequent in BS',
i.e. there are 15 Zeroes and 15 Ones in BS. Thus entropy of the second
exemplary input bit sequence BS' is 30 and BS' appears as if could not
further be compressed.

[0054]But, if another run length sequence RS' is formed from the second
exemplary input bit sequence BS' in the same way as the run length
sequence RLS is formed from BS a significant entropy reduction can be
achieved already by forming RLS'.

[0055]That is, RLS' comprises only 6 Zeroes but 24 Ones and has entropy of
21.65784.

[0056]By help of a dictionary mapping sequences of 1111 onto 1, sequences
of 1001 onto 01, sequences of 1110 onto 001 and sequences of 11 onto 0001
(as stop sequence for representing the last two bits), RLS' can be
transformed into compressed output sequence COS' consisting of only 17
bits with 8 Ones and 9 Zeroes with entropy of about 16.96.

[0057]The input bit sequence BS may be a comprised in a longer bit
sequence to-be-compressed or it may be the whole bit sequence
to-be-compressed.

[0058]For long bit sequences to-be-compressed, there is an embodiment of
the invention proposed which allows for transforming the bit sequence
into a run length sequence bit by bit. That is, connected to a first
encoder which sequentially generates the bits of the bit sequence, there
may be a transformation device which receives these generated bits and
outputs, for each received bit, an output bit. Thus transformation of the
bit sequence into the run length sequence can be done on-the-fly with
only one bit latency.

[0059]Said transformation device comprises means for receiving bits of a
sequence BS, BS', means for outputting bits to a second encoder which
encodes the outputted bits. The means for outputting bits are adapted
such that the value of an outputted bit dependents on the values of a
previously received bit and a currently received bit wherein the
previously received bit immediately precedes the currently received bit
in the bit sequence BS, BS'. That is, the outputted bit has a value
different from the value of the previously received bit if the currently
received bit is of a preferred possible bit value and, otherwise, has the
value of the previously received bit. The device is adapted for using the
currently received bit as previously received bit after outputting a bit
and for repeating reception of bits and outputting of bits until the end
of the bit sequence BS is reached. Thus, for each previously received bit
there is a corresponding outputted bit. For the last bit of the bit
sequence, said last bit having no subsequent bit thus never being a
previously received bit, a bit of said preferred possible bit value is
outputted by the device.

[0060]The device may comprise a counter whose value is initialized to One,
wherein the counter value is increased by One if the value of the
previously received bit equals that of the currently received bit and is
reset to One if the value of the previously received bit differs from
that of the currently received bit.

[0061]Then, the second encoder may be adapted for context-based arithmetic
encoding of the outputted bits wherein the context of an outputted bit is
defined by at least one of the value of the corresponding previously
received bit and the counter value.