D&R Industry Articles (September 2013)

Articles for the Week of September 30, 2013

There are alternatives to putting an OTP on-chip. The data can be held off-chip in some sort of programmable memory (or, perhaps, ROM). But this obviously has the disadvantage of requiring the cost of an extra chip. In smartphones it is not just the cost of another chip that is a problem, but the additional volume taken up by two chips. There is just not a lot of room inside a smartphone to fit everything.

Articles for the Week of September 23, 2013

Growing complexity of System-on-Chips (SoCs), functional debug of the additional hardware becomes a greater challenge. There may be multiple SoCs with common interface present in the same package. With evolution of these complex architecture, need arises not only for design innovation but also for verification strategy which can help verify such design quickly and effectively. This paper discuss about the need to have such design and its efficient verification methodology.

Articles for the Week of September 16, 2013

This paper describes the methodology and technology we used, to assess full-chip dynamic and static IR-drop for such complex and huge SoCs. Firstly, it outlines power-grid weakness and hot spot exploration using a testcase of STB SoC in 65nm WireBond and Flipchip variants. Additionally, it outlines the complexity in performing voltage drop analysis in vector-less mode without a VCD in terms of methodology and technology, specifically due to flipchip complexity.

Articles for the Week of September 9, 2013

SystemVerilog UVM sequences are a powerful way to model stimulus and response for functional verification. Unfortunately using SystemVerilog UVM sequences can require an extensive background in SystemVerilog, the UVM and object oriented programming. This paper explains a collection of techniques to allow the power of sequences with familiarity and simplicity of calling tasks.