"Qualcomm is looking to monolithic 3D and smart circuit architectures to make up for the loss of traditional 2D process scaling as wafer costs for advanced nodes continue to increase." Speaking in a keynote at DAC 2014 in San Francisco, Qualcomm's vice president of engineering, Karim Arabi, is reported to argue that 3D and EDA need to make up for Moore's Law.

This was the third time in the past year that Qualcomm executives have made such a call at major industry conferences. At IEDM 2013, Geoffrey Yeap, Qualcomm's VP of technology, stated in his invited talk: "As performance mismatch between transistors and interconnects continue to increase, designs have become interconnect-limited. Monolithic 3D (M3D) is an emerging integration technology poised to reduce the gap significantly between transistors and interconnect delays to extend the semiconductor roadmap way beyond the 2D scaling trajectory predicted by Moore's Law." Yeap provided the following chart for the growing gap between transistor delay and interconnect delay:

BEOL performance/area/cost scaling is the foremost issue for the 10nm and 7nm technology nodes.(Click here to see a larger image.)

Earlier that year, Robert Gilmore, Qualcomm's VP of engineering, in his invited talk at VLSI 2013 (Kyoto, Japan), used almost the same words and provided the following illustration (note the wafer is face-down):

Typical layer structure of a monolithic 3D-IC(Click here to see a larger image.)

Clearly, there seems to be a concentrated effort by Qualcomm to promote the development and adoption of monolithic 3D. In fact, Qualcomm has done more than just talking -- it has been investing in monolithic 3D development tools with institutions such as Georgia Tech (see their GTCAD LAB website reporting technology transfer in 2012 and 2014). Qualcomm has also been filing patents in this area, and recently announced an agreement to work with CEA-Leti.

It would seem that the number one motivation behind these efforts is Qualcomm's concern about future cost reductions. Early in 2012, Jim Clifford, Qualcomm's VP and GM (at that time), in his plenary talk at the SPIE conference titled A Mobile Wireless Phenomenon: a Continued Need for Advanced Lithography, made it very clear with his second slide. At that time there were already some concerns with the rollout schedule for EUV (extreme ultraviolet lithography). Jim called on the conference attendees to make sure to solve the escalation of advanced lithography cost, which was already dominating more than 50% of the overall advanced device cost. Jim presented the following curve showing the historical 29% cost reduction per year and the looming problem with the production cost beyond 28 nm:

Ongoing chip cost reduction is a must for new technology nodes. (Click here to see a larger image.) (Source: ITRS)

Jim continued to say: "If the next node doesn't cost less than the last node, we got a problem because I don't think the demand will be there." Well, it is now clear that EUV is not ready and that dimensional scaling below 28nm will require double and triple lithography with its associated additional costs.

Back to the DAC 2014 keynote, Arabi explained: "Mobile is becoming a centre of gravity for the user. It is providing a unique opportunity… but it becomes a challenge to develop, because you have to integrate them at lower power and low cost as well… One of the biggest problems is cost. We are very cost sensitive. Moore's Law has been great. Now, although we are still scaling down, it's not cost-economic anymore. It's creating a big problem for us." As I reported in my recent column, 28nm -- The Last Node of Moore's Law, dimensional scaling below 28 nm will result in increasing device cost. This was echoed multiple times at this DAC by other keynote speakers such as Hossein Yassaie, CEO of Imagination Technologies, who said: "Moore's Law is really over from my point of view. It's not that it can't scale, it's that the cost is not going down anymore."

Shrinking chips: number and length of transistors bought per $ (forecast). (Click here to see a larger image.)(Source: Linley Group)

Cost is not the only problem with dimensional scaling. The following IBM slide illustrates that interconnect now dominates device power:

The interconnect's effect on power is getting worse with dimensional scaling. In his DAC keynote, Arabi also stated: "Interconnect RC is inching up as we go to deeper technology. That is a major problem because designs are becoming interconnect-dominated. Something has to be done about interconnect. What needs to be done is monolithic three-dimensional ICs… So we are looking at true monolithic 3D. You have normal vias between different stacks. Then interconnect lengths will be smaller than with 2D. If we can connect between layers the delay becomes smaller. This is a technology for the end of the decade, but it can give us an advantage of one process node, with a 30% power saving and a 40% gain in performance."

Clearly, monolithic 3D integration has a very important role for the future of the semiconductor industry. It is therefore fitting that the traditional IEEE conference on SOI has extended its scope and now calls itself S3S: SOI technology, 3D Integration, and Subthreshold Microelectronics. The 2014 S3S Conference is scheduled for October 6-9, 2014, at the Westin San Francisco Airport. This would be a great opportunity to learn more about monolithic 3D technology, with five invited presentations covering topics from design tools to monolithic 3D NAND and other 3D memories. CEA Leti will present their work on CMOS monolithic 3D IC. Researchers from MIT and Stanford will present manufacturing monolithic 3D devices with materials other than silicon.

@chipmonk: I like your statement "amateurs getting too excited with PowerPoint engr!" For the most part, it has been like that. There are however some products that are seeing some commercial success (like Samsung's memory products). Perhaps some one from Samsung can share something here on the cost reduction roadmap for TSV-based products in the future.

As far jumping on Qualcomm's bandwagon on monolithic IC and going along for the ride, there are definitely risks involved (as seen by some who rode Q's TSV bandwagon in the past! Javelin any one?!!)

most always its technology challenge that raises the cost of using it. for the most part the most common process flow & materials for TSVs have been stuck in a blind alley - a consequence of amateurs getting too excited with PowerPoint engr.

The question regarding cost reduction for monolithic 3D is a good one. We have devoted a section on the MonolithIC 3D web site to present it, titled - 3D-IC Edge - http://www.monolithic3d.com/3d-ic-edge1.html. I believe you will enjoy reading it and I hope to get inputs for additional advantages.

The 3D NAND, which is now in mass production, is a good example for the cost reduction enabled by monolithic 3D, as multiple layers are simultaneously processed providing road map for cost reduction by scaling up.

Yes most sources are along the lines of the fourth picture. In the third picture, they have 22/20 as the last node. That would only make sense if they had only a few mask adders for double patterning, or if they had relaxed design rules to begin with (but using the most advanced transistors).

Thank you for the support. I agree that TSV has the potential to reduce significantly the off chip interconnect and accordingly provide are real reduction in power and increase of speed for most system out there. It also seems that the slow adaption of TSV is not due to technology challenge but rather the high cost associated with it.

But this has very little to do with monolithic 3D as those technologies complement each other rather. I believe that there is clear evidence out there that the interest in monolithic 3D is not the result of issues with TSV but far more with issues with dimension scaling. Dimension scaling while still going on had stopped providing the traditional cost reduction it once did. The delays in EUV make it clear that these are not a short time hick-up but rather a paradigm shift.

It is clear to me that the industry need to put far more efforts behind monolithic 3D as continuation of cost reduction would be critical for the industry ability to fulfill the promise of the emerging market of IOT and wearable.

Zvi what do you think TSV based 3-d stack does to RC delay off chip ? Just the same as on - chip and this is really the main driver for using TSVs in the context of SoC - DRAM combinations

French Govt. funded LETI too started with using TSVs to integrate SoC s to DRAM. After buiding and evaluating some simplified TVs including using a SoC of their own design, they too have backed off and then just a couple months back ( soon after Samsung started reporting their 3-d NAND ) started publicizing a change in direction to monolithic 3-d stacking of transistors.

If you have following reports in EE Times etc. its only after that QualComm started showing interest in 3-d stacking of transistors perhaps even for some super - large SoC of the future with zillion cores.

If you are privy with any actual support by Qualcomm of the recently initiated LETI R&D on monolithic 3-d stacking of transistors as you claim, then pray share it with the rest of us.

This just confirms that Qualcomm's own effort to do 3-d stacking of chips using TSVs has bombed out. So now they want to switch horses to stacked transistors. The question is who is going to foot the R&D bill ? The fabless wonders have made themselves very attractive to Wall St by using technology developed by IDMs in the US which then "diffused" to off shore Foundries through various "channels". Are fabless chip vendor like QCOMM going to subsidize any of the R&D for 3-d stacking of xsistors ? Is Wall st. going to let them ?

Regarding the statement ""Mobile is becoming a centre of gravity for the user...," it is true to a large extent but not quite the complete picture. More rigorous computing and storage is at the cloud layer for these types of mobile-centric use cases. Therein, M3D makes more sense in mobiles than in those in servers and switches at the cloud layer. Nonetheless, if M3D progresses to a state where it is cost-competitive and yields are proven, there is definitely opportunities for fabless / IDM companies to innovate. But I see this as still way out in to the future. In the interim, 2.5D/3D stacking is here to stay!