Thermal Layout Considerations for Integrated FET Chargers

Hello. Today's topic is about thermal layout considerations for integrated FET chargers. The agenda is, why this topic? We'll go over PCB electrical characteristics, DC parasitics, AC parasitics, grounding, then skip to PCB thermal characteristics, conduction, convection, and examples of layouts.
Why this topic? What design component is most often overlooked, any guesses? It's the PCB design. PCB is as critical as any other component. Use the same care with this design of the PCB as with any other IC, FET, inductor, caps, and other components.
Why is layout important? The placement of the components affects the connection impedance. Ground plane design effects the connection impedance. Electrical and thermal impedance affect current and heat flow. AC current across impedance causes noise. Heat flow across the thermal impedance causes temperature rise.
First we'll be talking about DC parasitics. Copper is a good conductor but not a perfect conductor. The placement of the copper, the copper thickness, and routing affects the regulation, transient response, efficiency, temperature rise, and noise immunity.
OK, here metals are good conductors. And here in the diagram we see a trace with cross-sectional area A and length l. You notice down at the bottom that resistance is the resistivity in the numerator times the length divided by the cross sectional area.
So the sensor resistivity is in the numerator, and we want a small resistance. We want a small rho value. You look in the table, and silver is the lowest. But that's kind of expensive. And not far behind is copper. So we use copper. And then you notice that lead, tin-lead solder, is about 10 times more resistive.
OK, we need to have a good way to estimate copper resistance so you can look at a trace and know what resistance it is. So we do this by taking the formula and breaking a trace. Say it's 100 mil trace by 1 inch long. So there's 10 squares if you divide it into equal squares with the width is l and the length is l.
The l's cancel out in the formula, and you get resistance equals rho over t. You plug in the value of 2.8 mils for 2 ounce copper, the bottom row in the table, and come out with 0.26 milliohms per square. So that one inch trace with 10 squares would be 2.6 milliohms.
OK, vias have resistance, too. So we have here shown a 60 mil board. So the via is 60 mils long. And the cross sectional area is shaded. And you plug in the numbers in the formula, and you get the resistance as 0.7 milliohms. Well, this can handle from 1 to 3 amps. So you have to understand your circuit and how much current and pulse current and everything else, and then put appropriate vias where needed to handle the current.
Talk about AC parasitics-- self inductance of PWB traces. Now if you have a trace hanging out in free air, the inductance is a logarithmic formula. And you can see the first row of the chart that we have a 10 mil wide edge. And it comes out to 24 nanohenries per inch. Well, if we increase the width by a factor of 10, then the inductance only drops to 14 nanohenries. So increasing the width in free air does not help the inductance very much, reduce it.
PCB traces over ground planes-- well, if you put that trace over ground plane or return the current in it, or just return it on the same layer with a ground plane underneath, either way you lower the inductance. But in this example, the current is returning in the ground plane. So the formula becomes linear, and you can see height on the top and width on the bottom. So the shorter the height, the shorter the gap between the trace and the board, the lower the inductance, and the wider the width, the lower the inductance.
So over on the right hand side, the English units, you see the width is 0.1 inch, or 100 mils. And now if it's 10 mils off the board, it's 0.5 nanohenries per inch. And if it's 60 mils off the board, it's 3 nanohenries per inch. This is quite a bit less than the 14 we saw before.
OK, now we take a 3 inch piece of wire. How much is inductance in that 3 inch wire? Well, it depends how it's configured. And it really matters for circuit performance. We take that loop of wire, and if you look in the fixture there on the meter, we loop the wire and plug it into the LCR meter. And we come up with 79 nanohenries for this loop of wire.
Now we take a 60 mil board with the copper facing away on one side, facing away from the loop, and put it up there. And the inductance drops to 52. Then over to the right, we flip over the board where the copper is adjacent to the loop, and it's 37 nanohenries.
Now we take away the board, bottom left, and squish out the area in the loop for two parallel wires, and it's 32 nanohenries. Now we put that copper board with the copper away from it, drops to 31, flip over the copper board, it's 27. We twist the wires with no copper board, it's 26.
We put the copper board up with the copper away, and it doesn't help much there. And then we flip over the board, and it's 25. So you can see the configuration and how you place the trace with respect to a copper board the leakage inductance really changes. And we'll see later how that affects the layout.
Now we'll talk about capacitance. We've got a 10 mil thick board here. And we've got 10 mil traces at right angles on top and bottom. And the shaded area has a capacitance of 0.01 picofarads, which isn't much. But if you have a circuit where you've got multiple nodes tied together, and the traces and the pads and everything, they can add up to 2 picofarads or more. And if you have this [AUDIO OUT] high impedance node like the input to a feedback over a noisy area like a clock or a switch node or something like that, you'll inject that into the circuit.
Bypass capacitor layouts-- basically a capacitor is a low impedance device. So you want to minimize the leads or lead length or routing. So keep the leads short. Put the part right next to where it's going to decouple, and minimize the lead length. You can lower the impedance also by using different caps in parallel, which provide a broad low frequency range, broad low frequency impedance.
And then you can also parallel ceramic caps of different values to get a wide range of low impedances. This really takes an experienced layout person to understand all these concepts and where the currents flow.
OK, more about capacitors-- capacitors can become inductive. And you look over here, the model of a cap is on the left as a cap in series with inductive leads and series with resistance. So you go to the figure there, and you can see frequency on the x-axis, impedance on the y-axis.
So as you start over at the left, at 0.1 kilohertz, the impedance is high. And as you sweep the frequency, you'll see all the curves. There's four different curves for oscon, polymer, tantalum, and ceramic caps. We'll hit a valley. This is where the capacitance value and inductive value become equal. And that's the resonant frequency of the cap. And that's also the ESR of the cap. Any further increase in frequency will cause impedance to increase.
Now here's a sweep of an inductor. Inductors can be capacitive. Because you've got winding around a core, magnetic core. And so you've got the capacitance in between the windings in parallel with inductance, and then series resistance. So you look at the frequency chart. And as you sweep the frequency from 1 kilohertz up to about 200 kilohertz, impedance increases. And then that's where the resonant frequency [AUDIO OUT].
Look over on the right hand side, and it's a chip inductor. And you can see it doesn't even start to roll off after 100 megahertz. We typically use this for the high switching converters, high frequency switching converters that switch in the 1 to 3 megahertz range.
OK, this is a diagram of a buck converter. The input is on the left. The output is on the right. When you turn on the top FET, it applies VIN to the switching node. And you can see the path of the current loop through the inductor and back through the ground plane. So you need a good ground plane for a loop area, returning the pulse current from the input cap back to the source.
Now you look at the wave forms, you see ringing on it. So when you turn on the QH, the top FET, the input goes from ground up to VIN very, very quickly. At this point in time, you can see the leakage inductance drawn in the schematic. This charges up this leakage inductance. So once the switching node gets to VIN, the polarity of these inductors switch and continue to drive the current and drive it up to the peak. And then the current oscillates between the two FETs.
To avoid this ringing, you reduce the inductance. And by using integrated FETs, that really reduces the connection between the length of conduction and loop area between the FETs and reduces the inductance. And you can see in the picture to the right there's hardly no ringing at all.
OK, now the top FET turns off, and the bottom FET turns on. And the inductor output L flips polarity and becomes an energy source. You need a good ground plane to return all the currents. So you can see all the components connected to the ground plane. You need multiple vias there to allow the current to return on the ground plane. Now it's also helpful, in addition to that, to add ground plane on the layer where the components are to add to the low impedance ground.
OK, now you look. This is called the high frequency loop between the two FETs. Because the top FET turns on momentarily and has a pulse of current. Then it turns off, and then the bottom FET turns on and has a pulse of current. And these are out of phase. So it's like an AC signal. It's a very high frequency loop. So you want to keep this layout area as tight as possible.
Now you have other concerns, like electric coupling, dV/dt. This is the switch node going up and down. So you want to minimize this area, and especially keep it away from any high impedance circuits. But it is necessary to have it a certain size to carry the current. And also it's very important to cool the inductor in the IC with this trace. So you can't make it too small for thermal reasons.
Connect power components properly-- OK, this is power stage. This is one of the most important stages. Because it's where you're going to have all the high pulse currents and generate all the noise. So the first thing to do is to draw a schematic, and draw it such that how you're going to place the components on the PCB board. And so you can understand what topology it is by looking at it.
OK, so for example, the switching FETs Q2 and Q4 turn on and off out of phase. And when Q2 turns on, it gets its energy from C3. So the current in C3 jumps up basically to the output current, as shown previously.
And that charges Q4-- drained to source capacitance was at zero. And it jumps up to VIN. And so it charges that very fast, that rise time, 5 to 10 nanoseconds. And that current coming out of that cap is a noise current. And you want it to return back to the cap in as short of loop area as possible. Because that loop area is antenna, and you don't want it coupling to anything else.
OK, so you can consider two sided mounting, put the FETs on one side and caps on the other. Or if the area permits, you can put all the components on the same side. But you need to keep the loop area as small as possible by using ground planes and many vias to conduct the high pulse current.
So as we saw before, any inductance in the di/dt path results in ringing on the switch node. So you really want to minimize this. Any inductance in series with the output inductor isn't as important. Because it will be small compared to the output inductor. Proper design will eliminate snubbers.
Watch out for parasitic components. Now as I've just mentioned, the inductance in series with the output inductor is not that big a deal. But output parasitic inductance in series with a cap just makes the cap less effective. So you want to try to avoid this or minimize it. So use wide conductors and ground planes to minimize impedance.
Board capacitance-- board capacitance is a good thing in parallel with an input cap or output cap or something like that. But you don't want capacitance between a switching waveform and a high impedance circuit like the feedback loop. So you want to segregate the parts. Keep them away from each other. Keep the power stage in one area and the small signal stuff away from it.
Magnetic coupling-- a loop antenna, and you want to keep that loop very small so it doesn't transmit. And you want to keep other circuits away from it, even if you have a DC circuit where you think minimum loop areas isn't important. It may not be in a quiet environment. But if you put it next to a noisy circuit, it'll pick up noise and affect that.
We'll talk about grounds and grounding. There's many different ways to ground. One way in the past was daisy chain everything together. This has a lot of potential differences with cause issues, DC issues, offsets. And then you've got the high impedance at high frequency, greater than 10 kilohertz, which is an issue.
And a little bit better is a parallel or star node grounding, where you route everything to a central point. Well, this has less potential differences. But at high frequencies, these traces on one level still have a lot of inductance, as shown in our example on the LCR meter.
Multipoint ground-- this is the best low impedance overall. You use vias to tie it to the ground plane, which is very low impedance. Low impedance means less voltage drop for any noise that's in the circuit, any pulse currents. Remember to segregate your circuits. So if you have the power stage in one little area, and the pulse current coming out of it returning right away, and your small signals is in a different area of the board, there's no current flowing between them. So there's no IR drop between the two circuits.

Description

February 14, 2015

One of the most often overlooked design component in electronic systems is the PCB, which is as critical as any other component. Designers should use the same care with PCBs as with IC and FET switch designs. In this two-part lecture, we cover PCB electrical characteristics (AC and DC parasitics, grounds) and thermal characteristics (conduction and convection concepts).