SAN FRANCISCO--Relentless scaling advances will highlight memory papers at February's International Solid State Circuits Conference here, but it may be break-throughs in off-beat memory architectures that raise a few eyebrows.
ISSCC, scheduled for Feb. 17-21, 2013 at the Marriott, features a slightly smaller percentage of memory papers than usual for the five-day affair (9 percent of the total is down from 10 percent this year and 10 pecent in 2011), but the topics are no less fascinating.

Memory subcommittee chair Kevin Zhang of Intel notes in his memory overview, "We continue to see progressive scaling in embedded SRAM, DRAM, and floating-gate based Flash for very broad applications. However, due to the major scaling challenges in all mainstream memory technologies, we see a continued increase in the use of smart algorithms and error-correction techniques to compensate for increased device variability."
Revving ReRAM

One of the standout papers for the memory sessions comes from Toshiba and Sandisk, who will describe a 32Gb ReRAM (Resistive random-access memory) test chip developed in 24nm process, with a diode as the selection device.

The allure of alternative non-volatile memories has been high cycling capability and lower power per bit in read/write but their densities don't compete with NAND flash. ISSCC organizers noted that the highest density for a single chip published at last year’s ISSCC is 64Mb for ReRAM and 8Gb for PRAM, while NAND can reach up to 128Gb.

The Sandisk-Toshiba test chip is a metal-oxide-based ReRAM is based on 24nm technology node with a diode as the selection device and a 2-layered architecture.....

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