In this work the impact of the layout of the top metal of the integrated circuit (IC) and the most relevant process and material parameters of IC wafer fab and assembly fab on package stress induced damages to the ICs during temperature cycling is studied by means of thermo-mechanical simulations with experimental verifications. Besides die size, the materials for passivation, silicon thickness, molding compound properties, the cohesion between the molding compound and the die surface, and lead frame yield stress, all are found to significantly influence the risk of damages or failures on the IC surface. The results suggest a more complete package stress relief design rule, pointing to a systematic approach to eliminate or suppress the package stress induced damages to the IC and consequently a possibly more efficient use of the silicon area in IC design.