Xilinx preps 20-nm IC tape-out

LONDON – Xilinx Inc. has announced that it will tape-out its first chip designed for manufacture in 20-nm CMOS in the second quarter of 2013 and will provide design support for its next generation of "all-programmable devices" made using 20-nm CMOS from March.

The 20-nm portfolio will address a wide range of systems and with embedded CPU cores provides a field-programmable alternative to ASICs and ASSPs. All-programmable implies that the devices include field-programmable hardware and software-programmable processors and can include a mix of FPGA, CPU cores, DSP cores, memory, often on multiple die in a multichip package. The portfolio is expected to address applications in wired and wireless networks, data centers, vision-based systems, and other high performance applications.

Xilinx's tape-out in 2Q13 is aimed for manufacture by Taiwan Semiconductor Manufacturing Co. Ltd. using its 20SoC manufacturing process, which is expected to ramp into volume production in the second half of 2013.

Xilinx said it would be preparing device samples for strategic customers in 2013 and is engaging with its first ten customers on architecture evaluations and implementation details.

"Xilinx went all in to move a generation ahead at 28-nm, and is doing the same at 20-nm to stay a generation ahead," said Victor Peng, senior vice president at Xilinx. The Vivado EDA tools will support initial 20-nm devices in March 2013, the company said.

Intel started double patterning a lot earlier. Due to pitch too small, their 45 nm diffusion and gate contacts had to be separately done with dry 193 nm, for example. This had to continue at 32 nm with immersion of course.

Well I actually wasn't aware NAND flash was already produced at 20nm. Amazing how far they pushed DUV immersion! Can EUV ever catch up???? EUV sounds DOA.
Xilinx can't use double patterning for their designs. So they are surely stuck at the 32nm node for ever.

Memory companies are doing volume manufacturing at 20nm. NAND flash from all major vendors is available at or near 20nm half pitch, achieved with now standard double patterning techniques. Are you referring to Logic ICs exclusively?

I'm really curious how they plan 20nm with DUV Immersion Lithography. Double patterning can provided limited patterns at the 28nm HP. Are they implying plans for triple patterning??
My suspicion is that there is a lot of bluffing going on at the moment.