Traditional transistor scaling drive the semiconductor industry through the 1990s, but led to the era of innovation driven transistor scaling. Strained silicon, high-k plus metal gate transistors, and fin based transistors were some of the key innovations in the last several process technology generations. This presentation will explore both the transistor scaling benefits from these innovations as well as the reliability implications covering the 90nm to 14nm timeframe.

Biography: Kaizad Mistry is vice president of the Technology and Manufacturing Group, and is currently responsible for directing process development activities for Intel's 10nm logic technology. Most recently, he managed the development of Intel's 22nm logic technology, the world's first to feature 3-D Tri-Gate transistors. Previously, he managed the development of Intel's 45nm logic technology, the world's first to feature high-k plus metal gate transistors. He was the device group manager for Intel's 90nm logic technology and played a leadership role in the world's first implementation of strained silicon transistors. Prior to joining Intel in 1998, Mistry managed the device physics & reliability group for the semiconductor technology division at Digital Equipment Corp. Mistry is an IEEE fellow, has authored or co-authored more than 70 journal and conference papers and holds 20 patents. In 2006, he was General Chair of the IEEE International Electron Devices Meeting.

This keynote presentation will explore the genesis, architecture and construction of the Hybrid Memory Cube. The presentation will open with a discussion on how both technical and market forces led to the creation of HMC. This will be followed by a dive into the Gen 2 HMC design—detailing the design goals for the device and how manufacturability was a priority from day one. 3D integration is pivotal technology for HMC. As such, it will be explored in the context of key enablers and ongoing challenges. Finally, the presentation will discuss how HMC encompasses a variety of RAS features to improve manufacturability and to ensure long term device reliability.

Biography: Brent Keeth is a senior fellow in and has been with Micron Technology since 1992, where he directs ultrahigh performance memory design and technology development programs including the Hybrid Memory Cube (HMC). Mr. Keeth earned BSEE (1982) and MSEE (1996) degrees from the University of Idaho and is an inventor on 257 U.S. patents and 184 foreign patents to date. He also coauthored textbooks DRAM Circuit Design—Fundamental and High-Speed Topics and DRAM Circuit Design—A Tutorial, both published by Wiley-IEEE Press in 2008 and 2001 respectively. Brent has reviewed papers for publication in the Journal of Solid-State Circuits and served numerous times on technical program committees for both the International Solid State Circuits Conference and the Symposium on VLSI Circuits.

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