On Fri, 28 Dec 2007, Benjamin Herrenschmidt wrote:> > I have embedded boards where proper CRS operations is critical since the> kernel brings the PCIe link up itself, and thus is likely to hit devices> still in the middle of CRS.

.. but that's perfectly fine. A PCI-E bridge will certainly retry it in hardware (or it isn't a PCI-E bridge!).

The CRS bit in question is purely the *software*visible* bit - ie whether the OS gets told about the delay or not. As long as the OS then just retries the same device, enabling CRS SV is pointless.

So I'm going to disable that thing. If there is some _other_ PCI-E bridge that is simply buggy, and cannot handle the hw retry itself or is just otherwise dodgy, we can have a white-list for cases where it really needs to be done, but the current code is just bogus.