What are the advantages of using component modeling using VITAL (style used by FMF) for FIFO devices?

1) The board designer can specify interconnect path delays (tipd) with VITAL. On IDT's current models we do not define "tipd".

2) The timing file is separated from the actual VHDL model, thus allowing board designers to manipulate timing based on their simulation needs. This way they can use two instances with different speed grades. On our existing models we do have timing, but it is embedded in the model. Every time the timing is changed in the model, the model must be recompiled. Also, we would rather not encourage the average user to modify the models.

3) The above separation of timing from the model allows the model to be used for multiple timings within the same design. It also allows the model to be used for future designs by just changing the timing file.

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