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Abstract

Described is a hardware implementation to provide a concurrent/real time Arbitration Utilization Circuit (AUC) for tracking the utilization of an expansion bus over a period of time, as used in Personal Computers (PCs).

Country

United States

Language

English (United States)

This text was extracted from an ASCII text file.

This is the abbreviated version, containing approximately
45% of the total text.

Concurrent/Real Time Arbitration Utilization Circuit

Described is
a hardware implementation to provide a
concurrent/real time Arbitration Utilization Circuit (AUC) for
tracking the utilization of an expansion bus over a period of time,
as used in Personal Computers (PCs).

The AUC is
designed to provide a running count for each bus
master level on the Micro Channel* (MC) bus, or other expansion
buses, and is used to determine the bandwidth of each bus master
level over a period of time. The AUC
provides information for
analyzing performance and to enhance the tuning capability of a
server. It may be used as a diagnostic,
or as a problem
determination aid. If a bus master is
not performing to
specification, the information gathered can be used to diagnose a
problem. For example, thirty-two bit bus
masters that are running
eight bit cycles, or streaming bus masters that are not streaming,
would cause bus masters to be on the bus longer than it should. This
anomaly can be captured by the AUC.

Server PCs
with the MC, or other expansion buses,
increasingly
use bus master type of adapters because it reduces the load placed on
the main system processor. Each bus
master performs its own
processing, thereby providing an increase in balanced server
operations. With the bus masters
operating on their own, server
tuning has become quite difficult. As a
result, a solution was
needed to show which bus masters are the most busy and which bus
masters may be using much of the channel bus bandwidth.

The concept
described herein uses the AUC to provide a means,
through the MC or other expansion buses, to indicate which bus
masters are the busiest and which may be using too much of the
channel bus bandwidth. It performs this
task by watching for a bus
master to gain control of the MC. At
that time, a counter begins
incrementing and keeps incrementing for as long as the bus master
keeps control. As soon as the bus master
releases the bus, the
counter for that bus master will stop.
The processor that controls
the AUC is interrupted when a counter for one of the sixteen levels
reaches its maximum so as to increment its software counters located
in memory. So as to meet the
concurrent/real time requirement, the
processor and its memory must reside with the AUC. This ensures that
the system's Central Processing Unit (CPU) will not be taxed with the
overhead of maintaining the counters.

From the
counters, the average bandwidth for each level and
other information can be derived to produce a MC utilization graph,
or analysis, and provide tuning capabilities to a server. This
operation can also detect which bus masters on the MC have stopped
functioning.

Figs. 1 and 2
show the circuit schematics for the AUC.
Fig. 1
shows the 4 bit decodes and the sixteen counters. Fig. 2 shows the
gate and output circuity of the AUC. A
processor is used to control
the AUC and to main...