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AXI4 Überblick ● AXI4—for high-performance memory-mapped requirements. ● AXI4-Lite—for simple, low-throughput memory-mapped communication (for example, to and from control and status registers). ● AXI4-Stream—for high-speed streaming data. "Low power is also important to ARM, and the CoreLink Network Interconnect is no exception. The RTL has been optimized to make extensive use of automated clock gate insertion by synthesis tools. Implementation trials have shown that as many as 95% of the flops are clock gated when idle." http://www.arm.com/products/system-ip/interconnect/axi/index.php

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