The Week In Review: Design

M&AImagination will sell its MIPS business to Tallwood, a California-based venture capital firm, for $65m in cash. The sale is expected to close in October. The rest of Imagination is slated to be sold to Canyon Bridge for £550 million in cash (~$740 million), a deal dependent on the MIPS sale. The Chinese-backed investment firm has featured recently in the news for its attempted purchase of Lattice, a deal which was blocked by the U.S. government. Earlier this year, Imagination announced Apple would no longer license the company’s GPUs, leading to a plunge in Imagination’s stock price.

Numbers
EDA and IP revenues increased 9.8% to $2.21 billion in Q2, up from $2.01 billion in the same period in 2016, according to the ESD Alliance. The strongest Q2 in five years included IP revenue that grew 18.8% to $793 million, while CAE, the biggest category, grew 2.2% to $677 million. PCB/multi-chip modules revenue was $195.4 million for the quarter, a 16.4% increase over Q2 2016. Hiring grew as well, with tracked companies employing 38,265 people, 9.4% more compared to Q2 2016, and up 2.8% compared to Q1 2017.

FPGA startup Efinix completed a $9.5 million funding round with support of Xilinx and Hong Kong X Technology Fund. Founded in 2012, the company’s programmable architecture is based on the eXchangeable Logic and Routing (XLR) cell, which can function as either a LUT-based logic cell or a routing switch encoded with a scalable, flexible routing structure, which the company says can provide up to 4X area efficiency and a 2X power advantage over traditional FPGAs.

DealsKilopassinked a deal with Nuvoton Technology, which will use Kilopass’ OTP NVM IP to store calibration values, keys for security algorithms, and specific configuration data in microcontroller designs targeting desktop and mobile computers.

PixelworkslicensedArterisIP’s FlexNoC interconnect IP for use as the backbone interconnect of its advanced video processing SoCs for projectors and other video displays. Pixelworks is a longtime customer of ArterisIP.

Mentor’s Precision Synthesis product now supportsSilicon Mobility’s OLEA Field-Programmable Control Unit, targeted at automotive applications. Silicon Mobility customers will receive licenses to use a version of the FPGA synthesis tool for mapping RTL to the programmable logic fabric.

Tool provider startup BaumimplementedVerific’s SystemVerilog and Verilog parsers function as the front end to its power analysis and modeling solution for SoCs.

Standards
The public review period for the Portable Stimulus Specification has been extended to Oct. 30. The specification defines a standard mechanism for the specification of verification intent and behaviors that would be reusable across target platforms and allow for the automation of test generation through a new Domain Specific language and equivalent C++ Class Library. The Early Adopter release is available from Accellera.

The USB 3.2 specification has been published. The new specification allows new USB 3.2 hosts and devices to be designed as multi-lane solutions, allowing for up to two lanes of 5 Gbps or two lanes of 10 Gbps operation with existing Type-C cables.

CertificationsSynopsys’s design platform, including digital, custom and SPICE tools, has been certified for Samsung Foundry’s 28FDS (FD-SOI) process technology. A Process Design Kit (PDK) and reference flow are also available.

DVCon Europe: Oct. 16-17 in Munich, Germany. The annual conference for design and verification features keynotes by Bosch’s Horst Symanzik on the design challenges of consumer MEMS products, plus a discussion of virtual prototyping of automotive electronics by Audi’s Berthold Hellenthal.

Arm TechCon: Oct. 24-26 in Santa Clara, CA. The Arm ecosystem-focused conference features a number of keynotes from Arm on subjects from the value of IoT data to state-of-the-art silicon process technologies. Invited speakers Stacey Higginbotham, Mary Aiken, and Jessica Barker will discuss the key challenges facing IoT and why a more human-centered approach is needed when designing security.

DAC: The call for 2018 contributions is now open for panels, research papers, sessions, and presentations covering EDA, embedded, design, and IP, plus focuses on AI, IoT, automotive, and security. The first submission deadline is November 14, 2017 for paper abstracts. The conference will be held June 24 – 28, 2018 in San Francisco, CA.