The CEVA-X2 is based on a VLIW/SIMD architecture with a 10-stage pipeline operating at 2GHz in typical conditions of a 16nm process.

Other key features include:

4.5 CoreMark/MHz score,

quad 16×16 MAC operations per cycle,

dual 32×32 MAC operations per cycle,

64-bit SIMD fixed-point operations,

up to two IEEE single-precision floating-point units operating in parallel.

The processor includes two Scalar Processing Units (SPUs), which support 8/16/32/64-bit data types for ALU operations. It supports both static branch prediction and optional dynamic branch prediction, and offers both supervisor and user modes.

At a system level, the CEVA-X2 includes a 2-way or 4-way set-associative data cache with write-through and write-back policies, as well as hardware and software pre-fetch capabilities.

Webinar: Voice Interfaces of the Future

Tech That’s Turning Sci-Fi into Reality

This webinar covers the current state and future possibilities of voice interfaces. It surveys the technologies that have enabled current proliferation of voice interfaces but also takes a critical look at the faults and drawbacks of current implementations. Finally, it explores the existing, emerging and future technologies that will eventually generate a revolution in the way we interact with machines.