DesignWare Technical Bulletin

IntroductionAs applications such as near-field communications (NFC), radio-frequency identification (RFID), and advanced sensors require more embedded non-volatile memory (NVM), designers are driven to incorporate advanced NVM technology to meet system demands. This article will highlight the key power, area, and reliability requirements of these markets and show how the requirements continue to change over time. It will also cover how Synopsys has leveraged patented device and design-level innovations to reduce NVM IP area and power by over 50% over previous generations, and the impact of these innovations on system-level design and performance.

Importance of Endurance in Sensor SystemsReal-time data logging is now more prevalent than ever. From measuring your blood pressure to real-time stress on a steel bridge, sensor networks are quickly driving a new age of data collection, aggregation and analysis, all requiring higher endurance in multiple-time programmable (MTP) NVM.

As shown in Figure 1, sensor system’s requirements depend on how much EEPROM is needed and how often the data needs to be written. The answers not only affect area and power (e.g., a large EEPROM generally takes more power) but also drive the endurance and retention requirements.

Figure 1: Endurance/retention tradeoffs that also drive size and power requirements of MTP NVM

To minimize the endurance challenges, designers must use IP that starts with the fundamentals and then innovates with custom devices, leading edge tools and state-of-the-art design. Understanding MTP NVM requires an expertise in how charge is transferred during program and erase cycles. This expertise is used to optimize performance over different manufacturing materials and layout through monitoring voltage, current and manufacturing level stressors during the development process, as shown in Figure 2.

Figure 2: Developing MTP/NVM requires expertise in multiple areas

Reducing Power Consumption and Area UseWhen most people think about power, they focus on battery life, but power decisions also affect area and dynamic performance. Lowering power consumption increases system performance by allowing battery or RF-powered MTP NVM devices to function for a longer time and from further away or through using smaller antennas. Reducing power can also lower system area, enabling lower cost and a wider range of packaging options. There is often a link between power and area and this combined reduction enables new applications such as RFID and Internet-of-Things (IoT).

When power is a key concern, starting with a technology evaluation can be the right approach followed by balancing how much NVM is needed in the system. As an example, higher density memories will typically require higher peak and average currents while NVM programming mechanisms (e-injection, blown gate, FN tunneling, etc) differ in currents as well. Figure 3 illustrates some fundamental differences between two popular programming mechanisms that can have an effect on supporting circuits and total area of the NVM.

Figure 3: Different NVM technologies have different power requirements

In addition, there are also system-level concerns where the choice of NVM technology and density may negatively impact other components. Applications that deal with high impedance supplies must take care that peak currents don’t dynamically push their system VDD outside the operating range of other on-chip components. At the system level, physically larger voltage regulators and batteries can be used to counteract high currents, but may have a negative impact on product size, cost and performance.

This trust didn’t happen by accident. It was built through product developers carefully evaluating application needs. These needs were then combined with the track record and evolution of NVM suppliers. When incorporating NVM IP, designers should understand their expectations for:

Data retention and endurance cycles

Manufacturability and yield

Performance, both now and in the future

Studying standard specs and data can be a straightforward comparison between NVM technologies, but designers must also consider additional factors when selecting an NVM IP supplier:

Synopsys Innovation with DesignWare MTP NVM IPSynopsys’ 180 nm MTP NVM technology was first productized in 2003. Since then, Synopsys NVM IP has shipped in over 3 billion units. As part of its drive for technology leadership, Synopsys is focused on area reduction, which results in cost savings for designers. Figure 5 highlights Synopsys’ track record of continued area reduction in the 180 nm node for 1kbit MTP NVM.

This area reduction has also been combined with reduced metallization and power reduction, as shown in Figure 6. Synopsys closely collaborated with its customers to develop MTP NVM IP that meets their area, power, and performance requirements.1. Smaller area → Lower capacitance/ Lower power

Innovative bitcell and HV architecture minimize area and capacitive loading