Abstract: Ensuring the correctness of integrated circuits (ICs) is essential for ensuring correctness, safety and security of electronic systems we rely on. As ICs continue to grow in size and complexity, the cost and effort required to validate them are growing at an unsustainable rate. To make matters worse, difficult bugs escape into post-silicon and even production systems.

We present the Quick Error Detection (QED) technique which targets post-silicon validation and debug challenges. QED drastically reduces error detection latency, the time elapsed between the occurrence of an error caused by a bug and its manifestation as an observable failure. Inspired by QED, we also present Symbolic QED which combines QED principles with a formal engine to detect and localize bugs during both pre- and post-silicon validation.

Experimental results collected from several commercial designs as well as hardware platforms demonstrate the effectiveness and practicality of QED and Symbolic QED:

Results from multiple commercial hardware platforms show that QED improves error detection latencies of post-silicon validation tests by up to 9 orders of magnitude, from billions of clock cycles to very few clock cycles. QED also improves bug coverage during post-silicon validation 4-fold.

With drastically improved error detection latencies, QED (together with a formal engine) automatically localizes logic and electrical bugs in billion transistor-scale designs during post-silicon debug. For example, we can now automatically narrow the locations of electrical bugs to a handful of candidate flip-flops (18 flip-flops on average for a design with ~ 1 Million flip-flops) in only a few hours (~ 9 hours on average). In contrast, traditional post-silicon debug techniques might take weeks (or even months) of manual work.

QED and Symbolic QED are effective for logic design bugs and electrical bugs inside processor cores, hardware accelerators, and uncore components such as cache controllers, memory controllers and interconnection networks. QED-based validation and debug techniques have been successfully used in industry.

Speaker Bio
Subhasish Mitra is Professor of Electrical Engineering and of Computer Science at Stanford University, where he directs the Stanford Robust Systems Group and co-leads the Computation focus area of the Stanford SystemX Alliance. He is also a faculty member of the Stanford Neurosciences Institute. Before joining the Stanford faculty, he was a Principal Engineer at Intel Corporation.
Prof. Mitra's research interests range broadly across robust computing, nanosystems, VLSI design, CAD, validation and test, and neurosciences. He, jointly with his students and collaborators, demonstrated the first carbon nanotube computer and the first 3D Nanosystem with computation immersed in memory. These demonstrations received wide-spread recognitions (cover of NATURE, research highlight to the United States Congress by the National Science Foundation, highlight as "important, scientific breakthrough" by the BBC, Economist, EE Times, IEEE Spectrum, MIT Technology Review, National Public Radio, New York Times, Scientific American, Time, Wall Street Journal, Washington Post and numerous others worldwide). His earlier work on X-Compact test compression has been key to cost-effective manufacturing and high-quality testing of a vast majority of electronic systems. X-Compact and its derivatives have been implemented in widely-used commercial Electronic Design Automation tools.
Prof. Mitra's honors include the ACM SIGDA/IEEE CEDA Richard Newton Technical Impact Award in Electronic Design Automation (a test of time honor), the Semiconductor Research Corporation's Technical Excellence Award, the Intel Achievement Award (Intel’s highest corporate honor), and the Presidential Early Career Award for Scientists and Engineers from the White House (the highest United States honor for early-career outstanding scientists and engineers). He and his students published several award-winning papers at major venues: IEEE/ACM Design Automation Conference, IEEE International Solid-State Circuits Conference, IEEE International Test Conference, IEEE Transactions on CAD, IEEE VLSI Test Symposium, and the Symposium on VLSI Technology. At Stanford, he has been honored several times by graduating seniors "for being important to them during their time at Stanford."
Prof. Mitra served on the Defense Advanced Research Projects Agency's (DARPA) Information Science and Technology Board as an invited member. He is a Fellow of the ACM and the IEEE.