In the past, there was only one load-with-reservation instruction,lwarx, and if a program attempted a lwarx on a misaligned address, itwould take an alignment interrupt and the kernel handler would emulateit as though it was lwzx, which was not really correct, but benign sinceit is loading the right amount of data, and the lwarx should be pairedwith a stwcx. to the same address, which would also cause an alignmentinterrupt which would result in a SIGBUS being delivered to the process.

We now have 5 different sizes of load-with-reservation instruction. Ofthose, lharx and ldarx cause an immediate SIGBUS by luck since theirentries in aligninfo[] overlap instructions which were not fixed up, butlqarx overlaps with lhz and will be emulated as such. lbarx can nevergenerate an alignment interrupt since it only operates on 1 byte.

To straighten this out and fix the lqarx case, this adds code to detectthe l[hwdq]arx instructions and return without fixing them up, resultingin a SIGBUS being delivered to the process.