82m9axev150.pdf

HT82M9AEE/HT82M9AAE
USB Mouse Encoder 8-Bit MCU with EEPROM
Technical Document
· Tools Information
· FAQs
· Application Note
Features
· Flexible total solution for applications that combine
· 128´8 data EEPROM
PS/2 and low-speed USB interface, such as mice,
joysticks, and many others
· 6MHz/12MHz internal CPU clock
· 4-level stacks
· USB Specification Compliance
· Two 8-bit indirect addressing registers
- Conforms to USB specification V2.0
- Conforms to USB HID specification V2.0
· One 16-bit programmable timer counter with
overflow interrupt (shared with PA7, vector 0CH)
· Supports 1 low-speed USB control endpoint and
· One USB interrupt input (vector 04H)
2 interrupt endpoint
· HALT function and wake-up feature reduce power
· Each endpoint has 8 bytes FIFO
consumption
· Integrated USB transceiver
· PA0~PA7, PB4/SDA and PB7/SCL support wake-up
· 3.3V regulator output
function
· External 6MHz or 12MHz ceramic resonator or crystal
· Internal Power-On reset (POR)
· 8-bit RISC microcontroller, with 4K´15 program
· Watchdog Timer (WDT)
memory (000H~FFFH)
· 16 I/O ports
· 224 bytes RAM (20H~FFH)
· 20/24-pin SSOP package
General Description
The USB MCU OTP body is suitable for USB mouse
and USB joystick devices. It consists of a Holtek high
performance 8-bit MCU core for control unit, built-in
USB SIE, 4K´15 ROM and 224 bytes data RAM.
There are two dice in the HT82M9AEE/HT82M9AAE
package: one is the HT82M9AE/HT82M9AA MCU, the
other is a 128´8 bits EEPROM used for data memory
purpose. The two dice are wrie-bonded to from
HT82M9AEE/HT82M9AAE.
The mask version HT82M9AAE is fully pin and functionally compatible with the OTP version HT82M9AEE device.
Rev. 1.50
1
December 22, 2008
HT82M9AEE/HT82M9AAE
Block Diagram
U S B D + /C L K
U S B D -/D A T A
V 3 3 O
U S B 1 .1
P S 2
B P
In te rru p t
C ir c u it
S T A C K
P ro g ra m
R O M
P ro g ra m
C o u n te r
M
T M R L
T M R H
U
fS
/4
Y S
P A 7 /T M R
X
T M R C
IN T C
E N /D IS
W D T S
In s tr u c tio n
R e g is te r
M
M P
U
D a ta
M e m o ry
X
P O R T A
P A C
P B C
T im in g
G e n e ra to r
O S C 2
O S
R
V
V
S T A T U S
A L U
P O R T B
P B
P B
P B
P B
P B
S h ifte r
C 1
E S
D D
S S
U
S Y S C L K /4
W D T O S C
X
P A 0 ~ P A 6
P A 7 /T M R
P A
M U X
In s tr u c tio n
D e c o d e r
M
W D T
W D T P r e s c a le r
0 ~
4 /S
5 ~
7 /S
P B
D
P B
C
3
A
L
6
A C C
Pin Assignment
1
2 4
P B 1
2
2 3
P B 0
V S S
1
2 0
O S C I
V S S
3
2 2
O S C I
V 3 3 O
2
1 9
O S C O
V 3 3 O
4
2 1
O S C O
U S B D + /C L K
3
1 8
V D D
U S B D + /C L K
5
2 0
V D D
U S B D -/D A T A
4
1 7
P A 7
U S B D -/D A T A
6
1 9
P A 7
R E S
5
1 6
P A 6
R E S
7
1 8
P A 6
P A 0
6
1 5
P A 5
P A 0
8
1 7
P A 5
P A 1
7
1 4
P A 4
P A 1
9
1 6
P A 4
P B 2
8
1 3
P A 3
P B 2
1 0
1 5
P A 3
P B 3
9
1 2
P A 2
P B 3
1 1
1 4
P A 2
1 0
1 1
P B 7 /S C L
P B 4 /S D A
1 2
1 3
P B 7 /S C L
P B 4 /S D A
H T 8 2 M 9 A E E /H T 8 2 M 9 A A E
2 0 S S O P -A
Rev. 1.50
P B 5
P B 6
H T 8 2 M 9 A E E /H T 8 2 M 9 A A E
2 4 S S O P -A
2
December 22, 2008
HT82M9AEE/HT82M9AAE
Pin Description
Pin Name
I/O
ROM Code
Option
Description
PA0~PA7
Bidirectional 8-bit input/output port. Each bit can be configured as a
wake-up input by ROM code option. The input or output mode is controlled by PAC (PA control register).
Pull-high
Pull-high resistor options: PA0~PA7
Pull-low
I/O
Pull-low resistor options: PA0~PA3
Wake-up
CMOS/NMOS/PMOS CMOS/NMOS/PMOS options: PA0~PA7
Falling edge wake-up options: PA0~PA1, PA4~PA7
Rising and falling edge wake-up options: PA2~PA3
PB0~PB3
PB4/SDA
PB5~PB6
PB7/SCL
I/O
Pull-high
Pull-low
Wake-up
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with pull-high resistor (determined
by pull-high options).
PB4 is wire-bonded with the SDA pad of the Data EEPROM.
PB7 is wire-bonded with the SCL pad of the Data EEPROM.
Pull-high resistor options: PB0~PB7
Pull-low resistor for options: PB2, PB3
Falling edge wake-up options: PB4/SDA, PB7/SCL
VSS
¾
¾
Negative power supply, ground
RES
I
¾
Schmitt trigger reset input. Active low.
VDD
¾
¾
Positive power supply
V33O
O
¾
3.3V regulator output
USBD+/CLK
I/O
¾
USBD+ or PS2 CLK I/O line
USB or PS2 function is controlled by software control register
USBD-/DATA
I/O
¾
USBD- or PS2 DATA I/O line
USB or PS2 function is controlled by software control register
OSCI
OSCO
I
O
¾
OSCI, OSCO are connected to a 6MHz or 12MHz crystal/resonator (determined by software instructions) for the internal system clock.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...............................0°C to 70°C
IOL Total ..............................................................150mA
IOH Total............................................................-100mA
Total Power Dissipation .....................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.50
3
December 22, 2008
HT82M9AEE/HT82M9AAE
D.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
¾
Min.
Typ.
Max.
Unit
3.3
¾
5.5
V
VDD
Operating Voltage
¾
IDD
Operating Current (6MHz Crystal)
5V
No load, fSYS=6MHz
¾
7
9
mA
No load, system HALT,
USB suspend
¾
¾
500
mA
¾
¾
300
mA
¾
¾
30
mA
¾
¾
20
mA
1.4
V
ISTB1
Standby Current (WDT Enabled)
5V
ISTB2
Standby Current (WDT Disabled)
5V
ISTB3
Standby Current (WDT Enabled)
5V
ISTB4
Standby Current (WDT Disabled)
5V
No load, system HALT,
input/output mode,
set SUSPEND2 [1CH].4
VIL1
Input Low Voltage for I/O Ports
5V
¾
0
1.2
VIH1
Input High Voltage for I/O Ports
5V
¾
2.0
¾
5
V
VIL2
Input Low Voltage (RES)
5V
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
5V
¾
0.9VDD
¾
VDD
V
IOL1
Output Sink Current for PA4~PA7,
PB0~PB1, PB4~PB7
5V
VOL=0.4V
2
4
¾
mA
IOH1
Output Source Current for PA4~PA7,
PB0~PB1, PB4~PB7
5V
VOH=3.4V
-2.5
-4
¾
mA
IOL2
Output Sink Current for PA0~PA3,
PB2~PB3
5V
VOL=0.4V
10
15
¾
mA
IOH2
Output Source Current for PA0~PA3,
PB2~PB3
5V
VOH=3.4V
8
12
¾
mA
RPD
Pull-down Resistance for PA0~PA3,
PB2~PB3
5V
¾
10
30
50
kW
RPH1
Pull-high Resistance for DATA(*)
¾
¾
1.3
1.5
2.0
kW
RPH2
Pull-high Resistance for CLK
¾
¾
2.0
4.7
6.0
kW
RPH3
Pull-high Resistance for PA0~PA7,
PB0~PB7
¾
¾
30
50
70
kW
VLVR
Low Voltage Reset
5V
¾
2.0
2.4
3
V
Note: ²*² The DATA pull-high must be implemented by the external 1.5kW
A.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
fSYS
System Clock (Crystal OSC)
5V
¾
6
¾
12
MHz
fRCSYS
RC Clock with 8-bit Prescaler
Register
5V
¾
0
32
¾
kHz
tWDT
Watchdog Time-out Period
(System Clock)
¾
Without WDT prescaler
1024
¾
¾
tRCSYS
tRF
USBD+, USBD- Rising & falling Time
¾
¾
75
¾
300
ns
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
¾
1024
¾
tSYS
tOSC
Crystal Setup
¾
¾
5
10
ms
Wake-up from HALT
¾
Note: Power-on period=tWDT+tSST+tOSC
WDT Time-out in normal mode=1/fRCSYS´256´WDTS+tWDT
WDT Time-out in HALT mode=1/fRCSYS´256´WDTS+tSST+tOSC
Rev. 1.50
4
December 22, 2008
HT82M9AEE/HT82M9AAE
EEPROM A.C. Characteristics
Symbol
Ta=25°C
Parameter
Remark
Standard Mode*
VCC=5V±10%
Min.
Max.
Min.
Max.
Unit
fSK
Clock Frequency
¾
¾
100
¾
400
kHz
tHIGH
Clock High Time
¾
4000
¾
600
¾
ns
tLOW
Clock Low Time
¾
4700
¾
1200
¾
ns
tr
SDA and SCL Rise Time
Note
¾
1000
¾
300
ns
tf
SDA and SCL Fall Time
Note
¾
300
¾
300
ns
tHD:STA
START Condition Hold Time
After this period the first
clock pulse is generated
4000
¾
600
¾
ns
tSU:STA
START Condition Setup Time
Only relevant for repeated
START condition
4000
¾
600
¾
ns
tHD:DAT
Data Input Hold Time
¾
0
¾
0
¾
ns
tSU:DAT
Data Input Setup Time
¾
200
¾
100
¾
ns
tSU:STO
STOP Condition Setup Time
¾
4000
¾
600
¾
ns
tAA
Output Valid from Clock
¾
¾
3500
¾
900
ns
4700
¾
1200
¾
ns
¾
100
¾
50
ns
¾
5
¾
5
ms
tBUF
Bus Free Time
Time in which the bus must
be free before a new transmission can start
tSP
Input Filter Time Constant
(SDA and SCL Pins)
Noise suppression time
tWR
Write Cycle Time
¾
Note: These parameters are periodically sampled but not 100% tested
* The standard mode means VCC=2.2V to 5.5V
For relative timing, refer to timing diagrams
Rev. 1.50
5
December 22, 2008
HT82M9AEE/HT82M9AAE
Functional Description
Execution Flow
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.
The system clock for the microcontroller is derived from
either 6MHz or 12MHz crystal oscillator, which used a
frequency that is determined by the SCLKSEL bit of the
SCC Register. The default system frequency is 12MHz.
The system clock is internally divided into four nonoverlapping clocks. One instruction cycle consists of
four system clock cycles.
When executing a jump instruction, conditional skip execution, loading to the PCL register, performing a subroutine call or return from subroutine, initial reset,
internal interrupt, external interrupt or return from interrupts, the PC manipulates the program transfer by loading the address corresponding to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to be effectively executed in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within the current program ROM page.
Program Counter - PC
The program counter (PC) controls the sequence in
which the instructions stored in the program ROM are
executed and its contents specify a full range of program memory.
S y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
When a control transfer takes place, an additional
dummy cycle is required.
T 2
T 3
T 4
T 1
T 2
T 3
T 4
O S C 2 ( R C o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
USB Interrupt
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter Overflow
0
0
0
0
0
0
0
0
1
1
0
0
Skip
Program Counter+2
Loading PCL
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: *11~*0: Program counter bits
S11~S0: Stack register bits
#11~#0: Instruction code bits
Rev. 1.50
@[email protected]: PCL bits
6
December 22, 2008
HT82M9AEE/HT82M9AAE
ROM data by two table read instructions: ²TABRDC²
and ²TABRDL², transfer the contents of the
lower-order byte to the specified data memory, and
the higher-order byte to TBLH (08H).
The three methods are shown as follows:
Program Memory - ROM
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
4096´15 bits, addressed by the program counter and table pointer.
¨
The instructions ²TABRDC [m]² (the current page,
one page=256words), where the table locations is
defined by TBLP (07H) in the current page. And the
ROM code option TBHP is disabled (default).
¨
The instructions ²TABRDC [m]², where the table locations is defined by registers TBLP (07H) and
TBHP (01FH). And the ROM code option TBHP is
enabled.
¨
The instructions ²TABRDL [m]², where the table locations is defined by Registers TBLP (07H) in the
last page (0F00H~0FFFH).
Certain locations in the program memory are reserved
for special usage:
· Location 000H
This area is reserved for program initialization. After a
chip reset, the program always begins execution at location 000H.
· Location 004H
This area is reserved for the USB interrupt service
program. If the USB interrupt is activated, the interrupt
is enabled and the stack is not full, the program begins
execution at location 004H.
Only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are
transferred to the lower portion of TBLH, and the remaining 1-bit words are read as ²0². The Table
Higher-order byte register (TBLH) is read only. The table pointer (TBLP, TBHP) is a read/write register (07H,
1FH), which indicates the table location. Before accessing the table, the location must be placed in the
TBLP and TBHP (If the OTP option TBHP is disabled,
the value in TBHP has no effect). The TBLH is read
only and cannot be restored. If the main routine and
the ISR (Interrupt Service Routine) both employ the
table read instruction, the contents of the TBLH in the
main routine are likely to be changed by the table read
instruction used in the ISR. Errors can occur. In other
words, using the table read instruction in the main routine and the ISR simultaneously should be avoided.
However, if the table read instruction has to be applied
in both the main routine and the ISR, the interrupt
should be disabled prior to the table read instruction. It
will not be enabled until the TBLH has been backed
up. All table related instructions require two cycles to
complete the operation. These areas may function as
normal program memory depending on the requirements.
Once TBHP is enabled, the instruction ²TABRDC [m]²
reads the ROM data as defined by TBLP and TBHP
value. Otherwise, the ROM code option TBHP is disabled, the instruction ²TABRDC [m]² reads the ROM
data as defined by TBLP and the current program
counter bits.
· Location 00CH
This location is reserved for the Timer/Event Counter
interrupt service program. If a timer interrupt results
from a Timer/Event Counter overflow, and the interrupt is enabled and the stack is not full, the program
begins execution at location 00CH.
· Table location
Any location in the program memory can be used as
look-up tables. There are three method to read the
0 0 0 H
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
U S B In te r r u p t S u b r o u tin e
0 0 C H
T im e r /E v e n t C o u n te r
In te r r u p t S u b r o u tin e
P ro g ra m
M e m o ry
n 0 0 H
L o o k - u p T a b le ( 2 5 6 W o r d s )
n F F H
L o o k - u p T a b le ( 2 5 6 W o r d s )
F F F H
1 5 B its
N o te : n ra n g e s fro m
0 0 H
to 0 F H
Program Memory
Instruction
Table Location
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *11~*0: Table location bits
P11~P8: Current program counter bits when TBHP is disabled
@[email protected]: TBLP bits
Rev. 1.50
TBHP register bit3~bit0 when TBHP is enabled
7
December 22, 2008
HT82M9AEE/HT82M9AAE
B a n k 0
Stack Register - STACK
0 0 H
This is a special part of the memory which is used to
save the contents of the program counter only. The
stack is organized into 4 levels and is neither part of the
data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
B P
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
W D T S
0 A H
S T A T U S
0 B H
IN T C
0 C H
0 D H
0 E H
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 4 return addresses are stored).
0 F H
T M R H
1 0 H
T M R L
1 1 H
T M R C
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
1 7 H
1 8 H
1 9 H
Data Memory - RAM for Bank 0
The data memory is designed with 224´8 bits. The data
memory is divided into two functional groups: special
function registers and general purpose data memory
(224´8). Most are read/write, but some are read only.
1 A H
U S C
1 B H
U S R
1 C H
S C C
1 D H
1 E H
1 F H
2 0 H
The unused spaces before the 20H is reserved for future expanded usage and reading these locations will
get ²00H². The general purpose data memory, addressed from 20H to FFH, is used for data and control
information under instruction commands.
T B H P
G e n e ra l P u rp o s e
D a ta M e m o ry
(2 2 4 B y te s )
F F H
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer registers (MP0 or MP1).
Bank 0 RAM Mapping
Indirect Addressing Register
Locations 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write
operation on [00H] ([02H]) will access the data memory
pointed to by MP0 (MP1). Reading location 00H (02H)
indirectly will return the result 00H. Writing indirectly results in no operation.
Data Memory - RAM for Bank 1
The special function registers used in the USB interface
are located in RAM Bank1. In order to access Bank1
register, only the Indirect addressing pointer MP1 can
be used and the Bank register BP should be set to 1.
The RAM bank 1 mapping is as shown.
The indirect addressing pointer (MP0) always points to
Bank0 RAM addresses no matter the value of Bank
Register (BP).
Address 00~1FH in RAM Bank0 and Bank1 are located
in the same Registers
The indirect addressing pointer (MP1) can access
Bank0 or Bank1 RAM data according to the value of BP
which is set to ²0² or ²1² respectively.
The memory pointer registers (MP0 and MP1) are 8-bit
registers.
Rev. 1.50
8
December 22, 2008
HT82M9AEE/HT82M9AAE
Accumulator
B a n k 1
0 0 H
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
B P
0 5 H
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
Arithmetic and Logic Unit - ALU
This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
0 9 H
W D T S
0 A H
S T A T U S
0 B H
IN T C
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
0 C H
· Rotation (RL, RR, RLC, RRC)
0 D H
· Increment and Decrement (INC, DEC)
0 E H
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
0 F H
T M R H
1 0 H
T M R L
1 1 H
T M R C
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, operations related to the status register may give different results from those intended.
U S C
1 B H
U S R
1 C H
S C C
1 D H
1 E H
1 F H
2 0 H
T B H P
4 1 H
P ip e _ c tr l
4 2 H
A W R
4 3 H
S T A L L
4 4 H
4 5 H
4 6 H
4 7 H
The TO flag can be affected only by a system power-up,
a WDT time-out or executing the ²CLR WDT² or ²HALT²
instruction. The PDF flag can be affected only by executing the ²HALT² or ²CLR WDT² instruction or during a
system power-up.
S IE S
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
M IS C
E n d p t_ E N
4 8 H
4 9 H
F IF O
4 A H
F IF O 2
F IF O
In addition, upon entering the interrupt sequence or executing a subroutine call, the status register will not be
automatically pushed onto the stack. If the contents of
the status are important and if the subroutine can corrupt the status register, precautions must be taken to
save it properly.
0
1
Bank 1 RAM Mapping
Rev. 1.50
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December 22, 2008
HT82M9AEE/HT82M9AAE
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by a system power-up or executing the ²CLR WDT² instruction. PDF is set by
executing the ²HALT² instruction.
5
TO
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is
set by a WDT time-out.
6~7
¾
Unused bit, read as ²0²
Status (0AH) Register
Interrupt
program which corrupts the desired control sequence,
the contents should be saved in advance.
The device provides an external interrupt and internal
timer/event counter interrupts. The Interrupt Control
Register (INTC;0BH) contains the interrupt control bits
to set the enable/disable and the interrupt request flags.
The USB interrupts are triggered by the following USB
events and the related interrupt request flag (USBF; bit
4 of the INTC) will be set.
· Access of the corresponding USB FIFO from PC
Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC may be
set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If
immediate service is desired, the stack must be prevented from becoming full.
· The USB suspend signal from PC
· The USB resume signal from PC
· USB Reset signal
When the interrupt is enabled, the stack is not full and
the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (USBF)
and EMI bits will be cleared to disable other interrupts.
When the PC Host access the FIFO of the
HT82M9AEE, the corresponding request bit of the USR
is set, and a USB interrupt is triggered. So user can easily decide which FIFO is accessed. When the interrupt
has been served, the corresponding bit should be
cleared by firmware. When the HT82M9AEE receives a
USB Suspend signal from the Host PC, the suspend line
(bit0 of the USC) of the HT82M9AEE is set and a USB
interrupt is also triggered.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at a specified location in the
program memory. Only the program counter is pushed
onto the stack. If the contents of the register or status
register (STATUS) are altered by the interrupt service
When the HT82M9AEE receives a Resume signal from
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt (1=enable; 0=disable)
1
EUI
Controls the USB interrupt (1=enable; 0= disable)
2, 5, 7
¾
Unused bit, read as ²0²
3
ETI
Controls the Timer/Event Counter interrupt (1=enable; 0=disable)
4
USBF
6
TF
USB interrupt request flag (1=active; 0=inactive)
Internal timer/event counter request flag (1:active; 0:inactive)
INTC (0BH) Register
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HT82M9AEE/HT82M9AAE
nal signal to conserve power.
the Host PC, the resume line (bit3 of the USC) of the
HT82M9AEE are set and a USB interrupt is triggered.
A crystal across OSC1 and OSC2 is needed to provide
the feedback and phase shift required for the oscillator.
No other external components are required. In stead of
a crystal, a resonator can also be connected between
OSC1 and OSC2 to get a frequency reference, but two
external capacitors in OSC1 and OSC2 are required.
Whenever a USB reset signal is detected, the USB interrupt is triggered and URST_Flag bit of the USC register is set. When the interrupt has been served, the bit
should be cleared by firmware.
The internal timer/event counter interrupt is initialized by
setting the timer/event counter interrupt request flag (bit
6 of the INTC), caused by a timer overflow. When the interrupt is enabled, the stack is not full and the TF is set, a
subroutine call to location 0CH will occur. The related interrupt request flag (TF) will be reset and the EMI bit
cleared to disable further interrupts.
The HT82M9AEE can operate in 6MHz or 12MHz system clocks. In order to make sure that the USB SIE functions properly, user should correctly configure the
SCLKSEL bit of the SCC Register. The default system
clock is 12MHz.
The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works within
a period of approximately 31ms. The WDT oscillator can
be disabled by ROM code option to conserve power.
During the execution of an interrupt subroutine, other interrupt acknowledge signals are held until the ²RETI² instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, ²RET² or ²RETI²
may be invoked. RETI will set the EMI bit to enable an
interrupt service, but RET will not.
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator), or instruction clock (system clock divided by 4), determine by ROM code option.
This timer is designed to prevent a software malfunction
or sequence from jumping to an unknown location with
unpredictable results. The Watchdog Timer can be disabled by ROM code option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no
operation.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
Priority
Vector
USB interrupt
1
04H
Timer/Event Counter overflow
2
0CH
Once the internal WDT oscillator (RC oscillator with a
period of 31ms at 5V normally) is selected, it is first divided by 256 (8-stage) to get the nominal time-out period of 8ms/5V. This time-out period may vary with
temperatures, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be realized. Writing data to WS2, WS1, WS0 (bits 2, 1, 0 of the
WDTS) can give different time-out periods. If WS2,
WS1, and WS0 are all equal to 1, the division ratio is up
to 1:128, and the maximum time-out period is 1s/5V. If
the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operates in the
same manner except that in the HALT state the WDT
may stop counting and lose its protecting purpose. In
this situation the logic can only be restarted by external
logic. The high nibble and bit 3 of the WDTS are reserved for user defined flags, which can only be set to
²10000² (WDTS.7~WDTS.3).
Once the interrupt request flags (TF, USBF) are set,
they will remain in the INTC register until the interrupts
are serviced or cleared by a software instruction.
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only one
stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged
once the ²CALL² operates in the interrupt subroutine.
Oscillator Configuration
There is an oscillator circuit in the microcontroller.
This oscillator is designed for system clocks. The HALT
mode stops the system oscillator and ignores an exterO S C 1
O S C 2
C r y s ta l O s c illa to r
System Oscillator
Rev. 1.50
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December 22, 2008
HT82M9AEE/HT82M9AAE
S y s te m
C lo c k /4
R O M
C o d e
O p tio n
S e le c t
W D T
O S C
W D T P r e s c a le r
8 - b it C o u n te r
7 - b it C o u n te r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
· All of the I/O ports remain in their original status.
If the device operates in a noisy environment, using the
on-chip 32kHz RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
· The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow performs a ²warm reset². After the TO and PDF flags are
examined, the cause for chip reset can be determined.
The PDF flag is cleared by a system power-up or executing the ²CLR WDT² instruction and is set when executing the ²HALT² instruction. The TO flag is set if the
WDT time-out occurs, and causes a wake-up that only
resets the program counter and SP; the others remain in
their original status.
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake-up the
device by mask option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it awakens from an interrupt, two sequence
may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is
enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request flag is set to
²1² before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 tSYS (system clock
period) to resume normal operation. In other words, a
dummy period will be inserted after a wake-up. If the
wake-up results from an interrupt acknowledge signal,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
WDTS (09H) Register
The WDT overflow under normal operation will initialize
a ²chip reset² and set the status bit ²TO². But in the
HALT mode, the overflow will initialize a ²warm reset²
and only the program counter and SP are reset to zero.
To clear the contents of the WDT (including the WDT
prescaler), three methods are adopted; external reset (a
low level to RES), software instruction and a ²HALT² instruction. The software instruction include ²CLR WDT²
and the other set - ²CLR WDT1² and ²CLR WDT2². Of
these two types of instruction, only one can be active depending on the ROM code option - ²CLR WDT times selection option². If the ²CLR WDT² is selected (i.e.
CLRWDT times is equal to one), any execution of the
²CLR WDT² instruction will clear the WDT. In the case
that ²CLR WDT² and ²CLR WDT² are chosen (i.e.
CLRWDT times is equal to two), these two instructions
must be executed to clear the WDT; otherwise, the WDT
may reset the chip as a result of time-out.
Power Down Operation - HALT
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
The HALT mode is initialized by the ²HALT² instruction
and results in the following:
· The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is selected).
· The contents of the on-chip RAM and registers remain
unchanged.
· The WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT oscillator).
Rev. 1.50
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December 22, 2008
HT82M9AEE/HT82M9AAE
Reset
The functional unit chip reset status are shown below.
There are four ways in which a reset can occur:
Program Counter
000H
· RES reset during normal operation
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
· RES reset during HALT
· WDT time-out reset during normal operation
· USB reset
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re set² that resets only the program counterand SP, leaving
the other circuits in their original state. Some registers
remain unchanged during other reset conditions. Most
registers are reset to the ²initial condition² when the reset conditions are met. By examining the PDF and TO
flags, the program can distinguish between different
²chip resets².
TO PDF
Timer/event Counter Off
Input/output Ports
Input mode
Stack Pointer
Points to the top of the stack
V
D D
RESET Conditions
0
0
RES reset during power-up
0
0
RES reset during normal operation
R E S
0
0
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
Reset Circuit
Note: ²u² stands for ²unchanged²
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra delay of 1024 system clock pulses when the system resets (power-up, WDT time-out or RES reset) or
the system awakes from the HALT state.
H A L T
W a rm
R e s e t
W D T
R E S
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will enable the SST delay.
O S C 1
C o ld
R e s e t
S S T
1 0 - b it R ip p le
C o u n te r
V D D
R E S
tS
S y s te m
S T
Reset Configuration
S S T T im e - o u t
C h ip
R e s e t
R e s e t
Reset Timing Chart
Rev. 1.50
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December 22, 2008
HT82M9AEE/HT82M9AAE
The registers status are summarized in the following table.
Reset
(Power On)
WDT
Time-out
(Normal
Operation)
RES Reset
(Normal
Operation)
RES Reset
(HALT)
WDT
Time-Out
(HALT)*
USB-Reset
(Normal)
USB-Reset
(HALT)
TMRH
xxxx xxxx
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMRL
xxxx xxxx
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMRC
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
00-0 1---
00-0 1---
000H
000H
000H
000H
000H
000H
000H
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
BP
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
TBHP
xxxx xxxx
0000 uuuu
0000 uuuu
0000 uuuu
0000 uuuu
0000 uuuu
0000 uuuu
STATUS
--00 xxxx
--1u uuuu
--00 uuuu
--00 uuuu
--11 uuuu
--uu uuuu
--01 uuuu
Register
Program
Counter
INTC
-000 0000
-000 0000
--00 uuuu
-000 0000
-uuu uuuu
-000 0000
-000 0000
WDTS
1000 0111
1000 0111
1000 0111
1000 0111
uuuu uuuu
1000 0111
1000 0111
PA
1111 1111
xxxx xxxx
1111 1111
1111 1111
xxxx xxxx
1111 1111
1111 1111
PAC
1111 1111
xxxx xxxx
1111 1111
1111 1111
xxxx xxxx
1111 1111
1111 1111
PB
1111 1111
xxxx xxxx
1111 1111
1111 1111
xxxx xxxx
1111 1111
1111 1111
PBC
1111 1111
xxxx xxxx
1111 1111
1111 1111
xxxx xxxx
1111 1111
1111 1111
AWR
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
STALL
0000 0110
0000 uuuu
0000 1110
0000 1110
0000 uuuu
0000 0000
0000 0000
SIES
0100 0000
uuuu uuuu
0100 0000
0100 0000
uuuu uuuu
0000 0000
0000 0000
MISC
0x00 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
FIFO0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
FIFO1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
FIFO2
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
Pipe_ctrl
0000 0110
0000 0uuu
0000 0110
0000 0110
0000 0110
0000 0110
0000 0110
Endpt_EN
0000 0111
0000 0uuu
0000 0111
0000 0111
0000 0111
0000 0111
0000 0111
USC
11xx 0000
11xx xuux
11xx 0000
11xx 0000
11xx xuux
1100 0u00
1100 0u00
USR
0000 0000
u0uu 0u00
0000 0000
0000 0000
u0uu uuuu
u1uu 0000
u1uu 0000
SCC
0000 0000
uu00 u000
0000 0000
0000 0000
uu0u u000
uu00 u000
uu00 u000
Note: ²*² stands for ²warm reset²
²u² stands for ²unchanged²
²x² stands for ²unknown²
Rev. 1.50
14
December 22, 2008
HT82M9AEE/HT82M9AAE
Timer/Event Counter
nal (TMR) pin. The timer mode functions as a normal
timer with the clock source coming from the fSYS/4
(Timer). The pulse width measurement mode can be
used to count the high or low level duration of the external signal (TMR). The counting is based on the fSYS/4.
A timer/event counter (TMR) is implemented in the
microcontroller.
The timer/event counter contains a 16-bit programmable count-up counter and the clock may come from an
external source or from the system clock divided by 4.
In the event count or timer mode, once the timer/event
counter starts counting, it will count from the current
contents in the timer/event counter to FFFFH. Once
overflow occurs, the counter is reloaded from the
timer/event counter preload register and generates the
interrupt request flag (TF; bit 6 of the INTC) at the same
time.
Using the internal clock source, there is only 1 reference
time-base for the timer/event counter. The internal clock
source is coming from fSYS/4. The external clock input
allows the user to count external events, measure time
intervals or pulse widths.
There are 3 registers related to the timer/event counter;
TMRH (0FH), TMRL (10H), TMRC (11H). Writing TMRL
will only put the written data to an internal lower-order
byte buffer (8 bits) and writing TMRH will transfer the
specified data and the contents of the lower-order byte
buffer to TMRH and TMRL preload registers, respectively. The timer/event counter preload register is
changed by each writing TMRH operations. Reading
TMRH will latch the contents of TMRH and TMRL counters to the destination and the lower-order byte buffer,
respectively. Reading the TMRL will read the contents of
the lower-order byte buffer. The TMRC is the
timer/event counter control register, which defines the
operating mode, counting enable or disable and active
edge.
In the pulse width measurement mode with the TON and
TE bits equal to one, once the TMR has received a transient from low to high (or high to low if the TE bit is ²0²) it
will start counting until the TMR returns to the original
level and resets the TON. The measured result will remain in the timer/event counter even if the activated
transient occurs again. In other words, only one cycle
measurement can be done. Until setting the TON, the
cycle measurement will function again as long as it receives further transient pulse. Note that, in this operating mode, the timer/event counter starts counting not
according to the logic level but according to the transient
edges. In the case of counter overflows, the counter is
reloaded from the timer/event counter preload register
and issues the interrupt request just like the other two
modes. To enable the counting operation, the timer ON
bit (TON; bit 4 of TMRC) should be set to 1. In the pulse
width measurement mode, the TON will be cleared au-
The TM0, TM1 bits define the operating mode. The
event count mode is used to count external events,
which means that the clock source comes from an exterBit No.
Label
0~2, 5
¾
Unused bit, read as ²0²
3
TE
Defines the TMR active edge of the timer/event counter
(0=active on low to high; 1=active on high to low)
4
TON
Enable/disable the timer counting (0=disable; 1=enable)
TM0
TM1
Defines the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
6
7
Function
TMRC (11H) Register
D a ta B u s
fS
Y S /4
T M 1
T M 0
T M R
1 6 B its
T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
L o w B y te
B u ffe r
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
1 6 B its
T im e r /E v e n t C o u n te r
(T M R H /T M R L )
O v e r flo w
to In te rru p t
Timer/Event Counter
Rev. 1.50
15
December 22, 2008
HT82M9AEE/HT82M9AAE
of the control register must write a ²1². The input source
also depends on the control register. If the control register bit is ²1², the input will read the pad state. If the control register bit is ²0², the contents of the latches will
move to the internal bus. The latter is possible in the
²read-modify-write² instruction. For output function,
CMOS/NMOS/PMOS configurations can be selected
(NMOS and PMOS are available for PA only). These
control registers are mapped to locations 13H and 15H.
tomatically after the measurement cycle is completed.
But in the other two modes the TON can only be reset by
instructions. The overflow of the timer/event counter is
one of the wake-up sources. No matter what the operation mode is, writing a ²0² to ET can disable the corresponding interrupt services.
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register will also
reload that data to the timer/event counter. But if the
timer/event counter is turned on, data written to it will
only be kept in the timer/event counter preload register.
The timer/event counter will still operate until overflow
occurs (a timer/event counter reloading will occur at the
same time). When the timer/event counter (reading
TMR) is read, the clock will be blocked to avoid errors.
As clock blocking may result in a counting error, this
must be taken into consideration by the programmer.
After a chip reset, these input/output lines remain at high
levels or in a floating state (depending on the
pull-high/low options). Each bit of these input/output
latches can be set or cleared by ²SET [m].i² and ²CLR
[m].i² (m=12H or 14H) instructions.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Input/Output Ports
There are 16 bidirectional input/output lines in the
microcontroller, labeled from PA to PB, which are
mapped to the data memory of [12H] and [14H] respectively. All of these I/O ports can be used for input and
output operations. For input operation, these ports are
non-latching, that is, the inputs must be ready at the T2
rising edge of instruction ²MOV A,[m]² (m=12H or 14H).
For output operation, all the data is latched and remains
unchanged until the output latch is rewritten.
Each line of PA0~PA7, PB4/SDA and PB7/SCL has the
capability of waking-up the device.
There are pull-high/low options available for I/O lines.
Once the pull-high/low option of an I/O line is selected,
the I/O line have pull-high/low resistor. Otherwise, the
pull-high/low resistor is absent. It should be noted that a
non-pull-high/low I/O line operating in input mode will
cause a floating state.
Each I/O line has its own control register (PAC and PBC)
to control the input/output configuration. With this control register, CMOS/NMOS/PMOS output or Schmitt
trigger input with or without pull-high/low resistor structures can be reconfigured dynamically under software
control. To function as an input, the corresponding latch
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
V
D a ta B u s
W r ite C o n tr o l R e g is te r
C o n tr o l B it
Q
D
C K
D D
P u ll- h ig h
O p tio n
Q
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
P o rt O u tp u t
C o n fig u r a tio n
R e a d D a ta R e g is te r
P A
P B
P B
P B
P B
D a ta B it
Q
D
C K
S
Q
0 ~
0 ~
4 /S
5 ~
7 /S
P A
P B
D
P B
C
A
L
3
7
6
P u ll- lo w
M
U
X
P A W a k e -u p
P A 7 /T M R
P A W a k e - u p O p tio n
Input/Output Ports
Rev. 1.50
16
December 22, 2008
HT82M9AEE/HT82M9AAE
Low Voltage Reset - LVR
The relationship between VDD and VLVR is shown below.
The microcontroller contains a low voltage reset circuit
in order to monitor the supply voltage of the device. If the
supply voltage of the device drops to within the range of
0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally.
V D D
5 .5 V
The LVR includes the following specifications:
2 .7 V
V
O P R
5 .5 V
V
2 .4 V
· For a valid LVR signal, a low voltage (0.9V~VLVR) must
exist for more than 1ms. If the low voltage state does
not exceed 1ms, the LVR will ignore it and will not perform a reset function.
0 .9 V
· The LVR uses the ²OR² function with the external
Note: VOPR is the voltage range for proper chip operation at 6MHz or 12MHz system clock.
RES signal to perform a chip reset.
V
L V R
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
R e s e t
*1
*2
Low Voltage Reset
Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: A low voltage has to exist for more than 1ms, after that 1ms delay, the device enters a reset mode.
Rev. 1.50
17
December 22, 2008
HT82M9AEE/HT82M9AAE
Data EEPROM Functional Description
· Serial clock (SCL)
· Acknowledge
The SCL input is used for positive edge clock data into
each EEPROM device and negative edge clock data
out of each device.
All addresses and data words are serially transmitted
to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth
clock cycle.
· Serial data (SDA)
The SDA pin is bidirectional for serial data transfer.
The pin is open-drain driven and may be wired-OR
with any number of other open-drain or open collector
devices.
D a ta a llo w e d
to c h a n g e
S D A
Memory Organization
S C L
S ta rt
c o n d itio n
· 1K Serial EEPROM
Internally organized with 128 8-bit words, the 1K requires an 8-bit data word address for random word addressing.
S to p
c o n d itio n
N o A C K
s ta te
A d d re s s o r
a c k n o w le d g e
v a lid
Device Addressing
The 1K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip
for a read or write operation. The device address word
consist of a mandatory one, zero sequence for the first
four most significant bits (refer to the diagram showing
the Device Address). This is common to all the
EEPROM device.
Device Operations
· Clock and data transition
Data transfer may be initiated only when the bus is not
busy. During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
data line while the clock line is high will be interpreted
as a START or STOP condition.
The next three bits are the fixed to be ²0².
· Start condition
The 8th bit of device address is the read/write operation
select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
A high-to-low transition of SDA with SCL high is a start
condition which must precede any other command
(refer to Start and Stop Definition Timing diagram).
If the comparison of the device address succeed the
EEPROM will output a zero at ACK bit. If not, the chip will
return to a standby state.
· Stop condition
A low-to-high transition of SDA with SCL high is a stop
condition. After a read sequence, the stop command
will place the EEPROM in a standby power mode (refer to Start and Stop Definition Timing Diagram).
1
0
1
0
0
0
0
R /W
D e v ic e A d d r e s s
D e v ic e a d d r e s s
S D A
W o rd a d d re s s
D A T A
S
S ta rt
P
R /W
A C K
A C K
A C K
S to p
Byte Write Timing
Rev. 1.50
18
December 22, 2008
HT82M9AEE/HT82M9AAE
Write Operations
· Read operations
· Byte write
The data EEPROM supports three read operations,
namely, current address read, random address read
and sequential read. During read operation execution,
the read/write select bit should be set to ²1².
A write operation requires an 8-bit data word address
following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will
again respond with a zero and then clock in the first
8-bit data word. After receiving the 8-bit data word, the
EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the
write sequence with a stop condition. At this time the
EEPROM enters an internally-timed write cycle to the
non-volatile memory. All inputs are disabled during
this write cycle and EEPROM will not respond until the
write is completed (refer to Byte write timing).
· Current address read
The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This address stays valid
between operations as long as the chip power is maintained. The address roll over during read from the last
byte of the last memory page to the first byte of the
first page. The address roll over during write from the
last byte of the current page to the first byte of the
same page. Once the device address with the
read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address
data word is serially clocked out. The microcontroller
should respond a No ACK (High) signal and following
stop condition (refer to Current read timing).
· Acknowledge polling
To maximise bus throughput, one technique is to allow
the master to poll for an acknowledge signal after the
start condition and the control byte for a write command have been sent. If the device is still busy implementing its write cycle, then no ACK will be returned.
The master can send the next read/write command
when the ACK signal has finally been received.
· Random read
A random read requires a dummy byte write sequence
to load in the data word address which is then clocked
in and acknowledged by the EEPROM. The
microcontroller must then generate another start condition. The microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the
data word. The microcontroller should respond with a
²no ACK² signal (high) followed by a stop condition.
(refer to Random read timing).
S e n d W r ite C o m m a n d
S e n d S to p C o n d itio n
to In itia te W r ite C y c le
S e n d S ta rt
S e n d C o tr o ll B y te
w ith R /W = 0
(A C K = 0 )?
N o
Y e s
N e x t O p e r a tio n
Acknowledge Polling Flow
D e v ic e a d d r e s s
S D A
D A T A
S to p
S
P
S ta rt
A C K
N o A C K
Current Read Timing
D e v ic e a d d r e s s
S D A
W o rd a d d re s s
S
S ta rt
D e v ic e a d d r e s s
D A T A
S
A C K
A C K
S ta rt
S to p
P
A C K
N o A C K
Random Read Timing
Rev. 1.50
19
December 22, 2008
HT82M9AEE/HT82M9AAE
· Sequential read
Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledgment. As long as the EEPROM receives an acknowledgment, it will
continue to increment the data word address and serially clock out sequential data words. When the memory address
limit is reached, the data word address will roll over and the sequential read continues. The sequential read operation is
terminated when the microcontroller responds with a ²no ACK² signal (high) followed by a stop condition.
D e v ic e a d d r e s s
S D A
D A T A n
D A T A n + 1
D A T A n + x
S to p
P
S
A C K
S ta rt
N o A C K
A C K
Sequential Read Timing
Data EEPROM Timing Diagrams
tf
tr
tL
S C L
tS
S D A
U
:S
tH
T A
tS
tH
IG H
D
O W
:S
T A
tH
D
:D
A T
tS
:D
U
A T
tS
U
tB
U F
:S
T O
P
tA
S D A
A
V a lid
O U T
V a lid
S C L
S D A
8 th b it
A C K
W o rd n
tW
S to p
C o n d itio n
R
S ta rt
C o n d itio n
Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the valid start
condition of sequential command.
Rev. 1.50
20
December 22, 2008
HT82M9AEE/HT82M9AAE
USB with MCU Interface
There are eight registers, including Pipe_ctrl, Address+Remote_WakeUp, STALL, SIES, MISC, Endpt_EN and FIFO
0~FIFO 2 in this buffer function.
Register
Name
Pipe_ctrl
Addr.+
Remote
STALL
SIES
MISC
Endpt_EN
FIFO 0
FIFO 1
FIFO 2
Mem. Addr.
41H
42H
43H
45H
46H
47H
48H
49H
4AH
Register Memory Mapping
Address+Remote_WakeUp register represents current address and remote wake-up function. The initial value is
²00000000² from MSB to LSB.
Register
Address
R/W
01000010B
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Remote Wake-up Function
0: Not this function
1: The function exists
Address value
Default value=00000000
Address+Remote_WakeUp Register
STALL, Pipe_ctrl and Endpt_EN Registers
STALL register shows whether the endpoint corresponding works or not. As soon as the endpoint work improperly, the
bit corresponding must be set.
Pipe_ctrl register is used for configuring IN (Bit=1) or OUT (Bit=0) pipe. The default is define IN pipe. Where Bit0
(DATA0) of the Pipe_ctrl register is used to setting the data toggle of any endpoint (except endpoint 0) using data toggles to the value DATA0. Once the user want the any endpoint (except endpoint 0) using data toggles to the value
DATA0, the user can output a LOW pulse to this bit. The LOW pulse period must at least 10 instruction cycle.
Endpt_EN register is used to enable or disable the corresponding endpoint (except endpoint 0). Enable Endpoint
(Bit=1) or disable Endpoint (Bit=0).
The bitmaps are list as follows:
Register
Name
R/W
Register
Address
Bit7~Bit3
Reserved
Bit 2
Bit 1
Bit 0
Default
Value
Pipe_ctrl
R/W
01000001B
¾
Pipe 2
Pipe 1
Data 0
0000 0110
STALL
R/W
01000011B
¾
Pipe 2
Pipe 1
Pipe 0
0000 0111
Endpt_EN
R/W
01000111B
¾
Pipe 2
Pipe 1
Pipe 0
0000 0111
Pipe_ctrl (41H), STALL (43H) and Endpt_EN (47H) Registers
Rev. 1.50
21
December 22, 2008
HT82M9AEE/HT82M9AAE
The SIES Register is used to indicate the present signal state which the USB SIE received and also determines
whether the USB SIE has to change the device address automatically.
Bit No.
Function
Read/Write
7
MNI
R/W
6~2
¾
¾
1
F0_ERR
R/W
0
Adr_set
R/W
Register Address
01000001B
SIES (45H) Registers Table
Function
Name
Read/Write
Description
Adr_set
R/W
This bit is used to configure the USB SIE to automatically change the device address with
the value of the Address+Remote_WakeUp Register (42H).
When this bit is set to 1 by F/W, the USB SIE will update the device address with the value
of the Address+Remote_WakeUp Register (42H) after the PC Host has successfully read
the data from the device by the IN operation. The USB SIE will clear the bit after updating
the device address.
Otherwise, when this bit is cleared to ²0², the USB SIE will update the device address immediately after an address is written to the Address+Remote_WakeUp Register (42H).
F0_Err
R/W
This bit is used to indicate when there are some errors that occurred when the FIFO0 is
accessed.
This bit is set by the USB SIE and cleared by F/W.
¾
¾
MNI
R/W
Unused bit, read as ²0²
This bit is for masking the NAK interrupt when MNI=²1², the default value=²0²
SIES Function Table
The MISC register is actually a command + status to control the desired FIFO action and to show the status of the desired FIFO. Every bit¢s meaning and usage are listed as follows:
Bit No.
Function
Read/Write
7
Len0
R/W
6
Ready
R
5
Set CMD
R/W
4
Sel_pipe1
R/W
3
Sel_pipe0
R/W
2
Clear
R/W
1
Tx
R/W
0
Request
R/W
Register Address
01000110B
MISC (46H) Registers Table
Rev. 1.50
22
December 22, 2008
HT82M9AEE/HT82M9AAE
Function
Name
Read/Write
Description
Request
R/W
After setting the other desired status, FIFO can be requested by setting this bit high active. After work has been done, this bit must be set low.
Tx
R/W
Represents the direction and transition end of the MCU accesses. When being set as
logic 1, the MCU wants to write data to FIFO. After work has been done, this bit must be
set to logic 0 before terminating the request to represent a transition end. For reading
action, this bit must be set to logic 0 to indicate that the MCU wants to read and must be
set to logic 1 after work is done.
Clear
R/W
Represents MCU clear requested FIFO, even if FIFO is not ready.
Sel_pipe1
Sel_pipe0
R/W
Determines which FIFO is desired, ²00² for FIFO 0, ²01² for FIFO 1 and ²10² for FIFO 2
Set CMD
R/W
Shows that the data in FIFO is setup as command. This bit will be cleared by firmware.
So, even if the MCU is busy, nothing is missed by the SETUP command from the host.
Ready
R
Len0
R/W
Indicates that the desired FIFO is ready to work.
Indicates that the host sent a 0-sized packet to the MCU. This bit must be cleared by a
read action to the corresponding FIFO. Also, this bit will be cleared by the USB SIE after
the next valid SETUP token is received.
MISC Function Table
The HT82M9AEE have two 8´8 bidirectional FIFO for
the three endpoints (control and Interrupt). User can
easily read/write the FIFO data by accessing the corresponding FIFO pointer register (FIFO0, FIFO1, FIFO2).
The following are two examples for reading and writing
the FIFO data:
HT82M9AEE allows a maximum of 8 bytes of data in
each packet.
HT82M9AEE FIFO is read by packet. To read from
FIFO, the following should be followed:
· Check the ready bit until the status = 1
The HT82M9AEE FIFO is written by packet. To write to
FIFO, the following should be followed:
· Select a set of FIFO, set in the write mode (MISC TX
bit = 1), and set the REQ bit to ²1²
· Write through the FIFO pointer register and take down
· Select one set of FIFO, set in the read mode (MISC
the data number that has been written
TX bit = 0), and set the REQ bit to ²1².
· Repeat steps 2 and 3 until writing is complete or the
· Check the ready bit until the status = 1
ready bit becomes 0 which indicates that the FIFO no
longer allows any data writing.
· Set MISC TX bit = 0
· Read through the FIFO pointer register, and record
the data number that has been read.
· Clear the REQ bit to 0. Complete writing.
· Repeat steps 2 and 3 until the ready bit becomes 0
which indicates the end of the FIFO data reading.
User writes the data through the FIFO pointer register,
user has to record the number of bytes that have been
written. The HT82M9AEE allows a maximum of 8 bytes
of data in each packet.
· Set MISC TX bit = 1
· Clear the REQ bit to 0. Complete reading.
User reads the data through the FIFO pointer register,
user has to record the number of bytes to be read. The
Rev. 1.50
23
December 22, 2008
HT82M9AEE/HT82M9AAE
There are some timing constrains and usages illustrated here. By setting the MISC register, the MCU can perform reading, writing and clearing actions. There are some examples shown in the following table for endpoint FIFO reading, writing and clearing.
Actions
MISC Setting Flow and Status
Read FIFO0 sequence
00H®01H®delay of 2ms, check 41H®read* from FIFO0 register
and check if not ready (01H)®03H®02H
Write FIFO1 sequence
0AH®0BH®delay of 2ms, check 4BH®write* to FIFO1 register and
check if not ready (0BH)®09H®08H
Check whether FIFO0 can be read or not
00H®01H®delay of 2ms, check 41H (if ready) or 01H (if not ready)
®00H
Check whether FIFO1 can be written to or not
0AH®0BH®delay of 2ms, check 4BH (if ready) or 0BH (if not ready)
®0AH
Write 0-sized packet sequence to FIFO 0
02H®03H®delay of 2ms, check 43H®01H®00H
Note: *: There are 2ms gap existing between 2 reading actions or between 2 writing actions
Register Name
R/W
Register Address
Bit7~Bit0
FIFO 0
R/W
01001000B
Data7~Data0
FIFO 1
R/W
01001001B
Data7~Data0
FIFO 2
R/W
01001010B
Data7~Data0
FIFO Register Address Table
USB Active Pipe Timing
The USB active pipe accessed by the host cannot be used by the MCU simultaneously. When the host finishes its work,
the signal, a USB_INT will be produced to tell the MCU that the pipe can be used and the acted pipe No. will be shown
in the signal, ACT_PIPE as well. The timing is illustrated in the figure below.
L a s t A c te d P ip e
A C T _ P IP E
U S B _ IN T
USB Active Pipe Timing
Suspend Wake-Up and Remote Wake-Up
signal will be cleared before the Idle signal is sent out by
the host and the Suspend line (bit 0 of the USC) is going
to ²0². So when the MCU is detecting the Suspend line
(bit0 of the USC), the Resume line should be remembered and taken into consideration.
If there is no signal on the USB bus for over 3ms, the
HT82M9AEE will go into a suspend mode. The Suspend
line (bit 0 of the USC) will be set to 1 and a USB interrupt
is triggered to indicate that the HT82M9AEE should
jump to the suspend state to meet the 500mA USB suspend current spec.
After finishing the resume signal, the suspend line will
go inactive and a USB interrupt is triggered. The following is the timing diagram:
In order to meet the 500mA suspend current, the programmer should disable the USB clock by clearing the
USBCKEN (bit3 of the SCC) to ²0². The suspend current is 400mA.
S U S P E N D
U S B R e s u m e S ig n a l
When the resume signal is sent out by the host, the
HT82M9AEE will wake-up the MCU by USB interrupt
and the Resume line (bit 3 of the USC) is set. In order to
make the HT82M9AEE function properly, the programmer must set the USBCKEN (bit 3 of the SCC) to 1 and
clear the SUSP2 (bit4 of the SCC). Since the Resume
Rev. 1.50
U S B _ IN T
The device with remote wake-up function can wake-up the
USB Host by sending a wake-up pulse through RMWK (bit
24
December 22, 2008
HT82M9AEE/HT82M9AAE
1 of USC). Once the USB Host receive the wake-up signal
from the HT82M9AEE, it will send a Resume signal to the
device. The timing is as follows:
pin USBD- is now defined as PS2 Data pin and USBD+
is now defined as PS2 Clk pin. The user can easily read
or write to the PS2 Data or PS2 Clk pin by accessing the
corresponding bit PS2DAI (bit 4 of the USC), PS2CKI
(bit 5 of the USC), PS2DAO (bit 6 of the USC) and
S2CKO (bit 7 of the USC) respectively.
S U S P E N D
M in . 1 U S B C L K
R M W K
U S B R e s u m e S ig n a l
The user should make sure that in order to read the data
properly, the corresponding output bit must be set to ²1².
For example, if user wants to read the PS2 Data by
reading PS2DAI, the PS2DAO should be set to ²1². Otherwise it always read a ²0².
M in .2 .5 m s
U S B _ IN T
If SPS2=0, and SUSB=1, the HT82M9AEE is defined as
a USB interface. Both the USBD- and USBD+ are driven
by the USB SIE of the HT82M9AEE. User only writes or
reads the USB data through the corresponding FIFO.
Configuring the Device as a PS2 Device
The HT82M9AEE can be defined as a USB interface or
a PS2 interface by configuring the SPS2 (bit 4 of the
USR) and SUSB (bit 5 of the USR). If SPS2=1, and
SUSB=0, the HT82M9AEE is defined as PS2 interface,
Both SPS2 and SUSB default is ²0².
I/O Port Special Registers Definition
· Port-A (12H) - PA
Bit No.
Label
Read/Write
Option
Functions
0~3
PA0~PA3
R/W
¾
I/O (R/W) has pull-low and pull-high option.
Has falling edge wake-up option.
4~6
PA4~PA6
R/W
¾
I/O (R/W) has pull-high option.
Has falling edge wake-up option.
7
PA7
R/W
¾
I/O (R/W) has pull-high option.
Has falling edge wake-up option, pin-shared with timer input pin.
PA (12H) Register
· Port-A Control (13H) - PAC
This port configure the input or output mode of Port-A
· Port-B Control (14H) - PB
Bit No.
Label
Read/Write
Option
Functions
0
PB0
R/W
¾
I/O (R/W), has pull-high option
1
PB1
R/W
¾
I/O (R/W), has pull-high option
2
PB2
R/W
¾
I/O (R/W), has pull-low and pull-high option
3
PB3
R/W
¾
I/O (R/W), has pull-low and pull-high option
4
PB4/SDA
R/W
¾
I/O (R/W), has pull-high option, can wake-up
5
PB5
R/W
¾
I/O (R/W), has pull-high option
6
PB6
R/W
¾
I/O (R/W), has pull-high option
7
PB7/SCL
R/W
¾
I/O (R/W), has pull-high option, can wake-up
PB (14H) Register
· Port-B Control (15H) - PBC
This port configures the input or output mode of Port-B for I/O mode
Rev. 1.50
25
December 22, 2008
HT82M9AEE/HT82M9AAE
USB/PS2 Status and Control Register - USC
Bit No.
Label
Read/Write
Option
Functions
0
PE0
R
SUSPEND
USB suspend mode status bit. When 1, indicates that the USB
system entry is in suspend mode.
1
PE1
W
RMOT_WK USB remote wake-up signal. The default value is ²0².
2
PE2
R/W
3
PE3
R
RESUME_O
4
PE4
R
PS2_DAI
USBD-/DATA input
5
PE5
R
PS2_CKI
USBD+/CLK input
6
PE6
W
PS2_DAO
Output for driving USBD-/DATA pin, when working under 3D
PS2 mouse function. The default value is ²1².
7
PE7
W
PS2_CKO
Output for driving USBD-/DATA pin, when working under 3D
PS2 mouse function. The default value is ²1².
URST_FLAG USB bus reset event flag. The default value is ²0².
When RESUME_OUT EVENT, RESUME_O is set to ²1².
The default value is ²0².
USC (0X1A) Register
Endpoint Interrupt Status Register - USR
The USR (USB endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select
the serial bus (PS2 or USB). The endpoint request flags (EP0IF, EP1IF, EP2IF) are used to indicate which endpoints
are accessed. If an endpoint is accessed, the related endpoint request flag will be set to ²1² and a USB interrupt will occur (If a USB interrupt is enabled and the stack is not full). When the active endpoint request flag is served, the endpoint
request flag has to be cleared to ²0².
Bit No.
Label
Read/Write
Option
Functions
0
PEC0
R/W
EP0IF
1
PEC1
R/W
EP1IF
2
PEC2
R/W
EP2IF
When set to ²1², indicates an endpoint 0 interrupt event. Must
wait for the MCU to process the interrupt event and clear this
bit by firmware. This bit must be ²0², then the next interrupt
event will be processed. The default value is ²0².
3
PEC3
R/W
¾
4
PEC4
R/W
SELPS2
When set to ²1², indicates that the chip is working under PS2
mode. The default value is ²0².
5
PEC5
R/W
SELUSB
When set to ²1², indicates that the chip is working under USB
mode. The default value is ²0².
6
PEC6
R/W
¾
7
PEC7
R/W
USB_flag
Reserved bit, set to ²0²
Reserved bit, set to ²0²
This flag is used to show that the MCU is in USB mode (Bit=1).
This bit is R/W by FW and will be cleared to zero after power-on
reset. The default value is ²0².
USR (0X1B) Register
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HT82M9AEE/HT82M9AAE
Clock Control Register - SCC
There is a system clock control register implemented to select the clock used in the MCU. This register consists of USB
clock control bit (USBCKEN), second suspend mode control bit (SUSPEND2) and system clock selection (SCLKSEL).
Bit No.
Label
Read/Write
Option
0~2
PF0~PF2
R/W
¾
3
PF3
R/W
USBCKEN
This bit is used to reduce power consumption in the suspend
mode. In the normal mode this bit must be cleared to zero(DeSUSPEND2 fault=²0²). In the HALT mode this bit should be set high to reduce power consumption and LVR with no function. In the USB
mode this bit cannot be set high.
4
PF4
R/W
5
PF5
R/W
¾
Functions
Reserved, must set to ²0².
USB clock control bit. When set to ²1², indicates a USBCK ON,
else USBCK OFF. The default value is ²0².
Reserved, must set to ²0².
6
PF6
R/W
SCLKSEL
System clock 6MHz or 12MHz option, when working on external oscillator mode. The default value is ²0².
0: Operating at external 12MHz mode
1: Operating at external 6MHz mode
The default value is ²0².
7
PF7
R/W
PS2_flag
This flag is used to show that the MCU is in PS2 mode (Bit=1).
This bit is R/W by FW and will be cleared to zero after power-on
reset. The default value is ²0².
SCC (0X1C) Register
Table High Byte Pointer for Current Table Read - TBHP
Bit No.
Label
Read/Write
Option
3~0
PGC3~PGC0
R/W
¾
Functions
Store current table read bit11~bit8 data
TBHP (0X1F) Register
Options
No.
Option
1
WDT clock source: RC (system/4) (default: T1)
2
WDT clock source: enable/disable for normal mode (default: disable)
3
PA0~PA7, PB4/SDA, PB7/SCL wake-up by bit (PA2, PA3 both wake-up by falling or rising edge)
(default: non wake-up)
4
PA0~PA7 pull-high by bit (default: pull-high)
5
PB pull-high by bit (default: pull-high)
6
LVR enable/disable (default: enable)
7
PA0~PA3, PB2, PB3 pull-low by bit (default: non pull-low 30kW)
8
²CLR WDT², 1 or 2 instructions
9
TBHP enable/disable (default: disable)
10
PA output mode (CMOS/NMOS/PMOS) by bit (default: CMOS)
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Application Circuits
Crystal or Ceramic Resonator for Multiple I/O Applications - HT82M9AEE
5 W
V D D
U S B -
0 .1 m F
U S B +
*
*
3 3 W
1 0 m F
1 0 0 k W
*
V D D
0 .1 m F
1 M W ***
V S S
5 W
P B 0 ~ P B 3 , P B 4 /S D A
P B 5 ~ P B 6 , P B 7 /S C L
2 2 p F
**
*
X 1
2 2 p F
0 .1 m F
1 0 k W
**
*
0 .1 m F
P A 0 ~ P A 7
O S C 1
1 .5 k W
V 3 3 O
0 .1 m F
O S C 2
R E S
4 7 p F *
3 3 W
U S B D -/D A T A
*
*
4 7 p F *
V S S
*
H T 8 2 M 9 A E E
4 7 p F
3 3 W
U S B D + /C L K
*
*
4 7 p F
Note: The resistance and capacitance for the reset circuit should be designed in such a way as to ensure that the VDD
is stable and remains within a valid operating voltage range before bringing RES to high.
X1 can use 6MHz or 12MHz, X1 as close OSC1 & OSC2 as possible
Components with * are used for EMC issue.
Components with ** are used for resonator only.
Components with *** are used for 12MHz application.
Crystal or Ceramic Resonator for Multiple I/O Applications - HT82M9AAE
V D D
U S B -
V D D
1 0 m F
1 0 0 k W
0 .1 m F
P B 0 ~ P B 3 , P B 4 /S D A
P B 5 ~ P B 6 , P B 7 /S C L
U S B +
V S S
2 2 p F
X 1
*
P A 0 ~ P A 7
2 2 p F
O S C 1
V 3 3 O
1 .5 k W
0 .1 m F
O S C 2
*
R E S
U S B D -/D A T A
0 .1 m F
V S S
U S B D + /C L K
H T 8 2 M 9 A A E
Note: X1 can use 6MHz or 12MHz, X1 as close OSC1 & OSC2 as possible
Components with * are used for resonator only.
Rev. 1.50
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HT82M9AEE/HT82M9AAE
Instruction Set
Introduction
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Central to the successful operation of any
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
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HT82M9AEE/HT82M9AAE
Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rev. 1.50
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
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HT82M9AEE/HT82M9AAE
Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
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HT82M9AEE/HT82M9AAE
Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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HT82M9AEE/HT82M9AAE
CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
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HT82M9AEE/HT82M9AAE
CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
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HT82M9AEE/HT82M9AAE
INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
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HT82M9AEE/HT82M9AAE
OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
Rev. 1.50
36
December 22, 2008
HT82M9AEE/HT82M9AAE
RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
Rev. 1.50
37
December 22, 2008
HT82M9AEE/HT82M9AAE
SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
Rev. 1.50
38
December 22, 2008
HT82M9AEE/HT82M9AAE
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev. 1.50
39
December 22, 2008
HT82M9AEE/HT82M9AAE
SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.50
40
December 22, 2008
HT82M9AEE/HT82M9AAE
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.50
41
December 22, 2008
HT82M9AEE/HT82M9AAE
Package Information
20-pin SSOP (150mil) Outline Dimensions
1 1
2 0
A
B
1
1 0
C
C '
G
H
D
E
Symbol
Rev. 1.50
a
F
Dimensions in mil
Min.
Nom.
Max.
A
228
¾
244
B
150
¾
158
C
8
¾
12
C¢
335
¾
347
D
49
¾
65
E
¾
25
¾
F
4
¾
10
G
15
¾
50
H
7
¾
10
a
0°
¾
8°
42
December 22, 2008
HT82M9AEE/HT82M9AAE
24-pin SSOP (150mil) Outline Dimensions
1 3
2 4
A
B
1 2
1
C
C '
G
H
D
E
Symbol
Rev. 1.50
a
F
Dimensions in mil
Min.
Nom.
Max.
A
228
¾
244
B
150
¾
157
C
8
¾
12
C¢
335
¾
346
D
54
¾
60
E
¾
25
¾
F
4
¾
10
G
22
¾
28
H
7
¾
10
a
0°
¾
8°
43
December 22, 2008
HT82M9AEE/HT82M9AAE
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SSOP 20S (150mil), SSOP 24S (150mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330.0±1.0
B
Reel Inner Diameter
100.0±1.5
C
Spindle Hole Diameter
13.0+0.5/-0.2
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
Rev. 1.50
2.0±0.5
16.8+0.3/-0.2
22.2±0.2
44
December 22, 2008
HT82M9AEE/HT82M9AAE
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
P
B 0
K 0
A 0
R e e l H o le
IC p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .
SSOP 20S (150mil)
Symbol
W
Description
Dimensions in mm
16.0+0.3/-0.1
Carrier Tape Width
P
Cavity Pitch
E
Perforation Position
8.0±0.1
1.75±0.10
F
Cavity to Perforation (Width Direction)
D
Perforation Diameter
1.5+0.1/-0.0
D1
Cavity Hole Diameter
1.50+0.25/-0.00
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
6.5±0.1
B0
Cavity Width
9.0±0.1
K0
Cavity Depth
7.5±0.1
2.3±0.1
t
Carrier Tape Thickness
0.30±0.05
C
Cover Tape Width
13.3±0.1
SSOP 24S (150mil)
Symbol
Description
W
Carrier Tape Width
P
Cavity Pitch
Dimensions in mm
16.0+0.3/-0.1
8.0±0.1
E
Perforation Position
F
Cavity to Perforation (Width Direction)
7.5±0.1
D
Perforation Diameter
1.5+0.1
D1
Cavity Hole Diameter
1.50+0.25/-0.00
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
6.5±0.1
B0
Cavity Width
9.5±0.1
K0
Cavity Depth
2.1±0.1
1.75±0.10
t
Carrier Tape Thickness
0.30±0.05
C
Cover Tape Width
13.3±0.1
Rev. 1.50
45
December 22, 2008
HT82M9AEE/HT82M9AAE
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor (China) Inc. (Dongguan Sales Office)
Building No. 10, Xinzhu Court, (No. 1 Headquarters), 4 Cuizhu Road, Songshan Lake, Dongguan, China 523808
Tel: 86-769-2626-1300
Fax: 86-769-2626-1311
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2008 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.50
46
December 22, 2008