Abstract: Low resistance p-layers are achieved in this paper using a graphite cap to protect SiC
surface from out-diffusion of Si during high temperature post-implantation annealing, which is
carried out to maximize the activation of Al dopant in 4H-SiC. With a graphite layer converted from
photoresist, as high as 1700 and 1800oC post-implantation annealing is able to be used. Low RMS
roughness of surface after high temperature annealing shows the effectiveness of the graphite cap.
Small sheet resistance and resistivity are also achieved from the high temperature annealing. At room
temperature, sheet resistances of 9.8 and 1.3 k/□, and the corresponding resistivities of 235 and
31 m-cm are obtained from 1700 and 1800oC annealed samples, respectively. The Al ionization
energy extracted from Arrhenius plot is also close to the typical reported values. Therefore, it can be
concluded that, using graphite cap could help to activate the Al dopant effectively during high
temperature annealing.

Abstract: We present p-type doping of bulk SiC crystals by the modified physical vapor transport (M-PVT) technique using TMA (Tri-Methyl-Aluminum). Using TMA as a dopant precursor allows a quite well defined crystal growth process control. The issue of improvement of conductivity (reduction of substrate resistivity) by reduction of unintentional acceptor compensation by nitrogen is addressed. It is shown that a decrease of compensation from approx. 3%...10% to approx. 0.5%...2.5% leads to a charge carrier mobility and, hence, conductivity increase of about factor two.

Abstract: From a viewpoint of device application using p-channel SiC MOSFETs, control of their
channel properties is of great importance. We aimed to control the electrical properties of 4H-SiC
p-channel MOSFETs through locating the p-type epitaxial layer at the channel area, so called
“epi-channel MOSFET” structure. We varied the dopant concentrations and the thickness of the
epi-channel layer, and investigated their electrical properties. In case of heavily doped epi-channel
samples, the devices indicated “normally-on” characteristics, and their channel mobility decreased
slightly in comparison with the inversion-type devices. As for lightly doped epi-channel samples, the
subthreshold current increased with thickness of the epi-channel layer keeping their “normally-off”
characteristics. Their channel mobility also increased with thickness of the epi-channel layer. The
peak value of field effect channel mobility of the sample with 2.5 μm thickness and 5×1015 /cm3
dopant concentration epi-channel was 18.1 cm2/Vs.

Abstract: We developed normally-off 4H-SiC vertical junction field effect transistors (JFETs) with
large current density. The effect of forming an abrupt junction between the gate and the channel was
simulated, and vertical JFETs were then fabricated with abrupt junctions. As a result, a large rated
drain current density (500 A/cm2) and a low specific on-resistance (2.0 mWcm2) were achieved for
small devices. The blocking voltage was 600 V. These results were due to a reduction of the threshold
voltage by forming the abrupt junction between the gate and the channel.

Abstract: With the recent technological advances in 4H-SiC PiN diode fabrication, simulation tools which enable the accurate and rapid prediction of losses of such devices in power electronics circuits will be increasingly sought-after. To this end, a physical electro-thermal model of the 4H-SiC PiN diode has been developed, which facilitates device optimization for power circuit applications. The performance of this model has been compared with both finite element simulations and experimental results; good matching for both switching and conduction characteristics has been observed.