True Televisions have the CRT Tube !!
Welcome to the Obsolete Technology Tellye Web Museum. Here you will see a TV Museum showing many Old Tube Television sets
all with the CRT Tube, B/W ,color, Digital, and 100HZ Scan rate, Tubes technology. This is the opportunity on the WEB to see, one more time, what real technology WAS ! In the mean time watch some crappy lcd picture around shop centers (but don't buy them, or money lost, they're already broken when new) !!!

Richtige Fernseher haben Röhren!

Richtige Fernseher haben Röhren!

In Brief: On this site you will find pictures and information about some of the electronic, electrical and electrotechnical technology relics that the Frank Sharp Private museum has accumulated over the years .

Premise: There are lots of vintage electrical and electronic items that have not survived well or even completely disappeared and forgotten.

Or are not being collected nowadays in proportion to their significance or prevalence in their heyday, this is bad and the main part of the death land. The heavy, ugly sarcophagus; models with few endearing qualities, devices that have some over-riding disadvantage to ownership such as heavy weight,toxicity or inflated value when dismantled, tend to be under-represented by all but the most comprehensive collections and museums. They get relegated to the bottom of the wants list, derided as 'more trouble than they are worth', or just forgotten entirely. As a result, I started to notice gaps in the current representation of the history of electronic and electrical technology to the interested member of the public.

Following this idea around a bit, convinced me that a collection of the peculiar alone could not hope to survive on its own merits, but a museum that gave equal display space to the popular and the unpopular, would bring things to the attention of the average person that he has previously passed by or been shielded from. It's a matter of culture. From this, the Obsolete Technology Tellye Web Museum concept developed and all my other things too. It's an open platform for all electrical Electronic TV technology to have its few, but NOT last, moments of fame in a working, hand-on environment. We'll never own Colossus or Faraday's first transformer, but I can show things that you can't see at the Science Museum, and let you play with things that the Smithsonian can't allow people to touch, because my remit is different.

There was a society once that was the polar opposite of our disposable, junk society. A whole nation was built on the idea of placing quality before quantity in all things. The goal was not “more and newer,” but “better and higher" .This attitude was reflected not only in the manufacturing of material goods, but also in the realms of art and architecture, as well as in the social fabric of everyday life. The goal was for each new cohort of children to stand on a higher level than the preceding cohort: they were to be healthier, stronger, more intelligent, and more vibrant in every way.

The society that prioritized human, social and material quality is a Winner. Truly, it is the high point of all Western civilization. Consequently, its defeat meant the defeat of civilization itself.

Today, the West is headed for the abyss. For the ultimate fate of our disposable society is for that society itself to be disposed of. And this will happen sooner, rather than later.

OLD, but ORIGINAL, Well made, Funny, Not remotely controlled............. and not Made in CHINA.

How to use the site:

- If you landed here via any Search Engine, you will get what you searched for and you can search more using the search this blog feature provided by Google. You can visit more posts scrolling the left blog archive of all posts of the month/year,or you can click on the main photo-page to start from the main page. Doing so it starts from the most recent post to the older post simple clicking on the Older Post button on the bottom of each page after reading , post after post.

You can even visit all posts, time to time, when reaching the bottom end of each page and click on the Older Post button.

- If you arrived here at the main page via bookmark you can visit all the site scrolling the left blog archive of all posts of the month/year pointing were you want , or more simple You can even visit all blog posts, from newer to older, clicking at the end of each bottom page on the Older Post button.So you can see all the blog/site content surfing all pages in it.

- The search this blog feature provided by Google is a real search engine. If you're pointing particular things it will search IT for you; or you can place a brand name in the search query at your choice and visit all results page by page. It's useful since the content of the site is very large.

Note that if you don't find what you searched for, try it after a period of time; the site is a never ending job !

Every CRT Television saved let revive knowledge, thoughts, moments of the past life which will never return again.........

Many contemporary "televisions" (more correctly named as displays) would not have this level of staying power, many would ware out or require major services within just five years or less and of course, there is that perennial bug bear of planned obsolescence where components are deliberately designed to fail and, or manufactured with limited edition specificities..... and without considering........picture......sound........quality........

Sunday, September 2, 2012

MIVAR 20C1L CHASSIS 2568 + 2247 + 2260 INTERNAL VIEW.

The tellye has a frequency synthesized tuning system with direct selection of 99 Channels and
manual search functions.

And it started using the TDA3562A instead of the TDA3560

Left: Signal processing or small signal panel

Centre: Synchronization + Frame deflection output

Right: Power supply and line output + EHT.

On the bottom of the plastic cabinet there is the ST-BY supply unit.

--------------------------

TDA3562A VIDEO CHROMA IC

The TDA3562A is a monolithic IC designed as
decode PAL and/or NTSC colour television standards
and it combines all functions required for the
identification and demodulation of PAL and NTSC
signals.
.CHROMINANCE SIGNALPROCESSOR

THE PHILIPS TDA3562A Circuit arrangement for the control of a picture tube :

1. Circuit arrangement for the control of at least one beam current in a picture tube by a picture comprising
a control loop which in one sampling interval obtains a measuring
signal from the value of the beam current on the occurrence of a given
reference level in the picture signal, stores a control signal derived
therefrom until the next sampling interval and thereby adjusts the beam
current to a value preset by a reference signal.
and a trigger
circuit which suppresses auxiliary pulses used to generate the beam
current after the picture tube has been started up and issues a
switching signal for the purpose of closing the control loop during the
sampling intervals and for releasing the control of the beam current by
the picture signal after the measuring signal has exceeded the threshold
value,
a change detection arrangement which delivers a change
signal when the stored signal has assumed a largely constant value, and
a logic network which does not release the control of the beam current
by the picture signal outside the sampling intervals until the change
signal has also been issued after the switching signal.

2. Circuit arrangement as set forth in claim 1, in
which the picture signal comprises several color signals for the control
of a corresponding number of beam currents for the display of a color
picture in the picture tube and the control loop stores a part measuring
signal or a part control signal derived therefrom for each color
signal, characterized in that the change detection arrangement includes a
change detector for each color signal which delivers a part change
signal when the relevant stored signal has assumed a largely constant
value, and the logic network does not release the control of the beam
currents by the color signals outside the sampling intervals until the
part change signals have been delivered by all change detectors.

3. Circuit arrangement as set forth in claim 1,
including a comparator arrangement which compares the measuring signal
with the reference signal and derives the control signal from this
comparison, characterized in that the change detection arrangement
detects a change in the control signal with respect to time and issues
the change signal when the control signal has assumed a largely constant
value.

4. Circuit arrangement as set forth in claims 1, 2, 3
including a control signal memory which contains at least one
capacitor, characterized in that the change detection arrangement
delivers the change signal when a charge-reversing current of the
capacitor occuring during the starting up of the picture tube falls
below a limit value.

5. Circuit arrangement as set forth in claim 2,
including a comparator arrangement which compares the measuring signal
with the reference signal and derives the control signal from this
comparison, characterized in that the change detection arrangement
detects a change in the control signal with respect to time and issues
the change signal when the control signal has assumed a largely constant
value.

Description:

BACKGROUND OF THE INVENTION

The invention
relates to a circuit arrangement for the control of at least one beam
current in a picture tube by a picture signal with a control loop which
in one sampling interval obtains a measuring signal from the value of
the beam current on the occurrence of a given reference level in the
picture signal, stores a control signal derived therefrom until the next
sampling interval and by this means adjusts the beam current to a value
preset by a reference signal, and with a trigger circuit which
suppresses auxiliary pulses used to generate the beam current after the
picture tube is turned on and issues a switching signal for the purpose
of closing the control loop during the sampling intervals and releasing
the control of the beam current by the picture signal after the
measuring signal has exceeded a threshold value.
Such a circuit
arrangement has been described in Valvo Technische Information 820705
with regard to the integrated color decoder circuit PHILIPS TDA3562A and is
used in this as a so-called cut-off point control. In the known circuit
arrangement, such a cut-off point control provides automatic
compensation of the so-called cut-off point of the picture tube, i.e. it
regulates the beam current in the picture tube in such a way that for a
given reference level in the picture signal the beam current has a
constant value despite tolerances and changes with time (aging, thermal
modifications) in the picture tube and the circuit arrangement, thereby
ensuring correct picture reproduction.
Such a blocking point
control is particularly advantageous for the operation of a picture tube
for the display of color pictures because in this case there are
several beam currents for different color components of the color
picture which have to be in a fixed ratio with one another. If this
ratio changes, for example, as the result of manufacturing tolerances or
ageing processes, distortions of the colors occur in the reproduction
of the color picture. The beam currents, therefore, have to be very
accurately balanced. The said cut-off point control prevents expensive
adjustment and maintenance time which is otherwise necessary.
Conventional
picutre tubes are constructed as cathode-ray tubes with hot cathodes
which require a certain time after being turned on for the hot cathodes
to heat up. Not until a final operating temperature has been reached do
these hot cathodes emit the desired beam currents to the full extent,
while gradually rising beam currents occur in the time interval when the
hot cathodes are heating up. The instantaneous values of these beam
currents depend on the instantaneous temperatures of the hot cathodes
and on the accelerating voltages for the picture tube which build up
simultaneously with the heating process and are undefined until the end
of the heating time. After the picture tube is turned on, these values
initially produce a highly distorted picture until the beam currents
have attained their final value. These picture distortions after the
picture tube is turned on are even further intensified by the fact that
the cut-off point control is not yet adjusted to the beam currents which
flow after the heating time is over.
For the purpose of
suppressing distorted pictures during the heating time of the hot
cathodes, the known circuit arrangement has a turn-on delay element
operating as a trigger circuit which, in essence, contains a bistable
flip-flop. When the picture tube and the circuit arrangement controlling
the beam currents flowing in it are turned on, the flip-flop is
switched into a first state in which it interrupts the supply of the
picture signal to the picture tube. Thus, during the heating time the
beam currents are suppressed, and the picture tube does not yet display
any picture. In sampling intervals which are provided subsequent to
flybacks of the cathode beam into an initial position on the changeover
from the display of one picture to the display of a subsequent picture
and even within the changeover, that is outside the display of pictures,
the picture tube is controlled for a short time in such a way that beam
currents occur when the hot cathodes are sufficiently heated up and an
accelerating voltage is resent. If these currents exceed a certain
threshold value, the flip-flop circuit switches into a second state and
releases the picture signal for the control of the beam currents and the
cut-off point control.
It is found, however, that the picture
displayed in the picture tube immediately after the switching over of
the flip-flop is still not fault-free. Because, in fact, the beam
currents are supported during the heating time of the hot cathodes, the
cut-off point control cannot respond yet. This response of the cut-off
point control takes place only after the beam currents are switched on,
i.e. after the flip-flop is switched into the second state and therefore
at a time in which the picture signal already controls the beam
currents. In this way the response of the blocking point control makes
its presence felt in the picture displayed.
With the known
circuit arrangement the brightness of the picture gradually increases,
during the response of the cut-off point control, from black to the
final value.
This slow increase in the picture brightness after
the tube is turned on is disturbing to the eyes of the viewer not only
in the case of the black-and-white picture tubes with one hot cathode,
but especially so in the case of colour picture tubes which usually have
three hot cathodes. With a color picture tube, color purity errors can
also occur in addition to the change in the picture brightness if, as a
result of different speeds of response of the cut-off point control for
the three beam currents, there are found to be intermittent variations
from the interrelation between the beam currents required for a correct
picture reproduction.

SUMMARY OF THE INVENTION
The
aim of the invention is to create a circuit arrangement which
suppresses the above-described disturbances of brightness and color of
the displayed picture when the picture tube is being started.
The
invention achieves this aim in that a circuit arrangement of the type
mentioned in the preamble contains a change detection arrangement which
emits a change signal when the stored signal has assumed an essentially
constant value, and a logic network which does not release the control
of the beam current by the picture signal until the change signal has
also been emitted after the switching signal.
In the circuit
arrangement according to the invention, therefore, the display of the
picture is suppressed after the picture tube is turned on until the
cut-off point control has responded. If the picture signal then starts
to control the beam current, a perfect picture is displayed immediately.
In this way, all the disturbances of the picture which affect the
viewer's pleasure are suppressed. The circuit arrangement of the
invention is of simple design and can be combined on one semiconductor
wafer with the existing picture signal processing circuits and also, for
example, with the known circuit arrangement for cut-off point control.
Such an integrated circuit arrangement not only requires very little
space on the semiconductor wafer, but also needs no additional external
leads. Thus the circuit arrangement of the invention can be arranged,
for example, in an integrated circuit which has precisely the same
external connections as known integrated circuits. This means that an
integrated circuit containing the circuit arrangement of the invention
can be directly incorporated in existing equipment without the need for
additional measures.
In one embodiment of the said circuit
arrangement, in which the picture signal contains several color signals
for the control of a corresponding number of beam currents for
representing a color picture in the picture tube and, for each color
signal, the control loop stores a part measuring signal or a part
control signal derived from it, the change detection arrangement
contains a change detector for each color signal which emits a part
change signal when the relevant stored signal has assumed an essentially
constant value, and the logic network does not release the control of
the beam currents by the color signals outside the sampling intervals
until the part change signals have been emitted from all change
detectors.
In principle, therefore, such a circuit arrangement
has three cut-off point controls for the three beam currents controlled
by the individual color signals. To reduce the cost of the circuitry,
the measuring stage is common to all the cut-off point controls, as in
the known circuit arrangement. All three beam currents are then measured
successively by this measuring stage. In this way, a part measuring
signal or a part control signal derived from it is obtained for each
beam current and is stored sesparately according to which of the beam
currents it belongs. Changes in the part measuring signal or part
control signal are detected for each beam current by one of the change
detectors each time. Each of these change detectors issues a part change
signal to the logic network. The latter does not release the control of
the beam currents by the picture signal outside the sampling intervals
until all the part change signals indicate that the part measuring
signal or the part control signal, as the case may be, remains constant.
This ensures that the cut-off point controls for the beam currents of
all color signals have responded when the picture appears in the picture
tube.
In a further embodiment of the circuit arrangement
according to the invention with a comparator arrangement which compares
the measuring signal with the reference signal and derives the control
signal from this comparison, the change detection arrangement detects a
change in the control signal with respect to time and issues the change
signal when the control signal has assumed an essentially constant
value. In the case of the representation of a color signal the
comparator arrangement derives several part control signals, whose
changes with time are detected by the change detectors, from a
corresponding comparison of the part measuring signals with the
reference signal. In this embodiment of the circuit arrangement of the
invention, preference is given to storage of only the control signal or
the part control signals for the purpose of controlling the beam
currents.
In another embodiment of the circuit arrangement of the
invention which includes a control signal memory which contains at
least one capacitor in which a charge or voltage corresponding to the
control signal is stored, the change detection arrangement issues the
change signal when a charge-reversing current of the capacitor occurring
during the turning on of the picture tube has fallen below a limit
value and has thus at least largely decayed. Such a detection of the
steady state of the cut-off point control is independent of the actual
magnitude of the control signal and therefore independent of, for
example, the level of the picture tube cut-off voltage, circuit
tolerances or ageing processes in the circuit arrangement or the picture
tube.

Detection of whether or not the charge-reversing current
exceeds the limit value is performed preferentially by a current
detector which is designed with a current mirror system which is
arranged in a supply line to a capacitor acting as a control signal
store. A current mirror arrangement of this kind supplies a current
which coincides very precisely with the charging current of the
capacitor. This current is then compared, preferably in a further device
contained in the change detection arrangement, with a current
representing a limit value or, after conversion into a voltage, with a
voltage representing the limit value. The change signal is obtained from
the result of this comparison.
On the other hand, digital
memories may also be used as control signal memories, especially when
the picture signal is supplied as a digital signal and the blocking
point control is constructed as a digital control loop. In such a case,
the comparator arrangement, the change detection arrangement and the
trigger circuit are also designed as digital circuits. Then, the change
detection arrangement advantageously forms the difference of the signals
stored in the control signal memory in two successive sampling
intervals and compares this with the limit value formed by a digital
value. If the difference falls short of the limit value, the change
signal is issued.

BRIEF DESCRIPTION OF THE DRAWINGS

An embodiment of the invention is described in greater detail below with the aid of the drawings in which:

FIG. 1 shows a block circuit diagram of the embodiment,
FIG. 2 shows a somewhat more detailed block circuit diagram of the embodiment,
FIG. 3 shows time-dependency diagrams of some signals occurring in the circuit diagram shown in FIG. 2, and
FIG. 4 shows a somewhat moredetailed block circuit diagram of a part of the circuit diagram shown in FIG. 2.

DETAILED DESCRIPTION OF THE INVENTION
FIG.
1 shows a block circuit diagram of a circuit arrangement to which a
picture signal is fed via a first input 1 of a combinatorial stage 2.
From the output 3 of the combinatorial stage 2 the picture signal is fed
to the picture signal input of a controllable amplifier 5 which at an
output 6 issues a current controlled by the picture signal. This current
is fed via a measuring stage 7 to a hot cathode 8 in a picture tube 9
and forms therein a beam current of a cathode ray by means of which a
picture defined by the picture signal is displayed on a fluorescent
screen of the picture tube 9.
The measuring stage 7 measures the
current fed to the hot cathode 8, i.e. the the beam current in the
picture tube 9, and at a measuring signal output 10, issues a measuring
signal corresponding to the magnitude of this current. This is fed to a
measuring signal input 11 of a comparator arrangement 12 to which a
reference signal is supplied at a reference signal input 13. In a
preferably periodically recurring sampling interval during the
occurrence of a given reference level in the picture signal, the
comparator arrangement 12 forms a control signal from the value of the
measuring signal fed to the measuring signal input 11 at this time, on
the one hand, and the reference signal, on the other, by means of
substraction and delivers this at a control signal output 14. From there
the control signal is fed to an input 15 of a control signal memory 16
and is stored in the latter. The control signal is fed via an output 17
of the control signal memory 16 to a second input 18 of combinatorial
stage 2 in which it is combined with the picture signal, e.g. added to
it.
The combinatorial stage 2, the controllable amplifier 5, the
measuring stage 7, the comparator arrangement 12 and the control signal
memory 16 form a control loop with which the beam current is guided
towards the reference signal in the sampling interval during the
occurrence of the reference level in the picture signal. For the
reference level, use is made in particular of a black level or a level
with small, fixed distance from the black level, i.e. a value in the
picture signal which produces a black or almost back picture area in the
displayed picture in the picture tube. In this case the control loop,
as described, forms a cut-off point control for the picture tube. If the
reference level is away from the black level, the control loop is also
designated as quasi-cut-off-point control.
The circuit
arrangement as shown in FIG. 1 also has a trigger circuit 19 to which
the measuring signal from the measuring signal output 10 of measuring
stage 7 is fed at a measuring signal input 20. When the circuit
arrangement and therefore the picture tube are turned on, the trigger
circuit 19 is set in a first state in which by means of a first
connection 21 it blocks the comparator arrangement 12 in such a way that
the latter delivers no control signal or a control signal with the
value zero at its control signal output 14. This prevents the control
signal memory 16 from storing undefined values for the control signal at
the moment of turning on or immediately thereafter.
The circuit
arrangement shown in FIG. 1 also has a logic network 22 which is
connected via a second connection 23, by means of which a switching
signal is supplied, with the trigger circuit 10 and via a third
connection 24 with the controllable amplifier 5. Like the trigger
circuit 19, the logic network 22 also finds itself controlled, when the
circuit arrangement is being turned on, by the switching signal in a
first stage in which by way of the third connection 24 it blocks the
controllable amplifier 5 with a blocking signal in such a way that no
beam currents controlled by the picture signal can yet flow in the
picture tube 9. Thus the picture tube 9 is blanked; no picture is
displayed yet.
When picture tube 9 is turned on, the hot cathode 8
is still cold so that no beam current can flow anyhow. The hot cathode 8
is then heated up and, after a certain time, begins gradually to emit
electrons as the result of which a cathode ray and therefore a beam
current can form. However, during the heating up of the hot cathode 8,
and because the cut-off point control has not yet responded, this would
be undefined and is therefore suppressed by the controllable amplifier
5. Only in time intervals which are provided immediately subsequent to
flybacks of the cathode rays into an initial position at the changeover
from the display of one image to that of a subsequent image, but even
before the start of the display of the subsequent image, the
controllable amplifier 5 delivers a voltage in the form of an auxiliary
pulse for a short time at its output 6, and when the hot cathode 8 in
the picture tube 9 is heated up sufficiently, this voltage produces a
beam current. The time interval for the delivery of this voltage is
selected in such a way that a cathode ray produced by its does not
produce a visible image in the picture tube 9, and coincides for example
with the sampling interval.
The measuring stage 7 measures the
short-time cathode current produced in the manner described and, at its
measuring signal output 10, delivers a corresponding measuring signal
which is passed via measuring signal output 20 to the trigger circuit
19. If the measuring signal exceeds a definite preset threshold value,
the trigger circuit 19 is switched into a second state in which it
releases the comparator arrangement 12 via the first connection 12 and,
by means of the second connection 23, uses the switching signal to also
bring the logic network 22 into a second state. The comparator
arrangement 12 now evaluates the measuring signal supplied to it via the
measuring signal input 11, i.e. it forms the control signal as the
difference between the measuring signal and the reference signal
supplied via the reference signal input 13. The control signal is
transferred via the control signal output 14 and the input 15 into the
control signal memory 16. It is subsequently fed via the output 17 of
the control signal memory 16 to the second input 18 of the combinatorial
stage 2 and is there combined with the picture signal at the first
input 1, e.g. is superimposed on it by addition. This superimposed
picture signal is fed to the picture signal input 4 of the controllable
amplifier 5 via the output 3 of the combinatorial stage 2. In the
second state of the logic network 22 the controllable amplifier 5 is
switched via the third connection 24 by the blocking signal in such a
way that the picture signal controls the beam currents only during the
sampling intervals and that, for the rest, no image appears yet in the
picture tube. The cut-off point control now gebins to respond, i.e. the
value of the control signal is changed by the control loop comprising
the combinatorial stage 2, the controllable amplifier 5, the measuring
stage 7, the comparator arrangement 12 and the control signal memory 16
until such time as the beam current in the picture tube 9 at the
blocking point or at a fixed level with respect to it is adjusted to a
value preset by the reference signal. For this purpose the sampling
interval, in which the picture signal controls the beam current via the
controllable amplifier 5 is selected in such a way that within it the
picture signal just assumes a value corresponding to the cut-off point
or to a fixed level with respect to it.

During the response of
the cut-off point control the control signal fed to the control signal
memory 16 changes continuously. Between the control signal output 14 of
the comparator arrangement 12 and the input 15 of the control signal
memory 16 is inserted a changed detection arrangement 25 which detects
the variations of the control signal. When the cut-off point control has
responded, i.e. the control signal has assumed a constant value, the
change detection arrangement 25 delivers a change signal at an output 26
which indicates that the steady stage of the cut-off point control is
achieved and the said signal is fed to a change signal input 27 of the
logic network 22. The logic network then switches into a third state in
which via the third connection 24 it enables the controllable amplifier 5
in such a way that the beam currents are now controlled without
restriction by the picture signal. Thus a correctly represented picture
appears in the picture tube 9.
A shadow-like representation of
individual constituents of the circuit arrangement in FIG. 1 is used to
indicate a modification by which this circuit arrangement is equipped
for the representation of color pictures in the picture tube 9. For
example, three color signals are fed in this case as the picture signal
via the input 1 to the combinatorial stage 2. Accordingly, the input 1
is shown in triplicate, and the combinatorial stage 2 has a logic
element, e.g. an adder, for example of these color signals. The
controllable amplifier 5 now has three amplifier stages, one for each of
the color signals, and the picture tube now contains three hot cathodes
8 instead of one so that three independent cathode rays are available
for the three color signals. However, to simplify the circuit
arrangement and to save on components, only one measuring stage 7 is
provided which measures all three beam currents successively. Also, the
comparator arrangement 12 forms part control signals from the
successively arriving part measuring signals for the individual beam
currents with the reference signal, and these part control signals are
allocated to the individual color signals and passed on to three storage
units which are contained in the control signal memory 16. From there,
the part control signals are sent via the second input 18 of the
combinatorial stage 2 to the assigned logic elements.
The circuit
arrangement thus forms three independently acting control loops for the
cut-off point control of the individual color signals, in which case
only the measuring stage 7 and to some extent at least the comparator
arrangement 12 are common to these control loops.
The change
detection arrangement 25 now has three change detectors each of which
detects the changes with time of the part control signals relating to a
color signal. Then via the output 26 each of these change detectors
delivers a part change signal to the change signal input 27 of the logic
network 22. These part change signals occur independently of one
another when the relevent control loop has responded. The logic network
22 evaluates all three part change signals and does not switch into its
third stage until all part change signals indicate a steady state of the
control loops. Only then, in fact, is it ensured that all the color
signals from the beam currents controlled by them are correctly
reproduced in the picture tube, and thus no distortions of the displayed
image, especially no color purity errors, occur. The color picture
displayed then immediately has the correct brightness and color on its
appearance when the picture tube is turned on.

FIG. 2 shows a
somewhat more detailed block circuit diagram of an embodiment of a
circuit arrangement equipped for the processing of a picture signal
containing three colour signals. Three color signals for the
representation of the colors red, green and blue are fed to this circuit
arrangement via three input terminals 101, 102, 103. A red color signal
is fed via the first input terminal 101 to a first adder 201, a green
colour signal is fed via the second input terminal to a second adder
202, and a blue colour signal is fed via the third input terminal 103 to
a third adder 203. From outputs 301, 302 and 303 of the adders 201,
202, 203 the color signals are fed to amplifier stages 501, 502 and 503
respectively. Each of the amplifier stages contains a switchable
amplifier 511, 512 and 513, an output amplifier 521, 522 and 523 as well
as a measuring transistor 531, 532 and 533 respectively. The emitters
of these measuring transistors 531, 532, 533 are each connected to a hot
cathode 801, 802, 803 of the picture tube 9 and deliver the cathode
currents, whereas the collectors of measuring transistors 521, 532, 533
are connected to one another and to a first terminal 701 of a measuring
resistor 702 the second terminal of which 703 is connected to earth. The
current gain of the measuring transistors 531, 532 and 533 is so great
that their collector currents coincide almost with the cathode currents.
By measuring the voltage drop produced by the cathode currents at the
measuring resistor 802 it is then possible to measure the cathode
currents and therefore the beam currents in the picture tube 9 with
great accuracy.
The falling voltage at the measuring resistor 702
is fed as a measuring signal to an input 121 of a buffer amplifier 120
with a gain factor of one, at the output 122 of which the unchanged
measuring signal is therefore available at low impedance. From there it
is fed to a first terminal 131 of a reference voltage source 130 which
is connected with its second terminal 132 to inverting inputs 111, 112
and 113 of three differential amplifiers 123, 124, 125 respectively. The
differential amplifiers 123, 124, 125 also each have a non-inverting
input 114, 115, and 116 respectively. These are connected to each other
at a junction 117, to earth via a leakage current storage capacitor 126
and to the output 122 of the buffer amplifier 120 via decoupling
resistor 118 and a leakage current sampling switch 119. In addition, the
input 121 of the buffer amplifier 120 can be connected to earth via a
short-circuiting switch 127.

From outputs 141, 142, and 143
respectively of the differential amplifiers 123, 124 and 125, part
control signals relating to the individual color signals are fed in the
form of electrical voltages (or, in some cases, charge-reversing
currents) via control signal sampling switches 154, 155 and 156, in the
one instance, to first terminals 151, 152 and 153 respectively of
control signal storage capacitors 161, 162, 163 which form the storage
units of the control signal memory 16 and store inside them charges
corresponding to these voltages (or formed by the charge-reversing
currents). In the other instance, the part control signals are fed to
second inputs 181, 182 and 183 of the first, second or third adders 201,
202, 203 respectively and are added therein to the color signals from
the first, second or third input terminals 101, 102 or 103 respectively.

The operation of the comparator arrangement 12 which consists
mainly of the buffer amplifier 120, the reference voltage source 130 and
differential amplifiers 123, 124, 125 will be explained below with the
aid of the pulse diagrams in FIG. 3. FIG. 3a shows a horizontal blanking
signal for a television signal which, as the picture signal, controls
the beam currents in the picture tube 9. In this diagram, H represents
horizontal blanking pulses which follow one another in the picture
signal at the time interval of one line duration and by means of which
the beam currents are switched off during line flyback between the
display of the individual picture lines in the picture tube. FIG. 3b
shows a vertical blanking pulse V by means of which the beam currents
are switched off during the change ober from the display of one picture
to the display of the next picture. FIG. 3c shows a measuring signal
control pulse VH which is formed from a vertical blanking pulse
lengthened by three line duration.
The short-circuiting switch
127 is now controlled in such a way that it is non-conducting only
throughout the duration of the measuring signal control pulse VH and
during the remaining time short-circuits the input 121 of the buffer
amplifier 120 to earth. This means that a measuring signal only reaches
the comparator arrangement 12 during frame change so that the parts of
the picture signal which control the beam currents producing the picture
in the picture tube exert no influence on comparator arrangement 12 and
therefore on the blocking point control.

Throughout the duration
of the measuring signal control pulse VH, the measuring signal from
output 122, reduced by a reference voltage issued by the reference
voltage source 130 between its first 131 and its second terminal 132, is
present at the inverting inputs 111, 112, 113 of differential
amplifiers 123, 124, 125. If the differential amplifiers 123, 124, 125
were not present, this difference would be fed directly as part control
signals to the control signal storage capacitors 161, 162, 162. The
differential amplifiers 123, 124, 125 amplify the difference and thus
form the control amplifiers of the control loops.
The comparator
arrangement 12 further contains a device for compensation of the
influence of any leakage currents occurring in the picture tube 9. For
this purpose, a voltage to which the leakage current storage capacitor
126 is charged is fed to the non-inverting inputs 114, 115, 116 of the
three differential amplifiers 123, 124 and 125. The charging is
performed by the measuring signal from output 122 of the buffer
amplifier 120 via the decoupling resistor 118 and the leakage current
sampling switch 119 which is closed only within the period of the
vertical blanking pulse V, and in certain cases only during part of the
latter. Within this time the beam currents are, in fact, totally
switched off by the picture signal so that in certain cases only a
leakage current flows through the measuring resistor 702. Consequently,
throughout the duration of the vertical blanking pulse V the measuring
signal corresponds to this leakage current. Because the leakage current
also flows during the remaining time, even outside the duration of the
vertical blanking pulse the measuring signal contains a component
originating from the leakage current which therefore is also contained
in the voltage fed to the inverting inputs 111, 112, 113 of differential
amplifiers 123, 124, 125 and is subtracted out in the differential
amplifiers 123, 124, 125.
The part control signal is fed from
output 141 of differential amplifier 123 by the first control signal
sampling switch 154 to the first terminal 151 of the first control
signal storage capacitor 161 during the period of a storage pulse L1 and
is stored in the said capacitor. Similarly, the part control signal
from output 143 of differential amplifier 125 is fed to the third
control signal storage capacitor 163 during the period of a storage
pulse L2 and the part control signal from output 142 of differential
amplifier 124 is fed to the second control signal storage capacitor 162
during a storage pulse L3. The storage pulses L1, L2 and L3 are
illustrated in FIGS. 3d, e and f. They lie in sequence in one of the
three line periods by which the measuring signal control pulse VH is
longer than the vertical blanking pulse V. These three line periods form
the sampling interval for the measuring signal or the part measuring
signals, as the case may be. During the remaining periods the outputs,
141, 152, 143 of the differential amplifiers 123, 124, 125 are isolated
from the control signal storage capacitors 161, 162, 163 so that no
interference can be transmitted from there and any distortion of the
stored part control signals caused thereby is eliminated. For the
duration of storage pulses L1, L2 and L3 the color signals at the input
terminals 101, 102, 103 are at their reference level i.e. in the present
embodiment at a level, corresponding to the blocking point or at a
fixed level with respect to it so that the control loops can adjust to
this level.

The switchable amplifiers 511, 512, and 513 each
receive at each input 241, 242, 243 a blanking signal BL1, BL2, BL3
respectively, the curves of which are shown in FIGS. 3g, h, i. These
blanking signals interrupt the supply of the color signals during line
flybacks and frame change, i.e. during the period of the measuring
signal control pulse VH, and thus the beam currents in these time
intervals are switched off. Naturally, the red color signal is let
through during the first line period after the end of the vertical
blanking pulse V, the blue color signal during the second line period
after the end of the vertical blanking pulse V and the green color
signal during the third line period after the end of the vertical
blanking pulse V by the switchable amplifiers 511, 512, 513 respectively
so that they can control the beam currents. Blanking signals BL1, BL2
and BL3 also provide for interruptions in the frame change blanking
pulse, which corresponds to the measuring signal control pulse, in the
corresponding time intervals. In these time intervals the beam currents
are measured and part control signals are determined from the part
measuring signals and stored in the control signal storage capacitors
161, 162, 163.

The circuit arrangement shown in FIG. 2 further
contains a trigger circuit 19 to which a supply voltage is fed via a
supply terminal 190. Via a reset input 191 a voltage is also supplied to
the trigger circuit 19 from a third terminal 133 of the reference
voltage source 130. When the circuit arrangement is turned on, this
voltage is designed so as to be delayed with respect to the supply
voltage so that when the circuit arrangement is brought into operation
the interplay of the two voltages produces a switch-on reset signal such
that a low-value voltage pulse occurs at the reset input 191 during
turn on, which means that the trigger circuit 19 is set in its first
state. The reset input 191 can also be connected to another circuit of
any configuration which generates a switch-on reset signal when the
picture tube is turned on.
The trigger circuit 19 is further
connected via a second connection 23 to a logic network 22 which, when
the circuit arrangement is turned on, is also set into a first state via
the second connection 23. In this first state the logic network 22
delivers a blocking signal at a blocking output 240 which is fed to the
three switchable amplifiers 511, 512, 513. By this means the supply of
the color signals to the output amplifiers 521, 522, 523 is interrupted
completely so that no beam currents can be generated by these. No
picture is therefore displayed.

An insertion signal EL which
extends over the three line periods by which the measuring signal
control pulse VH is longer than the vertical blanking pulse V, i.e. over
the sampling interval, is also fed via a line 233 to the trigger
circuit 19 and the logic network 22. As long as the trigger circuit 19
is in its first state, this insertion pulse EL is issued via a control
output 192 from the trigger circuit 19 and fed to the pulse generator
244. During the period of the insertion pulse EL this generator produces
a voltage pulse of a definite magnitude and passes this to output
amplfiiers 521, 522, 523 as an auxiliary pulse via switching diodes 245,
246, 247. By this means the beam currents are switched on for a short
time so as to receive a measuring signal despite the disconnected color
signals as soon as at least one of the hot cathodes 801, 802, 803
delivers a beam current.
In its first state the trigger circuit
19 also delivers a signal via a control line 211, and this signal is
used to switch the outputs 141, 142, 143 of the differential amplifiers
123, 124, 125 to earth potential or practically to earth potential. This
suppresses effects of voltages at the inputs 111 to 116 of the
differential amplifiers 123, 124, 125, especially effects of the
reference voltage source 130 which may in some cases initiate incorrect
charging of the control signal storage capacitors 161, 162, 163.
The
measuring signal produced by means of the pulse generator 244 at the
input 121 of the buffer amplifier 120 is also fed to the trigger circuit
19 via a measuring signal input 20. If it exceeds a preset threshold
value, the trigger circuit 19 switched into its second state. The logic
network 22 is then also switched into its second state via the second
connection 23. The differential amplifiers 123, 124, 125, too, are
triggered by the signal along the control line 211 into issuing a
control signal defined by the difference in the voltages at its inputs
111 to 116. The pulse generator 244 is blocked by the control output
192. The blocking signal issued from the blocking output 240 of the
logic network 22 now turns on the switchable amplifiers 511, 512, 513 in
the time intervals defined by the storage pulses L1, L2, L3 in such a
way that in these time intervals the color signals can produce beam
currents to form a measuring signal by which the control loops respond.
However, the display of the picture is still suppressed. The control
signal storage capacitors 161, 162, 163 are charged up in this process.
In the leads to the first terminals 151, 152, 153 there are change
detectors 251, 252, 253 which detect the changes of the charging
currents of the control signal storage capacitors 161, 162, 163 and at
their outputs 261, 262, 263 in each case deliver a part change signal
when the charging current of the control signal storage capacitor in
question has decayed and thus the relevant control loop has responded.
The part change signals are fed to three terminals 271, 272, 273 of the
change signal input 27 of the logic network 22.
When part change
signals are present from all change detectors 251, 252, 253, when
therefore all control loops have responded, the logic network 22
switches from its second to its third state. The blocking signal from
the blocking output 240 is now completely disconnected such that the
switchable amplifiers 511, 512, 513 are now switched only by the
blanking signals BL1, BL2, BL3. The colour signals are then switched
through to the output amplifiers 521, 522, 523 and the picture is
displayed in the picture tube.

FIG. 4 shows an embodiment for a
trigger circuit 19 and a logic network 22 of the circuit arrangements as
shown in FIGS. 1 or 2. The trigger circuit 19 contains a flip-flop
circuit formed from two NAND-gates 194, 195 to which the switch-on reset
signal, by which the trigger circuit 19 is returned to its first stage,
is fed via the reset input 191. All the elements of the circuit
arrangement in FIG. 4 are shown in positive logic. Thus, a short-time
low voltage at the reset input 191 immediately after the circuit
arrangement is started up is used to set the flip-flop circuit 194, 195
in such a way that a high voltage occurs at the output of the second
NAND gate 194 and a low voltage at the output of the second NAND gate
195. The low voltage at the output of the second NAND gate 195 blocks
differential amplifiers 123, 124, 125 via the control line 211 in the
manner described.
The insertion pulse EL is fed via the line 233
to the trigger circuit 19, is combined via an AND gate 196 with the
signal from the output of the first NAND gate 194 and is delivered at
the control output 192 for the purpose of controlling the pulse
generator 244.
The signals from the outputs of the NAND-gates
194, 195 are fed via a first line 231 and a second line 232 of the
second connection 23 as a switching signal to the logic network 22. The
first line 231 is connected to reset inputs R of three part change
signal memories 221, 222, 223 in the form of bistable flip-flop circuits
which when the circuit arrangement is started up are reset via the
first line 231 in such a way that they carry a low voltage at their
outputs Q. The second line 232 of the second connection 23 leads via
three AND gates 224, 225, 226 to setting inputs S of the three part
change signal memories 221, 222, 223. By means of the AND gates 224,
225, 226 the signal on the second line 232 of the second connection 23
is combined each time with one of the part change signals supplied via
the terminals 271, 272, 273. The signals from the outputs Q of the part
change signal memories 221, 222, 223 are combined by means of a
collecting gate 227 in the form of an NAND gate and are held ready at
its output 228.
The measuring signal is fed to the trigger
circuit 19 via the measuring signal input 20 and passed to a first input
197 of a threshold detector 198 to which at a second input a threshold
value, in the form of a threshold voltage for example, produced by a
threshold generator 199 is also supplied. When the voltage at the first
input 197 of the threshold detector 198 is smaller than the voltage
delivered by the threshold generator 199, the threshold detector 198
delivers a high voltage at its output 200. When, on the other hand, the
voltage at the first input 197 is greater than the voltage of the
threshold generator 199, the voltage at the output 200 jumps to a low
value. This voltage is supplied as the setting signal of the flip-flop
circuit 194, 195, reverses the latter and thereby switches the trigger
circuit 19 into its second state when the voltage at the first input 197
exceeds the voltage of the threshold generator 199.
Between the
output 200 and the flip-flop circuit 194, 195 in the circuit arrangement
shown in FIG. 4 there is inserted an inquiry gate 181 in the form of an
OR gate to which an inquiry pulse is fed via an inquiry input 193 of
the trigger circuit 19. This ensures that the flip-flop circuit 194, 195
is switched over only at a time fixed by the inquiry pulse--in the
present case a negative voltage pulse--and not at any other times due to
disturbances. As such an inquiry pulse it is possible to use, for
example, a pulse which occurs in the second line period after the end of
the vertical blanking pulse V, i.e. one which largely corresponds to
the storage pulse L2.
After the switching over of the flip-flop
circuit 194, 195 corresponding to the setting of the trigger circuit 19
into the second state, appropriately modified signals are supplied via
the control line 211 and the output 192 for the purpose of controlling
the pulse generator 244 and the differential amplifiers 123, 124, 125.
Modified voltages also appear on the lines 231, 232 of the second
connection 23, and these voltages release the part change signal
memories 221, 222, 223 such that they can each be set when the part
change signals reach the terminals 271, 272, 273.
In certain
cases, a further flip-flop circuit 234 is inserted in the lines 231, 232
to delay the signals passing along these lines; this is reset via the
first line 231 when the circuit arrangement is started up and thus it
also resets the part change signal memories 221, 222, 223. However,
after the trigger circuit 19 is switched into the second state the
further flip-flop circuit 234 is not set via the second line 232 of the
second connection 23 until a release pulse arrives via a release input
235 and another AND gate 236, for example a period of approximately the
interval of two vertical blanking pulses V after the switching of the
trigger circuit 19 into the second state. In this way it is possible to
bridge a period of time in which no defined signal values are present at
the terminals 271, 272, 273.
The signal at the output 228 of the
collecting gate 227 changes its state when the last of the three part
change signals has also arrived and has set the last of the three part
change signal memories. The signal is then combined via a gate
arrangement 229 of two NAND gates and one AND gate with the insertion
pulse EL of line 223 and with the signal on the second line 232 of the
second connection 23 or from the output Q of the further flip-flop
circuit 234 to the blocking signal delivered at the blocking output 24
which is fed to the switchable amplifiers 511, 512, 513.

FIGS.
31, m, n show the combinations of the blocking signal with the blanking
signals BL1, BL2, and BL3 at the blanking inputs 241, 242, 243 of the
switchable amplifiers 511, 512, 513 in the form of logic AND operations.
The dot-dash lines show resulting insertion signals A1, A2, A3 formed
by these operations after the starting up of the circuit arrangement and
before the occurrence of a beam current, i.e. in the first state of the
logic network 22. Here the resulting insertion signals A1, A2, A3 are
constant at low level. The dash curves show the resulting insertion
signals A1, A2, A3 after the appearance of a beam current and before the
steady state of the cut-off point control is reached, i.e. in the
second state of the logic network 22, while the continuous curves
represent the resulting insertion signals A1, A2, A3 in the steady state
of the cut-off point control, i.e. in the third state of logic network
22. The dash curves have similar shapes to storage pulses L1, L2, L3,
whereas the continuous curves correspond in shape to the inverses of the
blanking signals BL1, BL2, BL3. In this case a high level of the
resulting insertion signals A1, A2 or A3 means that the switchable
amplifier 511, 512 or 513 feeds the colour signal to the relevant output
amplifier 521, 522 or 523 respectively, whereas a low level in the
resulting insertion signal A1, A2 or A3 means that the relevant
switchable amplifier 511, 512 or 513 is blocked for the color signal.
The
circuit arrangement described is designed in such a way that the
trigger circuit 19 remains in its second state and logic network 22
remains in its third state even if charging currents reappear at the
difference signal storage cpacitors 161, 162, 163 due to disturbances
during the operation of the circuit arrangement. The cutoff point
control then makes readjustments without the displayed picture being
disturbed.
In the circuit arrangement shown in FIG. 2, the green
color signal can also be let through during the second line period after
the end of the vertical blanking pulse V and the blue color signal
during the third line period after the end of the vertical blanking
pulse V by the switchable amplifiers 511, 512, 513 for the purpose of
controlling the beam currents. The storage pulses L2 and L3 at the
control signal sampling switches 155 and 156 and the second and third
blanking signals BL2 and BL3 at the blanking inputs 242 and 243 are then
to be interchanged. The resulting insertion signals A2 and A3 as shown
in FIGS. 3m and n are also interchanged then accordingly.
In FIG.
2 a dashed line is used to indicate which components of the circuit
arrangement can be combined advantageously to form an integrated
circuit. The first terminals 151, 152, 153 of the difference signal
storage capacitors 161, 162, 163, one terminal 128 of leakage current
storage capacitor 126, three terminals 524, 525, 526 in the leads to the
output amplifiers 521, 522, 523 as well as a line connection 704
between the first terminal 701 of the measuring resistor 702 and the
input 121 of the buffer amplifier 120 will then form the connecting
contacts of this integrated circuit

-------------------------------------

TDA1180P TV HORIZONTAL PROCESSOR

DESCRIPTION
The TDA1180P is a horizontal processor circuit for
b.w. and colour monitors. It is a monolithic integrated
circuit encapsulated in 16-lead dual in-line
plastic package.

APPLICATION INFORMATION
Pin 1 - Positive supply
The operating supply voltage of the device ranges
from 10V to 13.2V
Pin 2 and 3 - Output
The outputs of TDA1180P are suitable for driving
transistor output stages, they deliver positive pulse
at Pin 3 and negative pulse at Pin 2.
The negative pulse is used for direct driving of the
output stage, while positive pulse is useful when a
driver stage is required.
The rise and fall times of the output pulses are
about 150 ns so that interference due to radiation
are avoided.
Furthermore the output stages are internally protected
against short circuit.
Pin 4 - Protection circuit input
By connecting Pin 4 of the IC to earth the output
pulses at Pin 2 and 3 are shut off ; this function has
been introduced to produced to protect the final
stages from overloads.
The same pulses are also shut off when the supply
voltage falls below 4V.
Pin 5 - Phase shifter filter
To compensate for the delay introduced by the line
final stages, the flyback pulses to Pin 6 and the
oscillator waveform are compared in the oscillatorflyback
pulse phase comparator.
The result of the comparison is a control current
which, after it has been filtered by the external
capacitor connected to Pin 5, is sent to a phase
shifter which adequately regulates the phase of the
output pulses.
The maximum phase shift allowed is: td = tp - tf
where tf is the flyback pulse duration.
Pin 5 has high input and output resistance (current
generator).
Pin 6 - Flyback input
The flyback pulse drives the high impedance input
through a resistor in order to limit the input current
to suitable maximum values.
The flyback input pulses are processed by a double
threshold circuit; this generates the blanking pulses
by sensing low level flyback voltage and the pulses
to drive the phase comparator by sensing high level
flyback voltage, therefore phase jitter caused by
ringing normally associated with the flyback pulse,
is avoided.
Pin 7 - Key and blanking pulse output
The key pulse for taking out the burst from the
chrominance signal is generated from the oscillator
ramp and has therefore a fixed phase position with
respect to the sync.
The key pulse is then added internally to the blanking
pulse obtained by correctly forming the flyback
pulse present at Pin 6.
The sum of the two signals (sandcastle pulse) is
available on low impedance at output Pin 7.

Pin 8 and 9 - Sync separators inputs
The video signal is applied by means of two distinct
biasing networks to pins 8 and 9 of the IC and
therefore to the respective vertical and horizontal
sync separators.
The latter take the sync pulses out of the video
signal and make them available to the rest of the
circuit for further processing.

Pin 10 - Vertical sync output
The vertical sync pulse, obtained by internal integration
of the synchronizing signal, is available at
this pin.
The output impedance is typically 10kW and the
lowest amplitude without load is 11V.
Pin 11 - Coincidence detector
From the oscillator waveform a gate pulse 7 ms
wide is taken whose phase position is centered on
the horizontal synchronism.
The gate pulse not only controls a logic block which
permits the sync to reach the oscillator-sync phase
comparator only for as long as its duration, but also
allows the latching and de-latching conditions of
the oscillator to be established.This function is
obtained by a coincidence detector which compares
the phase of the gate pulses with that of the
sync.
When the two signals are not accurately aligned in
time it means that the oscillator is not synchronized.
In this case the detector acts on the logic block to
eliminate its filtering effect and on the time constant
switching block to establish a high impedance on
Pin 12 (small time constant of low-pass filter).
This latter block also acts on the oscillator-sync
phase detector to increase its sensitivity and with it
the loop gain of the synchronizing system.
In this conditions the phase lock has low noise
immunity (wide equivalent noise bandwidth) and
rapid pull-in time which allows fairly short synchronization
times.
Once locking has taken place the coincidence detector
enables the logic block, causes a low impedance
on Pin 12 and reduces the sensitivity of the
phase comparator.
In these conditions the phase lock has high noise
immunity ( narrow equivalent noise bandwidth) due
to the complete elimination of interference which
occurs during the scanning period and the greater
inertia with which the oscillator can change its
frequency.
To optimize the behaviour of the IC if a video
recorder is used, the state of the detector can be
forced by connecting Pin 11 to earth or to + VS. The
characteristics of the phase lock thus correspond
to the lack of synchronization.
Pin 12 - Time constant switch, (see Pin 11)
Pin 13 - Control current output
The oscillator is synchronized by comparing the
phase of its waveform with that of the sync pulses
in the oscillator-sync phase comparator and sending
its output current I13 (proportional to the phase
difference between the two signals) to Pin 15 of the
oscillator after it has been filtered properly with an
external low-pass circuit.
The time constant of the filter can be switched
between two values according to the impedance
presented by Pin 12.
The voltage limiter at the output of the phase
comparator limits the voltage excursion on Pin 13
and therefore the frequency range in which the
oscillator remains held-in.
The output resistance of Pin 13 is:
l low when V13 > 4.3 or V13 < 1.6V
l high when 1.6V < V13 < 4.3V
To prevent the vertical sync from reaching the
oscillator-sync phase comparator along with the
horizontal sync,a signal which inhibits the phase
detector during the vertical interval is taken from
the vertical output stage; inhibition remain even if
the video signal is not present.
The free running frequenc of the oscillator is determined
by the values of the capacitor and of the
resistor connected to Pins 14 and 15 respectively.
To generate the line frequency output pulses, two
theresholds are fixed along the fall ramp of the
triangular waveform of the oscillator.
Pin14 - Oscillator (see Pin 13)
Pin 15 - Oscillator control current input (see
Pin 13)
Pin 16 - Ground

GENERAL DESCRIPTION f The TDA1170 and TDA1270 are monolithic integratedcircuits designed for use in TV vertical deflection systems. They are manufactured usingthe Fairchild Planar* process.Both devices are supplied in the 12-pin plastic power package with the heat sink fins bentfor insertion into the printed circuit board.The TDA1170 is designed primarily for large and small screen black and white TVreceivers and industrial TV monitors. The TDA1270 is designed primarily for drivingcomplementary vertical deflection output stages in color TV receivers and industrialmonitors.

APPLICATION INFORMATION (TDA1170)The vertical oscillator is directly synchronized by the sync pulses (positive or negative); therefore its freerunning frequency must be lower than the sync frequency. The use of current feedback causes the yokecurrent to be independent of yoke resistance variations due to thermal effects, Therefore no thermistor isrequired in series with the yoke. The flyback generator applies a voltage, about twice the supply voltage, tothe yoke. This produces a short flyback time together with a high useful power to dissipated powerratio.

Circuit arrangement for generating a sawtooth deflection current through a line deflection coil:
1. Circuit arrangement for generating a sawtooth deflection current flowing through a line deflection coil in an image display apparatus, which circuit arrangement comprises a deflection network including trace and retrace capacitor means coupling to said coil, and a first diode coupled to said retrace capacitor through which the deflection current flows during part of the trace interval, means for conveying the deflection current during the remainder of the trace interval including a second diode and a controllable switch coupled to said diode, said switch and second diode together being coupled in parallel with the first diode, the circuit arrangement further comprising an inductive element coupled to the switch, a third diode coupled to the deflection network and to said inductive element, a transformer having a core of a magnetic material and a winding, and a capacitor coupled to said winding and to the deflection network, characterized in that the inductive element is coupled via the third diode to the series combination of the above-mentioned series capacitor and part of the transformer winding less than all of said winding.

2. Circuit arrangement as claimed in claim 1, in which the inductive element comprises a winding, characterized in that the winding of the inductive element is wound on the transformer core.

3. Circuit arrangement as claimed in claim 1, characterized in that a first capacitor is coupled in parallel with the said part of the transformer winding and a second capacitor is coupled in parallel with the remainder of the winding, the ratio between the reactances of the said capacitors being equal to the ratio between the number of turns of the said parts of the winding.

4. Circuit arrangement as claimed in claim 1 in which the inductive element has a primary winding and a secondary winding which are coupled with one another, characterized in that the ratio of the number of turns of the secondary winding to that of the primary winding is substantially equal to ##EQU19## where m is the ratio of the turns number of the part of the transformer winding between the connection to the third diode and the series capacitor to the turns number of the entire winding, α is the ratio of the amplitude of the retrace voltage to the trace voltage, and δmax is the value of that ratio of the conduction time of the switch to the line period which is associated with the maximum value of a voltage supply source which supplies energy to the circuit arrangement.

5. A circuit arrangement as claimed in claim 1 wherein said core has two limbs, a tapped transformer winding and at least one high-voltage winding wound on one limb, a primary winding and a secondary winding wound on the other limb, the ratio of the number of turns of the secondary winding to that of the primary winding being greater than the ratio of the number of turns of the part of the transformer winding between the tapping and an end adapted to be connected to a series capacitor to the number of turns of the entire winding and being less than 1.

Description:

The invention relates to a circuit arrangement for generating a sawtooth deflection current through a line deflection coil in an image display apparatus, which circuit arrangement comprises a deflection network including the deflection coil, a trace capacitor and a retrace capacitor and a first diode through which the deflection current flows during part of the trace interval whilst during the remainder of the trace interval this current flows through a second diode and a controllable switch, which switch and which second diode are connected in parallel with the first diode, the circuit arrangement further comprising an inductive element which is connected to the switch and is coupled to the deflection network via a third diode, and a transformer which has a core of a magnetic material and a winding of which is coupled, in series with a capacitor, to the deflection network.
Such a circuit arrangement is described in "IEEE Transactions on Broadcast and Television Receivers," August 1972, volume BTR-18, Nr. 3, pages 177 to 182, and is a combination of a line deflection circuit and a switched-mode supply voltage stabilizing circuit, the controllable switch being used to perform both the said functions. This known circuit arrangement has the advantage that it can be fed with an unstabilised supply voltage and is capable of supplying a satisfactorily stabilized deflection current, a stabilized high voltage and, if desired, auxiliary voltages, the stabilization being obtained by control of the conduction time of the swtich.
When such a circuit arrangement is to be designed, amongst other problems the three following ones arise. Firstly care must be taken to ensure that the maximum voltage set up across the switch (a transistor) during the retrace interval does not exceed the permissible limit value for this element. Secondly the variation of the conduction time of the transistor must be capable of accommodating the supply voltage variations to be expected. Thirdly the (stabilized) trace capacitor voltage applied to the deflection coil during the trace interval must be selectable at will, for with a given deflection coil this voltage determines the intensity of the deflection current produced.

The said problems are not independent of one another. If, for example, the trace voltage is low, the maximum collector voltage of the transistor also is low; it may be further reduced by making the conduction time of the transistor as short as possible. It will therefore be clear that several degrees of freedom are required. One degree of freedom is available to a certain extent, namely the transformation ratio between two windings of the inductive element, one winding being connected between a terminal of the supply voltage source and the junction point of the collector and the second diode, whilst the other winding, which is coupled to the first one, is connected to the third diode, for the choice of the said ratio enables a freer choice of the trace voltage. However, the two other problems, specifically that of maximum collector voltage, are not solved thereby.
It is an object of the present invention to provide a circuit arrangement having one more degree of freedom, permitting the maximum permissible collector voltage to be freely determined, and for this purpose the circuit arrangement according to the invention is characterized in that the inductive element is connected via the third diode to the series combination of the abovementioned series capacitor and part of the transformer winding.
The introduction of a new parameter not only enables the maximum collector voltage to be reduced without the trace voltage being affected but also proves to enable a larger range of supply voltage variations to be accommodated. Hence, the step according to the invention permits of designing a circuit arrangement in which conflicting requirements can simultaneously be satisfied.
In a possible embodiment in which the inductive element has a winding the circuit arrangement is characterized in that the winding of the inductive element is wound on the transformer core.
Embodiments of the invention will now be described, by way of example, with reference to the accompanying diagrammatic drawings, in which
FIG. 1 is a circuit diagram showing schematically the basic elements of an embodiment of the circuit arrangement according to the invention,
FIG. 2 shows waveforms of voltages produced in said embodiment,
FIGS. 3a and 3b show graphs which may be used in the selection of the parameters, and
FIG. 4 is a circuit diagram of a modified part of the circuit arrangement of FIG. 1. The circuit arrangement shown in FIG. 1 includes a driver stage Dr to which signals from a line oscillator, not shown, are applied and which delivers switching pulses to the base of a switching transistor Tr. One end of a primary winding L 1 of a transformer T 1 is connected to the collector of the transistor Tr, which is of the n-p-n type, the other end of the winding L 1 being connected to the positive terminal of a direct-voltage source B to the negative terminal of which the emitter of the transistor Tr is connected. This negative terminal may be connected to the earth of the circuit arrangement.
A trace capacitor C t is connected in series with a line deflection coil L y of the image display apparatus, not shown further, of which the circuit arrangement of FIG. 1 forms part, the resulting series combination being shunted by a diode D 1 having the conductive direction shown and by a retrace capacitor C r . The capacitor C r may alternatively be connected in parallel with the coil L y . The said four elements represent the schematic circuit diagram including the basic elements of the deflection section only. This section may, for example, in known manner be provided with one or more transformers for mutual coupling of the elements, with devices for centering and linearity correction and the like.
A secondary winding L 2 of the transformer T 1 is connected to the anode of a diode D 3 , and the anode of a diode D 2 is connected to the junction point A of the elements D 1 , C r and L y . The cathode of the diode D 2 is connected to the collector of the transistor T r whilst the cathode of the diode D 3 is connected to a tapping Q on a winding L 3 of a transformer T 2 . One end of the winding L 3 is connected to the point A, the other end being connected to earth via a capacitor C 1 . The core of the transformer T 2 carries further windings across which voltages are produced which serve as supply voltages for other components of the image display apparatus. FIG. 1 shows one of said windings, the windings L 4 , which by means of a rectifier D 4 produces a positive direct voltage across a smoothing capacitance C 2 . One of said windings, for example the winding L 4 , is the high voltage winding, so that the voltage set up across the capacitor C 2 is the high voltage for the final accelerating anode of the display tube (not shown). The free ends of the windings L 2 and L 4 are connected to earth, and the winding senses of the windings shown are indicated in the Figure by polarity dots.
The operation of the circuit arrangement is similar to that described in the abovementioned paper and may be summarized as follows. During a first part of the line trace interval the diode D 1 is conducting. The voltage across the capacitor C t is applied to the deflection coil L y through which a sawtooth deflection current i y flows. At a given instant the transistor TR becomes conducting. When in about the middle of the trace interval the current i y reverses direction the diode D 1 is cut off, so that the current i y then flows through the diode D 2 and the transistor Tr. At the end of the trace interval the transistor Tr is cut off. As a result an oscillation, the retrace pulse, is produced across the capacitor C r whilst the energy derived from the source B and stored in the winding L 1 causes a current to flow through the diode D 3 . When the voltage across the capacitor C r has become zero again, the diode D 1 becomes conducting: this is the beginning of a new trace interval.

The diode D 3 remains conducting until the transistor Tr is rendered conducting, the energy stored in the winding L 2 being transferred to the winding L 1 . Stabilisation is provided, for example, by feeding back the voltage across the capacitor C t to the driver circuit Dr, in which a comparison stage and a modulator ensure that the conduction time of the transistor Tr is varied so that the said voltage and hence the amplitude of the deflection current remain constant. Compared with the known case in which the cathode of the diode D 3 is connected to the point A instead of to the tapping Q operation is different, the difference being as follows. In the known case the current passed by the diode D 3 flows to earth via the diode D 1 during the first part of the trace interval. In the arrangement shown in FIG. 1, during this same part energy is stored in the series combination L 3 , C 1 . The voltage v A across the capacitor C r , the voltage v c at the collector of the transistor T r and the voltage v 1 across the winding L 1 are plotted against time in FIGS. 2 a, 2b and 2c respectively. The symbol T indicates the line period, τ 1 indicates the retrace interval, τ 2 that part of the period T in which the transistor Tr is non-conducting, and τ 3 = δ T indicates the part of the period T in which this transistor is conducting. The number δ is the ratio between the time τ 3 and the period T.

The voltage v A consists of the retrace pulse of amplitude V during the time τ 1 and is zero during the time τ 2 . At the instant at which the transistor Tr is rendered conducting, i.e. the instant of transition t 1 between τ 2 and τ 3 , the voltage v C becomes substantially zero. Thus the volage V B of the source B is set up across the winding L 1 .
In the circuit arrangement of FIG. 1 two ratios are significant, namely the transformation ratio between the windings L 1 and L 2 , i.e. the ratio between the number of turns of the winding L 1 and that of the winding L 2 , which is equal to 1 : p, and the ratio of the turns number of the entire winding L 3 and that of the part of this winding between the tapping Q and the end connected to the capacitor C 1 , which ratio is 1 : m. First it will be assumed that the points Q and A coincide (m = 1).
During the time τ 3 the voltage cross the winding L 2 is equal to -pV B . During the time τ 1 the voltage v c is equal to V/p + V B . Let V o be the direct voltage across the capacitor C t , if the capacitance of this capacitor is large enough, or the direct voltage component of the voltage across this capacitor, if it has a comparatively small capacitance for the purpose of the S correction; in either case it is equal to the mean value of the voltage v A , for no direct-voltage component can be set up across the coil L y . The capacitor C 1 has a large capacitance, so that a direct voltage equal to V o is set up across it. The following equation applies: ##EQU1##
The mean value of the voltage across the winding L 3 also is zero, so that the equation applies: ##EQU2## In this formula the integral can be substituted, Yielding V o T = pV B . τ 3 , that is; V o = pδ. V B (1)
At given values of the ratios δ and p the diode D 2 will conduct during the time τ 1 . Because during this time the diode D 3 is conducting, the windings L 1 and L 2 will be short-circuited by the diodes D 2 and D 3 , causing the retrace pulse across the capacitor C r to be clipped and the deflection current to be distorted. U.S. Pat. Application No. 443,863 filed Feb. 19, 1974 describes steps for avoiding such an effect, for example by including in series with the diode D 2 a transistor which is cut off during the time τ 1 . A capacitor C 3 is connected between the ends of the windings L 1 and L 2 or between tappings thereon for the purpose of preventing the occurrence of parasitic oscillations which may be produced by the leakage inductance between the said windings in a manner such that no line-frequency voltage is set up across the capacitor C 3 . FIG. 1 shows the case where p <1.
The maximum value of the collector voltage v c of the transistor is equal to ##EQU3## where α is the ratio V/V o which depends upon the retrace ratio Z = τ1/T. The maximum value of V c is obtained when V B has its maximum value V B max, for which δ has the value δ min , for from the relationship (1) it follows that δ and V B are inversely proportional to one another because the voltage V o is maintained constant.
The voltage V o can be chosen by choosing the ratio p, so that the deflection current y is determined for a given deflection coil L y . However, from the above it follows that the maximum value of the voltage V c , which is highly critical for the transistor, is not controllable. Moreover, the relationship (1) can be written:
V o = p δ min . V B max = p δ max . V B min, where V B min is the minimum value of V B for which δ = δ max , and from which follows: ##EQU4## The ratio δ min has its minimum value δ 1 if the instant t 1 coincides with the middle of the trace interval, and δ max has its maximum value δ 2 if the instant t 1 coincides with the beginning t o of the trace interval. Hence the above ratio cannot exceed 2, so that the arrangement cannot accommodate larger variations of the voltage V B .
According to the invention the points A and Q do not coincide. The voltage across the winding L 3 is equal to v A - V o so that the voltage v Q in the point Q is equal to v Q = V o + m(v A - V o ) = mv A + (1 - m) V o . With the aid of the waveform of the voltage v A of FIG. 2a the waveform of the voltage v 1 across the winding L 1 between the positive terminal of the source B and the collector of the transistor Tr can be plotted (FIG. 2c), allowing for the fact that the diode D 3 is conducting during the times τ 1 and τ 2 .
Thus we have: ##EQU5## during time τ 3 : v 1 = - V B . Writing the condition for the mean value of the voltage v 1 being zero after some calculations yields. ##EQU6## The maximum value of the collector voltage v c is ##EQU7## from which follows: ##EQU8## after substitution of the formula (2). It can be shown that this function steadily decreases with decrease of the ratio m. It is plotted in FIG. 3a for z = 0.2, from which follows α ≉ π/2z ≉ 7,8, and with δ min = δ 1 = 1/2 (1 - z) = 0.4. The Figure shows that by making m less than 1 a reduction of the maximum collector voltage is obtained and that this result is independent of the ratio p.
From the formula (2) the following relationship can be derived: ##EQU9## ##EQU10## This function also is independent of the ratio p and it increases as m decreases. It is plotted in FIG. 3b for δ min = δ 1 = 0.4 and δ max = δ 2 = 0.8 (Z = 0.2), so that the entire δ range is used, whilst the Figure shows that a larger range of supply voltage variations can be accommodated, for when m is less than 1 the ratio V B max /V B min exceeds 2.
Similarly to the preceding case, the voltage V o can be determined by the choice of the ratio p. If the means described in the abovementioned U.S. Pat. Application No. 443,863 are to be dispensed with, it is found that an upper limit can be set to p. The diode D 2 will just be conducting during the time δ 1 if the lowest value of the voltage V c which is found in practice, that is ##EQU11## is equal to the voltage V. In the above expression, according to the formula (2), ##EQU12## from which we can derive: ##EQU13##
The above will be explained by means of two numerical examples. If the voltage V B can vary between 230 volts and 345 volts (with a mains voltage of 220 volts) V B max /V B min is less than 2, so this does not provide difficulty. If the transistor Tr is not capable of withstanding a voltage exceeding 1200 volts, it will be seen from FIG. 3a that m = 0.64. From the formula (2) it follows that ##EQU14## with δ min = δ 1 and ##EQU15## so that δ max = 0.56 < δ 2 . The formula (5) yields: ##EQU16## so that V o = 0.87 times 161 = 140 volts.

If now the voltage V B can vary between 115 volts and 345 volts (the mains voltage is 110 volts or 220 volts), then V B max /V B min = 3. FIG. 3b shows that m = 0.38, for which FIG. 3a yields V c max = 2.9 times 345 = 1000 volts. Formula (2) yields: ##EQU17## whilst ##EQU18## so that V o = 0.54 times 183 volts = 99 volts. Because m cannot be increased, a higher V o if desired requires p to exceed 0.54, and hence the step according to the abovementiond Patent Application must be used.
Similarly to what is the case in U.S. Pat. Application No. 473,771, filed June 1, 1973, the cores of the transformers T 1 and T 2 of FIG. 1 may be one and the same core, that is to say the windings L 1 , L 2 and the winding L 3 may be coupled to one another in spite of the fact that voltages of different waveforms are set up across the said windings. This is possible because the said voltage waveforms are not affected by the coupling, since the voltages V o and V B are "hard," that is to say they are externally impressed, and hence are not affected by the coupling. The currents flowing through the windings, however, are affected. In the lastmentioned Patent Application it is shown that the operation of the circuit arrangement is not adversely affected thereby, but on the contrary important advantages are obtained. It should be mentioned that instead of the tapping Q an additional winding may be wound on the same core as the winding L 3 , which additional winding has a smaller number of turns than the winding L 3 and is included between the cathode of the diode D 3 and the junction point of L 3 and the capacitor C 1 .

Formula (5) shows that the ratio m should not be excessively small, because in this case the ratio p also is small, with the result that large currents flow on the secondary side of the transformer T 1 . In addition, large currents then will flow through the leakage inductance of the said transformer, which gives rise to ringing at the instant t 1 . Furthermore difficulties will arise in designing the abovementioned embodiment using a single transformer. If for these reasons the formula (5) is not complied with, that is to say if p is made greater than the preferred value p max , the steps according to the abovementioned U.S. Pat. Application No. 443,863 have to be employed. This requires an additional transistor, which is expensive, or an additional diode, which does not prevent the production of a high V c max, whilst it was the very purpose of using a low m to obtain a low V c max.
In practice there is a leakage inductance between the two parts of the winding L 3 . In FIG. 4, which shows only part of the circuit arrangement, this leakage inductance is shown as an inductance L 5 between the point Q and an imaginary tapping Q' on the winding L 3 . The inductance L 5 prevents abrupt current transistions which in conjunction with the stray capacitances may give rise to ringing. This can be avoided by connecting a capacitor C 4 between points A and Q and a capacitor C 5 between the point Q and the junction point of the winding L 3 and the capacitor C 1 . If the ratio between the reactances of C 4 and C 5 is equal to that between the numbers of turns of the upper and lower parts of the winding L 3 , no alternating voltage is set up across the inductance L 5 so that no ringing can occur. The parallel connection of the capacitor C r and of the network C 4 , C 5 together with the inductive components of the circuit arrangement results in a resonant frequency the period of which is about equal to twice the time τ 1 .
Hereinbefore it has been assumed that the capacitance of the capacitor C 1 is sufficiently large to enable the voltage across it to be regarded as constant (= V o ). It should be mentioned that this is necessary only if one or more of the auxiliary voltages produced by means of windings of the transformer T 2 are obtained by means of trace rectification.

A combination deflection circuit and switching mode power supply uses only a single switching element. Across certain diodes in this circuit is a stable voltage. A capacitor and a transformer primary are series coupled to each other and together parallel coupled across at least one of the diodes. A rectifier is coupled to the transformer secondary to provide power to other portions of a television set.

1. A line deflection circuit for generating from a direct voltage source a sawtooth current flowing through a deflection coil, said circuit comprising a parallel resonant circuit comprising said coil, a trace capacitor coupled to said coil, and a retrace capacitor coupled to said coil; a first diode coupled to said retrace capacitor, the deflection current flowing during a first part of the trace period through said first diode and during a second part of the trace period through a controllable switch, energy being applied from said direct voltage source during the trace period to a first winding arranged between said direct voltage source and the switch, and being applied through a second diode conducting during the retrace period from a second winding to the parallel resonant circuit which is connected to the switch through a third diode conducting during the second part of the trace period, at least one of the second and third diodes being shunted by the series arrangement of a capacitor and a primary winding of a current supply transformer, and means for rectifying coupled to said transformer for the direct current supply to other stages of the device. 2.

A circuit as claimed in claim 1 wherein said switch comprises a transistor. 3. A circuit for generating from a direct voltage source a sawtooth current having trace and retrace periods through a deflection coil, said circuit comprising a trace capacitor, means for coupling said trace capacitor to said coil, a retrace capacitor coupled to said trace capacitor, diode coupled to said retrace capacitor, a first diode means coupled to said retrace capacitor for conveying said current during a first part of said trace period, a first winding having a first end means for coupling to said source and a second end, a controllable switch means coupled to said second end for conveying said current during a second part of said trace period, a second winding, a second diode means coupled between said first diode and said second winding for conducting during said retrace period, a third diode means coupled between said first diode and said switch for conducting during said second part of said trace period, and means for supplying direct current power comprising a transformer having primary and secondary windings, a capacitor series coupled to said primary, said primary and capacitor being parallel coupled to at least one of said second and third diodes, and a rectifier coupled to said secondary. 4. A circuit as claimed in claim 3 wherein said switch comprises a transistor.

Description:

The invention relates to a line deflection circuit for a device comprising a cathode-ray tube particularly a television receiver display tube, for generating a sawtooth current flowing through a deflection coil in which the deflection coil constitutes part of a parallel resonant circuit comprising also a trace capacitor, a retrace capacitor and a first diode, the deflection current flowing during a first part of the trace period through said first diode and during a second part of the trace period through a controllable switch, for example, a transistor, energy being applied from a direct voltage source during the trace period to a first winding arranged between said direct voltage source and the switch, and being applied through a second diode conducting during the retrace period from a second winding to the parallel resonant circuit which is connected to the switch through a third diode conducting during the second part of the trace period.

Such a circuit arrangement is known from "IEEE Transaction on Broadcast and Television Receivers",

August 1972, vol. BTR-18, No. 3, pages 177 to 182. The known circuit arrangement is the combination of a transistorized line deflection stage for a television receiver and a stabilised switch mode power supply, whereby one single switching element, the above mentioned transistor is both the switching transistor and the line deflection transistor.

An object of the invention was to further develop this circuit arrangement. It was found that an alternating voltage is present at the above mentioned second and third diode, which voltage is stabilized. The object according to the invention was to utilize this available and unilaterally stabilized rectangular voltage in a particularly advantageous manner.

This object is solved in that in a line deflection circuit of the kind described in the preamble the second and/or third diode is shunted by the series arrangement of a capacitor and a primary winding of a current supply transformer serving via rectifying for the direct current supply to other stages of the device.

An embodiment of the invention is shown in the drawings and will be further described hereinafter.

FIG. 1 shows the circuit improved according to this invention.

FIG. 2 shows different voltage variations as a function of time.

For the description of FIG. 1 the description of the Figures of the previously cited known circuit may be essentially used as a reference. A transformer is denoted by T1, a primary winding is L1; it is connected through a coupling capacitor CK to a secondary winding L2. A direct voltage source is UB. Furthermore a winding L3 is provided on the transformer secondary side which may serve for the high voltage generation UH through the diode Db.

The switching transistor is TR; rectangular pulses with the line frequency and originating from a driver stage (not represented) are applied to this transistor. The entire circuit arrangement thus serves for generating a sawtooth current flowing through a deflection coil L. The deflection coil L is part of a parallel resonant circuit consisting of a retrace capacitor C2, the deflection coil L itself and a trace capacitor C3.

In the operative condition a first diode D2 which is parallel connected to the said resonant circuit conducts during a first part of the trace period and conveys the negative part of the deflection current I 2 during the period from t1 to t3 (compare FIG. 2d). During this period the switching transistor TR is separated from the deflection circuit consisting of D2, L, C2, C3 by a third diode Dd biassed in the blocking direction.

At the instant t2 which is adjustable via the width of the rectangular pulses (compare FIG. 2f) at the base of TR, TR is rendered conducting. As a result a current can flow through L1 and TR which stores until the switch-off instant t4 the energy required for operating the circuit in L1. This energy is applied to the deflection circuit at the initiation of the retrace period t4 so as to compensate for losses. This energy storage is ended at the instant t1 of the new period.

Meanwhile the zero crossing of the deflection current occurs at instant t3. D2 is blocked. Due to the polarity change of the current I L the third diode Dd becomes conducting and the deflection current may be taken over by the switching transistor TR. This current is superimposed uninterfered on the part of the collector current originating from the power supply function of TR.

Thus the deflection function of the circuit in addition to the power supply function is ensured. This function may be influenced by shifting the instant t2. The limits of the control range are at t1 and t3. By comparison, for example, of the voltage UA over the diode D2 in the retrace period with a reference voltage a control magnitude for t2 can be derived. A stabilisation of the deflection in case of mains voltage and beam current fluctuations is then possible.

It is often essential to provide further stages in the television display apparatus with a stabilized voltage. Conventionally such supply voltages are obtained by trace rectification on an auxiliary winding of the line transformer. In this circuit this simple possibility is not given due to the connection with the power supply function. As can be seen in FIG. 2a the secondary voltage US consists of a rectangular voltage on which the flyback pulse of the deflection circuit is superimposed. When the trace part of US is rectified no stabilized direct voltage can be obtained due to the duty cycle variations caused by the control since the value of the voltage US between the instants t 2 and t 4 depends on that of the voltage UB.

A flyback rectification is feasible in this case. However, due to the small conduction angle an inadmissibly high internal resistance of the obtained supply voltage is to be taken into account.

According to the invention a rectangular voltage present alternatively across the diodes D1 and D2, respectively is used. These voltages do not contain a flyback pulse FIG. 2c shows the voltage variation UN on the secondary side L5 of a transformer T2 introduced for potential separation. A primary winding L 4 thereof is arranged in series with a capacitor C 4 and this series arrangement shunts the diode D1. The capacitor C 4 prevents a dc short circuit of the diode D1 by the winding L 4 and has a capacitance which is large enough for preventing an influence upon the variation of UN. The voltage across the capacitor C 4 is thus equal to the dc-component of the voltage across the capacitor C 3 , which component is stabilised since the voltage UA is. The voltage across the winding L 4 is equal to the difference between that across the diode D1 and that across the capacitor C 4 , the first mentioned voltage being equal to U A -U S . The voltage UN across the winding LS, which winding has the indicated winding sense, has the variation shown in FIg. 2c and between the instants t o and t 2 it is equal to the stabilised dc-component of the voltage present across the capacitor C 3 . The voltage UN is rectified with the aid of a diode DN and smoothed with the aid of a capacitor CN. The rectified voltage UL is applied to the parts of the apparatus using a low voltage which in this case are represented by a load resistor RL.

DN must have such a polarity that it conveys current during the time t o -t 2 . Then the rectified voltage is stabilised to the same extent as the deflection voltage. The conduction angle is large so that the internal impedance of the voltage source is low. The primary side L4 of the transformer T2 is connected to D1 as is shown in FIG. 1. D1 and DN are then conducting simultaneously so that the internal resistance of UN is further reduced. In the same manner the series arrangement of L4 and C4 in parallel with Dd is alternatively possible.

The transformer T2 may be formed with a relatively small core due to the high operating frequency. On account of the switching properties (Dd and D1 alternately conducting) the rectangular voltage cannot become larger than the direct voltage on CK (corresponds to the voltage UB). Overvoltages as a result of for example picture tube flash-overs are thus prevented.

" A method for tuning a television receiver having automatic frequency control to the carrier frequency of a selected broadcast channel with an associated channel number including generating a variable frequency signal by means of a local oscillator, generating a reference frequency signal by means of a reference oscillator, and generating a local oscillator correction signal for matching an intermediate frequency signal derived from said local oscillator signal and the carrier frequency signal with a predetermined nominal intermediate frequency signal, said method being characterized by the use of a microcomputer and comprising:
generating binary signals representing first and second digital tune words, said digital tune words representing a selected channel;
storing said first and second digital tune words in a first data memory in said microcomputer;
reading said first and second digital tune words from said first memory and generating a divided-down local oscillator frequency by the use of said first digital tune word and a divided-down reference oscillator frequency by the use of said second digital tune word;
comparing said divided-down local oscillator and reference frequencies and generating a control signal representative of the difference in frequency of said divided-down local oscillator and reference frequencies;
coupling said control signal to said local oscillator for causing it to be locked to the frequency of said received carrier signal;
mixing the local oscillator frequency signal and the carrier frequency signal to generate an intermediate frequency signal;
comparing said intermediate frequency signal with said predetermined nominal intermediate frequency signal and providing a tuning voltage to said microcomputer, said tuning voltage being indicative of the magnitude and direction of a tuning error between said intermediate frequency signal and said predetermined nominal intermediate frequency signal;
incrementally adjusting the reference oscillator frequency by means of a tuning signal provided to said reference oscillator by said microcomputer in response to said tuning voltage;
detecting when the incrementally changing, divided-down reference oscillator frequency causes the intermediate frequency signal to pass said predetermined nominal intermediate frequency signal; and
incrementally stepping the divided-down reference oscillator frequency back a predetermined number of steps following the passage of said predetermined nominal intermediate frequency signal by said intermediate frequency signal in tuning said television receiver to the selected channel.
"

A television tuning system employs a frequency synthesizer system for establishing the tuning of the receiver. A programmable frequency divider counter is connected between the output of a reference oscillator and a phase comparator to which the output of the local oscillator in the tuner also is applied. The phase comparator output provides a tuning voltage for controlling the tuning of the local oscillator. A microprocessor is used to control the count of the programmable frequency divider and initially to set a count corresponding to the selected channel in a counter connected between the output of the local oscillator and the phase comparator. The tuning consists of three discrete time periods. First, a settling time to allow channel change transients to settle; second, a short period of forced search at a relatively rapid rate to insure proper tuning; and third, a slower rate of step-by-step correction to accomodate for station drift and the like during reception. This third time period is initiated either by the passage of a fixed length of time following the start of the forced search period or by sensing a preestablished number of changes of state in the output of the frequency discriminator during the forced/search period.

1. A tuning system for the tuner of a television receiver capable of receiving a composite television signal and including frequency discriminator (AFT) circuit means, said system including in combination:
a reference oscillator providing a reference signal at a predetermined frequency;
a local oscillator in the tuner providing a variable output frequency in response to the application of a control signal thereto;
a programmable frequency divider means having first and second inputs coupled respectively to the output of said reference oscillator and said local oscillator for producing signals on first and second outputs having frequencies which are a programmable fraction of the frequency of the signals applied to the inputs thereto;
phase comparator means having one input coupled with the first output of said programmable frequency divider means and having another input coupled with the second output of said programmable frequency divider means for developing a control signal and applying such control signal to said local oscillator for controlling the output frequency thereof;
counter circuit means coupled with said programmable frequency divider means for initially setting said divider means to a predetermined division ratio and operating to change the programmable fraction of division thereof in accordance with changes in the count in said counter circuit means;
control circuit means coupled with the output of said frequency discriminator means and further coupled with said counter circuit means for causing said counter circuit means to count at a first rate in a predetermined direction determined by the state of the output signal from said discriminator means in the absence of a predetermined signal output from said frequency discriminator means until a predetermined maximum count is attained, thereupon resetting said counter circuit means to a count which is a predetermined amount less than said maximum predetermined count and continuing to count at said first rate in the same predetermined direction from said new count to continuously change the programmable fraction of said frequency divider means in accordance with the state of operation of said counter circuit means, said control means operating in response to said predetermined signal output from the frequency discriminator means for terminating operation of said counter circuit means; and
further means for terminating operation of said counter circuit means at said first rate and causing operation thereof at a second slower rate.
2. The combination according to claim 1 wherein said further means includes timing means initiated into operation simultaneously with the setting of said divider means to a predetermined division ratio, and after a predetermined time interval said timing means producing an output signal applied to said counter circuit means to cause operation thereof to take place at said second slower rate. 3. The combination according to claim 1 wherein said counter circuit means includes a reversible digital counter coupled with said programmable frequency divider, means and said control circuit means causes said counter circuit means to count in said predetermined direction when the output of said frequency discriminator is of a first state and to count in the opposite direction when the output of said frequency discriminator is of second state; and said further means comprises means coupled with the output of said frequency discriminator and with said counter circuit means to take place at said second slower rate in response to a predetermined number of changes of state of frequency discriminator. 4. The combination according to claim 3 further including means responsive to the selection of a new channel in said television receiver for resetting said further means to an initial condition of operation. 5. The combination according to claim 4 wherein said further means comprises a search termination counter means operative to provide an output signal applied to said counter circuit means in response to a count thereby of a predetermined number of changes of state of said frequency discriminator to cause said counter circuit means to be operated at said second slower rate.

Description:

BACKGROUND OF THE INVENTION
Both of the above mentioned patents are directed to frequency synthesizer tuning systems for use with television receivers to enable operation of the receivers with minimal viewer fine tuning adjustments. By the utilization of the frequency synthesizer tuning systems of these patents, the fine tuning adjustment which is necessary with conventional types of television receiver tuning systems has been substantially eliminated. The system employed in the '953 patent permits utilization of a frequency synthesizer tuning system which correctly tunes to a desired television station or channel even if the transmitted signals from that station are not precisely maintained at the proper frequencies. The '535 patent is directed to a signal seek tuning system adaptation of the frequency synthesizer tuning system of the '953 patent which still permits implementation of all of the desired wide-band pull in range of the frequency synthesizer system of the '953 patent.
The systems of the foregoing patents operate effectively to correct automatically for frequency offsets in a frequency synthesizer tuning system without affecting the operation of the conventional frequency synthesizer used in the system. The systems of these patents are in widespread use commercially and permit direct selection, with automatic fine tuning adjustment, of any desired VHF channel which the viewer wishes to observe. In addition, the signal seek adaptation disclosed in the '535 patent couples all of the advantages of the frequency synthesizer tuning system of the '953 patent with the desirability of providing bidirectional signal seek operation.
While the systems disclosed in the foregoing patents operate in a highly satisfactory manner to accomplish the desired results of accurate tuning without the necessity of fine tuning adjustments, the circuitry for accomplishing the desired results is somewhat complex. It is desirable to reduce the circuit complexity and the number of signal detectors for accomplishing these results without compromising the accuracy of operation of the system.
SUMMARY OF THE INVENTION
Accordingly, it is an object of this invention to provide an improved tuning system for a television receiver.
It is an additional object of this invention to provide an improved frequency synthesizer tuning system for a television receiver.
It is another object of this invention to provide an improved frequency synthesizer tuning system for a television receiver which includes a provision for adjusting the synthesizer loop for frequency offsets in the received signal with a minimum number of signal detectors.

It is a further object of this invention to tune the local RF oscillator of a television receiver to the correct frequency for a selected channel with a frequency synthesizer tuning system, and automatically to change the reference frequency of the synthesizer system, or adjust the count of a programmable divider that produces a signal that divides the frequency of the local oscillator of the tuner, if the AFT signal produced by the AFT frequency discriminator of the receiver is outside a predetermined range corresponding to correct tuning.
It is still another object of this invention to provide an improved frequency synthesizer tuning system for a television receiver which operates to adjust the synthesizer loop for frequency offsets in the received signal over a relatively wide pull in range in response to the output of the receiver frequency discriminator by changing the division ratio of a programmable frequency divider in the reference oscillator leg or local oscillator leg of the synthesizer loop at a first relatively high rate from an initial nominal value to a pre-established maximum in one direction, and then resetting the division ratio to a second nominal value once the maximum is reached and continuing to incrementally change the division ratio in the same direction from the second nominal value until a properly tuned condition is indicated by the output of the receiver AFT frequency discriminator, followed by control at a lower rate of operation to maintain tuning during transmitting station drifts.In accordance with a preferred embodiment of this invention, the frequency synthesizer tuning system for a television receiver includes a stable reference oscillator and a voltage controlled local oscillator in the tuner. A programmable frequency divider is connected between the output of the reference oscillator and one input to a phase comparator, the other input of which is supplied by the output of the local oscillator. The output of the phase comparator then comprises a control signal which is supplied to the local oscillator to control the frequency of its operation.
A counter circuit is connected to the programmable frequency divider for initially setting the divider to a predetermined division ratio upon selection of a desired channel by the viewer. The counter then operates to change the programmable fraction of the division ratio at a first relatively high rate in a direction controlled by the output from the receiver picture carrier discriminator in the absence of a predetermined signal output derived from the discriminator. A control means causes the counter circuit to count in this direction until it is determined that a station is tuned or a predetermined maximum count is attained if no station is correctly tuned, thereupon resetting the counter circuit to a count which is a predetermined amount less than the maximum predetermined count. Counting is continued in the same predetermined direction from the new lesser count to continuously change the programmable fraction of the frequency divider in accordance with the state of operation of the counter.

The high rate operation of the counter is terminated by the control means in response to a predetermined signal from the output of the discriminator, indicating that a station is correctly tuned, or after a fixed time-out interval; so that the system automatically adjusts for frequency offsets of the received signal which otherwise would cause the station to be mistuned if a conventional frequency synthesizer tuning system were used. After termination of the high rate operation of the counter, it is switched to a lower rate operation for maintaining tuning during transmitting station drifts.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a television receiver employing a preferred embodiment of the invention;
FIG. 2 is a detailed block diagram of a portion of the circuit of the preferred embodiment shown in FIG. 1;
FIG. 3 is a detailed circuit diagram of a portion of a circuit shown in FIG. 1;
FIG. 4 is a flow chart of the control sequence of operation of the circuit shown in FIG. 1 and 2; and
FIG. 5 shows a waveform and time/frequency chart, respectively, useful in explaining the operation of the circuit shown in FIGS. 1, 2 and 3.
DETAILED DESCRIPTION
Referring now to the drawings, the same reference numbers are used throughout the several figures to designate the same or similar components.
FIG. 1 is a block diagram of a television receiver, which may be a black and white or color television receiver. Most of the circuitry of this receiver is conventional, and for that reason it has not been shown in FIG. 1. Added to the conventional television receiver circuitry of FIG. 1, however, is a frequency synthesizer tuning system, in accordance with a preferred embodiment of the invention, which is capable of automatically changing the reference frequency when a frequency offset exists in the received signal for a particular channel.
Transmitted composite television signals, either received over the air or distributed by means of a master antenna TV distribution system, are received by an antenna 10 or on antenna input terminals to the receiver. As is well known, these composite signals include picture and sound carrier components and synchronizing signal components, with the composite signal applied to an RF and tuner stage 11 of the receiver. The stage 11 includes the conventional RF amplifiers and tuner sections of the receiver, including a VHF oscillator section and a UHF oscillator section. Preferably, the UHF and VHF oscillators are voltage controlled oscillators, the freuency of operation of which are varied in response to a tuning voltage applied to them to effect the desired tuning of the receiver.
The output of the RF and tuner stages 11 is applied to the remainder of the television receiver 14, which includes the IF amplifier stages for supplying conventional picture (video) and sound IF signals to the video and sound processing stages of the receiver 14. The circuitry of the receiver 14 may be of any conventional type used to separate, amplify and otherwise process the signals for application to a cathode ray tube 16 and to a loudspeaker 17 which reproduce the picture and sound components, respectively, of the received signal.The receiver 14 also includes a conventional AFT or automatic fine tuning discriminator circuit and additionally may include a synch separator circuit for producing an output in response to the presence of vertical synchronizatin pulses, a picture carrier detection circuit, and an automatic gain control (AGC) amplifier. Outputs representative of these sensor components are shown as being coupled over a group of lead 20 to sensory circuitry 22, which in turn couples outputs representative of the operation of these various sensor circuits to a microprocessor unit 23 for controlling the operation of the microprocessor unit.
The microprocessor unit 23 is utilized in the system of FIG. 1 for controlling the operation of a frequency synthesizer tuning system capable of automatic offset correction. When the viewer desires to select a new channel, he enters the desired channel number into a channel selection keyboard 25. There are a number of different keyboards which may be employed to accomplish this function, and the particular design is not important to this invention. The channel selector keyboard 25 also may include switches or keys for initiating a signal seek function in either the "up" or "down" direction.
Information represented by the selection of channel numbers on the keyboard 25 is supplied to the microprocessor unit 23 which provides output signals over a corresponding set of leads 27 to the tuners (local oscillators) 11 to effect the appropriate band switching control for the tuners 11 in accordance with the particular channel which has been selected. In addition, the keyboard 25, operating through the microprocessor unit 23, provides output signals which operate a channel number display 29 to provide an appropriate display of the selected channel number to the viewer.
The microprocessor M3870 unit 23 also processes the signals which are used to operate the channel number display 29 through a multiplexing circuit operation to decode the selected channel number into a parallel encoded signal. This signal is applied to corresponding inputs of the count-down counter or programmable frequency divider 31 to cause the division number of the divider 31 to relate to the divided down frequency of the tuner local oscillators connected to the input of the divider 31 through a prescaler divider circuit 32 to the frequency of the reference oscillator 34. Thus, the division number or division ratio of the local oscillator frequency obtained from the output of the programmable divider 31 is appropriately related to the frequency of the reference crystal oscillator 34.

The output of the oscillator 34 also is applied through a countdown circuit or programmable frequency divider 35. Conventional frequency synthesizer techniques are employed; and the microprocessor unit 23 automatically compensates, through appropriate code converter circuitry, for the non-uniform channel spacing of the television signals. It has been found most convenient to cause the programmable frequency divider 31 to divide by numbers corresponding directly to the oscillator frequency of the selected channel, for example, 101, 107, 113 . . . up to 931.
In accordance with the time division multiplex operation of the microprocessor 23, the count of the programmable frequency divider 35 initially is adjusted to a fixed count by the application of appropriate output signals from the microprocessor unit 23 to a point selected to be at or near the mid-point of the operating range of the programmable frequency divider 35. Thus, the output of the divider 35 is a stable reference frequency (because the input is from the reference crystal oscillator 34) which is used to establish initially and to maintain tuning of the receiver to the selected channel.
The output of the programmable divider 35 is applied to one of two inputs of a phase comparator circuit 37. The other input to the phase comparator circuit 37 is supplied from the selected one of the VHF or UHF oscillators in the tuner stages 11 through the programmable frequency divider 31. The phase comparator circuit 37 operates in a conventional manner to supply a DC tuning control signal through a phase locked loop filter circuit 39 and over a lead 40 to the oscillators in the tuner system 11 to change and maintain their operating frequency.
With the exception of the use of the microprocessor unit 23, the operation of the system which has been described thus far is that of a relatively conventional frequency synthesizer system incorporated into a television receiver. This system is similar to the system of the '953 patent. As in the system of that patent, the system shown in FIG. 1, when the transmitted station or station received on a master antenna distribution system provides the station or channel signals at the proper frequency, operates as a relatively conventional frequency synthesizer system. If, however, there is a frequency offset in the received signal to cause the carrier of the received signal to be displaced from the frequency which it should have to some other frequency, it is possible that the system would give the appearance of mistuning to the received station. The microprocessor 23, operating in conjunction with the sensory circuitry 22, is employed in conjunction with the countdown or programmable frequency divider circuit 35 to eliminate this disadvantage and still retain the advantages of frequency synthesizer tuning.
Reference now should be made to FIG. 2 which shows details of the interface between the keyboard 25, the microprocessor unit 23, and the circuitry used in the frequency synthesizer portions of the system. A commercially available microprocessor which has been used for the microprocessor 23, and which forms the basis for the diagramatic representation of the microprocessor in FIG. 2, is the Matsushita Electronics Corporation MN1402 four-bit single-chip microcomputer. This microcomputer has two, four-bit parallel input ports labeled "A" and "B". In addition, three output ports, a five-bit output port "C" and two four-bit output ports "D" and "E" are provided. The internal configuration of the microcomputer 23 includes an arithmetic logic unit (ALU), a read only memory (ROM) for storing instructions and constants, and a random access memory (RAM) used for data memory, arranged into four files, each file containing 16 four-bit words. These words are selected by X and Y registers and this memory is used, for example, for timers, counters, etc., and also is used to hold intermediate results. To facilitate an understanding of the operation of the system, a portion of this memory is shown in FIG. 2 as a clock 81 and a reversible counter 82 connected between the "B" input port and the "D" output port. The microcomputer 23 is programmed to permit it to operate in conjunction with the remainder of the circuits shown in FIG. 2. The programming techniques are standard, and the microcomputer 23 itself is a standard commercially available circuit component.
There are several system parameters that must be selected in the operation of the system shown in FIG. 2. The selection of the nominal frequency of the two signals that feed the phase comparator circuit 37 is an example. Channel selection is provided by changing the frequency division ratio of the selector counter 31 which divides the local oscillator signal after this signal is passed through a prescaler circuit 32 and a divide-by-two divider circuit 41. The nominal frequency from the programmable frequency divider 31 (selector counter) is selected so that the local oscillator (tuner) 11 can be set exactly on frequency for all channels.

Since the frequency divider 31 is able to divide only by integer numbers, one distinct frequency possibility in the range of one KHz is obtained, another in the range of two KHz, etc. A choice must be made as to which of these values is optimum. Each value yields the nominal frequency of all of the 82 channels by simply multiplying by an appropriate integer for each channel. To simplify the phase locked loop filtering problem by the filter 39, it is desirable that the frequencies of the signals supplied to the phase comparator 37 are as high as possible. This permits rapid acquisition of a new channel along with a very clean DC control signal to adjust the local oscillator. A trade-off for this, however, must be made to permit fine tunning adjustment of the local oscillator automatically to correctly tune in stations which are off their assigned frequency, or to manually provide this feature, if desired. The two-speed operation of the system in accordance with the present invention allows a better trade-off to be made by allowing rapid acquisition and then a slower speed for precise tuning.
A compromise solution which is utilized in the circuit of FIG. 2 is to cause the frequency division chain from the local oscillator 11 in the tuner to the phase comparator 37 to be composed of the fixed divide-by-256 prescaler 32, and a fixed divide-by-4 division, which is accomplished by the divider 41 at the input of the counter 31 and a second divider 42 at the output of the counter 31. The variable frequency divider counter 31 then is loaded by means of three latch circuits 44, 45 and 46 at an appropriate time by the time division multiplex operation of the microcomputer 23 and a number that programs the programmable frequency divider counter 31 to divide by the numerical value of the frequency of the local oscillator in MHz for the channel selected. For example, if the receiver is to be tuned to channel 2, which has a nominal local oscillator frequency of 101 MHz, the programmable frequency divider 31 is set to divide by 101. If the receiver is to be tuned to channel 83, which has a nominal local oscillator frequency of 931 MHz, the programmable frequency divider 31 is set to divide by 931. In both cases, the variable divider 31 produces a 1 MHz signal. However, because of the fixed divide-by-256 and the two fixed divide-by-two dividers in series with the programmable divider 31, an output frequency of 976.5625 Hz is supplied from the output of the divider 42 to the upper input of the phase comparator 37.

The division ratio of the selector counter 31 is established by appropriate output signals from the latch circuits 44, 45 and 46, as mentioned above. The initial operation for changing, or maintaining, the division ratio of the divider 31 is established by an entry of the two digits of the selected channel number in the keyboard 25. The microcomputer 23 operates as a time division multiplex system for continuously monitoring the input ports and the output ports to control the operation of the remainder of the system. The selection of the two digits of the desired channel number is affected by a time division multiplex iscanning of the outputs of the D output port of microcomputer 23 and providing that information at the A input port. From here the information is translated again to the D output ports to the appropriate drivers of the channel number display circuit 29 and to the latches 44, 45 and 46, and to a pair of similar four bit latches 49 and 50 which control the divider ratio of the counter 35.
Although the D output ports of the microcomputer 23 are connected in common to all of these various portions of the circuit, the selection of which of the latches are enabled to respond to the particular output signals appearing on the D output ports at any given time is effected through the C and E output ports of the microcomputer 23 in a time division multiplex fashion. A decoder circuit 52, connected to the lowermost three outputs of the E output port of the microcomputer 23, is used to apply unique decoding signals at different times in the time division multiplex sequence of operation of the microcomputer 23 to the five latch circuits 44, 45, 46, 49 and 50, respectively. At any given time in the sequence, only one of these latch circuits is enabled for operation. A latch load signal is applied from the upper output (EO3) at each cycle of operation of the signals appearing on the E output port to set the latch circuit which is enabled by the output of the decoding circuit 52 with the data appearing on the other inputs to the latch circuit. This data simultaneously appears on the four outputs of the D output port of the microcomputer 23.
Thus, in rapid sequence, the latch circuits 44, 45 and 46 are set to store the division number corresponding to the selected channel entered onto the keyboard 25, and the latch circuits 49 and 50 are each operated to set the programmable divider reference counter 35 to a center or nominal count, which is always the same upon the selection of a new channel on the keyboard 25. Similarly, the two right-hand outputs of the C output port (CO6 and CO5) enter the two digits of the selected channel number in the drivers of the display circuit 29 at the proper time in the binary encoded sequence when these digits appear on the four-bit binary encoded representation of the D output port. This results in a visual display of the channel number selected.
In addition to the selection of a channel number directly by the keyboard 25, the keyboard also may include an additional switch 56, which is scanned in the time division multiplex sequence to determine if the receiver is placed in a "seek" mode of operation (when the signal seek capability is incorporated into such a receiver). Operating in conjunction with the signal seek switch 56 are a pair of "up" and "down" seek direction input switches shown with a graphic representation of the seek directions on the keyboard 25. A further provision is provided by two keys labeled "U" and "D", which are used for "manual" fine tuning of the receiver in the "up" or "down" directions depending upon which of the two keys U or D has been operated. The keyboard 25 includes one additional switch 58 which may be used to disable the automatic fine tuning (AFT) portion of the circuit by rendering the microcomputer insensitive to the signal output from the AFT circuit, in a manner described more fully subsequently.
As is apparent from the foregoing, the microcomputer 23 provides the intelligence, decision making, and control for the system operation. It is a complete self contained computer. The decisions or signal inputs upon which the microcomputer 23 bases its operation include, in addition to the inputs from the keyboard 25, inputs on sensory inputs into the B input port and into the SNS1 and SNS0 inputs as shown in FIG. 2. These input signals are used to provide an indication to the microcomputer 23 of the presence or absence of a received signal; and if the presence of such a signal is indicated, the inputs provide a further indication of the accuracy of the tuning of the receiver to that signal. If the system is being operated solely in a manual mode of operation (AFT switch 58 open), the microcomputer 23 disregards all of this sensory information and tunes to the frequency allocation of the channel selected in the manner described above. The system will stay tuned to this condition, operating as a conventional frequency synthesizer, whether or not a station is present in the received signal.When the system is placed in its automatic mode of operation (similar to the mode of operation of the above mentioned '953 patent), the counter 82, integrally formed as part of the microcomputer 23, continuously adds or subtracts one number at a time from the nominal value or programmable division fraction entered into the programmable frequency divider 35 at the outset of each new channel number selection when frequency offset (mistuning) is present. The counter 82 is driven at a relatively high counting rate by clock pulses from the clock 81 during this initial or forced search mode of operation. Thus, automatic offset correction is provided for any channel which is off its assigned frequency. The offset correction automatically adjusts the frequency of the local oscillator by changing the division ratio of the signal from the reference oscillator 35 applied to the lower input of the phase comparator 37. By doing this, the output of the phase comparator 37 applied to the local oscillator 11 varies to cause the oscillator to be tuned in the proper direction to compensate for the transmitting station mistuning.
When the system is operating in its automatic mode of operation, the microcomputer 23 responds to the sensor information applied to it on its B input ports and on the S1 input port shown in FIG. 2. These inputs are obtained from the various outputs of the operational amplifiers shown connected to the corresponding input ports in the detailed circuit of FIG. 3. Depending upon whether the receiver is provided with a signal seek feature or not, one or more of the sensory inputs of the circuit of FIG. 3 are used. The system shown in the drawings has a capability of correcting for frequency offsets larger than 1.5 MHz on channels 2 and 7 and approximately 2 MHz on channels 6 and 13. The remainder of the channels have a range between these two values.
If the receiver is not tuned properly, the micromputer 23 executes the localized search of the tuning range mentioned above. Since there is a necessary settling down time for the tuning of a television receiver immediately following selection of a new channel, a time interval of 250 milliseconds has been selected to prevent any localized search or offset frequency correction until the expiration of this "settling down" time period. If, at the end of this 250 millisecond time interval, a properly tuned station is present, this is indicated by the sensory outputs from the television receiver and no localized search is effected to change the division ratio or programmable divider count in the reference counter 35 for a system that also has signal seek.
A system with no signal seek capability is described later that requires less sensory input but which uses a time period where a forced search is required directly after the settling time interval.

Upon termination of the 250 millisecond settling down period, the microcomputer 23 is rendered responsive to the sensory input signals on its sensory input signal ports. In the simplest form, only the output of the frequency discriminator 60 (FIG. 3) applied to three comparators 61, 62 and 63 is used to provide the necessary tuning information to the microcomputer 23. The outputs of these comparators are applied to the B12 and B11 inputs of the microcomputer.

The comparator 61 simply is a conventional comparator for determining whether or not the output of the frequency discriminator is positive or negative, as indicated in the upper waveform of FIG. 5. The comparators 62 and 63 are each adjusted with appropriate reference input levels to provide a narrow window centered about the center tuning frequency (fc) of the receiver. If the tuning of the receiver, as indicated by the output of the frequency discriminator 60, is outside this window on either side of the central axis shown in FIG. 5, one output condition is indicated on the input terminal B11 of the microcomputer. Only when the tuning frequency is within the tuning window, indicative of a properly tuned receiver, is the appropriate input applied to the microcomputer input terminal B11. This input overrides any other input that may be present on the input terminal B12 and is indicative of a properly tuned receiver. The input from the frequency discriminator 60, as applied to the microcomputer on its input port B12, is used to determine the direction of operation of the counter 82 of the microcomputer for the localized search count signals applied to the latch circuits 49 and 50 to change the count of the reference programmable divider counter 35 on a step-by-step basis.
The lower graph of FIG. 5 plots the relative frequency of the local oscillator 11 to the received signal frequency with respect to time. The various arrows are used to indicate the manner of operation of the counter 82 in the microcomputer 23 in conjunction with the reference counter 35 for adjusting for any mistuning conditions which may exist after the initial station selection has been effected in the manner described above.
If the receiver is properly tuned, the outputs from the comparators 62 and 63 of FIG. 3 which are combined together and applied to the input port B11 of the microcomputer 23, provide an indication that the tuning is within the properly tuned center frequency window. As a consequence, no further operation of the microcomputer to change any of the outputs applied to the latch circuits 49 and 50 for the duration of this condition is effected. On the other hand, if the receiver is mistuned on either side of the proper tuning frequency, the various operating characteristics shown in FIG. 5 are effected.
Assume initially that the receiver is capable of making tuning adjustments over a range of fc plus Δf to fc minus Δf, as indicated in the top waveform of FIG. 5. Three specific examples of mistuning will then be considered. Initially, assume that the local oscillator is mistuned relative to the received signal to a frequency f1 as shown in the lower graph of FIG. 5. In this condition, the outout of the frequency discriminator 60 is positive since this signal frequency lies to the lefthand side of the center or properly tuned region of operation of the discriminator. Under this condition of the operation, the input signal applied to the sensor port B12 of the microcomputer 23 is such that the microcomputer counter 82 is caused to advance in a positive direction to change the programmable division ratio or count of the reference counter 35 in a manner to force the output of the phase comparator 37 to adjust the frequency of the local oscillator until the proper tuning indicated at point B in the lower graph of FIG. 5 is reached. The time interval for accomplishing this result is measured from the upper end of the arrow representative of the frequency f1 to the point B.
Now assume that the receiver mistuning is to a frequency f2 which as shown in FIG. 5 as located on the righthand-side of the center axis fc. In this condition, the discriminator output is negative. This is reflected in the output of the comparator 61 applied to the input port B12 of the microcomputer 23. The polarity of this signal is identified by the microcomputer 23 to cause the counter 82 in it to operate in the reverse direction. As this count is applied on a step-by-step basis through the latch circuits 49 and 50 to the reference counter 35, the division ratio or count of the reference counter (divider) 35 is changed. As a result, the reference oscillator signal applied to the phase comparator 37 causes the phase comparator 37 output to drive the local oscillator frequency in a direction opposite to that considered in the first example. This is shown by the vector interconnecting the top of the arrow representative of f2 to point A on the time/frequency graph of FIG. 5.
As discussed in the general discussion above, whenever the tuning frequency reaches the narrow window on either side of fc, the outputs of the comparators 62 and 63 provide the necessary indication on the sensory input port terminal B11 to cause termination of the operation of the counter 82 in the microcomputer 23. Then the reference counter 35 remains set to the count attained just prior to the appearance of this input signal on the input port B11 of the microcomputer 23.
A third mistuning condition can exist, and ordinarily this condition results in an ambiguity which cannot be corrected simply by responding to the signal polarity at the output of the frequency discriminator. This is indicated by the mistuned condition where the difference between the local oscillator frequency f3 and the transmitter frequency is such that the signal f3 lies in the range to the right of the negative portion of the discriminator output shown in the upper waveform of FIG. 5. In this condition, the associated sound causes the discriminator output to be positive; so that the television receiver normally would attempt to tune toward the next adjacent channel and away from the properly tuned center frequency of the channel which is desired. The output of the discriminator 60 in this situation is the same as it was in the first example considered for frequency f1; so that the counter 82 of the microprocessor 23 operates to change the count in the reference counter 35 in a manner to cause the local oscillator frequency to go higher toward a frequency f3 +Δf, as shown in FIG. 5.
A predetermined number of counts of the counter 82 in the microcomputer 23 are necessary for the microcomputer to count through the frequency range Δf, and this range is selected to be within the pull in or operating range of the system. Once this count has been attained, the microcomputer counter 82 immediately is reset back to a count which corresponds to a frequency 2 Δf lower than the frequency attained by the maximum count. This is indicated in FIG. 5 by the frequency f3-Δf. Because the microcomputer counter 82 is limited to counting a number of counts equal to Δf, this new frequency now is on the lefthand side of the center line fc, shown in both waveforms of FIG. 5. This places the local oscillator frequency at a point such that the frequency discriminator output is the positive output shown on the lefthand-side of the upper waveform of FIG. 5. Counting continues in the same direction as previously. This time, however, it is in a proper direction to bring about correct tuning; and when the center frequency is reached, the output of the comparators 62 and 63 cause the microcomputer 23 to stop its count. The proper tuning point attained is indicated at point C on the graph of the lower part of FIG. 5.
Because the counter 82 of the microcomputer is limited to a maximum count equivalent to Δf above its initial count and thereupon is reset to a new count equivalent to 2 Δf lower than the maximum count, it is not necessary to utilize any other sensory inputs in order to properly tune the receiver over a wide pull in range (as much as plus or minus 2 MHz). Only the output of the conventional frequency discriminator 60 is used to provide the necessary sensory inputs.

The counter 82 of the microcomputer 23 is operated by the clock 81 during the foregoing sequence of operation, immediately following the selection of a new channel by the operation of the keyboard 25, at a fast or high speed operation. Typically, the counter steps are 10 milliseconds per step; so that there are no initial visual effects which can be noticed by an observer of the television screen of the receiver being tuned. The maximum forced search period is approximately 900 milliseconds in duration. At the end of this time interval, a timer in the microcomputer 23 causes a signal to be applied through the outputs of the E output port to the decoder circuit 52 indicative of the completion of this time interval. The decoder 52 then applies a pulse on an output lead connected to the B13 input of the B input port of the microcomputer 23. This pulse is sensed by the microcomputer 23 and is applied to the clock 81 to change the clock rate to a much slower rate, approximately one-third (1/3) or one-fourth (1/4) the rate used previously during the forced search mode of operation. This then permits the system to accomodate station drifts which normally occur at a very slow rate during the transmission and reception of a television signal. As a consequence, it is possible to use more filtering in the filter 39 on the tuning line (FIG. 1) and employ a smaller frequency window for the channel verification sensed by the circuitry shown in FIG. 3. The result is a more precise tuning from the receiver than is otherwise possible if only a high speed operation of the clock 81 is utilized.
When the channel once again is changed by operation of the keys in the keyboard 25 or operation of the channel selection circuitry from a remote control unit, this new channel input is sensed by the microcomputer 23 from the signals applied to the A input port and the clock 81 is reset to its fast time or the forced search mode of operation; and the process resumes.
Instead of employing an additional decoding function in the decoder 52, a separate decoder also could be connected to the outputs of the D output ports to feed back the signal to the B13 input terminal of the B input port of the microcomputer 23. The operation of the system to change the rate or frequency of the pulses applied by the clock 81 to the counter 82 otherwise is the same as described above.
Although applicant has found that it is preferable to correct for mistuning or frequency offsets by adjusting the count or division ratio of the counter 35, such offset adjustments also could be effected by adjusting the count in the counter 31 in the local oscillator signal line. The operation in such a case is the same as described above for adjusting the count in the counter 35.
If the receiver is to be used with an automatic signal seek mode of operation, however, additional sensory inputs are necessary. These inputs operate in conjunction with the output of the frequency discriminator 60. The operation of the microcomputer 23 in controlling the count of the reference programmable frequency counter divider 35 is the same as described above. The additional sensory inputs simply are used in conjunction with the outputs of the comparators 62 and 63 to signal the microcomputer 23 to assure that tuning is to a picture channel rather than an adjacent sound channel. This is accomplished by utilizing the output of the synchronizing signal separator 65 which is applied to a comparator 67 to produce an output signal to the SNS1 sensory input of the microcomputer 23 only when vertical synchronizing signal components are present.
In addition, the output of a picture carrier detector 69 is applied to the input of a comparator 70 to produce an output to the B10 sensory input of the microcomputer 23. If the picture carrier detector 69 is producing an output indicative of the presence of a carrier, but no output is being obtained from the vertical synch separator 65 at the same time, the system is mistuned to a sound carrier and the microcomputer 23 is permitted to continue its localized search until a properly tuned station is found. Only when there is coincidence of signals from the picture carrier detector 69, the synch signal separator 65, and the automatic frequency discriminator window as determined by the comparators 62 and 63, is the microcomputer operation terminated to indicate that a properly tuned channel is present.
Further insurance of tuning the receiver only to a strong signal also can be provided by the addition of an AGC amplifier 72. This is connected to a comparator 74 coupled to the B10 input port along with the output of the picture carrier detector comparator 70. When the AGC amplifier 72 is used as a sensory input, the microcomputer operation, when the system is used in a signal seek mode, is only terminated to indicate reception of a valid signal when that signal is strong enough to produce the desired output from the comparator 74. The signal level which is acceptable is set by a potentiometer 75.
It should be noted that when the system is operated in a signal seek mode, the sensory inputs must indicate the reception of a properly tuned signal within a pre-established time period. If no signal is sensed by the various sensory input circuits operating in conjunction with one another as described above, the microcomputer 23 automatically steps to the next channel number and repeats the sequence of operation described above. This is when it is placed in its signal seek mode of operation. If signal seek is not employed, the additional sensory circuits 65, 69 and 72 are not necessary, and the inputs to the microcomputer which are provided from these sensory circuits are not utilized. The sensory signal input which is used both for a receiver without a signal seek capability of operation and for a receiver which has a signal seek mode of operation in it, is the output of the frequency discriminator 60 operating in conjunction with the comparators 61, 62 and 63 as described above.
As indicated above, the wideband method of tuning precisely to an incoming signal that is at the wrong frequency described here only needs the frequency discriminator sensory information. The method that uses the additional sensors described above is needed to make this system operate compatibly with signal seek but it is not restricted to seek operation.

For a system that does not use signal seek operation, only the frequency discriminator sensory input is required for proper operation. The discriminator 60 is used for both fine tuning direction information and to produce a frequency window to indicate the presence of a correctly tuned station (channel verification). Initially, after a channel change, there is a 250 millisecond settling time, the same as the operation described above with compatible seek. After that, however, comes a period of time where a forced localized search is produced by the microcomputer 23. The forced search is needed to insure that the system will correctly tune to stations that initially may be tuned to the undesired zero voltage crossover in the right half of the upper curve of FIG. 5. Such signals may be within the frequency window of the discriminator 60; and if a search is not forced, this system will not correctly tune. The compatible seek system described previously correctly tunes the local oscillator without a forced search, because the picture carrier detector and vertical detector do not give an output for this situation and the system automatically goes into its search mode of operation. However, the non-seek system does not have a picture carrier sensor input and must be forced to search for an initial period of time sufficient to allow the system to tune up to its maximum frequency and then reset (loop) back to a frequency of 2 Δf lower. Then it is tuned to the positive left half portion of the discriminator curve (FIG. 5) and the frequency window created by the discriminator 60 is sufficient to insure proper tuning. If the discriminator output produced by the desired incoming signal created an initial situation that produces the correct tuning direction information, i.e., in the left half of the curve of FIG. 5, or in the right half portion that gives the correct direction and

frequency window information, the forced search would not be needed. However, the forced search will produce a correct tuning situation anyway. In these cases, the tuning either is correct to begin with or correct tuning is reached quickly. Then, even though the forced search is active, it simply alternates up and down through the correct tuning point because each time the receiver is tuned a little high in frequency, it produces a negative output from the discriminator 60; and the tuning direction signal causes the system to tune down in frequency.

Then, a positive discriminator output is produced, and the system tunes up in frequency. This continues until the forced search is removed by time-out of the microcomputer 23 (a fraction of a second). At such time, the receiver is correctly tuned by the frequency window of the discriminator to be very near fc. The system cannot tune to the undesired discriminator crossover shown in the right half portion of FIG. 5 because the polarity of the tuning direction signal always causes it to tune away from that point.
The fast time or forced search operation of the system can be terminated in a different way other than the preestablished time-out period described above in conjunction with the operation of the circuit shown in FIG. 2. Generally, it is desirable to build into the system (or program into the system by means of software) such a maximum time-out period to effect the operation which has been described above to terminate the search and cause the clock 81 thereafter to operate in a low speed mode of operation. Termination also can be accomplished by sensing the number of changes in the direction sensor input applied to the B12 terminal of the B input port to cause the search to be terminated when this direction changes three times (or more). By doing this, any flicker that might be observed on the screen of the television receiver is minimized, since the forced search still takes place at the high rate of application of clock pulses from the clock 81 to the counter 82 in the same manner described above.
Termination of the search, however, also may be effected by means of a search terminate counter 78 (FIG. 3), which is advanced by pulses applied to it each time the output of the comparator 61 changes its sign (indicative of a change in direction for the counter 82) as applied to it through the B12 input port, as described earlier. After three of these changes, or some other number if desired, an output pulse is obtained from the search terminate counter 78 and is applied to the SNS0 input of the microcomputer 23. This causes the operation of the clock 81 to be switched to its low speed mode of operation to terminate the fast or "forced search" mode of operation. The next time a new channel number is entered on the keyboard 25, a reset pulse is applied to the search terminate counter 78 to reset it to its original or zero count, thereby readying it for another sequence of operation. It is apparent that the search terminate counter 78 may not always be operated to terminate the count, since the time-out interval which is sensed by the decode circuit 52 and applied to the B13 input port of the microcomputer 23 may occur before there are three changes of direction of the search. In any event, the next time a new channel number is entered into the keyboard 25, the search terminate counter 78 is reset; so that it is irrelevant whether this counter reaches a full count or not to effect the termination of the forced search operation of the system.
FIG. 4 shows the control sequence of the system which is stored in the ROM (Read Only Memory) of the microcomputer 23. The microcomputer 23 operates by always running through the flow sequence, via loops L1, L2 and L3. Loop L1 corresponds to a new channel selection by two digit number entry. Loop L2 corresponds to channel number increment or decrement by an up or down key operation, respectively, or by seek operation. Loop L3 corresponds to fine tuning, either manual or automatic. To obtain exact timing for system control, the microcomputer 23 receives a standard timing pulse from the output of the reference counter 35 divided in a divide-by-five counter 80 and applied to the A13 input port of the microcomputer 23. The control functions which are programmed into the microcomputer 23, as indicated in the flow chart of FIG. 4, are outlined in the following paragraphs.Channel Number Correction: An invalid two digit channel number entry (0, 1, 84, 99) is corrected. When the operation of the receiver is in the signal seek mode, the next channel up from 83 is channel 2, and the next lower channel from channel 2 is 83.
PLL Control I: For a given channel number, a corresponding binary code for the PLL selector counter 31 is derived as described previously. For UHF channels, the local oscillator frequency separation between two adjacent channels is 6 MHz and the code for PLL is generated by the microcomputer 23 through means of a simple calculation. This code then is transferred from the microcomputer 23 to the latches 44, 45 and 46 as described previously.
PLL Control II: This routine of the microcomputer 23 is used to transfer the fine tuning data to the latches 49 and 50 which control the count of the reference counter 35 in the PLL circuit.
Channel Number Display: The channel number is transferred from the microcomputer 23 to the driver latches of the display driver circuit 29.
Key Input Detection: The keyboard is arranged as the matrix circuit shown in FIG. 2. ROM programming for scanning and acknowledging a keyboard entry only after successive indications provides protection against false entry due to contact bounce. The four data output lines of the D output port of the microcomputer 23 are used to transfer data to the phase lock loop section of the circuit and to the display circuit 29, as well as for scanning the keyboard matrix circuit.
Time Count: The microcomputer 23 receives a basic timing pulse of approximately 200 Hz from the output of the divider 80 and performs various controls for each timing pulse. By way of example, sensing for the vertical synch input (when the system is used with a signal seek capability) on the input port SNS1 takes place every 2.5 milliseconds. Automatic seek timing is selected to be 133 milliseconds for UHF channels. All of these timing pulses are derived from the basic synchronization timing pulse applied to the microcomputer on the A13 input port from the output of the divider 80. Various other timing values used in the microcomputer to properly time multiplex sequence the operation are derived from this basic timing pulse.
Sensor Input Detection: As described previously, the output of the comparators shown in FIG. 3 reflect the status of the tuning of the television receiver. If no signal seek mode of operation is used, only the frequency discriminator or AFT discriminator 60 is necessary. When a system is being used in a signal seek mode, a proper television signal receipt is indicated by the presence of a vertical synch signal at the output of the synch signal separator 65 and corresponding outputs are applied to the input leads B10 and B11 (high level input signals) indicative of tuning to the "correct tuned" frequency discriminator window and reception of a picture carrier. As stated previously, the signal present on the B12 input lead is used to determine the direction of tuning when the receiver is operated in its automatic mode.
Mode Detection: The status of the seek and automatic/manual (A/M) switches are detected. If the A/M switch (not shown) is in its automatic position, automatic seek and offset correction are active. If only the seek switch is on, only seek is performed. If the A/M switch is in manual, manual fine tuning (MFT) is active.
Automatic Mode: If the TV receiver is not properly tuned for VHF channels in automatic, the local oscillator frequency is shifted automatically toward proper tuning. The fine tuning data is generated in the microcomputer 23 and is transferred to the latches 49 and 50 for the reference counter 35 in the PLL circuit.
Manual Fine Tuning (MFT) Control: The local oscillator frequency is shifted by pushing the fine tuning up (U) or down (D) pushbutton or switch. This MFT control can be applied to VHF channels as well as to UHF channels.
Channel Up/Down: When a channel up (upward pointing arrow) or down (downward pointing arrow) key closure in the keyboard 25 is detected, or upon a direct access to an unused channel, this routine is activated and the system will advance to the next channel in the selected direction.The foregoing embodiment of the invention which has been described above and which is illustrated in the drawings is to be considered illustrative of the invention, which is not limited to the specific embodiment selected for this purpose. For example, hard-wired logic could be used to achieve the various circuit operations which are accomplished by the microcomputer 23 in conjunction with the other portions of the system. The relative ease of programming and debugging the microcomputer 23, however, make it much simpler to implement the system operation with the microcomputer than with hard-wired logic. With respect to the sensor circuit inputs to the system, an added degree of operating assurance can be provided by the addition of a sound carrier sensor in addition to the picture carrier sensor shown in FIG. 3. If this feature is desired, the output of the comparator for the sound carrier is combined with the outputs of the comparators 70 and 74 at the input terminal B10 of the B input port of the microcomputer 23. Because of the manner of the circut operation which has been described previously, however, the addition of a sound carrier detector to the system is not considered necessary, even for a system operating in the signal seek mode of operation. This is in contrast to conventional television receivers having a signal seek operation, in which detection of the sound carrier generally is a necessity to insure that mistuning of the receiver to an adjacent sound carrier does not take place.

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Resisting the tide of post-modernity may be difficult, but I will attempt it anyway.

Your choice.........Live or DIE.That indeed is where your liberty lies.

IMPORTANT NOTE: - FRANK SHARP obsoletetellyemuseum.blogspot.comwas founded as a public free WEB Museum to all kind of people and amateur and professional CRT TELEVISION Lovers who enjoy using and/or preserving - restoring vintage CRT Televisions sets, or only curious public who was unaware of that kind of technolgy of the past. The purpose is to provide information about vintage Television Receivers Publicy on the WEB that is generally difficult to locate; all this as a important milestone general worldwide reference for the future, globally in the public interest.obsoletetellyemuseum.blogspot.com does not provide support or parts for any apparatus on this site nor do we represent any manufacturer listed on this site in any way. Catalogs, manuals and any other literature that is available on this site is made available for a historical record only. Please remember that safety standards have changed over the years and information in old manuals as well as the old Television receivers themselves may not meet modern standards. It is up to the individual user to use good judgment and to safely operate old machinery. The obsoletetellyemuseum.blogspot.com web site will assume NO responsibilities for damages or injuries resulting from information obtained from this site. No offer to sell or license — Nothing in this site/Blog may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

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Sure Fun Times, A working TV Discovered with a CRT Oscilloscope !

Safety Hazards:

------------------------------------------------------Safety Hazards in Radio and TV Repair,------------------------------------------------------

People who believe they can conquer nature are clueless that the laws of nature are a precondition of their existence. Their weapon is a miserable idea.When man attempts to rebel against the iron logic of Nature, he comes into struggle with the principles to which he himself owes his existence as a man. And this attack must lead to his own doom.

Anyone attempting to repair any electronic equipment who does not fully understand the shock hazards, as well as the fire hazards associated with working with electronic equipment, should not attempt such procedures! Improperly attempted repair can kill you and burn down your house.Devices that plug into the wall can produce a very lethal electric shock as well cause a fire from incorrect or careless repairs both during servicing or later on.Improper repair of battery operated devices can also result in bad consequences for you, the device, and any equipment attached to it.

Why some people do repairs themselved then? If you can do the repairs yourself, the equation changes dramatically asyour parts costs will be 1/2 to 1/4 of what a professional will chargeand of course your time is free. The educational aspects may also beappealing. You also will learn a lot in the process.

Consumer electronic equipment like TVs, computer monitors, microwave ovens, and electronic flash units, use voltages at power levels that are potentially lethal. Even more so for industrial equipment like lasers and anything else that is either connected to the power line, or uses or generates high voltage.

Normally, these devices are safely enclosed to prevent accidental contact. However, when troubleshooting, testing, making adjustments, and during repair procedures, the cabinet will likely be open and/or safety interlocks may be defeated. Home-built or modified equipment, despite all warnings and recommendations to the contrary - could exist in this state for extended periods of time - or indefinitely.

Depending on overall conditions and your general state of health, there is a wide variation of voltage, current, and total energy levels that can kill.

Microwave ovens in particular are probably THE most dangerous household appliance to service. There is high voltage - up to 5,000 V or more - at high current - more than an amp may be available momentarily. This is an instantly lethal combination.

TVs and monitors may have up to 35 kV on the CRTbut the current isn't low - like a wrong legend saying a "couple of milliamps" but relatively high because of the boost circuit technology and transformer design. However, the CRT capacitance can hold a painful charge for a long time. In addition, portions of the circuitry of TVs and monitors as well as all other devices that plug into the wall socket are line connected.This is actually even more dangerous than the high voltage due to the greater current available - and a few hundred volts can make you just as dead as 35 kV!

Electronic flash units and strobe lights, and pulsed lasers have large energy storage capacitors which alone can deliver a lethal charge - long after the power has been removed. This applies to some extent even to those little disposable pocket cameras with flash which look so innocent being powered from a single 1.5 V AA battery. Don't be fooled - they are designed without any bleeder so the flash can be ready for use without draining the battery!

Even some portions of apparently harmless devices like VCRs and CD players - or vacuum cleaners and toasters - can be hazardous (though the live parts may be insulated or protected - but don't count on it!

This information also applies when working on other high voltage or line connected devices like Tesla Coils, Jacobs Ladders, plasma spheres, gigawatt lasers, hot and cold fusion generators, cyclotrons and other particle accelerators, as well as other popular hobby type projects. :-)

In addition, read the relevant sections of the document for your particular equipment for additional electrical safety considerations as well as non-electrical hazards like microwave radiation or laser light. Only the most common types of equipment are discussed in the safety guidelines, below.

SAFETY guidelines:

These guidelines are to protect you from potentially deadly electrical shock hazards as well as the equipment from accidental damage.

Note that the danger to you is not only in your body providing a conducting path, particularly through your heart. Any involuntary muscle contractions caused by a shock, while perhaps harmless in themselves, may cause collateral damage. There are likely to be many sharp edges and points inside from various things like stamped sheet metal shields and and the cut ends of component leads on the solder side of printed wiring boards in this type of equipment. In addition, the reflex may result in contact with other electrically live parts and further unfortunate consequences.

The purpose of this set of guidelines is not to frighten you but rather to make you aware of the appropriate precautions. Repair of TVs, monitors, microwave ovens, and other consumer and industrial equipment can be both rewarding and economical. Just be sure that it is also safe!

Don't work alone - in the event of an emergency another person's presence may be essential.

Always keep one hand in your pocket when anywhere around a powered line-connected or high voltage system.

Wear rubber bottom shoes or sneakers. An insulated floor is better than metal or bare concrete but this may be outside of your control. A rubber mat should be an acceptable substitute but a carpet, not matter how thick, may not be a particularly good insulator.

Don't wear any jewelry or other articles that could accidentally contact circuitry and conduct current, or get caught in moving parts.

Set up your work area away from possible grounds that you may accidentally contact.

Have a fire extinguisher rated for electrical fires readily accessible in a location that won't get blocked should something burst into flames.

Use a dust mask when cleaning inside electronic equipment and appliances, particularly TVs, monitors, vacuum cleaners, and other dust collectors.

Know your equipment: TVs and monitors may use parts of the metal chassis as ground return yet the chassis may be electrically live with respect to the earth ground of the AC line. Microwave ovens use the chassis as ground return for the high voltage. In addition, do not assume that the chassis is a suitable ground for your test equipment!

If circuit boards need to be removed from their mountings, put insulating material between the boards and anything they may short to. Hold them in place with string or electrical tape. Prop them up with insulation sticks - plastic or wood.

If you need to probe, solder, or otherwise touch circuits with power off, discharge (across) large power supply filter capacitors with a 2 W or greater resistor of 100 to 500 ohms/V approximate value (e.g., for a 200 V capacitor, use a 20K to 100K ohm resistor). Monitor while discharging and/or verify that there is no residual charge with a suitable voltmeter. In a TV or monitor, if you are removing the high voltage connection to the CRT (to replace the flyback transformer for example) first discharge the CRT contact (under the insulating cup at the end of the fat red wire). Use a 1M to 10M ohm 1W or greater wattage resistor on the end of an insulating stick or the probe of a high voltage meter. Discharge to the metal frame which is connected to the outside of the CRT.

For TVs and monitors in particular, there is the additional danger of CRT implosion - take care not to bang the CRT envelope with your tools. An implosion will scatter shards of glass at high velocity in every direction. There is several tons of force attempting to crush the typical CRT. Always wear eye protection. While the actual chance of a violent implosion is relatively small, why take chances? (However, breaking the relatively fragile neck off the CRT WILL be embarrassing at the very least.)

Connect/disconnect any test leads with the equipment unpowered and unplugged. Use clip leads or solder temporary wires to reach cramped locations or difficult to access locations.

If you must probe live, put electrical tape over all but the last 1/16" of the test probes to avoid the possibility of an accidental short which could cause damage to various components. Clip the reference end of the meter or scope to the appropriate ground return so that you need to only probe with one hand.

Perform as many tests as possible with power off and the equipment unplugged. For example, the semiconductors in the power supply section of a TV or monitor can be tested for short circuits with an ohmmeter.

Provide a reliable means of warning that power is applied and that high voltage filter capacitor(s) still hold a charge during servicing. For example, solder a neon indicator lamp (e.g., an NE2 in series with a 100K ohm resistor) across the line input and a super high brightness LEDs in series with 100K, 1 W resistors across the main filter capacitor(s).

Use an isolation transformer if there is any chance of contacting line connected circuits. A Variac(tm) (variable autotransformer) is not an isolation transformer! However, the combination of a Variac and isolation transformer maintains the safety benefits and is a very versatile device. See the document "Repair Briefs, An Introduction", available at this site, for more details.

The use of a GFCI (Ground Fault Circuit Interrupter) protected outlet is a good idea but may not protect you from shock from many points in a line connected TV or monitor, or the high voltage side of a microwave oven, for example. (Note however, that, a GFCI may nuisance trip at power-on or at other random times due to leakage paths (like your scope probe ground) or the highly capacitive or inductive input characteristics of line powered equipment.) A GFCI is also a relatively complex active device which may not be designed for repeated tripping - you are depending on some action to be taken (and bad things happen if it doesn't!) - unlike the passive nature of an isolation transformer. A fuse or circuit breaker is too slow and insensitive to provide any protection for you or in many cases, your equipment. However, these devices may save your scope probe ground wire should you accidentally connect it to a live chassis.

When handling static sensitive components, an anti-static wrist strap is recommended. However, it should be constructed of high resistance materials with a high resistance path between you and the chassis (greater than 100K ohms). Never use metallic conductors as you would then become an excellent path to ground for line current or risk amputating your hand at the wrist when you accidentally contacted that 1000 A welder supply!

Don't attempt repair work when you are tired. Not only will you be more careless, but your primary diagnostic tool - deductive reasoning - will not be operating at full capacity.

Finally, never assume anything without checking it out for yourself! Don't take shortcuts!

Many people who mistakenly feel that ‘old technology’ is somehow more user-friendly, in some strange way automatically good - merely because it is old. Don’t be fooled! Approach old equipment with an open and alert mind and realise that a hot chassis, or a resistor line cord, or asbestos insulation, or selenium rectifiers require much more thought and consideration for safety.

Live chassis are indiscriminate in whom they kill and even if you are a thoughtful, careful kind of person, that doesn’t mean the last person who handled the set was.

Vintage radio and television receivers use 'live chassis' techniques, in which the chassis is connected directly to one side of the incoming mains supply. This means they can be lethal to carry out repair or servicing work on, unless the appropriate safety measures are in place.

Another thing about live-chassis sets - live spindles. We’ve touched on this already but it’s worth making the point once more. The shafts of switches and potentiometers fixed to the chassis may well be at chassis potential and thus live. The bakelite or wood cabinet is insulated but these shafts are not, and if someone lost the proper grub screw and replaced a knob using a cheesehead screw, the next person to grip that knob may get a dose of 250 volts. Originally these grub screws were sealed and embedded in wax but you cannot rely on subsequent tinkerers having the same high standards.

Even in more orthodox apparatus standards of insulation were not always as high as they are now. Soldered connections to HT and mains wiring should always have rubber or plastic sleeving but in times gone by this was often omitted (or it may since have perished). Beware too of kinked and frayed braiding on cloth-covered mains cords, particularly when the cord has a dropper conductor.

If you are not satisfied that you fully understand the risks involved in this sort of work, do not proceed any further. Instead seek advice and assistance from a competent technician or engineer.

Whenever you acquire a new treasure there's always a terrific temptation to try it out. With mains-driven equipment that means plugging it in and seeing if it works. Well don't, not until you have made some quick checks.

Before contemplating connecting any unknown receiver to the mains supply, spend a little time inspecting it for signs of missing or loose parts, blown fuses, overheating or even fire damage. Use a meter to check obvious points to ensure no short circuit exists (e.g. across the mains input). If you then decide to apply power keep clear but be observant since an elderly electrolytic might explode! This can be avoided if you can apply power gradually through a variac. Auto-transformers are handy for supplying reduced power to sets being repaired but they are not a substitute for a proper isolation transformer!

If you are working with electricity and your work area has a concrete floor, a rubber mat is essential, particularly during damp weather! Where possible try to arrange a neat working area away from water or central heating pipes. For safety try to arrange that this area is separate from the area occupied by your family. This is emphasised because inadvertently rushing to answer a telephone you might just leave a TV chassis connected to a supply and curious little fingers know nothing of the dangers of electricity - or, for that matter - the lethal vacuum encased within every picture tube!

Many younger enthusiasts may not be aware of the dangers of mishandling tubes, in particular the old round types found in early TVs. When handling these tubes eye protection should be worn and tubes must not be left lying around, they must be stored in boxes. The glass is surprising fragile and can implode without any provocation or warning. Bits of glass flying around at high speed can be deadly. The notes following are inspired by Malcolm Burrell again.

Picture tubes are perhaps one of the most hazardous items in any TV receiver. This is because most are of glass construction and contain a very high vacuum. If you measured the total area of glass in any picture tube then estimated the pressure of air upon it at 14.7lb. per square inch, you would discover that the total pressure upon the device could amount to several tons! Fracturing the glass suddenly would result in an extremely rapid implosion such that fragments of glass, metal and toxic chemicals would be scattered over a wide area, probably causing injury to anyone in close proximity. In modern workshops it is now a rule that protective goggles are worn when handling picture tubes.

The weakest point in most picture tubes is where the thin glass neck containing the electron gun is joined to the bowl. It is therefore essential that you refrain from handling the tube by its neck alone. Once a tube is removed from the receiver hold it vertically with the neck uppermost and one hand beneath the screen with the other steadying the device by the neck.With larger devices it is sometimes easier to grip the peripheral of the screen with both hands.

Until the advent of reinforced picture tubes, most were mounted in the cabinet or on the TV chassis by some form of metal band clamped around the face.Never support the weight of the tube by this band since it has been known for the tube to slide out! Some of the larger tubes are extremely heavy. It may, therefore, be easier to enlist assistance.

Before starting to remove a tube, first discharge the final anode connection to the chassis metalwork and preferably connect a shorting lead to this connection whilst you are working. It might be convenient to keep a spare piece of EHT cable with a crocodile clip at one end and a final anode connector at the other.

Exercise care when removing picture tubes from elderly equipment. You may find that the deflection coils have become stuck to the neck. It is extremely dangerous to use a screwdriver prise them away. Gently heating with a hairdryer or soaking in methylated spirit is safer.

Disposal of picture tubes also requires care. Unless rendered safe they should never be placed in dustbins or skips. Many engineers swipe the necks off tubes in cavalier fashion using a broom handle but this is not recommended. A safer method is to make a hole in the side of a stout carton, preferably one designed to hold a picture tube. The tube is placed in the carton and the neck broken using a broom handle. The carton should then be clearly labelled that it contains chemicals and broken glass!

Therefore people who believe they can conquer nature are clueless that the laws of nature are a precondition of their existence. Their weapon is a miserable idea.When man attempts to rebel against the iron logic of Nature, he comes into struggle with the principles to which he himself owes his existence as a man. And this attack must lead to his own doom.

Think for yourself. Otherwise you have to believe what other people tell you.

For most people thinking is a matter of fortune.A society based on individualism is an oxymoron.Freedom is at first the freedom to starve.A wise fool speaks, because he has something to say.A fool speaks, because he has to say something.A wise fool is silent, because there is nothing to say.A fool is silent, because he has nothing to say.

Resist or regretWork for what's good for our people

Help stem the dark tideStand tall or be beat downFight back or die

The man who does not exercise the first law of nature—that of self preservation — is not worthy of living and breathing the breath of life.

We now live in a nation where doctors destroy health, lawyers destroy justice, universities destroy knowledge, governments destroy freedom, the press destroys information, religion destroys morals and our banks destroy the economy.The globalist argument is that if only we erase distinctions, obliterate identities, put everyone on a level playing field, etc.. we can eliminate war and everyone can be so prosperous and efficient, such great cogs in a well-oiled global machine.There will be no more historical grievances because people will no longer even care, they'll have no connection to the past, no foolish pride in past accomplishments of people totally unrelated to them.A globalized culture, no borders, everyone a citizen of the world.Know this: I will never acquiesce to this corrupt, inhuman, Borg-like vision. The dangerous lunatics who push us towards their globalized "utopia" are my enemy. How exactly all this will play out, whether through wars, or whether we can thwart the globalist agenda peacefully (this is my hope of course) I don't know. But I do know that unless people are willing to fight and die, globalism will win out in the end.The actual crimes committed by the EU against the European peoples are directly in violation of the 1948 UN genocide convention, Article II: (c) Deliberately inflicting on the group conditions of life calculated to bring about its physical destruction in whole or in part; (d) Imposing measures intended to prevent births within the group; (e) Forcibly transferring children of the group to another group.* The man who does not exercise the first law of nature—that of self preservation — is not worthy of living and breathing the breath of life.

TELEVISION HISTORY IN BRIEF

Television history

At 1928 Baird transmits from London to New York, using his mechanical system.with 30 vertical lines. By 1930 it was clear that mechanical television systems could never produce the picture quality required for commercial success. For this reason mechanical system was rapidly succeeded by the electronic TV systems. The first all-electronic American systems in 1932 used only 120 scanning lines at 24 frames per second Since the mid-1930s picture repetition frequency (field rate or frame rate) has been the same as the mains frequency, either 50 or 60Hz according to the frequency used in each country. This is for two very good reasons. Studio lighting generally uses alternating current lamps and if these were not synchronised with the field frequency, an unwelcome strobe effect could appear on TV pictures. Secondly, in days gone by, the smoothing of power supply circuits in TV receivers was not as good as it is today and ripple superimposed on the DC could cause visual interference. If the picture was locked to the mains frequency, this interference would at least be static on the screen and thus less obtrusive.To determine what electronic system to use, the BBC sponsored trial broadcasts by two systems, one by Baird, with 240 lines, and one by EMI with 405 lines. Scheduled electronic television broadcasting began in England in 1936 using 405-line system (lasted until the 1980s in the UK). Germany made their forst TV broadcasts at 1936 olympics using 180-line TV system. Germany also made their TV broadcasts by the fall of 1937 using a 441-line system. Also fFrance tested TV (455 line system). RCA introduced electronic television to the U. S. at the 1939 World's Fair,and began regularly scheduled broadcasting at the same time (525 line system).In 1940 the USA established its 525-line standard. At year 1941 the 525-line standard, still in use today in USA, was adopted.Russia also produced TV sets before the war (240 and 343 line systems).World War Two interrupted the development of television. Immediately after World War Two production of TV sets started in the U.S-In USA there was TV broadcasts and few throusand receivers at 1945. In the early 1950s, two competing color TV systems emerged: CBS sequential color (used color wheel) and RCA dot sequential system. At 1953 color broadcasting officially arrives in the U.S. on Dec. 17, when FCC approves modified version of an RCA system.It calls this new RCA color system "NTSC" color. The first NTSC color TVs were on the marker at 1954.In Europe the TV broadcasts started to use experiment using 625 line system 1950s. This standard is used nowadays throughout Europe. France also tried 819 line system at the same time (this system was in use to 1980s). The rest of Europe opted for 625 lines, a system devised in 1946 by two German engineers, M??ller and Urtel (it appears that the Russians came up independently with a very similar system). The use of PAL color standard started at around 1967 and is still in use. The SECAM color system (used in France) testing started also at 1967. The TV broadcasting history has not ended. The newst thign is digital television. It is expected that terrestrial television will open up billion-dollar opportunities for those companies and organisations best prepared to embrace this new broadcasting era. At 1996 small digital satellite dishes hit the market. They become the biggest selling electronic item in history next to the VCR.

Using TV 24H

TV has something for everyone. Idiots, intellectuals, fans of all sorts. Some people are couch potatoes, watch anything just to sit there and be mindless. That's their problem. Children have always needed to be monitored by their parents. If people gotta a mind for it they could figure out the real news even without the internet and there has always been a library.

Is TV bad in and of itself? The researchers aren’t saying that. But we all know that watching television is a solitary, isolating occupation that keeps you sedentary. Sitting in front of the boob tube reduces the time you have available to exercise, interact with your family, read books, and be outdoors. This new research dovetails with other studies, which have linked excessive TV time to obesity and higher rates of cardiovascular disease.

watching too much television can jeopardize your whole family’s health.

This should be a wake-up call to all adults. Stay active. Go outside. Spend time with your spouse and your children with the television off. Read a book and do crossword puzzles to stimulate your imagination and your brain. Reduce your screen time as much as you can.

The National Cancer Institute researchers suggest that watching TV is a public health issue. The price we are paying for our technology-driven lives may be much higher than we previously realized !

DON'T WATCH TV AT ALL !!

The Propaganda TV Machine a.k.a. The Ministry of Truth delivers The Truth from The Government to the people.

At least, that's what they say. In fact, a Propaganda Machine is only employed by The Empire and used to brainwash people into Gullible Lemmings who believe that everything is all right when in fact, it isn't, and that the very people who could help them are their enemies.

Girl Looking TV.

Happy Times:

Do you remember when a telly looked like a real telly? When it was a piece of furniture that you lavished love on, even polished from time to time ?When it was a piece of somewhat at looking in to ?When it was a piece of Highest tech looking inside ? First, this site is a Digital free, HD free, flat panel, HDMI, China, Turks, Afrika free zone. All in all a wealth of vintage information at your finger tips, a one stop unique experience. So step on in, leave the modern throw-away world behind, travel back in time to a vintage world of repair and enjoy.This site has stirred memories about the watching TV's days on a CRT TUBE television......Childhood memories, your parents getting their first colour tv, a b/w or color portable, perhaps memories of renting or buying your first set remote featured, perhaps your days working in the trade, selling or repairing them....... If you enjoyed this site, found its content left you all misty eyed then just talk about it as it would be very welcome............like the time to recover and restore a set ................and happy reminiscing.

Digital TV in Brief.

Digital TV:

Digital television is a hot topic now.If you have looked at television sets at any of the big electronics retailers lately, you know that Digital TV, or DTV, is a BIG deal right now in the U.S. In Europe Digital TV is also a hot topic, because many countries have started terrestrial digital TV broadcasts and plan to end analogue broadcasts after some years (will take 5-10 years). Satellite TV broadcasts have also shifted very much to digital broadcasts.The main advantage if digital broadcasts are that it does not havethe picture quality problems of analogue TVs (it had it's own videoproblems caused by video compression), it allowes putting more TV channels to same medium (TV channel frequencies and satellites) and it allows new services (like HDTV and interactive multimedia). The digital brodcasts are generally designed to use such modulation that the digital data stream (typically around 20-30 Mbit/s) is modulated to the same bandwidth (around 6 MHz) as the analogue TV broadcasts. The used modulation vary between different media, which means thatdifferent modulation techniques are used in terrestrial transmissions, cable TV and satellite. Different modulations are used because of the different characteristics of those transmission medias. There is not on "digital TV", but several different variations of it in use.The basic technology of digital TV, known as MPEG 2 video compressionand MPEG 2 transmission stream format, is same around the world, butis is used somewhat differently in different standards used in differentcountries.

USA uses ACTS Digital Televisio Standard, which standardizes NTSC format transmissions, HDTV transmission, sound formats and data signal modulation in use. The ATSC MPEG-2 formats for DTV, including HDTV, uses 4:2:0 samling for video signal. The US system uses a fixed power and a fixed maximum bitrate, at which some bits are always transmitted. That rate is typically 19.3 Mb/sec.

Europe uses DVB (Digital Video Broadcasting) standard. This standardallows basically normal PAL resolution transmisssion (vasically HDTVcould be added later but is not yet standardized) with several audio formats, digital data rates and digital signal modulation. There are several different variations fo DVB standard for different media:

DVB-T for terrestrial broadcastsDVB-S for satelliteDVB-C for cable TV

Those different DVB versions varyon the data signal modulation methods, error correction and frequency bands used. DVB and option for some interactive extra services, but thestandardization of this is not ready here yet(there are fire different incompatible interactive servicessystems in use in different countries and by different broadcasters).

The process of transmitting digital TV signal is the following: Analog video/audio - digitisation - MPEG compression - Multiplexing ( youcan now call it digital) - Preparation for transmisson - modulation toanalog carrier.Reception process is the following: Demodulation of analogue carrier - Error correction - Demultiplexing - MPEG decompression - DA conversion to get analogue signal (unless you use digital display). The analoguie video signal that gets digitized can be practically from any video source, for example produced with old analogue video production equipment and distributed with a video tape. In high-end system the information is analogue only in the image sensor on the video camera, and from this on the signal gets digitally processed. In many real-life TV production systems the reality is something between those two extremes.

At least in Europe, the signal level requirements for DVB-T are well below the analog requirements, so the transmitter power is much less than on the analog side. In the NorDig recommendation the minimum received signal level for 64QAM, 7/8 code rate with a Rayleigh fading path and 8 dB receiver noise figure would be -64 dBm. With other code rates, modulations and fading mechanisms, the requirement is lower. Many receivers can perform much better at conditions where there is no fading (a quasi error free less than one uncorrected error/hour signal even at 27 dBuV (-82 dBm) with 64QAM and 8 MHz channel width). For analog signals, the recommended level is more than 1 mV (+60 dBuV, -49 dBm). While the ERP can be at least 10 dB lower than analog, the question of power consumption is more complicated, since COFDM with 64QAM carriers require a quite good linearity, which may affect the efficiency and hence power consumption.

Digital TV system in use in USA

The FCC mandate to change our broadcast standards from NTSC analog to ATSC digital broadcasting (DTV) is big bold move, requiring changes in everything from the way the studios shoot video, the format that's transmitted, to the equipment we use to receive and watch broadcastsDTV (digital TV) applies to digital broadcasts in general and to the U.S. ATSC standard in specific. The ATSC standard includes both standard-definition (SD) and high-definition (HD) digital formats. The notation H/DTV is often used to specifically refer to high-definition digital TV. The federal mandate grants the public airwaves to the broadcasters to transmit digital TV in exchange for return of the current analog NTSC spectrum, allowing for a transition period in the interim. At the end of this period scheduled for 2006, broadcasters must be fully converted to the 8VSB broadcast standard. Digital Television ("DTV") is a new broadcast technology that will transform television. The technology of DTV will allows TV broadcasts with movie-quality picture and CD- quality sound and a variety of other enhancements (for example data delivery). With digital television, broadcasters will be able to offer free television of higher resolution and better picture quality than now exists under the current mode of TV transmission. If broadcasters so choose, they can offer what has been called "high definition television" or HDTV, television with theater-quality pictures and CD-quality sound. . Alternatively, a broadcaster can offer several different TV programs at the same time, with pictures and sound quality better than is generally available today. HDTV (high-definition TV) encompasses both analog and digital televisions that have a 16:9 aspect ratio and approximately 5 times the resolution of standard TV (double vertical, double horizontal, wider aspect). High definition is generally defined as any video signal that is at least twice the quality of the current 480i (interlaced) analog broadcast signal. There are 18 approved formats for digital TV broadcasts, but only two (720p/1080i) are proper definition of the term HDTV. The advent of high definition has allowed monitors to read images differently, either in standard interlaced format or progressively. Sets that do not have any decoding capabilities but can display the high-resolution image is often labeled as "HD-Ready" a term that describes 80% or more of the Digital TVs on the market. HDTV displays support digital connections such as HDMI (DVI) and IEEE 1394/FireWire, although standardization is not finished. HDTV in the US is part of the ATSC DTV format. The resolution and frame rates of DTV in the US generally correspond to the ATSC recommendations for SD (640x480 and 704x480 at 24p, 30p, 60p, 60i) and HD (1280x720 at 24p, 20p, and 60p; 1920x1080 at 24p, 30p and 60i). In addition, a broadcaster will be able to simultaneously transmit a variety of other information through a data bitstream to both enhance its TV programs and to provide entirely new services. The technical specifications of USA DTV system is defined in ACTS Digital Television Standards.

Digital TV in Europe

Digital TV brodacasting in Europe is done according to DVB standards. DVB technology has become an integral part of global broadcasting, setting the global standard for satellite, cable and terrestrial transmissions and equipment. There are three versions of DVB in use: DVB-S, DVB-C and DVB-T.DVB-T is a flexible system allowing terrestrial broadcastersto choose from a variety of options to suit their various service environments. This allows the choice between fixed roof-top antenna, portableand even mobile reception of DVB-T services. Broadly speaking the trade-off in one of service bit-rate versus signal robustness.

DVB-T network is very flexible. Having many transmitters all on the same frequency is not a problem for the used COFDM based system. COFDM has been chosen and designed to minimise the effects of multipath in obstructed reception areas. In fact multipath signals can significantly improve the overall received signal with no adverse effects. These properties are particularly valuable for radio cameras and mobile links. DVB-T because of its unique design which allows single frequency networks (SFN). This means that many transmitters along the planned routes can transmit on the same frequency. It is also possible to use simple gap fillers that amplify and retransmit the signal. In-air digital TV broadcasts in Europe use DVB-T. 8 MHz of bandwidth may be used to provide a 24 Mbps digital transmission path using Coded Orthogonal Frequency Division Multiplexing (COFDM) modulation (theoretical maximum 31.67 Mbits for 8 MHz bandwidth). In cases where less bandwidth is available (6 or 7 MHz), the data rate is somewhat lower (around 20 Mbit/s).

DVB-C does the same function as DVB-T, but the modulation used in this system is optimized to operate well in cable TV networks. The modulation used in DVB-C is QAM. Systems from 16-QAM up to 256-QAM can be used, but the system centres on 64-QAM, in which an 8MHz channel can accommodate a physical payload of about 38 Mbit/s. Digital cable TV in Europe uses DVB-C. The DVB standard for the cable return path has been developed jointly with DAVIC, the Digital Audio Visual Council. The specification uses Quadrature Phase Shift Keying (QPSK) modulation in a 200kHz, 1MHz or 2MHz channel to provide a return path for interactive services (from the user to the service provider) of up to about 3Mbit/s. The path to the user may be either in-band (embedded in the MPEG-2 Transport Stream in the DVB-C channel) or out-of-band (on a separate 1 or 2MHz frequency band).

DVB-S is the satellite version of DVB. Satellite transmission has lead the way in delivering digital TV to viewers. Established in 1995, the satellite standard DVB-S is the oldest DVB standard, used on all six major continents. QPSK modulation system is used, with channel coding optimised to the error characteristics of the channel. A typical satellite channel has 36 MHz bandwidth, which may support transmission at up to 38 Mbps (assuming delivery to a 0.5m receiving antenna) using Quadrature Phase Shift Keying (QPSK) modulation. 16 bytes of Reed Solomon (RS) coding are added to each 188 byte transport packet to provide Forward Error Correction (FEC) using a RS(204,188,8) code. For the satellite transmission, the resultant bit stream is then interleaved and convolutional coding is applied.

The core of the DVB digital data stream isthe standard MPEG-2 "data container",which holds the broadcast and service information.This flexible "carry-all" can containanything that can be digitised, includingmultimedia data. The MPEG-2 standards define how to format the various component parts of a multimedia programme (which may consist of: MPEG-2 compressed video, compressed audio, control data and/or user data). It also defines how these components are combined into a single synchronous transmission bit stream. The process of combining the steams is known as multiplexing. The multiplexed stream may be transmitted over a variety of links, standards / products.Each MPEG-2 MPTS multiplex carries a number of streams which in combination deliver the required services. A typical data rate of such multiplex is around 24 Mbps for terrestrial brodcasts.

European DVB systems currently transmit only standard definition TV signals and set top boxes also handle only normal TV resolution. It would be possible to transmit HDTV signals on DVB data stream, but those broadcasts have not yet started in any wide scale. There is one satellite broadcater that broadcasts HDTV DVB signals in Europe (some cable TV operators carry that signal on their cable).

Many DVB-T integrated TV sets, and some set top boxes, in the Europe come with a Common Interface slot - which is pretty much the same form-factor as a PC Card (aka PCMCIA) used in PC laptops. This CI slot accepts a Conditional Access Module, in the same way that DVB-S receivers do, which implements at least one (some can do more than one) decryption algorithm. This CAM may also, itself, have a smart card slot to accept a consumer subscription card to authorise decryption - you plug your smartcard into your CAM and your CAM into the CI slot in your receiver/IDTV. Some DVB receivers have an integrated CAM (in the case of some receivers this is implemented purely in software, with no extra hardware required) rather than a CI slot to plug in a 3rd party device. With these type of receivers you just plug in the smart card and don't have to worry about CI slots and buying CAMs. So there is an interface standard for DVB - but different broadcasters can chose different encryption schemes, requiring different CAMs for decryption.

DVB Standards and related documents are published by the European Telecommunications Standards Institute (ETSI). These include a large number of standards and technical notes to complement the MPEG-2 standards defined by the ISO.

There are few different standard how interactive TV functionaly is implemented in DVB-systems in use in differenct countries. DVB-MHP is one gaining some acceptance. Multimedia Home Platform (MHP) is the open middleware system designed by the DVB Project (www.dvb.org).

Obsolete Technology Tellye ! Visitors From 15/May/2012:

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