The Billion Cycle Challenge Seminar is coming to Paris(*), London and Munich in February - Register Now. Seating is limited.

Presented by EVE and Synopsys, this seminar promotes a new methodology to address HW/SW Co-Verification of complex SOCs and ASICs.

This seminar already won great reviews and has been called "innovative", an "eye-opener" and "a must-see" by designers in the US and Japan.

Using lessons learned from real projects, the seminar provides a solution to the Billion Cycle Challenge. Whether your chip goes into a cell phone, a network router or a set-top-box, the Billion Cycle Methodology gives you a faster path to high-quality working silicon, including functional software, firmware, operating system and application.

This half-day seminar starts at 9am (on-site registration opens at 8:30am) and includes lunch.

Who Should AttendRTL Hardware designers, verification engineers, ESL system architects, R&D managers, firmware and embedded software managers.
(*) The Paris edition of the seminar will be conducted almost entirely in French. Other locations will be conducted in English.