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The new system LSI chips with eDRAM will be manufactured using advanced technologies on NEC Yamagata's 300-millimeter (mm) production lines.

Embedded DRAM technology integrates DRAM on the same chip with logic circuits, and is viewed as an optimal solution for three-dimensional (3D) graphics acceleration systems and other applications that need to process high bandwidth data using low power. In the past, the integration of an eDRAM structure with a standard CMOS process proved challenging. NEC Electronics achieved its fully CMOS-compatible eDRAM technology by integrating a metal-insulator-metal 2 (MIM2) stacked DRAM capacitor on the company's standard CMOS process.

NEC Electronics first introduced MIM2 technology on 90 nm eDRAM in 2005, and volume production started that same year. The technology requires a material with a high dielectric constant to be placed between two electrodes, and a large charge to be maintained on the capacitor with low leakage and a small cell size. NEC Electronics has achieved this by 1) using a MIM structure for the electrodes in the DRAM cell to achieve lower resistance values and higher data processing speeds, 2) using cobalt-silicide (CoSi) DRAM cell transistors to increase driving performance, and 3) using zirconium-oxide (ZrO2) in the capacitance layer (ahead of other vendors) to increase capacitance of the unit area. These and other breakthroughs have allowed NEC Electronics to develop eDRAM chips using its most advanced 90 nm process and to secure its roadmap to 55 nm eDRAM and beyond.

Available now with NEC Electronics' unique 90 nm CMOS-compatible eDRAM process, the ASICs deliver significant advantages that promise to continue along the technological roadmap toward 55 nm processes and beyond.