The 68020 and 68030 CPUs were designed with the separate 68881 chip in mind. Their instruction sets reserved the "F-line" instructions - that is, all opcodes beginning with the hexadecimal digit "F" were "traps" which would throw an interrupt, handing control to the computer's operating system. If a 68881 were present in the system, the CPU would allow it to execute the instruction. If not, the OS would either call an FPU emulator to execute the instruction using 68020 integer-based software code, or would return an error code to the program.
The CPU/FPU pair were designed such that both could run at the same time. When the CPU encountered a 68881 instruction, it would hand the FPU all operands needed for that instruction, and then the FPU would release the CPU to go on and execute the next instruction.
When the Motorola 68040 processor was introduced, it included the FPU internally. Most instructions and numeric representation modes from the 68881 were supported in hardware, but some were not, and were emulated through a software package.

The Motorola 68882 was an improved version of the 68881, with better pipelining, and eventually available at higher clock speeds. Its instruction set was exactly the same as that of the 68881. Motorola claimed in some marketing literature that it executed some instructions 40% faster than a 68881 at the same clock speed, though this did not reflect typical performance at all.