Compression of items to minimize the required space*Multiple address spaces can now be shown as part of the same connection

Filtering options added

+ Memory connectivity analysis now manages also instances with identical names+ File paths within filesets now accept URI expressions+ Files can be drag-dropped to filesets from the file system+ Memory map visualization items have now bigger area for expand/collapse+ Port direction is now checked when a default value is set+ Port map invert and tieoff are now also shown on the top level of tree hierarchy+ Zooming now follows mouse location in design+ Enhanced usage of drafts in design:

+ New design for port map editor:
* Added feature to auto-connect logical and physical ports
* Logical and physical bounds are now easily editable + Added support for tieoff values in design and port maps+ Added feature to copy memory-elements along with their sub-elements+ Improved expression support:
* Basic comparison operators are now accepted
* Values true/false are now accepted+ System group names are now visible and editable in Bus editor+ Generated Verilog parameters are now correctly ordered for references+ Performance improvements