The Pentium 4 Goes Mainstream

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Just how good is the Pentium 4 with SDRAM? The answer, like most things in life, is “it depends”. We recently had the chance to take a close look at the Intel 845 chipset, and were able to contrast it with the Intel 850 and an almost-shipping motherboard using VIA’s P4X266 Pentium 4 DDR chipset. (Intel recently sued VIA over the P4X266 for intellectual property infringement). We also compared to a common Athlon DDR-based platform to gauge how the Pentium 4 using SDRAM shapes up.

The Intel 845 Intel is releasing the 845 chipset today. From the perspective of companies that build and sell systems, the 845 allows them to build PCs using the Pentium 4 and cheap SDRAM. This results in Pentium 4 systems that are very low cost. We’ve seen Pentium 4 system prices under $800 recently, and the price is still declining. It also signals the final curtain for the desktop Pentium III CPU, which has been Intel’s mainstay for the past few years.

Maximizing Bandwidth

The first wave of 845 boards will only support PC133 SDRAM. According to Intel, they’re still in the process of qualifying DDR memory solutions, and don’t anticipate any 845 boards supporting DDR memory until early in 2002. PC133 SDRAM has a maximum memory bandwidth of about 1.06GB/sec. This isn’t nearly enough for the Pentium 4, which is designed to consume up to 3.2GB/sec of memory bandwidth–akin to trying to feed a fire hose from a garden faucet. Intel had to do some clever engineering to eke out every last iota of bandwidth from the limited memory bandwidth.

Feature comparison of the leading Intel chipsets

Feature

Intel 815E/EP

Intel 850

Intel 845

Memory Technology

SDRAM

Dual Channel RDRAM

SDRAM

Memory Types

PC100/133

PC800/PC600

PC133

Peak memory B/W

1.06GB/s

3.2GB/s

1.06GB/s

Max Memory

512MB

2GB

3GB

AGP

AGP4X

AGP4X

AGP4X

I/O

ICH2

ICH2

ICH2

Process Technology

0.25um

0.25um

0.18um

FSB

133MHz

400MHz

400MHZ

Cache Line

32 Bytes

64 Bytes

64 Bytes

Internal Data paths

64 Bits

256 Bits

256 Bits

Write cache

No

Yes

Yes

In Order Queue (IOQ) depth

4

8

12

Open pages

4

8

24

Refresh

Flexible

Burst-only

Flexible

Dynamic Bus Inversion (DBI)

No

Yes

Yes

ECC

No

Yes

Yes

Packaging

544 BGA

615 OLGA

593 FCBGA

Staggered balls

No

No

Yes

Caps on package

No

No

Yes

Memory clock

Common

Source-synch

Source-synch

Memory electricals

Impedance comp

Current / temp calibration

Impedance Slew Rate comp

Source: Intel Corp.

The 845 adds several features to maximize the meager memory bandwidth available with PC133 SDRAM:

The number of open memory pages increases to 24; the 815E could only have four open memory pages, while the 850 supported eight. This helps reduce memory latency and increase access to memory in multitasking situations.

The in-order depth queue (IOQ) has been increased from the 850’s eight to 12 on the 845 to more efficiently manage read requests.

Memory refresh rates are flexible. This feature was actually introduced with the Intel 815. DRAM needs to be periodically refreshed to maintain their states (it’s just a bunch of tiny capacitors, after all). However, the refresh cycle does eat a bit into memory bandwidth. The 845 performs refresh cycles during periods of relatively low memory activity, so that memory bandwidth during high activity intervals is maximized.

All of these features combine to make the 845 probably the most efficient SDRAM memory controller on the market. It’s still not a balanced solution–the bandwidth hungry Pentium 4 still spends some time waiting for data. However, these features position the 845 well for the time when Intel releases the DDR variant. Intel is quick to point out that the 845 isn’t really competition for the 850, which the company positions as its performance solution. Instead, it’s really the titular successor to the 815 family.

In addition to features that are designed to wring out the last drop of memory bandwidth from PC133, Intel has added features to make life easier for board designers:

Dynamic Bus Inversion (DBI) is perhaps the most interesting. If you send a data word that’s all 0’s, which is then followed by a word that consists of all 1’s, the abrupt signal flip can create some signal noise on the bus. If we assume that a word with all 0’s consists of the signal lines pulled low, then a word that’s all 1’s will have all the signal lines pulled high. DBI adds a signal that tells the system that the following word will have the low and high signals swapped. In our extreme example above, the two words would both have signal lines pulled low, except for the DBI line. This tells the system that the next word is all 1’s, even though the signals are still in the same state. This makes for better system bus signal integrity and lower power consumption.

Unlike the 815, the 845 can make use of ECC memory. This makes the 845 an attractive option for low cost servers, though the DDR version will be much better suited to this.

The 845 is designed with a staggered ball array. This means that the connection to the motherboard no longer consists of a purely parallel, rectangular ball grid array (see Figure 1). This will allow board designers to more easily create four layer motherboards, lowering cost.

Intel’s put a lot of effort into making motherboard design an easier task, which is already resulting in a flood of 845 boards coming out of the far east.

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