Title (fr)

Publication

Application

Priority

US 17081998 A 19981013

Abstract (en)

[origin: US6011722A] A method for programming and/or erasing an array of stacked gate memory devices such as EPROM and EEPROM devices in a NOR array is disclosed. In the method, either a program verify or an erase verify is performed intermittently with the programming of a device or the erasure of the array. During the program-verify, one of either a negative VCS is applied to the deselected devices in the array, a negative VBS is applied to both the selected and deselected devices in the array, or both conditions are applied. Performing the program verify or erase verify in this manner is efficient and accurate. During the programming step, it is also advantageous if one of either a negative VCS is applied to the deselected devices in the array, a negative VBS is applied to the selected devices in the array, or both. With the application of a negative VCS to the deselected devices during programming, if there are any over-erased devices in the array, the presence of the over-erased devices will not adversely affect the programming of the devices.