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Digital spike filter with scannable nodes

Publishing Venue

Siemens

Related People

Other Related People:

Juergen Carstens - CONTACT

Abstract

In digital designs filters have to be implemented to clean up incoming external signals like interrupts from spikes. The filter of this invention eliminates high as well as low signal pulses, which are shorter than the group delay of the delay line used.
Innovation of this design
Filtering as described above has been done so far by connecting two complete spike filters in series. This results in redundant logic especially, if the delay line is considerably long. Another approach already uses the one line, but the output signal is generated by multiplexers using a combinatorical feedback loop, which is a problem for static timing analysis in general. Additionally, the logic may be modified by the logic optimizer of the synthesis tool, so that direct instantiation of multiplexers is required.
These problems can be prevented by using a RS FF which has not to be necessarily a scan FF. The advantages of this approach are:
 No redundant logic and reduced area, since only one delay line is used.
 No combinatorical feedback loop.
 Improved test coverage: only one node is not covered in structural tests like scan.
 The functional test of the filter can be reduced to a simple „static signals passing“ test.
Although a sequential element is used here, the filter still works completely asynchronous using the set / reset inputs of the RS FF. The data signal experiences no inversion.

Copyright

SIEMENS AG 2003

Country

Germany

Language

English (United States)

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Digital spike filter with scannable nodes

Idea: Tim Weyland, DE-Munich

In digital designs filters have to be implemented to clean up incoming external signals like interrupts from spikes. The filter of this invention eliminates high as well as low signal pulses, which are shorter than the group delay of the delay line used.

Innovation of this design

Filtering as described above has been done so far by connecting two complete spike filters in series. This results in redundant logic especially, if the delay line is considerably long. Another approach already uses the one line, but the output signal is generated by multiplexers using a combinatorical feedback loop, which is a problem for static timing analysis in general. Additionally, the logic may be modified by the logic optimizer of the synthesis tool, so that direct instantiation of multiplexers is required.

These problems can be prevented by using a RS FF which has not to be necessarily a scan FF. The advantages of this approach are:

- No redundant logic and reduced area, since only one delay line is used. - No combinatorical feedback loop.

- Improved test coverage: only one node is not covered in structural tests like scan. - The functional test of the filter can be reduced to a simple "static signals passing" test.

Although a sequential element is used here, the filter still works completely asynchronous using the set / reset inputs of the RS FF. The data signal experiences no inversion.

Funcionality

Static signal passing:

Assuming input in=0, the reset input of the FF (R) is active, resulting in out to be static 0. In case of in changes to 1, the reset input (R) will become inactive and set input (S) will become active, as soon as the rising edge has passed the delay line, resulting in out=1. So, static signals are passed without signal inversion.

Spike processing:

A falling edge on in will not show any effect until the incoming pulse is long enough, so that d_in and in both get 0. So, a spike of a length less the group delay of the delay line 1>0>1 will not be passed, since the FF1 keeps the value of out stable due to the data feedback (fig. 1).

In fact, FF1 not even needs to be clocked, since ist output value is kept stable anyway without clock.

This works vice versa with a rising edge on in where the NAND gate (plus inverter) filters a 0>1>0 spike.

Glitches and metastability:

Metastability of the design is prevented, since switching of R and S at the same time is impossible due to the subsequent switching of the AND and NOR gates (see transitions in fig. 2). The inverter after the NAND, which causes a delay to the signal at the S input, gives additional security. Transitions on R or S simultaneous to a rising clock edge do not affect the integrity of the filter logic.

Scan and test coverage:

For scan and other structural test modes a bypass multiplexer masks out the delay line signal to achieve control ability of node d_in. Test point B may be connected to any other node,...