TSMC says equipment vendors late for 14 nm

September 08, 2011 // Rick Merritt

Time is running out to make critical decisions for how to make 14-nm chips expected to hit production in 2015, and capital equipment vendors are falling behind. That was the upshot of a talk by the top R&D executive at Taiwan Semiconductor Manufacturing Co., (TSMC) at Semicon Taiwan.

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TSMC believes it needs to move to next-generation lithography and 450-mm wafers to make 14-nm chips cost effectively, but capital equipment makers threaten to miss the foundry's schedule on both fronts. "Every day we become more and more concerned," said Shang-Yi Chiang, senior vice president of R&D of TSMC.

Fabs need throughput of more than 100 wafers per hour. But so far extreme ultraviolet (EUV) lithography offers just five wafers per hour at best. Two alternatives using multiple e-beam direct write approaches get less than one.

Similarly, TSMC "put out our wish list for 450-mm wafers a few months ago, but some in the capital equipment industry felt it was too aggressive so now we dont know" what the schedule will be, Chiang said to EE Times after his talk. "We may have to do what we did at the 130-nm generation when some capacity was on 200- and some on 300-mm wafers," he said.

TSMC currently plans to bring up a pilot 450-mm wafer line at its Fab 12 in Hsinchu, followed by a production line in Taichung. The larger wafers are needed both to help keep pace with Moore's Law and to lower wafer costs as much as 30 percent.

The 450-nm wafers enable foundries to use fewer fabs, saving significant money on both land and labor costs. To meet expected demand for 32 million eight-inch equivalent wafers, TSMC could hire 20,000 engineers to run 22 plants. If it has to use today's 300-mm wafers the same output would require 29 plants and 27,000 engineers, Chiang estimated.

"450-mm wafers are not a technical issue but an economic issue which is probably more important than technical issue these days," Chiang said.

In lithography, today's 193-nm immersion systems will serve both the 28-nm node TSMC is ramping now and the next-generation 20-nm node. But at 20 nm, fabs will need to use double patterning, essentially running wafers through some exposure processes twice to draw finer lines.

At 14 nm the amount of double patterning with immersion systems could become prohibitively expensive for many customers. So TSMC will start testing a prototype 3100 series EUV machine from ASML in two weeks. It has already been testing an e-beam system from Mapper Lithography BV and will install another from KLA Tencor next year.

"If we cannot get EUV or e-beam to 100 wafers per hour throughput, we see few customers will be willing to continue migrating to finer technology nodes because of the cost," he warned.

TSMC hopes to ramp a 14-nm process in 2015 so "we have to make this decision [on lithography] early next year," Chiang said. "If we focus on using 193-nm immersion it becomes difficult to switch to EUV later on, [and] design rules will be defined based on the choice of lithography, so time is running out," he said.

Time is running out to make critical decisions for how to make 14-nm chips expected to hit production in 2015, and capital equipment vendors are falling behind. That was the upshot of a talk by the top R&D executive at Taiwan Semiconductor Manufacturing Co., (TSMC) at Semicon Taiwan.

TSMC believes it needs to move to next-generation lithography and 450-mm wafers to make 14-nm chips cost effectively, but capital equipment makers threaten to miss the foundry's schedule on both fronts. "Every day we become more and more concerned," said Shang-Yi Chiang, senior vice president of R&D of TSMC.

Fabs need throughput of more than 100 wafers per hour. But so far extreme ultraviolet (EUV) lithography offers just five wafers per hour at best. Two alternatives using multiple e-beam direct write approaches get less than one.

Similarly, TSMC "put out our wish list for 450-mm wafers a few months ago, but some in the capital equipment industry felt it was too aggressive so now we don’t know" what the schedule will be, Chiang said to EE Times after his talk. "We may have to do what we did at the 130-nm generation when some capacity was on 200- and some on 300-mm wafers," he said.

TSMC currently plans to bring up a pilot 450-mm wafer line at its Fab 12 in Hsinchu, followed by a production line in Taichung. The larger wafers are needed both to help keep pace with Moore's Law and to lower wafer costs as much as 30 percent.

The 450-nm wafers enable foundries to use fewer fabs, saving significant money on both land and labor costs. To meet expected demand for 32 million eight-inch equivalent wafers, TSMC could hire 20,000 engineers to run 22 plants. If it has to use today's 300-mm wafers the same output would require 29 plants and 27,000 engineers, Chiang estimated.

"450-mm wafers are not a technical issue but an economic issue which is probably more important than technical issue these days," Chiang said.

In lithography, today's 193-nm immersion systems will serve both the 28-nm node TSMC is ramping now and the next-generation 20-nm node. But at 20 nm, fabs will need to use double patterning, essentially running wafers through some exposure processes twice to draw finer lines.

At 14 nm the amount of double patterning with immersion systems could become prohibitively expensive for many customers. So TSMC will start testing a prototype 3100 series EUV machine from ASML in two weeks. It has already been testing an e-beam system from Mapper Lithography BV and will install another from KLA Tencor next year.

"If we cannot get EUV or e-beam to 100 wafers per hour throughput, we see few customers will be willing to continue migrating to finer technology nodes because of the cost," he warned.

TSMC hopes to ramp a 14-nm process in 2015 so "we have to make this decision [on lithography] early next year," Chiang said. "If we focus on using 193-nm immersion it becomes difficult to switch to EUV later on, [and] design rules will be defined based on the choice of lithography, so time is running out," he said.

450mm wafers cut engineering and land costs, TSMC said.

Lithography costs soar for immersion at 14nm, TSMC said.

Chiang suggested immersion lithography would be too expensive at 14 nm, exceeding traditional guidelines of half the capital equipment costs for a node. Despite the enormous costs of EUV and e-beam machines, estimated at as much as $120 million, they are still cheaper than immersion given the double patterning problems.

E-beam and EUV systems cost roughly the same. But E-beam systems currently under test do not require masks so could slightly cheaper to use than EUV, Chiang said.

EUV has "the broadest support and is the most likely route" forward, said Luc Van den hove, chief executive of the Imec research consortium based outside Brussels. "But this year and next we have to demo the production worthiness of this technology," Van den hove said in a separate talk.

Imec has been running wafers through an ASML 3100 pre-production system for three months "and we've seen improvement in throughput, but progress has been too slow and we have to further accelerate it," he said.

The power of the EUV source light is still too low, despite defining two approaches to creating the light source. "Progress has not been sufficient, and this is one of the highest priorities," said Van den hove who once ran Imec's lithography program.

As if the capital equipment problems were not enough, TSMC expects it will need to transition to a new transistor design at 14 nm, likely a FinFET. Intel announced plans to use such a 3-D transistor design starting at 20 nm.

Both TSMC and GlobalFoundries believe planar transistors can be used down to 20 nm. But they both expect to make the switch to 3-D structures such as FinFETs or fully depleted SOI at 14 nm.

Van den hove said FinFETs "are probably the most likely way. Beyond that we believe another technology breakthrough will be needed likely using super-high mobility materials such as germanium p-channel and III-IV materials for n-channels for 10 nm nodes," he added.

The good news is unexpected innovations have powered the industry past roadblocks in previous generations, despite as many as ten past predictions that Moore's law would end, said Chiang of TSMC. Based on feasibility demonstrations, he projected currently defined technologies could take CMOS scaling to geometries as fine as 7 nm.

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