Ok i created new VHDL called Vhd1.vhd file and in that file i import this.--------------data <= data_out WHEN as='0' AND rw='0' ELSE (OTHERS => 'Z');data_in <= data;--------------Then i use Set as Top-Level Entity for that file, then i go to compile and i get this error----------------------Error (10500): VHDL syntax error at Vhdl1.vhd(1) near text "data"; expecting "entity", or "architecture", or "use", or "library", or "package", or "configuration"----------------------I understand this error but you did not tell me to add any of them.

This was just a code snippet that needs to be added to your top level entity.You have to create an entity and an architecture with all the I/Os declarations, components declarations, then you instantiate your components and you wire them up to your I/Os.Please have a look at some VHDL or Verilog manuals.VHDL is like ADA language, Verilog is closer to C language. They are both well suited for what you want to do. Verilog is easier to learn.

Thank you. I was reading, searching and managed to make some code. But it does not work. Also i was trying usinf IF command insted WHEN and i did not make it work. I understand what is happening in code but i think that i did not add some part. VHDL code i was working on all morning. Update1: Code is working now but i dont see ADRESS BUSS lines in pin planner, and also there is data_bus as bidir group, and also input and output group all with 16 pins? As i can see my code have influence on all pins, and i just want to have influence on 16 in and 16 out pins. Only generated 49 pins, before it was 70.Update2: I dont understand why i need to declare all signals etc... All components are allready in TG.vhd. I only need to add inout part. I think that i need to connect TG68.vhd to this code and then reuse all declared in TG68.vhd.

Thank you. I was reading, searching and managed to make some code. But it does not work. Also i was trying usinf IF command insted WHEN and i did not make it work. I understand what is happening in code but i think that i did not add some part. VHDL code i was working on all morning. Update: Code is working now but i dont see ADRESS BUSS lines in pin planner, and also there is data_bus as bidir group, and also input and output group all with 16 pins? As i can see my code have influence on all pins, and i just want to have influence on 16 in and 16 out pins. Only generated 49 pins, before it was 70.

Again need help. With some help I created top level design file for TG68 and done some simulations but when I program core to FPGA I can't detect any signal movements. Hardware is ok because when I use any other simple designs for testing CLK and LEDs with signaltap I can see all the signals. Just like TG68 is not started or does not have clock I provided ?

Here is code and notice there are some voltage level translators on design but those are not important here, Tg68 just won't start. Do I need to provide some additional instructions here to start it or something. Also there is part of SDRAM controller that s not integrated, just point your attention to tg68 signals

Regarding ioHALT HALT is not implemented to TG68 as I know. TG68 is either not working on standalone version with tg68.vhd used for top level design file and provided basic clk directly without pll. When i try to program that to FPGA there are no signals detected with signaltap?

I think you should try to have the TG68 running from a small RAM/ROM implemented within the FPGA.Start with the minimal ROM : the reset vectors and an endless loop. Verify that the TG68 runs as expected with signaltap.Then, add more instruction and create an "Hello world" program in ASM.The best would be to have some test pins on the FPGA board that you can use for a UART implementation.Then, you can debug with this kind of cable : http://www.ftdichip.com/Products/Cables ... Serial.htmOnce you have that running, you can start accessing the external world : the A600 bus.

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