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Intel Pushes Their Linux-Friendly Xeon Phi

Phoronix: Intel Pushes Their Linux-Friendly Xeon Phi

In addition to NVIDIA and AMD announcing new high-end server/workstation GPUs to coincide with this week's SuperComputing SC12 conference in Salt Lake City, Intel has announced new details and release information on their Xeon Phi co-processors...

They have probably (and intelligently) decided that it would be easier to start with a HPC part, since the margins in this market allow for a very big and expensive die, and evolve it to eventually serve the graphics industry also. This may also be good for linux, since HPC requires good linux support.

I remember that some years ago intel was touting ray-traycing as the future of graphics, this card should probably be very good a it. Is there any open source ray-traycing engine?

Looking forward, this part should be fairly interesting, as it will surelly shake things up a bit due to the ease of programability and linux friendliness.

They have probably (and intelligently) decided that it would be easier to start with a HPC part, since the margins in this market allow for a very big and expensive die, and evolve it to eventually serve the graphics industry also. This may also be good for linux, since HPC requires good linux support.

I remember that some years ago intel was touting ray-traycing as the future of graphics, this card should probably be very good a it. Is there any open source ray-traycing engine?

Looking forward, this part should be fairly interesting, as it will surelly shake things up a bit due to the ease of programability and linux friendliness.

gcc doesn't really have support for Xeon Phi since it doesn't support their new SIMD extension. Intel just needed to be able to compile the kernel. If you want a compiler, you'll have to use icc.

The vector units in the Xeon Phi are using the same instruction format as the AVX instructions found in Sandy Bridge/Ivy Bridge chips that are already on the market. The Xeon Phi's extend the SIMD instruction length to 512 bits, but otherwise it is the same format (this was done intentionally, and AVX actually scales all the way up to 1024 bit SIMD instructions).

The bigger isssue with Xeon Phi is actually that the cores are simplified x86 meaning they drop some legacy instructions. That's not the end of the world but it does mean that GCC and the kernel need some tweaking so that they are only issuing valid instructions. To get the best performance out of these chips, your workload should be dominated by the SIMD instructions, which is what compute bound tasks are all about.

The vector units in the Xeon Phi are using the same instruction format as the AVX instructions found in Sandy Bridge/Ivy Bridge chips that are already on the market. The Xeon Phi's extend the SIMD instruction length to 512 bits, but otherwise it is the same format (this was done intentionally, and AVX actually scales all the way up to 1024 bit SIMD instructions).

I think you are wrong: on top of being wider there are now 32 registers instead of 16. Instruction encoding also is different and there are new instructions. So definitely something completely new