Further Study (June 2012)

PH.D CANDIDATE / RESEARCH ASSISTANT

UNIVERSITI TEKNOLOGI MALAYSIA

JALAN SEMARAK, KUALA LUMPUR

RESEARCH GROUP:VeCAD
Research Group works on high performance
VLSI design and FPGA implementation. Besides that, we also research new
methodologies for Digital System, such as verification and test
techniques. We
have accessibility to industrial tools of Mentor Graphics, Cadence and
Synopsis. Researchers will have opportunity to master these tools, which
is a
good preparation before working in industry.

RESEARCH TOPIC 1:THERMALLY AWARE SYSTEM-ON-CHIP TESTING

ABSTRACT: Temperature has been considered as one of the important issues in the design flow, especially the back-end process. In ITRS, TCAD is identified as an enabling methodology of thermal modeling for interconnect, semiconductor package and semiconductor materials, and reliability modeling. The existing tools for thermal modeling have been developed and most of them are used at device, process and circuit level, which is considered late when changes are needed to be done on the design based on the result of the tools. In addition, most of the tools are developed based on numerical methods or finite element methods, which are computationally expensive. As known for several years, testing power is several times higher than the design power. Therefore, both power and temperature issues in testing process cannot be ignored. In this research, we propose a parameterized thermal simulator that focuses on temperature-aware testing methodology, different from previous works which emphasize on the temperature-aware design flow. Expectedly, our thermal simulator is parameterized such that the temperature estimation can be done at pre-RTL, RTL and gate level. This is essential to allow early changes on the design such that the overheating problem does not happen in the real chips.

RESEARCH TOPIC 2:NEW FAULT MODEL FOR NEW CMOS TECHNOLOGY

ABSTRACT: After its discovery in 2004, graphene is recently predicted as a potential replacement for silicon and leading to ultrafast devices with simplified circuits that might be less expensive to manufacture. However, the fact that graphene is a zero band gap material by nature has raised many questions, a trait that is needed to switch on and off, which is critical for digital applications. Graphene, a flat monolayer of carbon atoms tightly packed into a two-dimensional (2D) honeycomb lattice exhibits the highest carrier mobility (100 000 cm/Vs) which is 100 times greater than Silicon and offer 5 times greater than Si MOSFET for saturation velocity (5x107 cm/sec). It also offers high thermal conductivity and monolayer thin body for optimum electrostatic scaling. Graphene has also been shown to be compatible with high-k dielectrics, thus gate dielectric scaling beyond the limits of SiO2 is possible. This is again in contrast to silicon technology, where the use of high-k dielectrics reduces mobility. Several recent research studies have demonstrated graphene inverter but there are issues remain, the inverter is always conducting and low inverter gain. For the first issue, the output stage dissipates a static power 0.77 mW, in contrast with a CMOS inverter, there is no static power dissipation. This problem can be reduced by using higher resistance, but making this inverter slower than a state-of-the-art CMOS inverter. Hence, there is a trade-off between the static dissipation and the highest possible clock rate. This fundamental research is to study on the feasibility to apply Graphene in the digital system design. Next, it is interesting to explore the new defects resulting from the new technology, which is a motivation to introduce the new fault model.

You will be assigned one of the research topics above. On a week-to-week
basis, you will be expected to list the main tasks associated with this research
topic and summarize the progress.

Requirements and Qualifications: You will be a motivated and self-starter. You will have completed Master's Degree (Electrical-Electronic or Computer) or equivalents for the PhD candidate position or completed Bachelor's Degree with at least second upper class for the research assistant position. You will have demonstrated strong skills in time management and
communication skills.

How To Apply:Applications (Cover Letter and Resume) may be submitted by e-mail no
later than 31 July 2012 to ooichiayee at ic.utm.my
with attention of Dr. Ooi Chia Yee.