HyperRAM and HyperFlash devices share the same signals except CS#, as illustrated in the following connection diagram. Having the HyperFlash and HyperRAM on a single bus reduces the number of pins and buses compared to the Quad SPI/SDRAM solution. Some designs are space-constrained and cannot accommodate two memory packages. Having one footprint that accommodates both HyperFlash and HyperRAM allows the design to use any combination of HyperFlash, HyperRAM, or HyperFlash + HyperRAM. This also allows to combine HyperRAM and HyperFLASH devices into a multi-chip package (MCP), so they can share all the signals except CS#.