Amkor Technology invites you to join us at the IMAPS 46th
International Symposium and Exhibition on Microelectronics held on
September 30 - October 3, 2013 at the Rosen Centre Hotel in Orlando,
Florida.

Amkor is pleased to author three papers at this year’s conference. All papers will be presented on Tuesday, October 1st, 2013:

ABSTRACT:

Selecting the
optimal flip-chip package technology for the next generation 28nm FPGA
is critical not only to meet reliability benchmarks for Pb-free bumps,
but also in meeting the field-use environment requirements for high
power devices. Component level reliability testing was conducted on
three separate package types: Bare die flip chip BGA (FCBGA), flip chip
molded BGA (FCMBGA) with capillary underfill, and FCMBGA with molded
underfill. Testing was conducted independently at two separate
facilities. Testing included moisture resistance testing (JESD22-A102D
Condition Level C), temperature cycle (JESD22-A104 Condition Level B),
1000hrs bake and hybrid test combining 100 hours of unbiased hast with
temperature cycling. Reliability monitoring was conducted through
multiple means including electrical testing for circuit continuity, CSAM
imaging at frequent read points to monitor silicon integrity and
underfill adhesion performance, cross-sections for the inspection of
bump crack propagation, and FIB analysis of the UBM structure after test
completion. In addition to reliability testing of three flip chip BGA
platforms, other usage factors were considered. These included package
specific design rule flexibility and future generation packaging
requirements. The results of the evaluation demonstrated that bump
integrity remained strong for all three package types – showing no
cracks after 1,500 temperature cycles and 1000hrs of bake. The
performance of both molded flip chip packages was equivalent and each
was better than the bare die. Ultimately, the FCMBGA with molded
underfill was selected based on design rule flexibility for passive
components as well as robustness on component test handling compared to
the other two capillary underfill package options.

Fernando
Roa, Director of Flip Chip Products at Amkor Technology, will be
presenting, "Application of Molded Underfill in Packaging of SMT
Modules" from 2:25pm - 2:50pm

ABSTRACT:

System in a
package (SIP) solutions are widespread in all sorts of electronic
appliances and, in special, for wireless communications, due their
convenience of integration different functionality (and silicon) into
one single ‘package’. OEMs prefer them over single point solutions
because they simplify their supply chain. But if SIP has helped
consolidate the supply chain it hasn’t helped process engineers ; as
these systems become more complex, with integration of different ICs,
switches, diodes, resistors, capacitors, coils, etc. the challenges
become varied and sometimes difficult to address. In this paper, we
review some of the challenges we have faced in developing a SIP MUF
solution, that is, modules which use a single encapsulation process :
challenges, benefits and adoption rates.

Bora Baloglu, Senior Engineer at Amkor Technology, will be presenting, "Warpage Characterization and Improvements for IC Packages with Coreless Substrate" from 4:55pm to 5:20pm

ABSTRACT:

Coreless package substrates are preferred for their superior electrical performance and thin profile compare to the conventional substrates with core. However, one of the major concerns with the coreless substrate packages is the warpage control. It is difficult to meet the industry standards for co-planarity needs because of the high CTE of the coreless substrates and the missing stiff core material in the stack up of the coreless structure. Finite element analysis (FEA) is utilized to investigate the use of coreless substrate in different package configurations. In this study, known stiffening structures such as a stiffener ring, one or two piece lid and molding options are investigated to characterize the advantages and disadvantages of using each of these structures to control the warpage in an IC package with coreless substrate. Available shadow moiré data is used for initial correlation of the finite element model and further design changes were carried out to stiffen the structure in the final packaged configuration. It is important to understand and make design considerations accordingly to improve assembly yield. Suggestions are made depend on the FEA findings which would guide the selection of the stiffening structure for a package with coreless substrate.