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The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

Bank Machine Usage

By default, the MIG output uses four Bank Machines. The design allows between two to eight Bank Machines where the trade-off is area versus performance.

Increasing the number of Bank Machines might improve the overall efficiency of the memory controller.

Behavioral simulation with the desired address/traffic pattern should be run to determine efficiency changes.

The number of Bank Machines is configured through RTL parameters in the memc_ui_top.v/.vhd module.

BM_CNT_WIDTH* = The width required for the Bank Machine counter. If four bank machines are used, BM_CNT_WIDTH needs to be set to two. If eight Bank Machines are used, BM_CNT_WIDTH needs to be set to three.

nBANK_MACHS** = The number of Bank Machines. This is set to four by default, but can be changed to a value between two and eight. When changing the number of Bank Machines, simulate the target traffic pattern to see a change in performance. Also, ensure timing is met.

*BM_CNT_WIDTH is only included in the Virtex-6 FPGA designs.

** As this number is increased, FPGA logic timing becomes more challenging and timing failures may occur depending on design and memory configuration.

For 7 Series Vivado designs, out-of-context (OOC) flow cannot be used. Use a non-OOC flow to manually modify the parameter.

For EDK users, a custom pcore should be created whenever parameter changes are made.

The following instructions can be followed to modify the bank machine parameters:

1. Open XPS project of the design.2. In the system assembly view of the XPS GUI, right click on axi_7series_ddrx (DDR3_SDRAM) IP and select option Make This IP Local.3. Navigate to local pcore directory of the XPS project.4. Locate BM_CNT_WIDTH and nBANK_MACHS parameters inside "../sources_1/edk/MicroBlaze_ProcessorSubSystem/pcores/axi_7series_ddrx_v1_08_a/hdl/verilog/<core_name>_mig.v" module:5. Generate the bitstream again with this rtl change.