The program does this automatically. CLEARANCE is set up in the DRC dialog. Your setting is now 5, which is probably too small. Use something like 10-15mils. In fact, all your settings are too small (I'm assuming MILS) . Use 15 as MIN WIDTH, 20 as MIN DRILL and 15 for CLEARANCE. A drill much less than 15mils usually costs more to produce.

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So, the pins are automatically isolated from GND? Do the parameters set in the net classes only apply to autorouting? Will I have to re-trace everything?

Here are the top and bottom layers, re-routed using your parameters (all in mil). I've also going to scatter more vias around the board, to get a better connection. I've noticed that large parts of the board are unfilled (appear blue), but I'm going to assume that's fine and just the clearance setting.

What parameters do you recommend for vias? I assume they don't need any clearance if they are connecting grounds?

For signal integrity, always make efforts to flood ground between adjacent signals. You can do this with a ground via between them, or moving the traces farther apart. When I place vias, I will set them in a pattern, like 0.25" apart, with adjacent rows offset by 0.125" (diagonal rows). There is no reason for this other than it looks good. I then will sprinkle in extra ground vias where they are needed. Every via that connects top gnd with bot gnd effectively lowers the impedance of your ground. As for clearance of your vias, they CAN sometimes violate your DRC rules. You have to examine each violation and check "OK" to allow the violation (it's usually a trivial violation).

Your board looks pretty good now, and will look even better if you address the above concerns.

For signal integrity, always make efforts to flood ground between adjacent signals. You can do this with a ground via between them, or moving the traces farther apart. When I place vias, I will set them in a pattern, like 0.25" apart, with adjacent rows offset by 0.125" (diagonal rows). There is no reason for this other than it looks good. I then will sprinkle in extra ground vias where they are needed. Every via that connects top gnd with bot gnd effectively lowers the impedance of your ground. As for clearance of your vias, they CAN sometimes violate your DRC rules. You have to examine each violation and check "OK" to allow the violation (it's usually a trivial violation).

Your board looks pretty good now, and will look even better if you address the above concerns.

You also need to uncheck THERMALS for your bottom layer.

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Thanks, I'll get those vias in. I've added one between the signals as you suggested, and it has filled in the area. Out of interest, why wasn't this already filled, like most areas of the board?

PCBWAY seems bigger than ALLPCB, and the price is quite different for these two fab.

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While, I enjoy the shipping discount from ALLPCB, and this is a very point I may consider for there are times of modifcation before we finalize our designs,and shipping cost is expensive for international business, At the same time ,the 24H lead time is attractive for me ,When I order on Monday, I got the tracking number on Tuesday, and receive them on weekend time ! I can test them and see if the boards perform well !