As usual I am putting mixed unstructured infromation on yet
another
tool, this time it is VCS.
I believe that it will provide a lot of practical information for
users
than the user guides or any other tutorial
provides. Any questions, please write to me at avimit at yahoo dat
com.

While using VHDL design files, a simulaiton file 'synopsys_sim.setup'
is usually defined, which defines
the compiled vhdl library.
Example 'synopsys_sim.setup' file:
------------
WORK > DEFAULTDEFAULT : ./workmemlib : ./mem_libxm_bus_lib : ./xm_bus_lib
---------------------------------
The first line maps the WORK library to a name 'DEFAULT', and the
second
line maps the 'DEFAULT' library
to a physcial directory called './work'.
The second line defines a library memlib which is mapped to a
physcial
directory called 'mem_lib'.

In the absence of any 'synopsys_sim.setup' file in your working
directory,
vcs will look for the same file in your home directory,
and if there is no 'synopsys_sim.setup' in your home directory, it
will look for the same file in the tool installation directory.
The default 'synopsys_sim.setup' is in the tool installation
directory,
which maps the default work directory to '.'.
You will see complied VHDL files in '.' in case you dont have a
'synopsys_sim.setup'
file.

VCS can be a 2 step process if only verilog is being used
vcs <source-files> [compile options]

Generating Makefile:vcs -lca -makedepends=makefile
state_machine_tb
It seems that the same above command is used to generate makefile,
and to do an incrimental compliation.
Incremental compliation is enabled by default:

VCS commands
removing like ncrm
updating like ncupdate
hierarchy browsing using commands
dump values in a txt file like ncsim
how to define the hierarchy
forcing nets in simulation, syntax.

VHDL files are compiled into a library.
Usually the default library is 'work' which is mapped to your
current
working directory i.e "."

Usually you will see that this 'work' library path is changed by
defining
the work library in synopsys_sim.setup file

WORK > DEFAULTDEFAULT : ./work_lib

Then other libs may be defined in the same file i.e
synopsys_sim.setup
file:

memlib : ./memlibpkg_lib : ./allcompiledpkgsxm_bus_lib : ./xm_bus_lib

Further observation about vhdl library and vhdl compliation:

vhdlan -work work fun_pkg.vhdl
OR
vhdlan fun_pkg.vhdl

which means that 'fun_pkg.vhdl' is complied into work_lib
when you see the contents of work_lib you will see files
FUN_PKG.sim
FUN_PKG__.sim

Now I have another file called
xmbus_master.vhd which intends to use 'fun_pkg' package from the
work
lib
i.e the xmbus_master.vhd has the following lines

use work.fun_pkg.all

now if I compile the xmbus_master.vhd like this

vhdlan -w xm_bus_lib xmbus_master.vhd

I would expect that the complier picks up fun_pkg from work_lib.
But
it DOESNOT!

Which emplies that 'work' in the statemetn use work.fun_pkg.all
refers
to the library xm_bus_lib, to which xmbus_master.vhd is being
complied
into.

On the other hand if I do the following

vhdlan -w memlib fun_pkg.vhdl

Then I use the following lines in xmbus_master.vhd

library memlib;use memlib.fun_pkg.all;

then I compile xmbus_master.vhd like

vhdlan -w xm_bus_lib xmbus_master.vhd

Then things are FINE, this time the complier picks up complied
'fun_pkg'
from the memlib.

So the conclusion is:

when using 'use work.abcd.all', 'work' refers to the current
compliation
lib given with -w option while compliling the file
containing 'use work.abcd.all' , and NOT to the 'work_lib' which
is
the default compliation lib

Step 3: cmView : for gui based analysis
:
This Step will let you see coverage results in a GUI
Example:
cmView

Step 3: vcs -cm_pp : for batch mode post
processing.
This step outputs report files
Example:
vcs -cm_pp -cm_report summary
This will generate human viewable reports in the simv.cm/reports
directory.
it also writes a summary file in the same directory, named 'cmView.summary'

vcs -cm line|cond|fsm|tgl|path|branch|assert

Example command
vcs -cm line+cond pid_filter_tb

vcs -cm line+cond+fsm+tgl+path
pid_filter_tb

adding -path gives an Error to avoid it use -lca

vcs -lca -cm path pid_filter_tb

And dont forget the -debug, in case you want to see anything : ).

vcs -lca -debug_all -cm
line+cond+fsm+tgl+path
pid_filter_tb

Still I have to face problems, so the final command line looked
like:

vcs -cm_tgl mda -lca -cm
line+cond+fsm+tgl+path
-debug_all pidf_tb

Now simulaiton may be launched, again all the coverage options
given
at the 'vcs' compilation
MUST be given to the simv as well or there will be NO coverage
recorded.
But then you cant use '-cm_tgl mda'. You see dont apply
your
common sense, or nothing will work.
After all vcs is developed by Synopsys not Google.

simv -cm line+cond+fsm+tgl+path -gui

NOTES:

-cm option creates simv.cm directory

During Simulation following files are produced:
test.line and test.fsm etc.. depending upon the coverage option.

To over ride the default 'test' name you can use
vcs source.v -cm line -cm_name test1vcs source.v -cm line -cm_name test2
...etc
OR
simv -cm line -cm_name test2simv -cm line -cm_name test3
etc...

Also, during simulation, VCS and VCS MX write the cm.decl_info
file
in either the simv.cm/db/verilog directory (for Verilog) or the
simv.cm/
db/vhdl directory (for VHDL). cmView needs this file to show
coverage information.

If you invoke your binary executable from a different location,
then
use -cm_dir option at runtime to specify the the path for the
coverage database directory

By default VCS does not compile the following for coverage:
• The source code in Verilog library directories
• Verilog library files
• Any module defined under the celldefine compiler directive

yv
For compiling for coverage source code from Verilog libraries.
celldefine
For compiling for coverage modules defined under the

To prevent this lowering of coverage percentages, use the
-cm_noconst compile-time option
Constant filtering for toggle coverage is available only for
Verilog-only designs

simv -cm fsm -cm_log run1.log

Hierarcy in the design, and inclusion/exclusion of
modules/files/instances.
-tree instance_name [level_number]
A level number of 0 (or no level number) specifies the entire
subhierarchy, 1 specifies only this instance, 2 specifies this
instance and those instances directly under this instance, and so
on

I intended to exclude cond+tgl+path, and include the fsm
coverage.
The above does write the fsm coverage, since fsm is not excluded
from
the list inside the cm_hier.file
NOTE: line coverage is always opened for
modules
or instances that have cond/path/fsm/branch coverage ON.

After several unsuccessfull runs to use '-tree' options, I
concluded
that it is 'case sensitive',
even though
i have a VHDL design,
and in my vhdl design pidf_tb, and pidf_u1 are lower case.
For some reason I am required to put the instance name in upper
case
Following works
begin fsm+line -tree PIDF_TB.PIDF_U1end
BUT the following DoestNOT work.
begin fsm+line -tree pidf_tb.pidf_u1end

Now my objective is only to remove the top level testbench from
coverage
collection. For this I will have to use [level number]
begin line+cond+fsm+tgl+path -tree
PIDF_TB
1 //using level number 1 will make
sure
only the testbench level is excluded from the coverage
collectionend

If I dont use the [level number] in front of PIDF_TB, then by
default
all scopes under PIDF_TB will be excluded from coverage
This is the same as using level number 0.

PROBLEM: while trying to use the -file option
------------------------
Warning-[VCM-HFUFR] Hier Config: regions not found
In the hier config file ( given by -cm_hier option ),
pattern
"-file or
specified by -filelist ---
/projects/leota/amittal/block_design_flow_dev/pid_filter/rtl/pidf.vhd"
did
not match any pattern.
Please check the hier config file "cm_hier.file".

I have been trying to use -file option and above is the warning
message.
The corresponding cm_hier.file is
Note that I have used full path for the file I wanted to exclude.
This
doesNOT work.
---------------
begin line+cond+fsm+tgl+path -file
/projects/leota/amittal/block_design_flow_dev/pid_filter/rtl/pidf.vhdend
--------------------------------

Now if I use relative path, then vcs does not complain about the
file
and things go on fine: The corresponding cm_hier.file is
This Does Work.
-------------
begin line+cond+fsm+tgl+path -file
../rtl/pidf.vhdend
----------------------------

The HDL Compiler and Behavioral Compiler user can use the
//synopsys translate_off directive in place of the //VCS
coverage off pragma and the
//synopsys translate_on directive in place of the //VCS
coverage on pragma.
The //VCS coverage on pragma enables line coverage after a
//synopsys translate_off directive and a
//synopsys translate_off directive disables line coverage
after a //VCS coverage on pragma.
Similarly the //VCS coverage off pragma disables line coverage
after a //synopsys translate_on directive and a
//synopsys translate_on directive enables line coverage after
a //VCS coverage off pragma.

Glitch supression.
To prevent this, there is the -cm_glitch compile-time option. Its
syntax is as follows:
vcs -cm line+cond+tgl -cm_glitch period

The -cm_glitch option is also a runtime option, but it only works
for toggle coverage

Collecting an Execution Count
-cm_count compile-time option

Post Processing:
vcs -cm_pp -cm_report summary
The above command is used to post process the results of Code
Coverage
generated during simulaion.
This command produces results in simv.cm/reports directory.

Some more imp commands:
vcs -cm_pp -cm line+cond -cm_report testlists

NOTE:
The graphical user interface (GUI) for cmView does not display
path coverage information. You must have cmView write path
coverage reports

VCS and VCS MX do not monitor the if statement in the for loop
statement and the if statement in the user-defined task

Branch coverage is implemented for Verilog
simulation
only :(

NOTE:
By default VCS and VCS MX do not monitor for branch coverage if
and case statements and uses of the ternary operator (?:) if they
are in user-defined tasks or functions or in code that executes as
a
result of a for loop. You can, however, enable branch coverage in
this code. See “For Loops and User-Defined Tasks and Functions”
on page 4

Assignment Coverage
-cm_line assigntgl
compile-time
option and keyword argument.
Note:
This is a Verilog-only feature. There is no
similar
report for VHDL

Note that the need of uvm_custom_install_vcs_recorder.sv is
essential, and so is the use of -ntb_opts uvm or you will get the
following error:

Error-[DPI-DIFNF] DPI import function not found
/pkg/qct/software/dv_meth/uvm/uvm-1.1d_r2/release/src/base/uvm_resource.svh,
390
The definition of DPI import function/task 'uvm_glob_to_re'
does not exist.
Please check the stated DPI import function/task is
defined, and its
definition is either passed in a source file at
compile-time, or provided in
a shared library specified using the LRM Annex-J options at
run-time.

$finish at simulation
time
0
Error: [UCLI-018] VCS Runtime Error
The simulation is not active due to an error. Commands are not
being accepted
Use "start <toolname> <cmd-line-args>" to restart tool
at the ucli prompt. If problem persists, please contact a synopsys
representative
Error: synopsys::finish -immediate
Error: can't read "State(status)": no such variable
Warning: [DVIT006]