Niagara II chip would have eight cores just like its predecessor, which Sun currently sells as the UltraSPARC T1. In addition, we pegged Niagara II as supporting twice the threads of the UltraSPARC T1, bringing it up to 64 threads, and shipping with one floating point unit per core as opposed to one floating point unit total. FB-DIMMs, two-way support, and 10 Gig-E? Yep, we got those suckers too, and Sun has confirmed them all in its presentation.

According to the latest documents, each Niagara II chip will ship with 8 cores, a 4MB shared L2 cache, four dual-channel FB-DIMM memory controllers, two 10 Gig-E ports and one PCI-E port. Each core also has a cryptographic acceleration unit with support for ciphers and hashes that can perform “free” encryption. The crypto unit runs in parallel with the main SPARC core at the same frequency.

True chip geeks might be interested to note the eight-stage pipeline – fetch, cache, pick, decode, execute, memory, bypass and writeback. Meanwhile, there’s a 12-stage pipeline for the floating point unit. Sun has also added a host of reliability features to the new chip.