12.1
A Logic-Synthesis Example

As an example of logic synthesis, we will compare two implementations of the
Viterbi decoder described in Chapter 11. Both versions used logic cells from a VLSI Technology cell library. The first ASIC was designed by hand using schematic entry and a data book. The second version of the ASIC (the one that was fabricated) used Verilog for design entry and a logic synthesizer.
Table 12.1
compares the two versions. The synthesized ASIC is 16 percent smaller and 13 percent faster than the hand-designed version.

How does logic synthesis generate smaller and faster circuits?
Figure 12.1
shows the schematic for a hand-designed comparator and MUX used in the Viterbi decoder ASIC, called here the
comparator/MUX example. The Verilog code and the schematic in
Figure 12.1
describe the same function. The comparison, in
Table 12.2
, of the two design approaches shows that the synthesized version is smaller and faster than the hand design, even though the synthesized design uses more cells.