Accelerator systems and methods are disclosed that utilize FPGA technology to achieve better parallelism and processing speed. A Field Programmable Gate Array (FPGA) is configured to have a hardware logic performing computations associated with a neural network training algorithm, especially a Web relevance ranking algorithm such as LambaRank. The training data is first processed and organized by a host computing device, and then streamed to the FPGA for direct access by the FPGA to perform high-bandwidth computation with increased training speed. Thus, large data sets such as that related to Web relevance ranking can be processed. The FPGA may include a processing element performing computations of a hidden layer of the neural network training algorithm. Parallel computing may be realized using a single instruction multiple data streams (SIMD) architecture with multiple arithmetic logic units in the FPGA.

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Revendications(19)

What is claimed is:

1. A neural network computing system comprising:

a Field Programmable Gate Array (FPGA) configured to have a hardware logic performing computations associated with a neural network training algorithm by receiving streamed data directly from a host computer device, the hardware logic including a processing element that performs computations related to a hidden layer of the neural network training algorithm, the processing element including a plurality of arithmetic logic units each representing a hidden node of the hidden layer; and

an interface for connecting the FPGA to the host computing device and receiving the streamed data.

2. The system as recited in claim 1, wherein the neural network training algorithm comprises a Web relevance ranking algorithm.

3. The system as recited in claim 2, wherein the Web relevance ranking algorithm comprises a LambdaRank algorithm.

4. The system as recited in claim 1, wherein the plurality of arithmetic logic units perform parallel computations.

5. The system as recited in claim 1, wherein the hardware logic of the FPGA includes an arithmetic logic unit performing computations related to the neural network training algorithm, the arithmetic logic unit having a plurality of multi-pipeline multipliers and a plurality of multi-pipeline adders.

6. The system as recited in claim 5, wherein at least one of the multi-pipeline multipliers and the multi-pipeline adders is based on floating-point numbers.

7. The system as recited in claim 1, wherein the hardware logic of the FPGA includes a processing element performing at least part of computations of both forward propagation and backward propagation of the neural network training algorithm.

8. The system as recited in claim 1, wherein the hardware logic of the FPGA includes a processing element for performing Lambda calculations of a LambdaRank algorithm.

9. The system as recited in claim 1, wherein the neural network training algorithm includes a plurality of input nodes each corresponding to a feature for Web relevance ranking.

10. The system as recited in claim 1, wherein the FPGA is provided on a substrate.

12. The system as recited in claim 1, wherein the FPGA has a directly accessible internal memory, and at least part of the streamed data is written directly to the internal memory to be accessed by the FPGA to perform the computations associated with the neural network training.

13. The system as recited in claim 1, wherein the interface comprises a downstream channel to send the streamed data from the host computing device to the FPGA, and wherein the downstream channel has a First In First Out (FIFO) unit.

14. A neural network computing system comprising:

a host computing device for storing and processing training data;

a Field Programmable Gate Array (FPGA) provided on a substrate, and configured to have a hardware logic performing computations associated with a neural network training algorithm by receiving streamed data directly from the host computer device, the FPGA including a hidden layer processing engine that performs computation associated with a hidden layer of the neural network training algorithm, the hidden layer processing engine including a plurality of processing elements each representing a hidden node of the hidden layer; and

streaming the processed training data to a Field Programmable Gate Array (FPGA) configured to have a hardware logic performing computations associated with a neural network training algorithm, the hardware logic including one or more processing engines that map to individual hidden nodes of the neural network training algorithm, the one or more processing engines performing at least part of computations of both forward propagation and backward propagation of the neural network training algorithm; and

enabling the FPGA to perform neural network training with respect to the streamed training data.

19. The system as recited in claim 15, wherein the FPGA further includes:

an output layer processing engine that performs computation associated with an output layer of the neural network training algorithm;

a lambda unit that performs computation associated with a calculation of lambda in the LambdaRank algorithm; and

an internal memory directly accessible by the hidden layer processing engine, the output layer processing engine and the lambda unit.

Description

RELATED APPLICATIONS

This application is related to U.S. patent application Ser. No. 11/737,605 entitled “FIELD-PROGRAMMABLE GATE ARRAY BASED ACCELERATOR SYSTEM”, filed on Apr. 19, 2007, which application is hereby incorporated by reference in its entirety.

BACKGROUND

In information retrieval, ranking is of central importance. Good ranking is the basis for relevance, while the relevance is the basis for Web search to attract users and advertisers. Ranking is usually done by applying a ranking function (a ranker) onto a set of objects (e.g., documents) to compute a score for each object and sort the objects according to the scores. Depending on applications the scores may represent the degrees of relevance, preference, or importance, but relevance is usually referred to without losing generality.

Information retrieval (IR) researchers have studied search relevance for various search engines and tools. Representative methods include Boolean, vector space, probabilistic, and language models. Earlier search engines and tools were mainly based on such IR algorithms. These search engines and tools incorporate in varying degrees the concept of the ranking function. Many factors may affect the ranking function for search relevance. These factors may include page content, title, anchor, URL, spam, and page freshness. It is extremely difficult to manually tune ranking function parameters to accommodate these factors for large-scale data sets, such as those that are common in many applications including World Wide Web (“Web”) applications and speech and image processing. For these large data sets, machine based learning algorithms have been applied to learn complex ranking functions from large-scale data sets.

Early algorithms for ranking function learning include Polynomial-based regression, Genetic Programming, RankSVM and classification-based SVM. However, these algorithms were only evaluated on a small-scale dataset due to the high computational cost. In fact, these traditional machine-learning algorithms operate slowly when searching large-scale data sets. Users often wait many hours, days, or even weeks to get results from these data sets.

More recently, Neural Network (NN) started to be intensively used in many application areas (such as pattern recognition, signal processing, time series analysis, etc.) due to its superior quality. For example, Microsoft's MSN has used RankNet and is now using LambdaRank, to produce a NN model to generate ranking models for web pages in the Live Search engine. In Web Search ranking, the scale of data sets is large, so the training process may cost a lot of time and huge human effort on general purpose computers. This leads to low relevance quality and large cost for the search engines.

This slow computation time may be due, in part, to a typical personal computer (PC) being unable to exploit full parallelism in machine-learning algorithms efficiently. Instruction level parallelism techniques somewhat improve the processing time. More particularly, distributed implementations with process level parallelism are faster than many of the PC central processing units (CPUs), which execute instructions in sequential manner. However, distributed implementations occupy many machines and are very hardware intensive. Additionally, for some algorithms, distributed computing yields poor speed improvement per processor added due to communication cost. A Graphics Processing Unit (GPU)-based accelerator is another potential solution, but it could only accelerate a limited spectrum of machine learning algorithms due to its special hardware structure optimized for graphics applications. Memory access bandwidth, communication cost, flexibility and granularity of parallelism remain bottlenecks for these solutions. Furthermore, despite their generally recognized performances, the high cost of developing ASICs (Application Specific Integrated Circuits) has hampered such hardware neural network computing devices from seeing significant applications.

SUMMARY

Disclosed are accelerator systems and methods that utilize FPGA technology to achieve better parallelism and processing speed. An FPGA-based accelerator has a Field Programmable Gate Array (FPGA) configured to have a hardware logic performing computations associated with a neural network training algorithm, especially a web relevance ranking algorithm such as LambaRank. The training data is first processed and organized by a host computing device, and then streamed to the FPGA for direct access by the FPGA in order to perform high-bandwidth computation with increased training speed. Thus, large data sets such as that related to web relevance ranking can be processed. The FPGA may include a processing element performing computations of a hidden layer of the neural network training algorithm. Parallel computing may be realized using a single instruction multiple data streams (SIMD) architecture with multiple arithmetic logic units in the FPGA.

In one embodiment, the hardware logic of the FPGA includes a processing element performing computations relating to a hidden layer of the neural network training algorithm. The processing element may have a plurality of arithmetic logic units each representing a hidden node of the hidden layer. Each arithmetic logic unit may include a plurality of multiple-pipeline multipliers and a plurality of multiple-pipeline adders. The multipliers and the adders can be based on floating-point numbers to improve weight precision. The plurality of arithmetic logic units performs parallel computations.

In one embodiment, the FPGA-based accelerator uses a PCI controller to communicate with a host CPU. The FPGA-based accelerator may also include DDR memory provided on the same PCI board with the FPGA.

According to another exemplary implementation, a neural network system includes a host computing device for storing and processing training data, a Field Programmable Gate Array (FPGA) provided on a substrate, and an interface for connecting the FPGA to the host computing device. The FPGA is configured to have a hardware logic performing computations associated with a neural network training algorithm by receiving streamed data directly from the host computer device.

Another aspect of the present disclosure is a method for neural network training. The method stores and processes training data on a host computing device; streams the processed training data to a Field Programmable Gate Array (FPGA) configured to have a hardware logic performing computations associated with a neural network training algorithm; and enables the FPGA to perform neural network training with respect to the streamed training data.

By virtue of the method and system disclosed herein, a user can train a ranking model with much less time and cost, making it possible to attempt different learning parameters of the algorithm in the same time, or carry out a study that depends on numerous ranking models.

This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

BRIEF DESCRIPTION OF THE FIGURES

The detailed description is described with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The use of the same reference numbers in different figures indicates similar or identical items.

FIG. 1 shows an exemplary architecture of an FPGA-based accelerator system for machine learning (training) in accordance with the present disclosure.

FIG. 11 illustrates an exemplary pipeline division in each processing unit such as an arithmetic logic unit.

DETAILED DESCRIPTION

Overview

An FPGA-based accelerator system for machine learning as described and claimed herein accelerates selected algorithms by providing better processing parallelism and memory access. The disclosed design takes advantage of the appearance of large, dense, highly parallel FPGA circuits with customizable hardware structure to realize large-scale neural networks in hardware, with the flexibility and low cost of software implementations.

One aspect of the present disclosure is a neural network system that has a Field Programmable Gate Array (FPGA) configured to have a hardware logic performing computations associated with a neural network training algorithm by receiving streamed data directly from a host computer device. The neural network system also has an interface for connecting the FPGA to the host computing device and receiving the streamed data.

Another aspect of the present disclosure is a method for neural network training. The method stores and processes training data on a host computing device; streams the processed training data to a Field Programmable Gate Array (FPGA) configured to have a hardware logic performing computations associated with a neural network training algorithm; and enables the FPGA to perform neural network training with respect to the streamed training data.

In particular, the disclosed design makes it possible to handle neural networks that are used for Web ranking, such as RankNet and LambdaRank. The training and application of these neural network face special challenges compared to existing neural network FPGA implementations, as discussed below.

First, Web ranking tends to have very large training data. The Web scale data makes it difficult or impossible to load all training data to the accelerator board before training. To overcome this difficulty, the disclosed streaming architecture uses the host computer to prepare the training data in its main memory, and then send the data streams to the FPGA accelerator board in a streamed fashion, continuously and repetitively as needed. The hardware logic in the FPGA on the accelerator board cause direct real-time access to the streamed data in training the neural network model.

Second, newer neural networks such as LambdaRank have a query level cost function, which is much more complex than common Back-Propagate (BP) NN algorithm. To address this complexity, some embodiments of the disclosed FPGA accelerator are elaborately designed to accelerate such neural networks on the hardware level.

Third, in order to obtain a ranking model that can rank tens of thousands web pages, the model may need to have high precision weights. To achieve the necessary high precision weights, some embodiments of the disclosed FPGA accelerator implements single precision floating point numbers instead of using fixed point numbers to update the weights.

The disclosed FPGA-based neural networks and methods can be applied to the training of any neural network model, but is particularly suited for training back propagation neural networks, and especially for training back propagation neural networks that handle a large training data set, such as that in Web ranking.

Exemplary FPGA Implementation of Neural Network Training

The neural network training algorithm is implemented using FPGA. The implementation is at least partially hardware-based using customer-configured a field programmable gate array. A unique data streaming method is used between a host computing device and the FPGA board to enable training of a large data set.

One embodiment is an FPGA-based acceleration device, which may include a substrate, such as a Peripheral Component Interconnect (PCI) card, with a Field-Programmable Gate Array (FPGA) and memories acting as caches, e.g., SRAM, SDRAM, and so forth, connected to a computing device. The FPGA has multiple logic blocks which are programmed to function as processing elements (PEs), as will be illustrated below. The memories of FPGA may have a hierarchy including at least an onboard common memory shared by the multiple logic blocks, and internal memories embedded in or directly accessible by each logic blocks or processing elements (PEs). One or more neural network algorithms may be implemented on one or more of the FPGAs with direct parallel architecture and/or pipelined architecture to exploit both application parallelism and direct functional logic implementation. The PCI could be replaced by other computer buses, including but not limited to PCI-X, PCI-Express, HyperTransport, Universal Serial Bus (USB) and Front-Side Bus (FSB).

A training data set or other data is first stored and preprocessed by the computing device, and at least part of the training data is then streamed directly onto the internal memories of the PEs on the accelerator board, or onto embedded memories in the FPGA, to increase memory access bandwidth and data locality. The training data set may comprise information collected from Web searches to assess relevancy, and other characteristics. The system may include or be associated with one or more PCs or other computing devices, each computing device having one or more accelerator cards.

FIG. 1 shows an exemplary architecture of an FPGA-based accelerator system for machine learning (training) in accordance with the present disclosure. The accelerator system 100 may include an acceleration device 101 comprising a Peripheral Component Interface (PCI) board 104 with a Field-Programmable Gate Array (FPGA) 106 and onboard memory 108, which can be any suitable RAM (including SRAM and/or SDRAM) such as DDR, DDR2 or DDR3, and so forth, connected to a computing device such as a host computer 114. The PCI board 104 may interface with a PCI bus 116 on or associated with the host computing device 114. The PCI board 104, and/or devices thereon, may communicate with the bus 116 thorough a PCI controller 118.

The FPGA 106 may comprise a computation logic 120 that communicates to the onboard memory 108 and/or the PCI controller 118 through one or more interfaces 122. The computation logic 120 has direct access to an internal memory 124, which can be an embedded RAM such as a dual port RAM. As will be shown further below, the computation logic 120 can be programmed or configured into multiple logic blocks to realize the functions of multiple processing elements (PEs).

The host computer 114 has a CPU 132, host memory RAM 134, chipsets 136, and a host storage (such as a hard disk) 138. Training data 140 or other data are stored in the host storage 138 and processed when necessary by the host computer 114. At least part of the training data 140 are streamed directly to the embedded memory 124 of the computation logic 120 in the FPGA 106, in order to increase memory access bandwidth and data locality. Software loaded on the computer 114 may be capable of programming or re-programming the FPGA 106 at any time during processing.

The FPGA-based accelerator may be used for generating ranking models for Web Search engines using a neural network training program, such as RankNet or LambaRank. This task is an iterative task in the search relevance ranking engineering pipeline. The ranking models need to update regularly (e.g. weekly) to reflect the dynamics of the Web on different markets characterized by languages and regions.

An exemplary procedure to use the FPGA-based accelerator is as follows. (1) Plug the accelerator 101 to host computer 114 that has PCI Express slot. The accelerator 101 in one embodiment is a PCI Express add-in card; (2) Install the device driver and software into the host computer 114; (3) Receive and prepare the training data set, feature set description file, and set the proper training parameters on the host computer; and (4) Run the accelerator 101 to train the ranking model. If the training model is not satisfactory, return to step (3) and modify the training settings and parameters to explore the parameter space.

Multiple FPGA-based accelerators may be used in parallel in the same host computer, and further multiple host computers may be used together to further improve the performance.

FIG. 2 shows an exemplary distributed deployment of the FPGA accelerator. As shown in FIG. 2, an acceleration system 200 may be composed of one or more computing devices 214, similar to computer 114, with each computing device 214 having one or more PCI cards 201, similar to PCI board 104. The computing devices 214 may be connected through a network 205. Thus, multiple cards 201 on multiple computing devices 214 may process data in parallel and thereby handle larger scale algorithms.

Machine Learning and Neural Network Training

The disclosed FPGA architecture could be used to accelerate a class of machine learning algorithms, particularly neural network training algorithms. Specific implementation of a neural network training algorithm is related to the process and computation involved in the actual algorithm. In the following, a generic back propagation neural network is illustrated, followed by a description of two exemplary classes of neural network algorithms that can be implemented with the disclosed FPGA architecture, namely pair-wise and query-wise neural network algorithms. Thereafter, an illustration of a more elaborate LambaRank algorithm is provided. It is appreciated that because the disclosed accelerator is based-on reconfigurable hardware FPGA, it can be reconfigured to adapt to a broader class of algorithms besides the algorithm described here.

FIG. 3 is a block diagram showing an exemplary back propagation neural network. The illustrated neural network 300 has three layers (but is conventionally referred to as a 2-layer NN, not counting the input layer), including an input layer with three neurons, a hidden layer with two neurons; and an output layer with two neurons. A back propagation neural network must have at least an input layer and an output layer, but it could have zero or more hidden layers.

The output of the neural network 300 is obtained by applying input values to the input layer, passing the output of each neuron to the following layer as input. At each neuron Ni, an output may be calculated as:
Oi=Σjxj*wj+θi,

for j=1 to m (to include all neurons in the previous layer).

Typically, in a neural network, the output of a neuron in a layer goes to all neurons in the following layer. Each pair of connected neurons forms an edge which has its own input weight. The weights for the input layer can be assumed to be 1 for each input. In other words, input values at the input layer are taken at their face values and are not weighted (although the face values themselves may be scaled or normalized before being applied as the input at the input layer, depending on needs). For this reason, the nodes in the input layer are usually not considered to be neurons and do not require much consideration in implementing the associated calculations. Accordingly, as will be seen herein, the main focus of the disclosed FPGA implementation is on the hidden layer and the output layer, especially the former.

The number of nodes in the input layer depends on the number of possible inputs, while the number of neurons in the output layer depends on the number of desired outputs. The number of hidden layers and the number of neurons in each hidden layer are usually not inherently defined by the number of inputs and outputs in advance, and could change per network configuration and type of data. This therefore becomes a point of design consideration. The embodiments illustrated in the present disclosure shows one hidden layer, and some embodiments have 10 or 20 hidden nodes in the hidden layer. But it is appreciated that from a mathematical solution point of view, there is no fundamental limitation to these choices of the hidden layer, and they are thus chosen according to the design preferences and hardware characteristics. In general, the addition of a hidden layer could allow the network to learn more complex patterns, but at the same time may decrease its performance. One could start a network configuration using a single hidden layer, and add more hidden layers if the network is not learning well.

The back propagation neural network works in two modes, a training mode and a production mode. The disclosed FPGA-based back propagation neural network is primarily for training. Once the neural network model is trained, it can be put into production (e.g., actual ranking) using any suitable implementation of the trained neural network model. In other words, the implementation of the trained neural network model does not have to be the same as the disclosed FPGA-based hardware/software implementation.

The training in the illustrated embodiments is supervised training. Such training is based on a training data set that includes ground-truth rating information which can be used as a feedback to check the result of each training cycle.

An exemplary training procedure of a typical back propagation neural network may be summarized as follows.

(1) Start by initializing the input weights for all neurons. The initialization may use random numbers between 0 and 1.

(2) Apply input to the network.

(3) Calculate the output.

(4) Compare the resulting output with the desired output (based on the training data) for the given input. The discrepancy is referred to as error.

(5) Modify the weights and threshold for all neurons based on the error.

(6) Repeat the process until the error reaches an acceptable value (e.g. error <2%), indicating that the neural network has been trained successfully. If the training reaches a maximum count of iterations without achieving an acceptable error level, the training may be considered unsuccessful.

The challenge of backward propagation neural network printing is to find a good algorithm for updating the weights and thresholds in each iteration (the above step (5)) to minimize the error. The weights and threshold for neurons in the output layer and that of hidden layers are usually updated separately as they may involve different calculations. Generally, during a training iteration of a back propagation neural network, the training algorithm starts modifying the weights at the output layer, and then proceeds backwards on the hidden layers one by one until reaching the input layer.

The detail of the training iteration of a back propagation neural network will be further illustrated using embodiments such as RankNet and LambaRank below. The detailed design of RankNet and LambdaRank algorithm are disclosed in Chris Burges, et al., Learning to Rank using Gradient Descent, ICML, Pages: 89-96, 2005 (RankNet); and in Christopher J. C. Burges, Ranking as Learning Structured Outputs, Proceeding of NIPS2005, Workshop on Learning to Rank, Pages: 7-11, December 2005 (LambdaRank).

Initialize: Initialize the weights over all edges of the neural network. The topology of the neural network defines the number of input (features), number of layers and number of hidden nodes in each hidden layer. Take a 2-layer NN as an example.

4. Calculate the cost using a cost function over all documents of this query: Cost(q)=f(On, On+1, . . . , Om)

5: Back propagate using the gradient calculated from Cost(q)

6: End for;

7: End for;

LambdaRank Algorithm

An exemplary training algorithm of a neural network based on LambaRank algorithm is illustrated below using a 2-layer neural network including an input layer (layer 0), a hidden layer (layer 1) and an output layer (layer 2).

Each feature corresponds to an input node. The training starts with a given feature set, which can be any usable set of relevant features, but is preferably a feature set carefully selected using a feature selection method or algorithm.

Calculate: The following is an exemplary pseudocode for the training procedure of the LambaRank algorithm.

where r(n) is the ground-truth rating of document n, and Rank(n) is the ranking position (given by the ground-truth ratings) of document n in this query. G, DG and MaxDCG are calculated as described in K. Jarvelin and J. Kekalainen, IR Evaluation Methods for Retrieving Highly Relevant Documents, In SIGIR 23, pages 41-48, 2000.

W1i(1)=W1i(1)+LearningRate*∑k=0DocNum-1(lambda(k)*Oik(0)),
Where LearningRate could be fixed or changed after every epoch.

7: End for;

8: End for;

Output: neural network models, including the weights and thresholds of the initialized neural network

The above description of the LambaRank algorithm uses the following notations:

Wij(0): i is the hidden node index, j is the feature index, and (0) is the layer index of the input layer.

W1i(1): i is the hidden node index, and (1) is the layer index of the hidden layer.

Oik(0): i is the hidden node index, k is the document index, and (0) is the layer index of the input layer.

Input(k,j): k is the document index, and j is the feature index.

Exemplary FPGA Implementation of LambaRank

In one embodiment, the above-described LambaRank neural network training algorithm is implemented using FPGA. The implementation is at least partially hardware-based using customer-configured a field programmable gate array. A unique data streaming method is used between a host computing device and the FPGA board to enable training of a large data set.

A streaming architecture is used to address the challenges faced by a Web ranking neural network algorithm such as LambaRank. The core concept of this design is to create a high bandwidth processing engine that can consume training data in a continuous order. Given the training data from host computer, a series of operations are performed in multiple computation units (or processing elements) in the processing engine. This design exploits the parallelism without explicitly managing allocation, synchronization, or communication among the computation units. These computation units may be carefully to enable the pipelined, high-bandwidth processing of the training data.

FIG. 4 is a block diagram showing the architecture of an accelerator system 400 that is operable to implement a LambaRank algorithm for relevance-ranking. The accelerator system 400 is based on the accelerator system 100 of FIG. 1, but has certain design aspects and components that are suited for LambaRank algorithm.

The accelerator system 400 includes an FPGA device 401 and a host computer 414 operatively in connection with each other. The FPGA device 401 has an FPGA 406 residing on a substrate, such as a PCI card 405. The FPGA board 406 is designed for a single PC with PCI interface connected to the host computer 414. One embodiment of the FPGA device 401 is a PCI card plugged in the host computer 414. The FPGA 406 has an onboard memory 408. Through a PCI interface 422, the PCI board 404 may interface with a PCI bus 416 on or associated with the host computer 414. The PCI board 404, and/or devices thereon, may communicate with the bus 416 thorough a PCI controller 418. The computation logic blocks of FPGA 406 are programmed to comprise a hidden layer processing engine hPE 460 and the output layer processing engine oPE 456. Each engine is configured to perform computation associated with the respective layer of the LambaRank algorithm being implemented, hidden layer by hPE 460 and the output layer by oPE 456, respectively. The hidden layer processing engine hPE 460 has a plurality of processing elements PE0-PE19, each representing a hidden node of the hidden layer. The illustrated hPE 460 has twenty processing elements. Although the number of the processing elements is flexible in principle, the choice may have an impact on the performance, complexity and cost of the FPGA accelerator 401. As will be shown, processing elements PE0-PE 19 can each be arithmetic logic unit (ALU) in some embodiments.

The FPGA 406 further has an internal memory 424 directly accessible by the processing engines such as hPE 460 and oPE 456.

The FPGA 406 further has a lambda unit 458 to perform computation associated with the calculation of lambda in the LambaRank algorithm. The lambda unit 458 may also have direct access to the internal memory 424. The FPGA 406, including the process engines hPE 460, oPE 456 and the lambda unit 458, is controlled by a control unit 454. The data communicated from the host computer 414 through PCI interface 422 is parsed by the parser 452.

One suitable commercial example that can be configured as FPGA 406 is Altera Stratix-II FPGA, which has logic array blocks (LABs) that can be programmed as processing elements, and memory block structures (such as M512 RAM, M4K RAM, and M-RAM blocks) that can be used as the internal memory as described herein. Altera Stratix-II FPGAs further support various high-speed external memory interfaces, including double data rate (DDR) SDRAM and DDR2 SDRAM, RLDRAM II, quad data rate (QDR) II SRAM, and single data rate (SDR) SDRAM.

The PCI controller 418 may either be an integral part of the FPGA 406 or a separate chip but placed on the same PCI board 404 together with the FPGA 406. One suitable commercial example for the PCI controller 418 is Xilinx Virtex5, which is a PCIe interface chip.

FIG. 5 is a block diagram showing a hardware-related LambaRank implementation using an accelerator system 500. FIG. 5 may be seen as a different representation of the accelerator system 400 showing certain process details but omitting some others. Particularly, the processing engines hPE 460 and oPE 456 in FIG. 4 are represented in FIG. 5 by their functional blocks FP 562 and BP 564 for the computations associated with forward propagation and backward propagation, respectively, in the LambaRank algorithm.

FPGA 506 operatively implements LambaRank Web relevance training algorithm. LambaRank software 542 is installed on the host computer 514, but at least part of the LambaRank training computation is implemented on and carried out by the FPGA 506. The LambaRank software 542 may have, or be associated with, a driver 544 having a register read/write (R/W) module 538 and/or a direct memory access read/write (DMA R/W) module 537 for operation of the LambaRank software 542 with the CPU, memory and storage of the host computer 514 through a PCI controller 518.

The FPGA 506 may include a PCI local interface 524 for interfacing between the PCI controller 518 and the processing units of the FPGA 506, e.g., FP 562, lambda unit 558 and BP 564. The PCI local interface 524 provides a downstream channel to stream data from the host computer 514 to the processing units FP 562, lambda unit 558 and BP 564 of the FPGA 506, and an upstream channel to send data from the processing units of the FPGA 506 to the host computer 514. The downstream channel users a register 525 as a placeholder for the stream data for data delays and shifts, and an FIFO 526 for PCI-to-FPGA data transmission. The upstream channel has an FIFO 528 for FPGA-to-PCI data transmission. Through the PCI local interface 522, the stream data including the feature data is sent to the forward propagation unit FP 562 to perform forward propagation calculations. At the same time, for each query, at least some data are temporarily stored in a query buffer 570 to be subsequently used by the backward propagation unit BP 564 to perform backward propagation calculations. This provides direct access of such data by the backward propagation unit BP 564 such that it does not have to request the same data from the host computer 514. Label data (such as ratings of the documents in the training data) are sent to the lambda unit 558 to perform lambda calculation.

The processing units FP 562, BP 564 and the lambda unit 558 implement the computation logic. As shown in FIG. 4, these processing units may comprise multiple processing engines (hPE 460 and oPE 456) and/or processing elements (PE0-PE19). The FPGA 506 may also have a memory management unit (MMU) for aligning or managing data for faster processing. The processing units of the FPGA 506 return an output to the PCI local interface 522 for further implementation or other use.

FIG. 6 illustrates an exemplary workflow 600 for using an FPGA accelerator such as shown in FIGS. 4-5 to train a neural network. The workflow 600 shows the actions taken by or occurring in software and hardware in the training processing, as well as the alternation therebetween. The first column 602 represents actions taken by the application software installed on a host computer such as 514. The second column 606 describes actions performed on, or by, hardware, such as accelerator device 401. In the following, steps (a)-(h) and (ee)-(hh) are steps for training a neural network algorithm such as LambaRank.

At (a), the application software prepares and parses the training data and parameters of neural networks model stored on the host computer. The possible data processing at this point may include organizing the data in the sequence of how the FPGA logic will access and utilize it. At (b), application software calls the write routine in the driver installed on the host computer to write the data to memories on the FPGA accelerator. The write routine may be implemented with a direct memory access (DMA) method to achieve high bandwidth access to the accelerator. At (c), the software sends instructions to set the initialize register (a register for initialization) and starts to write the initialized data onto the accelerator hardware with the DMA write. At (d), the software continues to poll or wait for the “DMA write done” register (a register to indicate the status of “DMA write done”) until the register is pulled up by hardware. At (e), the software pulls up the round-start register to declare a new round.

After this point, the actions on the application software side and the actions on the accelerator hardware side take place interactively. At (ee), the hardware waits for the announcement of a round-start from the software. Meanwhile, at (f), the software writes training data onto the hardware with DMA write. At least some of the training data is written directly to an internal memory (such as internal memory 424) directly accessible by the FPGA computation logic blocks such as processing units or processing engines. At (ff), the hardware parses the training data written by the DMA write and starts the training process. At (gg), the hardware continues the training process until the round finishes, and then sets the round-finish register valid. At (g), the software continues to poll the round-finish register until hardware pulls up the register. At (h), the software sets the prepare register (a register indicating a status of training result preparation) valid and reads training results from hardware with DMA read. At (hh), the hardware polls the prepare register until the register is pulled up by software, and then sends training results to the software. The training results may be intermediate data or final results.

In the training process, drivers (e.g., 444 and 544) installed on the host computer also runs driver routines to facilitate the communication between the application software and the accelerator hardware. The operations of the driver may mainly include register write, register read, DMA write and DMA read. Register access (write/raad) is used to communicate status and control signals between the software and the hardware. DMA engine could write/read large number of data without bringing heavy load to CPU. Software uses DMA write routines to write initialized data and feature data to memories in hardware. At the end of each round of the training process, DMA read is used to read back results from hardware.

Data Flow and Data Format

In lambda rank algorithm, the target is to find the optimal weights and thresholds for the neural networks in order to construct an efficient computation model for purposes such as Web ranking. A straightforward exemplary data flow is shown below:

Algorithm: LambdaRank

Initialize: initial Weight RAM and Threshold RAM

Do for t=1, 2, . . . N query

(1) Perform Forward Process (FP 562)

(2) Perform Lambda Calculation (lambda unit 558)

(3) Perform Backward Propagation (BP 564)

Output: the updated weights and thresholds of the neural networks.

To enable the data streaming mode access by the FPGA 506 (or FPGA 406), an exemplary data format as shown in FIG. 7 is used.

FIG. 7 shows an exemplary data format used for data streaming from a host computer (e.g., 514) to an FPGA (e.g., 506). The data format 700 represents a data stream in which each row represents a data row containing eight bytes (64 bits of data) arriving at the same time. In the illustrated example, all data is 64-bit aligned, and the blank parts are complemented by zeros. Any other size of the data row may be used, depending on the hardware characteristics. In each data block, some bytes are combined to contain the same data entry. Multiple data rows provide a data block for a query, and such multi-row data blocks arriving sequentially representing one query at a time. For example, data format 600 illustrates two data blocks, one for query 0 and the other for query 1. In the training, the data block for query 2 (not shown) follows the data block of query 1, and so on.

Further detail of the data format is explained using the data block of query 0. In each row, the data is filled from the right to the left. It is shown that the first row contains eight bytes, of which the first two bytes (the two bytes to the right in the first row) are combined to contain digits that represent the total number of documents in the training data for the present query (query 0); next two bytes are combined to contain digits that represent the total number of pairs of documents in the training data for the present query (query 0); and the next four bytes blank bytes (or fixed number of bytes). In the illustrated example, the total number of documents is four, mainly Doc 0, Doc 1, Doc 2 and Doc 4. In an actual web ranking training data set, the total number of documents in each query tends to be much greater.

The next two rows (the second and the third rows) of data contain data for indexes of the document pairs that are ranked together in relation to each other. Not all possible document pairs are used in the training in every query. Only those that are relevant are specified in these pair index rows. Every two bytes defining the identification of a specific pair, with the first byte defining the higher index (Index (H)) of the pair and the second byte defining the lower index of the pair (Index (L)). In the example illustrated in data format 600, there are five relevant document pairs for query 0. Unused bytes in the pair index rows are left blank. Naturally, if a large number of document pairs require more than two rows to define, the pair index rows may include more than two rows.

The next three rows (the fourth, fifth and sixth rows) of the data contain normalized gains

(Gr(n)-Gr(m))MaxDCG,
which can be pre-calculated from the training data and can therefore can be streamed from the host computer to the FPGA. In comparison, the terms (DGRank(n)−DGRank(m)) in the lambda calculation are to be calculated during the neural network learning by the FPGA. Each document pair corresponds to a normalized gain.

The rest of the rows of the data block for query 0 contain feature values of each document in the current query (query 0). In a Web ranking neural network, each document has a feature value with respect to each of the Nf features. This feature value is the input value for the corresponding node of the input layer of the neural network. The data format 600 illustrates four features (features 0-3), but any number features may be used depending on the selected feature set.

The data format for the next query (query 1) and all other subsequent queries is similar and will not be repeated herein.

The streamed data contains necessary information (generated and inserted by software), with which FPGA logic can perform computing functions over the data stream without interaction with software or drivers. Furthermore, the data is organized in the sequence of how FPGA logic is accessing and utilizing it, such that input data is consumed at the time FPGA logic receives it. The FPGA may buffer the result for a delayed read from the software, which further reduces the time and processing cost of hardware/software communication.

Processing Engine Architecture

In order to maximize the acceleration of the neural network training, the FPGA logic units (processing elements) are elaborately arranged. The LambdaRank, for example, mainly include three steps: forward process (FP), lambda calculation, and backward propagation (BP), according to the algorithm described herein. In these three steps, forward process and backward propagation share many basic calculation items. For efficient usage of FPGA board resources, one embodiment combines the FP and BP in one computation unit or processing engine. Moreover, a refined structured pipeline is integrated to the computation unit.

FIG. 8 is a diagram showing an exemplary architecture of the processing engines of the FPGA. The FPGA computation structure 800 has three main computation units, namely hidden layer processing engine hPE 860, output layer processing engine oPE 856 and lambda calculation unit 858. The data layer processing engine hPE 860 performs both FP and BP computations. Its main components are memory units RAM 868, control unit 854 and arithmetic logical units (ALU) ALU0870. For mapping to the structure of the neural network, ALU0870 is thought to be the hidden node layer. In the illustrated computation structure 800, the number of hidden nodes is ten, realized by Alu0_0-Alu0_9, which are all instances of ALU0. Each instance of ALU0 has access to corresponding data such as a threshold, an output node weight, an intermediate hidden node output, a hidden node weight O and the term 1-O2. These data are aligned with their corresponding arithmetic logic unit Alu0_0-Alu0_9 to be directly accessed the respective arithmetic logic unit Alu0_0-Alu0_9. The output node is realized by the oPE 856. These components are further illustrated below.

FIG. 9 is a diagram showing an exemplary structure of an arithmetic logic unit (ALU) in the FPGA. The arithmetic logic unit 900 is an exemplary instance of ALU0 which accomplishes the calculations associated with the hidden nodes. These calculations are a critical part in the neural network. As shown in FIG. 9, each instance of ALU0 is an arithmetic logic unit 800 which includes several multipliers M0, M10, M11 and M3, and several accumulators (adders) A20, A21, A22, A24 and A4. The arrangement of these multipliers and accumulators are configured according to the calculations associated with the hidden nodes of the neural network algorithm. The illustrated instance of ALU0 (800) is particularly designed for LambaRank. In one embodiment, each multiplier is a 3-pipeline floating point multiplier, and accumulator a 3-pipeline floating point accumulator. The detail of these 3-pipeline floating point multipliers and accumulators will be illustrated in a later section of this disclosure.

The ALU0, including its instances (such as arithmetic logic unit 900), is designed for FP and BP elaborately. The sequential processing relation is designed to be able to reuse calculation resources. In addition, a two-step arrangement is made for the pipeline. The relations between operating codes and the stages of pipeline can be seen in FIG. 9.

Forward propagation is implemented by the hidden node layer and the output node layer which consist of nodes having calculation abilities. As described earlier, ALU0 including its Alu0 instances constitutes the hidden node layer processing engine hPE, while the output processing engine oPE is the output node layer which has only one node. For every instance of ALU0, alu0_opcode generated by hPE_cu controls the status of the respective calculators. The oPE mainly realizes tanh and multiplier_accumulator functions in order to calculate the output O of the LambaRank neural network. Tanh function is referred in the implementation of sigmoid function, the detail of which will be shown later.

The basic structure of backward propagation is similar to or the same as ALU0 in the forward propagation. Although hPE_cu will make some differences in the alu0_opcode and the status of the calculators of backward propagation as compared to the forward propagation, the calculation process of backward propagation is closely associated with the hidden node layer. The sequential processes of the backward propagation and the forward propagation are thus combined for reusing of computing resources based on this commonality.

Lambda Calculation Architecture

Lambda calculation is the computation unit for calculating the critical parameter LAMBDA. This is the second step in LambaRank algorithm.

FIG. 10 shows an exemplary structure of processing modules in the lambda calculation unit. FP passes the results to the lambda calculation unit 1058. The lambda calculation unit 1058 puts the lambda values in the memory for BP. In the lambda calculation unit 1058, fp_o_rank ranks the FP results and stores them in the Rank RAM, which may be part of the internal memory of the FPGA. Under the control of lambda_calculation_control module, Lambda_calculation_datapath directs the data flow and calculation processing.

Data Organization

The accelerator system supports hierarchical memory organization and access methods using SDRAM, SRAM and RAM/registers within the FPGA.

According to one example, training data that will be iteratively used is streamed to an FPGA accelerator device, such as FPGA 106. The streamed training data may be organized according to its access order in logic associated with the FPGA so that the FPGA can fetch data in a so-called, and well-known, “burst” mode, thus enabling high bandwidth access to the data set.

Temporary data structures, such as intermediate variables, parameters, and so forth, and results, e.g., the learned model, could be stored in the onboard memory (such as the onboard memory 108) or registers inside the FPGA, which would act as high bandwidth, low latency cache. The data could be utilized without needing to access memory off of the FPGA, which would enhance the access speed of the cache.

Data Compression/Decompression

A bit-map based data compression/decompression method for the architecture may be implemented to increase memory capacity and bandwidth available in the accelerator system. Training data may be compressed by conventional compression software and stored in the memories associated with the acceleration device. The FPGA may then read and decompress the data before performing computations.

Implementation of Sigmoid

One embodiment has an efficient approximation of the sigmoid function implemented in the FPGA-based reprogrammable hardware-based artificial neural networks. The sigmoid part of the FPGA realizes the function sigmoid(x)=1/(1+exp(−x)), where x is the input. This module is consisted of a fixed-point number sigmoid function and an interpolation module. An exemplary implementation of the sigmoid function is disclosed in an article by M. T. Tommiskal, “Efficient Digital Implementation of the Sigmoid Function for Reprogrammable Logic”, IEE Proceedings—Computers and Digital Techniques, November 2003, Volume 150, Issue 6, p. 403-411. The interpolation part is a linear interpolation and coded for the specification fixed point numbers which are output from the sigmoid function. The interpolation is a linear interpolation which gives the final result from to the nearest two sigmoid values.

The core of this module is implemented by combinational circuit. The input data is a 3.3 fixed-point number. The output signal is 7-bit fraction and the integer part is assumed to be 0. The combinational (And_Plane) and sequential (Or_Plane) logic equations come from the table of the above referenced paper.

Floating Point Library

In the FPGA-based board, the referred floating point calculators mainly point to the adder and multiplier. For a clear conception, the adder is referred to with the name AddSubFloat32P3 because the adder could add/sub floating point number and has three-stage pipeline. The multiplier is called MulFloat32P3 for the same reason.

Adders

The automatically generated adder by tools provided by hardware component manufacturers (e.g., Altera's IP core) may not satisfy the requirements of certain neural network algorithms, such as LambaRank. The pipeline depth of seven or eight is found to be too deep to improve the efficiency of resources. Accordingly, some embodiments of the disclosed FPGA use three-stage adders with a similar frequency performance to short the pipeline. The implementation of the AddSubFloat32P3 module may be restricted with IEEE 754.

FIG. 11 illustrates an exemplary pipeline division in each processing unit such as an arithmetic logic unit. Illustrated in FIG. 11 is an exemplary three-pipeline (three-stage) adder used in arithmetic logic units of the FPGA. The first stage (Pipeline_0) sets up or prepares the shifted operands. The module obtains the difference signs of two operands, puts the input number with smaller exponent as the second operand, shifts the second operand, and changes it to 2's complement if signs are different. The second stage (Pipeline_1) adds up the two operands and prepares for calculating the leading-zero and rounding. The last stage (Pipeline_2) calculates the rounding result and constructs the three parts of the number (sign, exponent and mantissa) as an IEEE 754 floating point and outputs the result as sum_out.

The logic of the above second stage (Pipeline_1) is complex. It not only obtains the adder result of the shifted operands, but also prepares data for the next stage. The direct adding result needs to be changed to the real adder result. In other words, if the signs of operands are different, the adding result should change to its 2's complement; and if the signs are same, the adder result is the adding result. In practice, the first stage (Pipeline_0) has already got the guard bit, round bit and stick bit. After getting adder result, these three special bits are changed to a new guard bit, round bit and sticky bit. Exemplary rules can be derived from IEEE 754. At the same time, the adder result needs to be sent to the task part which calculates the number of leading-zero in it.

At the last stage (Pipeline_2), the rounding mantissa and the number of leading-zero in the adder result are both obtained. The three parts of the final result are then constructed according to the calculation rules.

Multipliers

The automatically generated multiplier by the tools provided by the component manufacturers (e.g., Altera's IP core) may not satisfy the requirements of some embodiments. The pipeline depth of five or six is found to be too deep to improve the efficiency of resources. Accordingly, some embodiments use a three-stage multiplier with a similar frequency performance to short the pipeline. The implementation of the multiplier MulFloat32P3 module is also restricted with IEEE 754 standard.

In an exemplary multiplier module, the calculation process is divided into three stages. The first stage divides two operands into three parts, preparing the exponent of the result. The second stage multiplies two operands and gets the mantissa for rounding. The last pipe calculates the rounding result and constructs three parts of the result (sign, exponent and mantissa) as an IEEE 754 floating point.

Performance

An exemplary model for measuring the performance of LambdaRank accelerator training is provided below. The exemplary performance model can be expressed as:
ttotal=tini+Nround*tround
Where the initialization time tini and per training round time tround are dependent on the implementation. The initialization time tini is relatively small in the hardware or software implementations compared with the training process. The main focus of the performance is thus on the modeling of the executing time of each training round.

For the executing time of the hardware and software implementation, in every round, the time of the training process could be calculated using the time used for training one query multiplied by the number of the queries directly. The processing time for a query can be divided into three parts as described herein, forward process (forward propagation), lambda calculation and backward propagation. Here, the forward process refers to the typical multiply-and-accumulate calculations for every feature in the neural networks. The processing of lambda calculation is decided by the partial ordering relations of the documents. Thus the processing time could be measured by the number of pairs which appear in the partial order in the current query. Lastly, the representation of backward propagation is similar to the forward process, except it adds two additional updating processes. In summary, the execution time around is given:
tround(HW)=Nquery*(αNdoc*Nf+βNdoc+μNpairs+Υ)

In some embodiments, such as the illustrated implementation of LambaRank algorithm, the FPGA-based accelerator significantly improves the speed of the training. For example, an exemplary accelerator system is able to speed up the LambdaRank algorithm by 15x˜30x on real search engine data. The training time for a typical run is reduced from 10 hours to about 20 minutes. As a result, the accelerator system enables the developers and researchers more trials in the same amount of working time, and produces much higher quality ranking models in a cost efficient way.

It is appreciated that the potential benefits and advantages discussed herein are not to be construed as a limitation or restriction to the scope of the appended claims.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as exemplary forms of implementing the claims.