Operation: Serial data is transmitted in two’s complement with the MSB first (one clock period after the WS changes).Transmitter and Receiver may have different word lengths(Word length adjustable upto 28 bits).If receiver is sent more bits than its word length, bits after its LSB are ignored. If receiver is sent fewer bits than its word length, missing bits are set to zero internally.Transmitter essentially consists a parallel to serial shift register.SCK defines the data rate. SD is the serial data out from the shift register.WS: The number of clock cycles it is asserted, defines the transmitter word length.Receiver essentially consists a serial to parallel converter.A counter is used at the receiver to count the number of cycles WS is assertedto find the transmitted word length.

Create my first project at Github: This script can be downloaded from https://github.com/agraja/text2perl/blob/master/text2perl.pl #!/usr/bin/perl # Tiny preprocessor: # Example: Paste this example in a file # Pass it as argument to this script # some text /* for(1..5) { */ # this line will be printed 5 times # /* } */ open(P,”|$^X”); print P […]

Here is a preprocessor in perl, primarily for Verilog, SystemVerilog, but may be used for any language. There are programs with a lot of repetitive text. Language features like functions, objects can reduce typing. Still, there is scope for putting it in lesser code using a text preprocessor. Limitations in existing preprocessors prompted in writing a new on […]

Wire Can be used for input, output, inout Multiple drivers, No drivers cause x Usage: Wire variable = value; Assign variable = value; Can be used to connect module instances Reg Can be used only for input Can’t be used in ‘assign’ statement It takes last assigned value, behaves like a variable Note: R […]