Abstract:

An apparatus and method for wafer level fabrication of high value
inductors directly on top of semiconductor integrated circuits. The
apparatus and method includes fabricating a semiconductor wafer including
a plurality of dice, each of the dice including power circuitry and a
switching node. Once the wafer is fabricated, then a plurality of
inductors are fabricated directly onto the plurality of dice on the wafer
respectively. Each inductor is fabricated by forming a plurality of
magnetic core inductor members on an interconnect dielectric layer formed
on the wafer. An insulating layer, and then inductor coils, are then
formed over the plurality of magnetic core inductor members over each
die. A plated magnetic layer is formed over the plurality of inductors
respectively to raise the permeability and inductance of the structure.

Claims:

1. An apparatus, comprising:an integrated circuit with power regulation
circuitry fabricated thereon;a switching node contact in electrical
connection with the power regulation circuitry on the integrated
circuit;an interconnect dielectric layer formed over the power regulation
circuitry and the switching node contact of the integrated circuit;a
plurality of magnetic core inductor members formed on the interconnect
dielectric;an inductor coil formed over the plurality of magnetic core
inductor members;a second dielectric layer formed over the inductor coil;
anda plated magnetic layer formed over the second dielectric.

2. The apparatus of claim 1, further comprising an electrical connection
between the inductor coil and the switching node.

3. The apparatus of claim 1, wherein the inductor coil is copper.

4. The apparatus of claim 1, wherein the magnetic core inductor members
are NiFe or NiFeCo.

5. The apparatus of claim 1, wherein the magnetic core inductor members
are laminations perpendicular to the direction of current flow through
the inductor coil.

6. The apparatus of claim 1, wherein the plated magnetic layer is NiFe or
NiFeCo.

7. A method comprising:fabricating a semiconductor wafer including a
plurality of dice, each of the die including power circuitry;fabricating
a plurality of magnetic core inductor members on an interconnect
dielectric layer formed over a plurality of dice on the wafer, including
forming a photoresist layer over a conducting layer, patterning the
photoresist layer to form molds therein, and filling the molds with a
conductive material;fabricating a plurality of inductor coils over the
plurality of magnetic core inductor members, including forming a
planarization surface over the plurality of magnetic core inductor
members, forming an insulation layer over the planarization surface,
forming a photoresist layer over the insulation layer, patterning the
photoresist layer to form a plurality of molds, and filling the plurality
of molds with a conductive material, wherein a plurality of inductors
directly onto the plurality of dice on the wafer are created, each of the
inductors being in electrical contact with the power circuitry on each of
the die respectively; andfabricating a plated magnetic layer over but not
under the plurality of inductors respectively, wherein no plated magnetic
layer is formed under the plurality of inductors.

8. The method of claim 7, wherein fabricating the semiconductor wafer
further comprises forming a switching node contact in electrical
connection with the power circuitry on each of the die on the wafer
respectively.

9. The method of claim 7, wherein fabricating the plurality of magnetic
core inductor members further comprises forming a plurality of
rectangular shaped members of NiFe or NiFeCo patterned on the wafer
surface.

10. The method of claim 7, wherein fabricating the plurality of magnetic
core inductor members further comprises:forming an adhesion layer over
the interconnect dielectric layer formed over each die on the wafer
respectively;forming a seed layer over the adhesive layer; andforming an
oxide protection layer over the seed layer.

11. The method of claim 10, further comprising:sputtering titanium over
the interconnect dielectric layer to form the adhesion layer;sputtering
copper over the titanium layer to form the seed layer; andsputtering a
second titanium layer over the copper layer to form the oxide protection
layer.

12. The method of claim 11, wherein forming the plurality of magnetic core
inductor members further comprises forming a plurality of rectangular
shaped members of NiFe or NiFeCo patterned on the wafer surface, and
wherein forming the plurality of rectangular shaped members of NiFe or
NiFeCo patterned on the wafer surface further comprises:forming a
photoresist layer over the second titanium layer;patterning the
photoresist layer to form rectangular shaped molds in the photoresist
layer; andfilling the molds with NiFe or NiFeCo to form the plurality of
rectangular shaped members.

13. The method of claim 7, further comprising:forming a plurality of
electrical connections between the plurality of inductor coils and a
plurality of switching node contacts on each of the die on the wafer
respectively.

14. The method of claim 7, wherein fabricating the plurality of top plated
magnetic layer over the plurality of inductors further comprises:forming
a protective layer over the plurality of inductors; andelectroplating a
ferromagnetic material over the protective layer.

15. The method of claim 14, wherein the protective layer consists of one
of the following types: an oxide layer; a nitride layer, oxy-nitride
layer, or a combination thereof.

16. The method of claim 14, wherein the electroplating a ferromagnetic
material consists of one of the following: NiFe or NiFeCo.

17. The method of claim 14, wherein electroplating the ferromagnetic
material further comprises:forming an adhesion layer over the blanket
protective layer;forming a seed layer over the adhesive layer; andforming
an oxide protection layer over the seed layer.

18. The method of claim 17, further comprising:sputtering titanium over
blanket protection layer to form the adhesion layer;sputtering copper
over the titanium layer to form the seed layer; andsputtering a second
titanium layer over the copper layer to form the oxide protection layer.

19. The method of claim 18, wherein electroplating the ferromagnetic
material over the protective layer further comprises:stripping the second
titanium layer;applying a negative potential to the wafer;
andelectroplating the wafer in a NiFe or NiFeCo electroplate bath.

Description:

CROSS REFERENCE TO RELATED APPLICATION

[0001]This application is a continuation of and claims priority to
commonly owned and co-pending U.S. patent application Ser. No.
11/504,972, filed Aug. 15, 2006, and entitled "APPARATUS AND METHOD FOR
WAFER LEVEL FABRICATION OF HIGH VALUE INDUCTORS ON SEMICONDUCTOR
INTEGRATED CIRCUITS," which is incorporated herein by reference in its
entirety and for all purposes.

BACKGROUND

[0002]The present invention relates to semiconductor integrated circuits,
and more particularly, to an apparatus and method for wafer level
fabrication of high value inductors directly on top of semiconductor
integrated circuits.

[0003]Inductors are commonly used in the electronics industry for storing
magnetic energy. An inductor is typically created by providing an
electric current though a metal conductor, such as a metal plate or bar.
The current passing though the metal conductor creates a magnet field or
flux around the conductor. The amount of inductance is measured in terms
of Henries. In the semiconductor industry, it is known to form inductors
on integrated circuits. The inductors are typically created by
fabricating what is commonly called an "air coil" inductor on the chip.
The air coil inductor is usually either aluminum or some other metal
patterned in a helical, toroidal or a "watch spring" coil shape. By
applying a current through the inductor, the magnetic flux is created.

[0004]Inductors are used on chips for a number of applications. Perhaps
the most common application is direct current to direct current or DC to
DC switching regulators. In many situations, however, on chip inductors
do not generate enough flux or energy for a particular application. When
this occurs, very often an off-chip discrete inductor is used.

[0005]There are a number of problems in using off-chip inductors.
Foremost, they tend to be expensive. With advances in semiconductor
process technology, millions upon millions of transistors can be
fabricated onto a single chip. With all these transistors, designers have
been able to cram a tremendous amount of functionality onto a single chip
and an entire system on just one or a handful of chips. Providing an
off-chip inductor can therefore be relatively expensive. Off-chip
inductors can also be problematic in situations where space is at a
premium. In a cell phone or personal digital assistant (PDA) for example,
it may be difficult to squeeze a discrete inductor into a compact
package. As a result, the consumer product may not be as small or compact
as desired.

[0006]An apparatus and method for wafer level fabrication of high value
inductors directly on top of semiconductor integrated circuits is
therefore needed.

SUMMARY

[0007]An apparatus and method for wafer level fabrication of high value
inductors directly on top of semiconductor integrated circuits is
disclosed. The apparatus and method includes fabricating a semiconductor
wafer including a plurality of dice, each of the dice including power
circuitry and a switching node. Once the wafer is fabricated, then a
plurality of inductors are fabricated directly onto the plurality of dice
on the wafer respectively. Each inductor is fabricated by forming a
plurality of magnetic core inductor members on an interconnect dielectric
layer formed on the wafer. An insulating layer, and then inductor coils,
are then formed over the plurality of magnetic core inductor members over
each die. A plated magnetic layer is formed over the plurality of
inductors respectively to raise the permeability and inductance of the
structure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 is a cross section of a semiconductor integrated circuit die
with power circuitry fabricated and an inductor fabricated thereon
according to the present invention.

[0009]FIG. 2 is a semiconductor wafer including a plurality of dice with
power circuitry fabricated thereon according to the present invention.

[0010]FIGS. 3A through 3H are a series of cross sections illustrating the
fabrication of the inductors fabricated on the wafer according to the
present invention.

[0011]FIGS. 4A and 4B illustrate various pattern arrangements of magnetic
core inductors and inductor coils of the inductors fabricated onto the
wafer according to the present invention.

[0012]FIG. 5 illustrates a plated magnetic layer formed over the magnetic
core inductors of either FIG. 4A or 4B according to the present
invention.

[0013]Like elements are designated by like reference numbers in the
Figures.

DETAILED DESCRIPTION

[0014]Referring to FIG. 1, a cross section of a semiconductor integrated
circuit die with power circuitry and an inductor fabricated directly
thereon according to the present invention is shown. The die 10 includes
a silicon substrate 12 with power circuitry fabricated thereon in
accordance with well known semiconductor manufacturing techniques (for
the sake of simplicity, the circuitry is not visible in the figure),
metal interconnect layer(s) 14 including one or more levels of metal
interconnect, and an interconnect dielectric layer 16 formed over the
metal interconnect layers 14. An inductor 18 is fabricated directly on a
plating layer 44 formed over the interconnect dielectric layer 16. The
inductor 18 includes a plurality of magnetic core inductor members 20
provided between resists spacers 22, a planarization surface 24 formed
over the inductor members 20 and spacers 22, an insulating layer 25,
another plating layer 27, an inductor coil 26, a protective layer 34
formed over the coil 26, and a segmented plated magnetic layer 36 formed
over the protective layer 34. An electrical contact 32 is provided
between the coil 26 and a switching node (not shown) provided one of the
metal layers of interconnect 14.

[0015]The present invention is directed to the wafer level fabrication of
the inductor 18 directly onto the die 10 in wafer form. FIGS. 2 and 3A
through 3G illustrate the fabrication sequence.

[0016]Referring to FIG. 2, a semiconductor wafer 40 including a plurality
of dice 10 is shown. Each die 10 includes power regulation circuitry
fabricated thereon, including a switching node 42. For the sake of
simplicity, the power regulation circuitry is not shown or described
herein. The switching node 42 is typically a metal contact of one of the
metal interconnect layers 14. The switching node 42 is in electrical
contact with the underlying transistors forming the power regulation
circuitry on the device.

[0017]In the subsequent discussion with regard to FIGS. 3A through 3F, the
wafer level fabrication process for forming the inductor 18 and the top
plated magnetic layer 34 on the die 10 is described in detail.

[0018]Referring to FIG. 3A, a cross section of the wafer 40 is shown. The
wafer includes the silicon substrate 12 having the power regulation
circuitry fabricated thereon, metal interconnect layers 14, and the
interconnect dielectric layer 16 formed over the metal layers 14. The
fabrication of the design and fabrication of the power circuitry and
metal interconnect levels 14 are well known and therefore are not
described in detail herein. The interconnect dielectric layer 16 is
formed over the metal layers 14.

[0019]The initial step in the fabrication of the inductor 18 involves the
forming of a plating layer 44 across the top surface of the wafer 40. The
plating layer 44 actually includes three layers, including an underlying
oxide protection layer, a middle seed layer, and an upper adhesion layer.
In one embodiment, the plating layer 44 is formed by sputtering 300
Angstroms of titanium, 3000 Angstroms of copper, and 300 Angstroms of
titanium on the wafer surface to form the protection, seed, and adhesion
layers respectively. It should be noted that specific embodiment
disclosed herein in merely exemplary, and that a plating layer 44 can be
formed using any one of a number of well known techniques and materials
and the invention should not be construed as limited to the metals and
thicknesses disclosed herein.

[0020]In the next step as illustrated in FIG. 3B, the photo resist layer
22 is formed over the plating layer 44. In various embodiments, the photo
resist layer 22 can be a spin-on BCB or SU8 layer approximately 30
microns thick. Once the resist layer 22 is formed, it is patterned to
form recess regions 46 that expose the underlying plating layer 44. The
recess regions 44 are formed using well-known photolithography techniques
including masking, exposing and etching of the resist layer 22. The
recess regions 46 form what are in essence "molds" which will be later
used to form the magnetic core inductor members 22.

[0021]As illustrated in FIG. 3c, the magnetic core inductor members 20 are
formed within the molds or recess regions 46 by electroplating. The upper
adhesion layer of titanium of the plating layer 44 is stripped away,
exposing the underlying copper seed layer. A negative bias or voltage is
then applied to the wafer 40 while submerged in a NiFe or a Ni FeCo
plating bath. During the plating, the recess regions 44 are filed with
NiFe or NiFeCo, forming the magnetic core inductor members 20. The recess
regions 44 thus define the shape and location of the inductor members 20
on each die on the wafer 40.

[0022]As illustrated in FIG. 3D, the inductor coils 26 are next formed on
the wafer surface. After the inductor members 20 are formed, the
planarization layer 24 is created across the top surface of the wafer. In
one embodiment, the planarization layer 24 is a spin-on layer such as BCB
or SU8. Once the layer 24 is formed, it is planarized or smoothed using
chemical mechanical polishing (CMP), as is well known in the
semiconductor fabrication art. A dielectric insulating layer 25 is next
formed across the wafer surface. In various embodiments, the insulating
layer 25 is formed by a plasma enhanced chemical vapor deposit of a
material such as oxide, nitride or oxynitride, spinning on a polymer such
as BCB or SU8, or a chemical vapor deposition of a polymer such as
Paralyne.

[0023]As illustrated in FIG. 3E, the inductor coils 26 are formed is a
manner similar to that described above with regard to the inductor
members 20. Specifically, another plating layer 27 including an
underlying oxidation protection Ti layer, a middle seed copper layer, and
an upper adhesion Ti layer, is formed across the wafer surface.
Thereafter, a photo resist layer 29 is formed and patterned, forming
recess regions, which expose the top adhesive Ti layer. The top adhesion
Ti layer is then stripped away, and the wafer 40 undergoes a plating
operation in a copper bath. The inductor coils 26 are formed by the
plating of copper from the bath onto the exposed seed copper layer within
the recess regions. For the sake of brevity, the aforementioned steps are
not illustrated in a sequence of figures. The process, however, is
essentially the same as that described above, and is therefore not
separately illustrated.

[0024]In the next step, the electrical contacts 32 are provided between
the coils 26 and the underlying switching nodes (not shown) provided one
of the metal layers of interconnect 14. The electrical contacts are
formed by etching vias into the top surface of the wafer down to the
switching node contact 42 of each die 10. The vias are then filled with
an electrically conductive material such as aluminum or copper. For the
sake of simplicity, only one electrical contact 32 is illustrated in the
Figures.

[0025]The segmented plated magnetic layer 36 is formed over the protective
layer 34 in the next steps as illustrated in FIGS. 3F and 3G
respectively. After the electrical contacts 32 are made, the protective
layer 34 is next formed. This involves first removing the resist layer 29
used to pattern and form the coil 26. After the resist layer 29 is
removed, a protective dielectric material, such as oxide, nitride, or
oxy-nitride, is deposited. In one embodiment, the protective layer 34 is
deposited to be approximately 1 micron thick. The dielectric material
forms the protective layer 34, which electrically isolates the underlying
coils 26 from the plated magnetic layer 36.

[0026]In the final steps, as illustrated in FIG. 3G, the plated magnetic
layer 36 is formed over the protective layer 34. The magnetic layer 36 is
fabricated by forming another plating layer (not illustrated) including
an underlying oxidation protection Ti layer, a middle seed copper layer,
and an upper adhesion Ti layer, across the wafer surface. A resist mask
(not illustrated) is then formed and patterned to preclude the
electroplating of magnetic material where it is not desired. The top Ti
layer of the plating layer is then stripped away in the exposed areas of
the resist. Thereafter, the wafer 40 undergoes another electroplating
operation in a bath containing a ferromagnetic material, such as NiFe or
NiFeCo, resulting in the plating of the magnetic layer 36. In subsequent
processing steps, the resist and exposed plating layer are removed,
resulting in the structure illustrated in FIG. 3G.

[0027]Referring to FIG. 3H, an enlarged cross section view of the final
die 10 is shown. The die 10 includes the silicon substrate 12 with the
power circuitry fabricated thereon, metal interconnect layers 14,
dielectric layer 16, plating layer 44, and an inductor 18 formed on the
plating layer 44. The inductor 18 includes magnetic core inductor members
20 formed between resist spacers 22, a planarization surface 24 and
insulation layer 25 formed over the inductor members 20 and spacers 22,
the inductor coil 26 formed over the insulation layer 25, the protective
layer 34, and the segmented plated layer 36 formed over the coils 26 and
the protective layer 34.

[0028]The ferromagnetic material, sometimes referred to as a permalloy,
used to form the magnetic layer 36, serves to raise the relative
permeability of the surrounding medium and thus elevate inductance.
Generally speaking, the more ferromagnetic material forming the layer 36,
the more magnetization will occur, creating a higher level of inductance.
In one embodiment, the magnetic layer over the coils 26 is broken into
segments to minimize eddy currents and skin related impedance roll off at
high frequencies of operation.

[0029]FIGS. 4A and 4B illustrate various pattern arrangements of magnetic
core inductors 20 and inductor coil 26 of the inductors before the
protective layer 34 and the magnetic layer 36 are fabricated thereon. In
FIG. 4A, the magnetic core inductors 20 are arranged in a chevron pattern
in the four corners of the die 10 while the coil 26 is a multi-turn coil.
In FIG. 4B, the magnetic core inductors 20 are positioned around the
periphery of the die 10, while the coil 26 makes a single turn. In each
embodiment, the magnetic core inductor members 20 are laminations
perpendicular to the direction of current flow through the inductor coil
26. It should be noted that these two embodiments are exemplary and in no
way should they be construed as limiting. In accordance with the present
invention, the layout of the inductors 20 and coils 26 is arbitrary and
can be done in any desirable manner.

[0030]Referring to FIG. 5, two segments of the plated magnetic layer 36 is
shown formed over the magnetic core inductors of either FIG. 4A or 4B is
shown. In this example, the two segments 36 have been patterned to form
two concentric squares over the underlying coil 36 and magnetic core
inductors 20. It should be understood, however, that the magnetic layer
36 can be patterned to virtually any desirable shape and should not be
limited to the specific embodiment illustrated herein.

[0031]While this invention has been described in terms of several
preferred embodiments, there are alteration, permutations, and
equivalents, which fall within the scope of this invention. It should
also be noted that there are many alternative ways of implementing the
methods and apparatuses of the present invention. For example, the steps
of the present invention may be used to form a plurality of high value
inductors 10 across many die on a semiconductor wafer. It is therefore
intended that the following appended claims be interpreted as including
all such alterations, permutations, and equivalents as fall within the
true spirit and scope of the present invention.