aef-embedded

วันอาทิตย์ที่ 12 กรกฎาคม พ.ศ. 2552

AVRUSBBoot is a bootloader for the Atmel AVR controllers. It uses a firmware-only USB driver to transfer binary data from thePC to the flash of the controller. Once the AVR is flashed with the bootloader, no other ISP programmer is needed; then themicrocontroller can be reprogrammed over USB.FeaturesSoftware works under multiple platforms. Linux, Mac OS X and Windows are tested.Tested with ATMega8-16No special USB controllers or smd components are needed.Bootloader fits into 1024 word bootloader blockHardwareBasically AVRUSBBoot can be used with all circuits which are supported by the AVR USB driver. To switch between thebootloader and the application, an aditional jumper is necessary. Here is an example (Here the levels on the data lines are 5Vwhich doesn't meet the USB specification! The supply voltage should be regulated to 3,3V - 3,6V):Firmware and adaptationThe firmware has to be adapted to your hardware. All necessary changes has to be done in the following two files:bootloaderconfig.h:Define the condition when the bootloader should be started, e.g. if a special pin is put to ground with a jumper, and theinitialisation of the hardware.usbconfig.h:Define the used data line pins. You have to adapt USB_CFG_IOPORT, USB_CFG_DMINUS_BIT andUSB_CFG_DPLUS_BIT to your hardware. The rest should be left unchanged.Compile the firmware. You need avr-gcc, avr-binutils and avr-libc:

$ cd firmware$ make

The bootloader firmware has to be written to the controller with a ISP programmer. Once the bootloader is flashed, you don'tneed a programmer and you can download the binary data over USB. Don't forget to set the fuses for the external clock sourcewhen flashing the bootloader for the first time!

SoftwareA C++ tool for downloading hex files is provided. To compile the program, you need libusb.

$ cd software$ make

When the device is connected and the bootloader is started (set the jumper before connecting the device), hex files can bewritten to the flash of the microcontroller:

วันพฤหัสบดีที่ 9 กรกฎาคม พ.ศ. 2552

USBasp is a USB in-circuit programmer for Atmel AVR controllers. It simplyconsists of an ATMega48 or an ATMega8 and a couple of passivecomponents.The programmer uses a firmware-only USB driver, nospecial USB controller is needed.

วันเสาร์ที่ 4 กรกฎาคม พ.ศ. 2552

It was twenty years ago that I left my on-grid home, and my job as an electronics engineer, to begin life on an alternative energy oriented organic farm. In the intervening years, I haveinstalled, maintained, and experimented with numerous RE systems in my area.

What I have come to understand from this experience is that off-grid life tends to become very much focused on the battery bank and its fate.

All power sources and loads breathe through this crucial pathway. Batteries are heavy, toxic, inefficient, and—to the amazement of many—electrically very fragile. Weak or failing batteries are a very likely cause of breakdown, especially in smaller solar-electric systems.Most newcomers to renewable energy are quite familiar with using water tanks or gas tanks, and naturally use this familiarity in trying to understand their battery banks. Everyone knows that a bigger water tank is better than a small one. Unfortunately, batteries are not like tanks, and the result is trouble. It is definitely not true that a big battery bank is necessarily better than a small one. An oversized battery bank can be almost impossible to charge properly. Without a minimum daily exercise regimen, it can become the equivalent of a couch potato. The main culprit is sulfation, which is a gradual crystallization of the battery’s plate material, rendering it electrically inactive.

Some TheoryPast issues of Home Power (see Access) have gone into the details of keeping lead-acid batteries healthy, so I will only touch on the main points here. The usual practice in maintaining a battery in good condition is to apply a periodic equalization charge over and above what would be a normal full charge. Unfortunately, this is an energy-wasting tactic. It ultimately results in cleanbattery plates, but at a steep price, especially if the energy must come from a generator.I initially went to the Internet to find any available information on the problem of sulfation. The search engines turned up several commercial sites that give useful details on the fine points of battery charging and equalization. A second resource is the IBM patent server (www.patents.ibm.com). I found relevant patents there, using keywords like “desulfate” and “rejuvenate.”

What this wealth of data shows is that there are numerous strategies for charging and electrically desulfating batteries. Most of them were designed or developed in the last twenty years or so. Considering that lead-acid batteries have been around for more thana century, this is a relatively new innovation. Virtually all of the devices and patents I found have in common the use of some form of pulsing charge current. This is in contrast to the constant or slowly varying currents generated by sources like solar-electric panels.

I distilled and simplified these various techniques, and came up with a basic circuit that will keep small to medium sized batteries in desulfated condition. It can even be used to bring old, sulfated units back into service. Use of the circuit has dramatically reduced the need for equalization charges in my own home system. Resonant Frequency The technique used in this circuit relies on a little known aspect of lead-acid batteries. They possess what is called a “resonant frequency,” at a surprisingly high frequency. The frequency is dependent on various physical details of the battery’s construction, but it is on the order of 2 to 6 megahertz, which is in the low

This resonance is just like that of a stringed musical instrument, where a pluck of the string creates a vibration of a specific tone. In the case of the battery,sulfur ions dissolved in the electrolyte take the place of the string. A sufficiently energetic electrical “pluck,” or pulse, will cause a similar vibration of these ions, backand forth throughout the electrolyte. When this vibrational state isoccurring, there are uncountable collisions between the ions in the electrolyte and the battery plates, as the back and forth vibration continues. It is this rhythmic beating of the plates which causes the breakup of the crystalline deposits, slowly but surely, for as long as the electrical pulsations are applied.It is not unlike sandblasting a rough surface, but on a micro-physical level. This is an advantage of electrical methods over the use of chemicals like EDTA. Rather than dissolving the sulfate deposit and allowing it to settle on the bottom of each cell, as with EDTA, the pulse technique returns the sulfate back into solution again.

Circuit DetailsThe circuit is in essence a very widely used form of switching DCto-DC convertor, which can take a DC voltage and step it up to a higher level. Figure 1 shows the version which is specifically for 12 volt systems. The basic pulse rate is set by the venerable 555 timer chip, U1, which switches the MOSFET Q1 at a 1 kHz rate. When Q1 is in the non-conducting state, current is drawn from the battery through L2 so that capacitor C4 can be charged slowly. Then Q1 is turned on for a brief 50 microseconds, causing the charge stored in C4 to start flowing through L1. When Q1 is turned off again, the stored inductive energy in L1 has to continue to flow somewhere, so it pulses back into the battery through diode D1. This current pulse can get as high as 6 amps. The use of an inductor to supply this pulse is what makes it possible to restore badly sulfated atteries with a high internal resistance. The peak voltage drop across the battery can initially be as high as 50 volts. With continued treatment, this peak voltage will decrease as the battery’s internal resistance gradually declines.

Figure 2 shows the version for use in 24 volt systems.

Its only additional feature is the use of a 79L12 voltage regulator (component U2, Digi-Key part number NJM79L12A-nd) to convert the 555’s input voltage down to 12 volts. Also L3 (Digi-Key part number DN4518-nd) is increased in value over L1 in the 12 volt unit, to compensate for the higher terminal voltage.

If an oscilloscope is available, it is easy to observe the ringing wave form across the battery terminals. It is likely that more than one frequency will be apparent, due to all the wiring and other details of the setup. It should be possible to see a small spark jump from the leads of the pulse generator as it is connected, a result of the high peak voltage available (keep this in mind ifyour batteries are not well ventilated). Depending on the case, and the type of inductors used for L1 and L2, a faint audio tone can also be heard when the circuit is operating. Digi-Key part number DN4516-nd will work for L1, and DN7437-nd will work for L2. There is no reverse olarity protection in this circuit, so make sure that the leads are clearly marked. A mistake will result in damaged components. Also, it is not a good idea to expose the 12 volt circuit to more han 16 volts at the terminals. See the parts table for a detailed component list. Butdon’t get too attached to using exactly these components, or to buying new stuff. The homebrewethic is based on an ability to make do, come up with alternatives, and recycle. My first trial units had quite a bit that was clipped out of old junk circuit boards.

UsageIt should be emphasized that pulsing energy to and from the battery happens at less than 100 percent efficiency. This circuit draws about 40 mA from the battery while in operation (less than 1 amp-hour per day), so some additional charging source is needed. For reconditioning a sulfated battery, I simply clip the circuit across the battery terminals in parallel with a 30 watt solar panel. In my initial testing, it took a month to partially reclaim a pair of golf cart batteries that had been allowed to sit, discharged, for almost a year. They had such a high internal resistance that a very small current would take the terminal voltage over 16 volts. For use in a functioning power system, you can clip the circuit across the main battery terminals, using as short a lead length as possible. When external equipment,such as an inverter, is connected across a battery bank, then additional low impedance paths are formed. The desulfator’s current pulses will appily flow down these paths as well, and it serves no purpose for the pulses to flow into the inverter.I had initially thought that this shunting, or dilution, of the current pulses away from the battery would be a problem. This has not proven to be the case, however, because the impedance of typical inverters at frequencies above 1 megahertz is not very low. (Note: impedance is just a fancy word for resistance, taking into account the circuit’s behavior at different frequencies.) One way to keep the external equipment from shunting away the current pulse would be to take some ferrite toroid cores and slip them over the battery leads as they leave the bank. This will increase the high frequency impedance without affecting the DC performance of the circuitry. The circuit as shown, with its approximately 6 amp peak capacity, is probably strong enough to maintain a bank of several hundred amp-hours. If you want to use the circuit with larger banks, it will be necessary to select D1, L1, and L2 for higher current capacity. You will also need to vary the pulse width from the 555 accordingly, so that Q1 is allowed to stay on for a longer period of each cycle. If you want to power the circuit from an auxiliary voltage source, so that the battery being treated remains trickle charged, simply remove R3 and place 12 volts across C1. It’s best to construct the unit in a shielded case. Otherwise it is likely to generate a fair bit of radio interference. The use of the shortest possible lead length is also a good idea. All the components are available from any general electronics distributor. Radio Shack is as good a place as any for getting the case, clip leads, circuit board, and other components.Does It Work?If badly sulfated batteries are treated, it is convenient to use a trickle charger of one or two amps. In this case, the simplest way to see that the circuit is having an effect is to note that the terminal voltage actually drops each day as the batteries slowly charge. This is a resultof the internal resistance of the cells decreasing as the plates become slowly cleared of the sulfate, and more useful plate area comes in contact with the electrolyte. Also, the specific gravity of the cells begins to rise slowly, evidence that the sulfate is going back intosolution. To further check the progress, you could do a discharge test, using a known load, to determine the useful capacity. This would involve measuring the length of time taken by the load to drop the battery voltage from a high level to a low level. If you repeat this test, a gradual lengthening of this interval should be noted. In one system I worked with, at first the batteries would not power even a small load. After treatment, they were able to run loads in the neighborhood of 5–10 amps for a few hours. This is far from “like new” condition, but it was sufficient for them to be returned to use in the small PV system they were taken from. I expect hat further treatment would have helped. It seems that the process is inherently slow. Lead sulfate is just not very willing to return into solution. Healthy Batteries I have used this circuit in my main system for over a year, and have not seen the need to equalize in that time (I do not own a generator). All of the cells’ electrolyte levels remain in step with each other, and there has been no problem with starting big loads—asure sign of battery health. Patience is required inreclaiming weak and tired batteries, and no amount ofdesulfating will help a battery with a shorted cell, or one that has lost plate material through excessive use. The device is especially useful for automotive batteries that sit for long periods. If you use a generator for equalization, this technique is a must. When you live off-grid, silence is golden.AccessAuthor: Alastair Couper, Kaupo, Maui, HI 96713kalepa@shaka.com

วันพุธที่ 1 กรกฎาคม พ.ศ. 2552

1 INTRODUCTIONThis report is intended to give an overview of the current status of the VHDL IEEEStandard 1076. The objective of this document is not to provide an overview of VHDL. Theobjective is to help positioning the existing VHDL standards as well as the ongoingstandardization activities. The report also highlights important European VHDL activities.Chapter 1 is this introduction.Chapter 2 lists existing standards and standardization activities. For each activity, ithighlights the objectives, current status and future plans.Quite some organizations are working on VHDL standardization or other VHDLpromoting activities. To help understand the positioning and the goals of theseorganizations, Chapter 3 contains a list of these organizations.Chapter 4 provides some details on European VHDL related tool efforts.Chapter 5 gives a few examples of European companies using VHDL. The chapter alsolists European R&D programmes related to VHDL.Chapter 6 lists some conclusions.All practical information available has been gathered into Chapter 7. This includeselectronic repositories (which ones and how to access them) and an extensive list ofcontacts within companies and organizations, plus various other information.

2 STATUS OF THE VHDL STANDARD2.1 VHDL IEEE Std 1076-1987The VHDL language was an offshoot of the VHSIC (Very High-Speed IC) program, fundedby the U.S. Department of Defense (DoD), and was first proposed in 1981. Thedevelopment of VHDL was carried out by IBM, Texas Instruments, and Intermetrics,starting two years later in 1983. In August 1985, version 7.2 of the language was releasedfor public review.Besides gaining the advantages of a hardware description language, the VHDL developerssought to unify the designs of all the VHSIC contractors and subcontractors into a singlelanguage. VHDL would allow anyone working on the program to define circuits andmodels independently of design tools and independently, too, of technology or vendor ofthe end product. Thus, a circuit could be designed and archived in VHDL, and laterfabricated with the most advanced technology.In principle, functional parts of a design could be reused in different applications anddifferent technologies without repeating valuable design work. These benefits wereespecially attractive to the DoD, which is often faced with obtaining equipment and spareparts for decades from multiple suppliers through multiple generations of newtechnologies. VHDL ultimately was included in Military Standard 454, and is arequirement for all DoD projects.In March of 1986, the IEEE took on the effort of standardizing VHDL. The VHDL Analysisand Standardization Group (VASG) was set up to review the language, with the goal ofrepairing known problems with the language and modifying the language where a broadconsensus formed around the modifications. The Air Force fully supported this work byawarding a contract to Intermetrics to develop the support software for the new languagestandard, now known as IEEE Std 1076.VHDL has been compared to ADA and many of the goals are the same as for the ADAlanguage. VHDL evolution however has differed from ADA and as a result is establishingitself as an industry standard language more rapidly. From the inception of the VHDLprogram, the DoD acknowledged the weaknesses in the ADA standardization approachand took steps which have resulted in a strong language. VHDL has benefited fromsubstantial industry review and participation throughout its development.When in March 1986 all rights to the VHDL language were transferred to the IEEE, theoriginal version 7.2 language went through a phase of substantial changes driven primarilyby industry representation from CAE vendors as well as users. The goals of the IEEE indeveloping a standard language were broader in scope. Driven by the need for aproduction quality language suitable as a design tool to be used throughout the designcycle, the IEEE enhanced the language substantially.This effort resulted in the creation of a world-class hardware description language whichwas ratified in December 1987 as the first industry standard hardware descriptionlanguage with overwhelming support from industry. One important reason for the strongsupport VHDL has received throughout industry is that unlike ADA, there are no otherstandard languages which VHDL must compete against. Recently, however, the IEEEstandardization of the Verilog Hardware Description Language has started.

2.2 VHDL IEEE Std 1076-1993Since its emergence as an IEEE standard, VHDL has been quite a success story. Despite thefact that VHDL was created from scratch, more and more companies signal that they areentering the VHDL marketplace or that they are expanding their current offerings. VHDLhas established itself as the premier hardware description language.The IEEE is very determined that standards be used by their communities. Therefore, itis an official IEEE requirement that all standards be reaffirmed at least every 5 years. Thisreaffirmation may be anything from reaffirmation simpliciter to a radical change. Theimportant point is that a group of experts and users within the standard’s designatedcommunity must care enough about the standard to keep it alive.For VHDL, the 5 year reaffirmation IEEE requirement means that the language had to bereballoted during 1992. Therefore, the VHDL Analysis and Standardization Group (VASG)began planning the eventual reballoting in June of 1990.The first decision made was to disallow radical changes to VHDL during thisrestandardization period. The language had great forward momentum in the marketplace,and radically altering it —even for sound technical reasons— could have a devastatingimpact to that momentum. Second, for much the same reason, it was decided to make thenew version of VHDL as upward compatible as possible. Finally, it was decided to allowchange requests to come from the users.In December 1992, the VHDL ballot successfully passed the IEEE requirements for the firsttime. Then, the resolution process for the comments received during this first ballot started.The team in charge to answer these comments changed the Language Reference Manual,so there had to be a second ballot.

The second ballot was held in May 1993. The ballot results were positive: 155 affirmative,40 negative and 14 abstention votes. This reflects a return rate of 85.6% and an approvalrate of 79%. The standard was then formally approved at the September 1993 meeting ofthe IEEE Standards Board’s Review Committee.The IEEE Std 1076-1993 was published during the first quarter of 1994. The new LanguageReference Manual (LRM) is self-sufficient, which means that the "old" LRM has becomeobsolete. The new LRM includes an appendix identifying portability issues.During the restandardization process, several working groups were formed. The followingworking groups submitted a PAR (a PAR is a Project Authorization Request, which givesa group a formal status as a working group moving towards a standard) to the IEEE NewStandards Committee, and were approved:1076a Shared Variables - amendment to IEEE 1076-19931076.1 Analog Extensions to VHDL1076.2 Standard Mathematical Package1076.3 Standard Synthesis Package1076.4 VHDL Timing and Back Annotation1076.5 Utility LibrariesRecently (April 1994) a new DASC Test Study Group is being formed.Another PAR which was approved, is the standardization of the Verilog HDL (PAR 1364).As only the VHDL Hardware Description Language is within the scope of this report, wedid not include any further information on this PAR. However, we mention it forcompleteness.Section 2.3, titled Extensions of VHDL, gives information on PAR 1076a and PAR 1076.1.Section 2.4, titled Definition of Standard Practices, gives information on PAR 1076.2, PAR1076.3, PAR 1076.4, PAR 1076.5 and the Test Study Group. As the IEEE StandardMultivalue Logic System for VHDL Model Interoperability (IEEE Std 1164-1993) and theIEEE Waveform and Vector Exchange Specification (IEEE Std 1029.1-1991) also define"Standard Practices", there are subsections giving information on this standard.First, we have another subsection on VHDL ’93, highlighting some reflections onVHDL ’93.

2.2.1 Reflections on VHDL ’93The user requirements gathered during the restandardization process can be classified asfollows:bugs and repairs (e.g., textio, which was ill-defined),improvements (e.g., provide a no-change option for conditional signal assignments), andnew concepts (e.g., introduce analog modelling).An additional division can be made betweenrequirements regarding the language itself andrequirements regarding its use (e.g., provide a SIN function).Some of the requirements, mainly the synthesis-related ones, could be answered by thestandardization of ’standard’ packages, such as the std_logic_1164 package defining anine-state multi-value logic type and its associated resolution and logical functions (whichhas already been voted on) or the standard packages of Ada. Such packages could bewritten in pure VHDL and introduced as part of the standard or of sub-standards. Anexample of a VHDL application that became a standard is WAVES.Other requirements included changes in the definition of the language itself.Among all the requests from users for a VHDL ’93 standardization, the requirementsconcerning analog domain, and more precisely mixed-mode simulation, were mostnumerous: about one fifth of the total. Europeans are particularly interested in this field.In the very early stages of the standardization process, it became apparent that it wouldnot be possible, due to the very different levels of requests as well as to scheduling, foranalog extension to be included in VHDL ’93. However, because of the interest ofdesigners in this topic, a PAR (a Project Authorization Request) of VHDL has beenlaunched. The first draft of the Language Reference Manual is expected to be balloted bythe end of 1994.Thus, VHDL ’93 (like VHDL ’87) does not cover the analog domain. Nevertheless, it is easyto find many papers and even tutorials explaining how to model analog parts in VHDL’87. For limited purposes, this has been done with VHDL ’87 and, of course, is possiblewith VHDL ’93.Indeed, VHDL ’93 offers some new possibilities for this purpose. The main one is theintroduction of a foreign "mechanism" that allows foreign models to be interfaced. Thesemodels can potentially be described in an analog modelling language. This is not a "pure"VHDL solution, and the interface is described so briefly that problems of portability anddependency on tool vendors are inevitable. Nevertheless, this interface does exist, whichis an important advantage.For people in search of a "pure" VHDL solution, one of the main problems is to identifythe "steady states" of the digital world during which the analog kernel may execute. Lastdeltaactivation processes should solve this. It is also possible to imagine calling foreignsubprograms from these processes to activate an external analog kernel.Analog modelling very often depends on parameters that can vary dynamically duringsimulation. One example of this is temperature. The dynamic characteristics of suchparameters cannot be represented by the use of generic parameters. Their representationas global signals or specific ports is definitely not satisfying. Shared variables, which arein fact global variables, have been introduced into VHDL ’93 and could be used for thispurpose.

2.3 Extensions to VHDL2.3.1 Analog VHDL (VHDL-A) Working GroupName : Analog Extensions to VHDL WG (VHDL-A)PAR : 1076.1Chair : Jean-Michel BergéContact list : see section 7.5Information : see section 7.5 for details on how to get more informationObjectivesThe purpose of the VHDL-A working group is to develop analog extensions to VHDL,i.e. to enhance VHDL such that it can support the description and simulation of circuitsthat exhibit continuous behaviour over time and over amplitude.VHDL-A must be suitable for the description and simulation of digital, analog, andmixed digital/analog systems. VHDL-A must be able to support any designmethodology and be technology independent.Technology independence means that components of any technology (electrical,mechanical, thermal, optical, fluid,...) must be supported, for example the attitude andorbit of a satellite.Mixed analog/digital simulations are a very important usage of VHDL-A, for examplemixed analog/digital simulation of an ASIC as well as mixed simulation of a mechanicalsystem (such as attitude and orbit of a satellite), together with a digital system (such asthe digital implementation of the satellite control system).The analog part of VHDL-A should be targeted primarily towards the followingapplications:- DC and transient analysis,- electronic circuits (OpAmps, PLLs, comparators,...),- lumped element systems (meaning that microwaves cannot be handled).The other domains (mechanical, thermal,...) could be easily introduced as they areanalogous to the electrical domain.Using VHDL-A, it should be possible to describe the structural composition of analogsubcircuits connected by analog wires. Analog components could embody SPICE netlistssince the analog simulator should understand this de facto standard description.Using VHDL-A, it should be possible to describe the behaviour of analog circuits. Twostyles should be provided: relations or equations, and procedural models. These twostyles will form the "core" of the analog part of VHDL-A.Activities completedThe Design Objectives Document is completed and is available via anonymous ftp fromthe VHDL-A repository mentioned in section 7.5.Activities plannedLanguage design phase, documentation and validation phases are going on Goal: the LRM(Language Reference Manual draft #1) will be ready for balloting by the end of 1994.Responses from the first ballot should be received and ready for analysis by March 1995.Further steps are to respond to all balloting responses, determine the result of the ballot,modify documents as required, and resubmit for balloting. Most probably, there will beat least two ballots. The earliest that balloting could be complete is August 1995. Thisschedule is rather ambitious. As more information is gathered and work progresses, theWork Group will reschedule the activities.Relationship with other Working Group / StandardsThrough DASC meetings.It has been decided that VHDL-A will be an extension of the current VHDL and not asupplement: i.e. the ballot only concerns analog extension (and not the entire language)and the result (if positive) will consist in two standards. The previous STD 1076 remainsthe same and the analog standard is created and refers to it.2.3.2 Shared Variables Working GroupName : Shared Variables WG (SVWG)PAR : 1076aChair : Stephen BaileyContact list : see section 7.5Information : see section 7.1 for details on how to get more informationObjectivesShared Variables received the largest percentage of negative votes and/or comments inballoting for VHDL 1076-1993. The working group was formed with the charter ofproposing an amendment to VHDL 1076-1993 (1076a) that would re-design the languageimplementation of shared variables in order to address as many as possible of the concernsthat balloters of 1076-1993 have as possible.Activities completedThe work is currently in the requirements phase. Requirements have been collected andshortly the voting on each requirement’s relative importance will start (some requirementsare in conflict with others). The final requirements document was planned to be completeby the end of February 1994.A technical writer, LRM editor and technical review committees have been formed. Arequirements committee is completing the requirements work.Activities plannedOnce the relative importance of each requirement has been established, the technicalcommittee and writer will begin work on a language re-design proposal. Languagechanges will be limited to areas related to shared variables.The proposal will be submitted to the technical review committee and re-worked asrequired by the committee’s feedback. Finally, the proposal will be submitted for a voteof the voting membership of the SVWG. If approved, the proposal will be given to theLRM editor who will integrate the changes with the LRM. The revised LRM will bereviewed and then submitted to the IEEE for balloting.Relationship with other Working Groups / StandardsAmendment to IEEE 1076-1993.The OO-VHDL study group will be monitoring the shared variables progress since onepossible approach (monitors) is object-oriented.2.4 Definition of Standard Practices2.4.1 Mathematical Package Working GroupName : VHDL Mathematical Package WGPAR : 1076.2Chair : Jose A. TorresContact list : see section 7.5Information : see section 7.1 for details on how to get more informationObjectivesDevelop a set of standard VHDL mathematical packages that include:most often used real and complex elementary functions, andthe required data types and type conversion functions.Activities completedStrawman proposal for a math real and complex package is done (includes packagedefinition and body).- Real functions include common real constants, common real functions and realtranscendental functions.Work is in progress to put together a test bench.- The NBS FORTRAN tests of math functions will be reused (15/10/93)- The WG is checking with Mentor Graphics if the tests for their math package can beused as a basis for the test bench (15/10/93).- The Vantage test bench template can be used as a basis for the test bench (15/10/93).- Some funding is available from Synopsys to develop a prototype of the test bench forthe math package (15/10/93).Electronic form of the package is available on request.Activities plannedFinish test bench,Verify proposed functions,Incorporate suggested changes, andBallot the package.Currently, they are looking at June-July 1994 to start balloting the packages.Relationship with other Working Groups / StandardsThis standard is meant to be compliant with VHDL Standard 1076.The VHDL Analog Extensions WG will submit analog requirements to the Math WG.No requirements were received by 25/11/93.The minutes of the 15/10/93 Math WG meeting mention the following: "There is stillthe issue about the need for double precision functions and the possibility that a newreal type called FLOAT may be part of the VHDL-A effort. This type will require greateraccuracy than the current REAL type. The current proposed solution for thisrequirement is to develop two math packages: one for each real type.One consequence of such a decision is that we could ballot the REAL based mathpackage almost immediately and could ballot the FLOAT package at the same time thatanalog is balloted."The COMPLEX package is intended to support analog needs, complex numbers shouldprobably be based on FLOATS.