To improve speed and noise immunity, VCC and GND side pins are used. The 74F712A/74F712-1 consist of five 3-to1 multiplexers designed for address multiplexing of dynamic RAMs and other multiplexing applications. The 74F712A has two select (S0, S1) inputs to determine which set of five inputs will be propagated to the five outputs. The outputs source 15mA and sink 64mA. The 74F712-1 is the same as the 74F712A except that it has a 30W termination impedance on each output to reduce line noise and the outputs sink 5mA. TYPICAL SUPPLY CURRENT (TOTAL) 29mA 25mA

Consists of five 2-to-1 Multiplexers High impedance PNP base inputs for reduced loading

Consists of five 3-to-1 Multiplexers High impedance PNP base inputs for reduced loading

Designed for address multiplexing of dynamic RAM and other 30W termination impedance on each output ­ 74F712-1 Outputs sink 64mA (74F712A only)

DESCRIPTION

The 74F711A/74F711-1 consist of five 2-to-1 multiplexers designed for address multiplexing of dynamic RAMs and other multiplexing applications. The 74F711A has a common select (S) input, an Output Enable (OE) input and an Output Inverting (INV) input to control the 3-State outputs. The outputs source 15mA and sink 64mA. The 74F711-1 is the same as the 74F711A except that is has a 30W termination impedance on each output to reduce line noise and the 3-State outputs sink 5mA. When the inverting input (INV) is Low, the input data path is inverted.

HD74HC365 : Buffers. Hex Bus Drivers With 3-state Outputs. Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips.

MC100E171FN : Multiplexers. 5V Ecl 3-Bit 4:1 Multiplexer , Package: Plcc, Pins=28. The MC10E/100E171 contains three 4:1 multiplexers with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs (see logic symbol). The three Select inputs control which one of the four data inputs in each case is propagated to the corresponding output. The 100 Series contains temperature compensation. 725 ps Max. D to Output.

MC100E175FN : 5V Ecl 9-Bit Latch With Parity , Package: Plcc, Pins=28. The a 9-bit latch. It also a tenth latched output, ODDPAR, which is formed as the odd parity of the nine data inputs (ODDPAR is HIGH if an odd number of the inputs are HIGH). The E175 can also be used to generate byte parity by using D8 as the parity-type select (L = even parity, H = odd parity), and using ODDPAR as the byte parity output. The LEN pin latches.

SN54AS32 : . Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs These devices contain four independent 2-input positive-OR gates. They perform the Boolean functions or in positive logic. The SN54ALS32 and SN54AS32 are characterized for operation over the full military temperature.

SN74LS75D : ti SN74LS75, Quad Bistable Latches. PRODUCTION DATA information is current as of publication date. Products conform to s per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. .