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Digital system design practical file

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INDEX
S.NO DESCRIPTION
PAGE
1.
Write a program in VHDL to implement all logic gates
using data flow modeling.
2
2.
Write a program for the following circuits, check the
waveform and the hardware generated using behavioral
modeling: (a)Half Adder (b)Full Adder
16
3.
Write a program for the 4:1 multiplexer, check the
waveform and the hardware generated using behavioral
modeling.
34
4.
Write a program for the 1:4 demultiplexer, check the
waveform and the hardware generated using behavioral
modeling.
44
5.
Write a program for the 8:3 encoder, check the
waveform and the hardware generated using behavioral
modeling.
54
6.
Write a program for the 3:8 decoder, check the
waveform and the hardware generated using behavioral
modeling.
65
7.
Write a program to implement 1-bit comparator in VHDL
using behavioral modeling.
73
8.
Write a program in VHDL to implement up-down counter
using behavioral modeling.
80
9.
Write a program to implement Binary to Gray code
converter using behavioral modeling in VHDL
89
10.
Write a program for the D flip-flop, check the waveform
and the hardware generated using behavioral modeling.
95
SIGNATURE
NO.

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Program 1
Aim: Write a program in VHDL to implement all logic gates using data flow
modeling.
Apparatus:
Tool used: Xilinx 8.2i
PC specification: 1GB RAM, 320GB hard disk
Theory:
AND gate: The AND gate is an electronic circuit that gives a high output (1) only if all its inputs
are high. A dot (.) is used to show the AND operation i.e. A.B. Bear in mind that this dot is
sometimes omitted i.e. AB.
OR gate: The OR gate is an electronic circuit that gives a high output (1) if one or more of its
inputs are high. A plus (+) is used to show the OR operation.
NOT gate: The NOT gate is an electronic circuit that produces an inverted version of the input
at its output. It is also known as an inverter. If the input variable is A, the inverted output is
known as NOT A. This is also shown as A', or A with a bar over the top, as shown at the
outputs. The diagrams below show two ways that the NAND logic gate can be configured to
produce a NOT gate. It can also be done using NOR logic gates in the same way.
NAND gate: This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate.
The outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate
with a small circle on the output. The small circle represents inversion.
NOR gate: This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The
outputs of all NOR gates are low if any of the inputs are high. The symbol is an OR gate with a
small circle on the output. The small circle represents inversion.
XOR gate: The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not
both, of its two inputs are high. An encircled plus sign ( ) is used to show the EOR operation.
XNOR gate: The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a
low output if either, but not both, of its two inputs are high. The symbol is an EXOR gate with a
small circle on the output. The small circle represents inversion.

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Program 2
Aim: To write a program for the following circuits, check the waveform and
the hardware generated using behavioral modeling.
(a)Half adder
(b)Full adder
Apparatus:
Tool used: Xilinx 8.2i
PC specification: 1GB RAM, 320GB hard disk
(A) HALF ADDER
Theory: The half adder adds two single binary digits A and B. It has two outputs, sum (S) and
carry (C). The carry signal represents an overflow into the next digit of a multi-digit addition.
The value of the sum is 2C + S. The simplest half-adder design, incorporates an XOR
gate for S and an AND gate for C. With the addition of an OR gate to combine their carry
outputs, two half adders can be combined to make a full adder.

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(B) FULL ADDER
Theory: A full adder adds binary numbers and accounts for values carried in as well as out. A
one-bit full adder adds three one-bit numbers, often written as A, B, and Cin; A and B are the
operands, and Cin is a bit carried in from the next less significant stage.[2]
The full-adder is
usually a component in a cascade of adders, which add 8, 16, 32, etc. binary numbers. The circuit
produces a two-bit output, output carry and sum typically represented by the signals Cout and S,
where .
VHDL code for implementing full adder using behavioral modeling:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity full_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
carry : out STD_LOGIC);
end full_adder;
architecture Behavioral of full_adder is

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Program 3
Aim: To write a program for the 4:1 multiplexer, check the waveform and the
hardware generated using behavioral modeling.
Apparatus:
Tool used: Xilinx 8.2i
PC specification: 1GB RAM, 320GB hard disk
Theory: In electronics, a multiplexer (or mux) is a device that selects one of several
analog or digital input signals and forwards the selected input into a single line. A multiplexer of
2n
inputs has n select lines, which are used to select which input line to send to the
output. Multiplexers are mainly used to increase the amount of data that can be sent over
the network within a certain amount of time and bandwidth. A multiplexer is also called a data
selector. An electronic multiplexer makes it possible for several signals to share one device or
resource, for example one A/D converter or one communication line, instead of having one
device per input signal.
4:1 multiplexer

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Program 4
Aim: To write a program for the 1:4 demultiplexer, check the waveform and
the hardware generated using behavioral modeling.
Apparatus:
Tool used: Xilinx 8.2i
PC specification: 1GB RAM, 320GB hard disk
Theory: A demultiplexer (or demux) is a device taking a single input signal and selecting one
of many data-output-lines, which is connected to the single input. A multiplexer is often used
with a complementary demultiplexer on the receiving end. Demultiplexers take one data input
and a number of selection inputs, and they have several outputs. They forward the data input to
one of the outputs depending on the values of the selection inputs. Demultiplexers are sometimes
convenient for designing general purpose logic, because if the demultiplexer's input is always
true, the demultiplexer acts as a decoder. This means that any function of the selection bits can
be constructed by logically OR-ing the correct set of outputs.
1:4 demultiplexer

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Program 5
Aim: To write a program for the 8:3 encoder, check the waveform and the
hardware generated using behavioral modeling.
Apparatus:
Tool used: Xilinx 8.2i
PC specification: 1GB RAM, 320GB hard disk
Theory: An encoder is a device, circuit, transducer, software program, algorithm or person that
converts information from one format or code to another. The purpose of encoder is
standardization, speed, secrecy, security, or saving space by shrinking size. Encoders are
combinational logic circuits and they are exactly opposite of decoders. They accept one or more
inputs and generate a multibit output code.
Encoders perform exactly reverse operation than decoder. An encoder has M input and N output
lines. Out of M input lines only one is activated at a time and produces equivalent code on output
N lines. If a device output code has fewer bits than the input code has, the device is usually
called an encoder.
Truth table for 8:3 encoder:-

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Program 6
Aim: To write a program for the 3:8 decoder, check the waveform and the
hardware generated using behavioral modeling.
Apparatus:
Tool used: Xilinx 8.2i
PC specification: 1GB RAM, 320GB hard disk
Theory: In digital electronics, a decoder can take the form of a multiple-input, multiple-output
logic circuit that converts coded inputs into coded outputs, where the input and output codes are
different e.g. n-to-2n , binary-coded decimal decoders. Decoding is necessary in applications
such as data multiplexing, 7 segment display and memory address decoding.
3:8 decoder uses all AND gates, and therefore, the outputs are active- high. For active- low
outputs, NAND gates are used. It has 3 input lines and 8 output lines. It is also called as binary to
octal decoder it takes a 3-bit binary input code and activates one of the 8(octal) outputs
corresponding to that code. The truth table is as follows:
Truth Table of 3:8 decoder

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Program 7
Aim: Write a program to implement 1-bit comparator in VHDL using
behavioral modeling.
Apparatus:
Tool used: Xilinx 8.2i
PC specification: 1GB RAM, 320GB hard disk
Theory:
A digital comparator or magnitude comparator is a hardware electronic device that takes two
numbers as input in binary form and determines whether one number is greater than, less than or
equal to the other number. Comparators are used in central processing units (CPUs)
and microcontrollers (MCUs).
The operation of a single bit digital comparator can be expressed as a truth table:

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Program 8
Aim: Write a program in VHDL to implement up-down counter using
behavioral modeling.
Apparatus:
Tool used: Xilinx 8.2i
PC specification: 1GB RAM, 320GB hard disk
Theory: The similarities between the implementation of a binary up counter and a binary down
counter leads to the possibility of a binary up/down counter, which is a binary up counter and a
binary down counter combined into one. Since the difference is only in which output of the flip-
flop to use, the normal output or the inverted one, we use two AND gates for each flip-flop to
"choose" which of the output to use.
From the diagram, we can see that COUNT-UP and COUNT-DOWN are used as control inputs
to determine whether the normal flip-flop outputs or the inverted ones are fed into the J-K inputs
of the following flip-flops. If neither is at logic level 1, the counter doesn't count and if both are
at logic level 1, all the bits of the counter toggle at every clock pulse. The OR gate allows either
of the two outputs which have been enabled to be fed into the next flip-flop. As with the binary
up and binary down counter, the speed up techniques apply.
3-Bit Synchronous Up-Down Counter

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for i in 0 to 2 loop
cout:=(a(i) and b(i)) or (b(i) and cin) or (a(i) and cin);
sum(i):=a(i) xor b(i) xor cin;
cin:= cout;
end loop;
return sum;
end"+";
begin
process(clk,pr,clr)
begin
if(pr='0' and clr='1') then
q<="111";
elsif (pr='1' and clr='0') then
q<="000";
elsif(pr='1' and clr='1' and clk='0' and clk' event) then
q<=q+ "100";
end if;
end process;
end Behavioral;

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Program 9
Aim: Write a program to implement Binary to Gray code converter using
behavioral modeling in VHDL
Apparatus:
Tool used: Xilinx 8.2i
PC specification: 1GB RAM, 320GB hard disk
Theory:
A Binary code is a way of representing text or computer processor instructions by the use of the
binary number system's two-binary digits 0 and 1. This is accomplished by assigning a bit string
to each particular symbol or instruction. For example, a binary string of eight binary digits (bits)
can represent any of 256 possible values and can therefore correspond to a variety of different
symbols, letters or instructions.
Gray code is a type of unit distance code. In unit distance code the bit patterns for two
consecutive numbers will differ in one bit position. We can also say it as Cyclic codes.
Binary to Gray Code Conversion
Follow the below Steps to convert Binary number to gray code. The steps are displayed here.
Lets Consider The Binary number B1 B2 B3 B4 ... Bn and the Gray code is G1 G2 G3 G4 ... Gn
1. Most significant bit (B1) is same as the most significant bit in Gray Code (B1 = G1)
2. To find next bit perform Ex-OR (Exclusive OR) between the Current binary bit and
previous bit. The formula for this conversion is shown below. This is as follows:
Gn = Bn (Ex-OR) Bn-1
3. Look the below Image for Binary to Gray code Conversion

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Program 10
Aim: To write a program for the D flip-flop, check the waveform and the
hardware generated using behavioral modeling.
Apparatus:
Tool used: Xilinx 8.2i
PC specification: 1GB RAM, 320GB hard disk
Theory: The D flip flop characteristic table has 3 columns. The first column is the value of D,
a control input. The second column is the current state that is the current value being output by
Q. The third column is the next state, that is, the value of Q at the next positive edge. It's labeled
with Q and the superscript, + (the plus sign). Sometimes, the current state is written as Q(t)
which means the value of Q at the current time, t, and the next state is written as Q(t + 1) which
means the value of Q at the next clock edge. However, I'll usually write it as Q+
.
The characteristic table is unusual, because the second column isn't really an input, it's an output.
The third column is really the same output, but just the output at a future time. The D flip flop
has two possible values. When D = 0, the flip flop does a reset. A reset means that the output, Q
is set to 0. When D = 1, the flip flop does a set, which means the output Q is set to 1. This is
how you can picture the flip flop working. When the clock is not at a positive edge, the flip flop
ignores D. However, at the positive edge, it reads in the value, D, and based on D, it updates the
value of Q (and of course, Q'). There is some small amount of delay while it reads in the control
input (from D) and the output. In fact, the "D" in D flip flop stands for "delay". It basically
means that the "D" value is not read immediately, but only at the next positive clock edge.