BUFT is a 3-state buffer with input I, output O, and active-Low
output enable (T). When T is Low, data on the input of the buffer is
transferred to the output. When T is High, the output is high
impedance (Z state or off). The outputs of the buffers are connected
to horizontal longlines in FPGA architectures.
The outputs of separate BUFT symbols can be tied together to form a
bus or a multiplexer. Make sure that only one T is Low at one time. If
none of the T inputs is active (Low), a 'weak-keeper' circuit (FPGAs)
prevents the output bus from floating but does not guarantee that the
bus remains at the last value driven onto it.
Pull-up resistors can be used to establish a High logic level if all
BUFT elements are off XC4000. For Virtex and Spartan2, when all BUFTs
on a net are disabled, the net is High.

cellInterfaceDeterminesUniqueNetlistStructure()
When false, the default behavior of this method, each cell will list itself
separately in a netlist, guaranteeing that the netlist will not have invalid
data at the expense of a larger file-size.

buft

Constructs a new buft, connecting its ports as given by the String-Wire pairs in the ArgBlockList. Any generic assignments are made through String-String pairs in the ArgBlockList.
The initial String parameter is the instance name.

Parameters:

parent - The parent Cell to the buft

instanceName - The instance name of the buft

abl - The list of String-Wire pairs for port assignments, and String-String pairs for generic assignments.

Method Detail

getCellName

Access the cell name associated with a derived class. The cellname field is lazily evaluated
on the first call of this method. Can be overriden to make cellname different by instance.
If the field does not exist, this defaults to the classname.

cellInterfaceDeterminesUniqueNetlistStructure

When false, the default behavior of this method, each cell will list itself
separately in a netlist, guaranteeing that the netlist will not have invalid
data at the expense of a larger file-size. Overriding this method to return true
allows JHDL to save memory and netlists to be smaller by sharing the netlist
structures that are guaranteed to be identical.
NOTE: Do not override this unless every possible condition responsible for structural
differences in a class (types and amount of children cells created, and arrangements
of wires connected to ports) is included in the cellInterface[] of that class.