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To enable Electrostatic Discharge (ESD) sign-off in a timely manner, both quantifying the number of checks and improving tool throughput for ESD simulations becomes necessary. Static ESD checks are critical to ensure reliability for System-on-Chip level ESD sign-off, and can typically involve 1,000+ simulations. In this paper, we have presented metrics for quantifying design size that can be used as a metric in gauging required machine resources and projecting subsequent runtimes based on existing data for different designs, reducing simulation iterations and ultimately impacting time-to-market. Our results have shown up to 7X improvement in total runtime using twelve machines.