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An FPGA can be a useful "swiss army knife", but all the nice features aren't easily accessible.
Enter "LabToy": A batteries-included collection of utilities, just double-click and go.
As the name implies, this isn't meant to compete against "real" test equipment. The main selling point is like a pocket knife - this fits into a shirt pocket and the power tools don't. And speaking of "selling points", it's free to use.
So what do we have here:
- Digital data: Shows the input state of all pins
- Analog data: Readings from the two ADCs, up to about 700 ksps sustained (XADC "simultaneous sampling" mode, phase-accurate between channels)
- Streaming data logger: Both analog and digital data can be written to a .vcd file, to be shown in gtkwave. There is no limit to the capture length. - Analog signal generator: 8 fully independent channels, sine, square wave, the usual suspects. Well, the DACs won't win any audiophile awards, but they are usable.
- "Programmable" digital LED mode: Configurable pulse width to suppress short glitches, or edge detect with a built-in pulse generator to highlight them.
- Analog LED mode: Shows the input value of the ADC in real time
Some screenshots: 1k sine / cosine from DAC jumpered to ADC (in gtkwave)
The digital signal is the generator's sync output that can be recorded as a digital input.
Realtime display of the inputs. With pocket knives in mind ("this button will unlock the large blade, allowing it to be manually returned to its folded position") I decided to keep the screen uncluttered and put descriptions into tooltips.
The large displays are the average voltage readings from the ADC. The smaller ones show the digital inputs in groups of four.
Generator controls (frequency, minimum voltage, maximum voltage, phase). The voltage scaling is a bit unusual (typically there is "AC magnitude" and "DC offset") but I chose this approach because it shows clearly the limitations of the 0..3.3V output range.
Most people will probably leave all this at the default values for a full-scale signal.
Data capture
Example: The output in gtkwave after I touched a jumper cable to the digital inputs on the DIL connector. +++ DO NOT USE THE +5V OUTPUT P24 FOR THIS KIND OF TEST +++ (3.3 V is available on the PMOD connector, bottom row)
The red "undefined" marks flag the first input in an 8-bit group. In this example, they aren't too meaningful, but they can alert me to the fact that no data events have been observed yet.
LED control
The two numbers give the number of consecutive 1 or 0 samples (at 125 MHz) before a signal change is propagated to the LED.
E.g. put 125 million there and it'll take one second after changing the input state for the LED to light / go dark.
Those can be used interactively to study an unknown signal.
"Level": no further processing ("level" mode and 1 / 1 sample counts is equivalent to directly connecting the LED to the physical input)
"Edge" mode generates a brief pulse on signal changes, the LED is dark otherwise.
"Invert" flips the input right next to the pin (0 becomes 1, black becomes white and man gets himself killed on the next zebra crossing -DA).
How to get it:
The file is attached: labToy0v1_beta.exe
The installer unpacks a single .exe.
Happy hacking!
Requirements:
Windows 64 bit (!)
.NET 4.5
FTDI libraries
CMOD A7 35 T (not 15 T).
Warnings:
Direct access to digital IO pins is an inherently dangerous activity.
"PROVIDED WITHOUT WARRANTY OF ANY KIND" means Just That.
And beware of the +5V pin.
PS:
If you try it, kindly let me know whether it works, or what goes wrong.

A few reasons are...
a - The introduction of logic hazards can cause glitches : https://en.wikipedia.org/wiki/Hazard_(logic)
b - Routing of clocks is very complex - It is hard to ensure that the same clock edge appears all over the FPGA at almost exactly the same time. Sometimes this is achieved with 'slight of hand' (e.g. using a on-chip PLL to advance phase of the clock, so that by the time it reaches the edge of the chip is in back phase with the original signal). Low-skew paths also exist, but are restricted to small areas of the FPGA, and the clock has to be connected to the correct pin to be placed and routed correctly.
c - FPGAs and their tools are designed to behave predictably under the "synchronous digital design" paradigm (something like https://hps.hs-regensburg.de/scm39115/homepage/education/courses/red/2_SynchronousDigitalCircuitDesignRules.pdf). If you work outside the paradigm you will be fighting against the tools and their assumptions.
d - There is almost nothing that you are unable to code in an FPGA friendly way, but there are infinitely many ways to write FPGA-hostile code. If you want your FPGA to place nice with you, you have to play nice with it.
So you can either add an RC filter to debounce you switch, or you can sample it using a reliable clock.

Hello everybody!
Since I was sharing this image with others, I thought I'd share it here at Digilent as well. The attached image shows the frequency response of several FFT windows, including the well-known rectangle and Hanning windows. The blue window is one I've put together, but haven't shared the FPGA source code used to implement it.
I challenge anyone to do better.
Oh, and one other comment ... all but the Hanning window can be used in an invertible FFT process.
Dan

Hi @Blake,
I was struggling with the same problem.
In Adam's project is mistake which result is an FMC-HDMI module is not recognizable by other devices.
The reason for that is not sending EDID at all.
The cause of this situation is wrong initialized EDID map.
In Adams example EDID is initialized by:
but the correct way is:
the body of iic_write2 is from LK example:
By the way, in LucasKandle example initialization is done in same way as in Adam's example so is the reason why it not worked in your case.
I hope it will helps. If you want I will post my working code for a ZedBoard with FMC-HDMI when I clean it because at the moment is kind of messy.

It seems to me the AXI Quad SPI block is sending address + data. Looking at the .xci file again, I see C_SPI_MEM_ADDR_BITS set to 24 bits. So 24 bits of address and 16 bits of data would yield 40 bits.

The warning you pasted is benign and simply means there are no ILAs present in your design.
The real issue could be your clock. You should review the datasheet for the dvi2rgb.Table 1 in section 5 specifies RefClk is supposed to be 200Mhz. Also, your constraint should follow the recommendation in section 6.1 for a 720p design.
Finally, @elodg gives some great troubleshooting information in this thread.

Hi @D@n,
I believe the new part that is used in the Arty A7 boards (and other A7 boards) is now a Spansion S25FL128SAGMF100; based on old schematics, I believe this was added in Rev D of the Arty A7 (dated August 2017), though I do not know when that particular Rev was then released (or if it even was released) to the public. I confirmed that the Arty S7 also uses this part and I wouldn't be surprised if most of our other Artix 7 based boards use it now as well.
I've requested that the chip name and images are updated in any appropriate tutorials and requested that the pdf version of the reference manual (updated wiki) is updated as well.
Thanks,
JColvin

@hamster I was able to run your AXI Slave interface. It works great!
It is now very easy to exchange information between PS and PL, and it even supports execute-in-place (e.g. I can put ARM instructions to register file and run PS CPU directly from it).
I have some questions about your AXI Slave design:
1) AXI_a*size has no effect on INCR type of burst transactions, but according to AXI protocol: the increment value depends on the size of the transfer. You set it only for WRAP type, is it correct? Thus, burst size is always 0 for INCR type?
2) Do you know how PS initiates INCR burst type? A kind of memset/memcpy need to be used for that or an incrementing pointer will also work?
3) Where WRAP type is necessary? How to use PS to work in WRAP mode?
You may also update your wiki page with following:
0) Create provided VHDL files
1) Create a block-diagram and add PS IP core to it
2) Apply configuration provided by your board's pre-settings; this will set all necessary initialization settings for PS (e.g. clock frequencies, DDR bindings, etc.)
3) Press auto-configure (or how it's called) ==> this will connect PS IP to DDR and to fixed IO
4) Add "External ports" to the diagram (create new AXI_CLK and AXI external ports) and connect them to PS ports
5) Generate VHDL wrapping code for this block diagram
6) Put generated system under axi_test_top by renaming it to axi_test_wrapper (default name is design_#_wrapper in my Vivado version)
7) This will auto-connect block-diagram external ports with axi_test_top
8 ) Add constrains file and rename/uncomment external ports where necessary
9) Generate bitstream
10) File->Export->Hardware and create .hwf file which contains PS configuration
11) Open Xilinx SDK and create a new project: select .hwf file as Hardware BSP for this project
12) Now, Xilinx SDK will auto-generate few .c and .h files which contain necessary PS initialization ==> clocks, IRQs, DDR, etc.
13) Add hello_world.c application to the project
@hamster Thank you very much. I've learned a bunch of new things thanks to your help!

Hi @Mahesh,
As @jpeyron said in the post marked as accepted solution, the Zynq processing system will be configured with the board presets when you first add the Zynq processing system IP core to the block design and run the block automation task from the green message that appears! Just remember to keep the Apply Board Preset option checked as shown in he picture. So this means if you are using the pre-built block design from the example project, a possible solution can be to remove the existing Zynq processing system block and adding a new one!

For comparison: My labToy project on CMOD A7 35 builds in 3:40 min (excluding clock IP, measured on my wristwatch by resetting synthesis, then "generate bitstream").
It's not a large project - about 20 % of DSP used and slices touched - but not trivial either.
A hello-world project compiles in maybe 1 min, give or take some. But my desktop was built for the job (water-cooled i7 4930 @ 4.5G, 32G quad-channel RAM, M2 SSD).
Most of this doesn't help with a one-LED design, but there are a number of things that will slow down the run considerably:
- Use correct timing constraints:
For example, a LED driven from logic clocked at 200 MHz can be very difficult to route (but at the 12 MHz crystal frequency it shouldn't matter much).
A simple
set_false_path -to [get_ports LED]
makes it "don't-care".
- Throw in extra registers where appropriate, especially between blocks (which tend to be physically separate). Most of the time, it does not matter whether the signal arrives one or two clock cycles late, and some spare registers will simplify implementation. This is especially useful for register rebalancing.
- For the extra registers, it may make sense to use a "don't touch" attribute. E.g. in Verilog:
(* DONT_TOUCH = "TRUE" *)reg [5:0] wa [1:NWRDELAY];
(* DONT_TOUCH = "TRUE" *)reg [17:0] wd [1:NWRDELAY];
(* DONT_TOUCH = "TRUE" *)reg we [1:NWRDELAY];
When I have multiple, parallel instances of a timing-critical block, the input registers are logically equivalent, get optimized away, and then P&R takes ages because timing is so difficult. The "don't touch" attribute" keeps them separate, possibly using a couple of FFs more than strictly necessary.
- Removal of redundant logic can take a long time. For example, when I simulate pipelined DSP like the "labToy" generators I simply carry all data all the way through the pipeline, even though most of it isn't needed. Optimization will eventually remove it, but the cost is runtime. The LabToy example includes 8 instances each with a 6-lane 14-cycle 18-bit wide pipeline, and it adds minutes to the synthesis time if I don't remove the unused ends of delay chains in the source code.
- Read and understand every warning, and read the timing report. "The compiler is my friend"
For example, with PLL blocks it is easy to create duplicate clocks with the same frequency (one from the constraints file, one from the IP block). Timing analysis tries to (and will eventually) sort out all possible interactions, but it takes a lot of time and can create meaningless but difficult routing constraints.
- Fix "critical warnings" related to timing. Even if common sense tells the design will work e.g. classroom demo with buttons, Vivado will waste a lot of time trying the impossible.

I solved my ethernet problem and the specific connections to make it work.
I didn't have I2C enabled on the Zynq7 customisation. so I also enabled I2C over EMIO. I think this hampered it's ability to communicate with the address chip
I changed in the Zynq 7 processor MIO configuration - the ENET0 MDIO device is now MDIO pins MIO 52-53.

@Shuvo Sarkar
What exactly needs to be done depends on what you mean by "region of interest" and "binary mask". I will assume that you are trying to replace some area of what is being displayed on the screen with a rectangular image. A good starting point would be to take the input stream and output it with modifications. The DemoScaleFrame function in video_demo.c does this. The resolution scaling being done by this function also may or may not be desirable for your project. The Bilinear interpolation function implemented on line 473 of the original source is the primary point of interest here. The three variables required to tell what is being written to in the destination frame are the index, i, which can be used to determine the color channel being written to, and the destination coordinate variables xcoDest and ycoDest. A good starting point to be able to see changes being made would be to add extra code to black out a rectangular area of the screen. This can be accomplished by wrapping the destFrame[iDest] statement within an if statement, that either writes a zero to destFrame[iDest] or runs the bilinear interpolation of the source frame, depending on the coordinates of the target pixel in the destination frame.
How you store, access, and process the binary mask (overlay image?) is a large topic that I would need more details to provide information on.
Let us know if you have more questions.
-Arthur

FTDI USBs like AD, AD2, DD are not working with RPI model B (1,2,3) data packets/bytes are randomly lost.
The EExplorer with different USB controller is working fine on these.
All devices are working with other embeddeds: Zed, Zybo, BeagleBone…
According reports AD is working with the original RPI model A and probably Zero because it has similar chipset/USB.
The problem seems to be with FTDI or RPI B USB, library or hardware. You can find such comments regarding RPI problems with other devices too. Unfortunately we couldn't remediate this problem.

@dcc,
If you actually want to set/read memory, you'll need to learn how to interact with a bus. I like to use a B4 pipelined wishbone bus. I find it very simple and easy to use. For example, you can find a very simple block RAM device here that interacts with a wishbone bus. (It would be even simpler if I wasn't keeping my high speed and low speed code in the same file ...)
Xilinx has committed themselves to the AXI bus--a bus that requires the management of five separate data paths just to get right. If you want access to DDR3 SDRAM, you'll need to use Xilinx's memory interface generator (MIG) to build an interface for you. (I tried without MIG, made lots of progress, but ... after two months of full time work on it hadn't finished the task. It's a shame. The memory access delay would've been about half of what Xilinx's delay is.) Xilinx's MIG generates a DDR3 interface to a memory using an AXI controller. You can see how I interact with that AXI controller in my own Arty design here. Within that file, take a look at the mig_axis component and then roll your eyes with me at the quantity of wires and communications paths you need to handle just to read or write from memory. Yuck.
That's why, in the same file, you'll find a wishbone to axi bridge, one I call wbm2axisp, or wishbone master to AXI slave pipelined. As a result, I can interact with that core using wishbone signals, such as i_wb_cyc to indicate that I am accessing the bus (needs to be high throughout the transaction), i_wb_stb to request a memory interaction (only needs to be high for one clock while o_wb_stall is low per request), i_wb_addr (specifying the address of my request, must be valid any time i_wb_stb is high), i_wb_we (specifies if I am reading or writing), i_wb_data (data to write, must be valid anytime i_wb_stb and i_wb_we are high), o_wb_ack (true any time a memory access completes), o_wb_stall (true if the memory isn't ready to accept a transaction), and o_wb_data (the data result of any read transaction). The number of wishbone signals are truly ... much less than that giant AXI bus. (10 signals, of which 4 have multiple bits associated with them.) Looking at the AXI bus, to interact with it you will need 35 signals, of which 23 have multiple bits. Take your pick. (By the way, going from an 8-bit data width to the 128 bit data width used by the DDR3 SDRAM is not nearly as hard as it sounds, if that's something you would be struggling with.)
If you are trying to read/write from memory to support both an ADC and a DAC, you'll need a couple of things. One of them is a FIFO. You can see an example of a FIFO supporting a UART here. DDR3 memory speed can be unpredictable, and it can drop out suddenly for a refresh cycle while you are trying to interact with it. Worse, that MIG interface takes upwards of 24 clocks to complete a transaction. (If you pipeline your requests, only the first will take 24 clocks, the rest can take one clock. See the wishbone B4 spec for a discussion of this.) However, with a FIFO you can weather some of these problems without dropping samples, and even get on and off the memory bus faster. Second, you'll need an arbiter--something that decides of the two transactions you'd like to make, which of them actually gets access to the bus. You can find my own wishbone arbiter here.
If you are wondering just how to get a wishbone transaction working, I have examples ranging from simple to complex. For example, here is a simple prefetch example that just reads a single value from memory (i.e., the next instruction for a CPU). Here's another, similar example, which reads two values from memory at a time. (When working with that SDRAM, the first can take 24 cycles per read, the second can do two reads in 25 clock cycles.) And, while we are at it, here's an example which reads 2^N values at once--but since it's got a cache within it, it ... tends to be more complicated. Another example would be the code I've used for building my own DMA. Take your pick. How deep would you like to dive into this? I could go on and on for a while with more examples ...
Is this the sort of thing you are looking for? Let me know, and I can offer more, explain any of the above, or ... you tell me.
Yours,
Dan

The trick is your code does not need to infer a block memory generator. It will actually need to explicitly implement the block memory generator INTERFACE. This is because the block memory generator is already being instantiated in the block diagram.
You will need to design a state machine in VHDL that properly implements the interface. For a description of the signals (en, we, addr, etc.) you should refer to the block memory generator Product Guide. You can find the guide by double clicking the block memory generator IP and selecting Documentation in the upper left corner.
The end goal will be to create a custom IP core that contains this custom VHDL. Since you do not have an AXI interface on your core, this should be pretty easy. I believe you can just create a new project that targets the ZYBO and has its top level ports be the desired ports on the IP block. Then I think you can run the Create and Package IP wizard from the tools menu to convert the project to an IP core so it can be inserted into you block diagram (which will be in a different vivado project). I'd recommend simulating your project before you convert it to an IP core to help make sure it is functioning as expected.
BTW, you can just expand the BRAM_PORTB interface on the block memory generator IP core and manually connect each of the signals to your IP core if you have difficulty making you custom IP implement the BRAM interface.
See the picture below for an example of what your end goal will be:

@silverwolfman,
I don't have my S6 on my desk to tell you how much time it took me to load the flash, but I do know I didn't use iMPACT. You can find my work here. In particular, the flash loader is called zipload, and depends upon the using the Digilent Adept utilities to load an initial configuration (generated from this toplevel file) into the flash.
Dan
P.S. I'll be redoing my work again soon, to prove that the updated ZipCPU can still fit (and work) on the device. You can see some of my update works in the 8-bit branch of the s6soc project, but ... although it builds, it hasn't been tested yet so ... it's still a work in progress.

@Hassan Iqbal,
Can I try to answer?
Your solution will have two parts. The first part will feed the camera image constantly into memory. When you get the vertical sync to start again at the top of the page, you just reset your write memory pointer. The second part of your solution will read the image out of memory on your other clock. This will read out with the synchronization parameters you are trying to achieve. This way, if you write faster than you read, you'll quietly and slowly drop a frame, and if you read faster than you write, you'll eventually get a full frame stuffed into your stream--but either way things will work. This approach will use a "nearest-neighbor" interpolator, and will handle over and underruns by frame dropping or stuffing respectively.
The trick you will have is that you only have one interface to memory. For that reason, both video streams will need to buffer their work into a FIFO. When the writer's FIFO is roughly half full, then it will need to write to memory until it's FIFO is empty. Likewise, when the reader's FIFO is half full, it'll want to initiate a read until its FIFO is full. This way, if both the writer and the reader want to access memory at the same time, they'll both be able to wait until the other completes it's memory access request/requirement.
I haven't checked on your memory timing requirements at all. That could make things difficult. If it makes things impossible, then drop color bits and you should be able to get back into the realm of possible again.
As for how to handle the multiple clocks, you will have three clocks you will need to deal with and work from. Two of these are your pixel clocks. The third is your memory clock. You can synchronize from the pixel to the memory clock and back again using the single "FIFO is half-full" wire.
Dan

@Manas,
Sam is trying to turn voltage = (12-bit-code)/4096 into microvolts = (1000)*(1000)*(12-bit-code)/4096, and he's trying to avoid division. Rearranging:
1000*1000/4096 = 500*500/1024 (just by dropping common factors of two from both numerator and denominator)
Shifting right by ten is equivalent to dividing by 1024, and then he multiplies by 500*500. Looks like it works alright.
I might be concerned personally about losing any precision in the divide by 1024 (i.e. shift right by 10), especially since it is being done before the multiply if I understand correctly--leaving you with only 2-bits of precision (did I read that right?). Looking at the above, you might simplify it further into a shift right by 6, followed by a multiply of 15625. To get here, all I did was cancel out any factors of two that were in both the numerator and denominator. Then --- rearrange your order of operations, so the multiply is done first. What makes this choice special is that 15625 can fit within an 18-bit multiplier. Hence you can do:
A = 15625*(12-bit-voltage-code)
inside a DSP multiplier, and hence inside one clock. The result of this multiply will be a 30-bit number. If you ignore the bottom six bits, the 24-bit number that remains will be the number of microvolts that you are looking for.
Converting this to a decimal display might take some more work though.
Dan

Hello,
R254 is a 0 ohm resistance. you can find it on bottom of the board. See picture attached. It is true though, that it has a tolerance of few miliOhms. They are not different from one board to another.
Best regards,
Bianca

Well I think that this is better stated as saying that most serial terminal applications can only connect to one COM port at a time. It is possible to mave multiple UARTs in your FPGA design and connect to multiple serial terminal applications. I like Putty myself, but there are other options.
Another possibility is to look around in the Digilent Project Vault and see at least 3 project with source code that might accomplish what you want to do. If you instantiate your own UART you can access any number of internal registers or memory.

Hi @Ahmed Alfadhel
I had the C code handy because I have been working on an atan2(y,x) implementation for FPGAs, and had been testing ideas.
I left it in C because I don't really know your requirements, but I wanted to give you a working algorithm, complete with proof that it does work, and so you can tinker with it, see how it works, and make use of it. Oh, and I must admit that it was also because I am also lazy 😀
But seriously:
- I don't know if you use VHDL or Verilog, or some HLS tool
- I don't know if your inputs are 4 bits or 40 bits long,
- I don''t know if you need the answer to be within 10% or 0.0001%
- I don't know if it has to run at 40Mhz or 400Mhz
- I don't know if you have 1000s of cycles to process each sample, or just one.
- I don't even know if you need the algorithm at all!
But it has been written to be trivially converted to any HDL as it only uses bit shifts and addition/subtraction. But maybe more importantly you can then use it during any subsequent debugging to verify that you correctly implemented it.
For an example of how trivial it is to convert to HDL:
if(x > 0) { x += -ty/8; y += tx/8;}
else { x += ty/8; y += -tx/8;}
could be implemented as
IF x(x'high) = '0' THEN
x := x - resize(y(y'high downto 3), y'length);
y := y + resize(x(x'high downto 3), x'length);
ELSE
x := x + resize(y(y'high downto 3), y'length);
y := y - resize(x(x'high downto 3), x'length);
END IF
My suggestion is that should you choose to use it, compile the C program, making the main() function a sort of test bench, and then work out exactly what you need to implement in your HDL., You will then spend very little time writing, debugging and improving the HDL because you will have a very clear idea of what you are implementing.

Nothing to worry about if only one is up at a time. It would mean that the frequencies of adjacent oscillators affect each other if they are running at the same time ("injection pulling", to the point that they agree on a common frequency ("locking").
Consider the oscillator as an amplifier with a feedback loop. The feedback path plus phase shift lead to a fairly narrow frequency response around the oscillation frequency or harmonically related frequencies). Weird things can happen with the gain - while it is unity in average steady-state operation, the circuit can get highly sensitive to external interference that is (near)-correlated with the oscillator's own signal.
Wikipedia:
Perhaps the first to document these effects was Christiaan Huygens, the inventor of the pendulum clock, who was surprised to note that two pendulum clocks which normally would keep slightly different time nonetheless became perfectly synchronized when hung from a common beam

For the Protocol / SPI-I2C /Spy mode you should specify the approximate (or highest) protocol frequency which will be used to filter transient glitches, like ringing on clock signal transition.
The Errors you get indicate the signals are not correctly captured.
- make sure to have proper grounding between the devices/circuits
- use twisted wires (signal/ground) to reduce EMI
- use logic analyzer and/or scope to verify the captured data / voltage levels at higher sample rate at least 10x the protocol frequency
Like here in the Logic Analyzer you can see a case when the samples are noisy:

Hi @askhunter,
The top.vhd is already added to the project. If you are wanting this file to be underneath the design_1 then you should right click on the design_1 and select add sources. Then add the vhdl files you would like to add to the design. It might be easier to start with a fresh project.
best regards,
Jon

Hi @Amin,
I know our content team is planning on updating our Petalinux projects. We currently do not have an ETA for this. Here is the Petalinux Support for Digilent Boards table that shows what Petalinux projects we have for our development boards and has a link to them as well. To use our most recent Petalinux release for the Zybo-Z7-20 I would suggest to download Vivado/SDK and Petalinux 2017.4. I would also suggest reading the Petalinux projects detailed readme as well.
thank you,
Jon

Hi @billskar23,
The Pmod ACL here uses the adxl345﻿. Here and here are forum threads that might be helpful. Here is an instructable on how to use spi in the linx platform. Here is spi open. Here is the plug and play instructable for linx. Here is another instructable using the Pmod ACL. Unfortunately, both of the instructables use the Pmod ACL in I2C and not SPI. Here is the adxl345 datasheet. On page 23 is the register map table. Page 15 describes how to use the spi communications. Clearing the SPI bit (Bit D6) in the DATA_FORMAT register (Address 0x31) selects 4-wire mode.
cheers,
Jon

Hi @Brinda,
You want to download the release version of Zedboard DMA project here. I was able to generate a bitstream without issues in vivado 2016.4. Unfortunately, Vivado projects are version specific. This project was made in and works with Vivado 2016.4 without having to make alterations to the project. What version of Vivado are you using?
cheers,
Jon

Szia @Andras
The Network Analyzer by default takes controls over the Wavegen channel 1 and configures the required frequency for each step. You could select NA/Wavegen/Channel/External but to be able the control the Wavegen manually, but in this case the previous Script solution won't work.
The Insert/Local lists specific variables and is available in other scriptable places, like scope custom math, measurements, logging, network analyzer custom plots
In each script editor including the Script tool you can use the Ctrl+Space to list available objects, variables... or child objects, properties, functions..

Hi @BYTEMAN,
I am not aware of a way to have those specific microblaze configuration pages to be used after the initial block automation. I would suggest to reach out to xilinx about this question. I believe you are correct about the xdc overriding the board file defaults.
thank you,
Jon

This is the warning that matters: "signal 'up_test' is read in the process but is not in the sensitivity list"
What has happened is the tools have detected that you read the value of "up_test" in the process, assumes that you have made an error, and helpfully added it to the process's sensitivity list. This is because for any async logic in processes all signals that are used in the process should be included in the sensitivity list.
Were "up_test" included in the sensitivity list you would get exactly the observed behavior (although now any simulations would hang/break... sigh).
If this is the right thing for the tools to do is an open question - sometimes it is, sometimes it isn't. Throwing an error rather than a warning would break existing code bases... issuing warnings lets these sorts of issues slip through.
By "you haven't defined is some way to filter out the changes of BTN", Ignore me - I was just waffling on to allude that you need to use "rising_edge()" somewhere to control the timing of when "up_test" gets updated.

If I take it to extremes, the answer is surprisingly complex (this is how it's done inside the clock management tiles or a cellphone, for example).
For household use, take (e.g.) a 32 bit counter and add "delta" at a high frequency, e.g. 100 MHz. Don't check for overflow, it will wrap around cyclically (which is the "correct" way to behave in this application. E.g. 0xFFFFFFFF + 3 becomes 0x00000002)
For example, at 100 MHz clock, a delta of 1 gives a cycle time of 42.9 seconds (2^32 / 100e6).
A delta of 43 gives a cycle time of one second. A delta of 42950 gives a cycle time of exactly 1 ms => 1 kHz.
Now we've got a 32 bit number. Take the highest bits (as many as the DAC needs), voilà, a sawtooth generator.
Plug that into your wavetable (you'll have to recalculate for a 0..31 range if using five ramp bits).
Simple lookup from a block RAM (aka "nearest-neighbor / zero-order interpolation") will give abysmal audio quality, or the wavetable grows so large that it doesn't fit into the FPGA. So I need higher-order interpolation or a different algorithm (e.g. CORDIC for sine), and things get messy.
PS: When working with signed numbers, check Verilog's "signed" keyword. It's not mandatory, but makes life easier.

I searched for inactive driver in the Windows device manager and found out that there appear 2 x USB Serial Converter A and 2 x USB Serial Converter B. I deleted all of them and powered the board. Now both boards work.

Hi @Jay Sngh,
I have received the Declaration of Conformity's for the Basys 3, the Pmod USBUART, and the Pmod RS232. The other two Pmods (the Pmod LVLSHFT and the Pmod SSR) are exempted based on "subassembly exemption". All of our boards are designed with UL-94V0 rated PCB material and are RoHS Complaint.
Let us know if you have any questions.
Thank you,
JColvin

@SUSHMA MANTAGANI,
I think what you are wondering is what is wrong with your design. To answer that question, you really need to use wireshark for debugging it. That will allow you to look at and inspect the packets that are crossing the wire, so that you can see if they are properly formed or not. Indeed, that will also allow you to figure out whether or not it is the fault of the computer you are transmitting from, or the fault of the one you are transmitting to, and what part of the packet(s) are actually at fault.
Dan

@shashi
Assuming that you are bringing the image onto your zedboard from a PC, your best option is probably to set up an ethernet connection to your board. This tutorial was written for the Zybo, but should still apply. Once you have a server running, and can pass received data to your algorithm, you will need to get the image data into a format that you can send. You have a few options here, you could use some sort of script to communicate with the board (for Python, possibly this library, looks like a significant challenge), or you could parse the image data into a format that whatever serial terminal you are using could accept - for TeraTerm, you would need to write a program to convert your image data into a Tera Term Macro, reference information here.
Hope this helps,
Arthur

Hi @jem2k,
I've tried to do some digging to find alternative sources for the project you are asking about. I haven't found anything, so instead I have asked if it possible that the project still exists somewhere on our site. I will return to you when I have an answer.
Thank you for your patience,
AndrewHolzer

@sandy3129 / Sandeep,
I think I've read through your post about five times over, and I'm still not quite certain what you wish to do. You wish to connect GPIO to the axi traffic generator ... why? To test whether or not the AXI interface works? Wouldn't it make more sense to do that from the Zynq CPU? Is there a particular AXI function that you wish to know if it works?
Dan

Great to hear Enrico! Let us know if you hit another roadblock or need anything else. Also, feel free to comment on the guide if things were not clear or if we could improve it in some way. A little constructive criticism is always welcome.
Mikel