Samueli Sees Life After Moore's Law

All signs are Moore's Law is really slowing down -- we don't have universal agreement, but all the data points we see show slowing down, and more important, beyond the 28 nm node cost per function is starting to go up. You still get performance and power advantages, but you don't get cost advantages, and historically you got all three, so now we need to think twice about how to migrate to the next node.

He predicted the 28 nm node will be "long lived... It may ultimately become the cheapest node available if you don't have to have the megachips."

Broadcom does have some of those megachips with its Ethernet switches and XLP network processors. It's skipping the 20 nm node to employ the 16 nm process that has the same feature sizes but adds the 3D transistor structures known as FinFETs.

Beyond that, the 10 nm has some process before the limits of physics loom large. "It's looking like 7 to 5 nm is close to end of the road, at that stage you have about 10 silicon atoms in a gate of a transistor."

In another IEDM keynote, academic researchers gave a progress report on one alternative to today's CMOS process. But their paper on advances making gigahertz-class transistors with grapheme also noted they still don't see their way around the current obstacles to making the process commercially viable.

"Being only one atom thick, graphene has a potential to overcome state-of-the-art Si and III-V semiconductors in high-frequency transistors at the ultimate scaling limits," they wrote in their paper. However, "there are several figures of merit that should be considered before GFETs can be used in realistic multi-stage electronic circuits, instead of InP heterojunction bipolar transistors."

Researchers showed a ring oscillator made in graphene at IEDM.

Broadcom, like Qualcomm, is keeping a weather eye on 3D stacks as one way to deliver at least a one-time boost. For its part, Broadcom is working with partners on a plan to put its networking chips on a silicon interposer next to silicon photonics devices to gain an edge in speed.

Longer-term, fast-moving digital designers could come to resemble their cousins in analog technology. "They all use older legacy technologies that work just fine -- they crank out tons of products," Samueli told us.

"In the future they may not be able to charge the premiumjs for 28nm, 16nm they charge today, but then they will not have the enormous expenditures of new multibillion dollar fabs every 18 monthys either. The biz dynamics will shift radically.

Imagine what that might be like!"

Yes - what egalitarian dreams! I can only imagine the large swaths of un-washed masses storming the bastile. Cake (FinFet) for everyone!

I just spoke with a technologist at a leading OEM and server design company who says Moore's Law ended about ten years and claims to have predicted the end about twelve years ago...whether or not that's true, it seems everyone is finally accepting that the days of packing more transistors and getting a denser and denser product are nearing an end--albeit slowly....

as the R&D cost incurred by the leading Foundry to keep up with Intel shoots up, that cost is bound to get xferred to their Fabless customers, cutting into their huge margin up to now. this is what I had meant as "the free lunch is over for the fabless wonders"

Yes, it is clear thar cost per transistor is not going down with dimension scaling, but new type of scaling - monolithic 3D - would keep Moore's Law in the near future. Samsung is already doing so with 3D NAND and other are moving toward monolithic 3D just as well. The first adaption of monolithic 3D is in the memory segment, and other segment will follow, as we just recently learned whith Qualcomm sign up with CEA Leti. In a recent Blog we articulated why Scaling makes monolithic 3D IC practical http://electroiq.com/blog/2013/10/scaling-makes-monolithic-3d-ic-practical/, and in our site we present the cost and othe benifits the monolithic 3d technology provides - http://www.monolithic3d.com/3d-ic-edge1.html

@Tarra: Fabs like TSMC are just starting to ramp up really expensive (profitable) 3-D stacking processes.

In the future they may not be able to charge the premiumjs for 28nm, 16nm they charge today, but then they will not have the enormous expenditures of new multibillion dollar fabs every 18 monthys either. The biz dynamics will shift radically.

This does level the playing field a bit. Design innovation is where companies will have to distinguish themselves. The best, most efficient design shall survive rather than the design on the latest process node.