For the Synchronous DC-DC converter switching performance of low-voltage power MOSFETs, the gate-drain charge density (Qgd) is an important parameter. The so-called figure-of-merit, which is defined as the product of the specific on-resistance (Ron.sp) and Qgd is commonly used to quantify the switching performance for a specified off-state breakdown voltage (BVds).

Wire Bond Shear (WBS) test is a method for evaluating the strength of a ball bond, to complement wire pull test. In foundry, wafer-level (WLR) WBS provides a quick way to demonstrate the integrity of metal bond pad, backend scheme as well as bond or via design. This is a big challenge for WLR WBS outsourcing as many of the factors affecting shear strength lying on the wire bonding parameters and shear test setup. This paper presents the outsourcing experiences of WBS tests and good shear strength was achieved from the outsource laboratory.

A study on the effect of process fabrication for MIM capacitors analog matching performance was carried out, impacts from the MIM dielectrics, capacitor top and bottom metal materials, capacitor metal etch, wet cleaning, annealing process will be revealed by comparing the Pelgrom coefficients, i.e. the dependence of difference in capacitance of the matching pairs with respect to their corresponding square root of capacitor areas, the smaller the difference the better the matching.

Diodes inherent in a CMOS process are light sensitive and could be exploited as photodetectors. To detect light the photo generated carriers need to be separated by the electrical field of an internal pn junction. They are either generated inside the depletion region or can get there by diffusion. The depth where these carriers are generated depends strongly on the wavelength. The generation profile, the pn junction depth and the diffusion length all impact the spectral sensitivity.

IC content in cars has been growing exponentially, adding significant complexity to automotive chip design and manufacturing. Today’s cars feature many semiconductor applications such as tire pressure monitoring sensors and accelerometers for airbag systems. Add electronic components to improve engine performance, increase fuel efficiency, control modern entertainment and communications devices, provide Internet capability and handle new comfort functions... Now add the challenge of making the associated ICs survive for many years in extreme heat and cold, rain and snow, salt, g-forces, humidity, dry and dusty conditions...and you’ve got your hands full designing for one of the most harsh IC operating environments.

In low leakage MOS device fabrication, careful pn junction design is critical to control overall device leakage, such as Band-To-Band Tunneling (BTBT) and Gate-Induced Drain Leakage (GIDL) that are always taken into consideration by device designers. Source/Drain implantation also play a very important role in suppressing silicon dislocation effect, which increases implanted species transient-enhanced diffusion (TED) and induces shallow-junction leakage.

Are you looking for a highly reliable embedded non-volatile memory (NVM) solution in an advanced technology node that is easy to integrate into your design? One that can serve as a platform for developing complete product families? This free webinar introduces X-FAB’s new XH018 eFlash option – the industry’s most cost-effective combination of high voltage and embedded flash for complex SoCs. Find out how it works and why eFlash is ideally suited for for high-speed microcontroller, digital power and automotive applications.

Photo detector integrated circuits (PDIC) require high-sensitivity and high-bandwidth photo diodes for the latest generation of Blu-ray data storage devices. Due to the very short 405nm wavelength used, carriers are generated close to the surface. Standard photo diodes have only a low sensitivity for blue light. Therefore, special adapted photo diodes are necessary to support sensitivity higher than 0.25A/W for a 405nm wavelength.

Successful integration of 100V LDMOS devices in 0.35μm CMOS technology is presented in this paper. These integrated devices are enhanced N-type and P-type LDMOS which are compatible with thin (14nm) and thick (40nm) layers of gate oxide. A breakdown voltage of more than 100V with RDS (ON) =200/180mΩ.mm2 for N-type LDMOS and RDS (ON) =690/640mΩ.mm2 for P-type LDMOS with 14nm/40nm gate oxide thickness.