The Saanlima Pipistrello is an FPGA development board with many on-board peripherals and pin headers compatible with the Papilio series of boards. It has USB connectivity to a host PC, and, by adding the Saanlima buffer wing, can be used as a replacement for the Openbench Logic Sniffer (OLS).

The FPGA firmware for the OLS has been ported for the Pipistrello, and can thus use the full 64MiB memory to store samples. It also has triggers on rising/falling edges as an extra feature.

All design source for the Pipistrello, including schematics and Eagle board files, are available under the CC-BY-SA 4.0 license.

Protocol

The protocol used is the same as the OLS protocol, with the addition of commands for edge triggers. See the source code for details.

The Pipistrello needs to be manually flashed with a FPGA bitstream to work with sigrok. These bitstreams can be downloaded from the Pipistrello wiki and the source code is available (see bug #1021 about possible automation for for this).