Area Efficient and Low Power VLSI Architecture of Min-Sum LDPC Codes using Wave-Pipelining

The superior error correction properties of LDPC (Low Density Parity Check) codes have gained great interest in the research fields. LDPC codes have wide applications in various fields like MIMO OFDM, WLAN, etc. This paper presents the study of Wave pipelining in LDPC encoder and decoder. The encoding of LDPC codes are quite complex when compared to the decoding part. Reduction of parity check matrix is analyzed by Gauss elimination method. Min sum iterative decoder has a reduced complexity with respect to the architecture-algorithm transformation, compared to other LDPC decoding algorithms. The architecture is designed for LDPC encoder and the variants of Min sum decoder and compared with that of pipelining and wave pipelining.