Not only was the C2L CMOS process simpler, denser and faster than previous ones, it lends itself to radiation-hard chips, which led to this CPU being found in various space probes. (The bulk silicon process used for our RCA 1802 is not as radiation tolerant as the later silicon-on-sapphire processes, but it was better than other contemporary processes.)

As it happens, it's also a great process for us to photograph and analyse, because the N and P structures show as different colours, and the layout is very readable.

Simple logic gates

Above we see a detail of our high-resolution images, showing several logic gates laid out with their complementary pullup and pulldown trees in their respective areas (Orange on green is NMOS, purple on blue is PMOS.) The power supply to each gate is the substrate (or well) so there are fewer contacts than in the usual technologies.

Middle-right is the simplest gate: an inverter, with a single pull-down and single pull-up. Above it is a 2-input NOR gate and to the left is a 3-input NOR gate. The three concentric transistors of the NOR3 are rarely seen on this chip, perhaps because of the reduced drive and speed of having 3 transistors in series.

NOR4 layout

If a NOR4 were laid out like the NOR3 above, it would be rather large because of the need for 4 concentric transistors. The largest (outside) transistors would present more load to their drivers, but wouldn't contribute more drive to the NOR4 because that will be limited by the innermost transistor.

So here we see an alternative layout technique, where an isolated region is created in the lower right, containing two of the pullups, the upper one of which is operated inside-out.