"Using Pentek's GateFlow Design Kit saved me valuable development time. I've successfully taken a function developed in Simulink with Xilinx IP and inserted it into the 7142 ISE project in place of the DAC's user block. I used your modified project and took advantage of the control register bits you set up, so I want you to know that was really helpful. I was able to generate the MCS file and test it in the hardware, and everything worked great. I appreciate your help along the way! A bonus was that I could do it mostly on my own quickly (as opposed to writing Verilog or VHDL that would have taken a lot of time and research). So we're convinced at this point that we really do have an end-to-end rapid development process for FPGAs!"

Custom Design Services

GateFlow for Cobalt Virtex-6, Onyx Virtex-7 and Flexor FMC Products

Using the FPGA Design Kit

The GateFlow FPGA Design Kit allows the user to modify, replace and extend the standard installed functions in the FPGA to incorporate special modes of operation, new control structures, and specialized signal-processing algorithms.

The Onyx Virtex-7, Cobalt Virtex-6 and Flexor FMC architectures configure the FPGA with standard factory supplied interfaces including memory controllers, DMA engines, A/D and D/A interfaces, timing and synchronization structures, triggering and gating logic, time stamping and header tagging, data formatting engines, and the PCIe interface. These resources are connected to the User Application Container using well-defined ports that present easy-to-use data and control signals, effectively abstracting the lower level details of the hardware.

The User Application Container

Shown below is the FPGA block diagram of a typical Cobalt, Onyx or Flexor module. The User Application Container holds a collection of different installed IP modules connected to the various interfaces through the standard ports surrounding the container. The specific IP modules for each product are described in further detail in the datasheet of that product.

The GateFlow Design Kit provides a complete Xilinx's ISE or Vivado project folder containing all the files necessary for the FPGA developer to recompile the entire project with or without any required changes. VHDL source code for each IP module provides excellent examples of how the IP modules work, how they might be modified, and how they might be replaced with custom IP to implement a specific function.

GateFlow for Other Virtex FPGA Products

Using the FPGA Design Kit

The GateFlow FPGA Design Kit is intended for the programming of predefined user blocks located in the data flow path specifically reserved for custom applications. These predefined blocks protect users from inadvertently altering base functionality.

Pentek recommends user programming be limited to the predefined user blocks to maintain base functionality. However, for more complex requirements, sufficient information is supplied in the kit for the user to modify, add to, or replace default board functions if necessary. Default configuration files are included with the Design Kit should it be necessary to restore standard factory configuration.

FPGA Design Kit User Block

Shown below is the block diagram of a typical software radio module. The diagram includes the FPGA and external hardware devices connected to it.

The blocks inside the FPGA are VHDL code modules that handle the standard factory functions and interfaces. The User Block is a VHDL module that sits in the data path with pin definitions for input, output, status, control and clocks.

In the standard Design Kit product, the User Block is configured as a straight wire between the input and output ports. By creating a custom algorithm inside the block that conforms to the pin definition, the user will have a low-risk experience in recompiling and installing the custom code. Since Pentek provides source code for all the modules, changes outside the user block can also be made by the user.

Pricing and Availability

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