The transistor drive in the large 555 diagram is differential, thus negating the need for the classic PNP/NPN pushpull stage. It seems that they couldn't get enough current to drive the upper stage's base-emitter enough, so they chose a darlington arrangement in order for enough output current.

I'm not sure what you're trying to do, the interface from the 555 to a driver of some sort? Why not take a fet driver (pretty much a high power push-pull) to drive a fet half-bridge?

If you can tolerate a few hundred nanoseconds of propagation delay, I've got a circuit that, in simulation, swings rail-to-rail and gives <20ns rise and fall times into a 1nF load, with almost zero shoot-through.

Actually it is a big loss in drive current capability. 200ma max is a hard act to follow for CMOS.

*****************

OK, I take it back, it can handle 100ma. Just looked at the datasheet.

I already have 100's of 555s though. Have I mentioned I really like this chippie?

While I haven't stated it, this will be used in my function generator eventually. I might give this chip an honorable mention though, and eventually buy a few.

The other reason I started this thread is I'm working on a 555 series for the AAC eBook projects. This might be used there for a driver chapter. Come to think of it, the function generator falls under that catagory too.

This circuit builds in some dead time to prevent shoot through. There may be an IC that does the same thing. The output swings rail-to-rail with input from a bipolar 555, and simulated rise and fall times are less than 20ns into a 1nF load, and around 100ns into 10nF.
I included the .asc file just in case anyone wants to simulate it in LTspice.