Architectural/Definition

FirstPass has demonstrated expertise in leading development from concept through to production. We understand the relationship between specification and implementation, and know how to partition designs and make trade-offs necessary for performance, risk mitigation and functional flexibility. We are very well versed in technology capability analysis and selection.

Technology Selection

FirstPass is very well versed in technology capability analysis and selection. We have developed a strong level of experience working with a wide range of ASIC foundries and FPGA suppliers.

Design

Our expertise includes digital, mixed signal, analog, I/O, memories, and very high speed circuitry including SerDes. We also have RTL expertise in both VHDL and Verilog. We have taken hundreds of designs from specification through to fabrication. Probability is high that we have directly related experience that meets your requirements and type of project.

Digital Design

VHDL, Verilog

RTL, C to RTL

Design IP integration

DesignWare, process libraries (memory, I/O, SERDES, etc.)

3rd-party design IP

Multiple voltage and power domains

SOC integration and HW/SW co-design

Design-for-synthesis

Synopsys Design Compiler, FPGA vendor specific tools

Design-for-test

Design-for-verification/debug

Analog/Mixed Signal

I/O design

SerDes, DDR3, Analog

PLL, DLL design

Band gap reference generator

Standard cell libraries

SRAM, DRAM

Sense amps, current amplifiers

Various timing circuits

SerDes PHY design and layout

Macros and Protocols

CSIX

PCIe Gen1/2/3

PCI

SPI 4.2

Infiniband

Rapid IO, Serial RIO

ARM Core

HyperTransport3

CPRI

SONET

SAS (Serial Attach SCSI)

SATA

Fibre Channel

Ethernet

2-Wire Serial

USB

XAUI

JESD204A/B

…and many more

Synthesis and Timing Closure

Synthesis and timing closure starts with robust design. We understand how to architect and code to meet timing and optimize power and area. Good synthesis planning pays dividends in physical implementation. We have experience with many synthesis and static timing analysis tools such as Design Compiler, PrimeTime, Synplify, Altera Quartus, Xilinx XST and Magma.

Functional Verification

FirstPass engineers are verification experts. As ASIC/FPGA and system capabilities have exponentially increased, verification methodologies have changed dramatically. The randomized, object oriented approach to verification has greatly increased the efficiency and quality of pre-silicon simulation. Verification metrics such as code coverage and functional coverage allow us to answer the question “When are we done?” These metrics also provide a good understanding of risk and program tracking. Widespread use of assertions in RTL coding have reduced debug time and increased correlation between specification, design and verification. Formal verification is showing tremendous capabilities as well. We are experts with System Verilog, Vera, and Specman as well as VHDL and Verilog testbenches for lower complexity devices. This verification methodology is the key to FirstPass success!

Platforms

Physical Design

FirstPass engineers have successfully performed physical implementation of designs onto FPGAs, Gate Arrays, Standard Cell, and transistor level full custom ASICs. We have designed libraries along with Design Rule Check files and Electrical Rule Check files. We have taken many designs from RTL to GDSII release to foundry, and performed all physical verification checks including timing, power, logic equivalency, layout versus schematic, on chip variation, cross talk, etc. Tight integration with the design functions results in a manageable, high performance, low risk and efficient physical implementation.

Full custom layout

Device matching

Parasitic extraction

LOD effects

Well proximity effects

LEF and .LIB generation

Place and route

Full chip floorplanning

Hierarchical and flat design

IP integration

Physical constraint generation

STA and timing closure

Power bussing and power analysis

Signal integrity

Physical verification (LVS, DRC, ERC)

Silicon Validation and Test

FirstPass currently does not have test facilities. Working with our partners, we have brought multiple designs into production. Our management team has extensive experience coordinating all efforts required for validation and test.

QuickRamp Program (QRP)

The QuickRamp Program (QRP) is a FirstPass proprietary example of High Level Verification methodology structured under a SystemVerilog UVM methodology. The primary objectives of QRP are to address time-to-market concerns caused by steep learning curves of SystemVerilog UVM efforts, and to promote standardization and re-use of a SystemVerilog UVM environment. This is achieved by providing the end user with an advanced starting point including a robust learning platform, and providing a rich offering of highly re-usable SystemVerilog verification components and methods. QRP can be utilized either as a simple learning platform, or as the seed for a powerful yet flexible working verification environment. Using QRP as a foundation will assure that your verification development effort remains in synchronization with industry leading methods and techniques.

Overview

A High Level Verification (HLV) environment for an ASIC or an FPGA

The ASIC/FPGA is represented as the Device Under Test (DUT)

The DUT is written in Verilog

The HLV environment is created using SystemVerilog utilizing UVM methodology

Structured as a generic System Verilog test environment with a broad selection of easily customized and highly re-usable components

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About Our Firm

FirstPass Engineering was incorporated in 1993 with the goal of providing ASIC design services to the Mil/Aero marketplace. Our highly experienced staff at FirstPass averages over 20 years of experience in the semiconductor field.