2. The wafer is then annealed at low temperature (about 600C). At low temperature the Ti layer only reacts with the silicon contacts to form a high resistivity TiSi phase (C49). 3. The un-reacted titanium is then etched off the wafer surface (An etch solution that does not remove silicide or oxide is used) 4. A second anneal is then performed at high temperature (>800C) to convert the high resistivity phase (C49 or TiSi) to the desired low resistivity phase (C54 or TiSi2).

PVD Step Coverage TechnologyTechniques are : Mechanical collimator : the sputtered atoms pass through a grid in the chamber Long Throw technology : the distance between the target and the wafer is increased (190, 245, 430 mm) and the neutral atoms arrive plus or minus perpendicularly on the wafer Ionized plasma : the neutral atoms sputtered from the target are ionized inside the chamber, and the metallic ions are collimated to the wafer which is biased

Step Coverage

Via or Trench filling with Sputtering- High aspect ratio features have limited line of sight to target. - Conventional, non-directional sputtering results in “cusping” of sputtered material at the via opening creating a void.