Mainstreaming

By Kurt Shuler
Gartner analyst Jim Tully’s assessment that network on chip (NoC) technology will be “mainstream” in two to five years is an acknowledgement of the technical and commercial success NoC interconnect IP has had in the consumer electronics system on chip (SoC) market over the last couple of years.

As reported by EE Times, Gartner’s latest “Hype Cycle for Semiconductors” shows Network on Chip technology climbing the “slope of enlightenment” after its sojourn in the “trough of disillusionment.” As SoCs have become more complicated, SoC makers like Texas Instruments, Toshiba and LG have chosen to use NoC technology to proactively address wire routing congestion issues, timing closure failures and the need to easily create derivative SoCs based on a single SoC.

“Network on Chip”: Words mean something.
As with many new technologies, an early impediment to adoption was semantic: What is a “network on chip?”

It seems obvious today that a network on chip interconnect digitally packetizes information, allowing it to travel over paths of varying bit widths. If done intelligently, the NoC technology will be based on small elements that are physically distributed throughout an SoC floor plan. This is in contrast to traditional crossbars and switches, which are monolithic IP blocks that are hard to fit in the white space between IP blocks without causing routing congestion and timing closure problems.

A few years ago, confusion reigned in academia and commercial marketing about the definition of a NoC, with some defining it down to include any type of interconnect technology: Hierarchal busses, smart switches, crossbars, etc.

But a strict definition requiring data packetization and serialization won out. Today you’ll find marketers trying to wiggle out of that old semantic trap by putting the adjective before the noun, using “on-chip network” to describe any type of interconnect.

Technically correct. But using this logic, two tin cans and a string are a “communications network.”

Commercialization leads to mainstream technology
Besides resolving confusion around naming, what is the key factor that helps make a technology mature enough to be considered mainstream?

Commercialization.

By commercialization, I mean that painful process where a technology is used by a lead customer, refined, then used by a larger set of customers and polished some more. This cycle continues until the technology is robust enough and complete enough to meet the needs of a large percentage of an emerging addressable market.

Geoffrey Moore’s “Crossing the Chasm” is a great book that describes the sequential steps a new technology must go through before it becomes mainstream, as well as the need for a market infrastructure to develop to support it.

Gartner Hype Cycle graphic source: Gartner Group and EE Times

This cycle, called the technology adoption life cycle, holds true for any new technology, whether we are talking about the wheel (which also required roads, carts and draft animals to achieve huge productivity gains), canned food or the fax machine.

Network on chip technology also went through this technology adoption lifecycle, with early “innovators” demanding a new interconnect technology to address their then-bleeding edge needs. An example is Texas Instruments’ OMAP team, which needed a more scalable interconnect for their OMAP mobile application processors as each grew in complexity. TI is an innovator for having started using NoC technology nearly 5 years ago.

In the following years, “early adopters” started using NoC technology, providing more feedback that helped shape it into a complete solution for SoC interconnects of any size or complexity. This made the NoC technology “safe” for the more conservative “early majority” companies to adopt.

The future of NoC technology for SoCs
What does the future of network on chip technology look like?

Adoption of NoC interconnects by SoC makers is expected to increase quickly during the next couple of years.

Current users of NoC technology chose this solution because they were already experiencing SoC routing congestion, timing convergence and derivative creation problems and they needed a practical solution. More SoC makers will have these problems in the next two years as the most advanced mainstream semiconductor manufacturing processes shrink below 40 nm, allowing SoC designers to put even more functionality (and IP blocks) on a single SoC.

Adding more IP blocks causes routing and timing issues to increase at a non-linear rate, causing excruciating pain to back-end engineers and delays in chip schedules. The only way to address the problems caused by adding more IP blocks is to use an interconnect technology that is scalable, packetized, low power, and high performance while providing end-to-end quality of service and accommodating any type of transaction protocol. These requirements can only be met by commercial network on chip interconnect IP.

Kurt Shuler

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Kurt Shuler is vice president of marketing at ArterisIP. He is a member of the US Technical Advisory Group (TAG) to the ISO 26262/TC22/SC3/WG16 working group and helps create safety standards for semiconductors and semiconductor IP. He has extensive IP, semiconductor, and software marketing experiences in the mobile, consumer, automotive, and enterprise segments working for Intel, Texas Instruments, and four startups. Prior to his entry into technology, he flew as an air commando in the US Air Force Special Operations Forces. Shuler earned a B.S. in Aeronautical Engineering from the United States Air Force Academy and an M.B.A. from the MIT Sloan School of Management.