ABSTRACT:In this talk ongoing work from a research project with the talk title is presented. The aim of this project is to develop techniques for optimal and heuristic integrated code generation for explicitly parallel processors (EPIC). First results on register reuse scheduling are presented where spilling of registers during register allocation is minimized by a local reordering of independent operations. On average 8.9% less values are spilled resulting in 3.4% reduction of static spill cost. Other ongoing work on scheduling for clustered architectures is discussed.

BIO:Since February 1995 Andreas Krall is an associate professor for computer science (Praktische Informatik) at the Institut fŘr Computersprachen, Technische Universitaet Wien. Since 2002 he is also managing the Christian Doppler research laboratory "Compilation Techniques for Embedded Processors" which is jointly funded by government and industry (Infineon, OnDemand Microelectronics). The main research interests of Andreas Krall are compilers and computer architecture. Current work are the development of an architecture description language with automatic generation of optimizing compilers, high performance instruction set simulators and VHDL processor descriptions. Other important topics are all kind of optimizations (instruction selection, register allocation, instruction scheduling, program analysis), static and dynamic binary translation and the Java virtual machine CACAO (www.cacaovm.org). Andreas Krall (co)authored more than 80 journal and conference articles and is a member in the ARTIST2 and HiPEAC European networks of excellence.