Abstract

ILP Processors with centralized architecture are costly in terms of power, area and clock rate and are thus not suitable for consumer electronic devices. The consequence is the emergence of architectures having many interconnected clusters each with a separate register le and a few functional units. Among the many inter-cluster communication models proposed, the extended operand model extends some of operand elds of instruction with a cluster speci er and allows an instruction to read some of the operands from a different cluster without any extra cost. Scheduling for clustered processors involves spatial concerns (where to schedule) as well as temporal concerns (when to schedule). A scheduler is responsible for resolving the con icting requirements of aggressively exploiting the parallelism offered by hardware and limiting the communication among clusters to available slots. This paper proposes an integrated spatial and temporal scheduling algorithm for extended operand clustered VLIW processors and evaluates its effectiveness in improving the run time performance of the code without code size penalty.