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Abstract:

In a method for driving a display device, an address counter is used for
generating a plurality of address variables corresponding to data of a
scan line. Next, an address mapping circuit generates a first target
address by data-mapping an address variable, and generates a second
target address by data mapping data stored in an address look-up table
memory. Subsequently, a row buffer memory accesses data corresponding to
a first scan line based on the first target address, and accesses data
corresponding to a second scan line based on the second target address.

Claims:

1. A method for driving a display device comprising:an address counter
generating a plurality of address variables according to data of a scan
line of a plurality of scan lines on a display panel;an address mapping
circuit address mapping the address variable generated by the address
counter to generate a corresponding first target address;the address
mapping circuit address mapping data stored in an address look-up table
memory according to the address variables generated by the address
counter to generate a corresponding second target address;a row buffer
memory accessing data corresponding to a first scan line of the plurality
of scan lines according to the first target address;the row buffer memory
accessing data corresponding to a second scan line of the plurality of
scan lines according to the second target address;the row buffer memory
accessing data corresponding to the first scan line according to the
address variables generated by the address counter; andthe row buffer
memory accessing data corresponding to the second scan line according to
data stored in the address look-up table memory.

2. The method of claim 1 further comprising:storing the first target
address, the second target address and the address variables into the
address look-up table memory.

3. The method of claim 1, wherein the address counter generates
corresponding 2n address variables according to the first scan line
including 2n bytes.

4. The method of claim 3 further comprising:the address mapping circuit
subtracting n from the address variable of the 2n address variables to
generate a corresponding parameter when the address variable is between n
and 2n;the address mapping circuit right shifting the parameter (m+1)
bits to generate the first target address when all of the m least
significant bits of the parameter represented in binary form are 1 and
the (m+1)th least significant bit is 0; andthe address mapping
circuit right shifting the parameter 1 bit to generate the first target
address when the least significant bit of the parameter represented in
binary form is 0.

5. The method of claim 4 further comprising:determining a value of the
least significant bit when the parameter is represented in binary form.

6. The method of claim 3 further comprising:reading out data stored in the
address look-up table memory corresponding to the first scan line and the
address variable of the 2n address variables, and subtracting n from the
data to generate a corresponding parameter when the address variable is
between n and 2n;the address mapping circuit right shifting the parameter
(m+1) bits to generate the first target address when all of the m least
significant bits of the parameter represented in binary form are 1 and
the (m+1)th least significant bit is 0; andthe address mapping
circuit right shifting the parameter 1 bit to generate the first target
address when the least significant bit of the parameter represented in
binary form is 0.

7. The method of claim 6 further comprising:determining a value of the
least significant bit when the parameter is represented in binary form.

8. The method of claim 3 further comprising:the address mapping circuit
subtracting n from the address variable of the 2n address variables to
generate a corresponding parameter when the address variable is between n
and 2n;the address mapping circuit right shifting the parameter (m+1)
bits to generate a first value, adding 1 to the first value to generate a
second value and subtracting the second value from the address variable
to generate the first target address when all of the m least significant
bits of the parameter represented in binary form are 1 and the
(m+1)th least significant bit is 0; andthe address mapping circuit
right shifting the parameter 1 bit to generate a third value, adding 1 to
the third value to generate a fourth value and subtracting the fourth
value from the address variable to generate the first target address when
the least significant bit of the parameter represented in binary form is
0.

9. The method of claim 8 further comprising:determining a value of the
least significant bit when the parameter is represented in binary form.

10. The method of claim 3 further comprising:reading out data stored in
the address look-up table memory corresponding to the first scan line and
the address variable of the 2n address variables, and subtracting n from
the data to generate a corresponding parameter when the address variable
is between n and 2n;the address mapping circuit right shifting the
parameter (m+1) bits to generate a first value, adding 1 to the first
value to generate a second value and subtracting the second value from
the address variable to generate the first target address when all of the
m least significant bits of the parameter represented in binary form are
1 and the (m+1)th least significant bit is 0; andthe address mapping
circuit right shifting the parameter 1 bit to generate a third value,
adding 1 to the third value to generate a fourth value and subtracting
the fourth value from the address variable to generate the first target
address when the least significant bit of the parameter represented in
binary form is 0.

11. The method of claim 10 further comprising:determining a value of the
least significant bit when the parameter is represented in binary form.

12. The method of claim 1 further comprising:the row buffer memory
outputting data corresponding to the first and the second scan line to
the display panel.

13. The method of claim 1 further comprising:generating data corresponding
to the first and the second scan line.

14. A display device using a low capacity row buffer memory comprising:a
display panel having a plurality of scan lines; anda timing controller
comprising:an address counter for generating a corresponding address
variable according to data of a scan line;an address look-up table memory
for storing look-up table data;an address mapping circuit for address
mapping the address variable to generate a corresponding first target
address, and generating a corresponding second target address according
to the address variable and the look-up table data stored in the address
look-up table memory; anda row buffer memory for storing the first target
address, the second target address and the address variable.

15. The display device of claim 14, wherein the display panel further
comprises a plurality of data lines.

16. The display device of claim 14, wherein the address counter is an
incremental counter.

Description:

BACKGROUND OF THE INVENTION

[0001]1. Field of the Invention

[0002]The present invention relates to a display device and related
driving method, and more particularly, to a display device and related
driving method using a low capacity row buffer memory.

[0005]Please refer to FIG. 1. FIG. 1 is a schematic diagram of a prior art
LCD display device 10. The LCD display device 10 includes an LCD panel 12
and a timing controller 14. The LCD panel 12 includes a plurality of data
lines D1-D2n and a plurality of scan lines G1-Gm, and
is divided into a front port and a back port. The data lines
D1-Dn are disposed on the front port of the LCD panel 12, while
the data lines Dn+1-D2n are disposed on the back port of the
LCD panel 12. Moreover, at each intersection of the data lines and the
scan lines, a pixel unit (shown as a dot in FIG. 1) is installed for
displaying images.

[0006]With increasing demands of large-size applications, the number of
the data lines and the scan lines also increases. Thus, in order to drive
the LCD panel 12 more efficiently, the timing controller 14 can generate
driving signals respectively corresponding to the front port and the back
port. The timing controller 14 includes a row buffer controller 16 and a
row buffer memory 18. The row buffer controller 16 is utilized for
receiving pixel input data DIN. The pixel input data DIN
includes odd-numbered pixel input data DIN--ODD and
even-numbered pixel input data DIN--EVEN, and is
respectively stored at corresponding addresses of the row buffer memory
18. When outputting data to different pixels of a scan line, the row
buffer controller 16 can read out the data stored at the corresponding
addresses of the row buffer memory 18 to generate front port pixel output
data DOUT--FRONT corresponding to the former half pixels
of the scan line and back port pixel output data
DOUT--BACK corresponding to the later half pixels of the
scan line. Therefore, the timing controller 14 can output data to the
pixel units of the scan line in sequence with a forward manner, that
means, the front port pixel output data DOUT--FRONT is
orderly outputted to the data line D1-Dn, while the back port
pixel output data DOUT--BACK is orderly outputted to the
data line Dn+1-D2n. A dashed arrow in FIG. 1 represents the
order of the output data.

[0007]Please refer to FIG. 2. FIG. 2 is a schematic diagram of the prior
art LCD display device 10 when outputting data in the forward manner.
Assuming that the LCD panel 12 includes 1280 data lines, i.e. each scan
line includes 1280 pixel units, the pixel input data DIN thus
includes data D1-D1280, among which the odd-numbered pixel
input data DIN--ODD includes the data D1, D3 . .
. D1279 and the even-numbered pixel input data
DIN--EVEN includes the data D2, D4 . . .
D1280. Meanwhile, the front port pixel output data
DOUT--FRONT includes the data D1-D640, and the
back port pixel output data DOUT--BACK includes the data
D641-D1280. At first, the prior art LCD display device 10 reads
in the data D1-D1280 to corresponding addresses of the row
buffer memory 18 in order. When outputting data in the forward manner,
after the last data D640 of the front port pixel output data
DOUT--FRONT is read in, the first data D641 of the
back port pixel output data DOUT--BACK is then read in. At
this time, the timing controller 14 can output the data to the LCD panel
12 with the order D1-D641-D2-D642- . . .
-D640-D1280.

[0008]Please refer to FIG. 3. FIG. 3 is a schematic diagram of a prior art
LCD display device 30. The LCD display device 30 includes an LCD panel 32
and a timing controller 34. The LCD panel 32 includes a plurality of data
lines D1-D2n and a plurality of scan lines G1-Gm, and
is divided into a front port and a back port. The data lines
D1-Dn are disposed on the front port of the LCD panel 32, while
the data lines Dn+1-D2n are disposed on the back port of the
LCD panel 32. Moreover, at each intersection of the data lines and the
scan lines, a pixel unit (shown as a dot in FIG. 3) is installed for
displaying images. The timing controller 34 includes a row buffer
controller 36 and a row buffer memory 38. Compared with the LCD display
device 10 outputting data with the forward manner, the LCD display device
30 can output data to pixel units of a scan line in sequence with a
backward manner, that means, the front port pixel output data
DOUT--FRONT is orderly outputted to the data lines
Dn-D1, and the back port pixel output data
DOUT--BACK is orderly outputted to the data lines
Dn+1-D2n. A dashed arrow in FIG. 3 represents the order of the
output data.

[0009]Please refer to FIG. 4. FIG. 4 is a schematic diagram of the prior
art LCD display device 30 when outputting data in the backward manner.
Assuming that the LCD panel 32 includes 1280 data lines, i.e. each scan
line includes 1280 pixel units, the pixel input data DIN thus
includes data D1-D1280, among which the odd-numbered pixel
input data DIN--ODD includes the data D1, D3 . .
. D1279 and the even-numbered pixel input data
DIN--EVEN includes D2, D4 . . . D1280.
Meanwhile, the front port pixel output data DOUT--FRONT
includes the data D1-D640, and the back port pixel output data
DOUT--BACK includes the data D641-D1280. At
first, the prior art LCD display device 30 reads in the data
D1-D1280 to corresponding addresses of the row buffer memory 38
in order. When outputting data in the backward manner, after the last
data D640 of the front port pixel output data
DOUT--FRONT is read in, the first data D641 of the
back port pixel output data DOUT--BACK is then read in. At
this time, the timing controller 34 can output the data to the LCD panel
32 with the order D640-D641-D639-D642- . . .
-D1-D1280. Since when outputting the front port pixel output
data, the data that is read in much earlier is outputted much later, so
that the row buffer memory 38 with a large capacity needs to be used for
the prior art LCD display device 30.

SUMMARY OF THE INVENTION

[0010]It is therefore a primary objective of the present invention to
provide a display device and related driving method using a low capacity
row buffer memory.

[0011]The present invention discloses a method for driving a display
device. The method includes an address counter generating a plurality of
address variables according to data of a scan line of a plurality of scan
lines on a display panel. An address mapping circuit address maps the
address variable generated by the address counter to generate a
corresponding first target address. The address mapping circuit also
address maps data stored in an address look-up table memory according to
the address variables generated by the address counter to generate a
corresponding second target address. A row buffer memory accesses data
corresponding to a first scan line of the plurality of scan lines
according to the first target address and the row buffer memory accesses
data corresponding to a second scan line of the plurality of scan lines
according to the second target address. The row buffer memory also
accesses data corresponding to the first scan line according to the
address variables generated by the address counter and the row buffer
memory accesses data corresponding to the second scan line according to
data stored in the address look-up table memory.

[0012]The present invention further discloses a display device using a low
capacity row buffer memory. The display device includes a display panel
having a plurality of scan lines. A timing controller includes an address
counter for generating a corresponding address variable according to data
of a scan line. An address look-up table memory is included for storing
look-up table data. An address mapping circuit for address mapping the
address variable to generates a corresponding first target address, and
generates a corresponding second target address according to the address
variable and the look-up table data stored in the address look-up table
memory. A row buffer memory is utilized for storing the first target
address, the second target address and the address variable.

[0013]These and other objectives of the present invention will no doubt
become obvious to those of ordinary skill in the art after reading the
following detailed description of the preferred embodiment that is
illustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a schematic diagram of a prior art LCD display device.

[0015]FIG. 2 is a schematic diagram of the prior art LCD display device
when outputting data in the forward manner.

[0016]FIG. 3 is a schematic diagram of a prior art LCD display device.

[0017]FIG. 4 is a schematic diagram of the prior art LCD display device
when outputting data in the backward manner.

[0018]FIG. 5 is a schematic diagram of an LCD display device of the
present invention.

[0019]FIG. 6 is a schematic diagram of signals of the present invention
LCD display device when in operation.

[0020]FIG. 7 illustrates relation between the address variable generated
by the address counter and addresses of input/output data stored in the
row buffer memory when driving the first scan line in the forward manner.

[0021]FIG. 8 illustrates relation between the address variable x generated
by the address counter and addresses of input/output data stored in the
row buffer memory when driving the other scan line in the forward manner.

[0022]FIG. 9 illustrates relation between the address variable x generated
by the address counter and addresses of input/output data stored in the
row buffer memory when driving the first scan line in the backward
manner.

[0023]FIG. 10 illustrates relation between the address variable x
generated by the address counter and addresses of input/output data
stored in the row buffer memory when driving the other scan line in the
backward manner.

DETAILED DESCRIPTION

[0024]Please refer to FIG. 5. FIG. 5 is a schematic diagram of an LCD
display device 50 of the present invention. The LCD display device 50
includes an LCD panel 52 and a timing controller 54. The timing
controller 54 includes an address counter 62, an address mapping circuit
64, an address look-up table memory 66 and a row buffer memory 68. The
address counter 62 can generate a corresponding address variable x
according to the number of pixels included in a scan line of a plurality
of scan lines. The address mapping circuit 64 can perform address mapping
for the address variable x. The address look-up table memory 66 can
receive and store the address variable x generated by the address counter
62 at a terminal A, can receive and store output data of the address
mapping circuit 64 at a terminal D, and can generate output data LUT(x,
y) at a terminal Q. The row buffer memory 68 can receive input data
DIN corresponding to display images at a terminal D, can store the
input data DIN according to signals received by a terminal A, and
can generate output data DOUT to the LCD panel 52 at a terminal Q.
Node 1-6 in FIG. 5 are utilized for defining data transmission path of
the LCD display device 50 in different operational states, and the
details will be discussed in the following.

[0025]Please refer to FIG. 6. FIG. 6 is a schematic diagram of signals of
the present invention LCD display device 50 when in operation. In FIG. 6,
VSYNC, DATA_IN and DATA_OUT respectively represent waveforms of a
horizontal synchronization signal, the input data DIN and the output
data DOUT. The LCD display device 50 includes four operation states:
state 1 represents a first half of input data of a first scan line (the
first scan line after the horizontal synchronization signal VSYNC is
triggered); state 2 represents a later half of input data of the first
scan line, and also represents a first half of output data of the first
scan line simultaneously; state 3 represents a first half of input data
of an other scan line; and state 4 represents an other state of input
data and output data of the other scan line.

[0026]When the LCD display device 50 is operated in state 1, the data
transmission path in FIG. 5 is node 1→node 4→node 5. At
this time, the address variable x is not performed as address mapping,
but is directly transmitted to the A terminal of the row buffer memory 68
as a target address for accessing the row buffer memory 68. Meanwhile,
the address variable x is also stored into the address look-up table
memory 66 through the A terminal of the address look-up table memory 66.

[0027]When the LCD display device 50 is operated in state 2, the data
transmission path in FIG. 5 is node 1→node 2→node
3→node 4→node 5. At first, the address mapping circuit 64
performs address mapping for the address variable x to generate a
corresponding target address, and then the corresponding target address
is transmitted to the A terminal of the row buffer memory 68 for reading
out the data accordingly. Meanwhile, the target address is stored into
the address look-up table memory 66 through the D terminal of the address
look-up table memory 66.

[0028]When the LCD display device 50 is operated in state 3, the data
transmission path in FIG. 5 is node 6→node 5. In this case,
instead of performing address mapping, the data LUT(x, y) stored in the
address look-up table memory 66 is directly read out as a target address
for accessing the row buffer memory 68, wherein x represents the address
variable generated by the address counter 62 and y represents the scan
line.

[0029]When the LCD display device 50 is operated in state 4, the data
transmission path in FIG. 5 is node 6→node 2→node
3→node 4→node 5. Firstly reading out the data LUT(x, y)
stored in the address look-up table memory 66, the address mapping
circuit 64 then performs address mapping for the data LUT(x, y) to
generate a corresponding target address. After that, the target address
is transmitted to the A terminal of the row buffer memory 68 for reading
out the data accordingly. Meanwhile, the target address is stored into
the address look-up table memory 66 through the D terminal of the address
look-up table memory 66.

[0030]Next, the manner that the address mapping circuit 64 of the present
invention performs address mapping is illustrated. Assuming that a scan
line can display 2n bytes, and since I byte includes 4 pixels, a scan
line thus includes 8n pixels. Please refer to FIG. 7 and FIG. 8. FIG. 7
illustrates the relation between the address variable x generated by the
address counter 62 and addresses of input/output data stored in the row
buffer memory 68 when driving the first scan line (y=0) in the forward
manner, while FIG. 8 illustrates the relation between the address
variable x generated by the address counter 62 and addresses of
input/output data stored in the row buffer memory 68 when driving the
other scan line (such as: y=1) in the forward manner. If a scan line
includes 8n pixels, data displayed by the scan line includes n front port
data D0˜Dn-1 and n back port data
Dn˜D2n-1, which respectively corresponds to the 2n bytes.
To simplify matters, the embodiments shown in FIG. 7 and FIG. 8 takes
n=16 for example. The address counter 62 of the present invention can be
an incremental counter, and can generate a corresponding address variable
x according to each read-in data respectively. If driving the first scan
line in the forward manner, when the data D0˜Dn+15 is in
order read in to addresses 0-(n+15) of the row buffer memory 68, the
value of the corresponding address variable x also increases from 0 to
(n+15) respectively. Meanwhile, the data with the order
D0-Dn-D1-Dn+1- . . . -D15-Dn+15 is
outputted to the LCD panel 52. When the address variable x equals n
(x=n), the first output data D0 can be read out from the address 0
of the row buffer memory 68, and thus the address 0 can be used for
storing the next read-in data Dn; when the address variable x equals
n+1 (x=n+1), the next output data Dn can be read out from the
address 0 of the row buffer memory 68, and thus the address 0 can then be
used for storing a next read-in data Dn+1; when the address variable
x equals n+2 (x=n+2), the next output data D1 can be read out from
the address 1 of the row buffer memory 68, and thus the address 1 can be
used for storing the next read-in data Dn+2; when the address
variable x equals n+3 (x=n+3), the next output data Dn+1 can be read
out from the address 0 of the row buffer memory 68, and thus the address
0 can then be used for storing the next read-in data Dn+3. The rest
are all completed in like manners.

[0031]As shown in the second half of FIG. 7, for the even-numbered back
port data (Dn, Dn+2 . . . Dn+14) of the back port data of
the first scan line, the address for reading in the (n+2s)th byte
and the address for reading out the sth byte are the same, and that
is:

LUT(n+2s,y)=LUT(s,y), 0≦s<(n/2) Formula 1

[0032]Similarly, for the odd-numbered back port data (Dn+1, Dn+3
. . . D2n+1) of the back port data of the first scan line, the
address for reading in the (n+2s+1)th byte and the address for
reading out the (n+s)th byte are the same, and that is:

LUT(n+2s+1,y)=LUT(n+s,y), 0≦s<(n/2) Formula 2

[0033]If setting s as 2t, Formula 2 and Formula 1 can be merged as
follows:

LUT(n+4t+1,y)=LUT(n+2t,y)=LUT(t,y), 0≦t<(n/4) Formula 3

[0034]If setting s as 4u+1, Formula 2 and Formula 3 can be merged as
follows:

LUT(n+8u+3,y)=LUT(n+4u+1,y)=LUT(u,y), 0≦u<(n/8) Formula 4

[0035]If setting s as 8v+3, Formula 2 and Formula 4 can be merged as
follows:

[0037]When n is equal to 16 (n=16), the address variable x represented in
binary form at most includes 4 bits, and thus the function h(x) can be
expressed by Verilog, a hardware description language (HDL), as follows:

[0038]wherein "'b" represents the address variable x expressed in binary
form, "?" represents arbitrary bits, and ">>" represents right
shifting. Discriminant 1 to Discriminant 4 respectively corresponds to
Formula 1, Formula 3, Formula 4 and Formula 5. Simply speaking, when the
least significant bit of the address variable x is 1, the value of the
function h(x) is equal to the value that x is right shifted one bit as
Formula 1 and Discriminant 1 indicate; when the last two bits of the
address variable x are "01", the value of the function h(x) is equal to
the value that x is right shifted two bits as Formula 3 and Discriminant
2 indicate; when the last three bits of the address variable x is "011",
the value of the function h(x) is equal to the value that x is right
shifted three bits as Formula 4 and Discriminant 3 indicate; and when the
address variable x is equal to "0111", the value of the function h(x) is
equal to the value that x is right shifted four bits as Formula 5 and
Discriminant 4 indicates.

[0039]When n is equal to other values, the address variable x represented
in binary form may includes more bits, and thus the function h(x) can be
generalized as:

[0040]while x[0]=1

[0041]x=x>>1;

[0042]h(x)=x>>1

[0043]wherein x[0] represents the least significant bit of the address
variable x expressed in binary form. Simply speaking, when the least
significant bit of the address variable x is equal to 1, the address
variable x is right shifted until the least significant bit is no longer
equal to 1, and the value of the function h(x) is then equal to the value
that the right-shifted address variable x if right shifted one bit
further; on the other hand, when the least significant bit of the address
variable x is not equal to 1, the value of the function h(x) is equal to
the value that the address variable x if right shifted one bit.

[0044]As n≦x<2n, form Formula 6, a Formula 7 can be obtained:

LUT(n+x,y)=LUT(h(x),y) Formula 7

[0045]As shown in the first half of FIG. 8, for the even-numbered front
port data (D0, D2 . . . D14) of the front port data of an
other scan line (such as: y=1), the address for reading in the 2sth
byte of the yth scan line is the same as the address for reading out
the (n/2+s)th byte of the (y-1)th scan line, and thus:

LUT(2s,y)=LUT(n/2+s,y-1), 0≦s<(n/2) Formula 8

[0046]Similarly, for the odd-numbered front port data (D1, D3 . . . D15)
of the front port data of the other scan line (such as: y=1), the address
for reading in the (2s+1)th byte of the yth scan line is the
same as the address for reading out the (n/2+s)th byte of the
(y-1)th scan line, and thus:

LUT(2s+1,y)=LUT(n/2+s,y-1), 0≦s<(n/2) Formula 9

[0047]From Formula 9 and Formula 6, a Formula 10 can be obtained as
follows:

LUT(2s+1,y)=LUT(h(n/2+s),y-1) Formula 10

[0048]For the front port data of a scan line, 0≦x<n, and thus a
Formula 11 can be obtained from Formula 8 and Formula 10 as follows:

[0051]The form of Discriminant 7-Discriminant 10 corresponding to the
function f(x) is similar to that of Discriminant 1-Discriminant 4
corresponding to the function h(x), and thus the function f(x) can be
represented as follows:

f(x)=h(n+x) Formula 12

[0052]As shown in the first half of FIG. 7, for the front port data
(D0˜D15) of the first scan line (y=0), there are no
initial values in the address look-up table memory 66. In this case, the
LCD display device 50 is operated in state 1, and the address calculation
path is node 1→node 4→node 5. Thus, the address variable x
is not performed as address mapping, but is directly utilized as a target
address ADD_f1 for accessing the row buffer memory 68. The target address
ADD_f1 is shown as follows:

ADD--f1=LUT(x,0)=x, 0≦x<n Formula 13

[0053]As shown in the second half of FIG. 7, for the back port data
(Dn˜Dn+15) of the first scan line (y=0), the LCD display
device 50 is operated in state 2 and the address calculation path is node
1→node 2→node 3→node 4→node 5. In this case,
the address mapping circuit 64 performs address mapping for the address
variable x to generate a corresponding target address ADD_f2. The target
address ADD_f2 can be obtained from Formula 7 and Formula 13 as:

ADD--f2=LUT(h(x-n),0)=h(x-n), n≦x<2n Formula 14

[0054]As shown in the first half of FIG. 8, for the front port data
(D0˜D15) of an other scan line (such as: y=1), the LCD
display device 50 is operated in state 3 and the address calculation path
is node 6--node 5. In this case, instead of performing address mapping,
the data LUT(x, y) stored in the address look-up table memory 66 is
directly read in as a target address ADD_f3 for accessing the row buffer
memory 68. The target address ADD_f3 is shown as follows:

ADD--f3=LUT(x,y), 0≦x<n Formula 15

[0055]As shown in the second half of FIG. 8, for the back port data
(Dn˜Dn+15) of the other scan line (such as: y=1), the LCD
display device 50 is operated in state 4 and the address calculation path
is node 6→node 2→node 3→node 4→node 5. In
this case, the data LUT(x, y) stored in the address look-up table memory
66 is firstly read out, and then the address mapping circuit 64 performs
address mapping for the data LUT(x, y) to generate a corresponding target
address ADD_f4. The target address ADD_f4 can be derived in the
following:

[0056]If 0≦x<n, from Formula 11 and Formula 13, a Formula 16 can
be obtained as:

[0059]Therefore, when the LCD display device 50 is operated in state 4,
the target address ADD_f4 can be obtained from Formula 12, Formula 16 and
Formula 18, and can be expressed as:

ADD--f4=LUT(x,y)=f(LUT(h(x,y-1))=h(LUT(x,y-1)+n), n≦x<2n
Formula 19

[0060]Please refer to FIG. 9 and FIG. 10. FIG. 9 illustrates a relation
between the address variable x generated by the address counter 62 and
addresses of the input/output data stored in the row buffer memory 68
when driving the first scan line (y=0) in the backward manner; and FIG.
10 illustrates a relation between the address variable x generated by the
address counter 62 and addresses of the input/output data stored in the
row buffer memory 68 when driving the other scan line (such as: y=1) in
the backward manner. If a scan line includes 8n pixels, data displayed by
the scan line includes n front port data D0-Dn-1 and n back
port data Dn-D2n-1, which respectively corresponds to the 2n
bytes. To simplify matters, the embodiments shown in FIG. 9 and FIG. 10
take n=16 for example. If driving the first scan line in the backward
manner, when the data D0-Dn+15 is in order read in to addresses
0-(n+15) of the row buffer memory 68, the value of the corresponding
address variable x also increases from 0 to (n+15) respectively.
Meanwhile, the data is outputted to the LCD panel 52 with the order
D15-Dn-D14-Dn+1- . . . -D0-Dn+15. When the
address variable x equals n (x=n), the first output data D15 can be
read out from the address 15 of the row buffer memory 68, and thus the
address 15 can be used for storing the next read-in data Dn; when
the address variable x equals n+1 (x=n+1), the next output data Dn
can be read out from the address 15 of the row buffer memory 68, and thus
the address 15 can then be used for storing the next read-in data
Dn+1; when the address variable x equals n+2 (x=n+2), a next output
data D14 can be read out from the address 14 of the row buffer
memory 68, and thus the address 14 can be used for storing the next
read-in data Dn+2; when the address variable x equals n+3 (x=n+3),
the next output data Dn+1 can be read out form the address 15 of the
row buffer memory 68, and thus the address 15 can then be used for
storing the next read-in data Dn+3. The rest are all completed in
like manners.

[0061]As shown in the second half of FIG. 9, for the even-numbered back
port data (Dn, Dn+2 . . . Dn+14) of the back port data of
the first scan line, the address for reading in the (n+2s)th byte
and the address for reading out the (n-s-1)th byte are the same:

LUT(n+2s,y)=LUT((n-1)-s,y), 0≦s<(n/2) Formula 20

[0062]Similarly, for the odd-numbered back port data (Dn+1, Dn+3
. . . D2n+1) of the back port data of the first scan line, the
address for reading in the (n+2s+1)th byte and the address for
reading out the (n+s)th byte are the same:

LUT(n+2s+1,y)=LUT(n+s,y), 0≦s<(n/2) Formula 21

[0063]According to a derivation process of Formula 1 to Formula 6, a
Formula 22 can be obtained from Formula 20 and Formula 21 as:

LUT(n+x,y)=LUT((n-1)-h(x),y), 0≦s<(n/2) Formula 22

[0064]As shown in the first half of FIG. 10, for the even-numbered front
port data (D0, D2 . . . D14) of the front port data of an
other scan line (such as: y=1), the address for reading in the 2sth
byte of the yth scan line is the same as the address for reading out
the (n/2-s-1)th byte of the (y-1)th scan line, and thus a
Formula 23 can be obtained as:

LUT(2s,y)=LUT((n-1)-h(n/2+s),y-1), 0≦s<(n/2) Formula 23

[0065]Similarly, for the odd-numbered front port data (D1, D3 .
. . D15) of the front port data of the other scan line (such as:
y=1), the address for reading in the (2s+1)th byte of the yth
scan line is the same as the address for reading out the (n/2+s)th
byte of the (y-1)th scan line, and thus a Formula 24 can be obtained
as:

LUT(2s+1,y)=LUT(n/2+s,y-1), 0≦s<(n/2) Formula 24

[0066]From Formula 22 and Formula 24, a Formula 25 can be obtained as:

LUT(2s+1,y)=LUT(n/2+s,y-1)=LUT((n-1)-h(n/2+s),y-1) Formula 25

[0067]From Formula 23 and Formula 25, a Formula 26 can be obtained as:

LUT(x,y)=LUT((n-1)-f(x),y-1) Formula 26

[0068]Denoting Formula 22 and Formula 26 with the functions H(x) and F(x)
as:

LUT(n+x,y)=LUT(H(x),y) Formula 27

LUT(x,y)=LUT(F(x),y-1) Formula 28

[0069]wherein H(x)=(n-1)-h(x), and F(x)=(n-1)-f(x)

[0070]From Formula 12, we can obtain:

F(x)=H(n+x)

[0071]As shown in the first half of FIG. 9, for the front port data
(D0-D15) of the first scan line (y=0), there are no initial
values in the address look-up table memory 66. In this case, the LCD
display device 50 is operated in state 1, and the address calculation
path is node 1→node 4→node 5. Thus, the address variable x
is not performed address mapping, but is directly utilized as a target
address ADD_r1 for accessing the row buffer memory 68. The target address
ADD_r1 is shown as follows:

ADD--r1=LUT(x,0)=x, 0≦x<n Formula 29

[0072]As shown in the second half of FIG. 9, for the back port data
(Dn-Dn+15) of the first scan line (y=0), the LCD display device
50 is operated in state 2 and the address calculation path is node
1→node 2→node 3→node 4→node 5. In this case,
the address mapping circuit 64 performs address mapping for the address
variable x to generate a corresponding target address ADD_r2. The target
address ADD_r2 can be obtained from Formula 22 and Formula 27 as:

ADD--r2=LUT(x,0)=H(x-n)=(n-1)-h(x-n), n≦x<2n Formula 30

[0073]As shown in the first half of FIG. 10, for the front port data
(D0-D15) of an other scan line (such as: y=1), the LCD display
device 50 is operated in state 3 and the address calculation path is node
6→node 5. In this case, instead of performing address mapping, the
data LUT(x, y) stored in the address look-up table memory 66 is directly
read in as a target address ADD_r3 for accessing the row buffer memory
68. The target address ADD_r3 is shown as follows:

ADD--r3=LUT(x,y), 0≦x<n Formula 31

[0074]As shown in the second half of FIG. 10, for the back port data
(Dn-Dn+15) of the other scan line (such as: y=1), the LCD
display device 50 is operated in state 4 and the address calculation path
is node 6→node 2→node 3→node 4→node 5. In
this case, the data LUT(x, y) stored in the address look-up table memory
66 is firstly read out, and then the address mapping circuit 64 performs
address mapping for the LUT(x, y) to generate a corresponding target
address ADD_r4. The target address ADD_r4 can be derived as follows:

[0075]According to the embodiments in FIG. 8 to FIG. 10, when driving the
LCD display device 50 to operate in different states with the
forward/backward manners, the manners that the address mapping circuit 64
performs address mapping can be summarized as follows:

[0076]Corresponding to the forward driving manner:

state 1: ADD_f1=x, 0≦x<n Formula 13

state 2: ADD--f2=h(x-n), n≦x<2n Formula 14

state 3: ADD--f3=LUT(x,y), 0≦x<n Formula 15

state 4: ADD--f4=h(LUT(x,y-1)+n), n≦x<2n Formula 19

[0077]Corresponding to the backward driving manner:

state 1: ADD_r1=x, 0≦x<n Formula 29

state 2: ADD--r2=(n-1)-h(x-n), n≦x<2n Formula 30

state 3: ADD--r3=LUT(x,y), 0≦x<n Formula 31

state 4: ADD--r4=(n-1)-h(LUT(x,y-1)+n), n≦x<2n Formula 33

[0078]Therefore, the present invention can generate the target addresses
for accessing the row buffer memory 68 according to the different
operation states of the LCD display device 50, and can utilize the
address mapping circuit 64 and the address look-up table memory 66 for
updating the target addresses, so that the row buffer memory 68 with a
large capacity is not needed to be used.

[0079]Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made while
retaining the teachings of the invention.

Patent applications by Hsiao-Ming Huang, Kao-Hsiung City TW

Patent applications in class Frame, field or scan rate conversion

Patent applications in all subclasses Frame, field or scan rate conversion