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The Transfer Complete Flag (TCF) interrupt gets raised after each writeto the TX FIFO (PUSHR) which means that it is not possible to devise atransfer procedure that makes full utilization of the FIFO depth (4entries on most controllers, 16 entries on some).

On the other hand, XSPI mode has a feature called "command cycling",which allows a single TX command to be run for a pre-specified number ofTX words. When the command cycle ends, the Command Transfer CompleteFlag bit asserts and raises an interrupt. The advantage in this mode isthat the TX FIFO can be better utilized (more words can be batched atonce).

Other changes brought by this patch: - The dspi->rx_end variable has been removed, since now the dspi_fifo_write function sets up dspi->words_in_flight, so dspi_fifo_read knows how much to read without overrunning the RX buffer. - Stop using poll mode unconditionally for TCFQ mode, since XSPI mode is a little less efficient than that, and so, poll mode doesn't bring as many improvements for XSPI. - Stop relying on the hardware transfer counter (SPI_TCR_GET_TCNT) and instead increment the message->actual_length based on the newly introduced dspi->words_in_flight variable. - The CTARE register is now written in the hotpath instead of just at transfer init time, since it contains the DTCP field (transfer preload - the counter indicating how many txdata words will follow), which is a dynamic value.

Due to the fact that the Chip Select toggling setting is part of thecommand written to the TX FIFO, the ending word of each buffer needs tobe sent via its own TX command, so that we have a chance to emit a1-word command with deasserted PCS.

- if (dspi->len > 0)+ /*+ * The only time when the PCS doesn't need continuation after this word+ * is when it's last. We need to look ahead, because we actually call+ * dspi_pop_tx (the function that decrements dspi->len) _after_+ * dspi_pushr_cmd_write with XSPI mode. As for how much in advance? One+ * word is enough. If there's more to transmit than that,+ * dspi_xspi_write will know to split the FIFO writes in 2, and+ * generate a new PUSHR command with the final word that will have PCS+ * deasserted (not continued) here.+ */+ if (dspi->len > dspi->bytes_per_word) cmd |= SPI_PUSHR_CMD_CONT; regmap_write(dspi->regmap_pushr, PUSHR_CMD, cmd); }@@ -620,93 +625,115 @@ static void dspi_pushr_txdata_write(struct fsl_dspi *dspi, u16 txdata) regmap_write(dspi->regmap_pushr, PUSHR_TX, txdata); }

-static void dspi_tcfq_read(struct fsl_dspi *dspi)-{- dspi_push_rx(dspi, dspi_popr_read(dspi));+ dspi->words_in_flight = dspi->len / dspi->bytes_per_word;++ if (dspi->words_in_flight > num_fifo_entries)+ dspi->words_in_flight = num_fifo_entries;++ bytes_in_flight = dspi->words_in_flight * dspi->bytes_per_word;++ /*+ * If the PCS needs to de-assert (i.e. we're at the end of the buffer+ * and cs_change does not want the PCS to stay on), then we need a new+ * PUSHR command, since this one (for the body of the buffer)+ * necessarily has the CONT bit set.+ * So send one word less during this go, to force a split and a command+ * with a single word next time, when CONT will be unset.+ */+ if (bytes_in_flight == dspi->len && dspi->words_in_flight > 1 &&+ !(dspi->tx_cmd & SPI_PUSHR_CMD_CONT))+ dspi->words_in_flight--;++ dspi_xspi_write(dspi, dspi->words_in_flight); }