Summary

Posted: Oct 23, 2018

Role Number: 200001832

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices — strengthening our dedication to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple products. Dynamic, smart people and inspiring, innovative technologies are the norm here. Will you join us in crafting solutions that do not yet exist?
As a member of Mixed-Signal design team, you will create and support innovative design methodology and customize and automate CAD flows for advanced Mixed-Signal IP designs. The design flows are used by multiple different IPs of multiple projects at multiple sites. Strong knowledge of Synthesis, P&R, Timing, Simulation CAD flows, EDA tools, UPF, algorithm, scripting (TCL/Perl/Python) and Makefiles is a requirement. You will collaborate with RTL, PD and timing design teams, CAD team, and EDA vendors. Good interpersonal skill is critical. Excellent verbal and written communication in English is required.

- We are looking for a self-motivated, dedicated problem solver. Strong interpersonal/communication skills are a requirement.

Description

As a team member of the Physical Design team, you will be involved with all aspects of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Provide innovative solutions to customize and improve quality and efficiency of mixed-signal design. Work with RTL and physical design teams to implement and customize design flows that are optimal for different IPs. Provide documentation, training and new-user-support. Responsible for diagnosis, resolution, regression of reported problems. Generate block/chip level static timing constraints. Create full chip floor-plan including pin placement, partitions and power grid. Develop and validate high performance low power clock network guidelines. Perform block level place and route and close the design to meet timing, area and power constraints. Generate and Implement ECOs to fix timing, noise and EM IR violations. Run Physical design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations to other designers. Participate in establishing CAD and physical design methodologies for correct by construction designs. Assist in flow development for chip integration.

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