a different means ofisolation—using dielectrics instead of conventional p-n junctions in reverse bias.

Benefits include fastertransistor switching speeds, protection from leakage current, as well as lower power consumption.

SOIfeaturesa thin layer of silicon on top of an insulator layer (frequently SiO2) that acts as a dielectricseparating the film of Si from the bulk substrate. Fabrication is a challenge sincethe top filmmust be

athin single-crystal Si film while the SiO2

dielectric is amorphous, which

poses many problems infabrication.1

Two industrially important fabrication methods will be discussed in this paper—the firstbeing SIMOX and a second method involving wafer bonding.

These methods of fabrication allowmicroelectronics manufacturers to push Moore’s law to the limit inthe miniaturization of devices.

technique of ion implantation in order to "inject" oxygen atoms into the silicon substrate. Hightemperature annealing follows which allowstheoxide

layer to distribute itself evenly as

a thin filmunderneath a monocrystalline silicon layer.

SIMOXhas been found to bevery suitable for commercial

purposes and is capable of yielding thin film layers with high quality uniformity and low defect density.6

SIMOX begins with ion implantation,which refers to theinjection of atoms into aspecific target.In thecase of SIMOX, the atoms being injected are oxygen atoms, and the target is the silicon substrate.

Ion implantation has been a technology present since 19525

and has been refined greatly so that it cansuit SOI fabrication.Gas is ionized and then accelerated

down a tube so that

oxygen ions can strike thesilicon wafer.

In general, the

number of atoms implanted

depends

on the dosage of incident ions as well asthe energy at which they strike the target.

These incident ions are accelerated through an electric fieldso that they can strike the wafer surface.Typical dosages for oxygen ions range from 1017

cm-2

to 1018

cm-2

while typical ion energies range from 50 keV to 200 keV.1

By varying the ion energy, the projectedrange of the oxygen

ions can be controlledto match the

desiredthickness of the surface silicon layer.

Operating temperatures for ion implantation need to remain high as to preserve themonocrystallinity of the

siliconsurface layer.

Incoming O+

ions bombard the Si lattice,

causing recoilwhich can then cause higher order displacements within the lattice. The net result can range from eithera defective region or even an amorphous region.Sufficientlyhigh dosages are necessary to helpcreatean amorphous

buried oxide layer

(BOX).Experiments show that temperatures of 500–

600

°C

are idealfor the SIMOX manufacturing process.1

Upon implanting oxygen atoms, the process of nucleation of SiO2

precipitates begins.

Thermodynamics governs the growth of these precipitates as theradialsize of these precipitatesdepends heavily on the temperature under which ion implantation is performed.

These precipitates aredriven to reduce their total free energy and so larger precipitates grow at the expense of smaller ones.

Coalescence may also occur when multiple precipitatescome into contact with each other. When thedensity of precipitates is high enough, the system may seek to lower the total free energy throughcoalescence.6

Coalescence

helps develop the desired BOX in the SOIstructure.

Side Effects of SIMOX

One of the consequences of the ion implantationprocess is the possibility of sputtering. Sputtering is a form ofphysical vapor deposition (PVD) that occurs when incidentatoms strike a target with enough energy todislodge theatoms in the lattice of the target.

In the case of SIMOX, O+

ions are sometimes capable of dislodging Si atoms or evenSiO2

molecules.6

Thus, controlling the dosage and incidention energy is critical to control the amount of sputtering.Sputteringis a form of erosion that will affect the thicknessof the

thickness of the film of SiO2

and surface layer silicon.

As a result, thedosage of incident oxygen ions as well as theincident energy needs

to be carefully controlled as they havesignificant effects upon the film thickness.

While sputtering has a receding effect on thethickness,ionimplantation itself has a swelling effect due totheadded presence of thenew ionsthat are implanted.

Figure2

demonstrates the effect of varying the dosage

at afixed temperature. A high enough dosage is required in ordertocreate a buried oxide layer, and this is indicated by thePage4

of8

Figure3:Temperature dependence of the Si/SiO2

interface in a hightemperature anneal for SIMOX.

[4]

critical dosage φc.Dosagesbelow this value are

too smallandareonlycapable offorming

precipitatesand lattice defects.

However, as the dosage increases, the crystallinity of the surface silicon layer beginsto suffer andswelling effects become more pronounced. At the same

time, the effects of sputteringbecomeincreasingly noticeable, resulting in a net thickness somewhat thinner than whatthe filmwouldhave been without the presence of sputtering.1

Ion implantation also causes significant damage

despite taking place at high temperatures. Thisis due to the collisions that the incident oxygen ions make

with the silicon lattice atoms that createFrenkel pairs.6

Vacancies are also scattered across the structure in addition tosilicon dioxideprecipitates.

with an abrupt interface with thesilicon crystal layers.Annealinghelpsto obtainthis

buried oxide layer (BOX)

by capitalizing on the principles ofdiffusion andthermodynamics.Hightemperatures help dissolve small oxideprecipitatescreatedfrom ionimplantation and also help redistributethe amorphous phase into a BOX.Thus, the

high temperature anneal

converts

theimplantedoxygenintoaSiO2

layer

and alsogives

the desired SOI structure

with abrupt interfaces between the silicon andsilicon dioxide.This can be shown in Figure3

which illustrates a high temperature anneal providing adesired SiO2/Si interface.It can be seen that insufficiently high temperatures will yieldpoor qualityinterfaces. Experiments have shown that 1350 °C is an optimal annealing

temperature.6

Additionally,annealing helpsto repair the damage in the silicon lattice caused by ion implantation. IonDefects in thesilicon lattice such as interstitial or vacancy defectsresult from ion implantation

and can hurt deviceperformance.

Proper annealing at high enough temperatures willrepair these lattice defects.

In thermal annealing it isonce againimportant to preserve themonocrystallinity of thesiliconsurface layer.The high temperature environment

may cause unintentional oxidation of the surface layerwhich results in thinning of that layer. One method that has been developed is to perform the annealingprocess in an environment that is not favorable foroxidation. Another method involves protecting thesurface silicon layer by using a capping layer.

Theimplementation of a capping layer also prevents someoxygen from being implanted into the BOX layer, resulting in a thinner layer than a wafer that does notfeature the capping layer.6

Variations in SIMOX Process

In order for SIMOX to be usedcommercially, it needs to feature cost efficient processes to favormass production.

The dosage of oxygen ions is directly related to the operating cost, and

subsequentlymuch research has been done in the field of lowering the oxygen ion dosage.Experiments have shownthat

at certain ion energies, doses below the critical

can yield high quality thin SOI films.

ThinBOX layershave their downsides too as there exists the possibility of thin silicon micropipes that can leak currentinto the bulk substrate.Methods such as internal oxidation (ITOX) have been used.1

Page5

of8

Figure4: Depiction of theBESOI

process.[1]

Another variation in the SIMOX process is the use of patterned buried oxide. Certain CMOSdevices do not require a BOX across the entire wafer, or sometimes a combination of bulk silicon andSOI is

desired.

A patterned oxygen implantation process can be performed followed by the ITOX processwhich helps smooth out the new lateral Si/SiO2

interfaces from the patterning.1

Overall, the cost of SIMOX is still high, and cost is one of the main challenges

in helpingproliferate this fabrication method.5

Wafer Bonding

The second method of fabrication of silicon-on-insulator chips that will be discussed is known aswafer bonding. Wafer bonding processes involve bonding two halves of wafers together to form

a finalstructure.

In order to create a bond between two surfaces, it would be ideal to createtwo flat, cleansurfaces so that the molecules can come sufficiently close enough for bonding. However, this is oftenimpractical as the costs are too high.

It

is much easier to rely on a chemically activated process

whichmakes the two bonding

surfaces more reactive7.

Hydrogen bonding is a phenomenon that can besuitable as long as hydrogen can be attached to these two surfaces.

Many chemicals can be used forthe

hydration

of the SiO2

surface, ranging

from water to acids and bases.

Water is a typically used moleculeand is discussed further.

The two surfaces are initially coated with OH groups and then fused together.Now, the temperature is raised in a heating

process thathelps evaporate water

while bonding the twowafers together. Approximately 75% of the water

is then lost by diffusing through the SiO2

layer.8

During

diffusion, some more silicon dioxide is formed

as oxygen reacts with the silicon lattice, freeing upadditional H2

gas. As temperatures surpass 800

°C,additional water leaves the bond interface, ultimatelyallowing

the silicon dioxide layers to fuse together. This process can be described by the equation:

Si–

OH + OH–

SI

Si–

O–

Si + H2O

More water is freed up helping add to additional thickness of the BOX as well as free hydrogen atomsthat escape via diffusion.7

The bonding step is only one crucial step in SOI fabrication by wafer bonding.

Processing stillneeds to be performed on these wafers to obtain the desired SOI structure with desired characteristics.

This is where several processes come intoplay.The industry uses several techniques that include bond-and-etchback SOI (BESOI), the Smart Cut™

process, and the ELTRAN™

process.1

These processes, for themost part, share many similarities, especially in the wafer bonding section of

fabrication, but they differin the post-processing techniques required to attain a desired film thickness.

BESOI

One of the methods of wafer bonding is known as abond-and-etchback SOI process (BESOI).

Thewafercan

firstbegrinded in a mechanical process and then polished usingchemical mechanical

polishing (CMP). However, is limited tofilms thicker than 5μm as mechanical processes becomesomewhat limited in the nano-scale regime.1

Etching can be usedto attain finer detail by including an

etch-stop

into the waferprior to bonding.

Since a chemically selective etch can beperformed, the etch-stop acts as a stop marker for the etchingprocess.Thus, after bonding, a selective etch can be applied tothe wafer that will etch away the undesired portions of thewafer, leaving a thin monocrystalline silicon surface film.

This isshown in Figure4

where the silicon above the etch-stop iseliminated after the BESOI process.

Unfortunately,

while etchingPage6

of8

Figure5: Depiction of the Smart Cut™ process

[1]

Figure6:XTEM of hydrogen platelets from implantation

[1]

is chemically selective and can effectively remote undesired material, contamination of the

etch-stopwith the silicon layer will occur.1

Thus, a more popular process, known as Smart Cut™ is being widelyused in the industry.

Smart Cut™

Process

Smart

Cut™

is thecommercial name for a specificprocess

of wafer bonding. Itfeatures hydrogen ion implantationwhich assists in slicing the siliconwafer. This process has grown tobecome a very popular form offabricating SOI wafers. Through ionimplantation, hydrogen atoms areimplanted into a silicon waferknown as the "seed" wafer. Thisseed wafer features a layer ofoxidized silicon which forms theSiO2. These hydrogen atoms helpproduce cavities within the siliconlattice. At the same time, a "handle wafer,"which features Si with a layer of silicon dioxide is prepared.Both wafers are cleaned to ensure a clean contact surface in bonding. Next, the "seed wafer" is flippedupside down in order to be bonded with the "handle wafer."

2,3

Figure5

illustrates the steps oftheSmart Cut™process, from hydrogen implantationall to the splitting of the seed wafer.

to dangling Si bonds toprevent the healing of these micro-cavities.Thesecavities grow

and build up until enough exist sothat the wafer plane

can be broken off by theapplication of force.7

In the end of Smart

Cut™

process, the"seed wafer" splits down the region of hydrogenion implantation. This process of mechanical splitting may feature some roughness. This can be fixedthrough polishing which produces aflat,clean cut surface.1

The newly bonded wafer is ready for furtherprocessing while the "seed wafer" can be reused to create additional wafers.

A major challenge that exists in theSmart Cut™process is to avoid blistering. Blistering occurswhen a small chunk of the silicon wafer breaks off as a result of pressure buildup. Much effort has beenplaced to reduce blistering, and one effective method has been to introduce a stiffener. The stiffenerhelps stiffen the top layer of the wafer and also helps by redirecting pressure across the wafer ratherthan upwards. In the case ofSmart Cut™, the handle wafer serves as the stiffener.1

There are many advantages of theSmart Cut™process, and one major factor is thedifferentiation between the seed and handle wafer. The seed wafer is the portion featuring the surfacesilicon layer and so it must feature high quality silicon with minimal lattice defects. On the other hand,the handle wafer acts as mechanical support, and can feature lower quality silicon.

Since the silicon filmPage7

of8

Figure7:Depiction of the ELTRAN process

using twolayers of porous silicon.

[1]

and buried oxide layer are typically thin relative to the handle wafer layer, only small amounts of highquality silicon are needed

per structure whereas in bulk silicon, the entire structure will need to be ofhigh quality materials. This helps reduce the amount ofhigh quality silicon processing needed, thuscutting down on processing time and cost.2,3

Furthermore, the ability

to control the Si film thickness andthe BOX layer thickness to the nanometer regime through hydrogen implantation makes the Smart Cut™

process very versatile.1

Finally, the versatility of the Smart Cut™ process as well as wafer bonding givesrise tothe name “Silicon-on-Anything,” as this technology allowswafers to be bonded onto manydifferentmaterials.

ELTRAN Process

Theepitaxial layer transfer orELTRAN

process is another commercially used process

used tocreate a thin layer of silicon.

This process relies onthe properties of porous silicon in

aiding the

cuttingofthe silicon wafer. Porous silicon is mechanicallyweak, but is capable of retaining the desiredmonocrystallinity.7

Using an electrochemical reaction,porous Si can be created by an etching process.Crystalline silicon can then be grown on top of thisporous layer and then later oxidized to form the seedwafer.Figure7

shows the use of two layers of poroussilicon. The interface between

the two porous layershas some interfacial stress which assists in thecracking andyields a cleaner cut than if only oneporous layer was used.1

The seed wafer is thenbonded to thehandle waferin a process similartothe Smart Cut™

process.

A powerfulwater jet can then aid in cracking the waferaround

themechanically weak porous silicon region.

Benefits fromSOI in Devices

The mentioned fabrication techniques are just a few out of many other methods.

Devices seegreat leaps in improvement no matter which fabrication method is used.