We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Firefox,
Internet Explorer 11,
Safari. Thank you!

AR# 46136

Description

The following AR will provide information/resources that will be usefulfor debugging PLL locking issueswhen using ChipScope IBERT.

Note: This Answer Record is a part of the Xilinx ChipScope Solution Center (Xilinx Answer 45310). The Xilinx ChipScope Solution Center is available to address all questions related to the ChipScope tool. Whether you are starting a new design with the ChipScope tool or troubleshooting a problem, use the ChipScope Solution Center to guide you to the right information.

Solution

The following steps should be taken when debugging a IBERT design which is having issues with the PLL not Locking.

1) Verify that the IBERT design is configured properly with the board setup

This is very basic, but it is important to double check that a mistake is not made here. It is a good idea to run through the IBERT wizard and re-verify that you have made all the appropriate selections which match your board configuration. More specifically, you want to verify the following:

System Clock pin location and I/O Standard matches what is on your board

Line Rate is set to the correct speed

Reference Clock configuration matches what you are using on the board

Physical Transceiver configuration matches what is used on the board

2) Determine if the PLL in the transceiver is LOCKED

This is very easy as there is a field in the IBERT GUI of Analyzer that tells you this. If the PLL is not locked, it is a good idea to look at the reference clock with an oscilloscope and verify that the clock is oscillating at the correct frequency, and the signal integrity is good.

3) Verify that the system clock is oscillating at the correct frequency and has good signal integrity

If the IBERT design is not using a separate system clock (that is,the clocks from the MGT are used instead) you can skip this step. The IBERT GUI in Analyzer should issue an error if there is something wrong with the system clock, but it is a good idea to check this so that we can be sure there is not something wrong with the system clock.

4) Verify that the PLL settings are set correctly for the transceiver

For this step, please refer to the Advanced IBERT Debugging Techniques answer record at (Xilinx Answer 46936).

5) Reset the transceivers

Now that we have verified that the clocks to the IBERT core are present and stable, the GTs should be reset at this time. If this still does not get the GT to link up, try changing the loopback mode to near-end PCS or PMA and then hit reset again.

6) If a Xilinx development board is available, try running the same IBERT configuration on a Xilinx development board

This will rule out whether this is a board related issue or a IBERT design related issue. If IBERT works on the Xilinx development board, you may have an issue related to your board which is causing IBERT to not work. If IBERT still does not work on a Xilinx development board, please open up a webcase with Xilinx Technical support for further assistance. A webcase can be opened at the following link: