tag: device scaling

Talk about boosting wafer sizes from 300mm to 450mm has been creeping back into presentations and discussions at conferences over the past couple months.
Earlier this year, discussions focused on panel-level packaging. These are basically similar approaches to the same problem, which is that wafers need to be larger to reap efficiencies out of device scaling. Whether either of these approach... » read more

It’s becoming apparent that traditional chip scaling is slowing down. The 16nm/14nm logic node took longer than expected to unfold. And the 10nm node and beyond could suffer the same fate.
So what’s the main cause? It’s hard to pinpoint the problem, although many blame the issues on lithography. But what could eventually hold up the scaling train, and undo Moore’s Law, is arguably t... » read more