The GW16113 has 332 ohm series termination resistors between the PSoC pins and the external connectors limiting the current to 10mA - contact sales@… for information on creating a Gateworks special with modified termination

Customizable Firmware

Pre-built firmware configurations may be available for download ​here.

Note The GW16113 is pre-programmed with all pins set to act as a GPIO / DIO.

Users can also choose to customize the firmware on their own to suit their needs. The Gateworks PSoC Creator source is available ​here. The ​Cypress PSoC Creator is the free Windows development tool provided by Cypress used to design and compile firmware for PSoC devices.

To program or recover a PSoC on the GW16113 you need to program it via JTAG which requires a GW16116 USB carrier that has pogo-pins to mate with the GW16113's JTAG pins. There are two methods involving different versions of the GW16115:

GW16115 pogo-pin adapter with resistor loading for the J1 Cypress 10-pin JTAG header with the Cypress miniProg programmer hardware/software and a .hex file

GW16115 pogo-pin adapter with resistor loading for the J2 Gateworks 10-pin JTAG header with a Gatworks JTAG dongle or gang programmer and a .xsvf file

The Cypress PSoC Programmer application needs the following settings:

Open the 'hex' file with firmware you wish to program

Configure device family to: Cy8C5xxxLP

Configure device to: CY8C5888LTQ-LP097

Verification: off

Autodetect: off

Protocol: SWD

Voltage: 3.3V

Procedure:

Connect MiniProg to Windows host PC

Connect MiniProg 10-pin jtag cable to J1 on GW16115 wich GW16113 loaded (do not provide external power by connecting USB to a host)

Connect via the connect icon

Power via the power icon

Program via the run icon

Notes:

Protocol of 5-wire JTAG will work as well and if 5-wire JTAG has been disabled via pin-config it silently falls back to SWD, so I find it better to just use SWD in the first place

Power on seems optional... it will eventually power the board on regardless

Firmware Images

The firmware resides in the 256KB PSoC FLASH therefore is non-volatile and contains both the bootloader as well as the main application. See below regarding firmware updates.

Firmware Updates

The PSoC has 256KB of programmable non-volatile FLASH that are used to contain the 'firmware application'. The pre-built firmware images provided by Gateworks contain a PSoC5 Bootloader application that allows for USB updates of the main application (aka bootloadable) firmware.

GW16113 bootloader details:

Bootloader is programmed at the factory via JTAG and is not able to be updated via USB (technically an application firmware can be created that allows updating the bootloader however Gateworks does not currently support this)

USB Vendor-ID and Product-ID of bootloader: 0x2beb:0x1100

Bootloader application is run when GW16113 comes out of reset (when PCI_RESET# is released) and will do one of the following depending on EEPROM configuration:

remain in the bootloader awaiting a command (to jump to existing app, or program new app)

remain in the bootloader awaiting a command if the state of the I/O ports latched coming out of reset matches a predefined value, otherwise jump to the application immediately

jump directly to application

main application can be instructed to jump to the bootloader and wait for a command (to allow firmware updating)

Options 1 and 2 above are designed to provide a fool-proof way of recovering from a failed firmware update, or faulty firmware that does not allow a method to jump back to the bootloader.

The factory default configuration is to stay in the bootloader a logic value of 0x55 (pin1,3,5,7 logic high, pin2,4,6,8 logic low) is latched on P12 (J1) when the GW16113 comes out of reset (option 2 above).

The bootloader configuration is stored in the PSoC EEPROM and can be altered via the gwsoc application (or directly by the main application if using custom firmware) if the default configuration does not suit your needs.

The gwsoc application running on the host processor has the ability to instruct the application to jump to the bootloader and await a command for updating the main application firmware. The '-p' command-line option is used to update the firmware providing a '.cyacd' file.

If for some reason the use case demands the 15KB FLASH space (of 256KB available) used by the bootloader or the ability to update the firmware via USB is not desired, the firmware can be customized by the user to eliminate the bootloader. The resulting firmware would need to be programmed via JTAG. Contact sales@… if this is a requirement.

General Purpose IO (GPIO)

The I/O pins allows a variety of Drive Modes:

strong drive

open drain, drives high

open drain, drives low

resistive pull-up (5.6kOhm typ)

resistive pull-down (5.6kOhm typ)

resistive pull up/down (5.6kOhm typ)

high impedance digital

high impedance analog

Several GPIO's will likely be able to be configured with different capabilities:

I2C Interface

The ​I2C component supports I2C slave, master, and multi-master configurations. The I2C bus is an industry-standard, two-wire hardware interface developed by Philips. The master initiates all communication on the I2C bus and supplies the clock for all slave devices.

The I2C component supports standard clock speeds up to 1mbps and is compatible with I2C standard mode, fast mode, and fast mode plus devices as defines in the NXP I2C-bus specification.

Serial Peripheral Interface (SPI)

The PSoC 5LP does not have a fixed hardware SPI master interface but instead uses resources from the UDB array. There is both a SPI Master component and SPI Slave component available but the default configuration for the GW16113 will support the master.

the value of 0x00005555 indicates that P12.0,2,4,6 cooresponding to J1.1,3,5,7 are reading high (these are inputs per the gpiodir setting above) and P3.0,2,4,6 cooresponding to J2.1,3,5,7 are outputing logic high

Linux Device Drivers

Linux native kernel drivers will be provided in the Gateworks Board Support Packages (coming soon).

PSoc 5LP and Firmware

The GW16113 is based upon the Cypress PSoC 5LP device which is a programmable device which can be best thought of as cross between a microcontroller combined with a PLD and programmable analog. This means that the board can operate in many different modes depending on how it is programmed.

PSoC Resources and Capabilities

Cypress provides pre-configured functional blocks referred to as 'Components' that can be supported by the PSoC. Conceptually these are virtual peripherals that each have their own datasheet, schematic library representation, and support code implementing an API.

The ​Cypress PSoC Creator is the free Windows development tool provided by Cypress used to design and compile firmware for PSoC devices. To create firmware that can be programmed on a PSoC you use this tool to drag-and-drop and configure schematic representations of components and edit ANSI-C code to configure and control the components.

A list of components compatible with the PSoC 5LP is available from Cypress ​PSoC5LP here and all of these are available within PSoC Creator.

Each PSoC 5LP has a fixed set of internal resources available such as:

RAM

FLASH storage

Univeral Design Blocks (UDB)

Digital clock dividers

Pins

DMA channels

Comparators

Programmable Analog Blocks

Interrupts

various Fixed blocks (ie USB, CAN, I2C, SPI, UART, controllers)

Each component has its own individual datasheet that contains details such as:

Features

Software API

Hardware configuration info

Resource usage

To determine what can fit into a PSoC you can compare the PSoC datasheet list of resources with the individual component datasheets. Preferably PSoC Creator can generate a resource summary by:

Cypress also has a nifty online tool that knows quite a bit about what each component needs and what is available. It is used for selecting a PSoC chip but can also be useful to prove that your basic needs can be met. You can find their epsg tool ​here. Note that this tool does not take into account that we only have 24 I/O pins available to connectors.