Hi,
The local register allocator can't do instruction scheduling. I think the
OP_LCONV_TO_I4 rule is wrong, it should use OP_ISHR_IMM. For some reason
it seems to work on the existing 64 bit ports.
Zoltan
On 9/7/06, Sergey Tikhonov <tsv at solvo.ru> wrote:
> Hello,
>> I have some questions about mono_local_regalloc. Is it possible to tell
> its logic right now not to reuse the same
> physical register in the same instruction? Alpha has "a lot" of
> registers and experience some penalty if the same
> register is used in the same or next instruction when results of
> previous instruction are not needed for next. For example:
> 1. op_loadmembase dest_reg1, offset1(basereg)
> 2. op_storemembase src_reg (= dest_reg1), offset2(basereg)
> 3. op_loadmembase dest_reg1, offset3(basereg)
> 4. op_storemembase src_reg (= dest_reg1), offset4(basereg)
>> I would like for 3rd and 4th instruction the different temp
> (dest_reg1/src_reg1) to be used.
> The better schedulling will be if the instructions are arranged in
> following sequence - 1,3,2,4, but I am not asking for that. :)
>> Another question: is the "reg: OP_LCONV_TO_I4 (reg)" operation correctly
> expected to be implemented by OP_LSHR_IMM (long right shift) opcode? The
> next unsigned version uses OP_ISHR_UN_IMM (integer shift).
>> Thank you,
> PS: My failed tests down to 7 and most of them pinvokes with valuetypes
> (pinvoke with simple types work).
>> --
> Sergey Tikhonov
>> Solvo Ltd.
> Saint-Petersburg, Russia
>tsv at solvo.ru>>