High-level synthesis rollouts enable ESL

SANTA CRUZ, Calif.  Three vendors promise to lift ASIC and FPGA designers above today's RTL design methodologies with high-level synthesis tools they will roll out this week. Though the companies all take different approaches, each claims huge time-to-market gains as well as quality of results.

The announcements may help enable electronic system-level (ESL) design, viewed by some observers as the next wave of electronic design automation. ESL has been hobbled by a lack of automated synthesis. Earlier this month, Forte Design Automation promised to fill that gap with Cynthesizer, a SystemC behavioral-synthesis product (see May 10, page 1).

But SystemC isn't the only way to go, according to Mentor, which calls Catapult an "algorithmic," rather than behavioral, synthesis tool. Aimed at compute-intensive applications such as digital signal processing, Catapult takes pure, untimed C++ and produces synthesizable code. It claims to speed design time by at least 50 percent while producing equal or better results than register-transfer-level hand coding.

Gary Smith, chief EDA analyst at Gartner Dataquest, believes Catapult will be "the most important announcement" of the Design Automation Conference, to be held next week in San Diego. "It looks like they have an interface synthesis capability," he said. While several vendors have offered behavioral synthesis for blocks, interface synthesis has been a missing piece of Smith's ESL "road map."

Proven in useBacked by 10 years of R&D, Catapult is not just a promise. It has been in use for about two years, counts more than 10 tapeouts and boasts customers including Alcatel, Ericsson, Nokia, Siemens and STMicroelectronics, said Shawn McCloud, high-level synthesis product manager at Mentor (Wilsonville, Ore.). Mentor disclosed some of the technology behind Catapult in a paper at the International HDL Conference in March 2001, where a Mentor representative told EE Times the company was about to go into beta sites with a C synthesis product.

"For the first time, we're starting from a completely abstract C++ description similar to what system designers are writing today to do system-level modeling," McCloud said. "The quality of results is not only matching what designers can do by hand, but is often surpassing it."

While Catapult handles both data path and control logic, McCloud said the tool is currently aimed at compute-intensive applications, particularly in the communications and video image-processing markets. It is not aimed at applications that are data-intensive, such as network switches.

"Our mission has been to synthesize completely from a C++ description," McCloud said. "What that means is that not only the algorithm, but also the interface is untimed." He said Mentor's patent-pending "interface synthesis" technology lets users keep a pure C++ description, and map C-language interfaces into hardware components. Then the tool builds the hardware tuned to the bandwidth of the interface.

Catapult imposes a few restrictions on the C++ code; for example, pointers must be statically determinable. Users specify constraints, and must provide a clock period and destination technology. For ASIC design, Catapult's C Library Builder allows users to collect the detailed characterization data the tool needs.

In addition to a cycle-accurate simulation model, Catapult produces readable, synthesizable RTL for both data path and control logic. In most cases, the quality of the code surpasses handcrafted code, McCloud said. He maintained that customers are typically seeing a 20 percent area reduction in ASIC designs compared with handcrafted RTL, while getting to RTL up to 20 times faster.

At Nokia's Dallas research center, Catapult has been in use for two years, said research manager Dennis McCain. He said the center has targeted Xilinx Virtex FPGAs, but not ASICs. Catapult is not yet in production use at Nokia.

"We normally develop our algorithms in Matlab or C code," McCain said. "With Catapult we can make architectural trade-offs at a very high level and generate synthesizable RTL, which shortens our design flow significantly." The time savings may be 50 or 60 percent compared with the previous hand-coded RTL flow, he said.

Quality of results is "pretty close" to hand-coded VHDL, McCain said. "If you really try hard you could probably do better than Catapult C with hand coding if you have a fixed specification. But typically we don't have a fixed specification, and it changes a lot," he said.

Yaunbin Guo, research engineer at Nokia, commented that he'd like to see improvements for handling control logic. "At this stage they're still focusing on compute-intensive applications," he said.

Reconfigurable approachCeloxica, for its part, is no stranger to C-language synthesis. The Abingdon, England, company's DK Design Suite offers synthesis and simulation using its proprietary Handel-C dialect. What's new with Agility C, which will be introduced this week, is synthesis using the industry-standard SystemC language.

Celoxica focuses on reconfigurable logic, including not only FPGAs but also new architectures like the so-called "programmable algorithm processing" of Elixent Ltd. "System-level design has got it all wrong to focus on ASICs," said Jeff Jussell, Celoxica's vice president. "C designers go to FPGAs for their first prototype."

Agility C can generate RTL code for ASIC design, but its real focus is programmable logic. The tool is "DSP-oriented," Jussell said, and aimed at applications such as digital imaging and signal processing. Agility C is still in prerelease mode, and Celoxica has not named any customers.

Unlike Mentor's Catapult, Agility C uses timed SystemC descriptions. "We believe that's the most efficient way to give the designer control," Jussell said. "If you're dealing with C and implementing in hardware, you can't get away without knowing a little bit about what the hardware does."

Software designers will probably stay with Celoxica's Handel-C offering, which is basically ANSI C with compiler directives, Jussell said. Agility C is aimed more at hardware designers who want to write in C++, or who already have intellectual-property (IP) blocks coded in SystemC.

Jussell said Celoxica doesn't believe there will be an area and performance sacrifice for Agility C, and he said that Handel-C synthesis has been found to often beat hand-coded RTL performance. "Where we really shine is when you have pieces in both the processor and the hardware, and we can move things back and forth to the processor, which you just can't do in VHDL or Verilog," he said. "Design times are 50 percent faster and our results end up the same or, very often, beat the goals."

Forget about CWith its claim to slash design times in half while providing equal or better results than hand-coded RTL, Waltham, Mass., startup Bluespec might appear to be in the same camp as Forte, Mentor and Celoxica. But there's a big difference. The Bluespec Compiler generates synthesizable RTL from SystemVerilog assertions, avoiding C-language synthesis entirely.

Another big difference: Bluespec is not primarily aimed at DSPs or data path-intensive designs. Shiv Tasker, Bluespec CEO, said most current evaluations are heavily tilted toward control logic, including a network-processing chip and an MPU. The company hasn't yet announced customers.

To use the compiler, engineers identify state elements and then specify behavior with design assertions in SystemVerilog. "We believe the engineer should be in control of the microarchitecture," Tasker said. "We found a way to raise the level of abstraction and still leave the engineer in control."

Bluespec recently announced a comprehensive suite of benchmarks using an IP library from Interra Systems. Some 25 small to medium-size designs were recoded at a design assertion level and tested to ensure identical functionality with the original Verilog designs. After running both the original Verilog and the Bluespec-synthesized RTL through equivalent synthesis flows, the tests showed equivalent or better results compared with hand-coded RTL, Bluespec said.

The Bluespec Compiler outputs Verilog 95 RTL code. That was chosen because it's "very predictable" for Synopsys' Design Compiler, Tasker said. It also produces a cycle-accurate C model that can be used for system-level verification with the Bluespec Simulator, which runs 1,000 times faster than Verilog, he said.

"This is really a method that bridges the gap between high-level modeling and hardware design," Tasker said.