Abstract:

The present invention relates to a shift register having a plurality of
stages electrically coupled to each other in series. Each stage includes
a first and second TFT transistor. The first TFT transistor has a get
electrically coupled to the output of the immediately prior stage, a
drain electrically coupled to the boost point of the stage, and a source
configured to receive one of the first and second control signals. The
second TFT transistor has a get electrically coupled to the output of the
immediately next stage, a drain and a source electrically coupled the
drain and the source of the first transistor, respectively.

Claims:

1. A shift register, comprising:(a) a first control line for providing a
first control signal, Bi1, and a second control line for providing a
second control signal, Bi2, wherein each of the first control signal Bi1
and the second control signal Bi2 is characterized with a period and a
phase, the periods of the first and second control signals Bi1 and Bi2
being identical and the phases of the first and second control signals
Bi1 and Bi2 being opposite to each other; and(b) a plurality of stages,
{Sj}, j=1, 2, . . . , N, N being a positive integer, electrically
coupled to each other in series, wherein each stage Sj comprises:a
first transistor M1 having a gate electrically coupled to the immediately
prior stage Sj-1, a drain electrically coupled to a node BP, and a
source electrically coupled to the first control signal line or the
second control signal line for receiving a corresponding control signal
therefrom, respectively; and(ii) a second transistor M2 having a gate
electrically coupled to the immediately next stage Sj+1, a drain
electrically coupled to the drain of the first transistor M1, and a
source electrically coupled to the source of the first transistor M1,
respectively.

2. The shift register of claim 1, wherein the source of the first
transistor M1 of the stage Sj and the source of the first transistor
M1 of the stage Sj+1 are electrically coupled to one of the first
and second control signal lines, while the source of the first transistor
M1 of the stage Sj+2 and the source of the first transistor M1 of
the stage Sj+3 are electrically coupled to the other of the first
and second control signal lines.

3. The shift register of claim 1, further comprising:(a) a first clock
signal line for providing a first clock signal, CK, and a second clock
signal line for providing a second clock signal, XCK, wherein each of the
first clock signal CK and the second clock signal XCK is characterized
with a period and a phase, the periods of the first and second clock
signals CK and XCK being identical and the phases of the first and second
clock signals CK and XCK being opposite to each other; and(b) a reference
line for providing a reference voltage, VSS.

4. The shift register of claim 3, wherein each stage Sj further
comprises an output for outputting a scanning signal, g(j), and wherein
the gate of the first transistor M1 is electrically coupled to the
immediately prior stage Sj-1, and the gate of the second transistor
M2 is electrically coupled to the immediately next stage Sj+1,
respectively.

5. The shift register of claim 4, wherein each stage Sj further
comprises a third transistor M3 having a gate electrically coupled to the
node BP, a drain electrically coupled to the first clock signal line or
the second clock signal line for receiving a corresponding clock signal
therefrom, and a source electrically coupled to the output, respectively.

6. The shift register of claim 5, wherein the drain of the third
transistor M3 of the stage Sj is electrically coupled to one of the
first and second clock signal lines when j is an odd number, while the
drain of the third transistor M3 of the stage Sj is electrically
coupled to the other of the first and second clock signal lines when j is
an even number.

7. The shift register of claim 5, wherein each stage Sj further
comprises a fourth transistor M4 having a gate, a drain electrically
coupled to the source of the third transistor M3, and a source
electrically coupled to the reference signal line for receiving the
reference voltage VSS therefrom, respectively.

8. The shift register of claim 7, wherein each Sj further comprises a
disable circuit electrically coupled between the node BP and the gate of
the fourth transistor M4 for operably disabling an output of the stage
Sj.

9. The shift register of claim 7, wherein each of the first transistor M1,
the second transistor M2, the third transistor M3, and the fourth
transistor M4 comprises a field-effect thin film transistor.

10. The shift register of claim 3, wherein the periods of the first and
second control signals Bi1 and Bi2 are (2*B*T), and the periods of the
first and second clock signals CK and XCK are (2*C*T), and wherein T is a
pulse width of the scanning signal g(j), and B and C are constants
satisfying the relationship of B=2*C.

11. The shift register of claim 10, wherein the first control signal Bi1
and the first clock signal CK have a relative phase that controls input
signals to be shifted in a forward or backward direction.

12. A shift register, comprising a first shift register circuit and second
shift register circuit that in use, are formed on the left and right
sides, respectively, of a display panel such that a pixel matrix of the
display panel is located between the first and second shift register
circuits, each of the first and second shift register circuits
comprising:(a) a first control line for providing a first control signal,
Bi1_L/Bi1_R, and a second control line for providing a second control
signal, Bi2_L/Bi2_R, wherein each of the first control signal Bi1_L/Bi1_R
and the second control signal Bi2_L/Bi2_R is characterized with a period
and a phase, the periods of the first and second control signals
Bi1_L/Bi1_R and Bi2_L/Bi2_R being identical and the phases of the first
and second control signals Bi1_L/Bi1_R and Bi2_L/Bi2_R being opposite to
each other; and(b) a plurality of stages, {Sj}, j=1, 2, . . . , N, N
being a positive integer, electrically coupled to each other in series,
wherein each stage Sj comprises:a first transistor M1 having a gate
electrically coupled to the immediately prior stage Sj-1, a drain
electrically coupled to a node BP, and a source electrically coupled to
the first control signal line or the second control signal line for
receiving a corresponding control signal therefrom, respectively; and(ii)
a second transistor M2 having a gate electrically coupled to the
immediately next stage Sj+1, a drain electrically coupled to the
drain of the first transistor M1, and a source electrically coupled to
the source of the first transistor M1, respectively;

13. The shift register of claim 12, wherein for each shift register
circuit, the source of the first transistor M1 of the stage Sj and
the source of the first transistor M1 of the stage Sj+1 are
electrically coupled to one of the first and second control signal lines,
while the source of the first transistor M1 of the stage Sj+2 and
the source of the first transistor M1 of the stage Sj+3 are
electrically coupled to the other of the first and second control signal
lines.

14. The shift register of claim 12, wherein each shift register circuit
further comprises(a) a first clock signal line for providing a first
clock signal, CK_L/CK_R, and a second clock signal line for providing a
second clock signal, XCK_L/XCK_R, wherein each of the first clock signal
CK_L/CK_R and the second clock signal XCK_L/XCK_R is characterized with a
period and a phase, the periods of the first and second clock signals
CK_L/CK_R and XCK_L/XCK_R being identical and the phases of the first and
second clock signals CK_L/CK_R and XCK_L/XCK_R being opposite to each
other; and(b) a reference line for providing a reference voltage, VSS.

15. The shift register of claim 14, wherein for each of the first and
second shift register circuits, each stage Sj further comprises an
output for outputting a scanning signal, g(j)_L/g(j)_R; and wherein the
gate of the first transistor M1 is electrically coupled to the
immediately prior stage Sj-1, and the gate of the second transistor
M2 is electrically coupled to the immediately next stage Sj+1,
respectively.

16. The shift register of claim 15, wherein for each of the first and
second shift register circuits, each stage Sj further comprises a
third transistor M3 having a gate electrically coupled to the node BP, a
drain electrically coupled to the first clock signal line or the second
clock signal line for receiving a corresponding clock signal therefrom,
and a source electrically coupled to the output, respectively.

17. The shift register of claim 15, wherein for each of the first and
second shift register circuits, the drain of the third transistor M3 of
the stage Sj is electrically coupled to one of the first and second
clock signal lines when j is an odd number, while the drain of the third
transistor M3 of the stage Sj is electrically coupled to the other
of the first and second clock signal lines when j is an even number.

18. The shift register of claim 15, wherein for each of the first and
second shift register circuits, each stage Sj further comprises a
fourth transistor M4 having a gate, a drain electrically coupled to the
source of the third transistor M3, and a source electrically coupled to
the reference signal line for receiving the reference voltage therefrom,
respectively.

19. The shift register of claim 18, wherein for each of the first and
second shift register circuits, each stage Sj further comprises a
disable circuit electrically coupled between the node BP and the gate of
the fourth transistor M4 for operably disabling an output of the stage
Sj.

20. The shift register of claim 18, wherein for each of the first and
second shift register circuits, each of the first transistor M1, the
second transistor M2, the third transistor M3, and the fourth transistor
M4 comprises a field-effect thin film transistor.

21. The shift register of claim 15, wherein the scanning signals,
{g(j)_L}, output sequentially from the first GOA shift register circuit
are operably applied to the odd number rows of the pixel matrix,
respectively, while the scanning signals, {g(j)_R}, output sequentially
from the second GOA shift register circuit are operably applied to the
even number rows of the pixel matrix, respectively, or vice versa.

22. The shift register of claim 14, wherein the periods of the first and
second control signals Bi1_L/Bi1_R and Bi2_L/Bi2 are (2*B*T), and the
periods of the first and second clock signals CK_L/CK_R and XCK_L/XCK_R
are (2*C*T), and wherein T is a pulse width of the scanning signal
g(j)_L/g(j)_R, and B and C are constants satisfying the relationship of
B=2*C.

23. The shift register of claim 22, wherein the first control signal
Bi1_L/Bi1_R, the second control signal Bi2_L/Bi2_R, the first clock
signal CK_L/CK_R and the second clock signal XCK_L/XCK_R have a relative
phase that controls input signals to be shifted in a forward or backward
direction.

[0002]Some references, if any, which may include patents, patent
applications and various publications, are cited and discussed in the
description of this invention. The citation and/or discussion of such
references is provided merely to clarify the description of the present
invention and is not an admission that any such reference is "prior art"
to the invention described herein. All references cited and discussed in
this specification are incorporated herein by reference in their
entireties and to the same extent as if each reference was individually
incorporated by reference.

FIELD OF THE INVENTION

[0003]The present invention relates generally to a shift register and more
particularly to a shift register with an embedded bidirectional scanning
function.

BACKGROUND OF THE INVENTION

[0004]A liquid crystal display (LCD) includes an LCD panel formed with
liquid crystal cells and pixel elements with each associating with a
corresponding liquid crystal cell. These pixel elements are substantially
arranged in the form of a matrix having gate lines in rows and data lines
in columns. The LCD panel is driven by a driving circuit including a gate
driver and a data driver. The gate driver generates a plurality of gate
signals (scanning signals) sequentially applied to the gate lines for
sequentially turning on the pixel elements row-by-row. The data driver
generates a plurality of source signals (data signals), i.e.,
sequentially sampling image signals, simultaneously applied to the data
lines in conjunction with the gate signals applied to the gate lines for
aligning states of the liquid crystal cells on the LCD panel to control
light transmittance therethrough, thereby displaying an image on the LCD.

[0005]In such a driving circuit, a bi-directional shift register is
usually utilized in the gate driver to generate the plurality of gate
signals for sequentially driving the gate lines, so as to allow a
positive or a reverse display image. Typically, a plurality of 2-to-2
bi-directional control circuits is employed in the bi-directional shift
register to control the scanning direction, forward or backward, of the
plurality of gate signals.

[0006]FIG. 7 illustrates a conventional 2-to-2 bi-directional control
circuit having two input terminals P and N, and two output terminals D1
and D2, and is operably controlled by two control signals Bi and XBi. The
control signals Bi and XBi are two DC signals set to have opposite
polarities, such as a high level voltage and a low level voltage, and
used to set the 2-to 2 bi-directional control circuits in a manner to
direct input signals in the shift register to be shifted in a forward or
backward direction. However, the use of the 2-to 2 bi-directional control
circuit in each stage of the shift register may cause voltage drops in
input signals of the stage, and increase power consumption and
manufacture costs.

[0007]Therefore, a heretofore unaddressed need exists in the art to
address the aforementioned deficiencies and inadequacies.

SUMMARY OF THE INVENTION

[0008]The present invention, in one aspect, relates to a shift register.
In one embodiment, the shift register includes a first control line for
providing a first control signal, Bi1; a second control line for
providing a second control signal, Bi2; a first clock signal line for
providing a first clock signal, CK; a second clock signal line for
providing a second clock signal, XCK; a reference line for providing a
reference voltage, VSS; and a plurality of stages, {Sj}, j=1, 2, . .
. , N, N being a positive integer, electrically coupled to each other in
series.

[0009]Each stage Sj includes an output for outputting a scanning
signal, g(j); a first transistor M1 having a gate electrically coupled to
the output of the immediately prior stage Sj-1, a drain electrically
coupled to the node BP, and a source electrically coupled to one of the
first and second control signal lines for receiving a corresponding
control signal therefrom, respectively; a second transistor M2 having a
gate electrically coupled to the output of the immediately next stage
Sj+1, a drain electrically coupled to the drain of the first
transistor M1, and a source electrically coupled to the source of the
first transistor M1, respectively; a third transistor M3 having a gate
electrically coupled to the node BP, a drain electrically coupled to one
of the first and second clock signal lines for receiving a corresponding
clock signal therefrom, and a source electrically coupled to the output,
respectively; and a fourth transistor M4 having a gate, a drain
electrically coupled to the source of the third transistor M3, and a
source electrically coupled to the reference signal line for receiving
the reference voltage therefrom, respectively.

[0010]Further, each stage Sj also includes a disable circuit
electrically coupled between the node BP and the gate of the fourth
transistor M4 for operably disabling an output of the stage Sj.

[0011]In one embodiment, the source of the first transistor M1 of the
stage Sj and the source of the first transistor M1 of the stage
Sj+1 are electrically coupled to one of the first and second control
signal lines, while the source of the first transistor M1 of the stage
Sj+2 and the source of the first transistor M1 of the stage
Sj-3 are electrically coupled to the other of the first and second
control signal lines. The drain of the third transistor M3 of the stage
Sj is electrically coupled to one of the first and second clock
signal lines when j is an odd number, while the drain of the third
transistor M3 of the stage Sj is electrically coupled to the other
of the first and second clock signal lines when j is an even number.

[0012]Each of the first control signal Bi1, the second control signal Bi2,
the first clock signal CK and the second clock signal XCK is
characterized with a period and a phase, wherein the periods of the first
and second control signals Bi1 and Bi2 are identical and the phases of
the first and second control signals Bi1 and Bi2 are opposite to each
other, wherein the periods of the first and second clock signals CK and
XCK are identical and the phases of the first and second clock signals CK
and XCK are opposite to each other. In one embodiment, the periods of the
first and second control signals Bi1 and Bi2 are (2*B*T), and the periods
of the first and second clock signals CK and XCK are (2*C*T), and wherein
T is a pulse width of the scanning signal g(j), and B and C are constants
satisfying the relationship of B=2*C.

[0013]In one embodiment, the first control signal Bi1 and the first clock
signal CK have a relative phase that controls input signals to be shifted
in a forward or backward direction.

[0014]In one embodiment, each of the first transistor M1, the second
transistor M2, the third transistor M3, and the fourth transistor M4
comprises a field-effect thin film transistor.

[0015]In another aspect, the present invention relates to a shift
register. In one embodiment, the shift register comprises a first shift
register circuit and second shift register circuit that in use, are
formed on the left and right sides, respectively, of a display panel such
that a pixel matrix of the display panel is located between the first and
second GOA shift register circuits.

[0016]Each of the first and second shift register circuits includes a
first control line for providing a first control signal, Bi1_L/Bi1_R; a
second control line for providing a second control signal, Bi2_L/Bi2_R; a
first clock signal line for providing a first clock signal, CK_L/CK_R; a
second clock signal line for providing a second clock signal,
XCK_L/XCK_R; a reference line for providing a reference voltage, VSS; and
a plurality of stages, {Sj}, j=1, 2, . . . , N, N being a positive
integer, electrically coupled to each other in series.

[0017]Each stage Sj includes an output for outputting a scanning
signal, g(j)_L/g(j)_R; a first transistor M1 having a gate electrically
coupled to the output of the immediately prior stage Sj-1, a drain
electrically coupled to the node BP, and a source electrically coupled to
one of the first and second control signal lines for receiving a
corresponding control signal therefrom, respectively; a second transistor
M2 having a gate electrically coupled to the output of the immediately
next stage Sj+1, a drain electrically coupled to the drain of the
first transistor M1, and a source electrically coupled to the source of
the first transistor M1, respectively; a third transistor M3 having a
gate electrically coupled to the node BP, a drain electrically coupled to
one of the first and second clock signal lines for receiving a
corresponding clock signal therefrom, and a source electrically coupled
to the output, respectively; and a fourth transistor M4 having a gate, a
drain electrically coupled to the source of the third transistor M3, and
a source electrically coupled to the reference signal line for receiving
the reference voltage therefrom, respectively. Each of the first
transistor M1, the second transistor M2, the third transistor M3, and the
fourth transistor M4 comprises a field-effect thin film transistor.

[0018]In one embodiment, each Sj further comprises a disable circuit
electrically coupled between the node BP and the gate of the fourth
transistor M4 for operably disabling an output of the stage Sj.

[0019]The scanning signals, {g(j)_L}, output sequentially from the first
shift register circuit are operably applied to the odd number rows of the
pixel matrix, respectively, while the scanning signals, {g(j)_R}, output
sequentially from the second GOA shift register circuit are operably
applied to the even number rows of the pixel matrix, respectively, or
vice versa.

[0020]For each shift register circuit, the source of the first transistor
M1 of the stage Sj and the source of the first transistor M1 of the
stage Sj 1 are electrically coupled to one of the first and second
control signal lines, while the source of the first transistor M1 of the
stage Sj+2 and the source of the first transistor M1 of the stage
Sj+3 are electrically coupled to the other of the first and second
control signal lines.

[0021]For each shift register circuit, the drain of the third transistor
M3 of the stage Sj is electrically coupled to one of the first and
second clock signal lines when j is an odd number, while the drain of the
third transistor M3 of the stage Sj is electrically coupled to the
other of the first and second clock signal lines when j is an even
number.

[0022]For each shift register circuit, each of the first control signal
Bi1_L/Bi1_R, the second control signal Bi2_L/Bi2_R, the first clock
signal CK_L/CK_R and the second clock signal XCK_L/XCK_R is characterized
with a period and a phase, wherein the periods of the first and second
control signals Bi1_L/Bi1_R and Bi2_L/Bi2_R are identical and the phases
of the first and second control signals Bi1_L/Bi1_R and Bi2_L/Bi2_R are
opposite to each other, wherein the periods of the first and second clock
signals CK_L/CK_R and XCK_L/XCK_R are identical and the phases of the
first and second clock signals CK_L/CK_R and XCK_L/XCK_R are opposite to
each other. In hone embodiment, the periods of the first and second
control signals Bi1_L/Bi1_R and Bi2_L/Bi2 are (2*B*T), and the periods of
the first and second clock signals CK_L/CK_R and XCK_L/XCK_R are (2*C*T),
and wherein T is a pulse width of the scanning signal g(j)_L/g(j)_R, and
B and C are constants satisfying the relationship of B=2*C.

[0023]In one embodiment, the first control signal Bi1_L/Bi1_R, the second
control signal Bi2_L/Bi2_R, the first clock signal CK_L/CK_R and the
second clock signal XCK_L/XCK_R have a relative phase that controls input
signals to be shifted in a forward or backward direction.

[0024]These and other aspects of the present invention will become
apparent from the following description of the preferred embodiment taken
in conjunction with the following drawings, although variations and
modifications therein may be affected without departing from the spirit
and scope of the novel concepts of the disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025]The accompanying drawings illustrate one or more embodiments of the
invention and, together with the written description, serve to explain
the principles of the invention. Wherever possible, the same reference
numbers are used throughout the drawings to refer to the same or like
elements of an embodiment, and wherein:

[0026]FIG. 1 shows a shift register according to one embodiment of the
present invention;

[0027]FIG. 2 shows a circuit diagram of a stage of the shift register
shown in FIG. 1;

[0028]FIG. 3 shows a timing chart of input and output signals of the shift
register shown in FIG. 1;

[0029]FIG. 4 shows another timing chart of input and output signals of the
shift register shown in FIG. 1;

[0030]FIG. 5 shows a shift register according to another embodiment of the
present invention;

[0031]FIG. 6 shows a timing chart of input and output signals of the shift
register shown in FIG. 5; and

[0033]The present invention is more particularly described in the
following examples that are intended as illustrative only since numerous
modifications and variations therein will be apparent to those skilled in
the art. Various embodiments of the invention are now described in
detail. Referring to the drawings, like numbers indicate like components
throughout the views. As used in the description herein and throughout
the claims that follow, the meaning of "a", "an", and "the" includes
plural reference unless the context clearly dictates otherwise. Also, as
used in the description herein and throughout the claims that follow, the
meaning of "in" includes "in" and "on" unless the context clearly
dictates otherwise.

[0034]The terms used in this specification generally have their ordinary
meanings in the art, within the context of the invention, and in the
specific context where each term is used. Certain terms that are used to
describe the invention are discussed below, or elsewhere in the
specification, to provide additional guidance to the practitioner
regarding the description of the invention. The use of examples anywhere
in this specification, including examples of any terms discussed herein,
is illustrative only, and in no way limits the scope and meaning of the
invention or of any exemplified term. Likewise, the invention is not
limited to various embodiments given in this specification.

[0035]As used herein, "around", "about" or "approximately" shall generally
mean within 20 percent, preferably within 10 percent, and more preferably
within 5 percent of a given value or range. Numerical quantities given
herein are approximate, meaning that the term "around", "about" or
"approximately" can be inferred if not expressly stated.

[0036]As used herein, the terms "comprising," "including," "having,"
"containing," "involving," and the like are to be understood to be
open-ended, i.e., to mean including but not limited to.

[0037]The description will be made as to the embodiments of the present
invention in conjunction with the accompanying drawings in FIGS. 1-6. In
accordance with the purposes of this invention, as embodied and broadly
described herein, this invention, in one aspect, relates to a shift
register with embedded bidirectional scanning function.

[0038]Referring to FIGS. 1 and 2, and in particular to FIG. 1, a shift
register 100 is shown according to one embodiment of the present
invention. The shift register 100 includes a first control line 111 for
providing a first control signal, Bi1, a second control line 112 for
providing a second control signal, Bi2, a first clock signal line 113 for
providing a first clock signal, CK, a second clock signal line 114 for
providing a second clock signal, XCK, a reference line 115 for providing
a reference voltage, VSS, and a plurality of stages, {Sj}, j=1, 2, .
. . , N, N being a positive integer, electrically coupled to each other
in series. Further, the shift register 100 also includes a first start
pulse input line 116 for providing a first start pulse, STP, and a second
pulse input line 117 for providing a second start pulse, ENDP. The first
start pulse STP servers as a start pulse signal in a forward function
operation of the shift register 100, and the second start pulse ENDP
servers as a start pulse signal in a backward function operation of the
shift register 100.

[0039]The first control line 111, the second control line 112, the first
clock signal line 113, the second clock signal line 114, and the
reference line 115 constitute a data bus formed on the periphery of a
substrate of a display panel (not shown). The plurality of stages,
{Sj} is also formed on the substrate adjacent to the data bus. The
data bus may also include the first and second pulse input lines 116 and
117. In one embodiment, the first and second pulse input lines 116 and
117 may correspond to first and second dummy circuits/stages for
generating the first and second start pulses STP and ENDP, respectively.

[0040]As shown in FIG. 2, each stage Sj includes an output for
outputting a scanning signal, g(j), and first to fourth transistors
M1-M4. The first to fourth transistors M1-M4 are field-effect thin film
transistors or the like.

[0041]The first transistor M1 has a gate electrically coupled to the
output of the immediately prior stage Sj-1 for receiving the output
scanning signal g(j-1) therefrom, a drain electrically coupled to the
node BP, and a source electrically coupled to one of the first and second
control signal lines 111 and 112 for receiving a corresponding control
signal Bi1/Bi2 therefrom, respectively.

[0042]The second transistor M2 has a gate electrically coupled to the
output of the immediately next stage Sj+1 for receiving the output
scanning signal g(j+1) therefrom, a drain electrically coupled to the
drain of the first transistor M1, and a source electrically coupled to
the source of the first transistor M1, respectively.

[0043]The third transistor M3 has a gate electrically coupled to the node
BP, a drain electrically coupled to one of the first and second clock
signal lines 113 and 114 for receiving a corresponding clock signal
CK/XCK therefrom, and a source electrically coupled to the output for
outputting the scanning signal g(j) of the stage Sj, respectively.

[0044]The fourth transistor M4 has a gate, a drain electrically coupled to
the source of the third transistor M3, and a source electrically coupled
to the reference signal line 115 for receiving the reference voltage VSS
therefrom, respectively.

[0045]For the first stage S1, the gate of the first transistor M1 is
electrically coupled to the first start pulse input line 116 for
receiving the first start pulse STP therefrom. For the very last, N-th
stage SN, the gate of the second transistor M2 is electrically
coupled to the second start pulse input line 117 for receiving the second
start pulse ENDP therefrom.

[0046]Further, each stage Sj (j=1, 2, 3, . . . , N) also includes a
disable circuit electrically coupled between the node BP, the reference
signal line 115 and the gate of the fourth transistor M4. The disable
circuit is configured operably to generate one or more signals responsive
to the input pulses so as to disable the shifter register when an
abnormal state occurs.

[0047]As shown in FIG. 1, in this exemplary embodiment, the source of the
first transistor M1 of the first stage S1 and the source of the
first transistor M1 of the second stage S2 are electrically coupled
to the first control signal line 111 for receiving the first control
signal Bi1 therefrom, while the source of the first transistor M1 of the
third stage S3 and the source of the first transistor M1 of the
fourth stage S4 are electrically coupled to the second control
signal line 112 for receiving the second control signal Bi2 therefrom.
Generally, the sources of the first transistors M1 of each two adjacent
stages Sk and Sk+1 are electrically coupled to one of the first
and second control signal lines 111 and 112 for receiving the
corresponding control signal Bi1/Bi2 therefrom, and the sources of the
first transistors M1 of each next two adjacent stages Sk+2 and
Sk+3 are electrically coupled to the other of the first and second
control signal lines 111 and 112 for receiving the corresponding control
signal Bi1/Bi2 therefrom, where k=1, 5, 9, . . . , (N-4).

[0048]The drain of the third transistor M3 of the first stage S1 is
electrically coupled to the first clock signal line for receiving the
first clock signal CK therefrom, and the drain of the third transistor M3
of the second stage S2 is electrically coupled to the second clock
signal line for receiving the second clock signal XCK therefrom.
Generally, the drain of the third transistor M3 of the stage Sj is
electrically coupled to one of the first and second clock signal lines
when j is an odd number, while the drain of the third transistor M3 of
the stage Sj is electrically coupled to the other of the first and
second clock signal lines when j is an even number.

[0049]An operation procedure of the shift register 100 is described with
reference to the stage circuit shown in FIGS. 1 and 2 and the driving
waveforms (timing charts) illustrated in FIGS. 3 and 4. For such a
configuration of the shift register, the forward and backward shift
directions of a pulse signal can be controlled by the relative phase or
timing order between the first control signal Bi1 and the first clock
signal CK.

[0050]In this exemplary embodiment, each of the first control signal Bi1,
the second control signal Bi2, the first clock signal CK and the second
clock signal XCK is characterized with a period and a phase. The periods
of the first and second control signals Bi1 and Bi2 are identical, as
indicated by TB, while the phases of the first and second control
signals Bi1 and Bi2 are opposite to each other. Further, the periods of
the first and second clock signals CK and XCK are identical, as indicated
by TC, while the phases of the first and second clock signals CK and
XCK are opposite to each other. According to the present invention,
TB=(2*B*T) and TC=(2*C*T), where T is a pulse width of the
scanning signal g(j), or the start pulse STP/ENDP, and B and C are
constants satisfying the relationship of B=2*C. Preferably, C=1.

[0051]FIGS. 3 and 4(a) show the timing charts of the signals of the shift
register in the forward function operation.

[0052]At first, during the time period of (t1-t0), the start pulse STP
having a high level voltage from time t0 to t1 is applied to the gate of
the first transistor M1 of the first stage S1. Accordingly, the
first transistor M1 of the first stage S1 is turned on, and the
boost point BP is charged by the high level voltage of the first control
signal Bi1, which, in turn, turns on the third transistor M3. However,
the first clock signal CK at the time period is in its low level voltage.
Thus, the output signal g(1) of the first stage S1 is in the low
level voltage, or no signal pulse is output from the first stage.

[0053]During the time period of (t2-t1), the third transistor M3 of the
first stage S1 is still turned on because of the voltage level
charged in the boost point BP. Accordingly, the output signal g(1) of the
first stage S1 has a pulse that is corresponding to the pulse of the
first clock signal CK. Meanwhile, the output pulse g(1) from the first
stage S1 is applied to the gate of the first transistor M1 of the
second stage S2. As a result, the first transistor M1 is turned on,
and the boost point BP is charged by the high level voltage of the first
control signal Bi1, which, in turn, turns on the third transistor M3 of
the second stage S2. However, the second clock signal XCK at the
time period is in its low level voltage. Thus, the output signal g(2) of
the second stage S2 is in the low level voltage, or no signal pulse
is output from the second stage S2.

[0054]During the time period of (t3-t2), the third transistor M3 of the
second stage S2 is still turned on because of the voltage level
charged in the boost point BP. Accordingly, the output signal g(2) of the
second stage S2 has a pulse that is corresponding to the pulse of
the second clock signal XCK. Meanwhile, the output pulse g(2) from the
second stage S2 is applied to the gate of the first transistor M1 of
the third stage S3. As a result, the first transistor M1 is turned
on, and the boost point BP is charged by the high level voltage of the
second control signal Bi2, which, in turn, turns on the third transistor
M3 of the third stage S3. However, the first clock signal CK at the
time period is in its low level voltage. Thus, the output signal g(3) of
the third stage S3 is in the low level voltage, or no signal pulse
is output from the third stage S3.

[0055]Similarly, during the time period of (t4-t3), the third stage
S3 outputs a signal g(3) having a pulse corresponding to the pulse
of the first clock signal CK; during the time period of (t5-t4), the
fourth stage S4 outputs a signal g(4) having a pulse corresponding
to the pulse of the second clock signal XCK; and so on. Each of the
output pulses, g(1), g(2), g(3), g(4), . . . , and g(N) is sequentially
shifted in the forward shift direction by one clock. The M4 is turned on
by the signal from the disable circuit to help keeping g(N) at the
voltage value VSS, which can be low voltage part of the first and second
clock signals CK or XCK, except during the time period of the gate pulse
output.

[0056]In the backward function operation, the start pulse ENDP is shifted
from the N-th stage SN to the first stage S1 by control the
timing relations/orders of the signals CK, XCK, Bi1 and Bi2. FIG. 4(b)
shows the timing charts of the signals of the shift register in the
backward function operation, where the signal shifting starts from, for
example, the pulse of the output signal g(4) of the fourth stage S4,
which has a high level voltage pulse from time t0 to t1. When the output
signal g(4) of the fourth stage S4 is applied to the gate of the
second transistor M2 of the third stage S3, it turns on the second
transistor M2 is turned on during the time period of (t1-t0).
Consequently, the boost point BP is charged by the high level voltage of
the second control signal Bi2, which, in turn, turns on the third
transistor M3 of the third stage S3. However, the first clock signal
CK at the time period is in its low level voltage. Thus, the output
signal g(3) of the third stage S3 is in the low level voltage, or no
signal pulse is output from the third stage S3 during the time
period of (t1-t0).

[0057]During the time period of (t2-t1), the third transistor M3 of the
third stage S3 is still turned on because of the voltage level
charged in the boost point BP. Accordingly, the output signal g(3) of the
third stage S3 has a pulse that is corresponding to the pulse of the
second clock signal XCK. Meanwhile, the output pulse g(3) from the third
stage S3 is applied to the gate of the first transistor M1 of the
second stage S2. As a result, the first transistor M1 is turned on,
and the boost point BP is charged by the high level voltage of the second
control signal Bi1, which, in turn, turns on the third transistor M3 of
the second stage S2. However, the first clock signal CK at the time
period is in its low level voltage. Thus, the output signal g(2) of the
second stage S2 is in the low level voltage, or no signal pulse is
output from the third stage S2.

[0058]Similarly, during the time period of (t3-t2), the second stage
S2 outputs a signal g(2) having a pulse corresponding to the pulse
of the first clock signal CK; during the time period of (t4-t3), the
first stage S1 outputs a signal g(1) having a pulse corresponding to
the pulse of the second clock signal XCK; and so on. Each of the output
pulses, g(N), g(N-1), g(N-2), g(N-3), . . . , and g(1) is sequentially
shifted in the backward shift direction by one clock.

[0059]FIG. 5 shows a shift register 500 according to another embodiment of
the present invention. The shift register 500 includes a gate-on-array
(GOA) shift register circuit 510 and a second GOA shift register circuit
520, which are formed on the left and right sides, respectively, of a
display panel such that a pixel matrix 530 of the display panel is
located between the first and second GOA shift register circuits 510 and
520.

[0060]Each of the first and second GOA shift register circuits 510 and 520
has the same configuration as that of the shift register 100 shown in
FIG. 1 and described above. However, the output signals {g(j)_L} of the
first GOA shift register circuit 510 are operably applied to the odd
number rows of the pixel matrix 530, respectively, while the output
signals {g(j)_R} of the second GOA shift register circuit 520 are
operably applied to the even number rows of the pixel matrix 530,
respectively.

[0061]The first control signal, the second control signal, the first clock
signal and the second clock signal applied to the first GOA shift
register circuit 510 are denoted by Bi1_L, Bi2_L, CK_L and XCK_L,
respectively. The first control signal, the second control signal, the
first clock signal and the second clock signal applied to the second GOA
shift register circuit 520 are denoted by Bi1_R, Bi2_R, CK_R and XCK_R,
respectively. Each of the first control signal Bi1_L/Bi1_R, the second
control signal Bi2_L/Bi2_R, the first clock signal CK_L/CK_R and the
second clock signal XCK_L/XCK_R is an AC signal characterized with a
period and a phase, wherein the periods of the first and second control
signals Bi1_L/Bi1_R and Bi2_L/Bi2_R are identical and the phases of the
first and second control signals Bi1_L/Bi1_R and Bi2_L/Bi2_R are opposite
to each other, wherein the periods of the first and second clock signals
CK_L/CK_R and XCK_L/XCK_R are identical and the phases of the first and
second clock signals CK_L/CK_R and XCK_L/XCK_R are opposite to each
other.

[0062]FIGS. 6(a) and 6(b) show the timing charts of the signals of the
shift register 500 in the forward function operation and the backward
function operation, respectively.

[0063]At first a start pulse (Bi1_L) turn on the transistor M1 of first
stage at left side and applies a high level voltage to boost point BP.
During the time period of (t4-t2) the transistor M1 of the first stage
S1--L is still turned on because of the voltage level charged
in the boost point BP. Accordingly, the output signal g(1)_L of the first
stage S1--L has a pulse that is corresponding to the pulse of
the first clock signal CK_L. Similarly the output signal g(3)_L of the
third stage S3--L has a pulse that is corresponding to the
pulse of the second clock signal XCK_L; and so on. Each of the output
pulses, g(1)_L, g(3)_L, g(5)_L, g(7)_L, . . . , and g(2N-1)_L is
sequentially shifted in the forward shift direction by one clock. At
right side the start pulse (Bi1_R) has a π/4 phase delay to left side
(Bi1_L), so the output signal g(2)_R of S2--R has a pulse
rising at the middle point of the g(1)_L pulse and falling at the middle
point of the g(3)_L pulse; and so on. Each of the output pulses, g(2)_R,
g(4)_R, g(6)_R, g(8)_R, . . . , and g(2N)_R is sequentially shifted in
the forward shift direction by another one clock. And the output signals
of right side stage and left side stage are sequentially shifted
alternatively.

[0064]In the backward scan mode the start pulse is applied to transistor
M1 of stage S2N--R. And according to the same principle the
output signals can shift sequentially from g(2N)_R to g(1)_L
alternatively by exchange signal Bi1_L with Bi1_R and Bi2_L with Bi2_R.

[0065]The present invention, among other things, discloses a shift
register having a plurality of stages electrically coupled to each other
in series. Each stage includes a first and second TFT transistor. The
first TFT transistor has a get electrically coupled to the output of the
immediately prior stage, a drain electrically coupled to the boost point
of the stage, and a source configured to receive one of the first and
second control signals. The second TFT transistor has a get electrically
coupled to the output of the immediately next stage, a drain and a source
electrically coupled the drain and source of the first transistor,
respectively. For such a configuration, the stage can operate in a
forward mode or a backward mode by changing the polarity of the first and
second control signals. Accordingly, the invented shift register needs no
additional 2-to-2 bi-directional control circuit, thereby reducing power
consumption and manufacture costs. Additionally, no additional 2-to-2
bi-directional control circuit in the invented shift register causes no
voltage drop in the input signals, which makes the signal trigger levels
of the shift register higher, therefore operation responses of the shift
register faster, and the shift register more reliable.

[0066]The foregoing description of the exemplary embodiments of the
invention has been presented only for the purposes of illustration and
description and is not intended to be exhaustive or to limit the
invention to the precise forms disclosed. Many modifications and
variations are possible in light of the above teaching.

[0067]The embodiments were chosen and described in order to explain the
principles of the invention and their practical application so as to
enable others skilled in the art to utilize the invention and various
embodiments and with various modifications as are suited to the
particular use contemplated. Alternative embodiments will become apparent
to those skilled in the art to which the present invention pertains
without departing from its spirit and scope. Accordingly, the scope of
the present invention is defined by the appended claims rather than the
foregoing description and the exemplary embodiments described therein.