[Strained Si wafer technology for high-speed LSI]Although Si-LSI technology has achieved high-speed and low-power-consumption devices by device shrinkage, there is a possibility that the device shrinkage will encounter difficulties. Thus, next-generation LSI technology requires an alternative method of achieving high-performance devices. A strained Si/SiGe heterostructure has a large potential, because Si on strain-relaxed SiGe receives tensile strain, causing the enhancement of carrier mobility. We have demonstrated a 200 mm strained-Si wafer fabrication technique. In this report, we introduce this fabrication technique and the electrical properties of the fabricated wafer. A test circuit was also fabricated to characterize the quality of the strained Si wafer. In addition, we introduce a technique of enhancing the strain relaxation of a SiGe virtual substrate on SiO2. , [URL].