IEDM: A perspective from afar

Stuck in snowy Ottawa, I missed the IEEE International Electron Devices Meeting in San Francisco, but the press kit offered more than enough fodder for a column.

Given the time of year, it would not be appropriate to be so blunt as to describe my style of introduction for recent columns as "habitual." As we move through the holiday season, allow me to view this method of reflection as "traditional."

Once again, I want to pause to look back at the previous edition of Dew Point. Pure Internet trollery aside, the most a writer can really aspire to is for his or her work to generate discussion. I want to thank the people who have contributed interesting, useful, and most of all, thoughtful comments on my posts here on EE Times. I have been sincerely delighted with the reader community for sharing their own insights. The motivation to comment is often rooted in the desire to correct or offer a different viewpoint. And that's the whole idea. So considering that reader responses agreeing with the author are generally more rare, it is amazing that each and every comment has been polite and positive. I am truly privileged for my opportunity here, and I hope that the EE Times community will continue this tradition thereby allowing comments and forums to remain free, open, and largely unregulated.

Speaking of reader comments and forums, few have ever been as lively as the responses to Peter Clarke's piece, "Update: PCM found in handset." I believe it has provided a lot of valuable information and analysis about phase change memory technology.

The discussion includes comments from RG Neale who wrote a long essay in two parts here on EE Times, "PCM scalability--Myth or realistic device projection," not to mention that he was a co-author with Gordon Moore on a seminal article on chalcogenide memories in 1970. ("Nonvolatile and reprogrammable the read-mostly memory is here," By R.G. Neale, D.L.Nelson, and Gordon E Moore, Electronics, September 1970).

But if the discussion flowing from Clarke's article has not provided you with technical insights and some new outlook on the non-volatile memory debate and the incessant, "Flash is dying and here is my replacement," it would be difficult to argue the entertainment value.

Some of my perspective might be attributable to the fact I am stuck here in blustery, cold, snowy Ottawa and missed the IEEE International Electron Devices Meeting in San Francisco. That said, I still believe that the reported appearance of PCM in a consumer product is overshadowing research showing continued scalability of tried and true floating gate flash. The Intel-Micron collaboration's paper disclosing their 25-nm flash was highlighted in the IEDM press kit. The paper discloses the use of air gaps used to isolate both wordlines and bitlines. That is a neat bit of process engineering at the gate level to reduce the inter-cell interference from unintentional coupling between floating gates. Scaling conventional flash structures to smaller nodes while maintaining coupling between wordlines and floating gates means that the gate stacks are tall and thin. The downside of that is that it also increases coupling and interference between neighboring cells. Since there's no lower K material than nothing at all, the air gap NAND is the best solution.

Years ago, before copper became a mainstay, there were some IBM microprocessors containing what looked suspiciously like air gaps. Knowing what the process architect had in mind would have simplified the analysis considerably. The images supplied by IEDM look like so many reverse engineering construction analyses we have seen over the years.

Readers of those reports are doubtless familiar with the analyst phrase, "the perceived gap in the dielectric layer may have been exaggerated by sample preparation." That's a nice way of saying the seam where a conformal layer met in a gap created a weakpoint that may have been blown out by either a chemical or mechanical process used to prepare the cross-section. The regularity of NAND flash arrays means that it would be relatively easy to tune the process for conformal dielectric coating so that it simply did not fill the gaps at all. (My apologies to the process engineers out there. By "easy" I really mean less difficult than lots of other recipes you develop.)

Several other bloggers have already covered the Intel-Micron air gap flash. As Dick James pointed out on his Chipworks site, "IBM proposed air gap technology as the final stop on the copper / low-k interconnect roadmap." That announcement in 2007 was used for their 10 years / 10 breakthroughs graphic. Looking back at the IBM poster, I realized that a decade of innovation launched with copper interconnect paralleled my career in semiconductor reverse engineering. It's amazing to look back at how futuristic copper seemed then compared with how everyday it has become. I wonder if we will eventually have a similar view of more recent innovations like metal gates and high-K dielectrics or if today's pace of change won't allow such fond memories reaching back so many years.

Don: a quick comment on air gaps. Since air has the lowest possible dielectric constant its use in silicon has been contemplated for several years to reduce parasitic capacitance. I believe the concept was first used by STM by introducing Silicon on Nothing (SON) technology for MOSFET. Others followed, there are a few patents on use of air gaps. I guess the challenge is on how to make them reliably and prevent anything (moisture?) getting inside them. But sealing silicon die seems easy to so where is the challenge? Anyone? Kris