Using FPGAs to build a compact, low cost, and low power Ethernet-to-Network Processor bridge

As carriers and cable providers begin rolling out triple-play and VoD services to their customers, OEMs are increasing their development efforts to roll out IP- (Internet Protocol) based systems, including PONs, CMTS, IP DSLAMs and other access and last-mile equipment. The common underlying physical layer for this is the ubiquitous Ethernet technology, now coupled with sophisticated QoS (Quality of Service) overlays.

Within this context, design engineers are devoting more design effort to connect their switched Ethernet backplanes to the system line cards and, specifically, to their Network Processors. System architects often select Ethernet Switches and Network Processors based on their individual features and rarely consider the challenge of interconnecting the two.

Design engineers are then left with the challenge of developing the bridge, fitting the solution and implementing it cost effectively. Moreover, because both interfaces run at very high speeds, power is also a significant concern. All of these challenges are addressed in this article.

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