//===-- SelectionDAGBuilder.h - Selection-DAG building --------*- C++ -*---===////// The LLVM Compiler Infrastructure//// This file is distributed under the University of Illinois Open Source// License. See LICENSE.TXT for details.////===----------------------------------------------------------------------===////// This implements routines for translating from LLVM IR into SelectionDAG IR.////===----------------------------------------------------------------------===//#ifndef LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H#define LLVM_LIB_CODEGEN_SELECTIONDAG_SELECTIONDAGBUILDER_H#include"StatepointLowering.h"#include"llvm/ADT/APInt.h"#include"llvm/ADT/DenseMap.h"#include"llvm/CodeGen/Analysis.h"#include"llvm/CodeGen/SelectionDAG.h"#include"llvm/CodeGen/SelectionDAGNodes.h"#include"llvm/IR/CallSite.h"#include"llvm/IR/Statepoint.h"#include"llvm/IR/Constants.h"#include"llvm/Support/ErrorHandling.h"#include"llvm/Target/TargetLowering.h"#include<vector>namespacellvm{classAddrSpaceCastInst;classAliasAnalysis;classAllocaInst;classBasicBlock;classBitCastInst;classBranchInst;classCallInst;classDbgValueInst;classExtractElementInst;classExtractValueInst;classFCmpInst;classFPExtInst;classFPToSIInst;classFPToUIInst;classFPTruncInst;classFunction;classFunctionLoweringInfo;classGetElementPtrInst;classGCFunctionInfo;classICmpInst;classIntToPtrInst;classIndirectBrInst;classInvokeInst;classInsertElementInst;classInsertValueInst;classInstruction;classLoadInst;classMachineBasicBlock;classMachineInstr;classMachineRegisterInfo;classMDNode;classMVT;classPHINode;classPtrToIntInst;classReturnInst;classSDDbgValue;classSExtInst;classSelectInst;classShuffleVectorInst;classSIToFPInst;classStoreInst;classSwitchInst;classDataLayout;classTargetLibraryInfo;classTargetLowering;classTruncInst;classUIToFPInst;classUnreachableInst;classVAArgInst;classZExtInst;//===----------------------------------------------------------------------===///// SelectionDAGBuilder - This is the common target-independent lowering/// implementation that is parameterized by a TargetLowering object.///classSelectionDAGBuilder{/// CurInst - The current instruction being visitedconstInstruction*CurInst;DenseMap<constValue*,SDValue>NodeMap;/// UnusedArgNodeMap - Maps argument value for unused arguments. This is used/// to preserve debug information for incoming arguments.DenseMap<constValue*,SDValue>UnusedArgNodeMap;/// DanglingDebugInfo - Helper type for DanglingDebugInfoMap.classDanglingDebugInfo{constDbgValueInst*DI;DebugLocdl;unsignedSDNodeOrder;public:DanglingDebugInfo():DI(nullptr),dl(DebugLoc()),SDNodeOrder(0){}DanglingDebugInfo(constDbgValueInst*di,DebugLocDL,unsignedSDNO):DI(di),dl(DL),SDNodeOrder(SDNO){}constDbgValueInst*getDI(){returnDI;}DebugLocgetdl(){returndl;}unsignedgetSDNodeOrder(){returnSDNodeOrder;}};/// DanglingDebugInfoMap - Keeps track of dbg_values for which we have not/// yet seen the referent. We defer handling these until we do see it.DenseMap<constValue*,DanglingDebugInfo>DanglingDebugInfoMap;public:/// PendingLoads - Loads are not emitted to the program immediately. We bunch/// them up and then emit token factor nodes when possible. This allows us to/// get simple disambiguation between loads without worrying about alias/// analysis.SmallVector<SDValue,8>PendingLoads;/// State used while lowering a statepoint sequence (gc_statepoint,/// gc_relocate, and gc_result). See StatepointLowering.hpp/cpp for details.StatepointLoweringStateStatepointLowering;private:/// PendingExports - CopyToReg nodes that copy values to virtual registers/// for export to other blocks need to be emitted before any terminator/// instruction, but they have no other ordering requirements. We bunch them/// up and the emit a single tokenfactor for them just before terminator/// instructions.SmallVector<SDValue,8>PendingExports;/// SDNodeOrder - A unique monotonically increasing number used to order the/// SDNodes we create.unsignedSDNodeOrder;enumCaseClusterKind{/// A cluster of adjacent case labels with the same destination, or just one/// case.CC_Range,/// A cluster of cases suitable for jump table lowering.CC_JumpTable,/// A cluster of cases suitable for bit test lowering.CC_BitTests};/// A cluster of case labels.structCaseCluster{CaseClusterKindKind;constConstantInt*Low,*High;union{MachineBasicBlock*MBB;unsignedJTCasesIndex;unsignedBTCasesIndex;};uint32_tWeight;staticCaseClusterrange(constConstantInt*Low,constConstantInt*High,MachineBasicBlock*MBB,uint32_tWeight){CaseClusterC;C.Kind=CC_Range;C.Low=Low;C.High=High;C.MBB=MBB;C.Weight=Weight;returnC;}staticCaseClusterjumpTable(constConstantInt*Low,constConstantInt*High,unsignedJTCasesIndex,uint32_tWeight){CaseClusterC;C.Kind=CC_JumpTable;C.Low=Low;C.High=High;C.JTCasesIndex=JTCasesIndex;C.Weight=Weight;returnC;}staticCaseClusterbitTests(constConstantInt*Low,constConstantInt*High,unsignedBTCasesIndex,uint32_tWeight){CaseClusterC;C.Kind=CC_BitTests;C.Low=Low;C.High=High;C.BTCasesIndex=BTCasesIndex;C.Weight=Weight;returnC;}};typedefstd::vector<CaseCluster>CaseClusterVector;typedefCaseClusterVector::iteratorCaseClusterIt;structCaseBits{uint64_tMask;MachineBasicBlock*BB;unsignedBits;uint32_tExtraWeight;CaseBits(uint64_tmask,MachineBasicBlock*bb,unsignedbits,uint32_tWeight):Mask(mask),BB(bb),Bits(bits),ExtraWeight(Weight){}CaseBits():Mask(0),BB(nullptr),Bits(0),ExtraWeight(0){}};typedefstd::vector<CaseBits>CaseBitsVector;/// Sort Clusters and merge adjacent cases.voidsortAndRangeify(CaseClusterVector&Clusters);/// CaseBlock - This structure is used to communicate between/// SelectionDAGBuilder and SDISel for the code generation of additional basic/// blocks needed by multi-case switch statements.structCaseBlock{CaseBlock(ISD::CondCodecc,constValue*cmplhs,constValue*cmprhs,constValue*cmpmiddle,MachineBasicBlock*truebb,MachineBasicBlock*falsebb,MachineBasicBlock*me,uint32_ttrueweight=0,uint32_tfalseweight=0):CC(cc),CmpLHS(cmplhs),CmpMHS(cmpmiddle),CmpRHS(cmprhs),TrueBB(truebb),FalseBB(falsebb),ThisBB(me),TrueWeight(trueweight),FalseWeight(falseweight){}// CC - the condition code to use for the case block's setcc nodeISD::CondCodeCC;// CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.// Emit by default LHS op RHS. MHS is used for range comparisons:// If MHS is not null: (LHS <= MHS) and (MHS <= RHS).constValue*CmpLHS,*CmpMHS,*CmpRHS;// TrueBB/FalseBB - the block to branch to if the setcc is true/false.MachineBasicBlock*TrueBB,*FalseBB;// ThisBB - the block into which to emit the code for the setcc and branchesMachineBasicBlock*ThisBB;// TrueWeight/FalseWeight - branch weights.uint32_tTrueWeight,FalseWeight;};structJumpTable{JumpTable(unsignedR,unsignedJ,MachineBasicBlock*M,MachineBasicBlock*D):Reg(R),JTI(J),MBB(M),Default(D){}/// Reg - the virtual register containing the index of the jump table entry//. to jump to.unsignedReg;/// JTI - the JumpTableIndex for this jump table in the function.unsignedJTI;/// MBB - the MBB into which to emit the code for the indirect jump.MachineBasicBlock*MBB;/// Default - the MBB of the default bb, which is a successor of the range/// check MBB. This is when updating PHI nodes in successors.MachineBasicBlock*Default;};structJumpTableHeader{JumpTableHeader(APIntF,APIntL,constValue*SV,MachineBasicBlock*H,boolE=false):First(F),Last(L),SValue(SV),HeaderBB(H),Emitted(E){}APIntFirst;APIntLast;constValue*SValue;MachineBasicBlock*HeaderBB;boolEmitted;};typedefstd::pair<JumpTableHeader,JumpTable>JumpTableBlock;structBitTestCase{BitTestCase(uint64_tM,MachineBasicBlock*T,MachineBasicBlock*Tr,uint32_tWeight):Mask(M),ThisBB(T),TargetBB(Tr),ExtraWeight(Weight){}uint64_tMask;MachineBasicBlock*ThisBB;MachineBasicBlock*TargetBB;uint32_tExtraWeight;};typedefSmallVector<BitTestCase,3>BitTestInfo;structBitTestBlock{BitTestBlock(APIntF,APIntR,constValue*SV,unsignedRg,MVTRgVT,boolE,MachineBasicBlock*P,MachineBasicBlock*D,BitTestInfoC):First(F),Range(R),SValue(SV),Reg(Rg),RegVT(RgVT),Emitted(E),Parent(P),Default(D),Cases(std::move(C)){}APIntFirst;APIntRange;constValue*SValue;unsignedReg;MVTRegVT;boolEmitted;MachineBasicBlock*Parent;MachineBasicBlock*Default;BitTestInfoCases;};/// Minimum jump table density, in percent.enum{MinJumpTableDensity=40};/// Check whether a range of clusters is dense enough for a jump table.boolisDense(constCaseClusterVector&Clusters,unsigned*TotalCases,unsignedFirst,unsignedLast);/// Build a jump table cluster from Clusters[First..Last]. Returns false if it/// decides it's not a good idea.boolbuildJumpTable(CaseClusterVector&Clusters,unsignedFirst,unsignedLast,constSwitchInst*SI,MachineBasicBlock*DefaultMBB,CaseCluster&JTCluster);/// Find clusters of cases suitable for jump table lowering.voidfindJumpTables(CaseClusterVector&Clusters,constSwitchInst*SI,MachineBasicBlock*DefaultMBB);/// Check whether the range [Low,High] fits in a machine word.boolrangeFitsInWord(constAPInt&Low,constAPInt&High);/// Check whether these clusters are suitable for lowering with bit tests based/// on the number of destinations, comparison metric, and range.boolisSuitableForBitTests(unsignedNumDests,unsignedNumCmps,constAPInt&Low,constAPInt&High);/// Build a bit test cluster from Clusters[First..Last]. Returns false if it/// decides it's not a good idea.boolbuildBitTests(CaseClusterVector&Clusters,unsignedFirst,unsignedLast,constSwitchInst*SI,CaseCluster&BTCluster);/// Find clusters of cases suitable for bit test lowering.voidfindBitTestClusters(CaseClusterVector&Clusters,constSwitchInst*SI);structSwitchWorkListItem{MachineBasicBlock*MBB;CaseClusterItFirstCluster;CaseClusterItLastCluster;constConstantInt*GE;constConstantInt*LT;};typedefSmallVector<SwitchWorkListItem,4>SwitchWorkList;/// Determine the rank by weight of CC in [First,Last]. If CC has more weight/// than each cluster in the range, its rank is 0.staticunsignedcaseClusterRank(constCaseCluster&CC,CaseClusterItFirst,CaseClusterItLast);/// Emit comparison and split W into two subtrees.voidsplitWorkItem(SwitchWorkList&WorkList,constSwitchWorkListItem&W,Value*Cond,MachineBasicBlock*SwitchMBB);/// Lower W.voidlowerWorkItem(SwitchWorkListItemW,Value*Cond,MachineBasicBlock*SwitchMBB,MachineBasicBlock*DefaultMBB);/// A class which encapsulates all of the information needed to generate a/// stack protector check and signals to isel via its state being initialized/// that a stack protector needs to be generated.////// *NOTE* The following is a high level documentation of SelectionDAG Stack/// Protector Generation. The reason that it is placed here is for a lack of/// other good places to stick it.////// High Level Overview of SelectionDAG Stack Protector Generation:////// Previously, generation of stack protectors was done exclusively in the/// pre-SelectionDAG Codegen LLVM IR Pass "Stack Protector". This necessitated/// splitting basic blocks at the IR level to create the success/failure basic/// blocks in the tail of the basic block in question. As a result of this,/// calls that would have qualified for the sibling call optimization were no/// longer eligible for optimization since said calls were no longer right in/// the "tail position" (i.e. the immediate predecessor of a ReturnInst/// instruction).////// Then it was noticed that since the sibling call optimization causes the/// callee to reuse the caller's stack, if we could delay the generation of/// the stack protector check until later in CodeGen after the sibling call/// decision was made, we get both the tail call optimization and the stack/// protector check!////// A few goals in solving this problem were:////// 1. Preserve the architecture independence of stack protector generation.////// 2. Preserve the normal IR level stack protector check for platforms like/// OpenBSD for which we support platform-specific stack protector/// generation.////// The main problem that guided the present solution is that one can not/// solve this problem in an architecture independent manner at the IR level/// only. This is because:////// 1. The decision on whether or not to perform a sibling call on certain/// platforms (for instance i386) requires lower level information/// related to available registers that can not be known at the IR level.////// 2. Even if the previous point were not true, the decision on whether to/// perform a tail call is done in LowerCallTo in SelectionDAG which/// occurs after the Stack Protector Pass. As a result, one would need to/// put the relevant callinst into the stack protector check success/// basic block (where the return inst is placed) and then move it back/// later at SelectionDAG/MI time before the stack protector check if the/// tail call optimization failed. The MI level option was nixed/// immediately since it would require platform-specific pattern/// matching. The SelectionDAG level option was nixed because/// SelectionDAG only processes one IR level basic block at a time/// implying one could not create a DAG Combine to move the callinst.////// To get around this problem a few things were realized:////// 1. While one can not handle multiple IR level basic blocks at the/// SelectionDAG Level, one can generate multiple machine basic blocks/// for one IR level basic block. This is how we handle bit tests and/// switches.////// 2. At the MI level, tail calls are represented via a special return/// MIInst called "tcreturn". Thus if we know the basic block in which we/// wish to insert the stack protector check, we get the correct behavior/// by always inserting the stack protector check right before the return/// statement. This is a "magical transformation" since no matter where/// the stack protector check intrinsic is, we always insert the stack/// protector check code at the end of the BB.////// Given the aforementioned constraints, the following solution was devised:////// 1. On platforms that do not support SelectionDAG stack protector check/// generation, allow for the normal IR level stack protector check/// generation to continue.////// 2. On platforms that do support SelectionDAG stack protector check/// generation:////// a. Use the IR level stack protector pass to decide if a stack/// protector is required/which BB we insert the stack protector check/// in by reusing the logic already therein. If we wish to generate a/// stack protector check in a basic block, we place a special IR/// intrinsic called llvm.stackprotectorcheck right before the BB's/// returninst or if there is a callinst that could potentially be/// sibling call optimized, before the call inst.////// b. Then when a BB with said intrinsic is processed, we codegen the BB/// normally via SelectBasicBlock. In said process, when we visit the/// stack protector check, we do not actually emit anything into the/// BB. Instead, we just initialize the stack protector descriptor/// class (which involves stashing information/creating the success/// mbbb and the failure mbb if we have not created one for this/// function yet) and export the guard variable that we are going to/// compare.////// c. After we finish selecting the basic block, in FinishBasicBlock if/// the StackProtectorDescriptor attached to the SelectionDAGBuilder is/// initialized, we first find a splice point in the parent basic block/// before the terminator and then splice the terminator of said basic/// block into the success basic block. Then we code-gen a new tail for/// the parent basic block consisting of the two loads, the comparison,/// and finally two branches to the success/failure basic blocks. We/// conclude by code-gening the failure basic block if we have not/// code-gened it already (all stack protector checks we generate in/// the same function, use the same failure basic block).classStackProtectorDescriptor{public:StackProtectorDescriptor():ParentMBB(nullptr),SuccessMBB(nullptr),FailureMBB(nullptr),Guard(nullptr),GuardReg(0){}/// Returns true if all fields of the stack protector descriptor are/// initialized implying that we should/are ready to emit a stack protector.boolshouldEmitStackProtector()const{returnParentMBB&&SuccessMBB&&FailureMBB&&Guard;}/// Initialize the stack protector descriptor structure for a new basic/// block.voidinitialize(constBasicBlock*BB,MachineBasicBlock*MBB,constCallInst&StackProtCheckCall){// Make sure we are not initialized yet.assert(!shouldEmitStackProtector()&&"Stack Protector Descriptor is ""already initialized!");ParentMBB=MBB;SuccessMBB=AddSuccessorMBB(BB,MBB,/* IsLikely */true);FailureMBB=AddSuccessorMBB(BB,MBB,/* IsLikely */false,FailureMBB);if(!Guard)Guard=StackProtCheckCall.getArgOperand(0);}/// Reset state that changes when we handle different basic blocks.////// This currently includes:////// 1. The specific basic block we are generating a/// stack protector for (ParentMBB).////// 2. The successor machine basic block that will contain the tail of/// parent mbb after we create the stack protector check (SuccessMBB). This/// BB is visited only on stack protector check success.voidresetPerBBState(){ParentMBB=nullptr;SuccessMBB=nullptr;}/// Reset state that only changes when we switch functions.////// This currently includes:////// 1. FailureMBB since we reuse the failure code path for all stack/// protector checks created in an individual function.////// 2.The guard variable since the guard variable we are checking against is/// always the same.voidresetPerFunctionState(){FailureMBB=nullptr;Guard=nullptr;}MachineBasicBlock*getParentMBB(){returnParentMBB;}MachineBasicBlock*getSuccessMBB(){returnSuccessMBB;}MachineBasicBlock*getFailureMBB(){returnFailureMBB;}constValue*getGuard(){returnGuard;}unsignedgetGuardReg()const{returnGuardReg;}voidsetGuardReg(unsignedR){GuardReg=R;}private:/// The basic block for which we are generating the stack protector.////// As a result of stack protector generation, we will splice the/// terminators of this basic block into the successor mbb SuccessMBB and/// replace it with a compare/branch to the successor mbbs/// SuccessMBB/FailureMBB depending on whether or not the stack protector/// was violated.MachineBasicBlock*ParentMBB;/// A basic block visited on stack protector check success that contains the/// terminators of ParentMBB.MachineBasicBlock*SuccessMBB;/// This basic block visited on stack protector check failure that will/// contain a call to __stack_chk_fail().MachineBasicBlock*FailureMBB;/// The guard variable which we will compare against the stored value in the/// stack protector stack slot.constValue*Guard;/// The virtual register holding the stack guard value.unsignedGuardReg;/// Add a successor machine basic block to ParentMBB. If the successor mbb/// has not been created yet (i.e. if SuccMBB = 0), then the machine basic/// block will be created. Assign a large weight if IsLikely is true.MachineBasicBlock*AddSuccessorMBB(constBasicBlock*BB,MachineBasicBlock*ParentMBB,boolIsLikely,MachineBasicBlock*SuccMBB=nullptr);};private:constTargetMachine&TM;public:/// Lowest valid SDNodeOrder. The special case 0 is reserved for scheduling/// nodes without a corresponding SDNode.staticconstunsignedLowestSDNodeOrder=1;SelectionDAG&DAG;constDataLayout*DL;AliasAnalysis*AA;constTargetLibraryInfo*LibInfo;/// SwitchCases - Vector of CaseBlock structures used to communicate/// SwitchInst code generation information.std::vector<CaseBlock>SwitchCases;/// JTCases - Vector of JumpTable structures used to communicate/// SwitchInst code generation information.std::vector<JumpTableBlock>JTCases;/// BitTestCases - Vector of BitTestBlock structures used to communicate/// SwitchInst code generation information.std::vector<BitTestBlock>BitTestCases;/// A StackProtectorDescriptor structure used to communicate stack protector/// information in between SelectBasicBlock and FinishBasicBlock.StackProtectorDescriptorSPDescriptor;// Emit PHI-node-operand constants only once even if used by multiple// PHI nodes.DenseMap<constConstant*,unsigned>ConstantsOut;/// FuncInfo - Information about the function as a whole.///FunctionLoweringInfo&FuncInfo;/// OptLevel - What optimization level we're generating code for.///CodeGenOpt::LevelOptLevel;/// GFI - Garbage collection metadata for the function.GCFunctionInfo*GFI;/// LPadToCallSiteMap - Map a landing pad to the call site indexes.DenseMap<MachineBasicBlock*,SmallVector<unsigned,4>>LPadToCallSiteMap;/// HasTailCall - This is set to true if a call in the current/// block has been translated as a tail call. In this case,/// no subsequent DAG nodes should be created.///boolHasTailCall;LLVMContext*Context;SelectionDAGBuilder(SelectionDAG&dag,FunctionLoweringInfo&funcinfo,CodeGenOpt::Levelol):CurInst(nullptr),SDNodeOrder(LowestSDNodeOrder),TM(dag.getTarget()),DAG(dag),FuncInfo(funcinfo),OptLevel(ol),HasTailCall(false){}voidinit(GCFunctionInfo*gfi,AliasAnalysis&aa,constTargetLibraryInfo*li);/// clear - Clear out the current SelectionDAG and the associated/// state and prepare this SelectionDAGBuilder object to be used/// for a new block. This doesn't clear out information about/// additional blocks that are needed to complete switch lowering/// or PHI node updating; that information is cleared out as it is/// consumed.voidclear();/// clearDanglingDebugInfo - Clear the dangling debug information/// map. This function is separated from the clear so that debug/// information that is dangling in a basic block can be properly/// resolved in a different basic block. This allows the/// SelectionDAG to resolve dangling debug information attached/// to PHI nodes.voidclearDanglingDebugInfo();/// getRoot - Return the current virtual root of the Selection DAG,/// flushing any PendingLoad items. This must be done before emitting/// a store or any other node that may need to be ordered after any/// prior load instructions.///SDValuegetRoot();/// getControlRoot - Similar to getRoot, but instead of flushing all the/// PendingLoad items, flush all the PendingExports items. It is necessary/// to do this before emitting a terminator instruction.///SDValuegetControlRoot();SDLocgetCurSDLoc()const{returnSDLoc(CurInst,SDNodeOrder);}DebugLocgetCurDebugLoc()const{returnCurInst?CurInst->getDebugLoc():DebugLoc();}unsignedgetSDNodeOrder()const{returnSDNodeOrder;}voidCopyValueToVirtualRegister(constValue*V,unsignedReg);voidvisit(constInstruction&I);voidvisit(unsignedOpcode,constUser&I);/// getCopyFromRegs - If there was virtual register allocated for the value V/// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise.SDValuegetCopyFromRegs(constValue*V,Type*Ty);// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,// generate the debug data structures now that we've seen its definition.voidresolveDanglingDebugInfo(constValue*V,SDValueVal);SDValuegetValue(constValue*V);boolfindValue(constValue*V)const;SDValuegetNonRegisterValue(constValue*V);SDValuegetValueImpl(constValue*V);voidsetValue(constValue*V,SDValueNewN){SDValue&N=NodeMap[V];assert(!N.getNode()&&"Already set a value for this node!");N=NewN;}voidsetUnusedArgValue(constValue*V,SDValueNewN){SDValue&N=UnusedArgNodeMap[V];assert(!N.getNode()&&"Already set a value for this node!");N=NewN;}voidFindMergedConditions(constValue*Cond,MachineBasicBlock*TBB,MachineBasicBlock*FBB,MachineBasicBlock*CurBB,MachineBasicBlock*SwitchBB,Instruction::BinaryOpsOpc,uint32_tTW,uint32_tFW);voidEmitBranchForMergedCondition(constValue*Cond,MachineBasicBlock*TBB,MachineBasicBlock*FBB,MachineBasicBlock*CurBB,MachineBasicBlock*SwitchBB,uint32_tTW,uint32_tFW);boolShouldEmitAsBranches(conststd::vector<CaseBlock>&Cases);boolisExportableFromCurrentBlock(constValue*V,constBasicBlock*FromBB);voidCopyToExportRegsIfNeeded(constValue*V);voidExportFromCurrentBlock(constValue*V);voidLowerCallTo(ImmutableCallSiteCS,SDValueCallee,boolIsTailCall,MachineBasicBlock*LandingPad=nullptr);std::pair<SDValue,SDValue>lowerCallOperands(ImmutableCallSiteCS,unsignedArgIdx,unsignedNumArgs,SDValueCallee,Type*ReturnTy,MachineBasicBlock*LandingPad=nullptr,boolIsPatchPoint=false);/// UpdateSplitBlock - When an MBB was split during scheduling, update the/// references that need to refer to the last resulting block.voidUpdateSplitBlock(MachineBasicBlock*First,MachineBasicBlock*Last);// This function is responsible for the whole statepoint lowering process.// It uniformly handles invoke and call statepoints.voidLowerStatepoint(ImmutableStatepointStatepoint,MachineBasicBlock*LandingPad=nullptr);private:std::pair<SDValue,SDValue>lowerInvokable(TargetLowering::CallLoweringInfo&CLI,MachineBasicBlock*LandingPad);// Terminator instructions.voidvisitRet(constReturnInst&I);voidvisitBr(constBranchInst&I);voidvisitSwitch(constSwitchInst&I);voidvisitIndirectBr(constIndirectBrInst&I);voidvisitUnreachable(constUnreachableInst&I);voidvisitCleanupRet(constCleanupReturnInst&I);voidvisitCatchEndPad(constCatchEndPadInst&I);voidvisitCatchRet(constCatchReturnInst&I);voidvisitCatchPad(constCatchPadInst&I);voidvisitTerminatePad(constTerminatePadInst&TPI);voidvisitCleanupPad(constCleanupPadInst&CPI);uint32_tgetEdgeWeight(constMachineBasicBlock*Src,constMachineBasicBlock*Dst)const;voidaddSuccessorWithWeight(MachineBasicBlock*Src,MachineBasicBlock*Dst,uint32_tWeight=0);public:voidvisitSwitchCase(CaseBlock&CB,MachineBasicBlock*SwitchBB);voidvisitSPDescriptorParent(StackProtectorDescriptor&SPD,MachineBasicBlock*ParentBB);voidvisitSPDescriptorFailure(StackProtectorDescriptor&SPD);voidvisitBitTestHeader(BitTestBlock&B,MachineBasicBlock*SwitchBB);voidvisitBitTestCase(BitTestBlock&BB,MachineBasicBlock*NextMBB,uint32_tBranchWeightToNext,unsignedReg,BitTestCase&B,MachineBasicBlock*SwitchBB);voidvisitJumpTable(JumpTable&JT);voidvisitJumpTableHeader(JumpTable&JT,JumpTableHeader&JTH,MachineBasicBlock*SwitchBB);private:// These all get lowered before this pass.voidvisitInvoke(constInvokeInst&I);voidvisitResume(constResumeInst&I);voidvisitBinary(constUser&I,unsignedOpCode);voidvisitShift(constUser&I,unsignedOpcode);voidvisitAdd(constUser&I){visitBinary(I,ISD::ADD);}voidvisitFAdd(constUser&I){visitBinary(I,ISD::FADD);}voidvisitSub(constUser&I){visitBinary(I,ISD::SUB);}voidvisitFSub(constUser&I);voidvisitMul(constUser&I){visitBinary(I,ISD::MUL);}voidvisitFMul(constUser&I){visitBinary(I,ISD::FMUL);}voidvisitURem(constUser&I){visitBinary(I,ISD::UREM);}voidvisitSRem(constUser&I){visitBinary(I,ISD::SREM);}voidvisitFRem(constUser&I){visitBinary(I,ISD::FREM);}voidvisitUDiv(constUser&I){visitBinary(I,ISD::UDIV);}voidvisitSDiv(constUser&I);voidvisitFDiv(constUser&I){visitBinary(I,ISD::FDIV);}voidvisitAnd(constUser&I){visitBinary(I,ISD::AND);}voidvisitOr(constUser&I){visitBinary(I,ISD::OR);}voidvisitXor(constUser&I){visitBinary(I,ISD::XOR);}voidvisitShl(constUser&I){visitShift(I,ISD::SHL);}voidvisitLShr(constUser&I){visitShift(I,ISD::SRL);}voidvisitAShr(constUser&I){visitShift(I,ISD::SRA);}voidvisitICmp(constUser&I);voidvisitFCmp(constUser&I);// Visit the conversion instructionsvoidvisitTrunc(constUser&I);voidvisitZExt(constUser&I);voidvisitSExt(constUser&I);voidvisitFPTrunc(constUser&I);voidvisitFPExt(constUser&I);voidvisitFPToUI(constUser&I);voidvisitFPToSI(constUser&I);voidvisitUIToFP(constUser&I);voidvisitSIToFP(constUser&I);voidvisitPtrToInt(constUser&I);voidvisitIntToPtr(constUser&I);voidvisitBitCast(constUser&I);voidvisitAddrSpaceCast(constUser&I);voidvisitExtractElement(constUser&I);voidvisitInsertElement(constUser&I);voidvisitShuffleVector(constUser&I);voidvisitExtractValue(constExtractValueInst&I);voidvisitInsertValue(constInsertValueInst&I);voidvisitLandingPad(constLandingPadInst&I);voidvisitGetElementPtr(constUser&I);voidvisitSelect(constUser&I);voidvisitAlloca(constAllocaInst&I);voidvisitLoad(constLoadInst&I);voidvisitStore(constStoreInst&I);voidvisitMaskedLoad(constCallInst&I);voidvisitMaskedStore(constCallInst&I);voidvisitMaskedGather(constCallInst&I);voidvisitMaskedScatter(constCallInst&I);voidvisitAtomicCmpXchg(constAtomicCmpXchgInst&I);voidvisitAtomicRMW(constAtomicRMWInst&I);voidvisitFence(constFenceInst&I);voidvisitPHI(constPHINode&I);voidvisitCall(constCallInst&I);boolvisitMemCmpCall(constCallInst&I);boolvisitMemChrCall(constCallInst&I);boolvisitStrCpyCall(constCallInst&I,boolisStpcpy);boolvisitStrCmpCall(constCallInst&I);boolvisitStrLenCall(constCallInst&I);boolvisitStrNLenCall(constCallInst&I);boolvisitUnaryFloatCall(constCallInst&I,unsignedOpcode);boolvisitBinaryFloatCall(constCallInst&I,unsignedOpcode);voidvisitAtomicLoad(constLoadInst&I);voidvisitAtomicStore(constStoreInst&I);voidvisitInlineAsm(ImmutableCallSiteCS);constchar*visitIntrinsicCall(constCallInst&I,unsignedIntrinsic);voidvisitTargetIntrinsic(constCallInst&I,unsignedIntrinsic);voidvisitVAStart(constCallInst&I);voidvisitVAArg(constVAArgInst&I);voidvisitVAEnd(constCallInst&I);voidvisitVACopy(constCallInst&I);voidvisitStackmap(constCallInst&I);voidvisitPatchpoint(ImmutableCallSiteCS,MachineBasicBlock*LandingPad=nullptr);// These three are implemented in StatepointLowering.cppvoidvisitStatepoint(constCallInst&I);voidvisitGCRelocate(constCallInst&I);voidvisitGCResult(constCallInst&I);voidvisitUserOp1(constInstruction&I){llvm_unreachable("UserOp1 should not exist at instruction selection time!");}voidvisitUserOp2(constInstruction&I){llvm_unreachable("UserOp2 should not exist at instruction selection time!");}voidprocessIntegerCallValue(constInstruction&I,SDValueValue,boolIsSigned);voidHandlePHINodesInSuccessorBlocks(constBasicBlock*LLVMBB);/// EmitFuncArgumentDbgValue - If V is an function argument then create/// corresponding DBG_VALUE machine instruction for it now. At the end of/// instruction selection, they will be inserted to the entry BB.boolEmitFuncArgumentDbgValue(constValue*V,DILocalVariable*Variable,DIExpression*Expr,DILocation*DL,int64_tOffset,boolIsIndirect,constSDValue&N);/// Return the next block after MBB, or nullptr if there is none.MachineBasicBlock*NextBlock(MachineBasicBlock*MBB);/// Update the DAG and DAG builder with the relevant information after/// a new root node has been created which could be a tail call.voidupdateDAGForMaybeTailCall(SDValueMaybeTC);};/// RegsForValue - This struct represents the registers (physical or virtual)/// that a particular set of values is assigned, and the type information about/// the value. The most common situation is to represent one value at a time,/// but struct or array values are handled element-wise as multiple values. The/// splitting of aggregates is performed recursively, so that we never have/// aggregate-typed registers. The values at this point do not necessarily have/// legal types, so each value may require one or more registers of some legal/// type.///structRegsForValue{/// ValueVTs - The value types of the values, which may not be legal, and/// may need be promoted or synthesized from one or more registers.///SmallVector<EVT,4>ValueVTs;/// RegVTs - The value types of the registers. This is the same size as/// ValueVTs and it records, for each value, what the type of the assigned/// register or registers are. (Individual values are never synthesized/// from more than one type of register.)////// With virtual registers, the contents of RegVTs is redundant with TLI's/// getRegisterType member function, however when with physical registers/// it is necessary to have a separate record of the types.///SmallVector<MVT,4>RegVTs;/// Regs - This list holds the registers assigned to the values./// Each legal or promoted value requires one register, and each/// expanded value requires multiple registers.///SmallVector<unsigned,4>Regs;RegsForValue();RegsForValue(constSmallVector<unsigned,4>&regs,MVTregvt,EVTvaluevt);RegsForValue(LLVMContext&Context,constTargetLowering&TLI,constDataLayout&DL,unsignedReg,Type*Ty);/// append - Add the specified values to this one.voidappend(constRegsForValue&RHS){ValueVTs.append(RHS.ValueVTs.begin(),RHS.ValueVTs.end());RegVTs.append(RHS.RegVTs.begin(),RHS.RegVTs.end());Regs.append(RHS.Regs.begin(),RHS.Regs.end());}/// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from/// this value and returns the result as a ValueVTs value. This uses/// Chain/Flag as the input and updates them for the output Chain/Flag./// If the Flag pointer is NULL, no flag is used.SDValuegetCopyFromRegs(SelectionDAG&DAG,FunctionLoweringInfo&FuncInfo,SDLocdl,SDValue&Chain,SDValue*Flag,constValue*V=nullptr)const;/// getCopyToRegs - Emit a series of CopyToReg nodes that copies the specified/// value into the registers specified by this object. This uses Chain/Flag/// as the input and updates them for the output Chain/Flag. If the Flag/// pointer is nullptr, no flag is used. If V is not nullptr, then it is used/// in printing better diagnostic messages on error.voidgetCopyToRegs(SDValueVal,SelectionDAG&DAG,SDLocdl,SDValue&Chain,SDValue*Flag,constValue*V=nullptr,ISD::NodeTypePreferredExtendType=ISD::ANY_EXTEND)const;/// AddInlineAsmOperands - Add this value to the specified inlineasm node/// operand list. This adds the code marker, matching input operand index/// (if applicable), and includes the number of values added into it.voidAddInlineAsmOperands(unsignedKind,boolHasMatching,unsignedMatchingIdx,SDLocdl,SelectionDAG&DAG,std::vector<SDValue>&Ops)const;};}// end namespace llvm#endif