CλaSH (pronounced ‘clash’) is a functional hardware description language that
borrows both its syntax and semantics from the functional programming language
Haskell. The CλaSH compiler transforms these high-level descriptions to
low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of CλaSH:

Strongly typed, but with a very high degree of type inference, enabling both
safe and fast prototyping using concise descriptions.

Interactive REPL: load your designs in an interpreter and easily test all
your component without needing to setup a test bench.

Higher-order functions, with type inference, result in designs that are
fully parametric by default.

Synchronous sequential circuit design based on streams of values, called
Signals, lead to natural descriptions of feedback loops.

Alternatively, if you want to explicitly route clock and reset ports,
for more straightforward multi-clock designs, you can import the
Clash.Explicit.Prelude module. Note that you should not import
Clash.Prelude and Clash.Explicit.Prelude at the same time as they
have overlapping definitions.

Readme for clash-prelude-0.99

CλaSH - A functional hardware description language

CλaSH (pronounced ‘clash’) is a functional hardware description language that
borrows both its syntax and semantics from the functional programming language
Haskell. The CλaSH compiler transforms these high-level descriptions to
low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of CλaSH:

Strongly typed, yet with a very high degree of type inference, enabling both
safe and fast prototyping using concise descriptions.

Interactive REPL: load your designs in an interpreter and easily test all
your component without needing to setup a test bench.

Higher-order functions, with type inference, result in designs that are
fully parametric by default.

Synchronous sequential circuit design based on streams of values, called
Signals, lead to natural descriptions of feedback loops.