Verilog-mode

AUTOINST not working with SV parameters array

The AUTOINST does not work for outputs which their width is defined by array of parameters.
The error message is:
Scan error: "Unbalanced parentheses"

Can this be fixed somehow?

The reason for using parameters array is that the design parameters are defined in a package so their values cannot be over-written from the top instance. By using parameters array (defined in the package) we can control with one parameters driven from the Top instance which parameters value to pick out of the array.