Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

This document contains information on products in the design phase of development. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local sales office that you have the latest datasheet before finalizing a design.

The Intel® Server Board Set SE8500HW4 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Intel Corporation server baseboards contain a number of high-density VLSI and power delivery components that need adequate airflow to cool. Intel’s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together. It is the responsibility of the system integrator that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of air flow required for their specific application and environmental conditions. Intel Corporation can not be held responsible if components fail or the Server Board does not operate correctly when used outside any of their published operating or non-operating limits.

Intel, Xeon and XScale are trademarks or registered trademarks of Intel Corporation.

The Intel® Server Board Set SE8500HW4 is the fourth generation of four-way Intel® IA32 Server Boards. The board set uses the Intel® E8500 Chipset, and the next generation of memory and processor technologies. This product diverges from other Intel® server boards and platforms in the following ways:

Addition of PCI Express* technology

Addition of Double Data Rate Two (DDR2) memory

Memory implemented across up to four Memory Boards, with enhanced performance and reliability features

Optional mass storage expansion for Fibre Channel and RAID

Removal of IDE, floppy, and PS/2* ports

The Intel® Server Board Set SE8500HW4 supports up to four 64-bit Intel® Xeon™ Processors MP with up to 8MB L3 cache and incorporates features that clearly differentiate it as a high availability server. Building on previous server platforms, the Intel® Server Board Set SE8500HW4 introduces redundant memory, networking, and the BIOS flash in addition to the enterprise features of hot-swap PCI slots, standards-based server management and serveroriented embedded I/O. Remote monitoring and management features are also included, providing a new level of user tools for server administration.

The Intel® Server Board Set SE8500HW4 consists of two primary boards: Main and Memory. Up to four Memory Boards plug vertically into the Mainboard. The board set was designed to work with the Intel® Server Platform SR4850HW4, a 4U chassis, and the Intel® Server Platform SR6850HW4, a 6U chassis. The board set may also be used in a non-Intel chassis that meets the power and cooling requirements found in this specification. Please refer to the Intel® Server Platform SR4850HW4 Technical Product Specification and Intel® Server Platform SR6850HW4 Technical Product Specification for more information on these products.

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Product Overview

Intel® Server Board Set SE8500HW4

This document describes the Mainboard and Memory Board components of the Intel® Server Board Set SE8500HW4.

Figure 1. Intel® Server Board Set SE8500HW4, Populated

1.1Board Set Features

This chapter discusses the features for the Intel® Server Board Set SE8500HW4, which includes:

Up to four 64-bit Intel® Xeon™ Processors MP with 1MB L2 cache or 64-bit Intel® Xeon™ Processors MP with up to 8MB L3 cache

The Intel® Server Board Set SE8500HW4 supports 64-bit Intel® Xeon™ Processors MP which are based on the Intel® NetBurst™ microarchitecture. Several architectural and microarchitectural enhancements have been added to this processor, including an increased L2 cache size and, for some models, an integrated L3 cache. Table 1 provides a feature set overview of the 64-bit Intel® Xeon™ Processors MP.

Figure 3. 64-bit Intel® Xeon™ Processors MP

Table 1. Processor Feature Overview

Feature

64-bit Intel® Xeon™

64-bit Intel® Xeon™

Processors MP with

Processors MP with up to

1MB L2 cache

8MB L3 cache

Package

FC-

mPGA4

L2 cache size

1MB

L3 cache size

N/A

4MB or 8MB

Core operating voltage

1.0975 to 1.4V

1.171 to 1.3250V

Cache operating voltage

N/A

1.1 to 1.25V

Front side bus

667MHz with data-bus Error Correcting Code (ECC),

bandwidth up to 5.33GB/s

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The 64-bit Intel® Xeon™ Processors MP includes the following advanced features:

Some processor signals do not have on-die termination and must be terminated at an end agent. The Intel® Server Board Set SE8500HW4 Mainboard was designed with two separate Front Side Buses (FSBs). For each bus with a processor installed, the first socket on that bus must be used to ensure proper signal termination. A processor must be installed in socket 1 before socket 2, and socket 3 before socket 4. Refer to Table 2 for processor installation order.

Table 2. Processor Installation Order

Number of

Sockets

VRM 10.2

VRM 9.1

VRM

Processors

J1F1

J1H22

10.2

1

2

3

4

J3F1

One

Installed

Installed

Installed

Installed

Two1

Installed

Installed

Installed

Installed

Installed

Installed

Three1

Installed

Installed

Installed

Installed

Installed

Installed

Installed

Installed

Installed

Installed

Installed

Four

Installed

Installed

Installed

Installed

Installed

Installed

Installed

1.There is no performance gained by splitting the processors across the FSBs. Intel has validated sequential process installation, with a one-processor configuration using socket 1; a two-processor configuration using sockets 1 and 2; and a three-processor configuration using sockets 1, 2 and 3.

2.The 9.1 VRM is only required when installing 64-bit Intel® Xeon™ Processors MP with up to 8MB of L3 cache.

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2.2Intel® E8500 Chipset

The Intel® E8500 Chipset is the highest performance, most scalable platform offering in the 64bit Intel® Xeon™ Processor MP family. The chipset represents the sixth-generation Intel fourway multi-processor platform, is architected for multi-core processors and includes these advanced features:

Support for up to four 64-bit Intel® Xeon™ Processors MP FSB operating at 667 MHz

Maintains coherency across both buses

Double-pumped 40-bit address buses with a total address bandwidth of 167 million addresses/second

The Intel® E8500 Chipset eXtended Memory Bridge (XMB) provides interface between the NB and DDR2 400MHz DIMMs. The Intel® Server Board Set SE8500HW4 includes up to four Memory Boards, each with an XMB and four DDR2 400MHz DIMM locations.

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2.2.3Intel® IOP332 Storage I/O Processor

The Intel® IOP332 Storage I/O Processor contains a PCI Express-to-PCI-X bridge and performs bridging functions between the PCI Express interface of the NB and PCI-X devices. The Intel® Server Board Set SE8500HW4 contains one Intel® IOP332 Storage I/O Processor that has two PCI bus interfaces which provide:

Slots 6 and 7 (PCI-X 100MHz, non-Hot Plug)

LSI Logic 53C1030 Ultra320 SCSI controller

Intel® Fibre Channel Module connector

2.2.4Intel® 82801EB I/O Controller Hub 5 (ICH5)

The Intel® 82801EB I/O Controller Hub 5 (ICH5) provides a hub interface-to-PCI bridge, PCI-to- LPC bridge and legacy I/O controllers. Some of the features of the ICH5 are not used in this board set. The Intel® Server Board Set SE8500HW4 contains one ICH5 which provides:

Integrated Serial ATA (SATA) controller

High-speed USB 2.0 host controller

ATI Radeon 7000 video controller

Support for System Management Bus (SMBus) specification, version 2.0 and I2C

ACPI power management logic support

Firmware Hub (FWH) interface support

2.2.5Intel® 6700 PXH 64-bit Hub (PXH)

The Intel® 6700 PXH 64-bit Hub performs bridging functions between the PCI Express interface of the NB and PCI-X devices. The Intel® Server Board Set SE8500HW4 contains one PXH that has two PCI bus interfaces which provide:

Slot 2 (PCI-X 133Mhz Hot Plug)

Broadcom BCM5704C dual channel Gigabit Ethernet controller

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3.I/O Subsystems

3.1PCI Subsystem

The PCI subsystem consists of eight slots, seven available to standard PCI adapters and one for the Intel® Server Board Set SE8500HW4-specific Intel® Fibre Channel Module.

PCI and PCI-X devices can deliver interrupts either by asserting IRQ signals that are routed to the PXH or Intel® IOP332 Storage I/O Processor IOxAPIC, or over the PCI-X bus via MSI. In either case, the PXH and/or Intel® IOP332 Storage I/O Processor forward the interrupt to the NB as an Inbound Write for the processor to handle the event.

Table 4 describes how the interrupts for each of the PCI devices are mapped to the PXH and Intel® IOP332 Storage I/O Processor.

Table 4. PCI Interrupt Mapping

Device

APIC

INTA#

INTB#

INTC#

INTD#

Broadcom*

PXH (B)

PX2B_IRQ0_N

PX2B_IRQ1_N

BCM5704

Slot 2

PXH (A)

PX2A_IRQ0_N

PX2A_IRQ1_N

PX2A_IRQ2_N

PX2A_IRQ3_N

Slot 6

Intel® IOP332 Storage I/O

PX1B_XINT4_N

PX1B_XINT5_N

PX1B_XINT6_N

PX1B_XINT7_N

Processor (B)

Slot 7

Intel IOP332 Storage I/O

PX1B_XINT6_N

PX1B_XINT7_N

PX1B_XINT4_N

PX1B_XINT5_N

Processor (B)

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Device

APIC

INTA#

INTB#

INTC#

INTD#

LSI Logic*

Intel IOP332 Storage I/O

PX1A_XINT0_N

PX1A_XINT1_N

-

-

53C1030

Processor (A)

Intel® Fibre

Intel IOP332 Storage I/O

PX1A_XINT2_N

PX1A_XINT3_N

-

-

Channel

Processor (A)

Module

3.1.2PCI IDSEL Signal

The IDSEL signal is used as a chip-select for devices during read and write transactions. The PXH and Intel® IOP332 Storage I/O Processor assert a specific address bit on a given PCI bus to toggle the IDSEL signal to the PCI device. For the Intel® Server Board Set SE8500HW4 Mainboard the address bit to IDSEL mapping is shown in Table 5.

Table 5. IDSEL Mapping

Device

Device #

IDSEL

Host Bridge

Broadcom* BCM5704

2

PX2B_AD<18>

PXH (B)

PXH (A)

Slot 2

2

PX2A_AD<18>

Intel® IOP332 Storage I/O

Slot 6

6

PX1B_AD<22>

Processor (B)

Intel IOP332 Storage I/O

Slot 7

7

PX1B_AD<23>

Processor (B)

LSI Logic* 53C1030

5

PX1A_AD<21>

Intel IOP332 Storage I/O

Processor (A)

Intel IOP332 Storage I/O

Intel® Fibre Channel Module

15

PX1A_AD<31>

Processor (A)

Internal to Intel IOP332

ROMB enabled on Intel IOP332

14

n/a

Storage I/O Processor

Storage I/O Processor

Note: When the ROMB solution is enabled, the IDSEL to the LSI Logic 53C1030 is inhibited by the Intel® IOP332 Storage I/O Processor. This effectively hides the SCSI controller from the system and the Intel® IOP332 Storage I/O Processor acts as the SCSI (or RAID) controller. Since the Intel® Fibre Channel Module is attached to the same bus as the SCSI controller, the Intel® Fibre Channel Module is set to device 15 so that it is not affected by the device hiding operation required for the ROMB solution.

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3.1.3Bus Arbitration Signals

Request (REQ#) signals indicate to the bus arbiter that an agent/device desires use of the bus. The Grant (GNT#) signal indicates to the agent/device that access to the bus has been granted. Every master has its own REQ#, which must be tri-stated while RST# is asserted. These are point-to-point signals which are assigned to every bus master.

In the Intel® Server Board Set SE8500HW4 there is one arbiter for each PCI bus on the PXH and Intel® IOP332 Storage I/O Processor. The PXH contains an arbiter for slot 2 and the BCM5704 and the Intel® IOP332 Storage I/O Processor contains an arbiter for slots 6 and 7, LSI Logic 53C1030, and the Intel® Fibre Channel Module.

Table 6. Arbitration Connections

Device

REQ#

GNT#

Host Bridge

Broadcom* BCM5704

PX2B_REQ0_N

PX2B_GNT0_N

PXH (B)

Slot 2

PX2A_REQ0_N

PX2A_GNT0_N

PXH (A)

Slot 6

PX1B_REQ1_N

PX1B_GNT1_N

Intel® IOP332 Storage I/O

Processor (B)

Slot 7

PX1B_REQ0_N

PX1B_GNT0_N

Intel IOP332 Storage I/O

Processor (B)

LSI Logic* 53C1030

PX1A_REQ0_N

PX1A_GNT0_N

Intel IOP332 Storage I/O

Processor (A)

Intel® Fibre Channel Module

PX1A_REQ1_N

PX1A_GNT1_N

Intel IOP332 Storage I/O

Processor (A)

3.1.4Wake On LAN

Wake On LAN (WOL) is supported on the Intel® Server Board Set SE8500HW4 either from PCI devices through the PME# signal, or PCI Express via the WAKE# signal.

Any PCI Express adapter can generate a wake event by asserting the WAKE# signal. This signal is OR’d to all other PCI Express WAKE# signals and routed to the ICH5 after being qualified with intrusion and a prior graceful shutdown. The assertion of a WAKE# signal will cause the system to return to the ACPI S0 sleep state. Once system power is up and the PCI Express devices are configured, a PME message is sent to the NB identifying the device that woke the system.

For all the PCI devices or the Ethernet controller, PME# is handled similarly to the PCI Express WAKE# signal. All PME# signals are OR’d together and routed to the ICH5 after being qualified with intrusion and a prior graceful shutdown. The PME assertion wakes the system but does not generate an interrupt from the ICH5. Once the system is powered up, the PXH or Intel® IOP332 Storage I/O Processor generate a PME interrupt message to the operating system. The operating system determines which slot is the PME source by polling the PXH and Intel® IOP332 Storage I/O Processor.

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3.1.5PCI Hot Plug* Support

PCI Hot Plug* is the concept of removing a standard PCI adapter card from a system without stopping the software or powering down the system as a whole.

In the Intel® Server Board Set SE8500HW4, PCI Slot 2 supports the PCI Hot-Plug Specification, Revision 1.1 and is configured so that the PXH isolates the slot from the PCI bus when no adapter is present. The four PCI Express slots support the PCI Express Base Specification, Revision 1.0a.

3.1.5.1Hardware Components

The Intel® Server Board Set SE8500HW4 contains buttons and LEDs to assist a user for hot plug operations. Buttons provide isolation circuitry to physically disconnect the hot plug adapter from the PCI buses while LEDs provide slot power and status. The LEDs have enough luminous intensity to pass through system-level light pipes and be visible at the top of a system. An attention button can be used to invoke a hot-plug sequence to remove or add an adapter without the use of an operating system/software interface.

Table 7. PCI Hot Plug LEDs

LED

State

Meaning

Power

Off

Power off: All main rails have been removed from slot. Card can be inserted or removed.

(Green)

On

Power on: Slot is powered on. Card cannot be inserted or removed.

Blinking

Power transition: Slot is in the process of changing state. Card cannot be inserted or

removed.

Attention

Off

Normal: Normal operation.

(Amber)

On

Attention: Power fault or operational problem at this slot.

Blinking

Locate: Slot is being identified at the user’s request.

3.1.5.2Software Components

PCI hot plug operations are supported by the system BIOS, an operating system driver and an optional operating system administrative interface. The Intel® Server Board Set SE8500HW4 BIOS provides initialization of the hot plug hardware components, logging of hot plug events through server management and ACPI table generation. Microsoft* Windows* Server 2003, Enterprise Edition includes support for PCI hot plug through the taskbar “Unplug or Eject Hardware” interface but may require an updated adapter device driver. Refer to other operating systems’ manuals for more information on how to perform hot-plug operations. Reference the PCI adapter release notes for specific information on support and driver requirements.

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3.1.5.3Hot Removal Example

3.1.5.3.1Under Microsoft Windows Server 2003, Enterprise Edition:

1.Open the cover of the system to access the adapters and status LEDs.

2.Double-click “Unplug/Eject” in the taskbar to open the “Unplug or Eject Hardware” menu.

3.Select the device to be removed and click “Stop”.

4.Wait for the power LED to turn off.

5.Dis-engage rocker, retention, and/or safety devices.

6.Remove the adapter.

3.1.5.3.2Under other operating systems:

1.Open the cover of the system to access the adapters and status LEDs.

2.Press the attention button for the slot. (press the attention button within five seconds to abort the hot plug operation)

3.Wait for the power LED to turn off.

4.Dis-engage rocker, retention, and/or safety devices.

5.Remove the adapter.

3.1.5.4Hot Addition Example

3.1.5.4.1Under Microsoft Windows Server 2003, Enterprise Edition:

1.Open the cover of the system to access adapters and view the status LEDs.

2.Install the adapter into the slot.

3.Engage rocker, retention, and/or safety devices.

4.Wait for the software user interface to open. Confirm the device to be enabled.

5.Wait for the power LED to turn on.

Note: If the attention LED is blinking, a power fault has occurred. The user may need to remove the adapter, wait for the LED to turn off, and re-start the hot add operation.

3.1.5.4.2Under other operating systems:

1.Open the cover of the system to access adapters and view the status LEDs.

2.Install the adapter into the slot.

3.Engage rocker, retention, and/or safety devices.

4.Press the attention button for the slot. (press the attention within five seconds to abort the hot plug operation)

5.Wait for the power LED to turn on.

6.Enable the device in your operating system.

Note: If the attention LED is blinking, a power fault has occurred. The user may need to remove the adapter, wait for the LED to turn off, and re-start the hot add operation.

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3.2Ultra320 SCSI Subsystem

A single LSI Logic* 53C1030 controller provides the on-board Ultra320 SCSI interface. The controller resides on the PCI Bus Segment A (PX1A), off the Intel® IOP332 Storage I/O Processor. For optimal performance, the controller is configured as a 64-bit PCI-X 100MHz device.

The LSI Logic 53C1030 supports two Ultra320 SCSI channels, both validated for LVDS operation. In the Intel® Server Platform SR4850HW4 the first channel is routed to the internal hot-swap hard disk drive bay and the second is optionally connected to an external connector. In the Intel® Server Platform SR6850HW4 both channels are routed to the internal hot-swap hard disk drive bay. Intel has not validated Single Ended (SE) operation for this device.

PCI Express and PCI-X adapter cards based on a LSI Logic 53C1030 controller should have the option ROM for the slot turned off in the system BIOS setup. This will allow the embedded LSI Logic 53C1030 controller firmware to manage the add-in adapters. The Intel® Server Board Set SE8500HW4 Mainboard does not have a physical flash device, so the system BIOS loads the required RISC F/W into the embedded LSI Logic 53C1030 controller during POST. A 53C1030-based adapter cannot take control of the embedded SCSI controller since those cards do not have the required RISC F/W to start the embedded SCSI device. Starting with the LSI Logic Fusion-MPT* SCSI BIOS 5.10.02, the embedded LSI Logic 53C1030 SCSI controller can control additional LSI Logic 53C1030-based adapter cards.

To activate the ROMB solution, a physical Intel® RAID Activation Key (RAK) and DDR2 400MHz RAID DIMM must be installed on the Intel® Server Board Set SE8500HW4 Mainboard. The RAK contains a registration code required to unlock the LSI Mega RAID* solution. The DDR2 400MHz RAID DIMM serves as memory for the Intel® IOP332 Storage I/O Processor and a disk cache to store write data for the drives. In addition to these components an Intel® RAID Smart Battery (RSB) may also be installed to refresh the RAID DIMM when system power drops below specifications.

After installing a RAK and DDR2 400MHz RAID DIMM, and optional RSB, the system BIOS setup allows the user to enable the ROMB solution. During option ROM scan, an option to configure the RAID is displayed. The following three chapters provide an overview of the Intel ROMB solution, however, for more information refer to the Intel® RAID Smart Battery Technical Product Specification.

3.3.1Intel® RAID Activation Key (RAK)

The RAK is a round one-wire serial EEPROM device programmed by Intel. This key has a registration code required to enable the LSI Mega RAID* solution.

3.3.2DDR2 RAID DIMM

The ROMB solution only supports 400MHz registered ECC, with a CAS latency of four clock cycles. Please refer to the Intel® Server Board SE8500HW4 Memory Qualification List for supported memory.

3.3.3Intel® RAID Smart Battery (RSB)

The RSB keeps the contents of the DDR2 400MHz RAID DIMM preserved if power drops below specifications. When the Intel® IOP332 Storage I/O Processor senses power has dropped below specifications, it initiates a power fail sequence that safely puts the RAID DIMM into self-refresh state. The power subsystem generates enough of a delay to allow the Intel® IOP332 Storage I/O Processor to complete its power fail sequence, even in the event of total system power loss.

After the power fail sequence is completed, additional logic keeps the RAID DIMM in selfrefresh mode. When power is restored, data from the RAID DIMM is safely written to the disk array.

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3.4Gigabit Ethernet

A single Broadcom* BCM5704C controller provides the on-board Gigabit Ethernet interface. This controller has two ports that can independently operate at 1000/100/10 Mbps and support failover and teaming for greater reliability and performance. The two Media Access Controllers support full-duplex and half-duplex modes at all speeds and have their own PCI configuration space and on-chip memory for higher performance with load balancing and packet buffering. For optimal performance, the controller is configured as a 64-bit PCI-X 133MHz device. The ICH5 contains an Ethernet controller, but this device is not used by the Intel® Server Board Set SE8500HW4.

3.5Serial ATA (SATA)

The ICH5 provides a Serial ATA (SATA) interface with a transfer rate of up to 1.5GB/s. The Intel® Server Board Set SE8500HW4 Mainboard has a standard 7-pin vertical connector for this feature. SATA cables should be 1m (40 inches) or less in length.

3.6Fibre Channel

The Intel® Fibre Channel Module seats into a custom-wired PCI Express x16 slot on the Intel® Server Board Set SE8500HW4 Mainboard, which is attached to the Intel® IOP332 Storage I/O Processor. The module uses a Qlogic* ISP2322 FC-PCI-X controller and has the following features:

Works with the Qlogic SANsurfer* Management Suite and other Qlogic FC cards

For more information, please refer to the Intel® Fibre Channel Module User Guide.

3.7Firmware Hubs

The Intel® Server Board Set SE8500HW4 Mainboard has a combined total of 4MB flash memory that serves as the firmware hub (FWH) for the system BIOS. The system BIOS fits into 2MB of flash, but twice that is required to support the rolling BIOS feature. See Chapter 5 for more information on the rolling BIOS.

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3.8Video

A single ATI* Radeon* 7000 video controller provides the on-board video interface. The ATI Radeon 7000 features the following technologies:

2D/3D video accelerator

Dual DAC for integrated, cost-effective multi-panel support

Resolutions from VGA up to UXGA (1600x1200)

16MB SDRAM video memory

32-bit/33MHz PCI host interface

Using the default operating system video driver options, the VGA signal is mirrored between the rear panel and the front panel connector. This design consideration was made to facilitate user debug of an operating system hard failure. When the system is in a failure state a portable monitor can be attached to the front of the system to determine root cause. Since this is an enterprise server, Intel has not validated the video driver configured with the front panel I/O board VGA connector in a non-mirrored, extended desktop, state.

3.9USB 2.0

The ICH5 provides four USB 2.0 interfaces with one internal connector on the Intel® Server Board Set SE8500HW4 Mainboard, a dual-stack USB connector on the rear panel, and one interface routed to the front panel connector.

3.10 Serial

The SIO provides two RS232 serial communication ports (COM1 and COM2). COM1 is provided through DB9 connector on the rear panel of the Intel® Server Board Set SE8500HW4 Mainboard while COM2 is internal to the chassis and available as an unshielded 9-pin header (2 x 5, with pin 10 removed for keying). COM1 is available as an Emergency Management Port (EMP) for remote server management, and when used in this mode, it is unavailable to the BIOS/operating system. When server management is setup for Serial Over LAN (SOL) remote server management, COM2 is unavailable to the BIOS/operating system.

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4.Intel® Server Board Set SE8500HW4 Memory Board

One to four Intel® Server Board Set SE8500HW4 Memory Boards plug vertically into the Intel® Server Board Set SE8500HW4 Mainboard. The Memory Board has the following features:

LED error indicators for each DIMM and an attention LED for hot plug events

LED indicator for both memory mirroring and RAID configurations

Memory hot plug at the card level, based on the PCI Hot Plug model

On board power converters for 0.9V, 1.5V, and 1.8V

Field Replaceable Unit (FRU) device

Two temperature sensors

Safety mechanism for instant power shut-down to the Memory Board

Figure 4. Memory Board Outline Diagram

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Figure 5. Memory Board Component Diagram

4.1DDR2 DIMM Support

DDR2 memory offers an effective doubling of the clock rate over DDR memory since data transfers happen on both the rising and falling edge of the clock (double pumped). Due to the lower clock frequency, and improved manufacturing technology, a significant power savings can be achieved, especially when the data bus is not active.

The Intel® Server Board Set SE8500HW4 Memory Board supports DDR2 400MHz (also referred to as PC2-3200) registered ECC SDRAM with On Die Termination (ODT). Both single-rank and dual-rank technologies are supported, however unbuffered and non-ECC will not function in the Intel® Server Board Set SE8500HW4. Within a single bank, both DIMMs must be identical. (The DIMMs must be identical in size and in the number of devices on the DIMM.)

Speeds less than DDR2 400MHz may be used, but performance will be reduced. Intel has only validated DDR2 400MHz SDRAM for specific memory parts; refer to the Intel® Server Board Set SE8500HW4 Board Memory Qualification List

4.2Installation Order

When only using two memory DIMMs, the first pair of sockets, DIMM_1A and DIMM_1B, must be populated. When using a mixture of single-rank and dual-rank memory DIMMs on one Memory Board, the dual-rank DIMMs must be installed in the first pair of sockets.

4.3Memory Initialization

The XMB provides hardware memory initialization. The initialization engine performs two passes. On the first pass, it writes the entire segment. On the second pass, it reads and tests the entire segment. Any errors are logged with the failing DIMM being flagged for BIOS.

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4.4Data Correction and Scrubbing

The XMB employs a Single Device Data Correction (x8 SDDC) algorithm for the memory subsystem that will recover from a component failure during read and write transactions. This corrects and logs a correctable memory error, and logs uncorrectable memory errors.

A patrol scrub can be turned on in the system BIOS that scrubs roughly 64GB of memory behind each XMB every day. The patrol scrub confirms the data for one cache line every 16k core cycles and then increments the address one cache line. During patrol scrub, an erroneous read will be logged and re-read. If the re-read is correctable, it is corrected (scrubbed) in memory. A conflicting read or write request pending issue will be held until the scrub is finished.

4.5Memory Board Components

DIMM_1B

DIMM_1A

Remote

Temperature

Temperature

Sensor

Sensor

DIMM_2B

Controller

DIMM_2A

Channel A

Channel B

E8500 eXtended Memory

Bridge

IMI

I2C

FRU

Main Board Connector

Figure 6. Memory Board Block Diagram

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4.5.1Button, Retention Latch and LEDs

The following sections provide an overview of the hardware required to support memory hot plug. See Section 10.1 for more information about memory hot plug support on the Intel® Server Board Set SE8500HW4.

4.5.1.1Attention Button

This is a user accessible push button that initiates the proper shut down of the Memory Board during a memory hot plug event. When pushed, a notification is sent to the memory hot plug controller on the Mainboard. The system blinks the attention LED until the request can be serviced. The BIOS interprets the request as a hot removal if the Memory Board is included in the current system memory configuration or as a hot add if it is not.

If the system rejects the removal request, the power LED remains lit. A removal request may be rejected if the current memory mode does not support hot removal. For example if only three good boards in a memory RAID mode remain, the system will reject a removal request to any of those three boards. If the system accepts the removal request it blinks the power LED, deinitializes the board, then turns off the power LED. After the power LED is turned off, the user may open the retention latch to remove the Memory Board.

4.5.1.2Retention Latch

The retention latch is a mechanical lock and handle used to remove the Memory Board from a chassis and the Mainboard. In the event of an unexpected memory hot plug operation, nonaccessible buttons under the retention latch will turn off power to the Memory Board. This safety feature is included to protect the user and circuits in the event that the attention button was not used properly.

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4.5.1.3LEDs

All LEDs are controlled by the BIOS through the Independent Memory Interface (IMI). Table 8 describes the LEDs on the Memory Board.

Table 8. Memory Board LEDs

Name

Color

Description

Mirror

Green

Memory Board is in a mirror mode

RAID

Green

Memory Board is in a RAID mode

Attention

Amber

When flashing, the Memory Board is in a hot plug event

Power1

Green

Memory Board is powered on, all rails are on

1B

Amber

DIMM_1B has had an error and needs to be replaced

1A

Amber

DIMM_1A has had an error and needs to be replaced

2B

Amber

DIMM_2B has had an error and needs to be replaced

2A

Amber

DIMM_2A has had an error and needs to be replaced

1- The power LED provides indication of Memory Board state. It is cleared when the Memory Board is inactive and set when the Memory Board is included in the current memory configuration. It blinks when a request is being serviced during a hot removal or hot add event.

4.5.2Temperature Sensors and FRU

A dual temperature sensing device provides a sensor at the left and right of the DIMM sockets. Server management sees this as one sensor, measuring the temperature drop across the board which estimates the heat generated by the DIMMs.

An EEPROM device provides 256 bytes of programmable Field-Replaceable Unit (FRU) space. Like all Intel server boards, this FRU is programmed during manufacturing to contain the board version and serial number but may be programmed to meet integrator-specific needs.

4.5.3I2C

The XMB, temperature sensor controller and FRU device are connected to the Mainboard Baseboard Management Controller. The I2C bus addressing for these devices is slot dependant and located on private I2C bus 3.

4.5.4Independent Memory Interface (IMI)

The Independent Memory Interface (IMI) is simultaneous and bi-directional, with a read bandwidth of up to 5.3 GB/s and a write bandwidth of up to 2.7 GB/s. The IMI also provides support for Memory Board hot plug signals and protects all transfers with a combination of packet-based CRC and/or x8 SDDC.

4.5.5Serial Presence Detect (SPD)

The Serial Presence Detect (SPD) bus is a low frequency serial chain that is routed to each DDR2 memory channel. The XMB acts as a master for the SPD bus and uses it to detect and configure the DIMMs.

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4.5.6Power

The Baseboard supplies 12V and 3.3V power to the Memory Board. The Memory Board has on board regulators to generate 1.8V, 1.5V and 0.9V. The XMB requires 1.5V and 1.8V, the DIMMs

require 1.8V and DIMM termination requires 0.9V. The I2C devices use the 3.3Vstby from the Mainboard.

4.6Memory Hot Plug

4.6.1Prerequisite for Memory Hot Plug

Before performing a Memory Board hot remove or add, ensure the system BIOS is configured to support this operation, and the operating system supports this capability. See Chapter 10.1 for more information about memory modes and their support for memory hot plug operations.

4.6.2Memory Board Hot Remove

If the board is already powered on, the following steps are required to ensure proper removal:

1.Press the attention button. The attention LED will begin flashing to indicate that the BIOS is preparing the board for a hot remove. The System BIOS will copy the data off the board and the attention LED will continue to flash as this operation completes.

2.When the attention LED stops flashing and turns off and the power LED has turned off, disengage the retention latch and remove the Memory Board. If the power LED does not turn off, the memory configuration may not support memory hot plug events, see Section 10.1 for more information.

4.6.3Memory Board Hot Add

1.Plug the Memory Board into the Mainboard and engage the retention latch.

2.Press the attention button to alert the BIOS that a Memory Board has been added to the system. The BIOS will prepare the board for operation and, depending on the memory mode, may blink the power LED to indicate the board is not yet available. When the power LED is on the board is in use. If the power LED does not stay solid green, the BIOS has rejected the Memory Board, see Section 10.1 for more information.

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Server Management

5.Server Management

Intel server management consists of many embedded technologies that consist of a combination of board instrumentation, sensors, interconnects, server management controllers, firmware algorithms, and the system BIOS. The Intel Server Management (ISM) 8.x application provides a systems management application for monitoring server hardware and operating system performance and health. The Intel Server Deployment Toolkit provides utilities that help integrate server building blocks for optimal operation. This toolkit includes tools for configuring FRU, SDR, firmware and BIOS; viewing the SEL; and capturing personality (settings) of one server and transferring the personality to another identical server.

The Intel® Server Board Set SE8500HW4 platform management system is based on the IPMI v2.0 Specification and includes the following major elements:

Figure 7 shows a logical block diagram of the server management for the Intel® Server Board Set SE8500HW4 and both the Intel® Server Platform SR4850HW4 and Intel® Server Platform SR6850HW4.

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Front Panel SDI Switch

System Identify Button

Reset Button

Power Button

System Status LED

Drive Activity/Fault LED

Identify LED

Power LED

Network Activity LEDs

FRU EEPROM

Temp Sensor

BASEBOARD

Front Panel Connectors

spkr

DIMM SPD (16)

Aux. IPMB

Connector

FRU EEPROM

PROCESSOR SOCKETS(4)

Hot-swap

Thermal Trip

Backplane

CPU 'Core' Temp

Header

DUAL

CPU OEM NV

CPU Voltage

TCO

NIC

Busses

CPU FRU

ICMB

Transceiver

Management

Header

Chip Set

Baseboard

Temp 1

BBD COM1

PCI PME

Private

Logic 2.5V

COMM MUX

COM 1

FANs (6)

To Power

EMP

INTELLIGENT PLATFORM MANAGEMENT BUS (IPMB)

Connector

Distribution

Board

5V

Power

12V

3.3V

Non-volatile, read-write storage

SYSTEM

SENSOR

FRU INFO

-12V

BASEBOARD

EVENT

DATA

& CONFIG

LOG

RECORDS

DEFAULTS

MANAGEMENT

1.25V

3.3V Standby

CONTROLLER

(BMC)

CODE

- Chassis ID

RAM

LVDS-A Term

System I/F

(updateable)

- Baseboard ID

LVDS-B Term

PORTS

- Power State

SMM

SMS

I/F

I/F

IMM

System LPC Bus

Figure 7. Server Management Block Diagram

Note: The interconnections and blocks shown are to illustrate the functional relationships between the system management elements. They do not map directly to the exact circuit implementation of the architecture.