To link to the entire object, paste this link in email, IM or documentTo embed the entire object, paste this HTML in websiteTo link to this page, paste this link in email, IM or documentTo embed this page, paste this HTML in website

VARIATION-AWARE CIRCUIT AND CHIP LEVEL POWER OPTIMIZATION IN
DIGITAL VLSI SYSTEMS
by
Mohammad Ghasemazar
______________________________________________________________
A Dissertation Presented to the
FACULTY OF THE USC GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
December 2011
Copyright 2011 Mohammad Ghasemazar

In today’s IC design, one of the key challenges is the increase in power consumption of the circuit which in turn shortens the service time of battery-powered electronics, and increases the cooling and packaging costs of server systems. On the other hand, with the increasing levels of variability in the characteristics of nanoscale CMOS devices and VLSI interconnects and continued uncertainty in the operating conditions of VLSI circuits, achieving power efficiency and high performance in electronic systems under process, voltage, and temperature (PVT) variations has become a daunting, yet vital, task. ❧ This dissertation investigates power optimization techniques in CMOS VLSI circuits both at circuit level and chip level, while considering the variations in fabrication process or operating conditions of such circuits and systems. First, at circuit level, we present and solve the problem of power-delay optimal design of linear pipeline utilizing soft-edge flip-flops which allow opportunistic time borrowing within the pipeline. We formulate this problem considering statistical delay models that characterize effect of process variation on gate and interconnect delays. To enable further optimization, the soft-edge flip flops are equipped with dynamic error detection (and correction) circuitry to detect and fix the errors that might arise from possible over-clocking. ❧ Second, we propose chip level solutions to the problem of low power design in Chip Multiprocessors (CMPs). We formulate this problem in the form of minimizing total power consumption of CMP while maintaining an average system-level throughput, or maximizing total CMP throughput subject to constraints on power dissipation or dietemperatures. ❧ We then propose mathematically rigorous and robust algorithms in the form of dynamic power (and thermal) management solutions to each of these problem formulations. Our proposed algorithms are hierarchical global power management approaches that aim to minimize CMP power consumption (or maximize throughput) by applying mainly dynamic voltage and frequency scaling (DVFS) technique, task assignment and consolidation of processing cores. To tackle the inherent variation and uncertainty of manufacturing parameters and operating conditions in these problems, our solutions adopt a closed loop feedback controller. Additionally, in one problem formulation, we focus primarily on the variations and uncertainty of CMP optimization problem parameters and adopt an algorithm based on partially observable Markovian decision process (POMDP) that uses belief states to determine unobservable system parameters, and then stochastically minimize overall CMP power consumption. Overall, simulation results of our solutions demonstrate promising results for the CMP power/thermal optimization problem.

The author retains rights to his/her dissertation, thesis or other graduate work according to U.S. copyright law. Electronic access is being provided by the USC Libraries in agreement with the author, as the original true and official version of the work, but does not grant the reader permission to use the work if the desired use is covered by copyright. It is the author, as rights holder, who must provide use permission if such use is covered by copyright. The original signature page accompanying the original submission of the work to the USC Libraries is retained by the USC Libraries and a copy of it may be obtained by authorized requesters contacting the repository e-mail address given.

VARIATION-AWARE CIRCUIT AND CHIP LEVEL POWER OPTIMIZATION IN
DIGITAL VLSI SYSTEMS
by
Mohammad Ghasemazar
______________________________________________________________
A Dissertation Presented to the
FACULTY OF THE USC GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
December 2011
Copyright 2011 Mohammad Ghasemazar