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axr0284 wrote:
> Hi,
> I was wondering if there are any general rules when coding for a CPLD
> versus an FPGA. Thanks,

CPLDs are sometimes faster for simple blocks.
They often have fewer flops and no block ram.
But it's just another target device for synthesis.
It either fits and makes Fmax, or it doesn't.
I don't change coding style.

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On Feb 5, 1:25 pm, Mike Treseler <> wrote:
> axr0284 wrote:
> > Hi,
> > I was wondering if there are any general rules when coding for a CPLD
> > versus an FPGA. Thanks,
>
> CPLDs are sometimes faster for simple blocks.
> They often have fewer flops and no block ram.
> But it's just another target device for synthesis.
> It either fits and makes Fmax, or it doesn't.
> I don't change coding style.
>
> -- Mike Treseler

Guest

On Feb 5, 10:55 am, axr0284 <> wrote:
> Hi,
> I was wondering if there are any general rules when coding for a CPLD
> versus an FPGA. Thanks,
> Amish

I have found that some vendor-bundled CPLD synthesis tools are
sensitive to entity complexity and size. So, for the CPLD with say 4
physical regions you might break your design apart into smaller
chunks. I have seen cases where the same design coded 2 different
ways is the difference between fits or doesn't fit. There are likely
some performance implications but I didn't look into that. If you
have good synthesis tools then this is probably less of an issue.

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