ACE’ing the verification of a cache coherent system using UVM

It is apparent
that the stimulus generation schemes must be sophisticated and
configurable to meet the complex verification requirements of the ACE
cache coherence capabilities. The UVM base class library provides
significant functionalities in string together a robust and configurable
stimulus generation infrastructure.

Typically, one would start with some atomic sequences and move
toward creating complicated ones as the basic functionality is
verified. Instead of creating a flattened logic in the sequence body,
hierarchical or nested sequences can be created that leverage the basic
sequences which have already been created, as shown in Figure 4.

Figure 4: Nested sequences

This can go up to multiple levels of hierarchy and thus it becomes
possible to converge towards meeting the requirements of the most
complex scenarios.

As the complexity increases across multiple
ACE components, there might be a requirement to coordinate the sequences
across multiple sequencers and drivers. This can be handled through
virtual sequences and sequencers

Figure 5: UVM BCL interaction

Now each ‘sequence’ extending from uvm_sequence has a reference (m_sequencer)
to the sequencer on which it is supposed to execute. So, whenever a
sequence is executed on a sequencer either directly through a sequence.start() or by setting it as the default_sequence of a sequencer in a specific phase, the ‘m_sequencer’
variable is appropriately set. A virtual sequence, which basically
orchestrates multiple sequences, can execute only on the virtual
sequencer. To ensure that the individual sequences within are
appropriately executed on the desired sequencer, they must be mapped to
the real sequencers instantiated within the virtual sequencers (route
‘B’ in Figure 5). This infrastructure can also be leveraged to enable
the sequencer composition to create a layered protocol implementation

The
other important functionality from a stimulus generation perspective is
the grouping of sequences and the creation of hierarchical sequences.
In UVM, similar sequences can be grouped together into a sequence
library.

Figure 6: UVM sequence library package

The ‘uvm_sequence_library’ is used to create a sequence library, as shown in Figure 6. The `uvm_sequence_library_utils(class_name) would build the library infrastructure. Any sequence can be registered to the sequence library through the add_typewide_sequence() method of the library.

Once the library is registered to be the default_sequence
of any sequence, the default functionality causes a random number of
sequences to be picked up and executed. Now, the default mode of
sequence library can be modified by changing the parameters of theuvm_sequence_library_cfg
class. The user can cause specific number of sequences to be picked up,
enable random cyclic sequences, and program a user-defined sequence
execution. Hence, without having to write multiple tests, the user can
create custom-defined sequence execution across multiple sequence
libraries, across different interfaces, through a virtual sequencer,
resulting in a stimulus management setup that helps meet all the
stimulus generation requirements much faster.