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Re: number of clock domains for ADC & DAC interface

Hi Michelle,

Welcome to the Xilinx Forum. I hope things are going well for you at Danmarks Tekniske Universitet.

I need to determine the reference clock input to the clock generator.I understand you have a board with ADC and DAC that you are interfacing to a Digilent Nexys Video board with Artix-7. It is always recommended that the main clock for ADCs and DACs be a low-jitter clock. Without low-jitter, the Effective-Number-Of-Bits (ENOB) for these devices could be degraded. Clocks generated by your Artix-7 FPGA will have jitter that is approximately 100ps Pk-Pk. However, clocks generated by a crystal oscillator can have jitter as low as 1ps Pk-Pk. You will find discussion in <this> long post about how jitter affects ENOB for an ADC.

So, the answer to your question is to use your “Option 1”. That is, you should use a crystal oscillator (XO) to create the main clock for the ADC and for the DAC.

With regards to clock domains, you will have at least two. The data-clock coming from the ADC will produce one clock-domain in the FPGA where you will capture the data coming from the ADC. Along with the data that you send to the DAC, you will also send a data-clock that is generated by the FPGA. This data-clock for the DAC will produce a clock-domain in the FPGA.