In a top down design methodology, typically the design is described in
some high level language. This high level description is later
successively mapped into lower level abstractions of the design. In
our work, we have taken Verilog Hardware Description Language (Verilog
HDL) [6], as our starting point of the design cycle. At a
higher abstraction, the designs described in Verilog are at register
transfer level (RTL). Hardware compilers are used to convert this RTL
description into gate level description while optimizing for the size
of the circuit.

For our project, we chose the hardware compiler vl2mv[7], which
compiles a given verilog description into a gate level interchange
format BLIF-MV[8].

vl2mv extracts a set of finite state machines (FSMs) which
preserve the behavior of the source Verilog programs which is defined
in terms of simulated results. Allocation of hardware gates to
operators in Verilog (i.e., resource binding) is based on the
assumption of unlimited resources. No scheduling is performed and no
optimization is applied on the Verilog source. The extracted FSMs are
not guaranteed to be ``optimal'' in any sense.

The underlying computation is mostly local memory accesses. After
creating the parse tree representing the control and data flow,
semantic checking is performed. Next the hardware gates are generated