General purpose linear voltage regulator. The circuit generates a 3.3V output voltage from an unregulated input voltage ranging from 5V to 30V. It features short circuit protection and 5mA output current capability.

XH018 LP3MOS 3.3V aregc01_3v3 is a 3.3v/1.8V linear voltage regulator for up to 20mA load current and internal bandgap reference. The regulator is implemented as macro cell that fits into the core-limited I/O ring.

XB06: LNA library: RF_LCVCO_CELLS. LCVCO2 is a fully integrated LC-VCO. It should be biased by the RF bias cell. It is based on a cross-coupled bipolar transistor pair. It contains AC-coupled varactors and a special circuit technique for maintaining the D

XB06: LNA library: RF_LCVCO_CELLS. LCVCO3 is a fully integrated LC-VCO. It should be biased by the RF bias cell. It contains a cross-coupled bipolar transistor pair and direct coupled varactors. For this reason, it has a higher tuning range than the other

XB06: LNA library: RF_VCO_CELLS. RINGVCO1 is a fully integrated VCO. It should be biased by the RF bias cell. It consists of a ringoscillator that is tuned by switching the delay chain between 2 and 4 delay stages. The transition between the two borders i

Compatible in its properties, like instruction set, address space and time behavior with the standard CPU MSP430 from TI. Important features: - 16 bit Risc CPU - 7 address modes for source operands- several low power features

LIN (Local Interconnect Network) is a serial communication protocol used in low cost automotive networks. It enables cost efficient bus communication for applications where the bandwidth of CAN is not required. Support of LIN specification 2.2A

Silicon-proven Verilog implementation of a flexible configurable SENT transmitter according to SAE standard J2716 JAN2010 “SENT – Single Edge Nibble Transmission for Automotive Applications”. Up to 16-bit data from two independent sensors.

IPMS_CAN is a CAN bus controller that performs serial communication according to the CAN 2.0B and the CAN FD specification.It is compatible to ISO CAN FD andthe non-ISO (Bosch) CAN FD standard and has extended time stamp and time trigger capabilities.

XC10: A_CELLS; A_CELLS_M1. aporc01 is a digital power-on-reset circuit. During power-on, POR output is kept high as long as the supply voltage is below the POR threshold voltage. After the threshold has been reached, the POR signals turns low. A delay of

XC10: A_CELLS; A_CELLS_M1. aporc02 is a digital power-on-reset circuit. PORB output is kept low as long as the supply voltage is below the POR threshold voltage. PORB signal is generated on both rising and falling edges of the supply voltage. During power

XC10: A_CELLS; A_CELLS_M1. aporc04 is a digital power-on-reset circuit. PORB output is kept low as long as the supply voltage is below the high POR threshold voltage. PORB signal is generated on both rising and falling edges of the supply voltage. During

XC10: A_CELLS; A_CELLS_M1. apogc01 is a general purpose, power good detector. A power good signal (active high) is generated as long as the supply voltage at the VDDA pin lies within the 4.5V - 5.5V limits. When the supply voltage is beyond the either low

XC06: A_CELLS. aporc01 is a dynamic Power-on-Reset circuit. During power-on, POR output is kept high as long as the supply voltage is bellow the POR threshold voltage. When the threshold voltage is reached, the POR signal turns low. A delay of few microse

XC06: A_CELLS. aporc02 is a Power-on-Reset circuit with hysteresis. Reset signals are generated on both the rising and falling edge of the supply voltage. During power-on, POR output is kept high as long as the supply voltage is bellow the high threshold

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