Become a Decoupling Capacitor Network Guru, Part 1

A decoupling capacitor network serves multiple purposes: minimizing the effects of AC signals and noise and acting as a local energy store close to the device being decoupled.

Like the perfect temperature at which beer should be served, asking questions about the design and location of a decoupling capacitor network will return different answers depending upon who is being asked. The funny thing is that, even though the answers may be very different, each respondent will be sure that only he or she is correct.

Before I discuss my preferred beer temperature and how I design and locate my decoupling capacitors, I think it is important we all understand why we have decoupling capacitor networks in the first place. These networks are intended to perform two functions: to provide a low-impedance path to ground for AC signals and noise signals superimposed on the DC supply voltage, and to act as a local energy store close to the device being decoupled, so that high-frequency demands for current (due to logic gates switching, for example) can be supplied without affecting the voltage rail. Remember that a power supply has a much slower response time to transient demands than the operational speed of the devices it powers. At higher frequencies, on-chip decoupling is required, but that's a story for another day.

Both of these requirements will have bearing on the design of the decoupling capacitor network. We must also understand the parasitic elements and construction of a real-world capacitor, which -- along with its capacitive element -- will have resistive and inductive elements, as illustrated below.

Equivalent series resistance (ESR) is defined by the resistance of the leads or pads and losses in the dielectric. This is typically in the range of 0.01 to 0.1Ω for a ceramic capacitor.

Equivalent series inductance (ESL) is defined by internal connections or leads and pads. This is very important in the case of decoupling, because it will dominate over the capacitance above certain frequencies.

From the model above, it is clear that the capacitor C and the ESL will form a series resonance creating a near short (it is not a dead short, due to the ESR). You can calculate the self-resonant frequency (SRF) of a capacitor using the following equation.

Equation for self-resonant frequency (SRF) of a capacitor.

What this means is that, if you have a specific AC frequency you wish to remove, you should ideally select a capacitor with a SRF at the relevant frequency. Another consideration is to ensure a low-impedance profile over a wide frequency band, which will require a range of capacitor values connected in parallel. For example, the network illustrated below employs two different value capacitors. Observe that there are more lower-value capacitors than higher-value ones.

When you are calculating this, do not forget the contribution of PCB interplane capacitance, which will dominate at high frequencies. Interplane capacitance is achieved by careful design of the PCB stack to ensure that the power and ground planes are closely coupled within the stack, thereby creating capacitance.

It's important to remember that the combined decoupling impedance is a function of all the different types and quantities of decoupling capacitors. The example below shows a combined decoupling capacitance (dark blue) formed using 100nF capacitors (pink), 10nF capacitors (yellow), and 11µF capacitors (cyan/turquoise). In this case, the combined decoupling impedance is required to be below 0.1Ω across a wide frequency range.

Decoupling impedance, which must be below 0.1Ω across a wide frequency range (click here for a larger version).

Your target impedance will be defined by the parameters of the voltage supply being decoupled, the maximum transient current, and the allowable ripple on the rail, as described by the following equation.

Equation for target impedance for a decoupling capacitor network.

Having defined the target impedance, you can then use the capacitors available to you and their supplied information -- capacitance, ESL, ESR, tolerance, and drift -- to design a network that meets your impedance profile.

Your selection of decoupling capacitor will generally involve a ceramic device -- commonly a multi-layer component -- although polymer capacitors may be used for some applications. When it comes to selecting the most appropriate device, obviously you will start by looking for a low ESR and an acceptable SRF. You will also need to understand how the capacitor will operate across the desired temperature range and, more importantly, how the capacitance will change with temperature. For example, an X5R capacitor will work between -55 and +85°C with a change in capacitance of ±15% across the temperature range. A Y7V capacitor will operate between -30 and +125°C while exhibiting a variation of +22 to -82% of capacitance value. Selecting the correct type is crucial.

Please remember to follow any recommendations made by the chip manufacturers. Some devices have on-chip decoupling, which reduces the board-level decoupling requirements. The reasons for this will become clear in my next column in this miniseries.

Based on the discussions above, your decoupling network should now acknowledge the parasitic elements and component tolerances of the various capacitors you've selected. Sad to relate, however, this does not guarantee the final performance of the network. This is because we have not yet taken into account any parasitic parameters associated with the component mounting, nor have we considered the effects of component placement. Both will have a significant effect upon the performance. I will address this next time. In the meantime, I prefer my beer ice cold, and I think I need one now.

Hi! I liked your article a lot. I have learned a lot from your articles. This time I wanted to ask you about the equation for the target impedance: since it is (voltage) * (maxVoltageRipple) / (current), I guess there is a problem with the units for impedance, which instead of being "ohms", the would be ( volts * ohm)? right, {V}*{V}/{A} = V*Ω . Please correct me if I am wrong, I am a complete newbie. Thanks.

Faraday <=> friend, Henry <=> horror.SMT any day, minimum layer spacing, lots of planes.4 via routing or 6 if you can afford feed-thru caps or posh X2Y caps. (prefer feed-thru's, but Scot's are canny with the cash), don't accept more than a few hundred pH for each cap on the layout. Cross sectional area of the power/return loop is proportional to inductance. Arrays are also useful, just alternate power and return. Sub 100nm CMOS have rise/fall times of a few 100ps, so the harmonics are well into the GHz.Biot-Savart law, James Clerk Maxwell etc.Dielectrics, most exhibit a capacitance/voltage/temperature drop off and ageing.What do you call a Welshman that makes deionized water for car batteries? Di Electric.X7R and especially X5R are ferroelectric as well, so we have a non-linear TCC and VCC with piezoelectric microphony chucked for bad measure!Despite the last paragraph, the ferroelectric dielectrics have a lower Q, fewer layers and less metal in comparison to low permittivity NP0/COG, therefore higher resistance and lower Q, less PSD oscillation.0402 2 terminal 4 via, or 0603 3 terminal feed thru's with 6 via, X7R 1uF and lot's of them. It usually costs the same price of the cap to get them stuffed onto the PCB. Random geometry proffered. And watch out for the unintended EBG!For SMT and ROHS, forget poly-anything. Unless necessary in analogue or RF.For bulk, Lytics have a very limited life unless de-rated (a few thousand hours). Tants fare better but 1/3 of voltage is a safe de-rate. (Tants do blow the copper and laminate off PCB's if production bungs them the wrong way round!).

Overstayed my time, but hope the thrupence worth is not too boring!I live in a market town in Schottland. Started learning German and met a German tractor driver today - "Kann ich kompostieren Ihren Traktor".

Most capacitor types are available as either SMT or TH. Oftentimes ceramic caps are used int SMT as decoupling due to low cost and low ESR. As others have noted, temperature and voltage operating conditions need to be accounted for.

(Aluminum) electrolytics are commonly available, as are tantalum. The Al electrolytics tend to be relatively large depending on voltage and capacitance. This can lead to mechanical shock and vibration problems, as the only thing holding them on the board is the glue between the pads and the PCB material.

Thank you for the comment, there is limited space for a blog so a number of your points will be addressed in part 2 which looks at how and where we mount the devices and what the driving requirements are.