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Xilinx Datacenter on a Chip

I talked recently about the Intel acquisition of Altera which seems to be all about using FPGA technology to build custom accelerators for the datacenter. Some algorithms, especially in search, vision, video and so on map much better onto a hardware fabric than being implemented in code on a regular microprocessor.

So if the heart of the future datacenter is a high-performance processor coupled with a programmable fabric then Xilinx just taped out what I think of as a datacenter on a chip, although they call it the industry's first All Programmable Multi-Processor SoC (MPSoC). It is on TSMC's 16FF+ process.

Of course this is the initial tapeout. Xilinx is already shipping parts in TSMC's 28nm and 20nm nodes.

Under the hood are seven processors:

A quad-core 64-bit ARM Cortex-A53 processor

A dual-core 32-bit ARM Cortex-R5 real-time processing unit

An ARM Mali-400 GPU

There are also a suite of integrated peripherals, security features and advanced power management. The All Programmable Zynq UltraScale+ MPSoC enables the development of flexible, standards-based platforms by providing 5X system level performance/watt and any-to-any connectivity with the security and safety required for next generation systems.

With processors and programmable fabric, the parts can obviously be used for a wide range of applications. But Xilinx call out three areas where they have focused. Embedded vision systems especially for advanced driver assistance systems (ADAS) and autonomous vehicles. Industrial internet of things to add a lot of local processing power so decisions can be made accurately and fast. And 5G mobile base stations, including multiple antennas, high data rates, and aggressive power limits.

Automotive
The Zynq UltraScale+ MPSoC is tailored for next-generation embedded vision systems, including industrial machine vision, surveillance, and automotive ADAS systems. For ADAS, the Zynq MPSoC tightly couples highly parallelized hardware image processing and analytics acceleration with software based algorithm configuration and control. With the addition of expanded memory with UltraRAM for video buffering, throughput is maximized and latency is reduced; a critical attribute for ADAS. Finally, to enable real-time safety-critical countermeasure decisions and initiate actuator commands, the Zynq MPSoC ARM with dual core Cortex-R5 engines can be utilized in lockstep mode along with cross-monitoring and diagnostic-protected voting in the programmable fabric. The Zynq MPSoC was designed with automotive ISO-26262 functional safety requirements in mind, while still offering a scalable and highly customizable programmable platform that will future-proof customer designs in the quickly changing ADAS space.
Industrial Internet of Things
For the Industrial Internet of Things, the Zynq UltraScale+ MPSoC family is ideally suited to integrate data acquisition, perform real-time diagnostics, and enable local decision-making for intelligent connected control systems. The combination of the MPSoC processing subsystem, the UltraScale programmable logic fabric, and the new UltraRAM on-chip memory technology create the ideal platform to process the vast quantities of data for analytics and manage real-time machine-to-machine (M2M) communication. With a dedicated security processing unit and dual core Cortex-R5 engines that can be configured for lockstep, the Zynq MPSoC also supports SIL3 functional safety and security requirements.
Next Generation Mobile
Zynq UltraScale+ MPSoC devices support the increased radio and baseband processing requirements of next generation 5G systems. This includes the support of new 'massive MIMO' and adaptive beamforming architectures, CloudRAN layer 1 baseband acceleration and associated Fronthaul applications, with flexible support of multiple standards and multiple bands at significantly lower power. The Zynq UltraScale+ MPSoC, with its quad core ARM Cortex-A53 processing subsystem, leverages an integrated fine grain power management system to implement lower power optimal hardware-software design for digital pre-distortion, beamforming control functions, and system management tasks.