There is disclosed a data handling system for use as a terminal or word processor including input-output means, intermediate memory and a magnetic tape cassette principal memory. Incoming data is accumulated alternately in one of the intermediate memories until its capacity is reached, then the data...http://www.google.ca/patents/US3764986?utm_source=gb-gplus-sharePatent US3764986 - Magnetic tape data processing system

There is disclosed a data handling system for use as a terminal or word processor including input-output means, intermediate memory and a magnetic tape cassette principal memory. Incoming data is accumulated alternately in one of the intermediate memories until its capacity is reached, then the data block is transferred to the principal memory at a high speed. An inverse sequence is followed for playback.

[57] ABSTRACT There is disclosed a data handling system for use as a terminal or word processor including input-output means, intermediate memory and a magnetic tape cassette principal memory. Incoming data is accumulated alternately in one of the intermediate memories until its capacity is reached, then the data block is transferred to the principal memory at a high speed. An inverse sequence is followed for playback.

During editing, line length adjustment is provided by converting spaces" near the end of an edited line into "carrier returns". Carrier returns far from the end of an edited line become spaces".

Search capability based on selectable identifying characters, both in forward and reverse directions of tape travel is also available. Searches may be part of the editing operation or simply in preparation for editing or a normal playback.

Our aforementioned parent applications are directed to so-called terminal equipment" used for data transmission, for obtaining access to, and for controlling a computer. This invention relates to such terminals which provide capability for editing, correcting, updating, augumenting, or otherwise changing previously stored data, which is relatively inexpensive, reliable and durable, and sufficiently versatile, to be compatible with commonly used information transmission and processing formats, and data transmission rates.

Editing is best accomplished locally and off-line" since it is a fairly slow real time operation. The capabilities of the equipment here disclosed are particularly adapted to complement our aforementioned terminal systems, but the principles of the invention are readily adapted to comparable terminal systems of other kinds.

With systems of the type in question, a letter or other message is prepared in draft and stored in a suitable memory medium. For editing, the original draft is retrieved, and the necessary corrections are inserted. No new draft is made, but the corrections are entered in the memory for subsequent retrieval to prepare the final draft (or for further revision),

Operational features required for highly flexible editing include automatic playback for rapid advance through the message individual character-by-character playback to reach a particular character for correction, multiple character insertion, and deletion. The latter should include deletion of an individual character, or character group such as words, sentences, lines etc. Additionally since the editing operation is likely to change line lengths, capability should exist for adjusting lines by converting spaces to carrier returns and vice versa to assure lines in the edited text of the proper length.

Also desirable is a search operation by which a message characterized by a selectable multiple character identifier code may be located in the data memory. For editing, this would be a high speed playback of con trolled length.

So far as applicants are aware, all heretofore proposed and available systems providing full scale editing and data formatting functions employ two separate memory systems, one containing the original raw or draft data, and the other receiving the edited data so that the end of the editing operation, the entire revised message is contained in the second memory. Such an arrangement, while workable, possesses several important practical disadvantages.

For example, if a punched paper tape is used as a memory medium, then each revision requires a new, and non-reusable tape. Where a magnetic tape is used as a memory medium, the latter disadvantage is avoided, but offsetting this are the duplication of mechanical equipment for the tape transport, and inherent technical and economic factors making the tape transport itself one of the weakest links in the entire system. Moreover, irrespective of the type of memory medium, use of a second tape is an inconvenience and a complication for the operator both during training, and thereafter during routine use.

In accordance with the present invention, we have discovered that by appropriate utilization of solid state memory equipment, and proper data formatting, the multiple tape memory arrangement of prior systems can be dispensed with, and with the need for duplicate data handling equipment including tape transport, playback and record circuitry, etc. Indeed, by judicious choice of components, and system organization in accordance with this invention, it has been found possible to provide the data editing and formatting capabilities of the most expensive currently available systems at a substantially reduced cost and without the need for the inconvenience and complexity of the multiple memories previously employed.

All of the desirable data processing features mentioned above, including individual character, word, and line deletion, character substitution, and augumentation, character-by-character playback and controlled continuous playback, and even line length adjustment are inexpensively provided. The system also provides for counting the number of typed lines while the original draft is being prepared to permit control of the length of a typed page. Also provided is facility for inserting a gap in the principal memory for storage of data added during an editing operation.

All of the foregoing functions are accomplished in accordance with this invention by the utilization of a data accumulator or editing memory having a capacity for storing a large number of characters, for example, about L000. For the editing operation, data is transferred from the principal memory to the editing memory in data blocks of some convenient size. This is preferably accomplished by use of an intermediate memory unit as described in our above-mentioned parent applications. Data is transferred from the intermediate memory under operator control and is halted whenever a correction or addition is to be made. Line length adjustment proceeds automatically. After editing, the data block is returned to the tape through the intermediate memory and stored in the same place on the tape from which it was removed.

if the editing operation results in deletion of part of a data block, then storage is not effected until there is accumulated in the editing memory enough data to form a complete data block. if the editing operation results in augumenting the data block, then only that part of the accumulated data forming one data block is returned to the tape. The remainder is retained in the accumulator, and becomes part of the next data block to be returned to the tape. the aforementioned process continues with excess data accumulating in the editing memory until the editing process for an entire message is completed, after which any remaining data is stored in the expansion space provided on the tape for this purpose. The editing operation is controlled by circuitry described below, in conjunction with a read only memory (ROM) in which reference characters such as carriage return, spaces, etc. are stored. The various functions of the terminal equipment described in our parent application are retained, and in addition the capability is provided for backward, as well as forward search.

OBJECTS OF THE INVENTION Accordingly, it is among the objects of this invention:

to provide an improved magnetic tape data storage and processing system or use as a data terminal and local message preparation and editing center;

to provide a keyboard controlled magnetic tape data processing machine which is simpler and less expensive than currently available devices, yet reliable and capable of providing a wide range of data editing and augmenting functions;

to provide a magnetic tape data processing system having data editing capabilities in which information is transferred to and from the principal tape memory for editing in large data blocks, and processes in an accumulator or temporary editing memory, and is thereafter returned to the principal memory;

to provide a data editing system in which data is transferred from the tape memory to an editing memory through an intermediate memory unit;

to provide such a system in which data is played into the editing memory from the intermediate memory unit under control of the operator, on a character-bycharacter basis, or continuously, until halted, either manually upon recognition of a preselected character combination;

to provide a data editing system in which data correction in the editing memory is effected by adding one or more characters by means of an external keyboard device, either serially or in parallel;

to provide a data editing system including a read only memory for storing a number of reference characters used during various data deletion operations to permit identification of the reference characters as part of the data to be deleted;

to provide a data editing system permitting line adjustment to accommodate increase or decreases in number of characters in message;

to provide such line adjustment by converting spaces near the desired end of an edited line to carrier returns, and converting carrier returns remote from the desired end of a line into spaces;

to provide such line adjustment in which carrier returns at the end of a paragraph are not converted to spaces even if they appear remote from the desired line end; and

to provide a data editing system capable of search of the principal memory for a desired character combination in either direction on the tape, and in the forward direction as part of the editing operation,

The exact nature of this invention, together with other general and specific objects and advantages thereof, will be apparent from consideration of the following detailed description and the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is an overall block diagram of an editing subsystem according to the invention in a data terminal as disclosed in our parent application Ser. No. 203,245;

FIGS. 2A and 3A show the actual circuitry in block form with signal flow paths for data included;

FIGS. 25 and 3B show in chart form the control signal input to and from the circuit blocks;

FIGS. 4A 4G show the operating characteristics of certain circuit elements employed in the system;

FIG. 5 is a detailed circuit diagram of the system input-output logic;

FIG. 6 shows the programming logic;

FIG. 7 shows the details of the input/output register, the associated control logic and the Read Only Memory;

FIG. 8 illustrates the details of part of the operating mode selection logic;

FIG. 9 illustrates the details of the tape memory operation control logic;

FIGS. 10 and 11, arranged as shown in FIG. 12, illustrate the construction of the intermedite memory and associated control logic, together with part of the data format control logic; and

FIGS. 13 16 show the details of the edit mode selection logic, the edit control logic, the editing memory, and the ROM control logic.

For convenient reference and correlation between the detailed description and the drawings, a reference numerical scheme has been adopted wherein the first digit or digits represent the FIGURE number on which the reference numeral first appears. Thus, an item bearing the reference numeral 604 first appears on and is described in connection with FIG. 6, and items bearing the reference numerals 1208 and 1294 first appear on and are described in connection with FIG. 12.

OVERALL SYSTEM ORGANIZATION (FIG. I)

The data editing subsystem is incorporated in a data terminal as described in our parent applications, but description of the overall system will be omitted, where possible. The reader is referred to our parent applications for such information if it is desired. Briefly, however, with reference to FIG. I, a terminal or data handling system of the type with which this inventin is to be used includes an input/output printer 102, a communication line coupler or modem 104 to interface with a communication channel, such as a telephone or telegraph line, a temporary data storage and processing unit 106, a principal memory unit I08 preferably including a magnetic tape cassette drive, and an associated magnetic tape cassette as the memory medium, and an editing memory 110.

Printer 102 may be a serial machine such as a teletype". Since the terminal is directly compatible with such a machine, a customer already possessing or preferring a teletype may readily convert the same into a tape storage terminal with all the attendant benefits of this invention.

Where letter writing or other typing functions are a principal intended use, a more versatile printer, such as that described and claimed in assignees copending U. S. Patent applications Ser. No. 79,202 filed Oct. 8, I970 entitled Input-Output Typewriter Apparatus; Ser. No. 98,627, filed Dec. 16, 1970, entitled Solenoid Drive Circuit; and Ser. No. 101,502, filed Dec. I970, entitled Improved Solenoid Drive Circuit is preferred. The latter is a parallel machine, and the equipment described is directly compatible with these, as Well as with the serial machines.

Data storage and processing unit 106 is comprised of an input-output (I/O) uit 112 including an input/output buffer and required control logic, connected to printer 102 by cable 114, and to coupler I04 by cable 116. Data storage and processing unit 106 also includes a pair of intermediate memory units 118A and B, connected respectively to input/out unit 112 by coupling unit 120 and to tape memory unit 108 by coupling unit 122. Each intermediate memory unit is preferably constructed of one or more random access memory units (RAM s) providing a data capacity of at least 1,280 bits per unit. While two RAMs are preferred, a single one may be provided, as in our parent application Ser. No. 123,187.

Editing memory 110 is also preferably comprised of RAM units, and advantageously should provide substantially greater storage capacity than expected for the majority of anticipated editing operations. A capacity of about 1,000 characters is preferred, but more may be provided where desired, if the resulting cost increase is acceptable. The editing memory is associated with one of the intermediate memories such as 118A if two are used, but data transfer is provided through coupling unit 120, and [/0 unit 112 as indicated by signal path I24, and as described in detail below.

The principal memory includes the actual tape transport (not shown) and record and playback circuits. Preferably separate tape tracks are provided, one for data and one for timing control pulses. Separate record circuits 126 and 130, and playback circuits 127 nd 132, couple the data and timing control pulses respectively to and from the tape.

A main control logic unit 134 is coupled to the system components mentioned above by signalling path 136 while a set of manual control inputs collectively denoted 140 provide external comman input capabil ity. External controls for the various system operations are mounted on an auxiliary keyboard or control panel (not illustrated) on printer 102 or otherwise within convenient reach of the operator The tape unit may be part of a console containing the system electronics.

DETAILED FUNCTIONAL DESCRIPTION FIGS. 2A and 3A show the actual circuity in block form with signal flow paths for data included. FIGS. 28 and 3B show in chart form the control signal input to and from the circuit blocks.

Referring to FIGS. 2A and 3A, there are shown an input/output unit 202, a three character (24bits) shift register 204, and a shift register control unit 206, a character identification unit 218, an intermediate memory control unit 222, an operating mode selection unit 302, a tape control unit 304, a master sequence control unit or programmer 306, a pair of master oscillators 308 and 310, an associated frequency selection and division unit 312, and an editing control unit 301. Also illustrated in FIG. 2A are intermediate memory units 118A and 1188, and read only memory unit (ROM) 138. FIG. 3A also illustrates the editing memory 110.

Broadly stated, input/output logic unit 202 receives incoming serial data over a lead 208, and provides the same over a lead 210 to the serial input of shift register 204. Parallel input data is received from a local source over leads 212a through 212]", and after suitable input processing, is provided over leads 214 to the parallel inputs of the shift register. Parallel inputs to the shift register are also provided by ROM 138, as explained below for carrier return/space conversion and EOM" code insertion.

Parallel outputs are provided by the shift register over 24 leads 216a-216x. These are provided to the character identification unit 218 described below for use during search and edit operations. Also, the first eight bits on leads 216a-h, are provided to input/output unit 202 for utilization during local playback operation. The eighth bit alone, representing a serial output of the shift register in provided to the input/output unit on the lead 216/: from which it is transferred serially to an intermediate memory control unit 222 over lead 224 for temporary storage in one of intermediate memory units or to appropriate serial utilization equipment over lead 226 during playback. Lead 226 also provides the data input to editing memory for the edit operation.

For data output or playback" operation, data is coupled serially from intermediate memory units 118A or B to input/output unit 202 over a lead 228 and then the shift register input over lead 210. The shift register data output is provided in parallel over leads 216 as previously noted, and then to printer 102, over a set of parallel leads 230.

As noted above, each of intermediate memory units 118A and B provides temporary storage for 1280 data bits before transfer to the tape memory in the record modes, or to other portions of the system in the playback, search", or edit" modes. For all operations except editing, data is stored alternately in each unit; while one unit receives data, the other emits data previously stored. For editing, only memory unit 118A is employed. Memory unit operation, including selection of the memory unit to receive data, is controlled by memory control unit 222.

Referring to FIGS. 1 and 2A, data transferred to the tape memory is provided to data record circuit 126, while data from the tape is provided by data playback circuit 128 over lead 242. correspondingly, timing control signals are provided to record circuit 130 over lead 244, and control signals from the tape are provided by playback circuit 132 over lead 246.

Mode selection unit 302 provides selective actuating signals for the system as required to establish and maintain operation in the record, playback, and search modes. Tape control unit 304 includes the forward and reverse tape drive mechanism and other portions of the system required to transfer information to and from the data and timing tracks on the tape. Sequence control unit 306, master clocks 308 and 310, and frequency selection and division unit 312 provide the sequence of control signals to effect transfer of information between the memory units, and into and out of the system, and to initiate the required data processing operations, as hereinafter described in detail.

Edit control unit 301, ROM 138 and editing memory 110 control the editing functions and the length of a typed page as described in detail hereinafter. For this purpose, ROM 138 stores the reference characters (space, period, etc.) used in the edit operation, and the end of message (EOM) character. These are used for character identification during the skip functions, and for carrier return/space interchange during line length adjustment. ROM 138 also provides the EOM code word for tape storage when needed.

Control signals for the above described operations are coupled between the various circuit units in the manner indicated in FIGS. 28 and 38. The exact nature of the signals involved will be more meaningful after consideration of the detailed construction of the system subunits, and description is deferred for this reason. Logic Elements Operation is described in terms of various conventional logic elements as illustrated in FIGS. 4(a) through (g).

FIG. 4(a) shows a two-input NAND gate. The output is low if and only if both inputs are high. Conversely, the output is high if either input is low. As is well known, utilization of both the conjunctive (low) and the disjunctive (high) aspects of the NAND function allows implementation of any combinational logic function. This approach is followed here.

To distinguish the two functions, the logic device of FIG. 4(a) is used to represent the conjunctive and is referred to as a NAND gate. FIG. 4(b) shows a conventional NAND gate providing the disjunctive function, for which the output is high if either or both inputs are low. This is actually an OR logic function with inverted inputs and will be so referred to. For convenience, the designation OR" will be used. FIGS. 4(c) and 4(d) respectively show conventional inverter, and EXCLU- SIVE OR circuits, while FIGS. 4(e) and 4U) show two types of bi-stable multi-vibrators or flip-flops. FIG. 4(e) shows a set-reset flip-flop comprised of a pair of cross coupled OR* gates having a set input designated S, a reset input designated R and a pair of complementary outputs designated ONE and ZERO. A single block representation of the same unit is also shown, along with a truth table containing the inputs and outputs for the meaningful operating states.

FIG. 4(f) shows a .l-K flip-flop having a pair of signal inputs designated .l and K, clock input designated C, reset input designated R, and two complementary outputs Q and O. A truth table indicating the relationship between the previous output states designated Qn-l, the output state On after time tn (the time the clock input returns low) and the J and K inputs is also shown in FIG. 4(1).

FIG. 4(g) shows a mono-stable or single shot multivibrator. A high level at the set or S input produces a high signal at the output, and a low signal at the Q output for a delay period d, determined by the choice of the circuit parameters. At the end of the delay period, the circuit returns to its rest state with a low signal at the 0 output and a high signal at the 6 output. If the circuit is retriggered by input transition during the delay period, it remains set until input transitions fail to occur for a time exceeding the delay time. Then, the outputs return to their respective rest conditions.

Additional logic units, such as conventional counters, decoders, shift register units, and the read only and random access memories will be described and/or identified as appropriate throughout the following description.

Input/Output Unit. (FIG.

Considering now the details of the invention, inputs from a parallel data source are provided in an eight-bit format, including six character code bits, a parity bit and an eighth bit for compatibility with other code formats having seven information bits, plus a parity bit. These are provided over leads 502(a) through 502(k) to eight NAND gates 504(a)-504(h), controlled by an ENTER DATA signal from the data source.

A second set of eight parallel signals is coupled over leads 732(a)-(h) to eight NAND gates, 508(a)-508(h) from ROM 138. Control for NAND gates S08 is provided by an OR" gate 510, which, in turn, receives as inputs, the EOM STROBE and ROM ENTER signals from mode selection unit 302, and edit control unit 301, respectively. Data is stored in the read only memory in a negative true logic format and is converted to a positive logic format by inverters S16(a)-(h).

NAND gates 504(a)(h) and 508(c)(h) are coupled to eight OR* gates 5l8(a)518(h), the outputs of which are coupled over leads 2l4(a)2l4(h) as the parallel inputs for bit positions 1 through 8 of shift register 204 [See FIG. 2.]

Serial inputs are provided remotely through a suitable coupler, or locally by a serial input unit such as a teletypewriter. The serial input data is coupled through a pair of fixed contacts of ON LINE-LOCAL selection switch 520 and a suitable input signal shaping circuit 522 to a NAND gate 524, controlled by a RECORD signal over lead 526, from mode selection unit 302.

The output of signal shaper 522 also provides the SE- RIAL START signal on lead 528, which actuates sequence control unit 306 to transfer the incoming serial information through shift register 204 and into one of memory units 118A or B for storage. NAND gate 524 is coupled to an OR* gate 530, the output of which is connected over lead 210 as the serial input to shift register 204. [See FIG. 2.] The other input to OR* gate 530 is provided by the output of one of the memory units over lead 228.

Input/output logic unit 202 also provides for selective gating of information from the shift register to one of memory units 118A or B when the system is operating in the RECORD mode. This is accomplished by a NAND gate 532 which receives as inputs, the TAPE STORE signal from mode selection unit 302 and the output of the eighth bit position of shift register 202 over lead 216/1. Lead 216i: is also OR-tied to a lead 534 which provides the I76 CLAMP signal from edit control unit 301. This signal is high (and thus without effect) except during a special memory formatting sequence which simplifies certain operations following entry of an EOM character during a record sequence. [This is described more fully in connection with FIGS. 10 and 11 below.] The low level on lead 534 inhibits NAND gate 532 and maintains its output on lead 224 high irrespective of the data output of the [/O register on lead 2l6h. The NAND gate output on lead 224 (see FIG. 2) provides the signal input to memory unit 118A or B.

Data outputs are provided either to a parallel printer, or serially to a teletype printer or to a suitable data coupler. For a parallel printout, the shift register data at the 1st eight bit positions, processed as described in our parent applications, is provided to the printer data input terminals Thereafter, the shift register is actuated, and a new code word is shifted serially from one of the intermediate memory units through OR gate 530, and the parallel printout is repeated. Serial output data is provided through an output circuit 546, described below. A printout sequence is initiated by a START PRINTOUT CYCLE signal, generated by a NAND gate 536. This receives as its inputs, the PLAY signal from mode selection unit 302, and an output, denoted No. 6, from sequence control unit 306, indicating previous serial shift cycle to be completed. An addition input, denoted UTILIZATION DEVICE READY, indicating that the data receiving unit is ready to accept further data, is provided by the output printer or by the data coupler.

The W5 signal actuates the internal operations for shifting data from the intermedi-