axi_dmac in loopback (dac_dma output to adc_dma input)

I have a picozed SDR board with ADI Linux running on it and we are able to stream through AD9361, using libiio ad9361_iiostream.c and osc.c application

Is it possible to test putting axi_dmac in simple loopback. In the FPGA we have dac_dma with FIFO output interface and adc_dma with FIFO input interface. I connected the dac_dma/fifo_rd_dout to adc_dma/fifo_wr_dout and dac_dma/fifo_rd_valid to adc_dma/fifo_wr_en. There are 2 more signals which were used. dac_dma/fifo_rd_en (input ) and adc_dma/fifo_wr_sync. I tied wr_sync signal to 1'b1 as we we have 2 channels( I and q each) and 64bit data bus.

I tied fifo_rd_en to 1'b1. Is above setup okay? Should I put both of them at same clock ?Lars

Thanks a lot. The DMA loopback is now working and on running libiio application when I send data, I receive the same back. I had put the DMA_dac and the DMA_adc fifo interfaces on the same clock.

One strange thing which I noticed with above is that, if I set the TX_buffer to size 2408 and RX buffer to 2408 bytes (in ad9361_iiostream.c) , I am receiving only 94,95,94,95,94,95.... I am sending oscillating data -- 1,2,3...99,0,1,2,3....99.

However if I increase the buffer size to 10000 then I get the same oscillating data 1,2,3,4,...99. Can you please help why is this so. Is there a minimum buffer size which has to be set ?