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Linux Now Has its First Open Source RISC-V Processor

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With its new, first-of-its-kind Linux-compatible multi-core CPU, SiFive is moving to pushing the open source RISC-V architecture into an expanded world of use cases, including machine learning and IoT.

SiFive has declared that 2018 will be the year of RISC V Linux processors.

When it released its first open-source system on a chip, the Freeform Everywhere 310, last year, Silicon Valley startup SiFive was aiming to push the RISC-V (“risk five”) architecture to transform the hardware industry in the way that Linux transformed the software industry. Now the company has delivered further on that promise with the release of the U54-MC Coreplex , the first RISC-V-based chip that supports Linux, Unix, and FreeBSD.

A block diagram of SiFive's U54-MC Coreplex. (Image sourse: SiFive)

“It's been easy for critics to dismiss RISC-V because it's only been in embedded systems thus far,” Jack Kang , VP of Product and Business Development at SiFive, told Design News . “But now we've taken RISC-V commercially beyond embedded into Linux processing applications.” This latest development has RISC-V enthusiasts particularly excited because now it opens up a whole new world of use cases for the architecture and paves the way for RISC-V processors to compete with ARM cores and similar offerings in the enterprise and consumer space, overcoming what Kang said is was a big criticism as far as the quality of the RISC-V architecture. Now applications such as AI and machine learning and IoT devices can be developed using open-source chip hardware.

In its standard configuration, before any third-party modifications or overclocking, the 64-bit, multi-core U45-MC Coreplex has four U54 CPUs and a single E51 CPU, each running at 1.5 GHz. SiFive said costumers can order the U45-MC in a variety of configurations besides the default. The U54 cores supports the RV64GC ISA, which RISC-V developers expect to become the standard ISA for Linux-based RISC-V devices.

“The U54 Coreplexes are great for companies looking to build SoC's around RISC-V,” Andrew Waterman co-founder and chief engineer at SiFive, as well as the one of the co-creators of RISC-V, told Design News. “ The forthcoming silicon is going to enable much better software development for RISC-V.”

Waterman said that, while SiFive had developed low-level software such as compilers for RISC-V the company really hopes that the open-source community will be taking a much broader roll going forward and really pushing the technology forward. No matter how big of a role we would want to have we can't make a dent,” Waterman said. “But what we can do is make sure the army of engineers out there are empowered.”

The next immediate question then becomes: What will be the killer app for RISC-V, product or service that finally breaks RISC-V out into the wider landscape? Rick O’Connor, Executive Director of the RISC-V Foundation, told Design News that it won't be that straightforward however. “People always want to know what's the killer app for RISC-V,” he said. “It's a romantic idea, but [RISC-V] is a very real architecture designed from a modular perspective. But it's not a simply an alternative ISA. There is no killer app sweet spot because you can tailor it.”

From his position in the RISC-V Foundation, O'Connor has a broad insight into the RISC-V ecosystem. The Foundation

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