HARD DRIVE ERASER - Systems, apparatuses and methods for erasing hard drives. A system, which can be configured as a stand-alone and portable apparatus, includes a control device configured to support an erase module. The erase module is configured to erase a hard drive such that data erased from the hard drive is forensically unrecoverable. The system further includes a user interface and at least one drive bay configured to provide communication between a hard drive and the control device.

2012-11-29

20120303921

DATA PROCESSING CIRCUIT WITH MULTIPLEXED MEMORY - A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can be autonomous. The several processing circuits each have an output for outputting memory access requests, which remain at the output for a validity duration interval defined by the clock signal of the particular processor. A multiplexing circuit multiplexes the access requests to a memory. The memory needs a minimum memory repetition period before it can accept an access request following acceptance of a preceding access request. The clock periods of the processing circuits are longer than the minimum memory repetition period. A timing circuit selects acceptance time points at which each particular access request from a first data processing circuit is accepted.

2012-11-29

20120303922

IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH ENHANCED RESOURCE POOL ALLOCATION - A method and controller for implementing storage adapter performance optimization with enhanced resource pool allocation, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines; a processor, and a plurality of resource pools. A plurality of work queues is associated with the resource pools. The processor initializes a list of types, and the associated amount of pages for each allocate type. The hardware engines maintain a count of allocate types, specifying a type on each allocation and deallocation, and performing allocation from the resource pools for deadlock avoidance.

2012-11-29

20120303923

CAPACITY AND LOAD ANALYSIS USING STORAGE ATTRIBUTES - A method includes determining a capacity model that configures computing resource capacity for a capacity container. The computing resource capacity includes a first storage attribute for an amount of storage in a storage component. A load model is determined that configures load for the capacity container. The load includes a second storage attribute for a storage requirement for a virtual machine. A profile of a virtual machine unit is determined for estimating available capacity in a capacity container. The profile is determined using virtual machine attributes for a set of virtual machines, wherein the virtual machine unit includes a storage requirement based on storage requirements for the set of virtual machines. The profile of the virtual machine unit is fit into available capacity. A number of virtual machine units is determined based on the fitting, the number of virtual machine units being a measure of available capacity.

2012-11-29

20120303924

Stochastic Processing - A system, method, and device for stochastically processing data. There is an architect module operating on a processor configured to manage and control stochastic processing of data, a non-deterministic data pool module configured to provide a stream of non-deterministic values that are not derived from a function, a plurality of functionally equivalent data processing modules each configured to stochastically process data as called upon by the architect module, a data feed configured to feed a data set desired to be stochastically processed, and a structure memory module including a memory storage device and configured to provide sufficient information for the architect module to duplicate a predefined processing architecture and to record a utilized processing architecture.

2012-11-29

20120303925

METHOD AND DEVICE FOR CONFIGURING MEMORY CAPACITY - The present invention discloses a method and a device for configuring memory capacity, which relates to the field of computer technologies, so as to solve the problem of complex operations of a method for configuring memory capacity in the prior art. A technical solution provided in an embodiment of the present invention includes: performing a first read/write operation on data in a first memory space; if a system status does not change during the first read/write operation, performing a second read/write operation on data in a second memory space obtained by updating the first memory space; if the system status changes during the first/second read/write operation, obtaining a memory address when the system status changes; and configuring the memory capacity according to the memory address. Embodiments of the present invention may be applied in an embedded system or a computer.

2012-11-29

20120303926

STORAGE SUBSYSTEM - There is provided a storage subsystem having a virtual volume and a page volume which has a page physical area allocated to the virtual volume. The storage subsystem divides an address space of the virtual volume into a plurality of pages, classifies each of the pages into one of a plurality of states including at least a first state and a second state, and further divide a page which is classified into the second state into a plurality of segments to managed the page classified into the second state. The first state is a state in which a page physical area is allocated to the page from the page volume, and the write data is stored in the page physical area. The second state is a state in which the predetermined pattern data and the segment are managed, in the memory, by correlating with each other.

2012-11-29

20120303927

MEMORY ALLOCATION USING POWER-OF-TWO BLOCK SIZES - Methods and systems for managing memory allocation requests are disclosed. Generally, the methods and systems relate to splitting and combining twin buffers for allocating memory of appropriate sizes in response to memory requests. One method disclosed is a method of allocating storage space in a memory of a computing system. The method includes receiving a memory allocation request, the memory allocation request defining a requested memory size, and the memory logically segmented into a plurality of blocks. The method also includes determining whether a block having a best-fit size is available from a buffer pool, the buffer pool selected from among the one or more buffer pools and defining a set of available blocks of a common size. The method includes, upon determining that no block having the best-fit size is available in the buffer pool, locating an available block from a second buffer pool from among the one or more buffer pools, the available block having a size twice the best-fit size. The method further includes splitting the available block into a pair of blocks of the best-fit size, and allocating a first of the pair of best-fit size blocks in response to the memory allocation request.

2012-11-29

20120303928

IMPLEMENTING ENHANCED DETERMINISTIC MEMORY ALLOCATION FOR INDIRECTION TABLES FOR PERSISTENT MEDIA - A method and a storage system are provided for implementing deterministic memory allocation for indirection tables for persistent media or disk drives, such as, shingled perpendicular magnetic recording (SMR) indirection tables. A plurality of fixed-size memory pools are used to store indirection data. The distribution of pool allocate sizes is fixed. A pool allocate size is selected based upon an indirection system request size.

Indirection memory architecture with reduced memory requirements for shingled magnetic recording devices - An indirection system in a shingled storage device is described that uses an efficient algorithm to map LBAs to DBAs based on a predetermined rule or assumption and then handles as exceptions LBAs that are not mapped according to the rule. The assumed rule is that a fixed-length set of sequential host LBAs are located at the start of an I-track. Embodiments of the invention use two tables to provide the mapping of LBAs to DBAs. The mapping assumed by the rule is embodied in the LBA Block Address Table (LBAT) which gives the corresponding I-track address for each LBA Block. The LBA exceptions are recorded using an Exception Pointer Table (EPT), which gives the pointer to the corresponding variable length Exception List for each LBA Block. The indexing into the LBAT and the EPT is made efficient by deriving the index from the LBA by a simple arithmetic operation.

2012-11-29

20120303931

MEMORY BLOCK SELECTION - The present disclosure includes methods and devices for memory block selection. In one or more embodiments, a memory controller includes control circuitry coupled to one or more memory devices having multiple Groups of planes associated therewith, each Group including at least two planes of physical blocks organized into Super Blocks, with each Super Block including a physical block from each of the at least two planes. The control circuitry is configured to receive a first unassigned logical block address (LBA) associated with a write operation and determine a particular free Super Block within a selected one of the multiple Groups to receive data associated with the write operation.

2012-11-29

20120303932

RUNTIME RECONFIGURABLE DATAFLOW PROCESSOR - A processor includes a plurality of processing tiles, wherein each tile is configured at runtime to perform a configurable operation. A first subset of tiles are configured to perform in a pipeline a first plurality of configurable operations in parallel. A second subset of tiles are configured to perform a second plurality of configurable operations in parallel with the first plurality of configurable operations. The process also includes a multi-port memory access module operably connected to the plurality of tiles via a data bus configured to control access to a memory and to provide data to two or more processing tiles simultaneously. The processor also includes a controller operably connected to the plurality of tiles and the multi-port memory access module via a runtime bus. The processor configures the tiles and the multi-port memory access module to execute a computation.

2012-11-29

20120303933

TILE-BASED PROCESSOR ARCHITECTURE MODEL FOR HIGH-EFFICIENCY EMBEDDED HOMOGENEOUS MULTICORE PLATFORMS - The present invention relates to a processor which comprises processing elements that execute instructions in parallel and are connected together with point-to-point communication links called data communication links (DCL). The instructions use DCLs to communicate data between them. In order to realize those communications, they specify the DCLs from which they take their operands, and the DCLs to which they write their results. The DCLs allow the instructions to synchronize their executions and to explicitly manage the data they manipulate. Communications are explicit and are used to realize the storage of temporary variables, which is decoupled from the storage of long-living variables.

2012-11-29

20120303934

METHOD AND APPARATUS FOR GENERATING AN ENHANCED PROCESSOR RESYNC INDICATOR SIGNAL USING HASH FUNCTIONS AND A LOAD TRACKING UNIT - A method and apparatus are described for generating a signal to resync a processor. In one embodiment, a particular load operation is picked from a load queue in the processor, and the particular load operation is completed out of order with respect to other load operations in the load queue. A load ordering block (LOB) in the processor receives a physical address of the completed load operation, and receives a probe data address that indicates an address of a requested data line. The LOB generates a signal to resync the processor when the physical address of the completed load operation matches the probe data address, (i.e., when bits, that have been set in a bit vector (e.g., Bloom filter) of the LOB by hashing the physical address of the completed load operation, match bits generated by hashing the probe data address).

2012-11-29

20120303935

MICROPROCESSOR SYSTEMS AND METHODS FOR HANDLING INSTRUCTIONS WITH MULTIPLE DEPENDENCIES - A processor includes an instruction unit which provides instructions for execution by the processor, a decode/issue unit which decodes instructions received from the instruction unit and issues the instructions, and a plurality of execution queues coupled to the decode/issue unit. Each issued instruction from the decode/issue unit is stored into an entry of at least one queue of the plurality of execution queues, wherein each entry of the plurality of execution queues is configured to store an issued instruction and a duplicate indicator corresponding to the issued instruction which indicates whether or not a duplicate instruction of the issued instruction is also stored in an entry of another queue of the plurality of execution queues.

2012-11-29

20120303936

DATA PROCESSING SYSTEM WITH LATENCY TOLERANCE EXECUTION - In a processor having an instruction unit, a decode/issue unit, and execution queues configured to provide instructions to correspondingly different types execution units, a method comprises maintaining a duplicate free list for the execution queues. The duplicate free list includes a plurality of duplicate dependent instruction indicators that indicate when a duplicate instruction for a dependent instruction is stored in at least one of the execution queues. One of the duplicate dependent instruction indicators is assigned to an execution queue for a dependent instruction. The dependent instruction is executed only when the one of the duplicate dependent instruction indicators is reset.

2012-11-29

20120303937

COMPUTER SYSTEM AND CONTROL METHOD THEREOF - A computer system used to execute an application includes a motion sensing unit, a processor and an instruction transfer unit. The motion sensing unit senses a gesture of a human body and generates an input instruction based on the gesture. The processor executes the application (or a game). The instruction transfer unit is connected with the motion sensing unit and the processor and serves as a communication interface between the motion sensing unit and the application. The instruction transfer unit transfers the input instruction to a control command, and the processor controls and executes the application in accordance with the control command.

2012-11-29

20120303938

PERFORMANCE IN PREDICTING BRANCHES - A method, data processing system, and computer program product for processing instructions. The instructions are processed by a processor unit while using a first table in a plurality of tables to predict a set of instructions needed by the processor unit after processing of a conditional instruction. An identification is formed that a rate of success in correctly predicting the set of instructions when using the first table is less than a threshold number. A sequence of the instructions being processed by the processor unit is searched for an instruction that matches a marker in a set of markers for identifying when to use the plurality of tables. An identification that the instruction that matches the marker is formed. A second table from the plurality of tables referenced by the marker is identified. The second table is used in place of the first table.

2012-11-29

20120303939

SYSTEM INTEGRATION SUPPORTING COMPLETELY WIRELESS PERIPHERAL APPLICATIONS - In accordance with various aspects of the disclosure, a method and apparatus is disclosed that includes features of a host computing device, and a wireless power transmission module and a wireless data transmission module both integrated on a circuit board of the host computing device. The host computing device is configured to transmit power and multi-media data to a peripheral device, upon receipt thereof from the wireless power transmission module and the wireless data transmission module, respectively. The peripheral device is configured to receive wirelessly power and multi-media data from a host computing device, and provide the received power and multi-media data to a wireless power reception module and a wireless data reception module, respectively, for processing, both modules being integrated on a circuit board of the peripheral device.

2012-11-29

20120303940

SYSTEM, METHOD AND PROGRAM PRODUCT TO MANAGE FIRMWARE ON A SYSTEM BOARD - An embodiment includes a computer comprising a system board and a removable programmable storage device. If the system board is replaced, the removable programmable storage device may be transferred to the replacement system board for the automatic transfer of information to the replacement system board and configuration of the replacement system board. In one embodiment, the computer receives a start up command. The computer determines whether a firmware image on the system board matches a firmware image on the removable programmable storage device. Based on determining that the firmware images do not match (when the system board is replaced with a new system board, for example), the computer replaces the firmware image on the system board with the firmware image on the removable programmable storage device. After the check and replacement, the computer proceeds with boot sequences.

2012-11-29

20120303941

METHOD AND APPARATUS FOR SECURING CPUS BOOTED USING ATTACHED FLASH MEMORY DEVICES - The present disclosure describes techniques evaluating compute and/or thermal loads (among other things) to aid in managing a collection of one or more containerized or modular data centers. For example, forecasts (or real-time measurements) of environmental factors (as well as projected computing demands) may be used to tailor the compute loads, cooling strategies or other metric of data center operations for a network of containerized or modular data centers. Doing so allows an operator of such a data center network to manage specific operational goals in real time.

2012-11-29

20120303942

CACHING OF BOOT DATA IN A STORAGE DEVICE - Example embodiments relate to caching data in a storage device. In example embodiments, a storage device is configured to receive a command to access data on the storage device. In response, the storage device may determine whether a computing device to which the storage device is coupled is currently booting. When the computing device is currently booting, the storage device may cache the data in a first portion of a cache used to cache boot data.

2012-11-29

20120303943

INFORMATION PROCESSING APPARATUS AND AUTHENTICATION CONTROL METHOD - According to one embodiment, a control module determines whether a second authentication key is present in a authentication key storage device when an information processing apparatus is powered on. The control module displays an identification code input screen for inputting an identification code if the second authentication key is not present, causes a storage device to execute an identification code authentication process of determining whether the identification code which is input to the identification code input screen agrees with the first identification code, and generates a third authentication key and stores the third authentication key in the authentication key storage device if the identification code authentication process is successfully carried out.

2012-11-29

20120303944

DATA RECOVERING SYSTEM AND METHOD - A basic input output system (BIOS) chip and method recovers specific data when an update of the BIOS chip begins. The BIOS chip obtains a space from a memory of a motherboard and names the space. The BIOS chip saves specific data from a non-volatile random access memory (NVRAM) of the BIOS chip into the space when an update of the BIOS chip begins. The BIOS chip reads the specific data from the space and saves the specific data into the NVRAM of the BIOS chip when the update of the BIOS chip is completed.

2012-11-29

20120303945

COMPUTER SYSTEM WITH MULTIPLE OPERATION MODES AND METHOD OF SWITCHING MODES THEREOF - In a computer system with multiple operation modes and a method of switching modes, the computer system switches the operation modes with multiple hard disk drives by a setting signal. The method of switching modes includes the following steps. A chip unit detects the number of the hard disk drives with no storage of the boot program and the chip unit decides the operation mode of the Redundant Array of Independent Disks. The chip unit produces a corresponding control signal and transmits the control signal to a switch unit. The switch unit produces a setting signal according to the control signal and delivers to the hard disk device to switch the operation modes of the hard disk.

2012-11-29

20120303946

METHOD AND APPARATUS FOR EMBEDDED SYSTEMS REPROGRAMMING - A reprogramming device is used for reprogramming embedded systems. The reprogramming device comprises a microprocessor, a memory programmed with software to accomplish the reprogramming of distinctly different embedded systems architectures, and one or more hardware devices that facilitate communication over multiple protocols contained in a portable package designed for both one-time and multi-occurrence use scenarios. In some embodiments, the reprogramming device is able to be used to enhance one or more attributes of performance of existing embedded systems through the reconfiguration of internally stored parameters. In some embodiments, the reprogramming device is also to be used to extract and receive information and instruction from existing embedded systems and enable useful presentation of this information. As a result, the reprogramming device is able to be used to adjust and/or monitor the parameters of the on-board diagnostics computer of a vehicle to ensure peak performance and detect errors.

2012-11-29

20120303947

Switching Between Multiple Operating Systems (OSes) Using Sleep State Management And Sequestered Re-Baseable Memory - Embodiments of switching between multiple operating systems (OSes) using sleep state management and sequestered re-baseable memory are generally described herein. Embodiments of the invention allow one OS to be suspended into S3 or sleep mode, saving its state to memory and turning off its devices. Then, another sleeping OS can be resumed from another location in memory by switching a memory base addressed to a sequestered memory region and restoring its device state. Other embodiments may be described and claimed.

2012-11-29

20120303948

ADDRESS TRANSLATION UNIT, DEVICE AND METHOD FOR REMOTE DIRECT MEMORY ACCESS OF A MEMORY - An address translation unit for Remote Direct Memory Access (RDMA) of a memory of a processor is provided. The address translation unit comprises an address translator and a signer. The address translator is configured to translate a received virtual address in a real address of the memory. The signer is configured to cryptographically sign the real address.

2012-11-29

20120303949

PACKET TRANSMISSION METHOD, APPARATUS, AND NETWORK SYSTEM - Embodiment of the present invention provides a packet transmission method. The method includes: receiving an encrypted packet sent by a client by using a virtual private network (VPN) tunnel, wherein the encrypted packet is sent by the client after the client determines, according to a preset control policy, that the control policy comprises an Internet Protocol (IP) address and a port number that are the same as a destination IP address and a destination port number of a packet to be sent and encrypts the packet to be sent, and the control policy comprises information about an IP address and a port number of an intranet server that can exchange a packet with a security socket layer protocol (SSL) VPN server; decrypting the encrypted packet; and sending the decrypted packet to a corresponding intranet server, wherein a source IP address of the decrypted packet is an external network IP address.

2012-11-29

20120303950

Implicit Certificate Scheme - A method of generating a public key in a secure digital communication system, having at least one trusted entity CA and subscriber entities A. The trusted entity selects a unique identity distinguishing each entity A. The trusted entity then generates a public key reconstruction public data of the entity A by mathematically combining public values obtained from respective private values of the trusted entity and the entity A. The unique identity and public key reconstruction public data of the entity A serve as A's implicit certificate. The trusted entity combines the implicit certificate information with a mathematical function to derive an entity information ƒ and generates a value k

Dynamic Platform Reconfiguration By Multi-Tenant Service Providers - A manageability engine or adjunct processor on a computer platform may receive a request for activation and use of features embedded within that platform from a service provider authorized by the manageability engine's manufacturer. The manageability engine may initiate a request for authority through the service provider to a permit server. The permit server may provide, through the service provider, proof of the service provider's authority, together with a certificate identifying the service provider. Then the manageability engine may enable activation of the features on the platform coupled to the manageability engine, but only by the one particular service provider who has been authorized.

2012-11-29

20120303953

Method and terminal equipment for applying digital rights management - A method and terminal equipment for applying digital rights management are disclosed by the present disclosure. The method includes the following steps: performing encryption processing on a portion of the content of a multimedia file using a pre-generated key when downloading the multimedia file; and downloading the encrypted multimedia file to a designated terminal equipment. With the present disclosure, the downloading speed of the multimedia file can be increased, and the waiting time for playing the file can be decreased.

2012-11-29

20120303954

Managing method, device and terminal for application program - A managing method for an application program is disclosed, which includes that: a first terminal converts a file of a specified application program stored by the first terminal per se into an intermediate file in a predetermined intermediate format, wherein the intermediate format can be identified by other terminals having a running environment of the application program (S

2012-11-29

20120303955

Security Association Management - A method and system for managing IPsec Security Associations in a Security Association Database (SADB) in an IP network is described. At a key management application, a domain extension header is inserted into a PF_KEY message containing instructions to a key engine unit. The domain extension header identifies a domain within the Security Association Database. The PF_KEY message is sent to the key engine unit, which carries out the instructions only for Security Associations in the domain of the Security Association Database indicated by the domain extension header.

2012-11-29

20120303956

SYSTEM AND METHOD FOR VERIFYING DELIVERY AND INTEGRITY OF ELECTRONIC MESSAGES - A server transmits a message from a sender to a destination address. During transmission, the server and the destination address have a dialog constituting an attachment, via a particular one of SMTP and ESMTP protocols, concerning the message, the server and the destination address. The message passes through servers between the server and the destination address. This passage is included in the attachment. Verifiers are provided for the message and for the attachments. The verifiers may constitute encrypted hashes of the message and of the attachment. The sender receives the message, the attachments and the verifications from the server before authentication and transmits the message, the attachments and the verifiers to the server to obtain authentication by the server. The server operates on the message and the message verifier to authenticate the message and operates on the attachments and the attachments' verifier to verify the attachments.

2012-11-29

20120303957

SOURCE-OF-LEAKAGE DETECTABLE E-MAIL ADDRESS FORMING, SENDING AND DETECTION - Provides e-mail address forming methods to know with certainty whether or not an e-mail address was leaked. A method includes: sending a receiver's identifier and a sender's identifier to a receiver's mail server; computing a value which is encrypted by the mail server with a secret key, the secret key being only possessed by the mail server, from the receiver's identifier, the sender's identifier, and a nonce issued by the mail server, and sending the value to a receiver; and forming an e-mail address (LD address) to be used by a sender who sends a mail to a receiver, by attaching a receiver's domain name to the encrypted value. Furthermore, the present invention has an e-mail address sending method, and en e-mail sending system which uses the e-mail address forming method to know with certainty whether or not the user of an e-mail address leaked the e-mail address.

2012-11-29

20120303958

SOURCE-OF-LEAKAGE DETECTABLE E-MAIL ADDRESS FORMING, SENDING AND DETECTION - Provides e-mail address forming methods to know with certainty whether or not an e-mail address was leaked. A method includes: sending a receiver's identifier and a sender's identifier to a receiver's mail server; computing a value which is encrypted by the mail server with a secret key, the secret key being only possessed by the mail server, from the receiver's identifier, the sender's identifier, and a nonce issued by the mail server, and sending the value to a receiver; and forming an e-mail address (LD address) to be used by a sender who sends a mail to a receiver, by attaching a receiver's domain name to the encrypted value. Furthermore, the present invention has an e-mail address sending method, and en e-mail sending system which uses the e-mail address forming method to know with certainty whether or not the user of an e-mail address leaked the e-mail address.

2012-11-29

20120303959

SOURCE-OF-LEAKAGE DETECTABLE E-MAIL ADDRESS FORMING, SENDING AND DETECTION - Provides e-mail address forming methods to know with certainty whether or not an e-mail address was leaked. A method includes: sending a receiver's identifier and a sender's identifier to a receiver's mail server; computing a value which is encrypted by the mail server with a secret key, the secret key being only possessed by the mail server, from the receiver's identifier, the sender's identifier, and a nonce issued by the mail server, and sending the value to a receiver; and forming an e-mail address (LD address) to be used by a sender who sends a mail to a receiver, by attaching a receiver's domain name to the encrypted value. Furthermore, the present invention has an e-mail address sending method, and en e-mail sending system which uses the e-mail address forming method to know with certainty whether or not the user of an e-mail address leaked the e-mail address.

2012-11-29

20120303960

Systems and Methods for Mutual Authentication Using One Time Codes - Methods and systems for mutual authentication and personalizing a transaction device, such as a payment, transaction, or identity card. Successively generated one time codes are calculated by a first and second entity. One of the codes is transmitted to the second entity, which verifies the code is proper, then encrypts a second one time code using a third one time code and transmits the encrypted data to the first entity. The first entity decrypts the data using the third one time code, verifies the encrypted second one time code is proper, thereby mutually authenticating, and establishing a shared encryption key for subsequent communications, including transmission of personalization data.

2012-11-29

20120303961

Systems and Methods for Authenticating Mobile Devices - Embodiments of the invention provide systems and methods for authenticating mobile devices. A registration request and identifying information for a mobile device or a secure element associated with the mobile device may be received. Based upon the received identifying information and a base level key, a rotated key for the mobile device may be determined. The determined rotated key may then be provided to the mobile device, and the rotated key may be utilized for subsequent authentication of the mobile device.

2012-11-29

20120303962

SYSTEM AND METHOD FOR EMBEDDING A WRITTEN SIGNATURE INTO A SECURE ELECTRONIC DOCUMENT - A system and method for embedding a written signature into a secure electronic document is disclosed. The method includes forming a placeholder electronic document containing content to be attested to by a signature. A signing individual can be selected from a signer list. A signature tag can be placed into the placeholder electronic document at a selected signature location. The signature tag is associated with the signing individual and defines the signature location for the signing individual to sign. The placeholder electronic document can be secured to form a secure electronic document having content configured to be uneditable. A signature can be captured with a signature capture device configured to enable the signing individual to write the signature to be embedded into the secure electronic document at the location indicated by the signature tag to mimic a real world experience of signing paper documents.

2012-11-29

20120303963

LONG-TERM SIGNATURE SERVER, LONG-TERM SIGNATURE TERMINAL, AND LONG-TERM SIGNATURE VERIFICATION SERVER - Long-term signature data is formed at a server side while a private key and the like are held at a client side. The long-term signature data is configured by arranging ES, STS, verification information, ATS (1st), and ATS (2nd) in a predetermined long-term signature format. Among these elements, those for which processing using the private key and original data are necessary are ES and ATS. Due to processing where the original data and the private key is necessary being performed by a client terminal

2012-11-29

20120303964

PORTABLE TERMINAL, AND METHOD FOR SECURING DATA TRANSMITTED BETWEEN HARDWARE MODULES - Provided are a portable terminal and a method for securing data transmitted between hardware modules of the portable terminal. The portable terminal may include an input module to encrypt input data, using a first secure key, if the portable terminal operates in a secure mode, and a processing module to receive the data, and to decrypt the user input data encrypted using the first secure key, using a second secure key, the first key and the second key being a pair.

2012-11-29

20120303965

SYSTEM FOR AND METHOD OF MANAGING ACCESS TO A SYSTEM USING COMBINATIONS OF USER INFORMATION - The present invention is directed to systems for and methods of controlling access to computer systems. A method in accordance with the present invention comprises performing a test that includes comparing input responses to randomly selected questions with corresponding pre-determined responses to the questions and granting access to the system in the event the test is passed. A first condition of passing the test is that each input response matches a corresponding pre-determined response. Once passing the test, the user is granted permissions to access data based on his position. For example, a corporate director generally has greater permissions than an engineer. Preferably, the user's permissions determine an encryption key and a decryption key that the user is able to use to access protected data.

DIGITAL RIGHTS MANAGEMENT SYSTEM AND METHOD FOR PROTECTING DIGITAL CONTENT - A digital content management system operative in a distributed network includes a SDP server and a client. The SDP server includes a content issuer and a right issuer. The content issuer is configured to randomly generate a first key, convert the first key to a second key by a conversion function, and encrypt a portion of a digital content item with the second key to form an encrypted portion, wherein the encrypted portion has its corresponding character code. The right issuer is configured to generate a right object, which includes the first key, and encrypt the right object.

2012-11-29

20120303968

METHOD AND SYSTEM FOR BUSINESS WORKFLOW CYCLE OF A COMPOSITE DOCUMENT - A method and system for a business workflow of a composite document are described. An integrity and authenticity of an entry table are identified and verified using a verification key, a map file corresponding to entries in the table are identified using a private user decryption key, signature verification keys and access keys are read from the map file, and authenticity of the map file and the document parts are verified. Following verification, content is delivered to a user for review, update and/or modification of the content, and then is encrypted, signed, and moved along the workflow, normally to the next workflow participant. A secure distribution version of a composite document is created from a master copy by creating a serialization including at least one part of a composite document and at least one user, creating a table listing document parts and associated users, generating encryption and decryption keys, encrypting document parts, applying signatures to encrypted document parts, updating the tables with the signed parts and updating the composite document with the updated tables. A master copy is updated from a secure distribution copy after the distribution copy has completed a workflow and a workflow wrap.

DATA STORAGE APPARATUS, STORAGE CONTROL APPARATUS AND DATA RECOVERY METHOD - According to one embodiment, a data storage apparatus includes a read module, a data transfer module, and a table generator. The read module reads encrypted data, in specific units, from a storage medium. The data transfer module transfers the data read by the read module, to a first buffer area. The table generator acquires key generation ID data identifying a new encryption key being used and an old encryption key used before, while the data transfer module is transferring the data, and generates table data including the key generation ID data associated with the units of data, respectively. The key generation ID data identifies the new encryption key being used and the old encryption key used before.

2012-11-29

20120303971

Dual Environment Computing System and Method and System for Providing a Dual Environment Computing System - A dual environment computing system and method is disclosed. The dual computing system includes a first computing environment and a second computing environment. A data repository encodes, at any one time, at least one of the first and second computing environments in a hibernated state. The dual environment computing system is arranged, on demand, to operate one of the first and second computing environments in an active state, the dual environment computing system being further arranged, on demand, to transition the one of the first and second computing environments being operated in the active state into a hibernated state in the data repository and to transition the other of the first and second computing environments from the hibernated state into an active state.

2012-11-29

20120303972

INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND PROGRAM - An information processing apparatus includes a data processor and a storage. The storage is divided into a protected area to which access is limited and a general purpose area which is freely accessible, and configured to store in the general purpose area encrypted content, and an encrypted title key obtained by encrypting a title key to be applied to decrypt the encrypted content, and store in the protected area a binding key applied to encrypt the title key, and a hash value of the encrypted title key. The data processor is configured to determine, in response to a request for access to the protected area from an external apparatus, whether or not to permit the access, and permit, only when access permission determination is made, the access to the protected area.

2012-11-29

20120303973

METHOD FOR PROTECTING SENSOR DATA FROM MANIPULATION AND SENSOR TO THAT END - In a method for protecting sensor data from manipulation, in the context of an authentication of the sensor, a number used once is sent from a control unit to the sensor, the sensor generating with the use of the number used once a cryptographic authentication message and sending at least a first part of the cryptographic authentication message to the control unit. In addition, the sensor data are provided with a cryptographic integrity protection, time-variant parameters being added to the sensor data and the sensor data being sent with the cryptographic integrity protection and the added time-variant parameters from the sensor to the control unit. For calculation of the initial parameters, at least a second part of the cryptographic authentication message is utilized.

2012-11-29

20120303974

Secure Removable Media and Method for Managing the Same - The invention provides a secure removable media. In one embodiment, the secure removable media comprises a non-volatile memory and a controller. The non-volatile memory corresponds to a media identifier, and comprises a public area, a hidden area, and a reserved hidden area for data storage, wherein a security program is stored in the public area, and a first firmware for retrieving the media identifier and a second firmware for accessing the hidden area are stored in the reserved hidden area. The controller receives secure data from an external device. The security program uses the first firmware to retrieve the media identifier from the secure removable media, generates an encryption key according to the media identifier given by the first firmware, encrypt the secure data according to the encryption key to obtain an encrypted secure data, and uses the second firmware to write the encrypted secure data to the hidden area. When the secure data is to be retrieved from the secure removable media, the security program reads the encrypted secure data from the hidden area, retrieves the media identifier from the non-volatile memory, generates a decryption key according to the media identifier given by the first firmware, and decrypts the encrypted secure data according to the decryption key to obtain the secure data.

2012-11-29

20120303975

DATA CONVERSION METHOD ON STORAGE MEDIUM, APPARATUS AND PROGRAM - In a data conversion auxiliary module which is at a higher level than a file system in a disk management hierarchy, data stored in a storage medium, which becomes an object, is successively accessed. Then, a data conversion module captures a sector-unit access request to a device driver from the file system, converts data of a sector which is returned from the device driver, and writes the conversion data in the sector. Thereby, data conversion can be executed on a specific region of the storage medium, which is associated with the data in the storage medium.

2012-11-29

20120303976

DATA STORAGE APPARATUS - A data storage apparatus includes a storage unit; a read/write console connected electrically to an external power supply source; a storage function unit; a power switch connected electrically to the power supply source, the storage unit and the storage function unit in such a manner that in a normal condition, the storage unit is charged electrically by the power supply source via the power switch, and that in an abnormal condition, the storage unit is supplied with electrical power from the power switch via the storage function unit so as to permit continuation of the read/write operation within the storage unit. A current detection unit detects current of the storage function unit in the abnormal condition and upon detecting current of the storage function unit reaching below a predetermined threshold value, the current detection unit generates and transmits a reset signal to the read/write console such that the read/write console orders a reset of the read/write operation.

2012-11-29

20120303977

POWER SUPPLY CIRCUIT - A power supply circuit includes a voltage converting module, a detecting module, a processor, and a selecting module. The voltage converting module includes at least one output port, each of which is connected to one load circuit to form a loop circuit. The detecting module can be selectively connected to a selected one of the formed loop circuits to detect at least one parameter of the loop circuit. The processor controls the selecting module to connect the detecting module to the selected loop circuit, and further determines the current of the loop circuit according to the at least one parameter.

2012-11-29

20120303978

COMPUTER INTEGRAL DEVICE SYSTEM AND METHOD THEREOF - A computer integral device includes a detection unit for detecting whether an external electronic device is in a determined position, wherein the external electronic device has been turned on; and a computer host, coupled to the detection unit. When the external electronic device is detected to be in the determined position, a power enable signal is sent to the computer host so as to activate the computer host to execute a computer turn on process. After the computer turn on process is executed by the computer host, the external electronic device may display image data received via a wireless communication link established between the computer host and the external electronic device.

2012-11-29

20120303979

COMPUTER APPARATUS AND POWER GENERATOR THEREOF - A power generator adaptive to a computer apparatus is provided. The power generator includes a logic operating unit, a power converting module, and a power management module. The logic operating unit receives a power pulse signal generated by a power button when the power button is pressed. The logic operating unit generates a power enabling signal according to the power pulse signal. The power converting module receives the power enabling signal and generates an internal voltage by converting an external voltage according to the power enabling signal. The power management module receives the internal voltage and the power pulse signal, and latches a generating state of the internal voltage according to the power pulse signal to generate a power stable signal. The power management module further provides the power stable signal to the logic operating unit to maintain a generating state of the power enabling signal.

2012-11-29

20120303980

WIRELESS POWER UTILIZATION IN A LOCAL COMPUTING ENVIRONMENT - Various embodiments of a wirelessly powered local computing environment are described. The wireless powered local computing environment includes at least a near field magnetic resonance (NFMR) power supply arranged to wirelessly provide power to any of a number of suitably configured devices. In the described embodiments, the devices arranged to receive power wirelessly from the NFMR power supply must be located in a region known as the near field that extends no further than a distance D of a few times a characteristic size of the NFMR power supply transmission device. Typically, the distance D can be on the order of 1 meter or so.

2012-11-29

20120303981

Providing power to powered device having multiple power supply inputs - A system for providing power to a load, having first and second power supply inputs respectively responsive to first and second input signals from first and second power supply sources to supply power to the load. For example, the first power supply input may be configured for supplying the load with power received from a communication link, such as an Ethernet link, and the second power supply input may be configured for supplying the load with power from an auxiliary power source. A power converter is provided to produce an output signal for supplying power to the load in response to the second input signal. The power converter is controlled to produce the output signal in accordance with a value of the first input signal.

2012-11-29

20120303982

ELECTRONIC DEVICE CONTROLLING SYSTEM AND METHOD - A cloud server of a data center being used to control electronic devices. The cloud server receives employee information from a client in electronic communication with the cloud server a first time. The cloud server notifies a power supply to power on electronic devices corresponding to an employee, in response to a determination that employee information matches identification information of the employee. The cloud server notifies the power supply to turn off the electronic devices corresponding to the employee when the cloud server receives the employee information from the client a second time.

System and Method of Utilizing Resources within an Information Handling System - A method of utilizing an information handling system includes detecting an event by a state controller configured to enable a plurality of operating states for a host system including a host system power on state and a host system power off state, and a plurality of processing module operating states including a processing module power on state and a processing module reduced operating state, and enabling an operating state associated with the event, including enabling the processing module power on state where the processing module controls a shared resource and a processing module non-shared resource in response to detecting a processing module power on event, and enabling the processing module reduced operating state where the processing module controls the shared resource in response to detecting a processing module reduced operating event.

2012-11-29

20120303985

State retention circuit adapted to allow its state integrity to be verified - A state retention component is provided which is configured to form part of data processing circuitry. The state retention component is configured to hold a state value at a node of the data processing circuitry when the data processing circuitry enters a low power mode. The state retention component comprises a scan input, wherein the state retention component configured, when a scan enable signal is asserted, to read in the state value from a scan input value applied at the scan input, and a scan output, wherein the state retention component is configured, when the scan enable signal is asserted, to read out the state value to the scan output. When the scan enable signal is not asserted, the state retention circuit outputs at the scan output a parity value, wherein the parity value is generated by combinatorial function circuitry on the basis of the state value and the scan input value, wherein the combinatorial function circuitry is configured such that the parity value inverts if either the state value or the scan input value changes, thus providing an external indication of the integrity of the state value held by the state retention component.

2012-11-29

20120303986

Verifying state integrity in state retention circuits - A data processing apparatus is provided comprising data processing circuitry configured to perform data processing operations. A plurality of state retention circuits forms part of the data processing circuitry and these circuits are configured to hold respective state values at respective nodes of the data processing circuitry it enters a low power mode. One or more scan paths connect the plurality of state retention circuits together in series, such that the state values may be scanned into and out of the respective nodes. A plurality of parity information generation elements are coupled to the scan path(s) and configured to generate parity information indicative of the respective state values held at those respective nodes by the state retention circuits. The plurality of parity information generation elements are arranged to provide one or more parity path(s), such that an output parity value generated at an output of the parity path will invert if one of said respective state values changes, providing an external indication of the integrity of the state values held by the state retention circuits.

2012-11-29

20120303987

ENERGY CONTROL APPARATUS AND METHOD USING PROPERTY OF ELECTRONIC DEVICE - An energy control apparatus and method using a usage property of an electronic device. The energy control method may include: setting a total power consumption to be less than a predetermined threshold; verifying a usage property for each electronic device when a collected total power consumption exceeds the threshold; calculating a scheduled end time based on the average usage time of each remaining electronic device excluding, from among operating devices, an electronic device of which power-off is unavailable; verifying a remaining electronic device excluding an electronic device of which scheduled end time is less than the threshold; controlling a temporarily stoppable electronic device to be temporarily stopped; controlling a power adjustable electronic device to decrease a power consumption when the total power consumption exceeds the threshold; and starting the temporarily stopped electronic device at a point in time when the total power consumption decreases to be less than the threshold.

2012-11-29

20120303988

DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD - When a packet received in a deep sleep mode matches a packet stored in a WOL-pattern storage region, a network portion performs reply processing suited for the matched packet after returning a power supply mode of a power supply unit from the deep sleep mode to a normal mode. When the packet received in the deep sleep mode matches a packet stored in a proxy-response-pattern storage region, the network portion performs reply processing suited for the matched packet while maintaining the power supply mode of the power supply unit at the deep sleep mode.

2012-11-29

20120303989

INFORMATION PROCESSING APPARATUS AND METHOD OF CONTROLLING LAUNCH THEREOF - An information processing apparatus is capable of quick launch, in which information of memory is held and the apparatus is launched using the information, and includes an RTC that keeps the time and generates an interrupt at a set time. The apparatus detects whether or not there is an instruction to turn a power supply on or off, and if an instruction to turn the power off is detected, determines whether or not the quick launch is active. If it is determined that the quick launch is active, the apparatus sets an interrupt generated by the RTC inactive.

2012-11-29

20120303990

POSTPONING SUSPEND - According to one general aspect, a method may include operating a computing device in a first power mode. The method may also include executing, by a processor of the computing device, at least one non-interactive task. The method may also include detecting, by a processor of the computing device, a request to place the computing device in a second power mode, wherein the second power mode consumes less system resources than the first power mode. The method may further include delaying the transition of the computing device to the second power mode until either the completion of the non-interactive task or an overriding triggering event.

2012-11-29

20120303991

METHOD AND APPARATUS FOR IMPROVED POWER MANAGEMENT OF MICROPROCESSORS BY INSTRUCTION GROUPING - A method of power gating a microprocessor having an instruction scheduling unit for receiving issued instructions from an instruction decoder; an execution unit receiving and sending signals from and to the instruction scheduling unit; and a state machine. The method comprises: obtaining a number of instructions per cycle being issued to the instruction scheduling unit; determining, if the number of instruction per cycle being issued to the instruction scheduling unit is less than a threshold level, and then determining if at least two of the instructions being issued to the instruction scheduling unit are independent of each other only when the instructions per cycle is less than the threshold level; determining when at least two of the instructions being issued to the instruction scheduling unit are independent of each other; and power gating the microprocessor to gate off power to idle macros with a signal from the state machine.

2012-11-29

20120303992

DISPLAY AND POWER MANAGEMENT METHOD THEREOF - A display and a power management method thereof are disclosed. The method includes: detecting a state of a Graphic Interface Card (GIC) in the display; turning off power supply to the GIC when the GIC is in a first state; and turning on power supply to the GIC when the GIC is in a second state. The method is capable of reducing power consumption of a display to satisfy environment protection requirements without sacrificing the functionality of the display's GIC.

2012-11-29

20120303993

METHOD AND APPARATUS FOR IMPROVED POWER EFFICIENCY FOR SERVER PLATFORMS - In one embodiment, a method includes determining if a power load requirement associated with a server arrangement is below a threshold. The server arrangement includes at least a first power supply and a second power supply, as well as a capacitor arrangement. The method also includes providing power to the server arrangement using the first power supply and not the second power supply when it is determined that the power load requirement is below the threshold, and providing the power to the server arrangement using the first power supply and the second power supply when it is determined that the power load requirement is not below the threshold.

2012-11-29

20120303994

APPARATUS FOR SYNCHRONIZING A DATA HANDOVER BETWEEN A FIRST CLOCK DOMAIN AND A SECOND CLOCK DOMAIN - Embodiments of the present invention provide an apparatus for synchronizing a data handover between a first clock domain and a second clock domain. The apparatus includes a calculator, a first-in-first-out storage, a synchronization pulse generator, a fill level information provider and a feedback path. The calculator is clocked with the clock of the first clock domain and configured to provide a synchronization pulse cycle duration information describing a temporal position of synchronization pulses at a clock of the second clock domain. The first-in-first-out storage is configured to take over an input data value in synchronization with the first clock domain and to provide an output data value in synchronization with the second clock domain and in response to a current synchronization pulse. The synchronization pulse generator is clocked with the clock of the second clock domain and configured to generate the subsequent synchronization pulse such that the subsequent synchronization pulse is located at the temporal position described by the synchronization pulse cycle duration information. The fill level information provider is configured to provide a fill level information describing a fill level of the first-in-first-out storage. The feedback path is configured for feeding back the fill level information to the calculator that is further configured to adjust the synchronization pulse cycle duration information based on the fill level information.

2012-11-29

20120303995

METHOD AND APPARATUS SYNCHRONIZING INTEGRATED CIRCUIT CLOCKS - Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.

2012-11-29

20120303996

APPARATUS FOR SYNCHRONIZING A DATA HANDOVER BETWEEN A FIRST CLOCK DOMAIN AND A SECOND CLOCK DOMAIN - Embodiments of the present invention provide an apparatus for synchronizing a data handover between a first clock domain and a second clock domain. The apparatus includes a calculator, a synchronization pulse generator, a phase information provider and a feedback path. The calculator is clocked with a clock of the first clock domain and configured to provide synchronization pulse cycle duration information describing a temporal position of a synchronization pulse at a clock of the second clock domain. The synchronization pulse generator is clocked with the clock of the second clock domain and configured to generate the synchronization pulse such that the synchronization pulse is located at the temporal position described by the synchronization pulse cycle duration information. The phase information provider is clocked with the clock of the second clock domain and configured to provide a phase information describing a phase relation between the synchronization pulse and the clock of the first clock domain. The feedback path is configured for feeding back the phase information to the calculator. In addition, the calculator is configured to adjust the synchronization pulse cycle duration information based on the phase information.

2012-11-29

20120303997

Flexible Bus Architecture for Monitoring and Control of Battery Pack - A method for diagnosing a control system for a stacked battery. The control system comprises a plurality of processors, a plurality of controllers, and a monitoring unit (control unit). The method comprises sending a diagnostic information from the central unit to a top processor of the plurality of processors, transmitting a return information from the top processor of the plurality of processors to the central unit, comparing the diagnostic information sent from the central unit with the return information received by the central unit, and indicating a communication problem if the diagnostic information sent from the central unit is different from the return information received by the central unit. The steps are repeated by eliminating the top processor from a previous cycle and assigning a new top processor if there is no problem with the reconfigurable communication system.

IMPLEMENTING FAILOVER PROCESSES BETWEEN STORAGE STAMPS - Embodiments of the present invention relate to invoking and managing a failover of a storage account between partitions within a distributed computing environment, where each partition represents a key range of data for the storage account. The partitions affected by the failover include source partitions hosted on a primary storage stamp and destination partitions hosted on a secondary storage stamp, where the storage account's data is being actively replicated from the primary to the secondary storage stamp. Upon receiving a manual or automatic indication to perform the failover, configuring the source partitions to independently perform flush-send operations (e.g., distributing pending messages as a group) and then configuring the destination partitions to independently perform flush-replay operations (e.g., aggressively replaying currently pending transactions). Upon completing the flush-replay operations, designating the secondary storage stamp as a new primary storage stamp such that live traffic is directed to the new primary storage stamp.

2012-11-29

20120304000

RESTORING STORAGE DEVICES BASED ON FLASH MEMORIES AND RELATED CIRCUIT, SYSTEM, AND METHOD - A restoring operation of a storage device based on a flash memory. In an embodiment, a storage device emulates a logical memory space (including a plurality of logical blocks each one having a plurality of logical sectors), which is mapped on a physical memory space of the flash memory (including a plurality of physical blocks each one having a plurality of physical sectors for storing different versions of the logical sectors). A method may detect a plurality of conflicting physical blocks for a corrupted logical block and determines a plurality of validity indexes. One or more of the conflicting physical blocks are selected according to the validity indexes. The selected conflicting physical blocks are then associated with the corrupted logical block. At the end, each one of the non-selected conflicting physical blocks is discarded.

2012-11-29

20120304001

IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH CHAINED HARDWARE OPERATIONS AND ERROR RECOVERY FIRMWARE PATH - A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to minimize hardware and firmware interactions and a bridge code configured to select a firmware sequence for error recovery to complete the operations responsive to an identified error in the predefined chain, and a design structure on which the subject controller circuit resides are provided. A selected predefined chain is configured to implement a particular performance path to maximize performance. Responsive to an identified predefined error during hardware operations in the predefined hardware chain, a bridge code is configured to select a non-performance path firmware sequence for error recovery completion of remaining operations.

2012-11-29

20120304002

MANAGING ROLLBACK IN A TRANSACTIONAL MEMORY ENVIRONMENT - A system and technique for managing rollback in a transactional memory environment is disclosed. The system includes a processor, a transactional memory, and a transactional memory manager (TMM) configured to perform a rollback on the transactional memory. The TMM is configured to, responsive to detecting a begin transaction directive by the processor, detect an access of a first memory location of the transactional memory not needing rollback and indicate that the first memory location does not need to be rolled back while detecting an access to a second memory location of the transactional memory and indicating that a rollback will be required. The TMM is also configured to, responsive to detecting an end transaction directive after the begin transaction directive and a conflict requiring a rollback, omit a rollback of the first memory location while performing rollback on the second memory location.

2012-11-29

20120304003

OPERATOR STATE CHECKPOINTS - A checkpoint marker can be received at a first operator. The first operator can process the checkpoint marker by sending the checkpoint marker to a second operator and sending state checkpoint information representing a state of the first operator to a checkpoint writer. The checkpoint information can be used to rehydrate the state of one or more operators. For example, after a system failure, system shutdown, etc., checkpoint information can be received from a reader unit at a checkpoint information input queue of the first operator. A state of the first operator can be rehydrated using the checkpoint information. Processing of information in a data input queue of the first operator can be suspended while the checkpoint information is used to rehydrate the state of the first operator. Other operators in a system with the first operator (e.g., the second operator) may be checkpointed and rehydrated in the same manner as the first operator.

2012-11-29

20120304004

RECOVERY OF A FAILED REGISTRY - A system, method, and computer-readable medium, is described that enables a registry recovery service to retrieve zone files from a target registry, archive the zone files, publish the zone files to a managed DNS server, reconcile ownership of the zone files, and publish the zone files to a provisioning DNS server. The registry recovery service may also implement a WHOIS server for the zone and ownership information and may also implement zone specific features particular to the target registry's TLD. The registry recovery service may also enable DNSSEC extensions on the recovered registry DNS services.

2012-11-29

20120304005

ELECTRONIC APPARATUS - A failure caused by a soft-error including MNU, of an electronic apparatus is prevented, while suppressing increase of a mounting area, power consumption, and processing time. The electronic apparatus stores data indicating the state of a flip-flop included in a sequential logic circuit within an arithmetic unit, each time when execution is performed on a check point provided for every predetermined number of instructions. When a symptom of a soft-error is detected, the apparatus sets the state of the flip-flop included in the sequential logic circuit within the arithmetic unit, based on the data stored after execution of the instruction at the immediately preceding check point, and restarts execution from the next instruction, being subsequent to the instruction associated with the immediately preceding check point.

2012-11-29

20120304006

LOW TRAFFIC FAILBACK REMOTE COPY - The local storage performs remote copy to the remote storage. For low traffic failback remote copy, the remote storage performs a delta copy to the local storage, the delta being the difference between the remote storage and local storage. The local storage backs up snapshot data. The remote storage resolves the difference of the snapshot of the local storage and the remote storage. The difference resolution method can take one of several approaches. First, the system informs the timing of snapshot of the local storage to the remote storage and records the accessed area of the data. Second, the system informs the timing of snapshot of the local storage to the remote storage, and the remote storage makes a snapshot and compares the snapshot and remote copied data. Third, the system compares the local data and remote copy data with hashed data.

2012-11-29

20120304007

METHODS AND SYSTEMS FOR USE IN IDENTIFYING ABNORMAL BEHAVIOR IN A CONTROL SYSTEM - Methods and apparatus for use in identifying abnormal behavior in a control system. Operating events associated with a control system are received, and an actual behavior of the control system is determined based on the received operating events. The actual behavior is compared to expected behavior to determine whether the actual behavior differs from the expected behavior. The expected behavior includes a correlation between a plurality of operating events associated with the control system. The expected behavior is updated based on an indication of whether the actual behavior is abnormal from a user.

2012-11-29

20120304008

SUPERVISED FAULT LEARNING USING RULE-GENERATED SAMPLES FOR MACHINE CONDITION MONITORING - A machine fault diagnosis system is provided. The system combines a rule-based predictive maintenance strategy with a machine learning system. A simple set of rules defined manually by human experts is used to generate artificial training feature vectors to portray machine fault conditions for which only a few real data points are available. Those artificial training feature vectors are combined with real training feature vectors and the combined set is used to train a supervised pattern recognition algorithm such as support vector machines. The resulting decision boundary closely approximates the underlying real separation boundary between the fault and normal conditions.

2012-11-29

20120304009

TEST APPARATUS AND TEST METHOD - A test apparatus that tests a device under test outputting a data signal and a clock signal indicating a timing at which the data signal is to be sampled, comprising an acquiring section that acquires the data signal output by the device under test, at a timing corresponding to the clock signal; a buffer section that includes a plurality of entries, buffers the data signal acquired by the acquiring section at the timing corresponding to the clock signal sequentially in the entries, and outputs the data signal buffered in the entries at a timing of a timing signal generated according to a test period of the test apparatus; and a judging section that judges pass/fail of the device under test based on a result of a comparison between the data signal output from the buffer section and an expected value.

2012-11-29

20120304010

CODE COVERAGE-BASED TAINT PERIMETER DETECTION - A code coverage-based taint perimeter detection system and method for testing software code by determining code coverage and detecting new coverage of the code. Embodiments of the system and method perform tainted data flow analysis on execution traces of the code to determine tainted branch targets. The tainted branch targets may be filtered to remove any tainted branch targets that have already been covered. New coverage can be determined by monitoring the filtered tainted branch targets, which in some embodiments involves the use of software breakpoints that are automatically placed at the locations in the tainted branch targets at runtime. Embodiments of the system and method use an iterative process to ensure that only tainted branch targets that have not already been covered or tested are examined.

2012-11-29

20120304011

SERVER AND POWER SUPPLY TEST METHOD - A control server is electronically connected with a number of test servers via a number network interfaces. The control server records a network interface number and an IP address of a baseboard management controller (BMC) of each test server, sets an IP address of a network card of the control server, and generates a test command. The test command comprises information in relation to a number of times for powering on a test server, a number of times for powering off the test server, and a time interval between a power-on operation and a power-off operation. The test command is sent to each test server by the control server according to the network interface number and the IP address of the test server. After receiving the test command, the BMC of the test server performs power-on/power-off operations of the test server according to the test command.

2012-11-29

20120304012

Administering Incident Pools For Event And Alert Analysis - Administering incident pools including receiving, by an incident analyzer from an incident queue, a plurality of incidents from one or more components of the distributed processing system; assigning, by the incident analyzer, each received incident to a pool of incidents; assigning, by the incident analyzer, to each incident a particular combined minimum time for inclusion in one or more pools, each particular combined minimum time corresponding to a particular incident; in response to the pool closing, determining, by the incident analyzer, for each incident in the pool whether the incident has met its combined minimum time for inclusion in one or more pools; and if the incident has been in the pool for its combined minimum time, including, by the incident analyzer, the incident in the closed pool; and if the incident has not been in the pool for its combined minimum time, including the incident in a next pool.

2012-11-29

20120304013

Administering Event Pools For Relevant Event Analysis In A Distributed Processing System - Methods, systems, and computer program products for administering event pools for relevant event analysis are provided. Embodiments include assigning, by an incident analyzer, a plurality of events to an events pool; determining, by the incident analyzer, an event suppression duration; determining, by the incident analyzer in dependence upon event analysis rules, to suppress events having particular attributes indicating the events occurred during the event suppression duration; and suppressing, by the incident analyzer, each event assigned to the events pool having the particular attributes indicating the events occurred during the event suppression duration.

2012-11-29

20120304014

PERFORMING ASYNCHRONOUS TESTING OF AN APPLICATION OCCASIONALLY CONNECTED TO AN ONLINE SERVICES SYSTEM - In a method, system, and computer-readable medium having instructions for performing asynchronous testing of an application that is occasionally connected to an online services system, metadata describing at least a portion of an online services database is retrieved and the at least a portion of the online services database is authorized for replication at a software application, information is determined for an entity for an application database from the metadata, a request is sent for a database using the software application interface and the request has an asynchronous operation call to the database for the entity, an execution of the asynchronous operation call is recorded within a callback function, a response is received for the asynchronous operation call, and a result is determined for the software application performance.

2012-11-29

20120304015

GENERATING APPROPRIATELY SIZED CORE FILES USED IN DIAGNOSING APPLICATION CRASHES - A method, system and computer program product for generating appropriately sized core files used in diagnosing application crashes. An instruction pointer corresponding to the instruction that led to the application crash is identified. Address ranges of the garbage collection module and the compiler module are obtained. A determination is made as to whether the address of the instruction pointer lies within any of these address ranges for each stack frame in a crash stack. If it does not, then read or write instructions executed prior to the instruction that led to the application crash are identified for each stack frame in the crash stack. If a value of a register involved in such read or write instructions is within the address range of the compiled code buffers and/or heap, then the compiled code buffers and/or heap need to be included in the core file; otherwise, they do not.

2012-11-29

20120304016

STORAGE CONTROL DEVICE, STORAGE DEVICE, AND DIAGNOSTIC METHOD - A storage control device includes an interface for a host computer and a memory device and a control unit that creates a read command that causes the memory device to reproduce data at an access target address, and creates a first diagnosis command that causes the memory device to conduct a diagnostic reproduction at an address subsequent to the access target address, according to the request received from the host computer, sequentially issues the read command and the first diagnosis command to cause the memory devices to execute sequential accessing and conducts a diagnosis to confirm the normality of the memory device.

2012-11-29

20120304017

SYSTEMS AND METHODS FOR 1553 BUS OPERATION SELF CHECKING - Systems and methods for 1553 bus operation self checking are provided. In one embodiment, a fault tolerant computer comprises a self-checking processor pair that includes a master processor, a checking processor, and self-checking pair logic; a 1553 bus transceiver; and a device comprising 1553 self-checking logic coupled between the self-checking processor pair and the 1553 bus transceiver, wherein the 1553 self-checking logic manages data communication between the 1553 bus transceiver and the self-checking processor pair. The 1553 self-checking logic includes a primary logic and a secondary logic that operate in lock-step. When the 1553 self-checking logic writes data to the 1553 bus transceiver, the 1553 self-checking logic compares a first 1553 formatted message generated by the primary logic to a second 1553 formatted message generated by the secondary logic, and generates an error indication when the first 1553 formatted message does not match the second 1553 formatted message.

2012-11-29

20120304018

APPARATUS FOR TESTING BASIC INPUT OUTPUT SYSTEM CHIP - An apparatus for testing a basic input output system (BIOS) chip includes a base and a connector. The base defines a receiving space for housing the BIOS chip. A number of signal pins are formed on sidewalls bounding the receiving space, to electrically connect the BIOS chip. The connector extends from a bottom of the base, and is electrically connected to the signal pins of the base to be connected to a diagnose card to debug the BIOS chip.

2012-11-29

20120304019

METHOD AND APPARATUS FOR MEMORY DUMP PROCESSING AND A MEMORY DUMP SYSTEM - The present application provides a method, an apparatus and a system for memory dump processing. The method comprises: invoking a first set of processing units to process a first stage of memory dump processing for each of memory blocks; invoking each set of processing units other than the first set of processing units to process a subsequent processing stage after completing the first stage respectively, to write the memory blocks into a storage device. The technical solutions provided in the present application enable processing each stage for each of the memory blocks in a pipeline manner, avoid instantaneous peak flow of disk I/O transmission and improve memory dump performance.