Hello, I'm using the 'ShiftReg V2.10' component to serialize a data stream out to a PIN. But, as the stream length is not fixed and/or the receiver of bitstream can terminate and request a restart of stream datas - I need a controlable flush of current FIFO datas in the input queue that was written by CPU into FIFO. I found the 'CLR FIFO' bits in the AUX CONTROL REG, but it seems for me that it is not working ?!? After using following code: REG_SHFT1_SR_AUX_CONTROL |= 0x03; REG_SHFT1_SR_AUX_CONTROL &= ((uint8) ~0x03); the 'F0_empty' seems never set: while (!(REG_SHFT1_SR_STATUS & 0x08)) CY_SYS_PINS_CLEAR_PIN(LED_B__DR, LED_B__SHIFT); Is there any clou to use it ??? I see that you defined the BIT to clear output FIFO for software-capture feature inside the component-code. But, as you use software-looped readout for FIFO to clear the output-queue... I doupt that this mechansim is working correctly, maybe ??? Please give me some hint how to clear/flush the input FIFO by HW routing or application SW, in case that it is loaded with invalid datas already. The clock input of component is gated and not active at the moment I use the 'clear FIFO' bits. Is it required to have a running clock on 'RegShift' component to do the flush by these bits Many thanks for your help and best regards. Carsten