Test techniques for Advanced Processors

@PhdThesis{sanchez:thesis,
author = "Edgar Ernesto {Sanchez Sanchez}",
title = "Test techniques for Advanced Processors",
school = "Politecnico di Torino, Scuola di Dottorato in
Ingegneria Informatica e dei Sistemi",
year = "2006",
type = "Tesi di Dottorato",
address = "Italy",
month = feb,
keywords = "genetic algorithms, genetic programming",
URL = "http://www.cad.polito.it/pap/db/__thesis_EESS.pdf",
size = "76 pages",
abstract = "As sketched by the SIA02 roadmap, today most of the
integrated circuit (IC) manufacturing cost is brought
about by the test and validation processes. The
increasing difficulty to generate appropriate testing
and validation patterns and the expensive elaboration
times required to test an IC, raised these costs up to
near 70percent. Moreover, test methodologies do not
progress at the same pace the manufacturing technology
does, contributing to enlarge the cost gap. The problem
of test is especially critical in the case of
microprocessors and microcontrollers. Modern designs
contain complex architectures that increase test
complexity. Indeed, pipelined and superscalar designs
have been demonstrated to be random pattern resistant.
Nowadays, the only possibility to test and verify both
practically and economically processor cores, relies on
the execution of carefully crafted programs. These
programs, usually called test programs, are composed of
a valid sequence of assembly instructions, that is fed
to the processor through its normal execution
instruction mechanism, and whose goal is to uncover any
possible design or production flaw in the processor
under test. In this thesis, a software-based
methodology to automatically generate test programs is
described. The methodology is based on an evolutionary
algorithm able to automatically generate test programs
for microprocessor cores, and may be used for different
processors since their instruction set architecture is
described in the form of an instruction library, and
because a fitness function can be defined, computed,
and used to drive the automatic generation of test
programs. The usefulness of the methodology is backed
up by the presentation of 3 different flavoured cases
of study: the first one tackles the verification of the
DLX/pII processor, the second one generates
post-silicon verification programs for the Pentium 4,
and the third one evolves a test set for the PLASMA
processor. The gathered experimental results
demonstrate the algorithm versatility and efficiency.
1. INTRODUCTION 4
2. STATE OF THE ART 9
3. PROPOSED APPROACH 13, EXPLOITATION OF EXISTING
PROGRAMS 18, DIVERSITY IN microGP 19
4. TEST PROGRAM GENERATION FOR PROCESSOR VERIFICATION
24, FUNCTIONAL VERIFICATION PLAN 25, TEST SET
GENERATION 26, EXPERIMENTAL EVALUATION 27, AUTOMATIC
COMPLETION OF EXISTING FUNCTIONAL TEST SETS 27, METRIC
COMPARISON 29, PURELY RANDOM APPROACH 31
5. TEST PROGRAM GENERATION FOR POST-SILICON
VERIFICATION 33, PROPOSED APPROACH 34, CASE STUDY: THE
PENTIUM 4 MICROPROCESSOR 36, EXPERIMENTAL SETUP 38,
EXPERIMENTAL RESULTS 40
6. TEST PROGRAM GENERATION FOR PROCESSOR TESTING 44,
METHODOLOGY DESCRIPTION 45, ARCHITECTURAL MODELS 47,
RT-LEVEL MODELS 49, PURE RT-LEVEL MODELS 49, HYBRID
RT-GATE LEVEL MODELS 52, GATE MODELS 52, CASE STUDY 53,
EXPERIMENT SETUP 55, EXPERIMENTAL RESULTS 56, HIGH
LEVEL METRICS COMPARISON 61
7. TEST PROGRAM GENERATION FOR SOLVING OBSOLESCENCE
PROBLEM 63, VERIFICATION METHODOLOGIES 65, EXPERIMENTAL
RESULTS 67
8. CONCLUSIONS 70
REFERENCES 72",
notes = "In english
",
}