optionally on data input, K/K#, and BWx#.
The end of top mark (A/A1/A2) is to define options.
IS61QDPB251236A : Don’t care ODT function
and pin connection
IS61QDPB251236A1 : Option1
IS61QDPB251236A2 : Option2
Refer to more detail description at page 6 for each
ODT option.
OCTOBER 2014
and
are synchronous, high-
performance CMOS static random access memory (SRAM)
devices. These SRAMs have separate I/Os, eliminating the
need for high-speed bus turnaround. The rising edge of K
clock initiates the read/write operation, and all internal
operations are self-timed. Refer to the
for a description of the basic
operations of these
SRAMs. Read and
write addresses are registered on alternating rising edges of
the K clock. Read and write performed in double data rate.
The following are registered internally on the rising edge of
the K clock:

Read address

Read enable

Write enable

Data-in for early writes
The following are registered on the rising edge of the K#
clock: