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ソリューション

What's New

- N/A (first release).

Known Issues

1. In the example design, the ClientRxStatus[5:0] output from the client side of the Fibre Channel v1.0 Core connects to the "fifo.vhd" or "fifo.v" design. However, only ClientRxStatus(4) is used inside the FIFO, which causes the rest of the bus to be optimized away. This will then cause errors when starting the simulation because this bus cannot be found, although it is listed in the "wave.do" file. The error specifies only that the signal cannot be found; this is not a problem with the core.

To work around this issue and prevent the ClientRxStatus bus from being removed, a signal named "temp1" is created from the bitwise-OR of this bus. When integrating the core into the user design, this will not be necessary if all bits of the bus are used or if the ClientRxStatus bus is not included in the simulation.

2. If ClientTxParity[1:0] is tied to "00", MAP will remove the parity checking logic and the control register. This will result with every frame having a bad CRC and an EOFni, even if both Parity (Bit 3) and EOFni (Bit 2) are disabled in the LinkControl (0x010) register.

To work around this issue, it is suggested that you do all of the following:

- Tie ClientTxParity[1:0] to the "temp1" signal created in issue #2 from above.

Since the "temp1" signal is non-constant, the logic parity checking logic will not be optimized away. This is how the port is connected in the top-level wrapper file that is generated with the Core.

3. The link for "Solution Records for this Core" on the "Web Links" tab of the "Customize..." window for the Fibre Channel Core does not produce any results.

To obtain valid results, make the following changes to the search string of the Web page and search again:

- Remove "coregen" from the search string.

- Remove the commas from the search string and separate the words by spaces.

or

- Search for "Fibre Channel."

4. If the Fibre Channel v1.0 Core is generated with Statistics, an enhancement exists to achieve 20% lower slice utilization. For more information on this issue, see (Xilinx Answer 19942).

- To obtain this enhancement, please install the patch below and regenerate the Core.

5. If the Fibre Channel v1.0 Core is operating at 2 Gb/s, the transmitter does not always transmit at the minimum IFG. For more information on this issue, see (Xilinx Answer 20215).

- To resolve this issue, please install the patch below and regenerate the Core.

6. In the FIFO used for the example design, the FIFO might get stuck when writing address loops back to 0. The address will loopback only if a large number of frames have been sent through it. This is not an issue with the Core, only with the example FIFO.

- To resolve this issue, install the patch below and regenerate the Core.

7. The Receive Error Statistics, Rx10bErrCnt and RxOsdErrCnt, might be incorrect occasionally. For more information on this issue, see (Xilinx Answer 20440).

- To resolve this issue, install the patch below and regenerate the Core. The new Core netlist and FCMGT.vhd or FCMGT.v file will contain the fixes necessary to resolve this issue.

8. The VHDL demonstration testbench (demo_tb.vhd) incorrectly initializes the Clk2N1 and Clk2P1 clock signals, which causes the MGTs to be improperly setup at the start of simulation for certain configurations.

- To resolve this issue, install the patch below and regenerate the Core. The new "demo_tb.vhd" will resolve this issue.

Patch

To resolve issues #4, #5, #6, #7, and #8 from above, apply the appropriate patch below for the version of ISE that you are using:

If the patch was installed for the 6.2.03i IP Update 1.2 version of the Core and then IP Update 4 was installed, the patch must be reinstalled. This is necessary because the IP Update 4 does not contain the fixes, and installing it overwrites the patched files.

Install the patch as follows:

1. Unzip the contents of the ".zip" file or "tar.gz" archive to the root directory of the Xilinx installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure pre-defined in the archive.

PC

Determine the Xilinx installation directory by entering the following at the command prompt:

"echo %XILINX%"

UNIX or Linux

Determine the Xilinx installation directory by typing the following:

"echo $XILINX"

NOTE: You might need to have system administrator privileges to install the patch.

2. After installing the patch, regenerate the Fibre Channel Core from the CORE Generator. The Core netlist, "demo_tb.vhd," and "FCMGT.v/FCGMT.vhd" files that are created will contain the fixes mentioned above. The Product Specification will also include the updated Device Utilization values.