FE-I4ATLASPixelChipDesignMarlon BarberoFigure 3: Sketch of the data transfer from Double-Column down to the storage FIFO.Hit data organization in record bandwidth reduction bits in recordSingle Pixel Hit Transfer 0% 202-Hit Transfer (fixed in region) 4% 232-Hit Transfer (across regions) 13% 244-Hits (in Double-Column) 5% 314-Hits (across Double-Columns) 15% 32Table 1: Bandwidth reduction with respect to single pixel hit transfer and size of record as afunction of record organization for a central module in the IBL.As a consequence, the reformatting algorithm chosen consists of sending 2 pixels hitsadjacent in φ together in the same data record, which not only reduces the data bandwidth out ofthe Front-End and fits a byte-based format, but also is in practice particularly simple toimplement. The data records are hence stored in the FIFO in the form of 3 times 8-bit records.The digital control block takes care of providing the logic to perform the transfer of the pixelhits from the 4-pixel regions to the FIFO. It also handles the recording of other types of datasuch as data header (header for transmission of pixel data), service messages (e.g. errormessages), address records and value records (for read back of global or local registers), or thevalue of the empty record word. Table 2 shows the 6 types of record word. All record words are24 bits long. Data header, address record, value record and service record can start an eventtransmission and as such start with 11101 flag (similar to what is done in the current ATLASpixel module [6]). The data stored in the FIFO are then transmitted out in slices of 8 bits by amechanism driven from the Data Output Block.5.2 Clock Multiplier unit, Data Output Block and 8b10b CoderSimulation has shown [7] that to fit IBL needs, data has to be transmitted out of FE-I4 at abandwidth of 160 Mb.s-1. The LHC bunch-crossing clock and hence the clock which reachesFE-I4 is 40MHz. As the IBL is inserted inside the present ATLAS pixel detector, it needs to fitconstraints of an already built-up system. In particular, sending a higher frequency clock to the7