Puneet Gupta

Puneet Gupta, Houston, TX US

Patent application number

Description

Published

20090000194

Systems and Methods of Converting Fuel - Systems and methods for converting fuel are provided wherein the system comprises at least reactors configured to conduct oxidation-reduction reactions. The first reactor comprises a plurality of ceramic composite particles, wherein the ceramic composite particles comprises at least one metal oxide disposed on a support. The first reactor is configured to reduce the least one metal oxide with a fuel to produce a reduced metal or a reduced metal oxide. The second reactor is configured to oxidize the reduced metal or reduced metal oxide to produce a metal oxide intermediate. The system may also comprise a third reactor configured to oxidize the metal oxide intermediate to regenerate the metal oxide of the ceramic composite particles.

SYSTEMS FOR PRODUCING SILICON TETRAFLUORIDE FROM FLUOROSILICATES IN A FLUIDIZED BED REACTOR - Systems for preparing silicon tetrafluoride by the thermal decomposition of an alkali or alkaline earth-metal fluorosilicate. The system includes a drying apparatus for removing moisture from a fluorosilicate feed; a fluidized bed reactor comprising a reaction chamber for thermal decomposition of fluorosilicate into silicon tetrafluoride gas and an alkali or alkaline earth-metal fluoride; a heater apparatus and an exhaust gas treatment system for treating gases discharged from the fluidized bed reactor.

06-17-2010

20100150808

PROCESSES FOR PRODUCING SILICON TETRAFLUORIDE FROM FLUOROSILICATES IN A FLUIDIZED BED REACTOR - Processes for preparing silicon tetrafluoride by the thermal decomposition of an alkali or alkaline earth-metal fluorosilicate in a fluidized bed reactor. A portion of silicon tetrafluoride that is generated in the decomposition reaction may be recycled to the reactor and used as a fluidizing gas to suspend the fluorosilicate material. Alkali or alkaline earth-metal fluoride residue generated in the decomposition reaction may be discharged from the reactor and reacted with fluorosilicic acid to produce an alkali or alkaline earth-metal fluorosilicate that may be introduced to the reactor for further generation of silicon tetrafluoride.

06-17-2010

20110101504

Methods of Grinding Semiconductor Wafers Having Improved Nanotopology - Methods for holding a workpiece with a hydrostatic pad are disclosed herein. The pad includes hydrostatic pockets formed in a face of the body directly opposed to the wafer. The pockets are adapted for receiving fluid through the body and into the pockets to provide a barrier between the body face and the workpiece while still applying pressure to hold the workpiece during grinding. The hydrostatic pads allow the wafer to rotate relative to the pads about their common axis. The pockets are oriented to reduce hydrostatic bending moments that are produced in the wafer when the grinding wheels shift or tilt relative to the hydrostatic pads, helping prevent nanotopology degradation of surfaces of the wafer commonly caused by shift and tilt of the grinding wheels.

05-05-2011

20110158882

Methods For Producing Silicon Tetrafluoride - Methods for producing silicon tetrafluoride by acid digestion of fluoride salts of alkali metal or alkaline earth metal and aluminum, optionally, in the presence of a source of silicon; methods for producing silane that include acid digestion of by-products of silane production to produce silicon tetrafluoride.

06-30-2011

20110158896

Methods For Producing Aluminum Trifluoride - Methods for producing aluminum trifluoride by acid digestion of fluoride salts of alkali metal or alkaline earth metal and aluminum, optionally, in the presence of a source of silicon; methods for producing silane that include acid digestion of by-products of silane production to produce aluminum trifluoride.

Trichlorosilane Vaporization System - A heat exchanger for vaporizing a liquid and a method of using the same are disclosed herein. The heat exchanger includes a housing, a tube, a heater, and a plurality of non-reactive members. The tube is disposed in the interior of the housing and has an inlet and an outlet. The heater is configured to heat the tube. The plurality of non-reactive members are disposed in an interior cavity of the tube in an arrangement such that a plurality of voids are defined between the members and the tube. The arrangement also permits liquid to pass through the voids and travel from the inlet of the tube to the outlet of tube. The plurality of non-reactive members and the tube transfer heat to the liquid as the liquid passes through the plurality of voids in order to vaporize the liquid.

12-08-2011

20120079847

PROCESSES FOR PURIFYING SILANE - Processes and systems for purifying silane-containing streams are disclosed with relatively less silane being lost in impurity streams by use of distillation and/or condensation operations.

04-05-2012

20120079848

SYSTEMS FOR PURIFYING SILANE - Processes and systems for purifying silane-containing streams are disclosed with relatively less silane being lost in impurity streams by use of distillation and/or condensation operations.

METHODS FOR PRODUCING SILANE - Methods and systems for producing silane that use electrolysis to regenerate reactive components therein are disclosed. The methods and systems may be substantially closed-loop with respect to halogen, an alkali or alkaline earth metal and/or hydrogen.

06-28-2012

20120164033

SYSTEMS FOR PRODUCING SILANE - Methods and systems for producing silane that use electrolysis to regenerate reactive components therein are disclosed. The methods and systems may be substantially closed-loop with respect to halogen, an alkali or alkaline earth metal and/or hydrogen.

SYSTEMS AND METHODS FOR PARTICLE SIZE DETERMINATION AND CONTROL IN A FLUIDIZED BED REACTOR - Systems and methods are provided for determining the size of particles within a fluidized bed reactor. The pressure of gas adjacent a gas inlet and adjacent a gas outlet of the reactor are measured with pressure sensors. An algorithm is applied to at least one of the pressure measurements to determine the size of particles within the reactor. The determined size of the particles can be used to control the operation of the reactor. A dosing system and method is provided for measuring defined volumes of particles for transport to the reactor.

METHODS FOR INTRODUCTING A FIRST GAS AND A SECEOND GAS INTO A REACTION CHAMBER - Gas distribution units of fluidized bed reactors are configured to direct thermally decomposable compounds to the center portion of the reactor and away from the reactor wall to prevent deposition of material on the reactor wall and process for producing polycrystalline silicon product in a reactor that reduce the amount of silicon which deposits on the reactor wall.

09-13-2012

20130004405

PROCESSES FOR PRODUCING SILANE IN A BUBBLE COLUMN - Methods for producing silane by reacting a hydride and a halosilane are disclosed. Some embodiments involve use of a column which is not mechanically agitated and in which reactants may be introduced in a counter-current arrangement. Some embodiments involve use of a baffled column which has multiple reaction zones.

01-03-2013

20130071310

PROCESS FOR REMOVING HYDROGEN SULFIDE FROM VERY SOUR HYDROCARBON GAS STREAMS USING METAL SULFIDE - A process for sweetening a gas stream containing hydrogen sulfide wherein said process comprises contacting said gas stream within a contacting zone a contacting composition comprising metal sulfide in a lower sulfided state and yielding from said contacting zone a product gas stream having a reduced hydrogen sulfide concentration and a recovered contacting composition comprising metal sulfide in a higher sulfided state.

03-21-2013

20130071314

PROCESS FOR PRODUCING HYDROGEN, SULFUR AND SULFUR DIOXIDE FROM HYDROGEN SULFIDE-CONTAINING GAS STREAMS - A process for making molecular hydrogen, elemental sulfur and sulfur dioxide from hydrogen sulfide. The process involves contacting a gas stream of hydrogen sulfide within a contacting zone with a contacting composition comprising metal sulfide in a lower sulfided state and yielding from the contacting zone a product gas stream comprising hydrogen and a recovered contacting composition comprising metal sulfide in a higher sulfided state. The higher metal sulfide is regenerated with oxygen to yield elemental sulfur and sulfur dioxide.

SYSTEMS FOR PRODUCING SILANE - Methods and systems for producing silane that use electrolysis to regenerate reactive components therein are disclosed. The methods and systems may be substantially closed-loop with respect to halogen, an alkali or alkaline earth metal and/or hydrogen.

05-16-2013

20130195432

TRICHLOROSILANE VAPORIZATION SYSTEM - A heat exchanger for vaporizing a liquid and a method of using the same are disclosed. The heat exchanger includes a housing, a tube, a heater, and a plurality of non-reactive members. The tube is disposed in the interior of the housing and has an inlet and an outlet. The heater is configured to heat the tube. The plurality of non-reactive members are disposed in an interior cavity of the tube in an arrangement such that a plurality of voids are defined between the members and the tube. The arrangement also permits liquid to pass through the voids and travel from the inlet of the tube to the outlet of tube. The plurality of non-reactive members and the tube transfer heat to the liquid as the liquid passes through the plurality of voids in order to vaporize the liquid.

SELENIUM-CONTAINING HYDROPROCESSING CATALYST, ITS USE, AND METHOD OF PREPARATION - A hydroprocessing catalyst composition that comprises a support material and a selenium component and which support material further includes at least one hydrogenation metal component. The hydroprocessing catalyst is prepared by incorporating a selenium component into a support particle and, after calcination thereof, incorporating at least one hydrogenation metal component into the selenium-containing support. The metal-incorporated, selenium-containing support is calcined to provide the hydroprocessing catalyst composition.

10-03-2013

20130284585

METHODS FOR PURIFYING HALOSILANE-CONTAINING STREAMS - Methods for purifying a halosilane-containing process stream are disclosed. In some embodiments, arsenic and phosphorous impurities are removed from halosilane-containing process streams by use of distillation.

10-31-2013

20140144082

Methods of Converting Fuel - A method for converting fuel may include reducing at least one metal oxide in a first reactor with a fuel to produce a reduced metal or a reduced metal oxide, transporting the reduced metal or reduced metal oxide from the first reactor to a second reactor, oxidizing at least a portion of the reduced metal or reduced metal oxide from the first reactor in the second reactor to produce a metal oxide intermediate, transporting the metal oxide intermediate from the second reactor to a third reactor, removing ash, char, or unwanted materials with a separation unit from the metal oxide intermediate transported from the second reactor to the third reactor, regenerating the at least one metal oxide, and transporting the regenerated metal oxide from the third reactor to the first reactor.

05-29-2014

20140328740

METHODS FOR PRODUCING SILANE - Methods and systems for producing silane that use electrolysis to regenerate reactive components therein are disclosed. The methods and systems may be substantially closed-loop with respect to halogen, an alkali or alkaline earth metal and/or hydrogen.

11-06-2014

Patent applications by Puneet Gupta, Houston, TX US

Puneet Gupta US

Patent application number

Description

Published

20100169846

METHODS FOR GATE-LENGTH BIASING USING ANNOTATION DATA - Methods for generating a biased layout for making an integrated circuit are disclosed. One such method includes obtaining a nominal layout defined by one or more cells, where each cell has one or more transistor gate features with a nominal gate length. Then, obtaining an annotated layout. The annotated layout contains information describing gate-length biasing of one or more of the transistor gate features in one or more cells of the nominal layout. A biased layout is produced by modifying the nominal layout using the information from the annotated layout. The biasing modifies a gate length of those transistor gate features identified by the information of the annotated layout.

07-01-2010

20100169847

STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING - A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

07-01-2010

20130014071

STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING - A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

01-10-2013

20130014072

STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING - A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

01-10-2013

20130014073

STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING - A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

01-10-2013

Puneet Gupta, La Jolla, CA US

Patent application number

Description

Published

20100023917

TOOL FOR MODIFYING MASK DESIGN LAYOUT - An embodiment of the invention provides a tool for modifying a mask design layout to be printed. The tool is executed by a computer system, and includes code for establishing a first level of correction for a mask design layout for a predetermined parametric yield without cost of correction to area of the mask design layout. The tool also includes code for correcting the mask design layout at said first level of correction based on a correction algorithm, the correction algorithm selecting a cell of the mask design layout having an edge placement error (EPE) for each gate feature in the cell. The correction algorithm selects the cell without loss to parametric yield as established by the predetermined parametric yield.

01-28-2010

Puneet Gupta, Sunnyvale, CA US

Patent application number

Description

Published

20090010171

Scaling BFD sessions for neighbors using physical / sub-interface relationships - In one embodiment, an apparatus includes a physical port and a plurality of logical sub-interfaces under the physical port. The physical port and the logical sub-interfaces are configured as a Bidirectional Forwarding Detection (BFD) neighbor group. The physical port being configured to run BFD sessions to detect failures at a first rate that is substantially faster as compared to a second rate of BFD sessions to detect failures on the logical sub-interfaces. The physical port notifies the logical sub-interfaces of a BFD failure at the physical port, with the logical sub-interfaces shutting down responsive to the notification. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure.

01-08-2009

20090323520

Bidirectional Forwarding Detection on Multilink Bundled Interfaces - Disclosed are, inter alia, methods, apparatus, computer-storage media, mechanisms, and means associated with Bidirectional Forwarding Detection (BFD) on multilink bundled interfaces. A packet switching device communicates with another packet switching device through a multilink bundled interface configured for communicating over a plurality of bundled communication links. A separate BFD session is conducted over each link of the multiple bundled communication links, and in response to a BFD-detected failure condition, the use of the one or more links or the entire bundled interface is removed from service.

Puneet Gupta, Saint Peters, MO US

Patent application number

Description

Published

20090136398

Optimized Liquid-Phase Oxidation - Disclosed is an optimized process and apparatus for more efficiently and economically carrying out the liquid-phase oxidation of an oxidizable compound. Such liquid-phase oxidation is carried out in a bubble column reactor that provides for a highly efficient reaction at relatively low temperatures. When the oxidized compound is para-xylene and the product from the oxidation reaction is crude terephthalic acid (CTA), such CTA product can be purified and separated by more economical techniques than could be employed if the CTA were formed by a conventional high-temperature oxidation process.

05-28-2009

20110256037

OPTIMIZED LIQUID-PHASE OXIDATION - Disclosed is an optimized process and apparatus for more efficiently and economically carrying out the liquid-phase oxidation of an oxidizable compound. Such liquid-phase oxidation is carried out in a bubble column reactor that provides for a highly efficient reaction at relatively low temperatures. When the oxidized compound is para-xylene and the product from the oxidation reaction is crude terephthalic acid (CTA), such CTA product can be purified and separated by more economical techniques than could be employed if the CTA were formed by a conventional high-temperature oxidation process.

10-20-2011

Patent applications by Puneet Gupta, Saint Peters, MO US

Puneet Gupta, San Jose, CA US

Patent application number

Description

Published

20130021107

VIA RESISTANCE ANALYSIS SYSTEMS AND METHODS - Component characteristics analysis systems and methods are described. In one embodiment, a ring oscillator comprises: at least one inversion stage operable to cause a signal transition; a target component that has an increased comparative impact or influence on a signal transition propagation in the ring oscillator; and an output component for outputting an indication of the impact the target component has on the signal transition. The target component can include a plurality of vias from one metal layer to another metal layer. The plurality of vias from one metal layer to another metal layer can be configured in a cell. The vias can correspond to a via layer. In one exemplary implementation, the output is coupled to an analysis component. The analysis component can include correlation of the via resistance into a wafer variations and generate a wafer map. The analysis component can include correlation of the via resistance into a wafer.

01-24-2013

20130027140

COUPLING RESISTANCE AND CAPACITANCE ANALYSIS SYSTEMS AND METHODS - The described systems and methods can facilitate examination of device parameters including analysis of relatively dominant characteristic impacts on delays. In one embodiment, at least some coupling components (e.g., metal layer wires, traces, lines, etc.) have a relatively dominate impact on delays and the delay is in part a function of both capacitance and resistance of the coupling component. In one embodiment, a system comprises a plurality of dominate characteristic oscillating rings, wherein each respective one of the plurality of dominate characteristic oscillating rings includes a respective dominate characteristic. Additional analysis can be performed correlating the dominate characteristic delay impact results with device fabrication and operation.

01-31-2013

Puneet Gupta, Uttar Pradesh IN

Patent application number

Description

Published

20130091352

Techniques to Classify Virtual Private Network Traffic Based on Identity - Techniques are provided for obtaining first and second digital certificates from a certificate authority database for establishing a secure exchange between network devices. The first digital certificate contains identity information of a first network device, and the second digital certificate contains classification information of the first network device. In one embodiment, a secure key exchange is initiated with the second network device, and the first and second digital certificates are transmitted as a part of the secure key exchange to the second network device. In another embodiment, the first and second digital certificates are received by an intermediate network device. The first digital certificate is encrypted and is not evaluated by the intermediate network device. The second digital certificate is evaluated for classification information of the first network device. Source information associated with the first network device is stored, and encrypted traffic is processed between the network devices.

04-11-2013

Puneet Gupta, Los Angeles, CA US

Patent application number

Description

Published

20130254734

Standard Cells having transistors annotated for gate-length biasing - A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

09-26-2013

Puneet Gupta, Elk Grove Village, IL US

Patent application number

Description

Published

20130287217

NOISE HANDLING DURING AUDIO AND VIDEO RECORDING - The disclosure is directed to techniques for noise handling in audio or video recording. Sounds that may be generated during the audio recording, such as by activation of switches, may appear as undesired artifacts in the recording. Techniques and apparatus are described whereby, when an undesired sound is generated, an inverse of the sound is applied to the sound, thereby canceling the unwanted sound from the recording. Further, the techniques can be adapted to many kinds of portable electronic devices having many kinds of switches and many kinds of undesirable sounds.

10-31-2013

20140063067

METHOD TO SELECT WORD BY SWIPING CAPACITIVE KEYBOARD - A method for an electronic device having a keyboard and a display, including, receiving an input reflecting selection of one or more of the keys, displaying, at a location on the display, one or more characters associated with the one or more selected keys, wherein the location corresponds to a region of the keyboard determined based on a subsequent candidate input character that is based on the one or more characters associated with the one or more selected keys, and detecting a swipe input associated with the determined region. An electronic device including a display, a keyboard, a memory, and a processor, the processor being configured to execute the method. The keyboard also includes a plurality of keys, each key corresponding to one or more different characters of a plurality of characters, and a plurality of sensors configured to detect one or more gestures along the plurality of keys.

03-06-2014

Puneet Gupta, Singapore SG

Patent application number

Description

Published

20130136686

METHODS FOR PRODUCING ALUMINUM TRIFLUORIDE - Methods for producing aluminum trifluoride by acid digestion of fluoride salts of alkali metal or alkaline earth metal and aluminum, optionally, in the presence of a source of silicon; methods for producing silane that include acid digestion of by-products of silane production to produce aluminum trifluoride.

05-30-2013

Puneet Gupta, Marina Del Rey, CA US

Patent application number

Description

Published

20140223404

Gate-Length Biasing for Digital Circuit Optimization - Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology that changes a nominal gate-length of a transistor to a biased gate-length, where the biased gate-length includes a bias length that is small compared to the nominal gate-length.

08-07-2014

20140245245

STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING - Methods, layouts and chip design layouts that use annotations for communicating gate-length biasing amounts to post-layout tools are disclosed. One method includes receiving a chip design layout designed to includes select ones of a plurality of nominal cell layouts and an annotated cell layout. The chip design layout is defined by a plurality of layers and the plurality of nominal cell layouts define transistors, wherein each of the plurality of nominal cell layouts define nominal length transistors, and the annotated cell layout also defines transistors. The annotated cell layout is associated with an annotation layer that identifies a gate-length biasing to be applied to at least one transistor of the annotated cell layout. The gate-length biasing identifies an amount of change for a gate length and not width-sizing of a gate width of the at least one transistor of the annotated cell layout. The annotation layer is used to communicate design-specific directives that require implementation. The method uses a processor to process the chip design layout, with reference to the annotation layer, to apply the gate-length biasing to the annotated cell of the chip design layout.

08-28-2014

Puneet Gupta, Simi Valley, CA US

Patent application number

Description

Published

20140262392

MACHINE TOOL WITH VIBRATION DETECTION - A method of detecting machine tool vibration is provided. The method includes receiving, from a sensor arranged in a machine tool, motion data measured along an axis. The method also includes comparing the motion data against a first threshold. The method also includes adjusting a counter if the motion data has a magnitude greater than the first threshold. The method also includes generating an alarm if the counter is greater than a second threshold.

09-18-2014

Puneet Gupta, Mountain View, CA US

Patent application number

Description

Published

20140365296

CROSS-DEVICE CONVERSION ESTIMATES - Systems and methods for cross-device conversion estimates determine an observed number of cross-device conversions based on different sets of devices being logged into the same online accounts. The observed cross-device conversions are extrapolated out based on a percentage of one set of devices having logged into the same accounts as the second set of devices.

12-11-2014

Puneet Gupta, Meerut IN

Patent application number

Description

Published

20150067337

Techniques to Classify Virtual Private Network Traffic Based on Identity - Techniques are provided for obtaining first and second digital certificates from a certificate authority database for establishing a secure exchange between network devices. The first digital certificate contains identity information of a first network device, and the second digital certificate contains classification information of the first network device. In one embodiment, a secure key exchange is initiated with the second network device, and the first and second digital certificates are transmitted as a part of the secure key exchange to the second network device. In another embodiment, the first and second digital certificates are received by an intermediate network device. The first digital certificate is encrypted and is not evaluated by the intermediate network device. The second digital certificate is evaluated for classification information of the first network device. Source information associated with the first network device is stored, and encrypted traffic is processed between the network devices.