H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials

H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices

H01L29/66234—Bipolar junction transistors [BJT]

H01L29/66272—Silicon vertical transistors

H—ELECTRICITY

H01—BASIC ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched

H01L29/70—Bipolar devices

H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals

H01L29/73—Bipolar junction transistors

H01L29/732—Vertical transistors

H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor

Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS

Das bekannte Verfahren hat den Nachteil, daß die Stromverstärkungswerte der Transistoren, welche bekanntlich in der Mehrzahl in einer in die Festkörperschaltung zu zerteilende Halbleiterplatte hergestellt werden, von Platte zu Platte Schwankungen unterworfen sind. The known method has the disadvantage that the current gain of the transistors, which are known to be produced in the majority in the solid state circuitry to Separating semiconductor plate, plate to plate fluctuate.

Das Verfahren nach der Erfindung und ihre Vorteile wird im folgenden an Ausführungsbeispielen erklärt, welche anhand der Zeichnung erläutert werden, The method of the invention and its advantages will be explained below using exemplary embodiments which are explained with reference to the drawing,

deren Fig. 9 bis 14 zur Erläuterung eines zweiten Ausführungsbeispiels nach der Erfindung herangezogen werden und the Fig. 9 to 14 are used for explanation of a second embodiment according to the invention, and

deren Fig. 15 in gleicher Teilschnittdarstellung einen monolithisch integrierten Planartransistor zeigt, der entsprechend einer Weiterbildung des Verfahrens nach der Erfindung dargestellt wurde. in the same partial sectional view showing a monolithic integrated planar transistor whose FIG. 15, which was prepared according to a further development of the method according to the invention.

Es erfolgen nun in beliebiger Reihenfolge die beiden Implantationsprozesse unterschiedlicher Beschleunigungsenergie und Dosis von Ionen des Leitungstyps der Basiszone, wie in der Fig. 12 durch die gestrichelten Linien angedeutet worden ist. It now take place in any order, the two implantation processes of different acceleration energy and dose of ions of the conductivity type of the base zone, has been suggested as shown in Fig. 12 by the dotted lines.

Method for forming very narrow doping regions in a semiconductor body and use of this method for producing semiconductor regions insulated from each other, bipolar semiconductor devices, integrated injection logics and double-diffused FET semiconductor devices