Intel tips Moorestown details, talks up x86 smartphones

At the recent Hot Chips conference, Intel revealed more details of its …

At Hot Chips this past week, Intel's Rajesh Patel revealed more details of the chipmaker's upcoming Moorestown platform. Patel, who is the lead architect of the platform's system-on-a-chip (SoC) part, also made it clear that he really does believe that Moorestown is a bona fide "smartphone" platform that will give us the world's first x86-based phones. I wasn't actually at the presentation, so I didn't get close enough to Patel to tell if there was any crack smoke on his breath as he made this smartphone claim, but I did get hold of the materials, so let's take a look.

Intel still isn't giving any real power draw information on Moorestown, other than to say that the platform has reduced Menlow's 1.6W idle power draw by 50 times. There's not a word said on how much it has reduced Menlow's peak power draw, so my guess is that the answer is "not much." This being the case, it's safe to assume that Moorestown's peak power draw is still well above (possibly by an order of magnitude) a comparable high-end ARM-based solution, but Intel plans to make up for this with a combination of very low idle power and a whole ton of spatial and temporal granularity in frequency scaling.

The result will be a part aimed at what Intel calls "high-end smartphones" (think the new Nokia 900, for example), with very good performance-per-watt for low-intensity smartphone workloads. But what will probably keep this hyperthreaded, x86-based beast of a "smartphone" platform out of any real smartphones is the fact that it has way more absolute performance than anyone needs on a phone right now. Intel will be asking users to pay for that performance with worse battery life than a comparable (probably single-chip) ARM-based solution, when in the end the ARM part is perfectly adequate for 99 percent of what people do on a smartphone, i.e., casual gaming, media playback, Web surfing, messaging, social networking, etc. I think almost everyone is going to pick the battery life over the performance.

Moorestown will be a better mobile gaming platform than anything from ARM, though, so if someone makes a gaming handheld out of it that won't be a bad thing. It's also the case that the platform may have a great future in point-of-sale terminals and other verticals where x86 compatibility is actually an advantage.

Ultimately, though, I expect that in late 2010 I'll be writing an article about the channel availability of Moorestown-based smartphones that reads a lot like the one I did on Menlow-based MIDs. The real x86 smartphone action is going to happen at the 32nm process node, with Medfield, Moorestown's successor. But that's a topic for another day.

Power gating and dynamic frequency scaling

Moorestown's massive reduction in idle power draw is accomplished using the same basic technology, power gating, that Intel used to reduce Nehalem's idle power. Power gating lets Intel address the problem of leakage current, which I've gone into some detail on in a previous post. And, also like Nehalem, Intel has divide up the Lincroft SoC into different power and clock regions that can be downclocked or turned off independently of one another.

Also included is an increased number of clockspeed levels at which parts of the Lincroft SoC can operate. The idea here, as in all dynamic power optimization schemes, is to dynamically scale frequencies to match the workload. By adding more granular frequency scaling options for Lincroft's different functional blocks, the part can more closely fit its performance profile to a workload's needs within a given timeslice.

The main problem with doing this kind of dynamic frequency scaling aggressively in normal server or desktop computing applications is that there's always some latency involved in these power state transitions, and that latency saps performance. (In other words, all of the frequency scaling potential in the world is no good if the chip takes too long to react to and adapt to real-time changes in a workload.) But my guess is that this latency/performance issue is less critical in mobile applications for a variety of reasons (limited multitasking, relatively simple applications, low OS overhead, etc.), so Intel can just go nuts with the number of power states.

Intel has also extended this dynamic frequency scaling to Moorestown's memory bus, so that the platform can scale memory latency and bandwidth (and bus power draw) to match the current workload.

Moorestown also implements hyperthreading to boost performance-per-watt, but I really can't see this doing anything for a smartphone. This is a feature that will help Moorestown in netbooks, if the platform finds a use in that vertical.