Status

The core was tested with several ASM and C programs.
It was implemented in Altera EPF10K50ETC144-3 device and
tested with AVR port of uC/OS-II The Real-Time Kernel, written by Ole Saether.(I used special version of the design with external SRAM for both program and data memories).
Update 22.12.12. Verilog version of the project is uploaded.