sberg@camtronics.com writes:> Is it possible to create a computer where the HLL gets compiled into> processor microcode, fully optimized, with some amazing increase in> speed?

Not only is it possibly, but (excuse me while I blow the dust off of
my resume) we did that on the Culler-7 back in 1985, at Culler
Scientific Systems (I'm pretty sure that we were the first VLIW to be
built for commercial purposes, too.)

Our optimizing compiler first fit the algorithm to the pipeline using
the rather extensive macroinstruction set, which included support for
pipelined ops etc; then if certain flags were set it would also
attempt to better fit the algorithm to the hardware, and when
reasonable it would create "custom" instructions for the inner loops,
which were loaded into the microstore as part of the process state.
The standard instruction set was usually sufficient, but there were
times that this was worth the effort.

Being a hardware weenie I can't supply any more details than
that, but I suspect that one of the members of Culler's vast
compiler department reads this group and can fill in more
details. At least 2 of the 4 are here at SGI now...