Memory 101: What you need to know about FRAM, part 2

In part two of this article, the author discusses the specifics of the read and write process with a particular focus on the requirements placed on the ferroelectric capacitor. Part one discusses the basic operating principles of FRAM, including the role played by hysteresis.

At the end of the read operation, the capacitor always points UP so if the datum indicated a DOWN state, it must be re-written (see figure 4).[1,2] The fundamental FRAM cell looks very much like a DRAM cell with the addition of an extra line. Unlike DRAM capacitors, which see a monopolar bias voltage on their substrate contact, memory circuits must be able to apply bipolar voltages to that side of a ferroelectric capacitor. Therefore, the local substrate contact of the DRAM capacitor is replaced by a plate line and wife connecting the bottom side of the ferroelectric capacitor to a separate driver circuit.

Figure 4: UP and DOWN bit line voltages during the read operation.

The plate line drives all of the ferroelectric capacitors in a single row in the word-parallel cell (see figure 5). The capacitive loading on the plate line can be reduced to a single memory cell using the bit-parallel approach. Given the layout and knowing the amount of charge the capacitor will generate, experienced memory circuit designers can proceed apace. Nevertheless, ferroelectric capacitors do have special properties that must be considered in the design.

Figure 5: The plate line in an FRAM may be run parallel either to the word line or the bit line.

ChargeThe ferroelectric capacitor will generate four to five times more charge than a DRAM capacitor during the read operation. Typically, a DRAM capacitor has a capacitance of approximately 20 fF and a voltage of ±˝ Vcc across it, yielding at most approximately 30 fC stored in a cell of 0.01 to 0.02 µm2. A typical ferroelectric capacitor in a commercial FRAM has an area of approximately 0.4 µm2 but delivers 32 µC/cm2 of polarization onto the bit line, equivalent to 128 fC of charge. The memory circuit must be able to support the movement of that much charge in the nanoseconds allotted for establishing the bit line sense voltage before the sense amplifier is enabled. The fundamental difference is that where a DRAM capacitor naturally shares its charge with the bit line when its pass gate is enabled, the charge inside the ferroelectric capacitor must be forced from the capacitor by the application of an external voltage from the plate line. The impedance of the drive and sense circuitry becomes the critical limitation, slowing memory cell operation below the maximum speed of the ferroelectric capacitor. Paul Larsen of the Philips Research Laboratory demonstrated in 1992 that PZT could switch as fast as 360 ps.[3] PZT in reality is probably faster.