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014_output_window : Output Window

Minimum Required Versions: SILOS 4.12.1.C

Example 014_output_window circuit is a one bit adder implemented as a Verilog gate level design. The
schematic
consisting of gate level primitives and the Verilog
netlist generated by Gateway are shown. The testbench source
file contains Verilog behavioral code to generate the input test pattern.
The SILOS graphical user interface includes the Output window which displays messages from the SILOS as well as output generated by Verilog source code statements (i.e. $display).

Verilog Code Messages

Simulate the project
"1bit_adder.spjx"
and observe that some text in the output window is displayed in
blue
. These text lines act as hypertext links to the source file line that wrote the text to the output window. Putting the mouse cursor on one of these links will display a
data tip
window with simulation time, source file and line number where the message was generated. Double clicking on a link will open a source edit window showing the
source file
and highlight the source line.

SILOS Error Messages

Run the project
"1bit_adder_err.spjx"
and observe the error message in output
window
. SILOS error messages are also written to the output window and are displayed as hypertext links if the message is related to a specific source file line. Double clicking on the link will open a file edit
window
and display the line that caused the error message.