AD9656EBZ problem

I've a problem when using the AD9656 Evaluation board AD9656EBZ, I cann't get any correct data from the board.

I found the register 0x0A has a wrong value 0x0, which should have the right value of 0x81.Bit 7 of this reg shows the status of PLL:0=PLL is not locked.Bit 0 shows the status of JTX link:0=Link not ready.

You mention using the Xilinx KC705 board to configure the AD9656. You are also using this board to capture the data, correct?

Before yesterday you mention that everything was working well. It was working well with the KC705, correct? Did the board stop working while it was running, or did it not come up after a power down? Did you make any change to the AD9656 configuration that coincided with the faulty behavior?

I talked to the designer and he said he never observed an issue with PLL lock, so I have no special PLL lock "tricks" to try.

You mention getting wrong data from the bad board. Does this mean that the bad board is producing data, but it is not the data you expect? Are the output drivers driving/toggling?

The contents of Register 0x0A are different between the good and bad board. Does your system have a way of doing a register dump to get the contents many registers (0x00 through 0x10A)? If so, could you get a dump of the register contents of the good and bad boards, and compare them?

How are you getting the power to the ADC board? Is it through the power connector on the side of the ADC board, or through the FMC connector?

Do you have a way of measuring the power supply current to the board, or to the ADC? If so, are these currents quite different between the good and bad boards?

Yes, my project is for academic purposes. I‘m using the Data acquisition system which consist of AD9656EBZ and FPGA evaluation boards to readout analog signals.We are doing the preliminary research for detector readout in CERN/ALICE-PHOS. My CERN account is wfeng@cern.ch.

We have preheater,working stand and soldering station to desolder and re-install the chip.