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Description

fixes two problems. First, ngd2vhdl was incorrectly shorting nets togetherif an array was referencing another array. This typically happened if acustomer was using the Exemplar synthesis toolset. Other synthesis toolshave been observed not to have this problem, since they write out arraysin a different fashion.

Second, the user must now specify a pulse width for the ROC cell. The ROCcell simulates the GSR/GR pusle of an FPGA during simulation. The defaultpulse width in 1.4 is 0 ns, which causes VHDL simulators to not simulate.Now, the user must specify the ROC width, using the -rpw option.

解决方案

1

If you have downloaded the latest ngd2vhdl patch, and are now getting theerror:

ERROR:basvh - A Reset-On-Configuration component is instantiated but no pulse width is specified for it. In order to simulate ROC properly, the pulse width for ROC must be specified with the command-line option -rpw.

This means that you must specify a non-zero pulse width for the ROC.

ngd2vhdl -rpw 10 design.nga

would create a 10 ns pulse width to simulate GR/GSR. This is a new featureadded to ngd2vhdl. This allows a user to change the GR/GSR width withoutediting the VHDL file, and/or using a VHDL configuration.

2

If you are using the Exemplar tool set for VHDL synthesis, and the VHDLcode you have processed uses a 1-dimensional array to reference another1-dimensional array, there will be a problem when simulating the designwith a .vhd file produced by ngd2vhdl. There are two solutions. The firstsolution is to use a 2-dimensional array, instead of a 1-dimensionalarray referencing another 1-dimensional array. The second solution isto download the latest ngd2vhdl patch: