Inside Advanced Packaging

Semiconductor Engineering sat down to discuss advanced IC-packaging, the OSAT industry, China and other topics with Ron Huemoeller, vice president of worldwide R&D at Amkor. What follows are excerpts of that conversation.

SE: Where are we in advanced IC-packaging today?

Huemoeller: We’ve hit the inflection point. Now we are coming to the other side of it. Regarding this need to integrate more die content per package, it’s real. This is coming from a couple of areas. One, you have the processor guys driving it. They are driving toward memory integration. But then you also have the mobile guys, who are using advanced lithography and leading-edge silicon. They are also bringing memory into it, as well as better performance. So you need a lot of different things all in the same package at the right cost point.

SE: In advanced packaging, there are several options. You have flip-chip, fan-outs and 2.5D/3D stacked die using through-silicon vias (TSVs). There is a widespread perception that 2016 will be the year for 2.5D. Is the industry finally adopting 2.5D?

Huemoeller: This is going to be propelled by some launches this year. You’ve got companies like AMD and Nvidia. They have multiple products behind that. It’s not just one. With those guys using it, and the supply chain maturing on those platforms, the cost will keep coming down. In addition, you have other guys designing it. Anybody in high-end networking is using it.

SE: Is 2.5D stack die moving into the mobile market?

Huemoeller: That’s been the problem with TSVs. The TSV hasn’t hit the cost point for mobile—yet. But these newer advanced fan-out technologies can. They might be a little at the upper end, but they are close enough that people will design into it. This is because they can get a package performance benefit.

SE: Let’s talk about fan-out. Not all fan-outs are alike. In simple terms, can you please describe the main difference between chip first and chip last in fan-out on traditional 300mm wafers?

Huemoeller: Chip first is a process whereby the die is attached to a temporary or permanent material structure prior to creating the RDL (redistribution layer), which will extend from the die to the BGA/LGA (ball grid array/land grid array) interface. In this manner, the yield loss associated with creating the RDL occurs after the die is mounted, subjecting the die to potential loss. The reverse is true for a chip last process. The RDL is created first and the die is then mounted. In this flow, the RDL structures can be either electrically tested or visually inspected for yield loss, thereby avoiding placing good die on bad sites. For low I/O die, where RDL is minimal and yields are very high, a die first flow is preferred. However, for high value die, a die last process is preferred.

Huemoeller: First, there is traditional fan-out like eWLP (embedded wafer level package). That market is still a niche. It’s still not a big market. This is for some RFICs and codecs. The bigger chunk, which is addressing processors for mobile, is advanced fan-out. It’s a limited field right now. There are only a few people looking at it.

SE: Are the major mobile OEMs rushing to use advanced fan-out?

Huemoeller: Advanced fan-out is not something that everyone will adopt out of the gate. It will take some more cost reduction. But it’s already happening for high-end phones from some OEMs. The next tier of players will start using these types of technologies once the cost curve kicks in. Then, you’ll see a bigger deployment.

SE: What’s holding the second-tier OEMs back in terms of using fan-out?

Huemoeller: They all want it, but they don’t want to pay for it yet. That’s where the cost curve comes in. Some guys will pay for it now. The other guys, which are the fast followers, won’t. So you have to bring the cost curve down. Then, they will pay more, but not a lot more.

SE: So for some OEMs, cost is still an issue for advanced fan-out. What are some of the other issues?

Huemoeller: It’s more processing.

SE: Today, advanced wafer-level packaging and fan-out is being done on 300mm round wafers. The industry is talking about moving towards a panel format, which will put more die on the substrate. In theory, this will reduce cost. Any thoughts?

Huemoeller: It’s a wafer-level process versus a substrate process. You are trading one for another. If you can get to a panel format, it will be lower cost because of the efficiencies. You will get more utilization off the line. It’s also problematic. You are trying to do complicated things on a large area. The reason why people are doing it on round wafers today is because of the equipment. Today’s equipment is set up to do wafer-level processing with high yields. It’s a different matter with panels. For example, you don’t see CMP for panels. It’s too expensive.

SE: Is Amkor working on it?

Huemoeller: We’ve been looking at the panel area for a lot of years. We are still looking at it. We have not given up on it. We are still working with suppliers on it. It’s a big challenge. You need different material sets. You run into all kinds of topology issues. You are talking about 2 micron line/space. For this, you must have a wafer-level surface to get good yields on that. You may have to go to CMP. And pretty soon, the cost is the same thing as having to go to a wafer. The substrate guys are trying to do it, but the cost is a lot higher. They are not there yet.

SE: What about doing chip first versus chip last on a panel format for advanced fan-out?

Huemoeller: Both processes can be performed on both panels and wafers. Chip last is the common flow for panel processing as panels are typically thicker and have carriers or core materials to provide structural reinforcement. However, panel technologies are limited in RDL to whichever stepping and plating technologies align to the equipment sets. In the case of panels, this is typically >10 micron line/space. On wafers, you can drive the RDL down to

Huemoeller: Swift is more mobile centric. Slim is more of a processor/HBM-centric. So, the market is bifurcated. Everything mobile-related is advanced or traditional fan-out. And then you have the high-end market, which is either advanced flip-chip, TSV 2.5D, or eventually Slim.

Huemoeller: Package-on-package will continue. This is just a different form of it.

SE: What else is hot besides fan-out and 2.5D?

Huemoeller: RF packages are growing faster than this sector. It is growing like crazy. Part of it is the IoT. Part of it is mobile and other things. RF is more like traditional packaging with good shielding techniques.

SE: Let’s move to the business side. According to Gartner, there are a total of 150 outsourced semiconductor assembly and test (OSAT) vendors in the market today. Some OSATs are large. Most are small. We are beginning to see some merger and acquisition activity in the arena. Are we finally seeing the long-awaited consolidation in the OSAT market?

Huemoeller: There has always been a little bit of that. Now, you are seeing bigger steps towards that consolidation. That is needed. Actually, it’s long overdue and healthy for the industry. It’s not unexpected.

SE: Why is it needed?

Huemoeller: There is quite a bit of investment required in the OSAT industry. In the market today, there are OSATs that cannot continue to invest. They are going to fall off. This leaves the OSATs that are left to sustain their businesses. They need to keep enough margin to allow them to maintain their investments. If there are too many people in the market, and there continues to be enough price pressure, you lose the option to reinvest. So, your ability to reinvest is diminished.

SE: Right now, there are approximately 10 to 15 mid- to large-sized OSATs. Is there enough room for all of these vendors?

Huemoeller: You need more than one vendor in the market. You need multiple vendors to keep it fair and level. But if there are too many vendors in the market, it’s not sustainable.

SE: So in advanced packaging, OSATs requires a certain scale to compete, right?

Huemoeller: Absolutely. It’s not even just in advanced packages. It’s even in what we call mainstream packaging. It includes things like copper wire. To continue to invest in the latest copper wirebonders, it’s still millions of dollars. So just to stay relevant in packaging you have to invest hundreds of millions of dollars. Most people can’t do that. But if you don’t do it, your technology becomes stale, you can’t compete, and you are not providing what the customers want.

SE: Is there room for the niche OSAT players?

Huemoeller: There is always room for the niche players. For example, there are OSATs that sit in the middle. These are guys with sales in the $600 million to $700 million range. They may survive as long as they provide good service for traditional mainstream products. Still others will work strictly on the lowest end of the cost curve and with fully depreciated equipment. That’s also a place where some might survive.

SE: What about TSMC’s moves into the packaging business?

Huemoeller: Even though they are investing in packaging, this is one way they can sell silicon. They are still a foundry.

SE: China is making a number of moves to expand into the chip-packaging market. For example, JCET recently bought STATS ChipPAC. In addition, China’s Tsinghua Unigroup has taken separate stakes in two Taiwan OSATs—ChipMOS and Powertech. Any thoughts?

Huemoeller: China wants to compete in semiconductors on the big stage. The fast way is to buy companies that know how to do that. They buy them and then they have the packaging expertise. It’s the fast path.