HyperThreading dropped

It also said that the part will not support HyperThreading, a key feature of the most recent generations of the Pentium 4.

Instead, HT will be used to differentiate the dual-core Pentium Extreme Edition - note that '4' is being dropped here, too - from the D. Both D and EE varieties will operate across an 800MHz frontside bus operating through an LGA775 socket.

Intel today spoke of the EE as a "four-thread" processor and the D as a "two-thread" chip.

The 1066MHz FSB found on the latest P4EE, the 3.73GHz model launch last week, will not be a feature of initial dual-core products. But Intel claimed the dual-core model will run 50-65 per cent faster, despite the lower clock speed.

D and EE chips will be fabbed at 90nm and represent single-die products, Intel digital enterprise group VP Stephen Smith said today. The chip maker has always avoided discussing this until now, leading some - including us - to assume that Smithfield might simply be a pair of Prescott processors packaged together.

Not so. In fact, it is the 65nm 'Presler', the next-generation desktop dualies, that is based on two separate dies bonded together in a single package and sharing a single frontside bus, Smith said.

The reason for this centres on manufacturing. A single wafer can be used as the basis for single-core 65nm desktop chips - aka 'Cedar Mill' - and/or Preslers, according to need. Intel can take two cores and ship them as two Cedar Mills or one Presler.

And since the 65nm Pentium M, 'Yonah', will also be available in single-core form, it's a good bet that it too will be a 'two chips, one package' processor.

Presler is officially due to ship H1 2006, as is Cedar Mill, but Smith let slip what recently leaked internal roadmaps have already shown - that Presler will ship in Q1 next year. The two chips will ship with 2MB and 4MB of L2 cache (2MB per core), respectively.

The Pentiums D and EE will launch next quarter, the latter as the 3.2GHz 840. It comprises 230m transistors - as will the D. HT is disabled rather than missing altogether in the lesser processor. Both support the 64-bit addressing EM64T system and the Execute Disable Bit. The chips measure 206mm² ®