if you put a C acrosss the feedback R giving a single pole low pass then there is little need for excessive slew rate - can be part of the anti-image/reconstruction filter

ideally higher frequency error V at the op amp input would then be reduced by ~ fc/GBW

with the feedback C there is a "feedthrough zero" that gives a small input Vdiff glitch at current steps due to the op amp output Z - decades old I/V app notes described the advantages of a low impedance output buffer inside the loop for op amp I/V

the op amp slew rate spec can still be a proxy for input diff pair linear operating range with degeneration, fet inputs improving both

but the low Vnoise parts can't have much degen

a compleltely new "highly linear" diff pair is used in AD8099/ADA4898 family parts - I think the ADA4898 is the best combination of specs for audio DAC I/V available today

you would need to look with a very good 'scope to see if ccs bias of the output to either rail helps - the ADA4898 has a 50 mA "linear current range" spec so you could bias at several times the fs current of most audio DAC chips

Let me place the question in a different way. Among the listed parameters, which are the most relevant?

I need to choose a pair of dual op-amps for I/V convertion but they must be electrically compatible with NE5532. I searched about this subject but all recommendations where based mostly on subjective tastes. I would like to get a technical explanation about the matter.

I show a sim of glitch at the input of the I/V op amp - Hawksford shows that you should want to minimize a function like the V^2 time integrated error V

GBW is the biggest help, low output Z as I mentioned makes the feedback C work better

the function to be integrated also depends on the linearity of the input stage - the ADA4898 uses a new linearized BJT input stage that is unmatched by previous monolithic op amp tech
if I've done the calc form the patent correctly the input stage gm is linear to -120 dB with |4 mV| input differential - the same number for a low noise bjt op amp is ~100 uV

I am planning to use them as I/V stage after a PCM61P - it has a settling time of 350ns. I am planning to get rid of the SR limiting capacitors in the I/V stage.
I just need to wait to get the adaptors from SMD to DIL.