Once the industry goes from its current 64-billion-bit flash chip to a 256-billion-bit chip (that’s 32 gigabytes), it will hit that brick wall of too few electrons per cell.

Mr. Harari said, the company has been able to build chips with four or eight layers. That’s the good news. The bad news is that they can write information to those chips only one time. That might be all right for distributing software or video games, but most flash memory is sold for use in devices like cameras, which need memory that can be erased and rewritten.

The chips are too power hungry. And so the computer industry is at a bit of a crossroad. And that's why GPU computing, this technology that we invented, has captured the imagination of the whole industry. Microsoft, with Windows7, is going to include Direct X computing, which is basically GPU computing. Apple computer, with the Snow Leopard operating system, is going to have Open CL, which is their version of GPU computing for their operating system. So all of a sudden the two most important operating systems in the world will include GPU computing or [use] the GPU's parallel computing technology core into it.

Here we [Nvidia] are with our technology called Cuda [a C-based architecture for coding in GPU] and GPU computing. And all of a sudden the speed-up is 50 times, 100 times, 200 times. And people are just astonished by the speed-ups. By the end of 2010, you're going to see GPU computing in the vast majority of the world's personal computers.

"We doubled down on manufacturing," Maloney says. "People said, 'You're insane!' " But Intel's entire competitive advantage--its ability to keep pace with Moore's Law and even exceed it--is in its manufacturing processes.

The new Nehalem EP chip is expected to allow one server to replace nine existing ones and pay for itself in just eight months. "Our job," Maloney says, "is to give them something so wonderful that they'll spend money again."

A key problem with copper interconnects is that at nanoscale-dimensions conductance is affected by scattering at the grain boundaries and sidewalls, Murali explained. "These add up to increased resistivity, which nearly doubles as the interconnect sizes shrink to 30nm." At the ~20nm scale the increased resistance would offset performance increases and negates gains made in higher density -- a roadblock to performance increases, if not to actual scaling.

The conductivity of graphene strips is found to be limited by impurity scattering as well as line-edge roughness scattering; as a result, the best reported GNR resistivity is three times the limit imposed by substrate phonon scattering. This letter reveals that even moderate-quality graphene nanowires have the potential to outperform copper for use as on-chip interconnects.