You should complete the VLSI CAD Part I: Logic course before beginning this course.
A modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks). How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus in this part of the course is on the key logical and geometric representations that make it possible to map from logic to layout, and in particular, to place, route, and evaluate the timing of large logic networks. Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: technology mapping, timing analysis, and ASIC placement and routing.
Recommended Background:
Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms). An understanding of basic digital design: Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Linear algebra and calculus at the level of a junior or senior in engineering. Elementary knowledge of RC linear circuits (at the level of an introductory physics class).

KJ

AL

Oct 21, 2018

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Great basic overview of the core design principles for EDA

From the lesson

Timing Analysis

You synthesized it. You mapped it. You placed it. You routed it. Now what? HOW FAST DOES IT GO? Oh, we need some new models, to talk about how TIMING works. Delay through logic gates and big networks of gates. New numbers to understand: ATs, RATs, SLACKS, etc. And some electrical details (minimal) to figure out how delays happen through the physical geometry of physical routed wires. All together this is the stuff of Static Timing Analysis (STA), which is a huge and important final "sign off" step in real ASIC design.

Taught By

Rob A. Rutenbar

Adjunct Professor

Transcript

[SOUND]. So here in lecture 12.6 we're going to continue our exploration of timing, and we're going to move from the logic side of things to the layout side, to the geometry side. One of the things that's true in any modern technology is that there's a lot of wire, you know, putting those 10 million gates together, you know, 10, 20 million wires you know, kilometers and kilometers of wire around the surface of the chip. There are real delays through all of those wires. How do I take the physical routed shape of a wire and turn it in to a delay. And it turns out there is really no substitute for treating the wire as an electrical circuit, a very simple electrical circuit. A so-called passive electrical circuit. Something made for us out of just resistors and just capacitors in order to move it to a point where I can ask a question like, how much delay from this input to this output on something with a complicated shape? Now, since I don't expect everybody in this class to have an electrical engineering degree in their background, I'm not really going to do any detailed circuit analysis. I'm going to assume that you know enough circuits from, say, a basic high school physics class or an introductory high school physics class so that I can talk about what a resistor is, and I can talk about what a capacitor is. And I can talk about how the physical routed wire turns into a very small circuit. But I'm not going to show you the interesting circuit analysis that lets me derived the delay result. I'm just going to show you how the physical routed wire has to be turned into a small interesting little circuit. And from that circuit we can actually do the analysis we need and as I've said so many times in this class, the amazing thing is we're going to build a tree. We're going to build a little data structure that looks like a tree and where this is heading is that a very particular kind of a computational walk. On this tree, that is derived from the circuit that we pull out of the wire is going to give us all of the delay information we need to be able to do all of the required timing analysis. So lets go look at the circuit level view of routed wires. So our next problem to focus on is how do we model the delays that are inherent to the wires, and the, and the interconnect. And you know, here's, sort of, the problem at a, at a high level. You placed the logic. And the logic put the pins at a certain distance apart. And so you now go in and route the wires. And, each wires has, an, an, you know, an input output delay. Or even more precisely, input to output delays. Because there's a delay each pin. Each of the elements that you're fanning out to connect. Where does the delay come from? How accurately can I predict that delay? How can we efficiently model that delay for the CAD purposes that we've been talking about for use in layout or synthesis or status timing analysis. You know, look, I mean, the wire is physically, a circuit object, you know, you put a waveform, an electrical waveform in one end of it. And, you know, you get a delay and it shows up, on the other end of it. And you know it might show up quickly for the part of the wire that's close, and far away for the part of the wire that's far away, at, at a greater distance. How am I going to model something like that? Well, you know we can take a step back and kind of talk about how people used to model these things. For example, the first model, the most historical classical older model is to say look the delay of the wire is related to the finite speed of signal propagation through the physical material. You know, there's a speed of light, it's a limit. And so to first order you know that model is that you know delay is the length. Right? So, a shorter wire is a faster wire and a longer wire is a slower wire. And you that's fine in terms of being qualitatively okay. So, for example I can do something like the bounding box is you know delta x plus delta y just like the placer. you know we could use something like that we'd have some formula based on the length of the bounding box. It's you know its its qualitiatvely okay its not accurate it is in fact extremely crude. The second source of delay is that we have to deal with the fact that delay is effected by the electrical circuit drive limitation. So, so that says look. What's really happening is not just the length but the electrical loading on the wires. So the, the delay is proportional to the length of the wire, the fan out of the wire, the capacitance of the you know, the driven pins. You know, a lot of, a lot of electrical stuff. So for example, we would say look the delay is related to the fact that the fanout is two, we have to account for the loading due to the two pins. The delay is some kind of a function, it's a function of the bounding box. The function of the size of the driver gate, the fan outs, and electrical characteristics of the pins and so on. You know, this is qualitatively better, and it's not that hard to curve fit some models for this data. But it still just focuses on the pins really. and it's not really focusing on the wire per say and it, it can still be really off by, by a lot. Then ultimately you're forced to, to, to admit that the delay comes from the electrical loading of the interconnect. It depends critically on the exact geometry of the wired net. I mean, I, I need to know the shape of the wire in order to figure this out. And so, the real honest electrical model for one of these things is an electrical circuit. You know, you have to model these things as a circuit and you have to analyze them as a circuit. And so the question is how do you analyze something like this as a circuit? So, I mean, if we look at the simplest possible case where I'm, I'm routing things in the first level of metal, you know there's a metal, a metal wire. It's separated from the silicon surface itself by some stuff which we can just treat as some sort of an insulating kind of layer. you know, how am I actually going to model this thing as a circuit. Now, you know, one of the first questions is, why do I have to model this as a circuit? And the real answer is just that the nanoscale will, you know, your transistors are measured in hundreds of atoms across. The interconnect geometry is large relative to the devices themselves and so it presents a significant amount of, sort of, you know, electrical stuff that you just, you just can't ignore. [NOISE] So, the most popular interconnect model that we're going to talk about are things called RC Trees, R for resistor, C for capacitor. So we're going to talk a little bit of circuits here. but we're not going to do anything in any detail, an hopefully, you know, people have seen this much circuit in some, in some basic high school. Or maybe introductory college physics. Right, so here's my wire again. And now I'm, I'm, I'm putting some dimension on it. So you know the metal wire is L units long, it's H units high, it's a W units wide. And it's sitting on top of an insulator of height D. And that's sitting on top of the silicon surface. So the first thing, in order to take this hunk of metal. It just a great big purple metal bar, as I've drawn it. Is to acknowledge that the metal has a resistance to current flowing down its length. So if you, you take some current, and you know you put it in one end, and it goes through the wire. It comes out the other end, there's a resistance, right? So that's what that zigzag line is. Right, and in physics, we can write a formula for that resistance. So that resistor value is rho, which is a material constant, times the length of the wire divided by the width times the height. And so the way you think about that is, how do you make a resistor bigger? And the answer is, you make the wire longer, L is bigger. How do you make a resistor smaller? And the answer is, you make the cross-sectional area bigger, so there's sort of you know, more places for the electrons to go through. Now, in an ASIC, I don't really get to control all those parameters. Right? I can control the length of the wire. And I can actually control the width of the wire. But I can't control the height of the wire. That's, that's the manufacturing process. So we're not going to use a row. We're going to use just a little lower case r, for our formula. So, the resistance R, is lower case r times the length divided by W because I can control the length and I can control the W. So I can model the resistance of this wire to current flow. The other thing that this wire has, which is maybe a little surprising, is that it has capacitance to the silicone substrate. So you remember what a capacitor is? A capacitor is just two conducting plates, separated by something that's not conducting. And the thing that's interesting in this case is that the thing that's conducting is the metal. And the other thing that's conducting is the silicon surface and there's an insulator between them which kind of prevents them from connecting to each other. So you're going to remember what a capacitor is just a metal plate or its a conducting plate separated by another conducting plate from an insulator so in this case the metal is one of the plates of the capacitor. The silicon is the other plate of the capacitor, and the insulator is the, just the, the dielectric material that's in between that's preventing them from connecting to each other. So again, there's a physics formula. The capacitance is epsilon, which is some material parameter stuff times the, basically the plate area of the capacitor, which in this case is W times L. Divided by the separation between the things where the conductors are, the things where the charge goes, which in this case is d, the height of the insulator. And again, I can't control all of this stuff. So, for us, for the asic the formula that we are interested in is that the capacitance is c, a smaller case parameter c, multiplied by basically the footprint of the wire, the width times the length. Because we can control the width and we can control the length. Now I have to tell you this. that model is incredibly simplistic. It's good enough for us to make some progress. but it's incredibly simplistic. So in a real capacitance. Or you know people just call this cap very frequently. You get a capacitance between any pairs of conducting surfaces. So in a multi layer metal process you get caps between all the layers. So I've got a little diagram here. It's three metal wires wide. It's kind of a cross section looking into metal wires running out of the slide. Three blue metal wires on metal three. Then on top of them, three blue metal wires on metal four. And then on top of that two but not three pink metal wires in metal five. left to right three boxes on the bottom layer, three boxes on the middle layer; a left box and middle box, but no right box. And what I'm showing you is between every pair of surfaces of conducting surfaces, there's a capacitor. So, up on the third row of conductors. There is a capacitor between the side of one metal five wire, and the side of another metal five wire. Those are fringe capacitors between two adjacent wires on the same layer. There are and I'm showing this sort of the right wires in row one and row two. there are overlap capacitances between wires on Adjacent layers. What we're basically talking about in our derivation are overlap capacitances between a wire and whatever's below it. there are sidewall fringe capacitances in which between the side of one wire and the top of another wire, if there's not another wire in the way. this stuff is incredibly complicated, you need real live computational electromagnetics to do this stuff. And depending on how accurately you want it there are really good approximations for how you do this. When you look a realistic process, you typically get numbers that just involve, some, some parameters and, you know? How long is the wire and, you know, how much do things overlap? And, you know? You can calculate first order numbers that are, that are very helpful. And if you need really really accurate numbers, you have to go off and do some more sophisticated computational stuff. We're not going to touch any of this stuff. I'm just going to use the lower case r and the lower case c that I showed you on the previous slide. Now, the Interconnect model that is the most famous and the most useful and the most practical is something called a Pi model. And it's called a Pi model, because the circuit we're about to build looks like a Pi, the Greek letter Pi. And so, it accounts for the resistance of this wire and the capacitance. Now, so, the first thing to think of is that the current goes in one end of the metal. And the current comes out the other end of the metal. And I'm drawing those two big circles, because those are nodes. Those are electrical nodes. And those are going to get, going to, going to appear when I draw this as a circuit. And so when I draw this as a circuit. What happens is, I get a resistance between those two nodes, right? Because there's a resistance to the current going in one of those circles, and coming out the other. But I also get capacitance, right? And where the capacitance goes. Right depending whether you are seeing this signal before. The capacitance in the model I am showing you goes to ground. Right and so we see people drawing that with, with a solid triangle, we see people drawing that with a an open triangle. And I'm not drawing it in my slides, but sometimes you see people drawing it with three little lines that get narrower like a point. And so this is a Pi model and one resistor and two capacitors. So the resistor is lowercase R times L divided by W, length divided by width. The capacitor value is C times W times L and I put half the capacitor on the left and half the capicator on the right. Because one of the things its very convenient is to make this model symmetric. So I split the capacitor with half of it on the left and half of it on the right this is a wonderful small model and I only need two numbers. Right, I need the R number and I need the C number, and I can fully paramiterize this little Circut model. But this is just one piece of metal. And the big idea is i replace every straight wire segment in my wire with a Pi model. All right, so, I've got a whole bunch of pieces of wire. One, two, three, four, five in this particular case. and I'm going to take every single one of those wire segments every single one of those straight line segments and replace it with one resistor and two capacitors. And if you're saying to yourself, wow if I have a great big wire that has a lot of bends and kinks and stuff like that there's a whole lot of resistors and a whole lot of capacitors. And the answer is, yes it's just the way it works. And one of the things I am not doing in the wires that I am showing you, is I'm not showing you any VLs. VLs typically actually just get modeled as a resistor. Okay. So that's actually pretty easy to deal with. and so every straight line segment becomes a Pi model but the other seems to be a little bit of complexity here right. And one of the things to be aware of in that this that, that, that thing is just that node right there. Okay. And so I've got one, two, three, four, five wire segments. I've got one, two, three, four, five Pi models with a resistor and three capacitors. There's three wire segments coming together at that point there. And the thing to be really, you know, very clearly aware of, is that those nodes are all electrically connected. So I'm going to draw a circle here. I'm going to draw a circle here. I'm going to draw a circle here. And I'm just saying look, all those capacitors are actually connected at the same node. So, I'm even just going to draw little dotted lines to sort of highlight that. and this is sort of awkward, and it would be nice if there was a little bit of a circuit kind of a trick we could do, because this is looking just a little bit complicated. So I'll just remind you that there's a nice simplification rule from basic circuits or physics, wherever you learned it. Parallel capacitors can be replaced by one bigger[COUGH] capacitor. And you just add the capacitor numbers together. So in that place where those three capacitors were all connected, you add the capacitor numbers together. So literally, any place multiple ends of a wire segment come together in one of these connected Pi models. You just add the capacitors together and the resistors just connect. Right? So, in this particular case, when I was at that, sort of, junction in the wire, and I had three capacitors, right? What actually happened, was that they all got replaced by one value of capacitor. An we get something, that actually looks kind of simple, you know, not so tremendously complicated. This is something called an RC tree. So why is it called an RC tree? It's called an RC tree because it's a tree of resistors. You look at that object and you say, oh, that's a tree. It's got a, it's got a root and it's got leaves. And when I walk down the links on the tree, what I'm walking over is the resistors and it's got capacitors hanging off of it. So this is a really famous object. And one of the reasons it's famous is because it's simple to analyze. And turns out I don't even need to analyze it like like a, like a circuit to be able to extract some value from it. So let's go do that next. [SOUND]

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