The floating-point DSP design flow includes Altera’s floating-point DSP compiler, which is integrated into the DSP Builder Advanced Blockset, Quartus® II RTL tool chain, and ModelSim simulator, as well as the MATLAB and Simulink tools from MathWorks to simplify the DSP algorithm-implementation process on FPGAs. The floating-point design flow combines and integrates the algorithm modeling and simulation, RTL generation, synthesis, place and route, and design verification stages. The integration enables quick development and rapid design-space exploration, both at the algorithmic level and at the FPGA level, and ultimately reduces overall design effort.

“Using Altera’s high-level DSP model-based flow, designers can implement and verify complex floating-point algorithms more efficiently and quickly than would be possible with traditional HDL-based design,” said Vince Hu, vice president of product and corporate marketing at Altera. “Once the algorithm is modeled and debugged at a high level, the design can be easily synthesized and targeted to any Altera FPGA.”

Altera® programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more about Altera’s FPGA, CPLD and ASIC devices at www.altera.com. Follow Altera via Facebook, RSS and Twitter.

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This entry was posted on Monday, September 12th, 2011
at 8:56 pm and is filed under News.

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