Intilop

Intilop's 76-nanosecond Full TCP Offload (TOE) Establishes Yet Another System Latency Record With Altera Stratix-V FPGA board from BittWare

Intilop extends their leadership in Hyper Accelerated TCP/IP processing by delivering another record breaking ‘Wire to User Application’ full system latency of 230 Nano seconds!

Santa Clara, CA -- (SBWIRE) -- 06/20/2012 -- Intilop, Inc. a pioneer and a recognized leader in providing complex networking Mega-IP building blocks and full systems, today announced delivery of a full FPGA based System Platform powered by their new Ultra Low latency 4th Gen 10G Nano TOE and Ultra Low latency Media Access controller. It integrates Ultra-Low Latency PHY available in Altera Stratix-V FPGAs. Full System Platform is on an Altera Stratix-V FPGA board from BittWare. This extends their leadership of more than 3 years in providing series of full TOEs and systems powered by them. Their mature, network proven series of TOE's have been deployed in hundreds of networks worldwide including blue-chip companies, financial institutions and major world stock exchanges enabling trade executions in record 1 us. The new platform is bound to shatter this record by yet another few hundred Nano seconds! It is also removing major traffic bottlenecks in Networks around the world.

The Full System FPGA platforms provide an ‘out of the box’ ready to use FPGA board where users can immediately start integrating/running the ultra-low latency full TCP offload hardware with their application software or with their hardware applications. This offers tremendous advantages by simplifying the tedious task of integration while removing risk of integrating a complex system on an FPGA.

This Hyper Accelerated FPGA Platform with all its integrated sub-system components; pegs the latency from Wire-to-User-FIFO at an unprecedented 230 ns! This opens up a new chapter in the ‘Race-to-Zero Latency’.

This ‘Game-changing’ 76 ns TOE Technology’ that delivers unprecedented performance at 20Gbps in full duplex is 100X faster than legacy TCP/IP software. This is the most deterministic performance with zero jitter by any complex protocol processor ever.

Intilop was the first company to deliver full TCP/IP stack in FPGA in early 2009 and has consistently broken latency and performance records with their subsequent products. “These new full System FPGA platforms based around our flagship Nano TOEs & EMACs further extend our leadership and are pleased to see accelerated pace of adoption in the networks worldwide”, says Kelly Masood, Intilop’s CTO.