This paper presents the implementation of a speaker-verification system on field programmable gate array. The algorithm is executed by software over an embedded system that includes a MicroBlaze microprocessor connected to a vector floating-point unit (VFPU). The VFPU is designed to speed up the resolution of any vector floating-point operation involved in the verification algorithm, whereas the microprocessor manages the control of the process and executes the rest of operations. With a clock frequency of 40 MHz, the system is capable of executing the complete algorithm in real time, processing a voice frame in 9.1 ms. The same verification process was carried out for two different systems: 1) an ARM Cortex A8 microprocessor; and 2) configuring
MicroBlaze with the scalar floating-point unit provided by Xilinx. The experimental results show that when comparing our proposed system against both systems, the number of clock cycles is reduced by a factor of 11.2× and 15.4×, respectively. The main advantage of the VFPU is its flexibility, which allows quick adaptation of the software to the potential changes produced in both the system and the user requirements. The algorithm was tested over a public database that contains the utterances of different users acquired under different environmental conditions, providing good recognition rates.

This paper presents a new proposal for hiding the cryptographic key, when the so-called side-channel attacks (SCAs) are applied to break the security of AES-128. The algorithm was executed on MicroBlaze, but the proposed method is generic and can be extended to any other microprocessor. SCAs are based on examining the correlation produced between the data and operations performed by the microprocessor and its actual power consumption. Traditionally, such weakness is counteracted by introducing countermeasures addressed to reduce as much as possible this correlation, making data and power consumption independent. On the contrary, the proposal presented in this paper introduces some modifications in the AES algorithm. These changes aim at concealing the true key by reinforcing the correlation coefficient in such a way that a classical attack leads to a false key. This way, the system misleads the attacker and apparently behaves as an unprotected system that, in fact, reveals a false positive. The complete system was built on a Virtex-5 FPGA. Experimental results show the strength of our implementation, which is capable of successfully hiding the true cryptographic key.

This paper describes the implementation on field-programmable gate arrays (FPGAs) of an embedded system for online signature verification. The recognition algorithm mainly consists of three stages. First, an initial preprocessing is applied on the captured signature, removing noise and normalizing information related to horizontal and vertical positions. Afterwards, a dynamic time warping algorithm is used to align this processed signature with its template previously stored in a database. Finally, a set of features are extracted and passed through a Gaussian Mixture Model, which reveals the degree of similarity between both signatures. The algorithm was tested using a public database of 100 users, obtaining high recognition rates for both genuine and forgery signatures. The implemented system consists of a vector floating-point unit (VFPU), specifically designed for accelerating the floating-point computations involved in this biometric modality. Moreover, the proposed architecture also includes a microprocessor, which interacts with the VFPU, and executes by software the rest of the online signature verification process. The designed system is capable of finishing a complete verification in less than 68 ms with a clock rated at 40 MHz. Experimental results show that the number of clock cycles is accelerated by a factor of x4.8 and x11.1, when compared with systems based on ARM Cortex-A8 and when substituting the VFPU by the Floating-Point Unit provided by Xilinx, respectively.

The main aim of this paper is the development of a new technology for biometric recognition that allows safe and secure access to universal services such as credit card payment, ATMs, access control, border control, etc. The technology being developed is very generic and easily adaptable to the specific particularities of disabled people; a collective that represents an important proportion of current population (e.g. about the 9% of the total Spanish population).

The main aim of this paper is the development of a
new technology for biometric recognition that allows safe and
secure access to universal services such as credit card payment,
ATMs, access control, border control, etc. The technology being
developed is very generic and ea
sily adaptable to the specific
particularities of disabled people;
a collective that represents an
important proportion of current po
pulation (e.g. about the 9% of
the total Spanish population).

Nowadays, biometrics is considered as a promising solution in the market of security and personal verification. Applications such as financial transactions, law enforcement or network management security are already benefitting from this technology. Among the different biometric modalities, speaker verification represents an accurate and efficient way of authenticating a person’s identity by analyzing his/her voice. This identification method is especially suitable in real-life scenarios or when a remote recognition over the phone is required. The processing of a signal of voice, in order to extract its unique features, that allows distinguishing an individual to confirm or deny his/her identity is, usually, a process characterized by a high computational cost. This complexity imposes that many systems, based on microprocessor clocked at hundreds of MHz, are unable to process samples of voice in real-time. This drawback has an important effect, since in general, the response time needed by the biometric system affects its acceptability by users. The design based on FPGA (Field Programmable Gate Arrays) is a suited way to implement systems that require a high computational capability and the resolution of algorithms in real-time. Besides, these devices allow the design of complex digital systems with outstanding performance in terms of execution time. This paper presents the implementation of a MFCC (Mel-Frequency Cepstrum Coefficients)—SVM (Support Vector Machine) speaker verification system based on a low-cost FPGA. Experimental results show that our system is able to verify a person’s identity as fast as a high-performance microprocessor based on a Pentium IV personal computer.

Nowadays, biometrics is considered as a promising
solution in the market of security and personal verification.
Applications such as financial transactions, law
enforcement or network management security are already
benefitting from this technology. Among the different biometric
modalities, speaker verification represents an accurate
and efficient way of authenticating a person’s identity
by analyzing his/her voice. This identification method is
especially suitable in real-life scenarios or when a remote
recognition over the phone is required. The processing of a
signal of voice, in order to extract its unique features, that
allows distinguishing an individual to confirm or deny his/
her identity is, usually, a process characterized by a high
computational cost. This complexity imposes that many
systems, based on microprocessor clocked at hundreds of
MHz, are unable to process samples of voice in real-time.
This drawback has an important effect, since in general, the
response time needed by the biometric system affects its
acceptability by users. The design based on FPGA (Field
Programmable Gate Arrays) is a suited way to implement
systems that require a high computational capability and the
resolution of algorithms in real-time. Besides, these devices
allow the design of complex digital systems with outstanding
performance in terms of execution time. This paper
presents the implementation of a MFCC (Mel-Frequency
Cepstrum Coefficients)—SVM (Support Vector Machine)
speaker verification system based on a low-cost FPGA.
Experimental results show that our system is able to verify
a person’s identity as fast as a high-performance microprocessor
based on a Pentium IV personal computer.

Many image-processing algorithms require several stages to be processed that cannot be resolved by embedded microprocessors in a reasonable time, due to their high-computational cost. A set of dedicated coprocessors can accelerate the resolution of these algorithms, although the main drawback is the area needed for their implementation. The main advantage of a reconfigurable system is that several coprocessors designed to perform different operations can be mapped on the same area in a time-multiplexed way. This work presents the architecture of an embedded system composed of a microprocessor and a run-time reconfigurable coprocessor, mapped on Spartan-3, the low-cost family of Xilinx FPGAs. Designing reconfigurable systems on Spartan-3 requires much design effort, since unlike higher cost families of Xilinx FPGAs, this device does not officially support partial reconfiguration. In order to overcome this drawback, the paper also describes the main steps used in the design flow to obtain a successful design. The main goal of the presented architecture is to reduce the coprocessor reconfiguration
time, as well as accelerate image-processing algorithms. The experimental results demonstrate significant improvement in both objectives. The reconfiguration rate nearly achieves 320 Mb/s which is far superior to the previous related works.

Many image-processing algorithms require several stages to be processed that cannot
be resolved by embedded microprocessors in a reasonable time, due to their high-computational
cost. A set of dedicated coprocessors can accelerate the resolution of these algorithms, alt
hough
the main drawback is the area needed for their implementation. The main advantage of a
reconfigurable system is that several coprocessors designed to perform different operations can
be mapped on the same area in a time-multiplexed
way. This work presents the architecture of
an embedded system composed of a microprocessor and a run-time reconfigurable coprocessor,
mapped on Spartan-3, the low-cost family of Xilinx FPGAs. Designing reconfigurable systems
on Spartan-3 requires much design effort, since unlike higher cost families of Xilinx FPGAs,
this device does not officially support partial reconfiguration. In order to overcome this
drawback, the paper also describes the main steps used in the design flow to obtain a successful
design. The main goal of the presented architecture is to reduce the coprocessor reconfiguration
time, as well as accelerate image-processing algorithms. The experimental results demonstrate
significant improvement in both objectives. The reconfiguration rate nearly achieves 320 Mb/s
which is far superior to th
e previous related works.

This paper describes the implementation of an iris recognition algorithm based
on hardware-software co-design. The system architecture consists of a general-purpose 32-
bit microprocessor and several slave coprocessors that accelerate the most intensive
calculations. The whole iris recognition algorithm has been implemented on a low-cost
Spartan 3 FPGA, achieving significant reduction in execution time when compared to a
conventional software-based application. Experimental results show that with a clock
speed of 40 MHz, an IrisCode is obtained in less than 523 ms from an image of 640x480
pixels, which is just 20% of the total time needed by a software solution running on the
same microprocessor embedded in the architecture.

This work aims to pave the way for an efficient open system architecture applied to embedded electronic applications to manage the processing of computationally complex algorithms at real-time and low-cost. The target is to define a standard architecture able to enhance the performance-cost trade-off delivered by other alternatives nowadays in the market like general-purpose multi-core processors. Our approach, sustained by hardware/software (HW/SW) co-design and run-time reconfigurable computing, is synthesizable in SRAM-based programmable logic. As proof-of-concept, a run-time partially reconfigurable field-programmable gate array (FPGA) is addressed to carry out a specific application of high-demanding computational power such as an automatic fingerprint authentication system (AFAS). Biometric personal recognition is a good example of compute-intensive algorithm composed of a series of image processing tasks executed in a sequential order. In our pioneer conception, these tasks are partitioned and synthesized first in a series of coprocessors that are then instantiated and executed multiplexed in time on a partially reconfigurable region of the FPGA. The implementation benchmark of the AFAS either as a pure software approach on a PC platform under a dual-core processor (Intel Core 2 Duo T5600 at 1.83 GHz) or as a reconfigurable FPGA co-design (identical algorithm partitioned in HW/SW tasks operating at 50 or 100 MHz on the second smallest device of the Xilinx Virtex-4 LX family) highlights a speed-up of one order of magnitude in favor of the FPGA alternative. These results let point out biometric recognition as a sensible killer application for run-time reconfigurable computing, mainly in terms of efficiently balancing computational power, functional flexibility and cost. Such features, reached through partial reconfiguration, are easily portable today to a broad range of embedded applications with identical system architecture.

In this thesis, the processing of impulsive signals generated by impacts between rigid bodies is investigated. One of the problems found when working with impacts is that their analysis is generally limited to indirect measurements: because collisions do not develop directly on the sensor, or it is not possible to install the sensor on the colliding bodies. This means that between the sensor and the point of impact there is a propagation medium that distorts the measured signal.The main effort of this thesis focuses on the problem of how to compensate or to reduce the effects of such distortion. To do this, the following points have been investigated and developed:1) The study of the mechanical impact theory and the development of a mathematical model of the impact process between two rigid bodies. Through this study, the characteristics of the impulsive signals generated by collisions are investigated.2) Definition of an experimental methodology for generating repeatable impacts and for determining the parameters of the mathematical model. The methodology is based on the design and implementation of an experimental prototype for generating controlled impacts between a test object and a sensorized impactor. To perform the experiments, a set of different test objects have been selected, cylinders made form aluminum, steel, bronze and brass in different sizes. Through a careful study and calculation of the experimental parameters, the validity of the mathematical model has been verified.3) Study of the indirect measurement problem, and proposal of a signal processing method, based on artificial neural networks, to determine an inverse filter in order to estimate the impacting signal (the impact force as a function of the time). This methodology adapts the training process to the characteristics of the impulsive signals that are generated during a collision, and that have been identified through the study and modeling of the impact process. The training uses real signals, which come from experimental impacts generated at different impacting velocities, and signals generated by a mathematical model of the impacting force.4) Proposal for a methodology to estimate the type of material and mass of test objects that collide. The problem found in this analysis is that both, the objects and their responses, have similar characteristics. With the method proposed in this thesis, it is possible to identify correctly the characteristics of one of the objects. The procedure considers the extraction of parameters from the vibrating signals of the objects, and then uses a neural network to classify those parameters.5) Evaluation process of the proposed methods. To determine the validity of the processing methods described above, first, the selection of the most appropriate sensors to acquire these signals has been analyzed (this signals have a very short duration and very large bandwidth). Secondly, a measurement and acquisition system for impulsive signals has been implemented.The experimental results show the validity of the proposed methods. In the case of the model, its validity has been verified with data from different test objects, made from different materials. Also, the proposed method used to deal with the distortion due to the indirect measurement has been tested with experimental data, from impacts with different test objects, and the results show that it operates properly. Likewise, the proposed method to identify the type of material and mass of the test objects has generated satisfactory results.

The main purpose of this work is to propose a dynamical model for simulating the response of different metallic objects when impacted by another rigid body. In addition, a methodology for estimating the model parameters is presented and discussed. Results from real experiments shows that by assuming certain characteristics on impacting objects, the dynamic model can reproduce the transient dynamics during contact time.

Complex algorithms usually require several computation
stages. Many embedded microprocessors have not enough
computational performance to resolve these algorithms in a
reasonable time, so dedicated coprocessors accelerate them
although the main drawback is the area devoted to them. A
reconfigurable coprocessor can drastically reduce the area,
since it accommodates a set of coprocessors whose
execution is multiplexed on time, although the
reconfiguration speed reduces the overall system
performance. Although self-reconfigurable systems are
possible on Spartan-3 FPGAs, it requires a hard design
task due to the lack of software and hardware support
available on higher-cost families. This paper describes the
architecture of a fast self-reconfigurable embedded system
mapped on Spartan-3, used as computation platform to
solve a complex algorithm, such as the image-processing
carried out in a fingerprint biometric algorithm. In order to
reduce the reconfiguration time, the system uses our
custom-made memory and reconfiguration controllers.
Moreover, the dynamic coprocessor can access directly to
external memory through our memory controller to
improve processing time.

Biometric systems, characterized by their high confidential
levels of security, are usually based on high-performance
microprocessors implemented on personal computers.
These advanced devices contain floating-point units able to
carry out millions of operations per second at frequencies in
the GHz range, being qualified to resolve the most complex
algorithms in just a few hundred of milliseconds. However,
their main drawback is the cost, and the necessary space
required to incorporate their external associated peripherals.
This disadvantage is especially significant in the low-cost
consumer market, where factors such as price and size
determine the viability of a product. The use of an FPGA is
a suited way to implement systems that require a high
computational capability at affordable prices. Besides, these
devices allow the design of complex digital systems with
outstanding performances in terms of execution times. This
paper presents the implementation of a SVM (Support
Vector Machines) speaker verification system on a low-cost
FPGA. Experimental results show as our system is able to
verify a person’s identity as fast as a high-performance
microprocessor based on a Pentium IV personal computer.

Reconfigurable computing adds to the traditional
hardware/software design flow a new degree of freedom in the
development of electronic systems. In a system-on-chip
platform, the fact that a MCU makes evolve at run-time a
hardware coprocessor mapped on a FPGA, to execute thus
different compute-intensive tasks in the same silicon-area,
results in a clear earned value applied to the system
implementation: the low-cost reached through the resources
time-multiplexing. Under that approach, this work merges
both reconfigurable computing and HW/SW co-design
technologies to develop an efficient architecture of an
automatic fingerprint authentication system (AFAS) oriented
to real-time embedded applications.