changing -coreid 0 to -coreid 1. At present it is not possible to connect to both Cortex-A9 cores simultaneously.

Working Items

halt, single-step, resume

breakpoints and watchpoints

reading/writing memory

inspecting core/register state

All memory accesses (including md/mw commands and disassembly) execute through the debug AHB on the L3 interconnect; resources on the L2 interconnect currently can not be accessed. This includes ROM, local PRCM, and anything in the Cortex-A9 "private memory region" (snoop-control unit, global interrupt controller, timers and watchdogs).

Non-Working Items

debugging A9 cores simultaneously

accessing L2 memory resources

unify a8/a9 code

Debug clocking

The debugger may not be able to access the A9 processor cores due to an issue with omap4430 clocking. If your debugger can identify JTAG devices, e.g.: