I use EBI interface for connecting to FPGA. All works fine (read, write, including using DMA). But I found that DMA transmits data in batches of 16 write cycles. For example, I run DMA-transfering 1024 bytes to FPGA and see (part of the transmission is visible):

It's normal behavior for DMA? Why do these pauses appear? Code for configuring and starting DMA transaction taken in this driver (see atmel_nand_dma_op function) as a basis. Processor: SAMA5D35.

Best Regards, arhiv6.

Last edited by arhiv6 on Mon Jun 18, 2018 7:28 am, edited 1 time in total.