General descriptionThe 74AUP1G386 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and falltimes across the entire VCC range from 0.8 V to 3.6 V.This device ensures a very low static and dynamic power consumption across the entireVCC range from 0.8 V to 3.6 V.This device is fully specified for partial power-down applications using IOFF.The IOFF circuitry disables the output, preventing the damaging backflow current throughthe device when it is powered down.The 74AUP1G386 provides a single 3-input EXCLUSIVE-OR gate.

DESCRIPTIONThe PTD08A020W is a high-performance 20-A rated, non-isolated digital PowerTrain module. It is the power conversion section of a digital power system. The PTD08A020W must be used in conjunction with a digital power controller such as the UCD92XX or UCD91XX family. The PTD08A020W receives control signals from the digital controller and provides parametric and status information back to the digital controller. Together, PowerTrain modules and a digital power controller form a sophisticated, robust, and easily configured power management solution.Operating from an input voltage range of 4.75 V to 14 V, the PTD08A020W provides step-down power conversion to a wide range of output voltages from, 0.7 V to 3.6 V. The wide input voltage range makes the PTD08A020W particularly suitable for advanced computing and server applications that utilize a loosely regulated 8-V to 12-V intermediate distribution bus. Additionally, the wide input voltage range increases design flexibility by supporting operation with tightly regulated 5-V, 8-V, or 12-V intermediate bus architectures.The module incorporates output over-current and temperature monitoring which protects against most load faults. Output current and module temperature signals are provided for the digital controller to permit user defined over-current and over-temperature warning and fault scerarios.The module uses double-sided surface mount construction to provide a low profile and compact footprint.Package options include both through-hole and surface mount configurations that are lead (Pb) - free and RoHS compatible.

DescriptionThe 54VCXH162245 is a low voltage CMOS 16 bit bus transceiver (3-state) fabricated with submicron silicon gate and five-layer metal wiring C2MOS technology. It is ideal for low power and very high speed 1.65 to 3.6V applications; it can be interfaced to 3.6V signal environment for both inputs and outputs.This IC is intended for two-way asynchronous communication between data buses; the direction of data transmission is determined by DIR input.The two enable inputs nG can be used to disable the device so that the buses are effectively isolated. The device circuits is including 26Ω series resistance in the A port outputs. Theseresistors permit to reduce line noise in high speed applications. Bus hold on data inputs is provided in order to eliminate the need for external pull-up or pull-down resistor.All inputs and outputs are equipped with protection circuits against static discharge, givingthem 2KV ESD immunity and transient excess voltage. All floating bus terminals during High ZState must be held HIGH or LOW.

Description The A8697 is a constant off-time current mode step-down regulator with a wide input voltage range. Regulation voltage is set by external resistors, to output voltages as low as 0.8 V.The A8697 includes an integrated power DMOS switch to reduce the total solution footprint. It also features internal compensation, allowing users to design stable regulators withminimal design efforts.

The off-time can be set with an external resistor, allowing flexibility in inductor selection. Additionally, the A8697 has a logic level enable pin which can shut the device down andput it into a low quiescent current mode for power sensitive applications.

Description The ZL50075 is a non-blocking Time Division Multiplex (TDM) switch with maximum 32,768 x 32,768 channels. The device can switch 64 kbps and Nx64 kbps TDM channels from any input stream to any output stream. With a number of enhanced features, the ZL50075 is designed for high capacity voice and data switching applications.

The ZL50075 has 64 input and 64 output data streams which can operate at 8.192 Mbps, 16.384 Mbps, 32.768 Mbps or 65.536 Mbps. The large number of inputs and outputs maintains full 32 K x 32 K channel switching capacity at bit rates of 65 Mbps and 32 Mbps. Up to 32 input and output data streams may operate at 65 Mbps. Up to 64 input and output data streams may operate at 32 Mbps, 16 Mbps or 8 Mbps. The data rate can be independently set in groups of 2 input or output streams. In this way it is possible to provide rate conversion frominput data channel to output data channel.

The ZL50075 uses a master clock (CKi0) and frame pulse (FPi0) to define the TDM data stream frame boundary and timing. A high speed system clock is derived internally from CKi0 and FPi0. The input and output data streams can independently reference their timings to the input clock or to the internal system clock.The ZL50075 has a variety of user configurable options designed to provide flexibility when data streams are connected to multiple TDM components or circuits. These include:• Variable input bit delay and output advancement, to accommodate delays and frame offsets of streams connected through different data paths• Two timing outputs, CKo1 - 0 and FPo1 - 0, which can be configured independently to provide a variety of clock and frame pulse options• Support of both ST-BUS and GCI-Bus formats - The ZL50075 also has a number of value added features for voice and data applications:• Per-channel variable delay mode for low latency applications and constant delay mode for frame integrity applications: • Per-channel A-Law/µ-Law Conversions for both voice and data• 64 separate Pseudo-random Bit Sequence (PRBS) test circuits; one per stream. This provides an integrated BitError Rate (BER) test capability to facilitate data path integrity checking

The ZL50075 has two major modes of operation: Connection Mode (normal) and Message Mode. In Connection Mode, data bytes received at the TDM inputs are switched to timeslots in the output data streams, with mapping controlled by the Connection Memories. Using Zarlink's Message Mode capability, microprocessor data can be broadcast to the output data streams on a per-channel basis. This feature is useful for transferring control and status information to external circuits or other TDM devices.

A non-multiplexed microprocessor port provides access to the internal Data Memory, Connection Memory and Control Registers used to program ZL50075 options. The port is configurable to interface with either 16 bit Motorola or Intel-type microprocessors.The mandatory requirements of IEEE 1149.1 standard are supported via the dedicated Test Access Port.

Description The TSV991/2/4 family of single, dual & quad operational amplifiers offers low voltage operation and rail-to-rail input and output. This family features an excellent speed/power consumption ratio, offering a 20MHz gainbandwidth, stable for gain above 3 (100pF capacitive load), while consuming only 1.1mAmax at 5V supply voltage. It also features an ultralow input bias current. These characteristics make the TSV991/2/4 family ideal for sensor interfaces, battery-suppliedand portable applications, as well as active filtering.

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The STR-A6259H is a 100 kHz PWM topology (with ±5% frequency jittering for minimum EMI) regulator specifically designed to satisfy the requirements for increased integration and reliability in flyback converters. It incorporates a primary control and drive circuit with an avalanche-rated power MOSFET.

Covering the power range from below 17 watts for a 230 VAC input, or to 13 watts for a universal (85 to 264 VAC) input, this device can be used in a wide range of applications,from DVD players and VCR player/recorders to ac adapters for cellular phones and digital cameras. An auto-burst standby function reduces power consumption at light load, while multiple protections, including the avalanche-energy guaranteed MOSFET, provide high reliability of system design.

Cycle-by-cycle current limiting, undervoltage lockout with hysteresis, overvoltage protection, and thermal shutdown protect the power supply during the normal overload and fault conditions.Overvoltage protection and thermal shutdown are latched after a short delay. The latch may be reset by cycling the input supply.

Low start-up current and a low-power standby mode selected from the secondary circuit completes a comprehensive suite of features. It is provided in an 8-pin mini-DIP plastic package with pin 6 removed. The leadframe plating is pure Sb, and the package complies with RoHS.

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Description The MC10/100EP05 is a 2−input differential AND/NAND gate. The device is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP05 is ideal for applications requiring the fastestAC performance available. The 100 Series contains temperature compensation.