> > No. Well it may be on some platforms but it isn't the same thing. On some> > devices a DMA transfer doesn't need the CPU involved but needs the CPU to> > respond within a set timescale (eg for coherency or bus arbitration). It> > I understand only the CPU can respond after it is notified by a> interrupt event, don't I?

The instruction stream being executed maybe, but not things like the cache

> Also could you give a example about how the CPU responds to a DMA transfer> within a set timescale if it is required?

The kind of thing you are dealing with is

DMA engine requests a cache line of data CPU wakes out of sleep, completes bus transaction CPU goes back to sleep DMA engine starts outputting data bits over SPI bus or similar