Just some musings:
You might be able to use
* A 16-bit shift-left register with only the lower 8 bits programmable -- the upper 8 bits are always loaded with zeros.
* An 8-bit shift-right register with the output fed to
* a 16-bit accumulator. The accumulator adds in the value of the 16-bit register whenever the output from the 8-bit register goes high, OR when the 16-bit register is initially loaded.
* A clock that generates 8 pulses and stops. It clocks both registers.
* Assorted switches, resistors, and LEDs for input, run, and output.

Timing and race conditions are left for the poor student to puzzle his or her head over.

Oh, those nasty professors! Always making someone work hard to remember their lessons.

I guess I'd go with counters. Increment count by fist term, and repeat a number of times equal to second term.

Or use an adder and a counter. Add first term to itself a number of times equal to second term.

Aw, heck. Who are we kidding? I'd argue with the professor until I was blue in the face that EPROMs are just fancy latches and all latches are made from gates!

Click to expand...

Yeah, that's a good argument. But now, If I use a counter, I would have to implement that counter with logic gates. No IC's are allowed basically. So what type of scheme can I use that implements the least # of gates?