PalmChip Bus Patent Threatens Most SoCs

A patent granted to PalmChip Corp. covers the
techniques used to implement on-chip CPU bus structures in nearly
all modern system-on-chip (SoC) designs, the company said. CPU or
system-interconnect intellectual-property vendors and most SoC
design teams may be infringing the new patent, PalmChip warned.

"Our first phase is to inform the SoC industry that we have been
granted this patent," said James Venable, VP of marketing at
PalmChip. "We want to give companies that are creating on-chip buses
an opportunity to examine their technology to see if there is a
conflict and then, if there is, to contact us. We intend to be
cooperative about this, not punitive. But of course we will defend
our patent aggressively."

As such, it describes the CoreFrame technology marketed by
PalmChip. But many SoC interconnect schemes, including ARM's Amba
and IBM's CoreConnect, also can be implemented with uni-directional,
multiplexed paths and separate high- and low-speed buses.

The full implications of the patent are not in the text, which is
a detailed description of the CoreFrame architecture and protocol,
but in the claims. The patent makes 16 claims, addressing SoC bus
structures that use point-to-point uni-directional connections in
place of tristate buses, structures that are organized to use only a
single buffer per line, structures that exchange data through a
shared main memory rather than making direct
peripheral-to-peripheral transfers and structures in which the
low-speed bus uses latches and peripherals with clock frequencies
different from that of the bus controller.

With its sweeping claims, the patent captures a critical point in
the evolution of the on-chip bus. Hence it is applicable to the vast
majority of SoC designs today, according to chip designers
interviewed.

"In the beginning, when designers first started putting IP
[intellectual property] onto chips, there was a tendency to just
migrate whatever system bus had been there when the IP was in
separate packages," said Thomas Petersen, director of product
strategy at MIPS Technologies Inc. "But almost from the moment
people started trying to put tristate buses on chips, they
recognized that it was a bad idea. The obvious alternative was to
use one-directional connections and multiplexers to emulate the bus,
and that's what people did."

There were many good reasons not to use tristate buses on SoCs,
even though some designers continued to do so. The bi-directional
buses presented a huge headache to test developers. And in advanced
processes, bus contentions were likely to damage the interconnect.
That led to logic faults being misdiagnosed as yield issues, further
complicating the search for the problem.

But the initial rejection of tristate was for quite another
reason. "It was actually the FPGA guys who invented the multiplexer
approach," said Leo Petropoulos, director of applications
engineering at Tensilica Inc. "They didn't have tristate drivers in
their logic cells, so as FPGAs got large enough to need on-chip
buses, they had to find an alternative. I first saw it in about
1991."

As it happened, Petropoulos said, the alternative worked very
well with current ASIC processes and tools, too. So it was widely
adopted by the SoC design community. By the late 1990s, ASIC vendors
were strongly discouraging the use of tristate buffers within the
chip, and IBM Microelectronics banned them outright. By then the
switch to multiplexers and uni-directional interconnect had become
nearly universal.

Enormous scopeThat time line indicates the enormous
scope of the technique's useful life - and hence of the patent's
claims. But it also raises a serious question for PalmChip. The
company filed the patent on May 2, 2000, after the move from
tristate to multiplexer-based buses was essentially complete. The
patent may be subject to the objection that it attempts to claim
structures that were already common industry practice well before
the date of filing.

The section of the PalmChip patent on prior art contains a
lengthy discussion of the technical needs and market challenges that
made CoreFrame an attractive technology. But it does not explicitly
cite the widespread use of the sorts of structures described in some
of the patent's claims.

In fact, the number of claims and the specific nature of some of
them suggest that the patent examiner was concerned about prior art,
said Kenneth Allen, a patent attorney with Townsend and Townsend and
Crew. "Often, individual claims come from discussions between the
examiner and the patent attorney," Allen explained. "The examiner
may cite what appears to be prior art, and the attorney will respond
with a narrower claim that makes it clear why the prior art is not
relevant."

Early in the history of SoCs, any integration of IP onto a single
chip was patentable, Allen said. But as SoCs proliferated, examiners
began to find that many integrations were obvious and therefore not
patentable. So patent attorneys had to show, through detailed
claims, that although the idea might appear obvious, there were
certain technical problems, the solutions to which were not obvious.

Even so the results are far from guaranteed. "Examiners are
allowed about eight hours per claim," Allen said. "They work from a
precise library of prior art, not from a detailed knowledge of
everything that has gone on in a field of study."

Allen emphasized that in understanding what a patent was really
trying to accomplish, it was important to look not just at the text,
but at the claims, and to compare the final draft with the initial
one. That makes it possible to see the evolution of the claims
through the give-and-take of examiner and attorney.

PalmChip's officers made it clear that they believe the new
patent, if properly understood, is free of prior art. "This was
absolutely the first use of unidirectional bus structures in a
system-on-chip application," asserted CEO Jauher Zaidi. Venable
emphasized the SoC angle. He said that while before the PalmChip
patent the most common implementation of on-chip buses had been
tristate, a variety of techniques had been used in other sorts of
chips, such as microcontrollers. But in the SoC arena, PalmChip had
priority, he said.

That, some might argue, hinges upon the definition of "SoC." And
in this area the PalmChip patent is distinctly vague. The
application defines its scope in these terms: "The present invention
relates generally to flexible modular integrated circuit
embodiments, and more specifically to a structured framework for
constructing and interfacing variable mixtures of computer
processors, memories, peripherals, and other functional modules on a
single semiconductor integrated circuit."

That definition would apply just as well to a family of
microcontrollers as to a chip more conventionally thought of as an
SoC. This is not surprising, given the lack, even today, of a widely
accepted definition. But the question of prior art may put that
disputed definition at the heart of the efforts to apply - or defeat
- the PalmChip patent.

If the impact of the patent on existing silicon bus architectures
and SoC design practices is potentially great, its effect on the
future of SoC design appears to be more limited. "Today we are in a
predicament where the conventional, multiplexer-based approach to
buses is causing congestion and severely straining the layout
tools," Tensilica's Petropoulos said. "People are starting to look
away from time-domain multiplexed interconnect schemes altogether,
and to think about packet-based interconnect between major blocks on
the SoC."

In fact, the evolution of interconnect between blocks is
following a path very similar to that of the public voice telephone
network. From shared, time-multiplexed buses interconnect is moving
toward more complex structures. "The idea of a crossbar switch for
connecting up blocks has been around forever," observed MIPS'
Petersen. "But now chip architects are starting to apply the concept
of quality-of-service to on-chip crossbars. And there is a lot of
thinking about packetized interconnect as well."

For Petersen, "A lot of the key ideas really crystallized in the
HyperTransport standard. There you have packetized communications,
virtual channels - pretty much everything you need on-chip. It's not
out of the question, if interconnect keeps getting more difficult to
model, to see some TCP ideas like error detection, retries and a
media-access controller for each block in the design. The overhead
would be well worth it if we could have really standard interconnect
and plug-and-play IP."

PalmChip, too, is looking ahead.

"In fact, as part of the development of our next-generation
architecture," Zaidi said, "we have filed additional patents
covering key concepts in the use of crossbar switches and matrix
networks in SoCs."

So it appears that PalmChip's claims, and the arguments over
them, are far from settled.