Intel opens up chip connections

SAN FRANCISCO--Intel announced two moves on Wednesday that will mean other chipmakers can tightly connect their own processors to Intel's.

In one step, the chipmaker will let two companies, Xilinx and Altera, plug their special-purpose chips into the front-side bus that Intel currently uses to connect its own processors to other processors, memory and all other computing subsystems.

In a second step, code-named "Geneseo," it will improve the ubiquitous PCI technology to accommodate a wide variety of accelerator chips, Pat Gelsinger, general manager of Intel's Digital Enterprise Group, said in a speech at the Intel Developer Forum here. IBM and Intel codeveloped Geneseo.

The moves counter rival Advanced Micro Devices, which has gained market share against Intel--particularly in server sales--and which offers a direct connection technology called "HyperTransport." HyperTransport, which began at AMD but is now being jointly developed by a number of computing industry companies, offers direct high-speed connections to and among processors.

AMD's "Torrenza" technology lets coprocessors such as graphics chips, mathematical number-crunchers or video game physics engines plug into HyperTransport. Intel is working on a comparable technology called CSI, variously translated as Common System Interconnect or Common System Interface.

But Gelsinger said PCI (peripheral component interconnect) is a better way to plug such accelerators into a computer.

"This takes the entire momentum of the PCI interface and extends it for a class of emerging application accelerators," Gelsinger said. "A much, much larger portion of the industry is going to benefit from that."

Intel hopes the PCI Special Interest Group that oversees PCI will embrace Geneseo as a successor to PCI Express 2.0, which is expected to debut in 2007. Geneseo itself could arrive as soon as 2008, Gelsinger said.

Because Intel is working with industry partners, it's hard to predict when Geneseo will become a reality. Gelsinger said it typically takes 12 to 18 months to develop such technology and an additional 12 months to bring it to market.

AMD argues it's got a leg up on Intel when it comes to plugging in accelerators and co-processors.

"Earlier this year, AMD announced it has unlocked the full-potential of co-processors and accelerators with its Torrenza initiative. Companies such as DRC and XtremeData already offer products today that can plug into AMD Opteron sockets," Marty Seyer, senior vice president of AMD's commercial segment, said in a statement.

The company also supports using PCI Express, he added. "We see multiple levels of co-processing, ranging from this latest proposed PCI Express approach to the ultimate of direct connect into HyperTransport," Seyer said.

Gelsinger told CNET News.com that Geneseo will be the mainstream method for plugging in co-processor chips, but that some companies are interested in using the front-side bus as well. And Intel wants to make sure it won't lose those partnerships to rivals.

Xilinx and Altera sell field-programmable gate array (FPGA) chips, which can be reprogrammed to perform any number of tasks. Gelsinger showed one called L3NIC that had a 4 gigabit-per-second Ethernet interface. Intel licenses the front-side bus designs to companies that sell chipsets, but the FPGA companies are the first processor makers to which Intel licensed the design.

Though FPGAs are flexible, Gelsinger didn't rule out that the possibility that others could license the front-side bus.

One company absent from the list was server maker Sun Microsystems, which sells only AMD-based x86 servers. But Sun's head x86 server engineer, Andy Bechtolsheim, endorsed Geneseo in a presentation at the show.

"From the standpoint of accelerators, the broadest market potential is ultimately going to be PCI slots," Bechtolsheim said. "This an extension to existing PCI express. This is very important, given the breadth of adoption of PCI Express in the industry."

Another fan is Simon McIntosh-Smith, vice president of applications at ClearSpeed, which builds calculation accelerators. ClearSpeed is a Torrenza partner, but software support built into Geneseo will give it at least one advantage, he said at the presentation.

"For us a lot of the excitement is not about raw bandwidth and latency, it's really about the enabling of software on top of that," McIntosh-Smith said. "We'd like to make acceleration as easy to get at and program as possible. There's some innovation in Geneseo that's going to make that much more possible."

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