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AR# 5063

Description

Keywords: STARTUP, STARTBUF, BitGen, Synopsys, configure, StartupClk

Urgency: Hot

General Description:I am using Synopsys FPGA or Design Compiler with the M1.5 software. My design has a STARTUP or STARTBUF block instantiated into it, and the CLK or CLKIN input port to the STARTUP/STARTBUF is left unconnected; if I use the default M1 options, the FPGA does not configure properly.

Solution

This problem was introduced to M1.5 with a change in the default options for BitGen. For more information, please see (Xilinx Solution 4681). One option that changed was if a signal is connected to the CLK/CLKIN pin of the STARTUP/STARTBUF component, the device startup clock signal connected to this port will, by default, be used to initialize the FPGA.

However, using FPGA or Design Compiler, any input ports that are not connected to components are grounded by default. If a STARTUP/STARTBUF component is instantiated and the CLK/CLKIN port is unconnected, Synopsys will connect a ground signal to the port. This causes the FPGA to never "wake up" after configurations unless one of the following things happen:

1. The "StartupClk" option in BitGen is changed to Cclk:

bitgen -g StartupClk:Cclk <design>.ncd

This can also be done from the "Design Manager Configuration Options" template.

-- and/or --

2. The Synopsys script is modified to leave the port unconnected by doing the following:

a. Connect a net to the CLK/CLKIN port of the instantiated STARTUP/STARTBUF component in the design. This can either be described into the HDL code or done from your Synopsys script.

b. Compile the design normally, leaving this "dummy" signal connected to the STARTUP/STARTBUF.

c. Before writing out the implementation netlist (.sxnf or .sedif), perform a disconnect_net -all on the "dummy" net.

This will leave the port unconnected and the design will implement properly.