Today I was reading this week’s issue of Time Magazine while eating lunch in my secret fish-and-chips restaurant at an undisclosed location in Milpitas, California when I chanced upon a fascinating article about RIM, maker of the BlackBerry. The article’s … Continue reading →

In a complete overhaul of its FPGA design tools, Xilinx has just announced the Vivado Design Suite for its current-generation 7 Series FPGAs (including the Zynq-7000 Extensible Processing Platform) and future FPGA generations. With this design-tool release, Xilinx is acknowledging … Continue reading →

Setup for this video is pretty complicated so bear with me. The following video shows a Xilinx test chip with “7 Series GTX” transceivers pumping 26Gbps data over four channels through a stand-alone Luxtera “silicon optics” multichannel transceiver module. The … Continue reading →

I’ve always wanted to use the British English word “bespoke” in a blog and Cadence Group Director of Product Marketing for the System Development Suite Frank Schirrmeister has now given me that opportunity with his EDPS forecast on system-level EDA … Continue reading →

Two weeks ago, I moderated a 3D IC panel at the 9th International SoC Conference in Newport Beach, California. Last week, I wrote about the first two speakers. (See “3D Thursday: Where can you start with 3D?” and “3D Thursday: … Continue reading →

Last week at the 9th International SoC Conference in Newport Beach, I moderated a 3D IC panel that did a great job of exploring today’s state of the art for 3D IC development. I will be blogging the presentations made … Continue reading →

I met with Nandan Nayampally, Director of CPU Product Marketing for the Processor Division at ARM, at ARM TechCon 2011 last week and asked him for a short-form way of understanding the three major classes of 32-bit ARM Cortex processor … Continue reading →

OK, well that didn’t take very long at all. Minutes after ARM rolled out the 64-bit ARMv8 architecture announcement at ARM TechCon 2011, AMCC announced that it will be producing a multicore server chip dubbed “X-Gene” based on the new … Continue reading →

It’s been more than a year and a half since Xilinx first started to talk publicly about the fusion of processors and FPGAs—a product now known as Zynq. It seemed inevitable that Altera would eventually counter with a competing product … Continue reading →

I recently ran into this unusual article written by Joe Fjelstad and published on the Global SMT & Packaging Web site. The article discusses the possibility of building hybrid chips using a brick-and-mortar approach as advocated by a joint paper … Continue reading →

Robert S Grimes’ recently published development story is a good case study in System Realization and SoC Realization. Grimes developed a quad laser control system for a high-power military application and the article he’s published in EETimes—Designing with core-based high-density … Continue reading →

Over the past week, I’ve published a 6-part series of blog posts based on the Xilinx White Paper describing how the company developed the low-power aspects of its Series-7 FPGA families. The lessons apply to any team developing ASICs and … Continue reading →

Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading →

Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading →

Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading →

Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading →

Xilinx wants you to have a quick course in 28nm low-power SoC design… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let that title fool you. This … Continue reading →

Want an advanced course in low-power design alternatives for advanced-process SoC design? Xilinx wants you to have one… for free. The company recently published a White Paper titled “Lowering Power at 28nm with Xilinx 7 Series FPGAs” but don’t let … Continue reading →

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About the author:

Steve Leibson has appeared on television with Leonard Nimoy (Star Trek's Mr. Spock), however he's not a TV star (although he's always open to offers). He is the Cadence EDA360 Evangelist and a Marketing Director at Cadence Design Systems, the leading EDA vendor for system and chip-level design tools, design IP and IP design platforms, and verification IP. Steve’s written some of the key books about IP-based SOC design including “Designing SOCs with Configured Cores,” published in 2006 and “Engineering the Complex SOC,” co-authored with Dr. Chris Rowen and published in 2004. An experienced design engineer, Steve has been evangelizing advanced, IP-centric SOC design since 2001.