News

PacketArc IP is used to demonstrate multi-threaded simulation speed-up

The impressive open-source simulator Verilator now in version 4 supports multi-threading. The developer Wilson Snyder needed a large real-world design to benchmark the performance, and we were happy to give him an IP core to play with.
And it is looking good! See slides 17 and forward in the presentation from ORConf 2018:Verilator 4.0: Open Simulation Goes Multithreaded

2017 August

Design win: High-performance L3/MPLS router

We are thrilled to announce that in our largest deal to date our IP will be used to produce a high-performance L3/MPLS router ASIC with multiple 100G Ethernet ports!