PCI-SIG, the organization responsible for the PCI Express (PCIe) standard input/output (I/O) technology, today announced the approval of 16 gigatransfers per second (GT/s) as the bit rate for the next generation of PCIe architecture, PCIe 4.0.

This decision comes after the PCI-SIG completed a feasibility study on scaling the PCIe interconnect bandwidth to meet the demands of a variety of computing markets.

After technical analysis, the PCI-SIG has determined that 16 GT/s on copper, which will double the bandwidth over the PCIe 3.0 specification, is technically feasible at approximately PCIe 3.0 power levels. The data also confirms that a 16GT/s interconnect can be manufactured in mainstream silicon process technology and can be deployed with existing low-cost materials and infrastructure, while maintaining compatibility with previous generations of PCIe architecture. In addition, the PCI-SIG will investigate advancements in active and idle power optimizations, key issues facing the industry.

"Experts in the PCIe Electrical Workgroup carefully analyzed a number of target bit rates for the next generation of PCIe architecture, taking into consideration several key factors, including our ability to continue using low-cost materials. We have concluded that 16 GT/s is a feasible technical solution that satisfies our member companies? requirements," said Al Yanes, PCI-SIG chairman. "While the preliminary analysis is encouraging, a lot more challenging work lies ahead in developing the specifications. The PCI-SIG looks forward to providing our members with a specification that not only satisfies their high performance requirements but also meets their power, cost and compatibility goals."

The final PCIe 4.0 specifications, including form factor specification updates, are expected to be available sometime in the 2014-2015 timeframe.