DesignCon SMEs: Tough Path to 25G+ High-Speed Signals

I asked five subject-matter experts (SMEs) -- some of my go-to engineers in high-speed design -- what are the big issues to watch for at DesignCon this month. They told me it ain’t gonna be easy, but a new generation of designs with serial electrical signals zipping along at 25 Gbits/second is being born--and there’s hope for an even faster generation beyond it.

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There’s a hornet’s nest of signaling issues handling such designs in a reliable way, they said. The good news is many of the tricks engineers will need will be described here for the first time.

“The biggest issues right now are around how we reliably get to 25G signals for 100 and 400G Ethernet, said Scott McMorrow, president and founder of Teraspeed Consulting Group.

“There are significant numbers of people having trouble making 10G work reliably, so the leap to 25G is pretty significant,” said McMorrow, a DesignCon veteran who works on an average of 20 projects a year. “The issues are all around signal loss, crosstalk and noise—it’s not well covered by the standards,” he said.

The issues crop up in places as seemingly mundane as a connector that may carry a signal just fine, but not pass it on through a pc board via to a trace as well as it should. “Some connector vendors do a good job of understanding and controlling crosstalk through the whole system, others don’t,” McMorrow said.

Chip packages are another culprit when the same tight arrays of balls and bumps that handled 10G signals are expected to carry 25G links, despite the fact that crosstalk scales linearly with frequency. “You have to find 2.5 times more margin or 9-10 dB—it’s possible but not without spending a lot of time understanding the problem,” he said.

At the end of the day, “engineers actually have to engineer these systems now, you can’t just thrown down chips and have it all magically work,” he said.

Secrets of the glass

Another DesignCon veteran and high-speed design consultant, Lee Ritchey of Speeding Edge (Glen Ellen, Calif.), will disclose fresh techniques for handling losses caused by the woven glass in pc boards. “I found a way to solve the skew problem the glass introduces in two sides of a differential pair,” said Ritchey.

A comparison of an open and uniformly spread glass weave with a 3.5 mil wire for contrast.

“A bunch of tricks have been proposed, but I have one that doesn’t cost any money, so I expect it will get some attention,” he said. “I’ve been using it quite awhile, and have chosen not to share it with the rest of the world, but I am doing it now because I have heard so many weird things proposed that I decided I am going to speak up,” he added.

Ritchey is humble about his secret trick, noting others may have come up with their own workarounds, maybe leveraging the way DDR3 DRAMs automatically realign signal edges. “It would be nice to say we had a brilliant flash [with our technique], but the reality is we stumbled on it” after noticing how cellphones handle non-uniformity in laser drilled pc board vias, he said.

The effects of woven glass are increasingly a focal point for high-speed engineers. “We’ve tinkered around a lot with the resins in pc boards, and we are tinkering more with the glass now,” he said.

Ritchey recalls first coming to DesignCon about 1994 when people were working on 10 Mbit/s Ethernet products, wondering how they would ever get to 100M. Then he worked at startup Procket that built a 350-pound system with 38 10G ports, and later at another startup that packed as many 10G ports into a 22-pound 1U pizza box.

“That’s still not making people happy--right now they are trying to do 100G,” he said. “This is really what DesignCon is all about,” he added.DesignCon resources:DesignCon Schedule Builder (program)

Rick: the solution for handling losses caused by the woven glass PCB's is one part of the solution -I would imagine it ensures a more uniform dielectric field alleviating the need for more expensive dielectrics. The other that is mentioned hits home to me -package is going to be a big issue. In addition to routing challenges for the exploding number of connections, minimizing reflections at the package-to-board interface is indeed a problem at higher signaling rates.
MP Divakar

NESA has worked on high speed serial problems for a long time (see EE Times, 8/17/1998). Some of the major problems for the IEEE 25/100 Gbps 802.3bj committee are the important design concepts to specify and how they relate to the IEEE 10/40 Gbps 802.3ae technology. From a physical designers point of view, a major problem is where and how to find and accumulate the technical application notes and form a coherent end to end reliable design. Few tools are appropriate for this level of design. A deep appreciation of advanced fundamentals as they relate to PCB materials, microwave and digital interconnect theory and design are required. Consultants such as myself and Scott McMorrow can fill the gap where there isn't a large and experienced SI staff.
Sincerely,
Ed Sayre, CTO
North East Systems Associates, Inc. (NESA)