FSBL generated image size too big

We regenerated the FPGA build using Vivado 2015.2.1, ported the hardware into the SDK, following the instructions on the ADC wiki page (link).

We're having a problem where the FSBL that is generated is much bigger than the FSBL from the reference image that we downloaded, where the reference fsbl.elf is 240K (found in bootgen_sysfiles.tgz), and the file that we generated from the SDK is 417K.

- When we boot using a BOOT.bin generated with our bitstream file, our fsbl.elf, and the reference u-boot.elf, we get video distortion on the monitor.

- When we boot using a BOOT.bin generated with our bitstream file, the reference fsbl.elf, and the reference u-boot.elf, it works as expected.

The extra large fsbl.elf is generated using both Linux and Windows tools.

Thanks for your quick reply, Lars. Yeah, that fixed the size discrepancy, which I'm ashamed to say I should have known.

But even with the release build of the FSBL, the video distortion remains. We've been through permutations of FSBL, bitstream, u-boot, device tree, and kernel configuration between the reference build and our build, and the video distortion only occurs when we're using our new FSBL, which we need to be able to change.

I've attached a picture of the video distortion, which might shed some light on the problem.

The description for this field is "Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence". Your value is 0x105 where as my value is 0x16d. I'm not sure if this actually makes a difference, but it might.

Since our testing shows that only the addition of our fsbl.elf causes the problem, Is it possible to get a copy of your FSBL project files generated from Vivado that we can diff against? Or conversely, are there any other FSBL files I can send to you for comparison?

Attachments

Okay, our build differs from yours in that you have the axivdma_v5_1 libsrc files, and we don't. That looks like a strong possibility. Clearly there's a setting that we don't have configured properly. That's what I'll look at next.

Thanks for your help with this. My coworker (who is the FPGA guy) and I will be out of the office until the end of the year, but when I get back, I'll post my results.

Lars, after comparing our FSBL files with yours, we didn't have vdma, iic, and spi files in our build. Those components were also not present in the system.hdf file. My coworker cleaned and rebuilt his FPGA project from scratch, and after that, all the files were there, and it works fine. We're not sure why they weren't present the first time, but they are there now.