Slideshow: Samsung cagey on smartphone SoC at ISSCC

Samsung’s answers were actually very revealing, according to David Kanter, a blogger and analyst of processor technology. “The fact that the switching is controlled at the software level tells you it’s slow,” he said.

Kanter suggested the ARM big.little approach pushes off to software developers a significant piece of the complexity of power management—deciding which applications to run where and when.

There’s always plenty of room to read between the lines at ISSCC, in part because presentations are carefully screened for what they do and do not share. For example, Shin’s talk described two quad-core ARM processor complexes, but he did not specifically define them as A15s and A7s.

I asked him before his talk if it was about the Exynos 5 Octa, the ARM big.little chip Samsung announced at the Consumer Electronics Show in January. Shin said he was not allowed to talk about the SoC in which the processor arrays appeared. He was not even able to acknowledge the big.little concept in his talk, he said.

“I am just a processor guy,” he told me.

Afterwards I joked with him about his grilling from competitors. “I have known some of them awhile, some of them are our customers,” he told me, in what I took as a reference to the Apple engineer.

Samsung’s foils (below) described its Exynos 5 Octa in a very minimalist fashion.

Click on image to enlarge.

The quad A15 block takes up much more room than the quad A7 in the Exynos 5 Octa.

Click on image to enlarge.

Samsung may have set a new standard for generic block diagrams.

Click on image to enlarge.

Samsung provided few details on the Exynos 5 Octa compared to summaries of other ISSCC designs.

A great question. And I must say, when I attend ISSCC and other such conferences, I am always struck with how much technical detail engineers are willing/able to share with a room fully of other engineers, some of whom happen to work for their fiercest rivals. It's got to be a delicate balance. I must also say that I too have observed presentations by Samsung where the presenter did not appear to want to answer detailed questions. Not faulting Samsung for this, but perhaps it is part of that particular company's policy.

I remember this presentation. I was there. Yongmin also talked about body biasing both forward and reverse to boost performance and reduce leakage respectively. So I got to the mic and asked him if they applied body biasing on both pmos and nmos devices or only one of them. He refused to answer. I asked him if he could at least shed some light on how much leakage decrease or what performance boost he got. Again, he refused to answer. Mr Shin was right on one point this is a circuits conference. A conference which is place where you come to share your technologies and ideas and help advance the field. This paper should not have been selected. You cannot mention you tried various power saving schemes without a mention of what the benefit was. The presentation seemed more like a press release rather than a conference presentation. ISSCC should send a clear message. If you want to present here - you have to share information. You cannot use it as a platform to only advertize your wares.
In Mr. Shin's defense, he was probably forced to not reveal anything.

Read Anand's article about the Exynos Octa: http://www.anandtech.com/show/6768/samsung-details-exynos-5-octa-architecture-power-at-isscc-13
Around 5W max power for quad 1.8GHz A15 cores is actually amazingly low. That's just 1.25W per core.
If anything, the large difference in power between A7 and A15 means that big.LITTLE has achieved its goal. Most of the time you will be running on the A7 cores, thus using only a fraction of the power (about 0.5W for 4 1.2GHz A7 cores according to the graph).