The multiple on-chip signature checking architecture proposed by the authors previously is an effective BIST architecture for testing the functional units in modern VLSI circuits. It is characterized by low aliasing, low area overhead and low testing time. However, a straight forward application of this architecture in testing the embedded RAMs will result in excessive area overheads. In this paper the authors propose a scheme to apply this architecture to embedded static RAMs with no significant increase in area. The scheme is applicable to testing chips that have multiple embedded RAMs of various sizes (e.g., ASIC chips in telecommunication applications)