In Atmel PDF doc11057 (Sam3X reference) page 1391 (Para 46.2 DC characteristics) , is Rpulldown part of the internal circuitry, and does it only refer to TST, ERASE and JTAGSEL select pins ?If so, is there a reference to the internal pulldown resistance for the general purpose I/O pins ?

What you might have overseen: On the same page of the data sheet you mentioned, the currents for the GPIO inputs with non activated resistors for pull-up/down are specified as Leakage current in the range of 2 to 30nA. This should answer your question for the load.In case of activated resistors - for the Due I expect only the pullup mode to be implemented, although the specification for the Arm obviously also allows a pulldown mode >edit: - pulldown only for TST,ERASE and JTAGSEL<.