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Verifying ESD Fixes Faster with Incremental Analysis

The author of this article, Dündar Dumlugöl, is CEO of Magwel. He has 25 years of experience in EDA managing the development of leading products used for circuit simulation and high-level system design.

Every designer knows how tedious it can be to shuttle back and forth between their layout tool and analysis tools. Every time an error or rule violation is found, you need to open up the design in the editor and make changes, save, export and re-run the analysis. This is especially true with ESD tools, which are fine for analysis, but often leave designers running blind when it comes to resolving errors. As a result, designers have no recourse other than to iterate back to layout to fix issues. Magwel’s ESDi offers refreshing features for locating the source of an error and, even more importantly, for making changes and testing fixes without leaving the ESD tool itself.

Magwel’s EDSi offers comprehensive and high speed ESD simulation on every pad pair. It takes into consideration competitive triggering so that it more accurately evaluates voltages and currents during discharge events. It also uses I/V curves that can be derived from TLP measurement data or that are user created. Regardless, device model I/V curves can include snapback, which is used to determine whether triggering occurs and the actual voltage after the triggering threshold is reached.

Another important benefit of the tool is its extremely high usability. This starts with ease of set up. For instance, ESD devices and their terminals can be automatically tagged in the layout. Users can also control whether all the pad pairs are run or if only a subset are to be simulated. Parallel processing speeds up the final results.

Another aspect of ESDi’s excellent usability is the error reporting. All test results are provided in a report grouped by category and sortable on any field, right inside the tool. Violations are highlighted for easy identification. By clicking on the reported error, the user can jump to the layout with the relevant geometries highlighted for easy viewing. In addition, EDSi can generate a graph diagram of all the devices and paths involved in the discharge event. Included in this are the net resistances, as well as device voltages and currents.

To illustrate the value of having editing capability in the analysis tool we will use a case where there is an HBM simulation error involving a primary and secondary ESD device with a poly resistor to help primary device triggering and limit current flow. After finding the error, the next step is to modify the resistor to alter the resistance, then perform re-simulation to see if the problem is fixed. This is a tricky modification because too high a resistor value can affect input pin behavior. So, the goal is to add just enough resistance to allow the protection to operate properly, but not to overdesign to the point where performance in operational mode is affected.

Figure 1 – Test circuit schematic with TLP models

Figure 2 – Test case in ESDi GUI

In this design, ESD device “Dev1” initially triggers first. However due to the low resistance of resistor “PolyR” of 3.3 Ohms, the primary device “esd3” never triggers. As a result, all of the current for the discharge event travels through Dev1 and the voltage drop across the device reaches 8V, which will lead to device burnout. After the initial simulation, the designer will want to change the area of the resistor to increase the resistance.

Figure 3 – Circuit with ESD violation

Inside of ESDi there is a suite of layout editing commands that allow the designer to modify the layout geometry. Using these commands, it is easy to change the width of the poly resistor and its contacts.

Once the geometry is changed, the ESD solver can be quickly rerun to perform an HBM simulation on the pad pair in question. With the changes that were made the new simulation results look much better. With the higher R value on PolyR, the primary device triggers, carrying the brunt of the current. Also, the voltage is clamped at a lower value, avoiding device burnout.

After debugging and experimentation, when optimal results have been obtained, the designer can move back to their layout tool and finalize the changes in the original design.

This is why customers say good things about ESDI for saving them considerable time and hassle by enabling them to make changes right in the analysis tool. For ESD integrity it is very important that designers and ESD experts have accurate, effective and easy to use tools. The earlier and more often ESD protection is reviewed, the lower the likelihood that an error or violation will make it through to silicon. Having editing built-in to ESDi makes the process more efficient and provides better results in the form of fewer design iterations and less rework.