Robert Swindells asked;
> How is the new interrupt code designed to be used on systems that have
> interrupt enables and masks split over multiple registers ?
Last night I wrote code for MPC83xx IPIC case as a brain storming
excercise. MPC IPC has 3 set of registers for 8 external source and
total 64 internal source. I approached with them looking at macppc
pic_heathrow.c;
struct ipic_ops {
struct pic_ops pic;
uint32_t pending_events_x; /* 8 external source */
uint32_t pending_events_l; /* 32 source 0..31 */
uint32_t pending_events_h; /* 32 source 32..63 */
uint32_t enable_mask_x;
uint32_t enable_mask_l;
uint32_t enable_mask_h;
}
As Matt mentions cascading interrupts, like for ones come thru GPIO,
can be hooked with an appropriate "slot" by having another xxx_ops
struct to make add_pic() call.
Toru Nishimura/ALKYL Technology