... S Programming for setup and control is accomplished using a 3-pin SPI-compatible serial interface. The AD6649 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent. PRODUCT HIGHLIGHTS 1. Integrated dual, 14-bit, 250 MSPS ADCs. ...

... VIN+ and VIN− should be matched, and the inputs should be differentially balanced. Input Common Mode The analog inputs of the AD6649 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that V 0 recommended for optimum performance. An on-board common-mode voltage reference is included in the design and is available from the VCM pin ...

... ADC. The output common-mode voltage of the ADA4930-2 is easily set with the VCM pin of the AD6649 (see Figure 27), and the driver can be configured in a Sallen-Key filter topology to provide band-limiting of the input signal. 15pF 200Ω ...

... Jitter, for more information about jitter performance as it relates to ADCs. POWER DISSIPATION AND STANDBY MODE As shown in Figure 37, the power dissipated by the AD6649 is proportional to its sample rate. The data in Figure 37 was taken using the same operating conditions as those used for the Typical Performance Characteristics ...

... VIN+ − VIN– >+0.875 Timing The AD6649 provides latched data with a pipeline delay input sample clock cycles, depending on the mode of operation. Data outputs are available one propagation delay (t rising edge of the clock signal. The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD6649 ...

... AD6649 ADC clock rate in hertz. CLK NCO SYNCHRONIZATION The AD6649 NCOs within a single part or across multiple parts can be synchronized using the external SYNC input. Bit 0 and Bit 1 of Register 0x58 allow the NCO to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written ...

... C23 0.9171314 FIR SYNCHRONIZATION The AD6649 filters within a single part or across multiple parts can be synchronized using the external SYNC input. The filters can be configured to be resynchronized on every SYNC signal or only on the first SYNC signal after the SPI control register is written. ...

... The final NCO provides a means to move this complex output signal away from dc so that a real output can be provided from the AD6649. The output NCO translates the output from frequency equal to the output frequency divided ...

... ADC clock cycles. An overrange at the input is indicated by this bit 7 clock cycles after it occurs. GAIN SWITCHING The AD6649 includes circuitry that is useful in applications either where large dynamic ranges exist or where gain ranging amplifiers are employed. This circuitry allows digital thresholds to be set such that an upper threshold and a lower threshold can be programmed ...

... Bits[5:2] of Register 0x40 (values between 0 and 13 are valid for k; programming provides the same result as programming 13 the AD6649 ADC sample rate in hertz. CLK DC Correction Readback The current dc correction value can be read back in Register 0x41 and Register 0x42 for each channel. The dc correction value is a 16-bit value that can span the entire input range of the ADC ...

... ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD6649 to prevent these signals from transi- tioning at the converter inputs during critical sampling periods. Rev Page ...

... SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD6649 part-specific features are described in the Memory Map Register Description section. Table 14. Features Accessible Using the SPI Feature Name Mode ...

... Address 0x18). If the entire address location is open (for example, Address 0x13), this address location should not be written. Default Values After the AD6649 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 15. Logic Levels An explanation of logic level terminology follows: • ...

... Open Open (global) 0x0B Clock divide Open Open (global) Bit 5 Bit 4 Bit 3 Bit 2 Soft reset 1 1 Soft reset 8-bit chip ID[7:0] (AD6649 = 0xA1) (default) Speed grade ID Open Open 00 = 250 MSPS Open Open Open Open Open Open Open Open External Open Open Open ...

... Bits[5:2] of Register 0x40 (values between 0 and 13 are valid for k; programming provides the same result as programming 13 the AD6649 ADC sample rate in hertz. CLK Bit 1—DC Correction Enable Setting this bit high causes the output of the dc measurement block to be summed with the data in the signal path to remove the dc offset from the signal path ...

... AD6649 NCO/FIR SYNC Pin Control (Register 0x59) Bits[7:2]—Reserved Bit 1—SYNC Pin Sensitivity If Bit 1 is set the SYNC input responds to a level. If this bit is set low, the SYNC input responds to the edge (rising or falling) set in Bit 0 of Address 0x59. Bit 0—SYNC Pin Edge Sensitivity If Bit 1 is set high, setting Bit causes the SYNC input to respond to a falling edge ...

... The VCM pin should be decoupled to ground with a 0.1 μF capacitor, as shown in Figure 28. For optimal channel-to-channel isolation Ω resistor should be included between the AD6649 VCM pin and the Channel A analog input network connection and between the AD6649 VCM pin and the Channel B analog input network connection ...