Abstract

We review the concept of the ‘chaos computing’ paradigm, which exploits the controlled richness of nonlinear dynamics to obtain flexible reconfigurable hardware. We demonstrate the idea with specific schemes and verify the schemes through proof-of-principle experiments.

Keywords:

1. Introduction

Recently, there has been a new theoretical direction in harnessing the richness of nonlinear dynamics, namely the exploitation of chaos to do flexible computations (Sinha & Ditto 1998, 1999). The aim is to use a single chaotic element to emulate different logic gates and perform different arithmetic tasks, and further have the ability to switch easily between the different operational roles. Such a computing unit may then allow a more dynamic computer architecture and serve as ingredients of a general purpose device more flexible than statically wired hardware.

A system is capable of universal general purpose computing if it can emulate all logic gates. The necessary and sufficient components of computer architecture today are the logical AND, OR, NOT and XOR (Exclusive OR) operations, from which we can directly obtain basic operations such as bit-by-bit addition and memory (Bartee 1991; Mano 1993). We first recall the theoretical scheme for flexible implementation of all these fundamental logical operations using low-dimensional chaos (Munakata et al. 2002; Sinha et al. 2002a,b), and then we give the specific realization of the theory in discrete- and continuous-time chaotic circuits (Murali et al. 2005).

2. Concept

We wish to use the rich temporal patterns embedded in a nonlinear time-series in a controlled manner to obtain a computing medium that is flexible and reconfigurable.

Now, we outline a theoretical scheme for obtaining all basic logic gates with a single chaotic system. Consider a chaotic element (our chaotic chip or chaotic processor) whose state is represented by a value x. In our scheme, all the basic logic gate operations (AND, OR, NOT and XOR) involve the following steps.

Inputswhere x0 is the initial state of the system, and X=0 when I=0 and X=δ (where δ is a positive constant) when I=1.

Chaotic update, i.e. x→f(x) where f(x) is a chaotic function.

Threshold mechanism to obtain output Zwhere x* is the threshold. This is interpreted as logic output 0 if Z=0, and logic output 1 if Z=δ.Since the system is chaotic, in order to specify the initial x0 accurately one needs a controlling mechanism. Here, we will employ a threshold controller to set the initial x0. Thus, in this example we will use the clipping action of the threshold controller to achieve the initialization and subsequently to obtain the output as well.

Note that, in our implementation, we demand that the input and output have equivalent definitions (i.e. 1 unit is the same quantity for input and output), as well as among various logical operations. This requires that constant δ assumes the same value throughout a network, and this will allow the output of one gate element to easily couple to another gate element as input, so that gates can be ‘wired’ directly into gate arrays implementing compounded logic operations.

In order to obtain all the desired input–output responses of the different gates, we need to satisfy the conditions enumerated in table 1 simultaneously. Thus, given a dynamics f(x) corresponding to the physical device in actual implementation, one must find values of threshold and initial state satisfying the conditions derived from the truth table to be implemented. For instance, the exact solutions of the initial x0 and threshold x* which satisfy the conditions in table 1 whenwith parameter a=1, and the constant δ=1/4 (common to both input and output and to all logical gates) are as follows: x0=0 and x*=3/4 for the AND operation; x0=1/8 and x*=11/16 for the OR operation; x*=1/4 and x*=3/4 for the XOR operation; x0=1/2 and x*=3/4 for the NOT operation.

Necessary and sufficient conditions to be satisfied simultaneously by the nonlinear dynamical element, in order to be capable of flexibly implementing the logical operations AND, OR, XOR and NOT with the same computing module.

Contrast our use of chaotic elements with the possible use of periodic elements on one hand, and random elements on the other. It is not possible to extract all the different logic responses from the same element in the case of periodic components, as the temporal patterns are inherently very limited. So the periodic elements do not offer much flexibility or versatility. Random elements on the other hand have many different temporal sequences. But they are not deterministic and so one cannot use them to design components. Only chaotic dynamics enjoys both richness of temporal behaviour as well as determinism. Here, we have shown how one can select out temporal responses corresponding to different logic gate patterns from such dynamics, and this ability allows us to construct flexible hardware.

However, note that, while nonlinearity is absolutely necessary for implementing all the logic gates, chaos may not always be necessary. In the representative example of the logistic map presented here, solutions for all the gates exist only at the fully chaotic limit of the logistic map. But the degree of nonlinearity necessary for obtaining all the desired logic responses will depend on the system at hand and on the specific scheme employed to obtain the input–output mapping. It may be the case that certain nonlinear systems will allow a wide range of logic responses without actually being chaotic.

3. Proof-of-principle experiments

(a) Discrete time nonlinear system

Here, we will present an implementation of the theory discussed in §2, and we will verify that the theoretical solutions are indeed realizable in electronic circuits (Murali et al. 2005). We use a threshold controller with the threshold level set by voltage level x0. The logic level input I=I1+I2 is added to x0 and used as the new input to the logistic map iteration to generate xn+1. This implements step 1 of the scheme. By using another threshold reference level voltage signal x*, the signal difference between xn+1 and x* is monitored as the logic level output. This constitutes the third (and final) step of the scheme.

In figure 1a the circuit realization of the chaotic logistic map is depicted. In the circuit implementation, xn−1, xn and xn+1 denote voltages normalized by 10 V as the unit. An analogue multiplier IC AD633 is used as a squarer and it produces the output voltage of /10 V for the given xn as the input. By using a suitable scale changer, summing amplifier and an inverter, the voltage proportional to xn+1 is available at the output of op-amp (OA3) circuit. A variable resistor VR1 is employed to control the parameter a from 0 to 1 in the logistic map. The output voltage of OA3 becomes a new input voltage to the multiplier AD633 after passing through two sample-and-hold circuits (SH1 and SH2), provided the terminals A and B are connected together. The sample-and-hold circuits are constructed with LF398 or ADG412 ICs and they are triggered by suitable delayed timing pulses T1 and T2 (shown in figure 1b). The timing pulses are usually generated from the clock generator providing a delay of feedback, and the delay is essential for obtaining the solution xn+1 of the logistic map. Usually, a clock rate of either 5 or 10 kHz is used.

Circuit implementation of (a) the logistic map module and (b) the timing pulses T1 and T2 generated from the clock generator providing a delay of feedback. The output voltage of OA3 becomes a new input voltage to the multiplier AD633 after passing through two sample-and-hold circuits, provided the terminals A and B are connected together. The sample-and-hold circuits are constructed with LF398 or ADG412 ICs and they are triggered by T1 and T2. See text for more details.

If the terminals A and B in figure 1a are connected to the respective terminals of the circuit of figure 2, we have the general circuit configuration for the flexible logic gate implementation. In the circuit, all input and output variables are again normalized by 10 V. The control circuit (dotted line box) is the threshold control unit which generates the signal x0 at terminal C corresponding to the input signal xn+1 at A under the threshold control voltage V0. The input voltage I=0, 0.25 or 0.5 V corresponding to different logic gates. Here x* is another reference threshold voltage being used to produce the difference voltage δ from the xn+1 signal. This δ and the input signal I determine the logic condition of the different gates. Here op-amps OA4 to OA9 are implemented with μA741 or AD712. The resistor R=100 kΩ and diode D=IN4148 or IN34A.

Circuit implementation of the flexible gates module. See text for details.

Figure 3 shows the timing sequences of the implementation of two representative gates. The output waveforms are generated with both PSPICE circuit simulations and also through hardware implementations. Figure 4 shows the schematic of the circuit implementing the half adder and figure 5 shows its corresponding timing sequences. These waveforms are again straightforwardly obtained in both simulation and experiments.

(a) Timing sequences of the OR gate implementation (i) first input I1, (ii) second input I2, (iii) state after chaotic update f(x) and (iv) output obtained by thresholding; and (b) timing sequences of the NOT gate implementation (i) input I, (ii) state after chaotic update f(x) and (iii) output obtained by thresholding. (Accuracy within 5 mV.)

Timing sequences of the half adder implemented by the schematic circuit in figure 4. (Accuracy within 5 mV.)

(b) Continuous-time nonlinear system

We now present a somewhat different scheme for obtaining logic responses from a continuous-time nonlinear system. Our processor is now a continuous-time system described by the evolution equation , where x= are the state variables and F is a nonlinear function. In this system we choose a variable, say x1, to be thresholded. Whenever the value of this variable exceeds a threshold E it resets to E, i.e. when x1>E then (and only then) x1=E.

Now the basic logic operation on a pair of inputs I1, I2 in this scheme simply involves the setting of an input-dependent threshold, namely the threshold voltage , where VC is the dynamic control signal determining the functionality of the processor. By switching the value of VC one can switch the logic operation being performed. Again I1/2 has value 0 when the logic input is 0, and has value Vin when the logic input is 1. Thus, the threshold E is equal to VC when the logic inputs are (0, 0), VC+Vin when the logic inputs are (0, 1) or (1, 0) and VC+2 Vin when the logic inputs are (1, 1). The output is interpreted as logic output 0 if xi<E, i.e. the excess above threshold V0=0. The logic output is 1 if x1>E, and the excess above threshold . The schematic of this method is displayed in figure 6.

when the input set is (0, 0), the output is 1, which implies that, for threshold , output ,

when the input set is (0, 1) or (1, 0), the output is 0, which implies that, for threshold , so that output V0=0, and

when the input set is (1, 1), the output is 0, which implies that, for threshold , x1<E so that output V0=0.

For a NAND gate () the following must hold true:

when the input set is (0, 0), the output is 1, which implies that, for threshold , output ,

when the input set is (0, 1) or (1, 0), the output is 1, which implies that, for threshold , output , and

when the input set is (1, 1), the output is 0, which implies that, for threshold , x1<E so that output V0=0.

In order to design a dynamic NOR/NAND gate, one has to find values of VC that will satisfy all the above input–output associations in a robust and consistent manner.

In our specific implementation, as the computing element, we consider a realization of the double scroll chaotic Chua's attractor given by the following set of (rescaled) three coupled ODEs(3.1)(3.2)(3.3)where α=10 and β=14.87 and the piecewise linear function with a=−1.27 and b=−0.68. The corresponding circuit component values are: L=18 mH, R=1710 Ω, C1=10 nF, C2=100 nF, R1=220 Ω, R2=220 Ω, R3=2.2 kΩ, R4=22 kΩ, R5=22 kΩ, R3=3.3 kΩ, D=IN4148, B1,B2=Buffers, OA1–OA3: op-amp μA741. Note that the circuit we use is the ring structure configuration of the classic Chua's circuit (Dmitriev et al. 2001).

We use the x1 variable, corresponding to voltage V1 across capacitor C1 for thresholding. In the experiment, we implement minimal thresholding (shown in the dotted box in figure 8). Instead of demanding that the x1 variable be reset to E if it exceeds E we only demand this in equation (3.2). This has very easy implementation, as it avoids modifying the value of x1 in the nonlinear element g(x1), which is harder to do. So then all we need to do is to implement instead of equation (3.2), when , and there is no controlling action if . In the circuit, the voltage VT corresponds to E (Murali et al. 2003).

Symbols for NOR, NAND and dynamic-NOR/NAND logic gates. The dynamic control signal VC determines the logic operation for the D-NOR/NAND logic gate.

In the representative example shown in figure 9, Vin=2 V. The NOR gate is realized around VC=0 V. At this value of control signal, we have the following: for input (0, 0) the threshold level E=0, which yields V0∼2 V; for inputs (1, 0) or (0, 1) the threshold level E=2 V, which yields V0∼0 V; and for input (1, 1) the threshold level E=4 V, which yields that V0=0 as the threshold is beyond the bounds of the chaotic attractor (see figure 9 for timing sequences). The NAND gate is realized around VC=−2 V. The control signal yields the following: for input (0, 0) the threshold level E=−2 V, which yields V0∼2 V; for inputs (1, 0) or (0, 1) the threshold level E=2 V, which yields V0∼2 V; and for input (1, 1) the threshold level E=4 V, which yields V0=0 (see figure 9 for timing sequences).

4. Ongoing VLSI implementation

We are currently developing a VLSI implementation of chaotic computing in a demonstration integrated circuit chip. The demonstration chip has a parallel read–write interface to communicate with a microcontroller, with standard logic gates. The read–write interface responds to a range of addresses to give access to internal registers, and the internal registers will interface to the demonstration chaotic computing circuits.

For the demonstration, we selected circuits that were based upon the known experimental discrete component implementations and, as such, the circuits are larger than is necessary in this first generation of chip. Currently, the TSMC 0.18 μm process is the IC technology chosen for the development. This process was chosen to demonstrate that the chaotic elements work in smaller geometries, and the extra metal layers in this process will provide a margin of safety for any routing issues that might develop.

For our proof-of-concept on the VLSI chip, a small ALU (arithmetic logic unit) with three switchable functions, two arithmetic functions (adder, multiplier, divider, barrel shifter or others) and one function of scratchpad memory is being implemented. The ALU switches between at least two arithmetic functions and a completely different function like a small FIFO (first-in, first-out memory buffer). This experiment takes a significant step towards showing the possibilities for future configurable computing. The three functions are combined into a single logic array controlled through a microcontroller interface. The microcontroller can switch functions, and then write data to the interface, and read the results back from the interface. Figure 10 shows the simplified representation of this experiment (Ditto et al. 2006).

Simplified schematic of the proof of concept VLSI implementation of an ALU which can switch between at least two arithmetic functions and a completely different function such as a small FIFO (first-in, first-out memory buffer).

5. Conclusions

In summary, we have demonstrated the direct and flexible implementation of all the basic logic gates using nonlinear dynamics. The richness of the dynamics allows us to select out all the different gate responses from the same processor by simply setting suitable threshold levels. These threshold levels are known exactly from theory and thus available as a lookup table. Arrays of such logic gates can conceivably be programmed on the run (for instance, with a stream of threshold values being sent in by an external program) to be optimized for the task at hand. For instance, they may serve flexibly as an arithmetic processing unit or a unit of memory, and can be swapped, as the need demands, to be one or the other. Thus, architectures based on such logic implementations may serve as ingredients of a general purpose computing device more flexible than statically wired hardware.