The V612 Digital Receiver supports one or two plug-in X6-250M modules, each providing up to 128 independent channels of DDC and one spectrum analyzer embedded in a Xilinx Virtex 6 FPGA. It supports monitoring and/or recording of wide- or narrow-band spectra or channelized IF band data. The receiver supports contiguous recording at 2,000 MByte/s until running out of disk space.

Eight DDC banks, each supporting 16 channels, support monitoring of 128 DDC channels per single module. Each DDC bank can select its own ADC and decimation rate; each DDC channel has its own programmable tuner and programmable low-pass filtering supporting output bandwidth up-to 800 KHz. The data is packetized in VITA-49 format with accurate timestamps, synchronous to an external PPS signal. An embedded, digital power meter monitors the power (dBFS) of any ADC input, supporting analog gain control of optional, user-supplied external front-end devices.

The spectrum analyzer, which supports windowing, calculates the wide-band spectrum of raw ADC data or the narrow-band spectrum of the cooked DDC output data at a programmable update rate. A programmable peak hold feature may be enabled to latch transient activity in the spectrum and the programmable threshold monitoring spectrum feature tracks spectral activities of up-to 512 bins.

A development kit is available to support creation of custom instrumentation. Users can insert custom-made VHDL cores into the supplied Framework to create advanced applications.