Universal Serial Bus 3.0 and 2.0 Specifications

USB 3.0

USB 3.0 internal connector and cable specification >: Describes the internal cable interface for USB 3.0 connections in a desktop, focusing on the electrical and mechanical requirements of the connector, and cable assembly. The detailed daughter card or direct-cable implementation is out of the scope of this documentation.

This is a final version of the physical layer (PHY) interface for PCI Express* (PIPE) and USB 3.0 architectures specification that supports PCI Express* and USB 3.0 architectures. The PIPE specification describes a standardized interface between PHY and media access control (MAC) implementations for PCIe* Gen2 and USB 3.0. This document can be used for both discrete PHY parts and for PHYs that are foundry macrocell implementations.

This specification describes the register-level host controller interface for all USB speeds and includes a description of the hardware/software interface between the system software and the host controller hardware.

The specification is intended for hardware component designers, system builders, and device driver (software) developers. The reader is expected to be familiar with the current USB specification revisions.

USB 2.0

This is a final version of the physical layer (PHY) interface for PCI Express* (PIPE) and USB 3.0 architectures specification that supports PCI Express* and USB 3.0 architectures. The PIPE specification describes a standardized interface between PHY and MAC implementations for PCIe* Gen2 and USB 3.0. This document can be used for both discrete PHY parts and for PHYs that are foundry macrocell implementations.

This is a final version of the physical layer (PHY) interface for PCI Express* (PIPE) and USB 3.0 architectures specification that supports PCI Express* and USB 3.0 architectures. The PIPE specification describes a standardized interface between PHY and MAC implementations for PCIe* Gen2 and USB 3.0. This document can be used for both discrete PHY parts and for PHYs that are foundry macrocell implementations.

The EHCI compliance testing program measures an EHCI controller implementation for conformance to the EHCI specification and evaluates the functionality of the EHCI controller function of a USB 2.0 host controller. It does not evaluate the functionality of the USB companion controllers.