Do annular electrodes present a scalable PCM solution? - Part 1

The tie-up between IBM & S. K. Hynix in a phase change memory (PCM) development program made a great deal of sense [1]. For both, the annulus-shaped electrode was a common feature of some of their reported PCM development work and many believe that is the future direction for PCM device design.

More recently a possible new direction for PCM development using self-assembly techniques as a means of achieving sub-lithographic contact areas has been published from a group at KAIST, Korea [2]. In this paper, I will explore the scaling potential of the technique and link it to the annular electrode structure.

In light of the over promotion that has characterized recent PCM history, very sensibly the information shutters are up with respect to details of specific development plans and progress of the joint IBM-S. K. Hynix work; this will, perhaps, change when there is something significant to report. Even so, from published data it is possible by simple analysis to anticipate possible problem areas, especially with respect to the essential requirement of the sub-20-nm lithographic scaling of PCM.

What is the ring or annular electrode, sometimes described as a confining, U-cup, edge-contact or ring-type electrode? While there are a number of variants, fundamentally it is an electrode, circular or square, with the central region of one of the contacts removed so that current flows into the amorphous memory material only from the annular edges of the electrode (see figure 1). The IBM/Macronix device uses a hybrid mixture of electrode materials for which the core is a high-resistance conductor rather than a dielectric; their design also uses thermal barriers. The S. K. Hynix device uses a square edge contact and in fills the central part of the electrode with dielectric.

Figure 1: A ring or annular electrode is an electrode, circular or square, with the central region of one of the contacts removed so that current flows into the amorphous memory material only from the annular edges of the electrode (a). The IBM/Macronix design (b) uses a high-resistance conductor rather than a dielectric for the core. The S. K. Hynix device (c) features a square edge contact and infills the central part of the electrode with dielectric.

While this type of device structure adds complexity with associated yield and cost implications, it has the potential to offer a solution to at least one but perhaps not all of the fundamental problems for sub-20-nm lithography.

The annular-shaped electrode first appeared in 2008, when lithographic nodes were in the range of 60 nm to 100 nm. Using sub-lithographic techniques, it gave PCM device designers access to small-contact-area devices and reduced reset currents. As current density is now recognized as a serious problem, especially for both the PCM material and the memory-matrix-isolation devices, this type of structure is receiving new attention. The effectiveness of the annular structure in reducing the current density seen by the matrix isolation device rests in simple geometry. The annular electrode reduces the current density in the body of the electrode, Jb at the electrode-matrix isolation device interface (diode or transistor) by

Jb = Jc(ac/Ab) [1]

where Jc is the contact current density at the electrode-active material interface, ac is the area of contact between the amorphous material and the bottom electrode at the annulus, and Ab is the area of the body of the bottom electrode.

For followers of PCM developments, it is important to always clearly distinguish between reset current and reset current density. Both are important but current density is destructive and can lead to element separation and electro-migration. While the annular electrode reduces the electrode body current density Jb the value for Jc current density at the active material-electrode interface remains high and close to the value of that of the same diameter solid-electrode interface.

In most close-packed PCM array matrix designs, the electrode area Ab will also be the area of the matrix-isolating device. The attractive proposition of reducing this aspect of current density meant much store was placed on the promise of annular electrode based PCM devices, especially when proven by devices of that design fabricated at 60-nm-plus node lithography.

Resistion: Even if you create a PCM structure where the active material is in the form of an annulus, at sub-20nm dimensions I think the device will still have to rely on thermal cross coupling within the device structure to keep the reset current density at a level that will avoid the consequences of element separation and electro-migration. This will also mean that in a close packed matrix of those devices the device- to-device separation will be approximately the same as the the thermal coupling distant and you will suffer the consequences of thermal cross talk.
In one of my earlier PCM papers in EETimes I looked briefly at a structure similar to the one you are suggesting. I characterized it as a Wrap Around Link (WAL)PCM structure and attempted to relate its likely performance to that of flat link PCM structures. If I remember it was described in a Numonyx patent. I am not aware that anybody is working on constructing memory matrix using that structure. I suppose it is just possible that it could form part of the IBM-SKH program.