A.5. Timer signals

The tables below lists the interface signals for the timer
subsystem.

Table A.12. Timer

Name

Direction

Width

Description

TIMER0EXTIN

Input

1

Timer0 external input. The external clock.
This must be slower than half of the TMER0PCLK clock because it
is sampled by a double flip-flop and then goes through edge-detection
logic when the external inputs act as a clock.

TIMER1EXTIN

Input

1

Timer0 external input. The external clock,
must be slower than half of the TMER1PCLK clock because it is sampled
by a double flip-flop and then goes through edge-detection logic
when the external inputs act as a clock.

TIMER0PRIVMODEN

Input

1

Defines if the timer memory mapped registers
are writeable only by privileged access.

TIMER1PRIVMODEN

Input

1

Defines if the timer memory mapped registers
are writeable only by privileged access.