Toshiba to Build Fab for 3D NAND Flash

LONDON — Toshiba is preparing to increase NAND flash manufacturing capacity and move to vertically organized 3D NAND with the start of construction in August of the second phase of Fab 5 at its Yokkaichi facility in Mie, Japan.

The building work will be completed in summer of 2014, Toshiba said in a statement, noting that decisions on equipment investment have not yet been taken but "will reflect market trends." This is a way of saying that Toshiba will vary the amount and speed of its capital expenditure at the site depending on market conditions.

A year ago, in July 2012, Toshiba cut NAND flash production by 30 percent because it had concerns about market oversupply and downward pressure on chip prices. However, within six weeks some customers for NAND flash were complaining that they could not get enough of the memory chips. (See: NAND flash memory in short supply.) Prices for NAND chips, which had been in decline for many years, have picked up in 2013. A weaker yen also gives Toshiba an advantage over rivals such as Samsung and SK Hynix in South Korea.

The second phase of Fab 5 will be built with an emphasis on minimizing the impact on the environment. LED-based lighting and energy-saving production methods with waste heat recovery are expected to reduce carbon dioxide emissions by 13 percent compared with Fab 4 on the same Yokkaichi site.

When kitted out with equipment, Fab 5 Phase 2 will be capable of running Toshiba's multilayered BiCS (Bit-Cost Scalable) manufacturing process for 3D NAND memories. Although this kind of technology is not yet in production, Toshiba is leading the charge towards 3D NAND. In late 2012 the company announced that it had 16-layer prototype devices based on a 50 nm diameter vertical channel. Samples are due this year with volume production in 2015.

Samsung actually proposed more options for 3D NAND Flash: TCAT, VSAT and vertical gate. I think they would win any 3D NAND war Toshiba starts.

If such a war can be run, that is. Since the 3D NAND is based on charge trapping in nitride, not floating gate, the nitride charge trapping reliability issues come to fore. The move to charge trapping has not yet preceded the move to 3D-NAND. This technology is still a high-risk technology that has not yet been qualified. Since it cannot prevent charge spreading like floating gate, there is a fundamental issue there.

If Toshiba doesn't buid more NAND capacity then they will loose market share to someone else who will - probably Samsung. It's a high stakes business and you have to be able to pull the trigger when you think the timing is right.

>> With so much die stacking being used in mobiles, it seems inevitable that at some point, it will be easier to "push a process node" by stacking rather than shrinking.

If you look carefully in these die stacking systems, we are not getting the best performance because the software we hope to mine their efficiencies are still sub-optimal. The main problem is not the stacking but embedded software that optimizes them.

With so much die stacking being used in mobiles, it seems inevitable that at some point, it will be easier to "push a process node" by stacking rather than shrinking. The question is when. The question is how it will be architectured. seem like keeping pieces in testable slabs makes the most sense. Will it make sense to bring BIST engines as a separate slab or stack a separate layer to handle this...