As Moore’s Law becomes more difficult to fulfill, integration of significantly different technologies such as spintronics, carbon nano tube field effect transistors (CNFET), optical nanocircuits based on metamaterials, and more recently the memristor, are gaining more focus thus creating new possibilities towards realization of innovative circuits and systems within the System on System (SoS) domain.

The memristor behaves as a switch, much like a transistor. However, unlike the transistor, it is a 2-terminal rather than a 3-terminal device and does not require power to retain either of its two states. Note that a memristor changes its resistance between two values and this is achieved via the movement of mobile ionic charge within an oxide layer, furthermore, these resistive states are non-volatile.

Large-capacity Content Addressable Memory (CAM) is a key element in a wide variety of applications. The inevitable complexities of scaling MOS transistors introduce a major challenge in the realization of such systems. Convergence of disparate technologies, which are compatible with CMOS processing, may allow extension of Moore’s Law for a few more years. This paper provides a new approach towards the design and modeling of Memristor (Memory resistor) based Content Addressable Memory (MCAM) using a combination of memristor MOS devices to form the core of a memory/compare logic cell that forms the building block of the CAM architecture. The non-volatile characteristic and the nanoscale geometry together with compatibility of the memristor with CMOS processing technology increases the packing density, provides for new approaches towards power management through disabling CAM blocks without loss of stored data, reduces power dissipation, and has scope for speed improvement as the technology matures

. Emerging Memory Devices and Technologies

Memory processing has been considered as the pace-setter for scaling a technology. A number of performance parameters including capacity (that relate to area utilization), cost, speed (both access time and bandwidth), retention time, and persistence, read/write endurance, active power dissipation, standby power, robustness such as reliability and temperature related issues characterize memories. Recent and emerging technologies such as Phase-Change Random Access Memory (PCRAM), Magnetic RAM (MRAM), Ferroelectric RAM (FeRAM), Resistive RAM (RRAM), and Memristor, have shown promise and some are already being considered for implementation into emerging products. Table II summarizes a range of performance parameters and salient features of each of the technologies that characterize memories. A projected plan for 2020 for memories highlight a capacity greater than 1 TB, read/write access times of less than 100 ns and endurance in the order of 10^12 or more write cycles.

The non-volatile characteristic and nanoscale geometry of the memristor together with its compatibility with CMOS process technology increases the memory cell packing density, reduces power dissipation and provides for new approaches towards power reduction and management through disabling blocks of MCAM cells without loss of stored data. Our simulation results show that the MCAM approach provides a 45% reduction in silicon area when compared with the SRAM equivalent cell. The Read operation of the MCAM ranges between 5 ns to 12 ns, for various implementations, and is comparable with current SRAM and DRAM approaches. However the Write operation is significantly longer.

Simulation results indicate a reduction of some 96% in average power dissipation with the MCAM cell. The maximum power reduction is over 74% for the memristor-based structure. The RMS value of current sunk from the supply rail for the MCAM is also approximately 47 μA, which correspond to over a 95% reduction when compared to SRAM-based circuitry. To the best of our knowledge this is the first power consumption analysis of a memristor-based structure that has been presented using a behavioral modeling approach. As the technology is better understood and matures further improvements in performance can be expected

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