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TECHNICAL LIBRARY

Accurate Worst-Case Model Generation with SPAYN

Introduction

Statistical fluctuations inherent in any IC manufacturing
process cause unavoidable variations in device and circuit performance.
These circuit performance variabilities can cause serious yield
and reliability problems if they are not accounted for at the circuit
design stage. It is imperative that the so-called statistical nature
of any process is determined so that costly re-design cycles are
avoided. Accurate worst-case model parameter sets need to be generated.
In addition, efforts must be made to define the relationships between
the variations in circuit simulator model parameters and the core
process variabilities which cause them. SPAYN is Silvaco's
statistical parameter analysis and worst-case modeling package.
It is the ideal tool for accomplishing these all-important tasks.

SPAYN makes the task of generating
realistic and accurate process corner models very easy. SPAYN
will also communicate with commercial circuit simulators including
SmartSpice so that the worst-case model parameter
sets associated with any particular circuit application can be determined
automatically. By merging model parameter information with E-test
data, the SPAYN user can relate model parameters,
parameter variabilities, and parameter correlations to process monitor
variables which are routinely measured.

SPAYN enables specific circuit performance
variations to be linked to the process-related parameters. The effects
on the circuit, of tightening or loosening the controls on these
process variables, can also be easily determined. Using data generated
by a combination of UTMOST and VWF, process corner
or worst-case model parameter sets can be generated for a process
under development. This topic will be the subject of future Simulation
Standard articles.

Example

Model parameters for the Berkeley Level 3 MOSFET
model were extracted, over a period of time, from over 1000 sites
on a 1µm CMOS process. Complete sets of n-channel and
p-channel parameters were collected on each site. These parameter
sets were read into SPAYN where preliminary analyses
were performed to determine suitable parameter distributions and
eliminate parameter sets containing troublesome outliers. Statistical
summary tables, histograms, and scatter plots were generated (see
Figure 1).

Figure 1a. Example of a parameter
histogram generated by SPAYN.

Figure 1b. Example of a scatter
plot generated by SPAYN.

A principal component analysis was performed on
the 27 correlated model parameters using an 80% variance retained
criteria. It was found that 6 independent components explained almost
81% of the variance of all of the original model parameters. Each
of these 6 components was then replaced by the model parameter with
which it was most correlated (i.e. its dominant parameter). Equations
were generated relating each of the non-dominant parameters to the
independent dominant parameters.

In this case, the dominant parameters were found
to be p-channel THETA parameter (19.7% variance), p-channel LD (19%),
n-channel UO parameter (12.9%), n-channel NFS parameter (10.3%),
n-channel KAPPA parameter (9.7%), and p-channel WD parameter (9.2%).
The identity of the independent dominant parameters can be changed
by the user if required. The process line-width, thickness, implant,
and diffusion variations related to each of these dominant parameter
variations were readily identified. Some examples of the equations
generated in this example are shown below:

The 6 dominant parameters, and the system of equations
derived in order to calculate the remaining dependent parameters,
were used as a basis for the generation of a process monitor chart
(see Figure 2) and accurate process corner models. For this example,
full CMOS Level 3 parameter sets, corresponding to all combinations
of the dominant parameters set to +/-3o, were generated. There were
a total of 64 of these corner models for the case of 6 uncorrelated
dominant parameters. Other parameter set generation possibilities
including the generation of a correlated Monte Carlo parameter set
are also offered as options by SPAYN.

SPAYN was then linked to a circuit
simulator using the VYPER environment and various
test circuits were simulated using the corner models (see Figures
3 and 4). From these simulations it was possible to identify good
worst-case model parameter sets for different circuit applications,
where the model parameter limits were realistic, and parameter correlations
were accounted for correctly. The effects of changing the control
on process variabilities can also be easily assessed.

Silvaco would like to thank Barry Mason and Paul
Stribley of GEC Plessey Semiconductors, Roborough, England, and
Rory Clancy and Kevin McCarthy of the National Microelectronics
Research Centre, Cork, Ireland, for their valuable contributions.
The data used in this article was supplied by GEC Plessey Semiconductors,
from their 6" wafer fabrication plant in Roborough, U.K., and came
from the production 1.0&uml;µm CMOS analog process.