On 16 May, David Forbes wrote:
> Hello,
>
> I'm a new poster to this list. I'm a hardware engineer working on a data
> collections system for a radiotelescope which is designed to read data
> from a linear CCD into an industrial PC running RTLinux. The CCD
> interface is all done in a Xilinx FPGA chip connected to an ECP port.
> The data rate needed is about 150 kbytes/sec.
>

I obtained regular performance of about 200 KB/sec without DMA. The key
requirement is to get full use of FIFO reads. I then found that FIFO
with no interrupts (they actually made things worse) and no DMA
delivered 200 KB/sec in a similar situation. I was reading a CCD over
the parallel port using ECP mode. The CCD chip wanted some fixed length
commands (all 4 bytes) and responded with data (ranging from 4 byte to
100K byte responses).

I've lost track of versions because this was almost two years ago. The
bulk of the code was done using ppdev device so that the chip controls
could run user mode instead of device driver. In testing for production
use this driver passed the 100K cycle performance test with sustained
200KB/sec. 100K cycles for this device means 10,000,000,000 bytes
transferred. It took a while.