Many cryptosystems embed a high-quality true random number generator (TRNG). The randomness quality of
a TRNG output stream depends on its implementation and may vary due to various changes in the environment
such as power supply, temperature, electromagnetic interferences. Attacking TRNGs may be a good solution
to decrease the security of a cryptosystem leading to lower security keys or bad padding values for instance.
In order to protect TRNGs, on-the-fly evaluation of their randomness quality must be integrated on the chip.
In this paper, we present some preliminary results of the FPGA implementation of functional units dedicated
to statistical tests for on-the-fly randomness evaluation. In the entropy test the evaluation of the harmonic
series at some ranks is required. Usually its approximation is costly. We propose a multiple interval polynomial
approximation. The decomposition of the whole domain into small sub-intervals leads to a good trade-off between
the degree of the polynomial (i.e. multipliers cost) and the memory resources required to store the coefficients
for all sub-intervals.

This paper presents the first version of a software library called PACE ("Prototyping Arithmetic in Cryptography
Easily"). This is a C++ library under LGPL license. It provides number systems and algorithms for prototyping
the arithmetic layer in cryptographic applications. The first version of PACE includes basic support of prime
finite fields and ECC (Elliptic Curve Cryptography) basic algorithms for software implementations.

In this work we present some improvements on hardware operators dedicated to the computation of power
operations with fixed integer exponent (x<sup>3</sup>, x<sup>4</sup>, . . .) in unsigned radix-2 fixed-point or integer representations.
The proposed method reduces the number of partial products using simplifications based on new identities and
transformations. These simplifications are performed both at the logical and the arithmetic levels. The proposed
method has been implemented in a VHDL generator that produces synthesizable descriptions of optimized
operators. The results of our method have been demonstrated on FPGA circuits.

In this work, we present a tool that generates division hardware units. This generator, called divgen, allows a fast and wide space exploration in circuits that involve division operations. The generator produces synthesizable VHDL descriptions of optimized division units for various algorithms and parameters. The results of our generator have been demonstrated on FPGA circuits.

This paper presents a C library for the software support of single precision floating-point (FP) arithmetic on processors without FP hardware units such as VLIW or DSP processor cores for embedded applications. This library provides several levels of compliance to the IEEE 754 FP standard. The complete specifications of the standard can be used or just some relaxed characteristics such as restricted rounding modes or computations without denormal numbers. This library is evaluated on the ST200 VLIW processors from STMicroelectronics.

The choice of modular multiplication algorithms for hardware implementation is not a straightforward problem. In this paper, we analyze and compare FPGA implementations of several state-of-the-art dedicated modular multipliers. For a given constant modulus <i>M</i>, there are several possible methods for generating an optimized modular multiplier, i.e. the dedicated (<i>X</i> x <i>Y</i>) mod <i>M</i> operator. Those modular multipliers can be generated using two kinds of algorithms: those that work for all values of <i>M</i> and those that only work for specific values of the modulo such as 2<sup>n</sup> &plusmn; 1. Several algorithms will be compared for both kind of algorithms. We also deal with two FPGA families, Virtex E and Virtex-II from Xilinx, to measure the impact of new specific built-in resources such as small embedded multipliers. The synthesizable VHDL files of the generated modular multipliers will be available on a web page.

The optimization of algorithms for self-timed or asynchronous circuits requires specific solutions. Due to the variable-time capabilities of asynchronous circuits, the average computation time should be optimized and not only the worst case of the signal propagation. If efficient algorithms and implementations are known for asynchronous addition and multiplication, only straightforward algorithms have been studied for division. This paper compares several digit-recurrence division algorithms (speed, area and circuit activity for estimating the power consumption). The comparison is based on simulations of the different operators described at the gate level. This work shows that the best solutions for asynchronous circuits are quite different from those used in synchronous circuits.

Direct table-based methods are frequently proposed for the implementation of low-precision evaluation of functions. We examine and compare the real implementation on current FPGAs of two methods, the single table and the bipartite table, introduced in the literature. We focus on the sine/cosine functions, input and output sizes in {8,...,12} and on LUT-based FPGAs and especially on the Virtex device family from Xilinx.

This paper describes a new digital reprogrammable architecture called Field Programmable On-line oPerators (FPOP). This architecture is a kind of FPGA dedicated to very low-power implementations of numerical algorithms in signal processing or digital control applications for embedded or portable systems. FPOP is based on a reprogrammable array of on-line arithmetic operators. On-line arithmetic is a digit-serial arithmetic with most significant digits first using a redundant number system. Because of the small size of the digit-serial operators and the small number of communication wires between the operators, single chip implementation of complex numerical algorithms can be achieved using on-line arithmetic. Furthermore, the digit-level pipeline and the small size of the arithmetic operators lead to high performance parallel computations. Compared to a standard FPGA, the basic cells in FPOP are arithmetic operators such as adders, subtracters, multipliers, dividers, square-rooters, sine or cosine operators. This granularity level allows very efficient power X delay implementations of most algorithms used in digital control and signal processing. The circuit also integrates some analog to digital and digital to analog converters.

This paper deals with the computation of reciprocals, square roots, inverse square roots, and some elementary functions using small tables, small multipliers, and for some functions, a final 'large' multiplication. We propose a method that allows fast evaluation of these functions in double precision arithmetic.The strength of this method is that the same scheme allows the computation of all these functions.

The most significant digit first function evaluation method (E-method) allows efficient evaluation of polynomials and certain rational fucntions on custon hardware. The time required for the computation is of the order of m carry-free addition operations, m being the number of digits in the result. We discuss a digit-parallel and a digit-serial implementation of this method on a DecPeRLe-1 board, made up with Xilinx FPGAs. After a presentation of the E-method, we give a discription of the architecture of the DecPeRLe-1 board, present our designs and analyze their performances.

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