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Abstract

Disclosed is a wiring scheme for multilevel thin film technologies which doubles the number of via connections between levels, loosens alignment tolerances, and maintains wiring density. In these structures the new wiring scheme creates a sufficient number of vias to wire high density structures (3 lines per channel).

Country

United States

Language

English (United States)

This text was extracted from an ASCII text file.

This is the abbreviated version, containing approximately
67% of the total text.

Via Rich Thin Film Wiring Scheme for Electronic Packaging

Disclosed is
a wiring scheme for multilevel thin film
technologies which doubles the number of via connections between
levels, loosens alignment tolerances, and maintains wiring density.
In these structures the new wiring scheme creates a sufficient number
of vias to wire high density structures (3 lines per channel).

Typical
circuitry designs for multilevel thin film structures
consist of running multiple parallel lines between vias placed in a
straight orthogonal array. In the 3
lines per channel design (Fig.
1) there are three unit length lines and one via per unit cell.
Wirability vias, additional vias within the array, must be small and
connect directly into lines. The
equipment for making the small vias
with tight alignment tolerances ( 0.5 micron) is complex and
costly.

The thin film
wiring scheme shown in Fig. 2 has much better
utilization of the wiring space. An
additional via is added at the
center of the unit cell and lines are placed diagonally with respect
to the original via grid. In the new
unit cell there are 2.8 unit
lengths of wiring compared to 3 unit lengths in the typical design.
However, there are now 2 vias per unit cell, double the via density
of the original design. The new via
position at the center of the
cell replaces the small wirability via in the original design. This
new wirability via is larger in size which allows looser level to
level al...