Internal Memory Controller and HyperTransport

One of
the largest problems in modern computer design is the presence of bottlenecks,
or areas of low performance which slow an otherwise fast system down.

In most
modern computers, data intended for video or main memory needs to be passed to
and through the Northbridge chip on the motherboard, and data from other sources like USB connections, PCI slots or hard-drives must pass
through the Southbridge chip, then the Northbridge.

With the
amount of information that needs to be
squeezed through the various data buses into the processor to be operated on,
bottlenecks inevitably develop, where the processor is waiting for the necessary
bits to be delivered by the I/O subsystem feeding it.

Processors get consistently faster every few months, while
data bus breakthroughs are irregular, the issue perpetuates itself.

AMD has
attempted to get around this constant problem by equipping its 64-bit processors with two advantages, internal DDR memory controllers and Hypertransport links. AMD has built the memory
controller (normally a part of the motherboard to which the processor is
attached), directly into their Opteron and Athlon 64 CPUs.

As you
can imagine, this considerably reduces the time it takes the processor to access memory, since data need only travel
between the processor and the physical memory. Communication with the controller
that arranges the data flow does not need to be passed outside the processor,
reducing the amount of computing cycles lost while waiting for the memory to
respond.

Another
benefit is the fact that memory traffic need no longer run between the
processor and the Northbridge. The Northbridge traditionally provides
the memory controller with data, and removing this bottleneck increases overall
operations.The
second part of the package is support for Hypertransport input/output
technology.

The Athlon64 Chipsets

As you would expect, all the usual suspects have
come up with chipset designs for the Athlon 64. AMD (of course), VIA, SIS,
Nvidia and Ali all have chipsets ready. ATI has announced that they are going to
support the new AMD processors in a future chipset, but details are still slim.

Designing chipsets for the Athlon 64 processor
means that these companies have to change a few of the design methods that they
have become used to. For one thing, the Athlon64's integrated support for
Hypertransport technology means that conventional means of connecting the
Northbridge (memory and graphics controller) chip to the CPU will have to
change, as the Athlon 64 needs a Hypertransport bus to feed it information.

For another, the memory controller, resident in the
Northbridge chip on conventional chipsets, will now be integrated into the CPU
itself, as the Athlon64 has it built into the actual die. Hence the memory bus
is now an independent path between the CPU and the RAM, shared by nothing. A
two-way Hypertransport link replaces the conventional 'front-side bus' design of
the memory in which separate pathways are provided for the memory, AGP
information and all other data from the other I/O subsystems like the PCI bus
(via the Southbridge chip).