What’sthedifferencebetweenVHDL&Verilog?-LeeChoonLin

This is a common question asked when beginner is looking at which HDL language to learn. I am well-versed in both languages, although I started as a Verilog user for 10 years. In short, here' some quick points to note:

VHDL is the first HDL(Hardware Description Language), which is developed since year 1980. After four years, Verilog was created by Prabhu Goel and Phil Moorby during winter of 1984.