CEVA unveils core for DSP control processing in 5G

IP vendor CEVA has posted details of its CEVA-X2, a configuration primarily aimed at Physical Layer Control of high-end multi-carrier and multi-standard cellular baseband.

The CEVA-X2 has been designed to tackle the PHY control complexity increase of LTE-Advanced Pro which includes Rel.13 multi-carrier and multi-standard handsets. Where the PHY Datapath tasks such as per-channel measurement and decoding are not required to run on the DSP, CEVA-X2 is claimed to offer a 30%-65% better die size efficiency and 10%-25% better power efficiency compared to CEVA-X4 DSP. The CEVA-X2 is also appropriate to run both the PHY and MAC for a range of other communication standards, including IEEE 802.15.4g, ZigBee, Thread and power line communications (PLC), combining power efficiency with minimal die area for such use cases.

Features of the IP include;

VLIW/SIMD architecture

10 stage pipeline

128 bit memory bandwidth

4.0 Coremark/MHz

Four-MAC 16x16 per cycle

64-SIMD fixed-point operations

Up to two IEEE single-precision floating-point operations

1.5GHz operating frequency in 16nm finFET

Instruction and data caches

Branch target buffer

CEVA-Connect Technology to schedule control and data planes of hardware accelerators