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tftex01.in : Passivated Device

This file performs Id/Vgs simulation of a TFT device with material properties corresponding to passivated alpha-Si:H material. The example shows:

Structure formation using Atlas syntax

Material and model settings for passivated a-Si

Forward Id/Vgs characteristics

The key command in TFT simulation is the defect statement. It is used to define a continuous density of trap states in the silicon and the relevant trapping cross-sections.

The Id/Vgs ramping is done in a similar manner to the threshold voltage tests for MOS devices described in the MOS example. Results from this example can be compared with the un-passivated a-Si device.

A more detailed description of TFT material settings is given in the Forward/Reverse Gate Voltage Characteristic example.

To load and run this example, select the Load example button in DeckBuild. This will copy the input file and any support files to your current working directory. Select the run button to execute the example.

These examples are for reference only. Every software package contains a full set of examples suitable for that version and are installed with the software. If you see examples here that are not in your installation
you should consider updating to a later version of the software.