Perhaps one of the most confusing, and misreported processor stories is that of the Cyrix Joshua processor. More correctly known as the VIA Cyrix III Joshua. Cyrix began sampling this successor to the MII in 1999, a tumultuous time in Cyrix’s history, as they were in the midst of being sold to VIA by National Semiconductor. The Joshua never made it into full production, being quickly killed off by the Centaur designed Samuel core. Centaur was the processor division of IDT which produced the Winchip series, bought by VIA only a month after their purchase of Cyrix.

Adding to the confusion was Cyrix bountiful use of code names for its upcoming products, with many seeming to overlap, change or be redundant. Understanding the methodology of their naming will greatly increase ones understanding of the products. Cyrix used a code name for the core of a processor, as well as a separate name for what application that core was going to be used in. Just like Intel used the P6 core for the PII, Celeron, and Xeon, Cyrix intended its cores to be able to be used in several products.

In the late 1990’s Cyrix had two new cores under development. The first was the Cayenne, an evolution of the 6x86MX/MII processor. The Cayenne was essentially an MII, with a dual (rather then single) issue FPU, support for 3DNow! instructions, and perhaps most importantly, a 256K 8-way associative on-die L2 cache. It retained the 7 stage pipeline of the MII, the 256 byte scratch pad L0 cache, an almost identical X-Y integer unit and the same 64K L1 cache. Cyrix had had industry leading integer performance, but always lagged in the area of FPU performance. The dual issue FPU was their attempt to help remedy this. However, FPU intensive benchmarks, such as Quake 3, showed the Cayenne core to be about half as fast as a Celeron of equal rating (500MHz vs PR500 Cyrix). Business apps, heavy in integer and light on floating point, showed the integer strength of the Cyrix, with a 400MHz Cyrix matching a 500MHz Celeron.

The Cayenne core was slated to be used in at least 3 different products. The first was the MXi, this was the successor to the MediaGX and thus would be highly integrated, including a PCI Bus controller, SDRAM controller, MPEG/DVD acceleration, 2D/3D Graphics as well as audio capabilities. The Jedi was to be a socket 7 (Super 7 really) compatible processor based on the Cayenne core. This was canceled in 1999 (nothing to do with potential lawsuits from Lucas Films as often was rumored). The third use of the Cayenne core was the Gobi, this was to be a Socket 370 compatible processor and it is this version that was widely sampled, and benchmarked, by many hardware review sites, magazines, etc. When VIA purchased Cyrix on June 30, 1999 the Gobi project was allowed to continue, MXi, and other projects were quickly shut down. The Gobi codename did not fit with VIAs core naming scheme however, thus is was renamed.

Back in the day of CPU’s National was on the forefront of CPU design, while Intel was messing around with 4 and 8 bit designs. It by itself was the 4th CPU, and the 1st bit slice device.

It consists of:
4 x 4 bit IMP-00A/520D – These are the Register and Arithmetic Units
1 x IMP16A-521D – Standard 16 bit Instruction set control chip (Based on the Data General Nova)
1 x IMP16A-522D – Extended 16 bit Instruction set (not sure what addition instructions it has)
These were sold in a set by National, and in a pretty nice box.

National IMP16A-500D

Later on National implemented them as a single chip, the IMP16A-500D PACE, and then the NMOS INS8900.
More infomation about the IMP16 can be found at Antique Tech

The Largest CPU Museum!

In my daily hunt for new processors, and other chips for the museum, as well as information about new chips, I constantly come across interesting chips, in strange locations. Here you will get a chance to learn WHERE many of the chips in the museum come from and what they are.