Industry leaders at the 35th annual SEMI Industry Strategy Symposium (ISS) in January described a perfect storm of cost, complexity and uncertainty as the industry struggles with process engineering complexity at sub-28nm nodes, hazy EUV installation schedules, 3D-IC challenges, and planning for a 450mm wafer transition. At no time have industry executives faced more strategic uncertainty or greater doubt about the future effectiveness of past competitive and collaboration models. Complicating the investment and unprecedented R&D challenges were conflicting forecasts on materials and capex spending for 2011-2012 and universal concerns on the European debt crisis that threaten to afflict global markets. On the positive side, the long-term growth in semiconductor demand that underlies the industry’s strength is strong with cloud computing, life sciences, smart grids and cleantech creating new applications to energize global chip demand.

William Holt, senior VP and GM at Intel, and Bernard S. Meyerson, an IBM Fellow and VP at IBM, described the industry’s successes at overcome leading-edge semiconductor technology barriers. Recent nodes have required advanced technical solutions such as strained silicon, high-K metal gates, new material sets and tri-gate transistors that have escalated the complexity and cost of keeping pace with Moore’s Law. In lithography, optical correction, alternating phase shift masks, double patterning and immersion have been required to supplement traditional geometric scaling efforts. Complicated, costly transition interconnect technology from copper, low K, lead-free, self-aligned vias, and ultra-low k solutions have also increased the challenges to leading-edge chip technology. Every node now presents an increasing set of technical barriers that need to be “surmounted, circumvented or tunneled through,” summarized Bill Holt. Bernie Myerson described the new scaling challenges as requiring “mitigating innovations,” or having “new knobs to turn after the small knobs broke.”

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Fortunately, both Holt and Myerson were optimistic that future scaling challenges will similarly be overcome with ingenuity, deep technical resources and sheer force of will. The escalating scale of technical barriers accompanying each node, however, left some in the audience wondering if past success in meeting the dictates of Moore’s Law will remain a good indicator of the future. Clearly, considerable advance work is being done on carbon nano tubes, graphene, photonics and other areas that may be ready for sub-10 nm — “the innovation pipeline is full for the next ten years,” said Holt—but the audience also learned about the growing need for “mitigating innovations,” and the new need to turn unexpected knobs every 18-24 months.

Of course, the big knob that turns in our industry is lithography and the ISS audience benefitted from a thorough description of the EUV roadmap from James Koonmen, senior VP at ASML and GM at Brion. Significant accomplishments have been achieved in litho for a decade and EUV is no exception. ASML now has six pre-production machines in the field for research, testing and development — an essential stage in the “industrialization” of EUV. Two suppliers are addressing the critical power source issues, but EUV productivity is still “a factor of 5 to 10 from where we want to be.” ASML hopes to “reach 125 wafers per hour within two years” with stable performance on resolution and overlay.

With this backdrop of uncertainty on scaling (not to mention the concurrent efforts in 3D chip stacking), discussions on the 450mm wafer transition took center stage on Day 2. Dan Hutcheson, CEO of VLSI Research and winner of the 2012 Bob Graham Award, moderated a panel comprised of key players: John Chen, VP of Technology for Nvidia, Paolo Gargini, director of Technology Strategy at Intel and ITRS chairman, Randir Thakur, executive VP and general manager of Applied Materials Silicon Systems Group, Kazuo Ushida, president of Precision Equipment for Nikon, and Takashi Abe, executive vice president of Sumco.

Nvidia’s Chen began the discussion with data that suggested that transistor cost is not scaling with recent node shrinks, a point echoed by Handel Jones, president of IBS. Beset with the diminishing returns of Moore’s Law and the inability to charge premium prices for advanced products, Chen is desperate for 450mm.

While vertical device structures, new material sets, and still-challenging EUV and 3D IC present unprecedented technical challenges and R&D costs on both suppliers and device manufacturers, the compound effect of 450mm wafer transition generated divergent opinions about the need for R&D efficiency and “new models” of industry collaboration. Applied’s Thakur compared the positive economic and technical environment of the 300mm transition with today’s financial outlook and R&D cost structure. He explained the challenges of working on stacking 450 mm development on top of three different nodes and cited concerns about the health of his suppliers saying, “The whole infrastructure needs to be ready.” Gargini is confident the industry can meet the challenge: “if we want to do it, we can do it.” He is confident that 450mm equipment development will take place in 2012-2014 and begin to move into production in 2015, while acknowledging,” the tipping point will come when litho production equipment is available.”

Virtually all presenters and panelists emphasized the critical need for synchronized timing on 450 deployment to avert the mistakes of the 300mm wafer transition of the last decade. While there are fewer leading-edge chip makers today than were present when the 300mm transition start-stopped out of the gates, the uncertainty of EUV and other technical barriers and the unproven coordination among the hyper-competitive consortium players, indicate insertion timing will be a tough decision with certain risk.

Fortunately for the industry, Hutcheson believes the 450mm transition will not be as costly overall as the 300mm transition. He estimates that 450mm development has been $0.5B so far, with another $7.6B needed by 2020 if all goes right. Unfortunately for the industry, that amount alone would overwhelm the total R&D spending by wafer equipment companies for the time period and represents only a half to a third of what other observers believe is necessary to fund 450mm R&D. 300mm development cost was $12 billion over a decade ago.

Several presentations during ISS addressed for need for new R&D funding industry collaboration models. Stephen G. Newberry, vice chairman of the Board, Lam Research Corporation, offering the automotive industry as a useful model where the industry has been able to raise prices for improved features and performance, and a few key suppliers embarked on critical R&D efforts jointly-funded by manufacturers. Michael R. Splinter, chairman and CEO, Applied Materials, also emphasized the need for “collaboration, coordination and consolidation” to solve the nexus of technical and economic challenges facing the industry. Even Intel fellow Paolo Gargini admitted, “This is going to be coordinated effort. The level of communication must go to a higher level.”

Yet for all the talk of collaboration and coordination, it was apparent that there are many different opinions about what level and form of collaboration is really required. Clearly the industry is at a crossroads where economic forces are pressuring profitability and accelerating consolidation, and new R&D funding methods will have to arise for the industry to advance as it has in the past.