Configures the PFI line on the AUX I/O connector for reading or writing.

TRUE: Writing enabled.

FALSE: Reading enabled (output tristated).

SPI Idle

Boolean

Indicator

Indicates when the SPI interface to either the clock circuit or ADC is being accessed.

To use the SPI or Apply Settings signals, you must wait for this signal to be TRUE.

SPI Device Select

U8

Control

Selects which SPI device to interact with.

0 = ADC

1 = PLL circuit

SPI Address

U16

Control

Configures the SPI address to read and write data.

Write data only to addresses supported by the selected device.

SPI Write Data

U32

Control

Configures the SPI data to write to a selected device at a SPI address.

SPI Read Data

U8

Indicator

Configures the SPI data to read from a selected device at a SPI address.

SPI Read

Boolean

Control

Executes the settings of the SPI Read Data signal when this signal is on a FALSE-to-TRUE transition.

SPI Write

Boolean

Control

Executes the settings of the SPI Write Data signal when this signal is on a FALSE-to-TRUE transition.

Clock 40 MHz

—

Clock

40 MHz base clock source.You can use this clock as a timebase for running your LabVIEW FPGA VI.

The 40 MHz onboard clock is the default clock. This clock is generated from a PLL in the NI FlexRIO FPGA module. The PLL source is either PXIe_CLK100 or PXI_CLK10.

Clock 200MHz

—

Clock

200 MHz base clock source.You can use this clock as a timebase for running code on your target FPGA. This clock is generated from a PLL in the NI FlexRIO FPGA module.

Data Clock

—

Constant Clock

FPGA clock used to sample input data.

In real-time sampling mode, eight samples from each analog input channel are valid on every rising edge of this clock. In TIS mode, 16 samples from only one analog input channel are valid on each clock cycle. During TIS mode, the data in the CLIP signals appears to be coming from both AI 0 and AI 1, but one channel is returning time-interleaved samples for the other channel, which provides 16 total samples on one channel.

Access only the analog input and over range signals in this clock domain.