Video at RISC-V 2018 Summit of Simon Davidmann presenting RISC-V Compliance in the Era of OPEN ISA and Custom Instructions

One mission-critical task for the RISC-V SoC developers and implementors is the need to test and verify that RISC-V cores are compliant to the specifications, including user and privilege modes. The RISC-V market will depend on the wide and diverse availability of silicon devices that can leverage the investment in RISC-V software across all conforming devices. This is only possible when building on a foundation of devices with guaranteed compliance with the specifications. Many RISC-V chips, systems and design flows will exploit the concept of custom instructions or other optimizations, delivering unique features. In these cases especially, the need to continuously test and confirm compliance throughout the design process becomes essential for all RISC-V based SoCs and systems. The technical issues of determining compliance with the RISC-V ISA are introduced with examples of customer extensions. The question of completeness and specification coverage are discussed and use cases of tool usage is provided. The Imperas experience of examining compliance on various proprietary RTL, open source RTL, FPGA, silicon, and ISS models will be explained with issues experienced being shown. This is the video of the presentation.

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Imperas OVP modeling and high-level simulation platforms unify both hardware and software development for multi-core designs, and are clearly the wave of the future. Access to the University Program allows my students access to advanced technologies essential to their future endeavors.

Professor Jong Tae Kim

Sungkyunkwan University, Seoul, South Korea - SKKU

As RISC-V adoption grows throughout the industry in a variety of application areas, so does the need for robust simulation support from both commercial and open source suppliers. We welcome Imperas' contributions to the rapidly accelerating RISC-V ecosystem.