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AR# 32927

XST - What is new in XST for Virtex-6 and Spartan-6 devices?

Description

Solution

In ISE Design Suite 11.2, XST introduced a new VHDL/Verilog parser for Virtex-6 and Spartan-6 families.

The new parser brings a lot of improvements to the XILINX Synthesis solution.

- Significantly enlarges VHDL/Verilog language coverage, including a great support for complex data structures such as records, multi-dimensional arrays, array of records, etc.

- Allows greater flexibility in design coding.

- Significantly reduces runtime and memory usage for processing of various HDL constructs.

- Processing of complex if, then, else, and case statements.

- Functions and generics calculation.

- Structural designs processing.

However, several constructs supported in the XST Standard version for older FPGA families (such as Virtex-5 and Spartan-3) are not VHDL/Verilog LRM compliant.

Some of them are rejected by the new parser and some of them are interpreted differently.

Such situations will require some VHDL/Verilog code changes to successfully process the design using the new parser.

In addition, several naming conventions were improved in XST for Virtex-6 and Spartan-6 families.

The names are more clear and predictable.

However, these changes might have an impact on existing UCF files and require some modification.

The goal of this solution record is to provide the list of changes in XST for Virtex-6 and Spartan-6 devices compared to XST Standard, which will require some designs adaptation when migrating designs to Virtex-6 and Spartan-6.

1) List of HDL constructs that need to be reworked before re-targeting the code for Virtex-6 and Spartan-6 devices.