The Transaction Generator (TG) is a transaction level (TL) SystemC simulator for benchmarking network-on-chips (NoCs) used in multiprocessor system-on-chip (SoC) applications. Utilizing this tool makes simulation of larger systems substantially faster and the results obtained at this higher level can be accurately used as an initial estimate in selecting and fine-tuning NoCs.

The TG generates traffic for network-on-chip according to abstract software and hardware models. During simulation the TG measures performance metrics from the application and platform models, and from the traffic routed through network-on-chip. Because this freely available, highly-versatile tool, works on the transaction level, simulation of larger systems is substantially faster than those done at the clock-cycle accurate level.

The tool is freely available to both OCP-IP members and non-members alike through GNU LGPL, and is useful for all system-level designers evaluating various interconnection solutions in a simulation model of a real, complex system. It can also be used to simulate IP blocks before real implementations are available which enables the design of interconnect and implementation of IP blocks and SW for processors to advance in parallel, saving time, resources, and ensuring a faster time-to-market.