Spin-lock on cpu0 results when attempting to boot securely

Edit: The format of this post has changed quite a bit from its original proposal.

I have flashed a RCW with SB_EN=1 and BOOT_HO=1. Cpu0 will be held in reset on PORESET. At this point I write to the SFP_SRKH and SFP_OTPMKR registers the appropriate key hash and key value, respectively. Upon releasing cpu0 the behavior I observe is that the core begins executing running but stops on a spin-loop at instruction 0x1D0.

As suggested below by bpe the contents of HPSR are:

SecMon_HP Status Register (HPSR): 0x8000AB00

The above indicates that no errors exist in the OTPMK or SRKH registers. Checking additional Sec_Mon registers indicates that no security violations have occurred. Additionally, all four scratch registers read as zero.

I am not able to find any errors in any of the status registers but clearly things are not working properly.

I see. The table's name is "ESBC Validation errors", so I was thinking these were error codes written if the ISBC failed to validate the ESBC. And yes, I overlooked including that in the post.

The reference you give indicates that the ISBC Verification failures (Table 1) is only for the P3/P5/P5 platforms.

The only tables with information for the LS1043A are 3 (core exceptions), 5 (system state failures), 6 (general header checking failures), 7 (key/signature/uid errors), 8 (verification errors), 9 (SEC/PAMU failures). Although this is a fair amount of good information, where are the ISBC validation errors for the LS1043A platform?