ARM Cortex-A73 targets low-power mobile

AUSTIN, Texas – ARM announced details about it next-generation mobile CPU core, the Cortex-A73, formerly code-named Artemis. The core represents a pivot from performance- and power-driven cores to a tighter focus on low power design.

The 0.65mm 2 Cortex-A73 is a new ARMv8 microarchitecture that runs at up to 2.8 GHz and is designed as a big core in a big.LITTLE configuration. The core was used in ARM’s recently announced 10nm FinFET test chip. ARM wouldn't confirm whether the test chip also used its new Mali–G71 graphics core.

The Cortex-A73 is foremost a premium SoC for mobile devices that require compute for ultra-high definition displays, augmented and virtual reality, 5G communications and greater than 20 megapixel cameras. It was also designed for use in set-top boxes and multi-function printers. These mobile devices and their mid-range counterparts are thinner and prone to thermal saturation that impedes performance.

“Smaller form factors demand increasingly efficient CPUs,” said Ian Smythe, ARM’s director of marketing programs. “[With the A-73] we can maintain more peak performance in the same power budget.”

The Cortex-A73 is 20% more power efficient than the A72, allowing for additional thermal headroom for the rest of the SoC. The A73 can be paired with A53 chips to boost power efficiency by up to 90%.

Using a variety of benchmarks, A73 outperforms its predecessor in typical mobile use cases, SIMD performance and memory throughput. However, the new CPU core does not show as big of a generation-over-generation performance improvement as previous offerings.

Performance improvement compared to Cortex-A72. Source: ARM

“We’ll take what the process technology gives us and we have to make sure we can do more with it. I don’t think you’ll see a linear trajectory every time,” said Nadan Nayampally, vice president of marketing and strategy for compute products at ARM. "This doesn’t mean we might not get more performance next time.”

The A73’s power achievements are largely due to tweaks in its microarchitecture, including optimizations for branch prediction, pre-fetching and memory throughput. For example, ARM upgraded the size of the data cache to 64K while sustaining parallel streams for better multi-core performance.