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SPIE 2017 - imec papers and interview

At the SPIE Advanced Lithography Conference imec published a number of papers on EUV, multi-patterning and other lithography issues. In addition to seeing several of the papers presented I had a chance to sit down with imec's director of advanced patterning, Greg McIntyre. In this article I will summarize my discussions with Greg and some of the key message from the imec work.

When we first sat down I told Greg I was surprised that neither Intel or Samsung mentioned Line Width Roughness (LWR) in their EUV readiness talks. Greg said that for the foundry N7 - 40nm metal pitches that vias can be printed with the materials available today and that the roughness is OK. He did note that further improvement would be required for 5nm.

We then talked about different imec papers from the conference.

Self-Aligned Block Technology: A Step Towards Further Scaling
Ass multi-patterning has evolved to produce smaller features the number of cut/block masks has been growing leading to Edge Placement Error (EPE) issues. By using materials with differences in etch rates Self-Aligned Blocks (SAB) can be created mitigating EPE. Figure 1 illustrates the basic concept. The masks for the SAB approach always come in pairs so it could be a mask reduction technique for immersion but not for EUV. Specifically, metal oxides were investigated as a material to fill between spacers for Self-Aligned multi-patterning. SAB is a promising technology for insertion at the imec 5nm node.

Figure 1. Self Aligned Block.

SAQP & EUV Block patterning of BEoL metal layers on imec's iN7 platform
The imec iN7 node has a metal 1 (M1) pitch of 42nm to match the contacted poly pitch and a metal 2 (M2) pitch of 32nm. Both M1 and M2 are unidirectional with self-aligned via 1 on a 42nm pitch connecting M2 to M1. M1 and V1 can both be created with single EUV exposures. For M2 single exposure EUV is challenging to meet a 21nm Tip To Tip (T2T). For M2 with immersion Self Aligned Quadruple Patterning (SAQP) with 4 to 5 masks is required. The number of masks makes overlay challenging and drive process complexity. SAQP with a single EUV block mask is promising. The photoresist needs to get a little better for blocks but there are knobs to address it. Figure 2 summaries the trade-offs of EUV single exposure, SAQP with immersion blocks and SAQP with EUV block.

Figure 2. EUV Versus SAQP and Block.

Novel Membrane Solutions for EUV Pellicle: Better or Not?
In my SPIE 2017: EUV Readiness for High Volume Manufacturing article I discussed the need for pellicles for EUV. The current approach to pellicles uses polysilicon but there are concerns about the scalability of polysilicon to higher power EUV light sources. A successful EUV pellicle needs to have high transmission of EUV light, be mechanically strong, thermally stable and stand up hydrogen exposure. Carbon Nano Tube (CNT) materials have good EUV transmission and mechanical and thermal properties, however, hydrogen attacks the material. With a coating to protect against hydrogen attack CNT looks promising as a pellicle material.

Exploration of a Low-Temperature PEALD Technology to Trim and Smooth 193i Photoresist
LWR is a major challenge for EUV and even immersion lithography as we move to the iN5 node and beyond. Plasma Enhanced Atomic Layer Deposition (PEALD) was investigated as a trim and smoothing option. For trimming various chemistries and powers were investigated. High power O2/Ar reduces the vertical height of the photoresist faster than the lateral width. O2/N2 low power chemistry can trim laterally while preserving the photoresist height. H2/Ar provide some trimming but saturate quickly, pure Ar doesn't provide any trimming. All of the chemistries provide some line smoothing with H2/Ar providing the best smoothing.

Low Track Height Standard cell Design in iN7 using Scaling Boosters
The size of standard cells used in logic designs is determined by the Minimum Metal Pitch (MMP) multiplied by the track height multiplied by the Contacted Poly Pitch (CPP). With the difficulties being experience with scaling MMP and CPP track height has become an increasingly important factor in scaling. The problem with track height scaling is that as the number of tracks shrinks the number of fins per transistor is also reduced and without optimization the cell performance is degraded. In this paper, a 7.5-track cell is achieved by adding a Middle Of Line (MOL) layers for layout optimization, for a 6.5-track cell a fully self-aligned gate contact is added and finally a buried rail is used to achieve a 6-track cell. The 6-track cell is a full 45% smaller than the 7.5-track cell.Single Exposure EUV Patterning of BEOL Metal Layers On The IMEC iN7 Platform
The imec N7 (iN7) or foundry 5nm (F5) node has a 42nm M1 pitch with 24nm T2T, Via is 21nm x 32nm with a 42nm pitch and M2 is a 32nm pitch with 25nm T2T. Options for M1 are SADP with EUV block or single EUV exposure, via is single exposure EUV and M2 options are SAQP with EUV block or single exposure EUV. Figure 3 summarizes the advantages and challenges of single exposure EUV.

Figure 3. EUV trade-offs for Metal layers.

Single exposure EUV with litho and etch co-optimization can meet the needs of 1D M1 metal. For M2 single exposure can be used for gridded designs at 32nm pitch but further optimization is needed on logic designs.

EUV Final Thoughts
Greg had a few final thoughts on EUV.

EUV pellicles - CNT and coated, you can inspect through them with 193 inspection tools They are ramping up manufacturing now.

They are working on alternate absorbers for reticles. Going to nickel or cobalt can make the absorbers much thinner reducing 3D effects. The current reticles are OK for N7 and N5 but will need to be improved for N3.

Directed Self Assembly (DSA)
I told Greg I thought there was less interest in DSA at the conference and he said DSA momentum is down. He did note the following:

Defectivity is down - he thinks the chip - chemo epitaxial process has the potential to be used for memory.

DSA is also being looked at to "heal" roughness for EUV.

Also materials that pull apart more are being looked at to get below 20nm.