Modern multi-core microprocessors cannot function anymore without memory caches, in multiple layers, and multiple caches per microprocessor core. These caches must be kept in-sync, so that modern multi-threaded software can safely make use of multiple cores. Keeping these various caches in sync is done with a cache coherence protocol, implemented in hardware using state machines. One of the challenges when developing cache coherence protocols is the validation whether it is functioning correctly. To do this efficiently it is important to be able to analyse parts of the cache coherence protocol separately, together with for instance the communication infrastructure that is used between the various caches. We have developed a proces to extract the communication aspects from cache coherence protocols from a protocol description, en turn these into a more compact state machine. We have implemented this process in a tool, that makes it possible to minimize Gem 5 state machines. The output of this tool can then be used for subsequent research. With the results we have achieved with this tool we have supported the hypothesis that minimization of cache coherence protocols can be done automatically.