Motivations

This page collects all informations on how to use PREEMPT-RT soft realtime
extension with the Altera NIOS II softcore processor. We have made an effort
to propose this new port. With codesign, a new difficulty appears with flexibility
during codesign generation. This page proposes to give important informations
specially to this important part. Our wish is that your experience on PREEMPT-RT
for NIOS II will be successful!

Howtos

You must have a design for NIOS II with MMU enabled. You must
verify that you can boot a standard Linux kernel first on your board. Please
follow this documentation.

Hardware requirements:

We have added the hrtimer support. So you must in your SoPC
builder design add a full featured 64-bit timer named hrclock.

You must have finally 2 timers:

A 32-bit timer named sys_clk_timer (clock event fot PREEMPT-RT).

A 64-bit timer named hrclock (clock source for PREEMPT-RT).

Please respect the name of the timers...

Software requirements:

It was difficult to synchronize the Linux kernel version for
NIOS II with the PREEMPT-RT patch version for the vanilla Linux kernel. We have
decided to start from the vanilla Linux kernel instead from the Linux kernel
for NIOS II...

Ready to use:

Guides

Guide
d'utilisation de PREEMPT-RT sur processeur softcore NIOS II. Version 1.0.
French version

Limitations

This initial port gives some extra latency with some boards. The cache size,
MMU parameters and SoPC design have directly influence on latency.

We have detected extra latency of up to 1500 µs with a Stratix 1S10 board
with a dd stressing. The NIOS II processor
used in this design has just 512B On-Chip Memory, 8kB Instruction Master Cache
and 4kB Data Master Cache.

We have just latency of up to 650 µs with a Cyclone 3C120 board with
a dd stressing. The NIOS II processor used in this design has 1024B On-Chip
Memory, 32kB Instruction Master Cache and 32kB Data Master Cache.

The Linux port for NIOS II may surely be improved for reducing latency (arch/nios2/kernel/entry.S
file).

This port is surely perfectible. If you make improvements, you may contact
us...

Latency measurement

Latency can be measured with classical tools provided through cross compilation.
The principe is to generate a periodic thread and to measure difference between
the effectiv period and the theorical period that defines latency.

cyclictest
: latency is measured on a period of 10000 µs with a thread of the maximal
priority 99:

# cyclictest -n -p 99 -i 10000

nanosleep.c with the driver leds.c:
the latency measurements have been done with the scope. The principle of measurement
is to generate a cyclic period to an ouput (blinking a led) with a fixed period
for example 10 ms. With the scope, we take a look to the generated signal
and we measure the maximum latency on the descending front if the scope is
synchronized to the ascending front. You can find explaination in this paper.
Latency is measured with a scope on a period of 10000 µs with a thread
of the maximal priority 99:

Downloads

The following Altera SoPC designs for PREEMPT-RT are given as an example without
any guaranty and AS IS. You must purchase
Altera tools for regenerating files for programming your Altera FPGA of your
board.