PLL

Charge Pump PLL IP

Description

This Charge Pump PLL is designed in CMOS LP technology, using seven metallization levels. These voltage pulses are converted to current pulses in the Charge Pump. These current pulses charge or discharge the Loop Filter to generate the control voltage for the VCO. The VCO generates a frequency (FVCO) proportional to this control voltage. This frequency is then divided by the Loop Frequency Divider, to generate FBCLK.

Features

Input frequency (MHz): 19.2-40MHz

VCO frequency: 1500-3000MHz

Output frequency: PHI: 23.4375-1500MHz

Uses LVT and SVT devices in GO1 and SVT25 devices in GO2

Area: 0.1788 mm2 (Target) (X = 208 m, Y =860 m)

Maximum power: 15.22 mW

Fractional mode supported

Seven metal level technology used for design:

4X (thin) metals

0Y (intermediate) metals

2Z (thick) metals

Applications

Used in frequency synthesis applications

Deliverables

Detailed Specification and Integration guide

LEF abstract

GDSII layout and Mapping files

LVS compatible netlist

Verilog-A Model

Clock Generator (28nm) PLL IP

Description

Clock generator PLL is designed to multiply an input clock signal by an integer 40 and 50. The output is 2.5GHz with 50% duty cycle with quadrature phases. Available in TSMC90LP, TSMC 65G, TSMC 28HPC, GF 28SLP

Charge Pump PLL (CMOS40) IP

Description

On the basis of its architecture its belongs to the class of Charge Pump PLLs. The key blocks in this architecture are mentioned in the following sections.

Phase/Frequency Detector

This block compares the phase difference between the corresponding rising edges of INFIN(buffered version of the Input Frequency Divider output) and FBCLK (buffered clock output from the Loop Frequency Divider), by generating voltage pulses with widths proportional to the input phase error.

Charge Pump and Loop Filter

Charge Pump converts the voltage pulses from the Phase/Frequency Detector to current pulses, which charge the Loop Filter and generate the Control Voltage for the Voltage Controlled Oscillator.

Voltage Controlled Oscillator

This is the oscillator inside the PLL, which produces a frequency output (FVCO) proportional to the input control voltage.Loop Frequency Divider Frequency Divider is present within the PLL for dividing VCO frequency (FVCO) by a factor called the Loop Division Factor (LDF). The output of this block is the FBCLK.

Input Frequency Divider

This Frequency Divider divides the PLL input frequency by a factor called the Input Division Factor (IDF). The output of this block is INFIN.

Output Frequency Divider

PLL output PHI is generated by dividing the FVCOBY2 clock (VCO clock divided by 2) by a factor called Output Division Factor (ODF). The divider that divides the FVCOBY2 to generate PHI is called Output Frequency Divider.

Lock Circuit

LOCKP signal is asserted high when the PLL enters the state of Coarse Lock, in which the average output frequency (for last 64 cycles of INFIN) is within ±10% (approximately) of the desired frequency. LOCKP signal is refreshed after every 64 cycles of INFIN. This is generated based on the result of the comparison of number of FBCLK cycles in a window of 58 INFIN cycles. The different cases generated after comparison are the following: If LOCKP is at L, then it goes to H in the next refresh cycle, if the number of FBCLK cycles in the 58 cycle INFIN window is 52 to 64. Otherwise, LOCKP stays at L. If LOCKP is at H, then it goes to L in the next refresh cycle, if the number of FBCLK cycles in 58 cycle INFIN window is less than 48 or higher than 68. Otherwise, LOCKP stays at H.