However the SPI is double-buffered so as long as you keep the buffer full you shouldn't have any gaps between bytes in a sequence.

That is, fill the next byte to be sent when the TX buffer full flag is not set and read out the received data on the RX buffer not empty flag - don't do the Tx on the Rx buffer empty flag otherwise there may be a gap due to the internal synchronisation (which is probably always there on the start byte).

I was hoping that was not the case as there is a 4.26us delay after the cs goes low and the first spi clock and a 11.52us delay after the last spi clock before the cs returns high (12Mbit/s). i do however see the same 4.26us delay between bytes. this chip does not seem to have dma, is there any way to speed this up?

However the SPI is double-buffered so as long as you keep the buffer full you shouldn't have any gaps between bytes in a sequence.

That is, fill the next byte to be sent when the TX buffer full flag is not set and read out the received data on the RX buffer not empty flag - don't do the Tx on the Rx buffer empty flag otherwise there may be a gap due to the internal synchronisation (which is probably always there on the start byte).