Jackytr:
Xilinx,and others, have mixed signal FPGAs with analog ADCs, which are pricey. We are simply providing an alternative. For example, what if you are higher volume, are always cost cutting, and really only need a 10 bit ADC? You could use a lower cost part, our IP and save a bunch of money. What if you have a space application? The part you referred to is not rad hard or rad tolerant. With our IP you could essentially get a rad hard ADC on a rad hard FPGA very easily. Similar alternative exist now if you are looking to lower power and board space. Please let us know if you need more clarification.

RaulHuertas:Thank you for reading all of the other comments and thank you for your support. Your assumptions of how we arrive at our solution are in the ballpark. However, we do lot more in our implementation which results in higher performance, such as improved resolution and bandwidth with a significantly slower clock. I think some of the confusion in the comments comes from us doing a poor job of explaining where we are innovating. We thought that providing performance results would be enough, and that readers could check the numbers against the published papers (many of which were cited by commentors). We could have probably called that out better, but we didn't want to seem like we were putting down anyone else's innovations. When you look at the performance numbers it becomes quite obvious that something unique is happening there. We are in talks with several of the FPGA companies and we can not comment further about how it works. Thanks again for your support, and please contact us if we can assist you or a customer in any way.

I'm trying to descipher how it works. The no LVDS output must be a PWM output, and the R-C ladder must be a low-pass filter. LVDS must be used as a comparator right? and the processing is successive aproximations... ingenious!. PWM resolution limits ADC resolution, and the band pass filter must limit sample rate. Now I gonna read all your posted references my friends. bye! thank you!

All the digital components of Stellamar’s ADCs implemented in FPGAs or ASICs are used in compliance with the digital specs and therefore in the digital domain. The power supply for the ADC I/Os needs to have the accuracy and stability for the required resolution. Also, the ADC I/O cells need to have a separate power supply. The output cells are selected to drive the filter load properly, thus allowing to achieve the required performance.

The key feature of Stellamar’s ADC is that it can be embedded in totally digital chips such as FPGAs. This is what we tried to capture with the name “all digital.” We could have called it "Almost All-Digital ADC" or "Mostly Digital ADC" as Max suggested or maybe, following your examples, “99% Digital ADC.” However people would have asked us immediately : “What does Almost All Digital or Mostly Digital mean? Is it equivalent to Fully Digital? How did you come up with 99% Digital?
After all as Shakespeare said "What's in a name? That which we call a rose by any other name would smell as sweet."

And another thing: it is implied that using parts nominally associated with the symbol domain means the design is thus digital. But that's silly. I can use any number of gates, flip flops, etc. in a design, whether part of an FPGA or in individual packages, and the determination of what is digital is determined by HOW the parts are used. If at some point in such a circuit, the precise voltage levels and other parameters are important to the function, then there I am using that part in the analog domain! If the system shrugs off parameter variations as long as the 1's and 0's are correctly recognized, then the part is being used in the digital domain.
The final output from the FPGA driving the filter network is, functionally, an analog output. Levels, timing, rise/fall times matter.

Dear mngardon, I think you are missing the point some are making. Your design is not all digital, it is maybe 99% compared to 98 or 97% (figures just for purposes of explanation) on another design. 100% would be the signal goes onto a standard digital input buffer and comes out as a data word somewhere. ANY R's and C's anywhere (apart from supply line decoupling) and any controllable thresholds and you've just left the digital domain. I'm not trying to detract from your actual achievement, just clarifying a point.