Design Space Re-Engineering for Power Minimization in Modern Embedded Systems

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Abstract

Power minimization is a critical challenge for modern embedded system design. Recently, due to the rapid increase of system's complexity and
the power density, there is a growing need for power control techniques at various design levels. Meanwhile, due to technology scaling, leakage power has become a significant part of power dissipation in the CMOS circuits and new techniques are needed to reduce leakage power.
As a result, many new power minimization techniques have been proposed such as voltage island, gate sizing, multiple supply and threshold voltage, power gating and input vector control, etc. These design options further
enlarge the design space and make it prohibitively expensive to explore
for the most energy efficient design solution.
Consequently, heuristic algorithms and randomized
algorithms are frequently used to explore the design space, seeking sub-optimal
solutions to meet the time-to-market requirements. These algorithms are
based on the idea of truncating the design space
and restricting the search in a subset of the original design space. While this approach can effectively reduce the runtime of searching, it may also exclude high-quality design solutions and cause design quality degradation.
When the solution to one problem is used as the base for another problem, such solution quality degradation will accumulate. In modern electronics system design, when several such algorithms are used in series to solve problems in different design levels, the final solution can be far off the optimal one.
In my Ph.D. work, I develop a {\em re-engineering} methodology to
facilitate exploring the design space of power efficient embedded systems design.
The direct goal is to enhance the performance of existing low power
techniques. The methodology is based on the idea that design quality can be improved
via iterative ``re-shaping'' the design space based on the ``bad'' structure
in the obtained design solutions; the searching run-time can be reduced
by the guidance from previous exploration. This approach can be
described in three phases: (1) apply the existing techniques to obtain
a sub-optimal solution; (2) analyze the solution and expand the design
space accordingly; and (3) re-apply the technique to re-explore the
enlarged design space.
We apply this methodology at different levels of embedded system design to
minimize power: (i) switching power reduction in sequential logic synthesis;
(ii) gate-level static leakage current reduction; (iii) dual threshold voltage CMOS
circuits design; and (iv) system-level energy-efficient detection scheme for
wireless sensor networks. An extensive amount of experiments have been conducted
and the results have shown that this methodology can effectively enhance
the power efficiency of the existing embedded system design flows with very little
overhead.