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Measurement of Setup/Hold and Resolution Time of a Flop on Silicon

Publishing Venue

The IP.com Prior Art Database

Abstract

Characterization for flip-flop (FF) setup/hold is a costly process in terms of runtime and storage. Yet there is no architecture to correlate liberty file numbers directly with silicon numbers. Resolution time for a FF is not characterized at all even for liberty files. This paper presents a ring oscillator based architecture for “On chip measurement of setup/hold & resolution time” that requires minimum manual intervention for different iterations.

Country

India

Language

English (United States)

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This is the abbreviated version, containing approximately
35% of the total text.

Measurement of Setup/Hold
and Resolution Time of a Flop on Silicon

Abstract— Characterization
for flip-flop (FF) setup/hold is a
costly process in terms of runtime and storage. Yet there is no architecture to
correlate liberty file numbers directly with silicon numbers. Resolution time
for a FF is not characterized at all even for liberty files. This paper
presents a ring oscillator based architecture for “On chip measurement of setup/hold
& resolution time” that requires minimum manual intervention for different
iterations.

Keywords—Metastability, Setup and hold time
measurement.

I. Introduction

Setup time and hold time numbers
mentioned in the liberty files are done in an iterative way. Clock edge is swept
from infinity to a point with respect to the data edge wherein the clock to q
delay (tcq) for a flop tends to degrade. When the degradation is around 30-40
percent, the skew between the data and clock edges is defined to be as the
setup time. When a transition starts failing to get captured, the skew between
the data and clock edges is defined as hold time.

To figure out these “When”, an
iterative process is required, wherein simulations are performed for different
skews between “CLK” & “DATA” pins of a flop.

Figure 1 depicts the phasor relationship between “CLK”
& “DATA” pins of a flop during metastability.

Figure 1 : Phasor relation
during Setup/Hold time violations.

Currently we don’t have an
architecture that can co-relate silicon no’s with the simulated no’s present in
liberty files for setup/hold. If we try to emulate the characterization
methodology adopted in simulation, then we will end up with a circuit which
requires many iterations & manual intervention per iteration.

Resolution time characterization
is done neither at silicon nor at simulation level which is necessary for model
enhancements & tightening the parameter knobs w.r.t “ﺡ” (resolution time constant).

A ring oscillator based structure
is proposed to

a) Automatically
create an iterative set of phasor relation for metastability condition.

b) Measure
resolution time of a flop during metastability.

The
paper is organized as follows: In section II, we described the conventional
ring oscillator made from a sequential element to measure its access time. In section
III, we formulated the RO frequency and described the symptom for onset of
metastability. In section IV, we presented the proposed architecture which can
measure the setup, hold and resolution time for a flop on silicon. In section V,
we described Skew measurement circuit which was an integral sub-component of
our proposed architecture. In section VI, we described DATA delay line used as
a skew generating circuit. In section VII, we described the measurement process
through a flowchart. In section VIII, we concluded with the application of
proposed art.