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Can someone help me figure out where does power analysis of Cadence Encounter RTL Compiler comes from

Started by Haoxiang on 6 Mar 2014 10:06 AM. Topic has 10 replies and 70589 views.
Last post on 11 Sep 2015 12:54 AM by ajay01.

Hi all,

New to this area, I have two questions that need your help.

1st, when I get the power analysis from Cadence Encounter RTL Compiler, It automatically shows Leakage, Internal, Net and Switching Power of the generated schematic. But then I get comfused, under which input pattern does the Compiler infer all the power values, especially switching power, since it's directly related to the frequency of input?

2nd, what's the difference between Leakage Power and Internal Power? And does Net Power means power consumed from the interconnect? I get confusion about these terms

10 Replies

1.Generaly basic power information come from .lib .like how much leakage when cell have different-different logic.for each cell in stander cell lib. and other information come from collapsed/port view of standered cell and macro.

Hi Ajay,
I have the same question with the power consumption results in RTL Compiler. I found your reply really helpful. But I still have 2 further questions about it:
1. As to the dynamic power, how does the RTL Compiler define the working frequency?
2. About the leakage power, what's the file in the standard cell library that defines it in different situations?
Looking forward to your reply! Thank you very much!
Best,
Zhaojun

1.As i mentioned,Dynamic power is the sum of two factors: switching power plus short-circuit power.Switching power is dissipated when charging or discharging internal and netcapacitances. Short-circuit power is the power dissipated by an instantaneous shortcircuitconnection between the supply voltage and the ground at the time the gateswitches state.Pswitching = a .f.Ceff .Vdd2Where a = switching activity, f = switching frequency, Ceff = effective capacitance,Vdd = supply voltagePshort-circuit = Isc .Vdd.fWhere Isc = short-circuit current during switching, Vdd = supply voltage,f = switching frequency

As we will go ahead in technology we required chip should work faster means frequency will increase.So as shown above equation dynamic IR drop increase.For that we are using Low Power Techniques and CPF flow.So RTL compiler set frequency based on requirement and leakage calculation and technicians which will be used during Physical implementation.

2. In standard cell library that defines as below:consider its a buffer.Then it will define leakage power when logic A and !A.And internal power At pin A.full table.Like that for all std. cell power define with different logic.

Hi Ajay,
Thank you so much for your answers! I found it really helpful to understand the RTL Compiler.
Then in order to satisfy different purposes like low power consumption, small area, etc. , are we able to change synthesis mode? I didn't find any CPF file in my rc directory, so in this case, what's the default synthesis frequency and input types?

Hi Ajay The information that u have provided is very helpful but my doubt is that how the internal power is calculated using .lib file of standard cell. because .lib file have internal power table 6*6 based on input transition time and capacitance value. so what is default value the we have choose when we didn't give any input in Encounter RTL compiler.

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