Main Group

*RISC-V Main Members Group*.
*Please note* that all of the subgroups here are moderated, members-only discussions related to the development of the RISC-V ISA. If you are looking for the public RISC-V mailing lists, please visit https://groups.google.com/a/groups.riscv.org/forum/#!forumsearch/
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Technical Committee

Welcome to the RISC-V Technical Committee secure area. In this section of the RISC-V Foundation workspace you will find meeting minutes, showings, reports, schedules, and project descriptions compiled by the Technical Committee, updated on a regular basis. Some areas are under construction, awaiting further developments, but all areas are included to indicate the future direction of the site. Access to this area is restricted to members of the Technical Committee (primary/alternate/observer) and the Board of Directors. Please keep watching this space for new information and developments.

The BitManip work group will define extensions to the Unprivileged ISA that are comprised of bit-based instructions. These extensions are intended to enable the development of code that is substantially more performant and efficient that what is possible with the base instructions. Performance testing will be conducted by compiling or hand-assembling routines and then measuring performance improvement in a RISC-V modelling environment. Where possible, all or portions of standard benchmark tests will be employed in this testing. The new instructions will include operations from one or more of the following categories: bit counts, shift/rotate, insert/extract, set/clear, permute, and logical/mask. A base extension will include commonly used functions that are simpler to implement. An extended extension will be proposed should there be instructions that provide even more performance and power savings at a cost of more complexity.

The Cryptographic Extensions Task Group will propose ISA extensions to the vector extensions for the standardized and secure execution of popular cryptography algorithms. To ensure that processor implementers are able to support a wide range of performance and security levels the committee will create a base and an extended specification. The base will be comprised of low-cost instructions that are useful for the acceleration of common algorithms. The extended specification will include greater functionality, reserve encodings for more algorithms, and will facilitate improved security of execution and higher performance. The scope will include symmetric and asymmetric cryptographic algorithms and related primitives such as message digests. The committee will also make ISA proposals regarding the use of random bits and secure key management.

Welcome to the RISC-V Debug Task Group secure area. The Debug Task Group's goal is the ratification of a specification for how to enable low-level hardware debugging on RISC-V implementations. In this section of the RISC-V Foundation Workspace you will find meeting minutes and slides, updated on a regular basis. Access to this area is restricted to members of the Debug Task Group. For updates, keep an eye on this space and the task group mailing list:debug@workspace.riscv.org. Success Criteria: A Foundation-Ratified Specification for Run/Halt debug of RISC-V based systems. This is desired by the 8th RISC-V Workshop in Barcelona, May 2018. Auxiliary Goals: Reference implementations & reference SW implementations, Documented SW conventions for debug-related tasks; Explicitly Out of Scope: Trace specification

This group will produce a Formal Specification for the RISC-V ISA. This is a specification of the ISA in a formal language, for precision, unambiguity, consistency and completeness. It should be readable and understandable as a canonical reference by practising CPU architects and compiler writers. It should executable and machine-manipulable for use in formal tools for establishing correctness and transformations in both compilers and CPU designs. [ This work is closely related to and complementary to the work of the Memory Model Task Group ]

The RISC-V J extension aims to make RISC-V an attractive target for languages that are traditionally interpreted or JIT compiled, or which require large runtime libraries or language-level virtual machines. Examples include (but are not limited to) C#, Go, Haskell, Java, JavaScript, OCaml, PHP, Python, R, Ruby, Scala or WebAssembly. Among other topics, the group expects to collaborate with several existing RISC-V extension working groups.

The memory model task group charter is to define the memory consistency model for the RISC-V architecture, to produce relevant documentation and supplementary material (such as formal mathematical specifications and compliance test cases), and to work with the other task groups to ensure their own specifications remain compatible with the memory model.

The OpCode Space Management Task Group is a standing group with the task of allocating reserved opcode space for new proposed standard extensions. The group works with task groups developing new standard extensions to avoid conflicts with other current and planned future extensions.

Define and ratify Packed-SIMD DSP extension instructions operating on XLEN-bit integer registers for embedded RISC-V processors. The TG will also define compiler intrinsic functions that can be directly used in high-level programming languages.

CHARTER FOR DEFINITION OF SV128 FOR RISC-V ARCHITECTURE
Using minicomputers as a starting point, logical addresses from the early to late 70’s grew from 16 to 32 bits. The main driver was main memory dram technology increases. In the early 90’s, the logical address space increased to 64 bits. Again, the main driver was the main memory dram technology increases. Today, in addition to increases in main memory technologies, the creation of cluster and node multicomputer systems has resulted in a step function in memory capacities. This coupled with newer contemporary memory reference models such as PGAS and WEB based referencing models, as well as the introduction of non-volatile memory, results is the need to define SEMANTICS for data references. This contrasts with previous logical address expansion that extended the address space (flat addressing).
Consequently SV128, should be capable of BOTH globally, directly referencing memory, independent of the underlying system architecture, as well as incorporating contemporary security models. Additionally, compatibility with existing RV32 and RV64 executable images need to be supported. As part of this effort, where ever possible, formal methods should be utilized.
The SV128 working group, will define a 128 virtual address space in 6 months.

The mission of RISC-V trusted execution environment working group are:
To define an architecture specification to support trusted execution environment for RISC-V processors
To provide necessary implementation guidelines and/or recommendations to assist hardware developers to realize the specification
To enable the development of necessary components, such as compiler, simulation model, hardware, and software components to support the specification

The group shall standardize both a hardware interface to the RISCV core and a packet/data format which will enable the development of commercial and open source trace encoders to be supported by any tools vendors. The interfaces are to provide enough information for: Instruction Trace. The interfaces should be suitable for in-order and out-of-order cores with extensions. The group will standardize the data format for: Compressed branch trace so that program flow can be reconstructed by debugging tools. The group’s progress shall be evaluated after one year at which time the charter may be revised if necessary to narrow the scope of effort.

The V Extension Task Group is tasked with developing the specification for the RISC-V base V vector extension, including written documentation, executable model, and compliance suite. The group is also responsible for outlining how future vector extensions can build on this baseline.

Marketing Committee

Welcome to the RISC-V Marketing Committee. In this section you will find a calendar for upcoming meetings along with documentation relating to our efforts to drive awareness and outbound messaging on RISC-V.
Chair: Ted Marena
Vice-Chair: Don Barnetson

The aim of Marketing Content Task Group is to drive the content creation and curation efforts for RISC-V marketing, making sure that relevant information is available, well presented, clear and comprehensive. The Content TG recommends activities related to e.g. the RISC-V website, newsletters, training material, and the Foundation's internal communication.

DRAFT Charter
1. Identify targeted market research on RISC-V which would be of interest to the RISC-V membership at large.
2. Facilitate and support research by 3rd party analyst firms on selected topics.
3. In conjunction with Racepoint and Foundation staff, liaise with market researchers and analysts who are preparing RISC-V related reports.
(Note: At this time, it is anticipated that the targeted research will not be funded or sponsored by the foundation or by member sponsorships. Rather, the resulting reports will be offered for a fee by the research organizations).

Building on the RISC-V Foundation’s growing footprint in China across more than 25 organizations and universities, the China Advisory Committee will guide the RISC-V Foundation’s education and adoption strategies to further accelerate the RISC-V ecosystem in the region. Participation in this committee is open to foundation members who have significant China-based operations.

RISC-V Security Standing Committee
Main Goals:
● Promote RISC-V as an ideal vehicle for the security community
● Liaise with other internal RISC V committees and with external security committees
● Create an information repository on new attack trends, threats and countermeasures
● Identify top 10 open challenges in security for the RISC-V community to address
● Propose security committees (Marketing or Technical) to tackle specific security topics
● Recruit security talent to the RISC-V ecosystem (e.g., into committees)
● Develop consensus around best security practices for IoT devices and embedded systems