Just to remind you that the complete CMOS fabrication process, we are not discussing in a single post. Complete CMOS fabrication, I have divided into different post as per above table.

Let’s start where we have left in the last post (3D view of the wafer).

Please follow the following steps, to create the Contact and the M1 Interconnects.

Final 3D View of silicon wafer.

Till Now we have created

Nwell

Active Region

Channel Stop Region

Field Oxide.

Gate Oxide

Poly layer.

N+ regions (Source and Drain) for NMOS device.

P+ regions (Source and Drain) for PMOS device.

Metal Contact and Metal M1.

Below the Metal 1 fabrication, the Process is known as FEOL (Front-End-Of-Line) process. After the last FEOL step, there is a silicon wafer with isolated transistors (without any wires). In BEOL (Back-End-Of-Line) part of fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. Details of FEOL and BEOL – theory we will discuss in next few post.

Till now in all the above few post we have discussed the Side view of the MOSFET (CMOS) fabrication for better understanding for creating different geometries. But in real world, VLSI designer don’t use this view for designing purpose. We as a VLSI designer always use CAD tools for designing the MOSFET shapes and in the CAD tools we always talk about the TOP VIEW. In the next post we will summarize TOP view along with the Side View along with the process of creating the CMOS inverter with the help of CAD tools.

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