Suigen Kyoh

Suigen Kyoh, Kanagawa-Ken JP

Patent application number

Description

Published

20110097827

PATTERN FORMATION METHOD AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - In one embodiment, a pattern formation method is disclosed. The method can place a liquid resin material on a workpiece substrate. The method can press a template against the resin material and measuring distance between a lower surface of a projection of the template and an upper surface of the workpiece substrate. The template includes a pattern formation region and a circumferential region around the pattern formation region. A pattern for circuit pattern formation is formed in the pattern formation region and the projection is formed in the circumferential region. The method can form a resin pattern by curing the resin material in a state of pressing the template. In addition, the method can separate the template from the resin pattern.

04-28-2011

20110159440

CLEANING RETICLE, METHOD FOR CLEANING RETICLE STAGE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In one embodiment, a method for cleaning a reticle stage of an extreme ultraviolet exposure apparatus is disclosed. The method can include pressing a particle catching layer of a cleaning reticle onto the reticle stage, and the cleaning reticle includes the particle catching layer formed on a substrate. The method can include peeling the cleaning reticle from the reticle stage. The method can include removing the particle catching layer from the substrate. I addition, the method can include forming a new particle catching layer on the substrate having the particle catching layer removed.

06-30-2011

Suigen Kyoh, Yokohama-Shi JP

Patent application number

Description

Published

20090031262

MASK PATTERN FORMATION METHOD, MASK PATTERN FORMATION APPARATUS, AND LITHOGRAPHY MASK - A mask pattern formation method and apparatus capable of performing OPC and lithography verification and obtaining OPC result, and a lithography mask are provided. The method of forming a mask pattern from a design layout of a semiconductor integrated circuit comprises inputting a design layout, performing first OPC on the design layout, calculating a first evaluation value for a finished planar shape of a resist pattern corresponding to the design layout based on the first OPC, determining whether the first evaluation value satisfies a predetermined value, if the first evaluation value does not satisfy the predetermined value, locally altering the design layout, performing second OPC on the altered design layout, calculating a second evaluation value for the altered design layout, performing second determination, and if the second evaluation value satisfies the predetermined value, outputting the result of OPC and the first and second evaluation values.

01-29-2009

20090037852

PATTERN DATA GENERATION METHOD AND PATTERN DATA GENERATION PROGRAM - A pattern data generation method of an aspect of the present invention, the method includes creating at least one modification guide to modify a modification target point contained in pattern data, evaluating the modification guides on the basis of an evaluation item, the evaluation item being a change in the shape of the pattern data for the modification target point caused by the modification based on the modification guides or a change in electric characteristics of a pattern formed in accordance with the pattern data, selecting a predetermined modification guide from among the modification guides on the basis of the evaluation result of the modification guides, and modifying the modification target point in accordance with the selected modification guide.

02-05-2009

20090199148

Pattern-producing method for semiconductor device - Disclosed is a method of producing a pattern for a semiconductor device, comprising extracting part of a pattern layout, perturbing a pattern included in the part of the pattern layout to generate a perturbation pattern, correcting the perturbation pattern, predicting a first pattern, to be formed on a wafer, from the corrected perturbation pattern, acquiring a first difference between the perturbation pattern and the first pattern, and storing information concerning the perturbation pattern including information concerning the first difference.

08-06-2009

20090293038

METHOD AND CORRECTION APPARATUS FOR CORRECTING PROCESS PROXIMITY EFFECT AND COMPUTER PROGRAM PRODUCT - A process proximity effect (PPE) correction method includes providing corrected cells arranged in a place/route arrangement, the corrected cells being obtained by correcting design data of a semiconductor device based on correction value for correcting PPE correction, determining whether a cell arrangement of the corrected cells is registered or not based on environmental profiles, conducting lithography verification if the corrected cells includes the cell arrangement not registered in the environmental profiles, the verification being performed on the corrected cells, wherein the corrected cell to be conducted the verification corresponds to the cell arrangement not registered, determining whether error is found or not in the verification, correcting the corrected cell to which the verification is conducted if the error is found and registering the cell arrangement in the environmental profiles, and registering the cell arrangement of the corrected cell if the error is not found.

11-26-2009

20090306805

SEMICONDUCTOR DEVICE PRODUCTION CONTROL METHOD - A semiconductor device production control method includes monitoring, after a production process of a semiconductor device, a process result at a predetermined position of a pattern to which the process is applied, to obtain a deviation with respect to a predetermined target result, quantitatively obtaining a degree of influence on an operation of a semiconductor device from the deviation of the process result, and comparing the degree of influence that is quantitatively obtained with a predetermined allowable margin for operation specifications of the semiconductor device.

12-10-2009

20100037193

METHOD OF CORRECTING PATTERN LAYOUT - A method of correcting a pattern layout includes: executing a process simulation under a plurality of conditions in which variations in a process parameter for forming a pattern corresponding to a design layout on a substrate are reflected, thereby estimating a plurality of finished patterns of the pattern; calculating dimensions of the plurality of the finished patterns; calculating a statistical amount from the calculated dimensions; comparing the statistical amount with a preset specification; calculating a correction amount when the specification is not satisfied; and correcting the design layout based on the calculated correction amount.

02-11-2010

20110065027

FLARE CORRECTION METHOD, METHOD FOR MANUFACTURING MASK FOR LITHOGRAPHY, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In one embodiment, a flare correction method is disclosed. The method can acquire a flare point spread function. The method can calculate a pattern density distribution in a first region of the mask, the distance from the pattern being equal to or shorter than a predetermined value in the first region. The method can calculate pattern coverage in a second region of the mask, the distance from the pattern being longer than the predetermined value. The method can calculate a first flare distribution with respect to the pattern by performing convolution integration between the flare point spread function corresponding to the first region and the pattern density distribution. The method can calculate a flare value corresponding to the second region by multiplying a value of integral of the flare point spread function corresponding to the second region by the pattern coverage. The method can calculate a second flare distribution by adding the flare value to the first flare distribution. In addition, the method can correct the pattern based on the second flare distribution.

03-17-2011

20120002181

EXPOSURE CONTROL SYSTEM AND EXPOSURE CONTROL METHOD - According to one embodiment, an exposure control system includes an overlap judgment unit that judges whether a position of a foreign matter that adheres to a back surface of a photomask overlaps a position of a chuck that holds the photomask when the photomask is held by the chuck, and an exposure decision unit that decides to hold the photomask by the chuck and perform exposure, when it has been determined that the position of the foreign matter does not overlap the position of the chuck.

01-05-2012

Patent applications by Suigen Kyoh, Yokohama-Shi JP

Suigen Kyoh, Kanagawa JP

Patent application number

Description

Published

20100067777

EVALUATION PATTERN GENERATING METHOD, COMPUTER PROGRAM PRODUCT, AND PATTERN VERIFYING METHOD - An evaluation pattern generating method including dividing a peripheral area of an evaluation target pattern into a plurality of meshes; calculating an image intensity of a circuit pattern when the evaluation target pattern is transferred onto a wafer by a lithography process in a case where a mask function value is given to a predetermined mesh; calculating a mask function value of the mesh so that a cost function of the image intensity, in which an optical image characteristic amount that affects a transfer performance of the evaluation target pattern to the wafer is set to the image intensity, satisfies a predetermined reference when evaluating a lithography performance of the evaluation target pattern; and generating an evaluation pattern corresponding to the mask function value.

03-18-2010

20100081294

PATTERN DATA CREATING METHOD, PATTERN DATA CREATING PROGRAM, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A pattern data creating method according to an embodiment of the present invention comprises: extracting marginal error patterns using a first result obtained by applying process simulation to mask pattern data based on an evaluation target cell pattern, applying the process simulation to mask pattern data based on an evaluation target cell pattern with peripheral environment pattern created by arranging a peripheral environment pattern in the marginal error patterns such that a second result obtained by creating mask pattern data and applying the process simulation to the mask pattern data is more deteriorated than the first result, and correcting the evaluation target cell pattern or the mask pattern data based on the evaluation target cell pattern when there is a fatal error.