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ZL2PD Programmable CMOS Clock Generator

Several CMOS ICs
are used to create a programmable digital clock reference for use with
frequency counters and other digital circuits. Several different
versions are described.

These designs were originally published in
'Break-In', New Zealand's amateur radio magazine in Sept/Oct 2009, and
are republished here with the permission of the editor.

Note: 'Break-In' is a term used in amateur
radio to describe a system which allows another person's signal to be
heard in the brief intervals between transmitted Morse Code symbols.

Introduction

Digital
clock generators form the ‘beating heart’ or 'time keeper' in a number
of circuits such as tone generators, frequency counters, and A/D
converters. Many chips these days include the necessary internal clock
generator circuitry. For the remainder, if you have complete design
freedom, it’s easy to select and source a single chip for such tasks.
Unfortunately, such “ideal” parts are becoming hard to purchase,
particularly in the tiny volumes required for hobbyist use.

For unusual clock frequencies, such as the two frequencies I wanted for
my digital dial, it’s typical to use a
crystal oscillator followed by a divider chain. In this case, it’s
possible to use a string of 74LS390 divide-by-10 chips or one of the
4020/4040/4060 CMOS binary dividers, for example, and a crystal of some
suitable multiple. Unfortunately, this inevitably raises the next
obvious problem - Locating the necessary crystal which often must be on
some equally unusual, albeit higher, frequency.

What I was wanted was a digital clock generator design which would
allow me to use almost any crystal I had in my junk-box and which used
cheap, easy to find parts.

This article describes my solution to this problem. Actually, it
describes two similar solutions. In this case, I was looking for a
method to provide two non-standard clock frequencies of 31.25 and 29.85
Hz. While other options exist, the solution described here may also be
a useful programmable clock generator solution for a number of other
applications. In addition, it only uses a few standard easy-to-find
CMOS chips.

Available Options

When
designing a system to deliver a square wave at some frequency, there
are a number of choices. These include:

The microprocessor is the most obvious solution for this requirement,
and it can be quite inexpensive. For example, an 8-pin PIC chip or a
similar sized PICAXE device are almost ideal. The latter devices can be
programmed in a simple version of the BASIC programming language,
making them easier for beginners to use.

The disadvantage of using any form of microprocessor is the need for a
PC, a programming interface of some sort, and some specialized
software. For many, there can be a forbidding and largely uncertain
learning curve to be overcome in order to achieve a satisfactory result
from a microprocessor. Also, despite the low cost of the
microprocessor, the startup costs for the items noted as well as
initial kits of software CDs, cables, boards and other hardware
necessary to get started can also be surprisingly high.

There is also the potential for relatively high levels of RF
interference to be generated by some microprocessors. This can be quite
a problem to resolve. In my case, I wanted to use the clock in a
digital dial for an HF transceiver so I was keen to avoid any such
problems. While it is true that any form of square wave clock source
can become an interference source, some microprocessors can be
particularly bad offenders in this respect.

The ideal solution for my application was the next option, one of the
relatively recent programmable clock chips from companies such as Cypress (See
Reference 1 - References are listed at the bottom of this page). These
chips are used as programmable clock sources in PCs and other devices.
Several software defined radios (SDR) also make use of these. The
difficulties with these chips include obtaining the required parts, as
well as the various hardware/software accessories required to program
or use them. While their features, cost and performance makes them
ideal for use, these factors sadly pushed this option out of contention
for my application.

The third alternative was to use standard CMOS chips. While easier to
purchase, the resulting design was inevitably going to be physically
larger than either of the previous options. However, CMOS parts are
usually still able to be purchased, and it doesn’t require a PC and
software to get the circuit going. Generally, then, for the hobbyist at
least, this is an acceptable compromise. This was the approach chosen
for this design.

Design Options

Two
designs are shown in some detail here, beginning with a three CMOS chip
design. This was later simplified to a “two chip plus transistor”
design. Both are shown here to permit the selection of a design for
your application. Both feature standard and inverted square wave
outputs. This was required for my digital dial, and it’s a common
requirement for a number of other applications.

The three chip design is designed around a CD4040 CMOS binary divider
chip. This offers division ratios across the entire range from 1 to
2048. The second design, using two chips and a transistor oscillator,
is designed with the similar CD4060 CMOS chip. This offers a wider
division ratio, up to 16384. While it allows the use of a greater range
of crystal frequencies, the CD4060 importantly omits several divider
outputs. This results in gaps in crystal frequencies which can be used
to generate specific clock frequencies, or gaps in output frequencies
available from specific crystals. Same issue - It just depends which
way you look at it!

I developed a simple Excel spreadsheet
to help me cope with this issue. Of course, this requires the use of a
PC and software…. As I’ll show later, a pencil and paper can also be
used to figure out settings for any available crystals to give a
required clock output, albeit at the cost of more of your time.

Three Chip Version

Figure
1 shows the three-chip design. It uses a 4001 as the crystal
oscillator, a 4040 binary divider, and a 4027 flip-flop used to reset
the 4040 counter when a specific divider has been reached. The 4040
outputs go logic-high when a specific divider ratio has been reached.
Diodes are used to logic-OR selected outputs to produce any required
division ratios up to 4096. The second flip-flop in the 4027 package
delivers a precision square wave output with equal on/off cycle times.
As mentioned earlier, the 4027 also produces both normal and inverted
outputs.

Figure 1 : Three chip version using a CD4040 binary divider supports
divider ratios up to 2048

Several designs along similar lines may be found on the internet. These
designs will prove traps for the unwary. For example, they avoid the
use of proper clocking for resetting the binary divider chip. Instead,
they resort to delaying the reset pulse through one or more spare CMOS
gates, or use a capacitor on the reset line to extend the reset pulse
to permit the chip to reset properly.

Both methods tend to be problematic. The values of such capacitors have
to be adjusted to suit various crystal frequencies, and neither method
works perfectly with higher speed HC4040 and HC4001 CMOS devices.
Problems include odd and erratic division ratios, and high rates of
jitter on square wave outputs.

The use of edge-triggered reset methods with the CD4027 shown here
resolves these problems, even with highest crystal frequencies I tried,
around 33 MHz.

A further
minor change is required depending on the frequency of the crystal
used. Figure 2 shows the changes required when using very low frequency
‘tuning fork’ type resonators. The two most commonly available
resonators are 32768 Hz watch or clock crystals, and 38.0 kHz crystals,
mostly used for remote control applications.

Two Chip Version

I
wanted to reduce the number of chips to reduce the required PCB area.
While I would have liked to find a totally reliable and repeatable
single standard CMOS chip solution, the best I could come up with uses
these two chips, along with a simple single transistor oscillator
stage. This is shown here in Figure 3.

Figure 3 : Two chip version with the CD4060 supports divider ratios up
to 16384

While using more parts overall, the PCB area
was reduced, and arguably, the cost is probably lower too, since
transistors are commonly found in the junk-box while the CMOS ICs you
want just never seem to be on-hand when required.

This version also uses the CD4060 binary divider. As noted earlier,
this extends the maximum division ratio to 16384, but with the loss of
the outputs for the first four divider stages (2, 4 and 8) inside the
chip as well as the output from the ‘mid-range’ 2048 divider.

At first glance, the requirement for a separate transistor oscillator
stage might appear strange, since the 4060 has an on-chip oscillator.
Unfortunately, the reset input on the 4060 not only resets all of the
divider stages, which is desirable, it also halts the oscillator, which
is most definitely not! So, an external oscillator stage is necessary.

I tested two different versions of the transistor oscillator. The
alternate version is required for use with low frequency ‘tuning fork’
32768 Hz and 38 kHz resonators. This schematic is shown in Figure 4.
Both oscillators are quite reliable, working with both standard and
higher speed HC CMOS devices. Some other transistor oscillator designs
reported as being suitable for CMOS did not work reliably for me when
tested with one or other CMOS logic family type.

Design Example

While a
spreadsheet is available here, this
section describes the ‘pen and paper’ design approach to using these
two designs. In this example, I’ll show how I configured the 4060
two-chip version for the 33.5 mS cycle time square wave I needed for my
digital dial.

Note: These were just the ones available from my junk box. The latter
two ceramic resonators are typical of those found in TV and video
remote controls. Other readers will probably have other crystals,
ceramic resonators, and ‘tuning fork’ type crystals.

Method:

1. Divide each available crystal frequency by the
required output frequency

i.e. Crystal
frequency (Hz) / Required output frequency (Hz)
= Result

2. Find one of these results which is an integer, or
at least very close to an integer value

3. Check if the integer value can be supported by the
binary divider you have selected

Check 38 kHz:

Closer evaluation of the 38 kHz crystal option shows that the available
division ratios are limited to results of 1264 and 1280 (i.e. 1024 +
128 + 64 + 32 +16 = 1264 and 1024+256 = 1280). To set the resulting
outputs to the correct value would require the 38 kHz crystal to be
tuned by about 200 to 300 Hz. Tuning fork type crystals just cannot shift that far, say by
adjusting the values of the oscillator capacitors, at least with this
circuit. So, the 38 kHz option was rejected.

Check 500 kHz:

For the 500 kHz resonator option, the nearest
divider ratios of 16384, 256, 64, 32 and 16 = 16752. An exact output of
29.85075 Hz requires a slightly adjusted crystal frequency of 500.05
kHz. This is well within the adjustment range of a ceramic resonator.
Testing confirmed this was a suitable option, and the 500kHz resonator
was used in the final circuit.

Note: In fact, since the actual frequency of 500 kHz ceramic resonators
can be varied by up to 5% by varying the capacitor values in the
oscillator, divider ratios of 16384, 256 and 16 (16384+256+16 = 16656)
was the setting finally used. This requires fewer diodes. The resonator
was able to be adjusted to about 497.19 kHz to give the required output
clock frequency of 29.85075 Hz, and that was the final configuration
used in the digital dial.

References

1.
See www.cypress.com and follow
the links to the programmable oscillator chips. One example of many is
the CY22392 device.