Metrology tools are increasingly challenged by the continuing decrease in the device dimensions, combined with complex disruptive materials and architectures. These demands are not being met appropriately by existing/forthcoming metrology techniques individually. Hybrid Metrology (HM) – the practice to combine measurements from multiple toolset types in order to enable or improve the measurement of one or more critical parameters – is being incorporated by the industry to resolve these challenges. Continuing our previous work we now take the HM from the lab into the fab. This paper presents the first-in-industry implementation of HM within a High Volume Manufacturing (HVM) environment. Advanced 3D applications are the first to use HM: 20nm Contact etch and 14nm FinFET poly etch. The concept and main components of this Phase-1 Host-based implementation are discussed. We show examples of communication protocols/standards that have been specially constructed for HM for sharing data between the metrology tools and fab host in GLOBALFOUNDRIES, as well as the HM recipe setup and HVM results. Finally we discuss our vision and phased progression/roadmap for Phase-2 HM implementation to fully reap the benefits of hybridization.

We explore how photoresist shrinkage behavior due to e-beam measurement by critical dimension-scanning electron microscope (CD-SEM) depends on various time-related factors. This will include an investigation of how the photoresist critical dimension (CD) and CD shrinkage varies with photoresist age and the differences in shrinkage trends between load/unload and static and dynamic repeatability cases, where time between measurements is a key variable. The results for this typical immersion argon flouride photoresist process will show that resist CD and shrinkage variation due to resist age and vacuum-cycling is insignificant, yet the shrinkage is strongly linked to time between consecutive measurements, with a well-defined, high-certainty logarithmic decay with time. These experiments identify a key difference between the shrinkage seen in static versus dynamic measurements, which will be shown to have far-reaching implications for the shrinkage phenomenon in general and for the best-known methods for executing CD-SEM metrology with photoresist samples.

The accelerated pace of the semiconductor industry in recent years is putting a strain on existing dimensional metrology
equipments (such as CDSEM, AFM, Scatterometry) to keep up with ever-increasing metrology challenges. However, a
revolution appears to be forming with the recent advent of Hybrid Metrology (HM) - a practice of combining
measurements from multiple equipment types in order to enable or improve measurement performance. In this paper we
extend our previous work on HM to measure advanced 1X node layers - EUV and Negative Tone Develop (NTD) resist
as well as 3D etch structures such as FinFETs. We study the issue of data quality and matching between toolsets
involved in hybridization, and propose a unique optimization methodology to overcome these effects. We demonstrate
measurement improvement for these advanced structures using HM by verifying the data with reference tools (AFM,
XSEM, TEM). We also study enhanced OCD models for litho structures by modeling Line-edge roughness (LER) and
validate its impact on profile accuracy. Finally, we investigate hybrid calibration of CDSEM to measure in-die resist line
height by Pattern Top Roughness (PTR) methodology.

Shrinking design rules and reduced process tolerances require tight control of critical dimension (CD) linewidth, feature shape, and profile of the printed geometry. The holistic metrology approach consists of utilizing all available information from different sources such as data from other toolsets, multiple optical channels, multiple targets, etc., to optimize metrology recipe and improve measurement performance. Various in-line CD metrology toolsets such as scatterometry optical CD, CD-SEM, and CD-AFM are typically utilized individually in fabs. Each of these toolsets has its own set of limitations that are intrinsic to specific measurement technique and algorithm. Here we define "hybrid metrology" to be the use of any two or more metrology toolsets in combination to measure the same dataset. We demonstrate the benefits of the hybrid metrology on two test structures: 22-nm-node gate develop inspect and 32-nm-node fin-shaped field effect transistor gate final inspect. We will cover measurement results obtained using typical BKM (nonhybrid, single toolset standard results) as well as those obtained by utilizing the hybrid metrology approach. Measurement performance will be compared using standard metrology metrics; for example, accuracy and precision.

Photoresist shrinkage is an important systematic uncertainty source in critical dimension-scanning electron microscope
(CD-SEM) metrology of lithographic features. In terms of metrology gauge metrics, it influences both the precision and
the accuracy of CD-SEM measurements, while locally damaging the sample. Minimization or elimination of shrinkage is
desirable, yet elusive. Because this error source will furthermore be a factor in CD-SEM metrology on polymer
materials, learning to work around this issue is necessary.
Tool-to-tool matching is another important component of measurement uncertainty that metrologists must control in
high volume manufacturing, and photoresist samples are a most difficult case due to shrinkage effects, as tool-to-tool
biases can vary based on the sample or other parameters. In this work, we explore different shrinkage effects and their
influence on matching. This will include an investigation of how the photoresist shrinkage rate varies with time from the
chemical development of the photoresists, which necessitates that measurements on different tools within a group be
performed in rapid succession to avoid additional error. The differences in shrinkage rates between static and dynamic
load/unload cases will also be addressed, as these effects also influence matching. The results of these dynamic effect
experiments will be shown to have far-reaching implications for the shrinkage phenomenon in general. Finally, various
sampling schemes for matching will be explored, through both simulation and experiment, for use with shrinking
materials. Included is a method whereby various fleet tools measure different locations, once per tool, within a uniform
line/space grating. Finally, we will assess how well matching can be achieved using these techniques.

Shrinking design rules and reduced process tolerances require tight control of CD linewidth, feature shape, and profile of
the printed geometry. The Holistic Metrology approach consists of utilizing all available information from different
sources like data from other toolsets, multiple optical channels, multiple targets, etc. to optimize metrology recipe and
improve measurement performance. Various in-line critical dimension (CD) metrology toolsets like Scatterometry OCD
(Optical CD), CD-SEM (CD Scanning Electron Microscope) and CD-AFM (CD Atomic Force Microscope) are typically
utilized individually in fabs. Each of these toolsets has its own set of limitations that are intrinsic to specific
measurement technique and algorithm. Here we define "Hybrid Metrology" to be the use of any two or more metrology
toolsets in combination to measure the same dataset. We demonstrate the benefits of the Hybrid Metrology on two test
structures: 22nm node Gate Develop Inspect (DI) & 32nm node FinFET Gate Final Inspect (FI). We will cover
measurement results obtained using typical BKM as well as those obtained by utilizing the Hybrid Metrology approach.
Measurement performance will be compared using standard metrology metrics for example accuracy and precision.

A key requirement for nanomanufacturing is maintaining acceptable traceability of measurements performed to determine size. Given that properties and functionality at the nanoscale are governed by absolute size, maintaining the traceability of dimensional measurements of nanoscale devices is crucial to the success of nanomanufacturing. There are various strategies for introducing traceability into the nanomanufacturing environment. Some involve first principles, but most entail the use of calibrated artifacts. In an environment where different types of products are manufactured, it is challenging to maintain traceability across different products mix. In this paper, we present some of the work we have done in developing methods to track the traceability of dimensional measurements performed in a wafer fabrication facility. We combine the concepts of reference measurement system, measurement assurance, and metrological timelines to ensure that traceability is maintained through a series of measurements that involve different instruments and product mixes, spanning a four-year period. We show how to use knowledge of process-induced and instrument systematic errors, among others, to ensure that the traceability of the measurements is maintained.

NIST has introduced a new standard for dimensional metrology and the calibration of the scanning electron microscope
(SEM) scale identifi ed as Reference Material (RM) 8820. RM 8820 was primarily intended to be used for calibrating the
X and Y scale (or magnifi cation) in SEMs but, can be used for an many other purposes. Essentially, all laboratory microscopes
can be calibrated to this same artifact. The NIST pattern is only one part of a very large array of test structures that
were designed for various dimensional metrology purposes useful to semiconductor production technologies. These and
other purposes, discussed in the presentation, RM 8820 can also be used on/in any other type of microscope, such as optical
and scanning probe microscopes and for scatterometry measurements.

Reference Material 8820 (RM 8820) is a new scanning electron microscope calibration reference material for nanotechnology
and nanomanufacturingtion recently released by NIST. This standard was developed to be used primarily for X and
Y scale (or magnifi cation) calibrations of scanning electron microscopes from less than 10 times magnifi cation to more
than 300 000 times magnifi cation, i.e., from about 10 mm to smaller than 300 nm range instrument fi eld of view (FOV).
This standard is identifi ed as RM 8820. This is a very versatile standard, and it can also be used for calibration and testing
of other type of microscopes, such as optical and scanning probe microscopes. Beyond scale calibration, RM 8820 can be
used for a number of other applications, some of which will be described in this publication.

For many years, lithographic resolution has been the main obstacle in keeping the pace of transistor densification to meet
Moore's Law. For the 32 nm node and beyond, new lithography techniques will be used, including immersion ArF
(iArF) lithography and extreme ultraviolet lithography (EUVL). As in the past, these techniques will use new types of
photoresists with the capability to print smaller feature widths and pitches. Also, such smaller feature sizes will require
thinner layers of photoresists, such as under 100 nm.
In previous papers, we focused on ArF and iArF photoresist shrinkage. We evaluated the magnitude of shrinkage
for both R&D and mature resists as a function of chemical formulation, lithographic sensitivity, scanning electron
microscope (SEM) beam condition, and feature size. Shrinkage results were determined by the well accepted
methodology described in ISMI's CD-SEM Unified Specification. A model for resist shrinkage, while derived elsewhere, was presented, that can be used to curve-fit to the shrinkage data resulting from multiple repeated
measurements of resist features. Parameters in the curve-fit allow for metrics quantifying total shrinkage, shrinkage rate,
and initial critical dimension (CD) before e-beam exposure. With these parameters and exhaustive measurements, a
fundamental understanding of the phenomenology of the shrinkage trends was achieved, including how the shrinkage
behaves differently for different sized features. This work was extended in yet another paper in which we presented
a 1-D model for resist shrinkage that can be used to curve-fit to shrinkage curves. Calibration of parameters to describe
the photoresist material and the electron beam were all that were required to fit the model to real shrinkage data, as long
as the photoresist was thick enough that the beam could not penetrate the entire layer of resist.
In this paper, we extend this work yet again to a 2-D model of a trapezoidal photoresist profile. This model thus allows
CD shrinkage in thin photoresist to be solved, which is now of great interest for upcoming realistic lithographic
processing. It also allows us to predict the change in resist profile with electron dose and the influence of initial resist
profile on shrinkage characteristics. In this work, the results from the previous paper will be shown to be consistent with
numerically simulated results, thus lending credibility to these papers' postulations. Also, results from this 2-D
profile model can also give clues as to how we might, in the future, model the shrinkage of contour edges of 3-D shapes.
With these findings, we can conclude with observations about the readiness of SEM metrology for the challenges of
future photoresist measurement, as well as estimate the errors involved in calculating the original CD from the shrinkage
trend.

A new multipurpose instrument calibration standard has been released by NIST. This standard was developed to be used
primarily for X and Y scale (or magnification) calibrations of scanning electron microscopes from less than 10 times magnification to more than 300 000 times magnifi cation, i.e., from about 10 mm to smaller than 300 nm range instrument field of view (FOV). This standard is identifi ed as RM 8820. This is a very versatile standard, and it can also be used for calibration
and testing of other type of microscopes, such as optical and scanning probe microscopes. Beyond scale calibration, RM 8820 can be used for a number of other applications, some of which will be described in this publication.

A key requirement for nanomanufacturing is maintaining acceptable traceability of measurements performed to
determine size. Given that properties and functionality at the nanoscale are governed by absolute size, maintaining the
traceability of dimensional measurements of nanoscale devices is crucial to the success of nanomanufacturing. There are
various strategies for introducing traceability into the nanomanufacturing environment. Some involve first principles, but
most entail the use of calibrated artifacts. In an environment where different types of products are manufactured, it is
challenging to maintain traceability across different products mix.
In this paper, we present some of the work we have done in developing methods to track the traceability of dimensional
measurements performed in a wafer fabrication facility. We combine the concepts of reference measurement system,
measurement assurance, and metrological timelines to ensure that traceability is maintained through a series of
measurements that involve different instruments and product mixes, spanning a four-year period. We show how to use
knowledge of process-induced and instrument systematic errors, among others, to ensure that the traceability of the
measurements is maintained.

For many years, lithographic resolution has been the main obstacle in keeping the pace of transistor densification to meet
Moore's Law. For the 45 nm node and beyond, new lithography techniques are being considered, including immersion
ArF (iArF) lithography and extreme ultraviolet lithography (EUVL). As in the past, these techniques will use new types
of photoresists with the capability to print 45 nm node (and beyond) feature widths and pitches.
In a previous paper [1], we focused on ArF and iArF photoresist shrinkage. We evaluated the magnitude of shrinkage for
both R&D and mature resists as a function of chemical formulation, lithographic sensitivity, scanning electron
microscope (SEM) beam condition, and feature size. Shrinkage results were determined by the well accepted
methodology described in ISMI's <i>CD-SEM Unified Specification</i> [2].
A model for resist shrinkage, while derived elsewhere [3], was presented, that can be used to curve-fit to the shrinkage
data resulting from multiple repeated measurements of resist features. Parameters in the curve-fit allow for metrics
quantifying total shrinkage, shrinkage rate, and initial critical dimension (CD) from before e-beam exposure. The ability
to know this original CD is the most desirable result; in this work, the ability to use extrapolation to solve for a given
original CD value was also experimentally validated by CD-atomic force microscope (AFM) reference metrology.
Historically, many different conflicting shrinkage results have been obtained among the many works generated through
the litho-metrology community. This work, backed up by an exhaustive dataset, will present an explanation that makes
sense of these apparent discrepancies. Past models for resist shrinkage inherently assumed that the photoresist line is
wider than the region of the photoresist to be shrunk [3], or, in other words, the e-beam never penetrates enough to reach
all material in the interior of a feature; consequently, not all photoresist is affected by the shrinkage process. In actuality,
there are two shrinkage regimes, which are dependent on resist feature CD or thickness. Past shrinkage models are true
for larger features. However, our results show that when linewidth becomes less than the eventual penetration depth of
the e-beam after full shrinkage, the apparent shrinkage magnitude decreases while shrinkage speed accelerates. Thus, for
small features, most shrinkage occurs within the first measurement. This is crucial when considering the small features
to be fabricated by immersion lithography.
In this work, the results from the previous paper [1] will be shown to be consistent with numerically simulated results,
thus lending credibility to the postulations in [1].
With these findings, we can conclude with observations about the readiness of SEM metrology for the challenges of both
dry and immersion ArF lithographies as well as estimate the errors involved in calculating the original CD from the
shrinkage trend.

Ever shrinking measurement uncertainty requirements are difficult to achieve for a typical metrology
toolset, especially over the entire expected life of the fleet. Many times, acceptable performance can be
demonstrated during brief evaluation periods on a tool or two in the fleet. Over time and across the rest of
the fleet, the most demanding processes often have measurement uncertainty concerns that prevent optimal
process control, thereby limiting premium part yield, especially on the most aggressive technology nodes.
Current metrology statistical process control (SPC) monitoring techniques focus on maintaining the
performance of the fleet where toolset control chart limits are derived from a stable time period. These
tools are prevented from measuring product when a statistical deviation is detected. Lastly, these charts
are primarily concerned with daily fluctuations and do not consider the overall measurement uncertainty. It
is possible that the control charts implemented for a given toolset suggest a healthy fleet while many of
these demanding processes continue to suffer measurement uncertainty issues. This is especially true when
extendibility is expected in a given generation of toolset. With this said, there is a need to continually
improve the measurement uncertainty of the fleet until it can no longer meet the needed requirements at
which point new technology needs to be entertained. This paper explores new methods in analyzing
existing SPC monitor data to assess the measurement performance of the fleet and look for opportunities to
drive improvements. Long term monitor data from a fleet of overlay and scatterometry tools will be
analyzed. The paper also discusses using other methods besides SPC monitors to ensure the fleet stays
matched; a set of SPC monitors provides a good baseline of fleet stability but it cannot represent all
measurement scenarios happening in product recipes. The analyses presented deal with measurement
uncertainty on non-measurement altering metrology toolsets such as scatterometry, overlay, atomic force
microscopy (AFM) or thin film tools. The challenges associated with monitoring toolsets that damage the
sample such as the CD-SEMs will also be discussed. This paper also explores improving the monitoring
strategy through better sampling and monitor selection. The industry also needs to converge regarding the metrics used to describe the matching component of measurement uncertainty so that a unified approach is
reached regarding how to best drive the much needed improvements. In conclusion, there will be a
discussion on automating these new methods3,4 so they can complement the existing methods to provide a
better method and system for controlling and driving matching improvements in the fleet.

Due to greater emphasis on precision than accuracy, many of the measurements made in semiconductor fabrication
facilities are not traceable to the SI (Systeme International d'Unites or International System of Units) unit of length.
However as the feature sizes of integrated circuits decrease and the use of lithography models becomes more prevalent,
the need for accuracy cannot be overemphasized. In response, the National Institute of Standards and Technology (NIST)
in conjunction with SEMATECH has developed a reference measurement system (RMS) that can be used to provide
accurate measurements for inline metrology tools. The RMS is a critical dimension atomic force microscope (CD-AFM)
with traceability to the SI meter.
In this paper we present a set of strategies for achieving accuracy for different types of measurands within an RMS and
examine several important factors when selecting reference instruments. We also present results of a recent evaluation of
linewidth and height using two CD-AFMs and a calibrated AFM with displacement interferometry in all three axes. We
further look at the stability of tips such as carbon nanotubes.

For many years, lithographic resolution has been the main obstacle for keeping the pace of transistor densification to
meet Moore's Law. For the 45 nm node and beyond, new lithography techniques are being considered, including
immersion ArF lithography (iArF) and extreme ultraviolet (EUV) lithography. As in the past, these techniques will use
new types of photoresists with the capability to print 45 nm node (and beyond) feature widths and pitches.
In a previous paper ("SEM Metrology for Advanced Lithographies," Proc SPIE, v6518, 65182B, 2007), we compared
the effects of several types of resists, ranging from deep ultraviolet (DUV) (248 nm) through ArF (193 nm) and iArF to
extreme UV (EUV, 13.5 nm). iArF resists were examined, and the results from the available resist sample showed a
tendency to shrink in the same manner as the ArF resist but at a lower magnitude.
This paper focuses on variations of iArF resists (different chemical formulations and different lithographic sensitivities)
and examine new developments in iArF resists during the last year. We characterize the resist electron beam induced
shrinkage behavior under scanning electron microscopy (SEM) and evaluate the shrinkage magnitude on mature resists
as well as R&D resists. We conclude with findings on the readiness of SEM metrology for these challenges.

Over the last few years, the need for shape metrology for process control has increased. A key component of shape
metrology is sidewall angle (SWA). However, few instruments measure SWA directly. The critical dimension atomic
force microscope (CD-AFM) is one such instrument. The lateral scanning capability and the shape of the CD-AFM
probe enable direct access to the feature sidewall. This produces profile information that could be used as a process
monitor. Due to their relative insensitivity to material properties, CD-AFMs have been used as reference measurement
systems (RMS) for measurands such as width. We present a technique for calculating the uncertainty of sidewall angle
measurements using a CD-AFM. We outline an overall calibration strategy; address the uncertainty sources for such
measurements, including instrument-related and parameter extraction; related; and discuss the way the calibration is
transferred to workhorse instruments.

One of the key challenges in critical dimension (CD) metrology is finding suitable calibration standards. Over the last
few years there has been some interest in using features measured with the transmission electron microscope (TEM) as
primary standards for linewidth measurements. This is because some modes of TEM can produce lattice-resolved
images having scale traceability to the SI (Systeme International d'Unites or International System of Units) definition of
length through an atomic lattice constant. As interest in using calibration samples that are closer to the length scales
being measured increases, so will the use of these TEM techniques.
An area where lattice-traceable images produced by TEM has been used as a primary standard is in critical dimension
atomic force microscope (CD-AFM) tip width calibration. Two modes of TEM that produce crystal lattice-traceable
images are high resolution transmission electron microscope (HR-TEM) and high angle annular dark field scanning
transmission electron microscope (HAADF-STEM). HR-TEM produces lattice-traceable images by interference
patterns of the diffracted and transmitted beams rather than the actual atomic columns, while HAADF-STEM produces
direct images of the crystal lattice. The difference in how both of these techniques work could cause subtle variations in
the way feature edges are defined.
In this paper, we present results from width samples measured using HR-TEM and HAADF-STEM. Next we compare
the results with measurements taken from the same location by two different CD-AFMs.
Both of the CD-AFM instruments used for this work have been calibrated using a single crystal critical dimension
reference material (SCCDRM). These standards, developed by the National Institute of Standards and Technology
(NIST) and SEMATECH, used HR-TEM for traceable tip-width calibration. Consequently, the present work and the
previous SCCDRM work provide a mutual cross-check on the traceability of the width calibration. Excellent agreement
was observed.

The need for 3D metrology is becoming more urgent to address critical gaps in metrology for both lithographic and etch
processes. Current generation lithographic processing (ArF source, where &#955;=193 nm) sometimes results in photoresist
lines with re-entrant profiles or T-topping, as do many etch processes. A re-entrant profile misleads top-down metrology
into reading the critical dimension (CD) as too large. Recent advances in gate process technology also raise challenges to
traditional top-down metrology. One such example is the FinFET, which is truly a 3D device with 3D metrology needs.
The ability to measure the bottom width of a profile is crucial for process control. Recently, tilt-beam critical dimension-scanning
electron microscopy (CD-SEM) applications have been developed to measure the bottom CD of such features,
using the tilted-view to "see" the bottom, avoiding the feature's larger top. This is an important achievement, as the
bottom of a profile is the main feature of interest in many processes.
Estimation of sidewall angle (SWA) is also important. For several years, tilt-beam CD-SEM has been an available
technique for this measurement, with limited adoption by the litho-metrology community. However, in this paper we
will explore another method to use the tilt feature to measure average sidewall angle, based on edgewidth measurement
and the assumption of basic trapezoidal profile and known height and combined with the ability to sample multiple-features.
While it will not provide exact profile shape, this technique can be quite useful in providing average profile
information and will definitely exhibit good throughput. Samples used will be photoresist and etched FinFET structures
to measure sidewall angles. Correlations of the results to a traceable CD-atomic force microscopy (AFM) reference
measurement system are provided. Conclusions will show preliminary findings of the readiness of tilt-beam CD-SEM
for measuring profile and, by extension, the status of measuring 3D structures such as FinFETs, and using CD-SEM as a
direct control of lithographic tooling for T-topped photoresist profiles.

Requirements for increasingly integrated metrology solutions continue to drive applications that incorporate process
characterization tools, as well as the ability to improve metrology production capability and cycle time, with a single
application. All of the most critical device layers today, along with even non-critical layers, now require optical
proximity correction (OPC), which must be rigorously modeled and calibrated as part of process development and
extensively verified once new product reticles are released using critical dimension-scanning electron microscopy (CD-SEM)
tools. Automatic setup of complex recipes is one of the major trends in CD-SEM applications, which is adding
much value to CD-SEM metrology. In addition, as integrated circuit dimensions continue to shrink, local line width
variation influences the statistical confidence of a measured CD's representation of the process. A feature, called
"Average CD (ACD)," measures multiple targets within the field of view (FOV). ACD allows not only measurements of
a single data point representing one discrete feature, but also sampling of the mean and variance of the process. These
two applications, automatic recipe creation and ACD, are combined in the second version of the DesignGauge software,
which is available for the latest-generation Hitachi S-9380II CD-SEMs. DesignGauge V2 is not only capable of offline
recipe creation and CD-SEM control, but it also has the ability to directly transfer design-based recipes into standard
CD-SEM recipes. These recipes can be used for OPC model-building and verification as with previous DesignGauge
applications. The software also provides design template-based recipe setup for production layer recipes, which yields
much needed improvement to production tool utilization, as production recipes can thus be written offline for new
products, improving first silicon cycle time, reducing engineering time required to generate recipes, and improving CD-SEM
utilization. Another benefit of the application is an improvement in recipe robustness over conventional direct
image-based pattern recognition. This work will show an extensive evaluation of DesignGauge V2, including rigorous
tests of navigation, pattern recognition success rates, SEM image placement, throughput of recipe creation, and recipe
execution. The impact of ACD will also be evaluated.

The conventional premise that metrology is a "non-value-added necessary evil" is a misleading and dangerous assertion,
which must be viewed as obsolete thinking. Many metrology applications are key enablers to traditionally labeled
"value-added" processing steps in lithography and etch, such that they can be considered integral parts of the processes.
Various key trends in modern, state-of-the-art processing such as optical proximity correction (OPC), design for
manufacturability (DFM), and advanced process control (APC) are based, at their hearts, on the assumption of fine-tuned
metrology, in terms of uncertainty and accuracy. These trends are vehicles where metrology thus has large opportunities
to create value through the engineering of tight and targetable process distributions. Such distributions make possible
predictability in speed-sorts and in other parameters, which results in high-end product. Additionally, significant reliance
has also been placed on defect metrology to predict, improve, and reduce yield variability. The necessary quality
metrology is strongly influenced by not only the choice of equipment, but also the quality application of these tools in a
production environment. The ultimate value added by metrology is a result of quality tools run by a quality metrology
team using quality practices.
This paper will explore the relationships among present and future trends and challenges in metrology, including
equipment, key applications, and metrology deployment in the manufacturing flow. Of key importance are metrology
personnel, with their expertise, practices, and metrics in achieving and maintaining the required level of metrology
performance, including where precision, matching, and accuracy fit into these considerations. The value of metrology
will be demonstrated to have shifted to "key enabler of large revenues," debunking the out-of-date premise that
metrology is "non-value-added." Examples used will be from critical dimension (CD) metrology, overlay, films, and
defect metrology.

For many years, lithographic resolution has been the main obstacle for keeping the pace of transistor densification to
meet Moore's Law. The industry standard lithographic wavelength has evolved many times, from G-line to I-line, deep
ultraviolet (DUV) based on KrF, and 193nm based on ArF. At each of these steps, new photoresist materials have been
used. For the 45nm node and beyond, new lithography techniques are being considered, including immersion ArF
lithography and extreme ultraviolet (EUV) lithography. As in the past, these techniques will use new types of
photoresists with the capability of printing 45nm node (and beyond) feature widths and pitches.
This paper will show results of an evaluation of the critical dimension-scanning electron microscopy (CD-SEM)-based
metrology capabilities and limitations for the 193nm immersion and EUV lithography techniques that are suggested in
the International Technology Roadmap for Semiconductors. In this study, we will print wafers with these emerging
technologies and evaluate the performance of SEM-based metrology on these features. We will conclude with
preliminary findings on the readiness of SEM metrology for these new challenges.

This paper is a comprehensive summary and analysis of a SEMATECH funded project to study the limits of optical
critical dimension scatterometry (OCD). The project was focused on two primary elements: 1) the comparison, stability,
and validity of industry models and 2) a comprehensive analysis of process stacks to evaluate the ultimate sensitivity and
limits of OCD. Modeling methods are a requirement for the interpretation and quantitative analysis of scatterometry
data. The four models evaluated show good agreement over a range of targets and geometries for zero order specular
reflection as well as higher order diffraction. A number of process stacks and geometries representing semiconductor
manufacturing nodes from the 45 nm node to the 18 nm node were simulated using several measurement modalities
including angle-resolved scatterometry and spectrally-resolved scatterometry, measuring various combinations of
intensity and polarization.
It is apparent in the results that large differences are observed between those methods that rely upon unpolarized and
single polarization measurements. Using the three parameter fits and assuming that the sensitivity of scatterometry must
meet the criterion that the 3&#963; uncertainty in the bottom dimension must be less than 2% of the linewidth, specular
scatterometry solutions exist for all but the isolated lines at 18 nm node. Scatterometry does not have sufficient
sensitivity for isolated and semi-isolated lines at the 18 nm node unless the measurement uses wavelengths as short as
200 nm or 150 nm and scans over large angle ranges.

The National Institute of Standards and Technology (NIST) and SEMATECH are working to address traceability issues in semiconductor dimensional metrology. In semiconductor manufacturing, many of the measurements made in the fab are not traceable to the SI unit of length. This is because a greater emphasis is often placed on precision and tool matching than on accuracy. Furthermore, the fast pace of development in the industry makes it difficult to introduce suitable traceable standard artifacts in a timely manner. To address this issue, NIST and SEMATECH implemented a critical-dimension atomic-force-microscope-based reference measurement system (RMS). The system is calibrated for height, pitch, and width, and has traceability to the SI definition of length in all three axes. Because the RMS is expected to function at a higher level of performance than inline tools, the level of characterization and handling of uncertain sources is on a level usually seen in instruments at national measurement institutes. In this work, we discuss recent progress in reducing the uncertainty of the instrument as well as details of a newly implemented performance monitoring system. We also present an example of how the RMS concept can be used in a semiconductor manufacturing environment.

An important outcome of the 90nm and 65nm device generations was the realization that new methods for predicting and controlling patterning were required to ensure successful transfer for all design rule compliant features through the required process window. This realization led to a strong increase in the use of CD-based and process window aware post-optical proximity correction (OPC) verification in production mask tapeouts. Accurate post-OPC verification is a necessity but many patterning issues could have been detected and removed earlier in the product development lifecycle. Of course, the 45nm and 32nm device generations are only expected to further strain the ability of device manufacturers to predict process control requirements, robust patterning design rules and first-time right reticle enhancement technology (RET) recipes. Therefore, improvements to the traditional process, OPC and design rule prediction/evaluation steps are needed.
In this paper we propose a patterning and CD control prediction methodology which incorporates not only the traditional dose, defocus and mask variation parameters but also implements RET parameter variations such as layout edge discretization, model inaccuracy, metrology error and assist feature placement. This methodology allows a more accurate prediction of process control requirements, worst case CD control layout geometries and RET subsystem accuracy/control requirements. Lithography engineers have long operated with specific (if not always fully understood) dose and focus control success requirements. To efficiently determine real worst design situations, we utilize a new methodology for quickly verifying the RET-ability of a lithography process + design rule set + OPC correction recipe based on coupling iterative layout generation with OPC testing. Our aim in this paper is to provide additional engineering rigor to the traditional experience-based OPC success requirements by looking at the total Litho + RET + metrology patterning problem and analyzing the individual component control needs.

Downscaling of semiconductor fabrication technology requires continuous improvements in production process control. To ensure tool-to-tool matching and compatibility of critical dimension-scanning electron microscopy (CD-SEM) measurements to measurements from other technologies, such as optical CD, or from other fabrication entities, accuracy has become a much more important factor than in the past. CD-SEM measurements have always yielded a bias, which can be quite significant, but also typically neglected since it does not vary much over a process window. However, the standard CD-SEM metrology approach to algorithm accuracy (which can be formulated "Accuracy= Precision + Calibration") does not work for small features; i.e., the measurement bias is not constant for small features. Limitations of the standard measurement algorithm, based on the treatment of the singular point of the waveform for CDs smaller than 30 nm and the new model library-based approach, were considered. The implementation of reliable measurement algorithms for features at the 45 nm node and beyond requires development of more sophisticated approaches to SEM signal treatment. A three-dimensional (3-D) physical model that takes into account physical processes related to the beam interaction with material is considered. Reliability of the new approach is verified using Monte-Carlo SEM simulation and real SEM images as compared to reference measurements; total measurement uncertainty (TMU) is improved with the better models. The relation of the developed method to the standard SEM measurement algorithm and model-based approach is also considered.

In order to stay competitive in the rapidly advancing international semiconductor industry, a manufacturing company needs to continually focus on several areas including rapid yield learning, manufacturing cost, statistical process control limits, process yield, equipment availability, cycle time, turns per direct labor hour, customer on time delivery and zero customer defects. To hold a competitive position in the semiconductor market, performance to these measurable factors mut be maintained regardless of the technology generation. In this presentation, the methodology applied by Freescale Semiconductor to achieve the fastest yield learning curve in the industry, as cited by Dr. Robert Leachman of UC Berkley in 2003, will be discussed.

There are numerous metrology challenges facing photolithography for the 45 nm technology node and beyond in the
areas of critical dimension (CD), overlay and defect metrology. Many of these challenges are identified in the 2005
<i>International Technology Roadmap for Semiconductors </i>(ITRS) [1]. The Lithography and Metrology sections of the
ITRS call for measurement of 45/32/22/18 nm generation linewidth and overlay. Each subsequent technology generation
requires less variation in CD linewidth and overlay control, which results in a continuing need for improved metrology
precision. In addition, there is an increasing need to understand individual edge variation and edge placement errors
relative to the intended design. This is accelerating the need for new methods of CD and overlay measurement, as well
as new target structures. This paper will provide a comprehensive overview of the CD and overlay metrology challenges
for photolithography, taking into account the areas addressed in the 2005 ITRS for the 45 nm technology generation and
beyond.

As the trends in integrated circuit fabrication follow Moore's Law to smaller feature sizes, one trend seen in lithographic technology is the continually increasing use of optical enhancements such as Optical Proximity Correction (OPC). Small size perturbations are designed into the nominal feature shapes on the reticle such that the intended shape is printed. Verifying the success of OPC is critical to ramp-up and production of new process technologies. CD-SEMs are imaging tools which are capable of measuring feature sizes in any part of a chip, either in a test structure or within a circuit. A new trend in CD-SEM utilization is the implementation of automated recipe generation of complex CD-SEM recipes. The DesignGauge system uses design-to-SEM recipe creation and data collection. Once the recipe creation flow is implemented, the task of recipe creation can be accomplished within minutes. These applications enable a CD-SEM to be utilized to collect data for very complex OPC CD-SEM recipe runs which measure many different unique linewidths, spaces, and pattern placements within a circuit to check OPC success and lithographic fidelity. The data collection can provide accurate data results that can be utilized for comparing achieved feature measurements to nominal values from the design layout. This new application adds much value to the CD-SEM compared to other technologies such as OCD, as it completes the evaluation of in-circuit behavior to test structures in a scribe lane, something OCD currently cannot do. The present work evaluates the capabilities of DesignGauge, which is available for the latest-generation Hitachi S-9380II CD-SEMs. The evaluation includes rigorous tests of navigation, pattern recognition success rates, SEM image placement, throughput of recipe creation and recipe execution.

The National Institute of Standards and Technology (NIST) and SEMATECH are working to address traceability issues in semiconductor dimensional metrology. In semiconductor manufacturing, many of the measurements made in the fab are not traceable to the SI definition of the meter. This is because a greater emphasis is often placed on precision and tool matching than accuracy. Furthermore, the fast pace of development in the industry makes it difficult to introduce suitable traceable standard artifacts in a timely manner. To address this issue, NIST and SEMATECH implemented a critical dimension atomic force microscope (CD-AFM)-based reference measurement system (RMS). The system is calibrated for height, pitch, and width and has traceability to the SI definition of length in all three axes. Because the RMS is expected to function at a higher level of performance than inline tools, the level of characterization and handling of uncertainty sources is on a level usually seen for instruments at national measurement institutes. We have implemented a performance monitoring system to help us check the long-term stability of the calibrations. In this paper, we discuss progress in improving the uncertainty of the instrument and the details of our performance monitoring. We also present a method for accounting for some of the uncertainty due to the higher order tip effects.

The National Institute of Standards and Technology (NIST) and The International Sematech Manufacturing Initiative
(ISMI) have been involved in a project to evaluate the accuracy of optical overlay measurements in the presence of
measurement target asymmetries created by typical wafer processing. The ultimate goal of this project is to produce a
method of calibrating optical overlay measurements on typical logic and memory production stacks. A method of
performing accurate CD-SEM and CD-AFM overlay measurements is first presented. These measurements are then
compared to optical overlay measurements of the same structures to assess the accuracy of the optical measurements.
Novel image rotation tests were also performed on these structures to develop a method to decouple errors from
metrology target asymmetries and measurement system optical asymmetries.

With shrinkage of device size, metrology requirements for Critical Dimension (CD), as defined as the ratio of precision of metrology to process tolerance (P/T), must meet the 0.1 (10%) or 0.2 (20%) criterion.[1][2][14] The precision requirement for gate CD at the 90nm node is thus ~ 0.3nm or less with P/T of 10%, which is far beyond what traditional CD metrology can achieve today. At future nodes, this requirement becomes even tougher, even with P/T of 20%. For years, scatterometry has demonstrated its capability to determine CD and cross sectional profile over periodically aligned line and space (i.e. grating) structures with superior precision. However, to gauge the true capability of scatterometry for process monitoring, the concept of Total Measurement Uncertainty (TMU)[11] of scatterometry in reference to CD-SEM and CD-AFM should be implemented since TMU comprehends both precision and accuracy relative to a reference measurement system. The methodology of implementation of TMU has been discussed in a separate article.[1][12][14][15][17] This paper presents a systematic study on TMU of scatterometry for Final Inspect (FI, post-etch) gate CD and profile, and includes a discussion on how the TMU may be further reduced. One potential option is to feed forward film stack information into the profile modeling, which reduces the number of parameters that have to be calculated during the real-time regression of the scatterometry data.

The Advanced Metrology Advisory Group (AMAG) is a council composed of the chief CD-metrologists from the SEMATECH consortium's Member Companies and from the National Institute of Standards (NIST). The AMAG wrote, with OCD tool supplier involvement, the "Unified Advanced Optical Critical Dimension (OCD) Scatterometer Specification for Sub-90nm Technology (2004 Version)" [22] to be a living document which outlines the required performance of OCD tools for supplier compliance to the 2003 International Technology Roadmap for Semiconductors (ITRS) and which conveys Sematech member companies' collective needs to vendors. Using this specification, evaluation efforts of currently available tools are being performed.
The 2004 AMAG Unified Specification for Scatterometry includes sections outlining the test methodologies, metrics, and wafer-target requirements for each parameter to be benchmarked, and, if applicable, prescribes a target specification compatible with the ITRS. The methodologies are valid for the demands of the 90nm technology node and beyond. Parameters to be considered include:
Precision, Repeatability and Reproducibility
Accuracy
System Matching
Noise and Spectral Sensitivity
Throughput
Interaction with sample
Measurement of material optical properties (n & k)
Pattern recognition/stage navigation accuracy
Specular Beam Width ("spot size")
Cost of ownership (COO)
When possible, the metrics in this specification have been made compatible with similar specifications in the AMAG CD-SEM Unified Specification so that fair intercomparisons of different tools can be made. Previous CD-SEM studies under this same project have been published, with the initial version of the International SEMATECH CD-SEM Unified Specification in 1998, and multi-supplier CD-SEM benchmarks in 1999, 2001 and 2003.

Downscaling of semiconductor fabrication technology requires an ever-tighter control of the production process. CD-SEM, being the major image-based critical dimension metrology tool, is constantly being improved in order to fulfill these requirements. One of the methods used for increasing precision is averaging over several or many (ideally identical) features, usually referred to as "Macro CD". In this paper, we show that there is much more to Macro CD technology- metrics characterizing an arbitrary array of similar features within a single SEM image-than just the average. A large amount of data is accumulated from a single scan of a SEM image, providing informative and statistically valid local process characterization. As opposed to other technologies, Macro CD not only provides extremely precise average metrics, but also allows for the reporting of full information on each of the measured features and of various statistics (such as the variability) on all currently reported CD SEM metrics. We present the mathematical background behind Macro CD technology and the opportunity for reducing number of sites for SPC, along with providing enhanced-sensitivity CD metrics.

The Advanced Metrology Advisory Group (AMAG) is a council composed of the chief CD-metrologists from the International SEMATECH Manufacturing Initiative (ISMI) consortium’s Member Companies and from the National Institute of Standards (NIST). The AMAG wrote and, in 2002, with CD-SEM supplier involvement, updated the “Unified Advanced CD-SEM Specification for Sub-130nm Technology (Version 2002)” to be a living document which outlines the required performance of advanced CD-SEMs for supplier compliance to the 2003 International Technology Roadmap for Semiconductors, and also conveys member companies’ other collective needs to vendors. Through applying this specification during the mid-2003 timeframe, a benchmarking effort of the currently available advanced CD-SEMs has been performed. These results are presented here. The AMAG Unified Specification includes sections outlining the test methodologies, metrics, and wafer-target requirements for each parameter included in the benchmark, and, when applicable, prescribes a target specification compatible with the ITRS and methodologies compatible with the demands of 90nm technology. Parameters to be considered include:
&bull;Precision, Repeatability and Reproducibility
&bull;Accuracy, Apparent Beam Width and Resolution
&bull;Charging and Contamination
&bull;Tool-to-Tool Matching
&bull;Pattern Recognition and Navigation Accuracy
&bull;Throughput
&bull;Instrumentation Outputs
&bull;Tool Automation and Utility
&bull;Precision and Accuracy of Profile Measurement
&bull;Precision and Accuracy of Roughness Measurement.
Previous studies under this same project have been published, with the initial version of the International Sematech Unified Specification in 1998, and multi-supplier benchmarks in 1999 and 2001. The results for the 2003 benchmark will be shown and compared to the ITRS, and composite viewpoints showing these 2003 benchmark results compared to the past results are also shown, demonstrating interesting CD-SEM industry trends.

The measurement of line-edge roughness (LER) has recently become a topic of concern in the litho-metrology community and the semiconductor industry as a whole. The Advanced Metrology Advisory Group (AMAG), a council composed of the chief metrologists from the International SEMATECH (ISMT) consortium’s Member Companies and from the National Institute of Standards and Technology (NIST), has a project to investigate LER metrics and to direct the critical dimension scanning electron microscope (CD-SEM) supplier community towards a semiconductor industry-backed, standardized solution for implementation. The 2003 International Technology Roadmap for Semiconductors (ITRS) has included a new definition for roughness. The ITRS envisions root mean square measurements of edge and width roughness. There are other possible metrics, some of which are surveyed here. The ITRS envisions the root mean square measurements restricted to roughness wavelengths falling within a specified process-relevant range and with measurement repeatability better than a specified tolerance. This study addresses the measurement choices required to meet those specifications. An expression for the length of line that must be measured and the spacing of measurement positions along that length is derived. Noise in the image is shown to produce roughness measurement errors that have both random and nonrandom (i.e., bias) components. Measurements are reported on both UV resist and polycrystalline silicon in special test patterns with roughness typical for those materials. These measurements indicate that the sensitivity of a roughness measurement to noise depends importantly both on the choice of edge detection algorithm and the quality of the focus. Measurements are less sensitive to noise when a model-based or sigmoidal fit algorithm is used and when the images are in good focus. Using the measured roughness characteristics for UV resist lines and applying the ITRS requirements for the 90 nm technology node, the derived expression for sampling length and sampling interval implies that a length at least 8 times the node (i.e., 720 nm) must be measured at intervals of 7.5 nm or less.

The purpose of this paper is to define standard methods for effective and efficient image-based dimensional metrology for microlithography applications in the manufacture of integrated circuits. This paper represents a consensual view of the co-authors, not necessarily in total agreement across all subjects, but in complete agreement on the fundamentals of dimensional metrology in this application. Fundamental expectations in the conventional comparison-based metrology of width are reviewed, with its reliance on calibration and standards, and how it is different from metrology of pitch and image placement. We discuss the wealth of a priori information in an image of a feature on a mask or a wafer. We define the estimates of deviations from these expectations and their applications to effective detection and identification of the measurement errors attributable to the measurement procedure or the metrology tool, as well as to the sample and the process o fits manufacture. Although many individuals and organizations already use such efficient methods, industry-wide standard methods do not exist today. This group of professionals expects that, by placing de facto standard meth-odologies into public domain, we can help reduce waste and risks inherent in a "spontaneous" technology build-out, thereby enabling a seamless proliferation of these methods by equipment vendors and users of dimensional metrology. Progress in this key technology, with the new dimensional metrology capabilities enabled, leads to improved perform-ance and yield of IC products, as well as increased automation and manufacturing efficiency, ensuring the long-term health of our industry.

We explore the implementation of improved overlay mark designs increasing mark fidelity and device correlation for advanced wafer processing. The effect of design rule segmentation on overlay mark performance is studied. Short loop wafers with 193 nm lithography for front-end (poly to STI active) as well as back-end (via to metal) were processed and evaluated. A comparison of 6 different box-in-box (BiB) overlay marks, including non-segmented, multi bar, and design-rule segmented were compared to several types of AIM (Advanced Imaging Metrology) grating targets which were non-segmented and design rule segmented in various ways. The key outcomes of the performance study include the following: the total measurement uncertainty (TMU) was estimated by the RMS of the precision, TIS 3-sigma and overlay mark fidelity (OMF). The TMU calculated in this way show a 40% reduction for the grating marks compared to BiB. The major contributors to this performance improvement were OMF and precision, which were both improved by nearly a factor of 2 on the front-end layer. TIS-3-sigma was observed to improve when design rule segmentation was implemented, while OMF was marginally degraded. Similar results were found for the back end wafers. Several different pitches and segmentation schemes were reviewed and this has allowed the development of a methodology for target design optimization. Resulting improvements in modeled residuals were also achieved.

Smaller device dimensions and tighter process control windows have created a need for CD metrology tools having higher levels of precision and accuracy. Furthermore, the need to detect and measure changes in feature profiles is becoming critical to in-line process control and stepper evaluation for sub-0.18micrometers technology. Spectroscopic CD (SCD<SUP>TM</SUP>) is an optical metrology technique that can address these needs. This work describes the use of a spectroscopic CD metrology tool to measure and characterize the focus and exposure windows for the process. The results include comparison to the established in-line CD-SEM, as well as a cross-section SEM. Repeatability and long-term stability data form a gate level nominal process are also presented.

One-dimensional linewidth alone is an inadequate metric for low-k1 lithography. Critical Dimension metrology and analysis have historically focused on 1-dimensional effects but with low-k1 lithography is has increasingly been found that the process window for acceptable imaging of the full 2D structure is more limited than the process window for CDs alone. The shape and area of the feature have become as critical to the proper patterning as the width. The measurement and analysis of Critical Shape Difference (CSD) of patterned features must be an integral part of process development efforts. Adoption of optical proximity correction (OPC) and other Optical Extension Technologies increases the need for understanding specific effects through the pattern transfer process. Sub-resolution features on the mask are intended to compensate the pattern so that the resulting etched features most accurately reflect the designer's intent and provide the optimum device performance. A method for quantifying the Critical Shape Difference between the designer's intent, OPC application, mask preparation, resist exposure and pattern etch has been developed. This work focuses on overlaying features from the various process stages and using CSD to quantify the regions of overlap in order to assess OPC performance. Specific examples will demonstrate the gap in current 1-D analysis techniques.

The AMAG comprised of representatives from International SEMATECH consortium member companies and the National Institute of Standards and Technology have joined to develop a new unified specification for an advanced scanning electron microscope critical dimension measurement instrument (CD-SEM). This paper describes the result of an effort to benchmark six CD-SEM instruments according to this specification.

The continuing demand for higher frequency microprocessors and larger memory arrays has led to decreasing device dimensions and smaller process control windows. Decreasing process control windows have created a need for higher precision metrology to maintain an acceptable precision to tolerance ratio with a reasonable sampling rate. In order to determine and reduce across chip, across wafer, and across lot linewidth variations, higher sampling is required which, in turn, demands faster move acquire measure (MAM) times to maintain throughput. Finally, the need to detect and quantify sidewall angle changes in addition to CD measurements is becoming critical. Spectroscopic Scatterometry is a metrology technique which offers the potential to meet these requirements. This work explores some of the fundamental technology concerns for implementing scatterometry in a manufacturing environment. These concerns include mark requirements and characterization necessary for library generation. Comparison of scatterometry data to in-line CD SEM, x-section SEM, and AFM results will be presented.

The Advanced Metrology Advisory Group (AMAG) comprised of representatives from International SEMATECH consortium member companies and the National Institute of Standards and Technology have joined to develop a new unified specification for an advanced scanning electron microscope critical dimension measurement instrument (CD-SEM). (Allgair, et al., 1998) This paper describes the results of an effort to benchmark six CD-SEM instruments according to this specification. The consensus among the AMAG metrologists was that many critical areas of performance of CD-SEMs required improvement. Following this assessment this specification for benchmarking was developed. The advanced CD-SEM specification addresses several critical areas for improvement, each with its own a separate section. The critical areas covered are: precision, accuracy, charging and contamination, performance matching, pattern recognition and stage navigation accuracy, throughput, and instrumentation outputs. Each section of the specification contains a concise definition of the respective performance parameter, and wherever appropriate refers to ISO definitions. The test methodology is described, complete with the relevant statistical analysis. Many parameters (including precision, matching, and magnification accuracy) are numerically specified to be consistent with the International Technology Roadmap for Semiconductors (ITRS, 1999). Other parameters, such as charging and linewidth accuracy, are targeted with guidelines for improvement. The test wafers developed for determining the level of compliance with the specification are also discussed. The AMAG circulated this report among the metrology instrument suppliers and conferred with them. Certain components of the specification have already been adopted by some of the manufacturers in their newer metrology instruments. International SEMATECH fabricated the AMAG test wafers described herein. Measurements on six state-of-the-art metrology instruments using the AMAG test wafers have been carried out and the results were processed according to this specification. A review of the results is presented in this paper.

Measurement system analysis is essential for determining the quality of data used for process control. Analysis of variation, or ANOVA, is a commonly used technique for measurement system analysis. Recently, the Advanced Metrology Advisory Group at SEMATECH has proposed using the Latin Square technique for determining the reproducibility and repeatability of a CD SEM. Advantages and disadvantages of the two techniques will be discussed.

Rapidly accelerating technology roadmaps have put increased pressure on in-line process control. CDs measured by automated SEMs are a common element of in-line process control. However, CD measurements alone may not be enough in all cases for adequate process control. For instance, degradation of feature integrity that does not lead to out of control CDs in photo can lead to scrap after etch. The cost of scrap and loss of time to results associated with catching photo process drift with after etch inspection has forced the development of new tools to monitor feature integrity in the ADI CD inspection module. Likewise, partially closed vias that are not caught with etch CD inspection can have a negative impact on copper processes. We describe a feature integrity monitoring technique using an automated CD-SEM that occurs simultaneously with the CD measurement to monitor and detect process drift prior to out of control CD events. We further describe the implementation of this technique in a production environment.

It is well known that systematic within-chip dimension (CD) errors can strongly influence product yield and performance, especially in the case of microprocessors. It has been shown that this across chip linewidth variation (ACLV) dominates the CD error budge, and is comprised of multiple systematic and random effects, including substrate reflectivity, reticle CD errors, feature proximity, and lens aberrations. These effects have material, equipment, and process dependencies, with the results being that significant ACLV differences between nominally identical tools/processes can in some cases be observed. We present here a new analysis approach which allows for optimization of exposure/defocus conditions to minimize overall CD errors for a given process. Emphasis is on control of [(mean) + 3 sigma] of CD errors for a given exposure/defocus conditions. Input metrology data is obtained from electrical resistance probing, and data is presented for multiple 248 nm DUV processes and tools with CD ground rules ranging from 180 nm to 140 nm.

Decreasing metal interconnect dimensions have led to tighter overlay tolerance requirements to ensure via to metal contact. These strict requirements often test the alignment capability of a manufacturing line; therefore, careful characterization is required to justify the overlay specification limits. A variety of technique can be combined for overlay process characterization including electrical resistance measurements, optical overlay measurements, CD SEM via misalignments and x-section yield. Available characterization techniques are then used to fully study the process window. Characterization data will be presented for a copper interconnect process.

Semiconductor manufacturers should ensure that their automated critical dimension scanning electron microscopes (CD-SEMs) are maintaining run functionality in addition to providing precise and reliable measurements over time. In the past, chip manufactures have focused more on tracking measurement repeatability because testing for automated run functionality has proven difficult. A new method employing SPC monitoring, e-beam image analysis, line scan tracking, and automation testing has been developed that tests for both measurement and job repeatability. This method will extend the monitor wafer's lifetime, prove useful for day-to-day system qualification, provide a benchmark for SEM qualification following maintenance work, and become an important cornerstone of system matching.

The stringent critical dimension control requirements in cutting edge device facilities have placed significant demands on metrologists and upon the tools they use. We are developing a unified, advanced critical dimension scanning electron microscope specification in the interests of providing a unified criterion of performance and testing. The specification is grounded on standard definitions and strong principles of metrology. The current revision is to be published as a SEMATECH document. A new revision, now in progress, will embody the consensus of a vendor/user conference.

DUV scanning exposure systems have been steadily gaining market acceptance for the past five years, and soon, all major suppliers will offer 248-nm scanning tools. One of the major reasons for the emergence of this technology has been the purported improvement in critical dimension (CD) uniformity across the scanned field versus what can be realized in a full field stepper. Using high precision electrical resistance CD metrology, we have characterized the across field CD control capability of several DUV scanning tools and DUV steppers. Analysis is carried out through focus for multiple linetypes representing various orientations and nearest-neighbor proximities. Where possible, different NA/(sigma) combinations are examined as well. Surprisingly good full field sub-0.20 micrometers CD control is obtained even for 0.50 NA, and higher NA allows for non zero process latitude at 0.14 micrometers geometries. While it was initially anticipated that 193 nm ArF lithography would be required for 0.18 micrometers technology manufacturing, it has become apparent that 248 nm lithography will be employed for these groundrules, particularly for logic applications with predominantly semi-isolated features.

Semiconductor manufacturers must ensure that their in-line critical dimension scanning electron microscopes (CD-SEMs) are providing precise and reliable data on a daily basis. As with other process equipment, tool stability and production worthiness is determined by a daily qualification procedure that involves measuring a reference, etched wafer's linewidth and comparing those results to a set target mean. However, repeated exposure to a SEM creates an unacceptable increase in the measured feature's CD. This increase can be disruptive to tool qualification, requires the introduction of new reference wafers, and ultimately limits the tool's availability to production. A new method for daily qualification using a rotating daily job scheme has been developed and employed for monitoring multiple systems at Motorola MOS-13/APRDL. This new procedure allows for better statistical process control, increase the reference wafer's useful life, and provides an easier method of monitoring the tool throughout its lifetime.

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Advanced PhotonicsJournal of Applied Remote SensingJournal of Astronomical Telescopes Instruments and SystemsJournal of Biomedical OpticsJournal of Electronic ImagingJournal of Medical ImagingJournal of Micro/Nanolithography, MEMS, and MOEMSJournal of NanophotonicsJournal of Photonics for EnergyNeurophotonicsOptical EngineeringSPIE Reviews