This paper presents a new technique for compiled zero delay logic
simulation, and includes extensive experiments that demonstrate its
performance on standard benchmarks. Our compiler partitions the
circuit into fanout-free regions (FFRs), transforms each FFR
into a linear sized BDD, and converts each BDD into executable code.
In our approach, the computation is sublinear in the number of
variables within each partition because only one path, from root to
leaf, of the BDD is executed; therefore in many cases, substantial
computation is avoided. In this way, our approach gets some of the
advantages of oblivious as well as demand-driven evaluation. We
investigated the impact of various heuristics on performance, and
based on this data, we recommend good values for design parameters. A
performance improvement of up to 67% over oblivious simulation is
observed for our benchmarks.