Lack of consistent handoff between analog and digital design boundaries and the inexistence of mature verification methodologies for mixed signal verification have been common reasons for chip re-spins. As AMS verification matures, so do the methodologies that support AMS verification which now include low-power, behavioral modeling abstraction, assertions, and metric driven verification methodologies.

I had the pleasure of meeting lots of customers during CDNLive! Silicon Valley 2012 and learned firsthand about their verification challenges and the approaches they're taking to address such challenges. Ken Luo from LSI Corporation delivered a presentation about real number model (RNM) development and application in mixed-signal SoC verification. Luo iterated that exploding operating modes, functionality demands for digital control, and calibration to mitigate against process variations are typical trends in modern SoC designs.

As such, analog simulation performance and convergence are bottlenecks for full chip verification. Luo discussed the benefits of adopting RNM, which include the continuous value and discrete time nature of real numbers that allow for pure digital solver simulation and high-speed performance. Also, Luo highlighted other features like multiple drivers and resolution function support for RNM, discipline association, and ease of connecting real to electrical nets using R2E/E2R connect modules.

Luo also shared some guidelines for RNM modeling regarding signal flow modeling (voltage vs. current), sampling approaches (uniform vs. non-uniform sampling) which are required to balance performance and accuracy, and modeling data processing algebraic equations vs. nonlinear table models. One of the key takeaways of the presentation is to "model what you need and not what you can" to reflect the specified functionality and avoid unnecessary high order effects. Another takeaway is to align the model development plan with the design development plan, maintain consistent interfaces for model/design, and to use version control to keep the model/design in sync.

Also, Luo discussed that models should be classified according to the block characteristics and verification requirements. Communication I/Os that toggle frequently and have low accuracy requirements can be modeled using Verilog, while high accuracy and frequently toggling nodes like clocks, oscillators, and high bandwidth amplifiers or high accuracy, less frequently toggling nodes like reference voltage/current and, low-speed high-resolution ADC/DAC, should be modeled using Verilog-AMS/Wreal.

Luo introduced an LSI application, which is a hard disk drive (HDD) PreAmplifier that performs small signal amplification (during READ operation) and voltage waveform shaping (during WRITE operation) interfaces to the HDD R/W heads. The PreAmp has been historically an analog ASIC, but today it has become a complex mixed-signal SoC due to > 4.0 Gbps high data rate requirements, multiple operation modes, programmability of bias/threshold control and calibration. The increased feature complexity poses a challenge to AMS verification due to extremely long simulation times, D/A interface coverage and lack of coverage measurement.

The LSI verification team used Cadence verification planning (vPlan) to collect and define model feature requirements and align verification milestones. Also, the team developed analog mixed-signal Universal Verification Components (UVC) and checkers for analog signals for amplitude, frequency, common mode voltage and sampling frequency. The team observed significant improvements (~600x) using the RNM models over SPICE simulations, which suffered convergence issues and didn't provide adequate coverage. The RNM models achieved 95% accuracy, enabled full coverage, and achieved first silicon success with zero functional bugs.