The CY7C375i is an In-System Reprogrammable ComplexProgrammable Logic Device (CPLD) and is part of theF

LASH

370iTM family of high-density, high-speed CPLDs. Like

all members of the F

LASH

370i family, the CY7C375i is de-

signed to bring the ease of use and high performance of the22V10 to high-density PLDs.

Like all of the UltraLogicTM F

LASH

370i devices, the CY7C375i

is electrically erasable and In-System Reprogrammable (ISR),which simplifies both design and manufacturing flows therebyreducing costs. The Cypress ISR function is implementedthrough a JTAG serial interface. Data is shifted in and outthrough the SDI and SDO pins. The ISR interface is enabledusing the programming voltage pin (ISR

The 128 macrocells in the CY7C375i are divided betweeneight logic blocks. Each logic block includes 16 macrocells, a72 x 86 product term array, and an intelligent product termallocator.

The logic blocks in the F

LASH

370i architecture are connected

with an extremely fast and predictable routing resource--theProgrammable Interconnect Matrix (PIM). The PIM brings flex-ibility, routability, speed, and a uniform delay to the intercon-nect.

Like all members of the F

LASH

370i family, the CY7C375i is rich

in I/O resources. Every macrocell in the device features anassociated I/O pin, resulting in 128 I/O pins on the CY7C375i.In addition, there is one dedicated input and four input/clockpins.

Finally, the CY7C375i features a very simple timing model.Unlike other high-density CPLD architectures, there are nohidden speed delays such as fanout effects, interconnect de-lays, or expander delays. Regardless of the number of re-sources used or the type of application, the timing parameterson the CY7C375i remain the same.

Logic Block

The number of logic blocks distinguishes the members of theF

LASH

370i family. The CY7C375i includes eight logic blocks.

Each logic block is constructed of a product term array, a prod-uct term allocator, and 16 macrocells.

Product Term Array

The product term array in the F

LASH

370i logic block includes

36 inputs from the PIM and outputs 86 product terms to theproduct term allocator. The 36 inputs from the PIM are avail-able in both positive and negative polarity, making the overallarray size 72 x 86. This large array in each logic block allowsfor very complex functions to be implemented in single passesthrough the device.

Product Term Allocator

The product term allocator is a dynamic, configurable resourcethat shifts product terms to macrocells that require them. Anynumber of product terms between 0 and 16 inclusive can beassigned to any of the logic block macrocells (this is calledproduct term steering). Furthermore, product terms can beshared among multiple macrocells. This means that productterms that are common to more than one output can be imple-

Pin Configurations

(continued)

PGA

Bottom View

1

2

3

4

5

6

7

8

9

10

11

R

P

N

M

L

K

J

H

G

F

E

I/O

109

D

C

B

A

12

13

14

15

7C375i­4

I/O

106

I/O

105

I/O

102

I/O

100

I/O

98

I/O

96

I/O

86

I/O

89

I/O

91

I/O

94

I/O

95

I/O

83

I/O

80

I/O

78

I/O

112

I/O

110

I/O

108

I/O

104

I/O

101

I/O

99

I/O

97

I/O

84

I/O

87

I/O

90

I/O

93

GND

I/O

81

I/O

79

I/O

75

/SDI

I/O

115

I/O

113

I/O

111

I/O

107

I/O

103

GND

CLK

3

I/O

82

I/O

85

I/O

88

I/O

92

CLK

2

GND

I/O

77

I/O

74

/I

4

/I

3

I/O

118

I/O

116

I/O

114

V

CC

V

CC

GND

V

CC

GND

I/O

76

I/O

73

I/O

71

/SDO

I/O

121

I/O

119

I/O

117

I/O

72

I/O

70

I/O

69

I/O

123

I/O

122

I/O

120

GND

I/O

68

I/O

67

I/O

126

I/O

125

I/O

124

V

CC

V

CC

I/O

66

I/O

65

I/O

64

I/O

127

GND

ISR

EN

GND

GND

I

2

GND

I/O

63

I/O

0

I/O

1

I/O

2

V

CC

V

CC

I/O

60

I/O

61

I/O

62

I/O

3

I/O

4

GND

I/O

56

I/O

58

I/O

59

I/O

5

I/O

6

I/O

8

I/O

53

I/O

55

I/O

57

I/O

7

I/O

9

I/O

12

GND

V

CC

V

CC

V

CC

GND

I/O

52

/

I/O

50

I/O

71

SMODE

I/O

10

I/O

13

GND

I/O

18

I/O

21

I/O

24

CLK

28

I/O

43

I/O

39

GND

CLK1

CLK

0

I/O

47

I/O

49

I/O

51

/I

0

I/O

11

I/O

15

I/O

17

I/O

20

I/O

23

I/O

26

I/O

29

I/O

40

I/O

37

I/O

35

I/O

33

GND

I/O

44

I/O

46

I/O

48

I/O

14

I/O

16

I/O

19

I/O

22

I/O

25

I/O

27

I/O

30

I/O

38

I/O

36

I/O

34

I/O

32

I/O

31

I/O

41

I/O

42

I/O

45

/I1

/SCLK

CY7C375i

Document #: 38-03029 Rev. **

Page 5 of 17

mented in a single product term. Product term steering andproduct term sharing help to increase the effective density ofthe F

LASH

370i PLDs. Note that product term allocation is han-

dled by software and is invisible to the user.

I/O Macrocell

Each of the macrocells on the CY7C375i has a separate I/Opin associated with it. The input to the macrocell is the sum ofbetween 0 and 16 product terms from the product term alloca-tor. The macrocell includes a register that can be optionallybypassed, polarity control over the input sum-term, and fourglobal clocks to trigger the register. The macrocell also fea-tures a separate feedback path to the PIM so that the registercan be buried if the I/O pin is used as an input.

Programmable Interconnect Matrix

The Programmable Interconnect Matrix (PIM) connects theeight logic blocks on the CY7C375i to the inputs and to eachother. All inputs (including feedbacks) travel through the PIM.There is no speed penalty incurred by signals traversing thePIM.

Programming

For an overview of ISR programming, refer to the F

LASH

370i

Family data sheet and for ISR cable and software specifica-tions, refer to ISR data sheets. For a detailed description ofISR capabilities, refer to the Cypress application note, "An In-troduction to In System Reprogramming with F

LASH

370i."

PCI ComplianceThe F

LASH

370i family of CMOS CPLDs are fully compliant with

the PCI Local Bus Specification published by the PCI SpecialInterest Group. The simple and predictable timing model ofF

LASH

370i ensures compliance with the PCI AC specifications

independent of the design. On the other hand, in CPLD andFPGA architectures without simple and predictable timing, PCIcompliance is dependent upon routing and product termdistribution.

3.3V or 5.0V I/O operation

The F

LASH

370i family can be configured to operate in both

3.3V and 5.0V systems. All devices have two sets of V

CC

pins:

one set, V

CCINT

, for internal operation and input buffers, and

another set, V

CCIO

, for I/O output drivers. V

CCINT

pins must

always be connected to a 5.0V power supply. However, theV

CCIO

pins may be connected to either a 3.3V or 5.0V power

supply, depending on the output requirements. When V

CCIO

pins are connected to a 5.0V source, the I/O voltage levels are

compatible with 5.0V systems. When V

CCIO

pins are connect-

ed to a 3.3V source, the input voltage levels are compatiblewith both 5.0V and 3.3V systems, while the output voltage lev-els are compatible with 3.3V systems. There will be an addi-tional timing delay on all output buffers when operating in 3.3VI/O mode. The added flexibility of 3.3V I/O capability is avail-able in commercial and industrial temperature ranges.

Bus Hold Capabilities on all I/Os and Dedicated Inputs

In addition to ISR capability, a new feature called bus-hold hasbeen added to all F

LASH

370i I/Os and dedicated input pins.

Bus-hold, which is an improved version of the popular internalpull-up resistor, is a weak latch connected to the pin that doesnot degrade the device's performance. As a latch, bus-holdrecalls the last state of a pin when it is three-stated, thus re-ducing system noise in bus-interface applications. Bus-holdadditionally allows unused device pins to remain unconnectedon the board, which is particularly useful during prototyping asdesigners can route new signals to the device without cuttingtrace connections to V

CC

or GND.

Design Tools

Development software for the CY7C375i is available from Cy-press's WarpTM, Warp ProfessionalTM, and Warp EnterpriseTMsoftware packages. Please refer to the data sheets on theseproducts for more details. Cypress also actively supports al-most all third-party design tools. Please refer to third-party toolsupport for further information.

Maximum Ratings

(Above which the useful life may be impaired. For user guide-lines, not tested.)