We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout.
It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate.
Initially we would build cards for MCH connectors 1 and 2, providing clock distribution on finger 2,
and fast controls and trigger feedback on port 1 of fabric A on finger 1.

We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout.
It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate.
Initially we would build cards for MCH connectors 1 and 2, providing clock distribution on finger 2,
and fast controls and trigger feedback on port 1 of fabric A on finger 1.

Drawings

On the CTR2 FCLKA, TCLKA and TCLKC all enter an SN65LVDT125A LVDS crosspoint switch, and from there can be routed to the FPGA or links, possibly via an Si5319 frequency synthesizer.

Changed:

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It is challenging to understand the AMC and µTCA clocking. My current understanding is that dual-star backplanes typically fanout one clock from each MCH to each AMC, and return one clock from each AMC to either MCH.

We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout.
It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate.

Line: 29 to 29

On the CTR2 FCLKA, TCLKA and TCLKC all enter an SN65LVDT125A LVDS crosspoint switch, and from there can be routed to the FPGA or links, possibly via an Si5319 frequency synthesizer.

Changed:

<<

It is challenging to understand the AMC and µTCA clocking. My current understanding is that dual-star backplanes typically fanout one clock from each MCH to each AMC, and return one clock from each AMC to either MCH. This implies to me that we should use the single clock as a fixed-frequency link clock and that the LHC clock should be embedded in the stream sent on fabric port 1 from the MCH to the AMCs.

>>

It is challenging to understand the AMC and µTCA clocking. My current understanding is that dual-star backplanes typically fanout one clock from each MCH to each AMC, and return one clock from each AMC to either MCH.

Design Thoughts

Clocking – per AMC spec:

Line: 27 to 27

It is challenging to understand the AMC and µTCA clocking. My current understanding is that dual-star backplanes typically fanout one clock from each MCH to each AMC, and return one clock from each AMC to either MCH. This implies to me that we should use the single clock as a fixed-frequency link clock and that the LHC clock should be embedded in the stream sent on fabric port 1 from the MCH to the AMCs.

On the CTR2 FCLKA, TCLKA and TCLKC all enter an SN65LVDT125A LVDS crosspoint switch, and from there can be routed to the FPGA or links, possibly via an Si5319 frequency synthesizer.

It is challenging to understand the AMC and µTCA clocking. My current understanding is that dual-star backplanes typically fanout one clock from each MCH to each AMC, and return one clock from each AMC to either MCH. This implies to me that we should use the single clock as a fixed-frequency link clock and that the LHC clock should be embedded in the stream sent on fabric port 1 from the MCH to the AMCs.

We are designing a microTCA module called the DTC (DAQ and Timing Card) for the HCAL SLHC readout.
It is currently envisioned that this will occupy one of the MCH slots in a dual-star type crate.
Initially we would build cards for MCH connectors 1 and 2, providing clock distribution on finger 2,
and fast controls and trigger feedback on port 1 of fabric A on finger 1.