This paper deals with a comprehensive study and comparison on the conventional linear-assisted converter and a new structure named, LDO-assisted converter based on a new class-AB LDO regulator instead of the conventional linear one, in terms of efficiency, output ripple, and load transient response. The new structure reduces difference between input and output voltages and also switching frequency of the buck converter,
corresponding to higher power efficiency, desired for power management systems of battery operated devices like biomedical implants and energy harvesting applications. A comparison analysis is done and the results are validated in HSPICE in a 0.18 µm CMOS process.

Wireless RF power transfer requires the deployment of multiple energy transmitters (ETs) to cover an entire area of interest. This letter aims at bounding the minimum cumulative power that ETs need to inject into the network, such that the recipient nodes harvest sufficient power to operate. The main findings are that, in the worst case, this scales as O(s1-a/2), where s and a are the number of ETs and the channel path loss. That is, the overall power decreases with the number of ETs. It is also shown that sophisticated design for power transmission can further improve the scalability by s-1.

New exact critical conditions for predicting subharmonic instability in switching regulators are approximated by simple design-oriented expressions valid under practical conditions. These simplified expressions contain the ripple and slope information of the feedback control signal. Depending on the converter topology, the controller used and values of parasitic parameters, either the slope or the ripple can be dominant in predicting instability. A discussion on the validity of this interpretation is illustrated through six different examples of switching regulators using the concept of the spectral radius and the relative degree of the system loop. Using this approach, the boundary between the desired stable region and the subharmonic instability can be easily obtained. The theoretical results are validated by means of numerical simulations.

The issue that you are holding represents a milestone for a new initiative called “Late Breaking News” (LBN). This is the inaugural Special Issue of IEEE Transaction on Circuits and Systems II (TCAS II), presenting the best work submitted to the LBN track of International Symposium on Circuits and Systems (ISCAS) 2016. The purpose of the LBN initiative is to recognize the quickly changing nature of innovation in circuits and systems. We believe that this poses a unique opportunity for the IEEE Circuits and Systems Society (CAS) to emerge as a forum in which innovations that cross boundaries and platforms from signal processing to architecture, and from theory to application, can all be evaluated holistically. With this in mind, we created the new effort of LBN to allow a small and elite set of the best and most timely new results in any given year to be presented at special sessions within ISCAS and then published in this special issue of TCAS II. We are delighted with the overwhelming response to the LBN call for papers. These papers were originally submitted as brief, one-page abstracts and a small subset were selected by a team of highly qualified reviewers and experts. The final selected papers were presented a few months later at ISCAS, giving audiences at ISCAS a chance to see very interesting work in a range of topics. For this year, the final sessions were organized around the following three themes: 1)
Emerging technologies and low-power subsystems;

Networks-on-Chip (NoCs) are currently the paradigm of choice to interconnect the cores of a chip multiprocessor. However, conventional NoCs may not suffice to fulfill the on-chip communication requirements of processors with hundreds or thousands of cores. The main reason is that the performance of such networks drops as the number of cores grows, especially in the presence of multicast and broadcast traffic. This not only limits the scalability of current multiprocessor architectures, but also sets a performance wall that prevents the development of architectures that generate moderate-to-high levels of multicast. In this paper, a Wireless Network-on-Chip (WNoC) where all cores share a single broadband channel is presented. Such design is conceived to provide low latency and ordered delivery for multicast/broadcast traffic, in an attempt to complement a wireline NoC that will transport the rest of communication flows. To assess the feasibility of this approach, the network performance of WNoC is analyzed as a function of the system size and the channel capacity, and then compared to that of wireline NoCs with embedded multicast support. Based on this evaluation, preliminary results on the potential performance of the proposed hybrid scheme are provided, together with guidelines for the design of MAC protocols for WNoC.

In this paper, a new structure based on linear-assisted DC-DC buck converter principle is proposed. Using a segmented LDO regulator instead of the conventional linear one in the hybrid scheme, reduces the difference between input and output voltages and also the switching frequency of the buck converter, while the circuit provides a lower output ripple, better transient response. In addition, the proposal achieves higher power efficiency rather than the linear-assisted converter, desired for power management systems of battery operated devices like biomedical implants and energy harvesting applications. A comparison analysis is done with regards to the mentioned performance indexes between the proposed structure and linear-assisted buck converter and the results are validated in HSPICE in a 0.35 µm CMOS process.

This paper presents the design exploration of a basic cascode circuit (CAS) targeted to increase the intrinsic gain A# of a graphene field-effect-transistor (GFET) by decreasing its output conductance go. First, the parameters of a large-signal compact-model, based on drift-diffusion carrier transport, are fit to measurements carried on 2 CVD
GFETs, fabricated independently by different research groups. Second, CAS circuits are simulated to perform a design exploration and provide design guidelines. Third, CAS circuits are fabricated and consequently measured. Performance metrics are provided in terms of go, transconductance gm and hence A#. Against these metrics, a
quantitative comparison between CAS and GFET is performed and conclusions are derived.

Given the high multi-disciplinarity of Molecular Communications (MolCom), researchers often face significant difficulties to understand each other. This impairment not only affect researchers with different backgrounds, but it also affects the different software tools. This paper motivates the development of the Molecular Communication Markup Language (MolComML). MolComML is proposed as an XML-based format to represent the considered elements, interactions, configuration and results of the experiments and simulations in the field of MolCom. MolComML is designed with the objective of converging all fields of research within Mol-Com to help the exchange of information. We overview its main functionality and define its basic composing elements.

This paper analyzes the influence of neighboring absorbing receivers in a point-to-point Diffusion-based Molecular communication (DMC) link, following a simulation-driven approach. It is shown that the distance from the transmitter-receiver link, the distance between receivers and their radius have a noticeable impact upon both amplitude and signal detection.

Graphene is a unique material for the implementation of terahertz antennas due to extraordinary properties of the resulting devices, such as tunability and compactness. Existing graphene antennas are based on pure plasmonic structures, which are compact but show moderate to high losses. To achieve higher efficiency with low cost, one can apply the theory behind dielectric resonator antennas widely used in millimeter-wave systems. This paper presents the concept of hybridization of surface plasmon and dielectric wave modes. Radiation efficiency, reconfigurability, and miniaturization of antennas built upon this principle are qualitatively discussed and compared with those of pure plasmonic antennas. To this end, a quantitative study of pure and hybrid plas-monic one-dimensional guided-wave structures is performed. The results show that hybrid structures can be employed to design terahertz antennas with high radiation efficiency and gain, moderate miniaturization, and tunability, while terahertz antennas based on pure plasmonic structures can provide high miniaturization and tunability yet with low radiation efficiency and gain.

Communications are becoming the bottleneck in the performance of Chip Multiprocessor (CMP). To address this issue, the use of wireless communications within a chip has been proposed, since they offer a low latency among nodes and high reconfigurability. The chip scenario has the particularity that is static, and the multipath can be known a priori. Within this context, we propose in this paper a simple yet very efficient modulation technique, based on Impulse Radio-On–Off-Keying (IR-OOK), which significantly optimizes the performance in Wireless Network-on-Chip (WNoC) as well as off-chip scenarios. This technique is based on interspersing information pulses among the reflected pulses in order to reduce the time between pulses, thus increasing the data rate. We prove that the final data rate can be considerably increased without increasing the hardware complexity of the transceiver.

The Wireless Network-on-Chip (WNoC) paradigm holds considerable promise for the implementation of fast and efficient on-chip networks in manycore chips. Among other advantages, wireless communications provide natural broadcast support, a highly desirable feature in manycore architectures yet difficult to achieve with current interconnects. As technology advancements allow the integration of more wireless interfaces within the same chip, a critical aspect is how to efficiently share the wireless medium while reliably carrying broadcast traffic. This paper introduces the {Broadcast, Reliability, Sensing} protocol (BRS-MAC), which exploits the particularities of the WNoC context to meet its stringent requirements. BRS-MAC is flexible and employs a collision detection and notification scheme that scales with the number of receivers, making it compatible with broadcast communications. The proposed protocol is modeled and evaluated, showing a clear latency advantage with respect to wired on-chip networks and WNoCs with token passing.

Powering wireless sensors has become a key challenge to enable the Internet of Things vision. A common approach to achieve this is to use Energy Harvesting. By means of this technology, sensors have access to an unlimited source of energy, which can extend their operation lifetime.
Unfortunately, typically the energy that is available surrounding the sensors is neither controllable nor predictable, showing significant variations in the expected harvested energy in terms of both space and time. This can cause the temporal disconnection of parts of the wireless network.
The objective of this thesis is to mitigate the undesirable effects of the spatio-temporal variations of the surrounding energy, by following a two-fold approach: first, to provide a high level understanding of the involved trade-offs in the design of a wireless sensor and the interconnecting network. Then, to synthesize an energy field to guarantee the required amount of ambient energy at the surrounding of the considered nodes.
The first part of the thesis starts by presenting a formal description of the environment. The derived energy model is first used to answer fundamental questions on throughput scaling and, then, to provide design guidelines for energy harvesting sensors. It is found that energy harvesting is a scalable solution to power and recharge IoT sensors, which require additional circuit design to guarantee their operation in energy scarce scenarios.
On the second part of this work, wireless RF power transmission from controllable Energy Transmitters (ETs) is considered as a feasible approach to synthesize an energy field to power sensors at-a-distance, hence tackling the lack of available ambient energy in spatial regions, at the cost of occupying the available wireless spectrum. Due to the limited transmission range of this approach, the use of multiple ETs to cover entire areas is required. We first discuss on the feasibility of synthesizing energy fields with multiple ETs. We show that powering those sensors with multiple ETs stands as a scalable approach, which presents a trade-off between the channel conditions and the energy multiplexing design complexity. We, then, present an opportunistic scheme to leverage the generated interferences of multiple ETs. Finally, we propose a joint energy and communication method to circumvent the imposed trade-offs of in-band multi-ET wireless RF power transmission.
Overall, we find that the analysis and design of wireless networked sensing systems, enabled by energy harvesting, and the development of novel wireless RF power transmissions schemes will play a key role in the future development of autonomous IoT deployments.

In this paper, a new structure based on linear-assisted DC-DC buck converter principle is proposed. Using a new class-AB LDO regulator instead of the conventional linear one (based on a push-pull output stage) in the hybrid scheme, reduces the difference between input and output voltages and also the switching frequency of the buck converter. Thus, the proposal achieves higher power efficiency rather than the conventional linear-assisted converter, desired for power management systems of battery operated devices like biomedical implants and energy harvesting applications. In addition, the circuit provides a lower output ripple and better transient response. A comparison analysis is done with regards to the considered performance indexes between the proposed structure and linear-assisted buck converter, and the results are validated in HSPICE in a 0.35 µm CMOS process.

This paper presents an output-capacitorless low dropout (LDO) regulator based on improved flipped voltage follower power stage for use in power management circuits. A new error amplifier (EA) structure, named as gain-bandwidth enhanced EA, is embedded in the LDO regulator. The LDO regulator is designed for the input and output voltages of 1.2 V and 1 V, respectively. Fast transients, low overshoot and undershoot, and low quiescent current of 6 µA are achieved for the proposed circuit. The LDO regulator is designed for maximum load current of 50 mA, achieving the current and power efficiencies of 99.99% and 83.3%, respectively. Additionally, up to 131 pF capacitance is used in the proposed LDO structure. The proposed circuit is designed and verified in HSPICE in TSMC 0.18 µm mixed signal CMOS process.

Recent years have seen the emergence and ubiquitous adoption of Chip Multiprocessors (CMPs), which rely on the coordinated operation of multiple execution units or cores. Successive CMP generations integrate a larger number of cores seeking higher performance with a reasonable cost envelope. For this trend to continue, however, important scalability issues need to be solved at different levels of design. Scaling the interconnect fabric is a grand challenge by itself, as new Network-on-Chip (NoC) proposals need to overcome the performance hurdles found when dealing with the increasingly variable and heterogeneous communication demands of manycore processors. Fast and flexible NoC solutions are needed to prevent communication become a performance bottleneck, situation that would severely limit the design space at the architectural level and eventually lead to the use of software frameworks that are slow, inefficient, or less programmable.
The emergence of novel interconnect technologies has opened the door to a plethora of new NoCs promising greater scalability and architectural flexibility. In particular, wireless on-chip communication has garnered considerable attention due to its inherent broadcast capabilities, low latency, and system-level simplicity. Most of the resulting Wireless Network-on-Chip (WNoC) proposals have set the focus on leveraging the latency advantage of this paradigm by creating multiple wireless channels to interconnect far-apart cores. This strategy is effective as the complement of wired NoCs at moderate scales, but is likely to be overshadowed at larger scales by technologies such as nanophotonics unless bandwidth is unrealistically improved.
This dissertation presents the concept of Broadcast-Oriented Wireless Network-on-Chip (BoWNoC), a new approach that attempts to foster the inherent simplicity, flexibility, and broadcast capabilities of the wireless technology by integrating one on-chip antenna and transceiver per processor core. This paradigm is part of a broader hybrid vision where the BoWNoC serves latency-critical and broadcast traffic, tightly coupled to a wired plane oriented to large flows of data. By virtue of its scalable broadcast support, BoWNoC may become the key enabler of a wealth of unconventional hardware architectures and algorithmic approaches, eventually leading to a significant improvement of the performance, energy efficiency, scalability and programmability of manycore chips.
The present work aims not only to lay the fundamentals of the BoWNoC paradigm, but also to demonstrate its viability from the electronic implementation, network design, and multiprocessor architecture perspectives. An exploration at the physical level of design validates the feasibility of the approach at millimeter-wave bands in the short term, and then suggests the use of graphene-based antennas in the terahertz band in the long term. At the link level, this thesis provides an insightful context analysis that is used, afterwards, to drive the design of a lightweight protocol that reliably serves broadcast traffic with substantial latency improvements over state-of-the-art NoCs. At the network level, our hybrid vision is evaluated putting emphasis on the flexibility provided at the network interface level, showing outstanding speedups for a wide set of traffic patterns. At the architecture level, the potential impact of the BoWNoC paradigm on the design of manycore chips is not only qualitatively discussed in general, but also quantitatively assessed in a particular architecture for fast synchronization. Results demonstrate that the impact of BoWNoC can go beyond simply improving the network performance, thereby representing a possible game changer in the manycore era.

This article presents a low quiescent current output capacitorless quasi-digital CMOS LDO regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is broken up to two smaller sizes based on a breakup criterion defined here, which considers the maximum output voltage variations to different load current steps to find the suitable current boundary for breaking up. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Therefore, using one smaller transistor for low load currents, and another one larger for higher currents, is the best trade-off between output variations, complexity, and power dissipation. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.35 µm CMOS process to supply a load current between 0-100 mA while consumes 7.6 µA quiescent current. The results reveal 46% and 69% improvement on the output voltage variations and settling time, respectively.

This paper introduces the concept of switch-mode tunable emulated reactive networks. The idea of implementing reactive networks based on the theory of gyrators is proposed and characterized in an application-driven design-oriented context. By means of using switch-mode power processing converters to synthesize gyrators, small
capacitors or inductors are effectively multiplied to emulate larger ideally lossless reactive elements. The proposed idea enables to electronically tune the values of reactive elements by means of timing control variables. The proposed tunable reactive networks target many potential applications such as tunable-front-ends for energy harvesting, electronic compensating active power filters, and tunable-front-ends for wireless power transfer links.

Simultaneous Wireless Information and Power Transmission (SWIPT) has been proposed as a feasible solution to enable joint power and data transfer for the nodes of a battery-less wireless networked sensor system. Different from existing approaches, where the incident energy is split between decoding and harvesting blocks at the receiver chain, this paper describes the design and implementation of an all-digital receiver circuit. We leverage the internal control signals of the circuit, targeting ultra-low power consumption, low bit-rate applications in SWIPT. A proof-of-concept receiver is modeled, implemented using off-the-shelf hardware, and validated through extensive experiments. Quantitative results demonstrate the benefits of this joint energy-data reception approach through a single receiver chain, offering bit-rates of 400 bps.

This paper deals with a circuit proposal along with theoretical analysis to provide a solution for enhancing
the stability and transient performance of external capacitorless low-dropout regulators (CL-LDOs) by segmenting the
pass transistor to smaller sizes. The stability and transient analysis is carried out on the CL-LDO with two different
size-segmented pass transistors in comparison with the conventional CL-LDO with single large size pass device. The
analysis shows that the pass transistor segmentation leads to better stability, i.e., greater phase margin especially at
no-load and light-load conditions, wider bandwidth, and improved transient behavior, i.e., lower settling time and output
voltage deviations due to the load transients. The aforementioned topologies are modeled and validated in HSPICE
using a 0.35 µm CMOS process, and the results are in conformity with the analytical statements.

This paper proposes the use of double-frequency (DF) buck converter architecture consisting of a merged structure of high and low frequency buck cells as a candidate topology for envelope elimination and restoration (EER) applications and integrated power supply of RF power amplifiers (RFPA) to obtain favorable tradeoffs in terms of efficiency, switching ripple, bandwidth, and tracking capability. It is shown that having two degrees of freedom in designing the DF buck helps to achieve high efficiency, low output ripples, and tracking capability with low ripples, simultaneously. A comparison analysis is done with regards to the mentioned performance indexes with the standard and three-level buck converters; in addition, the results are validated in HSPICE in BSIM3V3 0.35-µm CMOS process.

We appreciate the careful analysis and comments by Frégonèse and Zimmer, where they show that the model proposed, accurately reproduces experimental data from graphene FETs (GFETs) when an appropriate smoothing factor is used. The authors have proposed an extension of this model by Frégonèse et al. with an exact calculation of a denominator. We compared the model extension with the original work. Unfortunately, we did not use a suitable smoothing factor in our comparison, which lead to a strong artifact in the calculations and was absent in the exact solution. Following the argument, the authors agree with our colleagues that there is no artifact at the Dirac point in their GFET compact-model when a proper smoothing factor is used. We were not aware of the requirement of such a factor in specific cases when implementing the model because it is not mentioned; therefore, we apologize for misrepresenting their work.

In shared-memory multiprocessing, fine-grain synchronization is challenging because it requires frequent communication. As technology scaling delivers larger manycore chips, such pattern is expected to remain costly to support.; In this paper, we propose to address this challenge by using on-chip wireless communication. Each core has a transceiver and an antenna to communicate with all the other cores. This environment supports very low latency global communication. Our architecture, called WiSync, uses a per-core Broadcast Memory (BM). When a core writes to its BM, all the other 100+ BMs get updated in less than 10 processor cycles. We also use a second wireless channel with cheaper transfers to execute barriers efficiently. WiSync supports multiprogramming, virtual memory, and context switching. Our evaluation with simulations of 128-threaded kernels and 64-threaded applications shows that WiSync speeds-up synchronization substantially. Compared to using advanced conventional synchronization, WiSync attains an average speedup of nearly one order of magnitude for the kernels, and 1.12 for PARSEC and SPLASH-2.

Wireless RF power transmission from dedicated Energy Transmitters (ETs) is emerging as a promising approach to enable battery-less wireless networked sensor systems. However, when data communication and RF energy recharging occur in-band, sharing the RF medium and devoting separate access times for both operations
raises architectural and protocol level challenges. This paper proposes a novel method of concurrent transmission of data and energy to solve this problem, allowing ETs to transmit energy and sensors to transmit data in the same band synchronously. Our key idea concerns devising a physical layer modulation scheme that allows the data transmitting
node to introduce variations in the envelope of the energy signal at the intended recipient. We implemented a proofof-concept receiver, modeled and validated through extensive experimentation. We then propose a new physical layer mechanism for guaranteed successful delivery of information in a point-to-point link. Quantitative results demonstrate the feasibility of joint energy-data transfer, along with its associated benefits and tradeoffs.

In shared-memory multiprocessing, fine-grain synchronization is challenging because it requires frequent
communication. As technology scaling delivers larger manycore chips, such pattern is expected to remain costly to
support. In this paper, we propose to address this challenge by using on-chip wireless communication. Each core has
a transceiver and an antenna to communicate with all the other cores. This environment supports very low latency
global communication. Our architecture, calledWiSync, uses a per-core Broadcast Memory (BM). When a core writes
to its BM, all the other 100+ BMs get updated in less than 10 processor cycles. We also use a second wireless channel
with cheaper transfers to execute barriers efficiently. WiSync supports multiprogramming, virtual memory, and context
switching. Our evaluation with simulations of 128- threaded kernels and 64-threaded applications shows that WiSync
speeds-up synchronization substantially. Compared to using advanced conventional synchronization,WiSync attains
an average speedup of nearly one order of magnitude for the kernels, and 1.12 for PARSEC and SPLASH-2.

This article presents a low quiescent current output-capacitorless quasi-digital complementary metal-oxide-semiconductor (CMOS) low-dropout (LDO) voltage regulator with controlled pass transistors according to load demands. The pass transistor of the LDO is segmented into two smaller sizes based on a proposed segmentation criterion, which considers the maximum output voltage transient variations due to the load transient to different load current steps to find the suitable current boundary for segmentation. This criterion shows that low load conditions will cause more output variations and settling time if the pass transistor is used in its maximum size. Furthermore, this situation is the worst case for stability requirements of the LDO. Therefore, using one smaller transistor for low load currents and another one larger for higher currents, a proper trade-off between output variations, complexity, and power dissipation is achieved. The proposed LDO regulator has been designed and post-simulated in HSPICE in a 0.18¿µm CMOS process to supply a stable load current between 0 and 100¿mA with a 40¿pF on-chip output capacitor, while consuming 4.8¿µA quiescent current. The dropout voltage of the LDO is set to 200¿mV for 1.8¿V input voltage. The results reveal an improvement of approximately 53% and 25% on the output voltage variations and settling time, respectively.

Multisource energy harvesters are a promising, robust alternative to power the future Internet of Nano Things (IoNT), since the network elements can maintain their operation regardless of the fact that one of its energy sources might be temporarily unavailable. Interestingly, and less explored, when the energy availability of the energy sources present large temporal variations, combining multiple energy sources reduce the overall sparsity. As a result, the performance of a multiple energy harvester powered device is significantly better compared to a single energy source even if they harvest the same amount of energy. In this context, a framework to model and characterize the area for multiple source energy harvesting (EH) powered systems is proposed. This framework takes advantage of this improvement in performance to provide the optimal amount of energy harvesters, the requirements of each energy harvester, and the required energy buffer capacity, such that the overall area or volume is minimized. On top of these results, self-tunable energy harvesters are explored as a solution and compared to multisource EH platforms. As the results show, by conducting a joint design of the energy harvesters and the energy buffer, the overall area or volume of an EH powered device can be significantly reduced.

The scalability of Network-on-Chip (NoC) designs has become a rising concern as we enter the manycore era. Multicast support represents a particular yet relevant case within this context, mainly due to the poor performance of NoCs in the presence of this type of traffic. Multicast techniques are typically evaluated using synthetic traffic or within a full system, which is either simplistic or costly, given the lack of realistic traffic models that distinguish between unicast and multicast flows. To bridge this gap, this paper presents a trace-based multicast traffic characterization, which explores the scaling trends of aspects such as the multicast intensity or the spatiotemporal injection distribution for different coherence schemes. This analysis is the basis upon which the concept of multicast source prediction is proposed, and upon which a multicast traffic model is built. Both aspects pave the way for the development and accurate evaluation of advanced NoCs in the context of manycore computing.

Two trends have recently emerged in space systems and could even further strengthen in the future: small satellites, with the development of key modularisation and miniaturisation technologies, and the deployment of constellations and distributed networks of satellites. It is of primordial importance for Europe to properly analyse those trends and determine whether or not they could provide a competitive advantage for Earth Observation (EO) systems.
To address those challenges, “Operational Network of Individual Observation Nodes,” (ONION) investigates the distribution of spacecraft functionalities into multiple cooperating nodes, leveraging on the emerging fractionated and federated satellite system concepts. The proposed concept provides augmentation, supplementation, and possibilities of new mission for future EO Missions (for science and commercial applications).
ONION objectives:
1. Review the emerging fractionated and federated observation system concepts
2. Identify potential benefits to be obtained in light of observation needs in different Earth Observation domains
3. Identify key required technology challenges entailed by the emerging fractionated and federated satellite system concepts, to be faced in Horizon 2021-2027
4. Validate observation needs with the respective user communities to be fit for purpose in terms of scientific and commercial applications
5: To propose an overall strategy and technical guidelines to implement such concepts at Horizon 2021-2027
ONION will confirm the feasibility of the first established concepts to respond to the identified needs through use-cases. The baseline of the concept consists to supplementing current mission profiles with missing observation bands, augmenting mission lifetimes, and ultimately sharing the capabilities across multiple spacecraft platforms. ONION will enable mission designers and implementers to decide which fractionated and federated concepts will provide competitive imaging from space.

In recent years, several research groups have been created in the emerging research area of molecular communications. This is seen as a fundamental enabler for nano-scale networked devices. The heterogeneity of the biological environments that can host nano-scale communications has produced different proposals (e.g. neuronal networks, molecular diffusion, flow-based carrier mobility) analyzed by means of different research approaches and tools (different analytical models, simulators, lab experiments). For this reason, the need of integrating research activities at an EU level has emerged. The main objective of the CIRCLE is to integrate islands of heterogeneous research activities in a common research framework. The nature of the proposal is therefore strategic for the EU research objectives, highly interdisciplinary, inclusive of any input coming from any research activities that can contribute to identifying a research roadmap for the future years and feasible future exploitation plans.
In the short term, CIRCLE will facilitate the creation of an EU wide Molecular Communications (CIRCLE) forum and provide a support infrastructure for coordination of research across Europe. In the medium term, it will foster knowledge sharing via the CIRCLE forum and a dedicated web portal. This will focus on the sharing of both research methodologies and simulation code repositories. It will establish expert working groups in different research topics within the Molecular Communications domain and develop strategic Roadmaps for both academic research and industry involvement. In the long term, CIRCLE will push the Roadmaps at a Member State and EU level to ensure Molecular Communications research converges rapidly towards feasible products of interest in the marketplace.