e Technique Power grid verification in modern integrated circuits is an integral part of early system design where adjustments can be most easily incorporated. This work describes an early verification approach under the framework of current constraints where worst-case node voltage drops are computed via linear programs proportional to the grid size. The researchers propose an efficient method based on a sparse approximate inverse technique to greatly reduce the size of such linear programs while ensuring a user-specified overestimation margin (in volts) on the exact solution. Univ. of Toronto SRC Contact: William H. Joyner (william.joyner@src.org) Research Highlight: Report on the Variation-Aware Standard Cell Electrical Analysis Process variations, in particular those due to the lithography limitations are among the most fundamental challenges in nanometer integrated circuits. There are two types of lithography variations: systematic and random variation. The systematic lithography variation is introduced due to geometry pattern proximity. The random lithography variation is caused by random uncertainties. Line edge roughness (LER) is major source of random variation and may lead to serious device parameter fluctuations for sub-45nm ICs. For example, LER has been reported to be in the order of several nanometers and LER does not decrease as the device shrinks. Limited studies of LER have been conducted in some specific process and device modeling, but not at the standard cell/gate level or above. Standard cells are basic building blocks for digital designs and should be characterized with considering the random LER variation for early design characterization and optimization. This report proposes a new analytical LER variation model which can generically handle any RMS (root mean square) amplitude and frequency of LER and use it for LER variation aware standard cell characterization and analysis. The accuracy of the proposed LER model is validated against the physics based TCAD simulations. The team also presents a method to account for the LER variations in both statistical and deterministic analysis flows. Results show that the saturation current can vary by as much as 11.7% when the RMS value of LER is 12% from its nominal line edge for a typical standard cell (e. g. , NAND2), and the delay sensitivities due to LER variations is changed as much as 12.5% at typical corner and 31.6% at process corner when compared with that of the target design in the 45nm node standard cell library. Univ. of Texas/Austin SRC Contact: William H. Joyner (william.joyner@src.org)

www.src.org GRC is a program of Semiconductor Research Corporation P.O. Box 12053, Research Triangle Park, NC 27709

Technical Thrust: Test and Testability
Research Highlight: Initial Results of High-Quality Delay Tests on an Industrial Design, Including Results of Incorporating Resistive Opens and Shorts, Crosstalk and Fault Coverage Metric Current status in applying K Longest Path Per Gate (KLPG) test patterns to an AMD quad core processor is described. The goal is to determine whether system tests (and so test cost) can be reduced through the use of KLPG. The primary challenges are the size of the design, extensive clock gating, mixture of mixed D flip-flop and LSSD scan chains, and extensive test constraints. Texas A&M University SRC Contact: William H. Joyner (william.joyner@src.org) Research Highlight: Development of KLPG Tests Targeting Crosstalk This report summarizes research on maximizing delay increases due to capacitive crosstalk in the CodGen K Longest Paths Per Gate (KLPG) test generator. The path generation algorithm is modified so as to generate capacitively-coupled transitions that are aligned in time with the path under test. Texas A&M University SRC Contact: William H. Joyner (william.joyner@src.org) Research Highlight: Report on Fault Modeling and Analysis This report presents a modeling approach for fault coverage computation taking the relative probability into account. The researchers decouple the absolute probability computation of faults in two ways: the relative probability is calculated using layout information and generic distributions, the absolute probability is not needed as long as the team has a general defectivity information. The authors obtain this information through outlier analysis. This report shows the steps involved and how the member companies can get involved in the development of these techniques. Arizona State University SRC Contact: David C. Yeh (david.yeh@src.org) Research Highlight: Thermal Characterization of BIST, Scan Design and Sequential Test Methodologies It is a well known fact that during testing of a complex integrated circuit (IC), power consumption can far exceed the values reached during its normal operation. High power consumption, combined with limited cooling support, leads to overheating of ICs. This can cause permanent damage to the chip or can invalidate test results due to changes in the path delay. Therefore, even good chips can fail the test. To prevent this problem, a methodology to generate the thermal profile of chips during test is needed. If such profiles are provided beforehand, temperature-aware testing techniques can be devised. This paper addresses this problem by presenting a methodology for thermally characterizing circuits under test. In this methodology, first, the test sequences for each targeted test strategy, namely, built-in self-test (BIST), scan design and sequential test generation, are generated automatically. Then, power profiles are extracted by using the switching activity information obtained from simulations. Finally, a very fast thermal profiling tool is used to produce the final thermal profiles. To the best of the team's knowledge, this is the first work on characterizing the thermal effects of different test methods. Such a thermal characterization can be leveraged for temperature-aware system-on-chip (SoC) test scheduling. Experimental results present the maximum temperature values attained by using different testing techniques on several benchmarks. Results also demonstrate that low power testing techniques are not necessarily temperatureaware.

Princeton University SRC Contact: William H. Joyner (william.joyner@src.org) Research Highlight: Report on Test Data Compression Based on Deterministic Vector Clustering of Incompatible Test Cubes A new test data compression scheme presented in this report further explores the occurrence of similar vectors in test stimuli. With this technique it is not necessary to resort to any form of dictionaries. Instead, its goal is to see that test cubes that feature many similar specified bits are merged and EDT-compressed even in the presence of conflicts, whose particulars are encoded efficiently, as well. As a result, our solution offers very high compression ratios, elevates the encoding efficiency well above the threshold of 1.00, and preserves all benefits of continuous flow decompression. Poznan University of Technology SRC Contact: William H. Joyner (william.joyner@src.org) Research Highlight: Development of Low-Cost Supply Noise, Power Dissipation and Temperature Models This report summarizes research on the development of low-cost supply noise, power dissipation and temperature models. This work focuses on achieving constant power dissipation during the scan-in/out process, since this dominates total power dissipation during scan-based testing. With constant power dissipation, the temperature of the chip under test can be easily characterized at the test head, so that the temperature of each test pattern is known (for a given speed bin). Circuit delay rises with temperature, 3555% for a 100C rise in 65 nm technology. This information can then be used to adjust the capture clock timing during delay test, in order to ensure that all speed paths are tested with the minimum timing margin. Constant power can also be used to avoid unsafe temperature conditions that lead to test overkill. In addition to reordering patterns to achieve constant power, the patterns are filled to reduce their power. Texas A&M University SRC Contact: William H. Joyner (william.joyner@src.org)

Technical Thrust: Verification
Research Highlight: LEMA The latest version of LEMA has undergone a major overhaul. In addition to a much better GUI, LEMA now includes project management features, an editor for the labeled hybrid Petri net (LHPN) model, a learn tool that allows you to generate an LHPN from simulation data, a verification tool for checking properties of your VHDL-AMS or LHPN models, and a grapher for examining your simulation data. Univ. of Utah SRC Contact: William H. Joyner (william.joyner@src.org) Research Highlight: Formal Functional Verification of Flash Memories This is a report on an approach to abstract, formalize, and verify Flash memories. Flash memories contain specialized floating-gate or split-gate transistors which preclude traditional switch-level abstractions. The goal was to develop a new abstraction mechanism that is agnostic to transistor type, and use it for verifying a variety of Flash designs. The work provides the first platform for formal, functional verification of Flash memories. Univ. of Texas/Austin SRC Contact: William H. Joyner (william.joyner@src.org)

Research Highlight: Report on a Complete Version of Our Verification Tool The goal of this research task is to develop methodology and tools to support the simulation aided verification of analog and mixed-signal circuits. This report describes the latest version of LEMA, the tool that the researchers are developing for this task. Since the last release of LEMA, it has undergone a major overhaul. In addition to a much better GUI, LEMA now includes project management features, an editor for our labeled hybrid Petri net (LHPN) model, a learn tool that allows you to generate an LHPN from simulation data, a verification tool for checking properties of your VHDL-AMS or LHPN models, and a grapher for examining your simulation data. Univ. of Utah SRC Contact: William H. Joyner (william.joyner@src.org)

Device Sciences
Technical Thrust: Analog and Mixed Signal
Research Highlight: Power-Frequency Locus of 65nm RF Power CMOS This report presents measurements of the power-frequency locus for 65nm RF power CMOS devices. The researchers found that output power scales linearly with width for device widths smaller than 200um but starts to saturate for wider devices. This effect is exacerbated at higher frequencies, resulting in a decrease in the peak output power and the corresponding power added efficiency with increasing frequency. The main reason for the power saturation is the presence of non-scalable parasitic resistances in the wide devices. Mass. Institute of Technology SRC Contact: David C. Yeh (david.yeh@src.org)

Technical Thrust: Device Sciences Modeling & Simulation
Research Highlight: FLOOPS/FLOODS This is a script demonstrating how FLOOPS and FLOODS can simultaneously solve for both solid-phase regrowth and diffusion. A diffusivity dependent on material state is included. This shows how the links between level set and alagator can be used. Univ. of Florida SRC Contact: Kwok Ng (Kwok.Ng@src.org) Research Highlight: Inverse Piezoelectric Modeling in FLOOPS This report describes the implementation of the inverse peiozelectric modeling in FLOOPS and includes example code. Univ. of Florida SRC Contact: Kwok Ng (Kwok.Ng@src.org) Research Highlight: Final Report: Modeling Solid Phase Epitaxial Regrowth using Level Set Methods This final report is on solid-phase epitaxial regrowth modeling using level-set methods. Univ. of Florida SRC Contact: Kwok Ng (Kwok.Ng@src.org)

Research Highlight: Final Report: Strain Modeling During this contract, the team added elastic simulation capability to alagator. Initial implementation was 2D, but the researchers extended that to 3D. The research team added the capability to include generically strain in the body of the device, generic boundary conditions on the sides of the device, and inverse piezostrain operators. They also allowed the Young's modulus and Poisson's ratio to be free functions of such variables like temperature, doping, and composition. Univ. of Florida SRC Contact: Kwok Ng (Kwok.Ng@src.org) Research Highlight: Final Report Summarizing Research Accomplishments on Strained Wafer Studies This final report outlines research accomplishments of completed work and plans for future directions. Univ. of Florida SRC Contact: Kwok Ng (Kwok.Ng@src.org) Research Highlight: Report on KLMC Code for Prediction of Dislocation Dynamics in the Presence of Anisotropic Stress and Nonequilibrium Point Defect Concentrations The authors have simulated the formation of extended defects such as {311} clusters and dislocation loops using a kinetic Monte Carlo code. Applied anisotropic stress alters the formation energies of defect structures and thus has an impact on the formation and evolution of extended defects. Univ. of Washington SRC Contact: Kwok Ng (Kwok.Ng@src.org) Research Highlight: Final Report: Amorphous Layer Diffusion and Regrowth Regarding work in the Si system, it was determined that B diffusion is influenced by the presence of traps in the amorphous phase. It was also determined that the choice of species used for implantation can influence the generation of these traps. The solubility of B in amorphous Si was also determined along with the observation that diffusion in amorphous material is orders of magnitude faster than in crystalline material. Finally, the addition of C did not alter B diffusion, but increasing C content did tend increase the amount of B that is mobile. Univ. of Florida SRC Contact: Kwok Ng (Kwok.Ng@src.org)

Technical Thrust: Digital CMOS
Research Highlight: High-k/Metal Gate Stacks for CMOS Transistors Based on Si and III-V Channels The researchers have successfully developed highly reliable, ~1.43 nm EOT (without quantum correction), TiO(2)/Al(2)O(3) gate dielectric stack on Si with excellent electrical properties. The team has also obtained IETS (Inelastic Electron Tunneling Spectroscopy) data for ultra-thin TiO(2)/Al(2)O(3) gate dielectric stack on GaAs, which revealed a wealth of information concerning microstructures in the gate dielectric and at the dielectric/GaAs interface, as well as associated traps. Yale University SRC Contact: Kwok Ng (Kwok.Ng@src.org)

Research Highlight: Report on Initial p-channel pre-MOSFETs This report summarizes activity on establishing a baseline III-V structure in which a 2 dimensional hole gas is formed in an undoped, unstrained In(0. 53)Ga(0. 47)As channel layer. Having established this baseline, a systematic investigation of the impact of strain on the hole mobility can be undertaken. The baseline structure has demonstrated a room temperature mobility of 60-70 cm(2)/Vs with carrier concentrations in the range 1. 8x10(12) cm(-2) to 2. 4x10(12) cm(-2), depending on the doping levels incorporated. The rather modest mobility measurements may be compromised by diffusion of beryllium dopant into the device channel. This will be investigated by temperature dependent magnetotransport measurements which are on-going, and can be mitigated by moving to carbon doping, a system for which has been established recently in one of our other MBE tools. Univ. of Glasgow SRC Contact: Kwok Ng (Kwok.Ng@src.org) Research Highlight: Report on Process Modules Suitable for Realization of Gated Hall Bars to Enable Magnetotransport Measurements This report primarily comprises a review of ohmic contacts to p-type III-V materials, highlighting the motivation for choosing a Pt/Ti/Pt/Au metallization scheme as the means to realizing Hall bars which will, in future, be extensively used in the characterization of the impact of strain in p-type InGaAs materials. The Pt/Ti/Pt/Au contact has been used to successfully contact first-pass "MOSFET" structures, which are more fully described in the Progress Report for Task 1637. 002 . Univ. of Glasgow SRC Contact: Kwok Ng (Kwok.Ng@src.org) Research Highlight: Final Report:III-V on Silicon This report summaries the progress of SRC project 1580, III-V on silicon, during the period between Jan 2006 and Dec 2008. In this project, the researchers collaborated with IBM T. J. Watson Research Center, in which the team worked on epitaixal growth and IBM T. J. Watson Research Center focuses on the device fabrication and measurement. The entire work consists of three parts - MBE tool installation, characterization of the epitaxial growth, and the fabrication, design, and characterization of the III-V MOSFET. Univ. of Michigan SRC Contact: Kwok Ng (Kwok.Ng@src.org) Research Highlight: Piezoresistance from 77K to 300K Uniaxial stress enhanced hole mobility is measured for (100)/<110> silicon (Si) pchannel metal-oxidesemiconductor field-effect-transistor (MOSFET) from 300 to 87K. For the technologically important longitudinal compressive stress along <110>, the percent change in the uniaxial stress enhanced hole mobility is observed to increase at lower temperatures, which is opposite to devices under biaxial stress. The results are compared to six band k times p with finite difference formalism which shows that the larger mobility gain at lower temperatures results from greater uniaxial stress induced hole conductivity mass reduction due to more holes occupying states at the band edge which have a light hole conductivity mass in the channel direction. Small uniaxial stress altered phonon and surface roughness scattering rates are not an important factor in the enhanced mobility. Univ. of Florida SRC Contact: Kwok Ng (Kwok.Ng@src.org)

Research Highlight: Report Piezoreistance of SiGe and Ge at >1GPa of Stress The low-power and high-performance requirements at the 22nm and beyond technology generations may not be met with a Si channel MOSFET even with the highly successful performance boosters like process induced uniaxial stress. This has led to alternate high-mobility channel materials (group IV and III-V) being investigated extensively. However unstrained hole mobility in these materials is unlikely to be competitive with the 3-400% uniaxial stress enhanced mobility in Si. Selective epitaxy to obtain defectfree high mobility strained SixGe1-x channels have been recently investigated but only for small (<30%) Ge concentrations. Strain additivity on these SiGe channels using wafer bending has been investigated but only for the (110) surface orientation and stresses below 150MPa. In this work both, major integration issues as well as the additivity of strain in the (100) surface oriented SixGe1-x and Ge channels are addressed. These heterostructure Si/SixGe1-x/Si Quantum Wells (QW) are shown to have low Band-ToBand- Tunneling current despite their small bandgap and low interface state density which adds to their merit as a possible option for replacing Si channels. The performance enhancements from uniaxial strain are investigated through k. p calculations and validated with wafer bending experiments. Univ. of Florida SRC Contact: Kwok Ng (Kwok.Ng@src.org) Research Highlight: Report on SegFET Performance Enhancement Approaches This report describes approaches to SegFET performance enhancement and benefits of the corrugated substrate for reducing variability. Univ. of California/Berkeley SRC Contact: Kwok Ng (Kwok.Ng@src.org)

Technical Thrust: Memory Technologies
Research Highlight: Report on the Incorporation of States and Cr-SrZO(3) Energies into T-CAD This report describes the applicability of a mobile dopant model to describe physical observations of resistance switching. Instead of focusing on using oxide parameters in T-CAD, this work focuses on the inclusion of a chemical boundary condition that allows for the qualitative reproduction of a wide range of experimentally observed features. This report focuses on results of simulations carried out on various platforms, including TCAD, matlab, and comsol- all of which generate identical results- and that include both oxides and Si as the functional layer. Quantitative matching to the experimental results is poor, owing to limitions in understanding of the physical carrier injection process, but qualitative agreement is excellent for a range of experimentally observed switching phenomena. Carnegie Mellon University SRC Contact: Kwok Ng (Kwok.Ng@src.org) Research Highlight: Report on the Assessment of Junction States and Energies in Cr-SrZO(3) Junctions This report details observations regarding the role of crystal defects in the resistance switching of Schottky barriers formed at interfaces between metals and SrTiO(3) single crystals. This work focuses on characterization of these physically observable defects rather than the electronics states at the interfaces, as originally planned. This change reflects the evolving understanding of the role of defects in switching. These defects visible from the surface appear to play an important role in the switching behavior of these junctions. Measurements of the junction resistance as a function of electrode size and spacing indicate that these defects have a density on the surface of about 1 per square micron. EBIC images indicate that these defects also extend below the surface and some regions of clear surface have subsurface defects.

Contact areas that include these defects at the surface show low switching resistance ratio, although the junctions are still rectifying. Smaller contacts, which avoid surface defects, but which (presumably) contact the subsurface defects show high resistance contrast, but poor switching stability. The smallest possible contacts areas, made with AFM probes directly on the oxide surface, which (presumably) avoid the defects entirely, show high resistance ratio AND stability of the switching phenomena. Thus, it is concluded that these defects contribute the migration of oxygen vacancies in a way that undermines resistive switching, possibly by circumventing the kinetic barrier to motion needed for switch stability. Carnegie Mellon University SRC Contact: Kwok Ng (Kwok.Ng@src.org) Research Highlight: Report on the Refined Schottky Barrier Model in T-CAD with Measured Material Parameters This report describes the development of a model of mobile dopant devices that includes non-linear oxygen vacancy mobility. This represents as an attempt to introduce a physically realistic kinetic barrier into our understanding of the vacancy motion. The researchers have chosen to focus on this aspect of the motion rather than on interface states (as originally planned) because they have come to believe that the non-linear mobility is the most critical feature with which must supplement a standard drift diffusion model to reproduce switching. While non-linear mobility has been implemented as discussed in this report, we are still in the middle of implementing concentration dependent diffusivity. This report discusses why this aspect is also needed for a complete model. Carnegie Mellon University SRC Contact: Kwok Ng (Kwok.Ng@src.org)

Integrated Circuits & Systems Sciences
Technical Thrust: Circuit Design
Research Highlight: Power-Frequency Locus of 65nm RF Power CMOS This report presents measurements of the power-frequency locus for 65nm RF power CMOS devices. The researchers found that output power scales linearly with width for device widths smaller than 200um but starts to saturate for wider devices. This effect is exacerbated at higher frequencies, resulting in a decrease in the peak output power and the corresponding power added efficiency with increasing frequency. The main reason for the power saturation is the presence of non-scalable parasitic resistances in the wide devices. Mass. Institute of Technology SRC Contact: David C. Yeh (david.yeh@src.org) Research Highlight: Report on BER Performance of Advanced ECC Based I/O Links Modern state-of-the-art I/O links today rely exclusively upon a high SNR channel and an equalizationbased inner transceiver to achieve a BER of 1e-15. Recently, the researchers have proposed forward error-correction (FEC) coding to improve the BER and reduce power in high-speed I/O links. FEC relaxes the BER performance specification for the inner transceiver components, thereby enabling the design of low-power circuit components. The team explores this theme further by investigating the design of errorresilient components at the circuit level, i. e. , the design of low-power, non-ideal components supported by an error-resiliency mechanism in order to better optimize link power consumption. This report examines the performance vs. power trade-off for a latch circuit - a key building block for several

transceiver components especially the ADC, and develop a Markov chain model to capture memory errors due to sampler bandwidth limitations. Univ. of Illinois/Urbana-Champaign SRC Contact: David C. Yeh (david.yeh@src.org) Research Highlight: Report on Innovation of Circuit Techniques and Architectures Appropriate for Deep Submicron CMOS ADCs This report describes two different approaches in low-voltage deep submicron CMOS processes. First, the extended dynamic range delta-sigma modulator developed by Nima Maghari describes a new topology which can process input signal beyond full-scale, hence extending the dynamic range of the modulator. Next, Tawfiq Musah presents a new and improved correlated-level-shifting structure to enhance the effective loop gain of an amplifier. Both of the techniques discussed in this report are suitable for lowvoltage applications where limited signal swing and intrinsic gain reduction of the transistors are the limiting factors of the overall performance. Oregon State University SRC Contact: David C. Yeh (david.yeh@src.org) Research Highlight: Report on the Development of New I/O Architectures to Implement the Proposed MIMO Algorithm The suggested report includes a new receive-end staggered I/O far-end crosstalk cancellation algorithm for wire line application. This algorithm changes FEXT induced jitter into voltage domain amplitude noise using staggered delays and cancels this voltage domain error using an analog differentiatior. A fitted channel model for a 12" single-ended transmission line on a FR4 board is used to simulate the algorithms operating at a data rate of 5 Gb/s. The simulation results prove that the proposed system architecture can significantly reduce FEXT induced jitter and successfully compensate voltage domain eye closure due to the staggered delay. Univ. of Minnesota SRC Contact: David C. Yeh (david.yeh@src.org) Research Highlight: Report on ESD-Resilient Circuits for Internal I/O Power domain crossing circuits, also known as internal I/Os, are susceptible to gate oxide damage during CDM events. Circuit-level simulations of internal I/O circuits along with elements representing the package, ESD circuits and the substrate, elucidate the roles of the package, power clamp placement, backto-back diode placement and the decoupling capacitors in determining the amount of stress at the internal I/O circuits. This deliverable report presents an internal I/O model that can be used for CDM simulations. It also recommends design guidelines for preventing CDM failures in the internal I/O circuits. Univ. of Illinois/Urbana-Champaign SRC Contact: David C. Yeh (david.yeh@src.org) Research Highlight: Design Techniques for Wide-Operating Range, Low-Jitter, Low-Power Digital Phase-Locked Loops This report presents several novel design techniques for the design of low-power wide-operating range low-jitter phase locked loops for clock generation and data recovery. The digital PLL combines a pulsewidth modulated proportional path with a digital integral path to circumvent many of the drawbacks of analog PLLs. Adaptive bandwidth tracking techniques are employed to achieve wide-operating range with minimal jitter degradation. Designed in a digital 90nm CMOS process, the prototype DPLL achieves better than 0.7 ps r. m. s random jitter, less than 3.5ps peak-to-peak deterministic jitter while consuming

less than 1mW at 2.5GHz (in simulation). The operating range of the PLL is 0.5GHz-to-3GHz. A novel clock data recovery (CDR) circuit architecture that has excellent supply-noise immunity and built-in-selftest for jitter tolerance measurement is presented. The transistor-level simulations of the prototype CDR designed in a digital CMOS process indicate that the circuit can operate at 5 Gbps data rate with less than 5mW power consumption. Oregon State University SRC Contact: David C. Yeh (david.yeh@src.org) Research Highlight: Integration of Advanced Drain Modulators with Optimized RF Stages This report describes the design and measurement of advanced drain modulation base-station power amplifiers and of their critical subcircuits. Drain modulator circuits capable of high voltage operation (up to 50V) were analyzed and demonstrated experimentally. Overall drain efficiency of 50% was obtained with Freescale LDMOS transistors, using drain modulators with 28V operation and with more recent 50V operation. Our experimental high voltage modulator did not achieve the target bandwidth of 45MHz, but we show by simulation how this bandwidth can be attained. RF design for further increasing efficiency with Freescale HV8 transistors is also described. Univ. of California/San Diego SRC Contact: David C. Yeh (david.yeh@src.org)

Technical Thrust: Integrated System Design
Research Highlight: Outstanding Research Problems in NoC Design: System, Microarchitecture and Circuit Perspectives To alleviate the complex communication problems that arise as the number of on-chip components increases, network-on-chip (NoC) architectures have been recently proposed to replace global interconnects. This paper first provides a general description of NoC architectures and applications. Then, it enumerates several related research problems organized under five main categories: Application characterization, communication paradigm, communication infrastructure, analysis, and solution evaluation. Motivation, problem description, proposed approaches, and open issues are discussed for each problem from system, microarchitecture, and circuit perspectives. Finally, the authors address the interactions among these research problems and put the NoC design process into perspective. Carnegie Mellon University SRC Contact: David C. Yeh (david.yeh@src.org) Research Highlight: Higher Radix Squaring Operatings Employing Dual Operand Recoding The research team introduces a novel left-to-right leading digit first dual operand recoding of an operand for the purpose of designing the squaring operation on that operand. The dual recoding yields an array of non-negative partial squares of size essentially one half that of a comparable multiplier for both radix-4 and radix-8 designs. For radix-8 design the 128 bit square of a 64 bit operand can be obtained from a consolidated partial square array of just 11 rows. The researchers describe advantages of the left-to-right recoding compared to a previous right-to-left Booth-folding encoding applicable to radix-4. The team also shows further simplifications available to the designs of a rounded floating point square operation and to the efficient design of a low precision approximate square operation. The methods are all illustrated by application to a 16-bit normalized operand. Southern Methodist University SRC Contact: David C. Yeh (david.yeh@src.org)

Research Highlight: Design and Management of Voltage-Frequency Island Partitioned Networkson-Chip The design of many core Systems-on-Chip (SoCs) has become increasingly challenging due to high levels of integration, excessive energy consumption and clock distribution problems. To deal with these issues, the authors consider Network-on-Chip (NoC) architectures partitioned into several voltage-frequency islands (VFIs) and propose a design methodology for run-time energy management. The proposed approach minimizes the energy consumption subject to performance constraints. Then, we present efficient techniques for on-the-fly workload monitoring and management to ensure that the system can cope with variability in the workload and various technology-related parameters. Simulation results demonstrate the effectiveness of the approach in reducing the overall system energy consumption for a real video application. Finally, the results and functional correctness are validated using an FPGA prototype for an NoC with multiple VFIs. Carnegie Mellon University SRC Contact: David C. Yeh (david.yeh@src.org) Research Highlight: Generation of ISA-Independent Synthetic Benchmarks This report describes the progress on the benchmark synthesis experiments for multiple ISAs from a common synthetic benchmark. Benchmark profiling technique and metrics which are used for generating synthetic clone and algorithm to generating a synthetic clone is described. Experience in benchmark cloning by using LLVM compiler infrastructure is described and the performance of synthesized clone is compared. This framework will deliver the baseline synthetic benchmark across the different platforms in their early design stage. Univ. of Texas/Austin SRC Contact: David C. Yeh (david.yeh@src.org)

Interconnect and Packaging Sciences
Technical Thrust: Back End Processes
Research Highlight: Determination of the Mechanisms Responsible for Leakage and Time Dependent Dielectric Breakdown (TDDB) in Low-k Dielectrics Work is continuing to understand and quantify traps in low-k dielectric (LKD) films, and the influence of these defects on leakage, time dependent dielectric breakdown (TDDB) and reliability. The researchers report on recent results using photo excitation to increase carrier concentration at low voltages leading to early breakdown, opening the possibility of accelerated testing. In addition, the team has extended earlier work indicating that bias stressing can also cause a barrier decrease well before breakdown occurs. Preliminary estimates indicate that the leakage current can increase by a factor of 100 with the decrease in barrier observed, assuming a Schottky or tunnel-like conduction mechanism. While some scatter in the data is expected, such results should be useful for establishing (and differentiating between) models of leakage, TDDB, and accelerated testing. In addition, the authors show some initial second harmonic generation (SHG) (contactless) results demonstrating a sufficiently high trap density to permit trap to trap conduction through the insulator. Columbia University SRC Contact: R. Scott List (Scott.List@src.org)

Research Highlight: Report on the Study of Thermo-mechanical Instability of Porous Low-k Dielectrics: Impact on Electrical and Mechanical Reliability of Interconnects and Possible Route to Air-Gap This report summarizes the results of our first phase research that aims to find the factors affecting the mechanical and electrical stability of porous low-k dielectrics and their impact on the reliability of porous low-k/Cu interconnects. The specific aims of our research were 1) to understand the influence of thermal stress on the stability of pores in low-k and Ta barrier; 2) to find influence of barrier failure on reliability of porous low-k dielectrics; 3) to determine the presence/absence of impurities in low-k and their impact on current conduction mechanism. Our research reveals that 1) pores become unstable under thermal stress and undergo reconfiguration; 2) thermal stress triggers barrier failure; 3) the injection of Cu ions into low-k takes place under electrical bias, resulting in a unique current signature that can be used in detecting the presence of barrier defects; 4) impurity atoms migrate to and are trapped at barrier/low-k interface and affect the electron conduction mechanism. We believe that all these findings are of significant engineering importance in implementing porous low-k technologies as they suggest that 1) thermal stress management is of upmost importance in order to improve barrier reliability, 2) measurement of leakage current as a function of time may enable detection of barrier failure and 3) process development is necessary to limit the impurity trapping that impacts low-k/barrier interface quality. Univ. of Texas/Arlington SRC Contact: R. Scott List (Scott.List@src.org) Research Highlight: Report on Simulations of the Reliability of Multi-segment Interconnect Trees A technique for simulation of electromigration-induced atom diffusion and stress evolution in a confined metal interconnect was developed. It was shown that high-order implicit time integration methods result in stable simulations and much shorter simulation times than the low-order explicit schemes used in earlier work. A simulation tool was constructed to allow investigation of the conditions leading to void nucleation and growth in single interconnect segments and complex multi-segment interconnect trees. This tool allows mechanistic analyses of accelerated test results, as well as extension of these analyses to the much longer times expected under service conditions. Mass. Institute of Technology SRC Contact: R. Scott List (Scott.List@src.org) Research Highlight: Final Report: Circuit-Level Reliability and Conductivity Optimization A simulation tool for analysis of electromigration in multi-segment interconnects trees was developed and used to analyze failures in two-segment trees and compared with experimental results. It was shown the location and asymmetry of voids play important roles in determining the lifetime of interconnect trees. Future work would have focused testing of new layout concepts for improved reliability. Techniques that lead to grain growth and true bamboo structures in damascene copper were developed. However, these techniques also led to formation of thermal grooves which caused surface scattering so that only modest resistance improvements were observed (and resistances also sometimes increased). Mass. Institute of Technology SRC Contact: R. Scott List (Scott.List@src.org) Research Highlight: Final Report: Circuit-Level Reliability and Conductivity Optimization Experimental studies of electromigration-induced void and extrusion failures in Cu/SiO(2) and Cu/low-k interconnect trees were carried out. The results from these studies were the basis for development of simulations and analytic modeling from which emerged computationally compact models that were incorporated into circuit-level and material-property-dependent analyses of interconnect reliability. These

models, simulations, and tools allow more accurate reliability assessments, extrapolation of the impact of evolution and changes in interconnect technology, and development of layout strategies for improved interconnect reliability. Mass. Institute of Technology SRC Contact: R. Scott List (Scott.List@src.org) Research Highlight: Tailoring NiSi Surface Chemistry for WNx ALD: Oxidation, Precleaning, and Precursor Interactions Ni(Pt)Si oxide overlayers must be reduced prior to metallization to achieve good adhesion/contact resistance. Reduction must occur at moderate temperature to avoid Ni diffusion. The researchers have shown that atomic O/plasma oxidation of NiSi or Ni(Pt)Si results in kinetically-controlled oxidation of Si and transition metal(s) without passivation and regardless of substrate doping. Results show that atomic H exposure results in reduction of the metallic portion of the oxide/silicate overlayer at 300 K. However, no reduction of the SiO(2) overlayer is observed below ~ 700 K. The reasons can be understood in terms of the thermodynamics of silica reduction. Treatments involving NFx radicals and H/NH(3) are planned. Univ. of North Texas SRC Contact: R. Scott List (Scott.List@src.org) Research Highlight: Vacuum Ultraviolet (VUV) Photon and Atomic Oxygen (O) Free Radical Effects on the Surface Chemistry and Topography of Ultra Low-k Dielectric Materials Oxygen plasma-induced methyl abstraction from ultra low-k dielectrics is a serious problem during photoresist stripping, and the mechanism is not understood. Ex situ FTIR studies of O(2) plasma damage in SiCOH materials with varied k value, porosity and diffusivity, indicate that CH(3) abstraction is governed by a diffusion-dominated mechanism, with diffusion through interconnected nanopores. He plasma pretreatment prior to oxygen exposure also hinders methyl group abstraction. Plasma damage can therefore be limited either by limiting pore interconnectedness (controlled separately from total porosity and k value), or by He plasma pretreatment. Univ. of North Texas SRC Contact: R. Scott List (Scott.List@src.org) Research Highlight: Interfacial Organic Layers: Tailoring Nucleation on Dielectric Surfaces The goal of this project is to investigate the use of interfacial organic layers (IOLs) to tailor the nucleation characteristics of films grown by atomic layer deposition (ALD) on dielectric surfaces. The authors seek to develop IOLs that are self-limiting in their growth, and are capable of producing a density of nucleation sites at their surface that is independent of the underlying substrate, including substrates that are porous. Ideally, these organic layers will act as surface normalization coatings. Cornell University SRC Contact: R. Scott List (Scott.List@src.org)

Univ. of Illinois/Urbana-Champaign SRC Contact: R. Scott List (Scott.List@src.org) Research Highlight: Final Report: Equivalence Principle Algorithm for Microelectronic Structure Modeling This report documents the research accomplishments on the equivalence principle algorithm for solving multiscale problems arising from the electromagnetic modeling of circuit problems. Equivalence principle algorithm is essentially a domain decomposition scheme based on equivalence principle and integral equations. By introducing virtual equivalence surfaces to enclose the regions with fine features, lowfrequency physics is isolated from high-frequency physics. This results in a better conditioned matrix equation with smaller number of unknowns. This report summarizes the accomplishments on the equivalence principle algorithm, which include introduction of equivalence principle operators, modeling conducting current with tap basis scheme, improving the accuracy by using the high-order quadrature point sampling scheme, and acceleration of the equivalence principle algorithm using multilevel fast multipole algorithm. Numerical experiments are shown in a separate report on the benchmark data for comparison of various methods. Finally, future research directions are discussed. Univ. of Illinois/Urbana-Champaign SRC Contact: R. Scott List (Scott.List@src.org) Research Highlight: Report on the Benchmark Data for Comparison of Various Methods This report documents the numerical experiments that have been performed by equivalence principle algorithm (EPA). To verify the accuracy of EPA and demonstrate the effect of the facilities implemented in the EPA code, quite a few numerical experiments have been performed. Usually, the researchers benchmark the result with other codes in the group. They include analytical formula, the conventional electric field integral equation (EFIE) code, and the augmented EFIE code. Univ. of Illinois/Urbana-Champaign SRC Contact: R. Scott List (Scott.List@src.org) Research Highlight: Report on Joint Scale Dependence of Aging Kinetics in Sn-Ag-Cu Solders Sn-Ag-Cu (SAC) solders are susceptible to appreciable microstructural coarsening during storage or service, resulting in evolution of joint properties, and hence reliability, over time. Understanding that the coarsening kinetics are much faster in the small joints (335um diameter) attached to bond-pads with a Nibased surface finish(1), the coarsening behavior of the joints under four different conditions were compared: (i) as-reflowed (AR), (ii) isothermally aged (AG) at 125C for 96 hours, (iii) thermally cycled (TC) from -25C to 125C for 105 cycles (96 hours), and (iv) thermo-mechanical cycled (TMC) from 25C to 125C, resulting in the shear strain of 0. 1, for 105 cycles (96 hours). Microstructural analysis showed that faster coarsening rates can be attained by (i) increasing the aging temperature, and/or (ii) application of cyclic stress on the ball-joint samples. Also, particles in the interfacial region (a region within 40 um from the interface) coarsen at a faster rate than that in the central region (a region within 50 um from the centerline) at a selected aging condition. This is attributed to a local decrease in the Cu concentration at the interface due to the faster kinetics of the reaction of Cu with Ni (present in the bond pad) which enhances the dissolution of Ag into Sn. It is shown through microstructural analysis that majority of the particles in the examined samples were Ag(3)Sn, so the microstructural aging is determined primarily by the coarsening kinetics of Ag(3)Sn. Purdue University SRC Contact: R. Scott List (Scott.List@src.org)

Research Highlight: Report on the Dominant Diffusion Species of Thermomigration in Pb-free SnAgCu Solder Joints and the Determination of Heat of Transport The work was done by the force in a distance of atomic jump of 3 x 10(-10) m will be Delta w = 4.8 x 10(-27) Newton-meter = 4.8 x 10(-27) joule. This value is close to the thermal energy change we have calculated for thermomigration. Thus, if a current density of 10(4)A/cm(2) can induce electromigration in a solder joint, a temperature gradient of 1000 C/cm will induce thermomigration in a solder joint. Univ. of California/Los Angeles SRC Contact: R. Scott List (Scott.List@src.org)

Nonmanufacturing Sciences
Technical Thrust: Patterning
Research Highlight: Report on the Evaluation of Charging Behavior of Resists and Oxides as a Function of Helium Ion Energy and Dose Any insulating or poorly conducting specimen will acquire a fixed charge when irradiated by a high energy beam of charged particles. This leads to random variations in the signal levels generated, and distortions in the image. The charging behavior of a sample in a beam of helium ions differs from that in encountered under an electron beam of similar energy in several ways including the energy range over which charging occurs, the magnitude of the surface potentials produced, and the procedures which can be employed to minimize the resultant disturbance to the signals produced. Univ. of Tennessee/Knoxville SRC Contact: Daniel J. C. Herr (herr@src.org) Research Highlight: Report on the Measurement and Tabulation of the Ion Induced SE Yield, and the Yield of Rutherford Backscattered Ions, for a Range of Elements and Materials and for the He Ion Energies between 1-30keV This report contains experimental data on the yields of ion induced secondary electrons (iSE) and Rutherford Backscattered Ions (RBI) from twenty four elements as a result of irradiation by beams of Helium ions with energies in the keV range. Such data is essential for the development of models of ionsolid interactions, and is also an essential step towards being able to properly assess how the imaging and micro-analytical performance of the new Helium Beam Scanning Ion Microscope compares with that of the conventional scanning electron microscope. Univ. of Tennessee/Knoxville SRC Contact: Daniel J. C. Herr (herr@src.org) Research Highlight: Report on the Measurement and Performance of the ALIS ORION SIMincluding Resolution, Beam Current, Stability, Depth of Field, Signal to Noise Ratio The resolution and overall imaging performance of the Zeiss "ORION" helium ion beam scanning microscope has been evaluated using techniques developed as part of SRC project 2005-OJ-1281 and originally designed to test the electron beam tools used for critical dimension metrology and defect review. Other parameters of interest such as the magnitude and stability of the incident ion beam current have also been investigated. These results show that the ORION can ultimately be expected to offer significant advantages over conventional SEMs although some issues currently remain to be solved.

Univ. of Tennessee/Knoxville SRC Contact: Daniel J. C. Herr (herr@src.org) Research Highlight: First Stage Development of the IONiSE Monte Carlo Model A detailed Monte Carlo simulation program describing the transport and interactions of helium ions in a solid is being developed to support experimental studies on the ORION Helium ion scanning microscope. Univ. of Tennessee/Knoxville SRC Contact: Daniel J. C. Herr (herr@src.org) Research Highlight: Architectural Effects on Chemically Amplified Photoresists - Diffusion of Photoacid Generators in Star Resists Decreasing the diffusion distance of photoacid generators (PAG) is a critical challenge for extending chemical amplification to next generation lithography. The researchers have investigated the effect of polymer architecture on the diffusion of the photoacid. Bilayer films consisting of a star tert-butyl methacrylate (tBMA) homopolymer bottom film and a star tBMA homopolymer with 5% PAG as a top film were prepared. The progression of the reaction-diffusion front was measured by examining the change in film thickness after development for different post exposure bake (PEB) times. These results were compared with the progression of the reaction-diffusion front for a linear tBMA homopolymer. In both cases the reaction-diffusion front was found to progress proportionally to the square root of PEB time. The star architecture was found to significantly decrease the rate at which the reaction-diffusion front progressed. Cornell University SRC Contact: Daniel J. C. Herr (herr@src.org)