Title

Author

Date of Award

12-2015

Degree Name

Doctor of Philosophy

Department

Electrical and Computer Engineering

First Advisor

Dr. Bradley J. Bazuin

Second Advisor

Dr. Janos L. Grantner

Third Advisor

Dr. John Kapenga

Abstract

Wireless has become one of the most pervasive core technologies in the modern world. Demand for faster data rates, improved spectrum efficiency, higher system access capacity, seamless protocol integration, improved security and robustness under varying channel environments has led to the resurgence of programmable software defined radio (SDR) as an alternative to traditional ASIC based radios. Future SDR implementations will need support for multiple standards on platforms with multi-Gb/s connectivity, parallel processing and spectrum sensing capabilities. This dissertation implemented key technologies of importance in addressing these issues namely development of cost effective multi-mode reconfigurable SDR and providing a framework to map sequential wireless communication algorithms to the parallel domain.

Initially, a novel software defined radio platform using commercial off-the-shelf components was successfully developed. This hybrid platform consists of an USRP N210 device performing the role of an RF front end, an NVIDIA Quadro 600 GPU functioning as the parallel computing node, and a commodity PC with PCIe backplane as the high-speed interconnect. Validation of the architectural concepts was demonstrated through real-world applications on the GNURadio software. Performance analysis and benefits of the proposed architecture over other custom solutions was also demonstrated.

In the second project, we demonstrate an important application of GPU technology to SDR systems, namely the polyphase channelizer. The proposed channelizer architecture exploits block and thread level processing in the GPU and delivers high throughput, arbitrary resampling of multiple channels. These characteristics make it attractive for a variety of communication receiver algorithms.

Finally the third project will deal with critical high data rate dataflow between radio peripheral devices and parallel processing resources. Software routines for this project were written in C++ and are based on the UHD code from Ettus Research. In addition to enabling transfer of data, the software is also responsible for configuring the USRP devices. Analysis of performance metrics and dataflow bottlenecks, show the proposed architecture is capable of meeting the demanding requirements of current wireless standards.