We're already familiar with a few ways of loading numbers into the 6502's registers, and storing numbers from those registers into RAM or TIA registers. We'll re-visit those methods we know about, learn some new ones (not all of the 6502's addressing modes, but enough to get by with). This session we're going to have a bit of a look at the various ways that the 6502 can address memory, and how to write these in source code.

As you sould be aware by now, the 6502 has three registers - A, X and Y. "A" is our workhorse register, and we use this to do most of our loading, storing, and calculations. X and Y are index registers, and we generally use these for looping, and counting operations. They also allow us to access 'lists' or tables of data in memory.

Let's start with the basics. To load and store actual values to and from registers, we can use the following...

All registers can load numbers directly (called 'immediate values'). The above examples show the accumulator being loaded with #$80 (the number 128) and also the X register being loaded with the same value. You can do this with the Y register, too.

You can't STORE the accumulator to an immediate value. This is a meaningless concept. It's like me asking you to put a letter in your three. You may have a post-box numbered "three", but you don't have a "three".

All registers can load and store values to memory addresses by specifying the location of that address (or, of course, a label which equates to the location of that address). For example, the following two sections of code are equivalent...

As noted, the above will work for X and Y registers, too. This form of addressing (addressing means "how we access memory") is called 'absolute addressing'. Earlier we covered how the 6502 addresses code over a 16-bit memory range (that is, there are 2^16 distinct addresses that the 6502 can access, ranging from 0 to $FFFF). To form a 16-bit address, the 6502 uses pairs of bytes - and these are always stored in little-endian format (which means that we put the low-byte first, and the high-byte last). Thus, the address $F023 would be stored in memory as two bytes in this order... $23, $F0.

Now, when DASM is assembling our code, it converts the mnemonic we write for an instruction (eg: "lda") into an opcode (a number) which is the 6502's way of understanding what each instruction is meant to do. We already encountered the mnemonic "nop" which converted into $EA. Whenever the 6502 encountered an $EA as an instruction, it performed a 2-cycle delay - ie: it 'executed' the NOP.

We've briefly covered how each 6502 instruction may have one or two additional parameters - that is, there's always an opcode - but there may be one or two additional bytes following the opcode. These bytes hold things such as address data, or numeric data. For example, when we write "lda #$56", DASM will place the bytes $A9, $56 into the binary. The 6502 retrieves the $A9, recognises this as a "lda" instruction, then fetches the next byte $56 and transfers this value into the accumulator.

To signify absolute addresses, the two bytes of the address are placed in little-endian format following the opcode. If we write "ldy $F023" - indicating we wish to load the contents of memory location $F023 into the Y register, then DASM will put the bytes $AC, $23, $F0 into our binary. And the 6502 when executing will retrieve the $AC, recognise it as a "ldy" instruction which requires a two-byte address - and then fetches the address from the next two bytes, giving $F023 - and THEN retrieving the contents of that memory location and transfering it into the y register.

As you can see, this division of 16-bit addresses into low and high byte pairs essentially divides the memory map into 256 'pages' of 256 bytes each. The very first page (with the high-byte equal to 0) is known as 'zero-page', and this is treated a bit differently to the rest of memory. To optimise the space required for our binary, the 6502 designers decided that they would include a special version of memory addressing where, if the access was to zero page (and thus the high byte of the memory address is 0), then you could use a different opcode for the instruction and only include the low-byte of the address in the binary. This form of addressing is known as zero-page addressing.

As with our above example, if we were accessing memory location $80 (which is the same as $0080 - remember, leading zeroes are superfluous when writing numbers), then we *COULD* have an absolute access to this location (with the bytes $AC, $80, $00 - interpreted in a similar fashion as described above). But DASM is smart - and it knows that when we are accessing zero-page addresses, it uses the more efficient (both smaller code-size and faster execution) form of the instruction, and instead places the following in our binary... $A4, $80. The 6502 recognises the opcode $A4 as a "ldy" instruction (as was the $AC) but in this case only one byte is retrieved to form the low byte of the address, and the high byte is assumed to be 0.

Mostly we can rely on DASM to choose the best form of addressing for us.

So far, we have seen that what we can do with all the registers is essentially the same. Unfortunately, this is not the case with all the addressing modes! The 6502 is not 'orthagonal' - and this has some bearing on our choice of which register to use for which purpose, when designing our kernel.

OK, so now we should know what is meant by "absolute addresses" and "zero page addresses". Pretty simple, really. Both refer to the address of memory that the 6502 can theoretically access - and zero page addresses are those in the range $0000 to $00FF inclusive.

The session discussing Initialisation introduced an efficient way of clearing memory in a loop, using a register to iterate through 256 bytes, and storing 0 to the memory location formed by adding the contents of the x register to a fixed memory address. These addressing modes (using the X or Y register to add to a fixed memory address, giving a final address for access) are known as "Absolute,X" and "Absolute,Y" and "Zero Page,X" and "Zero Page,Y". It is probably a good idea now to track down a good 6502 book

That last line is interesting - an example of the non-orthogonality of our instruction set. All of the above examples deal with zero-page addresses (that is, the high byte of the address is 0). Theoretically, these instructions don't need to include the high-byte in the address parameters in the binary. However, there is no "zero page,y" load for the accumulator! There is a zero page,x one, though. Its a bit bizarre

So DASM will assemble "ldx $23,y" to a zero page,y instruction - 2 bytes long - but it will assemble "lda $23,y" to an absolute,y instruction - 3 bytes long. Such is life.

These zero page indexed instructions have a catch - the final address is always always always a zero page address. So in the following example...

ldy #1
lda $FF,y

Since (as we just discussed) this is an absolute indexed instruction, the accumulator is loaded with the contets of memory location $100. However, the following...

ldy #1
ldx $FF,y

Since this will assemble to a zero page indexed instruction, the final address is always zero-page (the high byte is set to 0 after the index register is added) - so we will actually be accessing the contents of memory location 0 (!!). That is, the address is formed by adding the y register and the address ($FF+1 = $100) and dropping the high-byte. Something to be very aware of!

Absolute indexed addressing modes are handy for loading values from data tables in ROM. They allow us to use an index register to step (for example) the line number in a kernel, and use the same register to access playfield values from tables. Consider this (mockup) code...

The above code fragment uses tables of data in our ROM. These tables contain the values which should be written to the playfield registers for each scanline. The x register increments once for each scanline, and our absolute,x load for each playfield register will load consecutive values from the appropriate tables.

Then, creating pretty graphics becomes simply a matter of putting the right values into those tables MyPF0, MyPF1, and MyPF2. This is where building tools to convert from images to data tables becomes extremely useful! We'll cover more of this way of doing things when we complete our sessions on asymmetrical playfields. The plan is to use a tool to create these data tables, and simplify our kernel by using data tables to display just about any asymmetrical image we want!

1. Use this method of absolute,x table access to modify or create a kernel which loads the graphics data from tables. Separate each playfield register into its own table, as above.

2. Can you extend this system to asymmetrical playfield? Don't worry, we're going to give a complete asymmetrical playfield kernel (and tools!) in the next session.

3. How would you incorporate colour changes into this system (ie: if you wanted clouds on the left, sun on the right)?

4. Each table requires 1 byte of ROM per PF register per scanline. Can you think of ways to reduce this requirement? What trade-offs are necessary when reducing the table size?

5. Find a 6502 cycle-timing reference, and try to calculate exactly how many cycles each instruction in your kernel is taking. Add-up all the instructions on each line, and work out just how much time you have left to do "all the other stuff". Such as sprite drawing!

Correct. This is why it is supremo important to ensure that any lookup tables used in timing sensitive code (kernel) don't require calculations which cross page boundaries.

For most 6502 instructions you can figure out the number of cycles required by counting memory accesses and remembering a couple of other rules: 2 cycle minimum, +1 for crossing a page boundary, +1 for branch taken. (There are exceptions of course...)

ldy #1 = 1 cycle to fetch the opcode + 1 cycle to fetch the immediate valuelda $00FF,y = 1 cycle to fetch the opcode + 2 cycles for the address + 1 cycle for the carry + 1 cycle to get the value from memory

That last line is interesting - an example of the non-orthogonality of our instruction set. All of the above examples deal with zero-page addresses (that is, the high byte of the address is 0). Theoretically, these instructions don't need to include the high-byte in the address parameters in the binary. However, there is no "zero page,y" load for the accumulator! There is a zero page,x one, though. Its a bit bizarre

I know everyone's heard me piss and moan about this on Stella List, but I don't think I've mentioned it since you took over maintenance of DASM so I'm going to mention it here:

lda $80,y

Should throw up an "Illegal Addressing Mode" error.

It should do this because:

A) It actually IS an error. There's no such thing as lda $80,y

B) The assembler shouldn't be trying to read our mind and ASSUME we mean lda $0080,y - there are certainly plenty of other errors where the assembler could try to guess what we really mean. This is the only one. Why?

C) It's very likely that this represents some other error that's going to be a bitch to debug if DASM doesn't flag it: If either it was supposed to be lda $80,x or lda $FF80,y it may not be obvious to spot.

D) This is a very common error for programmers making the transition from other CPUs (ie: 6809) which actually do have valid lda $80,y (I know I did it all the time at first)

I agree, but this should be either an option or only produce a warning. Else most old existing code wouldn't compile anymore.

I'd settle for a warning but I think a command line switch to turn "optimisation" on and off would be the best way to go. Have it default off and then assembling any old code would simply involve turning it on. (If it defaults to on we're back to square one since you have to be aware the assembler is going to try to optimise your code in order to turn off optimisation. If you're already aware of this behaviour you're already going to be making allowances for it anyway. So you don't really need the on/off switch.)

IMHO something like lda $0080 should be handled the same way. Either throw up a warning, or, assemble it corectly (Absolute, not Zero Page) unless the "optimisation" switch is on. In general I want an assembler to assemble exactly as written and not try to guess what I mean. And in particular if someone is doing something like lda $0080 on the 2600 it's probably for timing in the Kernal and they're expecting that extra cycle. Yes, I know about .w but you shouldn't have to hunt down some obscure syntax in order to get the assembler to behave properly.

Sure in both these cases the first time the assembler bites you on the ass by not behaving correctly is going to be the last. You're going to remember that 3 hour debug and never make that same "mistake" again. So the only people really affected are n00b's. Do you really want to saddle n00b's with an idiosyncratic assembler?

Anyway, I didn't mean to turn this into a big assembler design debate in the middle on Andrew's excellent lessons. Please, carry on...

NumberFinal and NumberInput represent the same value but different variable types which is basically what you're doing above. Or maybe it's closer to a local/variable relationship. Okay, neither is exactly the same situtation. but the fact that we can have this conversation indicates that there is a potential problem here and it should at least throw up a warning.

I'd suggest that an error or warning be generated but that an explicit override should be available, for example:

TMP EQU $80

LDA TMP,X LDA.w TMP,Y

Would be perfectly valid. The .w essentially says, "Yes, I meant to do that" while any actual ambiguity should at least generate a warning.

That last line is interesting - an example of the non-orthogonality of our instruction set. All of the above examples deal with zero-page addresses (that is, the high byte of the address is 0). Theoretically, these instructions don't need to include the high-byte in the address parameters in the binary. However, there is no "zero page,y" load for the accumulator! There is a zero page,x one, though. Its a bit bizarre

So DASM will assemble "ldx $23,y" to a zero page,y instruction - 2 bytes long - but it will assemble "lda $23,y" to an absolute,y instruction - 3 bytes long. Such is life.

Wow! This is great stuff. Let me see if I get the straight.

Example 1After the first lda instruction, A will hold the value contained at address $00 andafter the second lda instruction, A will hold the value contained at address $0100. Is that correct?

Nope, but JMP ($FCFF) would exhibit this glitch when crossing pages...the address gathered would be from $FCFF and $FC00.

* see MLFB page 85,86

I suppose that would only become an issue if you were using extended ram mapped in the rom area? But if that's the case, you could just use the native ram to avoid it (Hack'Em uses 3 sets of indirect jumps).

Heh...you are way ahead of me (shows how long it takes me to plunk out a post).

Neither example would be much for a beginner 2600 programmer to worry about, since you can't alter addresses reserved for rom (except in the case of extended ram), and you can't alter address $100 to even attempt to make LDA($FF),Y work