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HyperRAM Memory Controller

The new HyperRAM memories, based on low-power PSRAM technology, are a very welcome addition to the traditional RAM memories portfolio : they have been optimized for Mobile and Automotive applications.

They provide good Bandwidth performance

The interface, known as “HyperBus”, offers a low signal count (Address, Command and Data using only eight DQ pins)

They offer Low Power consumptionTypical power consumption during burst read is about 60 mA only.

User-friendly protocol, with Hidden Refresh mode, for example

Most devices are available for Automotive Temperature range…

ALSE has designed a very-low resource usage HyperBus Memory Controller, in order to provide an easy interface to the HyperRAM memories, along with high performance (up to 333 MBytes/s, which is x1.5 times faster than a 16 bits PSRAM running @ 108MHz).

Main Technical Features

Memory Operating Frequency typically up to 166 MHz, depending on FPGA and Memory speed grades, and (more marginally) on the customer PCB. This delivers a bandwidth up to 333 MBytes/s, with only 12 x IO pins (CS, Clk/Clk_n, DQS, DQ[7:0])

16 bits Slave Data Interface with Burst support.

_ Typically, the Controller will serve a Master that can be an Altera Nios IICPU, with or without caches, with or without Burst mode. A hardware master (DMA) is of course also possible (e.g : Video streaming DMAs, etc…)