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Storing data in three dimensions with racetrack memory

New work from IBM's Almaden Research Lab published in this week's edition of …

Work from researchers at IBMs Almaden Research Laboratory suggests that a new type of computer memory storage may be on the horizon. Currently, computer memory comes in one of two flavors: solid state RAM or magnetic hard disk drives, both of which rely on what's effectively two-dimensional storage. The new method adds some useful features to memory storage by extending the physical storage into the third dimension.

Over the past few years, an IBM research team, led by Stuart S. P. Parkin, has been developing a new method for storing information. Called racetrack memory (RM), it relies on U-shaped nanowires that are arranged perpendicular to the surface of a chip and act as a shift register. Bits can be read or written at the base of the wire. Once on the wire, bits can then be moved around as if they're on a memory stack thanks to nanosecond pulses of current applied to the ends of the U that shift all the bits to new locations on the wire.

A pair of articles from the Almaden group that describe RM appear in this week's edition of Science, the first describing the technology in depth, and the second reporting the construction of a simplified working device. The review article1 lays out the basics of racetrack memory. The smallest unit of RM is a U-shaped nanowire, with data stored in magnetic domain walls (DWs) arrayed along its length. A collection of these nanowires can be built onto a single chip, producing a memory density greater than anything solid state memory can currently handle. According to the researchers, even a two-dimensional RM setup would have a memory density higher than nearly all current solid state offerings.

Cartoon schematic of a single racetrack wire
Image credit: IBM Almaden Research Labs

DW-based bits are accessed using current pulses that exploit the phenomenon of spin-momentum transfer. The current shifts the entire set of bits along the wire, exposing a different DW to the reader and/or writer at the base. The system has some very appealing properties. The cost of storing a single bit is actually reduced as the number of DWs per racetrack increases. The average time needed to read a given bit is also independent of the number of DWs per racetrack—essentially, there's a "the more the merrier" situation when it comes to data density.Thanks to the fact that there are no moving parts, there is also no obvious fatigue or wearout mechanism for RM.

If RM devices pan out, they could potentially offer the low cost of HDD technology with the performance and reliability of solid-state devices. Because of these properties, interest in DW devices has fluctuated over the years. They were first proposed in the 1970s, and there was a flurry of research in the late seventies and early eighties on "magnetic bubble materials." That work never panned out due to technological hurdles that could not be overcome at the time. The accompanying research paper2 suggest those hurdles might be a thing of the past, as it describes the successful creation of a two-dimensional racetrack memory nanowire device.

The device is a single nanowire laid flat on a substrate, with read/write heads in the center of the wire and the current pulse generators that move the bits around on the ends of the wire. The wire is made of permalloy (Ni81Fe19), measured 200 nm in diameter, and extended six microns between the electrical contacts at each end. Sending 1.6V pulses across the wire produced a current density of nearly 2x108 A/cm2.

The setup functioned as a DW shift register memory device, the equivalent of a three-bit unidirectional serial-in, serial-out memory setup. The researchers were able to encode a series of information one bit at a time, shifting the memory down and then reading the data back out. The time needed to encode and shift one bit to was approximately 30ns and the authors suggest that the average access time for RM will be between 10 and 50ns. This compares reasonably well to the 5ms typical of HDD-based technology, and around 10ns for advanced solid state devices.

The researchers conclude their article by stating, "the motion of a series of DWs at high speed using nanosecond current pulses not only proves the viability of a shift-register memory but also presages the possibility of current-controlled DW–based logic devices." There is still work to do before an entire three-dimensional memory chip will replace your current memory solutions. The biggest problem may be heat; moving DWs requires a high current, which may destroy the wire or mangle the data it contains. Still, there are some ideas on how to deal with the heat, and this work represents a big step in the direction of a new dimension in memory storage.

Matt Ford
Matt is a contributing writer at Ars Technica, focusing on physics, astronomy, chemistry, mathematics, and engineering. When he's not writing, he works on realtime models of large-scale engineering systems. Emailzeotherm@gmail.com//Twitter@zeotherm