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Dynamical Heat Transfer Analysis on 3D-TSV Devices

Keywords: 3D TSV Device, Transient Thermal Analysis, Optimized Layout

The market demand for 3D devices using TSV (Through-Si-Via) technology is increasing rapidly. But the heat rise in the 3D-TSV device structure is of concern since many devices, each acting as potential "heat sources", are stacked together.
In this paper we investigate dynamical heat transfer of 3D-TSV devices for both steady- and transient-thermal state analyses using the conventional DRAM model. We create a heat analysis model, in which 8 DRAM layers with TSV are stacked and connected to each other with bumps. This device is packed in resin materials with low thermal conductivities such as adhesive and package molding, and the package is placed in a certain atmosphere for the evaluation of natural or forced heat convection. With this meticulous model, we clarify the heat transfer in the 3D-TSV DRAM for the first time using transient thermal analysis, with this result being a very crucial indicator towards detailed understanding and finding effective ways to optimize the thermal characteristics.
The representative results show the junction temperature is suppressed sufficiently below 95C by applying appropriate cooling on the package face with very small deviation in the package, if the heat source is 3D-DRAM at 0.2Watt only. For a logic LSI (5-10Watt), however, mounted to 3D DRAM device, the maximum temperature and the temperature difference in the device rise drastically. This could be caused not only by insufficient heat radiation, but also by heat resistance of adhesive and package molding. In order to avoid the heat rise problem in 3D-TSV DRAM, it is very important to optimize the layout of SiP elements such as logic LSI, DRAM, interposer, heat sink and we propose the best and optimized layout.
In summary, the understanding of the characteristic of heat behavior in 3D-TSV devices helps to clarify the specifications required and appropriate device structure.