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Asymmetric Gates Asymmetric gates favor one input over another Ex: suppose input A of a NAND gate is most critical Use smaller transistor on A (less capacitance) Boost size of noncritical input So total resistance is same g A = g B = g total = g A + g B = Asymmetric gate approaches g = 1 on critical input But total logical effort goes up

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Asymmetric Gates Asymmetric gates favor one input over another Ex: suppose input A of a NAND gate is most critical Use smaller transistor on A (less capacitance) Boost size of noncritical input So total resistance is same g A = 10/9 g B = 2 g total = g A + g B = 28/9 Asymmetric gate approaches g = 1 on critical input But total logical effort goes up

28
HI- and LO-Skew Def: Logical effort of a skewed gate for a particular transition is the ratio of the input capacitance of that gate to the input capacitance of an unskewed inverter delivering the same output current for the same transition. Skewed gates reduce size of noncritical transistors HI-skew gates favor rising output (small nMOS) LO-skew gates favor falling output (small pMOS) Logical effort is smaller for favored direction But larger for the other direction