Overlapping the execution of CPU operations permits a number of
operations to execute during each computer cycle, rather than
issuing a single operation and waiting for it to complete before
issuing the next. Virtually every RISC development project has
now turned its attention to this topic. Conventional computer
architectures use hardware at run-time to decide which operations
to perform each cycle. Far more speedup is available when the
compiler decides in advance. The speaker will describe Trace
Scheduling, which allows Very Long Instruction Word (VLIW) RISC
machines to overlap dozens of simultaneous operations. Despite
having instruction words over 1,000 bits long, they are used as
normal computers and yield the fastest uniprocessors by far for
any fixed circuit speed. These systems take full advantage of
nonvectorized code, do vector operations faster than a vector
machine, and can serve as optimal nodes for larger
multiprocessors.

Josh Fisher originated the concepts of Trace Scheduling compacting
compilers, and pioneered VLIW architectures for high-performance
computing. He has taught at the Courant Institute and Yale, and
founded Multiflow in 1984.

Open to the public. Refreshments will be served at 3:40 PM.
For information about the seminar or directions to the Center,
contact <SCIENCE@JVNCD.BITNET> or call 609/520-2000.
Reservations are not needed.
[Josh is an interesting guy, worth listening to if you're in the area. -John]
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