CeRAM Memory Gets ARM's Attention

A new approach aims to be a contender for next-generation memory. Here's how it works.

At present (and in the recent past), many types of memory devices and materials have been advanced in the quest to provide a nonvolatile memory that will scale lithographically and eventually outperform and replace flash memory (today's silicon-based NV memory workhorse) and unify the rest of the semiconductor memory device spectrum.

New to the scene is correlated electron random access memory (CeRAM). Proponents say it offers a number of attractive characteristics: thin film, fast bulk switching, no need for forming, stability over a wide temperature range, low-power and low-voltage operation, and scalability. All these would appear to make it a worthy candidate as a next-generation memory. CeRAM is the product of work by a team at the University of Colorado, Colorado Springs, under the direction of Dr. Carlos Paz de Araujo. They are responsible for the material research and development of this new type of memory, and they have verified its principles of operation and feasibility.

In 1986, Paz de Araujo and Dr. Larry D. McMillan founded the privately held Symetrix Corp. to conduct advanced research and development in the global semiconductor chip industry. Symetrix recently announced that CeRAM has clearly attracted the attention of ARM and a number of other important companies. On Feb. 4, Symetrix announced:

ARM is evaluating CeRAM technology as part of its strategy in embedded nonvolatile memory offerings and their discussions with Symetrix started over three months ago. Symetrix will provide its technology and the results from Symetrix programs ongoing at the University of Texas (Dallas) and the University of Colorado (Colorado Springs) to chip foundries engaged by ARM. Other chip companies are also working with Symetrix under similar terms.

What is CeRAM?
CeRAM is based on a transition metal oxide, in this case nickel oxide (NiO). The premise is that, by cleaning up NiO through a suitable doping technique, it is possible to obtain electrically conducting NiO that can make very rapid, reversible, nonvolatile bulk transitions between its electrically insulating and conducting states. In the past, these transitions were possible only at a high pressure and temperature, but they now can be achieved at room temperature with low switching voltages and currents. Key to the operation is a reversible metal-to-insulator transition (MIT) that has its roots in the work of Sir Nevill Mott and John Hubbard.

Interpreting the mechanism responsible for the observed electrical memory characteristics requires casting off many of the fundamentals that underpin the silicon-based solid state electronics industry. In the name of the new memory, "correlated" is the single word that describes the difference between this new type of solid state electronics and conventional single-crystal silicon-based electronics. In the latter, electrons are considered uncorrelated. (In simple terms, the difference is about the interaction of electrons with one another, which requires casting off the reliance on carrier transport considerations based on structural periodicity.) Proponents of the new memory say that, though an understanding of conventional electronics relies on a rigid density of states, meaning the act of doping does not affect the density of states of the solvent (i.e., silicon in today's electronics), for the CeRAM, the density of states is not rigid. Instead, its manipulation is key to the two resistance states that are the basis of this new approach.

One unique feature of CeRAM operation is its single-site oxidation and reduction (meaning the loss and gain of an electron). For the active material of the CeRAM, the oxidation and reduction occurs at the same nickel-ion site by means of quantum tunneling effects. From that point forward, the explanation of what is happening gets extremely complex and relies on effects that will not be familiar ground to those used to dealing with single-crystal electronics.

CeRAM: A two-terminal view
It will be essential for potential users of the CeRAM memory to understand the electrical characteristics, specifically current as a function of voltage. See the I-V curve illustrated in Figure 1.

Figure 1

An I-V curve showing electrical characteristics for CeRAM memory.

Here's an example of a CeRAM reset/set cycle. Starting with the device in its as-born conducting state, the initial part of the green set-state characteristics is marked in blue to indicate a voltage excursion that would represent a typical read access. If the voltage is increased following the green curve, at about 0.8 V, the characteristic makes a rapid transition to a high-resistance insulating state.

In the insulating state (the red curve in Figure 1), from the transition voltage (0.8 V) the current can be reduced toward zero and read cycles can be carried out (indicated by the blue overlay between 0 V and 0.2 V in Figure 1), or the voltage can be increased along the red part of the characteristic. In that direction, at about 1.6 V, the current starts to show a much greater increase with increasing voltage to a value where a rapid transition back to the conducting state occurs.

To avoid high levels of damaging current, it is necessary to limit the current to a compliance level (icomp). In the metallic state, the rapid fall in resistance causes the voltage across the device to fall to a value determined by icomp and the metallic state resistance. When the SET pulse is terminated, the voltage across the device will drop to zero, and the device will be in its SET state.

It is worth noting that access along the green curve for another reset cycle is possible only after the voltage across the device has returned to zero (to allow the transient electrons in a non-equilibrium situation to relax). In normal operation, this will occur because switching the device between its set and reset states will use pulses. Proponents say this return-to-reset requirement does not impose latency on the minimum SET and RESET time (due to the speed of phase transition).

Figure 2 shows actual CeRAM switching characteristic for real devices taken from the recently published thesis of Chris McWilliams at University of Colorado. Figure 2(a) is a plot of log current as a function of voltage, while Figure 2(b) is a direct plot from the measuring system. The characteristics are symmetrical and identical in the first and third I-V quadrants.

Resition-Yes without compliance current during the set operation the claimed switching speed combined with the self capacitance would (i = CdV/dt) for large area devices most likely result in destructive currents. And as I think you are suggesting, if the current is not limited then clearly the device would try and RESET itself and it might be considered that a cycle of destructive oscillations would occur. Given the switching speed is a fast as claimed one of the problems of creating a free running oscillators using a simple RC circuit, with a large series resistor from the power supply and a second compliance resistor in series with the capacitor is the need to reduce the voltage to zero after the device is SET.

When a ready supply of CeRAMs becomes available I think one of the projects for the future is to explore the use of the CeRAM as an oscillator, it will be a means of evaluating one aspect of the claimed switching speed. Twice, in the past, I have been involved in exploring the possibility of using threshold switching of phase change materials (PCM) to create a low cost thin film phased array antenna. While free running oscillators could be constructed, one of the problems was it was not possible to get the devices to oscillate a frequencies much above the reciprocal of the thermal time constant; although it was always possible to use the rapid switching transition to ring a microwave cavity and get a burst of pulses, a sort of "chirp".

Looking at the I-V, the CeRAM must have compliance to avoid breakdown (generally a local phenomenon producing a filament). Otherwise it would have self-RESET right after SET, since the SET voltage is larger than RESET voltage.

Dr. Araujo, CeRAM is looking even better than your successful FeRAM. Wish CeRAM be produced by many foundries so everybody can benefit. Designers are going to have a great time with this CeResistor. It is not going to be used just for a flash replacement. Great work again, congratulations!

The key point is the current density that is set by the complience current density equivalent and the materils doping strategy. The data that you see is one that was done for very large areas. It is clear that for very small areas, the resistance can be very high and in the insulating state even higher. This is where the capacitance of the bit line is a major issue, as I believe this is what you are worrying about. Let us now focus on lowering the resistance of the insulating state, as a read pulse would be sent at say 0.2 V. If the resistance is too high, the current is not even measureable. And this would be really a negative point. In essence, this is what led to the "filament" concept. Breaking down most of the small area devices became the normal way to think of RRAMs. And, this led to more than 12 years of research by large companies and laboratories world wide. Samsung for example, had a very definitive paper 12 years ago on NiO, which is still one of the best references. Within the same time period, two initiatives, one in JApan and one in South Korea, created National Centers for correlated electron devices. However, this was a bit too academic. The science was superb but no practical memory device came out. One key point is that there were too many ideas like spintronics, orbitronics and high Tc superconductors. But the idea that correlated electron devices should be the future hit many right notes. Now, a fundamental difference with the CeRAM concept is that the Strong Electron Coreelations are not in the electrons in the "free" electron gas but instead they are in the pairing of electrons in the Nickel Atom. That is, by design a clean (mostly defect free) material - not necessary single crystal, we can control the screening of each Nickel atom (ion) such that, each atom can create the gap or not for insulator to metal transition and vice versa. All p-type insulators can do this and we have made many materials in a controlable way. So, back to your concern, the control of the resistance, specially in the highly insulating state, and get it to work in such a way to have a good "signal" current, is in doping the MIM device. That is, these devices are in essence Metal-Insulator-Metal "diodes" - that is they obey almost perfectly "Simmons Tunneling Formula with Thermionic Emission" However, to make them store in either a conductive state or insulating state, we must either breakdown the oxide and make filaments, or, make a "disproportionation" quantum phase transition - that is, create a gap by spliting an energy level such that the fermi level goes to the middle of the energy gap, or collapsing the gap by screening, and creating a metal like behavior. Contrary to some charge trapping embodiements of RRAM, this is not a field controled device, but a voltage controlled device. The conductivity of the CeRAM devices, when ploting current density vs. electric field, which commonly gives the same slope (conductivity) to any size of area or thickness (standard Ohm's law J=sigma E), it isa completely area dependent. That is, a sigma for every area - clearly not Ohms law. And, you are right, the smallest area gives the smallest sigma. This is a matter of what is called the "Degeneracy Pressure" a purely quantum mechanical phenomenon which has its origin in the Pauli exclusion principle. Well then, the phenomenon is akin to putting actually compressive applied pressure as it is usually done in these insulators. NiO for example, requires 2.4 Million Atmosphere to become a metal. If you look carefully, the relationship between Applied pressure and Degeneracy Pressure is on that leads to Pressure being proportional to electron densities ofraised to 5/3 power. This is acoomplished if we can send by the tunneling at 1.2V (in NiO), electrons equal to this prssure. When this happens, the device conducts and changes the electron density coverage of the Nickel ions creating smaller ion potential radius (goes down to a Bohr radius) in which the bound electron that created the "Gap" and caused the insulating state, to be released. On the other hand, as the anode goes from Zero volts to about 0.6 V (for NiO), the hole injection, for an optimized area to MIM doping ratios, causes the device to go to high resistance as now the electron screening is imperfect. Thus, hole injection is like negative pressure as the electron density goes down near the anode. However, if the device is too small, the volume is small and the lectron Degeneracy Pressure is high, the hole injection is very much constrined by the large electron density. This is the physics of the phenomenon. To understand this well requires that the material is well balanced in maintaining the same coordination number throughout - something that happens only if the stoichiometry is perfect NiO, not NiOx or some dopant that donates electrons and heals the lattice occupying the places where oxygen is lackin. Then comes the first strong answer to your question: Over doping with CO, actually, as simple as puting W(CO)6, a commonly found source for ALD, we can easily go from a complete short to some reasonable resistance value. So, by design - also known as technological control of the material - we can accomplish the reults that are what you wish to see. Also, as you can see in the Symetrix Web site (Symetrixcorp.com) the active region for switching can be as thin as 5-10 nm. So, the thicknesses of near electrode buffer layer, can be thicker, but doped to the point of being shorts. So, imagine that the device is 70 nm thick: the middle layer, 10 nm and the near contact layers are 30 nm. The only thing that makes an insulator happen is the middle layer. The rest of the device is a short. Now, we have the freedom to dope the middle layer too. So, to get the higher current that you are asking for, and lower capacitance, we have 3 degrees of freedom: Thickness of the active region, thickness and doping level of the always conductive buffer layer, and doping of the active region. It is as if we had the ability to dope a filament, control its length and control the distance from filament tio near the electrodes, so that we would control the amount of current passing through the filament. Question - is it not better to control the bulk and not the filament. So, all RRAMs out there, do not have these degress of freedom. Also, because the near electrode material although an oxide, it is always conductive, due to the strong screening caused by the excess electron density due to doping, CeRAMs can have NiSi, COSi and even aluminum as electrodes - NO Platinum is needed, And, since ALD is at about 250 C, there are no temperatures that hurt high node Silicon technology. So, I do not understand why the CBRAM people are so happy with 3 V program and clusters of metal particles randomly moving in a sea of defects is such an answer to the world of Embedded devices. Also, the automotive industry wants higher than 125 C storage. With the quantum effect of CeRAM, it is beyonf further proof that we store both states at 400 c (NiO). Also, reading at 0.2 V has been shown to be stable to 1E12 (as far as we meadured) and that operating temperature varies from 4k (-260 C) to 150 C (as far as we tested) with no problem. So, why is the industry chasing filaments that result from breakdown? Beats me.

The key point is the current density that is set by the complience current density equivalent and the materils doping strategy. The data that you see is one that was done for very large areas. It is clear that for very small areas, the resistance can be very high and in the insulating state even higher. This is where the capacitance of the bit line is a major issue, as I believe this is what you are worrying about. Let us now focus on lowering the resistance of the insulating state, as a read pulse would be sent at say 0.2 V. If the resistance is too high, the current is not even measureable. And this would be really a negative point. In essence, this is what led to the "filament" concept. Breaking down most of the small area devices became the normal way to think of RRAMs. And, this led to more than 12 years of research by large companies and laboratories world wide. Samsung for example, had a very definitive paper 12 years ago on NiO, which is still one of the best references. Within the same time period, two initiatives, one in JApan and one in South Korea, created National Centers for correlated electron devices. However, this was a bit too academic. The science was superb but no practical memory device came out. One key point is that there were too many ideas like spintronics, orbitronics and high Tc superconductors. But the idea that correlated electron devices should be the future hit many right notes. Now, a fundamental difference with the CeRAM concept is that the Strong Electron Coreelations are not in the electrons in the "free" electron gas but instead they are in the pairing of electrons in the Nickel Atom. That is, by design a clean (mostly defect free) material - not necessary single crystal, we can control the screening of each Nickel atom (ion) such that, each atom can create the gap or not for insulator to metal transition and vice versa. All p-type insulators can do this and we have made many materials in a controlable way. So, back to your concern, the control of the resistance, specially in the highly insulating state, and get it to work in such a way to have a good "signal" current, is in doping the MIM device. That is, these devices are in essence Metal-Insulator-Metal "diodes" - that is they obey almost perfectly "Simmons Tunneling Formula with Thermionic Emission" However, to make them store in either a conductive state or insulating state, we must either breakdown the oxide and make filaments, or, make a "disproportionation" quantum phase transition - that is, create a gap by spliting an energy level such that the fermi level goes to the middle of the energy gap, or collapsing the gap by screening, and creating a metal like behavior. Contrary to some charge trapping embodiements of RRAM, this is not a field controled device, but a voltage controlled device. The conductivity of the CeRAM devices, when ploting current density vs. electric field, which commonly gives the same slope (conductivity) to any size of area or thickness (standard Ohm's law J=sigma E), it isa completely area dependent. That is, a sigma for every area - clearly not Ohms law. And, you are right, the smallest area gives the smallest sigma. This is a matter of what is called the "Degeneracy Pressure" a purely quantum mechanical phenomenon which has its origin in the Pauli exclusion principle. Well then, the phenomenon is akin to putting actually compressive applied pressure as it is usually done in these insulators. NiO for example, requires 2.4 Million Atmosphere to become a metal. If you look carefully, the relationship between Applied pressure and Degeneracy Pressure is on that leads to Pressure being proportional to electron densities ofraised to 5/3 power. This is acoomplished if we can send by the tunneling at 1.2V (in NiO), electrons equal to this prssure. When this happens, the device conducts and changes the electron density coverage of the Nickel ions creating smaller ion potential radius (goes down to a Bohr radius) in which the bound electron that created the "Gap" and caused the insulating state, to be released. On the other hand, as the anode goes from Zero volts to about 0.6 V (for NiO), the hole injection, for an optimized area to MIM doping ratios, causes the device to go to high resistance as now the electron screening is imperfect. Thus, hole injection is like negative pressure as the electron density goes down near the anode. However, if the device is too small, the volume is small and the lectron Degeneracy Pressure is high, the hole injection is very much constrined by the large electron density. This is the physics of the phenomenon. To understand this well requires that the material is well balanced in maintaining the same coordination number throughout - something that happens only if the stoichiometry is perfect NiO, not NiOx or some dopant that donates electrons and heals the lattice occupying the places where oxygen is lackin. Then comes the first strong answer to your question: Over doping with CO, actually, as simple as puting W(CO)6, a commonly found source for ALD, we can easily go from a complete short to some reasonable resistance value. So, by design - also known as technological control of the material - we can accomplish the reults that are what you wish to see. Also, as you can see in the Symetrix Web site (Symetrixcorp.com) the active region for switching can be as thin as 5-10 nm. So, the thicknesses of near electrode buffer layer, can be thicker, but doped to the point of being shorts. So, imagine that the device is 70 nm thick: the middle layer, 10 nm and the near contact layers are 30 nm. The only thing that makes an insulator happen is the middle layer. The rest of the device is a short. Now, we have the freedom to dope the middle layer too. So, to get the higher current that you are asking for, and lower capacitance, we have 3 degrees of freedom: Thickness of the active region, thickness and doping level of the always conductive buffer layer, and doping of the active region. It is as if we had the ability to dope a filament, control its length and control the distance from filament tio near the electrodes, so that we would control the amount of current passing through the filament. Question - is it not better to control the bulk and not the filament. So, all RRAMs out there, do not have these degress of freedom. Also, because the near electrode material although an oxide, it is always conductive, due to the strong screening caused by the excess electron density due to doping, CeRAMs can have NiSi, COSi and even aluminum as electrodes - NO Platinum is needed, And, since ALD is at about 250 C, there are no temperatures that hurt high node Silicon technology. So, I do not understand why the CBRAM people are so happy with 3 V program and clusters of metal particles randomly moving in a sea of defects is such an answer to the world of Embedded devices. Also, the automotive industry wants higher than 125 C storage. With the quantum effect of CeRAM, it is beyonf further proof that we store both states at 400 c (NiO). Also, reading at 0.2 V has been shown to be stable to 1E12 (as far as we meadured) and that operating temperature varies from 4k (-260 C) to 150 C (as far as we tested) with no problem. So, why is the industry chasing filaments that result from breakdown? Beats me.

Do not be scared. The data that you saw was purposely created for large geometries, with the piurpose of keeping the current low in that application arena. The beauty of CeRAM is that it is uniformily doped, so that the nanoscale devices can still maintain a decent on current that is not too small for bit line capacitance to kill you nor too high such that it is just a dead short. This is done by several means - the CO doping controls the voltage that the device operates, and the "elemental" doping controls the resistance and scattering. So, you can rest easy that the Resistance can be set high enough for a read operation and yet low enough not to make the signal too low.

In todays high-density array architectures, one of the main issue is about the bitline capacitance. If your read current is too low, you cannot read fast because of the bitline load. Of course you can split arrays and multiply sense banks like some already do, but this is a penalty some cannot afford in term of area. Today, I see nobody reading at 1µA or below in standard embedded nvm macrocells e.g., whatever the sense amp. So when I see the IV curves where Itrans=300nA for a 100x100nm square device, I am a bit 'scared'.