Accelerating Science and Engineering Application Performance

Accelerating Science and Engineering Application Performance

With funding from the National Science Foundation (NSF) and the University of Tennessee (UT), along with assistance from Intel, the National Institute for Computational Sciences (NICS) built Beacon—a cluster designed to help researchers optimize science and engineering applications for the Intel® Many Integrated Core Architecture (Intel® MIC Architecture). Nodes are equipped with the Intel® Xeon® processor E5 family and Intel® Xeon Phi™ coprocessors. By optimizing code, the NICS team and associated researchers found they could achieve more than 2.25 times better performance using a single Intel Xeon Phi coprocessor compared with two processors from the Intel Xeon processor E5 family. Building similar clusters will enable researchers to solve larger, more complex problems while controlling costs.

Challenges• Optimize performance. Provide a high-performance computing (HPC) cluster that would enable researchers to optimize their code for the Intel MIC Architecture.• Control costs. Find ways to build more efficient clusters that can help researchers solve larger, more complex problems without significantly increasing hardware acquisition expenses, energy consumption, or software development costs.

With funding from the National Science Foundation (NSF) and the University of Tennessee (UT), along with assistance from Intel, the National Institute for Computational Sciences (NICS) built Beacon—a cluster designed to help researchers optimize science and engineering applications for the Intel® Many Integrated Core Architecture (Intel® MIC Architecture). Nodes are equipped with the Intel® Xeon® processor E5 family and Intel® Xeon Phi™ coprocessors. By optimizing code, the NICS team and associated researchers found they could achieve more than 2.25 times better performance using a single Intel Xeon Phi coprocessor compared with two processors from the Intel Xeon processor E5 family. Building similar clusters will enable researchers to solve larger, more complex problems while controlling costs.

Challenges• Optimize performance. Provide a high-performance computing (HPC) cluster that would enable researchers to optimize their code for the Intel MIC Architecture.• Control costs. Find ways to build more efficient clusters that can help researchers solve larger, more complex problems without significantly increasing hardware acquisition expenses, energy consumption, or software development costs.