2018-03-19T14:42:47ZSigma-Delta Modulators with Passive RC Integrators: Theory, Design Methodology for Optimization and Silicon Resultshttp://hdl.handle.net/10362/31869
Título: Sigma-Delta Modulators with Passive RC Integrators: Theory, Design Methodology for Optimization and Silicon Results
Autor: Melo, João Luís Alvernaz de
Resumo: In this Thesis, energy and area efficient techniques are discussed and a CT SDM,
with 27.5 fJ/conv.-step of energy efficiency, employing passive RC integrators is
presented. Between each passive RC integrator a simple differential pair is added,
as low-gain open-loop amplifier, and most of the loop gain is obtained in the
1-bit comparator. Nevertheless, the processing gain is limited by the comparator’s
noise due to the low voltage swing at the input of this building block. In order
to maximize the performance, and due to a large number of trade-offs, such
as the nonlinear behavior of the 1-bit quantizer that drastically affects the NTF
(specially with low input signals), the circuit has been designed with a systematic
design methodology, also proposed in this thesis based on a genetic algorithm
(GA). Moreover, and due to the trade-off between RC variations and loop stability,
the modulator is also optimized taking this undesired behavior in consideration,
avoiding the need for any self-calibration. The 65 nm CMOS SDM prototype
designed, implemented and experimentally evaluated during this research work,
occupies only 0.013 mm2, dissipates 256 mWfrom a 0.7 V supply, and it achieves
a peak SNDR of 69.1 dB in a 2 MHz bandwidth (BW). The dynamic range (DR)
reaches 76.2 dB, which corresponds to a Schreier figure-of-merit (FoMSchreier) of
175.1 dB. To the best of the author’s knowledge, the proposed modulator is the
most energy- and area-efficient designs published thus far1, considering SDMs with BWs larger than 50 kHz published at the two flagship conferences requiring
silicon demonstration, namely, IEEE ISSCC and IEEE Symposium on VLSI Circuits
[1].2017-12-01T00:00:00ZAnalysis and Design Methodologies for Switched-Capacitor Filter Circuits in Advanced CMOS Technologieshttp://hdl.handle.net/10362/30792
Título: Analysis and Design Methodologies for Switched-Capacitor Filter Circuits in Advanced CMOS Technologies
Autor: Serra, Hugo Alexandre de Andrade
Resumo: Analog filters are an extremely important block in several electronic systems, such as RF transceivers, data acquisition channels, or sigma-delta modulators. They allow the suppression of unwanted frequencies bands in a signal, improving the system’s performance. These blocks are typically implemented using active RC filters, gm-C filters, or switched-capacitor (SC) filters.
In modern deep-submicron CMOS technologies, the transistors intrinsic gain is small and has a large variability, making the design of moderate and high-gain amplifiers, used in the implementation of filter blocks, extremely difficult. To avoid this difficulty, in the case of SC filters, the opamp can be replaced with a voltage buffer or a low-gain amplifier (< 2), simplifying the amplifier’s design and making it easier to achieve higher bandwidths, for the same power. However, due to the loss of the virtual ground node, the circuit becomes sensitive to the effects of parasitic capacitances, which effect needs to be compensated during the design process.
This thesis addresses the task of optimizing SC filters (mainly focused on implementations using low-gain amplifiers), helping designers with the complex task of designing high performance SC filters in advanced CMOS technologies. An efficient optimization methodology is introduced, based on hybrid cost functions (equation-based/simulation-based) and using genetic algorithms.
The optimization software starts by using equations in the cost function to estimate the filter’s frequency response reducing computation time, when compared with the electrical simulation of the circuit’s impulse response. Using equations, the frequency response can be quickly computed (< 1 s), allowing the use of larger populations in the genetic algorithm (GA) to cover the entire design space. Once the specifications are met, the population size is reduced and the equation-based design is fine-tuned using the more computationally intensive, but more accurate, simulation-based cost function, allowing to accurately compensate the parasitic capacitances, which are harder to estimate using equations. With this hybrid approach, it is possible to obtain the final optimized design within a reasonable amount of computation time.
Two methods are described for the estimation of the filter’s frequency response. The first method is hierarchical in nature where, in the first step, the frequency response is optimized using the circuit’s ideal transfer function. The following steps are used to optimize circuits, at transistor level, to replace the ideal blocks (amplifier and switches) used in the first step, while compensating the effects of the circuit’s parasitic capacitances in the ideal design. The second method uses a novel efficient numerical methodology to obtain the frequency response of SC filters, based on the circuit’s first-order differential equations. The methodology uses a non-hierarchical approach, where the non-ideal effects of the transistors (in the amplifier and in the switches) are taken into consideration, allowing the accurate computation of the frequency response, even in the case of incomplete settling in the SC branches.
Several design and optimization examples are given to demonstrate the performance of the proposed methods. The prototypes of a second order programmable bandpass SC filter and a 50 Hz notch SC filter have been designed in UMC 130 nm CMOS technology and optimized using the proposed optimization software with a supply voltage of 0.9 V. The bandpass SC filter has a total power consumption of 249 uW. The filter’s central frequency can be tuned between 3.9 kHz and 7.1 kHz, the gain between -6.4 dB and 12.6 dB, and the quality factor between 0.9 and 6.9. Depending on the bit configuration, the circuit’s THD is between -54.7 dB and -61.7 dB. The 50 Hz notch SC filter has a total power consumption of 273 uW. The transient simulation of the circuit’s extracted view (C+CC) shows an attenuation of 52.3 dB in the 50 Hz interference and that the desired 5 kHz signal has a THD of -92.3 dB.2017-12-01T00:00:00ZMonitoring and Information Alignment in Pursuit of an IoT-Enabled Self-Sustainable Interoperabilityhttp://hdl.handle.net/10362/30472
Título: Monitoring and Information Alignment in Pursuit of an IoT-Enabled Self-Sustainable Interoperability
Autor: Ferreira, José Alexandre Pires
Resumo: To remain competitive with big corporations, small and medium-sized enterprises (SMEs) often need to be more dynamic, adapt to new business situations, react faster, and thereby survive in today‘s global economy. To do so, SMEs normally seek to create consortiums, thus gaining access to new and more opportunities. However, this strategy may also lead to complications. Due to the different sources of enterprise models and semantics, organizations are experiencing difficulties in seamlessly exchanging vital information via electronic means. In their attempt to address this issue, most seek to achieve interoperability by establishing peer-to-peer mappings with different business partners, or by using neutral data standards to regulate communications in optimized networks. Moreover, systems are more and more dynamic, frequently changing to answer new customer‘s requirements, causing new interoperability problems and a reduction of efficiency. Another situation that is constantly changing is the devices used in the enterprises, as the Enterprise Information Systems, devices are used to register internal data, and to be used to monitor several aspects. These devices are constantly changing, following the evolution and growth of the market. So, it is important to monitor these devices and doing a model representation of them. This dissertation proposes a self-sustainable interoperable framework to monitor existing enterprise information systems and their devices, monitor the device/enterprise network for changes and automatically detecting model changes. With this, network harmonization disruptions are detected in a timely way, and possible solutions are suggested to regain the interoperable status, thus enhancing robustness for reaching sustainability of business networks along time.2017-12-01T00:00:00ZExtending nearly Zero-Energy Buildings Load Matching Improvement to Community-Levelhttp://hdl.handle.net/10362/29113
Título: Extending nearly Zero-Energy Buildings Load Matching Improvement to Community-Level
Autor: Lopes, Rui Miguel Amaral
Resumo: The nearly Zero-Energy Building (nZEB) concept is foreseen as a reference for the future of the European building stock. While several factors contribute to the introduction of legal instruments that promote a fast adoption of these buildings (e.g. energy efficiency), their relationship with Low Voltage distribution Grids (LVGs) is far more complex than the one of the regular buildings. In order to improve the grid interaction of nZEBs in particular, and of regular buildings equipped with distributed generation systems in general, Load Matching (LM) improvement incentives are
being promoted worldwide.
The literature shows that the existing LM improvement measures, that use the Energy Flexibility offered by controllable electricity demand devices, are only conducted at individual buildings (i.e. Building-Level) without taking into consideration the demand and on-site generation profiles of other buildings. Therefore, the first main objective of this research work refers to the assessment of impacts introduced by Building-Level LM improvement measures on existing LVGs. In order to improve the benefits offered to LVG operators and building owners (when compared to the existing Building-Level LM improvement measures), the second main objective concerns the development of a new LM improvement approach. For this purpose, the Cooperative Net-Zero Energy Community concept is introduced, extending the LM improvement to the Community-
Level.
A neighborhood made up of 33 buildings is considered to conduct the necessary experiments, where the benefits offered to LVG operators are quantified by three important Performance Indictors and the benefits offered to building owners are quantified by the respective electricity bills. The obtained results show that Building-Level LM improvement measures can be harmful to LVG operators when large amounts of controllable electricity demand are shifted to coincident periods. The conducted experiments also show that the proposed Cooperative Net-Zero Energy Community concept improves the benefits offered to LVG operators and building owners.2017-12-01T00:00:00Z