An ECE team led by Cameron Patterson is investigating methods to speed up implementation of large-scale FPGA designs. The work is supported by a grant from the Defense Advanced Research Projects
Agency (DARPA).

“The size of available FPGAs – well over 2 billion transistors – is adversely affecting productivity due to the time required for the FPGA tools to generate a new configuration after a design change,” Patterson says.

Current FPGA tools often require complete re-implementation of a design when a module change affects other modules, he says. “In the software domain, this would be analogous to recompiling all libraries whenever a change is made to application code. Unfortunately, the conventional approach does not exploit the inherent ability of FPGAs to rapidly update portions of the circuitry while other parts remain unchanged and even operational,” he adds.

The team is investigating the use of run-time reconfiguration (RTR) to add a software-like module linkage step, reducing the time required to add or replace a module by up to three orders of magnitude. “RTR has not previously been used in this way,” Patterson adds. The new tools will proactively generate a variety of new layouts to quickly accommodate module changes, much like chess-playing programs anticipating the human player’s future moves.