I think we are getting too hung up on the terms “staggered” vs. “parallel”.

The case that you are describing where detection can occur on both pairsets prior to powering of one pairset falls into the “parallel” category.

Yair: I agree to it but it is not clearly defined. What is the common knowledge so far is that
“parallel”
is when primary detection and secondary detection are done within Tpon. This definition is good and flexible for both single and dual signature when used for
“parallel”.

My questions are:

How “staggered”
is defined for single-signature?

How “staggered”
is defined for dual-signature?

In this case, “parallel” does NOT mean simultaneous.

Yair: I understand it, but it is not defined as such. We need text to define it in CC_DET_SEQ definition. We need text to define staggered as well.

It just means that they both occur prior to powering either pairset (this is covered with CC_DET_SEQ=0).

Yair:

Is it correct that
“parallel” is defined with in Tpon?

Is it correct that staggered detection can happen as follows for dual-sig PD.

Alt A is doing detection. Detection takes 499msec. Classifiy and before starting powerup, Alt B start to detect. In my mind, this was staggered too.

I am sure that it was the original intention in the SM for CC_DET_SEQ=3 but it doesn’t
cover all possibilist of CC_DET_SEQ=3 especially the popular ones that I am sure you want to support as well.

The definitions of CC_DET_SEQ variable in page 109 line 38 doesn’t
say that “staggered” in CC_DET_SEQ=3 means
that it is limited to the case that one of the pairs need to be on while the other pair is donning detection. This was never the only intent. If this was the intent, how should I interpret
“staggered” in CC_DET_SEQ=1?

Moreover, what if you want to POWER_ON both pairsets with minimum time delay between each pairsets and not wait to one pairset to be ON and only then to do detection on the
other?

This is a PSE system objective that PSE vendors need not to overlooked.

Thanks for making that clear. This confirms that a different interpretation of 'staggered' and 'parallel' lies at the base of this request. In essence, what Yair wants to do is possible using sequence 0 or 1.

What we may want to do is expand a bit the explanation of CC_DET_SEQ 3, because it misses this key bit of information that the second pairset can only proceed with detection after the first is powered on.

I would also assume that this staggered behavior is intentionally used to verify 4PID for dual-signature PDs ?

So, if we allow detection to happen before the first pairset of powered on, we'll break the 4PID mechanism of this sequence ?

For DS, Sequence 3 enforces that detection on secondary pairset does not occur until after the primary
pairset is powered. That is what is meant by “staggered”. For DS, Sequence 0, the detection/class has no enforced timing relationship. “Parallel” just means that they happen pseudo-concurrently, but not necessarily sync’d.