The AMC13 has 3 SFP transceivers which may be used for DAQ. There are 3 possible configurations, determined by the value written to CONF.SFP.ENABLE_MASK. In addition, CONF.EVB.ENABLE_DAQLSC must be set to '1'. The AMC13Tool2 command daq may be used to accomplish this configuration.

At power-up the S-Link Express core and associated GTX SERDES will be enabled for any SFP which are installed. The AMC13 must still be configured to send data on the appropriate SFP by writing the registers described above. Normally, ACTION.RESETS.DAQ should not be written as this will cause the GTX to be reset again, possibly bringing the link down.

Before data can be acquired through the link, the S-Link Express core must be properly configured by taking action on the receiver side (see uFEDKIT documentation for details)

After changing the DAQ output configuration the logic and high-speed transceivers may be reset by writing to ACTION.RESETS.DAQ (AMC13Tool2 command rd) but after this the links must be reconfigured from the receiver end.

The DAQ sender firmware itself was provided by the CMS cDAQ group. Links to the firmware
in the CERN SVN and it's documentation may be found here:

TTS

The TTS (Trigger Throttling System) output from the AMC13 is a four-bit code transmitted over
the transmit half of the bottom SFP fiber transciever, and is normally sent to the TCDS system
to control the trigger rate in response to pending buffer overflows. This system is intended
to be logically compatible with the legacy system documented
HERE.
Recently (2018) a new set of states has been added, please see this page.

The AMC13 outputs the TTS state as the four-bit code described in the links above:

0

0000

Disconnected

Hardware Failure or broken cable

1

0001

Overflow Warning

Imminent buffer overflow

6

0110

DAQ Overflow Warning

Overflow warning due to DAQ link backpressure (2018)

2

0010

Sync Lost

AMC13 is not synchronized with DAQ due to buffer overflow

4

0100

Busy

Cannot accept triggers

8

1000

Ready

Ready to accept triggers

9

1001

Private Request 1

Available for private use (2018)

a

1010

Private Request 2

Available for private use (2018)

b

1011

Private Request 3

Available for private use (2018)

c

1100

Error

Any other state that prevents functioning

f

1111

Disconnected

Hardware failure or broken cable

The states "Private Request 1..3" have the same priority as "Ready". They are never internally
generated by the AMC13 but are passed on if received from connected AMC cards in the crate.

The state "DAQ Overflow Warning" indicates that the AMC13 has an impending buffer overflow
and that simultaneously the DAQ output link has asserted the busy (backpressure) signal.

The states marked (2018) were recently added and must be explicitly enabled by setting
bit 9 in T1 register 1 (tentatively named CONF.ENABLE_WARNING_DUE_TO_DAQ_TTS in the AMC13
address table). These features were added in about firmware version 0x6061 (0x2261).

Any time the AMC13 is not in run mode (such as after power up)
the AMC13 sends state "0100" (busy).

Internally the AMC13 manages the TTS state using a 5 bit internal format; this is
exposed in a few monitoring registers. This format should be decoded as text
in the latest AMC13 software, but is documented here for completeness:

Bit 4

Disconnected

Bit 3

Error

Bit 2

Sync Lost

Bit 1

Busy

Bit 0

Overflow Warning

(A value of 0 means "ready")

The TTS state is sent over the same 5.0Gb/s link as the DAQ data. There's an input port in our link logic on the AMC side:

When the TTS state changes, a control word is sent across the link to transfer the information with minimum latency to the AMC13. A TTS state must persist for at least two BX to be guaranteed to be transmitted. Latency is "minimum" but not guaranteed to be any specific value.

Here are some more details on how the TTS state is generated in the AMC13:

The AMC13 contains an L1A FIFO into which L1A are stored when received by the TTC or generated by the internal L1A generator. The event builders (up to 3) read L1A from the FIFO and wait for available event fragments from each enabled AMC input. Then the event is built and sent out the corresponding DAQ link and/or stored in the SDRAM monitor buffer. The AMC13 internal TTS state is generated exclusively based on the number of L1A stored in the L1A FIFO.

Additionally, up to 12 TTS states are received as described above from AMC cards. The final TTS output state is simply a priority encoding of the 12 AMC states plus the local AM13 one.

Transition

FIFO level

RDY->OFW

96

OFW->RDY

63

OFW->BSY

224

BSY->OFW

223

BSY->SYN

225

TTC Simulator

The AMC13 has the ability to generate simulated TTC signals and distribute them to AMC cards in the crate.
This allows operation of a stand-alone test setup with only an AMC13 and AMC cards in a single crate without
requiring any external TTC hardware. The simulated TTC signal will always include a BC0 sent once per LHC orbit.
Four "BGO" channels are provided which can send programmed short or long format TTC commands either
once under program command or periodically.
In addition, ECR (event count reset) and OCR (orbit count reset) TTC commands may be sent by writing
to the ACTION.LOCAL_TRIG.SEND_ECR and ACTION.LOCAL_TRIG.SEND_OCR registers, respectively.

N.B. the OCR and ECR mentioned above will not be reflected in the AMC13 registers until after
the next L1A, as the current EvN and OrN in the AMC13 are not visible; they are used only to stamp
an event in in response to L1A.

The "BGO" channels are programmed using registers 0x24-0x27 (CONF.TTC.BGOn).
Each of the four channels requires the following settings, where BGOn is BGO0,
BGO1, BGO2 or BGO3.

Bit '1' to enable single command (trigger with ACTION.TTC.SINGLE_CMD) [1]

CONF.TTC.BGOn.ORBIT_PRESCALE

Orbit prescale (prescale is value + 1)

CONF.TTC.BGOn.BX

Bunch crossing number on which to send command

[1] Only one of four ENABLE_SINGLE may be set at one time.
If bit is set to 0 and ENABLE is set to '1' the commands are sent periodically

Locally-generated triggers may be sent in a rather flexible way. See the next section for details.

The simulated TTC function requires a TTC stream with at least the clock to be
input to the receiver side of the TTC SFP. This can be provided externally,
or via a short loop-back cable plugged
between the input and output sides of the bottom SFP.

This feature is enabled by setting CONF.DIAG.FAKE_TTC_ENABLE to 1. The local L1A generator
must also be enabled (CONF.TTC.ENABLE_INTERNAL_L1A set to 1).

TTC Command Details

The AMC13 can transmit and take action on several specific TTC commands.

Event Count Reset (send at the start of each lumisection to set the EvN to 1)

OC0

9

Yes

Orbit Count Reset - reset orbit count to 0

Resync

0x28

Yes

Resync after error

Note that for the programmable commands, there is both a command value register (8 bits)
and a mask value register (8 bits) which allows only specific bits to be matched when decoding
a received command.

Resync command

This command is designed to allow the CMS DAQ system to recover from cases where one or more data sources loses synchronization due to e.g. a radiation-induced single-event upset in the event number or buffer overflow. The idea is that when the SYN state is reported over TTS that the central trigger will stop sending triggers, issue a special "Resync" TTC broadcast command, and then wait for all data sources to send data for all the L1A received before the resync, then flush any remaining data and set TTS to RDY.

Here is Christoph Schwick's description of how this facility works:

When the Re-sync sTTS state is detected by the Trigger for 8 orbits no L1 Triggers are issued.

In BX 2000 of the following orbit the BGO 0101 (Re-sync) is issued.

It follows another gap of 8 orbits without triggers. This interval is used by sub systems to do whatever they need to do. If they need more time they are allowed to issue sTTS BUSY.

If the gap of 8 orbits has passed AND all sub-systems are in ready state in the following orbit at BX 2000 an EC0 (BGO 0111) is issued to reset all Event Counters of all sub-systems to '1'.

After the next BC0 'normal operation' is resumed.

Here is Mr Wu's description of how the AMC13 processes resync:

Upon receiving the resync, AMC module can either clear its buffer or continue to send data to the backplane link module until data are exhausted. Once no more data in the AMC, it should assert the new link input ResyncAndEmpty high for at least 10 ns and set TTS to Ready when AMC module is ready to accept new L1A.

The link module will send properly formatted event data for every L1A it received, if necessary with faked events. If an event has any faked data,
bit 23 of the AMC event trailer will be set to 1.

When AMC13 finished building all events of received L1As, it will reset the backplane links if any faked data have been detected. Otherwise it
will just remove TTS busy and forward AMCs' TTS state to the TCDS system.

AMC13 event number will be reset to 1 upon receiving the TTC command, event number in the link module will also be reset to 1 once resync is done.

If AMC13 itself went OOS due to TCDS ignoring TTS, AMC13 will never remove the TTS BUSY and a cold start must be done.

Local L1A Generator

This feature allows the AMC13 to generate L1A and transmit them over the TTC backplane signals to AMC cards.
It may be used in conjunction with the TTC Simulator described above, or with an external TTC input.

There are 4 modes of operation available:

Individual triggers under software control

Burst with count and spacing in BX or orbits specified

Continuous triggers equally spaced by BX or orbits

Random triggers from 2Hz to about 130kHz rate with CMS trigger rules respected

Various registers are used to control the local L1A generator. The easiest way to control this feature
is using the method AMC13::configureLocalL1A() in the AMC13 class. Then, call AMC13::sendL1ABurst() to
send a single software-triggered burst, or AMC13::startContinuousL1A() and AMC13::stopContinuousL1A() to
start or stop continuous triggers.

Rule 1 is always enforced. The rules parameter to AMC13::configureLocalL1A or
the CONF.LOCAL_TRIG.RULES item may be set as follows to suppress other rules:

0 means enforce all rules (1-4)

1 means all except rule 4

2 means enforce rules 1 and 2

3 means enforce only rule 1

Fake Data Generator

The AMC13 can generate fake AMC data for testing. This works even if the
AMC13 is not in the normal slot (it can be in any MicroTCA crate slot).
Enable this feature using the f option to the enable command, e.g.

> en 1-12 f t

The size of each fake event may be set with:

> wv CONF.AMC.FAKE_DATA_SIZE

where the value is the number of 64-bit words in the body of the event.
Here is an example for a small event (size set to 3):

Note that all the "user" data is filled with 16-bit counter data,
which starts at 0000 with the first word of the first AMC header,
but values 0000-0005 are replaced by fixed values, so the first visible
counter value is 0006.

TTC History Capture

This feature added to the T2 (Spartan) firmware starting in version 0x26
allows the capture of up to 512 TTC short-format broadcast commands in a buffer.
The commands may originate in the AMC13 itself (if the TTC simulator is being used)
or received externally on the TTC fiber input.

A filter feature is provided which checks incoming commands against a list
of up to 16 entries, and if a match is found the command is discarded rather
than being stored in the history.

Monitor Buffer

The AMC13 can store up to 1024 event blocks in SDRAM memory pages (aka buffers) each
occupying 512k bytes. The default mode at power-up is that up to 1024 blocks are stored
(independent of DAQ outputs), storing stops and the bit STATUS.MONITOR_BUFFER.FULL is set.
At any time the number of occupied buffers may be read from STATUS.MONITOR_BUFFER.UNREAD_EVENTS.
Note that if any AMC payload is > 32k bytes the event will be segmented and the number of buffers
will be greater than the number of events.

One buffer at a time may be read at MONITOR_BUFFER_RAM, which
presents a window of up to 512k bytes (0x20000 32-bit words). Advance to the next buffer by writing to
ACTION.MONITOR_BUFFER.NEXT_PAGE. Note that one buffer may contain only the first block
of a segmented event. Generally a user should call AMC13::readEvent() to obtain the next event
including all blocks/buffers as necessary. After reading an event the corresponding buffers are freed
and new events may be stored.

If the AMC13 is configured with multiple event builders, then the monitor buffer ram is segmented with the following register name (address in parentheses), and each event builder is responsible for a subset of AMCs:

The word count for the current buffer address is found at (0xd, 0xf, 0x1d) for first, second, third event builders. The register name is STATUS.MONITOR_BUFFER.WORDS_SFP0 for Buffer_0, and you can replace 0 with 1 or 2 for the other event builders.

When multiple event builders are active, L1As with the same event number are guaranteed to start at the same buffer page. The word count in a segment of the monitor buffer can be zero while there is still valid data in other segments to allow for that to happen. It is important to note that reading from only one event builder and then advancing to the next buffer page will cause a loss of data in the other event builders. The method AMC13::readEventMultiFED() will automatically determine the number of event builders and return a vector containing a vector of 64 bit words for each active event builder representing the L1A.

Monitor Buffer Overwrite Mode

The monitor buffer may be run in a special "overwrite mode" in which case it acts as a circular buffer which continuously fills, overwriting any older data which may be present (the default behavior is to stop when full). This special mode can be useful as a spy on the data stream sent to the DAQ for diagnosing problems. Overwrite Mode differs from normal mode as follows:

CONF.EVB.MON_FULL_OVERWRITE must be set to '1' to enable the mode

STATUS.MONITOR_BUFFER.UNREAD_BLOCKS points to the next page to be written (0-0x3ff).

Local Trigger Logic (DT)

The following section describes a local trigger implemented for the DT group according
to the following specification: DT AMC13 requirement (rev 2015-06-05).
This trigger logic is contained entirely in the T2 (Spartan) FPGA and is introduced in version 0x29.

This trigger uses Fabric B inputs from 12 AMC modules and TRIG0 and TRIG1 from
special T3 board as inputs to a 14-bit Look Up Table to generate a trigger at
every TTC clock cycle.

To align the trigger inputs, there is an 8 bit delay line at each trigger input.
The unit of the delay is one eighth of a TTC clock cycle.
To help adjusting the delays, there is a sampling buffer of 14-bit and 1024 deep
which samples the delayed input trigger at eight times of the TTC clock frequency.

Before using the trigger, delay adjustment is necessary.

First, write 1 to register 0x101 to enable the trigger.

Second, fill the LUT with 0xffffffff except 0x200 which should be loaded with 0xfffffffe. This results a trigger of simple OR of all fourteen trigger inputs.

Then write 1 to register 0x100 to enable the sampling.

After that send a signal to all fourteen trigger source so that LUT will receive trigger from all of them.

Read out the sampling buffer and first adjust the three LSB of the input delay so that the trigger will be recorded with the same seven MSB of the sample buffer read address. (assuming the input trigger signal is 25 ns wide, otherwise the trigger should be centered in the bins at least), this ensures the LUT clock edge is always optimally centered.

Next adjust the seven MSB of the input delay so that all input trigger have the same seven MSB address of the sample buffer.

This calibration should be repeated whenever possible to correct for possible timing drift due to temperature/voltage changes.

LUT trigger uses registers in the range of 0x100-0x10f and 0x200-0x7ff. The bits are numbered LSB-MSB within each 32-bit word, and thus may be treated as a single vector of 16384 bits. The address within this vector is formed using a 14-bit address as follows:

LUT Address Bit

13

12

11

...

1

0

Input

TRIG1

TRIG0

AMC12

...

AMC2

AMC1

This feature is controlled by the following registers on the T2 board (so use the writeT2 or ws commands in AMC13Tool2.exe).

Local Trigger Logic (HCAL)

The following section applies only to the HCAL firmware series (Kintex v0x4000 and up).
A local trigger may be formed from 8 bits supplied each BX from each AMC card.
There are a total of 8 independent logic triggers which are evaluated every BX
and output on an optical fiber at 1.6 Gb/s (actually the TTC clock times 40) with 8b10b encoding.
(Fabric B is not used because the HCAL uHTR did not connect it!)

Each of the 8 individual logic triggers works as follows:

Apply a mask to each of 8 bits from each of 12 AMCs (96 bits programmable). A '1' bit disables the corresponding input

Count the number of non-zero AMC bytes after masking (result is 0-12)

Apply a programmable threshold to this value, producing a '0' or '1' resut

So there are a total of 96 * 8 programmable mask bits and 8 programmable 0-12 thresholds.

Clock / Trigger Inputs

The AMC13 external trigger can come from one of 3 sources (optical fiber, internal or external copper signal).
The AMC operating clock can only come from the fiber input, though this can be provided in a self-contained way using a loop-back fiber .
The choices are enumerated in the following table.

Resetting the PLL

The PLL which recovers the clock on the TTC input may lose lock if e.g. the TTC clock is interrupted for some reason. This PLL may be reset using the following command in '''AMC13Tool2''':

> wv 0x0 0x8

Currently there is no address table entry nor dedicated command to accomplish this. This reset is performed only at power-up and not as part of any software initialization sequence in the AMC13 or HCAL software! It can require up to 100us for the PLL to lock.

HCAL Orbit Gap Calibration

The AMC13 implements several features to facilitate triggers for calibration purposes during the LHC "Orbit Gap" during which no normal L1A should occur. The details of this have to a certain extent been lost in time.

See 2009 CMS Note by Jeremy et al about this.
Here is a table of TTC command used by HCAL extracted from the document.

Wu's Debugging Guide

AMC13 quick trobleshooting with register dump
Last updated on 3/19/2015
Following description is accurate only for T1 versions
0x4020, 0x225, T2 version 0x27 and later.
Also make sure bit 11-0 of T1 reg 0x5 are all 0, any bit
set to 1 indicates that AMC module has a different backplane
link version as that of the AMC13 T1 firmware.
T1 version is bit 31-16 of T1 reg 0x1
T2 version is bit 15-0 of T2 reg 0x0
a)Keep firmware up to date
Always check for the latest firmware and upgrade
your system. New versions are released to fix bugs or
adding debugging information, so it is important to
keep your firmware up to date. If you have problems,
upgrade to the latest version and see if that solves
your problem.
b)TTC problems
Once set up right and TTC works correctly, check regularly
the following T2 registers:
0x7 counts bcnt errors, it should have no more than couple
of counts.
0x8 counts TTC single errors, it should have no more than couple
of counts.
0x9 counts TTC multiple errors, it should have no more than couple
of counts.
If TTC does not work,
first check T1 reg 0x4:
if bit0 is 1, TTC optical receiver is absent.
if bit7 is 1, there's no TTC input signal, check the
cabling to TTC source.
If AMC13 registers look OK, but AMC modules have TTC
problem, make sure your TTC decoder has the right timing.
AMC13 output TTC clock's edge is in the middle of the TTC
data on the backplane.
c)run stopped because of AMC13
If run stopped and bit 15-12 of T1 reg 0x19 is not 0x8, check T1 registers
0xe1a, 0xe1b and 0xe1c. If any of them is non-zero, at least one AMC is
causing the problem. Each AMC uses one byte, AMC1 using bit7-0 of reg 0xe1a
and AMC2 using bit15-8 of reg 0xe1a and AMC3 .... The definition of the byte is
bit7 if set, AMC has been in disconnected state
bit6 if set, AMC has been in error state
bit5 if set, AMC has been in out of sync state
bit4 if set, AMC is in disconnected state
bit3 if set, AMC is in error state
bit2 if set, AMC is in out of sync state
bit1 if set, AMC is in busy state
bit0 if set, AMC is in overflow warning state
If AMC13 is in overflow warning or busy states, first check T1 reg 0x0. If bit0
is set, cDAQ is down. Otherwise, check T1 reg 0xd4, if bit 18-16 are not all 0.
cDAQ full stopped sending data out. If cDAQ is neither down nor full, and bit 10-8
are all 0, then it is event builder not building events. Next check T1 register
0xe0c, if any bit of bit 11-0 is not 0, the corresponding AMC(bit 0 AMC1) has no
data.
d) data integrity problems
T1 register 0xb3-0xb5 counts event cmsCRC error for SFP0,SFP1 and SFP2
T1 register 0xb6-0xb8 counts event length error for SFP0,SFP1 and SFP2
T1 register space 0x800-0xdff are monitoring counters for AMC modules,
each AMC module occupies 0x80 32 bit space, AMC1 uses 0x800-0x87F.
following registers' address is offset address in their own space. Each counter
occupies two 32 bit space. Even address is the lower 32 bits and odd address is
the upper 16 bits of the counter.
offset 0x6-7 is event number of the event mismatch counter
offset 0x8-9 is Orbit count of the event mismatch counter
offset 0xa-b is BC count of the event mismatch counter
offset 0x12-13 is bad EventLength counter
offset 0x14-15 is trailer Evn mismatch counter
offset 0x1e-1f is link input Evn skip counter
offset 0x3a-3b short event at input counter(less than three 64bit words)
offset 0x3c-3d number padded words for short event
(offset less than 0x40 are from the backplane link module built inside the AMC module.)
offset 0x6a-6b is the same as offset 0x6-7, but counted inside AMC13
offset 0x6c-6d is the same as offset 0xa-b, but counted inside AMC13
offset 0x6e-6f is the same as offset 0x8-9, but counted inside AMC13
offset 0x70-71 is the same as offset 0x12-13, but counted inside AMC13
offset 0x78-79 is bad AMC event CRC counter
offset 0x7a-7b is TTS state is error counter
offset 0x7c-7d is TTS state is out of sync counter
offset 0x7e-7f is TTS state is disconnect counter
If all these counters are 0, there is no data integrity problem detected.
e) Other T1 registers containing important run information
0x46 number of L1A received
0xba low word of SFP0 sum of event length from CDF trailer
0xbb bit 55-32 of SFP0 sum of event length from CDF trailer
0xbc low word of SFP1 sum of event length from CDF trailer
0xbd bit 55-32 of SFP1 sum of event length from CDF trailer
0xbe low word of SFP2 sum of event length from CDF trailer
0xbf bit 55-32 of SFP2 sum of event length from CDF trailer
0xc0 SFP0 built event count
0xc1 SFP1 built event count
0xc2 SFP2 built event count
0xc4 SFP0 built event word count(lower 32 bit)
0xc5 SFP1 built event word count(lower 32 bit)
0xc6 SFP2 built event word count(lower 32 bit)
0xc8 SFP0 built event block count
0xc9 SFP1 built event block count
0xca SFP2 built event block count
in the range of 0x800-0xdff, for each AMC module:
offset 0xc-d number of events received at link input
offset 0x18-19 number of words received at link input
offset 0x40-41 number of words received by AMC13 from AMC module
offset 0x52-53 number of events received by AMC13 from AMC module
offset 0x72-73 number of event blocks received by AMC13 from AMC module
f) Monitor buffer can buffer up to 0x400 events/blocks, each buffer occupies
0x20000 32 bit words.
you can read any buffer using the following command:
rv [starting address] [length]
where starting address = 0x8000000 + (offset x 0x20000)
e.g. the starting address of the first buffer is 0x8000000
and the starting address of the second buffer is 0x8020000, etc.
maximum offset is 0x3ff and the length is in 32 bit words.
Please email comments and suggestions to
wusx@bu.edu with subject as amc13debug

Monitoring Registers

This section provides documentation on a few of the monitoring registers which have proven to be confusing. Eventually there should be detailed description for all registers, but who knows when this will get done!

AMC_EvN_Mismatch (offset 0x6/0x7)
This checks that the EvN in bits 32-55 of the first word sent by the AMC
Matches the current EvN in the AMC13 (reset to 1 on EcR, increment each L1A)
This check is performed in our link firmware in the AMC card.
AMC_Trailer_EvN_Bad
This checks if the 8 bits of EvN in the last word bits 24-31 match bit 32-39
of the first word.
AMC_EvN_Errors
This check if the EvN supplied by the AMC increments by one each L1A
AMC13_EvN_Mismatch
This is essentially the same as AMC_EvN_Mismatch except that the check
is performed in the AMC13 firmware.