These events may be entirely internal such as a regular 1KHz timer interrupt or transmitter ready for next byte for RS-232. Or these events may be external such as a (perhaps specific) state change on an input pin. External events may be regular (AC mains zero crossing) or as unpredictable as a button press. Or events may be set entirely by software. (See last paragraph.)

Interrupts may be deferred. A higher priority interrupt may be running when some event causes a lower priority interrupt. The lower priority interrupt waits (pending condition) until the higher priority interrupt is finished.

With the Cortex NVIC it is possible to force an interrupt pending condition. This might be used when an OS servicing an interrupt needs to enter the ISR that does task switching. This is yet another event.