Data-in for burst addresses 1 and 3
The following are registered on the rising edge of the K# clock:

Byte writes for burst addresses 2 and 4

概觀

The 18Mb IS61QDPB451236C/C1/C2 and IS61QDPB41M18C/C1/C2
are synchronous, high-performance CMOS static random access
memory (SRAM) devices.
These SRAMs have separate I/Os, eliminating the need for high-speed
bus turnaround. The rising edge of K clock initiates the read/write
operation, and all internal operations are self-timed. Refer to the Timing
Reference Diagram for Truth Table for a description of the basic
operations of these QUADP (Burst of 4) SRAMs.
Read and write addresses are registered on alternating rising edges of
the K clock. Reads and writes are performed in double data rate.
The following are registered internally on the rising edge of the
K clock: