Feasibility and implementation study of a high-throughput DVB-S2 LDPC Decoder on FPGA architecture

Autor/a:

Boistault, Etienne

Otros autores:

Ruiz Boqué, Sílvia; Combaz, Solène

Abstract:

[ENGLISH] The aim of this project consists in the study of the error correcting codes LDPC (Low Density Parity Check) in the context of the DVB-S2 standard (Digital Video Broadcasting for Satellite version 2) in order to design a functional high-throughput decoder running on a FPGA architecture. This system would be integrated to a High Data rate Receiver; a product manufactured by Zodiac Data Systems, a French aerospace company specialized in embedded systems. This project has been divided in four parts: the first one being a literature review of the LDPC codes, DVB-S2 standard and implementations ideas. The second phase was the development of a simulator in C/C++ using Microsoft Visual Studio 6.0. Thirdly, a study has been carried out in order to develop a design that will fit inside the system, following the constraints of the FPGA architecture. In parallel, changes have been made to the simulator for it to be as close as possible to the final design and obtain reference curves. Finally, the implementation of the decoder subsystem has been started in a FPGA using the Xilinx ISE program which works with VHDL language. This document is divided into four chapters, each one explaining a specific aspect of the project. The first chapter is an introduction to the LDPC codes, to the DVB-S2 standard and to the field-programmable gate array (FPGA). Chapter two is a comprehensive study of LDPC codes and an explained selection of development choices for the implementation of the decoding along with curves obtained thanks to early versions of the simulator. The third chapter provides the details of the adaptations of the design to fit in a FPGA environment. The last chapter is focused, on the development of the FPGA blocks to execute the decoding following the specifications.