No accurate documentation for this particular DRAM controller exists in public access. But it is suspected that Allwinner uses one of the revisions of Synopsys DesignWare DDR2/3-Lite Memory Controller IP (MCTL) combined with DDR2/3-Lite PHY IP in A10/A13/A20. Also this DRAM controller apparently has siblings in Rockchip RK29XX, RK30XX and TI KeyStone2 hardware, which have some documentation and some bits of kernel and bootloader sources available in the Internet. Not to mention the original Allwinner boot0 bootloader sources and the suspend support code from the linux-sunxi kernel. This provides enough hints for finding out how the DRAM controller actually works by checking various bits of information via the trial and error method.

This DRAM controller generation is similar to the one found in Xilinx Zynq UltraScale+ SoCs, but with reduced features, maybe an older version. The PHY has more differences, some parts are still similar to RK30xx and TI KeyStone2.

Some initial register dumps from A23 reveal that there are significant differences between the A31 and A23 dram controllers. There are dram controller register defines in the a23 suspend code in this code (dram_init) the SPL parameters are read and stored into structure defined here without using the definition.

The latest DRAM controller is similar to the previous sun9i generation, but with completely different register layout and some features removed. Controller and PHY registers got combined into a single block, with no particular or meaningful order.

There are some small differences between the various SoCs, especially in the PHYs, but overall it looks like they all use the same generation of DRAM controller.
It seems like H5 doesn't have a BIST anymore, also some data training regsiters vanished.