topic Re: place and route failed in Implementationhttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019471#M26292
<P>what are you doing with unisim.vcomponents.all</P>
<P>&nbsp;</P>
<P>You decalre it at the top inside pragma synthesis of f/ on,</P>
<P>then re definfe it again so synthesis can see it !</P>
<P>&nbsp;</P>Fri, 13 Sep 2019 12:14:17 GMTdrjohnsmith2019-09-13T12:14:17Zplace and route failedhttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019361#M26286
<P><I>hi</I>, please solve my error as&nbsp;</P><P><BR />Process "Place &amp; Route" failed. please find attached file for this</P>Fri, 13 Sep 2019 07:13:53 GMThttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019361#M26286harinatha.reddy@eldaas.com2019-09-13T07:13:53ZRe: place and route failedhttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019369#M26287
<P>There is little we can help with with only the error message.&nbsp;</P><P>Try increasing the P&amp;R effort.</P><P>what about the previous warnings on signals with no driver? Are these your signals or from the wrapped core?&nbsp;</P>Fri, 13 Sep 2019 07:32:31 GMThttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019369#M26287archangel-lightworks2019-09-13T07:32:31ZRe: place and route failedhttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019383#M26288
How does the simulation look ?<BR /> You have a bunch of logic with no drivers reported. <BR /> thats not good start<BR /><BR />Whats its telling you is you either have code that has no input or output some where, and as such is being optimised away by the placer.<BR />Or you have tried to do something that this chip cant do, like connect an internal clock net to an output , or drive a pin that can not be driven<BR /><BR />Always simulate first. That gets rid of the first group of problems, and leaves you with the simpler second group.<BR />Fri, 13 Sep 2019 08:36:19 GMThttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019383#M26288drjohnsmith2019-09-13T08:36:19ZRe: place and route failedhttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019467#M26289
<P>that are signals with no driver</P>Fri, 13 Sep 2019 12:07:03 GMThttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019467#M26289harinatha.reddy@eldaas.com2019-09-13T12:07:03ZRe: place and route failedhttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019468#M26290
<P>ya i simulated. there is no problem in simulation</P>Fri, 13 Sep 2019 12:08:25 GMThttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019468#M26290harinatha.reddy@eldaas.com2019-09-13T12:08:25ZRe: place and route failedhttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019470#M26291
<P>Its time to share your project with us so we can help further,</P>
<P>&nbsp;</P>Fri, 13 Sep 2019 12:11:52 GMThttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019470#M26291drjohnsmith2019-09-13T12:11:52ZRe: place and route failedhttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019471#M26292
<P>what are you doing with unisim.vcomponents.all</P>
<P>&nbsp;</P>
<P>You decalre it at the top inside pragma synthesis of f/ on,</P>
<P>then re definfe it again so synthesis can see it !</P>
<P>&nbsp;</P>Fri, 13 Sep 2019 12:14:17 GMThttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019471#M26292drjohnsmith2019-09-13T12:14:17ZRe: place and route failedhttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019480#M26293
<P>ok please find the attached project file file. i have on doubt in chipscope inserter, i am anable to get all topmodule ports can anyone help me how to get all ports in chipscope.if any reference designs for pci32 are there please provide me&nbsp;</P>Fri, 13 Sep 2019 12:34:29 GMThttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019480#M26293harinatha.reddy@eldaas.com2019-09-13T12:34:29ZRe: place and route failedhttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019484#M26294
<P>looks like the complete PCI core is empty !</P>
<P>could it be that you have no purchased licence for the core ?</P>
<P>&nbsp;</P>Fri, 13 Sep 2019 12:47:19 GMThttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019484#M26294drjohnsmith2019-09-13T12:47:19ZRe: place and route failedhttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019488#M26295
<P><LI-USER uid="9736"></LI-USER>&nbsp;</P><P>LoL</P><P>&nbsp;</P>Fri, 13 Sep 2019 12:59:31 GMThttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019488#M26295archangel-lightworks2019-09-13T12:59:31ZRe: place and route failedhttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019492#M26296
<P>i haved purchased license. but i am newly using chipscope. so please provide me any references how to use chipscope analyser</P>Fri, 13 Sep 2019 13:16:29 GMThttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019492#M26296harinatha.reddy@eldaas.com2019-09-13T13:16:29ZRe: place and route failedhttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019518#M26297
<P>No chipscope in the files you shared,</P>
<P>so that can't be your problem...</P>
<P>Is this a new problem ?</P>
<P>If so please lcose this forum, and open a new one.</P>
<P>&nbsp;</P>Fri, 13 Sep 2019 14:31:53 GMThttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019518#M26297drjohnsmith2019-09-13T14:31:53ZRe: place and route failedhttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019721#M26298
<P>chipscope is there sir in that files. it is Top_CDC.cdc file. in topmodule project it is there</P>Sat, 14 Sep 2019 03:38:00 GMThttps://forums.xilinx.com/t5/Implementation/place-and-route-failed/m-p/1019721#M26298harinatha.reddy@eldaas.com2019-09-14T03:38:00Z