There is a very useful post detailing configuration changes to support external PCIe reference clock that can be found here: i.MX6Q: Using an external reference for PCIe. Unfortunately, this post doesn't address the impact this has on ethernet functionality e.g. can ethernet still be used if PLL6 is bypassed? Figure 10-3 in the DL RM seems to imply that Div_enet output will be incorrect (and can't possibly ever be 125MHz).