This is actual hardware (clone), as opposed to software (emulators), such
as the ts10 or
SIMH or
KLH10 programs.

This project grow out of multiple of my interests:

My decades old interest in making an computer myself. Originally an
self-build microprocessor-based system. Then an self-designed processor
from 74xx logic. Then ideas of using an large PAL (PAL64R32)

My 10 year old interest in programmable logic (then knew about PALs,
saw early Xilinx, then Algotronix CAL1024) and using it for an own
microprocessor. Re-awakend by multiple magazine articles on how far
FPGAs have come

An interest in the PDP-10 stemming from reading a lot about it in
the Jargon File. And
also an general interest in old DEC computers from growing up on PDP-11
and VAX machines

The announcement of Doug Conroy's
PDP-8/X clone on
20000819, that brought all the previous parts together, igniting
interest in making an processor

Reading about Jan Gray's
xr16 CPU Core
and how to implement single cycle RISC machines in FPGAs on 20000822,
convincing me that one can make fast microprocessors that are actually
usable for daily work, not just toy/experiment/teaching systems

Frustration with the (then) non-availability of PDP-10 emulators
(ts10 was then "permanently near finished" with no code out, SIMH
pdp10 mode was not yet announced and so unknown to be in the making,
KLH10 was known to exist but regarded as "lost inside DEC jailled by
copyright")

Deciding on 20001230 that making an other PDP-8 (with no own PDP-8
background or software) or an PDP-11 (with PDP-11 Unix to run, but
already SIMH capable of doing that at more then original speed) or an
own processor design (with no software to run) would just be toy
projects. So better go for making an PDP-10, which may one day run an
today usable OS (be that native TOPS-20 or Linux or NetBSD (which is
being ported))

Since the project start the situation has changed by the appearance/release
of the 3 emulators (regarded by many, me inclusive, as PDP-10 microcode
implementations running on Intel micromachine). But a real hardware PDP-10
is still attractive.
Also Doug Conroy has
announced his
expected 10 clone project, but this is a small/toy microcoded machine
roughly at original speed, not the usable 10-30 times original, that this
project can grow to.
Also this project has spawned an
FPGA Programming Tools sister project called VirtexTools, and has thus
become the test case for the tools developed in that.

For more info on this project read the README file.
For some questions people have asked or may ask read the FAQ
list.

Addendum 2003.12.24: This project and VirtexTools canceled on
2003.12.24. After 1 month of forced break (HD crash, system rebuild) and
1.5 months since then of doing nothing on either this project or on
VirtexTools, I have come the the conclusion that I have lost all interest
in both of them. Reasons are many:

FPGA market pricing has an massive ramp between near identical
sized $50 and $500 Parts. When I started this project the ramp was at
200kGates (XC2S200). I wanted to stay underneath that ramp. So a 36bit
CISC needed to be done at LUT-by-LUT "assembler" programming level.
Also FPGA HLLs are awfull anyway, further reason to avoid them

This meant using JBits+Java, which limits to using single-family
Spartan-II parts, and unsure extension to future families (definitive
no Spartan-IIE, possibly will have Spartan-III). Also troubles with
JBits, and not fixable as it is closed source software

Making an own open source LUT oriented Compiler
(VirtexTools) delays
Project. And runs into problems with closed bit streams. Reverse
engineering bit streams is a lot of work, would delay even more
(years!), and reverse engineering needs redoing for other FPGA families
(every few years), and likely no docs for that

Until reverse engineering and own tools done, the price ramp will
have moved to large enough FPGAs to use HLLs. And they are easier to
use, faster, portable, vendor independant, no time reverse engineering.
So if FPGA, wait until then and redo in HLL. So scratch code done
sofar. So end project in its current low-level form. Back to zero

But until then also x86+emulator as fast as my chip could ever be.
Even underclocked fanless miniature VIA parts will be equal fast and
low-power and small. And far less work, just install existing emulator.
And no Java or awfull FPGA HLLs, just possibly adapt C code. Even
todays top x86 are faster than the originals, and as fast as my first
iteration would be, and their speed grows "automatically" with new x86
chips. And I could start installing today, upgrade later

Even getting rid of PC architecture (is anyway hidden under emulator
and C compiler) can be had easier by building some ARM based board with
an emulator built in. For an computer architecture independant of PC
manufacturers whims (DRM and such crap), even if not powerfull, just
as contingency, is way better using an ARM (or even non-PC x86) board,
that single-source closed FPGAs. Even 74(x)xx+PALs would be better than
FPGAs, despite totally underpowered. So no FPGA project at all

Switching from FPGA to emulator (on an 32bit CPU) makes the 36bit
PDP-10 (chosen because simple for FPGA) unattractive (32+4 or 2*18 bit
dual computation). OTOH emulators make the more complex VAX possible
(and faster single computation). And I know its native VMS (unlike
TOPS-10 or TOPS-20). And early Unix also used these. So if restart with
emulator do an VAX. So no PDP-10 project at all

Also my dislike of the x86 CPU is waning, so I could could just build
an non-PC architecture x86, and get that up to full speed. So no other
high-power to-use-daily CPU FPGA or emulation project at all

Making an toy CPU just for the act of making one is too much drudge
work to be fun (with FPGAs). And while small systems, such as PDP-1
(can run Spacewar) or PDP-8 (simplest) or even an 2*18bit PDP-10, will
today fit $50 FPGAs using HLLs, emulation is way fast enough for toys.
And my interest in layouting any CPU is largly satisfied from how far I
came in this first go. So no FPGA CPU at all

Only interesting needs-to-be-hardware CPU project remaining would be
to recreate an CPU+mem+frontpannel, wire wrapping 74(x)xx+PAL parts or
even own transistor modules, all hardware, no software tool (not even
PCB layout) frustration getting in the way. That would need to be
simple (PDP-12) to reduce design time, solder work and cost. But
collecting/restoring originals would be more usefull. And both of these
suffer from storage space problems

Using own CPU to help teach machine code and assembler is not worth
making an CPU either. Better use PDP-8 or PDP-11, or DOSemu (8088 PC),
or C64 emulator with fitting software for that. If non-PC hardware
wanted, put any of these small emulators in an flash based uC, and wire
its IO ports as external memory and IO bus. Or if wanting to show
internal CPU operation, go for the most transparent wire wrap PDP-8
recreation

The only remaining reason for this project is just as test case for
VirtexTools (as I have used it for the last year). This leads to no
extensions (as done none in last year) unless I need new test cases.
And even then other test cases may be more effective. And test case for
VirtexTools is also only worth it, so long I have an interest in making
them, which has now also ceased, due to large problems there. See thats
cancelation

This site and all work done up until now remains online, in case
someone wants to continue this project, copy "Current" and work on

Project Status

For the full details of done/doing/todo of the project best read the
Logfile. A short excerpt from it is here:

Instruction unit 100ffffmmboolean logic,
a set of 4-input 2-select muxes, driven by the 2 bits to be processed,
selecting from the 4 instruction bits that specify the operation

Milestone 2 (from 2001.12.29), aim for universalising system, and adding
an fairly simple but different instruction group (arithmetic testing):

Massive overhaul of central infrastructure to work with
multiple instruction units, provide immediate values from MA without
wasting an cycle, use faster distributed arithmetic registers (the
present AR becomes a temporary register for for the first of two memory
operands

Instruction unit 011tttmmmarithmetic testing,
an ALU for all the comparing/increment/decrement stuff, and an
zero/nonzero detector to control conditional skipping or jumping

Fast memory (16 words, at address 000..017) and multiplexer
to select between this and normal memory (which has been moved to
address 020..057)

Instruction unit 101tootmmhalf word,
an half word swap mux, and an unchanged/zero/one/extend modifier,
followed by an mux that select which of these to take

Instruction unit 110ooammabit testing,
an half word swap mux for the test pattern, an ALU for all the
nothing/zero/complement/one modification, and the test pattern "AND"
and zero/nonzero detector to control conditional skipping

Hardware to Run on

FPGA designs are nothing without hardware to run on. As they do not run on
an PC, like normal software (such as emulators), we need an FPGA based
board to run them on.

Normally FPGA developement ist done on prototype boards, which are just an
FPGA plus power supply and programming circuit on an board, with the IOs
run out to headers or prototyping area. These are prototype boards I have
looked into, to run my stuff on:

XSV Virtex Prototyping
Board has enough pins, as pinout analysis
shows, but too many are already in use, none free for wide 18/36bit
memory (existing memory is 16bit) or for missing hard disk interface.
Also requires programming its XC95108 CPLD to program FPGA or use RS23
or LPT

BurchED has many free pins. No
pinout analysis, but it seems to be all IO pins free from pictures. But
can only use 8pin OT-PROMs, not EEPROMs. And the manufacturer obsoletes
old offerings (such the old XC2S200 needed for my tools) as soon as now
ones appear (XC2S300E which is not supported), which makes it bad for
other people wanting to build copies of my system, which requires
an steady board supply

Board
Module EVALXC2S/XCV/XCVE-HQ240 an nice flexible board with IO pins
on the edge and EEPROM sockets. But very expensive, as it uses XCV
chips and in particular the required (large and complex) power supply.
No pinout analysis, but it seems to be all IO pins free, possibly some
with special plugs on them

Trenz
TE-XC2S Spartan-II Development System an nice board, more in my
price range. With EEPROM support, programming circuits built in, 4
identical module sockets. But 2 sockets each are on front and back of
board, which makes it impossible to use it as "large component" on an
other board. No pinout analysis, but it seems to be all IO pins
free

Quickstart
QST0201 is similar to the Trenz above. But all sockets on front
(and announced both-side usable in next revision), and at edges, so
usable as an large component. And manufacturer is interested in making
front pannels (has an interest in PDP-8/10/11 cloning). No pinout
analysis, but manufacturer claims all IO pins free (makes point that
pre-used pins is equal to lossed pins)

But ultimatively I will want this to run on an custom board for FPGA PCs.
For this I have started an separate
FPGA PC Project