Taiwan embeds ReRAM in 28-nm process

LONDON – The ability to embed resistive RAM (ReRAM) into mainstream logic process technology could have major implications for the design of system-on-chip, and foundry chip maker Taiwan Semiconductor Manufacturing Co. is keeping tabs on the emerging capability.

One of the more intriguing papers listed in the advance program for the 2012 International Electron Devices Meeting in December is authored by a research team from National Tsing-Hua University (Hsinchu, Taiwan) that is also affiliated with TSMC.

The abstract to the paper, titled "High-K metal gate contact RRAM (CRRAM) in
pure 28-nm CMOS logic process," states that a
contact RRAM (CRRAM) cell has been realized in a HKMG 28-nm CMOS logic
process without the use of any additional masking or process steps. This was done using a 35-nm by 35-nm contact hole.

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No additional information was released in advance of the conference, but online searches reveals that the Tsing-Hua research team has previously worked with titanium-oxide based ReRAMs, typically in a TiN/TiON/SiO2 stacked arrangement sitting at the base of a tungsten contact plug attached to the drain of a conventional planar MOSFET.

The design is said to be particularly compact compared with other types of ReRAM arrays and compatible with conventional logic manufacturing processes. As recently as 2010, the team was working on a 1T-plus-1R ReRAM in 90-nm CMOS logic and claiming 1 million read-write cycle endurance.

The amount of memory included on system chips is growing and becoming increasingly responsible for much of the power consumption. The facility to hold data in dense non-volatile memory on a SoC--rather than in power consuming SRAM for even a few processor cycles--could drive power savings in leading-edge manufacturing.

The fact that the CRRAM can be implemented without any addition to the processing deck indicates a potentially easy introduction into chip manufacturing. However the fact that the IEDM paper is still essentially academic and written at the memory-cell level rather than at the array level indicates that more R&D is to be done. A demonstration or projection of considerably higher endurance would also be desirable.

The paper also suggests a topic to watch for at another key chip gathering, the International Solid States Circuits Conference in February.