Thursday, 17 January 2013

SPICE Models No Longer Only A Foundry’s Worry

SPICE Models Play a Critical Role in Both Modeling and Design Communities

Circuit
designers work with foundry libraries to evaluate a foundry process
before they run real circuit designs. It, therefore, becomes necessary
to understand the models and use them properly. Complexities of modern
libraries have made it inefficient or almost impossible to understand
them by browsing into the files.

A library can easily contain
many different sections besides core models in a macro (sub-circuit)
format, such as multiple corner model sections, statistical model
sections, mismatch model components, models for layout dependent
effects and reliability models. Without a good understanding of those
details, simulations by combining those model sections may lead to
inaccurate results.

Second, foundry models often are not built
for specific applications. Design companies are investing in SPICE
models by doing model validations, customizing models for specific
needs or even building their own models. High-end systems-on-chip
(SoCs) are now integrating more functionalities and may have different
operation modes, evaluated by performance, power, area, lifetime, cost
(yield) and time to market.

Design specifications are tougher,
but the room to maneuver has shrunk. One set of generic models can’t
meet the requirements for all different applications. Thus, it’s
worthwhile for design companies to identify the real needs of their
applications, then work with foundries or third parties or build their
own capabilities to make model libraries more application specific and
provide more value for their designs.

Third, the key motivation
for a circuit designer to understand foundry model libraries is the
impact of process variations on circuit performance and yield. Although
process engineers have tried different ways to mitigate variation
sources during manufacturing, some remain in a design that are
fundamental and must be managed during different design stages,
including global and local random variations or LDE.

Designers
can only cross their fingers if they do not know the possible results
before tapeout. Modeling engineers have figured out ways to model those
systematic and random variation effects. The next step is to apply
that information and analyze the impact to a design.

Strain
engineering improves device performance, but leads to the strong layout
dependence of device characteristics. Designers then need to consider
the impact of LDE during pre-layout design, layout design, LVS
extraction and post-layout verifications. Understanding the LDE based
on the models would help designers better optimize area versus
performance, and reduce differences between pre- and post-layout
designs to shorten design time.

Increasing random variations,
especially the local mismatch for paired transistors, affect the final
chip yield and performance. Traditional PVT analysis and selective
Monte Carlo analysis give limited information that can help achieve
chip’s functionalities, but not the possible yield or performance
distributions.

A reliable and practical design for yield (DFY)
flow with fast and accurate statistical simulation engine is required.
Moreover, before using DFY tools for yield analysis targeting yield and
performance trade-off, designers need to know how corner models and
statistical models are defined. Otherwise analysis results, based on
improper use of the variation models, will offer the wrong direction
for design optimizations.