Multistandard PHY Control Processor

CEVA-X2 is primarily aimed at Physical Layer Control of high-end multi-carrier and multi-standard cellular baseband.

The CEVA-X2 has been specifically designed to tackle the huge PHY control complexity increase of LTE-Advanced Pro which includes Rel.13 multi-carrier and multi-standard handsets. PHY Control task challenges include:

• Support capacity increase up to 1.2Gbps in Rel.13 through the aggregation of 5 carriers and the use of MIMO 4x4 and 256 QAM. Control performance scales with the number of carriers and the PHY controller also needs to perform measurements, calibration and other processing functions per carrier,
• Support Dual-Connectivity to improve offload to Small-Cells and handle concurrent baseband connectivity to both macro and small cells,
• Merge efficiently Multi-RAT modems (LTE-A, 3G, TD-SCDMA, 2G) into a single unified modem to support dual SIMs, concurrent data over LTE-A and voice over 2G or 3G until VoLTE is widely deployed. Such a feature very low latency task switch to schedule modems concurrently,
• Control the whole modem datapath at the system level with its multiple DSPs and UL/DL coprocessors and HW accelerators, without Controller overhead. This requires sophisticated mechanisms such as Queue and Buffer Managers, QoS, Flow Control, to automatically schedule PHY components under ultra-low latency with minimal overhead,
• VoLTE EVS requires 5 to 10 times the complexity (performance and memory footprint) of previous generation voice codecs,
• Battery life needs to remain competitive despite the huge complexity increase.

Features

CEVA-X2 Key features

VLIW/SIMD architecture

10 stage pipeline

128 bit memory bandwidth

4.0 Coremark/MHz

Four-MAC 16x16 per cycle

64-SIMD Fixed-Point Operations

Up to two IEEE Single-Precision Floating-Point Operations

1.5GHz operating frequency in 16nm FF

Instruction and Data Caches

Branch Target Buffer

CEVA-Connect Technology to schedule control and data planes of Hardware Accelerators

Controller features

Four scalar operations per cycle

Zero latency ISA

Static branch prediction

Optional dynamic branch prediction

32-bit HW division and multiplication

Ultra-fast context switch

Supervisor and User modes

Semaphores

DSP features

Two SPU (Scalar Processing Unit)

Four 16x16 MAC per cycle

Two 32x32 MAC per cycle

64-bit SIMD processing

8/16/32/64 bit data type support

8/16/32/64 bit ALU operations

Four 16-bit operations per cycle

Two 32-bit operations per cycle

Two 64-bit operations per cycle

Optional single-precision IEEE floating point in each SPU

Loop buffer

System features

Data Cache

2-Way or 4-Way set-associative cache

Write-through and write-back policies

Non-blocking read and write on cache miss

Hardware and software pre-fetch capabilities

Instruction Cache

2-Way or 4-Way set-associative cache

Non-blocking read on cache miss

Hardware and software pre-fetch capabilities

CEVA-Connect

Offload the processor with dedicated HW control and data planes

Hardware queue and buffer managers for controlling the data flow in the PHY

Intelligent scheduling with high QoS and very low latency

Data traffic management

Special interfaces to connect multiple accelerators / DSP

High throughput system interfaces

Exceptional power efficiency

Incorporates Power Scaling Unit (PSU 2.0)

Enhanced power-optimized pipeline

Optimized for battery-operated and stationary devices

Scalable and configurable baseband control DSP architecture for use in advanced multi-RAT LTE modems through different processors, configurations and optional modules