(38D5) Does SOUT2 goes to high impedance even P51/SOUT2 set to CMOS output?

Question:

(Serial Interface) According the comment in the serial I/O2 timing figure in datasheet and user's manual, "When the internal clock is selected as the transfer clock, the SOUT2 pin goes to high impedance after transfer is completed." Does the SOUT2 pin go to high impedance even when the P45/SOUT2 P-channel output disable bit in the serial I/O2 control register is set to CMOS output (in output mode)? Also, what is the timing of the transition to high impedance? [2005/06/09]

Answer:

When the internal is selected as the transfer clock, the SOUT2 pin goes to high impedance regardless of the P45/SOUT2 P-channel output disable bit setting. In regards to timing, the SOUT2 pin goes to high impedance a half-cycle of the transfer clock after the last rise of the transfer clock. (#104946)