Contact Dr. Ron Lasky

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Since 2002 SMTA has had an SMT Process Engineer Certification Program that was developed by Jim Hall, Phil Zarrow and me. Some folks are a little nervous about taking the workshop and exam. In light of this concern, I have been asked by the Ohio SMTA chapter to give a 5 hour workshop on the types of problems one would be expected to solve. I have proposed a list of problems to be covered in the workshop. Here is a typical one that I might use. See if you can do it.

Component placement is the limiting process in an SMT line for throughput. Throughput (cycle time) is now one board every 50 seconds, when the line is running. There is one chipshooter (CS) and one flexible placer (FP). The bill of material (BOM) is 300 passives, 24 SICs (simple ICs), 8 CICs (complex ICs). The chipshooter is taking 50 seconds and the flex placer 20 seconds. All passives are being placed by the CS. The FP places CICs in one second. It places passives and SICs at the same rate.

1. Maximum throughput will be obtained when the CS and FP take the same amount of time. This can be accomplished by moving passives from the CS to the FP for placement.

a. What is the minimum cycle time if the line is balanced?

b. How many passives were moved to the FP to achieve this cycle time?

Note: We assume all other processes can keep up with the new and improved cycle time.

I will publish the solution in a few days. I expect to be giving this workshop quite frequently in the future.

Solution:

The FP takes 20 seconds to place the SICs and the CICs. The 8 CICs take 8 seconds, so the 24 SICs must take 12 seconds. Hence, the placement rate for SICs is 2 per second. The CS places 300 passives in 50 seconds, so it places 6 passives a second. Since the CS takes 50 seconds, to balance the line we must move passives to the FP. Our goal is that the time spent by the CS is the same as the FP. Let us assume that the number of passives we have to move to the CS is x, then time balancing can be expressed by the equation: