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Abstract

PURPOSE: To suppress the allocation of address space to an interruption address to only one i.e. an absolute minimum by attaching key information and interruption information on an interruption request, and preparing a master key in the key information.

CONSTITUTION: When the interruption request or an inter-processor communication request is generated in processor modules 1, 2,..., the interruption address is outputted to an address bus 10, and simultaneously, the key information and information(interruption information) with respect to the module in which an interruption cause and the interruption request are generated, etc., are outputted to a data bus 20. The key information stored in a key register 13 is compared with that outputted to the data bus 20 by a comparator 14, and only when the key information coincide with each other as a result of comparison, an interruption signal is inputted to processors 11, 21,.... Therefore, the module of an interruption destination can be specified by the key information not depending on an address. Thereby, the allocation of the address space to the interruption address can be minimized.

COPYRIGHT: (C)1992,JPO&Japio

JP20927490A1990-08-091990-08-09Interruption system for multi-processor system
PendingJPH0496167A
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