I had to lookup the definition of "lead" and "lag" networks: the "lead-lag compensator" is a control theory concept to describe a pole-zero pair network (eg. RL cct.) used to change frequency response.
Y/X = (s-z)/(s-p)
I'm guessing that, in your case, a "lead network" is a simple pole and a "lag" network is a simple zero; you'll want to get that confirmed (I can justify the other way around, too).

http://en.wikipedia.org/wiki/Bode_plot#Straight-line_amplitude_plot
Simple poles introduce a -20dB/dec slope; simple zeros introduce +20dB/dec. You'll have to start at the mid-point, since that's the only place you know absolute gain (238). As for phase, simple poles introduce a -45deg/dec slope, starting 1 dec before the knee-freq. and stopping 1 dec after (90 deg phase change); simple zeros introduce +45deg/dec with the same conditions.

It looks like you're doing this for a single-transistor CE amp. This means 2 "bypass capacitor" networks: one at the input, one and the output.

It would help forum members if you perhaps provided a schematic from which the problem definition arises.

Otherwise we are obliged to speculate about the implied meaning of "Bypass capacitor network: f = .05Hz"

Presumably this latter statement might be applied to an emitter bypass capacitance - as tyblu points out that the problem seems to be related to a CE amplifier design.

Whilst brevity is appreciated, a reasonable statement of the problem is also helpful. I suspect AAC members are put off by the information "drip feed" approach and this can lead to delays in seeing your questions successfully resolved.

Keep in mind also that posting in the homework forum means you are expected to provide some statement of your attempted solution (however error prone), rather than the rather overused statement about not knowing what to do next.