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Cache Line Replacement The cache memory is always smaller than the main memory (else why have a cache?). For this reason, it is often the case that a memory block being placed into the cache must replace a memory block already there. The process is called cache replacement and the method to choose the block to replace is the cache replacement policy.

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Example of a Cache Line Consider a cache memory with 256 (2 8 ) cache lines, each holding 16 (2 4 ) bytes. A 24-bit address would be divided as follows: A 4-bit offset into the cache line A 20-bit memory block tag The memory block tag is required because a number of different memory blocks can be mapped into the same cache line.

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Memory Tag 0xAB712 In our example that assumes a 24-bit memory address and a 16-byte cache line, the 20-bit memory tag 0xAB712 references a block containing addresses 0xAB7120 – 0xAB712F. For 256 (2 8 ) cache lines and a direct-mapped cache, this block would go to line 0x12. The cache tag would be 0xAB7. We can reconstruct the memory tag from the cache tag and the cache line number.

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Chapter 5 Large and Fast: Exploiting Memory Hierarchy 6 Replacement Policy Direct mapped: no choice Set associative Prefer non-valid entry, if there is one Otherwise, choose among entries in the set Least-recently used (LRU) Choose the one unused for the longest time Simple for 2-way, manageable for 4-way, too hard beyond that Random Gives approximately the same performance as LRU for high associativity

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The Dirty Bit and Replacement Consider a cache line. If the valid bit V = 0, no data has ever been placed in the cache line. This is a great place to put a new block. (This does not apply to direct mapped caches). In some cache organizations, the dirty bit can be used to select the cache line to replace if all cache lines have V = 1. If a cache line has D = 0 (is not dirty), it is not necessary to write its contents back to main memory in order to avoid data loss.

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Replacement for Cache Line 0x12 Suppose memory block 0xAB712 is located in cache line 0x12 of a cache with 256 cache lines. Now the CPU references memory block 0xCD112. This must also go into line 0x12. A direct-mapped cache contains only one block per cache line, so block 0xAB712 is replaced. If the block is dirty, it must be written back to main memory before being overwritten.

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Replacement for Set Associativity In an N-way set associative memory, each cache line can hold N memory blocks with their tags. Suppose memory block 0xCD112 must be read into cache line 0x12 and is not already there. Check if any of the four sets has V = 0. If so, there are no data in it. Read into that set. The next choice is a set with D = 0. A valid set that is not dirty can be simply overwritten. Otherwise, use some other way to pick the set.

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Writing to a Cache Suppose that the CPU writes to memory. The data written will be sent to the cache. What happens next depends on whether or not the target memory block is present in the cache. If the block is present, there is a hit. On a hit, the dirty bit for the block is set: D = 1. If the block is not present, a block is chosen for replacement, and the target block is read into the cache. The write proceeds and D = 1.

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Chapter 5 Large and Fast: Exploiting Memory Hierarchy 13 Sources of Misses Compulsory misses (aka cold start misses) First access to a block Capacity misses Due to finite cache size A replaced block is later accessed again Conflict misses (aka collision misses) In a non-fully associative cache Due to competition for entries in a set Would not occur in a fully associative cache of the same total size

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Chapter 5 Large and Fast: Exploiting Memory Hierarchy 14 Write-Through On data-write hit, could just update the block in cache But then cache and memory would be inconsistent Write through: also update memory But makes writes take longer e.g., if base CPI = 1, 10% of instructions are stores, write to memory takes 100 cycles Effective CPI = ×100 = 11 Solution: write buffer Holds data waiting to be written to memory CPU continues immediately Only stalls on write if write buffer is already full

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Chapter 5 Large and Fast: Exploiting Memory Hierarchy 15 Write-Back Alternative: On data-write hit, just update the block in cache Keep track of whether each block is dirty When a dirty block is replaced Write it back to memory Can use a write buffer to allow replacing block to be read first

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The Write Buffer This buffer exists between the L2 cache and main memory. It is used for memory writes.

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What is Written to the Buffer? Consider our previous example, with the L2 cache organized into 16-byte cache lines. Suppose the byte at address 0xAB7129 is written. The value is put into the write buffer. If only the byte itself is put into the buffer, then its address 0xAB7129 is also put there, in order to identify where to put the byte. If the entire cache line is written to the buffer, then only the memory tag 0xAB712 is needed.

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Chapter 5 Large and Fast: Exploiting Memory Hierarchy 18 Write Allocation What should happen on a write miss? Alternatives for write-through Allocate on miss: fetch the block Write around: dont fetch the block Since programs often write a whole block before reading it (e.g., initialization) For write-back Usually fetch the block

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Problems with Virtually Mapped Caches Cache misses have to invoke the virtual memory system (more on that later). This is not a problem. One problem with virtual mapping is that the translation from virtual addresses to physical addresses varies between processes. This is called the aliasing problem. A solution is to extend the virtual address by a process id.