Aldec's Active-HDL helps manage complex FPGA projects

The folks from Aldec have announced the immediate availability of Active-HDL 9.2, an HDL-based FPGA Design and Simulation solution that now offers flexible file management to allow engineers to effortlessly manage complex FPGA projects.

This powerful concept enables designers to create project structures compatible with FPGA synthesis and place and route tools – allowing one common project structure to be used between multiple vendor tools.

Team-based design features are also interwoven with the new file management feature to allow the design environment to be set up quickly, even when team members work from multiple locations.

Simulation performanceActive-HDL continues to dominate the FPGA market with powerful simulation performance, debugging tools and language support for VHDL 2008 and SystemVerilog(Design). Continued simulation performance optimizations from release to release enable users to benefit from faster simulation as the size of FPGA designs continues to grow.

Superior automationAs more designs are reused, Active-HDL now offers a powerful Net-Optimizer feature that allows the auto-routing of nets with the block diagram editor and removes all redundant net segments to deliver cleaner designs for documentation and visualization. Active-HDL 9.2 also introduces Mouse Gestures to improve the productivity of designers by enabling the execution of common tasks with a simple movement of the mouse.

Learn more…Click Here for additional information about Active-HDL 9.2 including a What’s New presentation, Resources, and free Evaluation Download. Popular Active-HDL videos are also available on YouTube by Clicking Here.

Pricing and availabilityCustomers with a current maintenance contract are eligible to update to the latest release at no cost. New customers and customers without current maintenance contracts are invited to contact a local Aldec Distributor for more information.

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