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Description

This is a fully pipelined implementation of the AES (rijndael) cipher with 128 bit keysize. Post place and route logs show the maximum speed to be 333 MHz when implemented on a Virtex-5 LX50T speed grade -1 FPGA with 45% LUT utilization and 27% register utilization. This comes out to a maximum throughput of ~ 42Gbps with an average of 1 encryption every cycle. The overall design has a latency of 30 clock cycles. A brief documentation is available
here
.

This core has been verified to be correct by the NIST designed Known Answer Tests (KAT).

P.S. If you download the project and find it to be useful, please do drop me a mail at my address
subhasis256@opencores.org
. I will appreciate it very much. :-)