[Gumstix-users] Setting DSP clock frequency on DM3730

I am having issues setting the clock frequency on a DM3730 project running
Angstrom and using DSPLink. I have done significant profiling and found
that the DSP clock is running at 260MHz. I have tried adjusting cpuFreq on
the arm as well as rebuilding DSPLink multiple times with different
configurations and cannot get the DSP to run at higher clock frequencies.
We are currently trying to run arm at 1GHz and have the DSP run at 800MHz to
prove out that max through put we can get on a data processing application
with this processor. I understand this will damage the life of the part but
we are currently in an exercise to learn what is possible. We are running
Angstrom built using Yocto project on a Overo Firestorm. Any advice on how
to set the DSP clock frequency for testing would be greatly appreciated.
Thanks
Patrick
--
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I am having issues setting the clock frequency on a DM3730 project running
Angstrom and using DSPLink. I have done significant profiling and found
that the DSP clock is running at 260MHz. I have tried adjusting cpuFreq on
the arm as well as rebuilding DSPLink multiple times with different
configurations and cannot get the DSP to run at higher clock frequencies.
We are currently trying to run arm at 1GHz and have the DSP run at 800MHz to
prove out that max through put we can get on a data processing application
with this processor. I understand this will damage the life of the part but
we are currently in an exercise to learn what is possible. We are running
Angstrom built using Yocto project on a Overo Firestorm. Any advice on how
to set the DSP clock frequency for testing would be greatly appreciated.
Thanks
Patrick
--
View this message in context: http://gumstix.8.x6.nabble.com/Setting-DSP-clock-frequency-on-DM3730-tp4969307.html
Sent from the Gumstix mailing list archive at Nabble.com.

I am having issues setting the clock frequency on a DM3730 project running
Angstrom and using DSPLink. I have done significant profiling and found
that the DSP clock is running at 260MHz. I have tried adjusting cpuFreq on
the arm as well as rebuilding DSPLink multiple times with different
configurations and cannot get the DSP to run at higher clock frequencies.
We are currently trying to run arm at 1GHz and have the DSP run at 800MHz to
prove out that max through put we can get on a data processing application
with this processor. I understand this will damage the life of the part but
we are currently in an exercise to learn what is possible. We are running
Angstrom built using Yocto project on a Overo Firestorm. Any advice on how
to set the DSP clock frequency for testing would be greatly appreciated.
Thanks
Patrick
--
View this message in context: http://gumstix.8.x6.nabble.com/Setting-DSP-clock-frequency-on-DM3730-tp4969308.html
Sent from the Gumstix mailing list archive at Nabble.com.

On Wed, Jul 2, 2014 at 3:22 PM, patrick.ingram <patrick.ingram@...>
wrote:
>
> We are currently trying to run arm at 1GHz and have the DSP run at 800MHz
> to
> prove out that max through put we can get on a data processing application
> with this processor. I understand this will damage the life of the part
> but
> we are currently in an exercise to learn what is possible. We are running
> Angstrom built using Yocto project on a Overo Firestorm. Any advice on how
> to set the DSP clock frequency for testing would be greatly appreciated.
>
I believe this should work...
Index: git/arch/arm/mach-omap2/clock.c
===================================================================
--- git.orig/arch/arm/mach-omap2/clock.c 2014-04-24 22:24:43.763004434 -0500
+++ git/arch/arm/mach-omap2/clock.c 2014-04-25 23:04:48.183903024 -0500
@@ -462,6 +462,7 @@
{
struct clk *mpurate_ck;
int r;
+ struct clk *dpll2_clk;
if (!mpurate)
return -EINVAL;
@@ -483,6 +484,16 @@
clk_put(mpurate_ck);
+ dpll2_clk = clk_get(NULL, "dpll2_ck");
+ r = clk_set_rate(dpll2_clk, 600000000);
+ if (IS_ERR_VALUE(r)) {
+ printk("Couldn't set DSP clock\n");
+ }
+ else {
+ printk("DSP clock set to 600Mhz\n");
+ }
+ omap3_dpll_recalc(dpll2_clk);
+
return 0;
}

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