Bug Description

After upgrading KiCad today (my previous update had been last week or the week before, I believe) eeschema's ERC no longer works the way it had been with hidden power/ground pins on my components. The same schematics which passed ERC last week, now show hundreds of errors.

(I don't know if it makes any difference, but the schematic is structured as follows, in so far as power and ground are concerned. There are two sheets, tied together by a parent sheet. There are 3 power/ground buses, called FAP, 0VDCA, and +4SW. Each of these buses has a single PWR_FLAG, located on the parent sheet. All of the components with hidden FAP, 0VDCA, and +4SW pins are on the two child sheets.)

As an afterthought, it occurred to me to wonder if the netlists are affected by the same problem. They are not. A netlist generated today is identical to the one generated last week, and indicates that the hidden power/ground pins are connected correctly.

The fix has now shown up in the nightly build, but the ERC is extremely flaky with respect to hidden power/ground pins in components. Sometimes it works, and sometimes it does not.

It is difficult to characterize when it works vs fails, because KiCad often aborts and exits without warning when running the ERC, but it seems to me that it works more often when the net label and the PWR_FLAG are on the _same_ wire segment, and usually fails when the net label and PWR_FLAG are on different wire segments (but still on the same net). Netlists are correct in either case.

In this design, components have a hidden +3VDC pin and a hidden 0VDC pin. The long arrows are the PWR_FLAG components. At the top of the attached image, there's a configuration in which ERC gives hundreds of errors that the +3VDC and 0VDC pins are not connected. As you see, the net labels for those buses are separated from the PWR_FLAGs by an extra wire segment.

At the bottom of the attached image, there's a configuration in which the ERC gives 0 errors. I have moved the +3VDC PWR_FLAG to the same wire segment as its net label, but not the 0VDC PWR_FLAG. Remarkably, _both_ types of no-connect errors (+3VDC _and_ 0VDC) vanish from the ERC.

I actually had to move the +3VDC PWR_FLAG a couple of times to get it to work, so my observation that just putting the net label and the PWR_FLAG on the same segment can't be exactly right.

Yesterday I had checked about 30 or so schematics, Jon, with perhaps 2/3 of them passing ERC and 1/3 failing. (That's just a general idea, not exact counts.) I only rechecked 5 of them with last night's build. 4 that failed yesterday still fail today, and 1 that passed yesterday still passes. It's probably of no use to you, but their URLs are:

Unfortunately, I don't understand the build system, so I don't really understand how to verify that the latest build I just installed (from PPA "deb http://ppa.launchpad.net/js-reynaud/ppa-kicad/ubuntu xenial main") incorporates your fix or not. There always seems to be a delay of a few days or even a week from when I see notices that a fix is incorporated to when I can actually verify it is working properly.

They are nightly, I was just not remembering the time the build is triggered each night. I put in my fixes after the build was already started, so unfortunately they won't be included until the next nightly.

The string after the "unknown" in your nightly versions is a Git hash (ca7aec2), it uniquely identifies each commit. If you find the matching commit in "master" branch (for nightly builds), you will know the latest change that is in your build.