Abstract:

A computer graphics rendering apparatus according to an embodiment of the
present invention generates a screen image, using plural texture images
having different mipmap levels. The apparatus generates a normalized
texture coordinate of a texture image, generates, from the normalized
texture coordinate of the texture image, a texel coordinate of a texel in
the texture image, according to a mipmap level of the texture image, and
generates, regarding an image block in the texture image, an index value
indicating a cache line corresponding to the image block, using a texel
coordinate of a texel in the image block. The apparatus generates the
index value such that index values of image blocks in the same position
are different, between two texture images having mipmap levels adjacent
to each other.

Claims:

1. A computer graphics rendering apparatus for generating a screen image,
using plural texture images having different mipmap levels, the apparatus
comprising:a first coordinate generating unit configured to generate a
normalized texture coordinate of a texture image;a second coordinate
generating unit configured to generate, from the normalized texture
coordinate of the texture image, a texel coordinate of a texel in the
texture image, according to a mipmap level of the texture image; andan
index generating unit configured to generate, regarding an image block in
the texture image, an index value indicating a cache line corresponding
to the image block, using a texel coordinate of a texel in the image
block, the index generating unit generating the index value such that
index values of image blocks in the same position are different, between
two texture images having mipmap levels adjacent to each other.

2. The apparatus according to claim 1, wherein,the index generating unit
generates the index value such that index values of image blocks in the
same position are different, among N (N is an integer equal to or larger
than 3) texture images having mipmap levels adjacent to one another.

3. The apparatus according to claim 1, wherein,the index generating unit
generates the index value of K1 bits (K1 is an integer equal to
or larger than 2) by generating a one-dimensional bit string using the
texel coordinate of the image block, slicing a bit string of K1 bits
from the one-dimensional bit string, and performing bit string rotation
for the bit string of K1 bits.

4. The apparatus according to claim 3, wherein,the index generating unit
determines a rotation amount of the bit string of K1 bits, based on
the mipmap level of the texture image.

5. The apparatus according to claim 3, wherein,the index generating unit
generates the index value of K1 bits by performing bit inversion for
a predetermined bit in the bit string of K1 bits, and the bit string
rotation for the bit string of K1 bits.

6. The apparatus according to claim 5, wherein,the index generating unit
performs the bit inversion for the most significant bit in the bit string
of K1 bits.

7. The apparatus according to claim 3, wherein,the index generating unit
generates the index value of K1 bits by performing an addition
process of adding a predetermined value to the bit string of K1
bits, and the bit string rotation for the bit string of K1 bits.

8. The apparatus according to claim 3, wherein,the index generating unit
generates the index value of K1 bits by performing a multiplication
process of multiplying the bit string of K1 bits by a predetermined
value, and the bit string rotation for the bit string of K1 bits.

9. The apparatus according to claim 3, wherein,the index generating unit
generates the one-dimensional bit string using bits in a binary notation
of horizontal and vertical components of the texel coordinate of the
image block.

10. The apparatus according to claim 9, wherein,the index generating unit
generates the one-dimensional bit string by arranging the bits in the
horizontal component and the bits in the vertical component alternately
from most significant bits to least significant bits.

11. The apparatus according to claim 1, further comprising:an offset
generating unit configured to generate, regarding a texel in the texture
image, an offset value indicating an address corresponding to the texel,
using a texel coordinate of the texel.

12. The apparatus according to claim 11, wherein,the offset generating
unit generates the offset value of K2 bits (K2 is an integer
equal to or larger than 2) by generating a one-dimensional bit string
using the texel coordinate of the texel, and slicing a bit string of
K2 bits from the one-dimensional bit string.

13. The apparatus according to claim 12, wherein,the offset generating
unit generates the one-dimensional bit string using bits in a binary
notation of horizontal and vertical components of the texel coordinate of
the texel.

14. The apparatus according to claim 13, wherein,the offset generating
unit generates the one-dimensional bit string by arranging the bits in
the horizontal component and the bits in the vertical component
alternately from most significant bits to least significant bits.

15. The apparatus according to claim 14, wherein,the offset generating
unit slices, from the one-dimensional bit string, K2 bits from the
least significant bit as the bit string of K2 bits.

16. The apparatus according to claim 1, further comprising:a judgment unit
configured to judge whether the image block is present in the cache line
indicated by the index value,wherein,when the image block is not present,
the judgment unit reads out the image block from the cache line, after
refilling the cache line with the image block, andwhen the image block is
present, the judgment unit reads out the image block from the cache line,
without refilling the cache line with the image block.

17. A computer graphics rendering method for generating a screen image,
using plural texture images having different mipmap levels, the method
comprising:generating a normalized texture coordinate of a texture
image;generating, from the normalized texture coordinate of the texture
image, a texel coordinate of a texel in the texture image, according to a
mipmap level of the texture image; andgenerating, regarding an image
block in the texture image, an index value indicating a cache line
corresponding to the image block, using a texel coordinate of a texel in
the image block, the method generating the index value such that index
values of image blocks in the same position are different, between two
texture images having mipmap levels adjacent to each other.

18. The method according to claim 17, wherein,the method generates the
index value such that index values of image blocks in the same position
are different, among N (N is an integer equal to or larger than 3)
texture images having mipmap levels adjacent to one another.

19. The method according to claim 17, wherein,the method generates the
index value of K1 bits (K1 is an integer equal to or larger
than 2) by generating a one-dimensional bit string using the texel
coordinate of the image block, slicing a bit string of K1 bits from
the one-dimensional bit string, and performing bit string rotation for
the bit string of K1 bits.

20. The method according to claim 17, further comprising:generating,
regarding a texel in the texture image, an offset value indicating an
address corresponding to the texel, using a texel coordinate of the
texel.

Description:

CROSS REFERENCE TO RELATED APPLICATION

[0001]This application is based upon and claims the benefit of priority
from the prior Japanese Patent Application No. 2007-272488, filed on Oct.
19, 2007, the entire contents of which are incorporated herein by
reference.

[0005]In the field of computer graphics, a method called texture mapping
is widely known. In the texture mapping, it is possible to give texture
to an object in an image, by pasting a texture image on the surface of
the object. In the texture mapping, in order to realize an increase in
speed of image processing, plural texture images having different
resolutions are often used to represent the texture. Each of the texture
images is called mipmap. The level of the resolution of each texture
image is represented by a number called a mipmap level.

[0006]In such texture mapping, plural texture images having different
mipmap levels may be simultaneously referred to. In this case, accesses
to these images occur simultaneously in a texture cache. Therefore, a
conflict of a cache line may occur among these images. In other words, a
same cache line may be used for these images.

[0007]In general, such conflict can be prevented by adopting a set
associative approach of two or more ways (hereinafter referred to as
"associative approach") or an approach of dividing a cache into two sets
such as a set for mipmaps at even levels and a set for mipmaps at odd
levels (hereinafter referred to as "division approach") (see, for
example, Ziyad S. Hakura and Anoop Gupta, Stanford University, "The
Design and Analysis of a Cache Architecture for Texture Mapping",
International Symposium on Computer Architecture, 1997). However, in the
associative approach, an increase in a circuit cost due to an increase in
associativity poses a problem. Further, in the division approach, it is
likely that only a half of the total capacity of the cache is used in
some case. Therefore, in the division approach, deterioration in
efficiency of the cache poses a problem. For example, when texture is
given to a large object, only a mipmap at level 0 is used even if a
mipmap function is adopted. In this case, a half of the total capacity of
the cache (a set for odd levels) is not used at all.

[0008]As described above, in the associative approach and division
approach, wastes related to caching of texture images, such as an
increase in a circuit cost and deterioration in efficiency of the cache,
pose problems.

SUMMARY OF THE INVENTION

[0009]An aspect of the present invention is, for example, a computer
graphics rendering apparatus for generating a screen image, using plural
texture images having different mipmap levels, the apparatus including a
first coordinate generating unit configured to generate a normalized
texture coordinate of a texture image, a second coordinate generating
unit configured to generate, from the normalized texture coordinate of
the texture image, a texel coordinate of a texel in the texture image,
according to a mipmap level of the texture image, and an index generating
unit configured to generate, regarding an image block in the texture
image, an index value indicating a cache line corresponding to the image
block, using a texel coordinate of a texel in the image block, the index
generating unit generating the index value such that index values of
image blocks in the same position are different, between two texture
images having mipmap levels adjacent to each other.

[0010]Another aspect of the present invention is, for example, a computer
graphics rendering method for generating a screen image, using plural
texture images having different mipmap levels, the method including
generating a normalized texture coordinate of a texture image,
generating, from the normalized texture coordinate of the texture image,
a texel coordinate of a texel in the texture image, according to a mipmap
level of the texture image, and generating, regarding an image block in
the texture image, an index value indicating a cache line corresponding
to the image block, using a texel coordinate of a texel in the image
block, the method generating the index value such that index values of
image blocks in the same position are different, between two texture
images having mipmap levels adjacent to each other.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011]FIG. 1 is a block diagram of a computer graphics rendering apparatus
according to an embodiment of the present invention;

[0012]FIG. 2 is a diagram for explaining a texture image and a screen
image;

[0015]FIG. 5 is a diagram for explaining a normalized texture coordinate
and a texel coordinate;

[0016]FIG. 6 is a diagram for explaining an index value and an offset
value;

[0017]FIG. 7 shows an example of an index map regarding a texture image at
level 0;

[0018]FIG. 8 shows an example of an index map regarding a texture image at
level 1; and

[0019]FIG. 9 shows an example of an index map regarding a texture image at
level 2.

DESCRIPTION OF THE EMBODIMENTS

[0020]Embodiments of the present invention will be described with
reference to the drawings.

[0021]FIG. 1 is a block diagram of a computer graphics rendering apparatus
101 according to an embodiment of the present invention. The rendering
apparatus 101 in FIG. 1 includes a vertex shader 111, a rasterizer 112, a
pixel shader 113 as an example of a first coordinate generating unit, a
texture unit 121, a raster operation unit 131, and a system memory 141.
The texture unit 121 includes a UV generator 151 as an example of a
second coordinate generating unit, a tag/index/offset generator 152 as an
example of an index generating unit and an offset generating unit, a
cache body 153 as an example of a judgment unit, and a filter 154.

[0022]As shown in FIG. 2, the rendering apparatus 101 in FIG. 1 generates
a screen image using a texture image. In FIG. 2, a screen image IS
is generated from a texture image IT. In FIG. 2, the texture image
IT and the screen image IS are stored in memories. When the
screen image IS is generated from the texture image IT, the
texture image IT is temporarily stored in a texture cache 201.

[0023]As shown in FIG. 3, the rendering apparatus 101 in FIG. 1 can
generate a screen image using plural texture images, which are mipmaps
having different mipmap levels. In FIG. 3, a screen image IS is
generated from texture images IT0, IT1, and IT2 at levels
0, 1, and 2. In FIG. 3, the texture images IT0, IT1, and
IT2 and the screen image IS are stored in memories. When the
screen image IS is generated from the texture images IT0,
IT1, and IT2, the texture images IT0, IT1, and
IT2 are temporarily stored in the texture cache 201.

[0027]The normalized texture coordinate is a coordinate system in which a
distance from one end to the other end of a texture image is set to 1. In
the normalized texture coordinate, regardless of the size and mipmap
level of the texture image, the coordinate at the upper left end (or the
lower left end) of the texture image is (0, 0), and the coordinate at the
lower right end (or the upper right end) of the texture image is (1, 1).

[0028]The texel coordinate is a coordinate system in which an interval
between adjacent two texels is set to 1. In the texel coordinate, the
coordinate at an end point of a texture image depends on the size and
mipmap level of the texture image. In the texture image IT0, the
coordinate at the upper left end (or the lower left end) of the image is
(0, 0), and the coordinate at the lower right end (or the upper right
end) of the image is (128, 128). In the texture image IT1, the
coordinate at the upper left end (or the lower left end) of the image is
(0, 0), and the coordinate at the lower right end (or the upper right
end) of the image is (64, 64). In the texture image IT2, the
coordinate at the upper left end (or the lower left end) of the image is
(0, 0), and the coordinate at the lower right end (or the upper right
end) of the image is (32, 32).

[0029]The size of the original image of a certain texture image is assumed
to be W×H pixels. In this case, relations u=s×W/2L and
v=t×H/2L hold between a normalized texture coordinate and a
texel coordinate of the texture image. In the relations, L represents the
mipmap level of the texture image.

[0031]The vertex shader 111 receives vertex row data of a polygon to be
rendered from the system memory 141, performs coordinate conversion and
lighting by the vertex, and generates coordinate values and various
parameters of each vertex.

[0032]The rasterizer 112 receives the coordinate values and various
parameters of each vertex from the vertex shader 111, and generates
pixels in the polygon and various parameters of each pixel.

[0033]The pixel shader 113 receives the various parameters of each pixel
from the rasterizer 112, and performs lighting and other processes by the
pixel. In the processes by the pixel by the pixel shader 113, texture is
referred to if it is necessary. In this case, the pixel shader 113
generates and outputs a normalized texture coordinate of a texture image.

[0034]The UV generator 151 receives the normalized texture coordinate from
the pixel shader 113. The UV generator 151 then generates, from the
normalized texture coordinate, a coordinate on the texture image (texel
coordinate), according to the size and mipmap level of the texture image.
In this way, a texel coordinate of each texel in the texture image is
generated from the normalized texture coordinate of the texture image,
according to the size and mipmap level of the texture image.

[0035]The tag/index/offset generator 152 receives the texel coordinate of
the texture image from the UV generator 151. The tag/index/offset
generator 152 then generates, regarding the texture image, a tag of a
cache 201 corresponding to the texture image, using a texel coordinate of
a texel in the texture image.

[0036]The tag/index/offset generator 152 further generates, regarding an
image block in the texture image, an index value indicating a cache line
corresponding to the image block, using a texel coordinate of a texel in
the image block.

[0037]The tag/index/offset generator 152 further generates, regarding a
texel in the texture image, an offset value indicating an address
corresponding to the texel, using a texel coordinate of the texel. The
offset is a relative address indicating a position of the texel in the
cache line.

[0038]The cache body 153 receives the tag, the index, and the offset from
the tag/index/offset generator 152. The cache body 153 accesses the cache
201 corresponding to the tag, and judges whether the image block is
present in the cache line indicated by the index value.

[0039]In the case of a cache mistake, i.e., when the image block is not
present, the cache body 153 reads out the image block from the cache
line, after refilling the cache line with the image block from the system
memory 141. In reading out a desired texel, the offset value is used.

[0040]In the case of a cache hit, i.e., when the image block is present,
the cache body 153 reads out the image block from the cache line, without
refilling the cache line with the image block from the system memory 141.
In reading out a desired texel, the offset value is used.

[0041]The filter 154 receives the read-out texel from the cache body 153,
and applies texture filtering to the texel. The filtered texel is sent to
the pixel shader 113, and processed by the pixel shader 113. The texel
processed by the pixel shader 113 is sent to the raster operation unit
131, processed by Z buffering (hidden-surface removing) and α
blending, and then written in a frame buffer in the system memory 141.

[0042]FIG. 6 is a diagram for explaining a process of generating an index
value and an offset value by the tag/index/offset generator 152.

[0043]FIG. 6A shows an image block B. The size of the image block B is
8×8 texels. Texel coordinates (u, v) of texels T0, T1,
T2, . . . , and T63 in the image block B are represented as
(u0, v0), (u1, v1), (u2, v2), . . . , and
(u63, v63), respectively. The texel coordinate (u, v) of an
arbitrary texel Ti in the image block B is represented as (ui,
vi). Each of "ui" and "vi" is 7-bit data that can take a
value from 0 to 127, and they are represented as follows:

ui=26ui(6)+25ui(5)+24ui(4)+23u.sub-
.i(3)+22ui(2)+21ui(1)+20ui(0).

vi=26vi(6)+25vi(5)+24vi(4)+23v.sub-
.i(3)+22vi(2)+21vi(1)+20vi(0).

[0044]In the above, "ui(0)" to "ui(6)" represent bits of first
to seventh digits in the binary notation of u, respectively. Further,
"vi(0)" to "vi(6)" represent bits of first to seventh digits in
the binary notation of v, respectively.

[0045]When an index value and an offset value regarding the image block B
are generated, a one-dimensional bit string is generated by using the
texel coordinates (u0, v0) to (u63, v63) of the image
block B. As an example of such bit string, FIG. 6B shows a bit string X.
The bit string X is a sequence like P63 . . . P2P1P0.
In this embodiment, P0, P1, P2, . . . , and P63 are
bit strings generated by using the texel coordinates (u0, v0),
(u1, v1), (u2, v2), . . . , and (u63, v63),
respectively. In this embodiment, Pi is a bit string arranged like
vi(6)ui(6), . . . ,
vi(2)ui(2)vi(1)ui(1)vi(0)ui(0).

[0046]In this way, Pi is generated by using respective bits in the
binary notation of ui and vi. Specifically, Pi is
generated by arranging bits in the binary notation of ui and bits in
the binary notation of vi alternately from most significant bits
(seventh digit bits) to least significant bits (first digit bits). The
bit string X is generated by arranging sixty-four Pi.

[0047]Subsequently, as shown in FIG. 6B, a bit string Y of K bits and bit
strings Z0 to Z63 of K bits are sliced from the one-dimensional
bit string X. The bit number K of the bit string Y is an example of a bit
number K1. The bit number K of the bit strings Z0 to Z63
is an example of a bit number K2. In this embodiment, K1 and
K2 have a relation of K1=K2. However, K1 and K2
may have a relation of K1≠K2. The bit number K is an
integer equal to or larger than 2. In this embodiment, the bit number K
is 6.

[0048]The bit strings Z0, Z1, Z2, . . . , and Z63 are
sliced from the bit strings P0, P1, P2, . . . , and
P63, respectively. The bit string Zi corresponds to 0 to 5 bit
portions of the bit string Pi. In this embodiment, six bits from the
least significant bit of the bit string Pi are sliced from the bit
string Pi as the bit string Zi. In this embodiment, values
represented by the bit strings Z0, Z1, Z2, and Z63
are used as offset values of the texels T0, T1, T2, . . .
, and T63, respectively.

[0049]The bit string Y is sliced from the bit string P0. The bit
string Y corresponds to 6 to 11 bit portions of the bit string P0.
In this embodiment, the bit string Y of six bits is sliced from the bit
string P0 generated by using one texel T0. The bit string Y may
be sliced from any one of the bit strings P1 to P63. In this
embodiment, a bit string YA of K bits is generated from the bit
string Y, a bit string YB of K bits is generated from the bit string
YA, and a value represented by the bit string YB is used as an
index value of the image block B.

[0050]As shown in FIG. 6B, the bit string YA is generated by bit
inversion of a predetermined bit in the bit string Y. In this embodiment,
the predetermined bit is the most significant bit in the bit string Y.
However, the predetermined bit may be another bit in the bit string Y.
FIG. 6B shows the inversion of the most significant bit vi(5).

[0051]As shown in FIG. 6B, the bit string YB is generated by bit
string rotation of the bit string YA. FIG. 6B shows the rotation of
the bit string YA to the left. The rotation amount of the bit string
YA is determined, based on a mipmap level L of a texture image I
having the image block B (see FIG. 6C). In this embodiment, the rotation
amount of the bit string YA is 2 L bits. Therefore, rotation amounts
at mipmap levels 0, 1, and 2 are 0, 2, and 4 bits, respectively.

[0053]In FIGS. 7 to 9, index values of image blocks in the same position
are different, between two texture images having mipmap levels adjacent
to each other. In other words, index values of image blocks in the same
position are different, between the texture image IT0 in FIG. 7 and
the texture image IT1 in FIG. 8, and between the texture image
IT1 in FIG. 8 and the texture image IT2 in FIG. 9.

[0054]For example, the index value of an image block B1 in FIG. 8 is
50.

[0055]The image block B1 in FIG. 8 is present in the same position as
an image block B0A in FIG. 7. The index value of the image block
B0A is 16, which is different from the index value of the image
block B1.

[0056]The image block B1 in FIG. 8 is present in the same position as
an image block B0B in FIG. 7 as well. The index value of the image
block B0B is 17, which is different from the index value of the
image block B1.

[0057]The image block B1 in FIG. 8 is present in the same position as
an image block B0C in FIG. 7 as well. The index value of the image
block B0C is 18, which is different from the index value of the
image block B1.

[0058]The image block B1 in FIG. 8 is present in the same position as
an image block B0D in FIG. 7 as well. The index value of the image
block B0D is 19, which is different from the index value of the
image block B1.

[0059]Such a relation holds between all image blocks in FIG. 8 and image
blocks corresponding thereto in FIG. 7. Such a relation also holds
between all image blocks in FIG. 9 and image blocks corresponding thereto
in FIG. 8. For example, the index value of an image block B2 in FIG.
9 is 11. However, index values of image blocks B1A, B1B,
B1C, and B1D corresponding thereto in FIG. 8 are 1, 5, 9, and
13 (≠11), respectively.

[0060]As described above, the tag/index/offset generator 152 generates an
index value such that index values of image blocks in the same position
are different, between two texture images having mipmap levels adjacent
to each other. An effect obtained by such process is explained below with
reference to FIG. 3.

[0061]FIG. 3 shows regions R0, R1, and R2. The regions
R0, R1, and R2 are areas where the screen image IS is
generated by using the texture images IT0, IT1, and IT2,
respectively. FIG. 3 further shows a boundary α between the region
R0 and the region R1, and a boundary β between the region
R1 and the region R2. In the process of generating such a
screen image IS, when an image near the boundary α is
rendered, image blocks in the same position at the level 0 and the level
1 are often referred to simultaneously. Similarly, when an image near the
boundary β is rendered, image blocks in the same position at the
level 1 and the level 2 are often referred to simultaneously. Therefore,
when index values of image blocks in the same position have the same
value, a conflict of a cache line occurs between the image blocks.
However, in this embodiment, since index values of image blocks in the
same position are different, such conflict is prevented.

[0062]Further, in this embodiment, the tag/index/offset generator 152
generates an index value such that index values of image blocks adjacent
to each other are different in respective texture images. Such a process
is adopted because, in the process of generating the screen image
IS, adjacent image blocks in respective texture images are often
referred to simultaneously. Consequently, according to this embodiment, a
conflict of a cache line between such image blocks can be prevented. Note
that, in FIGS. 7, 8, and 9, index values are different between all
adjacent image blocks.

[0063]The bit string Y and the bit string YB shown in FIG. 6 will be
compared. In this embodiment, the bit string YB is adopted as an
index value. It is also conceivable to adopt the bit string Y as an index
value, instead of the bit string YB. However, in this case, between
two texture images having mipmap levels adjacent to each other, there is
a place where index values of image blocks in the same position are the
same. For example, between the texture image in FIG. 7 and the texture
image in FIG. 8, index values of image blocks at the four corners become
same.

[0064]Therefore, in this embodiment, the bit string YB is adopted as
an index value. The bit string YB is generated by applying bit
inversion and bit string rotation to the bit string Y. According to the
bit string rotation, it is possible to adjust a period of a change in
index values according to a change in a normalized texture coordinate, to
the same period regarding texture images having different mipmap levels.
Consequently, in this embodiment, it is possible to prevent a situation
in which index values of image blocks in the same position become same
between texture images having different mipmap levels.

[0065]As described above, the bit string YB is generated by applying
the bit inversion and the bit string rotation to the bit string Y. These
processes can be performed by a relatively simple circuit. Therefore,
according to this embodiment, it is possible to realize, with a
relatively simple circuit, an index generating process that makes index
values of image blocks in the same position different between texture
images having different mipmap levels. Therefore, according to this
embodiment, it is possible to realize, at relatively low cost, the
rendering apparatus 101 that performs such process.

[0066]In this embodiment, the index generating process may be realized by
adopting a bit string other than the bit string YB. For example,
such a bit string may be generated by an addition process of adding a
predetermined value to the bit string Y and the bit string rotation
described above. Further, such a bit string may be generated by a
multiplication process of multiplying the bit string Y by a predetermined
value and the bit string rotation described above.

[0067]As described above, the tag/index/offset generator 152 generates an
index value such that all index values of image blocks in the same
position are different, between two texture images having mipmap levels
adjacent to each other. In this embodiment, as shown in FIG. 4, texture
images having the levels 0 to 7 are present for an original image. In
this embodiment, all index values of image blocks in the same position
may be different, between the image IT0 and the image IT1,
between the image IT1 and the image IT2, between the image
IT2 and the image IT3, between the image IT3 and the image
IT4, between the image IT4 and the image IT5, between the
image IT5 and the image IT6, and between the image IT6 and
the image IT7. On the other hand, in this embodiment, all index
values of image blocks in the same position may be different, between
IT0 and IT1, between IT1 and IT2, between IT2
and IT3, between IT3 and ITI4, between IT4 and
IT5, between IT5 and IT6, or between IT6 and
IT7. For example, all index values of image blocks in the same
position may be different only for texture images from the level 0 to a
predetermined level. The above description is also applicable to index
values of adjacent image blocks in respective texture images.

[0068]The tag/index/offset generator 152 may generate an index value such
that index values of image blocks in the same position are different,
among N (N is an integer equal to or larger than 3) texture images having
mipmap levels adjacent to one another. An example in the case of N=3 is
shown in FIGS. 7 to 9. In FIGS. 7 to 9, all index values of image blocks
in the same position are different, between the image IT0 and the
image IT1, between the image IT1 and the image IT2, and
between the image IT0 and the image IT2. The description in the
immediately preceding paragraph is also applicable to the case explained
in this paragraph.

[0069]As described above, the embodiment of the present invention can
provide a preferred method of caching of texture images, regarding a
computer graphics rendering apparatus and a computer graphic rendering
method.

[0070]Examples of specific aspects of the present invention are explained
with reference to the embodiment of the present invention. However, the
present invention is not limited to the embodiment.