There are articles on Habr for FPGA beginners, there are articles with PC board layouts. I have already referenced some of them in my first article on PCBs building. In the comments to my second article about SimBank, I had a discussion concerning the difficulties of FPGA development and supporting projects with it. There was an opinion that it's much easier to compile several simple devices instead of one complex unit. Sometimes, it's really true. When it goes about two, four or eight devices. And so on with a usual multiplicity. Until a comfortable limit is achieved. Is two too much? And what happens if you need 100 or 200 similar devices?To use FPGA or not in any task is the question to be answered by the developer himself (or together with the colleagues). Today, I want to talk about the specificity of an FPGA PC board creation. Let's take IO Designer tool by Mentor Graphics as the starting point.

Some may find my article useful, some may think it's simply interesting, but there will be guys who may not agree with me.

For some CAD systems, such as Altium Designer, regular updates appear with new microcircuits data bases. (If you are subscribed for the updates.) For Cadence and OrCAD, the manufacturers often publish the library elements of circuit symbols and cells for PC boards. For ExpeditionPCB by Mentor Graphics such luxury is rather an exclusion than a rule. As for PADS (another product for through designing of PC boards by Mentor Graphics), I have nothing to say as I've never worked with them. The designing system itself has a very convenient library components manager. There is a very good program, LP Wizzard (Land pattern wizzard), to build the component seats on PC boards according to IPC-7351 standard requirements. To create graphical circuit symbols for simple and more complex components, there is the possibility of import from file. And for FPGA, there is IO Designer that combines symbol, circuit, board (for the PC board) and Verilog(VHDL) project sections.IO Designer contains the data base for most of FPGA and CPLD by such manufacturers as Xilinx, Altera, Lattice and Acctel. With MG, the appearance of new FPGA families from various manufacturers is accompanies by updates to FPGA bases. But you will have to study new documentation for the microcircuits families anyway. Let's say we've chosen FPGA, studied (got familiar with) its specific features and are ready to create.When creating a project, we can select the FPGA manufacturer, FPGA family, type of housing and number of elements. In addition, we can specify the components speed (to accurately set the Part Number).

In FPGA, most contacts may be configured both for output and for input. It may seem great – just connect and do not bother. This one will be used for SD card controller connection, this one – for RGMII for Ethernet PHY and so on. But it's not so simple anyway. With such a fearless contacts assigning by convenience, we can come across many pitfalls. Documentation reading may help to avoid most of them, but contacts assigning won't be easier. And your board project may turn into an absolute mess.

In this picture, everything is not so bad because it is created "artificially" based on an elaborated project. Usually, everything's not so smooth at first. And at FPGA addition stage, not all the elements are placed on the board. But it is specially marked that the signals from the lower left contact comes not to the bottom corner of the FPGA. As a result, they are intersected with other signals and when laid out may require both additional transition holes and additional board layers. This will increase the production costs in the end.

The contacts setting possibilities may also be limited. It's good if our board is created for one specific product. There are the outputs of adjacent elements, and we make response buses/signals for them in the FPGA. Then we launch a pilot CAD project for the FPGA. If everything's ok, the board may be laid out.

Some digression: AFAIK, Xilinx Spartan-6 had specially assigned pins for DDR memory that were then conveniently laid out subject to correct interrelation of microcircuits in the board. And it was unnecessary to move or swap them afterwards.

Often, specifications require some unification and our board will be used for several projects in the future. This is the way a core board with processor is designed for operation with many other devices, some kind of debugging board with FPGA, processor and OS "for friends". And there's much to think about. To provide one pin in the contact for synchronization or for PLL signal output if necessary. To determine the signals direction in the bus: input, output or both ways. If our core board is always a master, such signals to the address bus or control signals may work only for output. If there's a response from the slave board on the bus such as WAIT or BUSY, they may be assigned to pins capable to work as outputs only. The same may be done with the pins determining the board availability. At first sight, such assigning limits the possibilities of future laying out and signals shuffling. But in practice, it's better to know such restrictions in advance instead of assigning all the signals as Inout.

We can select a file to take the list of signals from. This may be a pilot project, a file at Verilog or VHDL.

If we have not made any pilot project yet, we can do without compiling such a file. And then simply create the signals in a program window. Default signal types. For single and differential signals.Then we can proceed and specify the location where to download the file with our contacts layout.Then we need to understand the way we want our circuit to operate, either we need full-scale symbols or just lops in a circuit project will be enough with the description of all the contacts to be transmitted only in the form of a data share file with FPGA CAD system.I always liked the option without any circuit elements when all the exchange is realized via unknown internal paths. But, when you work in a team, you have to accept more down-to-earth game rules. So, the corporate standard always dictated to divide a symbol between banks, to separate the loops for configuration, earthing, power and other. Such division has its pros, but there are some cons, too. It was me who had to make a circuit symbol. For FPGA with 484 contacts, it's not so difficult to make a correct circuit symbol, though it may seem complicated. However, for a microcircuit with 1172 contacts, this task becomes quite and exhausting one. Most contacts have long and similar names that may be confused easily. All the symbols may be generated automatically. But, then they fail to match the "corporative" preferences. In IOD, a symbol may be easily created from the elements data base simply by dragging it from the contacts list window to the symbol window. I cannot say it's as simple as playing in a Funny Farm, but at this stage, we just can assign signals to the microcircuit contacts using a mouse. This method also allows to set the way of labeling: by name, by function, by contact number or in any other way. Usually, I select labeling by function. To my mind, such label is more informative. So, you can always read from the circuit what kind of signal may be put in here.

From my own observations, I can say that the last names in Xilinx (for series 6 and 7 families) are quite short and informative. IO_L6N_T0_VREF_13IO — input/output contactL6N — differential pairT0 — byte which allows internal data signals swap for memory (this is to be defined!)VREF — here, external support voltage may be connected to if required by the standard of signal selected for the bank and there isn't any other possibility to connect in inside the FPGA.13 — bank number.

In Altera, adequate functional labels may also be found sometimes, though (it's my subjective opinion) some poorly reproducible contact names are more frequent that cannot be put into the circuit sheet. Perhaps, if I made circuits with large memory volumes, multipliers or some type of colliders, I would find such names useful.IO_DIFFIO_T18p__DATA15_DQ3T0_X9__DQ3T9_X18_DQ5T27_X36In this case, the possibility to assign a Custom Label for the contact name is helpful. Or the possibility to enter the necessary label manually. Usually, I copy the function and reduce it to the following:IO_T18p_DATA15_DQWhere IO — may be used for input/output signalsT18p — is the number of differential pair in the upper segmentDATA15 — this contact may be used for parallel configuration downloadingDQ — for me, it's the abbreviated contact function (other options are DM and DQS)This is one of the examples of a contact naming based on its functionality, and with some specific project, any other attribute will be used in the first place.For instance, in Altera when LVDS signals are used, the external load should be placed first. For some banks, it is the load resistance at the receiving side only, for others, the output resistance is also required. This may be canceled in the circuit symbol in Custom Label property. The same is true for PCI type signals. 3.3V-PCI bus standard can be assigned not for all banks. This also may be included in the symbol. Despite this standard is more widely replaced with PCIe in desk top systems, it is still popular in production versions. And some customers look for this very version of units.An inscription may be added in a symbol for all the contact at once. This will reduce the text inside the symbol. As any additional information may overload the symbol and circuit, a compromise is required. I did it for Xilinx microcircuits that had microcircuits compatible by contacts inside one and the same housing with different number of logical elements, but in "tiny" microcircuits some contacts are not active. For such project, a circuit was partially unsoldered and there was a possibility to put a "lighter" microcircuit. Taking this into account when assigning the contacts, later, you can save on the missing components and the FPGA price.For convenience, I make the symbols divided into banks. An exclusion may be made for configuration contacts. For projects with complex synchronization structure, CLK inputs, local, global and other, may be collected into a separate symbol. VCCO bank power contacts are placed in the symbol together with the bank or in a separate symbol if the CHIEF designer wishes so.Most often, I use separate symbols for the core power, VCCAUX, earthing and other contacts. I heard, today, just a loop in the circuit may be created for all the power contacts in order not to overcharge it with the big number of typical contacts. It's not the way we do, therefore I have no experience in this options. Details of this may be found in reference documents or webinars and training materials at Mentor Graphics or its representatives sites.

I send the created symbols to the circuit project directly specifying the housing type and abstract it into the board, so the microcircuit is linked to the board, the circuit and the IODesigner.

Signals creation and assignmentAs it was described above, we can export the signals from a file or create them ourselves.

Signals may be assigned both with a mouse or via import/export operations. Holding SHIFT, CTRL or ALT keys pressed, you can re-assign the signals to already assigned contacts. Or assign all the selected signals into one bank. Visually, the banks are displayed in different colors. Different type contacts are displayed by different icons. Differential pairs display may be switched on. With time, occupied signals are colored.

After updating, we can see the symbols with the signals in the circuit.

Then, we check their connection on the board. Usually, it's the same "mess" as was shown above.Sometimes, I start with a simple list of signals to be automatically created in the system and then, using a circuit editor, I drag them to other elements.Another alternative is to import the list of signals from the circuit. Having synchronized the circuit project, the board and IO Designer, we can call the signals display in IO Designer window. With the loops coming from the FPGA to the components connected to it.Now, we can comb our signals. And this will be an automatic operation according to the rules we set. Configuration signals will stay intact. In addition, we can preliminary lock the signals to prevent from their position changing.

Please, note, DRAM3_RESET_B signal that must be assigned LVCMOS_1.35V input/output standard and cannot stay in the same bank with SSTL standard signals is assigned to bank 17, and all the rest of DRAM3* signals are assigned to bank 12. As the system has only four LVCMOS_1.35V signals, they are assigned LVCMOS1.8V standard with a level modifier.

Despite seeming complexity, the signals are now arranged according to the set rules for more convenient operations with the project in Quartus.In the picture, you can see the placed components and the lines stretching to them from the FPGA. Sometimes, if not all the components are placed, it is impossible to arrange all the contacts at once for failsafe laying out. Though, it depends on the task. After such arrangement of contacts, you may pass the circuit to final laying out or make the layout yourself.In addition, it may be exported to Verilog / VHDL file. Export in *.ucf, *.pin or other file is also possible. Give it to the FPGA designer for a pilot project, it may happen that something is omitted. However, in a small team, it not always works as your teammate may be very busy with other projects. (Old projects updates, new customer's desires or parallel projects.)Limitations.This method has it's own limitations and I do not have a universal answer for their bypassing. Mostly, they are related to the necessity of doing many things for unification and for future use. So, the crutches need to be invented. As the default Altera settings forbid placing a differential signal next to the differential signal, the compiler will give a warning. We can bypass it by placing SLEW_RATE = 0 MHz parameter into Pin Planner Quartus. Then, the compilation will be finished successfully, even if our real signal will have frequency of 20 MHz. In IODesigner, there isn't such a parameter. As a result, these contacts are engaged last in the circuit or I set such a signal type for them that avoids conflict, for example, PCB signal or configuration signal. There are other limitation that are usually bypassed. But, generally, I take them as positive for they make you read the documentation for the microcircuit well in advance before the ready board comes.For those who work in other designing systems, some items may seem unmarked or, maybe, unnecessary. So, as far as I know (heard), Altium allows for setting FPGA project compilation directly in the project with the circuit and board. I have no information about all its possibilities. And for people who design in it, no import to Quartus or ISE is required. But in our team, board project is made by one person, while FPGA project is the responsibility of another one. When passing the circuit for laying out, I try to give the most correct description of signals and leave some freedom for the board designer to change contacts. And we manage any possible warnings as they accumulate.In the end, I'd like to mention that IO Designer is not a silver bullet. It does not turn the circuit, board and FPGA project design process into an interactive game and does not exempt you from reading the microcircuit documentation. However, it's much more pleasant to work with such instrument. The article does not uncover all its advantages. I also cannot say anything for sure about the libraries completeness for all the microcircuits for I have experience only with some of Altera and Хilinx families. I used to work a bit with Lattice debugging set, but it was not a circuit and, moreover, a board. I've never worked with Actel at all. As for the remarks for Xilinx, I can note that my version does not have direct constraints file transfer to/from Vivado. Maybe, it will appear in the updates. As it's not me, who manages the FPGA Xilinx project, I did not see into the problem. We coped with export function via *.csv file. This post cannot be called a IODesigner guide. For this see Mentor Graphics lessons. I know, that Megratec company offers some training in Russian. www.megratec.ru.I also know Mentor Graphics prepares a new version of designing system, xPedition, for marketing. We'll see what will be added for IODesigner. Out of the presentations I saw, I was impressed by 3D boards display updates and designing of units with several boards in a single project.Besides the CADs I mentioned, there are other systems for PC boards. Each one has its advantages and the list of "Y items missing compared to X". And if I said nothing about their advantages compared to IOD alternative, please, don't take it personally. You may speak about it in the comments. Or write an article about your way to design FPGA in your CAD system.