The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.

A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.

New capabilities for flex and rigid-flex designs

Stack-Up by Zone for Flex and Rigid-Flex Designs: Multiple zones can be created using the new Cross-Section Editor to represent rigid-flex-rigid PCBs. The stack-up by zone feature provides faster, easier definition of stack ups for rigid-flex-rigid designs and improves MCAD-ECAD co-design.

Enhanced Contour, Arc-Aware Routing: Enhanced Contour is a more efficient method to add routing during Add Connect by following an existing connect line or a route keep-in, which will save time for PCB designers working on flex designs.

Cross-Section Editor

The Cross-Section Editor has been redesigned, leveraging the underlying spreadsheet technology found in Constraint Manager. It offers one-stop shop for features that require the cross section for their setup, such as dynamic unused pad suppression and embedded component design.

Dynamic concurrent team design

The New Allegro dynamic concurrent-team-design capability focuses on shortening the largest portion of the PCB layout design cycle. It provides dynamic concurrent PCB team design for multiple PCB designers to work on the same design at the same time without any set-up requirements. In addition, new features—including interactive etch-editing capabilities, Allegro TimingVision™ technology, auto-interactive delay, and phase-tuning capabilities—provide proven time reductions to route advanced high-speed interfaces such as DDRx and PCI Express® (PCIe®) by up to 80 percent.

New Padstack Editor

A new Padstack Editor eases padstack creation through a new modern user interface. New features include the padstack designer, padstack usage types, pad geometries, and several new drill features.

Expanded in-design rules for backdrill vias

Many improvements have been made to the backdrill process to assist PCB designers in managing the backdrill vias/padstacks, route around the backdrill vias/padstacks with accurate DRCs, and real-time feedback.

Tabbed routing

Tabbed routing is a new routing strategy in which trapezoidal shapes called tabs are added to parallel traces to control impedance in the pin-field/breakout region and crosstalk in open-field region. This method enables longer trace lengths and use of smaller trace spacing. Tabbed routing is used for impedance control and to manage

Support for watermark in generated PDF file in Allegro Design Authoring DE-HDL

Users can now embed a watermark such as “First Prototype”, “Confidential”, or “Review Copy” in the generated PDF file.

Tag-based ECSet mapping in Allegro Design Authoring DE-HDL

ECSet nodes now support tags (pin parameter), which can be used to uniquely identify a pin and remove any ambiguity.

Port Groups in Allegro Design Authoring DE-HDL

Net Groups can be pushed across different levels of hierarchy by creating a Port Group. The Port Group is made available to higher-level blocks through the hierarchical block symbol where they appear with a new Pin Shape for unique identification.

Import of pin delay properties in front end in Allegro Design Authoring DE-HDL

A new DE-HDL console command is now provided to import a file containing the pin delay values that can be used to define the complete delay for pin pairs. The format of this file is exactly the same as that one used for import/export by PCB Editor.

Support for page-level team design with Allegro Design Authoring Team Design Option

A significant advancement in Allegro design management features is the ability to manage designs at the page level, for both hierarchical and flat designs.

Graphical Design Difference Viewer in Allegro Design Entry Capture

Graphical Design Difference Viewer is a powerful, real-time, design difference, visual review utility in Allegro Design Entry Capture with the ability to perform logical as well as graphical comparisons on a page-by-page basis.

Advanced Annotation in Allegro Design Entry Capture

With the newly introduced Advanced Annotation feature supported by Allegro Design Entry Capture, users can assign reference ranges hierarchically by automatically assigning values and perform annotation on the whole design, on hierarchy block at any level.

PSpice virtual prototyping in Allegro AMS Simulator

New functionality introduced in PSpice® helps to overcome design challenges for electrical engineers by automating the code generation for multilevel abstraction models written in C/C++, SystemC.

New pin assignment options in FPGA System Planner

A new “FSP Bundle Swap” option is available. If the two bundles are the same size, the PCB designer can select the bundles and ask the FPGA System Planner engine to swap them, pin for pin. FPGA System Planner 17.2 also offers three new manual pin-swapping algorithms: show all destination pins, show all destination pins in the same bank, and two-pin selection.

Create custom connectors with user-defined groups and pin types in FPGA System Planner

Users can now create complex connector models with user-defined pin types and signal group capabilities.

Team design capability integrated into Allegro DE-HDL

All of the team design functionality is now built directly into Allegro Design Authoring DE-HDL. Team members can stay within DE-HDL to check out/in designs using menus integrated into the DE-HDL hierarchy viewer or by using a design dashboard. And users have the ability to manage designs at the page level, for both hierarchical and flat designs.

Hierarchical split symbol support

Hierarchical split symbols can now be managed with Allegro Library Manager.

Support for managing the “standard” library

Allegro EDM 17.2 now supports the standard library that contains the page borders, ioports, taps, power symbols, etc., so that librarians can not only manage these parts, engineers can stay connected to the database to select them.

Label Management

Track changes to a shared design project or design object by using labels to mark key stages or milestones. Labels can be used to mark anything, such as marking a design for review or marking it as having been reviewed. The administrator can predefine the labels to be sure everyone is consistent across all projects.

Unicode Support

Multi-byte Unicode support for Japanese and Chinese characters has been added for all non-ECAD/PTF properties and their values.

Easy Classification Editing

Cut, copy, and paste operations are now available as pop-up menu options. Revisions of classifications are now created for linked objects based upon distribution state and obsolescence.

Explore rigid-flex features of Allegro PCB Editor where you can create multiple zones using the Cross-Section Editor to represent rigid-flex-rigid PCBs and stack-up by zone for faster, easier definition of stack ups and improved MCAD-ECAD co-design