The Interrupt Mask Register (IMR) and Interrupt Service Register (ISR) are responsible for firing up different IRQs. The IMR bits line up with the ISR bits to work in sync. If an IMR bit is low, then the corresponding ISR bit with never fire an IRQ when the time comes for it to happen. The IMR is located at 0x3C and the ISR is located at 0x3E.

The Interrupt Mask Register (IMR) and Interrupt Service Register (ISR) are responsible for firing up different IRQs. The IMR bits line up with the ISR bits to work in sync. If an IMR bit is low, then the corresponding ISR bit with never fire an IRQ when the time comes for it to happen. The IMR is located at 0x3C and the ISR is located at 0x3E.

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The NF81-T56N-LF is a IPC form factor embedded board:

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* AMD Fusion G-T56N (1.65 GHz dual core) APU

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** 2x SO-DIMM sockets for DDR3 800-1066 SDRAM (Fixed at 1.5V)

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** VGA and LVDS (via Analogix ANX3110)

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* AMD A55E (Hudson-E1) southbridge

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** 6x USB 2.0/1.1 ports

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** 5x SATA3 6Gb/s, 1x mSATA socket

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** 6-Channel HD Audio (via VIA VT1705)

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** PCI and ISA (via ITE IT8888)??

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** NEC uPD78F0532 microcontroller on I2C ("SEMA")??

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* 2x RJ45 GbE (via Realtek RTL8111E x2)

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* Fintek F71869AD Super I/O

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** PS/2 KB/MS port

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** RS232 header (via Unisonic UTC 75232 RS232 driver/receiver)

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** GPIO header

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** CIR header

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* 1x MXIC MX25L1606E (SO8, soldered) 16 Mbit SPI flash (BIOS)

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Note: MX25L1606E is 16Mbit, 8bits in a byte, so 2MB. Jetway '''''lies'''''

Issue Analysis

pcie 06.0 bridge hang issue

The pcie 06.0 bridge hang issue is the primary remaining issue.

The Interrupt Mask Register (IMR) and Interrupt Service Register (ISR) are responsible for firing up different IRQs. The IMR bits line up with the ISR bits to work in sync. If an IMR bit is low, then the corresponding ISR bit with never fire an IRQ when the time comes for it to happen. The IMR is located at 0x3C and the ISR is located at 0x3E.