UROP Openings

ADC+FPGA for Micro-location IoT (Focus: EE)

Term:

Summer

Department:

MAS: Media Arts and Sciences

Faculty Supervisor:

Fadel Adib

Faculty email:

fadel@mit.edu

Apply by:

May 7, 2020

Contact:

Mergen Nachin; mergen@mit.edu

Project Description

This UROP project will focus on developing an ADC+FPGA pipeline for signal acquisition and processing in micro-location.
This project builds on our recent work TurboTrack, which enables tracking and localization of objects using wireless signals with unprecedented speed and accuracy. Check the following links for more details: http://news.mit.edu/2019/robots-track-moving-objects-unprecedented-precision-0219
Responsibilities:
The responsibilities of this position will include:
(1) developing Verilog code for ADC signal acquisition on Xilinx
(2) writing Verilog code for signal processing
(3) remote testing of system performance.

Pre-requisites

Prerequisites (ordered by importance):
- Proficient in Verilog on Xilinx FPGA
- Proficient in Python or C++
Preferred but not hard prerequisites:
- Background in Algorithms and Machine Learning
- Background in Signals and Systems is a plus but not necessary