AMD’s new Opteron 6100 series processor line, which was called “Magny-Cours” throughout its development, targets high-end server computing and contains the largest number of cores to date in a single x86 architecture chip. Several major server vendors, including Acer Inc., HP Co., Cray Inc. and Dell Corp., are expected to announce Opteron-powered systems in the coming weeks.

In addition to officially launching the latest Opteron chip on Monday, AMD also held a customer panel event in San Francisco which featured insight from a few AMD customers who are testing the new chips.

Matt Lavallee, director of technology at Shrewsbury, Mass.-based real estate data provider MLS Property Information Network Inc., said with houses staying on the market for longer than usual, the company needs to support twice as much bandwidth as it did 18 months ago.

While the additional cores are more expensive, this cost is easily offset by the decrease in SQL server costs. He said that he could reduce his 60 servers by about a third, which would “drop SQL server costs by about $100,000 per box.”

For Bruce Wright, chief technology officer at Mountain View, Calif.-based Kosmix Corp., power is the number one limiting factor in the data centre. “With the new Magny-Cours servers, we’ll get a five-to-one server reduction,” he said.

The need for high throughput is also a major factor in workload optimization on Magny-Cours, said Bruce Nelson, director of database management at Los Angeles-based online retail firm Shopzilla Inc.

Nelson said he was especially impressed with AMD’s HyperTransport technology link, which aims to improve processor-to-processor communication among four-processor servers. He added that he is now “pushing 6GB a second of throughput” with Magny-Cours.

Lavallee agreed, saying that the Magny-Cours chips are a huge step up in terms of bandwidth.

“On one box, you can cram far more VMs that can talk to each other,” he said. “Right now, we’re comfortable stacking 12 to 20 VMs per box, but (with Magny-Cours) we’re looking at 30 to 40.”

In theory, while more cores should lead to faster processing, some of the panelists acknowledged the challenges in properly parallelizing their workloads to take advantage of the additional cores.

“It’s not that easy,” Wright said. “The clock-speed war that we had in the last decade is now over, but it masked a lot of poor programming.”

During that time period, he said, every program would get faster as clock speeds increased. In today’s environment, however, users have to write code to take advantage of multiple cores.

Lavallee said that IT shops can use virtualization to “cheat” and run multiple nodes in parallel on the same core.

Despite this tactic, Nelson said the ability to separate workloads is an area that needs some attention. He also said that other areas like storage, the network, and peripherals represent the “weakest link of the chain” in terms of increasing I/O throughput and processing speed.

The spotlight will continue to stay on the high-end processor market later this week as AMD’s rival, Intel Corp., is expected to launch its own eight-core Nehalem-EX server chip.