>>>EOI is a more "high level" thing that some "intelligent" PICs that>>>automatically raise the priority do to restore the priority to what it>>>was before the interrupt occured.

>> Thank you, I know. Even 8259 has the notion of priority and EOI works the >>same way here.

> Ok, so why would you need an ack there then while eoi is just what you> need ? :-)

Don't ask me, ask the genirq authors. :-)

> Also, that's interesting what you are saying about 8259... I should be> able to convert ppc's i8259 to use fasteoi too...

I'm not sure it's feasible. The idea behind level/edge flows is to eliminate the interrupt priority I think. That's why they EOI ASAP (with the level handler masking IRQ before that) -- this way the other interrupts may come thru. I used to think that fasteoi was intended for SMP PICs which are intelligent enough to mask off the interrupts pending delivery or handling on CPUs and unmask them upon receiving EOI -- just like x86 IOAPIC does. This way, the acceptance of the lower priority interrupts shouldn't be hindered on the other CPUs. Maybe the scheme is different for OpenPIC (I know it has the different interrupt distribution scheme from IOAPIC)?