Several of Jasper’s “Intelligent Proof Kits” assertion-based verification IPs was also employed. Specifically, the IPKs for ACE, AXI3, APB, and ATB.

Key verification tasks

Exhaustive verification of clamp value correctness during isolation.

Prove data integrity for the interface slices.

Verify interface protocol certification in all valid power states.

Methodology

(Re-)Use the same formal verification environment for both low power and baseline functional verification.

However, for the low power-centric analysis some additional constraints had to be added.

Results

Formal low power verification setup was completed within couple of days (in contrast to the weeks corresponding simulation test benches would have taken to write and debug).

Within the first hour of the analysis the Low Power Verification App surprised us by unearthing problems with some clamp values thought to be correct.

The low power aspects of APB, AXI3, ACE & ATB interface slices for protocol correctness and data integrity were exhaustively proven to be valid in all power states.

In summary, as advertised, Jasper’s Low Power Verification flow “has improved our power-aware verification coverage with reduced cycle time.” An added benefit was/is that the reuse of the power-aware properties for future projects/derivatives is easy. The assertions are in IEEE standard SVA and very easy to modify. Finally, another unexpected bonus of this process was how easy it was for engineers who were completely new to formal technology to take advantage of its power.

Taking a step back, this success story is but one of 14 user presentations delivered at the Jasper User’s Group meeting. The paper topics were a mix of novel, “pure formal” verification methodologies, and deep dives on specific apps like the story recounted above.

To see them for yourself, they are posted on Jasper’s Formal Expert site (registration required).