Abstract
Moore’s Law has been fundamental in driving the information age explosion in the last 50 years. As the CMOS feature enters the era of extreme scaling (14nm, 11nm and beyond) for “More Moore,” IC manufacturability challenges are exacerbated, with the adoption of double/multiple patterning and other emerging lithography technologies. Meanwhile, the vertical scaling with 3D-IC integration using through-silicon-vias (TSVs) has gained tremendous momentum, which can further extend the conventional Moore’s Law (“More than Moore”) even if the feature size scaling stops ultimately. Furthermore, new material/devices such as nanophotonics are making headways to the ultimate on-chip integration. All these require new VLSI CAD tools and methodologies. This talk will present some recent results to push the envelope using multiple patterning lithography as well as other emerging technologies, such as 3D-IC and optical interconnects. Cross-layer modeling and CAD tool/methodologies will be discussed to achieve future heterogeneous integrated circuits and system integration.

Biography
David Z. Pan received his Ph.D. in computer science from UCLA in 2000. He was a Research Staff Member at IBM T. J. Watson Research Center from 2000 to 2003. He is currently a Full Professor and Brasfield Endowed Faculty Fellow with the Department of Electrical and Computer Engineering, UT Austin. He has published over 190 refereed journal and conference papers. He has served as an Associate Editor of several IEEE transactions (TCAD, TVLSI, TCAS-I, TCAS-II), IEEE CAS Society Newsletter, Science China Information Sciences, Journal of Computer Science and Technology. He has served as Chair of the IEEE CANDE Technical Committee and the ACM/SIGDA Physical Design Technical Committee, Program/General Chair of ISPD, Subcommittee Chair for DAC, ICCAD, ASPDAC, ISLPED, ICCD, ISCAS, and so on. He is a working group member of the International Technology Roadmap for Semiconductor (ITRS). He serves in the 2014 ACM/IEEE Design Automation Conference (DAC) Executive Committee.
He has received a number of awards, including the SRC 2013 Technical Excellence Award for his significant contributions in "Nanometer IC Design for Manufacturability," 10 Best Paper Awards (ICCAD 2013, ASPDAC 2012, ISPD 2011, IBM Research 2010 Pat Goldberg Memorial Best Paper Award in CS/EE/Math, ASPDAC 2010, DATE 2009, ICICDT 2009, SRC Techcon in 1998, 2007 and 2012), DAC Top 10 Author in Fifth Decade, DAC Prolific Author Award, Communications of the ACM Research Highlights (2014), ACM/SIGDA Outstanding New Faculty Award (2005), NSF CAREER Award (2007), SRC Inventor Recognition Award three times, IBM Faculty Award four times, UCLA Engineering Distinguished Young Alumnus Award (2009), ISPD Routing Contest Awards (2007), eASIC Placement Contest Grand Prize (2009), ICCAD’12 and ICCAD’13 CAD Contest Awards, among others. He is an IEEE Fellow.