If resistive memory of any type is able to challenge silicon as the solid state memory of choice at sub 20nm with 3D or stacked matrices, then progress towards that goal will depend on developing a thin-film matrix-isolation device that can act as a “sneak path” blocker. This will be more challenging if the memory element requires bipolar operation. Such was the problem addressed by a number of papers at IEDM 2013. Some solutions presented were either to use a bipolar threshold switch or to find some way of modifying the current carrying capability of a diode to selectively allow current to flow when required. (This solution is even better when the matrix isolation device is integral with the memory switching mechanism.) Of the many papers at IEDM exploring all aspects RRAM/ReRAM challenges, the following two point the way forward.

Paper 10.4 at IEDM 2013 from universities in Taiwan and Windbond Electronics was particularly noteworthy because the authors addressed the problem of integrating the memory and matrix isolation device by the use of a Ta-TaO thin-film diode. Then they went the extra mile by successfully addressing the additional problems of creating a 3D structure as well as removing forming and filaments from the mix. The structure is illustrated in Figure 1 as a small section of the matrix.

Figure 1: Illustration of the structure in paper 10.4 showing the integration of the memory and matrix isolation device with a Ta-TaO thin-film diode.

The memory array is fabricated by initially depositing alternate films of SiO and titanium, shown colored blue and orange in Figure 1. Those films are then etched into a line structure, where the titanium layers serve as one of the orthogonal electrodes of the memory matrix. Films of TiO2, TaOx, and Tantalum are deposited over the complete structure. Next, those three films are etched in lines orthogonal to the initially deposited films to create the matrix structure. The Tantalum (green in Figure 1) is the other electrode of the matrix. As shown in the Figure 1 inset, the memory and matrix isolating device is formed on the side walls of the vertical pillars. In this example, two stacked cells are created at each matrix crosspoint.

One of the keys to success (and the metric by which all progress in bipolar matrix isolation devices must be measured) is the rectification ratio. In this case, values of 103 were reported. The set and reset voltages were +5 and -6 volts respectively, with write currents of less than one micro-Amp possible. The on-to-off ratio was just over one order of magnitude, with values of 8 x107 to 3x 108 Ohms. Write/erase (W/E) endurance was 109 cycles using a 1micro-sec write pulse, with retention for only 104 secs at RT reported.

The approach to addressing individual devices within a projected 10Mbit matrix did away with the conventional ½V write signal on each orthogonal bit and word line in favor of 1/3, 2/3 and a ¼, ¾ schemes. These two new schemes reduced the bias on the sneak path devices to 1/4V.

Paper 10.5 featured the joint efforts from members of universities in Korea, Japan, and the US (Stanford). Their work looked at a two-pronged approach to the possible solutions to next generation 3D ReRAMs. One option was the used of a separate memory and isolation device, the so called 1R/1S approach employing TaOx /NbO2. The other was a hybrid NbO2/Nb2O5. A first was the use of conventional electrode materials like tungsten (W) and TiN that avoids the past difficulties associated with processing platinum. The basic structures are shown in Figure 2. Including two insets that are a conceptual view of the mechanism that involves the movement of oxygen ions to create and remove vacancies.

Figure 2: The basic structures proposed for 3D ReRAMs in paper 10.5.

In Figure 2, for illustration purposes and to show three separate structures, I have shown a link between the titanium electrodes of the TaO memory and the NiO selector to create the 1R/1S structure. In the paper, this was shown as a close-coupled continuation of the electrode structure.

This group reported a very high level of symmetry in the bipolar resistance switching (BRS) characteristics of the hybrid structure. That is a little surprising considering the structure is not perfectly symmetrical. There was an even higher level of symmetry for the threshold switch alone.

The TaOx device showed no perceptible change in on- or off-state resistance after 10,000 secs at 85 C. The 1S/1R structure was evaluated at 85 C using different read voltages, Vread and 1/2Vread while there was some small statistical variation in the high resistance state for devices written at 1.6Volts. Those written at 0.6V showed no detectable changeover the same period of time.

The conclusion was that although the 1R/1S structure offers what is claimed as the high reliability of the TaO ReRAM with the “outstanding” threshold switching of the NbO2, it is a complex process. However, the hybrid device (Nb2O5/NbO2) can be formed from a simple stack structure, but the control of oxygen concentration will be the key to success.

Current densities of 10 MegaAmps/sq-cm and the need for “heat confinement” design might be considered as causes for concern. The thermal design requirement was presented in a positive way as a means of reducing threshold current.

Summary

For Tantalum and Niobium based ReRAMs, oxygen is both the hero and villain of the piece. Understanding the effects of its movement electrically or concentration gradient driven now appears to be the key to further progress. It is interesting to note that, although the hybrid devices from both papers use the movement of oxygen ions and the creation of oxygen vacancies for different materials, in the case of the Nb2O5/NbO2 hybrid, no mention of the benefit of rectification from Shottky barrier modulation is acknowledged.

There is now a good consensus that the movement and interchange of oxygen ions and vacancies at an interface accounts for the memory effect. The degree to which this is a 2D surface effect versus a filament effect is still questioned. In addition, the degree to which unwanted and unintended defects can localize an inherently surface interface effect into a filament is one possible way of accounting for the difference.

An exciting pointer to the way ahead is shown in one of the insets to Figure 2, where threshold switching is accounted for as a reversible metal-to-insulator transition (MIT) attributed to the Jahn-Teller effect and a NbO rutile-to-distorted-rutile structural transition that occurs at ~800o C.

Whether it is Jahn-Teller, Mott-Hubbard, or Charge Transfer matters little. For this writer, it is the direction to move if we are ever to unify the memory spectrum and produce a URAM, a memory that combines non-volatility with write/erase speed. The open question is can the band splitting that occurs for threshold switching be made to stick and produce a reversible non-volatile effect? There are some that claim it can in doped NiO and the correlated electron based RAM (CeRAM). So the remaining question is: Is it time for the electronics industry to start to move out of its uncorrelated electron silicon based comfort zone?

Resistion- If, by not practical, you mean that it is not possible to fabricate such a structure then you might be right. Although not included in my review above, I looked at the practicality of the problem of the cumulative thickness of layers building up on the side walls of the vertical structure. Although the devices in the paper are relatively large I did considered a device where the minimum feature size (F) was 20nm, still much larger than where next generation NV memory must go. I also assumed it would be possible to reduce the side wall layer thickness for the TiO,and TaOx to 10nm and I did not leave a centre space; that is I completely filled in the space between the two facing sidewalls of TaOx with tantalum. For a two cell structure this would give a single cell size of a little over 5/2F2, compared with the 4F2 for a simple 2D crossover matrix. The practicality of the repeatable deposition of 10nm films (about 70 atoms thick) on the vertical side walls and then in-filling a deep, high aspect ratio, 10nm wide space between two TaOx surfaces with tantalum is non trivial but in a gedankenexperiment anything is possible.

Resistion: The authors of the 3D Vertical TaOx/TiO2 RRAM paper in their list of claims for their devices stated "forming free, self rectifying, self compliance and highly stable BRS."

I did not investigate the details of the compliance claims any further because I assumed that for some time ahead the array would be monolithically integrated with silicon and the memory array driver/decoder circuits would take care of providing compliance.