Comments

Ths old comment was quite screwed up. Replace it with a new version
that should be a bit more descriptive.
Signed-off-by: Stefan Roese <sr@denx.de>
---
arch/powerpc/cpu/ppc4xx/start.S | 26 ++++++++++++++------------
1 files changed, 14 insertions(+), 12 deletions(-)

Patch

diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.Sindex 65195f5..d77272c 100644--- a/arch/powerpc/cpu/ppc4xx/start.S+++ b/arch/powerpc/cpu/ppc4xx/start.S@@ -48,21 +48,23 @@
*-------------------------------------------------------------------------------
*/
-/* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards- *+/*+ * Startup code for IBM/AMCC PowerPC 4xx (PPC4xx) based boards
*
- * The processor starts at 0xfffffffc and the code is executed- * from flash/rom.- * in memory, but as long we don't jump around before relocating.- * board_init lies at a quite high address and when the cpu has- * jumped there, everything is ok.- * This works because the cpu gives the FLASH (CS0) the whole- * address space at startup, and board_init lies as a echo of- * the flash somewhere up there in the memorymap.+ * The following description only applies to the NOR flash style booting.+ * NAND booting is different. For more details about NAND booting on 4xx+ * take a look at doc/README.nand-boot-ppc440.
*
- * board_init will change CS0 to be positioned at the correct- * address and (s)dram will be positioned at address 0+ * The CPU starts at address 0xfffffffc (last word in the address space).+ * The U-Boot image therefore has to be located in the "upper" area of the+ * flash (e.g. 512MiB - 0xfff80000 ... 0xffffffff). The default value for+ * the boot chip-select (CS0) is quite big and covers this area. On the+ * 405EX this is for example 0xffe00000 ... 0xffffffff. U-Boot will+ * reconfigure this CS0 (and other chip-selects as well when configured+ * this way) in the boot process to the "correct" values matching the+ * board layout.
*/
+
#include <asm-offsets.h>
#include <config.h>
#include <asm/ppc4xx.h>