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AR# 64509

MIG UltraScale RLDRAM3 - timing and bus efficiency improvements available if traffic pattern is known and will not violate tWTR or tRC

Description

For RLDRAM3 IP designs having difficulty meeting data bus efficiency requirements, there is a TWTR_CHECK parameter that can be turned off which disables the memory controller from adhering to the tWTR timing specification.

This can in turn improve efficiency and overall throughput, but can only be used if the RLDRAM3 traffic pattern is known and guaranteed not to violate the tWTR.

Solution

If the traffic pattern is not known or is random, then TWTR_CHECK should be turned ON to prevent any tWTR spec violations which will cause data errors in both simulations and hardware.

To disable the tWTR check and improve your read efficiency, the following parameter located in <ip_name>_rld3.sv should be set: