HDMI® and PHY IP Cores

Silicon Image pioneered the HDMI (High Definition Multimedia Interface) specification to enable the transmission of premium digital content over an uncompressed, secure digital video and audio interface. It was the first company to ship HDMI-based chips and the first to provide HDMI functionality for consumer products. Additionally, Silicon Image is the primary author of the HDMI Compliance Test Specification, and hosts numerous HDMI Authorized Testing Centers worldwide, putting the company in a unique position to drive full compatibility among HDMI-enabled products. Silicon Image offers HDMI Transmitter and Receiver IP cores that include the digital logic and analog PHY. In addition, Silicon Image is the only company offering low-cost HDMI digital-only IP cores for use with an external PHY semiconductor provided by Silicon Image. These configurations offer both a lower bill-of-material cost and faster time-to-market at reduced technical risk compared to the use of discrete HDMI transmitter or receiver chips.

The Dual-mode HDMI Receiver and MHL Receiver IP core was developed to support two HD video connectivity standards - MHL and HDMI. In HDMI mode, Silicon Image's Dual-mode Receiver IP core supports HDMI 1.4a features, including all mandatory and optional 3D video formats and all 4Kx2K formats. The dual-mode IP core also supports HDMI Ethernet Channel to send and receive data via 100 Mbps Ethernet over an HDMI cable, while Audio Return Channel allows a TV to send audio streams from the TV to an HDMI attached A/V receiver for improve sound. The built-in Consumer Electronics Control (CEC) connection allows the user to operate multiple devices with one remote control.

In MHL mode, the dual-mode IP core supports video resolutions up to 1080p, allowing mobile devices such as smartphones, HD camcorders and portable media players to display HD content by connecting to HDTVs using existing connections. The built-in Remote Control Protocol (RCP) connection enables the user to operate multiple devices with one remote control.

The dual-mode IP core supports all relevant audio formats up to 8-channel digital audio, while its color space converter allows convenient interfacing with most video interfaces. The core is configurable, providing SoC designers access to multiple internal interfaces and hardware blocks, potentially reducing integration time and gate count. The core includes digital logic, analog GDSII, models, software and documentation. The first implementations of GDSII will be in 55 nm and 65 nm processes. In addition, this IP core supports High-bandwidth Digital Content Protection (HDCP) for both HDMI and MHL modes.