1) Use two pin headers, one pin is GND the other the signal. Where
Differential signals are involved, place the headers back to back, so a
common
differential probe can pick up the two hot signals directly. Spacing of the
headers is .1 inch, which is standard for modern TEK or HP equipment. Place
the headers in line with the signal and you'll get absolute minimum SI
disturbance. This implies usage of a high impedance active probe with low
C.

2) Use AMPs Mictor connector. You get 38pins of relatively high density
controlled impedance connection. This connector is used by both HP and TEK
logic
analyzers. In the board layout process, give the layout fellow the liberty
of re-assigning the pins, so the most natural flow through connection can be
made. This approach introduces SI effects which are related to how you do
your interconnect. Be careful with your stubs. If you have a simulator,
you
can check this. Else, just keep them as short as possible and double check
for rise time vs prop delay down the stub.

I have to provide test points for a 16-bit parallel datapath,
which are all single-ended LVPECL. The bus is synchronous,
and associated clocks and control are differential LVPECL, and
signals are 155 MHz, typical of SONET/SDH.

The test points would ideally be headers of some sort, but
signal integrity is a priority. It makes me nervous to route
the signals across the board to convenient test headers.
Is there a technique for doing this, or should I employ a
conservative approach?
I have been browsing Howard Johnson's book, High-Speed Digital Design,
and am aware of the section on "Embedded fixtures for Probing" p.103

Is this technique suitable for LVPECL, either single-ended
or differential? I have observed differential signals before,
but they were slow in comparison to these speeds. What special
considerations are there for observing high-speed differential
signals?

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