Nanometer IC technologies are on the horizon. They promise a lot. But will cost a lot as well. Therefore, we need to ask today: How may the billions of dollars we will have to spend on namometer-fablines and how will this affect the IC design domain? This talk (which is a repetition of a Design Automation Conference presentation) attempts to address the above question by analyzing the design-manufacturing interface. A partial answer is derived from a simple transisitor cost model proposed in the body of the DAC paper. Two observations of fundamental importance will be formulated during the talk. First, is that we need to refocus the IC design domain from a short time-to-market objective to cost minimization. Such design must be guided by an adequate cost objective funtion and performed using all design variables influencing some measure of design density and yield simultaneously. The second observation is that the design cost itself must be carefully controlled. It will be suggested in the talk that the first major steps towards this goal should be the development of new design styles supported by CAD tools that use highly regular, repetitive (across many products) and experimentally pre-characterized design building blocks.

Bio
Wojciech Maly is a Whitaker Professor of Electrical and Computer Engineering. His research interests have been focused on the interfaces between VLSI design, testing and manufacturing with the stress on the stochastic nature of phenomena relating these three VLSI domains.

W. Maly has been the recipient or co-recipient of various awards but he is most proud of two of them: Carnegie Mellon's Benjamin Richard Teare Teaching Award and Eta Kappa Nu CMU Sigma Chapter Excellence in Teaching Award.