Pin Description

Name

Type

Description

CLK

Input

Core clock signal

CEN

Input

Synchronous enable signal. When LOW the core ignores all its inputs and all its outputs must be ignored.

MODE

Input

When HIGH, the START will initiate a pseudo-random generate operation based on the initial seed (normal mode). When LOW, the START going high will force a true random re-seed (external entropy can also be applied via the SEED input).

START

Input

Starts the core operation

RESET

Input

Asynchronous core reset

SRESET

Input

Synchronous core reset

QREADY

Input

External circuitry is ready for the data

DONE

Output

Indicates the completion of a re-seed or generate operation

Q[ ]

Output

Output of pseudorandom data

QVALID

Output

Core is driving valid data on the Q bus

SEED[ ]

Input

Input of seed data. Ignored in the normal mode.

SVALID

Input

Seed data is valid

FAULT

Output

Internal seed source is not operational

Function Description

TRNG1 can be operated in two modes: forced re-seeding and normal. During the normal operation, asserting START causes the core to output the random numbers on its Q output. The numbers are produced by the random number generator based on internal entropy source and the data on the SEED input. Re-seeding in the normal mode occurs automatically.In the forced re-seeding mode the internal entropy source is directly used to generate the random numbers.

Available Versions

The TRNG1 core is available in with different datapath widths and throughputs.