CPFSK demodulation and synchronization

I am trying to build a binary CPFSK demodulator with self synchronization.
Modulation index is not fixed. I kind of prefer coherent demodulation, but
not sure how to do the synchronization.
The following is some understandings I have during the literature survey, I
appreciate if I can get some comment on my understandings.
1. One type of coherent demodulation I know of is ZCD based and using
Viterbi algorithm for symbol detection, but the Viterbi algorithm
computation complexity increases rapidly if modulation index h is a
rational number h=p/q, and when q is big. Say if h=0.3, then the trellis
diagram involves 20 states.
2. Another technique is correlation receiver as stated in the paper
"Coherent and Noncoherent detection of CPFSK" by William P. OSBORNE. If I
observe 3-5 bit symbol period, seems I can obtain near-optimum BER
performance. But I am not sure how to do timing and carrier synchronization
in this case. Can anyone help me on this?
3. I also tried to use a Costas loop to lock to the carrier and timing.
What I did is compute the derivative of the phase of the incoming signal,
and tried to use a Gardner timing error detector to sync the timing as
mentioned in this thread:
http://www.dsprelated.com/showmessage/125137/1.php
But when I observe the derivative of the phase it is very noisy even when
EbNo=20dB.
So I wonder what BER performance I am going to get using this method.
Can this synchronization technique be used with the correlation receiver in
2?
Thanks. a lot

Posted by Steve Pope●December 2, 2010

gobruins <chunmei.kang@n_o_s_p_a_m.gmail.com> wrote:

>I am trying to build a binary CPFSK demodulator with self synchronization.
>Modulation index is not fixed. I kind of prefer coherent demodulation, but
>not sure how to do the synchronization.

What is your preamable design like? How long are your packets?
Is it rectangular or shaped? And (perhaps most importantly) what is
the frequency offset?
Steve

Posted by gobruins●December 2, 2010

It is rectangular pulse, not sure how many samples per bit, it is
programmable. Modulation index can be any number from 0 to 1. It is really
a generic CPFSK demodulator. And I am looking for a demodulator and
synchronization technique which would give me a reasonably good BER
performance, and suitable for SDR application.
Seems if I use correlation receiver I would need many samples per bit
period, but using Viterbi algorithm, only the phase sampled at the end of
each bit period is required. Is it right?
ZCD detector requires large over clocking within the bit period.
For the problem I have is it necessary to use a coherent demodulator? If i
choose to use correlation receiver based demodulator, what type of clock
and carrier synchronization method I can use?
From the reference I read that I can also use a noncoherent correlation
receiver which does not require carrier sync, and if I observe 5 bit symbol
interval then I could loss less than 0.5dB, is it true? If in this case
again what type of clock synchronization I can use.
If I want to use costas loop type of synchronization, in the decision stage
is there any ML type of decision method that gives better performance than
hard decision? The reason I am hesitating using this sync technique is the
BER performance.

>>Modulation index is not fixed. I kind of prefer coherent demodulation,

but

>>not sure how to do the synchronization.
>
>What is your preamable design like? How long are your packets?
>Is it rectangular or shaped? And (perhaps most importantly) what is
>the frequency offset?
>
>
>Steve
>

> It is rectangular pulse, not sure how many samples per bit, it is
> programmable. Modulation index can be any number from 0 to 1. It is really
> a generic CPFSK demodulator. And I am looking for a demodulator and
> synchronization technique which would give me a reasonably good BER
> performance, and suitable for SDR application.
>
> Seems if I use correlation receiver I would need many samples per bit
> period, but using Viterbi algorithm, only the phase sampled at the end of
> each bit period is required. Is it right?
>
> ZCD detector requires large over clocking within the bit period.
>
> For the problem I have is it necessary to use a coherent demodulator? If i
> choose to use correlation receiver based demodulator, what type of clock
> and carrier synchronization method I can use?
> From the reference I read that I can also use a noncoherent correlation
> receiver which does not require carrier sync, and if I observe 5 bit symbol
> interval then I could loss less than 0.5dB, is it true? If in this case
> again what type of clock synchronization I can use.
>
> If I want to use costas loop type of synchronization, in the decision stage
> is there any ML type of decision method that gives better performance than
> hard decision? The reason I am hesitating using this sync technique is the
> BER performance. &#2013266080;
>
>
>
> >gobruins <chunmei.kang@n_o_s_p_a_m.gmail.com> wrote:
>
> >>I am trying to build a binary CPFSK demodulator with self
> synchronization.
> >>Modulation index is not fixed. I kind of prefer coherent demodulation,
> but
> >>not sure how to do the synchronization.
>
> >What is your preamable design like? &#2013266080;How long are your packets?
> >Is it rectangular or shaped? &#2013266080;And (perhaps most importantly) what is
> >the frequency offset?
>
> >Steve

One non-coherent approach is to use a differential detector followed
by a decision feedback equalizer (DFE). The output from the
differential detector could be sampled at twice the baud rate before
being fed to the DFE, and the phase of of the sampling doesn't have to
be controlled because the DFE will adapt.
This method may not be generic enough for you because it works best
with signals that contain a preamble.
Darol Klawetter

Posted by Vladimir Vassilevsky●December 2, 2010

gobruins wrote:

> It is rectangular pulse, not sure how many samples per bit, it is
> programmable. Modulation index can be any number from 0 to 1. It is really
> a generic CPFSK demodulator. And I am looking for a demodulator and
> synchronization technique which would give me a reasonably good BER
> performance, and suitable for SDR application.
>
> Seems if I use correlation receiver I would need many samples per bit
> period, but using Viterbi algorithm, only the phase sampled at the end of
> each bit period is required. Is it right?
>
> ZCD detector requires large over clocking within the bit period.
>
> For the problem I have is it necessary to use a coherent demodulator? If i
> choose to use correlation receiver based demodulator, what type of clock
> and carrier synchronization method I can use?
> From the reference I read that I can also use a noncoherent correlation
> receiver which does not require carrier sync, and if I observe 5 bit symbol
> interval then I could loss less than 0.5dB, is it true? If in this case
> again what type of clock synchronization I can use.
>
> If I want to use costas loop type of synchronization, in the decision stage
> is there any ML type of decision method that gives better performance than
> hard decision? The reason I am hesitating using this sync technique is the
> BER performance.

1. Equalizers and ML algorithms like Viterbi or such do make sense only
if there is some kind of memory in the channel. This memory includes
transmit/receive shaping filters, error correction and channel encoding,
and multipath propagation effects. If there is no memory, there is
absolutely no point in using such algorithms.
2. With or without Viterbi, the first thing to do is lock on the carrier
and symbol sync. Unless you are after something very special, the
Gardner and Costas trivia works just as good as anything else.
3. You already have all books, references and received a lot of good
advice here. What is exactly do you need?
Vladimir Vassilevsky
DSP and Mixed Signal Design Consultant
http://www.abvolt.com

Posted by Vladimir Vassilevsky●December 2, 2010

Darol wrote:

> On Dec 2, 11:52 am, "gobruins" <chunmei.kang@n_o_s_p_a_m.gmail.com>
> wrote:
>
>>It is rectangular pulse, not sure how many samples per bit, it is
>>programmable. Modulation index can be any number from 0 to 1. It is really
>>a generic CPFSK demodulator. And I am looking for a demodulator and
>>synchronization technique which would give me a reasonably good BER
>>performance, and suitable for SDR application.
>>
>>Seems if I use correlation receiver I would need many samples per bit
>>period, but using Viterbi algorithm, only the phase sampled at the end of
>>each bit period is required. Is it right?
>>
>>ZCD detector requires large over clocking within the bit period.
>>
>>For the problem I have is it necessary to use a coherent demodulator? If i
>>choose to use correlation receiver based demodulator, what type of clock
>>and carrier synchronization method I can use?
>>From the reference I read that I can also use a noncoherent correlation
>>receiver which does not require carrier sync, and if I observe 5 bit symbol
>>interval then I could loss less than 0.5dB, is it true? If in this case
>>again what type of clock synchronization I can use.
>>
>>If I want to use costas loop type of synchronization, in the decision stage
>>is there any ML type of decision method that gives better performance than
>>hard decision? The reason I am hesitating using this sync technique is the
>>BER performance.
>>
>>
>>
>>
>>>gobruins <chunmei.kang@n_o_s_p_a_m.gmail.com> wrote:
>>
>>>>I am trying to build a binary CPFSK demodulator with self
>>
>>synchronization.
>>
>>>>Modulation index is not fixed. I kind of prefer coherent demodulation,
>>
>>but
>>
>>>>not sure how to do the synchronization.
>>
>>>What is your preamable design like? How long are your packets?
>>>Is it rectangular or shaped? And (perhaps most importantly) what is
>>>the frequency offset?
>>
>>>Steve
>
>
> One non-coherent approach is to use a differential detector followed
> by a decision feedback equalizer (DFE). The output from the
> differential detector could be sampled at twice the baud rate before
> being fed to the DFE, and the phase of of the sampling doesn't have to
> be controlled because the DFE will adapt.

He uses RECTANGULAR pulses. What is the point of DFE ?

> This method may not be generic enough for you because it works best
> with signals that contain a preamble.

Any method works with or without preamble. Preamble is a small matter of
convenience, no more then that.
VLV

>> This method may not be generic enough for you because it works best
>> with signals that contain a preamble.

> Any method works with or without preamble. Preamble is a small matter of
> convenience, no more then that.

Traditionally it was used to give the PLL something to lock to
before the actual data started. That explanation doesn't work for
continuous signal systems, such as newer ethernet, though.
Another is that it allows a little delay for a repeater.
I believe that is true for USB. Each additional hub loses some
preamble bits, though there will still be some left at the end.
-- glen

> Darol wrote:
> > On Dec 2, 11:52 am, "gobruins" <chunmei.kang@n_o_s_p_a_m.gmail.com>
> > wrote:
>
> >>It is rectangular pulse, not sure how many samples per bit, it is
> >>programmable. Modulation index can be any number from 0 to 1. It is really
> >>a generic CPFSK demodulator. And I am looking for a demodulator and
> >>synchronization technique which would give me a reasonably good BER
> >>performance, and suitable for SDR application.
>
> >>Seems if I use correlation receiver I would need many samples per bit
> >>period, but using Viterbi algorithm, only the phase sampled at the end of
> >>each bit period is required. Is it right?
>
> >>ZCD detector requires large over clocking within the bit period.
>
> >>For the problem I have is it necessary to use a coherent demodulator? If i
> >>choose to use correlation receiver based demodulator, what type of clock
> >>and carrier synchronization method I can use?
> >>From the reference I read that I can also use a noncoherent correlation
> >>receiver which does not require carrier sync, and if I observe 5 bit symbol
> >>interval then I could loss less than 0.5dB, is it true? If in this case
> >>again what type of clock synchronization I can use.
>
> >>If I want to use costas loop type of synchronization, in the decision stage
> >>is there any ML type of decision method that gives better performance than
> >>hard decision? The reason I am hesitating using this sync technique is the
> >>BER performance. &#2013266080;
>
> >>>gobruins <chunmei.kang@n_o_s_p_a_m.gmail.com> wrote:
>
> >>>>I am trying to build a binary CPFSK demodulator with self
>
> >>synchronization.
>
> >>>>Modulation index is not fixed. I kind of prefer coherent demodulation,
>
> >>but
>
> >>>>not sure how to do the synchronization.
>
> >>>What is your preamable design like? &#2013266080;How long are your packets?
> >>>Is it rectangular or shaped? &#2013266080;And (perhaps most importantly) what

is

> >>>the frequency offset?
>
> >>>Steve
>
> > One non-coherent approach is to use a differential detector followed
> > by a decision feedback equalizer (DFE). The output from the
> > differential detector could be sampled at twice the baud rate before
> > being fed to the DFE, and the phase of of the sampling doesn't have to
> > be controlled because the DFE will adapt.
>
> He uses RECTANGULAR pulses. What is the point of DFE ?

Even with rectangular modulating pulses, isn't a DFE beneficial
because of the memory required to implement CPFSK?

>
> > This method may not be generic enough for you because it works best
> > with signals that contain a preamble.
>
> Any method works with or without preamble. Preamble is a small matter of
> convenience, no more then that.

With a preamble, cannot the DFE train faster and with greater accuracy
than using a blind technique (e.g. constant modulus)? This would lower
BER, especially for bursty signals.

>
> > Any method works with or without preamble. Preamble is a small matter of
> > convenience, no more then that.
>
> With a preamble, cannot the DFE train faster and with greater accuracy
> than using a blind technique (e.g. constant modulus)? This would lower
> BER, especially for bursty signals.
>
>

I have already learned DSP theory. Preamble is not needed, so
preamble does nothing to help/hurt signals. I think poreambles are put
into system to justify some asshole system engineer salary.