We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Firefox,
Internet Explorer 11,
Safari. Thank you!

Solution

General Information

There is currently no support for simulation of the Soft Error Mitigation Controller. Functional and timing simulation of a design, including the controller, compiles, but the controller does not exit the initialization state. There is no support for partial reconfiguration when using the Soft Error Mitigation Controller. For further information on unsupported features and limitations, see Chapter 9 of the Soft Error Mitigation Controller User Guide (UG764).

The Soft Error Mitigation Controller has been verified using production Virtex-6 FPGA devices. Use of this core on Engineering Silicon (ES) devices is not supported due to a silicon errata item regarding "Configuration Readback". The core might not work at all on ES devices, and if it does, its operation might be unreliable.Therefore, this core must not be used in ES silicon for any purpose other than evaluation. If you are using this core on an ES device for evaluation and you encounter a problem, please obtain a production device. For more information, refer to the Virtex-6 FPGA CES Errata at: http://www.xilinx.com/support/documentation/virtex-6.htm#131587.

The following devices are supported by the core for this release:

Virtex-6 XC CXT/LXT/SXT/HXT

Virtex-6 XQ LXT/SXT

Virtex-6L XC LXT/SXT

New Features

ISE 12.4 software support.

Core status changed to "production".

Resolved Issues

CR578075: VHDL example design file "sem_ext_byte.vhd" contained a logic error. This file is only present if VHDL output products are generated and the coreconfiguration requires an interface with external SPI flash.