Two input clocks (K and K#) for address and control
registering at rising edges only.
Two output clocks (C and C#) for data output control.
Two echo clocks (CQ and CQ#) that are delivered
simultaneously with data.
+1.8V core power supply and 1.5, 1.8V VDDQ, used
with 0.75, 0.9V VREF.

Read/write address

Read enable

Write enable

Byte writes for burst addresses 1 and 3

Data-in for burst addresses 1 and 3
The following are registered on the rising edge of the K#
clock:

概觀

The 18Mb IS61QDB451236C and IS61QDB41M18C are
synchronous, high-performance CMOS static random access
memory (SRAM) devices. These SRAMs have separate I/Os,
eliminating the need for high-speed bus turnaround. The
rising edge of K clock initiates the read/write operation, and
all internal operations are self-timed. Refer to the Timing
Reference Diagram for Truth Table for a description of the
basic operations of these QUAD (Burst of 4) SRAMs.
Read and write addresses are registered on alternating rising
edges of the K clock. Reads and writes are performed in
double data rate. The following are registered internally on
the rising edge of the K clock: