High-speed parallel fast Fourier transform/inverse fast Fourier transform (FFT/IFFT) module has become one of the most significant obstacle to practically developing realtime high-speed optic orthogonal frequency division multiplexing (OOFDM) system based on field programmable gate array (FPGA) platform due to its high complexity. This paper builds a simulation platform for OOFDM transceivers and realizes joint optimization of the IFFT and FFT module to reduce logic resource usage. The algorithm shortens word-length boundaries to reduce the time for searching optimized word-length and builds a mapping
table of the optimal word-lengths. Error between simulation results and verification results on an offline platform is within 0.5 dB indicating correctness of the proposed optimization algorithm. In addition, the FFT module based on the mapping table saves about 37.2% resource compared to the Spiral design.