Monthly Archives: February 2018

Embedded World 2018, Nuremburg, Germany–February 26, 2018. Ashling Systems (a subsidiary of the NeST Group) and Imperas Software today announced a partnership to provide integrated tools and solutions for RISC-V software development. The technology aspects of this alliance include the integration of Imperas’ high-performance virtual platforms, simulation engines and models into Ashling’s own RiscFree™ IDE and tools offering. On the business side, Ashling will promote, sell and support this new, comprehensive, turnkey solution spanning the solutions of both companies.

As leaders in the RISC-V initiative, both companies believe that the market demands an expanded ecosystem, a turnkey solution, and one-stop shopping for RISC-V development tools. Ashling is taking the lead in promoting and selling its RiscFree™ IDE integrated solution for RISC-V software development, debug and modeling.

“We are excited about our new closer relationship with Ashling in expanding the RISC-V ecosystem and market. Imperas simulation solutions and verification models, combined with Ashling tools, offer many benefits to RISC-V customers. It is essential for RISC-V silicon developers to use commercial grade high quality simulation solutions and Ashling’s worldwide sales and marketing outreach will leverage these benefits,” commented Simon Davidmann, CEO of Imperas Software.

“It’s great to be partnering with the leader in processor models and virtual platforms for embedded software development,” said John Murphy, Managing Director of Ashling Microsystems Ltd (Ireland)

“Our integration with Imperas brings Ashling closer to our vision to become the provider of a complete RISC-V turnkey solution,” said Guy Rabbat, President and CEO of Ashling Systems Corporation.

“We are proud that the Ashling team focuses on the future and where technology is heading, versus just the current situation. This alliance is a strong reflection of our ambition at NeST/Ashling to always look at where the ball is going to be, not where the ball is,” said J.K. Hassan, Chairman of the NeST Group.

RISC-V is an open architecture ISA under the governance of the RISC-V Foundation. It comes with many benefits such as enabling the open source community to improve and test embedded cores, ensuring trust and certifications, and portability at no additional cost.

“We are happy to see this alliance between two major members of our RISC-V Foundation. RISC-V has the potential to change the way SoCs and embedded systems are developed, and the business models around that. To achieve this potential, a solid ecosystem is needed, including RISC-V community members working together to build solutions that are greater than the sum of the individual pieces,” said Rick O’Connor, Executive Director of the non-profit RISC-V Foundation.

Ashling now delivers everything needed to develop a RISC-V application using either a real-time setup environment or pre-hardware simulation and modeling environment. Ashling debug tools will now include full IDE, RISC-V compilation, RTOS-aware debugging, JTAG probe, trace, and the full suite of simulation and hardware modeling.

Ashling’s RiscFree™ IDE for RISC-V is now available directly from Ashling. For more information, visit www.ashling.com

The latest in the Imperas line of RISC-V EPKs, the RV64GC Linux platform can boot Linux in under five seconds on a regular personal computer, allowing for applications to be executed at reasonable performance levels without the need for an actual RISC-V hardware device. Click here to view a video demonstrating Linux booting on the EPK.

“The RISC-V movement has tremendous potential but it is absolutely reliant on a robust ecosystem, including early software development solutions,” noted Simon Davidmann, President and Chief Executive Officer, Imperas Software, Ltd. “Imperas has uniquely solved this problem, providing RISC-V developers with commercial-grade processor simulation to accelerate software verification as well as hardware validation.”

The Imperas EPKs include source and binary models of specific RISC-V processor families from various companies, the high-performance OVPSim simulator, models of key platform components and operating system software. Models are available for the entire family of RISC-V processors as well as those from leading processor vendors. The processor model instruction set can be easily extended externally to the basic model code, allowing for fast updates and easy maintenance.

“The Imperas release of the first commercial simulator that can boot Linux on a RISC-V ISS model represents a significant milestone in the evolution of processors based on the RISC-V RV64GC ISA,” said Rick O’Connor, RISC-V Foundation executive director. “A key element of the RISC-V ecosystem is a robust, commercial virtual software development environment and Imperas has delivered on this promise.”

Imperas virtual platform products provide for a broad range of software verification and profiling capabilities. Model code coverage and instruction coverage enable an effective measure of software verification quality to be established. A broad range of profiling tools, including timing performance and power consumption, allow for effective quality metrics to be established, prior to hardware availability. An advanced debug solution is also included with advanced features designed specifically for complex multi-core software.

The Imperas RISC-V RV64GC Linux EPK will be demonstrated on the Imperas booth number 3A-419 at the Embedded World Conference held in Nuremberg, Germany on February 27th, 2018.

Abstract: Historically, architectural estimation, analysis and optimization has been done using either manual spreadsheets, hardware emulators, FPGA prototypes or cycle approximate/accurate simulators. Instruction-accurate software simulation, or virtual platforms, have the speed necessary to cover the range of system scenarios, can be available much earlier in the project, and are typically 5x less expensive than cycle approximate or cycle accurate simulators. Previously, because of a lack of timing information, virtual platforms could not be used for timing estimation. We report here on a technique for dynamically annotating timing information to the virtual platform results, achieving accuracy of better than +/-15%.

2. Virtual Platform Environment for the Bring Up and Test of a Secure Many-Core RTOS (Real Time Operating System), authored by Atsushi Shinbo and Shuzo Tanaka of eSOL TRINITY, Masaki Gondo of eSOL, Duncan Graham and Larry Lapides of Imperas Software.

When: February 28, 2018.

Abstract: The increasing numbers of cores in the individual SoCs, the move to multiple SoCs in Electronic Control Units (ECUs) and the increase in complexity of software for automotive electronics has led to the need for many-core support for RTOSs. In addition, security requirements on systems directly flow to security requirements on the RTOS. This increasing complexity of hardware, software and security requirements, magnifies the challenge to bring up and test the RTOS and basic software. This paper reports on the use of a virtual platform (software simulation) -based environment for bring up and testing of a secure, many-core RTOS on an ECU. The RTOS is the eMCOS RTOS from eSOL, the hardware represented in the virtual platform comprises two Renesas RH850F1H devices (SoCs), and the virtual platform tools are from Imperas.

For more information, or to set up meetings with Imperas at Embedded World, please email info@imperas.com.

Embedded World is the world’s leading meeting place for the embedded systems community. In its 16th year, the theme reflects the unbroken innovative power of the industry: “Embedded goes autonomous.” From a wide range of sensors all the way to embedded vision, systems are increasingly becoming aware of their environment, making independent decisions, and using actuators to engage with the world around them. The conference covers all aspects of the development and application of embedded systems, from basic technologies, to the development process, to special application areas. See www.embedded-world.eu for details.