Intel’s Shishpal Rawat has been Chair of Accellera for 6 years and is currently serving as President of CEDA, IEEE’s Council on Electronic Design Automation. In previous discussions, Rawat has insisted that his leadership is not what makes these organizations work. Only the enthusiastic efforts of the many members guarantee that both Accellera and CEDA continue to shape ideas, standards, and forward progress within design automation and its adjacent technologies.

Two years ago, I enjoyed a lengthy interview with Rawat about all of this, described here. This year, I’ve chatted with Rawat at DVCon in San Jose in March, and again by phone just prior to DAC in June. During the phone call, Rawat focused on CEDA’s activities at DAC in Austin. He told me the upcoming Sunday night panel, set to be moderated by SRC’s Bill Joyner on June 5th, was a new and very exciting addition to the DAC program.

Many know that last year at DAC in San Francisco, CEDA hosted a fascinating evening event – a competition between teams of academics whose proposals for further research into the EDA Blue Sky were judged by the audience and a panel of industry experts.

On our recent phone call in June, however, Rawat said the competition format would not be repeated this year at DAC. Instead, the 2016 CEDA evening event would showcase a different kind of excitement – that of young professionals in EDA offering optimism and career advice to up-and-coming technologists interested in hearing about opportunities in both academia and industry.

“This will be a new event we are trying out for the first time,” Rawat said. “Hopefully it will inspire students attending DAC to view the many different option available for their careers.”

He certainly sold me on attending the program in Austin where thanks to Bill Joyner and his speakers, the panel proved to be everything Rawat had promised and more. Again, a significant contribution to DAC from the folks at CEDA. [CEDA Panel: Covering new ground at DAC 2016]

Meanwhile, in our pre-DAC phone call Rawat also mentioned the upcoming Young Faculty Workshop in Austin. Sponsored by CEDA, as well as Cadence, ACM-Sigda, and NSF, this is a long-standing event that holds a special place in the hearts of all academics laboring away in EDA.

I asked Rawat if he would be attending.

“Unfortunately,” he said, “I have a CEDA meeting that I must attend all day on Sunday, so I will miss the Faculty Workshop.”

He seemed sharply disappointed by that schedule conflict, so I laughed and asked what could possibly take all day to hash out at a CEDA meeting on the first Sunday of DAC.

Rawat replied graciously, “One important part of the day is for CEDA’s Executive Committee to review the progress that has been made in our conferences – including DAC and ICCAD – our publications, journals and so on, and various technical activities in our chapters. Where we have been and where we want to go.

“Later in the day, we will make presentations to CEDA’s Board of Governors with suggestions for changes to the magazines, and other such things.”

“By the way,” he added, “the Board of Governors meeting is open to the public – typically all IEEE members who attend DAC. If you want to attend, you would be welcome.”

Again I laughed, “I’ve already over-spent $200 to register for the Sunday Workshop on Cyber-Physical Systems in Austin, so I can’t attend the CEDA meeting, but thank you!”

I asked Rawat to remind me how long CEDA has been around, and how does he perceive its impact on the industry to date.

He said, “We are in our 11th year – and yes, we have definitely had an impact. Previously, all of these efforts were spread across various societies within IEEE. But with CEDA, we have been able to focus on the growth areas in the technology.

“We serve our community well, paying close attention to the conferences we participate in and evolving our magazines, in particular IEEE Design & Test.”

“CEDA is also responsible for IEEE Embedded Systems Letter, the IEEE Transactions on Computer Aided Design of Integrated Circuits & Systems, and we are sponsors of both DAC and DATE.”

He said, “Yes, EDPS is another excellent conference,” and added that attending these types of focused meetings is part of his responsibilities as CEDA president, keeping tabs on what topics and trends are of interest.

“And Accellera,” I asked, “how are things progressing there?”

Before he answered, I reminded him that one definition of a workaholic might be someone who has a full time job, yet serves in a leadership role in two different technical societies.

Rawat laughed, “Well, at Accellera we are very busy trying to pull off DVCon in China.

“Of course, we have already launched in Europe and India, but we are still working out the details in China. There are definitely challenges, but we think we will have one there in 2017.”

Word on the street, I offered, is that DVCon India and DVCon Europe has both been very successful.

Rawat confirmed: “Yes, they have been very successful, thanks in large part to a lot of effort from the local communities there.

“Because those communities have the responsibility for setting their agendas from year to year – whether it be tools, technology, standards – the engineers who are attending the conferences in India or Europe are definitely learning things that are useful for their work.”

Do engineers glean equally practical info from DAC, I asked.

Rawat replied, “At DAC, there is some focus for the practicing engineer, and some focus for academia – here is where the tools currently work well, and where they can be improved.

“But what you see in a DVCon program is where the industry is going with UVM, SystemC, AMS, and so forth – topics that are very pragmatic. That has always been the focus for DVCon.”

But why, I asked, does there have to be a divide? Why can’t a conference embody the joining together of the academic and the pragmatic?

“When does a research idea reach the practitioner, is what you are really asking,” Rawat answered, invoking his own professional experience.

“I’ve been at Intel in strategic planning and funding for a very long time. I’ve seen new ideas over the years take a lot of time to develop into something that practicing engineers can use.

“But new ideas from academia need a gestation period. Anything that develops in academia is still only an idea or a concept, something that can take years to develop.

“And it takes even more time to be implemented in software, often 6-to-7 years to mature into something robust enough for an engineer to use.”

Rawat re-iterated that DAC and DVCon serve different purposes along the evolutionary time line of design technologies.

“DVCon, and things like DesignCon, are types of conferences where practical topics of verification and validation can be discussed,” he said.

“DAC, however, sets out a different set of goals.”

We ended our chat with the question journalists love to ask of people who work in the EDA user community: What do you do if the tools from third-party vendors don’t evolve fast enough?

Rawat took off his CEDA and Accellera hats, and put on his Intel one instead: “If the tools aren’t there, it has always been the case that people will develop them internally.

“The EDA industry, therefore, has to figure out where the majority of their users and customers are – they usually will develop tools for that clientele.

“But still, if there’s something unique that’s needed – a solution for a unique problem that the commodity solutions can’t address – then yes, the company has to develop a solution internally.

Knowing Rawat will be involved with both CEDA and Accellera for the foreseeable future, I asked him to predict where CEDA, Accellera – and Intel – would be 5 years from now.

“Actually, I am working in a group at Intel that is looking at all of the components of design that the company needs – IP, design tools, lab equipment, professional services.

“As companies like Intel, and organizations like CEDA and Accellera, work on all of this – it is pretty exciting today. And that will definitely still be the case in 5 years!”

Clearly Shishpal Rawat is committed to continued progress in design automation everywhere from academia to industry, and in the conferences and communications that knit these communities together. But surely he can’t always be calm and carrying on.

Are you very organized, I asked, hoping to unearth something like an Achilles heel in an individual who wears three different hats with such cool aplomb.

Again, gracious to a fault, he laughed and answered: “I am not unorganized.”

Mentor Graphics’ Tom Fitzpatrick gave a lunchtime talk at DVCon several weeks ago summarizing recent efforts to build a standard [set of standards?] around portable stimulus for verification. The room was packed with over 200 people and his talk was sufficiently complete, nobody asked any questions.

After his presentation, however, I did hear some comments. Namely that these types of standards are quite complex and difficult to develop. Hence, setting an actual delivery date of January 2017 for Portable Stimulus Standard Version 1 [PSS V1] is quite aggressive and optimistic.

I was not fully informed about Accellera’s Portable Stimulus Working Group [PSWG] prior to Fitzpatrick’s talk, so could not judge whether January 2017 is or is not overly optimistic as a delivery date for the standard. Since DVCon, I have studied the slides and attempted to better understand what this is all about: What is a Portable stimulus and what would a set of standards look like?

To answer those questions, I looked most closely at Slide No. 4, seen here: A Proposed Portable Stimulus Diagram.

Per the diagram, users can be any of the following: system architect, hardware, analog, or software developer, verification engineer, software test engineer, or post-silicon validation engineer. Each of these individuals may create an abstract portable stimulus model with specific syntax to reflect their requisite model parameters, and in so doing declare a use case and/or desired visualization mode.

That ‘model statement’ is then dumped into the design team’s amalgamated design tool set (can remain proprietary despite the ‘standardization’ of the process), which in turn generates a series of tests, targeted at various facets of the verification environment: UML/SysML, SystemC, HVL/UVM, C/C++, and/or AMS.

Reading further into the diagram, this verification environment – the one that’s going to crunch on the generated test sets – can be sitting on one or more platforms: a virtual platform, some sort of simulation engine, an emulation box, an FPGA prototyping platform, and/or a silicon board (whatever that is).

And that’s what I’ve gleaned so far from looking at Slide No.4.

That, and a high-level understanding of what Accellera is calling the ‘scope’ of the Portable Stimulus Standard. It includes middleware, operating systems and drivers, ‘bare-metal’ software, the hardware and software which together constitute an SoC, any type of ‘sub-system’, and/or the IP which is used to build any of the above.

Hmm. There’s a distinct wow factor in all of this, it’s so comprehensive. And it precipitates an unfortunate circling back around to my initial impression upon hearing Tom Fitzpatrick’s talk at DVCon: How can one standard, or set of standards, possibly cover all of this?

This proposed standard, or body of standards, will be so all-inclusive of everything and everyone involved in chip design and verification, it seems almost impossible to assemble – not to mention, be ready for prime time by January of next year.

Meanwhile, four companies on the list are vying to have their contributions to the standard be evaluated and accepted: Cadence and Mentor working as a team [promoting a domain-specific language that combines C++ and SystemVerilog intuitions], Breker [has a declarative C++ proposal], and Vayavya [suggesting a complementary syntax to generate register sequences, firmware and driver routines from a canonical/standard hardware/software interface description].

Again, this whole effort seems massive to me. Not just establishing the flow and detailed specs for a Portable Stimulus Standard, but sorting through the politics of corporate posturing/positioning, each party involved hoping to craft a document that most closely matches their internal technology road maps.

Nonetheless, let’s end on a positive note. Intel’s Faris Khundakjie, Mentor’s Tom Fitzpatrick, and Breker’s Tom Anderson – respectively the PSWG Chair, Vice-Chair, and Secretary – are three among many who deserve high praise for having the stamina and enthusiasm to go after this standard.

Listening to Tom Fitzpatrick speak on February 29th, it was clear: It’s not a question of whether the standard can be developed, but if it can be developed within the declared time frame. Which is why Accellera’s PSWG is proving, yet again, that technologists who work on standards are the salt of the earth.

They’re the ones who shun the glamour in favor of getting authentic work done, producing results that help make the world work together. Realists and optimists, the lot of them.

You would probably have learned more about Ajoy Bose by reading his biography than by attending Jim Hogan’s gentle exercise in collegiality on Tuesday night, March 1st, in Silicon Valley. The conversation between these two giants of EDA, hosted by EDAC as part of DVCon week, was consistently unstructured, whimsical and seemingly without outline.

The next day, I sat in a coffee shop and struggled to find a handle with which to write a coherent summary of the previous night’s random access memory album. But that handle would not reveal itself.

Then I happened to glance over to a nearby table where another caffeine addict was buried in a book: The Man Behind the Microchip. I asked the addict who exactly was the subject of the book and the answer came back: Robert Noyce.

So Robert Noyce is the man behind the microchip, I pondered. The only man behind the microchip? Like Steve Jobs invented the iPod/iPad/iPhone? Or Thomas Edison invented the electric light?

No wonder, I realized, it was hard to get a handle on the previous night’s Hogan/Bose interview. They didn’t do anything. Robert Noyce did it all. And without help. Hogan and Bose did nothing, and ergo had nothing to offer their audience.

These two were not part of a vast conspiracy of contributors, all adding their particular drips and drops of innovation into the trickle of technology, that rolled into a small creek of creativity, that ran into a moderate-sized stream of science-turned-engineering, which poured into a roaring river of real change, which crashed into a seething sea of twenty-first century digital life.

Of course, that’s nonsense. Robert Noyce did not do everything, and Hogan and Bose did not do nothing.

A week went by, and it felt increasingly wrong to leave the March 1st event unaddressed. So I revisited my notes from the evening, typed them up to examine them for fundamental truths, and took comfort in knowing that Graham Bell video-taped the dialog for posterity.

After all, my notes were only a snapshot of that unstructured, whimsical and seemingly without-outline conversation between Jim Hogan and Ajoy Bose. I may not have understood the random walk of their random access, but there have to have been fundamental truths expressed there.

And once typed up, it was clear; the fundamental truth was clear. Thousands and thousands of Hogans and Boses have contributed to the current instantiation of technical life. True, not all of them are lionized [foolishly] as The Man Behind the Microchip, and many thousands of have not contributed to an extent that warrants beings showcased on a stage in Silicon Valley.

But Hogan and Bose fall into neither of these categories. They have indeed contributed, and are worthy of being showcased. They’ve been part of the process of progress, yet have also been refreshingly candid about the unscripted nature of their contributions to the craft of business, technology, and creativity. They do not lay claim to fundamental truths, just stories and results – some successful and some not so much.

And that’s the reality about The People Behind the Microchip.

***************1 March 2016 …

Jim Hogan: I really respect this man. Tonight we will showcase several data points in his life. Record his knowledge. Let’s start, Ajoy, with your dad. An engineer, right?

Ajoy Bose: Yes, he was an engineer in a steel plant in India. Back then, there were just five IIT campuses in India, now there are 15. After WWII, however, India realized the [power in technology] and began to invest in engineering education.

Jim Hogan: Yes, back in the days when India was aligned with the Soviet Union.

Ajoy Bose: I came to the U.S. to do my PhD at UT Austin and fell in love with barbecues. I also learned the rules for American football [and fell in love with that too].

I didn’t have a clue at the time what EDA was, but I stumbled on a professor who introduced me to the technology – Steve Szygenda. He absolutely sold me on the glamour of EDA. Here 40 years later, I don’t just like EDA, I love EDA.

I also still love everything Texas, barbecues and football. I’ve been a Longhorn, and a fan of the Dallas Cowboys ever since.

[Laughing] In fact, when I first went looking for Office space, Roger Staubach – retired from football – was working in commercial real estate. I used his firm to get the Gateway Place office. I met Staubach several times, and even have a football autographed by him.

Jim Hogan: Hence, the Atrenta kick-off at Levy Stadium?

[Jim acknowledged that legendary SPICE author Larry Nagler was in the audience.]

Ajoy Bose: Yes, I worked with Larry a lifetime ago at Bell Labs. I went there in 1977 [drawn by the fact that] it’s where the transistor originated with William Shockley and John Bardeen.

Jim Hogan: Industry doesn’t do those types of research labs anymore. And we can’t rely on government to do that kind of work either.

Ajoy Bose: Yes, [back in the day], you worked on something in the lab and then saw it get used. But it’s not possible for companies to fund those kinds of labs today. Boards of directors [have squeezed corporate budgets] and made it impossible to continue.

Today, the best research is being done in academia. We’re depending on them [to continue the critical research], backed by the power and support of industry.

Jim Hogan: So your story takes us from India, to Texas, to New Jersey, to Boston and Gateway [acquired by Cadence in 1989].

Ajoy Bose: [Remember that] the proliferation of Verilog was built on two major thrusts. Compaq and Motorola were constantly on Cadence’s case to attend to SPICE and timing.

It was a lot of work [after we were acquired]. EDA tools were very glamorous [at the outset], but there is more than just a little grinding away at the details to make it all functional. So I decided to leave Cadence, particularly because I was getting interested [in the dynamics associated] with startups.

When I first was at Bell Labs, it was the largest non-governmental organization in the world with 1 million people. Then I went to Cadence with only 2000 people. From there, I went to a startup with only 2 people. But by that point, I had figured out how [things] really worked.

I started Interra in 1995 – bootstrapped it — and learned [the requisite skills for running a startup] via association with colleagues in Silicon Valley. But we had cash flow problems and so liquidated it quickly. [But out of that] grew Spyglass and Atrenta. And in all of this, I had only one mission in life – to build great EDA tools.

Through all of this, I also had two mentors, a technology mentor in Hermann Gummel, the first Kaufman Award winner, and a business mentor in Mike Hackworth from Cirrus Logic who recently won the Morris Chang Medal.

Mike was the one who taught me how to create and run a business, how to meet the people [who could help make a company successful], and most importantly – how to sell.

Jim Hogan: Always at a Board of Directors meeting you have three kinds of people – the tech founders, the VCs, and the ‘outside’ guy. The Board needs the technology founders, needs the investors, and definitely needs the ‘outside’ guy who will play [the devil’s advocate] in conversations.

Ajoy Bose: Yes, and someone with the knowledge about how to move the product across domains and platforms. As industries work up to these changes, it helps companies – it helped our company – to see growth momentum.

Jim Hogan: Okay, so your best advice to people in this room who are considering doing a startup?

Ajoy Bose: Be aware where the industry is going, and recognize opportunities as they show up. Know that you’ll never quite get it right when you build a business. The process is about building a technology, it’s not about ever being done and finished.

Sell the company quickly. Perhaps we waited too long to sell Atrenta, but we [wanted to grow] it to a decent size. A company that we would be remembered for after we are gone. Of course, if you don’t need a lot of money, you can take your time.

Jim Hogan: Yes, the founders can work for free for a few years – however long it takes to turn $4 million into $40 million.

Ajoy Bose: Also, decide carefully between building a great product and building a family of products. There will never be the same return [on a family of products] as on a small number of successful products. You’re never going to have a good ROI on everything on your platform, so you sometimes have to take a hard look at decide [what to eliminate].

Big is not always beautiful. Sometimes, small and quick is beautiful.

***************Epilogue …

Many years from now, no one will remember an evening in March 2016 when Jim Hogan interviewed Atrenta founder Ajoy Bose. No one will remember Atrenta was sold to Synopsys, or the companies in Bose’s life that came before Atrenta, his research, contributions to technology, or even remember Synopsys for that matter.

What they will remember, however, is the growth of technology. How one thing led to another, how tubes led to transistors, which led to integrated circuits, which lead to VLSI design, miniaturization, high-speed computation, email, the Internet, personal computing devices, the Cloud, the growth of Big Data and Big Data storage, WiFi, tablets, smart phones, a universe of mobile devices, and eventually the IoT.

Nope, nobody will remember the players, but they’ll sure as hell remember the plays.

***************Read more …

The Man Behind the Microchip: Robert Noyce and the Invention of Silicon Valley
by Leslie Berlin [2005]

Emulation is everything in verification today and therefore at the center of DVCon. Technology expert, Lauro Rizzatti, has prepared this brief tutorial for you, so you’ll be ready for the conference that starts on February 29th.

* The Past

Hardware emulation has been around for 3 decades. It started in the mid 80s with pioneers like Quickturn and Ikos, who used off-the-shelf FPGAs in the fabric of their emulators. The second decade saw the rise of several startups, some of them using custom silicon devices in the emulators.

Toward the end of the second the decade, consolidation left only 3 players on the market: Mentor and Cadence promoting custom-based emulators, and EVE using commercial FPGAs. In the third decade, Synopsys acquired EVE.

Over the past 30 years, the emulation technology evolved in two directions: hardware and software.

On the software side, emulators became easier to use, their usability improved, they expanded the deployment mode beyond in-circuit-emulation (ICE), and they supported remote access. The cost of emulators measured on a per-gate-basis, historically very high and a barrier to entry, has decreased dramatically to the point where pricing is about a penny per gate.

Once limited to large corporations developing very large digital (not analog or mixed-signal) designs such as processor and graphics – by the end of the third decade, emulators had been adopted by most segments of the electronics industry.

* The Present

Today, all three main EDA players offer emulators, although each is based on a unique architectural approach (Cadence, custom processors; Mentor Graphics, custom emulator-on-chip; Synopsys/EVE, commercial FPGAs) that can be used in several modes of deployment and can perform a multitude of verification tasks.

Emulators are being used to address everything from hardware verification to hardware/software integration, system validation, functional coverage analysis, low-power verification, power estimation, design-for-testability [DFT] fabric and test vector verification, performance characterization, and more.

The setup time, once a drawback that prevented or hindered the adoption of the technology, is now in the order of one or few days. Virtually all segments of the electronics industry use or can use emulation today.

Emulation is considered a high-value resource, able to alleviate unnecessary risk. As a result, it is considered cost-effective with an easily justified ROI.

* The Future

Emulators will continue to increase in capacity, speed, versatility, usability, and deployment modes.

Now seen as main stream verification tools, emulators will be tightly integrated into a suite of verification engines, sharing a common compiler (or at least a common front-end compiler), a common GUI, and a common database.

Undefeated by designs sizes, emulators will be used more and more in ICE, acceleration, system validation, functional coverage, SystemVerilog assertions, low-power verification, power estimation, DFT and test-vector verification, and performance characterization.

Finally – to further increase the ROI, emulation access will be increasingly offered via large data centers.

Sometimes you just gotta wonder what happens behind the closed doors of the executive suite. Last June, when Synopsys acquired Atrenta, Atrenta’s founder – a distinguished technologist, alum of IIT Kanpur, UT Austin, Bell Labs, Cadence and Interra, and profoundly well-seasoned EDA leader – closed the door on his leadership role at the company he founded 14 years before.

I will admit, I do not know if Dr. Ajoy Bose actually ever reported to duty at Synopsys last summer – the received wisdom would have us believe he needed to set foot there long enough to help his team transition into the Big Purple – but in truth, it is hard to imagine him ever playing second fiddle to Dr. Aart de Geus or Dr. Chi-Foon Chan, or anyone else for that matter. He is a man of that much dignity and gravitas.

Of course, if Bose did punch a time clock at Synopsys, it was for nary a nanosecond in geologic time. It’s been 9 months since the acquisition and now Bose is clearly free to speak in public about the past, present and future of the industry he has helped to create. That surely would not be happening if Bose was just a node in the org chart that has Chan and de Geus at the top of the pyramid.

So there’s one half of the good news included herein.

The other half is this: For the absolutely extraordinary convenience of the lucky ducks who will be at DVCon from February 29th to March 4th, they needn’t drive anywhere to hear Bose speak publicly on Tuesday evening, March 1st. Given the mind-numbing nature of the traffic in Silicon Valley in these boom times, the opportunity to not get into a car to seek out a different venue for the Tuesday evening EDAC event is pure gold.

Folks just have to duck out of the DVCon Happy Hour Exhibition Hall at 6 pm, seek out a nearby ballroom in the very same DoubleTree Hotel, enjoy EDAC’s hospitality in the food and wine category, and be in their seats by 7 pm – on the edge of their seats, no doubt – to see the Charlie Rose of EDA, Jim Hogan, help Dr. Bose plumb his years of success for kernels of truth that those in the audience will hopefully use to navigate their own successes going forward.

Hogan will help showcase Bose’s remarkable – dare we say, encyclopedic – knowledge of the n-dimensional process of translating obtuse technical solutions into thriving commercial enterprises. How the magic happens, in this case the EDA magic.

So add up the two halves of good news: Add Bose to Hogan to DVCon, and house them all under one roof, and you will see why you’ll only have yourself to blame if you don’t know more at the end of the first week in March than you did at the end of the last week in February.

Bose founded Atrenta in 2001. He began his career at AT&T Bell Laboratories in Murray Hill, N.J. and spent 12 years in a series of increasingly responsible positions ending as department head, IC Design Automation Department. From AT&T, he moved to Cadence Design Systems where he served as VP of Engineering. In this role, he managed and led the team that pioneered the Verilog simulation products. Prior to establishing Atrenta, Dr. Bose was founder and president of Software & Technologies, Inc. and Interra, Inc. During his tenure as Chairman and CEO of Interra, Dr. Bose incubated and spun out a number of successful ventures in EDA, Digital Video, and IT services.

Bose received a BSEE from the IIT Kanpur, which awarded him the Distinguished Alumni award. He received an MS and a PhD in
Electrical and Computer Engineering from the University of Texas at Austin.

What if I were to tell you that I attended a conference where people were really excited to be there, where the exhibit hall was filled with a crush of people making their way from booth to booth, talking with exhibitors and exchanging business cards madly. A conference where the South of the exhibit hall was dominated by Synopsys, the East by Cadence, and the West by Mentor, and where at the happiest hour, libations and snacks flowed freely in a sub-set of the booths and the whole exhibit hall became even more animated.

What if I told you the technical portion of the conference included a variety of content — touching at times on autos, wearables, the IoT, IP, standards, and verification — excellent panel discussions, well-attended poster sessions, detailed tutorials, and a keynote from the CEO of the largest company in the industry delivered to a packed, SRO ballroom full of designers, engineers, and engineering managers.

Finally, what if I told you the highly capable staff of MP Associates was running the whole thing with their usual aplomb, attending to details as diverse as registration, sound systems, lunch tickets, speaker logistics, and awards presentations.

If I told you all of this and you guessed I was talking about DAC, an event that fancies itself the Grandaddy of all EDA conferences, you would be wrong. But if you guessed instead I was talking about DVCon 2015, you’d be square-on correct.

And you wouldn’t be alone. More than one person this week, in and out of sessions at the Double Tree in San Jose, commented on the energy, the attendance, and the joie de vivre (well, maybe they didn’t use that exact term, but that’s what they meant) at DVCon, while simultaneously lamenting that this is what DAC used to feel like, but unfortunately no longer does.

They said DAC’s lost its energy, its freshness, and its relevance as a venue for communication, networking, or even for sales. So much so, that at least one long-time industry contributor told me he may not even go to DAC this year in San Francisco in June. So where does that leave us?

Well, let’s tick off the characteristics of DVCon 2015. I’m guessing around 1200 people were there over the course of the 4-day event, lots of designers and verification people because that’s what the D and the V stand for. In the areas of headcount and quality of attendees, therefore, DVCon 2015 is within shouting distance of similar metrics for recent editions of DAC.

Particularly if you factor in attendance at the two other annual conferences, the one in India and the one in Europe, that will now be part of the year-round DVCon cycle.

Then there’s the cost. Everybody and his brother knows that it’s wildly expensive to exhibit at DAC, with ponderous booths-on-steroids that are expensive to design, construct, staff, and then de-construct.

When DAC’s in San Francisco, in particular, the costs are over the top: food, labor, and housing all painfully expensive for everybody. Compare the ROI on those costs with what I saw at DVCon this week.

Yes, the SCaM booths have grown in size over the last several years, but many of the other 35 booths in the exhibit hall were simple table-top alcoves where the conversation was about the software and/or services of the exhibiting company, not about how many strobe lights, barkers, or comely talents could be assembled to guarantee the kind of sensory overload that’s become de rigueur for DAC.

Nobody complained to me this week about the costs of exhibiting at DVCon. What a contrast to DAC, where complaining about the costs of exhibiting has become a national pastime over the last few years all across the EDA Nation.

Finally, there’s the energy co-efficient. It’s true that for the sake of contrast I’m saying DVCon’s abuzz and DAC is not, although that’s not completely accurate.

Certainly, however, if you look at the mission statement for DAC — “The premier conference for design and automation of electronic systems [with] outstanding training, education, exhibits, and superb networking opportunities for designers, researchers, tool developers and vendors” — that’s seems a far more accurate description of DVCon than DAC these days.

Particularly again, when you factor into the equation the three DVCons now happening around the world: DVCon Silicon Valley, DVCon Europe and DVCon India.

Having said all of this, do I think DAC should be swapped out and DVCon swapped in instead? Of course, not. But I do think the powers-that-be running DAC might take some time to consider why a conference like DVCon is in ascendancy, and a conference like DAC is not.

Last week I had a chance to chat by phone with Accellera Chair Shishpal Rawat, and when I say chance that’s accurate. Rawat is so busy these days, it’s hard to believe he has time for any extraneous conversations. Not only does he have a full-time job at Intel, he has been chair of Accellera for four years and now is ramping up to take over the reins at CEDA at well.

Among other activities, both Accellera and CEDA sponsor several key conferences in the industry. Accellera is the primary sponsor of the Design and Verification Conference and Exhibition (DVCon). I asked Shishpal about this year’s efforts to take DVCon on the road and how that dovetails with the changes he’s seen at Accellera over his years of leadership.

He said, “Without a doubt, the biggest change is the international outreach that we are now doing in our programs. DVCon will debut in Bangalore this month and will debut in Europe next month on October 14th and 15th in Munich. Expanding the conference this way has required a great deal of work on the part of local dedicated volunteers in both India and Europe, in addition to the efforts of our established corps of hardworking people. We expect a very big group of attendees at both of these shows, which adds to the work load for everyone involved.”

I asked Shishpal how Accellera will know if all of this effort has been worthwhile and if the group should continue to take DVCon on the road.

Shishpal answered easily, “We will ask our member companies. They are the ones most likely to participate in these activities in large numbers. Plus, we’ll poll our EDA suppliers and get their feedback. ‘Has it been useful for their clients? What is the likelihood they will come again?

“Of course,” he added, “the cycle of topics offered at DVCon is an important draw. We also know that most companies cannot afford to send all of their employees to the conference, but perhaps the rest attend in the following years. If that’s the case, it may take more than just this year’s debut to find out if the conference has traction in India and Europe.”

What are some of the topics that are crucial to DVCon, I asked.

Shishpal said, “On the SystemC side, within Europe, Japan and Taiwan, the user group meetings have had good attendance for years. So we know this need will continue to be the core of DVCon.

“Of course, in Europe and India we will add activities around UVM, which is very popular, as well as UPF. So, there will be both SystemC and non-SystemC tracks in the program. This is what we sense the audience wants. From there on, it’s up to the technical committee to create a diverse set of program sessions that reflect evolution in the industry.”

As Accellera Chair, is Shishpal going to India and Europe for the DVCon ‘ribbon cuttings’ this fall?

He said, “Unfortunately, I can’t attend them all. Mentor Graphics’ Dennis Brophy, Vice Chair of Accellera, will represent Accellera in India, and I will be the representative in Europe in October.”

I asked Shishpal how he keeps up with his work and his volunteer activities as well.

He said, “There is a lot of activity going on for me over the course of every year, but Intel is very heavily involved in EDA standards. You will find Intel people have a presence in most of the subgroups of Accellera and Si2, so much so, that between the two organizations most of the standards are covered. And you can understand that from Intel’s point of view, my work with Accellera and CEDA contributes to that involvement.”

At my request, Shishpal clearly delineated between the work of the two organizations, CEDA and Accellera.

Shishpal said, “CEDA is devoted to industry professionals and looks at content and new techniques that will serve the EDA market, mostly within the academic domain. CEDA overlooks the content of DAC, DATE, ASP, and so forth, and works to get the right content for EDA and design development brought out into industry and commercialization.

“Accellera is performing standardization work for EDA tools and technology, standing at the boundary between where one tool finishes and the next operates. We have 13 working groups in Accellera, with Karen Pieper holding chair meetings regularly, so the standards being developed don’t conflict but work together. She is the one who keeps us all in line.

“Our current efforts are aimed at making EDA and IP standards widely available through the GET program that enables electronic download – both within Accellera and through the IEEE. The IEEE typically charges a fee for such downloads. However, some standards initially developed by Accellera have been donated to the IEEE with the intent of standardization and accreditation. We have made a special arrangement with the IEEE Standards Association to make the most popular standards available worldwide for free, whereby Accellera pays the IEEE a flat fee for downloads.”

Shishpal added, “After a standard is donated, the IEEE does a lot of work to get an international seal of approval for it. IEEE standards are worldwide standards, and this process is rigorous and expensive. It includes marshaling participation across many organizations, monitoring formats for the standards, being sure the standards meet certain metrics, and then organizing the vote to finalize acceptance. Once the IEEE standardization process is complete, IEEE hosts the standards on their site for user downloads.”

Changing direction, I asked Shishpal how he would characterize the applicability of Accellera’s efforts to the big bad world of third-party IP vendors.

“All IP developers, whether in-house or third-party vendors, are using established standards of SystemC, SystemVerilog, and so forth, which are the same standards used by component designers. In addition, they are using the IP-XACT standard, and the combination provides a single standard mechanism to guarantee compatibility amongst its users. Given that’s the case, it’s not surprising that companies like ARM, Intel, Texas Instruments, Sonics, Freescale, and NXP are members of Accellera.”

Given Rawat’s enthusiasm, I asked him to identify two or three major milestones he and others would like to be on the road map for the organization going forward.

He said, “We actually articulated those milestones quite clearly at DAC this past June in San Francisco. One is to finalize the verification standard UVM 1.2. We would also like to make that an international standard, via the IEEE, and have it accepted as an IEEE standard. Our working group is moving forward with that aggressively. We would like to get that process initiated by the end of 2014 and concluded by the end of 2015.”

He continued, “The next big thing that we would like to see is building the SystemVerilog AMS standard. Version 2.4 of Verilog AMS was released earlier this year, which was a great deal of hard work, and we would like to see the SystemVerilog version follow shortly.

“This is an important standard as it will address some of the fundamental differences between Verilog and SystemVerilog on how they treat some of the objects in analog design. We will need help from the user community to do that, but we are optimistic they will pitch in and help.

“Under the banner of the Design Technology Council, we successfully brought OpenAccess to life many years ago. We expect that same kind of success getting our SystemVerilog AMS standard into place. We need to look for experts and enthusiastic people willing to contribute time to figure this all out. And of course, it’s always a tussle between job and time allocated for this type of standards work.”

Speaking of the tussle, I asked Shishpal if all companies are as generous with their employees’ time as Intel seems to be when it comes to condoning participation in these types of standards efforts.

He said, “Influential leaders in the big companies understand the importance of this work. We have many Accellera companies who are heavily involved with standards drafting and coding standards such as UVM, UPF, etc.”

Are any companies so counter-intuitive in their thinking as to believe that pursuing standards actually reduces their ability to compete?

Answering philosophically, Shishpal replied: “Standards go through a natural cycle. If someone hasn’t actually tried to use them, they don’t work out. However, good standards are something that people are already using in practice.

“Verilog, for example, was initially a private language owned by Cadence. It went through phases of maturation after being made open, and eventually evolved into an important EDA standard. That is a very typical cycle. Plus, we don’t find people opposed to working on standards, because in truth these things actually improve the financial opportunities for the companies that embrace them.”

“In EDA, in particular,” Shishpal continued, “there is a lot of incentive to use standards. Previously, there were a lot of proprietary standards but over the years that has changed. GDS II became a de-facto standard, for example, and then the Liberty format came from Synopsys and became the de-facto standard.

“At this stage, we don’t see people trying to build their own standards in the workplace in EDA anymore. When you write a tool, there will be many stages in the life of that tool. Yes, there will be internal formats along the way as there is for any development cycle.

“But when you need to introduce that tool into the larger flow, you have to be able to exchange data between the various points in that flow. Standards sit at the boundary – they have to be done well, and they have to be definite. This is the only way to build a flow that will be useful and widely used by the customers.”

Shishpal added, “If you look at the interface between architecture and system-level development, there is a lot of need for innovation and eventually standardization. This is where a lot of work remains to be done. From a user’s point of view, however, even if there are setbacks along the way, standardization will be good for the industry. A great deal of effort is needed in this direction in the near future.”

Also on our phone call, PR Counsel Jill Jacobs added, “Standards always spawn innovation. And now, with IP being widely reused, standards are more important than ever.”

Closing out the conversation, I asked Shishpal how the heck he will be able to have the bandwidth to run both Accellera and CEDA.

He laughed and said, “Fortunately, there are volunteers in both organizations who are willing to help, and not only at the board level. From the working group chairs, to the promotions group chair, and on to the various committees, they are all putting in their time and I am happy to have them. Without their help, nothing would function!”

With the advent of September, the fall conference season begins. Here are some upcoming meetings you may want to attend.

*DesignCon China – September 2-5 – Shenzhen
Last year close to 13,000 attended ICC-China. Expect even more to attend this year.

*Mentor Graphics Forum – September 3 & 5 – Shanghai & Beijing
Keynote will be given by Mentor CEO Dr. Wally Rhines, followed by President of ARM Greater China Allen Wu talking about the next 10 billion chips to be manufactured in China.

*IDF14: Intel Developers Forum – September 9-11 – San Francisco
Intel CEO Brain Krzanich will give opening keynote, followed by lots of talk about the IoT.

*PCB West 2014 – September 9-11 – Santa Clara
The most important conference of the year for board designers.

*Mentor U2U Automotive – September 10 – Dearborn
The debut of a new Mentor User2User event focusing on one of Mentor’s favorite core competencies.

Agnisys exhibited at DVCon several weeks ago in Silicon Valley, but within the time constraints of the show I didn’t have a chance to talk with them. Fortunately, that was remedied at 9 am this morning – 9:30 pm in Noida – during a phone call with company CEO Anupam Bakshi, who was visiting his team in India at the time of our conversation.

Prior to his involvement with Agnisys, Bakshi served at Avid Technology, PictureTel, Blackstone Consulting Group, Cadence, and Gateway Design Automation.

******************

WWJD – Let’s start with the elevator pitch. In 25 words or less, when did the company start and what do you do?

Bakshi – We started 6 or 7 years ago and are Massachusetts-based, although a lot of our development is done in Noida. Our products, called IDesignSpec, focus on the area that the big EDA companies don’t, providing an executable specification tool for chip design.

WWJD – Define an executable specification.

Bakshi – It’s basically a document that describe the functional specs for the hardware.

WWJD – And what does that functional document currently look like?

Bakshi – It looks like a normal Word or OpenOffice doc, plain vanilla without any linkage to reality. Currently, all of the conversion process taking those specs into code happens manually, so what we bring to the table is the automatic conversion of that spec document to code.

WWJD – So how does that work, without revealing your secret sauce.

Bakshi – There is no secret sauce here – it’s patented. We have 3 patents, in fact, so we have revealed all. [Laughing] Basically, what we do is create a tool bar in Word, which allows you to create your spec in a more structured form. Then we can pick up that structured information and convert it into code.

WWJD – Is it like using one of the standard templates provided in Word or LibreOffice, which I actually use?

Bakshi – Yes, but it’s more like a micro-template. You click on the button on the IDesignSpec tool bar, and all those micro templates are dropped into your document. Then you click on other IDesignSpec buttons to do the checking and to generate the code.

WWJD – So basically, your tool bar creates handles or tags within the document the facilitates the conversion to code?

Bakshi – Right. We provide a way of putting a structure into that information, and then we’re picking that up and converting it to XML underneath, and then converting it to an output format.

WWJD – And what format is that?

Bakshi – The format could be anything from design, like RTL synthesizable code, or it could be verification code, UVM models, or it could be software, C code, or other forms of documentation, IP-XACT or SystemRDL.

Or users can create their own output format – customers do that all the time. We provide a TCL interface to Word, which gives you access to your structured data so you can create your own output format.

WWJD – Why haven’t the big design house created a tool like this for themselves? It seems like, for all the money spent in-house trying to optimize their design flows they would throw some resources at automating this part of the process.

Bakshi – It’s important to note here that we’re not converting everything from a functional specification. We do cover sequences and registers, but we’re not covering datapath design, fsm etc. That capability is currently in research and development. Nonetheless, we believe using our tool, you can cut down the time by 30 percent.

WWJD – Time for what?

Bakshi – The time needed to create your IP or your FPGA or your ASIC. The stuff we do, the code we generate, cuts down the time by 30 percent.

Bakshi – They are doing something like this, but why they haven’t come up with the [feature set] we offer – you need to ask them. We are the first do to something like this.

WWJD – What are your specific patents?

Bakshi – They include the fact that you can create these micro-templates, capture the structured data and generate the output. Plus, the fact that our tools back-annotate into the same document, including some error checking – overlapping fields, same name registers, or access-types not compatible, as well as other downstream issues that benefit from error checking up front.

WWJD – Is this stuff really novel? Isn’t it classic stuff from the software world?

Bakshi – Yes, but software checking doesn’t show up until much later in the design flow. Here at the level of the Word doc, you’re creating the spec, and the spec is checking with our checker right there – right there from the Word document itself. Catching errors up front is important, but having a spec’ing tool that checks for errors and creates correct-by-construction code is novel.

Our patent is related to all of this, including the template and back annotation.

WWJD – Okay, circling back to the basic info on the company – how many employees and what’s the exit strategy?

Bakshi – We have 15 employees, and as far as an exit strategy – we’re enjoying what we’re doing. We’re having fun, growing, and seriously want to do more of these specification tools. No one else is looking at these things right now.

WWJD – Who on the design team is using your tools? Who are your target customers?

Bakshi – The architects or high-level designers. We’ve been in the industry for 6 years, so we’ve had a lot of customers from various domains. Our target customers include ASIC, FPGA, IP companies and service providers, and industry verticals including aerospace and defense, medical, film broadcast and image equipment, computer hardware, scientific instruments, and life sciences. Our tools can be useful to anyone who uses design data.

WWJD – I have started a series of blogs called Node2Node that deal with how companies deal with the march down from one technology node to the next. Could I know by looking at the your annotated spec document if there’s a potential mis-match between my design and the process technology I’m targeting for manufacturing?

Bakshi – We’re creating stuff that’s correct-by-construction, so there’s no need for error checking downstream. However, that wouldn’t include checking to see if you’re targeting the wrong technology node. What we generate is correct-by-construction, and if there is any changes required based on the selected process node, the appropriate code will be generated automatically, so no mis-match needs to be flagged.

WWJD – With regards to security, how can I trust that your tool doesn’t include spyware that would allow a competitor to get access to my early architectural specs and beat me to market with the product?

Bakshi – We have military contractors as customers, so you can be assured there is no spyware.

WWJD – With all due respect, here in the age of the NSA, that’s not really a guarantee.

Bakshi – Look, you’re not going to sell to the military establishment if you can’t guarantee that the software doesn’t have any embedded spyware. Those guys go through a rigorous procedure of inspection before they buy off-the-shelf. If we’ve passed their scrutiny, then you should trust us.

WWJD – Do your commercial customers do a similar type of vetting as your military customers?

WWJD – I missed talking with your guys at DVCon. What were you announcing there, and given the nature of your customers, why were you at that particular conference?

Bakshi – We were there to see what others are doing in UVM and SystemC. We were also there to show off the soft launch of our newest tool. It’s called ‘Mystic Tool’ and is going to be like an early warning system for design and verification.

Currently, we’re working on something we plan to launch at DAC, so we were also at DVCon to test the waters and see if the industry liked it, and they did. They gave us some feedback and we’re going to incorporate that into the tool. It helped to have contact at DVCon with people who would be our target customers.

WWJD – What language do your developers use?

Bakshi – We use a collection of languages including Java, JavaScript, XSLT and .NET. Ours is a very novel approach. No one before has ever done what we’ve done to bring tools like this to the designers and developers, so it’s important to make the tools useful for everyone – those who use Word, or Excel, or even batch mode. That’s why we had to use all of these languages for our own development, to make sure it’s easy for people to use.

WWJD – Finally, how is it that you’re based in Massachusetts?

Bakshi – [Laughing] Because that’s where I have lived for 15 or 20 years!

In the spirit of full disclosure, Cadence paid for lunch yesterday for the Press Corps attending CDNLive 2014. We had a scrumptious gourmet meal at Tosca in the lobby of the Hyatt Regency before returning to the Santa Clara Convention Center next door to have an hour-long “one-on-one” with Cadence CEO Lip-Bu Tan. In truth, it was actually an hour-long “twenty-on-one” with CEO Tan, because all of the usual suspects EDA Press Corps was in the room throwing softball lobbing questions at Tan.

Over the course of the hour, we learned that CEO Tan has a host of different investment partners – sorry, didn’t write down the names – involved in his various VC-funded ventures that span everything from GoPro [the trendy wearable camera enterprise out of Half Moon Bay] to a fabless startup that he said can tape-out a design at 16 nanometers for a scant $15 million, rather than the usual $150 million being lamented today in the global press. [In fact, Tan mentioned so many ventures he’s involved with, it begs the question: How does he have time to run Cadence?]

We learned that CEO Tan is very excited about all of the technologies involved in the semiconductor design/supply chain, that he believes it’s a great time to be a player in the industry, and that Cadence is innovating rapidly on multiple fronts simultaneously. And if/whenever Tan senses that they’re slowing down in any particular area, he pushes Cadence Engineering to move forward even faster.

We also learned that Tan thinks there are extraordinary things happening in China, in Japan, in Korea, in India, in Israel – all places where innovation is running rampant. And he knows these things are happening, because he seems to be on a first-name basis with the leadership of every important semiconductor customer in the world. In fact, his narrative implied that Cadence’s product offerings are currently enjoying huge opportunities to have their tires kicked by potential customers specifically because Tan is close friends with high-level folks in those organizations who can, in turn, mandate that their teams buy test out Cadence’s latest and greatest.

By the way, one of the really important things CEO Tan hopes his customers will work on straightaway is battery life for mobile devices. He offered to commiserate with others in the room suffering from the same dilemma he has to endure: His cell phone won’t last more than a day between chargings, so he has to carry three phones to meet all of his communication needs. A lot of folks in the room nodded in agreement. He also said his wearable device/health monitor suffers from battery life shortfalls as well. Fix that, please, he asked of his customers.

Now lest you think it was all work and no play yesterday between 2 pm and 3pm at CDNLive, there were two moments of great hilarity during the hour.

One came when a hapless journalist at the back of the room was called on by the Cadence PR host sitting next to Tan at the front of the room. The poor journalist was reminded by said host that he had a question to ask. Unfortunately, we all knew his question had been planted, because the host said as much when inquiring from her entourage at the back of the room at the top of the hour why said journalist had yet to materialize prior to CEO Tan’s arrival in the room. I don’t think I’ve ever been in a situation where we all knew a question had been planted in a journalist’s brain. But then, there’s a first time for everything.

The other great moment of hilarity yesterday afternoon, I take credit for. Given the endless softball questions being lobbed at the CEO, I thought it was time to make sure I never got invited back [why should Cooley have all the fun]. So I raised my hand, was called on, and asked Tan [courteously] if he was aware of a long-standing criticism of Cadence – that the company’s system-level design tool strategy has for years been way behind offerings from Synopsys and Mentor Graphics.

I noted that Tan’s keynote at DVCon last week and CDNLive yesterday morning both included the same slide bragging on Cadence’s recent purchase of Forte as a critical cornerstone of their system-level strategy. But if that was the case, I asked, how did Tan account for the fact that at least one journalist there in our “twenty-on-one” meeting had written several weeks ago that the Forte sale to Cadence had, in truth, been a “Fire Sale”.

To his credit, Lip-Bu Tan looked me square in the face and answered:

A) The criticism is unwarranted. Cadence has had a long-standing system-level design tool strategy. It is different from offerings of Synopsys and (ahem) the “automobile” strategy of Mentor, but Cadence has been involved in system-level design, most clearly evidenced by their role as an IP provider;

B) Tan has been watching Forte for 11 years and respects their team and technology, but Cadence is not using the Forte acquisition as a launch pad for their system-level strategy (see A);

C) Looking directly at John Cooley – who had waved his arms excitedly in the air moments earlier to claim full credit for being the journalist who’d labeled the Forte event as a “Fire Sale” – Tan said firmly, “The purchase of Forte was not a fire sale.”

Tan then turned back to me and asked if he had answered my question. I may not have liked his answers, but I had to acknowledge he had responded in full.

Following that, Cooley tried to get CEO Tan to diss Synopsys’ Virtuoso initiative, but the CEO firmly refused to go there. He emphasized repeatedly, that he respects and admires “Aart, Chi-Foon, and Wally” and that was the end of that line of questioning. Period.

Finally, the Cadence PR machine closed out the hour by making sure the Press Corps was privy to the human side of CEO Tan. It would appear his wife does not make the tech-product purchasing decisions at home as much as do the two boys. Tan said that his two CMU-educated engineer sons are smart and savvy, and had advised him early on to invest in both Netflix and Tesla. Tan humbly acknowledged that he had, unfortunately, ignored those two pieces of advice and hence had lost out on the opportunity to win big in both movies and EVs.

Nonetheless, given the host of other investments he had mentioned during the hour, nobody in the Press Corps seemed overly concerned that CEO Tan will be running short of cash anytime soon. Nor Cadence for that matter.

**************Epilogue …

The fun of situational irony notwithstanding, we do need to ask ourselves sometimes why it’s so important to foster a cult of personality around CEOs. Particularly in EDA. After all, it’s just code and some algorithms. They’re just selling lines of code and some algorithms. Are they good, is the code fairly bug free, and does it work? Those really should be the only issues on the table.