”Patterned-by-Printing”: Flexible-Printed ZnO Electronics

Flexible electronics are necessary to meet the needs of a diverse array of applications—including health monitoring, electronic displays, and consumer packaging. While not all flexible electronics are printed and, conversely, not all printed electronics are flexible, there is a synergy in the combination of flexible and printed electronics. Unfortunately, the use of printing techniques often results in electronics whose performance cannot meet the requirements of flexible electronics applications. It is widely recognized that improving the performance of printed electronics is necessary for the potential of flexible-printed electronics to be realized. In our lab, we take advantage of the surface-sensitive nature of atomic layer deposition (ALD) to pattern inorganic materials to form high-performance ZnO electronics. “Patterned-by-printing” uses selective area deposition (SAD) as an alternative approach to printed electronics: an inhibiting polymer ink is printed and the active materials are deposited via spatial atomic layer deposition (SALD). Thus, the printable ink requirements are separated from the active materials requirements, while maintaining the advantages of additive device fabrication. Fully functional circuits can be fabricated using only the tools associated with the patterned-by-printing approach—namely a SALD tool, a printer, and a surface-cleaning tool. These patterned-by-printing tools and processes are each fully roll-to-roll compatible. Beyond the potential manufacturing advantages, patterned-by-printing enables freedom in circuit design due to the orthogonal nature of the patterning process. Selective area deposition of ZnO, Al2O3, and AZO is used to fabricate devices with architectures that can be difficult to obtain using subtractive processing methods. The orthogonal nature of patterned-by-printing removes any concerns associated with relative etch rates or solvent compatibility between different material layers. For example, vias between layers of conductor are accomplished by simple changes in the printed inhibitor pattern for the dielectric layer. In addition, the process flow can be easily optimized to control device interfaces and mitigate device defects. By selecting digital printing techniques to pattern the inhibitor, we can rapidly screen variations on a design theme. New device architectures and circuit designs can go from desktop to device testing in a single day. Large changes in architecture or circuit design do not require changes in the fundamental patterned-by-printing process flow. Furthermore, because the materials properties are those obtained from SALD—independent of the printing technique—a change in printing technique does not impact the function or performance of the device. By extension, this decoupling of the print technique from device performance should result in predictable performance as the process is scaled for manufacturing. In this talk, we will review the fundamentals associated with each of the patterned-by-printing processes—including SALD, inhibitor ink formulation, printing techniques, inhibitor removal, and overall substrate compatibility/handling. We will share examples of device architectures and full circuits fabricated using patterned-by-printing that illustrate the benefits of orthogonal patterning. New data highlighting devices on flexible substrates will also be shown, demonstrating our progress in realizing fully printed high-performance flexible electronics.