As I wrote, it is an interesting project. But why mini-USB? People might have invested on USB A-B cables...

Is it supporting USB Audio 2.0 like the XMOS Reference Design?

Thanks again
Roberto

Quote:

Originally Posted by JarekC

Hi,

I designed an additional PCB layout with galvanic isolation (ADUM4160/3160).
The PCB is mounted instead of USB connector.
On the new PCB there is new USB mini connector.
TAS1020B controls the signal PIN of ADUM4160.
ADUM can be powered from 3.3V or from external power supply.

In the standard version there is USB-B socket.
On the main PCB there no place for ADUM, so I add special doughter board.
After the addition this board there is no space for USB-B so I used USB-Mini socket.
I'm waiting for this doughter boards (planned delivery date March 2).

Thanks for the clarification, I stay tuned for the USB 2.0 version, I would like to order one with AES/EBU.

Cheers
Roberto

Quote:

Originally Posted by JarekC

In the standard version there is USB-B socket.
On the main PCB there no place for ADUM, so I add special doughter board.
After the addition this board there is no space for USB-B so I used USB-Mini socket.
I'm waiting for this doughter boards (planned delivery date March 2).

Perhaps you should check this document first before saying such an error:

Quote:

Originally Posted by JarekC

In XMOS I/O pins are reclocked with 400Mhz, this I do not like.

Look at Figure 8 at page 24 (posted below) to see that I/O ports in XMOS processor are driven by external audio master clock (one of two available - depending on incoming sample rate). 400 Mhz is the running frequency for the processor's internal threads. Moreover, I2S signal's retiming should not be done using a multiple of 44.1 or 48 KHz freq.? .. like 22.5792 || 24.576 Mhz OR 45.1584 Mhz || 49.152 Mhz. How above frequencies would fit in 400 Mhz or you think that XMOS has implemented some sort of ASRC at outputs

Perhaps you should check this document first before saying such an error:

Look at Figure 8 at page 24 (posted below) to see that I/O ports in XMOS processor are driven by external audio master clock (one of two available - depending on incoming sample rate). 400 Mhz is the running frequency for the processor's internal threads. Moreover, I2S signal's retiming should not be done using a multiple of 44.1 or 48 KHz freq.? .. like 22.5792 || 24.576 Mhz OR 45.1584 Mhz || 49.152 Mhz. How above frequencies would fit in 400 Mhz or you think that XMOS has implemented some sort of ASRC at outputs

"Yes, any external clock is resampled to 400MHz
If you tie I2S signals BCLK LRCLK and DATA to a low-jitter external
clock on the XMOS device, this will introduce a jitter in the order of
one to two 2.5ns (400MHz) cycles"

Another confirmation of this is that SPDIF out on XMOS reference board is reclocked with MCLK (U1 NS7SZ175 chip)