Fred Gilham <gilham@snapdragon.csl.sri.com> wrote:
+---------------
| There also seem to be some libraries in Scheme for this.
| > The PLT Scheme Simulation Collection provides a discrete-event
| > simulation engine based on a process interaction model. The PLT
| > Scheme Simulation Collection has been prototyped. The PLT Scheme
| > Inferencing Collection provides a rule-based inferencing engine.
+---------------
If Scheme is acceptable, there's also Aubrey Jaffer's SIMSYNCH:
http://swiss.csail.mit.edu/~jaffer/SIMSYNCH
Current Version Released Terms
1b9 2005-06-23 GPL
SIMSYNCH is a simulator for digital electronics at scales from
chip to board.
The design files are comprised of Scheme definitions and
expressions. These design files can be run as a Scheme program
at high speed. The design files can also be translated into
formats suitable for logic compilers (MACHXL and Verilog).
SIMSYNCH simulates blocks of synchronous logic, signals whose
states change simultaneously on a clock signal transition. Each
block also has a reset signal, which forces all signals to the
state specified in the design file. SIMSYNCH can simultaneously
simulate multiple blocks with different clocks and resets. Devices
can contain multiple blocks; Blocks can span multiple devices.
...
-Rob
-----
Rob Warnock <rpw3@rpw3.org>
627 26th Avenue <URL:http://rpw3.org/>
San Mateo, CA 94403 (650)572-2607