Op Amp Stability

Hi All It was mentioned that it might be use full for some people to understand a bit about some stability problems you can get with op-amps. Most of the seasoned engineers on here probably already know this and may like to make corrections to my post. I welcome constructive criticism and will take all on board and make any corrections needed. Hopefully this can turn in to a good resource for new engineers.

To benefit fully from this resource it would be beneficial that you have a basic understanding of how simulators work and also some basic knowledge of op-amp.

Op-amps are the building blocks of many circuits and have been used for many years. Most people don’t have issues with them but when they do it can be frustrating to figure out what’s going on and how to fix it.

I have had people in the past build an op-amp circuit that oscillates when it shouldn’t and they say my circuits not working correctly. I say yes it is, they look dumfounded and I say it is working correctly to the laws of physics. Then I say it might not be working to how you want it to work. That’s a different matter.

So how can these little op-amps cause so much trouble? Well first we have to look at a few of the parameters of the op-amp. I am not going to go through ideal op-amp parameters because we are in the real world and that won’t help us here so some of the issues that may arise.

figure 1​

Ok some simple op-amp shown here has 5 terminals the side terminals are – terminal which is called the inverting input terminal, the + terminal is called the non-inverting terminal, the two power supply connection top and bottom are + and – and the output is the terminal on the pointy end.

Historically the power supply terminals have been actually positive and negative supplies, because most op-amps are designed this way it is always better to use them like this if you can. Single supply operation is possible but has some limitations and several techniques have been developed to improve their operation for use with single supplies.

Main Parameters

Open Loop Gain(Avol) = This is the gain that an unloaded op-amp with no feedback will give you, feedback is when a percentage of the output signal in fed back into the input.

Feedback stabilizes the DC operating point only. Dynamic stability is degraded ! The bandwidth of the opamp unit remains unchanged.

However, the closed-loop bandwidth of the amplifier with feedback is larger than the open-loop bandwidth.
Why do they give us this gain on the data sheet, simple reason is, this is how you get the part, they don’t know what you are going to do with it.

Beta(β) = This is called the feedback fraction and is a ratio of the impedances used in the feedback loop. To keep it simple it is the ratio of the feedback resistors commonly placed around the loop to reduce the gain.
Beta(β) = R2/(R1+R2) see figure 5

Loop gain (Aβ)
This is a special gain and is the most important one which is an indication of the stability of an op-amp. Loop gain in the case of an inverting amplifier is the (-Aol*Beta) and is written as (-Aβ). This is important because if loop gain ever equals +1 with a phase shift of –360 ˚ the circuit could oscillate.

Closed Loop Gain (Acl)

This is Aol /1+(Aβ) and is the classic closed loop gain formula. This is derived from the open loop gain and the feedback fraction. For the case of an inverting amplifier this is Aol/(1-Aβ).

Gain Bandwidth Product(GBW)
This is the highest frequency (bandwidth) of the op-amp where the gain is reduced to 1 (output is the same magnitude as the input) or 0dB also called the unity gain bandwidth.

Noise Gain(NG)
It is the inverse of the feedback factor which defines stability. (Sometimes, this expression is called noise gain) . It is NG= (R1/R2)+1

Signal Gain(SG)
This is the gain formed by the closed loop of the op-amp. For an inverting amplifier it is R1/R2
For a non inverting amplifier it is (R1/R2)+1

So let’s pick an op-amp and do some work on it! The op-amp I am going to use is the LT1001 from linear technology. And I am going to simulate this in LTspice.

LT1001
Avol = 800V/mV which is 800,000 or 118dB
GBW =800KHz
Let’s see if we can simulate this.

figure 2

figure 3​

The convention in this document, unless otherwise noted, is that the solid red line on a plot is the magnitude of the output and the dashed red line is the phase difference between the input and the output -- we shall simply call this phase.

Well that’s not far off! Unity gain (0db on the magnitude line) is at approx. 800KHz and a gain of approx. 118dB. The black dotted lines highlight 0db and approximately 800kHz. The phase at this point (800kHz) is -45˚.

If we look at the magnitude line we see a nice gradual slope down to 0dB. This is the classic single pole response and is the same as a single RC low pass filter."

Single pole response

The reduction in magnitude of the output falls at 20dB per decade, which means for every increase of frequency of 10 times the output has reduced by 20dB. It’s interesting to note that a reduction in frequency of 10 times fc reduces the phase to -5.7˚and an increase takes the phase to -84.3˚.

Fc is called the cut off frequency as is the point where the output has fallen 3dB from the original input signal. The -5.7˚ mentioned above is the point at which it is accepted that attenuation of the input signal starts. The -84.3˚ mentioned above is the accepted stop band which is 10 times the cut off frequency, this adds up to -90 degrees the maximum phase shift a single pole response can give.

Now notice the end of the curve is sloping away steeper. This is a second pole response and this is a reduction in gain of 40dB/decade, what we have to do is keep away from this slope.

But in this case it’s fine as it is below the 0dB line and is stable because there is less than a gain of 1.

If this slope started before the gain reduced to 0dB then we could have problems with stability because of the reduction in phase margin. What can cause this to happen? Well in some cases all it needs it a bit of capacitance on the output, as shown in figure 4. The second cut off frequency which will have a reduction in gain of 40dB/decade is shown above the 0dB line marked by the cross hair on the plot.

figure 4figure 4a​

This is what happens when I add 100nF it creates another pole (with additional -20dB slope) at the open loop transfer function.

But look what is has done to my bandwidth, reduced it to about 45KHz, this is the useable frequency range if we want to stay away from this 40dB/decade slope . This is quite a large capacitance on the output but it just shows what happens.

I need to keep away from this 40dB/decade slope that causes problems. It is worth noting that you might expect to see exactly 180˚ phase shift at the start. Well this is because of the op-amps frequency properties which means you will only get 180˚ if the input to this configuration of circuit was d.c. If I reduced the plot frequency to 10uHz I would be getting close to 180˚ but it will never get there with an a.c signal.

Let’s look at an inverting amplifier with a gain of 10. Now we have closed the loop how do we tell if our system is still stable? We have to compare open loop gain where it meets the Vout/Vin gain line. Now once you have closed the loop measuring the phase on just the output does not tell us anything about phase margin it will only give us an indication of stability if we see any peaking on the plot, to do this properly you have to measure phase margin in the loop.

figure 5figure 6 ​

Or this can be done another way by plotting the loop gain. But you have to work out how to get the feedback factor.

Now you can just calculate it and plot that graph and look at the 0dB point. Or plot aol × 1/11.

Figure 6a

figure 6b
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Another option is to plot aol multiplied by the feedback fraction beta which is R2/(R1+R2). This gives the same phase margin of approx. 85˚so we are still stable.

And we have not lost any bandwidth either. But this was tedious I had to simulate open loop and the closed loop gain . There must be an easier way to do this? Of course there is.

figure 7​

This gives a very similar result of approx. 85˚ phase margin at 0dB. And there is no loss of bandwidth either. Here’s the circuit. Add a plot trace and plot V(fb)/V(-in).

figure 8​

What’s been done here is the loop has been broken and the signal source placed inside the loop. Now it is only the loop delay that is measured and you will notice I had to add gain to the chart in figure 6 because the new method gives a gain of 11.

As far as this amp is concerned it has the same gain as a non-inverting amplifier which is (R1/R2)+1. Let’s see what effect a bit of capacitance has on the phase margin. I’ll add 20nF to the output. The blue trace is the effect of the capacitance on the response.

figure 9​

Wooh look what that has done to the phase margin. Dropped it to 27˚ and reduced our bandwidth to less than 300 KHz.

The capacitance added might be a bit extreme but goes to show what happens when you add capacitance to the output of the op-amp. Well what could cause this effect?

1) Driving long cables
2) Driving Mosfets
3) Buffers used as references with support capacitors.

So what’s happening here? The load capacitance is creating a pole with the output impedance of the op-amp and reduces the loop gain. How can we fix this issue? One approach is to add some series resistance.

This adds a zero on the output and because a zero has a upwards slope of 20dB it cancels out part of the -40dB slope and returns it to -20dB. I didn’t calculate this value I just used 50R as a starting point. To calculate this properly takes some time because if you have phase droop you have to factor this in also.

Option 1

figure 10​

When should we use this approach? When we have light loads and DC gain is not critical.

Second Option

Figure 11

Figure 12​

Single pole response
So what is all this single pole response anyhow? Well let’s have a look at where this all comes from comes from. We will use a simple low pass filter for this discussion.

Figure 13​

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What we know.
1) A single pole response has a falling magnitude of 20dB per decade increase in frequency.
2) The corner frequency or break frequency is defined as 1/2×π×R×C which is when the output voltage has fallen to 0.707 of the input voltage.
3) The phase shift at this point lags by 45˚

How do we derive this?

Well 20log(0.707) = -3.01dB Why 0.707, I know 1/Sqrt(2) is 0.707 but why this value was chosen I don’t really know. I think it was derived from Butterworth’s original calculations and has became an expectable reduction in voltage at a certain frequency. But I suppose if you were happy with any other reduction you would change your corner frequency accordingly.

The phase shift is defined as the inverse sine of 0.707 which is 45˚ or if you knew the time difference between two sine waves then it can be worked out as 360˚×change in time ×frequency.

Figure 14​

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The picture above show how to calculate the reduction in magnitude or slope of the attenuation. wo is corner frequency w is 10 times the corner frequency and TF is the transfer function. Take the -20log of the transfer function and you will have your result. So time TC buy 10 for a decade increase in frequency. If it was just wo/w then this is just -20log of the square root of 2 which is -3dB.

Now let’s have a look at transient response which is how op-amps react to a step input voltage

Figure 15​

I had to use a LT1007 because the LT1001 was actually very good in this situation.

Figure 16​

A reference buffer that is unstable because of 100% feedback and a very large load capacitance which causes increased loop delay and of course causes a reduction in phase margin. This is just simulating turn on of the circuit.

Figure 17​

This is what happens with an amplifier with a gain of 10. Circuit driven with 0.01V 50Hz varying d.c waveform.

Figure 18​

If you want to perform a.c analysis in the above example, using the in loop method is the only way to see what is happening in a circuit that oscillates. Any other method will give us meaningless results because the circuit would need to be stable for the simulator to work correctly.

The Lab Method
How can we do this in the lab without having to break the loop? All we need to do is to measure the overshoot of the circuit, the damped frequency and the time of the decay to 5% of the original step input multiplied by the gain. Let’s use our gain of 10 opamp and I will replace the LT1001 with an LT1366.

Figure 19​

Plot showing overshoot from a 0.1V 1ns rise time step input. So we measure the damped frequency between two point which is 88Khz and convert to radians and then the time it takes for the output to be within 5% of the steady state value. This is 210mV and it happens to be after approx. 50us. Using the formula below

Use the formula below to work out phase margin.

Figure 20​

As we can see it’s about 11.5˚ and our calculated result is not far off.

Figure 21​

The Buffer
The buffer, what could be simpler? Well if not chosen and or configured correctly it could spell disaster for a circuit. What are the issue involved with this simple circuit?

Figure 22​

Op-amps used as buffer can be the most unstable of configurations. Because you have the lowest phase margin due to the 100% feedback. The plot below shows the response of the circuit above to a step input of 6V and duration of 50us with a 10ns rise time. This op-amp (OP-37) is not unity gain stable it requires a minimum gain of 5.

Figure 23​

So the fix for this is to use a feedback resistor R1 and add an input resistance R2 of the same value and then add a RC network across the inverting input and the source. The extra input resistance R2 has the benefit of balancing out any input offset voltage caused by input bias currents that might be an issue with an op-amp designed which just a single resistor in the feedback loop. For some applications i.e. driving A to D convertors, this could produce an undesirable offset voltage on the output.

The RC network reduces the loop gain of the circuit without affecting the closed loop gain. Because stable operation of the OP-37 requires a minimum gain of „5“(classical amplifier operation) the RC network reduces the feedback factor to less than 1/5. The capacitor ensures 100% feedback for DC (unity gain for input offset voltage). This design can now drive 100pF on the output.

Figure 24​

So as you can see this has greatly improved the operation of a non unity gain op-amp being used in a unity gain configuration. For some op-amps all you might need is just the two1K resistors. The fix for this depend greatly on the type of op-amp you are using and may involve a bit of trial and error.

Here is a version supplied by another member of this forum which is LVW, many thanks LVW. He has modified the values of R3 and C2 (previously 200R and 39pF respectively and now the op-amp can drive 1.5nF with only a slight ringing seen on the top left of the pulse. This soon quickly dies out and then the pulse carries on with no distortion.

Here is a version, schematic and plot below, supplied by another member of this forum which is LVW, many thanks LVW. He has modified the values of R3 and C2 (previously 200R and 39pF respectively and now the op-amp can drive 1.5nF with only a slight ringing seen on the top left of the pulse. This soon quickly dies out and then the pulse carries on with no distortion.

Figure 25

Figure 26

But following these steps you should be able to fix most of the issues you come across. It’s worth noting that most op-amps are unity gain stable and have much better input characteristics.

But you still need to be aware that some high speed op-amps need a certain minimum gain to be stable. There is off course a price to pay for all these fixes and that is generally a reduction in the response of the circuit.

I hope you have enjoyed reading this thread as much as I have enjoyed writing it.
I would like to say thanks to Steve and Ian for their continued support.

But most of all a huge thank you to Professor Lutz (LVW) for slapping my wrists on more than one occasion and making sure I used the correct terminology and explanations where needed. I sure have learned a lot from doing this. It's been frustrating and hard work at the same time but ultimately rewarding.