Artisan adds memories; Cadence respins media chip

Artisan Components (Sunnyvale, Calif.) will announce this week that it is tripling its memory-product offerings by adding a High-Density family of memory generators and beefing up offerings in its existing High-Speed and Low-Power memory lines. With 19 memory architectures now available, Artisan claims to offer the industry's "most comprehensive" memory portfolio.

The High-Density family is designed for high-volume, mainstream applications such as desktop computers and consumer electronics. It includes eight generators that produce synchronous and asynchronous single and dual-port SRAMs, synchronous register files, and a ROM generator. Artisan claims this family can yield SRAMs that offer over 130 kbits/mm2 on a 0.25-micron process.

The High-Speed memory family sports new and enhanced architectures that have been tuned to operate at speeds over 850 MHz under typical conditions in a 0.18-micron process. The Low-Power memory family offers some improvements designed to reduce area.

Artisan lowered the starting price for all of its memory generators to $390,000.

Cadence Design Systems Inc. (San Jose, Calif.) will redesign Sharp Corp.'s Data Driven Media Processor (DDMP) into a reusable core that complies with the Virtual Socket Interface Alliance standard as part of a long-term agreement, the two companies announced last week. The project is due to be completed in October, though the two companies will release tentative results in June.

Under the deal, Cadence will provide DDMP consultation to customers along with design consultation, and help to promote the processor to potential customers. Sharp, in turn, hopes to gain licensing and royalty revenues from new customers. Sharp hopes the agreement will spark interest in DDMP, a 3,800-Mops processor that consumes less than 800 milliwatts while in full operation, as a mutltimedia processor for applications such as digital information appliances and cellular phones being developed by other companies.

However, Sharp is now using an older design methodology, and must redesign the processor for each application it is targeting, the companies said.

With hopes of building up allies for the support of its plug-and-play CoreFrame Architecture, core vendor Palmchip Corp. (San Jose) has announced the formation of the CoreFrame DirectConnect Partner Program, a collaboration of third-party hardware and software providers chartered to address the complexities of advanced system-on-chip design.

Jauher Zaidi, Palmchip's president and chief executive officer, said the program enables partner companies to easily port their intellectual property to the company's CoreFrame on-chip interconnect architecture.