Solving of reported problem

Silicon bug workaround CPU_TC.052

The compiler prevents load (ld) and store (st) instructions to be combined.
For example, silicon bug workaround CPU_TC052 prevents that two ld.w instructions are
combined into one ld.dw instruction.

No default section alignment

By default the compiler generates a 4 byte alignment for sections, this is done because the
default initialization code does not know where code ends up and hardware could require a
word aligned read/access to the memory. With the option --no-default-section-alignment,
sections are no longer forced to a 4 byte alignment.

Please note, this means that you will have to use your own initialization code!
Furthermore you will have to remove the copy_unit = 4 part of the copytable declaration
within the LSL file.

New pragma's introduced

Pragma

Description

section_per_data_object

All data objects get their own section, using naming scheme like
"prefix.module_name.<symbol name>"

section_name_with_symbol

All section renaming pragma's will use a renaming scheme like
"prefix.symbol_name.<pragma value>"

Solving of reported problem

Some corrections have been made to the silicon bugs that affect specific derivatives.

The libraries have been updated to prevent new silicon bugs to
trigger. The libraries are rebuild, using the new compiler and assembler.

MMU libraries

Special MMU libraries have been added for derivatives that have a MMU on board.
These libraries can be found in the subdirectory lib/tc1_mmu/ and
lib/tc2_mmu. These MMU libraries contain a natural alignment for data
objects. For example, wordsized data is wordaligned and doublewordsized data is
doubleword aligned.

Please note, protected libraries for derivatives that do have a MMU
(e.g. TC11xx) are also updated with this requirement of the MMU.