Technically Speaking, Inc

Please note: This course is scheduled to run Onsite and Online simultaneously. If there is not adequate enrollment for Onsite, it may run in the Online version only.

Onsite and Online versions of this course have the exact same material and content.

Course Description

As FPGA designs become increasingly more complex, designers continue look to reduce design and debug time. The powerful, yet easy-to-use Vivado® logic analyzer debug solution helps minimize the amount of time required for verification and debug.

This one-day course will not only introduce you to the cores and tools and illustrate how to use the triggers effectively, but also show you effective ways to debug designs—thereby decreasing your overall design development time. This training will provide hands-on labs that demonstrate how the Vivado debug tool can address advanced verification and debugging challenges.

After completing this comprehensive training, you will have the necessary skills to:* This course does not focus on any particular architecture. Check with your local Authorized Training Provider for the specifics of the in-class lab board or other customizations.

Identify each Vivado IDE debug core and explain its purpose

Effectively utilize the Vivado logic analyzer

Implement the Vivado IDE debug cores using both the netlist insertion and HDL instantiation tool flows

Select effective test points in your design

Optimize design and core performance when debug cores are used

Execute various techniques for collecting data including

File storage

Scripting

Building custom triggers

Course Outline

Introduction to Vivado Logic Analyzer

Demo: JTAG-to-AXI Master Debug IP Transactions

Adding the Debug Cores – Netlist Insertion Flow

Lab 1: Inserting a Debug Core Using the Netlist Insertion Flow

Instantiating the Debug Cores – HDL Instantiation Flow

Lab 2: Adding a Debug Core Using the HDL Instantiation Flow

Debug Flow in IP Integrator

Lab 3: Debugging Flow – IPI Block Design

Triggering and Visualizing Data

Demo: Using Dashboards in the Vivado Logic Analyzer

Demo: Trigger on Startup

Tips and Tricks

Lab 4: Tips and Tricks

Scripting

Lab 5: VIO Tcl Scripting

Remote Access

Lab 6: Remote Access (Optional)*

* Check with your Authorized Training Provider to confirm whether this content is included with your specific class.

Lab Descriptions

Labs 1: Inserting a Debug Core Using the Netlist Insertion flow – Insert ILA cores into an existing synthesized netlist and debug a common problem.

Lab 2: Adding a Debug Core Using the HDL Instantiation flow – Build upon a provided design to create and instantiate a VIO core and observe its behavior using the Vivado logic analyzer.