Webinars

In this webinar, Imagination Technologies will share how their selection of standard cell architecture and use of several dynamic power techniques available in Design Compiler and IC Compiler helped them achieve optimal power and area savings for their MIPS family of CPU cores.
Maya Mohan, Hardware Design Engineer, Imagination Technologies and Jeffrey Lee, CAE Manager, Power Compiler, Synopsys
Jul 10, 2014

The demand for pin-limited compression is being driven by tighter form factors, the design of multicore SoCs that require few pins per core for test access, and the adoption of multisite testing as a technique to reduce test application time and cost. In this webinar, we will highlight how Synopsys’ new DFTMAX Ultra is designed from the ground up to achieve high compression using fewer digital scan pins and a minimum of one pair of scan pins. Our guest speaker will then discuss how DFTMAX Ultra is being successfully deployed to lower the cost of testing mixed-signal designs at Dialog Semiconductor.Richard Illman, Technical Staff Member, Dialog Semiconductor; Carl Holzwarth Corporate Applications Engineering Director, Synopsys; Chris Allsup, Marketing Manager, Synopsys Apr 17, 2014

Video and image processing hardware has become pervasive in smartphones, cameras, camcorders, autos, security equipment and a host of other devices. As the algorithms often begin in C and C++, high-level synthesis (HLS) from these languages to high-quality RTL can boost design productivity by 5-10X. Our guest speaker will discuss how Synopsys’ Synphony C Compiler HLS solution is being successfully deployed to meet the challenges of designing imaging processors at STMicroelectronics. Learn how you can use Synphony C Compiler and its C++ image processing library to accelerate the delivery of your high-performance image processing IP in a fraction of the time it takes using traditional methods.Franck Hellard, Principal Engineer, STMicroelectronics; Craig Gleason, CAE Manager, Synopsys; and Chris Allsup, Marketing Manager, Synopsys Apr 10, 2014

Increased design size and complexity can lead to exponential growth in turn-around-time (TAT). This webinar describes the methodology Fujitsu developed using DC Explorer and Design Compiler Graphical to achieve faster design convergence and reduced TAT on large, 40 million+ instance designs. You will hear how DC Explorer speeds up the development of high-quality RTL and constraints and generates an early netlist for guiding and optimizing floorplanning. This early floorplan exploration helps identify layout issues and provides more accurate area estimation up-front in the design flow to help create optimal design partitions, with a better starting point for implementation. Learn how Fujitsu then uses Design Compiler Graphical to achieve higher performance and tighter correlation with place and route for faster design convergence.Koji Inoue, Corporate Application Engineer, SynopsysDec 06, 2012

Hear about the new ECO Verification capabilities in Formality and other key new features, including its low power library checker, ease of use improvements and runtime enhancements.Mark Patton, Product Marketing Director, Synopsys; David Low, Corporate Applications Engineer, Synopsys
Oct 27, 2011

In this webinar you will learn how various ways of describing power intent with IEEE 1801 (UPF) can help you achieve more efficient low power designs. You will also have the opportunity to engage in an interactive Q&A session following the technical presentation.Somil Ingle, Corporate Applications Engineer, Synopsys; Mary Ann White, Product Marketing Director, Synopsys
Oct 12, 2011

Learn how the use of SystemVerilog constructs can result in concise, portable RTL that is easier to maintain and consistent with verification requirements.Liz Chambers, Product Marketing Manager for Design Compiler, Synopsys; James Argraves, Corporate Applications Engineering Manager for HDL Compiler, Synopsys
Apr 27, 2011