In static SER testing - data is written to the memory array under specified Alpha particle exposure, wait for some time (few minutes), then read and verify. This emulates the use case scenario where data written to SRAM is not frequently changing.

In non-static (or dynamic) SER testing - data is written to the memory array under Alpha particle exposed environment but for a very short wait time (varies between few ns to few us), read verify and changed again. This emulates the use case scenario where memory data frequently changes. Since stored data frequently changes in dynamic SER testing, the FIT rate for non-static (dynamic) SER is much lower than the static.

SEL or SEU is a different phenomenon where the SCR type circuit triggers and creates low resistance between VCC and GND under the effect of alpha/neurons. However, the nvSRAM triple well architecture design prevents to occur the SEL type scenario under the specified Alpha/Neuron intensity, therefore it measure 0 FIT/Device (means no evidence of failure found).