The following 2 instructions allow to initialize the bits of port C (BSR)
and are only used after a port configuration in E003H and only
since it is a bit initialization
with D3-D2-D1: Bit number
D0: Set / Reset

0743 LD (HL), 07H PC3 = 1
0745 LD (HL), 05H PC2 = 1
0747 RET

Then to access the bits of the port C it is necessary to use the classic address E002H with half a port in input (read) and
a half output port (write).

Depending on the reading or writing on the 8255, there is no reason to have two different behaviors.

EN:
Do not forget that there is also a 4069 (IC 3C) which inverts the signals that pass in one direction and the other: / READ and / WRITE.
Finally the LS74 (IC 7E) which is a flip / flop with the preset connected to an inverting gate (NAND) to the SENSE signal from where the / SENSE input.

Good point, I was convinced that port $E002 had a different behavior depending on whether you were reading or writing when in fact port $E003 hosts BSR mode. So, `LD A, $02` is like setting PC1 to 1 and PC0, PC2 and PC3 to 0 (I don't like this idea) out of 8255. And `XOR A` is like setting PC0, PC1, PC2, and PC3 to 0 (I still don't like the idea of touching the other three). But maybe I finally figured out why I had an interlock - it's the address I use that's at issue.

I had not noticed the inversions made by the IC 3C! I naively thought that they were diodes to avoid that the current passes in the other direction without taking into account the small circle meaning the inversion. So that can also explain a lot of problems I was having in LEP that left me perplexed!

Ok, I think things will be clearer for this next weekend and I will have to take into account this inversion! say that I probably lost a lot of time because of some kind of electronic details.

Thank you, this discussion has opened my eyes to potential errors in my version.

EN:
I think that it does not matter because PC4, PC5, PC6 and PC7 are in input thus impossible to write, and PC0 and PC1 are not used, remains PC2 which makes it possible to inhibit interruptions clock every 12H starting from starting the machine so very unlikely to have a problem.
Now I am here to touch only the concerned bist: it supposes to save the value in memory, to recover it to use it having modified it. In short, a lot of heavy operations in the machine cycle that slow down the transmission for nothing.

EN:
I just implemented another method and I arrive at a lightning transfer rate: sideroll-F is loaded in less than 2s!
I paufen the assembler and will publish it in the space "sharpeners" very soon, as soon as an exploitable version easily will be finished.

I have an issue with reading PC4: my oscilloscope shows me the signal is not working as a perfect square wave signal but something like that:

PC4.png (26.5 KiB) Viewed 550 times

if the period is small, PC4 has no chance to reach the high level (1), the more I grow period, I'm getting more chance to reach it but it seems to be around 3s for my "UltraFast" mode in MZ-700 to be able to capture all the transmitted bits and to run loaded program (you need to keep the high and low levels stable a consistent time).