Intel, Micron take NAND lead, roll 25-nm chip

LEHI, Utah -- Intel Corp. and Micron Technology Inc. have regained the process technology lead in NAND flash, by rolling out the first in a family of 25-nm devices.

The first 25-nm NAND device is a multi-level-cell (MLC), 8-GB device, which is said to reduce IC count by 50 percent over previous products. With the device, measuring 167-mm2, the Intel-Micron duo will retake the NAND process lead over the SanDisk-Toshiba duo and Samsung Electronics Co. Ltd., which have recently announced 32-nm and 30-nm products, respectively. Another player, Hynix Semiconductor Inc., has a 26-nm device waiting in the wings.

The 25-nm product announcement was supposedly embargoed for Monday (Feb. 1), but one analyst leaked the details on Friday (Jan. 29).

The 25-nm device is made at IM Flash Technologies LLC, a joint NAND fab venture between Intel (Santa Clara) and Micron (Boise, Ida.). Intel and Micron will initially ramp the 25-nm NAND device at IM Flash, followed by production within Micron's fab in Manassas, Va. Still to be seen, however, is when IM Flash will restart its delayed NAND fab in Singapore. Some analysts say that fab will ramp in 2011.

During a fab tour and press event at IM Flash, a 300-mm fab based here, the companies provided some clues to a major question: How did the Intel-Micron duo defy the laws of physics and push the technology down to 25-nm?

IM Flash may also be using a form of phase-shift mask technology. ''With the chip industry staying on Moore's Law and lithography stuck at the 193-nm wavelength, chipmakers are looking to double-patterning to drive linewidth shrinks,'' according to a recent report from Barclays Capital.

''SADP is the technology of choice in NAND, with all players adopting SADP at the 32-nm node. In our view, SADP was really the only choice due to (i) inadequate overlay and line edge roughness capabilities of the then existing litho tools, (ii) the simple nature of NAND 1-D structure, and (iii) availability of excess etch and CVD tool capacity,'' according to the report.

''Looking to the 22-nm node, our checks suggest that SADP is the preferred option for all the major NAND manufacturers as development is already underway and litho tools by themselves alone are not yet ready to satisfy the requirements at 22-nm,'' according to the report.

SADP is a costly but required process. ''With only one critical litho step, the method solves overlay as no alignment adjustment is necessary. Only one critical litho step means that the overlay requirement is not important, and is no longer applicable as a deciding factor. SADP involves the use of two critical etches and the use of CVD to deposit a spacer film and hard-mask,'' it added.

Intel and Micron declined to elaborate on its 25-nm manufacturing recipe, but they hailed the new announcement as a major achievement. The 25-nm device propels ''us in a pretty good lead'' in NAND process technology, said Rod Morgan, IM Flash's co-executive officer, at the event.

IM Flash started production with a 50-nm process in 2006, followed by a 34-nm process in 2008. With today's 25-nm process, the companies are extending their process leadership, added Tom Rampone, vice president and general manager of Intel's NAND Solutions Group.

"This will also help speed the adoption of solid-state drive solutions for computing," he said. Intel is among a plethora of companies selling SSDs, based on NAND.

SSDs are among the applications for NAND flash. The 25-nm NAND device will also reduce the costs for MP3 players, MCPs for cell phones and other products, said Brian Shirley, vice president of Micron's memory group.
It could also enable new and low-cost tablet PCs. Apple Inc.'s new tablet, dubbed the iPad, makes use of NAND.

The introduction of the 25-nm device also comes at the right time, as the NAND market appears to be recovering, he said. Demand is picking up, he added.

There is even talk about shortages in 2010. Gartner Inc. ''maintains that prices are likely to remain stable in the coming months before briefly softening during the second quarter and experiencing substantial
shortages in the second half of the year.''

The worldwide NAND market is expected to hit $18.807 billion in 2010, up from $15.416 billion in 2009, according to IC Insights Inc. The overall IC market is expected to hit $270.7 billion in 2010, up 15 percent over 2009, according to the firm. In 2009, the IC market hit $235.4 billion, down 10 percent.

Meanwhile, for consumer electronics manufacturers, the 25-nm device from the Intel-Micron duo provides the highest-density in a single two-bits-per-cell multi-level cell (MLC) die that will fit an industry-standard, thin small-outline package (TSOP). Multiple 8-GB devices can be stacked in a package to increase storage capacity.

For example, a 256-GB SSD can now be enabled with just 32 of these devices (versus 64 previously), a 32-GB smartphone needs just four, and a 16-GB flash card requires only two. The 25-nm, 8-GB device is sampling now and is expected to enter mass production in the second quarter of 2010.

NAND scaling already has some serious problems... as the NAND cell shrinks, doing 4b and 3b MLC is becoming much more difficult... Notice that IMF is doing just 2b MLC... Without some breakthroughs in error correcting codes for NAND, we are probably very near the end of NAND scaling (i.e. while it might be technically possible to scale NAND, there will be no economic benefit to scaling NAND)

My wild guess: 1) I think IMFT will do a die shrink. 2) That will get them to the 21- or 22-nm node. 3) Then, they will do 16-nm or so.
Another guess: Over time, I see them doing a charge-trap technology. In doing so, they will buy Spansion to gain the IP. This will give them 16-nm, 12-nm, etc.
Long term? I see 3-D, maybe phase-change...