I am an Associate Professor of Electrical and Computer Engineering and
a graduate field member of Computer Science at Cornell University. My
research group is part of the Computer Systems Laboratory, and we
broadly work on energy-efficient parallel computer architecture for
both high-performance and embedded applications. I am also interested
in parallel programming methodologies, hardware specialization,
interconnection networks, VLSI chip-design methodologies, and the
intersection between computer architecture and future emerging
technologies. Building prototype systems is an integral part of my
research, as this is one of the best ways to validate assumptions, gain
intuition about physical design issues, and provide platforms for
future software research.

My research has been recognized with several awards including a Cornell
Engineering Research Excellence Award (2015), an AFOSR Young
Investigator Program award (2015), an Intel Early Career Faculty Honor
Program award (2013), an NSF CAREER award (2012), a DARPA Young Faculty
Award (2012), and an IEEE Micro Top Picks selection (2004). My teaching
has been recognized with the Ruth and Joel Spira Award for Excellence
in Teaching (2016), two Michael Tien '72 Excellence in Teaching Awards
(2013,2017), and a James M. and Marsha D. McCormick Award for
Outstanding Advising of First-Year Engineering Students (2013).

In 2018, I was a Visiting Scholar at the Computer Laboratory at the
University of Cambridge, UK and a Visiting Fellow at Clare Hall also in
Cambridge, UK. Prior to joining Cornell University, I
received my Ph.D. in Electrical Engineering and Computer Science from
the Massachusetts Institute of Technology. From 2007 to 2009, I was a
visiting scholar in the Parallel Computing Laboratory at the University
of California at Berkeley; I received an M.Phil. in Engineering as a
Churchill Scholar at the University of Cambridge in 2000, and received
a B.S. in Electrical Engineering as a Jefferson Scholar at the
University of Virginia in 1999.

Oct 2018: Co-organized a coding sprint with
Princeton University for our DARPA POSH project including
a PyMTL
tutorial and collaborative hacking on our on-chip network
generator

Sep 2018: Paper on PyMTL as an open-source
Python-based hardware generation, simulation, and verification
framework was accepted to
the First
Workshop on Open-Source EDA Technology (WOSET'18) to be held in
conjunction with ICCAD-37

Sep 2018: Paper on a new architectural
framework for accelerating dynamic parallel algorithms on
reconfigurable hardware (in collaboration with Prof. Ed Suh and his
students) was accepted to
the 51st ACM/IEEE Int'l
Symp. on Microarchitecture (MICRO'18)

Jul 2018: Software and hardware
infrastructure originally developed for
CURIE Academy 2014
was adapted by Zhiru Zhang
for CATALYST
Academy 2018 as part of the educational outreach initiatives
funded through various National Science Foundation (NSF) grants

Jul 2018: Defense Advanced Research
Projects Agency (DARPA) proposal to develop HammerBlade, a platform
for continuous synthesis of polymorphic hardware and software (with
our collaborators Prof. Zhiru Zhang and Adrian Sampson at Cornell
University and Prof. Michael Taylor, Luis Ceze, and Mark Oskin at the
University of Washington) is funded as part of the DARPA
Software-Defined Hardware (SDH) program within the
new Electronics
Resurgence Initiative (ERI)

May 2018: Featured on
the Cornell
Research site for NSF Energy-Efficient Computing: from Devices to
Architectures (E2CDA) project

May 2018: Paper on
the Celerity
system-on-chip architecture and design methodology (in
collaboration with our colleagues at the University of Washington, UC
San Diego, University of Michigan, and Cornell) published in
IEEE Micro.
Celerity was one of six systems selected out of HOTCHIPS'17 for
inclusion in this issue, and it was the only academic chip!