ASML outlines a FinFET process two-step

LONDON – Eric Meurice, CEO of lithography equipment supplier ASML Holding NV (Veldhoven, The Netherlands), has explained how he expects logic process nodes to roll out over the next several years.

The IC miniaturization progress will be marked by the need to assimilate FinFETs into the manufacturing process and is set to produce a two-step node at 20-nm, Meurice said.

Meurice made his points in a conference call with financial analysts held to discuss the company's second quarter financial results. ASML as the leading supplier of lithography equipment is in a good position to know the plans of its customers although Meurice spoke generally and in aggregate rather than commenting on any individual company's plans.

His first point was that foundry suppliers would normally have started volume production of the 22-nm/20-nm node in the 2014, two years after the 32-nm/28-nm node, which started this year. The exception to this is Intel which is already claiming to be ramping its 22-nm FinFET process and has said that 25 percent of its shipments would be on the process in the second quarter of 2012.

Competition in the mobile sector is causing the foundries to speed up process introduction, Meurice said. "The reason for the acceleration of the logic business in 2013 is a shortened node transition period between the current 28 nanometer node and future 22 nanometer node which will be about only one year driven by the current race for best integration, best feature set, best power consumption in the mobile arena, where Intel architecture and the ARM architecture will boost play. This transition is also very, very lithography intensive as we expect between 1.7 and two times more immersion systems to be used for wafers in 22 nanometer compared to 28 nanometer."

However, Meurice said that the 22/20-nm process due to come from the foundries in 2013 will initially not have the benefit of FinFET technology, which the foundries are still perfecting.

Intel claims that non-planar FinFETs – or tri-gate transistors as it calls them – provide better on/off current control, reduce leakage and consume less power, than conventional planar transistors.

Meurice said that having introduced a fin-less 22/20-nm process the foundries would have to follow up with a 22/20-nm process node with FinFETs and improved performance shortly after (see UMC licenses IBM technology for 20-nm FinFETs).

Having moved to 22/20-nm with FinFET capability the industry will then shrink the technology to 14-nm or 12-nm for deployment in 2015 using the same FinFET architecture. Meurice did not indicate whether a 1X-nm logic node with FinFETs would require silicon-on-insulator wafers as its starting point. However, Meurice did say: "That node absolutely requires EUV. Without EUV you cannot shrink."

He added that the next few years would be highly beneficial for ASML regardless of the level of success of EUV because it will require a much greater use of lithography on more critical layers in logic IC production.

ASML has good insight since it sells the tools and knows node printing specs.
Good ASML is at least honest in node description: TSMC is calling the 20/22 finfet version "16nm"
I don't see this being interesting: no cost improvement and likly higher cost for 10-20% performance at same power (and that is not chip power just a few digital blocks that speed up...analog, mixed signal, and I/O power is worse). Chip power might at best be half the TSMC number 5-10%.
So TSMC thinks I will do all the work of porting a design to pay higher chip cost for 5-10% chip improvement?

I am told production for this TSMC "finfet 20nm" is 2H2015.
TSMC is very confused to think I would port all my 2013 20nm planar IP to a "finfet 20nm" called "16nm" for higher chip cost for a very small performance incrase at constant power.
Perhaps intel is right, is foundry model broken?

Peter,
Can you look into this. For a given chip in 20nm
True 14nm: porting chip should result in 2x more chips per wafer.
True 1/2 node (14 + 20)/2=17nm should result in 1.5X increase in chips per wafer.
And ideal moores law wafer price should be constant
So what does tsmc 16nm deliever regarding moores law. That will tells us if the node name is fake or real and if it offers any value.
Moores law
(cost) is all I care about. The performance numbers foundry quotes are never true. Foundry does not understand chip design and hence makes many wrong assumptions when benchmarking performance. Just one example being they just quote "median performance" and I need to sell entire distribution.

It's interesting that ASMLs Meurice is quoted as saying you need EUV for 14 nm node. My impression is that Intel has already frozen their 14 nm ground rules and they are not planning to use EUV litho. Maybe the foundries (TSMC, Samsung, Global Foundries, etc.) will need EUV for 14 nm logic? This is possible, but if EUV takes too long to develop I'm betting they will find another way.

TSMC plans to use EUV at 10nm.
But these names now mean nothing.
As I posted above tsmc "16nm" is really "20nm" if node name is suppose to represent transistor density (i.e moores law vs slick marketing)