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Compact 5-V, 10-A Synchronous Buck Regulator Cuts Heat, EMI

The Power by Linear LTC3310S developed by Analog Devices is a synchronous buck dc-dc converter capable of providing up to 10-A output from a 2.25- to 5.5-V input (Fig. 1). Its fixed-frequency peak current-mode architecture is ideal for high step-down ratio applications that demand fast transient response. It comes in a thermally enhanced, 18-lead, 3- × 3- × 0.94-mm LQFN package, and its E- and I- grades are specified from a –40 to 125°C operating junction temperature range.

1. This 1.2-V, 10-A step-down converter employs the LTC3310S.

The “S” in LTC3310S refers to the second generation Silent Switcher technology. This technology enables fast switch­ing edges for high efficiency at high switching frequen­cies, while simultaneously achieving good EMI perfor­mance. Ceramic capacitors on VIN keep all fast ac current loops small, also improving EMI performance. This architecture employs integrated hot loop bypass capacitors to deliver a highly efficient, small footprint solution at frequencies up to 5 MHz with excellent EMI performance.

The IC’s 2.25- to 5.5-V input range supports a wide variety of applications, including most intermediate bus voltages. Integrated low on-resistance MOSFETs deliver continuous load currents as high as 10 A with minimal thermal derating. Output voltages ranging from 0.5 V to VIN are ideal for point-of-load applications such as high-current/low-voltage reference designs. Other key applications include optical networking, telecom/datacom and automotive systems, distributed power architectures, and general medium- to high-power-density systems.

The LTC3310S’s low 35-ns minimum on-time enables a high step-down ratio power supply at high frequency. And its100% duty cycle operation delivers low dropout performance. Total reference voltage accuracy is ±1% over the –40 to 125°C operating junction temperature range.

By applying a square-wave clock signal to the MODE/SYNC pin, an internal oscillator synchronizes an internal PLL circuit to an external frequency. The MODE/SYNC pin either synchronizes the switch­ing frequency to an external clock, a clock output, or sets the PWM mode. The PWM modes of operation are either pulse skip or forced continuous. In pulse-skip mode, switching cycles are skipped at light loads to regulate the output voltage. During forced-continuous mode, the top switch turns on every cycle and light-load regulation is achieved by allowing negative inductor current.

Comparators with voltage hysteresis monitor the FB pin voltage; they pull the PGOOD pin low if the output voltage varies from the nominal set point or if a fault condition is present. A time delay to report PGOOD ignores short-duration output-volt­age transients.

The LTC3310S operates at a high bandwidth for fast transient response capability. Operating at a high loop bandwidth reduces the output capacitance required to meet transient response requirements. Applying a load transient and monitoring the system’s response or using a network analyzer to measure the actual loop response are two ways to verify and optimize the control loop stability. LTpowerCAD is a useful tool to help optimize the compensation components.

When the FB pin volt­age is greater than 110% of nominal during an output overvoltage, the LTC3310S top power switch turns off. If the output remains out of regulation for more than 100 μs, the PGOOD pin will be pulled low.

Frequency Setting

Three methods are used to set the switching fre­quency:

Connect a resistor from the RT pin to ground, which programs the frequency from 500 kHz to 5 MHz.

Synchronize the internal PLL circuit to an external frequency applied to the MODE/SYNC pin.

Use the internal nominal 2-MHz default clock.

Selection of the operating frequency is a tradeoff between efficiency, component size, transient response, and input-voltage range. The advantage of high-frequency operation is that smaller inductor and capacitor values may be used. Higher switching frequencies allow for higher control loop bandwidth and, therefore, faster transient response. The disadvantages of higher switching frequencies are lower efficiency because of increased switching losses, and a smaller input-voltage range due to minimum switch on-time limitations. Figure 3 shows a plot of efficiency and power loss vs. load current.

3. LTC3310S efficiency, and power loss vs. load current at 2 MHz, are illustrated.

The LTC3310S is specifically designed to minimize EMI/EMC emissions and maximize efficiency when switching at high frequencies. For optimal performance, the LTC3310S requires the use of multiple VIN bypass capacitors.

Many designs will benefit from additional 0.22-μF 0402 ceramic capacitors placed between the larger bulk input ceramic capacitors. If the additional 0.22-μF capacitors aren’t added to the layout, then the bulk input ceramic capacitors should be moved as close as to the VIN pin as possible.

Large, switched currents flow in the LTC3310S VIN, SW, and PGND pins, and the input capacitors. The loops formed by the input capacitors should be as small as possible by placing the capacitors adjacent to the VIN and PGND pins. Place the input capacitors, inductor, and output capaci­tors on the same layer of the circuit board. Place a local, unbroken ground plane under the application circuit on the layer closest to the surface layer.

The SW node should be as short as possible. Keep the FB and RT nodes small and away from the noisy SW node.