I am try to compile tlm1/bidir example from uvm-systemc-1.0-beta1 with SystemC 2.3.2
I got error as below and I have no idea what I have done wrong.
~/systemc/include/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_req_rsp_channels/tlm_put_get_imp.h:87:7: error: inherited virtual base class 'sc_core::sc_interface' has private destructor
class tlm_master_imp :
^
I have attached the full compile log
comp.log

Thanks for the help. I did some digging too and I also thought it is becaused by the clock events. So I tried to use the set_timeout on that example which should finished in 100 NS.
When I set the timeout to 30 NS, it killed the simulation at 30 NS as expected. But when I set it to 200 NS, the simulation will not finish. I haven't figure out why.

I can't find any example in the uvm-systemc preview package which DUT has clock and reset signals.
I tried to create clock with sc_clock in sc_main and connected it my dut's clock signal. But it looks the simulation will never finish.
So would someone let me know what's the right way to handle the clock and reset signals?

I am learning the TLM example at_4_phase in the SystemC 2.3.1 package.
But I don't know why there are 16 WRITE commands are generated by the traffic_generator?
From my understanding, the m_transaction_queue is enqueue-ed twice. So I think it should only generate 2 commands then the queue should be empty. Why it generate 16 WRITE and 16 READ commands instread?

Read some examples about TLM and find the calls about "b_transport" with delay. But all of them just ignore it in the implementation.
The sc_time_stamp() from both initiator and target are the same value in the print message. So I am not sure what's the "delay" should be used?
I should wait for "delay" time to start processing request or process the request as soon as possible with my "processing delay" then wait for "delay" time or something else?
Thanks.

I start to learn SystemC and SCV. But I don't have much experience on complex Makefile as the one provided in the install package by SCV.
It is too hard for me to understand who the files are really compiled.
I am not sure if any one can provide simple Makefile template (Only Linux platform is OK).
Thanks.

I try to find a simple template which can compile both the example code and my own (in the future).
The reason why I want one for the example code is I may try to do some modification on the example code to try things, it is too hard for me to tweak the original Makefile in the package.
About the command line, I think that is not a good idea. There's so many flags you have to remember for just compile a single file. I consider Makefile is more productive.

I have a dynamic array in sequence item as below:
rand int array_size;
rand int a [];
constraint c_order {solve array_size before a;};
constraint c_size { a.size() == array_size;};
In some tests, I hope to only create the array according to the randomized value of array_size but not do randomize on the value of it. Is there any way I can do that?

Most time, I expect random value to test DUT. But sometimes I hope to get some simple patterns to test my verification environment, for example I expect the size is random but the value are constant or in/decreasing etc.
If I use foreach, could I turn it off when I expect random value?

I try to define a sc_vector like this in SC_MODULE
sc_vector<sc_signal<sc_uint<C_WIDTH> > > sDin("sDin", C_SIZE);
Then I got this error:
expected identifier before string constant
sc_vector<sc_signal<sc_uint<C_WIDTH> > > sDin("sDin", C_SIZE);
^
I am not sure what is missing from there.

I have a top level module with template like this:
template <int TOP_DEPTH=10>
SC_MODULE(my_top){}
And I have several sub modules like this:
template <int DEPTH=10>
SC_MODULE(sub_module_xxx>
I try to instantiate sub modules with the modified DEPTH from top level:
const int DEPTH_MODULE_A = <math1 on TOP_DEPTH>
const int DEPTH_MODULE_B = <math2 on TOP_DEPTH>
...
sub_module_a<DEPTH_MODULE_A> *pSubModuleA;
sub_module_b<DEPTH_MODULE_B> *pSubModuleB;
...
I got compile error about "invalid use of non-static data member".
I am not sure what's the right way to do it in C++.
(I don't want DEPTH_MODULE_xxx to be static, because my top_module may be used as submodule in other project with different value of TOP_DEPTH. )