Misunderstanding how ground is implemented in circuit simulation is one of the most common misuses of electromagnetic (EM) simulators and their results. This white paper discusses the defi nition of ground in EM simulators and how to correctly choose among various grounding options, a topic of special importance to designers using the results in a circuit simulator. Many modern simulators now support the notion of local grounding, where different ports can use different ground defi nitions. New features in AWR’s AXIEM™ 2009 3D planar EM simulator offer extensive sources/ports and de-embedding options, including internal edge, fi nite difference/gap and extraction ports, and per-port, coupled line and mutual group de-embedding.

Electromagnetic (EM) simulation technology software has come a long way since
it first became popular for microwave and RF circuit design back in the 1980s.
With the sophistication of today’s EM tools, it is sometimes difficult to remember
how limited those early simulators were. The author is old enough to remember
when a challenging problem for a 3D planar simulator consisted of a coupled-line
filter with 1000 unknowns and 3D finite element simulators were stressed
by a simple multi-layer via transition in a package.

Electronic Design Automation (EDA) has been one of the great enabling technologies for modern electronics, including the class of analog circuits classified by their operating frequencies: RF/wireless, microwave, millimeter-wave, etc. Initially distinct and discrete software tools were developed for (logical) circuit simulation and (physical) layout, and these were later augmented by physical verification (DRC & LVS), system simulation, and electromagnetic analysis (EM). Later still, all of these tools came together under unifying environments providing a common database and standardized graphical (schematic) entry.

The benefit to having high-frequency design tools resident on a Vector Network
Analyzer (VNA) does not become obvious until the time comes to compare
simulation to measurements. At this point, the advantage of a more streamlined
work flow -- without the impediment of transferring data to a simulator running
on a separate PC or workstation - becomes clear. To illustrate the benefit of
such a novel, integrated solution (AWR’s Microwave Office software “inside”
the Anritsu VectorStar VNA), this application note follows the design flow for a high-speed serial backplane.

Today’s SoC integrates a collection of peripherals, memory, graphics, networking and I/O components that originate from a multitude of sources. It could comprise designs from within the company, from other companies or from third-party IP vendors. These independently developed components come together to enable a rich feature set for the SoC. However, accompanying this abundance of features is a significant amount of complexity that needs to be correctly and efficiently handled to render the integration successful. One such source of complexity is that components operate at clock frequency ranges that may be very different from those of their counterparts. The existence of these multiple clock domains and the need for them to exchange information creates a hotbed for CDC bugs to thrive. As a result, CDC verification becomes critical to ensure that metastability is not introduced in the design. In this article, we provide several situations with varying set of examples that showcase the challenges in CDC verification.

Next generation high power, high and width electronic devices rely on well-designed RF/microwave components for peak performance. In the specialized world of RF and microwave engineering, the design and development of power amplifi ers (PAs) is a specialty within a specialty that requires many years of focused engineering experience and a suitable collection of test and measurement (T&M) equipment.

Automated synthesis of microwave devices has been gaining in popularity in CAE
applications over the past decade. Antenna Magus now brings this capability to the
fi eld of antenna design. Antenna Magus provides a structured catalog of antennas
(monitor image below) with concise documentation, robust design algorithms, and
export models.

SYMMIC from CapeSym is a template-based thermal simulator that has been
optimized for monolithic microwave integrated circuit (MMIC) design. This
application note demonstrates the integration of Microwave Office and SYMMIC. The integration is script-based and requires minimum manual ntervention as compared to non-integrated thermal solvers. The example used here is an
extension of the MMIC high power amplifier (HPA) example that is part of the
standard Microwave Office set of examples.

Linear and nonlinear device models are the building blocks of most RF and
microwave designs. S-parameters are often used to represent linear devices. As a
“black-box” model, they can easily be obtained using a vector network analyzer and distributed for simulation. S-parameters use superposition to equate the linear relationship between incident and refl ected waves at all of the device’s ports. Nonlinear devices, however, distort waveforms such that their behavior cannot be represented through superposition or S-parameters.

3D electromagnetic (EM) simulators are commonly used to help design board-to-chip transitions. AWR now makes life easier for circuit designers with the introduction of Analyst, a full featured, 3D EM fi nite element method (FEM) simulator. The key advantage of Analyst over other available 3D simulators is its tight integration within the Microwave Offi ce® design environment, AWR’s circuit design and simulation platform. This application note highlights the unique features of Analyst by demonstrating the
optimization of the transition from a board-to- -chip signal path. The example shows how the ability to access Analyst from within in the Microwave Offi ce environment saves designers time and provides ready access to powerful layout and simulation tools that are not available in typical circuit design tools.

Like all RF and microwave components, a distributed filter design will remain only
a simulation exercise if it is not created with its manufacturing process in mind.
That is, the tight dimensional tolerances required to meet a set of performance
goals must be within the capabilities of the filter’s manufacturing process in order
to realize a reliable, repeatable filer

The X-band frequency range has been designated for critical military and
public safety applications such as satellite communications, radar, terrestrial
communications and networking, and space communications. It is important to
ensure that these signals deliver quality, reliable, and secure communications.
This application note describes the design and realization of a complex X-band
transmission analyzer for use in real-time material testing.

Moving to next-generation cellular systems requires new levels of performance
from RF power amplifiers (PAs). While designing PAs has always included the
challenge of maximizing efficiency while delivering high linearity, never have the
tradeoffs been so difficult as they are for 4G/LTE. For instance, the latest
higher-order modulation schemes require exceptional linearity throughout both
transmit and receive signal paths, yet wireless carriers demand the highest
possible efficiency at the system level.

Modern RF/microwave design flows make extensive use of electromagnetic (EM)
analysis in many ways, and its co-existence and concurrency with circuit design and analysis can not be underestimated. Prior to the circuit design and especially in larger designs, EM tools are used to create “library” parts such as inductors, transitions, and antennas. While these parts are fairly self-contained, they must ultimately be integrated into the overall design where at the very least they must be connected to the rest of the circuit or in a more complex case be coupled
to it. During both early and later stages of design, designers will switch from
circuit-based models to EM analysis of critical interconnects to better understand
couplings and achieve greater accuracy. EM analysis is used again before the
design goes to manufacturing, so that the metal in the design can be analyzed
one more time to verify circuit performance alongside design rule check (DRC ), layout versus schematic (LVS), and even design for manufacturability.

Understanding and correctly predicting cellular, radar, or satellite RF link performance
early in the design cycle has become a key element in product success. The
requirements of today’s complex, high performance wireless devices are driving
designers to assess critical measurements—noise fi gure (NF), 1dB gain compression
(P1dB), third order intermodulation distortion versus output power (IM3dBc), and signal-to-noise ratio (SNR)—long before manufacturing begins. Traditional modeling methods such as rules of thumb and spreadsheet calculations (Friis equations) give limited insight on the full performance of an RF link in next-generation wireless products.

The Traditional approach to RF/MW circuit design – which is the present day
foundation for high-frequency wireless design applications – is being pressured
simultaneously by an increase in operating frequencies / bandwidth and a decrease in physical footprint size. The result is that the physical design challenges faced by circuit designers are rapidly increasing, while choices for how these challenges should be best-addressed are not.

RF system-in-package (SiP) and multi-chip-module (MCM) designs present
engineers with the challenge of integrating complementary metal oxide semiconductor (CMOS) integrated circuits (ICs) for digital circuits and gallium
arsenide (GaAs) or silicon germanium (SiGe) devices for RF and microwave circuits with soft-board laminates and low-temperature co-fi red ceramic (LTCC) packages. Software used to design these complex circuits must seamlessly bring together synthesis, simulation, and verifi cation solutions via a single interface in order to ensure optimum component design and placement in each technology. It must also construct schematics and perform physical design entry for any technology in the SiP using uniform commands and menu options.

Harmonic balance (HB) analysis is a method used to calculate the nonlinear,
steady-state frequency response of electrical circuits. It is extremely well-suited
for designs in which transient simulation methods prove acceptable, such as
dispersive transmission lines in which circuit time constants are large compared
to the period of the simulation frequency, as well as for circuits that have a large
number of reactive components. In particular, harmonic balance analysis works
extremely well for microwave circuits that are excited with sinusoidal signals, such
as mixers and power amplifiers.

Near field communication (NFC) is being developed as a form of contactless
communication between wireless devices like smartphones and tablets. This
technology enables users to do things like swipe their devices at the checkout
stand or wave them over another NFC-compatible device to share information
instantly without complicated setups or physical connections.

Achieving the highest possible performance from circuits used in third-and
fourth-generation wireless systems is driving a tighter integration of previously
disparate tools. Certainly, a level of software synergy is essential when
designing circuits for use in today’s wireless systems that employ higher-order
modulation techniques together with advanced technologies, such as Orthogonal
Frequency Division Multiplexing (OFDM), multiple-input multiple-output (MIMO)
and digital predistortion (DPD) circuits, to name a few. As this white paper
illustrates, AWR’s Visual System Simulator (VSS) and National Instruments’
LabVieW graphical programming nvironment are now co-simulating so as to better enable designers to analyze, optimize, and verify complex RF circuits,
subsystems and digital signal processing within a unified framework.

Thermal effects in electronic devices are studied to investigate their influence on reliability and electrical performance. Due to the decreasing size of semiconductor devices operating at unchanged power levels, thermal analyses provide circuit designers with important information about device degradation and electro-thermal coupling. Steady state thermal analyses have been performed for many years in electronics reliability engineering to evaluate device lifetimes. Device channel temperature is the most critical parameter to determine in such a reliability study as it is the primary source for thermal degradation mechanisms. Many techniques exist for modeling and measuring device channel temperatures, however large discrepancies are reported in the literature [1].

High-frequency technology didn’t earn its reputation as black magic for no
reason. Unlike low-frequency circuits, microwave circuits don’t behave in a totally
predictable way, so “tweaking” has been an accepted mainstay of the microwave
design approach/fl ow. Fortunately, high-frequency design tools have dramatically improved so that tweaking of prototype circuits is much less common, and today’s engineer has powerful tools that can make sense of the black magic.

Long Term Evolution (LTE) is rapidly being deployed by major US carriers and will
serve most, if not all, top-tier markets some time during 2012. LTE is often called
a fourth-generation (4G) standard, and provides signifi cantly increased peak data
rates, with the potential for 100 Mbps downstream and 30 Mbps upstream,
reduced latency, scalable bandwidth capacity, and backwards compatibility with
existing Global System for Mobile Communications (GSM) and Universal Mobile Telecommunications System (UMTS) technology.

To fi ne-tune an RF/microwave design to meet new design criteria, engineers turn to
the built-in optimizers within their electronic design automation (EDA) software. A typical optimization case for a microwave filter, for instance, might include goals for in-band insertion loss and return loss, cutoff frequency, and out-of-band rejection. The large number of criteria that the optimization engine then has to take into consideration to create a landscape of “solutions” are more or less random, and, more often than not, quite large.

Many veteran designers no doubt remember how comparatively simple it was
to design base station or mobile phone amplifi ers when the only modulation
technique was analog and amplifi er performance could be verifi ed using
Additive White Gaussian Noise (AWGN). Nowadays, second (and subsequent)
generations of wireless networks usher in digital modulation techniques that
necessitate the need to stimulate amplifi ers and other circuits with waveforms
they actually process in service. It therefore necessitates far tighter integration between the baseband signal processing and high-frequency circuit design tools as well as actual test equipment for both generating these modulated waveforms and evaluating their effects on the performance of the design.

When simulating a complete subsystem such as a wireless communication
device or radar receiver, the quality of measurement data becomes essential
to ensure that the fi nished product meets or exceeds the demands the system
will encounter in service. The measurement data can be used to make changes to the system early in the design process, when those changes can be realized in the least amount of time and at the lowest cost. However, this can be
accomplished only if there is a direct link between the system being simulated
and the measurement equipment itself—that is, when there is “hardware in
the loop.”AWR’s Visual System Simulator™ (VSS) combined with its TestWave™
software provides an end-to-end communications system simulation environment that makes this possible.

One of the most common tasks required of an RF engineer is basic impedance
matching. AWR’s Microwave Office® software has included this ability for a long
time now via a manual ‘step through’ matching process, however, the latest
release of AWR’s Microwave Office now supports the addition of an automated
impedance matching wizard, coined iMatch, that allows the user to quickly
compare different matching topologies and choose the best solution based upon
requirements.

The concept of software defined radio (SDR) has existed for many years.
Consequently, you can find many descriptions of an SDR. A concise definition
of an SDR is a radio in which some or all of the physical layer functions are
software-defined. The physical layer function is the layer within the wireless
protocol in which processing of RF, IF, or baseband signals (including channel
coding) occurs. Many of today’s SDRs have part of the signal processing
implemented in software.

Architectural tools used by designers of RF and microwave communications
systems include budget simulators, spur searching utilities, and frequency
planning tools, all of which are often based on spreadsheets or hard-coded
algorithms with a non-commercial user interface. Having served designers well,
these “home brew” approaches are limited in functionality and/or breadth,
unsupported, and are as varied as the designers who create them. While the
level of effort to create these tools was great and once acceptable (if only because
there was no suitable alternative), few designers today have the time required to
build their own design utilities nor massage existing legacy ones to meet growing requirements of today’s communciation systems. This white paper outlines the benefi ts of using a commercial, specialized software program, such as AWR’s Visual System Simulator™ (VSS) software for end-to-end system design, while also embracing legacy approaches with the incorporation of spreadsheet views.

The system supports easy design in cooperation with test and simulation processes using a signal
analyzer/vector signal generator, as well as effective optimization of RF components and overall system
performance. Using simulation based on actual measurement data reduces the amount of design and prototyping work,
cutting R&D time and costs. Moreover, it can help match performance to requirements, preventing
over-specification waste and cutting product costs.

Emerging systems have three dimensions of complexity when it comes to making them CDC-safe. First, the number of asynchronous clock domains in designs can range from the tens to the hundreds for complex systems with many components. Second, the master clock frequencies vary per component. It is not uncommon for the ratio between the fastest and the slowest clocks to be greater than 10. Third, the clock frequencies themselves can change dynamically during the course of chip operation to save power. As a result, CDC verification becomes critical to ensure that metastability is not introduced in the design.

This article provides several situations with varying set of examples that showcase the challenges in CDC verification.

Verification requirements are growing in all market segments. Ensuring these requirements are met requires design verification that goes beyond traditional design rule checking (DRC), layout vs. schematic (LVS) comparison, and electrical rule checking (ERC). Small and large process nodes alike are affected by these requirements, while both system-on-chip (SoC) and full custom designs also need comprehensive reliability coverage. Learn how Calibre PERC can help you:

Understand the interactions between different power domains

Ensure signals and voltage domains are protected for all operating conditions

By default, a STA tool performs timing calculations based on single clock cycle behavior. There are cases, due to existence of slow logic between flops inside the ASIC/FPGA, where multi clock cycle behavior is required.
The best way to explain multicycle behavior is by comparing it against single clock cycle behavior.

Wave Semi Case Study: With FPGA designs approaching SOC levels of complexity, AXI has become the leading interconnect for IP in large FPGA projects. A significant portion of any AXI design involves software driving the interconnect. This case study covers the basics of AXI and shows how to leverage DPI to verify the same software code in an FPGA as well as in simulation.

Carafe is the second generation IFA software designed to explicitly extract the bridge, break, gate oxide short (GOS), and transistor gate bridge/break faults that may be caused by spot defects using the layout of the circuit and given defect parameters.

SpyGlass Lint and CDC are critical analysis tools for RTL designs that identify chip killer problems and shorten design cycle time. This document highlights the issues that come up when taking a XILINX FPGA-based design through the default SpyGlass flow. With a script-ware based approach, the work required to make the design SpyGlass compatible is significantly reduced. The approach takes care of handling Xilinx library files, design files and design constraints.

Multi-patterning technology was introduced at the 20 nm node to overcome lithographic limitations in current IC manufacturing processes. While processes like double and triple patterning may sometimes seem like magic, successfully implementing multi-patterning compliance in the IC design and verification flow requires a thorough understanding of multi-patterning techniques and their impact on your design. Learn what multi-patterning is, why you need it, and how Calibre® Multi-Patterning software can help you effectively and efficiently incorporate multi-patterning into your leading-edge designs.

This paper presents a complete and practical methodology to comprehensively solve the X problem in RTL design. It begins by reviewing common sources of Xs, and describes how they cause functional bugs as well as unwarranted debug that prolong verification cycles. Solving the X problem helps minimize simulation and synthesis iterations and enables various design analyses (e.g. power analysis), normally performed on netlists, to begin sooner. The pros and cons of various point solutions to this problem are described. The technologies discussed include structural analysis, formal analysis, coding for X-accuracy, and simulation techniques such as random seeding of state initial values. It is essential that a complete solution address both X-optimism and X-pessimism woes as well as be applicable to all sources of Xs, facilitate debug, provide coverage analysis, and enable automation, high performance, and usability. The requirements of a complete and practical solution, based on feedback from users who deal with X issues are provided. The summary of our interaction with users is that the X problem is multi-dimensional and needs a holistic solution that brings to bear the combination of structural analysis, simulation and formal analysis to solve effectively. We describe our user experiences and a case study based on our proposed solution.

Since the adoption of hardware description languages (HDLs) as the methodology of choice for digital design in the early 1990s, an abundance of EDA tools based on the Verilog, VHDL and, later, SystemVerilog languages have been introduced. Providing full support of these languages for simulation and synthesis purposes turned out to be a large differentiator between EDA providers in the early days. But over time, as the industry started to better understand the languages and their implications, the quality of the EDA tools improved to a point where digital design engineers expect full support of the IEEE standards that define these HDLs.

This paper will demonstrate building layered stimulus using OVM
sequences and sequencers. Virtual sequences and virtual sequencers
will be demonstrated by building a small collection of examples that
can be used in layered stimulus verification environments. The main
contribution of this paper is a new layering component that performs
the standard layering task while minimizing user programming
without requiring exotic connectivity, extended components or the
use of the factory.

With the advent of more complex design requirements and greater variability in operating environments, electrical overstress (EOS) is one of the leading causes of IC failures across all semiconductor manufacturers, and is responsible for the vast majority of device failures and product returns. Learn how Calibre PERC can help you:

Power dissipation is a major concern in modern day IC design. For wireless electronic appliances, battery life is one of the major influencers of the purchase decision and can be an effective differentiator. Mobile phones, PDAs, digital cameras and personal MP3 players are increasingly being sold on the long battery lives

Early physical design closure is critical for successful SoC delivery. Routing congestion is one of the key aspects of physical design closure. In this paper we have focused on the logical congestion aspects. We have established the need for a solution geared towards RTL authoring and creation teams. Some products are beginning to emerge in the EDA marketplace to tackle the congestion problem described above. SpyGlassÂ® Physical, a new product in the Atrenta SpyGlass family, is aimed specifically toward RTL designers and offers many capabilities to resolve logical congestion issues up front, during RTL development. The product has very easy to use physical rules with debug capabilities to pin point the root cause, as well as simple reports with the congestion status of RTL blocks.

This White Paper deals with the way SoCs are designed, a process of substantial complexity. This design process is undergoing significant transformation, and those changes are a central part of this piece.

Design patterns have a wide variety of applications in the design, verification and test flows of IC development. From significantly reducing rule deck complexity to simplifying the task of avoiding known yield detractors to enhancing workflows such as design rule waiver recognition, pattern matching has become a useful tool throughout design, verification, and test process. Learn how Calibre® Pattern Matching software can help you implement automated pattern capture and pattern matching in your various IC flows for maximum success at emerging process nodes.

This presentation and talk will present the two major approaches to ESL design entry and what is expected of the designer in each case. A specific coding example will be presented illustrating what is expecting too much of a C to RTL compiler, (and thus gets both the designer and the tool into trouble), plus the coding required to remedy the problem.

This white paper describes a novel approach for memory built-in self test (MBIST) and repair insertion at the register transfer level (RTL). The approach is independent of BIST IP technology and works with any supplier\'s qualified ASIC design kit and BIST libraries. The methodology describes both a bottom up and a top down approach to SoC design and validation - all at the RTL stage. Application of this approach on real industrial designs indicates enhancement of design productivity and shorter cycle time for functional validation.

In this white paper we will discuss various types of exceptions and describe how to avoid pitfalls using a systematic verification approach. Implementation tools such as synthesis and place and route make use of this information to better optimize the implementation and achieve better area, timing, power or routability. While timing exceptions are potent tool in the hands of implementation engineers, any mistake in specifying them can result in a chip failure.”

Multiple, independent clocks have become a fact of life on SoCs and other complex ASICs. In extreme cases, such as in large communications processors, clock domains may number in the thousands. Clock domain crossings pose a growing challenge to chip designers

Assertion Based Verification (ABV) has proven to cut debug time in half and has been promoted as the technology having the most impact on reducing verification time and cost. SystemVerilog with ABV has been viewed as the evolving standard for the most complex chip designs.

In spite of the promise of ABV, wide scale use has not materialized. Assertion Based Verification is a difficult technology to implement and is perceived as marginally cost effective. If it were easy everyone would have jumped on it by now.

Power challenges in today's IC designs create a significant increase in verification complexity. Critical design rule checking of variable spacing rules for densely packed multi-voltage nets is often verified with the traditional use of marker layers, a tedious and error-prone technique. Without an efficient means of verifying variable spacing within nets, designers often play it safe and simply apply maximum spacing throughout specific areas of a design, wasting valuable design area. Learn how to:

Constraints management is a major concern for designers today and increasing design complexity, coupled with mounting time to market pressure, makes faster timing closure and reduced iterations a necessity. Any late stage constraint change brings with it enormous costs, both in terms of time and money, and can lead to a failed design project

When a printed circuit board (PCB) includes a power plane that is near to signal traces or other power planes, there is a significant risk of energy transfer between parts of the system. Not only does this coupling lead to power switching noise being transferred into data signals, it also means that power supply systems may demonstrate additional resonances that are not seen in the individual components. This can affect the power integrity of the PCB and may reduce its speed or reliability. This paper will explore some of the potential power integrity issues that can affect a PCB and explain how simulation can be used to help reduce these effects.

In order to achieve satisfactory verification coverage in an asynchronous design, it is highly desirable to model a synchronizer with all the checks that can help catch the problem. Modeling uncertainty caused by metastable values at the output of the synchronizer is one of them.

This paper details some of the key features and frustrations of using the package construct in
SystemVerilog. The package construct is compared to similar features in other languages such as
the identically named construct in VHDL and namespaces in C++. Valuable lessons learned over
the course of multiple projects in the development of verification environments are described, and
the paper makes recommendations for basic DOs and DONTs for SystemVerilog package use. The
theme of code reusability is always important, and tips on how packages can be used to achieve this
are discussed.

This paper describes a novel method for modeling and verifying cache-coherent protocols using Jasper ActiveModel™ technology. The methodology and benefits of using ActiveModel technology to model and verify the ARM AMBA® AXI Coherency Extensions (ACE™) protocol are outlined. In addition, it describes how an ActiveModel protocol model becomes a valuable piece of system-level verification intellectual property (VIP) used to verify RTL designs. Finally, the collaboration between ARM and Jasper that resulted in the development of the interface-level VIP needed to verify RTL designs supporting the ACE protocol are detailed.

Today's designs contain several hundreds to thousands of registers and memory elements. Starting from documentation to design implementation to verification of each single register, each bit and its property involves a lot of time and complexity.

There is a category of high-end integrated circuits (ICs) – often referred to as "analog-on-top" since the
top level description is a SPICE netlist – that predominantly comprise analog circuitry augmented with
blocks of digital functionality. Until recently, these digital blocks were relatively small, each typically
containing only a few tens, hundreds, or (sometimes) thousands of logic cells. Such blocks were often
handcrafted by the analog designers using traditional custom design capture and layout technologies.

I am struck at how easy it is to get used to “good enough” ways of working. Often we fail to notice new innovations that can make our tasks easier and boost our productivity and reduce risk to success. When asked about connecting to other design team members locally and worldwide, engineers might think of a VPN link to their office computer or the headquarters email server. However, they would be missing the exciting developments of a whole new way of working that brings collaborative resources to bear on the design process, so that design creation, verification and integration is easier and less costly to do.

Platform-based methodology is projected to become the dominant approach for SoC design in the very near future. Automated assembly techniques equally will become the standard approach for building these designs in order to manage complexity, time to market and development cost. Adopting such techniques can have significant impact on each of these factors and carries a significantly lower startup cost than many people assume. More importantly, these techniques are starting to become a competitive advantage, especially in consumer segments. In this White Paper, we have reviewed the key steps needed to implement automated assembly methods. We have reviewed the costs and benefits associated with these tasks and discussed how they are working today for real designs.

Logical Equivalence Checking software like Cadence’s Conformal and Synopsys’ Formality create detailed reports of differences and errors, but it is often difficult to find, view, and fix the logic cones involved with the errors. SynaptiCAD’s Gates-on-the-Fly (GOF) can be used to easily find and view these specific logic cones on a schematic so that you can visualize just the paths you need to see without unnecessary clutter. GOF also simplifies mapping from RTL level constructs to their gate-level equivalents, so that you can pinpoint the locations where changes need to be made. And GOF's ECO mode supports both graphical and script-based editing features for tracking ECO changes. Metal-only ECO operations are also supported with an automatic spare gates flow.

In the silicon debug process, the basic question needs to be answered; do I have a process problem or a design problem?
Unlike conventional ring oscillator based, scribe line based structures, Ridgetop's patented approach provides fabless semiconductor firms with effective tools to help accelerate silicon debug.
Ridgetop's proven die level test structures allow more precise monitoring and troubleshooting for advanced IC design. Self-contained and occupying minimal space, the structures can be used to measure critical mismatch parameters and the extent of NBTI effects (intermittencies).

An overview of the UVM Reference Flow community contribution from Cadence. Presentation reviews what is the UVM Reference Flow contents, discusses roadmap and legal considerations, along with other facts needed for users looking to have a standardized reference for the UVM.

Timing divergence has a critical impact on the economic viability of migrating to sub-65nm process nodes. Clock concurrent optimization (CCOpt) is a revolutionary new approach to timing optimization: it merges physical optimization into clock tree synthesis and simultaneously optimizes clock delay and logic delay using a single unified cost metric. With CCOpt technology, engineers can achieve timing convergence and have a new degree of freedom to design and integrate faster, smaller, lower-power digital chips.

Modern digital designs reach the scale of complete systems and require support of Constrained Random Test and Functional Coverage in verification. Although VHDL does not have built-in, direct support for those methodologies, there are neat solutions that allow their quick implementation in your testbench.

In computer programs, caching is used to store the output from commonly used functions on the
disk so that, when executing a repeated instruction, the results may be obtained more quickly
without having to reprocess the request. This same mechanism can be used to speed up the
display of parameterized cells (PCells) in custom IC design. Some Electronic Design Automation
(EDA) tools cache PCells automatically for performance reasons; some require additional licenses;
and others offer no caching at all. In addition to the performance benefits, PCell caching can be
used to make tool-specific PCells visible in other tools in the design flow.

Integrated Development Environments have been popular in the software world for many years. While the first platforms were dedicated to a single language, modern systems such as Eclipse and Netbeans are structured so that they can be configured for different languages using plugins. This means that the IDE developer can exploit a stable code base and focus on producing a configuration for the language of interest. Since verification testbench writing is essentially a software activity, it was no surprise when IDEs for the popular e language started appearing in 2006. Indeed, there are also IDEs available for the Verilog and VHDL Hardware Description Languages (HDLs) and, more recently, for System Verilog.

This paper, using an example design, demonstrates how to meet challenging performance, latency and bandwidth goals by using the DesignWare® Interconnect Fabric for the ARM® AMBA® 3 AXI™ while minimizing the total area, power consumption and number of top-level wires. The paper also studies the design requirements and examines the optimization features of the DesignWare Interconnect Fabric used to meet the stringent timing requirements. Detailed technical analysis is provided for the selected architecture, pipelining mode, arbitration scheme and the slave visibility feature employed to reach timing closure for the links with demanding performance requirements. Final results are presented based on the hybrid architecture of the DesignWare Interconnect Fabric used to optimize the infrastructure resulting in a reduction in area, power and routing congestion.

This white paper demonstrates a solution for facilitating at-speed test at the register-transfer level. The RTL approach is important, because designers and test engineers usually verify the test coverage only at the gate level during the final ATPG stage. This RTL solution thus saves weeks of effort by fixing potential issues up front.

At a time when building a new global
“sustainable economy” requires
that we fundamentally change
the way we work and live,
High-Tech & Electronics companies
are more than ever hard-pressed
to create the next generation
of innovative and sustainable
smart and green products.

DFM defines the concept of considering the product from the beginning of the design/planning stage to the finished assembly. Considering all of the aspects that go into the development of a prototype before you begin layout will aid you in developing better forecasts for development and production costs as 80% of all product cost is fixed at the time of design.

Transaction-level modeling (TLM) is a methodology for building models at high levels of abstraction, those above RTL. TLM-2.0 is a library that contains classes that implements a methodology for building transaction-level models in systemC and connecting them together.

Low-power designs have become ubiquitous in today’s world. Designers of consumer and mobile products create aggressive low-power designs to compete on extended battery life. Tethered device designers (e.g., servers and routers) want to reduce cost of ownership. Consumers are also more conscious of “green” design in every area of electronics. Today, low-power designs are so popular that nine of ten new designs implement one or more power management techniques. In fact, every consumer device employs low-power techniques such as clock gating, multiple threshold voltages, and power shut down.

Today, systems and semiconductor companies are undergoing a disruptive transformation so profound that even the best-known companies will be impacted. The EDA industry now stands at a crossroads where it also must change in order to continue as a successful, independent business. The disruptive transformation we are speaking of is not about EDA developing new design tools. It is not about new methodologies. It is not about the functional verification crisis, or the move to electronic system level (ESL) design, or any of the issues that have dominated discussions about EDA to date. It is about something much larger. It begins with a shift from design creation to integration in the electronic systems industry, and results in a new focus on profitability. This realization, in turn, opens the way to EDA 360, a new vision for what the EDA industry can become.

In his 2000 book ‘Living on the Fault Line’, high-tech guru Geoffrey Moore (of
‘Crossing the Chasm’ fame) makes an eloquent case for corporations to focus on Core
and outsource Context. In Moore’s view, Core are the activities that directly affects the
competitive advantage of an organization, in other words differentiate it from the
competition. All other activities, and those are often the bulk of an organization, are
Context. The important message, of course, is that one should outsource its Context and
focus its best and brightest on its Core. The good news is that one company’s Context is
another company’s Core. An example is the paper multiplication industry. Having a
photocopy machine at work is handy, but once a manual needs to be reproduced for
customer ship wouldn’t you rather go to Kinko’s. They pick up and deliver your
materials, keep their machines humming 24 hrs a day, and are a lot cheaper than you
burning the midnight oil changing your office copier’s toner. The time saved should be
used on planning your next product.

Trefoil cable formation is used where three phases are carried by three single core power cables rather than a single multicore cable. The advantage of installing three single core cables in such a configuration is that it minimizes the induction of eddy currents, which reduce the effect of localized heating, while maintaining the current carrying capacity of the circuit. Trefoil cleats, are structures used to hold the three single core power cables in a trefoil form, along the length of the laid cables. Manufacturers of trefoil cleats are required to physically test their cleat designs to failure in an applied test, where a section of three single core power cables are held with the cleats and then short circuited. The resulting high dynamic electromagnetic forces being produced from the short circuiting of the three single phase cables, need to be held & maintained by the trefoil cleat. These, physical test can be costly in terms of both cost & time. In order to reduce the cost of trefoil cleat design & development, a time-dependent COMSOL Multiphysics model, including currents, induced electromagnetic forces, material plasticity & contact analysis has been set up to fully describe and simulate the dynamic load conditions on the cable & cleat design. Comparisons to physical tests & calculations using the test standard & empirical data show excellent comparisons. The model developed can now be used to quickly assess trefoil cleat designs without the huge expense & time.

This white paper focuses on how SoC designers and integrators can effectively assess the quality and completeness of soft IP cores. A methodology for accomplishing this goal is presented, and an overview is provided of the Atrenta IP Kit - an application of the SpyGlass® platform that implements a soft IP quality qualification methodology.

Functional verification of today’s large and complex designs is a
major challenge and bottleneck. As a result, various tools,
techniques, and languages have been developed to automate as
much as possible to maximize productivity. For example,
automatic testbench generation of random stimulus offers a
significant aid in finding obscure and hard-to-find bugs.

Static analysis tools provide many types of insight into the design and are being widely used to detect
and prevent various potential problems with designs. Applied during various phases of the design
project, they can detect minor issues to the most serious errors in designs. Tools in this category include
Design Rule Checking (DRC), Clock Domain Analysis, Automatic Formal Verification and Formal
Verification Tools.

This paper describes an approach to using Accellera's UVM, the Universal Verification Methodology, for functional verification by mainstream users. The goal is to identify a minimal set of concepts sufficient for constrained random coverage-driven verification in order to ease the learning experience for engineers coming from a hardware design background who do not have extensive object-oriented programming skills. We describe coding guidelines to address the canonical structure of a UVM component and a UVM transaction, the construction of the UVM component hierarchy, the interface with the design-under-test, the use of UVM sequences, and the use of the factory and configuration mechanisms.

Traditionally, area and timing have been the major issues faced by Integrated Circuit (IC) designers.
Now, power has also emerged as a major concern for three reasons. First, low power is favored by
numerous end‐applications, such as cellular phones, hand‐held gaming devices, and portable media
players. Second, there is an increase in power density due to higher clock speeds and shrinking
process geometries control. Last but not least, most system‐on‐chip (SoC) designs are composed of
different blocks running multiple applications with varying power requirements.

Power format standards, like Common Power Format (CPF) and the Unified Power Format (UPF),
are evolving to establish a power definition that can be used throughout the design, verification,
and implementation stages. While development of a consistent power definition seems promising,
it has direct implications on the complex verification issues that engineers face in debugging
power‐aware designs and the types of solutions needed to address them.

The enhancements to the IEEE SystemVerilog language
in the 2009 standard and in particular to the SystemVerilog
Assertions (SVA) allow us to create much more useful and
versatile checker libraries. They benefit primarily from the
following features: checker encapsulation, let declarations, clock
and disable inference, deferred assertions, elaboration error
tasks, and enhanced property operators. In this paper we first
identify the weaknesses of the current checker libraries by
examining an example from the OVL library. We then provide a
classification of checkers, and show how various forms of effective
checker libraries can be created using the new constructs.

A typical smartphone handset can contain numerous different RF systems, including multi-band cellular antennas, Wi-Fi, Bluetooth, NFC and navigation systems such as GPS and GLONASS. All these systems need to be able to coexist without causing cosite interference. This application note shows how CST STUDIO SUITE® and Delcross EMIT can be used to investigate interference between antennas on a smartphone, and how potential mitigation strategies can be investigated using simulation.

SystemVerilog Test Bench (SVTB) is a set of language extensions to the IEEE 1800 SV LRM used to reduce the amount of time and effort required to write tests which exercise SystemVerilog (SV) RTL code. Design Verification or more correctly defined “Design Exercise” is a methodology in which pre-defined basic boundary conditions of a design must be tested before submitting code to the project‟s official codebase.

Usage of a GALS approach for a SoC implies the creation of several
asynchronous paths. These paths can be critical for the system as
some of them are part of the system bus. They require special
attention during verification.

Real Intent is the leading provider of EDA software to accelerate Early Functional Verification and Advanced Sign-off of digital designs. It provides comprehensive clock-domain crossing verification, advanced RTL analysis and sign-off solutions to eliminate complex failure modes of SoCs. The Meridian and Ascent product families lead the market in performance, capacity, accuracy and completeness.

Floating-point arithmetic becomes a widely used format in digital system design. For example, DSP applications often demand high precision while operating with large dynamic ranges. The IEEE 754™-2008 floating-point arithmetic standard fulfills this criterion but it might be extremely hard to comprehend and use. This document discusses challenges associated with debugging floating-point arithmetic designs and explains how to tackle them using the tools available with your floating-point aware IDE.

Milandr, a 15-year-old product company based in Moscow that builds high-reliability integrated circuit (IC) products for the aerospace, avionics, automotive, and consumer markets, discusses the use of Cadence Virtuoso and ClioSoft SOS to reduce cycle time and improve designer productivity.

Functional verification consumes a significant portion of the time and resources devoted to the typical
design project. As chips continue to grow in size and complexity, designers must increasingly rely on a
dedicated verification team to ensure that systems fully meet their specifications.

Verification engineers have at their disposal a set of dedicated tools and methodologies for verification
automation and quality improvement. In spite of this, functional logic errors remain a significant cause of
project delays and re‐spins. A key reason is that two important aspects of verification environment quality
– the ability to propagate the effect of a bug to an observable point and the ability to observe the faulty
effect and thus detect the bug – cannot be analyzed or measured. Existing methods, such as functional
coverage and code coverage, largely ignore these two aspects, allowing functional errors to escape the
verification process despite excellent coverage scores. Existing tools are simply unable to assess the
overall quality of simulation‐based functional verification environments.

The Certitude Functional Qualification System from SpringSoft incorporates unique technology that
measures and drives improvement of all aspects of functional verification quality for simulation‐based
environments. This paper describes the fundamental aspects of functional verification that remain
invisible to existing verification tools. It then introduces the origins and main concepts of a technology
that allows this gap to be closed: Mutation‐based testing. It describes how SpringSoft uses this technology
to deliver Certitude, the industry’s first functional qualification solution. Finally, it describes how

SWISS is designed for defense to provide necessary interlock signals to the Ship’s weapon control systems for permitting and prohibiting firing of weapons. It ensures safety of ship, onboard men and machine from possible mid air collision of fired ammunition, close to the ship.

Tomorrow's memory standards hold the promise of higher performance. With the uncertain future of which protocols will emerge as industry standards many system architects conservatively choose from current DDR standards - adopting a "wait and see" approach. However, the needs to improve system performance and reduce power consumption are still paramount with next generation products. With memory subsystems representing significant influences on these two areas, designers must find new methods to improve the performance of memory sub-systems.
The Performance-IP method discussed here is implemented using small, distributed, logic elements requires no code changes and does not require the increase of system clock rates.

PCB designers who require state-of-the-art functionality, performance and productivity have always relied
on Cadence® Allegro® PCB Design products. Whether it’s the unique real-time, embedded, shape-based
routing engine that optimizes the router or the constraint-driven, interactive floorplanning methodology for
placing components—the Allegro suite of PCB tools provides you with the most comprehensive and cost-
effective design solution that is available today.
In this webinar, we’ll demonstrate how you can take a project from inception in design capture, the addition
of constraints, through placement and routing, all the way to manufacturing output—without leaving your
design environment. You can achieve all of this by using Cadence Allegro Design Entry CIS and Cadence
Allegro PCB Editor.

A coverage-driven verification plan defines verification goals in
terms of functional coverage points. Each area of functionality
required to be tested is described in terms of values, events and
combinations of these. SystemVerilog provides covergroups as one
way of obtaining coverage statistics to drive the testing activities.

Modern verification environments like those built with the Universal
Verification Methodology (UVM) more closely resemble software
applications than hardware applications. The challenge is that the
teams building and debugging such environments are more often
trained in hardware verification than software verification.

Multiple parallel CPU or DSP cores are becoming commonplace in today's complex System-on-chip projects. They are often the right solution to provide architecture that can meet demanding performance expectations at an optimal process shrink / power consumption / price point.

In a few weeks, the Accellera VIP TSC will release the "1.0" version
of the Universal Verification Methodology (UVM). This was the next step for the committee after it had released the UVM EA release early last year This has been quite significant because, the three
major verification vendors have aligned on a single SystemVerilog Base-Class Library and Methodology for the first time.

Power consumption is a key differentiator for semiconductor
products targeting the embedded market. The combination of system-level requirements and device-level characteristics presents a particular challenge for verifying the implementation of low power design features.

Circuit designs continue to get larger and more complicated. Custom layout, like most steps in the
IC design flow, has become more tedious and time consuming. Designers are always looking for
better tools to automate the process and help them become more productive. Schematic‐driven
layout (SDL) is a design methodology that assists designers with the physical implementation of
circuits, by providing automation and continuity between logic and layout. SDL relies on device
generation technology for automation of the creation of physical layout from schematic elements.

Sun designers and architects now view formal as a tool to understand and expose specification holes and errors. Exploring corner case scenarios early leads to cleaner, more robust implementations. And formal verification can help promote design leverage and reuse.

Ensuring the hardware testing results match RTL simulation results is the key to the strict verification guidelines of DO-254. This paper describes how to replay RTL simulation environment in the real hardware with the same flexibility, traceability and coverage ideal for DO-254 certification.

SystemC is a versatile C++ based design and verification language, offering various mechanisms and constructs required for embedded systems modeling. Using the add-on SystemC Verification Library (SCV) elemental constrained-random stimuli techniques may be used for verification.

Direct Memory Access (DMA) is one of several methods for coordinating the timing of data transfers between an input/output (I/O) device and the core processing unit or memory in a computer. DMA is one of the faster types of synchronization mechanisms, generally providing significant improvement over interrupts, in terms of both latency and throughput.
An I/O device often operates at a much slower speed than the core. DMA allows the I/O device to access the memory directly, without using the core. DMA can lead to a signifi-cant improvement in performance because data movement is one of the most common operations performed in processing applications. There are several advantages of using DMA, rather than the one in which core does a memory to transfer operation and vice versa and this paper discuss all these advantages with various applications of DMA Controller.
DMA is used in almost every complex system or subsystems , but its observed that teams either build the DMA controller from scratch for each project for specific application or take the existing DMAC available from elsewhere.
Here in this article I have tried to discuss the architecture of DMAC that can be used with any kind of Bus, configuration (parallel, serial transfers), can be connected to any kind of ports, most importantly any kind of software assumptions can be implemented in the DMAC very easily. I call it Universal DMA Controller.

The Open Verification Methodology (OVM) and the new Universal Verification methodology (UVM) have a number of methods for
terminating the run() phase at the completion of a test, usually via a combination of sequence completion, calls to the global stop_request mechanism and/or the recently-added objection mechanism. Many users also use built-in event and barrier constructs on a more
application-specific basis to achieve their goals. This plethora of choices has led to some confusion among the user community about how best to manage this important aspect of the testbench.

Precise verification coverage measurement remains a significant IC development requirement. By combining the exhaustive nature of formal technologies with accurate Observation Coverage techniques, OneSpin has moved the state-of-the-art forward in this critical area. Download this whitepaper to learn more about the Observation Coverage approach and how this has been leveraged in OneSpin's new Quantify coverage technology for precise, rapid formal and simulation coverage assessment.

Six years ago, when OASIS was introduced, we published an article highlighting why it was a positive replacement for GDSII [1]. Since then, users have started adopting OASIS in their flows, with benefits and disadvantages. One of OASIS strengths is its flexibility (unlimited coordinate precision, unlimited number of layers, etc...). But this flexibility has a price in terms of memory consumption and computing time.
A new standard, OASIS.MASK, is being introduced to address the requirements specific to photomask layout repre- sentation. This subset of OASIS (and as such fully OASIS compliant)introduces constraints that reflect the real-world limitations of mask manufacturing. As a result, OASIS.MASK interpretation and exploitation is more efficient and reliable.
[1]P. Morey. Going from gdsii to oasis. EEtimes, December 2008.

Moore’s law continues to drive both chip complexity and performance to new highs every year, and
continues to stress and periodically “break” existing design flows. Fortunately for EDA users, the same
shrinking geometries that make their design problems tougher are also helping to improve the
performance for their EDA tools.

But when it comes to functional verification, traditionally the largest bottleneck in the design process,
software-based approaches like simulation continue to lose ground. Why isn’t simulation speed keeping
pace with device complexity? Because many new devices like 3G cell phones, internet routers, image
processors, etc. require massive verification sequences that would take many CPU-years to simulate on
even the fastest PC. These sequences are often a result of the need to run long, contiguous, serial protocol
streams or complex embedded software in order to fully verify a new SoC or system design.

Increasingly, embedded software is overtaking the hardware content of SoC devices. The net result is a
kind of chicken-egg problem: which comes first - the “final” hardware or the “final” software?
Embedded software developers need an accurate model of the hardware in order to validate their code,
while the hardware designers need fairly complete software to fully validate their ASIC or SoC. Software
developers can sometimes get started using a bare-bones, non-cycle accurate high-level C model of the
processor or an instruction set simulator (ISS). Similarly, chip designers can simulate their design along
with small code snippets or diagnostics to verify basic functionality. But eventually both these groups
need to come together on a common model to verify the complete hardware and the embedded software
together. Unfortunately, for most teams that first complete model is the actual silicon.

The multi-GHz line rates enabled by SERDES introduce new design challenges in FPGAs, notably signal integrity issues which
have given rise to a number of design tools and methodologies. But equally as demanding, if not more so, are the functional
verification challenges associated with this complex technology.

With the widespread adoption of advanced low power design and
implementation techniques in SoC designs, the role of low power
verification has been more critical than ever. Advanced low power
design techniques, such as power gating, state retention, multi-VDD
etc, require significant revisions of the verification methodologies,
library infrastructure, advanced CAD tool support and serious
engineering efforts to tackle the huge complexity in both
implementation and verification.

The high-definition video trend continues to drive new consumer products. These products are now moving to higher resolution, more sophisticated video compression, such as H.264, and improved image and scaling algorithms up to 120 Hz. This trend is affecting digital TVs, set-top-boxes, game consoles, and even mobile devices. There is clearly a new high quality, high definition (HQHD) segment forming which requires an exponential increase in SoC processing capability to support the more complex algorithms associated with HQHD.

Even a single sided a board can be viewed from above or below. Clearly marking all layers with right reading text will enable the board manufacturer to verify the proper orientation for your board. The more layers that are employed to make a board, the more important this becomes.

Minimizing power consumption has become a critical requirement in
today’s designs. Active power management required to minimize
power consumption creates additional challenges for functional verification. IEEE Std 1801™-2009 [1] defines the Unified Power Format (UPF), which enables visualization and early verification of
the behavior of a design under active power management during RTL simulation.

UPF2.0 [1], with its ability to define power states and corruption semantics on them, has made low power verification flows powerful. This powerful flow provides more flexibility to a verification engineer to define sophisticated assertions, enabling them to isolate more low power issues in the design.

Using external VIP (Verification IP) brings several advantages including availability, independence in both checkers and coverage, robustness from use in several environments. However, the VIP must be developed so that it is easy for the user to incorporate the VIP into their environment. In this paper we look at practical lessons learned in both the development and deployment of VIP for use in complex OVM (Open Verification Methodology) SoC (System-on-Chip) verification environments.

Since the existence of integrated circuitries, there has been the necessity to check their
functions. In the case of digital circuitries, a test is quite simple: all possible test vectors are applied in succession, and then the circuitries’ reactions at the outputs (actual value) are compared to the expected patterns (nominal value). If there are no differences the circuitry
is correct.

During this presentation, some of our comments may contain projections or other forward-looking statements regarding future events or the future financial performance of the Company and/or the industry. We wish to caution you that such statements are predictions and contain risks and uncertainties and actual events or results may differ materially.

Scoreboarding is a critical function required of a verification environment. While much progress has been made in standardizing verification environments with the release of Accellera’s Universal Verification Methodology(UVM)[1], no standardized scoreboarding implementation is currently available.

A methodology is presented for writing modern SystemVerilog testbenches that can be used not only for software simulation, but especially for hardware-assisted acceleration. The methodology is
founded on a transaction-based co-emulation approach and enables
truly single source, fully IEEE 1800 SystemVerilog compliant,
transaction-level testbenches that work for both simulation and acceleration.

Software teams have long realized the return on investment (ROI) of software configuration management (SCM) systems, which have been used by software teams for decades to manage development, improve collaboration, and coordinate releases. In fact, SCM systems have become such an integral part of a software development environment that practically no significant software project is even started without a SCM methodology in place. Over the last decade, hardware design teams have encountered the same market forces as software designers: increased competition due to globalization, mandating the use of the best available engineers irrespective of location; an exponential increase in design complexity; and shrinking market windows. The result has been larger teams of engineers spread across multiple sites, managing complex flows, and sharing a large volume of constantly changing data. They need hardware configuration management (HCM) systems.

The Open Verification Methodology (OVM) and Verification Methodology Manual (VMM) libraries used to augment the capabilities of the SystemVerilog language introduce advanced stimulus generation capabilities suitable for designing large testbenches and verification IP in the form of sequences and scenarios. However, many verification teams struggle to fully utilize these techniques, and end up with testbenches that either only support directed tests, or support randomization while being difficult to maintain and enhance. In this paper, advanced stimulus generation concepts, architecture, and motivation will be described. Tips for a successful stimulus generation implementation will be provided, and solutions from the VMM and OVM libraries will be compared and contrasted.

A multi-layer protocol is a lower-layer protocol wrapped in a higherlayer
protocol, for example IP over Ethernet. Multi-layer protocols
are challenging because of the linkage between the layers required
for stimulus generation for a design under test (DUT) that is aware of
and processes both layers simultaneously. This paper will discuss the
challenges of verifying a design that supports multi-layer protocols
and the use of Open Verification Methodology (OVM) transaction
objects to overcome them, particularly in the creation of stimuli.

Triad Semiconductor (TRIAD) delivers mixed signal IC solutions using a radically different approach that allows you to integrate analog and digital circuitry into an application specific integrated circuit (ASIC) at a fraction of the cost and time normally required.

One of the big advantages of COMSOL Multiphysics is the possibility to implement user-defined partial differential equations (PDE) which can be coupled to COMSOL's predefined physics interfaces. However, using the tool’s standard user interface requires manual implementation of the PDEs and a multitude of problem-specific parameters. This process is not just error-prone but also very time consuming. As an alternative to this manual implementation one can use COMSOL’s Java Application Programming Interface (API) which provides an easy and efficient way to create a user-defined simulation package. Here, we demonstrate the usage of COMSOL's Java API by our implementation of a micromagnetic modeling and simulation package.

Functional verification has long been a major concern in digital design. Over the years, the huge investment in verification spurred the development of tools and methodologies for systematic and costeffective functional verification.

SystemVerilog provides a compelling advantage in addressing the verification complexity challenge ─ not simply as a new language for describing complex structures, but as a platform for driving a more efficient, realistic test of the design. It is no surprise then that the adoption of the language for verification purposes has been rapid.

Building robust, reusable testbenches means the testbench
elements must be configurable. At its essence, configuring a testbench is a matter of populating a database with name/value
pairs and providing a means for testbench objects to access that database.

There is an ever-increasing demand for higher performance microprocessors within a given power budget. Such a demand forces design choices – that were once seen only in high-speed custom blocks – to spread throughout the microprocessor core.

Cadence® OrCAD® Capture offers a comprehensive solution for entering, modifying, and verifying complex system designs quickly and cost-effectively. Whether used to design a new analog circuit, revise a schematic diagram for an existing PCB, or design a digital block diagram with an HDL module, OrCAD Capture allows designers to enter, modify, and verify the PCB design.

Designing a printed circuit board (PCB) can be quite a challenge when you don’t understand the
capabilities of your design tools. Creating designs with critical requirements and narrow deadlines requires
engineers to have comprehensive knowledge of the CAD tool you use daily. Even understanding some of
the fundamental operations like importing / exporting mechanical CAD data, creating a PCB library of
footprints, physical constraints management etc., can save time and make your job easier and more
productive.

In the functional verification of complex chips, there are several
phases where the requirements for the memory and runtime are far beyond the simple, single compute-server capabilities. With multi-core processors being ubiquitous nowadays, EDA tools have emerged over the last several years to provide solutions leveraging these multiple
cores through parallel computing to push the limits of memory and runtime limitations of erstwhile simple computer infrastructure.

We present GOLDMINE, a methodology for generating assertions automatically. Our method involves a combination of data mining and static analysis of the Register Transfer Level
(RTL) design. The RTL design is first simulated to generate data about the design’s dynamic behavior.

The OVM and VMM methodologies each provide powerful, flexible and intuitive frameworks for the construction of SystemVerilog verification environments. However, many SystemVerilog users also have models written in C, C++, or sometimes SystemC. Furthermore, the emergence of the SystemC TLM-1 and TLM-2.0 transaction-level modeling standards is having an impact on communication styles within SystemVerlog verification environments. This paper offers practical guidance on using the SystemVerilog Direct Programming Interface (DPI) to integrate existing C, C++ and SystemC code into an OVM- or VMM-based SystemVerilog testbench without jeopardizing portability from one simulator to another. This is achieved by presenting a set of simple, robust guidelines for creating portable DPI code.

Over the past decade, Phase-Locked Loops (PLLs) have become an integral part of the modern ASIC design. PLLs provide the clocks that sequence the operation of the various blocks on an ASIC chip as well as synthesize their communications. There are various types of PLLs targeting specific applications. Clock generator PLLs are capable of large frequency multiplication.

The verification of today’s bleeding-edge chips requires the best methodology and tools, including the application of high-capacity formal verification technologies throughout the design flow, from architectural exploration to post-silicon debug. We see this last area, post-silicon debug, as an important value delivered by formal technology for design and verification teams who have not employed formal analysis earlier in the process to get the design right the first time. As case studies demonstrate, using formal analysis to find bugs, fix them, and verify the fixes adds tremendous value in the post-silicon lab.

Verifying the current generation of complex SoCs requires the best methodology and tools, including the application of high-capacity formal verification technologies throughout the design flow, from architectural exploration to post-silicon debug. We see this last area, post-silicon debug, as an important value delivered by formal technology for design and verification teams who have not employed formal earlier in the process to get the design right the first time. As the case studies presented in this white paper demonstrate, the use of formal to find, fix, and verify the fix adds tremendous value in the post-silicon lab.

The mainstream use case for the UVM is to create a verification
environment that supports the running of multiple test cases which
run sequence based stimulus and use automatic checking and
coverage mechanisms to achieve closure on a verification plan.
However, there is another important use case which is not so well
addressed and that is the interactive debug of hardware and test
bench bugs.

The increase in mixed-signal content - both in size and complexity
– of an SoC demands a change in the existing mixed-signal verification techniques. Although some ad-hoc practices exist today for analog or mixed-signal verification, none of these
methods scale to the complex circuit conditions that analog and mixed-signal verification tasks encounter.

More features and more bandwidth capability enabled in our new generation switch chips create a daunting task for functional verification. Our verification methodology includes a top level test environment and many block level tests for key blocks. Both rely on random stimulus to achieve significant coverage.

This paper explains multi-level transaction level monitoring, scoreboarding and coverage collection for existing RTL designs. By applying the ideas in this paper, the reader will understand how to achieve higher level verification on reused or lower level design components.

There are several challenges in verifying a complex SoC (System on Chip) on time, like frequent specification changes, which include architectural and protocol changes that impact both verification effort and the delivery schedules. As an example, a SoC of ~140 M gates currently we are working on consists of large sub-chip components having hierarchical interconnects, needs to be comprehensively verified.

Functional verification requires, among other things,
dedicated programming constructs and mechanisms. Such are
accessible to a wide community of verification engineers
today more than in the past thanks to the SystemVerilog
language. Along with many verification specific constructs it
features object-oriented programming (OOP) framework.
OOP has been extremely successful in facilitating reuse in
many software application domains.

The NMI recently organised a one day conference taking a software perspective on low power hardware design verification. While hardware designers are becoming increasingly adept at adding clever power saving features into their designs, it is not always clear how software engineers use them. This day was targeted at trying to bridge that gap between hardware and software engineers.

In this case study, a team with little experience in formal verification describe how they used formal techniques to find real bugs, including some that probably would not have been found with simulation.

Over 50 engineers and engineering managers were surveyed at DAC 2009 by Jasper Design Automation as part of a market research and analysis program examining how designers use formal verification across the design cycle. Within eight application areas, respondents indicated which formal technology applications are most interesting and valuable, all the way down to each detailed engineering task within the application areas, and their hierarchy of value. The set of applications used in the survey are current uses of JasperGold and ActiveDesign, as developed by Jasper Design Automation and its customers.

This paper describes the theoretical background, current status and future challenges facing interoperable cryptosystem for safe delivery of Intellectual Property (IP) to be used in VHDL and SystemVerilog design and verification. The system must be reliable, and interoperable, i.e. enable safe use of IP source in a variety of tools. IEEE P1735 Working Group currently develops proposed standard describing such a cryptosystem.

Technology advances allows for the creation of larger and more designs. This poses new challenges, including efforts to
balance verification completeness with minimization of overall verification effort and cycle time.

Register transfer level (RTL) simulation run times are severely impacted by the verification requirements of today’s complex IC designs. Due to fierce market demands of increased functionality, the need to serve multiple applications with the same core design,
and shrinking time-to-market windows, it has become increasingly challenging to complete the verification plan on time.

The checker construct is a new feature defined in IEEE 1800-2009; it is intended to facilitate the definition and usage of libraries of assertions and to delineate verification code from RTL. In this paper, we describe our experience in using checkers for the evaluation of a cache controller design. The goal was to evaluate how easy it is to define and then utilize the checkers in a variety of configurations. Checkers were defined to include static concurrent assertions, procedural concurrent assertions, immediate and deferred immediate assertions. The checkers were then instantiated statically and procedurally in the design module. We also experimented with where the checkers are defined and how formal arguments were used. Simulation was used to confirm our results, with both pass and fail assertion results expected.

Release management is critical to the success of every hardware
development environment. However, it is typically the most
overlooked and underestimated task in most development teams. In
this ever increasing complex world of ASIC and FPGA designs, the
ability to manage the changes made by both design and verification
members in a sufficient way is needed where one can quickly
determine faulty RTL, synthesis, schematic, and layout updates. This
paper will address the drawbacks of a typical release flow, and will
put forth a proven 5 step process a design team can implement which
can be then be automated. . It also presents a case study, where a free
open source software tool ReleaseWorks® [3] was successfully used
to automate this 5 step process.

The term asynchronous reset is a term used with digital design, but, it is often misunderstood. The type of reset is used in the specification of fields or slave interfaces in CSRSpec and the specification of signals in SystemRDL. There are two types of reset: synchronous and asynchronous. Even though the names may imply otherwise, both types have timing constraints with respect to a clock.

Standard reference sources (Motorola's MECL System Design Handbook, for example1.7.1) give several formulas that relate to the propagation delay of a signal along a trace on a circuit board. These formulas have been combined and summarized in Figure 1.7a. The first part of the formula provides the basic propagation time under unloaded conditions. In that formula, a = 1 and b = 0 for Stripline configurations and a = .475 and b = .67 for Microstrip.

Despite many efforts to automate analog design and layout, these tasks remain primarily a full custom process, ; with the result that analog is occupying a larger and larger portion of the total design cycle time. Efforts to automate analog design have not been successful in the marketplace because the tools have not been able to equal the quality levels of full custom design, are complex to set up and use, and are expensive.
Tanner EDA’s new tool forgoes full automation in favor of accelerating the layout process by generating key analog design primitives, such as current mirrors and differential pairs. These primitives are often the most time-consuming aspect of layout and indeed the parts that are critical to the functionality of the silicon. The new tool applies matching techniques to address common processing artifacts, produces the optimal solution for parasitics and silicon area, and creates devices optimized for high yield.

Smaller devices with more memory and features, environmental constraints, global sourcing, increased speed and decreased cost—these demands pose significant challenges for the electronics manufacturers who, arguably, have the shortest product lifecycle of any industry. Delivering the latest, greatest, smallest
and next "must have" tech toy requires design and engineering solutions that will help the industry evaluate and improve product performance on the fly.

In this paper we propose a methodology to simplify the verification process by creating a library of small, generic Verilog-A (VA) based assertion modules that can be connected together to form more complex checkers for any circuit. This serves as a good infrastructure for designers to easily build their own checkers. A Cadence infrastructure with schematic elements like symbols and
forms are built to make the use of the library of assertions for a module level verification more intuitive and user friendly.

In order to successfully verify a design, the scope and details of the verification problem must be quantified and measured. These are written during verification planning as the feature set of
the design. Each feature has associated attributes that may be quantified with selected values and structurally arranged to reflect its nature, thereby defining its associated coverage model.

Performance analysis is an important aspect of TLM 2.0-based system design. While case-specific performance analysis can be hand coded into any model, it is possible to compute useful performance
analysis metrics in a generic fashion for TLM 2.0 models.

Most companies today aim to leverage existing design and
verification IP as part of the design and verification flow. Internal IP
is developed, tuned and reused over time to become a major
company asset and can be a competitive differentiator. A key
requirement for developing a central verification IP (VIP) repository
is to avoid the need to understand the implementation details or
modify existing IP for use in follow-on projects. In working with
many large and small corporations, we find that while many
companies strive for such cross-company (and cross-project)
component reuse, only a few manage to achieve this goal. This
document describes the recurring practices that allow companies to
excel in productivity and reuse.

With an increasing number of companies designing DSP into their products, the divisions between different specialities are falling away. Engineers and designers now have to have some knowledge of analog and digital designing, software engineering and mathematics as well.

Impedance matching is an essential part of antenna design. The input impedance of an antenna needs to be
reasonably close to the amplifier impedance (e.g. 50 Ohm), otherwise the signal is reflected back to the amplifier and not radiated by the antenna. In many applications matching circuits consisting of discrete inductors and capacitors, or transmission lines are used to improve the impedance matching characteristics of the antenna. This white paper discusses the optimization of matching circuits especially to antenna applications. Although the design of matching circuits sounds simple, there are many practical considerations that need to be addressed.

This project challenged students to design and prototype a wideband sequential power amplifier (PA). Sequential PAs offer similar efficiency benefits to Doherty PAs, but without the inherent narrowband restrictions. As part of the design challenge, a high-efficiency, broadband, 45 W peaking PA was required. A broadband Lange coupler for use as the output power combiner was required as well. Both of these designs were to be used in conjunction with a preexisting 10 W main amplifier.

This is where EasyCODE customers will always find the latest versions and updates for their products. We invite customers with older versions and interested users to download and test these product versions, free of charge and with no obligation, so they can see for themselves on the basis of their own daily requirements just how beneficial EasyCODE can be.

We propose a new methodology flow which will allow the visual definition of a complex SoC through instantiation of parametric IP such as processors, SDRAM controllers, DMA engines, on-chip buses, peripherals, switch matrices and coherency directories, coprocessors, etc.
Script based automation helps in integrating any IP with any configurations ,selects relevant and corresponding Verification IPs(in-house developed-if Design IPs are standard), uses suitable Bus Wrappers(OCP,EBI,Avalon,MicroBlaze,PicoBlaze,PIF,AXI,AHB,APB,Generic and others) and stitches all the components design as well verification(synthesizable testbench components ) together and making use of TLMs,BFM (replacing CPUs with Master BFMs) or Process Core based designs creates an CSOC environment.
The framework reduces the time to build integration and verify the functionality-it also has the complete set up from assembler to DFT.

Designers reduce board layout and placement time from weeks to minutes through CircuitSpace® AutoClustering™ technology, intelligent design (IP) reuse, and replication. Reductions in PCB design time have a direct impact on time-to-market for new products, which directly correlates to profitability.

Despite many efforts to automate analog design and layout, these tasks remain primarily a full custom process, ; with the result that analog is occupying a larger and larger portion of the total design cycle time. Efforts to automate analog design have not been successful in the marketplace because the tools have not been able to equal the quality levels of full custom design, are complex to set up and use, and are expensive.
Tanner EDA’s new tool forgoes full automation in favor of accelerating the layout process by generating key analog design primitives, such as current mirrors and differential pairs. These primitives are often the most time-consuming aspect of layout and indeed the parts that are critical to the functionality of the silicon. The new tool applies matching techniques to address common processing artifacts, produces the optimal solution for parasitics and silicon area, and creates devices optimized for high yield. This paper outlines explains how.

The recent years have seen LSI design complexity continuing to rise sharply. This phenomenon translates itself in the design specifications as they include non-deterministic parts more and more frequently. For example, in cases of designs using packets for data transmission, packets transfer order is determined by precise rules. But, depending on the timing of the transactions, the final order might be hard to predict.

All testbenches, even the simplest testbenches, need some kind of configuration knobs (sometimes called configuration fields or configuration parameters) that are used to control setting up some feature in the verification environment. Ideally, the environment also includes some kind of mechanism that allows test writers a way to override a configuration knob’s default value. Configuration knobs are typically setup in the testbench during the building phase and directly used for DUT (Design Under Test) initialization. There are various categories of configuration knobs including (but not limited to) testbench topology knobs, simulation specific knobs, verification component knobs, and testbench specific knobs.

While Silicon Realization encompasses most of what the industry has defined as
traditional “EDA,” it goes far beyond this definition by outlining a deterministic path to silicon that is broader, more efficient, and more effective than today’s point-tool based approaches. In its fullness, Silicon Realization addresses the business and technology challenges of complex silicon development, and enables design, implementation, and verification teams to attain higher levels of productivity, predictability, and profitability.

The Flight Computing System of a Novel Nano-Satellite takes advantage of the NI LabVIEWTM Embedded Module & the Low Power Mixed Signal ADI Blackfin® Target ZMobile to Achieve Precise Spacecraft Attitude Determination & Control.
The spacecraft “PurdueSat”, classified as a nano-satellite, is currently being developed by the School of Aeronautics and Astronautics at Purdue University.

This application note describes how to configure and connect the DesignWare® SATA AHCI IP core to the Synopsys PHY in a multi-port AHB-based configuration, and provides an analysis of the expected throughput on each port based on assumed system parameters. The expectation is that a user should be able to take this example and insert actual system parameters to come up with a performance estimate. We will look briefly at the architecture of the core to enable a better understanding of the subsequent sections describing the configuration and performance calculations of the core. Also, note that while this document only discusses the performance of an AHB-based configuration, the option to select an AXI-based configuration will be available in the near future. Due to the nature of the AXI-bus, which allows for overlapping transfers, we expect an increase in the performance of a multi-port configuration.

IC designers responsible for the physical implementation of the design face a huge problem of design
sign-off analysis. Today, they need to use different tools to verify the various design aspects, such as
timing, power, voltage drops, and chip temperature. The problem is that each of these analyses needs
the results of all the other analyses. Therefore, typically, these tools are run sequentially in a flow, so
that the results of one tool can feed the next tool.

Code coverage is a popular method to find design bugs and verification loopholes. However, once a piece of code is determined to be unreachable, diagnosing the cause of the problem can be challenging: since the code is unreachable, no counterexample can be returned for debugging. Therefore, engineers need to analyze the legality of nonexistent execution paths, which can be difficult. To address such a problem, we analyzed the cause of unreachability in several industrial designs and proposed a diagnosis
technique that can explain the cause of unreachability. In addition, our method provides suggestions on how to solve the unreachability problem, which can further facilitate debugging. Our experimental results show that this technique can greatly reduce an engineer’s effort in analyzing unreachable code.

In today’s hardware development, SystemC code is
widely used for virtual prototyping, where an abstract system
model is used to do an early exploration of the hardware
implementation as well as software development. The synthesis
tools, on the other hand, conventionally still rely on VHDL as
the entry language.

Power intent verification, whose complexity increases exponentially with the number of power domains and the number of different power states those domains can assume, is further complicated by the need to integrate digital and mixed-signal IP blocks. Digital IP blocks may be complex enough to have their own advanced low power techniques implemented internally.

Low power has quickly become a primary requirement for a large percentage of designs. As companies rush forward to incorporate the latest low power features, they are faced with the growing challenge of how to verify these complex structures and ensure successful silicon.

Virtual Prototypes (VPs) based on Transaction Level Modeling (TLM) have become a de-facto standard in today’s SoC design, enabling early SW development. However, due to the growing complexity of SoC architectures, full system simulations (HW+SW) become a bottleneck especially if a high timing accuracy is required.

For ultra-scale SoC designs that are now commonplace, it has
become impractical to use only traditional RTL design and verification techniques. ESL methodologies, used for designing at
levels of abstraction above RTL, are instrumental in determining design feasibility, honing requirements, and experimenting with architectures and algorithms to meet functionality as well as
performance and power requirements.

With design complexity growing by the day, the need for verification
technologies that can complement simulation based verification is
also gaining momentum. Formal verification has clearly emerged as
one of the strong candidates. In a typical simulation based
verification cycle, the number of bugs reported grows exponentially
in the beginning, but this number shrinks rapidly thereafter in the
cycle and what remains is a few difficult to find corner case issues.

We define four abstract models in common use today for electronic
design—electrical, digital gate, digital RTL, and transactional—and
discuss the relationships among them. The new low-power model
described by IEEE Std 1801-2009 UPF is introduced, and its
relationship to the other signal-level models for digital and analog
design is defined.

With the increasing complexity of systems, the
current simulation based circuit verification used in industry
are becoming more expensive while providing low coverage. The
paper presents a systematic way to reduce the verification time
by optimizing the execution order of test cases. Compared with
the default order maintained by engineers, the optimal order can
achieve a high coverage in a short time as it guarantees running
the important test case first.

Pin multiplexing is a common practice applied in order to save large number of pads in an SoC. This reduces the Die area of the chip but impose a number of limitations, like requirement of dedicated, complex pin muxing circuit. Traditionally there are three major types of pin multiplexing circuits which are in use; arbiter based , resgister configurable and priority muxing . Out of these , priority muxing simplifies the muxing strategy as it muxes the various functions together on the basis of timing criticality , also it utilizes the IP’s in built select signal . In this paper we propose a novel MUX cell design which can be applied at the places where priority muxing is used. This muxing strategy enables muxing of functions with equal timing criticality together at one single pad even with the priority intact. Which in turn limits the number of high driving pads in SoCs hence saving power and area both? The proposed circuitry is technology independent and also saves area . This circuit is applied in a SoC at 90nm technology by replacing traditional priority based pin muxing and almost 72% area saving and significant interface frequency increase is achieved

The goal of this presentation is to illustrate the requirements for automated analogue behaviour modelling techniques from the viewpoint of the designer. In the first paragraph the reasons for using
behavioural models are explained. Next the desired features of such techniques are given in general terms. Finally some of the available methods and tools are presented as an example.

Processor verification typically involves simulating the processor core(s) with their associated memories, loading those memories with diagnostics and letting the processors execute the code. A series of external checkers verify that the processor is functioning correctly by comparing it to a C++ instruction set reference model.

The thresholding inverters are the key to the TIQ based ADC circuit. For an n-bit ADC, total (2**n)-1 TIQ comparators are required. Each of the (2**n)-1 TIQ comparators are different from each other. We use special layout technique to generate (2**n)-1 unique comparators, the Systematic Parameter Variation (SPV) technique. The SPV technique is based on the spice parameter provided by the chip fabrication vendor.

Like any new technique that is introduced in the market, digital power control must first prove that it offers important advantages over state-of-the-art analog techniques. In this vein, the first and foremost issue to be addressed is the price, and the secondary considerations are converter size, performance and efficiency. This article covers these issues and also discusses digital power control from a broad standpoint.

Achieving the least possible delay in a video capture, streaming, and display system can be surprisingly affected by the specific H.264 encoder near the beginning of that flow. Read this white paper to learn more about what determines latency, and how to pick the best encoder for achieving low latency in your systems.

The Paper describes a model based approach to improve the robustness and re-liability of an embedded system with respect to real-time performance. It charac-terizes how real-time simulation models are generated, run and analyzed to gain knowledge of the dynamic system behavior. The system’s reactions to dynamic stimuli can be predicted without having to implement all hardware and software. A study with an automotive car body control unit illustrates how the timing model is developed parallel to the development progress. Findings and improvements are listed. Besides the technical aspects, the business impact for the current and future systems proves significant advantages of the chosen approach.

The increasing complexities of modern SoCs and short time-to-market requirements have
made efficient reuse of in-house and 3rd party IP mission critical. Since most IP requires
some degree of modification before reuse, it’s critical to address the root problems of
efficient comprehension, modification, and re-verification in IP reuse.

This paper describes a promising new technology and methodology that consists of
putting IP through a "reuse enabling" process. The resulting database is used by the IP
consumer with an analysis tool that allows both dynamic association of the relationship

In this paper, we will describe how a complete graphics processing
pipeline was implemented using an HLS methodology. As with most
real-life applications, this design consists of a complex mix of control logic, datapaths, interfaces, and hierarchy.

This paper discusses the experience of using plan and metric-driven
verification on a recent mixed-signal integrated-circuit (IC) prototype at Medtronic. The design consists of digital and analog
circuits which traditionally have been verified with unique tools and methodologies to perform simulation tests.

Intel defines numerous forms of reusable IP that are leveraged by many projects across different divisions and business groups. In order to ensure the successful reuse in the various system topologies demanded by Intel design teams, compliance of the IP to the specification is critical.

With shrinking process geometries, static and
dynamic power are increasing rapidly, forcing
designers to use a variety of implementation
techniques to control power. MIPS Technologies
processor cores designed for low power
applications use multiple power modes and employ
a Power Manager to ensure correct transitions
between these modes. This paper focuses on the
verification of the Power Manager in the context of
the – MIPS 1004K™ Coherent Processing System
(CPS), in which various software and hardware
events can control switching of power states.
Without exhaustive verification of the Power
Manager, the power management functionality of
the design cannot be guaranteed. This paper
discusses on how we successfully used formal
methods to verify the Power Manager.

Simulation and formal verification traditionally have been treated as completely separate processes. Simulation is procedural and dynamic in nature, highly efficient at testing basic functionalities, but can be difficult to control to target corner case scenarios. Formal is static in nature and highly efficient at finding corner case bugs, but it has serious capacity limitation due to state explosion. Each has its own advantages and limitations.

RTL-to-gate logic equivalence checking is a very
critical step inside circuit design flows. It is used to make sure
the gate-level circuit doesn’t alter functional behaviors of the
RTL. Of the various commercial logic equivalence checking
tools, Combinational Equivalence Checking (CEC) tools are often
used to prove equivalence between RTL and gate due to their
high efficiency and good scalability. However, unlike Sequential
Equivalence Checking (SEC), which traverses the product Finite
State Machine (FSM), combinational equivalence checking proves
equivalence for combinational circuits (i.e., Equivalences are
formally verified for combinational logic cones between the state
points.).

ESL Virtual Platforms are powerful tools to enable early software development and architectural exploration. However, there is often a need to integrate RTL models into the ESL environment, either for legacy blocks, or because a cycle-accurate model is required.

This article describes “asureMark™ ” ‐ the
Functional verification Capability Maturity Model (FV‐CMM™) benchmarking process developed by TVS to help the user measure the maturity of their verification processes and to provide a framework for planning
improvements.

A group of leading semiconductor companies have developed a roadmap for leveraging CMOS designs intended for manufacturing on bulk silicon to fabricate ICs on fully depleted silicon-on-insulator (FD-SOI) substrates with ultra-thin buried oxide layers, producing chips with improved performance and lower operating power. This white paper shows that porting circuits from bulk silicon to FD-SOI can be very direct, depending on the FD-SOI technology used by a specific chipmaker.

Power line communications (PLC) is a global
technology with worldwide interest in its development. In its simplest terms, PLC modulates communication signals over existing power lines. This paper highlights specifications for several PLC alliances and specifications and discusses new proprietary PLC technologies.

i have been ardent fan of Toyota manufacturing.Toyota was the first company who streamlined the processes and quality matrix in the factory units , established a flow and performance management in for the workers and implemented a methodology to track the production.This was indeed very different from the Ford(American) and other European companies who till then have been very much stressing on the luxury ,customization etc etc..

Cadence® Allegro® Design Entry CIS integrates a proven schematic-design-entry
system with a robust component information system (CIS). Whether used to
design a new analog circuit, revise a schematic diagram for an existing PCB, or
design a digital block diagram with an HDL module, Allegro Design Entry CIS
allows designers to enter, modify, and verify the PCB design. It also promotes
reuse of preferred components and known good-part data.

When selecting and evaluating debug interfaces and tools for ARM microcontrollers
many aspects have to be regarded. This article provides some guidance what should
be taken into consideration. More detailed information is available from ARM or the
according chip manufacturer.

Assertions are properties or facts describing the required and forbidden behavior of a design. They are “executable specifications” that are monitored during simulation by assertion checkers included in the design file.

Use of behavioral description and HLS (high level synthesis) flow has allowed designers to shorten design TAT (turn-around- time) with its better performance in hardware description, functional simulation and RTL generation when it compared to the design flow with RTL designs.

In this paper, we introduce the concept of full-chip mixed-signal validation (FCMSV) for SOCs, in which any top-level ports of an analog discipline are represented as real-valued signals for validation simulations. Secondly, it exploits SystemVerilog syntax, especially “real” ports, to create one testbench suite that spans a project from top-down development to final bottom-up implementation. Thirdly, it presents a global strategy to improve simulation speed by targeting specific analog blocks for replacement by BMODs. This methodology is a generic strategy independent of EDA tool. The methodology and environment outlined in this paper have been successfully applied to validate three successive projects.

Due to increased complexity in today's SoC designs, the importance
of design reuse, verification, and debug becomes inescapable.
SystemVerilog [1], VHDL [2], and SystemC [3] have unique
strengths which make them more suitable to certain application
domains. Mixed-language designs are proliferating because
designers want use the powerful features of one language for creating
test benches for designs written in the other language. Diversity of
design teams with their different preferences, and integrating a
growing number of IP blocks in a SoC, often written in different
languages, also leads to a mixed-language scenario.

The Accellera Verification IP Technical Subcommittee (VIP-TSC)
has spent the past year-and-a-half developing an interoperability
class library to allow OVM- and VMM1-based VIP to work together
in a single environment. This paper will describe the primary
obstacles we encountered while bridging these two independentlydeveloped
methodologies.

IP reuse has long been touted as one of the key factors in enabling
development of today’s complex SoC designs. The concept of reuse
seems simple and easy in theory, but there are a number of obstacles
that design and verification teams must address to be successful,
especially in the case of commercial IP cores. One of the significant
barriers to IP reuse today is the wide variety of design languages
used in IP.

Today's complex designs, especially those targeted to deep submicron technologies, demand a good methodology at all stages of the design cycle in order to meet the quick turnaround requirements of customers.

Introduction: The dual electromagnet configuration of Active Magnetic Levitation system (AML) where the electromagnets are locate opposite to each other, constitutes and single axis of the Active Magnetic Bearing. The same configuration can be used to test the single electromagnet AML controller. A single electromagnet AML was modeled and simulated with COMSOL Multiphysics. The modeling and simulation of the AML configuration is required when a new devices are designed or existing one are modeled for the verification and controller synthesis purposes. In both cases there is a request to add the control feedback to keep the levitated object at the desired position. Therefore, the model must be extended with the motion dynamics and controller formula. Such models are also useful for educational purposes to demonstrate interdisciplinary aspects of modeling, simulation and control. Use of COMSOL Multiphysics: Modeling with support of COMSOL Multiphysics is well suitable for educational and research purposes.

The magnetrons used in microwave ovens operate on the same frequency band as Wi-Fi equipment, and the radiation they release can interfere with the operation of wireless networks. This paper presents a multiphysics simulation of a magnetron using CST STUDIO SUITE®, with the aim of testing the electrical, magnetic, thermal and mechanical characteristics of a low-interference magnetron design.
The simulation results are then compared to measurements made experimentally, and the two sets of results are shown to be in good agreement.

Chip designers worldwide have told us that Jasper is fundamentally different in how we approach their technical and business problems by delivering a high ROI (return on investment) through the application of advanced formal verification techniques. Our tools address a spectrum of key verification challenges – from getting the architecture unambiguously right, to putting more power in the hands of designers, to promoting design reuse, to verifying critical functionality, to reducing process bottleneck, and even silicon debug.

This presentation/whitepaper is targeted for developers who already have an understanding of the Bluetooth technology and who would like to get a quick understanding of the new features introduced in Bluetooth 3.0 + High Speed version of Bluetooth Specification.

Current source based cell models are becoming a necessity for accurate timing and noise analysis at 65nm and below. Voltage waveform shapes are increasingly more difficult to represent as simple ramps due to highly resistive interconnects and Miller cap effects at receiver gates.

Our abilities encompass a wide variety of skills, commencing with the initial design and innovation of a product and culminating in the ongoing manufacture of a complete product or assembly. These turnkey solutions are individually tailored and are designed around each customer’s specific requirements.

Software developers today face significant opportunities and challenges. The appetite that both organizations and consumers share for software has made development a dynamic and competitive business, creating opportunities for large companies and start-ups alike.

Due to increases in design complexity, routing a reset signal to all registers is becoming more difficult. One way to
solve this problem is to reset only certain registers and rely on a software initialization sequence to reset other registers. This approach, however, may allow unknown values (also called Xvalues)
in uninitialized registers to leak to other registers, leaving the design in a nondeterministic state. Although logic simulation can find some X-problems, it is not accurate and may miss bugs.
A recent approach based on symbolic simulation can handle Xs accurately; however, it is not scalable. In this work we analyze the characteristics of X-problems and propose a methodology that
leverages the accuracy of formal X-analysis and can scale to large designs. This is achieved by our novel partitioning techniques and the intelligent use of waveforms as stimulus. We applied our
methodology to an industrial design and successfully identified several Xs unknown to the designers, including three real bugs,
demonstrating the effectiveness of our approach.

Schottky diodes use a metal-semiconductor junction as opposed to the semiconductor-semiconductor junctions used in standard diodes. This configuration allows for lower forward bias voltage drops (0.15V - 0.45V vs. 0.5-0.7V) and faster switching times, making them ideal for power supply switching operations. Drawbacks for schottky diodes include much higher reverse bias leakage current ratings. Because p-n recombination is not a factor in switching delay time, only capacitance affects the reverse switching time.

H.264 high and baseline profile codec systems are implemented on Virtex-5 multi-
FPGA board. The codec supports full HD class video and the FPGA board called
iNEXT consists of up to four 33-million FPGA.

Even in the very early days of electronic components failures appeared. Despite enormous development and production improvements this situation has not changed. Even automated equipment faults
continue to be created on circuit boards There is not a single manufacturing technique that will guarantee the 100 percent fault free circuit board. Each new technology creates new challenges and test methodologies to ensure fault free boards.

Many of the developments in silicon, software and development tools that embedded engineers use today first
appeared in disciplines other than embedded computing, and have been adopted and adapted from these other
disciplines to meet the requirements of embedded projects. For example, the C-language was developed at Bell
Labs for implementing system software on Unix machines, and GUIs found their first applications in gaming
machines and PCs.

Applications for non-volatile memory (NVM) encompass a wide range of programming
requirements. Some products require one-time programmable (OTP) memory that is
programmed during chip fabrication – mask ROM is good for this purpose if the code is frozen.
Other products need field-programmable OTP for applications such as analog trimming,
necessitating the use of secure in-system programmable NVM.

Proposed approach to increase the accuracy of channel simulations by including back-channel communications. The IBIS AMI modeling standard can be readily extended to support the new approach. This expands on the presentation given at the IBIS meeting in February, 2011. Related Sigrity products: SystemSI - Serial Link Analysis.

BSIM3 was developed in an effort to solve the problems of semiempirical models and as a complement to BSIM 1-2. It has extensive built-in dependencies of important dimensional and process parameters such as channel length, width, gate oxide thickness, junction depth, doping concentration, and so on.

6TL Engineering, headquartered close to Barcelona, Spain, producesmodular test platforms that fast-track development of customised electronic production test equipment. The platforms save specialist integrators and in-house test-engineering teams from spending time and effort to implement core functionalities such as control processing, power supplies, instrumentation and commonly used test functionality. Standardised interfaces allow customers to connect their own test fixtures and add specific test capabilities quickly and easily using 19-inch rack modules or, optionally, PXI modules.

FMR spectra of the periodic microstructures (one-dimensional magnonic crystals, 1D MCs) were obtained using COMSOL with use partial differential equation interface. Results of these calculations were successfully compared with an experimental data for Damon-Eshbach (DE) and Backward-Volume (BV) geometries. The presented tool allows to analyze periodic structures with various geometries and material parameter compositions, being at the same time a tool that can serve for optimization and tuning the absorption of electromagnetic waves in ferromagnetic materials.

In this paper an attempt has been made to design and analyze integrated circuit interconnects for unshielded four conductors with three levels system using Finite Element Method (FEM). The computational and simulation work has been carried out with help of COMSOL Multiphysics software. We illustrate that FEM is as accurate and effective for modeling multilayered multiconductor transmission lines in strongly inhomogeneous media. We mainly focus on designing of two electrostatic models of unshielded four interconnected lines with three levels system. We computed the capacitance and inductance matrices for these configurations.

This paper focuses on the diaphragm design and optimization of a piezoresistive Micro Electro Mechanical System (MEMS) pressure sensor by considering Very Large Scale Integration (VLSI) layout schemes. The aim of these studies is to find an optimal diaphragm shape by Finite Element Method (FEM) using COMSOL®, which is most suitable for VLSI layout. Optimal diaphragm shape is a diaphragm shape that results in reasonable output stimuli with minimal deflection and stress. Three different shapes of diaphragms are considered in this study are circular, square and rectangular. Not only form the VLSI layout aspect, but also from the pressure, stress and sensor output considerations, square shaped diaphragms are preferred.

CST PCB STUDIO™ is a specialist tool for the investigation of Signal and Power Integrity and the simulation of EMC and EMI effects on PCBs. Regardless of the application type – high speed digital, analog/mixed signal, or power supply – CST PCB STUDIO (CST PCBS) will help you to get it right first time.

With an install base of over 1.1 billion devices worldwide, HDMI has become the de facto multimedia interface for all digital home and mobile/portable multimedia devices. The recently introduced HDMI 1.4 specification further reinforces the HDMI message of performance, reliability and simplicity. Features like the HDMI Ethernet and Audio Return Channel (HEAC), introduced in version 1.4, further simplify digital home theater wiring while adding new and innovative features. In addition, the HDMI 1.4 specification supports advanced media capabilities such as enhanced color spaces for digital still cameras, 3D modes and ultra-high resolution display formats (up to 4x higher than 1080p) that will be key features in the nextgeneration of premium multimedia entertainment consumer electronic products.

EDWinXP is a Total Integrated EDA/ECAD Software package of seamlessly integrated, task oriented modules covering all stages of the electronic circuit design process - from capturing the idea of a circuit in the form of schematic diagram to generate a full set of documentation for manufacturing and assembling of PCBs". It is a complete suite that has Schematics Editor, PCB Layout Editor, Fabrication manager, Library manager and many more

The bank is part of a large European group that was founded more than a century ago. Headquartered in Paris, the group has a presence in more than 60 countries and employs more than 160,000 professionals. The group controls assets over 588 Billion Euros and owns market capital of just under USD 20 Billion.

Bugs in RTL code are problematic, but a bug in an architectural specification can be catastrophic. If the bug remains undetected until post-silicon debugging, the design process essentially starts all over again.

PCB Layout CAD software programs are undergoing dramatic and significant changes as companies release new versions at an increasingly rapid rate. These new versions not only fix bugs, but they add additional features and versatility.

Our abilities encompass a wide variety of skills, commencing with the initial design and innovation of a product and culminating in the ongoing manufacture of a complete product or assembly. These turnkey solutions are individually tailored and are designed around each customer’s specific requirements.

The market for voice over IP (VoIP) products is one of the fastest growing and fastest evolving markets in the high-tech world. Enterprise level VoIP is expected to grow 20% annually through 2009, according to The Insight Research Group. To stay on the leading edge, companies like Zultys Technologies must emphasize short time-to-market, lowered costs, and superior quality.

This paper presents a study of verifying a memory controller using a static functional verification tool. Static functional verification is a new technology that does not use vectors or dynamic simulation but analyses the behaviors of a design
by the use of a property language. This paper presents the design and verification challenges of a controller, and how static verification was used to debug the design, what improvements were seen in methodology, and what was achieved and learned by using a static tool.

The increasing complexity of system-on-a-chip and ASIC designs has caused an ever-widening gap between what can be designed and what can be. It is estimated that between 50-70% of the time required to design a complex IC is spent in verifying that the functionality of the system is correct. Bugs in a design are least expensive to fix just after they are created. At this stage the design is still fresh in the designer's mind and other parts of the project or other design team members are unaffected. Bugs are at least an order of magnitude more expensive to fix during system integration. In this phase it takes more time and people to analyse the cause, regression tests must be rerun, and the entire group may be delayed. These challenges are giving rise to some exciting new tools and approaches in Verification techniques.

Paper by Mike Turpin of ARM, Ltd., describing how to use Solidify for Sequential Equivalence check in order to uncover hidden "X" values in a design. This is particularly important for an IP provider where the RTL may be implemented using different synthesis flows. Hidden X's can cause differences between RTL simulation and the actual silicon, which are not caught by design flows that rely on other tools such as Logical Equivalence checking.

SimCluster is an innovative parallel, distributed simulation environment that provides a scalable, open, and flexible solution to increase RTL and gate-level simulation performance and capacity by 300-700% or more. SimCluster supports Verilog and VHDL design methodologies and the most popular simulators (NCVerilog, Verilog-XL, VCS, and ModelSim), hardware accelerators, and emulators.

Serial communication protocols are the backbone
in today’s automotive electric/electronic-architectures. Protocol
conformance is of paramount importance to ensure interoperability,
error free and reliable communication of electronic
control units.

NAND FLASH memories are non-volatile, inexpensive and of high capacity. These
characteristics make these devices ideal for fulfilling the storage requirements in the
exploding mobile device market.
Designers using NAND FLASH devices should follow the ONFI standard interface to ensure that their controller design will operate with devices from any vendor. The memories need both digital and analog interfaces between the devices and the system they serve.
When designers add NAND devices to the system design they must consider the least
expensive and lowest risk means of implementing the controller.

Over the past few years the discussion of hardware verification
languages (HVLs) has come full circle. At first, verification
teams tried to assess the strengths and weaknesses of individual
language features with the goal of creating their own verification
libraries and environments but generally without the context of a
reuse methodology. As these groups became more sophisticated
and sought to exchange and reuse verification IP (VIP), they
coalesced on the two IEEE standardized verification languages –
1800 SystemVerilog and 1647 e and moved toward the industry
supported methodologies and libraries built with these
languages. With the advent of a single methodology
implemented in both languages – OVM multi-language – the
discussion has returned to HVL features but now that the reuse
methodology known, a clear apples versus apples comparison is
now truly possible.

There are two main techniques used for RTL validation: simula-
tion and formal verification. The main drawback of simulation is
its inability to provide satisfactory design coverage when the num-
ber of important scenarios is very large. Formal verification pro-
vides exhaustive coverage, but its capacity is insufficient for realis-
tic designs.

Virtually all modern SoC designs today are mixed-signal in nature.
Most systems have to interface their millions of gates, DSPs,
memories, and processors to the real world through a display, an
antenna, a sensor, a cable or an RF interface. The already complex
task of functional verification at the SoC level is getting harder and
more time consuming. Up until recently, mixed-signal designs
could be decomposed into separate analog and digital functions.

Each DAC, we see a wealth of verification products proposed by those EDA companies exhibiting at the conference. All promise to solve the ever increasing time-to-market pressures, the escalating integration of embedded software and high-performance imposed on electronic products.

Thread-Metric is a free benchmark suite designed to measure the performance of an RTOS. It can be adapted to measure any RTOS, enabling performance comparison to assist in RTOS evaluation and selection. Links below provide a presentation that describes the Thread-Metric suite, and the code itself.

A mobile transceiver chip was designed by a fabless IC company and built on a SiGe BiCMOS process. The chip functioned properly in most aspects, except that it fell short of the RF power output specification. So the analog and RF design team rushed to debug and correct the problem.

This paper presents a new methodology to
characterize and simulate the electro-thermal aspects of packaged power drivers using lateral bipolars. Maximum elevation of junction temperature due to the electrical
power stress is sensed in the field of the drivers. Those measurements are further complemented by the transient
interferometric mapping (TIM) inspection.

Since its standardisation as IEEE 1149.1 in 1990, JTAG / Boundary Scan has developed to
one of the most important technology within the ensemble of various test strategies. This
topic’s high dynamics and practical relevance are marked by constantly new operation fields, system solutions and definitions of pursuing IEEE standards.

In the previous article we saw how traditional methods of increasing the performance of computer systems are reaching a plateau, while the advent of multicore processors has brought the seemingly impossible prospect of ever‐increasing performance without excessive increases in power consumption.

Hardware verification engineers have always faced the complexity of concurrent
execution and temporal considerations when verifying hardware designs. However, silicon manufacturers are now moving to multicore designs (i.e. multiple CPU cores on a single chip) to achieve the relentless drive for improved performance at lower power now demanded by consumers.

Delivering advanced system solutions since 1988, Signatec is a leading designer and manufacturer of high-speed, PC-based data acquisition, parallel and FPGA digital signal processing, continuous signal data recording and arbitrary signal generation systems. Signatec differentiates itself by being one of the only single-source suppliers that works with its customers to build affordable, real-time signal technology systems for advanced radar, SIGINT, ultrasound, imaging and other high-speed communications systems.

This paper aims at presenting a new model-based flow targeting analog/RF circuits sizing with significant improvements of parametric yield at a
very early stage in the design phase. The flow is then applied on a ST Microelectronics [2] LDO regulator design. In a first step, the regulator is modeled. In the second one, the design is optimally
sized. The process parameters are then modeled, and finally the sensitivity of the design to the process is analyzed.

Like all RF and microwave components, a differential fi lter design will remain only
a simulation exercise if it is not created with its manufacturing process in mind.
That is, the tight dimensional tolerances required to meet a set of performance
goals must be within the capabilities of the fi lter’s manufacturing process in order
to realize a reliable, repeatable fi ler.

Although all real engineers would like to create all of their designs from scratch, that just is not practical in today’s fast-paced ASIC development world. The need to integrate intellectual property (IP) from third-party providers is the reality.

ESO is the intergovernmental science and technology organisation in astronomy. It is carrying out an ambitious programme focussed on the design, construction and
operation of powerful ground-based observing facilities for astronomy to enable important scientific discoveries.

In contrast to accelerator devices
that attach to an expansion bus,
the new generation of computing
devices based on field-programmable
gate arrays (FPGAs) sits in processor
sockets and has the same access to system memory as a CPU.

Even a single sided a board can be viewed from above or below. Clearly marking all layers with right reading text will enable the board manufacturer to verify the proper orientation for your board. The more layers that are employed to make a board, the more important this becomes.

Cadence Virtuoso is one of most popular applications used by engineers in the semiconductor industry for completing various tasks related to a chip design project. This document provide instructions on how
to better optimize Exceed onDemand to maximize the performance benefit.

A GC Construction Manager in Connecticut and New York reduced overhead costs by 15% with Chameleon, another solution from Construction Imaging. “Chameleon has also helped us take advantage of payment discounts. We know which manager has an invoice at all times and can remind them if a discount is available.”

Written by Gregg Oetting, this technical paper highlights the expectations and challenges of data translation and the importance of model repair and validation. Based on a broad suite of test results, this paper can be an invaluable tool in customer engagements to help highlight the true cost of low quality translation.

Failure in cable insulation is generally preceded by a degradation phase that may last several years. A significant cause of cable system failures is the breakdown of electrical insulation between the electrodes. The operational stresses that occur in cable insulation which include thermal, mechanical and electrical effects will vary with time and can cause degradation due to the resulting physical and chemical changes in cable properties. It is widely recognized, irrespective of the causative mechanism, that degradation results in partial discharges (PDs) being generated at the degradation site(s). PDs are small electrical discharges produced by local enhancement of the electrical stress due to conditions around the fault. The internal discharge in insulation material and/or at its interface is caused by the strong and inhomogeneous electrical fields that are usually caused by voids, bubbles, or defects. Treeing discharge is also associated with internal discharge, and it starts from conducting particles or a void in solid insulation. This paper investigates the electric stress within an armoured XLPE insulated cable containing a void-defect. The finite element model of the performance of an armoured XLPE MV underground cable containing void-defect is developed using the COMSOL multiphysics. Use of COMSOL Multiphysics (Electrostatic model): a two-dimensional model of a single-core Cross-Linked Polyethylene (XLPE) cable containing a void-defect has been developed using the COMSOL multi-physics environment. The electrical field distribution in a typical cable construction, is described by a two-dimensional field model. The model is solved for a non-degraded system configuration as a base for further analysis. In addition, an air-filled void is introduced into the model cable insulation to investigate the effect of void presence on the XLPE electrical field insulation system.

This paper will describe some applications of COMSOL Multiphysics to the analysis of Frequency Selective Surface (FSS) structures. Particular attention will be devoted to the possibility of designing a stealthy antenna using the FSS structure. In fact, since it possesses a dual filter concept of frequency and polarization for electromagnetic wave, the Radar Cross Section (RCS) of the antenna is reduced.

We perform EM simulations of a low-pass microstrip filter consisting of a cross-junction open stub and two unit sections implemented as defected ground structures (DGS). The defect introduced by unit sections corresponds to an etched lattice on the copper backside ground plane. The filter presents wide and deep attenuation characteristics in the stopband. Different model implementations were carried out with the aim at evaluating the computational costs versus accuracy. Simulations of a high-fidelity model are in good agreement with experimental data reported in a previous paper. COMSOL simulation settings, enclosing box, computational costs, and simulation times for the considered models are provided.

The waveguide device modeled here specifically demonstrates the exploration of a small, but very important, subset of components of the family of microwave hardware devices designed to facilitate the optimized transfer of power from the generating source to the consuming load. Each of those components is called, in electronics terminology, a Tuned Stub.
A stub is a length of transmission line or waveguide that is connected to the active circuit at one end only. This paper models a
rectangular waveguide with three adjustable stubs distributed along the upper surface of the waveguide. The waveguide stubs are hollow, as is the waveguide, and they are each electromagnetically connected to the inner cavity, at right angles to the central axis of the waveguide via an aperture in the wall of the waveguide. In this case, three (3) stubs have been added along the length of the waveguide to optimize the tuning performance.

Nanoantennas have been successfully employed in a wide set of applications. We show the possibility to expand usual nanoantenna functionalities in the THz domain with a gold dipole nanoantenna. We considered an array of aligned planar gold nanoantennas over a silicon substrate. The high near field enhancement, localized at the device ends, indicates potential uses for THz spectroscopy and nonlinear optics. Far field properties of the gold nanoantennas are quantified with the resonance frequency positions of absorption and scattering efficiencies. The high field enhancement could be employed for the detection of few molecules with THz spectroscopy, since the effective absorption cross section of a molecule close to the nanoantenna ends would then be enhanced by several orders of magnitude.

The most commonly used approach to analyzing objects in an HDL design, is based on the well-known digital waveforms available with any commercial simulator today. Such a time domain representation of data with respect to time, allows verifying many parameters of a designed digital system, but it may not be efficient for applications such as image processing, digital filter design, embedded system design, and others. This document presents Plot, a new solution for a graph-based analysis of HDL objects, correlations between them, and a number of practical applications for it.

Today’s “smart” products leverage an intelligent combination of mechanical, electrical and software to deliver capabilities that weren’t achievable before. While bringing significant benefits for customers and for the companies that produce them, they brought as well a new level of complexity to product design and development.
In this Whitepaper, Tech-Clarity Research identifies the impact of "smart" products on engineering and product development and outlines a number of tangible steps using proven best practices and technology to improve mechatronics product development maturity.

"You could say the library is the brain of our development. All the information our developers need for their work is stored centrally, so they know, for instance, whether they can use a component for a new development or when it has been discontinued”
Lutz Napiwotzky, responsible for Engineering Applications Corporate IT at Bosch.
When the Bosch Group’s Automotive Technology Division, one of the world's leading suppliers to the automotive industry, analyzed their development processes, they quickly identified areas for improvement, including consistent data management. Each division structured data differently and stored it in different systems. As a result, tasks like tracing component use were inefficient and sometimes impossible.
After implementing Dassault Systèmes’ 3DEXPERIENCE platform Bosch engineers understand exactly which components were installed in which devices, including all configuration and material information. In particular, the component library structuring and versioning capabilities bring significant value to the Stuttgart-based company.

Blueprint for the design of a virtual reality camera recording and compressing 16 full HD (1080p) simultaneously sharing a single DDR3 DRAM chip with 16 bits data bus. Both I and P frames are used thanks to the reference frame compression with Compressed Frame Store (CFS) technology.

Since the introduction of the original USB standard in 1996, the USB interface has become one of the most successful connectivity standards. In today’s highly connected world, USB connections are found in the computing, consumer, mobile, industrial and automotive segments. Products are far ranging — from PCs and portable audio/video players to cell phones and digital TVs. With the trend of increasing data storage requirements driven by applications, such as high-definition video, combined with the desire to move this data quickly between host, storage, and portable devices, it was only a matter of time before there was a need to make this well-known standard even faster. This heralds the third-generation of this ubiquitous standard — the arrival of SuperSpeed USB 3.0.

The detection of the omni-present event chains in embedded applications goes far beyond functional modelling and static analysis. Once identified the analysis of their dynamics reveals a lot of data about the system like stability, critical paths or load reserves for future extensions. By using Task-Models and a real-time simulation tool the detection and analysis of event chains is very easy. Especially in distributed and collaborative development environments this is very helpful in reaching not only functional perfect systems but also delivering a high level of real-time quality.

Preparing a printed circuit board (PCB) design for manufacturing can often be a tedious and time-intensive task. A major trend in high-volume production designs is the use of complex powerplanes to keep layer count to a minimum and reduce the cost of manufacturing. Generating multiple types of manufacturing outputs helps widen the path to PCB manufacturing. Lastly, providing the fabrication vendor with accurate design data can directly improve product quality.

GiDEL is a leading designer and manufacturer of commercial FPGA computing, high end data
acquisition and processing board-level solutions. Based on Altera’s line of high-density FPGAs,
Gidel’s products provide innovative Commercial Off-The-Shelf (COTS) and application-specific
solutions for high-performance, real-time signal processing and I/O applications. GiDEL’s products
address OEM needs from prototype to production and span a variety of industry standard platforms.

Xilinx continues to refine the place and route algorithms in each of the ISE® software releases and provides up-to-date information on additional design techniques to help customers optimize routing in their Virtex®-6 FPGA designs, making it easier to reach performance and power design goals and achieve next-generation bandwidth requirements.

ACADto3Di is 3D modeler for IC packages that have been "drawn" inside of AutoCAD. It enables any package designer to create a 3D model from a simple bond document. Once converted to the 3Di format, the package can be viewed in 3D and the wires can have a full 3D DRC performed.

One of the most challenging tasks in analog circuit design is to adapt a functional block to ever new CMOS process technology. For digital circuits the number of gates per square mm approx. doubles per chip generation. Integration of analog parts in recent deep submicron technologies is much more difficult and additionally complicated because the usable voltage ranges are decreasing with every new integration step.

Formal Equivalence Checking (FEC) is a technique that formally
proves the equivalence of a schematics implementation
against a golden RTL model. This equivalence must be guaranteed
in light of possible multiple local hand-implemented
changes in the schematics. To overcome capacity problems,
FEC is usually performed on system sub-blocks, whereas the
“environment” is modeled with assumptions written using a
property specification language such as SVA. These assumptions
must later be proved relative to the driving logic. The
majority of FEC tools today are based on SAT-based model
checking formal verification engines. In this paper, we describe
an approach that can considerably reduce both the
time and computational effort required to complete FEC
activity in a project. It is based on an additional step introduced
to complement the traditional SAT-based model
checking algorithm. This step calculates a minimal set of required
assumptions using a new SAT-based algorithm. Minimizing
the set of assumptions greatly reduces the manual
debugging effort required of designers, as well as reduces the
number of iterative verifications.

The model-based development
of control algorithms on dedicated
rapid prototyping systems by means of
MATLAB®/Simulink® is an established
approach in numerous industry sectors.
As a rule, these development platforms
are based on powerful embedded
processors and operating systems that
ensure real-time behavior, fast booting
and reliable, autonomous operation in
the field. Extensive options for connecting
serial communication buses and I/O
channels are also usually available. These
systems are particularly employed in the
automotive industry, which uses them
to develop and test the functions of
electronic control units in actual vehicles.

As technology development begins to outpace manufacturing capability and price points continue to drop, semiconductor
manufacturers are searching for new strategies to meet these increasing demands. Shrikrishna Gokhale, Head of Sasken’s
Semiconductor Division, explains.

The objective of this document is to highlight Shax Engineering and Systems philosophy and methodology in facilitating engineering and design projects. Additionally, we will discuss the values that govern our elationships with our clients.

Systems such as smartphones and wireless PDAs include an application processor based on several processor cores (at least one CPU and one DSP), such as ARM, Freescale, ARC, TI and others. Verifying the application software that runs on a wireless device is usually a lengthy task.

Full-chip dynamic electro-thermal simulation is achieved by coupling a circuit simulator and a thermal solver. By letting both simulations run with their specific time-step, a higher computational efficiency is achieved. A scheduler synchronizes temperatures in the circuit simulator and dissipation patterns
in the thermal solver on an 'as-necessary' basis.

To that end, the company complements its Magellan line of point-of-sale (POS) scanners with three other product lines: the QuickScan family of general- purpose on-counter and handheld scanners for low-to-medium volume POS applications, the PowerScan family of handheld bar-code scanners for industrial users needing scanning capabilities from less than 1 in. to more than 36 ft, and the Falcon portable, vehicle, and fixed-station terminals and scanners that collect business-critical data throughout a supply chain.

Sigasi 2.0 Starter Edition is a freemium tool for VHDL design entry, code comprehension and design reuse.
It is designed to make existing text editors like Emacs and VIM obsolete. Full functionality of Sigasi 2.0 Pro is available for free, for small projects.

Chip/system co-simulation can provide the only effective way to identify chip-level power delivery issues that don't show up until the die is incorporated in the system. This presentation describes techniques for assessing a range of designs including 3D IC and 2.5D projects which incorporate silicon interposers. Sigrity products that are part of the TSMC reference flow are highlighted: XcitePI, PowerSI, OrbitIO, XtractIM and OptimizePI.

An IC socket can be defined as an electromechanical device, which provides a removable interface between the IC package and the system circuit board with minimal effect on signal integrity. A removable interface is the major reason for using a socket, and it is required for a variety of reasons, including ease of assembly, reworking, upgrading and cost savings.

According to Semico Research, the interconnect segment of the semiconductor intellectual property market will be $77M in revenue for 2007, with a compound annual growth rate of 31%, or roughly double the rest of the SIP market. Interconnect revenue surpassed DSP revenue as a category in 2006. The explosive growth of the interconnect segment is a result of the continued acceleration of the complexity being driven into single chip systems and the need to architect complex data flow structures. Outsourcing the interconnect design has become increasingly more economical.

The quality of results (QoR) and productivity shortfall statistics of functional verification by conventional simulation methodologies are well known: verification consumes 50% to 70% of design effort and design teams are spending more on verification tools than ever. Yet nearly 40% of designs require a respin and 20% require two respins - and the primary cause is functional error. Find out how hybrid simulation can save your budget and boost both QoR and productivity by turbo-charging your existing simulation methodologies.

For a long time ATE companies deliver
high quality ICT, Functional and Flying
probe Testers. Today’s Electronic
trends towards higher density and
speed has pushed electronic board
testers into an accessibility bottleneck
which affects peculiarly the Bed of Nails
(BoN).
It led ATE companies to allow add-on
JTAG testers, using Boundary Scan
technique, to restore the declining test
coverage. A seamless integration of
both technologies is mandatory to
make full use of Boundary Scan
promise.
While Marketers and analysts predict a
symbiotic future, SEICA and TEMENTO
SYSTEMS demonstrate an efficient
integration TODAY.

At 40 and 45 nm process nodes, power has become the primary factor for FPGA selection. This white paper details how Xilinx designed for this new reality in its recently introduced Spartan®-6 (45 nm) and Virtex®-6 (40 nm) FPGA families, achieving dramatic power reductions over previous generation Spartan-3A and Virtex-5 devices.

PCB designers have relied on CircuitSpace to
expedite their design process for several years.
One such customer is Troy Snow, Senior PCB
Designer with an Original Equipment Manufacturer
(OEM) located in Austin, Texas, who has been
using this software throughout his career.

Avio, a global leader in the aerospace industry with 5000 employees, develops and delivers subsystems and components to major international aeronautical, military, civil and space programs. See below how their trial of OpeniT software yielded a high return on investment, with a 47% reduction of their annual costs for all engineering applications used in Italy.

COMSOL, adding SPICE® elements into its FEM, gives the possibility of a direct modeling of oscillators: triode and load are FEM described while all the other components of the circuit are just simulated using SPICE®. The modeling is not a straight application of any module but needs the previous computation of the conductivity of the beam through the PDE interface. This paper is a bench mark showing the influence of the triode geometry on the performances of the circuit, mainly frequency and efficiency, and their evolution all along the process. It gives to the user of high power triodes/tetrodes the possibility to enter into their design in order to have a tube well matched to their needs, including on the thermal points.

This study is performed to know which central plate geometry is best suited for electrostatically actuated switch. The simulation is carried out in COMSOL Multiphysics, where user is free to model the geometry without depth knowledge about geometrical dependency of electrostatic. The study of the centrally suspended geometrical models such as circle, square and rectangle suspended by two short anchors is done. It is found that rectangular central plate suspended plate shows good deflection compared to other three geometries with constant voltage between for all three geometries.

This poster outlines the results of finite element analyses to study the antenna radiation pattern of an implanted medical device. Also presented are simulation results used to design an electrically small antenna for a portable control unit that communicates with the implants over the Medical Micropower Network Frequency Range [413 MHz to 457 MHz]. Alfred Mann Foundation’s Functional Electrical Battery Powered Micro-Stimulator system (FEBPM) uses a network of micro-stimulators to sequentially stimulate various nerves. The ultimate application of this technology is reanimation for patients who have suffered stroke, traumatic brain injury, or spinal cord injury.

VRALA is the ideal candidate as an Adaptive Optics actuator at visible wavelengths. Its electric characteristics variations, suitable current commands, and an effective magnetic circuit geometry provide a 2 kHz correction bandwidth and a 25 mm actuator density. The magnetic core allows unprecedented performances with a negligible thermal impact. Pre-shaping the coil currents greatly simplifies the control system. Equipped with an inductance measure circuit, the current generator also provides the control system with an accurate feed-back signal. COMSOL's non-linear model allows to define the optimized geometry, to compute the dynamic response to the closed-loop control system, and to calculate the circuit inductance. The tests performed on a preliminary prototype, match the design results in terms of power and force.

In this paper an attempt has been made to design and analyze integrated circuit interconnects for unshielded four conductors with three levels system using Finite Element Method (FEM). The computational and simulation work has been carried out with help of COMSOL Multiphysics software. We illustrate that FEM is as accurate and effective for modeling multilayered multiconductor transmission lines in strongly inhomogeneous media. We mainly focus on designing of two electrostatic models of unshielded four interconnected lines with three levels system. We computed the capacitance and inductance matrices for these configurations. Also, we determine the quasi-static spectral for the potential distribution of the integrated circuits.

Modern power transmission systems are in general designed to operate at high voltages in order to reduce resistive losses generated by high currents. This, however, tends to increase the risk for dielectric breakdown or flashovers if the equipment is not properly designed to withstand the stress. The present work illustrates how multiphysics simulations can be used to analyze and predict the electric and thermal stress on a high voltage bushing by solving a set of strongly coupled and nonlinear electric/thermal/fluid equations.

The accurate estimate of values of electromagnetic parameters are essential to determine the final circuit speeds and functionality for designing of high-performance integrated circuits and integrated circuits packaging. In this paper, a new quasi-TEM capacitance and inductance analysis of multiconductor multilayer interconnects is successfully demonstrated using the finite element method (FEM) with COMSOL multiphysics. We specifically illustrate two electrostatic models of open three interconnected lines with two levels system. Indeed, excellent agreement with results from the previous methods is demonstrated.

Railgun is an electrically-powered gun that accelerates a conductive projectile along magnetic metal rails. Various factors increase the projectile velocity. Each method has its own advantages and disadvantages. While increasing the projectile velocity, one has to keep in mind the longevity of the rail guns for practical use . Railguns are often damaged after few uses due to the extreme working conditions,reducing their life span drastically. Some of the problems encountered are Velocity Skin effect, Electro migration and flux leakage. We try and provide solutions to some of these problems. We also formulate a theoretical limitation on the current density in the gun. All these factors when simultaneously addressed would increase the life span of the rail gun.

The National Electrical Safety Code (NESC) requires that high voltage power lines in the U.S. be designed to limit electrostatic effects on nearby equipment. An example is that of a large vehicle underneath a transmission line. The tires insulate the vehicle’s body from ground. If a person standing on the ground makes contact with the vehicle surface, 60 Hz current can pass through the person. The NESC requires that this current be limited to 5 milliamperes. Common methods for analyzing this phenomenon use geometric simplifications and empirical formulas. The authors used COMSOL’s AC/DC module to perform three-dimensional finite element analysis to calculate vehicle short circuit currents to ground and validate the validate the simplified methods.

In this work COMSOL is utilized to obtain the Mason lumped parameter model for a piezoelectric transformer (PT) design. The Mason lumped parameters are relevant in the design process of power converters. The magnitude of the impedance is simulated for a specific interleaved multilayer thickness mode PT. The PT design has been prototyped and the measurements results are compared with simulations. Two methods for simplifying the PT model are given in order to decrease the simulation time. This paper aims to aid electrical engineers with less knowledge within the field of mechanics, to be able to simulate a PT design with COMSOL and extract the key electrical parameters.

In this paper an EMVD (Electro-Mechanical Valve Drive) for combustion engines is redesigned to achieve a fail-safe behavior when power loss occurs. The AC/DC Module and the Moving Mesh interface of COMSOL Multiphysics 4.2 are used to build up a transient model. This model also includes the calculation of eddy currents.

Computer simulation is mandatory for the optimization of electromagnetic devices. Here we concentrate on two classes of devices operating in the MHz and GHz range, namely microwave ovens and TEM cells for electromagnetic compatibility testing. In particular we concentrate on the issue that numerical results are usually different from the experimental ones and this can be due, among others reasons, to a much too simplified numerical model or uncertainties in material parameters. In order to address the first problem, we use very accurate numerical models, including electromagnetic and thermal simulation, and perform sensitivity analyses including possible deviations from the ideal case due to manufacturing tolerances (Figure 1), giving us the possibility to simulate a realistic use of the device. For the second problem, in order to avoid inhomogeneity of the load, we performed thermal measurements on a particular material made by agar (2%) and water (98%): its thermal and dielectric properties are very similar to water, but it has the consistency of a semi-solid gel, this allowing us to use different measurements approaches. Using this load, in fact, we can perform several thermocouples measurements (accurate both in position and in amplitude) and we can combine them with results obtained by an infrared camera in order to have a good mapping of temperature distribution inside different loads (both in volume and in shape). Both numerical and experimental results will be presented in order to validate the numerical models; then we’ll discuss different solutions for the optimization of the actual microwave ovens and TEM cells.

Liquid-crystal elastomers (LCEs) [1] have attracted a great attention in recent years due to their high potential in a wide range of applications, from microfluidics components [2] to artificial muscles [3]. The photo-mechanical response of LCEs is due to their constitutive photo-sensitive molecules, which change shape when absorbing part of the incident light. These microscopic deformations can cause a macroscopic contraction or expansion of the material, depending on the orientation of the molecules, the absorption coefficient of the medium and the light intensity. This phenomenon can be used, for instance, to drive a small actuator with light (see Figure 1). Towards future applications, it is important to develop an ab-initio tool able to couple in an exact way the optical response of the material and its mechanical deformation, in order to gain a deeper understanding of the behavior of LCEs when exposed to a light stimulus. Our work concerns the multi-physics finite-element modeling of the photo-mechanical response of LCEs, using COMSOL Multiphysics. The Radio Frequency package was used to solve the electromagnetic problem of the light scattering and absorption by the object. The resulting material deformation was then evaluated using the Structural Mechanics package by introducing an equation that expresses the strain in the material as a function of the retrieved light intensity. Using this approach, we modeled the macroscopic deformation of a two-dimensional LCE-based cantilever in response to a steady-state plane wave, as a function of the molecular alignment, absorption coefficient and light intensity, and compared our results with a simplified analytical model assuming the Beer-Lambert's law of absorption [4]. A very good agreement was found in the limit of a relatively strong absorption coefficient and/or thick sample, thereby validating our model. On the other hand, we found that when the wave nature of light becomes important, for instance when interferences due to multiple reflections at the interfaces of the medium cannot be neglected, the deformation of the material can deviate strongly from expectations. This illustrates clearly the relevance of our model to treat more realistic cases. In conclusion, by solving exactly the electromagnetic problem, our finite-element model completes the theoretical models known so far on the deformation of LCE-based materials. It can be easily applied to more complex geometries and may find use in a near future in the design of actuators for lab-on-a-chip devices [5] or in the implementation of soft motors [6].

There is urgent need to monitor dental and oral diseases, such as tooth decay, gum diseases, and teeth grinding. Such monitoring can be achieved by embedding sensors in the mouth. This technique faces some difficulties. The first is how the power needed for the operation of the sensors and the associated electronic chips can be generated. This power can be generated using the pressure exerted by the teeth during chewing on a piezoelectric device. The second is where the chip (LTC3108 power management IC) will be placed in the mouth and connected to the sensors without injuring the patient or causing discomfort. This can be solved by using a Hawley retainer [1], shown in Figure 1, since the chip is very small. The third is how the stored data can be retrieved. The paper addresses this issue and lays the framework for a design to provide digital wireless transmission of data for multiple sensors. Models of EM antenna radiation patterns are used along with circuit designs for analog to digital conversion and digital transmission. The size of the antenna is small enough to fit behind the upper row of the teeth. Our COMSOL design shows that data can be transmitted from the mouth without severe attenuation of the signal from the tissue. COMSOL is used to investigate the design of dipole antennas with impedance boundaries designed to represent different types of skin. The wireless transmission of the circuit is designed for a frequency of 5.8 GHz to accommodate a small size antenna that can fit inside the mouth. Skin depth penetrations of high-frequency EM waves are investigated with different types of biological tissues to determine if transmission through lip tissue is possible. The study shows that EM waves at the frequency of 5.8 GHz will penetrate the skin tissue around the lips. Different thicknesses of skin and fatty tissue were tested for EM wave attenuation at ranges from 2600 to 3100 um and 1 to 1.1 cm, respectively. Figure 2, Figure 3, and Figure 4 show that attenuation varies depending on the angle of incidence between the electromagnetic wave and the tissue. These attenuations vary from -3.1 to -7.3 dB normalized at 2600 um of skin to -3.9 to -8.5 dB at 3100 um skin. This range of attenuation was from an incidence angle of zero to 48.7o. The study proves that EM waves at 5.8 GHz can attenuate thin layers of tissue with a strong enough signal to transmit data. Furthermore, the study identifies the optimal angle range for receiving transmission. While this study was intended for determining if a signal can be transmitted through lips, the model can be modified to study penetration depths of signals for other areas on a human body, different biological tissue, or implanted devices.

Cables not only transfer the power
needed to run electrical equipment,
but also the data signals needed to
operate them. To prevent errors and device failures, the same attention must be paid to the choice and installation of the cabling as is paid to the rest of the system.

Electrically large structures such as aircrafts, ships, land vehicles and satellites have demanding and complex electromagnetic environments. CST STUDIO SUITE® brings together 20 years of experience in the simulation of 3D microwave & RF components, antennas and systems ...

AMPL chose NI AWR Design Environment because it is a powerful tool for MMIC design and at the same time reduces design cycle time. It has an intuitive user interface and is extremely user friendly when compared to other EDA software tools. Productivity, ease of use, simulation speed, availability of models, and innovative technologies are all key benefits of the software for AMPL. The most positive feature of NI AWR software cited by AMPL was an improved MMIC design flow that delivered a reduction in simulation time yet better accuracy with simulation results.

This White Paper provides some practical examples of calculating the Advanced Encryption Standard (AES) on 16 and 32-bit versions of eSi-RISC. The basic software implementation is refined using known techniques in the literature, and a novel implementation of Bertoni’s transposed MixColumns() transformation provides the most optimised fully software implementation. The final cycle count on eSi-3250 is shown to be better than ARM7TDMI, ARM9TDMI and LEON-2 embedded processor benchmarks and the code density is superior. Finally the white paper looks at how the user-defined instruction extensions can provide additional saving in power, memory and computation cycles.

This test case based upon a case-study MEMS accelerometer demonstrates the power of Modelbased methodology for MEMS sizing and performance optimization. Use of InfiniScale LYSIS tool set alongside with customer reference tools (3D EM simulation) is the only way to create an accurate enough, multi-dimensional behavioral model of the accelerometer.

Selective encryption is a new trend in content protection. It aims at reducing the amount of data to encrypt while achieving a sufficient and inexpensive security. This approach is particularly desirable in constrained communication (real time networking with delay constraints, mobile
communication with limited computational power...). In this paper we introduce selective encryption from information theory point of view.

The test system is capable of carrying out
manual and automated tests of standard
software modules. As these are standardized
software elements that are parameterized in
specific applications at a later stage, the test
environment has to fulfil high demands on
flexibility.

A widespread "truth" among developers of embedded software is that using C++ results in inferior code size and speed compared with using C. This article will attempt to sort out the facts from the fiction in this statement. By better understanding the underlying mechanisms of the language, a designer can avoid code bloat.
In this paper, we will discuss various C++ language features, compare them with C, describe their implications for the ARM code generation, and look at the efficiency of the different ARM architectures

Chemotherapy can be a very effective treatment for many types of cancers. However, the cell
membrane that surrounds each cancer cell makes it difficult for some chemotherapeutic agents to
penetrate inside and cause cell death. In addition, physicians infuse these agents throughout the body
in high concentrations. Unfortunately, this system-wide application often has serious side effects,
killing healthy as well as cancerous cells, while also causing nausea, hair loss, weakness and other
symptoms.

Global competition and ever-evolving business models make component re-use and standardization key imperatives for High-Tech companies to remain competitive. This includes High-Tech OEMs (consumer electronics, communications, and specialized electronics) as well as the critical Electronic Manufacturing Services (EMS) providers who must manufacture and deliver the final product. Critical to product innovation is managing an integrated part development process from design to procurement and driving a strategic sourcing strategy that ensures component compliancy and enables “Design Anywhere, Manufacture Anywhere (DAMA).” These initiatives deliver both agility and savings when successfully executed.

This video introduces the operating concepts of PDXpert software. Details may vary slightly from one release to the next. A step-by-step procedure for evaluating the current PDXpert release is available in the PDXpert Evaluation Guide and the related slideshow tutorial.

Vanguard Managed Solutions (VanguardMS) has been designing, developing, and deploying innovative and cost-effective networking solutions for over 40 years. During that period VanguardMS has established an enviable track record by focusing on “time-to-market” as the most critical element in successfully delivering complete managed-network solutions to meet the needs of its hundreds of customers around the world. In recent years VanguardMS has relied on Corelis’ ScanExpress Boundary-Scan test systems to shorten its development cycles and bring new products to market sooner by improving the productivity of its engineers in the development and debugging of prototype units.

Spectral Systems, Inc. (SSI) is a leading-edge aerospace engineering and product development company located in southwestern Ohio, the birthplace of manned flight. SSI was founded in 1995 and has grown very rapidly from an engineering service provider to a developer and integrator of advanced Intelligence, Surveillance and Reconnaissance (ISR) and Electronic Warfare (EW) systems, sensors and embedded processors.

A leading component provider of human interface solutions wanted to develop an ultra low power IC. The battery operated product was designed as a replacement for an earlier passive device to reduce cost and complexity. Customer had made a prototype using discrete ICs for proof of concept for performance however power consumption of the ASIC was the key challenge. Finding a silicon partner was a challenge for the customer as several vendors did not deem the power budget as practically achievable.

In the world of IT, managing desktop churn is a fact of life. After last decade’s flurry of corporate reorgs, you’re supporting more applications than ever before—sometimes 20+ per desktop. You’re also managing more vendor contracts as a result.

Packaging has always significantly impacted on microwave IC and amplifier performance. In most cases, the inherent parasitic capacitance and inductance of the package lead frame and wire bonds set a limit to circuit performance. Avago Technologies developed a bonded-wafer-to-wafer package technology in 2004 and now offers innovative microwave gallium arsenide (GaAs) VMMK devices based on the proprietary WaferCAP™ chip scale package. Surfacemount (SMT), very low cost VMMK amplifier and FET devices are available today and soon to be released diodes and detectors will be added to the VMMK series.

The evolution of functional verification has been exceptional over the last 10 years including the introduction of SystemVerilog, reusable testbench methodologies such as VMM and OVM, and raw simulator and formal tool capacity, performance, and debug capabilities.

Today, process technology has advanced to 32nm, resulting in an increase in the number of transistors per unit area and a reduction in package size. At the same time, system designers are trying their best to reduce the system size by increasing the component density on boards, adding as many features in the design as possible to deliver the industries’ best products in terms of space and size. Increased transistor density inside the chip, higher operating speeds, and increased component density on board in modern electronic systems has led to relatively more heat being generated in these systems. All this has made thermal management an integral and critical part of system management in all application domains, including automotive, industrial control, consumer electronics, battery powered systems, and so on. Many systems are equipped with cooling fans to deal with the heat generated. This has led designers to realize the need to come up with cost-effective, reliable, noise-free, and power efficient temperature-based closed loop fan control systems.

Over the past couple of decades, more and more applications are going digital. Implementation of digital systems is very simple as it is entirely about logic; however, complexity increases exponentially with signal speed, specifically clock synchronization, setup and hold time, jitter, and so on. These problems affect the functionality of not only the individual subsystem but also cause electromagnetic interference (EMI) when high frequency devices are operating in close proximity. Figure 1 shows a typical example of EMI caused by a DVD player on TV reception.

Undoubtedly, color plays a significant part in our perception of the world around us. We have often experienced situations
where the same object appears differently when illuminated with different light sources, giving the impression that the color of
an object is also tied to the light source used. This property of the illuminating light source can be quantized as CRI [Color
Rendering Index]. The CRI defines how accurately a sample light source reproduces an illuminated object’s color in
comparison to a reference light source of comparable color temperature. Figure 1 shows an example where the same object
appears differently when illuminated with light sources of different CRI.

The Photonic Element Library is specifically designed to provide the photonic industry with a complete backend solution for designing photonic devices. It employs the unique features of dw-2000™, such as our allangle, GDSII native, hierarchical database, and includes a library of parametric optical elements. These photonic elements enable designers to quickly go from simulation to ready-to-manufacture layouts.

With development costs for ASICs shooting up, prototyping with FPGAs is attractive alternative. This reduces the chance of ASIC re-spins and saves huge money. This platform was developed for ASIC validation and has two high end Vertex 5 FPGAs and 12 connectors each with 500 pins for board stack -up.

Another DAC is fast approaching and the organizing committee had the task to pull another rabbit from the proverbial top hat in order to lure attendees to San Diego. Hotel prices certainly did not do the trick. It seems that in San Diego the hotel managers have not heard about the recession, or may be they have and figured on DAC attendees to provide needed profits. Either way, room prices, given that DAC has negotiated a block of rooms, are over twice what I will pay at a good hotel with convenient public transportation to the convention center.

The folks at EVE, specialists in hardware/software co-verification, today began shipping four new vertical solutions, further expanding their ZeBu hardware-assisted verification family into computer/peripherals, embedded processors, networking, and video markets.

We review our latest developments in the field of Raman thermography and its application to GaN microelectronics. Device self-heating, the temperature rise in a device generated by electrical power dissipation, plays an important role for device performance and reliability, however, is difficult to assess as it occurs on sub-micrometer length scales in most devices, not observable using traditional thermography techniques.

Wind energy, solar electricity, electro mobility … these catchwords are met continually and
never before had such a global importance as today. In addition to all the advantages and
safety that were enabled by these development tendencies, they put high demands to the development of required electronic components.

lation engineers to customise individual sensors quickly. Costly DIP switches and LEDs
are clearly no longer suitable to accommodate
all possible requirements, especially with competitive pricing in mind. Storage requirements for all audio possibilities also mean it is simply not cost effective to store all messages all of the time.

: Accurate results are easily obtained after generating a WiFi antenna using the sketching tools in Remcom’s XFdtd Release 7. However, when the antenna design is placed in the realistic operating environment of a netbook computer, it must be tuned for optimal performance.

As bandwidth requirements for applications such as wireless, wireline and medical/imaging processing continue to grow designers depend on the toolsets necessary to provide them with the real-time signal processing capabilities that are needed.

The Digital Structured ASIC is dead. LSI has pulled the plug. Synplicity is winding down their entire structured ASIC line. Articles appear, almost daily, waxing nostalgic about the rise and fall of an industry. Yet, there is a new approach to using a structured (or platform, or array) approach to ASIC design. Mixed signal via-configured arrays.

A major mutual insurer initiated an extensive business transformation project, replacing its policy administration and billing systems. The project exposed a need for a testing process and servicing
strategy beyond the Insurer's internal capabilities.

The RISC architecture brings many advantages to the microcontroller space including the fact that compared to CISC
architectures it is much friendlier to compilers and very economical in silicon area. For silicon designers and their target customers, this translates to high performance at low cost.

This whitepaper explains how Test Automation tools can be used with C++ to support Test Driven Development (TDD) in an Agile-programming environment. This paper assumes some basic familiarity with Test Automation products.

The following video presents the ways in which you can identify specification inconsistencies, also known as conflicts, in your ASD:Suite Model and ways how to fix the conflicts, if found. Press the Play button to see how to check for conflicts and how to fix them using the ASD:Suite:

TLP Innovations produces the software product Train Load Predictor. The software began as an in-house solution created by Systemwide. TLP Innovations spun off from Systemwide in 2008 to further develop Train Load Protector, which is now a commercialized, feature-rich product that can do a full passenger impact analysis for a timetable, including passenger loads, service intervals and interchanging statistics.

With the current rise in oil prices, along with the growing costs associated with oil and gas exploration and production, E&P companies are depending more than ever before on advanced computer simulations and computer modeling to make better predictions and get more oil out every well drilled. Countless IT resources are consumed in order for businesses to remain competitive.

The ampacity of a cable depends on the cross section of its conductor. When selecting a cable design for a specific application it is of interest to choose the lowest possible conductor cross section in order to reduce material costs. Therefore an exact calculation of the ampacity is necessary (it is usually limited by the thermal resistance of the insulating cable materials). Commonly the ampacity is determined using semi-empirical methods to evaluate the maximum temperatures. These methods include safety margins that may result in low ampacity values. In this study COMSOL Multiphysics is used to determine temperature conditions in a high voltage cable connecting off shore wind platforms. It is shown that the conventional analytical methods don’t apply to the given conditions and the simulation is able to demonstrate alternative methods to determine the ampacity.

For the design of an inductive power and data transfer electromagnetic calculation are carried out. A transfer system is considered for loads that are distributed across some distances. For example, such loads are adjustable speed drives that are found in factory automation and intra-logistic. Physical properties of the inductive transfer are modeled via COMSOL. Lumped parameters are deduced from magneto static and quasi static calculations. Selected operating conditions are investigated with combined field and network calculations. Field calculations are 2D and 3D and they are carried out for stationary and in the frequency domain. Also heating is modeled at a basic level. Results are compared to experiments that are carried out at a purpose built test stand

Flexible electronics are temporarily affixed to a rigid carrier such as glass or silicon prior to device fabrication to facilitate robotic handling of the device, but also to allow optical lithography to stay within overlay design registration budget; without the rigid carrier, a freestanding flexible substrate such as polyimide would distort unacceptably during even minor temperature excursions due to its high coefficient of thermal expansion. Post fabrication the device must be released from its temporary carrier. Others have used UV-release of a temporary adhesive (bond-debond) [1], solvent release [2], backside laser ablation [3], backside sacrificial grinding, backside wet chemical [4,5] and plasma etching [4], mechanical separation [2], and thermal release [2] to affect this release. Each release technique possesses one or more significant disadvantages, including added cost, added processing time, limited throughput, added processing steps, and increased opportunity to introduce defects to a nearly finished device.

Electromagnetic wave analysis of waveguide has been done in this paper with the help of Finite Element Method (FEM) based COMSOL Multiphysics. The design is further extended by placing conductor on a dielectric slab included in the waveguide to form a shielded microstrip transmission line. The simulated models are analyzed to determine the wave propagation characteristics. The validation is done by evaluating the critical frequency, propagation constant and transversal field distribution of modes at given phase constant β and angular frequency ω.

Transmission-line transducers are used for the measurement of absorption and reflection of different materials, such as: liquids, granular medium, and ground. A simplified methodology for calculation of scattering parameters of such transducers is presented. The transducer cell is partitioned at each interface and the partial scattering equations are calculated, considering two interfaces at a time. Next, standard techniques are applied to solve the signal-flow diagrams to obtain the full scattering equations. The proposed methodology has been applied to a coaxial transducer cell filled with different low-loss liquids. The results have been confirmed with computer simulations and experimental measurements. Measurements and simulations were carried out in the 300 kHz to 3 GHz frequency range.

HIIPER is an experimental space propulsion device using a helicon and an IEC as a plasma generation and acceleration stage, respectively. There is an experiment in progress, but for true rapid iteration and to model the performance of the engine, COMSOL is a strong candidate for fulfilling these roles and continuing with the project until its production phase.
The simulation is built with very simple forms of each device and as the simulations succeed, additional complexity and detail is added until the full design is achieved. Each device is simulated separately with the goal of using the exit interface of the helicon as the entry interface of the IEC. The primary tools used are the AC/DC, DC Plasma, and Particle Tracking packages.

A wireless passive pressure sensor and the measurement system were design and simulated using COMSOL 4.3. The sensor is based on MEMS capacitor attached to a planar inductor for wireless powering and readout. An external coil is used for the measuring system. The pressure to be measured compresses the MEMS capacitor and changes sensor's resonance frequency. COMSOL 4.3 was used for the analysis of the two physics interactions. The Electromagnetic Waves module was used to simulate the antenna response and the effect of a coupled sensor in the frequency domain. Solid Mechanics module was used for the simulation of the compression of the sensor caused by an external pressure. Data obtained from the fabricated sensor were consistent with the simulation results.

Energy storage is an essential component for hybrid power system using non-conventional energy resources. Batteries, compressed air energy storage, pumped hydro plants etc. have been developed for storage. However, these have demerits like losses involved in energy conversion and time delay. Superconducting Magnetic Energy Storage (SMES) can be a good alternative as it stores electrical energy in the form of magnetic energy involving no loss during supplying the same. Solenoidal or toroidal low temperature superconducting coils (LTS) are in use for SMES [1]. First and second generation high temperature superconducting (HTS) coils are in operation either independently or with LTS coils in hybrid mode [2,3]. Such a hybrid coil made of BSCCO – 2212 (inner coil) and Nb-Ti (outer coil) was designed [3]. Thermal runaway and excitation tests of the prototype made of the same coil were performed [4,5]. In this work, the 3-dimensional magnetic field distribution of this hybrid coil is simulated using COMSOL Multiphysics. 3D Magnetic Fields section of the AC/DC module is considered for geometry (Figure 1). Preset Studies>Stationary option is selected for DC operation.

Wind energy is one of the fastest growing renewable energy sources for electricity generation over the past decade. The offshore installation of large-scale wind farms draws huge attention because of better wind profile. Direct drive synchronous wind turbine generators are now a global demand for light weight, compact, large scale wind turbine generators. Among various approaches in designing direct drive superconducting wind turbine generators, a comparatively new design (Figure 1) having both axial and radial air gaps between stator and superconducting rotor winding is selected for simulation work. It has the advantages of uniform stress and magnetic force around the circular coil. Elimination of gear box leads to light weight of the wind turbine generator. This paper deals with the simulation of magnetic flux distribution of stator and rotor coil of the same using the sliding mesh tool of COMSOL Multiphysics.

Induction furnaces are employed for vacuum distillation process to recover heavy metals after electro-refining operation. Induction furnace of suitable heating rate and cooled by passive means are required to be developed for this purpose. It is planned to set up a mock up induction furnace which will simulate the conditions to be realized in actual vacuum distillation furnace for this purpose. The mock-up facility will be used to demonstrate melting of 10 kg of copper in a graphite crucible and heated by induction furnace in a vacuum environment. The coil configuration and electrical parameters of the furnace are to be finalized to attain a temperature of about 1500 degC in 2 hours for the charge. Figure1 shows the schematic layout of the mock-up facility used. The furnace liner enclosing the crucible, essentially coupled with the magnetic field generated by coil, gets heated up and indirectly heats the crucible by radiation heat transfer. The melting of copper takes place in crucible. The copper liner prevents the coupling of stainless steel vessel with magnetic flux lines. The carbon felt insulation is used to prevent the heat loss to the coil and other parts. The stainless steel vessel encloses all the above parts. Thermal analysis of the mockup facility is being carried out using COMSOL Multiphysics code to optimize the various electrical parameters. First the Induction Heating Interface under the Heat Transfer Module of COMSOL Multiphysics was modeled and validated with the experimental data reported in the literature. The validated model was then used for 2D-axisymmetric transient thermal analysis of the mock-up facility. The heat transfer and electromagnetic characteristics have been investigated. The temperature distribution is shown in figure 2. The effect of various operating parameters, geometrical factors and material parameters has also been carried out. This paper details the thermal and electromagnetic modeling of the induction furnace and discusses the results obtained.

We study the topography influence of levees on the electric resistivity signal obtained with the Radio-Magnetotelluric method. Field measurements have been modeled with COMSOL, using the AC/DC and RF Modules. A levee situated in Orléans along the Loire river (France) has been considered in order to design a model tacking account of the skin depth and the incident wavelength, keeping a constant field in the whole model. The effect of the incident electromagnetic field direction is assessed with two different incident wave directions: BBC 5 and France-Inter. The simulations highlight the tri-dimensional effects in the apparent resistivity, observed on the crest of the levee, depending on the incident field direction and topography. A buried gas pipe is also characterized.

The well known Pierce design of electron and ion diodes is the base of particle source extraction systems [1,2]. It was heavily studied up to 1960 with analog computing and it now offers us a known case against which to compare the precision of fluid and particle tracing codes. The ideal model assumes zero particle kinetic energy at cathode emission, which is well matched in many sources: the extraction voltage is typically 20 kV, the emitter or plasma temperature below 0.5 eV, to which (in the case of plasma) we can add a small speed perpendicular to plasma surface equivalent to a kinetic energy of about 2 eV. Anyway, in the discretization of ideal model, we have to introduce a thin strip between the ideal cathode position where the ruling nonlinear Partial Differential Equation (nPDE) is singular and the simulated cathode position. In the construction of the COMSOL Multiphysics representation of the fluid model we can input not only the precise geometrical information on electrode size, but also the correctly defined mesh size and starting kinetic energy (all this information must be consistent). The expected and calculated exit radius of test particles agrees better than 4 digit precision (5 digits for most particles). The effect of small perturbations due to non uniform cathode emission current, of practical interest in many ion sources, can be so compared with a validated tool, which is important, since we know that this effect is small. The effect of the small emitter temperature is discussed with particle tracing models. Finally, the effect of anode lens aperture is computed (and compared to calculation), trying to determine aberrations due to finite aperture radius.

Continental – a global manufacturer of premium automotive multimedia systems for the OEM market – has applied state-of-the-art electromagnetic simulation techniques
in the design of its latest car radio and
multimedia systems (Figure 1), helping
it to maintain its reputation for high
quality, robust products.

In this paper a modular approach using the so-called System Assembly and Modeling (SAM) of CST STUDIO SUITE® is used to optimize a reflector antenna system in a piecewise manner. The results are compared to a full system simulation. It is shown that a similar accuracy to that of the full system simulation can be attained with the modular approach with a much shorter simulation time and using less computational resources.

The presence of multiple communication antennas on a tower means that antennas may have to be installed in sub-optimal positions. Electromagnetic simulation can be used to design the antennas themselves, and also to optimise the positioning of the antennas on the tower. This article will describe how multiple solvers in CST MICROWAVE STUDIO® can be combined to predict where to install an omnidirectional stacked bicone antenna array to minimise loss of omnidirectionality.

CST STUDIO SUITE includes various solver modules that are ideally suited to the analysis of static and low frequency devices. CST EM STUDIO®(CST EMS) is dedicated to full 3D EM simulation in a wide application range, including sensors, circuit breakers, magnets and coils.

As System-on-Chip (SoC) designs grow more complex they demand a higher-level of abstraction to functionally verify all modes of operation. The main focus of Accelera’s SCE-MI Co-Emulation Modeling Interface is to avoid communication bottlenecks when interfacing software models to current hardware emulation platforms during SoC verification. This allows the system to be modeled realizing its full performance potential. In this white paper, we will be discussing the Macro-based SCE-MI interface which utilizes synthesizable RTL macros which provide connection points between transactors and SCE-MI infrastructure.

Test Equipment Plus, Inc. provides service and support for the used test and measurement equipment market. They also design, manufacture and sell the Signal Hound® line of portable spectrum analyzers. The first prototypes of the analyzers were in need of a spectral filtering solution to be competitive in the market. This case study describes how Test Equipment Plus utilized the CST MICROWAVE STUDIO® electromagnetic simulation tool to design custom filter solutions through virtual prototyping.

In the world of electromagnetic and electromechanical design, state-of-the-art Finite Element simulation is critical to the virtual testing of new concepts and optimization of existing designs. CST EM STUDIO® is a specialist tool for the static and low frequency simulation, design and analysis of electromagnetic devices.

CST STUDIO SUITE® is a package of tools for designing, simulating and optimizing
electromagnetic systems, and is used in leading technology and engineering companies
around the world. The three pillars of CST’s products are accuracy, speed and usability.

Ajax Compilers (www.ajaxcompilers.com) is a privately funded startup company incorporated in January 2012 in Athens, Greece. The company focuses on the development of electronic design automation (EDA) tools for ASIC and FPGA SoCs, intellectual property (IP) blocks, compilers and code optimization tools. Products developed by AJAX Compilers include a compiler frontend generator, source-to-source code optimizers and intermediate-level profilers, a high-level synthesis environment and an ASIP (Application-Specific Instruction-set Processor) generation prototype.

This application note provides some practical examples of calculating a cyclic redundancy check
(CRC) on 16 and 32-bit versions of eSi-RISC, and looks at how the user-defined instruction
extensions can provide a saving in power, computation cycles and reclaiming memory space.

While High Voltage interfaces are broadly used in many IC applications like motor control, power management and conversion, LCD panel drivers and automotive systems, many IC designers still lack a low leakage, cost effective
and latch-up immune ESD protection clamp.
This white paper introduces a newly developed protection device and compares it with the traditional approaches, based on measurements on TSMC 0.35um 15V and TSMC 0.25um 40V technology. Within an area of 35.000um², the novel hebistor device with holding voltage above 40V
achieves more than 4kV HBM, 200V MM while the leakage and capacitance stay well below typical requirements (<10nA and <250fF).
Hebistor devices form a family of high voltage ESD/EOS/IEC protection clamps which are branded under the Sofics PowerQubic portfolio.

Micro-electromechanical systems (MEMS) represent a highly cost-effective way of building tiny sensors and actuators. But a major problem with MEMS devices is that they need to be hermetically sealed: a level of protection much higher than that generally used for integrated-circuit packaging. As they can measure as little as 1mm on a side, handling MEMS devices is extremely difficult and the use of conventional packaging techniques can damage the delicate MEMS structures. The alternative is to perform packaging at the wafer level.

From airports to refineries, power plants to water treatment facilities, the engineering and architectural firm Burns & McDonnell delivers planning, design and construction expertise to make clients successful. Founded in 1898, the 100% employee-owned firm has more than 2,900 engineers, architects, construction experts, planners, estimators, economists, technicians and scientists representing virtually all design disciplines.

Embedded systems often (e.g. in automobiles) are widely networked and run distributed applications on multiple microcontrollers. More and more the interconnected nodes are developed by different suppliers. Even for a single device multiple, separated development
groups provide basic software, drivers, communication stacks or application. This common, but not simple development setup inevitably needs collaboration support.

When migrating to a new CAD tool one of the primary concerns is to save important data in existing
designs and libraries. Sometimes it is desirable to translate existing libraries since time and effort have
been invested in creating them and you want to avoid having to repeat that development in a new tool.
Most legacy designs are typically maintained in their respective CAD tools and new designs going forward
are designed in the new tool set. This is primarily due to complexities and compatibility of the data coming
from one tool to another. No translation is completely perfect and some tools are more compatible than
others.

When migrating to a new CAD tool one of the primary concerns is to save important data in existing
designs and libraries. Sometimes it is desirable to translate existing libraries since time and effort have
been invested in creating them and you want to avoid having to repeat that development in a new tool.
Most legacy designs are typically maintained in their respective CAD tools and new designs going forward
are designed in the new tool set. This is primarily due to complexities and compatibility of the data coming
from one tool to another. No translation is completely perfect and some tools are more compatible than
others.

Developers are using real-time analysis tools in the development stage, to debug real-time events either not observable during “run-stop” debug sessions, or limited by the requirements of the application; such as inherently not freezable systems like engine control or pace makers. Furthermore, engineers are using real-time analysis tools in their final development stage to do performance tuning and coverage or in the test stage for HIL (hardware-in-the-loop) testing and white box testing. A typical requirement is that the real-time analysis tool must not disturb the real-time behaviour of the system.

Exhaustive testing to detect software errors constantly demands more time within
development cycles. Software errors with catastrophic consequences have often
pushed forward innovations in software analysis and testing. For example after the
explosion of Ariane 5 the code analysis tool PolySpace was introduced which could
have detected the fault in advance.

This paper details how to create useful timing and flow diagrams
so they may be utilized to document a design’s functionality and
identify the assertions and cover statements necessary for full
functional coverage with the CoverAll™ toolset.

In this whitepaper John Alpine, Spatial VP of R&D, examines the evolution of software development productivity, the point at which ideal productivity is achieved, and what the two major shifts in software productivity will be.

Linear motion electromagnetic actuators exploiting the Lorentz force are often used in applications requiring high bandwidth motion. A “loud speaker” or “voice-coil” actuator, as shown in Figure 1, is an example of such a device. Early computer hard disk drives used such Lorentz force linear motion actuators to move the magnetic recording heads radially over the spinning disks.

This paper reviews features of solenoid lenses to focus high-current electron beams. It also discusses how to characterize spherical aberration with a numerical orbit code and how to employ scaling methods to organize simulations for maximum generality.

In this article we discuss different types of electric motors for precise motion control (stepper motors, microstepper motors, servo motors) and the impact of the selected type of motor on a motion control system.

PCB layout plays a core role in the manufacturing of a printed circuit board. The layout process produces a graphical representation of the circuitry that is necessary to manufacture a PCB. PCB design is a detailed description and graphical representation of the circuit.

Today, you are faced with a large number of problems that have to be solved when creating storage platforms. In the past, you
selected a CPU performance point, added some memory and a SCSI controller to connect to your disk drives and you were good to go. About the only choice on the I/O side was whether to go with single- or dual- channel SCSI.

Of the issues facing hardware and software engineers in designing embedded applications, processor performance and total system development cost rank highest. With multimedia, networking devices and other system-on-chip products increasing in functionality and complexity, the ability to wring the most out of a processor is, perhaps, a more pragmatic measure of its value than clock speed.

An important use case for modeling of hardware IPs is to use the models to create Virtual Platforms. In a Virtual Platform, models of different IPs are stitched together, to be used to simulate the functionality of entire SoC (rather than mere components of a larger system). Different IPs have varied interface requirements, therefore connecting software models together can become a time consuming and error prone task, especially if the individual models use nonstandard interfaces.

Information Systems Specialist Chris O’Grady is a member of the development team for the Reconfigurable Cluster Element (RCE) initiative, headed by Mike Huffer, at the SLAC National Accelerator Laboratory at the University of Stanford. The RCE is cutting-edge technology which provides electronic data storage for extremely fast detectors. In fact, the detectors that the RCE reads out are so fast they can transmit snapshots at roughly 100 femtoseconds (a femtosecond is 10-15 or one quadrillionth of a second).

Since its introduction, static source code analysis has had a mixed reputation with development teams due to long analysis times, excessive noise or an unacceptable rate of false-positive results. Excessive false-positive results are the main reason why many source code analysis products quickly become shelfware after a few uses. Despite early shortcomings, the promise of static analysis remained of interest to developers because the technology offers the ability to find bugs before software is run, improving code quality and dramatically accelerating the availability of new applications. Though static analysis has historically struggled to deliver on this promise, a groundbreaking
new use of Boolean satisfiability (SAT) in the field is poised to help static analysis deliver on its potential.

The growing complexity of ASICs and programmable parts means functional verification is the nightmare that keeps projects managers up at night. Designers are creating ASICs that can't be completely verified in a reasonable time with the talent and computing resources they have available. As a result of the gap between what can be designed and what can be verified, achieving a functionally stable design is difficult and involves many iterations. This paper presents Solidification, a new low-risk methodology for faster debug of ASICs and programmable parts that significantly reduces verification time and effort while increasing quality and robustness of designs.

Reset schemes can be difficult to verify in logic simulation because of the non-determinism caused by unknowns (Xs) in the registers and their inaccurate handling in logic simulation which can mask bugs and
potentially lead to failures in silicon. Here, we describe a precise formal approach to X-verification of partial and full reset sequences. Insight, from Avery, addresses two kinds of X issues:

Capacitive sensing is emerging as a popular interfacing alternative to switches and knobs in consumer electronics, front panel display applications, and many industrial and automotive sensors. This article describes different kinds of noise impacting any capacitive sensing technology and the methods that can be implemented to overcome different kinds of noise under varied environmental conditions.

Touchscreen technology has existed for quite a while. Why did it take the iPhone to set the mobile world on fire for touchscreens? The key is in technology inflections. With the market shift from resistive to capacitive touchscreens, the invention of “gesture” motions, and the crystal clear, solid feel of glass screens, touchscreens have once again caught the attention of the worldwide electronics buyer.

Re-programmable microcontrollers are transforming the nature of embedded applications. Embedded applications in many industrial, automotive, and medical applications implement sensors that require calibration during manufacture to store offset,
compensation slope or other configuration data. These systems often have used potentiometers or Serial EEPROM devices to set up and store this calibration information.

The motivation behind the XDRC is to supply designers with a physical verification tool that can verify the design rules of the most advanced technologies. The XDRC surpasses dw-2000's DRC with improved performance, increased capacity, an expanded set of unique rules and provides designers with the flexibility
to combine them into complex scripts. Design Workshop Technologies’ dw-2000 software has become the ultimate tool for designing Optoelectronic, Analog, Mixed Signal and Photonic devices.

dw-2000 HLVS is the gateway to advanced features such as electrical layout extraction and network comparison. As is true with all dw-2000 modules, HLE and LVS are well-integrated with the dw-2000 programming environment (GPE) and easily customized to address a wide variety of problems.With these modules, you can easily implement extraction rules for any technology or application.

Dexcel had designed a product custom made for its customers to ease the Monitoring process for Radar Control and Monitoring System. This system uses all the data from various modules and control the TURN-ON Sequence of a Radar Transmitter. It also keeps on monitoring and scanning all the critical parameters of a transmitter and display the same with help of graphical user interface application on customer PC.

In a previous failure analysis project of a customer’s telecommunications product, DfR Solutions had identified Electrostatic
Discharge (ESD) damage to several different GaAs integrated circuits. In addition, DfR determined that these parts had ESD
sensitivity as low as 100V, which placed the components under the most sensitive ESD Component Sensitivity Classification
of Class 0 (<250 volts).

Now that 3G networks are available in China, innovative 3G commercial applications have become a
major means of increasing profitability. To support diverse applications and devices and interconnect
them, a 3G application delivery system is required that also provides a user-friendly experience and an
increased level of personalization through an Interactive Voice and Video Response (IVVR) interface.

This white paper discusses how the IP Multimedia Subsystem (IMS) network can be used to convert video content so that it is accessible to any user, and how network-based processing techniques could be applied to a wide variety of applications.

This white paper provides an introduction to HD Voice and discusses its current adoption rate and future potential. It also describes research trials and implementation issues, and sets HD Voice in its industry context.

Customers worldwide want to do more and more with their wireless devices. They want multiple functionalities packed into a single mobile device. They want even the most basic handsets to incorporate functionality that could not have been achieved in anything but the most expensive handsets only a few years ago.

A database is an ideal medium for collecting and analyzing coverage. At Oracle, we marry our Oracle database with coverage collection of our verification, and then use SQL to extract coverage metrics on-demand. This presentation outlines an intuitive scheme for database collection of coverage, and presents data showing the scalability and the high bandwidth this scheme is able to handle.

The significant burden of parasitics on the performance of post-layout verification forces design engineers to use additional techniques in order to match the requirements of next generation designs. A real gap appears between layout extraction and circuit simulation when adding layout parasitics into the flow. A review of the existing techniques as well as a merciless way to doubtlessly validate netlist reduction and circuit extraction
are presented in this paper.

Carpetright selected Fujitsu’s IMAC (Install, Move and Change) and break/fix services. IMAC ensures the hardware with its preconfigured POS software solution is delivered and installed correctly. As part of the on-going support, Fujitsu’s break/fix services guarantee a four-hour resolution to critical failures and deliver next-day response to less critical issues.

The LIN bus was standardized in the late 1990s, and has been in widespread use in the automotive industry since. The reason for its introduction was the necessity to increase the communication capability that pushed the envelope of CAN networks because of high numbers of ECUs and data volume in vehicles. From an economic point of view the challenge was to develop a cheaper alternative to the relatively complex CAN interface.

When talking about Automotive Test, usually a functional test of electronic devices (ECUs or electronic control units) in vehicles is the reference. In the process, the test system stimulates environmental states under which an ECU executes its assigned functions. The better and more complete an Automotive Tester is able to simulate the ECU’s original environment, the vehicle and its possible operation modes, the higher the quality of the functional test.

The Automated Optical Inspection (AOI) market has been on the move for a while. Well-known and long-term successful companies recently stopped their development and production of their AOI or AXI systems, others have decreased investments and laid off employees, and still others broke new grounds and opened competence centres and support offices.

In this letter, a dual-band parasitic radiator is designed and optimized to modify the current distribution on the
ground plane of a handheld terminal. Using a variable-length dual-band parasitic radiator, the ground current distribution is
controlled, and low speciﬁc absorption rate (SAR) and high radiation efﬁciency at 900 and 1880 MHz are obtained. The proposed
antenna scheme consisting of a dual-band parasitic element and a driven dual-band antenna reduces the peak SAR by 50% and 40% at 900 and 1880 MHz, respectively, compared to a conventional
dual-band antenna. Signiﬁcant increase in radiation efﬁciency is also obtained.

In previous work, we have demonstrated the utility of a feedback loop for enabling optimized transmit pulse shaping
in radar target recognition. This previous work was based on low-fidelity target models, but in this paper, we demonstrate the closed-loop, adaptive-waveform approach applied to highfidelity target model signatures generated by commercial electromagnetic FDTD software. We also incorporate the radar
equation into our models for us in the waveform design procedure. Because SNR varies with range, so do our optimized waveforms for target recognition. Constant-modulus waveform
constraints are enforced, and a template-based classification strategy is used.

Driven by the demands of the consumer electronics marketplace shrinking design cycles – programmable logic and reconfigurable silicon solutions are rapidly gaining acceptance by chip designers for a wide range of product developm development on a completed hardware platform and to reconfigure logic on a chip to handle different computational requirements are just two of the reasons designers are using their products.

This application note describes how to use shared memory for hardware-software
communications on the Altera Nios II platform. The example presented in this application note is a simple image filter that performs an edge-detection function. You can modify this example as needed to create other, more complex image filters or other similar functions.

USB 3.0 is rapidly being adopted by a growing number of system level companies, spawning many integrated device manufacturers (IDMs) to develop new chips to address this need. USB 3.0 supports data transfer rates up to 4.2 Gbits/sec, creating new challenges for IC package designers and signal integrity engineers that must be addressed as part of the high-speed SERDES design process. These higher data rates will require substantially improved modeling accuracy of the IC package’s interconnect, wire bonds, vias, and solder balls that are part of such high-speed data paths.

This paper presents a new approach dedicated to the compact modeling of organic transistors. Usual approach based
on silicon device experiences is to develop a compact model based on strong physical assumptions. In the frame of organic
electronics, this approach suffers from two main disadvantages, which are the time needed to develop a physical model and the fact that materials and device architectures are still submitted to many changes.

IC Design is driven by two simultaneous trends: miniaturization of microelectronics technology, and telecommunication market expansion . When considered at a user
level, these trends seem to be compatible: by making devices smaller, integration of a larger number of functionalities in your
smart phone is made possible and thus boosts the development of the telecom market.

This paper addresses analog/RF IC verification. We present significant improvements for statistical analysis at a very early stage in the design phase. First a new IC performances black-box modelling approach is presented, and then
illustrated with application on different 65nm IP designs and validated with comparison of mathematical models to spice simulations. Finally, a model-based statistical analysis is presented.

For more than 20 years Germany’s largest helium cooling system operated reliably with a traditional centralized process control system. Rising maintenance costs for this aging system lead to the decision to modernize the system with a process control concept that relies on a decentralized I/O system over PROFIBUS and on a high-availability concept based on system redundancy. Softing’s enhanced PROFIBUS protocol software provided the foundation for achieving the redundancy concept with PROFIBUS by guaranteeing an instantaneous and bump-less switchover of all connected I/O devices

For many products designed with today’s
high-performance integrated circuits, BGA
socketing systems are an essential option
during the design, testing, and/or production
phases of a new product development
process.

One of the modern world’s driving engines is the semiconductor also referred to as the IC (Integrated Circuits). These ICs are
fabricated, assembled and tested in billions of units every year. The semiconductor industry is being driven by the mantra “small, fast
and cheap”.

As multi-core SoCs continue to evolve, their interconnect architectures have become the major design challenge. Implementing Quality of Service (QoS) in order to share access to tightly-coupled memories; coordinating error detection and handle protocols; debugging data flow for concurrent processors; as well as fundamental challenges such as SoC timing closure are all effected by the level of interoperability the interconnect provides between IP cores and external memory..

Infotainment systems help drivers navigate safely to their destination while entertaining
passengers, and are no longer limited to high end vehicles: emerging driver assistance
automotive systems are now making their way into the mainstream market. The front
LCD displays need to dynamically switch from the GPS display to one of many camera
views, or even a combination of images captured by several cameras housed around
the vehicle.

Hardware Accelerators are a common technique used to offload performancecritical
or time-critical functions from centralized, and heavily used application
processors.
Unfortunately, the hardware accelerator design technique comes with a heavy cost –
complete sacrifice of programmability.

Finite element analysis is now well established as a numerical method to determine mechanical response and thereby assess design adequacies of industrial products. At the present time in the Indian industry, FEA application appears to be the exception than the norm. A few key industries however are showing a growing interest in FEA analyses, for their powerful capabilities.

Hawaii is a different beast.
It may be part of the US, but things operate with mindset unfamiliar to the typical go-go American, as you’ll immediately discover when waiting to get your rental car.
They refer to it quaintly as “Aloha time.”

As any ASIC designer knows all to well, the pressure is relentless to develop larger chips with more functions (including analog) and to deliver in record time. Fabs keep making smaller geometry processes which allows for more transistors per unit area, but this does not make the design easier. And then there is the cost of a mask set, which also continues to escalate to unbelievable levels.

This whitepaper explains how Test Automation tools can be used with Ada to support Test Driven Development (TDD) in an Agile-programming environment. This paper assumes some basic familiarity with Test Automation products.

Presents a case study on how the Open Verification Methodology (OVM) was successfully applied to implement a SystemVerilog simulation-based conformance test environment for next generation FlexRayTM 3.0 Communications System controllers.

The following video introduces the alternatives to verify ASD:Suite Models using the ASD:Suite Release 3 and provides a basic overview of the user interface and of the verification windows. Press the Play button to learn about visual verification using the ASD:Suite:

Enventive Engineering, Inc. provides state-of-the-art software solutions for mechanical engineering. Enventive is the best tool on the market today for identifying and optimizing the critical parameters that will drive mechanism performance and reliability, from concept through production. Enventive is best in class for travel and effort studies, and is exceptional for tolerance analysis, including variation analysis of forces and motion.

Boundary scan testing offers a solution to the challenges presented by high component density, the increasing use of area array packages – such as ball grid arrays (BGAs) and Field Programmable Gate Arrays (FPGAs) – and the prevalence of complex, multi-layer PCBs, which make test probe access and bed of nails testing impossible for many new board designs. The XJTAG Development System aims to solve these challenges and also allows test programs to be re-used and optimised for production testing.

Cedar Valley Construction continued to grow from a small company to one with over 1100 employees. This subcontractor turned to Construction Imaging to assist in expanding their business efficiently with the use of technology.

Grating-assisted optical coupling into long-range modes of strip plasmonic waveguides is analyzed by a 3D numerical simulation with COMSOL Multiphysics. We used the RF Module and its scattering formulation. A comparison with results obtained using the common 2D approximated analysis is shown for the case of 1D grating coupler and input Gaussian beam. Excited diffracted modal field distribution is calculated as it evolves in propagation. The computation is demanding because of the large box size (40x30x4 lambda^3) and has been carried out on a Linux workstation with 96 GB of RAM. Some peculiar features of 3D analysis compared to 2D analysis are pointed out such as frequency shift of the maximum and higher order mode excitation.

Atmospheric ice is a very complex material with varying electrical properties due to different polymorphs of ice itself. Also, if the medium to be considered is snow, then density becomes an additional parameter because it is a mixture of three dielectrics water, ice and air. The permittivity and loss tangent of naturally occurring ice and snow shows lot of variation at different conditions particularly temperature. This paper is a comparative study of some experimental results found from literature and simulations of dielectric properties of ice and snow in Comsol.

As interest in the electromagnetic spectrum expands towards the infrared and terahertz range, the distinct advantages of using semiconductors instead of metals for plasmonic applications must be understood. Plasmonic resonances in gold (Au) and indium nitride (InN) gratings are studied, in the terahertz (λ=30µm) regime. The electromagnetic properties of Au and InN are described by the Drude model. InN, has a lower plasma resonance frequency of fp ≈ 52 x 1012 Hz (Far IR) as compared to that of Au which has fp ≈ 2.18 x 1015 Hz (optical range). This leads to InN plasmonic structures demonstrating a greater confinement of surface waves to the interface and greater field enhancement (~1.4 times) as compared to Au in the THz regime.

Multiphysics processes manifest in turbo-generators due to the leakage electromagnetic field of the stator and rotor end winding and its associated effects at machine frontal end. Such processes are a compilation of coupled phenomena having different electromagnetic, thermal, fluid flow and mechanical backgrounds. Electric current circulation through the metallic frames used for stator core clamping and support, insulation design for the stator end winding, or electromagnetic forces acting on the stator end winding involute, are just a few relevant topics of interest for turbo-generator manufacturers.

In thin-film solar cells (a-Si:H, µc-Si:H, CIGS, etc.) scattering of light is very important to increase absorption of light in the active layers of solar cells. Today the most efficient thin-film solar cells are designed or deposited on random textured transparent conductive oxides (TCO). In order to study the scattering properties of the surface texture we have developed a numerical model in COMSOL, which calculates the scattering parameters from atomic force microscopy scan of surface texture/topography. This way we can study and evaluate the texture capabilities to scatter the light before producing such a texture, thus reducing time and cost for studying new types of textured surfaces. The simulation results obtained from the numerical model were compared to measured values.

The electron beam emitted backward by Plasma Focus devices is being investigated as a radiation source for IORT (Intra-Operative Radiation Therapy) applications. A Plasma Focus device is being developed to this aim. The electron beam is driven through an electron pipe made of stainless steel to impinge on a 50 μm brass foil, where conversion X-rays are generated. Electromagnetic forces in the Plasma Focus device have to be investigated to understand their influence on the electron beam produced by the extraction tube. The AC/DC Module in COMSOL is being used to simulate the electromagnetic field in the extraction tube to determine the optimum material.

Introduction: Medium voltage reclosers are representing nowadays an important link between transmission power systems and low voltage grids. With a high level of renewable energy penetration, the medium voltage networks are becoming bidirectional. Therefore, the associated switching devices must ensure the protection of newer types of power systems as well as new types of loads. The optimal design of medium voltage reclosers is therefore important in order to enable high level switching capabilities. GriedShield recloser is a well know medium voltage protection device where the single coil actuators are being successfully used. GriedShield recloser has the ability to perform as a recloser, sectionalizer or automated load break switch. Proven design rated for 10.000 full load operations [1]. One pole of such device can be considered as being composed of two main subsystems: power and actuation. The first is represented by the power connections and the key element that ensures the arc extinguish - the vacuum interrupter [2]. The second subsystem can be either mechanical or an electromagnetic-based actuation unit. The electromagnetic solution presents several advantages compared to the mechanical approach, such as fewer components, higher reliability and less maintenance. The dynamic characteristics of electromagnetic actuators are strongly influenced by their shape, material proprieties, electric and mechanical elements. The magnetic, electric and mechanical dynamics are actually mutually dependent, with each affecting the others. Therefore, in order to ensure a fast and efficient design it is important to consider the Finite Element modeling and simulation enabling electromagnetic actuators virtual prototyping. This paper focuses on modeling, simulation and optimization of the electromagnetic actuators integrated in ABB’s reclosers. In the next section, this paper gives an overview regarding the operating principle of a single phase recloser. The third part focuses on the set-up of a steady-state 2D finite element simulation including materials non-linearity. The fourth section illustrates the coupling of the 2D model with an optimization software, modeFrontier [3] as well as an optimization case study. The next section introduces the challenges related to the actuator’s modeling and simulation in 3D Transient. The final part of this paper presents the contribution of this work as well as the perspectives.

Recently it has been proved theoretically (Miñano et al, 2011) that the super-resolution up to λ /500 can be achieved using an ideal metallic Spherical Geodesic Waveguide (SGW). This SGW is as a theoretical design, in which the conductive walls are considered to be lossless conductors with zero thickness. In this paper, we study some key parameters that might influence the super resolution properties reported in (Miñano et al, 2011), such as losses, metal type, the thickness of conductive walls and the deformation from perfect sphere. We implement an realistic SGW in COMSOL Multiphysics and analyze its super resolution properties The realistic model is designed in accordance with the manufacturing requirements and technological limitations. Here we present the results for models, the ideal and the realistic SGW.

Currently there is much interest in electromagnetic metamaterials [1-9]. In our work we have focused on design of tunable metamaterial which can be made within available technology. In proposed design we use metallic split-ring resonators and thin-wires (Figure 1). Moreover we have decided to introduce nematic liquid crystal layer in design to obtain tunability (Figure 2). One can control propagation of electromagnetic waves by changing orientation of liquid crystal molecules. We have used COMSOL Multiphysics to validate our design with electromagnetic simulations where scattering parameters (elements of scattering matrix) have been computed. Afterwards we have retrieved effective refractive index, permittivity and permeability. Obtained results allow us to state that proposed metamaterial can be applied in construction of phase-shifter operating near 90 GHz. We have confirmed high tunability of proposed design. Relative change of real part of effective refractive index was about 67%, and relative shift of minimum of real part of refractive index was about 1.8%. We have recommended final structure to practical realization. We believe that our work could be used to further optimization of electromagnetic devices (phase-shifters, filters etc.).

This paper presents the electrical and thermal analysis of an OLED module. The OLED module consists of the OLED tile and the DC-DC converter incorporated in its backplane. The DC-DC converter is realized as an integrated circuit and its inductor is embedded in the the backplane. The DC-DC converter is highly efficient, but a fraction of the electrical power is dissipated in the integrated circuit and the planar inductor. This dissipation has negative consequences on the OLED characteristics. Additionally the planar inductor represents a loop antenna that radiates electromagnetic energy. The radiated disturbance of the planar inductor must conform to the EMC standards. The COMSOL Multiphysics is used to investigate both the electromagnetic and thermal performance of the OLED tile.

In Pressurised Heavy Water Reactors (PHWRs), the fuel bundles are located inside horizontal pressure tubes made of Zr 2.5 wt% Nb alloy. During reactor operation, pressure tubes undergo corrosion reaction with the heavy water coolant flowing through it and picks up a part of the hydrogen evolved. Assessment of the hydrogen concentration in the pressure tube forms part of the programme to assess the integrity of the component for continued operation. Presently, sliver samples are removed from the inside surface of the pressure tube and the hydrogen concentration is measured in laboratory from them using dedicated instruments. As the process involves considerable time and considerable radiation exposure, an insitu technique for the measurement is being developed. In this method, a tool head is inserted in the pressure tube and the hydrogen concentration is measured using an innovative technique. The tool head consists of a few modules and one of which is a split type induction coil for heating the pressure tube. Design of the coil geometry and other parameters are to be optimised to get the required heating pattern in the pressure tube. The flux from the induction coil also shall not interfere with the other modules which are a part of the tool head. The problem has been simulated using finite element software COMSOL Multiphysics. This paper gives details of the analysis carried out and the optimised parameters.

A three phase transformer with very low harmonic pollution transferred back to power line is here presented. In fact, thanks to the described setup, intermediate harmonics (5th and 7th) are not going out back to the power line feeding the primary. These results has been extensively validated versus measurements performed on produced and shipped machine. With these results, TMC is then featuring thermal and structural studies in order to know before the construction the working temperature and mechanical stresses of different parts both in normal working configuration and in presence of internal or external failures. From this knowledge TMC is then able to motivate and assure his customers about the employment of given materials and technical solutions.

The design of modern electric insulation devices for medium and high voltage (HV) applications requires computational work that goes beyond solving just a Laplace equation for the electric potential, and limiting the electric field below critical values. Both field calculation and determination of breakdown limits are often challenges for the development of HV insulation systems. Two examples are discussed. First, it is shown how the field distribution is modeled and simulated if injected space charge dominates the electrical behavior, which occurs particularly in gas insulation with Corona discharge or in in HV direct current (HVDC) solid polymer insulation. Secondly, a recipe is provided for modeling and simulation of dielectric breakdown of gases via electric sparks in the form of streamers.

This paper shows how a time-dependent and non-linear simulation of the dynamic operation behavior of an induction machine is executed by means of the "Rotating Machinery" interface from COMSOL Multiphysics 4.2a. The two-dimensional FEM model is connected to electrical circuits by coupling the physics "Rotating Machinery" and "Electrical Circuit" interfaces. These circuits include the lumped electrical components to simulate the electrical effects in the end area as well as the three-phase-voltage system to supply the stator. Simulations are made for constant slip values as well as dynamical start-up with an additionally defined equation of motion as an ordinary differential equation by means of the "Global ODEs and DAEs" interface.

The silicon cantilever with the planar coil was applied to the magnetic flux density measurements. The influence of shape and dimensions of planar coil on magnetic energy density was described. In cause of magnetic anisotropy of analyzed silicon structure FEM method and couple field method was applied in simulation. The Lorentz force based sensors owing to their potentially simpler fabrication and better stability seem to be a better solution. Therefore, the Lorentz-force acting on a microcantilever with the planar winding has been a promising alternative for the measuring of the quasi-stationary and low frequency magnetic fields. The dependence of the beam size on the beam end displacement and its angle as well for the assumed magnetic induction was carried out.

The TS (Turin Shroud) [1,2] is a fine linen fabric showing a not yet explainable [3] double body image of a scourged and crucified man stabbed on the side. Many hypotheses have been formulated without success [4] and perhaps the most reliable is one correlated to the Corona Discharge [5] that supposes the presence of an intense electric field, amplified by the presence of ionization induced by radon. Before to formulate specific hypotheses regarding the environmental conditions, that will be studied in the future, the analysis focalizes the interest on the verification of the effects of such an electric model on a linen sheet. Therefore the first steps is to simulate the electrostatic field distribution along a two-dimensional sheet enveloping a numerical manikin of a human body having his position coherent with that detected on the TS [6]. Two of the authors [7] have already performed a preliminary analysis using a rough numerical manikin composed of 11 ellipsoids.

The understanding of pH-sensitive hydrogel swelling response in different buffer environmental condition is essential for its use in different practical applications. This necessitates its simulation in steady state and transient conditions. This paper mainly deals with the details of the numerical simulation performed by developing coupled formulation of chemo-electro-mechanical behavior of the hydrogel in response to changing pH of the surrounding solution. Simulations were performed to determine the response of hydrogel with varying pH of the surrounding solution in a wide range of pH (2-12). The investigation of the responsiveness of the hydrogels is focused mainly on the study of effect of variation of pKa and Young’s Modulus of the gel. The methodology used for this finite element based simulation is presented. The swelling characteristics of the hydrogel obtained under steady state conditions in these investigations are compared with previous simulations using other models/methods. This analysis is carried out using COMSOL and the effects of fixed charge density, buffer solution pH and Young’s modulus on the swelling were studied in different simulations. These simulation results are compared with available experimental evidence to show the accuracy of the model.

This work presents the results of a 3D numerical magneto-hydrodynamic (MHD) simulation of an electromagnetic DC pump for liquid metal using a rectangular metal flow channel subjected to an externally imposed transversal inhomogeneous magnetic field. In this study. 3D numerical simulation based on the finite element method was carried out using the computer package COMSOL Multiphysics 3.5a.The application and the limits of the electromagnetic and the hydrodynamic models are discussed herein. The results of two typical examples are summarized here, including laminar brake flow and pumping conditions for turbulent metal flow. These simulations accurately represent the formation of an M shaped velocity profile of liquid metal and are consistent with the results of recently published experimental and theoretical works.

Numerical simulation of an electromagnetic trigger with a short-circuit ring is presented. The main goal of inclusion of a short-circuit ring in an electromagnetic trigger is to develop an element suitable for use in a circuit breaker with capabilities of selective switching. The main problem to be solved is vibration of a moving contact due to zero electromagnetic force between the anchor and the core at zero driving current. Inclusion of a short-circuit ring into the core results in induction of current in the ring during flux change. This current produces magnetic field that superimposes onto the main field and results in non-zero force between the anchor and the core during zero driving current in the windings. Numerical simulation reveals that inclusion of a short circuit ring does not significantly decrease the maximal force and that it effectively reduces vibrationy of a moving contact.

The design of a RFID-enabled temperature sensor is described in this paper. In this sensor, a change in temperature causes structural beams to bend, which results in a proportional displacement of the plates of the capacitor. Plates' displacement results, in turn, in changing the value of its capacitance. The capacitor of the sensor is coupled to the LC resonant network of a passive RFID tag. This makes the tag's resonance frequency dependent on the value of the sensor's capacitance. Hence, by measuring the shift in the resonance frequency, one can measure the change in temperature. COMSOL multiphysics program was used to design the sensor and simulate its performance. Simulation results show that the designed sensor can have a resolution of about 0.0014 °C/Hz. This sensor can be implanted on a tooth or a dental implant to monitor the mouth temperature.

The human body consists of many different types of tissues each with specific passive electrical properties. Vital activities lead to a characteristic change of these properties and geometrical changes. Magnetic induction is a non-contact method which can be used to determine these changes. The method is based on the creation of a primary magnetic field that will produce eddy currents in the trunk, currents will produce a secondary magnetic field that has to be detected around the trunk. The objective is to know the sensitivity of such a method to the geometric and impedance changes in the trunk considering the safety issues.

Performance degradation of a superconducting RF cavity after quenching in an external magnetic field was calculated using COMSOL. This degradation is due to the increased resistance of a superconducting surface with trapped magnetic flux. The amount of the trapped flux depends on the size of the normally-conducting opening that develops in the superconducting wall of a cavity during quenching. This size is found by solving time dependent problem of heat propagation in walls of RF cavities; the trapped flux can be found by making static magnetic modeling for any specific geometry that includes the quenching cavity and a source of the magnetic field. Results of simulation are compared with the data obtained in a specially designed experiment.

Designing a Radio Frequency (RF) birdcage coil used in Magnetic Resonance Imaging (MRI) at high frequencies where the wavelength is comparable with the coil dimensions is a challenging task. Before construction of the coil, not only calculating the capacitance value which is necessary for the coil to resonate at the desired frequency but also geometrically modeling the coil in a 3D simulation environment and making electromagnetic analysis inside the coil have importance in terms of observing the resonance behavior and other performance features of the coil. This study covers both design and simulation methods of low-pass and high-pass birdcage coils in COMSOL Multiphysics and the software tool developed to perform these design and simulation methods according to user-specified parameters.

Linear wave propagation through inhomogeneous structures of size R≫λ (Fig.1) is a computationally challenging problem, in particular when using finite element methods, due to the steep increase of the number of degrees of freedom as a function of R/λ. Fortunately, when the geometry of the problem possesses symmetries, one may choose an appropriate basis in which the stiffness matrix of the discretized problem is block-diagonal. A particular scenario is the case of a cylindrically-symmetric geometry, where an appropriate basis is the set of cylindrical waves with all possible azimuthal numbers (m). Each of the excited cylindrical harmonics propagate through the structure independently of all other harmonics, and therefore the fields associated with that harmonic can be found by solving an essentially two-dimensional PDE problem in the ρ-z (half)-plane. The cylindrical waves have a prescribed dependence on the azimuthal angle variable (φ), hence the name – 2.5D electromagnetics. This novel approach is applied to the problem of cloaking and wave scattering off a spherical nanoparticle on metallic and/or dielectric substrates.

We report here on the use of the COMSOL emw (electromagnetic waves) module in the design of a microwave launcher. This launcher is to be used in a microwave Doppler sensor that is incorporated into a chemical looping combustion system. The launcher is designed in two steps. First, we determine the best mode for launching a wave into air from an overmoded cylindrical waveguide. he TE11 mode is desired for efficient launching from the cylindrical waveguide into the flow region. We then develop a transition from a coaxial transmission line to the cylindrical waveguide. Of three different designs, a taper launcher is best for efficiently coupling microwave energy from a coaxial line to the cylindrical waveguide.

In order to design an RF MEMS based device, it is beneficial to have information concerning mechanical behavior. For model verification purpose, solution offered by simulation software equipped with predefined physics application is one valuable way to provide initial reference. To avoid unwanted particular total strain in RF MEMS structures, a compensation layer can be utilized. When the number of elements involved in the equations is huge and more resources consumed accordingly due to thin multilayers, an approach to reduce is useful, though accuracy is one aspect that has to be taken into account. Behavior of capacitor structure models shown throughout this study gives an opportunity to estimate the fabricated device and for which application it fits.

In this study, COMSOL®4.2a is used to model a microwave heating process in a TE10 rectangular waveguide. The sample consists of a small cylindrical Ca-alginate gel (D = 8 mm, H = 10 mm) inoculated with bacteria Escherichia Coli K12. The sample is placed along the microwave propagation direction into the waveguide. Maxwell’s equations and heat transfer are coupled to a microbial inactivation model under dynamic heating conditions. The microwave inactivation of bacteria is compared to a conventional inactivation by conduction with the same heating ramp during 4 min 30 s. The study clearly demonstrates that the microwave heating of small cylindrical sample is not homogeneous under dynamic heating conditions resulting in lower bacteria inactivation comparing to conventional heating.

The scattering by a buried sphere in the frequency domain with the use of the Finite Element Method (FEM) implemented by COMSOL Multiphysics, is analyzed. A short-pulse is used as an excitation with the spectrum spanning from 50 MHz to 1 GHz. In order to validate our results, a comparison with data available in the literature is presented, in the simple case of a perfectly-conducting (PEC) sphere. Afterwards, to gain insight on the role of the sphere radius and the distance of the buried sphere from the interface, other simulations are performed. The case of a dielectric sphere, instead of the perfectly-conducting one, is studied too.

A full-wave three dimensional (3D)electromagnetic simulator can be used to simulate and visualize the propagation of electromagnetic fields across PCBs. This article will describe how CST MICROWAVE STUDIO® can be successfully used to characterize the response of high-speed channels, and how typical SI results such as S-parameters, Time Domain Reflectometry (TDR) data and eye diagrams can be numerically calculated to predict the response of a channel.

Feature range and user experience are sometimes seen as mutually exclusive. The ever-increasing complexity of de-sign tasks means that engineers need a broad range of powerful simulation tools and features at their disposal, but only a few of these will be helpful in any one situation. Knowing which feature to use and when to use it can be a skill in its own right. CST STUDIO SUITE® 2013 streamlines the simulation process without compromising on its power or flexibility.

By law, products must comply with international EMC standards which have been developed to regulate electromagnetic emissions and the susceptibility of electrical and electronic systems. Striking a balance between EMC and competing design requirements poses major challenges to engineers. By including EMC compliant design at an early stage, additional costly development iterations can be avoided later on down
the line. Simulation allows problems to be identified and corrected early in the design process, before the first prototype is built.

When designing a chip for a high-speed application, the whole channel, including the package and the printed circuit board affects the performance. Find out how multi-level package design times can be reduced with the help of CST.

The designer chose NI AWR Design Environment because the software offers good availability of microwave circuit libraries and strong and efficient optimization. With the VBA macro, the complex feeding network was analyzed more quickly. In addition, the designer noted that NI AWR software has good documentation and a collection of “how-to” videos and application notes.

NI AWR Microwave Office provides an easy to use interface and built-in process definition tools that allowed the Nanjing University of Science and Technology School (NUST) to efficiently construct the models for vertically multilayer interdigital capacitors and multilayer spiral inductors for our LTCC design. AXIEM enabled us to easily tune, sweep, and optimize the value of the capacitors and inductors.

Wideband couplers have many practical applications at microwave frequencies. If realized in an inhomogeneous medium such as microstrip, these couplers yield poor directivity, which results in severe performance degradation. One of the major reasons for poor directivity is the mismatch in the odd and even mode phase velocities, along the coupled lines. Several methods have been suggested for compensating for the phase velocity mismatch, but these are limited to narrow bandwidths. The undergraduate design project described in this success story investigates the design and simulation of a unique wideband coupler that improves directivity by increasing the number of stages of the coupled line coupler, thus resulting in a multistage coupler, which improves bandwidth performance and, with optimally positioned capacitances, delivers improved directivity and phase compensation.

The EMA Component Information Portal™ (CIP) offers Cadence® OrCAD® Capture CIS users a comprehensive, "off-the-shelf" CIS management environment that includes a component library with a pre-defined set of fields to help take the guesswork out of defining a database schema. A web-based interface enables non-OrCAD Capture CIS users, like those in documentation and purchasing, to have access to the parts database behind OrCAD Capture CIS without using native software. CIP also provides users with a distributor interface that allows them to download distributor parts data directly into their CIS database. With enterprise integration the CIS database will hold data from external systems like ERP, MRP, PLM, PDM etc.

In video surveillance applications, pre-stored images are likely to be accessed remotely and interactively upon
user request. In such a context, the JPEG 2000 still image compression format is attractive because it supports flexible and
progressive access to each individual image of the pre-stored content, in terms of spatial location, quality level, as well as
resolution. However, when the client wants to play consecutive frames of the video sequence, the purely INTRA nature of JPEG 2000 dramatically penalizes the transmission efficiency.

This paper envisions coding with side information to design a highly scalable video codec. To achieve fine-grained scalability in terms of resolution, quality, and spatial access as well as temporal access to individual frames, the JPEG 2000 coding algorithm has been considered as the reference algorithm to encode INTRA information, and coding with side information has been envisioned to refresh the blocks that change between two consecutive images of a video sequence. One advantage of coding with side information compared to conventional closed-loop hybrid video coding schemes lies in the fact that parity bits are designed to correct stochastic errors and not to encode deterministic prediction errors.

This paper describes new methods in the Trak charged-particle optics code to find the self-consistent, beam-generated magnetic fields of high-current beams. The modifications are helpful for general work with relativistic electron beams. They are critical for simulations of high-power microwave devices like the relativistic magnetron and the magnetically-insulated line oscillator.

Visual System Simulator (VSS) is complete and comprehensive software for the design of today's complex communications systems. VSS technology provides engineers with the ability to design the right system architecture as well as formulate suitable specifications for each of the underlying components in the communications designs. Like AWR's flagship Microwave Office software, VSS is also built upon the AWR unique unified data model; seamlessly providing for system and circuit level co-simulation.

Challenge
Demonstrate compliance with stringent environmental regulations for more than 1,800 products and 160,000 parts from more than 7,000 suppliers.
Solution
An automated, enterprise-wide materials compliance data tracking system from Dassault Systemes ENOVIA provides a centralized compliance database on more than 160,000 parts.
Benefits
Approximately $1 billion in revenues protected by ensuring Agilent’s preparedness for European Union environmental regulations, compliance audits and customer inquiries.

SPICE Accurate Statistical Timing for 40nm and Below Amber Path FX is a trusted analysis solution for designers trying to close on power, performance, yield and area in 40 nanometer processes and below.

printLogic is a batch printing and metadata stamping integration for Matrix which does not require opening or viewing documents in order to print them. One of the most important aspects of printLogic is the ability to metadata stamp documents based on Administrative parameters and control, removing the individual user from the process. With these constraints in place, printLogic helps organizations comply with virtually all Regulatory Agencies.

Analog to Digital Converters (ADCs) are a widely needed and used circuitry in todays semiconductor chips. They convert an analog input signal to a proportional digital value, normally represented by a number of bits as binary number. Main properties of an ADC is the number of bits commonly named “resolution” and the speed of the ADC normally measured in samples per second.

Indyme Solutions, Inc. has been the leader of modern retail communications solutions for the last 20 years. Whether a shopper needs assistance, a cashier requires managerial support, or a security door is unexpectedly opened, relaying information to the appropriate personnel is critical to ensure a rapid response. Managing multiple communication channels is no simple task—it requires a robust central communications platform with reliable hardware backing.

Our customer wanted to develop a MEMS microphone preamp ASIC. The sensor process variations were limiting the yield of his microphone solution and the existing ASICs provided no mechanism to change the parameters of the ASIC to remove the non idealities of the sensor. The Customer came to Cosmic looking for an ASIC solution to calibrate the sensor variations and maintain constant preamp output for a given external input despite variation in the sensor due to manufacturing process. Cosmic understood the requirements, selected the appropriate technology node and provided a solution to meet the stringent requirements.

Data on host systems is often the most sensitive on the network. Terminal emulators on the desktop provide access to these systems, but many organizations are still using older products, deployed using best practices from many years ago.

Because the large majority of corporate data resides on host systems, organizations must make that data available to the desktop in order to retain a competitive advantage. The increased demand for host access coincides with a corresponding business trend of buying and customizing off-the-shelf applications,
rather than the time-consuming and risky process of building solutions from scratch.

Many different semiconductor technologies are currently being used for power amplifiers (PAs) that include a mix of Silicon and GaAs devices – Silicon Bipolar, Silicon MOSFET, GaAs MESFET, GaAs HBT and GaAs pHEMT. Avago uses enhancement-mode pHEMT (E-pHEMT) process for its PA design while most competitors have developed GaAs HBT technology. This paper shows why E-pHEMT technology can provide superior electrical and reliability performance for power amplifier design in wireless communications.

The design and implementation of a high isolation buffer amplifier is presented. This IC uses a two gain stage topology processed in the Avago Technologies Enhancement Mode pHEMT GaAs technology and is packaged in the 8-lead 2mm x 2mm LPCC. It operates preferably from a 5 Volt supply and consumes approximately 35 mA quiescent current. By varying an external bias resistor, the buffer amplifier can deliver maximum output power up to 20 dBm at 2 GHz. It has better than 40 dB of input-output port isolation and operates from 0.5 GHz to 6 GHz.

E-pHEMT (enhancement-mode high-electron mobility transistor) is a semiconductor process optimized for wireless applications that operate from a single positive voltage source. Ordinary depletion-mode pHEMTs conduct at zero gate bias, or when the drain current, Id, reaches a saturated level (Idss) at a gatesource voltage (Vgs) of 0 VDC. An E-pHEMT shows no conduction at zero gate bias, so that Id = 0 at Vgs = 0V. Thus, it can operate without the negative voltage (required for switch on) required for depletionmode devices.

The development of PHEMT, 24 to 31GHz 2W/4W power amplifier MMICs are described. The amplifier was designed with highly integrated distributed line-based low-loss power combining design techniques utilizing a 0.15μm GaAs PHEMT production process.

More than ever before, companies are being asked to do things faster. They need to get products to market faster to remain competitive and capitalize on market opportunity. That time pressure is being felt across all phases of the software development lifecycle. Developers need to deliver more innovation through complex code faster, and time allotted for formal quality control is shrinking. To deal with this pressure, companies are turning to Agile development methodologies for rapid iterative development cycles and the promise of improved efficiency and faster time to market. According to a recent study published by Dr. Dobbs and Forrester Research, over 45% of companies have implemented some form of Agile development.

Most developers would agree that consumers of software today continually demand more from their applications. Because of its pace of evolution to date, the world now anticipates a seemingly endless expansion of capabilities from their software, regardless of where that software is applied. For the last 40 years of computing, Moore’s Law has held true, with the number of transistors available in an integrated circuit doubling approximately every two years. This constant pace of innovation provided software developers with critical hardware resources, enabling them to expand the features and functionalities of their applications without concern for performance. However, while Moore’s Law still is holding steady, single-core processing has reached its performance ceiling. In response, hardware manufacturers have developed new multi-core (or multi-processor) devices to accomplish the speed gains to which the world had grown accustomed.

Software drives competitive business success in a global economy. In that context, software quality is key, and costs of defects late in the life cycle become prohibitive. Increasingly, therefore, we see organizations pushing quality (including security) initiatives, even in a difficult economy. Yet organizations have been releasing software and dealing with defects post-deployment for years. Why do current approaches tend to be inadequate? Companies make money and support business operations with their software using traditional testing techniques and dealing with some level of bugs post-release. Why is it the case that old quality models are falling short to sustain software development and deployment?

Aava Mobile was founded in 2009 by a team of engineering wizards with a strong background in mobile phone development who wanted to build an opensource mobile device platform for the OEM/ODM market. Aava Mobile’s open devices harness the creativity of developer communities and provide the flexibility to OEM/ODMs and mobile operators to incorporate their own user interface, content and services to differentiate their devices from competitors.

Sirona products are to be found in all fields of treatment and activities in a modern dental practice. These include, in addition to treatment equipment and instrumentation, the business division CAD/CAM Systems (production of ceramic inlays, onlays, partial crowns etc) and imaging systems with its products for X-Ray diagnosis. Sirona, as a system manufacturer, has the ability to combine products from the various business divisions – an example being CAD/CAM-Systems with 3D X-ray tube devices. The
Imaging Systems products range from intra-oral x-ray devices such as the Heliodent Plus range as shown in Figure 1, panorama x-ray devices (Orthopos range) to 3D devices (Galileos range).

Microdul produces proximity sensor chips that can be used with remote sensing plates. Changes in plate capacitance are detected by a digital auto-calibrating algorithm. An approaching human finger typically causes a switching operation. This principle is demonstrated in Figure 2. The capacitive switch can be used for many non-contact applications. The main challenge is to develop a sensor which can reliably distinguish between intentional switching operation and environmental interference.

Quality healthcare aimed at prevention is a trend that is rapidly gaining momentum. Medical devices that capture vital parameters and possess multiple connectivity features enable a seamless flow of information between caregivers and patients. Patient vitals can be located in a centralized repository, which can be accessed and processed by authorized personnel. Home healthcare is booming because of an increase in the aging population, rising healthcare costs, and demand of quality healthcare from remote locations. Technological innovations in the field of medical electronics and communication can drive the cost of healthcare. Applications for health at home include chronic disease management, post operative care, fitness, general wellness etc.

With the trend of increased adoption of consumer electronics in the automotive industry, the design of the center console is undergoing a major shift. This article covers some of the emerging trends which are finding increasing adoption in the center console. These technologies not only provide a seamless human machine interface for when the passenger uses a cell phone or the car navigation unit, but also enable automobile manufacturers to save money, improve reliability, and create a shift in the aesthetics of the car.

With the penetration of Wireless technology into the human interface device (HID) market, more and more sophisticated HID products are now coming out in the market with integrated wireless technology (wireless keyboards, wireless mice, etc). Often, developers are limited in their options: follow a popular wireless standard like Bluetooth or develop a proprietary protocol optimized for their application. While wireless standards provide the benefit of interoperability, they also introduce complexity and overhead that an application may not require, resulting in a higher system cost. On the other hand, proprietary protocol gives developers flexibility to customize applications at the expense of requiring developers to take on the development process.

As a result of inaccurate forecasting, Acme Cellular’s worldwide market share of cellular phone sales was declining. Our product portfolio included five different
models of cellular phones (AC-1 through AC-5). Each model is available in 6 different configurations for various languages and service providers. We also have three suppliers for Flash memory devices: Samsung, Toshiba, and Micron. Inventory control, for both unprogrammed (blank) and pre-programmed Flash memories, is critical, as more than 90 different part numbers must be generated and managed. Compounding these forecasting problems were shipping delays due to last- minute code changes.

In the context of electronic product manufacturing, mission-critical applications are those that are vital to the functioning of an overall system. If the application fails, there are typically undesirable results which might jeopardize human lives or may cause significant damage or loss. Examples of these applications are the brake or air bag system in your car, the chip inside a heart monitoring system, or the chip inside the circuitry that controls the navigation system of an airplane. Even though these are dramatic examples of mission-critical applications, our daily lives are full of similar applications with very low to no tolerance for failure.

Physical design is all about maximizing the manufacturable functionality on a single substrate. Increasingly, this requires the ability to design, validate and integrate unconventional devices in diverse manufacturing mediums.
Design Workshop Technologies’ dw-2000™ software is a powerful layout creation platform. It supports layout engineers in designing manhattan and complex, curve linear micro devices. For nearly two decades, dw-2000 has provided layout engineers with a proven product used in the physical design of microelectronic, RF, MEMS and photonic structures.

Over the last few years the optical component industry has embarked on a planar waveguide revolution. The basis of planar waveguide technology is to create optical waveguides on substrates utilizing manufacturing processes similar to those used in the semiconductor industry. The benefits of this technology are high yield scalable manufacturing, a platform for further optical integration and improved quality over manual assembly techniques. Planar technology is currently being used to manufacture a variety of components including AWG,VOA, OADM and SOA.

DCT Engine with Camera Link Interface (DECLI) is an integrated Camera Link Interface and DCT based image compression solution. It can provide interface to any industry standard mono chrome camera (CLI) and compress data by a fixed compression ratio of 32:1 (lossy) and out put the compressed data in serial, HDLC, parallel and PCM formats.

Because customization, personalization, and convenience are increasingly important to today's customers, BayTalkitec (BTT) decided to create a "Video Yellow Pages" application, which would respond to an SMS message by pushing a video to the sender's 3G mobile phone over a video call.

Beijing MXTelecom integrated high-capacity Dialogic® boards and Dialogic® HMP Software into its CTI solutions, including its IP Call Center and TICQ platform. One of the IP Call Center installations that used Dialogic HMP Software not only provided seamless PBX-IP connectivity for customers, but also reduced media processing implementation costs by about 60%.

CCMENA designed an integrated IVR, CRM, and contact center solution that would allow the international mobile satellite service provider Thuraya to manage its customer care operations more efficiently.

Combining video with voice and text applications to create multimedia services is an important development in the worldwide communications marketplace. Adding video promises to provide a robust new revenue stream for service providers and greatly enhance business solutions, including the contact center. This paper explores market segment trends, multimedia services, key multimedia standards, and the technical components needed to deliver multimedia services effectively. A section on Dialogic and multimedia discusses some of the Dialogic® products that can help make the move to multimedia faster and more cost effective.

Combining video with voice and text applications to create multimedia services is an important development in the worldwide communications marketplace. Adding video promises to provide a robust new revenue stream for service providers and greatly enhance business solutions, including the contact center. This paper explores market segment trends, multimedia services, key multimedia standards, and the technical components needed to deliver multimedia services effectively. A section on Dialogic and multimedia discusses some of the Dialogic® products that can help make the move to multimedia faster and more cost effective.

This paper supplies high-level and detail comparisons and a set of scenarios to help you decide whether an appliance gateway, gateway subsystem, or HMP interface boards are the appropriate option for an environment and for a particular set of development resources and deployment needs.

Published in "Metering International Issue" in 4-2008.
Using more advanced system design tools for embedded processors is just the start of a new era of system development for any measurement devices. With powerful processors like Blackfin and SHARC, designers can overcome development boundaries and realise highly functional devices rapidly and even to full series of production. This article describes some examples of “idea to final product” with these powerful new design methodologies.

FloRA is a coarse-grained reconfigurable array architecture with floating-point
operation capability. FloRA is implemented as a chip in Dongbu HiTek 130nm process,
and is evaluated using iNEXT board. We demonstrate JPEG decoder and fractal tree
generation at DAC’09 university booth.

System Design Group in Seoul National University (sdgroup.snu.ac.kr, led by Prof. Soo-Ik Chae) verified OpenVG 2D Vector Graphics Engine using iNTUITION prototyping board which is suitable development kit for video and graphics system including SDRAM, TFT-LCD, etc. Most computational blocks in graphics engine are implemented by dedicated hardware and off-chip SDR SDRAM memory is used. The system is developed on SoCBase platform provided by Center for SoC Design Technology in Seoul National University (soc.snu.ac.kr).

Quartz continues to be used widely in frequency control applications due to its high Q and temperature stable characteristics. In specific, ST-cut quartz provides the best
performance in narrow band SAW filter, SAW resonator, SAW oscillator, clock and data recovery unit, frequency translator, etc.
for many years.

One of the toughest (and unfortunately common) problems in embedded systems is
stack overflows and the collateral corruption that it can cause. As a result, we have
spent considerable effort inventing creative ways our customers can deal with this
problem. ThreadX developers have an array of tools at their disposal to detect and even
avoid stack overflow problems.

Specsavers has worked with Fujitsu across every aspect of its business for over ten years. For example, Fujitsu procures, commissions and installs every single piece of hardware in each Specsavers store, from EPOS terminals to printers to servers.

The Imperial Tobacco and Fujitsu teams participated in a three-day workshop to assess and fine tune the project requirements. From the outset, there were a number of criteria that had to be met if the project was to be successful.

A mixed-signal design team at a large IDM redesigned a signal amplifier IC for an electromechanical device. The designers retargeted the chip to run faster on a smaller process node. The new chip was no longer housed in a package; instead, the bare die was solder bumped and attached directly to the device in a mobile form factor.

IMST GmbH is a center of excellence and developer of professional radio technology.
We are proud to look back on more than 17 years of success. There have been many changes since 1992, but the values that created IMST – innovation, integrity and smart partnerships – have remained. We have held on to this tradition and it has served us well.

From a given technological node to the next, parameter dispersion (due to process
variations) and optical distortions (from layout to lithography) are strongly increasing. These phenomena, together with the ever increasing IC complexity, are impacting on yield and reliability. A methodology has to be defined to improve them for a nanometer scale process. To achieve that, an efficient prediction and monitoring of the IC performances has
to be performed.

Since sub-65nm technologies, Predefined corners (PDC) verification attains its limits. Corners number to be verified becomes huge with always the possibility of over-design. The worst is that these corners cannot guarantee the design; some corners could fall inside the process parameters
space while others could not really need to be tested.

Technology scale miniaturization and increased wireless and wireline designs result in complex RF and mixed-signal SoC designs growth thus requiring accurate prediction earlier in the design schedule.From the other side, the rapidly expanding telecommunications market and time-to-market pressures impose that the number of design iterations must be minimized.

IC Design is driven by two simultaneous trends: miniaturization of microelectronics technology, and telecommunication market expansion . When considered at a user
level, these trends seem to be compatible: by making devices smaller, integration of a larger number of functionalities in your
smart phone is made possible and thus boosts the development of the telecom market.

Broad market development of mobile devices and increase their computing power
gave new opportunities. Now handset mobile gadgets incorporate new
communication functions like audio/videoconferencing which were previously only available in the professional or premium grade devices. Popular services like FaceTime, Skype, Oovoo, Qik come to the mobile market as well.

Indirectly, there is big desire to have cross­platform implementation. Cross­
platform idea is a little bit cloudy thing because many people understand it
differently. It may mean support of different processors, compilers, operating system,
graphics and so on.

Today, the broadcast industry is increasingly turning its attention towards JPEG 2000. In recognition, the JPEG committee is currently finalizing the standardization of a new profile specifically dedicated to broadcast applications. This should be of no surprise as already the JPEG 2000 compression format guarantees the highest image and video quality while also offering many other properties that are particularly useful to the industry.

In high performance embedded systems test application, the requirement for accurate
measurement of AC and DC parameter is often critical. During development phase, IC devices are not permanently attached to the target board. Instead IC devices are connected via interconnect medium to the target board.

For over half a century, the semiconductor industry has been governed by a commonly known principle described as Moore’s Law. This “law” predicts that through technological advancement a doubling of the number of transistors per integrated circuit will occur within a given geometric area on regular 18 month intervals.

For today’s electronic module and equipment
designer, product life-cycle management
has become an increasingly important
competitive consideration for initial product design as it relates to both ongoing
manufacturing and to end-use customer
application.

For many products designed with today’s
high-performance integrated circuits, BGA
socketing systems are an essential option
during the design, testing, and/or production
phases of a new product development
process.

For many products designed with today’s
high-performance integrated circuits, BGA
socketing systems are an essential option
during the design, testing, and/or production
phases of a new product development
process.

The 20th century could have well been classified as the century of the automobile. Tremendous
changes in mindset and enhanced lifestyle of the populace at large created a spurt in the development
of the Automotive Industry. The period also saw significant advancements in the technology arena
with the spotlight settling on wireless communication. This sets the context for the current century:
Faster automobiles, state-of the art auto-infotainment, enhanced vehicle security etc. all facilitated by
a merger between the automobile industry and wireless communication and GPS based systems.

Cellular networks delivering 1Gbps of raw data throughput are on the horizon, and Tensilica is designing a DSP to meet the baseband-processing requirements of such networks: the ConnX Baseband Engine 64 (BBE64). The BBE64 achieves its performance by employing wide execution units that support up to 128x 18-bit operations in parallel, wide 640-bit registers, and massive I/O. The company targets a performance increase of 5-15 times for the BBE64 compared with the currently availablwe BBE16 for LTE.

Here is our collection of Wind River Tilcon Graphics Suite industry-specific demos. To see what can be achieved in as little as half the development time of traditional graphic library solutions, download demos to a local folder before running the EXE file. Windows XP or Windows Vista is required.

Here is our collection of Wind River Tilcon Graphics Suite industry-specific demos. To see what can be achieved in as little as half the development time of traditional graphic library solutions, download demos to a local folder before running the EXE file. Windows XP or Windows Vista is required.

Software development flows are often more thorough and well defined than hardware flows as far as specification lifecycle and requirements management are concerned. Reqtify, a requirement traceability tool developed by the Valiosys Group, is already used in this area by many customers worldwide.

Agile Software Development and the
breed of Agile Methodologies (XP, SCRUM, DSDM, etc.) have gained popularity since 2001. Primarily founded as methodologies for software projects executed at a single location, Agile Methodologies have started showing promising results in multi-site
projects too with many adopters and practitioners across the globe.

The success of a web application penetration testing project is directly proportional to the quality of its execution cycle. Executing a penetration testing project is very different from executing a functional testing project given the fundamentally different goals and challenges of penetration testing and
vulnerability analysis.

This whitepaper is the first in a series of three that will address these challenges. The paper will examine the challenge of achieving high quality while controlling costs. Topics covered will include: review of the limitations inherent in traditional methods, current best practices, and successful solution strategies that have been proven at leading global organizations in the automotive industry.

Product engineering organizations face the incredible challenge of ever shrinking market windows for innovation. These opportunities if missed, can lead to huge costs and overwhelming complexity, that can compromise quality and lead to very expensive recalls. Innovating in the face of these pressures require organizations to rethink their disconnected modeling practices and move to a unified lifecycle management approach integrating models into the core engineering process.

This paper will show that Agile practices and approaches must be blended with proven enterprise practices to achieve the right mix of agility and discipline. Scalability is achieved by leveraging a robust and unified application lifecycle management solution to automate processes and activities where possible, improve visibility and transparency across the organization, and automatically provide status reporting as a byproduct of the activities the team performs using the solution.

Presents a case study on how the Open Verification Methodology (OVM) was successfully applied to implement a SystemVerilog simulation-based conformance test environment for next generation FlexRayTM 3.0 Automotive Communications System controllers.

CVRx is developing a second generation system to provide Baroreflex Activation Therapy. This system, called XR-1, will be evaluated to determine its efficacy and safety. After using IBM® RATIONAL® DOORS® as the requirements management engineering platform for about a year, it was replaced with Integrity, a PTC product. CVRx selected PTC for its flexibility, integration of multiple disciplines in a single solution and capacity to provide comprehensive traceability between artifacts. By using Integrity, CVRx has compressed development cycles, improved productivity, mitigated risk, and streamlined regulatory and internal reporting.

Fiserv Insurance Solutions, a unit of Fiserv, Inc. (Nasdaq: FISV), specializes in progressive software and outsourcing solutions for the insurance industry. Hundreds of carriers, managing general agents and third-party administrators, rely on Fiserv for policy, claims, billing and reinsurance administration as well as point-of-sale solutions and straightthrough processing. More than 3,000 clients use the company’s market-leading financial and compliance solutions. Fiserv Insurance Solutions recently received six awards at the 12th Annual ACORD Awards ceremony, and received Certification Awards in the three industry sectors overseen by ACORD – Reinsurance, Property and Casualty, and Life and Annuities.

Swisslog is a global provider of integrated logistic solutions for warehouses, distribution centers and hospitals. Their comprehensive portfolio ranges from building complex warehouses and distribution centers including Swisslog’s software, in-house logistics solutions for hospitals as well as software and consulting services in the field of supply chain management.

Each of the following software is not free software. You may download it from the link below and evaluate it during the trial period free of charge, after which the software will stop running if it is not authorized. A unique authorization software key (softkey) will be provided to you to unlock the software for permanent use after you purchase it

EDALab s.r.l. located in Verona, Italy, addresses issues of technological innovation in the field of networked embedded systems. EDALab activities range from analysis and feasibility studies to full project management, providing services such as Embedded Software Development, modeling and conversion of hardware description languages, OS customization, and more.

Bochum-based NISYS GmbH develops solutions in the domain of advanced vehicle driver assistance systems. Algorithms developed by the company enable the automatic recognition of road markers and traffic signs (speed limits, merges, hazards), even at high speeds. Tools offered by NISYS GmbH simulate driving environments for endurance and durability tests through the auto-generation of ground-truth data.

In the September 2005 issue of IEEE Transactions on Device and Materials Reliability, the article entitled The Rosetta Experiment: Atmospheric Soft Error Rate Testing in Differing Technology FPGAs [Ref 1] described real-time experiments that evaluated large Xilinx FPGAs fabricated in two CMOS technologies (150 nm and 130 nm) for their sensitivity to radiation-induced, single-event upsets and detailed the results from simulation, beam testing, and atmospheric testing. These results were compared to circuit simulation (QCRIT) studies as well as to LANSCE neutron beam results.

QualCore has developed its own chip that is functionally and pin-to-pin compatible with with Analog Devices’ AD218 DSP. The chip series is called Vijay and is certified by Analog Devices. QualCore also provides the soft IP cores for this DSP, which are configurable and are therefore area optimal. Typical applications for the Vijay Core include Voice Compression, Audio Compression, Spectrum Analysis among many others

As one of the world's leading producers of oil and gas, the company profiled in this case employs over 2,000 people worldwide, and relies heavily on geological and geophysical software to support its production activities.

The focus of this paper is to examine usage metering in an E&P IT environment can be beneficial for many stakeholders; executives and IT management, individual users, and also providers to the industry.

As interest in the electromagnetic spectrum expands towards the infrared and terahertz range, the distinct advantages of using semiconductors instead of metals for plasmonic applications must be understood. Plasmonic resonances in gold (Au) and indium nitride (InN) gratings are studied, in the terahertz (λ=30µm) regime. The electromagnetic properties of Au and InN are described by the Drude model. InN, has a lower plasma resonance frequency of fp ≈ 52 x 1012 Hz (Far IR) as compared to that of Au which has fp ≈ 2.18 x 1015 Hz (optical range). This leads to InN plasmonic structures demonstrating a greater confinement of surface waves to the interface and greater field enhancement (~1.4 times) as compared to Au in the THz regime.

Negative Refractive Lens (NRL) has shown that an optical system can produce images with details below the classic Abbe diffraction limit. This optical system transmits the electromagnetic fields, emitted by an object plane, towards an image plane producing the same field distribution in both planes. Recently, two devices with positive refraction, the Maxwell Fish Eye lens (MFE) (Leonhardt et al. 2000) and the Spherical Geodesic Waveguide (SGW) (Minano et al. 2011) have been claimed to break the diffraction limit using positive refraction with a different meaning. In these cases, it has been considered the power transmission from a point source to a point receptor, which falls drastically when the receptor is displaced from the focus by a distance much smaller than the wavelength. Although these systems can detect displacements up to lambda/500, they cannot be compared to the NRL, since the SGW deals only with point source and drain.

There is limited option for non-intrusive flow measurement of liquid metals at high temperature. Liquid metal flowing in a conduit along with the transverse magnetic field induces emf in the liquid metal. The emf developed; which has linear dependency on flow velocity; can be used for flow velocity estimation. In case of conducting conduit the emf can be measured at the conduit wall. The main hindrance with this technique is the calibration. The induced emf depends upon the thermo-physical parameters like electrical conductivity, viscosity of the liquid metal as well as the electrical conductivity of the conduit wall. The flow meter calibrated with a fluid at some temperature will not behave in the same way with other liquid metal or at another temperature. Usage of flow meter with different fluid necessitates calibration with that fluid at required temperature; which increase the cost of usage. In this paper, an effort has been made, using numerical methods, to eliminate the repeated calibration work for different fluid at different temperature.

We present a Finite Element Method (FEM) to calculate the complex valued k(ω) dispersion curves of a photonic crystal slab in presence of both dispersive and lossy materials. In particular the method can be exploited to study plasmonic crystal slabs. We adopt Perfectly Matched Layers (PMLs) in order to truncate the open boundaries of the model, including their related anisotropic permittivity and permeability tensors in the weak form of Helmholtz's eigenvalue equation.

The job of designing end-winding corona protection (ECP) system is one of the very important and complex phases for insulation configuration of high voltage rotating machines. This complexity stems on one hand from the highly nonlinear characteristics of the ECP material and on the other hand from the coupled multiphysics phenomena of the involved performance evaluation. Simulation based ECP design is considered as a time-saving approach and finite element method was adopted in order to understand and solve this problematic. In this work a simulation tool with COMSOL Multiphysics was developed to calculate the electrical-thermal behavior of the ECP system. Compare to experimental approach, design process is simplified and the results are presented intuitively. 2D and 3D modeling were applied.

An easily implemented method is devised, where analytical criteria for the occurrence of streamer discharges in strong electric fields are evaluated. This is highly useful when designing high voltage power transmission systems and components where the insulation is provided by a gas, e.g. air or SF6.

Cochlear Implants are implantable devices which bypasses the non-functional inner ear and directly stimulates the hearing nerve with electric currents thus enabling deaf people to experience sound again. Implant electrode array design is limited in electrode count, due to their large size in accordance to scala tympani (ST) with restrictions for deeper insertion in ST thus depriving access to low frequency auditory neurons. Silicon semiconductor technology provides the fabrication of advanced high-density CI electrode arrays with more stimulation sites, integration of electronics, reduced size, multiplexing and specific site selection as per frequency. In this paper we present the simulation results for the three different electrode configuration of our proposed design. Electric filed density distribution near the stimulation site is studied by COMSOL Multiphysics 4.2a.

Cancer causes significant human deaths. Radiofrequency ablation is an encouraging procedure for cancer treatment. The objective is to demonstrate the multiphysics simulation methodology. This paper summarizes the problem , governing equations, methodology, assumptions, simulation results and discussion related to the thermal performance prediction of radio frequency ablation on a homogeneous tissue model. The electromagnetic interaction with biological tissue and thermal ablation coupling are highlighted. he main problem addressed in this paper is the prediction of temperature distribution of biological tissue due to Radio frequency energy of electrodes. his is critical to estimate and monitor the procedure to ablate only the defective tissues as identified by the physician. The simulation potential for the development safe procedure planning and protocol is highlighted.

Resistive magnets are one of the principal components of ion medical accelerator systems used in heavy ion cancer treatment. To fulfill medical requirements, like the size of irradiation field and an uniform dose distribution, some magnets of the transport beam line may require large aperture and a large region where the magnetic field is within specifications (good field region). After a validation benchmark between COMSOL simulations and measurements of a dipole magnet used in the CNAO facility, COMSOL Multiphysics has been used to characterize the magnetic field quality of a very large 90° bending magnet. A stiffening frame has then been foreseen to preserve the mechanical rigidity of the magnet and its impact on the field quality has been investigated

Previous studies proposed using bipolar radiofrequency ablation across two catheters placed on opposing surfaces of the ventricular wall to create transmural lesions. 2D and 3D models were built and solved with COMSOL Multiphysics software. With these models, it was possible to study the temperature distribution and lesion geometry (Figure), to compare the potential of two ways of applying electrical currents (bipolar mode, BM, vs. sequential unipolar, SUM) and to investigate the effect of other factors such as the ventricular wall thicknesses and catheter misalignment have never been studied in detail. Our results suggest that BM is in general more effective than SUM in achieving transmurality through the ventricular wall. These results could improve the safety and performance of these procedures.

Conventional heating of material wastes energy during heating due to inherent radiation, conduction and convection based heating mechanism. Alternate efficient heating methods are actively researched for improved efficiency. Radio frequency based electromagnetic heating is increasingly used for efficient heating in place of conventional heating. This requires coupling of electromagnetic and heat transfer for performance evaluation of an RF applicator. A dielectric disk is considered for heating performance evaluation. The methodology, material properties used and simulation results are reported. The uniformity of heat application or electromagnetic energy distribution is used as metric to evaluate the efficiency. The virtual design and heating results are reported. The multiphysics coupling and parametric modeling capability of COMSOL is highlighted.

The optimized design of a waveguide applicator has been proposed for superficial microwave hyperthermia using COMSOL Multiphysics 3.5a. In microwave hyperthermia cancer treatment body tissue is exposed to high temperatures using external and internal heating devices. Non-Invasive or external hyperthermia is used to treat tumors that are in or just below the skin (superficial). Non-invasive hyperthermia systems using waveguide applicators are less traumatic to patients. The dimensions of the waveguide is optimally selected to focus the energy more specifically over the tumor region. The 3D modeling of the waveguide applicator is performed using different dielectrics and the performance is verified by analyzing the resistive heating and temperature distributions in muscle like phantom.

The optical scattering and absorption of gold nanorods (GNRs) depends on its size, shape, and surroundings. This dependence is due to both intrinsic and extrinsic effects. A good understanding of this dependence is needed for applications of GNRs in photo-thermal therapy, optical and opto-acoustic imaging, biosensing, and other photonic areas. Extrinsic effects are caused by the production of localized and surface plasmons and are well understood through Mie theory for spherical particles and Maxwell’s equations for arbitrary objects. Intrinsic effects become prominent at the nano-scale, when the cluster size becomes comparable or smaller than the bulk mean free path of electrons between collisions and additional scattering of the conduction electrons from the cluster surface occur. The addition of this scattering will shorten the mean free path between collisions and increase the damping constant.

Non-conventional hydrocarbon resources become more and more challenging object for energy producing companies throughout the world. Being already known and long-explored method, the electromagnetically (EM) assisted recovery constitutes a promising idea of technology for deposits of such a kind. COMSOL has been used recently for modeling the thermal multiphase flow through porous media in the different frameworks [1], in-situ resistive heating field in a bitumen reservoir [2], etc. Although this experience demonstrated that some problems related to petroleum applications can be resolved successfully using fully-integrated models, the modeling of the real non-conventional fluids and their properties evolution requires considerable efforts and specific knowledge application. Nevertheless the multiphysics environment of COMSOL makes attractive to model phenomena of particular interest in parallel to petroleum related computations. The main advantage of this approach is to implement quasi-independent numerical models to different physical phenomena described each by its own equations and taking place in corresponding time and space regions [3]. In practice the total number of such models constituting a complex problem is limited by the computational power and the type of coupling between them may be a user-defined option. The main purpose of our current work is to develop an efficient COMSOL-based model for radio-frequency EM field distribution inside heterogeneous saturated porous media. Such a model can be a promising tool, for instance, in petroleum applications. As a successful example we can mention is the EM heating method for in-situ upgrading which can be found in [4]. Relatively simple geometrical configurations have been used to validate our models using comparison to available and developed analytical solutions. In particular for two different versions of the simulation, the accuracy and convergence rate of numerical EM field solutions for different grids and element orders have been checked. Then the models have been applied in more complex multidomain multiphysics framework of field-scale recovery problem. The examples of EM field computations are presented with detailed analysis of numerical solution accuracy and computational performance of the model. The advantages of the new model (where both elements choice and solver features have been explored) are demonstrated.

Linear wave propagation through inhomogeneous structures of size R≫λ (Fig.1) is a computationally challenging problem, in particular when using finite element methods, due to the steep increase of the number of degrees of freedom as a function of R/λ. Fortunately, when the geometry of the problem possesses symmetries, one may choose an appropriate basis in which the stiffness matrix of the discretized problem is block-diagonal. A particular scenario is the case of a cylindrically-symmetric geometry, where an appropriate basis is the set of cylindrical waves with all possible azimuthal numbers (m). Each of the excited cylindrical harmonics propagate through the structure independently of all other harmonics, and therefore the fields associated with that harmonic can be found by solving an essentially two-dimensional PDE problem in the ρ-z (half)-plane. The cylindrical waves have a prescribed dependence on the azimuthal angle variable (φ), hence the name – 2.5D electromagnetics. This novel approach is applied to the problem of cloaking and wave scattering off a spherical nanoparticle on metallic and/or dielectric substrates.

Thermally conducting but electrically insulating materials are needed for heat-sink LED lighting applications. We report on a cost effective and innovative method based on creating core-shell nanoparticles in polymer with aluminum (Al) nanoparticles as the high thermal conductivity core and ultrathin aluminum oxide (Al₂O₃) as a capping shell. The solid oxide shell around the Al core prevents agglomeration of Al nanoparticles. A coupled COMSOL heat transfer and AC/DC modules were used in the simulation. The mean effective thermal conductivity seems to exceed the value of 100W/m·K with an electrical permittivity of 52 at 12% Al-Al₂O₃ core-shell nanoparticles loading in a polyvinylidene fluoride polymer nanocomposite. These results are considered outstating but they need to be validated experimentally.

Topographic effects on magnetotelluric responses may be severe on rugged terrains. Finite elements simulation is a valuable tool to quantify this effect, due to its capability to match real morphologies. To do the estimate of the distortion, the AC/DC Module of COMSOL has been employed, using a model of homogeneous resistivity on which a DEM (Digital Elevation Model) profile of the Deep Freeze Range (Victoria Land, Antarctica) has been superimposed. Then, the MT responses at several surface sites has been computed.

A model of a cell counter sensor based on Impedance Spectroscopy (IS) has been implemented in COMSOL Multiphysics. The cell counter is a silicon-based microdevice consisting in 3D electrodes placed in a wide microchannel: cells flow in the microchannel through the electrodes to be detected. The model allows to evaluate the functionality of the device depending on geometrical parameters and material properties, cutting down experimental time. Two and three electrodes configurations have been tested, focusing on the variation of impedance due to the presence or absence of particles (polystyrene beads or cells). The resulting signal variation allows us to verify and quantify the efficiency of the device.

Magnetic separation of magnetic liquid phases/particles from non-magnetic liquid phases/particles are needed for pplications such as cleaning up oil spills by separating oil and water liquid phases or separating magnetic materials from non-magnetic materials in biomedical and microfluidic applications.
Magnetic fluids (also called ferrofluids), in a magnetic field, experience a magnetic force density. COMSOL Multiphysics was used to show that magnetic energy density of a particular permanent magnet configuration is a more intuitive way of understanding how a magnetic fluid moves in a magnetic field. As a result, a novel magnetic separation technique was developed, using permanent magnet edges and Halbach magnet arrays, that separated a variable magnetic volume fraction from a mixture of magnetic and non-magnetic liquid phases.

This paper presents an optimized combination of artificial diffusion techniques to stabilize a drift dominated streamer discharge model which includes COMSOL Multiphysics’ Transport of Diluted Species modules for positive ion, negative ion, and electron charge densities, coupled through the Electrostatic module. A Thermal Conduction and Convection module is responsible for the heat transfer in the model. Optimal 2D axisymmetric and 3D mesh schemes are also introduced to effectively solve the numerical problem. Several combinations of streamline diffusions and Crosswind diffusion with different tuning parameters are applied to the charge continuity and the thermal equations with different mesh element size distributions to determine the ideal approach.

The design challenge for hermostimulation equipment is to get a combination of high electric field strength and high emperature within the muscle tissue without causing pain or skin burns. In the present work, COMSOL Multiphysics is used to simulate the temperature distribution and electric field distribution within body tissue for varying body composition and varying design parameters of hethermostimulation equipment. COMSOL LiveLink™ for MATLAB® is used in order to do script based parametric analysis, sensitivity analysis and iterative optimization from MATLAB®. The present work has shown how the multiphysics approach gives information regarding design choices for thermostimulation equipment, and relative effectiveness of thermostimulation equipment for patients with different body composition.

A scheme for inductive wireless powering and readout of passive LC sensor is presented. The sensor’s inductor is designed as a planar square coil and is used as the power receiving component. The capacitor is connected directly to the inductor and it was designed as an interdigital capacitor. With a transmitting
coil (coupling antenna), an electromagnetic field is generated which couples with the sensor, affecting the impedance of the coupling antenna. This work studies the effects of permittivity variations in a capacitive transducer. All the fabrication and characterization processes were carried out at the clean room of the Universidad de los Andes. The design and the simulation of the wireless passive micro-sensor based on LC resonators were made using COMSOL-4.2a.

Pressurised Heavy Water Reactors (PHWR) play a prominent role in contributing power for the Nuclear Energy Programme in India. In 540MWe type PHWR reactors, there are horizontally placed Liquid Injection Shutdown System (LISS) tubes for injecting poison into the moderator to clamp down the nuclear power under trip conditions. The Horizontally placed LISS pipes are placed perpendicular to the horizontal Coolant Channels in the inter lattice positions as shown in Figure 1. The gap between the coolant channel and the LISS tube is critical considering the possibility of fretting damage in the event of closing of this gap. The Coolant channels consists of two co-axial tubes called Pressure tube (inner) and Calandria Tube (outer). The gap between LISS tube and calandria tube cannot be measured directly as the whole core of the reactor is enclosed in a vessel called Calandria vessel. Only easy access to the core is through the bore of the pressure tube for employing any inspection technique for measuring the gap. As the probing medium has to penetrate the pressure tube and calandria tube barriers, Electromagnetic technique only appears to be feasible for the inspection. Remote Field Pulsed Eddy Current technique is proposed for this measurement. The remote field originates from the exciter coil kept in the bore of the pressure tube and propagates through the outside metallic barriers and makes a re-entry into the pressure tube approximately at a axial distance of 2 diameters of pressure tube. The search coil is used at this location to pickup the prominent Remote Field. The pick up signals are further Digitally Signal Processed to gather information of the gap between LISS tube and calandrai tube. COMSOL Multiphysics software was used to map the poynting vector to guage the re-entry location of the remote field. The Poynting Vector mapping is shown in Figure 2. Further it is also simulated to know the order of the voltage to be picked by the remote pick up coil. The Figure 3 shows pick up voltage simulated for one turn.

Surface breaking cracks in conductive structures can be detected by conventional eddy current techniques. However, it is very difficult to detect inner layer defects in multilayered conductive structures either by conventional eddy current or ultrasonic methods. The transient/pulsed eddy current (PEC) technology can potentially overcome these limitations and is being developed for detection of deeper defects in multilayered aluminum structures [1-2]. An earlier work [3] successfully employed COMSOL Multiphysics, the finite element (FE) modeling software, to develop and optimize a reflection type probe where the driving and pickup coils were coupled coaxially. The probe could detect defects underneath a 3.6 mm thick aluminum plate and there was good agreement with experiment. However, it was not very effective in detecting inner layer cracks that originated at a ferrous fastener, as typically found in airplane wing structures. This necessitated the development of a different probe design. The present work describes the new probe design, which consists of two pickup coils, connected in differential mode, on either side of the central driver, as shown in Figure 1. The work involves modeling of a PEC probe and its optimization by varying geometry and other circuit parameters of the driver-pickup coil combination. The modeled differential pickup signal for a crack of length 9.0 mm, width 0.25 mm, and four different crack depths are shown in Figure 2. It reveals that, although the signal decreases with increase in crack depth, the probe can potentially detect a crack at a depth of 4.0 mm below an aluminum plate. In summary, the COMSOL software proved to be useful in presenting a visualization of diffusion of magnetic flux through the ferrous fastener and its interaction with the surrounding defect region, which led to development of an optimum probe design including appropriate location of the sensing coils in the probe.

Waterflooding and steam-flooding are used worldwide for EOR. Recently, CO2-flooding has attracted global attention as a means of EOR as well as for carbon capture and sequestration. These processes cause significant changes over time in the fluid composition of oil reservoirs. This paper demonstrates the feasibility of a borehole transient electromagnetic (TEM) system that can map the fluid dynamics of these processes. This mapping can delineate bypassed pay and yield the extent of flooding. We use COMSOL Multiphysics to simulate the borehole TEM system in 2D and 3D models of waterflooded and CO2-flooded reservoirs. These simulations prove the efficacy of this technology in providing deep and azimuthally sensitive measurements and illustrate how TEM diffusion responds to electrical resistivity contrasts.

Non contact charging of electronic equipment from mobiles to electric vehicle has created immense interest among researchers. There are various groups working on both radiative and non-radiative energy transfer. The idea based on strongly coupled magnetic resonances is of interest because of the increased distance of energy transfer. This technology based on resonant magnetic coupling with the introduction of negative refractive index materials in the environment is also novel and exciting. We simulate and analyze the effects of introduction of various materials between the resonant coils. The structure and physical parameters play an important role in efficiency and quantum of energy transfer. The array size of the various materials and structure has an important effect on the transfer coefficient. Since the permittivity and permeability of the two media have different features, the components of the electric field (or the magnetic field) changes when the observation point is moving towards the interface. This property and feature can be studied before optimizing the structure and physical nature of the system. The simulations are done using COMSOL Multiphysics a finite element analysis software. Some interesting results evolve as we introduce various medium in the environment. These aspects will be experimentally verified by studying a real time system.

Water-and-energy supply is a global issue of paramount importance. The demand for safe potable water is quickly exceeding the limits of natural regional water resources. Like oil, water is a finite resource; unlike oil, however, water has no alternatives. Water, energy and their environmentally sound solutions are interrelated; and of all the present-day environmental problems, those related to energy-and-water will have the worst long-term consequences if not resolved. Spiral-wound-reverse-osmosis (SWRO) desalination provides an alternative water resource that is both energy-efficient and highly-effective in removing particulate matter to well within the EPA’s NPDWRs. Thermodynamically SWRO is an isothermal, reversible process that is closer to the lower energy limit than any other present-day desalination process. Real-world energy consumption, however, still accounts for +50% of the total operating cost of SWRO desalination plants. According to the U.S. Desalination and Water Purification Roadmap, membrane-permeability and fouling-resistance are primary economic drivers which translate directly to the energy footprint of these multi-megawatt facilities, whereby biofouling (marine-bacteria-biofilms) is considered the "Achilles Heel" of SWRO-membrane processes. , Concurrent research demonstrating the feasibility of dielectrophoresis as a biofouling remediation technology revealed that colloidal particles can be effectively levitated to a steady height above a SWRO-membrane. This study is still largely inconclusive in that only clay-colloids were examined; the electrokinetic properties of which are drastically different than those of marine-bacteria. Rather than developing potentially-cost-prohibitive SWRO-membrane embedded microelectrode arrays, the primary focus of the simulation studies being conducted (utilizing COMSOL Multiphysics version 4.3; AC/DC, Microfluidics, & Particle-Tracing-Modules) are focused on developing a pretreatment-filtration device that is immediately upstream of the SWRO-membranes (d_p: 1-1000µm). The mCD device is an ideal desalination feasibility study platform. In order to better quantitatively describe the performance characteristics of a mCD device, numerical simulation efforts are being conducted utilizing COMSOL Mulitphysics.

Deep Ultraviolet Light Emitting Diodes (DUV LEDs) are presently operating at a relatively low efficiency, thus large amount of LED driving power is dissipating in heat. Thermal heating degrades LED performance and decreases LED’s lifetime. The degradation of DUV LED devices with temperature increase makes thermal management a key issue for DUV LEDs. We present a thermal analysis of DUV LED device by first investigating the thermal resistance of LED chip layers and interfaces, and then considering the overall heating of the LED package. COMSOL's AC/DC Module together with Heat Trasnfer Module was used to analyze the transient heating of the device. In addition, COMSOL Multiphysics Joule Heating interface has been used to analyze the thermal heating of the packaged DUV LED device. The modeled geometry included TO-39 package, submount and DUV LED die for realistic thermal simulations. Figure 1, shows a typical temperature distribution around DUV LED die mounted on submount and TO-39 package. The dissipated power in the device is 0.87Watts, and resulted junction temperature is 13 degrees above ambient. The temperature rise at the DUV LED die is primarily due to thermal resistance of submount, epoxy layer at the submount/TO-39 interface and thermal resistance of TO-39 package. For the calculations shown in Figure 1 the bottom surface of TO-39 package was maintained at the ambient temperature of 296K. To analyze detailed resistance of various interfaces, the transient heating analysis is performed and compared to experimental data for junction resistance fitting. The LED die is also investigated for temperature variations along semiconductor layers to locate regions of high temperature and high temperature gradients. The thermal analysis of DUV LEDs allowed us to identify thermal “bottlenecks” leading to overall device heating and temperature rise at the DUV LED die. The simulations also identified possible routes that will improve thermal management of the LED device and increase its performance and lifetime.

In this paper we want to figure out the development of a capacitive acceleration-sensor system with the FEM-Method. The sensor-system is in the position to detect accelerations in the range of ±20 g. Furthermore the sensor-element contains a printed RF-inductance, which is used for contactless data transfer. On the one hand the simulation of the L-C-oscillating circuit using the RF Module of COMSOL is shown, on the other hand the simulation of the sensor itself was done. The deflection of the sensor by an acceleration load was calculated and the change in sensor’s capacitance by the resulting deflection was evaluated. The changed capacitance of the sensor leads to a change in resonance frequency of the oscillating circuit, which could be detected.

Electromagnetic metamaterials present exotic and unusual properties hardly to be found in nature with many potential applications. They are usually built by distributing small resonant structures in periodical lattices. If the structure has chiral symmetry, the medium is called chiral metamaterial. Here the electrodynamics behavior of a chiral structure with a huge electromagnetic activity at microwave frequencies is modeled by making use of COMSOL Multiphysics RF's Module and successfully compared to the experiment. Linearly and circularly polarized modes at normal incidence have been simulated and different experimental conditions have been modeled to extract reflection and transmission coefficients for the electromagnetic characterization of the sample.

The optimal design of the grating coupler for surface plasmon generation is revisited for its interdisciplinary importance in the efficient use of energy, and the strong dependence of the energy convergence rate of the system on the design. This work contributes a comprehensive gradient based numerical optimization technique to optimize both geometry of the grating and parameters of the Gaussian beam simultaneously. The method modifies all geometrical boundaries of each groove independently in a fixed mesh. The efficiency of energy conversion between the Gaussian beam and the plasmon is maximized. The conversion rate of the optimal design is significantly greater than the initial uniform design. Results show the practical value of these tools to be used on a n-grooves grating.

A scheme for inductive wireless powering and readout of passive LC sensor is presented. The sensor’s inductor is designed as a planar square coil and is used as the power receiving component. The capacitor is connected directly to the inductor and it was designed as an interdigital capacitor. With a transmitting
coil (coupling antenna), an electromagnetic field is generated which couples with the sensor, affecting the impedance of the coupling antenna. This work studies the effects of permittivity variations in a capacitive transducer. All the fabrication and characterization processes were carried out at the clean room of the Universidad de los Andes. The design and the simulation of the wireless passive micro-sensor based on LC resonators were made using COMSOL-4.2a.

Performance degradation of a superconducting RF cavity after quenching in an external magnetic field was calculated using COMSOL. This degradation is due to the increased resistance of a superconducting surface with trapped magnetic flux. The amount of the trapped flux depends on the size of the normally-conducting opening that develops in the superconducting wall of a cavity during quenching. This size is found by solving time dependent problem of heat propagation in walls of RF cavities; the trapped flux can be found by making static magnetic modeling for any specific geometry that includes the quenching cavity and a source of the magnetic field. Results of simulation are compared with the data obtained in a specially designed experiment.

This work presents the study of spiral RF MEMS switch which has low actuation voltage due to spiral structure. This work is inspired by the superior performance of electrostatic RF MEMS switches over the conventional state-of-the-art solid-state devices and the potential applications in communication field. The customary high actuation voltage limits the reliability and applications especially in wireless communication, and hence focus on the realization of electrostatic low actuation voltage switches is rapidly increasing. The optimization of actuation voltage is achieved by analyzing the flexure design, beam topology, actuation electrodes and gap height using COMSOL Multiphysics models which are validated by simulations. It is observed that with more and more number of spiral ring structure actuation voltages can be reduced. The serpentine structure is suitable for low actuation switch is modeled and simulated in COMSOL Multiphysics.

Radiofrequency (RF) technology offers unique advantages for noninvasive selective heating of relatively large volumes of tissue. In this work, we present a mathematical model for selective non-invasive, non-ablative RF heating of cutaneous and subcutaneous tissue (with detailed fiber septa structures) including their thermo-elastic response. Our analysis shows that the fiber septa architecture affect the static electric field within subcutaneous fat. There is greater electric power absorption in the fiber septa filaments than in fat and it favors the flux of electric current density. When reaching the thermal steady-state, fiber septa contributes to enhance the selective heating of subcutaneous fat tissue. Fiber septa shows shrinkage due to its thermoelastic response, agreeing with clinical observations.

We study the topography influence of levees on the electric resistivity signal obtained with the Radio-Magnetotelluric method. Field measurements have been modeled with COMSOL, using the AC/DC and RF Modules. A levee situated in Orléans along the Loire river (France) has been considered in order to design a model tacking account of the skin depth and the incident wavelength, keeping a constant field in the whole model. The effect of the incident electromagnetic field direction is assessed with two different incident wave directions: BBC 5 and France-Inter. The simulations highlight the tri-dimensional effects in the apparent resistivity, observed on the crest of the levee, depending on the incident field direction and topography. A buried gas pipe is also characterized.

This whitepaper gives a general overview on different concepts of photonic crystal cavities. Important figures such as the transmission, the mode volume and the quality factor are discussed. The presented information will help the reader to decide which type of photonic crystal cavities will be most suited for the application in view.
A design example for a WDM channel filter is given in order to illustrate the design process for a photonic crystal
cavity. Furthermore two experimental examples from recent research are shown to demonstrate the wide range
of applications in which photonic crystal cavities could be used.