SC9 Power Management Kit - GLOBALFOUNDRIES 55 nm 55HV

ARM® Logic IP solutions are the ideal choice for advanced, deep submicron SoC designs. The Standard Cell Libraries are complemented by Power Management Kit and ECO Kit extensions, delivering optimal performance, power and area results.

Features

Very large cell set to ensure optimal implementation of all types of designs.

About 250 cells per Vt or channel length at 32/45nm

Smaller cell set in more mature technologies

Functions

Power gate header cells to switch power (VDD) and footer cells to switch ground (VSS)

Up, down and bidirectional level shifters with and without isolation capabilities

Dedicated isolation cells

Retention flip-flops, retention scan flip-flops and retention latches

Supporting cells like always-on buffers and inverters

All functions are implemented in multiple drive strengths

Includes UPF and CPF constructs, power aware back-end verilog models, well modeling

Patents granted on some design styles

Multi-Vt and channel length optimization for power gates and retention flip-flops for further leakage reduction

Multi-Vdd Characterization and overdrive voltage support

Deliverables

Front End (FE) and Back End (FB) views with full suite of design views and models that support most of the industry's popular design tools can be downloaded from the ARM DesignStart web site at: http://www.arm.com/support/designstart.php