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Tom Anderson, VP of MarketingTom Anderson is vice president of Marketing for Breker Verification Systems. He previously served as Product Management Group Director for Advanced Verification Solutions at Cadence, Technical Marketing Director in the Verification Group at Synopsys and Vice President of Applications Engineering at 0-In Design Automation. Before moving into EDA he was Vice President of Engineering at IP pioneer Virtual Chips, following roles in ASIC design and management. Tom holds a Master of Science degree in Electrical Engineering and Computer Science from MIT and a Bachelor of Science degree in Computer Systems Engineering from the University of Massachusetts at Amherst. « Less

Tom Anderson, VP of MarketingTom Anderson is vice president of Marketing for Breker Verification Systems. He previously served as Product Management Group Director for Advanced Verification Solutions at Cadence, Technical Marketing Director in the Verification Group at Synopsys and Vice President of Applications Engineering at … More »

To Standardize or Not to Standardize, That Is the Question

As regular readers know, Breker’s claim to fame is the automatic generation of multi-threaded, self-verifying test cases that run on multiple heterogeneous processors within an SoC. The source for the generation process is a graph-based scenario model that captures the design intent and verification space. We chose graphs as an enabling technology more than ten years ago for a number of reasons, some of which we’ll discuss in this post.

The catalyst for this discussion is a new effort within the Accellera standards body to form the Portable Stimulus Specification Proposed Working Group (PWG). Basically, Accellera has formed a proposed working group to determine whether a technical working group should be established to start developing a specification for a standard. What does this have to do with graphs, and Breker? We’ll do our best to explain the history and current status.

The first public announcement of possible graph standardization came in the form of a press release from our friends at Mentor Graphics. They proposed a new Accellera working group to develop a “Graph-Based Test Specification Standard.” As far as we know, Mentor is the only other EDA vendor to use graph technology as part of its verification solution. There are a number of key differences between their approach and ours, but that’s the subject for another post.

The important point is that one of the Big Three EDA companies feels that graphs are important enough in the industry to warrant consideration for standardization. Last week Accellera held the first meeting of the PWG, and Breker actively participated. We don’t believe in publicly airing the internal workings of standards bodies, so this is not a report on that meeting but rather a public statement of our thoughts and position.

Since graphs are part of our lifeblood, we think it’s exciting that the industry is willing to consider them as a key enabling technology. As the title of the PWG shows, Accellera views graphs primarily as enablers of portable stimulus. To us, and we believe to the other PWG participants, this means stimulus and test cases that can be reused vertically from IP block to system and horizontally from virtual prototypes to simulation to hardware platforms.

Despite our excitement, we have two significant reservations about the proposed standardization effort. The first is Accellera’s assumption that a portable stimulus standard would subsume any graph-based verification standard. We believe that graphs are the best known vehicle for achieving vertical and horizontal reuse, but are open to whatever other technologies may be proposed to solve this challenge and agree that Accellera should consider them.

However, as noted earlier, reusability is just one of the positive attributes of using graphs for verification. Another is closed-loop coverage, leading to predictable coverage closure. What we don’t want to see is Accellera choosing a technology (graphs or otherwise) for portable stimulus and then forming another working group on coverage closure that might choose something entirely different. The PWG must keep all the benefits of graphs in mind when considering technologies for standardization.

Our second concern is that the timing of this group may be a bit early in the evolution of graph-based verification. Yes, we’ve been using graphs for more then ten years so it’s not some raw, unproven technology. But this technology continues to evolve at a rapid pace, and the cliche that premature standardization hinders innovation happens to be true. Cadence expressed similar concerns at a recent DVCon panel and in a followup article by Brian Bailey.

Take the example of graph specification syntax, the most obvious area for standardization. Over the last year, we have made big strides in reducing the amount of work needed to specify a Breker graph-based scenario model. Our syntax is now standard C/C++ with just a few small extensions; it’s not a new language at all. Standardizing the specification format a year ago would have clearly been too early; perhaps it still is if we continue innovation at a rapid pace.

As with any EDA standard, the bottom line is what the users want. Several semiconductor companies gave excellent presentations at the first PWG meeting and made a good case for why they would like to start Accellera working in this direction. So, despite our reservations, let’s make the Breker position clear. We will participate actively in the PWG. If the industry decides to form a Working Group, we will join Accellera and will continue to participate actively.

Finally, if Accellera issues a call for donations or contributions, we will submit our specification format for consideration. As the EDA industry’s pioneer and leader in graph-based verification, we owe our colleagues and customers our expertise to help find the best possible solution for standardization when the time is right.