Monthly Archives: November 2017

The BCD process technology has been around since the mid-eighties, but there has more recently been phenomenal interest and growth in BCD technology. This has been driven by the growing need in Power Management IC (PMICs), motor-control, power audio and many other applications targeting the consumer, industrial or automotive markets. The need for more intelligence embedded in these integrated circuits has led to the integration of MCUs and consequently of RAMs, with growing requirements for larger capacity.

Relying on robust, dense and low-power RAMs is pivotal for Fabless companies; the appraised single-port RAM RHEA compiler combines all three of these characteristics. Users of the TSMC 180 nm BCD Gen 2 process now benefit from the most competitive RAM. Thanks to its innovative architecture, the density of RAMs has improved by up to 30% and dynamic power consumption savings can reach up to 50%. Furthermore, the single-port RAM RHEA compiler supports multiple power saving modes, thus reducing static power consumption by up to 8 times in minimum data retention mode, as low as 1.0 V, compared to stand-by mode.

A SpRAM RHEA instance of 2kx32 is as dense as 0,342 mm2 and features a dynamic power consumption as low as 65,27 uA/MHz, with a leakage current reduced down to 1,6 uA. SoC designers targeting the TSMC 180 nm BCD Gen 2 process now benefit from a ready-to-use compiler to instantiate RAMs between 256 bits and 328 kbits. Multiple form factors are supported to ease SoC integration. The memory compiler provides all views needed for a fast and smooth SoC integration including for BIST support.

“This new RAM compiler for the TSMC 180 nmBCD Gen 2 process relies on our robust RHEA architecture,” says Frederic POULLET, Business Operations Manager for memories at Dolphin Integration. “The SpRAM RHEA has benefited from our stringent qualification process and is silicon proven in numerous processes down to 55 nm, in various variants such as uLP, uLPeF, LP, LP eF and HV. The BCD process technology is a perfect example of the relentless innovation that drives the semiconductor industry in terms of application, design and process technology. Driven by markets that did not exist some years ago and the increasing interest from SoC designers for its impact on power loss, cost and board space, the demand for the TSMC 180 nm BCD Gen 2 process has exploded in recent times. We are very excited to contribute to this trend.”

Dolphin Integration contributes to “enabling low-power Systems-on-Chip” for worldwide customers – up to the major actors of the semiconductor industry – with high-density Silicon IP components best at low-power consumption.

“Foundation IPs” includes innovative libraries of standard cells, register files and memory generators as well as an ultra-low power cache controller. “Fabric IPs” of voltage regulators, Power Island Construction Kit and their control network MAESTRO enable to safely implement low-power SoCs with the smallest silicon area. They also star the “Feature IP”: from ultra-low power Voice Activity Detector with high-resolution converters for audio and measurement applications to power-optimized 8 or 16 and 32 bit micro-controllers.

Over 30 years of experience in the integration of silicon IP components, providing services for ASIC/SoC design and fabrication with its own EDA solutions, make DOLPHIN Integration a genuine one-stop shop addressing all customers’ needs for specific requests.

It is not just one more supplier of Technology, but the provider of the DOLPHIN Integration know-how!

If you were uncertain about the term “FlipChip” this tutorial will help you better understand what FlipChip packaging technology is all about.

FlipChip package technology has been around for 3-4 decades and started as a package solution for high pin count & high performance package requirements. At the beginning, the majority of FlipChip package applications were higher pin count SoCs (consisting of more than 700 pins), which a typical Wire-Bond BGA package type could not handle properly. In addition, some SoCs incorporated high speed interfaces (including RF) that wirebonds could not support due to the high wire inductance.

The demand for FlipChip package increased during the last decade and was driven by the mobile market, where package size and signal performance are critical.

Today, FlipChip package technology offer a range of benefits including: high pin count, high signal density, better power dissipation, low signal inductance, and good power/ground connectivity. FlipChip packages are quite popular today and you can find them in small devices such as cell phones where space is at a premium.

Figure 1: FlipChip Cross Section

Essentially, the name “FlipChip” describes the method used to connect a semiconductor die to a substrate. In a FlipChip package the dies are bumped and then “flipped” onto a substrate, hence the name “FlipChip”.

Thanks to the fact that the bumps are distributed across the entire the chip and not only located on the die edge, pads can be placed all over the surface of the die. This allows designers to place more pads per die, reduce the chip size, and optimize signal integrity.

The substrate provides the connectivity to the external PCB via solder balls. The substrate size, number of layers and material properties have direct impact on the total package cost. In some cases the substrate can be the most expensive element in a FlipChip package.

The bumps are placed directly on the I/Os pads and thereby connect the die to the substrate. Following the bumping process, the wafer is diced and finally, the bumped die is “flipped” on the substrate. The bumps connect the die and the substrate together into a single package.

Substrate Technology

FlipChip substrate is a small PCB located inside the package and is very similar to any other PCB. The difference is that the substrate size is much smaller than most of the PCBs you have seen.

Substrate design consists of layout of all signals from the package external balls to the bump pads.

Substrates can be made by different materials: laminate, build-up, ceramic and more. Substrate layout design rules varies from different suppliers.

Substrates can consist of many layers ranging from 2-18 layers to allow routing of all signals.

Wafer Bumping Technology

Wafer bumps provide the connectivity between the die and the substrate by offering low inductance, low resistance and reliable and high quality production.

Wafer bumps can be composed from eutectic, lead tin, lead free, high lead materials, or Cu pillar. The bump size and bump pitch vary between the different assembly houses.

FlipChip Assembly Process

During the final processing step of the wafer bumping, the bumps are placed on the pads of the chip which can be found on the wafer’s top side. . In order for the chip to be connected or mounted to a substrate, the die is turned or flipped over and brought into alignment with the pads located on the substrate.

Figure 2: Steps in FlipChip Production

There are 6 steps in the process of creating a FlipChip which provides it with substantial versatility when connecting devices.

FlipChip Pros and Cons

There are advantages and disadvantages to FlipChip package, starting with the assembly method which creates a much smaller chip compared to previous wirebond solutions. Because the chip is directly connected to the circuitry board, the wires are shorter which creates less inductance. This means that devices can now pass signals at significantly higher speeds while dissipating heat more efficiently.

For the first time since 1993, the semiconductor industry is expected to witness a new number 1 supplier. Samsung first charged into the top spot in 2Q17 and displaced Intel, which had held the number 1 ranking since 1993. In 1Q16, Intel’s sales were 40% greater than Samsung’s, but in just over a year’s time, that lead has been erased. Intel is now expected to trail Samsung in the full-year 2017 semiconductor sales ranking by $4.6 billion. Samsung’s big increase in sales this year has been primarily driven by an amazing rise in DRAM and NAND flash average selling prices.

In 1993, Intel was the number 1 ranked supplier with a 9.2% share of the worldwide semiconductor market (Figure 1, which does not include the pure-play foundries). In 2006, Intel still held the number 1 ranking with an 11.8% share. In 2017, Intel’s sales are expected to represent 13.9% of the total semiconductor market, down from 15.6% in 2016. In contrast, Samsung’s global semiconductor marketshare was 3.8% in 1993, 7.3% in 2006, 12.1% in 2016, and forecast to be 15.0% in 2017. Thus, it appears that Samsung’s accession to the number 1 position in the semiconductor sales ranking this year has had more to do with Samsung gaining marketshare than Intel losing marketshare.

For 2017, the top 10 sales leaders are forecast to hold a 58.5% share of the worldwide semiconductor market. If this occurs, this would be the largest share of the market the top 10 companies held since 1993.

Memory giants SK Hynix and Micron are expected to make the biggest moves in the top-10 ranking in 2017 as compared to the 2016 ranking. Spurred by the surge in the DRAM and NAND flash markets, each company is forecast to move up two spots in the top-10 ranking with SK Hynix occupying the third position and Micron moving up to fourth.

Figure 1: Top 10 Worldwide Semiconductor Sales Leaders 1993-2017

Excluding foundries, there is expected to be one new entrant into the top-10 ranking in 2017—U.S.-headquartered Nvidia, which is forecast to register a 44% increase in sales this year. Nvidia is expected to replace fabless supplier MediaTek, whose 2017/2016 sales are expected to be down by 11% to $7.9 billion.

Six of the top-10 companies are expected to have sales of at least $17.0 billion in 2017. As shown, it is forecast to take $9.2 billion in sales just to make it into this year’s top-10 semiconductor supplier list. It should be noted that if Qualcomm and NXP’s expected sales for this year were combined, as if Qualcomm’s pending acquisition had already occurred, the companies’ 2017 sales would be $26.3 billion, enough to place the combined entity into third place in the top 10 ranking. Moreover, Broadcom’s current attempt to acquire Qualcomm, while Qualcomm itself is in the process of attempting to acquire NXP, adds additional uncertainty with regard to the future top 10 ranking.

As would be expected, given the possible acquisitions and mergers that could/will occur over the next couple of years (e.g., Qualcomm/NXP, Broadcom/Qualcomm/NXP, etc.), as well as any new ones that may develop, the top-10 semiconductor ranking is likely to undergo some significant changes over the next few years as the semiconductor industry continues along its path to maturity.

To review additional information about IC Insights’ new and existing market research reports and services please visit our website: www.icinsights.com.

Siemens has entered into an agreement to acquire Saskatoon, Canada-based Solido Design Automation Inc., a leading provider of variation-aware design and characterization software to semiconductor companies worldwide. Solido’s machine learning-based products are currently used in production at over 40 major companies, enabling them to design, verify, and manufacture more competitive products than ever before. The acquisition of Solido further expands Mentor’s analog/mixed-signal (AMS) verification portfolio to help customers address the growing challenges of IC design and verification for automotive, communications, data-center computing, networking, mobile, and IoT applications. The terms of the transaction are not disclosed. Siemens expects to close the transaction in early December 2017.

“With the acquisition of Mentor we made a large commitment to EDA,” said Tony Hemmelgarn, president and CEO of Siemens PLM Software. “This new acquisition of Solido strengthens that presence and demonstrates our commitment to serving our customers in the IC industry.”

“Solido has become an invaluable partner helping our customers address the impact of variability to improve IC performance, power, area, and yield,” said Amit Gupta, founder, president and CEO of Solido Design Automation. “Combining our technology portfolio with Mentor’s outstanding IC capabilities and market reach will allow us to provide world-class solutions to the semiconductor industry on an even larger scale. We are also excited to contribute to Siemens’ broader digitalization strategy with our applied machine learning for engineering technology portfolio and expertise.”

Variation-aware design and characterization has become fundamental in developing modern semiconductor products with the best possible power, performance, and cost. When analog, mixed-signal, memory, and standard cell circuits are designed for today’s complex applications, the verification software needs to deliver very high confidence in the simulation results while avoiding time- and resource-intensive analysis methods. Solido’s proprietary machine learning-based, variation-aware design and characterization software is proven to deliver the required confidence while significantly reducing time and resources and delivering unrivaled data visualization.

“The combination of Solido and Mentor’s leading analog-mixed-signal circuit verification products creates the industry’s most powerful portfolio of solutions for addressing today’s IC circuit verification challenges,” said Ravi Subramanian, vice president and general manager of Mentor’s IC verification solutions division. “Solido joins Mentor at an exciting time. Having a power house like Siemens entering EDA is proving to be a true game changer for us.”

Siemens PLM Software, a business unit of the Siemens Digital Factory Division, is a leading global provider of software solutions to drive the digital transformation of industry, creating new opportunities for manufacturers to realize innovation. With headquarters in Plano, Texas, and over 140,000 customers worldwide, Siemens PLM Software works with companies of all sizes to transform the way ideas come to life, the way products are realized, and the way products and assets in operation are used and understood. For more information on Siemens PLM Software products and services, visit www.siemens.com/plm.

Siemens AG (Berlin and Munich) is a global technology powerhouse that has stood for engineering excellence, innovation, quality, reliability and internationality for 170 years. The company is active around the globe, focusing on the areas of electrification, automation and digitalization. One of the world’s largest producers of energy-efficient, resource-saving technologies, Siemens is a leading supplier of efficient power generation and power transmission solutions and a pioneer in infrastructure solutions as well as automation, drive and software solutions for industry. The company is also a leading provider of medical imaging equipment – such as computed tomography and magnetic resonance imaging systems – and a leader in laboratory diagnostics as well as clinical IT. In fiscal 2017, which ended on September 30, 2017, Siemens generated revenue of €83.0 billion and net income of €6.2 billion. At the end of September 2017, the company had around 372,000 employees worldwide. Further information is available on the Internet at www.siemens.com.

Solido Design Automation Inc. is a leading provider of variation-aware design and characterization software to technology companies worldwide, enabling them to design, verify, and manufacture more competitive products than ever before. Solido’s products are currently used in production at over 40 major companies. Solido ML Labs makes Solido’s machine learning technologies and expertise available to semiconductor companies in developing new software products. The privately held company is venture capital funded and has offices in the USA, Canada, Asia and Europe. Further information is available on the Internet at www.solidodesign.com.

Since its invention in the `60s, integrated circuit development has seen an aggressive and cyclic pace for improvement pushed by specific disruptive applications. These once were military/aerospace, mainframe computer, minicomputer, personal computers, networking, mobile and more recently smartphones. The traditional approach has always been to make the most out of digital and support it, when needed, with analog submodules. This resulted in “Small-A Big-D” devices, which could profit the most from Moore’s Law: highest-performance computing on cutting-edge process nodes, low cost-per-function and high production volume, to name a few. Some current and future hot applications will keep being pushed and enabled by Moore’s law, such as Augmented/Virtual Reality (AR/VR), Artificial Intelligence (AI – Machine Learning and Deep Learning), and Big Data. However, the most discussed topic today, specially inside the semiconductor environment, differs a bit. Internet of Things (IoT) is the next big wave that will drive the Semiconductor Industry to the next level. Plus, what is going to make this revolution possible is More than Moorerather than Moore’s law. In fact, IoT’s edge nodes invariably will consist of “Big-A Small-D” devices and there are some reasons for it.

Internet of Things (IoT)

Internet of Things is not a single market, but a collection of markets and applications that intend to connect ‘things’ to the cloud. It may involve end-users, industrial equipment or environmental monitoring, for instance, but all applications gather some common technical and business requirements. A complete IoT solution will, in general, require a cloud structure of servers and services, a broad number of edge nodes and a gateway that connects these to the cloud. Fortunately these three elements may be developed independently once standards are created – and they have been already discussed for a while now –, which enriches the design ecosystem and gives more opportunity to small and medium-sized businesses. Among those three elements, the most interesting for hardware companies is definitely the IoT edge node, for being pervasive and more susceptible to innovation.

Making a long technical story short, an IoT end node must have means to read something from the environment, process that information, store it and communicate it to the cloud. Nevertheless, everything must be executed securely and efficiently in terms of power consumption. All these features demand a broad expertise in IC design, including digital, analog and RF. Moreover, ultra low power design capabilities become crucial for long life span edge nodes, which is the case of most applications. [Read more…]

About Chipus

Chipus Microelectronics is a semiconductor company focused in the development of low-power, low-voltage, analog and mixed-signal intellectual property (IP) blocks for integrated circuits (ICs) and systems on chip (SoCs).

Relying on a strong experience in power management and data converters, the company has more than 150 IP blocks in process nodes from 40nm to 0.35um of various foundries. Since its foundation in 2008, Chipus has licensed such IPs and provided associated IC design services with firm commitment and flexible client support to customers worldwide (North and South America, Europe, and Asia).

Headquartered in Florianópolis, Brazil, Chipus has a US subsidiary in Silicon Valley and sales teams in both USA and Europe.

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that it has acquired nusemi inc, a company focused on the development of ultra-high-speed Serializer/Deserializer (SerDes) communications IP.

nusemi, a technology-leading startup with industry veteran leaders, is developing next-generation SerDes technologies that will complement Cadence’s existing SerDes solutions. These high-speed SerDes solutions will provide significant value to the hyperscale datacenter, edge computing, networking, and telecom segments by enabling very high bandwidth and efficient solutions with reduced power consumption and cost.
IP is a critical element of Cadence’s System Design Enablement strategy, with a focus on enterprise (HPC, datacenter, networking/edge computing, and storage), mobility, and automotive applications at the most advanced FinFET nodes. nusemi’s ultra-high-speed SerDes technology is highly complementary to Cadence’s strengths in memory, storage, interconnect and digital signal processing (DSP) IP.
“The demands of cloud services and high-performance computing require continued innovation to deliver faster, denser and longer reach connectivity at ever-increasing speeds,” said Babu Mandava, senior vice president and general manager of the IP Group at Cadence. “The nusemi team brings strong SerDes expertise, and their innovative architecture is well-positioned to meet those needs. We welcome nusemi’s talented team to Cadence.”
“nusemi is focused on providing a high-speed connectivity solution at new levels of power efficiency to enable the next generation of hyperscale data centers,” said Stefanos Sidiropoulos, co-founder and CEO of nusemi inc. “The synergy between the Cadence IP strategy and nusemi’s technology plus the combination of our talented teams will accelerate the delivery of our high-speed SerDes offering at the most advanced process nodes. We are excited to join Cadence to further our original vision.”
The transaction is not expected to have a material impact on Cadence’s fiscal 2017 operational results. Terms of the transaction were not disclosed.About CadenceCadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine’s 100 Best Companies to Work For. Learn more at www.cadence.com.