MC68HC711E20CFN2 Summary of contents

MC68HC11E Family Technical Data Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any ...

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Pin Descriptions 2.2 Introduction M68HC11 E-series MCUs are available packaged in: • • • • • • Most pins on these MCUs serve two or more functions, as described in the following paragraphs. Refer to Figure assignments for the PLCC/CLCC, ...

Pin Descriptions Figure 2-5. Pin Assignments for 48-Pin DIP (MC68HC811E2) 2.3 V and Power is supplied to the MCU through V supply, V power supply. Low-voltage devices in the E series operate at 3.0–5.5 volts. Very fast ...

Pin Descriptions 2.4 RESET A bidirectional control signal, RESET, acts as an input to initialize the MCU to a known startup state. It also acts as an open-drain output to indicate that an internal failure has been detected in either ...

Crystal Driver and External Clock Input (XTAL and EXTAL) These two pins provide the interface for either a crystal or a CMOS- compatible clock to control the internal clock generator circuitry. The frequency applied to these pins is four ...

Pin Descriptions 2.6 E-Clock Output ( the output connection for the internally generated E clock. The signal from E is used as a timing reference. The frequency of the E-clock output is one fourth that of the input ...

There should be a single pullup resistor near the MCU interrupt input pin (typically 4 There must also be an interlock mechanism at each interrupt source so that the source holds the interrupt line low until the MCU ...

PA7 can function as general-purpose I timer output compare for OC1. PA7 is also the input to the pulse accumulator, even while functioning as a general-purpose I OC1 output. PA6–PA4 serve as either general-purpose outputs, timer ...

A 15 3.3.1 Accumulators A, B, and D Accumulators A and B are general-purpose 8-bit registers that hold operands and results of arithmetic calculations or data manipulations. For some instructions, these two accumulators are treated as a single double-byte ...

Central Processor Unit (CPU) When an interrupt is recognized, the current instruction finishes normally, the return address (the current value in the program counter) is pushed onto the stack, all of the CPU registers are pushed onto the stack, and ...

Central Processor Unit (CPU) 3.3.6.4 Negative (N) The N bit is set if the result of an arithmetic, logic, or data manipulation operation is negative (MSB = 1). Otherwise, the N bit is cleared. A result is said to be ...

Central Processor Unit (CPU) A 4-page opcode map has been implemented to expand the number of instructions. An additional byte, called a prebyte, directs the processor from page 0 of the opcode map to one of the other three pages. ...

Direct In the direct addressing mode, the low-order byte of the operand address is contained in a single byte following the opcode, and the high-order byte of the address is assumed to be $00. Addresses $00–$FF are thus accessed ...

Central Processor Unit (CPU) 3.6.6 Relative The relative addressing mode is used only for branch instructions. If the branch condition is true, an 8-bit signed offset included in the instruction is added to the contents of the program counter to ...

Operating Modes and On-Chip Memory 4.2 Introduction This section contains information about the operating modes and the on-chip memory for M68HC11 E-series MCUs. Except for a few minor differences, operation is identical for all devices in the E series. Differences ...

Expanded Mode In expanded operating mode, the MCU can access the full 64-Kbyte address space. The space includes: • • The expansion bus is made up of ports B and C, and control signals AS (address strobe) and R/W ...

Operating Modes and On-Chip Memory 4.3.4 Bootstrap Mode When the MCU is reset in special bootstrap mode, a small on-chip read-only memory (ROM) is enabled at address $BF00–$BFFF. The ROM contains a bootloader program and a special set of interrupt ...

Refer to Figure Use of an external pullup resistor is required when using the SCI transmitter pin because port D pins are configured for wired-OR operation by the bootloader. In bootstrap mode, the ...

Operating Modes and On-Chip Memory 4.4.1 RAM and Input/Output Mapping Hardware priority is built into RAM and I/O mapping. Registers have priority over RAM and RAM has priority over ROM. When a lower priority resource is mapped at the same ...

The bootloader program is contained in the internal bootstrap ROM. This ROM, which appears as internal memory space at locations $BF00–$BFFF, is enabled only if the MCU is reset in special bootstrap mode. In expanded modes, the ROM/EPROM/OTPROM (if present) ...

Operating Modes and On-Chip Memory 4.4.2 Mode Selection The four mode variations are selected by the logic states of the MODA and MODB pins during reset. The MODA and MODB logic levels determine the logic state of SMOD and the ...

System Initialization Registers and bits that control initialization and the basic operation of the MCU are protected against writes except under special circumstances. Table 4-2 must be written within the first 64 cycles after reset. Table 4-2. Write Access ...

Operating Modes and On-Chip Memory 4.4.3.1 System Configuration Register The system configuration register (CONFIG) consists of an EEPROM byte and static latches that control the startup configuration of the MCU. The contents of the EEPROM byte are transferred into static ...

Address: Read: Write: Resets: Single chip: Bootstrap: Expanded: U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch prior to reset, but the function of COP is controlled by the ...

ROMON — ROM/EPROM/OTPROM Enable Bit When this bit is 0, the ROM or EPROM is disabled and that memory space becomes externally addressed. In single-chip mode, ROMON is forced enable ROM/EPROM regardless of the state of the ...

Operating Modes and On-Chip Memory REG[3:0] — 64-Byte Register Block Position These four bits specify the upper hexadecimal digit of the address for the 64-byte block of internal registers. The register block, positioned at the beginning of any 4-Kbyte page ...

System Configuration Options Register The 8-bit, special-purpose system configuration options register (OPTION) sets internal system configuration options during initialization. The time protected control bits, IRQE, DLY, and CR[1:0], can be written only once after a reset and then they ...

As described in the following subsections, these two methods of programming and verifying EPROM are possible: • • 4.5.1 Programming an Individual EPROM Address In this method, the MCU programs its own EPROM by controlling the PPROG register (EPROG in ...

Operating Modes and On-Chip Memory 4.5.2 Programming the EPROM with Downloaded Data When using this method, the EPROM is programmed by software while in the special test or bootstrap modes. User-developed software can be uploaded through the SCI or a ...

Operating Modes and On-Chip Memory ERASE — Erase Mode Select Bit Refer to EELAT — EEPROM Latch Control Bit Refer to EPGM — EPROM/OTPROM/EEPROM Programming EPGM can be read any time and can be written only when ELAT = 1 ...

ELAT — EPROM/OTPROM Latch Control Bit When ELAT = 1, writes to EPROM cause address and data to be latched and the EPROM/OTPROM cannot be read. ELAT can be read any time. ELAT can be written any time except when ...

Operating Modes and On-Chip Memory PGM — EPROM Programming Voltage Enable Bit PGM can be read any time and can be written only when ELAT = 1. 4.6 EEPROM Some E-series devices contain 512 bytes of on-chip EEPROM. The MC68HC811E2 ...

CSEL on-chip resistor-capacitor (RC) oscillator is used. The EEPROM programming voltage power supply voltage to the EEPROM array is not enabled until there has been a write to PPROG with EELAT set and PGM cleared. ...

EPROM and EEPROM Programming Control Register The EPROM and EEPROM programming control register (PPROG) selects and controls the EEPROM programming function. Bits in PPROG enable the programming voltage, control the latching of data to be programmed, and select the ...

EEPROM Bulk Erase This is an example of how to bulk erase the entire EEPROM. The CONFIG register is not affected in this example. 4.6.1.4 EEPROM Row Erase This example shows how to perform a fast erase of large ...

Operating Modes and On-Chip Memory 4.6.1.5 EEPROM Byte Erase This is an example of how to erase a single byte of EEPROM. BYTEE 4.6.1.6 CONFIG Register Programming Because the CONFIG register is implemented with EEPROM cells, use EEPROM procedures to ...

Resets and Interrupts 5.7 5.7.1 5.7.2 5.2 Introduction Resets and interrupt operations load the program counter with a vector that points to a new location from which instructions are to be fetched. A reset immediately stops execution of the current ...

Power-On Reset (POR) A positive transition on V used only for power-up conditions. POR cannot be used to detect drops in power supply voltages. A 4064 t the oscillator becomes active allows the clock generator to stabilize. If RESET ...

Resets and Interrupts 5.3.3 Computer Operating Properly (COP) Reset The MCU includes a COP system to help protect against software failures. When the COP is enabled, the software is responsible for keeping a free-running watchdog timer from timing out. When ...

Resets and Interrupts Special considerations are needed when a STOP instruction is executed and the clock monitor is enabled. Because the STOP function causes the clocks to be halted, the clock monitor function generates a reset sequence ...

CME — Clock Monitor Enable Bit This control bit can be read or written at any time and controls whether or not the internal clock monitor circuit triggers a reset sequence when the system clock is slow or absent. When ...

Central Processor Unit (CPU) After reset, the central processor unit (CPU) fetches the restart vector from the appropriate address during the first three cycles and begins executing instructions. The stack pointer and other CPU registers are indeterminate immediately after ...

Resets and Interrupts 5.4.4 Real-Time Interrupt (RTI) The real-time interrupt flag (RTIF) is cleared and automatic hardware interrupts are masked. The rate control bits are cleared after reset and can be initialized by software before the real-time interrupt (RTI) system ...

Serial Peripheral Interface (SPI) The SPI system is disabled by reset. The port pins associated with this function default to being general-purpose I/O lines. 5.4.9 Analog-to-Digital (A/D) Converter The analog-to-digital (A/D) converter configuration is indeterminate after reset. The ADPU ...

I bit in the CCR any associated local bits. Interrupt vectors are not affected by priority assignment. To avoid race conditions, HPRIO can be written only while I-bit interrupts are inhibited. 5.5.1 Highest Priority Interrupt ...

Interrupts The MCU has 18 interrupt vectors that support 22 interrupt sources. The 15 maskable interrupts are generated by on-chip peripheral systems. These interrupts are recognized when the global interrupt mask bit (I) in the condition code register (CCR) ...

Resets and Interrupts For some interrupt sources, such as the SCI interrupts, the flags are automatically cleared during the normal course of responding to the interrupt requests. For example, the RDRF flag in the SCI system is cleared by the ...

Non-Maskable Interrupt Request (XIRQ) Non-maskable interrupts are useful because they can always interrupt CPU operations. The most common use for such an interrupt is for serious system problems, such as program runaway or power failure. The XIRQ input is ...

Resets and Interrupts return address for the illegal opcode interrupt is the address of the first byte of the illegal opcode. Otherwise, it would be almost impossible to determine whether the illegal opcode had been one or two bytes. The ...

Resets and Interrupts 5.7.1 Wait Mode The WAI opcode places the MCU in wait mode, during which the CPU registers are stacked and CPU processing is suspended until a qualified interrupt is detected. The interrupt can be an external IRQ, ...

Because all clocks are stopped in this mode, all internal peripheral functions also stop. The data in the internal RAM is retained as long are unchanged by stop. Therefore, when an interrupt comes to restart the system, ...

Parallel Input/Output (I/O) Ports Port pin function is mode dependent. Do not confuse pin function with the electrical state of the pin at reset. Port pins are either driven to a specified logic level or are configured as high-impedance inputs. ...

Address: Read: Write: Reset: PORTCL is used in the handshake clearing mechanism. When an active edge occurs on the STRA pin, port C data is latched into the PORTCL register. Reads of this register return the last value latched into ...

Port E Port E is used for general-purpose static inputs or pins that share functions with the analog-to-digital (A/D) converter system. When some port E pins are being used for general-purpose input and others are being used as A/D ...

Parallel Input/Output (I/O) Ports Full handshake modes use port C pins and the STRA and STRB lines. Input and output handshake modes are supported, and output handshake mode has a 3-stated variation. STRA is an edge-detecting input and STRB is ...

Parallel I/O Control Register The parallel handshake functions are available only in the single-chip operating mode. PIOC is a read/write register except for bit 7, which is read only. Address: Read: Write: Reset: STAF — Strobe A Interrupt Status ...

Parallel Input/Output (I/O) Ports OIN — Output or Input Handshake Select Bit HNDS must be set to 1 for this bit to have meaning. PLS — Pulsed/Interlocked Handshake Operation Bit HNDS must be set to 1 for this bit to ...

Serial Communications Interface (SCI) transmitter and receiver are independent, but use the same data format and bit rate. All members of the E series contain the same SCI, with one exception. The SCI system in the MC68HC11E20 and MC68HC711E20 MCUs ...

Serial Communications Interface (SCI) 7.6.1 Idle-Line Wakeup To use the receiver wakeup method, establish a software addressing scheme to allow the transmitting devices to direct a message to individual receivers or to groups of receivers. This addressing scheme can take ...

Serial Communications Interface (SCI) 7.8 SCI Registers Five addressable registers are associated with the SCI: • • The SCI registers are the same for all M68HC11 E-series devices with one exception. The SCI system for MC68HC(7)11E20 contains an extra bit ...

Serial Communications Interface (SCI) TC — Transmit Complete Flag This flag is set when the transmitter is idle (no data, preamble, or break transmission in progress). Clear the TC flag by reading SCSR with TC set and then writing to ...

Serial Communications Interface (SCI) 7.9 Status Flags and Interrupts The SCI transmitter has two status flags. These status flags can be read by software (polled) to tell when the corresponding condition exists. Alternatively, a local interrupt enable bit can be ...

MC68HC(7)11E20. software has noticed the status indication. The software clearing sequence for these flags is automatic. Functions that are normally performed in response to the status flags also satisfy the conditions of the clearing sequence. ...

Serial Communications Interface (SCI) interrupt mask for TDRE. When TIE is 0, TDRE must be polled. When TIE and TDRE are 1, an interrupt is requested. The TC flag indicates the transmitter has completed the queue. The TCIE bit is ...

Serial Peripheral Interface (SPI) 8.4 SPI Transfer Formats During an SPI transfer, data is simultaneously transmitted and received. A serial clock line synchronizes shifting and sampling of the information on the two serial data lines. A slave select line allows ...

Clock Phase and Polarity Controls Software can select one of four combinations of serial clock phase and polarity using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects ...

Serial Peripheral Interface (SPI) 8.6.1 Master In/Slave Out MISO is one of two unidirectional serial data signals input to a master device and an output from a slave device. The MISO line of a slave device is ...

This sets the SS pin to act as a general-purpose output rather than the dedicated input to the slave select circuit, thus inhibiting the mode fault flag. The other three lines are dedicated to the SPI whenever the ...

Serial Peripheral Interface (SPI) A write collision error occurs if the SPDR is written while a transfer is in progress. Because the SPDR is not double buffered in the transmit direction, writes to SPDR cause data to be written directly ...

Serial Peripheral Interface (SPI) CPOL — Clock Polarity Bit When the clock polarity bit is cleared and data is not being transferred, the SCK pin of the master device has a steady state low value. When CPOL is set, SCK ...

Serial Peripheral Status Register Address: Read: Write: Reset: SPIF — SPI Interrupt Complete Flag SPIF is set upon completion of data transfer between the processor and the external device. If SPIF goes high, and if SPIE is set, a ...

Serial Peripheral Interface (SPI) 8.8.3 Serial Peripheral Data I/O Register The SPDR is used when transmitting or receiving data on the serial bus. Only a write to this register initiates transmission or reception of a byte, and this only occurs ...

Timing System 9.2 Introduction The M68HC11 timing system is composed of five clock divider chains. The main clock divider chain includes a 16-bit free-running counter, which is driven by a programmable prescaler. The main timer’s programmable prescaler provides one of ...

The COP watchdog clock input (E 2 counter chain. The COP automatically times out unless it is serviced within a specific time by a program reset sequence. If the COP is allowed to time out, a reset is generated, which ...

Timing System 9.4 Input Capture The input capture function records the time an external event occurs by latching the value of the free-running counter when a selected edge is detected at the associated timer input pin. Software can store latched ...

Writing to TI4/O5 has no effect when the TI4/O5 register is acting as IC4. 9.4.1 Timer Control Register 2 Use the control bits of this register to program input capture functions to detect a particular ...

Timing System 9.4.2 Timer Input Capture Registers When an edge has been detected and synchronized, the 16-bit free-running counter value is transferred into the input capture register pair as a single 16-bit parallel transfer. Timer counter value captures and timer ...

Timing System 9.5.2 Timer Compare Force Register The CFORC register allows forced early compares. FOC[1:5] correspond to the five output compares. These bits are set for each output compare that forced. The action taken as a result ...

Output Compare Mask Register Use OC1M with OC1 to specify the bits of port A that are affected by a successful OC1 compare. The bits of the OC1M register correspond to PA[7:3]. Address: Read: Write: Reset: OC1M[7:3] — Output ...

Timing System 9.5.4 Output Compare Data Register Use this register with OC1 to specify the data that stored on the affected pin of port A after a successful OC1 compare. When a successful OC1 compare occurs, a ...

Timer Counter Register The 16-bit read-only TCNT register contains the prescaled value of the 16-bit timer. A full counter read addresses the most significant byte (MSB) first. A read of this address causes the least significant byte (LSB) to ...

Timing System 9.5.6 Timer Control Register 1 The bits of this register specify the action taken as a result of a successful OCx compare. Address: Read: Write: Reset: OM[2:5] — Output Mode Bits OL[2:5] — Output Level Bits These control ...

Timing System 9.5.8 Timer Interrupt Flag 1 Register Bits in this register indicate when timer system events have occurred. Coupled with the bits of TMSK1, the bits of TFLG1 allow the timer subsystem to operate in either a polled or ...

Timing System 9.5.10 Timer Interrupt Flag Register 2 Bits in this register indicate when certain timer system events have occurred. Coupled with the four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either ...

Real-Time Interrupt (RTI) The real-time interrupt (RTI) feature, used to generate hardware interrupts at a fixed periodic rate, is controlled and configured by two bits (RTR1 and RTR0) in the pulse accumulator control (PACTL) register. The RTII bit in ...