Accessing via a multiplexer

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Description

Number of patent applications / Date published

710051000

Accessing via a multiplexer

38

20080222322

Structure for an Apparatus Configured to Implement Commands in Input/Output (IO) Hub - A design structure comprising a schematic structure of an apparatus configured to implement commands in an input/output (IO) hub comprising a programmable command generator having an input coupled to an external interface and an output providing commands. The programmable command generator selectively couples commands in a path between a front end of the IO hub and an IO hub logic address and command routing output.

09-11-2008

20140344487

Auto-Switching Interfaces to Device Subsystems - A method auto-switches interfaces between a client computer and subsystems in a device under management. A first output bus from a first subsystem is coupled to a client computer via a multiplexer, wherein the first subsystem is a subsystem from multiple system subsystems in the device under management. A hardware subsystem bus monitor monitors all output busses from the multiple system subsystems for a predetermined event on a bus. In response to the predetermined event being detected on a second output bus from a second subsystem in the device under management, the multiplexor decouples the first output bus from the client computer and couples the second output bus to the client computer.

11-20-2014

20100042761

Observing an internal link via a second link - In one embodiment, the present invention includes a method for selecting first data received in a first die of a multi-chip package (MCP) from a second die of the MCP via an intra-package link for output from a selector during a first clock period of a first clock signal, selecting second data transmitted from the second die to the first die for output from the selector during a second clock period, and transmitting the first and second data from the MCP via an external link. Other embodiments are described and claimed.

02-18-2010

20090307392

INTELLIGENT CABLE AND FLEXIBLE MULTIPLEXER - Embodiments of an intelligent cable and flexible multiplexer are taught herein. The cables and multiplexers can receive any brand or electronic gages using a variety of asynchronous or synchronous communication protocols and provide outputs according to a desired communication protocol, including USB and RS232.

12-10-2009

20100005202

DYNAMIC SEGMENT SPARING AND REPAIR IN A MEMORY SYSTEM - A communication interface device, system, method, and design structure for providing dynamic segment sparing and repair in a memory system. The communication interface device includes drive-side switching logic including driver multiplexers to select driver data for transmitting on link segments of a bus, and receive-side switching logic including receiver multiplexers to select received data from the link segments of the bus. The bus includes multiple data link segments, a clock link segment, and at least two spare link segments selectable by the drive-side switching logic and the receive-side switching logic to replace one or more of the data link segments and the clock link segment.

01-07-2010

20100332697

STORAGE DEVICE AND STORAGE DEVICE ASSEMBLY - A storage device includes a USB connector, a storage module, a first USB receiver, and a multiplexer. The USB connector is configured for connected to a computer. The storage module is configured for storing data. The first USB receiver is configured to receive a second storage device. The multiplexer is connected to the USB connector and the first USB receiver, and is capable of accessing the storage module, wherein the multiplexer is capable of accessing the storage module and the second storage device at the same time when the USB connector is connected to the computer and the second storage device is connected to the first USB receiver.

12-30-2010

20120017012

DEVICES, SYSTEMS, AND METHODS FOR MULTIPLEXING ONE OR MORE SERVICES AT A CUSTOMER PREMISES - Systems, devices, and methods for multiplexing one or more services are disclosed. Such systems and devices may have an architecture that includes communication interfaces, processors, storage devices, and software applications that generate virtual machines. Each of the virtual machines may receive a first set of service data for a service of the one or more services; process the first set of service data using the one or more software applications to generate a second set of service data and data instructions associated with the second set of service data; provides a service security function for the service; provide a service operating system; mine the first set of service data, including analytical information; and transmit the second set of service data and data instructions associated with the second set of service data to a display interface that may be a communication interface.

Method for Enhancing the Memory Bandwidth Available Through a Memory Module - A method for enhancing the memory bandwidth available through a memory module of a memory system is provided. The memory system includes a memory hub device integrated in a memory module. The memory system includes a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module. The memory system also includes a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module. In the memory system, the first set of memory devices are separate from the second set of memory devices. In the memory system, the first and second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces.

01-06-2011

20110022745

INTERFACING DEVICE AND METHOD, FOR EXAMPLE FOR SYSTEMS-ON-CHIP - An interface device, such as for a System-on-Chip (SoC) bus, transfers data from an input queue through an output to a target. The interface device includes a buffer network for buffering input data when the target is not available for receiving the data. A multiplexer switches between a first operating condition for directing to the target the data from the input queue, and a second operating condition for directing to the target the buffered data from the buffer network. A finite-state machine selectively switches the multiplexer between the first operating condition and the second operating condition based on an acknowledgement signal received from the target. This indicates the availability of the target for receiving the data.

01-27-2011

20090248918

METHOD AND SYSTEM FOR A USB ETHERTYPE TO TUNNEL USB OVER ETHERNET - Aspects of a method and system for USB Ethertype to tunnel USB over Ethernet are provided. In this regard, Ethernet frames comprising USB traffic may be identified via one or more headers in the Ethernet frames and the USB traffic may be processed according to the identification. In this regard, USB traffic and general Ethernet traffic may be multiplexed into egress frames based on the identification. Similarly, ingress Ethernet frames may be demultiplexed into USB traffic and general traffic based on the identification. Headers utilized to identify and/or route USB traffic and general traffic may comprise Ethertype and/or subtype fields. The subtype field may comprise information pertaining to a USB bus to which the traffic belongs and/or a version of the USB standard to which the traffic adheres.

10-01-2009

20100185795

DIGITAL VIDEO/AUDIO CAPTURE DEVICE AND METHOD THEREOF - In audio/video (AV) capture, two video streaming adapters (VSAs) receive an original input video signal and a compressed input video signal respectively to generate an uncompressed video streaming and a compressed video streaming respectively. The uncompressed video streaming and the compressed video streaming are transmitted to an external device by way of time division duplex. An interlock mechanism prevents concurrent transmission of the uncompressed video streaming and the compressed video streaming, so that the loss of real-time video streaming is reduced.

07-22-2010

20100312926

SWITCH FOR A TWO WAY CONNECTION BETWEEN A REMOVABLE CARD, A MOBILE WIRELESS COMMUNICATION DEVICE, OR A COMPUTER - A USB switching device can selectively connect between a removable card and a mobile wireless communication device and a computer. The removable card has a first port; the mobile wireless communicating device has a second port while the computer has a third port. The switching device comprises a first full duplex switch having an input and a first output and a second output, and a select port for switching the connection of the input to the first output and the connection of the input to the second output. The switching device further comprises a second full duplex switch having an input and a first output and a second output, and a select port for switching the connection of the input to the first output and the connection of the input to the second output. The switching device further comprises a third full duplex switch having an input and a first output and a second output, and a select port for switching the connection of the input to the first output and the connection of the input to the second output. The input of the first switch is connected to the first port. The input of the second switch is connected to the second port. The input of the third switch is connected to the third port. The first output of the first switch is connected to the second output of the second switch. The second output of the first switch is connected to the first output of the third switch. Finally, the first output of the second switch is connected to the second output of the third switch.

12-09-2010

20110022744

Storage Control Method and Related Storage Control Device for a Computer System - A storage control method for a computer system for automatically executing off line at a proper time includes a storage controller generating a command for accessing a storage device, receiving and transmitting the command through a port multiplier, and the port multiplier performing off line when a ready packet is not received from the storage device or the storage device is absent.

01-27-2011

20110040904

REMOTELY CONTROLLABLE SWITCH AND TESTING METHODS USING SAME - Apparatus, methods, systems, and computer-readable media are provided for remotely controlling the connection between a host computer and a multitude of connected devices. One apparatus described herein includes a multiplexer that has a host port for connection to a host computer, device ports for connection to the devices, and control lines. The multiplexer is operative to connect a device port to the host port based upon the status of the control lines. The apparatus further includes a controller connected to the multiplexer. The controller has an input interface and is operative to receive control data on the input interface that identifies a device port on the apparatus that should be connected to the host port. In response to receiving such control data, the controller is operative to place signals on the control lines that cause the multiplexer to connect the identified device port to the host port. The device port that is connected to the host port can be remotely selected by transmitting the appropriate data to the input interface of the controller.

APPARATUS AND METHOD FOR SUPPORTING EXTERNAL MEMORIES IN PORTABLE TERMINAL - An apparatus and method for supporting a plurality of external memories in a portable terminal are provided. The apparatus includes a first memory mounted in a first memory slot, a second memory mounted in a second memory slot, a control unit for creating a list of data items stored in at least one of the external memories and for outputting a command for selecting one of the external memories, and a switching unit for determining and selecting one of the external memories storing next data to reproduce during the reproduction of data included in the list, wherein the switching unit includes a multiplexer to which a command (CMD) interface for issuing a command to the selected external memory and a data (DAT) interface capable of reading/writing stored data are connected.

10-20-2011

20100180054

BLADE CENTER USB LOCKING - A computer-implemented method, system and computer program product for managing USB ports on blades in a blade center are presented. A set of remotely-transmitted instructions causes a multiplexer to physically disconnect one or more selected USB ports on a blade. In one embodiment, the same one or more selected USB ports are also software-disabled by a USB software-based controller.

CONTROL MODULE FOR COMMUNICAION NETWORKS AND METHOD FOR USING THE SAME - A control module for controlling a communication network includes a master control unit generating a master control signal and a master pulse signal, a slave control unit generating a slave control signal; and a switch unit electrically connected to the master control unit, the slave control unit, and the communication network. The switch unit includes a timer and a multiplexer. The timer receives the master pulse signal, generates a first selecting signal when the master pulse signal exists, or generates a second selecting signal when the master pulse signal stops. The multiplexer receives the master control signal, the slave control signal, and the first/second selecting signal, transmits the master control signal to the communication network when receiving the first selecting signal, or transmits the slave control signal to the communication network when receiving the second selecting signal.

02-23-2012

20120117283

ARRANGEMENT COMPRISING A FIRST SEMICONDUCTOR CHIP AND A SECOND SEMICONDUCTOR CHIP CONNECTED THERETO - A data communication method for semiconductor chips including transmitting load control data, pilot data and a transmission clock signal from a first semiconductor chip to one or more second semiconductor chips that are each coupled to one or more electrical loads, driving the electrical loads based on a timing defined by the load control data, deriving a transmission rate by dividing the transmission clock signal by a division factor prescribed by the pilot data, and transmitting diagnostic data at the transmission rate from the one or more second semiconductor chips to the first semiconductor chip.

05-10-2012

20090132734

Controller with Indirect Accessible Memory - A controller has an interface, a buffer memory, a first set of registers for accessing the buffer memory, a second set of registers independent from the first set of registers for accessing the buffer memory, and a control unit for decoding and executing buffer memory access commands received by the interface to access the buffer memory through either the first or second set of registers.

05-21-2009

20130007314

FIRST IN FIRST OUT DEVICE AND METHOD THEREOF - A FIFO device crossing a first and a second power domains is provided. The device comprises: a plurality of input registers belonging to the first power domain for receiving the input signal, and each of the input register having a first output; a first controller belonging to the first power domain for enabling the registers according to specific order and generating an initial signal; a multiplexer receiving the first outputs according to the specific order to generate a second output; a second controller belonging to second power domain, receiving the initial signal through an asynchronous interface and controlling the multiplexer to output second output; and an output register belonging to second power domain receiving the second output. First power domain operates according to a first clock signal. Second power domain operates according to a second clock signal. The first and second clock signals are asynchronous.

01-03-2013

20120260008

Method and Apparatus for Transferring Data - One embodiment of the invention comprises a non-transitory, tangible computer readable storage medium encoded with processor readable instructions to perform a method of transferring SDIO data. One method comprises buffering multiple IP packets to transfer from one of a SDCC host and a SDIO client to the other of the SDCC host and the SDIO client. A multiplexing header is attached to each of the multiple IP packets and one of at least one SDIO read command and at least one SDIO write command issued. The multiple IP packets are then transferred in a single SDIO transfer between the one of a SDCC host and a SDIO client to the other of the SDCC host and the SDIO client.

10-11-2012

20150067201

SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor device includes a data storage suitable for storing a training data for a training operation, a data bus inversion (DBI) calculator suitable for calculating DBI information for the training data input from the data storage through global transmission lines, generating a DBI flag signal based on the DBI information and outputting a DBI data, which is the training data inverted according to the DBI flag signal, in response to a DBI signal, a first multiplexer suitable for selectively outputting the training data input from the data storage through the global transmission lines or the DBI data to a first channel in response to a training signal and the DBI signal and a second multiplexer suitable for selectively outputting the training data input from the data storage through the global transmission lines or the DBI flag signal to a second channel.

03-05-2015

20130232286

OUTPUT INPUT CONTROL APPARATUS AND CONTROL METHOD THEREOF - An output input (I/O) control apparatus and a control method thereof are provided. The I/O control apparatus includes an interface control unit, a read-only memory, a random access memory, a multiplexer and a micro-process unit. The interface control unit is coupled to a memory apparatus through a bus, and the memory apparatus is external to the I/O control apparatus. The read-only memory stores judgment codes. The multiplexer is controlled by the micro-process unit to switch to the interface control unit, the read-only memory or the random access memory. When the bus is not busy, the micro-process unit can read data from the memory apparatus. When the bus is occupied and busy, the micro-process unit can read and execute codes from the read-only memory or the random access memory so as to avoid computer system instability or thermal damage.

MICROCONTROLLER - A microcontroller is disclosed, which includes a memory, a first storage unit, a plurality of second storage units, a multiplexer and a micro-controller unit (MCU). The first storage unit is for being written into with a first code. The second storage units are for being written into with a plurality of second codes. The multiplexer writes the first code and one of the said second codes into the memory according to a control signal so that the memory generates a system code. The MCU reads out the system code come from the memory to perform operations.

12-08-2011

20130145058

METHOD OF OPERATING A ROUTER - A router has multiple channel inputs and multiple channel outputs and a switch core for selectively connecting at least two of the channel outputs to respective channel inputs. Each channel output is connected to an output signal path containing a FIFO register and the router is configured so that first and second channel outputs are connected to a pair of channel inputs respectively. The router configuration is changed so that the first and second channel outputs are connected to first and second channel inputs respectively. The FIFO registers in the output signal paths of the first and second channel outputs are forced to equal fullness.

06-06-2013

20150032917

MULTIPLEXER FOR SIGNALS ACCORDING TO DIFFERENT PROTOCOLS - A multi-protocol multiplexer provides signals according to different protocols for accessing a storage subsystem to a connector, where the signals according to a first protocol are to be routed over a first subset of channels of an interconnect to the storage subsystem, and the signals according to a second protocol are routed over a second subset of channels of the interconnect.

01-29-2015

20100082857

SOLID STATE STORAGE DEVICE CONTROLLER WITH PARALLEL OPERATION MODE - Solid state storage devices and methods for operation of solid state storage devices are disclosed. In one such method, a master memory controller is comprised of a plurality of memory communication channels. At least one of the memory communication channels is used to communicate with one or more slave memory controllers. The master and slave memory controllers can operate in a parallel operation mode to communicate with a plurality of memory devices coupled to the memory communication channels of each memory controller.

DEVICE AND METHOD FOR WRITING/READING A MEMORY REGISTER SHARED BY A PLURALITY OF PERIPHERALS - A device and method for writing/reading a piece of data in/from a memory register shared by a plurality of peripherals, each peripheral having a peripheral clock signal, when two or more of the plurality of peripherals need to write/read such piece of data at the same time, the digital device including a central unit having the memory register and a bank of SL modules in signal communication with the central unit, the bank of SL modules being designed to write/read the piece of data. The bank of SL modules comprises a plurality of writing/reading modules whose priority value ranges between maximum and minimum priority values, each module being connected to a respective peripheral, the central unit includes a multiplexer in signal communication on the one hand with the plurality of writing/reading modules, and on the other hand with the memory register, each module comprises an arbitration cell, such that the first module is identified by the maximum priority value (Prmax′) and the other N−1 modules are identified by decreasing priority values, the central unit operating at a predetermined main clock frequency to write/read the piece of data in the memory register.

04-24-2014

20140115199

ELECTRONIC DEVICE AND SEMICONDUCTOR DEVICE - There is a need to alleviate or reduce crosstalk between bonding wires or wires in a device substrate. One selection configuration divides a multiplexed terminal group into three groups according to functions differently from another selection configuration that divides the multiplexed terminal group into two groups. A first multi-pin semiconductor device is configured such that the groups are successively arranged along one edge of the chip. The first semiconductor device connects with a second semiconductor device via a multiplexed terminal group. The multiplexed terminal group includes first through third interface terminal groups that differ from each other in signal input/output configurations.

04-24-2014

20100121994

STACKED MEMORY ARRAY - A memory subsystem, array controller, method, and design structure are provided for a stacked memory array. The memory subsystem includes an array controller and at least one memory array. The array controller includes a primary and secondary buffer interface to communicate with a memory controller via a cascade interconnected bus. The array controller also includes an array access controller to process memory access commands received via one of the primary and secondary buffer interfaces. The at least one memory array includes a memory cell array die separately packaged with respect to the array controller and coupled to the array controller in a stacked configuration via memory core data lines using through silicon vias (TSVs).

05-13-2010

20140359174

RECONFIGURABLE INSTRUCTION CELL ARRAY WITH CONDITIONAL CHANNEL ROUTING AND IN-PLACE FUNCTIONALITY - A reconfigurable instruction cell array is disclosed that includes an array of switch boxes. Each switch box within the array includes a set of I/O ports that are configured to receive a plurality of input channels from neighboring switch boxes in the array. Within a switch box, one of the I/O ports conditionally selects from the input channels received by the remaining I/O ports in the switch box to form a plurality of output channels to be driven to a neighboring switch box in the array.

12-04-2014

20140215104

Crosstalk Mitigation in On-Chip Interfaces - A system and method to reduce and/or eliminate crosstalk between various data paths of a data bus within integrated circuits (i.e., chips). The system and method can transmit both delayed and non-delayed data in respective transmission paths, store the delayed and non-delayed data upon receipt, and delay the reading of the delayed and non-delayed data from the storage unit to compensate for the delay implemented on the transmission of the delayed data.