A new algorithm for the multiplication of two n-bit numbers on the synchronouscomputation of partial sums of the two operands is studied. The new algorithm permitsefficient realization of the parallel multiplication using iterative arrays with multiplexeras one of its main component along with fU-adder. Multiplier arrays for the newtechnique and conventional array are constructed and simulated in P-Spice. This thesisinvestigates and compares the delays of multiplexer based array multiplier andconventional array multiplier. The new multiplier obtained has low circuit complexitypermitting high-speed operation and the interconnections of the cells are regular, wellsuited for VLSI redization,...,....-...,..tested for theQ1 PC1 bus cardBoth these projects mere sofixare des elopment efforts tonards contributing to dlfferentaspects of Roboucs and lZ1echatronics projects m the Controls and Roboucs Group..