In concert with his four panelists, Broadcom’s Ajat Hukkoo, Intel’s Ashu Bakhle, Samsung’s Hong Hao, and GlobalFoundries’ Luigi Capodieci, Kundu laid out qualitative motivations and quantitative guidelines for predicting how many re-spins can be expected when a design targets next-generation geometries.

Prof. Kundu began with an homage to the costs and challenges: “Chips are expensive to develop, the Spice models are expensive to develop, and the first-pass and second-pass models often are not working.”

It’s within this environment of uncertainty, Kundu said, that designers and their managers are having difficulty predicting how many re-spins will be needed to get things right, and thus budgets and schedules are equally unpredictable.

Ajat Hukkoo agreed: “At Broadcom, every time we migrated from one node to another, the partitioning [of the design] had to be re-evaluated for electrical considerations and costs.

“Then we [had to look at the] process characteristics and power leakage, because power profiles differ from node to node and may cause architectural changes. In particular, for SoC architectures built to new processes we had to rebuild structures, memories, and standard cells to [promote] power mitigation.

“In addition, the maturity of [the next] process has been an issue. How often have we in the product division received immature process [nodes] from foundries who are motivated by their competition to throw out processes prematurely?

“Meanwhile, our business demands that power be lower at every node and performance be higher, while the area maintains parity, and the schedule as well.”

Optimizing for those four metrics – power, performance, area, and schedule – requires solving a four-variable equation, Hukkoo said: “It takes knowledge and effort to figure it out, but the answer is never clear. Even with a coherent strategy, [developers] can expect approximately 2.5 revisions of the device before the vehicle will generate revenue.”

“Of course,” he added, “if the process is mature and without bugs, the cost is less, which is why the industry needs the foundries to provide processes that are better debugged to avoid shifting this validation burden onto the design team.”

Intel’s Ashu Bakhle elaborated: “Turning out silicon on advanced processes continues to get more expensive and throughput times are increasing, even as design evolution moves to system-based design and the pace of building IP blocks increases.

“The combination of these factors necessitates as few steppings as possible to get to market. One or two for all layers and a couple of metal-layer-only steppings is what’s economically desirable, but the design-process interaction continues to increase making this goal ever more challenging.

“[Therefore], we will have to depend on test chips to be part of the process, particularly as the environment becomes more complex and ties [together] changing structures and geometries, finFETs and stacking, lithography limits and the number of mask layers.”

Bakhle noted, “Design and architecture must now include SoCs, where software development is integral to chip design and launch cycles, and analog blocks and large fast digital blocks are all on the same chip. [A situation made even more complex] on the competitive side with multiple entrants using an increasingly mature IP ecosystem. In this environment, the cost driver becomes post-silicon validation.”

“Nonetheless,” he concluded, “there are motivations for moving to the next node in the cost per transistor, and power and performance considerations. But when you make the move, it’s product manufacturing and development costs that become important in time-to-market concerns.

“Ultimately, it’s about getting the right features to your customers as soon as possible, while [keeping an eye] on the costs.”

Samsung’s Hong Hao spoke next. “There is non-stop pressure today to adopt bleeding-edge process nodes,” he said, and then asked rhetorically if predicting how many re-spins are required in this environment is an art, a science, or just dumb luck?

“It’s probably a little of all three,” Hao acknowledged, “but hopefully I can make it more a science and less about luck.

“So, how many re-spins are required to hit your market and support a rapid production ramp? For trail blazers, it’s at least two to three. But today’s product reqs require early software, so early first silicon is valuable even if it doesn’t meet the product reqs.

“For followers who follow the trail blazers, however, with luck they may only require one or two re-spins. If there is no need to rush to the bleeding edge, always let the leading guys who are going before you do the hard work. That’s the real key to achieving minimum re-spins.”

Hao offered four succinct guidelines for making the move to advanced nodes:

1) Be sure these is good correlation between the PDKs and the actual process offered by the foundry.2) IP can come from many different sources, and with a variety of quality, so only use silicon-proven IP.3) Leave some margins, and don’t push too hard on the first few spins.4) The ability to target any process requires a close working relationship with the foundry. This is key to success.

Following the commentary from Broadcom, Intel, and Samsung, GlobalFoundries’ Luigi Capodieci found himself on the defensive.

“I carry the weight of speaking for all foundries,” he said. “How many re-spins should you expect in moving to advanced nodes? My answer is simple: Zero re-spins!

“But if there will be more than zero re-spins, then you do [need to ask] if advanced nodes still make sense. The answer requires looking at three different classes of advanced process nodes. Certainly the move makes sense down to 28 nanometers. There should be no re-spins at 28, because the PDK relationship to process is solid.

“The real problem is the transition to 20 and 14 nanometers, because double patterning [is required at those geometries]. In addition, finFETs are arriving at these nodes, and the introduction of EUV is delayed – again!”

Capodieci got a chuckle from the audience with this aside: “Of course, the joke about EUV is that it is always delayed until the next technology node.”

Continuing, he said, “Double patterning is a real technology, however, and is causing a disconnect in how we do thing, plus having profound implications in how we do design – of IP, in particular.

“There is [clearly] a design gap here, a patterning gap with the number of transistors which can be fabricated. [In addition] the number of unconstrained metal/via shapes needed in BEOL, [so we have to ask] designers: Can you actually use of these transistors today and figure out all of the [associated] interconnects?”

Capodieci said these are all legitimate concerns, but “GlobalFoundries is pioneering collaboration between the foundry and the designers” and progress is being made. Scaling will continue as a result of innovation in patterning and lithography, he said and concluded by advising moderation: “We suggest taking the middle path by redesigning your design-process interface together with your foundry.”

As soothing as that advice sounded, Broadcom’s Ajat Hukkoo reiterated to designers in the audience: “You should not go to immature process offered by your foundry. We have lost up to a year doing that – don’t do it!”

Capodieci would not settle for this final judgment. He retorted: “Even stable processes, when confronted with new designs or new IP placements, can have problems. [In that case], it’s not the foundry, it’s the experiment from the designers exploring new different corners of the design that is causing the problems.

“I’m not making excuses for the foundries, I’m just saying you have to use real products and real designs all the way to the process [to guarantee success].”

Capodieci ended on a sardonic note: “In the future for the foundries, rather than providing physical rules to the designers, perhaps we will just hand out the design?”