I have found two problems with the STR9 chip.
I am converting a project from the STR7 to the STR9.

On the STR7 I am using an SPI channel to drive an Audio DAC.
The SPI clk is also used to drive a timer input clock to generate a LeftRight clock for the audio DAC.
This all works correctly on the STR7.

Upon setting up the STR9 to do the same function I have 2 problems.

The SPI is set as a master with 16 bit data size.

On the STR7 data is clocked from the FIFO with no gaps between data frames.
On the STR9 there is a gap of around 2 SPI clocks between consecutive frames.

I have tried both DMA transfer data out, and also using the FIFO half
empty interrupt to refill the FIFO.
Both ways result in the same gap.

There is no mention in the data sheet, that I can find of this delay between transmits,
or in the current errata sheet
This is obviously a hardware issue.
If the STR7 can manage to output continous data, then surely the STR9
could also.

The second problem is with externally clocking the timer.
This problem has been mentioned before here

I am seeing the same problem. My timer is set to count SPI clocks and
toggle the output compare pin every 16 pulses.
However it is always out of sync, 6 pulses to late or possibly 10 pulses to soon.
Assuming the timer counter value is reset correctly the output compare pin
should toggle correctly on each 16 bit dataframe but this is not the case.

I do have a work around in that I can set the SPI CLK to a GPIO pin and
manually clock it until I see OCF2 bit in TIMx_SR is set,
then switch over to SPI mode, but I should not have to do this.
Again there is no such problem in the STR7.

Are these know issues ? If so why are they not mentioned in the datasheet or errata sheet.

Are there any plans to resolve these issues in future silicon revisions ?