G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Description

[0001]

The present invention relates to a semiconductor memory device, and more particularly, to a dynamic random access memory (DRAM).

[0002]

In a DRAM, the data is stored in a capacitor of a memory cell on the basis of whether or not there is a charge in the capacitor. Accordingly, the data must be refreshed to hold it in the capacitor, since the data will be lost with the elapse of time, due to a leakage of current from the capacitor.

[0003]

Therefore, a DRAM is set to operate in two modes, i.e. a read/write mode for reading or writing the data, and a refresh mode for refreshing the data. Although the operational speed of such a DRAM depends on the read/write and the refresh operational speeds at those modes, the timing of the refresh mode particularly can be an important factor in determining the operational speed of the DRAM.

[0004]

Accordingly, it is desirable to provide a dynamic random access memory having improved refresh timing, with a view to increasing the operational speed of the DRAM.

[0005]

According to the present invention, there is provided a dynamic random access memory comprising: a plurality of dynamic-type memory cells, arranged in rows and columns, for storing respective items of data; refresh control circuitry for causing the data in selected ones of those memory cells to be refreshed, when the memory is in a refresh mode, and including refresh address circuitry for generating refresh address signals denoting memory cells to be refreshed; and clock signal generating circuitry connected to receive row address strobe signals and column address strobe signals and operating in dependence thereon to generate a first clock signal, when a preset length of time has elapsed after receipt of a row address strobe signal , and to generate second and third clock signals in response to the said first clock signal, the said second clock signal being generated during a read/write mode of the memory and being delivered to addressing circuitry of the memory so as to cause that circuitry to latch an external address signal supplied thereto, and the said third clock signal being generated during the said refresh mode and being delivered to the said addressing circuitry, so as to cause that circuitry to latch a refresh address signal supplied thereto;
characterised in that the said clock signal generating circuitry includes signal modifying means including loading circuitry operative during the said refresh mode, said loading circuitry reducing the rate of change of an intermediate signal derived from the column address strobe signal and employed to determine the timing of the said third clock signal, thereby to cause the time delay between the said first and third clock signals, during the said refresh mode, to be greater than that between the said first and second clock signals during the said read/write mode.

[0006]

Reference will now be made, by way of example, to the accompanying drawings, in which:
Fig. 1 shows a circuit diagram of a clock generator previously considered by the present applicants;
Fig. 2 shows a circuit diagram of an address latch circuit and peripheral circuits previously considered by the present applicants;
Fig. 3 shows a timing chart for each clock signal of Fig. 1 during a read/write mode;
Fig. 4 shows a timing chart for each clock signal of Fig. 1 during a refresh mode;
Fig. 5 shows a chart for explaining timing of row and column address strobe signals in the read/write mode;
Fig. 6 shows a chart for explaining timing of row and column address strobe signals in the refresh mode;
Fig. 7 shows a circuit diagram of clock signal generating circuitry of a DRAM embodying the present invention;
Fig. 8 shows a circuit diagram of addressing circuitry of a DRAM embodying the present invention;
Fig. 9 shows a timing chart for each clock signal of Fig. 7 during a read/write mode;
Fig. 10 shows a timing chart for each clock signal of Fig. 7 during a refresh mode;
Fig. 11 shows a circuit diagram of clock signal generating circuitry of a further DRAM embodying the present invention;
Fig. 12 shows a circuit diagram of addressing circuitry of the further DRAM embodying the present invention;
Fig. 13 shows a timing chart for each clock signal of Fig. 11 during a read/write mode;
Fig. 14 shows a timing chart for each clock signal of Fig. 11 during a refresh mode; and
Fig. 15 shows a schematic block diagram of a DRAM embodying the present invention.

[0007]

Before describing the preferred embodiments, an explanation will be given of read/write and refresh timing in a DRAM previously considered by the present applicants.

The signals RAS and CAS are input from an external circuit of the DRAM to the input terminals 15 and 16 for setting the read/write mode and the refresh mode. The clocks ØA and ØL are generated from the RAS buffer 17 after a predetermined delay time. In this case, the delay time of the clock ØA is different from that of the clock ØL, as explained below. The clock ØB is obtained from a common node of the transistors TR2 and TR4, and the clock ØC is obtained from a common node of the transistors TR1 and TR3. That is, when the transistor TR2 is ON and the transistor TR4 is OFF, the clock øB is at a high level. When the transistor TR1 is ON and the transistor TR3 is OFF, the clock øC is at a high level as explained below.

[0010]

In Fig. 2, AL denotes an address latch circuit constituted by, for example, flip-flop circuits, and CU denotes a refresh address counter. N1 denotes a first input connection point (first node), and N2 a second input connection point (second node). Q1 to Q8 denote transistors constituting a peripheral circuit. An denotes an input address signal (TTL level) from an external stage (not shown), Qn a refresh address signal from the refresh address counter CU, Qn a complementary refresh address signal of the signal Qn , RAn a latched address signal (MOS level) from the address latch circuit AL, RAn a complementary latched address signal (MOS level) of the signal RAn , and Vrf a reference voltage level (approximately, 1.5 volts) generated from the internal circuit (not shown). The clocks øB, øC and øL are input from the clock generator shown in Fig. 1. In this case, the clock øL is used for activating the address latch circuit AL, the clock øB for controlling the input address signal An , and the clock øC for controlling the refresh address signals Qn and Qn.

[0011]

In the read/write mode, the charge of the node N1 is discharged in correspondence with the data of the external address signal An through the transistors Q1 and Q3 when the clock øB is high. The charge of the node N2 is discharged through the transistors Q6 and Q8. In this case, since the reference voltage Vrf is set to an intermediate level of an amplitude of the input address signal An , the discharge quantity of the node N2 is different from that of the node N1. As a result, the external address signal An can be taken into the address latch circuit AL.

[0012]

In the refresh mode, the charge of the node N1 is discharged in correspondence with the signal Qn from the refresh counter CU through the transistors Q2 and Q4 when the clock øC is high. The charge of the node N2 is discharged in correspondence with the signal Qn from the refresh counter CU through the transistors Q5 and Q7.

[0013]

With reference to Figs. 3 and 4, in which the ordinate V denotes voltage and the abscissa t denotes time, the row address strobe RAS and the column address strobe CAS are taken to be the respective trailing edges of the strobe signal waveform. The clock øA is obtained from the RAS buffer 17 and this clock is delayed by a predetermined delay time from the trailing edge of the signal RAS.

[0014]

The timing chart of Fig. 5 denotes the read/write mode, hereinafter called the "normal cycle", wherein tCRS denotes a set-up time of the signal CAS to signal RAS, and tRCD is a delay time between the signal RAS and the signal CAS.

[0015]

The timing chart of Fig. 6 denotes the refresh mode, hereinafter called the "CBR refresh cycle" where "CBR" means that the signal CAS is dropped from a high level to a low level before the signal RAS has dropped from a high level to a low level. In Fig. 6, tFCS denotes a set-up time of the signal CAS to the signal RAS for the refresh operation, and tFCH denotes a hold time of the signal CAS from the signal RAS for the refresh operation.

[0016]

In the normal cycle, the row address strobe signal RAS is changed from high level (H) to low level (L) when the row address signal is taken in from the external stage. At this time, the column address strobe signal CAS is held at the high level. In the CBR refresh cycle, the signal CAS is changed from high level to low level before the signal RAS is changed from high level to low level. This trailing timing of the signal CAS is detected in the clock generator shown in Fig. 1 and the generated clock øC is input to the transistors Q2 and Q5 shown in Fig. 2.

[0017]

The operations of the previously-considered normal cycle and the CBR refresh cycle are explained in detail hereinafter.

[0018]

Referring first of all to the normal cycle, in Fig. 3, the clock øA rises from low level to high level after a predetermined delay time from the trailing edge of the signal RAS. The clock øA is input to the transistors TR1 and TR2 shown in Fig. 1.

[0019]

In the normal cycle, since the signal CAS is high, the output of the inverter 18 is low so that the transistor TR4 is turned OFF and, since the output of the inverter 19 is high, the transistor TR3 is turned ON. Further, the transistor TR1 is turned OFF and the transistor TR2 is turned ON. Therefore, the clock øB is high and the clock øC is low. The clock øB is input to the transistors Q1 and Q6 shown in Fig. 2.

[0020]

In Fig. 2, the address latch circuit AL is constituted by, for example, flip-flop circuits as explained above. Therefore, the transistors Q1 to Q8 are provided for forming current paths to discharge the charge in the flip-flop circuits. As shown in the drawing, the node N1 is connected to the ground GND through either a first current path, consisting of the transistors Q1 and Q3, or a second current path, consisting of the transistors Q2 and Q4. Further, the node N2 is connected to the ground GND through either a third current path, consisting of the transistors Q5 and Q7, or a fourth current path, consisting of the transistors Q6 and Q8.

[0021]

When the clock øB is input to the transistors Q1 and Q6, these transistors are turned ON. The transistor Q3 is turned ON or OFF in correspondence with the high or low level of the input address signal An. In this case, when the transistor Q3 is turned ON, the charge of the node N1 is completely discharged to the ground GND. Since the reference voltage Vrf is set to an intermediate level between the high level and the low level at the input address signal An , the transistor Q8 is not completely turned ON so that the discharge quantity from the node N2 is smaller than that of the node N1. Consequently, when the transistor Q3 is completely turned ON, the node N1 is discharged and becomes low level. When the transistor Q3 is completely turned OFF, the node N1 is held at the high level. At this time, the node N2 is discharged and becomes low level since the transistor Q8 is turned ON at the intermediate state (i.e. incomplete turning ON state). As a result, the external address signal An is latched in the address latch circuit AL and the data based on the latched address signal is output in correspondence with the clock øL based on the row address signal RAn or the complementary signal RAn from the circuit AL.

[0022]

Referring now to the CBR refresh cycle, in this cycle the clock øC rises from low level to high level as shown in Fig. 4. That is, in Fig. 1, since the signal CAS is low, the output of the inverter 18 is high so that the transistor TR4 is turned ON. But, since the output of the inverter 19 is low, the transistor TR3 is turned OFF. Further, the transistor TR1 is turned ON and the transistor TR2 is turned OFF. Therefore, the clock øC is high and the clock øB is low.

[0023]

In Fig. 2, the clock øC is input to the transistors Q2 and Q5. Therefore, these transistors Q2 and Q5 are turned ON. The transistor Q4 is turned ON and the transistor Q7 is turned OFF when the refresh address signal Qn is high and the complementary refresh address signal Qn is low. Further, the transistor Q7 is turned ON and the transistor Q4 is turned OFF when the signal Qn is low and the signal Qn is high. The charge of the node N1 is discharged and becomes low level when the transistor Q4 is turned ON. The charge of the node N2 is discharged and becomes low level when the transistor Q7 is turned ON. Consequently, the refresh address signal from the counter CU is taken into the address latch circuit AL. The data based on the latched refresh address signal is output in correspondence with the clock øL based on the row address signal RAn and the complementary signal RAn.

[0024]

As shown in Fig. 6, it is necessary to drop the signal CAS from a high level to a low level before the signal RAS is dropped from a high level to a low level. Further, it is necessary to set the set-up time tFCS so that it is larger than the delay time caused by the inverters 18 and 19. In the normal cycle, it is necessary to raise the signal CAS from low level to high level before the signal RAS is dropped from high level to low level, as shown in Fig. 5. Approximately 10 to 20 nanoseconds are necessary for the set-up time tCRS.

[0025]

As is well-known, the row address strobe signal RAS is the earliest clock, based on the system operation speed. However, in the CBR refresh cycle, the column address strobe signal CAS must be input before the signal RAS is input. Therefore, some problems arise regarding this early input timing of the signal CAS. For example, it is not obvious whether or not the level of the CAS to be input is high in an initial state of a central processing unit (CPU). Therefore, a delay of approximately 50 nanoseconds occurs for inputting the signal CAS, since the signal CAS is input after determination by the CPU. Consequently, it is very difficult to achieve a high speed operation of the DRAM, owing to these delay times for the set-up time.

[0026]

A dynamic random access memory, having improved refresh timing, which embodies the present invention will be explained in detail hereinafter.

[0027]

In Fig. 7, INV 1 to INV 6 denote inverters. AND 1 to AND 3 denote AND gates. The signal RAS is delayed by a plurality of inverters INV 1 to INV 4 and the clock øA is obtained from the inverter INV 4. The inverters INV 1 to INV 4 correspond to the RAS buffer 17 shown in Fig. 1. However, in an embodiment of the present invitation, an inverted RAS signal (RAS) delayed by the inverters INV 1 to INV 2 is input to one input terminal of the gate AND 1. The signal CAS is inverted to an opposite level signal CAS in the other input terminal of the gate AND 1. Therefore, the signal CAS is obtained when the signal CAS is low. In this case, the signal RAS is always high. An internal clock øX is obtained by inverting the signal CAS. Therefore, the clock øC is obtained through the gate AND 2 when the clock øA and the signal CAS are high. The clock øB is obtained through the gate AND 3 when both clocks øA and øX are high. The clock øL is obtained through a NOR gate and the inverter INV 6, except when both clocks øB and øC are low. Further, many loads, for example, capacitive loads of other clock generators, are shown by a dotted line L. The gate AND 1 and the loading circuitry L together constitute signal modifying means. The signal CAS is sent to these loads so that the leading edge of the signal CAS becomes a gentle slope, as shown by a dotted line in Fig. 10. The present invention utilizes this gentle slope of the signal CAS. The operation of this circuit will be explained in detail hereinafter.

[0028]

In Fig. 8, Q9 to Q12 denote transistors. The external input address signal An is input to an input terminal 20. As is obvious from the drawing, the signals An , Vrf, Qn and Qn are input to either the source or the drain side of transistors Q₉ to Q₁₂ respectively. Conventionally, these signals are input to the gate side of each transistor as shown in Fig. 2. Therefore, each of transistors Q9 to Q12 is used only as a gate transistor. That is, the transistor Q9 is used for taking in the external address signal An when the clock øB is high in the normal cycle; the transistor Q10 is used for taking in the reference voltage Vrf when the clock øB is high in the normal cycle; the transistor Q11 is used for taking in the internal refresh address signal Qn when the clock ØC is high in the CBR refresh cycle; and the transistor Q12 is used for taking in the complementary refresh address signal Qn when the clock øC is high in the CBR refresh cycle.

[0029]

The operation of the circuits shown in Figs. 7 and 8 will be explained in detail with reference to Figs. 9 and 10.

[0030]

In the normal cycle shown in Fig. 9, the clock øB is generated from the gate AND 3 when both clocks øA and øX are high. That is, the signal CAS is high in the normal cycle, and the signal CAS generated from the gate AND 1 is low since the signal RAS is high. Therefore, the internal clock øX is high so that the clock øB is output from the gate AND 3, since the clock øA is high. In this case, the clock øC from the gate AND 2 is low, since the clock øA is high and the signal CAS is low. Therefore, the clock øL is output through the NOR gate and the inverter INV 6 when the clock øB is high.

[0031]

In the CBR refresh cycle shown in Fig. 10, the clock øC is generated from the gate AND 2 when the signal CAS and the clock øA are high. That is, the signal CAS is low in the CBR refresh cycle, and the signal CAS is high since the signal RAS is high. In this case, the clock øB is low, since the clock øA is high and the clock øX is low. Therefore, the clock øL is output through the NOR gate and the inverter INV 6 when the clock øC is high.

[0032]

As shown by a dotted line in the drawing, the starting point of the leading edge of the signal CAS is earlier than that of the clock øA. However, the time at which it is completely raised is later than that of the clock øA. That is, the leading edge of the signal CAS becomes a gentle slope caused by many loads. Therefore, the time when the clock øA and the signal CAS become high level is delayed so that the leading time of the clock øC depends on the leading edge of the signal CAS. This is because, as explained above, many loads, for example capacitive loads (see Fig. 7), are provided to the output of the gate AND 1 for utilizing the signal CAS.

[0033]

In an embodiment of the present invention, the difference of the leading time between the clock øB and the clock øC is utilized. That is, in the normal cycle shown in Fig. 9, the clock øB immediately rises since the internal clock øX is high because the signal CAS is low. But, in the CBR refresh cycle, the clock øC rises after the signal CAS is completely raised for the above explained reason, although the clock øA has already risen. Therefore, each of the gate transistors Q9 to Q12 shown in Fig. 8 is opened in correspondence with the input timing of these clocks øB and øC in the normal and the CBR refresh cycles.

[0034]

In Fig. 8, when the clock øB is input to the transistors Q9 and Q10 in the normal mode, these transistors are turned ON so that the external address signal An is input to the address latch circuit AL through the node N1 and the reference voltage Vrf is also input to the circuit AL through the node N2. The difference voltage between the signal An and the reference voltage Vrf is detected in the circuit AL and the row address signal RAn and the complementary row address signal RAn are output from the circuit AL in correspondence with the clock øL after this difference voltage is amplified. In this case, the clock øL is generated at the same timing in the normal and CBR refresh cycles, to obtain a stable operation of the circuit AL in these cycles.

[0035]

When the clock øC is input to the transistors Q11 and Q12 in the CBR refresh cycle, these transistors are turned ON so that the refresh address signal Qn and the complementary refresh address signal Qn are input to the circuit AL through the nodes N1 and N2. As a result, the latched row address signal RAn and the complementary signal RAn are output from the circuit AL.

[0036]

In an embodiment of the present invention, it is possible to set the refresh set-up time tFCS (see Fig. 6) so that it will become zero. That is, it is possible to set the same timing of the trailing edge between the signal RAS and the signal CAS as shown in Fig. 10. Further, it is possible to set the later timing of the trailing edge than the signal RAS. These are because the inverters 18 and 19 (see Fig. 1) are not provided in the clock generator shown in Fig. 7, since the timing of the clock øB is different from that of the clock øC. Consequently, it is possible to achieve a high speed operation of the system. As explained above, in the previously-considered clock generation shown in Fig. 1, the timing of the clock øB is the same as that of the clock øC, so that the inverters 18 and 19 are necessary. Therefore, it is necessary to set the refresh set-up time tFCS to a time sufficient to cover the delay time caused by these inverters 18 and 19 in the previously-considered clock generator.

[0037]

In Figs. 11 and 12, two CMOS (complementary metal oxide semiconductor) inverters are used in the clock generator, instead of the N-channel transistor used in the first embodiment shown in Fig. 7. In the case of a CMOS, the circuit can be operated by either a negative or a positive logic. But, in the case of the N-channel transistor, the circuit can be operated only by a positive logic. In general, the negative logic is better than the positive logic because the trailing operation of the signal is easier than the leading operation of the signal.

[0038]

In Fig. 11, AE denotes a delay signal delayed from the signal RAS, ALE a control signal for controlling generation of the clocks øB and øC, Q13 and Q15 P-channel MOS transistors, and Q14 and Q16 N-channel MOS transistors. The pair of transistors Q13 and Q14 and the pair of transistors Q15 and Q16 constitute respective CMOS inverters. The clock øA is obtained from the signal AE after a delay by inverters INV 7 and INV 8. This clock øA is input to the source of the transistors Q14 and Q16. The clock øB is obtained from a common node of the transistors Q13 and Q14, and the clock øC is obtained from a common node of the transistors Q15 and Q16. The clocks øB and øC are input to the NAND gate, to achieve a quick operation of the NAND gate.

[0039]

In Fig. 12, 21 denotes an address buffer comprising a NAND gate NAND 2 and an inverter INV 13. The address buffer 21 amplifies the external address signal An having a TTL level voltage to a clock AIn having a MOS level voltage in correspondence with the timing of the signal AE. The clock AIn is input to the address latch circuit AL and the complementary clock AIn inverted by the inverter INV 14 is also input to the address latch circuit AL.

[0040]

The operations of the circuits shown in Figs. 11 and 12 will be explained in detail with reference to Figs. 13 and 14.

[0041]

In the normal cycle shown in Fig. 13, initially the node N1 is high. When the signal AE is dropped from a high level to a low level, the clock øA also drops from a high level to a low level after a delay due to the two inverters INV7 and INV8. Therefore, the clock øB becomes low level since the clock øA is input to the source S of the transistor Q14. Further, when the signal ALE becomes high level after delay due to the inverters INV9 and INV10 and the gate NAND1, the node N1 becomes low level through the gate NOR and the clock øB becomes high level (not shown). In the circuit shown in Fig. 11, since the clock øB functions as "one shot pulse", only the curve from high level to low level is shown in Fig. 13.

[0042]

In the CBR refresh cycle shown in Fig. 14, initially the node N2 is low. However, since the signal CAS becomes high level before the signal AE becomes low level, the node N2 becomes high level and, then the node N1 becomes low level. Further, since the signal AE becomes low level, the clock øA also becomes low level so that the clock øC becomes low level through the source S of the transistor Q16. Further, since the signal ALE becomes high level, the node N2 becomes low level so that the clock øC becomes high level (not shown). In the circuit shown in Fig. 11, since the clock øC functions as "one shot pulse", only the curve from high level to low level is shown in Fig. 14.

[0043]

As is obvious from the above, when the node N1 is high, the clock øB is output, and when the node N2 is high, the clock øC is output, in correspondence with the timing of the clock øA. In this case, as explained above, the leading time of the signal CAS becomes a gentle slope, since many loads are connected in the path of the signal CAS.

[0044]

In Fig. 15, a MOS (metal oxide semiconductor) DRAM embodying the present invention comprises: a first clock generator 1 for generating clocks, for example øA, RAS, AE, etc.; a second clock generator 2A for generating clocks, for example, øB, øC, øL, ALE, etc. to activate a row address; a third clock generator 2B for generating clocks to control read/write operations for a column address; a write clock generator 3 for controlling a read/write mode based on an input write enable signal WE; a refresh control circuit 4 for generating a clock øO to control the operation of the internal refresh counter in the CBR refresh cycle; an address counter for generating an internal address signal for a refresh operation; an address buffer for a column side 6A and an address buffer for a row side 7A, each converting an input address level to an internal CMOS level; an address latch circuit for a column side 6B and an address latch circuit for a row side 7B, each latching an external address signal and a refresh address signal; a data input buffer 12 for converting the level of an input data DIN to an internal CMOS level; a data output buffer 13 for amplifying an output data DOT; a substrate bias generator 14 for generating a back bias voltage; a memory cell array constituted by a plurality of DRAM cells; row and column decoders 8 and 9; and a sense amplifier - I/O gate 10.

Claims (9)

A dynamic random access memory comprising:
a plurality (11) of dynamic-type memory cells, arranged in rows and columns, for storing respective items of data;
refresh control circuitry (4, 5) for causing the data in selected ones of those memory cells to be refreshed, when the memory is in a refresh mode, and including refresh address circuitry (5) for generating refresh address signals (Qn, Qn) denoting memory cells to be refreshed; and
clock signal generating circuitry (1, 2A) connected to receive row address strobe signals (RAS) and column address strobe signals (CAS) and operating in dependence thereon to generate a first clock signal (ØA), when a preset length of time has elapsed after receipt of a row address strobe signal (RAS), and to generate second (ØB) and third (ØC) clock signals in response to the said first clock signal (ØA), the said second clock signal (ØB) being generated during a read/write mode of the memory and being delivered to addressing circuitry (Q9, Q10, Q11, Q12, AL) of the memory so as to cause that circuitry to latch an external address signal (An) supplied thereto, and the said third clock signal (ØC) being generated during the said refresh mode and being delivered to the said addressing circuitry (Q9, Q10, Q11, Q12, AL), so as to cause that circuitry to latch a refresh address signal (Qn, Qn) supplied thereto;
characterised in that the said clock signal generating circuitry (1, 2A) includes signal modifying means (AND1, L) including loading circuitry (L) operative during the said refresh mode, said loading circuitry reducing the rate of change of an intermediate signal (CAS) derived from the column address strobe signal (CAS) and employed to determine the timing of the said third clock signal (ØC), thereby to cause the time delay between the said first (ØA) and third clock signals (ØC), during the said refresh mode, to be greater than that between the said first (ØA) and second clock signals (ØB) during the said read/write mode.

A memory as claimed in claim 1 or 2, wherein the said loading circuitry (L) comprises a capacitive load.

A memory as claimed in claim 1, 2 or 3, wherein the said clock signal generating circuitry (1, 2A) further comprises a series of inverters (INV1 to INV4) having an input for receiving the said row address strobe signal (RAS) and having a first output, between two of the inverters (INV2, INV3), at which an inverted row address strobe signal (RAS) is provided, and a second output, at which the said first clock signal (ØA) is provided, and wherein the said signal modifying means (AND1, L) thereof further include an AND gate (AND1) connected to receive the said inverted row address strobe signal (RAS) and the said column address strobe signal (CAS) from which signals the AND gate derives the said intermediate signal (CAS), which signal is delivered to another inverter (INV5) of the clock signal generating circuitry (1, 2A) to obtain an internal clock signal (ØX), the modified intermediate signal (CAS) and the said internal clock signal (ØX) being supplied respectively to second and third AND gates (AND2, AND3) of the clock signal generating circuitry (1, 2A), each of which second and third AND gates (AND2, AND3) also receives the said first clock signal (ØA), the said second clock signal (ØB) being provided at an output of the said third AND gate (AND3) and the said third clock signal (ØC) being provided at an output of the said second AND gate (AND2).

A memory as claimed in claim 4, wherein the said clock signal generating circuitry (1, 2A) further comprises a NOR gate (NOR), connected for receiving the said second and third clock signals (ØB, ØC), and a further inverter (INV6) having an input connected to the output of the said NOR gate (NOR), a fourth clock signal (ØL) being provided at an output of the said further inverter (INV6).

A memory as claimed in claim 1, 2 or 3, wherein the said clock signal generating circuitry (1, 2A) further comprises a series of inverters (INV7 to INV10) connected for receiving at an output thereof an additional signal (AE) generated by delaying the row address strobe signal (RAS) and for providing at an output thereof the said first clock signal (ØA), a NAND gate (NAND1) connected for receiving the said first, second and third clock signals (ØA, ØB, ØC) and producing a control signal (ALE) on the basis of those clock signals, first and second CMOS inverters (Q13, Q14; Q15, Q16), each comprising a P-channel transistor (Q13; Q15) and an N-channel transistor (Q14; Q16) connected together in series, respective sources of the N-channel transistors (Q14; Q16) being connected to receive the said first clock signal (ØA), and the said second and third clock signals (ØB, ØC) being provided at respective outputs of the first and second CMOS inverters, a NOR gate (NOR) having inputs connected to receive the said control signal (ALE) and the modified intermediate signal (CAS) and an output connected to an input of the said first CMOS inverter (Q13; Q15), and a gate transistor (Q17) connected to supply the said modified intermediate signal (CAS) to an input of the said second CMOS inverter (Q14; Q16) in accordance with an inverted version of the control signal (ALE).

A memory as claimed in claim 6, wherein the said clock signal generating circuitry (1, 2A) further comprises an additional inverter (INV11) connected to receive and invert the said control signal (ALE) so as to produce a fourth clock signal (ØL).

A memory as claimed in any preceding claim, wherein the said addressing circuitry (Q9, Q10, Q11, Q12, AL) comprises address latch means (AL), having respective first and second inputs connected to first and second nodes (N1, N2) of the circuitry, first and second gate transistors (Q9, Q10) connected to deliver an external address signal (An) and a reference signal (Vrf) to the said first and second nodes (N1, N2) respectively upon receipt of the said second clock signal (ØB), and third and fourth gate transistors (Q11, Q12) connected to deliver a refresh address signal (Qn) and a complementary refresh address signal (Qn) to the said first and second nodes (N1, N2) upon receipt of the said third clock signal (ØC).

A memory as claimed in claim 8, when read as appended to claim 6 or 7, wherein the said addressing circuitry further comprises address buffer means (21) including a NAND gate (NAND2) and an inverter (INV13) connected together in series for converting the external address signal (An) from the TTL level voltage to the MOS level voltage in accordance with the said additional signal (AE).