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Job Responsibilities and Requirements: The tasks for this role will cover technology scaling, power budgeting, power flow setup, power rollup, analysis, optimization, and silicon correlation. It will also be involved in power methodology enhancement, new tool and flow developments for power estimation, analysis and optimization. Key Qualifications Power analysis and optimization (Calypso, Power Artist, Spyglass, PT-PX, Joules) Well versed in technology scaling and power projections Well versed in RTL power estimation, simulation with Cadence and Synopsys, PT-PX, synthesis and implementation Language and Tools: Verilog, Python, Perl, Tcl, C/C++, Matlab Knowledge of SoC power analysis, use cases, power domains, power switches Power Flow development and support Power modeling and IP characterization UPF/CPF Description In this role, the candidate will define the SoC power projections and current max limits, setup the power flows to drive the power estimation, analysis and optimization. The candidate will communicate the outcome of the power analysis on a regular basis, drive the power optimization to ensure that the power goals are met, and provide methods, techniques, suggestions and feedbacks to reduce both leakage and dynamic power from RTL to gates. Collaborate with the project stakeholders including the members of the SoC system, DV and integration teams on various power tasks. Such tasks will include power architecting, power domain selection, use case selection, UPF, power virus analysis, power flows and algorithms development, deployment and support. Education BS/MS/PhD CE, EE, or CS Additional Requirements.

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