Chip designers make better copper interconnects

By
05.28.2003 :: 7:50AM EST

For the past several years, chipmakers have been using copper instead of aluminum in chip interconnects. Surprisingly, AMD began using copper interconnects before Intel, despite having a much smaller R&D budget. Copper is a superior conductor to aluminum, but is more difficult to integrate into the chipmaking process. One of the problems with copper, however, is that it tends to migrate into silicon wafers and contaminate the transistors. The traditional remedy to this problem has been to insert a barrier level between the copper and underlying silicon, thereby preventing copper migration. This barrier level, however, tends to reduce the efficiency of copper. Chip designers have been trying to get the barrier level as small as possible. Munich researchers now claim that they can create functional barrier levels of only 2 nanometers. This ultra-thin barrier should have only minimal electrical resistance. Current barrier levels are now 12 nanometers. This means that the copper interconnects can be used all the way down to the 35 nanometer generation. Karl Eberling, the head of research for Infineon, states that this discovery “mark[s] a significant milestone to provide all the high sophisticated technologies needed to manufacture the further shrunken next chip generations.” It appears that 35 nanometer chips are looking increasingly feasible.

USER COMMENTS 7 comment(s)

cool(7:55am EST Wed May 28 2003)now if they only could fix the heating problems! – by heat sucks

heat sucks…(9:26am EST Wed May 28 2003)The solution…SMP, w/ lower frequency chips. It's not all the chipmaker's fault. Relatively few programs take full advantage of SMP. Chips are only going to get denser and hotter. Hopefully Hyperthreading will motivate more companies to write their programs to support multi-threading, especially the games. – by Steven

hyper threading and such(10:47am EST Wed May 28 2003)I agree with that, hopefully HT is the catalyst to making all the different parts of the CPU work in parallel a normal thing for all chip companies. – by whatever

SMP(11:51am EST Wed May 28 2003)In addition chip makers will love the SMP options becoming a lot more widespread as they will no longe be selling one chip….but TWO….imagine doubling your volume..quite a nice prospect on their part…

even if the chips are slower and cost 25% less then their higher speed rated brethren that is still 50% more price total…meaning more revenue…which is always a good thing – by distempered

SMP is not a panacea(6:37pm EST Wed May 28 2003)While I'll be the first one to say that an increase in SMP-enabled systems would be great, SMP is not a viable solution in all respects, nor will it ever be. While most modern operating systems support SMP, many applications either don't support it at all or don't take full advantage of SMP resources.

Take the following pseudo-operation sequence:

1. A + B = C2. C + D = E

This is an extremely simple example of a non-parallel operation. Op #2 simply cannot proceed until Op #1 is completed since it relies on the results of Op #1 as one of its operands. If a program had many such “blocking” operations, increasing the number of CPU's would bring little or no benefits at all. However, if we had the following:

1. A + B = C2. D + E = F

Then both of these operations could execution concurrently. In fact (in simple terms), for N non-blocking operations, you can scale to N processors and get linear performance increases. Programs such as raytracers, scanline renderers, fluid dynamics simulations, and finite element stress analysis lend themselves well to SMP. These are not common desktop programs, though.

SMP can benefit a non-SMP-aware program by keeping the system more responsive, though. While one CPU could be maxed out, the other could be servicing other user requests, or even running another intensive program. In this respect, the SMP system would be functioning, at the macro level, as an asymmetric multiprocessing system, not SMP.

Internally, CPU's are becoming more SMP like every day (some would say they're already there and have been for some time). The problem, though, is keeping all the multiple execution units of a CPU busy enough, and the root of that problem is compilers. Until better compilers come along, all the SMP in the world is going to waste away once you go above four processors. – by J. Eric Smith

What deposition method?(8:19pm EST Wed May 28 2003)What deposition method was used to get the 2nm result? The routine barrier and seed deposition method is sputtering. A 2nm conformal sputtered film would be a pretty amazing result. They didn't use ALD, good. CVD would be my guess, but if it really was sputtered–WOW! – by BEN