TSMC pushes ahead with 450 nanometre wafer plans

TSMC European president Maria Marced said the foundry is pressing ahead to shift to 450 millimetre wafers, with pilots expected as early as 2013.

TSMC already has three 12-inch fabs producing more than a million wafers a year. She said it will continue to be the leading foundry worldwide. Challenges for TSMC include both economic and technical. Every process node becomes more and more difficult. Every generation requires additionally complex additions, and technology shrinks don’t give sufficient cost savings any more. But moving to 450 millimetre wafers will give “reasonable cost saving,” she said. Competitors are allying on the move to 450 millimetres – with TSMC allying with IBM, Intel, GlobalFoundries and Samsung. The reason for this is the sheer cost of moving to the next wafer size.

It will introduce a 450 mm pilot line at fab 12 in 2013-2014, and a 450 millimetre production line at Fab 15 in 2015-2016.

She also addressed a number of other topics affecting the semiconductor industry. Right now she said semi growth is stunted by economic woes in the third quarter, she said. Gartner and IHS iSuppli have both said that sales are slowing rapidly.

She said that bringing new technology into play drives real growth, and not advertising. Mobile internet computing will steadily grow between now and 2020, she said. TSMC thinks that smartphone needs lower operating power and usage time. High performance system on a chip devices will, however enable new applications including light sensising, sound recognition and radio reception.

TSMC estimates that R&D this year will be $1.1 billion, similar to the MIT budget. TSMC Capex for this year will be $7.4 billion.

28 nanometre product ranges deliver 30 percent more speed with 2X reduction in leakage, she said. Making 28 nanometre technology has been difficult but she said TSMC is very happy with its technology adoption. There have been 89 tapeouts in the quarter so far.

TSMC will introduce 20 nano technology in the second half of next year, and that poses a number of challenges too. This will be TSMC’s second generation of its hi-gate tech, and will deliver two times the density, with risk production beginning in the third quarter of next year.

There will be four generations of 20 nano tech, with a simplified set of offerings – 20G for high performance and 20SoC for mobile devices. TSMC will introduce 14 nanometre technology and it is investigating new materials for active power challenges while keeping up performance.

TSMC has a varied roadmap depending on the semiconductor types it will build. It is focusing on MEMS, on BCD and on embedded flash and embedded DRAM.

It claims it is a leader in e-Flash, it is developing 28 nano e-DRAM and e-DRAM at 80, 65 and 40 nanos are already in production. It claims it is the leader in BSI pixel technology and will continue to be able to scale its technology.