I need to divide the input frequency (let's say divide by 50) using the down count mode of the 74192 UP/DOWN decade counter. I will use the parallel inputs to give the desired count value. Since the count is more than 10, I will need cascade counters.
Please help me how to configure this implementation to divide the input frequency.

1) What is your input clock frequency?
2) What is the range of frequencies you need?
3) At what resolution?
4) From the above, you can answer what are the numbers you need in your divisor?
5) What are you trying to build?

1) What is your input clock frequency?
2) What is the range of frequencies you need?
3) At what resolution?
4) From the above, you can answer what are the numbers you need in your divisor?
5) What are you trying to build?

5) Programmable divided by N counter for a PLL
2) It varies from 88MHz to 108MHz. You know that, F = NxFR.
Finally, the output frequency of the divider should be the referance frequency,FR. ( FR is 100 kHz). I will set the desired count, to get the output frequency (F) at the VCO.
4) 880 to 1080
3) What do you mean as the resolution?

Hi!
I just need how to configure the 74F192 IC (I already selected 74F192) to get the frequency division.
For example: Which pin will give the divided frequency as the output from the last 74F192 IC of this cascaded system if I used down count mode? etc.

I wire up the 74192 and simulated it with a divisor of 60. I setup a 3rd 74192 to display the results. Before connecting the JK FF to divide the result by 2, the 3rd 74192 immediately increments by 1 when power is applied. With the JK FF, the up-counter would first increment after 60 counts and subsequently increments after every 120 counts.