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However, my understanding is that early eighties RAM chips typically took 375 ns for a full access cycle. The amortized access time can be reduced by using page mode, but the timing diagram doesn't seem to suggest this is happening.

3 Answers
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The Amiga A500 used 41256-15 DRAM chips for its onboard memory. According to the datasheet these had a cycle time of 260ns, so could easily match the 280ns timing constraint with 20ns to spare (although the board had two banks of them, and switching between the banks likely used up most of that 20ns).

The 375ns limit really only applied to the 4116 and 4164 type chips that were manufactured in huge bulk and were extremely cheap. Faster chips were available even back to the early 80s, but cost more money so designers of low-end micros tended to avoid using them where possible (cf the 4816A chips in the BBC micro we discussed previously, which were necessary in order to let a 6502 run at 2MHz with capacity left for video access between the CPU's accesses), especially when working with either 1MHz 6502 or 4MHz Z80 designs where faster RAM would have been useless.

To understand how Amiga memory bandwith should be calculated and how data fetching to Amiga Chipram works.

The timingslot schematic that rwallace refering to does not tell anything about how individual chipram ic' operates or are supposed to operate;
it just explains how the Amiga timing system is layed out.

The Amiga is a synchronized multiprocessor platform/architecture. It share same memory to some extension.
That shared memory is called chipram.
The shared memory require some rules to be followed to make it work and to avoid something called bus contention.
Bus contention occurs when more than one processor want access to the common address-, data-, or registerbus.

To solve this Amiga has a nested (interleaved) access to the buses (and some other solutions too).
It means that the bus access is divided into odd and even timeslots.
The whole timeslot concept is based on duration of one video raster-scanline, and that one timslot has a duration of approximatly 280ns.
Why 280ns? Because it's the speed of the color clock driving the amiga chipset (Agnus, Paula, and Denise. Agnus contains the DMA controller
responsible for memory access to chipram).

1000 000 000 / 3546895hz (colorclock) = 281.9367ns (PAL)

Due to the interleave approach to solve the bus contention problem the individual processors does not fetch data from chip memory with a bandwidth of 7mb/s but instead
half of that amount - 3.5mb/s. Now this it not the whole truth. In graphic intensive tasks the amiga chipset can take full control of the buses
and run at full bandwidth (7mb/s) at the expense of the cpu not having any access at all (no timeslots to its disposal). The DMA sytem can also be turned off and let the cpu have
full access and do all the work (every other timeslot that is).
Note: horisontal and vertical blanking period is not included in these situations.

It actually takes 560ns - two time slots (one time slot being 280ns)
for cpu to fetch data from memory (Fast OR Chip mem).

An example:

(PAL)

1000 000 000 / 7093790Mhz = 140.96837ns

140.96837ns * 4 cpu clockcycles = 563.87347ns

How much is the different clock-speeds in terms of nanoseconds (ns)?

Always divide the (Mhz) by 1000 000 000 (1000 000 000 / Mhz) and you will get ns.
When you read the inscription on memory ic's the access speed is written in nanoseconds e.g. 41256-15 means 150ns (access time).

To increase bandwidth to chip memory three 'rules' must be fulfilled:

Cpu clock need to be synchronized with masterclock.

Chip memory need to be fast enough to handle the new clockspeed.

The cpu clock need to be at least four times as fast, i.e. at the same speed as masterclock to double the bandwidth. The synchronization require cpu clock to be a multiple of masterclock.

Why does cpu need to be four times as fast to increase the bandwith?
Because of the interleaved approach to chipram between cpu and amiga chipset; this together with the fact that - as mentioned above - it takes 4 cpu clock cycles to fetch data from chipram (and fastram). In other words; cpu access chipram (and chipregisters) every other timeslot and therefore it needs to be quadrupled in clockspeed.

NOTE: This will only increase bandwidth between cpu <-> chip-ram and not the speed between Amiga Chipset <-> chip-ram.

DRAM access time isn't relevant for calculating bandwidth (it specifies latency, not overall throughput), cycle time is. The 41256-15 has 260ns cycle time. Also, just because the CPU takes two bus cycles to access memory doesn't mean that the total bandwidth of the system is limited to that rate, as the system also has a DMA controller that gets access to memory interleaved between the processor's accesses. I believe LVD's answer is correct, at least modulo the slight variation in speed between the PAL and NTSC models.
– JulesMar 31 at 10:24

@Jules: It seems a shame the Amiga was never designed to exploit DRAM chips' ability to perform multiple accesses within a page at a cost only slightly above the cost of a single access. If the DMA-based chips were designed to fetch pairs of words, and a pair of 16-bit pre-fetch buffers were added, performance could have been greatly improved even if all accesses were double accesses that took 1.5 chroma clocks to complete [if the CPU fetches the first half of a 32-bit word on one cycle and then requests the other, the second request wouldn't need to go out to RAM].
– supercatApr 9 at 0:36

@supercat - indeed, it seems that many systems produced in the 80s could have had superior IO performance if page mode had been exploited more frequently. There are isolated uses (e.g. the Spectrum's ULA fetching two bytes in the interval between the Z80 memory fetches), but AFAICT the capability wasn't routinely used in microcomputer class machines until the faster 80386 models turned up, and commodity DRAM was simply unable to cope with the demand of memory bandwidth necessary to keep them running at full speed without using page mode...
– JulesApr 9 at 2:56