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AMD’s long-term microprocessor strategy

AMD's CTO sheds some light on the company's long-term plans for world …

A recent post of mine on AMD's near-term anti-Intel strategy linked up an interview with AMD CTO Phil Hester. Hester talked about coherent HyperTransport licensing, and how that fits in with AMD's plans to fill the gap left by Intel's aging frontside bus architecture and lack of on-die memory controllers.

Hester has given a new interview to the EET, where he gives some great hints at AMD's near- to long-term strategy for growing the company's processor market share. In brief, the answer is to split the company's x86 microarchitecture into two lines, one for the mobile space and another for the server space:

Hester: We are evolving to what I'd say are a minimum of two brand-new core design points, new microarchitectures from the ground up. One is aimed at mobile computers and the very low-power space. Another is optimized for the high-end server space. The question we have now is: Can you pull down the server space, or pull up the mobile, enough to cover the desktop?

...The mobile microarchitecture could be pushed up to the desktop and down to what I believe in the next three to four years is going to be something that lives between your notebook and your PDA. That would be something that also works well in a set-top box or a digital TV. If you make it modular, you could come up with different design points to meet different costs: either a system limited to 1 watt of power consumption or the traditional notebook space. You would have the same basic microarchitecture, but with different caches or different bus widths to memory.

This bifurcation strategy, where you have one microarchitecture for low-power space and another for the server space, might at first seem to be exactly what Intel and the rest of the industry are leaving behind. Witness Intel's plans to ditch the Pentium 4's Netburst microarchitecture and to unify all of their x86 product lines across all segments on the new "Core" microarchitecture.

As we've seen over and over again the past few years, the needs of the server space and of the mobile space are rapidly converging on one overriding issue: power consumption. What's good for the notebook has turned out to be good for the datacenter, both in terms of process-based power saving techniques aimed at controlling transistor leakage and in terms of microarchitectural tricks like micro-ops fusion. Across the board, companies like IBM and Intel are moving to a single, one-size-fits-all, power-optimized microarchitecture, combined with multicore for scalability purposes, to address all commodity market segments.

So where does Hester's twofold grand strategy leave AMD? Pretty well positioned actually. The need for single-threaded performance is just not going away any time soon, and AMD knows this. So does Sun, which is why they're pairing the low-power UltraSparc T1 line with the forthcoming Rock—a second, higher-end microarchitecture that will focus on single-threaded performance by using a more traditional out-of-order design. And so does IBM, which is continuing to maintain the POWER5 microarchitecture as a separate microarchitecture for the high-end alongside Cell for power-sensitive applications. Finally, Intel knows this as well, which is why Itanium development still lumbers along.

In sum, despite first appearances this new, two-pronged tack finally brings AMD in line with what the rest of the industry has already announced: a flexible, low-power architecture aimed a spectrum of single- and multi-core applications, and a high-end architecture for very the lucrative and growing high-end server segment.

One final point by way of conclusion: in the list above of companies that are developing two microarchitectures—AMD, Sun, IBM, and Intel—Intel is the odd one out. Why? Because they're the only company whose high-end, single-thread-oriented server architecture has and will continue to have a separate ISA from the rest of their offerings. (Even IBM is allegedly moving the zSeries to POWER via the ECLipz project.) This means that Intel will have the burden of maintaining a separate software ecosystem for their premium architecture at a time when their competitors can get software side economies of scale with a unified ISA.

You want to know something that I totally can't prove and have no evidence at all for other than my intuition? Somewhere inside Intel, I think there must be a move afoot to develop a new high-end x86 architecture that can replace Itanium in the event that the forces described above make the company's two-ISA strategy untenable. This makes sense to me, but feel free to flame me for wild and unwarranted speculation in the discussion thread if it makes no sense to you.

Update: I was passed a rumor that says that the POWER6 core is based on the Cell PPE, and that POWER7 is internally called "Cell 2." Take that for what it's worth. At any rate, I mention this because it may well be the case that the POWER5/970 lineage really is dead, and that IBM will unify everything around Cell.