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Having architectural and implementation flexibility in nowadays complex designs is a must. Anticipating ever changing product requirements and market changes makes this mandatory. With the increasing need to use FPGAs to meet current performance requirements, this is not a simple task.

FPGA devices are typically used in a static manner. After solid verification and testing you freeze the functionality and treat this as a part of the hardware system: fixed functionality providing system integration, communication handling and high-performance data processing. A good and solid solution for many applications. However using a programmable device in a fixed configuration limits the dynamic capabilities excludes many application opportunities.

On the software side of embedded development more flexibility is available. The operating system available give you already an infrastructure that abstracts hardware functionality, provides means for process threading, task synchronization and memory management. With compiler technology specific platform behavior is abstracted from the programmer contributing to faster development and simpler specification of intended behavior of the application. This utilization model is a more suitable approach when design flexibility is key.

Partial Reconfiguration is an interesting technology available on FPGAs enabling re-use flexibility on your FPGA. This technology exists for quite some time. Adoption by the market has proven to be difficult and is not broadly applied apart from some very specific applications.

Years of study, research and technology investigation resulted in the creation of Dyplo: seamless software and FPGA integration enabling full threaded software tasks to run dynamically on the FPGA ánd can be swapped at runtime. To achieve this, extensive use of Partial Reconfiguration is part of this solution.

The use of Partial Reconfiguration in FPGA technology allows the creation of execution workspaces within the FPGA which behave similar to virtual memory on a processor where you can create processes, start them, stop them and reassign workspaces to different task or processes. The Dyplo processing infrastructure ensures that software and FPGA process execution behavior is the same, except for the execution performance.

As the Partial Reconfiguration techniques are embedded in and controlled by the Dyplo infrastructure, the user does not actively have to deal with the Partial Reconfiguration infrastructure himself. It is completely managed by the Dyplo Development Environment (DDE) and the Dyplo infrastructure. Using Dyplo and Partial Reconfiguration you make dynamic and run-time re-use of FPGA fabric available for both FPGA programmers and software engineers.

When building heterogeneous platforms, either FPGA only or System-on-Chip based integration platforms like the Xilinx Zynq 7000 processor, can now benefit from using this unique characteristics of what Partial Reconfiguration enables.