Tuning the 8255x Controllers Equalizer Application Note 435

Tuning Intel® 8255x Controller for Capacitor-Coupled Applications

Introduction

The adaptive equalizer is a key circuit block within the Intel® 8255x Gigabit Ethernet Controller PHY unit. Its job is to restore the distorted MLT-3 signal received at the end of the wire to a waveform that can be used to reliably extract the 125 MHz clock and decode the data.

Equalization is a three-step process based on voltage, phase, and bit error detection. Normally, the equalizer performs adaptation on a received signal that traversed a length of balanced CAT5 cable and passed through two magnetics modules along the way. The equalizer is optimized to amplify this specific signal for a range of cable lengths from zero to 100 meters. Equalizer adaptation occurs every time the PHY attempts to establish link.

When the 8255x controller is used in a point-to-point or backplane application, the differential pairs are typically connected to a link partner through circuit board traces and AC coupling capacitors instead of through magnetics modules and CAT5 cables. With capacitive coupling, “looks” like a high pass filter instead of the low pass filter presented by transformer-based connections. The MLT-3 signal passing through a capacitive coupled circuit will be distorted differently than an MLT-3 signal passing through a transformer. Higher slew rate and higher signal overshoot suggest a very “strong” signal. The signal amplitude may be higher than a signal attenuated by cable, but it could be lower than expected for such steep rise and fall times.

The 8255x controller’s adaptive equalizer can become confused by a received signal that is distorted in this way, and it can make setting errors. If the equalizer is set for too much gain, the controller may exhibit failure to achieve link, loss of link, or symbol errors. This Technical Advisory explains how to read the PHY equalizer settings and how to program the settings manually. If the 8255x controller in your system readily achieves link and receives data without errors, there is no need to adjust the equalizer settings, regardless of capacitive coupling on the analog pairs.

The adaptive equalizer is a key circuit block within the Intel® 8255x Gigabit Ethernet Controller PHY unit. Its job is to restore the distorted MLT-3 signal received at the end of the wire to a waveform that can be used to reliably extract the 125 MHz clock and decode the data.

Equalization is a three-step process based on voltage, phase, and bit error detection. Normally, the equalizer performs adaptation on a received signal that traversed a length of balanced CAT5 cable and passed through two magnetics modules along the way. The equalizer is optimized to amplify this specific signal for a range of cable lengths from zero to 100 meters. Equalizer adaptation occurs every time the PHY attempts to establish link.

When the 8255x controller is used in a point-to-point or backplane application, the differential pairs are typically connected to a link partner through circuit board traces and AC coupling capacitors instead of through magnetics modules and CAT5 cables. With capacitive coupling, “looks” like a high pass filter instead of the low pass filter presented by transformer-based connections. The MLT-3 signal passing through a capacitive coupled circuit will be distorted differently than an MLT-3 signal passing through a transformer. Higher slew rate and higher signal overshoot suggest a very “strong” signal. The signal amplitude may be higher than a signal attenuated by cable, but it could be lower than expected for such steep rise and fall times.

The 8255x controller’s adaptive equalizer can become confused by a received signal that is distorted in this way, and it can make setting errors. If the equalizer is set for too much gain, the controller may exhibit failure to achieve link, loss of link, or symbol errors. This Technical Advisory explains how to read the PHY equalizer settings and how to program the settings manually. If the 8255x controller in your system readily achieves link and receives data without errors, there is no need to adjust the equalizer settings, regardless of capacitive coupling on the analog pairs.