Abstract

Trellis codes and rate-k/n convolutional codes are often used in wired communications, terrestrial radio and satellite radio links for bandwidth efficiency. To further increase data rates and coding gain, higher rate codes with more states can be used. Cost effectiveness of decoders for these complex rate-k/n and trellis codes becomes a major issue. While cost-effective decoder architectures for rate-1/n convolutional codes and high speed decoder architectures are well know, current low-cost decoders for rate-k/n convolutional and trellis codes still resort to suboptimal decoding algorithms. This paper describes a new way to design cost-effective Viterbi decoders for complex rate-k/n convolutional and trellis codes through a co-design of state-processor mapping, topology scaling, scheduling, metric reordering, and VLSI structures of processing elements. New serial-access processing element structures are proposed. The 2q-way interleaving algorithms developed here for metric reordering can be applied to other applications such as interleave coding.