ISSCC preview: Revving ReRAMS, boosting memory bandwidth

"ReRAM now has the opportunity to be adopted as a storage-class
memory competing with the existing NAND Flash memories for
nonvolatile mass storage applications," the paper's presenters
argue.

Another ReRAM paper, from Panasonic, presents an ReRAM
filament-scaling forming technique and level-verify-write scheme
with endurance over 107 cycles for a 16nm cell. It is realized
within a 1T1R ReRAM array.

SRAM advances
On the SRAM front, designers continue to struggle with leakage and
dynamic power reductions as process nodes dive down past 45nm. The
use of "FinFETS and fully-depleted SOI are key to enabling the
continuous scaling of bit cell area and low voltage performance" at
22nm and below, Zhang notes.

TSMC will present a paper describing the first 112Mb 6T SRAM at
20nm. It's the smallest known 6T-SRAM bit cell area at 0.081μm2. A
four-state power-management scheme reduces retention leakage by over
65%.

Bandwidth busters
Memory bandwidth continues to advance this conference with one of
the highest reported data rates for memory transceivers. Rambus will
describe a single-ended transceiver design with a 6.4Gb/s/pin for
high-density dual-rank DIMM modules. At the 2012 ISSCC, Rambus
presented a paper for a similar technology but at half the speed
(3.2Gb/s/pin DDR4). T he devicealso achieves exceptional power
efficiency at 9.1mW/Gb/s, which is essential for future
applications.

DRAM data rate/pin trends

"This design has demonstrated the potential to be used in various
VLSI systems, including data center servers, networking, and
low-power handheld devices," Rambus writes in a paper preview. "The
design should enable significant boost in performance due to higher
data rate while keeping the overall DRAM power consumption at
minimum."