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Abstract:

A circuit module includes a multilayer substrate including built-in
capacitors and external components mounted on the surface of the
multilayer substrate. On the surface of a dielectric layer, an auxiliary
electrode is provided. The auxiliary electrode is electrically connected
to a capacitor electrode via a via electrode passing through the
dielectric layer. On the surface of a dielectric layer, a capacitor
electrode is arranged so as to face the capacitor electrode and the
auxiliary electrode connected to the capacitor electrode. The auxiliary
electrode is arranged in an area in which the capacitor electrodes
overlap each other as viewed from a lamination direction.

Claims:

1. A circuit module comprising: a multilayer substrate including at least
one built-in capacitor, a plurality of dielectric layers, and a plurality
of capacitor electrodes, the plurality of dielectric layers and the
plurality of capacitor electrodes being laminated to one another; wherein
a via electrode is provided between a pair of the plurality of capacitor
electrodes defining the at least one built-in capacitor.

2. The circuit module according to claim 1, wherein the via electrode
extends from one of the pair of the capacitor electrodes defining the at
least one built-in capacitor toward the other one of the pair of the
capacitor electrodes.

3. The circuit module according to claim 1, further comprising: an
auxiliary electrode provided in an area in which the pair of the
capacitor electrodes overlap each other as viewed from a direction in
which the plurality of dielectric layers and the plurality of capacitor
electrodes are laminated; wherein the auxiliary electrode and the via
electrode are connected to each other.

4. The circuit module according to claim 1, wherein the at least one
built-in capacitor is a capacitor group of at least two capacitors
defined by at least three of the plurality of capacitor electrodes; and
adjacent ones of the at least two capacitors in the capacitor group share
one of the plurality of capacitor electrodes.

5. The circuit module according to claim 4, wherein, for the at least
three of the plurality of capacitor electrodes of the capacitor group, a
plurality of the via electrodes or a plurality of the auxiliary
electrodes connected to the via electrodes are provided.

6. The circuit module according to claim 1, wherein a circuit element
other than the at least one capacitor is provided on at least one of the
plurality of dielectric layers.

Description:

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a circuit module that is included
in a communication apparatus for use in a high-frequency band and
includes a multilayer substrate including built-in capacitors.

[0003] 2. Description of the Related Art

[0004] As communication apparatuses, such as mobile telephones, decrease
in size and weight and increase in functionality, circuit elements
embedded in these communication apparatuses have been reduced in size and
increased in functionality. There is also an increasing demand for a
compact and multifunctional circuit module including such a circuit
element.

[0005] Each circuit module used in communication apparatuses, such as
mobile telephones, is generally produced with a multilayer substrate
including built-in capacitors. The multilayer substrate including
built-in capacitors is obtained by laminating a plurality of functional
layers. An active element and a passive element, which are required to
form a circuit module, are mounted on each of the functional layers.

[0006] An example of such a circuit module is disclosed in Japanese
Unexamined Patent Application Publication No. 2005-39263.

[0007] The configuration of the circuit module disclosed in Japanese
Unexamined Patent Application Publication No. 2005-39263 will be
described with reference to FIGS. 4, 5, and 6.

[0008]FIG. 4 is a cross-sectional view of a circuit module 100. The
circuit module 100 includes a multilayer substrate 101 including built-in
capacitors. The multilayer substrate 101 including built-in capacitors is
obtained by laminating a plurality of functional layers.

[0009] FIGS. 5 and 6 are diagrams illustrating functional layers 106 and
107, respectively. FIG. 5 is a plan view of the functional layer 106 as
viewed from the surface of the functional layer 106. On the surface of
the functional layer 106, capacitor electrodes C13 to C16 and inductor
electrodes L1 and L2 are formed. One end of the inductor electrode L1 is
connected to the capacitor electrode C13, and the other end of the
inductor electrode L1 is arranged close to the capacitor electrode C15.
One end of the inductor electrode L2 is connected to the capacitor
electrode C14, and the other end of the inductor electrode L2 is arranged
close to the capacitor electrode C16.

[0010] FIG. 6 is a plan view of the functional layer 107 as viewed from
the surface of the functional layer 107. On the surface of the functional
layer 107, capacitor electrodes C131, C141, C151, and C161 are formed.
The capacitor electrodes C131, C141, C151, and C161 face the capacitor
electrodes C13, C14, C15 and C16, respectively, formed on the surface of
the functional layer 106 via the functional layer 106, so that capacitors
C3 to C6 are formed in the functional layer 106 that is a capacitor
layer.

[0011] A design method of providing a good characteristic for a circuit
module by adjusting the value of a capacitor in a circuit to an optimum
value is often used.

[0012] For example, in the case of the multilayer substrate 101 including
built-in capacitors in the circuit module 100, the area of the capacitor
electrode C15 may be changed so as to adjust the capacitance value of the
capacitor C5. In this case, however, since the inductor electrode L1 and
the capacitor electrode C15 are close to each other on the same
dielectric layer, the state of coupling between the inductor electrode L1
and the capacitor electrode C15 is also changed. In a case in which the
thickness of the functional layer 106 is changed so as to change the
capacitance value of the capacitor C5, the capacitance values of the
other capacitors in the functional layer 106 that is a capacitor layer,
that is, the capacitors C4, C5, and C6, are also changed.

[0013] Such a change in a capacitance value will be described with
reference to FIGS. 7A and 7B. Referring to FIG. 7A, capacitor electrodes
1 and 2 face each other, so that a capacitor C1 is formed. An inductor
electrode 3 is formed over the capacitor electrode 1, and a coupling
capacitor C2 is formed between the inductor electrode 3 and the capacitor
electrode 1. FIG. 7B is a diagram illustrating the change in the area of
the capacitor electrode 1 which is performed so as to change the value of
the capacitor C1. As illustrated in the drawing, the reduction in the
area of the capacitor electrode 1 changes the value of the coupling
capacitor C2 between the capacitor electrode 1 and the inductor electrode
3. Although not illustrated, in a case where the position of the
capacitor electrode 2 in the lamination direction is changed so as to
change the value of the capacitor C1, the value of the coupling capacitor
C2 is also changed.

[0014] Thus, in a multilayer substrate including built-in capacitors in
the related art, when the value of a single capacitor in the substrate is
optimized, the state of coupling between a corresponding capacitor
electrode and another circuit element in the substrate is also changed.
Accordingly, it is necessary to change the overall design of the
multilayer substrate.

SUMMARY OF THE INVENTION

[0015] To overcome the problems described above, preferred embodiments of
the present invention provide a multilayer substrate including built-in
capacitors in which the value of one of the capacitors can be
independently adjusted without changing the state of coupling between a
corresponding capacitor electrode and another circuit element and the
values of the other ones of the capacitors.

[0016] A circuit module according to a preferred embodiment of the present
invention preferably includes a multilayer substrate including at least
one built-in capacitor. The multilayer substrate including at least one
built-in capacitor includes a plurality of dielectric layers and a
plurality of capacitor electrodes that are laminated to one another. A
via electrode is provided between a pair of the plurality of capacitor
electrodes defining the at least one capacitor.

[0017] In this case, only the capacitance value of a predetermined
capacitor can be independently adjusted without affecting the state of
coupling between a corresponding capacitor electrode and another circuit
element and the other capacitors.

[0018] The via electrode preferably extends from one of the pair of the
capacitor electrodes defining the at least one capacitor and is
preferably directed towards the other one of the pair of the capacitor
electrodes.

[0019] The circuit module preferably further includes an auxiliary
electrode that is provided in an area between the pair of the capacitor
electrodes overlapping each other as viewed from a lamination direction
and is arranged parallel or substantially parallel to the lamination
direction. The auxiliary electrode and the via electrode are preferably
connected to each other.

[0020] In this case, by providing an auxiliary electrode, the capacitance
value of a predetermined capacitor can be independently adjusted easily
without affecting the state of coupling between a corresponding capacitor
electrode and another circuit element and the values of the other
capacitors.

[0021] The at least one capacitor is preferably a capacitor group
including two or more capacitors defined by three or more of the
plurality of capacitor electrodes. Adjacent capacitors in the capacitor
group preferably share one of the plurality of capacitor electrodes.

[0022] In this case, only the capacitance value of a predetermined
capacitor can be adjusted while efficiently configuring a plurality of
capacitors.

[0023] For the three or more of the plurality of capacitor electrodes
defining the capacitor group, a plurality of the via electrodes or a
plurality of the auxiliary electrodes connected to the via electrodes are
preferably provided.

[0024] In this case, by providing a plurality of via electrodes or a
plurality of capacitors, the number of capacitors for which the
adjustment of a capacitance value can be performed at the same time is
increased. In a case in which a plurality of auxiliary electrodes is
provided for a single capacitor, the design flexibility of a capacitance
value is increased.

[0025] A circuit element other than the at least one capacitor is
preferably provided on one of the plurality of dielectric layers.

[0026] According to various preferred embodiments of the present
invention, a via electrode is provided for capacitor electrodes defining
a capacitor in a multilayer substrate including built-in capacitors.
Alternatively, a via electrode and an auxiliary electrode connected to
the via electrode may be provided for the capacitor electrodes. As a
result, only the capacitance value of the capacitor can be designed
without affecting the state of coupling between each of the capacitor
electrodes and another circuit element in the substrate and capacitors
defined by the other capacitor electrodes in the substrate. This leads to
the increase in design flexibility.

[0027] The above and other elements, features, steps, characteristics and
advantages of the present invention will become more apparent from the
following detailed description of the preferred embodiments with
reference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0028]FIG. 1 is a cross-sectional view of a circuit module according to a
first preferred embodiment of the present invention.

[0029]FIG. 2 is a cross-sectional view of a circuit module according to a
second preferred embodiment of the present invention.

[0030]FIG. 3 is a cross-sectional view of a circuit module according to a
third preferred embodiment of the present invention.

[0031]FIG. 4 is a cross-sectional view of a circuit module in the related
art.

[0032]FIG. 5 is a plan view of a functional layer 106 in the circuit
module in the related art.

[0033] FIG. 6 is a plan view of a functional layer 107 in the circuit
module in the related art.

[0035] A circuit module according to preferred embodiments of the present
invention that include a substrate including built-in capacitors will be
described below with reference to the accompanying drawings.

First Preferred Embodiment

[0036] The configuration of a circuit module 10 according to a first
preferred embodiment of the present invention is illustrated in FIG. 1.
FIG. 1 is a cross-sectional view of the circuit module 10.

[0037] As illustrated in FIG. 1, the circuit module 10 preferably includes
a multilayer substrate 20 including built-in capacitors and external
components 11 mounted on the surface of the multilayer substrate 20. The
external components 11 are connected to one of the main surfaces of the
multilayer substrate 20 including built-in capacitors via mounting
electrodes 12 disposed on the main surface of the multilayer substrate
20. For example, as the external component 11, a chip inductor, a
laminated capacitor, a surface acoustic wave filter, or a diode is
preferably selected in accordance with a desired function to be performed
by the circuit module 10.

[0038] The multilayer substrate 20 including built-in capacitors is
preferably defined by a laminate including a plurality of dielectric
layers 21 to 29 made of ceramic or a resin, for example. Predetermined
electrode patterns are provided on the surface and undersurface of the
laminate and between the dielectric layers. With these electrode
patterns, circuit elements, such as capacitors and inductors, and a
transmission line to transmit signals are defined. Only electrode
patterns related to a characteristic structure according to this
preferred embodiment are illustrated in FIG. 1, and the illustration of
the other electrode patterns is omitted.

[0039] Capacitor electrodes 30 and 31 are provided on the surfaces of the
dielectric layers 24 and 25, respectively. On the surface of the
dielectric layer 26 adjacent to the dielectric layer 25, a capacitor
electrode 32 is provided. The capacitor electrode 32 faces the capacitor
electrode 30 via the dielectric layers 24 and 25, so that a capacitor C11
is provided in an area filled in with large dots in FIG. 1. In addition,
the capacitor electrode 32 faces the capacitor electrode 31 via the
dielectric layer 25, so that a capacitor C21 (a dark shaded portion in
FIG. 1) is provided.

[0040] An auxiliary electrode 33 is provided on the surface of the
dielectric layer 27. The auxiliary electrode is connected to the
capacitor electrode 32 via a via electrode 37 passing through the
dielectric layer 26. On the surface of the dielectric layer 28, a
capacitor electrode 34 is provided so as to face the capacitor electrode
32 and the auxiliary electrode 33 connected to the capacitor electrode
32. The auxiliary electrode 33 is arranged in an area in which the
capacitor electrodes 32 and 34 face each other as viewed from the
lamination direction.

[0041] The capacitor electrode 32 faces the capacitor electrode 34 via the
dielectric layers 26 and 27 in an area in which there is no overlap
between the capacitor electrode and the auxiliary electrode 33 as viewed
from the lamination direction, so that a capacitor C31a is provided. On
the other hand, in an area in which the capacitor electrode 32 and the
auxiliary electrode 33 overlap each other, the auxiliary electrode 33
faces the capacitor electrode 34 via the dielectric layer 27, so that a
capacitor C31b is provided. Accordingly, a capacitor C31 (a lightly
shaded portion in FIG. 1) obtained by combining the capacitors C31a and
C31b is provided between the capacitor electrodes 32 and 34.

[0042] On the surface of the dielectric layer 29, a capacitor electrode 35
is provided. The capacitor electrode 35 faces the capacitor electrode 34
via the dielectric layer 28, so that a capacitor C41 (an area filled in
with small dots in FIG. 1) is provided.

[0043] An inductor electrode 36 is provided on the surface of the
dielectric layer 26. The inductor electrode 36 is connected to an
external electrode 39 provided on the other main surface of the
multilayer substrate 20 including built-in capacitors via a via electrode
38 passing through the dielectric layers 26 to 29 in the lamination
direction.

[0044] The inductor electrode 36 is capacitively coupled to the capacitor
electrode 32 disposed close to the inductor electrode 36 in the
dielectric layer 26. In addition, the inductor electrode 36 is
capacitively coupled to the edge of the capacitor electrode 34 in the
lamination direction.

[0045] In the present preferred embodiment, since the auxiliary electrode
33 to which the capacitor electrode 32 is electrically connected via the
via electrode 37 is provided, the value of the capacitor C31 can be
adjusted by changing the area of the auxiliary electrode. The value of
the capacitor C31 can also be adjusted by changing the thicknesses of the
dielectric layers 26 and 27 to change the position of the auxiliary
electrode 33 in the lamination direction. More specifically, the value of
the capacitor C31 can be adjusted by changing the thicknesses of the
dielectric layers 26 and 27 while maintaining the distance between the
capacitor electrodes 32 and 34.

[0046] Thus, the value of the capacitor C31 can be adjusted without
changing the area of the capacitor electrode 32 or 34 and the position of
the capacitor electrode 32 or 34 in the lamination direction.
Accordingly, the value of the capacitor C31 can be adjusted independently
of the values of the capacitors C11 and C21 defined by the capacitor
electrode 32 and the capacitor C41 defined by the capacitor electrode 34.
Since the area of the capacitor electrode 32 or 34 and the position of
the capacitor electrode 32 or 34 in the lamination direction are not
changed, the state of capacitive coupling between the capacitor electrode
and the inductor electrode 36 is also not changed.

[0047] As described previously, by providing an auxiliary electrode
connected to a capacitor electrode via a via electrode, it is possible to
independently adjust only the capacitance value of a predetermined
capacitor without affecting the state of coupling between the capacitor
electrode and another element and the capacitance values of the other
capacitors.

Second Preferred Embodiment

[0048] The configuration of a circuit module according to the second
preferred embodiment of the present invention is illustrated in FIG. 2.
FIG. 2 is a cross-sectional view of a circuit module 10a. Similarly to
the first preferred embodiment, only electrode patterns related to a
characteristic structure are illustrated, and the illustration of the
other electrode patterns is omitted. Referring to FIG. 2, the same
reference numerals are used to identify elements already described with
reference to FIG. 1, and the description thereof will be therefore
omitted.

[0049] In this preferred embodiment, the capacitor electrodes 31 and 32
face each other so that the dielectric layer 25 and a dielectric layer
25a are sandwiched therebetween. On the surface of the dielectric layer
25a, an auxiliary electrode 40 is provided. The auxiliary electrode 40 is
electrically connected to the capacitor electrode 32 via a via electrode
41. The auxiliary electrode 40 is arranged in an area in which the
capacitor electrodes 31 and 32 face each other as viewed from the
lamination direction. Each of the capacitor electrode 32 and the
auxiliary electrode 40 faces the capacitor electrode 31, so that the
capacitor C21 (a dark shaded portion in FIG. 2) is provided.

[0050] On the surface of the dielectric layer 26, a capacitor electrode 42
is arranged close to the capacitor electrode 32. On the surface of the
dielectric layer 28, a capacitor electrode 45 is arranged close to the
capacitor electrode 34. The capacitor electrodes 42 and 32 are
capacitively coupled to each other in the in-plane direction of a
dielectric layer, and the capacitor electrodes 45 and 34 are capacitively
coupled to each other in the in-plane direction of another dielectric
layer.

[0051] The capacitor electrode 42 is connected to an auxiliary electrode
44 provided on the dielectric layer 27 via a via electrode 43 passing
through the dielectric layer 26. Each of the capacitor electrode 42 and
the auxiliary electrode 44 faces the capacitor electrode 45, so that a
capacitor C51 (a lightly shaded portion in FIG. 2) is provided.

[0052] Thus, for the capacitor electrode 32, the via electrodes 37 and 41
that are connected in the lamination direction and the auxiliary
electrodes 33 and 40 that are connected to the via electrodes 37 and 41,
respectively, are provided. Accordingly, the values of the capacitors C21
and C31, which include the capacitor electrode 32, can be adjusted
independently of the other circuit elements.

[0053] In addition, for the capacitor electrode 42 of the capacitor C51,
the via electrode 43 and the auxiliary electrode 44 connected to the via
electrode 43 are provided. Accordingly, despite the fact that the
capacitor electrodes 32 and 42 are close to each other on the same
dielectric layer and the capacitor electrodes 34 and 45 are close to each
other on the same dielectric layer, the value of the capacitor C51 can be
independently adjusted without changing the state of coupling between the
capacitor electrodes 32 and 42 and the state of coupling between the
capacitor electrodes 34 and 45.

Third Preferred Embodiment

[0054] The configuration of a circuit module according to the third
preferred embodiment of the present invention is illustrated in FIG. 3.
FIG. 3 is a cross-sectional view of a circuit module 10b. Similarly to
the first preferred embodiment, only electrode patterns related to a
characteristic structure are illustrated, and the illustration of the
other electrode patterns is omitted. Referring to FIG. 3, the same
reference numerals are used to identify elements already described with
reference to FIG. 1, and the description thereof will be therefore
omitted.

[0055] In this preferred embodiment, the capacitor electrodes 32 and 34
face each other so that the dielectric layer 25a and dielectric layers
25b and 25c are sandwiched therebetween. On the dielectric layer 25b, the
auxiliary electrode 40 is provided. The auxiliary electrode 40 is
connected to the capacitor electrode 32 via the via electrode 41 passing
through the dielectric layer 25a. On the surface of the dielectric layer
25c, the auxiliary electrode 33 is provided. The auxiliary electrode 33
is connected to the capacitor electrode 34 via the via electrode 37
passing through the dielectric layer 25c. The auxiliary electrodes 33 and
40 are arranged in an area in which the capacitor electrodes 32 and 34
face each other as viewed from the lamination direction. Thus, each of
the capacitor electrode 32 and the auxiliary electrode 40 faces the
capacitor electrode 34 and the auxiliary electrode 33, so that the
capacitor C31 (a lightly shaded portion in FIG. 2) is provided.

[0056] In this preferred embodiment, between the capacitor electrodes 32
and 34 of the capacitor C31, the auxiliary electrodes 33 and 40 are
provided. Accordingly, in order to adjust the capacitance value of the
capacitor C31, the area of the auxiliary electrode 33 or 40 is changed or
the thicknesses of the dielectric layers 25a, 25b, and 25c are changed
while maintaining the distance between the capacitor electrodes 32 and
34.

[0057] Thus, the value of the capacitor C31 can be adjusted without
changing the area of the capacitor electrode 32 or 34 and the position of
the capacitor electrode 32 or 24 in the lamination direction.
Accordingly, the value of the capacitor C31 can be adjusted independently
of the values of the capacitors C11 and C21 including the capacitor
electrode 32 and the value of the capacitor C41 including the capacitor
electrode 34. Since the area of the capacitor electrode 32 or 34 and the
position of the capacitor electrode 32 or 34 in the lamination direction
are not changed, the state of capacitive coupling between the capacitor
electrode and the inductor electrode 36 is not changed.

[0058] By arranging a plurality of auxiliary capacitor electrodes between
capacitors defining a single capacitor, the adjustable range of a
capacitance value is increased. As a result, design flexibility is
increased, and fine adjustment of a capacitance value can be performed.

Other Preferred Embodiments

[0059] A substrate including built-in capacitors according to the present
invention is not limited to the above-described preferred embodiments,
and can be variously configured within the scope of the present
invention.

[0060] For example, in the above-described preferred embodiments of the
present invention, a via electrode and an auxiliary electrode are
preferably arranged so that they are connected to a capacitor electrode
with which a capacitor is defined. However, only the via electrode may be
provided, and the capacitance value of the capacitor may be adjusted with
the via electrode. In this case, a plurality of via electrodes may be
provided. The connection between electrode patterns in a substrate may be
changed so as to allow a capacitor electrode to function as a ground
electrode.

[0061] In the first preferred embodiment of the present invention, a via
electrode and an auxiliary electrode are preferably connected to the
capacitor electrode 32. However, the via electrode and the auxiliary
electrode may be connected to the capacitor electrode 34.

[0062] In the third preferred embodiment of the present invention, a via
electrode and an auxiliary electrode are preferably connected to the
capacitor electrode 32, and another via electrode and another auxiliary
electrode are preferably connected to the capacitor electrode 34.
However, for only one of the capacitor electrodes 32 and 34, a via
electrode and an auxiliary electrode may be provided. The number of
auxiliary electrodes may be two or more.

[0063] While preferred embodiments of the present invention have been
described above, it is to be understood that variations and modifications
will be apparent to those skilled in the art without departing from the
scope and spirit of the present invention. The scope of the present
invention, therefore, is to be determined solely by the following claims.