These bits always reflect the status of the processor, therefore they only have a reset value if the particular reset event affects the processor. For example, a PRESETDBGn event leaves these bits unchanged and a processor reset event such as nSYSPORESET sets DSCR[18] to a 0 and DSCR[1:0] to 10. To use the Debug Status and Control Register, read or write CP14 c1 with: MRC p14, 0, , c0, c1, 0 ; Read Debug Status and Control Register MCR p14, 0, , c0, c1, 0 ; Write Debug Status and Control