Traditional design flows separate design implementation from physical verification. As shown in Figure 1, Talus QDRC operates during implementation, reducing the post-implementation DRC sign-off effort and therefore both shortening the final physical design verification stage of chip development and eliminating sources of errors due to data conversion and file management issues. Talus QDRC has access to all layout layers with IP reference views to identify common problems that can affect final sign-off downstream in the flow, including LEF-versus-GDS mismatch and problems with metal fill, and open/short detection. It also saves cycle time by eliminating the need to stream data out of and back into the implementation flow for DRC or layout versus schematic (LVS) analysis.

1. Integrated flow eliminates sources of errors.

"Talus QDRC improves designers' productivity by eliminating DRC problems early in the flow. The design implementation teams using Magma have better visibility and control of their designs as they move to tapeout because potential DRC errors are eliminated during implementation," said Kevin Walsh, vice president of marketing for Magma's Physical Verification Business Unit.
"Talus QDRC is easy to implement in virtually any existing flow: leading foundries support Talus QDRC with foundry-certified design rule runsets, and a runset translator enables users to run Calibre rules during Talus implementation by reading and converting Calibre decks to produce Talus QDRC rules" added Walsh.

Talus QDRC is available now. Magma customers will present case studies on the use of the new tool and Magma engineers will present a Talus QDRC tutorial at MUSIC, Magma's users group conference, Feb. 27-28 in Santa Clara, California.