Graphenea

Monolayer Graphene on SiO2/Si (4" Wafer)

Our monolayer graphene on SiO2/Si (4” Wafer, fully covered) is a bidimensional material produced by CVD and transferred to a circular substrate of Si/SiO2 (300nm) by a wet transfer process. We consider it to be a benchmark product in the graphene market - not only for its excellent quality, but also for its shape, size and number of applications.

Graphene Film

· Transparency: > 97 %

· Coverage: > 95%

· Thickness (theoretical): 0.345 nm

· FET Electron Mobility on Al2O3: 2000 cm2/Vs

· Hall Electron Mobility on SiO2/Si: 2000-3500 cm2/Vs

· Sheet Resistance: 450±40 Ohms/sq (1cm x1cm)

· Grain size: Up to 10 μm

Substrate SiO2/Si

· Dry Oxide Thickness: 300 nm (+/-5%)

· Type/Dopant: P/Bor

· Orientation: <100>

· Resistivity: <0.005 ohm·cm

· Thickness: 525 +/- 20 μm

· Front surface: Single Side Polished

· Back Surface: Etched

· Particles: <10@0.3 μm

Quality control

All our samples are subjected to a rigorous QC in order to ensure a high quality and reproducibility of the graphene. Each batch must pass the following tests:

· Raman Spectroscopy: I(G)/I(2D)<0.7; I(D)/I(G)<0.05

· Optical Microscopy inspection of each individual sample to ensure good transfer quality and purity

If your application requires more specific controls (AFM, SEM...) please do not hesitate to contact us.

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Frequently Asked Questions

A: It has to be done under dry conditions. When using wafers such as Si or quartz a diamond pen can be used to cleave it.
In order to protect the graphene film from debris, we recommend doing it with the protective PMMA layer on top of graphene. In this case, we can provide you the sample with the PMMA on top.

When using thin substrates such as PEN or PEN you can easily cut them using scissors.

A: In principle, additional cleaning is not needed and you can use our graphene directly. However, thermal annealing can be applied, typically at 250-400C under inert atmosphere in order to have a cleaner graphene and to reduce absorbents on the graphene surface.

A: Our graphene on SiO2 is p-doped, with a charge carrier density of around 1013 cm-2. This intrinsic doping can be reduced by at least one order of magnitude by thermal treatments, which lower the Dirac voltage down to 40-80 V. Another alternative is using a passivation layer on top of the graphene, which prevents the presence of water between the substrate and the graphene film.