​VHDL - Programming the Field Programmable Gate Array (FPGA)

Universal Shift Register

In this tutorial, we will design and implement a 4-bit universal shift register that can perform right shift, left shift, and parallel loading. Universal Shift Register is a register which can be arranged to load and retrieve the data in different mode of operation.Likewise, a universal shift register is a combined design of serial in serial out (SISO), serial in parallel out (SIPO), parallel in serial out (PISO) , and parallel in parallel out (PIPO.)This project requires four D flip-flops and four 4-to-1 multiplexers. We will also use component instantiating method and structural VHDL coding in Xilinx .​For this tutorial, we will be using a pre-designed D flip flop and 4 to 1 mux VHDL design codes. Then we will instantiate the components as requires to achieve the desired design out puts.​

​\(\color{red}{Note:}\) make sure you save the D flip flop and 4 to 1 mux in the same directory as the Universal Shift Register.As it is shown in the block diagram below, the design will have serial inputs, mode selector, parallel inputs, clock, clear signals, and output.

Universal Shift Register Block diagram

We will use multiplexers so that the register can perform left shifting, right shifting, and parallel loading depending on the selection on the multiplexer m(1:0).

M(1)

M(0)

Operation

'0'

'0'

do nothing

'0'

'1'

shift right

'1'

'0'

shift left

'1'

'1'

parallel load

​

Then, write a VHDL structural code for the D flip flop and multiplexer module by using the previously designed D flip flop & multiplexer.\(\color{red}{Note:}\) don't forget to write VHDL code the D flip flop and 4 to 1 mux (code not shown here) and save them in the same directory as the D-FF and Mux combined Module and Universal Shift Register (VHDL code shown below).

Then write a testbench code and simulate a wave form. Don't forget to adjust the simulation run time to at least 200ns to allow the testbench code goes through all the possible combinations of the inputs. Next, run the simulation to obtain a waveform similar to the figure shown below.

​

Waveform for Universal Shift Register.

Finally, generate a programming file (.bit), Connect the FPGA board to the computer and program the FPGA board using the ADEPT software.​