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This project did not reach completion.

The TAPR Frequency Hopping Spread Spectrum Radio project was moved to inactive
status in the fall of 2002 for two primary reasons. First, we were faced
with continuing parts obsolescence problems that resulted in continual
redesign, and second, we were unable to obtain the RF design expertise needed
to finalize the RF board.

An Amateur 900Mhz Spread-Spectrum Radio Design

System design principles and high-level design details are described for a new spread-spectrum radio design for the 900 MHz. Amateur band. The radio is designed to provide a 10-base-T interface as the data port, and is designed to provide transport of IP-based data. It is planned to provide both stand-alone and fully-networked hub configurations. The design is based on Frequency-Hopped Spread Spectrum (FHSS) spreading. Use of Forward Error Correction (FEC) and QPSK modulation should provide significant system gain performance compared to other FHSS FSK designs. The radio is currently in the printed-circuit board layout stage.

Introduction

Significant enhancement in the use and application of computer networking in the last 5 years has led to the need for high performance wireless interconnection of computers. Traditional 1200-baud and 9600-baud packet links are not able to provide adequate speed for today's web-based applications. Further, long-haul linking of multiple radios in linked configurations has proven difficult and unreliable. This can be seen from simple numerical analysis of the poor reliability of such multiple-hop configurations . One solution to the reliability issue is to utilize other transport facilities for most of the transmission distance, such as the Internet.

In industry, wireless is valued greatly for the ability to provide mobility. Thus, fiber optics has replaced radio in the long-haul telephony networks (for most, but not all applications), and wireless is increasingly looked upon as a replacement for the wire copper loop. This inverts the traditional view of the wired and wireless domains .

Applications

A high-speed mobile data access infrastructure to the Internet has many applications for the radio amateur, and could allow the provision of services and applications not possible with current commercial technologies. This is especially true as the Internet performance improves to support constant-bit rate multimedia services. Current audio coding technology provides quite acceptable audio at 13 kb/s. Videoconferencing is reasonably acceptable at 112 kb/s. Web browsing is possible at any speed, but only tolerable above 28 kb/s. A wireless interconnection technology that could support data rates in this range would provide the ability for the radio amateur to provide audio conferencing, via the Internet, from a mobile laptop computer to anywhere in the world in real time. Mobile laptop videoconferencing is similarly possible. Access to databases, maps, Email, etc., anywhere on the Internet in real time would make the utility of such a service very great. The radio amateur, equipped with such a capability could prove invaluable in many public-service scenarios. Indeed, the Internet not only addresses many of the problems of previous-generation packet networking, in fact it provides a powerful tool in its almost universal accessibility and rich diversity of information.

System Requirements

The design of a radio to meet the above applications is described. The general requirements are that the radio provide at least 128 kb/s throughput (more in other modes) while providing 20-mile coverage with 1-watt output power. 10-base-T was selected as the desired interface, and it is intended for connection to the LAN port of a laptop or other computer. It is envisaged that both a point-to-point configuration and a hubbed multi-point configuration would be supported. In the point-to-point configuration the radios would simply provide a transparent LAN interconnection pipe. For example, one radio might be connected to an Internet service, and located on top of a tall building, while the other end would be connected to a mobile laptop computer.

In the multi-point configuration, several radios are placed at a common site, such as a tall building. One channel becomes the control channel, and each of the remaining radios serves as a data channel. This provides for multiple users to simultaneously access the hub site. In the hub mode, all radios transmit and receive in synchronism. Additionally, good Internet connectivity might not be available at such a hub site, so individual data channels of the hub can be dedicated as fixed point-to-point links that provide a remote link to the Internet from the hub site. The radio design supports these configurations automatically with additional hardware. The control channel allocates access to idle data channels.

In the hub mode, the hub provides for dynamic assignment of IP addresses to the user computers via the DHCP protocol. This eliminates many of the difficulties of IP address administration in a mobile environment. However, it does not allow the user to move the computer from one node to another while connected. Instead the link will be broken and will have to be re-established with a new IP address.

Spreading Methods

Both Direct-Sequence Spread Spectrum (DSSS) and FHSS were studied. The Harris Prism chipset was initially investigated for such a radio. This chipset is designed to provide 802.11 wireless LAN for mobile laptop computers. However, this excellent chipset cannot easily provide the required system gain and performance required for a 20-mile link. It was intended to provide a low-cost low-power 1 Mb/s LAN interconnection primarily within a few 100's of feet. The Prism chipset utilizes DSSS modulation, and provides a spreading gain of only 12 dB. maximum, 11 dB typically. Further it is designed for the 2.4 GHz. band, which we felt would be difficult for average amateurs to equip with adequate antennas and feedline to meet the link distance requirement. We chose to implement the first radio design in the 900 MHz. Amateur band (902-928 MHz., a width of 26 MHz.) due to the availability of commercial components.

At first blush 20 dB of system gain (100:1 spreading ratio) within a 26 MHz wide band implies a maximum data rate of 26/(100*2) = 130,000 b/s. Since we also wanted the radios to operate half-duplex (to minimize cost), this maximum rate would be further reduced to 65,000 b/s. The data rate could be doubled if QPSK modulation is utilized, because it halves the spectral requirements. However, we noted in several spectrum analyzer sweeps of the 900 MHz band in Dallas, Texas that a large number of very strong narrow-band carriers are present. Testing with commercial part-15 radios indicated that these strong carriers render DSSS radios inoperative when the link distance was increased beyond one or two miles.

However, tests with FHSS radios under the same conditions proved to be more encouraging. Eventually, 20-mile links were achieved with one FHSS radio when the antennas were converted to horizontal polarization. Horizontal polarization reduced the amplitude of the interfering carriers by more than 20 dB. Thus an FHSS-based radio design was selected.

System Design Parameters

The parameters that were initially selected for the radio design are based on the availability of off-the-shelf SAW filters for the IF strip, what we felt was an achievable settling time for the frequency hopping VCO, available integrated circuits, and an aggressive but hopefully reasonable demodulator synchronization time. These parameters have been selected as follows:

Table 1 indicates the modes of operation that are anticipated.

The use of FEC and QPSK provides at least 9 dB improvement in system gain as compared to uncoded non-orthogonal Frequency-Shift Keying (FSK) which is utilized in almost all commercial part-15 radios. However, the use of coherent modulation techniques increases both the cost of the radio and the difficulty of the design. We felt the 9 dB. performance improvement made this tradeoff worthwhile. Fortunately, Harris provides a DSP-based digital Costas-loop QPSK demodulator IC (the HSP 50210) which appears to have sufficient programmability to meet the synchronization speeds provided that some clever algorithms ("quick-lock") are employed.

Two risks are felt to represent the greatest challenges in the radio design. First is the ability of the hopping VCOS to settle to adequate frequency accuracy and stability within 10 milliseconds. Second is the ability of the Digital QPSK loop demodulator to achieve synchronization lock with our special "quick-lock" technique. The prototype design will be used to assess these design risks.

Table 1 - Proposed Operational Modes:

Block Diagram

Figure 1 is a block diagram of the baseband processing, processor, and LAN Interface portions of the radio. Figure 2 is a block diagram of the RF and IF processing parts of the radio. The radio design is based on a Motorola 68360 microprocessor. It controls all major functions of the radio, and the LAN interface. A Motorola 68160 provides the 10-base-T Ethernet port. FLASH memory is utilized solely in the processor, to allow updates of the code at a later time without physically opening the radio or removing / programming any EPROMS.

Figure 1 - Block Diagram: Baseband Processing and LAN Interface

Circuit Description - Transmit Direction

The data from the LAN port is buffered by the 68360 and converted to a proprietary frame format based on HDLC and then sent to a Qualcomm convolutional coder IC. In modes 0 and 1, the coder produces two output bits for each input bit (rate = 1/2 mode). In mode 2, the code is punctured to rate = 7/8. These two bits become the in-phase (I-) and quadrature (Q-) channels to a Motorola QPSK modulator IC. The modulator IC provides raised-cosine roll-off at baseband of the two channels via an FIR filter. It also contains two D-to-A converters, and thus provides the I- and Q- analog baseband output signals.

The two baseband analog signal are connected to a Harris quadrature up-converter IC that generates I- and Q- signals at the IF frequency of 85.35 MHz. These signals are then further upconverted to the 902 MHz band, and filtered by a dielectric filter to eliminate the IF image frequency. It is then amplified by a Motorola integrated PA chip to about 100 milliwatts. The signal is routed through a PIN diode switch and through a pair of directional couplers to the antenna connector. The directional coupler signals are rectified and filtered, and fed to an A-to-D converter chip. These signals provide measurement of the forward and reflected power levels.

Figure 2 - Block Diagram: RF and IF processing

Circuit Description - Receive Direction

In the receive direction, the signals are passed through a dielectric filter (to eliminate the image frequency) and then to a Motorola low-noise downconverter IC. From there they pass through an 85.5 MHz, 600 kHz wide SAW filter and an amplifier. At that point, they are sent to a Harris downconverter IC which provides a large amount of gain through a two-stage limiter, and then downconverts the signal to baseband, producing the I- and Q- baseband analog signals. These signals are then digitized by a pair of 10-bit A-to-D converters, and sent to the Harris digital Costas-loop demodulator IC.

The demodulator IC first performs a complex frequency rotation to adjust for any frequency offset and phase error between the transmitter and receiver, then provides symbol timing and carrier frequency acquisition and tracking. Finally it provides AGC on the demodulated baseband signals, and performs a soft-decision threshold comparison of the I- and Q- channels against the reference level. These are in the form of two 3-bit words, one for the I-channel, and one for the Q-channel.

The pair of I- and Q- soft decision signals are sent to the Qualcomm Viterbi decoder IC. Is it capable of determining the synchronization boundary of the QPSK symbols, and decoding the FEC algorithm. The decoded bits (at one half the rate of the input bits in modes 0 and 1) are then sent to the HDLC portion of the Motorola 68360. The microprocessor recovers and removes the HDLC frame, and transmits the received data out the 10-base-T LAN port via the 68160.

Hopping VCOS

The design utilizes two VCOS in a pair of phase-locked loops (PLLS). While one loop is operational on frequency, the other loop is busy slewing to a new frequency. At the end of each 10-millisecond period, the new VCO becomes the active VCO and the previously active VCO is slewed to another channel. In this manner, each VCO plays leapfrog, being utilized half the time. This allows each phase locked loop 10 milliseconds to achieve satisfactory frequency accuracy before it is switched into service.

All of the RF-determining reference frequencies are derived from a single crystal-controlled oscillator. This oscillator is ovenized to minimize its error from the desired frequency during temperature excursions.

The actual programming of the VCO PLLS occurs by a small PIC chip (one-time programmable single chip processor). This chip contains the hopping sequence of the radios, and cannot be altered by the user. United States Department of Commerce regulations prohibit the export of FHSS radios from the United States if the hopping sequence can be altered by the user.

Synchronization

The most difficult part of any design is the synchronization of the transmitter and receiver, both in terms of the Transmit / Receive switching (T/R) and also in terms of carrier frequency acquisition. An initial synchronization interval occurs prior to the radios becoming linked. This takes some time to occur. The demodulator utilizes a sweeping process to recover carrier lock. However once this is achieved, the microprocessor is capable of reading out the frequency error at the receiver demodulator from the acquisition register in the demodulator. Based on the actual RF channel utilized during the initial synchronization, it computes the master-oscillator frequency difference between the transmitter and receiver. Subsequently, each time that the radio hops channels, the microprocessor computes the new effective frequency difference, and pre-loads the demodulator carrier recovery loop register with the proper frequency offset value to place the recovered carrier very close to the proper frequency. This helps the demodulator lock very quickly. This is the "quick-lock" technique referred to earlier.

Acknowledgements

We would like to thank the Tucson Amateur Packet Radio Corporation (TAPR), which is sponsoring this project.

Copyright 1997 TAPR.

Project Status Archives

January 2001

News from the Conference Call January 28, 2001

Digital Board Status:

After much Head scratching, software massaging and hardware hammering the crew reports that it is finally starting to see a glimmer of light at the end of the tunnel. To this date they have the following accomplished:

Ethernet interface is working.

The Serial interface is working.

Download of FPGA appears good.

The SDSI version 7.4 tools have their problems fixed and are working.

HTTP server is functioning properly.

Items that need to be tested and hammered out include:

The total DC current draw of the operating board.

Fully wring out the FPGA.

Check out the D-A converter base-band data output

Check out the A-D converter base-band data input.

Run the Harris demodulator through its' paces.

Check out the two screen shots that Tom McDermott has provided to get a preview of what things will look
like.

(Click on figures for larger view)

There have been many software fixes and programming changes made by Tom in this endeavor as well as the hardware hacking. It looks like it is now coming to fruition though with this progress report.

RF Board Status:

The crew reports that the Transmitter is getting good signals to the RF PA at this point but the output of the PA is only +15dbm instead of the +30dbm that it should be. One theory for this is that perhaps there is something wrong with the output-matching network. It was also learned that the RF T/R switch is showing in excess of a 10db loss on TX. The RF low-pass filter is showing the same problem on transmit, but on receive has a very small amount of loss.

The receive LNA has no gain showing, but on the bright side it is showing no loss either. That is about a 15db problem. Educated guesses point to the matching network on the output again for this problem.

The Mixer/down-converter is not producing an 85 MHz IF output. The LO signals are good, The RF signals are low due to the LNA problem mentioned earlier.

One other bright picture here is that the TX I/Q modulator has vary good carrier balance without null adjustment, running better than the -70 dBC measurement limit.

July 2000

In general, progress is being made. Testing continues on the RF board with good results and testing begins on the digital board.

A telephone conference call was made Sunday evening, July 16, 2000

Participants
were:

Dave
Cummings

Steve
Ludvik

Tom
McDermott

Fred
Peerenboom

John
Schroeder

Bob
Stricklin

A
lively discussion took place about the following items.

SCHEMATIC
DIAGRAMS:

Steve
L will email copies of the schematics of the boards (as-built) in PDF form to
project participants.

BOARD
LAYOUTS:

Steve
L will email copies of the RF board layouts (in Cadence-Allegro format) and
copies of the Digital board layouts in (Mentor-EDA-Connect format) to project
participants. Dave
C will print B-size drawings of both of the layouts and send them to Bob S, Tom
M and John S.

RF
BOARDS:

Bob
S reported the RF boards appear to be working. He had to make some component value changes and worked on the
PIC code to accomplish this. He
also added some LED functions to the PIC code to track program progress. He
reports the code is now revision 0.10 and will send a copy to Steve Bible when
he gets at least 3 frequencies working on the RF boards.

DIGITAL
BOARDS:

The
first project that Bob S and Tom M are independently working on is to get the
BDM (Background Debugging Mode) device operational. Then they will tackle
getting the memory working. They
report the memory SIMMS on the new boards are 16 Meg.

UPDATE:
On July 26, 2000 Tom M reports that getting the BDM working is a bit more
of a struggle than anticipated. He
has downloaded and installed the MacGreigor software in addition the SDSI
software, but both lads fail to bring up the BDM successfully. His work is
focused on Verifying proper BDM signals, pull-ups, AC termination of the clocks,
proper pin-out of the BDM and other items that can lead to premature baldness.
We all know from past history that this is a tough problem.
Once solved, however, rapid progress is usually made.

SUMMARY:

In
general progress is being made. Fred
P will call everyone in about two weeks to verify that all have received the
schematics and board layout files from Steve L. At that time he will also check on the progress that each is
making with their part of the project.

January 2000

Overall the project proceeds well. We had hoped to have the current version of the RF Board
in alpha testing before January 1st, but with the additional changes in parts on board (to help
with fabrication later in the process) the RF board alpha sliped into first quarter 2000.
Once the final review of the new layout is complete, the process of board production and then fabriation to get us
to testing should be quick. When the RF board goes into fabrication the digital board will be starting into the layout process at the new production house. This will allow the digital board to come out about the time we have the RF board testing completed. This is the plan for now.

A digital board design review was held January 1st, 2000 in Dallas, Texas.

Attending the meeting:

Greg Jones

Steve Bible (Conference Call)

John Schoreder

Bob Stricklin

John Koster

1. PIC Code
The meeting started with a conference call made to Steve Bible regarding
the current status of the PIC chip for the RF board. Steve reports that
his is about completed with the programming, but requested some additional
information in order to complete the project.
Discussion covered the table look up issues and we would send the
information regarding the double indexed look up table as soon as possible.
Steve feels he will be ready when the RF boards are available for testing.

2. PIC and RF Testing
The group discussed testing of the RF board and PIC chip. John S will post
information that was discussed on testing the RF board.
The group agreed that the most effective way would be to lift two pins on
the PIC chip and connect a Max232 interface board to allow a program to
simulate the SPI calls that the controller board would provide.

3. Digital Board Schematic Review
The digital schematic was reviewed. The group proceeded to move through the
list of issues to be covered on the digital board. A lot of the changes
took place on the new circuits required to support the new Lvl1 Ethernet
interface chip we are changing to. Changes made as a result of the meeting
where made at the time and reviewed by the group. It helped
doing this meeting at Bob's house so he could pull up the necessary files
for review and change. Action items reflect the additional changes
or information needed. Once these items are provided and solved we should
be able to send the schematic capture to Steve L for layout to begin.

4. RF Board
Steve L will be sending the cadence files to David C and John S for final review
before the next board run/fab takes place. John S requested further information from
Steve L regarding the state of
the RF boards that will be delivered for testing, so that he and David
could begin to develop necessary test equipment interfaces.

Summary

Overall the project proceeds well. We had hoped to have the current version of the RF Board
in alpha testing before January 1st, but with the additional changes in parts on board (to help
with fabrication later in the process) the RF board alpha slipped into first quarter 2000.
Once the final review of the new layout is complete, the process of board production and then fabrication to get us
to testing should be quick. When the RF board goes into fabrication the digital board will be starting into the layout process at the production house. This will allow the digital board to come out about the time we have the RF board testing completed. This is the plan for now.

October 1999

TAPR has signed an agreement with the Dandin Group to take the TAPR design
from its current state into production which TAPR has access to production
for sale back into the amateur radio community. This is an agreement we
have been working on for several months. The bringing together of TAPR's
and Dandin's capabilities will help the speed of the project tremendously.
We will be reporting more information in the next PSR about the progress of
development.

There was a RF Board design review held October 15th, 1999.

The Dandin and TAPR groups meet Sunday, October 3rd, in Dallas, Texas to hold the RF design review and move the RF design from TAPR into Dandin.

Attending the meeting:

Greg Jones, TAPR

Tom McDermott, TAPR

Steve Bible, TAPR

Steve Ludvik, Dandin

David Cummings, TAPR

John Schoreder, TAPR

Bob Stricklin, TAPR

John Koster, TAPR

Steve L (of Dandin) will be keeping the master schematic changes during the meeting with Tom M keeping the secondary notes. These will be checked against each other once the updated schematics are available.

Functional Review
Tom went through the functional and operational design of the project. Steve L had brought his block diagram of the design and the group used this as a tool to follow the discussion and resolve identification of blocks to overall operations within the radio.

Interfaces
The group resolved interface issues and assigned/changed interface specs to reflect current state of development. Further resolution on the interface was made later during the schematic review. These interfaces are noted on the master schematic.

Connectors
The group resolved for the prototype run the connector issues. Later in the meeting the master connector was broken into two connectors (Analog and Digital). These changes are noted on the master schematic.

Layout and Physical Issues
The group discussed the layout and physical issues of the design. Steve L showed one of his examples of RF packaging. It was agreed later in the meeting that the current foot print would be kept during the layout of the board, but if the design allowed shrinkage Dandin would shrink the layout on the current size board (i.e. more blank board area that can be removed later).

Schematic Review
The group did a component by component review of the design. Several changes and corrections were made to the master schematic as the group discussed the current design. Several actions items were produced during this review (see below)

PIC
The group discussed the PIC controller on the RF Board. Steve Bible, who will be taking on the PIC programming, reviewed the PIC device and the group reviewed and made changes to the schematic in order for the design to work properly with the PIC selected. The group reviewed the operational working of the PIC with the overall design.

Other Issues
The group needs to develop a Test plan for when the prototypes arrive. Individuals will post their thoughts to the list on this subject and we will develop a test plan in the coming month.

The power supply or the location of a contract mfg for the power supply is an open item.

TAPR will be ready to hand off the Digital Board to Dandin in November sometime.

Conclusion
I want to thank everyone that attended the RF board review for making it such a successful meeting. The goals of 1. attain closure on key issues regarding the RF board, 2. be able to allow Dandin to take over RF layout, 3. gain clear understanding of goals for the next 2-4 months, and 4. increase the communications between the two groups and the participant members were all achieved.

Steve Ludvik, of the Dandin Group, working on a circuit analysis with Bob Stricklin and Tom McDermott.

The RF and Digital Boards.

August 1999

To update the status of the TAPR FHSS radio project: we brought on two additional members to the design team a few months ago, John Schroeder, K5ZMJ, and David Cummings, WA5TET. John and David have been working on revising the RF board. We found that due to a miscommunication with our board shop, that the dielectric thickness between the board core and the outer signal layers was only 7.5 mils, instead of the expected 25 mils. This lowered the effective impedance of the 50-ohm microstrip lines down to 21 ohms, which has caused problems with the RF signal levels. Additionally, several of the RF components that we used on the original layout of the RF board have since been discontinued. So John and David are redesigning the RF board to eliminate those parts, and substitute them for more general-purpose parts that we hope will have a longer production lifetime.

A more difficult part cancellation was that of the Motorola MC145750 QPSK modulator component. This part provided a number of functions in a single, compact IC. Unfortunately only having available limited documentation we were not able to get the phase-locked loop on it to operate. This, coupled along with it's production cancellation has forced us into a difficult redesign. Several years ago this type of redesign would have been virtually impossible for us to cope with, but thanks to improving FPGA technology, we are going to implement the baseband FIR filters for the modulator in a Xilinx FPGA (Field programmable Gate Array) component. One of the great difficulties with high-speed digital data radios is implementing the modulation filters. We need a large number of taps with a significant amount of precision of the coefficient values. The processing requirements (high data rate, lots of taps) places the computational load beyond what almost any general-purpose software-programmable DSP chips is able to accomplish. Fortunately, Xilinx has released a 'core' generator for their FPGA parts which implement in bit-serial arithmetic symmetric and non-symmetric FIR (Finite Impulse Response) digital filters. Our computation shows that they will be just fast enough to implement our modem filters. These filters will provide square-root of raised-cosine shaping to the transmit baseband I- and Q- channels. This logic will be added to new logic we have to generate for differentially-coding and word-formatting the QPSK symbols. Previously, we had also implemented the symbol-timing recovery logic in a small FPGA for the Harris QPSK demodulator, so we can put all of these different logic functions into a single Xilinx device.

Current estimates are that it will take about 40,000 gates of logic to fit all of this into a single FPGA. We've identified the proper parts, and the costs are within the design tolerance. Fortunately, the part comes in a 100-pin quad leaded flat pack that is amazingly small, so Bob Stricklin, N5BRG is confident he can fit it and a new dual D/A converter all onto the existing digital board. The D/A converter is from Analog Devices - it provides 2x interpolation of the signals which reduces the demands on the reconstruction filters after the analog output port. All the parts are surface-mount, and the FPGA has small lead spacing (about 20 mils) like the Motorola processor part (get out your microscope to probe these parts!).

All of these changes will result in the interface between the digital and analog radio boards being changed to baseband I- and Q- in both the transmit and receive directions. One benefit of doing this is that we will be able to test many of the receiver functions of the digital board by looping back the transmit signals to the receive signals. It also removes all of the digital baseband processing form the RF board - so hopefully the RF board will be easier to port to new frequencies in the future.

We now have design kits for the Xilinx components, and have begun coding and testing the logic. The Xilinx parts contain internal RAM to implement the logic configuration of the gates. Normally, a serial FLASH prom is used on the PC board to load the Xilinx part with it's logic functionality. We are instead going to implement a loader in the 68360 microprocessor. This will allow us to put all of the logic for the part into the software configuration of the radio, and alter the actual logic in the part with updates to the software, only. The code will be in the microprocessor's FLASH memory, and the processor will download the FPGA during the boot-up time.

Unfortunately, all of this redesign and component substitution has of course delayed the project. Our hope is that by beefing up the design staff we can put the RF and baseband design efforts in parallel, and keep things moving. One lesson learned is that ham radio projects now have to be finished within the production lifetime of the components used on the project - and those times are shrinking FAST!

April 1999

The team has found and fixed about four bugs in the radio transmitter section and are now getting about 35 milliwatts output power at 915 MHz (should be 100 mW, but this is only 5 dB. away). Bob Stricklin, N5BRG, needs to get the -5v supply working before we can test the T/R switch and see how much of this gets to the antenna connector.

This development will allow signal tracing back down the receiver path on the radio. 35 mW on the transmit board provides a strong signal on the receiver for troubleshooting.

Tom McDermott is experimenting with two different acquisition algorithms and derived the analytic performance of one of them. He will continue to run simulation determining which acquisition algorithm we will want to try to use in the first radio.

March 1999

During the TPRS Fall Digital Symposium, held in Austin on December 12th there was a lot of discussion about connecting radios to Internet Service Providers, based on actual experiences reported first hand. Joe Borovetz, WA5VMS's, experiences in working with his ISP and past discussion at conferences makes it seem that the first level of networking of the radio should be basic LAN bridging. This would be easier to setup and configure than routing in the early stages of deployment, where a city will have a handfull of radios to begin with.

As a result, we have modified the XINU stack on the radio to incorporate a 6-port software Ethernet switch between the TCP/IP stack and the Ethernet interface. This switch interfaces at the Ethernet-frame level (layer 2) between the radio stack and the 10-base-T port on the TAPR radio. It is an Ethernet learning-bridge, and appears to be compliant with IEEE 802.1D specification for learning bridges.

This required modification of some of the modules in XINU, and the inclusion of several new modules dealing with layer 2 switching. This has been completed and tested (as much as we can without the radio link). The stack and the 10-base-T ports have been verified to operate properly through the switch.

The learning bridge provides some intelligence so that LAN bridges will not forward unnecessary LAN traffic across the radio link, while still allowing transparency in the LAN bridging for ARP and other broadcast protocols. Additionally, the switch allows the stack on one radio to talk to the stack on another radio. This allows configuration and status control of a stack from both the near and far ends of a radio link.

The solution that has been implemented results in a radio with one IP address (the on-board stack) and one Ethernet address (the 10-base-T port). The radio link shares the Ethernet address from the 10-base-T port so that the bridging tables on the two radio will properly synchronize automatically. The layer-2 switching function assures optimum usage of the bandwidth on all three ports: radio, stack, and 10-base-T. Discussion with some of the hams at the meeting who work at Internet Service Providers (ISPs) and Internet Network Access Providers (NAPs) indicates that this solution should work well with minimized setup difficulties.

December 1998

Project Meeting

The development group meet for a social/review meeting on November 28th,
1998. The goal of the meeting was to have some food and discuss the
project.

As of the meeting, the RF board is transmitting a QPSK modulated signal on
a single frequency of 913MHz. Basic functionality has been demonstrated; however, there's
a lot more to test on the TX side of the design. There has been really good progress made in a short
period of time.
This was a major
milestone reached. Work will start to check out the receiver when the transmitter is a little further along. This
testing will be more difficult but since a lot of the circuitry is common
there is less to check out. A second unit will have to be completed,
including known modifications to the PCB, for this testing.

The digital board CPU, network interface and the Qualcomm forward error
correcting (FEC) chip Q1900 is working. We are also able to communicate
with the QPSK decoder registers. Initial testing indicated that a more
elaborate PLD solution would be required to support the high speed phase
adjustments and to support the odd clocking required for FEC. A design is
completed and ready for test and debug. A small PCB will be built to test
this before we make another pass at the digital PCB. The group has discovered
that high-speed phase adjustment is needed for Harris QPSK
demodulator. The PLD has some
350-500 gates of logic.

The group has been very happy with the performance of the Qualcomm part.
Thanks to Frank Anontio, N6NKF, for his assistance in getting us the samples
we require for the project.

The Software/Firmware is in place to handle the key networking interface and to
continue radio testing. Current plan is to use an HTTP interface to control
and test the radio functions. A PC based tool to interface with the radio
using UDP packets also works. The httpd software on the radio is working and the radios basic parameters can be accessed via a
web page and reconfigured.

Also, the group has decided to use a
Dallas Semiconductor Button part in the project. The "button" is a two
wire interface which provides a registered MAU
ethernet address for the radio.

The function of the hardware and software is so complex that each
small section of the radio must be proven before we can move on to the next
issue.

The projects moves forward, but as each small step is taken we can see just
how much more work will be required before we have a fully functioning
high-speed radio available.

Until the next report.

Status update for the FHSS radio project.

The SPI driver is written and working. The protocol module for the interface
to the PLD is written, but cannot be tested until the PLD is ready, and that's a ways
down the road.

HTTP/1.0 daemon is written, and code to send/receive HTML files is working.
This allows using a web-browser to read the configuration from the kernel, and
updating some of the parameters. The final parameter save portion is just stubbed
off right now until we settle how they are stored and configured in memory. But
can demo the operation from a browser and it looks nice.

Further testing of the Ethernet performance occurring. Getting started writing a
layer-2 demultiplexer in the TCP/IP stack. The current XINU stack only performs
layer-3 routing, and has no layer-2 functionality. This will then feed some new
software that does segmentation of the ethernet frame to fit into the radio's
10 millisecond transmit periods, and then encapsulate it with the radio link protocol.
Layer-2 demultiplexing will probably require some frame cloning on ethernet packets
containing broadcast addresses (sending the copy to layer-3).

November 1998

The Digital Board is fully operational with the OS and Stack. The project team has gotten the Qualcomm Q1900 convolutional coder/decoder (Viterbi decoder algorithm) working. The team is now ready to move on to sending coded I+Q data to the QPSK modulator on the RF board.

The project team has gotten the Qualcomm Q1900 convolutional coder/decoder (Viterbi decoder algorithm) working on the FHSS board. They are now able to send HDLC packets from the 68360 to the Q1900, loop them around with a couple of wires and accurately decode them with the Q1900. They then can send them to the HDLC receiver on the 68360 and successfully receive the frames. This means that the register and HDLC driver code is working, and the clock, data, timing and signals into and out of the Q1900 are functional. The spec sheet for the Q1900 leaves a lot to be desired in the timing department - basically they ended up measuring all the signals with a scope to figure out what it is doing.

The digital board still needs to have the Harris DSP and the 2 A/D's checked out, but most of the digital board is now working properly. The team is now ready to move on to sending coded I+Q data to the QPSK modulator on the RF board. Bob Stricklin, N5BRG, has been working on that board, and is checking out some undocumented operational aspects of the Motorola part (like how it syncs the I/Q line).

The goals for the short term include:

Install the Qualcomm and Harris parts on the digital board being tested. Write access routines in C to talk to the registers on both parts. These routines handle the strange way the Harris part communicates and handles the addressing offset to the registers. The Harris stuff is working, but the team hasn't tested the Qualcomm stuff yet, but it should be easier to do I/O than the Harris stuff, by far!

Install a Dallas Semiconductor DS2401 electronic serial number chip on the board being tested. This uses PB4 to communicate to the processor. Have C code working to pull the 48-bit serial number out of the part. This will become the Ethernet MAC address for the board. Will code it so that if the DS2401 cannot be read for some reason, that a default MAC address will be utilized from the conf.h file, and an error message will be dumped on the console.

Add the code to the 22V10 to do the decoding of chip-select and Read/Write for the Harris part, and the clocking for the Qualcomm part. Bob has installed a harness on it so that it can be reprogrammed right on the board. Really slick, Bob!

Complete the port from our current XINU 7.2.2 to version 7.9.

Program the HDLC serial channel on the 68360 to talk to the Qualcomm chip.

As reported in the last report, the VCOs are operational on the RF board. Now that the major elements of the digital board are completed, the team is not focusing on the RF side of the project. Getting the OS and stacking running before the 1998 DCC was a major achievement.

Some of the goals regarding the CPU board include:

CPU operational test, register verification (Complete Jan 98)

verify BDM working (Complete Jan 98)

RAM + FLASH testing (Complete Feb 98)

Ethernet I/F working

Develop stack running (Complete Aug 98)

exchanges ethernet packets

360 register I/O code

PC display / control of 360 registers

PC display / control of VLSI registers

Write PIC & 360 code, use simple stack to verify: (Under Test)

all VLSI registers can be read/written

(HARRIS, QUALCOMM, etc.)

360 can talk to/from PIC

360 can read/write packets via Ethernet I/F

360 can talk on HDLC to Viterbi chip for data

Modify PCB artwork and rebuild CPU board (Complete Aug 98)

The VCOs are now operational on the RF board and further testing of each
section is underway. Some of the goals regarding the RF board include:

Verify VCO spectral characteristics (Complete Jan 98)

Put Motorola QPSK encoder on board, drive from PIC (Under Test)

Add HARRIS 3724 Mod/Demod, test (Under Test)

Add Tx mixer, Tx PA, T/R switch

Add Rx down converter, IF post amp

Loopback testing

Turn RF board artwork

Here are a few images taken during the two meetings. Click on the photos to see the larger version

A photo of the CPU board Rev 2. CPU is operational. RAM (72 pin SIMM top). Flash (two chips in center). The CPU board is operational with both the OS and TCP/Ip Stack working on it!

A photo of the RF board Rev 1.

The RF and Digital boards connected. The BDM debug interface is seen in the upper right corner.

Tom McDermott, N5EG.

June 1998

The kernel for the radio is ported and is being debugged. The hardware problem still exists with getting the Ethernet port to work correctly, but the teams feels that the next alpha run of the digital board will clear that problem up. The emphasis in the last 3 months has been on the digital board and kernel, thus the RF board has not changed status -- operational at baseband.

The development group meet for a design review meeting on
June 28th, 1998. The goal of the meeting was to set goals for
the upcoming 6-8 months and review past progress.

As of the meeting, the digital board is about to be put into a second revision to eliminate the errors in the first board. Most of the digital board is fully tested, except for the ethernet interface. The interface shows intermittents during testing and the group feels that the cleaned up board should eliminate the problem.

The basic kernel is operational on the board, with the exception of the Ethernet driver module. The serial, timer, and several other modules have had to be rewritten from the ground up. It is expected the the ethernet driver may take 2 months to fully rewrite and get functional, since the manner in which the kernel handles the buffers might have to be optimized for our processor. As was discussed last issue, we have acquired a copy of XINU (a preemptive multitasking, prioritized scheduler) and a full-blown TCP/IP stack based on the design in the books by Doug Comer. We have to change the assembly modules, and port the code over from a SUN 3 workstation to the 68360 design. The total RTOS/STACK design is 630 different software code modules! Once the kernel/stack is operation, then we actually have to write the radio code. The Software Development Systems Inc (SDS) development tools have worked out very good. The tools include a Crosscode complier suite and singlestep on chip debugger.

Some of the major goals achived in the last 6 months include:

CPU operational test, register verification (Complete)

verify BDM working (Complete)

RAM + FLASH testing (Complete)

Ethernet I/F working (Partial)

Modify PCB artwork and rebuild CPU board (Begun)

Some of the future goals regarding the CPU board include:

Develop simple stack running (Partial on commerical board)

exchanges ethernet packets

360 register I/O code

PC display / control of 360 registers

PC display / control of VLSI registers

Write PIC & 360 code, use simple stack to verify (Started)

all VLSI registers can be read/written

(HARRIS, QUALCOMM, etc.)

360 can talk to/from PIC

360 can read/write packets via Ethernet I/F

360 can talk on HDLC to Viterbi chip for data

As reported in the last report, the VCOs are operational on the RF board. Further testing of the RF board has been delayed while the group has focused on the digital board The purpose being to get the digital board going so that more software people can be brough onboard to help, while the RF board gets worked on. Some of the goals regarding the RF board still include:

Verify VCO spectral characteristics (Complete)

Put Motorola QPSK encoder on board, drive from PIC ((temporary data))

Add HARRIS 3724 Mod/Demod, test

Add Tx mixer, Tx PA, T/R switch

Add Rx down converter, IF post amp

Loopback testing

Turn RF board artwork

Until the next report.

March 1998

The project team has decided to do all development around XINU, since the full source is freely available and meets the needs of the project. As of this writing, the software group has ported the code to the CPU board and is currently testing and debugging.

January 1998

Meeting to discuss short term goals and overall strategy for next 6-8 months. CPU operational as of this meeting and memory under test. RF board being brought up one section at a time. VCOs operating as modled.

The development group meet for two in-depth design and review meetings on
January 2nd and 3rd, 1998. The goal of the meeting was to set goals for
the upcoming 6-8 months. You can see some photos from the meeting at
http://www.tapr.org/tapr/html/taprfhss.html.

As of the meeting, the digital board is coming to life with the CPU starting to function. The Flash memory and RAM are now being tested. Then the network interface will be checked out. When this is done code development for the radio can really get underway. Initial code development and testing with the Motorola MC68360 will be done with a the simple 8 pin BDM. interface described in the Motorola literature. At this time we do not have access to the more expensive tools which would reduce development time. Real progress on the project is visible with major sections of the RF board functioning and the CPU operational on the digital board.

Some of the goals regarding the CPU board include:

CPU operational test, register verification (Complete Jan 98)

verify BDM working (Complete Jan 98)

RAM + FLASH testing (Complete Feb 98)

Ethernet I/F working

Develop simple stack running

exchanges ethernet packets

360 register I/O code

PC display / control of 360 registers

PC display / control of VLSI registers

Write PIC & 360 code, use simple stack to verify:

all VLSI registers can be read/written

(HARRIS, QUALCOMM, etc.)

360 can talk to/from PIC

360 can read/write packets via Ethernet I/F

360 can talk on HDLC to Viterbi chip for data

Modify PCB artwork and rebuild CPU board

The VCOs are now operational on the RF board and further testing of each
section is underway. Some of the goals regarding the RF board include:

Verify VCO spectral characteristics (Complete Jan 98)

Put Motorola QPSK encoder on board, drive from PIC (temporary data)

Add HARRIS 3724 Mod/Demod, test (temporary data)

Add Tx mixer, Tx PA, T/R switch

Add Rx down converter, IF post amp

Loopback testing

Turn RF board artwork

There has been a lot of discussion regarding development environment. In
the short term, the group can use existing public domain development tools
for the initial tests, but a more substantial complier, assembler, linker
will be required past the initial testing. Several packages are being
examined with diab??? being a leading choice.

Some of the goals in the development environment tools area are to ensure
the requirements list is meet for the selected items:
Assembler
C compiler (C++ preferred) with assembly source
output capability, viewable as text
Linker for multiple C++/Asm modules
Symbolic Debugger (C++)
Means for debugger to interact with target proc.
(most likely BDM Interface)
Runs on PC platform
Identify Vendor, Ident configuration for above requirements
Price the package, secure funding

Several people have inquired about what software will be developed. While
the team is continuing to discuss this, no decision has to be made until we
get past many of the initial issues of getting the radio operational. A
first thing to work on will be the selection or the development of the
kernel and an OS for the CPU, in order to help programming past the initial
test phase. An important issue is to select something that will allow
others interested in developing code the ability to do something. The team
has examined several stacks and kernels and is currently looking seriously
at XINU as the environment for the radio.

Here are a few images taken during the two meetings. Click on the photos to see the larger version

Spectrum Analyzer showing one VCO in a test transmit. The RF board is attached on the right side. The VCO is outputting a single constant frequency, about 1.022 Ghz. The VCO's hop in about 6 milliseconds, but are held at a constant frequency for this display. The RF board has two VCO's, PLL circuits, TCXO, and buffers installed. The RF mod/demod, and other parts are not yet installed.

Close up of RF board attached to spectrum analyzer.

Closeup of high resolution spectral analysis of the VCO output. Vertical is 10 db/div. This shows phase noise of LO is reasonably near the expected value. The VCO is not hopping for this test. The reference-frequency sidebands can not be seen in this photo, but they are about -60 dBc (the reference frequency for the PLL is about 100 khz.).

A photo of the CPU board. The CPU (right) is operational and the RAM (72 pin SIMM top) and Flash (two chips in center) are being debugged and tested. The cable is connected to the BDM interface which is used for testing and development of the board.