8.4. About the TCMs

The processor has two TCM interfaces to support the connection
of local memories. The ATCM interface has one TCM port. The BTCM
interface can support one or two TCM ports. Each TCM port is a physical
connection on the processor that is suitable for connection to SRAM with
minimal glue logic. These ports are optimized for low latency memory.

The TCM ports are designed to be connected to RAM, or RAM-like
memory, that is, Normal-type memory. The processor can issue speculative
read accesses on these interfaces, and interrupt store instructions
that have issued some but not all of their write accesses. Therefore,
both read and write accesses through the TCM interfaces can be repeated.
This means that the TCM ports are generally not suitable for read-
or write-sensitive devices such as FIFOs. ROM can be connected to
the TCM ports, but normally only if ECC is not used. See Hard errors. If the access
is speculative, the processor ignores any error or retry signaled
on the TCM port.

The TCM ports also have wait and error signals to support
slow memories and external error detection and correction. For more
information, see External TCM errors.

The PFU can read data using the TCM interfaces. The LSU and
AXI slave can each read and write data using the TCM interfaces.

Each TCM interface has a dedicated base address that you can
place anywhere in the physical address map, and must not be backed
by memory implemented externally. The ATCM and BTCM interfaces must
have separate base addresses and must not overlap.