SAS 6G Target IP Core – IPC-SS107-DT

The IntelliProp SAS Target Core (IPC-SS107-DT) is an industry standard
Serial-SCSI (SAS) core that enables device applications to connect to high
throughput SAS storage devices. The protocol interface is compliant to the
SAS specification as defined by the ANSI T10 Organization. As with all
IntelliProp cores, the IPC-SS107-DT core is fully verified in pseudo-random
simulation.

The IPC-SS107-DT is available for integration into target side ASIC and FPGA designs to provide an industry compliant SAS 3.0 and 6.0 Gb/s interface. Some of the target applications for the IPC-SS107-DT core are:

Internal interconnect for workstation and server storage

External workstation/Enterprise Storage interconnect

HDD /SSD hot-swap environments

SAS 6G Target IP Core Features

Fully compliant to the SAS 3.0 and 6.0 Gb/s industry specifications

Processor specific interfaces for register access.

Supports either SerDes, PIPE, or SAPIS interface

Synchronous design for easy integration

Configurable memories for performance and area trade-offs

Supports OOB and speed negotiation sequences

Auto open connections and close connections

Auto Credit management

Auto ACK/NAK transmission

Provided with the SAS Target IP Core

Documentation:

Comprehensive User Documentation

Design File Formats:

Encrypted Verilog

Constraints Files:

Provided per FPGA

Verification:

ModelSim verification model, Testbench and Drive Models

Instantiation Templates:

Verilog (VHDL wrappers available)

Reference Designs & Application Notes:

Synthesis and place and route scripts

Additional Items:

Simulation Script, Sample Vectors, Reference Design

Simulation Tool Used:

ModelSim (contact IntelliProp for latest versions supported)

Support:

The purchased core is delivered and warranted against defects for 6 months from the date of delivery. Phone and email technical support is included for 6 months from the delivery date.

Notes:

Other simulators are available. Please contact IntelliProp for more information.

Functional Description

The IPC-SS107A-DT is designed to be connected to a SAS-compliant host application to send and receive Out-of-Band (OOB) signals, primitives, and SAS frames. The SAS target core, as shown in the block diagram, is comprised of four blocks (PHY layer, LINK layer, PORT layer, and TRN layer), and the processor, SerDes, and Memory interfaces.