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S25FL128S VIO timing requirment

I'm using S25FL128S with VIO=1.8V. I found a "strange" requirement in S25FL128S datasheet, which says:

Apparently, the VIO have to track VCC, which is hard to be satisfied.

I checked schematic of ZC706, and didn't found any special design about VIO-VCC timing and tracking. So I'd like to know, what will happen if VIO doesn't satisfy the requirement of datasheet? Is Xilinx considered this requirement, or just ignored it?

回复： S25FL128S VIO timing requirment

Do you need a versatile I/O interface at your design? If not, why just ignore this? Simply connect this pin to Vcc and all will goes well.

I don't think any Xilinx board makes use of this versatile interface as there is no need. SPI<->FPGA usually has a I/O connection at a constant voltage level.

If you have a certain chip and the interface would change voltage levels at a real time, you can use this Vio, then yes, you need to track Vcc during power-up stage. If you cannot satisfy it but you still need to use it, you should consult Cypress about the possible consequences.

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