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Abstract:

The invention relates to a process for manufacturing a semiconductor
structure comprising a functionalized layer on a support substrate,
comprising the following steps: (a) implanting ionic species in a source
substrate comprising the said functionalized layer and a sacrificial
buffer layer located under the functionalized layer relative to the
direction of implantation, to a depth delimiting the thickness of an
upper part of the source substrate comprising the functionalized layer
and at least part of the buffer layer; (b) bonding the source substrate
to the support substrate; (c) fracturing the source substrate and
transferring the upper part of the source substrate to the support
substrate; (d) removing the buffer layer by selective etching with
respect to the functionalized layer.

Claims:

1. A method of manufacturing a semiconductor structure, comprising:
implanting ionic species into a source substrate comprising a first
support substrate, a first functionalized layer on the first support
substrate, and a sacrificial buffer layer, the first functionalized layer
including a first metal conductive electrode at a surface of the first
functionalized layer, the sacrificial layer located under the first
functionalized layer relative to a direction of implantation of the ionic
species into the source substrate, wherein the ionic species are
implanted at a depth delimiting a thickness of an upper part of the
source substrate, the upper part comprising the first metal conductive
electrode, the first functionalized layer, and at least part of the
sacrificial buffer layer; providing a second support substrate including
a second functionalized layer, the second functionalized layer including
a second metal conductive electrode at a surface of the second
functionalized layer; bonding the source substrate to the second support
substrate, the first metal electrode and the second metal electrode being
at a bonding interface; fracturing the source substrate and transferring
the upper part of the source substrate from the source substrate to the
second support substrate; and removing the sacrificial buffer layer by
selective etching with respect to the first functionalized layer.

2. The method of claim 1, wherein the sacrificial buffer layer comprises
a layer for confinement of the implanted species.

3. The method of claim 2, wherein the layer for confinement of the
implanted species comprises a confinement zone of the sacrificial buffer
layer that is doped with boron.

4. The method of claim 1, wherein a thickness of the sacrificial buffer
layer is between 10 nm and 1 μm.

7. The method of claim 1, further comprising applying a heat treatment
for repairing defects in the transferred first functionalized layer at a
thermal budget lower than a thermal budget at and above which the first
functionalized layer or the second support substrate is damaged.

8. The method of claim 1, wherein bonding the source substrate to the
second support substrate comprises annealing the source substrate and the
second support substrate at a temperature of between 200.degree. C. and
500.degree. C.

9. The method of claim 1, wherein the first metal electrode and the
second metal electrode comprise a metal selected from the group
consisting of tungsten, titanium, platinum, cobalt, nickel and palladium.

10. The method of claim 1, wherein the sacrificial buffer layer comprises
a material that allows selective etching of the sacrificial buffer layer
with respect to a material of the first functionalized layer.

14. The method of claim 12, wherein the sacrificial buffer layer
comprises a material that allows selective etching of the sacrificial
buffer layer with respect to a material of the first functionalized
layer.

15. A semiconductor structure, comprising: a source substrate including a
first support substrate, a first functionalized layer on the first
support substrate, and a sacrificial buffer layer, the first
functionalized layer including a first metal conductive electrode at a
surface of the first functionalized layer, the sacrificial layer located
under the first functionalized layer relative to a direction of
implantation of the ionic species into the source substrate, wherein
implanted ionic species are disposed within the source substrate at a
depth delimiting a thickness of an upper part of the source substrate,
the upper part comprising the first metal conductive electrode, the first
functionalized layer, and at least part of the sacrificial buffer layer;
and a second support substrate bonded to the source substrate, the second
support substrate including a second functionalized layer, the second
functionalized layer including a second metal conductive electrode at a
surface of the second functionalized layer.

16. The semiconductor structure of claim 15, wherein a thickness of the
sacrificial buffer layer is between 10 nm and 1 μm.

18. The semiconductor structure of claim 17, wherein the sacrificial
buffer layer comprises a confinement zone for confinement of the
implanted species.

19. The semiconductor structure of claim 18, wherein the confinement zone
of the sacrificial buffer layer is doped with boron.

20. The semiconductor structure of claim 15, wherein each of the first
metal electrode and the second metal electrode comprises a metal
individually selected from the group consisting of tungsten, titanium,
platinum, cobalt, nickel and palladium.

Description:

PRIORITY CLAIM

[0001] This application claims the benefit of the filing date of French
Patent Application Serial No. FR1156910, filed Jul. 28, 2011, for
"PROCESS FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE COMPRISING A
FUNCTIONALIZED LAYER ON A SUPPORT SUBSTRATE," the disclosure of which is
hereby incorporated herein in its entirety by this reference.

TECHNICAL FIELD

[0002] The field of the invention is that of semiconductor substrates used
in the electronics, optics and optoelectronics industry, and more
particularly in three-dimensional (3D) structures.

[0003] The invention relates more precisely to a process for manufacturing
a semiconductor structure comprising a functionalized layer on a support
substrate.

BACKGROUND

[0004] Semiconductor structures serve as a base for the formation of
electronic, optoelectronic, etc., devices.

[0005] To improve the performance of such devices, methods for increasing
the density of etched circuits per unit area have been developed.

[0006] The miniaturization of circuits, however, is physically limited.

[0007] Three-dimensional (3D) integration methods have been developed, in
which, in addition to attempting to reduce the size of circuits, the
circuits are stacked to form 3D structures and are connected via vertical
interconnections.

[0008] In the present text, the term "vertical" means a direction
perpendicular to the main face of the substrates in which these circuits
are formed.

[0009] The manufacture of structures of this type requires the successive
transfer, onto a support substrate, of the layers of which they are
constituted, usually by means of a process referred to in the art as the
SMARTCUT® process.

[0010] These layers are in fact produced separately on "source"
substrates, in which an embrittlement zone delimiting the layer to be
transferred is formed by implantation.

[0011] The transfer involves the successive bonding of each layer onto the
support substrate or onto a layer already transferred onto the support
substrate.

[0012] The bonding is often bonding by molecular adhesion.

[0013] The bonding is followed by an input of energy into the
embrittlement zone so as to bring about cleavage of the source substrate
along the embrittlement zone, the layer then being transferred onto the
support substrate.

[0014] The upper surface of the transferred layer (i.e. the surface of the
transferred layer that is opposite the surface bonded to the support
substrate) has a certain level of roughness caused by the fracture or
separation in the embrittlement zone.

[0015] It is known that a transfer of layers generally requires annealing
operations subsequent to the bonding or to the transfer, which reinforce
the molecular adhesion ("stabilizing" annealing) and/or which flatten the
surface of the transferred layer ("smoothing" annealing).

[0016] However, such annealing operations are in certain cases
problematic--especially that of the bonding of "functionalized" layers,
used in 3D structures.

[0017] In the present text, the term "functionalized layer" (also known as
the "active layer") means a semiconductor layer that has been processed
to have one or more functionalities.

[0018] The functionalization may thus comprise doping (creation of a p-n
junction), etching of "patterns" (e.g., designs obtained by removing
material in order to create or define electronic microcomponents),
formation of vertical electrical connections ("vias"), etc.

[0019] These active layers produced, however, are fragile and
non-homogeneous.

[0020] An excessive temperature increase may thus damage the active layers
and render them unusable.

[0021] It has been proposed to perform only low-temperature annealing
operations (below 500° C.).

[0022] However, the Applicant has found that, in some cases, smoothing
annealing at this temperature is insufficient to give the transferred
active layer the required uniformity.

[0023] Moreover, a simple polishing step that could be performed after
such annealing may be problematic since it could deteriorate the
uniformity of the transferred layer.

[0024] Finishing is, thus, a step that is particularly difficult to
perform, and the surface state obtained may be too rough (typically of
the order of 10 nm rms, whereas the target roughness may be on the order
of 1 nm or less) to be able to stack other active layers onto the
structure obtained.

[0026] The present invention is directed toward allowing the manufacture
of 3D structures comprising a functionalized layer that has a good
surface state without requiring a strong temperature increase.

[0027] Another aim of the present invention is generally to improve the
processes for manufacturing semiconductor structures requiring a step of
transfer of a functionalized layer in which it is not possible to exceed
a temperature of about 500° C.

[0028] In order to achieve the objectives outlined above, the present
invention relates to a process for manufacturing a semiconductor
structure comprising a first functionalized layer on a support substrate,
the process comprising the following steps:

[0029] (a) implanting ionic species in a source substrate comprising:
[0030] the first functionalized layer, the first functionalized layer
comprising at the surface a first metal conductive electrode, and [0031]
a sacrificial buffer layer located under the first functionalized layer
relative to the direction of implantation, wherein the ionic species are
implanted at a depth delimiting the thickness of an upper part of the
source substrate, the upper part comprising the first metal conductive
electrode, the first functionalized layer and at least part of the
sacrificial buffer layer;

[0032] (b) providing a support substrate comprising a second
functionalized layer, the second functionalized layer comprising at the
surface a second metal conductive electrode;

[0033] (c) bonding the source substrate to the support substrate, the
first metal electrode and the second metal electrode being at the bonding
interface;

[0034] (d) fracturing the source substrate and transferring the upper part
of the source substrate from the source substrate to the support
substrate; and

[0035] (e) removing the sacrificial buffer layer by selective etching with
respect to the functionalized layer.

[0036] The sacrificial buffer layer is thus preferably made of a material
that allows selective etching with respect to the material of the first
functionalized layer.

[0037] According to one advantageous embodiment of the invention, the
sacrificial buffer layer comprises a layer for confinement of the
implanted species.

[0038] For example, the confinement zone is a zone of the sacrificial
buffer layer that is doped with boron.

[0039] Preferably, the thickness of the sacrificial buffer layer is
between 10 nm and 1 μm.

[0040] According to one particular embodiment of the invention, the
sacrificial buffer layer is made of silicon dioxide.

[0041] In this case, the selective etching of the sacrificial buffer layer
is advantageously wet chemical etching with acid, in particular with
hydrofluoric acid.

[0042] Moreover, a heat treatment for repairing the defects of the
transferred first functionalized layer at a thermal budget lower than a
thermal budget at and above which the first functionalized layer or the
support substrate is damaged may also be applied.

[0043] The bonding step (c) may comprise the application of stabilizing
annealing at a temperature of between 200° C. and 500° C.

[0044] According to one particular embodiment of the invention, the
support substrate also comprises a second functionalized layer.

[0045] For example, the first functionalized layer of the source substrate
and/or the second functionalized layer of the support substrate comprise
an electrode located at the bonding interface, the electrode(s) providing
an electrical contact between the first functionalized layer of the
source substrate and the second functionalized layer of the support
substrate.

[0046] The first metal electrode and the second metal electrode are
advantageously made of a metal chosen from tungsten, titanium, platinum,
cobalt, nickel and palladium.

BRIEF DESCRIPTION OF THE FIGURE

[0047] Other characteristics and advantages of the present invention will
emerge on reading the description that follows of one preferential
embodiment. This description will be given with reference to the attached
drawings, in which FIG. 1 is a scheme representing the steps of the
process for manufacturing a semiconductor structure according to the
invention.

DETAILED DESCRIPTION

Formation of the Source Substrate Comprising a First Functionalized Layer

[0049] The source substrate 2 is a bulk or composite substrate (e.g.,
formed from a stack of layers of different materials) made of any
semiconductor or non-semiconductor material.

[0050] The source substrate 2 comprises, on one of its faces, referred to
as the "upper face," a first functionalized layer 4.

[0051] The first functionalized layer 4 may comprise a p-n junction and/or
a superposition of several layers of different materials.

[0052] Advantageously, the first functionalized layer 4 may comprise, at
the surface, a conductive first metal electrode 7a. For example, the
first metal electrode 7a may comprise one or more metals chosen from W,
Ti, Pt, Pd, Ni, Co, etc.

[0053] When such a first metal electrode 7a is present, its thickness must
be small enough to allow the implantation of ionic species such as
hydrogen and/or helium through the electrode 7a.

[0054] Thus, the thickness of the first metal electrode 7a is typically
less than 0.5 μm.

[0055] The upper surface 201 of the first functionalized layer 4 is a free
surface of the source substrate 2, intended to be bonded to a support
substrate in order to transfer the first functionalized layer 4 onto the
support substrate.

[0056] Under the first functionalized layer 4 is a buffer layer 5 which,
as described later, is a sacrificial layer intended for finishing the
semiconductor structure obtained after transferring the first
functionalized layer 4 onto the support substrate.

[0057] In this regard, the sacrificial buffer layer 5 is made of a
material that is able to be selectively removed with respect to the
material of the first functionalized layer 4.

[0058] For example, if the first functionalized layer 4 comprises highly
doped silicon, the sacrificial buffer layer 5 may be made of undoped or
sparingly doped silicon.

[0059] According to another example, if the first functionalized layer 4
comprises one or more silicon-based materials, the sacrificial buffer
layer 5 may be made of silicon dioxide (SiO2).

[0060] To form the source substrate 2, the sacrificial buffer layer 5 is
formed on a base substrate 200, and the first functionalized layer 4 is
then formed on the sacrificial buffer layer 5.

[0061] The formation of the sacrificial buffer layer 5 may be performed
via any suitable technique as a function of the chosen material.

[0062] For example, the sacrificial buffer layer 5 may be formed via any
deposition or epitaxy technique, or, alternatively, if it consists of an
oxide of the base substrate, by oxidation of the base substrate 200.

[0063] The thickness of the sacrificial buffer layer 5 may be chosen to be
between 10 nm and 1 μm.

[0064] The formation of the sacrificial buffer layer 5 is optionally
followed by a finishing step intended to promote the formation of the
first functionalized layer 4.

[0065] The finishing process may comprise wet etching, dry etching,
polishing, or a combination of these processes.

[0066] The formation of the first functionalized layer 4 is performed via
any suitable technique as a function of the nature of the first
functionalized layer 4.

[0067] For example, if the first functionalized layer 4 comprises a
conductive first metal electrode 7a, it may be formed by deposition of
one or more layers of the appropriate metal(s).

[0068] The formation of the first functionalized layer 4 may comprise
deposition over the entire surface of the sacrificial buffer layer 5, if
the first functionalized layer 4 is continuous.

[0069] Alternatively, if the first functionalized layer 4 is formed from
patterns, the formation of the first functionalized layer 4 may involve
the formation of a mask for selective deposition in order to obtain the
desired patterns.

[0070] In general, the first functionalized layer 4 may be formed via any
method known in the field of semiconductor processing (etching,
lithography, implantation, deposition, etc.) and its formation may also
involve transfer from another substrate.

[0071] Masking and selective deposition methods are well known in the
field of semiconductor materials and a person skilled in the art is
capable of selecting the appropriate method as a function of the
materials, the geometry of the patterns, etc. from all those that are at
his disposal.

Embrittlement of the Source Substrate

[0072] With reference to FIG. 1(b), an implantation of species through the
first functionalized layer 4 is performed in the source substrate.

[0074] The implantation energy is chosen such that the implantation peak,
i.e. the plane 202 in which a majority of atoms are implanted, is in the
sacrificial buffer layer 5, or even at a greater depth, in the base
substrate 200. It is this latter case that is illustrated in FIG. 1(b).

[0075] The implantation energy may be determined via preliminary
simulations, for example using the SRIM software.

[0076] As a guide, in the case of hydrogen implantation, the implantation
energy is between 10 and 250 keV.

[0077] As regards the implanted dose, it must be sufficient to allow
subsequent cleavage of the source substrate 2 along the embrittlement
plane 202.

[0078] In this regard, it is considered that, in the case of hydrogen, the
implanted dose should typically be between 2×1016 and
2×1017 cm-2.

[0079] According to a particularly advantageous mode of the invention, the
buffer layer comprises a zone (not shown) for confining the implanted
species.

[0080] The confinement zone may be, for example, a zone of the buffer
layer doped with boron. A boron-doped buffer layer may be made via
standard methods of epitaxy or of implantation of boron into silicon.

[0081] In this case, the implantation energy is chosen such that the
implantation peak is in the sacrificial buffer layer 5.

[0082] The confinement zone then has the effect of concentrating the
implanted atoms, which makes it possible to obtain fracture with less
energy input than in the absence of the confinement zone, especially by
employing a reduced thermal budget.

[0083] Moreover, this lower energy input makes it possible to reduce the
risk of detachment of the bonding interface during the fracture of the
source substrate.

[0084] Moreover, the implantation may be performed in a single step or
sequentially.

[0085] In the case of a single step, the implantation is performed after
the formation of the first functionalized layer 4 in the source substrate
2, and the implanted species pass through the first functionalized layer
4.

[0086] Specifically, if the implantation were performed before the
formation of the first functionalized layer, the heat treatments employed
during the formation of the layer would be liable to affect the implanted
zone, for example by blistering.

[0087] Alternatively, the implantation is performed sequentially, e.g., in
several steps with doses whose total is the dose required to allow
cleavage of the source substrate along the embrittlement plane 202.

[0088] Thus, part of the total dose (for example 10%) may be implanted
before functionalization of the layer, and the rest (for example 90%)
after its functionalization. This makes it possible to limit the effects
of the implantation on the first functionalized layer.

[0089] Moreover, a single species or several species may be implanted,
simultaneously or sequentially.

[0090] The sacrificial buffer layer 5 has the advantage of distancing the
embrittlement plane 202 (and thus the fracture front) from the first
functionalized layer 4, which makes it possible to reduce the risk of
damaging the functionalized layer by the implanted ions.

Bonding of the Source Substrate to a Support Substrate

[0091] The support substrate intended to receive the first functionalized
layer 4 may be chosen solely to serve as a mechanical support (stiffener)
for the layer, which is very thin, without having any particular
electrical functions (Si substrate that has not undergone any particular
treatment, glass, metallic substrate, etc.).

[0092] Alternatively, the support substrate may itself comprise a second
functionalized layer 6 intended to co-operate with the first
functionalized layer 4 during the functioning of the final semiconductor
structure.

[0093]FIG. 1(c) illustrates an example of such a support substrate 3, in
which the second functionalized layer 6 comprises at its surface a metal
electrode 7b.

[0094] The functionalization of the support substrate 3 may thus comprise
the use of a process for manufacturing electronic devices (the support
substrate 3 may be, for example, a CMOS structure) and/or the formation
of electrical interconnections and/or the metallization of the substrate.

[0095] As illustrated in FIG. 1(d), the source substrate 2 (FIGS. 1(a) and
1(b)) is bonded to the support substrate 3 (of FIG. 1(c)) via the first
functionalized layer 4.

[0096] This is direct bonding (e.g., without an additional layer being
interposed between the first functionalized layer 4 and the support
substrate 3), by molecular adhesion. In other words, direct atomic bonds
may be established between the first functionalized layer 4 and the
surface of the support substrate 3.

[0097] Where appropriate, if the support substrate 3 comprises a second
functionalized layer 6, the bonding is performed directly between the
first functionalized layer 4 of the source substrate and the second
functionalized layer 6 of the support substrate 3.

[0098] In the case illustrated in FIG. 1(d), the source substrate 2 and
the support substrate 3 are bonded via first metal electrode 7a and
second metal electrode 7b.

[0099] Preferably, bonding of two identical metals (for example Al--Al,
W--W, Ti--Ti, Pt--Pt, Cu--Cu, etc.) is favoured, although it is possible
to bond two layers of different materials (for instance W--Cu).

[0100] The bonding may be performed between two continuous metal layers
(i.e. covering the entire bonding interface 203) but also, where
appropriate, between two discontinuous, patterned metal layers.

[0101] In this case, the bonding interface 203 is electrically active
(i.e., it allows the passage of electrons between the support substrate 3
and the transferred first functionalized layer 4).

[0102] A heat treatment may be performed after bonding so as to reinforce
the bonding energy at the interface 203.

[0103] It is in fact necessary for this bonding energy to be sufficient,
in order that, during the subsequent detachment step, cleavage can take
place along the plane 202 of the source substrate 2 and not along the
bonding interface 203.

[0104] This heat treatment is typically performed at a temperature above
200° C., without exceeding a temperature beyond which the first
functionalized layer 4 would risk being degraded.

[0105] In general, this heat treatment may be performed at a temperature
below 500° C.

Fracture and Separation

[0106] Fracture of the source substrate 2 is then brought about along the
embrittlement plane 202.

[0107] To this end, a mechanical, thermal and/or other force is applied,
which brings about fracture of the source substrate 2 along the plane
202.

[0108] If a heat treatment is applied, it should correspond to a thermal
budget below a thermal budget that would risk degrading the first
functionalized layer 4.

[0109] Typically, the fracture heat treatment is performed at a
temperature below 500° C.

[0110] The remainder of the source substrate 2 may then be detached, and
optionally may be recycled.

[0111] The resulting structure comprises the support substrate 3 and the
transferred upper part 20 of the source substrate 2, which comprises the
first functionalized layer 4 covered either with part of the sacrificial
buffer layer 5 (if the embrittlement plane 202 were located in the
sacrificial buffer layer 5), or with the sacrificial buffer layer 5 and
part of the base substrate (if the embrittlement plane 202 were located
in the base substrate 200, as illustrated in FIG. 1(d)).

[0112] To obtain the final semiconductor structure 1 illustrated in FIG.
1(e), which comprises the support substrate 3 and the first
functionalized layer 4, the sacrificial buffer layer 5 is removed, along
with, where appropriate, any residual portion of the base substrate 200.

[0113] To this end, polishing may be performed (for example,
chemical-mechanical polishing (CMP)) to remove any residue of the base
substrate 200, followed by dry or wet selective etching in which the
etching agent allows etching of the material of the sacrificial buffer
layer 5 without substantial etching of the material of the first
functionalized layer 4.

[0114] A person skilled in the art is capable of selecting a suitable
product among the agents available on the market, taking into account the
materials of the sacrificial buffer layer 5 and of the active layer 4.

[0115] Thus, by way of example, in the case of a SiO2 sacrificial
buffer layer 5, wet etching based on 10% HF (hydrofluoric acid) may be
used.

[0116] This removal of the sacrificial buffer layer 5 makes it possible to
remove from the final semiconductor structure a majority of the defects
introduced during the implantation and to obtain a free surface 204 of
the first functionalized layer 4 that is sufficiently smooth.

[0117] In the preceding example, the case of an SiO2 sacrificial
buffer layer 5 etched via wet etching based on 10% HF makes it possible
to obtain roughness of less than 0.5 nm on the first functionalized layer
4.

[0118] The use of the sacrificial buffer layer 5 thus makes it possible to
dispense with a heat treatment for smoothing of the first functionalized
layer 4. Thus, in some embodiments, the methods may not include any heat
treatment process for smoothing the first functionalized layer 4.

[0119] Other finishing heat treatments may optionally be applied to repair
the defects caused by the implantation and to improve the functionality
of the first functionalized layer.

[0120] Conventionally, these heat treatments are performed in an oven or
in an RTA (rapid thermal annealing) treatment device.

[0121] In all cases, these heat treatments are performed at a thermal
budget that depends on the nature of the first functionalized layer 4
(especially the doping profile, the nature of the metals employed to form
the conducting electrodes and/or the interconnections, etc.), which
remains lower than a thermal budget that would run the risk of damaging
or impairing the functioning of the first functionalized layer 4
transferred onto the support substrate 3.

[0122] After these various treatments, it is possible, according to the
semiconductor structure that it is desired to obtain, to transfer a new
functionalized layer onto the first functionalized layer 4.

[0123] The low surface roughness of the first functionalized layer 4 in
fact enables such a transfer to be performed.