Because Freescale refrains from making their mcu peripherals logical and intuitive whenever possible...

Clear by writing 1 or clear by reading are very annoying features of some peripherals, that surely must cause millions of bugs for all Freescale users, especially those who are using C. I bet every single user sooner or later runs into classic Freescale bug 1: "the debugger is eating my SCI/SPI flags" and classic Freescale bug 2: "my timer flags are destroyed because I clear a flag with TIMER_REG |= 0x01 rather than TIMER_REG = 0x01".

But the C language has only been standardized for 18 years, so if we give Freescale more time they might at some point adapt their micros to support this new fancy language.

this issue isn't easy to fix. Would you like slowing down CPU like it's done in Microchip MCUs to solve this? Maybe slowing down peripherals? More complicated circuit and more expensive chip? One flag per register leading to more address space occupied by registers block (something like in S08 family, but first compare how many flags does S12D family have)? I wouldn't.

Changing logic level from 1 to 0 can hardly be expensive. The clear-by-read issues in SCI/SPI are seem to be there for backwards compatibility only.

Another case where the C language has clearly not been considered is the address map. A write to address zero should yield an error interrupt on a micro designed for the C language, to prevent null pointer access.

Also, companies like Freescale spend huge amounts of cash on things like AUTOSAR to reduce software bugs. In my opinion they should start fixing the simple things first.

Probably there's something like FISRn trigger, AND gate and "chip select" circuit, all wired so that when EQADC register is selected and WRite is high and data bus bit corresponding to FISRn bit position is '1', then FISRn trigger is reset. Simple.