I 'm new to PSoC and want to dig deeper into it So I bought a PSoC 4 pioneer kit as a starting point.

Now, I want to go for my 'real' first own design. This design uses a shift register component.

I've some questions:

1) It seems a counter is necessary to detect if the desired number of bits have been shifted, right?

2) I want to generate an interrupt if a new byte has been loaded from the FIFO into the shift register. I don't use the load input signal, but it seems that the load interrupt output can still be used for that purpose, right?

3) Is it possible to access the shift register status register (or the underlying UDB) by hardware? I want to detect if the FIFO is empty.

First the bad news: there is no signal of the shift register to indicate it is containing all zeroes.

The better news are: you might define (program) an UDB to be a shift-register with a all-zero signal.

The next bad news is: That turns out to be complicated since you will have to learn and use a "Hardware Description Language" (HDL) named "Verilog". On top of this page is a "Keyword Search" field, enter "UDB" or "Verilog" or both and get something to read or watch.

First the bad news: there is no signal of the shift register to indicate it is containing all zeroes.

Maybe a missunderstanding: I don't want to detect if the shift register contains all zeros, but if the FIFOs of the shift register component are empty.

The better news are: you might define (program) an UDB to be a shift-register with a all-zero signal.

I thought it's maybe possible to modify the existing component

The next bad news is: That turns out to be complicated since you will have to learn and use a "Hardware Description Language" (HDL) named "Verilog". On top of this page is a "Keyword Search" field, enter "UDB" or "Verilog" or both and get something to read or watch.

Shouldn't be a problem to learn it. But the key is to write it efficient ;)

You are not the only one here (and I'm afraid there will be some more coming) who is fighting with the forum software. Best is: Do not try anything, even when it seems to be simple

Use IE when attaching files, rumors tell that firefox will do as well, chrome definitively will NOT work.

Project questions can be solved quickly when you attach a "Workspace Bundle" which not only will contain your code, but your component and compiler settings, too.

There is a blog from Brad Budlong concerning verilog components, that was very helpful for me. When you know how to create new components you will know how to modify existing ones (without destroying the original

this sounds good. I started with the application notes regarding component creation (AN81623, AN82156 and AN82250), I think I have a base how to start.

Currently I'm on pen and paper, making notes, etc. In short, the whole design encodes the single bits of a software buffer into pulses with different pulse widths.

The purpose of the shift register is to fed a PWM component with fixed frequency and two fixed pulse widths (the PSoC 4 fixed timer/PWM module will be suitable, I think). The pulse width defines if it's a low or a high bit. The design needs to output the pulses continously as long as bytes are present in an software buffer with no delay between the bit pulses. If the buffer has been completely shifted out, the data signal must be go into an idle state.

So, my shift register needs to use the FIFOs, the FIFO status signals and if possible a bit counter to make the idle state easier.

Now, I'll try to make an assumption which of those functions will go into a datapath and which will be solved by the PLD ;)

This sound like you are re-implementing SPI... I would that try first: use a UDB-based SPI component, and feed its data signal to the PWM switch input. The SPI component already does everything you need.

Don't you think that it is a rather heavy start with PSoCs to begin with a DataPath object? Wouldn't it be better to get acquainted to Creator and the capabilities of PSoC4 (which are a bit reduced compared to the PSoC5).

yes, it's heavy ;) It's the hard way of learning by doing. However, I can still switch and build it up with the supplied components if my approach won't work.

Currently it seems that the example code of AN82156 (the UART Tx component) will be a good base. If I can modify it to fit my needs I should maybe also be capable to implement the PWM portion in that component, without using the seperate PWM component.

Primarily: your component must work correctly and fit into the two USBs a PSoC4 has got. Remember for future projects: a PSoC5 has got 24 UDBs and there is a rather comfortable development kit for this, but it is more expensive than a Pioneer board.

You have to prove that your implementation works, so you will need a logic analyzer. If you haven't got one, I can point you to a cheap source. VeriLog does not allow for debugging and simulation, so proving the correctness can turn out to be difficult.

The criteria for something to be "good" differs from the point of view and the context you are in. In the world of PSoCs "good" could mean "cheap". So how to be "cheap" when producing a component? "Quick & dirty" has turned out to be not "cheap", instead it could get expensive. I am really convinced that "cheap" is related to "easy to understand" which needs something I call "readability". The quintessence of this is: Write down everyting with understanable names in an easy-to-understand structure with only the necessary documentations. This will help you in, say 3 months, when picking up the sources again to understand which strike of genius had hit you when you wrote down that lines.