ATM Chip Database

The Bt8230 ATM Segmentation and Reassembly
Controller meets the needs of ATM terminal equipment
for a highly integrated, specification-compliant product.
The SRC combines a PCI bus interface, a proprietary
scheduling algorithm, a local memory controller, a DMA
coprocessor, and segmentation and reassembly coprocessor
to form a ATM adaption layer processor. 16,000 open
connections with robust OAM, signaling, and ILMI features are
supported by the Bt8230, as well as random VPI/VCI
assignment and interleaved AAL5 and AAL3/4 segmentation
and Reassembly. Furthermore features are

sustained 155 Mbps throughput

PCI master and slave operation

UNI 4.0 upgradable

GCRA transmit scheduler, ABR flow control upgradable

per VCC transmit queuing

JTAG boundary scan

An evaluation system is provided.
The Bt8230 has an integrated PCI Interface and
supports the per connection traffic management
required by the ABR service.