This joint effort has reduced Calibre nmDRC 20nm signoff runtimes by at least a factor of 3X and memory requirements by 60 percent compared to initial design kits released last year. In addition, Calibre PERC N20 design kits are now available to TSMC customers as part of the companies’ ongoing collaboration for IC reliability improvement.

The collaboration will continue as mutual customers ramp their releases of N20 production designs, with the goal of maintaining rapid turnaround on full-chip signoff runs for the largest SoC designs in the industry.

The Calibre PERC kit for N20 includes new checks for latch-up prevention and IO-ESD protection, and a number of multiple power domain checks, which represent a significant step forward in automating procedures that previously had to be done manually. Moreover, by using both the Calibre PERC and Calibre nmDRC kits, customers are able to quickly identify and correct voltage-aware DRC violations, which is critical for today’s multi-voltage advanced process designs.

Other ongoing collaboration between TSMC and Mentor is focusing on optimizing the Calibre DFM product family, which incorporates TSMC’s unified DFM (UDFM) engine. Improvements are expected to result in runtime reduction in TSMC’s latest DDK release, and customers who use any DFM tools compliant with TSMC UDFM engine will benefit.