(Cat? OR feline) AND NOT dog?
Cat? W/5 behavior
(Cat? OR feline) AND traits
Cat AND charact*

This guide provides a more detailed description of the syntax that is supported along with examples.

This search box also supports the look-up of an IP.com Digital Signature (also referred to as Fingerprint); enter the 72-, 48-, or 32-character code to retrieve details of the associated file or submission.

Concept Search - What can I type?

For a concept search, you can enter phrases, sentences, or full paragraphs in English. For example, copy and paste the abstract of a patent application or paragraphs from an article.

Concept search eliminates the need for complex Boolean syntax to inform retrieval. Our Semantic Gist engine uses advanced cognitive semantic analysis to extract the meaning of data. This reduces the chances of missing valuable information, that may result from traditional keyword searching.

Publishing Venue

Related People

Abstract

Differential Cascode Current Switch (DCCS) circuitry provides for complex functions in a single circuit (tree). Here, three mutually exclusive clocks are generated and are used to clock three separate data conditions into a latch. Fig. 1 shows three DCCS circuits used to generate three distinct clocks. The trees form NAND functions, but are not limited to a simple NAND function. OSC X, Y, Z may be different times during a cycle or they may be the same time with f(a) through f(1) defining different conditions or different instructions. OSC X, Y, and Z plus f(a) through f(1) must guarantee that one and only one of the signals latch hold, X clock, Y clock, and Z clock is present at any one time (+ level). The operation of the clock generation trees is as follows.

Country

United States

Language

English (United States)

This text was extracted from a PDF file.

At least one non-text object (such as an image or picture) has been suppressed.

This is the abbreviated version, containing approximately
52% of the total text.

Page 1 of 3

Clock Driver, Translator and Latch Circuit

Differential Cascode Current Switch (DCCS) circuitry provides
for complex functions in a single circuit (tree). Here, three
mutually exclusive clocks are generated and are used to clock three
separate data conditions into a latch. Fig. 1 shows three DCCS
circuits used to generate three distinct clocks. The trees form NAND
functions, but are not limited to a simple NAND function. OSC X, Y,
Z may be different times during a cycle or they may be the same time
with f(a) through f(1) defining different conditions or different
instructions. OSC X, Y, and Z plus f(a) through f(1) must guarantee
that one and only one of the signals latch hold, X clock, Y clock,
and Z clock is present at any one time (+ level). The operation of
the clock generation trees is as follows. When OSC X, Y, and Z are
all - (inactive), one current path in each tree will cause +X clock,
+Y clock, and +Z clock all to be -. The latch hold signal line will
go to a + level and all four output signals will conform to the rule
that one and only one signal will be + at all times. At some later
time, f(a), f(b), f(c), f(d), and OSC X will all go +. This will
cause the current flow path in tree 1 to change so that the latch
hold signal will go - and the X clock signal will go to +. In
all cases, there will be one and only one current flow path in each
tree and one and only one output at a + level. In a similar manner,
trees 2 and 3 also cause the latch hold line to go to a -
level and outputs clock Y and clock Z can go to a + level depending
on which tree has all + inputs. The four signals are then translated
down one or more levels (four levels shown) and sent to the latch
circuit in Fig. 2. The latch tree in Fig. 2 has four transistors at
the bottom of the tree. Since the clock driver circuit in Fig. l
guarantees one and only one + signal at any time, the latch tree will
always have one and only one current path active at all times. If
clock X is +, for example, data inputs X1, X2, X3, and X4 will be
examined, and if all + will cause the latch to be set to a one,
while if one or more inputs are -, the latch will be set to a
zero. When the X clock goes -, the latch hold signal will go + and
hold the contents of the latch in the state previously set.

Similarly, clocks Y and Z can be used to set the latch to a zero
or one. Note that a minimum of data inputs X1, Y1, and Z1 are
required for proper operation of the latch while inputs X2, X3, X4,
Y2, Y3, Y4, Z2, Z3, and Z4 are optional. There is no maximum limit on
X data, Y data, or Z data inputs exc...