Abstract. The paper covers the transformation of the Bron–Kerbosh algorithm to search all maximum graph clicks for implementation on Reconfigurable Computer Systems (RCS). It is shown that the use of RCS provides a close to linear growth of system performance at increasing the hardware resource of FPGA (Field Programmable Gate Array) computational field by adapting the architecture of computer device to the structure of application problem. At the same time, the growth of system performance is practically not observed for classical multiprocessor systems if a certain number of processors is reached. A structure of base operation of adding/removing elements from the RCS set is developed in which the pipeline processing is implemented. It is shown that the computational complexity of adding/excluding element operation is reduced to a linear due to this organization of calculations. A theoretical foundation of the high performance of structural implementation of the Bron-Kerbosh algorithm on RCS is presented. The comparative analysis of searching problem velocity of all maximum graph clicks on traditionally multiprocessor computer system based on the Intel Xeon E5504 processors and the theoretical velocity of solving problem, achieved by RCS based on Xilinx FPGAs of UltraScale family XCKU095, is performed.

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