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Abstract

Clock transitions to be detected, which are very slow with respect to the speed of operation of logic and clock in the machine used to detect this transition can result in the machine taking several cycles per transition instead of only one, or taking a cycle on noise. The detector system shown in Fig. 1 minimizes these problems. Fig. 2 is a timing diagram illustrating the operation of the system.

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English (United States)

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Slow Clock Transition Detector

Clock transitions to be detected, which are very slow with respect to the
speed of operation of logic and clock in the machine used to detect this transition
can result in the machine taking several cycles per transition instead of only one,
or taking a cycle on noise. The detector system shown in Fig. 1 minimizes these
problems. Fig. 2 is a timing diagram illustrating the operation of the system.

To detect a negative transition of a slow clock, a positive cycle latch 3 is set
to first indicate that the positive level of the slow clock signal has been detected.
Latch 3 is set by the presence of the + slow clock signal and a timing signal, -
Delayed R1. When the positive cycle latch is set, the slow clock is sampled to
detect the first indication of a negative level and a delay latch 5 is set, by the
signals + Delayed R2 and - slow clock. This indication of a negative level could
have been noise or the undefined state of the transition in the slow clock. A
period of time later, the slow clock is again sampled; and if it is negative at this
time, a negative cycle latch 9 is set. This indicates that a negative transition has
been detected. If it were noise which turned on the delay latch, the negative
cycle latch will not be set and the slow clock will again be sampled for the
negative level to set the delay latch and negative cycle latch.

The delay time to set the negative cycle latch 9 is sufficiently . long to cover
most noise and t...