The JFET will still operate with Vgs = 0 as it is a depletion-mode transistor. It will turn off with anything more negative than around -3 V. Theoretically at Vgs = 0, this will provide Id = Idss (max current) but wont be that stable.

But I still have a doubt, as the source will always be at 0V (in the example), and the gate is not receiving any biasing voltage, it will will be also 0V when there is no input signal. With this scenario, the current would equal Idss but will be "limited" by the Drain resistor. Ok?

My questions are:
1- When an audio signal is applied at the input (AC only), there will be negative cycles, that will decrease Id, correct?
2- At the positive cycle of the sinusoid the gate will become positive. How will the Id change if the maximum value should already be reached with 0V?

Sorry if I'm not clear as english is not my native language, but I'd really appreciate your help to make me understand the theory behind this...

Idss is NOT the maximum drain current. If Vgs goes positive, Id will be greater than Idss, unless it is limited by the drain resistor. As Vgs is increased above 0V, gate current will begin to flow. 500 millivolts p-p will probably not cause significant gate current to flow. 1V p-p will cause a little bias shift. You will not see signal voltages this large from a microphone or pickup.
If the input is cap-coupled, gate current will charge the cap slightly on the largest positive signal peaks, forcing the DC gate bias to go below zero volts. In this sense, it is self-biasing to an extent. As I said, this would be an unusual situation.