Asynchronous Design Aspects of High-Performance Logic

Architectural Modelling of a Bipolar Asynchronous Microprocessor

R. Kelly

Abstract

As VLSI process technologies develop and feature sizes shrink, the global
clocking schemes currently employed in synchronous systems are beginning to
experience difficulties in a number of areas. Asynchronous circuits have a
potentially higher performance than synchronous circuits since an
asynchronous circuit exhibits average-case performance, in contrast to
synchronous systems, which must be specifically designed to accommodate
worst-case conditions. However, asynchronous design techniques are not
widely understood or developed, particularly in the context of a large,
complex system.

Recently, an asynchronous design methodology, namely Micropipelines, has
been presented which has proved useful in developing an asynchronous CMOS
implementation of an existing commercial RISC architecture. A subsequent
project has been initiated to develop architectural modelling and
implementation tools for an asynchronous high-performance bipolar
implementation of the same target architecture.

This thesis presents the issues involved in asynchronous logic design, the
details of the particular asynchronous design methodology employed and an
introduction to the architectural modelling environment used in the
development of the bipolar asynchronous implementation. The development of
the system model is illustrated, with reference to the underlying primitive
components and the hierarchical composition of the complete design from
asynchronous sub-functions communicating via a well-defined signalling
protocol. A demonstration of how the architectural model can be used to
generate information regarding the internal operation of the system, which
is then used to improve the complete design is given. The suitability of
modelling asynchronous systems with the modelling environment employed is
discussed.