Tag Archives: network-on-chip

Taking a quick look at the NORCHIP 2010 conference program it appears that ADC & DAC papers make up around 18% of the population – 21% if you add the two TDC (time-to-digital) contributions. That’s got to be good enough: It means that more than every 5th contribution is directly relevant to me. Couldn’t really ask for more at a conference with such a broad scope.

Another topic that stands out in the program is Network-on-Chip (NoC), which is treated in as much as 22% of the contributions according to titles. Clearly a hot topic! I’m not currently aware that NoC is interesting for me, but that may change if I go to all of those presentations. 😉

RF/Analog papers make up around 28% of the contributions, and that’s a more relevant topic for me than NoC. The pie chart shows the approximate distribution over different topics. The “other” slice represents presentations on 3D integrated circuits and mostly digital stuff. I don’t know if it was a goal, but as you can see the organizing committee did an excellent job in dividing the space almost perfectly into 50% RF/analog + mixed, and 50% digital + 3D-IC.

The total number of contributions is 71, distributed over 40 oral presentations (4 invited) and 31 posters.

One that I’m curious about is the invited talk “Mixed-Signal versus Purely-Digital Self-Calibration of High-Resolution Pipeline A/D Converters” by professor João Goes from Universidade Nova de Lisboa, Portugal. Having worked quite a lot with ADC calibration myself (e.g., this patent), his talk is exactly my cup of tea, and it will be very interesting to hear his findings.