ALPS delivers SPICE-level accuracy with excellent performance and capacity for the most challenging
analog and mixed-signal designs. This tool can simulate design with up to 10 million instances.

Compared to traditional SPICE tools, ALPS has significant performance speedup and gained additional
speedup with its advanced parallel technique.On average, it can provide an additional four to seven times
higher speedup in parallel simulation mode with eight threads by utilizing advanced multi-threading
algorithm.

PVE : Layout verification

PVE is a graphical debugging environment for physical design tools. It allows you to browse and debug
verification results after DRC and LVS runs. It probes DRC and LVS database results and back-
annotates to layout viewer, schematic viewer, SPICE netlist browser and logic viewer. It is
a powerful tool for users to easily debug DRC errors and LVS discrepancies.

RCExplorer is an on-chip interconnect parasitic extraction and analysis tool for Analog, AMS and Digitial
designs. RCExplorer generates distributed 3D capacitance and resistance including advanced
manufacturing effects associated with 45nm processes and below. RCExplorer also provides
easy-of-use functionalities for interconnect analysis after extraction. RCExplorer is intergrated with leading
layout tools for both batch-mode and interactive usage