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Beamformer implementations (Mike Jones, Kris Zarb Adami, David Sinclair, Chris Shenton) Starting with top level considerations for now, ie Not, which FPGA board shall we use, rather 1.What is the structure of the beamformer (as function of AA specs) 2.What are the ideal properties of the processing nodes and interconnects to implement this 3.What existing/possible hardware is available to implement this for prototyping (incl AAVS1,2) 4.What is the most efficient (NRE cost, construction, power) solution for Phase 1

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Antenna processor ADCChannelize Data format and physical interface Analogue in (local to antenna or RFoF) Digital out (antenna to bunker or local rack) ADCChannelize Can be developed as block (almost) independently of architecture Processing load only ~500 GMAC/s – smallish chip compared to beamformer SKA.TEL.LFAA.RCV.DNA, SKA.TEL.LFAA.RCV.DCH, SKA.TEL.LFAA.SP.FB Clock Timing data in

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Beamformer node In partial beamformer, only one level of coefficient multiplication Everything else is just adders! Implement b = M.v in blocks – each block is a tile Ideal implementation (simplest connections) is node with N in = no elements in tile, N out = no of beams (average over bandwidth) + M.v Multiplier node Adder node Coefficient matrix in