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A FRAMEWORK FOR SOFT ERROR TOLERANT SRAM DESIGN
by
Riaz Naseer
________________________________________
A Dissertation Presented to the
FACULTY OF THE GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
December 2008
Copyright 2008 Riaz Naseer

With aggressive technology scaling, radiation-induced soft errors have become a major threat to microelectronics reliability. SRAM cells in deep sub-micron technologies particularly suffer most from these errors, since they are designed with minimum geometry devices to increase density and performance, resulting in a cell design that can be upset easily with a reduced critical charge (Qcrit). Though single-bit upsets were long recognized as a reliability concern, the contribution of multi-bit upsets (MBU) to overall soft error rate, resulting from single particle strikes, is also increasing. The problem gets exacerbated for space electronics where galactic cosmic rays carry particles with much higher linear energy transfer characteristics than terrestrial radiation sources, predictably inducing even larger multi-bit upsets. In addition, single-event transients are becoming an increased concern due to high operational frequencies in scaled technologies. The conventional radiation hardening approach of using specialized processes faces serious challenges due to its low-volume market and lagging performance compared to commercial counterparts. Alternatively, circuit-based radiation hardening by design (RHBD) approaches, where both memory cells and control logic are hardened, may incur large area, power and speed penalties if careful design techniques are not applied.; We develop a framework to harden SRAMs against these soft errors as technologies scale further in sub-100nm regime. This framework is based on a hybrid approach that combines spatial and temporal redundancy in a mathematical model to efficiently mitigate the effects of these transient errors. Particularly, the SRAM cells are left intact to exploit the benefits of state-of-the-art commercial processes and error correcting codes (ECC), and periodic memory scrubbing is used to obtain an effective bit error rate (BER) over the intrinsic physical bit error rate of the process. Only the peripheral circuitry is hardened using RHBD techniques, incurring an overall minimal penalty. This model-based hardening requires a careful characterization for establishing a clear problem domain. Therefore, we also develop simulation based methodologies to quickly estimate and characterize these transient effects. Using the guidelines provided by this characterization, two prototype SRAM ICs have been designed and fabricated. The effectiveness of the proposed model is demonstrated by the results of performing radiation tests on the fabricated prototype SRAM ICs.

A FRAMEWORK FOR SOFT ERROR TOLERANT SRAM DESIGN
by
Riaz Naseer
________________________________________
A Dissertation Presented to the
FACULTY OF THE GRADUATE SCHOOL
UNIVERSITY OF SOUTHERN CALIFORNIA
In Partial Fulfillment of the
Requirements for the Degree
DOCTOR OF PHILOSOPHY
(ELECTRICAL ENGINEERING)
December 2008
Copyright 2008 Riaz Naseer