In 1968 Lee Boysel, founder of Four Phase Systems, previously a designer
at Fairchild Semiconductor, published an article "Adder On
a Chip: LSI Helps Reduce Cost of Small Machine" in Electronics magazine.
Papers from Y. T. Yen, J. L. Seely, L. Cohen, R. Rubinstein, and F.
Wanlass also appear around this time.

This may or may not have been the origin of four phase
dynamic logic; be that as it may, this was the logic scheme that John Rhodes,
technical director of TMC, adopted to enable non-specialist engineers to
design quite complex ICs, using either PMOS or NMOS processes.

There were basically two types of logic gate - a '1' gate
and a '3' gate. These differed only in the clock phases used to drive them.
A gate could have any logic function - each and every gate had a customised
layout - hard to imagine in today's standard cell environments! Here's what
a 2-input NAND 1 gate and an inverter 3 gate looked like, together with their
clock phases (I'm using NMOS as it's easier to understand, in my humble opinion):

In practice the f1 and f3 clocks need to be non-overlapping, as do the
f2 and f4 clocks.
Considering the 1 gate, during the f1 clock
high time (aka precharge time) the output C precharges up to V(f1)-Vth. During the next quarter clock cycle
(the sample time), when f1 is low and f2 is high, C either stays high (if A or B are
low) or C gets discharged low (if A and B are high).

It ought to be clear that the A and B inputs must be stable throughout
this sample time and that the output C becomes valid during this time
- and therefore a 1 gate output can't drive another 1 gate's inputs. Hence,
making a great leap forward, we need 1 gates to feed 3 gates and they in
turn have to feed 1 gates.

It sounds complex but it all works out pretty well. Of course there are
some difficulties, the main one being that the gate output is dynamic.
This means that its state is held on capacitance at the gate output. But
the output track can cross clock lines and other gate outputs, all of which
can change the charge on the capacitor. In order that the gate output voltage
remains at some safe 0 or 1 level during the cycle the amount of change has
to be calculated and, if necessary, additional (diffusion) capacitance has
to be added to the output node.

In practice

So much for the theory. In practice four phase worked pretty well. The
designer entered his schematic on paper at a drawing board (!), then wrote
a netlist manually at a teletype, creating a paper tape. A stimulus tape
was created too, and a simulation could be run on the mainframe - at first
this was a Philips computer (a P880 with a light pen!) and later a VAX. The simulator was written in-house. We ran simulations
twice a day - you took your tapes down to the operator in a cardboard box,
and back would come your printout - columns of 0s and 1s - to check through.

For a given supply voltage, process and clock frequency the designer had
to do some calculations so that the layout people could, in turn, do their
calculations to work out the 'bulk-up' capacitance needed for each gate.
A gate with a lot of capacitance load could need bigger than minimum input
transistors (in order that the load could be discharged in time). This in
turn increased the load on the gates driving that gate's inputs. So it could
happen, especially in high frequency designs, that the gate sizing could
explode, and this would have to be solved somehow or other.

Analogue

The designs were mainly digital but we did do a little analogue - most
of this was special output stages, which were of course static. One interesting
application was the generation of a sine wave, a common requirement in telephony
(for example for tone generation for multi-tone signalling). Someone had
figured out that you could do this with a simple ADC
with relative output levels of 0, 1-1/Ö2, 1/Ö2, 1. Then there are no significant harmonics until
the 7th, so simple external filtering is all that's usually needed.