Scientists develop pulse compressor on silicon chip

Electrical engineers have taken another step towards replacing copper wiring on chips with optical interconnects by generating short, powerful light pulses on a chip.

Scientists at University of California, San Diego have developed the first ultra-compact, low power pulse compressor on a silicon chip, eliminating a major obstacle between finally producing optical interconnects that will have data transfer applications within PCs, data centres, imaging applications and other areas.

The optical interconnects will aggregate slower data channels with pulse compression, and will offer considerably higher data rates than copper, as well as generating much less heat than copper. Such aggregation devices will be critical to optical connections between high speed digital electronic processors in future digital information systems. The findings, published in Nature Communications journal, are another step closer to creating optical data transfer systems.

“Our pulse compressor is implemented on a chip, so we can easily integrate it with computer processors,” said Dawn Tan, who led development of the pulse compressor. “Next generation computer networks and computer architectures will likely replace copper interconnects with their optical counterparts, and these have to be complementary metal oxide semiconductor (CMOS) compatible. This is why we created our pulse compressor on silicon.”

In addition to increasing data transfer rates, optical interconnect offers the advantage of reduced power consumption caused by heat dissipation, switching and transmission of electrical signals, according to Eureakalert.

“At UC San Diego, we recognized the enabling power of nanophotonics for integration of information systems close to 20 years ago when we first started to use nano-scale lithographic tools to create new optical functionalities of materials and devices – and most importantly, to enable their integration with electronics on a chip. This Nature Communications paper demonstrates such integration of a few optical signal processing device functionalities on a CMOS compatible silicon-on-insulator material platform,” said Yeshaiahu Fainman, a professor in the Department of Electrical and Computer Engineering in the UC San Diego Jacobs School of Engineering.

The compressed pulses represent the largest compression demonstrated on a chip, as until now such high compression would only be possible through the use of bulk optics or fibre-based systems, which are considered too unwieldy for optical connects with regards to computing and other electronics. The new combination of high compression and miniaturisation are made possible by a nanoscale, light-guiding tool called an ‘integrated dispersive element’ which offers a component on the nanophotonics tool kit.

The pulse compressor operates by firstly broadening the spectrum of incoming laser light, for example to split green laser light into red, blues and green. Then the new integrated dispersive element manipulates the light so that each spectrum is travelling at the speed, the speed synchronisation at which pulse compression occurs.

This is essentially how the on-chip pulse compressor can transform a long pulse of light into a spectrally broader and temporally shorter pulse of light, which should allow multiplexing of data to achieve significantly higher data speeds.

“In communications, there is this technique called optical time division multiplexing or OTDM, where different signals are interleaved in time to produce a single data stream with higher data rates, on the order of terabytes per second. We’ve created a compression component that is essential for OTDM,” said Tan.

The UC San Diego electrical engineers believe that they are the first to report a pulse compressor on a CMOS-compatible integrated platform that is strong enough for OTDM.

“In the future, this work will enable integrating multiple ‘slow’ bandwidth channels with pulse compression into a single ultra-high-bandwidth OTDM channel on a chip. Such aggregation devices will be critical for future inter- and intra-high speed digital electronic processors interconnections for numerous applications such as data centers, field-programmable gate arrays, high performance computing and more,” said Fainman at the UC San Diego Jacobs School of Engineering and Deputy Director of the NSF-funded Center for Integrated Access Networks.