20nm Dilemma Explained

Semiconductor makers should shift from FinFETs to fully-depleted silicon-on-insulator technology, according to analyst Handel Jones.

This article is a follow up to an earlier analysis of the semiconductor roadmap.

Fully depleted silicon-on-insulator is the best solution for the 28nm and 20nm technology nodes because of its lower cost and leakage and higher performance than bulk CMOS.

The cost of a 100mm2 die in FD SOI at 28nm is 3.0% lower than bulk CMOS and 13.0% at 20nm due to higher parametric yield as well as lower wafer cost. The data also shows that an FD SOI die with comparable complexity to bulk CMOS is 10% to 12% smaller.

The combination of the smaller die area and higher parametric yield should give an equivalent product a 20% cost advantage at 20nm for FD SOI compared to bulk CMOS. In addition, at 28nm FD SOI has performance that is 15% higher than 20nm bulk CMOS. (See chart below.)

FD SOI can provide energy efficiency levels that are far superior to bulk CMOS for low Vdd and high Vdd. The power efficiency of bit cells is superior for FD SOI because of the lower leakage, along with better alpha particle immunity.

Despite these factors, Intel decided to adopt 22nm FinFETs rather than bulk CMOS. It also selected 22nm rather than 20nm in order to eliminate the need for double patterning.

Foundry vendors initially planned to migrate to 16/14nm FinFETs rather than 20nm bulk CMOS. But the reality of FinFETs is that the present device structures do not give cost competitive products through Q4/2017.

As a result, foundry vendors modified their plans. At TSMC, for example, 20nm bulk CMOS now is projected to represent 10% of total revenues in 2014 ($2.3 billion) and as much as 20% of total revenues in Q4/2014 ($1.1 billion).

However, I believe 20nm bulk CMOS will not provide lower cost per gate designs than 28nm, critical for high volume mobile chips. So there is significant uncertainty in the industry regarding the ramp-up rate of 20nm and 16/14nm FinFETs. One possibility is that 28nm wafer volumes will remain high through 2020. (See figure below.)

Shrinking FD SOI to 14nm (called 10nm by STMicroelectronics) also will give large cost advantage against FinFETs. Consequently, FD SOI provides both short-term and long-term cost, power consumption, and performance benefits.

One reason given for not embracing FD SOI is lack of support in the supply chain and concerns with being nonstandard. However, Soitec, SunEdison, and Shin-Etsu Handotai supply FD SOI wafers. If the industry adopts FD SOI they can expand capacity to address the supply chain challenges.

Other issues include the need to develop new libraries and IP, gain expertise in body biasing design capabilities and ensure the establishment of design flows. Leading EDA vendors say these areas can be addressed. Body biasing design techniques are not difficult to learn.

When the timeline of the semiconductor industry was based on a two-year window for new generations of process technology, taking an alternate path had high risks. But now with the lengthening of the timeline for new generations of technology -- and with 28nm and variants having high wafer volumes through 2020 -- the higher risk is in not making the optimum decision.

I welcome readers' views on how the 20nm dilemma will be resolved.

Handel Jones is chief executive of International Business Strategies, Inc.

Although double patterning is certainly a signficant barrier, a more aggressive shrinking (<0.7x) could bring back some more returns. Actually, the greater concern for me is the self-heating that could be aggravated in these thin silicon devices (FDSOI and FinFET). It's harder for heat to move away from hot spots in thin silicon. Even in the Intel trigate case, it has to move down from the narrowest point (the apex).