The meaning of the term "silicon compiler" has changed over the years as
advances in CAD tools have been made.
Initially it implied a glorious dream of specifying some extra switch
to a normal programming language compiler so, for example, it would
translate FORTRAN into layout, rather than into object code.
Soon, however, this dream was reduced to the use of regular methods for
converting logic into layout, such as
those discussed at the beginning of this chapter.
Although these methods do not use conventional programming languages as input,
they do translate from a layout-independent structural
or behavioral specification into
complete circuitry and therefore are called "silicon compilers".

The current excitement about silicon compilation began with the work on a
system called Bristle Blocks [Johannsen].
Here was a system that could take a high-level description of a processor
(an ISP description, see Chapter 2) and produce complex MOS layout
of the type often done by hand.
Although the system never produced completely working chips,
those that followed did [Southard], and they sparked a new meaning
for silicon compilers: systems that construct custom layout from high-level
languages.
No longer can a PLA generator be seriously called a silicon compiler.

The secret to the success of Bristle Blocks is the fact that its regularity
is in the floor-plan.
Rather than have a small regular structure that is customized, this
system has a processor floor-plan that is customized (see Fig. 4.18).
All aspects of the ISP language can be mapped into parts of this processor:
The data requirements specify the hardware datapaths and the control
requirements specify the structure of the PLA microcode decoder.
The datapath consists of columns of constant-width cells that
transfer data between the buses.
Each column is custom assembled to perform one of the specified processor
functions.
Special parameterized cells are textually described so they can adjust
their width and connections to stack correctly.
These cells are all designed to function with a two-phase clock for
synchronizing data transfer with processing.

FIGURE 4.18
Bristle Blocks architecture.

Modern silicon compilers translate structural descriptions into IC layout
using many of the same steps as do traditional language compilers.
A front-end parser reads the input description and converts it
to a structural representation such as the processor floor-plan used
by Bristle Blocks.
Some more advanced systems can handle higher-level behavioral
descriptions and reduce them to the structural level before producing
layout [Mitchell, Steinberg, and Schulman].
The back end then produces layout in two phases.
First, a set of procedurally defined cells are invoked to produce
the bulk of the circuitry for data operations.
Control sequences are often built with traditional PLA techniques.
Second, routers make the necessary connections between the major
structural components.
There are even optimization passes that can be invoked to compact
the layout.

Most silicon compilers are specialized to produce one type of design.
For example, FIRST always builds bit-serial chips for signal-processing
applications [Denyer, Murray and Renshaw].
In specialized silicon compilers, the input language can be very high level,
allowing nonprogrammers to specify chips for their own particular needs [Kahrs].
Another specialized silicon compiler, Miss Manners, compiles path
expressions into the necessary layout for synchronizing circuit
activity [Balraj and Foster].

Some silicon compilers have multiple architectures available
to them [Pope, Rabaey and Brodersen], but they all are restricted to
mapping a specific input language to a particular style of layout.
The most generalized commercial compilers simply have a larger set of
architectures available to them [SCI; Seattle Silicon; Buric and Matheson;
VTI].
Ayres describes a general-purpose language that can be used to construct
architectures, cell generators, and even analysis schemes for
silicon compilers [Ayres].

One way to improve the flexibility of silicon compilers is to have them
automatically select the correct architecture from the input specification.
Even harder would be to generate the architecture automatically according
to the needs of the specification.
If a silicon compiler could accept a general-purpose hardware-description
language and always produce a reasonable layout, then it would have achieved
its glorious initial goal.

Another approach to flexibility in silicon compilation is the use
of expert systems, which are collections of high-level rules
that interact to produce intelligent results.
Each rule is expressed as an if-then pair that shows a precondition
and an action to take.
The expert system continuously scans the list of rules to find and execute
those that are applicable.
Typically, there are two kinds of rules: control and
design.
Control rules direct the overall task, for example:

if need-an-inverter then
create-pullup,
create-pulldown,
connect-pullup-to-pulldown.

Rules can be arbitrarily complex and may interact with each other in
nonobvious ways.
However, given enough rules with the right preconditions, fairly
intelligent activity can be described.

Because the process of converting behavior to layout is so vast,
most expert systems tackle only one piece.
The Vexed system translates behavior to logic gates, seeking a structural
organization without attempting complete
layout [Mitchell, Steinberg, and Schulman].
By storing both actual behavior and required specifications, the system
knows when an adequate design has been produced.
Talib is an expert system that finishes the design task by translating
logic gates to nMOS layout [Kim, McDermott, and Siewiorek].

Some expert systems are specialized for particular tasks.
The Hephaestus system has rules for producing PLA and ring-oscillator
layouts [Simoudis and Fickas].
What makes this system interesting is its ability to track each design
decision and later to explain how a solution was achieved.

Expert systems may also be used exclusively for their control functions,
directing other expert or nonexpert system tools.
Such systems attempt to mimic the overall steps taken by human designers
who hierarchically organize their circuit.
In the Cadre system, multiple experts cooperate
in the layout task [Ackland et al.].
Starting with a structural specification of relative cell locations,
the system moves up and down the hierarchy to obtain a good layout.
A cell-generation expert is invoked first [Kollaritsch and Weste].
Next, a floor-plan is made and an evaluation expert determines whether the
cells or the floor-plan should be adjusted.
The manager expert controls this iteration until a satisfactory layout is
produced.
The notion of moving up and down the hierarchy is also found in other
expert systems [Gajski].

Silicon compilers are exciting because they raise the level at which design
is done.
It is no longer necessary to manipulate transistors in a layout.
The specification is at a much higher level, generally structural.
Silicon compilers must advance to the level at which they can handle any
abstract description, convert it to layout, and be efficient enough
to keep the designer from wanting to modify that layout.
Tools will then develop for simulating and analyzing the high-level
descriptions so that all design activity can take place at a comfortable
distance from IC layout.