Supported Processors

Xtensa Processor Architecture

The Xtensa processor architecture is a configurable and extensible synthesizable 32-bit RISC processor core. SoC and processor designers can select from a variety of options, such as instruction-set extensions (for example, narrow instructions, floating point instructions, etc.), memory, cache, and interrupt configurations. Moreover, Xtensa processors also support custom-defined instructions and registers. Nevertheless, all Xtensa processors share a common base instruction set architecture, thereby ensuring compatibility of third party application software and development tools.

Tensilica’s Diamond Standard Series processor family consists of a number of ready-to-use synthesizable cores and is based on the Xtensa processor architecture. The Diamond Standard 233L processor, for example, contains an MMU and fully supports running Linux.

Automatic Support for Custom Xtensa Cores

Despite the endless possibilities provided by the configurability and extensibility of the Xtensa architecture, generating an open source toolchain and kernel that fully support a specific configured Xtensa processor is straightforward. It only requires to update a small set of files inside the toolchain and kernel sources before the actual build process. All necessary files are typically provided by the processor vendor or directly from Tensilica in the form of a single overlay file. This mostly automated process (scripted) avoids having to manually port the kernel to a new processor variant, which would be typical for a fixed processor architecture.

Note that a processor configuration is also often referred to as a core variant in Linux. The following list shows processor configurations already included in the kernel: