I've been writing the CCS page on the wiki and I suddenly realized how a CAS works.

Now, if you're wondering why I was writing on the wiki about CCSs when I didn't understand the basic class-B/AB CAS, maybe you should check my work (a subtle hint to help me flesh out the wiki).

Most commonly in a CAS, the signal path is not separate from the output path, so voltage gain is zero. The togetherness of the signal and output paths makes NFB relatively simple: high-gain configurations (like the CFP) work quite well.

Now I present to you a low-power CFP Class AB output stage. C1 helps push/pull action, though a resistor in series might be beneficial. Quiescent current is theoretically about 27mA. Perhaps class-A is more practical for lower power like this but at least it shows I know something. THD at 1KHz is decent, especially with a 10k load.

I'm sure there's some tweaks I could make. You experienced readers feel free to educate me.

Looks to me like the current that the 47uf cap takes to charge to rail to rail voltage will have to come from the bases of the output transistors. This = output saturation for the time the cap is charging which most likely with BJT's = crispy, fried silicon chips.

__________________
All the trouble I've ever been in started out as fun......

Looks to me like the current that the 47uf cap takes to charge to rail to rail voltage will have to come from the bases of the output transistors. This = output saturation for the time the cap is charging which most likely with BJT's = crispy, fried silicon chips.

Definitely true. Maybe a much smaller (pF range) cap or no cap is better. As shown, the 22 ohm resistors will limit the current; it probably won't blow up on a real board, but it still isn't good.

With R3=56K I don't think C1 will do anything. Consider that its time constant (where the capacitor is halfway "kicking in") is 2.63 seconds, and that the original purpose of C1 was push-pull drive of the output Qs' bases at high frequencies. What you want there is a small capacitor with no series resistance (or inductance) - a few pF would do, try 100pF for starters. I don't think it is necessary at all though. Also, where is the signal input?

BTW, I have had very good results in many circuits using a simple JFET ccs - just tie the source and gate together and it will pass Idss, which is usually in the right range - 2-20mA depending on the FET. They don't match well but it is usually AC performance that matters, not DC. You can also get away with all N-channel JFETs, even in an otherwise complementary circuit; the component matching in such a circuit has to be better than mixing N and P-JFETs.

Quote:

Yes, the transistors only need one diode drop each however I don't want to get it too close to class B amplification.

The problem with running higher DC across the bases of Q1/Q2 is that you will need higher valued resistors for R5/R7 to reduce the idle current to something managable. With a single diode drop per output device, you can just use an ohm or two (or less on bigger devices); the output impedance is lower.

By the way, I just saw that your output devices are TO-92s. Watch out for the maximum dissipation on those! With +/- 30v rails, as you show, at 50mA bias, Q3 and Q4 will be dissipating 1475mW each. Q3/Q4 are going to go boom. Even at +/-12v as you showed originally, you'd be running 575mW - still a recipe for melted TO-92s. For TO-92s it's probably best to stay at or under 100mW - this will be a 20C rise over ambient temperature. Therefore, your idle current needs to be much lower.

By the way, I just saw that your output devices are TO-92s. Watch out for the maximum dissipation on those! With +/- 30v rails, as you show, at 50mA bias, Q3 and Q4 will be dissipating 1475mW each. Q3/Q4 are going to go boom. Even at +/-12v as you showed originally, you'd be running 575mW - still a recipe for melted TO-92s. For TO-92s it's probably best to stay at or under 100mW - this will be a 20C rise over ambient temperature. Therefore, your idle current needs to be much lower.

Yes, for lack of knowing any good high power pairs. I guess I'll try the bd139/140.

Quote:

why does the schematic in post 1 show 27mA passing q3 but only 0.1mA passing q2?

No earthly idea. I've never been able to get zero DC offset without some sort of feedback. I suspect that the transistors used are horribly matched. A better match (beta-wise according to LTSpice models) is the 5087 and 5210. Why is it that npn's always have at least 2x the beta of pnp's?

Oh yes, and I made a miscalculation with the circuit in my last post. R5 and R7 should be 47 ohms, not 10; this gives about 250mA quiescent current. Who said what about blowing to-92's!?

At any rate, here is my latest. For some reason it likes giving about 800mV pk-pk. It seems to me like its trying to turn 1mV to 1V, which would be a voltage gain of about 1k. R9 is feedback. The two germaniums can be replaced with a single silicon diode, but I was using them to test out the junction of the two bases as a possible feedback point. Both connections between Q13 and Q14 are candidates for feedback. Added Q2 and Q6 so that quiescent current cannot rise above about 75mA and so C1 won't crispy-fy the output pair. R1 and R4 are now 10k, which gives better OLG in the output drivers/pair, which also increases the effectiveness of the C1 coupling. R7 and R8 may be replaced with a trimmer with wiper to input so that output offset can be adjusted. However, this would also unevenly distribute signal between the output pair which would decrease maximum power output.