Multilayer-chip varistors mere prepared using the ZnO-glass system by applying tape casting technology. The effect of processing conditions on the multilayer ceramic microstructure and electrical properties mas studied. The location, size, and density of the pores within the multilayer structure were examined by scanning electron microscopy and the displacement method using distilled mater. The experimental results showed that the electrical properties of a multilayer-chip varistor could be influenced substantially by the porosities associated with environmental moisture in the range approximate to 15%-95% relative humidity at 25 degrees C. Such an effect can cause substantial current leakage as well as the separation of the I-V curves into four regions, i.e., prebreakdown, linear, breakdown, and upturn. A proposed pore model and equivalent circuit for the multilayer-chip ZnO varistors have been simulated with a commercial varistor and a serial resistance to demonstrate the observed I-V phenomena.