Runtime dynamic reconfiguration of field-programmable gate arrays (FPGAs) and devices incorporating microprocessors and FPGA has been successfully utilized to increase performance and reduce power consumption. While previous methods have been successful, they typically do not consider the runtime behavior of the application that can be significantly affected by variations in data inputs, user interactions, and environmental conditions. In this dissertation, we present a dynamically reconfigurable system and design methodology that optimizes performance and power consumption by determining which coprocessors to implement with an FPGA based upon the current application behavior.For dynamically reconfigurable systems, in which the selection of hardware coprocessors to implement within the FPGA is determined at runtime, online estimation methods are essential to evaluate the performance and power consumption impact of the hardware coprocessor selection. We present a base profile assisted online system-level performance and power estimation framework for estimating the speedup and power consumption of dynamically reconfigurable embedded systems.Importantly though, complex interactions between multiple application tasks, non-deterministic execution behavior, and effects of operating system scheduling introduce significant challenges. To address these, we further present an adaptive online performance and power estimation framework suing kernel speedup coefficient adaptation that monitors and adapts the changing application and system behavior for multitasked applications. By exhaustively examining predefined voltage and frequency settings for the microprocessor and hardware kernels, the potential speedup and power reduction can be effectively estimated for each configuration and voltage/frequency settings. These estimates can be utilized to determine the optimal system configuration. At the same time, the kernel speedup coefficients for each kernel can be dynamically updated to account for the difference between the estimated and actual performance measured at runtime.Finally, in order to quickly determine kernel selection and voltage and frequency settlings, we present an efficient, online heuristic performance and power estimation framework that significantly decreases execution time at the cost of a small increase in power consumption. This online heuristic estimation framework achieves significant power reduction compared to software only implementation without performance degradation.

Runtime dynamic reconfiguration of field-programmable gate arrays (FPGAs) and devices incorporating microprocessors and FPGA has been successfully utilized to increase performance and reduce power consumption. While previous methods have been successful, they typically do not consider the runtime behavior of the application that can be significantly affected by variations in data inputs, user interactions, and environmental conditions. In this dissertation, we present a dynamically reconfigurable system and design methodology that optimizes performance and power consumption by determining which coprocessors to implement with an FPGA based upon the current application behavior.For dynamically reconfigurable systems, in which the selection of hardware coprocessors to implement within the FPGA is determined at runtime, online estimation methods are essential to evaluate the performance and power consumption impact of the hardware coprocessor selection. We present a base profile assisted online system-level performance and power estimation framework for estimating the speedup and power consumption of dynamically reconfigurable embedded systems.Importantly though, complex interactions between multiple application tasks, non-deterministic execution behavior, and effects of operating system scheduling introduce significant challenges. To address these, we further present an adaptive online performance and power estimation framework suing kernel speedup coefficient adaptation that monitors and adapts the changing application and system behavior for multitasked applications. By exhaustively examining predefined voltage and frequency settings for the microprocessor and hardware kernels, the potential speedup and power reduction can be effectively estimated for each configuration and voltage/frequency settings. These estimates can be utilized to determine the optimal system configuration. At the same time, the kernel speedup coefficients for each kernel can be dynamically updated to account for the difference between the estimated and actual performance measured at runtime.Finally, in order to quickly determine kernel selection and voltage and frequency settlings, we present an efficient, online heuristic performance and power estimation framework that significantly decreases execution time at the cost of a small increase in power consumption. This online heuristic estimation framework achieves significant power reduction compared to software only implementation without performance degradation.

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dc.type

text

en_US

dc.type

Electronic Dissertation

en_US

dc.subject

online estimation

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dc.subject

performance and power estimation

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dc.subject

Electrical & Computer Engineering

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dc.subject

adaptable systems

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dc.subject

dynamically reconfigurable embedded systems

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thesis.degree.name

Ph.D.

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thesis.degree.level

doctoral

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thesis.degree.discipline

Graduate College

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thesis.degree.discipline

Electrical & Computer Engineering

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thesis.degree.grantor

University of Arizona

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dc.contributor.advisor

Lysecky, Roman

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dc.contributor.committeemember

Rozenblit, Jerzy

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dc.contributor.committeemember

Lysecky, Susan

en_US

dc.contributor.committeemember

Szidarovszky, Ferenc

en_US

dc.contributor.committeemember

Lysecky, Roman

en_US

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