1. Power system architecture :
1.1 NB power system introduction
1.2 Power sequence and control
Power plan introduction :
2.1 Power budget block diagram 2.2
NB power application
2.3 Multi–power device
No power debug :
3.1 No power debug notice & sequence
3.2 DCBATOUT short to GND 3.2 S5
Power No Good
3.3 Power on logic No Good

Foreword :

As we know, notebook power is provided by adaptors
(1(199VV)) or batteries (14.8V ). However, the
various( power voltages do not fit all devices in a notebook
unit. So a series of voltage transfer actions are needed to
provide power to all devices. (Problems may
arise( during the voltage transfer.)
As notebook is a portable computer, saving power is
also very important when the system is in battery mode.
In this lesson, we will use the Yuhina power circuit to
introduce the notebook power system.

1.Power system architecture

1.1 NB (Yuhina) power system : AUX Power

1.Power system architecture1.1 NB (Yuhina) power system : S5 Power

1.Power system architecture

1.1 NB (Yuhina) power system : S3 Power

1.Power system architecture

1.1 NB (Yuhina) power system : S0 Power

1.2 Power sequence and control

Why do we need to differentiate power type among( 在 ... 之中 ) AUX,S5,
S3,S0 ?How do we control them ?
Here is the answer:• AUX Power : For power button use , it is turned on with battery only
before you press the power button .
• S5 Power : For power button & wake on LAN use , it is turned on
with adapter before you press the power button .
• S3 Power : For stand_by mode use , it is turned on with South bridge
PM_SLP_S3# after you press the power button .
• S0 Power : For normal mode use , it is turned on with South bridge -
PM_SLP_S4# after you press the power button .

Block Diagram :

1.2.1 AUX_Power

When the battery or adaptor is

1.2.2 S5_Powera. Circuit operation – Power on logic :
1- The AC_IN signal was pulled hi when Adaptor was inserted .
2- Power on logic will output MAX1999_SD hi to trigger 3D3V_S5.
As a result, when Adaptor is inserted but power button has yet been
pressed,the S5_power will be turned on first .

1- When AC_IN is HI,
2- The MOS-U13 will be turned on, and 3D3V_LAN_S5 will be generated.
This power is for wake on LAN function.
3- The 1D5V_S5 LDO power will be turned on by 3D3V_S5 .
This power is for south bridge for wake on LAN usage .
Because adaptor power was inserted already, the Battery leakage current is not
a concern now.

1.2.3 S3_Power ：

Circuit operation – 5V_S3 :When the power button was pressed, south bridge will pull hi the
PM_SLP_S4#, and 5V_S3 power will be generated .

b. Circuit operation – 3D3V_S3 :3D3V_S3 power is generated by U25 N-MOS from 3D3V_S5 when
PM_SLP_S4# is hi .

After PM_SLP_S4# signal was generated for a few µ sec , the
South Bridge will output PM_SLP_S3# on hi level, and 1D5V_S0 will
be turned on .

b. Circuit operation – 5V,3D3V,&2D5V_S0 :

PM_SLP_S3# signal is also used to turn on 5V 、 3D3V 、 2D5V_S0.

c.Circuit operation – P4 CPU VCC_CORE_S0:

-- P4 CPU_ VCO power – architecture :

c.Circuit operation – P4 CPU VCC_CORE_S0:

1: 3D3V_S0 power on .
2: CM2843 provides 1D2V_VID to CPU.
3: CPU provides VID code
4: PWRGD_VID, which is provided by CM2843, will delay 1ms
while 1D2V_VID is on. So it will be turned on after the CPU VID code.

c.Circuit operation – P4 CPU VCC_CORE_S0:1: The step-down circuit starts working as soon as the switch signal begins.
2: The VCC_CORE is produced and will provide the CPU’s working power .
PS. This is one of the three phases in VCC_CORE.

d. P4 & Banias CPU VCC_CORE_S0 difference :

The power system can separate two kinds of architecture for CPU.
But the only difference between P4 and Banias CPU power
architecture is VCC_COER_S0. Such as below :