All the Perl that's Practical to Extract and Report

Navigation

The Fine Print: The following comments are owned by whoever posted them. We are not responsible for them in any way.
Without JavaScript enabled, you might want to
use the classic discussion system instead. If you login, you can remember this preference.

Please Log In to Continue

VHDL's generate construct (and the "for" loop used in processes) is not only for module instantiations. It's indeed capable of making what you demonstrated.

Anyhow, as a hardware engineer I find Perl very useful - it's automating a lot of tasks for me - including HDL code generation. When it comes to us logic designers / embedded engineers, Perl is one of the most useful and respected languages.