Abstract

The semiconductor memory includes a column address counter, a burst length counter and a data output switching circuit. Data are processed in synchronism with an externally applied clock. The memory has a circuit for setting a predetermined write time value and for holding the column address counter, burst length counter and data output switching circuit for a predetermined time interval determined by the write time value. The write time value determines the number of clock pules of the system clock that are counted from the time that the activation of a write control signal applied from outside, until the input data are transferred to an internal data bus.

Da Datensignale in Übereinstimmung mit der Bündellänge erzeugt oder empfangen werden sollten, nachdem die Bündellänge in das MRS programmiert worden ist, ist es in dem synchronen dynamischen RAM notwendig, den Zeitpunkt zu erkennen, um intern den Daten-Eingang/-Ausgang zu stoppen. Since data signals should be generated in accordance with the burst length or received after the bundle length has been programmed into the MRS, it is necessary in the synchronous dynamic RAM to recognize the time to internally to stop the data input / output.Dies wird erreicht durch Vergleich einer Taktimpulszählung mit einem in das MRS einprogrammierten und in dem Register gespeicherten Wert. This is achieved by comparing a clock pulse count with a programmed into the MRS and stored in the register value.Ein diesem Vorgang dienender Zähler wird als Bündelendezähler bezeichnet. A process serving this counter is called a bundle end counter.