... The ST62E62B is the erasable EPROM version of the ST62T62B device, which may be used to em- ulate the ST62T52B and ST62T62B devices as well as the ST6252B and ST6262B ROM devices. OTP and EPROM devices are functionally identi- cal ...

... PB6/ARTIMin and PB7/ARTI- ST62T52B ST62T62B/E62B Mout are either Port B I/O bits or the Input and Output pins of the ARTimer. Reset state of PB2-PB3 pins can be defined by option either with pull-up or high impedance ...

... EPROM context erasure. Note: Once the Readout Protection is activated longer possible, even for SGS-THOMSON, to gain access to the OTP contents. Returned parts with a protection set can therefore not be ac- cepted. ST62T52B ST62T62B/E62B Figure 4. ST62T52B/T62B Program Memory Map 0000h * RESERVED 087Fh ...

... EECTL it must also write to the image register. The image regis- ter must be written to first so that interrupt oc- curs between the two instructions, the EECTL will not be affected ST62T52B ST62T62B/E62B Dataspace addresses. Banks 0 and 38h-3Fh 30h-37h 28h-2Fh ...

... ST62T52B ST62T62B/E62B MEMORY MAP (Cont’d) Additional Notes on Parallel Mode: If the user wishes to perform parallel program- ming, the first step should be to set the E2PAR2 bit. From this time on, the EEPROM will be ad- dressed in write mode, the ROW address will be latched and it will be possible to change it only at the end of the programming cycle resetting E2PAR2 without programming the EEPROM ...

... PC menu (PC driven Mode) or automatically (stand-alone mode) 1.4.2 Program Memory EPROM/OTP programming mode is set by a +12.5V voltage applied to the TEST/V 0 programming flow of the ST62T62B is described in the User Manual of the EPROM Programming - Board. The MCUs can be programmed with the ST62E6xB EPROM programming tools available from SGS-THOMSON ...

... Switching between the three sets of flags is per- formed automatically when an NMI, an interrupt or a RETI instructions occurs. As the NMI mode is ST62T52B ST62T62B/E62B automatically selected after the reset of the MCU, the ST6 core uses at first the NMI flags. Stack. The ST6 CPU includes a true LIFO hard- ware stack which eliminates the need for a stack pointer ...

... ST62T52B ST62T62B/E62B 3 CLOCKS, RESET, INTERRUPTS AND POWER SAVING MODES 3.1 CLOCK SYSTEM The MCU features a Main Oscillator which can be driven by an external clock, or used in conjunction with an AT-cut parallel resonant crystal or a suita- ble ceramic resonator, or with an external resistor (R ). NET Figure 8. illustrates various possible oscillator con- ...

... ST62T52B ST62T62B/E62B 3.2 RESETS The MCU can be reset in three ways: – by the external Reset input being pulled low; – by Power-on Reset; – by the digital Watchdog peripheral timing out. 3.2.1 RESET Input The RESET pin may be connected to a device of the application board in order to reset the MCU if required ...

... ST62T52B ST62T62B/E62B DIGITAL WATCHDOG (Cont’d) The Watchdog is associated with a Data space register (Digital WatchDog Register, DWDR, loca- tion 0D8h) which is described in greater detail in Section 3.3.1 Digital Watchdog Register This register is set to 0FEh on Reset: bit C is cleared to “0”, which disables the Watchdog; the timer downcounter bits T5, and the SR bit are all set to “ ...

... The software activation option should be chosen only when the Watchdog counter used as a timer. To ensure the Watchdog has not been un- expectedly activated, the following instructions should be executed within the first 27 instructions: jrr 0, WD, #+3 ldi WD, 0FDH ST62T52B ST62T62B/E62B 23/68 23 ...

... ST62T52B ST62T62B/E62B DIGITAL WATCHDOG (Cont’d) These instructions test the C bit and Reset the MCU (i.e. disable the Watchdog) if the bit is set (i.e. if the Watchdog is active), thus disabling the Watchdog. In all modes, a minimum of 28 instructions are ex- ecuted after activation, before the Watchdog can generate a Reset ...

... ST62T52B ST62T62B/E62B IINTERRUPTS (Cont’d) 3.4.2 Interrupt Procedure The interrupt procedure is very similar to a call procedure, indeed the user can consider the inter- rupt as an asynchronous call procedure. As this is an asynchronous event, the user cannot know the context and the time at which it occurred re- sult, the user should save all Data space registers which may be used within the interrupt routines ...

... Watchdog), the MCU enters a normal reset proce- dure interrupt is generated during WAIT mode, the MCU’s behaviour depends on the state ST62T52B ST62T62B/E62B of the processor core prior to the WAIT instruction, but also on the kind of interrupt request which is generated. This is described in the following para- graphs ...

... ST62T52B ST62T62B/E62B POWER SAVING MODE (Cont’d) 3.5.3 Exit from WAIT and STOP Modes The following paragraphs describe how the MCU exits from WAIT and STOP modes, when an inter- rupt occurs (not a Reset). It should be noted that the restart sequence depends on the original state ...

... ST62T52B ST62T62B/E62B I/O PORTS (Cont’d) 4.1.1 Operating Modes Each pin may be individually programmed as input or output with various configurations. This is achieved by writing the relevant bit in the Data (DR), Data Direction (DDR) and Option reg- isters (OR). Table 11 I/O Port Option Selection lustrates the various port configurations which can be selected by user software ...

... Open Drain Output Push-pull Note *. xxx = DDR, OR, DR Bits respectively ST62T52B ST62T62B/E62B outputs advisable to keep a copy of the data register in RAM. Single bit instructions may then be used on the RAM copy, after which the whole copy register can be written to the port data regis- ...

... ST62T52B ST62T62B/E62B 4.2 TIMER The MCU features an on-chip Timer peripheral, consisting of an 8-bit counter with a 7-bit program- mable prescaler, giving a maximum count of 2 Figure 21. shows the Timer Block Diagram. The content of the 8-bit counter can be read/written in the Timer/Counter register, TCR, which can be addressed in Data space as a RAM location at ad- dress 0D3h ...

... ST62T52B ST62T62B/E62B TIMER (Cont’d) A write to the TCR register will predominate over the 8-bit counter decrement to 00h function, i. write and a TCR register decrement to 00h occur simultaneously, the write will take precedence, and the TMZ bit is not set until the 8-bit counter reaches 00h again ...

... The PWM signal is generated on the ARTIMout pin (refer to the Block Diagram). The frequency of this signal is controlled by the prescaler setting and by the auto-reload value present in the Re- load/Capture register, ARRC. The duty cycle of the PWM signal is controlled by the Compare Register, ARCP. ST62T52B ST62T62B/E62B 39/68 39 ...

... VALUE RELOAD REGISTER 000 PWM OUTPUT ST62T52B ST62T62B/E62B The ARTC counter is initialized by writing to the ARRC register and by then setting the TCLD (Tim- er Load) and the TEN (Timer Clock Enable) bits in the Mode Control register, ARMC. Enabling and selection of the clock source is con- trolled by the CC0, CC1, SL0 and SL1 bits in the Status Control Register, ARSC1 ...

... ST62T52B ST62T62B/E62B AUTO-RELOAD TIMER (Cont’d) Capture Mode with PWM Generation. In this mode, the AR counter operates as a free running 8-bit counter fed by the prescaler output. The counter is incremented on every clock rising edge. An 8-bit capture operation from the counter to the ARRC register is performed on every active edge on the ARTIMin pin, when enabled by Edge Con- trol bits SL0, SL1 in the ARSC1 register ...

... The flag is cleared by writing a zero to the CPF bit. Bit 0 = OVF: Overflow Interrupt Flag. This bit is set by a transition of the counter from FFh to 00h (overflow). The flag is cleared by writing a zero to the OVF bit. ST62T52B ST62T62B/E62B ARMC0 Operating Mode 0 Auto-reload Mode 1 ...

... If PDS=“1”, the A/D is powered and enabled for conversion. This bit must be set at least one instruction before the beginning of the ST62T52B ST62T62B/E62B conversion to allow stabilisation of the A/D con- verter. This action is also needed before entering WAIT mode, since the A/D comparator is not auto- matically disabled in WAIT mode ...

... ST62T52B ST62T62B/E62B A/D CONVERTER (Cont’d) Since the ADC is on the same chip as the micro- processor, the user should not switch heavily loaded output signals during conversion, if high precision is required. Such switching will affect the supply voltages used as analog references. The accuracy of the conversion depends on the ...

... Extended. In the extended addressing mode, the 12-bit address needed to define the instruction is obtained by concatenating the four less significant ST62T52B ST62T62B/E62B bits of the opcode with the byte following the op- code. The instructions (JP, CALL) which use the extended addressing mode are able to branch to any address of the 4K bytes Program space ...

... ST62T52B ST62T62B/E62B 5.3 INSTRUCTION SET The ST6 core offers a set of 40 basic instructions which, when combined with nine addressing modes, yield 244 usable opcodes. They can be di- vided into six different types: load/store, arithme- tic/logic, conditional branch, control instructions, jump/call, and bit manipulation. The following par- agraphs describe the different types ...

... ST62T52B ST62T62B/E62B INSTRUCTION SET (Cont’d) Conditional Branch. The branch instructions achieve a branch in the program when the select- ed condition is met. Bit Manipulation Instructions. These instruc- tions can handle any bit in data space memory. One group either sets or clears. The other group (see Conditional Branch) performs the bit test branch operations ...

... ST62P52B ST62P62B 1 GENERAL DESCRIPTION 1.1 INTRODUCTION The ST62P52B and ST62P62B are the Factory Advanced Service Technique ROM (FASTROM) version of ST62T52B and ST62T62B OTP devic- es. They offer the same functionality as OTP devices, selecting as FASTROM options the options de- fined in the programmable option byte of the OTP version ...

... GENERAL DESCRIPTION 1.1 INTRODUCTION The ST6252B and ST6262B are mask pro- grammed ROM version of ST62T52B and ST62T62B OTP devices. They offer the same functionality as OTP devices, selecting as ROM options the options defined in the programmable option byte of the OTP version. Figure 1. Programming wave form ...

ST6252B ST6262B 1.3 ORDERING INFORMATION The following section deals with the procedure for transfer of customer codes to SGS-THOMSON. 1.3.1 Transfer of Customer Code Customer code is made up of the ROM contents and the list of the selected mask ...