The course begins with a short review of SystemVerilog classes and class constructs, together with an overview of object-oriented concepts and features.

The majority of the course describes a methodology for using the building blocks of the UVM class library to create configurable, reusable UVM Verification Components (UVCs) based on a standard architecture, and with embedded randomization, coverage, and self-checking. The course then shows you how to combine multiple UVCs into a flexible, powerful verification environment.

Learning Objectives

After completing this course, you will be able to:

Understand the features and capabilities of the UVM class library for SystemVerilog

Create and configure UVCs for your verification environments

Combine UVCs to implement a verification environment based on a proven methodology for creating reusable, scalable, and robust verification components