The Pseudo-SRAM’s standard SRAM interface and 1-transistor DRAM-like memory cell make it an easy design-in for cellular phone and PDA applications, while providing a much lower cost than a traditional SRAM cell would at this density.

Until now, for applications requiring at least 4 megabytes (MB) of SRAM memory, designers had to design-in a multi-chip memory solution to meet those requirements.

With the high density of Toshiba’s Pseudo-SRAM a single-chip SRAM memory solution is possible. In addition, the 48 ball fine pitch ball grid array (FBGA) packaging further reduces the requirements for board space as compared to traditional SRAM or DRAM devices housed in thin-small-outline (TSOP) packaging.

In addition, to meet the high-density memory requirements in wireless and portable communications devices, designers have relied on DRAM solutions.

Its SRAM-like interface and self-refresh feature make the Pseudo-SRAM easy to design-in. Glue-logic, which is typically needed for the refresh operations with standard DRAM is not required for Pseudo-SRAM.

Toshiba’s 32Mb Pseudo SRAM operates using a single power supply voltage range of 2.50 volts (V) to 3.1V. Its standby current is 70 microamperes (A) with a deep power down standby mode of 5A.

The device also operates in a page mode with a page read operation of four words. It is logic compatible with SRAM write enable input.