PRODUCTSLPDDR3

H9CKNNNBKTMTDR

LPDDR3-SDRAM is a high-speed synchronous DRAM device internally configured as an 8-bank memory.

These devices contain the following number of bits:8 Gb has 8,589,934,592 bits

LPDDR3 devices use a double data rate architecture on the Command/Address (CA) bus to reduce the number of inputpins in the system. The 10-bit CA bus contains command, address, and bank information. Each command uses one clockcycle, during which command information is transferred on both the positive and negative edge of the clock.These devices also use a double data rate architecture on the DQ pins to achieve high speed operation. The double datarate architecture is essentially an 8n prefetch architecture with an interface designed to transfer two data bits per DQevery clock cycle at the I/O pins. A single read or write access for the LPDDR3 SDRAM effectively consists of a single8n-bit wide, one clock cycle data transfer at the internal DRAM core and eight corresponding n-bit wide, one-half-clockcycledata transfers at the I/O pins.Read and write accesses to the LPDDR3 SDRAMs are burst oriented; accesses start at a selected location and continuefor a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Activatecommand, which is then followed by a Read or Write command. The address and BA bits registered coincident with theActivate command are used to select the row and the bank to be accessed. The address bits registered coincident withthe Read or Write command are used to select the bank and the starting column location for the burst access.Prior to normal operation, the LPDDR3 SDRAM must be initialized. The following section provides detailed informationcovering device initialization, register definition, command description and device operation.

Double data rate architecture for command, address and data Bus;- all control and address except CS_n, CKE latched at both rising and falling edge of the clock- CS_n, CKE latched at rising edge of the clock- two data accesses per clock cycle