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David Culler Electrical Engineering and Computer Sciences University of California, Berkeley

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Timing Methodology • Rules for interconnecting components and clocks • Guarantee proper operation of system when strictly followed • Approach depends on building blocks used for storage elements • Focus on systems with edge-triggered flip-flops • Found in programmable logic devices • Many custom integrated circuits focus on level-sensitive latches • Basic rules for correct timing: • (1) Correct inputs, with respect to time, are provided to the flip-flops • Everything is stable when the clock ticks • (2) No flip-flop changes state more than once per clocking event EECS 150, Fa07, Lec 08-timing-synth

D D Q Q Tsu Th input clock Timing Methodologies (cont’d) • Definition of terms • clock: periodic event, causes state of storage element to change; can be rising or falling edge, or high or low level • setup time: minimum time before the clocking event by which the input must be stable (Tsu) • hold time: minimum time after the clocking event until which the input must remain stable (Th) data clock there is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized stable changing data clock EECS 150, Fa07, Lec 08-timing-synth

Clock Skew • The problem • Correct behavior assumes next state of all storage elementsdetermined by all storage elements at the same time • Difficult in high-performance systems because time for clock to arrive at flip-flop is comparable to delays through logic (and will soon become greater than logic delay) • Effect of skew on cascaded flip-flops: 100 In Q0 Q1 CLK0 CLK1 CLK1 is a delayed version of CLK0 original state: IN = 0, Q0 = 1, Q1 = 1 due to skew, next state becomes: Q0 = 0, Q1 = 0, and not Q0 = 0, Q1 = 1 EECS 150, Fa07, Lec 08-timing-synth

Summary of Latches and Flip-Flops • Development of D-FF • Level-sensitive used in custom integrated circuits • can be made with 4 switches • Edge-triggered used in programmable logic devices • Good choice for data storage register • Historically J-K FF was popular but now never used • Similar to R-S but with 1-1 being used to toggle output (complement state) • Good in days of TTL/SSI (more complex input function: D = JQ' + K'Q • Not a good choice for PLAs as it requires two inputs • Can always be implemented using D-FF • Preset and clear inputs are highly desirable on flip-flops • Used at start-up or to reset system to a known state EECS 150, Fa07, Lec 08-timing-synth

B has the same value in both on-set rows– B remains A has a different value in the two rows– A is eliminated The Uniting Theorem • Key tool to simplification: A (B' + B) = A • Essence of simplification of two-level logic • Find two element subsets of the ON-set where only one variable changes its value – this single varying variable can be eliminated and a single product term used to represent both elements F = A'B'+AB' = (A'+A)B' = B' A B F 0 0 1 0 1 0 1 0 1 1 1 0 EECS 150, Fa07, Lec 08-timing-synth

m-dimensional cubes in a n-dimensional Boolean space • In a 3-cube (three variables): • 0-cube, i.e., a single node, yields a term in 3 literals • 1-cube, i.e., a line of two nodes, yields a term in 2 literals • 2-cube, i.e., a plane of four nodes, yields a term in 1 literal • 3-cube, i.e., a cube of eight nodes, yields a constant term "1" • In general, • m-subcube within an n-cube (m < n) yields a term with n – m literals EECS 150, Fa07, Lec 08-timing-synth

Announcements • Typo corrected on HW3, prob. 1 • P3, yes there is an input to each controller described in the text that is not shown in the picture. • HW4 out tonight – it is a mid term review • Review session Tues • Mid term next Thurs in 125 Cory • Everything you want to know at hkn/student/online/cs/150 … EECS 150, Fa07, Lec 08-timing-synth

Definition of terms for two-level simplification • Implicant • Single element of ON-set or DC-set or any group of these elements that can be combined to form a subcube • Prime implicant • Implicant that can't be combined with another to form a larger subcube • Essential prime implicant • Prime implicant is essential if it alone covers an element of ON-set • Will participate in ALL possible covers of the ON-set • DC-set used to form prime implicants but not to make implicant essential • Objective: • Grow implicant into prime implicants (minimize literals per term) • Cover the ON-set with as few prime implicants as possible(minimize number of product terms) EECS 150, Fa07, Lec 08-timing-synth

Algorithm for two-level simplification • Algorithm: minimum sum-of-products expression from a Karnaugh map • Step 1: choose an element of the ON-set • Step 2: find "maximal" groupings of 1s and Xs adjacent to that element • consider top/bottom row, left/right column, and corner adjacencies • this forms prime implicants (number of elements always a power of 2) • Repeat Steps 1 and 2 to find all prime implicants • Step 3: revisit the 1s in the K-map • if covered by single prime implicant, it is essential, and participates in final cover • 1s covered by essential prime implicant do not need to be revisited • Step 4: if there remain 1s not covered by essential prime implicants • select the smallest number of prime implicants that cover the remaining 1s EECS 150, Fa07, Lec 08-timing-synth

Simulation and Functional Verification • Simulation vs. Formal Methods • Test Plan Development • What functions are to be tested and how • Testbench Development • Testing of independent modules • Testing of composed modules • Test Execution and Model Verification • Errors in design • Errors in description syntax • Ensure that the design can be synthesized • The model must be VERIFIED before the design methodology can proceed EECS 150, Fa07, Lec 08-timing-synth

Design Integration and Verification • Integrate and test the individual components that have been independently verified • Appropriate testbench development and integration • Extremely important step and one that is often the source of the biggest problems • Individual modules thoroughly tested • Integration not as carefully tested • Bugs lurking in the interface behavior among modules! EECS 150, Fa07, Lec 08-timing-synth

Presynthesis Sign-off • Demonstrate full functionality of the design • Make sure that the behavior specification meets the design specification • Does the demonstrated input/output behavior of the HDL description represent that which is expected from the original design specification • Sign-off only when all functional errors have been eliminated EECS 150, Fa07, Lec 08-timing-synth