You may be able to push it further, but there are rapidly diminishing returns in performance, and it quickly becomes difficult to test stability in a reasonable amount of time.
This is definitely worth mentioning, and why the efficiency score should be ignored.

Looks like it went smoothly, 12 hour custom blend test stable. That is generally enough for me to be comfortable with the results... Thanks for all the help man! I may tweak it further, but I think I can take it from here.

Just curious, if I wish to make an attempt at a command rate of 1, what timings should I loosen, and to what degree? My RAM is infuriatingly close to being stable at a CR of 1 at 1.65V, it will boot and perform fine but fail benchmarks.

Just curious, if I wish to make an attempt at a command rate of 1, what timings should I loosen, and to what degree? My RAM is infuriatingly close to being stable at a CR of 1 at 1.65V, it will boot and perform fine but fail benchmarks.

I would give the CPU more VCCSA (unless you are high already) before trying to loosen anything. Failing that, the only timing likely to make a large enough difference to stabilize a lower CR is CAS or maybe TCCD, both of which have pretty serious performance impact.

I would give the CPU more VCCSA (unless you are high already) before trying to loosen anything. Failing that, the only timing likely to make a large enough difference to stabilize a lower CR is CAS or maybe TCCD, both of which have pretty serious performance impact.

At what number would increasing the CAS not be worth the CR of 1? It currently sits at 11 (it will not tolerate anything lower), while my tCCD is 0. I am using 1V VCCSA, but jumping it to 1.1V did absolutely nothing noticable (bench still failed within a minute).

Also, completely unrelated... but I was tinkering with tRAS and man does that let you take it low... I am at 22 (from 31) and still able to potentially tweak it lower. That said, it may be one of those values with a hard minimum, so it could be misleading and it simply lets me set it as low as allowable in bios.

*EDIT* Final verdict: tRAS was able to go as low as 13, 12 caused BSOD. I verified that it was, in fact, a setting that worked in the BIOS by setting it there after the crash via MemTweakIt. This seems highly odd considering most sources state a tRAS of CL+tRCD is as best as you can usually expect, and for me that would be 24.Edited by KarateF22 - 11/5/13 at 10:38pm

If you can get CAS of 12 to work with CR1, it might be worth it, but even that is iffy.

Ultra low tRAS is rarely an overall benefit to performance. Memory write performance in particular seems to suffer from too low tRAS. Some benchmarks may show a minor improvement, but in my experience, you'll either run into stability issues that are difficult to pin down, or lose real performance if tRAS is too low. The only exception I've personally seen was back in the DDR days when Winbond chips could run tRAS 1 or 0, so the window would be reopened every clock cycle, which could be made stable with enough voltage (~3.5v on 2.5v parts) and cooling.

With DDR3, I try to keep tRAS betwen CAS + tRCD + B2B CAS Delay (almost always 4) as a minimum, and CAS + 2*tRCD as a maximum. There seems to be little real benefit to performance or stability outside these ranges, but it's not rare for even significantly lower settings to work.

If you can get CAS of 12 to work with CR1, it might be worth it, but even that is iffy.

Ultra low tRAS is rarely an overall benefit to performance. Memory write performance in particular seems to suffer from too low tRAS. Some benchmarks may show a minor improvement, but in my experience, you'll either run into stability issues that are difficult to pin down, or lose real performance if tRAS is too low. The only exception I've personally seen was back in the DDR days when Winbond chips could run tRAS 1 or 0, so the window would be reopened every clock cycle, which could be made stable with enough voltage (~3.5v on 2.5v parts) and cooling.

With DDR3, I try to keep tRAS betwen CAS + tRCD + B2B CAS Delay (almost always 4) as a minimum, and CAS + 2*tRCD as a maximum. There seems to be little real benefit to performance or stability outside these ranges, but it's not rare for even significantly lower settings to work.

CR wouldn't take, so I abandoned that route... it is interesting to note that my timings do not seem to respond to voltage at all. I cannot reach a higher CAS, CS, tRAS, or anything else at 1.65V compared to 1.55V. Extra voltage has, thus far, only affected the stability of RAM frequency. Speaking of tRAS, looks like I am reverting that change as every thread but one eventually failed over a 12 hour period... yet oddly enough the system didn't crash. Huh.