Part 2: EIPC’s 2018 Winter Conference in Lyon, Review of Day 1

Editor's Note: If you missed the beginning of this article click here.

Tamara den Daas-Wijnen, OEM Global Account Manager with Ventec International Group, discussed ultra-low Dk laminates for low-loss designs. She began by commenting that it was common for designers of high frequency PCBs to be concerned primarily with the loss tangent (Df) of a laminate, without considering it in combination with its dielectric constant (Dk), whereas the two properties were inseparable. She emphasised the importance of understanding the “impedance triangle,” a simple graphical representation demonstrating that for a given Dk and Df, the closer the controlled impedance conductor to the reference plane, the narrower it became. The consequence was that thinner layers required finer traces, which could lead to reduced yield in manufacture. Skin effect was also a significant contributor to signal losses and was more pronounced the finer the conductor. Hence it was desirable to keep conductors as wide as possible. She demonstrated that by decreasing the Dk, but maintaining the impedance, the track width could be increased and hence the trace resistance lowered.

Ventec had developed and qualified a cost-effective family of ultra-low Dk materials with enhanced insertion loss performance, based on a reacted polyphenylene oxide/PTFE/hydrocarbon resin chemistry which could be processed on a standard FR-4 line. Current trace widths could be maintained with smaller layer-to-layer separation, therefore Z-axis packaging density could be increased whilst maintaining or increasing trace width and giving the option of more layers for a given PCB thickness.

Stig Källman, global component engineer for PCB with Ericsson, described a PCB material toolbox to support today’s 3G and 4G networks and future high speed needs in 5G, in the most cost-effective and environmental way. He used the analogy of a Big Mac to illustrate the concept: “With the right recipe the taste is the same wherever you go…”

With the objective of standardization, he discussed the material constituents of laminate: glass, glass weave, copper and resin. It was his philosophy to know the impact of the prepreg, the impact of copper and the impact of process tolerances before considering suitable resin systems and selecting material suppliers. The first objective was to be cost-effective, using cost-efficient layer stack-ups and via structures, knowing manufacturing variation to avoid over-design, and achieving high manufacturing panel utilization.

He listed and detailed the recognized PCB technology drivers: smaller, faster, warmer, energy efficiency and environmental acceptability, and discussed the properties and needs of current halogen-free PCB materials covering the spectrum from standard FR-4.1 to microwave. For the future, the actual Df value of a material would be less significant than being able to hold that value steady over a range of temperatures. And dimensional stability would be increasingly important. He commented that the figures quoted on laminate suppliers’ data sheets were becoming more reliable. For the future, standardisation of copper surface roughness was urgently required, with classification in three levels of Ra being suggested. Materials needed to be UL-qualified to higher maximum operating temperatures, and design constraints should be introduced in minimum hole-wall to hole-wall distances to avoid CAF effects.

With regard to 5G, Källman showed videos demonstrating that 5G was becoming a reality, and Ericsson had already established a global 5G access and transport portfolio, with many additional hardware and software products in development.

Erkko Helminen, advanced development senior manager in corporate technology at TTM Technologies, gave a PCB fabricator’s perspective on the effects of 5G as a driver of PCB technology and processes.

The key feature of the next generation cellular network was 5G New Radio (NR), the global standard for a new air interface based on orthogonal frequency-division multiplexing (OFDM), designed to support the wide variation of 5G device-types. 5G NR technology development was already in progress, with emphasis on data rate, bandwidth, latency and energy saving. With frequencies trending from sub-6GHz towards 100GHz, multiple-input multiple-output mobile antenna design and fabrication became a challenge, with etching and registration accuracy being critical and innovative processes such as laser structuring being possible alternatives, and improvements in current millimetre-wave substrates being sought.

In ICT, the key next-generation PCB technology drivers were signal integrity, radio-frequency engineering and component miniaturization, and tighter and tighter tolerances would inevitably be demanded. HDI provided advantages in RF and high-speed PCBs.

Smartphone evolution was characterised by the increasing complexity of the advanced semiconductor package technology, antenna integration and placement, and the expansion of battery capacity. Consequently, the PCB was being forced into smaller spaces, with miniaturisation achieved by a shift from 100 micron subtractive-technology HDI, through 50 micron any-layer, towards 15 micron SLP and mSAT.

Driver assistance and safety systems, and developments towards autonomous vehicles were the main technology drivers in automotive electronics, with emphasis on reliability, miniaturisation and digitalisation. To put a perspective on connectivity requirements, Intel had estimated that an autonomous car would generate about 4000Gb of data every 24 hours.

Helminen suggested that candidates for the next generation of PCB technology solutions would include substrate integrated waveguides, innovative flexible and cable interconnect applications, innovative material solutions and innovative process technologies using automation and robotics, with overall cost savings being a prime objective.

EIPC Vice Chairman Emma Hudson from UL moderated the second technical session, with reliability as the theme.

Jean-Paul Birraux, sales and marketing manager with First EIE in Switzerland, discussed developments in panel and roll-to-roll automatic optical inspection and automatic visual inspection for PCBs and components. He began by reviewing First EIE’s product range, which included photoplotters—for which there was still a strong market, UV direct imaging, automatic optical and visual inspection systems, and inkjet printers. The trend was towards larger-format machines. First EIE’s direct imaging technology was based on single-head DMD principles with a collimated arc lamp UV source, giving full-spectrum 360 to 450 nm output.

A merger in 2015 with the Japanese company Inspec, who had long-term experience in AOI and AVI for packaging and components, established a synergy that enabled the development of a new generation of automatic visual inspection systems for PCB inspection. A unique feature was the capability to create a master reference image from a single sample, and to inspect both sides of a 240 mm x 240 mm circuit in a third of the time taken by a human inspector, capturing defects to the 20 micron level. A current project integrated First EIE’s latest EDI imager and two Inspec AVI systems in-line with developing and etching to enable continuous roll-to-roll processing, with resist inspection after developing and pattern inspection after etching.

Graham Naisbitt, managing director of Gen3 Systems and active member of several IPC, IEC and BSI standards committees, discussed the limitations of traditional ionic contamination testing of PCBs and assemblies, and described a new approach which aimed to use the dissolvable ionic material as a process indicator rather than as a cleanliness measurement that could give misleading results and fail reliable product. A recent paper published by Robert Bosch and Gen3 Systems had demonstrated the validity of the process monitoring approach, which had shown good reproducibility across a number of sites world-wide. Standardisation activities were in progress in IEC and IPC that reflected this change in approach. Naisbitt was heading the team leading the development of IEC 61189-5-504, a test method designed to monitor the soluble ionic residues present upon a test sample that could be a circuit board, an electronic component or an assembly. The conductivity of the solution used to dissolve the ionic residues was measured to evaluate the level of ionic residues, and process control was achieved by reproducing previous set limits of measured ionic material for any given test piece. The test was of short duration, 15 minutes, and run at room temperature.

Field Application Engineer Julie Ellis of TTM sees it all: good designs, bad designs, and everything in between. Her classes on proper DFM techniques are always a big draw. She taught at the inaugural AltiumLive in 2017 and was back at this year’s event. I caught up with Julie and asked her to discuss some of the things she covered in class. As she points out, many issues could be eliminated if designers communicated with their fabricators and had a better understanding of how PCBs are manufactured.

PCB designers working with flex or rigid-flex technology face many potential risks that can derail a project and cause costly design failures. As the name implies, flex and rigid-flex designs comprise a combination of rigid and flexible board technologies made up of multiple layers of flexible circuit substrates, attached internally and/or externally to one or more rigid boards. These combinations provide flexibility for the PCB designer working on dense designs that require a specific form factor. Rigid-flex allows the PCB design team to cost-efficiently apply greater functionality to a smaller volume of space, while providing the mechanical stability required by most applications.

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Part 2: EIPC’s 2018 Winter Conference in Lyon, Review of Day 1

Editor's Note: If you missed the beginning of this article click here.

Tamara den Daas-Wijnen, OEM Global Account Manager with Ventec International Group, discussed ultra-low Dk laminates for low-loss designs. She began by commenting that it was common for designers of high frequency PCBs to be concerned primarily with the loss tangent (Df) of a laminate, without considering it in combination with its dielectric constant (Dk), whereas the two properties were inseparable. She emphasised the importance of understanding the “impedance triangle,” a simple graphical representation demonstrating that for a given Dk and Df, the closer the controlled impedance conductor to the reference plane, the narrower it became. The consequence was that thinner layers required finer traces, which could lead to reduced yield in manufacture. Skin effect was also a significant contributor to signal losses and was more pronounced the finer the conductor. Hence it was desirable to keep conductors as wide as possible. She demonstrated that by decreasing the Dk, but maintaining the impedance, the track width could be increased and hence the trace resistance lowered.

Ventec had developed and qualified a cost-effective family of ultra-low Dk materials with enhanced insertion loss performance, based on a reacted polyphenylene oxide/PTFE/hydrocarbon resin chemistry which could be processed on a standard FR-4 line. Current trace widths could be maintained with smaller layer-to-layer separation, therefore Z-axis packaging density could be increased whilst maintaining or increasing trace width and giving the option of more layers for a given PCB thickness.

Stig Källman, global component engineer for PCB with Ericsson, described a PCB material toolbox to support today’s 3G and 4G networks and future high speed needs in 5G, in the most cost-effective and environmental way. He used the analogy of a Big Mac to illustrate the concept: “With the right recipe the taste is the same wherever you go…”

With the objective of standardization, he discussed the material constituents of laminate: glass, glass weave, copper and resin. It was his philosophy to know the impact of the prepreg, the impact of copper and the impact of process tolerances before considering suitable resin systems and selecting material suppliers. The first objective was to be cost-effective, using cost-efficient layer stack-ups and via structures, knowing manufacturing variation to avoid over-design, and achieving high manufacturing panel utilization.

He listed and detailed the recognized PCB technology drivers: smaller, faster, warmer, energy efficiency and environmental acceptability, and discussed the properties and needs of current halogen-free PCB materials covering the spectrum from standard FR-4.1 to microwave. For the future, the actual Df value of a material would be less significant than being able to hold that value steady over a range of temperatures. And dimensional stability would be increasingly important. He commented that the figures quoted on laminate suppliers’ data sheets were becoming more reliable. For the future, standardisation of copper surface roughness was urgently required, with classification in three levels of Ra being suggested. Materials needed to be UL-qualified to higher maximum operating temperatures, and design constraints should be introduced in minimum hole-wall to hole-wall distances to avoid CAF effects.

With regard to 5G, Källman showed videos demonstrating that 5G was becoming a reality, and Ericsson had already established a global 5G access and transport portfolio, with many additional hardware and software products in development.

Erkko Helminen, advanced development senior manager in corporate technology at TTM Technologies, gave a PCB fabricator’s perspective on the effects of 5G as a driver of PCB technology and processes.

The key feature of the next generation cellular network was 5G New Radio (NR), the global standard for a new air interface based on orthogonal frequency-division multiplexing (OFDM), designed to support the wide variation of 5G device-types. 5G NR technology development was already in progress, with emphasis on data rate, bandwidth, latency and energy saving. With frequencies trending from sub-6GHz towards 100GHz, multiple-input multiple-output mobile antenna design and fabrication became a challenge, with etching and registration accuracy being critical and innovative processes such as laser structuring being possible alternatives, and improvements in current millimetre-wave substrates being sought.

In ICT, the key next-generation PCB technology drivers were signal integrity, radio-frequency engineering and component miniaturization, and tighter and tighter tolerances would inevitably be demanded. HDI provided advantages in RF and high-speed PCBs.

Smartphone evolution was characterised by the increasing complexity of the advanced semiconductor package technology, antenna integration and placement, and the expansion of battery capacity. Consequently, the PCB was being forced into smaller spaces, with miniaturisation achieved by a shift from 100 micron subtractive-technology HDI, through 50 micron any-layer, towards 15 micron SLP and mSAT.

Driver assistance and safety systems, and developments towards autonomous vehicles were the main technology drivers in automotive electronics, with emphasis on reliability, miniaturisation and digitalisation. To put a perspective on connectivity requirements, Intel had estimated that an autonomous car would generate about 4000Gb of data every 24 hours.

Helminen suggested that candidates for the next generation of PCB technology solutions would include substrate integrated waveguides, innovative flexible and cable interconnect applications, innovative material solutions and innovative process technologies using automation and robotics, with overall cost savings being a prime objective.

EIPC Vice Chairman Emma Hudson from UL moderated the second technical session, with reliability as the theme.

Jean-Paul Birraux, sales and marketing manager with First EIE in Switzerland, discussed developments in panel and roll-to-roll automatic optical inspection and automatic visual inspection for PCBs and components. He began by reviewing First EIE’s product range, which included photoplotters—for which there was still a strong market, UV direct imaging, automatic optical and visual inspection systems, and inkjet printers. The trend was towards larger-format machines. First EIE’s direct imaging technology was based on single-head DMD principles with a collimated arc lamp UV source, giving full-spectrum 360 to 450 nm output.

A merger in 2015 with the Japanese company Inspec, who had long-term experience in AOI and AVI for packaging and components, established a synergy that enabled the development of a new generation of automatic visual inspection systems for PCB inspection. A unique feature was the capability to create a master reference image from a single sample, and to inspect both sides of a 240 mm x 240 mm circuit in a third of the time taken by a human inspector, capturing defects to the 20 micron level. A current project integrated First EIE’s latest EDI imager and two Inspec AVI systems in-line with developing and etching to enable continuous roll-to-roll processing, with resist inspection after developing and pattern inspection after etching.

Graham Naisbitt, managing director of Gen3 Systems and active member of several IPC, IEC and BSI standards committees, discussed the limitations of traditional ionic contamination testing of PCBs and assemblies, and described a new approach which aimed to use the dissolvable ionic material as a process indicator rather than as a cleanliness measurement that could give misleading results and fail reliable product. A recent paper published by Robert Bosch and Gen3 Systems had demonstrated the validity of the process monitoring approach, which had shown good reproducibility across a number of sites world-wide. Standardisation activities were in progress in IEC and IPC that reflected this change in approach. Naisbitt was heading the team leading the development of IEC 61189-5-504, a test method designed to monitor the soluble ionic residues present upon a test sample that could be a circuit board, an electronic component or an assembly. The conductivity of the solution used to dissolve the ionic residues was measured to evaluate the level of ionic residues, and process control was achieved by reproducing previous set limits of measured ionic material for any given test piece. The test was of short duration, 15 minutes, and run at room temperature.

Naisbitt gave details of a case study in which the testing procedure, known as PICT, had been optimised and used to demonstrate its advantages over established test protocols in achieving six-sigma criteria in the manufacture of electronic control units. And this could be reproduced at different manufacturing sites around the world. The PICT test was complementary to material/design element release based on SIR measurements, applying an IPC B52 approach.

Bill Birch, president of PWB Interconnect Solutions, reported the results of a three-year study within the HDP User Group Multi-lam project, to determine the reliability of multiple level microvia structures following exposure to lead-free assembly.

The Multi-lam project focused on “Type III” HDI designs, characterised by stacked microvias placed either on top of buried vias or offset to the buried vias. The terms “stack-on” and “stack-offset” were used to identify the two design variants. OEM data had shown that some stacked structures could be built reliably, but it was necessary to determine what combination of structures, materials and other parameters would result in acceptable reliability. Interconnect stress testing (IST) was carried out on a variety of stack-on and stack-offset designs, on builds with a range of finished thicknesses, materials with a range of z-axis CTE, and various BGA pitches, giving 27 possible constructions and 11 million microvias. Each of the test vehicles was pre-conditioned through 6 x 260°C reflow cycles before IST, in a design-of-experiment exercise.

The stack-on designs showed a higher incidence of failure than the stack-offset designs, and the principal failure mechanism was identified as pulling-off the cap of the buried via. The recommendation was to avoid stack-on designs.

In a related study, investigating failure modes associated with back-drilling, it had been observed that back-drilled holes failed on IST before full plated-through holes, and shallow back-drilled holes were less reliable than deep back-drilled holes. It had been shown that the failures occurred within the foil at the must-not-cut layer as a result of shear stresses within the hole when there was no knee of plated copper to balance the z-axis thermal expansion. The recommendation was to avoid shallow back-drilling unless representative testing had been carried out to qualify it on a particular design.

To the delight of those familiar with his tendency to over-run, Bill Birch was applauded for concluding his presentation within the allotted time slot!

There followed three short presentations from Alstom, which provided a company background and an insight into safety standards and quality and reliability requirements in preparation for the workshop and laboratory tour.

Jose Taborda described the electronic requirements for global railways and gave an overview of the range of products and services offered by Alstom world-wide. The company had sales of 7.3 Bn euro in 2016-17 and a current order book of 10 Bn euro. Its business strategy was to remain a customer-focused organisation with a complete range of transport solutions, creating value through innovation, based on principles of operational and environmental excellence, with diverse and entrepreneurial people. The company’s vision was to become the preferred partner for transport solutions.

Dr. Eric D’Almeida gave a summary of the constraints, standards and regulations that apply to railways. The applicable standards were EN50155 for on-board electronics, EN50125 for wayside electronics and EN5012x for safety requirements. In general, customer specifications were more stringent than railway standards. Electronics were required to operate in harsh environments, with ambient temperatures of -40°C to +85°C and board temperatures up to and exceeding 100°C, up to 95% RH with possible condensation, and saline conditions in marine environments, as well as having to withstand vibration and shock. A useful life of 20 years was required, together with the ability to withstand multiple repair operations. Key requirements were reliability and safety, and the reliability requirement fell into the high-performance category, close to that of aerospace and defence.

Thomas Boutaric continued the discussion of quality and reliability, with specific reference to printed circuit boards and assemblies. The minimum specification for PCBs was IPC-A-600 Class 2, and for assemblies IPC-A-610 Class 3, and they all required qualification for technology, materials and manufacturing processes. Various ageing tests were used by Alstom to demonstrate performance and ageing characteristics: thermal cycling, vibration and shock, salt mist, SIR, damp heat and cyclic damp heat. Many processes for PCB and PCBA manufacturing were special processes, requiring to be qualified, monitored and kept under control, whether within Alstom or at its suppliers.

After a full first-day programme of sixteen excellent presentations, delegates were grateful for the opportunity to leave their conference-room chairs and walk for a while. Dressed in white gowns and shoe covers and equipped with personal audio sets, the party was split into four groups, each with a knowledgeable Alstom guide, and shown round an impressive surface-mount assembly and test shop. Certain train-spotters in the party, hoping for a glimpse of rolling-stock in manufacture, were disappointed—the heavy engineering and vehicle-building operations are carried out elsewhere! This site was focused on the design, manufacture and test of traffic management, security and information systems for the railways.

Test room for electromagnetic compatibility

Vibration testing

SMT assembly line

For the most part, the shop was concerned with high-mix, small batch work, although a couple of long-running jobs were included to maintain continuity of operation. There was a full surface-mount line with two new pick-and-place machines with 25,000 components per hour capacity, a reflow oven, AOI and X-ray inspection, and a wave-solder line for manually inserted components. Alstom continued to use tin-lead solder. After 24-hours static burn-in, each completed assembly was ICT tested using bed-of-nails for long-running designs and flying-probe for prototypes. After testing, all assemblies were coated with a silicone conformal coating, applied manually. Every operation was recorded in a manufacturing control system. Every assembly was comprehensively labelled before being placed in storage or integrated into a rack to form a complete system, which was then subjected to burn-in and full functional test.

In a separate area delegates were shown Alstom’s global qualification and environmental testing laboratories, where all new designs were tested to a higher level than in production, and sample production assemblies were subjected to periodic re-qualification. The environmental testing included temperature cycling, shock and vibration, and electromagnetic compatibility. Railway devices operate in temperatures of -25°C to +70°C, and as low as -40°C in Russia! Alstom’s climatic laboratory was equipped with 10 chambers, each with a 1 metre cube capacity, and the facility to operate at -50°C to +130°C, with damp heat and salt spray as options.

It was well into the evening when delegates thanked their guides, peeled off their protective clothing and clambered wearily onto the buses that brought them back downtown to the internationally-famous Brasserie Georges for a magnificent conference dinner—a convivial opportunity for relaxing and networking.

Conference dinner

A few of the old and boring (the writer for example) retired to bed soon after dinner; others continued to make the most of the networking opportunity in the hotel bar, although the writer is reliably informed that the party dispersed at a reasonable hour!