The TSC80C31/80C51 is high performance SCMOS versions of the 8051 NMOS single chip 8 bit µC. The fully static design of the TSC80C31/80C51 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The TSC80C31/80C51 retains all the features of the 4 K bytes of ROM ; 128 bytes of RAM ; 32 I/O lines ; two 16 bit timers 5-source, 2-level interrupt structure ; a full duplex serial port ; and on-chip oscillator and clock circuits. In addition, the TSC80C31/80C51 has two software-selectable modes of reduced activity for further reduction in power consumption. In the Idle Mode the CPU is frozen while the RAM, the timers, the serial port, and the interrupt system continue to function. In the Power Down Mode the RAM is saved and all other functions are inoperative. The TSC80C31/80C51 is manufactured using SCMOS process which allows them to run from to 44 MHz with VCC 5 V. The TSC80C31/80C51 is also available at 20 MHz with V < Vcc 5.5 V.