There are several things that can contribute to elevated noise/distortion in High Speed ADC Applications. Assuming you have followed the High Speed ADC PCB layout best practices guidance provided at http://www.analog.com/en/search.html?q=High+Speed+ADC+Layout you may also want to consider the frequency characteristics of your Analog Input Source, and whether it is rated to drive a direct 0.1uF capacitance without additional buffering. In your schematic C3 serves to block the default DC bias coming from your source signal which allows the AC coupled input to assume the fixed 2.5V internal common mode of the AD9051 Analog Input (see Analog Input topic on d/s page 9). You also need to make sure your ADC CLK source is clean/low jitter to insure your analog input is being sampled correctly.