Hsinchu, Taiwan and Sunnyvale, California -- Nov. 5, 2013 -- Faraday Technology Corporation (TAIEX: 3035), the leading fabless ASIC/SoC and IP provider, today announced the availability of two integrated MIPI IP solutions, the Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) IP solutions in UMC’s 40nm LP and 55nm SP process technologies. As an active contributor of MIPI Alliance, Faraday has built in-house capability to guarantee the full compliance to MIPI specifications through proven silicon and the system compatibility to most MIPI compliant devices in the market.

Supporting up to 1.5 Gbps on each of the 4 data lanes, Faraday’s D-PHY complies with MIPI D-PHY specification version 1.1. To provide ASIC designers a robust and low risk solution, Faraday’s silicon-proven D-PHY analog IP integrates PLL, LDO, ESD cell and IO Pads to ensure the integrity of high speed signals and the protection of ESD. To unleash the power of pre-silicon system verification, Faraday also provides a MIPI verification platform, which integrates a FPGA with DSI or CSI-2 controller IP and a D-PHY test chip. The designers thus can conduct system-level verification in pre-silicon stage and shorten the design and development cycle time.

Faraday’s solution has been adopted by the customer in multimedia field, and enabled a quicker tape-out than the customer expected.

High-speed transmission interface is one of Faraday's core competences,” said Jason Hong, RD Vice President at Faraday. “Since launched, Faraday has always equipped our customers with the most enchanting IO solutions in terms of readiness, compliance performance, and cost, such as USB, SATA, Ethernet, LVDS, and PCIe, etc. This advantage stands out among ASIC peers, and can fully address customers’ requirement. By further adding the most integrated and silicon proven MIPI solution, Faraday has been poised for playing an even more important role in the product chain, and the hot market of mobile devices.

To cater for the escalating market demand, Faraday has an aggressive and clear roadmap ahead. Following the readiness of MIPI IP portfolio in 40nm LP and 55nm SP process, the advance process and next generation IPs are under development and are expected to create more market successes soon.

In the upcoming ET Japan event (Embedded Technology, Nov.20-22th), Faraday will demo the MIPI success case from the customer. Welcome to visit and learn more details then.

About Faraday MIPI

Faraday’s MIPI CSI-2 Solution

Available in both Transmit and Receive Controllers

Support the high resolution and multiple-camera applications in smart phone, tablet and image signal processor (ISP) with silicon proven D-PHY

Support a sleuth of resolutions and pixel formats in mobile and portable market, including the 4K resolution