SYSTEM FOR TESTING CONCEALED CONDUITS - A system for testing concealed ducts including a pull cable and a transmitter, the transmitter including a transmission means for emitting radiation disposed at one end of the pull cable and at least one electric wire disposed inside the pull cable, wherein the electric wire or wires enables electrical connection between the transmitter and the transmission means, and a receiver for receiving signals from the transmission means and for indicating strength of the received signals. The scope of the invention includes methods of finding blockage within a conduit pipe and finding the path of a conduit pipe, built into a partition, by inserting a pull cable into a conduit pipe and detecting the location of the front end of the pull cable.

2009-02-19

20090045809

Magnetic sensor and manufacturing method of the same - To provide a magnetic sensor that can be reduced in size and cost. Provided is a magnetic sensor which comprises: a magnetic field detection chip having a magnetic field detection element for detecting a magnetic field and an output terminal for outputting an output signal from the magnetic field detection element; and a substrate that has the magnetic field detection chip mounted thereon, and has a connection terminal for being connected to the output terminal of the magnetic field detection chip that is formed on a mount face of the substrate. An output-terminal formed face of the magnetic field detection chip is arranged not to be in parallel to the mount face of the substrate. More specifically, the output-terminal formed face of the magnetic field detection chip is arranged almost vertical to the mount face of the substrate.

2009-02-19

20090045810

MAGNETIC DETECTING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A magnetic detecting device includes a first and a second magnetoresistive element, and a first and a second fixed resistor connected in series to the first and the second magnetoresistive element, respectively. The first and the second magnetoresistive element each include a pinned magnetic layer and a free magnetic layer with a nonmagnetic conductive layer in between. The first and the second magnetoresistive element have the same layer structure except that the nonmagnetic conductive layers have different thicknesses. The thicknesses of the nonmagnetic conductive layers are set so that a positive interlayer coupling magnetic field acts between the free magnetic layer and the pinned magnetic layer of the first magnetoresistive element and a negative interlayer coupling magnetic field acts between the free magnetic layer and the pinned magnetic layer of the second magnetoresistive element. The first and the second fixed resistor have the same layer structure.

2009-02-19

20090045811

NOVEL METHOD FOR SEQUENCE DETERMINATION USING NMR - The invention relates to methods for analyzing polysaccharides. In particular, compositional and sequence information about the polysaccharides are derived. Some methods use NMR in conjunction with another experimental method, such as, capillary electrophoretic techniques for the analysis.

2009-02-19

20090045812

Method of Operation for a Magnetic Resonance Imaging Suite - A method of operation for a magnetic resonance imaging suite. A power supply of magnetic resonance injector system receives electrical power from an AC power outlet, both of which are located outside of a shielded room of the magnetic resonance imaging suite. Electrical power from the power supply of the magnetic resonance injector system is conveyed (via an appropriate power connection) into the shielded room of the magnetic resonance imaging suite and to a component (e.g., a power head) of the magnetic resonance injector system located inside the shielded room. While this electrical power is being conveyed, radio frequency energy emitted from the power connection is being filtered.

2009-02-19

20090045813

Resonant pulse induction metal detector - A metal detector transmitting high current pulses and employing the high voltage back EMF signals which occur at their termination. The method employed uses a resonant tuned receive coil which provides a major improvement in the depth of detection of metallic objects and interference rejection over current time and frequency domain metal detectors.

2009-02-19

20090045814

HIGH TEMPERATURE DOWNHOLE TOOL - Apparatus and method for estimating a downhole parameter include a high-gain semiconductor device having a plurality of semiconductor layers forming an active region, the active region having a bandgap offset that provides device operation through at least the temperature environment of a downhole location, the high-gain semiconductor device being used at least in part to estimate a downhole parameter.

ELECTROMETER WITH IN-MEASUREMENT RANGE ADJUSTMENT AND METHODS THEREOF FOR MEASURING ELECTROSTATIC CHARGE - An electrometer is disclosed. The electrometer has a high gain differential amplifier having a first input, a second input, and an output. The electrometer also has feedback switching circuitry. The electrometer further has a plurality of feedback elements configured to be selectively and cumulatively added in any parallel combination between the output and the first input of the high gain differential amplifier via the feedback switching circuitry. A method of adjusting a measurement range of an electrometer while the electrometer is being used to measure an electrostatic charge is also disclosed. One or more additional feedback elements are selectively added in parallel with one or more existing feedback elements which are coupled between an output and an input of a high gain differential amplifier of the electrometer.

2009-02-19

20090045817

ELECTRICAL TESTING DEVICE - The present invention is directed to an electrical testing device for use in an AC electrical power distribution circuit including a plurality of AC electric power transmitting wires coupled between an AC power distribution point and a device box. The device includes a plurality of electrical probes configured for insertion into an outlet receptacle. A plug test connection arrangement is configured to receive a plug connector when inserted therein. The plug connector includes a plurality of plug contacts and a termination arrangement configured to terminate the plurality of AC electric power transmitting wires such that electrical continuity is established between the AC power distribution point and the plurality of plug contacts. The plug test connection arrangement includes a plurality of test contacts configured to mate with the plurality of plug contacts when the plug connector is inserted into the plug test connection arrangement. The termination arrangement being in a detached relationship from the device box after the plurality of AC electric power transmitting wires are terminated. An electrical test circuit is configured to perform at least one electrical test. The electrical test circuit includes a switch mechanism configured to connect the electrical test circuit to the plurality of electrical probes at a first switch setting or connect the electrical test circuit to the plurality of test contacts at a second switch setting. At least one shock mitigation structure is coupled to the plurality of electrical probes or the plug test connection arrangement and is configured to prevent user access to the plurality of electrical probes or the plug test connection arrangement.

2009-02-19

20090045818

POWER-OVER-ETHERNET ISOLATION LOSS DETECTOR - An AC generator has a first terminal coupled through an Isolation Loss Detect (ILD) capacitor to the positive bus of a Power-Over-Ethernet (POE) system, and has a second terminal coupled through the primary of a transformer to earth ground. AC current flowing between earth ground and the positive bus causes a corresponding AC voltage to be developed across the secondary of this transformer. The secondary of the transformer is coupled to an AC detector, the output of which is coupled to a comparator. The threshold of the comparator is set such that when AC current flow through the ILD capacitor exceeds a value set by this threshold, an ISOLATION FAULT output is generated at the output of the comparator. In normal operation, isolation between earth ground and any conductor in the POE system coupled to the positive bus is high, so little or no AC current flows through the ILD capacitor. When an isolation loss occurs such as a short circuit between earth ground and any conductor in the POE system coupled to the positive bus, the AC current in the ILD capacitor and transformer increase significantly, causing the output of the AC detector to exceed the threshold of the comparator, and causing an ISOLATION FAULT output. A high level of galvanic isolation is maintained even with the added ILD circuit because the DC leakage current of the ILD capacitor is negligible. In an embodiment wherein distributed bypass capacitance exists from the positive and negative buses to earth ground, the known nominal AC current caused to flow in the ILD capacitor by this distributed capacitance allows a self-check function of the ILD system. A second comparator is coupled to the output of the AC detector, and a second threshold is set which is above zero but below the voltage caused by this nominal AC current flow. If the AC generator or AC detector fails, causing the detector output to drop significantly, this second comparator changes state to show a failure of the ILD circuit.

TACTILE SENSOR UTILIZING MICROCOILS WITH SPIRAL SHAPE - Provided is a material for tactile sensor, which is easy to be formed, and in which the shape, size and orientation of coils dispersed in the medium are sufficiently controlled. The tactile-sensitive material comprises a medium and a plurality of micro coils dispersed in the medium and constituting a LCR resonance circuit, and wherein each of the plurality of micro coils comprises at least one spiral coil portion, and coil axes of the plurality of micro coils are aligned along at least one direction and/or directed in at least one plane. When a tactile stress is applied to the tactile-sensitive material, the C component is varied significantly, which contributes to the improvement in sensitivity of the tactile sensor. Further, by providing a core at the coil center, the sensitivity is more improved.

2009-02-19

20090045821

Capacitive sensor with alternating current power immunity - A capacitive sensor includes a sensing electro, control unit, first and second comparator wherein the sensing electro includes a first and a second conduct ports. A positive input terminal of the first comparator and a negative input terminal of the second comparator are coupled to the first conduct port. A positive input terminal of the second comparator and a negative input terminal of the first comparator are coupled to the second conduct port. The first and second comparators respectively output first and second comparing signals according to voltages of the positive and the negative terminals thereof. The control unit charges the first conduct port and discharges the second conduct port when the first and second comparing signals correspondingly are in first and second logic states. The control unit is operable on the contrary when the first and second comparing signals are in opposition to the abovementioned description.

2009-02-19

20090045822

Capacitive detection systems, modules and methods - Capacitive detection systems, modules, and methods. In one embodiment, time interval measurement(s) are generated that are monotonic functions of the capacitance(s) of capacitive sensor(s) in a capacitive sensing area. In one embodiment, the generated time interval measurement(s), or any other monotonic function(s) of capacitance(s) of capacitive sensor(s) in a capacitive sensing area, may be analyzed to detect the presence of an object near the capacitive sensing area and/or to detect the position of an object near the capacitive sensing area.

2009-02-19

20090045823

Power efficient capacitive detection - Capacitive detection systems, modules, and methods. In one embodiment, a power saving mode is implemented when deemed appropriate, based on an analysis of previous detection or non-detection of the presence and/or position of an object near a capacitive sensing area.

SYSTEMS AND METHODS FOR AN OPEN CIRCUIT CURRENT LIMITER - A resistance measuring circuit includes a current generating component, a current control component, and a voltage measurement component. The magnitude of a target resistance can be measured by connecting the target resistance between first and second measurement terminals of the resistance measuring circuit, applying a current generated by the current generating component to the target resistance, and determining the voltage across the target resistance. When no target resistance is connected between the first and second measurement terminals, the current control component controls the current generating component to reduce current consumption of the resistance measuring circuit.

Multi-Site Probe - Various probe substrates for probing a semiconductor die and methods of use thereof are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first matrix array of conductor pins and a second matrix array of conductor pins on a probe substrate. The second matrix array of conductor pins is separated from the first matrix array of conductor pins by a first pitch along a first axis selected to substantially match a second pitch between a first semiconductor die and a second semiconductor die of a semiconductor workpiece.

2009-02-19

20090045828

Fine Pitch Testing Substrate Structure And Method Of Manufacturing The Same - The present invention provides a newly designed testing substrate for solving the problem with respect to fine pitches, and a method of manufacturing the testing substrate. The wiring space within the fine pitch can be enlarged by means of a circuit design with through holes, blind vias and stack vias, in association with process technologies for fine lines, blind vias, buried vias and filling vias. The manufactured testing substrate comprises a resting substrate and a probe base, being applicable to the test for IC's or packaged articles.

2009-02-19

20090045829

Wafer holder for wafer prober and wafer prober equipped with same - It is an object of the present invention to provide a wafer prober wafer holder that is highly rigid and increases the heat insulating effect, thereby improving positional accuracy, thermal uniformity, and chip temperature ramp-up and cooling rates, as well as a wafer prober device equipped therewith.

2009-02-19

20090045830

AUTOMATED CONTACT ALIGNMENT TOOL - A method for determining the alignment of a plurality of contacts in an electronic testing machine is disclosed. The contacts are swept over an electronic component taking a plurality of electrical readings. These electrical readings are charted against a desired orientation to determine alignment. Alignment can be corrected as necessary using an adjustment mechanism.

2009-02-19

20090045831

CONTACT WITH PLURAL BEAMS - To precisely control behavior of a probe at a portion near a contact, and to provide a probe with small electric capacity which can be used to inspect chips having high-speed and high-capacity signals. A parallel spring probe based on a principle of a link mechanism, the link mechanism including: a vertically extending vertical probe; and a plurality of linear or curved horizontal beams extending in a direction perpendicular to the vertical direction, the beams being fastened to a fixed end at one ends and connected to the vertical probe at the other ends, characterized in that distance between at least a pair of adjacent horizontal beams varies along a direction perpendicular to the vertical direction.

SEMICONDUCTOR DEVICE - A first power-cutoff switch is disposed between a power line and an internal power line dedicated for a circuit block, and has a current supply capacity having the level at which ON-current can protect an external examination environment. A second power-cutoff switch is disposed between a power line and an internal power line, and has a current supply capacity having the level at which ON-current can supply consumed current of the circuit block. A detecting circuit detects that a voltage of the internal power line matches a reference voltage. The first power-cutoff switch is ON/OFF by an operation state of the circuit block. The second power-cutoff switch is ON by detecting the matching of the volumes with the detecting circuit and is OFF by the ON/OFF operation of the first power-cutoff switch.

2009-02-19

20090045834

Digital circuits with adaptive resistance to single event upset - A digital circuit with adaptive resistance to single event upset. A novel transient filter is placed within the feedback loop of each latch in the digital circuit to reject pulses having a width less than T, where T is the longest anticipated duration of transients. The transient filter includes a first logic element having a controllable inertial delay and a second logic element coupled to an output of the first logic element. A first controller provides a control voltage VcR to each first logic element to control a rise time of the first logic element to be equal to T. A second controller provides a control voltage VcF to each first logic element to control a fall time of the first logic element to be equal to T.

2009-02-19

20090045835

Signal output circuit, optical pickup and optical device - Disclosed herein is a signal output circuit for outputting a signal onto a transmission line having a given transmission characteristic, the signal output circuit including a drive circuit adapted to drive an input signal by a current; and an output resistor which is connected to an output stage of the drive circuit and capable of adjusting the output signal waveform according to its resistance, wherein the drive current of the drive circuit and the resistance of the output resistor are variable.

APPARATUS FOR DYNAMIC DEPLOYMENT OF PIN FUNCTIONS ON A CHIP - An apparatus for dynamic deployment of pin functions on a chip is disclosed in the present invention. The apparatus comprises: an input pin receiving unit, capable of integrating a plurality of pins and selecting pin functions according to a program; an output pin control unit, capable of issuing a control signal to the plurality of pins; and a signal control unit, controlled by the program and coupled to the input pin receiving unit and the output pin control unit so as to communicate therebetween; wherein the pin functions are designated by the user to select an output signal for each of the plurality of pins according to the program.

2009-02-19

20090045838

INTEGRATED CIRCUIT APPARATUS - An integrated circuit apparatus includes a reconfigurable arithmetic operation device and a control device that generates mapping data defining a circuit configuration of the reconfigurable arithmetic operation device whose circuit configuration is changed while a given application is running and another application is newly implemented and run. The control device generates mapping data defining an intermediate configuration to shift from a circuit configuration defined by first mapping data to a configuration defined by final mapping data through the intermediate configuration.

2009-02-19

20090045839

ASIC LOGIC LIBRARY OF FLEXIBLE LOGIC BLOCKS AND METHOD TO ENABLE ENGINEERING CHANGE - A chip design methodology and an integrated circuit chip. The methodology includes providing a plurality of logic gates in a net list, wherein each of the logic gates comprises at least one spare input, synthesizing the net list, and connecting the spare inputs for performing an engineering change late in the design process. The invention is also directed to a design structure on which a circuit resides.

2009-02-19

20090045840

Method for Radiation Tolerance by Logic Book Folding - A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing transistors of the same doping type in different well regions that are physically isolated by intervening well regions with complementary doping. For example, n-type field effect transistors (NFETs) may be located in two outer rows of the book with separate Pwell regions, while p-type transistors are located in two inner rows of the book sharing a common Nwell region. Since the NFETs in separate wells are physically isolated from each other, a circuit structure which uses two NFETs in the two outer rows is much less likely to suffer multiple upsets from a single radiation strike. More complicated embodiments of the present invention include additional transistor rows in the stack with isolated Nwells and Pwells.

2009-02-19

20090045841

Method for Radiation Tolerance by Implant Well Notching - A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing notches in an implant well between adjacent transistors and fills the notches with complementary well regions that act as a barrier to charge migration. For example, a row of n-type field effect transistors (NFETs) is located in a Pwell region, while a row of p-type transistors is located in an Nwell region with portions of the Nwell region extending between the NFETs. More complicated embodiments of the present invention include embedded well islands to provide barriers for adjacent transistors in both rows of the book.

2009-02-19

20090045842

LOW-DELAY COMPLIMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) TO EMITTER-COUPLED LOGIC (ECL) CONVERTERS, METHODS AND APPARATUS - Example low-delay complementary metal-oxide semiconductor (CMOS) to emitter-coupled logic (ECL) converters, methods and apparatus are disclosed. A disclosed example apparatus includes a reference level generator circuit to generate first and second reference signals and a bias signal based on a CMOS supply voltage, a source follower circuit to convert a CMOS input signal to a single-ended ECL signal based on the first and second reference signals, and an ECL buffer circuit to convert the single-ended ECL signal to a differential ECL output signal based on the bias signal and an ECL supply voltage.

2009-02-19

20090045843

LEVEL SHIFTER CIRCUIT WITH PRE-CHARGE/PRE-DISCHARGE - A level shifter circuit and method of operating therefor. The level shifter circuit is coupled to receive a data signal via an input circuit, wherein the input circuit is in a first voltage domain. The level shifter circuit is also coupled to receive a clock signal from a second voltage domain. On a first portion of the clock cycle, true and complementary output nodes of the level shifter circuit (which are in the second voltage domain) are pulled to a first voltage by activation of respective pull transistors. On a second portion of the clock cycle, one of the true or complementary output nodes is pulled to a second voltage on a second voltage node by enabling the supply to the latch. Data is captured by the keeper, outputting true and complementary versions of the data signal in the second phase of the clock.

2009-02-19

20090045844

LEVEL SHIFTER AND SEMICONDUCTOR DEVICE HAVING OFF-CHIP DRIVER - Provided are a level shifter and a semiconductor device having an OFF-chip driver (OCD) using the same. The level shifter includes a plurality of series connected logic gates receiving a first-state input signal having a first power supply voltage level and generating a level-shifted first-state output signal having a second power supply voltage level. The logic gates receive as power supply voltages at least one intermediate power supply voltage having at least one voltage level intermediate between the first power supply voltage level and the second power supply voltage level, and an intermediate power supply voltage applied to the present logic gate is equal to or higher than an intermediate power supply voltage applied to the previous logic gate.

2009-02-19

20090045845

Adjusting Output Buffer Timing Based on Drive Strength - This invention operates to select a drive code for an adjustable drive strength transistor in a drive buffer. The drive code is determined employing a scaled-down drive transistor employing varying drive codes compared with a standard. The thus determined drive code is combined with an offset to generate the drive code for the adjustable strength transistor.

2009-02-19

20090045846

ADVANCED REPEATER WITH DUTY CYCLE ADJUSTMENT - An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selectably adjusting a duty cycle of the signal. The advanced repeater may further include circuitry for producing a delayed version of the signal.

2009-02-19

20090045847

GENERIC FLEXIBLE TIMER DESIGN - One embodiment of the present invention sets forth a set of three building block circuits for designing a flexible timing generator for an integrated circuit. The first and second building blocks include delay elements that may be customized and fine-tuned prior to fabrication. The third building block may be tuned prior to fabrication as well as after fabrication. The three building blocks may be incorporated into a modular architecture, enabling designers to easily generate well-characterized, flexible, generic timer circuits.

2009-02-19

20090045848

PHASE-FREQUENCY DETECTOR WITH HIGH JITTER TOLERANCE - A phase-frequency detection system and method for enhancing performance of the frequency detector in a phase-frequency detection system. Filtering of the frequency detector inputs makes operation of the frequency detector more robust in the presence of intersymbol interference within the incoming data signal and other non-ideal characteristics such as noise and crosstalk.

2009-02-19

20090045849

DATA BUS SENSE AMPLIFIER CIRCUIT - A data bus sense amplifier circuit can include a first sense amplifier block configured to provide first amplified signals by sensing inputted signals, a second sense amplifier block configured to provide second amplified signals by sensing the first amplified signals, and a sense amplifier control unit configured to provide first and second enable signals which control activations of the first and second sense amplifier blocks, respectively, wherein the sense amplifier control unit controls the first enable signal to be synchronized with the second enable signal so that the first enable signal is inactivated.

2009-02-19

20090045850

RTWO-BASED DOWN CONVERTER - A multiphase mixer using a rotary traveling wave oscillator is disclosed. In addition to the oscillator, the mixer includes first and second mixer circuits. The rotary traveling wave oscillator generates a first set of N/2 phase and a second set of N/2 phases, where each phase has a frequency that is a factor of N/2 less than the incoming radio frequency signal. The first set of phases are sine signals and the second set of phases are cosine signals. The first mixer circuit generates a first down-converted signal from the first set of phases and the incoming rf signal. The second mixer circuit generates a second down-converted signal from the second set of phases and the rf signal.

TIMING CONTROLLER, DISPLAY APPARATUS HAVING THE SAME AND METHOD FOR DRIVING THE DISPLAY APPARATUS - A timing controller, a display apparatus having the timing controller and a method for driving the display apparatus, the timing controller includes a control part, an inner clock and a control signal. The control part detects whether an external clock signal and image data received from an external image apparatus are abnormal. The inner clock generating part includes a reference voltage generating circuit outputting a reference voltage independent of temperature, and generates an inner clock signal using the reference voltage. The control signal generating part generates a first driving control signal using the external clock signal and generates a second driving control signal using the inner clock signal. Accordingly, the inner clock signal that is stable with respect to the surrounding temperature and voltage variation is generated when the external clock signal and the image data are abnormal, and thus driving reliability may be enhanced.

2009-02-19

20090045854

Apparatus and Method for Controlling a Master/Slave System via Master Device Synchronization - A method of operating a master/slave system includes the step of identifying a master receive data phase value to coordinate the transfer of data from a slave device without phase alignment circuitry to a master device with a universal phase aligner. Data is transferred from the slave device to the master device in accordance with the master receive data phase value. The master device characterizes a master transmit data phase value to coordinate the transfer of data from the master device to the slave device. Subsequently, the master device routes data to the slave device in accordance with the master transmit data phase value.

2009-02-19

20090045855

APPARATUS FOR INTERFACING AND TESTING A PHASE LOCKED LOOP IN A FIELD PROGRAMMABLE GATE ARRAY - An apparatus for interfacing a phase locked loop in a field programmable gate array. The apparatus comprising a phase locked loop cluster. The phase locked loop further comprising a plurality of RT modules, a plurality of RO modules, at least one TY module, a plurality of receiver modules and at least one buffer module. A phase locked loop selectively coupled to the RT modules, the RO modules, the TY modules, the receiver modules and at least one buffer module in the phase locked loop cluster.

2009-02-19

20090045856

CLOCK SIGNAL SYNCHRONIZING DEVICE WITH INHERENT DUTY-CYCLE CORRECTION CAPABILITY - One aspect relates to a clock signal synchronizing device, in particular to a delayed locked loop (DLL) with capability to correct static duty-cycle offset and to filter clock-jitter. One aspect relates to a clock signal synchronizing method with capability to correct static duty-cycle offset and to filter clock-jitter. In accordance one aspect, there is provided a clock signal synchronizing device including a delay circuit having a variable delay time and delaying an incoming clock signal or a signal generated therefrom to output a delayed clock signal. Also included is a negator for inverting the delayed clock signal to output an inverted delayed clock signal. Also included is a delay control circuit for controlling the delay circuit to adjust the phase relation between the incoming clock signal and the inverted delayed clock signal and a phase interpolator. The phase interpolator is activated when the incoming clock signal and the inverted delayed clock signal are substantially in phase and adds the incoming clock signal multiplied with a factor of substantially (1−p) to the inverted delayed clock signal multiplied with a factor of substantially p to output a compound signal to the delay circuit, p being a real number greater than or equal to 0 and smaller than or equal to 1.

2009-02-19

20090045857

DELAY LOCKED LOOP CIRCUIT - A delay locked loop increases an operation margin of a delay locked loop by using an output clock having more advanced phase than a DLL output clock. A clock delay compensation block receives an external clock signal to thereby generate a first multi clock and a second multi clock. A phase control block compares the first multi clock with the second multi clock to generate phase control signal controlling a shifting operation. A multi-phase delay control block performs a shifting operation based on the phase control signal to control the clock delay compensation block.

2009-02-19

20090045858

DELAY LOCKED LOOP CIRCUIT - A delay locked loop (DLL) circuit for a synchronous dynamic random access memory (SDRAM) is provided. If a locking state is broken due to an external change such as a change of tCK or power supply voltage, indicating that a delay of a delay replication modeling unit involved in a DRAM is abruptly changed, the locking state can be recovered within a certain time, e.g., 200 tCK, by creating an internal reset signal in the DLL circuit by a circuit that monitors the state and then conducting a phase update using a rough delay value.

2009-02-19

20090045859

Method and system for diagnostic imaging using a digital phase locked loop - A method and apparatus are provided for minimizing output pulse jitters in a phase locked loop. The method includes pre-setting the digital phase locked loop to a desired frequency, locking the digital phase locked loop to the desired frequency to generate an output signal, and filtering the output signal of the digital phase locked loop to maintain undesirable jitter to an acceptable range. In one embodiment, the apparatus is a medical imaging device. In another embodiment, the apparatus is a baggage imaging device.

2009-02-19

20090045860

Apparatus and method for two tier output stage for switching devices - A circuit for reducing EMI is provided. The circuit includes driver circuitry that drives a power switch, such as a power MOSFET. The power switch provides an output voltage. The circuit decreases the drive strength by which the power switch is driven during each output edge (i.e. when the output goes from low to high (rising edge) or high to low (falling edge)), and returns the drive strength to its normal level when the output edge is complete or approximately complete. Reducing the drive strength of the driver circuitry causes the output edge to occur over a longer period of time. This results in reduction of the EMI of the device.

2009-02-19

20090045861

System and method for effectively implementing an IQ generator - A system and method for effectively implementing an IQ generator includes a master latch that generates an I signal and a slave latch that generates a Q signal. The master latch includes a master data circuit, a master latch circuit, and a master clock circuit. The slave latch includes a slave data circuit, a slave latch circuit, and a slave clock circuit. A cross-coupled current-source technique is used to compensate for certain device mismatches. A current source A generates an operating current A for the master clock circuit, the master data circuit, and the slave data circuit, and a current source B generates an operating current B for the slave clock circuit, the master latch, and the slave latch. In addition, resistors are utilized to provide fixed impedances to compensate for device mismatches between certain components in the master clock circuit and the slave clock circuit.

2009-02-19

20090045862

CLOCK GENERATING CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A clock generating circuit of a semiconductor memory apparatus includes a phase splitter that delays a clock to generate a delayed clock and inverts the clock to generate an inverted clock, and a clock buffer that buffers the delayed clock and the inverted clock and outputs a rising clock and a falling clock.

2009-02-19

20090045863

System and method for removal of frequency-dependent timing distortion - A method of preparing a signal for measurement includes receiving the signal and selecting a first edge and a second edge within the signal. The method also includes delivering the first edge to a time interval measurement system after expiration of a first delay period and delivering the second edge to a time interval measurement system after expiration of a second delay period.

2009-02-19

20090045864

VARIABLE DELAY CIRCUIT AND DELAY CORRECTION METHOD - A variable delay circuit is provided which has a plurality of delay elements. The variable delay circuit comprises a delay time correction circuit for individually correcting a delay time on each of the plurality of delay elements to compensate for the variation in transistor performance among the plurality of delay elements.

2009-02-19

20090045865

SQUARE-FUNCTION CIRCUIT - A square-function circuit includes an input field-effect transistor (FET) having a gate that is driven by an input voltage and is configured to conduct an output current. The circuit also includes a feedback circuit coupled to a source of the input FET, the feedback circuit being configured to drive a source of the input FET based on the output current to set a magnitude of the output current to be substantially equal to a square of the input voltage.

DOUBLE STAGE COMPACT CHARGE PUMP CIRCUIT - A charge pump circuit comprising a plurality of charge pumps each having their outputs connected in parallel, each charge pump receiving a plurality of clock signals, a clock signal oscillator for providing the plurality of clock signals, the clock signals being out of phase, each charge pump having an output (VCP) that is coupled to the output of the at least one other charge pump, further comprising a first capacitor in each charge pump, the first capacitor being charged by a switching circuit receiving the clock signals to charge the first capacitor to a voltage between a supply voltage and a reference potential, and further comprising a second capacitor coupled in series with the first capacitor, the second capacitor provided between a first terminal (IN) of the charge pump and a second terminal (OUT) of the charge pump, wherein the first terminal (IN) of the charge pump is connected to a second terminal (OUT) of another charge pump and the second terminal (OUT) of the charge pump is connected to the first terminal (IN) of another charge pump, and wherein when the first capacitor is charged by the switching circuit, the second capacitor is charged by its connection to another charge pump, the switching circuit connecting a first terminal of the first capacitor to the supply voltage thereby elevating a second terminal of the first capacitor to an elevated voltage, the second terminal of the first capacitor being connected to a first terminal of the second capacitor, and thereby elevating a second terminal of the second capacitor to a further elevated voltage elevated above the elevated voltage on the first capacitor, the further elevated voltage on the second terminal of the second capacitor being provided to the charge pump output.

Reference voltage circuit - Provided is a reference voltage circuit whose power supply rejection ratio is large even in a case where a power supply voltage is low. Even in a case where the power supply voltage of a power supply terminal (

2009-02-19

20090045871

Device for demodulating a signal containing information being conveyed by phase shift keying - The invention relates to a device for demodulating an input signal containing information being conveyed by phase modulation of a carrier wave. A transmitter generates a signal controlling a phase variation in the carrier wave, for each symbol having N cycles, N being an integer strictly greater than 1. The phase variation stretches on the receiver side over n cycles, n being an integer greater than 1 and less than N. The device generates a single pulse for each symbol received suited to generate the leading edge of the pulse corresponding to the symbol considered after a constant duration from the moment the symbol considered starts; and generates the trailing edge of the pulse considered at a moment the phase shift corresponding to the symbol considered has to be measured. Conversion means generate an output signal with a voltage varying as a function of the duration of the pulse produced.

2009-02-19

20090045872

INTEGRATED TRANSCEIVER WITH ENVELOPE TRACKING - A transceiver comprises an amplifying circuit for amplifying an input signal to produce an output signal. A power supply is operable for varying the level of power supplied to the amplifying circuit in response to variation of an input signal envelope directed to the power supply. A processing circuit is operable for digitally detecting the input signal envelope to provide variation of the power supply level. The processing circuit is further operable for digitally delaying the digital input signal envelope to time align the power supply level with the input signal.

2009-02-19

20090045873

CLOSE-LOOP CLASS-D AUDIO AMPLIFIER AND CONTROL METHOD THEREOF - The present invention discloses a Class-D power amplifier and control method thereof. In one embodiment, the amplifier feeds back the signal at the output node to the inverting input of the comparator, and provides a high frequency triangular wave signal to the non-inverting input of the comparator. In addition, the non-inverting input of the comparator may be coupled to an offset voltage, while the inverting input of the comparator may be coupled to a fixed-frequency rectangular wave signal, a feedback signal which is derived from the output stage and an input signal. In use, the switching frequency may be at least substantially fixed, so as to reduce the influence on the system caused by electromagnetic interruption (EMI). Further, the control circuit is simple, and some devices can be integrated.

2009-02-19

20090045874

DIFFERENTIAL AMPLIFIER AND INPUT CIRCUIT USING THE SAME - A differential amplifier comprises a plurality of first switching elements configured to output differentially amplified signals through output terminals when a voltage level of a first input signal and a second input signal belongs to a first range and a plurality of second switching elements configured to output the differentially amplified signals through the output terminals when the voltage level of the first input signal and the second input signal belongs to a second range.

2009-02-19

20090045875

DATA AMPLIFYING CIRCUIT CONTROLLABLE WITH SWING LEVEL ACCORDING TO OPERATION MODE AND OUTPUT DRIVER INCLUDING THE SAME - A data amplifying circuit for an output driver has a swing level that is controllable according to an operation mode. The data amplifying circuit includes a mode responding circuit supplying an additional source current to a source node of an amplifying circuit in response to a mode selection signal. The mode responding circuit controls the supply of the additional source current in accordance with an operation mode. Another data amplifying circuit of a semiconductor device, according to the invention, includes a small-swing amplifier and a full-swing amplifier. The small-swing amplifier causes a swing level of the output signal to be relatively smaller, while the full-swing amplifier causes the output signal swing level be relatively larger. The small-swing and full-swing amplifiers are alternatively enabled in response to the mode selection signal.

2009-02-19

20090045876

LOW NOISE, LOW POWER, HIGH LINEARITY DIFFERENTIAL AMPLIFIER WITH A CAPACITIVE INPUT IMPEDANCE - A low noise, low power differential two-stage amplifier includes a first stage comprising a pair of electrical devices that sense an input signal difference across the pair of electrical devices; and a control feedback loop operatively connected to the first stage, wherein the first stage in combination with the control loop feedback is adapted to place an exact copy of the signal across a first pair of resistive components, wherein the first pair of resistive components are adapted to generate a differential signal current, wherein the control feedback loop is adapted to ensure that the differential signal current goes a second pair of resistive components to generate a voltage output. Preferably, the first and second pair of resistive components are in ratio to produce the exact copy of the signal with some gain at an output of the first stage.

2009-02-19

20090045877

POWER AMPLIFIER CIRCUIT FOR MULTI-FREQUENCIES AND MULTI-MODES AND METHOD FOR OPERATING THE SAME - A multi-frequency and multi-mode power amplifier is provided. The amplifier has a carrier power amplifier and a peaking power amplifier. The carrier power amplifier receives a first signal and outputs a first amplified signal, in which a first transistor size adjusting unit is included to adjust an equivalent transistor size based on a mode indication signal. The peaking power amplifier receives a second signal and outputs a second amplified signal, in which a second transistor size adjusting unit is included to adjust an equivalent transistor size based on the mode indication signal.

2009-02-19

20090045878

Amplifier - An amplifier includes a carrier amplifier which performs signal amplification at all times, a peak amplifier which operates only at a time when the high electric power is outputted, a combiner which combines the output from the carrier amplifier and the peak amplifier, and a distributor which distributes an input signal to the carrier amplifier and the peak amplifier. The carrier amplifier and the peak amplifier are included in a single package transistor.

2009-02-19

20090045879

Amplifier and Method for Operating the Same - An amplifier includes an input terminal, an output terminal, a cascode circuit with a first and a second transistor serially coupled between an output terminal and a terminal of a predefined potential with a control terminal of the first transistor being coupled to the input terminal, a first bipolar transistor having a collector/emitter path, forming a series circuit coupled to the terminal of a predefined potential with the first transistor, a power supply circuit for providing power supply voltages over a cascode circuit and a series circuit and a second bipolar transistor coupled between the output terminal and the terminal of the predefined potential with bases of the first bipolar transistor and the second bipolar transistor being coupled to each other and a current source.

2009-02-19

20090045880

Digital Controlled Oscillator - A digital controlled oscillator including a programmable current source, a first variable capacitor and a second variable capacitor. A comparator compares the voltage across the variable capacitors with a reference voltage level and generates a DCO output clock signal. A switching means alternately switches the variable capacitors to either charge from a programmable current source or discharge in response to an output signal of the comparator. A clock divider divides the DCO output clock signal by a factor N substantially greater than 1. A frequency monitor receives the divided clock signal, determines the time difference of successive clock periods of the divided clock signal and generates a feedback signal to adapt the frequency of the DCO output clock signal.

2009-02-19

20090045881

Method And Apparatus For Calibrating A Voltage Controlled Oscillator By Varying Voltage Applied To Power Supply Input - Methods and apparatus are provided for calibrating a voltage controlled oscillator, such as an N-stage voltage controlled ring oscillator. The voltage controlled oscillator comprises a power supply input and at least one gate delay element and has a frequency that is a function of a delay of the gate delay element and a voltage applied to the power supply input. A voltage controlled oscillator is calibrated by varying an output voltage of a programmable voltage source through a range of values; applying the output voltage to the power supply input of the voltage controlled oscillator; comparing an output clock frequency of the voltage controlled oscillator to a reference frequency clock for each of the output voltage values; and selecting a value of the output voltage that provides an approximate minimum frequency difference between the output clock frequency and the reference frequency clock.

2009-02-19

20090045882

SYSTEM FOR GENERATING A MULTIPLE PHASE CLOCK - A system for generating a multiple phase clock. The system includes a ring oscillator structure for generating multiple phases. The structure includes two or more unit oscillators, each unit oscillator implemented by a ring oscillator having M stages. The structure also includes a horizontal loop coupling the two or more unit oscillators to generate multiple phases. The number of phases generated is equal to the product of the number of unit oscillators and M.

2009-02-19

20090045883

SELF REFRESH OSCILLATOR AND OSCILLATION SIGNAL GENERATION METHOD OF THE SAME - A self refresh period signal generator includes: a voltage detection unit for detecting a voltage level of a power supply voltage in order to generate a plurality of period control signals according to the detected voltage level; and an oscillation unit for generating a ring oscillation signal having a constant period determined by a resistance of a period control resistor when a self refresh signal is activated, wherein the resistance of the period control resistor is controlled according to logic levels of the plurality of period control signals.

PASSIVE STRUCTURE FOR HIGH POWER AND LOW LOSS APPLICATIONS - An integrated circuit radio transceiver and method therefor includes a balun formed to have interleaved traces which is operable to satisfy high current density requirements while reducing resistive and capacitive reactance of the balun to minimize coupling losses and to maintain efficiency. The interleaved traces may be selectively coupled according to design and application requirements.

2009-02-19

20090045886

Wide-bandwidth balanced transformer - The present invention comprises novel means and apparatus which provide both impedance matching of arbitrary impedances and transformation between single-ended, floating, and balanced circuits over very wide operating bandwidths with very low excess loss and very low phase and magnitude ripple in the pass band. The present invention can provide high-performance matching, for example from a 50-ohm single-ended system to a 100-ohm balanced system over a bandwidth of 10 kHz to 10 GHz with an excess loss of less than nominally 1 dB and a bandpass magnitude ripple of less than ±0.5 dB. The present invention also provides precision low-loss power division over very wide-bandwidth. The novel means, according to the present invention, can utilize commonly available materials and can be optimized for specific applications to tailor performance to specific needs and to simplify assembly and reduce cost.

2009-02-19

20090045887

DIRECTIONAL COUPLER - A directional coupler with two sensing conductors and a basic coupler and a supplementary coupler corresponding to them. The basic coupler is based on the coupling between a first sensing conductor (

2009-02-19

20090045888

COUPLER - Various directional coupler arrangements are disclosed. For instance, an apparatus includes first, second, and third conductive patterns disposed on a substrate. Each of these conductive patterns includes a first end and an opposite second end. Moreover, each of these conductive patterns includes a first protrusion at its first end and a second protrusion at its second end.

2009-02-19

20090045889

High-speed router with backplane using muli-diameter drilled thru-holes and vias - A high-speed router backplane is disclosed. The router backplane uses differential signal pairs on multiple signal layers, each sandwiched between a pair of digital ground layers. Thru-holes are used to connect the differential signal pairs to external components. To reduce routing complexity, at least some of the differential signal pairs route through a via pair, somewhere along their path, to a different signal layer. At least some of the thru-holes and vias are drilled to reduce an electrically conductive stub length portion of the hole. The drilled portion of a hole includes a transition from a first profile to a second profile to reduce radio frequency reflections from the end of the drilled hole.

2009-02-19

20090045890

FILTERING CIRCUIT AND STRUCTURE THEREOF - A filtering circuit and a structure thereof are provided. The filtering circuit includes an input terminal, an output terminal, a resonant circuit, a first coupling portion, and a second coupling portion. The resonant circuit is coupled between the input terminal and the output terminal and includes M resonators which are arranged in sequence. A signal received by the input terminal can be transmitted to the output terminal by the resonant circuit through inter-coupling between adjacent resonators. The first coupling portion and the second coupling portion are respectively coupled to non-adjacent resonators. A part of the signal received by the input terminal is transmitted to the second coupling portion via the first coupling portion through cross-couple. Thereby, sideband interference can be further suppressed.

2009-02-19

20090045891

Micro Wave Chemical Reaction Device - The invention performs uniform chemical reactions with high efficiency by action of microwave onto reaction targets placed within a flow path along a center axis of a waveguide for transmission of microwave. The microwave chemical reaction device includes a circular waveguide for transmission of TM or TE mode microwave or a square waveguide for transmission of TE mode microwave and a flow path shielded from a space within the waveguide by a bulkhead of low microwave loss and coaxially extending along the center axis of the waveguide. Reaction targets to be subjected to chemical reactions are accommodated in the flow path and the microwave acts on the reaction targets within the flow path.

2009-02-19

20090045892

CIRCUIT BREAKER WITH ARTICULATING CONTROL CABINET - A circuit breaker is provided having three horizontal circuit breakers coupled together with a base housing. Each of the horizontal circuit breakers comprising a tank secured in the housing, first and second current transformers extending from the tank and exit and entrance insulators extending from the first and second current transformers. The housing is mountable on a support frame. To facilitate shipping and field assembly, the circuit breaker includes an control panel moveably coupled to the housing.

2009-02-19

20090045893

Electromagnetic switching device - An electromagnetic switching device is disclosed with an electromagnet and a movable magnet armature, which is mounted in the switching device with a resetting force, which counteracts the closing force, is different than zero in an OPEN position and is formed at least partially by a magnet arrangement with at least one permanent magnet. The magnet arrangement is arranged fixed in position in the switching device outside the magnetic circuit formed from the electromagnet and the magnet armature, and whose resetting force, which acts on the magnet armature, is at a maximum in the OPEN position.

Electromagnetic transmission device - An electromagnetic transmission device. A guide bar connects to a fixed base and includes magnetic-permeable material and a first central height plane. A coil connects to the fixed base. A support base movably fits on the guide bar. An annular magnetic member connects to the support base and is surrounded by the coil. A magnetization direction of the annular magnetic member is perpendicular to a moving direction of the support base and annular magnetic member. The annular magnetic member includes a second central height plane. The coil interacts with the annular magnetic member to generate a first force. When moving to separate the second central height plane from the first central height plane, the annular magnetic member interacts with the guide bar to generate a second force, driving the support base and annular magnetic member to move along a direction perpendicular to the magnetization direction of the annular magnetic member.

2009-02-19

20090045897

TRANSFORMER AND TRANSFORMER ASSEMBLY - The transformer has a bobbin, a coil assembly and a magnetic core assembly. The bobbin is mounted in the magnetic core assembly and has multiple connecting pins being formed on at least one side of a bottom surface of the bobbin. Each connecting pin has a top surface as a soldering surface that corresponds to a solder pad on a back of a circuit board. At least one fastener is further formed on the bottom surface of the circuit board. Therefore, when the transformer is mounted through the circuit board, the connecting pins are soldered on the back of the circuit board to reduce the total thickness of the combination of the transformer and the circuit board.

2009-02-19

20090045898

INDUCTOR MOUNTING, TEMPERATURE CONTROL, AND FILTERING METHOD AND APPARATUS - Methods and apparatus according to various aspects of the present invention may be implemented in conjunction with a inductor mount mounting to a mounting surface. The inductor mount may comprise an inductor having a center opening, and a surface area encompassing all of a front face, a back face, an inner surface about the center opening, and an outer edge concentric about the center opening. The inductor mount may further include mounting hardware holding the outer edge of then inductor to the mounting surface. A cooling element moves air into contact with the front face, through the center opening, and around the outer edge of the inductor. In various embodiments, the mounting hardware contacts less that ten percent of the surface area of the inductor.

2009-02-19

20090045899

Thin film magnetic device and method of manufacturing the same - A thin film magnetic device is provided, in which magnetic permeability in a high frequency range can be easily improved. Scratch-like grooves extending along an extending direction of a coil (for example, a Y-axis direction being an extending direction of a second coil part) are formed at least one side of a surface and a back of each of a lower magnetic film and an upper magnetic film. A magnetization direction of anisotropic magnetization is controlled in each of formation areas of the scratch-like grooves (formation areas of lower magnetic films and upper magnetic films), and therefore displacement (rotation) of the magnetization direction of the anisotropic magnetization is pinned by the scratch-like grooves. Consequently, certain magnetic permeability is kept even in a high frequency range. Moreover, such formation of the scratch-like grooves may not cause complexity in manufacturing process.

2009-02-19

20090045900

CONDUCTIVE WINDING MODULE AND TRANSFORMER HAVING SUCH CONDUCTIVE WINDING MODULE - A conductive winding module includes a plurality of conductive parts and at least one connecting part. Each conductive part includes a conductive body, a first terminal and a second terminal. The conductive body is interconnected between the first terminal and the second terminal and having a hollow portion therein. The connecting part has a first end and a second end for interconnecting any two adjacent conductive parts. A first connecting line is defined between the first end of the connecting part and the first terminal of an adjacent conductive part. A second connecting line is defined between the second end of the connecting part and the second terminal of an adjacent conductive part. The conductive parts are folded with respect to the first connecting line and the second connecting line such that the first hollow portions of the conductive parts are aligned with each other to define a through-hole.

2009-02-19

20090045901

CONDUCTIVE WINDING MODULE AND TRANSFORMER HAVING SUCH CONDUCTIVE WINDING MODULE - A conductive winding module includes a plurality of conductive parts and at least one connecting part. Each conductive part includes a conductive body, a first terminal and a second terminal. The conductive body is interconnected between the first terminal and the second terminal and having a hollow portion therein. The connecting part has a first end and a second end for interconnecting any two adjacent conductive parts. A first connecting line is defined between the first end of the connecting part and the first terminal of an adjacent conductive part. A second connecting line is defined between the second end of the connecting part and the second terminal of an adjacent conductive part. The conductive parts are folded with respect to the first connecting line and the second connecting line such that the first hollow portions of the conductive parts are aligned with each other to define a through-hole.

2009-02-19

20090045902

WIRE-WOUND TYPE COIL AND WINDING METHOD THEREFOR - A common-mode choke coil includes a magnetic core, external electrodes, first and second wires, and a magnetic top. The magnetic core includes a winding core section and first and second flange sections. The external electrodes are provided on the first and second flange sections. The first wire is directly wound around the winding core section. The second wire is wound around the outside of the first wire. The first turn of the second wire is wound while being in contact with the first turn of the first wire and the first flange section.

2009-02-19

20090045903

INDUCTOR STRUCTURE - An inductor structure including a coil layer and at least a gain lead is disclosed. The coil layer is disposed over a substrate and has a plurality of coil turns, wherein one of the coil turns is grounded. The gain lead is disposed under at least one of the inner side and the outer side of the grounded coil turn and is electrically connected in parallel to the grounded coil turn. The width of the gain lead is less than the width of the grounded coil turn.

2009-02-19

20090045904

INTER-HELIX INDUCTOR DEVICES - The invention is directed to inter-helix inductor devices. The inter-helix inductor device includes a dielectric substrate. An input end is disposed on the first surface of the dielectric substrate. A clockwise winding coil has one end connecting to the input end and at least one winding turn through the dielectric substrate. A counter clockwise winding coil includes at least one winding turn through the dielectric substrate, wherein the clockwise and counter clockwise winding coils are connected by an interconnection. An output end is disposed on the dielectric substrate, connects one end of the counter clockwise winding coil, and is adjacent to the input end.

MODERATELY HAZARDOUS ENVIRONMENT FUSE - A fuse for a moderately hazardous environment comprising includes: (i) a fuse element; (ii) first and second terminals connected to the fuse element; and (iii) a metal enclosure placed around the fuse element, the enclosure configured to protect the environment from an opening of the fuse element, and wherein the first and second terminals extend from the metal enclosure.

2009-02-19

20090045907

Microvaristor-Based Overvoltage Protection - The disclosure relates to an overvoltage protection means containing ZnO microvaristor particles for protecting electrical elements and a method to produce the means. Single microvaristor particles are placed in an arrangement having a monolayer thickness and are electrically coupled to the electrical element to protect it against overvoltages. Embodiments, among other things, relate to: 1-dimensional or 2-dimensional arrangements of microvaristor particles; placement of single microvaristors on a carrier; the carrier being planar or string-like, being structured, being a sticky tape, having fixation means for fixing the microvaristors, or having electrical coupling means. The monolayered overvoltage protection means allows very tight integration and high flexibility in shaping and adapting it to the electric or electronic element. Furthermore, reduced capacitance and hence reaction times of overvoltage protection are achieved.