ARM IP Talks! Keynote: Easing The Path To 32/28 nm

Will the 32/28 nm process nodes ever go "mainstream," or
will costs, complexity, and power problems put these nodes out of reach for all
but a handful of users? High-k metal gate technology could make the difference,
according to John Heinlein, vice president of marketing for ARM's Physical IP
division, in a keynote speech in the IP Talks! presentations hosted
by ChipEstimate.com at the Design Automation Conference.

IP Talks! presentations are ongoing at the ChipEstimate.com
booth Monday-Wednesday, with a long list of presenters from IP
companies and foundries. The half-hour talks are being videotaped, and a video
of the Heinlein keynote is already available.

Heinlein started his talk by noting that mobile computing
applications are now driving system-on-chip design. He cited a prediction that
calls for 2.4 billion consumer mobile devices by 2013, along with 11 billion
embedded and enterprise microcontrollers. One strong driver is the explosive
growth rate in 3G communications. "This really is an opportunity for us," he
said (referring, I believe, to the entire SoC design ecosystem).

Some Development
Challenges

Despite the opportunity, SoC development is becoming much
more complex and expensive, Heinlein noted. Mask costs are approaching $5
million, and it costs billions to develop a new fab. Semiconductor companies
need to make "many millions of units" to recover the costs of design and
tapeout.

ARM's John Heinlein
presents at IP Talks!

And then, power is a huge obstacle. "Power trends are going
in the wrong direction," Heinlein noted. At 45 nm, he said, power consumption
went up; in previous generations, it went down. The power challenge, in fact,
has limited the performance gains available at 45 nm. In addition, he noted, "battery
technology is not nearly keeping up with Moore's
Law."

Are High-K Metal
Gates the Answer?

High-k metal gates provide "one solution to the exploding
power problem," Heinlein said. He noted that ARM is working with the Common
Platform on this technology at 32/28 nm. The technology allows better
performance as one scales from node to node, while reducing power, especially
leakage.

"The shift to high-k metal gates, coming at 32 nm and 22 nm,
has the promise to bring scaling trends back to what we were used to," he said.
"It's also going to reduce design complexity because people had to do really
crazy things to manage the power. And it will make it easier to use aggressive
design styles."

ARM physical IP for 32 nm is now available for the Common
Platform, Heinlein said. It's the result of an early collaborative effort that
influenced the process development in such areas as resolution enhancement
technology (RET). He noted that ARM has done extensive silicon validation and
has taped out test chips. One added low-power technique is variable channel
lengths; this is said to provide more reduction than merely changing the
voltage threshold.

Some claimed results in the transition from 45 nm to 32 nm:
a 43% decrease in leakage, a 30% decrease in dynamic power for the same
performance, and a 55% area reduction for the same performance.

I did a separate, short video interview with John Heinlein
after his talk. In the video clip below, I asked about cost reduction, power
challenges, high-k versus silicon-on-insulator, and restricted design rules. To see the video, click here or launch the video below.

So will 32/28 nm ever become mainstream? "We're trying to
open this process technology to the broadest possible set of entrants,"
Heinlein said.