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A 1T SRAM? Sounds Too Good to be True!

At the IEEE’s International Electron Device Meeting (IEDM) in December a start-up named Zeno Semiconductors introduced a 1-transistor (1T) SRAM. Given that today’s SRAMs generally use between six and eight transistors per bit, this alternative promises to squeeze the same amount of SRAM into a space 1/6th to 1/8th the size of current SRAM designs, leading to significant cost savings.

The device is really a single standard NMOS transistor that behaves as if it were two bipolar transistors connected into something like a flip-flop, although the transistors’ bases are open, rather than cross-coupled to the opposite transistors’ collector, as is done in a standard flip-flop.

The cell is selected by activating the gate, and the bit is set or sensed via the source and drain to provide a differential signal.

This is a decidedly clever departure from standard SRAM configurations, and it reflects a careful observation of the actual behavior of different parts of the underlying single NMOS transistor teamed up with some very innovative thinking.

The single-transistor cell is relatively leaky, though, and slow, so another transistor must be added to the cell to make it behave more like standard memory chips, making the 2-transistor higher-performance version larger than the single-transistor cell shown in this post’s graphic.

Remember that DRAMs use a capacitor and a transistor, so the added transistor would behave similarly to the “Select” transistor in a DRAM cell.

Zeno is not the first company to try making a single-transistor SRAM. In the 1990s another firm pioneered a different sort of 1T SRAM that was based on a thyristor, rather than a transistor. The company’s name was T-RAM.

The Memory Guy asked former T-RAM CEO Kenneth Ervin Young, for his thoughts on the technology. He replied that Zeno’s bit cell appeared to have similar physics to T-RAM and could suffer from similar issues.

The biggest issue, he continued, is that it is likely to have high standby current. This alone makes it problematic in high density applications and also in IoT applications where battery life is a premium.

He said: “At T-RAM we filed over 100 patents and spent 5 years trying to overcome dozens of manufacturing issues with our version of a 1-T SRAM cell. Sadly even with nearly 100 engineering and high technology professionals working tirelessly, and successfully solving many manufacturing issues, we were still unsuccessful in getting the high yields required to profitability move into high-volume manufacturing. Any team following in our footsteps towards a 1-T SRAM technology, I wish the best of luck to.”

A subsequent conversation with one of Zeno’s technical advisors revealed an important difference between the two approaches. T-RAM’s leakage current problems stemmed from the fact that it used a 4-layer diode as the storage element, and these structures have a reverse bias diode leakage. Conversely, the Zeno memory is basically a single transistor and has intrinsically 1/6th the leakage of a conventional 6T SRAM cell. Although there is transistor body leakage which is offset by an injector, the larger leakage is from recombination in the transistor’s depletion region, and that leakage is less than that of a 6T SRAM cell.

This is a very interesting concept. Should it succeed it would not only have implications to the cost of chips with large internal SRAMs, but by reducing the cost of on-chip SRAM it could drive significant changes in the amount of memory used at each level of the memory hierarchy, driving changes to computer architecture.