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Abstract

This article concerns a modification performed on a 32 bit linear feedback shift register (LFSR) used in logic testing systems that permits it to function as a selectable one of several LFSR's.

Country

United States

Language

English (United States)

This text was extracted from an ASCII text file.

This is the abbreviated version, containing approximately
100% of the total text.

Expanded Linear Feedback Shift Register

This article
concerns a modification performed on a 32 bit
linear feedback shift register (LFSR) used in logic testing systems
that permits it to function as a selectable one of several LFSR's.

One LFSR may
be made to look as though it were several LFSR's
(as long as only one is addressed at a time) by adding a memory bank
to it. This strategy leads to
significant card area savings, the
disclosed configuration increasing flexibility and decreasing logic
tester hardware requirements by reducing the number of LFSRs needed
to test a chip.

Referring to
the drawing, the test array is partitioned into
two areas, the configuration and the seed area. Both sections share a
common address and data port, each address in both areas appearing as
a different LFSR. To load the array 1,
the microprocessor 2 serially
inputs the LFSR 3, selects an array address, and loads the array with
the LFSR data. The data can be
configuration or seed data. Before
the LFSR 3 is used, a preparation cycle is executed which selects an
LFSR address, loads the configuration register 4 with configuration
data, and loads the LFSR with a starting seed.
After the LFSR data
is used, it is shifted and its contents saved in the seed area of the
array 1.

To select a
different LFSR, the preparation cycle is again
executed, using a different array address.