The FEC_MDC could be routed to PAD_KEY_ROW2 or to PAD_FEC_MDC. AlsoFEC_MDIO could be routed to either PAD_FEC_MDIO or to PAD_KEY_COL2.For other fec pins also different options might exist. How does thisfit into this group scheme?

For uart1 indeed only one routing possibility exists, but look at uart2:

uart2 txd -> PAD_EIM_D26 -> PAD_PATA_DMARQ -> PAD_GPIO_7

uart2 rxd -> PAD_EIM_D27 -> PAD_PATA_BUFFER_EN -> PAD_GPIO_8

So this at least means that you should not name the array abovemx53_uart1_mux, but something like mx53_uart1_option1,mx53_uart1_option2 and so on.

Then it's probably possible to use mixtures of different optionsfor the uart.

I don't think that this grouping of pads to their functions makessense. On i.MX every pad is muxed independently and not in groups.Which pins belong to which function is board specific and not SoCspecific.