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What it's done is to stack 40nm-class RDIMM memory chips vertically using "through-silicon vias" (TSVs), micron-sized vertical holes through the silicon, with a copper filling. It first said it was going to use this technology in 2007.

Samsung claims that by using its TSV bonding process instead of conventional wire bonding, "signal lines are shortened significantly, enabling the multi-stacked chip to function at levels comparable to a single silicon chip". An 8GB RDIMM built this way is reckoned to use just 40 per cent of the power needed by a conventional RDIMM.

The 3D stacking means memory density can rise by 50 per cent, even with a 30 per cent server memory slot decrease, according to Samsung spokespeople. Its new chips are being tested by customers and Samsung says it will use the 3D TSV stacking with 30nm-class chips. ®