B bus goes via Barrel Shifter. It preprocesses data from source register by shifting left or right or even rotating. The Program Counter is that part of register Bank , that generate address. Registers in register bank are symmetric ie, they can have both data and address. Program counter generates address for nextfunction.Address Incrementer block, increments or decrements register value independent of ALU. There is an Instruction Decode and control block, that provides control signals. (Not in figure)

Pipeline

·In ARM 7, a 3 stage pipeline is used. A 3 stage pipeline is the simplest form of pipeline that donot suffer from the problems such as read before write.

·In a pipeline, when one instruction is executed, second instruction is decoded and third instruction will be fetched.

·This is executed in a single cycle.

Register Bank

ARM 7 uses load and store Architecture.

Data has to be moved from memory location to a central set of registers.

Data processing is done and is stored back into memory.

Register bank contains, general purpose registers to hold either data or address.

It is a bank of 16 user registers R0-R15 and 2 status registers.

Each of these registers are 32 bit wide.

Data Registersà R0-R15

·R0-R12à General Purpose Registers

·R13-R15 à Special function registers of which,

R13à Stack Pointer, refers to entry pointer of Stack.

R14à Link Register, Return address is put to this when ever a subrou

tine is called.

R15à Program Counter

Depending upon application R13 and R14 can also be used as GPR. But not commonly used.In addition there are 2 status registers

CPSRà Current program status register, status of current execution is stored.

SPSRà Saved program Status register, includes status of program as well as processor.

CPSR

CPSR contains a number of flags which report and control the operation of ARM7 CPU.

Conditional Code Flags

Nà Negative Result from ALU

Zà Zero result from ALU

Cà ALU operation Carried out

Và ALU operation overflowed

Interrupt Enable Bits Ià IRQ, Interrupt Disable

FàFIQ, Disable Fast Interrupt

T- Bit

If

T=0, Processor in ARM Mode.

T=1, Processor in THUMB Mode

Mode Bits

Specifies the processor Modes. Processor Modes will be discussed in the next part of this tutorial.

ARM features

Barrel Shifter in data path that maximize the usage of hardware available on the chip.

Auto increment and Auto decrement addressing modes to optimize program loop. This feature is not common in RISC architecture.

à 16 bit thumb compressed mode of instruction introduced. Here given the same memory, if 16 bit instruction is used, additional instructions can be packed. Thus code density can be increased. Embedding a 16 bit variant in a 32 bit processor is called a THUMB.