SandBridge Core Eyes Software-Defined Radio

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Startup Sandbridge Technologies will introduce its programmable baseband processor at the Microprocesor Forum this week, combining two buzzwords: “software-definable radio” and “reconfigurable computing”.

Sandbridge’s SandBlaster DSP and SB9600 baseband processor were designed for the multitude of standards surrounding wireless: everything from GSM and WAP protocols, to multimedia-specific algorithms like MPEG-4, to applications languages like Java. By 2006, 140 million of the 700 million mobile phones will have a digital camera attached, according to analyst firm In-Stat/MDR.

The reprogrammable nature of the core allows designers to specify which wireless algorithm the core needs to process at one time, the “software definition” of software-defined radio.

“Multimedia has already started,” said David Malek, Sandbridge’s vice-president of marketing. “Nokia has announced a new 3G phone (the 6650). Ericsson did the same. When those giants move into the market all the rest will have to follow.”

The possibility that a mobile device may be asked to process all of these, and more, has prompted designers to craft catchall architectures which could be used in a variety of situations. Although Intel Corp. will not address software-defined radio at the Forum here this week, Intel chief technical officer Pat Gelsinger has said SDR is one of his top personal priorities.

Sandbridge’s Sandblaster DSP and the SB9600 core, which contains several of the DSPs, fits within a unique niche in the reconfigurable spectrum. Hardwired microprocessors only execute code; they themselves are not programmable. ASICsblocks of hardwired cores which designers can add or subtract to like a jigsaw puzzlecontain the basic elements of programmability. On the far other end of the spectrum sit programmable logic devices and field programmable gate arrays, a “sea of gates” design which can be programmed to emulate hardwired logic for prototyping.

Somewhere in the middle sit companies like Triscend, which offers an enhanced version of an industry-standard cores surrounded by tens of thousands of gates of programmable logic; for example, the Triscend TE520 contains a 40-MHz 8032 microcontroller surrounded by the equivalent of 25,000 FPGA gates.

Tensilica and ARC Cores take a slightly different approach. The Triscend microprocessor core is known as a “hard” or fixed implementation, which discourages changes that might not be supported in the accompanying software tools. ARC’s cores, on the other hand, are “soft,” meaning that the hardware is actually provided as software code, which can be manipulated, altered, or even added to using custom or third-party instructions. The result can then be compiled using an included software compiler, and sent off to a foundry for manufacturing.

Sandbridge’s hardwired DSP cores can be quickly reprogrammed “on the fly”, Malek said allowing them to emulate functions like GSM and Bluetooth algorithms in software, then move on to other tasks.

Because a number of these functions may be operating simultaneouslysay, communicating through a wireless LAN while conducting a GSM telephone callthe DSPs are designed to handle eight simultaneous threads. The SB9600 contains four DSP cores, for a total of thirty-two threads. All told, the SB9600 can perform a whopping 40,000 RISC MIPS or 9.6 billion multiply-accumulate operations (MACs).

Although Malek called an external microcontroller unnecessary, the SB9600 still has an embedded 922T ARM core for easy programming, along with the usual complement of I/O ports and interrupts. The Sandbridge cores come with tools designed to let programmers do their work in C, not in a low-level assembly language.

Malek declined to disclose the core’s die size or power consumption, although the chip will be fabricated in 0.13-micron custom CMOS.

The end goal? To cut down design cycles. “Everyone wants to be first to market,” Malek said.

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