Jason Thorpe comments;
> > The reason why ARM designer offers this capability is unclear to me.
>
> It means the vectors are in the kernel address space, rather than in
> page 0. It makes VM management somewhat easier on those systems.
Ok, the point was taken. The design intent of CP15 reg1 V bit to move
reset entry and runtime exception vector looks to pursue dual goals
somehow and "reset entry" part is troublesome (not a solution) at best.
The architect of AVR32 made extensive research about ARM and other
RISC. It's definitely good learning experience to read the PDF identifying
which part is derived from which RISC design. I wonder how ARM can
be multi-core embedded w/o patching shortcomings.
Toru Nishimura/ALKYL Technology