Battery Powered Motor Drives: Power Stage Design

Welcome back to part three of the training series Battery Powered Motor Drive Applications. Designing High Performance Power Stage.
In the previous part, we have gone through the key parameters to define a high performance power stage and the selection of MOSFETs and gate drivers. In this part, we are continuing the discussion on the power stage design aspects.
We made the statement the MOSFET and gate driver selection is not independent. And we are going to see how they are dependent in the system design. The effect of ON state resistance of the MOSFET. A MOSFET with a low RDS_ON means lower conduction losses. The RDS_ON of the MOSFET depends mainly on two parameters-- the available gate-to-source voltage and the MOSFET operating temperature. The figure shows the RDS_ON of a typical MOSFET.
The MOSFET offers the minimum RDS_ON at the maximum VGS of 20 volts. But 20 volts is the absolute maximum gate for this rating of the FET. Therefore a gateway voltage less than 15 volts is preferred, which gives a good [INAUDIBLE] margin.
It can be observed that the variation of RDS_ON is minimum from around 8 volts to 20 volts gate-to-source voltage. The RDS_ON start increasing drastically as the gate voltage decreases from around 6 volts.
The [INAUDIBLE] on the right-hand side shows the performance of the gate drive DRV8305. The DRV8305 has a triple charge pump gate drive architecture. This ensures even at low DC bus voltage of 5 volts, the gate drive voltage output is 8 volts, ensuring that the MOSFET are conducting at the minimum RDS_ON and hence maximum efficiency.
In short, the design is not optimized by selecting the MOSFET with the lower RDS_ON, but need to select proper gate driver which can ensure the best gate drive performance at all conditions. For more details, check out the TI design TIDA-00771.
Effect of gate charge of the FET. The gate charge is one of the parameters which determines the switching [INAUDIBLE] or switching time of the MOSFET. For understanding this, let us have a look at the gate charge profile of a MOSFET.
The figure shows the gate-to-source voltage variation of the MOSFET with the gate charge. The figure below shows the internal parasitic capacitance of the MOSFET. There is gate-to-source capacitance CGS, gate-to-train capacitance CGD, called as the Miller capacitance, and the drain-to-source output capacitance CDS. RG is the internal gate resistance.
Figure on the right-hand side shows to complete switching characteristics of the MOSFET. For better understanding, it is divided into four regions. Initially, the MOSFET was off. The full DC bus voltage appears across the MOSFET, and current through the FET is 0. In region 1, we are trying to turn on the FET by supplying gate charge.
On the process, the gate charge increases, and at the end of region 1, the gate charge reaches the threshold charge QGS threshold. Now, the MOSFET starts conducting, and the current through the MOSFET increases from 0 to the full load current.
At the end of region 2, the MOSFET current reaches the full load current. In region 3, the drain-to-source voltage of the MOSFET slew from the full DC bus voltage to the on state or voltage drop of the MOSFET. During this region, majority of the gate current flows through the Miller capacitance CGD. Therefore, the gate voltage remains almost flat. The time duration for VDS slew can be approximately calculated as QGD divided by gate source current.
In region 4, the gate voltage continues to rise from the Miller voltage to the full gateway voltage. The FET switch losses occur in region 2 and 3. The switching loss can be reduced by reducing the duration of region 2 and 3 and which can be achieved by using a gate driver with a high gate source [INAUDIBLE] current.
Let us see some test research showing the effect of gate current on controlling the VDS slew and the efficiency. The VDS slew rate can be controlled by controlling or profiling to gate current. The [INAUDIBLE] shows the VDS slew rate with the 500 milliampere and 250 milliampere gate current. And we can see that with reduced gate current, the VDS slew is happening at more time.
The gate driver sink current and source current is also affecting the efficiency of the power stage. The test results on the right side show the effect of gate current on the switching loss. A higher gate current reduces the switching loss and hence low [INAUDIBLE] temperature. Refer TIVA-00771 for more details.
Challenges associated with very fast MOSFET turn on. We cannot increase the slew rate indefinitely without other consequences. And fast switching and high slew rate can cause dv/dt coupled induced voltages causing shoot-through. It can cause switch-node ringing, EMI problems, and high diode reverse recovery losses.
dv/dt coupled induced voltage. In the half-bridge shown in the figure, the low-side switch was on. On the process of controlling the motor current, the low-side switch is turned off, and the time is inserted. During that time, the bottom diode conducts. Until now, the phase node voltage, which is the voltage at the midpoint of the half-bridge is close to 0.
After that time, the top side switch is turned on. As the top side FET VDS slews during turn on the phase node voltage changes from approximately 0 to the DC plus voltage. The rate of change of phase node voltage is determined by the VDS slew rate of high set MOSFET.
This phase node dv/dt causes capacity current through the Miller capacitance CGD and charges the gate capacitance. This causes increase in voltage at the gate and if this induced voltage increases more than the gate pressure voltage, the bottom MOSFET will turn on. This leads to shoot-through as the top MOSFET is all the way on. That means on the problems of turning on the top FET, undesirably, we've returned on the [INAUDIBLE] also.
cdv/dt pickup, effect of VGS threshold and FET capacitance. Figure shows internal capacitances of the MOSFET. At steady state, VGS is equal to VDS multiplied by the capacitance ratio. If the VGS pick up voltage is less than the threshold voltage, the MOSFET stays off.
On rearranging this equation, we get away with the condition. If the MOSFET has the QGD less than QGS threshold, there will not be any shoot-through.
The Miller capacitor CGD is not a constant. It depends on the rate-to-source voltage. The VGS of the MOSFET is not a constant, which is depends on the temperature. The gate threshold voltage decreases with the increasing temperature and hence we need to take the VGS threshold at the operating MOSFET [INAUDIBLE] pressure.
How gate driver can protect inverter against dv/dt turn on. The gate path resistors of the MOSFET consist of the internal gate resistance of the MOSFET, the external gate resistance on gate, and the gate driver internal switch resistance RLO.
If the gate resistance is minimum, the dv/dt induced current will flow through the external gate resistor rather than through the gate capacitance. This reduces the chance of cdv/dt-induced turn on. The dv/dt limit to ensure the gate voltage stays in a standard threshold voltage can be calculated by using the equation shown. A lower gate resistance or a higher gate pull-down current enables high dv/dt switching and hence lowers the [INAUDIBLE].
The [INAUDIBLE] gate driver, DRV8305, has the feature of I drive, T drive state [INAUDIBLE], which enables a stronger pull-down on the low-side MOSFET while the high-side MOSFET is slewing.
The strong pull-down provides a path for the charge that couples into the MOSFET gate during high dv/dt. This gives protection against dv/dt turn on.
In summary, how to improve the dv/dt immunity. Choose a low-side MOSFET with a QGD/QGS threshold ratio less than 1. Select a gate drive stage with the minimum pull-down resistance for the FET. Slow down the turn on of the high-side gate drive, but this will increase the switching loss in the high-side MOSFET.
A proper layout. A differential grouping in the gate charging and the charging part helps introducing the common mode voltage pick up and reduces the gate path inductance.
The other design challenge due to faster switching is the phase node ringing. The main cause of ringing is the diode [INAUDIBLE]. A high rate of change of current, di/dt, due to [INAUDIBLE] cause high diode reverse recovery current.
The reverse recovery current will not flow through the load. Instead, it will flow through the parasitic layout inductance. And it is stored as energy in these inductors. The resonant network form right the FET capacitance and parasitic track inductance cause phase node ringing. The figure shows a test result, which is capturing the ringing at the phase node.
What are the concerns regarding this ringing? Voltage margin. The big value of the ringing voltage waveform has be considered in selecting the MOSFET with a sufficient absolute maximum voltage rating.
EMI/EMC. These ringing waveforms produce a lot of EMI concerns. How to reduce the ringing. The PCB layout has to be done to optimize or minimize the parasitic loop inductance. Use a low gate current to slow down the turn-on of the FET. Place decoupling capacitors near each inverter leg. An example placement is shown in the figure. Use RC snubber to attenuate the ringing.
Until now, we have discussed about the high-performance parameters and see that how the MOSFET and gate driver act together in designing a high-performance power stage.
In part 4, we will discuss about the protections required in these power stages. Thank you for watching. 欢迎回来参加培训 系列的第三部分 “电池供电型 电机驱动应用： 设计高性能 功率级”。 在上一部分中，我们已经 讨论了用于定义 高性能功率级的参数 以及 MOSFET 和栅极 驱动器的选择。 在这一部分中，我们将 继续讨论功率级 设计方面。 我们曾指出， MOSFET 和栅极驱动器的 选择并不是相互独立的。 我们将了解 它们在系统设计中 如何相互依赖。 MOSFET 接通 状态电阻的影响。 具有低 RDS_ON 的 MOSFET 意味着更低的导通损耗。 MOSFET 的 RDS_ON 主要取决于 两个参数： 可用的栅极至源极 电压和 MOSFET 工作温度。 图中所示为典型 MOSFET 的 RDS_ON。 MOSFET 在 20 伏的最大 VGS 下 提供最小的 RDS_ON。 但 20 伏是 此等级 FET 的绝对 最大栅极电压。 因此，最好 使用低于 15 伏的 网关电压，这样可以提供 良好的 [听不清] 裕量。 可以观察到， 栅极至源极电压 在大约 8 伏到 20 伏 之间，RDS_ON 的 变化最小。 当栅极电压 从大约 6 伏 下降时，RDS_ON 将 开始显著增大。 右侧的 [听不清] 显示了栅极驱动器 DRV8305 的性能。 DRV8305 具有一个三路 电荷泵栅极驱动架构。 这可确保 即使在 5 伏的 低直流总线电压下， 栅极驱动器电压输出 也是 8 伏，从而 确保了 MOSFET 在 最小 RDS_ON 下导通， 因而确保了最高效率。 简而言之，此设计 未通过选择 具有较低 RDS_ON 的 MOSFET 进行优化， 但需要选择 适当的栅极驱动器 以确保在所有情况下都具有 最好的栅极驱动性能。 有关更多详细信息，请查看 TI 设计 TIDA-00771。 FET 栅极 电荷的影响。 栅极电荷是 确定 MOSFET 的 开关 [听不清] 和 开关时间的 参数之一。 为了理解这一点，让我们 看一下 MOSFET 的栅极 电荷分布曲线。 图中显示了 带有栅极电荷的 MOSFET 的栅极至 源极电压变化。 下图显示了 MOSFET 的内部 寄生电容。 存在栅极至源极 电容 CGS、 称为 Miller 电容的 栅极至漏极 电容 CGD 和 漏极至源极输出 电容 CDS。 RG 是内部 栅极电阻。 右图显示了 MOSFET 的完整 开关特性。 为便于理解，将其 分成了四个区域。 起初，MOSFET 处于关闭状态。 MOSFET 上存在 全直流总线电压， 而且通过 FET 的 电流为 0。 在区域 1 中，我们将 尝试通过提供栅极电荷 来打开 FET。 在此过程中， 栅极电极会增加， 并且在区域 1 的 末尾，栅极电极 会达到阈值 电荷 QGS 阈值。 现在，MOSFET 开始导通， 通过 MOSFET 的 电流将 从 0 增加到 满负载电流。 在区域 2 的 末尾，MOSFET 电流 将达到满负载电流。 在区域 3 中， MOSFET 的 漏极至源极电压 将从全直流总线 电压转换为接通状态 或 MOSFET 的电压降。 在处于此区域期间， 大部分的栅极电流 都将流经 Miller 电容 CGD。 因此，栅极电压 几乎保持不变。 VDS 转换的 持续时间 大致可以按照 QGD 除以栅极 源极电流进行计算。 在区域 4 中， 栅极电压继续 从 Miller 电压升高 到全网关电压。 FET 开关损耗 发生在区域 2 和区域 3 内。 可以通过缩短 区域 2 和区域 3 的 持续时间来 降低开关损耗， 这可以通过 使用具有 高栅极源极 [听不清] 电流的 栅极驱动器来实现。 下面我们看一些试验 研究，这些研究 显示了栅极电流 对于控制 VDS 转换 和效率的影响。 可以通过控制栅极电流 或对其进行性能评测 来控制 VDS 转换速率。 [听不清] 显示了 栅极电流 为 500 毫安和 250 毫安 时的 VDS 转换速率。 我们可以看到， 在栅极电流降低时， VDS 转换的 发生更频繁。 栅极驱动器 灌电流和源电流 也影响 功率级的效率。 右侧的 试验结果 显示了栅极电流对 开关损耗的影响。 较高的栅极电流可降低 开关损耗，从而 降低 [听不清] 温度。 有关更多详细信息， 请参阅 TIVA-00771。 与快速打开 MOSFET 有关的挑战。 我们不可能无限 提高转换速率而不产生其他 后果。 快速开关 和高转换速率 可导致 dv/dt 耦合感应 电压，从而导致击穿。 它可导致开关节点 振铃、EMI 问题 和高的二极管反向 恢复损耗。 dv/dt 耦合感应电压。 在图中所示的 半桥中，下侧开关 处于接通状态。 在控制电机电流的 过程中， 将会关断低侧 开关，并插入时间。 在此期间， 底部二极管导通。 到现在为止， 相位节点电压， 即半桥中点 处的电压， 接近于 0。 该时间过后， 顶侧开关接通。 由于在接通期间 顶侧 FET VDS 将会转换， 相位节点电压 将会从大约 0 伏 变为直流正电压。 相位节点电压的 变化速率 由高侧 MOSFET 的 VDS 转换速率确定。 此相位节点 dv/dt 导致电容电流 通过 Miller 电容 CGD 并使栅极 电容充电。 这会导致栅极处 电压增加， 如果这个感应电压 增加到超过栅极压力 电压，底部 MOSFET 将会接通。 这会导致击穿， 因为顶部 MOSFET 始终接通。 这意味着 在接通顶部 FET 时 如果意外出现 问题，则可能是 我们也重新 接通了 [听不清]。 Cdv/dt 拾取、VGS 阈值的影响和 FET 电容。 图中显示了 MOSFET 的内部电容。 在稳态下，VGS 等于 VDS 乘以 电容比。 如果 VGS 拾取 电压低于阈值电压， 则 MOSFET 保持断开状态。 在调整此方程时， 我们成功考虑了这一条件。 如果 MOSFET 的 QGD 低于 QGS 阈值， 则不会出现 任何击穿。 Miller 电容器 CGD 不是常量。 它取决于 栅极至源极电压。 MOSFET 的 VGS 不是常量， 它取决于温度。 栅极阈值电压 随着温度的升高 而增加，因此，我们 需要在 MOSFET [听不清] 工作压力下 获取 VGS 阈值。 栅极驱动器如何能使 逆变器避免开启 dv/dt？ MOSFET 的栅极 路径电阻器 包括 MOSFET 的 内部栅极电阻、 栅极上的外部 栅极电阻 和栅极驱动器内部 开关电阻 RLO。 如果栅极 电阻为最小值， 则 dv/dt 感应电流 将会流经外部栅极 电阻器而非 流经栅极电容。 这会降低 Cdv/dt 感应开启的几率。 可以通过 使用所示的 方程来计算 dv/dt 限制， 以确保栅极电压保持在 标准阈值电压范围内。 较低的栅极电阻或 较高的栅极下拉电流 可以得到较高 dv/dt 开关速率， 从而降低 [听不清]。 [听不清] 栅极 驱动器 DRV8305 具有 I 驱动功能， 即 T 驱动状态 [听不清]， 此功能可以在高侧 MOSFET 进行转换时 使低侧 MOSFET 具有更强的下拉。 强下拉为 在高 dv/dt 期间 耦合到 MOSFET 中的电荷 提供了路径。 这样即可避免 开启 dv/dt。 总而言之，我们要解决的问题是： 如何提高 dv/dt 抗扰度。 选择 QGD/QGS 阈值比 小于 1 的低侧 MOSFET。 选择对 FET 具有 最小下拉电阻的 栅极驱动级。 减缓高侧栅极 驱动器的开启， 但这会增加 高侧 MOSFET 的 开关损耗。 适当的布局。 在栅极充电中 采用差动分组， 充电部件 可帮助引入 共模电压拾取 并降低栅极路径电感。 更快的开关导致的 另一个设计挑战 是相位节点振铃。 振铃的主要原因 是二极管 [听不清]。 [听不清] 导致的 高电流变化速率 di/dt 会导致高二极管 反向恢复电流。 反向恢复电流 不会流经负载。 而是流经 寄生布局 电感。 而且它会以能量形式 存储在这些电感器中。 谐振网络形成 FET 电容， 寄生跟踪电感导致 相位节点振铃。 图中显示了测试结果， 该测试在相位节点 捕获振铃。 关于这种振铃， 会有什么问题？ 电压裕量。 在选择具有 足够高的绝对 最大额定电压的 MOSFET 过程中， 已经考虑了振铃 电压波形的大值。 EMI/EMC。 这些振铃波形 会产生大量 EMI 问题。 如何减少振铃。 必须对 PCB 进行布局， 以便优化或最大限度地减少 寄生的回路电感。 使用低栅极电流 减缓 FET 的开启。 在每个逆变器引脚附近 放置去耦合电容器。 图中所示为 示例放置方法。 使用 RC 阻尼器 减弱振铃。 到现在为止，我们已经 讨论了高性能参数， 并介绍了在设计 高性能功率级的 过程中，MOSFET 和栅极 驱动器如何相互作用。 在第 4 部分中，我们 将讨论这些功率级中 需要的保护。