PCB Design Blog

With the 16.6 Allegro PCB Editor release, a simplified method to highlight or de-highlight all nets associated with a component is offered in all applications modes. Hover over a symbol(s), then use the RMB to access the ‘Highlight Associated Nets’ command. Nets assigned the DC Voltage property are ignored.
Here are the steps to accomplish highlighting nets:
Using any one of the application modes...

This week, you can view a couple of videos where customers describe how they used Cadence's Allegro TimingVision technology to achieve 4X faster timing closure on DDR3 and DDR4 memory subsystems of their designs and the IPC-2581 design data format and Allegro PCB Editor tools to eliminate surprises at the final stages of PCB design.
Cavium
Routing boards with high-speed interfaces had been a time-consuming,...

This week, you can view a video where a customer describes how they used the Cadence® Sigrity™ PowerSI® tool to enable their team to run what-if cases to gain insights that lead to useful changes in trace widths, impedance, and more. Nexus Technology At Nexus Technology, Joe Socha, signal integrity engineer, is responsible for analyzing tiny PCBs that are used as interposers between memory devices and their...

The following enhancements have been made to the 16.6 Allegro PCB Editor Thieving application. Thieving outline: New ‘Rectangle’ option added to the list. If selected, the user is required to make only two digitizations of a rubber-banded rectangle. Thieving style: A new ‘Line’ setting has been added to the existing ones of ‘Circle’ and ‘Rectangle’. The fill elements will...

The 16.6 release of OrCAD Capture/Capture-CIS provides several areas for you to customize the environment.
Read on for more details …
Customized Tooltips
You can now utilize TCL that can override the Tooltip being displayed.
Try this example:
1. Enter the following TCL commands in the Capture TCL Command window -
proc CustomToolTipForPageObjectsEnabler {args} {
return true;
}
...

The ‘dual_sided_component’ property in the Allegro PCB Editor 16.6 release can be leveraged to support vertical component applications. Apply the property ‘dual_sided_component’ to the symbol definition. Assuming a two-pin component, you will map pin 1 and pin 2 to unique padstacks, each with a ‘Begin’ or ‘End’ layer pad defined. The base layer is established using the Embedded...

The 16.6 Allegro PCB Editor release contains two new selection options, lasso and path, which are available with commands that normally support temp groups; ‘Move’ and ‘Highlight’ are two examples of those commands. If working in an application mode, you can access these selection options from the RMB – Selection Set menu: Read on for more details … Let’s look at a few examples...

Recently, an article was published in Printed Circuit Design and Fab about Multi-Fabric Planning for Efficient PCB Design (see page 22 of printed magazine).
Today's BGA-style packages have a significant impact on PCB layer count, route complexity, and cost. Efficient BGA net assignment and patterning of power and ground pins can make the difference between a four- and a six-layer PCB. Historically, there's...

This week, you can view a couple of videos where customers describe how they used the Sigrity and Cadence SiP Digital Layout products to simulate, verify, and reduce the size and costs of their designs.
Ericsson Meets DDR and PCIe Specs While Avoiding Crosstalk In this Expert Insights video from CDNLive India 2014, Sheetal Jain, a member of the modem organization at Ericsson Design, discusses how his team verified...

The 16.6 Allegro PCB Editor release contains several enhancement to the Artwork Film generation. Read on for more details …
Film Domain Artwork films can now be designated by the domain where they appear. There are four domains available; Artwork, PDF, IPC2581, and Visibility. Access the User Interface by clicking on ‘Domain Selection’. One of the benefits of the domain form is the ability to segregate...

The 16.6 Allegro PCB Editor release's new ‘Slide’ command utilizes a move-intersect algorithm that delivers smoother, more predictable, and localized edits. This change has allowed for simplifying the use model, integrating sliding of off-angle and arc routing, and providing new options to improve efficiency. In 16.6, the standard ‘Slide’ command has been replaced with a new version and is...

Beginning with the 16.6 Allegro PCB Editor release, lines and text can now be moved outside their present Class-Subclass structure. In previous releases, workarounds using the clipboard were necessary to accomplish this task.
Hover over the line, text, or rectangular element, then use the RMB to access the "Change Class/Subclass" command. Select a new class, then one of the subclasses within the Class structure...

A test point is a location within an electronic circuit that is used to either monitor the state of the circuitry or to inject test signals. Test points have two primary uses:
During manufacturing they are used to verify that a newly assembled device is working correctly. Any equipment that fails this testing is either discarded or sent for rework.
After sale of the device to a customer, test points may be used...

Exposing metal through solder mask openings is as necessary as it can be frustrating. For regular arrays and grids of pins of a flip chip, embedding the openings directly in the padstack definition for the bumps is perfect. But, what about for wire bond designs?
Fingers and power/ground rings need to be exposed so they can be bonded to, but visibility of surrounding metal should be minimized. At the same time, it is...

The Allegro Design Workbench Team Design Option (TDO) offers two (2) specific integrator roles for team design and collaboration: Logical design integrator Responsible for front-end design Physical design integrator Responsible for back-end design A logical design integrator or physical design integrator needs to enable Team Design and assign and inform team members to work on the design project from the list of designers...

The signal integrity (SI) prophets had predicted this time would come, and it turns out they were right. The techniques that SI engineers have been using for the past decade to analyze multi-gigabit serial link interfaces are now starting to be applied to parallel memory interfaces, such as DDR4. And it all makes sense.
Back when PCI Express initially came out at 2.5Gbps, we saw a seismic shift in how simulation and...

Just a brief post this week to mention a new capability for Allegro Design Entry HDL (DEHDL) that was made available in the 16.6-QIR4 release. You can now employ net renaming without loss of data:
All instances of the net will be renamed to a new name
All properties and constraints captured on the net instances retained
All membership to net objects are retained
The net rename capability is available...

Just a short post today. In the 16.6 Allegro PCB Editor release, multiple region shapes can now be assigned to a single region constraint object. Using the General Edit Application mode, pre-select multiple region shapes, then use the context-sensitive RMB menu to access the Assign to Region command. Ensure you are in General Edit Application mode. Consider an example where we will assign the region shapes associated...

The use of dual-sided contact components when placed on internal layers of the PCB allows connections to be made from either side of the device. One of the benefits of using this emerging technology is the reduction of core vias that may have been used to make connections from the component to either side of the PCB. Symbols targeted for dual-side applications must have the property ‘dual_sided_component’...

The 16.6 release of Allegro PCB Editor has several new enhancements for team design work (design partitioning) that help reduce the number of .DPF (design partition file) import/export iterations the PCB Design team experiences in the physical team design flow. Flexible Boundaries Designed to reduce the number of iterations between the master and partition designers, it’s now possible for partition designers to...

The 16.6 Allegro PCB Editor now has IPC 2581 data transfer capabilities. Thanks to Ed Hickey – the Allegro Sr. Product Engineering Manager - for preparing this information below. Read on for more details … IPC 2581 Overview PCBs have changed significantly over the past three decades, yet to the surprise of many, we still commonly use 30-year-old ways of communicating design intent to manufacturing. These...

The Add Connect with Offset command in Allegro PCB Editor 16.6 is designed to primarily address the requirement to route with non-standard angles to help minimize impedance discontinuities while routing across fiberglass substrates. Other routing applications may be applicable as a result of this implementation, including, but not limited to, package/connector breakout or routing associated with tester cards. The Offset...