tag: Breker

Predictions are divided into four posts this year. Part one covered markets and drivers. The second part looked at manufacturing, devices and companies and this part will cover methodologies and tools. In addition, the outlook from EDA executives will be provided in a separate post.
Intellectual property
As designs get larger, it should be no surprise that the size of the [getkc id="43" kc_... » read more

Demand for increasingly complex computation, more features, lower power, and shorter lifecycles are prompting chipmakers to examine how standardized hard IP can be used to quickly assemble systems for specific applications.
The idea of using chiplets, with or without a package, has been circulating for at least a half-dozen years, and they can trace their origin back to IBM's packaging schem... » read more

People love to make predictions, and most of the time they have it easy, but at Semiconductor Engineering, we ask them to look back on the predictions they make each year and to assess how close to the mark they were. We see what they missed and what surprised them. Not everyone accepts our offer to grade themselves, but most have this year. (Part one looked at the predictions associated with s... » read more

Semiconductor Engineering sat down to discuss the state of verification with Jean-Marie Brunet, senior director of marketing for emulation at [getentity id="22017" e_name="Mentor, a Siemens Business"]; Frank Schirrmeister, senior group director for product management at [getentity id="22032" e_name="Cadence"]; Dave Kelf, vice president of marketing at [getentity id="22395" e_name="OneSpin Solut... » read more

Semiconductor Engineering sat down to discuss the state of verification with Jean-Marie Brunet, senior director of marketing for emulation at [getentity id="22017" e_name="Mentor, a Siemens Business"]; Frank Schirrmeister, senior group director for product management at [getentity id="22032" e_name="Cadence"]; Dave Kelf, vice president of marketing at [getentity id="22395" e_name="OneSpin Solut... » read more

Semiconductor Engineering sat down to discuss the state of verification with Jean-Marie Brunet, senior director of marketing for emulation at [getentity id="22017" e_name="Mentor, a Siemens Business"]; Frank Schirrmeister, senior group director for product management at [getentity id="22032" e_name="Cadence"]; Dave Kelf, vice president of marketing at [getentity id="22395" e_name="OneSpin Solut... » read more

The evolution of processing architectures has solved many problems within a chip, but for each problem solved another one was created. Concurrency is one of those issues, and it has been getting much more attention lately.
While concurrency is hardly a new problem, the complexity of today’s systems is making it increasingly difficult to properly design, implement and verify the software an... » read more

Extra circuitry costs money, reduces performance and increases power consumption. But how much can really be trimmed?
When people are asked that question they either get defensive or they see it as an opportunity to show the advantages of their architecture, design process or IP. The same holds true for IP suppliers. Others point out that the whole concept of waste is somewhat strange, becau... » read more

Hardware prototyping and [getkc id="30" kc_name="emulation"] have been two sides of the same coin ever since the [gettech id="31071" comment="FPGA"] became a commercial success. Early emulators were all built from FPGAs, and most were used in-circuit, much like prototypes are today. More recently, emulation has become a major piece of the [getkc id="10" kc_name="verification"] flow, to the poin... » read more

When is a design ready to be taped out? That has been one of the toughest questions to confront every design team, and it's the one verification engineers lose sleep over.
Exhaustive [getkc id="56" kc_name="coverage"] has not been possible since the 1980s. Several metrics and methodologies have been defined to help answer the question and to raise confidence that important aspects of a block... » read more