All the news you're looking for from Tensilica, Inc. Find out how you can use Tensilica's customizable, extensible processors to speed your SOC design. See Tensilica for DSPs and all the processing you need to do in the dataplane (dataplane processors - DPUs).

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Wednesday, April 27, 2011

It's a 196-mile race in support of organ donations. Our 12-member team will start in lovely wine country and run across the Golden Gate Bridge, all the way to Davenport, a town near the ocean. No, I'm not a runner, but I am driving the van for the night shift. Yes, the relay runners will run from the 11 am start time on Saturday until approximately 5 pm on Sunday - straight through, resting in the van between runs! It will be crazy!

Wednesday, April 20, 2011

Ann Steffora Mutschler writes in System-Level Design that there are problems with bus-centric SOC designs. See what our VP Marketing, Steve Roddy, had to say about the problems and ways to get around them in this article titled, "To Bus or Not to Bus, That is the Question."

Wednesday, April 13, 2011

Power has become a first-order concern for ASIC and SOC designers right next to performance and area, whether the design is for portable mobile devices, for networking boxes, or for any other application. Optimizing a design for energy at an application and system level has the potential to cut processor and local-memory energy requirements by as much as half in many cases through intelligent design trade-offs. The amount of power savings made at the early architectural level far outweighs any potential power savings that might be made later at the RTL or physical design levels. Read this white paper to find out how to make the maximum power savings.

Monday, April 11, 2011

This paper discusses innovative ways to get around the biggest performance bottleneck when using a processor in your SOC design - the main bus. Tensilica has developed innovative techniques that relieve congestion on the main bus by bypassing it altogether.

Wednesday, April 06, 2011

We're in a major expansion mode and hiring like crazy. I just added a SW engineering position to our web listing. If you know of any good candidates, send them my way - paula@tensilica.com - we're having an employee bonus program right now!

Monday, April 04, 2011

Microprocessor Report has concluded an extensive review of Tensilica's ConnX BBE64 DSP. They conclude: Designers seeking an alternative to principally hardwired baseband designs in order to accelerate time to market, keep algorithm development in the software domain, or achieve flexibility will thus find the BBE64 a capable processor for next-generation basebands in cellular modems, handsets, and base stations.