H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed

H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation

H—ELECTRICITY

H01—BASIC ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof

H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer

H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326

H01L21/4814—Conductive parts

H01L21/4871—Bases, plates or heatsinks

H—ELECTRICITY

H01—BASIC ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed

H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation

H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection

H—ELECTRICITY

H01—BASIC ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto

H01L2224/10—Bump connectors; Manufacturing methods related thereto

H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process

H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

H01L2224/161—Disposition

H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive

H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked

H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

H—ELECTRICITY

H01—BASIC ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto

H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process

H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector

H01L2224/321—Disposition

H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive

H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked

H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

H—ELECTRICITY

H01—BASIC ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto

H01L2224/42—Wire connectors; Manufacturing methods related thereto

H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process

H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector

H01L2224/45001—Core members of the connector

H01L2224/45099—Material

H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof

H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C

H01L2224/45144—Gold (Au) as principal constituent

H—ELECTRICITY

H01—BASIC ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto

H01L2224/42—Wire connectors; Manufacturing methods related thereto

H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process

H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector

H01L2224/4805—Shape

H01L2224/4809—Loop shape

H01L2224/48091—Arched

H—ELECTRICITY

H01—BASIC ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto

H01L2224/42—Wire connectors; Manufacturing methods related thereto

H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process

H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector

H01L2224/481—Disposition

H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive

H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked

H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

H—ELECTRICITY

H01—BASIC ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto

H01L2224/42—Wire connectors; Manufacturing methods related thereto

H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process

H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector

H01L2224/484—Connecting portions

H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch

H—ELECTRICITY

H01—BASIC ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71

H01L2224/732—Location after the connecting process

H01L2224/73251—Location after the connecting process on different surfaces

H01L2224/73253—Bump and layer connectors

H—ELECTRICITY

H01—BASIC ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71

H01L2224/732—Location after the connecting process

H01L2224/73251—Location after the connecting process on different surfaces

H01L2224/73265—Layer and wire connectors

H—ELECTRICITY

H01—BASIC ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected

H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector

H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate

H01L2224/85002—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate being a removable or sacrificial coating

H—ELECTRICITY

H01—BASIC ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected

H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector

H01L2224/85909—Post-treatment of the connector or wire bonding area

H01L2224/8592—Applying permanent coating, e.g. protective coating

H—ELECTRICITY

H01—BASIC ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00

H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90

H01L2224/92—Specific sequence of method steps

H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types

H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto

H01L24/42—Wire connectors; Manufacturing methods related thereto

H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process

H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector

H—ELECTRICITY

H01—BASIC ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

H01L2924/0001—Technical content checked by a classifier

H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

H—ELECTRICITY

H01—BASIC ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

H01L2924/01—Chemical elements

H01L2924/01079—Gold [Au]

H—ELECTRICITY

H01—BASIC ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

H01L2924/10—Details of semiconductor or other solid state devices to be connected

H01L2924/11—Device type

H01L2924/12—Passive devices, e.g. 2 terminal devices

H01L2924/1204—Optical Diode

H01L2924/12044—OLED

H—ELECTRICITY

H01—BASIC ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

H01L2924/10—Details of semiconductor or other solid state devices to be connected

H01L2924/11—Device type

H01L2924/14—Integrated circuits

H—ELECTRICITY

H01—BASIC ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected

H01L2924/151—Die mounting substrate

H01L2924/153—Connection portion

H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface

H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

H—ELECTRICITY

H01—BASIC ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected

H01L2924/161—Cap

H01L2924/1615—Shape

H01L2924/16195—Flat cap [not enclosing an internal cavity]

H—ELECTRICITY

H01—BASIC ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected

H01L2924/181—Encapsulation

H—ELECTRICITY

H01—BASIC ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected

H01L2924/181—Encapsulation

H01L2924/1815—Shape

H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body

H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

H—ELECTRICITY

H01—BASIC ELECTRIC ELEMENTS

H01L—SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR

H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected

H01L2924/1901—Structure

H01L2924/1904—Component type

H01L2924/19041—Component type being a capacitor

Abstract

A process for forming a thermally enhanced Chip On Board semiconductor device (10) with a heat sink (30) is described. In one aspect, a thermally conducting filled gel elastomer material (50) or a silicon elastomeric material or elastomeric material, if the material is to be removed, is applied to the die surface (18) to which the heat sink is to be bonded. During the subsequent glob top application and curing steps, difficult-to-remove glob top material (38) which otherwise may be misapplied to the die surface adheres to the upper surface of the elastomer material. The elastomer material is removed by peeling prior to adhesion bonding of the heat sink to the die. In another aspect, the thermally conducting filled gel elastomer material (70) is applied between a die surface and the inside attachment surface (46) of a cap-style heat sink to eliminate overpressure on the die/substrate interface.

This invention relates generally to integrated circuit packages and methods of package assembly. More particularly, the present invention pertains to the manufacture of Chip On Board devices with heat sinks for high power dissipation.

2. State of the Art

Semiconductor devices are used in a wide variety of products, including computers, automobiles, integrated circuit cards, audio/video products, and a plethora of other electronic apparatus.

Modern electronic appliances such as computers have hundreds of integrated circuits (IC) and other electronic components, most of which are mounted on printed circuit boards (PCB). Heat is generated by such components. The heat generated by many IC's and other electronic components with simple circuits may often be dissipated without an additional heat sink. However, components requiring added heat sinks are becoming more numerous as the required speed, circuit complexity, and circuit density have increased.

In particular, as semiconductor devices have become more dense in terms of electrical power consumption per unit volume, heat generation has greatly increased, requiring package construction which dissipates the generated heat much more rapidly. As the state of the art progresses, the ability to adequately dissipate heat is often a severe constraint on the size, speed, and power consumption of an integrated circuit design.

The term “heat sink” is used herein in general reference to a passive heat transfer device, for example, an extruded aluminum plate with or without fins thereon. The plate is thermally coupled to an electronic component, e.g. semiconductor die, to absorb heat from the component and dissipate the heat by convection into the air. In this application, a heat sink will be distinguished from a “heat spreader”, the latter pertaining to a member which channels heat from a semiconductor die to leads which exit the die package. However, a heat sink and a heat spreader may together be used to cool a device.

Integrated circuit devices are constructed by making e.g. a (silicon or germanium) semiconductor die with internal and surface circuits including transistors, resistors, capacitors, etc. A single semiconductor die may contain thousands of such components and generate considerable heat. Electrical connection pads on an “active” surface of the semiconductor die are connected to the various die circuits. The integrated circuit device also includes electrical leads enabling the electrical connection pads of the semiconductor die to be connected to circuits on a printed circuit board (PCB) (or other substrate) of an appliance.

Dissipation of generated thermal energy is necessary for safe operation of an electronic appliance. An excessively high temperature of an IC may cause a circuit board fire and damage or destroy the appliance. High temperatures cause failure of the integrated circuits themselves. State of the art methods for absorbing and dissipating thermal energy from high speed Chip On Board (COB) semiconductor devices are inadequate for any or all of the following reasons: (a) insufficient heat transfer capability, (b) excessively large package size, especially the profile height, (c) complexity of manufacture, and/or (d) excessive cost.

In U.S. Pat. No. 5,450,283 of Lin et al., a method for making a semiconductor device with an exposed die backside is described. The method includes providing a printed wiring board (PWB) substrate with conductive traces, on which a semiconductor die is flip mounted and connected to the conductive traces. An electrically non-conductive coupling material is placed between the die and substrate. A package body is formed around the perimeter of the die, covering a portion of the conductive traces and any portion of the coupling material extending beyond the die perimeter. The backside of the die is left exposed through the use of a thin layer of tape placed in the mold cavity prior to the transfer molding of the package body around the die to prevent the flow of molding material forming the package from flowing on the inactive backside of the die. If the thin layer of tape adheres to the die after removal of the semiconductor device from the mold cavity, the thin layer of tape is removed from the die of the semiconductor device.

A device made with multiple layers of encapsulant is shown in U.S. Pat. No. 5,379,186 of Gold et al.

SUMMARY OF THE INVENTION

In accordance with the invention, an improved method for fabricating a Chip On Board semiconductor device requiring enhanced heat dissipation is applicable to direct attachment of semiconductor devices, such as dynamic memory semiconductor dice, to substrates, such as circuit boards and the like, and to the formation of modules incorporating a substrate, such as a circuit board.

In one aspect of the invention, an elastomer is used to cover a portion of a semiconductor die prior to glob top application of the die to the circuit board. The elastomer is removed, e.g. by peeling, from the die surface and includes any glob top material which has inadvertently been applied to the elastomer. Thus, the portion of the semiconductor die remains free of contaminants. If desired, since a portion of the semiconductor die is free of contaminants, providing a good adhesion surface, a heat sink may be attached to such portion of the semiconductor die. The method is applicable to both wire-bonded dies and flip-chip die bonding to circuit boards. Alternately, the elastomer may be retained on a portion of the semiconductor die after the molding or glob-topping of the die for the attachment of a heat sink thereto, if desired. The elastomer may be a highly thermally conductive elastomer to enhance the heat transfer from the semiconductor die to the surrounding environment. An example of a highly thermally conductive elastomer is a metal-filled elastomer or an elastomer filled with a highly thermally conductive material like metal.

The preferred elastomer is highly heat conductive, very compliant, has a relatively low adhesiveness and a high surface wetting property, all the type of properties that enhances heat transfer from the semiconductor die.

In another aspect of the invention, a heat conductive cap is formed over a semiconductor die and comprises a heat sink. A layer of the metal filled gel elastomer is placed between the non-active surface of a die and the cap. Compressing the die into the cap forms the desired adhesion to retain the die within the cap. The compliance of the elastomer enables the die and cap to be pressed together without overpressuring the die/circuit board interface. In addition, the high thermal conductivity of the elastomer enables devices having a very high heat output to be cooled to temperatures enabling reliable operation.

The method of the invention includes steps for forming direct die-to-circuit board connections for “heat sinked dies” as well as for forming “heat sinked” die modules which may be themselves connected to a substrate such as a circuit board.

These and other features and advantages will be more clearly understood from the following detailed description when taken in conjunction with the accompanying drawings. It is important to note that the illustrations are not necessarily drawn to scale, and that there may be other embodiments of the invention which are not specifically illustrated. Like elements of the various figures are designated by like numerals.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The invention is illustrated in the following figures, wherein:

FIG. 1 is a perspective view of a wire-bonded Chip On Board (COB) semiconductor device of the invention;

FIG. 2 is a perspective view of a flip-chip Chip On Board (COB) semiconductor device of the invention;

FIGS. 3A through 3G are cross-sectional views of a wire-bonded Chip On Board (COB) semiconductor device illustrating the steps of fabrication in accordance with the invention, as taken along line 3—3 of FIG. 1;

FIGS. 4A through 4F are cross-sectional views of a flip-chip Chip On Board (COB) semiconductor device illustrating the steps of fabrication in accordance with the invention, as taken along line 4—4 of FIG. 2;

FIG. 5 is a cross-sectional view of a Chip On Board (COB) semiconductor device of the invention having a cap as a heat sink;

FIG. 6 is a cross-sectional view of a circuit board mounted semiconductor device of the invention having a cap as a heat sink; and

FIG. 7 is a cross-sectional view of a circuit board mounted semiconductor device of the invention having a heat sink resiliently retained on the semiconductor die.

DETAILED DESCRIPTION OF THE INVENTION

As shown in drawing FIG. 1, a first semiconductor device 10 with a high heat generation rate is shown. The device 10 includes a semiconductor die 12 having an active surface 14 with bond pads 16, as known in the art. The semiconductor die 12 has a back side 18 which is bonded to a substrate 20, shown here as a printed circuit board (PCB). The bond pads 16 are shown as conventionally arrayed near the edges 32 of the semiconductor die 12, and are wire-bonded with conductive, e.g. gold, wires 22 to corresponding electrical connection pads 24 on the substrate 20. Leads on the upper surface 26 and below the surface 26 of the substrate 20 are not shown.

As shown, a heat-conductive heat sink 30 with fins 28 is mounted on the upper, i.e. active surface 14 of the semiconductor die 12, between the rows of bond pads 16. The heat sink 30 has a relatively large exposed surface area, enabling a high transfer rate of thermal energy. An adhesive 34 having a high heat conductance is preferably used, but other adhesives may be alternatively used to bond the heat sink 30 to the semiconductor die 12, particularly because the adhesive 34 is applied in a very thin layer.

Also shown in drawing FIG. 1 is a “glob top” material 38 applied to encapsulate and seal the semiconductor die 12, wires 22, and surrounding portions 36 of the substrate 20. A major portion of the heat sink 30 is exposed to the ambient air for high heat transfer rates. If necessitated by very high heat generation, a fan (not shown) may be used in the appliance to further increase heat dissipation. The glob top material 38 may be any suitable glob top material, an encapsulant type material, etc.

In an alternative arrangement, the glob top material 38 may be applied to overcover a major portion or all of the heat sink 30. This results in decreased heat dissipation capability, however, but may be used where the thermal output of the device permits.

It is evident that more than one device 10 may be attached to a single heat sink 30, and together sealed by application of glob top material 38.

The heat sink 30 is typically formed of a conductive metal such as aluminum, and has one surface 46 which is attachable by adhesive 34 to the semiconductor die 12. The heat sink 30 may be of any design which provides the desired heat dissipation, is joinable to the die active surface 14 and sealable by a glob top material 38. For example, the heat sink 30 may either have fins 28 or be finless.

Turning now to drawing FIGS. 3A through 3G, the steps of fabricating semiconductor device 10 from a semiconductor die 12, lead wires 22 and a heat sink 30 are outlined in more detail.

In drawing FIG. 3A, a semiconductor die 12 has an active surface 14 with wirebond pads 16 near opposing sides of the die 12. The back side 18 of the semiconductor die 12 is first bonded to the upper surface 26 of the substrate 20 by a layer of adhesive 40. The substrate 20 may be a printed circuit board (PCB) or other materials such as a flex circuit or ceramic. A layer of a thermally conductive filled gel elastomer 50 may be either applied to the semiconductor die while in wafer form or subsequently applied to active surface 14 between the arrays of bond pads 16 of the die 12 after singulation of the die 12 from the wafer. The purpose of the gel elastomer 50 is to provide a protective mask over an area of the semiconductor die 12 to which the heat sink 30 is to be bonded. Alternately, the elastomer may be retained on a portion of the semiconductor die 12 after the molding or glob-topping of the die 12 for the attachment of a heat sink thereto, if desired. The gel elastomer 50 is applied as a gel or as a semi-solid or solid coupon. The gel elastomer 50, or a suitable silicon elastomeric material, etc. if the elastomer 50 is to be disposed after removal from the die 12, or the use of a metal filled elastomer 50 if such is to remain on the die 12, may include one or more dams 52 to help prevent the flow of any subsequently applied material from covering the surface of the gel elastomer 50. The dams 52 may extend along one or more sides of the semiconductor die 12, as desired, and may be of any suitable height. The dams 52 may be of any suitable material. Alternately, the dams 52 may comprise a second layer of gel elastomer material 50 having a size smaller than that of the gel elastomer material 50. Subsequent glob top application is difficult to precisely control, and any glob top material 38 which lands on the gel elastomer 50 will be later removed by removal of the gel elastomer from the surface 14 of the semiconductor die 12. Typically, the gel elastomer 50 may be removed simply by peeling it from the surface 14 of the semiconductor die 12. Typically, if the gel elastomer 50 is to be removed from the semiconductor die 12 after the glob top material application, a silicon type elastomer may be used on the die 12 and removed therefrom for the application of a heat sink to the die 12.

The gel elastomer 50 is a recently developed material and includes Heat Path™ filled cross-linked silicone gels sold by Raychem. As used in this invention, the elastomer 50 is filled with a conductive material to provide high thermal conductivity. The gel elastomer material is compliant under light pressure, has a solid shape retention, cohesive strength and the ability to wet and adhere to surfaces.

In the next step, shown in drawing FIG. 3B, the wirebond pads 16 are wirebonded to electrical pads 24 on the substrate 20 by e.g. thermosonic, thermocompression or ultrasonic methods, as known in the art.

Alternatively, the wire bonding step may precede application of the elastomer 50.

In drawing FIG. 3C, depicted is the next step of the process, that of applying glob top material 38 or suitable potting material to encapsulate the wire connections and the edges 32 of the semiconductor die 12. The glob top material 38 is typically a thermally resistive polymer such as commercially available epoxy or urethane. The glob top material 38 is typically applied as a curable liquid through a small nozzle, not shown, to extend to the layer of gel elastomer 50, or nearly so. As shown, portions 38A and 38B of the glob top material 38 have spilled onto the exposed surface 44 of gel elastomer layer 50. Without use of the gel elastomer layer 50, effective removal of glob top portions 38A and 38B may damage the die 12 and/or substrate 20 and/or lead wires 22, etc.

Application of the glob top material 38 is followed by a curing step, such as by temperature elevation. The glob top material 38 is cured to provide a hard, impenetrable sealing surface.

As shown in drawing FIG. 3D, the layer of gel elastomer 50 is then peeled away in direction 42 from the surface 14 of the semiconductor die 12. It has been found that the lower surface 51 of the gel elastomer 50 may be easily and cleanly stripped from the surface 14 of semiconductor die 12 by simply peeling away the gel elastomer coupon. This leaves the surface 14 of the semiconductor die 12 clean and prepared for strong bonding of a heat sink 30 with an adhesive material 34, shown in drawing FIG. 3E.

The particular materials which may be used as die-to-substrate adhesives 40 include those commonly known and/or used in the art. Examples of such are polyimides, a 75% silver filled cyanate ester paste, an 80% silver filled cyanate ester paste, a silver filled lead glass paste, a silver filled cyanate ester paste, etc.

The adhesive material 34 used to bond the heat sink 30 to the surface 14 of the semiconductor die 12 may be an epoxy or the above identified die-to-substrate adhesives or an adhesive as known in the art.

As illustrated in drawing FIG. 3F, further glob top material 48 may be applied to the device 10, particularly between the existing glob top material 38 and the heat sink 30, for improved sealing. In this figure, the glob top materials 38 and 48 are shown overcovering the substrate 20 between device 10 and an adjacent device, of which only a connection pad 24A and a bond wire 22A are visible. The device 10 is effectively sealed to the substrate 20 to prevent electrical short-circuiting, wire breakage and debonding, and moisture penetration.

In drawing FIG. 3G, a semiconductor die 12 has an active surface 14 with wirebond pads 16 near opposing sides of the die 12. The back side 18 of the semiconductor die 12 is first bonded to the upper surface 26 of the substrate 20 by a layer of adhesive 40. The substrate 20 may be a printed circuit board (PCB) or other materials such as a flex circuit or ceramic. A layer of a thermally conductive filled gel elastomer 50 is either permanently applied to the semiconductor die while in wafer form or subsequently applied to active surface 14 between the arrays of bond pads 16 of the die 12 after singulation of the die 12 from the wafer. A layer or piece of disposable elastomer or tape 150 is releasably applied over the gel elastomer 50. The purpose of the elastomer or tape 150 is to provide a protective mask over an area of the gel elastomer 50 attached to the semiconductor die 12 to which the heat sink 30 is to be bonded. The elastomer 150 is applied as a semi-solid or solid coupon. The elastomer 150 is to be disposed after removal from the die 12 and may include one or more dams 52 to help prevent the flow of any subsequently applied material from covering the surface of the elastomer 150. The dams 52 may extend along one or more sides of the elastomer 150, as desired, and may be of any suitable height. The dams 52 may be of any suitable material. Alternately, the dams 52 may comprise a second layer of gel elastomer material 150 having a size smaller than that of the gel elastomer material 50. Subsequent glob top application is difficult to precisely control, and any glob top material 38 which lands on the elastomer 150 will be later removed by removal of the elastomer 150 from the surface of the gel elastomer 50. Typically, the elastomer 150 may be removed simply by peeling it from the surface of the gel elastomer 150 permanently attached to the semiconductor die 12. Typically, if the elastomer 150 is to be removed from the gel elastomer 50 after the glob top material application, a silicon type elastomer may be used on the die 12 and removed therefrom for the application of a heat sink to the die 12.

As shown in drawing FIG. 3G, the layer of elastomer 150 is then peeled away in direction 42 from the surface of the gel elastomer 50. It has been found that the lower surface 152 of the elastomer 150 may be easily and cleanly stripped from the surface of the gel elastomer 50 by simply peeling away the elastomer coupon. This leaves the surface of the gel elastomer 50 clean and prepared for strong bonding of a heat sink 30 with an adhesive material 34, shown in drawing FIG. 3E.

The glob top materials 38 and 48 may be the same or different materials. Glob top materials useful for this application include HYSOL™ FP4451 material or HYSOL™ FP4450 material, available from the DEXTER ELECTRONIC MATERIALS DIVISION OF DEXTER CORPORATION, etc.

Depicted in drawing FIG. 2 is another aspect of the invention, wherein the semiconductor die 12 is bonded flip chip fashion to electrical circuit traces 54 on the upper surface 26 of substrate 20. The semiconductor die 12 has an active surface 14 with a grid of electrical connections 56 attached to the corresponding traces 54. The electrical connections 56 may comprise a ball grid array (BGA) of solder balls, as shown, or other array. The opposite, back side 18 of the die 12 is directed upwardly, away from the substrate 20. A heat sink 30, here shown with fins 28, has an attachment surface 46 which is adhesively bonded to the back side 18 with adhesive 34. Glob top material 38 is applied to seal the semiconductor die 12, including its edges 32, and a surrounding portion 36 of the substrate. A major portion of the heat sink 30 is exposed to the ambient air for high heat transfer rates. Where very high heat dissipation rates are required, a fan (not shown) may be used to provide a high rate of air movement past the heat sink 30. This type of attachment may similarly be used in chip scale packages, if desired. In such an instance, the semiconductor die 12 would be replaced by a chip scale package 12′ bonded flip chip fashion to electrical circuit traces 54 on the upper surface 26 of substrate 20. The chip scale package 12′ having an active surface 14 with a grid of electrical connections 56 attached to the corresponding traces 54. The electrical connections 56 may comprise a ball grid array (BGA) of solder balls, as shown, or other array. The opposite, back side 18 of the chip scale package 12′ being directed upwardly, away from the substrate 20. A heat sink 30, here shown with fins 28, has an attachment surface 46 which is adhesively bonded to the back side 18 of the chip scale package with adhesive 34. Glob top material 38 is applied to seal the chip scale package 12′, including its edges 32, and a surrounding portion 36 of the substrate. A major portion of the heat sink 30 is exposed to the ambient air for high heat transfer rates. Where very high heat dissipation rates are required, a fan (not shown) may be used to provide a high rate of air movement past the heat sink 30.

The steps of fabricating the device 10 of drawing FIG. 2 are illustrated in drawing FIGS. 4A through 4F. If a chip scale package is used rather than a semiconductor die 12, all numerals and descriptions of the invention are the same except that the die 12 is a chip scale package.

As depicted in drawing FIG. 4A, a flip chip or semiconductor die 12 having an active surface 14 with a grid of connections 56 shown as solder balls is down bonded to electrical circuit traces 54 on a surface 26 of a substrate 20. The die 12 has an opposing back side 18 and edges 32. The substrate 20 may be a printed circuit board (PCB) or other material such as a flex circuit or ceramic. A layer or coupon of thermally conductive filled gel elastomeric material 50, alternately a suitable elastomer, silicon elastomeric material, etc. if the material 50 is to be discarded, is applied as a solid or semisolid to the back side 18 of the semiconductor die 12, either before or (preferably) after the die 12 is electrically down bonded to the substrate 20. The gel elastomer 50 masks the back side 18 from glob top material 38 which may be inadvertently misapplied to the back side 18, requiring removal by erosive blasting or other methods. The use of the gel elastomer material 50 obviates such glob top removal methods.

As shown in drawing FIG. 4B, the next step encompasses the application of glob top material 38 to encapsulate and seal the semiconductor die 12 and portions of the adjacent substrate surface 26. Preferably, the spaces 60 between the solder balls 56 are first filled with glob top material 38 or another low viscosity polymeric material. In these figures, the glob top material 38 is depicted as applied to form a nearly uniform depth over an extended substrate area. Some of the glob top material 38 is shown as having been misapplied to the gel elastomer layer 50 as portions 38A and 38B.

The glob top material 38 is then cured, for example, by heating.

As shown in drawing FIG. 4C, the gel elastomer layer 50 is then removed e.g. by peeling it from the back side 18 of the semiconductor die 12. The back side 18 of semiconductor die 12 in drawing FIG. 4D is then bare and clean for enhanced attachment of a heat sink 30 thereto.

In drawing FIG. 4E, a heat sink 30 is bonded to the back side 18 of semiconductor die 12 by a layer of adhesive 34, as already described relative to the embodiment of drawing FIG. 1.

A further application of a glob top material 48 may be performed, particularly to fill the spaces between the glob top 38 and the heat sink 30. The glob top material 48 may be the same as glob top material 38, or may be different.

Alternatively, a room temperature vulcanizing rubber (RTV) which may vary in the degree of thermal conductivity thereof may be used to completely cover and seal the device to the substrate 20, including the glob top material 38.

Although a major portion of the heat sink 30 is unencapsulated in the preferred embodiment, the heat sink may also be completely or nearly completely encapsulated.

The Chip On Board device 10 of drawing FIG. 1 or drawing FIG. 2 may be formed as merely one of a plurality of components attached and sealed to a substrate.

Alternatively, the chip scale package (CSP) device 10 may be a stand-alone encapsulated device whereby a grid of electrical connections is formed on the opposite side 58 of the substrate 20 for bonding to another substrate, not shown.

While application of the gel elastomer material 50 to the semiconductor die 12, when singulated or while in wafer form, is an additional step in device fabrication, it eliminates the troublesome step of glob top removal required by misapplication of glob top material to the die surface. A clean surface for bonding to a heat sink is assured. In addition, no other layers of good conductors and/or poor conductors are required, enabling both (a) high heat removal and (b) a device of reduced dimensions.

The gel elastomer may also be used as a permanent compliant member 70 between a semiconductor die 12 and a heat sink 30. As depicted in drawing FIG. 5, a semiconductor die 12 has an active surface 14 with a ball grid array (BGA) of solder balls 56 connected to traces (not shown) on a circuit board or other substrate 20. A layer 70 of gel elastomer is then applied to inside attach surface 46 of a cap style heat sink 30. The heat sink 30 may be finned, or have no fins 28. In one embodiment, the heat sink 30 has lateral walls 62 whose lower edges 64 are designed to abut the upper surface 26 of the substrate 20. Alternatively (FIG. 6), a portion of the substrate 20 is configured to fit within the open end 66 of the heat sink.

As depicted in drawing FIG. 7, a semiconductor die 12 has an active surface 14 with a ball grid array (BGA) of solder balls 56 connected to traces (not shown) on a circuit board or other substrate 20 having a plurality of apertures 21 therein. A layer 70 of gel elastomer is then applied to inside attach surface 46 of a cap style heat sink 30. The heat sink 30 may be finned, or have no fins 28. In one embodiment, the heat sink 30 has resilient spring members 31 having a portion thereof engaging a fin 28 while the other end thereof engages an aperture 21 of the substrate 20 to resiliently retain the heat sink 30 engaging the gel elastomer 70 which engages the back side 18 of the semiconductor die 12, leaving the heat sink 30 and die 12 free to move with respect to each other.

In either case as illustrated in drawing FIGS. 5, 6, and 7, the back side 18 of semiconductor die 12 is then pressed into the gel elastomer layer 70 for attachment thereto. The adhesion of the gel elastomer layer 70 to the attachment surface 46 of the heat sink 30 and the back side 18 of the semiconductor die 12 as well as the resilient spring members 31 holds the parts in place.

As a further step, the interior of the heat sink “cap” may be filled with encapsulant material 68. In the embodiment of drawing FIG. 5, encapsulant may be injected through holes (not shown) in the heat sink 30.

The embodiment of drawing FIG. 6 is shown with a further ball grid array (BGA) of solder balls 72 on the exterior surface 58 of the substrate. Thus, the device 10 may be bonded to another substrate such as a circuit board, not shown.

In an alternate method of forming the semiconductor devices of drawing FIGS. 5 and 6, the gel elastomer layer 70 is first applied to back side 18 of the semiconductor die 12, which is then pressed into the attach surface 46 of the heat sink 30.

In the embodiments of drawing FIGS. 5 and 6, overpressuring of the die/substrate interface is eliminated by the compliance of the filled gel elastomer. Simultaneously, the high thermal conductivity of the filled gel elastomer maintains high heat dissipation from the device.

It is apparent to those skilled in the art that various changes and modifications may be made to the method and apparatus of the invention as disclosed herein without departing from the spirit and scope of the invention as defined in the following claims.

Claims (43)

What is claimed is:

1. A method for preventing an encapsulant material from adhering to a surface of a semiconductor die comprising:

applying a layer of material as a mask to a portion of said surface of said semiconductor die;

applying an encapsulant material to the remaining portion of said surface of said semiconductor die;

curing said encapsulant material;

removing said layer of material from said surface of said semiconductor die, said removing including peeling said layer from said surface of said semiconductor die;

providing a heat sink having at least one surface; and

securing said heat sink to said surface of said semiconductor die.

2. The method of claim 1, wherein said encapsulant material includes a silicon gel material.

4. The method of claim 1, wherein the heat sink is resiliently mounted to said surface of said semiconductor die.

5. A method for preventing an encapsulant material from adhering to a surface of a chip scale semiconductor package comprising:

applying a layer of material as a mask to a portion of said surface of said chip scale semiconductor package;

applying an encapsulant material to the remaining portion of said surface of said chip scale semiconductor package;

curing said encapsulant material;

removing said layer of material from said surface of said chip scale semiconductor package said removing including peeling said layer from said surface of said semiconductor die;

providing a substrate;

bonding said chip scale package to said substrate;

providing a heat sink having at least one surface; and

securing said heat sink to said surface of said chip scale semiconductor package.

6. A method for preventing glob top material from adhering to a surface of a semiconductor die comprising:

applying a first layer of material to said surface of said semiconductor die;

applying a second layer of material as a mask to a portion of said surface of said first layer of material;

applying an encapsulant material to the remaining portion of said surface of said semiconductor die;

curing said glob top material

removing said layer of material from said surface of said semiconductor die, said removing including peeling said layer from said surface of said semiconductor die;

providing a heat sink having at least one surface; and

securing said heat sink to a surface of said second layer of material.

7. A method for preventing glob top material from adhering to a surface of a semiconductor die comprising:

applying a layer of material as a mask to a portion of said surface of said semiconductor die;

applying glob top material to the remaining portion of said surface of said semiconductor die;

curing said glob top material;

removing said layer of material from said surface of said semiconductor die, said removing including peeling said layer from said surface of said semiconductor die;

providing a heat sink having at least one surface; and

securing said heat sink to said surface of said semiconductor die.

8. A method for fabricating a Chip On Board semiconductor device with a heat sink, said method comprising:

providing a semiconductor die having a first side, a second side, and edges therebetween;

providing a substrate;

providing a thermally conductive heat sink member;

attaching the first side of said semiconductor die to said substrate;

covering at least a portion of the second side of said semiconductor die with a material having an exposed surface;

applying a material to encapsulate said edges of said semiconductor die;

maintaining said exposed surface of said material covering at least a portion of the second side of said semiconductor die substantially unencapsulated;

curing said material to encapsulate said edges of said semiconductor die;

removing said material having an exposed surface covering at least a portion of the second side of said semiconductor die ,said removing including peeling said material from said surface of said semiconductor die; and

attaching said heat sink member to the second side of said semiconductor die.

9. The method of claim 8, wherein providing said semiconductor die includes providing a semiconductor die having wire bond pads; and

wirebonding said wire bond pads of said semiconductor die to said substrate.

10. The method of claim 9, wherein said heat sink member is attached to said semiconductor die between said wire bond pads of said semiconductor die.

11. The method of claim 8, wherein providing said semiconductor die includes providing a semiconductor die having a surface having a grid of circuit connections configured for downbonding to a substrate; and

attaching said semiconductor die to said substrate includes attaching said grid of circuit connections to said substrate.

12. The method of claim 11, wherein said heat sink member is attached to a non-active back side surface of said semiconductor die.

13. The method of claim 8, wherein said substrate is a printed circuit board.

14. The method of claim 8, wherein the step of removing the material includes peeling said material away from the second side of said semiconductor die.

15. The method of claim 8, wherein said covering at least a portion of the second side of said semiconductor die includes covering at least a portion of the second side of said semiconductor die with a thermally conductive gel elastomer filled with thermally conductive particles.

16. The method of claim 15, wherein said gel elastomer is filled with metal particles.

17. The method of claim 8, wherein attaching said heat sink includes attaching said heat sink member to the second side of said semiconductor die with a thermally conductive adhesive.

18. The method of claim 8, wherein attaching said heat sink includes attaching said heat sink member to the second side of said semiconductor die with a polymeric tape.

19. A method for preventing glob top material from adhering to a surface of a semiconductor die comprising:

applying a layer of gel elastomer material as a mask to a portion of said surface of said semiconductor die;

applying glob top material to the remaining portion of said surface of said semiconductor die;

curing said glob top material;

peeling said gel elastomer material from said surface of said semiconductor die; and

attaching a surface of a heat sink to said surface of said semiconductor die.

20. The method of claim 19, wherein said gel elastomer material includes a gel elastomer material filled with particles.

21. A method for fabricating a Chip On Board semiconductor device with a heat sink, said method comprising:

providing a semiconductor die having a first side, a second side, edges therebetween, and electrical terminals;

providing a substrate having electrical connections;

providing a thermally conductive heat sink member;

attaching the first side of said semiconductor die to said substrate;

connecting said electrical terminals of said semiconductor die to said electrical connections of said substrate;

covering at least a portion of the second side of said semiconductor die with a compliant protective layer having an exposed surface;

applying a material to encapsulate said electrical terminals and die edges;

maintaining said exposed surface of said protective layer substantially unencapsulated by said material;

curing said material;

removing said protective layer, said removing including peeling said protective layer; and

attaching said heat sink member to the second side of said semiconductor die.

22. The method of claim 21, wherein said step of providing a semiconductor die includes providing a semiconductor die having wire bond pads; and

connecting said electrical terminals of said semiconductor die includes wirebonding said electrical terminals of said semiconductor die to said connections of said substrate.

23. The method of claim 22, wherein said heat sink member is attached to the second surface of said semiconductor die between said terminals of said semiconductor die.

24. The method of claim 21, wherein providing said semiconductor die includes providing a semiconductor die having an active surface with a grid of circuit connections configured for bonding to a substrate; and

connecting said electrical terminals of said semiconductor die to said electrical connections of said substrate includes bonding said grid to circuit connections on said substrate.

25. The method of claim 24, wherein said heat sink member is attached to a non-active back side surface of said semiconductor die.

26. The method of claim 21, wherein said substrate is a printed circuit board.

27. The method of claim 21, wherein removing said protective layer includes peeling said protective layer away from the second side of said semiconductor die.

28. The method of claim 21, wherein covering at least a portion of the second side of said semiconductor die includes covering at least a portion of the second side of said semiconductor die with a thermally conductive gel elastomer filled with thermally conductive particles.

30. The method of claim 28, wherein said gel elastomer is filled with metal particles.

31. The method of claim 30, wherein attaching said heat sink member includes attaching said heat sink member to the second side of said semiconductor die with a non-stress thermally conductive adhesive.

32. The method of claim 31, wherein attaching said heat sink member includes attaching said heat sink member to the second side of said semiconductor die with a polymeric tape.

33. A method for fabricating a semiconductor device assembly having a heat sink, said method comprising:

providing a semiconductor die having a first side, a second side, and edges therebetween;

providing a substrate;

providing a thermally conductive heat sink member;

attaching the first side of said semiconductor die to said substrate;

covering at least a portion of the second side of said semiconductor die with a material having an exposed surface;

applying a material to encapsulate said edges of said semiconductor die;

maintaining said exposed surface of said material covering at least a portion of the second side of said semiconductor die substantially unencapsulated;

curing said material to encapsulate said edges of said semiconductor die;

removing said material having an exposed surface covering at least a portion of the second side of said semiconductor die, said removing said material including peeling said material away from the second surface of said semiconductor die; and

attaching said heat sink member to the second side of said semiconductor die.

34. The method of claim 33, wherein providing said semiconductor die includes providing a semiconductor die having wire bond pads; and

wirebonding said wire bond pads of said semiconductor die to said substrate.

35. The method of claim 34, wherein said heat sink member is attached to said semiconductor die between said bond pads of said semiconductor die.

36. The method of claim 33, wherein providing said semiconductor die includes providing a semiconductor die having a surface having a grid of circuit connections configured for downbonding to a substrate; and

attaching said semiconductor die to said substrate includes attaching said grid of circuit connections to said substrate.

37. The method of claim 36, wherein said heat sink member is attached to a non-active back side surface of said semiconductor die.

38. The method of claim 33, wherein said substrate is a printed circuit board.

39. The method of claim 33, wherein said covering at least a portion of the second side of said semiconductor die includes covering at least a portion of the second side of said semiconductor die with a thermally conductive gel elastomer filled with thermally conductive particles.