First Open-Source SoC for IoT

Can IoT and Wearable semiconductors be made more cost-effective, and with faster turn around times to meet the needs of the fast-pace highly innovative 5G ecosystem? After covering earlier this year the RISC-V Foundation and the RISC_V’s 4th workshop hosted at the Massachusetts Institute of Technology (MIT)-hosted workshop , now we focus on the 5th RISC-V workshop which was hosted by Google last week and saw the RTL code open-sourced to the community as well as the release of the first open SoC.

5th RISC-V Workshop Addressed Memory Systems (Image Source: MIT)

To realize the promise of billions of IoT devices in 5G, the industry is working to address challenges such as lengthy hardware development cycles, high power consumption, expensive manufacturing and such. One of these challenges is to meet the requirements of industries as diverse as wearables, enterprise fleet logistics, smart power grids, and connected cars. No one solution fits all IoT so customizations will be needed and more so in the embedded IoT space. Google and its RISC-V partners held their 5th RISC-V workshop to continue their work in open HW microcontroller cores. RISC-V now includes a broad range of industry players such as Google, IBM, Qualcomm, Nvidia, HP, Cortus, Draper, Microsoft, Oracle, ADM, Codasip and SiFive.

Major progress was made at the workshop including SiFive’s announced that it was contributing its FE310 SoC RTL code to the open source community. This SoC is being incorporated into an Arduino-compatible development board making it the first RISC-V based open HW development platform for IoT. The workshop also discussed security and memory systems as areas of future work.