Machine Learning

Saturday, July 5, 2014

VLSI ieee projects 2014 guidance and support

Silicon mentor is a
hub to guide & backup the Mtech. and PhD students at the time of pursuing
their major & mini projects in semiconductor and communication domain. we
boost the students in thesis preparation and provide a technical platform for
research in the era of VLSI,Embedded Systems, Communication, Semiconductor,
Biology and Technology Interface and Electrical and Electronics. Students may
also reach us if they are willing for industrial tool specifications such as
cadence orcad,Xilinx FPGA implementation(VHDL Verilog HDL),Tanner EDA,Advance
Design System(ADS),AVR studio,MATLAB,H-spice,P-spice,Modelism,Network
simulator2,Proteaus and many more to follow. Major projects in VLSI & ECE.

VLSI Front End Projects: Front End includes the digital designing,RTL
design(Register Transfer Level),simulation and Design Under Test(DUT)
techniques.It consist of various key terms such as verilog,system
verilog,SVA,OVM,UVM,PERL,TCL etc. It comprises of concepts like clock,setup
& hold time,FSM and RTL optimization. It uses tools like Questa
Sim,Modelism,GTK wave,Xilinx,Icarves Verilog.

VLSI Back End Projects: Back End includes the design verification and
fabrication of a digital design. The verification field is a vast and
developing filed of semiconductor in India.The verification of a digital design
requires highly skilled semiconductor engineers for verifying a digital design.
The process of verification is repeated 15-20 times to prevent errors in the
design of a particular chip. Tools used in VLSI Back End design are Tanner
EDA, Advance Design System-ADS, Magic, SPICE(H-SPICE, P-SPICE,T-SPICE).