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Abstract

Programmed logic arrays usually consist of an AND array and an OR array. The number of cells connected may vary from zero to the maximum on any given array, line while the total connections in the average programmed array amount to 10% to 15% of all possible connections. Hence the performance of a lightly loaded line will vary greatly from that of the heavily loaded one.

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Programmed Power Proportioning for PLAs

Programmed logic arrays usually consist of an AND array and an OR array.
The number of cells connected may vary from zero to the maximum on any given
array, line while the total connections in the average programmed array amount
to 10% to 15% of all possible connections. Hence the performance of a lightly
loaded line will vary greatly from that of the heavily loaded one.

The basic idea described herein, is that of programming the drive power
levels to each array line to a degree that is proportional to the loading on that
individual line. This programming would be done simultaneously with the logic
function and implemented at the same mask level. The AND array of the figure
would be programmed in the following manner:

The bias current for any word line is determined by the equation: iE(n) = (FIn)
(iE Total)/EpsilonFI, where FIn is the number of emitters connected to the word
line under consideration, EpsilonFI is the number of emitters connected to all
word lines, and iE Total is the sum of all word line bias currents in the AND array.
Since two search lines are common to each input current switch, only the
heaviest loaded line is considered.

The resistor and bias current are chosen in the following way: Rm =
DeltaV/im, where DeltaV is the required voltage swing into the array and im is the
bias current in the mth input switch.

im = iLm x iT/EpsiloniL, where iLm is the total emitter current driven by the
mth search line, Ep...