For 4KB pages, x86 CPU has 2 or 1 level TLB, first level is data TLB andinstruction TLB, second level is shared TLB for both data and instructions.

For hupe page TLB, usually there is just one level and seperated by 2MB/4MBand 1GB.

Although each levels TLB size is important for performance tuning, but forgenernal and rude optimizing, last level TLB entry number is suitable. Andin fact, last level TLB always has the biggest entry number.

This patch will get the biggest TLB entry number and use it in furture TLBoptimizing.

For all kinds of x86 vendor friendly, vendor specific code was moved to itsspecific files.