PCB guidelines

A well designed PCB is necessary to achieve good RF performance. A poor layout can lead
to loss in performance or functionality.

A qualified RF layout for the IC and its surrounding components, including matching networks,
can be downloaded from www.nordicsemi.com.

To ensure optimal performance it is essential that you follow the schematics- and layout
references closely. Especially in the case of the antenna matching circuitry (components between
device pin ANT and the antenna), any changes to the layout can change the behavior, resulting in
degradation of RF performance or a need to change component values. All the reference circuits
are designed for use with a 50 ohm single-ended antenna.

A PCB with a minimum of two layers, including a ground plane, is recommended for optimal RF
performance. On PCBs with more than two layers, put a keep-out area on the inner layers directly
below the antenna matching circuitry (components between device pin ANT and the antenna) to
reduce the stray capacitances that influence RF performance.

A matching network is needed between the RF pin ANT and the antenna, to match the antenna
impedance (normally 50 ohm) to the optimum RF load impedance for the chip. For optimum
performance, the impedance for the matching network should be set as described in the recommended
AQFN73 package reference circuitry from Circuit configuration no. 1.

The DC supply voltage should be decoupled as close as possible to the VDD pins with high
performance RF capacitors. See the schematics for recommended decoupling capacitor values. The
supply voltage for the chip should be filtered and routed separately from the supply voltages of
any digital circuitry.

Long power supply lines on the PCB should be avoided. All device grounds, VDD connections, and
VDD bypass capacitors must be connected as close as possible to the IC. For a PCB with a topside
RF ground plane, the VSS pins should be connected directly to the ground plane. For a PCB with a
bottom ground plane, the best technique is to have via holes as close as possible to the VSS
pads. A minimum of one via hole should be used for each VSS pin.

Fast switching digital signals should not be routed close to the crystal or the power supply
lines. Capacitive loading of fast switching digital output lines should be minimized in order to
avoid radio interference.

PCB layout example

The PCB layout shown below is a reference layout for the AQFN package with internal
LDO setup and VBUS supply.

Important: Pay attention to how the capacitor C3 is grounded. It is not directly
connected to the ground plane, but grounded via VSS_PA pin F23. This is done to create
additional filtering of harmonic components.

For all available reference layouts, see the Reference Layout section on the Downloads tab
for nRF52840 on www.nordicsemi.com.