Monday, March 2, 2015

It is interesting that while Samsung
is continuing to develop 3D devices and processing on a single chip -

"Samsung described a second generation of
its 128 Gbit 3-D NAND flash, a 3-bit/cell version with 32 layers now in
production on a 68.9mm2 die. The Korean giant is ahead of the
pack in dense flash and also is expected to beat TSMC to market with 14/16nm
FinFET logic later this year, a fact that help it retain archrival Apple as a
foundry customer."

ITRS and Intel focus on developing chip
stacks -

"Paolo Gargini who leads the ITRS
semiconductor road map effort said chip stacks are today what high-K metal gate
design was in 2007, the next big requirement for progress.

Intel fellow Mark Bohr disagreed. “We need
vertical interconnects one or two orders of magnitude more dense than today’s
through-silicon vias,” he said"

SAN FRANCISCO — This year’s International Solid-State Circuits Conference once again served up a smorgasbord of silicon innovations. Despite the rising costs and complexity of chasing Moore’s Law, engineers cooked up smaller, faster, more media-rich devices and the strange new world of ultra-low power design delivered a few exotic dishes at the annual gathering of chip designers.
My time at the event started with a reception where for the first time I met Lynn Conway, co-author of one of the landmark texts in chip design. In 1979, Conway’s MPC79 event paved the way for quickly turning software files into running chip prototypes, establishing a model of how to spread enabling abstractions quickly to enable innovation.

Samsung described a second generation of its 128 Gbit 3-D NAND flash, a 3-bit/cell version with 32 layers now in production on a 68.9mm2 die. The Korean giant is ahead of the pack in dense flash and also is expected to beat TSMC to market with 14/16nm FinFET logic later this year, a fact that help it retain archrival Apple as a foundry customer.

Only a handful of papers at ISSCC described designs using TSMC’s 16nm process. Expect many more next year as well as perhaps the first papers of foundry customers using Intel’s 14nm FinFET process.
In the hallways at ISSCC, I sought out topic experts to get their opinions on paper sessions they attended. Behzad Razavi of UCLA said he saw a trend to soft radio with transmitters reduced to DSPs linked to small ADCs and antennas, although receivers still require more complex analog circuits.
You don’t have to go to the cloud for analytics, said Chris van Hook, a medical electronics specialist at the Imec institute outside Brussels. More self-learning algorithms are getting embedded at node-level chips in papers he saw.

Jim Warnock, a designer of IBM mainframe processors, aid he was most fascinated by papers in the low-power digital track. “Some of them are running at a few hertz off picowatts with way different kinds of circuit designs…it’s a different world,” he said.

Indeed, I ran into one post-doc from Berkeley who told me aboutstartup Psikick that is designing integrated IoT chips that aim to run off energy harvesters. He said he hopes to launch his own IoT chip startup eventually.

Back at the high end, analyst David Kanter of the Linley Group said IBM’s mainframe chip designers will be challenged to continue differentiate their processors as they increasingly move to off-the-shelf technologies. If a landmark fab sale goes through as expected, the group will design its next zSeries chips in a 14nm process run by Globalfoundries.

IBM’s Warnock expressed confidence he has a laundry list of accelerator blocks for analytics and mainframe functions he can imagine integrating into future mainframe chips. And he said he hopes to design chips made in Globalfoundries’ giant Malta, New York fab.

The event echoed with groans of designers trying to squeeze more out of increasingly complex and costly process nodes. “We should keep on scaling to 7 and 5nm but we need to harvest the sweet nodes,” said Geoffrey Yeap, vice president of technology at Qualcomm, speaking on an evening panel on Moore’s Law.

Liam Madden rallied for the 2.5-D chip stacks he is helping create at Xilinx, the latest of which will use a 20nm process pack 19 billion transistors including 10 ARM A9 cores. With two new metal layers added in the latest nodes, “the RC delays are killing you routing across chip,” he said.

Paolo Gargini who leads the ITRS semiconductor road map effort said chip stacks are today what high-K metal gate design was in 2007, the next big requirement for progress.

Intel fellow Mark Bohr disagreed. “We need vertical interconnects one or two orders of magnitude more dense than today’s through-silicon vias,” he said
.
Madden agreed but expressed confidence TSV density “will go up at least an order of magnitude in the next two or three years, but getting beyond that will be tricky.”

Despite the pains of progress, engineers showed plenty of silicon innovations at the event. The follow pages cull out a few of them.