20nm Dilemma Explained

Semiconductor makers should shift from FinFETs to fully-depleted silicon-on-insulator technology, according to analyst Handel Jones.

This article is a follow up to an earlier analysis of the semiconductor roadmap.

Fully depleted silicon-on-insulator is the best solution for the 28nm and 20nm technology nodes because of its lower cost and leakage and higher performance than bulk CMOS.

The cost of a 100mm2 die in FD SOI at 28nm is 3.0% lower than bulk CMOS and 13.0% at 20nm due to higher parametric yield as well as lower wafer cost. The data also shows that an FD SOI die with comparable complexity to bulk CMOS is 10% to 12% smaller.

The combination of the smaller die area and higher parametric yield should give an equivalent product a 20% cost advantage at 20nm for FD SOI compared to bulk CMOS. In addition, at 28nm FD SOI has performance that is 15% higher than 20nm bulk CMOS. (See chart below.)

FD SOI can provide energy efficiency levels that are far superior to bulk CMOS for low Vdd and high Vdd. The power efficiency of bit cells is superior for FD SOI because of the lower leakage, along with better alpha particle immunity.

Despite these factors, Intel decided to adopt 22nm FinFETs rather than bulk CMOS. It also selected 22nm rather than 20nm in order to eliminate the need for double patterning.

Foundry vendors initially planned to migrate to 16/14nm FinFETs rather than 20nm bulk CMOS. But the reality of FinFETs is that the present device structures do not give cost competitive products through Q4/2017.

As a result, foundry vendors modified their plans. At TSMC, for example, 20nm bulk CMOS now is projected to represent 10% of total revenues in 2014 ($2.3 billion) and as much as 20% of total revenues in Q4/2014 ($1.1 billion).

However, I believe 20nm bulk CMOS will not provide lower cost per gate designs than 28nm, critical for high volume mobile chips. So there is significant uncertainty in the industry regarding the ramp-up rate of 20nm and 16/14nm FinFETs. One possibility is that 28nm wafer volumes will remain high through 2020. (See figure below.)

Shrinking FD SOI to 14nm (called 10nm by STMicroelectronics) also will give large cost advantage against FinFETs. Consequently, FD SOI provides both short-term and long-term cost, power consumption, and performance benefits.

One reason given for not embracing FD SOI is lack of support in the supply chain and concerns with being nonstandard. However, Soitec, SunEdison, and Shin-Etsu Handotai supply FD SOI wafers. If the industry adopts FD SOI they can expand capacity to address the supply chain challenges.

Other issues include the need to develop new libraries and IP, gain expertise in body biasing design capabilities and ensure the establishment of design flows. Leading EDA vendors say these areas can be addressed. Body biasing design techniques are not difficult to learn.

When the timeline of the semiconductor industry was based on a two-year window for new generations of process technology, taking an alternate path had high risks. But now with the lengthening of the timeline for new generations of technology -- and with 28nm and variants having high wafer volumes through 2020 -- the higher risk is in not making the optimum decision.

I welcome readers' views on how the 20nm dilemma will be resolved.

Handel Jones is chief executive of International Business Strategies, Inc.

Although double patterning is certainly a signficant barrier, a more aggressive shrinking (<0.7x) could bring back some more returns. Actually, the greater concern for me is the self-heating that could be aggravated in these thin silicon devices (FDSOI and FinFET). It's harder for heat to move away from hot spots in thin silicon. Even in the Intel trigate case, it has to move down from the narrowest point (the apex).

Yes, the industry has moved to Finfets to solve the problems with bulk. It's going to be difficult for FDSOI to become mainstream now. A few points:
(1) Yes, Finfets when executed properly give significantly lower wafer costs than FDSOI. That's what I heard from both Intel and TSMC people who made the decision in their respective companies.
(2) SOITEC is known to have significant yield problems getting 5nm or 8nm thin SOI uniformly across the wafer. I heard some bad yield numbers from their employees. The $500 wafer cost assumption is optimistic.
(3) With AMD moving away from SOI and the industry choosing Finfets over FDSOI, SOITEC is in trouble. It's been funding various marketing pushes by hiring consultants and third parties who push SOI... They also fund the SOI consortium. Some of the recent stuff about SOI in the press comes from those efforts. If you speak with decision makers in companies, they say Finfets WHEN EXECUTED WELL, are better, cheaper and more scalable.
(4) SOITEC was formed to commercialize the French Govt's (CEA/LETI's) SOI invention. So, ST Micro, which gets a lot of funding from the French govt, is pushing the technology.

"All the industry is going to FinFet, following Intel that has a three years lead and experience"...

Oh sure, I mean Intel has a PERFECT record on process selection, they've NEVER jumped on a technology before it was "ready for prime time" and regretted the consequences, have they? Oh and by the way has anybody seen my bubble memory USB key, I think I must have misplaced it somewhere...hmm!?

The same situation of 2002/2003, when AMD chose the SOI process for ClawHammer. The problems were numerous, but this decision revealed itself good for AMD, if we see at the recent past. http://www.geek.com/chips/amd-paid-ibm-46-million-to-solve-some-soi-problems-552954/

Today AMD has to do a gamble, and FD-SOI could be a good pick (like Altera and Intel alliance).

I think no one has disagreed that 28 nm bulk planar is the cheap(est) starting point. Going to FDSOI or FinFET adds cost, and going to 20 nm adds cost. With the added cost of FDSOI or FinFET, the shrink should be beyond 20 nm to make up, but is 14 nm even enough? Especially with increased lithography costs at 14 nm only adding to the costs?

And be patient... STMicroelectronics will soon be announcing a "major foundry player" that will be both a dual FD-SOI manufacturing source for ST, plus an open source for the industry. This important piece of news came out of the company's Q4 and FY13 presentation in Paris on January 28th....

I am not sure where you get the 3.5nm thickness from. Although it is a great improvement over 6nm vs 12nm argument you were making not long ago. As publicly stated multiple times and will be shown at VLSI symp in a few months, 14nm FDSOI is using 6nm channel thickness. It uses Si channel for NFET and SiGe for PFET. NONE of the FinFET devices published so far have a strain knob for PFET despite all the performance claim and continue to normalize the current per footprint which I consider cheating as a device engineer - this is exactly how TSMC claimed performance parity or even advantage over Intel 22nm. And by the way there is no 16nm or 14nm gate length in 16nm FinFET technology. The shortest gate length in FinFET is 30nm and low leakage devices go all the way to 50nm. Please see TSMC's paper. Those rule of thumb thickness versus gate length don't come into play when you design technology relevant devices. And believe me I did this for both FinFET and FDSOI for more than 6 years.

Dear Sang Kim. You are making the assumption that 14nm technology needs a 14nm gate length, which is not true. This is know across all companies. The technology node number is just a label, without any direct connection to any dimension on the device.
I agree embedded SiGe is not doable on FDSOI, and that's why I used SiGe in the channel, with performance competing with anything that is out there. However, I do not agree FinFET does not need a strain knob. It does and as far as I have seen (experimentally and by analyzing data from Intel and TSMC so far) eSiGe does NOT work the way it used to. The explanation you provided as only the top of the channel conducting the current actually makes things worse. You are paying the capacitance penalty for the entire gated portion of the fin, so if only the top portion really conducts it's less current for a given capacitance.

TSMC's 16nm technology has a gate length of 30nm or more. Same is Intel's 22nm. The cross sections have been clearly shown in conferences. 10nm platform that you quote also has a gate length of more than 20 nm as will be shown in June.
This is the first time I hear FinFET does not need strain and strain is bad. Please talk to people that run wafers.
Whether it's most of the current in the top or all of it, at the end of the day what matters is current per capacitance or gm divided by capacitance. If you do that math FinFET comes shy. Please see broadcom's invited paper at iedm 2013. FinFET ft - even intrinsic , which is simply 1/2pi gm/Cgs comes worse than 20nm planar.
We can talk all day how beautiful a PowerPoint FinFET is. But the fact is that one by one people are seeing its problems.

IBM uses SOI for its Power processors. Your point is valid: Freescale stopped using SOI because of gaps in the design IP, and AMD also retreated. It is hard to gain back the cost of the wafer for $20 chips, I was told.