In a VHDL testbench I instantiate the module "packetfile_ctrl.vhd"
as U1

In the attached macro I add waves. These waves are inputs and outputs
of the module "packetfile_ctrl.vhd".
But what if I want to view internal signals? For example the internal
signal
last_block:
If I write the following command in my macro I do not get a wave of
this signal
"add wave sim:/tb_packetfile_ctrl/u1/last_block"
So how can I add an internal signal?
Is there an alternative way without using the macro (this means
adding a wave belatedly when the waveform - editor is already opened)
?

Some additional question:
Is the shown macro for functinal or for timing simulation ?
The background of this question: When I run the simulation and
open the "signals" window --> ADD WAVE ---> ALL SIGNALS IN DESIGN
I can find the original names of the primary inputs and outputs
but I can NOT find the original internal names, these seem to be
renamed by the compiler.
If I want to analyse a state machine it is impossible without
the original names.

So my question: How can I simulate (functional) without losing
the original names ?

ALuPin_at_web.de (ALuPin) wrote in message news:<b8a9a7b0.0401052315.f3148fa_at_posting.google.com>...

Quote:

Dear Sir or Madam,

I have a question concerning Modelsim:

In a VHDL testbench I instantiate the module "packetfile_ctrl.vhd"
as U1

In the attached macro I add waves. These waves are inputs and outputs
of the module "packetfile_ctrl.vhd".
But what if I want to view internal signals? For example the internal
signal
last_block:
If I write the following command in my macro I do not get a wave of
this signal
"add wave sim:/tb_packetfile_ctrl/u1/last_block"
So how can I add an internal signal?
Is there an alternative way without using the macro (this means
adding a wave belatedly when the waveform - editor is already opened)
?

Wait a minute. You are siming a netlist, not source code.
This may be the reason last_block is gone.
Compile the source files and try
vsim TB_PACKETFILE_CTRL

Hi,

what do you mean with "Compile the source files" ?
Compiling the source files in Modelsim or in QuartusII (Processing
->Start Compilation) ?
When I compile the design in QuartusII and use the following (changed)
macro
I cannot find the internal names yet. (like for example last_block).
last_block is visible somehow, but only in combination with different
additional
signals like dataa, datab, datac, datad, aclr, aload, sclr, sload ...

In a VHDL testbench I instantiate the module "packetfile_ctrl.vhd"
as U1

In the attached macro I add waves. These waves are inputs and outputs
of the module "packetfile_ctrl.vhd".
But what if I want to view internal signals? For example the internal
signal
last_block:
If I write the following command in my macro I do not get a wave of
this signal
"add wave sim:/tb_packetfile_ctrl/u1/last_block"
So how can I add an internal signal?
Is there an alternative way without using the macro (this means
adding a wave belatedly when the waveform - editor is already opened)
?

To be able to add internal module signals in ModelSim 10.1c (for example when simulating a test bench module which has not any I/O pins/ports, the internal signals are necessary to be observable) as follows:

1- Start simulation from the Simulate menu by clicking option "Start Simulation..." (not by double clicking on the module).

2- In the dialog which opens to ask the model/module to simulate, click on "Optimization Options..." button. in the dialog which opens in the Visibility tab check the "Apply the full visibility to all modules (full debug mode)".

In a VHDL testbench I instantiate the module "packetfile_ctrl.vhd"
as U1

In the attached macro I add waves. These waves are inputs and outputs
of the module "packetfile_ctrl.vhd".
But what if I want to view internal signals? For example the internal
signal
last_block:
If I write the following command in my macro I do not get a wave of
this signal
"add wave sim:/tb_packetfile_ctrl/u1/last_block"
So how can I add an internal signal?
Is there an alternative way without using the macro (this means
adding a wave belatedly when the waveform - editor is already opened)
?

To be able to add internal module signals in ModelSim 10.1c (for example when simulating a test bench module which has not any I/O pins/ports, the internal signals are necessary to be observable) as follows:

1- Start simulation from the Simulate menu by clicking option "Start Simulation..." (not by double clicking on the module).

2- In the dialog which opens to ask the model/module to simulate, click on "Optimization Options..." button. in the dialog which opens in the Visibility tab check the "Apply the full visibility to all modules (full debug mode)".

I don't think Modelsim 10.1 was around in 2004 when that post was written :)