eASIC announces next phase of structured ASIC business strategy

April 27, 2004

Stepping up from a Structured ASIC IP provider to a fabless semiconductor

San Jose, California, April 27, 2004 — eASIC® Corporation, a provider of breakthrough Structured ASIC technology and products, today announced stepping up to the next phase in its business strategy of fabless semiconductor model. With this move, the company will offer Structured ASIC chips, while continuing to provide Structured ASIC technology as licensable IP core for embedding in System-on-Chip. This strategy allows eASIC to play both in the Standard Cell arena as well as in the emerging Structured ASIC market. eASIC’s innovative Structured ASIC technology provides ASIC designers with the unique advantages of free NRE (Non Recurring Engineering) and FPGA-like design re-configurability, in addition to other Structured ASIC benefits such as low-cost and fast turnaround time.
“Coming out with Structured ASIC chips based on their innovative eASICore configurable technology makes a lot of sense for eASIC,” stated Jim Lipman, president of SemiView Inc. “Designers are looking for application-adaptable design implementations that address the mid-volume chip market, but without the high cost and long development cycles associated with ASIC design. Structured eASIC appears to be a very viable candidate for this purpose.”

In the first phase of its business strategy, eASIC focused on offering its patented Structured ASIC technology as licensable IP in the form of embedded configurable logic called eASICore®. The eASICore was initially introduced in year 2000 at 0.18 micron, targeting TSMC and UMC processes and later was implemented in silicon at 0.15 and 0.13 micron. The eASICore has been adapted by leading semiconductor companies who helped further improving the technology. Entering the second phase, a Structured ASIC chip is being developed in partnership with Flextronics Semiconductor (NASDAQ: FLEX). This Structured ASIC product family will be fabricated by a world-class IDM semiconductor company, at 0.13 micron, and is scheduled for production launch in early Q1 2005.

“Having the experience of founding the world’s first Structured ASIC company and bringing it to $40M revenue, I have learned the challenges and pitfalls of a young company building an ASIC business,” said Zvi Or-Bach, eASIC founder and CEO. “Forward thinking, at eASIC we devised a two-phase strategy. First, we developed and brewed the technology as an IP, so we won’t be distracted by manufacturing operation issues. And in parallel, we attracted industry leaders as early-adopters to support us in perfecting and validating the technology. The next phase was to establish strategic partnership with a first-class manufacturing company and thus leverage our innovative technology with their proven production and manufacturing expertise. We are very pleased to work together with Flextronics as we plan to jointly offer the FlexASIC, Structured ASIC product family”.

Structured eASIC

eASIC has developed a unique Structured ASIC technology dubbed Structured eASIC. The patented Structured eASIC architecture consists of an array of logic cells (eCells) with SRAM based LUTs (Look Up Table) and flip-flops. eCells are inter-connected by a segmented wiring grid utilizing upper metal layers, which are customized per customer design with a single Via-mask. Logic programming of the eCell is done similarly to an FPGA, by loading a bit-stream to program the LUTs and flip-flops after powering up the device. Thus, a customer design is implemented on the Structured eASIC fabric by using a combination of bit-stream to program the LUTs and single custom Via-mask for customizing the routing. Moreover, single Via-customization has a perfect fit for an alternative lithography approach, namely the Direct-write eBeam. Using Direct-write eBeam eliminates the customization tooling cost, shortens time-to-market and adds manufacturing flexibility.

About eASIC

eASIC® has developed a breakthrough Structured ASIC technology aimed at dramatically reducing the overall fabrication cost and time of customized high-performance semiconductor chips. eASIC’s technology enables rapid and low-cost ASIC and System-on-Chip designs by its innovative use of proven programmable logic fabric in conjunction with single-via customizable segmented routing. As single-via generates ten times higher throughput of Direct-write e-Beam customization, it enables eASIC to offer NRE-free Structured ASIC. The Structured eASIC technology was successfully proven in silicon and validated by world-class semiconductor vendors. Partnering with industry leaders to jointly develop, manufacture and market Structured ASIC products, the company is positioned to become the preferred Structured ASIC solution.

Headquartered in San-Jose California, eASIC Corporation is a privately held company, founded in 1999 by Zvi Or-Bach, the founder of Chip Express, who led the invention of Structured ASIC technology.