While the ARM is a Load/Store architecture, there is one significant and important exception. That exception is the use of a ''semaphore'' which must be read from and/or written to memory in one atomic cycle (so that, for instance, an interrupt cannot get between reading and writing).

While the ARM is a Load/Store architecture, there is one significant and important exception. That exception is the use of a ''semaphore'' which must be read from and/or written to memory in one atomic cycle (so that, for instance, an interrupt cannot get between reading and writing).

Latest revision as of 08:08, 22 December 2011

SWP

Instruction

SWP[S]

Function

SWaP register with memory

Category

Semaphore

ARM family

ARMv3 (and ARMv2as (ARM3))

Notes

-

Contents

While the ARM is a Load/Store architecture, there is one significant and important exception. That exception is the use of a semaphore which must be read from and/or written to memory in one atomic cycle (so that, for instance, an interrupt cannot get between reading and writing).

SWP will swap a word between register(s) and memory as follows: There is an address and two values, an original data and loaded data.

This instruction will load a word from <address> and remember it. The contents of register <original> are then written to the location pointed to by <address>. The remembered word is then placed in <loaded> (it does not overwrite the original data).