Atrenta – What's PR got to do with it?https://www10.edacafe.com/blogs/ed-lee
Just another EDA Blogs weblogThu, 14 Jan 2016 18:44:28 +0000en-UShourly1https://wordpress.org/?v=4.79101573Jim Hogan and Bernard Murphy on IoT Security: How the human body’s defense mechanism may be the model for repelling attacks on the IoThttps://www10.edacafe.com/blogs/ed-lee/2014/10/16/jim-hogan-and-bernard-murphy-on-iot-security-how-the-human-bodys-defense-mechanism-may-be-the-model-for-repelling-attacks-on-the-iot/
https://www10.edacafe.com/blogs/ed-lee/2014/10/16/jim-hogan-and-bernard-murphy-on-iot-security-how-the-human-bodys-defense-mechanism-may-be-the-model-for-repelling-attacks-on-the-iot/#respondThu, 16 Oct 2014 18:27:14 +0000http://www10.edacafe.com/blogs/ed-lee/?p=2386

This article by Atrenta’s CTO Bernard Murphy and investor Jim Hogan has attracted a lot of interest.

Murphy and Hogan say that we can draw inspiration from biology on how to design the IoT fortress: specifically, how the human body wards off attacks from bacteria, viruses, other bad and harmful stuff.

And they describe in detail the concept on how electronic engineers can plan to do so.

It’s an intriguing piece that gives electronic designers a first huge step on how to secure the IoT and keep those of us who are IoT-interconnected – Borg Collective like – protected from the inevitable cyber attacks.

]]>https://www10.edacafe.com/blogs/ed-lee/2014/10/16/jim-hogan-and-bernard-murphy-on-iot-security-how-the-human-bodys-defense-mechanism-may-be-the-model-for-repelling-attacks-on-the-iot/feed/02386Security for IoT is a lot like the BORG Collectivehttps://www10.edacafe.com/blogs/ed-lee/2014/07/24/security-for-iot-is-a-lot-like-the-borg-collective/
https://www10.edacafe.com/blogs/ed-lee/2014/07/24/security-for-iot-is-a-lot-like-the-borg-collective/#commentsFri, 25 Jul 2014 01:49:48 +0000http://www10.edacafe.com/blogs/ed-lee/?p=2284

Bernard Murphy, CTO of Atrenta, talks about the challenges to security that the IoT will bring in our continuing coverage of the IoT panel at DAC…and sees the IoT as a lot like a biological system!!!!

Murphy: The IoT represents a new level of challenge for security – not just because you have to worry about automotive, medical and so on. But also, if you believe the numbers, then the number of potential edge nodes in an IoT is on the order of a trillion or more. That’s two to three orders of magnitude bigger than any existing network you can imagine. It’s about the number of cells you find in a new born baby.

So a trillion edge nodes looks like a biological system. Why is that relevant? Because our approach to security today is very atomic….It’s not a system level approach. You think in terms of system level and you look at analogies with biological systems, then you think in terms of different things.

Of course, you need all the antibodies and antiviruses. But you also want to think about things like signaling – help I’m under attack. It’s not the same thing as defending yourself. You still want to defend. But you also want to signal to your nearest neighbors or an organization around you that you’re under attack. It can isolate you or send in defenses.

Hogan: Bring the white blood cells.

Murphy: And related to that is a mechanism for behavioral detection as opposed to signature detection. Everything we know about software viruses is all based today on signature detection.

The problem with that is that it is a very expensive approach in terms of power when you try to get down to these low power nodes. Why don’t you typically run antivirus on your cell phone? Because it’s going to consume a lot of power.

So, you need localized defenses. You need these signaling mechanisms. In biology there’s this concept of programmed cell death. I may choose to sacrifice myself if I can’t defend myself any longer, because I’m not going to be able to continue my function, but at a minimum I should try to preserve the health of the system.

Hogan: The Collective.

Murphy: Yeah, BORG. We need to start thinking about security in this bigger IoT context as a system problem, and biology is an interesting analogy for that.

Security is going to be HUGE. The IoT is not for sissies. Does it scare you?

As we had previously announced, venture capitalist Jim Hogan moderated a panel at DAC regarding the IoT.

It was an eye opener about all things IoT……or maybe we should call it the IoE (The Internet of Everything), or as one prominent editor noted, the IoW (The Internet of Whatever). Our panelists included: Gary Smith, Market Analyst, GSEDA; Frank Schirrmeister, Group Director, System Development Suite, Cadence; Bernard Murphy, CTO, Atrenta; and Randy Smith, VP of Marketing, Sonics.

Very lively discussion among panelists, but also from the floor! Most notably editor Gabe Moretti of Chip Design and Simon Bloch of Samsung. Bloch, Sr. Director of R&D in mobile consumer wireless devices, posed questions and stimulated discussion to the point where he might be called the unannounced 6th panelist.

Over the next few blogposts, we’ll share snippets of that discussion. Gary Smith will start us off…..

The IoT just a Wall Street buzz word?

Smith: The “IoT“ is what I call a Wall Street buzz word because it’s being used to get stock prices up. I guess it’s working now. Wall Street hasn’t caught on yet.

It’s very much like IP. That’s another Wall Street buzz word. It’s completely meaningless unless you put an adjective in front of it because there’s at least ten different types of IP that serve different markets, have different price lines and different margins.

One of the problems in my job is to come up with numbers. But you have to find something you can measure. And you cannot measure IoT.

When you get into system design, you start looking at the markets vertically (industrial, consumer, automotive). It depends on what market you’re after. You have to decide: “I’m going after the medical market” or “I’m going after the military market” or “I’m going after the automotive market” or the consumer market. There’s a lot of markets you want to be in and there’s a lot of markets you don’t want to be in.

So, you’ve just got to watch out what you are really talking about. When somebody says IoT, you should ask, “what market are you talking about?” The IoT is not a market, it’s a Wall Street buzz word.

IoT = buzzword? Or a technology that can be applied to vertical markets?

As DAC frenzy hits us all, here’s an event that EDA/IP users and media people ought to consider attending.

It’s a Jim Hogan-moderated discussion event on

IoT system design concerns

Jim will 1) introduce the topic; 2) spur, moderate, provoke discussion and 3) sum up what we’ve learned during this session. Of course, this group of speakers are pretty opinionated and won’t need much provocation.

Participants? An eminent cast:

Bernard Murphy, CTO, Atrenta

Frank Schirrmeister, Group Director, System Development Suite, Cadence

Gary Smith, Market Analyst, GSEDA

Randy Smith, VP of Marketing, Sonics

Along with Jim Hogan, EDA/IP’s pre-eminent industry visionary and investor

When: Wednesday June 4, 1:00 – ­2:15 pm

Where: Room 256, DAC at Moscone Center

What will this slate of opinion makers talk about?

The IoT has captured razzle-dazzle headlines and frenzied consumer mindshare in the past year. It’s clearly the biggest electronics apps area to surface since the cell phone.

However, these devices require a foundation that we’re just now trying to understand, define and build. While the consumer demand for these devices is feverish, they really exist at the end of a ubiquitous IoT SYSTEM that has been conceived but now needs to be built and deployed.

But what is the IoT system? What concerns do EDA/IP vendors have in preparing tools for designers of the IoT system?

In the end, we’d like to think that our discussion will help us answer how we get to the IoT.

Please RSVP to Liz Massingill, liz@leepr.com

We hope to see you there!

]]>https://www10.edacafe.com/blogs/ed-lee/2014/05/20/building-iots-jim-hogan-convenes-discussion-at-dac/feed/02240Real RTL Signoff™ is a Comprehensive Signoffhttps://www10.edacafe.com/blogs/ed-lee/2014/03/17/real-rtl-signoff-is-a-comprehensive-signoff/
https://www10.edacafe.com/blogs/ed-lee/2014/03/17/real-rtl-signoff-is-a-comprehensive-signoff/#respondTue, 18 Mar 2014 05:20:27 +0000http://www10.edacafe.com/blogs/ed-lee/?p=2183RTL Signoff is certainly one of the hot topics in chip design circles lately, and one that is garnering great interest and concern. I chatted recently with Piyush Sancheti, VP of Marketing at Atrenta, on what it is, why it’s a design imperative, and how it should be done.

Liz: Piyush, thanks for taking the time out to chat with me today on this vital topic…RTL Signoff.

Piyush: No problem, Liz

Liz: So, to start out, what is RTL Signoff?

Piyush: “RTL Signoff” gained momentum as an established concept in 2013. While the concept is not new, a commonly-accepted definition did not exist in the past, which is now beginning to emerge. Here’s what I think RTL Signoff is: a comprehensive series of well-defined MUST-pass requirements for your RTL before you commit the design to downstream implementation such as synthesis and physical layout. In addition to this complete set of RTL Signoff requirements, you need tools and methodologies to meet the requirement, along with tangible metrics to measure your pass/fail criteria.

Liz: What do you mean by “comprehensive?”

Piyush: I’m talking about a comprehensive list of MUST-pass requirements spanning robustness of RTL across a wide range of structural, functional and implementation issues.

Liz: What has changed in today’s SoC design to require this RTL Signoff mandate?

Piyush: There’s been a huge explosion in design complexity resulting from the hyper-integration of multiple functions on a single chip. We see that entire PCBs or systems are now being replaced with a single SoC. To manage this complexity, SoC designers are increasingly reliant on externally-sourced semiconductor IP, both from 3rd party suppliers and from other design groups within the company. Typically this IP is delivered as user-configurable RTL, which then gets configured for the SoC needs and subsequently integrated. What used to be a lot of design from scratch now is integration of these RTL IP blocks, which makes it extremely critical that they be signed off before integration into the SoC.

Liz: In cases like that, where the SoC replaces an entire PCB, what does that mean to the SoC?

Piyush: A surge of functionality (computing, audio, video, wireless, gaming, external interfaces, memory interfaces, power management, etc.) is crammed into a single chip the size of your thumbnail. We are beginning to see SoC designs with more than a billion gates. This is a staggering task…to ensure that all SoC functions work seamlessly…that the device can be manufactured reliably, is cost effective, has hours of battery life, and responds instantly to your every command. So the question is: how does a designer ensure that all of this will work?

Liz: This sounds quite overwhelming.

Piyush: Liz, it IS overwhelming. Along with this explosion in design complexity, we now have very short market windows and shrinking product cycles – sometimes windows are as short as 3-6 months. A miss on such tight windows can jeopardize the entire project. As you can see, there’s a burning need to manage this risk, which, as I said before, is driving increased reliance on 3rd party IP and internal IP reuse.

Using proven IP content reduces content design risk, but there’s still the risk in assembly and “spec” compliance. IP is not quite plug-and-play yet. They are open to bugs, misuse, abuse and surprises when used outside tested configurations. Any of these issues can derail a project schedule.

Liz: So, how can RTL Signoff rescue today’s chip designer?

Piyush: Let me answer it backwards by saying that the benefit is that it can contribute up to 60% reduction in the design risk.

Liz: How so?

Piyush: RTL tools run faster than layout tools. This allows you to find and fix a lot more problems at RTL, per unit of time, than you can at synthesis or layout. What’s more, higher quality RTL reduces risk of iteration from synthesis or layout back to RTL. And as we all know, a restart of design layout is very expensive. We have customer data that estimated schedule risk on a high-end SoC at more than one year, so a 60% reduction does get their attention.

Liz: What other ways can RTL Signoff help the designer?

Piyush: RTL Signoff can be applied very effectively to IP, both internal and external. Since most IP is sourced as RTL, signoff checks can and must be enforced as part of handoff requirements from the IP supplier, AND as acceptance checks by the SoC team. When dealing with configurable IP, acceptance checks by the SoC team for the configuration you want to use becomes all the more important. Trust but verify.

If your design team employs a rigorous IP signoff methodology at RTL, you get significant efficiencies for SoC level RTL Signoff. At the SoC level you must validate assumptions in the IP and make necessary tweaks when the two are not in sync. Once those are validated, the SoC level signoff can focus on IP integration and commonplace issues at the top level. Then it’s not necessary to validate the internals of IP at this stage, as long as you can intelligently abstract IP validation models. Abstraction can drive an order of magnitude improvement in analysis time and hardware requirements. Ultimately this leads to a significantly-simplified signoff flow.

Liz: Any final thoughts you’d like to add?

Piyush: I’d say that for 2014, RTL Signoff is no longer a choice … It’s a design imperative! Leading-edge SoC design teams have been practicing and reaping the benefits of RTL Signoff for some years now, and it is now present in mainstream SoC design flows. If you are not doing it, you should be! Selective checklists are not a substitute for a comprehensive and disciplined approach. You wouldn’t sign off layout with selective checks…. just as you wouldn’t drive a car on three tires. It’ll probably work but it’s not a guarantee that you’ll get where you want to go. So, you shouldn’t accept anything less than comprehensive RTL Signoff.

Liz: Thank you, Piyush, for alerting us to the crucial need for comprehensive RTL Signoff.

“Ahhh, the age old question of, ‘What does EDA and IP need to do this year?’ Well, …

The IP folks need a way to provide fully validated IP to their customers with not only a good understanding of all the validation that has been done, but also the expected use model and configurations for the IP. The use model is critical because it is quite common for IP to be ‘abused’ in a way or mode that the IP vendor never expected. When this happens, the customer must be able to assess the problem in-situ and work with the IP vendor to find a resolution. A standardized quality metric is much more desirable than the current option of comparing each vendor’s unique assessment of their validation. This validation and analysis should include, but is not limited to, power, clock domains, testability and physical. The ‘clean’ IP can then be used with more confidence by their customers in their SoC integration.

The EDA folks need a way to allow SoC integrators an easy way to use the IP in a productive methodology which allows them to focus on the integration issues and not on the block level issues which take up valuable resources and time. This ‘intelligence’ of SoC integration must be shared between the integrators and the IP vendors in a way that is both elegant and efficient. Hopefully we can ride this year’s zodiac horse into the year of ‘more productive SoC design’.”

We asked Mike Gianfagna, VP of Marketing at eSilicon and former VP of Corporate Marketing at Atrenta, about EDA, IP and the chip industry in 2014.

Ed: What does EDA and IP need to do in 2014?

Mike: Work more effectively with each other. IP integration continues to be a huge bottleneck for SoC design. A more uniform quality metric and a way to enforce it is desperately needed. This problem can’t be solved in isolation. EDA and IP companies need to collaborate to tame this issue. They can do it.

Ed: What does the chip industry want from EDA and IP in 2014?

Mike: The same thing really. Every SoC project is dependent on somebody’s IP. Whether it’s internally supplied or provided by your favorite IP supplier or your favorite ASIC supplier, the requirement for easy integration with no surprises is the same. Better collaboration between members of the SoC supply chain will definitely help.

There’s an EDA industry reunion at the Computer History Museum on October 16th. “EDA: Back to the Future” is being put on by EDAC along with several sponsors, and it looks like it will be a night to remember. To learn more about the event and purchase tickets click here.

Part of this event is a fund raising auction. I recently talked with Mike Gianfagna at Atrenta about the auction to understand what that part is all about.

Ed: Mike, I understand that part of the event on October 16th is a fund raising auction. Can you tell me a little about that?

Mike: Sure Ed. The Computer History Museum is working on an exhibit for EDA – one that captures the rich history of this industry and preserves some of its innovation in the form of physical artifacts and some of its pioneers in the form of oral histories, captured on video. It’s a terrific project, but we need money to keep the progress going. The auction on the evening of October 16th is focused on raising that money.

Ed: What can we expect at the auction? What will we be able to bid on?

Mike: There will be something for every taste and every budget at the auction. The evening will begin with a silent auction and the evening will end with a live auction. We have an incredible range of items to bid on. Want a golf lesson with a PGA pro? We have that. Want a surfing lesson with a world-famous surfer? We have that, too. EDA has a lot of wine aficionados, so there will be plenty of great wine and winery tours to bid on, too. There are also some fantasy weekends in all kinds of places, tickets to some hot sporting events and sailing adventures on San Francisco Bay.

Ed: Wow! That’s a great lineup. I know there will be many “EDA luminaries” at the dinner. Do they factor into the auction?

Mike: Well, as a matter of fact they do Ed. Want to have lunch with Aart de Geus, Jim Hogan or Penny Herscher? You can bid on that. How about dinner with Simon Segars or Kathryn Kranen? You can bid on that, too. You can also bid on Jim Hogan’s top 12 Cabernets or be a part of the pit crew for an American LeMans race with Jack Harding.

Ed: Sounds like there is quite a collection of items assembled for this event. Who is doing all the work to make this auction happen?

Mike: The entire “EDA: Back to the Future” event is staffed with volunteers Ed. I’m helping to coordinate the auction, but I have a lot of help from other members of our committee. And many of our EDA luminaries, EDAC member companies and members of the industry in general are all being exceptionally generous in their donations to the auction. I’ve just touched on a few here. There are many more. Check out the event web site for the latest list.

Ed: Thanks Mike. This sounds like an exciting part of the event – I look forward to seeing how it turns out.

]]>https://www10.edacafe.com/blogs/ed-lee/2013/08/28/the-rtl-signoff-conversation-goes-to-asia/feed/01931How to avoid timing exception pitfallshttps://www10.edacafe.com/blogs/ed-lee/2013/08/20/how-to-avoid-timing-exception-pitfalls/
https://www10.edacafe.com/blogs/ed-lee/2013/08/20/how-to-avoid-timing-exception-pitfalls/#respondTue, 20 Aug 2013 19:27:13 +0000http://www10.edacafe.com/blogs/ed-lee/?p=1917We often think that we’ve got the timing job nailed down and that there aren’t any problems that we can’t easily, almost routinely solve. Using timing exceptions to optimize synthesis or P&R shouldn’t be a problem.

However, making an error when specifying timing exceptions can possibly shut down a design project.

Take a look at what Atrenta’s Shaker Sarwary, Ramesh Dewangan and Sridhar Gangadharan say about how to avoid this situation: