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Vivado Sysgen - The generated Accumulator block does not behave the same when implemented in DSP48s or within the Fabric

Description

My Sysgen simulations appear to work correctly but the design does not behave as expected on hardware.

It does not appear to come out of reset correctly.

Is this a known issue?

Solution

There is a known issue when using this block in Sysgen 2014.2.

If this block is configured to use the "Fabric" implementation, then everything appears to work as expected.

However, if the implementation is changed to use the DSP48s on the device, incorrect behavior can be seen when running on hardware or when simulating the HDL Netlist project generated from the HDL Netlist compilation target.