About This File

General Overview
Universal Verification Methodology Multi-Language (UVM-ML) provides a modular solution for integrating verification components written in different languages into a unified and coordinated verification environment. It consists of an open source library that enables such integrations, and can be extended to support additional languages and methodologies.

This release of the UVM-ML implementation is the result of collaboration work between Advance Micro Devices, Inc., and Cadence Design Systems, Inc. It expands on the mature technology provided by Cadence in Incisive and in previous UVM-ML postings on UVMWorld. It is provided as open source under the Apache 2.0 license.

Information on all news and features can be found in the ml/docs/ directory.

This UVM-ML package is intended to serve as a basis for the verification community to collaboratively expand and evolve the multi-language verification methodology. Please read the “Status, Use, and Disclaimers” section below for full details.

Platforms and Simulators
This release of UVM-ML should run on any simulator supporting one or more of the standard languages: IEEE 1800 (SystemVerilog), IEEE 1647 (e), and IEEE 1666 (SystemC). It was tested on the Linux operating system with various combinations of simulators and languages.

UVM-ML Open Architecture: Status, Use, and Disclaimers
This section provides guidance and status regarding the use of the UVM Multi Language Open Architecture solution.

The UVM-ML Open Architecture package is an open source solution, developed jointly by AMD and Cadence. We welcome feedback including suggestions for improvements. For any feedback or questions, please contact support_uvm_ml@cadence.com

Use and Disclaimers:

Licensing: This package is an open source library, protected under the Apache license (see legal clause at the bottom).

Access: This package is available as early access to the verification community, and therefore changes to its content and behavior should be expected.

Backward compatibility cannot be guaranteed. Changes are expected to take place when the verification community jointly refines the solution, to fit user requirements. We will aim, however, to provide help in adjusting to changes.

Quality: this package is still under development. It is being tested and regressed with all active versions of Incisive and with the Accellera OSCI simulator before being released. The user needs to be aware of the simulator version on which the solution is tested. AMD tested the open source solution on other commercial simulators. Issues reported to AMD and Cadence will be addressed.

Standardization: This package is not a standard. However, it is available as open source to all potential users.

Support: Since this is not a product, it does not have a committed level of product support. We will provide help via the UVMWorld community on Accellera where the source code is posted. For Cadence customers, Cadence will provide direct support as needed.

Note: the model described above is similar to how the very successful OVM and UVM-1.0ea (early version) were provided in the beginning. We believe you can gain significant value from access to this solution, and also be able to participate in developing it to ensure it addresses your needs.
-------------------------------------------------------------------------------------------------------What's new in each version
For the full listing and more details please see the release-notes.txt file at the top of the release package.
Please note that the items in red might require some changes on the user's side while upgrading to this version, please read these items carefully in the release notes.

1.9:

Fully qualified with IES version 15.2 and Xcelium 17.04-17.10.

Runtime phase synchronization between UVM-e to UVM-SV is now supported in UVM-ML OA (only with Xcelium 17.10).

System C TLM2 convenience sockets (including passthrough_initiator/target_socket) are now supported by UVM-ML OA.

1.8

Fully qualified with IES version 15.2 and Xcelium 16.11-17.04.

New debug command for tracing serialization in SV and e : uvm_ml trace_ser

Moving from one Xcelium agile version to the other requires reinstallation of UVM-ML (running install_xclm.csh again) against the respective version) and no additional manual steps are needed

UVM-SV 1.2 is now fully supported (please read RELEASE_NOTES.txt under ml directory for more details).

When working with Incisive 15.2, the user can take some steps in order to skip compiling the e part of the adapter (this might be important for users that compile other
e code on top of Specman, like VIP). The steps are documented in the UVM-ML OA user guide under:
"Linking the Specman UVM-e Adapter From Incisive Version 15.2 On".

OSCI 2.3.1 is now supported instead of OSCI 2.3, meaning that the supported OSCI versions are: 2.3.1 and 2.2.

gcc 4.8.3 is now supported

1.5.1:

Fully qualified with IES versions 14.1,14.2 and 15.1.

Early adopters UVM-SV 1.2 support for IES (please read RELEASE_NOTES.txt under ml directory for more details).

UVM-ML tcl commands are now available from Specman with all supported simulators.

UVM-ML tcl commands are renamed (they all start with uvm_ml prefix, followed by a space and the command name, e.g uvm_ml print_tree). The old names are still supported.

Pre-compiled UVM-SC parts for IES were eliminated.

Examples are enhanced and extended.

Updated the Backplane API version number.

New debug commands in IES to print the UVM-ML tree, port connections, and port registrations.

Improved the handling of UVM-ML bitness (once users select 32 or 64 bit mode, the library and all examples will run in that mode)

Enhanced sequence layering capabilities

Enhanced the test_env.csh script to provide more validity testing of the user's environment and to provide better suggestions how to fix issues

irun_uvm_ml.*.f option files were reorganized (including a name change): IES irun invocation options were grouped into several option files, reflecting the usage context, and adding comments to clarify their meaning

This release might require some changes on the user's code while upgrading to this version, see details in the release_notes.txt”

1.4.2:

Fully qualified with IES version 14.1

Enables usage of Cadence UVM extensions on top of UVM-ML OA

Support for UVM ML configuration tracing on the SV side, activated by the +UVM_CONFIG_DB_TRACE command-line option

Added new backplane API functions enabling the time notification (wakeup) service and updated the backplane API version number

Updated the sequence layering examples. The code is simplified and type conversion using mltypemap is demonstrated

Eliminated the UVM SV warnings

Mechanism to recognize whether OSCI was compiled with pthreads and compile the custom sc_simcontext.cpp accordingly

1.4.1:

New examples showing basic TLM communication

Default installation is 32bit instead of 64bit

Setup and install scripts renamed

UVM-SC has been updated with a standalone phase controller that can run through the common and UVM phases. In addition user defined schedules, which can be synchronized with the standard UVM phases, are supported as well.

Enhanced UVM-SC to support run_test() in the SC-standalone mode (not collaborating with other frameworks)

Methodology and examples for sequence layering across languages

Enhancements in how unified hierarchy works

1.4:

Support for uvm-1.1d (in place of uvm-1.1c)

Addition of a portable UVM-SC adapter.

Simulator independent and tested to run on several simulators

Architected to be highly modular and extensible

A new architecture providing a Backplane that connects Frameworks (where Frameworks can be of different languages or methodologies)

Three examples of language frameworks are provided: UVM-SV, UVM-e, UVM-SC

Enables creating a unified hierarchy of components of different frameworks

1.2.2:

Multi-Language configuration

Support of TLM1 and TLM2 communication between all the provided frameworks

Enhanced synchronization of test phases and delegation of phasing control to a designated framework

User Feedback

Recommended Comments

I just tried to run the example in the package, but there are a lot of link error, can't find "ml_uvm_pkg.sv", etc. Could you give me some help for that, after read whole documents and can't get the example run is really depressed.

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Thank you very much for the quick support, the problem has been solved. It's indeed an environment issue and reason is the newest GCC version not support really well with NCSC. I can get the example running and will dig into it now. Thanks!