Experts at the Table: Stacking the Deck

By Ann Steffora Mutschler System-Level Design sat down to discuss challenges to 3D adoption with Samta Bansal, product marketing for applied silicon realization in strategy and market development at Cadence; Carey Robertson, product marketing director at Mentor Graphics; Karthik Chandrasekar, member of technical staff in IC Design at Altera; and Herb Reiter, president of Eda2Asic Consulting. Part One of this series can be found here.

SLD: With 3D in its many forms impacting design and manufacturing, are we going to see the same kind of competition among EDA vendors and other industry players as we’ve seen in the past? Reiter: If you attended an MBA program, you get told many times, ‘Customers, good. Competitors, bad.’ And now we are telling the MBAs and business managers, ‘Competitors, good; coopetition, cooperation, standards, and so on. So we are brainwashing our executives and that’s not an easy undertaking. At Sematech, it’s really a pleasure to have an IBM and an Intel guy sitting next to each other and joking with each other about a certain topic and saying, ‘Yes, we agree.’ That’s the only way we can go. The beauty is we have a lot of smart people in this industry, and this is necessary. We are facing cost-effectiveness as a pressure and the EDA tools are very important because you can overdesign something that never breaks but you can’t afford it. Or you can underdesign it, and it breaks before you ship it. EDA has to show you where the difference and the borderline between overdesign and underdesign. That’s our value as an industry. Robertson: Coopetition, absolutely, because 3D IC does represent a paradigm shift. With a paradigm shift that means opportunity. By the same token, we have all of these major customers who don’t have all of any one suite of products. What they’re actually looking at is, ‘I have my IC designers and my system designers. They have these sets of products. In an ideal world I want them to be able to do their system design on a 2D SoC or a 3D-IC with a similar design flow.’ So they’re going to push us to enable that. It represents opportunity along with way for point tools to innovate and say, ‘Well, what about this instead,’ but the first thing that customers want is some consistency from node to node; they’re going to want consistency from design flow to design flow. So they’re going to be advocating that and if for some reason a point tool does not step up because of this paradigm shift then there’s opportunity for innovation. I think we’re all starting at this knowing that for us to be successful, for customers to be efficient, it’s not a swapping out your complete design flow, throwing that out, ‘That was the 2D world, here’s 3D world: All new start to finish.’ We won’t realize any efficiency. Bansal: I completely agree. If you think about it, it’s a lot of overhead on one EDA vendor, as well, because right now we are in a test chip phase. We are collaborating with several customers, and guess what? We have 10 flavors for 10 customers. And developing those 10 flavors is neither cost-effective for them nor for us; it’s a lot of burden. In that sense, it’s not only optimizing our efficiency within what we provide to the customer. I think standards will also make it cost-efficient for them as well as for EDA vendors. It’s a win-win situation in that sense for all of us. Competition, in this case, is going to be working hand-in-hand, and once standards are in place it’s just only going to make it effective. That’s when it will go mainstream. Otherwise, for us, it’s not a repeatable and sustainable process from an EDA vendor perspective to support these 100 flavors and 100 ways.

SLD: What are the pieces of the 3D standards? What needs to be standardized? Chandrasekar: If you look at it just in the short term, I think we need standardized SPICE models for all the microbumps, through-silicon vias and you need some standardized approaches for validating your system-level connectivity, DRC and LVS. For the long term we also need to standardize the material set we actually use for the 2.5D and 3D design because there are too many variations right now. You can get an interposer from your foundry, you can get one from your OSAT and you get different underfill materials, there is so much variation even the EDA tools cannot handle the amount of what-if scenarios you might produce in this case.

SLD: How will the number of packaging options impact adoption of 3D? Bansal: Sematech is looking into that so we can do this what-if pathfinding in that area because—and whenever I’m talking about 3D-IC I always make it a point to say—it’s not only about IC optimization. It’s about IC and package optimization. If ultimately you design and optimize an IC and it sits on a package that was expensive, guess what? Your system cost is so huge you’re not going to make it. It has to be the entire system optimization and materials and all the things Karthik brought up. It’s very, very critical. I had dinner with a foundry and they raised a concern of yield and reliability that comes along with it because here comes one material’s property of the bump and here comes another. And then we are using their fab to put it together. But who is responsible for this? Finger pointing will happen. How do you manage around it? It seems we’ll get around the technical challenges in terms of tools. But this ecosystem definitely needs to be sorted out for us to make it mainstream, and this cooperation between the companies with standards has to happen both from a manufacturing perspective and from the tooling perspective.

SLD: How should we lay out the responsibilities between ecosystem players? Chandrasekar: That seems fairly confusing right now because different people want to be involved in different stages in the design. The foundries want to own the full turnkey model, and then if you look at OSATs they want to be involved in different stages of the design. There are big business implications. Robertson: In addition to standards and ecosystem, I’m really interested to see what falls out in terms of best practices that none of us can enforce but, as was already mentioned, you talk to 10 different companies with their strategy and their design flow is 10 different styles. You take a digital designer today and you put him in virtually any top 20 semiconductor company, the flow is going to look the same. This is how you go about timing closure. With analog and RF it’s a little bit different, but they pretty much fall into several methodologies. Literally today you have 10 different companies that will have 10 different approaches in terms of how they are going to do their design, model the TSVs, and timing approach. It’s all over the map. It’s going to be very interesting to see how this falls out into best practices because that’s going to help us drive what the flow is going to look like. Bansal: That’s the only way to make it repeatable and sustainable.