Hi Mike
How do you mean Intel is cooking the books? Are you suggesting their GM is higher than it appears? I remember reading an EET article saying their costs per wafer are three times as high as TSMC.

I agree with 3D guy for Intel standard merchant product. Where SOCs do present another question including for Intel.
For any standard product short run through five quarters of production requires a very volume high peak to see a marginal cost reduction for pulling down the full run average. Foundries may not be as product focused on the line. And how many see greater than 100 million unit runs?
On QUANTA for determining Intel marginal cost of production jury is still out on whether there actually is a cost reduction per millimeter square of dice area from Sandy Bridge to Ivy Bridge. Increased Ivy dice suggest there should be on Intel’s standard integration rule of no more than 10% increase in wafer cost per generation, although that rule has been broken many times in the past. Then the question arises whether or not there will actually be demand for that volume of Ivy supply? Also knowing Sandy oversupplied still floods the channels.
Ivy frequency distribution suggests Intel is fibbing on the ease of manufacturing trigate and this analysts suspects work overtime to make the sort above 2.4 GHz.
Finally having accelerated at 32 nanometer from a commercial industrial art into 22 nanometers applied science what are the real RISK development costs over production alone which this analyst suggests are high.
Intel annual financial won’t necessarily reveal the whole story where the books have been substantially cooked for a very long time. With a new generation of Haswell product in the mix, this analyst believes RISK production costs are more likely to rise than stay flat or decline.
Mike Bruzzone
Camp Marketing