Beyond UVM Registers — Better, Faster, Smarter

Adoption of SystemVerilog UVM is growing stronger. Verification teams are expanding their knowledge with respect to UVM features and capabilities. These verification teams are using the UVM Register layer with good success. But the UVM Register layer has many moving parts and intricate details. It can be difficult to adopt and it can be difficult to model complex registers. It is a complex system. In this paper we review the concepts behind the UVM Register package and try to think about creating a different kind of register model, one that achieves the same goals with much less detail and much less moving parts.