Method and apparatus for maximizing utilization of an internal processor bus in the context of external transactions running at speeds fractionally greater than internal transaction times

Posted at 11:00 am on 07/13/1999 by Dr. Rahul Razdan

Use of an
internal processor data bus is maximized in a system where external transactions
may occur at a rate which is fractionally slower than the rate of the internal
transactions. The technique inserts a selectable delay element in the signal
path during an external operation such as a cache fill operation. The one cycle
delay provides a time slot in which an internal operation, such as a load from
an internal cache, may be performed. This technique therefore permits full use
of the time slots on the internal data bus. It can, for, example, allow load
operations to begin at a much earlier time than would otherwise be possible in
architectures where fill operations can consume multiple bus time slots (Full Patent Here).