I'm sorry but this announcement isn't as exciting as it should be...maybe it's because I am not in a good mood today.
100G in a single optical module. This is all fine and good if you desire point-to-point communication only. Separating CPU, RAM and storage by using fiber links only invites disaster as you now have more componets that can fail and therefore MTTF goes down.
More importantly is when are the major router/switch box producers going to get involved? Did anyone talk with them? Without them, as far as I am concerned, this is pointless. Can you see Cisco, Juniper or Big Iron putting a PCIx16 card slot into their machines so that 100G switching/routing can occur? or even 4x25G?
This is where the explosion in the computing centers will occur. Without I/O to the world, the compute centers become data bound and do not need to expand their processing capacity.
I cannot see a switch using 4x25G ports unless multiple switches are run in parallel or one big switch with 4 fabrics. Four times the cost for implementing switching or wait for a re-designed switch. I'll wait.
On the other hand, I envision a complete redesign of switch fabric to take advantage of this 100G I/O. Can you say photonic fabric?
Now this would be an important and meaningfull announcement.

Hello Shmuel,
The answer to your question about the Intel Si Photonics module in the Open Compute Summit demo, based on the type of rack interconnect shown, is that it has four parallel 25G modulators driving four parallel single-mode fibers. This is the same approach as proposed for standardization in the IEEE 802.3bm 40 Gb/s and 100 Gb/s Fiber Optic Task Force by three companies (Avago, Luxtera, Oclaro), for up to 500m reach data center application, and referred to as PSM4 (parallel single-mode 4-channel). Each company showed the technical feasibility of this approach based on their internal and unique technology, both Si Mod and InP DML based. What they have failed to do so far is demonstrate that there is an economic advantage and broad market potential. Many end users, including carriers and some IDC operators prefer duplex SMF for longer reach applications. This is enabled by WDM, for example the existing IEEE LR4 standard, the 2010 Intel announcement, recent IBM IEEE proposal, the Kotura announcement (see link provided by Rick) which they proposed to the IEEE, and many others. It is therefore not clear why on this thread commenting about the Intel demo at the Open Compute Initiative, there is a detailed description of how to set the frequency of each color {wavelength}. Perhaps a technical conference paper about the earlier work accidently got into the Summit marketing package.

Another example of the announcement being light on content and heavy on marketing is the liberal use of adjectives to specify performance, instead of the more traditional numbers. For example, the modules are claimed to operate at “very low power levels”. At least for this spec we can quantify the adjectives because the modules were visible on the cards and had hefty heat sinks mounted on them. The heat sink size puts the module power dissipation above 3W, possibly 4W. This is similar to what other 100G board mounted optics dissipate today. (Also, earlier comment stated 4x15.2G for the 2010 announcement; it should have stated 4x12.5G).

The 2010 Intel announcement was a 4x15.2G WDM Muxed/Demux chip set that carried 50Gb/s per fiber. The announcement last week is no longer WDM, and only carries 25Gb/s per fiber, so that’s a drop in fiber capacity by a factor of 2x. This research has been going on for the past decade and the track record so far of commercializing technology is not great. If we extrapolate the trend, in 2014 there will be a big media event announcing a great new Si Photonics chip set which will carry 10Gb/s per fiber.
The announced 100G server to TOR switch application, based on Intel server roadmap, will not be need until 2017 and appreciable 100G server I/O volume won’t happen until 2020. So the good news is that gives 4 to 7 more years to iron out the bugs in the announced chip set. Unfortunately by then, 4x25G will not be the architecture of choice for I/O as the industry moves to 50Gb/s per lane and fiber. Perhaps better coordination with the guys that design products that pay the bills at Intel might help focus the photonics research towards something that would help the company.

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)

My Mom the Radio StarMax MaxfieldPost a commentI've said it before and I'll say it again -- it's a funny old world when you come to think about it. Last Friday lunchtime, for example, I received an email from Tim Levell, the editor for ...

A Book For All ReasonsBernard Cole1 CommentRobert Oshana's recent book "Software Engineering for Embedded Systems (Newnes/Elsevier)," written and edited with Mark Kraeling, is a 'book for all reasons.' At almost 1,200 pages, it ...