The purpose of the present invention is to provide a capacitance-to-voltage conversion circuit that makes it possible to maintain a capacitance-to-voltage conversion processing time, reduce power consumption, and reduce noise. In synchronization with two consecutive sampling periods of a first sample-and-hold circuit (12), a second sample-and-hold circuit (14) simultaneously samples and holds, in a second capacitive element (Cout3), the positive-phase output voltage (VOp) and negative-phase output voltage (VOn) of a differential amplifier (15), which are sampled and held by the first sample-and-hold circuit (12). Next, in a separate sampling period, the second sample-and-hold circuit (14) connects the second capacitive element (Cout3), which has accumulated charge in advance, to a positive-phase capacitive element (Cout1) and negative-phase capacitive element (Cout2) of the first sample-and-hold circuit (12) immediately before the positive-phase and negative-phase capacitive elements (Cout1, Cout2) are held at a desired level. At this time, the load capacitance connected to the output of the differential amplifier (15) is increased and a band is narrowed.