Translation of abstract (English)

Within this doctoral thesis work, major parts of the preamplifier and readout chip HELIX128-2 have been developed. Among others these circuits included the 'Bias Generator' part, which uses digital-to-analogue converters to provide bias currents and control voltages for the amplifier stages of the chip, and a serial interface for programming all the chips operational parameters. Furthermore, a complete characterisation of the chip, also under irradiation with a 137Cs-source was performed. Deficiencies found during the necessary tests and measurements resulted in an improvement of the chip within several revision steps: 2.2, 2.3, 3.0, 3.1 and 3.1a. The modifications required therefore, included all parts of the circuit, except for the frontend and multiplexer. Especially the pipeline r/w logic control has been improved within this work. HELIX128-2 is a low noise VLSI readout chip for 128 channels of silicon strip detectors or MSGCs (ENC = 462e+35.4e/pF for a new chip and 571e+52.0e/pF$ at 3.9kGy). Its architecture implements besides an analogue readout path similar to the CERN RD20/FElix chip (Charge sensitive preamplifier, shaper, analogue memory and serial readout of a triggered samples' channel data) also an undelayed binary readout path. The latter is intended for trigger applications and uses individual comparators following each channel's frontend, and a combination of their data in groups of four channels. The two parts of this thesis are: A description of the HELIX128-2 with a special emphasis on the circuits' implementation. The second part presents the characterisation results of the chip including the chip performance after irradiation doses up to 3.9kGy.