Hardware

Although the AT93C46 EEPROM is connected to the FTDI chip, the device uses default FTDI VID:PID information.

The use of an USB A connector on the device's side is unfortunate, as it requires a special A to A cable.

The probes are easy to identify, as they are colour coded.
There are four groups with white, blue, yellow, and green (data, clock) and black (ground) heat shrunk sleeves with 8 + 1 (+ 1) wires each.
Individual wires have black to purple (eight data lines), gray (the group's ground), and white (clock in the blue and green groups) isolation.
The vendor software reflects the D0-D31 and CLK1, CLK2 names and the colour coding in the UI.

Capabilities

The device can sample 34 channels at a rate of up to 500MSa/s in timing mode (internal clock).

In sample mode CLK1 and CLK2 can be used to control the data acquisition. The sample rate can be up to 200MHz.
Optionally acquisition can be "gated" (like using a chip select).
Clock skew can get adjusted, to cater for rise and hold times.
Unused clock lines can be used (get acquired) like regular data lines.

Although sample memory is rather constrained (FPGA block RAM exclusively, no external memory attached), compression is quite effective.
Compression is available at sample rates up to 200MHz.
Every other of up to 2K "slots" can communicate a period of unchanged signals of arbitrary duration, referring to the preceeding slot.
Which translates to up to 1K transitions over an extended period of time, sampled at a rate of up to 200MHz.
In practice this implementation allows surprisingly successful use of the device in more situation than one would expect.

TODO trigger capabilities, two conditions A and B, either A or B, or A then B (or none, of course), logic as well as edges, counters, phew :)

Operation

Startup

The onboard FPGA does not feature non-volatile memory for bitstream retention,
therefore, in order for the device to become operational,
a bitstream must be uploaded from the computer first.
This occurs via the FTDI USB interface:
A series of FT245BL command bytes
facilitates bit-banging an SPI-like protocol
on the traces between FT245BL and FPGA,
which effectively results in a bitstream upload to the FPGA.

A pre-arranged command byte sequence may be extractable
from the offial LogicPort software(1) specifically the file LogicPort.ccf:
The byte sequence after the one-line header ending on 0x0D 0x0A
looks very similar to the cold boot transmission
observed below
using the official software.

Warning: Uploading an incompatible or damaged bitstream or incorrectly uploading it can permanently damage the FPGA!

TODO: (gsi's opinion) Re-consider the validity or severity of the above warning.
According to this reasoning we should warn users to use any device that firmware gets loaded into.
Strictly speaking FPGA based devices are even more robust in that respect compared to MCUs,
since incomplete upload procedures won't take effect at all, damaged netlists won't take effect
(FPGA configuration is checksummed, which MCU firmware download usually is not),
downloading netlists that were created for a different chip won't take effect (caught in hardware, too),
and any version of vendor's published netlists should be safe to load.
Using unsupported features of a netlist, or emitting inappropriate commands
at runtime after loading the netlist is a different matter, but equally applies
to any other FPGA or MCU based device, and is not what the above warning was about.
Only the creation and use of self-made netlists without the vendor's help would qualify
for the above warning, but that should be well understood, and shall not apply to either
this specific LA model or any other sigrok supported FPGA based device (compare this to FX2).