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2 Semi Networking Day Christophe Fitamant Sales & Marketing Director, Yole Développement Christophe Fitamant joined Yole Développement in 2013 to lead Média and Sales activities. He holds an engineering degree of INP Grenoble - Phelma - with a major in Chemical Process Engineering. He has worked at IBM Corbeil-Essonnes, and Applied Materials. He s lived in California when he managed the Applied etch product support group for Taiwan and Japan. Back to France for Lam Research he first took the responsibility of the ST Crolles site, before taking the Sales Account Management for Europe. With the acquisition of SEZ in Austria by Lam in 2008, he led Sales and Marketing for Lam penetration in MEMS and Advanced Packaging for Clean Copyrights Yole Développement SA. All right reserved.

3 Fields of Expertise Yole Developpement is a market, technology and strategy consulting company, founded in We operate in the following areas: Photovoltaic Power Electronics Microfluidic & Med Tech Advanced Packaging Our expertise is based on research done by our in-house analysts, conducting open-ended interviews with most industry players. 30+ full time analysts with technical and marketing degrees Primary research including over 3,500 interviews per year HB LED, LED & LD Equipment and materials MEMS & image sensors

5 Semi Networking Day Rozalia Beica Chief Technical Officer, Yole Développement Rozalia Beica is the CTO and Business Unit Manager leading Advanced / 3D Packaging and Semiconductor Manufacturing activities within Yole Développement. For more than 15 years she has been involved in research, strategic marketing and application of WLP and 3D/TSV at materials (Rohm and Haas), equipment (Semitool, Applied Materials, Lam Research) and device manufacturing (Maxim IC) organizations. Rozalia has authored over 50 papers and publications and she is actively participating in several 3D & Advanced Packaging Committees worldwide. Rozalia holds a M.Sc. in Chemical Engineering (Romania), a M. Sc. In Management of Technology (USA) and a GXMBA from IE University (Spain) Copyrights Yole Développement SA. All right reserved.

8 Introduction The evolution of semiconductor packaging technologies over the past 40 years has been driven by the need to bridge the increasing I/O interconnect gap, between the fast decreasing silicon geometries (Moore s law) and the slower shrink of the Printed Circuit Board technologies Wafer-level-packaging market is gaining more and more significance in the semiconductor industry; it shows the greatest potential for significant future growth in the semiconductor industry. Historically supported by the market growth in flip-chip wafer bumping with electroplated gold, solder bumps and today copper pillars; wafer-level-packages are actually coming in many different, namely Fan-in WLCSP packages, 3D WLP, FO WLP packages, 2.5D Glass / Silicon interposers and of course 3DIC integration with TSV interconnects

11 WLP Middle-End Technologies Wafer level packages are true Middle-end technologies, leverage similar type of process manufacturing know-how Middle end technologies are found in the overlap area between the IDMs or CMOS foundries backend of line (BEOL) wafer fabs and the the back-end wafer bumping assembly facilities of the OSATs and wafer bumping houses Middle-end vs Front-End vs Back-End FE wafer manufacturing PVD CMP implant etch inspection cleaning CVD Wafer test TSV RDL / wiring Middle-end Courtesy of Stats ChipPAC BE assembly & test dicing handling thinning BGA C2C / C2S bumping inspection W2W C2W underfill molding Final test Middle-end is a strategic area where Foundries, OSATs, WLP Houses and IDMs stepped in, an infrastructure that has emerged by itself in the last 5 years. Middle-end infrastructure is growing and is the leading driver and the fastest growing semiconductor packaging technology with more than 18% CAGR in units over the next 6 years

17 Market Trends The move to embedded wafer-level-packages Embedded wafer-level-packaging technologies are not new Several players, such as Freescale with RCP, Infineon with ewlb, and Ibiden for die embedding into PCB laminated substrates have developed dedicated technologies and have processed IP in this area for years. Benefits of embedded package integration include: Miniaturization, electrical and thermal performance improvement, cost reduction and simplification of logistic for OEMs 1 st -generation ewlb cross-section (Courtesy of Infineon) Embedded die ibga package (Courtesy of Imbera/Daeduck) Multi-chip SiP Module based on Chip Embedding technology (Courtesy of AT&S) Integrated passive IC ready for embedding into PCB laminate (Courtesy of NXP/FCI)

20 FOWLP Cost Motivation to Continue Die Shrinkage! Fan-in WLCSP Wireless SOC 90nm Next CMOS generation Fan-Out WLP PCB 0.5mm pitch Wireless SOC 45nm FC-CSP, WB/FC-BGA PCB 0.5mm pitch Wireless SOC 65nm Next CMOS generation PCB 0.4mm pitch Smaller die size Lower front-end cost thanks to more advanced lithography No more interposer substrate/micro-bumps/wb RDL on Fan-Out area provided are sufficient! Higher functionality when moving to Combo(s) Same or even higher pin-counts are possible PCB mother-board need to remain cheap Pitch evolution is typically limited to mm Filling the I/O gap between IC and PCB evolution Some restrictions are appearing at the package level, since global chip trends tend toward smaller chip areas with an increasing number of interconnects: so the shrinkage of the pitches and pads at the chip/package interface is happening much faster than the shrinkage at the package/board. As a result: FC-CSP, WB/FC-BGA package cost is increasing fast with I/O density (mainly due to interposer substrate cost) Fan-in WLCSP are substrate-less but face inherent limitations due to available die area for re-routing Fan-out WLP has the potential to realize any number of interconnects with standard pitches at any shrink stage of the wafer node technology

21 FOWLP Thickness Motivation WB-BGA 0.8mm PMU chip Fan-Out WLP PMU chip 0.55mm PCB 0.5mm pitch PCB 0.5mm pitch I/O pads are all located at the center of the die Front-end IC design constraint! Issues are: package height (necessary for Wire- Bonds) and thermal dissipation (flip-chip packages would be better) No Wire-Bond Lower package height Better heat dissipation FC configuration No more interposer substrate/micro-bumps/wb RDL on Fan-Out area provided are sufficient! Meeting with new form factor and package performance Some specific Power Management Units (PMU) have > 120 I/Os pads, all located at the center of the PMU chip due to specific IC design reasons. Using Wire Bonds takes a lot of height to connect the chip to the UFBGA substrate Move to FC-BGA/FOWLP First simulations show that electrical performance and heat dissipation are expected to be better than WB-BGA/FC-BGA configurations (please see next slides)

23 First ewlb Package in High-Volume Production! First design win for ewlb In early 2009, Infineon (GE) was the first company to commercialize its own ewlb packaging technology in an LGE cell-phone ASE and STATSChipPAC are qualified as subcontractors for ewlb manufacturing Infineon s chip is a wireless baseband SOC with multiple integrated functions (GPS, FM radio, BT) The same ewlb product is in production in some Nokia handsets since 2010 The first ewlb package with Infineon s wireless Baseband SOC was found in an LG cellphone (Reverse Engineering pictures courtesy of SystemPlus Consulting and Binghamton University )

25 Price per pin (c$) FOWLP Cost Model (2012 Data Update) FC BGA QFN WL CSP 300mm FOWLP double RDL 300mm FOWLP single RDL WB-BGA Pin count # FOWLP is now a lower-cost package platform than any competing flip-chip solution The FOWLP cost position ( $/IO) is a clear advantage compared to flip-chip packages today However, the application window is still quite narrow (between IOs only) and there s strong restriction in terms of chip to package IC co-design environment only a few companies are mature enough to design their chip/package for FOWLP at this early stage

26 FOWLP Cost Analysis Conclusion There is no barrier to entry for FOWLP from the end-user perspective, as it is estimated that FOWLP manufacturing cost will be reduced by 2-2.5x in a five-year time frame between , thanks to several different factors: FOWLP Cost/die* $0.5 $ mm FOWLP Yield, test and productivity of FOWLP lines will rapidly increase with time Production volume will increase dramatically with time Depreciation of the infrastructure with time New infrastructure will emerge for PANEL 300mm FOWLP * for a reference scenario FOWLP manufacturing using Gen2 LCD display old fabs $0.20 $ x Cost reduction! PANEL FOWLP 470mmx370mm

29 No. of Patent Families Overall Trend of Patent Filing in the Domain Preliminary remark: for all of the evolution charts, the data corresponding to the years 2010 and 2011 may not be complete, since a significant number of patent applications filed during those years might not have been published yet Patent filing trends for FOWLP technologies Yole Developpement July Priority Years The FOWLP technological area has picked up significantly only in recent years, coinciding with the need to meet future device packaging requirements

30 Evolution of Top 10 Assignees for FOWLP Patents Evolution of top 10 assignees for FOWLP patents (includes related and relevant) ACE (TW) Yole Developpement July INFINEON (GE) SAMSUNG (KR) STATS CHIPPAC (SG) TESSERA (USA) Priority Years Up to Bubble size represent number of Patent Families ASE (TW) FREESCALE (USA) MICRON (USA) MEGICA (TW) QIMONDA (GE) In recent years (i.e. from 2005), most players have increased their focus on innovation Exceptions: Tessera and Micron, whose filings in the last few years have decreased

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