Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors.

a first capacitor including a first plate, a second plate, and a fexoelectric material disposed between ie first and second plates, the first plate coupled to plate line structure; a second capacitor including a first plate, a second plate, and a ferroelectric .materia! disposed between the first and second plates, the first plate coupled to the plate line structure;

a first transistor vertically displaced relative to the first capacitor and coupled to the second plate of the first capacitor; and

a second transistor vertically displaced relative to the second capacitor and coupled to the second plate of the second capacitor.

2. The apparatus of claim 1 wherein the first transistor includes a first semiconductor pillar extending from the second plate of the first capacitor and the second ■transistor includes a second semiconductor pillar extending from the second plate of the second capacitor.

3. The apparatus of claim 2 wherein the first transistor includes a channel region within th first semiconductor pillar and source/drain regions included in the first semiconductor pillar.

4. The apparatus of claim 1 wherein the first transistor includes a first semiconductor pillar disposed between the second plate of the first capacitor arid a digit line.

5. The apparatus of claim 1 wherein the first transistor and the second 'transistor are vertically displaced relative to one another.

6. The apparatus of claim 1 wherein the first plates of the first and second capacitor share a common composition with the plate line structure.

7. Th apparatus of claim 1 wherein the first transistor and the second transistor are laterally displaced relative to one another.

8. The apparatus of claim 1 wherein the first and second transistors are in a common horizontal plane and the first and second, transistors isiclude respective gates along a word line that extends along the horizontal plate.

9. The apparatus of claim 1 wherein the first transistor and the first capacitor are Included in a first memory' cell and the second transistor and the second capacitor are included in a second memory cell, and wherein the first and second capacitors are vertically displaced relative to one another and wherein the plate line structure is shared by die first and second memory cells.

10. An apparatus, comprising:

a first memory cell; and

a second memory cell;

wherein each memory cell comprises:

a first transistor;

a first ferroelectric capacitor including a ferroelectric material, coupled to the first transistor and vertically displaced relative to the first transistor;

a second transistor; and

a second Ferroelectric capacitor coupled to the second transistor and vertically displaced relative to the second transistor.

1 1. The apparatus of claim 1.0, further comprising".

a plate line structure shared by the first and second memory cells.

12. The apparatus of claim 11 wherein the first and second memory cells are laterally displaced relative to one another.

13. T e apparatus of claim 10 wherein the first and seecmd memory cells are vertically displaced on opposing sides of one of a plate line structure shared by the first and second memory cells or a digit line shared by the first and second memory cells.

14. The apparatus of clam 10, further comprising:

a first digit line shared by the first and second memory ceils; and

a second digit line shared by tire first and second memory ceils.

15 , The apparatus of claim 10„ fiallier cofriprismg:

a first 4igit lin shared b the first and second memory ceils;

a second digit line coupled to the first memory cell; and

a third digit line coupled to the second memory cell.

16. An apparatus, comprising:

a first ferroelectric capacitor including first and second plates;

a second ferroeleciric capacitor including first and second plates, wherein the first and second ferroelectric capacitors are vertically displaced relative to one another;

a first transistor including a first semiconductor pill r coupled to the second piate of the first ferroeleciric capacitor and disposed between the first capacitor and a first digit line; and

a second transistor including a second semiconductor pillar coupled to the second plate of the second ferroelectric capacitor and disposed between the second capacitor and a second digit line.

17. The apparatus of claim 16 wherein the first and second digit lines are in a common horizontal plane.

18. The apparatus of claim 16, further comprising:

a third transistor including a third semiconductor pillar coupled to the First plates o the first and second capacitors and disposed between the first and second capacitors and a plate line structure.

19. The apparatus of claim 18 wherein the third semiconductor pillar has a different dimension for of at least one of a channel length or a channel width.

20. The apparatus of claim 18 wherein the third transistor is vertically displaced relative to the first and second transistors.

21. The apparatus of claim 20 wherein the third transistor is above the first and second transistors.

22. The apparatus of claim 20 wherein the third transistor is below the first and second transistors.

23. The apparatus of claim 1 . further comprising:

a third- transistor including a third semiconductor pillar coupled to the first plate of the first capacitor and disposed between the first capacitor and a plate line structure; and a fourth transistor including a fourth semiconductor pillar coupled to the first plate of the second capacitor and disposed between the second capacitor and -the plat line structure.

24. An apparatus, comprising:

a first capacitor including first and second plates, and further including a ferroelectric material disposed between the first and second plates;

a second capacitor including first and second plates, and further including a ferroelectric material disposed between the first and second plates; a first vertical transistor di sposed between the second plate of the first capacitor and a first digit line;

a second vertical transistor disposed between the second plate of the second capaci tor ami a second digit line; an d

a third vertieal transistor disposed between the first plates of the first and secoiid capacitors and a plate line structure, wherein the third vertical transistor is vertically displaced from the first and second vertical transistors.

25. The apparatus of claim 24 wherein the first and second transistors are in a common horizontal plane,

26. The apparatus of claim 24, further comprising:

a first word line including gates of the first and second transistors; and

a second word line including a gate of the third transistor.

27. The apparatus of claim 26 wherei the first word line extends along a first horizontal plane and the second word line extends along a second horizontal plane that is vertically displaced from the horizontal plane of the first word line,

28. The apparatus of claim 24 wherein first and second capacitors, and the first, second, and third vertical transistors are included in a first memory cell, and wherein the first and second digit lines are shared .with a second memory cell over which the first memory cell is stacked,

29. The apparatus of claim 24 wherein first and second capacitors, and .the first, second, and third vertical transistors are included .in first memory cell, and wherein the plate line structure is shared with a second memory cell over which the first, memory cell is stacked. 30, An apparatus, comprising;

a firs ferroelectric capacitor including first and second plates;

a second ferroelectric capacitor including first and second plates;

a first vertical transistor disposed between the second plate of the first ..ferroelectric capacitor and a first digit Sine;

a second vertical transistor disposed between the first plate of the first ferroelectric capacitor and a plate line structure, wherein the first vertical transistor is vertically displaced if om the second vertical transistor;

a third vertical transistor disposed between the second plate of the second ferroelectric capacitor and a second digit line; and

a fourth vertical transistor disposed between the first plate of the second ferroelectric capacitor and the plate line structure,, wherein the third vertical transistor is vertically displaced from 'the 'fourt vertical transistor.

31 , The apparatus of claim 30 wherein the first, second third, and fourth vertical transistors are in a common vertical plane.

32, The apparatus of claim 30 wherein first and third vertical transistors are in a first common horizontal plate as one a o he and the second and fourth vertical transistors are i a second common horizontal plane as on another.

33, The apparatus of claim 32 wherein the first common horizontal plane is •vertically displaced from the second common horizontal plane .

34, The apparatus of claim 32, further comprising a word line including gates of the first and third transistors, wherein the word Hn extends along the first common horizontal plane.

35, The apparatus of claim 30 wherein first and second ferroelectric capacitors, and the first, second, third, and fourth vertical transistors are included irt first memory cell, and wherein the first and second digit lines are shared with a second memory cell over whkh the first m mor cell is stacked,

36. T e apparatus of claim 30 wherein first -and second ferroelectric capacitors^ and the first, second, third, and fourth vertical transistors are included in a first memory cell, and wherein the plate line structure is shared with a second memory cell over which the first memory cell is stacked.

37. The apparatus of claim 30 wherein each of the first, second, third, and fourth transistors comprises:

a semiconductor pillar;

a gate dielectric material;

a channel region in the semiconductor pillar; and

source/drain regions in the semiconductor pillar.

38. A method of accessing a memory cell, comprising;

activating first and second transistors of the memory cell;

applying a voltage to a plate line coupled to first and second ferroelectric capacitors, the first ferroelectric capacitor coupled to the first transistor and vertically displaced relative to the first transistor and the second ferroelectric capacitor coupled to the second transistor and vertically displaced relative to the second transistor; and

comparing a first voltage developed at a first digit line coupled t the first ferroelectric capacitor to a second voltage developed at a second digit line coupled to the second ferroelectric capacitor.

Description:

FERROELECTRIC MEMORY CELLS

CROSS-REFERENCE TO RELATED APPLICATION

1 This application claims the filin benefit of U.S. Provisional Application No. 62/381,942, filed August 31, 2016. This application is incorporated, by reference herein in its entirety and for all purposes.

BACKGROUND

I Memory devices are widely used to store information in various electronic devices such as computers, wireless communication .devices, cameras, digital displays, and. the like, information is stored by programing different states of a memory device. For example, binary devices have two states, often denoted by a logic "1 " or a logic "0." In other systems, snore than states may be stored. To access the stored information, the electronic device mm read, or sense, die stored state in the memory device. To store information, the electronic device may write, or program., the state in the memory device. ] Various types of memory devices exist, including- ra dom access memory (RAM), read only memor (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRA ), magnetic RAM (M.RAM), resistive RAM (RRAM), flash memory, and others. Memory devices may be volatile or non-volatile. Non-volatile memory,, e.g„, flash. memory, can store data for extended periods of time even in the absence of an external power souree> Volatile memory devices, e.g., DRAM, may lose their stored state over time unless they are periodically refreshed b an external power source. A binary memory device may, for example, include charged or discharged capacitor, A charged capacitor may, however, become discharged ove tim through leakage currents, resulting in 'the loss of the stored information. Certain features of volatile memory ma offer performance advantages, such as faster read or write speeds, while features of non-volatile memory, such as the ability to store data without periodic ref eshing, may be advantageous, |00 | FeRAM may use similar device architectures as volatile memory but. may have non-volatile properties due to the use of a ferroelectric capacitor as a storage device. FeRAM devices may thus have improved performance compared to other non-volatile and volatile memory devices. It is desirable-, howe er, to improve the operation of -FeRAM devices. For example, it may be desirable to have improved nois resistance during .memory cell sensing, more compact circuits and reduced layout size, -and improved timing for operation of FeRAM devices.

SUMMARY

|®05] Apparatuses including ferroelectric memory cells and methods for accessing a memory cell are described. An example apparatus includes first and second capacitors, and first and second transistors. The first capacitor includes a first plate, a second plate, and a ferroelectric material disposed between the first and second plates, the ' firs plate coupled to a plate hue structure. The second capacitor includes a first plate,, a second plate, and a ferroelectric material disposed between the first and second plates, the. first plate coupled to the plate line structure. The first transistor is vertically displaced relative, to the first capacitor and coupled to the second plate of die .first capacitor. The second transistor is vertically displaced relative to the second capacitor and coupled to the second plate of the second capacitor.

|0O6| Aii example method includes activating first and second transistors of the memory cell and applying a voltage to a plate line coupled to first and second ferroelectric capacitors. The first ferroelectric capacitor is coupled to the first transistor and vertically displaced relative to the first transistor, lite second ferroelectric capacitor is coupled to the second transistor and vertically displaced relative to the second transistor. A first, voltage developed at a first digit line coupled to the first ferroelectric capacitor is compared to a second voltage developed at a second digit line coupled to the second ferroelectric capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

|007J Figure 1 is a block diagram of an example memory array that supports ferroelectric memoiy in accordance with various embodiments of die present disclosure.

|008| Figure 2 A is a schematic diagram of an example circuit that includes a column of memory cells according to an embodiment of the present disclosure. Figure 2B is a schematic diagram of a sense component according to an embodiment of the disclosure.

(009] Figure 3 A and Figure 3B are diagrams of example non-linear electrical, propertie for a ferroelectric memory cell in accordance with va ious embodiments of the present disclosure.

fUlCiJ Figure 4A is a schematic diagram of example- memor cells including two tottststors and two capacitors according t an embodiment of the disclosure.

JultJ Figure 4B is a diagrammatic cross-sectional side view of a region of an example memor arra showing example memor cells including two transistors and two capacitors according to an embodiment of the disclosure.

0J2| Figure 5A is a- schematic- diagram of example memory ceils including two transi stors and two capac itors according to an embodiment of the disc losure .

(013 J Figure SB is a diagrammatic cross-sectional side view of a region of an example memoiy array showing example memory cells including two traasistors and two capacitors according to an embodiment of the disclosure.

|014| Figure 6A is a schematic diagram of example mem y' cells including two transistors and two capacitors according to an embodiment of the disclosure.

fOlS] Figure 6B is a diagrammatic cross-sectional side view of a region of an example memor arra showing example memory cells including two transistors and two capacitors according to an embodiment of the disclosure.

}016 Figure ?A is schematic diagram of example memory cells including two transistors and two capacitors according to an embodiment of the disclosure.

[017 j Figure 7B is a. diagrammatic cross-sectional side vie of a region of an example memory array showin example memory cells including two transistors and two capacitors according to an embodiment of the disclosure. 018| Figure 8A is a schematic diagram of example memory cells including two transistors and two capacitors according, to an enibodi merit of the disclosure,

|019| Figure SB is a diagrammatic cross-sectional side view of a region of an example memory array showing example memory cells including two transistors and two capacitors according to an embodiment of the disclosure.

[Q ] Figure 9A is a schematic diagram of example memory cells including three transistors and two capacitors according to an embodiment of the disclosare.

|02l| Figure 9B is a diagrarnmatic cross-sectional side view of a region of an example- memory array showing example memory ceils including three transistors and two capacitors according to a embodimen t of the disclosure.

j¾22} Figure 1 A is a schematic diagram of example memory- ceils including three transistors and two capacitors according to an embodiment of the disclosure,

}023 | Figure I OB is a diagrammatic cross-sectional side view of a region of an example memory array showing example m mory cells including three transistors and two capacitors according to an embodiment of the disclosure.

102.41 Figure 11A is a schematic diagra of example memory cells including four transistors and two capacitors according to an embodiment of the disclosure.

|025| Figure I I B is a diagrammatic cross-sectional side view of a region of an example memory array showing example memory- cells including four transistors and two capacitors according to an embodiment of the disclosure,

}§2&f Figure 12A is a . schematic diagram of exampl memory - cells including four transistors and two capacitors according to an embodiment of the disclosure.

}(t27} Figure 128 is a diagrammatic cross-sectional side view of a region of an example memory array showing example .memory cells including four transistors and. two capaci tors according to an embodiment of the disclosure.

(028| Figure I S A is a schematic diagram of example memory cells including four transistors and two capacitors according to an embodiment of the disclosure. |02 | Figure 138 is a diagrammatic cross-sectional side view of a region of an example memory array showing example memory cells including four transistors and two capacitors according to an embodiment of die disclosure.

|030J Figure 14 is a block diagram of a memory arra that supports a ..ferroelectric memory in accordance with various embodiments of the present disclosure,

|031| Figure 15 is a block diagram of a system that supports a ferroelectric memory in accordance with various embodiments of the present disclosure.

DETAILED DESCRIPTION

|03¾| Certain details are set forth below to provide a. sufficient understanding of embodiments of the disclosure. However, it will be clear to one skilled in the art that embodiments of the disclosure may be practiced without these particular details. Moreover, the particular embodiment of the present disclosure described herei are provided by wa of example and should, net be used to Hmit the scope of the disclosure to these particular embodiments. In other instances, well-known, circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the disclosure.

|ft33| Figure 1 .illustrates art example memory array 10 that supports ferroelectric memory in accordance with various embodiments of the present disclosure. Memory array 10 may also be referred to as art ' electronic memory apparatus. Memory array 1.0 includes memory cells 105 mat. are programmable to store differen states. Each state may represent different logic values. For example, for a memory storing two states, the logic values may be denoted as a logic 0 and a logic 1. In some cases, memory cell 105 is configured to store more than tvvo logic values. A memory cell 105 m include a piumliiy of capacitors to store a charge representative of the programmable states. For example, charged arid uncharged capacitors may represent two logic values, respectively,

| Operations such as reading and writing may he performed on m mor' cells 105 by •activating -Or selecting the appropriate access lines 12 and digit lines 15. Access lines 12 may also be ' .referred to as word lines .12. Activating or selecting a. word line 12 or a digit line 15 may include applying a voltage to the respective line. Word line 12 and digit Sines 15 are nmde of conducti ve materials. For example, word lines 12 and digit lines 15 may be made of metals ' (such as ' copper, aluminum, gold, tungsten, etc.), metal alloys, doped semiconductors, other conductive materials, or the like. According to the example of Figure 1, eac row of memory ce lls 105 is coupled to a word line .12 WL, and eac column of memory cells 105 is coupled to digit lines 15 BL-T and BL-C. By activating the respective word lines 12 and digit lines 15 (e.g., applying a voltage to the word lines 12 or digit lines 15), a memory cell 105 may be accessed at their intersection. Accessing the memory cell 105 may include reading or writing the memory celt 105. The intersection, of a word lines 12 and digit lines 15 may be referred to as an address of a memory cell.

J In some architectures, the logic storing device of a cell, e.g., capacitors, may be electrically isolated from the digit lines by selection components. A word line 12 may be coupled to and ma control the selection components. For example, the selection components may be transistors and the word Ike 12 may be coupled to the gates of the transistors. Activating the word line 12 results in an electrical coupling or closed circuit between the capacitors of a memory cell 105 and corresponding digit line 15. The digit lines may then be accessed to either read or write the memory cell 105.

} Accessing memory: cells 105 may be controlled through a ro decoder 20 and a column decoder 30. I some examples, a row decoder 20 receives a ro address from the memory controller 40 and activates the appropriate word lines 12 based on the received • row address. Similarly, a column decoder 30 receives a column address from the memory controller 40 and activate the appropriate digit lines 15. For example, memory array 1.0 may include multiple word lines 12, and multipl digit lines 15. Thus, by activating word lines .12 WL and digit lines 15 BL-T and BL-C, the memory cell 105 at their intersection may be accessed

|Θ38| Upon accessing, a memory ceil 105 may be read, or sensed, by sense component 25 to determine the stored state of the me-rttory cell 105, For example, after accessing the memory cell 105, the ferroelectric capacitors of memory cell 105 may discharge onto corresponding digit lines 15.. Discharging the ferroelectric capacitors may be based on biasing, or applying a voltage, to the ferroelectric capacitors. The discharging may cause a change in the voltage of the digit lines 15, which sense componen 25 may compare to a reference voltage (not shown) in order to determine the stored state of the memory cell. 105. For example, if a digit line .15 has a higher voltage than the reference voltage., then sense component 25 may determine that the stored state in memory ceil 105 is a logic 1 and vice versa. Sense component 25 may include various transistors or ■ am lifiers in order to detec (e.g., compare) sad amplify a difference in the signals, which ma include latching the amplified difference. A. separate sense component 25 may- be provided for each pai of digit lines BL-T and BL-C. The detected logic state of memory cell 105 may then ' be. utput throug column decoder 30 as output 35.

£639} A memory cell 105 may be programmed, or written, by activating the relevant word lines 12 and digit lines 15. As- discussed above, activating wor Sines 12 couples the corresponding row of memor cells 105 to their respective digit lines 15, B controlling the relevant digit lines 15 while the word lines 12 are activated, a memory cell 105 .ma be written— e.g., logic valise may be stored in the memory cell 105. Column decode 30 may accept data, for example input 35, to be written to the memory cells 105. A ferroelectric memory cell 105 may be written by- applying- a voltage across the ferroelectric capacitor. This process is discussed -in more detail below.

|Θ 0| in some memory architectures, accessing the memor ceil 105 may degrade or destroy the stored logic state, and re-write (e.g., restore) operations may be performed to return the original logic state to memory ceil 105. For example, the capacitors may be partially or .completely discharged during a sense operation, corrupting the stored logic state. So tire logic state may be re-written after a sense operation. Additionally, activating word lines .52 may result in the discharge of all memory cells in the row. Thus, .several or all memory cells 105 in the row may need to be re-written.

I The memor controller 40 may control the operation (e.g., read, wife, restore, etc) of memory cells 105 through the various components, such as row decoder 20, column decoder 30, and sense component 25, Memory controller 40 may generate row and column address signals in order to activate the desired word lines 12 and digit lines 15. Memory controller 40 may also generate and control various voltage potentials used during the operation, of memory arra 10. in general, the arnphtode, shape, or duration of an applied voltage discussed herein may be adjusted, or varied and may be different for the various operations for operating memory array HI. Furthermore, one, multiple, or all memor cells 105 withiti memory array 10 may be accessed simultaneously. For example, multiple or all cells of memory array 10 ma be accessed simultaneously during a reset operation in which all memory cells 105, or a group of memory cells 105, are set to a single logic state.

j Figure 2A illustrates ail example csrcuir. 20 that includes a. column of memory cells according to an embodiment of the present disclosure. Figure 2 illustrates an example circuit 20 thai includes memory cells 105 i -accordance with various embodiments of the present disclosure. Circuit 20 includes memory cells 105 MC(0)- €{n), where depends on the array size. The circuit 20 further includes word lines WL(0)-WL(n}, digit lines BL-T and BL-C, and sense component.25, The digit line BL-T is coupled to- a sense node A of the sense component 25 and the digit line BL-C is coupled to a sense node B of the sense component 25. The word lines, digit lines, and sense component may be examples of memory cells 105, word lines 12, digit lines 15, and sense component 25, respectively, as described with reference to Figure 1. While one column, and n rows of memory cells 105 are shown in Figure 2A, a memor array may include many columns and rows of memory cells as those shown.

j Memory ceils 103 may include a logic storage component, such as capacitors and selection components (not shown i Figure 2A). The capacitors of the memory cells 105 may be ferroelectric capacitors. The isoelectric capacitors may not discharge upon coupling to digit lines BL-T and BL-C, As previoiisly described, various states may be stored by charging or discharging the capacitors of the memory cell .1 OS. The selection components of memory cell 105 may be activated by a respective word line W L. Each of ■ the memory cells 105 is coupled to a plate line CP that may be used ' during access of the memory ceils 105.

I The stored state of a memory cell 105 may be read or sensed by operating various

■ elements represented in circuit 20. Memory cell 105 may be in electronic communication with di it Hues BL-T and BL-C. For example, as will be described in more detail below, capacitors of the memory cell .105 can be isolated from digit lines BL-T and BL~C when selectio components of the memory cell 105 are deacti vated, and the capacitors can be coupled to digit lines BL-T and BL-C when selection components are activated. Acti vating -selection components of the mem ry ceils 105 may be referred to as selecting memory cell 105. In some cases, selection components ate transistors and the operation is controlled by applying voltages to the transistor gates, where die voltage magnitud is greater than the threshol voltage of the. transistors. Word lin WL may activate the selection components. For example, a voltage applied to word line WL is applied to the transistor gate of the selection components of the memor celt 105. As a result, the capacitors of the selected memory cell 105 are coupled to digit lines BL-T and BL-C, respectively. Word lines WL(0)-WL(n) are ta electronic communication with selection components of memoiy cells 3 5 yC(0)-MC(n), respectively. Thus, activating the word line WL of a respective memory cell 1 5 may activate th memory cell 05. For example, activating WL(G) activates memory cell MC(O), activating WL(1} activates memory ceil MC(!), and so on.

I To sense the logic value stored by a memory cell 105, the word line WL may be biased to select a respective memory cell 105, and a voltage may be applied to the plate line CP. Biasing the plate line CP may result in voltage difference across the capacitors of a memory cell 105, which may yield a change in the stored charge on the capacitors. The magnitude of the change in stored charge may depend o the initial state of each capacitor— e.g., whether the initial state stored corresponded to a logic 1 or a logic 0. When the selection components of the memory cells 105 ar activated by the word line WL, the change in stored charge due to biasing the plate line CP may cause a change in the voltages of digit lines BL-T and BL-C based on the charge stored on the capacitors of the memory cell 105. The change i the voltage of digit lines BL-T and BL-C may cause a change on sense nodes A and B of the sense component 25, respectively. The resulting voltage of digit lines BL-T and BL-C may he compared to one no h r by the sense component 25 in order to determine the logic value represented by the stored state of each memor cell 105.

»J Sense component 25 may include various transistors or amplifiers to detect and amplify a difference in signals, which ma including latching the amplified difference. Sense component 25 may include a sense amplifier that receives and compares the voltage of its sense nodes (e.g., sense nodes A and B). The voltages of the sense nodes A and B ma be affected by the voltages of the digit lines BL-T and BL-C, respectively. The sense amplifier output (e.g., sense node A) may h driven to a higher (e.g., a positive) or lower (e.g., negative or ground) supply voltage based on the comparison. The other sense node (e.g., sense node B) ma be driven to a complementary voltage (e.g., the positive supply voltage is complementary to the negative or ground voltage, and the negative or ground voltage- is complementary to tire positive supply voltage). For instance, if the sense node A has a higher voltage than sense node B, then the sense amplifier- ma drive the sense node A to a positive supply voltage and drive the sense node B to a negative or ground voltage. Sense component 25 may latch the state of the sense amplifier (e.g., voltages of sense node A and/or sense node B and/or the voltages of digit lines BL-T and BL-C), which may- ' be used to determine the stored state and logic value of memory cell 105, e.g., logic 1. Alternatively, if the sense node: A has a lower voltage than sense node B, the sense amplifier may drive th sense node A to a negativ or ground voltage and drive the sense node B to a positive supply voltage. Sense component 25 may also latch the sense amplifier state for determining the stored state and the logic value of memory cell 105, e.g., logic 0. [047] The stored state may represent, a logic value of memory cell 105, .which may then be -output, for example, through column decoder 30 as output 35 with reference to Figure. 1 , in embodiments where the sense component 25 also chives the digit lines BL-T and BL- C to complementary voltages, the complementary -vohages ' -maybe applied to -the memory cell 105 to restore the original ' data slate read. By restoring the data, a separate restore operation is unnecessary.

|048| Figure 2B illustrates a sense -component 25 according to an embodiment, of the disclosure. The sense component 25 includes p-type field effect transistors 252 and 256 and n-iype field effect transistors 262 and 266. Gates of the transistor 252 and transistor 262 are coupled to .sense node A. Gates of the transistor 256 and transistor 266 are coupled to sense node B. The transistors 252 and 256, and the transistors 262 and 266 represen a sense amplifier. A p-type field effect transistor 258 is configured to be coupled to a power- supply (e.g., V EAD voltage power supply) and is coupled to a ' . common node of the transistors 252 and 256. The transistor 258 is activated by an active PSA signal (e.g., active low logic). A n~type field effect transistor 268 is configured to be coupled to a sense -amplifier reference voltage (e.g., ground) and is coupled to a common node of the transistors 262 and 266. The transistor 268 is activated by an activ NSA signal- (e.g., active hig logic).

}04 | In operation, the sense amplifier is activated by activating the PSA and NSA signals to couple the sense amplifier to the voltage of the power supply and the sense amplifie reference voltage. When activated, the sense amplifie compares the voltages of sense nodes A and 8, and amplifies a voltage difference by driving tire sense nodes A and B to complementary voltage levels (e.g., driving sense node A to VREAD and sens node B to ground, or driving sense node A to ground and sense node B to VREAD). Whe the sense nodes A and B have been driven to the complementary voltage levels, the voltages of sense nodes A and B are latched by the sense amplifier and remain latched until th sense amplifier is deactivated.

f050] With reference to Figure 2.4, to write memory cell 105, a voltage ma be applied across the capacitors of the memory cell 105. Various methods may be used, in some examples, selection components may be acti vated through word .lines WL, respectively, in order to couple the capacitors to digit lines BL-T and BL~C. For ferroelectric capacitors, a voltage may be applied across capacitors of the memory cell 105 by controlling the voltage of digit lines BL-T ' and BL~C to apply a positive or negative voltage across the capacitors. ■in. some embodiments, a- com lementary voltage is appl ied to the capaci tors of the -memory cell 105 to write the memory cell 105, for example, using the digit lines BL-T and BL-C, and plate line CP. As a .non-limiting example, in. som embodiments, to writs a first logic value to ' the memory cell 105 a first voltage is applied to one plate of the capacitors and a second voltage complementar to the first voltage is applied to the other plait* of the capacitors, and to write a second logic value to the memory cell 105 the second voltage is applied to the one plate of the capaci tors and the firs t voltage is applied to the other plate of the capacitors.

feS!J In some examples, a restore operation may be performed after sensing. As previously discussed, the sense operation may degrade, or destroy the originally stored state of the memory cell 105. After sensing, the state may he wri tten back t the memory cell 105. For example, sense component 25 ma determine the stored state of memory cell 105 and may then write the same state back, for example, through the digit lines BL-T and BL- C,

|053| A ferroelectric material is characterized by -spontaneous electric polarization, for example, it maintains non-zero electric polarization in the absence of an electric field. Example, ferroelectric materials include- barium titanate (BaTiOS), lead titanate (PbTi03), lead zirconium titanate (PZT), and strontium bismuth tantalate (SBT). Th ferroelectric capacitors described herein may include these or other ferroelectric materials. Electric polarization within a ferroelectric capacitor results in a net charge at the ferroelectric material's surface and attracts opposite charge through die capacitor .terminals. Thus, charge is stored at the interface of the ferroelectric material and the capacitor terminals. Because the electric polarization may be maintained in the absence of an ' externally appl ied electric field for relatively long times, even indefinitely, , charge leakage may be significantly decreased as compared with, for example, capacitors employed in volatile memory arrays; This may reduce the need to perform refresh operations as described above for some volatile memory architectures.

] Hysteresis curves 300 .may be understood from the perspective of a single terminal of a capacitor. By way of example, if the ferroelectric material has a negative polarization, positive charge accumulates at the terminal. Likewise, if the ferroelectric material has a positive polarization, negative charge accumulates at the terminal. Additionally, it should be understood that the voltages in hysteresis curves 300 represent a voltage difference across the capacitor and are directional. For example, a positive voltage may be realized by applying a positive -volt age to the terminal in question and maintaining the second terminal at ground (or approximately zero volts (0V)). A negative voltage may be applied by maintaining the terminal i question at ground and applying a positive voltage to the second terminal for example, positive voltages may be applied to negativel polarize the terminal in question. Similarly, two positive voltages, two negative voltages, or any combination of positive and negative voltages may be applied to the appropriate capacitor terminals to generate the voltage difference shown in hysteresis curves 300.

| As depicted in hysteresis curve 300-a, the ferroelectric material ma maintain a positive or negative polarization with a zero voltage difference, resulting in two possible charged states: charge state 305 and charge state 310. According to the example of Figure 3, charge state 305 represents a logic 0 and charge state 310 represents a logic 1. in some examples, the logic values of the respective charge states may be reversed without loss of understanding. 056| A logic 0 or 1 may be written to the memory cell by controlling the electric polarization of the ferroelectric material, and thus the charge on the capacitor terminals, by applying voltage. For example, applying a net positive voltage 315 across the capacitor results in charge accumulation until charge state 305-a is reached. Upon removing voltage 315, charge state 305-a .fellows path 320 until it reaches charge state 305 at zero voltage potential. Similarly, charge state 10 is written by applying a net negative voltage 325, which results in charge state 310-a, After removing negative: voltage 325, charge state 310-a follows path 330 -until it reaches charge state 310 at zero voltage. Charge states 305 and 310 may also be referred to as the remnant polarization (Pr) values, which is the polarization (or charge) that remains .upon removing the external bias (e.g., voltage).

[057} To read, or sense, the stored state of the ferroelectric capacitor, a voltage may be applied across the capacitor, in response, the stored charge, Q, changes, and the degree of the change depends on the initial charge state, and as a result, the final stored charge (Q) depends on whether charge state 305-b or 310-b was initially stored. For example, hysteresis curve 300~b illustrates two possible stored charge state 305-b and 310-b. Voltage 335 may be applied across the capacitor as previously discussed. Although depicted as a positive voltage, voltage 335 may be negative. In response to voltage 335, charge state 305-b may follow path 340, Likewise, if charge state 3IG-b was initially stored, then it follows path 345. The final positio of charge state 305-c-. and charge state 310-c depend on a number of factors, including the specific sensing scheme and circuitry.

}U58} In some cases, the final charge may depend on the intrinsic capacitance of the digit line coupled to the memory cell. For example, if the capacitor is coupled to the digit line and voltage. 335 is applied, the voltage of the digit line may rise due to its intrinsic capacitance. So a voltag measured at a sense component may not equal voltage 335 and instead may depend on the voltage of the digit line. The position of final charge states 305-c and 310-c on hysteresis curve 300-b may thus depend on . the capacitance of the digit line and may be determined through a load-line analysis. Charge states 305-e and 310-c may be defined with respect to the digit tine capacitance. As a result, the voltag of the capacitor, voltage 350 or voltage 355, may be different and may depend on the initial state of the capacitor.

|Θ59| By comparing the digit line voltage to a reference voltage, the initial state of the capacitor ma be determined. The digit line voltage may be the difference between voltage 335 and the final voltage across the capacitor, voltage 350 or voltage 355 (e.g., voltage 335 - voltage 350) or (e.g., voltage 335 - voltage 355). A reference voltage may be generated such that its magnitude is between the two possible digit line voltages in order to determine the stored logic state, for example, if the digit line voltage is higher or lower than, the reference voltage. For example, the reference voltage may be an average of the two quantities (voltage 335 - voltage 350} and (voltage 335 - voltage 355). In another example, the reference voltage may be provided by isolating a voltage on first sense node of a sense component, then causing a voltage change on a second sense node of the sense component through a digi line, and comparing the resultin voltage of the second sense node with the isolated voltage of the first sense node. Upon, comparison by the sense component, the sensed digit line voltage m be determine to he higher or lower than the reference voltage, and the stored logic value of the ferroelectric memory cell (e.g., a logic 0 or 1) may be determined.

|Θ60| Figure 4A is a schematic diagram of two memory cells 105(0) and 105(1) according to an embodiment of the disclosure. A dashed line demarcates an approximate boundar of the memory cell 105. Each of the memor cells 105 includes two selection components Tl and T2 and two capacitors C 1 and C2. The capacitors C I and€2 may be ferroelectric capacitors. The selectio components Tl and T2 may be transistors, for example, n-iype field effect transistors. In such an example, each of the memory ceils 105 includes two transistors and. two capacitors (e.g., 2T2€).

|061| Operation of the selection components Tl and T2 is controlled by applying voltages to the transistor gates. A respective word line WL may activate the selection components (e.g., WL0 ma activate the selectio components Tl and T2 of memory cell 105(0), and WL.1 may activate the selection components Tl and T2 of memory cell 105(1)). I The capacitor CI has a first plate coupled to a plate line CP and has a second plate. The capacitor C2 has a first plate coupled to the plate line CP and has a second plate. The • second plate of the capacitor C I is coupled to the selection component T! and the second plate o th capacitor C2 is coupled to the selection component T2. The -selection component Tl. is .further coupled to a digit line BL-T and the selection component T2 is further coupled to a digit line BL-C. When activated, such as by respective word line WL, the second plate of the capacitor C 1 and the second plate of the capacitor C2 are coupled to the digit l ines BL-T and BL-C, respectively. As 'previously discussed, when coupled to the digi fines BL-T and BL-C, the .memory cell 105 may be accessed. For example, a stored state of the memory cells 105 may be read and/or the memory cells 105 m y be wri tten to store a new state or the same state. Various voltages, for example, complementary voltages in some embodiments, may be applied to the plates of ' the capacitor CI and C2 over the digit tines BL-T and BL-C and the plate line CP to access (e.g., read and/or write) the memory cells 105.

I Figure 4B shows a region of memory arra 10 including exa p e memory cells 105(0) and 305(1 ) of Figure 4A according to an. embodiment of the disclosure. In the embodiment of Figure 4-B, the memory cells 105(0) and 105(1) are laterally displaced relative to one another. A dashed tine demarcates an approximate boundary of a memory cell 105. some embodiments the configuration of the memory cells 105 ma be considered to comprise memory cells within a 4F2 architecture, where F indicates a 'min mum feature size of a given technology .

The illustrated, portion of memory array 10 is supported by a base (not shown). The base may comprise semiconductor material; and may, for example, comprise, consist essentially of, or consist of monoerystalliiie .silicon. The base may be referred to as a semiconductor substrate. The term "semiconductor substrate" means an construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semkonduetive wafer (either alone or in assemblies comprising other materials), and seitiiconductive material layers (either alone or i assemblies comprismg otiie materials). The term ''substrate" refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. In some applications the base may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more -of refractory metal materials, barrier materials; diffusion materials, insulator materials, etc.

|06S| Th adjacent memory cells 105(0} and 105(1) are in a common column as one another within the memory- array. The memor cells 105(0) and 105(1) are shown along digit lines BL-T and BL-C. The digit lines BL~T and B.L-C may be coupled with a sense component 25 of fee - ' type described above with reference to Figures 1 and 2.

066j The memory eel! 105(0) comprises first and second transistors TI and T2, and comprises first and second capacitors C and C2 between the first and second transistors. The first capacitor CI comprises a first plate 1 14, a second plate 116, and a ferroelectric material 118 between fee first and second plates 1 14 and 116. Similarly, the second capacito C2 comprises a first plate 120, a second plate 122, and a ferroelectric material 124 between the first and second plates 320 and 122.

|067| In the shown embodiment fee second plates 1 16 and 122 are container-shaped outer plates, and the first plates 1 34 and 120 are inner plates which extend into the container- shaped outer plates. In other embodiments the second plates 1 1 and 122 may have other configurations,- and the first plates 114 and 120 may also have other configurations.

}Q68j The first plates 1 14 and 120 are coupled with a plate line structure CP. In the .illustrated, embodiment fee first plates 114 and 120 share a common. composition. ith the plate line structure CP, In other embodiments the plate line structure CP may comprise a different composition as compared to the first plates 1 14 and 120.

69 The first and second capacitors, CI and€2, are vertically displaced relative to one another,, with the second capacitor C2 being above the first capacitor CL - The first transistor Tl is between the first capacito CI and the digit line BL-T and is vertically displaced relative to the first capacitor CI, and the second. ' transistor T2 is between the second capacitor C2 and fee digit line BL-C and is vertically displaced relative to the second capacitor C2. [070] I the shown embodiment a first semiconductor pillar 128 extends upwardly from the digi line BL-T to the second plate 16 of the first capacitor CI,, ari the first transistor Tl is along such first semiconductor pillar. The first transistor Tl has a conductive transistor gate 1.30 which is spaced from the semiconductor pillar 128 by gate dielectric materia! 132. The first transistor Tl has a channel region within, semiconductor pillar 128 and along the gate dielectric material 132, and has sotsrce/drain regions 136 and 138 within the semiconductor pillar and on opposing sides of the channel region. The source/drain region 136 is coupled with the second plate 1 16 of the first capacitor CI , a d th source/drain, region. 138 is coupled with the digit line BL-T, ίη· the shown embodiment the so«rca tein region 136 extends to the second plate 1 16 of the first capacitor CI . In other embodiments the source/drain region 136 may extend to an electrical interconnect which in turn, extends to the second plate 1 16 of the first capacitor CI, Also, in the shown embodiment lite soutfee drain 138 extends to the digi t l ine BL-T. in other embodiments ' the source/drain region 138 may extend to an. eleciricai interconnect which in turn extends to the digit line BL~T.

|071J A second semiconductor pillar 140 extends downwardly from the digit line BL-C to the second plate 122 ' of the second capacitor C2, and the second transistor T2 is along such second semiconductor pillar. The second transistor T2 has a second conductive transistor gate 1 2 whic is spaced from the semiconductor pillar 140 by gate dielectric material 144. The second transistor T2 has a second channel region within the semiconductor pillar 140 and along the gate dielectric material 144, and has source/drain regions 148 and 150 within the semiconductor pillar and on opposing sides of the channel region. The source/drain region 148 is coupled with the second plate 122 of second capacitor G2, and the source/drain region 150 is. coupled with the digit lin BL-C. In the shown embodiment, the source drain region 148 extends to the second plate 122 of the second capacitor€2, In other embodiments the source/drab region 148 may extend to an electrical interconnect which in turn extends to the second plate 122 of the second capacitor C2. Also, hi the shown embodiment the source/drai region 150 extends to the digit line BL-C, In other embodiments the souree drain region 150 may extend to an electrical interconnect which in turn extends io the digit line BL-C.

| 72| The conductive gates 130 and 142 of the first and second transistors Tl and Ϊ2 are coupled with a first word line WLO. Such first word line may extend in and oat of the page relative to the cross-section section of Figure 4B,

1073] The memory- cells 105(0} and 05(1 } are substantially identical to one another, with the term, "substantially identical" meaning that the memory cells are identical to within reasonable tolerances of -fabrication and measarement. The memory cell 105(1 ) comprises first and second capacitors CI and C2 together with first and second transistors XI and T2, The first and second transistors T l and T2 comprise conductive gates 30 and 14 which are coupled with a second word line WLI . Accordingly, the second memory cell 105(1) is along a different row (i.e. word line) than the memory cell 105(0) withi the memory array 10.

|Θ74] In the illustrated embodiment of Figure 4B the plate line structure CP is a rail extending horizontally along the column defined by the digit lines BL~T and BL~C. Such rail is shared by the memory cells 105(0) and 1 3(1), as well as by all other memory cells along such column, hi other embodiments the plate line structure CP may be subdivided into a plurality of separate structures.

}075| In the illustrated embodiments of f igure 4B the first and second transistors Tl and T2 of the memory cell 105(0) are vertically displaced relati ve to one another, as are the first and second capacitors CI and C2. Further, the first and second capacitors CI and C2, and first and second transistors " Π and T2, ar in s common vertical plane as one another (i.e., are vertically stacked one atop another). I» other embodiments the first and second capacitors C I and C2, and/or first and second transistors Tl and T2, may be provided in different configurations.

|076| Figure 5A is schematic diagram of two memory ceils 105(0) and 105(1) according .to embodiment of the disclosure. A dashed line demarcates an approximate boundary of the memory ceil 105, Each of the memory cells 105 includes two selection components Tl and T2 and two capacitors CI and C2. The capacitors I and C2 may be ferroelectric capacitors. The selection components Tl and T2 may be transistors, for example, n-type field effect transistors, in such an example, each -of the memory cells 105 includes two transistors and two capacitors (e.g., 2T2C),

The capacitor CM has a first plate coupled- to a plate line CP and has a second plate. The capacitor C2 has a. first plate 120 coupled to the plate line CP and a second plate. The second plate of the capacitor C I is coupled to the selection component T! and the second plate of the capacitor C2 is coupled to the selection componen T2. The selection component Tl is further coupled to a digit line BL-T and the selection component T2 is further coupled to a digit line BL-C. When activated, such as by respective word line WL, the second plate of the capacitor and the second plate of the capacitor€2 are coupled to the digit lines BL-T and BL-C, respectively. As previously discussed, when coupled to the digit lines BL-T and BL-C, the memory cells 105 may be accessed. For example, a stored state of the memory cells 105 may be read and or the memory ' cells 105 may be written to store a new state or the same state. Various voltages, for example, compl mentary voltages in some embodiments, ma be applied to the plates of the capacitor CI and C2 over the digit lines BL-T and BL-C and the plate lin CP to access (e.g., read .and/or write) the memory cells 105.

j Figure 5B shows a portion of a- memory array 10 including example memor cells 105(0) and 105(1) of Figure 5 A according to an embodiment of the disclosure. - la the embodiment of Figure 5B S the memory cell 105(0) is vertically stacked over the memory cell 105(1). A dashed line demarcates an approximate boundary of the memory cells 105(0) and 1 3(1 ). In contrast to the memory cells 105(0) and 1 5(1) of Figure 4 A, which in some embodiments comprise memory cells within a 4F2 architecture, in some embodiments the memory ceils 105 of Figure 5 A may be considered to comprise memory cells within an 8F2 architecture, where F indicates a .minimum features size of a given technology ,

O801 The illustrated portion of memory array 10 ma be supported by a base (not shown) analogous to the base of Figure 4S. The memory cells 105(0) and 105(1 ) are in a common column as one another within the memory array. Digit lines BL-T and BL~C are between the memory cell s 105(0) and 1.05(1), and extend in and ou t of the page relative to the cross- section, of Figure SB, The digit lines BL-T and BL-C may be coupled with a sense component 25 of the type previously described with reference to Figures 1 and 2. Th digi lines BL-T and BL-C are shared by the memory cells 105(0) and 105(1 ).

(081 J The memory cell 1 5(0) comprises first and second transistors Tl and T2 which are laterally displaced relative to one another. The memory cell 105(0) comprises the first capacitor Cl above the first transistor Tl , and comprises the second capacitor C2 above the second transistor T2. The .first transistor Tl is vertically displaced relativ to the first capacitor C and the second transistor T2 is vertically displaced relative to the second capacito C2. The first capacitor Cl comprises a first plat 114, a second plate 116, arid ferroelectric material 118 between the first and second plates 114 aad 1 16. The second capacitor C2 comprises a first plate 120, a second plate 122, and ferroelectric material 124 betwee the first and second plates 120 and 122.

}082| n the shown , embodimeat tire second plates 1 16 and 122 are container-shaped outer plates, and the first plates 1 3 and 120 are inner plates which extend into the container- shaped outer plates, hi other ■■ embodiments . ' the second plates 1 36 and 122 may have other configurations, and the first plates 114 and 120 may also have other configurations.

}083| The first plates 14 and 120 are coupled with a plate line structure CP provided above the first and second capacitors Cl arid C2 of the memory cell 105(0). I the illustrated -embodiment the first plates 114 and 120 share commo composition with the plate line structure CP. In othe embo iments the plate line structure CP may comprise a •different composition as compared to the first plates 114 and 120.

f084] The first and second capacitors Cl and€2 are laterally displaced relative -to one another, and in the shown embodiment are in a same horizontal plane as one another (i.e., are horizontally aligned wit one another). The first transistor Tl is between the first capaci tor CI. and the digit line BL-T, and the second transistor T2 is between the second capacitor C2 and the digit line B ' L-C. fa. the shown embodiment die first and second transistors Tl and T2 ate in a common horizontal plane as one another, and the word line WLO extends along such horizontal plane and comprises ' the gates 130 and 142 of the first and second transistors Tl and T2,

f§8S| A first semiconductor pillar 128 extends upwardly from the digit line BL-T to the second plate 1 16 of the first capacitor CI , and the first transistor Tl is along such first semiconductor pillar. A second semiconductor pillar ί 40 extends upwardly from the digit line BL-C to the second plate 122 of th second capaci tor C2, and the second transistor T2 is alon the second semiconductor pillar 140.

| 86| The first transistor Tl includes the gate dielectric material 132, and further includes the first channel region within the semiconductor pillar 128 and along the gate dielectric material 132, and source/drain regions 136 and 138 within the semiconductor pillar and on opposing sides of the channel region. The source/drain region 13.6 is coupled with the second plate 1 16 of first capacitor CI, and ' the source/drain region 138 is ' coupled with the digit line BL-T. The second transistor Ύ2 includes the gate dielectric material 144, and fofther mciiides the second channel region within the semiconductor pillar 140 and along the gate dielectric material 144, and source drain regions 148 and 150 within the semiconductor pillar and on opposing sides of the channel region. The source/drain region 148 is coupled with the second plate 122 of second capacitor C2, and the source/drain region 150 is coupled with the digit line BL-C.

|08?1 The memory cell 105(1) similar to memory ceil 105(0), and comprises first and secoad capacitors CI and C2 together with first and second transistors Tl and T2. The first and second transistors Tl and T2 comprise conductive gates 130 and 142 which are coupled with a second word line WLl . The first plates 1 14 and 120 of the first and second capacitors C.1 and C2 are coupled with the plate line structure CP provided beneath the capacitors CI and C2, [088] The memory cell 105(1) comprises first and second transistors Tl and T2 which are laterally displaced relative to one another. The memory cell 105(1) comprises the first capacitor CI below the first transistor Tl, and comprises the second capacitor C2 below the second transistor T2. The first capacitor C comprises a first plate 1,14, a second plate 1 16, and fenoelec rie material 1. IS between the first and second plates 1 14 and 1 16. The second capacitor C2 comprises a first plate 120, a second plate 122, and ferroelectric material 124 between the first and second plates 120 and 122.

|089| in the illustrated embodiment the digit line BL-T and BL-C are ' in a common horizontal plane as one another. An axis 159 extending through the digit lines BL-T and BL-C may be considered to define a .mirror plane. The memory cell 105(1 ) may he considered to be a substantially mirror image of the memory cell 105(0) across the mirror plane. The term "substantially mirror image" is utilized to indicate thai the memory cell 105( 1) may be a minor image of the memory cel t 105(0) to withio reasonable tolerances of fabrication and measurement

|O90| In the illustrated embodiment of Figure SB the digit lines BL-T and BL-C re shared b the memory cells 105(0) and 105(1). In other embodiments a plate line structure CP may be shared by memory cells 105(0) and 105(1) which are vertically displaced on opposing sides of the plate line ' structure CP from one -another. Figures 6A and 6B illustrate an example of such other embodiments,

| 91J Figure 6A is schematic diagram of two memory cells 105(0) and 105(1) according to an embodiment of the disclosure. dashed line demarcates an approximate 'boundary of the memory cell 105, Each of the memory cells 105 includes two selection components Tl and T2 and two capacitors C and C2. The capacitors I and€ may be ferroel ctric capacitors. The selection components Tl and T2 may be transistors, for example, n-type field effect transistors. In such an example, each of th -memory cells 105 includes two transistors and two capacitors (e.g., 2T2C). The memory cells 105(0) aid 05(1) of Figure 6A share a plate lin structure CP and are coupled to -different digit lines BL-T and different digit lines BL-C, In contrast, the memory cells 105(0) and 105 . (1) of Figure 5. A share digit lines BL-T and share digit lines BL-C and are coupled to different plate lines CP.

I Operation of the memory ceils 105(0} and 105(1) of Figure 6 A is similar to the operation of the -memory cells 105(0) and 105(1) of Figure 5A previously described, and will not be repeated in the interest of brevity.

Figure 6B shows a portion of a memory array 10 comprising a pair of memory cells

105(0 and 105(1) of Figure 6.4 according to an embodiment of the disclosure. In the embodiment of Figure 6B, the memory cell 105(0) is vertically stacked over the memory cell 105(1 ). A dashed Sine demarcates an approximate boundary of the memory cells 105(0) and 105(1 ). In. some embodiments the memory cells 105 of Figure 6B may be considered to comprise memory ceils within a 8F2 architecture, where F indicates a minhttum features size of a given technology, m contrast to the memory cells of Figure SB,, the memory cells .105(0) and 105(1) of Figure 6B share a plate line structure CP and are coupled to different digit lines BL-Ϊ and different digit lines BL-C,

j The illustrated portion of memory array 10 ma be supported by a base (not shown) analogous to the base of Figure 4B. The memory cells 105(0) and 105(1) are in a common -column as one another within the memory array. A horizontally-extending rail is between the memory cells 105(0) arid 105(1), and extends along the cross-section f Figure 6B. The.ra.il is a plat line structure CP that is shared fey the memory cells 105(0) and 105(1), Digit lines BL-T and BL-C are between the memor cells 105(0) and 105( 1), and extend, in and out of the page relative to the cross-section of Figure- 5B. The digit Sines BL-T and BL-C may be coupled with a sense component 25 of the type previously described with reference to Figures 1 and 2.

I The memory cell 105(0) comprises first and second transistors Tl and T2 which are laterally displaced relative to one another. The memory cell 105(0) comprises a first capacitor CI below the first transistor T.l„ and comprises second capacitor C2 below the second transistor T2. The first capacitor Cl comprises a first plate 1 1 , second plate 1 16, and ferroelectric material 118 between the first and second plates 1.14 and 1.16. The second capacitor C2 comprises a first plate 120, a second plate 122, and ferroelectric material 124 between th first .and second plates 120 and 122.

|Θ96| The first plates 1 14 and 120 are coupled with the plate line structure CP. In the illustrated embodiment th first plates 1 14 and 120 share a common, com osition with the plate line struc ure CP. I» other .embodiments the plate line structure CP ma comprise a different composition as compared to the first plates 11.4 and 120.

|0981 A first semiconductor pillar 128 extends downwardly from the digit line BL-T to the second plate 3 i 6 of the first capacitor CI, and the first transistor Tl is along such first semiconductor illar. A second semiconductor pillar 140 extends downwardly from the digit line BL-C to the second plate 122 of the second capacitor C2, and the second transistor T2 is aiong such second semiconductor ί liar,

I&99 The first transistor Tl includes the gate dielectric material 132, and further includes the first channel region within the semiconductor pillar 128 and along the gate dielectric material 132, and the source/drain, regions 136 and 138 within the semiconductor pillar and on opposing sides of the channel region. The source/drain region 136 is coupled with the second plate 1 16 of first, capacitor CI. and the source/drain region 138 is coupled with the digit line BL-T. The second transistor T2 includes the gate dielectric material 144, the Second channel region, and the source/drain regions 148 and ISO; The source/drain region 148 is coupled -with the second plate 122 of second capacitor C2, and the source/drain region 150 is coupled with the digit line BL-C. [0100] The memory cell 105(1) is similar to memory cell 05(0). and comprises first and second capacitors CI and C2 together with first and second transistors Tl and T2. The first and second transistors Tl and T2 comprise conductive gates 130 and 142 which are coupled with a second word line WLL The first plates 1 14 and 120 of the first and second capacitors CI and C2 are coupled with the plate line structure CP provided beneath live capacitors CI and C2.

|ftl01| An axis 161 extending along the plate line structure CP may he considered to define a mirror plane. This memory cell 1.05(1) ma be considered to be a substantially mirror image of the memory cell 105(0) across the mirror plane. The term "substantially mirror image" is utilized to indicate that the memory cell 105(1) ma he a mirror image of the memory cell 105(0} to within reasonable tolerances of fabrication and measurement. In comparison to the memory cells 105(0) and 105(1 ) previously discussed with reference to Figure SB,, the memory cells 105(0) and 105(1) of the illustrated embodiments of Figure 6B are niirrored with respect to the plate line structure CP whereas the memory cells 105(0) and 105( 1 ) of Figure SB are mirrored with, respect to the digit lines BL-T and BL- C.

105(0) (i.e., the digit line BL- ' Γ above word line WLO) and the digit line BL-T of memory cell 105(1) (i.e., the digit Ike BL-T below word line WLl) are coupled to one another. The digit line BL-C of memory cell 105(0) (i.e., the digit line BL-C above word line WLO) and the digit line 105(1) (i.e., the digit line BL-C below word line WLl) are coupled to one another. Electrical properties of the coupled digit l ines BL-T are compared with those of the coupled digi t li nes BL-C with the sense component 25 of the type described above with reference to Figures 1 and 2.

[0103 J Figure 7A is a schematic diagram of two memory cells 1.05(0} and 1 5(1 ) according to an embodiment of the disclosure. A dashed line demarcates an. approximate boundary of the memory cell. 105. Each of the memory cells 105 includes two selection components Tl and T2 and two capacitors CI and C2. The capacitors Cl and€2 may be ferroelectric capacitors. The selection components Tl and T2 may be transistors, for example, n-type field effect transistors. In such an example, each of the memory cells 105 includes two transistors and two capacitors (e.g., 2T2C).

0104] A respective word, line WL may activate the selection components (e.g., WLO may activate tbe selection components T l and T2 of memory cell 105(6) and WL i may acti vate the selection componenis Tl and T2 of memory cell 1.05(1}). The capacitor CI has a first plate coupled to a plate line CP and has a second plate. The capacitor C2 ha s a first plate coupled to the plate line CP and has a second plate. The second plate of the capacitor C I is coupled to the selection component Tl and the second plate of the capacitor C2 is coupled to the selection component T2. The selection, component Tl. is further coupled to a digit line BL-T and the selection component T2 |s further coupled to a digit line BL-C. The memory cells 105(0) md 105(1) are coupled to a shared digit line BL-T and coupled to it&rent digit lines BL-C " . When activated, such as by respective word line WL, the second plate of the capacitor C I and the second plate of the capacitor C2 are coupled to the digit lines BL-T and BL-C, respectively. As previously discussed, when coupled to the digit lines BL-T and BL-C, the memory cells 105 may be accessed. For example,, a stored state of the memory cells 105 may be read and or the memory cells 105 may he written to stor a new state or the same state. Various voltages, for example, complementary voltages in some embodiments, may he applied to the plates of the capacitor CI and C2 over the digit Sines BL-T and BL-C and the plate tine CP to access (e.g., read and/or write) the memory cells 105.

1 . 01051 Figure 78 shows a regio of a memory array 10 including example, memory cells 105(0) and 105(1) of Figure 7A according to an embodiment of the disclosure, la the embodiment of Figure ?B, the memory cells 105(0} is vertically stacked over the memory cell .105(1). A dashed tine demarcates, aft approximate boundary of the memory cell : .105(0) and 105(1). In some embodiments the configuration of the memor cells 105 may be considered to comprise memory ceils within a 4F2 architecture, where F indicates a minimum features size of a gi ven technology.

pl06j The memory cells 1.05(0) and 105(1) are similar" to the memory cells 105(0) aid 105(1) of tbe ' embodiment of Figure 4B, however, the memory' ceils 105(0) and 105(1) are vertically stacked in the embodiment of Figure 7B rather than laterally displaced as in the embodiment of Figure 4B. The memory cells 1.05(0) and 105(1) of the embodiment o Figure ?B include the same eleme ts as tlie memory cells 105(0) and 105(1 ) of the embodiment of Figure 4B. Where applicable, the reference numbers of the memory cells 105(0) and 105(1) of the embodiment of Figure 4B are used for the memory cells 105(0) and 105(1) of the embodiment of Figure 7B. The memory cells 105(0) and 105(1) share a digit line BL-T.

I&107] Tlie memory cell 105(0) includes first and second capacitors, CI and C2, which are vertically displaced relative t one another, with the second capacitor C2 being above the first capacitor CI . A first transistor Tl is between the first capacitor Cl and the digit line BL-T, and the second transistor T2 is between me second capacitor C2 nd the digit line BL-C, in the illustrated embodiments of Figure 7B the first and second transistors Tl and T2 of the memor eel! 105(0) ' are vertically displaced relative to one another, as are the first and second capacitors Cl and C2. Further, th first and second capacitors. Cl and C2, and first and second transistors Tl and T2 S are in a common vertical plane as one another (i.e., are vertically stacked one atop another), in other embodiments the first and second capacitors Cl and C2, and/or first and second transistors Tl and T2, may be provided in different configurations.

{0108 j The memory cells 105(0) and 105(1) ate substantially identical to one another, with the term "substantially identical' * meaning that the memory cells are identical to within reasonable tolerances of fabrication and measurement Th memory cell 105(1) comprises first and second capacitors Cl and C2 together with first and second transistors Tl and TZ, An axis 163 extending through the digit line BL-T may be considered to define a mirror plane. The .memory cell 1.05(1 ) may be considered to be a substantially mirror image of the memory cell .105(0) across the mirror plane. The term, "substantially mirror image" is. utilized to indicate that the memory cell 105(1) ma be mirror image of the memory cell 105(0) to within reasonable tolerances of fabrication and measurement. In comparison to ■the memory cells 105(0) and 105(1) previously discussed with reference to Figure 4B, the memory cells 105(0) and 105(1) of the illustrated embodiments of Figure 7B are similar to in structure to the memory cells of Figure 4B, ' but are vertically stacked and mirrored with respect to the digit line BL~T, whereas the memory cells 105(0) and 105(1) of Figure 4B are laterally displaced.

|0!O*>i Figure SA is a schematic diagram of four memory cells 305(0)- 105(3) according to an embodiment of the disclosure. A dashed line demarcates an approximate boundary of the memory cell 105. Each of the memory ceils 105 includes two selection components Tl and T2 and two capacitors CI and C2. The capacitors I and C2 may be ferroelectric capacitors. The selection components Tl and T2 may be transistors, for example., n-type- field effect transistors. In such an example, each of the memory cells 105 includes two transistors and two capacitors (e.g., 2T2C).. The memory cells 105(0). and 1 5(1), similarly to cells of Fi gure 6 A, share a plate line structure CP and are coupled to different digit lines BL-T and different digit lines BL-C. The memory cells 105(2) and 105(3) also share a plate line structure CP and are coupled to different digit tines BL-T and different digit lines BL-C. The memory cells 105(1) and 105(2) share the digit lines BL-T and share the digit lines BL-C, similarly to ceils 105(0) and 105(1 ) in Figure 5A. As previously discussed, when coupled to the digit lines BL-T and BL-C, the .memory cells 105 may be accessed. For example 5 a stored state of the memory cells 305 may be read and/or the memory cells 105 may be written to store a new state or the same state. Various voltages, for example, complementary voltages in some embodiments, may be applied to the plates of the capacitor CI and C2 over the digit lines BL-T and BL-C ami the plate line CP to access (e.g., read and/or write) the memory cells 105.

|0 I IO] Figure SB shows a portion of a memory array 11 comprising example memory cells 105(0)- 105(3) of Figure SA according to an embodiment of the disclosure, in the embodiment, of Figure SB, the memory cells 105(0)- 105(3) are vertically stacked. A dashed line demarcates an approximate boundary of the memory ceils 105(0) and 105(f). In some embodiments the memory cells 105(0)- 105(3) of Figure SB may be considered to comprise memory cells within an 8F2 architecture, where F indicates a minimum features size of a given technolog , [0.1.11 J The memory cells .105(0) and 105(1 } have a similar configuration as the memory cells 1.05(0) and 105(1) of the embodiment of Figure 6B, The memory cells 105(2) and 105(3) also have a similar configuration as the memory cells 1.05(0) and. 105(1 ) of the embodiment of Figure 6B. In comparison with the memor cells 105(0) and 105(1 } of Figure 6B, however, two vertically stacked memory cells 105 (e.g., memory cells 105(0) and .105(1 } of Figure SB) are stacked on two other vertically stacked memory cells 105 (e.g., memory cells .105(2) and 105(3} of Figure SB). The memory cells .105(0} and .105(1), and the memor cells 1 5(2) and 105(3) of the embodiment of Figure 8B include the same elements a the memory cells .105(0) and 105(1 ) of the embodiment of Figure 4B.. Where applicable, the reference numbers of the memory cells 1 5(0} and 105(1 ) of the embodiment of Figure 4B are used for the memory cells 105(0) and 105(1), and memory cells 105(2} and 105(3) of the embodiment of Figure 7B. The memory cells 105(1) and 105(2) share a digit line BL-T and share a digit line BL-C.

10.112] The memory cell 105(0} comprises first and second transistors Tl and 12 which are laterally dispiace relative to one another. The memory cell 105(0) comprise a first capacitor CI below the first transistor Tl, and comprises a second capacitor C2 below the second transistor T2, The first and second capacitors C I and C2 are laterally displaced relative to one another, with the second capacitor C2 being in a same horizontal plan as the first capacitor CL The first transistor Tl is between the first capacitor CI and a digit line BL-T, and the second transistor T2 is between the second capacitor C2 and a digit line BL-C, The digit lines BL-T and BL-C extend in and out of th page relative to the cross- sectio of Figure 6B. I the shown embodiment me first and second transistors Tl and T2 are in a common horizontal plane as one another, and the word line WLO extends along such horizontal plane and comprises the gates 30 and 42 of the first and second transistors Tl and T2,

(0113] The memory ceil 105(1 ) is similar to memory cell 105(0), and comprises first and second capacitors CI and€2 together with first and second transistors Tl and T2. The first and second transistors Tl and T2 comprise conductive gates 30 and 42 which are coupled with a second word line WLl. The first plates 1 14 and 120 of the first and second capacitors Cl and C2 are coupled with the plate line structure CP. The memory ceil 105(2) and 05(3) are also similar to memory ceil 105(0), and each comprise first and second capacitors Cl and C2 together with first and second transistors Tl and T2. The first and second transistors T l and T2 of the memory cell 105(2) are 'coupled with, third word line WL2 and the first and second transistors TI and T2 of the memory cell 1.05(3) are coupled with a fourth word line L3,

[0114] In the illustrated embodiment the digit line ,BL~T and BI.-C are in a common horizontal plane as one another. An axis 165 extending throug the digit lines BL-T and BL-C shared by the memory cells 105(1) and 105(2) may be considered to define a mirror plane. The .memory cells 105(3) and 105(2} may be considered to be a substantially mirror image of the .memory cell 105(0) and 105(1) across the mirror plane. The term "substantially mirror image" is utilized to indicate that the memory cells 105(3) and 105(2) may be a mirror image of the memory celt 105(0) and .105(1) to within reasonable tolerances of fabr ication and measurement

10115) Figure A is a schematic diagram of two memory ceils 105(0) arid 105(1 ) according to an eittbodiment of the disclosure. A dashed line demarcates an approximate boundary of the memory cell 105, Each of the memory cells 105 includes three- selection ' components Tl„ T2, and T3 and two capacitors Cl and C2. The capacitors Cl and C2 may b ferroelectric capacitors. The selection components Tl, T2, and T3 may be transistors, for example, n-.type field effect transistors. In such an example, each of the memory cells 105 includes three transistors and two- apacitors (e.g., 3T2C).

| II6j Operation of the selection components Tl , Γ2, and T3 is controlled by applying voltages to the transistor gates. A respective word line WL may activate the selection components (e.g., WL0 may activate the selection components Tl, T2, and T3 of memory cell .1 5(0) and WLl may activate the selection components Tl , T2, and T3 of memory cell 105(1)), The capacitor Cl has first plat coupled to the selection component T3 aid has a second plate. The capacitor C2 has a first plate coupled to the selection component T3 and a second plate. The selection component T3 is former coupled to the plate line CP. The second plate of the capacitor l is coupled to the selection component Tl and the second plate of the capacitor C2 is coupled to the selection component T2, The selection component Tl is -further coupled io a digit line BL-T and the selection component T2 is further coupled to a digit line BL-C, When the selection components Tl, T2, and 13 are activated;, such as by respective word line L, the second plate of the capacitor C I and the second plate of the capacitor C2 are coupled to the digit lines BL-T and BL-C, respectively, and the first plate of the capacitor CI and the first plate of the capacitor C2 are coupled to the plate line CP. As previously discussed, when coupled to the digit lines BL-T and BL-C, the memory cells 105 m y be accessed. For example, a stored st ate of the memory cells 1.05 ma be read -and/or the memory cells 105 may be written to store a new state or the same state. Various voltages, for example, complementar voltages in some embodiments, may be applied to the plates of the capacitor C I and C2 over the digit lines BL-T and BL-C and the plate line CP to access (e.g., read and/or write) the memory cells 105.

|Θ117] Figure B shows a portion of a memory array 10 including example memory cells 105(0) and 105(1) of Figure 9A according to an embodiment of the disclosure, in the embodiment of Figure 9B, the memory cell 105(0) is vertically stacked over the memory cell 305(1), A dashed tine demarcates an approximate boundary of the memory cells 105(0) and 105(1), In some embodiments ' the memory cells 105 of Figure 9B may be considered to comprise memory cells within an 8F2 architecture, where F indicates a minimum features size of a gi ven technology.

}§! 18} The illustrated portio of memory array 10 may be supported by a base (not shown) analogous to the base of Figure 4B, The memory cells 105(0) and 105(1) are in a common column as one another within the .memory array. Digit lines BL-T and BL-C are between the memory celts 105(0) and .105(1), and extend in and out of the page relative to the .cross- section of Figure 9B. The digit lines BL-T and BL-C may be coupled with a sense component 25 of the type previously described with, reference to Figures 1 mid 2. The digit lines BL-T and BL-C are shared by the memory ceils 105(0) and 105(1).

P119j The memory cell 105(0) comprises first and second transistors Tl and T2 which are laterally displaced relative to one another. The memory cell 105(0) comprises the first capacitor€ 1 above the first transistor T 1 , and comprises the second capacitor C2 above the second transistor T2, The first capacitor CI comprise a first plate 1 14, a second plate 1 16, and ferroelectric material I IS between the first and second plates 114 and 1 16. The second capacitor€2 comprises a first plate 120 and a second plate .122, and ferroelectric material 124 between the first and second plates 120 and 122.

[0120] in the shown embodiment the second plates 116 and 122 are container-shaped outer plates, and the first plates 114 and 120 are inner plates which extend into the container- shaped outer plates, in other embodiments the second plates 16 and 1 2 may have other configurations, arid the ' first plates 1 14 and .120 ma also ha ve other configurations.

1.21] Th first plates .1 14 and 120 are coupled with a third transistor T3 which is vertically displaced relative to the transistors Tl and T2. The third transistor T3 ma be verticall displaced relative to the capacitors CI and C2. The transistor T3 is coupled to a plate line structure CP provided above the transistor T3 and above first and second capacitors CI and C2. In the illustrated embodiment the first plates .1 14 and 120 share a common composition ,

|0122] The first and second capacitors CI and C2 are laterally displaced relative t one another, and in the shown embodiment are in a same horizontal plane as one another (i.e., are horizontally aligned with one another}. The first transistor Tl is Between the first capacitor C and the digit line BL-T, and the second transistor T2 is between tire second capacitor C2 and the digit line BL-C. In the shown embodiment the first and second transistors Tl and T2 are i a common horizontal plane as one another, and the word line WLO extends along such horizontal plane and comprises the gates 130 and 142 of the first and second transistors Tl and T2. The third transistor T3 is between the first and second capacitors C.I and C2 and the plate line structure CP. A word line WLO extends along a horizontal plane and comprises a gate 560 of th third transistor T3. The WLO of the t ird transistor T3 extends alon a horizontal plane that is vertically displaced from the common horizontal plane of the first and second transistors T l and T2, and of the word .line WLO . of the first and second transistors Tl and T2, 0l23j A first semiconductor ' pillar 128 extends upwardly from the digit line BL-T to the second plate 116 of the first capacitor CI, and the .first ' transistor Tl is along such first ■semiconductor pillar. A second semico ductor pillar 140 extends upwardly from the digit l ine BL-C to the second plate 122 of th second capaci tor C2, and the second transistor T2 is along the second semiconductor pillar 140.

{0124] The first transistor Ti includes the gate dielectric material 132, and further includes the first channel region within the semiconductor pillar 128 and along the gate dielectric material 132. and source/drain regions 136 and 138 within the semiconductor pillar and on opposing sides of the channel region. The source/drain region 136 is eoupled with the second plate 1 16 of first capacitor C L, and the source/drai region 138 is coupled with the digit line BL-T. The second transistor T2 includes the gate dielectric material 1 4, and further includes the second channel region, and source/drain regions 148 and 150. within the semiconductor pillar and on opposing sides of the channel region. The source/drain region 148 is coupled with the second plate 122 of second capacitor C2 t and the source/drain region 150 is coupled with the digit line BL-C.

10125] A third semiconductor pillar 170 extends upwardly from the first plates 114 and 120 to the plate line structure CP. The third transistor T3 is along the third semiconductor pillar 170. The third transistor T3 includes a gate dielectric ' material 172, a third channel region, and source/drain regions 174 and 176. The source drata region 174 is coupled with the first plates 1 14 and 120 of the first and second capacitors CI and C2, and the source/drain region 176 is coupled with the plate line structure CP. In some embodiments, the third semiconductor pillar 170 may have different dimensions (e.g., channel length and/or width) from the first and second semiconductor pillars 128 and 140, as is shown in Figure B. I other embodiments, the third pillar 170 may have similar dimensions (e.g., channel length and/or width} as the first and second semiconductor pillars 128 and 140.

|0l26j The memory celt 105(1) similar to memory cell 105(0), and comprises first and second capacitors CI and C2 together with transistors T L T2, and T3. The transistors Tl and T2 comprise conductive gates 130 and 142 which are eoupled with a second word line WLI, and the transistor T3 comprises conductive gate 160 which is coupled with the second word line WIT that extends along a horizontal plaae that is vertically displaced from th common horizontal plane of the first and second transistors Tl and T2.

0127] The memory cell 105(1) comprises first and second transistors Tl and T2 which are laterally displaced relative to one another. The memory cell 105(1) comprises the first capacitor CI below the first transistor Tl , and comprises the second capacitor C2 below the second transistor T2. The first capacitor CI comprises a first plate 114, a second plate 116, and feToelectric material 1 IS between the first and second plates 114 and 116. The second capacitor C2 comprises a first plate 120, a second plate 122, and ferroelectric material 124 between the first and second plates 120 and 122. A third transistor T3 is vertically displaced from the first and second transistors Tl and T2 and between the capacitors C! and C2 and the plate line structure CP.

10128] In the illustrated ein odimeni the digit line BL-T and BL-C are in. a common horizontal plane as one another, .An axis 167 extending through the digit lines BL-T and BL-C may be considered to define a mirror plane.. The memory cell 105(1 ) may be considered to be a substantially minor image of the memory ceil 105(0} across the mirror plane. The term "substantially mirror image" is utilized to indicate that tire memory cell 105(1) may be a mirror image of the memor cell 105(0) to within reasonable tolerances of fabrication and measurement.

10129] in the illustrated embodiment of Figure 98 the digit lines BL-T and BL-C are shared by the memory cells 105(0) and 105(1). in other embodiments a plate line structure CP may be shared by memory cells 105(0) and 105(1 ), which are vertically displaced on opposing sides of the plate line structure CP from one another. Figures 1 OA and JOB illustrate an example of such other embodiments.

(0130] Figure 10A is a schematic diagram, of two memory cells .105(0) and 105(1) according to an embodiment of the disclosure. A dashed line demarcates an approximate boundary of the memory cell 105. Each of the memory cells 105 includes three selection components Ti , T2, and T3 and two capaciiors CI and C2. The capacitors CI and C2 may be ferroelectric capaciiors. The selection components Tl , T2, and T3 may be transistors. for example, n-type field effect transistors. In such an example, each of the memory cells

105 includes three transistors and two capacitors (e.g., 3T2C).

10131] The memory cells 105(0) and 105(1) of Figure IDA share a plate line structure CP and are coupled to different digit lines BL-T and different digit lines BL-C. in contrast, the memory cells 105(0) -and 105(1) of Figure 9A share digit lines BL-T and share digit lines BL~C and are coupled to different plate lines CP.

f0132| Operation of the -memory- cells 105(0) and 105(1) of Figure 10A. is similar to the operation of the memory cells 105(0) and 105(1 ) of Figure 9 A, and will not be repeated in the interest of brevity,

01 3] The capacitor CI has a first plate coupled to the selection component T3 and has a second plate. The capacitor€2 has a first plate coupled to the selection component T3 and a second plate. The selection component T3 is further coupled to the plate line CP. The second plate of the capacitor Cl is coupled to the selection component Tl and the second plate of the capacitor C2 is coupled to the selection component T2. The selection component Tl is further coupled to a digit line BL-T and the selection component T2 is fnrther coupled to digit line BL-C. When the selection components TL T2, and IB are activated, such as by respective word line WL„ the second plate of die capacitor Cl and the second plate of the capacitor C2 are coupled to the digit lines BL-T and BL-C, respectively; and the first plat of the capacitor Cl and the first plate of the capacitor€2 are coupled to the plate line CP,

1 . 0134! Figure OB shows a portion of a memory array 30 comprising a pair of memory cells 105(0) and 105(1) of Figure Ι0Α according to an embodiment of the disclosure, hi the embodiment of Figure 10B, tire memory cell 105(0} is vertically -stacked ove the -memory cell 105(1). A dashed Hoe demarcates ' an approximate -boundary of the memory cells 105(0) and 105(5 ). in some embodiments the memory cells 105 of Figure 9B may he considered to comprise memory cells within an 8F2 architecture, where F indicates a minimum features ' size of a gi ven technology.

[0135] The illustrated portion of memory array 10 ma he supported by a base (not shown) analogous to the base of Figure 4B. The memory cells 105(0) and 105(1) are in a common column as one another within the memory array. A horizontally-extending, rail is between the memory cells 1.05(0) and 105(1), and extends along the cross-section of Figure IOB. The rail is a plate line structure CP that is shared by the memory cells 105(0) and 105(1), The memory cell 105(0) comprises first and second transistors Tl and T2 which are laterally displaced relative to one another. The memory ceil 105(0) comprises a first capacitor CI below the first transistor Tl, and comprises a second capacitor C2 belo the second transistor T2. In contrast to the memory cells of Figure 9B, the memory cells 105(0) and 105(1 ) of Figure IOB share a plate line structure CP and are coupled to different digit lines BL-T and different digit lines BL-C.

f 0:1,36] The first capacitor CI comprises a first plate 1 14, a second plate 1. 16, and ferroelectric material 118 between the first and second plates 1 14 and 1 16. The second capacitor€2 comprises a first plate 120 and a second plate .122, and ferroelectric -material 124 between the first and second plates 120 and 122,

[0137] In the shown embodiment the second lates 1 16 and 122 are container-shaped outer plates, and the first plates 1 14 and 120 are inner plates which extend into the container- shaped outer plates, in other embodiments the second plates 116 and 122 ma have other configurations, and the first plates 3 34 and 120 may also have other configurations.

|0138j The first plates 1 14 and 120 are coupled with the third transistor T3, which is vertically displaced relative to the transistors Tl and Ϊ2, and capacitors CI and C2. The third transistor T3 is coupled to plate line structure CP. In the illustrated embodiment the first plates 114 and 120 share a common composition.

[0139] The first and second capacitors CI and C2 are laterally displaced relative to one another, with the second capacitor C2 being in a same horizontal plane as the first capacitor CI . The first transistor Tl is betwee the first capacitor CI and a digit line 8L- T, and the second transistor T2 is between the second capacitor C2 and a digit line BL-C. The digit lines BL-T and BL-C extend in and out of the page relati ve to the cross-section of Figure IOB, In the shown embodiment the first and second transistors Tl and T2 are in a common horizontal plane as one another, and the word line L0 extends along such horizontal plane and comprises the gates 130 and 142 of the first and second transistors Tl and T2, The third transistor T3 is between the first and second capacitors CI and C2 and the plate line structure CP. A word line WI.,0 extends along a horizontal plane and comprises gate 160 of the third transistor T3, The WLO of the third transistor T3 extends ■along a horizontal plane that is vertically dis laced from the common horizontal plane of the first and second transistors XI and T2 !: and of the word line WLO of the first and second transistors Tl and T2.

fill 0] A first semiconductor, pillar .128 extends downwardly from the digit line BL-T. to the second plate 116 Of the first capacitor CI , and the first transistor Tl is along such first semiconductor pillar. A second semiconductor pillar 140 ' extends downwardly from the digit line BL-C to the second plate .122 of the second capacito C2 ; and the second transistor T2 is along such second semiconductor pillar 140,

[0141] The first transistor Tl includes the gate dielectric material 132, and liitther includes the first channel region within the semiconductor pillar 128 and along the gate dielectric material 132, and the source/drain regions 136 and 138. The source/dram region 136 is coupled with the second plate 116 of first capacitor CL and the sowce/drahi region .138 is coupled with the digit line BL-T. The second transistor T2 includes the gate dielectric material 144, and further includes the second channel region, and the source/drain .regions 148 and 150 within the semiconductor pillar and on opposing sides of the channel region The source/drain region 148 is coupled with the second plate 122 of second capacitor C¾ and the source/drain region 150 is coupled with the digit line BL-C,

1 . 0] 2] A third semiconductor pillar 170 extends downwardly fr the first plates 114 and 120 of the first and second capacitors CI and C2 to the plate line structure CP. The third transistor T3 is alon the third semiconductor pillar 170. The third transistor T3 includes a gate dielectric, .material 172, a third channel region, and source/drain regions 174 and 176. The source/drain region 174 is coupled with the first plates 11.4 and 120 of the first and second capacitors€1 and C2, and the source/drain region 176 is coupled with the plate line structure CP. In some embodiments, the third semiconductor pillar 170 may h e different dimensions (e.g., channel length and/or width) from the first and second semiconductor pillars 128 and 140, as is shown in Figure 10B. In other embodiments, the third pillar 1 0 may have similar or the same dimensions (e.g., channel length and/or width) as the first and second semiconductor pillars 128 and 140.

10143] The memory ceil 105(1) is similar to memory celt 105(0), and comprises first and second capacitors CI and C2 together with, transistors XI, T2, and T3. The first and second transistors Tl and T2 comprise conductive gales 130 and 142 which are coupled with a second word line WLl, and the- transistor T3 comprises conductive gate 160 which is coupled with the second word line WLI that extends along a horizontal plane that is vertically displaced from the common horizontal plane of the first and second transistors Tl. and T2.

0144] Th memory ceil 1.05(1) comprises first and second transistors Tl and T2 which are laterally displaced relative to one another. The memory cell 105(1) comprises the first capacitor CI above the first transistor Tl , and comprises the second capacitor C2 above the second transistor T2. The first capacitor CI comprises a first ptate 114, a second plate 1 16, and ferroelectric material 3 18 between the first and second plates 1 1 and 1 16. The second capacito C2 comprises a first plate 120, a second plate .122, and ferroeieciric material 124 between the first and second plates 120 and 122, A third transistor T3 is vertically displaced from the first and second transistors XI and T2 and between the -capacitors- CI and C2 and the plat line structure CP.

}914S] A axis 169 extending along the plate line structure CP may be considered to define a mirro plane. The memor ceil .105(1) may be. considered to be a substantially mirror image of the memory cell 105(0) across th mirror plane. The term "substantially mirror image" is utilized to indicate that the memory cell 1 ,05(1) may be a mirror image of the memory cell 105(0.) to within reason able tolerances of fabrication and measurement In- comparison to the .memory cells 105(0) and 105(1 ) previously discussed --with reference to Figure 9B, the memory cells .105(0) and 105(1) of the illustrated embodiments of Figure 10B are mirrored with respect to the plate line structure CP whereas the memory cells .105(0) and 105(1 ) of Figure 9B are mirrored with respect t the digit lines BL-T and BL- C. [0146] In the illustrated embodiment the digit line BL-T of memory cell 105(0) (i.e., the digit line BL-T above word line WLO) and the digit line BL-T of memory cell 105(1) (i.e., the digit line BL-T below word line WLl) are coupled to one another. The digit line BL-C of memory cell 105.(0) (i.e., the digit line BL-C above word line WLO) ami the digit line 105(1) (i.e., the digit line BL-C below word line WLl) are coupled to one another. Electrical properties of the coupled digit lines BL-T are compared with those of the coupled digit Hues BL-C with a sense component 25 of the type described above with reference to Figures 1 and 2.

|0147| Figure 1 1 A is a schematic diagram of two memorj' cells 105(0) and 105(f) according to an embodiment of the disclosure. A dashed line demarcates an approximate boundary of the memory cell 105. Each of the -memory cells 105 includes four selection components T1-T4 and two capacitors ' CI and C2. The capacitors C I and C2 ma be ferroelectric capacitors. The selection components T1-T4 may be transistors, for example., ii-type field effect transistors. Its such an example, each of the memory cells 105 includes four transistors and two capacitors- (e.g., 4T2C).

|0148] Operation of the selection components TLT4 is controlled by applying voltages to the transistor gates. A respective word line WL may activate the selection components (e.g., WLO may activate the selection components TI-T4 of memory cell 105(0) and WLl mm activate the selection components 11 -T4 of memory cell 105(1)).

|0149] The capacitors C I and C2 each have a first plate coupled to a respective selection component T2 and T3 and have second plate coupled to a respective selection component T l and T4, The second plate of the capacitor Cl is coupled to the selection component Tl and the second plate of the capacitor C2 is coupled to the selection component T4. The selection component Tl is further coupled to a. digit line BL- and the selection component T4 is further coupled to a digit line BL-C, Whe activated, such as by respective word line WL, the second plates of the capacitors Cl and C2 are coupled to the digit lines BL-T and BL-C, respectively. The selection components T2 and T3 are- urther coupled to a plate line CP. When activated, such as by respective word line WL, the first plates of the capacitors Cl and C2 are coupled to the plate line CP. As previously discussed, when coupled to the digit lines BL-T and BL-C, the memory cells 105 may be accessed. For example, a stored state of the memory cells 105 may be read .and/or the memory cells 105 ma be written to store a new state or the same state. Various voltages, for example, complementary voltages in some embodiments, may be applied to ■■ the plates of the capacitor CI and C2 over the digit lines BL-T and BL-C and the plate line CP to access (e.g. , read and/of write) the memory cells 105.

fftlSO] Figure I IB . , shows a region of a memory array 10 including example memory ceils .105(0) and 105(1) of Figure 11 A according to an ' embodiment of the disclosure, hi the embodiment of Figure 1 I B, the memory cells 105(0) and 105(1 ) are laterally displaced relative to one another. A dashed line demarcates aft ap r im te boundary of a memory cell 105. The memory cells 105(0) and 105(1) are substantially identical to one another, with the term "substantially identical" meaning that the memory cells ar identical, to within reasonable tolerances of fabrication and measurement In some embodiments the configuration of the emoi cells 105 may be considered to comprise memory cells within a 4F2 architecture. , where F indicates a minimum, features size of a gi yen ' technology

10151 j The illustrated portion of memory arra 0 may be supported by a base (not shown) analogous to the base of Figure 4B. The adjacent memory cells 105(0) and 105(1 ) are in a commo column as one another -within the memory ' array. The memory cells 105(0) and 105(1) ar show along digit Hues BL-T and BL-C. The digit lines BL-T and BL-C are coupled with a- sense component 25 of the type described abo ve with reference to Figures 1 and 2.

|0152 The memory cell 105 comprises first, second, third, and fourth transistors T1-T4 and firs and second capacitors CI and C2. In the illustrated embodiments of Figure Ϊ IB the first, second, third, and fourth transistors ΊΊ -Τ4 of the memory cell 105(0) are vertically displaced relative to one another, as are the first and second capacitors CI and C2, Further, the first and second capacitors C 1 and€2, and first, second, third, and fourth transistors T1.-T4 are in a common vertical plane as one another (i.e., are vertically stacked one atop another). The first capacitor Cl comprises a first plate 114, a second plate 1 16, and a ferroelectric material 118 between the first and second plates 114 and 116. Similarly, the second capacitor C2. comprises a first plate 120, a second plate 122, and a ferroelectric material 124 between the first and second plates 120 and 122.

|0153] The first transistor Ti is between the first capacitor CI and the digit ime BL-T, and the fourth transistor T4 is between the second capaci tor C2 and the digit line BL~C . The second transistor T2 is between the first capacitor CI and the plate line ' structure CP and the fourth transistor T3 i between the second capacitor C2 and the plate line structure CP.

(0154] In. the shown embodiment a first semiconductor pillar J 2.8 extends upwardly from the digit line BL-T to the second plate 1 16 of the first capacitor CI, and the first transistor T . is along such first semiconductor pillar. The first transistor Ti has a conductive transistor gate 130 which is spaced fr m the semiconductor pillar 128 by gate dielectric material 132. The first transistor T t has a ' channel region within semiconductor pilla 128 and along the gate dielectric material .132, and has source/drain regions 136 and 138 within the semiconductor pillar and on opposing sides of the channel region. The source/drain region 136 is coupled with the second plate 1 16 of the first capacitor CI , and the source/drain region 138 s coupled with the digit line BL-T, in the shown embodiment the source/drain region 136 extends to the second plate 116 of the first capacitor C I . A second semiconductor pillar 140 extends downwardly from the plate line structure CP to the first plate 114 of the first capacitor CI, and the second transistor T2 is along such second pillar, A third semiconductor pillar 170 extends upwardly from the plate line structure CP to the first plate 120 of the second capacito C2, and the third transistor T3 is along the second semiconductor pillar 170, A fourt semiconducto pillar 190 extends downwardly from the digit line BL-C to the second plate 122 of the second capacrtor C2, and the fourth transistor T4 is along the fourth semiconductor pillar 190.

(0155] The first transistor Tl includes the gate dielectric material 132, the channel region, and source/drain region 136 and 138. The source/drain region 136 is coupled with the second plate 1 16 -of first capacitor CI, and the source/drain region 38 is coupled with the digit line BL-T. Hie fourth transistor T4 include the gate dielectric, material 144, the channel region, and source/drain regions 194 and 196, The source/drain region 194 is coupled with the second plate 122 of second capacitor C2, and the source drain region 1 6 is coupled with the digit. line .BL~C.

fOI5&j The second transistor T2 includes the gate dielectric material 144, the channel region, and soarce/drasn regions 148 and 150. The source/drain region 148 is Coupled with the first plate 114 of first capacitor CI , and the source/drain region 130 is coupled with the plate line structure CP. The third transistor T3 includes the gate dielectric material Π.2, the channel region, and source/drain regions 174 and 1 76, The source/drain region 174 is coupled with the first plate 120 of second capacitor C2, and the source/drain region 176 is coupled with the plate line structure CP, The conductive gates of the first second, third, and fourth transistors T1-T4 are coupled with a first word line WL0, Such first word line may extend in and out of the page relative to die cross- section section of Figure 1 I B,

[0157] The memory cell 105(1 ) similar to memory cell 105(0), and comprises first and second capacitors CI and€2 together with first, second, third, and fourth ' ' transistors TL T2, T3, and T4. The first, second, third, and fourth transistors T1-T4 comprise conductive gates thai, are coupled with a second word line WLl . The first plates 114 and 120 of the first and second capacitors CI and€2 are coupled with the second and third transistors T2 and T3 and the second plates 1 16 and 122 of the first, and second capacitors CI and C2 are coupled with the first and fourth transistors Tl and T4.

{0158 j in the illustrated embodiment of Figure MB the plate line structure CP is a rail extending horizontally along the column defined by the digit lines BL-T and BL-C. Such plate line stniciure CP is shared by the memory cells 105(0) and 305(1 ), as well as by all other memory 'Celts along such column.

}0159] Figure 12 A is a schematic diagram of two memory cells 105(0) and 105(1) according to an embodiment of the disclosure. A dashed Hoe demarcates an approximate boundary of the memory celt 105, Each of the memor cells 105 includes four selection components T1-T4 and two capacitors CI and C2, The capacitors CI and C2 may be ferroelectric capacitors. The selection components Tl ~T4 ma be transistors, fo example, n-type. field effect .transistors. In such an example, each of the ..memory cells 105 includes four transistors and two capacitors (e.g., 4T2C). [0160] Operation of the selection components T1- 4 is controlled by applying voltages to the transistor gates, A respective word line WL may activate the- selection components (e.g., WLO may activate the selection components T1-T4 of memory cell 105(0) and Li may activate the selection components T1-T4 of memory cell 105(1)}, The capacitors C I and C2 each have a first plate coupled to a plate line CP through transistors T2 and T4. The capacitor CI has a second plate coupled to a digit .line BL-T through transistor Τ.Ϊ and the capacitor C2 has a second plate coupled to a digit line BL- through transistor T3. When the transistors Tl and T3 ar activated. Such as by respective word line WL, the second plates of the capacitors C.1 and C2 are coupled to the digit lines BL-T and BL-C, respectively. As previously discussed, when coupled to the digit lines BL~T and BL-C, the memory ' ceils 105 may be accessed. For example, a stored state of the memory ceils 105 may be read and/or the memory cells 105 may be m t en to store new state or the same state. Various voltages, for example, complementary voltages in some embodiments, may be applied to the plates of the capacitor Ci and C2 over the digit lines BL-T and BL-C and the plate Sine CP to access (e.g., read and/or write) the memory cells 105.

10161] Figure I2B shows portion of a memory array 10 including example memory cells 105(0) and 305(1 ) of Figure 12A according to an embodiment of the disclosure. In Ihe embodiment of Figure Ϊ2Β, the .memory cell 105(0) is Vertically stacked over the memory cell 05(1 ). A dashed Sine demarcates m approximate boundary of the memory cells 05(0) and 105(1 ). in some embodiments the memory cells 105 of Figure 12B may be considered to comprise memory cells within an 8F2 architecture, where F indicates a minimum features size of a given technology,

}fil62) The illustrated portion of memory array 1 may he supported by a base (not shown) analogous to the base of Figure 4B . The memory cells 105(0) and 105(1) are in a common .column as one another within the memory array. Digit lines BL-T and BL-C are between the memory cells 105(0) and 1 5(f), and extend in and out of the page relative to the cross- section of Figure 12.B. The digit lines BL-T and BL-C may be coupled with a sense component 25 of the type previously described with, reference to Figures 1 and 2. The digit lines BL-T and BL-C are shared by the memory ceils 105(0) and 105(1). |β163] The memory cell 105(0) comprises first, second, third, and fourth transistors Tl - T4. The first and third transistors Ti and 73 are laterally displaced relative to one another, and the second and fourth transistors T2 and T4 are laterally displaced relative to one another. The memory cell 105(0) comprises the f rst capacitor CI between the first and second transistors T.I and T2, and comprises the second capacitor C2 between the third and fourth transistors T3 and T4. The first capacitor CI comprises a first plate 114, a second plate 1.16, and ferroelectric material 118 between the first and second plates 114 and 116. The second capacitor C2 comprises a first plate 1:20 and a second plate 122, and ferroelectric material 124 between the first and second plates 120 and 122. Hie second transistor T2 is above the first capacitor Cl and the fourth transistor T4 is a ove the second capacitor C2.

10104] In the sho wn embodiment the second plates 11 and 122 are container-shaped outer plates, and the first plates 114 and 120 are inner plates which extend into the container- shaped outer plates. In other embodiments the second plates 1 16 and 122 may have other configurations, and the first plates 1 14 and 120 may also have other configurations.

|0165] The first plates 114 and 120 are coupled to the second transistor T2 and fourth 'transistor T4„ respectively. The second and fourth ' transistors T2 and T4 are coupled to a plate line structure CP provided above the second and fourth transistors T2 and T4.

{0166 j The first and second capacitors C and€2 are laterally displaced relative to one another, and in the shown embodiment are in a same horizontal plane as one another (i.e., are horizontally aligned with one another).

|0!67] The first transistor T l is between the first capacitor C I and the digit line BL-T, and the third transistor T3 is between the second capacitor€2 and the digit line BL-C. In the shown embodiment, the first and third transistors Tl and T3 are m a common horizontal plane as one another, and the word line WL0 extends along such horizontal plane and comprises the gates 130 and 160 of the first and third transistors ' Tl and T3. The second transistor T2 is between the first capacitor CI and the plate line structure CP and the fourth transistor T4 is betwee the second capacitor C2 and the plate line structure CP, in the shown embodiment the second and fourth transistors T2 and Γ4 are in a common horizontal plane as one another, and the word line WLO extends along suc horizontal plane and comprises the gates J 44 and 180 of the second and fourth transistors T2 and T4. The first and third transistors Tl and T3 are i a common horizontal plane that is vertically displaced from the common horizontal plane of the second and fourt transistors T2 and T4.

|0168] A first semiconductor pillar 128 extends upwardly from die digit line BL-T to the second plate 1 .16 of the first capacitor CI, and the first transistor Tl is along such first semiconducto pilar .128. A second semiconductor pillar 140 extends downwardly from the plate line structure CP to the first plate 1.14 of the first capacitor CT and the second transistor T2 is along suc second pillar, A third semiconductor pillar 170 extends upwardly from the digit line BL-C to fee second plate 122 of the second capacitor C2, and the third transistor T3 is along the third semiconductor pillar ί 70, A fourth senhconductot pillar 190 extends downwardly from the plate line structure CP to the first plate 120 of he second capacitor C2, and the fourth transistor T4 i along the fourth semiconductor pillar 190.

|0169] The first transistor Tl includes the gate dielectric material 132, tire first channel region, and source/drain regions 336 and 138. The source/drain region 136 is coupled with the second plate 116 of first capacitor C I , and the source/drain ' region 338 is coupled with fee digit line BL-T, The third transistor T3 includes fee gate dielectric material 172, fee third channel region, and source/drain regions 174 and 176. The . source/drain region 174 is conpled with the second plate 122 of second capacitor C2, and the soiree/drain region 176 is -coupled with the digit line BL-C, The second transistor T2 ' includes the gate dielectric material 142, the second channel region, and source/drain regions 1 8 and 150. The source/drain region 1.48 is coupled with the first plate 1 14 of first capacitor CL and the source/drain region 150 is coupled with the plate line structure CP. The fourt transistor T4 includes the gate dielectric material 182, the second channel region, and source/drain regions 194 and 196. The source/drain region 194 is coupled with the first plate 120 of second capacitor C2, and the somxje rain region 196 is coupled with fee plate line structure CP. [0170] The memory cell 105(1) similar to memory cell 05(0), and comprises first and second capacitors Cl and C2 together with first, second, third, and ibisrth transistors TL T2, T3, and T4, The first and third transistors Tl and T3 comprise conductive gates 130 •and 160 which are coupled with a second word line WLL The second and fourth tansistofs T2 and T4 comprise conductive gates 144 and 180 which are coupled with a second word line WLI. The first plates J 14 and 120 of the first and second capacitors Cl and C2 are coupled with the second and fourth transistors T2 and T4 and the second plates .1 16 and 122 ' of the first and second capacitors C l and C2 are coupled with the first and third transistors Tl and T3.

J0171J Th memory cell 1.05(1) comprises first and second transistors Tl and T which are laterally displaced relative to one another. The memory cell 105(1) comprises the first capacitor Cl below the first transistor Tl,. and comprises the second capacitor C2 below the third transistor T3, The first capacitor Cl comprises a first plate 1 14, a. second plate .1 16, and ferroelectric rnateriai 1 8 between the first and second plates 1 14 and 116. The second capacitor C2 comprises a first plate 120, a second plate 122, and ferroelectric material 124 between the first and second plates 120 and 122. The second and fourth 'transistors T2 and T4 are verticall displaced from the first and third transistors Tl and 3, respectively, and the second and fourth ' transistors T2 and T4 are between the capacitors Cl and C2 and the plate line structure CP.

|0172 J in the illustrated embodiment the digit line BL-T and BL-C are in a common horizontal plane as one another. An axis 173 extending through the digit lines BL-T and BL-C may he considered to define a mirror plane. The memory cell 105(1) may be considered to be a substantially mirror image of the memor cell 105(0) across the mirror plane. The term "'substantially mirror image" is utilized to indicate that the memory cell .105(1) may be a mirror image of th memory cell 105(0) to within reasonable tolerances of 'fabrication and measurement.

fW73] in the illustrated embodiment of Figure 12B the digit lines BL-T and BL-C ate shared by the memory cells 105(0) and 105(1), In other embodiments a plate line structure CP may be shared by memory cells 105(0) and 105(1) which are vertically displaced on opposin sides of the plate line structure CP from one another. Figures 13 A and 13B illustrate an example of such other embodi ments.

0T74j Figure 1.3 A is a schematic diagram of two memory cells 105(0} and 105(1) according to an embodiment of the disclosure. A dashed line demarcates an approximate boundary of the memory cell 105. Each of the memory cells 105 includes four ' selection components T1-T4 and two capacitors CI and C2. The capacitors CI. and . C2 may be ferroelectric capacitors. The selection components T1-T4 may be transistors . , for exam le, n-type field effect transistors, in such an example, eac of the memory cells 105 includes four transistors and two capacitors (e.g., 4T2C),

J0175] The memory ceils 105(0) and 105(1) of Figure 13.4 share a plat line structure CP and are coupled to different digit lines BL-T aad different digit tines BL-C. in contrast, the memory ceils 105(0) and 105(1) of Figure 12A share digit line BL-T and share digit line BL-C and are coupled to different p ate lines ' GP.

|®!76| Operation of tire memo cells 1.05(0) and 105(1) of Figure DA is similar to the operation of the memory ceils 105(0) and .105(1} of Figure 12A, and will not he repeated in the interest of brevity.

( ' 0177} Figure 13B shows a portion of a memory -array 10 comprising a pair of memory cells 105(0} and 105(1} of Figure 12 A according to a embodiment of the disclosure, in the- etsbodimea of Figure I2B, the memory cell 105(0) is vertically stacked over the memory cell 105(1), A dashed Hue demarcates an approximat boundar of the m mor cells 105(0) and 105(1). in some embodiments the memory cell s 105 of Figure 12B may be considered to comprise memory- cells within an 8F2 architecture, where F indicates a minimum features ske of a given technology.

(0Ϊ 78 j The illustrated portion of memory array 10 may be supported by a base (not shown) analogous to the base of Figure 4B, A. horizontally-extending plate line structure CP is. between the memory ceils 105(0) and 105(1), and extends along the cross-section of Figure 13B. The 60 is a plate line structure. CP is shared by the memory cells 105(0) and 105(1). The memory cell 105(0) comprises first, second, third, and fourth transistors Tl- T4. The first and third transistors Tl and T3 are laterally displaced relative to one another, and the second and fourth transistors T2 and T4 which are laterally displaced relative to one another. The memory cell 105(0} comprises a first capacitor CI between the first and •second transistors ΊΊ and T2„ and comprises second capacitor C2 between the third aid fourth transistors T3 and T4. in contrast to the memory cells of Figure T2B, the memory cells 105(0) and 105(1) of Figure 1.3B share a plate line structure CP and are coupled to different digit lines BL-T and different digit lines BL-C.

$17 ] The first capacitor CI comprises a first plate 114, a second plate 116, and first isoelect i material 1 18. The second capacitor C2 comprises a first plate 120 and a second plate 122, and ferroelectric material 124 between the first and second plates 120 and 122. The second transistor T2 is abov the first capacitor CI and the fourth transistor T4 is above the second capacitor C2.

]0180] In the sho wn embodiment the second plates 116 and 122 are contain er~shaped outer plates, and the firs plates 1 14 and 120 are inner plates which extend into the container- shaped outer plates. In other embodiments the second plates 116 and 122 may have other configurations, and the first plates 1 14 and 120 may also have other configurations.

10181] The first plates 114 and 320 are coupled to the second transistor T2 and fourth 'transistor T4„ respectively. The second and fourth transistors T2 and T4 are coupled to a plate line struc ture CP provided below the second and "fourth- ransistors T2 and T4.

{ ' 0182] The first and second capacitors C and€2 are laterally displaced relative to one another, with the -second capacitor C2 being in a same horizontal plane as the first capacitor C 1.

|01S3| The first transistor Tl is between the first capacitor C I and the digit line BL-T, and the third transistor T3 is between the second capacitor€2 and the digit line BL-C. In the .shown embodiment, the first and third transistors Tl and T3 are in a common- horizontal plane as one another, and the word line WL0 extends along such horizontal plane and comprises the gates 130 and 160 of the first and third transistors ' Tl and T3. The second transistor T2 is between the first capacitor CI. and the plate line structure CP and the fourth transistor T4 is betwee the second capacitor C2 and the plate line structure CP, in the shown embodiment the second and fourth transistors T2 and T4 are in a common horizontal plane as one another, and the word line WLO extends along such horizontal plan and comprises the gates 144 and 180 of the second and fourth transistors T2 and T4. The first and third transistors Tl and T3 are. in a common horizontal plane that is vertically displaced from the common horizontal plane of the second and fourt transistors T2 and T4.

1018 ] A. first semiconductor pillar 1.28 extends downwardly from the digit line BL-T to the second plate I .16 of the first capacito C I, and the first transistor Tl is along such first semiconductor pillar 128. A second semiconductor pillar 140 extends upwardly from the plate line .structure CP to the first plate 1 .14 of the first capacitor C.l , and the second transistor T2 i along suc second pillar. A third semiconductor pillar 170 extends downwardly from the digit line BL-C to the second plate 122 of the second capacitor C2, and the third transistor T3 is along the second semiconductor pillar 170. A fourth semiconductor pillar 1 0 extends upwardly from the plate line structure CP to the first plate 120 of the second capacitor C2 S and the fourth transistor T4 is along the fourth semiconductor pillar 1 0,

|0185] The first transistor Tl includes the gate dielectric material 132, fee first channel region, and source/drain regions 336 and 138. The source/drain region 136 is coupled with the second plate 116 of first capacitor C I , and the source drain ' region 338 is coupled with live digit line BL-T, The third transistor T3 includes the gate dielectric materia! 172, the third channel region, and source/drain regions 174 and 176. The . source drain region 174 is coupled with the second plate 122 of second capacitor C2, and the source/drain region 1 6 is coupled with the digit line BL-C,

I&IM] The second transistor T2 includes the gate dielectric material 1 2, the second channel region, and source/drain regions 148 an 150. The source/drain region 148 is coupled with the first plate 1 14 of first, capacitor C L and the source/drain region 150 is. coupled with the plate line structure CP. Th fourth transistor T4 includes the gate dielectric material J.82, the second channel region, and source/drain regions 194 and 196. The source/drain regio W4 is coupled with the first plate 120 of second capacitor C2, and the source/drain region 196 is coupled with the digit line BL-C. |0i8?| The memory cell 105(1} similar to memory cell 105(0). nd comprises first and second capacitors Cl and C2 together with first,, second, third, and fourth transistors Tl , T2, T3, and T4, The first and third transistors Tl and T3 comprise conductive gates 130 •and 160 which are coupled with a second word line WLL The second and fourth transistors T2 and T4 comprise conductive gates 144 and 180 whic are coupled with a second word line WLL The first plates .1 14 and 120 of the first and second capacitors Cl and C2 are coupled with the second and fourth transistors T2 and T4 and the second plates .1 16 and 122 ' of the first and second capacitors C 3 and€2 are coupled with the first and third transistors Tl and T3.

J0J88J The memory cell 1.05(1) comprises first and second transistors Tl and T2 which are laterally displaced relative to one another. The memory cell 105(1) comprises the first capacitor Cl above the first transistor Tl , and comprises the second capacitor C2 above the third transistor T3. The first capacitor Cl comprises a first plate 1 1 , a second plate 1 16, and ferroelectric material 3 38 between the first and second plates 3 34 and 1 16. The second capacitor C2 comprises a first plate 120, a second plate 322, and ferroelectric material .124 between the first and second plates 120 and 122, The second and fourth transistors T2 and T4 are vertically displaced from the Inst and third transistors T and T3 and the second and fourth transistors T2 and T4 are between the capacitors Cl and C2 and the plate line structure CP. lit the illustrated embodiment the digit line BL-T and BL-C are in a common horizontal plane as one another. An axis 173 extending through the digit lines BL-T and BL-C may be considered to define a mirror plane. The .memory cell 105(1) may be considered to be a. substantially' mirror image of die memory cell 105(9) across the mirror plane. The term, "substantially mirror image" is utilized to indicate that the■memory cell 3.05(1) may be a mirror image of the memory cell 305(0} to within reasonable tolerances of fabrication and measurement

f#l$9j In the illustrated embodiment of Figure JOB the digit line BL-T of memory ceil 305(0) (i.e., the digit line ' BL-T above word line WLO) and the digit line BL-T of memory cell 105(1) (i.e., the digit line BL-T below word line WLI) are coupled, to one another. The digit line BL-C of memory cell 105(0) (i.e., the digit line BL-C above word line WLO) and the digit line 105(1) (i.e., the digit line BL-C below word line WLl) are coupled to one another. Electrical properties of the coiipled digit Sines BL-T are compared with those of the coupled digit lines BL-C with a sense component 25 of the type described above with reference to Figures 1 and 2.

|β190| Various embodiments of memory cells havin ' two, three, o four transistors and two capacitors have been disclosed with reference to Figures 1-13. The transistors hi some embodiments of the memory cells may be vertical transistors each formed from a respective semiconductor pillar. The conductive materials of the first and second plates of the capacitors CI -and C2 may be any suitable conductive materials, including, for example, one or more of various metals (e.g., tun sten, titanium, etc.), nietal-contaimng compositions (e.g., metal nitride, metal carbide, metal silicide, etc,), cond ctively-doped semiconductor materials (e.g., conductivery-doped silicon, conductively-do ed germanium, etc), etc. Some or all of plates of the capacitors CI and C2 ma comprise the same composition as one another, or may comprise different compositions relative to one another.

10191] The capacitors CI and C2 are ferroelectric capacitors. The ferroelectric materials of the capacitors CI and C2 may compose any suitable composition or combination of compositions, i some embodiments the capacitor dielectric materials may ' comprise ferroelectric material. For instance, the capacitor dielectric materials may comprise, consist essentially of, o consist of one or more materials selected from th group consisting of transition metal oxide, zirconium, zirconium oxide, hafnium, hafnium oxide, lead zirconium titanate, tantalum oxide, and barium strontium titanate; and having dopant therein which comprises one or more of silicon, aluminum, lanthanum* yttrium, erbium, calcium, magnesium, niobium, strontium, and a rare earth element, hi some embodiments the ferroelectric materials may comprise a same composition as one another, and in other embodiments may comprise different compositions relative to one another.

|0l93j The semiconductor pillars may comprise any suitable semiconductor materials including, for example, one or both of silicon and germanium. The source/drain, regions, and channel region, may be doped with any suitable dopants. In some embodiments the source drain regions may be n-type majority doped, and in other embodiments may be p~ type majority doped.

|®!94] The word lines (WLO and WL1) and digit lines (BL-T and BL-C) may compris any suitable electrically conductive material, including, for example, one or more of various metals (e.g., tungsten, titanium, etc.), metal -containing compositions (e,g.„ metal nitride, metal carbide, metal silicide, etc.), conducti ely-doped semiconductor materials- (e.g., conductively-doped silicon, conductively-doped germanium, etc.), etc. The word lines and digit lines may comprise ' the same composition as one another, or may comprise different compositions relative to one another.

|fll95j Insulative material may surround the various components of memory cells disclosed herein. Such insulative material may comprise an suitable composition or -combination of compositions; including, for example, one or more of silicon dioxide, silico nitride, borophosphosilicate glass, spin-on dielectric, etc. Although insulative material ma be a single homogeneous material in some embodiments, in other embodiments the insulative material may include two or more discrete insulative compositions.

|0I 6j Although the memory cells 105(0) and 105(1 ' ) are shown vertically stacked in Figures 5B, 6B, 9B, 108, 12B, and 13B, m some embodiments of the invention, a single layer of .memory cells- is included in a memory, array. For example, in some embodiments a memory array includes a single layer of memory cells 105(1), without memory cells 105(0) stacked thereon,

{0197] Figure 1.4 illustrates a block diagram of a portion of memory 1400 that includes memory array 1.0 that supports a ferroelectric memory in accordance with various embodiments of the present disclosure. Memory array 10 may be referred to as an electronic memory apparatus and includes memory controller 40 and memory cell 105, which may be examples of memory controller 40 and memory ceil 105 described with reference to Figures I, 2, or 4-13,

|01 8] Memor controller 40 may include biasing component 1405 and timing component 1410, and may operate memory array 10 as described in Figur 1. Memory controller 40 may be in electronic communication with word lines 12, digit lines 15, and sense component 25, which ma b examples of word line 12, digit line 15, and sense component 25 described with reference to Figures 1 , 2, or 4-13. The components of memory array 10 may be in electronic communication with each other and may perform •the functions described with reference to Figures 1-13,

J0J99] Memory controller 40 may be configured to activate word Ikes 12 or digit lines 15 by applying voltages to tlie word and digit lines. For example, biasing componen 1 05 may be configured to appl a 'voltage to operate memor celt 105 to read or write memory cell 105 as described above. In some cases, memory controller 40 may include a row decoder, column decoder, or both, as described with reference to Figure 1. This may enable memory controller 40 to access one or more memory cells 105. Biasing component 1405 may also provide voltage potentials for the operation of sense component 25.

Ι&2ΘΘ] Memory controller 40 may further determine a logic state of the ferroelectric memory cell 105 based on activating sense component 25, and write the logic state of the ferroelectric memory cell 105 back to the ferroelectric memory cell 105.

[0201] In some cases, memory controller 40 ma perform its operations usin timing component 1410, For example, timing component 1 10 may control the timing of the various word tine selections or plate line biasing, including timing for switching and voltage application to perform the memory fractions, such as readin and writing, discussed herein. In some cases, timing component 1410 may control the operations of biasin component 1405. For example, the -memory ' controller 40 may control the biasing component 1405 to provide a read voltage VR.EAD to the plate line CP to change the voltage of the memory ceil, the digit lines BL-T and BL-C, and sense node A and sense node B of sense component 25. Following the biasing of the plate line CP, the memory controller 40 may control the sensing component 25 to .compare th voltage of sense node A to the voltage of sense node B.

10202] Upon determining and amplifying the voltage difference, the sense component 25 may latch the state, where it may he osed ' in accordance with the operations of an electronic device that memory array 10 is a part.

10203] Figure 15 illustrates a system 1500 that supports a .ferroelectric memory in accordance with various embodiments of the present disclosure. System 1500 includes a device 1505, which may be or include a printed circuit board to Connect or physically support various components. Device 1505 may he computer, notebook computer, laptop, tablet computer, mobile phone, or the like. Device 1505 includes a. memory 5 array 10, which may be an example of memory array 10 as described with reference to figures I and 4-13. Memory array 10 may contain memory controller 40 and memory eetl(s) 105, which may be examples of memory controller 40 described with reference to Figures 1 and 1.4 and memory cells 05. described with reference to FIG. .1, 2, and 4-13. Device 1505 may also include a processor 15 0, BIOS component 1515, peripheral component(s 20, and input/output control component 1525. The components of device 1505 may be in electronic communicahon with one another through bus 1530,

[0204] Processo 1510 may be configured to operate memory array 10 through memory controller 40. In some cases, processor 1510 may rform the functions of memory controller 40 described wit reference to Figures 1 and 8. In other cases, memory controller 40 may be integrated into processor 1510, Processor 1 510 may he a general- purpose processor, a digital signal processor (DSP), an applicatioir-specific integrated circuit (ASIC), a field-progi¾m abie gate arra (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or it may be a combination of these types of components. The processor 1510 may perform various functions and operate the memory array 10 as described herein. Processor 1510 may, for example, be configured to execute computer-readable instructions stored in memory array 10 to cause device 1505 perform various functions or tasks. (0205 J BIOS component 1515 may be a software component tha includes a basic input/output system (BIOS) operated as firmware, which may initialize and run various hardware components of system 1500, BI OS component 1515 may also manage data flow between processor 1510 and the various components, e.g., peripheral .components 1520, inpat/outpttt control component .1525, etc, BIOS component 1515 may include a program or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

|02 β 7} Input/output control component 1525 may manage data communication between processor 1510 and peripheral components) 1520, input devices 1535, or output devices 1540. Input/ ' output control component 1525 may also manage peripherals not integrated into device 1505. in some cases, input/output control component 1525 may represent a physical connection or port to the external peripheral.

|0208j Input 1535 may represent a device or signal external to device 1505 that provides input to device 1505 or its components. This may include a user interface or interface with or between other devices, in some cases, input 1535 ma be a peripheral, that interfaces with device 1505 via peripheral eoroponentis) 1520 or may be managed by input/output control component 1525.

10209} Otttput 1540 may represent a device or signal external to device 1505 configured to receive output from device 1505 or any of its components. Examples of output 1 40 may include a display, audio speakers, a printing device, another processor or printed circuit board, etc, in some cases, output 1540 may be a peripheral that interfaces with device .1505 via peripheral components) 1 20 or ma b managed by input/output control component 1525, [0210] The components of memory controller 40, device 1505, and memory array 10 may be made up of circuitry designed to . carry out their functions. This may include various circoii elements, for example, conductive lines, transistors, capacitors, iiiduciors, resistors,, amplifiers, or other active or inactive lements, configured to carry out the funct ons described herein.

{0211 J From the foregoing it will be appreciated that, although specific enibodimeiits of the disclosure have been described herein for purposes of illustration, various modifications may he made wi thout deviating ' from t he spiri t and scope of "the d isclosiire. Accordingly, the disclosure is not limited except as by the appended claims.