Headlines for Wednesday May. 30, 2007

The DesignWare SATA AHCI core is compliant with the SATA 2.6 specification and AHCI 1.1 specification, and includes an ARM AMBA 2-compliant subsystem interface. The DesignWare SATA AHCI core has been verified against the industry-standard AHCI software drivers provided as part of the Linux® and Windows Vista™ operating systems.

Headlines for Tuesday May. 29, 2007

Silicon Image today announced that by combining its digital implementations of the HDMI IP cores with its HDMI analog physical layer (PHY) semiconductors, the company has begun to achieve significant market success, having already sold approximately four million HDMI PHY semiconductors.

Headlines for Thursday May. 24, 2007

Implemented in the 65-nanometer (nm) Common Platform process, Synopsys' DesignWare PHY for PCI Express and digital controllers are the first 65-nm IP to pass the PCI Express 1.1 compliance testing by the PCI-Special Interest Group (PCI-SIG(R)). Additionally, Synopsys' DesignWare USB 2.0 nanoPHY IP in the Common Platform 90-nm process is the first implementation to have earned Hi-Speed USB 'On-the-Go' (OTG) logo-certification by the USB Implementers Forum for devices manufactured at multiple foundries using a single GDSII source.

Headlines for Wednesday May. 23, 2007

The PCI Express Generation II product from PLDA features double the transfer speed – up to 5Gb/s – while maintaining the same quality, backward-compatibility, and ease of integration inherent in PLDA's PCI Express products. A complete test chip for PLDA's Generation II IP will be available to third parties beginning Q1 2008.

Headlines for Tuesday May. 22, 2007

STMicroelectronics, Intel and Francisco Partners today announced they have entered into a definitive agreement to create a new independent semiconductor company from the key assets of businesses which last year generated approximately $3.6 billion in combined annual revenue.

Headlines for Monday May. 21, 2007

With CHAINarchitect, chip architects can easily explore new interconnect topologies and perform ''what if'' analyses to optimize on-chip communications (bandwidth and latency) between IP cores along with overall system characteristics such as power, die area, system-level performance and others.

Headlines for Friday May. 18, 2007

Based on cryptographic research into ''side channels'' DesignTag is a small, low power, active digital circuit supplied as an IP core for inclusion in larger designs. The presence of DesignTags can be detected by a sensor placed in contact with the package of the chip which contains them. DesignTag communicates a unique tag to the sensor which can then be used to access information on the tagged product in a web-based database.

Headlines for Tuesday May. 15, 2007

Synopsys' industry-leading USB 2.0 nanoPHY mixed-signal IP, now available in the TSMC 65-nm process nodes, uses half the power and die area compared to previous USB solutions and enables faster time-to-market and reduced risk.

Headlines for Monday May. 14, 2007

The enhanced 360 MV supports the verification of IP with configurable functionality, such as optional memory-management units, or configurable synchronous or asynchronous FIFO implementations, and configurable dimensions, such as configurable bus-widths, FIFO depths, or register counts

Headlines for Thursday May. 03, 2007

Engineers who are thinking of launching a silicon intellectual property (IP) business in their garage with a couple of friends had better think again, according to panelists at this week's EDA Consortium meeting. The overall message: it's a big business for big players now.