Maskinnær programmering - V15

Spørsmål #68

Consider array accesses only (A, B) and ignore any other accesses. The elements of A and B have a size of 4 bytes. Given a 16KB direct mapped cache with 64 byte blocks, initially empty, which of the following statements is true:

Only cold cache misses will take place.

Loop tiling using blocks of 16x16 elements plus an array padding of 1KB between A and B does not avoid all conflict and capacity misses.

All conflict and capacity misses can be avoided by just inserting the right padding space between A and B.