Cadence noise aware PLL design flow: have lock problem

Started by lunren on 6 Feb 2012 4:16 PM. Topic has 9 replies and 6707 views.
Last post on 7 Feb 2012 3:40 PM by lunren.

Hi All,

It is a bit long story. I will try my best to explain it clear. Thanks for your patience to read it through and give me some feedback. Recently I tried to follow Cadence noise-aware PLL design flow (PLL Macro Model Wizard) to verify my design. (We got the PLL_workshop from Cadence already) I think I successfully extracted VCO (oscmm), pfd+cp (pllTTpfd_cp) models. Then in 1st step, I run pll bench. It doesn't lock, vtune keeps going up. I think maybe I need to swap Fref and Fcomp (though I knew it is not correct to do so) to see what will happen. It turned out that the loop locks and I got correct phase noise curve which matches my simulation results (combining block noise with matlab) very well.

My interests are to see power supply noise effects on phase noise. So in 2nd step, I re-run the simulation with VCO model &quot;oscmm_vdd&quot;. However the loop doesn't lock. I swapped Fref and Fcomp back, it still doesn't lock and vtune keeps going up. Then I replaced VCO model with &quot;oscmm&quot; and tried to reproduce what I got in 1st step, however the loop can't get locked whatever I played with Fref and Fcomp. I replaced model pllTTpfd_cp with transistor design, it locks. So I think there is some problem with the extracted model of pfd+cp. I re-extracted the model for pfd+cp (flowing the flow), but the problem doesn't get solved.

Then I paid more attention to how the pfd+cp model was get extracted. From the log file, I found that (can find how to attach file, just type here :

To me, it seems the extracted model is not correct since Iup_max and Idown_max are not equal and the number is not correct (should be 100uA). Then I run simulation to extract the pfd+cp model for cell &quot;pfd_cp_bench&quot; provided by Cadence in library &quot;PLL_workshop&quot;, what I got is:

It seems the extracted model have the same problem: Iup_max and Idown_max are not equal (I verified that the current should be 4mA). But the pll_bench from library &quot;PLL_workshop&quot; have no lock problem.

I am wondering why my pll model doesn't lock and how to deal with this problem. If you need more information, please let me know.

Hi Tawan,
What do you mean by special permission to access PLL Noise Aware flow? I thought we need special permission (or license) to get library "PLL_workshop", but it is not PLL Noise Aware flow needs special permission, is it?
We did asked Cadence permission for library "PLL_workshop" last year and of course it already expires.

Hi Tawna,
My problem is not to get "PLL_workshop" library and the doc "PLL.pdf". My problem is that after I flow the PLL Noise Aware Flow, the loop doesn't lock.
I think the pfd+cp extraction model has some problem which cause the PLL fail to lock. I need some help on this.

The point is that to get detailed help on this, you would be best logging a service request rather than covering it in the forum. The number of folks who will have got access to the workshop library is fairly small, so if you're expecting help from one of us here at Cadence, and we are having to reference information within that workshop (which contains some IP, hence the restrictions on access), it's best not to do so in a public forum. Plus the fact that it's not obvious why it is not working for you and would need some more detailed investigation.

BTW, my guess with the merged paragraphs is that you're using Chrome; Chrome does not seem to work well with the community forums.

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To obtain the PLL Noise Aware
Flow library (that I mentioned in my previous email), you need
to have the SPLA and Kit exhibit signed (also mentioned previously). It is
only that library (containing the IP) which is not available to
the "general public". It is easier to use the Noise Aware PLL Flow
if you have access to that library.