The ULA is a fairly simple system, even if it looks complex, even the smallest CPLD should be enough to fit the complete ULA.

The ULA was made with technologies from the 80s where PLD wasn't there yet and PAL was just at their infancies.

ULA is a similar concept than a PAL/PLD, but instead of using some programmable logic it was made in factory, and can't be modified after being build.

An ULA (which is *not* a Ferranti, in the Orics) is made of prefabricated blocks as in modern CPLD/FPGA where we connect the input and output of theses blocks. I don't have the details of the ULA used in the Oric for how the blocks are made, but you can be sure that there are way less of them than on a modern CPLD, event the smallest one.

The real problem with CPLD is that most of them are 3.3V maximum and the 5V CPLDs start to get really old.

The good news is I've probably found the company who made the ULA, they are defunct, but I'm trying to contact the founder of that company and try to get some information, if not Tangerine design itself, at least internal plans of a bare ULA.

Tangerine always made a thing about their expertise in ULA design. There was a picture in one article about Oric that showed a £100,000 design computer used to design ULAs. So either they did design it - or they lied a lot.

Allegedly Dr Paul Johnson had a drawing of the ULA on his wall, but he wouldn't release details about it as he didn't know who had the rights to Oric.

As far as I can say, in the UK legaly nobody own the name and IP of the Oric as they have expired. I think it is the same in france, and I'm honestly not sure that the french company really own anything apart from just the hardware. (the story about all of that is really fishy) if anyone here have good knowledge about trademark in the UK and europe that would be really welcome.

I'm not saying they have lied about the ULA, but the ULA itself (not the way it is wired) was not designed by tangerine.

If you have contact with Paul, I would be really please to have a copy of that drawing, even if it is with a NDA. My goal is not to show original documents, but to understand the remaining part of the ULA, and how it was build.

I know what the CDI on the chip mean as it is the manufacturer initials: California Device Inc. Found the founder of that company, but can't get to talk with him, if people want to try to, please send me a message I will give you his name.
The rest of the chip ID is still a mystery to me

I would like to get from him, or any person he knows or could point to, internal documentation about the unprogrammed ULA, so present in, in the same way as the guy who do the same on the Ferranti ULA used in the ZX 81 (or spectrum can't remember)

7x or 8x after CDI is probably the chip revision, (or batch), the last 4 numbers are YYWW with YY the two last digit of the year and the next two the week of manufacturing:
8422 will be 1984, Week 22.

What HCS mean and 10017, no idea at all. But HCS could be the name of the component internally at CDI.

(Hum looks like Mike Brown was on the same track as me in 2014) HCS may stand for a type of transistor (HC Series)

In fact I may have found, thanks to him what I was looking for.

(edit: tried to contact Mike Brown to know his advancement on that point if he have more informations that what I've already found)

Just stumbled on this thread and I wanted to clarify the status of the "Oric in FPGA" project":

First of all, I am not involved in any way in this project.

However, I created the Github repository for the Oric-in-FPGA project 5 years ago using the "Export to Github" feature of Google Code, as it was the time Google Code was being decommissioned, so I "saved" a few projects I thought were worth saving on my Github account so that important works such as this would not get lost.

It actually says so on the repository's home page ("Automatically exported from code.google.com/p/oric-in-fpga") but I thought I'd mention it again so that it is perfecly clear.

What I also would like to mention is I am NOT maintaining this project in any way, as I don't have any knowledge of VHDL or FPGA hardware). However, I do encourage you of course to fork this repository if you feel like maintaining it!!