A method and system for analog video noise reduction by blending finite impulse response (FIR) and infinite impulse response (IIR) filtering are provided. A filtering mode may be selected to generate noise-reduced pixels using FIR, IIR, or a blend of FIR/IIR filtering. Blending a current pixel and an...http://www.google.com.au/patents/US7639309?utm_source=gb-gplus-sharePatent US7639309 - Method and system for analog video noise reduction by blending FIR and IIR filtering

Method and system for analog video noise reduction by blending FIR and IIR filteringUS 7639309 B2

Abstract

A method and system for analog video noise reduction by blending finite impulse response (FIR) and infinite impulse response (IIR) filtering are provided. A filtering mode may be selected to generate noise-reduced pixels using FIR, IIR, or a blend of FIR/IIR filtering. Blending a current pixel and an FlR-filtered current pixel may generate a first blended current pixel. The FIR filtering may be based on the current pixel, a previous collocated pixel, and a next collocated pixel. Blending the current pixel and an IIR-filtered current pixel may generate a second blended current pixel. Blending the first blended current pixel and the second blended current pixel using an adaptive blending factor may dynamically generate a filtered output pixel. The IIR filtering may be based on the current pixel and a collocated pixel of the previous second blended video image or of the previous filtered output video image.

Images(10)

Claims(20)

1. A method for handling analog signals in video systems, the method comprising:

generating a first blended current pixel using finite impulse response (FIR) filtering of a current pixel in a current video image;

generating a second blended current pixel using infinite impulse response (IIR) filtering of said current pixel; and

blending said generated first blended current pixel and said generated second blended current pixel to generate a filtered output pixel.

2. The method according to claim 1, further comprising dynamically modifying an adaptive blending factor for said blending of said generated first blended current pixel and said generated second blended current pixel.

3. The method according to claim 1, further comprising FIR filtering said current pixel based on a previous collocated pixel, a next collocated pixel, and a plurality of filter coefficients.

4. The method according to claim 3, further comprising blending said FIR-filtered current pixel and said current pixel based on an FIR blending factor.

5. The method according to claim 4, further comprising dynamically modifying said FIR blending factor.

6. The method according to claim 1, further comprising IIR filtering said current pixel based on an IIR-filtered previous collocated pixel.

7. The method according to claim 6, further comprising blending said IIR-filtered current pixel and said current pixel based on an IIR blending factor.

8. The method according to claim 7, further comprising dynamically modifying said IIR blending factor.

9. The method according to claim 1, further comprising feeding back said generated filtered output pixel to generate a subsequent second blended current pixel for processing a next video image.

10. The method according to claim 1, further comprising feeding back said generated second blended current pixel to generate a subsequent second blended current pixel for processing a next video image.

11. A system for handling analog signals in video systems, the system comprising:

circuitry within a chip that generates a first blended current pixel using finite impulse response (FIR) filtering of a current pixel in a current video image;

said circuitry within said chip generates a second blended current pixel using infinite impulse response (IIR) filtering of said current pixel; and

said circuitry within said chip blends said generated first blended current pixel and said generated second blended current pixel to generate a filtered output pixel.

12. The system according to claim 11, wherein said circuitry within said chip dynamically modifies an adaptive blending factor for said blending of said generated first blended current pixel and said generated second blended current pixel.

13. The system according to claim 11, wherein said circuitry within said chip FIR filters said current pixel based on a previous collocated pixel, a next collocated pixel, and a plurality of filter coefficients.

14. The system according to claim 13, wherein said circuitry within said chip blends said FIR-filtered current pixel and said current pixel based on an FIR blending factor.

15. The system according to claim 14, wherein said circuitry within said chip dynamically modifies said FIR blending factor.

16. The system according to claim 11, wherein said circuitry within said chip IIR filters said current pixel based on an IIR-filtered previous collocated pixel.

17. The system according to claim 16, wherein said circuitry within said chip blends said IIR-filtered current pixel and said current pixel based on an IIR blending factor.

18. The system according to claim 17, wherein said circuitry within said chip dynamically modifies said IIR blending factor.

19. The system according to claim 11, wherein said circuitry within said chip feeds back said generated filtered output pixel to generate a subsequent second blended current pixel for processing a next video image.

20. The system according to claim 11, wherein said circuitry within said chip feeds back said generated second blended current pixel to generate a subsequent second blended current pixel for processing a next video image.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE

This application makes reference to:

U.S. application Ser. No. 11/314,690 filed Dec. 20, 2005;

U.S. application Ser. No. 11/313,592 filed Dec. 20, 2005;

U.S. application Ser. No. 11/314,680 filed Dec. 20, 2005; and

U.S. application Ser. No. 11/313,871 filed Dec. 20, 2005.

Each of the above stated applications is hereby incorporated by reference in its entirety.

FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[Not Applicable]

MICROFICHE/COPYRIGHT REFERENCE

[Not Applicable]

FIELD OF THE INVENTION

Certain embodiments of the invention relate to processing of analog signals. More specifically, certain embodiments of the invention relate to a method and system for analog video noise reduction by blending finite impulse response (FIR) and infinite impulse response (IIR) filtering.

BACKGROUND OF THE INVENTION

In video system applications, random noise present in analog video signals, such as NTSC or PAL signals, for example, may result in images that are less than visually pleasing to the viewer. To address this problem, noise reduction (NR) operations may be utilized to remove or mitigate the analog noise present. Traditional NR operations may use either infinite impulse response (IIR) filtering based methods or finite impulse response (FIR) filtering based methods. IIR filtering may be utilized to significantly attenuate high frequency noise. However, IIR filtering may result in visual artifacts such as motion trails, jittering, and/or wobbling at places where there is object motion when the amount of filtering is not sufficiently conservative. In some instances, setting the IIR filtering conservatively may mitigate the noise removing capability even for places where there is little or no motion, such as a static area in video. As a result, there may be many instances where objectionable noise artifacts remain in the video signal.

Another traditional NR operation may be FIR filtering based methods. FIR filtering may not be subject to artifacts such as motion trail, motion blurry, jittering and/or wobbling, for example, as much as IIR-based filtering may be. FIR filtering may provide acceptable perceptual quality for moving areas to most viewers. However, in a practical NR system, which may not be able to employ a large number of video images to perform FIR filtering as a result of the cost of storage, the system's noise reducing capability may be very limited in those areas where there is little or no motion.

In order to improve the NR effectiveness it may be necessary to achieve both significant NR in areas of little or no motion and be free of motion artifacts such as motion trails, motion blur, jittering or wobbling in areas where there is motion.

Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.

BRIEF SUMMARY OF THE INVENTION

A system and/or method is provided for analog video noise reduction by blending finite impulse response (FIR) and infinite impulse response (IIR) filtering, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

These and other features and advantages of the present invention may be appreciated from a review of the following detailed description of the present invention, along with the accompanying figures in which like reference numerals refer to like parts throughout.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a block diagram of an exemplary video analog noise reduction system, in accordance with an embodiment of the invention.

FIG. 2 is a diagram illustrating exemplary consecutive video frames for noise reduction operations, in connection with an embodiment of the invention.

FIG. 3A is a block diagram of an exemplary finite impulse response (FIR) filtering system with noise reduction, in accordance with an embodiment of the invention.

FIG. 3B is a block diagram of an exemplary finite impulse response (FIR) filtering system with noise reduction and frame storage, in accordance with an embodiment of the invention.

FIG. 3C is a block diagram of an exemplary infinite impulse response (IIR) filtering system with noise reduction, in accordance with an embodiment of the invention.

FIG. 4A is a block diagram of an exemplary FIR/IIR blended filtering system with noise reduction, in accordance with an embodiment of the invention.

FIG. 4B is a block diagram of an exemplary FIR/IIR blended filtering system with noise reduction and frame storage for IIR filtering feedback, in accordance with an embodiment of the invention.

FIG. 4C is a block diagram of an exemplary FIR/IIR blended filtering system with noise reduction and frame storage for FIR/IIR filtering feedback, in accordance with an embodiment of the invention.

FIG. 4D is a block diagram of an exemplary FIR/IIR blended filtering system with noise reduction and frame storage for IIR filtering or FIR/IIR filtering feedback, in accordance with an embodiment of the invention.

FIG. 5 is a flow diagram with exemplary steps illustrating the operation of the FIR/IIR blended filtering system, in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Certain embodiments of the invention may be found in a system and/or method for analog video noise reduction by blending finite impulse response (FIR) and infinite impulse response (IIR) filtering. A filtering mode may be selected to generate noise-reduced pixels using FIR filtering, IIR filtering, or a blend of FIR/IIR filtering. Blending a current pixel and an FIR-filtered current pixel using an FIR blending factor may generate a first blended current pixel. The FIR filtering may be based on the current pixel, a previous collocated pixel and a next collocated pixel. Blending the current pixel and an IIR-filtered current pixel using an IIR blending factor may generate a second blended current pixel. Blending the first blended current pixel and the second blended current pixel using an adaptive blending factor may dynamically generate a filtered output pixel. The IIR filtering may be based on the current pixel and a collocated pixel of the previous second blended video image or of the previous filtered output video image. The blending factors may be dynamically modified based on a motion metric parameter.

FIG. 1 is a block diagram of an exemplary video analog noise reduction system, in accordance with an embodiment of the invention. Referring to FIG. 1, there is shown a video processing block 102, a processor 104, a memory 106, and a data/control bus 108. The video processing block 102 may comprise registers 110 and filter 116. In some instances, the video processing block 102 may also comprise an input buffer 112 and/or an output buffer 114. The video processing block 102 may comprise suitable logic, circuitry, and/or code that may be adapted to filter pixels in a video frame or a video field from a video input stream to reduce analog noise. For example, video frames may be utilized in video systems that support progressive displays while video fields may be utilized in video systems that support interlaced displays. Video fields may alternate parity between top fields and bottom fields. A top field and a bottom field in an interlaced system may be deinterlaced or combined to produce a video frame.

The video processing block 102 may be adapted to receive a video input stream and, in some instances, to buffer at least a portion of the received video input stream in the input buffer 112. In this regard, the input buffer 112 may comprise suitable logic, circuitry, and/or code that may be adapted to store at least a portion of the received video input stream. Similarly, the video processing block 102 may be adapted to generate a filtered video output stream and, in some instances, to buffer at least a portion of the generated filtered video output stream in the output buffer 114. In this regard, the output buffer 114 may comprise suitable logic, circuitry, and/or code that may be adapted to store at least a portion of the filtered video output stream.

The filter 116 in the video processing block 102 may comprise suitable logic, circuitry, and/or code that may be adapted to perform an FIR filtering operation with noise reduction (FIR-NR) on a current pixel in a video frame or video field, to perform an IIR filtering operation with noise reduction (IIR-NR) on the current pixel, or to perform an FIR-IIR blended filtering operation with noise reduction (FIR-IIR-NR) on the current pixel. In this regard, the filter 116 may be adapted to operate in a plurality of filtering modes, where each filtering mode may be associated with one of a plurality of supported filtering operations. The filter 116 may utilize video content, filter coefficients, threshold levels, and/or constants to generate the filtered video output stream in accordance with the filtering mode selected. In this regard, the video processing block 102 may generate blending factors to be utilized with the appropriate filtering mode selected. The registers 110 in the video processing block 102 may comprise suitable logic, circuitry, and/or code that may be adapted to store information that corresponds to filter coefficients, threshold levels, and/or constants, for example. Moreover, the registers 110 may be adapted to store information that corresponds to a selected filtering mode.

The processor 104 may comprise suitable logic, circuitry, and/or code that may be adapted to process data and/or perform system control operations. The processor 104 may be adapted to control at least a portion of the operations of the video processing block 102. For example, the processor 104 may generate at least one signal to control the selection of the filtering mode in the video processing block 102. Moreover, the processor 104 may be adapted to program, update, and/or modify filter coefficients, threshold levels, and/or constants in at least a portion of the registers 110. For example, the processor 104 may generate at least one signal to retrieve stored filter coefficients, threshold levels, and/or constants that may be stored in the memory 106 and transfer the retrieved information to the registers 110 via the data/control bus 108. The memory 106 may comprise suitable logic, circuitry, and/or code that may be adapted to store information that may be utilized by the video processing block 102 to reduce analog noise in the video input stream. The processor 104 may also be adapted to determine noise levels for a current video frame or video field based on an early-exit algorithm (EEA) or an interpolation estimate algorithm (IEA), for example. The memory 106 may be adapted to store filter coefficients, threshold levels, and/or constants, for example, to be utilized by the video processing block 102.

In operation, the processor 104 may select a filtering mode of operation and may program the selected filtering mode into the registers 110 in the video processing block 102. Moreover, the processor 104 may program the appropriate values for the filter coefficients, threshold levels, and/or constants into the registers 110 in accordance with the selected filtering mode. The video processing block 102 may receive the video input stream and may filter pixels in a video frame in accordance with the filtering mode selected. In some instances, the video input stream may be stored in the input buffer 112 before processing. The video processing block 102 may generate the appropriate blending factors needed to perform the noise reduction filtering operation selected by the processor 104. The video processing block 102 may generate the filtered video output stream after performing the noise reduction filtering operation. In some instances, the filtered video output stream may be stored in the output buffer 114 before being transferred out of the video processing block 102.

FIG. 2 is a diagram illustrating exemplary consecutive video frames for noise reduction operations, in connection with an embodiment of the invention. Referring to FIG. 2, there is shown a current video frame 204, a previous video frame 202, and a next video frame 206. The current video frame 204 or FRAME n may correspond to a current frame being processed by the video processing block 102 in FIG. 1. The previous video frame 202 or FRAME (n−1) may correspond to an immediately previous frame to the current video frame 204. The next video frame 206 or FRAME (n+1) may correspond to an immediately next frame to the current video frame 204. The previous video frame 202, the current video frame 204, and/or the next video frame 206 may be processed directly from the video input stream or after being buffered in the video processing block 102, for example. The current video frame 204, the previous video frame 206, and the next video frame 208 may comprise luma (Y) and/or chroma (Cb, Cr) information.

Pixels in consecutive video frames are said to be collocated when having the same frame location, that is, . . . , Pn−1(x, y), Pn (x, y), Pn+1 (x, y), . . . , where Pn−1 indicates a pixel value in the previous video frame 202, Pn indicates a pixel value in the current video frame 204, Pn+1 indicates a pixel value in the next video frame 206, and (x, y) is the common frame location between pixels. As shown in FIG. 2, for the frame location (x, y) is such that x=0, 1, . . . , W−1 and y=0, 1, . . . , H−1, where W is the picture width and H is the picture height, for example.

Operations of the video processing block 102 in FIG. 1 need not be limited to the use of exemplary consecutive video frames as illustrated in FIG. 2. For example, the video processing block 102 may perform filtering operations on consecutive video fields of the same parity, that is, on consecutive top fields or consecutive bottom fields. Accordingly, notions of difference between the terms frame and field should not limit the scope of various aspects of the present invention. When performing noise reduction operations on consecutive video fields of the same parity, pixels in the video processing block 102 are said to be collocated when having the same field location, that is, . . . , Pn−1(x, y), Pn (x, y),Pn+1 (x ,y), . . . , where Pn−1 indicates a pixel value in a previous video field, Pn indicates a pixel value in a current video field, Pn+1 indicates a pixel value in a next video field, and (x, y) is the common field location between pixels.

FIG. 3A is a block diagram of an exemplary finite impulse response (FIR) filtering system with noise reduction, in accordance with an embodiment of the invention. Referring to FIG. 3A, there is shown an FIR filtering system 310 that may comprise a motion metric (MM) calculation block 312a and an FIR noise reduction (FIR-NR) block 314. The FIR filtering system 310 may be implemented as a portion of the video processing block 102 in FIG. 1, for example. The MM calculation block 312a may comprise suitable logic, circuitry, and/or code that may be adapted to determine a motion metric (MM) parameter based on contents from a current pixel, Pn, a previous collocated pixel, Pn−1, and a next collocated pixel, Pn+1. The MM calculation block 312a may utilize the MM parameter to determine an FIR blending factor, αfir.

The FIR blending factor, αfir, may be determined by a mapping operation of the motion information. This mapping operation may respond rapidly to motion to avoid unnecessary filtering in moving areas, for example. The FIR-NR block 314 may comprise suitable logic, circuitry, and/or code that may be adapted to FIR filter the current pixel, Pn. The FIR-NR block 314 may be adapted to perform a 3-tap FIR filtering operation given by the expression:
Pn,fir(x,y)=c0·Pn−1(x,y)+c1·Pn(x,y)+c2·Pn+1(x,y), (1)
where c0, c1, and c2 are the 3-tap FIR filter coefficients. In this regard, the FIR filter coefficients may be stored in at least a portion of the registers 110 in FIG. 1, for example. The FIR-NR block 314 may be adapted to generate an FIR-blended current pixel, Pn,outfir, based on the expression:
Pn,outfir(x,y)=αfir·Pn(x,y)+(1−αfir)·Pn,fir(x,y), (2)
where αfir is the FIR blending factor generated by the MM calculation block 312a. In this regard, equation (2) blends or combines the values of the current pixel and the FIR-filtered current pixel generated in equation (1). The level of blending provided by equation (2) is based on the value of the FIR blending factor, αfir.

In operation, the MM calculation block 312a and the FIR-NR block 314 may receive the current pixel, Pn, the previous collocated pixel, Pn−1, and the next collocated pixel, Pn+1. The MM calculation block 312a may utilize the contents of the received pixels to generate the FIR blending factor, αfir, The FIR-NR block 314 may utilize the contents of the received pixels to generate the FIR-filtered current pixel in accordance with equation (1). The FIR-NR block 314 may utilize the results from equation (1) and the FIR blending factor, αfir, generated by the MM calculation block 312a to generate the FIR-blended current pixel, Pn,outfir, in accordance with equation (2).

FIG. 3B is a block diagram of an exemplary finite impulse response (FIR) filtering system with noise reduction and frame storage, in accordance with an embodiment of the invention. Referring to FIG. 3B, there is shown an FIR filtering system 320 that may comprise the MM calculation block 312a and the FIR-NR block 314 in FIG. 3A and a memory 316. The FIR filtering system 320 may be implemented as a portion of the video processing block 102 in FIG. 1, for example. The memory 316 may comprise suitable logic, circuitry, and/or code that may be adapted to store at least a portion of video frames or video fields from the video input stream. The memory 316 may be adapted to store consecutive collocated pixels from the video input stream or from a buffered portion of the video input stream, for example. The memory 316 may be adapted to transfer stored pixels to the MM calculation block 312a and to the FIR-NR block 314 for processing.

In operation, the previous collocated pixel, Pn−1, may be received first and may be stored in the memory 316. The current pixel, Pn, may be received next and may also be stored in the memory 316. When the next collocated pixel, Pn+1, is received by the FIR filtering system 320, all three pixels necessary to generate the FIR blending factor, αfir. and to perform the operations described in equation (1) and equation (2) have been received. The next collocated pixel, Pn+1, may be transferred directly to the MM calculation block 312a and to the FIR-NR block 314 for processing. The current pixel, Pn, and the previous collocated pixel, Pn−1, may also be transferred from the memory 316 to the MM calculation block 312a and to the FIR-NR block 314 for processing. The next collocated pixel, Pn+1, may be stored in the memory 316 to be utilized as a current pixel and/or a previous collocated pixel in a subsequent operation of the FIR filtering system 320. In this regard, when the next collocated pixel, Pn+1, is being received and stored, the previous collocated pixel, Pn−1, and the current collocated pixel, Pn, may be fetched from the memory 316 for processing with the next collocated pixel, Pn+1, in the MM calculation block 312a and the FIR-NR block 314. Moreover, calculation of the motion metric by the MM calculation block 312a may require that a region of pixels in a neighborhood around the next collocated pixel, Pn+1, the previous collocated pixel, Pn−1, and the current collocated pixel, Pn, also be stored in the memory 316 and also be fetched from the memory 316 at the appropriate instance.

Motion-adaptive FIR-based filtering systems, such as those described in FIGS. 3A-3B may generally provide filtered outputs with few motion trail artifacts but may be limited in the amount of noise that may be reduced even for static areas in the video signal.

FIG. 3C is a block diagram of an exemplary infinite impulse response (IIR) filtering system with noise reduction, in accordance with an embodiment of the invention. Referring to FIG. 3C, there is shown an IIR filtering system 330 that may comprise an MM calculation block 312b, an IIR noise reduction (IIR-NR) block 318, and a delay block 320. The IIR filtering system 330 may be implemented as a portion of the video processing block 102 in FIG. 1, for example. The MM calculation block 312b may comprise suitable logic, circuitry, and/or code that may be adapted to determine a motion metric (MM) parameter based on contents from a current pixel, Pn, and from an IlR-filtered previous collocated pixel, P′n−1. The MM calculation block 312b may utilize the MM parameter to determine an IIR blending factor, αiir. The IIR blending factor, αiir, may be determined by a mapping operation of the motion information. This mapping operation may respond rapidly to motion to avoid unnecessary filtering in moving areas, for example.

The IIR-NR block 318 may comprise suitable logic, circuitry, and/or code that may be adapted to IIR filter the current pixel, Pn. The IIR-NR block 318 may also be adapted to generate an IIR-blended current pixel given by the expression:
P′n,outiir(x,y)=αiir·Pn(x,y)+(1−αiir)·P′n−1,outiir(x,y), (3)
where the IIR blending factor, αiir, controls the contribution of the IIR-filtered previous collocated pixel, P′n−1, to the IIR-blended current pixel. The delay block 320 may comprise suitable logic, circuitry, and/or code that may be adapted to delay by one video frame or video field the transfer of the recursive feedback from the output of the IIR-NR block 318 to the MM calculation block 312b and to the input of the IIR-NR block 318. In this regard, both the MM calculation block 312b and the IIR-NR block 318 utilize a recursive feedback operation based on the IlR-filtered previous collocated pixel, P′n−1.

In operation, the current pixel, Pn, and the IIR-filtered previous collocated pixel, P′n−1, are received by the MM calculation block 312b and the IIR-NR block 318. The MM calculation block 312b may generate the IIR blending factor, αiir. The IIR-NR block 318 may IIR filter the current pixel, Pn, and may utilize the IIR-filtered current pixel and the IlR-filtered previous collocated pixel, P′n−1, to perform the operation described by equation (3). The resulting IIR-blended current pixel may be transferred to the delay block 320 and may be utilized as the IIR-filtered previous collocated pixel, P′n−1, for a subsequent operation in the IIR filtering system 330.

Motion-adaptive IIR filtering methods may achieve significant noise reduction but may result in artifacts such as motion trails and/or blurring of moving objects. To avoid these motion artifacts, IIR noise reduction operations may be configured conservatively, limiting, in some instances, the ability to reduce analog noise components.

FIG. 4A is a block diagram of an exemplary FIR-IIR blended filtering system with noise reduction, in accordance with an embodiment of the invention. Referring to FIG. 4A, there is shown an FIR-IIR blended filtering system 400 that may comprise a multiplexer (MUX) 402, an MM calculation block 404, an FIR-NR block 406, an IIR-NR block 408, an FIR-IIR blending block 410, and a delay block 412. The FIR-IIR blended filtering system 400 may be implemented as a portion of the video processing block 102 in FIG. 1, for example.

The MUX 402 may comprise suitable logic, circuitry, and/code that may be adapted to select the inputs to the MM calculations block 404 in accordance with a filtering mode. The MUX 402 may be adapted to select a previous collocated pixel, Pn−1, a current pixel, Pn, and a next collocated pixel, Pn+1, when an FIR filtering mode is selected. The MUX 402 may be adapted to select the current pixel, Pn, and the IIR-filtered previous collocated pixel, P′n−1, when an IIR filtering mode is selected. When an adaptive FIR-IIR filtering mode is selected, the MUX 402 may be adapted to first select the pixels necessary for FIR filtering and then select the pixels necessary for IIR filtering. In another embodiment of the invention, when the adaptive FIR-IIR filtering mode is selected, the MUX 402 may be adapted to first select the pixels necessary for IIR filtering and then select the pixels necessary for FIR filtering.

In another embodiment of the invention, when the adaptive FIR-IIR filtering mode is selected, for example, the MUX 402 may enable selection of the IIR-filtered previous collocated pixel, P′n−1, a current pixel, Pn, and a next collocated pixel, Pn+1,

The MM calculation block 404 may comprise suitable logic, circuitry, and/or code that may be adapted to determine a motion metric (MM) parameter based on contents from at least one of the current pixel, Pn, the previous collocated pixel, Pn−1, the next collocated pixel, Pn+1, and the llR-filtered previous collocated pixel, P′n−1. The MM calculation block 404 may be adapted to generate a different MM parameter for each of the filtering modes supported by the FIR-IIR blended filtering system 400. For example, when the FIR-IIR blended filtering system 400 supports an FIR filtering mode, an IIR filtering mode, and an adaptive FIR-IIR filtering mode, the MM calculation block 404 may be adapted to determine three different MM parameters. The MM calculation block 404 may be adapted to generate an FIR blending factor, αfir, an IIR blending factor, αiir, and/or an adaptive FIR-IIR blending factor, αadaptive. The MM calculation block 404 may generate the blending factors based on the MM parameter for the filtering mode selected, for example.

The MM parameter generated by the MM calculation block 404 may comprise a luminance (Y) component, MMy(x, y), and two chrominance (Cb, Cr) components, MMCb(x,y) and MMCr(x, y). The luminance component of the MM parameter may be determined based on the expression:

MMY(x,y)=1wΧh|(i,j)∑Diffn(i,j),(4)
where w and h are the width and height of a window or neighborhood around the pixel location (x, y), i and j may correspond to indices that may be utilized to identify the location of pixels in the neighborhood, Diffn(i, j) is a differential variable that may be determined in accordance with the filtering mode selected, and Σ|Diffn(i, j)| is a sum of the absolute values of the differential variables determined in the neighborhood of size wxh. The neighborhood size may be determined by taking into consideration the effect on moving impulses, generally thin edges, and/or the effect on smoothing out noise, for example. Some exemplary neighborhood sizes may be 3Χ3, 5Χ3, 3Χ5, 7Χ3, 5Χ5, 7Χ5, and 7Χ7, for example. Selection of a neighborhood size may depend, at least in part, on implementation requirements.

The values of Diffn(i,j) in equation (4) may be determined based on the following expressions:
Diffn(i,j)=2*(|Pn(i,j)−Pn−1(i,j)|+|Pn(i,j)−Pn+1(i,j)|), (5)
Diffn(i,j)=4*(|Pn(i,j)−P′n−1(i,j)|), (6)
Diffn(i,j)=2*(|Pn(i,j)−P′n−1(i,j)|+|Pn(i,j)−Pn+1(i,j)|), (7)
where equation (5) may be utilized when the FIR filtering mode is selected, equation (6) may be utilized when the IIR filtering mode is selected, and equation (7) may be utilized when the adaptive FIR-IIR filtering mode is selected. The factor 2 in equation (5) and equation (7) and the factor 4 in equation (6) may depend on the implementation of the FIR-IIR blended filtering system 400 and may be utilized to maintain a specified precision for integer operations. In this regard, the factors in equation (5), equation (7), and equation (6) need not be limited to the examples provided.

The chrominance components of the MM parameter, MMCb(x, y) and MMCr(x, y), may be determined by following an approach substantially as described for determining equation (4). In this regard, determining the chrominance components may require consideration of the lower resolution of the chrominance components to the luma component in 4:2:2 video format, for example. The MM parameter determined by the MM calculation block 404 may be given by the expression:
MM(x,y)=w0·MML(x,y)+w1·MMCb(x,y)+w2·MMCr(x,y), (8)
where w0, w1, and w2 are weight factors that may be utilized to value differently the contribution of the luminance and chrominance components to the MM parameter. The weight factors w0, w1, and w2 may satisfy the conditions that w0+w1+w2=1. When setting w0>w1, and w0>w2, the luma component may contribute more than the chroma component, for example. The weight factors w0, w1, and w2 may be stored in the registers 110 in FIG. 1, for example.

The MM calculation block 404 may be adapted to generate the blending factors αfir, αiir, and αadaptive based on the following expression:
α=K0(1−(K1/MM2)), (9)
where K0 and K1, are factors determined for each of the blending factors and MM is the MM parameter determined in equation (8) for a selected filtering mode. For example, the factors K0, FIR and K1, FIR may be utilized to determine αfir, the factors K0, IIR and K1, IIR may be utilized to determine αiir, and the factors K0, adaptive and K1, adaptive may be utilized to determine αadaptive. The non-linearity of equation (9) may enable the blending factors to increase more rapidly as the MM parameter increases and avoid artifacts such as motion blurriness or motion trails for moving objects, for example. Moreover, the non-linear behavior of the blending factors may allow moving content to retain its sharpness.

The MM calculation block 404 may also be adapted to generate noise levels for a plurality of noise level intervals that may be utilized to determine and/or detect the analog video noise level in a current video field or video frame. In this regard, the MM calculation block 404 may utilize the MM parameters and may collect and accumulate the MM parameters into corresponding noise level intervals to determine the noise level corresponding to each of the noise level intervals. The noise level intervals may be determined from information stored in at least a portion of the registers 110. For example, the registers 110 may comprise information regarding the number of noise level intervals, the noise level interval lower threshold, NOISE_RANGE_LOWER_THD, and/or the noise level interval upper threshold, NOISE_RANGE_UPPER_THD. The MM calculation block 404 may generate the noise levels for each of the noise level intervals and may store the results in at least a portion of the registers 110, for example. In this regard, the processor 104 may utilize the noise levels determined by the MM calculation block 404 by retrieving the information from the registers 110, for example.

The FIR-NR block 406 may comprise suitable logic, circuitry, and/or code that may be adapted to generate an FIR-blended current pixel, Pn,outfir, in accordance with equation (1) and equation (2) and utilizing the FIR blending factor, αfir, generated by the MM calculation block 404. The FIR-NR block 406 may receive the current pixel, Pn, the previous collocated pixel, Pn−1, and the next collocated pixel, Pn+1, directly from the video input stream or from the input buffer 112 in FIG. 1, for example. In some implementations, at least a portion of the received data, such as the value of the current pixel, Pn, and the value of the previous collocated pixel, Pn−1, for example, may be fetched from the memory 106 in FIG. 1 to the input buffer 112 in the video processing block 102, for example. The FIR-NR block 406 may transfer the FIR-blended current pixel, Pn,outfir, to the FIR-IIR blending block 410 for processing.

The IIR-NR block 408 may comprise suitable logic, circuitry, and/or code that may be adapted to generate an IIR-blended current pixel, P′n,outiir, in accordance with equation (3) and utilizing the IIR blending factor, αiir, generated by the MM calculation block 404. The IIR-NR block 408 may receive the current pixel, Pn, directly from the video input stream or from the input buffer 112 in FIG. 1, for example. The IIR-NR block 408 may receive IIR-filtered previous collocated pixel, P′n−1, from the delay block 412. The IIR-NR block 408 may transfer the IIR-blended current pixel, P′n,outiir, to the FIR-IIR blending block 410 for processing and to the delay block 412 for storage. The delay block 412 may comprise suitable logic, circuitry, and/or code that may be adapted to store the IIR-blended current pixel, P′n,outiir, for one video frame or video field. After one video frame or video field, the IIR-blended current pixel, P′n,outiir, stored in the delay block 412 may correspond to the IlR-filtered previous collocated pixel, P′n−1. The delay block 412 may be adapted to transfer the IIR-filtered previous collocated pixel, P′n−1, to the MUX 402 and to the IIR-NR block 408 for processing.

The FIR-IIR blending block 410 may comprise suitable logic, circuitry, and/or code that may be adapted to receive the FIR-blended current pixel, Pn,outfir, from the FIR-NR block 406 and the IIR-blended current pixel, P′n,outiir, from the IIR-NR block 408 and generate a filtered output pixel, Pn,out. In this regard, the FIR-IIR blending block 410 may utilize the adaptive FIR-IIR blending factor, αadaptive, generated by the MM calculation block 404. The filtered output pixel, Pn,out, may be generated in accordance with the following expression:
Pn,out(x,y)=αadaptive·Pn,outfir(x,y)+(1−αadaptive)·P′n,outiir(x,y) (10)
where the adaptive FIR-IIR blending factor, αadaptive, blends the values of the FIR-blended current pixel, Pn,outfir, and the IIR-blended current pixel, P′n,outiir.
In operation, the current pixel, Pn, the previous collocated pixel, Pn−1, the next collocated pixel, Pn+1, and the IIR-filtered previous collocated pixel, P′n−1, may be received by the MUX 402. The filtering mode may be selected and the appropriate pixel values may be transferred from the MUX 402 to the MM calculation block 404. The MM calculation block 404 may determine the MM parameter based on the filtering mode selected and may generate the blending factors αfir, αiir, and αadaptive. The MM calculation block 404 may transfer the corresponding blending factor to the FIR-NR block 406, the IIR-NR block 408, and the FIR-IIR blending block 410. The FIR-NR block 406 may FIR filter the current pixel, Pn, and generate the FIR-blended current pixel, Pn,outfir, based on the FIR blending factor, αfir. The IIR-NR block 408 may IIR filter the current pixel, Pn, and generate the IIR-blended current pixel, P′n,outiir, based on the IIR blending factor, αiir. The IIR-blended current pixel, P′n,outiir, may be transferred to the delay block 412. The FIR-IIR blending block 410 may receive the FIR-blended current pixel, Pn,outfir, and the IIR-blended current pixel, P′n,outiir, and may generate the filtered output pixel, Pn,out, by utilizing the adaptive FIR-IIR blending factor, αadaptive, generated by the MM calculation block 404.

FIG. 4B is a block diagram of an exemplary FIR-IIR blended filtering system with noise reduction and frame storage for IIR filtering feedback, in accordance with an embodiment of the invention. Referring to FIG. 4B, there is shown an FIR-IIR blended filtering system 420 that may comprise the MUX 402, the MM calculation block 404, the FIR-NR block 406, the IIR-NR block 408, the FIR-IIR blending block 410, and a memory 414. The FIR-IIR blended filtering system 420 may be implemented as a portion of the video processing block 102 in FIG. 1, for example. The memory 414 may comprise suitable logic, circuitry, and/or code that may be adapted to store at least a portion of consecutive video frames or video fields. The memory 414 may be adapted to store a current pixel, Pn, a previous collocated pixel, Pn−1, and an IIR-blended current pixel, P′n,outiir, for example. After one video frame or video field delay, the IIR-blended current pixel, P′n,outiir, stored in the memory 414 may correspond to an llR-filtered previous collocated pixel, P′n−1.

In operation, the previous collocated pixel, Pn−1, may be received first and may be stored in the memory 414. The current pixel, Pn, may be received next and may also be stored in the memory 414. The IIR-blended current pixel, P′n,outiir, may be stored in the memory 414 after being generated in a previous filtering operation by the FIR-IIR blended filtering system 420. When the next collocated pixel, Pn+1, is received, all necessary pixel values for generating the current filtered output pixel, Pn,out, are available to the FIR-IIR blended filtering system 420. The previous collocated pixel, Pn−1, the current pixel, Pn, and the IlR-filtered previous collocated pixel, P′n−1, may be transferred from the memory 414 to the MUX 402, the FIR-NR block 406, and/or the IIR-NR block 408. In this regard, the operations for generating the current filtered output pixel, Pn,out, by the FIR-IIR blended filtering system 420 may be substantially as described in FIG. 4A.

FIG. 4C is a block diagram of an exemplary FIR-IIR blended filtering system with noise reduction and frame storage for FIR-IIR filtering feedback, in accordance with an embodiment of the invention. Referring to FIG. 4C, there is shown an FIR-IIR blended filtering system 430 that may comprise the MUX 402, the MM calculation block 404, the FIR-NR block 406, the IIR-NR block 408, the FIR-IIR blending block 410, and the memory 414. The FIR-IIR blended filtering system 430 may be implemented as a portion of the video processing block 102 in FIG. 1, for example. The memory 414 in FIG. 4C may be adapted to store a current pixel, Pn, a previous collocated pixel, Pn−1, and a filtered output pixel, Pn,out, from an immediately previous operation by the FIR-IIR blended filtering system 430, for example. After a video frame or video field, the filtered output pixel, Pn,out, stored in the memory 414 may correspond to a previous filtered output pixel, Pn−1,out. The IIR-NR block 408 in FIG. 4C may be adapted to generate an IIR-blended current pixel, P′n,outiir, based on the current pixel, Pn, and the previous filtered output pixel, Pn−1,out.

In operation, the previous collocated pixel, Pn−1, may be received first and may be stored in the memory 414. The current pixel, Pn, may be received next and may also be stored in the memory 414. The filtered output pixel, Pn,out, from an immediately previous filtering operation by the FIR-IIR blended filtering system 430 may be stored in the memory 414. When the next collocated pixel, Pn+1, is received, all necessary pixel values for generating the current filtered output pixel, Pn,out, are available to the FIR-IIR blended filtering system 430. The previous collocated pixel, Pn−1, the current pixel, Pn, and the previous filtered output pixel, Pn−1,out, may be transferred from the memory 414 to the MUX 402, the FIR-NR block 406, and/or the IIR-NR block 408. In this regard, the operations for generating the current filtered output pixel, Pn,out, by the FIR-IIR blended filtering system 430 may be substantially as described in FIG. 4A. In some instances, the performance of the FIR-IIR blended filtering system 420 in FIG. 4B may provide better noise reduction operations for a wide range of motion conditions than the FIR-IIR blended filtering system 430 in FIG. 4C. In this regard, the selection of the FIR-IIR blended filtering system 420 or the FIR-IIR blended filtering system 430 may be based on system requirements and/or architectural implementations, for example.

FIG. 4D is a block diagram of an exemplary FIR-IIR blended filtering system with noise reduction and frame storage for IIR filtering or FIR-IIR filtering feedback, in accordance with an embodiment of the invention. Referring to FIG. 4D, there is shown an FIR-IIR blended filtering system 440 that may comprise the MUX 402, the MM calculation block 404, the FIR-NR block 406, the IIR-NR block 408, the FIR-IIR blending block 410, the memory 414, and a multiplexer (MUX) 416. The FIR-IIR blended filtering system 440 may be implemented as a portion of the video processing block 102 in FIG. 1, for example. The MUX 416 may comprise suitable logic, circuitry, and/or code that may be adapted to select between storing into the memory 414 a filtered output pixel, Pn,out, from the FIR-IIR blending block 410 or an IIR-blended current pixel, P′n,outiir, from the IIR-NR block 408. In this regard, the MUX 416 may be utilized to select a feedback mode of operation for the FIR-IIR blended filtering system 440.

The memory 414 in FIG. 4D may be adapted to store a current pixel, Pn, a previous collocated pixel, Pn−1, a filtered output pixel, Pn,out, from an immediately previous filtering operation by the FIR-IIR blended filtering system 440, and/or an IIR-blended current pixel, P′n,outiir, for example. When the filtered output pixel, Pn,out, is selected for storage by the MUX 416, after one video frame or video field the filtered output pixel, Pn,out, stored in the memory 414 may correspond to a previous filtered output pixel, Pn−1,out. Similarly, when the IIR-blended current pixel, P′n,outiir, is selected for storage by the MUX 416, after one video frame or video field the IIR-blended current pixel, P′n,outiir, stored in the memory 414 may correspond to an IlR-filtered previous collocated pixel, P′n−1. The IIR-NR block 408 in FIG. 4D may be adapted to generate an IIR-blended current pixel, P′n,outiir, based on the current pixel, Pn, and either the previous filtered output pixel, Pn−1,out, or the IlR-filtered previous collocated pixel, P′n−1, in accordance with the feedback mode selection.

In operation, the previous collocated pixel, Pn−1, may be received first and may be stored in the memory 414. The current pixel, Pn, may be received next and may also be stored in the memory 414. The MUX 416 may select to store in the memory 414 the filtered output pixel, Pn,out, from an immediately previous filtering operation by the FIR-IIR blended filtering system 430. In the alternative, the MUX 416 may select to store in the memory 414 the IIR-blended current pixel, P′n,outiir. When the next collocated pixel, Pn+1, is received, all necessary pixel values for generating the current filtered output pixel, Pn,out, are available to the FIR-IIR blended filtering system 430. The previous collocated pixel, Pn−1, the current pixel, Pn, and the previous filtered output pixel, Pn−1,out, or the IlR-filtered previous collocated pixel, P′n−1, may be transferred from the memory 414 to the MUX 402, the FIR-NR block 406, and/or the IIR-NR block 408. In this regard, the operations for generating the current filtered output pixel, Pn,out, by the FIR-IIR blended filtering system 440 may be substantially as described in FIG. 4A.

FIG. 5 is a flow diagram with exemplary steps illustrating the operation of the FIR-IIR blended filtering system, in accordance with an embodiment of the invention. Referring to FIG. 5, there is shown a flow diagram 500. In step 504, after start step 502, the processor 104 in FIG. 1 may select a filtering mode of operation. The processor 104 may select between an FIR filtering mode, an IIR filtering mode, and an adaptive FIR-IIR filtering mode. The selected filtering mode may be utilized to control the operation of the MUX 402 in FIG. 4A, for example.

In step 506, the MM calculation block 404 may utilize the pixel information received from the MUX 402 to generate the appropriate MM parameter in accordance with the selected filtering mode. The MM calculation block 404 may generate the appropriate blending factors based on the generated MM parameter. For example, for the FIR blending mode, the FIR blending factor, αfir, may be generated and the adaptive FIR-IIR blending factor, αadaptive, may be set to 1. This approach may result in a filtered output pixel, Pn,out, in equation (10) that may depend on the FIR-blended current pixel, Pn,outfir, generated by the FIR-NR block 406. In another example, for the IIR blending mode, the IIR blending factor, αiir, may be generated and the adaptive FIR-IIR blending factor, αadaptive, may be set to 0. This approach may result in a filtered output pixel, Pn,out, in equation (10) that may depend on the IIR-blended current pixel, P′n,outiir, generated by the IIR-NR block 408. In another example, for the adaptive FIR-IIR filtering mode, the blending factors αfir, αiir, and αadaptive may be generated by the MM calculation block 404.

In step 508, the FIR-NR block 406 may FIR filter the current pixel, Pn, based on filter coefficients provided from the registers 110 in FIG. 1 and the values of the previous collocated pixel, Pn−1, and the next collocated pixel, Pn+1. The IIR-NR block 408 may IIR filter the current pixel, Pn, by recursive feedback of the IIR-filtered previous collocated pixel, P′n−1. In step 510, the FIR-NR block 406 may generate the FIR-blended current pixel, Pn,outfir, and the IIR-NR block 408 may generate the IIR-blended current pixel, P′n,outfir In this regard, the FIR-blended current pixel, Pn,outiir, may correspond to a first blended current pixel for an FIR-IIR blended filtering system and the IIR-blended current pixel, P′n,outiir, may correspond to a second blended current pixel for the FIR-IIR blended filtering system.

In step 512, the FIR-IIR blending block 410 may generate the filtered output pixel, Pn,out, by blending the FIR-blended current pixel, Pn,outfir, from the FIR-NR block 406 and the IIR-blended current pixel, P′n,outiir, from the IIR-NR block 408 based on the adaptive FIR-IIR blending factor, αadaptive. In step 514, the filtered output pixel, Pn,out, or the IIR-blended current pixel, P′n,outiir, may be stored in the memory 414 for subsequent filtering operations. In this regard, the MUX 416 in FIG. 4D may be utilized to select a feedback mode of operation that may best suit the operational and/or architectural requirements of the system. After step 514, the process may proceed to end step 516.

Accordingly, the present invention may be realized in hardware, software, or a combination thereof. The present invention may be realized in a centralized fashion in at least one computer system, or in a distributed fashion where different elements may be spread across several interconnected computer systems. Any kind of computer system or other apparatus adapted for carrying out the methods described herein may be suited. A typical combination of hardware and software may be a general-purpose computer system with a computer program that, when being loaded and executed, may control the computer system such that it carries out the methods described herein.

The present invention may also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods described herein, and which when loaded in a computer system is able to carry out these methods. Computer program in the present context means any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: a) conversion to another language, code or notation; b) reproduction in a different material form.

While the present invention has been described with reference to certain embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the present invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present invention without departing from its scope. Therefore, it is intended that the present invention not be limited to the particular embodiment disclosed, but that the present invention will include all embodiments falling within the scope of the appended claims.