By using a proprietary formal engine that was developed specifically for constraint verification we do not inundate designers with noise. Subtle issues are flagged by our Confirm product that goes the extra mile to establish constraint correctness.

What cannot be proven formally is converted into a System Verilog Assertion. The SVA generated by Confirm is integrated into an RTL simulation environment to establish constraint correctness while reusing your existing regressions. Confirm does not synthesize RTL to gates and so its integration with an RTL simulator is seamless – the SVA generated by Confirm is compact and unimpacted by logic-cone complexity because we can refer to any of the RTL nets on a design. Refocus allows us to map gate-level constraints to RTL allowing SDC signoff using RTL.

FishTail’s SDC Verification flow reads the RTL description for a design along with either gate or RTL level Tcl constraints. Refocus maps the constraints to the design, flagging syntax and constraint application issues. The constraint are formally proven using Confirm and issues are presented to an engineer for review using a powerful debug environment. Constraints that fail formal proof are converted into assertions generated by Confirm and integrated into RTL simulation.