Every time I look at the design and verification tools of today, I think to myself that it's not-so-long ago that I was designing my first ASICs as gate-level schematics using nothing but pencil-and-paper. No synthesis, simulation, timing analysis, or whatever -- you name it (in design tools) and we didn't have it.

Now I look at the tools of today and they simply blow me away -- and I think that we're still in the "early days" -- I cannot even imagine what the tool landscape will look like in 5, 10, 15, 20... years time...