Single-molecule nanotube oscillator ripe for CMOS

Portland, Ore. -- IBM Corp.'s T.J. Watson Research Center has crafted an experimental IC that uses a single-molecule nanotube as the common transistor channel for five CMOS-like inverters wired as a ring oscillator. The fully integrated device, which reportedly runs 400,000 times faster than the fastest nanotube-based circuits developed at other labs, could serve as a blueprint for integrating nanotube transistors into production CMOS chips.

Experimental methods of adding nanotube-based transistors to standard CMOS circuits have been tried at IBM and elsewhere, but all have had to fall back on manual manipulations with an atomic-force microscope or have had to resort to exotic processing steps. But the new work demonstrates that fully integrated circuits are possible by growing nanotubes in place on a standard silicon substrate and then adding metallization layers using standard photolithographic techniques. It also demonstrates that standard CMOS circuitry can be crafted with the nanotube serving as the channel for both p-and n-type transistors.

The work builds on an achievement declared in 2001, when IBM demonstrated the use of nanotubes to enable a transistor channel measuring 15 angstroms (1.5 nanometers)--over 40 times smaller than the tiniest features on today's state-of-the-art 65-nm silicon ICs. The ring oscillator experiment "was a difficult project, with many troublesome process steps, but the performance we gained was better than anyone else has achieved before," said Phaedon Avouris, an IBM fellow and manager of the Nanometer Scale Science and Technology program at the T.J. Watson center (Yorktown Heights, N.Y.). "A ring oscillator is the standard way of learning how to optimize a new IC process. We are characterizing the use of nanotubes as an electronic material in real ICs."

Using single-molecule nanotubes for each device on future ICs could simplify manufacturing and provide the kind of rigorous consistency needed to adapt commercial CMOS processes for use with carbon nanotube transistors, Avouris said.

'Positive development'The IBM work is "a positive development, as we have moved nanotubes from the transistor to the circuit level, which enables the industry to begin looking at the system level," said Dean Freeman, research director for Gartner Dataquest.

Earlier efforts to build working circuits from carbon nanotube transistors--including projects at Stanford University and the Netherlands' Delft University of Technology--failed to achieve full integration, instead requiring external wiring to connect the devices into a circuit. As a result of the mismatch between the current-driving capabilities of the tubes' nanoscale channels and those of the millimeter-scale cable, the performance of the prior attempts topped out at 200 Hz.

At 80 MHz, the IBM device's performance "is not state-of-the-art yet," Avouris said. "But we know how to get there from here, because all that remains are engineering problems."

"We think that all we have to do is optimize our current design to get perhaps half-a-gigahertz performance," said Joerg Appenzeller, a member of the technical staff at the T.J. Watson center. "And we already have plans on how to change our design to achieve hundreds of gigahertz."

According to IBM, the limiting factor is not the nanotube, which can switch at up to 1 terahertz (1,000 gigahertz), but the parasitic capacitance that results from the more than 300x size difference between the 15-Å-wide nanotube and the 500-nm-wide electrodes that connect to it.

"For the signal to propagate from inverter to inverter, it had to charge the relatively large capacitance of the gate," said Avouris. That limited performance. "But we know how to make the parasitic capacitance smaller by shrinking the electrodes, and we are re-engineering the basic carbon nanotube transistor design for ultralow parasitic capacitance."

IBM estimates that it will be 10 years before it has fully optimized the process for use with standard CMOS chips. By 2016, however, the International Technology Roadmap for Semiconductors predicts CMOS features will have shrunk below 20 nm, lessening the mismatch between silicon feature sizes and carbon nanotubes.