JESD204B vs. Serial LVDS I/F for wideband data converter apps

JESD204B IntroductionThe JESD204A industry standard for serial interfaces was developed to address the problem of interconnecting the newest wideband data converters with other system ICs in an efficient and cost saving manner. The motivation was to standardize an interface that would reduce the number of digital inputs/outputs between data converters and other devices – such as FPGAs (field-programmable gate arrays) and SoC (system-on-chip) devices – through the use of a scaleable high-speed serial interface.

Trends show that new applications, as well as advances in existing ones, are driving the need for wideband data converters with increasingly higher sampling frequencies and data resolutions. Transmitting data to and from these wideband converters poses a significant design problem as bandwidth limitations of existing I/O technologies force the need for higher pin counts on converter products. Consequently, systems PCB designs have become increasingly more complex in terms of interconnect density. The challenge is routing a large number of high-speed digital signals while managing electrical noise. The ability to offer wideband data converters with Gsps sampling frequencies, using fewer interconnects, simplifies the PCB layout challenges and allows for smaller form factor realization without impacting overall system performance.

Market forces continue to press for more features, functionality, and performance in a given system, driving the need for higher data-handling capacity. The high-speed A/D converter and D/A converter-to-FPGA interface had become a limiting factor in the ability of some system OEMs to meet their next-generation data-intensive demands. The JESD204B serial interface specification was specifically created to help solve this problem by addressing this critical data link. Figure 1 shows typical high-speed converter to FPGA interconnect configurations using JESD204A/B.

Some key end-system applications that are driving the deployment of this specification, as well as a contrast between serial LVDS and JESD204B, are the subject of the remainder of the article.

The applications driving the need for JESD204BWireless infrastructure transceiversOFDM-based technologies such as LTE used in today's wireless infrastructure transceivers use DSP blocks implemented on FPGAs or system-on-chip devices driving antenna array elements to generate beams for each individual subscriber's handset. Each array element can require movement of hundreds of megabytes of data per second between FPGAs and data converters in both transmit or receive modes.

Medical imaging systemsMedical imaging systems including ultrasound, computational tomography (CT) scanners, magnetic resonance imaging (MRI), and others generate many channels of data that flow through a data converter to FPGAs or DSPs. Continually increasing I/O counts are driving up the number of components by requiring the use of interposers to match FPGA and converter pin out and increasing PCB complexity. This adds additional cost and complexity to the customer's system that can be solved by the more efficient JESD204B interface.

Serial LVDS vs. JESD204BChoosing between Series LVDS and JESD204B InterfaceIn order to best select between converter products that use either LVDS or the various versions of the JESD204 serial interface specification, a comparison of the features and capabilities of each interface is useful. A short tabular comparison is provided in Figure 2.

Figure 2. Comparison between the serial LVDS and JESD204 specifications

At the SERDES level, a notable difference between LVDS and JESD204 is the lane data rate, with JESD204 supporting greater than three times the serial link speed per lane when compared with LVDS. When comparing the high-level features like multi-device synchronization, deterministic latency and harmonic clocking, JESD204B is the only interface that provides this functionality. Systems requiring wide bandwidth multichannel converters that are sensitive to deterministic latency across all lanes and channels won't be able to effectively use LVDS or parallel CMOS.