Qflow 1.1: An Open-Source Digital Synthesis Flow

Table of Contents

A digital synthesis flow is a set of tools and methods used
to turn a circuit design written in a high-level behavioral language
like verilog or VHDL into a physical circuit, which
can either be configuration code for an FPGA target like a Xilinx
or Altera chip, or a layout in a specific fabrication process
technology, that would become part of a fabricated circuit chip.
Several digital synthesis flows targeting FPGAs are available,
usually from the FPGA manufacturers, and while they are typically
not open source, they are generally distributed for free (presumably
on the sensible assumption that more people will be buying more
FPGA hardware).

The OpenMSP430 microprocessor from OpenCores, placed and
routed by qflow.

Qflow is a complete tool chain for synthesizing digital
circuits starting from verilog source and ending in physical layout
for a specific target fabrication process. In the world of
commercial electronics, digital synthesis with a target application
of a chip design is usually bundled into
large EDA software systems like Cadence or Synopsys. As commercial
electronics designers need to maintain cutting-edge performance,
these commercial toolchains get more and more expensive, and have
largely priced themselves out of all but the established integrated
circuit manufacturers. This leaves an unfortunate gap where startup
companies and small businesses cannot afford to do any sort of
integrated circuit design. The algorithms for digital synthesis
are all tied up in closed-source software, and development is
controlled by a few EDA software vendors.

From a long time ago, bits and pieces of open source software for
digital synthesis have been developed. The oldest of these are
probably VIS and SIS, two software tools developed at Berkeley for
verilog parsing, logic verification, and mapping of logic onto
a digital standard cell library. They perform the task of logic
optimization and cell mapping admirably. The main drawback of
these tools is that they lack sophistication in dealing with
complicated structures in the verilog source code. The
principal need for the synthesis tool is that it must be able
to map a logic circuit to a standard cell library. For this
reason, a number of open-source parsers like icarus and
cver, which target either FPGAs or executable computer
code, or both, have not been considered for qflow (however, they
are both useful for functional verification of both the source
code and the gate-level netlist; see the tutorial page for
details on running icarus verilog for simulation).

After a thorough investigation of alternatives, I settled on
two good choices for front-end synthesis: The first is a
combination of the open-source verilog parser Odin-II
and optimizer/mapper abc to anchor the digital synthesis
flow. They have the advantage that they are part of an existing
open-source FPGA synthesis flow called vtr
("verilog-to-routing"). The second is a recent entry (2013) into
the field: The extraordinarily capable
yosys.
This is a synthesis tool able to
handle every type of Verilog-2005 syntax, and can synthesize
large projects off of Open Cores. Due to the versatility and
capability of yosys, I have chosen it as the default frontend.
Odin-II and ABC can be specified as an alternative frontend.

Digital standard cell libraries are a major component of the
flow. While synthesis tools can make use of proprietary digital
standard cells provided by various vendors (usually the
fabrication facility, such as X-Fab, or IBM, or TSMC, but
sometimes by 3rd-party vendors), the problem with proprietary
standard cell libraries is that they cannot be distributed, and
cannot therefore be used for examples and posted on public
websites. Fortunately, there have been a few sets of open-source
standard cells for popular processes. Some of these are based
on the "scalable CMOS rules" from MOSIS, a set of design rules
that are more conservative than the vendor rules and are allowed
by the vendors to be distributed openly. Physical layout generated
using the scalable CMOS rules may be distributed as open-source,
and can be fabricated in the processes for which the rules were
designed. For the first distribution of qflow, I am using the
Oklahome State University (OSU) open-source standard cell library.
In the near future, I hope to expand the distribution to include
support for the open-source libraries from VLSI Technology
(vlsitechnology.org), as well as the rest of the OSU standard
cell libraries.

After mapping onto a standard cell library, a design needs to
be placed and routed. The placement stage determines a rough
estimate of the routing required, and tries to put all the
cells into a block, ordering them to minimize the total
amount of wiring connecting all the pins together. A placement
tool known as graywolf was developed (under the name
"TimberWolf") at Yale University, and was distributed as open
source for a time until it was taken commercial. The last
open-source version of this tool does not perform detail
routing, but is a professional-grade placement tool.

The final step in creating a digital standard-cell layout is
the detail route, describing exactly how the physical wiring
should be generated to connect together all the pins in the
design. An open source detail router has been pointedly
missing. Eventually, knowing that an open source digital
synthesis tool flow for chip design would never be created
without one, and deciding that lack of cutting-edge performance
should not be an impediment to the creation of a working flow,
I coded up a moderately capable detail router, called
qrouter, which has now become the final link in the
open source synthesis chain.

It should not be assumed that the qflow tool
chain can be used to create the next generation of
multi-gigahertz microprocessors. But the qflow tool
chain is perfectly capable of handling digital subsystems
needed by many chips, including host-to-device communications
(SPI and I2C, for example), signal processing (digital filters,
sigma-delta modulators), arithmetic logic units, and so forth.
Early versions of the qflow digital flow were used to create
digital circuits used in high-performance commercial integrated
circuits. It's real, and it works!

Qflow is an evolving set of tools that makes use of the best
components that are available, are open-source, and that can
be made to work within the flow. When better alternatives to
any component exist, I will incorporate them into the flow.

Click on Reference here or on
the button in the menu on the left to see how to use qflow.

Qflow itself is a framework for managing a digital synthesis
flow. It contains a number of tools unique to itself, but also
relies on a number of tools that must be obtained elsewhere.

Click on Install here or on
the button in the menu on the left to get installation instructions
for the base qflow tool chain manager.

Required components of qflow: Note that qflow can make use
of both front-end synthesis tools, yosys and Odin_II,
but only one of them is manadatory, and yosys is the
preferred front-end. abc is used by both yosys and
Odin_II, but different versions need to be compiled for
each tool; see details below.

The qflow package contains all the scripts and most of the
tools necessary for the open-source digital synthesis flow.
It also comes with some of the files from the OSU (Oklahoma
State University) 0.35um standard cell library, to provide
a default technology.

Verilog source

You can write your own, or you can download example Verilog
source from the OSU site (see below) or
opencores.org

Warning: Most of the target applications on Open Cores
make extensive use of all the features of Verilog-2005; they
are all easily handled by yosys. The alternative
Odin-II frontend will usually fail to synthesize the Open
Cores sources without some editing of the source code.

Digital standard cell technology

For purposes of experimenting with the flow, qflow provides
a set of files for the OSU 0.35um open-source standard cell set.
This is an excellent source for LEF and GDS standard cells.
The cells are all compatible with the MOSIS SCMOS rules for
the various processes available through MOSIS (mostly TSMC
and AMI, 0.18um to 0.5um). The standard cell set is available
from vlsiarch.ecen.okstate.edu
and is available for download, free of charge
(see also the Flows main page). Look for the "osu_soc"
tarball; as of this writing, the current tarball is
osu_soc_v2.7.tar.gz.
Be aware that this tarball does not extract into its own
directory, so it is recommended to create a directory
called "osu_soc_v2.7", place the tarball into it, and
extract it there.

See the Reference page
for instructions on how to use qflow with a different
technology.

The important components to have (all of which are in the
OSU standard cell sets) are:

This extraordinarily capable verilog parser and logic
synthesizer was written by
Clifford Wolf.
It is an industrial-grade tool that will
synthesize everything from decoders up to microprocessors with
ease and accuracy. The code can be obtained from
the Yosys website.
Click on the "Download" link on the left, and follow instructions
to compile and install. More detailed instructions are available
in the README file in the distribution.

Some previous comments on this page about difficulties in
compiling and installing yosys have been dealt with over
a few version iterations. As of this writing (April 2015),
yosys is in version 0.5, and I have no problems at all
compiling it and all its dependencies. Note that the
default configuration uses the clang compiler; on
a Linux system with a stock gcc compiler, you will want to
first do "make config-gcc" before doing "make".
Otherwise, yosys should compile without complaint.

Note that yosys makes use of the logic optimizer "abc"
(see below), but will download and compile the appropriate
version as part of its make script.

Verilog parser and logic verification (Odin-II)

This Verilog parser, written by Peter Jamieson,
was introduced at FCCM 2010 and continues to undergo
development as part of the FPGA synthesis tool chain VTR.
Obtain Odin-II from Google Code.
You may want to follow the link to the VTR distribution (also
see below), which may contain the most recent code base
for Odin-II.

As of August 2, 2013, the Odin-II developers fixed a
problem that made the Odin-II output incompatible with
qflow. For a while, I posted a patch, but now I recommend
that you make sure that your version of Odin-II post-dates
the change. An additional patch was posted in October
2013.

As of May, 2015, Odin-II is not supported by the qflow
development version 1.1.

Logic optimization (abc)

This tool takes the BLIF format description and creates a
netlist representation using a set of standard cells described
in the "genlib" format, performing logic optimization along
the way. Obtain this tool from
EECS at U.C. Berkeley. Here you will find a
pointer to the latest code download on BitBucket.

The complete FPGA synthesis flow vtr contains both
Odin-II and abc, and can be obtained from
Google Code. In general, this is the best
place to get the most recent sources for both Odin-II and
abc.

Note that yosys also uses abc for combinatorial logic
optimization, but yosys will automatically download and
compile the correct version of abc with the compile-time
options needed by yosys.

Placement (graywolf)

Obtain this tool from GitHub
graywolf.
Specifically, this can be cloned from the git repository using
the command "git clone git://github.com/rubund/graywolf".
Graywolf is the placement tool formerly known as TimberWolf.
It is currently maintained by Ruben Undheim in a much
streamlined form. "cmake" is required to build graywolf.
Graywolf should compile cleanly using "cmake ." and "make",
and install with "make install" to a standard directory
(default /usr/local/).

Detail Router (qrouter 1.3)

Obtain Qrouter 1.3 from OpenCircuitDesign:
Qrouter home page
This is a work in progress, but is a full-featured multi-layer,
sea-of-gates maze router. For a very very long time, a good
open-source maze router was not available anywhere, and it had
been on my list of important things to do for ages. Finally,
in June of 2011, I finally sat down and wrote it. Although
as a starting point it was based on router code by Steve Beccue,
it is totally overhauled and can be considered written from
scratch for all practical purposes. It is a command-line-only
tool, taking standard format (LEF and DEF) files as input and
generating an annotated DEF format file as output.

Static Timing Analysis (vesta)

Vesta is a static timing analysis tool that is part of the
qflow package.