forth

When you develop software, you need some kind of toolchain. For example, to develop for an ARM processor, you need a suitable C compiler, a linker, a library, and a programmer. FPGAs use a similar set of tools. However, instead of converting source code to machine language, these tools map the intent of your source code into configuration of FPGA elements and the connections between them.

There’s some variation, but the basic flow in an FPGA build is to use a synthesizer to convert Verilog or VHDL to a physical design. Then a mapper maps that design to the physical elements available on a particular FPGA. Finally, a place and route step determines how to put those elements in a way that they can be interconnected. The final step is to generate a bitstream the chip understands and somehow loading it to the chip (usually via JTAG or by programming a chip or an external EEPROM).

One problem with making your own tools is that the manufacturers typically hold the bitstream format and other essential details close to their chest. Of course, anything can be reverse engineered (with difficulty) and [James Bowman] was able to build a minimal CPU using an open source Lattice toolchain. The project relies on several open source projects, including IceStorm, which provides configuration tools for Lattice iCE40 FPGAs (there is a very inexpensive development platform available for this device).

We’ve covered IceStorm before. The IceStorm project provides three tools: one to produce the chip’s binary format from an ASCII representation (and the reverse conversion), a programmer for the iCEstick and HX8K development boards, and database that tells other open source tools about the device.

Those tools blend with other open source tools to form a complete toolchain–a great example of open source collaboration. Yosys does the synthesis (one of the tools available on the EDAPlayground site). The place and route is done by Arachne. The combined tools are now sufficient to build the J1A CPU and can even run a simple version of Forth. If you’ve ever wanted to play with an FPGA-based CPU design, you now have a $22 hardware option and free tools.

The 6502 CPU is probably the most famous of all the 8-bit processors out there, whether in the form of bare chips for homebrew computers, or as slightly modified derivative chips found in everything from the C64, the NES, and the BBC Micro. For this edition of the Hacklet, we’re taking a look at all the 6502-based builds on hackaday.io.

There aren’t many transistors on a 6502, making it perfect for implementing on an FPGA. [Michael A. Morris] has an Arduino FPGA shield, and his soft-6502 project is called Cameleon. There’s a bunch of SPI Flash and FRAM on board, and the 128kB of (parallel) SRAM on the board is more than enough to handle any computational task you can throw at it.

Maybe programmable logic isn’t your thing, and you’d just like a simple computer like the Ohio Scientific or the Apple I. The L-Star is for you. That’s [Jac Goudsmit]’s build featuring a 6502, a Parallax Propeller, and little else.

The Parallax Propeller is a powerful (multi-core!) chip that’s easily capable of handling video out, keyboard in, and serving up the ROM and RAM of a computer. [Jac]’s build does it all beautifully, and if you’re looking for the easiest way to run code on a 6502, this is how you do it.

There’s some weird stuff going on in this machine – 18-bit addressing and 80kB of RAM. So far [Eric] has managed to dump the ROM, and he’s taking a look at the floppy controller board to see if he can figure out how it’s mapped. It’s one thing to figure out what’s broken on an Apple II or C64; those are well documented machines. It’s another thing entirely to figure out a machine very few people have heard of, and we tip our hat to [Eric] and his efforts.

Here’s a build that both does and doesn’t have a 6502 in it. [BladeRunner]’s SheMachine is a single board computer that has a 65c816 in it. The ‘816 is an interesting beast that operates as a standard 6502 until a bit is flipped in one of its registers. After that, it has a 24-bit address space for addressing 16 Megabytes of memory, 16-bit registers, but is still completely backwards compatible with the 6502. Yes, it does have weird interleaved address pins, but we can only imagine what the world would be like if this chip came out a few years earlier…

[BladeRunner] is designing the SheMachine with 1MB of SRAM – more than enough, really – and is mapping all the memory through a CPLD. That’s how you should do it, anyway.

Forth is a very interesting programming language. It’s very flexible and is extremely efficient on low powered hardware, but unfortunately not very popular simply due to the fact that it’s not very popular. There were a few Forth-based microcomputers built in the 1980s, but these were largely unsuccessful.

[Leon] is a Forth aficionado and came up with his own Forth development board in the hopes of Forth making a comeback. It’s a very small and cheap board – only about $12 in parts – but it’s still extremely powerful and a fun platform for investigating Forth.

Compared to other programming languages found in 80s microcomputers, Forth is just weird. It’s a stack-based language, so instead of adding two numbers like 3 + 4, Forth uses postfix notation (or Reverse Polish Notation) so the same statement is expressed as 3 4 +. It’s a much more efficient way for computers to handle data, and some claim it’s more efficient for humans as well.

[Leon] created his own board able to be programmed in Forth, shown above, that uses an ATMega328 microcontroller. He’s using AmForth to put Forth on his system, but also extended the base AmForth install with his own floating point version. making this version of Forth at least as powerful as any 80s microcomputer or ATMega development board is today.

[Leon] put together a great demo of the capabilities of Forth and his dev board. You can check that out below.

The Jupiter Ace was a small membrane keyboard, cassette tape drive computer akin to the ZX Spectrum released in 1982. Priced at £90, it was a little more expensive than its home computer contemporaries, but had a very interesting feature: instead of BASIC, the Ace ran Forth. This interpreted stack-based language is far more capable than the BASIC variants found on home computers of the day, but unfortunately the Ace failed simply because Forth was so foreign to most consumers.

Not wanting to let a good idea die, [prof_braino] is bringing Forth back into the modern age. He’s using a Parallax Propeller to emulate a simple home computer running Forth. Instead of a book-sized computer, the new Propeller version runs on a single chip, with 8 CPU cores running 24 times faster than the original, with 32 times more RAM and an SD card for basically unlimited storage.

[James Bowman] of the Willow Garage published a paper on his J1 CPU core for field-programmable gate arrays. This was originally developed and used for the Ethernet cameras on the PR2 (you know, that incredibly expensive beer delivery system?) robot. It uses a 16-bit von Neumann architecture and lacks several processor features you’d expect a CPU to have such as interrupts, multiply and divide, a condition register, and a carry flag. None-the-less, its compact at just 200 lines of Verilog and it can run at 80 MHz. [James] compares the J1 to three different FPGA CPU Cores commonly used and discusses how the system is built in his 4-page paper that has the details you’re interested in but won’t take all day to dig through.