3D NAND Production Starts at Samsung

LONDON — Samsung Electronics Co. Ltd. has begun mass production of a 128 Gbit NAND flash memory that is integrated in multiple layers, and claims that it is the first company to do so.

The memory is based on a charge-trap cell rather than the conventional floating gate non-volatile cell used in 2D NAND flash. In the vertical arrangement this charge-trap cell shows increased reliability between a factor of 2 and a factor of 10 over conventional floating-gate NAND flash memory, Samsung claimed in a press release.

The technology is capable of stacking up 24 layers, but Samsung did not disclose how many layers it had used in its 128 Gbit vertical NAND, nor whether the memory cells are multilevel cell or whether it had relaxed the design geometry from the leading edge in 2D memory, which stands at about 19 or 16 nm.

The company did say that the memory would provide improvements in performance and area ratio, and a V-NAND chip is suitable for a wide range of consumer and commercial applications including embedded NAND storage and solid-state drives.

The V-NAND component has the same memory capacity as a 128 Gbit 2D NAND flash memory announced by Samsung in April 2013 that uses a 3-bit multilevel cell manufactured in a 1X nm manufacturing process; 1X nm implies a geometry somewhere between 10 and 19 nm.

The 128 Gbit V-NAND is made using what Samsung calls charge-trap-flash (CTF) technology and a vertical interconect process to link memory cells. The company claims to have achieved half the die area of a 2X nm class 2D NAND flash. However, Samsung did not compare the 128 Gbit V-NAND against a 2D memory made using 1X nm class manufacturing process.

"Following the world's first mass production of 3D vertical NAND, we will continue to introduce 3D V-NAND products with improved performance and higher density, which will contribute to further growth of the global memory industry," said Jeong-Hyuk Choi, senior vice president responsible for flash products and technology at Samsung, in the press release.

Samsung said that after 10 years of research it has amassed more than 300 patents either pending or granted on 3D memory

Assuming the 24 levels maximum, and a F=50 nm 6F^2 design rule, the maximum 3D density is equivalent to a conventional 12.5 nm floating gate. So the density lead for this case is temporary, until someone (if anyone) hits 10 nm floating gate. Increasing the number of levels or shrinking the 3D NAND design rule could increase costs when the number of steps starts multiplying, e.g., doubling.