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Abstract:

A memory device with improved thermal isolation. The memory cell includes
a first electrode element, having an upper surface; an insulator stack
formed on the first electrode element, including first, second and third
insulating members, all generally planar in form and having a central
cavity formed therein and extending therethrough, wherein the second
insulator member is recessed from the cavity; a phase change element,
generally T-shaped in form, having a base portion extending into the
cavity to make contact with the first electrode element and making
contact with the first and third insulating members, and a crossbar
portion extending over and in contact with the third insulating member,
wherein the base portion of the phase change element, the recessed
portions of the second insulating member and the surfaces of the first
and third insulating members define a thermal isolation void; and a
second electrode formed in contact with the phase change member.

Claims:

1. A method of fabricating a memory device, comprising the steps
of:forming an electrode element, generally tabular in form;forming an
insulator stack, including first, second and third insulating layers, on
the first electrode;etching a cavity through the insulator
stack;selectively etching the second insulator layer to form a recess in
the side of the cavity;depositing a phase change memory element,
extending into the cavity to make contact with the third and first
insulator members and the first electrode member, whereby the phase
change member and the second insulator member define a thermal isolation
void between the third and first insulator members; anddepositing a
second electrode member in contact with the phase change memory element.

2. The method of claim 1, wherein the cavity-etching step and the
selective etching step are combined, the etchant being chosen to provide
a selectively more active etch of the second insulating member.

3. The method of claim 1, wherein the phase-change element is deposited
with a sputtering process, the process being controlled to produce a
reduced cross-sectional area in the portion of the phase-change element
adjacent the recessed second insulating member.

4. The method of claim 1, wherein the phase-change element is deposited in
a generally T-shaped form, with a crossbar member atop the third
insulating member and a central portion extending into the cavity.

5. The method of claim 1, wherein the phase-change element is deposited in
a generally I-shaped form, with a crossbar member atop the third
insulating member, a central portion extending into the cavity, and a
base member underlying the first insulating member.

Description:

REFERENCE TO RELATED APPLICATION

[0001]This application is a divisional of U.S. patent application Ser. No.
11/408,598 filed on 21 Apr. 2006; which application claims the benefit of
U.S. Provisional Patent Application No. 60/739,079 entitled "Improved
Thermal Isolation for an Active-Sidewall Phase Change Memory Cell" filed
on Nov. 21, 2005, each of which is incorporated by reference as if fully
set forth herein.

PARTIES TO A JOINT RESEARCH AGREEMENT

[0002]International Business Machines Corporation, a New York corporation;
Macronix International Corporation, Ltd., a Taiwan corporation, and
Infineon Technologies A.G., a German corporation, are parties to a Joint
Research Agreement.

[0006]Phase change based memory materials are widely used in read-write
optical disks, and such materials are seeing increasing use in computer
memory devices. These materials have at least two solid phases, including
for example a generally amorphous solid phase and a generally crystalline
solid phase. Laser pulses are used in read-write optical disks to switch
between phases and to read the optical properties of the material after
the phase change, and electrical pulses are employed in the same manner
in computer memory devices.

[0007]Phase change based memory materials, like chalcogenide based
materials and similar materials, also can be caused to change phase by
application of electrical current at levels suitable for implementation
in integrated circuits. The generally amorphous state is characterized by
higher resistivity than the generally crystalline state, which can be
readily sensed to indicate data. These properties have generated interest
in using programmable resistive material to form nonvolatile memory
circuits, which can be read and written with random access.

[0008]The change from the amorphous to the crystalline state is generally
a lower current operation. The change from crystalline to amorphous,
referred to as reset herein, is generally a higher current operation,
which includes a short high current density pulse to melt or breakdown
the crystalline structure, after which the phase change material cools
quickly, quenching the phase change process, allowing at least a portion
of the phase change structure to stabilize in the amorphous state. It is
desirable to minimize the magnitude of the reset current used to cause
transition of phase change material from crystalline state to amorphous
state. The magnitude of the reset current needed for reset can be reduced
by reducing the size of the phase change material element in the cell and
of the contact area between electrodes and the phase change material, so
that higher current densities are achieved with small absolute current
values through the phase change material element.

[0010]A specific issue arising from conventional the phase change memory
and structures is the heat sink effect of conventional designs.
Generally, the prior art teaches the use of metallic electrodes on both
sides of the phase change memory element, with electrodes of
approximately the same size as the phase change member. Such electrodes
act as heat sinks, the high heat conductivity of the metal rapidly
drawing heat away from the phase change material. Because the phase
change occurs as a result of heating, the heat sink effect results in a
requirement for higher current, in order to effect the desired phase
change.

[0011]One approach to the heat flow problem is seen in U.S. Pat. No.
6,815,704, entitled "Self Aligned Air-Gap Thermal Insulation for
Nano-scale Insulated Chalcogenide Electronics (NICE) RAM", in which an
attempt is made to isolate the memory cell. That structure, and the
attendant fabrication process, is overly complex, yet it does not promote
minimal current flow in the memory device.

[0012]It is desirable therefore to provide a memory cell structure having
small dimensions and low reset currents, as well as a structure that
addresses the heat conductivity problem, and a method for manufacturing
such structure that meets tight process variation specifications needed
for large-scale memory devices. It is further desirable to provide a
manufacturing process and a structure, which are compatible with
manufacturing of peripheral circuits on the same integrated circuit.

SUMMARY OF THE INVENTION

[0013]An important aspect of the claimed invention is a memory device with
improved thermal isolation. The memory cell includes a first electrode
element, having an upper surface; an insulator stack formed on the first
electrode element, including first, second and third insulating members,
all generally planar in form and having a central cavity formed therein
and extending therethrough, wherein the second insulator member is
recessed from the cavity; a phase change element, generally T-shaped in
form, having a base portion extending into the cavity to make contact
with the first electrode element and making contact with the first and
third insulating members, and a crossbar portion extending over and in
contact with the third insulating member, wherein the base portion of the
phase change element, the recessed portions of the second insulating
member and the surfaces of the first and third insulating members define
a thermal isolation void; and a second electrode formed in contact with
the phase change member.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 is a cross-sectional view that illustrates an embodiment of a
phase change memory element employing a vacuum cell thermal isolation
element.

[0015]FIG. 1a illustrates a current path in a phase change memory element
as shown in FIG. 1.

[0018]The following discussion describes embodiments of the invention with
particular reference to FIGS. 1-3. It will be understood that the
examples and features shown are exemplary and illustrative in nature and
not intended to limit the scope of the invention. That scope is defined
solely by the claims appended hereto.

[0019]The present invention concerns memory elements and memory cells. As
used herein, and as is well known in the art, a memory cell is a circuit
device designed to hold a charge or state to indicate the logic level of
a single data bit. Memory cells are arrayed to provide, for example, the
random access memory for a computer. Within certain memory cells, a
memory element performs the function of actually holding the charge or
state. In a conventional dynamic random access memory cell, for example,
a capacitor indicates the logic level of the cell, with a fully charged
state indicating a logic 1, or high, state, and fully discharged
indicating a logic 0, or low, state.

[0020]A memory element 10, an embodiment of the present invention, is
illustrated generally in FIG. 1. As seen there, the memory element 10 is
shown as a single unit, for purposes of clarity. In practice, each
element is a part of a memory cell, which in turn is part of a larger
memory array, as discussed more fully below. The structure of a memory
element will be discussed first, followed by a description of the process
for fabricating the same.

[0021]The memory element is formed on a substrate 12, which is preferably
a dielectric fill material such as silicon dioxide. Substrate material
surrounds and extends over the lower electrode 14, including an upper
ledge 15 lying over the top of the lower electrode 14. The lower
electrode 14 preferably is formed from a refractory metal such as
tungsten, and it is formed in the oxide layer. Other suitable refractory
metals include Ti, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, and Ru, as well as
oxides and nitrides of such materials. For example, materials such as
TiN, RuO or NiO are known and effective refractory metals.

[0022]Above the lower electrode and in contact with it is a phase change
element 16, generally having a T-shape, with the upright portion in
contact with and extending vertically from the lower electrode, through
the substrate upper ledge 15 overlying the lower electrode. An upper
electrode 26 is formed atop the crossbar portion of the phase change
element.

[0023]The phase change element 16 can be formed from a class of materials
preferably including chalcogenide based materials. Chalcogens include any
of the four elements oxygen (0), sulfur (S), selenium (Se), and tellurium
(Te), forming part of group VI of the periodic table. Chalcogenides
comprise compounds of a chalcogen with a more electropositive element or
radical. Chalcogenide combinations denote chalcogenides amalgamated with
other materials such as transition metals. A chalcogenide combination
usually contains one or more elements from group IV of the periodic table
of elements, such as germanium (Ge) and tin (Sn). Often, chalcogenide
combinations include one or more of antimony (Sb), gallium (Ga), indium
(In), and silver (Ag). Many phase change based memory materials have been
described in technical literature, including combinations of: Ga/Sb,
In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te,
In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S. In the
family of Ge/Sb/Te materials, a wide range of compositions may be
workable. The compositions can be characterized as
TeaGebSb.sub.100-(a+b).

[0024]One researcher has described the most useful combinations as having
an average concentration of Te in the deposited materials well below 70%,
typically below about 60% and ranged in general from as low as about 23%
up to about 58% Te and most preferably about 48% to 58% Te.
Concentrations of Ge were above about 5% and ranged from a low of about
8% to about 30% average in the material, remaining generally below 50%.
Most preferably, concentrations of Ge ranged from about 8% to about 40%.
The remainder of the principal constituent elements in this composition
was Sb. These percentages are atomic percentages that total 100% of the
atoms of the constituent elements. (Ovshinsky '112 patent, cols 10-11.)
Particular combinations evaluated by another researcher include
Ge2Sb2Te5, GeSb2Te4 and GeSb4Te7. (Noboru Yamada, "Potential of Ge-Sb-Te
Phase-Change Optical Disks for High-Data-Rate Recording", SPIE v.3109,
pp. 28-37 (1997).) More generally, a transition metal such as chromium
(Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt)
and mixtures or combinations thereof may be combined with Ge/Sb/Te to
form a phase change material that has programmable resistive properties.
Specific examples of memory materials that may be useful are given in
Ovshinsky '112 at columns 11-13, which examples are hereby incorporated
by reference.

[0025]Phase change materials are capable of being switched between a first
structural state in which the material is in a generally amorphous solid
phase, and a second structural state in which the material is in a
generally crystalline solid phase in its local order in the active
channel region of the cell. These materials are at least bistable. The
term amorphous is used to refer to a relatively less ordered structure,
more disordered than a single crystal, which has detectable
characteristics, such as higher electrical resistivity than the
crystalline phase. The term crystalline is used to refer to a structure
relatively more ordered than in an amorphous state, which has detectable
characteristics such as lower electrical resistivity than the amorphous
phase. Typically, phase change materials may be electrically switched
between different detectable states of local order across the spectrum
between completely amorphous and completely crystalline states. Other
material characteristics affected by the change between amorphous and
crystalline phases include atomic order, free electron density and
activation energy. The material may be switched either into different
solid phases or into mixtures of two or more solid phases, providing a
gray scale between completely amorphous and completely crystalline
states. The electrical properties in the material may vary accordingly.

[0026]Phase change materials can be changed from one phase state to
another by application of electrical pulses. It has been observed that a
shorter, higher amplitude pulse tends to change the phase change material
to a generally amorphous state. A longer, lower amplitude pulse tends to
change the phase change material to a generally crystalline state. The
energy in a shorter, higher amplitude pulse is high enough to allow for
bonds of the crystalline structure to be broken and short enough to
prevent the atoms from realigning into a crystalline state. Appropriate
profiles for pulses can be determined, without undue experimentation,
specifically adapted to a particular phase change combination. In
following sections of the disclosure, the phase change material is
referred to as GST, and it will be understood that other types of phase
change materials can be used. A material useful for implementation of a
phase change element described herein is Ge2Sb2Te5.

[0027]Between the lower electrode and the crossbar of the phase change
element lie three dielectric layers. Immediately above the lower
electrode is the substrate upper ledge 15, as described above. Atop and
formed on the upper ledge is an intermediate dielectric layer 18. Formed
on the intermediate dielectric layer, and extending into contact with the
lower surface of the phase change element, is an upper dielectric layer
24. The upper dielectric layer is preferably composed of the same, or
similar, material as the substrate, such as silicon dioxide, while the
intermediate dielectric is preferably formed of SiN or a similar
material.

[0028]The upper ledge and upper dielectric layer make contact with the
upright portion of the phase change element. The intermediate dielectric
layer, however, does not extend to the phase change element, but rather
that layer is recessed, so that vacuum isolation cell 22 is defined by
the end of the intermediate dielectric layer and the upright portion of
the phase change element, on one axis, and the upper ledge and upper
dielectric layer on the other. This chamber preferably contains a vacuum,
and it provides improved thermal isolation for the phase change element.
In the area adjacent the vacuum isolation cell, the upright portion of
the phase change element is pinched to form neck 20, a zone of reduced
cross-sectional area.

[0029]In operation, current flows through the memory element from lower
electrode 14, into the phase change element 16, and out through the upper
electrode 26. Of course, the current direction could be altered by
changes in element geometry, as will be understood by those in the art.
In either event, the phase change material is subject to joule heating as
current flows, as discussed above, resulting in a temperature rise in the
center of the GST material. When the temperature exceeds the level
required for phase change, a portion of the phase change material changes
state. Temperature is not uniform throughout the phase change element,
with changing values of current density producing significant variations.
The temperature of the phase change material determines the effect
produced, so the current is chosen to produce a temperature sufficient to
create the desired result--either an amorphous state or a crystalline
state--in the GST material. If it is desired to read the element status,
a low current is employed for sensing purposes. The read operation is
non-destructive, as the element temperature is kept below the threshold
for a phase change.

[0030]The vacuum isolation cell 22 functions to contain heat within the
phase change element, which has several positive effects. First, by
preventing the migration of heat away from the phase change element, this
design reduces the total heat required to effect phase changes, which in
turn reduces the current required for each SET or RESET operation. At the
same time, retaining heat within the phase change element reduces the
heat transferred to the remainder of the memory array, which translates
directly into increased lifespan for the device. Given the vast numbers
of memory elements within a complete integrated circuit--at least eight
billion elements for a 1 GB memory device, for example--it can be
appreciated that the effects of such a heat reduction will be
significant. The efficiency of the phase change element is further
enhanced by concentrating the current within the phase change element, in
the area of neck 20. This effect is shown in the detail view of FIG. 1a,
in which arrows enter from electrode 14 (not shown) with a relatively
uniform current density, but are concentrated at the contact with contact
element 30, producing an area 27 of high temperature, which with proper
current selection leads to a phase change in that area. The illustrated
design leads to reduced current consumption by the memory element.

[0031]Memory element 10 is subject to a number of variations as seen in
FIGS. 2a -2f. These variations do not affect the overall performance,
function or design of memory element 10, but they do produce changes in
specific performance parameters or manufacturability, as will be
understood by those of skill in the art. Discussions of the following
variations each take the memory element 10 of FIG. 1 as a starting point.

[0032]The variation shown in FIG. 2a, removes the crossbar portion of the
phase change element, leaving an hourglass-shaped element that extends to
the upper surface of the upper dielectric layer. The advantage of this
design is improved fabrication, as the layer of GST material above the
upper dielectric layer is dispensed with. Better thermal isolation,

[0033]The variation of FIG. 2b adds a bottom flange 17 to the phase change
element, producing an element resembling an I-beam in outline. This
design provides improved thermal isolation between the central portion of
the phase change element and the bottom electrode.

[0034]In FIG. 2c the neck 20 is not formed, leaving the upright portion of
the phase change element as a straight member. This change clearly
simplifies the manufacturing process.

[0035]The variation of FIG. 2d moves in the opposite direction. Here the
neck 20 is held straight, but a void 21 is formed inside the upright
member. It can clearly be seen that this design constricts the current
flow path even more than does the design of FIG. 1, producing more
concentrated heating. Also, the void 21 also increases the degree of
thermal isolation, serving the concentrate the heat even more. It is
preferred to deposit this material by a sputtering process, and the
internal void 21 is formed by controlling sputtering conditions, as is
known in the art.

[0036]The variation of FIG. 2e includes a neck 20 formed the opposite of
the neck shown in FIG. 1. Rather than having a reduced cross-sectional
area, the neck here has an increased cross-section, protruding into the
vacuum isolation cell, as result of the deposition process.

[0037]Similarly, FIG. 2f depicts a design in which the neck 20 protrudes
into the vacuum isolation cell, but the protrusion is notched.

[0038]An embodiment of a process for fabricating the memory element 10
depicted in FIG. 1 is illustrated in FIGS. 3a -3f. The process begins
with a substrate 12, as shown in FIG. 3a. A lower electrode 14 is formed
in the substrate, using known techniques. The materials for both the
substrate and the electrode are discussed above.

[0039]Next, as seen in FIG. 3b, a substrate upper ledge 15, plus layers of
an intermediate dielectric 18 and an upper dielectric 24 are formed
across the width of the substrate. Each of these layers has a thickness
of from about 10 nm to about 50 nm, preferably 30 nm.

[0040]Removal of material to prepare for the phase change element is seen
in FIG. 3c. It is preferred to follow the conventional lithographic
process of applying a photoresistive film; imprinting a pattern, as
through a mask or reticle; exposing the pattern to visible light or other
radiation; stripping the undesired portions of resist material to form an
etch mask; and etching the material layers. It is preferred to employ a
dry, anisotropic etch, which may be controlled with an optical device
that senses arrival at the lower electrode layer.

[0041]The vacuum isolation cell is formed in the step shown in FIG. 3d,
where a wet etch, preferably phosphorous acid, is employed to selectively
etch the SiN of the intermediate dielectric layer 18 a controlled
distance back from the surface formed by the ends of the substrate upper
ledge 15 and the upper dielectric layer 24.

[0042]Phase change element 16 is added in the following step, illustrated
in FIG. 3e. As shown, a conventional deposition step, preferably
employing a sputtering or plasma enhanced sputtering process, is employed
to form the phase change element 16. The width of the upright portion of
the phase change element (which is also the width of the etched area)
should be from about 10 nm to about 100 nm, preferably 50 nm.

[0043]Finally, the upper electrode 26 is deposited in the final step,
shown in FIG. 3f. That element and the phase change element are patterned
to the desired lateral dimension, using conventional lithographic
techniques as discussed above.

[0044]While the present invention is disclosed by reference to the
preferred embodiments and examples detailed above, it is to be understood
that these examples are intended in an illustrative rather than in a
limiting sense. It is contemplated that modifications and combinations
will readily occur to those skilled in the art, which modifications and
combinations will be within the spirit of the invention and the scope of
the following claims. What is claimed is: