Abstract:

A non-volatile memory is described having memory cells with a gate
dielectric. The gate dielectric is a multilayer charge trapping
dielectric between a control gate and a channel region of a transistor to
trap positively charged holes. The multilayer charge trapping dielectric
comprises at least one layer of high-K.

Claims:

1. A non-volatile memory comprising:source and drain regions located in a
transistor body region, the source and drain regions are laterally spaced
apart to form a channel region therebetween;a control gate isolated from
and located vertically above the channel region;a multilayer charge
trapping dielectric between the control gate and the channel region to
trap positively charged holes, wherein the multilayer charge trapping
dielectric comprises at least one layer of high-K dielectric having a
dielectric constant (K) greater than seven;a discrete bi-polar junction
having an n-type region substantially underlying the channel region and
having a p-type region substantially underlying the n-type region;
andprogram circuitry to program the multilayer charge trapping dielectric
by uniformly injecting holes onto the at least one layer of high-K
dielectric.

2. The non-volatile memory of claim 1, wherein the multilayer charge
trapping dielectric comprises a layer of high-K dielectric located
between first and second layers of oxide.

8. The non-volatile memory of claim 7, wherein the multilayer charge
trapping dielectric comprises a layer of Ta2O5 located between
first and second layers of HfO.sub.2.

9. The non-volatile memory of claim 7, wherein the multilayer charge
trapping dielectric comprises a layer of HfO2 located between first
and second layers of La2O.sub.3.

10. The non-volatile memory of claim 7, wherein the multilayer charge
trapping dielectric comprises a layer of ZrO2 located between first
and second layers of HfO.sub.2.

11. The non-volatile memory of claim 7, wherein the multilayer charge
trapping dielectric comprises a layer of ZrO2 located between first
and second layers of Lanthanide Oxide.

12. The non-volatile memory of claim 7, wherein the multilayer charge
trapping dielectric comprises a layer of HfO2 located between first
and second layers of Lanthanide Oxide.

13. A memory device comprising:an array of positive charge hole trapping
transistor memory cells, each memory cell including:source and drain
regions located in a transistor body region, the source and drain regions
are laterally spaced apart to form a channel region therebetween,a
control gate isolated from and located vertically above the channel
region, a multilayer charge trapping dielectric between the control gate
and the channel region to trap positively charged holes, wherein the
multilayer charge trapping dielectric comprises at least one layer of
high-K dielectric having a dielectric constant (K) greater than seven;
anda discrete bi-polar junction having an n-type region substantially
underlying the channel region and having a p-type region substantially
underlying the n-type region and configured to uniformly inject holes
into the channel region; andwrite circuitry to write data to the memory
cells during a write operation.

14. The memory device of claim 13, wherein the multilayer charge trapping
dielectric comprises a layer of high-K dielectric located between first
and second layers of oxide.

15. The memory device of claim 13, wherein the multilayer charge trapping
dielectric comprises an oxide layer, a nitride layer, and a layer of
high-K dielectric.

17. The memory device of claim 13, wherein the at least one layer of
high-K dielectric comprises an oxide of one of Praseodymium (Pr),
Neodymium (Nd), Samarium (Sm) Gadolinium (Gd), and Dysprosium (Dy).

18. A method of programming a non-volatile memory transistor
comprising:injecting positively charged holes into a multilayer
dielectric located between a control gate and a channel region of the
transistor, the multilayer dielectric comprising at least one layer of
high-K dielectric having a dielectric constant (K) greater than seven and
selected from the group: ZrSnTiO, ZrON, ZrAlO, ZrTiO4, HfAlO3,
HfSiON, CrTiO3, and YSiO; andtrapping the positively charged holes
in the at least one layer of high-K dielectric, wherein the injecting
positively charged holes comprises uniformly injecting holes via a p-n
device having an n-type region substantially underlying the channel
region and having a p-type region substantially underlying the n-type
region.

19. A non-volatile memory comprising:a source and a laterally spaced-apart
drain region positioned in a substrate to form a channel region
therebetween;a control gate isolated from the channel region and
positioned on a first side of the channel region;a multilayer charge
trapping dielectric positioned between the control gate and the channel
region to trap positively charged holes, wherein the multilayer charge
trapping dielectric comprises at least one layer of high-K dielectric
having a dielectric constant (K) greater than seven; anda back gate
structure positioned on an opposing second side of the channel region
that is operable to program the multilayer charge trapping dielectric by
injecting holes onto the at least one layer of high-K dielectric.

20. The non-volatile memory of claim 19, wherein the back gate structure
comprises a semiconductor junction region that is configured to inject
the holes onto the at least one layer of the High-K dielectric when a
predetermined voltage is applied to the region.

21. The non-volatile memory of claim 19, wherein the semiconductor
junction region is configured to inject the holes onto the at least one
layer of the High-K dielectric when the semiconductor junction region and
the control gate are suitably biased.

22. The non-volatile memory of claim 19, wherein the multilayer charge
trapping dielectric comprises a layer of high-K dielectric located
between first and second layers of oxide, wherein the layer of high-K
dielectric includes one of HfO2, ZrO2, ZrSnTiO, ZrON, ZrAlO,
ZrTiO4, Al2O3, La2O3, LaAlO3, HfAlO3,
HfSiON, Y2O3, Gd2O3, Ta2O5, TiO2,
Pr2O3, CrTiO3, and YSiO.

23. The non-volatile memory of claim 19, wherein the multilayer charge
trapping dielectric comprises an oxide layer, a nitride layer, and a
layer of high-K dielectric, wherein the layer of high-K dielectric
includes one of Al2O3, HfO2, or ZrO.sub.2.

24. The non-volatile memory of claim 23, wherein the layer of high-K
dielectric is formed using an atomic layer deposition process.

26. The non-volatile memory of claim 25, wherein the multilayer charge
trapping dielectric comprises a layer of Ta2O5 located between
first and second layers of HfO.sub.2.

27. The non-volatile memory of claim 25, wherein the multilayer charge
trapping dielectric comprises a layer of HfO2 located between first
and second layers of La2O.sub.3.

28. The non-volatile memory of claim 25, wherein the multilayer charge
trapping dielectric comprises a layer of ZrO2 located between first
and second layers of HfO.sub.2.

29. The non-volatile memory of claim 25, wherein the multilayer charge
trapping dielectric comprises a layer of ZrO2 located between first
and second layers of Lanthanide Oxide.

30. The non-volatile memory of claim 25, wherein the multilayer charge
trapping dielectric comprises a layer of HfO2 located between first
and second layers of Lanthanide Oxide.

31. A memory device comprising:an array of cells, each memory cell
comprising,a source and a laterally spaced-apart drain region positioned
in a substrate to form a channel region therebetween;a control gate
isolated from the channel region and positioned on a first side of the
channel region;a multilayer charge trapping dielectric positioned between
the control gate and the channel region to trap positively charged holes,
wherein the multilayer charge trapping dielectric comprises at least one
layer of high-K dielectric having a dielectric constant (K) greater than
seven; anda back gate structure positioned on an opposing second side of
the channel region that is operable to program the multilayer charge
trapping dielectric by injecting holes onto the at least one layer of
high-K dielectric.

32. The memory device of claim 31, wherein the back gate structure
comprises a semiconductor junction region that is configured to inject
the holes onto the at least one layer of the High-K dielectric when a
predetermined voltage is applied to the region.

33. The memory device of claim 31, wherein the semiconductor junction
region is configured to inject the holes onto the at least one layer of
the High-K dielectric when the semiconductor junction region and the
control gate are suitably biased.

34. The memory device of claim 31, wherein the multilayer charge trapping
dielectric comprises a layer of high-K dielectric located between first
and second layers of oxide.

35. The memory device of claim 31, wherein the multilayer charge trapping
dielectric comprises an oxide layer, a nitride layer, and a layer of
high-K dielectric.

[0003]Flash memory is non-volatile, which means that it stores information
on a semiconductor in a way that does not need power to maintain the
information in the chip. Flash memory is based on the Floating-Gate
Avalanche-Injection Metal Oxide Semiconductor (FAMOS transistor), which
is essentially a Complimentary Metal Oxide Semiconductor (CMOS) Field
Effect Transistor (FET) with an additional conductor suspended between
the gate and source/drain terminals. Current flash memory devices are
made in two forms: NOR flash and NAND flash. The names refer to the type
of logic used in the storage cell array. Further, flash memory stores
information in an array of transistors, called "cells," each of which
traditionally stores one or more bits of information.

[0004]A flash cell is similar to a standard Metal Oxide Semi-conductor
Field Effect Transistor (MOSFET) transistor, except that it has two gates
instead of just one. One gate is the control gate (CG) like in other MOS
transistors, but the second is a floating gate (FG) that is insulated all
around by an oxide layer. The FG is between the CG and the substrate.
Because the FG is isolated by its insulating oxide layer, any electrons
placed on it get trapped there and thus store the information.

[0005]When electrons are trapped on the FG, they modify (partially cancel
out) an electric field coming from the CG, which modifies the threshold
voltage (Vt) of the cell. Thus, when the cell is "read" by placing a
specific voltage on the CG, electrical current will either flow or not
flow between the cell's source and drain connections, depending on the Vt
of the cell. This presence or absence of current is sensed and translated
into 1's and 0's, reproducing the stored data.

[0006]A different non-volatile memory, Nitrided Read Only Memory (NROM),
utilizes inherent physical features of an oxide-nitride-oxide (ONO) gate
dielectric and known mechanisms of program and erase operations to create
two separate physical bits per cell. The NROM cell is based on localized
negative charge trapping. The cell is an n-channel MOSFET device where
the gate dielectric is replaced by an ONO stack. Two spatially separated
narrow charge distributions are stored in the nitride layer above
junction edges. The NROM cell is programmed by channel hot electron
injection.

[0007]The NROM memory devices have attracted much attention due to their
advantages over the traditional floating-gate flash device, including
lower programming voltage, better scalability, and improved cycling
endurance. An advantage of the NROM cell is the negligible vertical
retention loss due to inhibition of direct tunneling. Further, in
floating gate technology the electron charge is stored in a conductive
layer, and any minor oxide defect or oxide trapped charge under the gate
might cause leakage and loss of all the stored charge. NROM technology,
however, uses a nitride insulator as a retaining material, hence only a
large defect in the oxide (comparable to the cell size) could degrade
retention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 is a block diagram of a memory according to one embodiment of
the invention.

[0009]FIG. 2 is a cross-section of a prior art transistor.

[0010]FIG. 3 is a cross-section of a transistor of one embodiment with a
buried P--N junction.

[0011]FIG. 4 is a cross-section of a transistor of one embodiment with a
multi-layered dielectric.

DESCRIPTION

[0012]In the following detailed description of the invention, reference is
made to the accompanying drawings which form a part hereof, and in which
is shown, by way of illustration, different embodiments in which the
invention may be practiced. These embodiments are described in sufficient
detail to enable those skilled in the art to practice the invention.
Other embodiments may be utilized and structural, logical, and electrical
changes may be made without departing from the scope of the present
invention.

[0013]The terms wafer and substrate used in the following description
include any structure having an exposed surface onto which a layer is
deposited according to the present invention, for example to form the
integrated circuit (IC) structure. The term substrate is understood to
include semiconductor wafers. The term substrate is also used to refer to
semiconductor structures during processing, and may include other layers
that have been fabricated thereupon. Both wafer and substrate include
doped and undoped semiconductors, epitaxial semiconductor layers
supported by a base semiconductor or insulator, as well as other
semiconductor structures. The term conductor is understood to include
semiconductors, and the term insulator is defined to include any material
that is less electrically conductive than the materials referred to as
conductors.

[0014]As recognized by those skilled in the art, memory devices of the
type described herein are generally fabricated as an integrated circuit
containing a variety of semiconductor devices. The integrated circuit is
supported by a substrate. Integrated circuits are typically repeated
multiple times on each substrate. The substrate is further processed to
separate the integrated circuits into dice as is well known in the art.

[0015]Relative terms such as above, below, lateral and adjacent are not
limited to a specific coordinate system. These terms are used to describe
relative positions between components and are not intended to be
limitations. As such, additional components can be positioned between
components that are above, below, lateral and adjacent to each other.
Further, the figures are provided to help facilitate an understanding of
the detailed description, are not intended to be accurate in scale, and
have been simplified.

[0016]The following detailed description is, therefore, not to be taken in
a limiting sense, and the scope of the present invention is defined only
by the appended claims, along with the full scope of equivalents to which
such claims are entitled.

[0017]FIG. 1 is a simplified block diagram of an integrated circuit memory
device 100 in accordance with an embodiment of the invention. The memory
device 100 includes an array of non-volatile memory cells 102, address
circuitry 104, control circuitry 110, and Input/Output (I/O) circuitry
114.

[0018]The memory device 100 can be coupled to a processor 120 or other
memory controller for accessing the memory array 102. The memory device
100 coupled to a processor 120 forms part of an electronic system. Some
examples of electronic systems include personal computers, peripheral
devices, wireless devices, digital cameras, personal digital assistants
(PDA's) and audio recorders.

[0019]The memory device 100 receives control signals across control lines
122 from the processor 120 to control access to the memory array 102 via
control circuitry 110. Access to the memory array 102 is directed to one
or more target memory cells in response to address signals received
across address lines 124. Once the array is accessed in response to the
control signals and the address signals, data is written to or read from
the memory cells across data, DQ, lines 126.

[0020]It will be appreciated by those skilled in the art that additional
circuitry and control signals can be provided, and that the memory device
of FIG. 1 has been simplified to help focus on the invention. It will be
understood that the above description of a memory device is intended to
provide a general understanding of the memory and is not a complete
description of all the elements and features of a typical memory device.

[0021]In embodiments of the invention, a p-channel MOSFET with a high
dielectric constant, high-K, gate insulator with hole trapping in the
gate insulator is provided as a memory device. Programming can be
achieved by hot hole injection from a transistor channel, light generated
holes accelerated in an electric field, holes injected into the device by
a buried p-n junction, or holes generated at the gate insulator-substrate
interface by highly energetic electrons tunneling off of the gate. Data
can be read by operating the transistor in the forward direction, or if
holes are injected only near the drain by operating the transistor in the
reverse direction.

[0022]Different methods of programming holes in the high-K dielectric can
be employed in the present invention. Many of the available programming
techniques are well known in the art and briefly explained below. For
purposes of simplicity, control circuitry 110 is referred to herein as
encompassing program circuitry to program a multilayer charge trapping
dielectric by injecting holes onto the at least one layer of high-K
dielectric.

[0023]Flash memories based on p-channel MOSFETs using hole trapping in
gate oxides as a memory technique and hot hole injection are known.
Further, hole trapping has been described for use in fuses and anti-fuse
devices. In such memories and structures, holes from a silicon substrate
are generated by large negative gate voltages, hot hole injection from
the channel, or by light.

[0024]FIG. 2 depicts a simplified cross-section of a prior art metal oxide
semiconductor field effect transistor (MOSFET) in a substrate 200. The
MOSFET includes a source region 202, a drain region 204, and a channel
region 206 in the substrate 200 between the source region 202 and the
drain region 204. A gate 208 is separated from the channel region 206 by
a gate oxide 210. A source line 212 is coupled to the source region 202.

[0025]In a memory device, a bitline conductor 214 is coupled to the drain
region 204. A wordline conductor 216 is coupled to the gate 208. In
conventional operation, a drain to source voltage potential (Vds) is set
up between the drain region 204 and the source region 202. A negative
voltage potential is then applied to the gate 208 via the wordline 216.
Once the negative voltage potential applied to the gate exceeds the
characteristic voltage threshold (Vt) of the MOSFET, the channel 206
forms in the substrate 200 between the drain region 204 and the source
region 202. Formation of the channel 206 permits conduction between the
drain region 204 and the source region 202, and a current (Ids) can be
detected at the drain region 204.

[0026]During operation of the conventional MOSFET of FIG. 2, some change
in the device drain current can be programmed for MOSFETs operated in the
forward direction due to holes being trapped in the gate oxide 210 near
the drain region 204. This can be accomplished by hot hole injection when
the transistor is operated with a drain voltage, Vds, near the gate
voltage, Vgs.

[0027]Since in this case the holes are trapped near the drain region 204,
however, they are not very effective in changing the characteristics of
the MOSFET. They are only effective if the transistor is operated in the
reverse direction during the read cycle as in reading an NROM device. As
such, hot hole injection of the prior art can be used with embodiments of
the present invention.

[0028]Alternatively, a sufficiently large negative gate bias voltage can
be applied to cause tunnel electrons from the gate to gain enough energy
to exceed the band gap energy of the gate insulator. As a result,
energetic hole-electron pairs are generated in the silicon substrate and
the holes have enough energy to overcome the barrier at the insulator and
substrate interface.

[0029]The holes are then injected from the substrate into the gate
dielectric, where they remain trapped. A large shift in the threshold
voltage of the p-channel MOSFET results. The device can subsequently be
reset by applying a positive gate bias voltage. It is known in the art
that the positive charge generated in gate oxides by hot hole injection
can be erased by avalanche electron injection.

[0030]Another prior art method to inject holes is to generate electron
hole pairs by providing incident light. The holes are accelerated towards
the gate insulator or oxide and trapped in the gate insulator. Trapped
positive charge results in a change in the device drain current and can
be used as a memory effect or memory device. This is accomplished by hot
hole injection when the transistor is operated with a drain voltage near
Vgs. Erasure is achieved by hot electron injection by operation with a
drain voltage, Vds, much larger than the gate voltage, Vgs.

[0031]FIG. 3 depicts a semiconductor device having a bipolar (pnp)
transistor-like structure, according to one embodiment of the invention,
which allows uniform injection of holes. The device includes a source
region 302, a drain region 304, a back gate region 306, and a channel
region 308 in the substrate 300 between the source region 302 and the
drain region 304. A gate 310 is separated from the channel region 308 by
a multi layer gate dielectric 312. The gate dielectric contains at least
one layer of a high-K dielectric, as explained below. A source line 314
is coupled to the source region 302. A bitline conductor 316 is coupled
to the drain region 304. A wordline conductor 318 is coupled to the gate
310. A terminal 320 is coupled to the back gate region 306. The back gate
306 forms a p-n junction with substrate 300.

[0032]When a positive voltage Veb is applied to the back gate region 306
via the terminal 320 and a negative voltage is applied to the gate 310
via the wordline 318, holes are injected from the p-n junction in the
back gate region into the gate insulator 312. This effect is depicted in
FIG. 3 and results in a change in the device threshold voltage.

[0033]Regardless of the programming method employed, embodiments of the
present invention use a high-K (high dielectric constant) dielectric in
the gate dielectric to trap positive charged holes. For the present
embodiments, high-K dielectrics are defined as those with a dielectric
constant greater than that of silicon nitride (i.e., >k=7).

[0034]FIG. 4 depicts a simplified cross-section of a metal oxide
semiconductor field effect transistor (MOSFET) memory cell of the present
invention. The memory cell is formed in a substrate 400. The cell
includes a source region 402, a drain region 404, and a channel region
406 in the substrate 400 between the source region 402 and the drain
region 404. A gate 408 is separated from the channel region 406 by a
multi layer gate dielectric 410. The dielectric layers include one or
more layers of high-K dielectric material.

[0035]A source line 412 is coupled to the source region 402. In a memory
device, a bitline conductor 414 is coupled to the drain region 404. A
wordline conductor 416 is coupled to the gate 408.

[0036]High-K dielectrics have smaller bandgap energies, and less voltage
is required to inject holes into the gate insulator 410. These high-K
dielectrics can be composite layers, or nanolaminates, formed by
oxidation, chemical vapor deposition (CVD), evaporation, or atomic layer
deposition (ALD), depending on the material used. The band gap energy of
high-K dielectrics becomes smaller as the dielectric constant increases.

[0037]Example high-K dielectrics of the present invention gate dielectric
include a high-K dielectric between two layers of an oxide. The high-K
dielectric layer in the composite gate insulator can be selected from
Table 1 and the associated fabrication techniques:

[0038]Further examples of the present invention gate dielectric include an
oxide-nitride--high-K dielectric composite layered gate insulator. The
high-K dielectric layer in the composite gate insulator can be selected
from ALD formed Al2O3, HfO2 or ZrO2.

[0039]Further examples of the present invention gate dielectric include
three stacked layers of high-K dielectrics. The high-K dielectric layers
in the composite gate insulator can be selected from dielectrics of Table
2 formed by ALD.