Cortex-A53 Processor

It makes use of a highly efficient 8-stage in-order pipeline balanced with advanced fetch and data access techniques for performance. It fits in a power and area footprint suitable for entry-level smartphones, and is at the same time capable of delivering high-aggregate performance in scalable enterprise systems via high core density.

The Cortex-A53 delivers significantly higher performance than the highly successful Cortex-A7, and is capable of deployment as a standalone applications processor or paired with either the Cortex-A72 or Cortex-A57 processor in a big.LITTLE™ configuration for optimum performance, scalability and energy efficiency. It is supported by a range of optimized IP targeted at designing the most efficient complete ARM-based SoCs. ARM Mali™ processors support all graphics, video and display demands, ARM POP™ IP solutions deliver an accelerated time-to-market, and optimized System IP provides the interconnect and peripheral components.

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Overview

The Cortex-A53 delivers 64-bit capability and significantly increases performance over Cortex-A7, in a footprint suited for cost-sensitive applications. It is smaller and lower power than the Cortex-A9 processor and delivers more performance on key benchmarks. This means it can enable devices with the compute power of today’s high-end smartphone in the lowest power and area footprint.

As well as running 64-bit applications, the Cortex-A53 seamlessly and efficiently runs legacy ARM 32-bit applications. It is highly scalable, from a single multi-core CPU cluster, to a dual-cluster big.LITTLE CPU subsystem in combination with the Cortex-A72 or Cortex-A57 processor, to a multi-cluster enterprise system connected through AMBA® 5 CHI Coherent Interconnect technology. Full ARMv8-A support in a small and highly configurable package means that the Cortex-A53 is highly suited to a broad range of mobile, consumer, general purpose, and enterprise applications.

It features coherent interoperability with ARM Mali family graphics processing units (GPUs) for GPU compute applications, and connects seamlessly to AMBA interconnect for 16-core and 32-core configurations, delivering programmability with the most aggregate performance per Watt to high-performance enterprise applications by maximizing core count in a thermally constrained rack.

Applications

Built as a low-power processor with 64-bit capabilities, the Cortex-A53 processor is applicable in a range of devices requiring high performance in power-constrained environments.

Key target markets include:

High-end smartphones (with big.LITTLE technology)

Smartphones

Wireless networking infrastructure

Low-power servers

Smart TVs

Set-top boxes

The Cortex-A53 processor delivers significantly more performance than its predecessors at a higher level of power efficiency. This takes the performance of the core above that of the Cortex-A7 processor, which defines many popular mainstream and entry-level mobile platforms. The performance graph below shows the performance improvements of the Cortex-A53 processor against the Cortex-A7 processor.

The ARMv8-A architecture brings a number of new features. These include 64-bit data processing and extended virtual addressing and a 64-bit general purpose registers. Further features of the architecture are shown in the Specifications tab. The Cortex-A53 processor is ARM’s first ARMv8-A processor aimed at providing power-efficient 64-bit processing. It features an in-order, 8-stage, dual-issue pipeline, and improved integer, NEON™, Floating-Point Unit (FPU) and memory performance.

The Cortex-A53 can be implemented in two execution states; AArch32 and AArch64. The AArch64 state gives the Cortex-A53 its ability to execute 64-bit applications, while the AArch32 state allows the processor to execute existing ARMv7-A applications.

ARM big.LITTLE processing is a power-optimization technology where high-performance ARM CPU cores are combined with the most efficient ARM CPU cores to deliver peak-performance capacity, higher sustained performance, and increased parallel processing performance, at significantly lower average power. The Cortex-A57 acts as a big processor and is paired in a configuration with the Cortex-A53 processor.

Yes

Yes

Floating-Point Unit (FPU)

Hardware support for Floating-Point operations in half-, single- and double-precision Floating-Point arithmetic. Now with IEE754-2008 enhancements.

The processor also utilizes the widely established ARM MPCore multicore technology, enabling performance scalability and control over power consumption to exceed the performance of today's comparable high-performance devices while remaining within tight mobile power constraints. Multicore processing provides the ability for any of the four component processors, within a cluster, to shut down when not in use, for instance when the device is in standby mode, to save power. When higher performance is required, every processor is in use to meet the demand while still sharing the workload to keep power consumption as low as possible.

Snoop Control Unit (SCU)

The SCU is responsible for managing the interconnect, arbitration, communication, cache to cache and system memory transfers, cache coherence and other capabilities for the processor. The Cortex-A53 MPCore processor also exposes these capabilities to other system accelerators and non-cached DMA driven peripherals to increase performance and reduce system wide power consumption. This system coherence also reduces software complexity involved in maintaining software coherence within each OS driver.

Accelerator Coherence Port

This AMBA 4 AXI compatible slave interface on the SCU provides an interconnect point for masters that are better interfaced directly with the Cortex-A53 processor. This interface supports all standard read and write transactions without additional coherence requirements. However, any read transactions to a coherent region of memory will interact with the SCU to test whether the information is already stored in the L1 caches. The SCU will enforce write coherence before the write is forwarded to the memory system and may allocate into the L2 cache, removing the power and performance impact of writing directly to off-chip memory

Generic Interrupt Controller (GIC)

Implementing the standardized and architected interrupt controller, the GIC provides a rich and flexible approach to inter-processor communication and the routing and prioritization of system interrupts. Under software control, each interrupt can be distributed across CPU, hardware prioritized, and routed between the operating system and TrustZone software management layer. This routing flexibility and the support for virtualization of interrupts into the operating system, provides one of the key features required to enhance the capabilities of a solution utilizing a hypervisor.

Overview

The Cortex-A53 processor can be incorporated into SoCs with a broad range of ARM technology including System IP, Physical IP, and development tools. A broad range of SoC and software design solutions, tools and services from the ARM Connected Community complements this technology. That provides ARM partners with a smooth path through the development, verification and production of fully-functional, compelling devices while significantly reducing time-to-market.

The Mali family of products combine to provide the complete graphics stack for all embedded graphics needs, enabling device manufacturers and content developers to deliver the highest quality, cutting-edge graphics solutions across the broadest range of consumer devices.

The Cortex-A53 can be used with all Mali high-end graphics processors, and the Mali-DP500 display processor and Mali-V500 video processor are also compatible.

System IP

The ARM interconnect and memory controller IP addresses the critical challenge of efficiently moving and storing data between up to 16 Cortex-A53 MPCore processors, high-performance media processors and dynamic memories to optimize the system performance and power consumption of the SoC. The CoreLink system IP enables SoC designers to maximize the utilization of system memory bandwidth and reduces static and dynamic latencies. While the ARM CoreSight technology provides complete on-chip debug and correlated, real-time trace visibility for all cores of the Cortex-A53 MPCore processor, reducing risk and speeding up development of high-quality multiprocessing software. The new AMBA 4 Cache Coherent Network (CCN) provides optimum system bandwidth and latency. The CCN provides AMBA 4 AXI Coherency Extensions (ACE) compliant ports for full coherency between multiple Cortex-A53 MPCore processors, better utilizing caches and simplifying software development. This feature is essential for high-bandwidth applications including gaming, servers and networking that require clusters of coherent single and multicore processors. ARM CoreLink CCN interconnect and memory controller IP boosts system performance and power efficiency.

Physical IP

ARM Physical IP Platforms deliver process optimized IP, for best-in-class implementations of the Cortex-A53 processor at 40nm and below. A set of high performance POP™ IP containing advanced ARM Physical IP for 28nm and 16ff technologies supports the Cortex-A53, enableing rapid development of leadership physical implementations. POP IP supports the ARM strategy of offering specifically targeted Physical IP to enable partners to achieve tuned implementations of ARM cores. ARM is uniquely positioned to design the optimization packagess in parallel with the Cortex-A53 processor design, enabling the processor and physical IP combination to deliver highclass performance in a mobile power envelope while facilitating rapid time-to-market.

Tools Support

ARM DS-5 Development Studio fully supports all ARM processors as well as a wide range of third party tools, operating systems and EDA flows. DS-5 is unique in its ability to provide solutions that take full advantage of the complete ARM technology portfolio, offering a comprehensive range of software tools to create, debug and optimize systems based on the Cortex-A53 processor.

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