IEDM Set to Stage FinFET vs. FDSOI

The advance program for the 2013 International Electron Devices Meeting (IEDM) has been published. Session 9 on advanced CMOS platforms is likely to be one of the highlights.

In that session, a speaker from Taiwan Semiconductor Manufacturing Co. Ltd. will provide details on the company's 16nm FinFET CMOS process. This will be immediately followed by a paper on the FDSOI process for the 14nm node. The authors of the FinFET paper all come from TSMC, but the authors of the FDSOI paper come from STMicroelectronics, Soitec, Leti, IBM, Globalfoundries, and Renesas.

IEDM, one of the landmark events of the electronic engineering calendar, bridges academic and commercial research in electron-based devices. This year's meeting takes place Dec. 7-9 at the Washington Hilton Hotel.

The foundry TSMC will soon ramp up the production of 20nm circuits and has released 16nm design information. (See: TSMC Releases 16nm FinFET Design Flows.) A TSMC author will present on the 16nm FinFET process that is optimized for mobile and computing applications. According to the abstract of the paper, the process provides twice the logic density and a performance improvement of more than 35 percent (or a 55 percent reduction in power consumpiton) over TSMC's 28nm HKMG planar bulk CMOS process. The following paper on FDSOI -- far from the only FDSOI paper in the conference -- will give details on devices that have a gate length of 20nm but are intended for nodes labeled 14nm.

Intel, which is just beginning to manufacture 14nm FinFET ICs, will be present in the session but with a paper detailing how it can add embedded DRAM to its older 22nm FinFET process (or tri-gate process, as the company calls it). The paper should explain how Intel has achieved more than 100 microseconds of retention time at 95 degrees C for a gigabit array.

Not to be left out, engineers at Fujitsu Semiconductor Ltd. will present Paper 9.6, which addresses the addition of embedded flash nonvolatile memory to its 55nm CMOS logic process that is enhanced using the Deeply Depleted Channel technology licensed from SuVolta Inc. (See: SuVolta Power-Saving Chip Process Enters Production.)

Intel's more advanced process technology at 14nm and below is not scheduled to be discussed in any paper at the conference, but engineers from Intel will present in Session 4 on modeling tunneling field effect transistors (TFETs) in III-V materials for use in a subthreshold voltage manner at nodes of 9nm and below.

Advanced CMOS platforms is just one strand of many that will be represented at IEDM, which will include 215 presentations in 33 sessions. There will be numerous memory papers covering NAND, ReRAM, CBRAM, ferroelectric, and phase-change approaches. The continued expansion of the significance of electronics means that IEDM has an increased emphasis on analog circuits, MEMS sensors, and displays. Circuits and processes for biosensors and bioMEMS will be covered, along with energy harvesting, power devices, magnetics, and spintronics.

thank you Adele...no, I didn't realize that finFET was built on SOI substrate first!...since doing my research on SiGe devices while with U of Toronto in early 90-ties I have not been following basic transistor technology that closely...looking to hear from you on how finFET vs FDSOI debate continues at IEDM!...Kris

Kris, as of course as you know, FinFETs were originally developed on SOI - because it was easier! And there's that great animation on the SOI Consortium website that shows why that's still the case. But is easier necessarily in the interests of the foundries? If bulk FinFETs are more complicated but they get higher margins on them, it seems logical that's what they'll push...? Whereas for IDMs, they reap the savings (cheaper and easier) themselves. Not sure how good this trend would be for the industry, tho. On the other hand, we're starting to see some complaints from designers re: pain points in bulk FinFETS. Either way, looking forward to this IEDM for sure!

re: self-heating -- the paper summary indicates that they're looking at 6nm (!!) FD-SOI, and finding self-heating "comparable" to bulk FinFETs. So maybe not going away, but certainly not a show stopper!

note intel 14 Finfet now delayed. delay is more like a year for the volumn Broadwell release not the 3 months CEO stated. Broadwell will not be in volumn in market until end of 2014 and there is even talk Broadwell will be cancelled due to it being so late or a limited volumn release. my contact a copy manufacturing engineer says they are still not even involved in the manufacturing and he should of been involved 5 quarters ago.

My primary purpose was not to lower or higher number of FinFET or FDSOI papers in IEDM. FinFET is at high volume manufacturing now over 2 years at 22nm by Intel while FDSOI is not manufacturable at any technology node yet. Therefore, when FDSOI test chips become available, I propose the minimum requirements for measurement of the transistor electrical transfer characteristcs for both FinFET and FDSOI for fair comprison. The minimum requirements are posted in detail. SKim

michigan, so are you saying that despite much time there has not been enough progress in FinFET and this has led to lower number of papers in IEDM? But no other company apart from TSMC is presenting paper which means more companies are developing FDSOI. Don't u think.

I think your correct. FinFET sounded good but all the 3D process variation and high gate capacitance means many design blocks on the SOC have worse PPA. I think this is one of the reasons Apples 28nm A7 is much better than Intel's FinFET Bay Trail