EP 0980145 A4 2000-09-20 - OUTPUT BUFFER CIRCUIT

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JP 9701506 W 19970501

Abstract (en)

[origin: US6278294B1] To prevent a through current from flowing through a pair of MOS transistors of a final stage of a push-pull buffer circuit, a reset circuit is provided which receives signals individually from two inverter gate groups of a control system and an output system disposed at the stage preceding the push-pull buffer circuit, delays the input signals, and makes a logical decision on them. Even when an input/output circuit formed by two power supply systems becomes unstable at the time of power ON-OFF operation and the signal output from a signal level converter circuit yields logic that causes a through current flow into the final stage, the reset circuit forcedly cancels this logic by feedback.