General Description

SSL1-AXI has a “lookaside” interface to the rest of system through two AXI interfaces:

AXI3/AXI4 slave for control

AXI3/AXI4 master for data transfer

The data stream through the control interface contains processing commands. Each command consists a pointer to the descriptor in the system memory. Descriptor contains source, destination, encryption context, processing length, and status.

The encryption context (keys, encryption state, etc.) as well as the packets are stored in the system memory attached to the AXI bus and are read and written via the master interface.

The design is fully synchronous and is available in Verilog.

Key Features

Throughput of 6-8 bits per clock (600-800 Mbps at 100 MHz)

Supports both encryption and decryption

Optional public-key RSA and ECC engines

Done signal for interrupting the CPU

Test bench provided

Symbols

Applications

Embedded SSL/TLS applications

Synthesis Results

The size of the core depends on the core configuration (public key cryptography option is listed separately)