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AR# 33779

Description

This Release Note and Known Issues Answer Record is for the SPI-3 (POS-PHY L3) Link Layer v7.1 Core, released in ISE 11.4 as well as the SPI-3 (POS-PHY L3) Link Layer v7.1 Rev1 Core, released in 11.5, and contains the following information:

Solution

New Features in v7.1

ISE 11.4 software support

Device support for Spartan-6 FPGA -4 speed grade

New Features in v7.1Rev1

ISE 11.5 software support

Bug Fixes in v7.1

Map DRC error: "ERROR:LIT:566 - MMCM_ADV symbol "tfmmcm" has been detected to have aconfiguration that requires the COMPENSATION setting to be ZHOLD instead of'INTERNAL'. The map application can automatically set the COMPENSATIONattribute provided that the original COMPENSATION attribute is left with itsdefault value by the designer."

CR 534442 Description: Removed the COMPENSATION attribute from the MMCM in the example design to leave it with the default ZHOLD value.

Bug Fixes in v7.1Rev1

(Xilinx Answer 34157) Virtex-6 FPGA core should not be used in production due to potential block RAM memory collisions

Cores configured with independent clocks and direct mode transfer flow-control might encounter hold time issues in hardware on the input DTPA bus unless one of the following conditions are met:

Generate TX_CLK using a DCM/MMCM and select an appropriate phase shift for the system to meet timing

Ensure the DTPA input data is already center aligned on the clock

Transmit the data on the rising edge and then clock it into the FPGA on the falling edge

The Tx and Rx cores are provided with default timing constraints in the UCF file generated with the core. Depending on the core configuration, target architecture, and speed grade, the core might run significantly faster. The user can modify the constraints to meet their performance requirements. As long as all timing constraints are met, the SPI-3 Link Core will operate at the user specified rate. Note that the best way to verify timing closure is with user logic, rather than the example design. Implementing only the example design might artificially limit the performance of the SPI-3 Link Core (e.g., if the User Interface is routed to I/O pins).

A DCM with a PHASE_SHIFT on its clock is required to meet the OIF specification's 2 ns input timing requirement. This solution is necessary only if the system's timing budget cannot permit the Link Core to exceed the 2 ns input requirement.

Known Issues in v7.1

(Xilinx Answer 34157) Virtex-6 core should not be used in production due to potential block RAM memory collision