This paper deals with the testable design of conservative logic based sequential circuits by using two test vectors. The conservative logic based sequential circuits are built from the reversible gates. This Reversible or information lossless circuits have extensive applications in quantum computing, optical computing, as well as ultra-low power VLSI circuits.The optimized designs of reversible D Latch,Reversible negative enable D latch,Master slave Flip-Flop,Double edge triggered Flip-Flops and its application circuits like reversible universal shift registers, four bit binary counter are proposed.This proposed design can identify any stuck-at-fault in the circuits and this proposed circuit is efficient than the conventional circuit designed using classical gate in terms of number of gate count,delay in the circuit,garbage output, power dissipation and testability.This proposed design can identify any stuck-at-fault in the circuits.