Please note that a new bus interface is not the same as rewriting every single fucking core. I'm dead tired of people writing new SPI controllers and UARTs. We have like 500 of those damn things with slightly different address maps and where at least 495 of them lack a proper testbench, documentation and drivers

The main problem with using AXI (trademark aside) is the bus master. At very least Mor1kx should support it and it is not trivial to add it (afair it currently assumes a bus with synchronous transactions). How is it done in pulpino?