Asynchronous design startup closes first round of funding

February 06, 2008 //

French startup Tiempo, specializing in the design of asynchronous ICs, has raised 1.1 million($1.6 million) in an initial round of financing with venture capital firms Emertec Gestion and Schneider Electric Ventures.

PARIS  French startup Tiempo, specializing in the design of asynchronous ICs, has raised 1.1 million($1.6 million) in an initial round of financing with venture capital firms Emertec Gestion and Schneider Electric Ventures.

Tiempo said the funds would be used to strengthen the development plan of the company's IP and EDA products but also to accelerate their commercialization worldwide.

Tiempo claims its solution allows semiconductor companies to design complex chips with ultra low power consumption and ultra low electromagnetic emission. It also contributes to reduce time-to-market by suppressing major design efforts on clock distribution and timing closure issues, and to increase productivity by improving the resistance of their circuits to the physical variations of the manufacturing technologies, the startup specified.

Tiempo noted that its portfolio of IPs includes asynchronous cores of microcontrollers, microprocessors, crypto-processors and miscellaneous communication and sensor interfaces.

Tiempo was founded in July 2007 by Serge Maginot, former R&D director at Synopsys, Inc., and Marc Renaudin, former Professor at the National Polytechnical Institute of Grenoble (INPG) and former head of the CIS research group of the TIMA Laboratory (research labs from INPG, CNRS and Joseph Fourier University). The startup is located in Montbonnot Saint-Martin, near Grenoble (France),

"Tiempo technology is the result of more than 15 years of scientific researches * the latest 8 years within the TIMA Laboratory * on the design of asynchronous integrated circuits and the development of dedicated EDA tools," stated Renaudin, CTO of Tiempo. "The outcome of these researches is chip prototypes that demonstrate outstanding performances for a very competitive silicon area, as well as a synthesis tool that makes our innovating asynchronous design technology now usable at industrial level."

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