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Abstract

CMOS technology is very attractive because low power circuits can be designed with it. However, the currents generated in the parasitic bipolars can result in latch-up of the entire circuit (Fig. 1). In this configuration the collector current of the PNP is base current for the bipolar NPN, and vice versa. This phenomenon results in latch-up of the circuit. This article describes a circuit structure (Figs. 2A and 2B) that provides two additional diffusions 10 and 20 of the same conductivity as the source/drain of adjacent FETs and are connected to separate drain lines. In this configuration, the parasitic currents of the NPN bipolar are divided into drainage line current IC2 and regular current IC1 .

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United States

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English (United States)

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Scr-Free CMOS Structure

CMOS technology is very attractive because low power circuits can be
designed with it. However, the currents generated in the parasitic bipolars can
result in latch-up of the entire circuit (Fig. 1). In this configuration the collector
current of the PNP is base current for the bipolar NPN, and vice versa. This
phenomenon results in latch-up of the circuit. This article describes a circuit
structure (Figs. 2A and 2B) that provides two additional diffusions 10 and 20 of
the same conductivity as the source/drain of adjacent FETs and are connected to
separate drain lines. In this configuration, the parasitic currents of the NPN
bipolar are divided into drainage line current IC2 and regular current IC1 . The
magnitude of currents IC1 and IC2 depends upon the relative base doping of the
parasitic bipolars which can be controlled by properly doping the base regions.
The magnitude of the current IC1 is sufficiently reduced to prevent turn-on in the
PNP and avoid latch-up. The same phenomenon applies to the NPN devices.