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AR# 46132

MIG 7 Series DDR3/DDR2 - Trace Matching and Derating Guidelines

Description

The MIG 7 Series DDR3/DDR3 designs require specific trace matching guidelines be followed to ensure the target data rate be achieved. These trace matching guidelines are specified in the Design Guidelines section of the 7 Series FPGAs Memory Interface Solutions User Guide.

NOTE: This answer record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

The trace matching requirements specified in the user guide are between:

Any DQ and its associated DQS/DQS#

Any Address and Control signal and the corresponding CK/CK#

CK/CK# and DQS/DQS#

The user guide specifies not only the matching requirements for maximum operation, but how much the guidelines can be loosened for slower interfaces. Refer to the user guide for specific trace matching numbers.