CDCL6010 is not bad for a chip, but it uses CML logic and is a QFN package. Seems like a lot of work...

&nbsp;&nbsp;.. the QFN package is not a problem but the CML somehow is. To solve this problem, I'm thinking to use AC coupled LVDS receivers (perhaps little logic gates from TI) wired into CDCL6010's outputs and adapted for CML logic (CML to LVDS). The reference will be one VC(X)O from Crystek.
Any thoughts or ideeas?
Cheers

Originally posted by excelon
&nbsp;&nbsp;.. the QFN package is not a problem but the CML somehow is. To solve this problem, I'm thinking to use AC coupled LVDS receivers (perhaps little logic gates from TI) wired into CDCL6010's outputs and adapted for CML logic (CML to LVDS). The reference will be one VC(X)O from Crystek.
Any thoughts or ideeas?
Cheers

You throw away the performance of a crystal based oscillator, when using a synthesizer

You throw away the performance of a crystal based oscillator, when using a synthesizer

&nbsp;&nbsp;Unfortunately, it's true... though I was thinking to use the VCXO to feed the PLL synthesizer thus have up to 10 synchronized CML outputs available for various digital circuits used in my future DAC - I hope the losses will be minimal in this way...
&nbsp;&nbsp;It's supposed to have the digital part completely isolated from the analogic one (that's why I want to use differential, AC coupled clock signals). These 10 clock signals should be synchronous with each other so the clock delays on my board should be minimal (the layout will try to reflect that). In addition, the fs and 64-fs clocks will be directly generated by the CDCL6010, so I wouldn't have to use (noisy) external circuits to do divide the master clock signal (CPLDs or FPGAs for example).
I have a good impresion about differential signals in therms of jitter when are properly implemented (good PS and layout, minimal noise). Unfortunately, my project requires to have one low-jitter clock oscillator with multiple outputs. In addition, I need multiple frecv. generated by one (VC)XO to used them with various input sample rates. So, this is what I come so far: XO and PLL synth.
thanx for repply!

Originally posted by excelon
&nbsp;&nbsp;Unfortunately, it's true... though I was thinking to use the VCXO to feed the PLL synthesizer thus have up to 10 synchronized CML outputs available for various digital circuits used in my future DAC.
&nbsp;&nbsp;It's supposed to have the digital part completely isolated from the analogic one (that's why I want to use differential, AC coupled clock signals). These 10 clock signals should be synchronous with each other so the clock delays on my board should be minimal. In addition, the fs and 64-fs clocks will be directly generated by the CDCL6010, so I woult not have to use (noisy) external circuits to do that (CPLDs or FPGAs for example).
I have a good impresion about differential signals in therms of jitter when are properly implemented (good PS, layout, minimal noise). Unfortunately, my project requires to have one low-jitter clock oscillator with multiple outputs. In addition, I need multiple frecv. generated by one (VC)XO to used them with various input sample rates. This is what I come so far: XO and PLL synth.
thanx for repply!

why not buy various VCXO's and select them where required ? And please use simple logic to divide clocks, otherwise you throw away the child with the bathwater

why not buy various VCXO's and select them where required ? And please use simple logic to divide clocks, otherwise you throw away the child with the bathwater

Yes, this is one possibility, though I still need 10 Synchronous clocks from the same VCXO with lowest jitter possible and I do need digital domain to be sepparated from the analog one (this is mandatory). I guess this sepparation can be made using AC-coupled differential signaling... so I'm back to the CDCL6010 "problem".
Though, I consider that CPLDs aren't so good for the clock division tasks... a lot of noise from surrounding, on-chip signals.
regards

Originally posted by excelon
Yes, this is one possibility, though I still need 10 Synchronous clocks from the same VCXO with lowest jitter possible and I do need digital domain to be sepparated from the analog one. I guess this can be solved using AC-coupled differential signaling... so I'm back to the CDCL6010 "problem".
I'm familiar with VHD but I'm wondering if CPLDs will be a good solution to do the clock's division tasks... when we spoke about jitter. BTW the CPLD chip that I'm using now runs up to 100 MHz.
regards

it will be only a board, perhaps 250 mm. long in the final form though the digital circuitry will take less space. There aren't any cables, only (paired-for differential, same length) PCB tracks. I'll try to keep them as short as possible without using vias. Also, I'll isolate these drivers from the rest of chips (having it's own PS) so CPLD isn't a solution anymore...
thanx