JESD204B FPGA Debug Tool From ADI & Xilinx

It seems to have been a long time coming, but the folks at Xilinx and Analog Devices Inc. (ADI) tell me that they are now seeing a rapid adoption of the JESD204B interface standard in a wide variety of application areas and markets, including medical, wireless, aerospace, and defense.

Just to make sure we're all tap-dancing to the same drum beat, the traditional way of getting the data from an analog-to-digital converter (ADC) into an FPGA was to use a parallel data bus. This isn't really an issue if your design uses only a single ADC. The problem is that many systems require large numbers of ADCs, which results in nightmare routing concerns at the board level and consumes a lot of pins on the FPGA. The solution is JESD204B, which is a high-speed serial interface that was designed from the ground up to facilitate data communication between ADCs and FPGAs; also between FPGAs and digital-to-analog converters (DACs).

Of course, we now have a problem in that many designers in this arena are not terribly confident about using these high-speed links, which operate in the 312.5 Mbps to 12.5 Gbps range. In order to address this issue, ADI has released a special FPGA-based reference with software and HDL code that reduces the design risk of high-speed systems incorporating JESD204B-compatible converters.

Working with Xilinx, ADI has also created the Analog Devices Linux JESD204B Eyescan Software, which works with Xilinx 7 series FPGAs and Zynq All Programmable SoCs. This tool, which is available for free with ADI converters, provides an on-chip, 2D statistical eyescan.

The transceivers in Xilinx 7 series FPGAs and Zynq All Programmable SoCs feature dedicated 2D eyescan hardware blocks that monitor the link and record the 2D eyescan data. In the case of a Zynq All Programmable SoC, the on-chip ARM Cortex-A9 dual processor subsystem can be used to process this data and present it on a display (using the HDMI interface, for example), all without requiring a host computer. Similar capabilities can be achieved in 7 series FPGAs using a 32-bit MicroBlaze soft processor core.

This eyescan display can be used by designers to check the quality of the link while fine-tuning the link's characteristics by such means as pre-emphasis (in the ADC) and post-equalization (in the FPGA).

Click here to learn more and to download the reference design, and click here to view a video on JESD204B A/D converters, FPGAs, and eyescan diagrams.