Tech Beat: Codewords cut PCM energy needs

Researchers leverage codeword techniques to minimize PCM energy consumption by as much as 44%.

With the release of 45-nm phase change memory (PCM) modules from by Micron Technology Inc., PCM finally appears to be ready to go prime time. At smaller processes, of course, the approach still has some issues, as anybody who's followed the ongoing debate about the technology on this website knows. One challenge is energy dissipation, a key concern for the types of mobile applications the current Micron product targets. Now, researchers from Rice University and the University of California at Los Angeles have developed a mixed software-memory overhead solution that can cut energy costs by as much as 22.5%.

Phase change memory is based on a material that changes from a conductive crystalline state to a nonconductive, amorphous state with the application of heat. The Rice/UCLA technique leverages the fact that the PCM uses less energy for read operations than for set/reset operations, and focuses on minimizing set/reset. Basically, before writing data to the memory module, the system reads the pre-existing data. An algorithm encodes the new data to reduce the number of bit set/reset operations. Then, it compares the new data to the old data and writes to memory only the data bits of the file that have changed.

The Rice group applied a codeword approach that uses the established N-flip technique to minimize the number of bits that must be flipped when a new word is overwritten on an existing word. In the N-flip technique, a word is written in either its normal or its inverted (logic 1, 0 complement) form, depending on which form minimizes the number of bits that need to be flipped. An extra bit (memory overhead) identifies whether a given word is normal or inverted.

The new method represents each individual word in a specialist data set (ASCII, imaging etc) as a subset of words, each identified by additional code bits. The form of the subset would then be the normal N bits plus the overhead of K code bits, giving a total subset for each word of up to 2K words. The algorithm selects the encoded version of the word that requires the minimum number of highest energy flips for the overwrite procedure.

As an example, consider alphanumeric ASCII code. To simplify the process, the group takes advantage of the fact that seven letters (e,t,a,o,i,n and s) constitute the most commonly used letters in the English language. Clearly, these letters are more likely to be overwritten on each other or overwritten on most of the other letters of the alphabet; indeed, these particular overwrites represent over 60% of all probable overwrites.

According to Ron Neale, our PCM contributor for the Memory Designline, the final version of each of what are called ‘data aware’ words of the most probable seven consists of a 3-bit prefix, the N bits, and the K word option code "The three-bit prefix identifies the one of seven letters, followed by all possible 2(N+K) codes. For example if the letter (e) is in the memory with a given (N+K) bit form from an earlier overwrite, and a new overwrite of the letter (t) is required, then all that is necessary is a change of the 3-bit code —the rest can remain as is." The other, less commonly used letters of the alphabet are given the common prefix of (111) followed by the (N +K) bits of code with those codes selected on the basis of the probability of a particular overwrite.

The group is working with a non-deterministic polynomial (NP) technique, meaning that they start with a likely solution, then test to determine whether or not is correct. "It is a technique that is often applied to code breaking and encryption," says Neale. "You make a guess at some aspect of the solution and then by multiple tedious calculations, test its accuracy. Clearly if on inspection the output of a piece of, say, encrypted text is readable, you can claim you have an NP-complete solution. In the case of power dissipation the test would be whether the power is reduced—the result would be pretty obvious.”

The Rice group balances the energy savings derived by minimizing set/reset against the additional memory overhead to tease out the best possible performance. The team developed a single-level cell (SLC) PCM prototype, leveraging a memory controller from a TI-MSP 430 microcontroller. They used a reset/set energy ratio Er/Es=2 and assumed a negligible read energy. The algorithms that develop the codes run off-line, minimizing the impact on chip performance. The results are saved in the controller, which provides an interface between the PCM and the processor.

In tests, the approach reduced energy cost for saving audio and image data by an average of 15.6% and 22.5%, respectively. Modeling suggests that the theoretical limit could run as high as 44%.

This work raises an interesting question of whether it's best to deal with defects in inherent limitations of memory by modifying hardware or by compensating via these types of mixed memory overhead and software solutions. Given the degree to which hardware solutions promised to aggressively push design roles going forward, compensation may be the most efficient and economical approach.

What do you think?

AcknowledgmentsThanks go to Ronald Neale, former editor-in-chief of Electronic Engineering and senior scientist at Harris Semiconductor, where he was responsible for the PCM development program.

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The whole idea of making this data-dependent is silly and unnecessary. If it were to make sense, then you would be better dealing with the data at a higher level. For example, if you want to store ASCII data efficiently, then compress it first - saving far more than 22%.
There is an extremely simple way to get a similar power saving (over 23%), albeit at the cost of extra bits. For each 8-bit byte, you have an additional "invert" bit. For each data read, you use this bit to see if the data bits should be inverted. When writing, you consider both the non-inverted and inverted versions of the data, and choose whichever uses least power. Simple, fast, low-power, and independent of the data.

Thanks for your comments. That's interesting. Based on the paper, I'd understood that having Er/Es greater than 1 was what delivered the energy savings. I'll have to reach out to the authors and see what they say.

Actually, no—the method works in no small part because the energy required to reset a bit (Er) is roughly twice that of the energy required to set a bit (Es), while the read energy is negligible. It's a nifty bit of work.

Kristin- The RICE authors also raise the subject of multi-level cell (MLC-PCM) and cite the IBM-MLC. It would certainly be interesting to hear their view on how their memory overhead would be added to IBM’s drift compensating codeword memory overhead and methodology. In that respect, they might also need reminding that the write process for the multi-level cell and some earlier MLC work involves starting with a cell in the reset state and reaching the required data state resistance value by iterative steps. How many more memory codeword solutions to PCM memory problems can be added before in becomes a write never memory (WNM) because there is no room for the data?