MIPI RFFE VIP

The MIPI RFFE VIP (RF Front End) is a highly flexible and configurable verification IP that can be easily integrated into any SOC verification environment. Supporting UVM, this RFFE VIP is part of the asureVIP portfolio of implementation-proven VIP offerings.

The MIPI RFFE VIP supports both Master and Slave functionalities and has been entirely programmed in System Verilog and provides support for OVM/UVM based testbenches. The VIP comes with a protocol Bus Monitor which checks for non-compliance with MIPI RFFE specification. The monitor will collect the information from the bus and will frame the high level abstraction classes such as command and address/data frames. During the ‘master passive’ and ‘slave active’ mode configuration the monitor will collect the information from the bus and inform the slave on what command is initiated from the master and how many bytes are to be transferred from slave to Master.

Customers using the asureVIP products do so with the confidence of knowing that they have been independently developed by T&VS and successfully deployed by leading SoC companies around the world.

T&VS can also offer asureVIP customers an independent hardware verification service (asureVERIF) that not only reduces development costs and time-to-to-market, but also improves product quality.

About Us

Organisations developing complex microelectronics and embedded systems use T&VS to test and verify their hardware and software products, employ industry best practice and to help manage peaks in their development and testing programmes. T&VS are experienced in safety certification, security testing, training and also offer Verification IPs and our own EDA tool for requirements management and verification signoff.

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The 2-day Formal Verification Bootcamp is for design and verification engineers looking to enhance their knowledge of formal verification and to learn how to write effective assertions to find and fix bugs. The course is a mix of presentations and hands-on development exercises.