Requirements for and Design of a Processor with Predictable Timing

Abstract

This paper introduces a set of design principles that aim to make processor
architectures amenable to static timing analysis. Based on these principles,
we give a design of a hard real-time processor with predictable timing, which is
simultaneously capable of reaching respectable performance levels.
The design principles we identify are recoverability from information loss in
the analysis, minimal variation of the instruction timing, non-interference between
processor components, deterministic processor behavior, and comprehensive
documentation. The principles are based on our experience and that of other
researchers in building timing analysis tools for existing processors.