on 2/26/03 1:15 PM, John Klos at john@ziaspace.com wrote:
> Hi,
>
> I'm committing code to allow the manual configuration of L3 cache on 7450
> / 7455 based accelerators such as the Sonnet Crescendo PCI.
>
> If you're tracking current, please give this a try. It might also be
> worthwhile if someone could test a manual configuration on a new 745x
> based G4 from Apple, just to make sure it generally works.
>
> In order to test, use values from sys/arch/powerpc/include/spr.h in your
> kernel config like this example:
>
> options L2CR_CONFIG="(L2CR_L2E)"
> options L3CR_CONFIG="(L3CLK_35|L3CKSP_4|L3PSP_0|L3RT_PB2_SRAM)"
There are a couple of caveats to be aware of here.
First, the code will not make any changes to the L3 cache settings if the
cache was already enabled (i.e. if the L3E bit is already set in L3CR).
Additional code would be needed to safely disable the cache before changing
settings, so just disabling this test to try it out would not be a good
idea.
I believe all Apple hardware that shipped with 745x or later CPUs enables L3
in firmware. Of course, verifying that the code leaves well enough alone on
these machines would still be a good test case.
Second, the setting for L3CR_CONFIG given above is only likely to be correct
for this particular piece of hardware (the Sonnet Crescendo PCI G4/700).
Some of the bits in L3CR are dependent on details of the hardware design
that we're not privy to, so anyone who wants to use L3CR_CONFIG will need to
start by discovering the L3CR setting used by their upgrade manufacturer.
(Note that this same problem applies to L2CR_CONFIG for G3 and G4 CPUs
earlier than the 745x series.)
An AGP Power Mac G4 machine with one of the early 745x upgrades that
requires software to enable the L3 cache would be a good, non-trivial test
case. (Perhaps only the PowerLogix cards? Neither Sonnet nor Giga Designs
has any enabler software on their web sites for their AGP machine upgrades.)
With the upgrade manufacturer's software installed, install the Apple "CHUD"
tools from here:
http://developer.apple.com/tools/debuggers.html
and use the "Reggie" application to get the L3CR register setting. This is
the value you'll want to use for L3CR_CONFIG.
(Reggie didn't work on my 7500 for some reason, so I had to resort to other
means...)
> This example gives me this on a 700 MHz 7455 with 256k of L2 cache and 1
> meg of 200 MHz (700 MHz / 3.5) L3 cache:
>
> cpu0 at mainbus0: 7450 (Revision 2.1), ID 0 (primary)
> cpu0: HID0 8450c0a4<EMCP,TBEN,NAP,DPM,ICE,DCE,SGE,BTIC,BHT>
> cpu0: 700.00 MHz
> cpu0: 256KB L2 cache, 1MB L3 backside cache at 3.5:1 ratio
>
> The files changed are sys/arch/powerpc/include/spr.h,
> sys/arch/powerpc/conf/files.powerpc, and sys/arch/powerpc/oea/cpu_subr.c.
>
> Thanks to Monroe Williams for the code. Yay for the fast-as-hell, under
> $300 USD accelerator!
>
> John Klos
-- monroe
------------------------------------------------------------------------
Monroe Williams monroe@pobox.com