Memory test tips #4: Characterizing phase change memory

One of the non-volatile computer memory technologies on the horizon, phase change memory (PCM), might one day replace the flash memory devices now used in everything from digital cameras and mp3 players to smartphones and PCs. Not only is PCM technology much faster and more scalable than flash memory, it’s far more durable. Developing a viable product requires accurate characterization, though. The problem is that conventional methods for measuring load resistance (Rload) can introduce data distortions that compromise results. New techniques involving current limiting and high-speed pulse generators provide a more effective alternative.

Essentially, a PCM cell is a chunk of a chalcogenide alloy that, through the focused application of heat in the form of an electrical pulse, can change rapidly from an ordered crystalline phase with low resistance to a disordered, amorphous phase with much higher resistance. The switch from the crystalline to the amorphous phase and back is triggered by melting and quick cooling (or a slightly slower process known as re-crystallization).

The differing levels of resistivity of the crystalline and amorphous phases of these alloys are what allow them to store binary data. The high resistance amorphous state is used to represent a binary 0; the low resistance crystalline state represents a 1. However, the latest materials and designs support multiple distinct levels, so a single cell can represent multiple bits, for greater memory density.

A germanium/antimony/tellurium alloy known as GST, with a melting temperature in the range of 500º to 600º C, is one of the promising PCM materials now being studied. In the amorphous phase, it has short-range atomic order and low free-electron density, which results in higher resistivity. This is sometimes referred to as the RESET phase, because it is usually formed after a RESET operation, in which the temperature of the device under test (DUT) is raised slightly above the melting point, then suddenly quenched to cool it. The rate of cooling is critical for the formation of the amorphous layer. The typical resistance of the amorphous layer can exceed 1 MO.

In the crystalline phase, the GST material has long-range atomic order and high free-electronic density, which results in lower resistivity. This is also known as the SET phase because it is formed after a SET operation, in which the temperature of the material is raised above the re-crystallization temperature but below the melting point, then cooled slightly slower to allow crystalline grains to form throughout the layer. The typical resistance of the crystalline phase ranges from 1 to 10 kO. Because the crystalline phase is a low-energy state, when heat is applied to material in the amorphous phase and the temperature approaches the crystallization temperature, it tends to change spontaneously to the crystalline phase.

In a typical GST PCM device’s structure, heating/melting affects only a small area around the tip of the resistor, which is attached to the underside of the GST layer (see figure 1). Erase/RESET pulses set high resistance, or logical “0,” and form an area of an amorphous layer on the device. Erase/RESET pulses are higher, narrower, and steeper than Write/SET pulses. A SET pulse, which sets a logical “1,” re-crystallizes the amorphous layer back to the crystalline state.

Figure 1: In a typical GST PCM device structure, a resistor heats a small region of the GST layer to a precise temperature to place it in the convert it to the amorphous state (logical 0), or heats and cools it to the crystalline state (logical 1).