Monday, September 01, 2008

Digital Verification Engineer

This position will work with senior and lead analog and digital designers to verify digital filtering and interfaceblocks.

The sucessful candidate will:

Have knowledge and experience with typical ASIC design/verification flow and tools;Should understand the overall mixed signal functionality of the ASIC.Should be able to abstract analog behavior into simplified Verilog behavioral models.Must be familiar with directed random testing methodologies with experience with System Verilog, Specman, or Vera.Must have experience with code coverage and functional coverage.Must be capable of writing a verification plan.Qualifications Knowledge of Verilog, digital signal processing, system-on-chip (SOC) design. Experience with Cadence NC-Verilog or Synopsys VCS. Experience with System Verilog, Specman, or Vera. Experienced with writing or contributing to test plans. Experie nce with code coverage and functional coverage. Must possess excellent communication skills both oral/written. Bachelors or Masters Degree in EE. 5+ years exp.

Additional Qualifications:Writing System Verilog Assertions a plus. Mixed-signal simulation experience a plus. Experience with power analysis a plus. Experience with ATPG a plus. Experience with Static Timing Analysis a plus. Experience with Matlab a plus.Experience with Verilog A/AMS a plus. Ability to lead a design and verification product development team a plus.