Abstract:Multiprocessor architectures can be used to increase the amount of work that can be performed and to divide the software effort into manageable tasks units. The two major methods of inter-processor communication in these multiprocessors make use of message passing using a communications sub-system or the preparation of data buffers in processor shared memory. A message passing system requires a certain amount of processing overhead which subtracts from the total processing resource. A circuit switched, shared memory multiprocessor based on the two-dimensional spanning bus hypercube is described. This design eliminates most of the processing overhead attributed to message passing systems. Circuit switching allows the sender to transfer directly into the receivers' address space by establishing a dedicated transmission path between the two nodes. Thus, data sets for cascaded calculations (using separate processors) can be prepared directly in the following processors' address space. This work details the design and the operation of the interconnection mechanism. The paper describes the global and local addressing schemes that were devised to allow a VME bus-based multiprocessor to operate as a shared memory multiprocessor configured as a two-dimensional spanning bus hypercube. An intelligent switch has been designed to permit multiple connections within the spanning bus hypercube. A simulation model for the implementation was developed using the NETWORK II.5 simulation system. The design was implemented and tested in 3 μm CMOS using the suite of Mentor Graphics tools to establish the connection and communication delay parameters for the system architecture