Search

Modeling and Implementing High Performance Programs on FPGA

This work investigates the potential of high performance computing (HPC) on fieldprogrammable
gate arrays (FPGAs), highlighting concepts and programming techniques
to pursue performance using high level synthesis (HLS) tools. We compute the peak
single precision floating point performance on the AlphaData 7V3 board using a model
of replicated processing elements, then implement a benchmark to verify the predicted
performance in hardware, using both the SDAccel framework and a custom reference
design provided by Xilinx. The benchmarks reach 302GOp/s and 548GOp/s on the two
platforms, respectively. The techniques are applied to the field of stencil computations,
proposing a temporally pipelined streaming design for the 2D Jacobian stencil that
scales with available area on the chip, by using on-chip memory to buffer the incoming
wavefront, achieving a sustained performance of 256GOp/s on a 256 × 256 grid. Finally
the current state of FPGAs is discussed based on the results obtained, and comments
are made on the future of reconfigurable computing in HPCShow more