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Synthesis with Higher Abstractions for Effort-Less FPGA Programming

Zhiru Zhang, Cornell University

Friday 2/6, 11:30-12:30pm

CIC Panther Hollow

Abstract

Over the last two decades, FPGAs have evolved from a small chip with a few thousand logic blocks to heterogeneous system-on-chips containing hardened DSP blocks, embedded memories, and billions of transistors. These advances have made FPGAs an attractive hardware device for high-performance reconfigurable computing. However, there is still a considerable productivity gap between register-transfer level FPGA design and traditional software design. Enabling high-level programming of FPGAs is a critical step in bridging this gap and pushing FPGAs further into the computing space.

In this talk, I will briefly review the progress we have made in research and commercialization on high-level synthesis (HLS) for FPGAs. In particular, I will use a few industrial designs as case studies to motivate the need for HLS tools, and explore their benefits and limitations. I will further describe novel scheduling and mapping algorithms that significantly improve the quality of the synthesized designs. Afterwards, I will outline additional research challenges and introduce some of our ongoing work along those directions.

Bio

Dr. Zhiru Zhang is an assistant professor in the School of ECE at Cornell University and a member of the Computer Systems Laboratory. His current research focuses on high-level design automation for heterogeneous computing. His work has been recognized with a best paper award from TODAES and the Ross Freeman award for technical innovation from Xilinx. In 2006, he co-founded AutoESL Design Technologies, Inc. to commercialize his PhD dissertation research on high-level synthesis. AutoESL was acquired by Xilinx in 2011 and the AutoESL tool was rebranded as Vivado HLS after the acquisition.