Manufacturing Bits: July 8

Intel foundry deal
At the Semicon West trade show in San Francisco, Intelannounced that it has entered into a foundry agreement with Panasonic’s LSI Business Division. Intel’s custom foundry business will manufacture future Panasonic system-on-chips (SoCs) using Intel’s 14nm low-power manufacturing process.

Intel’s low-power process will be a derivative of its general-purpose 14nm process, said Sunit Rikhi, vice president and general manager of Intel’s Custom Foundry unit. Panasonic’s next-generation SoCs will target the audio visual-based equipment markets.

Intel’s 14nm process, to roll out later this year, is the company’s second-generation finFET technology. Five other semiconductor companies have announced agreements with Intel’s custom foundry business, including Altera, Achronix Semiconductor, Tabula, Netronome and Microsemi.

New Applied-TEL name
At Semicon, Applied Materials and Tokyo Electron Ltd. (TEL) unveiled the new name of their combined company, which will be used once the merger closes in the second half of 2014. The new name is Eteris, which is derived from the concept of eternal innovation for society. No other details were given for the combined company.

In addition, looking to accelerate the development of finFETs and 3D NAND, Applied Materials has rolled out two new tools. One tool is targeted to bring down the cost of chemical mechanical polishing (CMP), while the other addresses issues with chemical vapor deposition (CVD).

CMP is an enabler for the finFET gate and the staircase structure in 3D NAND. These new device architectures can require as many as 10 additional polishing steps, which can drive up costs, according to Sidney Huey, global product manager for CMP at Applied.

The new Reflexion LK Prime CMP system from Applied is designed to address the problem. The tool features six polishing stations and eight integrated cleaning stations with process control. The increase in process modules doubles wafer throughput for many applications, providing up to a 100% boost in productivity, he said.

Meanwhile, 3D NAND requires enabling deposition technology for vertical gate formation and patterning applications. In fact, there are two challenges in CVD for 3D NAND. “The challenge is the layer-to-layer control on the gate stack,” said Terrance Lee, vice president of marketing and strategy for the Dielectric Systems and Module unit at Applied. The other challenge is the development of the hard mask, Lee said.

The new Producer XP Precision CVD system from Applied supports the 3D NAND transition by delivering layer-to-layer film thickness control for CD uniformity across the wafer. A new modular mainframe architecture and high-speed protocol further increase high-throughput density and low cost of ownership.

What are Shrinky Dinks?
Nanowires are a promising technology for future transistors, but they are difficult to align in the same direction at tiny dimensions.

The University of Illinois at Urbana-Champaign has apparently solved the problem by devising a technology called Shrinky Dinks. Using a self-assembly process, the technology shrinks plastic polymers under high heat. The self-assembly process enables researchers to create dense arrays of nanowires in a controllable way.

Illinois researchers are using plastic that shrinks when heated to pack nanowires together for electronics applications. (Source: SungWoo Nam)

In the lab, researchers have demonstrated an approach to assemble a parallel array of nanowires using shrinkable shape memory polymers. Using the thermal-induced shrinkage of polystyrene, researchers achieve tunable densities up to 300% amplification in a controlled process.

They also demonstrated a scalable assembly of nanowires on a 2.5- × 6-inch scale. Researchers also demonstrate the transfer of the shrink-assembled nanowire arrays onto 2D and 3D substrates.

“Chemists have already done a brilliant job in making nanowires exhibit very high performance. We just don’t have a way to put them into a material that we can handle,” said SungWoo Nam, a professor of mechanical science and engineering at the The University of Illinois at Urbana-Champaign, in a statement on the university’s Web site. “With the shrinking approach, people can make nanowires and nanotubes using any method they like and use the shrinking action to compact them into a higher density.”

The group is now exploring a thin-film solar cell technology based on nanowires. This technology could be more efficient than traditional thin-film solar cells.

Making invisible chips
The National Institute of Standards and Technology (NIST) has devised a novel metamaterial structure, which operates at a lateral spatial frequency that exceeds the diffraction limit. In other words, the structure can stop light in one direction, but lets it pass in the other.

In the future, the technology could be used in applications like optical communications. Metamaterials involve materials that reverse the refractive index. The technology has also been used to form cloaking devices that appear invisible.

Existing metamaterials are difficult to make. It is problematic to devise materials at scales small enough to manipulate the short wavelength of visible light, according to NIST. In the lab, however, NIST demonstrated that high-contrast asymmetric transmission of visible light can be provided by a planar device of wavelength-scale thickness. The device consisted of a pair of non-symmetric sub-wavelength gratings and a passive hyperbolic metamaterial.

For this device, NIST combined two light-manipulating nanostructures–a multi-layered block of alternating silver and glass sheets and metal grates with very narrow spacings. According to NIST, the block is opaque to visible light coming in from outside. Light can propagate inside the structure within a narrow range of angles.

In the future, the new structure could be integrated into photonic chips and bio-sensing systems.