Abstract

Major concern in a high speed digital to analogue converter (DAC) is the occurrence of glitches which limiting the performance of the converter. As technology moving toward higher speed and smaller sizes, eliminating glitches is very important to ensure maximum performance of a DAC. Glitches limit maximum performance of a DAC especially in term of switching speed where it restrict the high speed performance of DAC. In some cases glitches can cause the converter to be unusable. This work discusses the design methodology to further improve glitches in the existing hybrid DAC with current-limited swing reduced driver circuit. The 12 bit hybrid DAC architectures is composed of 8-LSB binary-weighted resistor and 4-MSB thermometer coding in order to have optimize performance. The improved DAC design is accomplished by incorporating a Low Pass RC filter which function to attenuate the amplitude of the glitch that exceed the cutoff frequency, Fc . Simulation results shows that glitch impulse area was 9.1046pVs while peak glitch is only 1.08mV. This results indicates that this design achieves 70% improvement in glitch impulse area reduction compared with original version DAC and showing improvement of 47.71% compared to DAC with only current limited SRD. Overall, this project have successfully achieves lower glitch impulse are