Falling between low-level IP components such as adders and
multipliers and large IP blocks including Ethernet, PCI, H.264 and
processors, these blocks fill a void in the middle of the IP space.
This is the area used most often by internal design teams, but
inadequately addressed with current IP due to the level of
customization required for each application.

At the heart of Bluespec's' bus fabric IP offering is a unique
Transaction Level Modeling (TLM2) bus payload data structure and
protocol. This generic representation supports multiple bus protocols
and is based on the Open SystemC Initiative (OSCI) TLM 2.0 draft
specification. Use of the TLM2 representation allows designers to work
with bus interactions on a transaction level for high-level modeling
or efficient hardware implementation. DetailsD of each bus-specific
signaling protocol are encapsulated within library building blocks,
eliminating the need to be re-designed and re-verified each time a
design includes channels or interfaces based on that protocol.

Package Components

For each supported bus protocol, the associated AzureIP package
includes:

Master Transactor to convertc a stream of TLM2 operation
descriptors, communicated through transaction level GET/PUT
interfaces, into a sequence of protocol-specific bus operations.

Slave Transactor to convert a sequence of protocol-specific bus
operations into a stream of TLM2 operation descriptors, communicated
through transaction level GET/PUT interfaces.

Bus Fabric Constructor, a modulem constructor that, given a set of
master and slave interfaces, creates the complete bus fabric and any
associated arbiters as required.

Extreme Reuse

The unique capabilities of Bluespec's' patented technology allow
designers using these packages to achieve levels of design reuse
unavailable using other technologies. Since AzureIP package components
are implemented natively in Bluespec source code, they do not
represent fixed modules with a few, pre-selected degrees of
parameterization.

Instead, each package component represents a design template,
which is automatically transformed by the Bluespec compiler into a
specific instantiation, parameterized and optimized to the specific
application context of each use. Unused capabilities are automatically
removed, saving power and area as compared to the results that can be
achieved using more traditional hardware IP.

As the TLM2 structure is common to different bus structures,
entire designs can be completed and verified independent of the
specific bus protocol selected for each interface or communication
channel. This allows a single design to be used in multiple
applications, each time using a different set of selected bus
protocols. This flexibility also allows designers to postpone
decisions regarding which protocol to use until late in the design
cycle.

AzureIP Foundation Libraries

Bluespec, developer of the only ESL synthesis for control logic
and complex datapaths in chip design, has developed these libraries to
offer ESL designers flexibility, along with an ability to modify and
synthesize their designs. The AzureIP Foundation Library, first
introduced earlier this year, is a path to faster time to market,
rapid design composition, including customization and reuse, increased
quality and decreased verification costs.

Built at the transaction level for quick simulation, blocks can be
automatically compiled to efficient, detailed register transfer level
(RTL) code. Blocks can be used at any level of abstraction, from
abstract, system-level modeling to a more detailed ESL implementation.
Parameterized building blocks deliver plug-and-play customization.

In related news, Bluespec and EVE today announced immediate
availability of an integrated solution of ESL synthesizeable
transactors and models that run on EVE's hardware-assisted
verification platforms. (See news release dated May 7, 2007, titled:
"Bluespec, EVE Create Platform for ESL Verification, Modeling,
Architectural Design.") This integration offers high simulation speed
with hardware accuracy early in the development cycle for
architectural exploration, virtual prototyping, modeling and
verification.

Bluespec's entire product line will be demonstrated in Booth #6963
during the 44th Design Automation Conference (DAC) June 4-8 at the San
Diego Convention Center in San Diego, Calif.

Pricing and Availability

The AzureIP Foundation Libraries are included as part of
Bluespec's ESL software. Design services are available to further
accelerate system modeling and implementation.

Contact George Harper, Bluespec's vice president of marketing, for
more details. He can be reached at (781) 250-2200 or via email at
george.harper@bluespec.com.

About Bluespec

Bluespec Inc. manufactures an industry standards-based Electronic
Design Automation (EDA) toolset that significantly raises the level of
abstraction for hardware design while retaining the ability to
automatically synthesize high-quality RTL, without compromising speed,
power or area. The toolset, the only one focused on control and
complex datapaths, allows ASIC and FPGA designers to reduce design
time, bugs and re-spins that contribute to product delays and
escalating costs. More information can be found on www.bluespec.com or
by calling (781) 250-2200.

Copyright 2007 Bluespec Inc. Bluespec and AzureIP are trademarks
of Bluespec Inc. AMBA, AHB and AXI are trademarks of ARM Limited. All
other brands, products or service names may be trademarks or service
marks of the companies with which they are associated.
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