A Page of Links - useful places to find more about SystemC, TLM2 and its ecosystem. Click on the logos.

Simulator Vendors:

Imperas Software Imperas is a young company producing tools and technologies for virtual platforms. Imperas was the instigator of Open Virtual Platforms and the creator of much of the OVP technology and models. Imperas provides the fastest OVP simulators and develops and markets advanced tools for software development using virtual platforms.

Open Virtual Platforms OVPworld.org is the site for downloading the OVPsim simulator and the distribution packages of the OVP Fast Processor Models. There are open source models of processors as well as virtualization peripherals for components such as ethernet, keyboard, mouse, LCD.

Cadence Design Systems Part of the Cadence System Development Suite, the Virtual System Platform enables pre-RTL software design, verification, and system analysis before committing to hardware design. It automates the process of creating a virtual prototype, debugging software, and deploying the virtual prototype to the software team—allowing software development to begin months earlier and preventing schedule slips in prototype delivery.

Mentor Graphics Vista™ is a complete TLM 2.0-based solution for architecture design, analysis, verification and virtual prototyping enabling system architects and SoC designers to make viable architecture decisions and enabling hardware and software engineers validate their hardware and software.

Accellera OSCI SystemC [Accellera took over OSCI in 2015] The Open SystemC Initiative (now part of Accelera) is dedicated to defining and advancing SystemC standards for system-level design. Standards are developed in a collaborative and open environment by technical working groups. Core SystemC Language and Examples, Release 2.2 can be downloaded including the open source OSCI reference SystemC TLM2 simulator.

User Groups:

NASCUG The North American SystemC Users Group (NASCUG) organization accelerates the use of SystemC for new and established users of the language in North America.

ESCUG European SystemC Users Group. If you want to join the European SystemC Users Group, or if you have any question concering the European SystemC Users Group, please feel free to contact Axel Braun.

JSCUF Japan SystemC Users Forum. The SystemC standard language has made ESL methodology widely used in industries, said Toshibas Hiroshi Imai, chair of the SystemC Working Group in Japan, EDA-TC/JEITA. The TLM-2.0 standard will help broaden the use of the ESL methodology to overcome the challenges of design productivity and quality.

TSCUG Taiwan SystemC Users Group. In 2005, Taiwan launched various ESL movements in education, training, standardization and industrialization. As part of that movement, an ESL Working Group was formed within the Taiwan SoC Consortium to raise the awareness and promote the adoption of ESL design methodologies. Recognizing the importance of SystemC to the ESL community, the ESL WG recently transformed to become the Taiwan SystemC Users Group (TSCUG), an independent user organization that will host regular open forums to further promote ESL technologies.

LASCUG Latin American SystemC Users Group. Latin American groups were early adopters of SystemC from its very beginning, and the use of the language has grown considerably since then, said Professor Guido Araujo of Brazils Computer Systems Laboratory at the University of Campinas, and organizer of the Latin America SystemC Users Group (LASCUG). LASCUG grew up from the need of these groups to collectively share their ideas and accumulated knowledge on SystemC technologies and applications. LASCUG will allow us to increase the dissemination of SystemC in Latin America, while enabling a valuable repository of knowledge and experiences for the region.

Silicon IP Developers:

ARM Holdings The ARM comprehensive product offering includes 32-bit and 64-bit RISC microprocessors, graphics processors, enabling software, cell libraries, embedded memories, high-speed connectivity products, peripherals and development tools. Combined with comprehensive design services, training, support and maintenance, and the companys broad Partner community, they provide a total system solution that offers a fast, reliable path to market for leading electronics companies.

MIPS MIPS is a leading provider of intellectual property (IP) processor architectures and cores which are broadly used in products such as consumer entertainment, home networking and infrastructure equipment, LTE modems and embedded applications. MIPS is also at the heart of a growing number of Internet of Things (IoT) devices, advanced driver assistance systems (ADAS) and emerging intelligent applications including autonomous vehicles. Originally founded in 1984 as MIPS Computer Systems Inc. by researchers from Stanford University, today MIPS designs have shipped in billions of units across the globe and have even reached the outer edges of our solar system.

Synopsys ARC Synopsys offers a comprehensive spectrum of configurable cores ranging from the industrys smallest and lowest power to 1650 DMIPS of performance. Synopsys configurable processor technology has been used by over 150 customers worldwide who collectively ship more than 550 million ARC-based chips annually. Designers can differentiate their products by tailoring DesignWare® ARC® configurable cores to the target systems requirements using its patented configuration technology. The DesignWare ARC configurable CPU/DSP cores enable SoC designers to build highly competitive products by easily customizing the core to a target application.

Cadence Tensilica Tensilica is the #1 supplier of audio DSP IP cores and 4G baseband DSP IP cores for the mobile, handset, and home entertainment markets. In fact, no matter what the function is, if your SOC design demands a highly-efficient, programmable computational engine for a data-intensive task, Tensilica innovative technology can provide a solution for you. For the most common and broadly applicable tasks in the dataplane, Tensilica has ready made solutions like our HiFi Audio DSPs, our ConnX Communications DSPs and our Diamond Standard controllers for deeply embedded dataplane control.

Andes Andes Technology Corporation was founded in Hsinchu Science Park, Taiwan in 2005 to develop innovative high-performance/low-power 32-bit/64-bit processor cores and its associated development environment to serve worldwide rapidly-growing embedded system applications. It delivers the best super low power CPU cores with integrated development environment and associated software and hardware solutions for SoC development.
In order to meet demanding requirements of todays electronic devices, Andes delivers configurable software/hardware IP and scalable platforms to respond to customers’ needs for quality products and faster time-to-market. Andes comprehensive CPU includes entry-level, mid-range, high-end, extensible and security families to address full range of embedded electronics products, especially for connected, smart and green applications.
For more information about Andes Technology, please visit http://www.andestech.com

RISC-V RISC-V (pronounced risk-five) is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. The RISC-V ISA was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.

Renesas Renesas Electronics Corporation (TSE: 6723), the worlds number one supplier of microcontrollers, is a premier supplier of advanced semiconductor solutions including microcontrollers, SoC solutions and a broad range of analog and power devices. Business operations began as Renesas Electronics in April 2010 through the integration of NEC Electronics Corporation (TSE:6723) and Renesas Technology Corp., with operations spanning research, development, design and manufacturing for a wide range of applications. Headquartered in Japan, Renesas Electronics has subsidiaries in 20 countries worldwide.

Books:

IEEE 1666 LRM Provides a precise and complete definition of the SystemC class library. SystemC is an ANSI standard C++ class library for system and hardware design.

SystemC: From the Ground Up Black, David C., Donovan, Jack. SystemC provides a robust set of extensions to C++ that enables rapid development of complex hardware/software systems. This book focuses on the practical uses of the language for modeling real systems. The wealth of examples and downloadable code methodically guide the reader through the finer points of the SystemC language.

Transaction-Level Modeling with SystemC TLM Concepts and Applications for Embedded Systems. Ghenassia, Frank (Ed.) Currently employed at STMicroelectronics, Transactional-Level Modeling (TLM) puts forward a novel SoC design methodology beyond RTL with measured improvements of productivity and first time silicon success. The SystemC consortium has published the official TLM development kit in May 2005 to standardize this modeling technique.

ESL Design and Verification. A Prescription for Electronic System Level Methodology Electronic System Level (ESL) design has mainstreamed – it is now an established approach at most of the worlds leading system-on-chip (SoC) design companies and is being used increasingly in system design. From its genesis as an algorithm modeling methodology with no links to implementation, ESL is evolving into a set of complementary methodologies that enable embedded system design, verification and debug through to the hardware and software implementation of custom SoC, system-on-FPGA, system-on-board, and entire multi-board systems. This book arises from experience the authors have gained from years of work as industry practitioners in the Electronic System Level design area; they have seen SLD or ESL go through many stages and false starts, and have observed that the shift in design methodologies to ESL is finally occurring.

Doulos Doulos has been at the heart of SystemC language and methodology development right from the start. Authors of the LRM and contracted by OSCI to write the new Transaction Level Modeling Standard (TLM-2.0), Doulos SystemC experts have been on the front line of SystemC application, working alongside customers, since 2001. More than 600 companies worldwide have benefited from Doulos SystemC training and project support.

Forte Design Systems This introductory course is intended for designers who are investigating language alternatives for high-level design. SystemC is an open source C++ library that is emerging as a standard for high-level design and system modeling. Designers who complete the course will gain a clear understanding of the fundamentals of SystemC and considerations affecting its choice as a language for high-level design.

Model Providers:

Imperas Software Imperas is a young company producing tools and technologies for virtual platforms. Imperas was the instigator of Open Virtual Platforms and the creator of much of the OVP technology and models. Imperas provides the fastest OVP simulators and develops and markets advanced tools for software development using virtual platforms.

Open Virtual Platforms OVPworld.org is the site for downloading the OVPsim simulator and the distribution packages of the OVP Fast Processor Models. There are open source models of processors as well as virtualization peripherals for components such as ethernet, keyboard, mouse, LCD.

Hardware Accelerators and Emulators:

Cadence Design Systems The Cadence® Palladium® series delivers high system throughput, verification automation, and advanced debug to perform plan- and metric-driven system-level hardware/software co-verification. Capable of handling chip designs of up to 256 million gates, it also enables software to be developed and verified on a real hardware implementation using live data. The Palladium series leverages advanced RTL and ESL verification automation features, such as assertion-based acceleration and transaction-based acceleration. It also uses real-world stimuli provided by external equipment. The Palladium series emulates HW/SW designs at up to MHz speeds— months before silicon tapeout—reducing the risk in committing to final silicon.

Mentor The Veloce® Emulation Platform dramatically reduces risk in the verification of today’s complex SoCs and is a core technology in the Mentor Enterprise Verification Platform™ (EVP). The Veloce2 emulator is the leading high-performance, high-capacity hardware-assisted solution for verifying embedded systems and SoC designs. The Veloce emulator accelerates block and full SoC RTL simulations during all phases of the design process.

Synopsys EVE Synopsys (with its acquisition of EVE) is the leader in Hardware/Software Co-Verification. Nine of the top 10 semiconductor companies rely on ZeBu fast emulators to verify their SOCs. Early SOC and SW development may leverage an Instruction Set Simulator (ISS) for the processor core, often written in C or SystemC, and operating at a higher level of abstraction than the SOC sub-system. An ISS can be integrated with ZeBu via a transactor (e.g. AMBA AXI) to provide a high-performance link to the rest of the emulated SOC.

Aldec Virtual platforms play a significant role in system level development, but require integration with ultra fast emulation systems for HW/SW co-verification. The integration of Aldecs Transaction Level Emulation System with Imperas OVPsim virtual platform simulator provides a high performance solution, ideal for early HW/SW co-development and architectural exploration.

Model Service Providers:

Circuit Sutra CircuitSutra is an emerging company focusing on SystemC modeling services to create virtual platforms of SoCs and to use OVP virtual platforms to provide embedded software services. Starting with the open framework of OVP, CircuitSutra has integrated SystemC / TLM2.0 models into OVP based virtual platforms, and added drivers for those peripherals that have been added to the virtual platform.

Nuum Solutions Nuum Solutions is an OVP partner providing embedded software / systems and OVP model development services to their clients. Their expertise is in aerospace, industrial automation and commercial broadcasting. Nuum has found that virtual platforms are a great addition to their embedded system development methodology, and have written two white papers on the use of virtual platforms. More information can be found on their OVP Library page.

Posedge Software Posedge Software is a consulting company providing services in the areas of embedded software development and verification and hardware verification. Posedge also has significant experience integrating various tools to achieve a product flow for a specific task. Posedge has used OVP for virtual platform development, and integrated it with SystemC/TLM-2.0 environments, as well as using OVPsim with Cadences Specman ISX verification product. Posedge presented a paper on this at the 2009 Virtual Platform Workshop and have additional information on their OVP Library page.

Sibridge Technologies Sibridge Technologies is an electronic design services company focused on providing innovative solutions for design, verification, and silicon platform software development for semiconductor products. Sibridge offers a unique blend of three critical components in the development of SoCs: design and verification IP portfolios; strong chip design, integration and verification expertise; and pre- and post- silicon firmware development and validation. Sibridge has used OVP technology for embedded software development, co-authoring an article on their experience titled Audio-Decode Application Is Realized on Open Virtual Platform. and providing models back on their OVP Library page.

Industry Organizations:

IEEE 1666 LRM Provides a precise and complete definition of the SystemC class library. SystemC is an ANSI standard C++ class library for system and hardware design.

OSCI The Open SystemC Initiative (OSCI) is an independent, not-for-profit association composed of a broad range of organizations dedicated to defining and advancing SystemC as an open industry standard for system-level modeling, design and verification. SystemC is a language built in C++ that spans from concept to implementation in hardware and software.

Accellera Accelleras mission is to drive worldwide development and use of standards required by systems, semiconductor and design tools companies, which enhance a language-based design automation process. Its Board of Directors guides all the operations and activities of the organization and is comprised of representatives from ASIC manufacturers, systems companies and design tool vendors.

OCP-IP OCP-IP (Open Core Protocol International Partnership) is an organization dedicated to supporting and proliferating the OCP core interface, or socket, for plug and play SoC design. OCP-IP has developed a virtual platform based demo which uses SystemC/TLM-2.0 components and an OVP processor model and virtual platform. A number of the components were created using OCP-IPs Modeling Kit. For more information on the OCP-IP virtual platform demo, visit the OCP-IP site.

Other Places with good information:

Wikipedia SystemC: From Wikipedia, the free encyclopedia. SystemC is a set of C++ classes and macros which provide an event-driven simulation kernel in C++ (see also discrete event simulation). These facilities enable a designer to simulate concurrent processes, each described using plain C++ syntax. SystemC processes can communicate in a simulated real-time environment, using signals of all the datatypes offered by C++, some additional ones offered by the SystemC library, as well as user defined. In certain respects, SystemC deliberately mimics the hardware description languages VHDL and Verilog, but is more aptly described as a system-level modeling language.