The XU-RT integrates complex, 2.5 GSPS digitizing and signal generation with real-time signal processing on an XMC IO module for demanding DSP applications. The tight coupling of the analog I/O to the Kintex Ultrascale FPGA core realizes architectures for SDR, RADAR, DRFM and LIDAR front end sensor digitizing and processing. The PCI Express system interface sustains transfer rates over 7.2 GB/s for data recording and integration as part of a high performance real-time system.

The XU-RT features a dual-channel, 14-bit 2.5 GSPS A/D and a dual-channel, 2.8 GSPS 16-bit DAC, each with bandwidth over 5 GHz for wideband, undersampling applications. Internal mixers and decimator/interpolator capabilities (respectively) support concurrent, real-time frequency conversion. The sample clock may be sourced a low-jitter internal PLL or externally via a front-panel SMA and multiple cards can be synchronized for sampling or up/down-conversion.

A Xilinx Kintex Ultrascale XCKU 060/085 with 2 banks of 2GB DRAM provide a very high performance DSP core for demanding applications such RADAR and wireless IF generation. The close integration of the analog IO, memory and host interface with the FPGA enables real-time signal processing at extremely high rates.

The XU family can be fully customized using VHDL and MATLAB and the FrameWork Logic toolset. The MATLAB BSP supports real-time hardware-in-the- loop development using the graphical, block diagram Simulink environment with Xilinx System Generator.

IP logic cores are also available for SDR applications that provide multi-channel modulations for PSK and FSK systems. These IP cores transform the XU-RT module into versatile receiver and transmitter, ready for integration into your application.

Software tools for host development include C++ libraries and drivers for Windows and Linux. Application examples demonstrating the module features and use are provided, including streaming DAC samples from disk. The XU-RT can be used with the Andale high speed data record/playback system for arbitrary waveform generation from recorded data at sustained rates of 7600 MB/s.

The board comes complete with working logic (Framework Logic) and software drivers (Malibu). Please see the data flow diagram.

The simplied data flow from Adc(s) to host application works as follows. Samples from the Adc(s) are clocked into the FPGA. The samples are packed where necessary for efficient use of the RAM chips. The RAM is used as a virtual FIFO to decouple the continuous stream of the Adc(s) from the block transfer nature of PCIe. The user application sets the packetsize. When a whole packet of data is available in the RAM, the PCIe DMA controller does a bus master transfer to the host memory. At configuration time the device drivers reserve physical memory for this purpose. When the transfer is complete, the DMA controller sends an interrupt to Malibu which then copies the packet from the busmaster area to virtual memory and then fires an event in the User application with a reference to the data.

The simplified data flow in the reverse direction for host to Dac(s) is similar. Onboard RAM is configured as a virtual FIFO between the PCIe and the Dac(s). When there is room in the RAM chips for a packet of samples, the PCIe DMA controller interrupts the host, which then signals the application to provide a packet of samples. The samples are copied from virtual memory to physical memory and then the PCIe DMA controller copies them into RAM. As data is flowed to the DAC(s) the RAM has more space for more packets and so the process is repeated.

The product comes with the following support items to help you with your project:

Malibu Software, including

Arb, Snap, Wave & Stream – example applications as sourcecode to setup the board for acquisition and waveform generation. Shows designer how to stream Adc samples to host file and stream from host to Dacs, written in C++.