OCP1 has a rearranged switching stage and the IRS20957S can directly see the Uds of the upper and the lower MosFet.
The data sheet basically would allow the resulting fast changes of the floating Vss. Theoretically - but I never tried and I am not sure if we can trust in this.
Furtheron this arrangement also slightly impacts the driver voltages and also the overvoltage protection would need some reconfiguration.
Zero real life experience how IRS20957 will act and which pitfalls in layout are related to this.
Overall a configuration with many potential risks.

OCP2 is giving direct information to IRS20957 about the Uds of the high side MosFet, but the low side detects Vds+Vf.
Vds+Vf will be about 500..700mV larger than Vds, ==> I adjusted the OCP divider accordingly.
More unpleasant is that Vds+Vf will have systematically more disturbances than the nicely snubbered Vds only. ==> Layout less forgiving.
Also the temperature coefficent of Vf is negative, which will reduce the feature of temperature depending shut down levels.
Overall some downsides visible, but not to many unknown risks.

I am voting for the configuration OCP2.
What do you think?
Or are there already real life experiences for the attached configurations with IRS20957?

In the schematics of the previous posting the switching stages look so simple.
Two MosFets, four diodes and some rail caps.

The attached file shows my model in LT-Spice of one reasonable layout arrangement for the version OCP2. The model translates the obvious parasitics of the layout and also ESR and LSR of the caps into an equivalent electrical circuit.
Not modeled are the less obvious parasitics, which would need a 3D FE simulation of the electrical and magnetic fields......

Why do I attempt to model it?
- It is always better to know about the short comings of a layout, rather than living on the edge as a result of trial and error.
- Trashing multiple real PCBs is expensive. Better spend the money on components, but not on trashing FR4. Of course a perfect first shot is unrealistic, but a satisfying good working first shot is clearly my goal.
- Less repetitive 'dumb work'.

Layout is by far not ready, but started.
Please note, the large inductance (L_snub3, L_snub4) of the snubbers is an intended resonant optimization. ==> Good snubbering with a small snubber cap and low snubber losses. The inductance could be reached by a large geometric loop of the snubber, but for the sake of radiated EMI I will keep the loops small and adjust the inductance by small torroids (material 2 or 6) across the legs of the snubber resistors.

Hope you can see the model in the attached file.
So far transferring the WMF from LTspice into a word file seems to be the best method to post larger schematics from LTspice....

Why do I attempt to model it?
- It is always better to know about the short comings of a layout, rather than living on the edge as a result of trial and error.
- Trashing multiple real PCBs is expensive. Better spend the money on components, but not on trashing FR4. Of course a perfect first shot is unrealistic, but a satisfying good working first shot is clearly my goal.
- Less repetitive 'dumb work'.

Really true, im curious how did you calculate the inductance for a PCB track? my meter cannot go that low.. of course speaking under the assumption you didn't feed a high frequency signal into the track path and view the respected change of the signal. Question is purely from a instrument measurement view.

I also cannot measure it, except feeding a defined high di/dt through a track and measure the voltage drop. U= L*di/dt.
But there are good rules of thumb for calculation from geometry. It is not rocket science.
It is more about using old and well known fundamental know how.
Have a look to slyp173 from TI. www.ti.com/lit/ml/slyp173/slyp173.pdf

Markus, what's your experience on PCB thickness and its impact to inductance and reliability? Next time I think am going to go for 0.4mm or even thinner PCB instead of typical 1.6mm FR4 PCB to cut the inductance. What I am concerned about is reliability, especially for SMD ceramic capacitors, like 0603, 1206 and 1812, which can fail if too much strain is applied to them. What do you think?

I also cannot measure it, except feeding a defined high di/dt through a track and measure the voltage drop. U= L*di/dt.
But there are good rules of thumb for calculation from geometry. It is not rocket science.
It is more about using old and well known fundamental know how.
Have a look to slyp173 from TI. www.ti.com/lit/ml/slyp173/slyp173.pdf

Thanks for the material, read a few parts of the paper that i found interesting not all (got a bit lazy)

Ive also educated myself with more supporting matreial that can help one gets to PCB devlopment like ESR, resonance circuits.

BTW have you tried to tame mosfet gate drive ringing using "axel bead HF inductors".. i would really like to see the effects its has in the 50Mhz region. Its a pity i havent developed a home made PCB (ever) im trying to gather as muchas i can before undertaking expensive options like this.

@Adam:
Answering your questions on PCB thickness and SMD caps might violate the trust of my employer. Sorry, there will be once and while topics that I cannot share. (For the same reason I reduced and finally stopped to comment on the SMPS discussions, because my work evolved more and more close to that topic.)

@Reactance:
So far my gate drive always turned reasonably calm, as soon as the drain-source-snubbering was OK. Up to now my gate snubbers (if any at all) were more a cosmetic topic. Also in the current design I am not convinced whether I will really need them.
Do you mean 'axel bead HF inductors' or axial bead HF inductors?
In case you really mean 'axel', please post a link/picture - never heard this name.

@Tower:
...let's hope that we will still like the design idea, when reality enters the catwalk.

Markus, what's your experience on PCB thickness and its impact to inductance and reliability? Next time I think am going to go for 0.4mm or even thinner PCB instead of typical 1.6mm FR4 PCB to cut the inductance. What I am concerned about is reliability, especially for SMD ceramic capacitors, like 0603, 1206 and 1812, which can fail if too much strain is applied to them. What do you think?

Well i prefer 2.4mm thick PCBs which allow me to directly solder SMD 805 chip ceramics vertically from TOP to Bottom layer thru holes[NPTH] in key places and works like a magic.