ASHIM GUPTA

R&D engineer expert in design and delivering new technologies in very large systems as well as small turnkey projects. Customer centric with distinguished talent to understand requirements, analyze usability and model common engineering solutions. Effective at collaborating with different product groups, resolving conflicts while focusing on product deployment. Skilled in software programming & algorithms, with an aptitude of problem solving.

Founder and Chief Editor of Practical Management, providing free management articles designed for existing or aspiring managers and leaders in the organization.

Developed a new technology for IC Compiler & Design compiler product for low power design flow. . The new chip design style was emerging that optimized the power by varying the voltage, frequencies and on-state of different functional blocks in the design. The key implementation roles included:-

Implemented the physical design partitioning of the chip into voltage areas and placement of cells with new constraints.

Introduced new library specifications for special power management cells like level-shifters & mtcmos switch cells in synopsys liberty specifications.

Introduced new specifications for power domains and power connectivity prior to UPF.

Implemented insertion and placement of power management cells in the design.

Enhanced the existing logical & physical optimization to work on new power partitions.

Developed rules for power and ground connectivity based on which the tool could automatically connect the power/ground for the low power design.

Contributed to the “Accelera -Unified Power Format” effort in which the EDA industry wanted a consolidated power constraints standard for low power design methodology.

Collaborated with other groups in Synopsys to make them migrate to low power flow by providing them training and consultation on the technology. This involved reviewing their project designs and managing dependencies between the projects , providing common functionalities to all of them.

Conceptualized and led few projects to streamline the reporting mechanism for low power designs. This was acknowledged by the customers as a big improvement in the usability of the solution and provided critical insight into their design specifications.

Successfully provided closure on various critical customer engagements, building customer confidence in Synopsys low power solution and it’s seamless adoption

Worked with different R&D teams across the globe, improved team effectiveness through common knowledge sharing and achieved resource efficiency through proper mentoring. Created guidelines for working with new and offshore teams, such that it leads to a win-win situation for all rather than conflict of interests

Developed small web applications using CGI/perl for team collaboration and task assignments and tracking.

Developed the front-end of C-Compiler for Qualcomm's VLIW Digital Signal Processor. It included a parser which conforms to the ANSI C standard, all the error checking and generation of compilers intermediate representation. The grammar written in YACC++ style generates an Abstract syntax tree (AST). The ANSI C semantic checks are performed on the AST. AST is then translated to higher level intermediate representation . The parser was written in YACC++ (Compiler resources Inc) which apart from providing object-oriented interface has many additional features over unix-yacc, ~24000 lines of code.

Developed Edif to Spice translator for CAD team, it included implemention of module for dumping spice from data-structures while reusing existing edif parser and design database.

Implemented SpiceLint netlist checker tool to identify the correctness of connectivity and expands all the includes to find any redundancies.

Implemented Spice2Spice technology migration tool, it scaled and modified the spice netlist according to the user specified equations and libraries.

All implementations were done in ‘C++’ using object oriented design methodologies.

Involved in Development & support of Software Tools for ASIC design Flow. The job consists of integrating Third party CAD tools into TI's own design flow. This is to use the best third party and our own tools to give a competitive edge to TI.

Developed a new tool SdfAligner for ASIC design kit, it required performing various operations on the SDF in order to perform custom back annotations of delays. It could read in the design/netlist and various SDF files from different 3rd party tools, aligns them according to TI's ASIC libraries. It also merged the non-output peripheral delays of a sub chip into the parent design SDF. Finally it would generate a single file for back annotations. I modified the yacc generator so that it can generate the object oriented parsers that could be paused and resumed by the applications. This allowed simultaneous processing/searching of multiple files while keeping linear memory and cpu usage. This modified parser is under GPL and has been popularly downloaded from http://members.tripod.com/~ashimg/ooyacc.html . The software was written in C++ and followed object oriented methodology, ~16000 lines of code.

Ported VHDL translator for TI-ASIC to new VHDL parser developed by Compass Inc. The job required traversing the DLS libraries built by the parser and translating it to TI's central design database format

Supported Various TI netlist translators that were used to translate a netlist in one language to a common data model and back to another languages. These tools provided insight to grammar of different hdls and the netlist data structures and disk caching/memory management techniques.