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This paper describes a novel design-flow for securebalanced circuits and a new security metric. Cryptographiccircuit specifications are refined and passed to optimizationand mapping tools for mapping to a library of power-balancedcomponents. Logic optimization tools are then applied to generatesecure synchronous circuits for layout generation. The libraryconsists of novel mixed 1-of-2 and 1-of-4 components based onN-nary logic. This paper presents a technique for evaluating thesecurity of such circuits. A security metric is introduced whichis based on the common selection function that is widely used inDPA attacks. This is used to compare the security level for thedifferent kinds of circuits generated. The paper highlights whichcircuits are more secure and demonstrates a trade-off betweenefficiency and security.