True Televisions have the CRT Tube !!
Welcome to the Obsolete Technology Tellye Web Museum. Here you will see a TV Museum showing many Old Tube Television sets
all with the CRT Tube, B/W ,color, Digital, and 100HZ Scan rate, Tubes technology. This is the opportunity on the WEB to see, one more time, what real technology WAS ! In the mean time watch some crappy lcd picture around shop centers (but don't buy them, or money lost, they're already broken when new) !!!

Richtige Fernseher haben Röhren!

Richtige Fernseher haben Röhren!

In Brief: On this site you will find pictures and information about some of the electronic, electrical and electrotechnical technology relics that the Frank Sharp Private museum has accumulated over the years .

Premise: There are lots of vintage electrical and electronic items that have not survived well or even completely disappeared and forgotten.

Or are not being collected nowadays in proportion to their significance or prevalence in their heyday, this is bad and the main part of the death land. The heavy, ugly sarcophagus; models with few endearing qualities, devices that have some over-riding disadvantage to ownership such as heavy weight,toxicity or inflated value when dismantled, tend to be under-represented by all but the most comprehensive collections and museums. They get relegated to the bottom of the wants list, derided as 'more trouble than they are worth', or just forgotten entirely. As a result, I started to notice gaps in the current representation of the history of electronic and electrical technology to the interested member of the public.

Following this idea around a bit, convinced me that a collection of the peculiar alone could not hope to survive on its own merits, but a museum that gave equal display space to the popular and the unpopular, would bring things to the attention of the average person that he has previously passed by or been shielded from. It's a matter of culture. From this, the Obsolete Technology Tellye Web Museum concept developed and all my other things too. It's an open platform for all electrical Electronic TV technology to have its few, but NOT last, moments of fame in a working, hand-on environment. We'll never own Colossus or Faraday's first transformer, but I can show things that you can't see at the Science Museum, and let you play with things that the Smithsonian can't allow people to touch, because my remit is different.

There was a society once that was the polar opposite of our disposable, junk society. A whole nation was built on the idea of placing quality before quantity in all things. The goal was not “more and newer,” but “better and higher" .This attitude was reflected not only in the manufacturing of material goods, but also in the realms of art and architecture, as well as in the social fabric of everyday life. The goal was for each new cohort of children to stand on a higher level than the preceding cohort: they were to be healthier, stronger, more intelligent, and more vibrant in every way.

The society that prioritized human, social and material quality is a Winner. Truly, it is the high point of all Western civilization. Consequently, its defeat meant the defeat of civilization itself.

Today, the West is headed for the abyss. For the ultimate fate of our disposable society is for that society itself to be disposed of. And this will happen sooner, rather than later.

OLD, but ORIGINAL, Well made, Funny, Not remotely controlled............. and not Made in CHINA.

How to use the site:

- If you landed here via any Search Engine, you will get what you searched for and you can search more using the search this blog feature provided by Google. You can visit more posts scrolling the left blog archive of all posts of the month/year,or you can click on the main photo-page to start from the main page. Doing so it starts from the most recent post to the older post simple clicking on the Older Post button on the bottom of each page after reading , post after post.

You can even visit all posts, time to time, when reaching the bottom end of each page and click on the Older Post button.

- If you arrived here at the main page via bookmark you can visit all the site scrolling the left blog archive of all posts of the month/year pointing were you want , or more simple You can even visit all blog posts, from newer to older, clicking at the end of each bottom page on the Older Post button.So you can see all the blog/site content surfing all pages in it.

- The search this blog feature provided by Google is a real search engine. If you're pointing particular things it will search IT for you; or you can place a brand name in the search query at your choice and visit all results page by page. It's useful since the content of the site is very large.

Note that if you don't find what you searched for, try it after a period of time; the site is a never ending job !

Every CRT Television saved let revive knowledge, thoughts, moments of the past life which will never return again.........

Many contemporary "televisions" (more correctly named as displays) would not have this level of staying power, many would ware out or require major services within just five years or less and of course, there is that perennial bug bear of planned obsolescence where components are deliberately designed to fail and, or manufactured with limited edition specificities..... and without considering........picture......sound........quality........

Controller for Switch Mode Power
Supplies Supporting Low Power
Standby and Power Factor.

The TDA 16846-2 (this name is used in the description for all types) is optimized to
control free running or fixed frequency flyback converters with or without Power Factor
Correction (Current Pump). To provide low power consumption at light loads, this device
reduces the switching frequency in small steps with load, towards an adjustable
minimum (e. g. 20 kHz in standby mode). Additionally, the startup current is very low. To
avoid switching stress on the power devices, the power transistor is always switched on
at minimum voltage. A special circuit is implemented to avoid jitter. The device has several protection functions: VCC over- and undervoltage, mains undervoltage, current
limiting and 2 free usable fault comparators. Regulation can be done by using the
internal error amplifier or an opto coupler feedback (additional input). The output driver
is ideally suited for driving a power MOSFET. Fixed frequency and synchronized
operation are also possible.
The TDA 16846-2 is suited for TV-, VCR- sets, SAT receivers and other sets for
consumer electronics. It also can be used in PC monitors.
The TDA 16847-2 is identical with TDA 16846-2 but has an additional power
measurement output (pin 8) which can be used as a Temporary High Power Circuit.

Functional Description
Start Up Behaviour (Pin 14)
When power is applied to the chip and the voltage V14 at Pin 14 (VCC) is less than the
upper threshold (VON) of the Supply Voltage Comparator (SVC), then the input current
I14 will be less than 100 µA. The chip is not active (off state) and driver output (Pin 13)
and control output (Pin 4) will be actively held low. When V14 exceeds the upper SVC
threshold (VON) the chip starts working and I14 increases. When V14 falls below the lower
SVC threshold (VOFF) the chip starts again from its initial condition. Figure 4 shows the
start-up circuit and Figure 5 shows the voltage V14 during start up. Charging of C14 is
done by resistor R2 of the “Primary Current Simulation” (see later) and the internal diode
D1, so no additional start up resistor is needed. The capacitor C14 delivers the supply
current until the auxiliary winding of the transformer supplies the chip with current
through the external diode D14.
It is recommended to apply a small RF snubber capacitor of e.g. 100 nF parallel to the
electrolytic capacitor at pin 14 as shown in the application circuits in Figures 15, 16 , and
17.
To avoid multiple pulses during start up in fixed frequency mode (danger of transformer
saturation), the IC works in freerunning mode until the pulses at pin 3 (RZI) exceed the
2.5 V threshold (only TDA 16846-2, TDA 16847-2).

Over- and Undervoltage Lockout OV/SVC (Pin 14)
When V14 at Pin 14 exceeds 16.5 V, e. g. due to a fault in the regulation circuit, the Error
Flip Flop ERR is set and the output driver is shut-down. When V14 goes below the lower
SVC threshold, ERR is reset and the driver output (Pin 13) and the soft-start (Pin 4) are
shut down and actively held low.
Primary Voltage Check PVC (Pin 11)
When the voltage V11 at Pin 11 goes below 1 V the Error Flip Flop (ERR) is set. E.g. a
voltage divider from the rectified mains at Pin 11 prevents high input currents at a too low
input voltage.
Free Usable Fault Comparator FC1 (Pin 10)
When the voltage at Pin 10 exceeds 1 V, the Error Flip Flop (ERR) is set. This can be
used e. g. for mains overvoltage shutdown.
Free Usable Fault Comparator FC2 (Pin 6)
When the voltage at Pin 6 exceeds 1.2 V, the Error Flip Flop (ERR) is set. A resistor
between Pin 9 (REF) and ground is necessary to enable this fault comparator.
Voltage dependent Ringing Suppression Time
During start-up and short-circuit operation, the output voltage of the converter is low and
parasitic zero crossings are applied for a longer time at Pin 3. Therefore the Ringing
Suppression Time TC1 (see “Off-Time Circuit OTC (Pin 1)”) is extended with a factor of
2.2 at a low output voltage. The voltage at pin 1 must not fall below the limit V1L.

THOMSON TDA8172 TV VERTICAL DEFLECTION OUTPUT CIRCUIT,

DESCRIPTION
The TDA8172 is a monolithic integrated circuit in
HEPTAWATTTMpackage. It is a high efficiency
power boosterfordirectdriving of verticalwindings
of TV yokes. It is intendedfor use in Color andB &
W television as well as in monitorsand displays.

MOUNTING INSTRUCTIONS
The power dissipated in the circuit must be re-
moved by adding an externalheatsink.
Thanks to the HEPTAWATTTMpackage attaching
the heatsinkis very simple, a screw or a compres-
sion spring (clip) being sufficient.
Between the heatsink and the package it is better
to insert a layer of silicon grease, to optimize the
thermal contact ; no electrical isolation is needed
between the two surfaces, since the tab is con-
nected to Pin 4 which is ground.

THOMSON TDA7265 25 +25W STEREO AMPLIFIER WITH MUTE & ST-BY.

DESCRIPTION
The TDA7265 is class AB dual Audio power am-
plifier assembled in the Multiwatt package, spe-
cially designed for high quality sound application
as Hi-Fi music centers andstereo TV sets.

BRIDGE APPLICATION
Another application suggestion concerns the
BRIDGE configuration, where the two power am-
plifiers are connected as shown by the schematic
diagram of figure.17.
This application shows, however, some operative
limits due to dissipation and current capability of
the output stage. For this reason, we reccomend
to use the TDA7265 in bridge with the supply volt-
age equal/lower than ±16V when the load is 8Ω;
with higher loads (i.e.16Ω), the amplifier can work
correctlyin the whole supplyvoltage range.
The detected characteristics of T.H.D. vs Pout
and FrequencyResponse are shown in fig.18 and
fig.19.
With R1=8Ω, Vs=+/-16V the maximum output
power obtainableis 50Wat T.D.H.=10%.
The quiescent current remains unchanged with
respect to the stereo configuration (~80mA as
typical at Vs=+/-16V).
The last point to take into consideration concerns
the short-circuit protection.As for the stereo appli-
cation, the TDA7265 is fully protected against any
kind of short-circuit ( between Out/Gnd, Out/+Vs
and Out/-Vs).

TDA9817; Single/multistandard VIF/SIF-PLL and FM-PLL/AM demodulators.

GENERAL DESCRIPTION
The TDA9817 is an integrated circuit for single standard
vision IF signal processing and FM demodulation.
The TDA9818 is an integrated circuit for multistandard
vision IF signal processing, sound AM and FM
demodulation.

FUNCTIONAL DESCRIPTION
The integrated circuit comprises the functional blocks as
shown in Fig.1:
• Vision IF amplifier and VIF AGC detector
• Tuner AGC
• Frequency Phase Locked Loop detector (FPLL)
• VCO, Travelling Wave Divider (TWD) and AFC
• Video demodulator and amplifier
• Sound IF amplifier and SIF AGC
• Single reference QSS mixer
• AM demodulator
• FM-PLL demodulator
• Audio Frequency (AF) signal processing
• Internal voltage stabilizer.
Vision IF amplifier and VIF AGC detector
The vision IF amplifier consists of three AC-coupled
differential amplifier stages. Each differential stage
comprises a feedback network controlled by emitter
degeneration.
The AGC detector generates the required VIF gain control
voltage for constant video output by charging/discharging
the AGC capacitor. Therefore for negative video
modulation the sync level and for positive video
modulation the peak white level of the video signal is
detected. In order to reduce the reaction time for positive
modulation, where a very large time constant is needed,
an additional level detector increases the discharging
current of the AGC capacitor (fast mode) in the event of a
decreasing VIF amplitude step. The additional level
information is given by the black-level detector voltage.
Tuner AGC
The AGC capacitor voltage is converted to an internal
IF control signal, and is fed to the tuner AGC to generate
the tuner AGC output current at pin TAGC (open-collector
output). The tuner AGC takeover point can be adjusted at
pin TADJ. This allows to match the tuner to the SAW filter
in order to achieve the optimum IF input level.
Frequency Phase Locked Loop detector (FPLL)
The VIF-amplifier output signal is fed into a frequency
detector and into a phase detector via a limiting amplifier.
During acquisition the frequency detector produces a
DC current proportional to the frequency difference
between the input and the VCO signal. After frequency
lock-in the phase detector produces a DC current
proportional to the phase difference between the VCO and
the input signal. The DC current of either frequency
detector or phase detector is converted into a DC voltage
via the loop filter, which controls the VCO frequency. In the
event of positive modulated signals the phase detector is
gated by composite sync in order to avoid signal distortion
for overmodulated VIF signals.
VCO, Travelling Wave Divider (TWD) and AFC
The VCO operates with a resonance circuit (with L and C
in parallel) at double the picture carrier frequency. The
VCO is controlled by two integrated variable capacitors.
The control voltage required to tune the VCO from its
free-running frequency to actually double the picture
carrier frequency is generated by the frequency-phase
detector (FPLL) and fed via the loop filter to the first
variable capacitor. This control voltage is amplified and
additionally converted into a current which represents the
AFC output signal. At centre frequency the AFC output
current is equal to zero.
For TDA9818: the VCO centre frequency can be
decreased (required for L accent standard) by activating
an additional internal capacitor. This is achieved by using
the L accent switch. In this event the second variable
capacitor can be controlled by a variable resistor at the
L accentswitchforsettingtheVCOcentrefrequencytothe
required L accent value.
The oscillator signal is divided by 2 with a TWD which
generates two differential output signals with a 90 degree
phase difference independent of the frequency.
Video demodulator and amplifier
The video demodulator is realized by a multiplier which is
designed for low distortion and large bandwidth. The
vision IF input signal is multiplied with the ‘in phase’ signal
of the travelling wave divider output. In the demodulator
stage the video signal polarity can be switched in
accordance with the TV standard.
The demodulator output signal is fed via an integrated
low-pass filter for attenuation of the carrier harmonics to
the video amplifier. The video amplifier is realized by an
operational amplifier with internal feedback and high
bandwidth. A low-pass filter is integrated to achieve an
attenuation of the carrier harmonics for B/G and
L standard. The standard dependent level shift in this
stage delivers the same sync level for positive and
negative modulation. The video output signal at pin CVBS
is 1.1 V (p-p) for nominal vision IF modulation, in order to
achieve 1 V (p-p) at sound trap output.

Sound IF amplifier and SIF AGC
The sound IF amplifier consists of two AC-coupled
differential amplifier stages. Each differential stage
comprises a controlled feedback network provided by
emitter degeneration.
The SIF AGC detector is related to the SIF input signal
(average level of AM or FM carrier) and controls the SIF
amplifier to provide a constant SIF signal to the
AM demodulator and single reference QSS mixer. At
L standard (AM sound) the SIF AGC reaction time is set to
‘slow’ for nominal video conditions. But with a decreasing
VIF amplitude step the SIF AGC is set to ‘fast’ mode
controlled by the VIF AGC detector. In FM mode this
reaction time is always ‘fast’.
Single reference QSS mixer
The single reference QSS mixer is realized by a multiplier.
The SIF amplifier output signal is fed to the single
reference QSS mixer and converted to intercarrier
frequency by the regenerated picture carrier (VCO). The
mixer output signal is fed via a high-pass for attenuation of
the video signal components to the output pin QSS. With
this system a high performance hi-fi stereo sound
processing can be achieved.
For a simplified application without a sound IF SAW filter
the single reference QSS mixer can be switched to the
intercarrier mode by connecting pin SIF2 to ground. In this
mode the sound IF passes the vision IF SAW filter and the
composite IF signal is fed to the single reference QSS
mixer. This IF signal is multiplied with the 90 degree TWD
output signal for converting the sound IF to intercarrier
frequency. This composite intercarrier signal is fed to the
output pin QSS, too. By using this quadrature detection,
the low frequency video signals are removed.
AM demodulator
The AM demodulator is realized by a multiplier. The
modulated SIF amplifier output signal is multiplied in
phase with the limited (AM is removed) SIF amplifier
output signal. The demodulator output signal is fed via an
integrated low-pass filter for attenuation of the carrier
harmonics to the AF amplifier.
FM-PLL demodulator
The FM-PLL demodulator consists of a limiter and an
FM-PLL. The limiter provides the amplification and
limitation of the FM sound intercarrier signal. The result is
high sensitivity and AM suppression. The amplifier
consists of 7 stages which are internally AC-coupled in
order to minimize the DC offset.
Furthermore the AF output signal can be muted by
connecting a resistor between the limiter input pin FMin
and ground.
The FM-PLL consists of an integrated relaxation oscillator,
an integrated loop filter and a phase detector. The
oscillator is locked to the FM intercarrier signal, output
from the limiter. As a result of locking, the oscillator
frequency tracks with the modulation of the input signal
and the oscillator control voltage is superimposed by the
AF voltage. The FM-PLL operates as an FM demodulator.
Audio Frequency signal processing
The AF amplifier consists of two parts:
1.
The AF pre-amplifier for FM sound is an operational
amplifier with internal feedback, high gain and high
common mode rejection. The AF voltage from the
PLL demodulator, by principle a small output signal, is
amplified by approximately 33 dB. The low-pass
characteristicoftheamplifierreducestheharmonicsof
the intercarrier signal at the sound output terminal
pin Vde-em at which the de-emphasis network for FM
sound is applied. An additional DC control circuit is
implemented to keep the DC level constant,
independent of process spread.
2.
The AF output amplifier (10 dB) provides the required
output level by a rail-to-rail output stage. This amplifier
makes use of an input selector for switching to AM,
FM de-emphasis or mute state, controlled by the
standard switching voltage and the mute switching
voltage.
Internal voltage stabilizer
The bandgap circuit internally generates a voltage of
approximately 1.25 V, independent of supply voltage and
temperature. A voltage regulator circuit, connected to this
voltage, produces a constant voltage of 3.6 V which is
used as an internal reference voltage.

General Description
The SDA 9402 (PRIMUS) is a new component of the
Micronas MEGAVISION® IC set in a copper CMOS
embedded DRAM technology. The SDA 9402
comprises all main functions of a digital featurebox in
one monolithic IC. The amount of features is limited in
favour of a low-cost solution. But no trade-off has been
made concerning picture quality. It is ideally suited to
work in conjunction with the ’enhanced digital
deflection processor’ SDA 9380. The package is pin-
upward compatible to other medium-range and high-
end devices of the SDA940X family. A 50/60Hz
derivative is also available (SDA9402S).

CVBS Frontend
The CVBS frontend consists of the color-decoding circuit itself, a sync processing circuit
for generation of H/V signals out of the CVBS signal, and the luminance processing. The
main task of the luminance processing is to remove the color carrier by means of a notch
filter. For PAL and SECAM operation a baseband delay line is used for U and V signals.
This can be used as comb filter in NTSC operation (only for chrominance). The RGB
input can either be used as an overlay for the CVBS channel (RGB+FBL) or as a full
master channel (RGB+H/V). The overlay is done by means of a soft-mix and can be used
e.g. for ’SCART’ connector. This block incorporates a matrix (for RGB signals) which is
switched off for YUV (e.g. YPbPr) input signals. A CBS (contrast, brightness, saturation)
control makes the input signal adjustable.
5.1.1
Source select
Figure 5-1 shows the analog frontend. The analog CVBS signal can be fed to the inputs
CVBS1...7 of SDA 9402 (amplitude 0.5...1.5Vpp). One signal is selected via CVBSEL1
and fed to first ADC. A second signal is selected via CVBSEL2 and fed to the other ADC.
CVBS4&5 or CVBS6&7 are intended to use as separate Y/C inputs (YCSEL). After
clamping to the back porch (switchable to sync-tip clamping by CLPSTGY) both signals
are AD-converted with an amplitude resolution of 9 bit. The conversion is done using a
20.25 MHz free-running stable crystal clock. Before this the signals are lowpassed by
antialias filter. Three inputs can be looped back to output CVBSO1-3 (CVBOSEL1,
CVBOSEL2, CVBSELO3). A signal addition is performed to output a CVBS signal even
when separate Y/C signals are used at input. Inputs that are not used are roughly
clamped to fit in the allowed voltage region. For stand-by operation (power-down mode),
A/D and D/A converter are switched off by STANDBY keeping the source-selector
operational.

Clamping
The clamp timing for the analog inputs is generated from its corresponding CVBS signal.
The clamping algorithm works with a split measurement pulse and a clamping pulse. The
measurement pulse is used to detect the clamping error. The clamping pulse is used to
enable current sources for reducing the detected clamping errors. The start and length
of the measurement signal is adjustable independently for both channels (CLMPST1,
CLMPD1, CLMPST2, CLMPD2). The start and length of the clamping signal is
adjustable for both channels independently (CLMPST1S, CLMPD1S, CLMPST2S,
CLMPD2S). Clamping signals for RGB-channel are not split. Clamping for these ADC
are controlled by CLMPST2 and CLMPD2 only. Clamping can be suppressed for some
lines by CLMPLOW and CLMPHIGH to ignore copyprotection information. No external
sync signals are required.

Synchronization
After elimination of the high frequency components of the CVBS signal by a low pass
filter, horizontal and vertical sync pulses are separated. Horizontal sync pulses are
generated by a digital phase locked loop. The time constant can be adjusted between
fast and slow behavior in four steps (PLLTC) to accommodate different input sources
(e.g. VCR). The time-constant can be changed during normal operation without visible
picture degradation.

Additionally weak input signals from a satellite dish (’fish’) become more stable when
SATNR is enabled. Vertical sync pulses are separated by integration of equalizing
pulses. A vertical flywheel mode improves vertical sync separation for weak signals
(VFLYWHL, VFLYWHLMD). Additionally, v-syncs may be gated by VTHRL and VTHRH
to reject invalid v-syncs. When no input signal is connected the device switches to a free-
running mode. The device can be configured to switch-on background color when no or
only a weak signal is applied (NOSIGB). 50 Hz or 60 Hz operation for sync separation
may be forced separately or selected to work automatically (FLNSTRD)

The digital multistandard chroma decoder is able to decode NTSC and PAL signals with
a subcarrier frequency of 3.58MHz and 4.43MHz (PAL B1)/M/N/602), NTSC M/4.4) as
well as SECAM signals with automatic standard detection. Alternatively a standard can
be forced. The demodulation is done with a regenerated color-carrier. For use of non-
standard crystals or factory adjustment, the frequency of the free-running regenerated
subcarrier can be adjusted between +/-270 ppm via SCADJ. For this purpose the crystal
deviation (SCDEV) can be read out via I²C after chroma PLL locking (indicated by
SCOUTEN) and can be stored in ?C ROM for SCADJ. For test purposes, CPLLOF
allows a loop opening of the chroma PLL
For adjustment to the specific operational area an automatic norm detection is
selectable. Available 50 Hz color standards are PAL B, PAL N and SECAM. Available
60 Hz color standards are NTSC M, PAL M, PAL60 and NTSC44. For each line standard,
one or more color standards can be chosen for automatic standard detection. In addition,
a standard can be forced as well. Within each line standard, the standard is detected by
consequently switching from one to another. This standard detection process can be set
to slow or fast behavior (LOCKSP). In slow behavior, 25 fields are used to detect the
standard, whereas 15 fields are used in fast behavior. If unsuccessful within this time
period the system tries to detect another standard. For SECAM detection, a choice
between different recognition levels is possible (SCMIDL, SCMREL) and the evaluated
burst position is shiftable (BGPOS).
Color standard (STDET), line standard (LNSTDRD) and color killer status (CKSTAT)
can be read out.

Chroma filter characteristics
An Automatic Chroma Control (ACC) produces a stable output for input chroma
variations from (approximately) -30 dB to +6 dB compared to nominal burst value. The ACC reference value is programmable for NTSC and PAL independently (NTSCREF,
PALREF) to ensure correct color saturation. With ACCFIX, the ACC is disabled and a
constant value (dependent on NTSCREF and PALREF) is used instead. ACCFRZ holds
the current ACC value. The maximum amplification of the ACC can be limited by
ACCLIM. This results a smooth attenuation of color intensity for weak color carrier. If the
chrominance signal is below an adjustable threshold (CKILL (PAL; NTSC) or CKILLS
(SECAM)) the color is switched off. To prevent on / off switching, a hysteresis is given
by CON or CONS which is the value of switching on the color.
COLON switches on the color under any circumstance. The output of the colordecoder
can be set to UV or CrCb data by CRCB. For NTSC only, the color impression (tint) can
be adjusted by the Hue Control between -88 and 90 in steps of 0.7° (HUE). Low
chrominance values (+/- 1...3 LSB) may be deleted by UV-coring (UVCOR). The Chroma
bandwidth can be adjusted by CHRF. The value of CHRF has no linear dependency on
effective bandwidth. The proper constellations are shown in Figure 5-7. A filter with
asymmetrical characteristic around the color carrier is available (IFCOMP) .

IF prefilter
For SECAM mode, the de-emphasis filter can be adjusted by DEEMPFIR and
DEEMPIIR. The bell filter can be adjusted by BELLFIR and BELLIIR.

Bell filter (baseband): standard (black) and implementation (red)
The delay between Y and C is well aligned and can also be adjusted in steps of 50ns
(YCDEL). No picture shifting occurs when switching between different color standards
(e.g. SECAM -> PAL). A delay-line is implemented for PAL and SECAM signals. It acts
as a simple chrominance comb-filter for NTSC and can be disabled by COMB. This
improves the vertical chroma resolution, but cross-color remains.

Luminance Processing
A luminance notch filter is implemented to reject the chroma information from luminance.
Depending on the color standard, one of three different notch characteristics is chosen
(’PAL’, ’NTSC’, ’SECAM’). For PAL and SECAM standards, five different characteristics
are available. For NTSC standard, four different characteristics are available. They can
be selected by NTCHSEL. Alternatively, no notch should be used for Y/C input
(NOTCHOFF). The filter characteristics can be found in Figure 5-11...Figure 5-14. In
SECAM operation, the notch filter can be fixed to one frequency or toggle between 4.4
and 4.25 MHz depending on the transmitted color (Dr, Db) (SECNTCH). A simple
lowpass-filter can be enabled by LPPOST to further reduce high-frequency noise
component from the CVBS signal.

Filter characteristics for Y/C mode
For applications for which a black offset is not desired, controlling may be done using
LMOFST. The positive or negative offset is added to the Y signal before scaling.

RGB-Frontend
An analog RGB input port for an external RGB or YUV source is available. The incoming
signal is clamped to the back porch by a clamping pulse. As the memory is only able to
store a 4:2:2 picture, the YUV input signal is downconverted to 4:2:2. There are two operation modes available. The first one uses this input as an overlay input (soft mix).
The RGB or YUV signal must then be synchronized to the main CVBS signal. The so
called independent mode uses RGB / YUV including sync or H/V signals. This can be
used, for example, for a DVD player or set-top-box. When using H sync from a non CVBS
input (e.g. separate H-sync) this must be indicated by HINP. The usage of separate V
sync must be set by VINP.

Possible input signals for RGB Frontend
The delay of luminance and fast-blank can be adjusted by YFDEL, and chrominance can
be delay adjusted by UVDEL. If necessary, fast-blank can be adjusted fine by FBLDEL.

Digital Prefiltering
A digital prefiltering can be enabled. This reduces the bandwidth of very steep input
signals, such as a display of characters. A band limitation is required, because the
succeeding deskewing filter performs best below 14 MHz. The filtering is performed in
all four channels and can be disabled by AABYP. For signal conversion to 4:2:2, an
additional chrominance lowpass can be enabled by CHRSF. The deskewing filter can be
disabled by SKEWSEL. This is necessary when using the HOUT50-pin in connection
with a Micronas picture-in-picture device (e.g. SDA938x, SDA948x, SDA958x).
In this application, the RGB input (in1, in2, in3) of the PiP can not be used for other RGB
signals (e.g. ’SCART’ is not possible).

RGB->YUV Matrix
RGB or YUV signals are selected by YUVSEL. The matrix coefficients are set according
to ITU recommendations.

Contrast, Brightness and Saturation Control of Input signal
The YUV signal can be manipulated in order to fit to the main channel. The contrast can
be adjusted between 0 and 1.97 in 64 steps (CONADJ). The brightness is adjustable in
255 steps (BRTADJ). Due to the independent chroma adjustment of U and V (64 steps
each, USAT, VSAT), UV as well as CrCb input signals can both be displayed correctly.

Soft Mix
The soft-mixing is done by means of alpha-mixing. Alpha is derived from the fast blank
input (FBL), which indicates a signal insertion. The value of ? is between ’0’ and ’128’.
’0’ means that only the main signal is fed through to the output. ’128’ means that only the
inserted signal becomes visible.

FBL activity and overflow detection
It is important to know whether the FBL input is used or not. Therefore a detection circuit
gives information via the I2C bus to the microcontroller. The circuit uses the FBL value
as input. If it is greater than a threshold for one or five clock cycles (FBLCONF), the I²C
register FBLACTIVE is set. This register is reset when it is read by the microcontroller.
PFBL, PG, PR, PB indicate an overflow of the corresponding ADC (upper limit:
ADC=255) exceeding 5 clock cycles duration. These signals are also set by overflow and
reset by I²C reading only.

Horizontal Prescaler (sample-rate-converter)
The main application is the conversion of the data coming from the 40.5/20.25MHz pixel
clock domain down to the number of pixels stored in the memory (factor 2/3). Generally
the number of incoming pixels can be decimated by a factor between 1 and 64 in a
granularity of 2 output pixels. The horizontal scaler reduces the number of incoming
pixels by subsampling. To prevent the introduction of alias distortion low pass filters are
used for luminance and chrominance processing (Figure 5-23). In case of ITU656 input,
the lowpass filter must be disabled by HAAPRESC.
The horizontal prescaler consists of two main subsampling stages. The first stage is a
scaler for rational decimation factors in a range of 1 to 2, controlled by HSCPRESC. The
second stage is a MTA (moving target average) filter for integer decimation factors
(1,2,3,4...32), controlled by HDCPRESC. Due to its architecture the MTA filter
automatically adapts its low pass filter characteristic to the used subsampling factor.

Noise Reduction
The Figure 5-24 shows a block diagram of the motion adaptive temporal noise reduction
(first order IIR filter). The structure of the temporal motion adaptive noise reduction is the
same for luminance as for chrominance signal. Noise reduction is enabled by NRON.

Temporal noise reduction
The equation below describes the behavior of the temporal adaptive noise reduction
filter. The same equation is valid for the chrominance signal. Depending on the motion
in the input signal, the K-factor Ky (Kuv) is adjustable between 0 (no motion) and 15
(motion) by the motion detector. The K-factor for the chrominance filter can be either Ky
(output of the luminance motion detector, TNRSEL=0) or Kuv (output of the chrominance
motion detector, TNRSEL=1). The delay of the feedback path is a field delay.

The output of the motion detector is weighted TNRCLC and TNRCLY. The output is
mapped to the values Ky and Kc by look-up-tables (LUT Y and LUT C). The input value
range is separated into 8 segments, where segment 0 covers the range 0...3, segment
1 covers the range 4...7 etc. and segment 7 covers the range 48...63 of motion value.

Noise Measurement
The noise measurement algorithm can be used to change the parameters of the
temporal noise reduction processing depending on the actual noise level of the input
signal. This is done by the TV- microcontroller which reads the noise level (NOISEME),
and sends different parameter sets to the temporal noise reduction registers of the SDA
9402 depending on this value (0=no noise, 30=strong noise). Value 31 indicates an
overflow status which means that the measurement failed. The line taken for noise
measurement is selected by NMLINE. When NOISEME contains updated data which
was not read so far, NMSTATUS is set. NMSTATUS is reset when read.

Horizontal Postscaler
After field memory, the display processing is performed using a different clock. In this
way a decoupling of input and output clocks is achieved.
The conversion to the display clock is done by an interpolation filter. This can be used
for horizontal expansion in the range of 1...4 in steps of 2 pixels (HSCPOSC). Due to
increased clock frequency in the backend part (36 MHz instead of 27MHz), the horizontal
expansion factors result as 0.75 ... 3. This ensures that the factor 0.75 gives no loss of
resolution. This is used to show a 4:3 picture on a 16:9 tube.

Because of the nonlinear characteristic and integer number of pixel, sometimes different
HSCPOSC values result in the same decimation factors.

Panorama Mode
The picture can be geometrically distorted in horizontal direction for an improved
impression in the case of expansions of 4:3 pictures to a 16:9 ratio tube. It is enabled by
HPANON. The idea behind this panorama mode is to keep the middle part of the picture
in a 4:3 ratio and to stretch the left and the right to fill the entire width of the 16:9 screen.
For the adjustment of the expansion process, the picture is divided into 5 segments. For
each of these segments the increment value for the expansion factor can be defined
separately.

Visualization of panorama segments
Each end of a segment can be defined individually in a granularity of two output pixels.
For every segment an increment value can be defined (HINC0...HINC4) which indicates
the amount of decimation/expansion. One LSB is equivalent to an offset of 0.125 to
HSCPRESC per double pixel. This means that with HINC, HSCPRESC is altered in the
range from -32...31.875 per double pixel.

Peaking
The luminance peaking filter improves the overall frequency response of the luminance
channel. It consists of two filters working in parallel. They have high pass (HP) and band
pass (BP) characteristics. Their gain factors are programmable separately (BCOF,
HCOF). Values greater than 4 peak the signal, whereas values less than 4 attenuate the
signal. The high pass and the band pass filters are equipped with a common coring
algorithm. It is optimized to achieve a smooth display of grey scales, not to improve the
signal-to-noise ratio. Therefore no artifacts are produced. Coring can be switched off
(YCOR). The Figure 5-33 shows the block diagram of the peaking block

Peaking filter: Bandpass and Highpass filter
The peaking filter clock frequency is CLKB36 (36 MHz). The maximum signal frequency
of the picture stored in the memory is 6.75 MHz. Due to a peaking after postscaler, the
frequency range of the peaking filter varies with the expansion factor of the postscaler.

Digital color transition improvement (DCTI)
A new digital algorithm is implemented to improve horizontal transitions of the
chrominance signals resulting in a better picture sharpness. A correction signal
proportional to the slope of the detected horizontal transition of the input signal is added
to the original input signal. Different correction signals are selected according to the
bandwidth of the input signal. The amplitude of the correction signal is adjustable by the
I²C bus parameter ASCENTCTI.
The exact position of a color transition is calculated by detecting the corresponding zero
transition of the second derivative of both chrominance signals. Low pass filtering is
performed to avoid noise sensitivity. The I²C bus parameter THRESHC modifies the
sensitivity of the DCTI circuit. High values of THRESHC result in an improvement only
of significant color transitions. Small color variations remain unchanged.
To eliminate “wrong color” transitions, which are caused by over- and undershoots at the
chroma transition, the sharpened chroma signals are automatically limited to a proper
value.

Coarse and fine delay
Before digital-to-analog conversion an adjustment of the phase of the luminance is
performed. A coarse delay from -8 to +7 in steps of 1 pixel CLKB36 (~28 ns) are possible
(COARSEDEL). FINEDEL shifts the luminance one CLKB72 (~14 ns) pixel. This can be
used to compensate delays, when Y and UV are externally processed differently (e.g.
lowpass filtered).

Oversampling and DAC
After conversion into 8:8:8 format (CLKB72=72MHz), three 9-bit digital-to-analog
converters are used for analog YUV output. This twofold-oversampling generates 1920
active pixels per line (when using recommended settings) and simplifies the external
postfiltering. Output voltage is determined by PKLY, PKLU and PKLV in a range of 0.4
...1.9 V (fullscale).

DAC output signals
8 bits of the luminance D/A converter are used for the entire signal. The 9th bit is used
for over- and undershoots caused by the peaking to prevent or reduce clipping artifacts.
As the CTI block seldomly produces such overshoots, a full-scale operation can be
activated by CHROMAMP.

HOUT Generator
The HOUT generator has two operation modes, which can be selected by the parameter
HOUTFR. The HOUT signal is active high for 64 clock cycles (CLKB36). In the
freerunning-mode the HOUT signal is generated depending on the PPLOP parameter.
In the locked-mode the HOUT signal is locked on the incoming H-Sync signal derived
from CVBS. The polarity of the HOUT signal is programmable by the parameter
HOUTPOL.

VOUT Generator
The VOUT generator has two operation modes, which can be selected by the parameter
VOUTFR. In the freerunning-mode (VOUTFR=1) the VOUT signal is generated
depending on the LPFOP parameter.
In the locked-mode the VOUT signal is synchronized by the incoming V-Sync signal
derived from CVBS, delayed by some lines (OPDEL). During one incoming V-Sync
signal, two VOUT pulses have to be generated. The polarity of the VOUT signal is
programmable by the parameter VOUTPOL. The VOUT signal is active high for two
output lines.

Background Generator
This generator is able to realize an automatic closing and opening of the displayed
picture. This means that with every picture the displayed colored background, defined by
UBORDER, VBORDER and YBORDER will get bigger or smaller. The original picture
data will be replaced by the background values and vice versa. There is also the
possibility to realize a fixed border via the I²C bus (BORDPOSH and BORDPOSV). 4096
different colors are available.
BORDPOSH and BORDPOSV also influence the window generation. This means the
automatic opening and closing of the picture will start or end at the position which is
defined with these values. The border is calculated with the following formula: The
horizontal border on the left side of the TV screen is 2*BORDPOSH and 2*BORDPOSH
on the right side of the TV screen. This means, that 4*BORDPOSH pixels are overwritten
with border values. The same applies to the vertical direction. 4*BORDPOSV lines in
total are overwritten with background values. BORDERV decides whether upper or
lower or both borders are displayed. BORDERH decides whether left or right or both
borders are displayed.

Digital 656 input
The IC decodes a digital 8bit@27MHz data stream according to ITU.BT656 standard.
The input is selected by EN656.

Clock Concept
A single 20.25 MHz crystal at fundamental mode is used as clock reference. All other
clocks are derived from this source. The CVBS frontend works with 20.25 MHz, the RGB
frontend works with 40.5 MHz, the oversampling DACs use 72.0 MHz and the memory
and all parts behind the memory are clocked with 36 MHz.
Three different clock concepts are supported. The difference is the behavior in clocking
the memory output. The frontend part of the SDA 9402 uses a free-running but crystal-
stable clock (CLKF). After deskewing, an orthogonal picture is written into the memory.
The read out is done using the (CLKB) clock.
The horizontal sync-signal output (HOUT) is derived from a counter running with CLKB.
The VOUT is directly derived from the input vertical signal, which is generated by the
sync-separation block. This ’H-freerunning-V-locked mode’ is only possible together with
a DC coupled deflection controller.
In ’H-and-V-locked mode’ CLKB is line-locked to the incoming signal. The freerunning
YUV picture data and the internal H signal are converted to the line-locked domain. Now
HOUT and the sync signal in the 1fH domain are directly coupled.
In case of ’H-and-V-freerunning mode’ the HOUT and VOUT signals are derived from
counters running with CLKB. There is no connection to the incoming signal. This mode
can be used for stable pictures when no signal is applied (e.g. channel search with OSD
insertion).

Clock system
A clock output of 27MHz (50 Hz version:13.5 MHz) is possible (pin 27:clkout). This clock
is 3/4 of CLKB36. HOUT and VOUT are in line with this sampling clock. The clock output
can be disabled by CLKOUTON. Additionally a 20.25 MHz clock can be output to pin 74
(656hin/clkf20) to supply other ICs (e.g. PiP) with the same clock (CLKF2PAD). When
enabled, 656-input with separate H/V-sync is not possible. For 656-output operation,
CLKB36 is given to pin 9 (656clk).

Linelocked clock generation
Linelocked horizontal sync pulses are generated by a digital phase locked loop. The time
constant can be adjusted between fast and slow behavior in eight steps (TICO) to
accommodate different input sources (e.g. VCR). Noisy input signals become more
stable when a noise-reduction is enabled (HSWIN). The PLL control can be frozen up to
15 lines before v-sync (FION) for a duration up to 15 lines (FILE). This may be used to
reduce disturbances by h-phase errors which are produced by VCR’s. Because of the
delay between read and write pointer of field memory (Figure 5-31), the incoming 50Hz
v-sync lies in the active picture area.
The output frequency for the 100/120 Hz version dependent on IICINCR is
The value is internally divided by two for the 50/60 Hz version.

I²C bus clock domains
The registers themselves are grouped in an I²C bus interface block, one in each domain.
The transmitted data is received by the I²C bus kernel. The I²C bus kernel itself is located
in the CP domain. This means that the working frequency is 20.25 MHz. The data is
transmitted to the I²C bus interface blocks via an internal serial bus.
For the write process, the I²C bus master has to write a ’don’t care’ byte to the
subaddress FFh (store command) to make the register values available to the four I²C
bus interface blocks (except for the not-take-over registers).
In order to have a defined time step for the several blocks in the different domains, where the data will be available from the I²C bus interface blocks, the data are made valid with internal V-sync related
signals (rising edge), depending on the different clock domains. The subaddresses,
where the data are made valid with the V-sync signal of the 20.25 MHz domain are
indicated in the overview of the subaddresses with „V20“, the others are called “V40”,
“V36F” and “V36B”, respectively. The I²C parameter V20STAT, V40STAT and
V36BSTAT reflect the state of the register values. If these bits are read as ’1’, then the
store command was sent, but the data is not made available yet. If these bits are ’0’ then
the data was made valid and a new write or read cycle can start. The bits V20STAT,
V40STAT and V36BSTAT may be checked before writing or reading new data,
otherwise data can be lost by overwriting. No V36FSTAT register exist. To make the
register values available to the four I²C bus interface immediately after sending, the I²C
bus master has to write a ’don’t care’ byte to the subaddress FEh (store command).

I²C bus clock domains
For the read process, the I²C bus master must not send a store command. In order to
have a defined time step for the I²C bus interface blocks in the different domains, where
the data will be available from the different blocks, the data is made valid with the same
V-Sync related signals mentioned above for the write process. The SDA 9402
distinguishes between two different types of read-registers. The behavior of the “normal”
read registers does not differ from the behavior of the write registers.Only the direction
of the data flow is opposite. The “rs typ” read registers behave differently. They can be
only set (means value 1) by the internal blocks using the rising edge of a corresponding
signal. After reading by the I²C bus master, the registers will be automatically reset
(means value 0) by the I²C bus kernel/interface.

For example the register NMSTATUSbelongs to the “rs typ” read registers. NMSTATUS signalizes a new value for NOISEME. So if NMSTATUS is read as ’0’ the current noise measurement has not been updated.
If the NMSTATUS is read as ’1’ a new noise measurement value can be read. All other
“rs typ” read registers work in the same way. The “rs typ” read registers will be marked
in the overview with the short cut “rstyp” or will have the additional hint “Note: reset
automatically when read/write” in the detailed I²C bus command description.
By default all registers are made valid by the internal V-Sync related signals and, in
addition, a store command has to be sent for write registers. The registers, which should
also be made available immediately as for writing and reading, are marked with the short
cut NTO (No take over mechanism).
Registers which need a hand-shake mechanism between the I²C bus interface and the
different blocks are marked with the shortcut HS (Hand shake mechanism). This means
that all bits of the registers are used when the last register is written. After PPLIP9-2 is
written, PPLIP1-0 must be written to allow these bits to have effect.
The registers for the write parameter STOPMODE are directly connected to the read
registers of the parameter SMMIRROR. So it is possible to check the I²C bus protocol by
writing and reading to the register STOPMODE and SMMIRROR, respectively.
The transmitted data is internally stored in registers. Writing to or reading from a non -
existant register is permitted and does not generate a fault by the IC.
After switching on the IC, all bits of the SDA 9402 are set to defined states, (refer to
Table 6- 2). POR is set after reset to pin 24. It stays ’1’, until it is cancled via software
PORCNCL. This can be used to decide during TV operation, whether to program all
registers (e.g. after power failure reset) or only altered ones (normal TV operation).

SDA 9380 EDDC Enhanced Deflection Controller and RGB Processor,

General description
The SDA 9380 is a highly integrated deflection controller and RGB video processor for CTV receiv-
ers with 15 to 19kHz or 31 to 38kHz line frequencies. The deflection component controls among oth-
ers an horizontal driver circuit for a flyback line output stage, a DC coupled vertical saw-tooth output
stage and an East-West raster correction circuit. All adjustable output parameters are I²C-Bus con-
trolled. Inputs are HSYNC and VSYNC. The HSYNC signal is the reference for the internal clock
system which includes the=χΝ=and χΟ=control loops.
The RGB processor has two YUV/RGB inputs and one RGB input. One YUV/RGB input and the
RGB input are for SVGA and text/OSD with fast blanking. The RGB output stage has two control
loops for cut off and white level with halt capability in vertical shrink modes. An overall Y output and
an adjustable delay of the RGB outputs related to this signal are suitable for a scan velocity modula-
tion circuit.
The supply voltages of the IC are 3.3V and 8V. It is mounted in a P-MQFP package with 64 pins.

System description
5.1
Functional description
5.1.1 Deflection controller
The main input signals are HSYNC with a frequency range of about 31 to 38kHz and VSYNC with
vertical frequencies of 50 to 120 Hz. When connecting pin FH1_2 with Low level a line frequency of
15 to 19kHz is suitable.
For displaying computer signals horizontal frequencies up to 38 kHz can be processed.
In the selectable Monitor mode the adaptation to the input frequency in the range of 31.25 to 38kHz
is done automatically. Two output pins (H35K and H38K) for controlling e.g. the supply voltage of the
line output stage indicate the frequency of HSYNC. When the H-frequency is increasing, these out-
puts are stable until the frequency of HSYNC appears on the output HD (see 11.1). In case of
decreasing H-frequency they are changed immediately to flag the new detected frequency but
change of the PLL frequency will be not allowed until the supply voltage of the H-output stage (B+)
is decreased. Pin HSAFE is used to watch B+.
The output signals control the horizontal as well as the vertical deflection stages and the East-West
raster correction circuit.
The H-output signal HD (open drain output) compensates the delays of the line output stage and its
phase can be modulated vertical frequent to remove horizontal distortions of vertical raster lines (V-
Bow, V-Angle). Time reference is the middle of the front and back edge of the line flyback pulse. A
positive HD pulse switches off the line output transistor. Maximal H-shift is about 2.25 µsec for
fH=31kHz.
Picture tubes with 4:3 or 16:9 aspect ratio can be used by adapting the raster to the aspect ratio of
the source signal.
The V-output saw-tooth signals VD- and VD+ controls a DC coupled output stage and can be dis-
abled. Suitable blanking signals are delivered by the IC.
The East-West output signal E/W is a vertical frequent parabola of 6th order, enabling an extreme
corner correction for super flat tubes. The common corner correction realised with coefficients of
fourth order, is separately adjustable for the upper and lower part of the screen.
The pulse width modulated horizontal frequent output signal PWM has two options. A vertical fre-
quent parabolic function or a constant pulse width in each line, selectable by I²C, is available. After
external integration the parabola may be used for vertical dynamic focusing rsp. the DC voltage for
adjustment of H-offset or rotation.
The output D/A delivers a variable DC signal and an I2C Bus controlled digital output is available for
general purpose.
The picture width and picture height compensation (PW/PH Comp) processes the beam current
dependent input signal IBEAM with effect to the outputs E/W and VD to keep width and height con-
stant and independent of brightness.
The alignment parameter AFC EHT Compensation enables to adjust the influence of the input sig-
nal IBEAM on the horizontal phase.
The selectable start up circuit controls the energy supply of the H-output stage during the receiver's
run up time by smooth decreasing the line output transistors switching frequency down to the nor-
mal operating value (softstart). HD starts with about 1.7 times the line frequency and converges within 85ms to its final value. The high time is kept constant. The normal operating pulse ratio H/L is
either 45/55 or 40/60 (selectable by I²C). A watch dog function limits an increasing of the HD period
to max. +10%.
The implemented Black Switch-Off behaviour is defined by two I2C bits (BSO1, BSO0). When
enabled the signal at BSOIN (e.g. the supply voltage of the line output stage) is watched. If its level
does not come up to a defined threshold Black Swich-Off is started (see 11.2). At first the RGB out-
puts are switched to continuous blanking immediately and the vertical output signals are changed to
about 115..120% overscan. After a delay of 42 lines the picture tube capacitance is discharged with
a current of some mA. From now the vertical overscan rate is calculated depending on the actual
voltage at BSOIN to get the desired deflection angle. Three relations are selectable by I2C. After the
voltage at BSOIN is dropped down to about 20% of its initial value the output HD and the overscan
calculation may stop.
The protection circuit watches an EHT reference and the saw-tooth of the vertical output stage. If
the EHT succeeds a defined threshold or if the V-deflection fails (refer to 11.5) the related bit is set in
the status byte and the output PROTON goes High. The output HD is deactivated (H-level) immedi-
ately independent of the selected Black Switch-Off function.
HPROT:
input
Vi < V2
continuous blanking
Vi > V1
HD disabled
V2 ≤=Vi < V1
operating range
VPROT:
vertical saw-tooth voltage
Vi < V1 in first half of V-period
or Vi > V2 in second half : HD disabled
The pin SCP delivers the composite blanking signal SCP. It contains burst (Vb), H-blanking HBL
(VHBL) and selectable V-blanking (control bit SSC). The phase and width of the H-blanking period
can be varied by I2C-Bus. For the timing following settings are possible :
BD = 1
: TBL = 0
BD = 0, BSE = 0 (default value)
: THBL = tf (H-flyback time)
BD = 0, BSE = 1(alignment range)
: THBL = (4 * H_blanking-time + 1) / CLL
: TDBL = (H_shift + 4 * H_blanking_phase
- 2*H_blanking_time + 45) / CLL
SSC = 0
: TBL = TVBL during V-blanking period
SSC = 1
: TBL is always THBL

RGB processing
To provide an accurate biasing of the picture tube the offsets and gains of the RGB output stages
are continuously adjusted by a cut off and white level control loop. Leakage, cut off and white current
are measured each frame during vertical flyback at the DCI input. The position of the measurement
lines is adjustable by IIC bus (see page 31). The reference currents for the cut off and white levels
are adjusted by IIC bus with a 6 bit parameter for each output and a common 3 bit gain parameter.
Because the video amplifiers are part of the control loops, the overall gain and offset is no more
adjustable in this stage. For proper dimensioning of the video amplifiers there is an IIC status bit
(CLOW), which is 0 when all offset and gain actuators of the RGB outputs are within 50% of its full
range. The control loops can be switched to halt mode to switch off the measurement lines in verti-
cal shrink mode. When the TV screen is switched on brightness and contrast ramp up in a soft start
mode as soon as the cut off control loop is locked.
There are three circuits implemented for beam current limiting:
-First there is a circuit for accurate average beam current limiting. The beam current is measured at
the Ibeam input and limited by reducing first contrast and, after half contrast is reached, brightness
too. All parameters (limit value, gain, up time constant and down time constant) are adjustable by IIC
bus.
-Second a peak drive limiter circuit is implemented for the higher frequency content of the video sig-
nal. It reduces contrast when a limit value is exceeded by the R, G or B video signals. Also all
parameters (limit value, up time constant and down time constant) are adjustable by IIC bus.
-Third there is a soft clipper for the very high frequency content of the video signal. It limits the R, G
or B video signals according to the diagram at 11.7. Limit value and slope are adjustable by IIC bus.
The TV screen can be switched to blue by IIC bus when no video signal is available.
When the blue stretch function is activated by IIC bus, the gain of the red and green output is
reduced by 17% for amplitudes more than 80% of the nominal amplitude. This shifts white towards
light blue.
A black stretch function (switchable by IIC bus) stretches video signals with a black level which is
higher than the clamping level towards black. Therefore the peak dark value of the video signal is
stored. The height of the peak dark value determines the amount of stretch (diagram at 11.6). The
screen area in which the peak dark detector is enabled is programmable by IIC bus. So it is possible
to screen black borders of the picture (e.g. letter box format) which otherwise prevent the desired
function of black stretch.
An overall luminance output is provided for supplying a circuit for scan velocity modulation. The
delay of the RGB outputs to the luminance output is adjustable by IIC bus. So a proper alignment of
the video signals and the current in the SVM coil is possible.

Circuit description
The HSYNC is reference for a numeric PLL. This PLL generates a clock which is phase locked to
the incoming horizontal sync pulse and exactly 864 times faster than the horizontal frequency. The
polarity of the external horizontal sync pulses may be positive (see figure below) or negative. In
case of negative polarity the incoming HSYNC signal is automatically inverted for an easier applica-
tion in VGA or SVGA mode.

Incoming signal HSYNC (internal clock)
Pulse width tw for I2C-bus Bit ’HSWMI’=0:
1.5 µs ... 4.5µs (High or Low level)
FH1_2 = High
3.0 µs ... 9.0µs (High or Low level)
FH1_2 = Low
Pulse width tw for I2C-bus Bit ’HSWMI’=1:
0.8 µs ... 4.5µs (High or Low level)
FH1_2 = High
1.7 µs ... 9.0µs (High or Low level)
FH1_2 = Low
(The specified pulse width depends on the I²C-bus bits INCR4...INCR0 rsp. PLL clock frequency.
The above values are valid for INCR = 6. For higher INCR values the allowed pulse width is
decreasing proportional to the increasing PLL clock frequency.)
The described input signal is first applied to an A/D converter. Conversion takes place with 7 bits
and a nominal frequency of 27 MHz. The digital PLL uses a low pass filter to obtaine defined slopes
for further measurements (PAL/NTSC applications). In addition the actual high and low level of the
signal as well as a threshold value is evaluated and used to calculate the phase error between inter-
nal clock and external horizontal sync pulse. By means of digital PI filtering an increment is gained
from this. The PI filter can be set by the I2C-bus VCR bit so that the lock-in behaviour of the PLL is
optimal in relation to either the TV or VCR mode. Moreover it is possible to adapt the nominal fre-
quency by means of 5 I2C-bus bits (INCR4..INCR0) to different horizontal frequencies. An additional
bus bit GENMOD offers the possibility to use the PLL as a frequency generator which frequency is
controlled by the INCR bits.

Once an increment has been obtained, either from the PI-filter or the I2C-bus, it can be used to
operate the Digital Timing Oscillator. The DTO generates a saw-tooth with a frequency that is pro-
portional to the increment. The saw-tooth is converted into a sinusoidal clock signal by means of sin
ROM’s and D/A converters and applied to an analog PLL which multiplies the frequency by 4 (for
detailed explanation see pinning and I2C-bus description) and minimizes residual jitter. In this man-
ner the required line locked clock is provided to operate the other functional parts of the circuit. If no
HSYNC is applied to pin 18 the system holds its momentary frequency for 2040 lines and following
resets the PLL to its nominal frequency. The status bit CON indicates the lock state of the PLL.
The system also provides a stable HS-pulse for internal use. The phase between this internal pulse
and the external HSYNC is adjustable via I2C bus bits HPHASE. It can be shifted over the range of
one TV line.
An external clock (CLKI) can be provided by pin selection (CLEXT = H) or I²C control (SCLIIC = H,
CLEXTIIC = H). This is recommended when using the SDA 9380 with a scan rate conversion sys-
tem. The clock frequency has to be 864 · fHSYNC. The external clock mode can not be used with
18.75, 33.75kHz, 35kHz and 38kHz line frequency. Therefore switching to external clock mode is
only possible when INCR = 6, but always allowed during operating without any danger for the H-out-
put stage.
The input signal at VSYNC is the vertical time reference. It has to pass a window avoiding too short
or long V-periods in the case of distorted or missing VSYNC pulses. The window allows a VSYNC
pulse only after a minimum number of lines from its predecessor and sets an artificial one after a
maximum number of lines. The window size is programmable by I2C-bus.
Values which influence shape and amplitude of the output signals are transmitted as reduced binary
values to the SDA 9380 via I²C bus. A CPU which is designed for speed reasons in a pipe line struc-
ture calculates in consideration of feedback signals (e.g. IBEAM) values which exactly represent the
output signals. These values control after D/A conversion the external deflection and raster correc-
tion circuits.
The CPU firmware is stored in an internal ROM.

Explanation of some control items
Vertical aspect,
Two special control items are implemented for the user to adjust the
Vertical scroll:
vertical height (control item: Vertical aspect) and the vertical position
(Vertical scroll). These items may be stored for every display mode to
get an individual height and position if desired. Changing these para-
meters automatically influences the outputs VD+, VD-, E/W, HD in such
a way that absolutely no raster distortion happens. There is no need
for the user to re-adjust any geometry parameter.
The difference of the function of Vertical size and Vertical aspect is
the following: Varying Vertical size causes a linear stretching of the
saw-tooth to eliminate the tolerance of linear components (e.g. feed-
back resistor). But adjusting Vertical aspect takes into consideration
that more or less picture height needs very more or less S-correction
(no linear relation). Therefore Vertical aspect should be used for chang-
ing the aspect ratio (e.g. 16:9 source on 4:3 CRT) or if an individual
picture height is desired for the various PC graphic standards. Vertical
aspect = -128(minimum value) results in a vertical reduction to 37.5%.
Vertical size,
The purpose of these control parameters is the alignment in the factory
Vertical shift:
and service to adapt the output signals VD+, VD- to the picture tube and
to eliminate tolerances of the hardware and deflection yoke. Only one
set of these parameters is required for all display modes.
Vertical linearity,
Changing the vertical linearity and S-correction has no influence on the
Vertical S-correction: E/W-geometry. That means, straight vertical lines remain straight. The
output signals E/W and HD are automatically changed so no re-adjust-
ment of the related control items is needed. This feature saves time for
adjustment of the so called ’smart’ mode (4:3 source on 16:9 CRT)
Guard band:
This control item is useful for optimizing self adaptation. Video signals
with different number of lines in consecutive fields (e.g. VCR search
mode) must not start the procedure of self adaptation. But switching
between different TV standards has to change the slope of the vertical
saw-tooth getting always the same amplitude (self adaptation). To avoid
problems with flicker free TV systems which have alternating number of
lines per field an average value of four consecutive fields is calculated. If
the deviation of these average values (e.g. PAL : 312.5 lines or 625 half
lines) is less or equals Guard band, no adaptation takes place. When it
exceeds Guard band, the vertical slope will be changed.
Vertical EHT comp.:
This item controls the influence of the beam current dependent input
signal IBEAM on the outputs VD+ and VD-

M2 is a 16-bit controller based on Infineon’s C16x core with embedded teletext and
graphic controller functions. M2 can be used for a wide range of TV and OSD
applications.

Overview
M2 is designed to provide absolute top performance for a wide spectrum of teletext and
graphic applications in standard and high end TV-sets and VCRs. M2 contains a data
caption unit, a display unit and a high performance Infineon C16x based microcontroller
(so that M2 becomes a one chip TV-controller) an up to level 3.5 teletext decoder and
display processor with enhanced graphic accelerator capabilities. It is not only optimized
for teletext usage but also, due to its extremely efficient architecture, can be used as a
universal graphic engine.
M2 is able to support a wide range of standards like PAL, NTSC or applications like
Teletext, VPS, WSS, Chinatext, Closed Caption and EPG (Electronic Program Guide).
With the support of a huge number of variable character sets and graphic capabilities a
wide range of OSD applications are also open for M2.
A new flexible data caption system enables M2 to slice most data, making the IC an
universal data decoder. The digital slicer concept contains measurement circuitries that
help identify bad signal conditions and therefore support the automatic compensation of
the most common signal disturbances. M2’s enhanced data caption control logic allows
individual programming, which means that every line can carry an individual service to
be sliced and stored in the memory.
The display generation of M2 is based on frame buffer technology. A frame buffer
concept displays information which is individually stored for each pixel, allowing greater
flexibility with screen menus. Proportional fonts, asian characters and even HTML
browsers are just some examples of applications that can now be supported.
Thus, with the M2, the process of generation and display of on-screen graphics is split
up into two independent tasks. The generation of the image in the frame buffer is
supported by a hardware graphics accelerator which frees the CPU from power intensive
address calculations. The graphics accelerator ‘prints’ the characters, at the desired
‘screen’ position, into the frame buffer memory based on a display list provided by the
software.
The second part of the display generator (the screen refresh unit) then reads the frame
buffer according to the programmed display mode and screen refresh rate and converts
the pixel information into an analog RGB signal.
Furthermore, M2 has implemented an RGB-DAC for a maximum color resolution of
state-of-the-art up to 65536 colors, so that the complete graphic functionality is
implemented as a system on chip. The screen resolution is programmable up to SVGA,
to cover today’s and tomorrow’s applications, only limited by the available memory
(64 Mbit) and the maximum pixel clock frequency (50 MHz).
The memory architecture is based on the concept of a unified memory - placing program
code, variables, application data, bitmaps and data captured from the analog TV signal’s
vertical blanking interval (VBI) in the same physical memory. M2’s external bus interface supports SDRAMs as well as ROMs or FLASH ROMs. The organization of the memory
is linear, so that it is easy to program the chip for graphic purposes.
The SW development environment “MATE” is available to simplify and speed up the
development of the software and displayed information. MATE stands for: M2 Advanced
Tool Environment. Using MATE, two primary goals are achieved: shorter Time-to-Market
and improved SW qualitiy. In detail:

Micronas
The architecture of M2 comprises of a 16-bit microcontroller which is derived from the
well known Infineon Technologies C16x controller family. Due to the core philosophy of
M2, the architecture of the CPU core is the same as described in other Infineon
Technologies C16x derivatives.
The CPU, with its peripherals, can be used on one hand to perform all TV controlling
tasks, and on the other hand to process the data, sliced by the slicer, and the acquisition
unit according to the TTX standard. Furthermore it is used to generate an “instruction list”
for the graphic accelerator which supports the CPU by generating the display.
M2 has integrated two digital slicers for two independent CVBS signals. One slicer is
used to capture the data (e.g. Teletext or EPG) from the main channel, the other slicer
can be used to slice the WSS information from a different channel, which is helpful e.g.
to support PIP applications in 16:9 TVs. Both slicers separate the data from the analog
signal and perform the bit synchronization and framing code selection before the data is
stored in a programmable VBI buffer in the external RAM. Capturing and storing the raw
data in the RAM does not need any CPU power.
M2’s display concept has improved in comparison to the common known state of the art
Teletext-ICs. The display concept is based on a pixel orientated attribute definition
instead of the former character orientated attribute definition.
For the processing of this new pixel based attribute definition the display generator
architecture is divided in two subblocks: the graphic accelerator (GA) and the screen
refresh unit (SRU).
The graphic accelerator is used to modify the frame buffer. From an abstract point of
view, the graphic accelerator is a DMA which is optimized for OSD functionality, so e.g.
bitmaps can be copied to the frame buffer. The graphic accelerator is used to draw
rectangles, parallelograms, horizontal, vertical and diagonal lines. The user does not
need to access the graphic accelerator directly, thanks to an easy to handle SW-GDI
function which is available with the M2 hardware.
The DMA functionality of the display generator (DG) supports the pixel transfer between
any address of entire external memory. The teletext and graphic capabilities can be used
simultaneously, so that M2 can combine teletext information with e.g. background
images and advanced high resolution OSD graphics.
M2 uses the frame buffer located in external memory so every bitmap can be placed at
any location on the screen. The contents of the frame buffer does not have to be set up
in real time. The duration of the set up of the screen depends on the contents of the
displayed information.
M2 supports two hardware display layers. To refresh the screen the M2 reads and mixes
two independent pixel sources simultaneously.
Different formats of the pixels which are part of different applications (e.g. Teletext
formats, 12-bit RGB or 16-bit RGB values) can be stored in the same frame buffer at the
same time.

The screen refresh unit is used to read the frame buffer pixel by pixel in real time and to
process the transparency and RGB data. A color look up table (CLUT) can be used to
get the RGB data of the current pixel. Afterwards the RGB data is transferred to the D/A
converter. The blank signal and contrast reduction signal (COR) is also processed for
each pixel by the SRU and transferred to the corresponding output pins.
The pixel, line and field frequencies are widely programmable so that the sync system
can be used from low end 50 Hz to high end 100 HZ TV applications as well as for any
other standard.
The on chip clock system provides the M2 with its basic clock signals. Independent
clock domains are provided for the embedded controller, the bus interface and the
display system. The pixel clock can vary between 10 MHz and 50 MHz.
Due to the unified memory architecture of M2, a new bus concept is implemented. An
arbiter handles the bus requests from the different request sources. These are:
• Slicer 1 requests (normally used as a TTX slicer)
• Slicer 2 requests (used as a WSS slicer)
• Graphic accelerator requests
• Screen refresh unit requests
• Data requests from the CPU via XBUS
• Instruction requests via the CPU program bus
For exploiting the full computational power of the controller core the code of time critical
routines can be stored in one bank of the external SDRAM separated from all display
information (frame buffer, character set etc.). An instruction cache (I-CACHE) is used
for buffering instruction words in order to minimize the probability of wait states to occur
when the microcontroller is interfering with the display generator (DG) for access rights
to the external memory devices. The data cache (D-CACHE) serves for operand reads
and writes via the XBUS from/to external memory devices.
The external bus interface (EBI) features interleaved access cycles to one or two static
external memory devices (ROM, Flash-ROM or SRAM) with a total maximum size of
4 MByte and one PC100 compliant (Intel standard) SDRAM device (16 MBit organized
as 2 memory banks or 64 MBit organized as 4 memory banks).
For TV controlling tasks M2 provides three serial interfaces (I2C, ASC, SSC), two general
purpose timers, (GPT1, GPT2), a real time clock (RTC), a watch dog timer (WDT), an A/
D converter and eight external interrupts.

Overview
M2’s microcontroller and its peripherals are based on a Cell-Based Core (CBC) which is
compatible to the well known C166 architecture.
In M2, the CPU and its peripherals are generally clocked with 33.33 MHz which results
in an instruction cycle time of 60 ns. The implementation of the microcontroller within M2
deviates from other known C16x derivates since the controller’s XBUS is not used as the
external bus. All external access cycles of the microcontroller, the display generator and
the acquisition unit are performed via a high performance time interlocking SDRAM bus.
The external bus interface (EBI) manages the arbitration procedure for access cycles to
the external synchronous DRAM in parallel to an external static memory (ROM or
FLASH; for more details refer to Chapter 4.4).
Due to the realtime critical bus bandwidth requirements of the display generator,
unpredictable wait-states for the controller may occur. These wait-states do not destroy
the overall average system performance, because they are mostly buffered by the CPU
related instruction and data buffers. Nevertheless they can influence, for example, the
worst disconnection response time.
Emulation is now performed by an on-chip debug module which can be accessed by a
JTAG interface.
The following microcontroller peripherals are implemented:
• 2 KByte IRAM (System RAM)
• 2 KByte XRAM (XBUS located)
• 32 Interrupt Nodes
• General Purpose Timer Units (GPT1 and GPT2)
• Real Time Clock (RTC)
• Asynchronous/Synchronous Serial Interface (ASC0)
• High-Speed Synchronous Serial Interface (SSC)
• I2C Bus Interface (I2C)
• 4-Channel 8-bit A/D Converter (ADC)
• Watchdog Timer (WDT)
• On-Chip Debug Support Module (OCDS)
• 42 Multiple Purpose Ports
Central Processing Unit
The CPU executes the C166 instruction set (with the extensions of the C167 products).
Its main features are the following:
• 4-stage pipeline (Fetch, Decode, Execute and Write-Back).
• 16 ⌠ 16-bit General Purpose Registers
• 16-bit Arithmetic and Logic Unit
• Barrel shifter
• Bit processing capability.

• Hardware support for multiply and divide instructions
Internal RAM (IRAM)
The internal dual-port RAM is the physical support for the General Purpose Registers,
the system stack and the PEC pointers. Due to its close connections with the CPU, the
internal RAM provides fast access to these resources. As the GPR bank can be mapped
anywhere in the internal RAM through a base pointer (Context Pointer CP), fast context
switching is allowed. The internal RAM is mapped in the memory space of the CPU and
can be used also to store user variables or code.
Interrupt Controller
Up to 32 interrupt sources can be managed by the Interrupt Controller through a multiple
priority system which provides the user with the ability to customize the interrupt
handling.
The interrupt system of M2 includes a Peripheral Event Controller (PEC). This processor
performs single-cycle interrupt-driven byte or word transfers between any two locations
in the entire memory space of M2.
In M2, the PEC functionalities are extended by the External PEC which allows an
external device to trigger a PEC transfer while providing the source and destination
pointers. New features also include the packet transfer mode and the channel link mode.
Besides user interrupts, the Interrupt Controller provides mechanisms to process
exceptions or error conditions, so-called “hardware traps”, that arise during program
execution.

System Control Unit
M2’s System Control Unit (CSCU) is used to control system specific tasks such as reset
control or power management within an on-chip system built around the core. The power
management features of the CSCU provide effective means to realize standby
conditions for the system with an optimum balance between power reduction, peripheral
operation and system functionality. The CSCU also provides an interface to the Clock
Generation Unit (CGU) and is able to control the operation of the Real Time Clock (RTC).
The CSCU includes the following functions:
• System configuration control
• Reset sequence control
• External interrupt and frequency output control
• Watchdog timer module
• General XBUS peripherals control
• Power management additional to the standard Idle and Power Down modes
• Control interface for Clock Generation Unit
• Identification register block for chip and CSCU identification.

OCDS
The On-Chip Debug System allows the detection of specific events during user program
execution through software and hardware breakpoints. An additional communication
module allows communication between the OCDS and an external debugger, through a
standard JTAG port. This communication is performed in parallel to program execution.

Memory Organization
In normal operation mode the memory space of the CPU is configured in a “Von
Neumann” architecture. This means that code and data are accessed within the same
memory areas, i. e. external memory, internal controller memory (IRAM), the address
areas for integrated XBUS peripherals (I2C, internal XBUS memory (XRAM)) and the
special function register areas (SFR, ESFR) are mapped into one common address
space of 16 MBytes. This address space is arranged as 256 segments of 64 KBytes
each and each segment is again subdivided into four data pages of 16 KBytes each.
All internal memory areas and the address space of the integrated XBUS peripherals are
mapped to segment 0. Code and data may be stored in any part of the memory, except
for the SFR blocks, which can not be used for instructions. Despite this equivalence of
code and data, proper partitioning is necessary to make use of the full bandwidth of the
memory system.
The integrated C16x controller communicates via 2 busses with the memory interface.
In normal operation mode access to segments 00H to 41H (excluding internal memory
areas) is mapped to the read only program memory bus (PMBUS), whereas access to
segments 42H to FFH is mapped to the XBUS. In bootstrap loader mode (BSLMode)
instruction fetches to external memory areas via PMBUS are redirected to the internal
bootstrap loader ROM (BSLROM). Operand (data) accesses remain unchanged.

External Memory
M2 provides an external bus interface (EBI) to access an external SDRAM, together with
an external static memory device (ROM or SRAM). To optimize the overall system
performance, access to both memory types is interlocked. Because of high performance
requirements M2 provides only one bus type (Demultiplexed 16-bit Bus). Depending on
the reset configuration (refer to Chapter 6.1) an external ROM/SRAM size from
128 KByte up to 4 MByte can be chosen. Although external addresses (represented by
pins A0 … A20) are always word addresses, byte accesses to the SDRAM are possible
by using mask signals LDQM and UDQM.

The external SDRAM connected to M2 is a multifunctional, byte or word addressable
device which can be used for frame buffers, character sets, pixel graphics, acquisitions,
microcontroller workspace and any other data storage purposes.
Using a 100 MHz external memory bus the theoretical optimum memory bandwidth is
limited to 200 MByte/s. In order to keep the sustainable memory bandwidth as close to
the optimum as possible, the bank oriented architecture of SDRAM devices has to be
exploited. Basically, display related information should be separated from controller
related data items.
The following allocation is recommended for a 2 bank, 2 MByte device:
• “Display Bank”: Both Frame Buffers, Character Set, Pixel Graphic, Graphic
Accelerator Instructions (GAI), Application Data (i.e. TTX, EPG, …)
• “Controller Bank”: Instruction Code, VBI-buffer, Application Data (i.e. TTX, EPG, …)
The suggested allocation leads to best performance results since it reduces the number
of time consuming row commands on the SDRAM.

External Static Memory Devices
M2 supports access to external ROM, Flash ROM and SRAM devices which provide a
read cycle time tRC < 120 ns. Only 16-bit word access is supported. The maximum memory size is limited by the number of external address lines. Up to 21 external
address lines are configurable, thus devices providing up to 4 MByte of static external
memory can be connected to M2.

External Memory Configuration
The interlocking execution of access cycles to different memory modules is supported.
All external SDRAM access cycles must be executed with a pre-defined burst length
BL = 4 and latency 3. Write access cycles, which modify less than four SDRAM
locations, are achieved by activating mask control signals L/UDQM.
The integrated refresh controller of the EBI checks for the compliance of refresh periods
and executes refresh operations on the SDRAM devices. The configuration of different
external SDRAM types can be controlled by a special SW driver as well as refresh
modes and power down features. The microcontroller and the acquisition unit use a
common interface to the EBI. A separate connection to the EBI is provided for the display
generator. The EBI performs an arbitration procedure for granting right access to either
of the request sources. But granting right access to one source does not exclude
requests initiated by the other source from being served. A maximum of two access
requests from a source may be served consecutively if the other source is addressing
an SDRAM location. Up to four consecutive access cycles from the same source are
served if the other source is addressing an external ROM device.

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IMPORTANT NOTE: - FRANK SHARP obsoletetellyemuseum.blogspot.comwas founded as a public free WEB Museum to all kind of people and amateur and professional CRT TELEVISION Lovers who enjoy using and/or preserving - restoring vintage CRT Televisions sets, or only curious public who was unaware of that kind of technolgy of the past. The purpose is to provide information about vintage Television Receivers Publicy on the WEB that is generally difficult to locate; all this as a important milestone general worldwide reference for the future, globally in the public interest.obsoletetellyemuseum.blogspot.com does not provide support or parts for any apparatus on this site nor do we represent any manufacturer listed on this site in any way. Catalogs, manuals and any other literature that is available on this site is made available for a historical record only. Please remember that safety standards have changed over the years and information in old manuals as well as the old Television receivers themselves may not meet modern standards. It is up to the individual user to use good judgment and to safely operate old machinery. The obsoletetellyemuseum.blogspot.com web site will assume NO responsibilities for damages or injuries resulting from information obtained from this site. No offer to sell or license — Nothing in this site/Blog may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

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Sure Fun Times, A working TV Discovered with a CRT Oscilloscope !

Safety Hazards:

------------------------------------------------------Safety Hazards in Radio and TV Repair,------------------------------------------------------

People who believe they can conquer nature are clueless that the laws of nature are a precondition of their existence. Their weapon is a miserable idea.When man attempts to rebel against the iron logic of Nature, he comes into struggle with the principles to which he himself owes his existence as a man. And this attack must lead to his own doom.

Anyone attempting to repair any electronic equipment who does not fully understand the shock hazards, as well as the fire hazards associated with working with electronic equipment, should not attempt such procedures! Improperly attempted repair can kill you and burn down your house.Devices that plug into the wall can produce a very lethal electric shock as well cause a fire from incorrect or careless repairs both during servicing or later on.Improper repair of battery operated devices can also result in bad consequences for you, the device, and any equipment attached to it.

Why some people do repairs themselved then? If you can do the repairs yourself, the equation changes dramatically asyour parts costs will be 1/2 to 1/4 of what a professional will chargeand of course your time is free. The educational aspects may also beappealing. You also will learn a lot in the process.

Consumer electronic equipment like TVs, computer monitors, microwave ovens, and electronic flash units, use voltages at power levels that are potentially lethal. Even more so for industrial equipment like lasers and anything else that is either connected to the power line, or uses or generates high voltage.

Normally, these devices are safely enclosed to prevent accidental contact. However, when troubleshooting, testing, making adjustments, and during repair procedures, the cabinet will likely be open and/or safety interlocks may be defeated. Home-built or modified equipment, despite all warnings and recommendations to the contrary - could exist in this state for extended periods of time - or indefinitely.

Depending on overall conditions and your general state of health, there is a wide variation of voltage, current, and total energy levels that can kill.

Microwave ovens in particular are probably THE most dangerous household appliance to service. There is high voltage - up to 5,000 V or more - at high current - more than an amp may be available momentarily. This is an instantly lethal combination.

TVs and monitors may have up to 35 kV on the CRTbut the current isn't low - like a wrong legend saying a "couple of milliamps" but relatively high because of the boost circuit technology and transformer design. However, the CRT capacitance can hold a painful charge for a long time. In addition, portions of the circuitry of TVs and monitors as well as all other devices that plug into the wall socket are line connected.This is actually even more dangerous than the high voltage due to the greater current available - and a few hundred volts can make you just as dead as 35 kV!

Electronic flash units and strobe lights, and pulsed lasers have large energy storage capacitors which alone can deliver a lethal charge - long after the power has been removed. This applies to some extent even to those little disposable pocket cameras with flash which look so innocent being powered from a single 1.5 V AA battery. Don't be fooled - they are designed without any bleeder so the flash can be ready for use without draining the battery!

Even some portions of apparently harmless devices like VCRs and CD players - or vacuum cleaners and toasters - can be hazardous (though the live parts may be insulated or protected - but don't count on it!

This information also applies when working on other high voltage or line connected devices like Tesla Coils, Jacobs Ladders, plasma spheres, gigawatt lasers, hot and cold fusion generators, cyclotrons and other particle accelerators, as well as other popular hobby type projects. :-)

In addition, read the relevant sections of the document for your particular equipment for additional electrical safety considerations as well as non-electrical hazards like microwave radiation or laser light. Only the most common types of equipment are discussed in the safety guidelines, below.

SAFETY guidelines:

These guidelines are to protect you from potentially deadly electrical shock hazards as well as the equipment from accidental damage.

Note that the danger to you is not only in your body providing a conducting path, particularly through your heart. Any involuntary muscle contractions caused by a shock, while perhaps harmless in themselves, may cause collateral damage. There are likely to be many sharp edges and points inside from various things like stamped sheet metal shields and and the cut ends of component leads on the solder side of printed wiring boards in this type of equipment. In addition, the reflex may result in contact with other electrically live parts and further unfortunate consequences.

The purpose of this set of guidelines is not to frighten you but rather to make you aware of the appropriate precautions. Repair of TVs, monitors, microwave ovens, and other consumer and industrial equipment can be both rewarding and economical. Just be sure that it is also safe!

Don't work alone - in the event of an emergency another person's presence may be essential.

Always keep one hand in your pocket when anywhere around a powered line-connected or high voltage system.

Wear rubber bottom shoes or sneakers. An insulated floor is better than metal or bare concrete but this may be outside of your control. A rubber mat should be an acceptable substitute but a carpet, not matter how thick, may not be a particularly good insulator.

Don't wear any jewelry or other articles that could accidentally contact circuitry and conduct current, or get caught in moving parts.

Set up your work area away from possible grounds that you may accidentally contact.

Have a fire extinguisher rated for electrical fires readily accessible in a location that won't get blocked should something burst into flames.

Use a dust mask when cleaning inside electronic equipment and appliances, particularly TVs, monitors, vacuum cleaners, and other dust collectors.

Know your equipment: TVs and monitors may use parts of the metal chassis as ground return yet the chassis may be electrically live with respect to the earth ground of the AC line. Microwave ovens use the chassis as ground return for the high voltage. In addition, do not assume that the chassis is a suitable ground for your test equipment!

If circuit boards need to be removed from their mountings, put insulating material between the boards and anything they may short to. Hold them in place with string or electrical tape. Prop them up with insulation sticks - plastic or wood.

If you need to probe, solder, or otherwise touch circuits with power off, discharge (across) large power supply filter capacitors with a 2 W or greater resistor of 100 to 500 ohms/V approximate value (e.g., for a 200 V capacitor, use a 20K to 100K ohm resistor). Monitor while discharging and/or verify that there is no residual charge with a suitable voltmeter. In a TV or monitor, if you are removing the high voltage connection to the CRT (to replace the flyback transformer for example) first discharge the CRT contact (under the insulating cup at the end of the fat red wire). Use a 1M to 10M ohm 1W or greater wattage resistor on the end of an insulating stick or the probe of a high voltage meter. Discharge to the metal frame which is connected to the outside of the CRT.

For TVs and monitors in particular, there is the additional danger of CRT implosion - take care not to bang the CRT envelope with your tools. An implosion will scatter shards of glass at high velocity in every direction. There is several tons of force attempting to crush the typical CRT. Always wear eye protection. While the actual chance of a violent implosion is relatively small, why take chances? (However, breaking the relatively fragile neck off the CRT WILL be embarrassing at the very least.)

Connect/disconnect any test leads with the equipment unpowered and unplugged. Use clip leads or solder temporary wires to reach cramped locations or difficult to access locations.

If you must probe live, put electrical tape over all but the last 1/16" of the test probes to avoid the possibility of an accidental short which could cause damage to various components. Clip the reference end of the meter or scope to the appropriate ground return so that you need to only probe with one hand.

Perform as many tests as possible with power off and the equipment unplugged. For example, the semiconductors in the power supply section of a TV or monitor can be tested for short circuits with an ohmmeter.

Provide a reliable means of warning that power is applied and that high voltage filter capacitor(s) still hold a charge during servicing. For example, solder a neon indicator lamp (e.g., an NE2 in series with a 100K ohm resistor) across the line input and a super high brightness LEDs in series with 100K, 1 W resistors across the main filter capacitor(s).

Use an isolation transformer if there is any chance of contacting line connected circuits. A Variac(tm) (variable autotransformer) is not an isolation transformer! However, the combination of a Variac and isolation transformer maintains the safety benefits and is a very versatile device. See the document "Repair Briefs, An Introduction", available at this site, for more details.

The use of a GFCI (Ground Fault Circuit Interrupter) protected outlet is a good idea but may not protect you from shock from many points in a line connected TV or monitor, or the high voltage side of a microwave oven, for example. (Note however, that, a GFCI may nuisance trip at power-on or at other random times due to leakage paths (like your scope probe ground) or the highly capacitive or inductive input characteristics of line powered equipment.) A GFCI is also a relatively complex active device which may not be designed for repeated tripping - you are depending on some action to be taken (and bad things happen if it doesn't!) - unlike the passive nature of an isolation transformer. A fuse or circuit breaker is too slow and insensitive to provide any protection for you or in many cases, your equipment. However, these devices may save your scope probe ground wire should you accidentally connect it to a live chassis.

When handling static sensitive components, an anti-static wrist strap is recommended. However, it should be constructed of high resistance materials with a high resistance path between you and the chassis (greater than 100K ohms). Never use metallic conductors as you would then become an excellent path to ground for line current or risk amputating your hand at the wrist when you accidentally contacted that 1000 A welder supply!

Don't attempt repair work when you are tired. Not only will you be more careless, but your primary diagnostic tool - deductive reasoning - will not be operating at full capacity.

Finally, never assume anything without checking it out for yourself! Don't take shortcuts!

Many people who mistakenly feel that ‘old technology’ is somehow more user-friendly, in some strange way automatically good - merely because it is old. Don’t be fooled! Approach old equipment with an open and alert mind and realise that a hot chassis, or a resistor line cord, or asbestos insulation, or selenium rectifiers require much more thought and consideration for safety.

Live chassis are indiscriminate in whom they kill and even if you are a thoughtful, careful kind of person, that doesn’t mean the last person who handled the set was.

Vintage radio and television receivers use 'live chassis' techniques, in which the chassis is connected directly to one side of the incoming mains supply. This means they can be lethal to carry out repair or servicing work on, unless the appropriate safety measures are in place.

Another thing about live-chassis sets - live spindles. We’ve touched on this already but it’s worth making the point once more. The shafts of switches and potentiometers fixed to the chassis may well be at chassis potential and thus live. The bakelite or wood cabinet is insulated but these shafts are not, and if someone lost the proper grub screw and replaced a knob using a cheesehead screw, the next person to grip that knob may get a dose of 250 volts. Originally these grub screws were sealed and embedded in wax but you cannot rely on subsequent tinkerers having the same high standards.

Even in more orthodox apparatus standards of insulation were not always as high as they are now. Soldered connections to HT and mains wiring should always have rubber or plastic sleeving but in times gone by this was often omitted (or it may since have perished). Beware too of kinked and frayed braiding on cloth-covered mains cords, particularly when the cord has a dropper conductor.

If you are not satisfied that you fully understand the risks involved in this sort of work, do not proceed any further. Instead seek advice and assistance from a competent technician or engineer.

Whenever you acquire a new treasure there's always a terrific temptation to try it out. With mains-driven equipment that means plugging it in and seeing if it works. Well don't, not until you have made some quick checks.

Before contemplating connecting any unknown receiver to the mains supply, spend a little time inspecting it for signs of missing or loose parts, blown fuses, overheating or even fire damage. Use a meter to check obvious points to ensure no short circuit exists (e.g. across the mains input). If you then decide to apply power keep clear but be observant since an elderly electrolytic might explode! This can be avoided if you can apply power gradually through a variac. Auto-transformers are handy for supplying reduced power to sets being repaired but they are not a substitute for a proper isolation transformer!

If you are working with electricity and your work area has a concrete floor, a rubber mat is essential, particularly during damp weather! Where possible try to arrange a neat working area away from water or central heating pipes. For safety try to arrange that this area is separate from the area occupied by your family. This is emphasised because inadvertently rushing to answer a telephone you might just leave a TV chassis connected to a supply and curious little fingers know nothing of the dangers of electricity - or, for that matter - the lethal vacuum encased within every picture tube!

Many younger enthusiasts may not be aware of the dangers of mishandling tubes, in particular the old round types found in early TVs. When handling these tubes eye protection should be worn and tubes must not be left lying around, they must be stored in boxes. The glass is surprising fragile and can implode without any provocation or warning. Bits of glass flying around at high speed can be deadly. The notes following are inspired by Malcolm Burrell again.

Picture tubes are perhaps one of the most hazardous items in any TV receiver. This is because most are of glass construction and contain a very high vacuum. If you measured the total area of glass in any picture tube then estimated the pressure of air upon it at 14.7lb. per square inch, you would discover that the total pressure upon the device could amount to several tons! Fracturing the glass suddenly would result in an extremely rapid implosion such that fragments of glass, metal and toxic chemicals would be scattered over a wide area, probably causing injury to anyone in close proximity. In modern workshops it is now a rule that protective goggles are worn when handling picture tubes.

The weakest point in most picture tubes is where the thin glass neck containing the electron gun is joined to the bowl. It is therefore essential that you refrain from handling the tube by its neck alone. Once a tube is removed from the receiver hold it vertically with the neck uppermost and one hand beneath the screen with the other steadying the device by the neck.With larger devices it is sometimes easier to grip the peripheral of the screen with both hands.

Until the advent of reinforced picture tubes, most were mounted in the cabinet or on the TV chassis by some form of metal band clamped around the face.Never support the weight of the tube by this band since it has been known for the tube to slide out! Some of the larger tubes are extremely heavy. It may, therefore, be easier to enlist assistance.

Before starting to remove a tube, first discharge the final anode connection to the chassis metalwork and preferably connect a shorting lead to this connection whilst you are working. It might be convenient to keep a spare piece of EHT cable with a crocodile clip at one end and a final anode connector at the other.

Exercise care when removing picture tubes from elderly equipment. You may find that the deflection coils have become stuck to the neck. It is extremely dangerous to use a screwdriver prise them away. Gently heating with a hairdryer or soaking in methylated spirit is safer.

Disposal of picture tubes also requires care. Unless rendered safe they should never be placed in dustbins or skips. Many engineers swipe the necks off tubes in cavalier fashion using a broom handle but this is not recommended. A safer method is to make a hole in the side of a stout carton, preferably one designed to hold a picture tube. The tube is placed in the carton and the neck broken using a broom handle. The carton should then be clearly labelled that it contains chemicals and broken glass!

Therefore people who believe they can conquer nature are clueless that the laws of nature are a precondition of their existence. Their weapon is a miserable idea.When man attempts to rebel against the iron logic of Nature, he comes into struggle with the principles to which he himself owes his existence as a man. And this attack must lead to his own doom.

Think for yourself. Otherwise you have to believe what other people tell you.

For most people thinking is a matter of fortune.A society based on individualism is an oxymoron.Freedom is at first the freedom to starve.A wise fool speaks, because he has something to say.A fool speaks, because he has to say something.A wise fool is silent, because there is nothing to say.A fool is silent, because he has nothing to say.

Resist or regretWork for what's good for our people

Help stem the dark tideStand tall or be beat downFight back or die

The man who does not exercise the first law of nature—that of self preservation — is not worthy of living and breathing the breath of life.

We now live in a nation where doctors destroy health, lawyers destroy justice, universities destroy knowledge, governments destroy freedom, the press destroys information, religion destroys morals and our banks destroy the economy.The globalist argument is that if only we erase distinctions, obliterate identities, put everyone on a level playing field, etc.. we can eliminate war and everyone can be so prosperous and efficient, such great cogs in a well-oiled global machine.There will be no more historical grievances because people will no longer even care, they'll have no connection to the past, no foolish pride in past accomplishments of people totally unrelated to them.A globalized culture, no borders, everyone a citizen of the world.Know this: I will never acquiesce to this corrupt, inhuman, Borg-like vision. The dangerous lunatics who push us towards their globalized "utopia" are my enemy. How exactly all this will play out, whether through wars, or whether we can thwart the globalist agenda peacefully (this is my hope of course) I don't know. But I do know that unless people are willing to fight and die, globalism will win out in the end.The actual crimes committed by the EU against the European peoples are directly in violation of the 1948 UN genocide convention, Article II: (c) Deliberately inflicting on the group conditions of life calculated to bring about its physical destruction in whole or in part; (d) Imposing measures intended to prevent births within the group; (e) Forcibly transferring children of the group to another group.* The man who does not exercise the first law of nature—that of self preservation — is not worthy of living and breathing the breath of life.

TELEVISION HISTORY IN BRIEF

Television history

At 1928 Baird transmits from London to New York, using his mechanical system.with 30 vertical lines. By 1930 it was clear that mechanical television systems could never produce the picture quality required for commercial success. For this reason mechanical system was rapidly succeeded by the electronic TV systems. The first all-electronic American systems in 1932 used only 120 scanning lines at 24 frames per second Since the mid-1930s picture repetition frequency (field rate or frame rate) has been the same as the mains frequency, either 50 or 60Hz according to the frequency used in each country. This is for two very good reasons. Studio lighting generally uses alternating current lamps and if these were not synchronised with the field frequency, an unwelcome strobe effect could appear on TV pictures. Secondly, in days gone by, the smoothing of power supply circuits in TV receivers was not as good as it is today and ripple superimposed on the DC could cause visual interference. If the picture was locked to the mains frequency, this interference would at least be static on the screen and thus less obtrusive.To determine what electronic system to use, the BBC sponsored trial broadcasts by two systems, one by Baird, with 240 lines, and one by EMI with 405 lines. Scheduled electronic television broadcasting began in England in 1936 using 405-line system (lasted until the 1980s in the UK). Germany made their forst TV broadcasts at 1936 olympics using 180-line TV system. Germany also made their TV broadcasts by the fall of 1937 using a 441-line system. Also fFrance tested TV (455 line system). RCA introduced electronic television to the U. S. at the 1939 World's Fair,and began regularly scheduled broadcasting at the same time (525 line system).In 1940 the USA established its 525-line standard. At year 1941 the 525-line standard, still in use today in USA, was adopted.Russia also produced TV sets before the war (240 and 343 line systems).World War Two interrupted the development of television. Immediately after World War Two production of TV sets started in the U.S-In USA there was TV broadcasts and few throusand receivers at 1945. In the early 1950s, two competing color TV systems emerged: CBS sequential color (used color wheel) and RCA dot sequential system. At 1953 color broadcasting officially arrives in the U.S. on Dec. 17, when FCC approves modified version of an RCA system.It calls this new RCA color system "NTSC" color. The first NTSC color TVs were on the marker at 1954.In Europe the TV broadcasts started to use experiment using 625 line system 1950s. This standard is used nowadays throughout Europe. France also tried 819 line system at the same time (this system was in use to 1980s). The rest of Europe opted for 625 lines, a system devised in 1946 by two German engineers, M??ller and Urtel (it appears that the Russians came up independently with a very similar system). The use of PAL color standard started at around 1967 and is still in use. The SECAM color system (used in France) testing started also at 1967. The TV broadcasting history has not ended. The newst thign is digital television. It is expected that terrestrial television will open up billion-dollar opportunities for those companies and organisations best prepared to embrace this new broadcasting era. At 1996 small digital satellite dishes hit the market. They become the biggest selling electronic item in history next to the VCR.

Using TV 24H

TV has something for everyone. Idiots, intellectuals, fans of all sorts. Some people are couch potatoes, watch anything just to sit there and be mindless. That's their problem. Children have always needed to be monitored by their parents. If people gotta a mind for it they could figure out the real news even without the internet and there has always been a library.

Is TV bad in and of itself? The researchers aren’t saying that. But we all know that watching television is a solitary, isolating occupation that keeps you sedentary. Sitting in front of the boob tube reduces the time you have available to exercise, interact with your family, read books, and be outdoors. This new research dovetails with other studies, which have linked excessive TV time to obesity and higher rates of cardiovascular disease.

watching too much television can jeopardize your whole family’s health.

This should be a wake-up call to all adults. Stay active. Go outside. Spend time with your spouse and your children with the television off. Read a book and do crossword puzzles to stimulate your imagination and your brain. Reduce your screen time as much as you can.

The National Cancer Institute researchers suggest that watching TV is a public health issue. The price we are paying for our technology-driven lives may be much higher than we previously realized !

DON'T WATCH TV AT ALL !!

The Propaganda TV Machine a.k.a. The Ministry of Truth delivers The Truth from The Government to the people.

At least, that's what they say. In fact, a Propaganda Machine is only employed by The Empire and used to brainwash people into Gullible Lemmings who believe that everything is all right when in fact, it isn't, and that the very people who could help them are their enemies.

Girl Looking TV.

Happy Times:

Do you remember when a telly looked like a real telly? When it was a piece of furniture that you lavished love on, even polished from time to time ?When it was a piece of somewhat at looking in to ?When it was a piece of Highest tech looking inside ? First, this site is a Digital free, HD free, flat panel, HDMI, China, Turks, Afrika free zone. All in all a wealth of vintage information at your finger tips, a one stop unique experience. So step on in, leave the modern throw-away world behind, travel back in time to a vintage world of repair and enjoy.This site has stirred memories about the watching TV's days on a CRT TUBE television......Childhood memories, your parents getting their first colour tv, a b/w or color portable, perhaps memories of renting or buying your first set remote featured, perhaps your days working in the trade, selling or repairing them....... If you enjoyed this site, found its content left you all misty eyed then just talk about it as it would be very welcome............like the time to recover and restore a set ................and happy reminiscing.

Digital TV in Brief.

Digital TV:

Digital television is a hot topic now.If you have looked at television sets at any of the big electronics retailers lately, you know that Digital TV, or DTV, is a BIG deal right now in the U.S. In Europe Digital TV is also a hot topic, because many countries have started terrestrial digital TV broadcasts and plan to end analogue broadcasts after some years (will take 5-10 years). Satellite TV broadcasts have also shifted very much to digital broadcasts.The main advantage if digital broadcasts are that it does not havethe picture quality problems of analogue TVs (it had it's own videoproblems caused by video compression), it allowes putting more TV channels to same medium (TV channel frequencies and satellites) and it allows new services (like HDTV and interactive multimedia). The digital brodcasts are generally designed to use such modulation that the digital data stream (typically around 20-30 Mbit/s) is modulated to the same bandwidth (around 6 MHz) as the analogue TV broadcasts. The used modulation vary between different media, which means thatdifferent modulation techniques are used in terrestrial transmissions, cable TV and satellite. Different modulations are used because of the different characteristics of those transmission medias. There is not on "digital TV", but several different variations of it in use.The basic technology of digital TV, known as MPEG 2 video compressionand MPEG 2 transmission stream format, is same around the world, butis is used somewhat differently in different standards used in differentcountries.

USA uses ACTS Digital Televisio Standard, which standardizes NTSC format transmissions, HDTV transmission, sound formats and data signal modulation in use. The ATSC MPEG-2 formats for DTV, including HDTV, uses 4:2:0 samling for video signal. The US system uses a fixed power and a fixed maximum bitrate, at which some bits are always transmitted. That rate is typically 19.3 Mb/sec.

Europe uses DVB (Digital Video Broadcasting) standard. This standardallows basically normal PAL resolution transmisssion (vasically HDTVcould be added later but is not yet standardized) with several audio formats, digital data rates and digital signal modulation. There are several different variations fo DVB standard for different media:

DVB-T for terrestrial broadcastsDVB-S for satelliteDVB-C for cable TV

Those different DVB versions varyon the data signal modulation methods, error correction and frequency bands used. DVB and option for some interactive extra services, but thestandardization of this is not ready here yet(there are fire different incompatible interactive servicessystems in use in different countries and by different broadcasters).

The process of transmitting digital TV signal is the following: Analog video/audio - digitisation - MPEG compression - Multiplexing ( youcan now call it digital) - Preparation for transmisson - modulation toanalog carrier.Reception process is the following: Demodulation of analogue carrier - Error correction - Demultiplexing - MPEG decompression - DA conversion to get analogue signal (unless you use digital display). The analoguie video signal that gets digitized can be practically from any video source, for example produced with old analogue video production equipment and distributed with a video tape. In high-end system the information is analogue only in the image sensor on the video camera, and from this on the signal gets digitally processed. In many real-life TV production systems the reality is something between those two extremes.

At least in Europe, the signal level requirements for DVB-T are well below the analog requirements, so the transmitter power is much less than on the analog side. In the NorDig recommendation the minimum received signal level for 64QAM, 7/8 code rate with a Rayleigh fading path and 8 dB receiver noise figure would be -64 dBm. With other code rates, modulations and fading mechanisms, the requirement is lower. Many receivers can perform much better at conditions where there is no fading (a quasi error free less than one uncorrected error/hour signal even at 27 dBuV (-82 dBm) with 64QAM and 8 MHz channel width). For analog signals, the recommended level is more than 1 mV (+60 dBuV, -49 dBm). While the ERP can be at least 10 dB lower than analog, the question of power consumption is more complicated, since COFDM with 64QAM carriers require a quite good linearity, which may affect the efficiency and hence power consumption.

Digital TV system in use in USA

The FCC mandate to change our broadcast standards from NTSC analog to ATSC digital broadcasting (DTV) is big bold move, requiring changes in everything from the way the studios shoot video, the format that's transmitted, to the equipment we use to receive and watch broadcastsDTV (digital TV) applies to digital broadcasts in general and to the U.S. ATSC standard in specific. The ATSC standard includes both standard-definition (SD) and high-definition (HD) digital formats. The notation H/DTV is often used to specifically refer to high-definition digital TV. The federal mandate grants the public airwaves to the broadcasters to transmit digital TV in exchange for return of the current analog NTSC spectrum, allowing for a transition period in the interim. At the end of this period scheduled for 2006, broadcasters must be fully converted to the 8VSB broadcast standard. Digital Television ("DTV") is a new broadcast technology that will transform television. The technology of DTV will allows TV broadcasts with movie-quality picture and CD- quality sound and a variety of other enhancements (for example data delivery). With digital television, broadcasters will be able to offer free television of higher resolution and better picture quality than now exists under the current mode of TV transmission. If broadcasters so choose, they can offer what has been called "high definition television" or HDTV, television with theater-quality pictures and CD-quality sound. . Alternatively, a broadcaster can offer several different TV programs at the same time, with pictures and sound quality better than is generally available today. HDTV (high-definition TV) encompasses both analog and digital televisions that have a 16:9 aspect ratio and approximately 5 times the resolution of standard TV (double vertical, double horizontal, wider aspect). High definition is generally defined as any video signal that is at least twice the quality of the current 480i (interlaced) analog broadcast signal. There are 18 approved formats for digital TV broadcasts, but only two (720p/1080i) are proper definition of the term HDTV. The advent of high definition has allowed monitors to read images differently, either in standard interlaced format or progressively. Sets that do not have any decoding capabilities but can display the high-resolution image is often labeled as "HD-Ready" a term that describes 80% or more of the Digital TVs on the market. HDTV displays support digital connections such as HDMI (DVI) and IEEE 1394/FireWire, although standardization is not finished. HDTV in the US is part of the ATSC DTV format. The resolution and frame rates of DTV in the US generally correspond to the ATSC recommendations for SD (640x480 and 704x480 at 24p, 30p, 60p, 60i) and HD (1280x720 at 24p, 20p, and 60p; 1920x1080 at 24p, 30p and 60i). In addition, a broadcaster will be able to simultaneously transmit a variety of other information through a data bitstream to both enhance its TV programs and to provide entirely new services. The technical specifications of USA DTV system is defined in ACTS Digital Television Standards.

Digital TV in Europe

Digital TV brodacasting in Europe is done according to DVB standards. DVB technology has become an integral part of global broadcasting, setting the global standard for satellite, cable and terrestrial transmissions and equipment. There are three versions of DVB in use: DVB-S, DVB-C and DVB-T.DVB-T is a flexible system allowing terrestrial broadcastersto choose from a variety of options to suit their various service environments. This allows the choice between fixed roof-top antenna, portableand even mobile reception of DVB-T services. Broadly speaking the trade-off in one of service bit-rate versus signal robustness.

DVB-T network is very flexible. Having many transmitters all on the same frequency is not a problem for the used COFDM based system. COFDM has been chosen and designed to minimise the effects of multipath in obstructed reception areas. In fact multipath signals can significantly improve the overall received signal with no adverse effects. These properties are particularly valuable for radio cameras and mobile links. DVB-T because of its unique design which allows single frequency networks (SFN). This means that many transmitters along the planned routes can transmit on the same frequency. It is also possible to use simple gap fillers that amplify and retransmit the signal. In-air digital TV broadcasts in Europe use DVB-T. 8 MHz of bandwidth may be used to provide a 24 Mbps digital transmission path using Coded Orthogonal Frequency Division Multiplexing (COFDM) modulation (theoretical maximum 31.67 Mbits for 8 MHz bandwidth). In cases where less bandwidth is available (6 or 7 MHz), the data rate is somewhat lower (around 20 Mbit/s).

DVB-C does the same function as DVB-T, but the modulation used in this system is optimized to operate well in cable TV networks. The modulation used in DVB-C is QAM. Systems from 16-QAM up to 256-QAM can be used, but the system centres on 64-QAM, in which an 8MHz channel can accommodate a physical payload of about 38 Mbit/s. Digital cable TV in Europe uses DVB-C. The DVB standard for the cable return path has been developed jointly with DAVIC, the Digital Audio Visual Council. The specification uses Quadrature Phase Shift Keying (QPSK) modulation in a 200kHz, 1MHz or 2MHz channel to provide a return path for interactive services (from the user to the service provider) of up to about 3Mbit/s. The path to the user may be either in-band (embedded in the MPEG-2 Transport Stream in the DVB-C channel) or out-of-band (on a separate 1 or 2MHz frequency band).

DVB-S is the satellite version of DVB. Satellite transmission has lead the way in delivering digital TV to viewers. Established in 1995, the satellite standard DVB-S is the oldest DVB standard, used on all six major continents. QPSK modulation system is used, with channel coding optimised to the error characteristics of the channel. A typical satellite channel has 36 MHz bandwidth, which may support transmission at up to 38 Mbps (assuming delivery to a 0.5m receiving antenna) using Quadrature Phase Shift Keying (QPSK) modulation. 16 bytes of Reed Solomon (RS) coding are added to each 188 byte transport packet to provide Forward Error Correction (FEC) using a RS(204,188,8) code. For the satellite transmission, the resultant bit stream is then interleaved and convolutional coding is applied.

The core of the DVB digital data stream isthe standard MPEG-2 "data container",which holds the broadcast and service information.This flexible "carry-all" can containanything that can be digitised, includingmultimedia data. The MPEG-2 standards define how to format the various component parts of a multimedia programme (which may consist of: MPEG-2 compressed video, compressed audio, control data and/or user data). It also defines how these components are combined into a single synchronous transmission bit stream. The process of combining the steams is known as multiplexing. The multiplexed stream may be transmitted over a variety of links, standards / products.Each MPEG-2 MPTS multiplex carries a number of streams which in combination deliver the required services. A typical data rate of such multiplex is around 24 Mbps for terrestrial brodcasts.

European DVB systems currently transmit only standard definition TV signals and set top boxes also handle only normal TV resolution. It would be possible to transmit HDTV signals on DVB data stream, but those broadcasts have not yet started in any wide scale. There is one satellite broadcater that broadcasts HDTV DVB signals in Europe (some cable TV operators carry that signal on their cable).

Many DVB-T integrated TV sets, and some set top boxes, in the Europe come with a Common Interface slot - which is pretty much the same form-factor as a PC Card (aka PCMCIA) used in PC laptops. This CI slot accepts a Conditional Access Module, in the same way that DVB-S receivers do, which implements at least one (some can do more than one) decryption algorithm. This CAM may also, itself, have a smart card slot to accept a consumer subscription card to authorise decryption - you plug your smartcard into your CAM and your CAM into the CI slot in your receiver/IDTV. Some DVB receivers have an integrated CAM (in the case of some receivers this is implemented purely in software, with no extra hardware required) rather than a CI slot to plug in a 3rd party device. With these type of receivers you just plug in the smart card and don't have to worry about CI slots and buying CAMs. So there is an interface standard for DVB - but different broadcasters can chose different encryption schemes, requiring different CAMs for decryption.

DVB Standards and related documents are published by the European Telecommunications Standards Institute (ETSI). These include a large number of standards and technical notes to complement the MPEG-2 standards defined by the ISO.

There are few different standard how interactive TV functionaly is implemented in DVB-systems in use in differenct countries. DVB-MHP is one gaining some acceptance. Multimedia Home Platform (MHP) is the open middleware system designed by the DVB Project (www.dvb.org).

Obsolete Technology Tellye ! Visitors From 15/May/2012:

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