On Sat, May 8, 2010 at 18:32, Johannes Weiner wrote:> On Fri, May 07, 2010 at 02:28:16PM -0400, Mike Frysinger wrote:>> On Fri, May 7, 2010 at 06:15, Oskar Schirmer wrote:>> > On Thu, May 06, 2010 at 14:46:04 -0400, Mike Frysinger wrote:>> >> On Thu, May 6, 2010 at 06:37, Oskar Schirmer wrote:>> >> > struct ser_req {>> >> > + u16 sample;>> >> > + char __padalign[L1_CACHE_BYTES - sizeof(u16)];>> >> > +>> >> > u16 reset;>> >> > u16 ref_on;>> >> > u16 command;>> >> > - u16 sample;>> >> > struct spi_message msg;>> >> > struct spi_transfer xfer[6];>> >> > };>> >>>> >> are you sure this is necessary ? ser_req is only ever used with>> >> spi_sync() and it's allocated/released on the fly, so how could>> >> anything be reading that memory between the start of the transmission>> >> and the return to adi7877 ?>> >>> > msg is handed over to spi_sync, it contains the addresses>> > which will be used to programme the DMA: the spi master>> > transfer function will read these fields to start DMA.>>>> so the issue is coming from the SPI master drivers and not the AD7877 driver>> No, the issue is coming from ad7877 placing a transmission buffer> into the same cache line with memory locations that are accessed outside> the driver's scope.

you missed the point of my comment. as i clearly explained in theother structure, the AD7877 driver was causing the cache desync. hereit is the SPI master that is implicitly causing it. i'm not talkingabout the AD7877 being correct wrt to the implicit SPI/DMArequirements, just what code exactly is triggering the cache issues.

> /*> * DMA (thus cache coherency maintainance) requires the> * transfer buffers to live in their own cache lines.> */> char __padalign[...];>> ? It might be obvious what the code does, but I agree with> Mike that it might not be immediately apparent why it's needed.