SN54221 and SN74221 DemonstrateElectrical and Switching CharacteristicsThat Are Virtually Identical to the SN54121and SN74121 One Shots

D

Pinout Is Identical to the SN54123,SN74123, SN54LS123, and SN74LS123

D

Overriding Clear Terminates Output Pulse

TYPE

MAXIMUM

OUTPUT

PULSE

LENGTH(S)

SN54221

21

SN74221

28

SN54LS221

49

SN74LS221

70

description/ordering information

The '221 and 'LS221 devices are dualmultivibrators with performance characteristicsvirtually identical to those of the '121 devices.Each multivibrator features a negative-transition-triggered input and a positive-transition-triggeredinput, either of which can be used as an inhibitinput.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54221, SN54LS221, SN74221, SN74LS221

DUAL MONOSTABLE MULTIVIBRATORS

WITH SCHMITT TRIGGER INPUTS

SDLS213B - DECEMBER 1983 - REVISED NOVEMBER 2004

2

POST OFFICE BOX 655303

·

DALLAS, TEXAS 75265

description/ordering information (continued)

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the inputpulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering from inputs withtransition at rates as slow as 1 V/s, providing the circuit with excellent noise immunity, typically of 1.2 V. A highimmunity to V

CC

noise, typically of 1.5 V, also is provided by internal latching circuitry.

Once fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timingcomponents, or the output pulses can be terminated by the overriding clear. Input pulses can be of any durationrelative to the output pulse. Output pulse length can be varied from 35 ns to the maximum by choosingappropriate timing components. With R

ext

= 2 k

and C

ext

= 0, an output pulse typically of 30 ns is achieved

that can be used as a dc-triggered reset signal. Output rise and fall times are TTL compatible and independentof pulse length. Typical triggering and clearing sequences are shown as a part of the switching characteristicswaveforms.

Pulse-width stability is achieved through internal compensation and is virtually independent of V

CC

and

temperature. In most applications, pulse stability is limited only by the accuracy of external timing components.

Jitter-free operation is maintained over the full temperature and V

CC

ranges for more than six decades of timing

capacitance (10 pF to 10

µ

F) and more than one decade of timing resistance (2 k

to 30 k

for the SN54221,

2 k

to 40 k

for the SN74221, 2 k

to 70 k

for the SN54LS221, and 2 k

to 100 k

for the SN74LS221).

Throughout these ranges, pulse width is defined by the relationship: t

w

(out) = C

ext

R

ext

In2

0.7 C

ext

R

ext

. In

circuits where pulse cutoff is not critical, timing capacitance up to 1000

µ

F and timing resistance as low as 1.4 k

can be used. Also, the range of jitter-free output pulse widths is extended if V

CC

is held to 5 V and free-air

temperature is 25

°

C. Duty cycles as high as 90% are achieved when using maximum recommended R

T

. Higher

duty cycles are available if a certain amount of pulse-width jitter is allowed.

The variance in output pulse width from device to device typically is less than

±

0.5% for given external timing

components. An example of this distribution for the '221 is shown in Figure 3. Variations in output pulse widthversus supply voltage and temperature for the '221 are shown in Figures 4 and 5, respectively.

Pin assignments for these devices are identical to those of the SN54123/SN74123 or SN54LS123/SN74LS123so that the '221 or 'LS221 devices can be substituted for those products in systems not using the retrigger bymerely changing the value of R

ext

and/or C

ext

; however, the polarity of the capacitor must be changed.

FUNCTION TABLE

(each monostable multivibrator)

INPUTS

OUTPUTS

CLR

A

B

Q

Q

L

X

X

L

H

X

H

X

L

H

X

X

L

L

H

H

L

H

H

L

H

Pulsed-output patterns are tested during

AC switching at 25

°

C with Rext = 2 k

, and

Cext = 80 pF.

This condition is true only if the output of

the latch formed by the two NAND gateshas been conditioned to the logic 1 stateprior to CLR going high. This latch isconditioned by taking either A high orB low while CLR is inactive (high).

SN54221, SN54LS221, SN74221, SN74LS221

DUAL MONOSTABLE MULTIVIBRATORS

WITH SCHMITT TRIGGER INPUTS

SDLS213B - DECEMBER 1983 - REVISED NOVEMBER 2004

3

POST OFFICE BOX 655303

·

DALLAS, TEXAS 75265

timing component connections

VCC

Rext

To Cext

Terminal

To Rext/Cext

Terminal

NOTE: Due to the internal circuit, the Rext/Cext terminal never is more positive than the Cext terminal.

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES:

1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

SN54221

SN74221

UNIT

MIN

NOM

MAX

MIN

NOM

MAX

UNIT

VCC

Supply voltage

4.5

5

5.5

4.75

5

5.25

V

IOH

High-level output current

-800

-800

µ

A

IOL

Low-level output current

16

16

mA

v/

t

Rise or fall of input pulse rate

B input

1*

1

V/s

v/

t

Rise or fall of input pulse rate

A input

1*

1

V/

µ

s

TA

Operating free-air temperature

-55

125

0

70

°

C

On products compliant to MIL-PRF-38535, this parameter is not production tested.

NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.