Comments

If the ready bit in the transmit buffer descriptor (TxBD[R])
is previously detected as not set during a prior frame transmission,
then the ENET_TDAR[TDAR] bit is cleared at a later time, even if
additional TxBDs were added to the ring and the ENET_TDAR[TDAR]
bit is set. This results in frames not being transmitted until
there is a 0-to-1 transition on ENET_TDAR[TDAR].
Workarounds:
code can use the transmit frame interrupt flag (ENET_EIR[TXF])
as a method to detect whether the ENET has completed transmission
and the ENET_TDAR[TDAR] has been cleared. If ENET_TDAR[TDAR] is
detected as cleared when packets are queued and waiting for transmit,
then a write to the TDAR bit will restart TxBD processing.
This case main happen when loading is light. A ethernet package may
not send out utile next package put into tx queue.
How to test:
while [ true ]
do
ping <IP> -s 10000 -w 4
ping <IP> -s 6000 -w 2
ping <IP> -s 4000 -w 2
ping <IP> -s 10000 -w 2
done
You will see below result in overnight test.
6008 bytes from 10.192.242.116: seq=1 ttl=128 time=0.722 ms
4008 bytes from 10.192.242.116: seq=0 ttl=128 time=1001.008 ms
4008 bytes from 10.192.242.116: seq=1 ttl=128 time=1.010 ms
10008 bytes from 10.192.242.116: seq=0 ttl=128 time=0.896 ms
After apply this patch, >1000ms delay disappear.
Signed-off-by: Frank Li <Frank.Li@freescale.com>
---
drivers/net/ethernet/freescale/fec.h | 1 +
drivers/net/ethernet/freescale/fec_main.c | 32 +++++++++++++++++++++++++++-
2 files changed, 31 insertions(+), 2 deletions(-)

On 25/07/13 14:06, Li Frank wrote:
>If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously detected as not set during a prior frame transmission, then the ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in frames not being transmitted until there is a 0-to-1 transition on ENET_TDAR[TDAR].>>Workarounds:>code can use the transmit frame interrupt flag (ENET_EIR[TXF]) as a method to detect whether the ENET has completed transmission and the ENET_TDAR[TDAR] has been cleared. If ENET_TDAR[TDAR] is detected as cleared when packets are queued and waiting for transmit, then a write to the TDAR bit will restart TxBD processing.>>This case main happen when loading is light. A ethernet package may not send out utile next package put into tx queue.>>How to test:>while [ true ]>do> ping <IP> -s 10000 -w 4> ping <IP> -s 6000 -w 2> ping <IP> -s 4000 -w 2> ping <IP> -s 10000 -w 2>done>>You will see below result in overnight test.>>6008 bytes from 10.192.242.116: seq=1 ttl=128 time=0.722 ms>4008 bytes from 10.192.242.116: seq=0 ttl=128 time=1001.008 ms>4008 bytes from 10.192.242.116: seq=1 ttl=128 time=1.010 ms>10008 bytes from 10.192.242.116: seq=0 ttl=128 time=0.896 ms>>After apply this patch, >1000ms delay disappear.>>Signed-off-by: Frank Li <Frank.Li@freescale.com>
Acked-by: Fugang Duan <B38611@freescale.com>
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From: Duan Fugang-B38611 <B38611@freescale.com>
Date: Thu, 25 Jul 2013 08:16:23 +0000
> On 25/07/13 14:06, Li Frank wrote:>>If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously detected as not set during a prior frame transmission, then the ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in frames not being transmitted until there is a 0-to-1 transition on ENET_TDAR[TDAR].>>>>Workarounds:>>code can use the transmit frame interrupt flag (ENET_EIR[TXF]) as a method to detect whether the ENET has completed transmission and the ENET_TDAR[TDAR] has been cleared. If ENET_TDAR[TDAR] is detected as cleared when packets are queued and waiting for transmit, then a write to the TDAR bit will restart TxBD processing.>>>>This case main happen when loading is light. A ethernet package may not send out utile next package put into tx queue.>>>>How to test:>>while [ true ]>>do>> ping <IP> -s 10000 -w 4>> ping <IP> -s 6000 -w 2>> ping <IP> -s 4000 -w 2>> ping <IP> -s 10000 -w 2>>done>>>>You will see below result in overnight test.>>>>6008 bytes from 10.192.242.116: seq=1 ttl=128 time=0.722 ms>>4008 bytes from 10.192.242.116: seq=0 ttl=128 time=1001.008 ms>>4008 bytes from 10.192.242.116: seq=1 ttl=128 time=1.010 ms>>10008 bytes from 10.192.242.116: seq=0 ttl=128 time=0.896 ms>>>>After apply this patch, >1000ms delay disappear.>>>>Signed-off-by: Frank Li <Frank.Li@freescale.com>> > Acked-by: Fugang Duan <B38611@freescale.com>
Applied, thanks.
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