Shorie, You are not trying to create a holy war on SV(SystemVerilog) vs. SC(SystemC), aren't you? IMO, I don't think there is any big different at the end. Only thing I could tell you is that where was your home base, is that in hardware side or software side. If you are thinking the concept of the final product in either hardware or software, you can start your small bit in SV or SC, respectively. That is my 2 cents.

Hi Frank -- Well said, I did have to make a concession on one point: Using text for design input has logistical advantages such as running a diff program for managing changes.
All this ESL is so "programmers" can design hardware that has inherent parallelism that a good design will exploit. Just after the programmers find out how to really program multi-core I may become interested in that idea.
For many years there has been a way to run procedural code to solve procedural problems. It is called a COMPUTER!

The best "language" for HLS isn't a language at all, it's a graphical block diagram -- something a system engineer can use to see the datapaths and to wrap his or her mind around the signal processing that needs to be done. Think of tools like Simulink or SPW.
For those who are solving problems that are mostly control-oriented and not datapath-oriented, then the best language for HLS is none at all -- HLS isn't the right technology for those designs. Square peg, round hole.

"Plain old C++ may seem logical when first considering a move to HLS ..." What's logical about using a language, optimized for sequential computing, for HW design, where there is abundant, fine-grain, heterogeneous parallelism? Or about using a language for a fixed architecture (von Neumann), when HW design is all about finding good architectures for each app? SystemC hardly addresses or improves on these misplaced assumptions! No wonder Amit.Hermony talks about "weird coding style"! Perhaps it's time to re-examine all these misplaced assumptions and look for languages and computational models for HLS that are more tailored for HW design?

Hi Amit - you should check out the more modern offerings from Cadence and Forte. Both of these synthesize datapath and control logic together, and both synthesize untimed or loosely-timed SystemC. The technology to use HLS for production design is finally here, and companies are doing just that!

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