Friday, August 19, 2005

Embedded in you ARM: code density problem

ARM cpu is a very popular low power consumption cpu used by many embedded design. ARM use RISC design, and that's how the ARM name came from--Advance Risc Machine.There is some advantage of RISC design over CISC (eg. Intel cpu), but the code density (code size) on RISC cpu is much higher than a CISC cpu. This is not good for embedded system, because in embedded system, every byte is counted.

Why RISC cpu's code density is just higher? The simple answer is RISC cpu instruction set is fix size and some times it needs more instruction set to accomplish an action, compare with CISC cpu.

To solve the code density problem, ARM design the Thumb instruction sets. ARM was first design as 32 bit cpu (mean all instruction sets are 32 bits), Thumb instruction code are subset of the most commonly use ARM code and compress into 16 bit instruction code.

The 16 bit Thumb code will be decompress as original 32 bit instruction set before execution in cpu, since the decompress is done by hardware, there is almost no overhead for decompression.

Overall there is an improvement about 30% in code density on using Thumb code. Even though thumb code execute slower than normal ARM code, but sometimes in certain condition, Thumb may perform better than ARM, when you have slow memory access, because access of the shorter Thumb code is fater than the ARM code.

The other advantages of using thumb code is, you can have your embedded device design with a 16 bit bus, which will lower down the cost of the hardware.

All ARM9 and XScale included with Thumb technology, according to some website.

Remark:-

Below is some simple and easy undertand of the CISC and RISC design. For detail explaination of it, please refer to the web.

What is the different between CISC and RISC design?
RISC stand for Reduce Instruction Set Computing, it has less instruction set compare to CISC (Complex ...). RISC is less complicated in chip design, less transistor, smaller in size, cheaper, consume less power...
RISC will have fix size instruction set which help the pipeline design possible and easier.

What is a pipeline?
Normally machine use a cpu cycle to complete execution of an instruction. Pipeline design split each instruction into (normally) 5 stages. The cpu with pipeline design doesn't need to wait until an execution of instruction to be completed before it fetch in another instruction, once a stage of instruction is completed, the cpu will fetch in the next instruction.
Effectively with pipeline design, cpu can execute 5 instruction together (insteed of 1 after another), if these instruction does not depend on each other.
Super pipeline refer to cpu which have more than 5 stage.

What is superscalar?
Superscalar cpu have more than 1 pipeline. Normally 1 for instruction and another for data.