Intel looks to low-power, high-performance chip future

IDF Intel will this week detail how its multi-core strategy to square the circle of reducing processor power consumption without limiting performance.

Performance will be limited, of course, at the core level, but by including more cores, the overall, chip performance will rise, Intel Senior Fellow and Digital Enterprise Group CTO Steve Pawlowski said today.

Pawlowski's comments, made to reporters a day ahead of CEO Paul Otellini's Intel Developer Forum keynote, tends to confirm claims that his boss will talk up power conservation when he unveils the chip giant's next-generation processor architecture tomorrow.

Pawlowksi highlighted the current approach in which power consumption is traded off against "single-thread performance". Going forward - for which read 'Intel's next-gen architecture' - power consumption has to be constant, he said - it can't continue to rise with each new generation of processor. While that may once have meant an implicit limit to raw horsepower, multiple cores will mean that will no longer be the case.

As fabrication process shrink to 65nm and beyond, the growing transistor budgets will be used to add new functionality, again in a bid to boost performance without increasing the power draw.

Unlike AMD, which has consistently stated the need for a new architecture to enable multi-core, Intel takes a pragmatic approach, guiding the decision whether to develop single-die, multi-core parts like today's Pentium D, or multi-die, single-package chips like next year's 65nm Pentium D, 'Presler'. Which we use, he said, depends on "manufacturing cost efficiencies... best mix of product architecture and volume manufacturing capabilities".

Pawlowski also hinted at greater integration between the processor and the rest of the system, which plays into the company's platform strategy, so expect more functionality to be delivered by the CPU in co-operation with the chipset, as much to tie the two together into a platform as for architectural reasons.

Virtualisation will allow Intel to drive the number of cores without being hindered by a paucity of multi-threaded applications or the ability of the host operating system to cope with future processors containing dozens and even hundreds of cores, Pawlowski suggested.

However many cores CPUs contain over the coming years - Pawlowski said he "can see greater than four cores on the horizon" - they will all be founded on the x86 instruction set. Some elements may be shifted out of the core, he suggested, with application profiling indicating that other parts of the ISA should be brought closer to the execution units, but thanks to the crucial need for backwards compatibility Intel is "going to build x86 processors for a long time", he said. ®