Tuesday, December 30, 2008

The following paper presents the architecture, design, validation, and hardware prototyping of the main architectural blocks of main profile H.264/AVC decoder, namely the blocks: inverse transforms and quantization, intra prediction, motion compensation and deblocking filter, for a main profile H.264/AVC decoder. These architectures were designed to reach high throughputs and to be easily integrated with the other H.264/AVC modules. The architectures, all fully H.264/AVC compliant, were completely described in VHDL and further validated through simulations and FPGA prototyping. They were prototyped using a Digilent XUP V2P board, containing a Virtex-II Pro XC2VP30 Xilinx FPGA. The post place-and-route synthesis results indicate that the designed architectures are able to process 114 million samples per second and, in the worst case, they are able to process 64 HDTV frames (1080x1920) per second, allowing their use in H.264/AVC decoders targeting real time HDTV applications.

Externally, the FSM is defined by its primary inputs, outputs and the clock signal. The clock signal determines when the inputs are sampled and outputs get their new values. Internally, it means, that machine stores a state which is updated at each tick of the clock. There are two major types of FSM. If the primary outputs depend on the current state only, then it's a Moore machine.

If the primary outputs are a function of both the primary inputs and the current state, it is known as Mealy machine.

This paper gives an example for FSM with VHDL, in which ISE is used for viewing wave forms.

In this paper, a new unit intended to augment a general-purpose core that is able to perform a SAD operation was proposed. This SAD implementation can easily be extended to perform the complete SAD operation

Thursday, December 11, 2008

An implementation of an On Chip Memory (OCM) based Dual Data Rate external memory controller (OCM2DDR) for Virtex II Pro is described. The proposed OCM2DDR controller comprises Data Side OCM (DSOCM) bus interface module, read and write control logic, halt read module and Xilinx DDR controller IP core. The presented design supports 16MB of external DDR memory and 32 to 64 bits data conversion for single read and write operations. The implementation uses 1063 slices of Virtex2Pro FPGA and runs at 100 MHz. The major benets of the proposed design are high bandwidth to external memory with reduced and more predictable access times compared to the Xilinx PLB DDR controller implementation. More specially, the read and write accesses are 2,44 and 4,25 times faster, than the PLB based solution respectively.

Wolfgang Hoeflich from AMI Semiconductor described how a high-definition video scaler ASIC was quickly created using a flexible FPGA-to-ASIC conversion flow. This ensured reproduction of the FPGA functionality and enabled first time fully functional silicon supporting video resolutions up to 1080p.

TI proposed to use Digital signal processors (DSPs) handle the vast majority of video encoding applications unaided, and FPGAs as a co-processor to offload certain tasks that satisfy even the most demanding video applications.

Saturday, December 6, 2008

A tutorial for booting a fully functional operating system based on the Linux 2.4 kernel on a Xilinx University Program Virtex II-Pro based development board was presented by John H. Kelm. Furthermore, a reconfigurable hardware accelerator that can be accessed directly by applications or via a character device driver was described.

Crosstool that is a software package created by Dan Kegel that allows x86 Step 11 Linux machines to target the PowerPC405 core of the XUP board was applied.

In the MEMOCODE 2007 (the 5th), the basic design challenge was to implement a high-performance Matrix-matrix multiplication (MMM) using any HW and SW design methodology and targeting any FPGA development platform of the contestants’ choice.

In the MEMOCODE 2008, the hardware accelerated crypto sorter designs were proposed for the MEMOCODE 2008 HW/SW co-design contest. The goal was to sort an encrypted database of records partitioning the problem between a PowerPC processor and the dedicated hardware resources available on a Xilinx Virtex II Pro FPGA. The MIT team won the top honor. The code is in OPENCORE. The documentation can be downloaded from OPENCORE also.

The following link listed some the submission and the corresponding documentations: