Nodes

Description

What are nodes?

Full nodes target increased transistor density and often are where major technology changes (such as high-k/metal gate and finFET) are introduced. Nodelets, also called inter-nodes, provide further optimization of the full node.

A chip consists of transistor and interconnects. The transistors serve as a switches. The interconnects, which reside on the top of the transistor, consist of tiny copper wiring schemes that transfer electrical signals from one transistor to another.

Chips have 10 to 15 layers of copper interconnects. Generally, the second metal layer, called metal two (M2), has the tightest pitch. Historically, technology node names were based on a fraction of the tightest pitch used. However, node names have drifted away from the pitch to focus on the next node and features. Today, node names are more often considered a marketing term. Node names and specs no longer correspond to the M2 pitch, and don’t match from one vendor to the next.

At each node, chipmakers scaled the transistor specs by 0.7X. Using lithography techniques to shrink the transistor dimensions, the industry delivered a 15% performance boost at each node, plus a 35% cost reduction, a 50% area gain and a 40% power reduction. The formula worked as chipmakers marched down the various process nodes with numerical nanometer designations, such as 90nm, 65nm, 45nm and so on.

Things began to fall apart after 28nm, however. Intel continues to follow the 0.7X scaling trend. But at 16nm/14nm, others deviated from the traditional equation and relaxed the metal pitch.

More importantly, it became more difficult to scale the transistor specs after 28nm. Lithography provided the shrinks for some but not all specs. So, the cost-per-transistor-one key metric in scaling-no longer moved in a steep downward linear curve.

Moreover, fewer foundry customers could afford to move to advanced nodes amid escalating design costs. The average IC design cost for a 16nm/14nm chip is $80 million, compared to $30 million for a 28nm planar device, according to Gartner. It costs $271 million in 2019 to design a 7nm chip, according to Gartner.

Moving to finFETs at 16nm/14nm became prohibitively expensive for many customers, but not all apps require leading-edge nodes (such as IoT or automotive).

There are foundry customers that can afford the design costs at advanced nodes. They need the latest processes for traditional applications like smartphones. Other drives for advanced nodes include AI/machine learning, high-performance computing, and cryptocurrency.

To accomplish that, the semiconductor industry can’t afford to stop-or even slow down, which is why chipmakers continue to find new ways to propel chip scaling. Many of these fall under a broad category called over-scaling. Intel calls it “hyper-scaling.”

For example, starting at 22nm/20nm, chipmakers began to use 193nm immersion lithography along with various multiple patterning techniques. Aimed at reducing the pitch beyond 40nm, multiple patterning involves a process of using several lithography, etch and deposition steps in the fab.

At the same time, the structures have moved from planar to 3D. The finFET is the best example. Then, you have gate-over-contact and others. This in turn changes the materials integration mix.

Then, in another example, vendors use design technology co-optimization techniques. The idea here is to reduce the track height and cell size in a standard cell layout at each node.

Standard cells are pre-defined logic elements in a design. The cells are laid out in a grid. The track defines the height of a standard cell layout. For example, 10nm may have a 7.5-track height with a gate-pitch of 64nm and a metal pitch of 48nm, according to Imec.

Then, at 7nm, the height is reduced from 7 to 6 tracks, which results in a gate and metal pitch of 56nm and 36nm, respectively, according to Imec. This, in turn, provides a 0.52X scaling boost.

Starting at 14nm, Intel took it a step further by introducing a double-height track technology, where two sets of tracks are combined for lower overall resistance and higher performance.

It’s a matter of debate whether this technique brings scaling back on the traditional cost-per-transistor curve. But this and other techniques are becoming a necessary part of the equation.

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A transmission system that sends signals over a high-speed connection from a transceiver on one chip to a receiver on another. The transceiver converts parallel data into serial stream of data that is re-translated into parallel on the receiving end.