*Sequence announced PowerArtist-XP, described as the “first and most comprehensive analysis-driven, automatic RTL power-reduction technology within a completely integrated environment. [The tool] allows IP and SoC RTL designers, without becoming power experts, to analyze, visualize and reduce power by 10-to-60% or more within minutes on multi-million instances, with 50% fewer RTL edits, and productivity gains of 10X at a minimm … PowerArtist-XP is compatible with all standard design flows, including synthesis, simulation, and formal verification, and all leading formats and constraints including CPF, UPF, and Synopsys Design Constraints (SDC).”

*Silicon Frontline Technology announced its Fast 3D extraction software for post-layout verification has been qualified at TSMC’s 40 and 65 nanometer processes. Per the Press Release: “The tool supports TSMC's new iRCX format to improve parasitic extraction and modeling accuracy, and ensures EDA tool interoperability for high performance chip designs.”

*Synfora announced PICO Extreme Power, which the company says “is the industry’s first algorithmic synthesis tool to automatically minimize power consumption at the system-level based on a variety of techniques, including automatic multi-level clock gating insertion … Researchers at Rice University designed and evaluated a low-density parity check (LDPC) decoder for w next generation wireless handset SoC… and demonstrated a 23.5% reduction in dynamic power over an identical design using a standard flow. The Indian Institute of Science (IISc) evaluated the effectiveness of the approach using eight complex applications from video, imaging and wireless domains, [and] results indicate as much as 50% savings in dynamic power for executing a single task in some of the applications and as much as 30% savings while executing a large number of tasks.”

*Synopsys announced its DesignWare minPower Components IP, which the company says “dramatically reduce power in datapath logic compared to traditional power optimization methods. By using the DesignWare minPower Components, leading wireless, networking and DSP companies achieved power reduction of up to 48 percent in datapath logic.

*Synopsys also announced that
Achronix Semiconductor is using IC Compiler and IC Validator for designing next generation high-end FPGAs.

*Synopsys also announced that
NetLogic Microsystems has agreed to establish Synopsys as its primary EDA partner.

*TSMC announced an enhanced version of its 0.13-micron process. Per the Press Release”
“The 0.13-micron/0.11-micron family now includes a slim standard cell, SRAM and I/O with substantial area reduction … The process also adopts LD-MOS (5V~20V) on RF platforms to enable analog and power management applications. The slim platform is available in the third quarter this year while the LD-MOS on RF platforms will be available in Q4 this year.”

*Zocalo Tech announced the company’s Zazz product is now shipping. Per the Press Release: “The Zazz Front End includes an advanced incremental parser, elaborator and design viewer. An existing design or new design is read into Zazz, where it is parsed, elaborated, and graphically displayed … and then modified with the editor of choice without leaving Zazz. Zazz supports Verilog 1995, Verilog 2001 and SystemVerilog design files.”