MIT creates 64-core chip design

Boffins at MIT have emerged from their smoke filled labs with a new chip design which fixes some of the problems of parallel processing.

Developed by Prof. Daniel Sanchez and team, Swarm is a 64-core chip that includes specialised circuitry for both executing and prioritizing tasks in a simple and efficient manner.

The cunning plan is to take the onus off software developers who have always found programming for multi-cores a bit tricky.

To be fair, tricking for multi-core chips is a bit like herding cats and after you end up doing it too long your ears start to bleed. This makes programming the beasties expensive both in terms of overheads and long term psychiatric care.

This has kept parallel processing convenient only for large tasks with a few thousands of instructions. MIT’s Swarm uses specialised circuitry for delegating even the smallest of tasks efficiently and enforcing a strict priority among them. As a result, programmers can execute tasks in parallel with little overhead, making software run up to tens times faster.

Sanchez said that Swarm supports tiny tasks, as small as tens of instructions, efficiently. Supporting smaller tasks allows more parallelism, simply because there often is a lot of parallelism inside each large task.

Swarm also enforces a global order among these tasks which current multicores cannot support ordered execution efficiently. This helps deal with data conflicts.

Sanchez and team compared Swarm versions of six common algorithms to their highly-optimized parallel counterparts. Remarkably, the Swarm software executed the same task three to 18 times faster, despite requiring only about one tenth of the code. In one case, the system was able to achieve an impressive 75-fold speedup on an algorithm that computer scientists had so far failed to parallelize.

He thinks that the complexity of developing software for multi-core systems may have been one of the key reasons why chip manufacturers have been holding back on the number of cores. Swarm could now solve this problem and pave the way for general-purpose chips with a huge number of cores.

A paper describing the advance appears in the latest edition of the journal IEEE Micro.