450 mm Update on SEMI Standards -- Feb 2015

450 mm Update on SEMI Standards -- Feb 2015

SEMI Standards task forces are working
on encouraging the industry to collaborate on key issues like the
technical parameters for 450 mm silicon wafers, physical interfaces, carriers,
assembly and packaging. To date, SEMI has 13 task forces working on 450 mm and
has published nineteen (19) 450 mm standards with 15 more in the pipeline.

Here’s an update
on the newly-published SEMI 450 mm specifications as well as the other 450 mm
SEMI Standards.

450 mm
Polished Single Crystal Silicon Wafer Specification

SEMI M1-0215 – Specifications for Polished
Single Crystal Silicon Wafers was revised and published in October 2014. The
new edition includes a significant addition of a 450 mm polished single
crystal polished wafer specification and the guide for specifying 450 mm wafer for 32, 22, and 16 nm technology generation. Today, the specification
requirements for 450 mm diameter wafers are much more extensive that those of
previous smaller diameters. Standardized parameters include edge profile,
warp, conductivity, dopant, and surface conditions.

To provide
some context about history, SEMI M1 was originally published in 1980s. The
first wafer specification was 50 mm (2 inch) or about the width of credit
card. Over the years, wafers got larger and larger. In the
early 1990s, the wafer size was increased to 200 mm (8 inch), and in 1997, the
300 mm (12 inch) wafer was standardized. A 300 mm wafer may yield 2.25 times
more chips per wafer than an older 200 mm wafer. For 450 mm, 5 times more
chips per wafer can be squeezed out of a wafer compared to that of 200 mm
wafer, yet the process of making the chip takes about the same amount of time
to go through the factory. More chips are produced per wafer, which in
turns reduces the cost. Thus, wafer manufacturers and users are moving
ahead to formalize a specification for 450 mm wafer. The International Polished Wafer Task
Force will
continue to refine associated parameters to adapt to the dynamic
semiconductor industry.

Wafer Specification Standard

SEMI M1 provides the essential dimensional and certain
other common characteristics of silicon wafers, including polished wafers as
well as substrates for epitaxial and certain other kinds of silicon wafers.

SEMI M80 specifies the FOSB used to ship 450 mm wafers
from wafer suppliers to their customers (typically IC manufacturers), while
maintaining wafer quality. SEMI E162 defines the basic interface dimensions
of a load port on the semiconductor manufacturing equipment, where 450 mm FOSB
can be loaded and unloaded. The intention of SEMI E162 is to define a set of
requirement and features to enable interoperability of load ports and
carriers without limiting innovative solutions.

Physical Interfaces & Carriers Committee

This committee develops specifications to enhance the
manufacturing capability of the semiconductor industry, specifically addressing
mechanical, electrical, and special equipment specifications; and material
movement integration, including substrate support and containment structures.
For more information on committee activities, please contact Michael Tran at mtran@semi.org or Chie Yanagisawa at cyanagisawa@semi.org.

Silicon Wafer Committee

This committee develops international standards
fulfilling the requirements for commercial silicon wafers. Silicon Wafer
Committee standardization includes specifications and guides for silicon
wafers, test methods for silicon wafer quality and geometry, shipping box
related topics, wafer ID related topics, and business related topics to support
smooth communication between silicon suppliers and customers. For more
information on committee activities, please contact Kevin Nguyen at knguyen@semi.org or Naoko Tejima at ntejima@semi.org

Assembly & Packaging Committee

This committee develops specifications to enhance the
manufacturing capability of the semiconductor industry as it relates to the
packaging and assembly of the semiconductor chip, including the materials,
piece parts, and interconnection schemes, and unique packaging assemblies that
provide for the communication link between the semiconductor chip and the next
level of integration. This committee also discusses total infrastructure for
Chip to Final Set system and processes such as Testing and Design Software,
Transportation Tools, Reliability and Traceability issues, EHS issues,
Inspection methods, etc. For more information on committee activities, please
contact Paul Trio at ptrio@semi.org or Naoko Tejima at ntejima@semi.org.