LMX1501A PLL Frequency Synthesizer

1.1 GHz Frequency Synthesizer
for RF Personal Communications

General Description
The LMX1501A are high performance frequency synthesizers with integrated prescalers designed for
RF operation up to 1.1 GHz. They are fabricated using National's ABiC IV BiCMOS process.
The LMX1501A and the LMX1511 contain dual modulus
prescalers which can select either a 64/65 or a 128/129
divide ratio at input frequencies of up to 1.1 GHz. Using a
proprietary digital phase locked loop technique, the
LMX1501A's linear phase detector characteristics can
generate very stable, low noise local oscillator signals.
Serial data is transferred into the LMX1501A via a three line MICROWIRE TM interface (Data,
Enable, Clock). Supply voltage can range from 2.7V to 5.5V.
The LMX1501A feature very low current
consumption, typically 6 mA at 3V.
The LMX1501A is available in a JEDEC 16-pin surface
mount plastic package.

The simplified block diagram below shows the 19-bit data register, the 14-bit R Counter and the S Latch, and the 18-bit
N Counter (intermediate latches are not shown). The data stream is clocked (on the rising edge) into the DATA input, MSB first.
If the Control Bit (last bit input) is HIGH, the DATA is transferred into the R Counter (programmable reference divider) and the
S Latch (prescaler select: 64/65 or 128/129). If the Control Bit (LSB) is LOW, the DATA is transferred into the N Counter
(programmable divider).

PROGRAMMABLE REFERENCE DIVIDER (R COUNTER)AND PRESCALER SELECT (S LATCH)
If the Control Bit (last bit shifted into the Data Register) is HIGH, data is transferred from the 19-bit shift register into a 14-bit
latch (which sets the 14-bit R Counter) and the 1-bit S Latch (S15, which sets the prescaler: 64/65 or 128/129).

Divide Ratio of Programmable Divider

PROGRAMMABLE DIVIDER (N COUNTER)
The N counter consists of the 7-bit swallow counter (A counter) and the 11-bit programmable counter (B counter). If the Control
Bit (last bit shifted into the Data Register) is LOW, data is transferred from the 19-bit shift register into a 7-bit latch (which sets
the 7-bit Swallow (A) Counter) and an 11-bit latch (which sets the 11-bit programmable (B) Counter).