For those in fabless semiconductor or IP startup mode (or even thinking about how to start up and get funding), take a look at Paul McLellan’s report on a couple of panel sessions at the annual GSA Entrepreneurship Conference, held last Thursday, July 18 at the Computer History Museum.

Of note is that the first session’s panelists brought a variety of funding models to the table – from a traditional VC to Intel Capital to a brand new incubator on the scene – SKTA Innopartners. In fact, any of you fabless guys really should talk to Angel Orrantia at SKTA. They are focused on fabless semiconductors and enterprise software.

Below is an excerpt from Paul’s write-up:

GSA Entrepreneurship: Getting Money In and Out

Paul McLellan

by

Paul McLellan

Published on 07-18-2013 11:32 PM

This afternoon and evening I was at GSA’s entrepreneurship conference at the Computer History Museum. The first two panel sessions were essentially on getting money into companies to get them started (or growing them), and getting money out when you have built the business.

The world did not come to an end in 2012, so we can now breathe a sigh of relief and prognosticate about 2013. Or can we? Well, we can but what sort of world will it be for the EDA and IP industries in 2013? Should we even go there?

We think so. So we asked industry friends, associates, clients and media folks to ponder what industry-shattering events or breakthroughs we might see in EDA & IP this coming year.

We’ll be posting predictions from these industry visionaries over the next couple of weeks. We hope that you will find them as enlightening and entertaining as we did.

2013is all about lithography, EUV, the end of Moore’s law, 3D as a savior etc. Specifically:

• There will be a lot of discussion about the costs of 20nm since it is so much more than 28nm. It will be a very slow transition with some people going straight to 14/16nm (which is really 20nm with smaller transistors which is really 26nm with smaller transistors). Expect lots of discussion about the end of Moore’s law.

• EUV lithography will not become commercial during 2013 and so will miss the 10nm node.

• TSV-based 3D ICs will start to become mainstream. Memory on logic, and mixed digital/analog on interposer. Expect lots of discussion about “more than Moore” and how 3D is the new way for scaling.

• The death of a giant will finally take place. Nokia, still #1 only a year ago, will be dismembered. A consortium of Apple, Google and Samsung will buy the patents for billions. Huawei will buy the handset and base-station businesses for peanuts.

• Synopsys will acquire Mentor. EDA will otherwise be fairly boring with the big three being the only companies able to attack the upcoming problems that require dozens of tools to be updated, not just a new point tool inserted in the flow.

• If the IPO markets are open, Jasper, eSilicon, Atrenta and Tensilica will go public. If someone doesn’t buy them first.

Founded in 2005 by Steve Yang and Jason Xing, the company’s been busy over the last year. How? Merging with analog EDA vendor Huada Empyrean Software (HES), getting that US$28M infusion to fund global R&D, customer support and sales expansion, and working on OpenAccess-based product lines that we’ll probably see in some integrated form toward the end of 2012.

ICScape’s booth will greet attendees right at the entrance to the exhibit floor, in Booth 1602. The company’s executives will be there to:

1) talk about its technology,

2) introduce current customers (a major silicon valley Fabless IC company and a major Silicon Valley analog device company) who will also be available at the booth to share firsthand experience,…..and

Get the answers from noted EDA & IP investor Jim Hogan and Paul McLellan – industry pundit and editor-in-chief of DAC Knowledge Center – as they define the new path to prosperity in EDA & IP.

Jim and Paul will give a short presentation and steer an audience-oriented discussion on what direction startups and established companies in the EDA & IP space ought to steer if they want to show their investors the money.

What direction? SOC Realization…no longer just a vision. It’s the sweet spot in EDA & IP – where to invest and where to anchor your EDA/IP startup. So if you are contemplating starting up or re-igniting a company in the EDA & IP space, this session will help you think about how your technology will analyze and verify design concepts much earlier in the design process…at much higher levels of abstraction than before.

Where’s the opportunity? SoC Realization as a cockpit to guide a design from concept to implementation, ensuring that the design is synchronized for both the hardware and software aspects of the system’s functionality.
What’s the upshot? These changes in the SoC Realization supply chain will alter the 1) relative values of the chain’s components and 2) ability to leverage that value into profit. SoC Realization will revalue every entity in EDA & IP – the company you want to start up, or the one you’re working for.

What: Define the state and future of, and path to prosperity for EDA & IP industry.

Format will be ashort presentation, then audience-oriented discussion on what direction startups and established companies in the EDA & IP space ought to steer if they want to show their investors the money.

Why: This session will help attendees think about how their companies’ technology will have to analyze and verify design concepts much earlier in the design process…at much higher levels of abstraction than before. That’s where the money in EDA & IP will be in the coming years.

Hogan and McLellan will propose that EDA & IP companies will have to help users guide their SoC designs from concept to implementation, ensuring that the design is synchronized for both the hardware and software aspects of the system’s functionality.What’s the upshot? These changes in the SoC realization supply chain will alter the: 1) relative values of the chain’s components; 2) ability to leverage that value into profit; an 3) valuing of every entity in EDA & IP – the company you want to start up, or the one you’re working for.

A couple of weeks ago, a client asked, in essence, “why comment on articles or blogs?”

OK, so he didn’t say it exactly like that. But he did say that he’s

…struggling to figure out what really makes sense regarding the growing amount of posting by anybody and everybody….Is all this writing and blogging serving a real purpose? I’m not sure. Some blogs get recognition and response….I think most don’t.

He’s got a point. I think bloggers (indie, company and editorial) all feel, in our gut, that there’s value. But how do we measure that value? What do comments add to a blog or article? Tough one.

So I asked some of the bloggers what they thought. First off, I went to one of the longest running bloggers in EDA – Karen Bartleson. (Is it really three years, Karen? She’s at http://www.synopsys.com/blogs/thestandardsgame). She shed really insightful light on why EDA blogs get so few comments, if we compare them to consumer blogs like Yelp. And, she has her blog up on what she’s seen in the three years since she started her blog. So do take a look at Karen’s analysis of EDA blogging. I bet she’s got a take on the state of EDA blog comments.

Karen’s, along with a bunch of other bloggers’ comments on EDA blog comments gave me some trends to ponder. Some recurring points:

__the honeymoon infatuation period for EDA blogging has come…and is going. Now there needs to be some sense of longterm value.

My take…just what is “value” in terms of EDA blogs? Different from perspectives of the client, journalist and PR person.

__some indie bloggers say they see their blogs as diaries, written for themselves and interested people.

My take…everyone is aware of a larger cast of potential viewers, however. (By and large, they value comments but don’t use it as a metric of their blog’s value.)

__there are more eyeballs on the blogs than we can ascertain.

My take… however, these numbers are impossible to get for viewers and bloggers hosted by other sites. There’s no SRDS* in the EDA & IP social media world.

*SRDS was (is?) an organization that certified reader numbers for print publications so that they could charge advertising rates based on readership.

__engineers by and large are pretty quiet, shy types who rarely will comment or extend a discussion, even if they do read the blog, article and their accompanying comments.

My take…this came up a lot. I’m not sure…would their shyness prevent them from commenting? Probably. Would the relatively anonymous filter of the comment field encourage them to speak out? Potentially.

__by and large, the number of comments aren’t an accurate measure of eyeballs.

My take…lots of agreement that some sort of metric on value is reasonable, understandable. Less agreement on whether it’s needed now.

(One person compared the dilemma to the old attempt to measure column inches to value, which measures volume but doesn’t take into account perceptual, qualitative value.)

__commenting is a lot like getting a quote into an editorially-written article insofar as creating an authoritative voice that gets recognized, over time, as an industry voice to listen to…or not, depending on the content of the comment).

My take…one especially insightful editorial blogger felt that comments are a dynamic part of a living, breathing article that encompasses new perspectives with new comments and discussion.

One difference that I see is that the editor or author of the article hasn’t vetted the comment or incorporated it into his or her article. The comment is a response to the vetted article, which is the insightful editorial blogger’s point, I now see.

__the blog (and blogger) or article (and author) and its comments, to some degree, form a community onto each of themselves.

My take…this discussion got a bit abstract for me but I hear the notion. Help!

__this is a good time to talk about the expectations of each community (indie bloggers, editorial bloggers, company bloggers) and how to sync up each community so that there is value for everyone.

My take…but it’ll require the different goals and expectations of each community to somehow sync up so that each community’s efforts bring value to one another. How does that sync up with goals and expectations of customers, clients?

Of course, there’s no answer (yet) to the question about value here. The bloggers (indie, company and editorial) feel that there is value in commenting. Many of them agree that no one can measure value right now but that there ought to be some way to do so. Most everyone thinks that there is an existing, intangible value of being a voice of authority, an industry citizen.

Jim McCanny, co-founder and CEO of Altos Design Automation, Inc., is one of the most vocal voices on the use of characterization technology and what trends will be coming down the chip design pike.

I was able to catch Jim to talk about where EDA was heading and how characterization technology plays into those trends issues and chip design challenges.
……………
Ed: I was at an event, recently, where the premier investor in EDA startups cited Altos as one of his startups that did it right. Altos also got mentioned in Paul McLellan’s book, EDAgraffiti, as a company that did it right. What did Altos do that was “right?”

Jim: The things we did right? Well, I’d say that we focused on a real need – characterization run-time was too long to support the electrical analysis needs of 90nm and below. We used an experienced team and got a product to market quickly. And finally, we took only a relatively small amount of funding and relied mostly on organic growth and kept control of the company.

This last item, I think, is the one that has resonated with private investors. It made us somewhat immune to the big economic downturn in early 2009, as we had always been operating in a very fiscally responsible way.

Ed: Good point.

Jim: Finally while it was nice to be mentioned as a company who did it right, I don’t think we can be the “model” for every EDA startup. We did it right for the particular market we were going after and the current economy. Other target markets at another time might require a different approach.

Ed: I’m still fuzzy on what characterization is. Can you give me the 30 second elevator explanation?

Jim: I’d be glad to lessen some of the mystery, Ed. It’s elevating the behavior of a group of related analog transistors to a higher level of abstraction that is fundamental to digital design. For example a simple Nand gate typically has four unique analog transistors. Characterization enables each Nand gate to be modeled as a cell with equivalent timing, power and noise characteristics. That is equivalent to a 4X reduction in the circuit size to be analyzed.

Ed: So how big are we talking about?

Jim: For complex cells and blocks, there can be hundreds or even thousands of transistors and for memory instances there are often millions of transistors so the abstraction dramatically reduces the number of distinct elements that the digital design tools have to work with. Without characterization, there would be no synthesis, place and route or static timing analysis. There would be no IP reuse, basically no SoC design flow.

Ed: So characterization is obviously extremely significant to chip design. I recall that Altos started off back five or six years ago, touting the onset of statistical timing analysis (SSTA) and how characterization would be a required element in SSTA-based design flows. Adoption hasn’t really been overwhelming, yet it appears that characterization helps with static timing analysis driven chip design as well as SSTA driven chip design. What’s the difference in productivity and value that characterization brings to static timing analysis and SSTA based chip design?

Jim: SSTA is one of the areas that we saw as driving the need for faster characterization.

Ed: Now, can you remind me what SSTA is again?

Jim: Sure. SSTA is a methodology for predicting the impact of process variation of the performance of your design. It requires an accurate library that captures the effect of variation on timing (delay, slew, constraints etc.). Creating accurate models in a reasonable time frame is a big challenge. For example, the most accurate method is to use Monte-Carlo simulation but that would take thousands of times longer than “nominal” characterization (which itself can take days or even weeks). Clearly this “brute-force” approach wasn’t going to work if SSTA was to be feasible. We are able to create an SSTA library hundreds of times faster than using Monte Carlo, but still with great accuracy. Without this capability, SSTA would not get anywhere.

Ed: So is the push to lower manufacturing processes a factor in the increasing use of SSTA?

Jim: Yes! We are now starting to see serious usage at 28nm. You actually bring up a good point. There are several methods for predicting process variation such as “corner” analysis or “advanced on-chip-variation” (AOCV). Both of these solutions require either more characterization or longer characterization run-time; so our “ultra-fast” characterization technology is still very relevant whether SSTA is used or not.

Ed: As we get down to finer processes, what problems will chip/SoC designers encounter?

Jim: For most of today’s designs, the key challenge is optimizing both power and timing. Variation can play havoc with this process which is why SSTA is starting to get some traction. If you add too much margin then you can kill your power budget. However if you don’t account for variation you can have a dead part on your hands or suffer from low yield.

Ed: What else will crop up?

Jim: Another key challenge is what to do with all the available silicon real estate. The most obvious thing is to integrate more and more components on-chip. To get to market quickly this means using off the shelf IP. Making sure all the IP works together in a consistent way is tough. If you rely on pre-built models from the IP vendor you may suffer from over-guard banding or simply that the models are not up to date with the version of the process you are using. The best way around this is to either re-characterize everything to a single well defined set of characterization criteria or run an independent validation of your IP before using it.

Ed: IP quality is definitely a challenge. Harking back to that EDA investor, he seems to be saying that the valued technology will be in the front end, going forward. What’s your take and how does characterization play into that supposed trend?

Jim: There has always been value at both ends in EDA. Layout verification, layout editing, place & route, post-layout simulation, static timing analysis are all back-end solutions and major EDA markets. Sure integrating systems and software has huge potential but so does any solution that can make sure your chip will work in silicon or can improve its yield.

Ed: So what’s ahead for EDA? Is it a stagnant, mature industry, as so many people were saying a year and two years ago? Or maturing but vital in the semiconductor supply chain?

Jim: I don’t think it’s mature. There is simply too much churn in customer needs. Current tools are continuously getting enhanced and new tools are always coming on the market. Just look at the Spice simulation market. Three years ago, I think everyone would have said it’s stagnant. But look at all the new players and new capabilities that have come out in the last few years.

Ed: What do you see here?

Jim: There have been big improvements in performance, capacity, new models, new integrations into other solutions and innovative use of distributed processing.

Ed: So what is the technology development/adoption cycle for EDA?

Jim: I think EDA has cycles of about 8-10 years from the leading-edge adopters to trailing-edge users. There were a lot of new solutions around 2000 that have served the industry well for the past decade, but are now aging. Obviously, sometimes the EDA industry gets ahead of itself and has to go through a few lean years like we have just done. The danger is that when the industry needs new tools and solutions they won’t be there, as the past year and half has been pretty brutal and instead of investing in the future, many of the big EDA companies had to make cuts. Key areas such as analog automation, IP integration and verification and system and software design still need a lot of work.

Ed: Keeping in mind that there could be a reduction in new tools, what technologies do you see rising above the others in terms of user need, value added and just plain necessary for, say, 28nm designs that are full of complex IP blocks, many of which don’t integrate easily with one another?

Jim: Tools that truly enable IP integration and verification. By verification I don’t mean “will the IP work stand-alone” but “will it work as desired in the integrated system,” e.g. at the voltage levels being used, at the process corners being used, with the expected amount of process variation etc.

Ed: And what issues will we see rise to crisis level in power? Timing? How will they get fixed?

Jim: Power is really dynamic but timing is usually analyzed statically. How do you really model dynamic, temporal effects such as IR drop, crosstalk and substrate noise using static methods without gross “worst-casing”. In addition noise effects can cause very analog like waveforms that break the assumptions of today’s delay models that assume a linear or piecewise linear ramp. There is room for better timing models and smarter ways to statistically model the impact of dynamic effects like noise and IR drop and possibly hybrid static-dynamic analysis tools.

Ed: So what’s ahead for characterization technology? For Altos?

Jim: Our focus is in “enabling a world of IP.” By that, we mean that we want to make reuse of any form of IP highly productive, be it cells, complex I/Os, embedded memory or custom blocks. To do this we are working on bringing the same kind of automation and performance we have brought to complex cell characterization to IP block characterization. We also see characterization as more than model creation but also as a means to validate IP. A characterization tool tells you how the block will perform under a range of different conditions but doesn’t tell you if it performs as expected or how much margin you have to deal with the “unexpected”. We are on a path to change that.

Ed: Seems promising! I look forward to hearing more on this front down the road. Thanks, Jim, for taking time out of your busy day to share your viewpoints on these topics.

Steve Leibson in Leibson’s Law did a comprehensive and insightful job of covering the Hogan/McLellan entrepreneurial workshop in his blog on Wednesday. Thank you, Steve! And thank you, Jim and Paul, for enlightening us on how to start up an EDA company.

Jim and Paul made some very hard-hitting points in this valuable how-to workshop (at DVCon Tuesday night), one of which was emphasized by Leibson: “Sizzle is the highest leverage marketing point” said Hogan.

Afterward, a couple of attendees shared with us that “there is no sizzle in EDA!” And “as we all know, many engineering driven startups (even some engineering driven mature companies) undervalue or don’t understand the importance of sizzle – a big mistake.”

What is sizzle? How do you define it?

Is there sizzle in EDA? Why or why not? Who has it, if there is sizzle in EDA?