INTRODUCTION TO MC 68HC11 MICROCONTROLLER:

INTRODUCTION:

INTRODUCTION Motorola Inc ,one of the pioneers in microcontroller manufacturing has introduced this 8-bit microcontroller M68HC11 in the year 1985 and it is descended from the Motorola 6800 microprocessor. Now it is produced by Freescale Semiconductors. It is a CISC microcontroller , optimized for low power consumption and high-performance operation at bus frequencies up to 4 MHz .

Contd..:

Contd.. The 68HC11 devices are more powerful and more expensive than the 68HC08 microcontrollers, and are used in barcode readers, hotel card key writers, amateur robotics, and various other embedded systems. The MC68HC11A8 was the first MCU to include CMOS EEPROM.

Series of M68HC11:

Series of M68HC11 The 68HC11 is available in various series as below A series - basic model. D series - economical alternative, less memory, peripherals. E series - has wide range of I/O capabilities. F series - higher speed, extra I/Os.

OPERATING MODES:

OPERATING MODES The 6811 can operate in one of the four modes : Single-chip mode: uses internal memory for program & data. Expanded mode :allows for use of external memory. Bootstrap mode: used to load programs into RAM. Test mode : used by Motorola to test the chip is operation

Single chip (MODA=0, MODB=1) :

Single chip (MODA=0, MODB=1) i . No external address and data bus functions CPU can only access on-chip memory ii.Ports B and C are general purpose parallel I/O iii.All software needed to control MCU must be in internal memory iv. On reset, execution begins at address #E000

Bootstrap (MODA=MODB=0) :

Bootstrap (MODA=MODB=0) i . On power up or reset, the program in the bootstrap ROM is executed ii.CPU waits for a 256-byte program segment to be downloaded through the serial link and stored starting at address #0000 iii.Execution then begins at address $0000 iv.Permits wide variety of programs to be downloaded

Test Mode (MODA=1, MODB=0) :

Test Mode (MODA=1, MODB=0) i.Primarily used to test the chip by the manufacturer ii. Overrides some automatic protection mechanisms

SALIENT FEATURES:

SALIENT FEATURES The HCMOS MC68HC11 is an advanced 8-bit MCU with numerous on-chip peripheral capabilities. Up to 10MIPS Throughput at 10MHz 256 Bytes of RAM , 512 Bytes of In-System Programmable EEPROM and Programming Lock. Eight channel 8-bit Analog to Digital Convertor One serial peripheral interface, with a speed up to 1M

Contd…:

Contd … The MC68HC11 is available in two packages . One is 48-pin dual inline package (DIP) and the other is the 52 Pin Plastic Leaded Chip Carrier(PLCC) known as Lead quad pack. In the 48 pin DIP package 38 pins are available for I/O functions.(34 I/O lines+ 2 interrupt lines + 2 hand shake control lines). Similarly in a 52 PLCC pack 42 pins are meant for different I/O functions, and the remaining are used for interrupt and handshake signals.

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68HC 11 ARCHITECTURE:

68HC 11 ARCHITECTURE It is based on HCMOS Technology and has a common internal bus for the address and data of 8-bits. It has an MCU clock whose frequency can be educed to zero. As the MCU is completely MOSFET based the power dissipation is negligible in stop or start states.So,this is optimized for lowpower consumption and high performance operation.

Block Diagram Of MC68HC11:

Block Diagram Of MC68HC11

CPU FEATURES:

CPU FEATURES An 8M.Hz XTAL(external clock) with 2 M.Hz clock related operations. A 16-bit program counter that loads a powerup value from a reset vector address 0xFFFE – 0xFFFF Two 8- bit Accumulators A and B work as general purpose registers. They can be concatenated as a 16-bit double accumulator [D]. Two 16-bit Index registers Ix and Iy can be used as pointers to memory locations and hold the 16 bit addresses of memory locations .

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Contd.. It has a multiplexed address and data bus. One 16 –bit stack pointer ,which decreases by 1 after the push of each byte. Two external interrupts IRQ ,XIRQ .One of the is can be configured as non- maskable external interrupts like NMI in 80196. Although this is an 8-bit processor ,it has some 16-bit instructions.( ADD,Sub,shift and rotate)

68HC11 Registers :

68HC11 Registers The MC68HC11 microcontroller has a rich set of registers and they are classified into two categories : CPU registers and I/O registers. The CPU Registers are shown in the next slide . A and B are the two 8-bit registers called general purpose accumulators which are used to perform most of the arithmetic operations. These two accumulators can be concatenated to form a 16-bit accumulator which is known as double accumulator “D”. This accumulator is used for 16 bit operations .

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Contd.. Index registers (IX and IY).Two 16-bit registers used mainly in addressing memory operands. They normally used to hold addresses of 16-bit memory locations.These registers are also , some times used for them for 16-bit computation also. Stack Pointer (SP):Stack is a first in first out data structure.This 16-bit stack pointer register hold the address of the stack top.

REGISTER ORGANISATION:

REGISTER ORGANISATION

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Program Counter(PC): It is a 16-bit register which stores the address of the next instruction to be executed. The 68HC11fetches the instruction one byte at a time and increments the PC by 1 after after fetching each instruction byte. After the execution of an instruction the PC is incremented by the number of bytes of the executed instruction.

Condition Code Register (CCR):

Condition Code Register (CCR) This is an 8-bit register used to keep track of the program execution status , control the execution of conditional branch instructions and enable/disable the interrupt handling . This register contains five status indicators, two interrupt masking bits, and a STOP disable bit. The register is named for the five status bits since that is the major use of the register .

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Contd.. These status flags reflect the results of arithmetic and other operations of the CPU as it performs instructions. The five flags are half carry (H),negative (N), zero (Z), overflow (V), and carry/borrow (C). The half-carry flag, which is used only for BCD arithmetic operations is only affected by the add accumulators A and B (ABA), ADD, and add with carry (ADC) addition instructions

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Contd.. The N, Z, V, and C status bits allow for branching based on the results of a previous operation. Simple branches are included for either state of any of these four bits. The H bit indicates a carry from bit 3 during an addition operation. This status indicator allows the CPU to adjust the result of an 8-bit BCD addition so it is in correct BCD format, even though the add was a binary operation. This H bit, which is only updated by the ABA, ADD, and ADC instructions, is used by the DAA instruction to compensate the result in accumulator A to correct BCD format .

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Contd.. The N bit reflects the state of the most significant bit (MSB) of a result. For twos complement, a number is negative when the MSB is set and positive when the MSB is 0. The N bit has uses other than in twos-complement operations. By assigning an often tested flag bit to the MSB of a register or memory location, the user can test this bit by loading an accumulator.

Contd…:

Contd … The Z bit is set when all bits of the result are 0s. Compare instructions do an internal implied subtraction, and the condition codes, including Z, reflect the results of that subtraction. A few operations (INX, DEX, INY, and DEY) affect the Z bit and no other condition flags.

Contd…:

Contd … The C bit is normally used to indicate if a carry from an addition or a borrow has occurred as a result of a subtraction. The C bit also acts as an error flag for multiply and divide operations. Shift and rotate instructions operate with and through the carry bit to facilitate multiple-word shift operations .

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Contd.. The STOP disable (S) bit is used to allow or disallow the STOP instruction. Some users consider the STOP instruction dangerous because it causes the oscillator to stop; however, the user can set the S bit in the CCR to disallow the STOP instruction. If the STOP instruction is encountered by the CPU while the S bit is set, it will be treated like a no-operation (NOP) instruction, and processing continues to the next instruction.

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Contd.. The interrupt request (IRQ) mask (I bit) is a global mask that disables all maskable interrupt sources. While the I bit is set, interrupts can become pending and are remembered, but CPU operation continues uninterrupted until the I bit is cleared. After any reset, the I bit is set by default and can be cleared only by a software instruction. When any interrupt occurs, the I bit is automatically set after the registers are stacked but before the interrupt vector is fetched. After the interrupt has been serviced, an RTI instruction is normally executed, restoring the registers to the values that were present before the interrupt occurred. The XIRQ mask (X bit) is used to disable interrupts from the XIRQ pin. After any reset, X is set by default and can be cleared only by a software instruction

Addressing Modes:

Addressing Modes Addressing modes are used to specify the operands needed in an instruction. The M68HC11 CPU supports SIX addressing modes. They are Immediate addressing mode Direct addressing Extended addressing Indexed (with either of two 16-bit index registers and an 8-bit offset) Inherent and Relative addressing mode.

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Contd … Each of the addressing modes (except inherent) results in an internally generated, double-byte value referred to as the effective address. This value appears on the address bus during the external memory reference portion of the instruction All bit-manipulation instructions use immediate addressing to fetch a bit mask, and branch variations use relative addressing mode to determine a branch destination.

Immediate (IMM):

Immediate (IMM) In the immediate addressing mode, the actual argument is contained in the byte(s) immediately following the instruction in which the number of bytes matches the size of the register. These instructions are two, three, or four (if pre byte is required) bytes. In this case, the effective address of the instruction is specified by the character # sign and implicitly points to the byte following the opcode . The immediate value is limited to either one or two bytes, depending on the size of the register involved in the instruction.

Character prefixes:

Direct Mode (DIR):

Direct Mode (DIR) In the direct addressing mode, the least significant byte of the effective address of the instruction operand appears in the byte following the opcode The high-order byte of the effective address is assumed to be $00 and is not included in the instruction. This limits use of the direct mode to operands in the $0000-$00FF area of the memory.

Examples:

Examples ADDA $00 ; adds the value stored at the memory location with the effective address $0000 to accumulator A. SUBA $20 ;subtracts the value stored at the memory location whose address is $0020 from accumulator A. LDD $10 ; loads the contents of the memory locations at $0010 and $0011 into double accumulator D, where the contents of the memory location at $0010 are loaded into accumulator A and those of the memory location at $0011 are loaded into accumulator B.

Extended Mode (EXT):

Extended Mode (EXT) In the extended addressing mode, the effective address of the operand appears explicitly in the two bytes following the op code EX: LDAA $1003 ; loads the 8-bit value stored at the memory location with effective address $1003 into accumulator A.

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Contd … LDX $1000 ; loads the 16-bit value stored at the memory locations with the effective addresses $1000 and $1001 into the index register X. The byte at $1000 will be loaded into the upper byte of X and the byte at $1001 will be loaded into the lower byte of X. ADDD $1030 ; adds the 16-bit value stored at the memory locations with the effective addresses $1030 and $1031 to double accumulator D.

Indexed Mode (INDX, INDY):

Indexed Mode (INDX, INDY) In the indexed addressing mode, one of the index registers (X or Y) is used in calculating the effective address. So, the effective address is variable and depends on the current contents of the index register X (or Y) and a fixed, 8-bit unsigned offset contained in the instruction. Because the offset byte is unsigned, only positive offsets in the range from 0 to 255 can be represented. If no offset is specified, the machine code will contain $00 in the offset byte.

Examples:

Examples ADDA 10,X ; adds the value stored at the memory location pointed to by the sum of 10 and the contents of the index register X to accumulator A. Each of the following instructions subtracts the value stored at the memory location pointed to by the contents of index register X from accumulator A SUBA 0,X SUBA ,X

Inherent Mode (INH):

Inherent Mode (INH) In the inherent mode, everything needed to execute the instruction is encoded in the opcode . The operands are CPU registers and thus are not fetched from memory. These instructions are usually one or two bytes. Exs : ABA ; adds the contents of accumulator B to accumulator A. INCB ; increments the value of accumulator B by 1. INX ; increments the value of the index register X by 1.

Relative Mode (REL):

Relative Mode (REL) The relative addressing mode is used only for branch instructions. Branch instructions, other than the branching versions of the bit- manipulation instructions, generate two machine-code bytes, one for the opcode and one for the branch offset. The branch offset is the distance relative to the first byte of the instruction immediately following the branch instruction. The branch offset has a range of 128 to 127 bytes.

Example:

Example BEQ $e164 $e100 ADDA #10 ... $e164 DECB ... The 68HC11 will branch to execute the instruction DECB if the Z bit in the CCR register is 1, when the instruction BEQ $e164 is executed.

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Contd.. Port A has three fixed-direction input pins, four fixed-direction output pins, and one bidirectional pin. The direction of the PA7 pin is controlled by the data direction register A bit 7 control bit (DDRA7) in the pulse accumulator control (PACTL) register. Port A data is read from and written to the PORTA register.

Ports B & PORT C:

Ports B & PORT C Port B is a general-purpose, 8-bit, fixed-direction output port. Writes to the port B register (PORTB) cause data to be latched and driven out of the port B pins. Port C is a general-purpose, 8-bit, bidirectional I/O port. The primary direction of data flow at each port C pin is independently controlled by a corresponding bit in the data direction control register for port C (DDRC ).

PORT D:

PORT D Port D is a general-purpose, 6-bit, bidirectional data port . Two port D pins are alternately used by the asynchronous serial communications interface (SCI) subsystem. The remaining four port D pins are alternately used by the synchronous serial peripheral interface (SPI) subsystem . The primary direction of data flow at each of the port D pins is selected by a corresponding bit in the data direction register for port D (DDRD).Port D can be configured for wired-OR operation by setting the port Dwired -OR mode control bit (DWOM) in the SPI control register (SPCR).

PORT E:

PORT E Port E is an 8-bit, fixed-direction input port PE7-PE0. Port E pins alternately function as analog-to-digital (A/D) converter channel inputs. Port E input buffers are specially designed so they will not draw excessive power-supply currents when their inputs are driven by intermediate levels. The features of these ports are given in a table in the next slide

Features of I/O Ports:

Features of I/O Ports

RESETS AND INTERRUPTS:

RESETS AND INTERRUPTS Reset is used to force the microcontroller unit (MCU) to assume a set of initial conditions and to begin executing instructions from a predetermined starting address. For most practical applications, the initial conditions take effect almost immediately after applying an active-low level to the RESET pin. Some reset conditions cannot take effect until/unless a clock is applied to the external clock input (EXTAL) pin.

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Contd.. Once the reset condition is recognized, internal registers and control bits are forced to an initial state. These initial states, in turn, control on-chip peripheral systems to force them to known start-up states. Most of the initial conditions are independent of the operating mode. After reset, the CPU fetches the restart vector from locations $FFFE,FFFF ($BFFE,BFFF if in special test or bootstrap mode) during the first three cycles and begins executing instructions.

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Contd.. The stack pointer and other CPU registers are indeterminate immediately after reset; however, the X and I interrupt mask bits in the CCR are set to mask any interrupt requests. Also, the S bit in the CCR is set to disable the stop mode. After reset, the RAM and I/O mapping (INIT) register is initialized to $01, putting the 256 bytes of random-access memory (RAM) at locations$0000–$00FF and the control registers at locations $1000–$103F. The8-Kbyte read-only memory (ROM) and/or the 512-byte EEPROM may or may not be present in the memory map because the two bits that enable them in the configuration control (CONFIG) register are EEPROM cells not affected by reset or power-down .

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Contd.. During reset, the timer system is initialized to a count of $0000. The prescaler bits are cleared, and all output-compare registers are initialized to $FFFF. All input-capture registers are indeterminate after reset. The timer overflow interrupt flag and all eight timer function interrupt flags are cleared. All nine timer interrupts are disabled since their mask bits are cleared.

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Contd.. The real-time interrupt flag is cleared, and automatic hardware interrupts are masked. The rate control bits are cleared after reset and may be initialized by software before the real-time interrupt system is used. The pulse accumulator system is disabled at reset so that the pulse accumulator input (PAI) pin defaults to being a general-purpose input pin.

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Contd … The computer operating properly (COP) watchdog system is enabled if the NOCOP control bit in the CONFIG register (EEPROM cell) is clear and disabled if NOCOP is set. The COP rate is set for the shortest duration timeout. The reset condition of the SCI system is independent of the operating mode. At reset, the SCI baud rate is indeterminate and must be established by a software write to the BAUD register. All transmit and receive interrupts are masked, and both the transmitter and receiver are disabled so the port pins default to being general-purpose I/O lines.

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Contd.. The SPI system is disabled by reset. The port pins associated with this function default to being general-purpose I/O lines. The A/D converter system configuration is indeterminate after reset. The conversion complete flag is cleared by reset. The A/D power-up (ADPU) bit is cleared by reset, disabling the A/D system.

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Contd.. The EEPROM programming controls are all disabled so the memory system is configured for normal read operation. A few registers are not forced to a startup condition as a result of reset. Since these registers do not affect the starting conditions at MCU pins. One such register is the main-timer input-capture register. Since these registers are not useful until after an input capture occurs, it is not important to force them to a startup state during reset.

Power-On Reset (POR):

Power-On Reset (POR) The POR is only intended to initialize internal MCU circuits. As VDD is applied to the MCU, the POR circuit triggers and initiates a reset sequence. POR triggers an internal timing circuit that holds the RESET pin low for 4064 cycles of the internal PH2 clock. The MCU does not advance past this reset condition until a clock is present at the EXTAL pin long enough for these 4064-cycle PH2 clocks to be detected. The internal POR circuit will not retrigger unless VDD has discharged to 0 V; therefore, the internal POR circuit is not suitable as a power-loss detector.

COP Watchdog Timer Reset:

COP Watchdog Timer Reset The COP watchdog timer system is intended to detect software processing errors. When the COP is being used, software is responsible for keeping a free-running watchdog timer from timing out. If the watchdog timer times out, it is an indication that software is no longer being executed in the intended sequence; thus, a system reset is initiated.

External Reset:

External Reset In addition to the internal sources, reset can be forced by applying a low level to the RESET pin. The resulting reset sequence is identical to the internal causes. Upon recognition of the reset request, internal logic turns on an internal N-channel device, which actively holds the RESET pin low for about four cycles .

Interrupt Process:

Interrupt Process The CPU in a microcontroller sequentially executes instructions. In many applications, it is necessary to execute sets of instructions in response to requests from various peripheral devices. These requests are often asynchronous to the execution of the main program. Interrupts provide a way to temporarily suspend normal program execution so the CPU can be freed to service these requests. After an interrupt has been serviced, the main program resumes as if there had been no interruption

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Contd.. The instructions executed in response to an interrupt are called the interrupt service routine. These routines are much like subroutines except that they are called through the automatic hardware interrupt mechanism rather than by a subroutine call instruction, and all CPU registers are saved on the stack rather than just saving the program counter. Interrupts can be enabled or disabled by mask bits (X and I) in the CCR and by local enable mask bits in the on-chip peripheral control registers.

Return from Interrupt:

Return from Interrupt When an interrupt has been serviced as needed, the return-from interrupt(RTI) instruction terminates interrupt processing and returns to the program that was running at the time of the interruption. During servicing of the interrupt, some or all of the CPU registers will have changed. To continue the former program as if it had not been interrupted, the registers must be restored to the values present at the time the former program was interrupted. The RTI instruction accomplishes this by pulling (loading) the saved register values from the stack memory. The last value to be pulled from the stack is the program counter, which causes processing to resume where it was interrupted .

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Contd.. The MC68HC11 has 21 independent interrupts . In this,6 are non- maskable and 15 are maskable . The three high priority interrupts are RESET , HIRQ and IRQ .

TIMERS :

TIMERS The MC68H11 has one 16-bit free-running 16-bit counter with a 4-stage programmable pre- scaler . A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter. Three independent input-capture functions are used to automatically record (latch) the time when a selected transition is detected at a respective timer input pin. Five output-compare functions are included for generating output signals or for timing software delays.

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Contd.. The timer subsystem involves more registers and control bits than any other subsystem on the MCU. Each of the three input-capture functions has its own 16-bit time capture latch (input-capture register) and each of the five output-compare functions has its own 16-bit compare register. All timer functions, including the timer overflow and RTI, have their own interrupt controls and separate interrupt vectors.

SELF PROTECTION:

SELF PROTECTION All pins of M68HC11 have internal inherent diode clamps to Vss .This MCU has certain special internal circuit arrangements such that the MCU can operate at V DD 7 volts with out damage . The COP watch dog timer will always provide protection from any malfunction. The watch dog timer also provides self protection to the MCU from damage.