Panelists look at IP quality versus design productivity

A fundamental problem in the industry is to analyze and implement the tradeoffs between improving IP quality and losing design productivity.

PARIS  A fundamental problem in the industry is to analyze and implement the tradeoffs between improving IP quality and losing design productivity. .

During a panel discussion at the IP-ESC 2009 Conference last week in Grenoble, France, IP buyers and sellers confronted experiences and issues.

Franois Rémond, director, CAD & design methodology at STMicroelectronics NV (Geneva, Switzerland), recognized that, over the last few years, SoC design productivity raised thanks to IP-based integration methods. At the same time, he observed that IP quality improved with costly investments in design for reuse methods.

Two points must be highlighted, he continued.

Firstly, debugging an IP issue at the SoC level is extremely costly because of the nature of the integration, the lack of observable points and the possible lack of deep IP understanding from the SoC team.

Secondly, Rémond noted that the IP functionality issue can be a killer for SoC time-to-market.

Looking more closely at quality versus productivity, Rémond declared: "The quality of the IP is a must to deal with complex SoC integration. There is no compromise there."

He continued: "Complex IPs are now hardware/software codesigns, and we need to integrate software quality metrics in the picture. The quality of integration documentation is key. And, transforming an ad-hoc RTL block into a reusable IP has a high cost. It is better to start with reuse in mind."

Finally, Rémond called for further improvements in the way quality is measured and communicated.