Intel Stratix 10 Overview

Intel®
Stratix® 10 devices support IEEE Std. 1149.1 BST and IEEE Std. 1149.6 BST. When you perform Boundary-Scan Test
(BST), you can test pin connections without using physical test probes and capture
functional data during normal operation. The boundary-scan cells (BSCs) in a device can
force signals onto pins, or capture data from pin or core logic signals. Forced test
data is serially shifted into the BSCs. Captured data is serially shifted out and
externally compared to expected results.

Intel®
Stratix® 10 devices are implemented using
multiple die inside the package, connected together using EMIB (Embedded Multi-die
Interconnect Bridge) technology. The multiple die implementation is transparent to BST.
There is a single boundary-scan chain for the complete device that includes every die
inside the package.

You can perform BST on
Intel®
Stratix® 10 devices before, after, and during
configuration.

Intel Stratix 10 JTAG BST Architecture

JTAG Circuitry Functional Model

Instruction register—determines which action to perform and which data
register to access.

Bypass register (1-bit long data register)—provides a
minimum-length serial path between the TDI and TDO pins.

Boundary-scan register—shift register composed of all the BSCs of the
device.

Figure 1. JTAG Circuitry Functional Model

Test access port (TAP) controller—controls the JTAG
BST.

TMS and TCK pins—operate the TAP controller.

TDI and TDO pins—provide the serial path for the
data
and instruction registers.

Note:TRST pin is not available in
Intel®
Stratix® 10 devices.

JTAG Pins

Table 1. JTAG Pin Descriptions

Pin

Function

Description

TDI

Serial input pin for:

Instructions

Test data

Programming data

TDI is
sampled
on the rising edge of TCK
and should be driven on the falling-edge of TCK.

TDI pins have internal weak
pull-up resistors.

TDO

Serial output pin for:

Instructions

test data

Programming data

TDO is driven on the
falling edge of TCK
and should be sampled on the rising-edge of TCK.

The pin is tri-stated if data is not being
shifted out of the device.

TMS

Input pin that provides the
control signal to determine the transitions of the TAP controller
state machine.

TMS is sampled on the rising edge of
TCK
and should be driven on the falling-edge of TCK.

TMS pins have internal weak
pull-up resistors.

TCK

The clock input to the BST
circuitry.

—

IEEE Std. 1149.1 Boundary-Scan Register

The boundary-scan register is a large
serial shift register that uses the TDI pin as an input
and the TDO pin as an output.
The boundary-scan
register consists of boundary-scan cells for each IO pin and padding
bits. You can use the boundary-scan register to test external pin connections or to capture internal
data.

Boundary-Scan Cells of Intel Stratix 10 Device I/O Pin

The
Intel®
Stratix® 10 device 3-bit BSC consists of the following registers:

Capture registers—Connect to
internal device data through the
OUTJ,
OEJ, and
PIN_IN signals.

Update registers—Connect to
external data through the
PIN_OUT and
PIN_OE signals.

The TAP controller generates the global control signals for the IEEE Std. 1149.1 BST registers (SHIFT, CLOCK, and UPDATE) internally. A decode of the instruction register
generates the MODE signal.

The data signal path for the boundary-scan register runs from the serial
data in (SDI) signal to the serial data out
(SDO) signal. The scan register begins at the
TDI pin and ends at the
TDO pin of the device.

IEEE Std. 1149.6 Boundary-Scan Register

The BSCs for HSSI transmitters (GXB_TX[p,n]) and receivers/input clock buffers (GXB_RX[p,n])/(REFCLK[p,n])
in
Intel®
Stratix® 10
devices are different from the BSCs for the I/O pins.

Note: You have to use the EXTEST_PULSE JTAG instruction for AC-coupling on HSSI transceiver. Do not use the EXTEST JTAG instruction for AC-coupling on HSSI transceiver. You can perform AC JTAG on
the
Intel®
Stratix® 10
device before, after, and during configuration.

Figure 6. UIB and eSRAM BSC with IEEE Std. 1149.1 BST Circuitry
for
Intel®
Stratix® 10 DevicesThe differential reference clock input pins for UIB and eSRAM are sharing the BSC
per pair as shown in this figure. The capture value (DATAIN) would
be invalid if one or both differential inputs are abnormal.

Allows
you to capture and examine a snapshot of signals at the device
pins during normal device operation and permits an initial data
pattern to be an output at the device pins. Allows
you to test the external circuit and

Use
this instruction to preload the test pattern into the update
registers before loading the EXTEST instruction.

EXTEST

00 0000 1111

board-level interconnects by forcing a
test pattern at the output pins, and capturing the test results
at the input pins. Forcing known logic high and low levels on
output pins allows you to detect opens and shorts at the pins of
any device in the scan chain.

The
high-impedance state of EXTEST
is overridden by bus hold and weak pull-up resistor features.

BYPASS

11 1111 1111

Places
the 1-bit bypass
register between the TDI and
TDO pins. During normal
device operation, the 1-bit bypass register allows the BST data to pass
synchronously through the selected devices to adjacent devices.

You
will get a '0' reading in the bypass register out.

USERCODE

00 0000 0111

Selects the 32-bitUSERCODE register and places
it between the TDI and TDO pins to allow serial shifting
of USERCODE out of TDO.

The 32-bit USERCODE is a
programmable user-defined pattern.

IDCODE

00 0000 0110

Identifies the devices in a
JTAG chain. When the IDCODE
register is selected by the IR then in the CAPTURE_DR
state,
the IDCODE instruction places
the 32-bit Device ID register between the TDI and TDO pins to allow serial shifting of Device ID out
of TDO.

Selects the
Device
ID register and places it between the TDI and TDO pins to allow serial shifting of
Device
ID register out of TDO.

IDCODE instruction is the default instruction in
the Test-Logic-Reset state.

HIGHZ

00 0000 1011

Sets
all user I/O pins to an inactive drive state.

Places
the 1-bit bypass
register between the TDI and
TDO
pins.

If you
are testing the device after configuration, the programmable
weak pull-up resistor
or the bus hold feature overrides the HIGHZ value at the pin.

CLAMP

00 0000 1010

Places
the 1-bit bypass
register between the TDI and
TDO
pins.

If you
are testing the device after configuration, the programmable
weak pull-up resistor
or the bus hold feature overrides the CLAMP value at the pin. The CLAMP value is the value stored in
the update register of the boundary-scan cell (BSC).

EXTEST_PULSE

00 1000 1111

Enables board-level connectivity
checking between the transmitters and receivers that are AC coupled by
generating three output transitions:

Driver
drives data on the falling edge of TCK in the UPDATE_IR/DR state.

Driver
drives inverted data on the falling edge of TCK after entering the RUN_TEST/IDLE state.

Driver
drives data on the falling edge of TCK after leaving the RUN_TEST/IDLE state.

EXTEST_TRAIN

00 0100 1111

Behaves the same as the EXTEST_PULSE instruction except that the output
continues to toggle on the TCK falling
edge provided that the TAP controller is in the RUN_TEST/IDLE state.

Intel Stratix 10 I/O Voltage for JTAG Operation

The TCK pin has an internal weak pull-down
resistor, while the TDI, and TMS pins have internal weak pull-up
resistors.
The VCCIO_SDM
supply powers the TDI, TDO, TMS, and TCK pins.

The JTAG pins support 1.8 V
TTL/CMOS I/O standard.

Note: For any voltages higher than 1.8 V, you
have to use level shifter. The output voltage of the level shifter for the JTAG pins
must be the same as set for the VCCIO_SDM
supply.

Table 5. TDO Output Buffer

TDO Output Buffer
Condition

Voltage (V)

VCCIO_SDM

1.8

Performing Intel Stratix 10 Boundary-Scan Testing

You can issue BYPASS, IDCODE, and SAMPLE JTAG
instructions before, after, or during configuration without having to interrupt
configuration.

To interrupt configuration in order to perform BST you can either hold
nCONFIG low or issue the following sequence via JTAG: an IR scan updating with 0x201
(COMMAND) followed by two 34 bit DR scans updating with 34’h3_0000_0000 then
35’h1_0000_0005. Once configuration is interrupted, you can issue other JTAG
instructions to perform BST.

If you design a board for JTAG configuration of
Intel®
Stratix® 10 devices, consider the connections for the dedicated
configuration pins.

Note: For SoC device, you can only see
the FPGA TAP controller in the JTAG chain upon device power up. The TAP controller for
the HPS component only appears in the JTAG chain once the device is configured with a
programming file/design containing the HPS component. You need to include the
information about the HPS component when generating the test patterns for boundary-scan
testing. You can download the boundary-scan description language (BSDL) file for the SoC
device from the
Intel®
Stratix® 10
Device BSDL Files page.

Note: Dummy bits exist in the boundary-scan
register during boundary-scan operations in
Intel®
Stratix® 10 devices. However, these dummy bits do not have any impact
on the pins. The dummy bits appears on the TDO
immediately before the corresponding boundary-scan register segment and have an unknown
value X, which can be either a 0 or 1.

Enabling and Disabling Intel Stratix 10 BST Circuitry

Enabling BST Circuitry

The IEEE Std. 1149.1 BST circuitry is enabled after
the device is configured. If you need to perform the boundary-scan test prior to
configuration, you must execute the MISCCTRL instruction upon
device power up to enable the BST circuitry.

4 The JTAG pins are
dedicated. Software option is not available to disable JTAG in
Intel®
Stratix® 10 devices.

Intel Stratix 10 IEEE Std. 1149.1 BST Guidelines

Consider the following guidelines when you perform BST with
IEEE Std. 1149.1 devices:

If
the first two bits shifted out of the instruction register in the SHIFT_IR state are not 1
and then
0,
the TAP controller did not reach the proper state. To solve this problem, try one of
the following procedures:

Verify that the TAP
controller has reached the SHIFT_IR state correctly. To advance
the TAP controller to the SHIFT_IR state, return to the TEST-LOGIC-RESET state and send the 01100 code to the TMS
pin.

Check the
connections to the VCC, GND, JTAG, and
dedicated configuration pins on the device.

Perform a
SAMPLE/PRELOAD test cycle
before the first
EXTEST test cycle to ensure that known data is present
at the device pins when you enter
EXTEST mode. If the
OEJ update register contains 0, the data in the
OUTJ update register is driven out. The state must be
known and correct to avoid contention with other devices in the system.

Do not perform EXTEST testing during in-circuit reconfiguration because EXTEST is not supported during in-circuit
reconfiguration.

After configuration, you
cannot test any pins in a differential pin pair. To perform BST after
configuration, edit and redefine the BSC group that correspond to these
differential pin pairs as an internal cell.