June 19, 2012 AT 10:41 pm

Freescale Announces $13 ARM Cortex-M0+ Microcontroller Board

Above: the Kinetis L Microcontroller board from Freescale. The board features a Cortex-M0+ ARM processor, a suspiciously familiar minty-fresh board silhouette, and headers that remind me of summers in Ivrea. From EDA360:

There are two major reasons for reading this blog post:

A 32-bit microcontroller that sells for as little as $0.49 in 10K quantities and consumes 50µA/MHz

A $12.95 development board to be available late in September

These are two of the salient attributes of the Freescale Kinetis L microcontroller, previewed at Design West in San Jose back in March and now announced at the Freescale Technology Forum in San Antonia with alpha samples shipping. The target for this product is the vast sea of products and applications that currently incorporate 8- and 16-bit microcontrollers—mainly for reasons of legacy code, legacy familiarity, and cost. It will take a compelling product to hurdle these barriers and the low prices for the Kinetis L silicon and development board will help to jump those hurdles.

Late in September, eh? There’s a thing I go to every year in New York that happens in late September*…

Freescale Semiconductor Inc. is sampling the industry’s first microcontroller to use ARM’s ultra-low-power Cortex-M0+ processor, which aims to convert 8- and 16-bit applications to 32-bit status by offering one-third the energy consumption of 8-bit processors while delivering twice the performance of a 16-bit processor.

“The plus of our new Cortex M0+ is really a minus as far as power is concerned,” said Warren East, ARM’s chief executive officer. “We worked with Freescale to design a core that could extend the battery life of mobile applications the way an 8-bit microcontroller does, but while delivering the 32-bit performance people expect from ARM.”

7 Comments

The ‘preorder here’ on the linked Newark.com site appears to be a simple jpg place holder. Also theAmpHour.com site appears to be down or otherwise 503 Service Temporarily Unavailable. at least as of now – 6/19 530pm HST (GMT-10).

I updated the ‘preorder’ link to the page I found the original pre-order link from, which shows both boards. I guess the black board is just a placeholder, but that’s the only ARM M0+ board for $13, so it’s a good bet that it’s the same board.

AmpHour was down because Chris happened to be doing maintenance. It’s back up now.

Freescale: announce early, deliver late. But I have my own professional bias as well. 🙂

Joking aside, I’m actually pretty excited about the M0+. The current M0 (LPC1114, LPC11U24, etc.) is already a nice, efficient little core with very impressive power numbers, but it’s main bottleneck is the Von Neumann architecture compared to the Harvard architecture on the M3/M4.

The M0 is single-pipeline, meaning that instructions and data both pass through the same pipeline and so you can’t send an instruction and read a result at the same time (in the same clock cycle). This basically doubles the time it takes to execute code compared to the 3 pipeline Harvard architecture on the M3 + M4 (it has seperate pipelines for instructions and data plus a third for peripherals), meaning commands and data can be handled much more efficiently. While the M3 is pushing out a command, it’s pulling in a chunk of data in the same cycle, cutting execution time in half for many operations at the same operating frequency as the single-pipeline M0.

50MHz is still a lot of headroom even with a single pipeline architecture, and that’s also one of the things that keeps the core so small and low-power (low-leakage due to smaller gate count, low-cost due to the small die size, etc.).

What’s nice with the M0+ is that it will introduce a 2-pipeline architecture with seperate I+D channels, while still keeping a very low gate count and excellent (even improved) power numbers. What this means is that you can double the execution speed, getting up to 2x the bang for your buck with no power increase!

But it all comes back to the nonsense of even considering MHz a valid metric for anything other than marketing. Most instructs on the M3 and many on the M0 execute in a single clock cycle, which is what you really need to look at and what makes the ARM chips so efficient. The Cortex M0, despite the single pipeline, is actually extremely efficient for certain types of calculations. It has the option to include a single-cycle 32-bit*32-bit multiply, for example. Doing say 10-million 32-bit multiplies a second is perfectly doable on a 50MHz LPC1114 … but would take much much longer on an 8-bit processor even at 50MHz.

50MHz is already pretty good for a $1 processor, but it’s even more impressive when you take a look at how efficient the instruction set is on the small ARM cores. The M0 is good, but the M3+M4 will be significantly faster per MHz moving a lot of bytes and data around. The M0+ should address this bottleneck, though, and put many M0+ instructions on part with the larger M3/M4s.

Sorry … this should really be a blog post … it’s turned into a monster comment.