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AR# 50461

Description

The calibration algorithm and hard block settings for all interfaces have been updated in MIG 7 Series v1.6. All users must upgrade to MIG 7 series v1.6 as the previous calibration algorithm and hard block settings can exhibit calibration failures and data corruption on reads.

Note: MIG 7 Series v1.6 is not production status IP. Users must upgrade to v1.7 or higher. Please upgrade IP and see (Xilinx Answer 53420).

Solution

This Design Advisory details the changes made to the calibration algorithm in MIG 7 Series v1.6.

Updated Phaser_OUT Circular Buffer Settings (All Interfaces):

Description: Changes to the Phaser_OUT circular buffer initialization have been implemented to ensure, across FPGA process variation, the Phaser_OUT outputs are phase aligned. Potential Failure Mode: Without the updated Phaser_OUT Cicular Buffer settings, some devices may exhibit Write Leveling or Write Calibration Failures due to misaligned Phaser_OUT outputs. For example, ddr_can_n and ddr_addr[0] are misaligned by one clock cycle.Fix: Updated Phaser_OUT Circular Buffer initial values.

Updated Phaser_IN and DQS IOB Configuration (DDR3 and DDR2 Only):Description: Changes to the configuration of the Phaser_IN block have been implemented to ensure reliable DQS preamble detection across all possible component (FPGA and DRAM) variations. Potential Failure Mode: Without the Phaser_IN block configuration changes, some devices may exhibit data corruption on reads at high data rates shortly after operation begins.Fix: Updated UCF and rtl Phaser_IN and I/O configuration.

Updated Write Leveling Logic for 2:1 Mode (DDR3 Only):Description: Changes to the Write Leveling Phaser_Out tap decrement/increment logic have been implemented to ensure the appropriate Write Latency is used in 2:1 mode.Potential Failure Mode: Without the updated 2:1 Write Leveling logic, Write Calibration failures can be seen due to the Write Latency incorrectly being set to CWL+1 instead of CWL.Fix: Updated the Write Leveling Phaser_OUT tap increment and decrement logicUpdated Phaser_IN DQSFOUND and Phase Lock Calibration (DDR3 Only):Description: Added synchronization flip-flops to the Phaser_IN outputs to ensure proper calibration results.Potential Failure Mode: Without the calibration updates, Read Leveling failures or Read Data failures can be seen.Fix: Updated the Phaser_IN outputs used during the DQSFOUND and Phase Lock stages of calibration.Revision History:08/06/2012 - Update to Design Advisory07/25/2012 - Initial Release