What kind of pins is needed when connected to the memory of CS0 space?

Question:

As for the address bus A18 to A21 of SH7145, the general port is selected as an initial function when it is the on-chip ROM invalid mode. What kind of pin processing is necessary when the pins are connected to the memory of CS0 space?

Answer:

At on-chip ROM invalid mode, though SH7145 access the memory of CS0 space after power-on reset, pins of A18 to A21 enter the state of high impedance because those pins become a general-purpose port. Please process the pull-down to avoid the malfunction of the memory when you connect the pins of A18 to A21 to the memory of the CS0 space.