Friday, November 30, 2007

A quite interesting paper that came out in the 2006 ESSDERC, and has now been published in an special issue of the IEEE TED. It has been written by R. Woltjer, L. Tiemeijer and D. Klaassen, from the Philips Research Labs., Eindhoven.They review compact modelling from its beginnings, and explain two different examples (the PSP model, obiously, and a compact model for integrated inductors). It is quite interesting as a first (or second...) contact with this world.By the way, the paper (An industrial view on Compact Modelling) is here.

MSM is the main technical forum to present the latest research and development in design, modeling and simulation methods, tools and applications in the MEMS, microelectronic, semiconductor, sensor, materials and biotechnology fields. Process, device and circuit simulation is one of the topics explicitly mentioned. Semiconductors and Microelectronics is indicated as one of the application areas.

The Workshop on Compact Modeling (WCM) is one of the largest event devoted to the Compact Modeling field. WCM has become a very important open forum for discussion among experts in this field as well as feedback from technology developers, circuit designers, and EDA tool vendors.

The suggested topics include all important aspects of compact model development and application: intrinsic models, extrinsic/interconnec models, atom/quantum models, statistical models, and model extraction and interface.

A limited number of papers will be selected for oral presentations and the remaining accepted papers will be planned for poster presentations with oral briefing. The deadline for abstract submission is December 6 2007.

The Chairman of WCM is Professor Xing Zhou (from Nanyang Technological University, Singapore). He was the person who created WCM and has made this workshop very successful.

I think that it is a must for Compact Modeling researchers to attend WCM. Many of the last advances in this field are presented there.

Overview: As we dive deeper into the nanometer space, we must rethink the way we design. Tools, techniques, and methods that once worked without fail cannot hold up at the 65 and 45 nm depths, making it more challenging than ever to achieve yield.

Not only are more DRC rules required, but the rules are becoming much more complex in light of more manufacturing issues. Yet advanced DRC is still not enough. We must redefine the sign-off process itself to include a spectrum of new methods that assess design quality. More of the responsibility for yield must shift to the designer, so the fabless model, where foundry information flows freely, increases in importance.

In the nanometer age, sign-off must include not only fundamental, rule-based physical verification and parasitic extraction, but also a set of automated technologies that help improve yield by enhancing the design itself.

What you will learn: This tutorial goes into detail on these new technical challenges and solutions within both the business and historical context of the IC design and manufacturing process. It shows the importance of the fabless model as part of a more holistic DFM methodology, and includes demonstrations of what the new tools look like.

Overview: This online demo shows how IC designers can easily verify their designs throughout the entire IC design process, using Calibre LVS and the integrated design debug environment. We look at some typical LVS designs errors, and show the user how to easily identify these, fix them, and then validate that they are fixed correctly. The strong integration Calibre has into the Cadence Virtuoso design environment is shown as part of the design flow.

What you will learn:

How to easily track down IC design errors using Calibre LVS

How to identify the locations of these errors in your design environment

How Calibre interacts with the Cadence Virtuoso design creation environment

How Calibre LVS can improve your productivity by reducing your LVS debugging time

Tools demonstrated:

Calibre LVS to verify your IC design

Calibre RVE to visualize the results and identify them in the Cadence Virtuoso environment

Calibre Interactive as a launch platform to re-run your verification once the design has been fixed

Tuesday, November 6, 2007

IWCM is an interesting forum to present and discuss the recent advances in compact modeling and simulation of semiconductor devices and integrated circuits. Actually IWCM is one of the few existing Workshops devoted mostly to compact modeling, and the only one who takes place in Asia.

Monday, November 5, 2007

San Jose, CA and Feldkirchen, Germany -- Cadence Design Systems, GmbH announced the formation of an academic network in Europe to promote the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence. This initiative will establish a knowledge network among selected European universities, research institutes, industry advisors and Cadence to facilitate the sharing of technology expertise in the areas of verification, design and implementation of microelectronic circuits.

Universities were selected with particular strengths and competencies in mind-- such as analog mixed-signal, radio frequency (RF), and low power design, all of which have been identified as key challenges for the coming years by the electronics industry. Under the initiative, Cadence will provide software, training and design methodology instruction to each of the institutions. Trained on the latest techniques with leading-edge software, the universities will then share their knowledge with other academic and research institutions. Students from these universities will graduate with an in-depth knowledge of how to tackle the pressing design issues that the industry is facing, learned on the most advanced design automation products available today.

So far three universities have joined the network in lead roles: The University of Heidelberg will lead high-level verification methodology; the Technical University of Ilmenau will concentrate on RF design methodology; and the Albert-Ludwigs-University of Freiburg will be the lead university for analog mixed-signal methodology. Planning to join the initiative shortly are the Polytechnic University of Bucharest, Romania, the University of Bristol, UK, and the University of Pavia in Italy.

"Our high standards in teaching and research have led Cadence to select us to be the lead university for analog mixed-signal methodology," said Prof. Dr.-Ing. Yiannos Manoli, head of the Microelectronics Group at IMTEK, University of Freiburg and Director of HSG-IMIT. "The increasing demand for highly skilled graduates in microelectronic design requires a solid and broad theoretical knowledge combined with a practical skill set in state-of-the-art techniques. Being part of this network will enable us to instruct our students using leading-edge technology."

Sean Redmond, vice president, EMEA for Cadence, said: "With the increase in development of complex industrial electronic systems, our customers are finding that they need engineers with broad technology competence. This network provides an exchange platform for the industry, academia and Cadence to stimulate the use of leading-edge technology at these universities. We are enthusiastic about this initiative and believe that the broad portfolio of Cadence solutions provides a perfect instrument to transfer up-to-date design methodology."