Description: Grant applications are sought to develop application-specific integrated circuits (ASICs), as well as circuits (including firmware) and systems, for rapidly processing data from highly-segmented, position-sensitive germanium detectors (pixel sizes in the range of 1 mm to 1 cm) and from particle detectors (e.g., gas detectors, scintillation counters, silicon drift chambers, silicon pixel and strip detectors, particle calorimeters, and Cherenkov counters) used in nuclear physics experiments. Areas of specific interest include (1) representative circuits such as low-noise preamplifiers, amplifiers, peak sensors, timing sensors, analog storage devices, analog-to-digital and time-to-digital converters, transient digitizers, and time-to-amplitude converters; (2) front-end, digitizing, and multiplexing circuits operating in cryogenic environment, to allow for reduction of noise, power, and number of feedthroughs in highly segmented germanium detectors; (3) multiple-sampling circuits , to allow for pulse-shape analysis; (4) readout electronics for solid-state pixilated detectors, including interconnection technologies, charge sharing processing and correction circuits (pixel pitch below 250 m), and amplifier-sample-and-hold circuits; (5) systems with exceedingly large dynamic range (&gt; 5000) employing, for example, either dynamic charge sensitive amplifier (CSA) gain changing or combinations of a standard linear CSA with a time-over-threshold (TOT) that works well into CSA saturation; and (6) constant-fraction discriminators with uniform response for low- and high energy gamma rays. These circuits should be fast; low-cost; high-density; configurable in software for thresholds, gains, etc.; easy to use with commercial auxiliary electronics; low power; compact; and efficiently packaged for multi-channel devices.
In addition, planned luminosity upgrades at RHIC will require fine-grained vertex and tracking detectors (both silicon and gas) for high particle multiplicity environments. Therefore, grant applications are sought for advances in microelectronics that are specifically designed for low-noise amplification, digitization and smart on-chip processing (triggering, neighboring, sparsification, data reduction) of detector signals, and that are suitable for these next generation detectors. The microelectronics and associated interconnections must be lightweight and have low power dissipation. Of particular interest are designs that minimize higher-gate leakage currents due to tunneling and maintain dynamic range.

c: Advanced Devices and Systems

Description: Grant applications are sought for improved or advanced devices and systems used in conjunction with the electronic circuits and systems described in subtopics a and b above:
Areas of interest regarding devices include (1) wide-bandgap semiconductors (i.e., semiconductor materials with bandgaps greater than 2.0 electron volts, including Silicon Carbide (SiC), Gallium Nitride (GaN), and any III-Nitride alloys); (2) inhomogeneous semiconductors such as SiGe; and (3) device processes such as silicon-on-insulator (SOI) or silicon-on-sapphire (SOS).
Areas of interest regarding systems include (1) bus systems, data links, event handlers, multiple processors, trigger logics, and fast buffered time and analog digitizers. For detectors that generate extremely high data volumes (e.g., &gt;500 GB-s), (2) advanced high-bandwidth data links are of interest.
Grant applications also are sought for generalized software and hardware packages, with improved graphic and visualization capabilities, for the acquisition and analysis of nuclear physics research data.

d: Active Pixel Sensors

Description: Active Pixel Sensors in CMOS (complementary metal-oxide semiconductor) technology are replacing Charge Coupled Devices as imaging devices and cameras for visible light. Several laboratories are exploring the possibility of using such devices as direct conversion particle detectors. The charge produced by an ionizing particle in the epitaxial layer is collected by diffusion on a sensing electrode in each pixel. The charge is amplified by a relatively-simple low-noise circuit in each pixel and read out in a matrix arrangement. If successful, this approach would make possible high-resolution, position-sensitive particle detectors with very low mass (approximately 50 microns of silicon in a single layer). This approach would be superior to the present technology that uses a separate silicon detector layer, which is bump-bonded to a CMOS readout circuit. Grant applications are sought to advance the development of integrated detector-electronics technology, using CMOS monolithic circuits as particle detectors. The new active pixel detector with its integrated electronic readout should be based on a standard CMOS process. The challenge is to design a sensor with low noise readout (S-N ~ 30:1 for mid-resistivity silicon designs, also see reference on First Test Results of MIMOSA-26) circuits that have sufficiently high sensitivity and low power dissipation, in order to detect a minimum ionizing particle in a thin epitaxial-like or equivalent layer (~10-30 microns).
Grant applications also are sought for the next generation of active pixel sensors, or even strip sensors, which use the bulk silicon substrate as the active volume. This more advanced approach would have the advantage of developing relatively larger signals and allowing sensitivity to non-minimum ionizing particles, such as MeV-range gamma rays.

e: Manufacturing and Advanced Interconnection Techniques

Description: Grant applications are sought to develop (1) manufacturing techniques for large, thin, multiple-layer printed circuit boards (PCBs) with plated-through holes, dimensions from 2m x 2m to 5m x 5m, and thicknesses from 100 to 200 microns (these PCBs would have use in cathode pad chambers, cathode strip chambers, time projection chamber cathode boards, etc); (2) techniques to add plated-through holes, in a reliable robust way, to large rolls of metallized mylar or kapton (which would have applications in detectors such as time expansion chambers or large cathode strip chambers); and (3) miniaturization techniques for connectors and cables with 5 times to 10 times the density of standard inter-density connectors.
In addition, many next-generation detectors will have highly segmented electrode geometries with 5-5000 channels per square centimeter, covering areas up to several square meters. Conventional packaging and assembly technology cannot be used at these high densities. Grant applications are sought to develop (1) advanced microchip module interconnect technologies that address the issues of high-density area-array connections including modularity, reliability, repair-rework, and electrical parasitics; (2) technology for aggregating and transporting the signals (analog and digital) generated by the front-end electronics, and for distributing and conditioning power and common signals (clock, reset, etc.); (3) low-cost methods for efficient cooling of on-detector electronics; (4) low-cost and low-mass methods for grounding and shielding; and (5) standards for interconnecting ASICs (which may have been developed by diverse groups in different organizations) into a single system for a given experiment these standards should address the combination of different technologies, which utilize different voltage levels and signal types, with the goal of reusing the developed circuits in future experiments.
Lastly, highly-segmented detectors with pixels smaller than 100 microns present a significant challenge for integration with frontend electronics. New monolithic techniques based on vertical integration and through-silicon vias have potential advantages over the current bump-bonded approach. Grant applications are sought to demonstrate reliable, readily-manufacturable technologies to interconnect silicon pixel detectors with CMOS front-end integrated circuits. Of highest long term interest are high-density high-functionality 3D circuits with direct bonding of high resistivity silicon detector layer of an appropriate thickness (50 to 500 microns) to a 3D stack of thin CMOS layers. The high resistivity detector layer would be fully depleted to enable fast charge collection with very low diffusion. The thickness of this layer would be optimized for the photon energy of interest or to obtain sufficient signal from minimum ionizing particles.

f: Other

Description: In addition to the specific subtopics listed above, the Department invites grant applications in other areas that fall within the scope of the topic description above.