University of Southern California, B.S. in Computer Science and Engineering (5/93)

Graduated with Summa Cum Laude.

RESEARCH INTEREST

Embedded Systems

Computer Architectures

System Software

High-Speed Networking

Cloud Computing.

EXPERIENCE

Sogang Univeristy(2011-present)

Associate Professor

Teaching embedded systems and computer architecture courses.

Performing various researches.

Cisco Systems(2001 – 2011)

Senior Engineer

I have worked for a group that builds internet core routers. An internet core router can be viewed as a very complex embedded system that consists of processors, system-on-chips, memories and IO chips. It is a key element in IP network that is essential for various IP based applications such as Voice of IP, IPTV, Video on Demand, etc. I have architected, designed, and verified various parts of the internet router which perform packet forwarding/classification, QoS scheduling, and queueing in internet routers. During my tenure, we launched two most complex multi-core based internet routers in the world: CRS-1 and CRS-3, which can switch up to 92 terabits and 322 terabits of internet traffic respectively. One of my main roles was architecture modeling and simulation of the internet router.

Computer Systems Laboratory, Stanford University (1997 – 2000)

Research Assistant: Supervisor was Prof. Michael J. Flynn.

My PhD research was focused on exploring various reconfigurable computing architectures. One of the candidate architectures was FPGA. My PhD thesis was to develop new circuit, architecture, and software techniques to improve the cost and performance of applications mapped on FPGAs so that new FPGA can be integrated with processor core or used independently in embedded systems. My works in this area include

Designed Self-timed Postcharge buffers to speed up the programmable interconnect of FPGAs. This scheme reduces the interconnect delay of applications mapped on FPGAs by up to 400 % over existing techniques and significantly boosted up the performance of mapped applications.

Designed a coarse-grained carry architecture for FPGAs. This method improved the area efficiency of the applications involving arithmetic operations such as multiplications and fused-multiplications. o Designed multi-ported FPGA logic block architectures and hierarchical mapping technique for data intensive applications. This new architecture exploits parallelism and data locality available in applications.

Other research works during my PhD period include

Designed an optimal datapath for a partitionable multiplier which can be configured as FIR filters or parallel multipliers with variable input widths. 64-bit multiplier can be partitioned into two 32-bit multipliers or four 16-bit multipliers.

Designed and compared various encoding methods for Pyramid Video encoder. Pyramid Video encoder is useful for low bandwidth channel.

Designed packet switching algorithms for optical switching networks.

Swan Instruments, Santa Clara, CA (1995 – 1996)

Software/Hardware Designer

Main role was to implement window-based programs for controlling high capacity floppy disk drive and testers.

HONORS & AWARDS

Graduated with Summa Cum Laude, ranked in the 1st place in Computer Science and Engineering Department, University of Southern California (1993)