RapidIO spec bows at embedded conference

BOSTON  Mercury Computer Systems Inc. and the Networking and Computer Systems Group of Motorola's Semiconductor Products Sector (Austin, Texas) announced a new spec for high-speed chip-to-chip and board-to-board interconnections at the Embedded Systems Conference on Tuesday (Feb. 29). Dubbed RapidIO, the spec is the result of a yearlong collaboration to provide the kind of high-speed data rates inside a box that InfiniBand is to bring to inter-box connections.

Both companies had been working independently to develop a high-speed interconnect, said Richard Jaenicke, director of product marketing at Mercury (Chelmsford, Mass.). Once the companies discovered each other's efforts, "we quickly realized that unless we did something together to pull the industry towards a common solution, we'd end up with a fragmented state of interconnects, so we decided to join forces," Jaenicke said. The two companies "recently talked to a number of other companies to get their inputs on the spec, and now we're ready to announce the architecture and form an industry trade association to take over stewardship of it as an open spec."

RapidIO is a switched-fabric interconnect using packet-switching protocols. Its initial implementation will have an 8-bit data path and 250-MHz clock rate, according to Jaenicke. "But the spec leaves room for wide and narrower data paths and higher frequencies," he said. It relies on memory-mapped addressing, low voltage differential signaling (LVDS) transmission and double-edge clocking. At 8 bits and 250 MHz, it is capable of 500 Mbits/second per line, 500 Mbytes/s per port and, when operating full duplex, 1 Gbyte/s overall. The interconnect's latency is very low, Jaenicke said.

In addition, RapidIO was designed to be "very small and easy to implement," said Jaenicke. "It can fit in a single FPGA with room left for the other side of the interface," he explained, "or in a small corner of some other chip  an ASIC or microprocessor."