ESD Protection Apparatus and Electrical Circuit Including Same - An ESD protection apparatus includes a substrate, a transistor structure arranged in the substrate, and a diode structure arranged in the substrate, a high-resistance electrical connection being provided between the transistor structure and the diode structure in the substrate.

2010-11-25

20100295095

DEPLETION-LESS PHOTODIODE WITH SUPPRESSED DARK CURRENT AND METHOD FOR PRODUCING THE SAME - The invention relates to a photo-detector with a reduced G-R noise, which comprises a sequence of a p-type contact layer, a middle barrier layer and an n-type photon absorbing layer, wherein the middle barrier layer has an energy bandgap significantly greater than that of the photon absorbing layer, and there is no layer with a narrower energy bandgap than that in the photon-absorbing layer.

2010-11-25

20100295096

Integrated Devices on a Common Compound Semiconductor III-V Wafer - A method of fabricating an integrated circuit on a compound semiconductor III-V wafer including at least two different types of active devices by providing a substrate; growing a first epitaxial structure on the substrate; growing a second epitaxial structure on the first epitaxial structure; and processing the epitaxial structures to form different types of active devices, such as HBTs and FETs.

2010-11-25

20100295097

FIELD-EFFECT TRANSISTOR - A field-effect transistor according to the present invention includes a silicon substrate that has a resistivity of not more than 0.02 Ω•cm, a channel layer that is formed on the silicon substrate and has a thickness of at least 5 μm, a barrier layer that is formed on the channel layer and supplies the channel layer with electrons, a two dimensional electron gas layer that is formed by a hetero junction between the channel layer and the barrier layer, a source electrode and a drain electrode that each form an ohmic contact with the barrier layer, and a gate electrode that is formed between the source electrode and the drain electrode, and forms a Schottky barrier junction with the barrier layer.

2010-11-25

20100295098

III-V HEMT DEVICES - A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed at a top surface side of the AlGaN layer. A band gap of the AlGaN layer is wider than a band gap of the p-GaN layer and the SI-GaN layer. Moreover, impurity concentration of the SI-GaN layer is less than 1×10

2010-11-25

20100295099

IMAGE SENSING DEVICE AND PACKAGING METHOD THEREOF - An image sensing device and packaging method thereof is disclosed. The packaging method includes the steps of a) providing an image sensing module, having a light-receiving region exposed, on a first substrate; b) forming a plurality of first contacts around the light-receiving region on the image sensing module; c) providing a second substrate, having a plurality of second contacts corresponding to the plurality of first contacts and an opening for allowing the light-receiving region to be exposed while the second substrate is placed over the image sensing module, the plurality of second contacts being disposed around the opening; d) connecting the plurality of first contacts and the plurality of second contacts; and e) disposing a transparent lid above the light-receiving region, on a side of the second substrate which is opposite to the plurality of second contacts.

2010-11-25

20100295100

INTEGRATED CIRCUIT HAVING A BULK ACOUSTIC WAVE DEVICE AND A TRANSISTOR - A bulk GaN layer is on a first surface of a substrate, wherein the bulk GaN layer has a GaN transistor region and a bulk acoustic wave (BAW) device region. A source/drain layer is over a first surface of the bulk GaN layer in the GaN transistor region. A gate electrode is formed over the source/drain layer. A first BAW electrode is formed over the first surface of the bulk GaN layer in the BAW device region. An opening is formed in a second surface of the substrate, opposite the first surface of the substrate, which extends through the substrate and exposes a second surface of the bulk GaN layer, opposite the first surface of the bulk GaN layer. A second BAW electrode is formed within the opening over the second surface of the bulk GaN layer.

2010-11-25

20100295101

INTEGRATED JFET AND SCHOTTKY DIODE - The present invention discloses an integrated junction field effect transistor (JFET) and Schottky diode, comprising a depletion mode JFET which includes a source, a drain and a gate, wherein the drain is not provided with an ohmic contact such that it forms a Schottky diode.

2010-11-25

20100295102

NORMALLY-OFF INTEGRATED JFET POWER SWITCHES IN WIDE BANDGAP SEMICONDUCTORS AND METHODS OF MAKING - Wide bandgap semiconductor devices including normally-off VJFET integrated power switches are described. The power switches can be implemented monolithically or hybridly, and may be integrated with a control circuit built in a single- or multi-chip wide bandgap power semiconductor module. The devices can be used in high-power, temperature-tolerant and radiation-resistant electronics components. Methods of making the devices are also described.

2010-11-25

20100295103

GATE ETCH OPTIMIZATION THROUGH SILICON DOPANT PROFILE CHANGE - Improved semiconductor devices comprising metal gate electrodes are formed with reduced performance variability by reducing the initial high dopant concentration at the top portion of the silicon layer overlying the metal layer. Embodiments include reducing the dopant concentration in the upper portion of the silicon layer, by implanting a counter-dopant into the upper portion of the silicon layer, removing the high dopant concentration portion and replacing it with undoped or lightly doped silicon, and applying a gettering agent to the upper surface of the silicon layer to form a thin layer with the gettered dopant, which layer can be removed or retained.

2010-11-25

20100295104

SEMICONDUCTOR STRUCTURES HAVING BOTH ELEMENTAL AND COMPOUND SEMICONDUCTOR DEVICES ON A COMMON SUBSTRATE - A semiconductor structure comprising: a substrate; a seed layer supported by the substrate; an elemental semiconductor layer disposed over a first portion of the seed layer; and a compound semiconductor layer disposed on a second portion of the seed layer. The first portion of the seed layer is electrically insulated from the second portion of the seed layer. A first semiconductor device is formed in the elemental semiconductor layer. A second semiconductor device is formed in the compound semiconductor layer. The second semiconductor device includes: a first electrode in contact with a first region of the compound semiconductor layer; a second electrode in contact with a second region of the compound semiconductor layer; and a third electrode. The third electrode controls carriers passing in a third region of the compound semiconductor layer disposed between the first region and the second region. A fourth electrode is in electrical contact with the second portion of the seed layer.

2010-11-25

20100295105

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes: an element portion formation step of forming an element portion on a base layer; a delaminating layer formation step of forming a delaminating layer in the base layer; a bonding step of bonding the base layer having the element portion to a substrate; and a separation step of separating and removing a portion of the base layer in the depth direction along the delaminating layer by heating the base layer bonded to the substrate. The method further includes, after the separation step, an ion implantation step of ion-implanting a p-type impurity element in the base layer for adjusting the impurity concentration of a p-type region of the element.

2010-11-25

20100295106

TRANSISTOR STRUCTURE AND DYNAMIC RANDOM ACCESS MEMORY STRUCTURE INCLUDING THE SAME - A dynamic random access memory structure is disclosed, in which, the active area is a donut-type pillar at which a novel vertical transistor is disposed and has a gate filled in the central cavity of the pillar and upper and lower sources/drains located in the upper and the lower portions of the pillar respectively. A buried bit line is formed in the substrate beneath the transistor. A word line is horizontally disposed above the gate. A capacitor is disposed above the word line as well as the gate and electrically connected to the upper source/drain through a node contact. The node contact has a reverse-trench shape with the top surface electrically connected to the capacitor and with the bottom of the sidewalls electrically connected to the upper source/drain. The word line passes through the space confined by the reverse-trench shape.

FERROELECTRIC MEMORY DEVICE AND FABRICATION PROCESS THEREOF, FABRICATION PROCESS OF A SEMICONDUCTOR DEVICE - A method for fabricating a ferroelectric memory device, including terminating a surface of the interlayer insulation film and a surface of the contact plug with an OH group; forming a layer containing Si, oxygen and a CH group on the surface of the interlayer insulation film and the contact hole terminated with the OH group by coating a Si compound containing a Si atom and a CH group in a molecule thereof; converting the layer containing Si, oxygen and the CH group to a layer containing nitrogen at a surface thereof, by substituting the CH group in the layer containing Si, oxygen and the CH group at least at a surface part thereof with nitrogen atoms; and forming a layer showing self-orientation on the surface containing nitrogen.

2010-11-25

20100295109

Memory Arrays, Semiconductor Constructions And Electronic Systems - Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.

2010-11-25

20100295110

DEVICE AND MANUFACTURING METHOD THEREOF - A device manufacturing method includes forming a first insulation film on a semiconductor substrate. A first mask is formed on the first insulation film to extend in a first direction and have a linear pattern. The first insulation film is etched using the first mask as mask to process the insulation film into a linear body. A second mask is formed on the linear body to extend in a second direction different from the first direction and have a linear pattern. The linear body is etched using the second mask as mask to process the linear body into a pillar element. A first conductive film is formed to cover the pillar body. The first conductive film is etched to form a first electrode of the first conductive film on side surfaces of the pillar body.

2010-11-25

20100295111

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor element and a protection diode formed on a semiconductor substrate. Over the semiconductor substrate, a first interlayer dielectric layer is formed so as to cover the semiconductor element and the protection diode. In the first interlayer dielectric layer, a first plug electrically connected to the semiconductor element and a second plug electrically connected to the protection diode are formed. The area of the top surface of the second plug is greater than the area of the top surface of the first plug.

2010-11-25

20100295112

SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device has a semiconductor substrate, a plurality of first insulating films formed on the semiconductor substrate with predetermined spacing therebetween, an element isolation region formed between the first insulating films in a first direction, a floating gate electrode comprising a first charge accumulation film formed on the first insulating film, a second charge accumulation film formed on the first charge accumulation film and having a width in a second direction orthogonal to the first direction smaller than the width of the first charge accumulation film, and a third charge accumulation film formed on the second charge accumulation film and having the width in the second direction larger than the width of the second charge accumulation film, a second insulating film formed on the second charge accumulation film and between the second charge accumulation film and the element isolation region, a third insulating film formed on the charge accumulation film and the element isolation region along the second direction, and a control gate electrode formed on the third insulating film.

2010-11-25

20100295113

SEMICONDUCTOR DEVICES COMPRISING A PLURALITY OF GATE STRUCTURES - Semiconductor devices including a plurality of gate structures disposed on a semiconductor substrate are provided. Each of the gate structures includes a tunnel dielectric layer, a floating gate, an inter-gate dielectric layer, a control gate, and a mask layer. Liners cover opposing sidewalls of adjacent floating gates. Spacers are disposed on the liners, the spacers protruding from opposing sidewalls of adjacent ones of the gate structures, and a top of each of the spacers is disposed below a top of a corresponding one of the gate structures. The liners define sidewalls of respective air gaps and the spacers define tops of the respective air gaps.

2010-11-25

20100295114

Semiconductor Constructions - Some embodiments include formation of polymer spacers along sacrificial material, removal of the sacrificial material, and utilization of the polymer spacers as masks during fabrication of integrated circuitry. The polymer spacer masks may, for example, be utilized to pattern flash gates of a flash memory array. In some embodiments, the polymer is simultaneously formed across large sacrificial structures and small sacrificial structures. The polymer is thicker across the large sacrificial structures than across the small sacrificial structures, and such difference in thickness is utilized to fabricate high density structures and low-density structures with a single photomask.

2010-11-25

20100295115

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE INCLUDING NONVOLATILE MEMORY CELL - A nonvolatile semiconductor memory device includes the following structure. Element isolation films are formed at predetermined intervals in a first direction in a surface region of a semiconductor substrate. The element isolation films extend in a second direction and isolate the surface region of the semiconductor substrate to provide element regions. Upper surface of the element isolation films are lower than upper surface of the element regions of the semiconductor substrate. A tunnel insulating film is formed on the element region. A charge accumulation layer is formed only on the tunnel insulating film. A block layer continuously is formed in the first direction on the charge accumulation layer and the element isolation film. A bottom surface of the block layer on the element isolation film is lower than the upper surface of the element region of the semiconductor substrate. A gate electrode is formed on the block layer.

2010-11-25

20100295116

Semiconductor Device and Manufacturing Method Thereof - A semiconductor device having a first semiconductor region and second semiconductor region including impurities formed on an insulating layer formed on a semiconductor substrate, an insulator formed between the first semiconductor region and the second semiconductor region, a first impurity diffusion control film formed on the first semiconductor region and a second impurity diffusion control film formed on the second semiconductor region, a channel layer formed on the first impurity diffusion control film and second impurity diffusion film to cross at right angles with a direction where the first semiconductor region and the second semiconductor region are extended, a gate insulating film formed on the channel layer and a gate electrode formed on the gate insulating layer.

2010-11-25

20100295117

JUNCTION-FREE NAND FLASH MEMORY AND FABRICATING METHOD THEREOF - A junction-free NAND flash memory is described, including a substrate, memory cells, source/drain inducing (SDI) gates electrically connected with each other, and a dielectric material layer. The memory cells are disposed on the substrate, wherein each memory cell includes a charge storage layer. Each SDI gate is disposed between two neighboring memory cells. The dielectric material layer is disposed between the memory cells and the SDI gates and between the SDI gates and the substrate.

2010-11-25

20100295118

Nanocrystal Based Universal Memory Cells, and Memory Cells - Some embodiments include memory cells that contain a dynamic random access memory (DRAM) element and a nonvolatile memory (NVM) element. The DRAM element contains two types of DRAM nanoparticles that differ in work function. The NVM contains two types of NVM nanoparticles that differ in trapping depth. The NVM nanoparticles may be in vertically displaced charge-trapping planes. The memory cell contains a tunnel dielectric, and one of the charge-trapping planes of the NVM may be further from the tunnel dielectric than the other. The NVM charge-trapping plane that is further from the tunnel dielectric may contain larger NVM nanoparticles than the other NVM charge-trapping plane. The DRAM element may contain a single charge-trapping plane that has both types of DRAM nanoparticles therein. The memory cells may be incorporated into electronic systems.

2010-11-25

20100295119

VERTICALLY-ORIENTED SEMICONDUCTOR SELECTION DEVICE FOR CROSS-POINT ARRAY MEMORY - A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more first silicide layers on the surface of the base. The second doped region is electrically coupled to a second silicide layer on the upper surface of the mesa. A gate conductor is provided on one or more sidewalls of the mesa.

2010-11-25

20100295120

VERTICALLY-ORIENTED SEMICONDUCTOR SELECTION DEVICE PROVIDING HIGH DRIVE CURRENT IN CROSS-POINT ARRAY MEMORY - A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more first silicide layers on the surface of the base. The second doped region is electrically coupled to one of a plurality of second silicide layers on the upper surface of the mesa. A gate conductor is provided on one or more sidewalls of the mesa.

2010-11-25

20100295121

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a semiconductor device including a first silicon pillar, an interlayer dielectric film provided on an upper surface of the first silicon pillar and having a through-hole filled with a conductive material, and a first-diffusion-layer contact plug provided on an upper-side opening of the through-hole. An area of a lower-side opening of the through-hole is equal to an area of the upper surface of the first silicon pillar, and an area of the upper-side opening of the through-hole is larger than the area of the lower-side opening of the through-hole. With this configuration, an area of a contact surface between the conductive material within the through-hole and the first-diffusion-layer contact plug is larger than the area of the upper surface of the first silicon pillar.

2010-11-25

20100295122

MOSFET HAVING RECESSED CHANNEL - A MOSFET having a recessed channel and a method of fabricating the same. The critical dimension (CD) of a recessed trench defining the recessed channel in a semiconductor substrate is greater than the CD of the gate electrode disposed on the semiconductor substrate. As a result, the misalignment margin for a photolithographic process used to form the gate electrodes can be increased, and both overlap capacitance and gate induced drain leakage (GIDL) can be reduced.

2010-11-25

20100295123

Phase Change Memory Cell Having Vertical Channel Access Transistor - Memory devices are described along with methods for manufacturing. A device as described herein includes a substrate having a first region and a second region. The first region comprises a first field effect transistor comprising first and second doped regions separated by a horizontal channel region within the substrate, a gate overlying the horizontal channel region, and a first dielectric covering the gate of the first field effect transistor. The second region of the substrate includes a second field effect transistor comprising a first terminal extending through the first dielectric to contact the substrate, a second terminal overlying the first terminal and having a top surface, and a vertical channel region separating the first and second terminals. The second field effect transistor also includes a gate on the first dielectric and adjacent the vertical channel region, the gate having a top surface that is co-planar with the top surface of the second terminal. A second dielectric separates the gate of the second field effect transistor from the vertical channel region.

Split gate oxides for a laterally diffused metal oxide semiconductor (LDMOS) - An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes a first heavily doped region to represent a source region. A second heavily doped region represents a drain region of the semiconductor device. A third heavily doped region represents a gate region of the semiconductor device. The semiconductor device includes a gate oxide positioned between the source region and the drain region, below the gate region. The semiconductor device uses a split gate oxide architecture to form the gate oxide. The gate oxide includes a first gate oxide having a first thickness and a second gate oxide having a second thickness.

2010-11-25

20100295126

High dielectric constant gate oxides for a laterally diffused metal oxide semiconductor (LDMOS) - An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes a first heavily doped region to represent a source region. A second heavily doped region represents a drain region of the semiconductor device. A metal region represents a gate region of the semiconductor device. The semiconductor device includes a gate oxide positioned between the source region and the drain region, below the gate region. The semiconductor device uses a high dielectric constant (high-κ dielectric) material.

DOUBLE INSULATING SILICON ON DIAMOND DEVICE - A silicon-on-diamond (SOD) transistor includes a silicon-based substrate, a diamond insulating layer over the silicon-based substrate, a silicon-based insulating layer directly over and in contact with the diamond insulating layer, a body over the silicon-based insulating layer, and a gate over the body. The structure of the SOD transistor provides improved drain induced barrier lowering (DIBL) in fully-depleted SOD transistors by using a second, silicon-based insulating layer.

2010-11-25

20100295129

FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION - A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

2010-11-25

20100295130

SEMICONDUCTOR DEVICE HAVING BIT LINE EXPANDING ISLANDS - Provided is a semiconductor device having bit line expanding islands, which are formed underneath bit lines to reliably expand and connect the bit lines. The semiconductor device includes: a semiconductor layer in which an isolation region and an active region are defined; an insulating layer, which is formed on the semiconductor layer; a plurality of bit lines, which are formed on the insulating layer; and one or more bit line expanding islands, which are formed inside the insulating layer and are electrically connected to a lower portion of at least one of the plurality of bit lines

2010-11-25

20100295131

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A buried insulating layer is buried at a position lower than a surface of a semiconductor substrate, and a cap insulating layer, which is made of a material different from the buried insulating layer, is formed on the buried insulating layer not to protrude into a shoulder portion of a step between the semiconductor substrate and the buried insulating layer.

2010-11-25

20100295132

PROGRAMMABLE PN ANTI-FUSE - Structure and method for providing a programmable anti-fuse in a FET structure. A method of forming the programmable anti-fuse includes: providing a p− substrate with an n+ gate stack; implanting an n+ source region and an n+ drain region in the p− substrate; forming a resist mask over the n+ drain region, while leaving the n+ source region exposed; etching the n+ source region to form a recess in the n+ source region; and growing a p+ epitaxial silicon germanium layer in the recess in the n+ source region to form a pn junction that acts as a programmable diode or anti-fuse.

2010-11-25

20100295133

Resistor of Semiconductor Device and Method of Forming the Same - The resistor of a semiconductor device comprises a semiconductor substrate comprising isolation layers and active regions, a gate insulating layer and a first polysilicon layer formed over the active region, a second polysilicon layer separated into a first pattern formed on the isolation layer, and a second pattern formed over the first polysilicon layer and higher than the first pattern, a first interlayer dielectric layer covering the first pattern over the isolation layer, a second interlayer dielectric layer formed over the first interlayer dielectric layer, contact holes exposing the first pattern in the first and second interlayer dielectric layers, and contact plugs filling the respective contact holes and coupled to the first pattern.

2010-11-25

20100295134

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor memory device according to one embodiment includes: a semiconductor substrate having an active region divided by an element isolation region; a plurality of stacked-gate type memory cell transistors connected in series on the active region; select transistors connected to both ends of the plurality of memory cell transistors on the active region; and a bit line contact connected to a drain region belonging to the select transistor in the active region, a vertical cross sectional shape of a lower portion of the bit line contact in a channel width direction of the plurality of memory cell transistors being in a skirt shape.

2010-11-25

20100295135

SEMICONDUCTOR MEMORY DEVICE AND PRODUCTION METHOD THEREFOR - In a static memory cell comprising six MOS transistors, the MOS transistors have a structure in which the drain, gate and source formed on the substrate are arranged in the vertical direction and the gate surrounds the columnar semiconductor layer, the substrate comprises a first active region having a first conductive type and a second active region having a second conductive type, and diffusion layers constructing the active regions are mutually connected via a silicide layer formed on the substrate surface, thereby realizing an SRAM cell with small surface area. In addition, drain diffusion layers having the same conductive type as a first well positioned on the substrate are surrounded by a first anti-leak diffusion layer and a second anti-leak diffusion layer having a conductive type different from the first well and being shallower than the first well, and thereby controlling leakage to the substrate.

2010-11-25

20100295136

METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A method for fabrication of 3D semiconductor devices utilizing a layer transfer and steps for forming transistors on top of a pre-fabricated semiconductor device comprising transistors formed on crystallized semiconductor base layer and metal layer for the transistors interconnections and insulation layer. The advantage of this approach is reduction of the over all metal length used to interconnect the various transistors.

2010-11-25

20100295137

METHOD AND APPARATUS PROVIDING DIFFERENT GATE OXIDES FOR DIFFERENT TRANSITORS IN AN INTEGRATED CIRCUIT - An integrated circuit and gate oxide forming process are disclosed which provide a gate structure that is simple to integrate with conventional fabrication processes while providing different gate oxide thicknesses for different transistors within the integrated circuit. For a flash memory, which may utilize the invention, the different gate oxide thicknesses may be used for lower voltage transistors, memory array transistors, and higher voltage transistors.

2010-11-25

20100295138

METHODS AND SYSTEMS FOR FABRICATION OF MEMS CMOS DEVICES - A MEMS integrated circuit including a plurality of layers where a portion includes one or more electronic elements on a semiconductor material substrate. The circuit includes a structure of interconnection layers having a bottom layer of conductor material and a top layer of conductor material where the layers are separated by at least one layer of dielectric material. The bottom layer may be formed above and in contact with an Inter Dielectric Layer. The circuit also includes a hollow space within the structure of interconnection layers and a MEMS device in communication with the structure of interconnection layers.

2010-11-25

20100295139

MEMS PACKAGE - An apparatus and method for manufacturing a micro-electrical mechanical system (MEMS) package comprising a first molded body having a first acoustic port, a second molded body connected to the first molded body, a leadframe at least partially integral with at least one of the first and second molded bodies, a die cavity provided on at least one of the first and second molded bodies and having a second acoustic port, a MEMS die provided on the die cavity, a channel connecting the first and second acoustic ports, the first molded body sealing at least a portion of the channel, and a lid attached to the second molded body and sealing at least a portion of the die cavity.

2010-11-25

20100295140

SEMICONDUCTOR DEVICE - A semiconductor device includes a housing defining a cavity, a magnetic sensor chip disposed in the cavity, and mold material covering the magnetic sensor chip and substantially filling the cavity. One of the housing or the mold material is ferromagnetic, and the other one of the housing or the mold material is non-ferromagnetic.

2010-11-25

20100295141

TWO COLOUR PHOTON DETECTOR - A two-color radiation detector includes a mesa-type multi-layered mercury-cadmium-telluride detector structure monolithically integrated on a substrate. The detector is responsive to two discrete wavelength ranges separated by a wavelength range to which the detector is not responsive. The detector further includes two contact points deposited on the layer disposed furthest away from the entry point of the radiation, the contact points being isolated with respect to each other by a trench disposed within the layer.

TWO-DIMENSIONAL SOLID-STATE IMAGING DEVICE - A two-dimensional solid-state imaging device includes: pixel regions arranged in a two-dimensional matrix, wherein each pixel region has a plurality of subpixel regions, a metal layer with an opening of an opening size smaller than the wavelength of an incoming electromagnetic wave and a photoelectric conversion element are arranged with an insulating film interposed therebetween, at least one photoelectric conversion element is arranged in the opening provided at a portion of the metal layer in each subpixel region, a projection image of the opening is included in a light receiving region of the photoelectric conversion element, the opening is arrayed so as to cause a resonance state based on surface plasmon polariton excited by the incoming electromagnetic wave, and near-field light generated near the opening in the resonance state is converted to an electrical signal by the photoelectric conversion element.

2010-11-25

20100295144

Tiled Light Sensing Array - A method is provided of forming a light sensing arrangement for use in a light sensor. The method comprises tiling a plurality of individual light sensing elements on a carrier, each element having a notch formed in an edge thereof, the notch being adapted to provide space, when the elements are tiled together, for an electrical connection to be made between the carrier and a surface of the element arranged to faced away from the carrier. Each element may comprise Silicon Photomultiplier (SPM) circuitry.

2010-11-25

20100295145

PHOTODIODE AND METHOD OF FABRICATING PHOTODIODE - A light-absorbing layer is composed of a compound-semiconductor film of charcopyrite structure, a surface layer is disposed on the light-absorbing layer, the surface layer having a higher band gap energy than the compound-semiconductor film, an upper electrode layer is disposed on the surface layer, and a lower electrode layer is disposed on a backside of the light-absorbing layer in opposition to the upper electrode layer, the upper electrode layer and the lower electrode layer having a reverse bias voltage applied in between to detect electric charges produced by photoelectric conversion in the compound-semiconductor film, as electric charges due to photoelectric conversion are multiplied by impact ionization, while the multiplication by impact ionization of electric charges is induced by application of a high-intensity electric field to a semiconductor of charcopyrite structure, allowing for an improved dark-current property, and an enhanced efficiency even in detection of low illumination intensities, with an enhanced S/N ratio.

2010-11-25

20100295146

SEAL RING STRUCTURE FOR INTEGRATED CIRCUITS - A seal ring structure for an integrated circuit includes a seal ring being disposed along a periphery of the integrated circuit and being divided into at least a first portion and a second portion, wherein the second portion is positioned facing an analog and/or RF circuit block and is different from the first portion in structure. A P

2010-11-25

20100295147

ISOLATION STRUCTURE AND FORMATION METHOD THEREOF - An isolation structure comprising a substrate is provided. A trench is in the substrate. A sidewall of the trench has a first inclined surface and a second inclined surface. The first inclined surface is located on the second inclined surface. The slope of the first inclined surface is different from the slope of the second inclined surface. A length of the first inclined surface is greater than 15 nanometers.

Integrated circuit structure with capacitor and resistor and method for forming - An integrated circuit structure with a metal-to-metal capacitor and a metallic device such as a resistor, effuse, or local interconnect where the bottom plate of the capacitor and the metallic device are formed with the same material layers. A process for forming a metallic device along with a metal-to-metal capacitor with no additional manufacturing steps.

SEMICONDUCTOR DEVICE - A semiconductor device includes a first substrate having a first surface on which a passive element is formed and a second surface on which a shield layer is formed, and a second substrate having a first surface on which an active element is formed. The first substrate is mounted on the second substrate with the second surface of the first substrate facing the second substrate.

2010-11-25

20100295152

Precision high-frequency capacitor formed on semiconductor substrate - A precision high-frequency capacitor includes a dielectric layer formed on the front side surface of a semiconductor substrate and a first electrode on top of the dielectric layer. The semiconductor substrate is heavily doped and therefore has a low resistivity. A second electrode, insulated from the first electrode, is also formed over the front side surface. In one embodiment, the second electrode is connected by a metal-filled via to a layer of conductive material on the back side of the substrate. In alternative embodiments, the via is omitted and the second electrode is either in electrical contact with the substrate or is formed on top of the dielectric layer, yielding a pair of series-connected capacitors. ESD protection for the capacitor can be provided by a pair of oppositely-directed diodes formed in the substrate and connected in parallel with the capacitor. To increase the capacitance of the capacitor while maintaining a low effective series resistance, each of the electrodes may include a plurality of fingers, which are interdigitated with the fingers of the other electrode. The capacitor is preferably fabricated in a wafer-scale process concurrently with numerous other capacitors on the wafer, and the capacitors are then separated from each other by a conventional dicing technique.

2010-11-25

20100295153

INTEGRATED CIRCUIT SYSTEM WITH HIERARCHICAL CAPACITOR AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers with the second group of metal layers to form a capacitor.

2010-11-25

20100295154

Capacitor Structure - One or more embodiments are related to a semiconductor chip comprising a capacitor, the capacitor comprising: a plurality of conductive plates, each of the plates including a first conductive strip and a second conductive strip disposed over or under the first conductive strip, the second conductive strip of each plate being substantially parallel to the first conductive strip of the same plate, the second conductive strip of each plate electrically coupled to the first conductive strip of the plate through at least one conductive via, the second conductive strips of each group of at least two consecutive plates being spaced apart from each other in a direction along the length of the plates.

2010-11-25

20100295155

TECHNIQUES FOR CAPACITIVELY COUPLING SIGNALS WITH AN INTEGRATED CIRCUIT - System and apparatus for capacitively coupling signals with an integrated circuit (IC) are described. Capacitive elements disposed with a transmitting IC effectively function as AC coupling capacitors for a PCIe, DisplayPort™ or other interconnect linking the transmitting IC with a receiver disposed remote there from. Integrating the coupling capacitors allows for a smaller and more economical design for the circuits that utilize the interconnect.

2010-11-25

20100295156

STRUCTURE FOR SYMMETRICAL CAPACITOR - Capacitance circuits are provided disposing a lower vertical-native capacitor metal layer above a planar front-end-of-line semiconductor base substrate, planar metal bottom plates spaced a bottom plate distance from the base and top plates above the bottom plates spaced a top plate distance from the base defining metal-insulator-metal capacitors, top plate footprints disposed above the base substrate smaller than bottom plate footprints and exposing bottom plate remainder upper lateral connector surfaces; disposing parallel positive port and negative port upper vertical-native capacitor metal layers over and each connected to top plate and bottom plate upper remainder lateral connector surface. Moreover, electrical connecting of the first top plate and the second bottom plate to the positive port metal layer and of the second top plate and the first bottom to the negative port metal layer impart equal total negative port and positive port metal-insulator-metal capacitor extrinsic capacitance.

2010-11-25

20100295157

ESD PROTECTION DEVICE - An ESD protection device is described, which includes a first P-type doped region, a second P-type doped region, a first N-type doped region, a second N-type doped region and an isolation structure. The first P-type doped region is configured in a substrate. The second P-type doped region is configured in the first P-type doped region. The first N-type doped region is configured in the first P-type doped region and surrounds the second P-type doped region. The second N-type doped region is configured in the substrate and surrounds the first P-type doped region. The isolation structure is disposed between the first P-type doped region and the second N-type doped region, wherein a spacing is deployed between an outward edge of the first N-type doped region and the isolation structure.

2010-11-25

20100295158

Semiconductor Constructions - In some embodiments, an opening is formed through a first material, and sidewall topography of the opening is utilized to form a pair of separate anistropically etched spacers. The spacers are utilized to pattern lines in material underlying the spacers. Some embodiments include constructions having one or more openings which contain steep sidewalls joining to one another at shallow sidewall regions. The constructions may also contain lines along and directly against the steep sidewalls, and spaced from one another by gaps along the shallow sidewall regions.

QUAD FLAT PACKAGE STRUCTURE HAVING EXPOSED HEAT SINK, ELECTRONIC ASSEMBLY AND MANUFACTURING METHODS THEREOF - A quad flat package (QDP) structure having an exposed heat sink is provided. The QDP structure includes a leadframe, a chip, a heat sink, an insulating layer and a molding compound. The leadframe includes a die pad and multiple leads surrounding the die pad. The chip is disposed on the die pad and electrically connected to the die pad and the leads. The heat sink has a top surface, a bottom surface opposite thereto, and a side surface connected to the top and the bottom surfaces. The die pad is disposed in a central area of the top surface of the heat sink and electrically connected to the heat sink. The molding compound encapsulates the chip, the die pad, an inner lead portion of each lead and heat sink, and exposes the bottom surface of the heat sink and an outer lead portion of each lead.

Semiconductor device - Portions of a wiring layer extending like cantilevers from an inner peripheral edge of an opening in a substrate are joined to respective terminals of a semiconductor chip mounted on the substrate. A junction portion between each portion of the wiring layer and the corresponding terminal is sealed with resin.

2010-11-25

20100295163

STACKED SEMICONDUCTOR PACKAGE ASSEMBLY - A stacked package assembly includes N (where N≧2) package bodies stacked together. Each package body is made up of a substrate which comprises a top surface and a bottom surface, and a chip packaged in the substrate. The top surface of the substrate of each package body includes (N−1) pads, and the bottom surface includes N pads. The Kth pad on the top surface of the substrate of each package body is electrically connected to the (K+1)th pad on the bottom surface thereof. The Kth (K=1, 2, . . . , (N−1)) pad on the top surface of the substrate of one lower package body corresponds to the Kth pad on the bottom surface of the substrate of another upper package body stacked above the lower package body.

2010-11-25

20100295164

AIRGAP MICRO-SPRING INTERCONNECT WITH BONDED UNDERFILL SEAL - A package includes a pad chip having contact pads, a spring chip having micro-springs in contact with the contact pads to form interconnects, the area in which the micro-springs contact the contact pads forming an interconnect area, an assembly material between the pad chip and the spring chip arranged to form a gap between the pad chip and the spring chip, and an underfill material in a portion of the gap to form a mold from the pad chip and the spring chip. A package includes a pad chip having contact pads, a spring chip having micro-springs in contact with the contact pads to form interconnects, the area in which the micro-springs contact the contact pads forming an interconnect area, an assembly material between the pad chip and the spring chip arranged to form a gap between the pad chip and the spring chip, an underfill material in the gap to form a mold from the pad chip and the spring chip, and at least one wall between the underfill material and the interconnect area. A method of assembling a package includes aligning a pad chip with a spring chip to form at least one interconnect in an interconnect area, adhering the pad chip to the spring chip so that there is a gap between the pad chip and the spring chip, dispensing underfill material into the gap to seal the interconnect area from an environment external to the package, and curing the underfill material to form a solid mold.

2010-11-25

20100295165

STRESS-ENGINEERED INTERCONNECT PACKAGES WITH ACTIVATOR-ASSISTED MOLDS - A package has a pad chip having contact pads, a spring chip having micro-springs in contact with the contact pads to form interconnects, the area in which the micro-springs contact the contact pads forming an interconnect area, a chemical activator in the interconnect area, and an adhesive responsive to the chemical activator in the interconnect area. A package has a pad chip having contact pads, a spring chip having micro-springs in contact with the contact pads to form interconnects, a chemical activator on one of either the pad chip or the spring chip, and an adhesive responsive to the chemical activator on the other of either the pad chip or the spring chip. A method includes providing a pad chip having contact pads, providing a spring chip having micro-springs, applying a chemical activator to one of either the pad chip or the spring chip, applying an adhesive responsive to the chemical activator on the other of the pad chip or the spring chip, aligning the pad chip to the spring chip such that the micro-springs will contact the contact pads, and pressing the pad chip and the spring chip together such that the chemical activator at least partially cures the adhesive.

2010-11-25

20100295166

Semiconductor package - The semiconductor package includes a printed circuit board, a first semiconductor chip, and a second semiconductor chip. The printed circuit board includes a slot. The first semiconductor chip is mounted on the printed circuit board to cover a first part of the slot. The second semiconductor chip is mounted on the printed circuit board to cover a second part of the slot separate from the first part. The first semiconductor chip is substantially coplanar with the second semiconductor chip.

2010-11-25

20100295167

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes an insulating substrate, a semiconductor chip, an insulating layer, and a sealing layer. The insulating substrate has an opening. A semiconductor chip is disposed in the opening. An insulating layer is disposed on a first surface of the insulating substrate. The insulating layer covers the opening. The sealing layer is disposed on a second surface of the insulating substrate. The sealing layer seals the semiconductor chip and the opening.

2010-11-25

20100295168

SEMICONDUCTOR PACKAGE USING CONDUCTIVE PLUG TO REPLACE SOLDER BALL - Exemplary embodiments provide a semiconductor package and methods for its formation. The disclosed semiconductor package can use conductive plug(s) to replace solder ball(s) of a conventional BGA semiconductor package. In one embodiment, the semiconductor package can include a conductive pad disposed over a first dielectric layer having a conductive plug directly extended from the conductive pad through the first dielectric layer and protruded over a surface of the first dielectric layer from about 0 micron to about 50 microns or greater. In various embodiments, arrays of the conductive plugs can be formed for the semiconductor package and can be further connected to a printed circuit board. Various exemplary methods for forming the semiconductor package can include a through-hole metal deposition to form the conductive plugs.

2010-11-25

20100295169

SEMICONDUCTOR SUBSTRATE AND METHOD OF CONNECTING SEMICONDUCTOR DIE TO SUBSTRATE - A semiconductor substrate includes a substrate layer and a circuit film formed over the substrate layer. One or more openings are formed in the circuit film and the substrate layer. Conductive plates are formed over the circuit film at the peripheries of the openings. A semiconductor die is attached to the circuit film, below the openings with an adhesive material. A conductive material is disposed in the openings to electrically connect the semiconductor die to the conductive plates.

2010-11-25

20100295170

SEMICONDUCTOR DEVICE - A semiconductor device includes a multilayer wiring substrate and a double-sided multi-electrode chip. The double-sided multi-electrode chip includes a semiconductor chip and has multiple electrodes on both sides of the semiconductor chip. The double-sided multi-electrode chip is embedded in the multilayer wiring substrate in such a manner that the double-sided multi-electrode chip is not exposed outside the multilayer wiring substrate. The electrodes of the double-sided multi-electrode chip are connected to wiring layers of the multilayer wiring substrate.

2010-11-25

20100295171

ELECTRONIC DEVICE AND METHOD - An electronic device and method is disclosed. In one embodiment, a method includes providing an electrically insulating substrate. A first electrically conductive layer is applied over the electrically insulating substrate. A first semiconductor chip is placed over the first electrically conductive layer. An electrically insulating layer is applied over the first electrically conductive layer. A second electrically conductive layer is applied over the electrically insulating layer.

2010-11-25

20100295172

POWER SEMICONDUCTOR MODULE - Disclosed is a power semiconductor module having improved heat dissipation performance, including an anodized metal substrate including a metal plate, an anodized layer formed on a surface of the metal plate, and a circuit layer formed on the anodized layer on the metal plate, a power device connected to the circuit layer, and a housing mounted on the metal plate and for defining a sealing space which accommodates a resin sealing material for sealing the circuit layer and the power device.

2010-11-25

20100295173

Composite Underfill and Semiconductor Package - Embodiments of the invention exploit physical properties of nanostructures by using nanostructures in a composite underfill. An embodiment is a composite underfill comprising an epoxy matrix applied between a substrate and a semiconductor chip and a suspension of nanostructures distributed within the epoxy matrix. Another embodiment is a semiconductor package comprising a semiconductor chip, a carrier, wherein the semiconductor chip is bonded to the carrier, and a composite underfill comprising a plurality of nanostructures dispersed in an epoxy medium between the carrier and the semiconductor chip. Further embodiments include a method for creating a semiconductor package comprising a composite underfill.

2010-11-25

20100295174

WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE - A wiring substrate includes: a semiconductor chip on which a plurality of bumps are mounted, and a plurality of connection pads which are joined to the bumps mounted on the semiconductor chip in a flip chip method, wherein the connection pads of a peripheral portion of the wiring substrate are formed in a non-solder mask defined structure, and the connection pads of a center portion of the wiring substrate are formed in a solder mask defined structure.

2010-11-25

20100295175

WAFER LEVEL CHIP SCALE PACKAGE - A semiconductor device of the invention includes a semiconductor substrate having a first insulating section formed on one surface thereof. A first conductive section is disposed on the one surface of the semiconductor substrate. A second insulating section is superimposed over the first insulating section and covers the first conductive section. A second conductive section is superimposed over the second insulating section. A third insulating section is disposed over the second insulating section and covers the second conductive section. These first conductive section, second insulating section, second conductive section, third insulating section, and terminal altogether constitute a structure. A third opening is formed between adjacent structures. The third opening is formed passing through the third and second insulating sections to expose the first insulating section.

2010-11-25

20100295176

SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, CIRCUIT SUBSTRATE, ELECTRO-OPTICAL APPARATUS, AND ELECTRONIC EQUIPMENT - A semiconductor device is provided with a plurality of protrusions which are made of a resin and which protrude higher than electrodes, and conductive layers which are electrically connected to the electrodes and which cover the top surfaces of the protrusions. A method for manufacturing the semiconductor device includes a step of applying a layer of the resin to the semiconductor device except for the electrodes, a step of patterning the conductive layers on the electrodes and the layer of the resin in accordance with the protrusions, and a step of removing the layer of the resin located between the conductive layers by the use of the patterned conductive layers as masks so as to form the protrusions.

2010-11-25

20100295177

ELECTRONIC COMPONENT MOUNTING STRUCTURE, ELECTRONIC COMPONENT MOUNTING METHOD, AND ELECTRONIC COMPONENT MOUNTING BOARD - In an electronic component mounting structure, a semiconductor element (an electronic component) provided with an electrode pad and a board provide with an electrode pad corresponding to the electrode pad are connected via a conductive material portion. On a surface of the board, there is formed solder resist having an opening regulating an area of the electrode pad. The conductive material portion is formed to protrude from a surface of the solder resist. An elastic coefficient of the conductive material portion is lower than that of the solder resist. A solder bump and the conductive material portion are connected via a metal layer. The conductive material portion is formed to have an area larger than that of the opening of the solder resist. An edge of the conductive material portion is adhered to a portion of the surface of the solder resist. Thus, in a case of mounting an electronic component on a board by flip-chip connection, a reliability of connection can be secured.

2010-11-25

20100295178

SEMICONDUCTOR CHIP PACKAGE AND MANUFACTURING METHOD THEREOF - A first wiring pattern is formed on a surface of a first support plate; a semiconductor chip is disposed on the first wiring pattern; and electrode terminals of the semiconductor chip are electrically connected to the first wiring pattern at required positions. Post electrodes connected to a second wiring pattern of a wiring-added post electrode component integrally connected by a second support plate are collectively fixed and electrically connected to the first wiring pattern formed on the first support plate at predetermined positions. After sealing with resin, the first and second support plates are separated; a glass substrate is affixed on a front face side; and external electrodes connected to the second wiring pattern are formed on a back face side.

2010-11-25

20100295179

BGA SEMICONDUCTOR DEVICE HAVING A DUMMY BUMP - A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.

2010-11-25

20100295180

WIRE BONDING STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention relates to a wire bonding structure, and more particularly to a manufacturing method for said wire bonding structure. The wire bonding structure comprises a die that connects with a lead via a bonding wire. At least one bond pad is positioned on an active surface of the die, and a gold bump is provided on the bond pad; furthermore, a ball bond can be positioned upon the gold bump. The bond pad and the gold bump can separate the ball bond and the die, which can avoid damaging the die during the bonding process.

2010-11-25

20100295181

REDUNDANT METAL BARRIER STRUCTURE FOR INTERCONNECT APPLICATIONS - A redundant metal diffusion barrier is provided for an interconnect structure which improves the reliability and extendibility of the interconnect structure. The redundant metal diffusion barrier layer is located within an opening that is located within a dielectric material and it is between a diffusion barrier layer and a conductive material which are also present within the opening. The redundant diffusion barrier includes a single layered or multilayered structure comprising Ru and a Co-containing material including pure Co or a Co alloy including at least one of N, B and P.

2010-11-25

20100295182

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Provided is a method for forming a Cu wiring that does not cause Cu elution during CMP when a Ru material is used as a barrier metal film for the Cu wiring. The method has a step (d) of removing a second barrier metal film (Ru film) formed on a first barrier metal film on an upper surface of an interlayer insulating film, and a step (e) of depositing a seed copper (Cu) film on the first and the second barrier metal films after the step (d). By removing the second barrier metal film on the upper surface before the seed copper film is formed, copper is prevented from eluding into a slurry due to a battery effect of the second barrier metal film and copper.

2010-11-25

20100295183

METHOD FOR PROVIDING ELECTRICAL CONNECTIONS TO SPACED CONDUCTIVE LINES - An integrated circuit and a method of formation provide a contact area formed at an angled end of at least one linearly extending conductive line. In an embodiment, conductive lines with contact landing pads are formed by patterning lines in a mask material, cutting at least one of the material lines to form an angle relative to the extending direction of the material lines, forming extensions from the angled end faces of the mask material, and patterning an underlying conductor by etching using said material lines and extension as a mask. In another embodiment, at least one conductive line is cut at an angle relative to the extending direction of the conductive line to produce an angled end face, and an electrical contact landing pad is formed in contact with the angled end face.

2010-11-25

20100295184

Method Of Manufacturing Semiconductor Device Including Wiring Layout And Semiconductor Device - A method of manufacturing a semiconductor device having a first wiring layer, a first interlayer insulating film, a second interlayer insulating film, a third interlayer insulating film, and a second wiring layer, in which the method includes depositing the second wiring layer on the third interlayer insulating film and, where the widths of first wiring layer and the second wiring layer are 10.0 μm or greater, executing one of etching the second wiring layer to set a width of 1.0 μm or greater in a portion where the first wiring layer and the second wiring layer overlap and etching the second wiring layer to seta horizontal distance of 2.0 μm or greater between adjacent portions of the first wiring layer and the second wiring layer.

2010-11-25

20100295185

Nonvolatile Memory Device and Method of Manufacturing the Same - A nonvolatile memory device comprises a semiconductor substrate comprising alternating, parallel active regions and isolation regions; first and second selection lines intersecting the active regions and the isolation regions; first junctions formed in the active regions between the first and second selection lines; spacers formed on sidewalls of the first and second selection lines; second junctions deeper than the first junctions formed in the first junctions, respectively; contact plugs coupled to one side of the respective second junctions; and dummy plugs coupled second sides of the respective second junctions.

Semiconductor device and method for fabricating the same - A semiconductor device which can prevent a deterioration in the electrical properties by preventing sputters generated by laser welding from adhering to a circuit pattern or a semiconductor chip and a method for fabricating such a semiconductor device are provided. A connection conductor is bonded to a copper foil formed over a ceramic by a solder and resin is injected to a level lower than a top of the connection conductor. Laser welding is then performed. After that, resin is injected. This prevents sputters generated by the laser welding from adhering to a circuit pattern or a semiconductor chip. As a result, a deterioration in the electrical properties can be prevented.

2010-11-25

20100295188

SEMICONDUCTOR DEVICE HAVING DEEP CONTACT STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device having a deep contact structure having an improved contact resistance is presented. The semiconductor device includes a semiconductor substrate, a first interlayer insulating layer, a contact plug, a second interlayer insulating layer, and a copper contact pad. The contact plug is formed in the first interlayer insulating layer and has a bulbous shaped upper side wall and an inwardly tapered lower side wall that extends downward towards the semiconductor substrate. The second interlayer insulating layer is formed over first interlayer insulating layer such that the second interlayer insulating layer includes a hole that exposes a top surface and a peripheral portion of the bulbous shaped upper side wall of the contact plug. The copper contact pad is buried within the hole so that the exposed parts of the bulbous shaped upper side wall of the contact plug protrude into the copper contact pad.

2010-11-25

20100295189

METHOD FOR REPAIRING CHIP AND STACKED STRUCTURE OF CHIPS - A method for repairing a chip with a stacked structure of chips is provided. First, a first chip is provided, which includes a first circuit block with a first function, a second circuit block with a second function, and a signal path electrically connected to the first and the second circuit blocks. A second chip is provided, which includes a third circuit block with the first function. The functions of the first and the second chips are verified. The first circuit block is disabled if the first circuit block is defective. The third circuit block is electrically connected to the signal path to replace the first circuit block and provide the first function if the second circuit block is functional and the third circuit block is functional.

WIRING BOARD, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING WIRING BOARD AND SEMICONDUCTOR DEVICE - In the wiring board, insulating layers and wiring layers are alternately laminated, and the wiring layers are electrically connected by the vias. The wiring board includes first terminals arranged in a first surface and embedded in an insulating layer, second terminals arranged in a second surface opposite to the first surface and embedded in an insulating layer, and lands arranged in an insulating layer and in contact with the first terminals. The vias electrically connect the lands and the wiring layers laminated alternately with the insulating layers. No connecting interface is formed at an end of each of the vias on the land side but a connecting interface is formed at an end of each of the vias on the wiring layer side.

2010-11-25

20100295192

AERATION APPARATUS - Provided is an aeration apparatus, which is enabled, when stopped, to prevent an air injection nozzle from being choked, by keeping the air injection nozzle out of contact with an object to be treated. An aeration apparatus (

2010-11-25

20100295193

Fuel Vaporizer system - A fuel vaporizer including a mist vaporizer and a boiler, the boiler being integrated with the mist vaporizer, the mist vaporizer and the boiler including a housing, baffles joined to the housing, conduit extending through the baffles, fuel in a mist form adjacent the conduit and a pool of fuel contained between the housing and baffles.