Questa Sim

Hi,
Is there way in system Verilog to compare line by line two files(its not know whether file will have strings or digit so no %s, %d )
Can I call $system in SV to do diff in questasim or Is there any best way to do it like tcl command etc ?
Thanks,
GSB

Hi,
Please revert back if the PA experts who can comment on the Power Aware GLS with the questasim.
There are some difference like the way questa taking the Hard Macros as different optimisation and the visibilty to the design is removed while elaborating. If anything critical, known are shared will be helpful.
-paulki

Hi all !
I'm new to questasim 10.1b but i'm use to Active-HDL and I want to know two thing
First is there a way to define a macro inside a file
I know that with Aldec->Active-HDL we can use the function : +define+ but i'm not able to find the equivalent with questa
Second is there a way to set many variable into a

Good idea is always to start with simulations. Once you are sure that there are no compilation errors, and your design is performing as expected, then move on to synthesis.
Industry follows the similar flow : Design --> simulation --> Synthesis --> Backend flow
Modelsim is from Mentor. Latest Modelsim (...)

Hi,
I am using questasim.
While checking assertion, It is showing pass in the waveform, but its showing fail in log file.
Assertion logic is right and signals is also behaving right.
please send me code

i'm also looking for a simulator for system verilog. i'm a student and can't afford to buy a full version of Models sim with questa in it. i would really appreciate if anyone could point me in the right direction. for that matter does anybody know if there are free system verilog simulators out there? i need it so i could (...)

Hi,
Is there any evaluation version software that can support systemverilog? I have heard that questasim is one such tool which supports systemverilog. Is it available freely? Plz let me know about this.
Thanks

Are there any free tools that support SystemVerilog? I'm looking into CAD tools and design methods at work (luckily starting with pretty much a blank slate), and at least for verification SystemVerilog seems to do just about everything I'm looking for (constrained random, assertions, etc).
I could get an eval copy of questa or Aldec, but since