Staff Engineer EMIR and Physical Design

Job Details

The candidate will work closely in a DI team for EM and IR drop analysis. The candidate will be responsible for at-least two of the following tasks.Should be able to work on EM / IR analysis for flat designs.Interface with packaging team and IP team for bumping / bonding activities and IP integration.Ownership of bumping, pad-ring planning, partitioning, pin optimization, floor plan, power plan placement, top level CTS, routing and chip level timing closure using industry standard EDA tools, along with related backend activities in demanding schedule deadline. Should be able to run DRC, LVS, EM, IR, and DFM.Own parasitic extraction, timing closure in PD and signal integrity sign-off as needed.The candidate possessing following will be preferred.Assist DI manager for power architecture, work on power planning and get IR drop to the spec.Co-ordinate across IP, packaging, RTL design, verification and power architecture teams for resolving any physical design issuesFull chip STA sign-off experience.Full chip physical verification sign-off experience including DFM..Must be technically adept, a strong team player and have demonstrated experience of taping out in challenging timelines for complex and relevant SoCs. The candidate needs to have excellent interpersonal and communication skills and good problem solving skills.Qualifications The engineer should be at-least BE with 9 to 12 years of relevant VLSI physical design experience. Strong individual contributors needed to support product line ASIC design. The candidate will work on leading edge storage solutions in an ASIC, full custom and SoC design.The candidate should have demonstrated experience/exposure to high-speed digital physical design and physical verification including ASIC through semi-custom high-speed digital designs from synthesis through tape out.Domain ExpertiseExperience in chip level power estimation , Dynamic and Static IR drop analysis.Hierarchical and flat level physical design flow which includes, bumping, padring planning, partitioning, pin optimization, floor plan, power plan placement, top level CTS, routing and chip level timing closure, Should be able to run DRC, LVS, EM, IR, DFM. Low power design with UPF.Technology node 28nm / 40nmToolsAnsys RedHawk for IR (static, dynamic) and EM analysis,Synopsys tool for PnR and timing closure.Mentor Calibre for physical verification,Additional Exposure to Encounter is desirable.Custom routes design using Industry standard tools. ICC is preferred. Knowledge of Virtuoso is desired. Degree: MCA/ PGDCA | ME/ M.Tech./ MS (Engg/ Sciences)