The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.

A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.

Cadence® Xcelium™ Parallel Logic Simulation is the EDA industry’s first production-ready third-generation simulator. It is based on innovative multi-core parallel computing technology, enabling systems-on-chip (SoCs) to get to market faster than current solutions. On average, customers can achieve 2X improved single-core performance and more than 5X improved multi-core performance versus previous generation simulators. The Xcelium simulator is cloud-ready and runs on your existing compute resources with leading runtime and capacity, making it the simulator of choice throughout the verification flow.

The Xcelium simulator offers the following benefits aimed at accelerating system development:

Multi-core engine architected for fast SoC simulation

Provides an average speed-up of 3X for register-transfer level (RTL), 5X for gate-level simulation (GLS), and 10X for design for test (DFT)

Single-core engine refactored for fast IP simulation

Proven engine runs comprehensive set of simulation use cases

Provides an average of 2X speed-up over the Cadence Incisive® Enterprise Simulator

Productivity features enable efficient verification

Innovative solutions on top of fast engines reduce overall project time

Provides enhanced smart exclusion flow and parallel multi-core

The multi-core engine in the Xcelium simulator provides fine-grained design parallelism to speed-up SoC simulations that run for days or weeks in second-generation simulators.

Its unique compile/elaboration process analyzes each design’s dependency graph and automatically maps it to the optimal number of cores to maximize its speed. Users can set the number of cores on the command line without recompile. The Xcelium simulator further extends innovation within the Cadence Verification Suite, which is comprised of best-in-class core engines, verification fabric technologies, and solutions that increase design quality and throughput, thus fulfilling verification requirements for a wide variety of use cases and vertical segments.

The Xcelium Parallel Simulator has demonstrated a 4X speed-up for gate-level simulation and 5X for RTL simulation on ARM®-based SoC designs. Based on these results, we expect Xcelium can enhance our ability to deliver the most complex SoCs in a fast and highly reliable way.

Fast, scalable simulation is key for us to meet the tight development schedules of our complex 28nm FD-SOI SoCs and ASICs for smart driving and industrial IoT. We measured 8X faster serial-mode DFT performance with the Cadence Xcelium Parallel Simulator, and selected it as the standard simulation solution...

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