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MTL Memory Cell With Resistor Loads

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

The operating margins of a memory cell employing merged transistor logic (MTL) technology are improved by incorporating load resistors in the connections between the word line and the PNP transistors of the cell. P-type polysilicon runners are a convenient means of providing load resistors of suitable values with a minimum of area used, because they can be integrated with the PNP emitters. The disclosed cell, contains "pull-up" resistors 5 and 6. In the original cell these resistors do not exist, that is, their value is zero. The original cell suffers from a conflict in design considerations. To achieve a large sense signal, the transistors 1 and 2 have to have relatively high beta values. High beta is difficult to achieve as the size of the geometries is reduced to favor high cell densities.

Country

United States

Language

English (United States)

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MTL Memory Cell With Resistor Loads

The operating margins of a memory cell employing merged transistor logic
(MTL) technology are improved by incorporating load resistors in the connections
between the word line and the PNP transistors of the cell. P-type polysilicon
runners are a convenient means of providing load resistors of suitable values
with a minimum of area used, because they can be integrated with the PNP
emitters. The disclosed cell, contains "pull-up" resistors 5 and 6. In the original
cell these resistors do not exist, that is, their value is zero. The original cell
suffers from a conflict in design considerations. To achieve a large sense signal,
the transistors 1 and 2 have to have relatively high beta values. High beta is
difficult to achieve as the size of the geometries is reduced to favor high cell
densities. In a particular typical example analyzed, the use of 500 ohms instead
of zero for the value of resistors 5 and 6 permits the beta requirements to drop
from 10 to 2 and still maintain approximately the same sense signal. The
resistors improve the DC stability of the cell, especially during memory access.
Even though resistors as low as a few hundred ohms in value enhance the
sensing requirements, in a large array it would probably be necessary to use a
sophisticated discharge/restore system for cell access. One such plan
discharges unselected word lines and pulls down the selected bit pair lines. Such
complications are not needed if the res...