RICE (US)—Scientists have created the first two-terminal memory chips that use only silicon, one of the most common substances on the planet, in a way that should be easily adaptable to nanoelectronic manufacturing techniques.

The work promises to extend the limits of miniaturization subject to Moore’s Law, a prediction made by Intel co-founder Gordon Moore that the number of transistors on a chip will double about every two years.

Last year, researchers in the lab of James Tour, a professor at Rice University, showed how electrical current could repeatedly break and reconnect 10-nanometer strips of graphite—a form of carbon—to create a robust, reliable memory “bit.”

At the time, they didn’t fully understand why it worked so well. Now, they do. It turns out the circuit doesn’t need carbon at all.

Jun Yao, a graduate student in Tour’s lab and primary author of the paper that appears today in the online edition of Nano Letters, confirmed his breakthrough idea when he sandwiched a layer of silicon oxide, an insulator, between semiconducting sheets of polycrystalline silicon that served as the top and bottom electrodes.

Applying a charge to the electrodes created a conductive pathway by stripping oxygen atoms from the silicon oxide and forming a chain of nano-sized silicon crystals.

Once formed, the chain can be repeatedly broken and reconnected by applying a pulse of varying voltage.

The nanocrystal wires are as small as 5 nanometers (billionths of a meter) wide, far smaller than circuitry in even the most advanced computers and electronic devices.

“The beauty of it is its simplicity,” says Tour, a professor of chemistry, mechanical engineering, materials science, and computer science. That, he says, will be key to the technology’s scalability.

Silicon oxide switches or memory locations require only two terminals, not three (as in flash memory), because the physical process doesn’t require the device to hold a charge.

It also means layers of silicon-oxide memory can be stacked in tiny but capacious three-dimensional arrays.

“I’ve been told by industry that if you’re not in the 3-D memory business in four years, you’re not going to be in the memory business. This is perfectly suited for that,” Tour says.

“Manufacturers feel they can get pathways down to 10 nanometers. Flash memory is going to hit a brick wall at about 20 nanometers. But how do we get beyond that? Well, our technique is perfectly suited for sub-10-nanometer circuits,” he says.

The Texas-based tech design company PrivaTran is already bench testing a silicon-oxide chip with 1,000 memory elements built in collaboration with the Tour lab. “We’re real excited about where the data is going here,” says PrivaTran CEO Glenn Mortland, who is using the technology in several projects supported by the Army Research Office, National Science Foundation, Air Force Office of Scientific Research, and the Navy Space and Naval Warfare Systems Command Small Business Innovation Research (SBIR), and Small Business Technology Transfer programs.

“Our original customer funding was geared toward more high-density memories,” Mortland says. “That’s where most of the paying customers see this going. I think, along the way, there will be side applications in various nonvolatile configurations.”

Yao had a hard time convincing his colleagues that silicon oxide alone could make a circuit. “Other group members didn’t believe him,” says Tour, who adds that nobody recognized silicon oxide’s potential, even though it’s “the most-studied material in human history.”

“Most people, when they saw this effect, would say, ‘Oh, we had silicon-oxide breakdown,’ and they throw it out,” he says. “It was just sitting there waiting to be exploited.”