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Abstract

The open collector driver circuit illustrated is capable of sinking a predetermined current magnitude in the Down level. When input A is Up, the T1 emitter is biased off such that T2 must conduct, turning on T3. Output A will go Down. When input A is pulled Down, T2 will turn off such that T3 is off. Output A will be pulled Up. Schottky barrier diode (SBD) S3 is included to level shift such that an acceptable noise tolerance is established for the down-level input. Diodes D1, D2 and D3 clamp the base of T1 to provide an acceptable noise tolerance for the up-level input. Select/inhibit operation is established via transistor T4. When Z is Up, the collector of T4 is pulled Down. This pulls Down the base of T1 which cuts off any emitter current from input A during the inhibit mode of operation.

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United States

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English (United States)

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Open Collector Driver Circuit

The open collector driver circuit illustrated is capable of sinking a predetermined
current magnitude in the Down level. When input A is Up, the T1 emitter is
biased off such that T2 must conduct, turning on T3. Output A will go Down.
When input A is pulled Down, T2 will turn off such that T3 is off. Output A will be
pulled Up. Schottky barrier diode (SBD) S3 is included to level shift such that an
acceptable noise tolerance is established for the down-level input. Diodes D1,
D2 and D3 clamp the base of T1 to provide an acceptable noise tolerance for the
up-level input. Select/inhibit operation is established via transistor T4. When Z is
Up, the collector of T4 is pulled Down. This pulls Down the base of T1 which
cuts off any emitter current from input A during the inhibit mode of operation.
SBD diode S1 is included to assure that T2 is also off, causing T3 to be off.
Therefore, the output will go to the + state (inhibit mode). SBD diode S2 is
included to decrease the disable delay by removing the transient charge from the
emitter of T2. This results in T3 turning off more rapidly. S2 may be integrated
within the collector of T4, thus preserving chip silicon area.