Why is Solid State Lighting (SSL) so important to semiconductor equipment and material suppliers? The need to save energy will propel SSL into a huge market… but only if the cost of those bright white LEDs can be reduced to the cost range of a normal light bulb.

Semiconductor-related costs account for about 60% of the typical LED-based luminaire, 40% for the LED itself and another 20% for the driver/power supply, and have the most potential to come down sharply in the near term. Equipment suppliers see a path to reducing LED production cost by 2X within five years, partly by applying some learnings from the high-volume semiconductor business. And applying the experience of other thin-film sectors in using roadmaps and cost of ownership models to set priorities for investment could be a big help as well, with the U.S. Department of Energy just out with an initial sector roadmap, and work planned on a cost-of-ownership model.

Veeco: Bringing Down SSL Costs

Equipment makers say there are real options for making big improvements in process yields and productivity to bring down SSL costs. Veeco, KLA-Tencor and Ultratech, for example, each project 2-3X potential improvement, both from evolutionary improvements in existing tools for what’s becoming a higher volume market, and from completely new approaches based in part on applying experience in other thin-film manufacturing to the specific needs of the HB-LED sector.

“We think overall epitaxial processing cost has to come down 3X, and we see a path to be able to do that,” says Jim Jenson, VP of marketing for the MOCVD business at Veeco Instruments, Inc. (Plainview, NY). He notes progress on development of better uniformity and repeatability, optimized flow geometries, better temperature control, faster processing time, improved system architecture and optimized batch sizes, though it could take a few years for all these developments to get into high-volume production.

The key epitaxial deposition process, which can take long hours per batch of 45 2-inch sapphire wafers, and determines much of the quality of the LED device in final binning is one clear focus for better uniformity and better throughput. The MOCVD tool grows the whole stack— the buffer layer, the bulk GaN layer, and the lower temperature p-n junction active region— with atomic layer precision, on materials with mismatched thermal properties. To maximize yield, wafer curvature is carefully controlled during the MOCVD process so the wafer is as flat as possible at 700-800°C for deposition of the critical layers.

The initial industry roadmap from DOE sets a goal of 70% improvement in within-wafer uniformity by 2015, 60% improvement in wafer-to-wafer, which would mean a 68% drop in epitaxy cost.

Veeco argues that its current design gets a uniform gas distribution by a laminar top-to-bottom flow, which gets the gas past the wafer table and away from the wafers after reaction, preventing deposition buildup on the chamber sides and ceiling to eliminate the need for downtime for frequent cleaning. It also has in-situ metrology that continually samples temperature, reflected light (to indicate film composition and thickness) and curvature on the wafers. Jenson notes that plenty of headroom exists for improvements in metrology that could make a big difference, such as better temperature measurement and control.

Another more radical option under consideration by both the established and potential new suppliers is to divide the process into separate chambers optimized to the different requirements of the different layers, typically using hydride vapor phase epitaxy (HPVE) for the thick GaN. But this equipment to date is not yet high volume. Oxford Instruments, for example, recently announced the first multiwafer HVPE reactors.

Applied Materials Making Progress on MOCVD Solutions

Applied Materials, Inc. (Santa Clara, CA) reports it’s making progress on possible MOCVD solutions as well. “We see techniques from IC processes used for decades that would apply,” says Pat Lamey, strategic marketing and new business development for the energy and environmental solution group. He notes that Applied’s development focus is now getting feedback from customers, and is based on a combination of commonly used MOCVD processes and “some technology that’s been written about for decades but never brought to production.”

Lamey also reiterates that better process control is key to improving overall LED yields and costs, because it’s crucial to overall throughput and performance. “We’re seeing a segment of the solid state business with potential for significant improvement in the next half decade, and the sooner we can bring the production techniques and controls known from our other technologies and products, the faster it will move into the market place,” says Lamey. “A roadmap will be a particularly helpful, especially since the LED industry is transitioning from a two-inch substrate to a 100mm substrate,” he notes.

Likely to propel the biggest jump in manufacturing productivity, however, could be the entry of some big silicon chip makers who are used to doing very controlled production in very high volumes. “The customer base is evolving as new players from the IC industry enter the field,” says Lamey, who adds, “Their entry will have a huge impact on manufacturing technology."

Improve Defect Inspection and Source Analysis, says KLA-Tencor.

KLA-Tencor Corp. (Milpitas, CA) sees another potential 2X cost reduction from improvements in defect inspection and defect source analysis, according to Richard Solarz, KLA-Tencor senior director of technology. He says that the LED industry currently lacks both appropriate inspection equipment to find the critical defects and efficient systems to figure out what’s causing them. Tools developed to inspect finer features on silicon for the IC industry find a lot of defects that don’t matter for LEDs, and can’t find others that do. They can’t differentiate the problematic micropits or threading defects in sapphire from the particles that don’t matter, and they can’t bin the finished die by the qualities of interest. And laser-based bare wafer/film surface analysis tool in the front end developed for the hard disk industry can’t talk to the image-based patterned-wafer inspection tool in the backend, developed to inspect wafer-level chip packaging, making it difficult to quickly track defects back to their source.

“Now that we understand the key defect needs of many of the LED manufacturers, we have identified key changes we need to make in our tools to isolate these defects. And we need to overlay the defect maps from the tools,” says Solarz. “Working with our customers, we believe that we can reduce manufacturing cost in many cases by as much as a factor of two.”

“There are opportunity costs in serving these emerging industries,” Solarz notes, as from the perspective of the $250B semiconductor industry, the $5 billion LED market looks like very tiny niche to justify investment in equipment development, despite its growth prospects. “Without clear roadmaps and customer alignment in solid state lighting markets, it is riskier to assign resources to this market. Roadmaps will certainly help us anticipate and design improvements to our inspection tools in a more timely fashion to meet the lighting industry’s needs,” he notes, pointing to the lengthy work likely needed to develop inline monitoring of indium clusters, and to the difference in opinion about the need for a color quality monitor. “The answers range from solid ‘yes’ to solid ‘no’,” says Solarz. “People ask us for a custom tool, but if we knew everyone wanted one, we would build it.”

Ultratech Sees Clear Path to 2X Lithography Cost Reduction

Ultratech, Inc. (San Jose, CA) argues that there’s also a clear path to 2X reduction in lithography costs, as well, from moving from mask aligners to 1X projection steppers. The company argues that the SSL sector’s move to larger wafers with more warp, and smaller feature size, means projection lithography will bring better yields and lower cost of ownership.

The transition from 2-inch to 4-inch wafers means 4X more die per wafer, but also means wafer warpage becomes more of a problem. With 2-inch wafers, warp is typically only _25 microns, so mask aligners work fine. But at 4-inch, there may be >100 microns of warp, and at 6-inch, >200 microns, making proximity lithography problematic, argues CTO Andy Hawryluk. And this is not always a regular wafer to wafer curvature like Pringles potato chips, but can be an irregular wafer-to-wafer variation more like a Lays potato chip, from the local temperature variations in deposition. Producers are also moving to slightly smaller feature size. The typical 5 micron contacts obscure the LED a bit, so reducing the contacts down to 1 micron or even below can produce a bit more light out of the die— resolution where defect density starts to limit yield on mask aligners, says Hawryluk.

The company has sold LED makers more than 20 of these projection tools to date, based on an equipment platform used for power devices, MEMS and thin-film heads. “The number one driver is yield,” says Doug Anberg, VP of advanced stepper technology, who claims the improvement makes up for the cost of the tool in a year. Some producers are trying low-cost used reduction steppers, but their high NA means a low depth of focus that creates problems with the warped surface.

Ultratech is developing a new model 1X projection stepper specifically designed for the LED market, slated for introduction mid-2010. Anberg says the re-design of the older tool uses better current-generation electronics and other component technology that cut both the purchase price and maintenance costs. Designed specifically to deal with warped LED wafers, the tool maps and tilts the wafer to adjust the focus section by section. It also adds a robust vision system that can see and align to targets through the epi layers that tend to obliterate them.

For resists requiring high exposure doses, additional throughput gains are expected with follow-on enhancement projects that will reportedly improve throughput from _64 wph now to 78.6 wph for 4inch wafers, to reduce the total cost of ownership by up to 50% on 4-inch wafers, and potentially 60% on 6-inch.

EV Group: Nanoprinting to Extract More Light

EV Group (EVG; St. Florian, Austria) sees potential for improving LED efficiency by structuring the surface by nanoimprint to extract more light. Most producers are exploring the technology, reports Paul Lindner, executive technology director, but most are still in development, with cost of materials and throughput remaining concerns.

The EVG 850 automated temporary bonding system

Wafer-level optics or packaging could also help bring down costs significantly. “With larger wafers, wafer-level packaging becomes more interesting,” says Lindner, noting that 6-inch wafers are coming. “We are looking very carefully at this.” If even one of the wafers was high yield, and costs were low, a wafer-level bonding process with singulation and binning at the end could be effective, though Lindner says that is very difficult to get the yield information needed to evaluate the process. Wafer-level processes for imprinting optical lenses on top of the light, based on technology developed for CMOS image sensors, might also be possible.

Now that the LED makers need thin wafers for better efficiency, some producers still process the thin wafers, which can leads to breakage. Most users, however, now temporarily bond the wafers to a rigid carrier, with different degrees of automation, which improves yields. Bonding throughput is about 25 wafers per hour, though work is underway on systems to bond more wafers at once.

EVG is also a long time supplier of mask aligners to the sector. Lindner argues that mask aligners remain the most cost effective choice, with users getting throughputs in the 100-200 wafers per hour range, and not pushing for solutions to any pressing unsolved problems in lithography, nor asking for projection steppers.

“We have individual customer roadmaps for what the requirements are for the next generation mask aligner, but not what that means for the LED,” says Lindner. “We’re missing the consolidated information for the industry for where the improvements should be overall. A roadmap would be very helpful.”

Sierra Ventures: Monumental not Incremental Improvements

Others suggest that the opportunities still exist for bringing down the cost of LEDs from totally new approaches, rather than from incremental improvements to the current processes. Robert Walker, principal at Sierra Ventures, and a veteran of HB LED manufacturing, suggests that if someone did figure out how to put the epi layers of GaN on silicon, then the whole downstream process could be run in an old 6-inch CMOS fab very efficiently. Or the epi layers could be patterned to grow in islands for much less warpage.

LED professionals, meanwhile, caution the silicon guys that LEDs are an alternative universe where their core assumptions about device scaling, wafer size, yield management and automation don’t necessarily apply. “If you’re a CMOS guy, the first thing you should do is forget everything you know,” jokes Walker, noting a list of differences. The LED is going to stay a single diode at sizes around 1 mm2. Larger wafer diameters are only of modest importance when the bottleneck MOCVD chamber already produces large batches of smaller wafers. Manual wafer handling may be cheaper than automation with fewer, longer steps, when the batch of little wafers may sit in the reactor for much of the workday.

SEMI is exploring ways to help support member needs for ongoing roadmap and cost information and other possible pre-competitive working groups.