IBM0436A1ANLAA and IBM0418A1ANLAA are 1Mb Synchronous Register-Latch Mode, high-per-formance CMOS Static Random Access Memories (SRAM). These SRAMs are versatile, have a wide input/output (I/O) interface, and can achieve cycle times as short as 4.5ns. Differential K clocks are used to initiate the read/write operation; all internal operations are self-timed. At the rising edge of the K

clock, all address, write-enable, sync select, and data input signals are registered internally. Data out-puts are updated from output registers off the falling edge of the K clock. An internal write buffer allows write data to follow one cycle after addresses and controls. The device is operated with a single +3.3V power supply and is compatible with 2.5V LVTTL I/O interfaces.

The Late Write function allows for write data to be registered one cycle after addresses and controls. This fea-ture eliminates one bus-turnaround cycle, necessary when going from a read to a write operation. Late write is accomplished by buffering write addresses and data so that the write operation occurs during the next write cycle. When a read cycle occurs after a write cycle, the address and write data information are stored tempo-rarily in holding registers. During the first write cycle preceded by a read cycle, the SRAM array is updated with address and data from the holding registers. Read cycle addresses are monitored to determine if read data is to be supplied from the SRAM array or the write buffer. The bypassing of the SRAM array occurs on a byte-by-byte basis. When only one byte is written during a write cycle, read data from the last written address has new byte data from the write buffer and remaining bytes from the SRAM array.

Mode Control

Mode control pins M1 and M2 are used to select four different JEDEC-standard read protocols. This SRAM supports single clock, register latch operation (M1 = V

DD

, M2 = V

SS

). This datasheet describes single clock

register latch functionality only. Mode control inputs must be set at power up and must not change during SRAM operation. This SRAM is tested only in the register-latch mode.

Sleep Mode

The sleep mode is enabled by switching the synchronous signal ZZ High. When the SRAM is in the sleep mode, the outputs go to a High-Z state and the SRAM draws standby current. SRAM data is preserved and a recovery time (t