The Race To 10/7nm

Amid the ongoing ramp of 16/14nm processes in the market, the industry is now gearing up for the next nodes. In fact, GlobalFoundries, Intel, Samsung and TSMC are racing each other to ship 10nm and/or 7nm technologies.

The current iterations of 10nm and 7nm technologies are scaled versions of today’s 16nm/14nm finFETs with traditional copper interconnects, high-k/metal-gate and low-k dielectrics. In finFETs, the control of the current is accomplished by implementing a gate on each of the three sides of a fin.

Fig. 1: FinFET vs. planar: Source: Lam Research

But not all of today’s 10nm and 7nm technologies are alike, as the node numbers and specs among vendors are different and confusing. In a nutshell, Intel’s 14nm process is roughly equivalent to 10nm from other foundries in terms of specs, and Intel’s 10nm is similar to 7nm from its rivals. In addition, a full-scaled process from Intel and others is now being extended from the traditional two-year cadence to roughly 2.5 to 3 years.

Regardless of the nomenclature or the timing, though, all chipmakers face similar challenges at 10nm and 7nm. The processes are becoming more complex, making it difficult to find the killer defects that impact yield. In addition, patterning remains challenging. And at some point during 7nm, some hope to insert extreme ultraviolet (EUV) lithography, a move that brings more risk into the equation.

Cost, of course, is key because only a select group of foundry customers with deep pockets can afford 10nm and 7nm. With that in mind, the big question for foundries and their customers is whether there is enough demand and volume to obtain a sufficient return at these nodes. Another uncertainty is whether the returns are enough to sustain the R&D costs for 5nm.

So will 10nm and/or 7nm blossom or fizzle out? “Right now, it’s too early to tell,” said Samuel Wang, an analyst at Gartner. “Big or not depends on many factors, such as yield, fab cycle times, cost and others.”

Others have a different viewpoint. “Digital designs from Apple and Qualcomm are migrating to 10nm and 7nm,” said Handel Jones, chief executive of International Business Strategies, a market research firm. “So 10nm/7nm will be a big technology node with wafer capacity in excess of 200,000 wafer starts per month by 2025.”

Jones noted that 10nm and/or 7nm are likely to be long-running nodes, and for good reason. If 5nm goes into production, the cost of technology will be astronomical. “So, high-volume wafer users will stay at 10nm/7nm for multiple generations of designs,” he said.

Clearly, customers will need to get a handle on the manufacturing issues in order to have more realistic expectations about their 10nm and/or 7nm design schedules. Semiconductor Engineering has taken a look at 10nm/7nm and highlighted the difficult process steps.

Node confusion
Not all will move to 16nm/14nm and beyond. For many, it’s too expensive or not required. And many trailing-edge processes in older fabs remain viable and in demand, including 200mm technology. “For 8-inch, we are fully loaded to meet the growing demand of our customers for power management, RF switches and embedded non-volatile memory,” said Po Wen Yen, chief executive of UMC, in a recent conference call.

In fact, there is no one technology that can fit all needs. For example, GlobalFoundries is readying a 22nm FD-SOI technology for low-power applications. “FD-SOI makes sense for certain people,” said Gary Patton, chief technology officer at GlobalFoundries. “FinFETs makes sense for certain people.”

For those who migrate beyond 16nm/14nm, it will require deep pockets. In total, it will cost $271 million to design a 7nm chip, according to Gartner. In comparison, it costs around $80 million to design a 16nm/14nm chip and $30 million for a 28nm planar device, the research firm said.

Besides cost, foundry customers face other challenges, as they must weigh the various and confusing options from chipmakers. Here are the latest roadmaps among the foundries:

• Intel will ramp up 10nm finFETs by year’s end, with 7nm and 5nm in R&D.
• TSMC is shipping 10nm, with 7nm in risk production.
• Samsung is shipping 10nm, with plans to develop 8nm, 7nm and 6nm.
• GlobalFoundries skipped 10nm and is moving to 7nm.

The choices are complicated as chipmakers release a range of half nodes. “I suspect Samsung’s 8nm is a relaxed version of their 7nm using multiple patterning,” Gartner’s Wang said. “Samsung’s 6nm is a tighter version of their 7nm, which will be comparable with Intel’s 7nm.”

Adding to the confusion is that each chipmaker views the market differently. For example, Intel says 10nm will be a big node. In contrast, GlobalFoundries has a different opinion, saying that 7nm has some advantages over 10nm. 7nm hits a more desirable power, performance and area scaling target for foundry customers, according to GlobalFoundries’ Patton. “The scaling factor for 10nm is pretty modest,” Patton said. “7nm will be a long node.”

As stated above, though, Intel’s 14nm process is similar to 10nm from others, while Intel’s 10nm is equivalent to 7nm from the competitors. “You have to ignore the node names,” said Mark Bohr, senior fellow and director of process architecture and integration at Intel. “(Intel’s foundry competitors) are developing advanced technologies and they’re about three years behind Intel in terms of their capabilities, despite the names.”

Still, all chipmakers are moving in the same direction. “7nm, for example, will bring with it several new major inflections alongside typical smaller changes in order to continue to scale finFETs and stave off an architecture change to something like gate-all-around,” said Mike Chudzik, senior director of the Transistor and Interconnect Group at Applied Materials.

Chudzik sees a shift toward self-aligned quadruple patterning (SAQP), cobalt fill for contacts and self-aligned gate contacts. “7nm foundry will bring widespread adoption of sub-40nm pitches, which in turn drives SAQP or EUV,” Chudzik said. “Given the state of EUV, we’ll see SAQP as the patterning solution of choice with perhaps some select use of EUV steps.”

Mask/litho challenges
The process starts with a photomask. A chipmaker designs an IC, which is then translated into a file format. Then, a photomask is developed based on that format.

The photomask is a master template for a given IC design. After a mask is developed, it is shipped to the fab. The mask is placed in a lithography tool. The tool projects light through the mask, which in turn patterns the images on a wafer.

At 10nm, vendors will use today’s 193nm immersion-based optical lithography and multiple patterning. Then, TSMC will extend immersion/multi-patterning at 7nm with plans to insert EUV at the latter stages of 7nm. In contrast, Intel and Samsung hope to insert EUV sooner than later at 7nm.

So initially, chipmakers will use traditional optical masks, which are becoming more complex at each node. “Until EUV is ready for production use, the industry is also going to see an increase in the number of masks required to pattern one wafer layer,” said Aki Fujimura, chief executive of D2S.

“On top of that, optical lithography has already reached its limits per mask layer, which is shifting more burden onto the mask in order to further extend scaling until EUV arrives,” Fujimura said. “This equates to increasing mask complexity to address the need for control and resilience to manufacturing variation. Overlay requirements will be more difficult as well, which makes the position accuracy of mask features just as important as CD accuracy.”

As a result of the growing complexity with optical lithography, chipmakers want EUV, which promises to simplify the patterning flow. In EUV, a power source converts plasma into light at 13.5nm wavelengths, enabling finer features on a chip.

EUV requires a different mask type. An optical mask consists of an opaque layer of chrome on a glass substrate. An EUV mask consists of 40 to 50 alternating layers of silicon and molybdenum on a substrate.

Today, the industry is capable of producing EUV masks despite some gaps in the arena. EUV pellicles, for one, is the main gap.

“The mask infrastructure can be made ready for EUV,” Fujimura said. “But ‘can be’ and ‘is’ are different things. Furthermore, learning to use each new technology that is needed in the mask infrastructure and then learning to integrate them into an operational flow for high-volume manufacturing of EUV masks still requires investment and time.”

EUV lithography itself, meanwhile, is still not in production amid a number of delays with the technology. The power source, resists and tool uptime are the main issues.

EUV is making progress, though. ASML is readying its latest EUV scanner—the NXE:3400B. Initially, the tool will ship with a 140-watt source, enabling a throughput of 100 wafers per hour (wph).

To put EUV in production, however, chipmakers want 200 watts or more of source power. A 210-watt source, which enables 125 wph, is in R&D at ASML.

Despite the challenges, chipmakers will likely insert EUV at 7nm and/or 5nm. What about the cost of EUV? “We traditionally calculate cost by how much it costs to make a wafer. Then you decide how much, therefore, the die cost is, which factors in your yield. But there is another element, and that’s cycle time. It only takes five or six layers for me to replace multi-pattering with EUV. And I can knock off 20 masking steps, plus depositions, etches and so forth. If you think it’s 1.5 days between masking steps in multiple patterning, I save a month on my cycle time using EUV,” said Harry Levinson, senior fellow and senior director of technology research at GlobalFoundries.

Transistor trends
Meanwhile, chipmakers are following the same transistor path at 10nm and 7nm–they are extending the finFET and making the fins taller and thinner.

For example, at 22nm, Intel’s finFET technology had a fin pitch of 60nm and a fin height of 34nm. In comparison, the fin pitch and fin height are both 42nm for Intel’s 14nm.

At 10nm, Intel’s fin pitch is 34nm and the fin height is 53nm, meaning the fins are taller. “We’ve also packed them closer together to improve transistor density,” said Kaizad Mistry, vice president and co-director of logic technology development at Intel. “And we made them taller to improve transistor performance.”

Taller fins boost the drive current in the device, but they are also subject to unwanted parasitic capacitance, which could alter the ideal behavior of the circuit.

Intel, meanwhile, also scaled the gate pitch and moved to a so-called contact-over-active-gate scheme. Traditionally, the contact has been situated on the gate, but away from the active transistor. “In our 10nm technology, we allow the contact to be placed directly above the active transistor,” Mistry said. “So, you can pack transistors closer together.”

Fig. 3: Gate contact. Source: Intel

Intel’s new gate scheme will require precise alignment. And forming the gate itself is also challenging. “Cycle times are increasing for this step, driven by the complexity of the stack,” said Mohith Verghese, director of global product marketing at ASM International. “The metal gate stack is also getting very complicated. It is not just a matter of having an NFET and a PFET metal. There are several layers in the metal stack. And issues, such as nucleation of thin layers, fine tuning of threshold voltage for multi-Vt devices, and fine tuning selective removal and etch steps, all add to increased cycle time.”

BEOL/MOL blues
Basically, a chip has two main structures—the transistor and interconnects. The transistor, as in a finFET, serves as a switch in a device and resides on the bottom of the structure. Transistors are manufactured in the front-end-of-the-line (FEOL) in a fab.

The interconnects, which reside on the top of the transistor, are made in the backend-of-the-line (BEOL) in a fab. Starting at 22nm, chipmakers added a new layer called the middle-of-line (MOL), which connects the transistor and interconnects.

Both the BEOL and MOL are critical. “We can make the transistor faster and faster. But if we cannot supply the current and electrons in an efficient way to the transistor, we cannot harvest the benefits of the faster transistor,” said Keyvan Kashefi, global product manager at Applied Materials. “As we move to 7nm, the delays and the performance become limited, mainly by the contact and back-end-of-line, because those become the bottleneck.”

The interconnects—tiny copper wiring schemes in devices—are becoming more compact at each node, causing a degradation in performance and an increase in the resistance-capacitance (RC) delay in chips.

For the interconnects, chipmakers form a sea of tiny trenches, which are filled with conductive copper. Typically, the trenches are lined with a thin barrier layer (tantalum nitride) and a liner (tantalum). At each node, the liner/barrier film is taking up too much room and the volume of conductive copper is shrinking. So, some replaced tantalum with cobalt for the liner. “With cobalt, we significantly reduced the thickness of the liner,” Kashefi said.

At 7nm, chipmakers hope to reduce the liner/barrier thickness even further. For this, they are evaluating new materials, such as cobalt and ruthenium for the liner and manganese for the barrier.

Meanwhile, the separate MOL structure is fast becoming the big bottleneck. The MOL consists of upper and lower layers. In the upper layers, there are tiny contacts, which are three-dimensional structures with a gap. The gap is filled with tungsten, sometimes called a tungsten plug. The tungsten plug provides an electrical connection from the interconnects to the transistor.

As the features shrink, the size of the tungsten plug, and the volume of materials inside the structure, decreases. This, in turn, causes unwanted contact resistance in devices. “As the size shrinks, less and less area and volume are available for the current conductance,” Kashefi said. “So the main focus is how to maximize that volume of the conductor and how to make the conductor less resistive.”

To solve that problem, Applied Materials recently introduced a metal-organic tungsten film. The film can replace the barrier and nucleation layers and performs the functions of both. This increases the volume of the tungsten and lowers the contact resistance.

Fig. 5: FinFET at 16/14nm, 10nm, 7nm. Source: Applied Materials

Now, chipmakers are focusing on the next battle—the lower layers of MOL. The lower layers involve a separate contact to the junction, which resides on the transistor itself. The contact is also based on tungsten.

In scaling, the metal-to-semiconductor contact develops a resistive Schottky barrier. “Schottky barrier height could account for 32% degradation in the drive current of an NMOS silicon-based finFET when compared to ideal contacts,” said Reza Arghavani, a managing director at Lam Research, during a recent presentation.

To solve that problem, some are proposing to replace tungsten with cobalt for this contact.
Process control
Meanwhile, metrology, the science of measurements, is used to characterize tiny films and structures. Metrology helps to boost yields and prevent defects in the fab, which impacts the overall cost for chipmakers.

Planar devices require six different critical dimension (CD) measurements. The measurements are conducted using a scanning electron microscope (CD-SEM). At advanced nodes, though, the days of using just a CD-SEM are over. “You are going to have 30 different metrology techniques in the fab,” said David Fried, chief technology officer at Coventor.

For example, finFETs require 12 or more different CD measurements, such as the gate height, fin height and sidewall angle. For this, chipmakers use CD-SEMs and scatterometry. Scatterometry measures the changes in the intensity of light in a device.

Then, for film thickness measurements, metrologists require optical and X-ray metrology. “The challenge is that one measurement or metrology technique doesn’t necessarily solve all of the problems,” Fried said. “There are so many different things you need to measure in different structures and films.”

Finding killer defects is also difficult. Chipmakers use optical and e-beam systems to find defects. “The cadence of Moore’s Law may be slowing, but defect challenges seem to be accelerating,” said Mark Shirey, vice president of customer engagement at KLA-Tencor.

At each node, the defects are becoming smaller and harder to find. “Lateral scaling, namely denser transistor layouts, drives the need to detect smaller defects and increases the need for design-aware inspection and review. Vertical scaling, such as taller fins, drives the need for detecting and verifying buried defects,” Shirey said.