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Hierarchical separation of dynamic power components during PVT-independent contributor based power abstraction for accurate multi-corner power analysis

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method to achieve accurate multi-corner dynamic power analysis by hierarchically separating the dynamic power components, based on process, voltage, and temperature (PVT) dependence, while performing PVT independent contributor based power abstraction.

Country

Undisclosed

Language

English (United States)

This text was extracted from a PDF file.

This is the abbreviated version, containing approximately
46% of the total text.

Page 01 of 4

Hierarchical separation of dynamic power components during PVT -independent contributor based power abstraction for accurate multi -corner power analysis

1. Introduction

Macro/IP Block

C orner 1 … Corner N

Cell

Library

Cell P ower

M acro Power

Library

Characterization

Contributor

Abstract

M odel

Generation

Contributor

based M acro P ower Abstract

Corner 1 …Corner N Workload 1…Workload N

Chip

Chip Level P ow er Analysis

Input to Wafer Test, System Planning, P ower Sorting and Binning

Figure 1. PVT independent contributor based power abstraction and analysis

PVT-independent contributor based dynamic power abstraction and analysis was introduced in [1, 2]. As shown in Figure 1, it abstracts dynamic power as a contributor (capacitance) at each level of design hierarchy (standard cell, IP types, and chip). During power analysis, at any level of design hierarchy of interest, these PVT-independent dynamic power contributors are evaluated at a particular PVT & workload condition to compute dynamic power.

Ideally, dynamic power from these PVT-independent abstracts can be calculated as C* V^2 * f * event. But in realityAC power = C * V^x * f * event , where x is abstracted to be a single number > 2 for a chip power rail, and (x-2 ) captures the dependency of effective switching capacitance on voltage [2]. x is extracted from post-silicon hardware power measurements for a particular rail.

The above approach is not preferred in next generation technologies like 14nm. This is due to the following reasons. 1) There is a notable increase in cross-current (short circuit) power contribution to overall chip power (especially in technologies where the threshold voltage is low). Unlike other dynamic power components, cross-current power is heavily dependent on threshold voltage, and thereby also on operating voltage [3]. 2) Other contributors to internal power like miller capacitance, transistor gate and drain capacitance are also weakly dependent on threshold voltage, and thereby operating

1

Page 02 of 4

voltage.

These effects (especially effect 1) limit the accuracy of the existing state-of-art contributor based approach [1, 2] of hierarchically abstracting dynamic power as a PVT-independent capacitance, and then computing dynamic power using this capacitance, across multiple corners of PVT. The proposed approach overcomes these limitations by hierarchically separating dynamic power components based on process, voltage and temperature dependence during PVT-independent contributor based power abstraction.

This approach enables 1) accurate multi-corner pre-silicon dynamic power analysis for future technologies. 2) Aggressive pre-silicon power trade-off analyses like cross current power vs. slew. 3) Better tracking and optimization of pre-silicon power for the different ac power components at all levels of design hierarchy. For example, hierarchical tracking of cross-current power.