A semi custom design flow was used to implement and fabricate an analog circuit. The pixel level detector circuit was designed on a sea-of-gates called an analog-leaf-cell. Cadence Tools was used to design the schematic, layout, and simulate the analog circuit. Once the layout and schematic has been verified (LVS) on Cadence tools, a post extraction simulation is observed. When all specifications have been reached, the circuit design is ready to be fabricated and is sent out to MOSIS. Eight weeks later, the integrated circuit is fabricated and packaged into an IC chip and returned to students to be tested.