Following Multiple Patterns

The lithography market is in flux. Today, chipmakers plan to extend today’s 193nm immersion lithography and multi-patterning to at least 10nm and 7nm. For the most critical layers, though, it’s unclear if optical lithography can extend beyond 7nm. For that reason, chipmakers hope to insert extreme ultraviolet (EUV) lithography at 7nm and/or 5nm. To get a handle on the state of patterning, Semiconductor Engineering recently and separately sat down with Uday Mitra, vice president of strategy and marketing for etch and patterning at Applied Materials; Michael Lercel , director of product marketing at ASML; and Richard Wise, technical managing director at Lam Research. What follows are excerpts of those conversations.

SE: EUV lithography is not in mass production yet, but it is making progress. ASML is readying its latest EUV scanner—the NXE:3400B. Initially, the tool will ship with a 140-watt source, enabling a throughput of 100 wafers an hour. A 210-watt source is in development, enabling 125 wafers an hour. Where are we in EUV?

Lercel: (The NXE:3400B) is shipping soon. The target is still to have it run at 125 wafers an hour. The data we have shown is that we are running at about 100 wafers an hour now. It’s enough for companies to get started and get it integrated. It will be upgraded to the full 125 wafers an hour later. That will be 210 watts. We are working out the specifics of when to upgrade systems.

Wise: EUV is pretty much making steady progress. Power scaling, clearly, is on a good trajectory. We’ll see where it will end up in production. But there will be some progress as well as some challenges on power scaling. Resists are a significant and a remaining challenge.

SE: What else?

Wise: We are probably equally optimistic as we were last year. Last year, we were pretty clear. We need EUV for industry scaling. So now, we see steady progress. You see the rate and pace of people announcing the need for EUV, and the need for mask count reduction. The whole industry needs it to continue scaling.

Mitra: You have to look how the mask count is increasing. In the production flow, the fin is typically being done by SAQP. But in the cut, you are using three or four immersion steps. Who wants to use three or four immersion steps? It’s not only the cost, but it’s also how do you align these things together. So there, EUV makes perfect sense. But that doesn’t solve your overall edge placement problem. You still need materials innovations to solve that. And also it doesn’t solve all of your device issues. So, EUV helps with resolution. The problem with EUV is that it’s a point solution.

SE: Can you elaborate?

Mitra: At each node, the features are getting smaller and smaller. EUV still helps. Definitely, it’s a good building block. But after all, it’s a point solution. Gone are the days of simple geometric scaling enabled by litho. Now, it is more 3D and materials. So, if you look at the whole silicon process holistically, you had high-k/metal-gate and several generations of finFETs. Then, maybe you will have gate-all-around. All of these are being enabled by materials. And similarly, even in the patterning space, you traditionally just had scanners. Every two years, you had either a wavelength or numerical aperture change. That was until we came to 193nm immersion with 1.35 NA. And then it stopped. The void has been filled by materials. Then, EUV will come in. But once again, it’s a point solution. It’s 13.5nm wavelength at 0.33 NA. It’s not like two years later you get something else.

SE: Chipmakers have moved down the scaling path with various multi-patterning flows in the fab, such as self-aligned double/quadruple (SADP/SAQP) patterning and double patterning (litho-etch-litho-etch). This will get us to 7nm. But let’s say EUV doesn’t happen at 7nm and/or 5nm. Can we extend 193nm immersion to 5nm using self-aligned octuple patterning (SAOP)?

Lercel: Some have made presentations on SAOP. It’s tough to get beyond SAQP. I won’t predict it will never happen.

Wise: In the absence of EUV, we all know that 8 to 10 masks per level just becomes untenable.

Mitra: All of the capabilities are there for octuple patterning. It has its own challenges. How do you manage your distribution? You might have some pitch walking issues. The big challenge is the cuts. The question is how do you make all of those cuts without having massive overlay errors.

SE: Let’s say the industry inserts EUV at 7nm and/or 5nm. Chipmakers will continue to use immersion/multi-patterning for the lines and other parts of the flow. EUV may be used for the cuts and vias. Lithography can’t do it all, right?

Mitra: The devices are getting more 3D-like. And there are a lot more materials going into making the devices. And then, how you pattern the device involves a lot of materials engineering. It involves selective etch, selective deposition and selective removal.

Wise: Etch has been successful in immersion in reducing things like line-edge roughness. So, we focus a lot on things we can do in etch, deposition and cleans to help break the stochastic trade-off with resist sensitivities (in EUV).

SE: Let’s move to photoresists. Resists are light-sensitive materials. They form patterns on a surface when exposed to light. For EUV, they are critical. What about EUV resists?

Lercel: It looks like we are seeing continued progress. We saw some good stuff with the metal organic materials from Inpria, as well as the chemically amplified resists. The resist infrastructure looks like it is in place for 7nm. People would probably look for some incremental improvements before 5nm.

Wise: The resists today are 35mJ/c2 to 50mJ/cm2 to get good images. All the throughput and cost assumptions work around 20mJ/cm2. It’s a linear relationship. So if you are running 40mJ/cm2 instead of 20mJ/cm2, all of a sudden your scanners are twice as expensive. So it’s a big gap in terms of performance. Power scaling is seeing more steady progress. Resists are making progress, but it’s slow. Maybe a few years ago, we thought it would accelerate the way power scaling has done. The resists seem to be more fundamental and endemic to the physics.

SE: What else?

Wise: The first implementation for EUV will most likely be vias and contacts, because you get the mask count reduction. Positive tone materials are fairly mature and they are performing well. It seems likely they would stay as an organic material. But for cuts and pillars, you want a negative tone. And there is a potential gap in where your inorganics are and where we need them to be.

SE: Let’s move to the mask infrastructure. Basically, a pellicle is a thin, transparent membrane that covers a photomask during the production flow. The pellicle prevents particles and contaminants from falling on the mask. If a particle lands on a mask, the scanner would likely print an unwanted defect on a wafer. What about the pellicle for EUV?

Mitra: The biggest challenge is the pellicle. Having a pellicle that can withstand the power required is tough. The question for the pellicle is the absorption. How much of the light goes through is the problem.

Lercel: There has been a lot of progress since last year. We are working on basically industrializing the pellicle. We had an R&D site previously. But now, we are ramping up a sub-supplier to produce these in larger volumes. So we’ve tested a number of these, including on customer tools. We continue to drive down the defect levels.

SE: What else is going on in EUV pellicles?

Lercel: (The sub-supplier) is building the films. We have a company that effectively is like a MEMS foundry that we use. We actually mount the films to the pellicle frame at ASML. The other thing is that we now have pellicle mounting tools. Now, we have tools that we can ship to customer sites. Customers will get those soon. They can mount their own pellicles. It’s essential for the infrastructure.

SE: Today, the industry will use optical inspection to inspect EUV masks, although there are some resolution issues here. That’s why the industry wants actinic inspection, which uses the same 13.5nm wavelength as EUV. Actinic can supposedly find more defects in EUV masks, compared to optical. But the industry is still several years away from developing this tool. Do we really need actinic inspection?

Lercel: We have a strategy that (actinic inspection) doesn’t have to happen. The pellicle is removable. If you want to inspect the reticle, you can pop the pellicle off. And you can do any inspection, such as e-beam and optical. Then, you put the pellicle back on. Or, you can even do a wafer print check. That’s the other option. You print on the wafer and look for defects on the wafer.

SE: The industry would rather have an actinic tool, right?

Lercel: Our positon is that it doesn’t have to happen. A lot of customers would prefer it to happen, because you could inspect through the pellicle. You would also get the phase defects.

Hi memister. Good points. I will look into this…. Right now, though, DSA is not ready. Defects remain an issue. SAQP is ready…..Maskless isn’t happening. Imprint is targeted for NAND. Both lack funding. So, I don’t see another NGL besides multi-patterning or EUV. That’s not a good thing.