I even tried to port it to MiSTer. The code is in very beginning stage. It exploits Xilinx ability to synthesize non-synthesizable code. Most likely the code is being written by people who just start to learn HDL programming. I think it still needs couple years to wait for well organized code. Then it will be possible to port to other boards.

P.S.: there is no way to port it to MiST. Core requires a lot of BRAM.