Memory Scaling Challenges Detailed by Micron R&D Director

At LithoVision, Erik Byers, Director of R&D Process and Equipment Development for Micron Technology, shared his insight on Memory scaling trends, emerging technologies, 3D integration, and associated lithography challenges. Byers commented that when considering the major challenges to the cadence of DRAM and NAND scaling, resolution is not the primary limitation; in reality, difficulties including process margins (overlay, CDU, linewidth roughness), materials, equipment and process control capabilities, as well as metrology complexities must be overcome (Figure 1A). In addition, the economics of planar scaling is also a significant challenge. He commented that sub-20 nm lithography is enabled by fab and photomask complexity, and showed that pitch multiplication techniques are capable of patterning to the sub 1x nm node (Figure 1B).

Figure 1A. When considering the major challenges to the cadence of DRAM and NAND scaling, resolution is not the primary limitation (left image). Figure 1B. Byers showed pitch multiplication techniques are capable of patterning to the sub 1x nm node.

In the case of DRAM scaling, Byers cited problems such as overlay and patterning demands, structural stability, control capabilities, highly integrated/complex flows, and increasing metrology demands. DRAM process complexity drives a marked increase in the number of process steps to enable shrinks, while conversion capital expenditures scale with the number of steps, and there is significant reduction in wafer output per existing cleanroom area (Figure 2A). In contrast, NAND scaling is limited by physics. Word line to word line coupling creates a significant parasitic effect at small CDs and charge loss effects are also magnified at small dimensions (Figure 2B).

Figure 2A. Byers described the impacts of DRAM process complexity (left image). Figure 2B. He reported that NAND scaling is limited by physics.

The memory market is transforming, and Byers highlighted end market diversification with growth in embedded, enterprise, server, and client storage areas, without any one-size-fits-all architecture. As memory architecture is evolving, the focus is on balancing value across latency, endurance, volatility and cost. There are several alternative memory concepts being explored such as PCM, MVORAM, STTRAM and CBRAM (Figure 3A), which use new materials, storage concepts, and materials technology. It was explained that memory scaling will inevitably go three-dimensional (3D), but vertical integration presents a number of new challenges (Figure 3B). Small variations are magnified through the tall stacks, deep stacks bring further obstacles to planarization, and low temperature requirements necessitate new film innovations, etc.

Delving into litho challenges, Byers described the different areas of Micron’s lithography concentration across the DRAM, NAND, and Emerging Technology sectors, and noted that emerging technologies face unique issues such as alignment through deep/opaque stacks and overlay of the electrode to the small via. He noted that reducing process variation will be imperative to decreasing feature-to-feature variation for high-quality patterning.

Figure 3A. There are several alternative memory concepts being explored such as PCM, MVORAM, STTRAM and CBRAM (left image). Figure 3B. It was explained that memory scaling will inevitably go 3D, but vertical integration presents a number of new challenges.

Byers reported that local CD uniformity has scaled more than 100% from the 30 nm node, and this trend must continue to enable the DRAM roadmap. He cautioned that feature sizes are approaching the regime where linewidth roughness (LWR) has significant impact on device performance. In addition, the overlay budget, which is increasingly critical with sub 2xnm features, is pushing the capability of litho scanners and leaving little margin for process effects. For instance, for future nodes, the Process component represents 51% of the DRAM overlay budget. This makes it the largest opportunity for improvements through mark engineering and design, reticle contributions, substrate and stress effects, feed forward/back loops, metrology sampling, and lot based wafer to wafer corrections.

The high topography experienced in vertical integration creates new lithography depth of focus (DOF) challenges due to macro scale film non-uniformity (Figure 4). 3D NAND processes can also show systematic false field leveling as a result of the scanner leveling system penetrating to different depths within the array as compared to the periphery. Byers warned that within field false leveling errors can contribute to 50 nm or more of additional focus error. He showed Nikon scanner transparency detection enhancements are able to compensate for this and apply a correction to successfully mitigate the systematic error. Further innovations in modeling and process improvements will help as well. He commented that EUV also has many obstacles to achieve the line-edge roughness and CDU requirements for the advanced nodes (Figure 5A).

Figure 5A. Byers commented on obstacles to achieve the line-edge roughness and CDU requirements for the advanced nodes (left image). Figure 5B. He reiterated that 3D integration brings a new set of process hurdles and encouraged the audience to be prepared.

In his closing remarks, Byers stressed that DRAM technology scaling is reaching its limits, and it is difficult to maintain the cadence trend while also satisfying structural and cost per gigabyte requirements. Further, challenges with planar NAND scaling will fuel the push for 3D applications. These scaling limitations and diversifying applications create many opportunities for new memory technologies, and future memories will follow 3D integration (Figure 5B). Byers reiterated that 3D integration brings a new set of process hurdles and encouraged the audience to be prepared.