In nanowire-based logic, the semiconducting material (e.g., Si,
GaN, SiGe) is grown into individual nanowires rather than being part of the
substrate. This offers us the opportunity to stack multiple layers of
nanowires to create a three-dimensional logic structure which has high
quality semiconductors in all vertical layers. We detail a feasible
three-dimensional programmable logic architecture which can plausibly be
realized from layers of semiconducting nanowires, making only modest
assumptions about the control and placement of individual nanowires in the
assembly. This shows a natural path for continuing to scale areal logic
density once nanowire pitches approach fundamental limits. We show that
the three dimensional systems are volumetrically efficient, with the
surface area reducing roughly in proportion to the number of vertical
layers. We further show that, on average, delay is reduced 18% from
compact layout in three dimensions. For only a 20% area impact, we show
how to avoid adding any manufacturing steps to physically isolate portions
of nanowire layers.