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Quick Summary Multi level cells in PCM appear imminent A number of proposals exist to handle hard errors and lifetime issues of PCM devices Resistance Drift is a lesser explored phenomenon – Will become increasingly significant as number of levels/cell increases – primary cause of soft errors – Naïve techniques based on DRAM-like refresh will be extremely costly for both latency and energy – Need to explore holistic solutions to counter drift 2

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Phase Change Memory - MLC Chalcogenide material can exist in crystalline or amorphous states The material can also be programmed into intermediate states – Leads to many intermediate states, paving way for Multi Level Cells (MLCs) 3 Resistance AmorphousCrystalline (11)(00)(10) (01) (111) (000) (101)(011)(010)(001) (110)(100)

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System Level Solutions Dynamic events can affect reliability – Temperature increases can increase α and decrease drift time – Cell lifetime/wearout is also an issue – Soft error rate depends on prevalence of drift prone states These effects should be taken into account to dynamically adjust LARDD frequency Start with a low LARDD rate – Double rate when errors exceed pre-set threshold – Mark line as defunct when hard errors exceed pre-set threshold 12

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Reducing Overheads with Circuit Level Solution Invoking ECC on every LARDD increases energy consumption Parity – like error detection circuit is used to signal the need for a full fledged ECC error detect – Number of Drift Prone States in each line are counted when the line is written into memory – 0 is stored as a Flag for even number of Drift Prone States, 1 for odd – The Flag is computed at each LARDD – A Flag mismatch invokes a full-fledged ECC Reduces need for ECC read-compare at every LARDD cycle 13 (11) (00)(10) (01)