Using an MDE Approach for Modeling of Interconnection Networks

As System-on-Chips (SoCs) become more complex, high performance interconnection mediums are required to handle their complexity. Network-on-Chips (NoCs) enable integration of more Intellectual Properties (IPs) into the SoC with increased performance. In the recent MARTE (Modeling and Analysis of Real-time and Embedded Systems) Profile, a notion of multidimensional multiplicity has been proposed to model repetitive structures and topologies. This paper presents a modeling methodology based on that notation to model the delta network family of interconnection networks for NoC construction.