9/28/20045Importance of Avoiding Branch Stalls•Crucial in modern microprocessors, which issue/execute multiple instructions every cycle– Need to have a steady stream of instructions to keep the hardware busy– Stalls due to control hazards dominate•So far, we have looked at static schemesfor reducing branch penalties– Same scheme applies to every branch instruction•Potential for increased benefits from dynamic schemes– Can choose most appropriate scheme separately for each instruction• Branches to top of loop have different behavior (Taken) than “if (x == 0) return;” (Not Taken)– Can “learn” appropriate scheme based on observed behavior– Dynamic (hardware) branch predictionschemes• For both direction (T or NT) and target prediction• Key element of all modern microprocessors

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9/28/20046Dynamic Branch Prediction (1): Branch Prediction (History) Buffer•Small memory indexed by the low-order bits of the branch instruction–Storesasingle bitof information: T or NT• Starts off as T, flips whenever a branch behaves opposite to prediction– For now, assume supported in the IDstage• Benefits for larger pipelines, more complex branches•Problems with this simple scheme– Prediction value may not correspond to branch being considered

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