Pin Name Description
1 TDO JTAG Test Data Out
2 QACK Not Needed
3 TDI JTAG Test Data In
4 TRST JTAG Test Reset
5 HALTED Not Needed
6 Vcc Target 1.8 – 5.0V:
This is the target reference voltage. It indicates that the target has power and it is also used
to create the logic-level reference for the input comparators. It also controls the output logic
levels to the target. It is normally fed from Vdd I/O on the target board.
3.0 – 5.0V:
This input is used to detect if the target is powered up. If there is a current
limiting resistor between this pin and the target Vdd, it should be 100 Ohm or less.
7 TCK JTAG Test Clock
8 CKSI Not Connected ??
9 TMS JTAG Test Mode Select
10 <reseved>
11 SRESET Soft-Reset
12 GROUND System Ground
13 HRESET Hard-Reset
14 <reseved>
15 CKSO Not Connected on the 8421
16 GROUND System Ground

On-Chip Debug (OCD) connector

The internal OCD port uses an electrical standard known as JTAG/COP. The signals have to be buffered to protect the hardware from damage and we use a JTAG wiggler to do this.

Those with some electrical experience could build their own circuit, but most will opt for ordering one.