METHOD OF MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE - A method of manufacturing a photoelectric conversion device, comprises forming a first insulating film on a semiconductor substrate, forming a gate electrode by forming an electrically conductive layer on the first insulating film and patterning the electrically conductive layer, etching an exposed surface of the first insulating film, forming a charge accumulation region of a photoelectric converter by implanting impurity ions of a first conductivity type into the semiconductor substrate through a thinned portion of the first insulating film formed by the etching, removing the thinned portion, forming a second insulating film covering the semiconductor substrate and the gate electrode, and forming a surface region of the photoelectric converter by implanting impurity ions of a second conductivity type opposite to the first conductivity type into the semiconductor substrate through the second insulating film.

2010-12-09

20100311201

METHOD OF FORMING SUBSTRATE FOR USE IN IMAGER DEVICES - A method of fabricating a semiconductor substrate structure comprises forming an oxide region in contact with a first semiconductor, e.g. silicon, substrate, implanting P-type dopants into the first semiconductor substrate to form a P-doped region, bonding the oxide region to a second semiconductor, e.g. silicon, substrate, and removing a portion of the first semiconductor substrate before or after implanting.

Passivation process for solar cell fabrication - Embodiments of the invention contemplate the formation of a high efficiency solar cell using a novel plasma oxidation process to form a passivation film stack on a surface of a solar cell substrate. In one embodiment, the methods include providing a substrate having a first type of doping atom on a back surface of the substrate and a second type of doping atom on a front surface of the substrate, plasma oxidizing the back surface of the substrate to form an oxidation layer thereon, and forming a silicon nitride layer on the oxidation layer.

2010-12-09

20100311204

METHOD FOR FORMING TRANSPARENT CONDUCTIVE OXIDE - Embodiments disclosed herein generally relate to a process of depositing a transparent conductive oxide layer over a substrate. The transparent oxide layer is sometimes deposited onto a substrate for later use in a solar cell device. The transparent conductive oxide layer may be deposited by a “cold” sputtering process. In other words, during the sputtering process, a plasma is ignited in the processing chamber which naturally heats the substrate. No additional heat is provided to the substrate during deposition such as from the susceptor. After the transparent conductive oxide layer is deposited, the substrate may be annealed and etched, in either order, to texture the transparent conductive oxide layer. In order to tailor the shape of the texturing, different wet etch chemistries may be utilized. The different etch chemistries may be used to shape the surface of the transparent conductive oxide and the etch rate.

2010-12-09

20100311205

SEMICONDUCTOR DEVICE - The reliability of the semiconductor device which has the structure which stores a plurality of semiconductor chips with which plane sizes differ in the same sealing body in the state where they are accumulated via the insulating film which has adhesive property is improved.

2010-12-09

20100311206

Semiconductor Device and Method of Forming Through Hole Vias in Die Extension Region Around Periphery of Die - A semiconductor wafer contains a plurality of semiconductor die. The semiconductor wafer is diced to separate the semiconductor die. The semiconductor die are transferred onto a carrier. A die extension region is formed around a periphery of the semiconductor die on the carrier. The carrier is removed. A plurality of through hole vias (THV) is formed in first and second offset rows in the die extension region. A conductive material is deposited in the THVs. A first RDL is formed between contact pads on the semiconductor die and the THVs. A second RDL is formed on a backside of the semiconductor die in electrical contact with the THVs. An under bump metallization is formed in electrical contact with the second RDL. Solder bumps are formed on the under bump metallization. The die extension region is singulated to separate the semiconductor die.

2010-12-09

20100311207

Compounds Having A Diphenyl Oxide Backbone and Maleimide Functional Group - A compound having a diphenyl oxide backbone, and pendant from the backbone at least one hydrocarbon chain, the hydrocarbon chain containing an ester functionality and being terminated with a maleimide functional group is prepared from the reaction of diphenyl oxide, formaldehyde or paraformaldehyde, and a compound containing both carboxylic acid and maleimide functionality. Exemplary compounds include:

2010-12-09

20100311208

METHOD AND APPARATUS FOR NO LEAD SEMICONDUCTOR PACKAGE - A leadframe for use in fabricating a no lead semiconductor package contains connecting bars between individual electrical contact pads. For embodiments having a die pad, the leadframe further includes connecting bars between the contact pads and the die pad. The lower surfaces of the connecting bars are coplanar with the lower surfaces of the contact pads and/or the die pad, and the upper surfaces of the connecting bars are recessed with respect to the upper surfaces of the contact pads and/or the die pad. The semiconductor package is fabricated by encapsulating the die and the leadframe in a molding compound and then removing the connecting bars. The leadframe is typically formed by half etching a metal sheet to form the connecting bars. The connecting bars are removed from the encapsulated package by a selected cutting, sawing, or etching means, based on a predetermined pattern.

2010-12-09

20100311209

METHOD O ENCAPSULATING A WAFER LEVEL MICRODEVICE - The present invention discloses a method of encapsulating a wafer level microdevice, which includes: fabricating a microdevice on top side of a first silicon wafer; depositing a first capping carbon film on the top side of the first silicon wafer; implementing a backside fabricating process of wafer from bottom side of the first silicon wafer by carrying the top side of the first silicon wafer through the first capping carbon film; removing the first capping carbon film by selective gaseous reaction with carbon; and encapsulating an encapsulation wafer onto the top side of the first silicon wafer. The present invention deposits and removes the first capping carbon film by means of chemical technology, thereby protecting the microdevice on the top side of the first wafer during implementing the backside fabricating process of wafer. The top side does not need to be protected through the encapsulation wafer before implementing the backside fabricating process of wafer, which makes the wafer thinner and convenient to be handled.

2010-12-09

20100311210

NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile semiconductor storage device includes: a substrate; a control circuit layer provided on the substrate; a support layer provided on the control circuit layer; and a memory cell array layer provided on the support layer. The memory cell array layer includes: a first lamination part having first insulation layers and first conductive layers alternately laminated therein; and a second lamination part provided on either the top or bottom surface of the respective first lamination part and laminated so as to form a second conductive layer between second insulation layers. The control circuit layer includes at least any one of: a row decoder driving word lines provided in the memory cell array layer, and a sense amplifier sensing and amplifying a signal from bit lines provided in the memory cell array layer.

METHOD FOR PRODUCING DISPLAY DEVICE - In a liquid crystal display device, a first substrate includes electrical wirings and a semiconductor integrated circuit which has TFTs and is connected electrically to the electrical wirings, and a second substrate includes a transparent conductive film on a surface thereof. A surface of the first substrate that the electrical wirings are formed is opposite to the transparent conductive film on the second substrate. the semiconductor integrated circuit has substantially the same length as one side of a display screen (i.e., a matrix circuit) of the display device and is obtained by peeling it from another substrate and then forming it on the first substrate. Also, in a liquid crystal display device, a first substrate includes a matrix circuit and a peripheral driver circuit, and a second substrate is opposite to the first substrate, includes a matrix circuit and a peripheral driver circuit and has at least a size corresponding to the matrix circuit and the peripheral driver circuit. Spacers is provided between the first and second substrates. A seal material is formed outside the matrix circuits and the peripheral driver circuits in the first and second substrates. A liquid crystal material is filled inside a region enclosed by the seal material. A protective film is formed on the peripheral driver circuit has substantially a thickness equivalent to an interval between the substrates which is formed by the spacers.

2010-12-09

20100311213

METHOD OF FORMING AN INVERTED T SHAPED CHANNEL STRUCTURE FOR AN INVERTED T CHANNEL FIELD EFFECT TRANSISTOR DEVICE - A method of forming an inverted T shaped channel structure having a vertical channel portion and a horizontal channel portion for an Inverted T channel Field Effect Transistor ITFET device comprises providing a semiconductor substrate, providing a first layer of a first semiconductor material over the semiconductor substrate and providing a second layer of a second semiconductor material over the first layer. The first and the second semiconductor materials are selected such that the first semiconductor material has a rate of removal which is less than a rate of removal of the second semiconductor material. The method further comprises removing a portion of the first layer and a portion of the second layer selectively according to the different rates of removal so as to provide a lateral layer and the vertical channel portion of the inverted T shaped channel structure and removing a portion of the lateral layer so as to provide the horizontal channel portion of the inverted T shaped channel structure.

2010-12-09

20100311214

MASK-SAVING PRODUCTION OF COMPLEMENTARY LATERAL HIGH-VOLTAGE TRANSISTORS WITH A RESURF STRUCTURE - The invention relates to a method for the production of a first lateral high-voltage MOS transistor and a second lateral high-voltage MOS transistor complimentary thereto on a substrate, wherein the first and second lateral high-voltage MOS transistors each have a conductivity type opposite a drift region, comprising the steps of providing a substrate of a first conductivity type comprising a first active region for the first lateral high-voltage MOS transistor and a second active region for the second lateral high-voltage MOS transistor, and the producing at least one first doping region of the first conductivity type in the first active region and, on the other hand, in the second active region, a drain extension region of the first conductivity type extending from the substrate surface to the interior of the substrate, which allows a simultaneous implantation of doping material in the first and second active regions through respective mask openings of one and the same mask.

Method for Forming Active and Gate Runner Trenches - A method for forming a trench-gated field effect transistor (FET) includes the following steps. Using a first mask, defining and simultaneously forming a plurality of active gate trenches and at least one gate runner trench extending to a first depth within a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench; and using the first mask and a second mask for protecting the at least one gate runner trench, further extending only the plurality of active gate trenches to a second and final depth within the silicon region.

2010-12-09

20100311217

Non-Volatile Memory Device Having A Nitride-Oxide Dielectric Layer - A non-volatile memory cell may include a semiconductor substrate; a source region in a portion of the substrate; a drain region within a portion of the substrate; a well region within a portion of the substrate. The memory cell may further include a first carrier tunneling layer over the substrate; a charge storage layer over the first carrier tunneling layer; a second carrier tunneling layer over the charge storage layer; and a conductive control gate over the second carrier tunneling layer. Specifically, the drain region is spaced apart from the source region, and the well region may surround at least a portion of the source and drain regions. In one example, the second carrier tunneling layer provides hole tunneling during an erasing operation and may include at least one dielectric layer.

2010-12-09

20100311218

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF EVALUATING SEMICONDUCTOR DEVICE - A semiconductor device has: a silicon (semiconductor) substrate; a gate insulating film and a gate electrode, which are formed on the silicon substrate in this order; and source/drain material layers formed in recesses (holes) in the silicon substrate, the recesses being located beside the gate electrode. Here, each of side surfaces of the recesses, which are closer to the gate electrode, is constituted of at least one crystal plane of the silicon substrate.

2010-12-09

20100311219

Methods of Forming a Plurality of Capacitors - A method of forming a plurality of capacitors includes an insulative material received over a capacitor array area and a circuitry area. The array area comprises a plurality of capacitor electrode openings within the insulative material received over individual capacitor storage node locations. The intervening area comprises a trench. Conductive metal nitride-comprising material is formed within the openings and against a sidewall portion of the trench to less than completely fill the trench. Inner sidewalls of the conductive material within the trench are annealed in a nitrogen-comprising atmosphere. The insulative material within the array area is etched with a liquid etching solution effective to expose outer sidewall portions of the conductive material within the array area. The conductive material within the array area is incorporated into a plurality of capacitors.

2010-12-09

20100311220

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND NAND-TYPE FLASH MEMORY - A method for manufacturing semiconductor device has forming a plurality of trenches having at least two kinds of aspect ratios on a semiconductor substrate, filling the plurality of trenches with a coating material containing silicon, forming a mask on the coating material in a part of the trenches among the plurality of trenches filled with the coating material, implanting an ion for accelerating oxidation of the coating material into the coating material in the trenches on which the mask is not formed, forming a first insulating film by oxidizing the coating materials into which the ion is implanted, removing the coating material from the part of the trenches after removing the mask and forming a second insulating film in the part of the trenches from which the coating material is removed.

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - When single crystal semiconductor layers are transposed from a single crystal semiconductor substrate (a bond wafer), the single crystal semiconductor substrate is etched selectively (this step is also referred to as groove processing), and a plurality of single crystal semiconductor layers, which are being divided in size of manufactured semiconductor elements, are transposed to a different substrate (a base substrate). Thus, a plurality of island-shaped single crystal semiconductor layers (SOI layers) can be formed over the base substrate. Further, etching is performed on the single crystal semiconductor layers formed over the base substrate, and the shapes of the SOI layers are controlled precisely by being processed and modified.

2010-12-09

20100311223

Method Of Dicing Wafer Using Plasma - Provided is a method of dicing a wafer that is thin and includes a low-K material using plasma without causing chipping and cracking during sawing without using an etch mask and without performing a separate wafer coating process. The method includes recognizing scribe lines of a front side of the wafer by using an image recognizing unit to obtain recognition information, performing two etching processes, wherein at least one includes plasma etching, on a backside of the wafer by using the recognition information to separate the wafer into a plurality of semiconductor chips, and adhering the plurality of semiconductor chips to an extended tape or a die attach film.

2010-12-09

20100311224

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - According to one embodiment, a manufacturing method of a semiconductor device includes forming a plurality of first trenches in a semiconductor substrate, forming an insulating member in the first trenches, removing a part of a portion of the insulating member, forming second trenches in the insulating member, and attaching a protection film. The semiconductor substrate has a first and a second main surface. The insulating member has an upper face located higher than the first main surface. The portion is located higher than the first main surface.

2010-12-09

20100311225

WAFER PROCESSING METHOD - A wafer processing method for dividing a wafer into individual devices along streets. The wafer processing method includes the steps of forming a division groove on the front side of the wafer along each street, attaching the front side of the wafer to the front side of a rigid plate having a plurality of grooves by using an adhesive resin, applying ultraviolet radiation to the adhesive resin to thereby increase the holding force of the adhesive resin, grinding the back side of the wafer to expose the division grooves to the back side of the wafer, attaching an adhesive tape to the back side of the wafer, immersing the wafer and the rigid plate in hot water to swell the adhesive resin, thereby decreasing the holding force of the adhesive resin, and removing the rigid plate from the front side of the wafer.

2010-12-09

20100311226

Die-Sorting Sheet and Method for Transporting Chips Having Adhesive Layer - A die-sorting sheet includes a pressure-sensitive adhesive layer exposed on an outer periphery of the carrier sheet, and a base film exposed on a central area that is inside the outer periphery. A method for transporting a chip having an adhesive layer according to the present invention includes the steps of: providing the above die-sorting sheet that is fixed with a frame through the pressure-sensitive adhesive layer on the outer periphery; temporarily attaching a picked up chip through an adhesive layer thereof onto the base film exposed on the die-sorting sheet; and transporting the die-sorting sheet to a subsequent step while the chip is temporarily attached on the sheet through the adhesive layer.

2010-12-09

20100311227

METHOD FOR PRODUCING SEMICONDUCTOR CHIP WITH ADHESIVE FILM, ADHESIVE FILM FOR SEMICONDUCTOR USED IN THE METHOD, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - The method for producing a semiconductor chip with an adhesive film of the present invention comprises steps of preparing a laminate in which at least a divided semiconductor wafer comprising a plurality of semiconductor chips, obtained by forming a cut which separates the semiconductor wafer into a plurality of semiconductor chips on one side of the semiconductor wafer in a thickness less than that of the semiconductor wafer and by grinding the other side of the semiconductor wafer on which no cut is formed to reach the cut, an adhesive film for a semiconductor and a dicing tape are laminated, the adhesive film for a semiconductor having a thickness in the range of 1 to 15 μm and a tensile elongation at break of less than 5%, and the tensile elongation at break being less than 110% of the elongation at a maximum load; and dividing the adhesive film for a semiconductor by picking up the plurality of semiconductor chips in a laminating direction of the laminate, thereby preparing a semiconductor chip with an adhesive film.

2010-12-09

20100311228

METHOD FOR FORMING TRANSPARENT CONDUCTIVE OXIDE - Embodiments disclosed herein generally relate to a process of depositing a transparent conductive oxide layer over a substrate. The transparent oxide layer is sometimes deposited onto a substrate for later use in a solar cell device. The transparent conductive oxide layer may be deposited by a “cold” sputtering process. In other words, during the sputtering process, a plasma is ignited in the processing chamber which naturally heats the substrate. No additional heat is provided to the substrate during deposition such as from the susceptor. After the transparent conductive oxide layer is deposited, the substrate may be annealed and etched, in either order, to texture the transparent conductive oxide layer. In order to tailor the shape of the texturing, different wet etch chemistries may be utilized. The different etch chemistries may be used to shape the surface of the transparent conductive oxide and the etch rate.

2010-12-09

20100311229

AMORPHOUS GROUP III-V SEMICONDUCTOR MATERIAL AND PREPARATION THEREOF - A reactive evaporation method for forming a group III-V amorphous material attached to a substrate includes subjecting the substrate to an ambient pressure of no greater than 0.01 Pa, and introducing active group-V matter to the surface of the substrate at a working pressure of between 0.05 Pa and 2.5 Pa, and group III metal vapor, until an amorphous group III-V material layer is formed on the surface.

METHOD FOR A GATE LAST PROCESS - A method for fabricating a semiconductor device is disclosed. The method includes providing a substrate; forming one or more gate structures over the substrate; forming a buffer layer over the substrate, including over the one or more gate structures; forming an etch stop layer over the buffer layer; forming a interlevel dielectric (ILD) layer over the etch stop layer; and removing a portion of the buffer layer, a portion of the etch stop layer, and a portion of the ILD layer over the one or more gate structures.

2010-12-09

20100311232

Method of Manufacturing Nonvolatile Memory Device - A method of manufacturing a nonvolatile memory device comprises providing a semiconductor substrate defining active regions and isolation regions with a gate insulating layer and a floating gate formed over each active region and isolation layer formed in the respective isolation regions, forming a dielectric layer on a surface of the isolation layers and the floating gates, forming a polysilicon layer over the dielectric layer through a polysilicon deposition process using a nitrogen source gas, a silicon source gas, and an impurity doping gas, and patterning the polysilicon layer to form a control gate.

2010-12-09

20100311233

Semiconductor device manufacturing method - In an MIS-type GaN-FET, a base layer made of a conductive nitride including no oxygen, here, TaN, is provided on a surface layer as a nitride semiconductor layer to cover at least an area of a lower face of a gate insulation film made of Ta

2010-12-09

20100311234

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is provided. A first bond of a first wire loop is formed. A wire is bonded through a ball to a lead or a chip electrode of a semiconductor chip to form a second bond of the first wire loop and a first bond of a second wire loop. A second bond of the second wire loop is formed. The ball provides a large bonding area, and thus, provides a strong bonding strength.

COPPER INTERCONNECT STRUCTURE WITH AMORPHOUS TANTALUM IRIDIUM DIFFUSION BARRIER - A method of forming a diffusion barrier for use in semiconductor device manufacturing includes depositing, by a physical vapor deposition (PVD) process, an iridium doped, tantalum based barrier layer over a patterned interlevel dielectric (ILD) layer, wherein the barrier layer is deposited with an iridium concentration of at least 60% by atomic weight such that the barrier layer has a resulting amorphous structure.

2010-12-09

20100311237

FORMATION OF A TANTALUM-NITRIDE LAYER - A method of forming a material on a substrate is disclosed. In one embodiment, the method includes forming a tantalum nitride layer on a substrate disposed in a plasma process chamber by sequentially exposing the substrate to a tantalum precursor and a nitrogen precursor, followed by reducing a nitrogen concentration of the tantalum nitride layer by exposing the substrate to a plasma annealing process. A metal-containing layer is subsequently deposited on the tantalum nitride layer.

2010-12-09

20100311238

METHOD OF FORMING COPPER WIRING LAYER - A method of forming a copper wiring layer, which includes forming a pattern of copper seed layer on a substrate, and forming a copper wiring pattern on the pattern of copper seed layer by means of electroless plating. At least one component of semiconductor device selected from the group consisting of the gate electrode, the source electrode, the drain electrode, and a wiring connected with at least one of these electrodes is formed by a method comprising forming a pattern of copper seed layer, and forming a copper wiring pattern on the pattern of copper seed layer by means of electroless plating.

2010-12-09

20100311239

Method for forming dual damascene pattern - A method for forming a dual damascene pattern includes preparing a multi-functional hard mask composition including a silicon resin as a base resin, wherein the silicon resin comprises about 20 to 45% silicon molecules by weight, based on a total weight of the resin; forming a deposition structure by sequentially forming a self-arrangement contact (SAC) insulating film, a first dielectric film, an etching barrier film, and a second dielectric film over a hardwiring layer; etching the deposition structure to expose the hardwiring layer, thereby forming a via hole; coating the multi-functional hard mask composition over the second dielectric film and in the via hole to form a multi-functional hard mask film; and etching the resulting structure to expose a part of the first dielectric film using a photoresist pattern as an etching mask, thereby forming a trench having a width greater than that of the via hole.

2010-12-09

20100311240

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device according to an embodiment, includes forming a wiring in a surface of a first insulating film on a semiconductor substrate, exposing the first insulating film in whose surface the wiring is formed to a plasma containing a rare gas so as to form a densified layer on the surface of the first insulating film, removing an oxide film formed on the wiring, after the densified layer is formed and forming a second insulating film on the wiring from which the oxide film is removed and on the densified layer, wherein the processes from the removal of the oxide film to the formation of the second insulating film are carried out without being atmospherically-exposed.

2010-12-09

20100311241

THREE-STATE MASK AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - A three-state mask, which is used during exposure of a lithography process and formed in a regular pattern, includes a first transmission region to transmit substantially all incident light, second transmission regions to transmit a portion of incident light, and shield regions to block transmission of light. Therefore, the three-state mask shortens two lithography processes into one lithography process, eliminates misalignment between a via hole and a trench, prevents lowering of a sheet resistance (R

2010-12-09

20100311242

METHODS FOR FABRICATING SEMICONDUCTOR DEVICES - Methods are provided for fabricating a semiconductor device. One method comprises providing a first pattern having a first polygon, the first polygon having a first tonality and having a first side and a second side, the first side adjacent to a second polygon having a second tonality, and the second side adjacent to a third polygon having the second tonality, and forming a second pattern by reversing the tonality of the first pattern. The method further comprises forming a third pattern from the second pattern by converting the second polygon from the first tonality to the second tonality forming a fourth pattern from the second pattern by converting the third polygon from the first tonality to the second tonality forming a fifth pattern by reversing the tonality of the third pattern, and forming a sixth pattern by reversing the tonality of the fourth pattern.

2010-12-09

20100311243

Bottom electrode etching process in MRAM cell - A BE patterning scheme in a MRAM is disclosed that avoids damage to the MTJ array and underlying ILD layer while reducing BE-BE shorts and BE-bit line shorts. A protective dielectric layer is coated over a MTJ array before a photoresist layer is coated and patterned on the dielectric layer. The photoresist pattern is transferred through the dielectric layer with a dielectric etch process and then through the BE layer with a metal etch that includes a certain amount of overetch to remove metal residues. The photoresist is stripped with a sequence involving immersion or spraying with an organic solution followed by oxygen ashing to remove any other organic materials. Finally, a second wet strip is performed with a water based solution to provide a residue free substrate. In another embodiment, a bottom anti-reflective coating (BARC) is inserted between the photoresist and dielectric layer for improved critical dimension control.

2010-12-09

20100311244

DOUBLE-EXPOSURE METHOD - The present invention discloses a double-exposure method comprising a first lithography process and a second lithography process. Between the first and the second lithography process, coat Resolution Enhancement Lithography Assisted by Chemical Shrink (RELACS) material on the first photoresist pattern, promote thermal crosslinking reaction at the interface between the RELACS materials and the first photoresist pattern; afterwards, remove the RELACS material which does not crosslink with the first photoresist pattern. This method not only realizes higher lithography resolution, but also avoids the adverse effects of the second exposure on the first photoresist pattern in double-exposure technology.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A problem of a resist mask collapse due to a plasma process is solved. In a method of manufacturing a semiconductor device including steps of a plasma process to a sample having a mask made of an organic material, the plasma process includes a first step of a plasma process under a gas containing any of fluorine, oxygen, or nitrogen, or containing all of them, and a second step of the plasma process under a gas containing a rare gas without containing any of fluorine, oxygen, and nitrogen, and the first step and the second step are repeated.

STRUCTURED LAYER DEPOSITION ON PROCESSED WAFERS USED IN MICROSYSTEM TECHNOLOGY - The invention relates to a method and a through-vapor mask for depositing layers in a structured manner by means of a specially designed coating mask which has structures that accurately fit into complementary alignment structures of the microsystem wafer to be coated in a structured manner such that the mask and the wafer can be accurately aligned relative to one another. Very precisely defined portions on the microsystem wafer are coated through holes in the coating mask, e.g. by mans of sputtering, CVD, or to evaporation processes.

2010-12-09

20100311249

MULTI-GAS FLOW DIFFUSER - Embodiments of the disclosure generally provide a method and apparatus for processing a substrate in a vacuum process chamber. In one embodiment a vacuum process chamber is provided that includes a chamber body and lid disposed on the chamber body. A blocker plate is coupled to the lid and bounds a staging plenum therewith. A gas distribution plate is coupled to the lid. The gas distribution plate separates a main plenum defined between the gas distribution plate and the blocker plate from a process volume defined within the chamber body. The gas distribution plate and the blocker plate define a spacing gradient therebetween which influences mixing of gases within the main plenum.

2010-12-09

20100311250

THIN SUBSTRATE FABRICATION USING STRESS-INDUCED SUBSTRATE SPALLING - A method for manufacturing a thin film direct bandgap semiconductor active solar cell device comprises providing a source substrate having a surface and disposing on the surface a stress layer having a stress layer surface area in contact with and bonded to the surface of the source substrate. Operatively associating a handle foil with the stress layer and applying force to the handle foil separates the stress layer from the source substrate, and leaves a portion of the source substrate on the stress layer surface substantially corresponding to the area in contact with the surface of the source substrate. The portion is less thick than the source layer. The stress layer thickness is below that which results in spontaneous spalling of the source substrate. The source substrate may comprise an inorganic single crystal or polycrystalline material such as Si, Ge, GaAs, SiC, sapphire, or GaN. In one embodiment the stress layer comprises a flexible material.

2010-12-09

20100311251

BATCH PROCESSING METHOD FOR FORMING STRUCTURE INCLUDING AMORPHOUS CARBON FILM - A batch processing method for forming a structure including an amorphous carbon film includes performing a preliminary treatment of removing water from a surface of the underlying layer by heating the inside of the reaction chamber at a preliminary treatment temperature of 800 to 950° C. and supplying a preliminary treatment gas selected from the group consisting of nitrogen gas and ammonia gas into the reaction chamber while exhausting gas from inside the reaction chamber; and, then performing main CVD of forming an amorphous carbon film on the underlying layer by heating the inside of the reaction chamber at a main process temperature and supplying a hydrocarbon gas into the reaction chamber while exhausting gas from inside the reaction chamber.

2010-12-09

20100311252

OXYGEN PLASMA REDUCTION TO ELIMINATE PRECURSOR OVERFLOW IN BPTEOS FILM DEPOSITION - A method including providing a semiconductor substrate in a reaction chamber; flowing a first reactant including silicon and oxygen, a boron dopant and a phosphorus dopant into the reaction chamber so that a layer of BPTEOS is deposited on the semiconductor substrate; stopping the flow of the first reactant, boron dopant and phosphorus dopant into the reaction chamber and so that a phosphorus dopant and boron dopant rich film is deposited over the layer of BPTEOS; and reducing the film comprising exposing the film to an O

2010-12-09

20100311253

ELECTRICAL CONNECTOR AND MANUFACTURING METHOD THEREOF - An electrical connector includes a fixing member having a support seat; a plurality of terminals, each having an embed section embedded within the fixing member along an extension direction via an insert-molding process and a contact section exposing from the support seat of the fixing member; and an insulated body for seating on the support seat of the fixing member. The insulated body has an insert face formed with a plurality of terminal holes. The insert face is dented inwardly so as to form a plug reception chamber in spatial communication with the terminal holes. When the insulated body is seated on the support seat of the fixing member, the contact sections of the terminals pass through the terminal holes in the insulated body and are retained within the plug reception chamber.

2010-12-09

20100311254

ELECTRONIC DEVICE WITH EMI SHIELD SPRING DEVICE - An electronic device comprises a circuit board, a conductive member, and a spring contact. The conductive member is spaced from the circuit board and comprises a surface opposite to the circuit board. The surface defines a recessed portion. The spring contact is connected to the conductive member and contacts the circuit board to achieve grounding. The spring contact comprises an end movably received in the recessed portion.

2010-12-09

20100311255

ELECTRICAL CONNECTOR HAVING AT LEAST ONE HOLE WITH SURFACE MOUNT PROJECTIONS - An electrical connector for electrically coupling an electronic module and an electrical component. The connector includes a connector body that has first and second mating surfaces. The connector body includes interconnects that extend through the connector body between the first and second mating surfaces for electrically coupling the module and the component. The connector body has a hole extending therethrough along a central axis. The hole is configured to receive a guide pin from one of the module and the component. The connector also includes surface mount projections that are coupled to the connector body and extend toward the central axis of the hole. The projections engage and flex against the guide pin when the guide pin is inserted into the hole. The projections form an interference fit with the guide pin to hold the connector body in a mounted position.

2010-12-09

20100311256

ELECTRICAL CONNECTOR WITH IMPROVED CONTACTS - An electrical connector includes an insulative housing defining a receiving room having a bottom wall and a mating portion extending upward from an inner face of the bottom wall of the receiving room and a plurality of contacts received in the housing. The mating portion has a plurality of receiving passageways communicating with the receiving room and a plurality of nose portions are above the receiving passageways. Each contact defines an elastic portion, a soldering portion, and a fixing portion between the elastic portion and a soldering portion. The elastic portion includes a first contacting portion protruding from the nose portion in the receiving room, a second contacting portion extending from the fixing portion, and a connecting portion between two contacting portions and defining an arc portion extending in an upward-to-downward direction and under the nose portion. The arc portion defines a node extending far from the nose portion.

2010-12-09

20100311257

FLASH MEMORY DEVICE WITH TELESCOPIC CONNECTOR PORT AND A CASING OF THE FLASH MEMORY DEVICE - A flash memory device includes a cover, an electrical module, a slider and a rotatable member for driving the slider. The cover defines a receiving chamber and an opening communicating with the receiving chamber. The electrical module is slideably received in the receiving chamber and includes a circuit board and a connector port electrically connected with the circuit board. The rotatable member has a fixed axis around which the rotatable member revolves. The rotatable member includes a protrusion slideably received in a slot defined in the slider. The connector port is driven to telescopically extend through the opening by the slider which is further driven by the protrusion.

COVER STRUCTURE FOR PORTABLE ELECTRONIC DEVICES - A cover structure includes a cover, a main body and an elastic member. The cover includes an engaging portion and a sliding member. The main body includes a latching portion. The elastic member is integrally formed with the main body. The elastic member defines a sliding hole allowing the sliding member to slide therein. At least one protrusion is formed in the sliding hole and divides the sliding hole into two sections. The sliding member passes the protrusion from one section to another section of the sliding hole while the engaging portion is engaged in or detached from the latching portion.

Universal Plug Adapter - A universal plug adapter, comprising: a main body, at least a set of plug pins, an orientation guide rod allowing sliding of pins and a slide block restricting the shift of pins; the plug pin comprises of at least two pins of different sizes, of which a single pin can be pushed every time; a sliding groove is set laterally onto the slide block; the groove is deep upwards and shallow downwards; the pin is provided with a bulge; when the pin is pushed, the bulge moves along the groove of the slide block groove; given the different depth of the groove, the bulge pushes the slide block to shift, such that the bulges on other pins cannot be aligned with the center of the groove, so other pins not yet pushed are restricted in original position.

2010-12-09

20100311262

ELECTRICAL CONNECTOR FOR A SOLAR MODULE ASSEMBLY - An electrical connector includes a rigid body, cable mating bodies disposed within the body, and contacts joined to the cable mating bodies. The body has an upper side and an opposite mounting side that is configured to be mounted to a first solar module. The body frames a window that extends through the body from the upper side to the mounting side. The cable mating bodies are configured to electrically couple the first solar module with cables to communicate electric current generated in the first solar module with one or more of an electrical load and an additional solar module. The contacts extend into the window of the body and are arranged in the window to mate with the module contacts to electrically couple the first solar module with the cable mating bodies.

2010-12-09

20100311263

CONNECTOR CLAMP WITH OPENING UNIT - The invention relates to a connector clamp having a housing and a current bar disposed thereon, and having a receiving unit for receiving a conductor, and having a clamping unit with a clamping spring held in the housing for clamping the conductor against the current bar in order to conduct an inserted conductor to the current bar in an electrically conductive manner. An activation unit is provided that acts on the clamping spring in order to open the clamping unit. The activation unit is provided with an indicator unit for indicating a clamping state of the clamping unit. The activation unit is coupled in terms of movement to the clamping unit. The receiving unit is disposed spatially between a fixed section of the clamping spring and the activation unit so that the indicator unit indicates the clamping state of the clamping unit independently of the spatial position of the housing.

2010-12-09

20100311264

BURN-IN SOCKET - A burn-in socket includes a base, a sliding plate mounted to the base, a number of contacts, and an actuator mounted on the base. The contact each has a base portion secured to the base and a pair of arms extending through the pin holes of the sliding plate. The actuator includes a frame and a number of actuating portion extending downwardly from the frame for driving the sliding plate to slide on the base in a first direction. The actuator includes a number of pushing portions contacting with the sliding plate and driving the sliding plate to move in a second direction opposite to said first direction.

DUAL DIRECTIONAL CONNECTOR - A connector is provided that permits locking between a pin and a housing a canted coil spring yet permit separation by allowing turning of the canted coil spring so that the canted coil spring can compress along the minor axis. In one example, the connector incorporates two grooves on the pin to allow the rotation. In another example, the connector incorporates two grooves in the bore of the housing to allow the rotation. The connector may be used in a number of applications or industries, such as for aerospace, automotive, and medical device industries, to name a few.

ALIGNMENT ASSEMBLY FOR ELECTRICAL CONNECTORS - A high speed electrical connector assembly is disclosed providing a first subassembly having connector assemblies attached to a daughtercard, and a second subassembly having connector assemblies attached to a backplane. A keying guide module is mounted to the daughtercard and a keying guide pin is mounted to the backplane. The alignment of the keying guide module and keying guide pin aligns the connector assemblies on the daughtercard and backplane.

2010-12-09

20100311269

ELECTRICAL CONNECTOR ASSEMBLY HAVING A CABLE RETENTION ELEMENT - An electrical connector assembly includes a housing, a cable and a cable retention element. The housing holds contacts that are configured to be electrically joined with a peripheral device. The housing includes a cable port that is disposed at an outer surface of the housing. The cable extends from the cable port of the housing along a cable axis. The cable is electrically coupled with the contacts in the housing. The cable retention element is attached to the cable and is at least partially disposed within the housing. The cable retention element includes a body that is joined with the cable and a wing protruding from the body in a direction oriented at an angle with respect to the cable axis. The wing engages the housing to prevent the cable from being removed from the housing.

2010-12-09

20100311270

ELECTRONIC APPARATUS AND CONNECTOR MODULE USED FOR THIS ELECTRONIC APPARATUS - An electronic apparatus wherein at least one detachable module is inserted into a rack and the module is connected with the rack by male/female connector, wherein it is made possible to detect any bending of pins of the male connector before the module is mounted in the rack and therefore incomplete mounting of the module to the rack can be prevented. A light source with high linearity is provided at each of the pins at the male connector side, while conversely a light receiving unit of light is provided at each of the receptacles at the female connector side. Before connection of the connectors, if all receiving units receive light, normality of the pins is detected. Instead of providing the light receiving units at the female connector side, providing a reflecting part at the female connector side and providing a light receiving unit at the male connector side is possible.

Radio frequency coxial connector - A RF coaxial connector has an insulative housing, an internal terminal and an external terminal. The insulative housing has a cavity. The internal terminal is mounted in the cavity and has a mounting section, two resilient arms protruding from the mounting section, a free section formed between the resilient arms and a contacting section protruding from the free section. The external terminal is mounted on the insulative housing. The internal terminal provides sufficient resistance force against a pin conductor of a corresponding connector engaged with the RF coaxial connector for stable signal transmission.

2010-12-09

20100311273

RECEPTACLE CONNECTOR - A receptacle connector includes an insulating body having a base portion, and a shell enclosing the insulating body. Two opposite side surfaces of the base portion respectively define an inserting passage extending longitudinally and having a front end opened freely. A front of each inserting passage is provided with a preventing block. A fixing cavity is formed in a rear of the inserting passage by the partition of the preventing block. The preventing block has a guiding surface inclined outward from front to rear. The shell has two side boards against the corresponding side surfaces of the base portion. Two fixing portions are protruded inwardly from two substantially corresponding portions of two bottom edges of the side boards for gliding along the corresponding guiding surfaces in the respective inserting passages to buckle into the corresponding fixing cavities and then restrained by the preventing blocks in the fixing cavities.

2010-12-09

20100311274

ECO CONTACTOR - The present invention relates to an improved a shielded contactor having an insulative material or proxy (

2010-12-09

20100311275

IMPLEMENTING ADAPTABLE THREE PHASE MODULAR LINE FILTERING - A modular line filter connector is provided for implementing adaptable three-phase power filtering. A plurality of selected modular components defines the modular line filter connector. The modular line filter connector includes a pair of outer cylinders providing power filtering connections including, for example, line-to-line connections, line-to-common connections, common-to-protective earth connections, and line-to-protective earth connections. The selected modular components are mounted between the pair of outer cylinders and disposed along the length of the modular line filter connector. Different modular components are selected to adapt the modular line filter connector for different filtering applications.

2010-12-09

20100311276

Battery Connector - A battery connector includes an insulating housing, a plurality of conductive terminals, an insulating cover and a shell. A bottom surface of the insulating housing defines a plurality of terminal recesses each extending longitudinally to penetrate through a mating front surface of the insulating housing. Each of the conductive terminals includes a base portion, a contact portion, and an elastic portion elastically connecting the contact portion to the base portion. The conductive terminals are placed to the insulating housing from the bottom surface thereof. The insulating cover is covered on the bottom surface of the insulating housing to secure the conductive terminals in the corresponding terminal recesses. The shell encloses the insulating housing to make the insulating cover further locate between the bottom surface of the insulating housing and the shell for preventing the conductive terminals from electrically contacting the shell.

2010-12-09

20100311277

PHASE ADJUSTABLE ADAPTER - A phase adjustable adapter that can maintain its value of characteristic impedance in a manner that is independent of its electrical length. Embodiments of the adapter include a center conductor and an adapter body in surrounding relation to the center conductor so as to form an insulative gap. The adapter body has form factor that is defined by the ratio of an outer dimension of the adapter body to the length of the adapter body, where the form factor changes in accordance with the change in the length of the adapter body.

2010-12-09

20100311278

CONNECTOR ASSEMBLY HAVING A UNITARY HOUSING - A connector insert includes a unitary body, cavities extending through the body, and contacts. The body extends between mating and loading sides. The loading side is configured to engage a circuit board. The mating side is configured to mate with a peripheral connector to electrically couple the circuit board with the peripheral connector. The cavities extend through the body from the mating side to the loading side. The contacts are held in the cavities of the housing and protrude from each of the mating and loading sides to engage the circuit board and peripheral connector and to provide an electronic signal path between the circuit board and the peripheral connector. The contacts are loaded into the cavities through the loading side and retained in the body by an interference fit between the contacts and the body. The interference fit prevents the contacts from being removed from the body through the mating side.

2010-12-09

20100311279

Electrical Connector and Illuminating Module - An illuminating module includes an illuminating device and an electrical connector. The illuminating device includes a first conductive contact and a second conductive contact. The electrical connector includes an external plug, a first internal conductive terminal and a second internal conductive terminal. The first internal conductive terminal electrically connects the external plug and the first conductive contact. The second internal conductive terminal electrically connects the external plug and the second conductive contact. The connection manner of the first internal conductive terminal and the first conductive contact belongs to fool-proof connection. The connection manner of the second internal conductive terminal and the second conductive contact belongs to fool-proof connection. The misconnection between the first and the second internal conductive terminals of the electrical connector and the first and the second conductive contacts of the illuminating device is prevented by means of the design of the illuminating module.

2010-12-09

20100311280

DUAL-BARREL, CONNECTOR JACK AND PLUG ASSEMBLIES - Disclosed herein are dual-barrel, connector jack and plug assemblies. Particularly, plug assemblies having two single barrel connectors that are situated side-by-side. Each barrel may include two or more contacts for receiving and transmitting DC IN+ electrical signals. Further, each barrel may include two or more contacts for receiving and transmitting DC IN− electrical signals. Inside each barrel connector may be disposed center pins. The barrel connectors may be cylindrically-shaped and configured to mate to a dual-barrel, connector jack assembly as described herein. A bridge component may be disposed between the barrel connectors for preventing the plug assembly from being inserted into the jack assembly in the wrong orientation. The bridge assembly may be shaped to prevent improper insertion into a corresponding aperture of the jack assembly.

2010-12-09

20100311281

AUDIO PLUG WITH CORE STRUCTURAL MEMBER - Plugs with core structural members and methods for manufacturing plugs with core structural members are provided. A plug can include a core structural member that may increase the structural integrity of the plug. The plug can further include contact pads and traces, and each trace can electrically couple with one of the contact pads and extend along a plug axis towards the proximal end (e.g., base section) of the plug. In orientation-specific embodiments, the traces may be disposed on the surface of the plug. However, in other embodiments, the traces may be disposed below but near the surface of the plug. The plug may also include one or more insulating layers to prevent contact pads and traces from shorting.

2010-12-09

20100311282

CONNECTOR SHELL HAVING INTEGRALLY FORMED CONNECTOR INSERTS - A connector shell includes a frame, a dividing wall and a plurality of connector inserts. The frame surrounds a periphery of the shell. The dividing wall is homogeneously formed with the frame and separates a plurality of recesses. The connector inserts are homogeneously formed with the frame and the dividing wall. The inserts are disposed with one or more of the recesses. Each insert includes a body and a plurality of cavities. Each body is configured to hold a plurality of contacts that protrude from each of a mating and a loading side. The contacts are configured to be mounted to a circuit board in a location proximate to the loading side and to mate with a plurality of other electrical connectors in a location proximate to the mating side.

2010-12-09

20100311283

LOCKING CONNECTOR FOR ENGAGING A USB RECEPTACLE - A locking connector for engaging a Universal Serial Bus (“USB”) receptacle, including: a connector housing having a locking cam opening on one side of the connector housing, the connector housing split along a longitudinal axis of the locking connector forming a connector housing gap on the same side of the connector housing as the locking cam opening; a locking cam surface positioned within the locking cam opening in contact with the connector housing; and a pivotable locking cam actuating lever connected to a top of the locking cam surface, the locking cam actuating lever having a locked position and an unlocked position, the locking cam surface in a rotated position expanding the connector housing when the cam actuating lever is in the locked position, the locking cam surface in a relaxed position with the connector housing not expanded when the cam actuating lever is in the unlocked position.

CONTACT BASE - In a contact base with a plurality of contact springs for making contact with electronic components, in particular ICs, the contact springs each have an elongate contact blade, the longitudinal centre plane of said contact blade being situated parallel to the bending plane of the spring arm of the contact spring. Furthermore, the spring arm is formed in such a way that, when a pin is pressed, the contact blade moves in a direction which differs from the feed direction of the component in such a way that the contact blade moves along the pin.

2010-12-09

20100311286

ELECTRICAL CONNECTION DEVICE - The invention relates to an electrical connection device for transmitting high current levels, comprising at least one flat contact having a tulip contact and a contact blade having a prescribed blade thickness, wherein the flat contact is suitable for receiving the contact blade having the prescribed blade thickness. A contact force for contacting is applied by an upper spring in the contact area. The tulip contact comprises a free entry width in an unloaded state that approximately corresponds to the prescribed blade thickness.

2010-12-09

20100311287

ELECTRICAL CONTACT FOR USE WITH LGA SOCKET CONNECTOR - An electrical contact adapted for use in an electrical socket comprises a planar retaining body for being retained in the electrical socket, a soldering portion extending from a bottom end of the retaining body, and a resilient arm extending from a top end of the retaining body. The resilient arm comprises a first beam sloped upwardly and a second beam extending upwardly and reversely from the first beam. The first beam has a first angle with respect to a plane of the retaining body and a second angle with respect to another plane both perpendicular to the plane of the retaining body and a horizontal plane. The second beam has a contacting end at the top end thereof and toward the retaining body. An offset is defined between the contacting end of the resilient arm and the soldering portion.

2010-12-09

20100311288

ELECTRICAL CONTACT ELEMENT AND A METHOD OF PRODUCING THE SAME - The present invention relates to a method of producing a electrical contact element, in which a multilayer structure is formed by applying a diffusion barrier layer to a base material and at least one metallic layer made of a metal to the diffusion barrier layer, at least one layer formed of tin being applied as the metallic layer. The present invention further relates to an electrical contact element with an electrically conductive base material and a coating which is formed on at least one portion of the electrically conductive base material, the coating having a diffusion barrier layer formed on the base material and the outer layer containing tin. To prevent whisker formation when using the electrical connector element, the present invention proposes, as a solution to the method-related problem, to subject the multilayer structure to a heat treatment such that at least one element of the layer located under the outer layer of the multilayer structure diffuses into said outer layer and the heat-treated outer layer comprises tin. To solve the device-related problem of the invention, it is proposed that the outer layer of the coating be a layer thoroughly alloyed by the diffusion of tin and at least one further metallic element.

2010-12-09

20100311289

COMPOSITE ASSEMBLY FOR AN ELECTRICAL CONNECTOR AND METHOD OF MANUFACTURING THE COMPOSITE ASSEMBLY - A composite assembly for an electrical connector includes a conductive substrate and an electrodeposited layer. The conductive substrate is configured to form a conductive path of the electrical connector. The electrodeposited layer is disposed on the conductive substrate and includes a dielectric material. A method of manufacturing a composite assembly for an electrical connector includes providing a fluid bath that includes a dielectric material and immersing at least part of a conductive substrate into the fluid bath. The method also includes applying a voltage potential between the fluid bath and the conductive substrate and electrodepositing a dielectric layer that includes the dielectric material on the conductive substrate.

MARINE POWER SPLITTING GEARBOX - A power splitting gearbox is provided that allows a single prime mover to distribute power, for example torque, to multiple final drive assemblies, such as surface drives or other final drives. The power splitting gearbox can be provided downstream from a marine transmission and can be mounted directly to a transom of a marine vessel. The gearbox can have a back wall that accepts and supports mounting surfaces of the multiple final drive assemblies such that the gearbox bears the weight of the multiple final drive assemblies. The gearbox has two outputs that rotate in opposing directions so that a pair of final drive assemblies mounted to the gearbox will counter-rotate a pair of propellers for providing a propulsive force that moves the marine vessel.

2010-12-09

20100311292

INFLATABLE LIFERAFT - The present invention relates to an inflatable liferaft comprising at least an inflatable first tube, an inflatable second flotation tube, said first and second flotation tubes being adapted to be arranged substantially above each other, said first and second flotation tubes extending circumferentially for providing a substantially ring-shaped area; and a bottom element which is adapted to provide a bottom to the substantially ring-shaped area. Furthermore, said first and second flotation tubes are arranged separately substantially above each other, and said first and second flotation tubes are mainly connected via said bottom element.

PIVOTAL SURFBOARD FIN ASSEMBLY - A pivotal surfboard fin assembly for use on a surfboard, the assembly comprising: an insert bracket having a board face mountable to the bottom surface of the surfboard and a bracket face with a lock pin aperture and a flex plug cavity; an elastomeric flex plug having a flex plug hole, a first flex plug surface, and a second flex plug surface, the flex plug disposed in the flex plug cavity; a surfboard fin having a fin blade, a mounting edge, a flex pin channel, a fixed lock pin mountable to the surfboard fin and disposable into the lock pin aperture, a biased flex pin slidably disposable into the flex pin channel and the flex plug hole; and a first compression pin and a second compression pin engaged with the insert bracket and operative to laterally compress the flex plug.

DYED CELLULOSE COMMINUTION SHEET, DYED NONWOVEN MATERIAL, AND PROCESSES FOR THEIR PRODUCTION - The present invention relates to a process for the dyeing of cellulosic fibers in the form of a comminution sheet to produce a dyed cellulose pulp comminution sheet with high moisture content. The dyed cellulose comminution sheet contains (a) a cellulose pulp comminution sheet having a cellulose content of from about 60 weight percent to about 99.9 weight percent cellulose based on the total weight of solids in the cellulose pulp comminution sheet, and a density of from about 0.3 g/cm

2010-12-09

20100311297

Laminated Fabric - There is provided a laminated fabric with a structure in which a face textile is laminated on one side of a durable film with a temporary adhesive layer interposed therebetween and a back textile is laminated on the other side of the durable film with a durable adhesive layer interposed therebetween.

2010-12-09

20100311298

METHOD FOR FABRICATING FUNCTIONAL FILM - It is an object to provide a functional-film fabricating method capable of forming uniform coating films without degrading the productivity, in the event of occurrence of non-ejectable nozzles, out of nozzles in an ink jet apparatus.

2010-12-09

20100311299

Hobby Blocks Including Latently-Adhesive Surfaces - Described herein is a block set including a plurality of blocks having latently adhesive surfaces. Also described is a method of creating a bound structure from the individual blocks, including activating the adhesive of the latently adhesive surface of one or more of the blocks; and contacting an activated adhesive surface of the one or more blocks with another of said blocks, to bond the blocks together.