Comments

If we have two cache events that require different settings of the L2SEL
bits in MMCR1 then we can not schedule those events simultaneously. Add
logic to the constraint handling to express that.
Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
---
arch/powerpc/perf/power7-pmu.c | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)

On Wed, Oct 31, 2012 at 01:09:56PM +1100, Michael Ellerman wrote:
> If we have two cache events that require different settings of the L2SEL> bits in MMCR1 then we can not schedule those events simultaneously. Add> logic to the constraint handling to express that.> > Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Acked-by: Paul Mackerras <paulus@samba.org>