I am familiar with the use of ORG or CODE to branch around an interrupt vector by placing vectors to the main program and interrupt routine, but in the case of OSCCAL, what is needed is to execute the code at memory location at 1FF.. which in the chip I am using at present is CFA.. which is a movlw FA. If the code was: movlw 0xFA OSCCAL

I can see how this would work.. but how do the two ORG statements in the template accomplish this?

I don't know that chip but as a guess: if the devices PC is set to 0x1ff on reset, then the move instruction there will be executed to load a preset value into the W register, and the PC incremented. If that increment means the PC wraps back to 0x000 then the w register value will be written to OSCCAL.Susan

AussieSusan, So what you are suggesting is that when the "ORG 0x1ff" sets the PC to the last memory location.. It then executes the instruction there, which is a movlw 0xFA, and when the PC rolls over to 0x000... the "ORG 0x000, OSCCAL" loads the 0xFA into the OSCCAL register. If that is what that code does, it would certainly accomplish the task. Thanks for explaining... I was not aware that the ORG statement could be used to execute existing code at an address.. I only read about it allowing code to be inserted at specific addresses in memory.

No - the ORG instruction tells the assembler where to place the next code.What sets the PC is the 'reset' of the device. Check Table 4-1 ofg the data shet for that device and you will see that the PCL register has a power on reset value of 0xff. Also read section 4.7.1.Susan

I get it now.. I was assuming that the reset vector pointed to 0x000.. I see now that it points to the top of memory... gets the OSCCAL value loaded into the W register by executing the instruction at 0x1FF, and then rolls over to 0x000 to load W into OSCCAL.. Thanks VERY MUCH for the clarification.. I'm learning... slowly!!