What is the Cray-2 Reboot?

The goal of this project is to make a clock and gate equivalent recreation of a Cray Research Cray-2 supercomputer that will run on an FPGA board. Resources permitting, a small IC run using MOSIS or CMP will be the stretch goal for the project. This project will be made of a number of phases:

1) Find documentation, code, etc. (This as expected is hard) 2) Conversion of module logic to working Verilog code - Complete (with the exception of the memory module) 3) Cleanup of Verilog code - 50% mark 4) Interconnecting all the Verilog together into a functional machine 5) Software emulation of the Verilog code for verification 6) Recovery and/or creation of basic OS & C compiler for the system (c complier will likely be a translated version of TCC) 7) Testing on FPGAs

The CRAY-2 Computer System set the standard for the next generation of supercomputers in 1985. It was characterized by a large Common Memory (256 million 64-bit words), four Background Processors, a clock cycle of 4.1 nanoseconds (4.1 billionths of a second) and liquid immersion cooling. It offers effective throughput six to twelve times that of the CRAY-1 and ran an operating system based on the UNIX operating system.

The CRAY-2 Computer System used the most advanced technology available at the time. The compact mainframe was immersed in a fluorocarbon liquid that dissipated the heat generated by the densely packed electronic components. The logic and memory circuits were contained in eight-layer, three-dimensional modules. The large Common Memory was constructed of the densest memory chips available at the time, and the logic circuits were constructed from the fastest silicon chips available.

The CRAY-2 mainframe contained four independent Background Processors, each more powerful than the CRAY-1 computer. Featuring a clock cycle time of 4.1 nanoseconds, faster than any other computer system available, each of these processors offered exceptional scalar and vector processing capabilities. The four Background Processors could operate independently on separate jobs or concurrently on a single problem. The very high-speed Local Memory integral to each Background Processor was available for temporary storage of vector and scalar data.

Common Memory was one of the most important features of the CRAY-2. It consists of 256 million 64-bit words randomly accessible from any of the four Background Processors and from any of the high-speed and common data channels. The memory was arranged in four quadrants with 128 interleaved banks. All memory access was performed automatically by the hardware. Any user could use all or part of this memory.

In conventional memory-limited computer systems, I/O wait times for large problems that use out-of-memory storage ran into hours. With the large Common Memory of the CRAY-2, many of these problems became CPU-bound.

Control of network access equipment and the high-speed disk drives was integral to the CRAY-2 mainframe hardware. A single Foreground Processor coordinated the data flow between the system Common Memory and all external devices across four high-speed I/O channels. The synchronous operation of the Foreground Processor with the four Background Processors and the external devices provided a significant increase in data throughput.

To complement the new CRAY-2 architecture, Cray Research developed an interactive operating system based on AT&T's UNIX System V. The CRAY-2 Operating System was supported by a FORTRAN compiler based on the proven Cray Research FORTRAN compiler, CFT.

The CRAY-2 Computer System represented a major advance in large-scale computing. The combination of four high-speed Background Processors, a high-speed Local Memory, a huge Common Memory, an extremely powerful I/O capability and a comprehensive software product offered unsurpassed and balanced performance for the user.

The CRAY-2 mainframe was elegant in appearance as well as in architecture. The memory, computer logic, and DC power supplies were integrated into a compact mainframe composed of 14 vertical columns arranged in a 300°arc.

The upper part of each column contained a stack of 24 modules and the lower part contains power supplies for the system. Total cabinet height, including the power supplies, was 45 inches, and the diameter of the mainframe was 53 inches. Thus, the "footprint" of the mainframe was a mere 16 square feet of floor space.

An inert fluorocarbon liquid circulated in the mainframe cabinet in direct contact with the integrated circuit packages. This liquid immersion cooling technology allowed for the small size of the CRAY-2 mainframe and was thus largely responsible for the high computation rates.