(Cat? OR feline) AND NOT dog?
Cat? W/5 behavior
(Cat? OR feline) AND traits
Cat AND charact*

This guide provides a more detailed description of the syntax that is supported along with examples.

This search box also supports the look-up of an IP.com Digital Signature (also referred to as Fingerprint); enter the 72-, 48-, or 32-character code to retrieve details of the associated file or submission.

Concept Search - What can I type?

For a concept search, you can enter phrases, sentences, or full paragraphs in English. For example, copy and paste the abstract of a patent application or paragraphs from an article.

Concept search eliminates the need for complex Boolean syntax to inform retrieval. Our Semantic Gist engine uses advanced cognitive semantic analysis to extract the meaning of data. This reduces the chances of missing valuable information, that may result from traditional keyword searching.

Publishing Venue

Related People

Abstract

A cache to be filled with array elements having a stride of N bytes is accomplished in the following mapping scheme. Currently used cache mapping schemes map main memory lines to cache modulo P (a power of 2, for example, 128). If N is an even multiple of line size (LS), the currently used cache line mapping scheme results in a great deal of cache interference because N/LS is not relatively prime to P; thus, only a portion of the cache gets utilized. A scheme is designed which reduces the cache miss ratio and achieves even cache utilization by mapping main memory lines to cache modulo P, where P is a prime, thus maintaining cache interference at a minimum. The following is a practical scheme using P=127: 1. Remove, from the address, the last Log2LS bits which indicate the byte location within a line. 2.

Country

United States

Language

English (United States)

This text was extracted from a PDF file.

This is the abbreviated version, containing approximately
96% of the total text.

Page 1 of 1

Scheme to Achieve Even Cache Utilization in Engineering and Scientific
Computation

A cache to be filled with array elements having a stride of N bytes is
accomplished in the following mapping scheme. Currently used cache mapping
schemes map main memory lines to cache modulo P (a power of 2, for example,
128). If N is an even multiple of line size (LS), the currently used cache line
mapping scheme results in a great deal of cache interference because N/LS is
not relatively prime to P; thus, only a portion of the cache gets utilized. A scheme
is designed which reduces the cache miss ratio and achieves even cache
utilization by mapping main memory lines to cache modulo P, where P is a prime,
thus maintaining cache interference at a minimum. The following is a practical
scheme using P=127: 1. Remove, from the address, the last Log2LS bits which
indicate the byte location within a line. 2. Take the next 14 bits, and compute
the line address modulo 127 as in step 3. 3. Treat the middle 14 bits as two 7-
bit half words lower (AL) and upper (AU). The line address (LA) for cache is
given by: LA = (AL + AU.128) mod 127 = (AL + AU) mod 127 = AL + AU + CB
AL and AU are added, and if this results in a carry bit (CB), it is also added to the
sum, resulting in the LA in the cache. This algorithm generates addresses LA in
the range 0 to 127, and the only situation where LA will be 0 is when both AL and
AU are zero. Depending upon the specific situation, similar schemes can be
fo...