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An excellent article is up at the Association of Computing Machinery’s website – David Brown interviews Steven Furber on the design of the low power, high performance ARM processor.

If those two names don’t have you instantly clicking links, shame on you. Steven Furber was one of the original team at Acorn who came up with the legendary BBC Micro, and who went on to design the Acorn RISC Machine processor.

David Brown worked with Andy Bechtolsheim to design the original Sun workstation, and was one of the ‘dream team’ who worked with Jim Clarke to form Silicon Graphics. These guys really are rockstars of the computing world.

The interview covers the early adventures of the BBC Micro, how that lead on to the development of the ARM CPU, and the design decisions needed to build power-efficient processors.

Energy efficient computing is becoming a really hot topic (if you’ll pardon the pun) and I think it would be excellent to see the legacy of Acorn live on if ARM processors start making inroads to the data centre. With OpenSolaris being ported to the latest ARM Cortex designs this could be happening sooner than we think.

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There’s been a great need for a while now for a decent, easy to understand introduction to HPC. Those of us who’ve worked in this niche understand the acronyms and weird technology, but for newcomers – even those with a good background in IT – HPC can be an intimidating arena.

Couple this with the blurring between ‘traditional’ HPC systems for research, and new high end business solutions for statistical analysis and database warehouses, and there’s a real need to de-mystify HPC for all.

Douglas Eadline, working with Sun and AMD, has written HPC for Dummies, and the blurb explains:

This special edition eBook from Sun and AMD shares details on real-world uses of HPC, explains the different types of HPC, guides you on how to choose between different suppliers, and provides benchmarks and guidelines you can use to get your system up and running.

What makes this really great is that this is a free ebook, available direct for download from Sun’s site. I can highly recommend that anyone with an interest in HPC (or just large scale systems design) grabs this and has a read through.

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The Hotchips conference is over, and with it comes some news from Sun about their SPARC plans. Sun shared details of it’s “Rainbow Falls” processor – the next iteration in the Niagara line.

Boasting 16 cores, each with it’s own cache, it’s an impressive bit of silicon. Each core has 4 Coherency Units (COU). Familiar to anyone who’s played with big Silicon Graphics kit and other cc:NUMA boxes, Coherency Units keep track of memory contents (from L2 cache up to physical RAM).

4 COUs per core, along with 16 seperate L2 caches, is a lot on a single die. To simplify things (and to help improve performance) Sun has added a Core to Cache Crossbar (CCX). Two cores will share a single entry point into the CCX, which is linked to every core on the chip.

All pretty impressive stuff – remember, this is all on the processor die – and it sounds like it would be ideal in a large system. Those M9000 boxes look pretty inviting, especially after the disappointment of the Niagara system board upgrades for the F15k.

And in fact, maybe that’s what Oracle has up it’s sleeve. The Prophets of Larry have said they will be making a major SPARC announcement on October 14th, during Larry’s yearly sermon to the faithful at Oracleworld. (Sorry, guys – I love you really)

With IBM pushing forward development of it’s fearsome Power7 chip, and with Power6 a bit of a monster anyway, Sun clearly needs to keep in the game – especially after (foolishly) canning Rock.

The Oracle announcement will be aimed clearly at blowing the doors off IBM – check their rhetoric and the fuzzy teaser advert on the Sun plus Oracle is Faster page.

Now, there are a number of ways they could bury IBM in the TPC-C benchmarks. Most obvious would be a massive RAC install, probably with Fujitsu’s new 8 way SPARC64 chip. But that wouldn’t really be blowing the Sun SPARC trumpet, would it?

The current top end Niagara box – the T5440 – can have up to four 8 core Niagara CPUs (along with half a terabyte of RAM). It’s pretty good, but again – the only way you can scale is by clustering them. Oracle have an insanely great scalable database solution with Oracle RAC, so it would seem a no-brainer.

However, if Sun are close to releasing Rainbow Falls, they could use the system boards and interconnects from the M9000 chassis to produce a hugely thread-dense NUMA machine. All that coherency hardware makes no sense for a cluster – it’s role is in a big Single System Image (SSI) machine.

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Back in 2005 when Sun released the Niagara chip – the UltraSPARC T1 – they also took the unusual step of open sourcing the hardware design of the CPU. Having a ground breaking 8 core, 32 thread CPU was impressive enough, but sharing the internals with anyone who was interested – awesome!

Recently Sun have announced a partnership with Europractice, who are a pan-European group setup to promote student learning of chip design across Europe. It follows on from the successful Eurochip organisation which had similar aims.

With Europractice, Sun are making CPU design details, chip architecture documentation, and FPGA tools available to Universities across Europe. As part of that, Sun are hosting two one day events in London at the beginning of December to spill the beans on all aspects of the OpenSPARC design, as well as some history of the SPARC family.

Sadly this is only open to Europractice members from academic institutions, but Sun have continued their theme of openness by making all the slides and documentation available via their web site.