I wonder why NVidia decided to add this complexity to their midrange cards. Correct me if I am wrong, but the NV30/35 never output 8 pixel values at once, only 8 Z/stencil. And, considering the limit of this particular setup (no loopbacks, single texturing and no pixel shaders) I wonder if there are REAL situations (aside synthetic benchmarks) were the ability to write 2 pixels at once is used. Dropping this feature would have saved a few transistors without affecting too much the performance in real world apps.

IMHO nVidia reuse the ROP Design (and everything behind) from NV30. In this case the ROP allready can work with 4 pixel/clock.

The ability to write 4 (simple) pixel per clock is not very usefull for games at all. But In the case of CAD applications it should help much more.