The library will be tested using the 8×8 multiplier example
multi8b supplied with the Alliance software. The regular synthesis
flow uses four programs in sequence to convert file
multi8.vhd
to a structural logic description
multi8.vst.
In the classical flow defined by Alliance, this is done with four commands:

Programs
VASY and
BOOM
refine a VHDL description to an RTL level.
BOOG
maps this to a structural logic description.
LOON
optimises the netlist for speed and area.

One objective of this paper is to define a more sophisticated
command sequence which will give a faster netlist.

The first two programs work at the behavioural level and do not
reference any standard cell library. So the starting point for the
sclib testing will be the netlist produced by BOOM.
However, I have found that this netlist can be improved by applying a
sequence of BOOM commands:

The VHDL description multi8.vbe synthesises to a smaller
and faster netlist that multi8_boom.vbe. The BOOM option -n
applies a "no optimisation" algorithm, but a logic simplification is done which,
for example, reduces the number of cell pins connected to a power supply.
So the starting point will actually be the BOOM netlist
multi8.vbe
produced after the four BOOM steps above.