Back in a former life (when I was hardware design guy) I used to do a lot of work with shift registers. By far the biggest problem I used to see was problems with the clock. In some cases you get a little noise on it that causes extra shift operation. Sometimes the clock rise and fall rates are too slow, or too fast. If you're hand wiring it, it's pretty easy to do have too much capacitance on the clock like, leading to a slow rise time. If that's the case you can always try putting a pullup resistor on that line - that can help sometimes.

My first suggestion would be to use a very good scope on the clocks and other logic lines. Make sure the edges are nice and clean, and getting to the right logic levels. Take a look at the datasheet and make sure the rise and fall times are within specs.

If you've got a multi-trace scope, you should be able to feed a fixed level in the ADC, put one trace (the sync) on whichever signal indicates the start of a data word, and the other on the data. In theory you should be able very clearly see a stable pattern on the scope. If not, there's still something wrong.

One other thing that would be helpful is if you have a schematic of what you're doing. There may be something design-wise that is causing the problem.

I haven't had a lot of time to sit down and work through this, but I think a lot of the trouble may be the reliance on 4024s. Those are ripple counters.
The issue with a ripple counter is that not all of the outputs change state at the same time. That means you can get glitches all over the place.

I'm also concerned about the clock divider. It seems like when when Q3 pops high, you'll reset the counter, but that will mean that the pulse on Q2 output will also get reset. That means that sometimes Q2 will be a nice wide pulse, and sometimes a short glitchy pulse. Depending on what you're trying to do, that glitchy pulse may really cause some havoc.

My gut tells me that you should really look at designing this using synchronous counters instead of the 4024.

{edit} It looks like there is a nice 4 bit synchronous counter called the 4520 available. You might want to look at using that.

GaryLast edited by Mongo1 on Wed Oct 19, 2011 10:03 am; edited 1 time in total

They shouldn't as long as there is enough setup time before you try to access the memory. You should probably be fine as long as you use the inverted clock to derive the read and write signals. That means one phase of the clock will do the counting, and the other phase will access the memory. That's a pretty typical design approach.

That's some pretty wild stuff! I wasn't too sure what was going on there. Were you sampling an incoming stream, or did you have a sample in memory that was constantly replaying? It was a bit difficult to tell.

I think that once I get the ADC passing in the correct data, the fidelity will be better. The serial ADC makes it more complicated than it should be, parallel ADCs are hard to find (maybe not, know any modern models?), and I just purchased a PIC programmer, so I think I might try my hand at using a micro-controller for this project with a new circuit.

That said, I did learn a lot from this little experiment.

I've been thinking about doing the PIC thing myself. I write embedded software for a living, so I kind of hate to do it at home too

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