Technical question:
Can I sever power to an IC while the rest of the circuit is still in operation? This IC and its outputs are not being used while the power is severed.

I have a rotary switch that chooses either channel A, channel B, channel C... or a looping sequence A-B-C, A-B-C, etc. I'd like to use the same indicator lights on the control panel to show which channel is being used - despite whether its going through the 4017 IC, or taking its power directly from the channel select. But, if I don't sever power to the 4017,

This schematic is a gross, gross simplification of the actual circuit (analog sequencer sequential switch) I'm working on... Meant to make it easier to understand than the full confusing-ass sketchmatic. But I'll include the full version, too - in case that helps anyone.

Hopefully the question and materials are clear enough. Basically, can I just kill the 4017 during operation, or will that cause a detectable voltage boost in the rest of my circuit that will screw up the CV output to my synth (I've heard this kind of thing happen before when screwing around on my breadboard). My voltage source is 9V.

The answer is both yes and no. It depends on the circuit and the ICs. Some ICs tolerate being partially powered or having active signals on input pins while not being powered, others do not. Best place to go is the datasheets. Other ICs can be damaged - and again - much depends on the actual circuit in which they are used. It is always best to power the whole thing on or off as a unit. As a general rule of thumb, CD4xxx series logic ICs do not like input pins to be above Vdd or below Vss. If that doesn't happen during this power change, then it should be OK. If, however, the Vdd pin is at ground with a low impedance current path, then any input signal will be above the Vdd level and the parasitic diodes can conduct (which is not a good thing).

You probably want to be mindful of nasty pop noises when you switch power off and on to a chip within a powered design._________________FPGA, dsPIC and Fatman Synth Stuff

Time flies like a banana.Fruit flies when you're having fun.BTW, Do these genes make my ass look fat?corruptio optimi pessima

Ok, thanks JovianP - that's pretty helpful.
Looking at the CD4017 datasheet, it lists absolute maximum VDD voltage range as -.5V to 20v. Then, sounds like if I ensure all IC inputs, including Vdd are at Ground, should be fine.

Scott -
One question about that... If I need the 4017 pin 16 (VDD in) going to ground when that portion of the circuit is shut off, should I use a standard pull-down resistor on pin 16? Or would that be bad to use on the VDD pin?

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