Ching-Chao: We first coined the term “In-Situ De-embedding” (or ISD) for the de-embedding software we launched in 2011. It was a new approach to remove the non-causality artifact commonly found in other de-embedding methods.

Ed: What was the problem you saw coming?

Ching-Chao: Accurate de-embedding is crucial to characterize the electrical performance of a component, from chip to package, PCB, connector and cable. A Vector Network Analyzer (VNA) is perhaps the best equipment to use for characterization because it measures the detailed electrical behavior of a component at every frequency. However, a component, or device under test (DUT), does not usually lend itself to direct measurement and needs to be mounted on a fixture for connection to the VNA. The effect of the fixture needs to be removed (i.e., de-embedded) in order to get the true electrical behavior of the DUT itself.

Ed: So how did the electrical behavior get measured before?

Ching-Chao: The traditional approach is to fabricate and measure test coupons that resemble the fixture’s lead-ins and/or lead-outs. Information is extracted from the test coupons and de-embedded from the fixture + DUT measurement data. To collect more information, the TRL (thru-reflect-line) calibration method requires that multiple test coupons be built. This method takes up a fair amount of board space.

AtaiTec Corp. president Dr. Ching-Chao Huang co-authored a DesignCon 2014 paper that looks at new methodologies to characterize connectors for 25+ Gbps boards.

What’s eye opening is how the authors used AtaiTec’s In-Situ De-embedding (ISD) software to extract connector-only data from a large board and compare them directly with simulation results from a 3D field solver.