3.1.10. Clock generation

Clock generation on the PB-A8 is provided by a PLL implemented
in the Cortex-A8 test chip and a number of on-board programmable
clock generators. The PLL provides the internal clock source for
the processor internal clock divider and external AXI interface. The
on-board programmable clock generators provide clock sources for
the peripherals in the Northbridge, Southbridge and dedicated peripheral
interface devices.
See Clock architecture for details
of PB-A8 clock usage and routing.