TI pushes pillar flip-chip for next-gen ICs

SAN JOSE, Calif. -- Texas Instruments Inc. said that it will no longer use
traditional wirebonding techniques for devices at the 45-/40-nm node and below,
as the workhorse chip-packaging technology is fast running out of gas for
leading-edge designs.

TI (Dallas) will continue to use wirebonding for devices above 45-/40-nm. But
for those nodes and below, TI is embracing an emerging technology called
fine-pitch copper pillar flip-chip packages. The company is jointly working with
IC-packaging specialist Amkor Technology Inc. as part of a long-term
collaboration in the arena.

To move down the process path, the industry mainly talks about chip scaling
and integration. “As an industry, we’ve over-integrated,’’ said Tom Thorpe, vice
president and manager of External Development and Manufacturing at TI.

To enable next-generation designs, chip-packaging is now playing a more
critical role in the IC flow, Thorpe said. Technologies like fine-pitch copper
pillar flip chip packages will enable a new class of application processors,
digital signal processors and power management devices, he added.

In fact, for some time, TI has quietly been shipping its early baseband OMAP
processors based on pillar flip-chip.

For decades, though, IC makers like TI have used cost-effective and workhorse
wirebonders for use in packaging. Chip makers will continue to use wirebonders
for the foreseeable future, but these systems are hitting the wall at the
leading-edge, possibly at the 45-nm node.

One of the ongoing problems is that wirebonding tends to stress and damage
the low-k dielectric interconnects in leading-edge IC designs. There are also
performance issues with packages using wirebonders.

As a result, TI and other chip makers are looking at alternative packaging
techniques. In fact, it has been widely known for about two years that TI is
moving away from wirebonders for leading-edge designs only, he said. “At 45-nm,
we won’t use anymore wirebonders,’’ he said. TI will continue to use wirebonders
for parts at above 45-nm, it was noted.

To enable ''fine-pitch’’ technologies at the 45-/40-nm node and beyond, TI
evaluated three chip-packaging technologies: copper pillar flip chip and two
types of gold studded techniques.

Traditional solder-based flip-chip was not in the cards. For years, chip
makers have used traditional solder-based flip-chip technology for leading-edge
processors, graphics chips and other products. The trouble with solder-based
flip-chip is that the technology hits the wall at 150 micron pitches.
''150-micron pitch is the leading edge,’’ said Mark Gerber, manager of TI’s
worldwide copper pillar program.

Ultimately, for leading-edge ICs, TI selected fine-pitch copper pillar flip-chip
packages, which are said to shrink bump pitch up to 300 percent compared to
current solder bump flip chip technology. Capable of pad structures of less than
50 microns, the technology also boosts performance, making it ideal for wireless
and embedded processing applications, according to TI.

This lead-free technology makes use of a newly developed assembly process.
The fine pitch flip chip layout design methodology typically reduces substrate
layer count as compared to standard area array flip chip, yielding a low-cost
package solution. The fine pitch flip chip package was developed for very thin
die, which, when combined with the low standoff height of the copper pillar bump
itself, reduces package height.

“As chip I/O density increases with each process node, we had to find a way
to decrease the distance between pins,” Thorpe said. “Working together, Amkor
and TI rapidly developed, qualified and deployed a new package platform that
will not only address TI’s flip chip package needs for the next decade but will
also serve as a game changer for the industry. This new packaging technology
will drive down the size and cost of semiconductors while boosting performance
-- a win for TI, Amkor and our customers.”

''We are committed to partnering with TI in applying this new technology on
chip scale packages (CSP), conventional package on package (PoP), and next
generation PoP configurations,” said said Ken Joyce, president and CEO of Amkor
Technology.

Initial production of these packages will take place in Amkor’s plants. Over
time, TI will produce these package types in its own factories.

I'd like to hear a bit more about this in terms of the practical use of the parts. It's interesting in terms of cost savings and performance improvements but the use of the part is an important consideration too. Ti's OMAP processor ends up on a 0.4mm pitch BGA package. That means tighter space and trace limits for the PCB layout as well as vias in the BGA land pads (please fill and plate the vias in the pads). Expect to see this leading to even smaller pitches on the components. I haven't yet seen a 0.3mm pitch part I have heard that they are on the way.

Don't confuse the IC bump pitch with the package bump pitch. Current production IC's are often in the 150 to 250 micron pitch range, while it sounds like this will be closer to 50 microns!
That's going to really challenge probe cards, since even 80 micron area array is tough to pull off these days. Often the package can be used as the space transformer for the probe head. Tricky stuff though... Of course this works for 1 up.. Multi-up represents a new challenge. Finally, they haven't talked about the substrate, which is really the enabler. Finer pitch probably means no solder mask, Sn cap, and 1 or 2 mil traces.. Cool stuff. There aren't that many places that can pull that off.