Industry View: Doug Wong of Toshiba on the Future of Memory

Douglas Wong, senior member of the technical staff for Toshiba, talks about flash memory scaling, going 3D, and his picks for next-generation memory.

The memory industry is in a time of historic change. The shift from PCs to mobile/tablet computing platforms is driving a shift toward NAND flash, and next-generation technologies loom on the horizon. We took the opportunity to talk with Douglas Wong, senior member of the technical staff for Toshiba America Electronic Components, to get his take on key challenges in the memory space and how Toshiba plans to address them.

Douglas Wong, Toshiba

EETimes: What are the biggest challenges facing the memory industry right now?

Douglas Wong: NAND flash has been at the forefront of lithography scaling within the electronics industry. It's the densest thing that's being produced in real volume yet at this point, but certainly scaling is beginning to slow down. Is there a theoretical problem with making things smaller? Really, the answer is probably no. We know we can make things smaller. Direct e-beam is higher resolution, and X-ray lithography would be higher resolution, but it's nowhere near to production capable in any volume. EUV would have been the solution, but it keeps getting pushed out. It's more of an engineering problem than a theoretical problem.

EETimes: Ultimately, though, memory scaling becomes a problem of fundamental physics, right? A gate can only get so small before it can't store enough electrons to perform properly.

Wong: Clearly one of the biggest challenges is endurance. The question is what kind of endurance people really need out of their flash memory today. With current technology, we can still do 3,000 write/erase cycles on two-level-cell memory products. If the density gets higher and the number of write/erase cycles needed gets less, then actually we could probably continue to scale for a while. We're thinking that existing floating-gate technologies will last for at least another five to seven years.

The biggest problem using the latest geometry NAND flash is basically do people have a powerful enough [error correction code] engine on their processor to deal with the latest NAND? As manufacturers, we can release a new NAND technology, but we have to wait for the controllers to catch up. That's always been an ongoing race. We would like a new controller every time we move to a new NAND lithography node, but generally speaking, the controller guys do not necessarily match up with us on product introduction schedules. Of course, you can always avoid scaling by introducing more triple-level cell technologies, but eventually we're going to need some kind of replacement technology.

EETimes: What do you consider the most promising candidates?

Wong: We're basically looking at doing 3D as a first approach, multilevel stacks within the same die. Right now, they have multiple layers for wiring, but really the memory cells themselves are still stuck at the silicon surface. The idea is to stack multiple NAND flash layers vertically, and then we won't have to shrink in the X-Y direction as much. 3D NAND flash and ReRAM, those are basically our front runners for extending nonvolatile memory densities in the future.

The other interesting thing that we've been working on is MRAM. The interesting, exciting thing about that, of course, is the endurance is going to be literally unlimited. A nonvolatile memory that is extremely fast with virtually unlimited write/erase endurance could open up all kinds of opportunities.

The interesting question will be what can that enable? That will change the way electronic systems actually access NAND flash. People today use NAND flash kind of like a hard drive. They copy information at power up from the NAND flash into DRAM and then execute the code itself from the DRAM. With MRAM, you don't have to shadow anymore. It's already there when you turn it on, and it's way faster -- basically close to DRAM speed. So then we have the advantage that you need less endurance from NAND flash when you have that kind of memory available.

Wong: When I worked on the first NAND flash products at Toshiba, a 2MB chip [16Mb] was around $20. Nowadays, $20 would buy you somewhere on the order of 30GB of memory. The original 20MB chip was fabricated using a 0.7Ám process, and today we use a 19nm process. Interestingly enough, I was running the numbers, and the cost per bit has decreased faster than the scaling has decreased. In other words, the ratio of 700nm squared divided by 19nm squared is 1,000x. Even if you take into account two-bit-per-cell versus one-bit-per-cell [architectures], based on physical area, that's only a 2,000x difference, but the price has actually gone down faster than that. Obviously, more than just lithography scaling has contributed to the cost decline. Automation has had something to do with it, and efficiency and the shift to larger wafers, but still, the consumer is not interested in the technology. They are interested in value. The consumer is not willing to pay more for the same capability, so our goal is to continue to reduce the cost per bit, despite using more advanced technologies such as 3D memory.

While 3D memory continues to be developed by our R&D group, we continue to develop existing floating gate NAND technologies. We just announced our latest lithography node, A19 nm, which will be ramping into production later this year, and are actively working on the next generation. And when floating gate NAND are no longer able to scale, the new 3D memory technologies should be ready to become the new standard bearers.

Tom, it is interesting that the subjects of the papers presented at the recent NV Workshop 2013, Monterey, CA, exactly match and reflect Doug Wong and Toshiba's views, with the same three front runners. The breakdown was as follows:-Flash 42.5%, ReRAM 30%, MRAM 12%, PCM 5%, CbRAM 5%, FeRAM 2.5% and memory architecture 2.5%. I included a graphical anaysis of this in the conclusion of Part 2 of my paper on IBM's latest MLC-PCM results. Part 1 of which you will find in EETimes memory section. Always remember the real picture of the future of NV memory is made from many "bits" of "multi-level" and "multi-dimensional" information.

The 3D NAND is multiple layers on same piece of silicon sharing same charge trapping layer. Of course under Coulomb repulsion, the charges may hop to next location, so retention still needs improvement.

Ron: I'd be surprised if Toshiba is ruling those out. My take was that, in this limited space, Wong didn't get to go into everything on the drawing board. But, yes, I'd be interested in hearing his take on those, too.

Doug Wong and Toshiba have 3D-NAND and ReRAM as their non-volatile (NV) memory front runners with MRAM also in the race, with respect to the potential to meet future scaling and write/erase endurance requirements. It would be nice to have heard Doug Wong's considered technical view of why phase-change memory (PCM), ferroelectric FeRAM and CbRAM are not on his or Toshiba's memory list. Should the omission of those latter three technologies from his answers be interpreted as a view that those technologies do not have the potential to scale or meet endurance requirements, or are their other technical reasons why they are not on the list?

The idea of 3D NAND is truly exciting in its potential to blow current performance levels out of the water. I'd be really interested to hear how it would be manufactured, and whether such memory would be, essentially, a cube of current 2D displays, or perhaps in a different shape -- it could be spherical, for example, if that would offer any performance enhancement. Does anyone know the answer to either question?