DesignCon Revs to 28 G, Beyond

Here are eight hot sessions on high-speed design -- many driven by the move to 100G Ethernet -- at least some of which Rick Merritt hopes to see this week.

Many of the world's top experts in high-speed chip and board design will convene in Silicon Valley this week at DesignCon to explore the engineering zen of life at 28 Gbit/s and beyond.

The event gathers signal and power integrity specialists to explore every technique for squeezing an extra drop of link budget to enable ultra-fast connection. Topics span everything from signaling techniques to channel materials, the latest in gigahertz testers, and new modeling and simulation software. Here are just eight of the several dozen sessions at the show that give some flavor of the need for speed in today's leading-edge designs.

Engineers from Cisco, Intel, Marvel, and other companies will give an update on the 100 Gbit/s Ethernet backplane standard, a.k.a. IEEE 802.3bj. Their focus is on signaling techniques for tight link budgets. In a separate session, Cisco engineers will talk about hitting acceptable bit-error rates on 100G designs.

The rise of Internet traffic, especially over mobile systems, is driving a need for 100G links in core networks. Those links are primarily built up from four 25G connections based on 28G SerDes. Several sessions will explore the nuances of taming 28G SerDes, including one from SiSoft.

LSI engineers will push beyond some of the 28G work in a talk on a 56 Gbit/s chip-to-module link that gives a look at what's coming next. Similarly, Rambus will take a look into the future in a session on optimization techniques for a package-to-board interface of a 50 Gbit/s medium-reach SerDes channel.

The IEEE 802.3bq standard for delivering 40G of Ethernet 30 meters over copper twisted pairs is the subject of a talk by Cisco. Two engineers from Ericsson will talk more broadly about issues getting high-speed serial links into production systems.

Experts from Altera, Broadcom, Huawei, Juniper, and Samsung will also present their work. And, as usual, there will be a solid collection of high-speed design consultants, the firemen who step in when designs just aren't working.

I don't expect I'll be able to get to even half of these sessions, which are just some of the cream of the conference. If you are showing or seeing something cool at DesignCon, jump on the message boards here or around one of our other stories on the event, and give us the benefit of your perspective.

We've been hearing for years that FR4 is dead, but it's the gift that just keeps on giving. Why? Because engineers keep finding ways to get enough signal integrity out of it and avoud going to more expensive laminates. Thins the pre-emphasis, smarter PCB design, and better simulation tools have let that happen. Plus, not everyone needs the highest data rates. It's really just at the data centers and server farms. the rest of us can ive with 1Gbps and even slower. Case in point, a tutorial on jitter at DesginCon was attended by over 200 people. There were plenty of people at DesginCon who are now just trying fr figure out how to design for 10Gbps.

Seems to me if someone could invent and patent an FR4 replacement that was cost effective they could make profits as large as some countries' GDP. What we need is one of these new materials to also be more effective at insulating homes or going into auto bodies to get manufacturing volumes up and unit cost down. Has EE Times published any articles on who's driving research in this area?