9.2 Master and slave modes

In a multi-processor operation when the SPI interface is used, the microcontrollers operate in the master and slave modes. In master mode the microcontroller is in full control of the communication since it initiates and ends the communication session and generates the SPI clock signal. In slave mode the microcontroller listens when the master initiates and ends the communication session and uses the SPI clock signal generated by the master. SPI master/slave connection is shown in Fig. 9-2. The figure shows the 4-pin SPI interface even though this connection can also operate with the 3-pin SPI interface.

Fig. 9-2 Master/slave connection using SPI interface

NOTE: Using the SSx pin in slave mode of operation is optional.

9.2.1 Master Mode

The following steps should be taken to set up the SPI module for the master mode of operation:

If using interrupts:

Clear the SPIxIF bit in the respective IFSn register,

Set the SPIxIE bit in the respective IECn register,

Write the SPIxIP bits in the respective IPCn register.

Write the desired settings to the SPxCON register with MSTEN (SPIxCON<5>) =1.

Clear the SPIROV (SPIxSTAT<6>) status bit.

Enable SPI operation by setting the SPIEN (SPIxSTAT<15>) control bit.

Write the data to be transmitted to the SPIxBUF register. Transmission will start as soon as data are written to the SPIxBUF register.

In master mode, the system clock is prescaled and then used as the serial clock. The prescaling is based on the settings in the PPRE<1:0> (SPIxCON<1:0>) and SPRE<1:0> (SPIxCON<4:2>) control bits. The serial clock generated in the master device is via the SCKx pin sent to slave devices. Clock pulses are only generated when there are data to be transmitted/received. The CKP (SPIxCON<6>) and CKE (SPIxCON<8>) control bits determine on which edge of the clock data transmission occurs.

Fig. 9-3 SPI module in master mode of operation

With the help of Fig. 9-3, the following description of the SPI module operation in master mode can be given.

Once the module is set up for master mode of operation and enabled, data to be transmitted are written to the SPIxBUF register, i.e. to the SPIxTXB register, the sequence of transmitting via the SPI transmitter starts. The presence of new data in the SPIxBUF register, i.e. in the SPIxTXB buffer, is denoted by setting the SPITBF status bit (SPIxSTAT<1>).

The contents of the SPIxTXB register are moved to the shift register, SPIxSR, and the SPITBF bit is cleared by the module.

A series of 8/16 clock pulses shifts out 8/16 bits of transmit data from the SPIxSR to the SDOx pin and simultaneously shifts in the data at the SDIx input pin into the SPIxSR register of the slave device.

When the transfer is complete, the following events will occur:

The interrupt flag bit, SPIxIF, is set. SPI interrupts can be enabled by setting the interrupt enable bit SPIxIE. The SPIxIE flag is not cleared automatcally by the hardware.

Also, when the ongoing transmit and receive operation is completed, the contents of the SPIxSR are moved to the SPIxRXB register.

The SPIRBF (SPIxSTST<0>) is set by the module, indicating that the receive buffer is full. Once the SPIxBUF register is read by the used code, the hardware clears the SPIRBF bit.

If the SPIRBF bit is set (receive buffer is full) when the SPI module needs to transfer data from SPIxSR to SPIxRXB, the module will set the SPIROV (SPIxSTST<6>) status bit, indicating an overflow condition.

Data to be transmitted can be written to SPIxBUF by the user software at any time as long as the SPITBF (SPIxSTST<1>) status bit is clear. The write can occur while SPIxSR is shifting out the previously written data, allowing continuous transmission.

9.2.2 Slave mode

The following steps should be taken to set up the SPI module for the slave mode of operation:

In slave mode, data are transmitted and received as the external clock pulses appear on the SCKx pin. The CKP (SPIxCON<6>) and CKE (SPIxCON<8>) control bits determine on which edge of the clock data transmission occurs. Both data to be transmitted and data that are received are respectively written into or read from the SPIxBUF register.
A few additional features provided in the slave mode are:

Slave select synchronization – the SSx pin allows a synchronous slave mode. If the SSEN (SPIxCON<7>) control bit is set, transmission and reception is enabled in slave mode only if the SSx pin is driven to a low state (pin SSx is active if at the low logic level). If the SSEN bit is set and the SSx pin is driven high, the SDOx pin is no longer driven and the current transmission stops even if the module is in the middle of a transmission. An aborted transmission will be retried the next time the SSx pin is driven low. If the SSEN (SPIxCON<7>) control bit is cleared, the SSx pin does not affect the SPI interface (three-pin SPI interface).

SPITBF status flag operation – the function of the SPITBF (SPIxSTAT<1>) bit is different in the slave mode od operation. The following describes the function of the SPITBF for various settings of the slave mode of operation:

If SSEN (SPIxCON<7>) is cleared (3-pin SPI interface), the SPITBF is set when the SPIxBUF (i.e. SPIxTXB) is loaded by the user code. It is cleared when the module transfers SPIxTXB to the shift register SPIxSR. This is similar to the SPITBF bit function in master mode.

If SSEN (SPIxCON<7>) is set (4-pin SPI interface), the SPITBF is set when the SPIxBUF (i.e. SPIxTXB) is loaded by the user code. It is cleared only when the module completes data transmission. A transmission will be aborted when the SSx pin goes high and may be retried at a later time when the pin goes low. Each data word is held in SPIxTXB until all bits are transmitted to the receiver.

Fig. 9-4 SPI slave mode: 3-pin SPI interface

Fig. 9-5 SPI slave mode: 4-pin SPI interface

Fig. 9-6 CKP and CKE bit functionality

The operation for 8-bit mode is shown. The 16-bit mode is similar.
When a new data word has been shifted into SPIxSR and the previous contents of SPIxRXB have not been read by the user software, the SPIROV bit (SPIxSTAT<6>) will be set (overflow condition). The module will not transfer the received data from SPIxSR to SPIxRXB. Further data reception is disabled until the SPIROV bit is cleared. The SPIROV bit is not cleared automatically by the module and must be cleared by the user software.
Setting the control bit DISSDO (SPIxCON<11>) disables transmission at the SDOx pin. This allows the SPIx module to be configured for a receive only mode of operation. If the DISSDO bit is set, the SDOx pin will be controlled by the respective port function (input or output).