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Abstract:

A semiconductor structure comprises a top metal layer, a bond pad formed
on the top metal layer, a conductor formed below the top metal layer, and
an insulation layer separating the conductor from the top metal layer.
The top metal layer includes a sub-layer of relatively stiff material
compared to the remaining portion of the top metal layer. The sub-layer
of relatively stiff material is configured to distribute stresses over
the insulation layer to reduce cracking in the insulation layer.

Claims:

1. A semiconductor structure, the structure comprising: a top metal
layer, the top metal layer including a sub-layer of relatively stiff
material compared to the remaining portion of the top metal layer, a bond
pad formed on the top metal layer; a conductor formed below the top metal
layer; and an insulation layer separating the conductor from the top
metal layer; wherein the sub-layer of relatively stiff material is
configured to distribute stresses over the insulation layer to reduce
cracking in the insulation layer.

2. The semiconductor structure of claim 1, wherein the sub-layer extends
to cover an area at least as large as the area under the bond pad.

3. The semiconductor structure of claim 1, wherein the insulation layer
has a thickness selected to resist cracking due to vertical and
horizontal stresses on the semiconductor structure.

4. The semiconductor structure of claim 1, wherein the insulation layer
has a thickness that resists formation of cracks due to stresses caused
by at least one of a bond wire attachment process or temperature
excursions.

5. The semiconductor structure of claim 1, wherein the conductor is
patterned with gaps.

6. The semiconductor structure of claim 5, wherein the gaps extend in a
direction of current flow through the conductor.

7. A method of forming a semiconductor structure comprising: forming a
top metal layer, wherein forming the top metal layer includes forming a
sub-layer of the top of metal layer, the sub-layer being relatively stiff
compared to the remaining portion of the top metal layer, forming a bond
pad on a surface of the top metal layer; forming a conductor below the
top metal layer; and forming an insulation layer separating the conductor
from the top metal layer; wherein the sub-layer of relatively stiff
material is configured to distribute stresses over the insulation layer
to reduce cracking in the insulation layer.

8. The method of claim 7, wherein forming the sub-layer comprises forming
the sub-layer to extend over an area at least as wide as the area under
the bond pad.

9. The method of claim 7, wherein forming the insulation layer comprises
forming the insulation layer with a thickness selected to resist cracking
due to vertical and horizontal stresses on the semiconductor structure.

10. The method of claim 7, wherein forming the insulation layer comprises
forming the insulation layer with a thickness that resists formation of
cracks due to stresses caused by at least one of a bond wire attachment
process or temperature excursions.

11. The method of claim 7, further comprising patterning the conductor
with gaps.

12. The method of claim 11, wherein patterning the conductor with gaps
comprises patterning the gaps to extend in a direction of current flow
through the conductor.

13. A semiconductor structure comprising: at least one electrical device
in a substrate; one or more intermediate metal layers between a top metal
layer and the substrate; one or more insulation layers, the one or more
insulation layers separating the one or more intermediate metal layers
and the top metal layer; and a passivation layer over the top metal
layer; the passivation layer patterned to form a bond pad on a surface of
the top metal layer, wherein the at least one electrical device is
located directly under the bond pad; and wherein one of the one or more
insulation layers located adjacent to the top metal layer has a thickness
selected to resist cracking due to stresses caused by at least one of a
bond wire attachment process or temperature excursions.

14. The semiconductor structure of claim 13, wherein the insulation layer
having a thickness selected to resist cracking is relatively thicker than
the other insulation layers.

15. The semiconductor structure of claim 13, wherein the insulation layer
having a thickness selected to resist cracking has a thickness of at
least 1.5 μm.

16. The semiconductor structure of claim 13, wherein the top metal layer
further comprises a sub-layer of the top metal layer, the material of the
sub-layer being relatively stiff compared to other portions of the top
metal layer.

17. The semiconductor structure of claim 13, wherein a conductor formed
from a segment of the intermediate metal layer that is adjacent to the
insulation layer that is adjacent to the top metal layer has at least one
gap, at least a portion of the conductor formed directly under the bond
pad.

18. The semiconductor structure of claim 17, wherein the at least one gap
extends in a direction of current flow through the conductor.

19. The semiconductor structure of claim 13, further comprising: one or
more vias formed in the insulation layer located adjacent to the top
metal layer to interconnect the at least one electrical device with the
top metal layer.

Description:

[0001] This application is a continuation of prior U.S. patent application
Ser. No. 12/825,030 filed Jun. 28, 2010, which is a continuation of U.S.
patent application Ser. No. 11/737,392 filed Apr. 19, 2007, now U.S. Pat.
No. 7,795,130, which is a continuation of Ser. No. 11/305,987, filed Dec.
19, 2005, now U.S. Pat. No. 7,224,074, which is a divisional of prior
patent application Ser. No. 10/698,184, filed Oct. 31, 2003, now U.S.
Pat. No. 7,005,369, which claims the benefit under 35 U.S.C. §119(e)
of U.S. Provisional Application Ser. No. 60/496,881, filed Aug. 21, 2003,
and U.S. Provisional Application Ser. No. 60/507,539, filed Sep. 30,
2003, all of which are incorporated herein by reference in their
entirety.

TECHNICAL FIELD

[0002] The present invention relates generally to the formation of
semiconductor devices and in particular a formation of active circuits
under a bond pad.

BACKGROUND

[0003] Integrated circuits comprise two or more electronic devices formed
in and/or on a substrate of semi-conductive material. Typically, the
integrated circuits include two or more metal layers that are used in
forming select devices and interconnects between said devices. The metal
layers also provide electrical paths to input and output connections of
the integrated circuit. Connections to the inputs and outputs of the
integrated circuit are made through bond pads. Bond pads are formed on a
top metal layer of the integrated circuit. A bonding process (i.e. the
bonding of a ball bond wire to the bond pad) can damage any active
circuitry formed under the metal layer upon which the bonding pad is
formed. Therefore, present circuit layout rules either do not allow any
circuitry to be formed under the bonding pad or only allow limited
structures that have to be carefully tested.

[0004] Damage under bonding pads can be caused by many reasons but mainly
it is due to the stresses which have occurred during bond wire attachment
process and the subsequent stresses after packaging. For example,
temperature excursions after packaging exert both lateral and vertical
forces on the overall structure. The metal layers of integrated circuit
are typically made of soft aluminum that are separated from each other by
harder oxide layers. The soft aluminum tends to give under the forces
while the harder oxide layers do not. This eventually leads to cracks in
the oxide layers. Once an oxide layer cracks, moisture can enter causing
corrosion of the aluminum layers and eventually failure of the circuit
function. Therefore, the bonding process typically requires the real
estate below the bond pad serve only as a buffer against damage that
occurs during the bonding process. However, as chip designers try and
reduce the size of chips it would be desired to able to use the real
estate under the bonding pad for active circuits or interconnects.

[0005] For the reasons stated above and for other reasons stated below
which will become apparent to those skilled in the art upon reading and
understanding the present specification, there is a need in the art for
an improved integrated circuit that effectively allows for use of the
real estate under bonding pads for active circuits and interconnects.

SUMMARY

[0006] The above-mentioned problems of current systems are addressed by
embodiments of the present invention and will be understood by reading
and studying the following specification. The following summary is made
by way of example and not by way of limitation. It is merely provided to
aid the reader in understanding some of the aspects of the invention.

[0007] In one embodiment, a semiconductor structure is provided. The
structure comprises a top metal layer, a bond pad formed on the top metal
layer, a conductor formed below the top metal layer, and an insulation
layer separating the conductor from the top metal layer. The top metal
layer includes a sub-layer of relatively stiff material compared to the
remaining portion of the top metal layer. The sub-layer of relatively
stiff material is configured to distribute stresses over the insulation
layer to reduce cracking in the insulation layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present invention can be more easily understood and further
advantages and uses thereof more readily apparent, when considered in
view of the description of the preferred embodiments and the following
figures in which:

[0009] FIG. 1 is a partial cross-sectional view of an integrated circuit
of one embodiment of the present invention;

[0010] FIG. 2 is a top view of a portion of a metal layer with gaps of one
embodiment of the present invention; and

[0011] FIGS. 3A through 3G are partial cross-sectional side views of one
method of forming an integrated circuit in one embodiment of the present
invention.

[0012] In accordance with common practice, the various described features
are not drawn to scale but are drawn to emphasize specific features
relevant to the present invention. Reference characters denote like
elements throughout Figures and text.

DETAILED DESCRIPTION

[0013] In the following detailed description of the preferred embodiments,
reference is made to the accompanying drawings, which form a part hereof,
and in which is shown by way of illustration specific preferred
embodiments in which the inventions may be practiced. These embodiments
are described in sufficient detail to enable those skilled in the art to
practice the invention, and it is to be understood that other embodiments
may be utilized and that logical, mechanical and electrical changes may
be made without departing from the spirit and scope of the present
invention. The following detailed description is, therefore, not to be
taken in a limiting sense, and the scope of the present invention is
defined only by the claims and equivalents thereof.

[0014] In the following description, the term substrate is used to refer
generally to any structure on which integrated circuits are formed, and
also to such structures during various stages of integrated circuit
fabrication. This term includes doped and undoped semiconductors,
epitaxial layers of a semiconductor on a supporting semiconductor or
insulating material, combinations of such layers, as well as other such
structures that are known in the art. Terms of relative position as used
in this application are defined based on a plane parallel to the
conventional plane or working surface of a wafer or substrate, regardless
of the orientation of the wafer or substrate. The term "horizontal plane"
or "lateral plane" as used in this application is defined as a plane
parallel to the conventional plane or working surface of a wafer or
substrate, regardless of the orientation of the wafer or substrate. The
term "vertical" refers to a direction perpendicular to the horizontal.
Terms, such as "on", "side" (as in "sidewall"), "higher", "lower",
"over," "top" and "under" are defined with respect to the conventional
plane or working surface being on the top surface of the wafer or
substrate, regardless of the orientation of the wafer or substrate.

[0015] Embodiments of the present invention provide a method and structure
of an integrate circuit that allows the use of real estate under bonding
pads for active devices and interconnects. Moreover, embodiments of the
present invention provide a structure that can use all the metal layers
below the bond pad for functional interconnections of the device. In
addition, embodiments of the present invention also provide a structure
that allows submicron interconnects lines with a TiN top layer and
relatively wide lines capable of carrying high currents to exist
simultaneously under a bond pad.

[0016] FIG. 1 illustrates a partial cross-section view of an integrated
circuit 100 of one embodiment of the present invention. In this
embodiment, the part of the integrated circuit 100 shown includes a
N-channel MOS power device 102, a N-DMOS device 104 and a NPN bipolar
device 106. As FIG. 1 also illustrates three conductive layers, which in
this embodiment includes a first metal layer M1 108, a second metal layer
M2 110 and a third metal layer M3 112. The metal layers 108, 110, and 112
can be made of conductive material such as aluminum, copper and the like.
Moreover, in another embodiment, at least one of the metal layers 108,
110 and 112 is made by a sub-micron process that forms many sub-layers of
alternating conductive layers. The third metal layer M3 112 can be
referred to as the top metal layer 112. As illustrated, a bond pad 130 is
formed on a surface of the third metal layer M3 112 by patterning a
passivation layer 132. A ball bond wire 114 (bond wire 114) can be
coupled to the bonding pad 130 to provide an input or output to the
integrated circuit 100. Although, this embodiment, only illustrates three
metal layers 108, 110 and 112, other embodiments have more or less metal
layers. For example, in an embodiment with more than three metal layers,
additional metal layers are formed between metal layers 108 and 110. Each
interconnect metal layer 108, 110 and 112 is formed by conventional
methods known in the art such as depositing and patterning.

[0017] As illustrated in FIG. 1, vias 116 selectively couple the
interconnect metal layers 110 and 108 to form electrical connections
between devices 102, 104 and 106 of the integrated circuit 100. Further
shown are vias 118 that provide electrical connections to elements of the
devices 102, 104 and 106 and the first metal layer 108.

[0018] In one embodiment, the sub-micron process is used to form metal
layer M2 110 and metal layer M3 112. The sub-micron process uses many
sub-layers to form a metal layer. In one embodiment, the sub-layers are
alternating layers of Ti, TiN and Al alloys. Further in one embodiment,
the top layer of the sub-layers of metal layer 110 (i.e. the sub-layer
facing metal 112) is a TiN layer 120. The TiN layer 120 is used in this
location because of its low reflective properties that aid in the
pattering of metal layer 110. However, the presence of sub-layer 120
tends to increase the probability that cracks will form in an oxide layer
separating the metal layer 110 from metal layer 112. In particular,
because the TiN layer tends to be hard it doesn't yield when stress is
applied. As a result, lateral stresses on the separating oxide tend to
form cracks in the separating oxide layer. Further in another embodiment,
a layer of TiW forms sub-layer 120.

[0019] Embodiments, of the present invention reduce the probability of the
cracks forming in the separating oxide layer 122. In one embodiment, the
separating oxide layer 122 (i.e. the oxide layer that separates metal
layer 110 from metal layer 112) is formed to be relatively thick. In one
embodiment, the separating oxide layer 122 is formed to be at least 1.5
um thick. The use of a separating oxide layer 122 that is relatively
thick reduces the probabilities of crack forming in the oxide layer 122.
In further another embodiment, the separating oxide layer is generally a
dielectric or insulating layer.

[0020] Moreover in one embodiment, the third metal layer M3 112 includes a
relatively hard sub layer 126 of very stiff and hard material. The hard
sub-layer 126 is formed adjacent the separating oxide layer 122 and
opposite a side of the third metal layer M3 forming the bond pad 114. The
hard sub layer 126 is very stiff and hard compared to aluminum. The hard
sub layer distributes lateral and vertical stresses over a larger area of
the oxide 122 thereby reducing the propensity of cracking in the oxide
122. In one embodiment, the material used for the hard sub-layer 126 is
TiN. This is due to the compatibility of TiN with conventional sub-micron
deposition and etch techniques. In yet another embodiment, the hard
sub-layer 126 is a layer of nitride. In one embodiment, the hard
sub-layer 126 is approximately 80 nm in thickness. In further other
embodiments, materials such as TiW are used for the hard sub-layer 126.

[0021] In further another embodiment, the second metal layer M2 110 is
formed to have gaps 124 in selected areas. Very wide (lateral widths) of
the second metal layer 110 tend to weaken the structure thus creating a
higher chance that cracks will occur in the separating oxide layer 122.
In this embodiment, the gaps 124 tend to strengthen the structure by
providing pillars of harder oxide. The impact of the gaps 124 on the
function of the integrated circuit is minimized by the proper layout.
That is, the density of the gaps may be minimized so that a layout design
is not constrained significantly. In one embodiment, the gaps 124 take no
more than 10% of the total area of the second metal layer M2 110 under
the bond pads. In another embodiment, the gaps are oriented such that the
impact on current flow through the second metal layer M2 110 is
minimized. An example of gaps 124 formed to minimize the impact on the
current flow in the second metal layer M2 is illustrated in FIG. 2. FIG.
2, also illustrates the third metal layer 112.

[0022] FIGS. 3A through 3G illustrates the forming of relevant aspects of
one embodiment of the present invention. FIG. 3A illustrates a partial
cross-sectional side view of the start of the formation of an integrated
circuit 300 on a substrate 301. The partial cross-sectional side view
illustrates that integrated circuit 300 in this embodiment includes a
N-Channel MOS 302, a N-DMOS 304 and a NPN device 306. It will be
understood in the art that other types of devices can be formed in the
integrated circuit 300 and that the present invention is not limited to
only integrated circuits with N-Channel MOS, a N-DMOS and NPN devices.
Since the formation of the devices 302, 304 and 306 are not a critical
part of the present invention, FIG. 3A illustrates that they are already
formed. These devices 302, 304 and 306 are formed by techniques known in
the art such as deposition, etching masking and implantation. A first
insulating layer 308 is formed overlaying devices 302, 304 and 306. In
one embodiment, the insulating layer 308 is a layer of first oxide layer
308. Vias 310 are formed by techniques known in the art such as masking
and etching. The vias 310 are then filled with conductive material to
form contacts with the first metal layer 312 and elements of the devices
302, 304 and 306. The first metal layer 312 is formed by first depositing
a metal layer and then patterning the first metal layer 312 to form
select interconnects. A second insulating layer 314 is then formed
overlaying the first metal layer M1 312 and exposed areas of the first
oxide layer 308. In one embodiment, the second insulting layer 314 is a
second oxide layer 314. Vias are formed in the second layer of oxide 314
by masking a surface of the second layer of oxide and etching the vias
316 down to select portions of the patterned first metal layer 312. The
vias 316 are then filled with conductive material.

[0023] Referring to FIG. 3B, a second metal layer M2 318 is deposited on a
surface of the second oxide layer. In one embodiment, the second metal
layer 318 is formed by a sub-micron process comprising a plurality of
alternating layers of different metals. In one embodiment, the
alternating layers of metal are Ti, TiN and Al alloys. A top sub layer
320 of the second metal layer M2 318 is made of TiN which aids in the
pattering of the second metal layer M2 318. The top sub layer 320 is
illustrated in FIG. 3C. As illustrated in FIG. 3C, in this embodiment,
the second metal layer 318 is then patterned to form gaps 322. The gaps
322 strengthen the structure by providing pillars of hard oxide. A third
insulating layer 324 is then formed overlaying the second metal layer M2.
This is illustrated in FIG. 3D. In one embodiment, the third insulating
layer 324 is a third oxide layer 324. The third oxide layer 324 also
fills in the gaps 322. In one embodiment, the third oxide layer 324
(separating oxide layer 324) is formed to be relatively thick. Moreover,
in one embodiment the thickness of the separating oxide layer 324 is at
least 1.5 um.

[0024] A layer of relatively stiff and hard metal layer 326 is then formed
on the surface of the separating oxide layer 324. This is illustrated in
FIG. 3E. This hard layer 326 distributes both lateral and vertical stress
is over a larger area of the separating oxide layer 324. Some embodiments
of the hard layer 326 are formed by a layer of nitride such as TiN or
SiN. In yet another embodiment the hard layer 326 is formed by a layer of
TiW. Moreover, in one embodiment, the hard layer 326 is formed to be
approximately 80 nm in thickness. Referring to FIG. 3F the third metal
layer M3 328 is formed overlaying hard layer 326. In one embodiment, the
hard layer 326 is a sub layer formed during the formation of the third
metal layer M3 328 by conventional sub-micron deposition and etch
techniques. In still another embodiment (not shown), the hard layer 326
is a sub layer of the third metal layer M3 328 formed near the separating
oxide layer 324. A bond pad 330 is then formed on an upper surface of the
third metal layer M3 328 by patterning a deposited passivation layer 332.
This is illustrated in FIG. 3G. Further as illustrated in FIG. 3G, a ball
bond wire 334 is then coupled to the bond pad 330. Although, not shown in
the Figures, vias are formed in the relatively thick oxide 324 so that
the top metal layer 328 can also be used to interconnect devices.
Moreover, it will be understood in the art that a single integrated
circuit may have multiple bond pads and the present invention is not
limited to a single bond pad.

[0025] Although specific embodiments have been illustrated and described
herein, it will be appreciated by those of ordinary skill in the art that
any arrangement, which is calculated to achieve the same purpose, may be
substituted for the specific embodiment shown. This application is
intended to cover any adaptations or variations of the present invention.
Therefore, it is manifestly intended that this invention be limited only
by the claims and the equivalents thereof.