Using Vivado IP with SynplifyThis document is a step-by-step guide to incorporating Vivado-generated IP, using the H-2013.03 versions of the synthesis software. The methodologies described here only apply to the H-2013.03 releases. Methodologies will change in subsequent releases, as further improvements are scheduled.

Analyzing Conversion Issues with Gated Clocks and Generated ClocksThe Synopsys FPGA synthesis tools provide two features, Fix Gated Clocks and Fix Generated Clocks, which move the generated clock and gated clock logic from the clock pin of a sequential element to its enable pin. However, some situations require unconverted clock structures to be modified. This document explains what to do when user intervention is required for the conversion to be performed.

Inferring Xilinx RAMsAs field-programmable gate arrays become larger and more complex, so do the resources available on the FPGA chip. One such resource is dedicated built-in RAM. Xilinx devices offer two RAM memory resources, block RAM and distributed RAM, which can either be inferred automatically from the RTL code or instantiated in your design using Synplify software. This application note focuses on the inference of synchronous block RAM and distributed RAM in the Synplify Pro and Synplify Premier FPGA synthesis tools.