Statistical Modeling and Worst-Case Design Parameters

Abstract

In integrated circuit technology, the final dimensions of all structures (transistors, capacitors, interconnecting wires, etc.) on finished wafers usually differ from their drawn (intended) dimensions due to several processing effects such as lateral expansion of local oxidation, imperfect etching, mask alignment tolerances, etc. It is observed, for example, in a 2 μm CMOS process, a polysilicon line drawn to be 2μm could be any where between 1.3–1.8 μm. Similarly, a 4 μm drawn metal line would turn out to be anywhere between 3.2–4.2 μm. Further, since transistor dimensions are determined by the width of the crossing polysilicon and by the lateral diffusion of the source and drain, transistor width to length ratio (Wm/Lm) can vary appreciably from the intended value. In addition to the line-width variations, there are many other process related variations such as changes in oxide thickness, sheet resistance, threshold voltage, etc., which result in the spread in device performance. Clearly, device parameters are subject to statistical variations due to manufacturing process disturbances. These variations affect the circuit performance dramatically. For example, changes in threshold voltage due to process variations will result in changes in transistor characteristics, which in turn affect DRAM access time and refresh rate, clock speed, etc., in digital circuits and op-amp gain in analog circuits. In the worst case the circuits might cease to function.