tag: PPA

Rising systemic complexity and more potential interactions in heterogeneous designs is making it much more difficult to ensure a chip, or even a block within a chip, will functioning properly without actually monitoring that behavior in real-time.
Continuous and sporadic monitoring have been creeping into designs for the past couple of decades. But it hasn’t always been clear how effective... » read more

Power-related issues are beginning to clash with process variation at 7/5nm, making timing closure more difficult and resulting in re-spins caused by unexpected errors and poor functional yield.
Variability is becoming particularly troublesome at advanced nodes, and there are multiple causes of that variability. One of the key ones is the manufacturing process, which can be affected by every... » read more

Reliability is emerging as the top priority across the hottest growth markets for semiconductors, including automotive, industrial and cloud-based computing. But instead of replacing chips every two to four years, some of those devices are expected to survive for up to 20 years, even with higher usage in sometimes extreme environmental conditions.
This shift in priorities has broad ramificat... » read more

The surge of data from nearly ubiquitous arrays of sensors is changing the dynamics of where and how that data is processed. There is simply too much data to send everything to a centralized processing facility in the cloud, and even 5G won't provide enough bandwidth to handle all of this data.
This has big implications on a much broader scale. Data is valuable. And while clean data is more ... » read more

Anirudh Devgan, president of Cadence, sat down with Semiconductor Engineering to discuss machine learning inside and outside of EDA tools and how that will affect the future of chip and system design. What follows are excerpts of that discussion.
SE: How do you see the market and use of machine learning shaping up?
Devgan: There are three main areas—machine learning inside, machine lear... » read more

Safety and security are emerging as key design tradeoffs as chips are added into safety-critical markets, adding even more complexity into an already complicated optimization process.
In the early days of semiconductor design, performance and area were traded off against each other. Then power became important, and the main tradeoffs became power, performance and area (PPA). But as chips inc... » read more

Activity surrounding the 5nm manufacturing process node is quickly ramping, creating a better picture of the myriad and increasingly complex design issues that must be overcome.
Progress at each new node after 28nm has required an increasingly tight partnership between the foundries, which are developing new processes and rule decks, along with EDA and IP vendors, which are adding tools, met... » read more

It wasn’t too long ago that machine learning (ML) seemed like a fascinating research topic. However, in no time at all, it has made a swift transition from a world far-off to common presence in news, billboards, workplaces, and homes. The concept itself is not new but evidently what has caused it to take off is the rapid growth of data in many applications and more computational power. Closer... » read more

As designs increase in complexity to cater to the insatiable need for more compute power — which is being driven by different AI applications ranging from data centers to self-driving cars—designers are constantly faced with the challenge of meeting the elusive power, performance and area (PPA) targets.
PPA over-design has repercussions resulting in increased product cost as well as pote... » read more