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Abstract

For higher density DRAMs, the pitch of the metal lines significantly influences the cell, and thereby the chip density. For the 256 Mb DRAM, although the projected minimum lithography dimension is 0.25 mm, further reducing the metal linewidth would improve the line capacitance and line-to-line coupling noise. For damascene metal lines, spacer techniques may be used to reduce the width of the oxide groove. However, tops of the spacers are always tapered, so, if used, damascene metal lines would have the same width as the minimum lithography dimension near the top. Proposed below is the use of selective oxide deposition to fabricate sub-lithographic damascene metal lines. In addition, we also propose the fabrication of sub-lithographic contact holes using selective oxide growth. Proposed process flow

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United States

Language

English (United States)

This text was extracted from an ASCII text file.

This is the abbreviated version, containing approximately
52% of the total text.

For higher
density DRAMs, the pitch of the metal lines
significantly influences the cell, and thereby the chip density. For
the 256 Mb DRAM, although the projected minimum lithography dimension
is 0.25 mm, further reducing the metal linewidth would improve the
line capacitance and line-to-line coupling noise. For damascene
metal lines, spacer techniques may be used to reduce the width of the
oxide groove. However, tops of the
spacers are always tapered, so,
if used, damascene metal lines would have the same width as the
minimum lithography dimension near the top.
Proposed below is the
use of selective oxide deposition to fabricate sub-lithographic
damascene metal lines. In addition, we
also propose the fabrication
of sub-lithographic contact holes using selective oxide growth.
Proposed process flow

The proposed
process flow is described below.
1. The photoresist over the oxide is
exposed and grooves are etched
in the oxide, as shown in Figure 1 and Figure 2. If a contact is
needed to a diffusion or a metal underneath, the etch is done down to
the diffusion or the metal.
2. Now the wafer is immersed in a
solution of hydroflurosilicic
acid (H2SiF6) solution saturated with silica (SiO2). The continuous
addition of boric acid (H3BO3) causes oxide deposition at the oxide
surface at room temperature (1,2). The
rate of addition of boric
acid and SiO2 concentration may be adjusted to prevent the formation
of any oxide residue on resist...