Hello! I have added sdram chip support to https://github.com/MIPSfpga/mipsfpga-plus project (mfp_ahb_ram_sdram module). It was successfully tested on Terasic DE10-Lite board and can be ported to other boards.

Supported boards: – Terasic DE10-Lite

Main features: – sdram access module is very small (about 300 rows); – only x16 sdram DQ width is supported; – only main operations are supported (init, read, write and auto-refresh); – page (burst) memory access is not supported; – cpu clock is used to run sdram access module (no clock domain crossing); – it is easy tunable: all time constraints are coded as module params; – Micron Technology, Inc. (“MTI”) SDRAM Verilog model (v2.3) is used for simulation; – all code is simulated with modelsim and tested on Terasic DE10-Lite board; – 04_memtest program added – it writes a big array to memory, flushes cache and then read it after delay. The program displays the current step on LED. 7-segment indicator shows information about current iteration and error count. – there is a separate sandbox, where I have developed this sdram access module: https://github.com/zhelnio/ahb_lite_sdram. It contains some testbenches and standalone hardware tests. This project includes AHB-Lite master, that works without cpu. It can be used to port sdram support to other boards. – MFP_USE_SLOW_CLOCK_AND_CLOCK_MUX is not supported with sdram; – PLL ip core have to be added to board top level code to provide fixed memory clock shift;