4DSP Support

said
over 3 years ago

Hi,

The reason why both clocks to change is that DAC clock is generated by the ADC clock in the firmware. Please refer the afe7225_phy in the source code. If you change the frequency, idelay may need to change as well.

Thanks,Kyu

C

Customer

said
over 3 years ago

Well Arnaud's post says that AFE7225 gets its clock from CDCE62005. As well he explains:- Start training in the firmware; the firmware will automatically adjust input iDelays and perform Bitslip to align the serial linksBut in the SD111 (FMC30RF star) documentation I see that the ADC clock is an FPGA f/w input while the DAC clock is a f/w output to AFE7225. These are part of the f/w section AFE7225 PHY. But the AFE7225 PHY is not documented or explained. Particularly the operation of IDELAY, its training and how it relates to the ADC clock. I guess the whole point of training was to adjust the IDELAY relative to tho ADC clock. But it does not work. Please provide support for the AFE7225 PHY, IDELAY and its training.

C

Customer

said
over 3 years ago

I would highly appreciate an answer on this.

4DSP Support

said
over 3 years ago

Yes, by using a bit align machine, the training adjusts the IDELAY relative to the ADC clock. Basically, bit align machine compares the test pattern, finds the 1st and 2nd edges and then sets the [font=Verdana]IDELAY t[/font]ap value to the middle. However, this design is optimized for the default frequency that reference design uses. If clock is changed, possibly bit align machine may not set the optimal tap values. You can always change the [font=Verdana]IDELAY t[/font]ap values manually instead of using the training. If you open "fmc30rf_afe7225.cpp" in the reference software, you can disable the training and set the manual [font=Verdana]IDELAY tap values[/font]. For more information on [font=Verdana]IDELAY[/font], please refer Xilinx user guides.