We have big problems on NOR flash booting.
We've designed our custom device with 32bit NOR flash , actually 2×16 NOR configuration on NCS0.
Say 1 NOR device is connected with D0-D15 data bus, and the other one is connected with D16-D31 EBI1 data bus.

We tried to read NOR device ID by using modified Samba applet, but we couldn't access the upper flash device connected to D16-D31 ( EBI1 data bus ).
Say more detail, the value was always 0xffff, and the data bus were not changed in spite of writing on it.

Thus, we doubt that the at91 processor doesn't support 32 bit data bus for NCS0.

nexfield wrote:Say 1 NOR device is connected with D0-D15 data bus, and the other one is connected with D16-D31 EBI1 data bus.

Starting a sentence with "say" indicates a hypothetical situation.
Is your board real or hypothetical?

nexfield wrote:We tried to read NOR device ID by using modified Samba applet, but we couldn't access the upper flash device connected to D16-D31 ( EBI1 data bus ).
Say more detail, the value was always 0xffff, and the data bus were not changed in spite of writing on it.

Thus, we doubt that the at91 processor doesn't support 32 bit data bus for NCS0.

Samba is a network protocol.
Don't you mean SAM-BA?
If that's the extent of testing your hardware, then IMO that's a rash conclusion (which is backwards).

No, I wrote nothing close to that.
Do not conflate booting from a NVM with accessing a NVM.
The default SoC configuration on startup mandates a 16-bit interface for the SMC NVM when used for boot.
If the SMC NVM is not the boot device, then the interface could be 8, 16, or 32 bits.

Yes, according to the datasheet you are wrong.
From the datasheet: "All instructions fetches, regardless of the state of ARM9EJ-S core, are made as 32-bit accesses on the AHB.
If the ARM9EJ-S is in Thumb state, then two instructions can be fetched at a time."