Proceedings Paper

Dynamically Reconfigurable processors are becoming increasingly viable with the advent of modern field- programmable devices. A key feature of dynamically reconfigurable FPGAs is that the logic, and interconnect is time-multiplexed. This enables the implementation of large circuits by partitioning the specification into multiple segments, that execute one after the other on the reconfigurable processor. The available resources can be reused which gives us virtually an infinite pool of resources. In this paper, we introduce a novel technique of temporal partitioning and synthesis of behavioral specification for reconfigurable architectures. We try to optimize the overall latency by performing a trade-off between the total number of partitioned segments, and the latency of each segment. Our approach integrates partitioning and scheduling, and performs design exploration to exploit the trade-off. We also introduce an enhanced Force-Directed List Scheduling algorithm to perform partitioning. We demonstrate the effectiveness of our approach with experimental results.