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Tuesday, April 30, 2013

Here is a view from Mike Bryant of Future Horizons, taken from the Enable450 newsletter, for which, I must thank Malcolm Penn, chairman and CEO.

This is a question often asked by journalists and others not directly involved in 450mm technology, and indeed was one of the questions that formed the basis of the SMART 2010/062 report Future Horizons produced for the European Commission.

It is also a question every new 450mm project has to answer in its funding request to the European Commission, and whilst working on the Bridge450 submission we realised the arguments have become rather unclear over time. The following gives some insight and clarity into the question.

In 1970, Gordon Moore re-formulated predictions on computer storage by Turing and others into a simple statement that the number of transistors per unit area of an IC will double every two years for at least the next ten years. This became known as “Moore’s Law” and apart from the occasional hiccup has in fact been followed for the past forty years. Note that Moore never suggested a doubling in density every eighteen months, this time period coming from a different statement concerning transistor performance.

Of course, doubling the number of transistors would not be that helpful if the price per unit area also doubled. The semiconductor industry has thus strived to maintain the cost of manufacturing per unit area at a constant price, and analysed over time has done a remarkable job in maintaining this number such that the ASP of logic devices has sat at around $9 per square centimetre for this whole period during which the cost of everything else including the equipment, materials and labour used to make the IC have increased, labour costs in particular increasing by a factor of around five times.

The actual cost of processing a wafer appreciates by around 6 percent per annum due to technology cycle upgrades and insertions, for example in the past the replacement of aluminium interconnects with copper or more recently the move to double patterning for lithography of critical layers. Several approaches have been used to maintain a constant area cost, these being:

Improvements in yield - this obviously reduces wastage and vast improvements have been made in this field though yields are now so good that the problem is more maintaining these levels with each new process node rather than improving them further.

Increasing levels of automation - this is still an area undergoing improvement but again we have entered an area of diminishing returns on the investment required.

Introducing larger wafer sizes - this has been performed on an irregular basis over the history of the semiconductor industry. The increase in surface area reduces many but not all of the processing costs whilst material costs tend to stay fairly constant per unit area. Thus, at the 300mm transition, the increase in area by 2.25 times gave a cost per unit area reduction of 30 percent, approximately compensating for the increased processing costs acquired over the 90nm and 65nm nodes.

In addition, larger wafers and better yields allowed larger die sizes, which also reduced the cost of packaging and test, with wafer-scale integration once touted as a solution to reduce costs further at least for large systems. However, in recent years, the average die size has in fact shrunk and it is believed we are now around the optimal die sizes.

As mentioned above, some costs are not inherently reduced by a larger wafer size. Lithography costs are more or less proportional to the total area although small savings are still made as a smaller proportion of time is spent moving onto to the next wafer, whilst tasks such as metrology and CMP also increase somewhat with wafer size.

The result is that the cost of these types of operations grow as a percentage of the total cost of wafer processing and so in a following wafer size transition the savings made are on a smaller percentage of the overall processing cost. Thus, there comes a point where wafer processing costs are dominated by operations not effected by a wafer size increase and so increasing the wafer size becomes uneconomic.

Furthermore, although disputed by some companies, the International Technology Roadmap for Semiconductors (ITRS) has been predicting a slowdown in the rate of the technology cycle defined in Moore’s Law from two years to three years, resulting in a slowing of the increase in functional density per square centimetre.

At the same time the cost of wafer processing is predicted to grow far more rapidly than in the past due to the need to introduce new processes or processing techniques at every node. An interesting slide from ARM below paints a picture of this well. Obviously, it is not the actual new process names in the boxes that count so much as the fact there are so many of them.