New Solution Shortens FinFET Custom Design Tasks From Days To Hours

Synopsys has unveiled a new custom design solution intended to improve the productivity gap arising from an increasing adoption of FinFET-based designs. “The new visually assisted automation technologies will shorten custom design tasks from days to hours, reduce iterations and enable reuse”, according to the company.

FinFET productivity gap is becoming an important issue to solve. FinFETs have complicated series and parallel stacks. With inflexible layout, the cost of mistakes is high and there is a threefold increase in layout effort.

Custom Compiler provides a comprehensive custom design solution based on the industry standard Open Access database. It provides an open environment spanning schematics, simulation analysis and layout. The solution is unified with Synopsys’ circuit simulation, physical verification and digital implementation tools.

Custom Compiler Assistants are productivity aids that leverage the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints.

Custom Compiler is already in use for production work on the most advanced nodes and is supported on FinFET process technologies by leading foundries. Others users include STMicroelectronics and memory developer GSI.