Web-Based Program for Fast FPGA Prototype Delivery

Actel Corporation unveiled its new Online Protoyping Service (OPS), a Web-based sample delivery program. Designed to make it easy to evaluate and prototype with no up-front investment, the new OPS program allows designers to request free samples of Actel-programmed field-programmable gate array (FPGA) devices via a Web interface. The OPS program currently supports Actel's antifuse-based Axcelerator, SX-A, eX and MX families. Actel guarantees 24-hour delivery for North American customers and delivery within 48 to 72 hours for customers in Europe and Asia. Customers interested in receiving programmed samples can provide a completed design file via the Web at http://www.actel.com/OPS .

"By providing free samples via the Internet, this program greatly benefits our customers by drastically reducing their overall hardware and prototype silicon investments," said Saloni Howard-Sarin, director of antifuse and tools marketing at Actel. "With the convenient and easy-to-use OPS program, customers don't have to contact sales or issue a purchase order in order to obtain pre-programmed FPGAs. And with delivery of devices within 24 hours, we're giving our customers a significant head start on their next-generation designs."

Based on a 0.15-micron, seven-layer metal antifuse process, the Axcelerator family, with devices ranging in density from 125,000 to 2-million system gates, delivers over 500 MHz operation and up to 100 percent resource utilization. Built upon the company's AX architecture, Axcelerator FPGAs avoid in-rush current spikes, simplify system power supply design and generally offer lower standby and dynamic power consumption than competing solutions.

The SX-A family features up to 108,000 system gates, or 36,000 application-specific integrated circuit (ASIC) gates, and delivers system performance of up to 250 MHz. The SX-A family offers I/O capabilities that provide full support for hot swapping and is also 66 MHz PCI compliant.

The low-power eX family of devices is optimized for portable applications and is competitively priced compared with complex programmable logic devices (CPLDs), low-density gate array ASICs and two-chip FPGA alternatives.

The MX family, with density ranging from 3,000 to 54,000 system gates, provides performance up to 250 MHz, are live at power-up and require up to five times lower stand-by power consumption than other 5-volt FPGA devices.

Benefits of Actel's Antifuse Devices

Actel's live at power-up, single-chip, antifuse-based Axcelerator, SX-A, eX and MX FPGAs offer benefits that SRAM-based offerings and conventional ASIC solutions are unable to offer, including design security and immunity to firm errors. Nonvolatile antifuse-based FPGAs offer levels of design security beyond conventional SRAM-based FPGAs and ASIC solutions, enabling designers to safeguard against common security problems, including overbuilding, cloning, reverse engineering and anti-tampering. Firm errors, which occur when high-energy neutrons generated in the upper atmosphere strike the configuration cells of SRAM-based FPGAs, can be impossible to prevent. However, because the antifuse configuration cannot be altered once programmed, firm errors are nonexistent with Actel devices.