EDA vendors brace for 90-nm challenge in 2003

SAN JOSE, Calif.  The ramp-up to 90-nanometer chips will give the electronic design automation industry a strong focus in 2003, according to EDA industry executives and observers. Technology users can expect to see this year include design for manufacturability, integrated databases, integrated verification suites, power analysis and system-level design.

But not all efforts will be focused on high-end chip design. FPGA and printed-circuit board designers can expect more-sophisticated tools also, even as prices drop to accommodate tight budgets.

Ninety-nm chips will start moving off the production lines in 2003, vendors say, and supporting tools will be available too. "For the coming year, the focus is on getting 90-nm production ready, and for 60 nm, it's development," said Wally Rhines, chief executive officer of Mentor Graphics Corp. and president of the EDA Consortium.

Among the biggest stumbling blocks to 90-nm and finer linewidths is design for manufacturability, which includes optical-proximity-correction (OPC) and phase-shift technologies as well as increasing attention to yield optimization. "Manufacturability is the issue that has surprised people in terms of difficulty at 130 nm, and they're dreading it at 90 nm," said Ray Bingham, president and CEO of Cadence Design Systems Inc.

Sanjiv Kaul, senior vice president for corporate applications and marketing at Synopsys Inc., said the move to 90 nm also mandates a new approach to verification, because 90 nm "means much faster and bigger chips." In 2003, he said, EDA users will see a move toward unification of design and verification languages, and assertion-based verification will come into widespread use.

Manufacturability and verification challenges will definitely worsen in 2003, said Gary Smith, chief EDA analyst at Gartner Dataquest. Smith said that he's talked to a few design teams that are getting an early start on 65-nm designs, which is "where the wall comes down between manufacturing and design."

As one moves into nanometer design, Smith said, OPC and phase shifting become essential, and it becomes important to model and predict across-the-die variations. One possible solution, he said, is statistical timing analysis.

Even at 90 nm, Smith said, there will be 100-million-gate designs, mandating a shift to system-level design. But, he said, "the tools aren't even close to being there." What's closer and will probably emerge in 2003, Smith said, is the "intelligent testbench," which brings a variety of verification tools and utilities into an integrated environment.

Linking two worlds

While it's unclear what design-for-manufacturability (DFM) tools will emerge this year, what may start to happen is a conceptual shift. "The manufacturing environment isn't fully understood by designers, and the design environment isn't understood by manufacturing people, but the two realms are becoming increasingly interdependent," Cadence's Bingham said.

"We can't expect to hold designers accountable for critical mask and process decisions anytime soon," noted Atul Sharan, senior vice president of worldwide marketing at Numerical Technologies Inc. "There is a huge opportunity in 2003 for a new wave of design-to-silicon specialists who truly understand the pitfalls encountered during the handoff of advanced designs to manufacturing."

What will be key in 2003, Sharan said, is the emergence of "process-smart EDA tools" that don't force designers to become process experts.

Mentor Graphics, said Rhines, will tackle DFM in 2003 by upgrading its physical-verification tools. Design-rule checks are no longer enough, he noted. What's becoming critical are checks for density, OPC and phase shifting, as well as extraction that can handle cross-coupling, Rhines said.

Work on linking design to manufacturing will continue for several years, but one thing that will happen in 2003 is design-tool integration on a single database, Bingham said. Cadence, at least, intends to create such an environment based on the OpenAccess database, which will be released to the engineering community in January 2003.

"A single database addresses cost, performance and capacity, and things happen faster with less support," Bingham said. "You're pushing more results through faster in an era of constrained resources. That's the big 2003 story."

Synopsys hasn't yet revealed its plans for opening its Milkyway database  but it sounds like that may happen quickly. "I think the industry will have open databases," Kaul said. "Synopsys will announce its intentions in January."

Intelligent verification

The two leading EDA vendors, Cadence and Synopsys, also appear to be moving toward the "intelligent testbench" described by Dataquest's Smith. "In each verification area, whether it's system or functional or co-verification or mixed signal, our road map will be pushed along," Bingham said. "What I think will matter is that it will all operate in a single cockpit."

"In 2003, we will start seeing a unification of design and verification languages," Kaul said. "Solutions around SystemVerilog will become real. Tighter integration around simulation, testbench creation, coverage and analysis tools will be production-ready."

There's been a lot of talk about assertion-based verification, but 2003 is the year it will finally become adopted, predicted Scott Sandler, CEO of Novas Software Inc. "We'll see simulation-based engines that make use of assertions, as well as refinements to formal tools," he said. "There will be some powerful applications  but there will be a lot of unfulfilled claims also."

The verification challenge isn't just about functionality or timing. At 130 nm and below, Kaul noted, signal integrity is a "killer," power is more important and leakage power becomes a bigger proportion of power dissipation. One improvement 2003 will bring, Kaul predicted, is better support for dual-threshold voltage designs.

Chip designers can expect to see "a great deal of activity" with respect to power, said Vic Kulkarni, president and CEO of Sequence Design Inc. "The holy grail is a complete, predictable, and automated power flow," he said.

The big story for 2003 will be the emergence of full-chip dynamic and IR drop analysis, said Andrew Yang, CEO of startup Apache Design Solutions Inc. Sang Wang, CEO of Nassda Corp., is thinking along similar lines. This year's challenge, he said, is "full-chip post-layout analysis for timing, power, signal integrity and IR drop effects."

System-level design

Just as designers must take more physical effects into account at 130 nm and below, gate complexity is spiraling out of control. Will 2003 be the year that engineers finally embrace system-level design? Some observers think so.

"The most important trend for 2003 will continue to be the push toward design and verification at higher levels of abstraction," said Jacob Jacobsson, president and CEO of Forte Design Systems Inc. "SystemC and behavioral design will grow to play a significant role in the definition of complex ASICs and SoCs systems-on-chip."

"As soon as SystemC gains momentum in the verification space," said Moshe Guy, president and CEO of Summit Design Inc., "the entire design paradigm will move forward, while HDL, with its important new additions in SystemVerilog, will be focused on block-level hardware implementation."

Jacques Benkoski, president and CEO of Monterey Design Systems, believes that design planning will move to higher levels of abstraction. "Prototyping really caught fire in 2002 and we believe that this trend will continue in 2003," he said. "An exciting area will be the convergence of physical front-end design, where chip designers can perform planning and prototyping in a single integrated environment."

It would be a mistake, some note, to assume that all EDA development efforts will focus on ASIC and SoC design in 2003. Many people won't be doing that kind of design, noted Mentor's Rhines.

"We've reached the point where the typical VC venture capital investment is not going to tolerate $20 million before first silicon," he said. "That's causing things to happen at the low end, where a lot more people are moving to FPGAs." Rhines also said the low-end pc-board market is "very strong."

In 2003, Rhines said, FPGA users will see tools that address performance, power dissipation and embedded-processor functionality. Bernard Aronson, president and CEO of Synplicity Inc., said that 2003 will bring new design and debugging tools for "programmable SoC" devices.

In pc-board design, the differentiation between what were previously "high-end" and "mainstream" tools is disappearing, said Nick Martin, founder and CEO of Altium Ltd. Even low-cost tools will provide improved simulation and signal-integrity features, he said.

Detailed 2003 predictions from 34 EDA vendors can be found at EEdesign.com.