Soldering in a bigger SPI ROM from the same manufacturer with the same specs except for size just works. I used a Winbond W25Q128FVSG and flashed the

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existing coreboot ROM for a 64mbit chip, due to the way the Intel Flash Descriptor works it still boots with a smaller image.

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To actually benefit from the bigger chip you need to modify the Intel Flash Descriptor. There are two changes you need to make:

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1. Change the flash layout to encompass the whole chip.

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2. change the chip density in the descriptor to the new size.

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You can do both with ifdtool, as long as it is recent enough. (I patched it to do 2. in early march 2016)

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For 1. run `ifdtool --layout layout.txt coreboot.rom`, edit the layout file and update it with `ifdtool --newlayout layout.txt coreboot.rom`. You may need to remove the overlap check in ifdtool as somehow that sometimes fails and prevents you from changing the layout. Make sure you run this on an actual image, not just the 4kb descriptor or ifdtool will segfault, as it tries to actually move the sections, not just change the layout in the header. In this case also pad the file to 16MB as we're increasing the size, this is not needed if you change to a smaller chip.

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my layout:

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00000000:00000fff fd

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00500000:00ffffff bios

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00003000:004fffff me

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00001000:00002fff gbe

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00fff000:00000fff pd

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00fff000:00ffffff res1

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00fff000:00ffffff res2

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00fff000:00ffffff res3

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00000000:00a0bfff ec

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if you use a smaller ME than the stock 5MB one you can also reduce the size of the me area:

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00000000:00000fff fd

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00183000:00ffffff bios

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00003000:00182fff me

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00001000:00002fff gbe

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00fff000:00000fff pd

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00fff000:00ffffff res1

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00fff000:00ffffff res2

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00fff000:00ffffff res3

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00000000:00a0bfff ec

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Layout of this file is:

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<start address>:<end address> <section name>

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Start addresses need to end in 000 and end addresses in fff, due to the way the addresses are stored in the IFD. Note that the fd section needs to be at the start. Ignore pd, res[1,2,3] and ec.

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This should result in a coreboot.rom.new file.

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2. Run `ifdtool -D 16 coreboot.rom.new` to change the chip density to 128mbit. You can select a chip using -C but this doesn't matter because if there is no second chip the density is ignored and you cannot set it to 0 in this version of the IFD.

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Soldering in a second SPI chip doesn't just work because lenovo was cheap and left out a few required resistors, if you are up for an adventure you can try soldering them also in, but they are tiny smd ones. Theoretically should work.

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Now you can extract the new IFD (first 4k bytes) from the (probably now broken) coreboot image and

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build a new Image using it.

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Now you can flash it externally as internal flashing doesn't work with an IFD smaller than the chip present. From now on internal flashing should work.

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All of these steps can be done beforehand or on a different computer, but I did it in this order because I only got that one laptop and a raspberry pi for external flashing.

I recommend using SOIC clip, you can find a decent one from Pomona online. Depending on the flasher you use, you may have to use separate
3.3V source. Make sure not to feed more than 3.3V to the chip. You can use any device such as
Raspberry Pi, BeagleBoard or Buspirate -- the latter being the slowest. For how to wire up the
clip, see this guide (just for the setup). Then connect the clip to the chip, aligning it with the diagram above.

Read the flash. Twice. Compare the files to be sure. Save a copy of it on external media.

Bigger SPI ROM

Soldering in a bigger SPI ROM from the same manufacturer with the same specs except for size just works. I used a Winbond W25Q128FVSG and flashed the
existing coreboot ROM for a 64mbit chip, due to the way the Intel Flash Descriptor works it still boots with a smaller image.

To actually benefit from the bigger chip you need to modify the Intel Flash Descriptor. There are two changes you need to make:

1. Change the flash layout to encompass the whole chip.

2. change the chip density in the descriptor to the new size.

You can do both with ifdtool, as long as it is recent enough. (I patched it to do 2. in early march 2016)

For 1. run `ifdtool --layout layout.txt coreboot.rom`, edit the layout file and update it with `ifdtool --newlayout layout.txt coreboot.rom`. You may need to remove the overlap check in ifdtool as somehow that sometimes fails and prevents you from changing the layout. Make sure you run this on an actual image, not just the 4kb descriptor or ifdtool will segfault, as it tries to actually move the sections, not just change the layout in the header. In this case also pad the file to 16MB as we're increasing the size, this is not needed if you change to a smaller chip.

Start addresses need to end in 000 and end addresses in fff, due to the way the addresses are stored in the IFD. Note that the fd section needs to be at the start. Ignore pd, res[1,2,3] and ec.

This should result in a coreboot.rom.new file.

2. Run `ifdtool -D 16 coreboot.rom.new` to change the chip density to 128mbit. You can select a chip using -C but this doesn't matter because if there is no second chip the density is ignored and you cannot set it to 0 in this version of the IFD.

Soldering in a second SPI chip doesn't just work because lenovo was cheap and left out a few required resistors, if you are up for an adventure you can try soldering them also in, but they are tiny smd ones. Theoretically should work.

Now you can extract the new IFD (first 4k bytes) from the (probably now broken) coreboot image and
build a new Image using it.

Now you can flash it externally as internal flashing doesn't work with an IFD smaller than the chip present. From now on internal flashing should work.

All of these steps can be done beforehand or on a different computer, but I did it in this order because I only got that one laptop and a raspberry pi for external flashing.