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4. If it is possible, probe the link on the boardto see if there is any activity whena packet is trasmitted from the MAC.

5. Try loopback in the switch if it allows to do so.

6.Probe with Chipscope Pro at the TX and RX side of the GTP/GTX interface. Activity at the TX side will indicate whether a packet made it to GTP/GTX or not. Activity at the RX side will indicate the packet indeed arrived in the FPGA, from the link partner. If there is some activity at the receive side, then probe MAC signals such as good frame and bad frame signals.

7. Make sure the timing in the design is met.

8. Modify the GTP/GTX parameter to test with different values of RXEQMIX, TXPREEMPHASIS and TXDIFFCTRL. 9. If this is a custom board, try with a Xilinx Demo Board if available.

10. Try connecting with a different link partner if possible.

If the above doesn't resolve the problem, open a webcase with Xilinx Technical Support. Also, check with the ethernet switch vendor to make sure the switch configurationhas been done correctly or not.