Delivering the next generation of chips is getting harder, but announcements at this week's International Electron Devices Meeting (IEDM) show that the chip makers are making real progress in creating what they term 7nm processes. While the node numbers are perhaps less significant than they once were, it shows that while Moore's Law may have slowed, it is still alive, with major improvements coming on the current generation of 14nm and 16nm chips. In particular, at this week's conference, representatives of the big foundries (companies that make chips for other companies)—TSMC and the alliance of Samsung, IBM, and GlobalFoundries—announced their plans for making 7nm chips.

TSMC (Taiwan Semiconductor Manufacturing Company), the world's largest foundry, announced a 7nm process that it said would enable 0.43 times die-sizing scaling compared with the current 16nm process, allowing for much smaller dies with the same number of transistors or the ability to put a lot more transistors into a die of the same size. Most importantly, the company said this provides either a 35-40 percent speed gain or a 65 percent power reduction. (Note those figures apply to the transistors themselves; it's not likely you'd see that much power or speed improvement in a finished chip.)

Most impressively, the company said it was already manufacturing a fully-functional 256 Mbit SRAM test chip, with pretty good yields. On the chip, the cell size of the smallest high-density SRAM is just 0.027 µm2 (square microns), making it the smallest SRAM yet. This indicates that the process works, and TSMC said it is working with customers to get their 7nm chips to market as soon as possible. The foundry will start 10nm production this quarter, with chips set to ship early next year. The 7nm generation is slated to start production in early 2018.

Meanwhile, the Albany Nanotechnology Center (consisting of researchers from IBM, GlobalFoundries, and Samsung) discussed its proposals for a 7nm chip that it claimed had the tightest pitch ( between different elements of the transistors) of any process yet announced.

The alliance said its 7nm process would produce the tightest pitches ever, as well as offer a substantial improvement over the 10nm process it unveiled a couple of years ago. Those are now ramping up production at Samsung, with chips to be widely available early next year. (GlobalFoundries has said it will skip 10nm and go directly to 7nm.) It has also said that the new process could enable a 35 to 40 percent performance improvement.

The alliance's process has a number of big differences from TSMC's, and from previous nodes. Most notably, it relies on Extreme Ultraviolet Lithography (EUV) in multiple critical levels of the chip, while TSMC is using the 193nm immersion lithography tools that have been in use for generations, albeit with more multi-patterning. (Multi-patterning means using the tools multiple times on the same layer, which adds time and increases defects; the group suggested that using conventional lithography on this design would require up to four separate lithography exposures on some critical layers of the chip.) As a result, such chips are unlikely to be produced until 2018-2019 at the earliest, because the EUV tools are unlikely to have the necessary throughput and reliability until then.

In addition, it uses new high-mobility materials and strain techniques within the silicon to help improve performance.

In both the TSMC and alliance designs, the basic underlying cell structure for the transistor hasn't changed. They still use FinFET transistors and a high-K/metal gate—the big defining characteristics of the last process node.

Because of delays, Intel recently introduced generation of its 14nm chips, known as Lake, and now plans to follow that up with both a 10nm low-power mobile design called Cannonlake due out at the end of next year and yet another 14nm desktop design known as Coffee Lake. Intel has not yet disclosed many details of its 10nm process other than to say that it expects better transistor scaling than it has historically been able to achieve and that it will use conventional lithography.

One thing to note: in all of these cases, the node numbers, such as 7nm, no longer have any real relationship to any physical feature in the chips. Indeed, most observers think TSMC's current 16nm node and Samsung's current 14nm node are just a bit denser than Intel's 22nm node, which started high volume production in and are notably less dense than Intel's 14nm node, which started shipping in volume in early 2015. Most predictions say that the upcoming 10nm nodes that TSMC and Samsung are talking about will be just a bit better than Intel's 14nm production—with Intel likely to regain the lead with its own 10nm node.

Of course, we won't really know how well any of these processes work and what kind of performance and cost we'll get until actual chips start shipping. It should make 2017 and interesting years for the chip makers.

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