Product Description

ONetSwitch30 is an All Programmable open networking innovation platform.

ONetSwitch30 is based on the Xilinx Zynq-7000 SoC, and mainly adopts the Gigabit ports. It can achieve a comprehensive experiment platform integrating calculations, storage, networks and interconnection by extension. Both its software and hardware can realize custom programming. Its reference designs are abundant and flexible, can be used to various researches on the evolution of network prototypes, and the development of customized network products. Especially, the features of the miniaturization and low power are adapted to the multi-node network tests and deployments.

Features

General

Main Silicon XC7Z030-2SBG485

Power Supply DC 12V

Primary Config. TF card

Auxiliary Config. QSPI flash/JTAG

Processing System

Processor _Dual ARM Cortex-A9@800MHz_

Cache (L1)32KB Inst. + 32KB Data per core; (L2)512KB; (OCM)256KB

DRAM DDR3 1GBytes

Flash Quad SPI flash 256Mb

DMA 8 channel (4 for Programmable Logic)

Ethernet 1x GE RJ45

Peripherals USB / USB-UART / USB JTAG / TF card

Programmable Logic

FPGA Logic 125K LCs, Kintex-7, ~1.9M ASIC gates

Host I/F AMBA AXI4 interconnect, max 100Gbps between PS-PL

DRAM DDR3 2GBytes

Ethernet 4x GE RJ45

Peripherals 2x PMOD

User IO user LEDs/push buttons/DIP switch

Extension mini PCIe for wireless NIC or SSD

Block Diagram

Board Layout

Specification

workflow

Overview

A bottom-up approach is recommended when developing on the Xilinx Zynq SoC-based ONetSwitch.The figure below from Xilinx Wiki shows a high level block diagram of the Xilinx design flow for Zynq AP SoC.

For any layer or component in this hierarchy, you can either download the pre-built images for quick use, or modify then generate it by yourself in the way described below.

Get Prepared

Prepare the Boot Medium

Xilinx Zynq SoC offers different types for system booting, on your demand.Here in the GitHub for an ONetSwitch, the SD boot is chosen as default. An FAT partition in the size of 512MB is used for storing the boot and kernel images, while an EXT partition typically larger than 1GB is for the root file system and the applications(e.g. OpenFlow switch software).For the detailed how-to, please refer to Xilinx Wiki Prepare Boot Medium.

Setup a Serial Console

It is a must to use the USB-UART when running an interactive program on the platform or debugging. Here's a helpful link on Xilinx Wiki Setup a Serial Console.

Get a Linux Environment

Software development on ONetSwitch requires a Linux environment for easy cross compilation.Ubuntu 12.04 LTS x86_64 may lack some needed 32-bit libraries. This can be fixed by installing ia32-libs.Ubuntu 14.04 LTS x86_64 may also lack some needed 32-bit libraries. This can be fixed by installing libc6-i386.

Install Xilinx Tools

Xilinx Vivado and SDK must be installed for ONetSwitch development. DownloadNotice that, by 2014 Q4, all our projects are developed with Vivado 2013.4.When working in a Linux environment, especially for software developers, remember to setup the environment variables for cross compiler and the Vivado/SDK tools.

Use Pre-Built Images

This repo stores the common FSBL, SSBL(u-boot), Linux kernel(uImage) and root file system(rootfs), as well as the SDN/OpenFlow executables. It is easy to find them in the repo according to the folder and file names.The boot loaders are board-dedicated, while the kernel image and the rootfs are applicable to all ONetSwitch boards.

ready-to-download

This is a sub-folder associated with each project, usually contains the FPGA image(system.bit) and the project-specific devicetree blob(devicetree.dtb).The boot.bin, which is created by Xilinx SDK, always consists of the common FSBL and u-boot from common-bin above, and the project-specific system.bit.

An example here to prepare for an OpenFlow software switch (ofs-sw) on ONetSwitch30 using pre-built images.You need to collect following items and make copies of them to the FAT partition.

You need also to extract the compressed rootfs to the EXT partition and then put the application images to somewhere in the extracted folder structure.In this example, some runtime libs are required so the sw-lib is copied as well.

Notice that, all the boot.bin are prepared to start the kernel in the EXT partition, using the pre-built u-boot with suffix -ext.elf in its file name. If you want to simply run all in an FAT partition, rootfs as uramdisk and the u-boot with suffix -ram.elf. The FPGA image should be used in the boot.bin regeneration.

The process needs Xilinx SDK, and working environment in Linux with cross compiler installed. See more information in our Software Design Guide.

Application Design

The applications, often the final target what we want, run on top of the OS (Linux as we mentioned above, or any others from 'bare-metal' to Android.)For SDN/OpenFlow application, we have done following and hope to get more from you.

Integrate and Test

Prepare the Boot Image

The boot image, boot.bin, is created in Xilinx SDK, by assembling the FSBL, the FPGA image, and the SSBL in sequence.1. Select 'Xilinx Tools' from the SDK menu2. Choose 'Create Zynq Boot Image', a pop-up appears3. Add fsbl.elf, system.bit, u-boot.elf sequentially4. Click 'Create Image' and wait for the generation5. Rename the output binary to boot.bin

Use the Test Sequence

Project-specific test sequence is provided as a demo. It mainly shows the usage of the board and the features of the application.Try the test sequence and check the results.

Prepare Boot Medium

Input Files Required

Output Files Produced

bootable SD card

Task Description

The following instructions are taken from the OMAPPedia wiki.

The following instructions assume a Linux system. Furthermore, most commands require root permissions. After completing this steps the SD card holds two partitions which can be read/written under Linux. Windows can - if at all - only access the FAT partition; but even this seems to depend on the card reader/driver used.

Insert SD card and figure out the corresponding device. The last lines of the dmesg output should tell you under which device file the inserted SD card is available in the system. dmesg

Warning: The following commands will use '/dev/sdX' to refer to the SD card device. Replace this with the actual device on your system. Executing the following commands on the wrong device may corrupt your data on other file systems. Also, all data on your SD card will be destroyed.

The fdisk utility does not seem to erase the first few bytes of the first sector in the card when the partition table is saved. Use dd to erase the first sector.

Ref:

Setup a Serial Console

This guide will explain where and how to install the USB drivers and how to install and configure a terminal emulator which allows talking to the board.

Downloading and installing USB to UART drivers

When using a Xilinx Development Board with a USB UART port use your mini-B USB cable to connect the USB UART port on the board to a PC. If the driver for this CP210x USB to UART bridge is recognized by your PC you may go to the next section, suggested HyperTerminal. If your USB to UART is not automatically recognized, the diver can be found and downloaded from the Silicon Labs website linked below.

Configuring Putty (Windows)

Open your putty

Once open, select the option of Serial connection

Then select Select Serial in the Category section. inlkbuthgrxfthcygukgyftrgetrxychtgyjhbkblknm;l.png

To set the "Serial line to connect to" you must open the device manager to see which COM your board is connected. To open you device manager go to Start -> (type in search) Device Manager Go to the "Ports (COM & LPT)" section and look what COM your Silicon Labs USB to UART bridge is connected to

Write in the correct COM that your board is connected to.

Baud, section specific to the board, thus check the Getting started guide for the board that you have to get the correct baud rate.

Configuring minicom (Linux)

Minicom should be started with the -D <serial device> command line switch e.g. minicom -D /dev/ttyUSB0 In minicom hit ctrl+a z, to get the help up. Navigate to options->serial port setup and configure the line according to your target platform.

Xilinx Vivado Tools

Output Files Produced * Installation of Xilinx tools on user's local computer

Task Description

The complete hardware/software work flow for Xilinx devices relies on a number of Xilinx-provided tools. These tools are available as download for Linux and Windows based systems. Please, follow the installer to install the tools on your system. Note that the Xilinx SDK tools must also be installed for embedded linux applications.

Platform specific hints & tips

Ubuntu 12.04 LTS x86_64 users may run into issues related to missing dependencies when installing the Xilinx tools. This release of Ubuntu lacks some needed 32-bit libraries which need to be installed. This can be done by executing: bash$ sudo apt-get install ia32-libs

Setting Up the Tools

Many software items, such as Linux, use the environment variable CROSS_COMPILE, to invoke the cross compiler that is used to build it (SDK must be installed). Also the PATH environment variable has to be extended to find the newly installed tools.

Ref:

Quick Start

Intro

An ONetSwitch enables users in different development roles to build a complete networking system in a single node. Users can build the embedded system either from scratch, or based on some pre-built images.In either way, getting-started projects would help you * to get acquainted with the board and its components

Project to verify the calibration and read/write operations on PL DDR3 SDRAM.

The table below shows the applicability.

Reference Design

Intro

An ONetSwitch dedicates to networking applications, as what the product name implies. The 'All-Programmable' allows the users to get any of their inspiration realized by customizing the gateware and/or the software.Reference designs here would help you * to comprehend the usage of board components in different cases

to avoid developing from scratch, especially for beginners * to share your mind and contribute to our community

Hardware Design

Intro

The design for ONetSwitch hardware, i.e. the FPGA part as Programmable Logic, commonly follows a Xilinx Vivado flow.Here we provide a reference tcl script and folder structure, which show a guideline to manage the project generation and organization in Vivado, with IP package and block design integration.All of our Getting-Started projects and reference designs are organized in this way.

Tcl Script

Project Root

The folder is assigned as the ROOT, when it originally contains following * myproj (folder) stores all the design sources and tcl.

myproj.tcl (script) to generate the project.

IP Designs

All the design sources of user IPs are listed in the folder ROOT/myproj/ip.The IPs should be managed in each subfolder, e.g.,ROOT/myproj/ip/my_ip_0, ROOT/myproj/ip/my_ip_1, ... ROOT/myproj/ip/my_ip_n

In each IP folder, e.g., ROOT/myproj/ip/my_ip_n, contains typically

src (folder) contains all design sources - hdl, netlist..

my_ip_n.tcl (script) to package single IP to a zip for an IP-repository.

To generate or modify my_ip_n.tcl, please follow the Vivado IP flow.

IP Repository

The script myproj.tcl fetches the ip_list and then sources all the my_ip_n.tcl, storing the zip in a newly created folder ip-repo in the ROOT.The ip-repo is a runtime folder for IP generation and package.

Modify the ip_list variable in "myproj.tcl" to add IPs to your block design.

Block Design

Only one block design can be supported in this tcl script.The system block design can be created by sourcing ROOT/myproj/bd/myproj_bd.tclThe myproj.tcl automatically generates the wrapper for the block design.

The myproj_bd.tcl can be generated by running write_bd_tcl after a complete block design in Vivado. Please follow Vivado tcl scripting guide for details.

Sources and Constraints

Common hdl, netlist and constraint files can be stored and organized in ROOT/myproj/sources and ROOT/myproj/constrsHierarchical folder structure is allowed.

Simply modify the source_files and constr_files variables in myproj.tcl to add these sources to your design.

Project Generation

In the Vivado tcl shell, change directory to the ROOT and simply source the tcl. e.g.,

cd ROOT
source myproj.tcl

The tcl collects all IPs, blockdesign(s), common hdl/netlist/constraints and then generates the project.Synthesis and implementation flows can be added after that.

Project Cleanup

Build FSBL

An FSBL can be generated within the template in SDK, based on the exported hardware description from Vivado system design.We have done some patches to the template (for ONS30), and added functions to program the clock generator during the boot stage (for ONS30 and ONS45). So it is recommended to make use of the pre-built FSBLs directly instead of regenerating, unless the following PS clock settings doesn't meet your design. Below is a typical settings for PS Clocks configured during FSBL stage.Find the pre-built FSBL images for different boards here.Find the details of FSBL changes comparing to the official version here.

Build SSBL (u-boot)

This step must be done in a Linux environment.Download our official u-boot repo, and refer to the Xilinx Wiki Build U-Boot for u-boot image generation.To build u-boot for ONetSwitch execute

Build and Modify Rootfs

For uramdisk.image.gz, you have to put it directly in the FAT partition and use it together with u-boot-ons*-ram.elf.For rootfs_ext4.tar.gz, you need to extract and copy to the EXT partition with sudoer privilege, use with u-boot-ons*-ext.elf.

Build Device Tree Blob

The Xilinx Wiki Build Device Tree Blob provides two ways to create an original .dts.Changes has been done on the original tcl-generated .dts when the ONetSwitch and certain applications require more device/driver supporting. The recommended way is to take ours as the baseline, use or make changes on our modified .dts, and finally generate the .dtb using the Linux device tree complier.