Tuesday, May 16, 2017

Job Description: You will be responsible for developing a tool framework to breakdown and manage the power consumption of the Power Management ICs across all projects. The so-called power KPIs Key Performance Indicator are indeed strategic data critical for the competitiveness of battery powered system likes mobiles phones, wearables, IoT devices. You will be part of an enthusiastic and international system engineering team located in Munich and will get in touch locally with several design and validation teams.

Your main tasks in this full time position will be to:- Setup a new framework to manage the power data in a new tool and environment- Migrate existing project power consumption specifications and measurements currently in Excel- Measure and correlate power KPIs on engineering samples in the post-silicon lab.- Validate current power modelling approach and propose further model optimizations- Contribute to the reporting and documentation for other teams and management

Synopsis: This document provides guidelines for creating computational device models that work well in simulation. We build our discussion around the mathematical notion of “well-posedness”. We show that the requirements for a model to be well-posed stem from the internal working mechanisms of simulators. Therefore, our main aim is to provide insight into the numerical procedures used by simulators in order to help model developers avoid ill-posedness issues. We start our discussion with an example that shows how an ill-posed Verilog-A model can produce different simulation results in different simulators. We then provide a step-by-step simulation case study. In this case study, we illustrate the role of device models in simulations by examining the steps a simulator goes through, from taking a netlist as input to producing a simulation result as output. Finally, we distill our discussion in a functional definition of a well-posed model. As an extension to our theoretical discussion, we also provide practical guidelines that should be followed by Verilog-A models in order to avoid ill-posedness issues.

This document is published as a part of the Nano-Engineered Electronic Device Simulation (NEEDS) initiative. NEEDS is an NSF-funded initiative whose charter includes the development of tools and techniques for the production of high-quality device models1:

“NEEDS has a vision for a new era of electronics that couples the power of billion-transistor CMOS technology with the new capabilities of emerging nano-devices and a charter to create high-quality models and a complete development environment that enables a community of compact model developers.