With the current focus on IC processing challenges at sub-20nm device length scales, interest in micron-scale wafer processing seems to be out of the limelight. However, in the world of MEMS, micron-scale processing is dominant for high-volume components such as gyroscopes and accelerometers. In a typical MEMS process flow, tens of microns of silicon are etched to release structural features that are a few microns wide. And while those in IC process integration may think that MEMS processing should be simpler than for leading-edge ICs, the increasing complexity and customization in MEMS designs raise a different set of processing issues, which demand further understanding for successful device manufacturing.

Drive capacitors and proof mass based on [1] illustrate a variety of structures in a typical MEMS gyroscope.

Without the Manhattan-rule restrictions of the CMOS world, MEMS layouts often result in non-rectilinear shapes such as triangular release holes, curved comb fingers, and non-perpendicular corners, all structures infrequently seen in IC layouts. These structures are often manufactured by etching through 10-100um silicon using deep reactive ion etching (DRIE) to form high-aspect ratio holes and trenches, using Bosch or other time-multiplexed process schemes. A variety of MEMS packaging schemes such as TSV integration and wafer bonding before or after the devices are released, introduce further challenges to the process flows.

Examples of different polymerization and lateral/vertical etch rates during DRIE, resulting in (a) some mask undercut and (b) V-shaped profile.

In particular, a good understanding of DRIE ensures that the device can be successfully released and function as designed. For example, significant etch undercut under the masking material can be caused by thin sidewall polymer and high lateral etch rates, resulting in smaller features than expected. In contrast, a thicker sidewall polymer and low lateral etch rate can result in a V-shaped profile. The combination of polymer thickness and lateral and vertical etch rates can be explored to understand the process window and ensure that mask undercut is minimized or within a given tolerance.

At a MEMS manufacturer, these lessons are typically learned with costly and time-consuming iterative silicon experimentation. Many MEMS producers have now gone fabless, further obscuring the understanding of design-process interactions. In either manufacturing or fabless development, new virtual fabrication software tools such as Coventor’s SEMulator3D allow different processes and integration schemes to be evaluated during the design phase. This capability can provide detailed understanding of existing and potential fabrication issues during the manufacturing phase.