In order to build the high performance CMOS circuits certain electrical design rules are taken into account. These rules are used to develop the mathematical model of the physical phenomenon occurring in the circuits.

As the current CMOS fabrication processes are improved and the device dimensions are shrinking these design rules will change.

Hence as the device dimensions are changing the electrical parameters of the devices are also has to be scaled accordingly to apply the previously developed models to the current modern devices and circuits.

In scaling of the MOS devices the characteristics of the device are maintained and the basic operational characteristics are preserved by introducing a dimensionless factor . Efforts are under way to make transistors as small as possible to increase speed and circuit complexity per unit of chip area.

For this purpose, we have to adjust a fabrication process and the bias voltage to allow proper operation of reduced size devices. The adjustments aim at achieving small dimension, at the same time, avoiding several side effects, such as the smaller dimension effects. Such a shrinking of device without side effects is called as scaling.

Advantages of Scaling :

The reduction in lateral dimensions of the MOSFET and interconnects size is known as ‘scaling’ of the geometric dimensions of the MOSFET.

The advantages of Scaling are as follows,
(1) Improved current driving capability improves the device characteristics.
(2) Due to small geometries the capacitance reduces.
(3) Improved interconnect technology reduces the RC delay.
(4) The multiple threshold devices due to scaling adjusts the active and stand by power trade-offs.
(5) The integration density improves due to single chip devices.
(6) Enhanced performance in terms of speed and power consumption.
(7) Cost of a chip decreases by twice.

Disadvantages of Scaling :
1) The power consumption per unit area increases as devices are scaled down. That means scaled devices run increasingly hot. This is a severe performance limitation for scaled devices.
2) The scaling leads to mistakes of having scale proportionally to zero dimension or to zero threshold voltages.
3) Since scaling reduces the carrier mobility, gain of the device reduces.
4) Due to reduction in conductor size, the current handling capacity of the device reduce. To solve this addition metal layers are necessary for more densely packed structure.
5) As the packing density per chip increases, due to higher power density, the device becomes very hot and needs forced cooling at the additional cost.
6) Higher fields also cause hot electron and oxide reliability problems.

FaceBook

Likes

Additonal Information

electronics-tutorial.net

This is an initiatory website for a simplified information about basics of electronics for beginners and advanced professionals..
Online tutorials designed are mainly intended to understand the basic concepts of electronics engineering. While using this site, you agree to have read and accepted our terms of use and privacy policy.