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Hi @Blake,
I was struggling with the same problem.
In Adam's project is mistake which result is an FMC-HDMI module is not recognizable by other devices.
The reason for that is not sending EDID at all.
The cause of this situation is wrong initialized EDID map.
In Adams example EDID is initialized by:
but the correct way is:
the body of iic_write2 is from LK example:
By the way, in LucasKandle example initialization is done in same way as in Adam's example so is the reason why it not worked in your case.
I hope it will helps. If you want I will post my working code for a ZedBoard with FMC-HDMI when I clean it because at the moment is kind of messy.

It seems to me the AXI Quad SPI block is sending address + data. Looking at the .xci file again, I see C_SPI_MEM_ADDR_BITS set to 24 bits. So 24 bits of address and 16 bits of data would yield 40 bits.

Hi @neocsc,
Here is a verified Nexys Video HDMI project updated from Vivado 2016.4 to Vivado 2017.4. You should be able to find the updated project in the proj folder . Here is a GitHub project done in HDL using the clocking wizard, DVI2RGB and RGB2DVI IP Cores for another FPGA. Here is a unverified Nexys Video Vivado 2017.4 HDMI pass through project made from the linked Github project. In the next few days I should have the bandwidth to verify this project.
thank you,
Jon

The warning you pasted is benign and simply means there are no ILAs present in your design.
The real issue could be your clock. You should review the datasheet for the dvi2rgb.Table 1 in section 5 specifies RefClk is supposed to be 200Mhz. Also, your constraint should follow the recommendation in section 6.1 for a 720p design.
Finally, @elodg gives some great troubleshooting information in this thread.

Hi @D@n,
I believe the new part that is used in the Arty A7 boards (and other A7 boards) is now a Spansion S25FL128SAGMF100; based on old schematics, I believe this was added in Rev D of the Arty A7 (dated August 2017), though I do not know when that particular Rev was then released (or if it even was released) to the public. I confirmed that the Arty S7 also uses this part and I wouldn't be surprised if most of our other Artix 7 based boards use it now as well.
I've requested that the chip name and images are updated in any appropriate tutorials and requested that the pdf version of the reference manual (updated wiki) is updated as well.
Thanks,
JColvin

@hamster I was able to run your AXI Slave interface. It works great!
It is now very easy to exchange information between PS and PL, and it even supports execute-in-place (e.g. I can put ARM instructions to register file and run PS CPU directly from it).
I have some questions about your AXI Slave design:
1) AXI_a*size has no effect on INCR type of burst transactions, but according to AXI protocol: the increment value depends on the size of the transfer. You set it only for WRAP type, is it correct? Thus, burst size is always 0 for INCR type?
2) Do you know how PS initiates INCR burst type? A kind of memset/memcpy need to be used for that or an incrementing pointer will also work?
3) Where WRAP type is necessary? How to use PS to work in WRAP mode?
You may also update your wiki page with following:
0) Create provided VHDL files
1) Create a block-diagram and add PS IP core to it
2) Apply configuration provided by your board's pre-settings; this will set all necessary initialization settings for PS (e.g. clock frequencies, DDR bindings, etc.)
3) Press auto-configure (or how it's called) ==> this will connect PS IP to DDR and to fixed IO
4) Add "External ports" to the diagram (create new AXI_CLK and AXI external ports) and connect them to PS ports
5) Generate VHDL wrapping code for this block diagram
6) Put generated system under axi_test_top by renaming it to axi_test_wrapper (default name is design_#_wrapper in my Vivado version)
7) This will auto-connect block-diagram external ports with axi_test_top
8 ) Add constrains file and rename/uncomment external ports where necessary
9) Generate bitstream
10) File->Export->Hardware and create .hwf file which contains PS configuration
11) Open Xilinx SDK and create a new project: select .hwf file as Hardware BSP for this project
12) Now, Xilinx SDK will auto-generate few .c and .h files which contain necessary PS initialization ==> clocks, IRQs, DDR, etc.
13) Add hello_world.c application to the project
@hamster Thank you very much. I've learned a bunch of new things thanks to your help!

Hi @m72
The preview is further fixed. I hope there are no more issues with this: https://forum.digilentinc.com/topic/8908-waveforms-beta-download/
Here you have the project: EMU_2CH_EACH_V10 (2).dwf3work

Actually, I'm not sure what Diglent's policy is about questions that aren't specific to Xilinx or Digilent products. The various FPGA vendors are certainly competitors but I have a hard time seeing non-commercial customers as 'competitors' regardless of which vendors' products they are using.
I would agree that, even though some of the people who respond to questions posted to Digilent's Forum have recent experience with a variety of FPGA vendor's devices and tools, posting questions to a website dedicated to Xilinx based products when your question is specific to Intel is a good way to get bad information and probably unwise. Also, and this hasn't happened yet, I suspect that having a lot of questions about non-Xilinx devices and tools would be confusing to a lot of readers and make the experience for many of them of reading posts to Digilent's forum less useful.
Intel has a community forum as does Xilinx. Neither is, in my experience, as helpful as Digilent's most of the time. Intel is, well not Altera, and even Altera's community support wasn't that great. Digilent's Forum is a great place to ask about Digilent products and Xilinx tools. Even restricted to that it' must be hard for people to find answers that have already been posted because a a lot of questions keep getting repeated.
I do heartily suggest that it would be more appropriate to seek out answers to questions like saif1's at forums where people who hang out there are very knowledgeable about the tools and devices for the platform that you are working on. There also must be vendor agnostic forums out there somewhere dealing with FPGA development tools and devices.
My last word is that an awful lot of questions would be answered if the poster only took the time to read through the vendors' literature. If there's any practice that's bad form it's wasting other peoples time because you can't be bothered or don't have the time to read readily available literature. Everyone's time is as important to them as yours is to you.

Hi,
I just have opened a new terminal and launch minicom through the new terminal which works the same way as SDK terminal but I have to close the SDK terminal before connecting to minicom. Thanks @D@n and @jpeyron

Hi @lwew96,
We have not used a reconstruction filter. I did find a paper that discusses a reconstruction filter with the AD5541 here. Hopefully one of the more experienced community members will have some input for you as well.
best regards,
Jon

Thanks @OvidiuD,
I'll take one step after another and the forums are quite a good source of knowledge.
So far, I plan to start with very basic schemes in order to understand how Vivado works.
Then I will work on communicating with the Axoloti through SPI.
Best regards

@Ahmed Alfadhel,
You have a couple of options available to you:
It's not clear, from your pictures above, whether or not the -40dB stop band was achieved. Some amount of noise is to be expected due to truncation errors, etc. Without seeing an estimated PSD, I can't tell. It may be that it's doing exactly what you required of it.
-40dB is only so good. With more taps, you should be able to go deeper. How deep depends upon your requirements. How good do you want the signal to look?
You may also need to provide more bits to both your signal and coefficient values in order to do better.
You did prescale your coefficients so that, when rounded to integers, the taps were useful, right?
Also, be aware, the filter will be specified for full scale. You'll want to measure it against a full scale input. Anything less will introduce additional truncation error. This is one of those reasons why the dynamic range (i.e. number of bits) of the input and output signals are so important.
Enjoy!
Dan

Hi @ahmedengr.bilal,
Like I mentioned in the previous post there is no HDMI output from the Linux side, neither the embedded rootFS provided by petalinux nor the kernel configuration we give out is set to accommodate this feature.
Regarding the missing media-ctl and v4l2-ctl, you have not activated the v4l-utils in the rootfs configuration of the petalinux. to do this you need to navigate to your petalinux project folder and run:
petalinux-config -c rootfs
Once the menu appears you need to go to Filesystem Packages->misc->v4l-utils and activate: v4l-utils, libv4l, media-ctl. Rebuild the whole project and it should be working now.
-Ciprian

Hi @YellowYoung,
Welcome to the Digilent forums!
The PmodCAN facilitates CAN communication to another device through the PL.The PmodCAN uses SPI communication to communicate between the host board and itself. It would not be able to connect to the CAN on the PS.
To use the CAN bus on the PS you would need to use the MIO Pmod JE1 as discussed in the user guide for the Zedboard here in section 2.9.2 Digilent Pmod Compatible Headers (2x6). The user guide states the bank that the MIO pins are connected to a 3.3V bank so you would need to make a level shifting circuit for CAN communication to work since CAN uses voltage level as part of its communication.
If all you need to do is communicate data from the Zedboard using CAN communication. Then you can send data from the PS to the PL and then send that data through the PmodCAN. Here is an Avnet forum thread that discusses sending data from the PS to the PL. Here is a Xilinx forum thread that initially discusses how they accomplished sending data from the PS to the PL.
best regards,
Jon

The example I posted would work for Linux or Mac with "common" tools installed. As to Windows... can't really help much there.
git's not part of Python, it's used for managing code; you can achieve the same end result here by downloading the ZIP from https://github.com/bdlow/dlog-utils-portable/archive/master.zip and unzipping to a folder.
Virtual environment support is a standard part of Python 3; you can skip that if you like but without virtual environments eventually your Python installation will end up like this: https://xkcd.com/1987/
Ah, of course, in Windows `activate` is a batch script not a shell script: https://www.techcoil.com/blog/how-to-create-a-python-3-virtual-environment-in-windows-10/

Hi,
as I may not have time for FPGA work for a while - just started in a fascinating new role related to high-speed digital diaper changing - I decided to post this now.
Here's the Github repo (MIT-licensed)
The project provides a very fast (compared to UART) interface via the ubiquitous FTDI chip to a Xilinx FPGA via JTAG. Most importantly, it achieves 125 us response time (roundtrip latency), which is e.g. 20..1000x faster than a USB sound card.
It also reaches significantly higher throughput than a UART, since it is based on the MPSSE mode of the FTDI chip.
Finally, it comes with a built-in bitstream uploader, which may be useful on its own.
I implemented only the JTAG state transitions that I need but in principle this can be easily copy-/pasted for custom JTAG interfacing.
So what do you get:
On the software side an API (C#) that bundles transactions, e.g. scattered reads and writes, executes them in bulk and returns readback data
On the RTL side a very basic 32 bit bus-style interface that outputs the write data and accepts readback data, which must be provided in time. See the caveats.
In general, a significant increase in complexity over a UART. The performance comes at a price. In other words, if a UART will do the job for you, DO NOT use this project.
For more info, please see the repo's readme file.
For CMOD A7-35, it should build right out-of-the-box. For smaller FPGAs, comment out the block ram and memory test routines, or reduce the memory size in top.v and Program.cs.
I hope this is useful.
When I talked to the FTDI guys at Electronica last week I did not get the impression that USB 3.0 will make FT2232H obsolete any time soon for FPGA: They have newer chips and modules but it didn't seem nearly as convenient, e.g. the modules are large and require high density connectors. In FPGA-land, I think USB 2.0 is going to stay...
Cheers
Markus

Hi @Jaraqui Peixe,
Unfortunately, Digilent does not have the ability to obtain these licenses for you with regards to Xilinx negotiations.
I do not doubt that the Spartan 3E Starter Boards you have are as good as new and work as such, but the reality is that last variant of ISE 14.7 that could support the FPGA chips on the Basys 2 and the Spartan 3E (both over 10 years old), was released by Xilinx back in 2013, so active support on these boards is limited as the required software will not install on newer OS's (at least the Windows variants anyway). As @xc6lx45, it is possible to make it work though.
What I would probably recommend is looking into the newer 7 series boards, such as the Basys 3 (the most similar to the Basys 2) or if you would want access to more memory than is provided in BRAM, both the Arty A7 and the Nexys A7 have on-board DDR memory. All of these boards work with Microblaze and are supported by the free Vivado WebPACK from Xilinx (which is license-free if that is a factor for you and includes Microblaze). Naturally, there is no guarantee that the Vivado software that supports these Artix 7 FPGA chips will become end-of-life'd, but I can at least say from Digilent's end that I have not heard of this happening in the near future.
Thanks,
JColvin

You might have a look at Trenz Electronics "Zynqberry". I think they managed to get one of the cameras to work (not sure). What I do remember is that the board has some custom resistor circuitry to additional pins for the required low-speed signaling.

Thank you all for replying!
@elodg Thanks for the tip! I was indeed using the vivado library IP core. From opencores I presume you meant this controller? https://opencores.org/projects/sdcard_mass_storage_controller
If so, it does look promising, since it will basically be a direct hardware link to the SD card (if I am reading this correctly), currently it's running on the microBlaze and going through SPI. I just hope that the PmodSD supports the opencores controller.
I registered there and hope to download and test the code soon! It appears to be written in verilog, hopefully that wont clash with my vhdl code.
@MirceaDabacan Thanks for the explanation! I will search for some low power speakers to use with the AMP2 that I have right now since I couldn't find the max vpp specs of my JBL charge 2+. Your suggestion for the I2S2 is also a very interesting solution and if I do want to hook up a separate amplifier then I will definitely look into that module!
@D@n Thanks for the suggestion! Creating a high speed buffer, with a much larger capacity than the RAM that is available on my basys 3 is very interesting! Considering that the data files are about 13 MB worth of samples per track, I could easily load the music from the SD card minute by minute, giving me ample time to continuously buffer during playback.
Thanks for the support! Much appreciated!
I will post back with my new findings!
Jonathan

Hi @hello.parth,
The Ethernet IP cores use the AXI BUS. You would need to implement the AXI BUS communication to interact with the Ethernet IP Cores. This is not an easy task.
You do not need to use Microblaze or the Ethernet IP Cores to use the ethernet on the Nexys Video. Here is a community members( @hamster) VHDL GigabitTX project using the Nexys Video.
thank you,
Jon

@zygot,
@Ahmed Alfadhel is not using a Basys3 board, and so this is really a bad example of attaching one question to another post. @Ahmed Alfadhel appears to be using an Artix-A7 board. In that case, the sys_clk is properly constrained, but he may well have some of the DDR3 I/O pins improperly constrained. These are the pins located on Bank 35.
I think the problem in this case is that @Ahmed Alfadhel has improperly constrained in DDR DQS pins. For example, ddr3_dqs_[0] should be set to pin N2, not to A6.
Compounding the problem is the way these pins are hidden in a "board definition file" rather than in the XDC file, making it likely to have conflicting pin definitions.
@Ahmed Alfadhel,
If you are following Digilent's instructions, you might want to double check that you have the appropriate board definition file. If you are trying this on your own, using only an XDC file, then you might find these instructions valuable. Also, I would recommend you not attach unrelated issues to old posts. Perhaps the Digilent staff might be kind enough to separate these two issues into separate forum posts--since they really are quite different. For example, the Basys3 board doesn't have the DDR3 memory which is the source of your pin-connection troubles.
Dan

Hi @ebattaglia42,
What operating system are you currently on? If you are Windows, can you attach a picture of what is shown in the Windows Device Manager and what you see in the WaveForms Device Manager (it should pop up when you initially connect the EE Board).
The other thing I would suggest to try would be to use a different USB cable (make sure it's not just for charging only) and/or USB port on your computer as that is another source of error that is easy to check.
Thank you,
JColvin

Hi @HelplessGuy,
To clarify you are trying to connect the Pmod GPS to the Zybo? Here is a completed Vivado 2018.2 Zybo/Pmod GPS without the sd card portion and using the interrupt. Here is a completed Vivado 2018.2 Zybo/Pmod GPS with the sd card portion and does not use the interrupt. Make sure you have the digilent board files installed correctly and that you fix the path to the vivado library to reflect where it is on your pc in Vivado's project manager->settings.
thank you,
Jon

Hi @jli853,
I reached out to one of our design engineers about this forum thread. They responded that
"Unless you do a non-blocking (overlapped) transfer the time it takes to execute the function will include not only the time to transfer the data over USB but also to shift it onto the JTAG scan chain. When the function returns all data has been transferred to the target JTAG device. How long that takes is going to very with the TCK frequency, as well as the PC side hardware and operating system. I don’t have any measured data to provide."
thank you,
Jon

Hi @BROLYNE,
I have not worked with multisim. I did find Digilent's Programming Digilent FPGA Boards Through Multisim and NI's Getting Started with Digilent Boards in Multisim tutorials that should help with getting the seven segment going.
thank you,
Jon

Hi @billskar23,
The Pmod ACL here uses the adxl345﻿. Here and here are forum threads that might be helpful. Here is an instructable on how to use spi in the linx platform. Here is spi open. Here is the plug and play instructable for linx. Here is another instructable using the Pmod ACL. Unfortunately, both of the instructables use the Pmod ACL in I2C and not SPI. Here is the adxl345 datasheet. On page 23 is the register map table. Page 15 describes how to use the spi communications. Clearing the SPI bit (Bit D6) in the DATA_FORMAT register (Address 0x31) selects 4-wire mode.
cheers,
Jon

Hi @armin,
Sorry for the confusion. I am suggesting that you program your Arty-A7 as you would normally through the usb uart. The program on the Arty-A7 should be a UART controller using pin E15 and E16 on Pmod Port JB for the TX and RX of the project.
cheers,
Jon

Szia @Andras
The Network Analyzer by default takes controls over the Wavegen channel 1 and configures the required frequency for each step. You could select NA/Wavegen/Channel/External but to be able the control the Wavegen manually, but in this case the previous Script solution won't work.
The Insert/Local lists specific variables and is available in other scriptable places, like scope custom math, measurements, logging, network analyzer custom plots
In each script editor including the Script tool you can use the Ctrl+Space to list available objects, variables... or child objects, properties, functions..

Hi, Jon,
I made a small software to test how big an array of char can be in SDK and still assign and read correct values on the ARTY-Z7-20 DRAM Memory.
I found out that it goes all to way to 500 MB. I did not check further, but that is a hell of a memory capacity !!! Very good !!!
Regards,
Antonio

Hi @Ictinike,
Have you resolved your issue, or found anything new? You mentioned this issue began when you updated the firmware; have you tried rolling back to a previous version and seeing if things work properly? If you are still having issues, I can help you troubleshoot and find the real issue at cause here.
Regards,
AndrewHolzer

Hi @Foisal Ahmed,
I have not setup a project like this. I would suggest to look through the 7 Series FPGAs Configurable Logic Block User Guide. I would also reach out to xilinx support as well.
thank you,
Jon

hi @jpeyron,
I followed the guide at GitHub under Readme in PMODSD. can you please guide me step wise on how to start from block design and than going to SDK and running the demo. I have added the pmodsd and zynq PS IPs, after auto connection and running the generate bitstream I get following error.
I need your guidance at this

Thank you Jpeyron! I reprogrammed the eeprom with your tool and now Vivado can find the CMOD A7
No idea how it went wrong in the first place however.. If I find something, I will let you know.
Thanks everyone!

Hi @Sung
The WaveForms application can be used in demo mode to explore the features. In demo mode the protocol signals are not generated properly but you can see the options a real device would provide.
1. You can use the Logic Analyzer to capture and decode communication.
This is mostly useful for debugging protocol like for timing, glitches...
2. You can use the Protocol interface to send or to capture data and save in text file.
You can also use JS code to automate communication in Custom tab or Script interface.
3. You can use the WaveForms SDK to create custom application/script.

FTDI USBs like AD, AD2, DD are not working with RPI model B (1,2,3) data packets/bytes are randomly lost.
The EExplorer with different USB controller is working fine on these.
All devices are working with other embeddeds: Zed, Zybo, BeagleBone…
According reports AD is working with the original RPI model A and probably Zero because it has similar chipset/USB.
The problem seems to be with FTDI or RPI B USB, library or hardware. You can find such comments regarding RPI problems with other devices too. Unfortunately we couldn't remediate this problem.