TSMC launches 0.15-micron manufacturing process

Taiwan Semiconductor Manufacturing Co. Ltd. today delivered its first 0.15-micron wafers to Altera Corp., claiming to have achieved the same yields as its 0.18-micron process technology.

The advance reduces average die sizes by 26% and boosts performance by 25% to 30% compared with TSMC's previous-generation process, and by nearly twice that of its 0.25-micron process, the company said.

The Hsinchu, Taiwan-based pure-play foundry said its 0.15-micron process was qualified at Fab 3 and will be deployed in three additional fabs by the end of 2001. TSMC said it has accepted tapeouts from three companies in addition to Altera and expects to ramp the new process into high volume in the third quarter.

TSMC said its 0.15-micron manufacturing line widths will enable Altera to accelerate its use of copper interconnects by one process generation, an option the company is expected to exercise in future PLD devices.

"Not only has TSMC delivered to us the foundry industry's first 0.15-micron technology, but they have done so with excellent yields and excellent device performance," said Francois Gregoire, senior director of technology for Altera, San Jose. "As a technology driver, we are actively working with TSMC to extend their 0.15-micron technology development program with a copper interconnect alternative. Within two months, we will receive from TSMC the first 100% copper chip at the 0.15-micron generation, that will give us a good understanding of the benefits of copper which will be used for all our products on 0.15-micron and 0.13-micron processes."

TSMC said its 0.15-micron technology family will include baseline, low-voltage, and low-power processes. The first baseline and low-voltage processes are beginning production now, while the low-power process will begin production in the third quarter.

TSMC's 0.15-micron technology employs seven layers of metal and has an L-effective gate length of 0.11 micron. Gate delay is 16 ps for the low-voltage version with gate overdrive and as low as 14 ps for a special, CPU-targeted process option. Features include 1.2- and 1.5-V core options and I/Os from 2.5 to 3.3 V.

The technology's 6T SRAM cell size enables use of up to 16 Mbits of SRAM on a single die, suiting the technology for a variety of system-on-chip applications in the networking, computing, and consumer market segments, according to TSMC.

The company added that is has already received an array of 0.15-micron libraries, such as core cells, memory compilers, and I/O cells, from library vendors, including Artisan Components, Avant!, Nurlogic, Synopsys, and Virage Logic.