Any ports declared between the ( and /*AUTOARG*/ are presumed to be
predeclared and are not redeclared by AUTOARG. AUTOARG will make a
conservative guess on adding a comma for the first signal, if you have
any ifdefs or complicated expressions before the AUTOARG you will need
to choose the comma yourself.

First, parameters are built into an enumeration using the synopsys enum
comment. The comment must be between the keyword and the symbol.
(Annoying, but that's what Synopsys's dc_shell FSM reader requires.)

Next, registers which that enum applies to are also tagged with the same
enum.

Finally, an AUTOASCIIENUM command is used.

The first parameter is the name of the signal to be decoded.

The second parameter is the name to store the ASCII code into. For the
signal foo, I suggest the name _foo__ascii, where the leading _ indicates
a signal that is just for simulation, and the magic characters _ascii
tell viewers like Dinotrace to display in ASCII format.

The third optional parameter is a string which will be removed
from the state names. It defaults to "" which removes nothing.

The fourth optional parameter is "onehot" to force one-hot
decoding. If unspecified, if and only if the first parameter
width is 2^(number of states in enum) and does NOT match the
width of the enum, the signal is assumed to be a one-hot
decode. Otherwise, it's a normal encoded state vector.

You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included. For example the
same expansion will result from only extracting inouts starting with i:

Expand AUTOINOUTCOMP statements, as part of M-x verilog-auto.
Take input/output/inout statements from the specified module and
insert the inverse into the current module (inputs become outputs
and vice-versa.) This is useful for making test and stimulus
modules which need to have complementing I/O with another module.
Any I/O which are already defined in this module will not be
redefined. For the complement of this function, see
verilog-auto-inout-module.

You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included. For example the
same expansion will result from only extracting signals starting with i:

/*AUTOINOUTCOMP("ExampMain","^i")*/

You may also provide an optional third argument regular
expression, in which case only signals which have that pin
direction and data type matching that regular expression will be
included. This matches against everything before the signal name
in the declaration, for example against "input" (single
bit), "output logic" (direction and type)
or "output [1:0]" (direction and implicit type). You also
probably want to skip spaces in your regexp.

For example, the below will result in matching the output "o"
against the previous example's module:

/*AUTOINOUTCOMP("ExampMain","","^output.*")*/

You may also provide an optional fourth argument regular
expression, which if not "" only signals which do NOT match
that expression are included.

You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included. For example the
same expansion will result from only extracting signals starting with i:

You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included. For example the
same expansion will result from only extracting signals starting with i:

/*AUTOINOUTMODULE("ExampMain","^i")*/

You may also provide an optional third argument regular
expression, in which case only signals which have that pin
direction and data type matching that regular expression will be
included. This matches against everything before the signal name
in the declaration, for example against "input" (single
bit), "output logic" (direction and type) or
"output [1:0]" (direction and implicit type). You also
probably want to skip spaces in your regexp.

For example, the below will result in matching the output "o"
against the previous example's module:

/*AUTOINOUTMODULE("ExampMain","","^output.*")*/

You may also provide an optional fourth argument regular
expression, which if not "" only signals which do NOT match
that expression are included.

You may also provide an optional regular expression, in which case only
parameters matching the regular expression will be included. For example the
same expansion will result from only extracting parameters starting with i:

You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included. For example the
same expansion will result from only extracting inputs starting with i:

Unless you are instantiating a module multiple times, or the module is
something trivial like an adder, DO NOT CHANGE SIGNAL NAMES ACROSS HIERARCHY.
It just makes for unmaintainable code. To sanitize signal names, try
vrename from URL `http://www.veripool.org'.

When you need to violate this suggestion there are two ways to list
exceptions, placing them before the AUTOINST, or using templates.

Any ports defined before the /*AUTOINST*/ are not included in the list of
automatics. This is similar to making a template as described below, but
is restricted to simple connections just like you normally make. Also note
that any signals before the AUTOINST will only be picked up by AUTOWIRE if
you have the appropriate // Input or // Output comment, and exactly the
same line formatting as AUTOINST itself uses.

For multiple instantiations based upon a single template, create a
commented out template:

/* InstModule AUTO_TEMPLATE (
.sig3 (sigz[]),
);
*/

Templates go ABOVE the instantiation(s). When an instantiation is
expanded verilog-mode simply searches up for the closest template.
Thus you can have multiple templates for the same module, just alternate
between the template for an instantiation and the instantiation itself.
(For backward compatibility if no template is found above, it
will also look below, but do not use this behavior in new designs.)

The module name must be the same as the name of the module in the
instantiation name, and the code "AUTO_TEMPLATE" must be in these exact
words and capitalized. Only signals that must be different for each
instantiation need to be listed.

Inside a template, a [] in a connection name (with nothing else
inside the brackets) will be replaced by the same bus subscript
as it is being connected to, or the [] will be removed if it is
a single bit signal.

Inside a template, a [][] in a connection name will behave
similarly to a [] for scalar or single-dimensional connection;
for a multidimensional connection it will print a comment
similar to that printed when a template is not used. Generally
it is a good idea to do this for all connections in a template,
as then they will work for any width signal, and with AUTOWIRE.
See PTL_BUS becoming PTL_BUSNEW below.

Inside a template, a [] in a connection name (with nothing else inside
the brackets) will be replaced by the same bus subscript as it is being
connected to, or the [] will be removed if it is a single bit signal.
Generally it is a good idea to do this for all connections in a template,
as then they will work for any width signal, and with AUTOWIRE. See
PTL_BUS becoming PTL_BUSNEW below.

If you have a complicated template, set verilog-auto-inst-template-numbers
to see which regexps are matching. Don't leave that mode set after
debugging is completed though, it will result in lots of extra differences
and merge conflicts.

If no regular expression is provided immediately after the AUTO_TEMPLATE
keyword, then the @ character in any connection names will be replaced
with the instantiation number; the first digits found in the cell's
instantiation name.

If a regular expression is provided, the @ character will be replaced
with the first () grouping that matches against the cell name. Using a
regexp of "\([0-9]+\)" provides identical values for @ as when no
regexp is provided. If you use multiple layers of parenthesis,
"test\([^0-9]+\)_\([0-9]+\)" would replace @ with non-number
characters after test and before _, whereas
"\(test\([a-z]+\)_\([0-9]+\)\)" would replace @ with the entire
match.

will apply an Emacs style regular expression search for any port beginning
in pci_req followed by numbers and ending in _l and connecting that to
the pci_req_jtag_[] net, with the bus subscript coming from what matches
inside the first set of \( \). Thus pci_req2_l becomes pci_req_jtag_[2].

Since \([0-9]+\) is so common and ugly to read, a @ in the port name
does the same thing. (Note a @ in the connection/replacement text is
completely different -- still use \1 there!) Thus this is the same as
the above template:

.pci_req@_l (pci_req_jtag_[\1]),

Here's another example to remove the _l, useful when naming conventions
specify _ alone to mean active low. Note the use of [] to keep the bus
subscript:

.\(.*\)_l (\1_[]),

Lisp Templates:

First any regular expression template is expanded.

If the syntax @"( ... )" is found in a connection, the expression in
quotes will be evaluated as a Lisp expression, with @ replaced by the
instantiation number. The MAPVALIDP1X example above would put @+1 modulo
4 into the brackets. Quote all double-quotes inside the expression with
a leading backslash (\"...\"); or if the Lisp template is also a
regexp template backslash the backslash quote (\\"...\\").

There are special variables defined that are useful in these
Lisp functions:

vl-name Name portion of the input/output port.
vl-bits Bus bits portion of the input/output port ('[2:0]').
vl-mbits Multidimensional array bits for port ('[2:0][3:0]').
vl-width Width of the input/output port ('3' for [2:0]).
May be a (...) expression if bits isn't a constant.
vl-dir Direction of the pin input/output/inout/interface.
vl-modport The modport, if an interface with a modport.
vl-cell-type Module name/type of the cell ('InstModule').
vl-cell-name Instance name of the cell ('instName').

Normal Lisp variables may be used in expressions. See
verilog-read-defines which can set vh-{definename} variables for use
here. Also, any comments of the form:

/*AUTO_LISP(setq foo 1)*/

will evaluate any Lisp expression inside the parenthesis between the
beginning of the buffer and the point of the AUTOINST. This allows
functions to be defined or variables to be changed between instantiations.
(See also verilog-auto-insert-lisp if you want the output from your
lisp function to be inserted.)

Note that when using lisp expressions errors may occur when @ is not a
number; you may need to use the standard Emacs Lisp functions
`number-to-string' and `string-to-number'.

After the evaluation is completed, @ substitution and [] substitution
occur.

For more information see the M-x verilog-faq and forums at URL
`http://www.veripool.org'.

You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included. For example the
same expansion will result from only extracting outputs starting with ov:

Expand AUTOOUTPUTEVERY statements, as part of M-x verilog-auto.
Make output statements for any signals that aren't primary inputs or
outputs already. This makes every signal in the design an output. This is
useful to get Synopsys to preserve every signal in the design, since it
won't optimize away the outputs.

You may also provide an optional regular expression, in which case only
signals matching the regular expression will be included. For example the
same expansion will result from only extracting outputs starting with ov:

/*AUTORESET*/ presumes that any signals mentioned between the previous
begin/case/if statement and the AUTORESET comment are being reset manually
and should not be automatically reset. This includes omitting any signals
used on the right hand side of assignments.

By default, AUTORESET will include the width of the signal in the
autos, SystemVerilog designs may want to change this. To control
this behavior, see verilog-auto-reset-widths. In some cases
AUTORESET must use a '0 assignment and it will print NOWIDTH; use
verilog-auto-reset-widths unbased to prevent this.

AUTORESET ties signals to deasserted, which is presumed to be zero.
Signals that match verilog-active-low-regexp will be deasserted by tying
them to a one.

AUTORESET may try to reset arrays or structures that cannot be
reset by a simple assignment, resulting in compile errors. This
is a feature to be taken as a hint that you need to reset these
signals manually (or put them into a "\=`ifdef NEVER signal<=\=`0;
\=`endif" so Verilog-Mode ignores them.)

AUTOSENSE cannot always determine if a \=`define is a constant or a signal
(it could be in an include file for example). If a \=`define or other signal
is put into the AUTOSENSE list and is not desired, use the AUTO_CONSTANT
declaration anywhere in the module (parenthesis are required):

/* AUTO_CONSTANT ( `this_is_really_constant_dont_autosense_it ) */

Better yet, use a parameter, which will be understood to be constant
automatically.

OOps!

If AUTOSENSE makes a mistake, please report it. (First try putting
a begin/end after your always!) As a workaround, if a signal that
shouldn't be in the sensitivity list was, use the AUTO_CONSTANT above.
If a signal should be in the sensitivity list wasn't, placing it before
the /*AUTOSENSE*/ comment will prevent it from being deleted when the
autos are updated (or added if it occurs there already).

If verilog-auto-star-expand is set, .* pins are treated if they were
AUTOINST statements, otherwise they are ignored. For safety, Verilog mode
will also ignore any .* that are not last in your pin list (this prevents
it from deleting pins following the .* when it expands the AUTOINST.)

/*AUTOTIEOFF*/ is used to make stub modules; modules that have the same
input/output list as another module, but no internals. Specifically, it
finds all outputs in the module, and if that input is not otherwise declared
as a register or wire, creates a tieoff.

AUTORESET ties signals to deasserted, which is presumed to be zero.
Signals that match verilog-active-low-regexp will be deasserted by tying
them to a one.

/*AUTOUNUSED*/ is used to make stub modules; modules that have the same
input/output list as another module, but no internals. Specifically, it
finds all inputs and inouts in the module, and if that input is not otherwise
used, adds it to a comma separated list.

The comma separated list is intended to be used to create a _unused_ok
signal. Using the exact name "_unused_ok" for name of the temporary
signal is recommended as it will insure maximum forward compatibility, it
also makes lint warnings easy to understand; ignore any unused warnings
with "unused" in the signal name.

To reduce simulation time, the _unused_ok signal should be forced to a
constant to prevent wiggling. The easiest thing to do is use a
reduction-and with 1'b0 as shown.

This way all unused signals are in one place, making it convenient to add
your tool's specific pragmas around the assignment to disable any unused
warnings.

This ONLY detects outputs of AUTOINSTants (see verilog-read-sub-decls),
and all buses must have widths, such as those from AUTOINST, or using []
in AUTO_TEMPLATEs.

This does NOT work on memories or SystemVerilog .name connections,
declare those yourself.

Verilog mode will add "Couldn't Merge" comments to signals it cannot
determine how to bus together. This occurs when you have ports with
non-numeric or non-sequential bus subscripts. If Verilog mode
mis-guessed, you'll have to declare them yourself.

Verilog-mode attempts to detect changes to this local variable, but they
are only insured to be correct when the file is first visited. Thus if you
have problems, use M-x find-alternate-file RET to have these take effect.

Note includes are only read when the file is first visited, you must use
M-x find-alternate-file RET to have these take effect after editing them!

It is good to get in the habit of including all needed files in each .v
file that needs it, rather than waiting for compile time. This will aid
this process, Verilint, and readability. To prevent defining the same
variable over and over when many modules are compiled together, put a test
around the inside each include file: