This paper describes the principles of high level modeling of digital hardware circuits using the Extended Timing Diagrams (ETD) formalism which adds conditions, events, action expressions and particular constraints to traditional timing diagrams. Hierarchy and concurrency are integrated too such that a full top-down design becomes possible, enhancing in… (More)

The ever increasing complexity of digital hardware, forces the hardware designer to switch from a low-level capture-and-simulation process to a high-level design-and-synthesis process. In order to assist the designer during the specification phase, we designed MODES, a new high-level specification environment. MODES integrates graphical specification… (More)