Dhaval Brahmbhatt -2017 Vice Chair Mr. Brahmbhatt brings over 30 years of experience in the Silicon Valley as Engineer, Adjunct Faculty, Technologist, entrepreneur businessman, community leader, and as a Senior Executive. He has founded high-tech companies and has also provided guidance to entrepreneurs. He is a creative technologist with 11 US patents and has provided services as an IP Expert Witness. Mr. Brahmbhatt has reviewed SBIR/STTR grant applications for various agencies of the United States Government in subjects ranging from Nanotechnology, Advanced Semiconductors, MEMS/NEMS, to Communications, sensors, etc. Mr. Brahmbhatt is a registered Language Interpreter with California Judicial Council for 6 south Asian languages (from India) and one language from Fiji.

Mr. Brahmbhatt founded the IEEE SF Bay Area Nanotechnology Council and is its past Chairman. Mr. Brahmbhatt has taught Nanotechnology courses at SPIE annual conferences, Santa Clara University Graduate School of Engineering and at the Ohlone College. He was placed on the Nanotechnology Advisory Board of Foothill College and on the Committee to Advance Nanoscience Education at SRI. Mr. Brahmbhatt was a member of the Blue Ribbon Task Force on Nanotechnology for the State of California and worked on its Education Sub-committee. He is a Senior member of the IEEE and is also involved with the IEEE Vehicle Technology Society. He has been recognized numerous times by the IEEE with citations and awards. Mr. Brahmbhatt is the former President and Board Member of the prestigious Silicon Valley Engineering Council.

He is currently President & CEO of PHYchip Corporation, a company he founded in 2002. This company works in renewable energy, IP expert witness work, and government contracts. He has earned a graduate degree in Physics from India and a MS Electrical Engineering degree from the University of Cincinnati. He is a certified energy efficiency engineer and a green building professional.

Paul Brunemeier, 2016 Chair Emeritus – Dr. Brunemeier is a nanostructure and semiconductor technologist and has developed and scaled materials, device processes, and equipment (lasers, FETs, MEMS, nano, and CMOS) throughout a career spanning nearly 30 years. He currently operates his own consulting business. Prior to this he served as Sr. Director of Engineering for Amprius, where he discovered a silicon nanostructure that enabled the company to greatly increase lithium-ion battery cycle life. He led his team to build and ramp the company’s first pilot line for silicon nanowire lithium ion batteries.

Dr. Brunemeier has 19 publications and conference presentations and is primary inventor on six patents, five of which were commercialized. He holds a physics Ph.D. from University of Illinois and conducted his thesis research in semiconductor quantum-well lasers in the laboratory of Nick Holonyak, Jr., the inventor of the LED. Dr. Brunemeier also earned a physics BS from University of California at Davis, with a concentration in physics of materials.

Folarin Erogbogbo, 2016 Vice Chair – Upon receiving his B.S in Chemical Engineering, Prof. Erogbogbo stayed on as an National Science Foundation IGERT Fellow to pursue a graduate degree in Chemical and Biological Engineering at University at Buffalo (SUNY) with Professor Mark Swihart. He then moved to the Institute for Lasers Photonics and Biophotonics and served as a Ford Fellow with Professor Paras N. Prasad. He has published multiple high impact peer reviewed articles on nanoplatforms for biomedical applications. He has won numerous awards for his research and mentoring work. Professor Erogbogbo joined the SJSU faculty in the summer of 2013 as an Assistant Professor in the Biomedical, Chemical and Materials Engineering Department. His research focuses on scalable synthesis of biocompatible nanomaterials for biomedical applications.

Vasuda Bhatia, 2017 Secretary – Dr. Bhatia is a professor at Amity Institute of Renewable and Alternative Energy and Amity Institute of Advanced Research and Studies, Amity University, India. She received her B.Tech. (Bachelors of Technology) in Materials and Metallurgical Engineering from Indian Institute of Technology (IIT) Kanpur, India in 1995, MS in Materials Science from the University of Cincinnati in 1997 and the Ph.D. in Electrical Engineering from Texas A&M University in 2001. She was research scientist at Stellar Micro Devices, Austin, Texas; visiting faculty at IIT Kanpur, India and research associate at Jawaharlal Nehru Centre for Advanced Scientific Research, Bangalore, India. Her research interests include synthesis, characterization and device applications of nanomaterials; materials for renewable energy applications; field emission devices and materials and development of sensors and sensing devices for bio, chemical and gas applications.

Ning Ge, 2017 Treasurer – Mr. Ning is a master technologist of Hewlett-Packard Labs. He has worked at HP since 2006 and has about 110 US/PCT granted patents/patents applications & defensive publications and a dozen of peer reviewed internal & external journal papers. In the past Ning worked on thermal inkjet technology and served as lead role for HP consumer printhead development for years (you probably are printing with printhead designed by him if you are using HP consumer printer). Currently he is focusing on memristor, next generation selector, neuromorphic computing, ink & chemical sensing, low cost MEMS & packaging etc in HP labs. Ning has a bachelor and master in IC Design from Nanyang Technological University, Singapore and a master in Intellectual Property Management from National University of Singapore, Singapore. Currently he is pursuing a part-time PhD study on nano device from Nanyang Technological University, Singapore and expected to graduate by end of this year.

Lincoln Bourne, 2017 Promotions Chair – Lincoln is a Senior Scientist/Engineer at IBM. He helped launch Linear Tape Open, a new platform for magnetic data storage, with revenues now exceeding $1 Billion per year. His current role is to move new materials and processes into mass production. Before IBM, Lincoln joined two early-stage startups seeking to commercialize novel materials, and helped each to achieve a successful IPO – Superconductor Technologies and Conductus. Lincoln has a PhD in Physics from UC Berkeley, where he was a National Science Foundation Fellow. He led the team that found the mechanism of high-temperature superconductivity to be fundamentally different from the phonon-mediated electron pairing of all previous superconductors, a result described by Physics Today as “A tour de force, experimentally”.

Geetha Dholakia – Dr. Dholakia’s research interests are at the interface of Physics, Materials Science and Electrical Engineering. She studies electronic transport at the nanoscale in nanomaterials and soft materials, researching the application of multifunctional materials such as nanowires, nanoscale films and organic films to organic electronic devices and photovoltaic systems. She has extensive experience in scanning probe microscopy and its instrumentation and has worked to miniaturize instruments for NASA on board rover missions. She has been associated with IEEE SFBA Nanotechnology Council since 2008. During this time she has organized and co-chaired two conferences – Nanotech Enabled Energy Generation & Management in 2009 and Nanotechnology Consumer Applications in 2011. She received a PhD in Physics from the Indian Institute of Science, Bangalore, India and Masters in Physics from the Indian Institute of Technology, Madras, India.

Don Gardner, Donald Gardner is an IEEE Fellow and a Principal Engineer at Intel. He received his Ph.D. in Electrical Engineering from Stanford University. Donald is the inventor or co-inventor of 96 granted U.S. patents including for high-frequency voltage converters, embedded and electrochemical capacitors, and inductors using magnetic materials. He has published 160+ papers that have been cited by over 4,400 authors (h-index = 32). He has received five Best Paper and Poster awards and Intel’s highest technical award “For Fundamentally Changing Platform Power Delivery with Integrated Voltage Regulators and Magnetic Inductors on CMOS”. In addition, an award for the “World’s First Integrated Voltage Regulator” was bestowed for the idea of creating high-frequency integrated voltage regulators which was implemented by a team of brilliant designers in the “Haswell” fourth-generation Intel microprocessors which resulted in a 50~100% laptop battery life increase. He also invented embedded MIM capacitors that are in third and fourth generation Intel microprocessors. Don also developed integrated inductors with magnetic material that have the highest inductance density known. He invented new electrochemical capacitors for energy storage suitable for IoTs. He also conceived reflowed copper technology and used it to fabricate the first working chip with copper-based interconnections and also invented an Al alloy/Ti metallization for interconnections that was widely used by most microchip manufacturers. His current interests include energy storage devices, power delivery technology for future microprocessors, magnetic materials for inductors, new materials integration and nanostructure design.

Dr. Murthy is a polymath inventor and expert in nano, solar, big data, and video games. He holds the track record for the fastest growing private company in the USA.He grew a variety of companies by both organically and inorganically, one of them from $60M to $550M in revenue only one year and a valuation to $3.5B.

He has served on the board of directors the of IEEE and the boards of six IEEE societies. Dr. Murthy is an expert in mergers and acquisitions (M&A) and corporate governance.

Ranjeet Pancholy– Dr. Pancholy is a Semiconductor Technology Expert with over 30 years of Advanced Technology Research and Development, Fabless Manufacturing, and Cost Optimization experiences for ASIC/SOC, Nanotechnology and Renewable Energy fields. He is currently a Consultant for Global clients for Industry, Operations, Management and Manufacturing of Semiconductor and Renewable Energy Products. Previously, Dr. Pancholy worked at large Multinational Semiconductor companies like Qualcomm Technologies, Seagate Technology, Cypress Semiconductors, Rockwell International and Hughes Aircraft Company in Research, Engineering and Management Capacities managing over $4B per year production of ASICs/ SOCs/MEMs and mobile chip sets. Dr. Pancholy has 5 US and International Patents and over 30 Publications in International Journals and Conferences. He has been an editor of IEEE Transactions on Electron Devices, Consultant and United Nations UNDP Advisor to Government of India for SCL Chandigarh Fab, Executive Committee member Conference Organizer and Chairman of several IEEE conferences on Electron Devices, Nanotechnology, Reliability Physics and Nuclear Radiation Effects. He received his PhD. Degree in Electrical Engineering from University of New Mexico, Albuquerque, NM, a MSEE from Oklahoma State University, Stillwater Oklahoma and M.Sc. and B.Sc. Physics degrees from the Birla Institute of Technology & Science, Pilani, India. He is member of executive Committee of San Francisco Bay Area Nanotechnology Council and currently involved with new advanced micro wind and micro power renewable energy devices.

John Paul Strachan – Dr. Strachan is a researcher at Hewlett-Packard Labs. He received his BS in physics and PhD in applied physics from Massachusetts Institute of Technology in 2001 and Stanford University in 2007, respectively. He has published 24 peer-reviewed papers and holds 6 patents, with more than 30 pending. He currently develops next generation memories and computational devices at HP. Previously, he has researched nanomagnetic devices for non-volatile memory, and nutrient sensors for precision agriculture with Solum, Inc, which he helped co-found. His interests include nanoelectronics, sensors, novel computational schemes, and generally finding new ways to understand and exploit material, structural, and electronic properties at the nanoscale.

Kris Verma – Dr. Verma is a veteran of the Semiconductor Industry with over 37 years experience in Semiconductor Devices, Fabrication, Factories buildings, R/D, Reliability plus 5 years in the Hard Disk Drive Industry , all in Silicon Valley, California. His expertise resides in CMOS processes, Devices, Wafer Manufacturing, VLSI CHIPS for HDD and R/D projects management in High Tech Industry. Presently, he is engaged as a Sr. Faculty member at California Polytechnic Institute training engineers through courses including: Solar Energy’s Opportunities and Challenges, Nano-Technology, and Smart Power Grid. He is also Program Director for CalPT’s Symposium on Solar Energy. He was awarded an IEEE Millennium medal winner in 2000 for his contributions including 20 published papers and chairing numerous IEEE meetings and conferences. He is also an Emeritus Chairperson of the IEEE SFBA Nanotechnology Council. In addition, he is also involved as an IEEE officer for Photovoltaic chapter start-up and SVEC Board Member. Dr. Verma was awarded an ISQED fellowship and Best Engineer Award from IEEE Santa Clara valley Section in 2008 and 2010 respectively. He earned his PhD in EE from University of Utah, Salt Lake City and MBA from Portland University, Oregon.

Nick Massetti– Mr. Massetti has over 40 years of industry experience spanning multiple applications of integrated circuit device and fabrication technology. He has recently retired from the position of Sr. Technology and IP Coordinator for image sensor manufacturer OmniVision Technologies. Prior to that he directed technology related assessments of intellectual property for IPValue Management. He mined and evaluated the patent portfolios of Fortune 500 high-tech companies. He previously served as Senior Director, VLSI Manufacturing Technology, for HDD industry leader Seagate Technology where he ensured mass market commercialization of state-of-the art IC fabrication technology. Prior to that, he was Director of Technology Development & Quality Systems at Texas Instruments. There he developed and applied high speed analog BiCMOS manufacturing technologies to products used in high capacity storage systems, wireless communication components, and PC processor interfaces. Earlier in his career he developed CMOS logic and non-volatile memory technologies, and managed pilot fabrication lines at NCR Microelectronics and Philips Semiconductors. In his initial career assignment at Hughes Aircraft he fabricated a space qualified image sensor subsequently used for Earth Resources imaging on the Landsat IV Satellite. He has been active in promoting nanotechnology by organizing forums and speaking on the subject. He has published related on-line articles. Since 2005 he has held multiple Chapter officer positions for the San Francisco Bay Area IEEE Nanotechnology Council Chapter. As an NSF peer reviewer he continues to support investments in small high tech businesses. Mr. Massetti holds a Master of Science degree in Applied Solid State Physics from the University of California, San Diego. He also earned his Bachelor of Science degree in Physics at St. Mary’s College of California.

Ira Feldman– Mr. Feldman is the principal consultant at Feldman Engineering Corp., where he manages and develops unique high technology solutions and business strategies. As a successful executive, he has proven his leadership ability to resolve product management and engineering challenges within organizations as well as with their supply chain and customers. Mr. Feldman’s broad knowledge and management experience with high volume manufacturing of complex technology products is the result of his extensive expertise in the semiconductor test and computer test industries. As Vice President of Business Development for Microfabrica, he identified and successfully brought to market many new applications for their EFAB technology (which is a breakthrough platform that enables the creation of sub-millimeter, 3D, fully-assembled micro-machines and precision parts of unprecedented scale and performance). Previously, at the probe card manufacturer NanoNexus, he was the Director of Products and Applications and the Director of Design Engineering. He managed a global team of engineers at Agilent Technologies (now Verigy/Advantest) that integrated Automatic Test Equipment (ATE) into end customers’ high volume manufacturing facilities prior to that. At Hewlett-Packard, at the star of his career, he drove the successful manufacturing introduction and ramp up of several generations of high-end mini-computers. He earned both a BS in Engineering and a Master of Engineering degree from Harvey Mudd College. And he publishes his “High Technology Business Development” blog which often covers nanotechnology, MEMS, semiconductor, and test topics.

Jeongwon Park – Dr. Park is senior research scientist in the Advanced Technologies Group, Office of the CTO Group, at Applied Materials, USA. He is an adjunct professor in the department of electrical engineering at Santa Clara University. He received a PhD from the University of California, San Diego in Materials Science and Engineering in 2008. His expertise is in nano-materials including CNT and graphene, nano-electronics, III-V semiconductor and Silicon Integrated Circuit processing coupled with a strong background in design and test. In addition to the industrial affiliations, he is currently involved with a close collaboration program with Stanford EE faculty members (Profs. Saraswat, Nishi, Phillip Wong, etc), MIT and UC Berkeley though his position at Applied Materials. His teaching efforts at Santa Clara include graduate level coursework on: “Fundamentals of Semiconductor Physics”, “Nanoelectronics”, “Nanotechnology”, “Nanomaterials”, etc in the Electrical Engineering Department at Santa Clara University. During his PhD, he focused on nanoelectronics with carbon nanotubes and organic field effect transistors including fabrication within a clean room, experience with CMOS, MEMS, packaging, device processing/measurements, simulations and modeling tools. These supplemental areas of focus and his continued interest and study of epitaxial Si, SiGe, III-V cleaning, Carbon Nanotube, Graphene, and similar materials have been on-going in parallel with his professional career. He has been a guest researcher at NASA Ames Research Center, Lawrence Berkeley National Labs(LBNL), and Sun Microsystems, in addition to his work at UCSD, Hanyang University, Institute for Advanced Engineering, and Seoul National University in Korea. He has published more than twenty papers.

Jianhua (Joshua) Yang – Dr. Yang is Principal Research Scientist at HP Labs, leading the ReRAM (Memristor) device study effort. His current research interest is Nanoelectronics and Nanoionics, especially for memory and computing applications, where he authored and co-authored over 100 papers in academic journals and international conferences, and holds 15 granted and over 60 pending US Patents. In the last 3 years, he has been invited to international conferences or universities to give over 20 keynote speeches, invited talks, or seminars. He recently guest-edited two journal special issues on Non-volatile Memory technologies for Nanotechnology and Applied Physics A, respectively. He also serves as a co-editor of Applied Physics A. He obtained his PhD from the University of Wisconsin – Madison in Material Science Program in 2006 and joined HP at that time.