A CMOS four-quadrant analog current multiplier is described. The circuit is based on the square-law characteristic of an MOS transistor and is insensitive to temperature and process variations. The circuit is insensitive to the body effect so it is not necessary to place transistors in individual wells. The multiplier has a large -3-dB bandwidth (50 MHz with 10-¿m transistors) and an approximately constant input impedance. The circuit was realized on a CMOS semicustom array. Measurements have shown that the nonlinearity is less than 1% at the maximum input current range and less than 0.2% when the input range is restricted to 50% of the maximum