Abstract

This study presents mathematical model and optimization in switching actions using timing and signal constraints while performing arithmetic and logical operations in serially designed ALU. Signal and timing constraints are inevitable to describe in VLSI circuit design in order to get perfect synthesis, post simulation and implementation on FPGA. For the simulation and verification of our idea, VHDL programming and MODEL SIM tool is utilized. Our proposed study not only corresponds to different arithmetic and logical operations but also depicts the concepts of serial to parallel data conversion through FSM.

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