Empowers designers to do "more" with highest levels of trust, integrity, and parasitic accuracy for on-time tapeout

Key Benefits

Trusted by all leading customers and foundries—provides the best-in-its-class accuracy for all design nodes for faster design convergence

Massively parallel and cloud-ready for fastest single and multi-corner performance with linear scaling to 1000s of CPUs for on-time tapeout

Built-in massively parallel and cloud-ready 3D Field Solver, Quantus FS, for all critical and advanced-node designs for accurate parasitics

Provides many market-leading analysis features and functionality to support both digital and transistor designs extraction

Foundry certified at TSMC down to 7nm and for early 5nm designs

Certified for advanced-node processes at other foundries worldwide

The Cadence® Quantus™ Extraction Solution is the industry’s most trusted signoff parasitic extraction tool. As a single, unified tool, the Quantus solution supports both cell-level and transistor-level extractions during design implementation and signoff. It’s an integral component of our in-design methodology with both the Innovus™ Implementation System and Virtuoso® platforms.

The Quantus Extraction Solution is the linchpin that allows designers to do more with Rs and Cs on both digital- and transistor-level flows, assuring on-time tapeout.

The Quantus solution is central to full flow for both digital and transistor extraction

Using these [Quantus, Tempus, and Tempus ECO] signoff engines, which are consistent with the Cadence Innovus Implementation System for both extraction and static timing analysis, ensured tight correlation and a reduction in design iterations during signoff for quick design convergence.

Customer Support

Get the most out of your investment in Cadence technologies through a wide range of training offerings. We offer instructor-led classes at our training centers or at your site. We also offer self-paced online courses. Overview