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Abstract

This article describes a method for controlling hard and soft resets to a processor during hardware verification, to increase availability of the system under test and to increase test coverage.

Country

United States

Language

English (United States)

This text was extracted from an ASCII text file.

This is the abbreviated version, containing approximately
60% of the total text.

Processor Reset Control for Hardware Verification

This article
describes a method for controlling hard and soft
resets to a processor during hardware verification, to increase
availability of the system under test and to increase test coverage.

Hardware processor verification is entirely
dependent on
running test cases. The majority of test
cases are run in an
automated fashion. Test case or hardware
bugs can cause the
processor to checkstop (signal a fatal error) or hang--both
unrecoverable conditions that require a hard reset to continue.
These fatal errors halt an automated run and result in lost test
time. A device, such as a
microcontroller, gate array, or an
external tool such as a test server, can be used to generate hard
processor resets for the system under test.
The device monitors
checkstop signals from each processor in the system under test, and
in response to a checkstop condition, issues hard resets. The device
can detect processor hang conditions by using a time-out function: if
a given response or scenario is not detected in a specified period of
time, then a hang condition is assumed, and a hard reset is
initiated. The hard reset allows the
processor to continue executing
test cases. The test case that caused
the error condition can be
investigated later, after the automated run.

Some
processors also have a soft reset mechanism which acts
much like a non-maskable external interrupt.
For these processors,
test...