EmbeddedSystemsDesign

This course is designed to bring FPGA designers up to speed on developing embedded systems using the Vivado® Design Suite. The features and capabilities of both the Zynq® All Programmable System on a Chip (SoC) and the MicroBlaze™ soft processor are covered in lectures, demonstrations, and labs, along with general embedded concepts, tools, and techniques. The hands-on labs provide students with experience designing, expanding, and modifying an embedded system, including adding and simulating a custom AXI-based peripheral using bus functional model (BFM) simulation.

The Xilinx Zynq All Programmable SoC enables a new level of system design capabilities over previous embedded technologies and this is highlighted throughout the course.

Level

Embedded Hardware 3

Training Duration

2 days

Who Should Attend?

Engineers who are interested in developing embedded systems with the Xilinx Zynq All Programmable SoC or MicroBlaze soft processor core using the Embedded Development Kit.

1.1 Embedded UltraFast Design MethodologyOutlines the different elements that comprise the Embedded Design Methodology. 1.2 Overview of Embedded Hardware DevelopmentOverview of the embedded hardware development flow. 1.3 Driving the IP Integrator ToolDescribes how to access and effectively use the IPI tool. 1.4 Overview of Embedded Software DevelopmentReviews the process of building a user application. 1.5 Driving the SDK ToolIntroduces the basic behaviors required to drive the SDK tool to generate a debuggable C/C++ application. 1.6 AXI: IntroductionIntroduces the AXI protocol. 1.7 AXI: VariationsDescribes the differences and similarities among the three primary AXI variations. 1.8 AXI: TransactionsDescribes different types of AXI transactions. 1.9 Introduction to InterruptsIntroduces the concept of interrupts, basic terminology, and generic implementation. 1.10 Interrupts: Hardware Architecture and SupportReviews the hardware that is typically available to help implement and manage interrupts.

Day 2

2.1 AXI: Connecting AXI IPDescribes the relationships between different types of AXI interfaces and how they can be connected to form hierarchies. 2.2 Using the Create and Import Wizard to Create a New AXI IPExplains how to use the Create and Import Wizard to create and package an AXI IP. 2.3 AXI: BFM SimulationDescribes how to perform BFM simulation, which can accelerate the pace of verification. 2.4 MicroBlaze Processor Architecture OverviewOverview of the MicroBlaze microprocessor architecture. 2.5 MicroBlaze Processor Block Memory UsageHighlights how block RAM can be used with the MicroBlaze processor. 2.6 Zynq-7000 All Programmable SoC Architecture OverviewOverview of the Zynq-7000 All Programmable SoC architecture. 2.7 Zynq UltraScale+ MPSoC Architecture OverviewOverview of the Zynq UltraScale+ MPSoC architecture.