Calypto adds VHDL support to PowerPro CG

SAN FRANCISOCalypto Design Systems Inc. has added new sequential power optimizations and support for VHDL designs its PowerPro CG automated register transfer level (RTL) power optimization solution, the company said Monday (Oct. 20)

Calypto (Santa Clara, Calif.) said PowerPro CG (clock gating) automatically reduces power by reading a synthesizable RTL design captured in VHDL or Verilog and generating a RTL design identical to the original design with additional clock-gating enable logic.

Support for VHDL will be of particular benefit to customers in European consumer and wireless electronics companies where VHDL is the dominant design language, Calypto said.

PowerPro CG identifies sequential clock-gating enable conditions based on Calypto's sequential analysis technology. The new sequential optimizations save additional power in heavily clock-gated RTL code, such as existing consumer and wireless designs that previously have been optimized manually, Calypto said.

The latest release of PowerPro CG finds clock-gating enable conditions beyond those already present in the design, according to Calypto.

The latest version of PowerPro CG is shipping now, Calypto said. It runs on Linux and is a no-cost upgrade for existing customers, the company said.