Here is the abstract you requested from the DPC_2009_3D technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Thermal Test Vehicle Integration of 3-D VLSI

Keywords: 3-D, Thermal Management, VLSI

The University of Arkansas is developing a novel 3-D packaging technology using die stacking. In order to develop the process and demonstrate the heat removal capability of fluid-cooled channels, a 4-layer thermal test vehicle including heat dissipation resistors, meander temperature sensing resistors and vaious daisy chains has been designed.
TSVs are etched and filled with copper to provide electrical connections between the two faces of a process wafer. Copper posts and dams are plated up and used to provide electrical connections and mechanical support between each pair of layers. Micro-fluid channels for cooling are formed between silicon layers. Coolant is circulated through the fluid channels to remove heat from individual dies. A flip chip bonder is utilized for stacking dies using copper/tin intermetallic connections.
Prototype fabrication is in process. In order to achieve stackable ultrathin chips, the TSV technology and copper dam and post technology developed previously have been adapted and integrated. Wafer bonding, thinning and debonding technology have been improved for reasonably good yield. Finally, the structure will be mounted with manifolds and coolant will be circulated in the system so that thermal and reliability tests can be performed. Up-to-date results will be presented at the conference.