Intel shows off 10nm Cannon Lake wafer at Beijing event

Intel has offered an update on its long-delayed 10nm process node, promising that it'll be worth the wait and 'a full generation ahead of other "10nm" technologies' in at least two important metrics: Transistor density and transistor performance.

Intel has since been working hard on bringing its now two-year-delayed 10nm node to life, and earlier this year claimed to have cracked the problem with the promise that 2015's delayed 10nm Cannon Lake parts would hit shop shelves before the end of the year. Now, the company is doubling-down on its promises for the 10nm node: At the Intel Technology and Manufacturing Day in Beijing yesterday the company showed off a Cannon Lake wafer, based on the company's 10nm node, for the first time.

'Intel manufacturing processes advance according to Moore’s Law, delivering ever more functionality and performance, improved energy efficiency and lower cost-per-transistor with each generation,' claimed Stacy Smith, Intel's group president of manufacturing, operations and sales, at the event. 'We are pleased to share in China for the first time important milestones in our process technology roadmap that demonstrate the continued benefits of driving down the Moore’s Law curve.'

As well as showing off proof that it can build 10nm Cannon Lake parts - or, at least, put them on a wafer - the company made bold claims about the superiority of its delayed 10nm node compared to the competition. In a presentation by Intel senior fellow Mark Bohr the company claimed the 10nm node on which Cannon Lake is based is 'a full generation ahead of other "10nm" technologies' in both transistor density and performance. At the same time, Bohr proposed a new standardised transistor density metric which, he claimed, would 'clear up the node naming mess' that sees very different technologies from competing companies all referred to as 10nm.

Other technologies and products discussed at the event include updates on Intel's 22FFL process node, a 22nm FinFET process aimed at low-power devices, plans for field-programmable gate arrays (FPGAs) based on the same 10nm process node as Cannon Lake, dubbed Falcon Mesa, and the demonstration of an Intel-manufactured 10nm ARM Cortex-A75 test chip wafer running in excess of 3GHz. The company also unveiled a 64-layer triple-level cell (TLC) 3D NAND solid-state drive (SSD), which it says will be targeted at data centres now with more broad availability by the end of the year.