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PCI-SIG releases the PCIe 2.0 spec

The PCI Express Base 2. you.

The PCI-SIG announced today that final version of the PCI Express Base 2.0 Specification is now out and available to members. Version 0.9 of the spec was released back in October of 2006, and today's release of the final version means that the spec is officially ready for prime time. Indeed, pretty soon it'll be time for me to dust off the old PCI Express article and update to v2.0.

PCIe 2.0 adds a number of enhancements that make the spec more useful for the kinds of coprocessor hosting that PCIe is increasingly being pressed into service for. At the top of the list is increased signaling speed (5GHz) that results in increased per-link bandwidth. Specifically, each lane doubles from 2.5 GT/s under the PCIe 1.1 spec to 5 GT/s under the 2.0 spec, with the result that a PCIe 2.0 x16 link has a peak bandwidth of 16 GB/s.

The new spec also supports a number of features at the protocol level, some of which give the operating system more control over the PCIe link. For instance, the new spec gives the OS the ability to dynamically adjust the speed of a link, and to receive notifications when the link speed and width change.

Devices based on the PCIe 2.0 spec are backwards compatible with devices based on the 1.0 and 1.1 specifications. We should see products that support the new spec start trickling out at some point later this year, now that the spec is finalized. As was the case with the original introduction of PCIe, graphics cards will be the first products to make use of PCIe 2.0, as motherboard and chipset makers replace the current generation of x16 PCIe 1.1 links with PCIe 2.0 links intended for GPUs.

When you combine the new generation of DirectX 10-compatible graphics cards with the extra bandwidth that PCIe 2.0 affords, you get a recipe for another leap in PC graphics sometime in the second half of 2007.