Moore’s Law: Will Lack of R&D Funding Kill It?

That very issue was one of the key "take aways" from last week’s ISS. What I heard from a variety of speakers is this:

A massive restructuring is underway that will leave only a handful of companies producing devices at the leading edge. Bob Johnson, VP of research at Gartner, predicts that by 2014 there will be only 10 companies operating at the leading edge: 1-2 nonmemory IDMs, 4-5 memory companies, and 3 foundries.

Hundreds of other companies will still be producing devices at somewhat larger dimensions, but the fragmentation is widening between those that can afford the most advanced-node technology, and those who can’t. "Those two segments are radically different and they’re going to get even more different," said Handel Jones, CEO of International Business Strategies, also speaking at the Industry Strategy Symposium. Despite that rift there’s still growth for those who choose not to push ahead to the advanced nodes. In fact, he expects to see capacity shortages for some of these lagging feature dimensions in the next few years.

Johnson described several economic forces at work that could derail Moore’s Law due to lack of R&D funding. One factor is the number of major IDMs that are moving from a full manufacturing position to an asset-light or fabless position. “The number of companies that are actually participating in the leading edge is shrinking,” Johnson said. “If you look forward about five years, you come to the very realistic assumption that there are going to be at most 10 companies doing leading edge manufacturing. By leading edge, I mean the two most advanced process nodes. Right now, that would be 45nm and 32nm. By 2014, it would be 22nm and 15nm. How many of those companies will be operating at the absolute leading edge, in other words 15nm, by 2014? Just cut those numbers in half,” he said. “You’ve really got about five companies out there that are really going to be seriously considering manufacturing in accordance with the Moore’s Law pace.”

Jones also predicts significant changes over the next 5-10 years. By the time the 22nm generation rolls around in 2012, he predicts there will be only three IDMs: Intel, Samsung and STMicroelectronics, and in terms of foundries working at 22nm, he thinks TSMC and GobalFoundries (which recently acquired Chartered Semiconductor) will be around. The fate of Samsung, which recently entered the foundry business, will depend on the success of their model, he said, adding that SMIC is an unlikely participant, and the capacity of UMC is “unclear.”

A similar situation exists in the memory market. “What we see today is a number of companies in the DRAM, NAND flash and NOR flash businesses, but if you look out two to five years, you’re going to have one or two companies and that’s it,” Jones said. Samsung will again be a major player, with a projected 50% of the DRAM market and 60% of the NAND flash market. “What we see now is Samsung moving ahead very rapidly and the others falling behind. The gap is widening,” he said. Toshiba is a distant second, at least in NAND flash, where Jones expects them to garner 30% of the market.Johnson said the higher costs of leading edge technology also means that companies must target only very large markets. At the 32nm mode, he said those markets needed to be about $2 billion. “The idea of being able to build a leading edge device that might target a $100 million market… those days are gone,” he said. “If we look at our current forecast and take it out to 2013, there are really only about five major markets that qualify for the greater than $2 billion TAM. That’s PCs, cell phones, video games, TVs and set-top boxes. That includes all the new things we’re seeing coming out of the CES show,” Johnson said.

Another trend that affects the ability of the equipment industry to fund R&D is capital intensity. Long term the trend in capital intensity—simply capital spending as a percent of revenue—has been declining, Johnson noted. In part, this is because people know how to build fabs more efficiently, but it’s also because the industry’s growth rate is declining. Once at 17% CAGR, Johnson said we’re realistically looking at a long term growth rate in the 5%-7% range. “It takes less capital to keep that going,” he said.

One of the main drivers behind this consolidation is price pressure. “The semiconductor industry, even though it’s recovering from a revenue perspective, is not healthy from a profit perspective,” Jones said. “Today, a relatively small number of semiconductor companies are making good profits. The market in 2010 will be comparable to the market in 2007 from a revenue perspective. Unit volumes though are up about 20-30%, so we’ve had an erosion of prices by 20%-30%. We’ve had some efficiency improvements but we’ve also seen a loss in gross profit margin and also a loss in operating income.”

Jones believes this will result in “a significant restructuring” in which “only the top two or three companies in specific markets will survive." The drive from 32nm to 28nm will force additional consolidation, he added.

A similar type of consolidation is seen on the front-end semiconductor manufacturing equipment front (less so on the back-end test and packaging side). Gartner’s Johnson said that equipment suppliers will have “lost” about $116 billion in revenue between 2007 and 2014 due to the recession and record low levels of capital expenditures. This equates to about $17.4 billion in lost R&D.

This is happening at the same time when R&D costs are escalating due to a demand for continued shrinks, more advanced device structures and even a move to 450mm wafers (which continues to be a hotly debated topic).

Many believe this consolidation and funding gap has the potential to stop Moore’s Law dead in its tracks, perhaps at the 22nm generation. Jones said that the benefits of scaling, which he measures in terms of cost per gate trend, are not what they once were. The move to 90nm achieved a big cost decline in cost per gate, in part due to the transition from 200mm to 300mm wafers and associated productivity gains, he said. The move to 65nm brought “a fairly reasonable” decline, and then a small decline with 45nm and 32nm transitions. With 22nm, however, he said there actually will be an increase in the cost per gate — and without a reduction in cost per gate, many will question the need to move to the small feature dimension. "When you look at what applications drive the technology, if it is low-power (such as for handsets), that’s a cost-driven market," Jones said. "Maybe going to a smaller dimensions will not give you the required payback.”

As a result of increasing costs, Jones also sees a reduction in the number of designs at advanced technology nodes. He said for a 28nm design, the costs can easily be in the $100M-150M range, and if you add software it can be up to $200M. “If you look at the normal metrics for R&D, you need 10× revenue from a production point of view. You then need $1.5 billion in revenue — and of course that happens in only a small number of products,” he said. “After 22nm, the technology gets even tougher. The two year cycle is fading fast.”

Bob Bruck, VP of Intel’s technology and manufacturing group and GM of technology manufacturing engineering, also spoke at ISS, adding that the number of fabs built each year has been declining: less than ten are expected to be built in 2011 and 2012, respectively (the majority of those being 300mm fabs). The cost of a fab is about $4B, a pilot line costs $1B-$2B, and an advanced R&D process team can cost $500M-$1B. “You’ve got to have a large TAM to support this kind of investment, and you’ve got to have a pretty good gross margin on the product base to support this kind of investment,” he said. "These types of dynamics are shaping this consolidation effect."

Johnson adds that "the guys that are making the chips" are facing an increasingly difficult decision: ‘Do I go with the leading edge or don’t I?’ He said we’ve been seeing the effects of that decision for some time. "Looking at the lag between when the first company beings producing at a given node – and of course that has always been Intel – and when 10% of the AASP design starts have occurred at the node. The 10% is a fairly arbitrary number but it indicates a fairly reasonable change for actually getting volume production happening at that node. At 130 nm, the industry was in lock-step. By 90/65 nm, we have a two year lag for the AASPs which largely determines foundry production to start getting their designs in behind the industry leaders. By 32 nm, we’re thinking that’s going to be a four year lag. If the foundry sweet spot, and the sweet spot of the AASPs and the ASICs that addresss some of the key consumer markets and mobile markets are actually be going to be running behind the leading edge. They’re not going to be leading edge when they start getting good volume," Johnson said.

Conclusion: Within five years, the ability of the industry to stand the traditional Moore’s Law technology curve will depend not upon the laws of physics. The real question is how do we pay for it and how to fund the necessary R&D to get there.

One bright spot: through-silicon vias (TSV) and 3D integration, which have the ability to increase functionality equivalent to a move to a new technology node. “In the past we were very cautious on TSV. We’ve become a lot more positive,” Jones said.

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