I have purchased a 7" TFT LCD with CPLD controller (Sainsmart as it turns out. )

I have the display connected directly to a DUE and have changed the model parameter in the sketch to :- UTFT myGLCD(CPLD,38,39,40,41);

I have the latest version of the UTFT library and uploaded the "UTFT_Demo_800X480".

The display "works" but has artifacts left from the previous screens and results in blotchy and incorrect colours displayed.

The only other similar instance I could find was at the link below.http://forum.arduino.cc/index.php?topic=290406.0

I have tried many different power supplies and these have little to no effect.I am currently using a BK precision 15A bench power supply.The touch screen and SD control wires are not connected to the DUE.

I am suspecting it is a timing issue with the signal or simply, the screen is junk.

I have purchased a 7" TFT LCD with CPLD controller (Sainsmart as it turns out. )

I have the display connected directly to a DUE and have changed the model parameter in the sketch to :- UTFT myGLCD(CPLD,38,39,40,41);

I have the latest version of the UTFT library and uploaded the "UTFT_Demo_800X480".

The display "works" but has artifacts left from the previous screens and results in blotchy and incorrect colours displayed.

The only other similar instance I could find was at the link below.http://forum.arduino.cc/index.php?topic=290406.0

I have tried many different power supplies and these have little to no effect.I am currently using a BK precision 15A bench power supply.The touch screen and SD control wires are not connected to the DUE.

I am suspecting it is a timing issue with the signal or simply, the screen is junk.

Any help would be appreciated.

I need to point out that the author of the UTFT libraries does not support the use of his libraries on any Sainsmart nor Mcufriends.com products. They are using the libraries in violation of the licenses.

Sheild? Not really, hand wired perf board. I have been over this many times as I suspected it to be the problem. Currently this is the third iteration, having gone from ribbon cable to this board. wires are <50mm long. Without any change in the display output behavior.

Thank you for the information.I still would like to get a link to the display you bought, but I understand it might no longer be available.A photo of the backside of your display might also have helped.

You report the marks on the PCB, and no marks of any chips on the PCB, so the controller may be hidden on the display panel or on the flexible connection part.

As you get output on your display, you seem to have selected the correct controller in UTFT, and I can look there and google the marks on your PCB to find out more.

CPLD controller : Complex Programmable Logic Device is a general name, the specific CPLD display controller used in these displays would need more searching.

I do not know if the clock speed of the Due can be easily reduced, but it may be easy to increase the length of the write pulse to the display in UTFT. I will take a look, and report later.

Make sure you have uncommented line 4 in HW_ARM_defines.h, if you use a wiring that corresponds to the CTE shield.You can increase the WR pulse length in UTFT\hardware\arm\HW_ARM_defines.h://#define pulse_low(reg, bitmask) cbi(reg, bitmask); sbi(reg, bitmask);#define pulse_low(reg, bitmask) cbi(reg, bitmask); cbi(reg, bitmask);cbi(reg, bitmask);sbi(reg, bitmask);

@david_prentice

David,

if you happen to look into this topic, you could help with your broader knowledge, now that some information is available.

Jean-Marc

No personal message please; any question may be useful for other users. Use code tags for code. Make links clickable with URL tags. Provide links to the product in question.

I did get a CPLD "running" with MCUFRIEND_kbv (remotely. ghlawrence testing on his hardware)From memory, the CPLD is unintelligent. You can't change rotations etc in hardware.

Most CPLDs will simply provide a 8080-16 parallel interface to your Due.Accept a tiny number of commands.

I have no idea what screen or CPLD is involved. The OP has not provided any photos of the pcb or links to the sale item.

If the OP can display something on the screen, the 8080-16 driver must be correctly wired.You can slow down the UTFT pulse_low() operation. Most modern TFT controllers have a minimum 66ns Write cycle. The actual low pulse is 15ns.The SSD1963 has a 33ns WR cycle. I would expect a CPLD to be at least 66ns.

Yes, you do have to worry about timing on a fast Cortex-M4 or possibly a Due M3.

An 84MHz Due has a 11.9ns clock cycle. I would be amazed if a Due can achieve cbi() in one clock cycle.On the other hand, if I had to use two cbi() for an SSD1963 perhaps the Cortex-M3 output driver does achieve 11.9ns. (the SSD1963 requires minimum tPWLW=12ns pulse width, tDSW=4ns is not significant)

I would never expect UTFT to have timing problems. Perhaps the Compiler has done something new.And we seem to be talking about 0.1ns i.e. 100 picosec !! Pcb track length becomes significant.