The Cisco ATM Port Adapter supports up to 8192 virtual connections. Any combinations of virtual circuit and virtual path can be supported up to a maximum number of 8191 virtual circuit/virtual path combinations. These virtual circuits can be either PVCs that are created manually or SVCs created through point-to-point and point-to-multipoint UNI signaling.

These capabilities contribute to the high-performance throughput, and specifically benefit applications that require many virtual circuits, such as in DSL applications and in a campus LAN.

Advanced Traffic Management

Advanced traffic management mechanisms in the Cisco ATM Port Adapter architecture allow for the support of bursty client/server traffic, while supporting applications that require guaranteed or best-effort service.

Designed for ATM virtual circuits that need a static amount of bandwidth that is continuously available for the duration of the active connection

Per-Virtual Circuit and Per-Virtual Path Traffic Shaping

Traffic shaping is a function typically provided on ATM edge devices to ensure that bursty traffic conforms to a predetermined contract. Specifically, traffic shaping ensures that traffic from one virtual circuit does not adversely impact another, resulting in data loss. This function is very important when connecting to an ATM WAN or public ATM network, especially when the ATM switches enable traffic policing that discards all traffic that exceeds the predetermined contract at the ingress of the ATM network.

The Cisco ATM Port Adapter supports traffic shaping on a per-virtual circuit basis and per-virtual path basis. Supporting traffic shaping in hardware means that there is no performance degradation when shaping is enabled. Providing traffic shaping on a per-virtual circuit and per-virtual path basis allows flexibility and control over every virtual circuit and virtual path configured.

Depending on the selected ATM service class, the Cisco ATM Port Adapter supports highly configurable parameters such as peak cell rate (PCR), sustainable cell rate (SCR), maximum burst size (MBS), and minimum cell rate (MCR). These parameters can be defined based on the specific bandwidth requirements of an individual virtual circuit, as needed for a specific application.

The Cisco ATM Port Adapter hardware shapes the virtual circuit to the specific parameters using a wheel-based scheduling algorithm to ensure fairness across the ATM interface. If two cells compete for the same time slot, the virtual circuits, by default, are prioritized in the following order (starting with highest priority):

0 CBR, control

1 AAL5 or AAL2 VoATM virtual circuit (any service category)

2 VBR-rt

3 VBR-nrt

4 ABR

5 UBR, UBR+

Prioritizing the virtual circuits in this manner ensures that the high-priority and guaranteed traffic have precedence over the best-effort traffic. It is also possible to configure a custom prioritization scheme on a per-virtual circuit basis.

To provide further flexibility, the Cisco ATM Port Adapter allows each of these parameters to be set over a wide range of small increments.

Supported Traffic-Shaping Granularity - OC-3, DS3, and E3 Versions

Parameter

Range

Increments

PCR

56 kbps to line rate

2.29-kbps increments for OC-3c/STM-1, 0.674-kbps increments for DS3, and 0.515-kbps increments for E3

SCR

56 kbps to line rate

2.29-kbps increments for OC-3c/STM-1, 0.674-kbps increments for DS3, and 0.515-kbps increments for E3

MBS

1 to 65535

One cell

High-Performance Architecture

The Cisco ATM Port Adapter is based on advanced dual segmentation and reassembly (SAR) architecture. One SAR processor is dedicated for transmission and one for reception. Each SAR supports AAL5 ATM adaptation for high-performance data applications. Many of the Cisco ATM Port Adapter advanced traffic management features mentioned previously are a direct result of this SAR design.

The Cisco ATM Port Adapter also includes a large amount of buffer memory locally on the port adapter, a feature unique to the Cisco ATM Port Adapter. This buffer memory is partitioned on a per-virtual circuit and per-virtual path basis, providing better overall performance and the ability to absorb large bursts of traffic. This design ensures that bursty traffic from one virtual circuit does not prevent another virtual circuit from being serviced, an issue that could be crucial for any service provider ATM network.

This new feature provides the ability to keep track of the bandwidth used by a virtual circuit or virtual path on a per-interface basis. It prevents the oversubscription of the ATM link and is configurable by the user.

The total bandwidth allocated on the interface is tracked by aggregating the values specified for sustained cell rate for each virtual circuit. Whenever a new virtual circuit is requested, the requested rate is checked against the available rate to ensure that the available bandwidth is not exceeded. This check can be disabled if link-over subscription is desired.

ATM Layer Connection Management

OAM cells are used for ATM layer end-to-end link management messages. This ensures that the remote end of the connection is alive and functioning. Support is provided for both OAM F4 and F5 flows. During segmentation, the OAM cells have the highest priority, and they are transmitted ahead of other queued data. During reassembly, the OAM traffic is routed to a global OAM receive buffer pool of 512 64-byte buffers.

The Cisco ATM Port Adapter supports the Cisco IOS Software IP QoS-to-ATM CoS (IP-to-ATM CoS) feature. This implements a solution for coarse-grained mapping of quality-of-service (QoS) characteristics between IP and ATM. These features ensure consistent QoS between IP and ATM interworked networks. IP/ATM networks can now offer different service classes across the entire WAN, not just the routed portion. Critical applications can be given higher classes of service during periods of high network usage and congestion. Great QoS flexibility becomes available for more important traffic and user types.

Per-virtual circuit QoS features enable you to apply advanced queuing and bandwidth management functionality such as Class-Based Weighted Fair Queuing (CBWFQ), Weighted Random Early Detection (WRED), or low-latency queuing (LLQ) to an individual virtual circuit. Also supported is IP-to-ATM CoS mapping using the virtual-circuit bundling feature that allows you to divide traffic on different virtual circuits depending on the desired CoS.

ATM-to-Frame Relay Interworking

The ATM-to-Frame Relay service interworking function allows communication between a Frame Relay end user and an ATM end user. It is based on the FRF.8 implementation agreement, which specifies that a Frame Relay end station may communicate with an ATM end station provided that there is a router performing the specifications given in FRF.8 in the software between the two end stations.

This feature enables delay-sensitive real-time packets and packets that are not real-time data to share the same link by fragmenting the long data packets into a sequence of smaller data packets (fragments). The fragments are interleaved with the real-time packets. On the receiving side of the link, the fragments are reassembled and the packet reconstructed. This method of link fragmenting and interleaving (LFI) helps guarantee the appropriate QoS for the real-time traffic.