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AR# 21856

Spartan-3 - SRL16, 32, and 64 Timing. How do I analyze these paths?

Description

The Spartan-3 DC and Switching Characteristics Data Sheet does not specify minimum pulse width requirements for the SRL16. What speeds can the SRL16, SRL32, and SRL64 handle and how do I perform a timing analysis on SRLs?

Solution

SRL16

Timing Analyzer does not directly report a timing analysis on the SRL16. However, there is a minimum pulse width check that is carried out when Timing Analyzer is run to make sure the design meets the hardware requirement. The minimum pulse widths check are as follows:

Speed Grade -> - 5 - 4

Pulse width low of the CLK 0.842 0.968

# Minimum pulse width low for the clock to the shift

# register or the LRAM.

#

Pulse width high of the CLK 0.842 0.968

# Minimum pulse width high for the clock to the shift

# register or the LRAM.

#

If these pulse width checks are not met, there will be a warning reported at the top of the Timing Analyzer Report.

SRL32

When the SRL32 is used with the dedicated Q15 routing between the two SRL16s, Timing Analyzer does not report this path in the PERIOD analysis. This is the case with most other dedicated routes within a SLICE as well, not just the SRL16 to SRL16 (Q15 output). Knowledge about this path might be desired for timing analysis, so we do have a minimum pulse width check as mentioned above. The minimum pulse width check accounts for the first lut to second lut setup for the internal lut-to-lut routing. The same values are used for the pulse width check as is used for the SRL16, shown above. If these pulse width checks are not met, there will be a warning reported at the top of the Timing Analyzer Report.

SRL64

The limitation on the SRL64 is going to be the Slice-to-Slice routing. This path IS analyzed in Timing Analyzer. Doing a PERIOD analysis on the design will confirm if your SRL64 can meet your desired speed.