microprocessor architecture and programming

MICRO
PROCESSOR ARCHITECTURE AND MICROPROGRAMMING

Note: To run
examples or practice, please use 8086 emulator, WinAsm ect. You
can search from search engines.

The word micro is used in
microscopes, microphones, microwaves, microprocessors, microcomputers,
microprogramming, microcodes etc. It means small. A microprocessor is an
example of VLSI bringing the whole processor to a single small chip. With the
popularity of distributed processing, the emphasis has shifted from the single
mainframe system to independently working workstations or functioning units
with their own CPU, RAM, ROM and a magnetic or optical disk memory. Thus, the
advent of the microprocessor has transformed the mainframe environment to a
distributed platform.

Basic components
of a microprocessor:

·ROM
stores the boot program.

·The
path from CPU to devices is through Buses. But what would be the size of these
Buses?

Bus
Sizes

1. The Address bus: 8085
microprocessor has
16
bit lines. Thus, it can access up to 2^16 = 64K Bytes. The
address bus of 8086 microprocessor has a 20 bits address bps. Thus it can
access up to 2^20 = 1M Byte size of RAM directly.

2. Data bus is the number of bits
that can be transferred simultaneously. It is 16 bits in 8086.

Microprocessors

The microprocessor is a complete
CPU on a single chip. The main advantages of the microprocessor are:

·compact
but powerful

·Can
be micro programmed for user's needs;

·easily
programmable and maintainable due to small size; and

·Useful
in distributed applications.

A microprocessor
must demonstrate:

·More
throughput

·More
addressing capability

·Powerful
addressing modes

·Powerful
instruction set

·Faster
operation through pipelining

·Virtual
memory management.

However, RISC machine do not
agree with above principles. Some of the most commercially available
microprocessors are: Pentium, Xeon, G4 etc.

The assembly language for more
advanced chips subsumes the simplest 8086/ 8088 assembly
language. Therefore, we will confine our discussions to Intel 8086/8088 assembly
language. You must refer to the further readings for more details on assembly
language of Pentium, G4 and other processors. All microprocessors execute a
continuous loop of fetch and execute cycles.

while (1)

{

fetch (instruction);

execute (using date);

}

STRUCTURE OF 8086 CPU

The 8086 microprocessor
consists of two independent units:

1. The Bus Interface unit, and

2. The Execution unit.

The
CPU of INTEL 8086
Microprocessor

The word independent implies that
these two units can function parallel to each other. In other words they may be
considered as two stages of the instruction pipeline.

The Bus Interface Unit

The BIU (Bus Interface Unit)
primarily interacts with the system bus. It performs almost all the activities
relating to fetch cycle such as:

·Calculating the physical address of the
next instruction

·Fetching the instruction

·Reading or writing data memory or 110 ports
from memory or Input1 Output.

The instruction1 data is then
passed to the execution unit. This BIU consists of:

(a) The Instruction
Queue

The instruction queue is used to
store the instruction "bytes" fetched. Please note two points here:
that it is (1) A Byte (2) Queue. This is used to store information in byte
form, with the underlying queue data structure. The advantage of this queue
would only be if the next expected instructions are fetched in advance, thus,
allowing a pipeline of fetch and execute cycles.

(b) The Segment
Registers

These are very important
registers of the CPU. Why?
We
will answer this later. In 8086 microprocessor, the memory is a byte organized,
that is a memory address is byte address. However, the number of bits fetched
is 16
at
a time. The segment registers are used to calculate the address of memory
location along with other registers. A segment register is 16 bits
long.

The BIU contains four sixteen-bit
registers, viz., the CS: Code Segment, the DS: Data Segment, the SS: Stack
Segment, and the ES: Extra Segment. But what is the need of the segments:
Segments logically divide a program into logical entities of Code, Data and
Stack each having a specific size of 64 K. The segment register holds the
upper 16 bits of the starting address of a logical group of memory, called the
segment. But what are the advantages of using segments? The main advantages of using segments
are:

·The addresses that need to be used, in
programs are re-locatable as they are the offsets. Thus, the segmentation
supports re-locatability.

·Although the size of address is 20 bits,
yet only the maximum segment size, that is 16 bits, needs to be kept in
instruction, thus, reducing instruction length.

The 8086 microprocessor uses
overlapping segments configuration. The typical memory organization for the
8086 microprocessor may be as per the following diagram.

Logical
Organization of Memory in INTEL 8086 Microprocessor

Although the size of each segment
can be 64K,
as
they are overlapping segments we can create variable size of' segments, with
maximum as 64K. Each segment has a specific function. 8086 supports the
following segments:

As per model of assembly program,
it can have more than one of any type of segments. However, at a time only four
segments one of each type, can be active. The 8086 supports 20 address lines,
thus supports 20 bit addresses. However, all the registers including segment
registers are of only 16 bits. So, how may this mapping of 20 bits to 16 bits
is performed? Let us take a simple mapping procedure:

The top four hex digits of
initial physical address constitute segment address. We can add offset of 16
bits(4 Hex digits) from 0000h to FFFFh to it. Thus, a typical segment which
starts at a physical address 10000h will range from 10000h to 1FFFFh. The
segment register for this segment will contain 1000h and offset will range from
0000h to FFFFh. But, how will the segment address and offset be added to
calculate physical address? Let us explain using the following examples

The value of the Instruction
Pointer, holding address of the instruction = 1234h

The value of the code segment
register (CS) =
448Ah

Physical address of the
instruction

Physical Address = CS
(Hex) x
16
+ IP

(c) Instruction
Pointer

The instruction pointer points to
the offset of the current instruction in the code segment. It is used for
calculating the address of instruction as shown above.

Execution Unit (EU)

Execution unit performs all the
ALU operations. The execution unit of 8086 is of 16 bits. It also contains
the control unit, which instructs bus interface unit about which memory
location to access, and what to do with the data. Control unit also performs decoding
and execution of the instructions. The EU consists of the following:

(a)! Control
Circuitry, Instruction Decoder and ALU

The 8086 control
unit is primarily micro-programmed control. In addition it has an instruction
decoder, which translates an instruction into sequence of micro operations. The
ALU performs the required operations under the control of CU which issues the
necessary timing and control sequences.

(b) Registers

All CPUs have a defined number of
operational
registers.
8086
has
several general purposes and special purpose registers.

REGISTER SET OF
8086

The 8086 registers
have five groups of registers. These groupings are done on the basis of the
main functions of the registers. These groups are:

General Purpose
Register

8086 microprocessors
have four general purpose registers namely, AX, BX, CX, DX. All these registers
are 16 - bit
registers. However, each register can be used as two general purpose byte
registers also. These byte registers are named AH and AL for AX, BH and
BL for BX, CH and CL for CX, and DH and DL for DX. The H in register name
represents higher byte while L represents lower byte of the 16 bits registers.
These registers are primarily used for general computation purposes. However,
in certain instruction executions they acquire a special meaning.

AX register
is also known as accumulator. Some of the instructions like divide, rotate,
shift etc. require one of the operands to be available in the accumulator.
Thus, in such instructions, the value of AX should be suitably set prior to the
instruction.

BX
register is mainly used as a base register. It contains the starting base
location of a memory region within a data segment.

CXregister
is a defined counter. It is used in loop instruction to store loop counter.

DX register
is used to contain I10 port address for 110 instructions.

Segment
Registers

Segment Registers are used for
calculating the physical address of the instruction or memory. Segment
registers cannot be
used
as byte registers.

Pointer and
Index Registers

The 8086 microprocessor has three
pointer and index registers. Each of these registers is of 16 bit and cannot be
accessed byte wise. These are Base Pointer (BP), Source Index (SI) and
Destination Index (DI). Although they can be used as general purpose registers,
their main objective is to contain indexes. BP is used in stack segment, SI in
Data segment and DI
in
Extra Data segment.

Special
Registers

A Last in First
Out (LIFO) stack is a data structure used for parameter passing, return address
storage etc. 8086 stack is 64K bytes Base of the stack is pointed to by the
stack segment (SS) register while the offset or top of the stack is stored in
Stack Pointer (SP) register. Please note that although the memory in 8086 has
byte addresses, stack is a word stack, which is any push operation, will occupy
two bytes.

Flags Register

A flag represents
a condition code that is 0 or 1. Thus, it can be represented using a flip-
flop. 8086 employs a 16-bit flag register containing nine flags. The following
table shows the flags of 8086.

Conditional Flags represent
result of last arithmetic or logical instruction executed. Conditional flags
are set by some condition generated as a result of the last mathematical or
logical instruction executed. The conditional flags are:

Flags

Meaning

Comments

CF

Carry Flag

1 if there is a carry bit

PF

Parity Flag

1 on even parity 0 on odd parity

AF

Auxiliary Flag

Set (1) if auxiliary
carry for BCD occurs

ZF

Zero Flag

Set if result is
equal to zero

SF

Sign Flag

Indicates the sign of
the result (1 for minus , 0 for plus)

OF

Overflow Flag

set whenever there is an overflow of the result

Control flags, which are set or
reset deliberately to control the operations of the execution unit. The control
flags of 8086 are as follows:

Flags

Meaning

Comments

TF

Single step trap flag

Used for single stepping through
the program

IF

Interrupt Enable Flag

Used to allow/inhibit the
interruption of the program

DF

String direction
Flag

Used with string
instruction

INSTRUCTION SET
OF 8086

After discussing the basic
organization of the 8086 micro-processor, let us now provide an overview of
various instructions available in the 8086 microprocessor. The instruction set
is presented in the tabular form. An assembly language instruction in the 8086
includes the following:

Label:
Op-code Operand(s); Comment

For example, to add the content
of AL and BL registers to get the result in AL, we use the following assembly
instruction.

NEXT: ADD AL,BL ;AL + BL

Please note that NEXT is the
label field. It is giving an identity to the statement. It is an optional
field, and is used when an instruction is to be executed again through a LOOP
or GO TO. ADD is symbolic op-code, for addition operation. AL and BL are the
two operands of the instructions. Please note that the number of operands is
dependent upon the instructions. 8086 instructions can have zero, one or two
operands. An
operand
in 8086 can be:

1.A register

2.A memory location

3.A
constant called literal

4.A label.

Comments in 8086 assembly start
with a semicolon, and end with a new line. A long comment can be extended to
more than one line by putting a semicolon at the beginning of each line.
Comments are purely optional, however recommended as they provide program
documentation. In the next few sections we look at the instruction set of the
8086 microprocessor. These instructions are grouped according to their
functionality.

Data Transfer
Instructions

These instructions are used to
transfer data from a source operand to a destination operand. The source
operand in most of the cases remains unchanged. The operand can be a literal, a
memory location, a register, or even an 110 port address, as the case may be.
Let us discuss these instructions:

Note: If you want to run these
examples, please use 8086 emulator, WinAsm ect. You can search
from search engines.

Note: Be careful check “;”.
Semicolon means comments. All comments are written after Semicolon.

MNEMONIC

DESCRIPTION

EXAMPLE

MOV des, src

DES ←
SRC; Both the operands should be byte or word. SRC operand can be register,
memory location or an immediate operand DES can be register or memory
operand. Restriction: Both source and destination cannot be memory operands
at the same time.

MOV
CX,037AH

MOV
AX,BX

PUSH operand

Pushes the
operand into a stack. SP ← SP-2;

Value [TOS] ← operand.
Initialize stack segment register, and the stack pointer properly before
using this instruction. No flags are affected by this instruction. The
operand can be a general purpose register, a segment register, or a memory
location. Please note it
is
a word stack and memory address is a byte address, thus, you decrement by 2
Also you decrement as SP is initialized to maximum offset and condition of
stackful is a zero offset (so, it is a reversed stack)

PUSH BX

; decrement
stack pointer

; by; two, and
copy BX to

; stack.

; decrement
stack pointer

; by two, and
copy

; BX to stack

POP des

POP a word
from stack. The des can be a general-purpose register, a
segment register (except for CS register), or a memory location. Steps are:

des ← value [TOS]

SP ← SP+2

POP AX

; Copy content
for top

; of stack to AX

XCHG des, SRC

Used to
exchange bytes or words of SRC and des. It requires at least one of the
operands to be a register operand. The other can be a register or memory
operand. Thus, the instruction cannot exchange two memory locations directly.
Both the operands should be either byte m e or word type. The segment
registers cannot be used as operands for this instruction.

XCHG DX,AX

XLAT

Translate a
byte in AL using a table stored in the memory. The instruction replaces the AL register with
a byte from the lookup table. This instruction is a complex instruction

IN accumulator,
port address

It transfers a
byte or word from specified port to accumulator register In case an 8-bit
port is supplied as an operand then the data byte read from that part will be
transferred to AL register. If a 16-bit port is read then the AX will get 16
bit word that was read. The port address can be an immediate. Operand, or
contained in DX register. This instruction does not change any flags.

IN AL,028h

OUT port address, Accumulator

It transfers a
byte or word from accumulator register to specified port. This instruction is
used to output on devices like the monitor or the printer.

LEA register source

Load
"effective address" (refer to this term in block 2, Unit 1 in addressing
modes) of operand into specified 16 bit register. Since, an address is an
offset in a segment and maximum can be of 16 bits, therefore, the
register can only be a 16-bit register. LEA instruction does not change any
flags. The instruction is very useful for array processing.

LEA BX, PRICES

; Assume PRICES
is

; an array in
the data

; segment

LDS des-reg

It
loads data segment register and other specified register by using consecutive
memory locations.

LDS
SI, DATA

; DS ←
content of memory

; location
DATA &

; DATA + 1

; SI content of

; memory
locations

;DATA+2&DATA+

: 3

LES des-reg

It
loads ES register and other specified register by using consecutive memory
locations. This instruction is used exactly like the LDS except in this case
ES &
other
specified registers are initialized.

LAHF

Copies
the lower byte of flag registers to AH. The instruction does not change
any flags and has no operands.

SAHF

Copies
the value of AH register to low byte of flag register. This instruction is
just the opposite of LAHF instruction. This instruction has no operands.

PUSHF

Pushes
flag register to top of stack.

SP ← SP - 2;
stack [SP] ←Flag Register.

POPF

Pops
the stack top to Flag register.

Flag
register ←
stack
[SP]

SP ← SP+2

Arithmetic Instructions:

ADD

Adds
byte to byte, or word to word. The source may be an immediate operand, a
register or a memory location. The rules for operands are the same as that of
MOV instruction. To add a byte to a word, first copy the byte to a word
location, then fill up the upper byte of the word with zeros. This
instruction affects the following flags: AF, CF, OF, PF, SF. ZF.

ADD
AL,74H

; Add
the number 74H to

; AL
register, and store the

; result
back in AL

ADD
DX,BX

; Add
the contents of DX to

; BX
and store the result in ;

DX,
BX remains

; Unaffected.

ADC des, src

Add
byte +
byte
+ carry
flag, or word +
word
+ carry
flag. It adds the two operands with the carry flag. Rest all the details are
the same as that of ADD instruction.

INC des

It
increments specified byte or word operand by one. The operand can be a
register or a memory location. It can effect AF, SF, ZF, PF, and OF flags. It
does not affect the carry flag, that is, if you increment a byte operand
having OFFH, then it will result in 0 values in register and no carry flag.

INC
BX

; Add 1
to the contents of BX

INC
BL

Add 1
to the contents of BL

AAA

ASCII
adjusts after addition. The data entered from the terminal is usually in
ASCII format. In ASCII 0-9 are represented by codes 30-39. This instruction
allows you to add the ASCII codes instead of first converting them to decimal
digit using masking of upper nibble. AAA instruction is then used to ensure
that the result is the correct unpacked BCD.

ADD
AL,BL

; AL=00
1
10
10 1, ASCII 05

; BL=00
1
1
100 1, ASCII 09

; after
addition

; AL = 01
101 110, that is,

; 6EH-
incorrect

; temporary
result

AAA

; AL = 00000
100.

; Unpacked
BCD for 04

; carry
= 1, indicates

; the
result is 14

DAA

Decimal
(BCD) adjust after addition. This is used to make sure that the result of
adding two packed BCD numbers is adjusted to be a correct BCD number. DAA
only works on AL register.

; AL = 0 10
1 100 1
(59BCD)

; BL = 001 1
0101 (35BCD)

ADD
AL, BL

; AL = 10001
101 or

; 8Eh
(incorrect BCD)

DAA

; AL = 1001
0100

; =94
BCD : Correct

SUB des, src

Subtract
byte from byte, or word from word. (des ← des - src).
For subtraction the carry flag functions as a borrow flag, that is, if the
number in the source is greater than the number in the destination, the
borrow flag is to set 1. Other details are equivalent to that of the ADD
instruction.

SUB
AX, 3427h

; Subtract
342% from AX

; register,
and store the

; result
back in AX

SBB des, src

Subtract
operands involving previous carry if any. The instruction is similar to SUB,
except that it allows us to subtract two multi byte numbers because any
borrow produced by subtracting less-significant byte can be included in the
result using this instruction.

SBB
AL,CH

; subtract
the contents

; of CH
and CF from AL

; and
store the result

; back
in AL.

DEC src

Decrement
specified byte or specified word by one. Rules regarding the operands and the
flags that are affected are same as INC instruction. Please note that if the
contents of the operand is equal to zero then after decrementing the contents
it becomes 0FFH or 0FFFFH, as the case may be. The carry flag in this case is
not affected.

DEC
BP

; Decrement
the contents of BP

; register
by one.

NEG src

Negate
- creates
2's complement of a given number, this changes the sign of-a number. However,
please note that if you apply this instruction on operand having value -128
(byte operand) or -32768 (word operand) it will result in overflow condition.
The overflow (0F)
flag
will be set to indicate that operation could not be done

NEG
AL

; Replace
the number in AL
with
its 2's

; complement

CMP des,src

It
compares two specified byte operands or two specified word. The source and
destination operands can be an immediate
number, a register or a memory location. But, both the operands cannot be
memory locations at the same time. The comparison is done simply by
internally subtracting the source operand from the destination operand. The
value of source and the destination, operand is not changed but the flags are
set to
indicate
the results of the comparison.

CMP
CX,BX

; Compare
the CX register

; with
the BX register

; In
the example above, the

;CF,
ZF, and the SF flags

AAS

ASCII
adjusts after subtraction. This instruction is similar to AAA (ASCII
adjust after addition) instruction. The AAS instruction works on the AL
register only. It updates the AF and CF flags, but the OF,
PF, SF and the ZF flags remain undefined

SUB
AL,BL

AAS ;result

DAS

Decimal
adjust after subtraction. This instruction is used after subtracting two
packed BCD numbers to make sure the result is the packed BCD. DAS only works
on the AL register. The DAS instruction updates the AF, CF, SF, PF and ZF
flags. The overflow (OF) is undefined after DAS.

SUB
AL,BH

DAS

MUL Src

This
is an unsigned multiplication instruction that multiplies two bytes to
produce a word operand or two words to produce a double word such as: AX ←AL*
src (byte multiplication src is also byte)

DX or
AX ← AX * Src (word multiplication is two word). .This instruction assumes
one of the operand in AL (byte) or AX (word): the src operand can be
register or memory operand. If the most significant word of the result is
zero then, the CF and the OF flags are both made zero. The AF, SF, PF, ZF
flags are not defined after the MUL instruction. If you want to multiply a
byte with a word, then first convert - byte to a word operand.

MOV
AX,05 ;AX=05

MOV
CX,02 ;CX=02

MUL
CX

;
result in DX=0

;AX=0AH

AAM

ASCII
adjusts after multiplication. Note: Two ASCII numbers cannot be multiplied
directly. To multiply first convert the ASCII number to numeric digits by
masking of the upper nibble of each byte. This leaves unpacked BCD in the
register. AAM
instruction
is used to adjust the product to two unpacked BCD digits in AX after the
multiplication has been performed. AAM defined by the

Instruction
whiles the CF, OF and the AF flags are left undefined.

MUL BH

; AX=AL * BH=002Dh

AAM

; AX=00000100
00000101

;BCD 45 : Correct result

DIV src

This
instruction divides unsigned word by byte, or unsigned double word by word.
For dividing a word by a byte, the word is stored in AX register, divisor the
src operand and the result is obtained in AH : remainder AL: quotient. It can
be represented as: AH: Remainder AL: Quotient Similarly for double word
division by a
word
we have

DX: Remainder

AX: Quotient

A division by
zero results in run time error. The divisor src can be
either in a register or a memory operand.

; AX = 37D7h = 14295

; decimal

; BH = 97h = 15 1 decimal

DIV BH

; AX / BH quotient

;AL=5Eh=94

; decimal
Reminder AH =65h = 101

; decimal

IDIV

Divide signed
word by byte or signed double word by word. For this division the operand
requirement, the general format of the instruction etc. are all same as the
DIV instruction. IDIV instruction leaves all flags undefined.

; AL = 1 1001 01 0 = -26h =- 38 decimal

; CH = 0000001 1 = + 3h =3 decimal

; According to
the operand

; rules to
divide by a byte

; the number should
be

; present in a
word register, ;

- i.e. AX. So,
first convert

; the operand in
AL to word

; Operand. This
can be done

;by sign
extending the

; AL register,

; this makes AX

; 11111111
11001010.

IDN CH

; AXICH

;AL=
11110100=-OCH

;= - 12 Decimal

;AH=
11111110=-02H=

;-02 Decimal

; Although the
quotient is

; actually
closer to -13

; (-'12.66667)
than -12, but

; 8086 truncates
the result to give-12.

AAD

ASCII adjusts
after division. The BCD numbers are first unpacked, by masking
off the upper nibble of each byte. Then ADD instruction is used to convert
the unpacked BCD digits in AL and AH registers to adjust them to
equivalent binary prior to division. Such division will result in unpacked
BCD quotient and remainder. The PF, SF, ZF flags are updated, while the AF, CF,
and the OF flags are left undefined.

AAD

DIV
CH

CBW

Fill
upper-byte or word with copies of sign bit of lower bit. This is called sign
extension of byte to word. This instruction does no1 change any flags. This
operatio11 is done with AL register in the result being stored in
AX.

CBW
;convert signed

CWD

Fill
upper word or double word sign bit of lower word. This instruction is an
extension of the CWD

These instructions are used at the
bit level. These instructions can be used for testing a zero bit, set or
reset a bit and to shift bits across registers. Let us look into some such
basic instruction.

NOT des

Complements
each bit to produce 1's complement of the specified byte or word operand. The
operand can be a register or a memory operand.

; BX = 00 1
1 10 10 000 1 0000

NOT
BX

;BX=
11000101 1110 1111

AND des, src

Bitwise
AND of two byte or word operands. The result is des ←des
AND src. The source can be an immediate operand a register, or a
memory operand. Destination can be a register or a memory operand. Both
operands cannot be memory operands at the same time. The CF and the OF flags
are both zero after the AND operation. PF, SF and ZF area updated, AF is left
undefined.

; BH = 001 1
1010 before

AND BH, 0Fh

; BH = 0000
10 10

; after
the AND operation

OR des, src

OR
each corresponding bits of the before byte or word operands. The other
operands rules are same as AND des ←des
OR src.

; BH = 001 l
1010 before

OR BH,
0Fh

; BH = 001 1
1 1 1 1 after

XOR des,src

XOR each
corresponding bit in a byte or word operands rules are two same as AND and OR.
Des ← Des + src

;BX
=0011110101101001

; CX = 00000000
1 1
11
11 1 1

XOR
BX,CX

;BX=0011110110010110

; Please
note, that the bits in

; The
lower byte is inverted.

TEST des, src

AND the
operands to update flags, but do not change operands value. It can be used to
set and test conditions. CF and OF are both set to zero, PF, SF and ZF are all
updated, AF is left undefined after the operation.

TEST
AL,
80h

SHL / SAL des, count

Shift
bits of word or byte left, by count. It puts zero(s) in LSB(s). MSB is
shifted into the carry flag If more than one bits are shifted left, then the CF
gels the most recently moved MSB. If the number of bits desired to be shifted
is only 1, then the immediate number. 1 can be written as one of the
operands.

However,
if the number of bits desired to be shifted is more than one, then the second
operand is put in CL register.

SAL
BX,01

SHR des, count

It
shifts Bits of a byte or word to register put zero in MSB. LSB is moved into
CF.

SHR
BX,01

MOV
CL,02

SHR
BX,CL

SAR des, count

Shifts
bits of word or byte right, but it retains the value of new MSB to that of
old MSB. This also called arithmetic shift operation, as it does not change
the MSB, Which is sign bit of a number.

SAR
AL, 01

SAR
BH,01

ROL des, count

Rotate
bits of word or byte left, MSB is transferred to LSB and also to CF. The operation
is called rotate as it

Circulates
bits. The operands can be register or memory operand

ROR ds, count

Rotate bits
of word or byte
right LSB is transferred to MSB and also to CF.

ROR
BX,1

RCL des, count

Rotate
bits of words or byte left, MSB to CF and CF to LSB. The operation is
circular and involves carry flag in rotation.

RCR des, count

Rotate
bits of word or byte right, LSB to CF to MSB. This instruction rotates left

Program
Execution Transfer Instructions

These instructions are the ones
that cause change in the sequence of execution of instruction. This change can
be through a condition or sometimes may be unconditional. The conditions are
represented by flags. For example, an instruction may be jump to an address if
zero flag is set, that is the last ALU operation has resulted in zero value.
These instructions are often used after a compare instruction, or some
arithmetic instructions that are used to set the flags, for example, ADD or
SUB. LOOP is also a conditional branch instruction and is taken till loop
variable is below a certain count.

MNEMONIC

DESCRIPTION

EXAMPLE

CALL Proc 1

This function
results in a procedure1 function call. The return address is saved on the
stack. There are two basic types of CALLS. NEAR or Intra-Segment, calls: if
the call is made to a procedure in the same segment as the calling program.
FAR or Inter segment call: if the call is made to a procedure in the segment,
other than the calling program. The saved return address for NEAR procedure
call is just the IP. For FAR Procedure call IP and CS are
saved as return address. A procedure can also be called indirectly, by first
initializing some 16-bit register, or some other memory location with the new
addresses as follows.

CALL procl

CALL proc2

The new
instruction address is determined by name declaration proc 1 is a near
procedure, thus, only IP is involved. proc2 involves new CS: IP pair. On call
to proc 1 stackIP

->

IP <=
address
offset of proc 1

on call to
proc2

Stack [top]
<=CS

Stack [top]
<=IP

CS code segment
of proc2

->

IP address offset
of proc2

->

Here we assume
that procl is defined within the same segment as the calling

procedure,
while proc2 is defined in another segment. As far as the calling program is
concerned, both the procedures have been called in the same manner. But while
declaring these procedures, we declare procl as NEAR procedure and proc2 as
FAR procedure, as follows:

procl PROC
NEAR

proc2 PROC FAR

LEA BX, procl

CALL BX

RET number

It returns the
control from procedure
to calling program.

Every
CALL should be a RET instruction. A RET instruction, causes return from
NEAR or FAR procedure call. For return from near procedure the values of the
instruction pointer is restored from stack: While for far procedure the CS:
IP pair get is restored. RET instruction can also be followed by a number.

RET 6

; In
this case, 8086

; increments
the stack

; pointer
by this number

; after
popping off the 1P

; (for
new) or IP and CS

; registers
(for far) from

; The
stack. This cancels

; the
local parameters, or

; temporary
parameters

; created
by the

; Programmer.
RET

; instruction
does not

; affect
any flags.

JMP
label

Unconditionally
go to specified address and get next instruction from the label specified.
The label assigns the instruction to which jump has to take place within the
program, or it could be a register that has been initialized with the offset
value. JMP can be a NEAR JMP or a FAR jump, Just like call.

JMP
CONTINUE

; CONTINUE
is the label

; given
to the instruction

; where
the control needs

; To be
transferred.

JMP
BX

; initialize
BX with the

; offset
of the instruction,

; where
the control needs

; To
be transfer

Conditional
Jump

All
the conditional jumps follow some conditional statement, or any instruction
that affects the flag.

MOV CX. 05

MOV
BX, 04

CMP CX, BX

; this
instruction will set

; various
flags like the ZF,

; and
the CF.

JE
LABELl

; conditional
jump can

; now
be applied, which

; checks
for the ZF, and if

; it is
set implying CX =

; BX,
it makes

; a
jump to LABELl,

; otherwise
the control

; simply
falls

; through
to next

; instruction

; in
the above example as

; CX is
not equal to BX

; the
jump will not take

; place
and the next

; instruction
to conditional

;jump
instruction will be

; executed.
However, if

; JNE (Jump
if not equal

; to)
or JA (Jump if

above),
; or
JAE (Jump

above
or

; equal)
jump instructions

; if
applied instead of JE,

; will
cause the conditional

;Jump to occur

All the conditional
jump instructions which are given below are self-explanatory.

Please note that a
"/" is used to separate two mnemonics which represent the
same instruction.

JA
/ JNBE

Jump
if above / Jump if not neither below nor equal.

JAEIJNB

Jump
if above or equal Jump if not below

JB/JNAE

Jump
if below1 Jump if not above nor equal

JBE/JNA

Jump if
below or equal / Jump if not above

JC

Jump
if carry flag set

JE/JZ

Jump if equal
/ Jump
if zero flag
is
set

JNC

Jump
if not carry

JNE/JNZ

Jump
if not equal /
Jump
if zero flag is not set

JO

Jump
if overflow flag is set

JNO

Jump
if overflow flag is
not
set

JP/JPE

Jump
if parity flag is set /
Jump
if parity even

JNP/JPO

Jump
if not parity /Jump if parity odd

JG/JNLE

Jump
if greater then
/
Jump if nut less than nor equal

JA/JNL

Jump
if above / Jump if
not
less than

JL/JNGE

Jump if less
than /
Jump
if not greater than nor equal

JLE/JNG

jump if less
than or equal to / jump if not greater than

JS

Jump if
sign flag is set

JNS

jump
if sign flag is not set

LOOP
label

This
is a looping instruction of assembly. The number of times the looping is
required is placed in CX register. Each iteration decrements CX register by one
implicitly, and the Zero Flag is checked to check whether to loop again. If
the zero flag is not set (CX is zero) greater than the control goes back to
the specified label in the instruction, or else the control falls through to
the next instruction. The LOOP instruction expects the label destination at
offset of - 128 to +127 from the loop

Instruction
offset.

; Let
us assume we want to

; add
07 to AL register,

; Three
times.

MOV CX,03

; count
of iterations

L1 :
ADD AL,

LOOP
L1

;
loop back to L1

; until
CX

; set
(CX is zero) greater than the

; becomes
equal to zero

;control
goes back to the

; Loop
affects no flags.

LOOPE/ LOOPZ
label

Loop
through a sequence of instructions while zero flag = 1 and
CX is not equal to zero. There are two ways to exit out of the loop, firstly,
when the count in the CX register becomes equal to zero, or when the
quantities that are being compared become unequal.

Let us assume
we
have
an array of 20 bytes. We want to see if all the elements
of that array are equal to 0FFh or
not. To scan 20 elements of the array, we loop 20 times. And we come out of
the loop, when either the count of iterations has become equal to 20, or in
other words CX
register
has decremented to zero, which means all the elements of the array are equal
to 0FFh, or an element in the array is found which is not equal to 0FFh. In
this case, the CX register may still be greater than zero, when the control
comes out. This can be coded as follows:

(Please
note here that you might not understand everything at this place, that is
because you are still not familiar with the various addressing modes. Just
concentrate on the LOOPE instruction):

MOV BX, OFFSET
ARRAY

; Point
BX at the start

; of
the ARRAY

DEC
BX ; put
number of

; array
elements in CX

MOV
CX, 10

L1:
INC BX ;
point
to

; next
element in array

CMP
[BX] ,0FFh

; compare
array element

; with
0FFh

LOOPE
L1

; When
the control comes

; out
of the loop, it has

; either
scanned all the

; elements
and found them

; to be
all equal to 0FFh, or

; it is
pointing to the first

; non-0FFh,
element in the

; Array.

LOOPNE/LOOPNZ
label

This
instruction causes Loop through a sequence of instructions while zero flag = 0 and
CX is not equal to zero. This instruction is just the opposite of the
previous instruction in its functionality.

JCXZ
label

Jump
to specified address if CX=0. This instruction will cause a jump, if the
value of CX register is zero. Otherwise it will proceed with the next
instruction in sequence.

This
instruction is useful when you want to check whether CX is
zero even prior to entering into a loop. Please note that LOOP instruction
executes the loop at least once before decrementing and checking the value of
CX register. Thus, CX=O will execute the loop once and decrement the CX
register, making it 0FFFFh, which is non-zero: This will cause FFFFh times.
Execution of loop. To

avoid
such type of conditions you can

proceed
as follows:

JCXZ
SKIP -LOOP

; if CX
is already 0, skip

; loop

L1 : SUB
[BX],07h

INC
BX

LOOP
L1

; loop
until CX=0

SKIP
LOOP

In addition to these
instructions, there are other interrupt handling instructions also, which too
transfer the control of the program to some specified location.

String Instructions

These are a very strong set of
8086 instructions as these instructions process strings, in a compact manner,
thus, reducing the size of the program by a considerable amount.
"String" in assembly is just a sequentially stored bytes or words. A string
often consists of ASCII character codes. A subscript B following the
instruction indicates that the string of bytes is to be acted upon, while
"W" indicates that it is the string of words that is being acted
upon.

MNEMONIC

DESCRIPTION

EXAMPLES

REP

This
is an instruction prefix. It causes repetition of the following instruction
till CX becomes zero. REP. It is not an instruction, but it is an
instruction prefix that causes the CX register to be decremented. This prefix
causes the string instruction to be repeated, until CX becomes equal to zero.

REP
MOVSB STR1,STR2
The above example copies byte by byte contents. The CX register is
initialized to contain the length of source string. REP repeats the operation
MOVSB that copies the source string byte to destination byte. This operation
is repeated until the CX register becomes equal to zero.

REPE/REPZ

It
repeats the instruction following until CX =O or ZF is not equal to one.
REPEIREPZ may be used /
with
the compare string instruction or the scan string instruction. REPE causes
the string instruction to be repeated, till compared bytes or words are
equal, and CX is not yet decremented to zero.

REPNE/REPNZ

It
repeats instruction following it until CX =O or ZF is equal to 1. This
comparison here is just inverse of REPE except for CX, which is checked to be
equal to zero.

MOVS/MOVSB/MOVSW

It
causes moving of byte or word from one string to another. This instruction
assumes that:

·Source string is in Data segment.

·Destination string is in extra data segment

·SI stores offset of source string in extra segment

·DI stores offset of destination string is in data
segment

·CX contains the count of operation

A single byte
transfer rewires:

·One byte transfer from source string
to destination.

·Increment of SI and DI to next byte

·Decrement count register that is CX
register

Assumes
both data and extra segment start at address 1000 in the memory.
Source string starts at offset 20h and the destination string starts at
offset 30h. Length of the source string is 10 bytes. To copy the source
string to the destination string, proceed as follows:

MOV AX, 1000h

MOV DS,AX

; initialize
data segment and

MOV ES,AX

; extra
segment

MOV SI,20h

MOV DI,30h

;load offset
of start of

;source string
to SI

;load offset
of start of

;destination
string to DI

MOV CX, 10

; load length of
string to CX

; as counter

REP MOVSB

; Decrement CX
and

; MOVSB until

; CX =o

; after move SI
will be one

; greater than
offset of last

; byte in source
string, DI

; will be one
greater than

; offset of last
destination

; String. CX
will be equal

: To zero.

CMPS/CMPSB/CMPSW

It compares
two string bytes or words. The source string and the

destination
strings should be present in data segment and the extra segment respectively.
SI and DI are used as in the previous instruction. CX is used if more than
one bytes or words are to be compared; however for such a case appropriate
repeating prefix like REP, PEPE etc. need to be used.

MOV cx,10

MOV S1,OFFSET
SRC-STR

; offset of
source

; string in SI

MOV DI, OFFSET
DES-STR

; offset of
destination

; string in DI

REPE CMPSB

; Repeat the
comparison of

; string bytes
until

; end of string
or until

; compared bytes
are not

; Equal.

SCAS/SCASB/SCASW

It scans a
string. Compare a string byte with byte in AL or a string word with a word in
AX.
The
instruction does not change the operands in AL (AX) or the operand in
the string. The string to be scanned must be present in the extra
segment, and the offset of the string must be contained in the DI register.
You can use CX if operation is to be repeated using REP prefixes.

MOV AL, 0Dh

; Byte to be
scanned

; for in AL

MOV D1,OFFSET
DES-STR

MOV CX,l0

REPNE SCAS
DES-STR

; Compare byte
in DES-STR

; with byte in
AL register

; Scanning is
repeated while

;the bytes are
not equal and

;it is not end
of string. If a

; carriage
return 0Dh is

; found, ZF = DI
will point

; at the next
byte after the

; Carriage
return. If a

; carriage
return is not

; found then, ZF = 0 and

; CX = 0. SCASB or

; SCASW can be
used to

; explicitly
state whether

; the byte
comparison or the

;word
comparison is

; required.

LODS/LODSB/

LODSW

It loads
string byte into AL or a string word into AX. The string byte is assumed to
be pointed to by SI register. After the load, the SI pointer is automatically
adjusted to point to the next byte or word as the case may be. This
instruction does not affect any flag.

MOV S1,OFFSET
SRC-STR

LODS SRC-STR

; LODSB or LODSW
can

; be used to
indicate to the

; assembler,
explicitly

; whether it is
the byte that

; is required to
be loaded or

: the word

STOS/STOSB/

STOSW

It stores byte
from AL
or
word from AX into the string present in the extra segment with offset given
by DI. After the copy, DI is automatically adjusted to point to the next byte
or word as per the instruction. No flags are affected.

MOVDI,OFFSET
DES_STR

STOSB
DES_STR

Processor
Control Instructions

The objectives of these
instructions are to control the processor. This raises two questions:

·How
can you control processor, as this is the job of control unit?

·How
much control of processor is actually allowed?

Well, 8086 only allows you to
control certain control flags that causes the processing in a certain
direction, processor synchronization if more than one processor are attached
through LOCK instruction for buses etc.

MNEMONIC

DESCRIPTION

EXAMPLE

STC

It sets carry
flag to 1.

CLC

It clears the
carry flag to 0.

CMC

It complements
the state of the carry flag from 0 to 1 or 1 to 0 as the case
may be.

CMC; Invert
the carry flag

STD

It sets the
direction flag to 1. The string instruction moves either
forward (increment SI, DI) or backward (decrement SI, DI) based on this flag
value. STD instruction does not affect any other flag. The set direction flag
causes stings to move from right to left.

CLD

This is
opposite to STD, the string operation occurs in the reverse
direction:

CLD

; Clear
the direction flag

; so
that the string pointers

; Auto-increment.

MOV
AX, 1 000h

MOV
DS, AX

; Initialize data
segment

; and
extra segment

MOV
ES, AX

MOV
SI, 20h

; Load
offset of start of

; source
string to SI

MOV
DI,30h

; Load
offset of start of

; destination
string to DI

MOV
CX,10

; Load
length of string to

; CX as
counter

REP
MOVSB

; Decrement
CX and

; increment

; SI
and DI to point to next

; byte,
then MOVSB until

;CX=0

Note: These instructions include
instructions for setting and closing interrupt flag, halting the computer, LOCK
(locking the bus), NOP etc.

ADDRESSING MODES

The basic set of operands in 8086
may reside in register,
memory
and immediate operand. How can these operands be accessed through various
addressing modes? The answer to the question above is given in the following
sub-section. Large number of addressing modes helps in addressing complex data
structures with ease. Some specific Terms and registers roles for addressing:

·Base register (BX, BP): These
registers are used for pointing to base of an array, stack etc.

·Index register (SI, DI):
These registers are used as index registers in data and/or extra segment.

·Displacement: It represents offset from
the segment address.

·

Addressing
modes of 8086

Mode

Description

Example

Direct

Effective
address is the displacement of memory variable.

Register
Indirect

Effective
address is the contents of a register.

[BX]

[SI]

[DI]

[BP]

Based

Effective
address is the sum of a base register and a displacement.

LIST
[BX]

(OFFSET
LIST + BX)

[BP +
1

Indexed

Effective
address is the sum of an index register and a displacement.

LIST
[SI]

[LIST
+ DI]

[DI
+2]

Based
Indexed

Effective
address is the sum of a base and an index register.

[BX +
SI]

[BX]
[DI]

[BP +
DI]

Based
Indexed with displacement

Effective
address is the sum of a base register, an index register, and a displacement.

In
general, the register addressing mode is the most efficient because registers
are within the CPU and do not require memory access.

MOV
AL,CH

MOV
AX,CX

Immediate
Addressing Mode

An immediate operand can be a
constant expression, such as a
number, a character, or an arithmetic expression. The only constraint is that
the assembler must be able to determine the value of an immediate operand at
assembly time. The value is directly inserted into the machine instruction.

MOV AL, 05

Mode

Description

Example

Immediate

Please
note in the last examples the expression (2 + 3)/5, is
evaluated at assembly time.

MOV
AL, 10

MOV AL,'A'

MOV
AX,'AB’

MOV
AX, 64000

MOV AL, (2 + 3)/5

Direct
Addressing Mode

A direct operand refers to the
contents of memory at an address implied by the name of the value.

Mode

Description

Example

DIRECT

The
direct operands are
also
called as Re-locatable operands as they
represent the offset of a label from the beginning of a segment. On reloading
a program even in a different segment will not cause change in the offset
that is why we call them re-locatable. Please note that a variable is considered
in Data segment (DS) and code label in code segment (SS) by default. Thus, in
the example, COUNT, by default will be assumed to be in data segment, while
LABEL 1, will be assumed to be in code segment. If we specify, as a
direct operand then the address is non-re-locatable. Please note the value of
segment register will be known only at the run time.

MOV
COUNT, CL

; move CL
to COUNT (a byte variable)

MOV
AL,COUNT

; move
COUNT to AL

JMP LABEL1

;jump
to LABEL1

MOV
AX,DS:5

; segment
register and

; offset

MOV
BX,CSEG:2Ch

; segment
name and
offset

MOV
AX,ES:COUNT

; segment
register and

; Variable.

; The
offsets of these

; variables
are calculated

; with
respect to the

; segment
name (register)

; specified
in the

; instruction.

Indirect
Addressing Mode

In indirect addressing modes,
operands use registers to point to locations in memory, So, it is actually a
register indirect addressing mode. This is a useful mode for handling strings/
arrays etc. For this mode two types of registers are used. These are:

·Base register BX, BP

·Index register SI, DI

BX contain offset/ pointer in
Data Segment

BP contains offset/ pointer in
Stack segment.

-SI contains offset/pointer in
Data segment.

DI contains offset /pointer in
extra data segment.

There are five different types of
indirect addressing modes:

1.Register
indirect

2.Based
indirect

3.Indexed
indirect

4.Based
indexed

5.Based
indexed with displacement.

Mode

Description

Example

Register
indirect

Indirect
operands are particularly powerful when processing list of arrays, because a
base or an index register may be modified at runtime.

MOV
BX, OFFSET ARRAY

; point
to start of array

MOV
AL,[BX]

; get
first element

INC
BX

; point
to next

MOV
DL,[BX]

; get
second element

The
brackets around BX signify that we are referring to the contents of memory
location, using the address stored in BX. In the following example, three
bytes in an array are added together:

MOV
S1,OFFSET ARRAY

; address
of first byte

MOV
AL,[SI] *

; move
the first byte to AL

IMC
SI

;point
to next byte

ADD
AL, [SI]

;add
second byte

INC
SI

;point
to the third byte

ADD
AL, [SI]

;add
the third byte

Based Indirect and
Indexed Indirect

Based and
indirect addressing modes are used in the same manner. The contents of a
register are added to a displacement to generate an effective address. The
register must be one of the following:

SI, DI, BX or
BP. If the registers used for displacement are base registers, BX or BP, it
is said to be base addressing or else it is called indexed addressing. A displacement
is either a number or a 1abel whose offset is known at assembly time.
The notation may take several equivalent forms. If BX, SI or DI is used, the
effective address is usually an offset from the DS register; BP on the other hand,
usually contains an offset from the SS register.

; Register added
to an offset

MOV DX,
ARRAY[BX]

MOV DX,[DI + ARRAY]

MOV DX,[ARRAY + SI]

; Register added
to a constant

MOV AX,[BP + 21

MW DL,[DI - 21 ; DI + (-2)

MOV DX,2[SI]

Based Indexed

In this type
of addressing the operand's effective address is formed by combining a base
register with an index register.

MOV AL,[BP]
[SI]

MOV DX,[BX 1 SI]

ADD CX,[DII
[BX]

; Two base
registers or two

; index
registers cannot be

; combined, so
the

; following
would be

; incorrect:

MOV DL,[BP + BX]

; error : two base
registers

MOV AX,[SI + DI]

; error : two index
registers

Based Indexed with
Displacement

The operand's
effective address is formed by combining a base register, an index register,
and a displacement.

MOV DX, ARRAY
[BX][SI]

MOV AX, [RX + SI
+ ARRAY]

ADD DL,[BX + SI
+ 3]

SUB CX, ARRAY
[BP +SI]

Two base
registers or two index registers cannot be combined, so the following would
be incorrect: