Note that they are calculated from the front-end design and not accurate enough. But of course the possible difference range won't be large. We will keep our updates.

Fixing the url for you. Interesting numbers at 130nm, very promising as well for the future of ASIC development.So If it was shrunk down to 45nm it would energy wise (optimal) result in a saving that result in about ~2 Watt chip, that does 1.25Gh/s.Guess I wasn't that far off, when I estimated 1Gh/s for a single usb powered Chip based on a 45nm design. Still estimates, but at least an estimate I could believe.

So If it was shrunk down to 45nm it would energy wise (optimal) result in a saving that result in about ~2 Watt chip, that does 1.25Gh/s.Guess I wasn't that far off, when I estimated 1Gh/s for a single usb powered Chip based on a 45nm design. Still estimates, but at least an estimate I could believe.

More precisely, scaled to 45nm, Bit Erupter's chip would give 1.96 Ghash/s at 2.5 Watt.This is 787 Mhash/sec and slightly better(!) than my prediction of 700 Mhash/sec for BFL's ASIC.

If BFL uses standard cell, I think they would have to go with 45nm to have chance to meet their spec.What is the mask cost of 45nm these days?

But I figure they will go with a 45nm multiple wafer run, ie several designs on one wafer to cut down the initial cost.They will quickly get delivery problems but now they have proven their product.I guess the next step is to get enough preorders by then to cover the cost of a full mask set.

So If it was shrunk down to 45nm it would energy wise (optimal) result in a saving that result in about ~2 Watt chip, that does 1.25Gh/s.Guess I wasn't that far off, when I estimated 1Gh/s for a single usb powered Chip based on a 45nm design. Still estimates, but at least an estimate I could believe.

More precisely, scaled to 45nm, Bit Erupter's chip would give 1.96 Ghash/s at 2.5 Watt.This is 787 Mhash/sec and slightly better(!) than my prediction of 700 Mhash/sec for BFL's ASIC.

It would not be a good idea to run a chip at 2.5 watts, a bit below 2 watts is a lot wiser, when a usb slot variance can easily dip below 2.5 watts.Also the chip alone is not the only thing which will be drawing power, you have to take that into account, hence why the design should be below 2watts.

Only reason why your prediction "fits" is because you just assumed they'll be using 2 usb ports to power it and also apparently going over the spec of those usb slots are capable of providing.

It would not be a good idea to run a chip at 2.5 watts, a bit below 2 watts is a lot wiser, when a usb slot variance can easily dip below 2.5 watts.Also the chip alone is not the only thing which will be drawing power, you have to take that into account, hence why the design should be below 2watts.

Spec says 500mA, so you can draw 500mA. There is no such thing as "slot variance"; you are making that up...

You would be a pretty bad designer if you needed 0.5W or more to merely power ancillary logic. At most there will be a ~5-10% loss due to the 5V->Vcore power conversion (I doubt the ASIC will run on 5V). The rest (LED) should literally need 0.05W or less. Remember there is no active cooling (it's a coffee warmer). So we are talking about 2.3-2.4W available to the chip.

The USB 1.x and 2.0 specifications provide a 5 V supply on a single wire from which connected USB devices may draw power. The specification provides for no more than 5.25 V and no less than 4.75 V (5 V±5%) between the positive and negative bus power lines. For USB 3.0, the voltage supplied by low-powered hub ports is 4.45–5.25 V.

The usb spec, has a 5% variance. That is what I mean. But I won't be continueing in this thread anymore since you clearly taking this very personal to start attacking me for my opinion.

This is such an improvement, that ~500 Mhash/Joule should be possible at 65nm. Combined with the fact that BFL disclosed that Jalapenos will be wall-powered, after all, I think this makes it very, very likely that BFL is developing at 65nm and not 45nm.

This is such an improvement, that ~500 Mhash/Joule should be possible at 65nm. Combined with the fact that BFL disclosed that Jalapenos will be wall-powered, after all, I think this makes it very, very likely that BFL is developing at 65nm.

However you have also made a convenient assumption that it will utilise two usb ports to power it, allowing it to have twice as much power, for a max of 5 watts. That is abit of a stretch to assume that and why the math to me does not add up for it to do 3.5 Gh/s at 2.5W and is what I stated.

See Lethos, I was right. I correctly predicted 3 months ago that it would use 2 USB ports, and BFL confirmed it:

The Jalapeno draws it's power from two USB port connectors. Both need to be connected to achieve the full 4.5 GH/s performance. (At the users discretion, a single USB connector can be used if it has a 2nd head split off as is common for use with laptop DVD drives).

This is such an improvement, that ~500 Mhash/Joule should be possible at 65nm. Combined with the fact that BFL disclosed that Jalapenos will be wall-powered, after all, I think this makes it very, very likely that BFL is developing at 65nm and not 45nm.

This is such an improvement, that ~500 Mhash/Joule should be possible at 65nm. Combined with the fact that BFL disclosed that Jalapenos will be wall-powered, after all, I think this makes it very, very likely that BFL is developing at 65nm and not 45nm.

mrb: What are your thoughts about the bASIC line using a little less than 2x the power per GH/s of the BFL SC line? You'd expect a 90nm chip to use twice the power of a 65nm chip all else being equal, right? Then what did BFL gain by going full custom? Shouldn't the BFL be significantly more efficient than 2x?

The bASIC power consumption estimate from Tom "8-10 devices per 1000W PSU" is too vague to make a statement at this point... For starters he did not say if he was talking about 24Ghash/s or 57Ghash/s devices.