(Nanowerk News) Brion Technologies, a division of ASML, today announces a new product for semiconductor manufacturers who need the most powerful computational lithography for the next node of chip manufacturing, for a new generation of faster and more energy-efficient electronic devices.

Tachyon Flexible Mask Optimization (Tachyon FMO), part of ASML's Holistic Lithography portfolio, enables the seamless use of multiple Optical Proximity Correction (OPC) techniques in a single mask tapeout, permitting the use of advanced and computationally intensive OPC in those local areas where they provide maximum benefit. The use of different OPC techniques tailored to localized imaging challenges can result in tapeout cycle time which is just one-third of alternative technologies, and which results in the same desired level of imaging performance.

The key to Tachyon FMO enabling the use of multiple mask correction approaches is the high quality boundary healing between the different correction areas. Thus, different areas within a design can have different correction techniques applied without inducing trouble-areas, known as hotspots, in the boundary regions between them. Brion has developed an elegant solution that detects and manipulates hotspots and has the ability to cleanly reinsert the corrected hotspots back into the full chip design without introducing new defects due to proximity effects of neighboring patterns.

Tachyon FMO enables a number of flexible application modes such as repair, insertion of known-good libraries, efficient correction of mask revisions, and applying advanced OPC techniques in highly localized areas where such techniques provide real benefit.

This new product is particularly relevant for 2x nm designs which require more advanced scanner capabilities like ASML's FlexRay illuminator and FlexWave customized wavefronts, along with sophisticated OPC techniques to achieve pattern fidelity in lithography. Techniques such as model based sub-resolution assist features (MB-SRAF) and 3D mask modeling (M3D) are essential to good imaging, yet can be computationally intensive and can add complexity and cost to mask making. Tachyon FMO provides a strong return on investment for customers by achieving the desired imaging performance, while increasing effective throughput (at the same or lower cost) and reducing mask complexity. Tachyon FMO has been demonstrated on real customer cases to reduce tapeout cycle time by over 65%, compared to using advanced techniques for the entire chip. It has also shown a 15-20% reduction in mask complexity, which has a strong correlation with reduced cost and increased yield in mask manufacturing.

STMicroelectronics (ST) has been evaluating Tachyon FMO for its 2x nm node development, focusing on the hotspot repair application. ST has demonstrated dramatic defect reductions for the contact layer through the application of Tachyon MB-SRAF along with Tachyon FMO, while ensuring no new defects were introduced by the repair method itself. Emek Yesilada PhD, the R&D OPC leader for ST's silicon technology development group said, "Tachyon FMO has demonstrated an effective hotspot repair technology that give us access to advanced mask correction methods in a cost effective way."

Jim Koonmen, general manager of Brion Technologies said, "We are excited by the new applications and use cases that are enabled by Tachyon FMO's defect-free boundary healing. Mask correction at 2x nm and below brings with it some very significant computational challenges, so we continue to innovate in order to help our customers successfully manage these challenges while simultaneously achieving their desired imaging and cost targets."

About mask tapeout

In integrated circuits design, tape-out or tapeout is the final part of the design cycle before a photomask is manufactured. In its current practice (also known as 'mask data preparation' or MDP) chip makers perform checks and make modifications to the mask design specific to the manufacturing process. Optical proximity correction (OPC) is the most common example, which corrects for the diffraction and interference behavior of light when printing the sub-micron scale features of modern integrated circuit designs. The term's origin dates back to when photomasks were manually "taped out" using black tape on sheets of PET film.

About Brion Technologies

Brion Technologies is a division of ASML and an industry leader in computational lithography for integrated circuits. Brion's Tachyon™ platform enables capabilities that address chip design, photomask making and wafer printing for semiconductor manufacturing. Brion is headquartered in Santa Clara, California. For more information: www.brion.com