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9.2 System Generator for DSP - What types of timing constraints are automatically created by System Generator for DSP when generating the HDL Netlist?

Description

What types of constraints are automatically created by System Generator for DSP when generating the HDL Netlist? Is it possible that constrains my be created that are not used or are empty?

Solution

When System Generator for DSP generates the HDL Netlist for a model it creates a file called modelname_cw.xcf. This is the synthesis constraints file used by XST. These constraints are then passed on to the implementation tools via the netlist.

System Generator will write out several different timing constraints automatically depending on your design.

First System Generator for DSP will always write out a single Global period constraint. For models that contain additional clock domains, a multi-cycle FROM/TO constraint will be written out for each additional sample rate domain, FROM all elements a given CE drives TO all elements that same CE drives.

In addition to the multi-cycle FROM/TO timing constraints, cross-clock domain, group-to-group constraints will also be written. System Generator for DSP writes out constraints for all possible combinations between each CE time group. It is possible that there may be many more FROM/TO or Group-to-group constraints listed than are actually used in the design. The constraints that are not being used will be empty during timing analysis in PAR.