“The successful silicon validation of our HBM2 IP subsystem is a significant step forward in enabling the next generation of high bandwidth applications using Open-Silicon’s HBM-based solutions. It further reinforces our commitment to 2.5D ASIC designs and other memory intensive ASIC-based platforms,” said Taher Madraswala, President and CEO, Open-Silicon. “This achievement also sets the stage for our next generation multi-port Advanced eXtensible Interface (AXI) based HBM2 IP subsystem, which will target 2.4Gbps per-pin data rates, and beyond, in TSMC’s 7nm technology.”

“Open-Silicon’s successful silicon validation of an HBM2 IP subsystem in 16nm means that volume production of HBM2 ASIC SiPs are now a reality,” said Herb Reiter, President, eda2asic Consulting, Inc. and author of the most recent Multi-Die IC User Guide, co-sponsored by the Electronic System Design Alliance (ESD Alliance). “The benefit to the industry is significant, in that system developers of high bandwidth applications can minimize risk and time-to-market by having access to a complete silicon-proven HBM IP subsystem, and design/manufacturing of HBM2 ASIC SiPs from a single vendor.”

The HBM2 IP subsystem fully complies with the HBM2 JEDEC® standard, translates user requests into HBM command sequences (ACT, Pre-Charge) and handles memory refresh, bank/page management and power management on the interface. It includes the PHY and custom die-to-die I/O needed to drive the interface between the logic die and the memory die-stack on the 2.5D interposer. It features data transfer rates of up to 1.6/2Gbps per-pin at up to 5mm interposer route trace lengths. This enables a full 8-channel connection from a 16nm SoC to a single HBM2 memory stack at 2Gbps, achieving bandwidths up to 256GB/s.

Open-Silicon’s HBM2 IP subsystem addresses the implementation challenges associated with interoperability, 2.5D design, overall SiP design, packaging, test and manufacturing. Multiple built-in test and diagnostic features, such as probe pads and loop-back for issue isolation within the various IP subsystem components, not only address the test and debug challenges, but help in yield management and yield improvement while ramping HBM2 ASIC designs into volume production. For more information, visit www.open-silicon.com/high-bandwidth-memory-ip.

Visit booth #708 in the exhibit hall at the TSMC OIP Ecosystem Forum in Santa Clara, CA, USA, September 13, 2017 to learn more about Open-Silicon’s HBM2 IP subsystem solution and other innovative custom SoC solutions.

About Open-Silicon

Open-Silicon transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers’ products by innovating at every stage of design — architecture, logic, physical, system, software and IP — and then continues to partner to deliver fully tested silicon and platforms. Open-Silicon applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing and test capabilities. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed 300+ designs and shipped over 130 million ASICs to date. Privately held, Open-Silicon employs over 250 people in Silicon Valley and around the world. To learn more, please visit www.open-silicon.com.