A two-stage ultra-wide-band CMOS low-noise amplifier (LNA) is presented. With the common-gate configuration employed as the input stage, the broad-band input matching is obtained and the noise does not rise rapidly at higher frequency. By combining the common-gate and common-source stages, the broad-band characteristic and small area are achieved by using two inductors. This LNA has been fabricate...
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A switched-capacitor bias that provides a constant Gm-C characteristic over process and temperature variation is presented. The bias can be adapted for use with subthreshold circuits, or circuits in strong inversion. It uses eight transistors, five switches, and three capacitors, and performs with supply voltages less than 0.9 V. Theoretical output current is derived, and stability anal...
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We consider the problem of blind equalization of a finite impulse response and single-input multiple-output system driven by an M-ary phase-shift-keying signal. The existing single-mode algorithms for this problem include the constant modulus algorithm (CMA) and the multimodulus algorithm (MMA). It has been shown that the MMA outperforms the CMA when the input signal has no more than four constell...
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Phase-locked loops (PLLs) are a critical component in modern systems. Digital PLLs (DPLLs) are increasingly popular in CMOS technologies due to their ease of integration and scalability with digital logic. However, digital quantization results in larger steady-state systematic jitter, or dithering. High resolution is needed to control the oscillator to minimize the dithering. This brief proposes a...
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Maximally linear digital differentiators (DDs) are known for high accuracy in narrow frequency bands centered at the frequency for which they are designed. In this paper, designs of DDs of odd and even lengths having maximal linearity at the middle of the frequency band are presented. Applying the maximal linearity constraints to the magnitude response of a differentiator gives a system of linear ...
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In this brief, a systematic design procedure for a second-order all-digital phase-locked loop (PLL) is proposed. The design procedure is based on the analogy between a type-II second-order analog PLL and an all-digital PLL. The all-digital PLL design inherits the frequency response and stability characteristics of the analog prototype PLL
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This brief proposes a multiplexing scheme to realize an I/Q-channel time-interleaved (TI) bandpass sigma-delta modulator that shares operational transconductance amplifiers to minimize power consumption and silicon area for a low-intermediate-frequency (IF) wireless receiver. The test chip was fabricated for a 10.7-MHz IF system with a 0.35-mum CMOS process. The measured peak signal-to-noise disto...
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This brief presents an efficient and accurate numerical method to determine the multiparameter sensitivity of amplifier harmonic distortion (HD). The method is developed into the frame of steady-state shooting method and allows a fast exploration of HD perturbation due to small fluctuations of parameters nominal value
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Using a simple input-regeneration approach and index-transformation techniques, a new formulation is presented in this paper for computing an N-point prime-length discrete sine transform (DST) through two pairs of [(N-1)/4]-point cyclic convolutions, where [(N-1)/4] is an odd number. The cyclic convolution-based algorithm is used further to obtain a simple regular and locally connected linear syst...
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Near-field beamforming using a microphone array has found many applications, such as sound acquisition in small rooms. However, robust near-field adaptive beamforming (NABF) against focal point errors has not been studied much in the literature until recently. In this brief, a robust near-field adaptive beamformer is proposed. The proposed method is developed by combining a new formulation of the ...
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This brief introduces a simple circuit solution to secure loop stability of an analog-domain fast-frequency offset cancellation loop (OCL). The OCL is composed of a low-IF receiver, phase-domain frequency offset detector (OD), and fractional-N phase-locked loop (PLL). Since the OCL uses a phase-domain OD, a stability concern is essentially needed for its practical use. From the frequency-domain an...
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A dual-band LC voltage-controlled oscillator (VCO) architecture suitable for GSM/PCS/DCS applications is presented. The VCO utilizes a fourth-order resonance tank and avoids quality-factor-deteriorating switches. The paper outlines the design tradeoffs and the VCO when using a fourth-order resonator. The 0.8-GHz/1.8-GHz test chip was fabricated in the 0.5-mum IBM-5AM SiGe process and has achieved ...
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In this brief, a new embedded negative voltage-level converter (level shifter) is presented. The proposed circuit can convert a positive input signal to a negative output signal with reduced or even without (depending on the application) voltage stress on the used MOS devices. The circuit has been designed in a 0.18-mum triple-well standard CMOS technology, using double-gate-oxide-thickness MOS tr...
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A conventional differential pair LC oscillator is capable of generating only a single fundamental oscillation frequency. This brief presents the theoretical study of a novel oscillator that incorporates higher order LC filters to produce multiple oscillation frequencies that may be several octaves apart. These multiple oscillation frequencies are obtained from a single oscillator, thereby reducing...
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2007 IEEE International Symposium on Circuits and Systems (ISCAS 2007)

Aims & Scope

Part I will now contain regular papers focusing on all matters related to fundamental theory, applications, analog and digital signal processing. Part II will report on the latest significant results across all of these topic areas.