VIA double stuffs x64 clone chips

Two Nano X2s, one package

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Intel and Advanced Micro Devices are not the only ones innovating in the x64 chip racket. VIA Technologies has carved out a niche for itself for low-powered chips suitable for netbooks, small form factor PCs, micro servers, and other embedded devices, and is double-stuffing its sockets with the QuadCore X4 chips to better compete with Intel's Atom and AMD's future "Bobcat" processors.

The QuadCore X4 that crams two of its latest dual-core Nano X2 processors, which were launched in early January and which were supposed to start shipping in the first quarter, onto a single chip package. This is cheaper and easier than designing, taping out, and manufacturing a real quad-core processor and is in fact what Intel itself did for its early dual-core "Paxville" Xeon processors from late 2005 (before the Core architecture was available) and what AMD is doing with its current Opteron 6100s, which are really two Opteron 4100s in a single fat socket.

VIA's Nano X2 dual-core processor

The original Nano processor is based on VIA's Isaiah 64-bit architecture, which debuted in early 2008 with a single-core design. The Nano chip was initially deployed using a 65 nanometer process from either Fujitsu or Taiwan Semiconductor Manufacturing Corp, who bake VIA's chips, but with the X2 dual-core variants, VIA is shifting to 40 nanometer processes.

The Isaiah cores have a superscalar core design that features out-or-order execution; the core has two pipelines fed by eight branch predictors. The Isaiah core has seven execution units, including two integer units, two store units, one load unit, and two media units that have a 128-bit wide data path; the media units can do up to two double-precision or four single-precision operations per clock. (The first unit can do various floating point operations, but the second unit can only do multiplies.)

The Isaiah are designed to have clock speeds that scale from 800MHz to 2GHz and use a front side bus architecture called V4 by VIA that is like old the FSB used by Intel in its Xeon and Pentium chips; that VIA V4 bus can scale from 533MHz to 1.33GHz. Each Isaiah core has 64KB of L1 data cache, 64KB of L1 instruction cache, and 1M of L2 cache.

The chip also has a feature called Padlock, which includes a random number generator and an AES encryption/decryption engine. And importantly, VIA has also reverse-engineered Intel's VT virtualization extensions, so hypervisors can run atop the Isaiah cores.

The Nano chips are pin-compatible with prior VIA C7 standard and Eden low-power processors and their VX900 and VN1000 chipsets. The Nano X2, Eden X2, and now QuadCore X4 chips can similarly plug into the same sockets and use the same chipsets.

The Nano X2 chips are the standard version of the X2 design, and mysteriously VIA has not released their clock speeds yet and Mini-ITX and Nano-ITX system vendors don't seem to have the parts yet, either, although they were supposed to have them ready for sale in systems by the end of the first quarter.

The Nano X2 E-Series variant is aimed at low-power operation and has clocks that spin at 1.2GHz or 1.6GHz and are aimed at embedded Linux and Windows Embedded Standard 7 applications. The Nano X2 E-Series chips and system boards are sampling now at 1.2GHz and 1.6GHz and are expected to ship in the second quarter.

The Eden X2 is a geared down version of the Nano X2 that is designed for fanless operation; it is not clear when this chip will start sampling or be available, or what clock speeds it will run at, but VIA has said that it maxes out at five watts of thermal dissipation using Intel's TDP scaling.

And that leaves the just-announced VIA QuadCore X4, which puts two Nano X2 chips on a single 21mm by 21mm package that slides into the NanoBGA2 socket.

VIA's QuadCore X4 chip package

VIA has put out a little more data about the QuadCore X4 than it did for the Nano X2 that it is based on (yup, that is odd). The company says that it will run the four the four cores on the X4 package at 1.2GHz and higher, that all four 1MB L2 caches will be fired up, that the V4 bus will run at the top-end 1.33GHz speed, and that the TDP for the X4 package will be 27.5 watts.

VIA says that the X4 chip package is "21 per cent more energy efficient than the nearest competitor," but declines to say who that competitor is or what chip it is referring to.

VIA will be showing off the QuadCore X4 chip package at the Computex trade show in its stomping grounds in Taipei, Taiwan, at the end of May. It says it expects to begin volume shipments in the third quarter. ®