1) For table 1 of Berkeley paper , why "Input must be valid for at least two clock periods in the new domain." ?

The explanation:

the width of the input pulse must be greater than the period of the synchronizer clock plus the required hold time of the first synchronizer flip-flop. The safest pulse width is twice the synchronizer clock period.

Could anyone tell why it has to do with hold time of the first synchronizer flip-flop ?

2) For pulse synchronizer or what we known as toggle synchronizer, I do not understand the explanation highlighted in yellow that is given below:

One restriction of a pulse synchronizer is that input pulses must have a minimum spacing between pulses equal to two synchronizer clock periods.

This problem is more severe when the clock period of input pulse is greater than twice the synchronizer clock period

1 Answer
1

The input signal needs to be stable in order to avoid issues with meta stability. Consider the timing diagram taken from this article:
C1 and A are in your source clock domain and C2 and B are in your destination clock domain. If the clock edges violate the timing constraints, the B flip-flop may not detect the high A input. If A changes before the next C2 edge, the high A signal will be missed. This is why you need to hold A stable for two clock periods.

\$\begingroup\$Why is it hold time but not the setup time of the first synchronizer flip-flop ?\$\endgroup\$
– kevinNov 3 '17 at 21:02

\$\begingroup\$@kevin it is both really. This is why I said timing constraints.\$\endgroup\$
– user110971Nov 3 '17 at 21:06

\$\begingroup\$you do not really need hold time in this case since the signal A is "before" the rising clock edge of C2. Even if it is "after" the rising clock edge of C2, we will regard it as being missed by that particular rising edge of C2\$\endgroup\$
– kevinNov 3 '17 at 21:26

\$\begingroup\$@kevin you have to keep in mind that the diagram shows one possibility. If your C2 clock occurs just before the A signal changes, you’ll have a hold time violation.\$\endgroup\$
– user110971Nov 3 '17 at 21:29

1

\$\begingroup\$@kevin Worst case scenario for a setup time violation is: A changes, the C2 clock goes high after a little less than the setup time, generating a violation. You need to keep the signal stable until the next clock cycle + hold time, or for a total of clock period + setup time + hold time. Since usually setup + hold time < clock period, holding the signal stable for two clock cycles solves the problem.\$\endgroup\$
– user110971Nov 9 '17 at 16:01