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Abstract:

An embodiment of the present invention provides a TFT array substrate
comprising: a base substrate (1) and thin film transistors. The thin film
transistor comprises a gate electrode (2), a semiconductor layer (5), a
semiconductor protective layer, a source electrode (8) and a drain
electrode (9). The semiconductor protective layer is disposed adjacent to
the semiconductor layer (5) and comprises a composite lamination
structure, which comprises a protective layer formed of an insulating
material capable of preventing de-oxygen of the semiconductor layer (5)
and an insulating layer formed of an insulating material to be etched
more easily.

Claims:

1. A thin film transistor (TFT) array substrate comprising: a base
substrate and a thin film transistor functioning as a switching element,
the thin film transistor comprising a gate electrode, a semiconductor
layer, a semiconductor protective layer, a source electrode and a drain
electrode, wherein the semiconductor protective layer is disposed
adjacent to the semiconductor layer and comprises a composite lamination
structure, which comprises a protective layer formed of an insulating
material capable of preventing de-oxygen of the semiconductor layer while
contacting the semiconductor layer and an insulating layer formed of an
insulating material to be etched more easily.

2. The TFT array substrate according to claim 1, wherein the gate
electrode is provided on the base substrate, and the semiconductor layer
is arranged over the gate electrode.

3. The TFT array substrate according to claim 2, wherein the
semiconductor protective layer comprises a gate insulating composite
lamination structure disposed between the gate electrode and the
semiconductor layer and adjacent to a lower side of the semiconductor
layer, the gate insulating composite lamination structure comprises a
gate insulating protective layer formed of an insulating material capable
of preventing de-oxygen of the semiconductor layer while contacting the
semiconductor layer and a gate insulating layer formed of an insulating
material to be etched more easily.

4. The TFT array substrate according to claim 2, wherein the source
electrode and the drain electrode are arranged on the semiconductor
layer, with a channel defined therebetween.

5. The TFT array substrate according to claim 2, wherein the
semiconductor protective layer comprises an etching stop composite
lamination structure arranged within the channel and adjacent to a
topside of the semiconductor layer, and the etching stop composite
lamination structure comprises an etching stop protective layer formed of
an insulating material capable of preventing de-oxygen of the
semiconductor layer while contacting the semiconductor layer and an
etching stop insulating layer formed of an insulating material to be
etched more easily.

6. The TFT array substrate according to claim 1, wherein the
semiconductor layer is arranged on the base substrate, and the gate
electrode is provided on the semiconductor layer.

7. The TFT array substrate according to claim 7, wherein the
semiconductor protective layer comprises a buffer insulating composite
lamination structure located between the base substrate and the
semiconductor layer and adjacent to a lower side of the semiconductor
layer, and the buffer insulating composite lamination structure comprises
a buffer insulating protective layer formed of an insulating material
capable of preventing de-oxygen of the semiconductor layer while
contacting the semiconductor layer and an buffer insulating layer formed
of an insulating material to be etched more easily.

8. The TFT array substrate according to claim 7, wherein the source
electrode and the drain electrode are arranged on the semiconductor
layer, with a channel defined therebetween.

9. The TFT array substrate according to claim 7, wherein the
semiconductor protective layer comprises an etching stop composite
lamination structure arranged within the channel and adjacent to the
topside of the semiconductor layer, and the etching stop composite
lamination structure comprises an etching stop protective layer formed of
an insulating material capable of preventing de-oxygen of the
semiconductor layer while contacting the semiconductor layer and an
etching stop insulating layer formed of an insulating material to be
etched more easily.

10. The TFT array substrate according to claim 1, wherein the
semiconductor layer is formed of a metal oxide semiconductor material.

11. The TFT array substrate according to claim 1, wherein the ratio of
thickness of the protective layer to that of the insulating layer is in a
range from 1/10 to 3/5.

12. The TFT array substrate according to claim 11, wherein a thickness of
the protective layer is in a range from 300 Å to 1500 Å, and a
thickness of the insulating layer is in a range from 1000 Å to 20000
Å.

13. The TFT array substrate according to claim 1, wherein the etching
stop protective layer is formed of silicon oxide or metal oxide, and the
etching stop insulating layer is formed of nitride or organic insulating
materials.

14. The TFT array substrate according to claim 1, wherein the protective
layer is formed of SiOx or Al2O3, and the insulating layer
is formed of SiNx or organic resin.

15. The TFT array substrate according to claim 1, further comprising a
passivation layer and a transparent pixel electrode.

16. The TFT array substrate according to claim 3, wherein the
semiconductor protective layer comprises an etching stop composite
lamination structure arranged within the channel and adjacent to a
topside of the semiconductor layer, and the etching stop composite
lamination structure comprises an etching stop protective layer formed of
an insulating material capable of preventing de-oxygen of the
semiconductor layer while contacting the semiconductor layer and an
etching stop insulating layer formed of an insulating material to be
etched more easily.

17. The TFT array substrate according to claim 8, wherein the
semiconductor protective layer comprises an etching stop composite
lamination structure arranged within the channel and adjacent to the
topside of the semiconductor layer, and the etching stop composite
lamination structure comprises an etching stop protective layer formed of
an insulating material capable of preventing de-oxygen of the
semiconductor layer while contacting the semiconductor layer and an
etching stop insulating layer formed of an insulating material to be
etched more easily.

18. A liquid crystal display comprising the array substrate according to
claim 1.

Description:

TECHNICAL FIELD

[0001] An embodiment of the present invention relates to a thin film
transistor (TFT) array substrate.

BACKGROUND

[0002] Along with the development of the display manufacturing
technologies, thin film transistor liquid crystal displays (TFT-LCDs)
have been prevailing in the recent flat display market due to
characteristics, such as compactness, low power consumption, and non
radiation, and the like.

[0003] A prior art process for producing a TFT array substrate commonly
comprises: depositing a gate metal film, a gate insulating film, a metal
oxide film (semiconductor film), a source-drain metal film, a passivation
layer film as well as a transparent conductive film onto a substrate, and
forming successively, through several photolithography processes, the
patterns of a gate electrode, a gate insulating layer, a semiconductor
layer, a source electrode, a drain electrode, a passivation layer as well
as a transparent pixel electrode. Usually, one photolithography process
successively comprises film formation, exposure, development, etching and
removing etc.; the etching process comprises dry etching and wet etching.
Wet etching has the drawbacks of poor anisotropy, severe undercutting,
poor control on patterns, failure for fine characteristic dimensions,
production of considerable chemical liquid waste, and the like; in
contrast, due to the advantages, such as good anisotropy, good
controllability, flexibility, repeatability, processing safety, easy
automation, no chemical liquid waste, no contamination introduced during
process, and high brilliancy, and the like, dry etching is widely used in
the photolithography process for a TFT array substrate.

[0004] In the above processes for making a TFT array substrate, the
formation of the semiconductor layer and the source electrode as well as
the drain electrode is conducted through successive processes, that is,
the semiconductor layer film is firstly deposited and then the
source-drain metal film are deposited. In order to prevent the damages to
the semiconductor film in depositing the source-drain metal film,
typically one etching stop layer is deposited onto the semiconductor
film, and next the source-drain metal film is deposited. After the
patterning process, the etching stop layer retains within the channel
between the source electrode and the drain electrode over the
semiconductor layer. One surface of the semiconductor layer contacts the
etching stop layer, and the other surface contacts the gate insulating
layer. The etching stop layer and the gate insulating layer are usually
formed of an insulating material, such as SiNx, Al2O3,
SiOx, etc. If the semiconductor layer is formed of a metal oxide
material and the etching stop layer and the gate insulating layer are
formed of SiNx, SiNx contained in the etching stop layer and
the gate insulating layer will seize the oxyanion in the metal oxide of
the semiconductor layer, causing de-oxygen of the metal oxide of the
semiconductor layer and thus unstable behavior of the TFT array
substrate.

[0005] In order to enhance the stability of the TFT array substrate, the
etching stop layer and the gate insulating layer may also be formed of
Al2O3 or SiOx. However, in the case of dry etching, if the
patterns of the etching stop layer and the gate insulating layer are
formed of Al2O3 or SiOx, the etching rate will be low,
which is adverse to large scale production.

SUMMARY

[0006] A technical problem overcome by embodiments of the present
invention is to provide a TFT array substrate capable of improving the
stability of thin film transistor (TFT) device and further suitable for
large-scale production.

[0007] One embodiment of the present invention provides a TFT array
substrate, comprising a base substrate and a thin film transistor
functioning as a switching element. The thin film transistor comprises a
gate electrode, a semiconductor layer, a semiconductor protective layer,
a source electrode and a drain electrode. The semiconductor protective
layer is disposed adjacent to the semiconductor layer and comprises a
composite lamination structure, which comprises a protective layer formed
of an insulating material capable of preventing de-oxygen of the
semiconductor layer (5) and an insulating layer formed of an insulating
material to be etched more easily.

[0008] For example, the gate electrode is arranged on the base substrate,
and the semiconductor layer is arranged over the gate electrode.

[0009] For example, the semiconductor protective layer comprises a gate
insulating composite lamination structure arranged between the gate
electrode and the semiconductor layer and adjacent to a lower side of the
semiconductor layer, and the gate insulating composite lamination
structure comprises a gate insulating protective layer formed of an
insulating material capable of preventing de-oxygen of the semiconductor
layer while contacting the semiconductor layer and a gate insulating
layer formed of an insulating material to be etched more easily.

[0010] For example, the source electrode and the drain electrode are
arranged above the semiconductor layer with a channel defined
therebetween.

[0011] For example, the semiconductor protective layer comprises an
etching stop composite lamination structure, which comprises an etching
stop protective layer formed of an insulating material capable of
preventing de-oxygen of the semiconductor layer while contacting the
semiconductor layer and an etching stop insulating layer formed of an
insulating material to be etched more easily.

[0012] For example, the semiconductor layer is provided on the base
substrate, and the gate electrode is provided on the semiconductor layer.

[0013] For example, the semiconductor protective layer is a buffer
insulating composite lamination structure located between the substrate
and the semiconductor layer and contacting a lower side of the
semiconductor layer, and the buffer insulating composite lamination
structure comprises a buffer insulating protective layer formed of an
insulating material capable of preventing de-oxygen of the semiconductor
layer while contacting the semiconductor layer and a buffer insulating
layer formed of an insulating material to be etched more easily.

[0014] For example, the source electrode and the drain electrode are
arranged on the semiconductor layer with a channel defined therebetween.

[0015] For example, the semiconductor protective layer comprises an
etching stop composite lamination structure located within the channel
and adjacent to the topside of the semiconductor layer, and the etching
stop composite lamination structure comprises an etching stop protective
layer formed of an insulating material capable of preventing de-oxygen of
the semiconductor layer while contacting the semiconductor layer and an
etching stop insulating layer formed of an insulating material to be
etched more easily.

[0016] For example, the semiconductor layer is formed of a metal oxide
semiconductor material.

[0017] For example, the ratio of the thickness of the protective layer to
that of the insulating layer is in a range of 1/10 to 3/5.

[0018] For example, a thickness of the protective layer is in a range of
300 Å to 1500 Å, and a thickness of the insulating layer is in a
range of 1000 Å to 20000 Å.

[0019] For example, the etching stop protective layer is formed of silicon
oxide or metal oxide, and the etching stop insulating layer is formed of
nitride or organic insulating materials.

[0020] For example, the protective layer is formed of SiOx or
Al2O3, and the insulating layer is formed of SiNx or
organic resins.

[0021] For example, the array substrate further comprises a passivation
layer and a transparent pixel electrode.

[0022] For example, the reacting gases correspondingly for forming
SiNx is SiH4, NH3 and N2, or SiH2Cl2,
NH3 and N2.

[0023] In the TFT array substrate according to the embodiment of the
present invention, the semiconductor protective layer adjacent to the
semiconductor layer employs a composite lamination structure, in which
the protective layer contacting the semiconductor layer is formed of an
insulating material capable of preventing de-oxygen of the semiconductor
layer, for example, silicon oxide or metal oxide, which structure can
avoid de-oxygen of the semiconductor layer and thus be in favor of
improving the stability of the TFT array substrate; the insulating layer
contacting the protective layer (i.e., not contacting the semiconductor
layer) is formed of an insulating material to be etched more easily, for
example, nitride or organic insulating materials, which structure is
beneficial to improve the overall etching speed for the array substrate,
and therefore improve the productive capacity and is suitable for
large-scale production.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to clearly illustrate the technical solution of the
embodiments of the invention, the drawings of the embodiments will be
briefly described in the following; it is obvious that the described
drawings are only related to some embodiments of the invention and thus
are not limitative of the invention.

[0025] FIG. 1(a)-(f) is structural schematic view of the TFT array
substrate according to a first embodiment of the present invention,
wherein:

[0026] FIG. 1(a) is a structural schematic view of the TFT array substrate
in the first embodiment after the first photolithography process;

[0027] FIG. 1(b) is a structural schematic view of the TFT array substrate
in the first embodiment after the second photolithography process;

[0028] FIG. 1(c) is a structural schematic view of the TFT array substrate
in the first embodiment after the third photolithography process;

[0029] FIG. 1(d) is a structural schematic view of the TFT array substrate
in the first embodiment after the fourth photolithography process;

[0030] FIG. 1(e) is a structural schematic view of the TFT array substrate
in the first embodiment after the fifth photolithography process;

[0031] FIG. 1(f) is a structural schematic view of the TFT array substrate
in the first embodiment after the sixth photolithography process;

[0032] FIG. 2(a)-(f) is structural schematic view of the TFT array
substrate according to a second embodiment of the present invention,
wherein:

[0033] FIG. 2(a) is a structural schematic view of the TFT array substrate
in the second embodiment after the first photolithography process;

[0034] FIG. 2(b) is a structural schematic view of the TFT array substrate
in the second embodiment after the second photolithography process;

[0035] FIG. 2(c) is a structural schematic view of the TFT array substrate
in the second embodiment after the third photolithography process;

[0036] FIG. 2(d) is a structural schematic view of the TFT array substrate
in the second embodiment after the fourth photolithography process;

[0037] FIG. 2(e) is a structural schematic view of the TFT array substrate
in the second embodiment after the fifth photolithography process;

[0038] FIG. 2(f) is a structural schematic view of the TFT array substrate
in the second embodiment after the sixth photolithography process.

[0039] The objects, solutions and advantages of the embodiments of the
present invention will be more apparent from the following clear and
complete description about the embodiments of the present invention in
connection with embodiments and accompany drawings. Obviously, the
described embodiments are merely part of the embodiments of the present
invention, but not all the embodiments. Based on the described
embodiments of the present invention, all the other embodiments achieved
by the ordinary skilled in this art without any creative work belong to
the protective scope of the present invention.

[0040] In an embodiment of the present invention, a TFT array substrate
comprises: a base substrate 1 and a thin film transistor acting as a
switching element. The thin film transistor comprises a gate electrode 2,
a semiconductor layer 5, a semiconductor protective layer, a source
electrode 8 and a drain electrode 9. The semiconductor protective layer
adjacent to the semiconductor layer 5 adopts a composite lamination
structure. The composite lamination structure comprises a protective
layer formed of an insulating material capable of preventing de-oxygen of
the semiconductor layer 5 while contacting the semiconductor layer 5 and
an insulating layer formed of an insulating material to be etched more
easily.

[0041] The TFT array substrate comprise a plurality of gate lines and a
plurality of data lines, these gate lines and data lines intersect one
another so as to define a plurality of pixel areas in an array
arrangement, and each pixel area comprises a thin film transistor; the
gate electrode of the thin film transistor is connected with a
corresponding gate line or formed integratedly with the gate line, and
the source electrode of the thin film transistor is connected with a
corresponding data line or formed integratedly with the data line. The
following description is made only for a thin film transistor of one
pixel area, but the description also applies for the thin film
transistors of other pixel areas.

Embodiment 1

[0042] As shown in FIG. 1(f), the TFT array substrate in this embodiment
comprises: a base substrate 1; a gate electrode 2 formed on the base
substrate 1; a gate insulating layer 3 covering the gate electrode 2 and
extending onto the base substrate 1; a gate insulating protective layer 4
covering the gate insulating layer 3; a semiconductor layer 5 formed on
the gate insulating protective layer 4; a source electrode 8 and a drain
electrode 9 formed on the semiconductor layer 5, with a channel 15 being
defined between the source electrode 8 and the drain electrode 9; a
composite lamination structure formed in the channel 15, comprising an
etching stop protective layer 6 and an etching stop insulating layer 7,
wherein the etching stop protective layer 6 is located below the etching
stop insulating layer 7 and contacts the semiconductor layer 5; a
passivation layer 10 completely covering the source electrode 8, the
etching stop insulating layer 7, and the drain electrode 9 as well as
gate insulating protective layer 4, wherein a portion of the passivation
layer 10 covering the drain electrode 9 is formed with a via hole 12; a
transparent pixel electrode 11 formed on the passivation layer 10 and
connected with the drain electrode 9 through the via hole 12.

[0043] In one example, the semiconductor protective layer adjacent to the
semiconductor layer 5 comprises a composite lamination structure formed
in the channel 15, i.e., comprises an etching stop protective layer 6 and
an etching stop insulating layer 7 over the semiconductor layer 5.

[0044] In another example, the semiconductor protective layer adjacent to
the semiconductor layer 5 comprises a composite lamination structure
comprising the gate insulating layer 3 and the gate insulating protective
layer 4, located below the semiconductor layer 5 and between the
semiconductor layer 5 and the gate electrode 2.

[0045] In yet another example, the semiconductor protective layer adjacent
to the semiconductor layer 5 comprises both of the cases of the above
examples so as to provide protection for the semiconductor layer 5 on
both the upper side and the lower side thereof.

[0046] The TFT array substrate in this embodiment is used, for example,
for a vertically-driven type or horizontally-driven type liquid crystal
display; however, the present invention is not limited thereto.

[0047] In this embodiment, the gate insulating layer 3/the etching stop
insulating layer 7 has a thickness in a range from 1000 Å to 20000
Å and may be formed of nitride or organic insulating materials, for
example, SiNx or organic resin. The reacting gases correspondingly
for forming SiNx comprise SiH4, NH3 and N2, or
SiH2Cl2, NH3 and N2.

[0048] In this embodiment, the gate insulating protective layer 4/the
etching stop protective layer 6 has a thickness in a range from 300 Å
to 1500 Å and may be formed of silicon oxide or metal oxide, for
example, SiOx or Al2O3.

[0050] In one example, the etching stop protective layer 6 and the gate
insulating protective layer 4, which both contact the semiconductor layer
5, are each formed of the material(s) which can avoid de-oxygen of the
semiconductor layer 5 but are difficult for etching; while the gate
insulating layer 3 and the etching stop insulating layer 7, which both do
not contact the semiconductor layer 5, are each formed of the material(s)
to be etched more easily.

[0051] In this embodiment, in the composite lamination structure serving
as the semiconductor protective layer, the ratio of the thickness of the
gate insulating protective layer 4 to that of the gate insulating layer 3
is for example from 1/10 to 3/5. Or, in the composite lamination
structure serving as the semiconductor protective layer, the ratio of the
thickness of the etching stop protective layer 6 to that of the etching
stop insulating layer 7 is for example from 1/10 to 3/5.

[0052] Due to the fact that the semiconductor protective layer, comprising
the composite lamination structure formed of the above materials, will
not seize the oxyanion in the semiconductor layer 5, the stability of the
TFT array substrate is improved, and also the etching speed upon the gate
insulating layer and the etching stop layer is increased, which promotes
productive capacity and is suitable for large-scale production.

[0053] The base substrate 1 may employ a transparent non-alkali glass
substrate or a quartz substrate, or employ other transparent substrates
having certain hardness.

[0054] The semiconductor layer 5 is formed of a metal oxide semiconductor
material, for example, transparent amorphous oxide semiconductor IGZO
(In--Ga--Zn--O) and, for example, through sputtering method, and the
thickness thereof is in a range from 50 Å to 1000 Å.

[0055] The gate electrode 2, the source electrode 8 and the drain
electrode 9 is formed through sputtering or thermal evaporation method,
and the range for their thicknesses is from 4000 Å to 15000 Å.
The gate electrode 2, the source electrode 8 and the drain electrode 9
may be formed of a monolayer film formed of any one of Cr, W, Cu, Ti, Ta
or Mo, or formed of alloy of any one of the above metals, or formed of a
multilayer film formed of the any combination of the above metals.

[0056] The passivation layer 10 for example is formed by using PECVD and
the range for the thickness is for example from 1000 Å to 3000 Å.
The passivation layer 10 may be formed of oxide, nitride or oxynitride.
The reacting gases correspondingly for forming nitride comprise SiH4, NH3
and N2, or SiH2Cl2, NH3 and N2.

[0057] The transparent pixel electrode 11 is formed through sputtering or
thermal evaporation method, and the range for the thickness is for
example from 300 Å to 1500 Å, and the transparent pixel electrode
11 may be formed of a transparent metal oxide material, for example,
formed of an ITO film or an IZO film.

[0058] The TFT array substrate in this embodiment may be formed by using
six photolithography processes. One exemplary workflow is described as
follows with reference to FIGS. 1(a)-1(f).

[0059] Step (1): as shown in FIG. 1(a), a gate metal film is deposited
onto a base substrate 1 and then through a first photolithography
process, is formed into the patterns of the gate electrode 3 and the gate
scanning line (not shown in the figures).

[0060] Step (2): as shown in FIG. 1(b), on the substrate after step (1) a
gate insulating film and a metal oxide used for forming the semiconductor
layer are deposited sequentially, and then through a secondary
photolithography process, are formed into the patterns of the gate
insulating layer 3, the gate insulating protective layer 4 and the
semiconductor layer 5. The gate insulating layer 3 covers the gate
electrode 2 and extends to the base substrate 1. The gate insulating
protective layer 4 covers the gate insulating layer 3, and the plain size
of the gate insulating protective layer 4 is substantially the same as
that of the gate insulating layer 3.

[0061] Step (3): as shown in FIG. 1(c), on the substrate after step (2)
two layers of etching stop insulating films are deposited, and then
through a third photolithography process, are formed into the patterns of
the etching stop protective layer 6 and the etching stop insulating layer
7. The etching stop insulating layer 7 covers the etching stop protective
layer 6 and has the same plane size as that of the etching stop
protective layer 6, and the etching stop protective layer 6 is disposed
on and contact with the semiconductor layer 5. The etching stop
protective layer 6 and the etching stop insulating layer 7 essentially
correspond to the channel region of the thin film transistor to be
formed.

[0062] Step (4): as shown in FIG. 1(d), on the substrate after step (3) a
source-drain metal film is deposited, and then through a fourth
photolithography process, is formed into the patterns of the source
electrode 8, the drain electrode 9 and the data scanning line (not shown
in the figures). The source electrode 8 and the drain electrode 9 are
provided on the semiconductor layer 5 and respectively arranged on both
sides of the etching stop protective layer 6 and the etching stop
insulating layer 7 while defining a channel therebetween.

[0063] Step (5): as shown in FIG. 1(e), on the substrate after step (4) a
passivation layer film is deposited, and then through a fifth
photolithography process, is formed into the pattern of the passivation
layer 10 having a via hole 12, and the via hole 12 is located over the
drain electrode 9 while exposing a part of the drain electrode 9.

[0064] Step (6): as shown in FIG. 1(f), on the substrate after step (5) a
transparent conductive film is deposited, and then through a sixth
photolithography process, is formed into a pattern of the transparent
pixel electrode 11, and the transparent pixel electrode 11 is provided
above the via hole 12 and contact the transparent pixel electrode 11 with
the drain electrode 9 via the via hole 12.

[0065] In this embodiment, the etching process of the respective
photolithography processes can be implemented with dry etching.

[0067] In one example, the semiconductor protective layer adjacent to the
semiconductor layer 5 comprises a composite lamination structure formed
in the channel 15, i.e., comprises an etching stop protective layer 6 and
an etching stop insulating layer 7.

[0068] In another example, the semiconductor protective layer adjacent to
the semiconductor layer 5 comprises a composite lamination structure
comprising a buffer insulating layer 14 and a buffer insulating
protective layer 13, located between the semiconductor layer 5 and the
base substrate 1.

[0069] In yet another example, the semiconductor protective layer adjacent
to the semiconductor layer 5 comprises both of the above cases so as to
provide protection for the semiconductor layer 5 at the upper side and
lower side thereof

[0070] Similarly, the TFT array substrate in this embodiment is used, for
example, for a vertically-driven type or horizontally-driven type liquid
crystal display; however, this invention is not limited thereto.

[0071] In this embodiment, the material, the thickness and the formation
process for the buffer insulating layer 14 may be the same as that of the
gate insulating layer 3/etching stop insulating layer 7 in the first
embodiment.

[0072] In this embodiment, the material, the thickness and the formation
process for the buffer insulating protective layer 13 may be the same as
that of the gate insulating protective layer 4/etching stop protective
layer 6 in the first embodiment.

[0073] In this embodiment, the gate insulating layer 3 does not directly
contact with the semiconductor layer 5 and thus can adopt a monolayer
structure, and the material, the thickness and the formation process for
this monolayer structure maybe the same as that of the gate insulating
layer 3/etching stop insulating layer 7 in the first embodiment and also
maybe the same as that of the gate insulating protective layer 4/etching
stop protective layer 6 in the first embodiment.

[0074] The material, the thickness and the formation process for the other
layers constituting the array substrate structure of this embodiment may
be the same as that in the first embodiment, and therefore its detailed
description is omitted here.

[0075] The semiconductor layer 5 is formed of a metal oxide semiconductor
material, for example, a transparent amorphous oxide semiconductor IGZO
(In--Ga--Zn--O), for example, through sputtering method, and the
thickness thereof is in a range from 50 Åto 1000 Å.

[0076] Due to the fact that the semiconductor protective layer, comprising
a composite lamination structure formed of the above materials, will not
seize the oxyanion in the semiconductor layer 5, the stability of the TFT
array substrate is improved, and also the etching speed upon the gate
insulating layer and the etching stop layer is increased, which promotes
productive capacity and is suitable for large-scale production.

[0077] The TFT array substrate in this embodiment maybe formed through six
photolithography processes, for example. One exemplary workflow is
described as follows with reference to FIGS. 2(a)-(f).

[0078] Step (1): as shown in FIG. 2(a), on the base substrate 1 two layers
of buffer insulating films and a metal oxide film are sequentially
deposited, and then through a first photolithography process, are formed
into the patterns of the buffer insulating layer 14, the buffer
insulating protective layer 13 and the semiconductor layer 5; the buffer
insulating protective layer 13 covers the buffer insulating layer 14 and
have the same plane size as that of the buffer insulating layer 14, and
the buffer insulating layer 14 covers the base substrate 1.

[0079] Step (2): as shown in FIG. 2(b), on the substrate after step (1)
two layers of etching stop insulating films are deposited, and through a
second photolithography process, are formed into the patterns of the
composite lamination structure of the etching stop protective layer 6 and
the etching stop insulating layer 7; the etching stop insulating layer 7
covers the etching stop protective layer 6 and has the same plane size as
that of the etching stop protective layer 6, and the etching stop
protective layer 6 is located onto and contact the semiconductor layer 5.

[0080] Step (3): as shown in FIG. 2(c), on the substrate after step (2) a
source-drain metal film is deposited, and through a third
photolithography process, is formed into the patterns of the source
electrode 8, the drain electrode 9 and the data scanning line (not shown
in the figures), and the source electrode 8 and the drain electrode 9 are
located on the semiconductor layer 5 and provided respectively on both
sides of the etching stop protective layer 6 and the etching stop
insulating layer 7.

[0081] Step (4): as shown in FIG. 2(d), on the substrate after step (3) a
gate insulating film is deposited, and then through a fourth
photolithography process, is formed into the patterns of the gate
insulating layer 3 and the via hole 12, and the via hole 12 is arranged
over the drain electrode 9.

[0082] Step (5): as shown in FIG. 2(e), on the substrate after step (4) a
transparent conductive film is deposited, and then through a sixth
photolithography process, is formed into a pattern for the transparent
pixel electrode 11, and the transparent pixel electrode 11 is provided
above the via hole 12 and is connected with the transparent pixel
electrode 11 with drain electrode 9 via the via hole 12.

[0083] Step (6): as shown in FIG. 2(f), on the substrate after step (5) a
gate metal film is deposited with, and then through a sixth
photolithography process, is formed into the patterns of the gate
electrode 3 and the gate scanning line (not shown in the figure).

[0084] In this embodiment, the etching process of respective
photolithography processes may be implemented with dry etching.

[0085] Obviously, various alternation and modification can be made by the
ordinary skilled in this art, without departing from the spirit and
essence of the present invention, which can also be regarded as the
protective scope of this invention.

Patent applications by Jianshe Xue, Beijing CN

Patent applications by Xiang Liu, Beijing CN

Patent applications by BOE TECHNOLOGY GROUP CO., LTD.

Patent applications in class In array having structure for use as imager or display, or with transparent electrode

Patent applications in all subclasses In array having structure for use as imager or display, or with transparent electrode