In these days of processor optimization packages (POPs) the lines are becoming blurred. Even if a company had taken an architectural license it might make sense to take a proven design as a starting point and then deviate from it for design purposes. There may also a lot more advantage to be achieved by innovating at a higher, or indeed lower, level of abstraction.

[Get a 10% discount on ARM TechCon 2012 conference passes by using promo code EDIT. Click here to learn about the show and register.]

For example, one way to innovate would be to take the Cortex-A15 core and apply the Fast14 technology Apple got hold of when it acquired Intrinsity Inc., confirmed in April 2010. Fast14 applies dynamic or domino logic constructs and novel signal encodings that can make logic and arithmetic units faster while consuming less power. This in turn might have implications for instruction pipelines and arithmetic logic units. Changes there might then require the use of an architectural license.

Similarly innovation in an area such as so-called "big-little" processing might make for a bigger power saving in operation than building a processor core from the ground up. Big-little was first discussed by ARM in 2011 at the announcement of the Cortex-A7 processor core. It is the method whereby a pairing of a high-performance processor core and a power-efficiency tuned processor core share processing duties in a cache-coherent combination with an overall power-saving advantage. The Cortex-A15 and Cortex-A7 were introduced as a big-little pairing that could use this technique with the forecast that chips including such pairings would appear in 2013.

But that does not mean that Apple might not have been working this ground in parallel under the architectural license.

Of course Apple may have created a completely novel processor core AND innovated with Fast14 and big-little power saving.

All of which could explain why the Apple A6 processor has, on separate occasions, been described as both a four-core and a dual-core processor and as a Cortex-15 implementation and as a custom implementation.