Brad Howe, vice president of IC engineering at programmable logic vendor Altera Corp. said in a statement that IC Compiler's technologies such as concurrent multicorner/multimode optimization and in-design automatic DRC repair were a strong enabler to enable Altera to achieve performance and area targets and meet the tight design schedule for its forthcoming Stratix V FPGAs.

The new release of IC Compiler also provides power-sensitive designers with access to a leakage optimization engine integrated in IC Compiler, Synopsys said. Recommended for final-stage leakage recovery on a close-to-tapeout design, this engine is architected to deal with a multitude of cell variants to deliver optimal leakage reduction while preserving timing, according to the company.

This new release also delivers up to 10 percent lower out-of-the-box clock tree power and a 10 percent reduction in total buffer count for reduced dynamic power consumption, according to Synopsys. Additional quality-of-results improvements include advances in clock feasibility, signal integrity and electro-migration closure, Synopsys said.

Also Monday, Synopsys released version 2010.12 of its Galaxy Implementation Platform. The latest Galaxy Platform release includes new technologies to address the scalability, convergence and throughput needs of "gigascale" design, Synopsys said. The latest release also includes comprehensive foundry-validated 28-nm silicon process node support for all routing and DRC rules, extraction and lithography requirements, Synopsys said.