Foundry Files Blog

FDX “Not a Niche” Technology

Of all of the numbers claimed for the GLOBALFOUNDRIES fully depleted SOI technology, the one that stands out in my mind is 39.

That is the number of mask layers required to create a 22nm fully depleted SOI chip, one with eight metal layers. And it compares, said Jamie Schaeffer, the FDX™ program director, with 60 masks for a comparable chip with FinFET transistors.

Of course, comparisons between FinFET and FD-SOI technologies are inexact. Each have their merits. With FD-SOI, the starting SOI wafer costs several times more than a bulk wafer. There are drive current differences. But consider how many more delicate fin-creating etch steps, how many more multi-passes through expensive scanners, are represented by those extra 21 mask layers. Then it starts to become clear that FD-SOI may provide cost advantages that were not really there when the competition was between bulk planar and SOI planar technologies.

Continuity Concerns

22FDX® designs are prototyping now, with risk production in Q1 2017. The recently announced 12FDX™ technology moves to commercial production in 2019. Dan Hutcheson, CEO of VLSI Research Inc., surveyed 75 decision-makers at six chip companies, six EDA and IP vendors, and two universities, and found that one of their concerns was continuity.

“One of the issues expressed in the survey was ‘Is there a future?’ They wanted to make sure there was a next node” to FD-SOI technology.

Schaeffer also tagged the importance of the succession factor. “The entire FDX roadmap, integrating 22 and 12FDX, provides a complementary path to FinFETs,” he said.

However, Schaeffer took slight umbrage when I asked a question that implied that the real volumes will remain in the FinFET arena, with processors and graphics chips, while FDX would be well-suited to the smaller potatoes, to the design teams that didn’t quite have the resources to tackle a FinFET project.

“We are not doing this as a niche technology,” he replied. “We are targeting high-volume opportunities—transceivers, WiFi, vision processing, and automotive. We intend to fill a large volume of our Fab 1 in Dresden, and have plans in place from a capacity perspective,” Schaeffer said.

GLOBALFOUNDRIES 22FDX is Manufactured in Europe’s Largest 300mm Factory

That word, transceivers, is key to the FDX program. The 22FDX transistors exhibit an Fmax in the 325 GHz range, capable of meeting the nascent 5G cellular specification.

Schaeffer said that the 22FDX and 12FDX technologies provide “a unique opportunity to integrate mmWave transceivers with ADCs, DACs and digital baseband. FinFETs provide the digital scaling but not the RF performance that is needed at mmWave frequencies. In the IoT market, FDX technology could support microcontroller-based SoCs with integrated low-power wireless. It also could come into play for products based on the new gigabit-class WiFi standards. And depending how quickly the 5G cellular standard is firmed up and how it fits in with the assisted-driving cars of the future, FDX may find large volumes in the automotive space.

Analog Friendly

Hutcheson said he was skeptical of SOI until he undertook the VLSI Research survey, and talked to device physicists about the relative merits of FinFETs and SOI transistors. “When we surveyed design engineers, they said that for analog, SOI is much better than FinFETs.”

Dick James, senior fellow at ChipWorks (Ottawa), said that analog designers depend on an ability to adjust the width of their transistors. With FinFET-based circuits, designers deal with “a quantized transistor width,” adjusting transistor widths by using multiple fins. “With planar transistors, analog designers can tune their circuits by putting wider transistors wherever they want,” James said.

The debate over power consumption also tilts in favor of SOI, James said. With the buried oxide layer (BOX), “every transistor, theoretically, can be surrounded by an insulation layer, and that helps control leakage and parasitics.”

Back-biasing also plays a role in controlling power by raising the threshold voltage and reducing leakage where appropriate, he said.

The debate over the relative merits of bulk FinFETs versus SOI technology has been going on for decades now, picking up intensity in the summer of 1998 when IBM formally announced that it would turn to SOI for its server processors. Intel vehemently supported its continued path on bulk silicon, ultimately leading to FinFETs, which have occupied center stage for much of the last decade.

Now the FD-SOI or FinFET debate – where each fits in today’s technology spectrum — is reaching a new level of intensity, one that will play out in the marketplace.

But why 22? Why not call it FDX20? And why 12, instead of using the 10nm delineation favored by others? This goes back to the cost-of-production issue. With 22nm design rules, Schaeffer said, single-pass patterning is sufficient. No double patterning is necessary. With 12nm, double-patterning gets the job done on critical layers, obviating the need for triple or quad patterning.

There you go. With 39 mask layers, superior carrier frequencies at low power, FDX could provide an alternative to FinFETs, especially in markets where the combination of transistor density and good RF performance is valued. Let the competition begin.

About Author

Dave Lammers

Dave Lammers started writing about the semiconductor industry while working at the Associated Press Tokyo bureau in the early 1980s, a time of rapid growth for the industry. He joined E.E. Times in 1985, covering Japan, Korea, and Taiwan for the next 14 years while based in Tokyo. In 1998 Dave, his wife Mieko, and their four children moved to Austin to set up a Texas bureau for E.E. Times. A graduate of the University of Notre Dame, Dave received a master’s in journalism at the University of Missouri School of Journalism.