Comment: Clockless DSP offers superior performance

A session on data-converter techniques at the recent ISSCC included a paper on a clockless ADC/DSP/DAC [1] by Bob Schell and Yannis Tsividis of Columbia University. The basic idea is to use a continuous-time DSP instead of sampling and conventional clock signals. The result: no aliasing and no tones at frequencies not related to the input. Since the scheme is driven by signal activity, the power dissipation goes down as the input activity decreases. Chalk one up for asynchronous A/D converters.

The converter uses a level-crossing detector that continuously tracks the input (Figure 1). The detector outputs signals indicating the timing and direction of level changes. This data goes through a 16-tap FIR filter that produces an 8-bit word. Figure 2 shows measured results for a voice band system. Note the lack of aliasing—there are no "image" frequencies or beating of input and sampling frequencies. SNR results compare very favorably with conventional architectures, with a noise floor 5.4 dB lower than regular 8-bit systems.

Figure 1. Operation of delta modulator encoding of input, delaying of information, and reconstruction by the first accumulator/multiplier block.

About the authorShiv Balakrishnan has more than 25 years of experience in signal processing including 12 years at Tektronix. He has held engineering and technical marketing positions in startups as well as Fortune 500 companies like Philips, Sun and TI. His consulting work spans the range from signal processing system design to market research and competitive analysis. Shiv is named co-inventor on multiple DSP and wireless patents. His undergraduate degree is from the Indian Institute of Technology and graduate studies were at the University of Florida and Purdue University.