HTR to DCC2 links use National DS90CR285/286 Channel Link technology. These are in principle
28 bit links but we only use 24 of them. The low-level link format is as shown in the table below
from 2008 onwards.

Of the 24 bits, 16 are used for data. Of the remaining 8, originally two were used for framing bits
(named S0, S1) and the other 6 were for ECC coding. The original format is described here. This was changed due to the PCB layout
problem described here
in ~2008.

In the DCC2, a Channel Link receiver is not used but instead a deserializer implemented in
a Spartan-3 FPGA.