Slideshow: Lam Eyes Next $1B Opportunity

SANTA CLARA, Calif. -- At 70, David K. Lam is as excited as ever about the future of the semiconductor industry and what he says is his billion-dollar opportunity to nudge it forward for the second time.

Thirty years ago, Lam helped establish the plasma etcher that became a workhorse tool for cutting fine lines in chips. By fielding a reliable, automated version of the tool, the company that bore his name became the first founded by an Asian American to go public on NASDAQ.

Today he has a new venture he thinks could give the industry a lift at a time when it's getting hard to keep making chips faster, smaller, and cheaper. This time Lam is taking what many have seen as a rival technology -- direct electron-beam lithography -- and bringing it into the conventional process flow.

"In the old days most new semiconductor technologies were disruptive now they have to be complementary -- you have to find ways to use what you have," said Lam.

Chip giants Intel and Taiwan Semiconductor Manufacturing Co. each pitched in a cool billion dollars last year to help finish development of extreme ultraviolet lithography. EUV is widely seen as the successor to today's immersion lithography used to print ever finer lines on chips.

EUV has been delayed many times. It involves a huge set of engineering efforts, perhaps rivaled only by putting a man on the moon. The delays forced engineers time and again to find ways to extend the current immersion lithography to keep alive Moore's Law of producing a generation of smaller, faster cheaper chips every two years or so.

But now immersion is showing signs it is running out of gas and EUV is still not ready. This year for the first time fabs are running wafers twice through the immersion machines to print lines for 20nm chips, adding time and cost to an already complex and expensive process.

If EUV doesn't come in time for the next generation at 14 nm they may have to use four passes, a.k.a. quad patterning, for some critical layers. Intel has said it sees a path to using quad patterning cost effectively even down to 10nm, but others shudder at the thought.

"When you go to quad or more patterns, the cost are astronomical," said Lam. "It's not just the mask costs but cycle times, time-to-market and the complexity of the process that really effects yield -- we lump it all these together in total costs."

Lam shows estimates (above) of lithography rising from 25 percent of the costs of making a chip in 1984 to 70 percent today. "By 2018 if we don't have EUV and have to go to quad or octal patterning, it will drive costs through the roof -- it's unsustainable," Lam said.

Multibeam's e-beam system could eliminate many of the extra steps, Lam claims. The exact number of reduced steps varies based on how a fab uses the technique.

Multibeam got its start as one of a handful of efforts to find an alternative to EUV, using electron beams to write directly on wafers without using masks. But recently, Lam made a course change at Multibeam to parallel rather than collide with the lumbering industry effort.

With EVU still a distant reality, other technologies are drawing industry attention. EUV has been delayed so many times that its inclusion at 10nm is still not sure. Post 10nm, the problems for which EUV was envisioned will remain the same. We will need to look for reducing the wavelength to increase NA. I wonder why industry is still betting for EVU and not putting some money and faith to other technologies.

I agree the opportunity for a non-EUV lithography is opening up wider. EUV like immersion has issues with increasing NA. E-beam seems to be the dominant alternative. At the same time, there is a common sentiment that putting too many electrons through a small area (especially directly into an insulated device) cannot have good clean consequences. But that is exactly what is needed for overcoming shot noise, more electrons per sq. nm. But this need might not be necessary for ArF immersion masks which cannot shrink 4x feature sizes below ~160 nm anyway. So I think this plan still works out well for mask writing.

ASML rcently indicated it is seeking an additional 1.7B in funding to prepare for EUV and 450mm HVM in 2018. This delay is an opportunity for eBeam lithography to provide complementary 1D line cut support of multi-patterned 193i lithography required to sustain HVM >10nm. Enhanced eBeam performance drawing from Model Based Mask Data Prep (MB-MDP) can be implemented so that discrete structures and patterns can be addressed individually with specific shot tasking providing superior control of dose margin. Called Shot or Dose Modulation, this is a new technique of assigning optimized electron beam energy and current to specific devices or geometries. This can enhance eBeam dose control accuracy over a chip (and wafer) potentially improving LER and minimizing shot noise typically encountered with contact holes and complex geometries. Refinement of this technique might be the best approach to minimizing shot noise.

"The real problem is not the doses per se, but the "shot noise". Shot noise is a stochastic, or statistical, process involving some electrons "spilling over" to the edge of the patterned feature making the edge jagged, leading to "line-edge roughness", or LER. The smaller the feature the more serious the problem, and the problems plagues all lithographic technologies: 193nm Optical, EUV and E-Beam. It's a random process due to probability and there is no real cure. However, the problem can be mitigated. Mitigating processes are practiced at fabs today to reduce the effect of shot noise and improve LER when needed. "

Pretty impressive that the man is still so passionate about technology at age 70. I never heard that before about Lam being the first company founded by an Asian American to go public. That's pretty cool.