A topology for single-chip implementation of computing structures based on shuffle-exchange (SE)-type interconnection networks is presented. The topology is suited for structures with a small number of processing elements (i.e. 32-128) whose area cannot be neglected compared to the area required for interconnection. The processing elements are implemented in pairs that are connected to form a ring. In this way three-quarters of the interconnections are between neighbors. The ring structure is laid out in two columns and the interconnection of nonneighbors is routed in the channel between the columns. The topology has been used in a VLSI implementation of the add-compare-select (ACS) module of a fully parallel K=7, R=1/2 Viterbi decoder. Both the floor-planning issues and some of the important algorithm and circuit-level aspects of this design are discussed. The chip has been designed and fabricated in a 2- mu m CMOS process using MOSIS-like simplified design rules. The chip operates at speeds up to 19 MHz under worst-case conditions (V/sub DD/=4.75 V and T/sub A/=70 degrees C). The core of the chip (excluding pad cells) is 7.8*5.1 mm/sup 2/ and contains approximately 50000 transistors. The interconnection network occupies 32% of the area.>