The DesignWare MIPI M-PHY IP supports HS Gear1, Gear2, Gear3, and Gear4 rates ranging from 1.248 Gbps to 11.6 Gbps. Low-speed capabilities are available via Type-1 M-PORTS with Gear1 to Gear5 PWM modes and Type-II M-PORTS, allowing for SYS-BURST mode. The M-PHY’s modular architecture allows implementation of a variety of transmitter and receiver lanes to meet a broad range of applications and all the modes outlined in the protocol specification. A sophisticated clock recovery mechanism and power efficient clock circuitry are designed to guarantee the integrity of the clocks and signals needed to meet strict timing requirements. The DesignWare MIPI M-PHY IP supports large and small amplitudes, slew rate control and dithering functionality for optimized electromagnetic interference (EMI).