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Abstract:

Carbon nanotube template arrays may be edited to form connections between
proximate nanotubes and/or to delete undesired nanotubes or nanotube
junctions.

Claims:

1.-25. (canceled)

26. A carbon nanotube (CNT) circuit template, comprising:a plurality of
isolated CNT segments, the CNT segments interconnecting to form
electrically-responsive junctions,wherein at least one of the CNT
segments or at least one of the junctions is configured to exhibit a
nonlinear current-voltage response, and wherein at least one of the CNT
segments or at least one of the junctions is configured for selective
deletion by means of application of electromagnetic energy.

27. The CNT circuit template of claim 26, wherein the CNT segments are
arranged in a rectilinear array.

28. The CNT circuit template of claim 26, wherein the CNTs are arranged in
a hexagonal pattern.

29. The CNT circuit template of claim 26, wherein the CNTs are arranged in
a three-dimensional pattern.

30. The CNT circuit template of claim 26, wherein the template includes at
least one junction connecting at least three segments.

31. The CNT circuit template of claim 26, wherein the template includes at
least one junction connecting exactly three segments.

32. The CNT circuit template of claim 26, wherein the CNT segments include
at least one semiconducting CNT segment.

33. The CNT circuit template of claim 26, wherein the CNT segments include
at least one metallic CNT segment.

34.-51. (canceled)

52. A carbon nanotube (CNT) circuit template, comprising:a first array of
substantially parallel, laterally separated CNTs;a second array of
substantially parallel, laterally separated CNTs arranged at an angle to
the first array of CNTs; andan intermediate layer disposed between the
first array of CNTs and the second array of CNTs;wherein the intermediate
layer includes a material configured to be removed or deactivated by
exposure to an energy, permitting at least one CNT of the first array of
CNTs to contact at least one CNT of the second array of CNTs.

53. A carbon nanotube (CNT) circuit template, comprising:a plurality of
isolated CNT segments, the CNT segments interconnecting to form
electrically-responsive junctions,wherein at least one of the CNT
segments or at least one of the junctions is configured to exhibit a
nonlinear current-voltage response, and wherein at least one of the CNT
segments or at least one of the junctions is configured for selective
deletion by means of chemically attacking the at least one segment or
junction.

54. The CNT circuit template of claim 53, wherein chemically attacking the
at least one segment or junction includes applying an activatable
composition to the at least one segment or junction, and selectively
activating the activatable composition.

55. The CNT circuit template of claim 54, wherein the activatable
composition is photosensitive, and wherein selectively activating the
activatable composition includes applying electromagnetic energy to the
activatable composition.

56. The CNT circuit template of claim 54, wherein the activatable
composition is an enzyme.

57. The CNT circuit template of claim 54, wherein the activatable
composition includes a nucleotide.

Description:

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001]The present application is related to and claims the benefit of the
earliest available effective filing date(s) from the following listed
application(s) (the "Related Applications") (e.g., claims earliest
available priority dates for other than provisional patent applications
or claims benefits under 35 USC §119(e) for provisional patent
applications, for any and all parent, grandparent, great-grandparent,
etc. applications of the Related Application(s)).

RELATED APPLICATIONS

[0002]For purposes of the USPTO extra-statutory requirements, the present
application constitutes a continuation-in-part of U.S. patent application
Ser. No. ______, entitled CONNECTIBLE NANOTUBE CIRCUIT, attorney docket
no. 0505-026-001B-000000, naming Roderick A. Hyde, Muriel Y. Ishikawa,
Nathan P. Myhrvold, Clarence T. Tegreene, Charles Whitmer, and Lowell L.
Wood, Jr. as inventors, filed contemporaneously herewith, which is
currently co-pending, or is an application of which a currently
co-pending application is entitled to the benefit of the filing date.

[0003]For purposes of the USPTO extra-statutory requirements, the present
application constitutes a continuation-in-part of U.S. patent application
Ser. No. ______, entitled NANOTUBE CIRCUIT ANALYSIS SYSTEM AND METHOD,
attorney docket no. 0505-026-001C-000000, naming Roderick A. Hyde, Muriel
Y. Ishikawa, Nathan P. Myhrvold, Clarence T. Tegreene, Charles Whitmer,
and Lowell L. Wood, Jr. as inventors, filed contemporaneously herewith,
which is currently co-pending, or is an application of which a currently
co-pending application is entitled to the benefit of the filing date.

[0004]The United States Patent Office (USPTO) has published a notice to
the effect that the USPTO's computer programs require that patent
applicants reference both a serial number and indicate whether an
application is a continuation or continuation-in-part. Stephen G. Kunin,
Benefit of Prior-Filed Application, USPTO Official Gazette Mar. 18, 2003,
available at
http://www.uspto.gov/web/offices/com/sol/og/2003/week11/patbene.htm. The
present applicant entity has provided above a specific reference to the
application(s) from which priority is being claimed as recited by
statute. Applicant entity understands that the statute is unambiguous in
its specific reference language and does not require either a serial
number or any characterization, such as "continuation" or
"continuation-in-part," for claiming priority to U.S. patent
applications. Notwithstanding the foregoing, applicant entity understands
that the USPTO's computer programs have certain data entry requirements,
and hence applicant entity is designating the present application as a
continuation-in-part of its parent applications as set forth above, but
expressly points out that such designations are not to be construed in
any way as any type of commentary and/or admission as to whether or not
the present application contains any new matter in addition to the matter
of its parent application(s).

[0005]All subject matter of the Related Applications and of any and all
parent, grandparent, great-grandparent, etc. applications of the Related
Applications is incorporated herein by reference to the extent such
subject matter is not inconsistent herewith.

BACKGROUND

[0006]According to the International Technology Roadmap for Semiconductors
(ITRS), device sizes will continue to shrink, roughly in accordance with
Moore's Law (which predicts a doubling of the number of transistors per
unit area every 1.5-2 years). As device size requirements grow ever more
stringent, traditional silicon lithography techniques may become
inadequate, requiring a shift in materials and/or in circuit design
techniques to keep pace with demands for improved performance.

SUMMARY

[0007]In one aspect, a method of constructing a circuit comprises
providing an array of carbon nanotubes including a plurality of segments.
At least a subset of the segments intersect to form electrically
responsive junctions. The method further includes selectively
inactivating at least one segment or junction. Inactivating may including
application of electromagnetic energy (e.g., by directing a laser towards
the segment or junction), application of an electron beam, chemical
attack (e.g., by an activatable composition such as a photochemical, an
enzyme, or a targetable composition such as a nucleotide-containing
composition), and/or application of a voltage. Application of a voltage
may include applying the voltage to segments and/or to junctions, and may
include application of timed pulses, which may be timed to temporally
overlap at a common center (such as the segment or junction to be
inactivated). The carbon nanotubes may be arranged, for example, in a
rectilinear array, a hexagonal pattern, or a three dimensional pattern,
and may include junctions connecting at least or exactly three segments.
Providing the array of carbon nanotubes may include growing the carbon
nanotubes along selected paths. The carbon nanotubes may include
semiconducting nanotubes and/or metallic nanotubes. The method may
further include measuring an electrical property of at least one segment
or junction, and may in addition selecting a segment or junction to
inactivate in response to the measured electrical property.

[0008]In another aspect, a carbon nanotube circuit template includes a
plurality of carbon nanotube segments that interconnect to form
junctions. At least one of the segments or at least one of the junctions
exhibits a nonlinear current-voltage response, and at least one of the
segments or at least one of the junctions is deletable. The carbon
nanotubes may be arranged, for example, in a rectilinear array, a
hexagonal pattern, or a three dimensional pattern, and may include
junctions connecting at least or exactly three segments. The carbon
nanotubes may include at least one semiconducting segment and/or at least
one metallic segment. At least one of the carbon nanotubes may be
deletable by application of electromagnetic energy (e.g., by directing a
laser towards the segment or junction), application of an electron beam,
chemical attack (e.g., by an activatable composition such as a
photochemical, an enzyme, or a targetable composition such as a
nucleotide-containing composition), and/or application of a voltage.

[0013]Single-walled carbon nanotubes (SWCNTs) may be metallic or
semiconducting depending on their chirality. Individual SWCNTs have a
chirality defined by circumferential vector (n,m) in terms of graphite
lattice units. When (n-m)/3 is an integer, the SWCNTs generally behave as
metals, while other SWCNTs generally behave as semiconductors. Fuhrer II
found three types of behavior for crossed SWCNTs, depending on whether
the constituent CNTs were metallic-metallic (MM),
semiconducting-semiconducting (SS), or metallic-semiconducting (MS). MM
junctions and SS junctions exhibited roughly linear I-V behavior, with MM
conductivities in the range of 0.086-0.26 e2/h and SS conductivities
in the range of at least 0.011-0.06 e2/h. MS junctions exhibited
nonlinear I-V behavior, with much lower conductivities in the linear
range and with a Schottky barrier of 190-290 meV. Theoretical
calculations (see, e.g., Buldum, et al. "Contact resistance between
carbon nanotubes," Phys. Rev. B 63:161403(R) (April 2001), incorporated
herein by reference) suggest that the conductivity of such junctions may
be a sensitive function of atomic structure in the contact region (e.g.,
registration of hexagon structures in adjacent nanotubes).

[0014]CNTs may also be fabricated in a Y-shape, in which three nanotubes
converge at a junction (see, e.g., Papadapoulos "Electronic Transport in
Y-Junction Carbon Nanotubes," Phys. Rev. Lett. 85(16):3476-3479,
incorporated herein by reference). Such systems (and the special subset
of T-shaped junctions) have been computationally modeled and found to
exhibit current rectification (see, e.g., Srivastava, et al.,
"Computational Nanotechnology with Carbon Nanotubes and Fullerenes,"
Comp. Sci. Eng. 3(4):42-55 (July/August 2001), incorporated herein by
reference). Experimental results (Papadapoulos, supra) confirm rectifying
behavior.

[0015]The rectifying structures described above may be combined to form
more complex circuit elements (e.g., logic gates, such as those described
in Derycke, et al., "Carbon Nanotube Inter- and Intramolecular Logic
Gates," Nano Lett., 1(9):453-456 (August 2001), incorporated herein by
reference) and circuits (e.g., a scalable one-bit adder, described in
Patwardhan, supra), using conventional circuit design principles.

[0016]As shown in FIG. 1, a template device comprises two arrays of CNTs
10, 12 set at an angle to one another (90 degrees as shown, but other
angles may also be used). An intermediate layer 14 is interposed between
the two arrays of CNTs. (FIG. 1 is shown in exploded view for clarity; in
most embodiments, the CNTs 10, 12 will be in contact or at least in close
proximity to intermediate layer 14.) As shown, the intermediate layer 14
is a flat layer, but in other embodiments, it may be a coating on the
CNTs or have any other physical configuration that interposes it between
CNTs of the two arrays. The CNTs of each array may be metallic,
semiconducting, or a mixture of both types. In the configuration shown in
FIG. 1, the CNTs of the first array 10 are insulated from the CNTs of the
second array 12 by the intermediate layer.

[0017]FIG. 2 shows a plan view of the template device of FIG. 1 after
selective editing of the intermediate layer 14. As seen at junction 16,
the intermediate layer is removed, allowing a CNT of the first array 10
and a CNT of the second array 12 to contact one another to form a
junction. In addition, segment of CNT 18 has been removed between two
additional junctions 20. In some embodiments, segments or junctions may
be removed by an electron beam, ion beam, and/or a laser beam, either by
direct etching or by illumination followed by a chemical development
process. In other embodiments, segments or junctions may be removed by
application of a voltage, for example by application of one or more timed
pulses along the CNTs that are selected to temporally overlap at a common
center, or by application of a voltage directly to a junction or segment.
By selecting junctions at which the CNTs may be connected and segments or
junctions in which they may be removed, complex circuits of CNTs can be
built up in the template. In other embodiments, additional intermediate
layers and CNT arrays may be added to increase the available complexity.

[0018]The intermediate layer 14 may comprise any material that serves to
separate the CNTs and that can be selectively removed or deactivated. In
some embodiments, the intermediate layer may comprise a resist
composition, which may be removed by conventional lithographic techniques
(including but not limited to photoresist, e-beam resist, or X-ray
resist). In other embodiments, the resist may comprise a material that
can be locally removed or deactivated by application of a voltage between
the first selected CNT and the second CNT, potentially obviating the need
for lithographic systems.

[0019]The arrays of CNTs 10 and 12 may be formed by a variety of methods,
including but not limited to pick-and-place, self-assembly of
already-formed CNTs (e.g., by the methods of Dwyer, et al., "The Design
of DNA Self-Assembled Computing Circuitry," IEEE Trans. VLSI Sys.,
12(11):1214-1220 (November 2004), incorporated herein by reference), or
in situ growth of CNTs (e.g., by the methods of Jung, et al., "Mechanism
of Selective Growth of Carbon Nanotubes on SiO2/Si Patterns," Nano
Lett. 3(4):561-564 (March 2003), incorporated herein by reference). Some
of these methods may lend themselves to production of CNTs having
particular chiralities and/or conductivities, while others may produce
arrays of CNTs having a distribution of chiralities and/or
conductivities.

[0020]In embodiments where the chiralities and/or conductivities are not
known a priori, it may be desirable to interrogate the material
properties of individual CNTs in order to determine appropriate
connections and/or deletions (e.g., by electrical testing, plasmon
interactions, optical testing, atomic force microscopy, and/or other
types of microscopy). In still other embodiments, it may be desirable to
interrogate properties of individual CNTs or of groups of CNTs to locate
regions having desired properties after some or all of the connections
and/or deletions have been made. In yet other embodiments, it may be
desirable to examine physical properties, as well as or instead of
electrical properties, of CNTs and junction during any point in the
process to determine additional connections and/or deletions or other
configurational aspects. Physical properties may include, but are not
limited to, location, size, defect location, and/or chemical environment.

[0021]FIG. 3 shows an interconnected set of CNTs including Y junctions 30.
Such an interconnected set may be produced, for example, by welding of
long nanotubes (see, e.g., Terrones, et al., "Molecular Junctions by
Joining Single-Walled Carbon Nanotubes," Phys. Rev. Lett. 89(7):075505
(August 2002), and Krasheninnikov, et al., "Ion-irradiation induced
welding of carbon nanotubes," Phys. Rev. B, 66:245403 (2002), both of
which are incorporated herein by reference). Arrays of Y-branched CNTs
have also been produced by Papadopoulos, supra; these can be
interconnected by similar techniques, or by the selective interconnection
technique illustrated in FIGS. 1 and 2. In some embodiments, production
of such interconnected sets of CNTs may be effectively random, while in
other embodiments, CNTs may be interconnected in a predictable pattern.

[0022]In either case, sections 32 of the interconnected set 30 may be
determined to act as logic gates or other desired circuit elements or
circuits. In some embodiments, such sections may be located by
determination of the chirality and/or conductivity of individual segments
within the interconnected set by empirically determining the electrical
properties of a interconnected set through application of voltages to
selected "input" CNTs 34 and measurement of selected "output" CNTs 36, or
by a combination of these methods (e.g., by determining chirality of
selected "input" and "output" CNTs, identifying interconnecting junctions
between them, and applying signals to the CNTs to determine behavior of
the set of input CNTs, output CNTs, and interconnecting junctions). In
some embodiments, segments or junctions of the interconnected set 30 may
be deleted as discussed above. Such deletion may occur before, during, or
after any measurement of properties of the interconnected set.

[0023]In a large interconnected set 30, many sections 32 having desired
circuit properties may be present (either by design and controlled
self-assembly, or by chance). Once identified as discussed above, these
sections may be isolated from the interconnected set, either physically
(by cutting junctions outside the desired section and moving it to a
desired location), or effectively, by disconnecting segments of junctions
not in the desired section to leave only continuous CNTs (which may
function as leads) connected to the desired section inputs and outputs.

[0024]In some embodiments, template structures such as those shown in
FIGS. 1 and 3 may be constructed in bulk, and then individually edited to
form custom circuits. In such embodiments (and in particular in
embodiments in which the chiralities and/or conductivities of individual
CNTs are not known a priori), the determination of which CNT sections to
connect and/or delete may be made using customized software.

[0025]In some embodiments, the customized software accesses a model of a
CNT template structure (using measurements of properties of CNTs in the
particular template if appropriate) and identifies the effect of editing
the CNT template structure, either by deleting segments or junctions, or
by forming connections between segments in physical proximity. The model
includes the electrical behavior of the CNT segments and junctions of the
template (e.g., the rectifying properties or lack thereof of individual
junctions, and/or the conductivities of the CNT segments).

[0026]In some embodiments, the customized software may determine circuit
behavior from first principles. In other embodiments, the software may
store schematics for building block structures (including by way of
nonlimiting example the logic gates and adders discussed above), and
allow circuit designers to specify circuit designs using conventional
methods. The software then locates regions within the model of the
template structure that could be modified as discussed above to implement
the particular designs. In some embodiments, a computer-based system may
then control the application of voltages, dynamic masks, serial e-beam
etchers, or whatever other editing tools were appropriate to produce the
desired circuit on a particular template structure.

[0027]Those having skill in the art will recognize that the state of the
art of circuit design has progressed to the point where there is
typically little distinction left between hardware and software
implementations of aspects of systems. The use of hardware or software is
generally a design choice representing tradeoffs between cost,
efficiency, flexibility, and other implementation considerations. Those
having skill in the art will appreciate that there are various vehicles
by which processes, systems and/or other technologies involving the use
of logic and/or circuits can be effected (e.g., hardware, software,
and/or firmware, potentially including CNT-based circuits in whole or in
part), and that the preferred vehicle will vary with the context in which
the processes, systems and/or other technologies are deployed. For
example, if an implementer determines that speed is paramount, the
implementer may opt for a mainly hardware and/or firmware vehicle.
Alternatively, if flexibility is paramount, the implementer may opt for a
mainly software implementation. In these or other situations, the
implementer may also opt for some combination of hardware, software,
and/or firmware, potentially including CNT-based circuits in whole or in
part. Hence, there are several possible vehicles by which the processes,
devices and/or other technologies involving logic and/or circuits
described herein may be effected, none of which is inherently superior to
the other. Those skilled in the art will recognize that optical aspects
of implementations may require optically-oriented hardware, software, and
or firmware.

[0028]Other embodiments of the invention will be apparent to those skilled
in the art from a consideration of the specification or practice of the
invention disclosed herein. It is intended that the specification be
considered as exemplary only, with the true scope and spirit of the
invention being indicated by the following claims.

Patent applications by Charles Whitmer, North Bend, WA US

Patent applications by Clarence T. Tegreene, Bellevue, WA US

Patent applications by Lowell L. Wood, Jr., Bellevue, WA US

Patent applications by Muriel Y. Ishikawa, Livermore, CA US

Patent applications by Nathan P. Myhrvold, Bellevue, WA US

Patent applications by Roderick A. Hyde, Redmond, WA US

Patent applications in class With specified electrode composition or configuration

Patent applications in all subclasses With specified electrode composition or configuration