I don't understand why anybody here is surprised by the prohibition of publishing any results of a benchmark. Nowadays it is pretty much standard operating procedure that publishing any benchmark results without vendor's agreement is a breach of license.

I don't understand why anybody here is surprised by the prohibition of publishing any results of a benchmark. Nowadays it is pretty much standard operating procedure that publishing any benchmark results without vendor's agreement is a breach of license.....I would be more surprised if anyone could show me a current licensing terms for an American product withouth the anti-bench-marking clause.

I don't understand why anybody here is surprised by the prohibition of publishing any results of a benchmark. Nowadays it is pretty much standard operating procedure that publishing any benchmark results without vendor's agreement is a breach of license.

I would be more surprised if anyone could show me a current licensing terms for an American product withouth the anti-bench-marking clause.

What does licensing have to do with anything.

Company X has a product they claim can do Y. There is some skepticism that it can do Y. If it really can do Y then proof would improve sales and Company X directly benefits. If the product can do Y then it is in Company X best interest to publish results.

Butterfly Labs (BF Labs?) isn't licensing anything. They are selling a product and benchmarks for electronic products are rather routine. It helps consumers make an informed decision as to the actual performance per $.

I don't disagree with any of that. Not really sure what you are refuting.

You seemed to insinuate their pricing made no sense and that it was evidence of scam. But apparently I misunderstood and you seem to agree with me that particularly in the scenario they use s-asics, that their pricing strategy is likely completely sensible?

If so, good. I also think you -along with everyone else- agree that the performance and power consumption claims are completely believable if this is an s-asic. I think everyone agrees the pictures and PCB look pretty damn real. BFL people dont seem to meet Inaba wearing a face mask and sunglasses. They dont seem to make any fuzz about canceled orders.

Someone remind me, what evidence was there again of this being a scam?

* Company accepting pre-orders before product is ready (which isn't necessary as they would have already had to procure the sASICS)* Company claims product will ship in 4-6 weeks but the prototype isn't even working yet (6 weeks from initial claim was on 11/18 so they already missed that).* Company also puts all the "promised" on all new pre-orders at 6 weeks out which keep every future order beyond Paypal chargeback period.* Company calls themselves "Butterfly Labs Inc." but there is no "Butterfly Labs Inc." in the US. There are 12 BF Labs Inc (and one B.F.L. Inc) in the US but nothing on the website links them to that particular entity and no information available for BF Labs Inc link them to Butterfly Labs. * Company claims to have decade of experience but has no prior products and didn't exist 6 months ago.* Company planned a public demo 2 weeks ago but was unable to have product working.* Company has never explained how 32 boards = 50x performance.* Company claims that product is useful for medical imaging (which would be incompatible w/ sASIC design).* Company performance claims are not possible (although not probable) w/ sASIC but board voltage and flash loader would indicate high end FPGA.* Company now plans a public demo in which no hard numbers can be provided.* Company "knows" board will produce 1.05 GH (not the 3 significant digits) but actually hasn't mined anything yet. They also know the rig box will produce exactly 50.45 GH despite smaller product not working at the claimed speeds.* Company (in one of the very few announcements) claimed it wouldn't put rig box up for pre-order until singles had been demoed yet it failed to live up to that claim.

One more to add, this is their statement with implication that bitcoin was not the main purpose of the device:

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Firstly, I would like to point out that we have yet to go public with our BitForce release. At some point recently, several notables from the bitcoin community found out about our development and approached us about applications for the bitcoin market. Since then we have been working on bitcoin mining compatibility for our drivers. The pre-order offer which you are discussing is meant to provide these people early access to our hardware. Our public announcement will come in roughly two weeks. Why not now? Because we're not ready.

Regarding the press release draft someone found, we didn't know about that until it was mentioned here, thanks for that. It seems one of our staff used an online PR generator several weeks ago in preparation for our announcements. Apparently it auto published a draft along with a link for penis enlargement. Excellent. Luckily, they pulled it down on request. I sincerely thank you all for this heads up. It could have been more embarrassing than it was.

Which you can see is completely a lie. I'm sure they're experience in "computational research", "Medical imaging "...etc .

Question 1: If these are indeed FPGAs (I.E., reprogrammable), then is it possible to extrapolate/guess performance figures for other hashing algorithms (MD5, RIPEMD, Whirlpool, etc...) based on stated performance figures for SHA256? It seems to me that these could indeed be useful in other applications, when reprogrammed to something other than SHA256 - for instance a nice little portable MD5 cracker-in-a-box.

Question 2: Also assuming these are reprogrammable, what would the expected performance loss be from flashing them for a single round of SHA256 (instead of double) and then using external software and/or hardware take care of doubling the hashes and fiddling with the nonces? Is this at all feasible, or is having everything all done at once in a single chip the only way to do it?

Example: chip #1 does the first SHA256 round, and then chip #2 does the second SHA256 round, and some external software/hardware increments the nonce and sends it back to chip #1. Perhaps I don't grok how this all works, but there are several experts here and I would like to know whether I have the idea down pat.

Question 1: If these are indeed FPGAs (I.E., reprogrammable), then is it possible to extrapolate/guess performance figures for other hashing algorithms (MD5, RIPEMD, Whirlpool, etc...) based on stated performance figures for SHA256? It seems to me that these could indeed be useful in other applications, when reprogrammed to something other than SHA256 - for instance a nice little portable MD5 cracker-in-a-box.

Question 2: Also assuming these are reprogrammable, what would the expected performance loss be from flashing them for a single round of SHA256 (instead of double) and then using external software and/or hardware take care of doubling the hashes and fiddling with the nonces? Is this at all feasible, or is having everything all done at once in a single chip the only way to do it?

Example: chip #1 does the first SHA256 round, and then chip #2 does the second SHA256 round, and some external software/hardware increments the nonce and sends it back to chip #1. Perhaps I don't grok how this all works, but there are several experts here and I would like to know whether I have the idea down pat.

Its just too convenient have the name Bitforce for a medical imaging device.

I like that name. Very professional.

Wait, what is bitcoin? maybe we should try to make it mine bitcoins instead.

Question 1: If these are indeed FPGAs (I.E., reprogrammable), then is it possible to extrapolate/guess performance figures for other hashing algorithms (MD5, RIPEMD, Whirlpool, etc...) based on stated performance figures for SHA256? It seems to me that these could indeed be useful in other applications, when reprogrammed to something other than SHA256 - for instance a nice little portable MD5 cracker-in-a-box.

If they are FPGA then they could be reprogrammed. Someone would need to design a bitstream to perform whatever task you want. SHA-256 hashing is about 5x as computationally intensive as MD5 and Bitcoin involves a double hash so ballpark you could get ~10 billion MD5 hashes per second if the board really can do 1 billion double SHA-256 hashes. The exact level of performance would depend on how good the bitstream programmer is and how effectively they can utilize all the LUTs to squeeze every hash of performance out of the chip.

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Question 2: Also assuming these are reprogrammable, what would the expected performance loss be from flashing them for a single round of SHA256 (instead of double) and then using external software and/or hardware take care of doubling the hashes and fiddling with the nonces? Is this at all feasible, or is having everything all done at once in a single chip the only way to do it?

It is certainly possible but IMHO not economical. We think of hashing as hard because it takes a long time to find a block but in reality a single hash is very easy. For example if each chip can perform 1B hashes per second then on average one hash takes only a single nano second (actually that isn't true it takes a couple however each chip is working on multiple hashes at once). To use two chips working together requires significant bandwidth and introduces latency issues. The board would have to be designed to handle that and it is improbable that a multi-chip solution (working on a single hash) would be faster or cheaper.

Hashing is an almost perfectly parallel task that is somewhat rare in computer science. Usually you have more dependencies between tasks which require intra-chip communication to solve the problem. Generally speaking the more intra-chip or intra-node communication necessary the more overhead in parallel processing (i.e. 4 chips aren't 4x as fast they are 3.2x as fast, 16 chips aren't 16x as fast they are only 12x as fast, etc).

Since each hash is independent and can be solved quickly if you want more hashing power just use more chips, or boards, or rigs.

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Example: chip #1 does the first SHA256 round, and then chip #2 does the second SHA256 round, and some external software/hardware increments the nonce and sends it back to chip #1. Perhaps I don't grok how this all works, but there are several experts here and I would like to know whether I have the idea down pat.

As above that would require 1 billion x 512 bytes x 8 bits = 4 tbps (terrabits per second) of intrachip bandwidth. You could potential do that but it would be a lot of work, complexity, and potential performance bottlenecks for less hashing power. Generally you want to minimize intra-element communication UNLESS a single element (SIMD group, chip, server, cluster, etc) can't solve the problem in a reasonable amount of time.

TL/DR version:You use intra-chip processing when you have to because the problem is too complex or has too many dependencies on other results to process in a single chip. Bitcoin doesn't have that problem. It is just about as perfectly parallel as problems come in computer science.

The 5830: Where can you find it new? How much does that cost? For what 250 mhash or so?

The 5970: Okay, yes Newegg sold the last bit they had for $300, that was an awesome deal. Where else can I buy a 5970 for $300?Keyword being new! I need to snatch up a bajillion.

As for some of the other, lower end 6xxx series. I feel quite stupid and spoke before thinking. It proves the point of 'sneezing the wrong way will cause a flame war,' at least on this forum.In that case, I'm going to say that I also took into account the power usage, and obviously the heat/cooling involved.

Bought a 6950 (albeit used) for $200 and pushing 400 MHash/s. Live in an apartment that is too cold and dont pay electricity so I get free heating and a gaming card when I need one. FPGA only wins in W/Mhash and even then only if you pay for electricity.

To use two chips working together requires significant bandwidth and introduces latency issues. The board would have to be designed to handle that and it is improbable that a multi-chip solution (working on a single hash) would be faster or cheaper.

Hashing is an almost perfectly parallel task that is somewhat rare in computer science. Usually you have more dependencies between tasks which require intra-chip communication to solve the problem. Generally speaking the more intra-chip or intra-node communication necessary the more overhead in parallel processing (i.e. 4 chips aren't 4x as fast they are 3.2x as fast, 16 chips aren't 16x as fast they are only 12x as fast, etc).

As above that would require 1 billion x 512 bytes x 8 bits = 4 tbps (terrabits per second) of intrachip bandwidth. You could potentially do that but it would be a lot of work, complexity, and potential performance bottlenecks for less hashing power. Generally you want to minimize intra-element communication UNLESS a single element (SIMD group, chip, server, cluster, etc) can't solve the problem in a reasonable amount of time.

OK, this is what I thought might be the case. The only reason I considered splitting the work in such a manner was because of the physical proximity of the chips to each other. I assumed that having them so close could indicate high bandwidth - however the numbers needed don't add up. Thanks for clarifying that.

Someone noted that there was a support chip on the board that is usually used to store firmware - not to mention the JTAG headers as well. That's why I think these have more applications than we might think they do.

I thought I would poke my head in and give an update and response to some of the comments made here in the last few days.

Firstly, I'm sorry everyone's expectations for a demo last weekend were not met. This is an exciting process for us and it's clear some of you share the same level of enthusiasm... (although I wonder if some of it might be better channeled). In any case, sorry to let you down.

We're well past the bringing to life phase of the board. It does what it was designed to do and at the performance levels intended. There are some tuning issues that took us longer than expected which we've dialed the board down in order to more easily address. We didn't want to demo a tuned down system that's not representative of our performance envelope, so we simply pushed the demo forward in order to give the team the time they need. We're now near the end of that process.

As Inaba mentioned, we'll be bringing a live running unit to his data center tomorrow for a quick look and performance demonstration. Since we're not at our final figures, he's agreed to simply confirm or deny if the unit is generally within the performance class expected. I think rather than fuzzy numbers, everyone just wants to know if this unicorn is real. Fair enough... we expect to clarify that once and for all tomorrow afternoon. We'll follow up with a more formal demo once we're finished.

There has also been fevered speculation by a couple forum members about elaborate payment methods etc. Instead of commenting on them directly, I'd like to simply make notice to any of our customers that if you're uncomfortable with your pre-order purchase, you're welcome to cancel your pre-order slot and get a full refund with no questions asked.

I really don't think so, but if so and you figure out what FPGA then you could make some estimates. Going from the SHA256 numbers directly is a bit harder.

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Question 2: Also assuming these are reprogrammable, what would the expected performance loss be from flashing them for a single round of SHA256 (instead of double) and then using external software and/or hardware take care of doubling the hashes and fiddling with the nonces? Is this at all feasible, or is having everything all done at once in a single chip the only way to do it?

External? Not feasible. A block header is 80 bytes. The result is 32 bytes. Do the data rate calculations for a billion of them a second. The data rate for a miner is only small because the ability to increment the nonce 'locally' (on chip) reduces the required data rate by a factor of 4 billion. (The same thing applies to GPUs).

I'd like to simply make notice to any of our customers that if you're uncomfortable with your pre-order purchase, you're welcome to cancel your pre-order slot and get a full refund with no questions asked.

If anyone cancels their pre-order slot, will it become available again for purchase at the lower price?

I'd like to simply make notice to any of our customers that if you're uncomfortable with your pre-order purchase, you're welcome to cancel your pre-order slot and get a full refund with no questions asked.

If anyone cancels their pre-order slot, will it become available again for purchase at the lower price?

Wow, I wouldn't even consider this so close to an answer. I mean in ~15 hours or so you'll at least have a good idea if this is fantasy or reality. Why pull the trigger now?

I'd like to simply make notice to any of our customers that if you're uncomfortable with your pre-order purchase, you're welcome to cancel your pre-order slot and get a full refund with no questions asked.

If anyone cancels their pre-order slot, will it become available again for purchase at the lower price?

Wow, I wouldn't even consider this so close to an answer. I mean in ~15 hours or so you'll at least have a good idea if this is fantasy or reality. Why pull the trigger now?

I'd like to simply make notice to any of our customers that if you're uncomfortable with your pre-order purchase, you're welcome to cancel your pre-order slot and get a full refund with no questions asked.

If anyone cancels their pre-order slot, will it become available again for purchase at the lower price?

Wow, I wouldn't even consider this so close to an answer. I mean in ~15 hours or so you'll at least have a good idea if this is fantasy or reality. Why pull the trigger now?

I'd like to simply make notice to any of our customers that if you're uncomfortable with your pre-order purchase, you're welcome to cancel your pre-order slot and get a full refund with no questions asked.

If anyone cancels their pre-order slot, will it become available again for purchase at the lower price?

Wow, I wouldn't even consider this so close to an answer. I mean in ~15 hours or so you'll at least have a good idea if this is fantasy or reality. Why pull the trigger now?

A recap (assumming the company is pretending to be using sASICS):* Company is offering pre-orders before product is ready (which isn't necessary as they would have had to already acquire the sASICS)

We are going in circles here. I see nothing weird about selling their first batch of test chips for a discount for all the reasons already mentioned.

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* Company claims product will ship in 4-6 weeks but the prototype isn't even working yet 7 weeks later (the 6 weeks from initial claim was on 11/18 so they already missed that).

IIRC the preorder actually had a 4-8 week delivery schedule. They have not missed that yet. Even if they do, a tiny delay (if that) is evidence of a scam now? Better tell AMD, nVidia, intel, microsoft, etc.

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* Company also puts all shipping estimates for new pre-orders at a continual 6 weeks out which just happens to put every single order (both past and future) outside of Paypal chargeback period.

So anything with a 6 week shipping date is suspicious to you? Better tell my Audi dealer as I ordered my car 3 months ago and Im still waiting.

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* Speaking of Paypal. The company has the assets to acquire a multi-hundred thousand dollar sASIC design and run but can't accept credit cards via their established merchant account and instead relies on Paypal which has much less protection for the consumer.

And less protection to the seller. I had to give my Audi dealer a certified bank check. Scammers!

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* Company calls themselves "Butterfly Labs Inc." but there is no "Butterfly Labs Inc." in the US. There are 12 BF Labs Inc (and one B.F.L. Inc) in the US but nothing on the website links them to that particular entity and no information available for BF Labs Inc link them to Butterfly Labs.

Since you can pay with a bank transfer, Im sure you'll get the correct name and address, though I agree they should put that on their site.

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* Company claims to have decade of experience but has no prior products and didn't exist 6 months ago.

Obviously the people in that company have experience and the company is a startup (/spin off). We said the same thing when we spun out a cmos image sensor chip company, since the team had many years of experience, just not under that company name.

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* Company planned a public demo 2 weeks ago but was unable to have product working in time.

Big deal. Particularly since that demo was not even officially announced.

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* Company has never explained how 32 boards = 50x performance.* Company claims that product is useful for medical imaging (which would be incompatible w/ sASIC design).* Company performance claims are not impossible (although improbable) w/ high end sASIC but board voltage and onboard flash loader would indicate high end FPGA not a sASIC.

Not knowing the technical details of their yet to ship product is not evidence of a scam.

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* Company now plans a public demo in which no hard numbers can be provided.

Inaba is allowed to say whether or not the board generally meats the performance claims; considering they admit issues with the software, I think thats entirely reasonable. When is the last time AMD or Intel allowed publishing benchmarks of preproduction hardware? If for whatever reason there still is 10-20% lower performance than promised, it doesnt exactly prove a scam or does it.

* Company calls themselves "Butterfly Labs Inc." but there is no "Butterfly Labs Inc." in the US. There are 12 BF Labs Inc (and one B.F.L. Inc) in the US but nothing on the website links them to that particular entity and no information available for BF Labs Inc link them to Butterfly Labs.

Since you can pay with a bank transfer, Im sure you'll get the correct name and address, though I agree they should put that on their site.

* Company claims to have decade of experience but has no prior products and didn't exist 6 months ago.

Obviously the people in that company have experience and the company is a startup (/spin off). We said the same thing when we spun out a cmos image sensor chip company, since the team had many years of experience, just not under that company name.

The website clearly says: "Butterfly Labs has more than a decade of experience in FPGA & ASIC stand alone system design." To me, that's very different than saying that some people that work at this company have worked on this type of stuff for a while.

* Company has never explained how 32 boards = 50x performance.* Company claims that product is useful for medical imaging (which would be incompatible w/ sASIC design).* Company performance claims are not impossible (although improbable) w/ high end sASIC but board voltage and onboard flash loader would indicate high end FPGA not a sASIC.

Not knowing the technical details of their yet to ship product is not evidence of a scam.

You're right, a lack of details doesn't mean it's a scam. The point is that the details we do have don't add up.

Could you elaborate on what you mean? I think you miss his point: quoting 3 significant figures implies that level of confidence in the measurement. If they had simply said 1 GH/s and 50 GH/s, it would mean a very different thing.