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Abstract:

Disclosed herein is a manufacturing method of a display device including:
forming a gate electrode on a substrate; forming a laminated film by
photolithography technique. The laminated film is provided above the gate
electrode with a gate insulating film sandwiched therebetween and
includes a semiconductor layer, at least either a source/drain electrode
or a pixel electrode, a planarizing film and a pixel isolation film. The
manufacturing method further includes forming a functional layer and a
common electrode in this order after the formation of the laminated film.
The functional layer includes an organic electric field light-emitting
layer. Two or more layers are patterned all together in at least part of
the laminated film during the formation of the laminated film.

Claims:

1. A manufacturing method of a display device comprising: forming a gate
electrode on a substrate; forming a laminated film by photolithography
technique, the laminated film being provided above the gate electrode
with a gate insulating film sandwiched therebetween and including a
semiconductor layer, at least either a source/drain electrode or a pixel
electrode, a planarizing film and a pixel isolation film; and forming a
functional layer and a common electrode in this order after the formation
of the laminated film, the functional layer including an organic electric
field light-emitting layer, wherein two or more layers are patterned all
together in at least part of the laminated film during the formation of
the laminated film.

2. The manufacturing method of the display device according to claim 1,
wherein three photomasks are used during the formation of the laminated
film.

3. The manufacturing method of the display device according to claim 2,
wherein the formation of the laminated film includes forming, as the
laminated film, the semiconductor layer, a first protective film, the
planarizing film, the source/drain electrode and the pixel isolation film
in this order from the side of the gate electrode, patterning the first
protective film and the semiconductor layer using a first photomask after
the formation of the first protective film on the semiconductor layer,
patterning, after the formation of the planarizing film, the formed
planarizing film using a second photomask having a first opening at least
in a first region for a light-emitting region, etching the first
protective film using the patterned planarizing film as a mask so as to
expose the semiconductor layer in the first region, forming, after the
etching of the first protective film, the source/drain electrode and the
pixel isolation film in this order first and then patterning the formed
pixel isolation film using a third photomask having an opening at least
in the first region, and exposing the semiconductor layer in the first
region by etching the source/drain electrode using the patterned pixel
isolation film as a mask.

4. The manufacturing method of the display device according to claim 3
further comprising: forming a second protective film after the patterning
of the first protective film and the semiconductor layer and prior to the
formation of the planarizing film, wherein the second protective film is
etched together with the first protective film using the patterned
planarizing film as a mask.

5. The manufacturing method of the display device according to claim 4,
wherein, during the formation of the gate electrode, the gate electrode
is formed in a second region for a transistor section on the substrate,
and an electrode layer is formed in a third region for a capacitor
section and in a fourth region for an interconnect section, during the
formation of the laminated film, the first protective film and the
semiconductor layer are removed in the fourth region at the time of
patterning using the first photomask, and at the time of etching using
the planarizing film as a mask, the semiconductor layer is exposed in the
second and third regions by removing the first and second protective
films while at the same time exposing the electrode layer in the fourth
region by removing the second protective film and the gate insulating
film.

6. The manufacturing method of the display device according to claim 3,
wherein, during the formation of the laminated film, an oxide
semiconductor is used as the semiconductor layer, and the semiconductor
layer in the first region is subjected to a resistance reduction
treatment after the patterning using the third photomask.

7. The manufacturing method of the display device according to claim 3,
wherein, during the formation of the laminated film, the pixel isolation
film is subjected to reflow after the patterning of the pixel isolation
film and the source/drain electrode.

8. The manufacturing method of the display device according to claim 1,
wherein four photomasks are used during the formation of the laminated
film.

9. The manufacturing method of the display device according to claim 8,
wherein the formation of the laminated film includes forming, as the
laminated film, the semiconductor layer, the first protective film, the
planarizing film, the source/drain electrode and the pixel isolation film
in this order from the side of the gate electrode, patterning the first
protective film and the semiconductor layer using a first photomask after
the formation of the first protective film on the semiconductor layer,
patterning, after the formation of the planarizing film, the formed
planarizing film using a second photomask, etching the first protective
film using the patterned planarizing film, forming, after the etching of
the first protective film, the source/drain electrode first and then
patterning the formed source/drain electrode using a third photomask, and
forming the pixel isolation film and patterning the formed pixel
isolation film using a fourth photomask having an opening at least in a
region for a light-emitting region.

10. The manufacturing method of the display device according to claim 1,
wherein five photomasks are used during the formation of the laminated
film.

11. The manufacturing method of the display device according to claim 10,
wherein the formation of the laminated film includes forming, as the
laminated film, the semiconductor layer, the first protective film, the
source/drain electrode, the planarizing film, the pixel electrode and the
pixel isolation film in this order from the side of the gate electrode,
patterning the first protective film using a first photomask after the
formation of the first protective film on the semiconductor layer,
patterning the source/drain electrode using a second photomask after the
formation of the source/drain electrode, patterning, after the formation
of the planarizing film, the formed planarizing film using a third
photomask, patterning, after the formation of the pixel electrode, the
formed pixel electrode using a fourth photomask, and patterning, after
the formation of the pixel isolation film, the formed pixel isolation
film using a fifth photomask.

12. The manufacturing method of the display device according to claim 1,
wherein six photomasks are used during the formation of the laminated
film.

13. The manufacturing method of the display device according to claim 12,
wherein the formation of the laminated film includes forming, as the
laminated film, the semiconductor layer, the first protective film, a
third protective film, the source/drain electrode, the planarizing film,
the pixel electrode and the pixel isolation film in this order from the
side of the gate electrode, patterning the first protective film and the
semiconductor layer using a first photomask after the formation of the
first protective film, patterning the third and first protective films
using a second photomask after the formation of the third protective
film, patterning the source/drain electrode using a third photomask after
the formation of the source/drain electrode, patterning, after the
formation of the planarizing film, the formed planarizing film using a
fourth photomask, patterning, after the formation of the pixel electrode,
the formed pixel electrode using a fifth photomask, and patterning, after
the formation of the pixel isolation film, the formed pixel isolation
film using a sixth photomask.

14. A display device comprising: a gate electrode provided on a
substrate; a laminated film provided above the gate electrode with a gate
insulating film sandwiched therebetween, the laminated film including a
semiconductor layer, at least either a source/drain electrode or a pixel
electrode, a planarizing film and a pixel isolation film; a functional
layer provided on the pixel isolation film of the laminated film and
including an organic electric field light-emitting layer; and a common
electrode provided on the functional layer, wherein an opening is
provided in at least part of the laminated film to penetrate two or more
layers.

15. The display device according to claim 14 comprising: the
semiconductor layer; the planarizing film; the source/drain electrode;
and the pixel isolation film in this order from the side of the gate
electrode, wherein the source/drain electrode serves also as the pixel
electrode.

16. The display device according to claim 14 comprising: the
semiconductor layer; the planarizing film; the source/drain electrode;
and the pixel isolation film in this order from the side of the gate
electrode, wherein part of the semiconductor layer is exposed from the
planarizing film in a first region for a light-emitting region on the
substrate, and the exposed portion of the semiconductor layer serves also
as the pixel electrode.

17. The display device according to claim 15 comprising: a first
protective film made of at least one of silicon oxide, silicon nitride
and silicon oxynitride between the semiconductor layer and the
planarizing film.

18. The display device according to claim 17 comprising: a second
protective film made of aluminum oxide between the first protective film
and the planarizing film.

19. The display device according to claim 18, wherein the gate electrode
is provided in a second region for a transistor section on the substrate,
an electrode layer is provided in a third region for a capacitor section
and in a fourth region for an interconnect section, the source/drain
electrode is provided in contact with the semiconductor layer in an
opening penetrating the planarizing film, the second protective film and
the first protective film in the second and third regions, and the
source/drain electrode is provided in contact with the electrode layer in
an opening penetrating the planarizing film, the second protective film
and the gate insulating film in the fourth region.

20. Electronic equipment comprising: a display device including a gate
electrode provided on a substrate, a laminated film provided above the
gate electrode with a gate insulating film sandwiched therebetween,
having a semiconductor layer, at least either a source/drain electrode or
a pixel electrode, a planarizing film, and a pixel isolation film, a
functional layer provided on the pixel isolation film of the laminated
film and including an organic electric field light-emitting layer, and a
common electrode provided on the functional layer, wherein an opening is
provided in at least part of the laminated film to penetrate two or more
layers.

Description:

BACKGROUND

[0001] The present disclosure relates to a manufacturing method of a
display device having a photolithography process and a display device
manufactured thereby.

[0002] In a flat panel display such as an organic EL (Electro
Luminescence) display device, thin film transistors (TFTs), an
interconnect layer and other components adapted to drive pixels are
arranged on a substrate, and pixels including an organic EL layer are
formed on top thereof (e.g., Japanese Patent Laid-Open No. 2001-195008).
In manufacturing steps of such a display device, each of the layers is
patterned by a thin film formation process based on photolithography
technique.

SUMMARY

[0003] In a manufacturing process based on photolithography technique as
described above, photomasks are used on which patterns of the respective
layers are drawn in advance. However, TFTs and capacitive elements are
formed on a substrate first, and then coated with a planarizing film,
after which the patterns of a pixel electrode and pixel isolation film
are formed on the planarizing film. Therefore, a different photomask is
necessary for patterning of each layer. Further, photoresist and other
materials are necessary at each patterning step, and the formed layers
undergo coating, exposure, development, post-bake and other steps, thus
resulting in more film formation steps and higher cost.

[0004] The present disclosure has been made in light of the foregoing, and
it is desirable to provide a display device that can be manufactured by a
low-cost and simple process, a manufacturing method of the same and
electronic equipment having the same.

[0005] A manufacturing method of a display device according to an
embodiment of the present disclosure includes forming a gate electrode on
a substrate and forming a laminated film by photolithography technique.
The laminated film is provided above the gate electrode with a gate
insulating film sandwiched therebetween and includes a semiconductor
layer, at least either a source/drain electrode or a pixel electrode, a
planarizing film and a pixel isolation film. The manufacturing method
further includes forming a functional layer and a common electrode in
this order after the formation of the laminated film. The functional
layer includes an organic electric field light-emitting layer. In the
formation of the laminated film, two or more layers are patterned all
together in at least part of the laminated film.

[0006] In the manufacturing method of a display device according to
another embodiment of the present disclosure, a laminated film is formed
by photolithography technique in the laminated film formation step after
forming a gate electrode on a substrate. The laminated film is provided
above the gate electrode with a gate insulating film sandwiched
therebetween and includes a semiconductor layer, at least either a
source/drain electrode or a pixel electrode, a planarizing film and a
pixel isolation film. Then, a functional layer and a common electrode are
formed in this order, thus forming a display device. The functional layer
includes an organic electric field light-emitting layer. In the laminated
film formation step, two or more layers are patterned all together in at
least part of the laminated film, thus contributing to less consumption
of photomasks as compared to patterning of one layer at a time. Further,
the manufacturing method contributes to less consumption of photoresist
and other materials and a smaller number of steps.

[0007] A display device according to a further embodiment of the present
disclosure includes: a gate electrode provided on a substrate; a
laminated film provided above the gate electrode with a gate insulating
film sandwiched therebetween, including a semiconductor layer, at least
either a source/drain electrode or a pixel electrode, a planarizing film
and a pixel isolation film; a functional layer provided on the pixel
isolation film of the laminated film and including an organic electric
field light-emitting layer; and a common electrode provided on the
functional layer. An opening is provided in at least part of the
laminated film to penetrate two or more layers.

[0008] Electronic equipment according to a further embodiment of the
present disclosure includes the display device according to the
embodiment of the present disclosure.

[0009] The manufacturing method of the display device according to a
further embodiment of the present disclosure forms the laminated film by
photolithography technique after forming the gate electrode on the
substrate. The laminated film is provided above the gate electrode with
the gate insulating film sandwiched therebetween and includes the
semiconductor layer, at least either the source/drain electrode or the
pixel electrode, the planarizing film and the pixel isolation film. Then,
the manufacturing method forms the functional layer and the common
electrode in this order, thus forming the display device. The functional
layer includes the organic electric field light-emitting layer. Two or
more layers are patterned all together in at least part of the laminated
film, contributing to less consumption of photomasks, photoresist and
other materials and a smaller number of steps. This allows for
manufacture of a display device by a low-cost and simple process.

[0010] The display device according to a further embodiment of the present
disclosure includes not only the gate electrode provided on the substrate
and also includes the laminated film. The laminated film is provided
above the gate electrode with the gate insulating film sandwiched
therebetween and includes the semiconductor layer, at least either the
source/drain electrode or the pixel electrode, the planarizing film and
the pixel isolation film. The opening is provided in at least part of the
laminated film to penetrate two or more layers. This contributes to less
consumption of photomasks, photoresist and other materials and a smaller
number of steps, thus allowing for manufacture of a display device by a
low-cost and simple process.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011]FIG. 1 illustrates the cross-sectional structure of a display
device according to a first embodiment of the present disclosure;

[0012] FIGS. 2A and 2B are diagrams illustrating the manufacturing method
of a TFT shown in FIG. 1 in order of the steps;

[0013] FIGS. 2C and 2D are diagrams illustrating steps continued from
FIGS. 2A and 2B;

[0014]FIG. 2E is a diagram illustrating a step continued from FIGS. 2C
and 2D;

[0015] FIG. 2F is a diagram illustrating a step continued from FIG. 2E;

[0016]FIG. 2G is a diagram illustrating a step continued from FIG. 2F;

[0017]FIG. 2H is a diagram illustrating a step continued from FIG. 2G;

[0018] FIGS. 3A and 3B are diagrams illustrating the manufacturing method
of a TFT according to a comparative example in order of the steps;

[0019] FIGS. 3C and 3D are diagrams illustrating steps continued from
FIGS. 3A and 3B;

[0020]FIG. 3E is a diagram illustrating a step continued from FIGS. 3C
and 3D;

[0021] FIG. 3F is a diagram illustrating a step continued from FIG. 3E;

[0022]FIG. 3G is a diagram illustrating a step continued from FIG. 3F;

[0023]FIG. 3H is a diagram illustrating a step continued from FIG. 3G;

[0024] FIG. 4 is a diagram illustrating the current-voltage characteristic
of the embodiment;

[0025] FIG. 5 illustrates the cross-sectional structure of a display
device according to a second embodiment of the present disclosure;

[0026]FIG. 6A is a diagram illustrating the manufacturing method of the
display device shown in FIG. 5 in order of the steps;

[0027] FIG. 6B is a diagram illustrating a step continued from FIG. 6A;

[0028] FIG. 6C is a diagram illustrating a step continued from FIG. 6B;

[0029]FIG. 6D is a diagram illustrating a step continued from FIG. 6C;

[0030]FIG. 6E is a diagram illustrating a step continued from FIG. 6D;

[0031]FIG. 6F is a diagram illustrating a step continued from FIG. 6E;

[0032] FIG. 7 is a characteristic diagram illustrating the relationship
between treatment time and sheet resistance in a resistance reduction
treatment (argon plasma treatment);

[0033] FIG. 8 illustrates the cross-sectional structure of a display
device according to a third embodiment of the present disclosure;

[0034] FIGS. 9A and 9B are diagrams illustrating the manufacturing method
of the display device shown in FIG. 8 in order of the steps;

[0035]FIG. 9C is a diagram illustrating a step continued from FIGS. 9A
and 9B;

[0036]FIG. 9D is a diagram illustrating a step continued from FIG. 9C;

[0037]FIG. 9E is a diagram illustrating a step continued from FIG. 9D;

[0038]FIG. 9F is a diagram illustrating a step continued from FIG. 9E;

[0039]FIG. 9G is a diagram illustrating a step continued from FIG. 9F;

[0040] FIG. 10 illustrates the cross-sectional structure of a display
device according to a fourth embodiment of the present disclosure;

[0041] FIGS. 11A and 11B are diagrams illustrating the manufacturing
method of the display device shown in FIG. 10 in order of the steps;

[0042] FIGS. 11C and 11D are diagrams illustrating steps continued from
FIGS. 11A and 11B;

[0043] FIG. 11E is a diagram illustrating a step continued from FIGS. 11C
and 11D;

[0044] FIG. 11F is a diagram illustrating a step continued from FIG. 11E;

[0045] FIG. 11G is a diagram illustrating a step continued from FIG. 11F;

[0046] FIG. 11H is a diagram illustrating a step continued from FIG. 11G;

[0047] FIG. 11I is a diagram illustrating a step continued from FIG. 11H;

[0048] FIG. 12 is a diagram illustrating the overall configuration
including peripheral circuitries of the display device according to the
embodiments;

[0049] FIG. 13 is a diagram illustrating the circuit configuration of a
pixel shown in FIG. 12;

[0050] FIG. 14 is a plan view illustrating the schematic configuration of
a module including the display device shown in FIG. 12;

[0052] FIG. 16A is a perspective view illustrating the appearance of
application example 2 as seen from the front, and FIG. 16B is a
perspective view illustrating the appearance thereof as seen from the
back;

[0054]FIG. 18 is a perspective view illustrating the appearance of
application example 4; and

[0055]FIG. 19A is a front view of application example 5 in an open
position, FIG. 19B is a side view thereof, FIG. 19C is a front view in a
closed position, FIG. 19D is a left side view, FIG. 19E is a right side
view, FIG. 19F is a top view, and FIG. 19G is a bottom view.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0056] A detailed description will be given below of the preferred
embodiments of the present disclosure with reference to the accompanying
drawings. It should be noted that the description will be given in the
following order.

1. First embodiment (example in which a total of five photomasks are used
in a drive substrate formation step (TFT source/drain is used as a pixel
electrode)) 2. Second embodiment (example in which four photomasks are
used in the drive substrate formation step (TFT semiconductor layer is
used as the pixel electrode)) 3. Third embodiment (example in which six
photomasks are used in the drive substrate formation step) 4. Fourth
embodiment (example in which seven photomasks are used in the drive
substrate formation step) 5. Application examples (examples of a module
and electronic equipment)

First Embodiment

[Configuration of the Display Device 1A]

[0057]FIG. 1 illustrates the cross-sectional structure of a display
device 1A according to a first embodiment of the present disclosure. The
display device 1A is, for example, an active matrix type organic EL
display and has a plurality of pixels arranged in a matrix form. It
should be noted, however, that FIG. 1 shows only the region for one
pixel. The display device 1A includes a functional layer 20, a common
electrode 21 and a protective layer 22 on a drive substrate 11A. The
functional layer 20 includes an organic EL layer. A sealing substrate 23
is attached to the protective layer 22 using an unshown adhesive layer.
In the functional layer 20, a region for an opening H4 of a pixel
isolation film 19 which will be described later serves as a
light-emitting section 10A. The display device 1A may be a so-called top
emission or bottom emission display device.

[0058] In the drive substrate 11A, a transistor section 10B, a capacitor
section 10C and an interconnect contact section 10D are provided for each
pixel on a substrate 11 to drive the pixel. The specific configuration of
each of the transistor section 10B, the capacitor section 10C and the
interconnect contact section 10D will be described later.

[0059] The functional layer 20 includes an organic EL layer, emitting
light when applied with a drive current. The functional layer 20 is made
up, for example, of a hole injection layer, a hole transport layer, an
organic EL layer and an electron transport layer (none of them are shown)
that are stacked in this order from the side of the substrate 11. The
organic EL layer emits light as a result of the recombination of
electrons and holes when applied with an electric field. It is only
necessary for the organic EL layer to be made of an ordinary low or high
molecular weight organic material. The material of the organic EL layer
is not specifically limited. Further, the red, green and blue
light-emitting layers, for example, may be patterned, one for each pixel.
Alternatively, a white light-emitting layer may be provided above the
entire surface of the substrate. The hole injection layer is designed to
provide enhanced hole injection efficiency and prevent leaks. The hole
transport layer is designed to provide enhanced hole transport efficiency
to the organic EL layer. It is only necessary to provide these layers
other than the organic EL layer as necessary.

[0060] The common electrode 21 acts, for example, as a cathode and
includes a metal conductive film. If the display device 1A is a bottom
emission display device, the common electrode 21 includes a reflective
metal film, and more specifically, a single metal made of one of aluminum
(Al), magnesium (Mg), calcium (Ca) and sodium (Na), a single-layer film
made of an alloy containing at least one of the above, or a multilayer
film made up of two or more layers of the above metals stacked one on top
of another. Alternatively, if the display device 1A is a top emission
display device, the common electrode 21 includes a transparent conductive
film made, for example, of ITO (indium tin oxide). The common electrode
21 is formed on the functional layer 20 while being insulated from the
anode (a source/drain electrode layer 18 which will be described later in
the present embodiment) so that the common electrode 21 can be shared
among all the pixels.

[0061] The protective layer 22 may be made of an insulating or conductive
material. Among insulating materials that can be used are amorphous
silicon (a-Si), amorphous silicon carbide (a-SiC), amorphous silicon
nitride (a-Si1-xNx) and amorphous carbon (a-C).

[0062] The sealing substrate 23 includes a plate material made, for
example, of quartz, glass, metal foil, silicon or plastic. It should be
noted, however, that if the display device 1A is a top emission display
device, the sealing substrate 23 includes a transparent substrate made,
for example, of glass or plastic and may have, for example, an unshown
color filter or light-shielding film.

[Detailed Configuration of the Drive Substrate 11A]

[0063] The drive substrate 11A includes the transistor section 10B, the
capacitor section 10C and the interconnect contact section 10D as
described above. In the present embodiment, the patterns of the
transistor section 10B, the capacitor section 10C and the interconnect
contact section 10D are formed on the substrate 11 by a thin film
formation process based on photolithography technique although described
in detail later.

[0064] The substrate 11 includes a plate material made, for example, of
quartz, glass, metal foil, silicon or plastic. It should be noted,
however, that if the display device 1A is a bottom emission display
device, the substrate 11 includes a transparent substrate made, for
example, of glass or plastic.

(Transistor Section 10B)

[0065] The transistor section 10B corresponds to a sampling transistor 5A
or a drive transistor 5B in a pixel drive circuit 50a which will be
described later and is a TFT having an inverted staggered (so-called
bottom gate) structure. The transister section 10B has a gate electrode
12a arranged on the substrate 11, and a semiconductor layer 14 is
provided on the gate electrode 12a with a gate insulating film 13
sandwiched therebetween. A first protective film 15, a second protective
film 16 and a planarizing film 17 are stacked in this order on the
semiconductor layer 14. In the first protective film 15, the second
protective film 16 and the planarizing film 17, contact holes H3
(openings) are provided to penetrate these films from the surface of the
planarizing film 17 to that of the semiconductor layer 14. The
source/drain electrode layer 18 (source/drain electrodes 18a) is formed
on the planarizing film 17 in such a manner as to fill the contact holes
H3. A laminated film 24 made up of the semiconductor layer 14, the first
protective film 15, the second protective film 16, the planarizing film
17, the source/drain electrode layer 18 and the pixel isolation film 19
is a specific example of the "laminated film" in the present disclosure.

[0066] The gate electrode 12a serves as an interconnect adapted to control
the carrier density of the semiconductor layer 14 based on a gate voltage
(Vg) applied to the transistor section 10B and supply a potential. The
gate electrode 12a includes a single metal made, for example, of one of
molybdenum (Mo), titanium (Ti), aluminum (Al), silver (Ag) and copper
(Cu), an alloy thereof, or a laminated film made of two or more of the
above metals. More specifically, the gate electrode 12a has, for example,
a laminated structure containing a metal layer made of a low-resistance
material such as aluminum or silver sandwiched between molybdenum or
titanium films. Alternatively, the gate electrode 12a may be made, for
example, of an aluminum-neodymium (Nd) alloy (AlNd alloy). Still
alternatively, the gate electrode 12a may include a transparent
conductive film made, for example, of ITO, AZO (aluminum-doped zinc
oxide) or GZO (gallium-doped zinc oxide).

[0067] The gate insulating film 13 is a single-layer film made of one of
silicon oxide film (SiO2), silicon nitride film (SiN) and silicon
oxynitride film (SiON) or is a laminated film made up of two or more
layers of the above materials.

[0068] The semiconductor layer 14 forms a channel when applied with a gate
voltage and includes, for example, an oxide semiconductor containing at
least one of indium (In), gallium (Ga) and zinc (Zn). Indium gallium zinc
oxide (IGZO or InGaZnO) is among such oxide semiconductors. This oxide
semiconductor film 14 is, for example, 20 to 100 nm in thickness.

[0069] The first protective film 15 is a single-layer film made up, for
example, of one of silicon oxide film, silicon nitride film and silicon
oxynitride film or a laminated film made up of two or more layers of the
above materials. The first protective film 15 prevents damage to the
semiconductor layer 14. Provision of the first protective film 15 makes
it possible to stably maintain the features of the semiconductor layer 14
for extended periods.

[0070] The second protective film 16 is made, for example, of aluminum
oxide (Al2O3) and suppresses entry of outside air (e.g.,
hydrogen) into the semiconductor layer 14. The second protective film 16
also stores oxygen atoms and supplies them to the semiconductor layer 14
in the manufacturing process.

[0071] The planarizing film 17 is made, for example, of polyimide or
acrylic-based resin and formed above the entire surface of the substrate
11. It should be noted, however, that the contact holes H3 adapted to
ensure electrical connection between the source/drain electrode layer 18
and the semiconductor layer 14 are provided in the planarizing film 17,
the first protective film 15 and the second protective film 16.

[0072] The source/drain electrode layer 18 is made of the same metal or
transparent conductive film listed for the gate electrode 12a. The
source/drain electrode layer 18 is divided into segments, one for each of
the transistor section 10B, the capacitor section 10C and the
interconnect contact section 10D. In the present embodiment, the
source/drain electrode 18a arranged in the region for the transistor
section 10B serves as a source or a drain while also serving as a display
pixel electrode (e.g., anode electrode). That is, the source/drain
electrode 18a extends to the region for the light-emitting section 10A on
the planarizing film 17 and is in contact with the functional layer 20 in
the opening H4 of the pixel isolation film 19. In the present embodiment,
it is preferred that a metal film made of AlNd alloy should be provided
on the topmost surface of the source/drain electrode 18a to prevent
thermal deformation.

(Capacitor Section 10C)

[0073] The capacitor section 10C serves, for example, as a holding
capacitive element 5C in the pixel drive circuit 50a which will be
described later. In the capacitor section 10C, an electrode layer 12b is
provided on the substrate 11, and the semiconductor layer 14 is provided
on the electrode layer 12b with the gate insulating film 13 sandwiched
therebetween. The electrode layer 12b is an electrode whose pattern is
formed in the same layer and, for example, in the same step as the gate
electrode 12a in the transistor section 10B. The gate insulating film 13
and the semiconductor layer 14 are formed continuously from the
transistor section 10B.

[0074] A contact hole H2 is provided above the semiconductor layer 14 so
as to penetrate the first protective film 15, the second protective film
16 and the planarizing film 17. A portion (an electrode layer 18b) for
the capacitor section 10C in the source/drain electrode layer 18 is
formed in such a manner as to fill the contact hole H2 (at least to cover
the bottom surface of the contact hole H2). This allows for a capacitive
element to be formed that includes the electrode layer 18b and the gate
insulating film 13 which is sandwiched between the semiconductor layer 14
and the electrode layer 12b.

[0075] It should be noted that the capacitor section 10C is provided for
each pixel. The percentage of the capacitor formation region in each
pixel (percentage in the pixel aperture (practical light-emitting
region)) should preferably be about 40% or less.

(Interconnect Contact Section 10D)

[0076] In the interconnect contact section 10D, the electrode layer 12b is
provided to extend from the region for the capacitor section 10C. In the
interconnect contact section 10D, a contact hole H1 is provided above the
electrode layer 12b so as to penetrate the gate insulating film 13, the
second protective film 16 and the planarizing film 17. A portion
(electrode layer 18c) for the interconnect contact section 10D in the
source/drain electrode layer 18 is formed above the electrode layer 12b
in such a manner as to fill the contact hole H1.

[0077] As described above, the source/drain electrode layer 18 is provided
on the planarizing film 17 in the present embodiment. The pixel isolation
film 19 having the opening H4 is formed on the source/drain electrode
layer 18. The opening H4 is opposed to the source/drain electrodes 18a.
The pixel isolation film 19 is made of a photosensitive resin material
such as polyimide or acrylic-based resin.

[Manufacturing Method]

[0078] The display device 1A as described above can be manufactured, for
example, as described below. First, the pattern of the drive substrate
11A (the gate electrode 12a and the laminated film 24) is formed using
photolithography technique. For example, each film is formed first,
followed by steps including coating with photoresist, pre-bake, exposure
using a photomask, development, post-bake, etching (wet or dry),
photoresist removal and the like, after which the film is patterned.

[0079] In the present embodiment, a total of five photomasks are used in
such a photolithography process. Going into more detail, a photomask (M1)
is used to pattern the gate electrode 12a (the electrode layer 12b), and
a total of four photomasks (M2 to M5) are used to pattern the laminated
film 24 (the semiconductor layer 14, the first protective film 15, the
second protective film 16, the planarizing film 17, the source/drain
electrode layer 18 and the pixel isolation film 19). More specifically,
the drive substrate 11A is manufactured by the following procedure.

[0080] That is, the above-described gate electrode material is formed over
the entire substrate 11 by, for example, sputtering, followed by
patterning by photolithography using the photomask M1 (unshown). More
specifically, as illustrated in FIG. 2A, the gate electrode 12a is formed
in a selective region (a region 10B1 for the transistor section 10B) on
the substrate 11, and the electrode layer 12b is formed across regions
10C1 and 10D1 respectively for the capacitor section 10C and the
interconnect contact section 10D. The gate electrode 12a and the
electrode layer 12b are formed all together.

[0081] Next, as illustrated in FIG. 2B, the gate insulating film 13 is
formed, for example, by CVD (Chemical Vapor Deposition) method over the
entire surface of the substrate 11 on which the gate electrode 12a and
the electrode layer 12b have been formed. At this time, if a silicon
nitride film is formed as the gate insulating film 13, a mixture gas
containing silane (SiH4), ammonia (NH3) and nitrogen is used as
a raw material gas. Alternatively, if a silicon oxide film is formed as
the gate insulating film 13, a mixture gas containing silane and
dinitrogen oxide (N2O) is used.

[0082] Next, the semiconductor layer 14 is formed on the gate insulating
film 13, for example, by sputtering. More specifically, IGZO is used as
the semiconductor layer 14, reactive sputtering is performed using an
IGZO ceramic as a target. At this time, for example, a chamber of a DC
(direct current) sputtering system is exhausted to a predetermined vacuum
level first. Then, the target and the substrate 11 are placed in the
chamber, after which a mixture gas of argon (Ar) and oxygen (O2) is
introduced for plasma discharge.

[0083] Next, the first protective film 15 made of the above-described
materials is formed on the semiconductor layer 14, for example, by CVD
method.

[0084] Next, as illustrated in FIG. 2C, the first protective film 15 and
the semiconductor layer 14 are patterned all together by photolithography
using the photomask M2 (unshown). At this time, the surface of the gate
insulating film 13 is exposed in the region 10D1 for the interconnect
contact section 10D. That is, a contact hole H1a is formed to penetrate
the first protective film 15 and the semiconductor layer 14 in the region
10D1.

[0085] Next, as illustrated in FIG. 2D, the second protective film 16 made
of the materials described above is formed, for example, by sputtering
above the entire surface of the substrate 11 followed by the coating with
the planarizing film 17, for example, by spin coating or slit coating
above the entire surface of the substrate 11.

[0086] Next, as illustrated in FIG. 2E, the planarizing film 17 is
patterned by photolithography using the unshown photomask M3. At this
time, contact holes H3b are formed in the region 10B1 for the transistor
section 10B, and a contact hole H2b is formed in the region 10C1 for the
capacitor section 10C, thus exposing the surface of the second protective
film 16. A contact hole H1b is also formed in the region 10D1 of the
planarizing film 17 for the interconnect contact section 10D, thus
exposing the surface of the second protective film 16. That is, the
contact holes H1b, H2b and H3b adapted to act as mask openings in the
next step are formed in the regions 10B1, 10C1 and 10D1.

[0087] Next, as illustrated in FIG. 2F, dry etching is, for example,
performed using the patterned planarizing film 17 as a mask, thus
removing selective regions from the second protective film 16 and the
first protective film 15 all together in the regions 10B1 and 10C1 and
thereby exposing the surface of the semiconductor layer 14. This allows
for the contact holes H2 and H3 to be formed that penetrate the
planarizing film 17, the second protective film 16 and the first
protective film 15.

[0088] In the region 10D1, a selective region is removed from the second
protective film 16 and the gate insulating film 13, thus exposing the
surface of the electrode layer 12b. This allows for the contact hole H1
to be formed that penetrates the planarizing film 17, the second
protective film 16 and the gate insulating film 13. It should be noted
that the etching selectivity at this time should preferably be, for
example, 20 or more between the semiconductor layer 14 and the first
protective film 15, and 3 or more between the electrode layer 12b and the
gate insulating film 13.

[0089] Next, after the formation of the contact holes H1 to H3, the
source/drain electrode layer 18 is formed, for example, by sputtering.
The source/drain electrode layer 18 is formed by depositing the
above-described materials over the entire surface of the planarizing film
17 in such a manner as to cover the bottom surfaces of the contact holes
H1 to H3. Then, as illustrated in FIG. 2G, the source/drain electrode
layer 18 is patterned by photolithography using the unshown photomask M4.
More specifically, the source/drain electrode layer 18 is divided for
each of the regions 10B1, 10C1 and 10D1 and shaped into a desired form.
This allows for the transistor section 10B, the capacitor section 10C and
the interconnect contact section 10D to be formed on the substrate 11.

[0090] Next, the pixel isolation film 19 made of the above-described
materials is formed, for example, by coating on the source/drain
electrode layer 18 above the entire surface of the substrate 11. Then, as
illustrated in FIG. 2H, the pixel isolation film 19 is patterned by
photolithography using the unshown photomask M5. More specifically, the
opening H4 is formed in a region 10A1 (region for the source/drain
electrode 18a acting as an anode electrode) for the light-emitting
section 10A. The drive substrate 11A is manufactured as described above.

[0091] Then, the functional layer 20 is formed on the drive substrate 11A,
for example, by vacuum deposition, followed by the formation of the
common electrode 21 made of the above-described materials, for example,
by sputtering. Next, after the formation of the protective layer 22, the
sealing substrate 23 is attached to the protective layer 22, thus
completing the manufacture of the display device 1A shown in FIG. 1.

[Action and Effect]

[0092] When a drive current commensurate with the video signal of each of
red, green and blue is applied to each of the red, green and blue pixels
in the display device 1A, electrons and holes are injected into the
functional layer 20 via the source/drain electrode layer 18 serving as an
anode and the common electrode 21 serving as a cathode. The electrons and
holes respectively recombine in the organic EL layer included in the
functional layer 20, thus emitting light. The display device 1A displays
full color RGB images as described above.

[0093] In the present embodiment, the gate electrode 12a and the electrode
layer 12b are formed on the substrate 11, followed by the formation of
the laminated film 24 including the semiconductor layer 14, the first
protective film 15, the second protective film 16, the planarizing film
17, the source/drain electrode layer 18 and the pixel isolation film 19
on or above the gate electrode 12a with the gate insulating film 13
sandwiched therebetween by photolithography technique in the
manufacturing process of the display device 1A (drive substrate 11A)
described above. Then, the functional layer 20 including the organic EL
layer and the common electrode 21 are formed in this order. In the step
of forming the laminated film 24, two or more layers are patterned all
together in at least part of the laminated film 24. For example, the
first protective film 15 and the semiconductor layer 14 are patterned all
together using the photomask M2. Further, the second protective film 16
and the first protective film 15 are patterned all together in the
regions 10B1 and 10C1, and the second protective film 16 and the gate
insulating film 13 are patterned all together in the region 10D1 using
the patterned planarizing film 17 as a mask, thus forming the contact
holes H1 to H3.

[0094] Further, the source/drain electrode layer 18 is formed on the
planarizing film 17 using the contact hole H3 formed as a result of the
patterning of two films at the same time, thus making it possible to use
the source/drain electrode layer 18 as an anode electrode. It is also
possible to form the capacitor section 10C and the interconnect contact
section 10D, i.e., the sections necessary for driving the pixels, in the
same step as that of forming the transistor section 10B using the contact
holes H2 and H1.

[0095] Here, as a comparative example of the present embodiment, FIGS. 3A
to 3H illustrate the manufacturing method of a drive substrate using nine
photomasks in the photolithography process in order of the steps. That
is, one photomask is used during the formation of the gate electrode, and
a total of eight photomasks are used in the steps from the formation of
the semiconductor layer to that of the pixel isolation film in a
comparative example. More specifically, a gate electrode 102a and an
electrode layer 102b are formed in selective regions on a substrate 101
using an unshown photomask M101, followed by the successive formation of
a gate insulating film 103, a semiconductor layer 104 and a first
protective film 105. Then, as illustrated in FIG. 3A, the first
protective film 105 is patterned in the form of an island using an
unshown photomask M102, followed by the patterning of the semiconductor
layer 104 in the form of an island using an unshown photomask M103 as
illustrated in FIG. 3B.

[0096] Next, as illustrated in FIG. 3c, the gate insulating film 103 is
patterned using an unshown photomask M104, followed by the formation of a
source/drain electrode 106. Then, as illustrated in FIG. 3D, the
source/drain electrode 106 is patterned using an unshown photomask M105.
Next, a second protective film 107 is formed, followed by the patterning
of the same film 107 using an unshown photomask M106 as illustrated in
FIG. 3E. Next, a planarizing film 108 is formed above the entire surface
of the substrate, followed by the patterning of the planarizing film 108
using an unshown photomask M107 as illustrated in FIG. 3F, thus allowing
for a contact hole H101 communicating with the source/drain electrode 106
to be formed. Next, an anode electrode 109 is formed in such a manner as
to fill the contact hole H101, followed by the patterning of the anode
electrode 109 using an unshown photomask M108 as illustrated in FIG. 3G.
Finally, a pixel isolation film 110 is formed above the entire surface of
the substrate, followed by the patterning of the pixel isolation film 110
using an unshown photomask M109 as illustrated in FIG. 3H, thus forming
an opening H102 adapted to partition the light-emitting region.

[0097] In the above comparative example, each film is patterned by
photolithography to manufacture the drive substrate. Therefore, a total
of nine photomasks are used, thus resulting in more consumption of
photoresist and other materials, higher cost and a larger number of film
formation steps.

[0098] In contrast, the present embodiment changes for the better the
configuration of the layers making up the laminated film 24 and the order
thereof, thus ensuring a reduced number of times of patterning by
photolithography.

[0099] FIG. 4 illustrates the voltage-current characteristic (relationship
between a gate voltage Vg and drive current Id) of the transistor section
10B in the drive substrate 11A manufactured using five photomasks as
described in the present embodiment. Thus, even if the order of stacking
the layers such as the source/drain electrode layer 18 and the
planarizing film 17 is changed, the first protective film 15 and the
second protective film 16 are provided on and above the semiconductor
layer 14 (an etch stopper structure is achieved), thus allowing for the
formation of highly reliable TFTs.

[0100] As described above, in the present embodiment, at least two or more
layers of the laminated film 24 are patterned all together in the step of
forming the same film 24. Here, the first protective film 15 and the
semiconductor layer 14 are patterned all together using, for example, the
photomask M2. Further, etching is performed using the planarizing film 17
as a mask, thus forming the contact holes H1 to H3 in the regions 10B1,
10C1 and 10D1 all together. This contributes to less consumption of
photomasks, photoresist and other materials and a smaller number of steps
in the manufacturing process. This allows for manufacturing of a display
device by a low-cost and simple process.

Second Embodiment

[0101] A description of a display device (display device 1B) according to
a second embodiment of the present disclosure will be given next. In the
description given below, the same components as those of the display
device 1A according to the first embodiment are denoted by the same
reference symbols, and the description will be omitted as appropriate.

[Configuration of the Display Device 1B]

[0102] FIG. 5 illustrates the cross-sectional structure of the display
device 1B. The display device 1B is an active matrix type organic EL
display as is the display device 1A according to the first embodiment,
and includes the functional layer 20, the common electrode 21, the
protective layer 22 and the sealing substrate 23 on a drive substrate
11B. Further, in the functional layer 20, a region for a opening H4 of a
pixel isolation film 19A which will be described later serves as a
light-emitting section 30A.

[0103] In the drive substrate 11B, the transistor section 10B, the
capacitor section 10C and the interconnect contact section 10D are also
provided for each pixel on the substrate 11 to drive the pixel in the
present embodiment. Further, the patterns of the transistor section 10B,
the capacitor section 10C and the interconnect contact section 10D are
formed on the substrate 11 by a thin film formation process based on
photolithography technique.

[0104] Further, in the laminated film 24, the contact holes H3 and a
contact hole H5 are provided in the transistor section 10B and the
capacitor section 10C to penetrate the planarizing film 17, the second
protective film 16 and the first protective film 15. The contact hole H1
is provided in the interconnect contact section 10D to penetrate a
planarizing film 17A, the second protective film 16 and the gate
insulating film 13. Still further, the source/drain electrode layer 18 is
formed on the planarizing film 17A in such a manner as to fill the
contact holes H1, H3 and H5.

[0105] It should be noted, however, that part (14a) of the semiconductor
layer 14 is exposed from the planarizing film 17A and the pixel isolation
film 19A in the region for the light-emitting section 30A in the present
embodiment, and that the functional layer 20 is provided on and in
contact with the exposed region of the semiconductor layer 14. That is,
in the present embodiment, the region 14a of the semiconductor layer 14
serves as a display pixel electrode (e.g., anode electrode). The region
14a has been treated for reduced resistance and therefore shows a
resistance value suitable for use as a pixel electrode.

[0106] It should be noted that the source/drain electrode layer 18 is
divided into segments for each of the transistor section 10B, the
capacitor section 10C and the interconnect contact section 10D, as with
the first embodiment. In the present embodiment, however, the same layer
18 is removed from the region for the light-emitting section 30A by the
patterning step which will be described later.

[0107] The display device 1B may be a top emission or bottom emission
display device as with the first embodiment. It should be noted, however,
that if the display device 1B is a top emission display device, the gate
electrode 12a (electrode layer 12b) is used as a reflective electrode. In
this case, it is preferable to stack an AlNd alloy as the gate electrode
12a. Alternatively, if the display device 1B is a bottom emission display
device, the gate electrode 12a (electrode layer 12b) should preferably be
separated as far as possible from the light-emitting section 30A. It
should be noted that if the display device 1B is a bottom emission
display device, it is possible to take advantage of the transparency of
the oxide semiconductor, thus making it possible to extract emitted light
from under the substrate 11 without any problem.

[Manufacturing Method]

[0108] The display device 1B as described above can be manufactured, for
example, as described below. First, the pattern of the drive substrate
11B (gate electrode 12a and laminated film 24) is formed using the
photolithography technique as described above.

[0109] It should be noted, however, that a total of four photomasks are
used in such a photolithography process in the present embodiment. Going
into more detail, one photomask (M1) is used to pattern the gate
electrode 12a (electrode layer 12b), and a total of three photomasks (M2,
M3A and M4A) are used to pattern the laminated film 24 (semiconductor
layer 14, first protective film 15, second protective film 16,
planarizing film 17A, source/drain electrode layer 18 and pixel isolation
film 19A). More specifically, the drive substrate 11B is manufactured by
the following procedure.

[0110] That is, the pattern of the gate electrode 12a (electrode layer
12b) is formed by photolithography using the unshown photomask M1 in the
same manner as in the first embodiment. Next, the gate insulating film
13, the semiconductor layer 14 and the first protective film 15 are
formed in this order in the same manner as in the first embodiment. Then,
the first protective film 15 and the semiconductor layer 14 are patterned
all together by photolithography using the unshown photomask M2 in the
same manner as in the first embodiment, thus forming the contact hole H1a
in the region 10D1. Next, the second protective film 16 and the
planarizing film 17A are formed above the entire surface of the substrate
11 in the same manner as in the first embodiment.

[0111] Then, as illustrated in FIG. 6A, the planarizing film 17A is
patterned by photolithography using the unshown photomask M3A. At this
time, the contact hole H3b is formed in the region 10B1 for the
transistor section 10B in the same manner as in the first embodiment,
thus exposing the surface of the second protective film 16. Further, the
contact hole H1b is also formed in the region 10D1 of the planarizing
film 17A for the interconnect contact section 10D, thus exposing the
surface of the second protective film 16. A contact hole H5b is formed to
extend from the region 10C1 for the capacitor section 10C to a region
30A1 for the light-emitting section 30A. That is, the contact holes H1b,
H5b and H3b adapted to act as mask openings in the next step are formed
in the regions 10B1, 10C1, 10D1 and 30A1.

[0112] Next, as illustrated in FIG. 6B, dry etching is, for example,
performed using the patterned planarizing film 17 as a mask, thus
removing selective regions from the second protective film 16 and the
first protective film 15 all together in the regions 10B1, 10C1 and 30A1
and thereby exposing the surface of the semiconductor layer 14. This
allows for the contact holes H3 and H5 to be formed that penetrate the
planarizing film 17A, the second protective film 16 and the first
protective film 15. The contact hole H1 is formed in the region 10D1 to
penetrate the second protective film 16 and the gate insulating film 13
in the same manner as in the first embodiment.

[0113] Next, after the formation of the contact holes H1, H3 and H5, the
source/drain electrode layer 18 is formed, for example, by sputtering as
illustrated in FIG. 6C. The same layer 18 is formed by depositing the
above-described materials over the entire surface of the planarizing film
17A in such a manner as to cover the bottom surfaces of the contact holes
H1, H3 and H5. Next, the pixel isolation film 19A made of the
above-described materials is formed, for example, by coating on the
source/drain electrode layer 18 above the entire surface of the substrate
11.

[0114] Next, as illustrated in FIG. 6D, the pixel isolation film 19A is
patterned by photolithography using the unshown photomask M4A. More
specifically, the opening H4 is formed in the region 30A1 for the
light-emitting section 30A. At the same time, an isolation groove H6a is
formed in the region 10B1, and an isolation groove H6b is formed between
the regions 10C1 and 10D1.

[0115] Next, as illustrated in FIG. 6E, wet etching is, for example,
performed using the patterned pixel isolation film 19A as a mask, thus
selectively removing the region 30A1 of the source/drain electrode 18 for
the opening H4 and the regions for the isolation grooves H6a and H6b.
That is, the semiconductor layer 14 is exposed in the region 30A1. At the
same time, the source/drain electrode layer 18 is divided at several
predetermined locations. This allows for the transistor section 10B, the
capacitor section 10C and the interconnect contact section 10D to be
formed on the substrate 11.

[0116] It should be noted that, after the patterning of the source/drain
electrode layer 18 using the pixel isolation film 19A as a mask, the
regions of the pixel isolation film 19A near the isolation grooves H6a
and H6b are in a so-called overhung shape (shape e1 in which the pixel
isolation film 19A hangs over the edge of the source/drain electrode 18a
as illustrated in an enlarged view of FIG. 6E) as a result of etching.
Such an overhung shape may be left unremoved. This makes it less likely
that leaks between the pixels may occur during vapor deposition of the
functional layer 20.

[0117] Alternatively, after the patterning of the source/drain electrode
layer 18, the pixel isolation film 19A is subjected to reflow, thus
bringing the pixel isolation film 19A into close contact with the
planarizing film 17 in such a manner as to fill the isolation grooves H6a
and H6b. This makes it possible to cover the electrode edge, a possible
cause of deterioration of the organic material (including shorting
between the anode and cathode resulting from faulty coverage of the
light-emitting layer), with an insulating material, thus providing
improved reliability. Here, a case is taken as an example in which such
reflow is performed.

[0118] Next, as illustrated in FIG. 6F, the exposed portion of the
semiconductor layer 14 is treated for reduced resistance. More
specifically, a plasma treatment using Ar, H2 or NH3 as a
reactive gas should preferably be performed so as to reduce the sheet
resistance, for example, to 5 kΩ/sq. or less. Here, FIG. 7
illustrates the relationship between the treatment time and sheet
resistance in an Ar plasma treatment. Thus, the sheet resistance has been
reduced to 1E+3 [kΩ/sq.]. This allows for the exposed portion (14a)
of the semiconductor layer 14 to act as an anode electrode. The drive
substrate 11B is manufactured as described above.

[0119] Then, the functional layer 20, the common electrode 21 and the
protective layer 22 are formed in this order on the drive substrate 11B
in the same manner as in the first embodiment, after which the sealing
substrate 23 is attached to the protective layer 22, thus completing the
manufacturing of the display device 1B shown in FIG. 5.

[Action and Effect]

[0120] As described above, in the present embodiment, the gate electrode
12a and the electrode layer 12b are formed on the substrate 11, followed
by the formation of the laminated film 24 including the semiconductor
layer 14, the first protective film 15, the second protective film 16,
the planarizing film 17A, the source/drain electrode layer 18 and the
pixel isolation film 19A on or above the gate electrode 12a with the gate
insulating film 13 sandwiched therebetween by photolithography technique
in the manufacturing process of the display device 1B (drive substrate
11B). Then, the functional layer 20 including the organic EL layer and
the common electrode 21 are formed in this order. In the step of forming
the laminated film 24, two or more layers are patterned all together in
at least part of the laminated film 24. Here, for example, the first
protective film 15 and the semiconductor layer 14 are patterned all
together using the photomask M2 in the same manner as in the first
embodiment. Further, the second protective film 16 and the first
protective film 15 are patterned all together in the regions 10B1, 30A1
and 10C1, and the second protective film 16 and the gate insulating film
13 are patterned all together in the region 10D1 using the patterned
planarizing film 17A as a mask, thus forming the contact holes H1, H3 and
H5.

[0121] Further, the semiconductor layer 14 is partially exposed, and the
exposed portion thereof is treated for reduced resistance in the contact
hole H5 formed as a result of the patterning of two films at the same
time, thus making it possible to use the part (14a) of the semiconductor
layer 14 as an anode electrode. Still further, it is possible to form the
capacitor section 10C and interconnect contact section 10D, i.e., the
sections necessary for driving the pixels, in the same step as that of
forming the transistor section 10B using part of the contact hole H5 and
the contact hole H1.

[0122] That is, the present embodiment also changes for the better the
configuration of the layers making up the laminated film 24 and the order
thereof, thus ensuring a reduced number of times of patterning by
photolithography as compared to the above-described comparative example.
This contributes to less consumption of photomasks, photoresist and other
materials and a smaller number of steps, thus allowing for manufacturing
of a display device by a low-cost and simple process.

Third Embodiment

[0123] A description of a display device (display device 1C) according to
a third embodiment of the present disclosure will be given next. In the
description given below, the same components as those of the display
device 1A according to the first embodiment are denoted by the same
reference symbols, and the description will be omitted as appropriate.

[Configuration of the Display Device 1C]

[0124] FIG. 8 illustrates the cross-sectional structure of the display
device 1C. The display device 1C is an active matrix type organic EL
display as is the display device 1A according to the first embodiment and
includes the functional layer 20, the common electrode 21, the protective
layer 22 and the sealing substrate 23 on a drive substrate 11C. Further,
in the functional layer 20, a region of the pixel isolation film 19 for
the opening H4 serves as a light-emitting section 31A. The display device
1C may be a top emission or bottom emission display device as with the
first embodiment.

[0125] In the drive substrate 11C, the transistor section 10B and the
capacitor section 10C are also provided for each pixel on the substrate
11 to drive the pixel in the present embodiment. Further, the patterns of
the transistor section 10B and the capacitor section 10C are formed on
the substrate 11 by a thin film formation process based on
photolithography technique. It should be noted that, although not shown
here, an interconnect contact section can be formed as follows. That is,
an interconnect contact section can be formed by etching down to the
surface of the electrode layer 12b during the etching using a planarizing
film 17b which will be described later so as to provide a contact hole
and forming an anode electrode 25 in such a manner as to fill the contact
hole.

[0126] It should be noted, however, that, in the present embodiment, the
laminated film 24 includes a source/drain electrode layer 18e and the
second protective film 16 provided in this order on and above the first
protective film 15, and that the planarizing film 17B is formed on the
second protective film 16. Further, the anode electrode 25 electrically
connected to the source/drain electrode layer 18e is separately provided
on the planarizing film 17B. The opening H4 of the pixel isolation film
19 is formed on the anode electrode 25.

[Manufacturing Method]

[0127] The display device 1C as described above can be manufactured, for
example, as described below. First, the pattern of the drive substrate
11C (gate electrode 12a and laminated film 24) is formed using the
photolithography technique as described above.

[0128] It should be noted, however, that a total of six photomasks are
used in such a photolithography process in the present embodiment. Going
into more detail, one photomask (M1) is used to pattern the gate
electrode 12a (electrode layer 12b), and a total of five photomasks (M2B
to M6B) are used to pattern the laminated film 24 (semiconductor layer
14, first protective film 15, source/drain electrode layer 18e, second
protective film 16, planarizing film 17B, anode electrode 25 and pixel
isolation film 19A). More specifically, the drive substrate 11C is
manufactured by the following procedure.

[0129] That is, the pattern of the gate electrode 12a (electrode layer
12b) is formed by photolithography using the unshown photomask M1 in the
same manner as in the first embodiment. Next, the gate insulating film
13, the semiconductor layer 14 and the first protective film 15 are
formed in this order in the same manner as in the first embodiment. Then,
the first protective film 15 is patterned by photolithography using the
unshown photomask M2B as illustrated in FIG. 9A.

[0130] Next, the source/drain electrode layer 18e is formed. Then, the
same layer 18e and the semiconductor layer 14 are patterned all together
using the unshown photomask M3B as illustrated in FIG. 9B, thus forming a
through-hole H7a in a region for the electrode layer 12b.

[0131] Then, as illustrated in FIG. 9C, the second protective film 16 and
the planarizing film 17B are formed by the above-described method above
the entire surface of the substrate. Next, the planarizing film 17B is
patterned using the unshown photomask M4B as illustrated in FIG. 9D, thus
forming a contact hole H8a adapted to act as a mask opening in the next
step.

[0132] Next, as illustrated in FIG. 9E, the second protective film 16 is
etched using the patterned planarizing film 17B as a mask. This exposes
the surface of the source/drain electrode layer 18e, thus forming a
contact hole H8 used to establish electrical connection with the anode
electrode 25.

[0133] Next, the anode electrode 25 is formed in such a manner as to fill
the contact hole H8, followed by the patterning of the same electrode 25
using the unshown photomask M5B as illustrated in FIG. 9F. Then, the
pixel isolation film 19 is formed above the entire surface of the
substrate, followed by the patterning of the same film 19 using the
unshown photomask M6B as illustrated in FIG. 9G, thus forming the opening
H4 adapted to partition the light-emitting region. The drive substrate
11C is manufactured as described above.

[0134] Then, the functional layer 20, the common electrode 21 and the
protective layer 22 are formed in this order on the drive substrate 11C
in the same manner as in the first embodiment, after which the sealing
substrate 23 is attached to the protective layer 22, thus completing the
manufacture of the display device 1C shown in FIG. 8.

[Action and Effect]

[0135] As described above, in the present embodiment, the gate electrode
12a and the electrode layer 12b are formed on the substrate 11, followed
by the formation of the laminated film 24 including the semiconductor
layer 14, the first protective film 15, the source/drain electrode layer
18e, the second protective film 16, the planarizing film 17B, the anode
electrode 25 and the pixel isolation film 19 on or above the gate
electrode 12a with the gate insulating film 13 sandwiched therebetween by
photolithography technique in the manufacturing process of the display
device 1C (drive substrate 11C). Then, the functional layer 20 including
the organic EL layer and the common electrode 21 are formed in this
order. In the step of forming the laminated film 24, two or more layers
are patterned all together in at least part of the laminated film 24.
Here, for example, the source/drain electrode layer 18e and the
semiconductor layer 14 are patterned all together using the photomask M3B
(the through-hole H7a is formed to penetrate the source/drain electrode
layer 18e and the semiconductor layer 14).

[0136] That is, the present embodiment also changes for the better the
configuration of the layers making up the laminated film 24 and the order
thereof, thus ensuring a reduced number of times of patterning by
photolithography as compared to the above comparative example. This
contributes to less consumption of photomasks, photoresist and other
materials and a smaller number of steps, thus allowing for manufacture of
a display device by a low-cost and simple process.

Fourth Embodiment

[0137] A description of a display device (display device 1D) according to
a fourth embodiment of the present disclosure will be given next. In the
description given below, the same components as those of the display
device 1A according to the first embodiment or the display device 1C
according to the third embodiment are denoted by the same reference
symbols, and the description will be omitted as appropriate.

[Configuration of the Display Device 1D]

[0138] FIG. 10 illustrates the cross-sectional structure of the display
device 1D. The display device 1D is an active matrix type organic EL
display as is the display device 1A according to the first embodiment and
includes the functional layer 20, the common electrode 21, the protective
layer 22 and the sealing substrate 23 on a drive substrate 11D. Further,
in the functional layer 20, a region of the pixel isolation film 19 for
the opening H4 serves as the light-emitting section 31A. The display
device 1D may be a top emission or bottom emission display device as with
the first embodiment.

[0139] The transistor section 10B, the capacitor section 10C and the
interconnect contact section 10D are also provided for each pixel on the
substrate 11 to drive the pixel in the present embodiment. Further, the
patterns of the transistor section 10B, the capacitor section 10C and the
interconnect contact section 10D are formed on the substrate 11 by a thin
film formation process based on photolithography technique.

[0140] It should be noted, however, that, in the present embodiment, the
laminated film 24 includes two first protective layers, namely, first
protective films 15a and 15b, on the semiconductor layer 14, and that the
source/drain electrode layer 18e and the second protective film 16 are
provided in this order on and above the first protective film 15b. The
planarizing film 17B is formed on the second protective film 16, and the
anode electrode 25 electrically connected to the source/drain electrode
layer 18e is separately provided on the planarizing film 17B. The opening
H4 of the pixel isolation film 19 is formed on the anode electrode 25.
The first protective films 15a and 15b are made, for example, of a
silicon oxide as is the first protective film 15 in the first embodiment.

[Manufacturing Method]

[0141] The display device 1D as described above can be manufactured, for
example, as described below. First, the pattern of the drive substrate
11D (gate electrode 12a and laminated film 24) is formed using the
photolithography technique as described above.

[0142] It should be noted, however, that, in the present embodiment, a
total of seven photomasks are used in such a photolithography process.
Going into more detail, a photomask (M1) is used to pattern the gate
electrode 12a (electrode layer 12b), and a total of six photomasks (M2C
to M7C) are used to pattern the laminated film 24 (semiconductor layer
14, first protective films 15a and 15b, source/drain electrode layer 18e,
second protective film 16, planarizing film 17B, anode electrode 25 and
pixel isolation film 19). More specifically, the drive substrate 11D is
manufactured by the following procedure.

[0143] That is, the pattern of the gate electrode 12a (electrode layer
12b) is formed by photolithography using the unshown photomask M1 in the
same manner as in the first embodiment. Next, the gate insulating film 13
and the semiconductor layer 14 are formed in this order in the same
manner as in the first embodiment. Then, the first protective film 15a is
formed, for example, by CVD method, after which the first protective film
15a and the semiconductor layer 14 are patterned all together by
photolithography using the unshown photomask M2C as illustrated in FIG.
11A, thus forming the contact hole H1a in the region 10D1 for the
interconnect contact section 10D.

[0144] Next, as illustrated in FIG. 11B, the first protective film 15b is
formed above the entire surface of the substrate, for example by CVD
method. Then, as illustrated in FIG. 11C, the first protective films 15a
and 15b are patterned all together using the unshown photomask M3C. At
this time, the first protective film 15b and the gate insulating film 13
are patterned all together in the region 10D1, thus forming a
through-hole H1c.

[0145] Next, the source/drain electrode layer 18e is formed. Then, the
source/drain electrode layer 18e is patterned using the unshown photomask
M4C as illustrated in FIG. 11D, thus dividing the same layer 18e into
segments, one for each of the regions 10B1, 10C1 and 10D1 and forming the
transistor section 10B, the capacitor section 10C and the interconnect
contact section 10D.

[0146] Then, as illustrated in FIG. 11E, the second protective film 16 and
the planarizing film 17B are formed in this order by the above-described
method above the entire surface of the substrate. Next, the planarizing
film 17B is patterned using the unshown photomask M5C as illustrated in
FIG. 11F, thus forming the contact hole H8a adapted to act as a mask
opening in the next step.

[0147] Next, as illustrated in FIG. 11G, the second protective film 16 is
etched using the patterned planarizing film 17B as a mask. This exposes
the surface of the source/drain electrode layer 18e, thus forming the
contact hole H8 used to establish electrical connection with the anode
electrode 25.

[0148] Next, the anode electrode 25 is formed in such a manner as to fill
the contact hole H8, followed by the patterning of the same electrode 25
using the unshown photomask M6C as illustrated in FIG. 11H. Then, the
pixel isolation film 19 is formed above the entire surface of the
substrate, followed by the patterning of the same film 19 using the
unshown photomask M7C as illustrated in FIG. 11I, thus forming the
opening H4 adapted to partition the light-emitting region. The drive
substrate 11D is manufactured as described above.

[0149] Then, the functional layer 20, the common electrode 21 and the
protective layer 22 are formed in this order on the drive substrate 11D
in the same manner as in the first embodiment, after which the sealing
substrate 23 is attached to the protective layer 22, thus completing the
manufacture of the display device 1D shown in FIG. 10.

[Action and Effect]

[0150] As described above, in the present embodiment, the gate electrode
12a and the electrode layer 12b are formed on the substrate 11, followed
by the formation of the laminated film 24 including the semiconductor
layer 14, the first protective films 15a and 15b, the source/drain
electrode layer 18e, the second protective film 16, the planarizing film
17B, the anode electrode 25 and the pixel isolation film 19 on or above
the gate electrode 12a with the gate insulating film 13 sandwiched
therebetween by photolithography technique in the manufacturing process
of the display device 1D (drive substrate 11D). Then, the functional
layer 20 including the organic EL layer and the common electrode 21 are
formed in this order. In the step of forming the laminated film 24, two
or more layers are patterned all together in at least part of the
laminated film 24. Here, for example, the first protective film 15a and
the semiconductor layer 14 are patterned all together using the photomask
M2C, thus forming the contact hole H1a to penetrate the first protective
film 15a and the semiconductor layer 14 in the region 10D1. Further,
after the formation of the contact hole H1a, the first protective film
15b and the gate insulating film 13 are patterned all together in the
region 10D1 using the photomask M3C, thus forming the contact hole H1c.

[0151] That is, the present embodiment also changes for the better the
configuration of the layers making up the laminated film 24 and the order
thereof, thus ensuring a reduced number of times of patterning by
photolithography as compared to the above comparative example. This
contributes to less consumption of photomasks, photoresist and other
materials and a smaller number of steps, thus allowing for manufacture of
a display device by a low-cost and simple process.

[Configuration of the Display Device and Pixel Circuit Configuration]

[0152] A description of the overall configuration of the display devices
1A to 1D (hereinafter simply referred to as the display devices)
respectively according to the first to fourth embodiments and the pixel
circuit configuration thereof will be given next. FIG. 12 illustrates the
overall configuration including peripheral circuitry of the display
device used as an organic EL display. As described above, a display
region 50 is formed on, for example, the substrate 11. The display region
50 has a plurality of pixels PXLC arranged in a matrix form. Each of the
pixels PXLC includes an organic EL element. A horizontal selector (HSEL)
51, a write scanner (WSCN) 52 and a drive scanner (DSCN) 53 are provided
around the display region 50. The horizontal selector 51 serves as a
signal drive circuit. The write scanner 52 serves as a scan drive
circuit. The drive scanner 53 serves as a power line drive circuit.

[0153] In the display region 50, a plurality (integer n) of signal lines
DTL1 to DTLn are arranged in the column direction, with a plurality
(integer m) of scan lines WSL1 to WSLm and power lines DSL1 to DSLm
respectively arranged in the row direction. Further, the pixel PXLC (one
of red, green and blue pixels) is provided at each of the intersections
between one of the signal lines DTL and one of the scan lines WSL. Each
of the signal lines DTL is connected to the horizontal selector 51 so
that a video signal is supplied from the horizontal selector 51 to each
of the signal lines DTL. Each of the scan lines WSL is connected to the
write scanner 52 so that a scan signal (selection pulse) is supplied from
the write scanner 52 to each of the scan lines WSL. Each of the power
lines DSL is connected to the drive scanner 53 so that a power signal
(control pulse) is supplied from the drive scanner 53 to each of the
power lines DSL.

[0154] FIG. 13 illustrates a specific circuit configuration example of the
pixel PXLC. Each of the pixels PXLC has a pixel drive circuit 50a
including an organic EL element 5D. The pixel drive circuit 50a is an
active drive circuit having a sampling transistor 5A, a drive transistor
5B, a holding capacitive element 5C and the organic EL element 5D. Of
these components, the transistor 5A (or transistor 5B) corresponds to the
transistor section 10B in the above embodiments, and the holding
capacitive element 5C to the capacitor section 10C in the above
embodiments.

[0155] The sampling transistor 5A has its gate connected to the associated
scan line WSL, one of its source and drain to the associated signal line
DTL, and the other of its source and drain to the gate of the drive
transistor 5B. The drive transistor 5B has its drain connected to the
associated power line DSL and its source to the anode of the organic EL
element 5D. The cathode of the organic EL element 5D is connected to a
grounding interconnect 5H. It should be noted that the grounding
interconnect 5H is shared by all the pixels PXLC. The holding capacitive
element 5C is arranged between the source and gate of the drive
transistor 5B.

[0156] The sampling transistor 5A goes into conduction in response to a
scan signal (selection pulse) supplied from the scan line WSL, thus
sampling the video signal potential supplied from the signal line DTL and
allowing the potential to be held by the holding capacitive element 5C.
The drive transistor 5B is supplied with a current from the power line
DSL at a predetermined first potential (not shown), thus supplying a
drive current commensurate with the signal potential held by the holding
capacitive element 5C to the organic EL element 5D. When supplied with
the drive current from the drive transistor 5B, the organic EL element 5D
emits light at the brightness commensurate with the video signal
potential.

[0157] In such a circuit configuration, the sampling transistor 5A goes
into conduction in response to a scan signal (selection pulse) supplied
from the scan line WSL, thus sampling the video signal potential supplied
from the signal line DTL and allowing the potential to be held by the
holding capacitive element 5C. Further, a current is supplied from the
power line DSL at the above predetermined first potential to the drive
transistor 5B, thus supplying a drive current commensurate with the
signal potential held by the holding capacitive element 5C to the organic
EL element 5D (each of the red, green and blue organic EL elements). When
supplied with the drive current, the organic EL element 5D emits light at
the brightness commensurate with the video signal potential, thus
allowing for an image to be displayed on the display device based on the
video signal.

APPLICATION EXAMPLES

[0158] A description of application examples of one of the above display
devices (display devices 1A to 1D) to electronic equipment will be given
below. Among examples of electronic equipment are a television set, a
digital camera, a laptop personal computer, a personal digital assistance
such as a mobile phone and a video camcorder. In other words, one of the
above display devices is applicable to electronic equipment across all
disciplines adapted to display a video signal fed thereto or generated
therein as an image or picture.

(Module)

[0159] One of the above display devices is built into a variety of
electronic equipment including application examples 1 to 5, which will be
described later, as a module as shown in FIG. 14, for example. This
module is manufactured, for example, as follows. That is, a region 210
exposed from a sealing substrate 60 is provided on one side of the
substrate 11. Then, the interconnects of the horizontal selector 51, the
write scanner 52 and the drive scanner 53 are extended to the exposed
region 210, thus forming external connection terminals (not shown). An
FPC (flexible printed circuit) 220 adapted to exchange signals may be
provided on the external connection terminals.

Application Example 1

[0160] FIG. 15 illustrates the appearance of a television set. This
television set has, for example, a video display screen section 300
including a front panel 310 and a filter glass 320. The video display
screen section 300 corresponds to one of the above display devices.

Application Example 2

[0161] FIGS. 16A and 16B illustrate the appearance of a digital camera.
This digital camera has, for example, a flash-emitting section 410, a
display section 420, a menu switch 430 and a shutter button 440. The
display section 420 corresponds to one of the above display devices.

Application Example 3

[0162] FIG. 17 illustrates the appearance of a laptop personal computer.
This laptop personal computer has, for example, a main body 510, a
keyboard 520 adapted to be manipulated for entry of text or other
information and a display section 530 adapted to display an image. The
display section 530 corresponds to one of the above display devices.

Application Example 4

[0163]FIG. 18 illustrates the appearance of a video camcorder. This video
camcorder has, for example, a main body section 610, a lens 620 provided
on the front-facing side surface to capture the image of the subject, an
imaging start/stop switch 630 and a display section 640. The display
section 640 corresponds to one of the above display devices.

Application Example 5

[0164] FIGS. 19A to 19G illustrate the appearance of a mobile phone. This
mobile phone is made up, for example, of an upper enclosure 710 and a
lower enclosure 720 that are connected together with a connecting section
(hinge section) 730 and has a display 740, a subdisplay 750, a picture
light 760 and a camera 770. Each of the display 740 and subdisplay 750
corresponds to one of the above display devices.

[0165] Although the present disclosure has been described above with
reference to the preferred embodiments, the present disclosure is not
limited thereto and may be modified in various ways. For example,
although examples have been described in the above embodiments in which
the bottom gate TFT has the first protective film 15, the same film 15
does not necessarily have to be provided.

[0166] Further, cases have been taken in the above embodiments as examples
in which four to seven photomasks are used to form the drive substrate by
patterning (three to six in the step of forming the laminated film 24).
However, eight photomasks may be used to form the drive substrate (seven
in the step of forming the laminated film 24). In the manufacturing
process according to the comparative example shown in FIGS. 3A to 3H, for
example, etching the second protective film 107 using the planarizing
film 108 as a mask contributes to the reduction of the number of
photomasks used by one as compared to the manufacturing process according
to the comparative example.

[0167] The present disclosure contains subject matter related to that
disclosed in Japanese Priority Patent Application JP 2011-066283 filed in
the Japan Patent Office on Mar. 24, 2011, the entire content of which is
hereby incorporated by reference.

[0168] It should be understood by those skilled in the art that various
modifications, combinations, sub-combinations and alterations may occur
depending on design requirements and other factors insofar as they are
within the scope of the appended claims or the equivalents thereof.

Patent applications by Takahide Ishii, Kanagawa JP

Patent applications by SONY CORPORATION

Patent applications in class In array having structure for use as imager or display, or with transparent electrode

Patent applications in all subclasses In array having structure for use as imager or display, or with transparent electrode