Barefoot Joins 400GbE-Switch Club
The startup plans to bring programmability to 400G Ethernet, with samples of its Tofino 2 switch chip due in 1H19. Employing 50Gbps PAM4 serdes, the new product delivers 12.8Tbps of bandwidth.

Editorial: Chiplets Gain Design Winlets
More companies are deploying multiple die in a single package using 2.5D and 3D approaches, including Intel’s new Foveros technology, but cost remains a problem.

December 24, 2018

Snapdragon 855 Is a Prime Choice
Qualcomm’s next-generation processor for premium smartphones offers a “prime core,” a new AI accelerator, and multigigabit wireless connectivity, including 2Gbps LTE and optional 5G.

New MCUs Embrace Cortex-M33
NXP and STMicroelectronics are sampling the first Arm Cortex-M33 microcontrollers that implement TrustZone and other security features: NXP’s LPC5500 family and ST’s STM32L5 family.

December 10, 2018

Esperanto Maxes Out RISC-V
The startup has developed a high-performance RISC-V CPU called ET-Maxion that it plans to ship in its first AI accelerator and also license to select customers.

PAM4 Drives Serdes to 100Gbps
Data centers are on the cusp of 400G Ethernet adoption enabled by 100Gbps-per-lambda optical modules, which require PHYs with sophisticated signal processing. Six vendors are now sampling such chips.

Ambiq Apollo 3 Boosts Wearables
Ambiq is using its initial success in Huawei wearables to improve its Apollo MCUs. Apollo 3 Blue adds features while reducing power compared with Apollo 2.

December 3, 2018

AMD Ships Industry’s First 7nm GPU
By moving its Vega GPU architecture to 7nm, AMD boosted the performance of its Radeon Instinct cards, which support AI and scientific computing but not PC graphics.

TI Samples Its First 64-Bit Arm
Texas Instruments’ new Sitara AM65x processors combine up to four Cortex-A53 CPUs, three real-time-control subsystems, two 32-bit Cortex-R5F microcontroller cores, and an optional GPU.

Intel, AMD Monsters Battle for HPC
SC18 brought new server-processor disclosures from Intel and AMD. The former announced its 48-core Cascade Lake Advanced Performance while the latter disclosed new details of its 64-core Rome.

Arteris Upgrades NoC for AI
The new version of Arteris IP’s network-on-a-chip (NoC) intellectual property adds several upgrades, including features that help to design artificial-intelligence processors and other SoCs.

Imagination Cuts GNSS Power
A new package of synthesizable intellectual property (IP) for integrating a low-power global-navigation receiver in SoCs, the Ensigma Series 4 takes “snapshots” to save energy when determining location.

November 12, 2018

SiFive Raises RISC-V Performance
At the Linley Fall Processor Conference, SiFive revealed its 7 Series cores. The new CPU is its most complex yet, moving into the same class as Arm’s “little” Cortex-A family.

Editorial: AI Competition Begins to Bloom
Several new vendors are challenging Nvidia’s performance lead in neural-network inference and training, including Cornami, Graphcore, Habana, Intel/Nervana, Wave, and Xilinx.

Wave Exposes Broad Roadmap
Wave Computing is offering evaluation versions of its initial AI-acceleration systems while developing a second-generation ASIC, new MIPS cores, and its first licensable AI accelerators.

Tachyum Tries for Hyperscale Servers
The startup is developing a 64-core server processor, targeting tapeout late next year. The 7nm design implements a VLIW instruction set with custom vector and matrix instructions and a custom fabric.

Eta Compute MCU Puts AI in IoT
The startup’s new Tensai chip combines an MCU with a DSP for machine learning. Eta completes its solution with optimized neural-network software for machine learning.

Editorial: NXP Drives to the Future
Facing a future without Qualcomm, NXP will focus on its core automotive and industrial markets while de-emphasizing networking and mobile. Its new AI strategy focuses on software.