6.4.3 Effect of real surfaces Departure from the ideal case is due to Work function difference between the doped polysilicon gate and substrate The inevitably.

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Presentation on theme: "6.4.3 Effect of real surfaces Departure from the ideal case is due to Work function difference between the doped polysilicon gate and substrate The inevitably."— Presentation transcript:

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6.4.3 Effect of real surfaces Departure from the ideal case is due to Work function difference between the doped polysilicon gate and substrate The inevitably charges at the Si-SiO 2 interface and within the oxide

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To accommodate the work function difference The metal is positively charged and the semiconductor surface is negatively charged at equilibrium. A tilt in the oxide conduction band (implying an electric field) The bend down near the semiconductor surface. In fact, if the Ф ms is sufficiently negative, an inversion region can exist with no external voltage applied. To obtain the flat band conduction, we must apply a negative voltage to the metal (V FB = Ф ms. Equilibrium Diagram

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Charges in oxide Alkali metal ions (particularly Na + ) can be incorporated inadvertently in the oxide. Sodium ions introduce positive charges (Q m ) in the oxide, which in turn induce negative charges in the semiconductor. (distance sensitive) Charges at O/S interface (Q it ) Result from sudden termination of the semiconductor crystal lattice at the oxide surface. Fixed charges in transition layer (Q f ) Near the interface is a transition layer (SiOx) containing fixed charges (Q f ) Uncompensated Si bonds Some ionic Si left Q it and Q f are about 10 10 charges/cm 2 for carefully treated interfaces with {100} surfaces. Interface charge For simplicity we will include the various oxide and interface charges in an effective positive at the interface Q i (C/cm 2 ) The effect of this charge is to induce an equivalent negative charge in the semiconductor.

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Since the difference in work function and the positive interface charge both tend to bend the bands down at the semiconductor surface, a negative voltage must be applied to the metal relative to the semiconductor to achieve the flat band conduction. Flat band condition

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Influence of material parameters on threshold voltage All four terms give negative contributions in the p-channel case. Negative threshold voltage (V T ) for p-channel devices. N-channel devices may have either positive or negative threshold voltages, depending on the relative values of terms.

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Influence of material parameters on threshold voltage All terms except Q i /C i depend on the doping in the substrate. Ф ms and  F have relatively small variations as E F is moved up or down by the doping. Large changes can occur in Q d, which varies with the square root of the doping impurity concentration. p-channel: V T is always negative. n-channel for lightly doped p-type substrates, negative flat band voltage terms can dominate resulting in a negative V T. for more heavily doped substrates, the increasing contribution of N a to the Q d term dominates, and V T becomes positive.

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Threshold voltage In a p-channel devices (V T <0 always) A negative V T means that the negative voltage we apply must be larger than V T in order to achieve strong inversion. We expect to apply a negative voltage from metal to semiconductor in order to induce the positive charges in the channel. In an n-channel devices A positive value for V T means the applied voltage must be larger than this threshold value to obtain strong inversion and a conducting n channel. We expect to apply a positive voltage to the metal to induce the n channel. (enhancement mode, normally off) A negative V T means that a channel exists at V=0 due to the Ф ms and Q i effects. We must apply a negative voltage V T to turn the device off. (depletion mode, normally on) Since lightly doped substrates are desirable to maintain a high breakdown voltage for the drain junction, V T will be negative for n-channel devices made by standard processing.

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1. Type of substrate doping If the high-frequency capacitance is large for negative gate biases and small for positive biases, it is a p-type substrate, and vice versa. For the low frequency C-V curve for p-type material, as the gate bias is made more positive (or less negative), the capacitance goes down slowly in depletion and then rises rapidly in inversion. As a result, the low frequency C-V is not quite symmetric in shape. high-frequency low-frequency

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3. The minimum depletion capacitance C min → C dmin The minimum MOS capacitance, C min, is the series combination of C i and minimum depletion capacitance C dmin =  s /W m, corresponding to the maximum depletion width. We can in principle use the measurement of C min to deduce C dmin.

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4. Minimum depletion capacitance C dmin =  s /W m → substrate doping The minimum MOS capacitance, C min, is the series combination of C i and minimum depletion capacitance C dmin =  s /W m, corresponding to the maximum depletion width. We can in principle use the measurement of C min to deduce C dmin. We can use deduced C dmin to find W m and then to determine the substrate doping N a.

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5. Substrate doping → flat-band capacitance C FB Debye length is determined from the substrate doping. The semiconductor capacitance at flat band C FB is determined from the Debye length capacitance. The overall MOS flat band capacitance, C FB, is the series combination of C Debye and C i.

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7. C i, V FB, substrate doping → V T Once C i, V FB, and substrate doping are obtained, all terms in the V T expression are known. V FB Interestingly, the threshold voltage V T does not correspond to exactly the minimum of the C-V characteristics, C min, but a slightly higher capacitance marked as point 4. In fact, it corresponds to the series combination of C i and 2C dmin. The reason for this is that when we change the gate bias around strong inversion, the change of charge in the semiconductor is the sum of the change in depletion charge and the mobile inversion charge, where the two are equal in magnitude at the onset of strong inversion.

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8. Fast interface state density, D it  These defects can change their charge state relatively fast in response to changes of the gate bias. A fast interface state moving above the Fermi level would tend to give up its trapped electron to the semiconductor (or equivalently capture a hole). The same fast interface state below the Fermi level captures an electron (or gives up a hole). (Note: To talk in terms of electron or holes depends on which is the majority carrier in the semiconductor.)  The fast interface states give rise to a capacitance which is in parallel with the depletion capacitance in the channel(and hence is additive), and this combination is in series with the insulator capacitance C i.  The fast interface states contribute to the low frequency capacitance C LF, but not the high frequency capacitance C HF.

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8. Mobile ion charge, Q m  Bias-temperature stress test Heat up the MOS device to ~200-300 o C (to make the ions more mobile) and apply a positive gate bias to generate a field of ~1MV/cm within the oxide. After cooling the capacitor to room temperature, the C-V characteristics are measured. The capacitor is heated up again, a negative bias is applied so that the ions drift to the gate electrode. And another C-V measurement is made.  The positive bias repels positive mobile ions such as Na + to the oxide-silicon interface so that they contribute fully to a flat band voltage we can call V FB +.  The negative bias attracts positive mobile ions, so they are too far away from the interface to affect the semiconductor band-bending, but induce an equal and opposite charge on the gate electrode. V FB + is determined.  from the difference of the two flat band voltages, we can determine the mobile ion content using

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Deep depletion If the gate bias is varied rapidly from accumulation to inversion, the depletion width can momentarily become greater than the theoretical maximum for gate bias beyond V T. This causes the MOS capacitance to drop below the theoretical minimum, C min, for a transient period. Zerbst technique This capacitance transient, C-t, forms the basis of a powerful technique to measure the lifetime. Deep depletion and Zerbst technique

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6.4.7 Current-Voltage characteristics of MOS gate oxides There can be some leakage current for real insulators.

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Fowler-Nordheim and direct tunneling Fowler-Nordheim tunneling Current for electrons going from the Si conduction band to the conduction band of SiO2, and then having the electrons “hop” along in the oxide to the gate electrode. Direct tunneling As the gate oxides are made thinner, that the electrons in the conduction band of Si can tunnel through the gate oxide and emerge in the gate, without having to go via the conduction band of the gate oxide. Tunneling currents are becoming a major problem in modern devices because the useful feature of high input impedance for MOS devices is degraded.

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Pursuit of high gate capacitance It is necessary to increase the gate capacitance C i (=  i /d) in order to increase the drain current. High-k dielectrics Use insulators with a dielectric constant higher than SiO 2, instead of reducing the gate oxide thickness d. Reducing d too much will increase the gate oxide field and cause the tunneling. Fowler-Nordheim tunneling current Electric field in the gate oxide Constant, function of m n * and barrier height Fowler-Nordheim tunneling current as a function of electric field across the oxide

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Time-dependent dielectric breakdown(TDDB) Prolonged charge transport through gate oxides can ultimately cause catastrophic electrical breakdown of the oxides, known as time-dependent dielectric breakdown (TDDB). 1.Electron tunneling into the conduction band of the gate oxide from the negative electrode cathode), then gaining energy from the electric field, thus becoming “hot” electrons in the gate oxide. 2.If they gain sufficient energy, they can cause impact ionization within the oxide and create electron-hole pairs. 3.These impact-generated holes, with very low mobilities, are trapped at defect sites within the oxide, near the cathode. 4.The resulting band diagram is altered by this sheet of trapped positive charge, which causes the internal electric field between this point and the gate to increase. 5.As a result, the barrier for electron tunneling from the gate into the oxide is reduced. 6.More electrons can tunnel into the oxide, and cause more impact ionization. 7.We get a positive feedback effect that can lead to a runaway TDDB process.

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Distortion of band edges by trapped holes and electrons from impact ionization leading TDDB

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6.1 Transistor Operation 6.2 The Junction FET 6.3 The Metal-Semiconductor FET 6.4 The Metal-Insulator-Semiconductor FET 6.5 The MOS Field-Effect Transistor We analyze the conductance of the channel and find the I D -V D characteristics as a function of gate voltage V G.