Abstract

Low latency, application, specific multipliers are required f o r many DSP algorithms. Tree multipliers are an obvious answer to this requirement. However, tree architectures have not been considered for automatic multiplier generation because they have been considered to be irregular. In this paper, a recursive methodology for generating $n \rightarrow2$ compressors (for n in the range $3\leq5$ n $5\leq64$) using the basic cells $3\rightarrow2$ and $4\rightarrow2$ is presented. This methodology results in a highly regular and modular layout that can be automatically generated. The performance of the resulting compressors is competitive with detailed full-custom design. The area and latency of the resulting layout for any n is predictable t o a fair degree of accuracy.

Copyright 1990 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.