Formality tackles ECOs

Some products donít get a lot of love and attention. They are considered mainstream products and they go through many minor improvement cycles, but few of these changes are enough to attract a lot of attention. One of these products in the Synopsys fold is their equivalence checker Ė Formality. Today, they are adding a new capability that will help with functional ECOs and adding the tag Ultra to the tool name. I spoke to Gal Hasson, senior director of marketing for RTL synthesis and test, about his new capability. This is an optional add-on to the tool so you donít automatically get it if you already have Formality.

When an RTL change is made, Formality Ultra makes it easier to find the changes in the netlist and then to drive the tools such as place and route to effect the change.

ECO normally happen late in the cycle and may come about becomes of bugs found during the verification process or late spec changes. Traditionally, these changes may cause you to iterate through the entire back end flow, but sometimes the risk of doing this is too high.If changes are made in the RTL, a user needs to quickly find the changes in the netlist without a complete re-synthesis, which could change many aspects of the final netlist. The goal is to minimize the impact on the place and route and thus any problems that come about from timing closure. An ECO loop would traditionally have taken between 3 and 10 weeks, based on a survey that Synopsys performed in 2013. They found that ECOs in network designs were the quickest and changes in processor took the most amount of time.

The new tool speeds up the cycle by quickly identifying the changes, then helps in the verification process by isolating the cones of logic that are affected and only re-verifying those pieces that have changed. This takes what was a 3 to 9 hours process down to 3 to 16 minutes. With the changes verified, they can be automatically fed into IC Compiler to make the minimal changes necessary.

Some of their customers are finding that this capability enables much more complex changes to be taken through the ECO process and thus saves them having to do as many revs through Design Compiler.

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