PATTERNED LIGHT EMITTING DEVICES - Light-emitting devices, and related components, systems and methods are disclosed. A light-emitting device can include a multi-layer stack of materials that includes a light-generating region and a first layer supported by the light-generating region. During use of the light-emitting device, light generated by the light-generating region can emerge from the light-emitting device via a surface of the first layer. The surface of the first layer can have a dielectric function that varies spatially as a pattern and at least about 45% of a total amount of light generated by the light-generating region can emerge from the light-emitting device emerges via the surface of the light-emitting device.

2009-01-15

20090014743

METHOD OF MAKING A LIGHT-EMITTING DIODE - Methods are disclosed for forming a vertical semiconductor light-emitting diode (VLED) device having an active layer between an n-doped layer and a p-doped layer; and securing a plurality of balls on a surface of the n-doped layer of the VLED device.

2009-01-15

20090014744

Semiconductor light-emitting device and method - The present invention discloses a semiconductor light-emitting device including a semiconductor light-emitting element, a first attaching layer and a wavelength conversion structure. The primary light emitted from the semiconductor light-emitting element enters the wavelength conversion structure to generate a converted light, whose wavelength is different form that of the primary light. In addition, the present invention also provides the method for forming the same.

2009-01-15

20090014745

Method of manufacturing high power light-emitting device package and structure thereof - A method of manufacturing high power light-emitting device packages and structure thereof, wherein the method thereof includes the steps of: (a) forming a plurality of lead frames, each of the lead frames includes a heat-dissipating element and a plurality of leads; (b) electroplating an outer surface of the lead frames each; (c) coating conductive gel on a surface of the heat-dissipatings each; (d) arranging at least one light-emitting chip on the conductive gel; (e) forming an encapsulant on each of the lead frames; (f) connecting at least one top electrode of the light-emitting chip with one of the leads; (g) coating silicon gel for covering the at one light-emitting chip, and forming integrally a focusing light convex surface on a top surface of the silicon gel; and (h) cutting off the tie-bars to separate the lead frames from one another, whereby forming a plurality of high power light-emitting device packages.

2009-01-15

20090014746

SOLDER ALLOYS - Lead-free solder compositions for bonding and sealing flat panel displays, CCD's, solar cells, light emitting diodes, and other optoelectronic devices are disclosed. The solders are based on alloys of Sn, Au, Ag, and Cu and one or more rare earth metals chosen from the following, Y, La, Ce, Pr, Sc, Sm, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. Optionally, the compositions may comprise In, Bi, or Zn. The solder compositions exhibit superior bonding capability in joining dissimilar surfaces such as those present in both the flat panel display and light emitting devices. Additionally the solders provide a strong barrier to the diffusion of both water and oxygen into these devices thus promoting longer device life times.

2009-01-15

20090014747

MANUFACTURING METHOD OF LIGHT EMITTING DIODE APPARATUS - A manufacturing method of a light emitting diode (LED) apparatus includes the steps of: forming at least one temporary substrate, which is made by a curable material, on a LED device; and forming at least a thermal-conductive substrate on the LED device. The manufacturing method does not need the step of adhering the semiconductor structure onto another substrate by using an adhering layer, and can make the devices to be in sequence separated after removing the temporary substrate, thereby obtaining several LED apparatuses. As a result, the problem of current leakage due to the cutting procedure can be prevented so as to reduce the production cost and increase the production yield.

2009-01-15

20090014748

METHOD OF ELECTRICALLY CONNECTING ELEMENT TO WIRING, METHOD OF PRODUCING LIGHT-EMITTING ELEMENT ASSEMBLY, AND LIGHT-EMITTING ELEMENT ASSEMBLY - A method of electrically connecting an element to wiring includes the steps of forming a conductive fixing member precursor layer at least on wiring provided on a base, and arranging an element having a connecting portion on the wiring such that the connecting portion contacts the conductive fixing member precursor layer, and then heating the conductive fixing member precursor layer to form a conductive fixing member latter, thereby fixing the connecting portion of the element to the wiring, with the conductive fixing member layer therebetween, wherein the conductive fixing member precursor layer is composed of a solution-tape conductive material.

2009-01-15

20090014749

CHIP-TYPE LED AND METHOD OF MANUFACTURING THE SAME - An embodiment of the present invention has an insulating substrate in which a first concave hole for mounting an LED chip and a second concave hole for connecting a metallic small-gauge wire are formed, where a metallic sheet that serves as a first wiring pattern is formed at a portion that includes the first concave hole, a metallic sheet that serves as a second wiring pattern is formed at a portion that includes the second concave hole, an LED chip is mounted upon the metallic sheet inside the first concave hole, the LED chip is electrically connected to the metallic sheet inside the second concave hole via a metallic small-gauge wire, and the chip-type LED is sealed with a clear resin.

2009-01-15

20090014750

RESIN FOR OPTICAL SEMICONDUCTOR ELEMENT ENCAPSULATION CONTAINING POLYBOROSILOXANE - The present invention relates to a resin for optical semiconductor element encapsulation containing a polyborosiloxane obtained by reacting a silicon compound with a boron compound; and an optical semiconductor device containing the resin and an optical semiconductor element encapsulated with the resin. The resin for optical semiconductor element encapsulation according to the invention exhibits an excellent advantage that it is excellent in all of heat resistance, transparency, and light resistance.

2009-01-15

20090014751

III-Nitride Semiconductor Light Emitting Device and Method for Manufacturing the Same - Disclosed herein is a IE-nitride semiconductor light emitting device comprising a plurality of nitride semiconductor layers including a substrate and an active layer deposited on the substrate, in which the substrate is provided with protrusions to let the lights generated in the active layer emit out of the light emitting device and each of the protrusions has a first scattering plane and a second scattering plane, which are not parallel to each other.

POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A power semiconductor device of the present invention has an active region and an electric field reduction region and includes: an emitter region of a first conductivity type; a base region of a second conductivity type in contact with the emitter region; an electrical strength providing region of the first conductivity type in contact with the base region; a collector region of the second conductivity type in contact with the electrical strength providing region; and a collector electrode in contact with the collector region; wherein the collector region is disposed on both a active region and a electric field reduction region each containing a dopant of the second conductivity type, and the collector region disposed on the electric field reduction region includes a region having a lower density of carriers of the second conductivity type than the collector region disposed on the active region.

2009-01-15

20090014754

TRENCH TYPE INSULATED GATE MOS SEMICONDUCTOR DEVICE - A vertical and trench type insulated gate MOS semiconductor device includes a plurality of regions each being provided between adjacent ones of a plurality of the straight-line-like trenches arranged in parallel and forming a surface pattern of a plurality of straight lines. A plurality of first inter-trench surface regions are provided, each with an n

2009-01-15

20090014755

DIRECT BOND SUBSTRATE OF IMPROVED BONDED INTERFACE HEAT RESISTANCE - A direct bond substrate formed by bonding semiconductor substrates together, a semiconductor device using the direct bond substrate and a manufacturing method thereof are disclosed. A nitride film, oxynitride film, carbide film or an oxide film containing carbon is provided on the bonded interface of the semiconductor substrates in the direct bond substrate.

2009-01-15

20090014756

Method of producing large area SiC substrates - A method for growing a SiC-containing film on a Si substrate is disclosed. The SiC-containing film can be formed on a Si substrate by, for example, plasma sputtering, chemical vapor deposition, or atomic layer deposition. The thus-grown SiC-containing film provides an alternative to expensive SiC wafers for growing semiconductor crystals.

2009-01-15

20090014757

QUANTUM WIRE SENSOR AND METHODS OF FORMING AND USING SAME - A solid-state field-effect transistor device for detecting chemical and biological species and for detecting changes in radiation is disclosed. The device includes a quantum wire channel section to improve device sensitivity. The device is operated in a fully depleted mode such that a sensed biological, chemical or radiation change causes an exponential change in channel conductance of the transistor.

2009-01-15

20090014758

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In a semiconductor device, a SiN first protective insulating film is formed on a semiconductor layer. A T-shaped gate electrode is formed on the semiconductor layer. A SiN second protective insulating film spreads in an umbrella shape from above the T-shaped gate electrode. A hollow region is formed between the two SiN films. The SiN films are coated with a SiN third protective insulating film with the hollow region remaining.

2009-01-15

20090014759

SOLID STATE IMAGING APPARATUS AND METHOD FOR FABRICATING THE SAME - A semiconductor device of the present invention includes a substrate; an imaging region which is formed at part of the substrate and in which photoelectric conversion cells including photoelectric conversion sections are arranged in the form of an array; a control-circuit region which is formed at part of the substrate and in which the imaging region is controlled and a signal from the imaging region is outputted; and a copper-containing interconnect layer formed above the substrate and made of a material containing copper. Furthermore, a first anti-diffusion layer and a second anti-diffusion layer are formed, as anti-diffusion layers for preventing the copper from diffusing into each photoelectric conversion section, on the photoelectric conversion section and the copper-containing interconnect layer, respectively.

2009-01-15

20090014760

CMOS IMAGE SENSOR AND METHOD OF MANUFACTURE - A CMOS image sensor that is capable of substantially completely intercepting unnecessary light incident from the outside and preventing the occurrence of a hot pixel phenomenon and a method of fabricating the same are disclosed. A CMOS image sensor includes an epitaxial layer having a plurality of photodiodes. The epitaxial layer may be formed over a main pixel region and a dummy pixel region, which may be defined on a semiconductor substrate. A device passivation layer may be formed by depositing and planarizing oxide over the epitaxial layer. A silicon oxide layer may be formed by depositing and planarizing silicon oxide over the device passivation layer. The silicon oxide layer may have a concavo-convex type oxide pattern over the main pixel region and a planar oxide pattern over the dummy pixel region. A plurality of dark matrix elements may be formed by sequentially stacking a dual layer and a metal layer over the silicon oxide layer. A planarization process may be performed until the concavo-convex type oxide pattern is exposed. Micro lenses may be formed such that the micro lenses are aligned with photodiodes which will be formed at the main pixel region and the dummy pixel region.

2009-01-15

20090014761

IMAGE SENSOR PIXEL AND FABRICATION METHOD THEREOF - Provided is an image sensor pixel in which a specific or entire area of a field oxide layer inside the pixel can be used as a photodiode so as to increase a fill factor, and a fabrication method thereof. The image sensor pixel includes: a photodiode which is buried inside a semiconductor substrate; and pixel transistors which are formed after the photodiode is formed. In addition, the image sensor pixel includes: pixel transistors; a field oxide layer which separates the pixel transistors; and a photodiode which is located at the lower portion in a specific or entire area of the field oxide layer. In addition, the fabrication method includes: (a) forming a trench region in a specific area of a semiconductor substrate; (b) forming a photodiode which includes at least a portion of the trench region; and (c) forming pixel transistor, after the photodiode is formed. Accordingly, a surface area of a photodiode increases, thereby improving a fill factor and photosensitivity. In addition, in a unit pixel of an image sensor, the entire pixel area becomes a photodiode region except for a region where transistors are formed, thereby maximizing the fill factor.

2009-01-15

20090014762

BACK-ILLUMINATED TYPE SOLID-STATE IMAGE PICKUP DEVICE AND CAMERA MODULE USING THE SAME - The present invention provides a solid-state image pickup device including an image pickup pixel section which is provided on a semiconductor substrate and in which a plurality of pixels each having a photoelectric conversion element and a field-effect transistor are arranged, and a peripheral circuit section for the image pickup pixel section. An interconnect layer driving the field-effect transistor in the image pickup pixel section is formed on a first surface side of the semiconductor substrate. A light receiving surface of the photoelectric conversion element is located on a second surface side of the semiconductor substrate. The solid-state image pickup device includes a first terminal exposed from the second surface side of the semiconductor substrate, and a second terminal electrically connected to the first terminal and connectable to an external device on the first surface side of the semiconductor substrate.

2009-01-15

20090014763

CMOS image sensor with photo-detector protecting layers - An image sensor includes a logic region and an APS region having a first gate electrode, a photo-detector, a first protecting layer, first spacers, and a second protecting layer. The first gate electrode is formed over a semiconductor substrate. The photo-detector is formed to a side of the first gate electrode within the semiconductor substrate. The first protecting layer is formed over the first gate electrode and the photo-detector. The first spacers are formed over the first protecting layer to the sides of the first gate electrode. The second protecting layer is formed over the first protecting layer and the spacers. The first and second protecting layers are for preventing a contaminant from reaching the photo-detector.

2009-01-15

20090014764

IMAGE SENSOR WITH AN IMPROVED SENSITIVITY - An embodiment of an image sensor comprising photosensitive cells, each photosensitive cell comprising at least one charge storage means formed at least partly in a substrate of a semiconductor material. The substrate comprises, for at least one first photosensitive cell, a portion of a first silicon and germanium alloy having a first germanium concentration, possibly zero, and for at least one second photosensitive cell, a portion of a second silicon and germanium alloy having a second germanium concentration, non-zero, greater than the first germanium concentration.

2009-01-15

20090014765

High voltage operating field effect transistor, bias circuit therefor and high voltage circuit thereof - A high voltage operating field effect transistor has a source region and a drain region spaced apart from each other in a surface of a substrate. The source region is operative to receive at least one of a signal electric potential and a signal current. A semiconductor channel formation region is disposed in the surface of the substrate between the source region and the drain region. A gate region is disposed above the channel formation region and is operative to receive a bias electric potential having an absolute value equal to or larger than a first constant electric potential which changes according to an increase or decrease in a drain electric potential. A gate insulating film region is disposed between the channel formation region and the gate region.

2009-01-15

20090014766

NON-VOLATILE MEMORY DEVICE AND FABRICATION METHOD THEREOF - In one embodiment, a non-volatile memory device includes an isolation film defining an active region in a semiconductor substrate; a tunnel insulating film located on the active region; a control gate located on the isolation film; an inter-gate dielectric film parallel to the control gate and located between the control gate and the isolation film; an electrode overlapped by the control gate and the inter-gate dielectric film, wherein the electrode extends over the tunnel insulating film on the active region to form a floating gate; and a source region and a drain region formed in the active region on both sides of the floating gate.

DEEP TRENCH DEVICE WITH SINGLE SIDED CONNECTING STRUCTURE AND FABRICATION METHOD THEREOF - A deep trench device with a single sided connecting structure. The device comprises a substrate having a trench therein. A buried trench capacitor is disposed in a lower portion of the trench. An asymmetric collar insulator is disposed on an upper portion of the sidewall of the trench. A connecting structure is disposed in the upper portion of the trench, comprising an epitaxial silicon layer disposed on and adjacent to a relatively low portion of the asymmetric collar insulator and a connecting member disposed between the epitaxial silicon layer and a relatively high portion of the asymmetric collar insulator. A conductive layer is disposed between the relatively high and low portions of the asymmetric collar insulator, to electrically connect the buried trench capacitor and the connecting structure. A cap layer is disposed on the connecting structure. A fabrication method for a deep trench device is also disclosed.

SEMICONDUCTOR DEVICE - A technique that can realize high integration even for multilayered three-dimensional structures at low costs by improving the performance of the semiconductor device having recording or switching functions by employing a device structure that enables high precision controlling of the movement of ions in the solid electrolyte. The semiconductor element of the device is formed as follows; two or more layers are deposited with different components respectively between a pair of electrodes disposed separately in the vertical (z-axis) direction, then a pulse voltage is applied between those electrodes to form a conductive path. The resistance value of the path changes according to an information signal. Furthermore, a region is formed at a middle part of the conductive path. The region is used to accumulate a component that improves the conductivity of the path, thereby enabling the resistance value (rate) to response currently to the information signal. More preferably, an electrode should also be formed at least in either the x-axis or y-axis direction to apply a control voltage to the electrode.

2009-01-15

20090014771

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device including a semiconductor substrate; a plurality of memory cell transistors aligned in a predetermined direction on the semiconductor substrate, each memory cell transistor provided with a first gate electrode including a floating gate electrode comprising a polycrystalline silicon layer of a first thickness, a control gate electrode provided above the floating gate electrode, and an inter-gate insulating film between the floating and the control gate electrode; a pair of select gate transistors on the semiconductor substrate with a pair of second gate electrodes neighboring in alignment with the first gate electrode, each second gate electrode including a lower-layer gate electrode comprising the polycrystalline silicon layer of the first thickness, an upper-layer gate electrode provided above the lower-layer gate electrode; a polyplug of the first thickness situated between the second gate electrodes of the pair of select gate transistors; and a metal plug provided on the polyplug.

2009-01-15

20090014772

EEPROM MEMORY CELL WITH FIRST-DOPANT-TYPE CONTROL GATE TRANSISTOR, AND SECOND-DOPANT TYPE PROGRAM/ERASE AND ACCESS TRANSISTORS FORMED IN COMMON WELL - A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell.

2009-01-15

20090014773

TWO BIT MEMORY STRUCTURE AND METHOD OF MAKING THE SAME - A method for fabricating the memory structure includes: providing a substrate having a pad, forming an opening in the pad, forming a first spacer on a sidewall of the opening, filling the opening with a sacrificial layer, removing the first spacer and exposing a portion of the substrate, removing the exposed substrate to define a first trench and a second trench, removing the sacrificial layer to expose a surface of the substrate to function as a channel region, forming a first dielectric layer on a surface of the first trench, a surface of the second trench and a surface of the channel region, filling the first trench and the second trench with a first conductive layer, forming a second dielectric layer on a surface of the first conductive layer and the surface of the channel region, filling the opening with a second conductive layer, and removing the pad.

2009-01-15

20090014774

NONVOLATILE SEMICONDUCTOR MEMORY ELEMENT AND NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A memory element includes: a semiconductor region formed in a semiconductor substrate; source and drain regions formed at a distance from each other in the semiconductor region; a first insulating layer formed on the semiconductor region between the source and drain regions; a charge accumulating layer formed on the first insulating layer, and having a stacked structure including at least three conductor films and inter-conductor insulating films provided between the adjacent conductor films, a dielectric constant of any one of the inter-conductor insulating films located at a greater distance from the semiconductor substrate being higher than that of any one of the inter-conductor insulating films closer to the semiconductor substrate, a dielectric constant of each of the inter-conductor insulating films being lower than that of the first insulating layer; and a second insulating layer formed on the charge accumulating layer, and having a higher dielectric constant than that of any one of the inter-conductor insulating films.

MEMORY DEVICE, MEMORY AND METHOD FOR PROCESSING SUCH MEMORY - An integrated memory device, an integrated memory chip and a method for fabricating an integrated memory device is disclosed. One embodiment provides at least one integrated memory device with a drain, a source, a floating gate, a selection gate and a control gate, wherein the conductivity between the drain and the source can be controlled independently via the control gate.

2009-01-15

20090014777

Flash Memory Devices and Methods of Manufacturing the Same - Provided are flash memory devices. Embodiments of such devices may include a tunnel insulator formed on a substrate, a charge-storage layer formed on the tunnel insulator, a lower buffer layer formed on the charge-storage layer, a blocking layer formed on the lower buffer layer, and a first gate electrode formed on the blocking layer. Such devices may include second gate electrode formed on the first gate electrode, such that the lower buffer layer includes a silicon-free insulator, the blocking layer includes oxides or ternary lanthanum compounds, and

2009-01-15

20090014778

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile semiconductor memory device includes bit line diffusion layers extending along the X direction in an upper portion of a semiconductor substrate; and gate structures extending along the Y direction on the semiconductor substrate and each including a charge trapping film and a gate electrode. The nonvolatile semiconductor memory device further includes a first interlayer insulating film in which first contacts respectively connected to the bit line diffusion layers are formed; and second contacts that penetrate through a UV blocking film and a second interlayer insulating film formed on the first interlayer insulating film and have bottom faces respectively in contact with the first contacts and top faces respectively in contact with metal interconnections.

2009-01-15

20090014779

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A nonvolatile semiconductor memory device includes bit line diffusion layers extending along the X direction in an upper portion of a semiconductor substrate; and gate structures extending along the Y direction on the semiconductor substrate and each including a charge trapping film and a gate electrode. The nonvolatile semiconductor memory device further includes a first interlayer insulating film in which first contacts respectively connected to the bit line diffusion layers are formed; and second contacts that penetrate through a UV blocking film and a second interlayer insulating film formed on the first interlayer insulating film and have bottom faces respectively in contact with the first contacts and top faces respectively in contact with metal interconnections.

2009-01-15

20090014780

DISCRETE TRAP NON-VOLATILE MULTI-FUNCTIONAL MEMORY DEVICE - A multiple layer tunnel insulator is fabricated between a substrate and a discrete trap layer. The properties of the multiple layers determines the volatility of the memory device. The composition of each layer and/or the quantity of layers is adjusted to fabricate either a DRAM device, a non-volatile memory device, or both simultaneously.

2009-01-15

20090014781

Nonvolatile memory devices and methods for fabricating nonvolatile memory devices - A nonvolatile memory device may include: a tunnel insulating layer on a semiconductor substrate; a charge storage layer on the tunnel insulating layer; a blocking insulating layer on the charge storage layer; and a control gate electrode on the blocking insulating layer. The tunnel insulating layer may include a first tunnel insulating layer and a second tunnel insulating layer. The first tunnel insulating layer and the second tunnel insulating layer may be sequentially stacked on the semiconductor substrate. The second tunnel insulating layer may have a larger band gap than the first tunnel insulating layer. A method for fabricating a nonvolatile memory device may include: forming a tunnel insulating layer on a semiconductor substrate; forming a charge storage layer on the tunnel insulating layer; forming a blocking insulating layer on the charge storage layer; and forming a control gate electrode on the blocking insulating layer.

2009-01-15

20090014782

Semiconductor Device and Manufacturing Method of the Same - Disclosed is a semiconductor device. The semiconductor device includes a first gate formed in a trench of a semiconductor substrate, a first gate oxide layer on the semiconductor substrate including the first gate, a first epitaxial layer on the first gate oxide layer, first source and drain regions in the first epitaxial layer at sides of the first gate, an insulating layer on the first epitaxial layer, a second epitaxial layer on the insulating layer, a second gate oxide layer on the second epitaxial layer, a second gate on the second gate oxide layer, and second source and drain regions in the second epitaxial layer below sides of the second gate.

2009-01-15

20090014783

ULTRA-THIN BODY VERTICAL TUNNELING TRANSISTOR - A vertical tunneling, ultra-thin body transistor is formed on a substrate out of a vertical oxide pillar having active regions of opposing conductivity on opposite ends of the pillar. In one embodiment, the source region is a p+ region in the substrate under the pillar and the drain region is an n+ region at the top of the pillar. A gate structure is formed along the pillar sidewalls and over the body layers. The transistor operates by electron tunneling from the source valence band to the gate bias-induced n-type channels, along the ultra-thin silicon bodies, thus resulting in a drain current.

2009-01-15

20090014784

VERTICAL MOS TRANSISTOR AND METHOD THEREFOR - In one embodiment, a vertical MOS transistor is formed without a thick field oxide and particularly without a thick field oxide in the termination region of the transistor.

Field Effect Transistors Having Protruded Active Regions and Methods of Fabricating Such Transistors - Provided are a field effect transistor, a method of manufacturing the same, and an electronic device including the field effect transistor. The field effect transistor may have a structure in which a double gate field effect transistor and a recess channel array transistor are formed in a single transistor in order to improve a short channel effect which occurs as field effect transistors become more highly integrated, a method of manufacturing the same, and an electronic device including the field effect transistor. The field effect transistor can exhibit stable device characteristics even when more highly integrated in such a manner that both the length and width of a channel increase and particularly the channel can be significantly long, and can be manufactured simply.

2009-01-15

20090014787

Multi-Layer Semiconductor Structure and Manufacturing Method Thereof - A power MOSFET structure comprises at least one first gate in the cell area and at least one second gate at the peripheral that are both in a semiconductor substrate. The first and second gates are electrically connected, and the second gate is connected to a contact so as to electrically connect to a bond pad for transmitting gate control signals. The semiconductor substrate comprises a first semiconductor layer, a second semiconductor layer and a third semiconductor layer in downward sequence. The first and third semiconductor layers are of a first conductive type, e.g., n-type, and the second semiconductor layer is of a second conductive type, e.g., p-type. The first and third semiconductor layers serve as the source and the drain, respectively.

2009-01-15

20090014788

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A type semiconductor device includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; a plurality of gate electrodes which are formed in gate trenches via gate insulating films, the gate trenches being formed through the second semiconductor layer and the third semiconductor layer; a plurality of impurity regions of the second conductivity type which are formed at regions below bottoms of contact trenches, the contact trenches being formed at the third semiconductor layer in a thickness direction thereof between corresponding ones of the gate trenches and longitudinal cross sections of the contact trenches being shaped in ellipse, respectively; first electrodes which are formed so as to embed the contact trenches and contacted with the impurity regions, respectively; and a second electrode formed on a rear surface of the semiconductor substrate.

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device includes a gate electrode formed through an insulating film in a groove having a first side surface adjacent to a source region and a base region, and a second conductive type first impurity region formed adjacent to a second side surface of the groove between the groove and a lead-out portion of a drain region existing below the base region so as to extend downward beyond a lower end of the groove.

2009-01-15

20090014791

Lateral Power MOSFET With Integrated Schottky Diode - A semiconductor device includes a substrate. The substrate includes a semiconductor material. An electrically isolated region is formed over the substrate. A metal-oxide-semiconductor field-effect transistor (MOSFET) is formed over the substrate within the electrically isolated region. The electrically isolated region includes a trench formed around the electrically isolated region. An insulative material such as silicon dioxide (SiO2) may be deposited into the trench. A diode is formed over the substrate within the electrically isolated region. In one embodiment, the diode is a Schottky diode. A metal layer may be formed over a surface of the substrate to form an anode of the diode. A first electrical connection is formed between a source of the MOSFET and an anode of the diode. A second electrical connection is formed between a drain of the MOSFET and a cathode of the diode.

2009-01-15

20090014792

POWER SEMICONDUCTOR DEVICE - A power semiconductor device comprising an array of cells distributed over a surface of a substrate, the source regions of the individual cells of the array comprising a plurality of source region branches each extending laterally outwards towards at least one source region branch of an adjacent cell and presenting juxtaposed ends, the base regions of the individual cells of the array comprising a corresponding plurality of base region branches merging together adjacent and between the juxtaposed ends of the source region branches to form a single base region surrounding the source regions of the individual cells of the array in the substrate. The junctions between the merged base region and the drain region are solely concave laterally and define rounded current conduction path areas for the on-state of the device between adjacent cells that are depleted in the off-state of the device to block flow of current from the source regions to the drain electrode. Floating voltage regions of opposite conductivity type to the drain region are buried in the substrate beneath the merged base region and present features corresponding to and juxtaposed with features of the merged base region in each cell so that the voltage of the floating voltage regions tends to the voltage of the source regions when depletion layers blocking the current conduction paths reach the floating voltage regions, whereby to enhance the development of the depletion layers. The features of the floating voltage regions define rings of the opposite conductivity type to the drain region that surround the current conduction paths of respective cells. The floating voltage regions include respective islands situated within the current conduction paths.

2009-01-15

20090014793

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes: a semiconductor substrate; a pair of first diffusion layer regions provided near a top face of the semiconductor substrate; a channel region provided between the first diffusion layer regions of the semiconductor substrate; a gate insulation film provided on the channel region and on the semiconductor substrate such as to overlap with at least part of the first diffusion layer regions; a gate electrode provided on the insulation film; a pair of silicon selective growth layers provided on the semiconductor substrate at both sides of the gate electrode, each of the pair of silicon selective growth layers overlapping with at least part of the first diffusion layer regions, and being provided at a distance from the gate electrode; second diffusion layer regions provided in each of the silicon selective growth layers, peak positions of impurity concentration of the second diffusion layer regions being shallower than bottoms of the silicon selective growth layers; and third diffusion layer regions provided near side faces of the silicon selective growth layers, and electrically connecting the first diffusion layer regions to the second diffusion layer regions.

2009-01-15

20090014794

MOSFET WITH LATERALLY GRADED CHANNEL REGION AND METHOD FOR MANUFACTURING SAME - The present invention relates generally to a semiconductor device having a channel region comprising a semiconductor alloy of a first semiconductor material and a second, different material, and wherein atomic distribution of the second material in the channel region is graded along a direction that is substantially parallel to a substrate surface in which the semiconductor device is located. Specifically, the semiconductor device comprises a field effect transistor (FET) that has a SiGe channel with a laterally graded germanium content.

2009-01-15

20090014795

Substrate for field effect transistor, field effect transistor and method for production thereof - A π gate FinFET structure having reduced variations in off-current and parasitic capacitance and a method for production thereof are provided. The structure of an element is improved so that an off-current suppressing capability can be exhibited more strongly. A field effect transistor, wherein a first insulating film and a semiconductor region are provided so as to protrude upward with respect to the flat surface of a base, the field effect transistor has a gate electrode, a gate insulating film and a source/drain region, and a channel is formed at least on the side surface of the semiconductor region, wherein that the first insulating film is provided on an etch stopper layer composed of a material having an etching rate lower than at least the lowermost layer of the first insulating film for etching under a predetermined condition.

2009-01-15

20090014796

Semiconductor Device with Improved Contact Structure and Method of Forming Same - A contact structure includes a first contact formed in a first dielectric layer connecting to the source/drain region of a MOS transistor, and a second contact formed in a second dielectric layer connecting to a gate region of a MOS transistor or to a first contact. A butted contact structure abutting a source/drain region and a gate electrode includes a first contact formed in a first dielectric layer connecting to the source/drain region of a MOS transistor, and a second contact formed in a second dielectric layer with one end resting on the gate electrode and the other end in contact with the first contact.

FINFET SRAM WITH ASYMMETRIC GATE AND METHOD OF MANUFACTURE THEREOF - A FinFET SRAM transistor device includes transistors formed on fins with each transistor including a semiconductor channel region within a fin plus a source region and a drain region extending within the fin from opposite sides of the channel region with fin sidewalls having a gate dielectric formed thereon. Bilateral transistor gates extend from the gate dielectric. An asymmetrically doped FinFET transistor has source/drain regions doped with a first dopant type, but the asymmetrically doped FinFET transistor include at least one of the bilateral transistor gate electrode regions on one side of at least one of the fins counterdoped with respect to the first dopant type. The finFET transistors are connected in a six transistor SRAM circuit including two PFET pull-up transistors, two NFET pull down transistors and two NFET passgate transistors.

2009-01-15

20090014799

Semiconductor device and method for manufacturing the same - A semiconductor device and a method for manufacturing a semiconductor device are provided. A semiconductor device comprises a first single-crystal semiconductor layer including a first channel formation region and a first impurity region over a substrate having an insulating surface, a first gate insulating layer over the first single-crystal semiconductor layer, a gate electrode over the first gate insulating layer, a first interlayer insulating layer over the first gate insulating layer, a second gate insulating layer over the gate electrode and the first interlayer insulating layer, and a second single-crystal semiconductor layer including a second channel formation region and a second impurity region over the second gate insulating layer. The first channel formation region, the gate electrode, and the second channel formation region are overlapped with each other.

2009-01-15

20090014800

SILICON CONTROLLED RECTIFIER DEVICE FOR ELECTROSTATIC DISCHARGE PROTECTION - An SCR device includes a substrate, a plurality of isolation structures defining a first region and a second region in the substrate, an n well disposed in the substrate, an n type first doped region disposed in the first region in the substrate, a p type second doped region disposed in the second region in the substrate, and a p type third doped region (PESD implant region) disposed underneath the first doped region in the first region in the substrate. The well is disposed underneath the first region and the second region, and the third doped region isolates the first doped region from the well.

NANOELECTROMECHANICAL TRANSISTORS AND METHODS OF FORMING SAME - Nanoelectromechanical transistors (NEMTs) and methods of forming the same are disclosed. In one embodiment, an NEMT may include a substrate including a gate adjacent thereto, a source region and a drain region; an electromechanically deflectable nanotube member; and a channel member electrically insulatively coupled to the nanotube member so as to be aligned with the source region and the drain region, wherein electromechanical deflection of the nanotube member is controllable, in response to an electrical potential applied to the gate and the nanotube member, between an off state and an on state, the on state placing the channel member in electrical connection with the source region and the drain region to form a current path.

2009-01-15

20090014804

MISFET, SEMICONDUCTOR DEVICE HAVING THE MISFET AND METHOD OF MANUFACTURING THE SAME - To solve the problem, a MISFET covered with an insulating film which generates stress is provided. The MISFET including a gate insulating film; a gate electrode disposed on the gate insulating film, the gate electrode including a polysilicon portion and a silicide portion; and a source/drain disposed adjacent to the gate electrode, in which the ratio between the polysilicon portion and the silicide portion is determined depending on a strain for enhancing the driving capability of the MISFET, the strain being generated on the basis of the stress through the gate electrode in a channel region of the MISFET.

2009-01-15

20090014805

METHOD TO IMPROVE PERFORMANCE OF SECONDARY ACTIVE COMPONENTS IN AN ESIGE CMOS TECHNOLOGY - According to various embodiments, there are eSiGe CMOS devices and methods of making them. The method of making a substrate for a CMOS device can include providing a DSB silicon substrate including a first bonded to a second layer, wherein each layer has a (100) oriented surface and a first direction and a second direction and the first direction of the first layer is approximately aligned with the second direction of the second layer. The method can also include performing amorphization on a selected region of the first layer to form a localized amorphous silicon region and recrystallizing the localized amorphous silicon region across the interface using the second layer as a template, such that the first direction of the first layer in the selected region is approximately aligned with the first direction of the second layer.

2009-01-15

20090014806

Semiconductor Device and Method for Manufacturing the Same - A semiconductor device and method of manufacturing thereof. The semiconductor device has at least one NMOS device and at least one PMOS device provided on a substrate. An electron channel of the NMOS device is aligned with a first direction. A hole channel of the PMOS device is aligned with a different second direction that forms an acute angle with respect to the first direction.

2009-01-15

20090014807

DUAL STRESS LINERS FOR INTEGRATED CIRCUITS - Dual stress liners for CMOS applications are provided. The dual stress liners can be formed from silicon nitride having a first portion for inducing a first stress and a second portion for inducing a second stress. An interface between the first and second stress portions is self-aligned and co-planar. To produce a co-planar self-aligned interface, polishing, for example, mechanical chemical polishing is used.

Semiconductor device and method for manufacturing the same - A semiconductor device includes a semiconductor substrate, and a p-channel MOS transistor provided on the semiconductor substrate, the p-channel MOS transistor comprising a first gate dielectric film including Hf, a second gate dielectric film provided on the first gate dielectric film and including aluminum oxide, and a first metal silicide gate electrode provided on the second gate dielectric film.

2009-01-15

20090014810

METHOD FOR FABRICATING SHALLOW TRENCH ISOLATION AND METHOD FOR FABRICATING TRANSISTOR - A method of forming a shallow trench isolation includes sequentially forming a pad oxide layer and a pad nitride layer over a semiconductor substrate. A portion of the pad nitride layer is etched and patterned. The patterned pad nitride layer is used as a etching mask to etch the pad oxide layer and the semiconductor substrate, thus forming a trench. An oxide layer is formed over the surface of the trench by an oxidation process. A barrier liner layer is formed over the oxide layer to create a tensile stress in a vertical direction to the semiconductor substrate. The trench is filled with insulation material and then planarized to expose a top face of the patterned pad nitride layer. A shallow trench isolation structure is completed by removing the patterned pad nitride layer and pad oxide layer. The process prevents a divot effect cased on an edge area of shallow trench isolation structure.

2009-01-15

20090014811

Dynamic Array Architecture - A semiconductor device includes a substrate portion and a number of diffusion regions defined within the substrate portion. The diffusion regions are separated from each other by a non-active region of the substrate portion. The semiconductor device includes a number of linear gate electrode segments defined to extend over the substrate portion in a single common direction. In one embodiment, the diffusion regions are defined in a non-symmetrical manner relative to a centerline of the substrate portion. In another embodiment, the substrate portion corresponds to a region of the semiconductor device in which first and second cells are defined, and respectively include diffusion shapes of different size. In another embodiment, one or more of the diffusion regions is defined to have a periphery formed by more than four orthogonally related sides.

2009-01-15

20090014812

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - Disclosed herein is a semiconductor device, including: a first group of transistors formed on a semiconductor substrate; and a second group of transistors formed on the semiconductor substrate, each of which is lower in operating voltage than each of the transistors in the first group; wherein each of the transistors in the first group includes a first gate electrode formed on the semiconductor substrate through a first gate insulating film, and a silicide layer formed on the first gate electrode; each of the transistors in the second group includes a second gate electrode formed in a trench for gate formation, formed in an insulating film above the semiconductor substrate, through a second gate insulating film; and a protective film is formed so as to cover the silicide layer on each of the first gate electrodes of the first group of transistors.

2009-01-15

20090014813

Metal Gates of PMOS Devices Having High Work Functions - A semiconductor structure includes a refractory metal silicide layer; a silicon-rich refractory metal silicide layer on the refractory metal silicide layer; and a metal-rich refractory metal silicide layer on the silicon-rich refractory metal silicide layer. The refractory metal silicide layer, the silicon-rich refractory metal silicide layer and the metal-rich refractory metal silicide layer include same refractory metals. The semiconductor structure forms a portion of a gate electrode of a metal-oxide-semiconductor device.

High voltage device and method for fabricating the same - A high voltage device includes drift regions formed in a substrate, an isolation layer formed in the substrate to isolate neighboring drift regions, wherein the isolation layer has a depth greater than that of the drift region, a gate electrode formed over the substrate, and source and drain regions formed in the drift regions on both sides of the gate electrode.

2009-01-15

20090014816

High voltage operating field effect transistor, and bias circuit therefor and high voltage circuit thereof - A high voltage operating field effect transistor has a substrate and a semiconductor channel formation region disposed in a surface of the substrate. A source region and a drain region are spaced apart from each other with the semiconductor channel formation region disposed between the source region and the drain region. A gate insulating film region is disposed on the semiconductor channel formation region. A resistive gate region is disposed on the gate insulating film region. A source side electrode is disposed on a source region side of the resistive gate region and is operative to receive a signal electric potential. A drain side electrode is disposed on a drain region side of the resistive gate region and is operative to receive a bias electric potential an absolute value of which is equal to or larger than that of a specified electric potential and which changes according to an increase or decrease in a drain electric potential.

2009-01-15

20090014817

INSULATING FILM AND ELECTRONIC DEVICE - An electronic device including a semiconductor layer having silicon as a major component; and a dielectric film epitaxially grown directly on a major surface of the semiconductor layer, wherein the dielectric film consists of a dielectric material having a Ruddlesden-Popper type structure, the Ruddlesden-Popper type structure is expressed by a chemical formula A

2009-01-15

20090014818

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, a first insulating film formed on a side surface of the gate electrode, a second insulating film covering a surface of the first insulating film and formed of a material different from a material of the first insulating film, and a third insulating film covering the semiconductor substrate, the gate electrode and the second insulating film and formed of a material different from the material of the second insulating film.

2009-01-15

20090014819

Micromechanical Component, Method for Fabrication and Use - A micromechanical component that can be produced in an integrated thin-film method is disclosed, which component can be produced and patterned on the surface of a substrate as multilayer construction. At least two metal layers that are separated from the substrate and with respect to one another by interlayers are provided for the multilayer construction. Electrically conductive connecting structures provide for an electrical contact of the metal layers among one another and with a circuit arrangement arranged in the substrate. The freely vibrating membrane that can be used for an inertia sensor, a microphone or an electrostatic switch can be provided with matching and passivation layers on all surfaces in order to improve its mechanical properties, said layers being concomitantly deposited and patterned during the layer producing process or during the construction of the multilayer construction. Titanium nitride layers are advantageously used for this.

2009-01-15

20090014820

Semiconductor mechanical sensor - A semiconductor mechanical sensor having a new structure in which a S/N ratio is improved. In the central portion of a silicon substrate

2009-01-15

20090014821

Method for producing conductor structures and applications thereof - This publication discloses a method for forming electrically conducting structures on a substrate. According to the method nanoparticles containing conducting or semiconducting material are applied on the substrate in a dense formation and a voltage is applied over the nanoparticles so as to at least locally increase the conductivity of the formation. According to the invention, the voltage is high enough to cause melting of the nanoparticles in a breakthrough-like manner. With the aid of the invention, small-linewidth structures can be created without high-precision lithography.

2009-01-15

20090014822

MICROELECTRONIC IMAGERS AND METHODS FOR MANUFACTURING SUCH MICROELECTRONIC IMAGERS - Microelectronic imagers and methods of manufacturing such microelectronic imagers are disclosed. In one embodiment, a method for manufacturing a microelectronic imager can include irradiating selected portions of an imager housing unit. The housing unit includes a body having lead-in surfaces and a support surface that define a recess sized to receive a microelectronic die. The method also includes depositing a conductive material onto the irradiated portions of the housing unit and forming electrically conductive traces. The method further includes coupling a plurality of terminals at a front side of a microelectronic die to corresponding electrically conductive traces in the recess in a flip-chip configuration. The microelectronic die includes an image sensor aligned with at least a portion of an optical element carried by the housing unit and at least partially aligned with the recess. The method can then include depositing an encapsulant into the recess and over at least a portion of the microelectronic die.

2009-01-15

20090014823

SOLID STATE IMAGING DEVICE IN WHICH A PLURALITY OF IMAGING PIXELS ARE ARRANGED TWO-DIMENSIONALLY, AND A MANUFACTURING METHOD FOR THE SOLID STATE IMAGING DEVICE - A solid state imaging device includes a plurality of imaging pixels that are arranged two-dimensionally along a main face of a semiconductor substrate. Each imaging pixel in the solid state imaging device includes a photodiode that performs photoelectric conversion and a color filter that is disposed higher in the Z axis direction than the photodiode. Also, light blocking portions have been formed between pairs of adjacent imaging pixels, on the main face of the semiconductor substrate to a height in a thickness direction (Z axis direction) of the semiconductor substrate that is substantially equal to or higher than top edges of the optical filters. Each light blocking portion is constituted from a combination of a light blocking film and a light blocking wall.

2009-01-15

20090014824

SOLID-STATE IMAGING DEVICE, METHOD FOR MANUFACTURING THE SAME, AND CAMERA HAVING THE DEVICE - Provided is a solid-state imaging device that realizes sensitivity improvement while maintaining flare prevention effect even when miniaturization of cell is advanced. The solid-state imaging device according to the present invention includes: light receiving units formed on a semiconductor substrate; an antireflection film arranged above the semiconductor substrate, except above the light receiving units; and microlenses arranged above the light receiving units, in which the antireflection film is formed at a position equal to or higher than a position of the microlenses.

2009-01-15

20090014825

Flexible photo-detectors - Apparatus including flexible line extending along a length. Flexible line includes first charge carrier-transporting body, photosensitive body over first charge carrier-transporting body, and second charge carrier-transporting body over photosensitive body. Each of first and second charge carrier-transporting bodies and photosensitive body extend along at least part of length of flexible line. Photosensitive body is capable of near-infrared or visible light-induced generation of charge carrier pairs. Second charge carrier-transporting body is at least semi-transparent to near-infrared light or visible light.

2009-01-15

20090014826

Image sensor package and fabrication method thereof - An image sensor package and a method for fabricating thereof are provided. A substrate having an insulator filled cavity is provided with an image sensor device electrical connected to a metal layer, thereon. A covering plate is then disposed on the substrate. The substrate is subsequently thinned to expose the insulator. Removing a portion of the insulator, a hole is formed and a conductive layer is filled therein to form a via hole. Next, a solder ball is located over a backside of the substrate which is electrically connected to the metal layer through the via hole. The image sensor package is thinned, thus, the dimensions thereof are reduced.

SEMICONDUCTOR MEMORY DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR MEMORY DEVICE - In a method of manufacturing a semiconductor memory device, an opening is made in a part of an insulating film formed on a silicon substrate. An amorphous silicon thin film is formed on the insulating film in which the opening has been made and inside the opening. Then, a monocrystal is solid-phase-grown in the amorphous silicon thin film, with the opening as a seed, thereby forming a monocrystalline silicon layer. Then, the monocrystalline silicon layer is heat-treated in an oxidizing atmosphere, thereby thinning the monocrystalline silicon layer and reducing the defect density. Then, a memory cell array is formed on the monocrystalline silicon layer which has been thinned and whose defect density has been reduced.

2009-01-15

20090014829

Semiconductor fuse box and method for fabricating the same - A semiconductor fuse box includes a fuse structure and a protective structure disposed between the fuse structure and an integrated circuit structure. The protective structure has at least one irregular side surface. The protective structure (which may also include a pad formed there-under) extends beyond a bottom of the fuse structure. Such an irregular side surface and such an extension of the protective structure minimize propagation of damaging energy to the adjacent integrated circuit structure when a laser beam is directed to the fuse structure.

2009-01-15

20090014830

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including at least one of the following steps: Forming an insulating film having at least one trench on and/or over a semiconductor substrate. Forming a metal film on and/or over a surface of an insulating film, including inside the trench. Forming a metal seed layer on and/or over the metal film inside the trench. Forming a metal plating layer on and/or over the metal seed layer to fill the trench.

2009-01-15

20090014831

Electronic device comprising an integrated circuit and a capacitance element - An electronic device (ICD) comprises an integrated circuit (AIC) and a capacitance element (PIC). The integrated circuit (AIC) is provided with a plurality of circuit contact pairs (CI). The capacitance element (PIC) is provided with a plurality of capacitance contact pairs (CC). A capacitance is present between each of at least part of the capacitance contact pairs (CC). The plurality of capacitance contact pairs (CC) faces the plurality of circuit contact pairs (CI). At least a part of the capacitance contact pairs (CC) is electrically coupled in a pair-by-pair manner to at least a part of the circuit contact pairs (CI).

2009-01-15

20090014832

Semiconductor Device with Reduced Capacitance Tolerance Value - A semiconductor device includes a capacitance, the numerical value of which is relevant for a device function. The capacitance is formed from a parallel connection of at least a first and a second capacitor element, wherein the first and second capacitor elements are formed in respective manufacturing steps that exhibit uncorrelated process fluctuations.

2009-01-15

20090014833

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - An exemplary semiconductor device includes a semiconductor substrate on which lower electrodes are formed. The lower electrodes are arranged in an array including a rows extending substantially parallel to one another along a first direction. A stripe-shaped capacitor support pad is interposed between a pair of adjacent ones of the rows and is connected to lower electrodes in the pair of adjacent ones of the rows. The semiconductor device may include plurality of capacitors each including a one of the lower electrodes, a dielectric film, and an upper electrode. An upper end of the capacitor support pad is below the upper ends of the lower electrodes. A portion of the stripe-shaped capacitor support pad is interposed between adjacent ones of lower electrodes included within at least one of the rows and is connected to the adjacent ones of lower electrodes included within the at least one of the rows.

2009-01-15

20090014834

Contact plug structure - A contact plug structure for a checkerboard dynamic random access memory comprises a body portion, two leg portions connected to the body portion and a dielectric block positioned between the two leg portions. Each leg portion is electrically connected to a deep trench capacitor arranged in an S-shape manner with respect to the contact plug structure via a doped region isolated by a shallow trench isolation structure. Preferably, the body portion and the two leg portions can be made of the same conductive material selected from the group consisting of polysilicon, doped polysilicon, tungsten, copper and aluminum, while the dielectric block can be made of material selected from the group consisting of borophosphosilicate glass. Particularly, the contact plug can be prepared by dual-damascene technique. Since the overlapped area between the contact plug structure and a word line can be dramatically decreased, the bit line coupling (BLC) can be effectively reduced.

2009-01-15

20090014835

Semiconductor device including MIM element and method of manufacturing the same - A semiconductor device includes a first wiring layer which is provided above a semiconductor substrate and includes a first insulating film and a wiring buried in the first insulating film, a second insulating film provided above the first wiring layer, a third insulating film provided on the second insulating film, and a capacitor element provided on the third insulating film. The wiring includes an upper surface having a protruding portion. The capacitor element includes a lower electrode provided on the third insulating film, a capacitor insulating film provided on the lower electrode, and an upper electrode provided on the capacitor insulating film.

2009-01-15

20090014836

Memory Array with a Selector Connected to Multiple Resistive Cells - An array includes a transistor comprising a first terminal, a second terminal and a third terminal; a first contact plug connected to the first terminal of the transistor; a second contact plug connected to the first terminal of the transistor; a first resistive memory cell having a first end and a second end, wherein the first end is connected to the first contact plug; and a second resistive memory cell having a third end and a fourth end, wherein the third end is connected to the second contact plug.

2009-01-15

20090014837

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a semiconductor device and a method of manufacturing the same. A high-resistance silicon wafer is manufactured in such a manner that a large-sized silicon wafer manufactured by the Czochralski method is irradiated with neutrons, and high-resistance and low-resistance elements are simultaneously formed on the high-resistance silicon wafer. Thus, the manufacturing cost can be remarkably saved, and the reliability of products can be enhanced.

2009-01-15

20090014838

SEMICONDUCTOR DEVICE - The invention is based upon a semiconductor device where a high voltage bipolar transistor is manufactured on the same wafer with a high-speed bipolar transistor, and has a characteristic that the high-speed bipolar transistor and the high voltage bipolar transistor are formed on each epitaxial collector layer having the same thickness and are provided with a buried collector region formed in the same process and having the same impurity profile, the buried collector region exists immediately under a base of the high-speed bipolar transistor, no buried collector region and no SIC region exist immediately under a base of the high voltage bipolar transistor and distance between a base region and a collector plug region of the high voltage bipolar transistor is equal to or is longer than the similar distance of the high-speed bipolar transistor.

Method for the production of crystalline silicon foils - The invention is a method for the production of a silicon foil with a targeted charge carrier transport to the p-n transition by means of an integral electric field (‘drift field’). By varying the crystal growth speed and introducing a doping substance into the fluid silicon beforehand, a crystallization process can be carried out in such a way that a gradient over the foil thickness is produced in the doping profile in the silicon. This gradient of the doping profile gives rise to an electric field. With the aid of various foil casting techniques foils that are suitable for the production of solar cells can thus be produced in a relatively simple manner.