Abstract

This work presents the implementation of a tightly-coupled hardware architectural enhancement to the Altera FPGA-based Nios II embedded processor. The goal is to accelerate finite field arithmetic operations in the binary fields of F2163 and F2193, for application in a high-performance embedded system implementing elliptic curve cryptography (ECC). The concept is to augment the embedded processor with a few custom instructions for fast finite field arithmetic operations. Instead of a coprocessor, hardware acceleration of the arithmetic operation is provided by custom logic tightly coupled to the processor core and directly controlled by the instruction stream. This concept, which may be considered as a hardware-software co-design approach, is evaluated by prototyping an elliptic curve cryptosystem (ECC) on an Altera Stratix FPGA development board. Experimental results shows that for the point multiplication operation, which is the core operation in an ECC computation, the implementation with custom instructions and tightly-coupled hardware is about 50% faster than the coprocessor-based hardware.