Want a terabyte iPad? Then you’ll want to read this

In the latter half of the 19th century, the introduction of elevators and steel trusses enabled us to put up taller buildings with denser cores. It changed urban landscapes forever–packing more people into small spaces. Now, chips are set to benefit from a similar design leap.

Applied Materials on Wednesday introduced a new machine that could help meet our demand for cheap, small Flash memory by reconceptualizing how chips are built. The machine will enable chipmakers to build memory chips that are constructed upwards like a multi-story building as opposed to on a flat surface. They new chips would also be a significant advancement over the 3-D transistors that Intel (s intc) is building today.

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Applied Materials (s amat) expects the chips to be in devices the end of 2014 at the earliest — evolutions in chips take a long, long time to get to the end user. But the promise of this machine, and the subsequent ability of those that use it to build chips, is that they will be able to stack many layers of multi-cell flash memory on one chip. That’s one way to keep pushing chip architecture down the cost curve enabled by Moore’s Law.

And that means it may be possible to build terabyte or petabyte memory that can fit into a mobile phone or tablet without resorting to expensive and exotic alternatives. So today’s 64GB iPad may soon get higher-end cousins that can store even more memories and games on the tablet — if we don’t all run to the cloud with our content first.

I thought we already had 3-D chips

The chips that Applied envisions for its customers (folks that run big chip manufacturing plants such as Samsung, TSMC and even Intel) will have several layers of multicell memory on a chip — the resulting structure actually looks more like a pyramid because the stair-step design is the easiest way for the elements on the chip to connect in order to communicate between cells.

Other 3-D chips such as the Intel tri-gate transistors or even the alternative designs put forth by IBM and others, are kind of 3-D, but not fully. In their case, the transistors are layered on top of the chip and then that layer is pushed up like a wrinkle in fabric giving the transistors more surface area. But in the Applied model (which has backers at Samsung and Toshiba) the transistors are actually stacked in layers on a chip. The difference in significant in terms of how much memory you can cram onto the chip.

The Applied model is also different from other innovations in memory technology where the chips themselves are stacked, like the announcement from Intel and Micron last December on their new stacks that will enable 128 GB of storage on devices.

The road goes on forever but the cost efficiencies end.

The problem with many of these other methods is they can add more memory, but at a greater costs. In some cases, the amount of technology can lead to more manufacturing defects or chips that consume too much power or space. Applied (and some of its customers) believe that the only way to go to keep adding density without overwhelming costs (or making giant chips) is to build up.

And thus, the idea of these skyscraper chips, which Brad Howard, head of advanced technology, etch business unit with Applied, says are coming. He noted that right now an undisclosed number of its customers are testing the new Centura Avatar machine in pilot lines in their chip plants and thinks that roughly around the time when we try to jam a terabyte of memory into a cell-phone-sized package, it will become more cost effective to build up in layers as opposed to stacking chips or adding wrinkles to our flash chips. If he’s right, then the skyscraper era will begin.

It is indeed a yield matter. That said, TCO will only be competitive if the etch tool is able to process more than one ‘device equivalent’ layer in a single step, otherwise you would just linearly multiply the TCO by the number of stacked layer of device (except wafer cost)…