Get Started with HDL
Verifier

Test and verify Verilog and VHDL using HDL simulators and FPGA boards

HDL
Verifier™ lets you test and verify Verilog® and VHDL® designs for FPGAs, ASICs, and SoCs. You can verify RTL against test benches
running in MATLAB® or Simulink® using cosimulation with an HDL simulator. These same test benches can be used
with FPGA and SoC development boards to verify HDL implementations in hardware.

HDL
Verifier provides tools for debugging and testing FPGA implementations on Xilinx® and Intel® boards. You can use MATLAB to write to and read from memory-mapped registers for testing designs on
hardware. You can insert probes into designs and set trigger conditions to upload internal
signals into MATLAB for visualization and analysis.

HDL
Verifier generates verification models for use in RTL test benches, including Universal
Verification Methodology (UVM) test benches. These models run natively in simulators that
support the SystemVerilog Direct Programming Interface (DPI).

Design Verification Automation

The HDL
Verifier software consists of MATLAB functions,
a MATLAB System
object™, and a library of Simulink blocks,
all of which establish communication links between the HDL simulator
and MATLAB or Simulink.

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