ERM – The Crucial Questions

At the tenth anniversary of the international technology roadmap for semiconductors (ITRS), a new chapter declares that emerging research materials (ERM) could provide solutions to future technological challenges. Michael Garner answers the crucial questions on ERM.

Global Semiconductor Forum: Can the industry keep Moore’s Law through the 2012-2015 ITRS ‘brick wall’?

Michael Garner: Our industry believes we can continue Moore’s Law well beyond this point. The goal of the ITRS is to identify future issues and encourage researchers, suppliers and our industry to identify solutions. Because of this the ERM chapter was added to the 2007 ITRS roadmap to identify materials in research with the potential for solving specific ‘brick wall’ issues.

GSF: What are emerging research materials (ERM)?

MG: ERM include low dimensional materials, such as carbon nanotubes, nanowires, nanoparticles, III-V compounds, graphene, macromolecules, self assembling materials, complex metal oxides and spin materials. The challenge for all these includes interface and integration for potential applications and metrology and modelling necessary in accelerating progress.

GSF: What ERM have the potential to extend CMOS to extreme limits of scaling and what challenges does that pose?

MG: There is a lot of interest in III-V compounds, carbon nanotubes, semiconductor nanowires and graphene and graphitic carbon as potentially extreme CMOS technologies. The ability to control properties and deposit them in controlled locations and directions is required and is very challenging. Other issues include the control of doping, formation of low resistance contacts and integration with other materials, which is also very difficult.

GSF: What ERM have the potential to extend lithography and what are the challenges involved?

MG: Novel macromolecules could enable resist with the ability to print smaller features and reduced line-edge roughness. Combined lithography with self assembled materials has the potential for generating features at higher density than the
lithography with reduced line edge roughness. Macromolecules are needed to improve imprint technology. Each of these has promise but have significant challenges to be viable solutions. These are highlighted in the ERM chapter.

GSF: Are there any materials that could extend interconnect scaling?

MG: Potential materials to extend interconnects include low dimensional materials such as CNTs as vias or interconnects or novel nanowires. Macromolecules could enable new ultra low-K inter-level dielectrics.

GSF: How difficult is it to integrate a new material into IC technology?

MG: The integration is extremely difficult and has often required over ten to 15 years from identification and research to implementation. Integration of a new material often requires new processes, these must be compatible with other materials on the wafer. The formation of ‘reliable’ interfaces is also challenging, requiring significant effort.

GSF: What are the options to continue scaling beyond CMOS?

MG: The ITRS (ERD) chapter identifies a number of alternate-state memory and logic technologies, based on alternate ‘state’ operation. Examples include ferroelectric FET memories, fuse-anti-fuse memories, molecular state, spin state and others. The emerging research devices (ERD) chapter has a comprehensive options list and a critical assessment of their capabilities.

GSF: What are the materials’ challenges for ‘beyond CMOS’ devices?

MG: The critical challenges to support these beyond CMOS devices are to identify materials with properties that enable the stable state and that enable reading or changing the state in a reliable manner. Since less is known about the required material properties for different device concepts, research is needed to understand the mechanisms of state change in the materials.

GSF: Would ‘beyond CMOS’ devices be integrated on silicon wafers?

MG: It is not clear whether they need to be integrated on the silicon wafer at this stage. In many cases, it would be preferred but if devices offer significant advantages, heterogeneous integration might be an option.

GSF: Would ‘beyond CMOS’ be a direct replacement for CMOS devices?

MG: That is unclear. CMOS performs many functions extremely well so having a direct replacement might be very difficult. On the other hand, beyond CMOS may enable new information processing architectures that complement CMOS.

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