The ZBT SRAM memory Application Notes from both Xilinx and Altera provide good reading material concerning the ZBT memory interfacing. The Xilinx App Note is marked "Under Obsolescence", what does not diminish its educational value. The Verilog and VHDL code archives need a careful revision because they are targeting older versions of Xilinx devices.

The Wishbone-compatible non-commercial ZBT SRAM memory controller has been released to Open Cores by Victor Lopez Lorenzo in 2009. The author has simulated and verified the design on a Xilinx Virtex-5 FPGA board ML-506.

Note: Internet Explorer seems to have some problems displaying the Open Cores page. Try Firefox instead.

Please inquire concerning other specs and details that have not been covered above.