The first version of my open-source OpenCV–compatible FPGA Stereo Correspondence Core is now available! (have a look at my previous FPGA Stereo Vision Project post for some more context) It’s written purely in synthesizable Verilog, and uses device-agnostic inference for … Continue reading →

As alluded to in a few of my other posts, I’m working on developing an open-source FPGA-accelerated vision platform. This post is a detailed overview of the project’s architecture and general development methodology. Future (and past) posts will elaborate on … Continue reading →

Eventually, when my FPGA stereo-vision project nears its terminus, I’m going to want to produce a refined sensor board that combines the image sensors and FPGA onto a single board. In preparation for that, this board is a test vehicle … Continue reading →

Reflow soldering is not new. The electronics industry has been using it forever. Hobbyists have been flocking to it in droves. Many use toaster ovens. A growing contingent use skillets. A few do it open-loop. Some use integrated PID controllers. … Continue reading →

Another piece of my ongoing FPGA stereo-vision project. This board is, as the name suggests, a breakout board for Aptina’s excellent MT9V032 1/3″ VGA image sensor. The board’s main purpose in life is to connect the LVDS output of the … Continue reading →

It has now been just over 6 years since I launched the last incarnation of my website. Finally, it has now been supplanted by this – a site that can safely be regarded as superior in virtually every way (if … Continue reading →