General Description

The CMAC1 core provides implementation of cryptographic hashes AES-CMAC per NIST SP 800-38B and AES-XCBC. The cores utilize “flow-through” design that can be easily included into the data path of a communication system or connected to a microprocessor: the core reads the data via the D input, key from the K input and outputs the hash result via its Q output. Data bus widths for D, K, and Q are parameterized. The design is fully synchronous and is available in both source and netlist form.

The core is designed for flow-through operation, with I/O interface of parameterizable width. The input data can contain any number of bytes (data padding is performed inside the core). The output data is the 128-bit MAC value.

Throughput

The throughput of the core on long data packets depends on the core configuration and ranges

from 0.8 bit to 12.8 bits per clock for the 128-bit key

from 0.57 to 9.1 bits per clock for the 256-bit key

On short packets, performance is up to two times lower.

CMAC2 provides two times the performance of CMAC1 at the expense of larger size and lower maximum frequency.