A new class of t-error correcting and all unidirectional error detecting (t-EC/AUED) codes with reduced number of check bits is presented. The encoding/decoding algorithms for this class of codes can be implemented with faster as well as simpler hardware. The ROM implementation of the proposed scheme results in significant saving of word length
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The paper presents SOLiT, an automated system for synthesising reliable sequential circuits with multilevel logic implementation. The reliability enhancement is achieved by using concurrent error detection scheme with coding techniques. The system receives the behavioural description of finite-state machines, determines the required checker circuits, and generates the physical layouts. The synthes...
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RISC processors have approached an execution rate of one instruction per cycle by using pipelining to speed up execution. However, to achieve an execution rate of more than one instruction per cycle, processors must issue multiple instructions in each processor cycle. The paper evaluates the architectural features of iHARP, a VLIW processor with an instruction issue rate of four, which has been de...
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The paper describes a new interconnection network for massively parallel systems, referred to as star-connected cycles (SCC). The SCC graph presents an I/O-bounded structure that results in several advantages over variable degree graphs like the star and the hypercube. The description of the SCC graph includes issues such as labelling of nodes, degree, diameter and symmetry. The paper also present...
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A novel high-speed serial/parallel (S/P) sum-of-products (SOP) hardware structure, based on two's complement number coding, as well as the mathematical framework needed when optimising the hardware structure with respect to bus utilisation is presented. The hardware blocks necessary to obtain a regular and efficient circuit structure are described. The SOP hardware structure basically consists of ...
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A postgeneration method for test time reduction of scan-designed circuits is developed. The maximum overlapping condition between consecutive applied patterns is identified. The application of the condition facilitated with the developed active sliding compatibility process significantly reduces the number of test clocks. It is demonstrated that the test clocks can be reduced by 50% on average fro...
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Video compression is becoming increasingly important, with several applications. There are two kinds of redundancies in a video sequence, namely spatial and temporal. Vector quantisation (VQ) is an efficient technique for exploiting spatial correlation. Temporal redundancies are usually removed by using motion estimation/compensation techniques. The coding performance of VQ may be improved by empl...
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The paper analyses an SRT radix-B division algorithm where the determination of the quotient digits is performed in parallel with the updating of the residual. The authors do not use any prescaling digit prediction (in order to reduce the complexity of the selection function) as it is done using other prediction-based techniques. The authors present application examples of radix-2 (and radix-4, br...
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High-level synthesis consists of many interdependent tasks such as scheduling, allocation and binding. To make efficient use of time and area, functional unit allocation must be performed using a library of modules which contains a variety of module types with identical functionality, but different area and delay characteristics. The synthesis technique presented in the paper simultaneously perfor...
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Using isomorphic embedding of the original dependence graphs in another graph before its space-time mapping onto array architectures, two linear processor arrays are designed for the Gauss-Jordan algorithm with partial pivoting and Cholesky decomposition. Each of these arrays comprises only (n+1)/2 processing elements (PEs), where n is the number of columns in the input matrices. The block pipelin...
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The authors propose a new circular assignment-based switchbox router, CONVERGE, based on segment assignment in circular routing. The CONVERGE router is divided into three phases: the iterative phase, the merging phase and the via reduction phase. In the iterative phase, circular routing will be applied to assign vertical or horizontal segments cycle by cycle. In the merging phase, if switchbox rou...
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Aims & Scope

Published from 1994-2006, IEE Proceedings - Computers and Digital Techniques contained significant and original contributions on computers, computing and digital techniques. It contained technical papers describing research and development work in all aspects of digital system-on-chip design and the testing of electronic and embedded systems, including the development of design automation tools. It was aimed at researchers, engineers and educators in the fields of computer and digital systems design and testing.