The Very first question that potentially arises
here is "What is Synthesis
?"

Synthesis is a blanket term which refers to the
automatic translation of HDL code into an equivalent netlist of digital
cells. Netlist is nothing but the structural logic description equivalent to the
HDL input source. The source (HDL code) is the technology independent logic
description written by the designer. The netlist contains the technology
specific digital cells required for the actual design. There is no standard
format for the netlists that logic synthesis produces, but EDIF
(Electronic Design Interchange Format) is widely used.

Hardware Description
Languages (HDLs) allow the specification of designs in a non-structural
manner, much like a programming language. HDLs are used to describe logic
systems before they are actually implemented so that architectures can be
verified before the logic is actually built. With the advent of synthesis
tools, these high level logic descriptions can be transformed into technology
specific description (netlist) automatically, reducing the design time
and increasing flexibility.

The next possible question would be "What
is a Synthesizable Description ?"

Certain constructs in a hardware description language are either ignored or
are not supported by synthesis tools. The reason for this is that some
constructs have no direct hardware correlation or the hardware intent is
extremely abstract. For example timing related constructs are ignored as the
timing should come from the cells of the technology specific library.
Constructs that are typically not supported include floating-point arithmetic
operators, loop statements without a globally static range, timing related and
file manipulation related constructs.

In September 1999 a standard syntax and semantics for VHDL register
transfer level (RTL) synthesis was defined. The subset of IEEE 1076 (VHDL)
that is suitable for RTL synthesis along with the semantics of that subset for
the synthesis domain. This standard defines a means of writing VHDL that
guarantees the interoperability of VHDL descriptions among any other RTL
synthesis tools that comply with this standard. Compliant synthesis
tools may have any features above those required by this standard. This
standard also minimizes the potential for functional simulation mismatches
between models both before and after they are synthesized.

In April 1999, a draft for a standard for Verilog register transfer level
synthesis was proposed by the IEEE committee. This standard defines a subset
of IEEE 1364-1995 (Verilog HDL) that is suitable for RTL synthesis and defines
the semantics of that subset for the synthesis domain.

In layman's terms, synthesis is a process which translates a description of
the function a module should perform (the behavior) into a composition, that
is, an interconnection of elements (the structure). Synthesis approaches can
be defined at each level of abstraction: circuit, logic and architecture.

Circuit Synthesis

The task of circuit synthesis is to translate a logic description of a
circuit into a network of transistors that meets a set of timing constraints.
this process can be divided into two stages.

Derivation of transistors from logic equations: This
requires the selection of circuit style (complementary static,
pass-transistors, dynamic-logic, DCVSL, etc) and the construction of logic
network. Construction of the logic network is up to the designer.
Basically, the logic gate implementation is transformed or mapped to the
transistor equivalent based on the chosen design style.

Transistor sizing to meet performance constraints: The choice of
the transistor dimensions has a major impact on the area, performance, and
power dissipation of a circuit. The performance of a gate is sensitive to
a number of layout parasitics, such as the size of the diffusion area,
fan-out, and the interconnect capacitances. With these daunting
challenges, many transistor sizing tools have been developed, whose
success rests in their ability of accurate modeling of the performance of
the circuits using RC equivalent circuits and a detailed knowledge of the
subsequent layout generation process. One important point to remember is
that the quality of the cell library has a strong influence on the
complete design.

Logic Synthesis

Logic synthesis is the task of generating a structural view of a
logic-level model. This model can be specified in many different ways, such as
state diagrams, finite state machines (FSMs), schematic diagrams, boolean
equations, truth tables, or HDL descriptions. This data structure is
converted into a network of generic logic cells. this n

The synthesis techniques differ according to the nature of the circuit
(combinational or sequential) or the intended implementation architecture
(multilevel logic, PLA, or FPGA). The synthesis process consists of a sequence
of optimization steps, the order and nature of which depend on the chosen cost
function- area, speed, power or a combination of the three. Typically, logic
optimization systems divide the task into following steps:

A technology independent phase, where the the input HDL is parsed (also
called as analysis) and translated (also called as elaboration)
to a data structure. This data structure is converted into a network of
generic logic cells. This network of generic logic cells is
technology-independent since cell libraries in any technology normally
contain NAND gates and inverters.

Next is the logic optimization phase where the logic is
optimized using a number of boolean or algebraic manipulation techniques.
Many optimization algorithms could be employed here based on the logic
involved (combination or sequential). This steps attempts to improve this
technology-independent network under the control of designer. The output
of this stage is an optimized, but technology-independent logic network.

Further we proceed to the logic-mapping (also called
technology-mapping) phase, where the synthesizer maps the optimized logic
to a specified technology-dependent target cell library. This phase takes
into account the properties of the intended implementation architectures.
The technology-independent description resulting from the earlier phases
is thus translated into a gate netlist or a PLA description.

The two-level minimization tools were the first logic-synthesis
techniques to become widely available. The Espresso program
developed at the university of California at Berkeley is an example of a
popular two-level minimization program. Wide availability of such tools made
regular array-based architectures such as PLAs the prime choice for the
implementation of random logic functions. Later state-machine synthesis came
into picture. tasks involved include state minimization that aims at reducing
the number of machine states, and the state encoding that assigns a binary
encoding to the states of a finite state machine. The emergence of multilevel
logic synthesis environments such as the Berkeley MIS tool
swung the trend towards the standard cell and FPGA implementations that offer
higher performance or integration density for a majority of random-logic
functions. The combination of these techniques with sequential synthesis has
made the RTL synthesis environments complete. The Synopsys Design
Compiler is one of the leaders in the domain and spurred a dramatic
change in the way digital circuit design is performed.

Architecture synthesis is the latest development in the synthesis area. It is
also referred to as behavioral or high-level synthesis. Its
task is to generate a structural view of the architecture/circuit in particular
of its data-path, and a logic-level specification of its control unit, given a
behavioral description of the task to be executed, and a set of performance,
area and/or power constraints. The data-path is an interconnection of resources
(implementing arithmetic or logic functions), steering logic circuits (like
multiplexers and busses), that send data to the appropriate destination at the
appropriate time and registers or memory arrays to store data.

In synthesis jargon, these functions of determining what resources are
needed to perform the task, binding the behavioral operations to
hardware resources, and determining the execution order of the operations on
the produced architecture are called allocation, assignment and scheduling.

While these operations represent the core of architecture synthesis, other
steps can have a dramatic impact on the quality of the solution. An example of
this are optimizing transformations that manipulate the initial behavioral
description so that a superior solution can be obtained in terms of area or
performance. Pipelining is a typical example of such
transformation.

Circuit implementations are evaluated on the basis of the following
objectives: area, cycle-time (clock-period) and latency (number of cycles for
performing all operations as well as throughput (rate of computation) in the
case of pipelined circuits. In general, area and performance depend on the
resources as well as on the steering logic, storage, wiring and control. A
common simplification is to consider area and performance as depending only on
resources. Circuits for which this assumption holds are called resource
dominated circuits and are typical of some application fields such as digital
signal processing (DSP).

Architectural exploration consists of traversing the design space and
providing a spectrum of feasible non-inferior solutions among which the designer
can pick the desired implementation. Architectural synthesis tools can select an
appropriate design point, according to some user specified constraints, and
construct the corresponding data path and control unit.