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Acceleration

Acceleration are techniques that are used to address performance shortcomings of traditional simulation. For example, the design model (i.e., DUT) can be mapped into a hardware accelerator and run much faster during verification, while the testbench continues to run in simulation on a workstation. In this section of the Verification Academy, we focus on building verification acceleration skills.

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Design & Verification Languages

Verification languages are the foundation of the very dynamic electronics industry. Industry continually demands improvements in the process of providing differentiated products into their markets. These verification language courses provide in-depth knowledge of key design and verification languages so that you can identify and deploy them in your upcoming projects.

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Formal-Based Techniques

This topic area focuses on formal-based techniques, ranging from formal property checking to clock-domain crossing (CDC) verification. Assertion-based verification (as it relates to formal property checking) is also covered in this topic area.

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Seminars

FPGA Verification

The definition of what FPGA really means has changed dramatically over the last two decades. Whether blazing the trail or being on the trailing edge of Moore’s Law, this is an exciting time to be an FPGA Designer. New opportunities bring new challenges for the FPGA market. As devices grow and become more complex resembling complete systems, the task of verifying such a system becomes daunting. In this section you will find timely, unbiased information from subject-matter experts that will help you navigate through this ever-changing landscape.

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Planning, Measurement, and Analysis

This topic area focuses on the early stages of a verification project. Topics include considerations for analyzing and evolving your verification capabilities, verification planning, and the introduction of metrics into a flow to measure success.

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Simulation-Based Techniques

This topic area focuses on simulation-based techniques, ranging from stimulus generation, coverage modeling, and correctness checking. Building a contemporary testbench using UVM is also covered in this topic area.

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UVM/OVM

Welcome to the most complete UVM/OVM Online resource collection.

Here you’ll find everything you need to get up to speed on UVM, OVM and latest additions; UVM Express and UVM Connect. Whether it’s downloading the kit(s), discussion forums or online or in-person training. The UVM/OVM Academy Courses provide a great overview of the introductory and advanced methodology concepts, including videos that walk you through some useful code examples.

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Formal Assertion-Based Verification

In this course the instructors will show how to get started with direct property checking including: test planning for formal, SVA coding tricks that get the most out of the formal analysis engines and much more.

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Formal-Based Technology: Automatic Formal Solutions

After a brief introductory session outlining the general architecture of formal apps, in each subsequent session of the course will deep dive on a specific verification challenge and the corresponding formal application.

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Power Aware CDC Verification

This course describes the low power CDC methodology by discussing the low power CDC challenges, describing the UPF-related power logic structures relevant to CDC analysis, and explaining a low power CDC verification methodology.

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VHDL-2008 Why It Matters

VHDL-2008 matters because it facilitates advanced verification, adds reusable data structures, simplifies RTL coding and adds fixed and floating point math packages. VHDL-2008 is the largest change to VHDL since 1993.

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Coverage Cookbook

The Coverage Cookbook describes the different types of coverage that are available to keep track of the progress of the verification process, how to create a functional coverage model from a specification, and provides examples of how to implement functional coverage for different types of designs.

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UVM Cookbook

The UVM library is both a collection of classes and a methodology for how to use those base classes. UVM brings clarity to the SystemVerilog language by providing a structure for how to use the features in SystemVerilog. However, in many cases UVM provides multiple mechanisms to accomplish the same work.

UVM Resources

UVM Documentation

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OVM Cookbook

The OVM is an open source SystemVerilog class library that was the outcome of a collaboration between Mentor Graphics and Cadence Design Systems. There are three main reasons why you should consider using the OVM and these are productivity, commercial considerations and enablement.

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About Us

The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

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Verification Horizons

The Verification Horizons publication expands upon verification topics to provide concepts, values, methodologies and examples to assist with the understanding of what these advanced functional verification technologies can do and how to most effectively apply them.

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Subject Matter Experts (SME's)

Harry Foster is Chief Verification Scientist for Mentor Graphics' Design Verification Technology Division. He holds multiple patents in verification and has co-authored six books on verification--including the 2008 Springer book Creating Assertion-Based IP. Harry was the 2006 recipient of the Accellera Technical Excellence Award for his contributions to developing industry standards, and was the original creator of the Accellera Open Verification Library (OVL) standard.

Tom Fitzpatrick is currently a Verification Technologist at Mentor Graphics Corp. where he brings over two decades of design and verification experience to bear on developing advanced verification methodologies, particularly using SystemVerilog, and educating users on how to adopt them. He has been actively involved in the standardization of SystemVerilog, starting with his days as a member of the Superlog language design team at Co-Design Automation through its standardization via Accellera and then the IEEE, where he has served as chair of the 1364 Verilog Working Group, as well as a Technical Champion on the SystemVerilog P1800 Working Group. At Mentor Graphics, Tom was one of the original designers of the Advanced Verification Methodology (AVM), and later the Open Verification Methodology (OVM), and is the editor of Verification Horizons, a quarterly newsletter with approximately 47,400 subscribers. He is a charter member and key contributor to the Accellera Verification IP Technical Subcommittee. He has published multiple articles and technical papers about SystemVerilog, verification methodologies, assertion-based verification, functional coverage, formal verification and other functional verification topics.

Kurt Takara has over 20 years of experience in engineering design and verification, technical marketing and engineering services. He is a Technical Marketing Engineer at Mentor Graphics Corporation and specializes in assertion-based verification methods and applications, including formal and clock-domain crossing (CDC) verification. Takara has held engineering, marketing, consulting services and project management roles in electronics and EDA companies such as Synopsys, Ikos Systems, Raytheon and Magnavox. He holds a BSEE from Purdue University and an MBA from Santa Clara University.

Mark Eslinger has over 20 years of experience in chip design and verification, pre/post sales support, and technical marketing. As a technical marketing specialist in the Design Verification Technology Division of Mentor Graphics, Mr. Eslinger has a special focus on assertion-based methods and formal verification. He works with customers worldwide to help them adopt advanced methodologies. Prior to Mentor Mr. Eslinger held positions in the engineering and technical marketing organizations in the semiconductor, systems, and EDA industry, including Lockheed, Synopsys, Abstract, Sente/Sequence, Averant, and AccelChip. He holds a MSEE from Santa Clara University.

Joe is part of the DVT Product Marketing team, responsible for Questa Formal and CDC product lines. Prior to joining Mentor last year, Joe’s former marketing position was Director of Product Marketing for Jasper Design Automation, which was recently acquired by Cadence. Prior to Jasper, Joe held Product Marketing positions at both Cadence, and Verisity (Verisity was acquired by Cadence in 2005). In his time at Cadence, in addition to running many successful marketing campaigns, Joe was able to bring his personal passion for video creation to the work place, and helped Cadence expand their video presence in social media channels. Before transitioning to product management and marketing, Joe worked as an EE in FPGA design, Electronic Design Automation (EDA) tools for FPGAs and ASICs, and ASIC verification. Joe’s educational background includes MBA, MSEE and BSEE degrees from Cornell University, Ithaca, NY.

Gordon Allan is the Product Manager and Architect for Visualizer Debug at Mentor Graphics, focusing on advanced debug solutions for today’s complex SoC designs and OOP testbenches. Gordon was one of the developers of Accellera UVM, and was responsible for Mentor's UVM/OVM Methodology Cookbooks published here on the Verification Academy website and appreciated by over 20,000 engineers worldwide, as well as several conference papers on Verification topics at DVCon and elsewhere. Prior to joining the EDA industry in 2010 he gained over 18 years of SoC Design and Verification experience in lead engineer and senior consultant roles, working with many of the top semiconductor companies, fabless startups, system houses and EDA companies worldwide and giving him firsthand experience of customers’ challenges from spec to tapeout. Gordon is based in Silicon Valley.

Rich Edelman is a Verification Technologist specializing in helping customers adopt and deploy the UVM and OVM. Rich has worked in ASIC companies, EDA consulting, EDA start-ups, and 2 of the big three. Rich first got involved with the AVM while developing his “RPS training class”, which was an easy way for people to learn about the AVM. Rich’s verification interests range from DPI and transaction recording to register modeling, sequences and class-based debug. Rich has published many related conference papers, including a Best Paper on SystemVerilog DPI at DVCON, and various transaction recording papers with IPSOC. Rich received a BSEE, a BSCS and an MSCS from Washington University in St. Louis

Ms. Burns has over 25 years of experience in the chip design and the EDA industries in various roles of engineering, applications engineering, technical marketing and product management. She is currently the Product Manager in the Design and Verification Technology Division at Mentor Graphics responsible for simulation with Questa and ModelSim. Prior to Mentor Graphics, Ms. Burns has held engineering and marketing positions at CoWare, Cadence, Synopsys, Viewlogic, Computervision and Intel. She holds a BSCpE from Oregon State University.

Bob Oden supports customer adoption of UVM and advanced verification technologies across North America. He has developed the UVM Framework, UVMF, which has been used by nearly twenty companies to establish company wide verification libraries. He has deep advanced verification methodology experience using e, AVM, OVM, and UVM. Bob has over 20 years experience in design and verification and holds two U.S. patents. He holds a BSEE from California State University, Chico

Adam Erickson is a Verification Methodologist at Mentor Graphics, where he’s served as a principal developer of the OVM, UVM, and UVM Connect. Since earning his Masters in Engineering Sciences at Dartmouth College, Adam has collected 22 years experience in design, verification, and implementation of integrated circuits for companies large and small. He has committed the last 16 of those years developing EDA software and methodological solutions for increasing productivity and reuse in verification. He has authored articles for Verification Horizons and published several conference papers, including Best Paper on a cost-benefit analysis of UVM macros at DVCon 2010. When he’s not improving existing solutions or developing ideas for new ones, Adam can often be found teaching their virtues to others. Adam is currently the primary technical representative for Mentor Graphics on the Accellera VIP-TSC, the committee responsible for UVM standardization.

Andreas Meyer is a Verification Technologist with Mentor Graphics, focusing on functional verification methodology. Andy was one of the developers of OVM, is the author of Principles of Functional Verification, and has been a consultant in the design and verification space for many years.

Mark Olen is currently a Functional Verification Technologist at Mentor Graphics Corp. He has spent thirty years in semiconductor design verification and manufacturing test, and has authored papers in the areas of intelligent testbench automation, design for test technology, and semiconductor manufacturing test automation. He wrote his first testbench in 1981 at Raytheon, and went on to spend ten years working at Teradyne in the ATE and DFT industries. He became Vice President of Cascade Microtech's thin film wafer probe division, before co-founding Lighthouse Design Automation where graph-based Intelligent Testbench Automation was first successfully applied to semiconductor design verification. Mark graduated from MIT with a BS in EE&CS.

As Director of Emerging Technologies, Stephen Bailey seeks out and develops new technology, solutions and business opportunities in functional verification and related areas. He brings many years of industry experience working in R&D, applications and technical and product marketing. He has contributed to the industry through participation in industry standards, including chairing VHDL (IEEE 1076) and UPF (IEEE 1801) working groups, and serving in various roles from member of technical program committee to conference chair with conferences such as DVCon. Prior to joining the EDA industry, Steve developed embedded software and software development tools. Steve has BS and MS degrees in computer science from Chapman University.

Jason Polychronopoulos is a Product Manager for Verification IP at Mentor Graphics. He has over 14 years of experience in functional verification, verification tools, methodologies and design of verification IP. Mr. Polychronopoulos holds a Masters in Electronic Engineering from The University of Manchester.

Matthew Ballance is a Verification Technologist at Mentor Graphics for the Design Verification Technology division, specializing in the Questa inFact Intelligent Testbench Automation tool. He has 15 years of experience in the EDA industry, and has previously worked in the areas of HW/SW Co-verification and transaction-level modeling.

Mark Peryer is a Verification Methodologist within the Design Verification and Technology division at Mentor Graphics and is responsible for developing and deploying verification methodologies and solutions. He developed his first verification environment for a graphics processor in the mid-eighties and although the languages and the techniques have changed, he has continued to work on hairy verification problems ever since. Mark is the author of many conference papers, articles and training classes and holds an honours degree in Electronic Engineering from Southampton University.

Michael Horn is a Principal Verification Architect specializing in helping ASIC and FPGA groups and companies to deploy UVM and OVM. He started his career in the telecom and storage industries doing design and verification. For the past several years, Michael has been working with Mentor Graphics to help Mentor's customers to use Mentor's tools, but also to grow the customers verification capabilities and techniques. He has been using high level verification languages since 1999 starting with Specman E then moving to Vera and now SystemVerilog. Michael has co-authored numerous publications and conference papers including papers for DVCon. He received his BSEE from the University of Illinois at Urbana-Champaign

Erich Marschner has more than 30 years of experience developing language-based tools, systems, methodology, and industry standards for electronic systems design and verification. Currently, Erich is a Verification Architect with the Design Verification and Technology Division at Mentor Graphics and vice-chair of the IEEE 1801 UPF working group.

Chuck Seeley has over 27 years of experience in engineering design and verification, and technical marketing. As a Technical Marketing Engineer at Mentor Graphics Corporation he specializes in both assertion-based verification and coverage driven verification methods. He holds a BSEE from Portland State University.

Raghu Ardeishar is a Verification Technologist at Mentor Graphics for the Design Verification Technology division, specializing in Verification IP. He has 12 years of experience in the EDA industry, and has previously worked in the areas of HW design and verification. He has a Masters in Electrical Engineering from Virginia Tech.

Jim Kenney has 30 years of simulation experience including hardware emulation and HW/SW co-simulation. He’s worked as a developer, applications engineer, and is currently the Marketing Director for Mentor’s Emulation Division. He holds a BSEE from Clemson University.

Dr. Hans van der Schoot is a recognized specialist in verification technology, and employed as a methodologist in the Emulation Division at Mentor Graphics. Hans has a solid background and wealth of knowledge in functional verification from his many years as a researcher, engineer and consultant in the field, with extensive practical experience providing verification methodology and implementation consulting and training services in the industry. He has authored multiple papers pertinent to hardware verification and software testing. Hans obtained his doctorate degree in computer science from the University of Ottawa, Canada, after graduating from the University of Twente in the Netherlands, also in computer science. Prior to joining Mentor Graphics, he was the Vice President Engineering at XtremeEDA. He has also worked independently as an expert design verification consultant, following senior engineering positions with Qualis Design, PMC-Sierra, and Nortel Networks.

John Stickley is a Verification Technologist at Mentor Graphics Emulation Division. His research interests are in electronic design verification methodologies. His most recent work at Mentor Graphics has been in the area of high-performance emulation based verification techniques in particular with using SystemVerilog OVM/UVM and SystemC TLM-2.0 based testbench modeling - particularly in conjunction with the use of virtual processor platforms. He has 30 years of experience in the EDA industry and holds a BSEE degree from Cornell University.

Thomas Ellis is a Verification Technologist at Mentor Graphics for the Design Verification Technology division, specializing in the Questa Verification Management tool. Prior to joining the Design and Verification division, Thomas held the position of applications engineer in the Customer Support division. He holds a BSCS and BSEE from Oregon Institute of Technology.

Doug Smith is an Application Engineering Consultant for Mentor Graphics based in the Austin Texas area where he provides tool, language, and verification methodology support across the Questa simulation and formal functional verification platform. Doug started his career at Sun Microsystems, performing block and fullchip verification as part of the UltraSparcV processor team, and emulated the UltraSparcIII and ASIC chipset for Sun's workgroup servers. Afterwards, he led and managed a team of verification engineers overseas offering SoC and IP verification services on large designs such as TI's OMAP processors and Freescale's GSM radio. He also worked on 802.11 MAC/PHY verification and his team specialized in synthesizable, emulation-friendly verification IP.

Prior to Mentor, he provided application support in formal technologies, and was a subject-matter expert as a trainer and consultant for Doulos, where he delivered training in design best-practices, verification methodologies like UVM, and hardware languages like VHDL, Verilog, SystemVerilog. Doug holds a masters degree in Computer Engineering from the University of Cincinnati and a bachelors degree in Physics from Northern Kentucky University. Currently, he resides in Paige, Texas with his wife and two of his three children as a beekeeper and hobby farmer.

Dr. Levitt is a Principal Engineer in the Formal Verification Group of Mentor Graphics DVT. He oversees R&D with a focus on algorithm development. Jeremy earned his Ph.D in Electrical Engineering from Stanford in 1997, M.S. in 1993 and a B.A.Sc in Engineering Science from the University of Toronto in 1991.

Ahmed Eisawy is a member of the Technical & Product Marketing team of the Analog/Mixed-Signal group – part of the Deep Sub-micron Division – at Mentor Graphics. For the last five years, he’s been working as a member of the marketing team to drive the development of Analog/Mixed-Signal simulators forward with new technologies as well as engage with customers for evaluations, training & education, solving complex problems as well as help the customers through methodology assessments to improve their flow. Previously, Ahmed worked for seven years in technical support where he worked closely with customers, helping resolve problems and help formulate the customer needs into tool enhancements. He received his BSEE from Cairo University in 1999 and his MSEE from the same university in 2002.

Cliff Cummings is President of Sunburst Design, Inc., a company that specializes in world class Verilog, SystemVerilog and synthesis training. Mr. Cummings is an independent consultant and trainer with 27 years of ASIC, FPGA and system design experience and 17 years of Verilog, SystemVerilog, synthesis and methodology training experience. Mr. Cummings has completed many ASIC designs, FPGA designs and system simulation projects, and is capable of answering the very technical questions asked by experienced design engineers. Mr. Cummings has taught expert Verilog, SystemVerilog and synthesis topics to thousands of engineers world-wide since 1992.

Neil Johnson has been working in ASIC and FPGA development for more than 14 years. He's a functional verification specialist and currently holds the position of Principal Consultant at XtremeEDA Corp, a design services firm specializing in all aspects of ASIC and FPGA development. Neil is also co-moderator for AgileSoC.com, a site dedicated to the introduction of Agile development methods to the world of hardware development.

Jin Zhang, VP of Marketing and Customer Relations, Oski Technology has over 15 years of experience working in EDA, driving the effort of bringing new products and services to market. At Oski, she is responsible for the overall marketing strategy as well as business development in Asia Pacific. Prior to that, she was the General Manager at EVE China, and Director of Technical Marketing at Real Intent. She has also worked at Cadence Design Systems and Lattice Semiconductor. Jin has a PhD in logic synthesis and verification and a Master’s degree in International Management focusing on Asia Pacific.

Jim Lewis, the founder of SynthWorks, has twenty-eight years of design, teaching, and problem solving experience. In addition to working as a Principal Trainer for SynthWorks, Mr. Lewis does ASIC and FPGA design, custom model development, and consulting. Mr. Lewis was previously employed with Zycad's Protocol division where he worked as an on-site VHDL trainer, methodology consultant, and ASIC designer. As a representative from Zycad, he provided VHDL training, methodology consulting, and ASIC design for Lockheed Sanders in their development of 22 ASICs for the F22 program. On another assignment for Zycad, he worked as a VHDL trainer, Synopsys synthesis trainer, problem solver, and ASIC designer for SGS Thomson in their development of a Video Codec chip. In addition to other responsibilities, Mr. Lewis acted as an on-site focal point for resolving VHDL synthesis issues for both companies.

Mr. Lewis was also employed by TRW where he designed ASICs, FPGAs, and worked as a member of their VHDL Methodology Development Group. Mr. Lewis, who holds a BSEE/BSCEE and MSEE from Purdue University, is a member of the IEEE and the Eta Kappa Nu, and Tau Beta Pi Honor Societies. Mr. Lewis is chair of the IEEE 1076 VHDL Analysis and Standardization Working Group (VASG) and is an active member in IEEE and Accellera's VHDL standardization efforts. Mr. Lewis is also co-author of VHDL-2008: Just the New Stuff and recommends The Designer’s Guide to VHDL and the VHDL-2008 LRM.

John Aynsley is co-founder and CTO at Doulos, where he runs the technical team as well as consulting for customers and delivering training courses and seminars. John has spent his entire career working in EDA, specializing in simulation, languages (particularly VHDL, SystemVerilog, and SystemC), hardware verification and system modeling, and has written many training courses and technical papers in these areas. He is co-author of the IEEE 1666 SystemC standard, author of the OSCI TLM-2.0 LRM, and an active contributor to several technical working groups and forums. His current role spans technical consulting, technical marketing, and business management.

Ram Narayan is a Consulting Member of Technical Staff in Oracle Labs. He is a member of the RAPID SoC Hardware Verification Team since January 2013. Prior to joining Oracle, Ram was a Principal Member of Technical Staff in the Platform Emulation Team at Advanced Micro Devices. In this capacity, he was driving improvements to the pre-silicon emulation strategy to impact the post-silicon validation effort and reduce the time to market. Ram joined AMD from Mentor Graphics in 2010. As an Application Engineer at Mentor Graphics, he helped Mentor's customers realize their verification goals with a range of technologies including Simulation, Formal Verification, Assertion and Coverage Based Verification, Testbench Automation, Hardware Software Co-verification and Hardware Emulation. Ram has 26 patents granted in the US. Ram received a B.Tech. in Electrical Engineering at The Indian Institute of Technology, Bombay in 1991 and an M.S. in Computer Engineering at The University of Texas at Austin in 1994.

Peet James was recently described by a customer as a “Verification Animal”. Over his 25+ years of experience he has always had one foot entrenched in improving both design and verification methodologies and processes, and the other foot entrenched in directly applying these to actual projects. Peet’s specialty is verification planning and management where he typically takes a team of engineers and guides them into architecting, documenting and implementing successful verification environments. Peet started out working at Sperry, IBM & Motorola, and then moved into consulting as one of the principles at Qualis Design Corporation. Peet has been with Mentor Graphics for the past 3 years. Peet has many award winning papers and is a published author of a book on verification planning.

Steve Chappell is a Solutions Architect specializing in Intelligent Testbench Automation and other advanced verification techniques. He has been designing and verifying (or helping others design and verify) hardware and software products in the Semiconductor IP and EDA industries for about fifteen years, the last five with Mentor Graphics. He has been a regular presenter and track chair at User2User Conferences across the country. He holds BSEE and MSEE degrees, both from Stanford University.

Albert Chiang is currently the Product Marketing Manager for the Questa Verification Platform. He has over 20 years of experience designing and verifying ASICs & ARM based SOCs. Currently he is focused on the burgeoning field of Design Verification, where he has published and presented papers at IEEE, ARM Developer’s Conference (now ARM TechCon), DVCon, and numerous public seminars worldwide. Previously to Mentor Graphics, he was an senior design engineer at VLSI Technology, design engineer at Intel Corporation, and a PMM/TMM/AE at Synopsys. He has a BSEE from California State University and an MBA from Santa Clara University.