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FET Structure

Publishing Venue

IBM

Related People

Jambotkar, CG: AUTHOR

Abstract

A method is disclosed for fabricating an FET structure which provides improved performance characteristics. The FET source and drain of such structure have thick SiO(2) islands beneath them formed in a manner self-aligned to the SiO(2)/Si(3)N(4) sidewall of the N/+/ polysilicon gate.

Country

United States

Language

English (United States)

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FET Structure

A method is disclosed for fabricating an FET structure which provides
improved performance characteristics. The FET source and drain of such
structure have thick SiO(2) islands beneath them formed in a manner self-aligned
to the SiO(2)/Si(3)N(4) sidewall of the N/+/ polysilicon gate.

Starting with a P/-/ substrate 2 as shown in Fig. 1, a layer 4 of approximately
500 angstroms of SiO(2) is grown. Then, ~ 800 angstroms of Si(3)N deposited
and, using a photoresist mask 7, patterns are formed in the Si(3)N(4) 6/SiO(2) 4.
Thereafter, ~ 5000 angstroms deep trenches 8 are etched i substrate 2.
Retaining mask 7, "field channel stopper" P regions 10 are formed at the bottom
of trenches 8 through the ion implant of a suitable dose of boron.

As shown in Fig. 2, photoresist 7 is removed and ~ 1 mu m of SiO(2) 3 is
thermally grown in the silicon regions not covered by Si(3)N(4). The Si(3)N(4)
layer 6 is then removed.

As shown in Fig. 3, there is then deposited an N/+/ doped layer 0.9 mu m) of
polysilicon 5 and a layer ~ 0.2 mu m) of Si(3)N(4) 13, and then patterns are
formed in the composite layers. Using the polysilicon/ nitride composite as a
mask, a suitably low dose of arsenic is ion-implanted into the P/-/ substrate to
obtain the final structure including N region 9, as shown in Fig. 3.

Thereafter, steps are taken to successively deposit ~600 angstroms of Si(3)N
11 and ~ 0.9 mu m of SiO(2) 12, as shown in Fig. 4. Through vertically
directional reactive ion etching (RIE), SiO(2) 12, Si(3)N(4) 11 and thin SiO(2) 4
are etched so as to obt...