3.2
Transistor Parasitic Capacitance

Logic-cell delay results from transistor resistance, transistor (intrinsic) parasitic capacitance, and load (extrinsic) capacitance. When one logic cell drives another, the parasitic input capacitance of the driven cell becomes the load capacitance of the driving cell and this will determine the delay of the driving cell.

Figure
3.4
shows the components of transistor parasitic capacitance. SPICE prints all of the MOS parameter values for each transistor at the DC operating point. The following values were printed by PSpice (v5.4) for the simulation of Figure
3.3
:

3.2.1 Junction Capacitance

The junction capacitances,
C
BD
and
C
BS
, consist of two parts: junction area and sidewall; both have different physical characteristics with parameters:
CJ
and
MJ
for the junction,
CJSW
and
MJSW
for the sidewall, and
PB
is common. These capacitances depend on the voltage across the junction (
V
DB
and
V
SB
). The calculations in Table
3.1
assume both source and drain regions are 6
m
m
¥
1.2
m
m rectangles, so that A
D
=
A
S
=
7.2
(
m
m)
2
, and the perimeters (excluding the 1.2
m
m channel edge) are P
D
=
P
S
=
6
+
1.2
+
1.2
=
8.4
m
m. We exclude the channel edge because the sidewalls facing the channel (corresponding to
C
BSJ
GATE
and
C
BDJ
GATE
in Figure
3.4
) are different from the sidewalls that face the field. There is no standard method to allow for this. It is a mistake to exclude the gate edge assuming it is accounted for in the rest of the model—it is not. A pessimistic simulation includes the channel edge in P
D
and P
S
(but a true worst-case analysis would use more accurate models and worst-case model parameters). In HSPICE there is a separate mechanism to account for the channel edge capacitance (using parameters
ACM
and
CJGATE
). In Table
3.1
we have neglected
C
J
GATE
.

3.2.2 Overlap Capacitance

The overlap capacitance calculations for C
GSOV
and C
GDOV
in Table
3.1
account for lateral diffusion (the amount the source and drain extend under the gate) using SPICE parameter
LD
=
5E-08
or L
D
=
0.05
m
m. Not all versions of SPICE use the equivalent parameter for width reduction,
WD
(assumed zero in Table
3.1
), in calculating C
GDOV
and not all versions subtract W
D
to form W
EFF
.

FIGURE 3.5
The variation of
n
-channel transistor parasitic capacitance. Values were obtained from a series of DC simulations using PSpice v5.4, the parameters shown in Table
3.1
(
LEVEL=3
), and by varying the input voltage,
v(in1)
, of the inverter in Figure
3.3
(a). Data points are joined by straight lines. Note that
CGSOV
=
CGDOV
.

3.2.4 Input Slew Rate

Figure
3.6
shows an experiment to monitor the input capacitance of an inverter as it switches. We have introduced another variable—the delay of the input ramp or the
slew rate of the input.

In Figure
3.6
(b) the input ramp is 40
ps long with a slew rate of 3
V/ 40
ps or 75
GVs
–1
—as in our previous experiments—and the output of the inverter hardly moves before the input has changed. The input capacitance varies from 20 to 40
fF with an average value of approximately 34
fF for both transitions—we can measure the average value in Probe by plotting
AVG(-i(Vin))
.

(a)

(b)

(c)

FIGURE 3.6
The input capacitance of an inverter. (a) Input capacitance is measured by monitoring the input current to the inverter,
i(Vin)
. (b) Very fast switching. The current,
i(Vin)
, is multiplied by the input ramp delay (
D
t
=
0.04
ns) and divided by the voltage swing (
D
V
=
V
DD
=
3
V) to give the equivalent input capacitance,
C
=
i
D
t
/
D
V
. Thus an adjusted input current of 40
fA corresponds to an input capacitance of 40
fF. The current,
i(Vin)
, is positive for the rising edge of the input and negative for the falling edge. (c) Very slow switching. The input capacitance is now equal for both transitions.

In Figure
3.6
(c) the input ramp is slow enough (300
ns) that we are switching under almost equilibrium conditions—at each voltage we allow the output to find its level on the static transfer curve of Figure
3.2
(a). The switching waveforms are quite different. The average input capacitance is now approximately 0.04
pF (a 20
percent difference). The propagation delay (using an input trip point of 0.5 and an output trip point of 0.35) is negative and approximately 150
–
127
=
–23
ns. By changing the input slew rate we have broken our model. For the moment we shall ignore this problem and proceed.

The calculations in Table
3.1
and behavior of Figures
3.5
and
3.6
are very complex. How can we find the value of the parasitic capacitance,
C
, to fit the model of Figure
3.1
? Once again, as we did for pull resistance and the intrinsic output capacitance, instead of trying to derive a theoretical value for
C,
we adjust the value to fit the model. Before we formulate another experiment we should bear in mind the following questions that the experiment of Figure
3.6
raises: Is it valid to replace the nonlinear input capacitance with a linear component? Is it valid to use a linear input ramp when the normal waveforms are so nonlinear?

Figure
3.7
shows an experiment crafted to answer these questions. The experiment has the following two steps:

Remove all the parasitic capacitances for inverter
m9/10
—except for the gate capacitances
C
GS
,
C
GD
, and
C
GB
—and then adjust
c3
(0.01
pF) and
c4
(0.025
pF) to model the effect of these missing parasitics.

(a)

(c)

(b)

(d)

FIGURE 3.7
Parasitic capacitance. (a) All devices in this circuit include parasitic capacitance. (b) This circuit uses linear capacitors to model the parasitic capacitance of
m9/10
. The load formed by the inverter (
m5
and
m6
) is modeled by a 0.0335
pF capacitor (
c2
); the parasitic capacitance due to the overlap of the gates of
m3
and
m4
with their source, drain, and bulk terminals is modeled by a 0.01
pF capacitor (
c3
); and the effect of the parasitic capacitance at the drain terminals of
m3
and
m4
is modeled by a 0.025
pF capacitor (
c4
). (c) The two circuits compared. The delay shown (1.22
–
1.135
=
0.085
ns) is equal to
t
PDf
for the inverter
m3/4
. (d) An exact match would have both waveforms equal at the 0.35 trip point (1.05
V).

We can summarize our findings from this and previous experiments as follows:

Since the waveforms in Figure
3.7
match, we can model the input capacitance of a logic cell with a linear capacitor. However, we know the input capacitance may vary (by up to 20
percent in our example) with the input slew rate.

The input waveform to the inverter
m3/m4
in Figure
3.7
is from another inverter—not a linear ramp. The difference in slew rate causes an error. The measured delay is 85
ps (0.085
ns), whereas our model (Eq.
3.7
) predicts

The last two observations are useful. Since the gate capacitances are nonlinear, we only see about 0.025/0.037 or 70 percent of the 0.037
pF gate-oxide capacitance, C
O
, in the input capacitance,
C
. This means that it happens by chance that the total gate-oxide capacitance is also a rough estimate of the gate input capacitance,
C
ª
C
O
. Using L and W rather than L
EFF
and W
EFF
in Eq.
3.9
helps this estimate. The accuracy of this estimate depends on the fact that the junction capacitances are approximately one-third of the gate-oxide capacitance—which happens to be true for many CMOS processes for the shapes of transistors that normally occur in logic cells. In the next section we shall use this estimate to help us design logic cells.