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AR# 34704

Spartan-6 - Use of the PLL DRP will result in Post Config CRC errors

Description

When I use the PLL DRP in my Spartan-6 FPGA design, I see errors in the Post Config CRC check. Why is this? Can I use the Post Config CRC and PLL DRP together?

Solution

Use of the PLL DRP is not masked; therefore, any change to the PLL results in a CRC error. Pausing the CRC check during DRP writes will not work around this as the values will still be checked and the next CRC check will not match the golden CRC value.