MEMORY MODULE, IN THE PETABIT (10[15]) TO EXABIT (10[18] BIT) RANGE, BASED ON PHOTON ECHO PHENOMENON, FOR SYSTEMS INTEGRATION INTO CONTEMPORARY COMPUTER CONFIGURATIONS BUT MORE IMPORTANTLY TO BE THE MEMORY COMPONENT IN FUTURE CONFIGURATIONS WHICH IS

MEMORY MODULE, IN THE PETABIT (10[15]) TO EXABIT (10[18] BIT) RANGE, BASED ON PHOTON ECHO PHENOMENON, FOR SYSTEMS INTEGRATION INTO CONTEMPORARY COMPUTER CONFIGURATIONS BUT MORE IMPORTANTLY TO BE THE MEMORY COMPONENT IN FUTURE CONFIGURATIONS WHICH IS COMMENSURATE WITH RESULTS OF CURRENTADVANCED R & D OF OTHER COMPONENTS, E.G., ULTRA VLSI (VERY LARGE SCALE INTEGRATED CIRCUITS) BY MANY COMPANIES WORLD-WIDE, VHSIC (VERY HIGH SPEED INTEGRATED CIRCUIT) BY DEFENSE DEPARTMENT, OPTICAL SWITCHIG, LASER GENERATED CLOCK RATES, AND OTHERS. WITHOUT RANDOM ACCESS MEMORY COMPONENT WITH PHOTON ECHO MEMORY (PEM) CHARACTERISTICS, THE UPPER VALUES OF HIGH TECHNOLOGY IN THOSE OTHER COMPONENTS CANNOT POSSIBLY BE REALIZED; A COMMENSURATE RAM IS ESSENTIAL; AND THIS PEM PROJECT IS THE ONLY ONE KNOWN TO BE DIRECTED THERETO. THIS PROJECT WILL PRODUCE A SUITABLE "BASELINE" FOR INITIATION OF PHASE II, WHICH WILL BE DIRECTED TO FABRICATION AND ASSEMBLY OF AN ADVANCED DEVELOPMENTAL MODEL OF A 3D PEM AT THE 10(9) (GIGABIT) LEVEL. THAT BASELINE, TOBE PRODUCED BY PHASE I, WILL INCLUDE A COMPLETE INVENTORY, DESCRIPTION, SELECTION OF MATERIALS, AND WORK PLAN FOR THE CONDUCT OF PHASE II, IN ADDITION TO UPDATE OF TECHNOLOGIES INVOLVED BEYOND THE PROOF OF PRINCIPLE ALREADY ESTABLISHED (TO POINT OF PATENT ABILITY). PHASE III WILL THEN PRODUCE ADVANCED DEVELOPMENTAL AND ENGINEERING DESIGN MODELS OF A 10(15) BIT MODULE, AS WELL AS SPECIFICATIONS FOR VALUE ENGINEERING, SYSTEMS INTEGRATION, AND PRE-PRODUCTION PROTOTYPE AND COMPLETE SPECIFICATIONS FOR PRODUCTION MODELS.