DESIGN of area- and power-efficient high-speed data path logic
systems are one of the most substantial areas of research in VLSI
system design. In digital adders, the speed of addition is limited by the
time required to propagate a carry through the adder. The sum for each
bit position in an elementary adder is generated sequentially only after
the previous bit position has been summed and a carry propagated into
the next position.
The CSLA is used in many computational systems to alleviate the
problem of carry propagation delay by independently generating multiple
carries and then select a carry to generate the sum [1]. However,
the CSLA is not area efficient because it uses multiple pairs of Ripple
Carry Adders (RCA) to generate partial sum and carry by considering
carry input and , then the final sum and carry are
selected by the multiplexers (mux).
The basic idea of this work is to use Binary to Excess-1 Converter
(BEC) instead of RCA with in the regular CSLA to achieve
lower area and power consumption [2]–[4]. The main advantage of this
BEC logic comes from the lesser number of logic gates than the

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Carry Select Adder (CSLA) is one of the fastest adders used
in many data-processing processors to perform fast arithmetic functions.
From the structure of the CSLA, it is clear that there is scope for reducing
the area and power consumption in the CSLA. This work uses a simple and
efficient gate-level modification to significantly reduce the area and power
of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root
CSLA (SQRT CSLA) architecture have been developed and compared with
the regular SQRT CSLA architecture. The proposed design has reduced
area and power as compared with the regular SQRT CSLA with only a
slight increase in the delay. This work evaluates the performance of the
proposed designs in terms of delay, area, power, and their products by
hand with logical effort and through custom design and layout in 0.18- m
CMOS process technology. The results analysis shows that the proposed
CSLA structure is better than the regular SQRT CSLA.

INTRODUCTION

Design of area- and power-efficient high-speed data path logic systems
are one of the most substantial areas of research in VLSI system
design. In digital adders, the speed of addition is limited by the time
required to propagate a carry through the adder. The sum for each bit
position in an elementary adder is generated sequentially only after the
previous bit position has been summed and a carry propagated into the
next position.

BEC

As stated above the main idea of this work is to use BEC instead of
the RCA with

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