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CS136 4 Overcoming Limits Advances in compiler technology + significantly new and different hardware techniques may be able to overcome limitations assumed in studies However, unlikely such advances when coupled with realistic hardware will overcome these limits in near future

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CS136 20 How to Exceed ILP Limits of This Study? These are not laws of physics –Just practical limits for today –Could be overcome via research Compiler and ISA advances could change results WAR and WAW hazards through memory: eliminated WAW and WAR hazards through register renaming, but not in memory usage –Can get conflicts via allocation of stack frames –Because called procedure reuses memory addresses of previous stack frames

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CS136 21 HW v. SW to increase ILP Memory disambiguation: HW best Speculation: –HW best when dynamic branch prediction better than compile-time prediction –Exceptions easier for HW –HW doesn’t need bookkeeping code or compensation code –Very complicated to get right in SW Scheduling: SW can look ahead to schedule better Compiler independence: HW does not require new compiler to run well

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CS136 22 Performance Beyond Single-Thread ILP Much higher natural parallelism in some applications –Database or scientific codes Explicit thread-level or data-level parallelism Thread: has own instructions and data –May be part of parallel program or independent program –Each thread has all state (instructions, data, PC, register state, and so on) needed to execute Data-level parallelism: Perform identical operations on lots of data

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CS136 23 Thread Level Parallelism (TLP) ILP exploits implicit parallel operations within loop or straight-line code segment TLP explicitly represented by multiple threads of execution that are inherently parallel Goal: Use multiple instruction streams to improve –Throughput of computers that run many programs –Execution time of multi-threaded programs TLP could be more cost-effective to exploit than ILP

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CS136 24 Do Both ILP and TLP? TLP and ILP exploit two different kinds of parallel structure in a program Could a processor oriented to ILP still exploit TLP? –Functional units are often idle in data path designed for ILP because of either stalls or dependencies in the code Could TLP be used as source of independent instructions that might keep the processor busy during stalls? Could TLP be used to employ functional units that would otherwise lie idle when insufficient ILP exists?

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CS136 26 Fine-Grained Multithreading Switches between threads on each instruction, interleaving execution of multiple threads Usually done round-robin, skipping stalled threads CPU must be able to switch threads every clock Advantage: can hide both short and long stalls –Instructions from other threads always available to execute –Easy to insert on short stalls Disadvantage: slows individual threads –Thread ready to execute without stalls will be delayed by instructions from other threads Used on Sun’s Niagara (will see later)

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CS136 27 Course-Grained Multithreading Switches threads only on costly stalls –E.g., L2 cache misses Advantages –Relieves need to have very fast thread switching –Doesn’t slow thread »Other threads only issue instructions when main one would stall (for long time) anyway Disadvantage: pipeline startup costs make it hard to hide throughput losses from shorter stalls –Pipeline must be emptied or frozen on stall, since CPU issues instructions from only one thread –New thread must fill pipe before instructions can complete –Thus, better for reducing penalty of high-cost stalls where pipeline refill << stall time Used in IBM AS/400

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CS136 28 Simultaneous Multithreading (SMT) Simultaneous multithreading (SMT): insight that dynamically scheduled processor already has many HW mechanisms to support multithreading –Large set of virtual registers that can be used to hold register sets for independent threads –Register renaming provides unique register identifiers »Instructions from multiple threads can be mixed in data path »Without confusing sources and destinations across threads! –Out-of-order completion allows the threads to execute out of order, and get better utilization of the HW Just add per-thread renaming table and keep separate PCs –Independent commitment can be supported via separate reorder buffer for each thread Source: Micrprocessor Report, December 6, 1999 “Compaq Chooses SMT for Alpha”

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CS136 33 Covert-Channel Attacks on Crypto Most (not all) crypto code behaves differently on “1” bit in key vs. “0” bit –Runs longer or shorter –Uses more or less power –Accesses different memory –Etc. Usually called “information leakage” Has been successfully used in lab to crack strong crypto –Even recovering some bits makes brute-force attack practical for getting remainder –Some modern implementations try to fight by doing wasted work on shorter path of “if”, etc.

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CS136 34 SMT Attack on SSH On SMT machine, lower-priority thread’s execution rate depends on higher-priority one’s instructions –More stalls in top thread mean more speed in bottom one –Stalls vary depending on what crypto code is doing »Operates at very low level »Thus much harder to defend against Successful attack on ssh keys has been demonstrated in lab Best known defense: don’t do SMT –Careful coding of crypto could probably also work –Note that this also applies to things like cache and TLB –Lots of ways to leak information unintentionally!

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CS136 35 Power 4 Single-threaded predecessor to Power 5. 8 execution units in out-of-order engine; each can issue instruction each cycle.

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CS136 40 Initial Performance of SMT Pentium 4 Extreme SMT yields 1.01 speedup for SPECint_rate benchmark; 1.07 for SPECfp_rate –Pentium 4 is dual-threaded SMT –SPECRate requires each benchmark to be run against vendor- selected number of copies of same benchmark Pairing each of 26 SPEC benchmarks with every other on Pentium 4 (26 2 runs) gives speedups from 0.90 to 1.58; average was 1.20 8-processor Power 5 server 1.23 faster for SPECint_rate w/ SMT, 1.16 faster for SPECfp_rate Power 5 running 2 copies of each app had speedup between 0.89 and 1.41 –Most gained some –Floating-point apps had most cache conflicts and least gains

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CS136 45 No Silver Bullet for ILP No obvious overall leader in performance AMD Athlon leads on SPECInt performance, followed by the Pentium 4, Itanium 2, and Power5 Itanium 2 and Power5 clearly dominate Athlon and Pentium 4 on SPECFP Itanium 2 is most inefficient processor both for floating-point and integer code for all but one efficiency measure (SPECFP/Watt) Athlon and Pentium 4 both use transistors and area efficiently IBM Power5 is most effective user of energy on SPECFP, essentially tied on SPECINT

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CS136 48 Commentary Itanium is not significant breakthrough in scaling ILP or in avoiding problems of complexity and power consumption Instead of pursuing more ILP, architects turning to TLP using single-chip multiprocessors In 2000, IBM announced Power4, 1st commercial single-chip, general-purpose multiprocessor: has two Power3 processors and integrated L2 cache –Sun Microsystems, AMD, and Intel have also switched focus from aggressive uniprocessors to single-chip multiprocessors Right balance of ILP and TLP is unclear today –Maybe desktops (mostly single-threaded?) need different design than servers (can do lots of TLP)