Time flies like a banana.Fruit flies when you're having fun.BTW, Do these genes make my ass look fat?corruptio optimi pessimaLast edited by JovianPyx on Sat Feb 15, 2014 7:51 am; edited 1 time in total

Well, certainly we can use USB to receive a MIDI data stream and I may do that with special programs I write for a PC. In fact, I've done that with one synth and an Aleatoric Sequence Generator (a big nasty VB.NET program).

But I also have a number of hardware MIDI synths that use the standard 5 pin DIN and when I'm creating a piece that uses those other hardware devices with a PC based sequencer, I need to use the 5 pin DIN. The electronics for the interface are so inexpensive it's not worth mentioning the price. In fact, I've already got a PMOD board with the MIDI current loop electronics that will plug into one of the PMOD connectors.

But that's the real beauty of an FPGA - we can just substitute the modules we need. There is ethernet on the board and I'd bet usable/modifiable cores and then one could have MIDI over ethernet.

The problem I have with using USB for transmitting MIDI data streams is that I have no software that supports it on the PC side. That is, software that includes a well featured sequencer. For that I use Cakewalk (an ancient version that runs on a win98SE box). Educate me if I am wrong, but is it not true that things that can use USB for MIDI must see the USB port as a MIDI port and not a COM port? I have a feeling that this FPGA board will show up as some COM port when the driver is loaded and the bridge is setup (assuming there is a bridge)._________________FPGA, dsPIC and Fatman Synth Stuff

Time flies like a banana.Fruit flies when you're having fun.BTW, Do these genes make my ass look fat?corruptio optimi pessima

There is a free version of Vivado that supports the FPGA. I've not used it, but I know it's a different sort of work flow from ISE (which I have used)._________________FPGA, dsPIC and Fatman Synth Stuff

Time flies like a banana.Fruit flies when you're having fun.BTW, Do these genes make my ass look fat?corruptio optimi pessima

This looks really cool and more flexible than the Mojo boards (also cool, but the tutorials seem uber-basic).

I'm having some conceptual trouble in figuring out how one goes from digital logic to audio processing. I'm broadly familiar with DSP and have some experience with Motorola/Freescale 56k assembler (long ago). what I'm specifically interested in is FX processing rather than pure synthesis, and I'm particulary implemented in reimplementing Dattoro's classic algorithms as found in the Ensoniq ESP2 chip. I've spent some time looking at Scott's project pages and source files, but (to put it in a nutshell) I'm not seeing what's better about implementing in an FPGA vs a regular DSP chip. Or rather, I'm not seeing that it's any easier from the development POV - obviously it would allow me to reimlement the EDP2 chip if I were bent on doing that.

Am I looking in the wrong place? I'm trying to find examples that are just slightly above 'Hello Word', eg adding some gain to a signal or summing two signals or other very basic DSP operations. Sorry for asking such an obvious question, but the FPGA Synth Wiki seems to go from LED-blinking Hellow World examples straight into phase distortion oscillators.

Putting the question another way, suppose I have a DSP algorithm chart, what is my workflow for changing this into a digital circuit?

To me, whether you do DSP in a DSP chip or a FPGA is the same exercise. Different languages, but the processes are the same. We need to create a new sample before the sample clock ticks over.

In my view, if you are more comfortable with a specific DSP device, then use that. An FPGA is not a DSP device specifically, though it can be used that way. Some of the newer ones do have built in DSP accereration hardware, but again, these devices are also not specifically DSP. And I believe that if you wanted a contest between "best FPGA" and "best DSP" for a DSP job, you'd probably find DSP ICs that would be faster or better in some way or other. The strength an FPGA has is parallelism. If you can take advantage of that, then an FPGA can be the better platform._________________FPGA, dsPIC and Fatman Synth Stuff

Time flies like a banana.Fruit flies when you're having fun.BTW, Do these genes make my ass look fat?corruptio optimi pessima

Thanks for that remarkably clear answer. I have the full chip specification for the ESP2 and it would be a fascinating intellectual exercise to re-implement it on FPGA but ultimately I'm interested in it because I'm a fan of Dattoro's algorithms.

Concerning the free version of Vivado, you have to have WebTalk enabled for it to work:

13. WebTalk Notice, Consent and Opt-Out.

(a) Collection and Transmission of Data. "WebTalk" is a feature of the Software that electronically transmits to Xilinx various data relating to Licensee's use of the Software. WebTalk does not transmit the actual logic designs or Bitstreams processed via the Software. The types of data that WebTalk will transmit to Xilinx include: (i) constraint data (e.g., location assignments, clock and timing requirement and assignments, any constraints set via the Software graphical user interface), (ii) device data (e.g., targeted device and family), (iii) compilation data (e.g., device, memory and I/O utilization, time of compilation), (iv) design data (e.g., the number of each type of file used, intellectual property cores/LogiCORE IP cores logic functions used, and intellectual property parameterization), (v) Software data (e.g., synthesis, simulation and timing analysis tools used, and version and build of the Software), (vi) platform data (e.g., operating system, speed and number of processors and main memory), (vii) Authorization Codes data, (viii) Software errors log data (e.g., previous exit status), and (ix) help access data. Xilinx may correlate the data collected by WebTalk (primarily via the Authorization Codes data) to determine the identity of the Licensee and the User. WebTalk functions by bundling the collected data resulting from your use of the Software and writing it to html and/or xml files which are electronically transmitted over the internet to Xilinx by https (hypertext transfer protocol secure) post. WebTalk collects and maintains the last usage_statistics_webtalk file that was meant for transmission for a given design. Every new re-compilation of that given design will overwrite the previous file. If the https post transmission fails, or an internet connection is not available at the time of attempted transmission, the data is stored as an html and/or xml file. Once an internet connection is achieved by Licensee, the https post transmission will again be attempted upon re-compilation. The operation of WebTalk will not materially affect the performance of the Software.

(b) Use, Protection and Disclosure of Data. Xilinx uses the data received via WebTalk so that Xilinx can continuously improve the Software and other products, technologies and services that Xilinx offers to its customers, and also for sales and marketing email communications (for example, for selective announcement of new Xilinx products and services, distribution of marketing data, etc.). Xilinx uses reasonable efforts to maintain the privacy of the data during transmission (as discussed above) and after receipt by Xilinx via "firewalls" and other commonly available physical and technical security measures. However, due to technological limitations, the transmission of data through various internet service providers not under contract with Xilinx, and the risk of unlawful interceptions and accessing of transmissions and/or data, Xilinx cannot completely assure Licensee or Users, and Licensee and Users should not expect, that the data will be absolutely protected or confidential. If you attempt to tamper with or modify the Software in any way (other than as expressly authorized by Xilinx in this Agreement), Xilinx disclaims all responsibility for the operation of WebTalk and for the collection, transmission and protection of data as described herein. Xilinx may disclose data received via WebTalk to its corporate subsidiaries and to its authorized distributors and sales representatives (collectively, "Sales Partners"), which disclosures may be in a form that may be correlated to personally identify Licensee and Users, for their use of such data in the same manner as Xilinx might use such data. Except for disclosures to its Sales Partners, the data received by Xilinx via WebTalk will not be intentionally disclosed by Xilinx to any third parties in a form that is knowingly capable of being correlated to personally identify Licensee and its Users; however, Xilinx may share this data in an aggregate form that does not knowingly identify Licensee and its Users with its business affiliates including without limitation electronic design automation (EDA) companies with whom Xilinx has a commercial relationship including, but not limited to, Synopsys, Mentor Graphics, and Cadence. Xilinx also seeks to require Sales Partners and business affiliates to exercise reasonable efforts to maintain the confidentiality of the data disclosed to them. In addition to disclosures to Sales Partners, Xilinx may disclose personally identifiable data (collected by WebTalk and correlated to Licensee and Users), with or without prior notice, when Xilinx believes that the law requires it, in response to subpoenas or at the demand of governmental agencies, to protect its systems or business, or to respond to an emergency. Further, Xilinx reserves the right to transfer any and all data collected by WebTalk from Licensee and Users to a third party in the event that Xilinx sells or transfers substantially all of its assets related to the Software to such third party.

(c) Enable/Disable. Please note that WebTalk will collect and transmit certain data that may contain (or be correlated to reveal, primarily via the Authorization Codes data) personally identifiable information. By agreeing to this Agreement, you hereby give your consent (on behalf of Licensee and Users) for Xilinx to use and disclose this information anywhere in the world for the purposes and as described in this Agreement. Licensee or its Users may disable/enable WebTalk during installation or by editing the user preferences in Project Navigator, iMPACT, Vivado or PlanAhead or by running the xwebtalk command line utility which is located in your ise/bin/<os> folder, where os is nt, nt64, lin or lin64. Please note that WebTalk data transmission is mandatory for ISE WebPACK and Vivado WebPACK software (which are made available by Xilinx at no charge) and for alpha, beta or similar early access versions of Xilinx software products, and WebTalk makes decisions on data transmission based on the Authorization Codes used for design compilation; the only exception to this mandatory transmission is if the software is used on a machine that is not connected to the internet. If you obtained ISE WebPACK or Vivado WebPACk software (which are made available by Xilinx at no charge) and desire to have the ability to disable WebTalk, you may purchase a license to another version of the Software and not use the ISE WebPACK or Vivado WebPACK software. Versions of the Software for which Xilinx is paid a license fee contain the capability for disabling WebTalk as described herein.

The important bit is:

Please note that WebTalk will collect and transmit certain data that may contain (or be correlated to reveal, primarily via the Authorization Codes data) personally identifiable information. By agreeing to this Agreement, you hereby give your consent (on behalf of Licensee and Users) for Xilinx to use and disclose this information anywhere in the world for the purposes and as described in this Agreement.

Meh, they're not claiming ownership of your IP. I got a call from the marketing department of Cypress (PSOC) but they just wanted to know what sort of things I thought their chip would be good for, how many units a commercial product of that kind might sell, what was my level of experience etc. I don't think you ought to be concerned about if you don't have a bunch of capital invested in product development/IP.

There are only 2 documents I was able to find on www.digilentinc.com, those are a schematic and a features document. I will download the Xilinx Zynq chip docs from the Xilinx site.

The Digilent site says (in the product description) that there is a linux distro that will run on it. From the small amount of the docs I've looked at, it appears the it can boot from a microSD card (which I need to get). There may be other ways to boot it as well.

I have a feeling that this will take a few days to get "hello-world" stuff running, but it should be fun and it will keep me off the streets._________________FPGA, dsPIC and Fatman Synth Stuff

Time flies like a banana.Fruit flies when you're having fun.BTW, Do these genes make my ass look fat?corruptio optimi pessima

I agree, the videos are very well done. Despite the fact that the processing system can be tightly coupled to the programmable logic, however , it can be run independently from the programmable logic block so maybe just getting some "hello world" stuff may not be as far away as you might think. It should be interesting how well the Vivado design environment and flow works with the development board you purchased Scott.

I have not downloaded the Vivado design suite yet nor have I worked with it so I suppose you will be our testing ground

Oh yes, and that was one of the things pointed out in the videos - you don't need to use either of the ARM cores if you don't need them.

Though when I see those two juicy 650 MHz 32 bit ARM cores (with floating point), I start to think about how I can make an instrument using those as well as FPGA fabric for accelerator logic. I think that just one of those ARM cores all by itself would probably make a nice synth.

Anyway, I need to scrounge up a USB cable since nothing but the board comes with the order. It's a standard type USB cable, nothing special about it for programming the board.

I'll probably start out with ISE 14.x since that is required at minimum. Just a LED blinker... I don't know if ISE can deal with the ARM cores at all, I'll find out though. ISE is probably messier than Vivado. I've downloaded the installer, but haven't yet run it._________________FPGA, dsPIC and Fatman Synth Stuff

Time flies like a banana.Fruit flies when you're having fun.BTW, Do these genes make my ass look fat?corruptio optimi pessima

I've started a project in ISE 14.6 which supports the zynq 7010 IC. However, with ISE, one needs a UCF file to connect IC pins to named resources that will be used in the design. So far, I can't find a "master UCF file" that describes all of the board's connections.

Some of the search hits indicate that UCF is now obsolete for Vivado - but I'm not using Vivado yet and ISE requires the file. I may have to try Vivado if I can't get anywhere with ISE 14.6.

Well, Digilent is responsible for creating a master UCF - they have it for other boards, but I think this one being so new has some details yet to be finished. Another thing that is missing is the file package required for creating the linux boot on the micro-SD card. Their documentation says that they will be the supplier of that. Not sure why the UCF and the linux files aren't there yet - I would have thought that those are required to do the testing that I hope they did. I'd have appreciated at least a UCF so that I can play with the FPGA without the ARMs for now. I've not looked for reference designs yet, I don't have the USB cable to power/program it yet anyway..._________________FPGA, dsPIC and Fatman Synth Stuff

Time flies like a banana.Fruit flies when you're having fun.BTW, Do these genes make my ass look fat?corruptio optimi pessima

I borrowed a USB micro B cable from my son and was able to run the demo stored in the QSPI flash. Stored there is a tiny bootable Linux. When I plugged the cable in, the board looked like it was doing something with activity on the USB LEDs. So I looked at the ports and there was a COM port that wasn't there before. I ran hyperterminal and connected to the port at 115.2 kbaud, 8 bits, 1 stop, no flow control and I got a ZyBo> prompt. I can see that telnetd, ftpd and httpd daemons are running. The Linux file system as booted consumes about 4.6 megabytes of DDR3 SDRAM. Within 'top' I can see that about 25 megs are used when Linux is running. There are also two commands for playing with LEDs and slide switches. write_led 0xNN writes the bits of NN to the LEDs (0x0F turns them all on) and read_sw reads and displays the 4 bit number represented by the slide switches. There is a tiny web server (httpd) that I was able to connect to with Firefox. I also used FTP to copy a jpg image to the server, I used vi to edit index.html so that it would display the image and that worked too. I had to dig around to change the IP address from it's default of 192.168.1.10 to 192.168.0.10. I used the command ifcfg to reconfigure the network interface.

Wow, fantastic news !!! I can see from the "TTY" ports output that Linux is loading many of the usual suspects ! You can also try a SSH session with Putty and wee if that service is running. It usually is in Linux. May ask you for PW's.

Did you see if a video adapter block was created and enabled? Check for output on your HDMI or VGA ports ...

Wow, fantastic news !!! I can see from the "TTY" ports output that Linux is loading many of the usual suspects ! You can also try a SSH session with Putty and wee if that service is running. It usually is in Linux. May ask you for PW's.

Did you see if a video adapter block was created and enabled? Check for output on your HDMI or VGA ports ...

In any event, it's ALIVE !

Bill

Yes, I noticed something about SSH as I rummaged through the file system. I think it's the dropbear process. Anyway, I did connect using SSH and yes it asks for a username and password. Since the only account configured (as far as I can tell) is root, I entered root as the username. Then since I had no documentation to work with, I thought ZyBo, Xilinx, Digilent and Zynq might be passwords - all failed. So I guessed 'root' for the password - and that worked!

There was also something about video in my rummaging, so I will indeed (later today) try a VGA monitor (no HDMI equipment down here) and see if there's anything on it. There's no keyboard connector on the board, so I can't imagine what would be displayed there except maybe some hello-world sort of thing.

Looking in the bin subdirectory, there are some interesting command files including gzip and rpm. Apparently, this Linux seems derived from Red Hat - now I see why I feel comfortable in there... Heh - found sendmail... Most of the common command line utilities are there.

It's been great fun playing with this even in this minimal capacity. I've had to dust off my Linux command line skills. I've never had an embedded Linux system before, so this tiny Linux is a new experience and lots of fun. One of the best things about it is that I can do dangerous stuff in there and if I clown it up, I just power cycle and a few seconds later it's running again all healed._________________FPGA, dsPIC and Fatman Synth Stuff

Time flies like a banana.Fruit flies when you're having fun.BTW, Do these genes make my ass look fat?corruptio optimi pessima

Two more files appeared on the Digilent site for the ZyBo. They are the master UCF file and the board description files needed by Vivado.

Today, I got those files and used the master UCF to build two small test designs. The first is a simple counting LED blinker using Verilog statements. The second is a cylon LED display using a PicoBlaze embedded microcontroller. Both work as expected. The PicoBlaze design was interesting because I started with a design for a Spartan-3A device. The old design used version 3 of PicoBlaze which was not prepared for the block RAMs that are in the Zynq. I found version 6, downloaded that and modified the source code to accomodate it. It's a little different, but the docs are good so not too hard to get it working. The new embedded processor is running with the system clock of 125 MHz. Version 6 is spec'd to be able to handle up to 240 MHz depending on the device. That is a significant boost in performance over version 3 which tops out at 50 MHz._________________FPGA, dsPIC and Fatman Synth Stuff

Time flies like a banana.Fruit flies when you're having fun.BTW, Do these genes make my ass look fat?corruptio optimi pessima

You cannot post new topics in this forumYou cannot reply to topics in this forumYou cannot edit your posts in this forumYou cannot delete your posts in this forumYou cannot vote in polls in this forumYou cannot attach files in this forumYou can download files in this forum

Please support our site. If you click through and buy from our affiliate partners, we earn a small commission.