Intel’s Ice Lake Processors Have Taped In At The PAO Second Generation 10nm Process

Intel’s official twitter account has tweeted that Ice Lake has been taped in at the 10nm process. This marks a milestone in Intel’s product roadmap and means that the second generation 10nm processors are on track for their reveal in 2018. To those who aren’t aware, Intel’s first generation 10nm processors are code-named Cannon Lake and are expected to be launched later in 2017.

Intel’s 10nm based Cannon Lake on track for 2017 release – Ice Lake processors have taped in on the 10nm process

Intel modified their tick-tock schema last year and converted it into a PAO schema (tick-tock-tock) which basically includes 1 node shrink and 2 architectural optimizations as opposed to 1 node shrink and 1 optimization. 14nm was launched with Broadwell as the “Process” portion, followed by Skylake as the “Architecture” portion and concluded by Kabylake as the “Optimization” portion. This means that to stay on-track with their new schema, they must introduce 10nm based processors before the year is over.

This is classically achieved by introducing mobility SKUs near the end of the year since they are one of the easiest to fabricate and usually have enough yield to start shipping in bulk. Following the same logic, we can expect Intel to unveil the first 10nm Cannonlake mobility processors sometime in 2H 2017. At the same time, Intel is on track to unveil their KabyLake based 14nm Coffeelake processors in 2H 2017 as well (its a hot-mess of code names, I know) . These will be based on the optimized 14nm+ process and will have more than 4 cores (Kaby Lake is currently limited to only quad core variants as our more diligent readers might recall).

So when Intel says their 10nm Processors have taped-in, what does that mean?

Well, a tape-in is not the same as tape-out. A tape out is the last stage of IC design process in which the final design is sent to the fabrication facility to be, well, fabricated. It essentially means that the designing stage is over and the production stage has begun. Fun fact: Its called a tape out because in the past, magnetic tapes were used to store all the ASIC design files which was then sent to the fabrication facility.

A tape in is a relatively newer term that is reserved for complicated SOCs that require more than one IPs and designs to be integrated. You can think of it like this: the various components of the SOC have been finalized by their low-level design teams and handed over (taped-in) to the top level design team which will basically finalize the top level layout and design of the soc before sending it to the fabrication facility (taping out).

Area scaling of Intel’s processes as compared to TSMC, on a physical basis.

This is a key milestone in the process and means that the brunt of the work required for the Ice Lake processors has been done. It also implies that the first generation 10nm products are much further down the assembly line and on-track for their 2017 release. The company still holds the industry advantage in terms of process that they have always enjoyed (assuming you don’t fall for the marketing names that other foundries employ which are not indicative of the physical process) and appears to be confident in its promised delivery of 10nm products.