Multi-core Network-on-Chip System for Multimedia Applications

Network-on-chip is an approach of designing the communication
subsystems between intellectual property cores in a system on
chip. The System on Programmable Chip (SoPC) is an FPGA device that
can accommodate multiple CPU cores, memory and a vast range of
peripherals. Network-on-chip applies to the networking theory and
communication methods to on chip communication. It brings notable
improvements to over conventional bus and crossbar
interconnections. Its main advantages include improved scalability
of system on chips, improved power efficiency of complex system on
chip to other designs. The complexity of systems on chip is
steadily increasing and this has resulted in more and more
resources integrated on a single chip. Current standard on chip
communication structures which include shared buses among others
cannot provide the scalability required to connect all of these
resources and this is where the concept of network on chip comes
into place. With today's growing need for high capacity in
smaller size, high performance, and cheaper electronic systems has
led to more complex systems with higher demands. The need to
integrate multiple intellectual properties onto a single chip has
therefore increased and traditional shared bus communication cannot
scale with this increase in system on chip design. Traditional
shared bus communication also reduces the performance in multiple
core system on chip since the possibility for each core to take the
bus master before it can transmit or receive data is
reduced. Therefore, in an interconnection network structure which
is adopted by network on chip, interconnected routers are the
spines of the whole system. The performance of the network depends
mainly on the performance of these routers. There are a number of
significant factors which determines the working mechanism of a
router and its performance. These factors include switching
strategy, routing algorithm, flow control mechanism and network
topology.