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AR# 68163

High Speed SelectIO Wizard - Logic might reset while waiting for DLY_RDY or VTC_RDY during the reset sequence

Description

When using High Speed SelectIO Wizard (HSSIO), the state machine can restart while waiting for DLY_RDY or VTC_RDY to go high.

The state machine has a timer to reset the state machine when the reset state machine is idle. When combining multiple HSSIO cores, there might be occasions when the timers incorrectly time-out.

Note: this Answer Record should not be viewed in isolation. For all other known issues and to see what version of Vivado / High Speed SelectIO Wizard these issues have been resolved in, please refer to (Xilinx Answer 64216)

Solution

This issue is resolved in the 2016.3 version of the High Speed SelectIO Wizard.

For designs in Vivado 2016.2 and earlier versions, the reset state machine can be fixed by editing the Verilog RTL for the reset state machine.

The reset state machine RTL that causes the reset sequence to restart is defined in rst_scheme.v.