Dr. Uday Mitra, VP and CTO for the Etch Business Unit and Patterning Module at Applied Materials, discussed materials enabled solutions for edge placement error (EPE) and logic scaling at the Nikon symposium. Mitra opened his talk by showing how materials-enabled solutions are already benefitting NAND, DRAM, and logic devices (Figure 1A). In the case of NAND, materials solutions have supported the transition from 2D to 3D technology by enabling the uniform deposition of increasing numbers of thinner (oxide/nitride) pairs with low stress, highly selective, and uniform etch processes (Figure 1B). For DRAM, spacer-based patterning techniques such as self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), and self-aligned litho etch (SA-LE), as well as other self-aligned structures have enabled device scaling. In the case of logic technology, Mitra reported that for the last four device generations, the gap between lithography resolution and minimum pitch requirements have been bridged by materials innovations.

Resolution is no longer the most critical factor limiting scaling. Now the limiting factor is EPE, defined as the movement of an edge in any direction, which results in vertical misalignment between the process layers. Mitra noted that while today’s chips have up to 100 billion vias, 1 via off typically results in a dead chip, and partial misalignment impacts chip reliability as well. Litho, etch, and deposition processes all contribute to the EPE budget. There are a multitude of potential sources within each area, including overlay, CD uniformity, and stochastics in the case of EUV lithography (Figure 2A).

Figure 2A. Many possible sources of EPE (left image). Figure 2B. Materials co-optimization and square spacers can be used to address EPE issues.

Mitra described that while a conventional SAQP process can lead to problematic pitch walking, materials co-optimization methods and square spacers can be used to address EPE issues like this. The co-optimization of the film deposition and etch process for a square spacer would consist of first identifying suitable high quality films for the mandrel/spacer from a broad portfolio of possible materials and techniques, then optimizing etch for selectivity and local uniformity control, and finally eliminating multiple steps of etch/deposition/metrology with holistic tuning (Figure 2B).

The EPE margin is defined as the current EPE minus the maximum allowable EPE, with the maximum allowable EPE equaling only ¼ of the critical pitch. Unfortunately, EPE increases with smaller nodes as the litho alignment errors and process variation stack up (Figure 3A). Although EUV helps with resolution, it only marginally improves EPE. Mitra emphasized that self-aligned schemes are imperative to address this challenge. He reported that the path to minimized EPE is through fully self-aligned patterning, but this requires new materials and highly selective etch removal techniques. Applied Materials’ SelectraTM Etch system achieves extreme selectivity using a radical-based etch, with ion filtering of the plasma, thereby enabling damage-free, extreme selectivity etch without polymers. Mitra reported that SelectraTM delivers atomic level precision enabling FinFET’s ≤ 10 nm, as well as advanced gate-all-around (GAA) architectures (Figure 3B).

Multi-color patterning is a key enabling technology for many self-aligned schemes, and a self-aligned gate contact (SAGC) generated using multi-color patterning was shown. The gapfill included a dielectric film matrix of four materials, with highly selective etch for each material, a highly selective metal/liner recess, and multi-material CMP polishing with ~nm uniformity control (Figure 4A). Mitra showed a selective etch matrix comparison for a self-aligned gate contact that clearly highlighted the importance of materials and etch selection for SAGCs (Figure 4B). He reported that there has been rapid adoption of materials-enabled self-aligned structures to address EPE issues, and cited examples from IEDM 2017 of a self-aligned gate contact from C. Auth of Intel as well as a “fully aligned via” from B. Briggs at IBM.

Advanced nodes pose tremendous scaling challenges for all device types, and EPE has become the top limiting factor. Lithography-based solutions alone are insufficient, so self-aligned structures are vital to solving very tight EPE margins. Mitra summarized his insightful presentation reiterating that as the industry is rapidly transitioning to self-aligned structures, materials-enabled solutions are increasingly crucial for continued scaling success.