Hi Max - you are unsure of 5, 10, or 20 years. I agree, the crystal ball is mucho muddied right now. But we as an industry had better figure it out fast. With the economics flat or nearly flatted at 28nm, only a very few will see a need to go lower (for some other reason than cost scaling). I wonder about the slowing of innovation from this bottoming out as well. However, an aspect that may help us do this sooner rather than later: since 28nm will be around for a long long time, being the bottom of the cost bathtub, it is the perfect platform to try out monolithic 3d techniques (and any other ideas out there), especially for SoCs. The NAND folks are already getting there.....

Monolythic GaAS combining optics and electonics on one die. In development for 30 years and now moving from R+D to commercialization by DR. Talyor (U.Conn Tech Dean, PHD) at POET Technologies.

Many X clockspeed performance of Si (I am not exaggerating) , up to 70% less power of current SI models. Can be built with existing Semi fab equipement. Little known company that is "coming out to the wolrd" exploding with 400% stock performance this year.

This post may come off as a pump mail (full discolure, I am a shareholder), this said - I highly encourage you to check this out - if only for your interest.

BAE verified technology. NASA funded (previously), design kits are built..company now turning into a fabless licensing play (see ARM), with first partner being announced within months.

It will be nice to see TSMC or Intel showing better cost of transistors. What I have seen out there is density chart which is actually do not result in reduce transistor cost due to the higher wafer cost. BUT this is well known by now, the real problem is the SoC costs !, it will be nice if you really read the blog before posting comments. Please look again at the SRAM density chart from the recent ISSCC 2014. If effectively the density increase from 28nm to 16nm is about 10% than the SoC cost will much higher at 16nm. Unless you can show data that is different you need to admit that 28 nm costs would be the cheapest for SoC for a while. And you are advise to read a previous blog published by EE Times " Why 450mm Will Be Pushed-Back Even Further" http://www.eetimes.com/author.asp?section_id=36&doc_id=1321239& , which provide additional support to the problem with embedded SRAM scaling. So regardless if you like monolithic 3D or not the 28nm is the last node of Moore's Law.

The industry is in a deep dodo -- 450mm (infinitely?) delayed, EUV (infinitely?) delayed, and even pure logic transistors cost is not dropping anymore. One can believe Intel's charts if one chooses to but, clearly, their life is at stake over this question, so they must be optimistic or short their own stock. Everyone else's data shows level cost at best, somewhat up realistically.

But this blog brings the other whammy to the table -- memory shrink ... that barely happens anymore. Which means that complex chip cost below 28nm will go up. Significanly.

You can still use below 28nm even if the cost of the transistor is the same.

But you would see die sizes shrinking and total transistor counts staying the same to keep margins the same. Or they could increase prices (not likely!). Nvidia 20nm and Intel 16nm parts are coming soon. They will confirm if 28nm was the last cost effective node.

Because those going there have a use case that they believe requires it, and for which they believe their customers will be willing to pay enough to let them do it profitably.

The question going forward will be what applications will require going below 28nm, and whether customers will be willing to pay what below 28nm parts will cost.

Moore's Law has historically meant semiconductor components would be progressively smaller, faster, and cheaper. It's increasingly apparent that cheaper will no longer be part of the equation, and the new paradigm will be smaller, faster, and more expensive. We are all in the process of finding out what that will mean for the semiconductor business.

thank you @DMcCunney...looking forward to see who is willing to pay for faster, smaller and more expensive...let's examine those in more details: faster is probably only marginally faster as chip delays are dominated by interconnect lines not intrinisic transistor speed...smaller doesn't really matter much unless the application is constrained in space like smartphone...and noone likes more expensive so I am not sure who will be willing to do faster, smaller and more expensive afterall...Kris

Good point @tpfj...we need to add power dissipation to this consideration...so "faster, smaller, less power hungry and more expensive"...maybe addition of lower power tiltes some applications towards using less than 28nm processing

@krisi: I am not sure who will be willing to do faster, smaller and more expensive afterall

I'm not either.

We were already bumping into speed limits as paople trid to push CPUs faster. (There was an amusing series on a tech site as the editors successfully pushed a Pentium to 5ghz, using liquid nitrogen to cool it. It was a "Kids, don't try this at home!" story.) Aside from the technical challenges in pushing the chips faster, you had the parallel challenge of how to handle the heat faster CPUs generated.

Smaller still matters, and not just in handheld platforms like smartphones, with System On a Chip the promised land.

But the question is always "What will the customer pay for?"

The industry is already segmented, and there are "commodity" markets where price is the driver of the purchase decision and higher level niche markets where price is only one factor and more can be charged. (And an industry challenge is that everything eventually becomes a commodity.)

I'm sure there will be applications for that sort of technologies, and markets willing to pay what it will cost to produce. The question is whether the markets will be large enough to fund the R&D investments needed. You get your R&D funds from the revenues you get by selling products to your customers, and the size of your market and the total revenues you can generate will place hard caps on what you can devote to R&D.

The old Chinese curse is "May you live in interesting times". Well, we are.

EUV is now being considered for 7 nm insertion with double patterning (10 nm insertion decision point past). I am not sure if that is an improvement to the cost curve. The source power target is not fixed, has to keep moving up.

Broadwell is right around the corner. Lets see what their die sizes are at 16nm. Perhaps SRAM amount will stay the same to compensate for poor SRAM scaling.

Intel is a good example to use since they don't need to take a margin hit in desktops and and servers. If 16nm really costs the same as 22nm they will have to reduce the die size by 50% to give the same margins.

22nm vs 28nm is just margin case because no need for double patterning yet(according to intel). Why hasn't TSMC just migrated to 22nm without it ? Or is really hard to make 22nm work with single patterning ?

It's a good question, it might be just to differentiate from Intel's 22 nm. But the aggressive DP cost might be too high to be tolerated by customers, maybe they'll go for 16 nm to get FinFET benefit (if any) as well.

Unlike the foundries we don't really know enough about Intel to analyze the transistor or their SoC costs. We do know that the for the foundries 28nm is the last node of Moore's Law. As to Intel it might help you reach your own conclosing if you read our blog: Intel vs. TSMC: an Update <http://www.monolithic3d.com/2/post/2014/01/intel-vs-tsmc-an-update.html>

This whole article and discussion is prettty menaingless without Intel. There is no "wall" for Intel at 28nm whatsoever. The problem is with the other foundries who do not have the capital needed for follow Intel not to mention to ecatch up with their 2 node advanatge in the foreseeable future. It seesm to me that for now Moor's law is alive and well at Intel, but not so much at TSMC, GloFo, STM, tec.

Intel does have volume to help pay off, but still there are some mixed signals regarding 14 nm. It's the first node to have such signals, particularly from its former 14 nm designated fabs. Maybe not a wall, but more like an obstacle in the course.

Currently ,cost at 22nm at intel is more expensive than 28nm(at least according to fpga compnies who sell such silicon).

Also intel will lose a lot of stock market value if it appears that moore's law is dead, since better manufacturing is their only or at least most of it's core value today in a world that is shifting to ARM.

The reason is that 28nm is a planar transistor, 22 (20) can't be panar it has to be FinFET for many reason. TSMC decided t ojump to 16(14) with FinFET. There will b esome 20nm -planar but doesn't have an advantage.

B. Below 28 nm the embedded SRAM bit cell scale very poorly. Just to keep with 2X density improvement per node, at 14 nm bitcell area should be less than 0.04 µm². The published data from TSMC and Samsung shows ~0.07 µm². Accordingly SoC build at 14nm would cost much more than the one at 28 nm.

@Max. I agree with you about monolythic 3D IC's becoming mainstream. It certainly seems like the logical choice and the ~28nm "wall, if you will, will drive this technology relatively quickly. My crystal ball indicates that Fab 42, currently on hold, will be completely retooled to eventually accommodate carbon nanotube technology (likely a hybrid). It won't happen in this decade and maybe not until well into the next. Meanwhile the industry is in for seismic changes. I'm glaad to be nearing the twilight of my career in this industry. I see lots of pain ahead.

Nothing except semiconductor based technology has gotten cheaper and better for so long a period of time. We have just gotten used to it.

If semiconductors start getting more expensive per transistor, innovation will have to take a new direction. Why does loading an OS take multiple GB of memory? Because memory is cheap and bloated software is the path of least resistance.

Never underestimate the ability of really smart people to figure out a way to make more from less - as long as there is money to be made in doing so...

Moore's Law stopping at 28 nm will cause some shock waves in our industry but it is far from 'doom and gloom'. The collapse of number of vendors from 50 to less than 5 due to the escalating costs associated with dimension scaling was not a happy trend. Now we hopefully see the playing field get broaden again with growing number of vendors and growing diversified technology innovations.

SHANGHAI, Jan. 26, 2014 /PRNewswire/ -- Semiconductor Manufacturing International Corporation ("SMIC"，NYSE: SMI; SEHK: 981) , China's largest and most advanced semiconductor foundry, announced today that its 28nm technology has been process frozen and the company has successfully entered Multi Project Wafer (MPW) stage to support customer's requirements on both 28nm PolySiON (PS) and 28nm high-k dielectrics metal gate (HKMG) processes. Over 100 IPs from multiple third party IP partners as well as SMIC's internal IP team are prepared to serve various projects from worldwide design houses that have been showing interest in SMIC 28nm processes.

"The first SMIC 28nm MPW shuttle included both 28PS and 28HKMG related customer products for verification, which was already launched at the end of 2013 as planned," said Dr. Shiuh-Wuu Lee, Executive Vice President of Technology Development of SMIC. "By taking more MPW shuttles in 2014, we will continue to take more positive steps to strengthen and diversify our technology offerings and meet customers' growing demands on both advanced and differentiated technologies."

Sang Kim, I think you are quoting the cost of bare wafer which is far less than what it costs to fabricate. And for your reference 14nm FDSOI uses a Si thickness of 6nm. That's all you need for a gate length of about 20nm that fits the pitch and by the way is far less than what FinFETs are using. Even at 10nm you do not need to scale the gate length. All needed is self-aligned contact, a card Intel has already played at 22nm.
At the end Moore's low has nothing to do - at least to the first order - with the gate length. Regardless of transistor choice, whether bulk planar, FinFET, or FDSOI, each transistors need three contacts and routing metals. Pattering of those contacts and metal lines with enough design flexibility is what forced the industry to use multi- pattering (4 masks just for contact vias at 20nm). Soon we'll need up to 4 masks to print active regions, at least 3 to define gate, plus one more for each gate length, 5-6 for contacts, 2-4 for each via, and 3 for dense metals. FinFETs complexity just adds to the cost (both development and design). And its cost adder is by no means close to the 2% number that Mr Bohr quoted.

1) Moore's law was based on the observation made on bipolar IC's. By your argument, it was fulfilled the day CMOS was born.

2) Cost of the bare Si wafer is just a fraction of the total fabrication cost. A cost difference of about $400 between Si and SOI wafers is well absorbed by reduction in the number of masks. I'll asure you, STM is one of the most cost-sensitive companies and would not do FDSOI if it would cost more. On the other hand, Intel is known for large margines. So, when Mr. Bohr claims bulk FinFET adds only 2% to process cost, I put a big question mark there.

3) Bulk Si technology did not stop at 28nm. There is bulk planar technologies by both Samsung and TSMC at 20nm. IMO, fabless companies where better off going to 20nm than getting distracted by the lure of FinFET, just to waste more than a year of design and finally figuring out things are not as rosy as the powerpoints show.

4) Contrary to all claims, I do not see big advantage at product level by FinFET products that are out there. The original claim was FinFET allows reduction in operating voltage of 200mV at the same performance, a 40% drop in active power just from FinFET (let alone natural ~30% reduction in power from node to node). This was never seen in products.

5) There is absolutely nothing in semiconductor physics that says 5nm is the minimum channel thickness.

6) Technology node is note represented by gate length. A 14nm node does not mean 14nm gate length. For all I see from publications, Intel and TSMC FinFET are using a gate length of 30nm or longer (up to 50nm for very low leakage devices), while FDSOI is at 25nm or smaller.

7) IBM is a member of the SOI Industry Consortium: http://www.soiconsortium.org/about-us/list-of-members.php

Promoting FDSOI is only one aspect of the consortium. SOI market spans far more, including RF, MEMS, etc.

8) IBM did not exit FDSOI. What will be 14nm FDSOI offering by ST was a joint development that started at IBM facility and was transfered to ST's site. This is very similar to other joint developments IBM had done with ISDA partners in the past (including the 28nm bulk planar that powers iphones). The fact that IBM decided to use SOI FinFET for its own server products is also very similar to IBM's use of PDSOI at 45nm, 32nm, and 22nm, despite the fact that IBM developed both bulk and PDSOI technolgies at each node.

9) S3S is an IEEE conference. IEEE decided to merge SOI conference, sub-Vt confernce, and 3D, because the committee beleived there is a strong harmony between these topics, despite covering seemingly different fields.

1) Moore's law is a bout cost, not about gate length, nor performance, nor leakage. Those are historically governed by Dennard's scaling and we can argue whether it still holds or not. But the discussion here is about the cost. As I pointed out earlier, Moore's law was made in the bipolar days. It was extended through NMOS and later CMOS days because they integrated chips continued to made at a lower cost per component.

2) ST demonstrated U8540 chips two years ago and it was shown to drop total power by 35% copared to 28nm bulk. Ironically ST-Ericson was disintegrated shortly after. So there is no product in the market. ST had continued making test chips for a handful of customers and all those that I am aware of had seen the benefit. However, ST does not have the fab capicity and said they are announcing the fab partner soon. So there is not such thing as ST "is not able to manufacture". There is a bog difference between "not being able to" and "not doing".

3) I have not seen any data suggesting 20nm bulk had leakage issue. Several companies in fact made the announcement that they will design in 20nm as their next node after 28nm. Others complained that there is not enough performance gain and would like to go directly to FinFET.

4) When talking about the FinFET performance what is the reference points? As for the leakage, their SoC paper used devices at 108nm pitch to show ULP leakage -- as opposed to 90nm pitch for other devices, which means these are roughly at Lg = 30+18nm = 48nm! I am confident you can get the same level of the leakage in a bulk planar device with the same gate length. As for the performance, both Intel and TSMC published data normalized to the footprint and not the actual device width. This is actually how TSMC claims performance better than Intel. While we can argue if this is thr right choice or not, first of all none of them were transparent in reporting numbers. Second, the higher current comes at the expense of higher capacitance, so it is not clear if there is net AC performance. Intel showed a RO delay of 13ps at VLSI'12 at 0.7V. That device would be about 10ps at 1V. Their 45nm node at the same leakage was 5ps! TSMC even did not show this. They showed a TCAD simulation of aggragate of what they claim to be representative of circuit performance.

5) It's been a while that node number has nothing to do with gate length. All discussions predicting requirements of Lg vs thickness are irrelevant here. BTW, quantum confinemnet is nothing to be scared of. It's already in play even in buld devices (you have a triangular quantum well vs the square shaped in FinFET). The inversion layer thickness is only 2-3nm in any advanced device. That's all you need to make a transitor. Yes, variability is a problem but it kicks in at much thicker films, and unfortunately FinFET does not have any magic to offer.

6) Please read TSMC's paper again. Minimum gate length is 30nm -- and so is in Intel's although they decided to call it 26nm at a later point. Their low leakage device is also at 50nm gate length. As I mentioned above, technology node has nothing to do with gate length.

7) As I mentioned in my previous comment, IBM developed FDSOI along with its partners and transferred it to partner sites. There is no skipping here. This is very much same as the 28nm LP devices that powers iphones today. It was develped as a part of common platform and transferred to parners sites. BTW, ST has a paper in the upcoming VLSI. Channel length is not 14nm and channel thcikness is 6nm. It has the same gate pitch and metal pitch of what the FinFET camp calls 14nm.

8) I invted you to attend the conference in October in the bay area and you can see if there is harmoney or not. I beleive the organizing commettees of the three conferenced agreeded there is enough overlap to merge those together. But you are welcome to attend and comment if you think otherwise.

"Moore's law is the observation that, over the history of computing hardware, the number of transistors on integrated circuits doubles approximately every two years. The law is named after Intel co-founder Gordon E. Moore, who described the trend in his 1965 paper."

I think performance would be a better yardstick, but we have to stick to number of transistors. 3D ICs will keep it going a bit longer, maybe.

Bunnie Huang, in his keynote today, quoted from this article and said it was a really interesting read. That's why it's back on the EE Times home page. Great keynote today. Now that Moore's Law is slowing down, it's better for smaller companies that want to spend more time on hardware and software design and optimization rather than having to plan for the next few months when Moore's Law was going to make their product obsolete. He said Moore's Law favored bigger companies that could have several teams working on next generation simultaneously.

The last earnings meeting they were saying 24 NXT-1970 multipatterning tools in Q1 alone, while hoping to squeak out a few more NXE:3300 EUV this year. Two things boggle me: 1) why continue with EUV if multipatterning is already a good business for ASML, and customers are paying (including the same as paying for EUV)? and 2) why continue the traditional Moore's Law shrink if the traditional cost reduction model is not viable anymore (due to new lithographies, high-k, fins, future channels, etc.)?