FPGADesignExpert(ISE)

This 3-day comprehensive hands-on workshop is specially designed for designers new to FPGAs design or programmable logic. Beginning with the architecture of Xilinx FPGA, the workshop will first provide the essential knowledge required to implement a design successfully using the ISE software tools. The first part of the workshop will give you a headstart on not just a fast design turn, but an elegant design as well. The second part of the workshop shall focus on how to create more efficient designs to enhance overall performance. You will learn how to create a faster design, fit your design into a smaller FPGA or a lower speed grade, thereby reducing your system cost and development time. Plus, you will configure your personal evaluation board using Xilinx in-systemconfiguration software, which you may take with you after the workshop. Ultimately, the workshop objective is to groom you into a FPGA Design Expert.Level- Fundamental to Intermediate

Duration3 days

Who Should Attend Digital and ASIC designers who are interested in FPGA design training, and have a working knowledge of HDL (VHDL or Verilog) and who are new to Xilinx FPGAs

Prerequisites

Working HDL knowledge (VHDL or Verilog)

Digital design experience

Why this training pays huge dividendsAfter completing this training, you will be able to:

Take advantage of the primary features of the 7 series FPGAs

Use the Xilinx Project Navigator to implement and simulate an FPGA design

Read reports and determine whether your design goals were met

Use the Clocking Wizard to create MMCM instantiations

Use the I/O Planner to make good pin assignments

Use the Xilinx Constraints Editor to enter global timing constraints

Describe the architectural features of the 7 series FPGAs

Create and integrate cores into your design flow by using the CORE Generator™ software system

Describe the clocking feature s of the 7 series FPGAs and how they can be used to improve performance

Increase performance by duplicating registers and pipelining

Increase system reliability by adding an appropriate synchronization circuit

Describe different synthesis options and how they can improve performance

Lab 1: Xilinx Tool Flow – Create a new project in the ISE Project Navigator and use the ISE Simulator to perform a behavioral simulation. Implement the design using default software options and download to the demo board.

Lab 2: Clocking Wizard and Pin Assignment – Use the Clocking Wizard to customize a DCM and incorporate your clocking resources into your design. Use the PlanAhead™ tool to assign pin locations and implement the design using the Project Navigator in the ISE software.

Lab 3: Pre-Assigning I/O Pins Using the PlanAhead Tool – This lab introduces the basics of making good I/O pin assignments with the PlanAhead tool. Perform Weighted Average Simultaneously Switching Output (WASSO) analysis to avoid ground bounce and use the Design Rule Checker to follow the I/O banking rules.

Lab 4: Global Timing Constraints – Enter global timing constraints with the Xilinx Constraints Editor. Review the Post-Map Static Timing Report to verify that the timing constraints are realistic. Use the Post-Place & Route Static Timing Report to determine the delay of the longest constrained path for each timing constraint.

Lab 5: Designing with FPGA Resources – Create block RAM and clocking FPGA cores using the CORE Generator™ tool. Instantiate these cores and other clock resources and implement the design.