6 Digital Logic Technologies Programmable Logic Array PLA: Based on the idea that logic functions can be realized in sum-of-products form. A PLA comprises a programmable collection of AND gates that feeds a set of OR gates, configured to realize any sum-of-product functions of the PLA Inputs 6

8 Digital Logic Technologies Programmable Array Logic PAL: In a PLA both the AND and the OR planes are programmable. Historically the programmable switches presents two difficulties for the manufacturers, they are hard to fabricate and reduced speedperformance. 8

9 Digital Logic Technologies Programmable Array Logic PAL: These Drawbacks led to the development of a device were only the AND Plane is programmable while the OR plane remains fixed. This devices were called the PALs. 9

11 Digital Logic Technologies Complex Programmable Logic Devices CPLDs: CPLDs were created as a substitute for the PLAs and PALs which are useful for implementing a wide variety of small digital circuits. This small digital circuits will be limited to a relatively small amount of inputs and outputs. 11

12 Digital Logic Technologies Complex Programmable Logic Devices CPLDs: For implementing more complex circuits, either multiple PLAs or PALs can be used or a CPLD. A CPLD comprises multiple circuit blocks on a chip, with internal wiring resources to connect the circuit blocks. Each circuit block is similar to a PLA or a PAL. 12

14 Digital Logic Technologies Field Programmable Gate Arrays FPGAs: Is a programmable logic device that supports implementation of relatively large logic circuits (Much more than 20,000 gates). FPGAs, does not contains AND or OR planes as the CPLDs. Instead, FPGAs provide logic blocks for implementation of the required functions. 14

15 Digital Logic Technologies Field Programmable Gate Arrays FPGAs: They contain tree main types of resources: Logic Blocks I/O blocks for connecting to the package pins and interconnection wires and switches More sophisticated state of the art FPGAs also contain: Complex I/Os Memories Analog Custom laid out processors 15

17 Digital Logic Technologies Application Specific Integrated Circuit, ASICs: Chips that are design using state of the art VLSI technologies and that are tailored to some specific needs (or applications). In the 1980 s Application Specific Integrated Circuits (ASIC) designs were focused to meet time-to-market and customers specific requirements. 17

19 Digital Logic Technologies Standard Cell Design: Is a design methodology where a library of macros (cells), which are predefined and pre-laid-out, is provided by a vendor. The user designs his/her circuit with these cells (logic function blocks) resulting in a schematic defining the interconnects among selected cells. 19

21 Digital Logic Technologies Gate Array Design: The Gate Array design uses a custom interconnection pattern of an array of uncommitted logic gates. These are called Gate Arrays. Wafers of chips containing the uncommitted logic gate arrays can be pre-fabricated up to the point of the final metallization steps which creates the logic personalization. 21

23 Field Programmable Logic Arrays, FPGAs FPGAs are Integrated Circuits Whose Internal Functional Operation is Defined by the User RAPID SYSTEM PROTOTYPING OF ELECTRONIC SYSTEMS. They can be Programmed using a Hardware description Language, VHDL 23

30 Introduction To VHDL VHDL: Very High Speed Integrated Circuit (VHSIC) Hardware Description Language. VHDL Is an Industry Standard Language to Describe Hardware From the Abstract to Concrete Level. 30

31 BRIEF HISTORY OF VHDL VHDL is a Derivative of the VHSIC Program by US Dept. of Defense Along With IBM, Texas Instruments, and Intermetrics. In 1986 VHDL Became IEEE Standard and After Several Revisions. It Was Adopted As the IEEE 1076 Standard. 31

32 BRIEF HISTORY OF VHDL In 1999 the Analog and Mixed Signal Extensions Were Added to VHDL (VHDL-AMS) In 2000 the latest upgrade (Object Oriented added ) 32

37 When Should VHDL Be Used? VHDL is highly beneficial to use as a structured, top down approach to design. VHDL makes it easy to build, use, and reuse libraries of circuit elements. VHDL can greatly improve your chances of moving into more advanced tools and device targets. 37

38 Advantages of VHDL The Ability to Code the Behavior and to Synthesize an Actual Circuit. Power and Flexibility Device (specific FPGA) Independent Design 38

40 Getting Started with VHDL Its Easy To Get Started With VHDL, But Its Difficult To Master It. To Begin With, A Subset of The Language Can Be Learned To Write Useful Models. Later More Complex Features Can Be Learned To Implement Complex Circuits. 40

41 A First look at VHDL Lets start with a simple Combinational circuit: an 8-bit Comparator. 41

42 An 8 Bit Comparator Comparator Specifications: Two 8-bit inputs 1-bit Output Output is 1 if the inputs match or 0 if they differ. 42

43 An 8 Bit Comparator A[8] Comparator B[8] EQ A B

44 Comparator VHDL Source Code -- Eight-bit Comparator entity compare is port (A, B : in std_logic_vector (0 to 7); EQ : out std_logic); end compare; architecture comp of compare is begin EQ <= 1 when (A=B) else 0 ; end comp; An entity declaration that defines the inputs and outputs - the ports of the circuit An architecture that defines the function of the circuit 44

45 Entities and Architectures Every VHDL design description has at least one entity/architecture pair. A large design has many entity / architecture pairs and are connected to form the complete circuit. 45

46 What is an Entity? An entity declaration describes the circuit as it appears from outside - from perspective of its input and output interfaces. An entity declaration is analogous to a block symbol on a schematic. 46

47 What is an Entity? entity compare is port (A, B : in std_logic_vector (0 to 7); EQ : out std_logic); end compare; The entity declarations includes a name, compare, and a port statement defining all the inputs and outputs of the entity. 47

48 What is an Architecture? Architecture Describes the Actual Function - or Contents of the Entity to Which It Is Bound. Architecture Is Roughly Analogous to a Lower Level Schematic Referenced by the High Level Functional Block Symbol. 48

49 What is an Architecture? architecture comp of compare is begin EQ <= 1 when (A=B) else 0 ; end comp; The architecture declaration begins with a unique name, comp, followed by the name of the entity to which the architecture is bound, in this case compare. 49

50 What is an Architecture? architecture comp of compare is begin EQ <= 1 when (A=B) else 0 ; end comp; Between the keywords begin and end is found the actual functional description of the comparator. 50

51 Data Types VHDL s high level data types allow data to be represented in much the same way as in high-level programming languages. A data type is an abstract representation of stored data. 51

52 Data Types These data types might represent individual wires in a circuit, or a collection of wires. 52

55 Design Units Design units are a concept unique to VHDL that provide advanced configuration management capabilities. Design units are segments of VHDL code that can compiled separately and stored in a library. 55

57 Package Design unit A Package is a collection of commonly used data types to be used globally among different design units. Package declaration is identified by the package keyword. 57

58 Package Design Unit Items defined within a package can be made visible to any other design unit in the complete VHDL design and they can be compiled into libraries for later reuse. A package can consist of two basic parts A package declaration A package body (optional) 58

60 Package Body The package body defines the actual behavior of the items specified in the package. The relationship between package and package body is somewhat similar to that of entity and its corresponding architecture. 60

61 VHDL Configurations VHDL allows you to create more than one alternate architecture for an entity. This feature helps in experimenting with different implementations of circuit description. Its also useful for simulation and for project team environments. 61

62 VHDL Configurations Configuration declarations are not generally used for synthesis, and may not be supported by the synthesis tools. Configuration declarations are always optional, even for complex circuits. 62

63 VHDL Configurations An example of configuration declaration configuration t_build of rcomp is for structure for COMP1: compare use entity work.compare (comp); for ROT1: rotate use entity work.rotate (rotate1); end for; end t_build; 63

65 Levels of Abstraction (Styles) VHDL supports many possible styles of design description. These styles differ primarily in how closely they relate to the underlying hardware. 65

66 Levels of Abstraction (Styles) Levels of Abstraction refers to how far your design description is from an actual hardware realization. The three main levels of abstraction are: Behavior Dataflow (RTL) Structure 66

69 VHDL Timing Issues The Concept of Time Is the Critical Distinction Between Behavioral Descriptions and Low Level Descriptions. The Concept to Time May Be Expressed Precisely, With Actual Delays Between Related Events 69

75 Max+Plus II Development Software It also provides design programming, compilation, and verification support for all devices supported by the MAX+PLUS II BASELINE software including the EPM7128S, EPF10K20, and EPF10K70 devices 75

76 Max+Plus II Development Software The MAX+PLUS II University software can be freely distributed to students for installation on their personal computers and provides instant access to online help. For more information, follow the University Program Link at 76

77 Max+Plus II Development Software This Tool was created to help during the various implementation steps: Design Graphical Entry VHDL Model Compilation Simulation Verification Synthesis 77

82 Max+Plus II Development Software MAX+PLUS II University software targets the UP1 and UP1X development boards. the FLEX10K and MAX7000S devices can be configured and programmed (respectively) to interact with the included hardware or with any other external design. 82

83 Max+Plus II Development Software 83

84 Max+Plus II Half-Adder We will use our previous Half-Adder model as an example of how to perform a VHDL code entry. 84

85 Max+Plus II Half-Adder, Code Entry 85

86 Max+Plus II Half-Adder, Compiler 86

87 Max+Plus II Half-Adder, Simulation 87

88 Session II INTRODUCTION TO VHDL PART II 88

89 Dataflow (RTL) Modeling The dataflow level of abstraction is often called Register Transfer Language (RTL). The dataflow level of abstraction describes how information is passed between registers in the circuit. 89

90 Concurrent and Sequential VHDL VHDL Allows Both Concurrent and Sequential Statements to Be Entered. The Difference Between Concurrent and Sequential Statements Must Be Known for Effective Use of the Language. 90

91 Concurrent VHDL All Statements in the Concurrent Area Are Executed at the Same Time. There Is No Significance to the Order in Which Concurrent Statements Occur. 91

102 VHDL code for Full Adder The simulator evaluates all the expressions, L1-L5, then applies the results to the signals. Once the simulator has applied the results it waits for one of the signal to change and it reevaluates all the expression again. 102

103 VHDL code for Full Adder This cycle will continue until the simulation is completed. This is called event driven simulation. It is more computationally efficient than time driven simulation. 103

104 Signals In the Full_adder VHDL code we came across signal. architecture dataflow of full_adder is signal s1, s2, s3: std_logic; begin end dataflow; So what are signals? 104

105 Signals Signals Are Used to Carry Data From Place to Place in a VHDL Design Description. Signals Are Similar to Wires in a Schematic. Signals are internal to an entity, so they exist only in the architectures. 105

106 Sequential VHDL Sequential Statements Are Executed One After the Other in the Order That They Appear. Example of Sequential Statement: Process. 106

107 Sequential VHDL Begin Statement Statement Statement End 107

108 Process Construct The Process construct is the primary means to describe sequential operations. Process starts with the keyword process and ends with the keyword end process. The process construct itself is treated as a concurrent statement. 108

124 IF Statements The if statement can have multiple elsif statement parts but only one else statement part. 124

125 Case statement The Case statement is used whenever a single expression value can be used to select between a number of actions. A Case statement consists of the keyword case followed by an expression and the keyword is. 125

126 Case statement The expression will either return a value that matches one of the choices in a when statement part or match an others clause. 126

128 Loop Statements The loop statement is used whenever an operation needs to be repeated. Loop statements are implemented in two ways while condition loop statement for condition loop statement 128

129 Loop Statements (while) The while condition Loop statement will loop as long as the condition expression is TRUE. while (day = weekday) loop day := get_next_day (day); end loop; 129

130 Loop Statements (for loop) for i in 1 to 10 loop i_squared(i) := i*i; end loop; This loop will execute 10 times whenever execution begins and its function is to calculate squares from 1 to 10 and insert them into i_squared signal array. 130

131 Next statement The next statement allows us to stop execution of a particular iteration and go on to the next iteration. for i in 0 to max_limit loop if (done (i) = true ) then next; else done(i) := true; end if; q(i) <= a(i) and b(i); end loop; 131

132 Exit statement The VHDL exit statement allows the designer to exit or jump out of the loop statement currently in execution. for i in 0 to max_limit loop if (int_a <= 0) then exit; else int_a := int_a-1; q(i) <= 3.14 / real(int_a * i); end if; end loop; 132

133 Assert Statement Assert Statements Are Very Useful for Reporting Textual Strings to the Designer. The Assert Statement Checks the Value of a Boolean Expression. If the Condition Is Not True, a Report (Message) Is Generated During the Simulation. 133

134 Assert Statement An assert statement includes two options, either or both of which may be used. The first Option Report: displays a user defined message if the condition is false 134

135 Assert Statement An assert statement includes two options, either or both of which may be used. The second Option: Severity: allows the user to choose a severity level if the condition is false. The four levels of severity are Note, Warning, Error Failure 135

136 Wait Statements The wait statement allows to suspend the sequential execution of a process or subprogram. The condition for resuming execution of the suspended process or subprogram can be specified by three different means. 136

139 Wait on Statement The wait on signal clause specifies a list of one or more signals upon which the wait statement will wait for the events. process begin if (reset = 1 ) then q <= 0 ; elsif clock event and clock = 1 then q <= d; end if; wait on reset, clock; end process; 139

140 Wait Until Statement The wait until Boolean_expression clause will suspend execution of the process until the expression returns a true value. process begin wait until clock = 1 and clock event; q <= d ; end process; 140

141 Wait for Statement The wait for time_expression clause will suspend execution of the process for the time specified by the time expression. wait for 10 ns; The wait statement will suspend for 10 ns and after 10 ns the execution will continue. 141

142 Structural VHDL Structural-level design methods can be useful for managing the complexity of a large design description. Structure level of abstraction is used to combine multiple components to form a larger circuit. 142

143 Structural VHDL Structural VHDL Descriptions Are Quite Similar in Format to Schematic Netlists. Larger Circuits Can Be Constructed From Smaller Building Blocks. 143

144 Example of Structural VHDL Let us consider an ALU with An OR gate An XOR gate A Half Adder A Full Adder A Multiplexer 144

171 Max+Plus II alu_pack, Simulation The ALU_PACK design can not be simulated since it is a Package. Its operation will be verified together with the designs that will use it. In this case this will be the ALU main design. 171

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