The timing chart for the TDD LVDS is the same as the chart for the FDD LVDS. In LVDS mode the Tx and Rx have dedicated pins, i.e. the concept of port 0 and port 1 goes away, and there is no multiplexing Tx and Rx on the same "bus" as in the CMOS case.

For TDD LVDS mode , Port 0 is TX and Port 1 is RX. These cannot be swapped / multiplexed. As pointed above by Omek , the FDD timing diagram holds good for TDD, Care needs to be taken to sample Tx/RX according to ENSM state as explained in UG570 , figure 11. (below)