Comments

From: Will Auld <will.auld.intel@gmail.com>
CPUID.7.0.EBX[1]=1 indicates IA32_TSC_ADJUST MSR 0x3b is supported
Basic design is to emulate the MSR by allowing reads and writes to the
hypervisor vcpu specific locations to store the value of the emulated MSRs.
In this way the IA32_TSC_ADJUST value will be included in all reads to
the TSC MSR whether through rdmsr or rdtsc.
As this is a new MSR that the guest may access and modify its value needs
to be migrated along with the other MRSs. The changes here are specifically
for recognizing when IA32_TSC_ADJUST is enabled in CPUID and code added
for migrating its value.
Signed-off-by: Will Auld <will.auld@intel.com>Reviewed-by: Andreas Färber <afaerber@suse.de>Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
---
target-i386/cpu.h | 2 ++
target-i386/kvm.c | 14 ++++++++++++++
target-i386/machine.c | 21 +++++++++++++++++++++
3 files changed, 37 insertions(+)