MER INFORMATION

The Single-chip Cloud Computer (SCC) is an experimental multicore processor created
by Intel Labs for the many-core research community. The chip is built to study
many-core processors, their programmability and scalability while utilising messagepassing
as a communication model. The chip has a distributed memory architecture that
combines fast-access on-chip memory with large amounts of o-chip private and shared
memory. Additionally, its design is meant to favour message-passing over the traditional
shared-memory programming as is the norm for distributed memory systems. To this
eect, the platform deliberately provides neither hardware supported cache-coherence,
nor atomic memory read/write operations across cores and the on-chip memory, also
known as message passing buer is quite small.
The SCC provides support for very fast communications among the cores with reduced
latency. This allows for the creation of very ecient message-passing protocols and
support for message-passing programming model. This design employs explicit exchange
of messages among dierent processors, implicitly avoiding data consistency issues arising
from concurrent data access and merges both communication and synchronization.
However, due to the limited size of the message passing buers, the message-passing is
ideal for transfer of small amounts of data, but not very ecient for large data transfers.
In addition, replicating all datasets and exchanging them as messages is less ecient
and more wasteful than using the data directly in shared memory. In some cases, the
message data read from the main memory, is passed through the message passing buers
and eventually written back to the same memory modules. Besides, the chip provides
access to shared memory allowing the cores to share data without necessarily copying it
among the cores over the on-chip network.
In this thesis, we develop procedures for sharing data among multiple cores; concurrently
coordinated by message-passing on the Single-chip Cloud Computer. We further
make and investigate a proposition that, for architectures that combine message-passing
with shared-memory, the message-passing is not necessarily essential for data-transfer
but for coordinating shared-memory access and synchronization of operations on the
dierent cores.

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BibTeX @mastersthesis{Walulya2014,author={Walulya, Ivan},title={Synchronization and memory consistency on Intel Single-chip Cloud Computer},abstract={The Single-chip Cloud Computer (SCC) is an experimental multicore processor created
by Intel Labs for the many-core research community. The chip is built to study
many-core processors, their programmability and scalability while utilising messagepassing
as a communication model. The chip has a distributed memory architecture that
combines fast-access on-chip memory with large amounts of o-chip private and shared
memory. Additionally, its design is meant to favour message-passing over the traditional
shared-memory programming as is the norm for distributed memory systems. To this
eect, the platform deliberately provides neither hardware supported cache-coherence,
nor atomic memory read/write operations across cores and the on-chip memory, also
known as message passing buer is quite small.
The SCC provides support for very fast communications among the cores with reduced
latency. This allows for the creation of very ecient message-passing protocols and
support for message-passing programming model. This design employs explicit exchange
of messages among dierent processors, implicitly avoiding data consistency issues arising
from concurrent data access and merges both communication and synchronization.
However, due to the limited size of the message passing buers, the message-passing is
ideal for transfer of small amounts of data, but not very ecient for large data transfers.
In addition, replicating all datasets and exchanging them as messages is less ecient
and more wasteful than using the data directly in shared memory. In some cases, the
message data read from the main memory, is passed through the message passing buers
and eventually written back to the same memory modules. Besides, the chip provides
access to shared memory allowing the cores to share data without necessarily copying it
among the cores over the on-chip network.
In this thesis, we develop procedures for sharing data among multiple cores; concurrently
coordinated by message-passing on the Single-chip Cloud Computer. We further
make and investigate a proposition that, for architectures that combine message-passing
with shared-memory, the message-passing is not necessarily essential for data-transfer
but for coordinating shared-memory access and synchronization of operations on the
dierent cores.},publisher={Institutionen för data- och informationsteknik (Chalmers), Chalmers tekniska högskola},place={Göteborg},year={2014},note={53},}

RefWorks RT GenericSR ElectronicID 193594A1 Walulya, IvanT1 Synchronization and memory consistency on Intel Single-chip Cloud ComputerYR 2014AB The Single-chip Cloud Computer (SCC) is an experimental multicore processor created
by Intel Labs for the many-core research community. The chip is built to study
many-core processors, their programmability and scalability while utilising messagepassing
as a communication model. The chip has a distributed memory architecture that
combines fast-access on-chip memory with large amounts of o-chip private and shared
memory. Additionally, its design is meant to favour message-passing over the traditional
shared-memory programming as is the norm for distributed memory systems. To this
eect, the platform deliberately provides neither hardware supported cache-coherence,
nor atomic memory read/write operations across cores and the on-chip memory, also
known as message passing buer is quite small.
The SCC provides support for very fast communications among the cores with reduced
latency. This allows for the creation of very ecient message-passing protocols and
support for message-passing programming model. This design employs explicit exchange
of messages among dierent processors, implicitly avoiding data consistency issues arising
from concurrent data access and merges both communication and synchronization.
However, due to the limited size of the message passing buers, the message-passing is
ideal for transfer of small amounts of data, but not very ecient for large data transfers.
In addition, replicating all datasets and exchanging them as messages is less ecient
and more wasteful than using the data directly in shared memory. In some cases, the
message data read from the main memory, is passed through the message passing buers
and eventually written back to the same memory modules. Besides, the chip provides
access to shared memory allowing the cores to share data without necessarily copying it
among the cores over the on-chip network.
In this thesis, we develop procedures for sharing data among multiple cores; concurrently
coordinated by message-passing on the Single-chip Cloud Computer. We further
make and investigate a proposition that, for architectures that combine message-passing
with shared-memory, the message-passing is not necessarily essential for data-transfer
but for coordinating shared-memory access and synchronization of operations on the
dierent cores.PB Institutionen för data- och informationsteknik (Chalmers), Chalmers tekniska högskola,LA engLK http://publications.lib.chalmers.se/records/fulltext/193594/193594.pdfOL 30