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Net Burst was replaced with the Core microarchitecture, released in July 2006.The Net Burst microarchitecture includes features such as Hyper-Threading, Hyper Pipelined Technology, Rapid Execution Engine and Replay System which are were introduced for the first time in this particular microarchitecture.It stores decoded micro-operations, so that when executing a new instruction, instead of fetching and decoding the instruction again, the CPU directly accesses the decoded micro-ops from the trace cache, thereby saving considerable time.Moreover, the micro-ops are cached in their predicted path of execution, which means that when instructions are fetched by the CPU from the cache, they are already present in the correct order of execution.An example is shift and rotate operations, which suffer from the lack of a barrel shifter which was present on every x86 CPU beginning with the i386, including the main competitor processor, Athlon.Within the L1 cache of the CPU, Intel incorporated its Execution Trace Cache.

The "Presler" has an 800 MHz front-side bus, 64-bits wide, capable of transferring 6.4 GB/s, with 800 MHz DDR2 memory.called P68 inside Intel, was the successor to the P6 microarchitecture in the x86 family of CPUs made by Intel.The first CPU to use this architecture was the Willamette-core Pentium 4, released on November 20, 2000 and the first of the Pentium 4 CPUs; all subsequent Pentium 4 and Pentium D variants have also been based on Net Burst.To address this issue, Intel devised the Rapid Execution Engine and has invested a great deal into its branch prediction technology, which Intel claims reduces branch mispredictions by 33% over Pentium III.With this technology, the two ALUs in the core of the CPU are double-pumped, meaning that they actually operate at twice the core clock frequency.

A smaller instructions per clock (IPC) is an indirect consequence of pipeline depth—a matter of design compromise (a small number of long pipelines has a smaller IPC than a greater number of short pipelines).