Even with industry-wide challenges such as source power and its consequent constraints on wafer throughput, as well as machine uptime and yields, Samsung is rosy on the prospects of EUV technology in its own fabs. The company says using EUV tools allows it to reduce the number of masks needed to produce features at critical levels of the chip, thereby improving productivity—one of the largest expected benefits to foundries of the move to this exotic lithography method.

A cutaway of an ASML EUV scanner similar to the ones Samsung is employing for 7-nm LPP

As one example of its own innovations in dealing with the challenges of EUV, the company says it has developed its own defect-detection capabilities for EUV masks to prevent flaws from making their way to wafers—another difficulty that had bedeviled would-be adopters of this tech. The net result of using EUV scanners for its 7-nm LPP chips is that Samsung can claim a 40% increase in areal density over its 10-nm process with up to 20% higher performance or 50% lower power. To assist potential customers in implementing their designs on this process, Samsung is providing a wide range of standard IP and supporting design tools to partners like Ansys, ARM, Cadence, Mentor, Semco, Synopsys, and VeriSilicon.

Along with TSMC, whose 7-nm process is already producing customer silicon without the use of EUV, Samsung's transition to production-readiness for 7-nm LPP marks the second domino to fall in the race to next-generation process nodes. Only Intel's 10-nm process remains in the works at the leading edge, and the blue team hasn't promised production silicon from that process until late next year. Intel now finds itself firmly in the unenviable position of playing catch-up to pure-play foundries in silicon technology (at least on paper), and that is a remarkable turn of events for a company that used to claim it was a generation ahead of those foundries in process tech. We'll be eager to see what customers Samsung lands as it ramps 7-nm LPP.