The bus frequency is only relevant when acting as master. The bus frequency should not be set higher than the maximum frequency accepted by the slowest device on the bus.

Notice that, due to asymmetric requirements on low and high I2C clock cycles in the I2C specification, the maximum frequency allowed to comply with the specification may be somewhat lower than expected.

See the reference manual, details on I2C clock generation, for maximum allowed theoretical frequencies for different modes.

Parameters

[in]

i2c

A pointer to the I2C peripheral register block.

[in]

freqRef

An I2C reference clock frequency in Hz that will be used. If set to 0, HFPER clock is used. Setting it to a higher than actual configured value has the consequence of reducing the real I2C frequency.

[in]

freqScl

A bus frequency to set (bus speed may be lower due to integer prescaling). Safe (according to the I2C specification) maximum frequencies for standard fast and fast+ modes are available using I2C_FREQ_ defines. (Using I2C_FREQ_ defines requires corresponding setting of type.) The slowest slave device on a bus must always be considered.

[in]

i2cMode

A clock low-to-high ratio type to use. If not using i2cClockHLRStandard, make sure all devices on the bus support the specified mode. Using a non-standard ratio is useful to achieve a higher bus clock in fast and fast+ modes.

Get slave address used for I2C peripheral (when operating in slave mode).

For 10-bit addressing mode, the address is split in two bytes, and only the first byte setting is fetched, effectively only controlling the 2 most significant bits of the 10-bit address. Full handling of 10-bit addressing in slave mode requires additional SW handling.

Parameters

[in]

i2c

Pointer to I2C peripheral register block.

Returns

I2C slave address in use. The 7 most significant bits define the actual address, the least significant bit is reserved and always returned as 0.

Get slave address mask used for I2C peripheral (when operating in slave mode).

The address mask defines how the comparator works. A bit position with value 0 means that the corresponding slave address bit is ignored during comparison (don't care). A bit position with value 1 means that the corresponding slave address bit must match.

For 10-bit addressing mode, the address is split in two bytes, and only the mask for the first address byte is fetched, effectively only controlling the 2 most significant bits of the 10-bit address.

Parameters

[in]

i2c

Pointer to I2C peripheral register block.

Returns

I2C slave address mask in use. The 7 most significant bits define the actual address mask, the least significant bit is reserved and always returned as 0.

Set slave address mask used for I2C peripheral (when operating in slave mode).

The address mask defines how the comparator works. A bit position with value 0 means that the corresponding slave address bit is ignored during comparison (don't care). A bit position with value 1 means that the corresponding slave address bit must match.

For 10-bit addressing mode, the address is split in two bytes, and only the mask for the first address byte is set, effectively only controlling the 2 most significant bits of the 10-bit address.

Parameters

[in]

i2c

Pointer to I2C peripheral register block.

[in]

mask

I2C slave address mask to use. The 7 most significant bits define the actual address mask, the least significant bit is reserved and should be 0.

Set slave address to use for I2C peripheral (when operating in slave mode).

For 10- bit addressing mode, the address is split in two bytes, and only the first byte is set, effectively only controlling the 2 most significant bits of the 10-bit address. Full handling of 10-bit addressing in slave mode requires additional SW handling.

Parameters

[in]

i2c

Pointer to I2C peripheral register block.

[in]

addr

I2C slave address to use. The 7 most significant bits define the actual address, the least significant bit is reserved and always set to 0.

It may also be used in interrupt driven mode, where this function is invoked from the interrupt handler. Notice that, if used in interrupt mode, NVIC interrupts must be configured and enabled for the I2C bus used. I2C peripheral specific interrupts are managed by this software.