While it is true that many complex 68K addressing modes are slower than the
expansion of those modes into multiple instructions, it would be nice if
compilers were aware of the resulting code size tradeoff. Our group here at
Tek sells an instrument whose firmware barely fits into several megabytes of
ROM. Outside of speed-critical inner loops, we would gladly take the speed
penalty that the complex instructions imply, in order to get the 10-20%
estimated space savings. GCC seems to make a reasonable static tradeoff in
this area, but it would be nice if more compilers (a) allowed the programmer
to hint at compile time or within the language about speed/space tradeoffs,
and/or (b) were better at guessing dynamically when they were in a
speed-critical section of code. Of course (b) is a *very* difficult
problem...