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解决方案

2. In the v5.0 SPI-4.2 (PL4) core, the RSClkPhase static configuration signal sets the relationship between RSClk and RStat. However, this does not currently work under all conditions, and RSClk may be shifted by 90 or even 180 degrees, regardless of the RSClkPhase setting.

3. Please do not install 4.2_ip_update3 onto the 5.1i ISE software. The 4.2_ip_update3 contains the SPI-4.2 (PL4) v5.0 core, and this IP update was only tested on the 4.2i software. The use of 4.2_ip_update3 with the ISE5.1i software may cause adverse effects.

4. While every attempt was made to keep the constraints as consistent as possible between v4.0 and v5.0, certain modifications are required to update the constraints when a conversion to v5.0 is performed.

11. When I use the Xilinx SPI-4.2 (PL4) core and I set the Almost Full Assert/Negate values for the Sink or Source FIFO to be less than 6, data is lost. (An Overflow_n flag is asserted before FFAlmostFull_n is asserted (active Low).)

1. When post-NGDBuild or post-route simulation is run with a SPI-4.2 (PL4) core, the Source status signals on the user interface of the core do not behave properly. Glitches of "X" or "unknown" appear on the SrcStatCh signal, and the SrcStat output is never updated.

1. When Fixed Static Alignment is used, it is necessary to determine the best DCM setting (PHASE SHIFT) to insure that the target system will contain the maximum system margin and perform across voltage, temperature, and process (multiple chips) variations.

3. In SPI-4.2 (PL4) Core versions 4.0 and 5.0, the use of automatic static alignment may result in DIP4 errors on the Sink Core. The DIP4 errors appear on the device, but the simulation will not display them.