ABSTRACT:
Small satellites consisting of a set of integrated circuits (IC), i.e., nano-spacecraft, have been introduced recently to solve challenges such as propulsion cost and launch weight. The conventional spaceship takes 18,000 years from Earth to a nearest star, i.e., Alpha Centauri, but the spacecraft-on-a-chip technology dramatically reduces the travel time to 20 years due to its light weight and great energy efficiency. However, high risks of radiation induced damages and mission period over 20 years (longer than usual lifetime of IC) are considered as technology barriers. It is intrinsically impossible to avoid unexpected radiation exposure. The shielding metal adds significant weight, which nullifies the fundamental advantage of the nano-spacecraft. In this talk, self-healing process is introduced for sustainable space electronics. Degradation and recovery mechanisms for total ionizing dose, single event effect, hot carrier, and tunneling stress are discussed in silicon nanowire gate-all-around FETs. Dual contact pads of the gate allow current flow creating heat for on-chip annealing, which recovers interface states and bulk traps in the gate dielectric. The effect of the self-healing is examined for practical applications such as a logic transistor, high-speed DRAM, and non-volatile Flash memory. Therefore, the lifetime of devices can be extended, which opens an opportunity for nano-spacecraft sustainable for more than 20 years of deep space exploration. The technology will have an impact on terrestrial applications with critical requirements as well.

SPEAKER BIOGRAPHY:
Dong-Il Moon is a postdoctoral researcher at the Center for Nanotechnology at NASA Ames Research Center. He was previously a senior engineer of Device & Process Integration Technology Group at SK Hynix (2015). He received Ph.D. (2015) and M.S. (2010) in EE from KAIST, and B.S. (2008) in EECS from Kyungpook National University. His honors include the best Ph.D. thesis award in Department of EE at KAIST (2015), grand prize for thesis award from Lam Research Korea (2014), the best research student award in EE from KAIST twice (2012, 2014). His research includes fundamental and applied aspects of nano devices. He has explored the emerging nanoscale devices in layout, mask fabrication, wafer processing, simulation, and modeling. Especially, he led a research team responsible for developing the suspended silicon nanowire on a bulk silicon substrate, which is used as a basic building block for a nano-scale circuit. Based on the developed novel process, advanced MOSFETs such as a gate-all-around FET, a tri-gate FinFET, and an independently controlled double-gate FET were fabricated, which were utilized for various applications such as a logic transistor, a memory cell, and a biosensor. He has authored or coauthored one book chapter, 70 articles in peer-reviewed scientific journals, and 16 proceeding papers for international conferences.

AGENDA:

11:30 am – Registration & light lunch (pizza & drinks)

Noon – Presentation & Questions/Answers

1:00 pm – Adjourn

COST: FREE, but a $5 donation is requested to help cover the cost of lunch

ABSTRACT (extended here):
A qubit is a unit of quantum information—the fundamental currency of quantum computing, which is predicted to be hugely more efficient for solving problems that are challenging for traditional computers, such as breaking secret codes. This presentation will describe a path to development of a practical qubit design based on silicon CMOS processing technology. The qubit device is an electrostatic silicon quantum dot (QD) with an implanted donor. We demonstrate for the first time coherent two-axis control of a two-electron spin logical qubit that evolves under QD-donor exchange interaction as well as interaction with the donor nucleus, with decoherence as good as that of competing systems.

SPEAKER BIOGRAPHY (extended here):
Malcolm Carroll is the Principal Investigator for research on silicon quantum computing at Sandia National Laboratories, including development of quantum dots, cryoelectronics and quantum error correction schemes for future quantum circuitry. In 2001 he received a Ph.D. in Electrical Engineering from Princeton University and joined Bell Labs/Lucent Technologies at Murray Hill, NJ. In 2003 and 2006 he became a senior and then principal member of the technical staff at Sandia National Laboratories. Dr. Carroll was a Fulbright Fellow and has been an author on over 50 peer reviewed articles and 3 patents. He co-founded and is an organizing committee member of the Silicon Quantum Computing Workshop series and is an external advisor for the Australian Centre for Quantum Computing Technology.

AGENDA:

11:30 am – Registration & light lunch (pizza & drinks)

Noon – Presentation & Questions/Answers

1:00 pm – Adjourn

COST: FREE, but a $5 donation is requested to help cover the cost of lunch

We are now in a very exciting period of time when many new and disruptive technologies emerge across a wide range of industries, making the existing technologies obsolete faster than anyone could anticipate. The new products with emerging technologies are generally smaller, lighter, stronger, more reliable and cheaper. To achieve all these, process control has becoming more important than ever, which gives good opportunities for various metrology tools to be incorporated into the advanced manufacturing processes. This leads to new challenges to integrate the metrology tools into the manufacturing tools. In this talk, I will review and compare several metrology tools and their applications in nanotechnology, and discuss about some of the challenges in integrating the tools into the manufacturing process.

SPEAKER BIOGRAPHY:

Dr. Min Yang joined Bruker Nano Surfaces as Director of Applications Development, responsible for developing new applications for tribology, optical and stylus metrology, and optical coordinate measurement. Min has over 20 years of experience in tribology, metrology and failure analysis, mostly in the data storage business in Silicon Valley. She started her career as a tribology integration engineer for head/disk interface designs and held a number of positions at IBM and Western Digital in tribology and failure analysis. Prior joining Bruker, Min was an Engineering Director at Western Digital, responsible for the development of tribology and failure analysis testing on a wide variety of instruments including, SEM/EDX, AFM, FIB, TOF-SIMS, FTIR, Raman, optical analysis tools, and test chambers. Min holds a BSEE from Beijing University of Technology, a Masters in Materials Science from Beijing Aeronautical Materials Institute, and both a Masters in Mechanical Engineering and a PhD in System Engineering from UC San Diego.

AGENDA:

11:30 am – Registration & light lunch (pizza & drinks)

Noon – Presentation & Questions/Answers

1:00 pm – Adjourn

COST: FREE, but a $5 donation is requested to help cover the cost of lunch

One-dimensional (1D) materials like carbon nanotubes (CNTs) and two-dimensional (2D) materials like graphene have potential applications in low-power electronics and energy-conversion systems. These are also rich domains for fundamental discoveries as well as technological advances. This talk will present recent highlights from our research on CNTs, graphene, and MoS2. As an example, we used CNTs to enable the most energy-efficient phase-change memory (PCM) devices to date. We have also studied graphene from basic transport measurements, to the recent wafer-scale demonstration of analog dot product nanofunctions. We are presently evaluating the unusual thermal and thermoelectric properties of other 2D materials (like MoS2) which could lead to unconventional applications in energy harvesters and thermal circuits. Our studies ultimately reveal fundamental limits and new applications that could be achieved through the co-design and heterogeneous integration of 1D and 2D nanomaterials. For more info please visit http://poplab.stanford.edu.

SPEAKER BIOGRAPHY:

Eric Pop (epop@stanford.edu) is an Associate Professor of Electrical Engineering (EE) at Stanford, where he leads the SystemX Heterogeneous Integration Focus Area. He was previously on the faculty of the University of Illinois Urbana- Champaign (2007-13) and worked at Intel (2005-07). His research interests are at the intersection of electronics, nanomaterials, and energy. He received his PhD in EE from Stanford (2005) and three degrees from MIT (MEng and BS in EE, BS in Physics). His honors include the 2010 PECASE from the White House, and Young Investigator Awards from the ONR, NSF CAREER, AFOSR, and DARPA. He is an IEEE Senior member, he served as the General Chair of the Device Research Conference (DRC), and on program committees of the VLSI, IRPS, MRS, IEDM, and APS conferences. In a past life, he was a DJ at KZSU 90.1 from 2001-04.

AGENDA:

11:30 am – Registration & light lunch (pizza & drinks)

Noon – Presentation & Questions/Answers

1:00 pm – Adjourn

COST: FREE, but a $5 donation is requested to help cover the cost of lunch

The virtuous cycle of integrated-circuit (IC) technology advancement has been sustained for over 50 years, resulting in the proliferation of information and communication technology with dramatic economic and social impact. Industry experts predict that the pace of increasing transistor density will slow down dramatically within the next 5 years, however, due to fundamental limits of the conventional photolithographic patterningprocess. Scaling of IC feature sizes beyond the resolution limit of lithography has been enabled by multiple-patterning techniques, but at significant incremental cost. In the first part of this seminar, I will describe a more cost-efficient approach for defining sub-lithographic features, to help extend the era of Moore’s Law.

Beyond Moore’s Law,the proliferation of mobile electronic devices and the emergence of applications such as wireless sensor networks and the Internet of Things have brought energy consumption to the fore of challenges for future information-processing devices. The energy efficiency of a digital logic integrated circuit is fundamentally limited by non-zero transistor off-state leakage current. Mechanical switches have zero leakage current and potentially can overcome this fundamental limit. In the second part of this seminar, I will describe recent progress toward realizing the promise of ultra-low-power mechanical computing.

SPEAKER BIOGRAPHY:
Tsu-Jae King Liu received the B.S., M.S., and Ph.D. degrees in Electrical Engineering from Stanford University. From 1992 to 1996 she was a Member of Research Staff at the Xerox Palo Alto Research Center (Palo Alto, CA). In August 1996 she joined the faculty of the University of California, Berkeley, where she currently holds the TSMC Distinguished Professorship in Microelectronics in the Department of Electrical Engineering and Computer Sciences and serves as Associate Dean for Academic Planning and Development in the College of Engineering.

Dr. Liu’s research awards include the DARPA Significant Technical Achievement Award (2000) for development of the FinFET, the IEEE Kiyo Tomiyasu Award (2010) for contributions to nanoscale MOS transistors, memory devices, and MEMs devices, the Intel Outstanding Researcher in Nanotechnology Award (2012), and the Semiconductor Industry Association Outstanding Research Award (2014). She has authored or co-authored close to 500 publications and holds over 90 U.S. patents, and is a Fellow of the IEEE. Her research activities are presently in advanced materials, process technology and devices for energy-efficient electronics.

AGENDA:

11:30 am – Registration & light lunch (pizza & drinks)

Noon – Presentation & Questions/Answers

1:00 pm – Adjourn

COST: FREE, but a $5 donation is requested to help cover the cost of lunch

Economic adulteration of milk is a serious issue that has caused illness in 0.3 million people in 2008 alone. This is made possible by the fact that milk quality is assessed solely on its nitrogen content. Currently only a small amount of milk is checked for adulteration as small molecule adulterants are detected via HPLC-MS and GC-MS systems in centralized laboratories, at significant cost in terms of resources, time, and product useful shelf-life. Thus portable, field-deployable systems are strongly needed for detection of milk adulteration. This talk will focus on directions and challenges of designing such systems and using nano-structures for performing sensing from real samples such as milk. The talk will also discuss efforts at HP Labs to enable such sensing via a nano structured surface enhanced Raman sensor (SERS).

SPEAKER BIOGRAPHY:

Dr. Viktor Shkolnikov is a researcher at HP Labs, where he leads several microfluidics for life sciences projects. His research interests include experimental fluid dynamics and transport phenomena (especially micro/nano-fluidics), electrokinetics and electrohydrodynamics, microscale cooling, Lab-on-a-Chip and drug delivery devices, and fluid mechanics as applied to health care and life sciences. Viktor Shkolnikov received his Ph.D., M.S., and B.S. all in Mechanical Engineering and all from Stanford University.

AGENDA:

11:30 am – Registration & light lunch (pizza & drinks)

Noon – Presentation & Questions/Answers

1:00 pm – Adjourn

COST: FREE, but a $5 donation is requested to help cover the cost of lunch

The computing demands of future data-intensive applications far exceed the capabilities of today’s electronics, and cannot be met by isolated improvements in transistor technologies or integrated circuit (IC) architectures alone. Transformative nanosystems, which leverage the unique properties of emerging nanotechnologies to create new IC architectures, are required to deliver unprecedented performance and energy efficiency. However, emerging nanomaterials and nanodevices suffer from significant imperfections and variations. Thus, realizing working circuits, let alone transformative nanosystems, has been infeasible.

As a case-study for realizing nanosystems, I will present my work on carbon nanotube field-effect transistors (CNFETs), a leading candidate for energy-efficient and high-performance digital systems. Unfortunately, substantial imperfections and variations inherent to carbon nanotubes (CNTs), combined with low current densities, restricted demonstrations to stand-alone transistors or logic gates, with severely limited performance, yield, and scalability. I will describe techniques to overcome these major challenges through a combination of new CNT process techniques and CNFET circuit design solutions. This imperfection-immune paradigm transforms CNTs from solely a scientifically-interesting material into working nanosystems such as the first microprocessor [Nature 2013] and the first digital sub-systems [ISSCC 2013, JSSC 2014, ACS Nano 2014] built entirely using CNFETs. These are the first system-level demonstrations among promising emerging nanotechnologies for high-performance and highly energy-efficient digital systems. This approach also enables high-performance CNFETs with the highest current-drive to-date (which are, for the first time, competitive with comparably-sized silicon-based transistors from commercial foundries [IEDM 2014]). All of the fabrication and design techniques are VLSI-compatible, and can be applied to arbitrary technology nodes; to illustrate, I will describe recent results from a 14 nm-node CNFET [IEDM 2015].

Beyond specific CNT technologies, I will also present my work on building new architectures to achieve high degrees of energy efficiency for emerging data-intensive applications. Such new architectures are naturally enabled by a range of beyond-silicon emerging nanotechnologies (including CNTs). I will demonstrate the first monolithically-integrated three-dimensional (3D) nanosystem architectures [VLSI Tech. 2014, IEDM 2014] with vertically-integrated layers of logic, memory, and sensing circuits. These include the largest nanosystem yet fabricated using beyond-silicon emerging nanotechnologies, with over 2 million CNFETs and over 1 million Resistive Random Access Memory (RRAM) cells, all integrated vertically over a conventional silicon substrate with over 1 million silicon transistors (all fabricated at the Stanford Nanofabrication Facility). With dense and fine-grained connectivity between sensing, storage and computation, such nanosystems can capture terabytes of data from the outside world every second, and produce “processed information” by performing in-situ classification of the sensor data using on-chip accelerators designed using CNFET logic.

I will conclude by giving my vision for how the ubiquitous computing technology that is critical for meeting society’s challenges in the 21st century can be realized by harnessing the capabilities of multiple nanomaterials and nanodevices in complex nanosystems.

SPEAKER BIOGRAPHY:

Max Shulaker will be joining MIT in Electrical Engineering and Computer Science as a faculty member, having finished his PhD in Electrical Engineering at Stanford University under the supervision of Professor Subhasish Mitra and co-advised by Professor Philip Wong. He received his B.S. from Stanford University in Electrical Engineering. Max’s current research interests are in the broad area of nanosystems. His research results include the demonstration of the first carbon nanotube computer (highlighted on the cover of Nature, Sept. 2013), the first digital sub-systems built entirely using carbon nanotube FETs (awarded the ISSCC Jack Raper Award for Outstanding Technology-Directions Paper, 2013), the first monolithically-integrated 3D integrated circuits combining arbitrary vertical stacking of logic and memory (IEDM 2014), the highest-performance CNFETs to-date (IEDM 2014), and the first highly-scaled CNFETs fabricated in a VLSI-compatible manner (IEDM 2015). He was a Fannie and John Hertz Fellow and a Stanford Graduate Fellow.

AGENDA:

11:30 am – Registration & light lunch (pizza & drinks)

Noon – Presentation & Questions/Answers

1:00 pm – Adjourn

COST: FREE, but a $5 donation is requested to help cover the cost of lunch