By that rationale if I am reading the band gap voltage (which according to the datasheet is 1.2V) I should expect to see 35.8% of the full scale value of the A/D converter (running in 12 bit mode) when I read from channel 28. So I should expect to see a reading of 1466.

However :
With the ADC_TAD_MUL_0 set – I get a reading of 2917
With the ADC_TAD_MUL_31 set – I get a reading of 1939 instead.

Neither of these is even close to the 1466 I am expecting.

Unless of course I am being an idiot, and I'm always willing to eat humble pie if it solves the problem!

Thanks in advance

James

Ttelmah

Joined: 11 Mar 2010Posts: 13983

Posted: Fri Feb 02, 2018 1:20 pm

I'd set the BGREQ bit as well. Otherwise the band gap may not actually be on.

As a comment, you need ACT=USB added to your clock setup if you intend to use the USB.

PCM programmer

Joined: 06 Sep 2003Posts: 20477

Posted: Fri Feb 02, 2018 2:42 pm

Put a delay after you enable the band gap generator. See what happens.

I have stuck the above code changes in, and it makes absolutely no difference.

My ADC reading is 2913

However I then had an email from Richard @ ccs support, who has found this. . .

To get the correct VBG reading I had to increase the sampling time. To do that I had to use a slower ADC clock, surprisingly the internal clock was to fast, a 1ms ADC clock period with a sampling time of 31 Tad seem to work for me. For example with a clock speed of 32MHz the following ADC setup worked for me to read it correctly:

Code:

setup_adc(ADC_CLOCK_DIV_32 | ADC_TAD_MUL_31);

originally I had this setup

Code:

setup_adc(ADC_CLOCK_INTERNAL | ADC_TAD_MUL_31);

Under the new settings I get an ADC value of this....

BAND GAP:1479

Which is pretty much where I'd expect it to be.

However - I am at a loss to explain why! Any ideas?

Thanks

James

temtronic

Joined: 01 Jul 2010Posts: 6462Location: Greensville,Ontario

Posted: Mon Feb 05, 2018 8:03 am

this
setup_adc(ADC_CLOCK_INTERNAL

most PICs 'internal' is ONLY supposed to be used for sleeping PICs..it's somewhere in the ADC section, a chart or table, that shows valid adc clock vs CPU clock...usually there's 2 or 3 valid settings you can use.

the div_31 is interesting to me... 32 makes sense, 31 is just 'odd' though I don't use that PIC so I'll assume it's a correct value

Jay

Ttelmah

Joined: 11 Mar 2010Posts: 13983

Posted: Mon Feb 05, 2018 9:43 am

temtronic wrote:

this
setup_adc(ADC_CLOCK_INTERNAL

most PICs 'internal' is ONLY supposed to be used for sleeping PICs..it's somewhere in the ADC section, a chart or table, that shows valid adc clock vs CPU clock...usually there's 2 or 3 valid settings you can use.

the div_31 is interesting to me... 32 makes sense, 31 is just 'odd' though I don't use that PIC so I'll assume it's a correct value

Jay

I'm sorry Jay, this is wrong for the PIC24's.
The internal clock is often recommended.

I originally was going to suggest increasing the divider, since some other chips in the family have the internal RC too fast without a divider, and /2 has to be selected. However I checked the data sheet, and for this chip it is specific that the internal clock is slow enough.
Looks like a case where the data sheet is wrong for this chip....

On several of the other chips there is advice _not_ to have a TAD_MUL of 0. However '1' is enough if you have the delay as you do.

I'd suggest:

setup_adc(ADC_CLOCK_DIV_2 | ADC_TAD_MUL_1);

Might well work (assuming you have the acquisition delay you show in your code).