Power-Saving Design Brings DDS Flexibility To Portables

This innovative design blends low power consumption with a programmable modulus architecture to achieve new levels of modulation and output-frequency control.

Direct digital synthesis (DDS) has served a wide range of applications due to its fast frequency switching speed and modulation capabilities. But it has often been relegated to a secondary choice in favor of analog phase-locked- loop (PLL) synthesis for cases where low power consumption and low cost are key factors. However, the model AD9913 from Analog Devices (www.analog.com) provides the fast-switching and modulation flexibility of DDS technology across a 125-MHz output bandwidth with PLL-like low power consumption of only about 50 mW.

The power consumption of DDS solutions has traditionally been high. For example, when one of the first DDS products with integrated digital-to-analog converter (DAC), the model AD9850, was introduced in the mid-1990s, it consumed 380 mW of power for a 50-MHz output bandwidth. Innovations embodied in the AD9913 have resulted in a 20X improvement in power consumption versus bandwidth relative to the AD9850.

The AD9913 brings three key benefits to portable and/or instrumentation applications. The low 50-mW power consumption allows designers to take advantage of the benefits of DDS in handheld and other portable applications. The programmable modulus architecture is an attractive feature for network clocking and instrumentation applications. It allows synthesis of frequencies that are an arbitrary rational (ratio of two integers) sub-multiple of the sample rate. A conventional DDS can only synthesize rational sub-multiples of the sample rate when the denominator is a power of 2, such as 1/4 and 5/16 while the AD9913 is not limited by this power-of-2 constraint. It can generate output signals that are arbitrary rational sub-multiples of the sample rate, such as 1/10, 3/7, or 286/11487 (as long as they fall within the programming range of the AD9913). Finally, the AD9913 offers extremely flexible waveform generation in the manner of some of the firm's earlier DDS products.

The low power consumption of the AD9913 is made possible by several power-saving innovations. The first of these involves the portion of the DDS that converts the instantaneous phase values produced by the phase accumulator to amplitude values based on a sine and/or cosine function. Traditionally, a read-only-memory (ROM) lookup table performed this task. However, as DDS technology evolved to higher speeds and greater complexity, the power burden of the ROM approach became prohibitive. This led to the use of a proprietary angle-rotation algorithm that relies on a computational engine to perform sine and/or cosine conversions. The angle-rotation algorithm approach dates back to the model AD9850 DDS, and was found to significantly reduce power consumption relative to the ROM lookup table approach. Without the angle-rotation algorithm, many of the early DDS offerings would have required special thermal packaging to accommodate the increased power dissipation. Furthermore, thermal considerations might have forced the exclusion of many of the valuable features found in the company's existing DDS portfolio (e.g., digital phase and/or frequency modulation of the DDS output signal, digital filtering to mitigate sin(x)/x loss, multiple DDS cores for multi-channel applications).

The next major breakthrough in power reduction can be attributed to the firm's patented phase-interleaved DDS architecture (United States Patent No. 6,587,863). The earlier power reduction enabled by the angle-rotation algorithm made it possible to consider operating multiple DDS cores on the same chip. It was found that running multiple DDS cores at a lower sample rate consumed less power than running a single DDS core at a very high sample rate. This was a significant breakthrough, because high resolution (14 b or more), high sample rate (1 GHz or higher) digital-to-analog-converter (DAC) cores would require innovations in DDS technology in order to take advantage of these new DAC cores. The interleaved DDS architecture enabled designers to incorporate multiple copies of the already lower-power DDS cores and operate them at a lower sample rate than the high-frequency DAC core. This new innovative architecture along with the transition to a 180-nm CMOS fabrication process led to a dramatic increase in DDS output bandwidth with only a moderate cost in power consumption relative to the previous generation of lower-frequency DDS products.

Even with these innovations, however, power consumption still was excessive in the context of handheld and portable applications. In order to bridge this gap another innovation was necessary. This came about with the introduction of a new proprietary variant of the angle rotation algorithm that further reduced the power consumed by the DDS core. The new algorithm combined with a design philosophy focused on low power operation enabled designers to reach the desired low power design goals. The new philosophy included turning off all extraneous internal clocks when not required for a particular operating mode and shaving power from every circuit block so long as it did not degrade spectral performance or unduly limit bandwidth.

The result is the AD9913, which operates at sample rates to 250 MHz with only 50 mW power consumption. A sample rate of 250 MHz yields about 100 MHz of usable bandwidth. That output-frequency capability, in conjunction with the low power consumption, makes the AD9913 an attractive candidate for a wide range of radio-control units as well as wireless scanners for bar codes and radio-frequency-identification (RFID) tags. For applications requiring higher than 100 MHz, however, an auxiliary PLL must be employed for upconversion. Other portable/handheld applications that can benefit from low-power DDS technology include software-defined radios (SDRs), remote or portable cable television test equipment, medical glucose meters, wireless fire alarms, and electronic measurement equipment such as spectrum analyzers and waveform generators.

Unique Architecture

Fig. 1 shows the low power consumption characteristics of the AD9913 when operating at a nominal output frequency of 100 MHz. The plot indicates three different operating modes (single tone, linear sweep, programmable modulus) with the REFCLK input driven directly with either a differential or single-ended source (internal PLL disabled).

The AD9913's programmable modulus architecture is unique and sets it apart from conventional DDS devices. A conventional DDS relies on a phase accumulator for its frequency resolution, with the size of the accumulator (in bits) determining the frequency resolution of the DDS.

A conventional DDS with a phase accumulator having C-bit resolution will provide frequency resolution of f S/2C, where f S is the sample rate of the DDS. The digital tuning word, M, can be any integer from zero to 2C - 1} - 1. Technically, tuning words from 2C - 1 to 2C- 1 are allowed, but these result in the synthesis of a Nyquist image frequency (i.e., a counter-rotating phasor). The digital tuning word and the DDS sample rate (fS) leads to the familiar DDS frequency synthesis equation, where fO is the DDS output frequency:

fO/fS = M/2C (1)

Because M must be an integer, for any given sample rate a conventional DDS can only synthesize 2C - 1 unique frequencies. That is, for M = 0 the output frequency is zero (DC) and for M = 2C - 1 - 1 the output frequency is just shy of 0.5fS. All remaining output frequencies are constrained to be increments of fs2C (the frequency resolution of the DDS). In most cases, such fine frequency resolution is more than satisfactory. For example, in the case of the AD9913, which possesses a 32-b accumulator, the frequency resolution is (250 MHz)/232, or approximately 0.058 Hz.

Now consider the case in which a conventional DDS with a 32-b accumulator is called upon to synthesize an output frequency of exactly 1/1000th of the sample rate. This implies that fO/fS = 1/1000. Substituting this for the left-hand side of Eq. 1 and solving for M yields: M = 232/1000, or M = 4294967.296, where is it apparent that M is not an integer. A conventional DDS requires an integer value for M, the nearest of which is 4,294,967 in this example. The difficulty is that the use of this tuning word does not exactly synthesize a frequency of 0.001fS, but approximately 0.000999999931fS instead. In some applications this slight deviation in desired frequency is unacceptable (network clock applications, for example).

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The C-bit phase accumulator in a conventional DDS results in a fixed modulus (N), namely N = 2C. The programmable modulus DDS architecture employs a clever modification of the phase accumulator that allows the modulus to be any integer such that 1 ≤ N ≤ 2C. That is, N can have a user-programmable value. With the programmable modulus DDS architecture, for N = 1 or N = 2 the synthesized frequency is 0 Hz, so the lowest useful modulus number (for generating an output other than DC) is N = 3.

A programmable modulus DDS, like a conventional DDS, requires that M in Eq. 1 be an integer. However, since N is programmable, the equation for the DDS output frequency changes to:

fO/fS = M/N (2)

The implication of Eq. 2 may not be readily apparent, but it is significant. Consider the case of choosing the specific modulus, N = 2C. This particular choice of N makes possible the same set of frequencies that a conventional DDS can synthesize. However, the programmable modulus DDS not only includes the entire set of conventional DDS frequencies, but many, many more. This is because each unique choice of N (from 3 to 2C), includes all of the frequencies associated with M (1 ≤M <0.5N - 1). Compared to a conventional DDS, this represents a much larger set of possible output frequencies for any given sample rate.

The advantage of the programmable modulus architecture is that almost any rational frequency ratio is synthesizable. For example, it is now possible to exactly synthesize the frequency, fO = fS/1000 by making M = 1 and N = 1000. In fact, not only is fO = fS/1000 synthesizable, but so also is every harmonic of fS/1000 up to the 499th harmonic . For more comparing conventional DDS versus programmable modulus architectures, readers are invited to download a free copy of application note AN-953 from the Analog Devices website at www.analog.com.

Developing the programmable modulus while maintaining low power consumption was not trivial. While it may seem simple to modify a conventional accumulator by adding some extra logic that forces the accumulator to roll over at the new modulus value, it should be noted that the original DDS power-conserving innovation involved the angle-rotation algorithm, which draws its efficiency by the fact that the accumulator modulus is a power of 2. Altering the accumulator modulus to anything other than a power of 2 precludes the use of the power-saving angle-rotation algorithm.

The cleverness of the accumulator modification is twofold. First, it provides the modulus variation while maintaining the power-of-2 requirement of the angle-rotation algorithm. Second, it does so in a way that minimizes the impact on spurious performance. In both Fig. 2 and Fig. 3, the spectrum analyzer plots span 0 Hz to 125 MHz with the AD9913 sample rate at 250 MHz. In Fig. 2, the AD9913 is configured as a conventional DDS with a frequency tuning word of 262,160,001 (f0 ≈ 15.26 MHz). This is as close as a conventional DDS can get to an M/N ratio of 1,000/16,383, which is the programmable modulus setting used in Fig. 3. The difference in frequency between the two cases is only about 0.00136 Hz (approximately 1 MHz). Both traces appear nearly identical except for slight differences in spurious components.

In spite of its low power consumption, the AD9913 does not skimp on its waveform generation capabilities, and can generate linear frequency or phase versus time ramp waveforms. A user programs start and end points (32 b for frequency or 14 b for phase). Both ramp directions, start to end and end to start, are independently programmable with both step size and step rate parameters. These control parameters, along with other user control features, enable the generation of a wide range of modulated output signals. Fig. 4 shows an example of the waveform generation capability, with a time-domain plot of a frequency sweep from 1 to 10 MHz in 6 s (6 kHz steps in 4-ns intervals). The rising edge on the bottom trace indicates the start of the frequency sweep. The device was programmed to switch back to and remain at 1 MHz after reaching 10 MHz so that the end of the frequency sweep would be apparent on the trace.

Like many of the firm's DDS products, the AD9913 features an integrated reference clock multiplier that allows designers to consider lower-frequency clock sources. In addition to directly driving the device with a high-frequency clock source, a designer can use a lower-frequency clock source or crystal resonator with the AD9913's integral PLL (1X to 64X) frequency multiplier to generate the required internal 250-MHz sample clock. With the direct clock signal, the AD9913's reference clock (REFCLK) input port can accept either a differential or single-ended source.