Recently, the information technology industry has been accelerating its move to solve more and more computer science problems with heterogeneous and parallel computing. As many students know, parallel computing has historically been used to achieve the performance requirements of high performance computing (HPC) for specific engineering and scientific applications. Recent engineering grads today need to embrace how parallel computing has moved to center stage. From smart phones and tablets to large-scale data center clusters, almost all computer systems are being built using multicore platforms from Intel and other vendors.

This increase in the use of multicore systems in association with other technology innovations has led to the information technology industry’s use of heterogeneous and parallel computing. These solutions have been used to address problems as diverse as gaming, visualization of seismic data, high-speed analytics to catch threats to national security, as well as big data on large-scale clusters using MapReduce. Unfortunately, because of the cost and complexity of alternatives and the dominance and utility of the Intel architecture, computer engineering and computer science curricula have often been limited to CPU-oriented solutions for their teaching and undergraduate and graduate research.

Beyond the x86 architecture

Beyond the x86 architecture, various high-performance platforms and tools are available to address parallelization and acceleration techniques such as GPUs, cell processors, and FPGAs. Modern FPGAs are more than a bunch of configurable logic gates. They can rightly be called a system on chip (SoC) with multi-core processors and a rich set of peripherals. While in terms of raw capability they are an ideal platform to implement parallelism, they have been seen, with some justice, as difficult to use and to program. “Place and route” are three ugly words to many computer engineering students. That being said, with the right set of modern tools and platforms, engineering and computer science students with little hardware experience can write parallel algorithms and execute embedded designs with FPGAs.

New tools for new environments

Single vendor tools are available today such as ImpulseCoDeveloper that provides CPU-to-FPGA co-design with partitioning control that supports a wide range of FPGA-based systems. Another important tool called OpenCL is an open source high-level programing language that provides a framework for writing programs that execute across heterogeneous platforms: CPUS, GPUs, DSPs, FPGAs, and other processors. It has broad industry support from companies such as Intel, Advanced Micro Devices, Nvidia, and ARM Holdings. Additionally, OpenCL includes a C-friendly language for writing kernels, plus application programming interfaces (APIs) that are used to define and then control the platforms.

Thinking outside the box: a hybrid approach

Finally, thinking outside the box sometimes requires using the features of the box itself. Solarflare, the application acceleration and high-performance 10GbE networking company recently announced its University Program to enable the placement of its ApplicationOnloadTM Engine (AOE) in classrooms. The hybrid architecture of the AOE enables students to determine which portions of code benefit most from hardware processing, and which portions are most effectively processed in software on the host server. This approach provides students the ability to optimize their compute and network infrastructure for their application processing.

For classroom instruction in computer engineering, this architecture enables the instruction to focus on the application development since the entire data path is already built. Moreover, a kernel bypass user level library is available to accelerate portions of business logic that are amenable to acceleration on the host CPU in user space. The sweet spots for such instruction in computer engineering instruction and application development range from big data analytics, to software defined networks, to network security. All of which are key employment areas for graduates of computer science and computer engineering programs.

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Bruce Tolley is the Vice President of Solutions, Solarflare. He is responsible for solutions and outbound marketing including technical, event, and partner marketing activities. Prior to joining Solarflare, Tolley was a Senior Product Line Manager at Cisco Systems where he managed the Ethernet transceiver business, and launched Layer 2/3/4, Metro Ethernet, 10 Gigabit switches. Prior to Cisco, he served in various marketing management roles at 3Com Corporation. Formerly Study Group Chair of the IEEE 802.3aq 10GBASE-LRM standards project, Tolley has been a frequent contributor to the IEEE 802.3 Ethernet standards projects. He holds a BA from UC Santa Cruz, MA from Stanford University, MBA from Haas School of Business, UC Berkeley, and a PhD from Stanford University. Write to: btolley@solarflare.com