To increase the performance and reliability of
highly integrated circuits like DSP processors,
Microprocessors and SoCs, transistors sizes are continues to
scale towards Deep Submicron and Very Deep Submicron
dimensions . As more and more transistors are packed on the
chip to increase the functionality more metal layers are being
added to the integrated chips. Hence the performance of the
chips depends more on the performance of global interconnect
and on-chip busses than gate performance. The performance
of the global interconnects and on-chip data busses is limited
by switching activity, energy dissipation and noise such as
crosstalk, leakage, supply noise and process variations etc.
which are the side effects of the technology scaling. To increase
the performance of overall system it is necessary to control
and reduce these technology scaling effects on on-chip data
buses. One of the favorable techniques to increase the
efficiency of the data buses is to encode the data on the onchip
bus. Data encoding technique is the promising method to
increase the performance of the data bus and hence overall
system performance. Hence high performance data bus
encoding technique is propose which reduces switching
activity, transition energy dissipation, crosstalk and crosstalk
delay. The proposed method reduces the switching activity by
around 23%, energy dissipation by 46%, 6C, 5C and 4C type
crosstalk by around 89%, 73% and 31% respectively and
crosstalk delay by around 44% to 50% compare to unencoded
data.