As the industry has lowered its chip-testing costs over the years, IC test has been somewhat predictable. But in the emerging 2.5D and 3D chip era, IC test is entering the spotlight and the traditional test flow is under the gun. And there is a little-known debate brewing over a 3D design-for-manufacturing (DFM) standard over the test access architecture.

STMicroelectronics has integrated TSVs, embedded DRAM, and back biasing techniques to it 28nm CMOS platform, now moving towards production of a smartphone processor. The ultra-thin-body fully depleted SOI technology is cost effective because of fewer implant steps and a planar architecture, said STMicroelectronics program manager Franck Arnaud.

The MEMS foundry business is a paradox that is up for grabs. The balance of power could soon change as several silicon foundry vendors — such as GlobalFoundries, TowerJazz, SMIC, UMC, TSMC and X-Fab — will expand their efforts in MEMS. "In MEMS, you will see consolidation," said Peter Himes, vice president of marketing for MEMS foundry Silex.

The International Electron Devices Meeting will be held in Washington, D.C. in 2013 and 2015, but after that will be held annually in San Francisco, said IEDM 2011 chairman Kazunari Ishimaru. Since 1982, IEDM has alternated between Washington, D.C. and San Francisco, but attendance is significantly higher when it is held near Silicon Valley.

Amid the IC downturn, many chip makers are slowing down their fab expansion plans. But not all are in the same boat. Gearing up for demand from Apple Inc.'s iPad, iPhone as well as other end-user products, South Korea's Samsung Electronics Co. Ltd. is moving on three chip fronts, including plans to ramp its U.S. fab.

Intel senior fellow Mark Bohr said III-V and germanium channel materials may serve to reduce power consumption on future ICs while delivering good performance. In a plenary speech at the IEDM conference now underway in Washington, D.C., Bohr said "our real goal is good performance at lower voltage," noting that III-V transistors can operate at .5V.

IBM technologists said their fully depleted SOI transistors and ring oscillator test circuits are delivering performance competitive with the best-reported bulk finFETs. Bruce Doris, an IBM Albany research manager, said the work shows that "there is a bit of a misnomer out there that the bulk FinFET has superior performance."

Samsung had to work hard to overcome the performance degradation effects which come from simple scaling. External resistances, strain effects, and implant doping all get harder as the contacted poly pitch shrinks to 80nm.

Resistive RAMs (ReRAMs) are one of several next-generation memory candidates to succeed NAND flash, but there are material, production and cost issues associated with the technology. Elpida, Hynix, Micron, Panasonic, Samsung, Sharp and others are working on ReRAM. In fact, Micron and Sony have forged an alliance in ReRAM. And IMEC made a big announcement.

Last of three parts: Blurring the lines between packaging and manufacturing; progress on cross-disciplinary test and tools; issues in packaging, interconnect and test; who's in charge and driving changes; why tools are lagging for creating TSVs; who owns what; debate over whether the supply chain will grow or shrink.

Second of three parts: Starting points for stacking; where standards are needed; 2.5D vs. 3D stacks; the role of test; the challenge of interconnects; potential power shifts in terms of who's in control.

Following a record year in terms of semiconductor sales and unit shipments, 2011 turned into a lower growth year than initially expected with several challenges emerging for the packaging material suppliers.