Course Objective
Main Course Objective is to provide hands on knowledge in Digital VLSI using FPGA board. The program will focus on practical aspects and include examples which are relevant to the current industry requirements. Lab sessions will include the following:
• Digital Design concepts.
• FPGA design flow using Vivado.
• Clocking resources implementation in Vivado & Static timing analysis Vectorization.
• Block Memory implementation in vivado.
• FSM implementation in Vivado & XSIM simulation
• Vivado logic analyzer & its features
• Introduction to HLS
• Optimizing for Area and Resources