A Modified Partial Product Generator Using RADIX 4 to Remove ECW

Adders are the most important element of the arithmetic unit especially fast parallel adder. Redundant binary signed digit (RBSD) adders are designed to perform high speed arithmetic operations. Generally in a high radix modified booth encoding algorithm the partial products are reduced in multiplication process. While designing high performance multipliers a redundant binary (RB) representation can be used due to its high modularity and carry-free addition, The traditional RB multiplier requires an extra RB partial product (RBPP) row. Redundant binary representation (RBR) is a numeral system that uses more bits than needed to represent a single binary digit so that most numbers have several representation because an error-correcting word (ECW) is generated by both the radix-4 Modified Booth encoding (MBE) and the RB encoding. This results in an additional RBPP accumulation stage for the MBE multiplier. In this thesis, a new RB modified partial product generator (RBMPPG) is proposed; it removes the extra ECW therefore saves one RBPP accumulation stage. Hence the proposed work generates fewer partial product rows than a traditional RB MBE multiplier. Operation of the system over time show that the proposed work based designs considerably improve the area and power consumption when the word length of each operand in the multiplier is at least 32 bits; these reductions over previous NB multiplier designs incur in a modest delay increase (approximately 5 percent). By using the proposed RB multiplier design the power-delay product can be reduced by up to 59 percent when compared with existing RB multipliers.