As the lithography is both the most costly and critical process towards fully functioning semiconductor devices, it is obvious that developments within the lithography field are closely followed and analyzed. This year at the SPIE Microlithography Conference it became clear that a major shift in lithography tool and process techniques is required to continue scaling as befits Moore’s Law. EUV lithography is not going to be ready for Intel’s needs at the 32nm node while immersion lithography has not ‘matured’ enough for the chip giant to ‘risk’ production for its introduction of 45nm node IC devices. Instead, Intel plans to retain the use of ‘dry’ 193nm ArF DUV tools, while adopting a Double Patterning (DP) imaging regime through to the 32nm node. Although there are various DP strategies possible, few experts in the field believe that some form of throughput, cycle-time and cost impact on fab operations will not occur. Although not all leading-edge IC manufacturers may pursue a DP strategy, it would now seem certain that everyone will need to look deeply into the pros and cons before making such critical manufacturing decisions. We are very pleased to have been able to assemble in this discussion piece, a group of experts within the lithography discipline to cover some of the key issues surrounding DP strategies, especially at such short notice, so soon after the SPIE Conference.