Abstract:

An integrated circuit package system comprising: forming an area array
substrate; mounting surface conductors on the area array substrate;
forming a molded package body on the area array substrate and the surface
conductors; providing a step in the molded package body; and exposing a
surface conductor by the step.

Claims:

1. An integrated circuit package system comprising:forming an area array
substrate;mounting surface conductors on the area array substrate;forming
a molded package body on the area array substrate and the surface
conductors;providing a step in the molded package body; andexposing a
surface conductor by the step.

2. The system as claimed in claim 1 further comprising coupling an area
array device to the surface conductors.

3. The system as claimed in claim 1 wherein forming the molded package
body includes:electrically connecting a first integrated circuit to the
area array substrate;positioning a second integrated circuit over the
first integrated circuit; andinjecting a molding compound on the
substrate, the surface conductors, the first integrated circuit, and the
second integrated circuit.

4. The system as claimed in claim 1 wherein exposing the surface conductor
includes:forming contact pads on the area array substrate for mounting
the surface conductors;forming system contacts on the opposing side of
the area array substrate; andcoupling a via between the contact pad and
the system contact.

5. The system as claimed in claim 1 wherein providing the step in the
molded package body includes:forming a core section of the molded package
body; andreducing a step height from the core section for forming a
region surrounding the core section being coplanar to the area array
substrate including exposing the surface conductors.

6. An integrated circuit package system comprising:forming an area array
substrate having a component side and a system side;mounting surface
conductors on the area array substrate including pressing a solder
ball;forming a molded package body on the area array substrate and the
surface conductors including a core section;providing a step in the
molded package body including reducing a step height from the core
section for forming a region surrounding the core section being coplanar
to the area array substrate; andexposing a surface conductor by the step
for reducing a package height of a package stack.

7. The system as claimed in claim 6 further comprising coupling an area
array device to the surface conductors including coupling a flip chip
integrated circuit, a ball grid array package, or an interposer.

8. The system as claimed in claim 6 wherein forming the molded package
body includes:electrically connecting a first integrated circuit to the
area array substrate including coupling an electrical interconnect
between the first integrated circuit and the substrate;positioning a
second integrated circuit over the first integrated circuit including
applying a second adhesive; andinjecting a molding compound on the area
array substrate, the surface conductors, the first integrated circuit,
the second integrated circuit, and the electrical interconnect.

9. The system as claimed in claim 6 wherein exposing the surface conductor
includes:providing the area array substrate under the molded package body
including providing a laminate glass epoxy substrate, a ceramic
substrate, or a flexible tape substrate;mounting a flip chip integrated
circuit on the area array substrate including coupling a contact pad to
the flip chip integrated circuit;coupling a via to the contact pad;
andcoupling a system contact to the via.

10. The system as claimed in claim 6 further comprising:coupling an
embedded chip to the area array substrate;mounting a chip interconnect to
the active side of the embedded chip including coupling a third external
chip over the core section; andwherein:reducing the step height from the
core section for exposing the surface conductors including mounting a
first area array device and a second area array device.

11. An integrated circuit package system comprising:an area array
substrate;surface conductors mounted on the area array substrate; anda
molded package body, having a step, on the area array substrate and the
surface conductors includes the surface conductors exposed by the step.

12. The system as claimed in claim 11 further comprising an area array
device coupled to the surface conductors.

13. The system as claimed in claim 11 wherein the molded package body
includes:a first integrated circuit electrically connected to the area
array substrate;a second integrated circuit over the first integrated
circuit; anda molding compound on the area array substrate, the surface
conductors, the first integrated circuit, and the second integrated
circuit.

14. The system as claimed in claim 11 wherein the surface conductor
exposed includes:contact pads, on the area array substrate, with the
surface conductor mounted thereon;system contacts on the opposing side of
the area array substrate; andvias between the contact pads and the system
contacts.

15. The system as claimed in claim 11 wherein the molded package body
having the step includes:a core section of the molded package body; anda
step height reduced from the core section includes a region around the
core section that is coplanar to the area array substrate with the
surface conductors exposed.

16. The system as claimed in claim 11 further comprising:a component side
and a system side on the area array substrate;a solder ball, pressed, on
the area array substrate;a core section in the molded package body;a step
height reduced from the core section includes a region around the core
section that is coplanar to the area array substrate; anda package height
of a package stack reduced by the step height.

17. The system as claimed in claim 16 further comprising an area array
device coupled to the surface conductors includes a flip chip integrated
circuit, a ball grid array package, or an interposer.

18. The system as claimed in claim 16 wherein the molded package body
includes:a first integrated circuit electrically connected to the area
array substrate includes an electrical interconnect coupled between the
first integrated circuit and the area array substrate;a second integrated
circuit over the first integrated circuit includes a second adhesive
applied; anda molding compound on the area array substrate, the surface
conductors, the first integrated circuit, the second integrated circuit,
and the electrical interconnect.

19. The system as claimed in claim 16 wherein the surface conductor
exposed includes:a laminate glass epoxy substrate, a ceramic substrate,
or a flexible tape substrate as the area array substrate;a flip chip
integrated circuit on the area array substrate includes a contact pad
coupled to the flip chip integrated circuit;a via coupled to the contact
pad; anda system contact coupled to the via.

20. The system as claimed in claim 16 further comprising:an embedded chip
coupled to the area array substrate;a chip interconnect mounted to the
active side of the embedded chip includes a third external chip coupled
over the core section; anda first area array device and a second area
array device mounted on the surface conductors.

[0004]The present invention relates generally to semiconductor packaging,
and more particularly to an integrated circuit packaging system for
stacking an area array integrated circuit package.

BACKGROUND ART

[0005]The electronic industry continues to seek products that are lighter,
faster, smaller, multi-functional, more reliable and more cost-effective.
In an effort to meet such requirements, package assembly techniques have
been developed for multi-chip packages (MCP) and chip stack packages.
These types of packages combine two or more semiconductor chips in a
single package, thereby realizing increased memory density,
multi-functionality and/or reduced package footprint.

[0006]The use of several chips in a single package does, however, tend to
reduce both reliability and yield. If, during post assembly testing, just
one chip in the multi-chip or chip stack package fails to meet the
functional or performance specifications, the entire package fails,
causing the good chip(s) to be discarded along with the failing chip. As
a result, multi-chip and chip stack package may lower the productivity
from the assembly process.

[0007]A 3-dimensional package stack addresses this yield problem by
stacking several assembled packages that each contain a single chip and
that have already passed the necessary tests, thereby improving the yield
and reliability of the final composite package. However, package stacks
have tended to use lead frame type packages rather than area array type
packages. Lead frame type packages typically utilize edge-located
terminals such as outer leads, whereas area array type packages typically
utilize surface-distributed terminals such as solder balls. Area array
type package may therefore provide larger terminal counts and/or smaller
footprints when compared with corresponding lead frame type packages.

[0008]Thus, a need still remains for an integrated circuit package system
for package stacking. In view of the rate of development of consumer
electronics and the insatiable demand for multi-function devices at low
manufacturing costs, it is increasingly critical that answers be found to
these problems. In view of the ever-increasing commercial competitive
pressures, along with growing consumer expectations and the diminishing
opportunities for meaningful product differentiation in the marketplace,
it is critical that answers be found for these problems. Additionally,
the need to save costs, improve efficiencies and performance, and meet
competitive pressures, adds an even greater urgency to the critical
necessity for finding answers to these problems.

[0009]Solutions to these problems have been long sought but prior
developments have not taught or suggested any solutions and, thus,
solutions to these problems have long eluded those skilled in the art.

DISCLOSURE OF THE INVENTION

[0010]The present invention provides an integrated circuit package system
including: forming an area array substrate; mounting surface conductors
on the area array substrate; forming a molded package body on the area
array substrate and the surface conductors; providing a step in the
molded package body; and exposing a surface conductor by the step.

[0011]Certain embodiments of the invention have other aspects in addition
to or in place of those mentioned above. The aspects will become apparent
to those skilled in the art from a reading of the following detailed
description when taken with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1 is a cross-sectional view of an integrated circuit package
system for package stacking, in an embodiment of the present invention;

[0013]FIG. 2 is a cross-sectional view of an integrated circuit stack
using the integrated circuit package system for package stacking of FIG.
1;

[0014]FIG. 3 is a cross-sectional view of a package stack using the
integrated circuit package system for package stacking of FIG. 1;

[0015]FIG. 4 is a cross-sectional view of an interposer stack using the
integrated circuit package system for package stacking of FIG. 1;

[0016]FIG. 5 is a cross-sectional view of an interposer stack in an
alternative embodiment using the integrated circuit package system for
package stacking of FIG. 1;

[0017]FIG. 6 is a cross-sectional view of an integrated circuit package
system for package stacking, in a first alternative embodiment of the
present invention;

[0018]FIG. 7 is a cross-sectional view of an integrated circuit package
system for package stacking, in a second alternative embodiment of the
present invention;

[0019]FIG. 8 is a cross-sectional view of a package stack using the
integrated circuit package system for package stacking of FIG. 6;

[0020]FIG. 9 is a cross-sectional view of a package stack using the
integrated circuit package system for package stacking of FIG. 7;

[0021]FIG. 10 is a cross-sectional view of an integrated circuit package
system for package stacking, in a third alternative embodiment of the
present invention; and

[0022]FIG. 11 is a flow chart of an integrated circuit package system for
manufacturing the integrated circuit package system for package stacking
in an embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0023]The following embodiments are described in sufficient detail to
enable those skilled in the art to make and use the invention. It is to
be understood that other embodiments would be evident based on the
present disclosure, and that process or mechanical changes may be made
without departing from the scope of the present invention.

[0024]In the following description, numerous specific details are given to
provide a thorough understanding of the invention. However, it will be
apparent that the invention may be practiced without these specific
details. In order to avoid obscuring the present invention, some
well-known circuits, system configurations, and process steps are not
disclosed in detail. Likewise, the drawings showing embodiments of the
system are semi-diagrammatic and not to scale and, particularly, some of
the dimensions are for the clarity of presentation and are shown greatly
exaggerated in the drawing FIGS. Where multiple embodiments are disclosed
and described, having some features in common, for clarity and ease of
illustration, description, and comprehension thereof, similar and like
features one to another will ordinarily be described with like reference
numerals.

[0025]For expository purposes, the term "horizontal" as used herein is
defined as a plane parallel to the plane or surface of the package
substrate, regardless of its orientation. The term "vertical" refers to a
direction perpendicular to the horizontal as just defined. Terms, such as
"above", "below", "bottom", "top", "side" (as in "sidewall"), "higher",
"lower", "upper", "over", and "under", are defined with respect to the
horizontal plane. The term "on" means there is direct contact among
elements. The term "system" as used herein means and refers to the method
and to the apparatus of the present invention in accordance with the
context in which the term is used. The term "processing" as used herein
includes stamping, forging, patterning, exposure, development, etching,
cleaning, and/or removal of the material or laser trimming as required in
forming a described structure.

[0026]Referring now to FIG. 1, therein is shown a cross-sectional view of
an integrated circuit package system 100 for package stacking, in an
embodiment of the present invention. The cross-sectional view of the
integrated circuit package system 100 depicts an area array substrate 102
having a component side 104 and a system side 106. The area array
substrate 102 may be laminate glass epoxy resin, flexible tape, ceramic,
inorganic materials, low dielectric materials, semiconductor material, or
the like. A first adhesive 108 may be on the component side 104. A first
integrated circuit 110 may be positioned on the first adhesive 108 and
electrically connected to a contact pad 112 by an electrical interconnect
114.

[0027]A second adhesive 116, substantially similar to the first adhesive
108, may be positioned on the active side of the first integrated circuit
110. A second integrated circuit 118 may be mounted on the second
adhesive 116. The electrical interconnect 114 may electrically couple the
second integrated circuit 118 to the contact pad 112.

[0028]A surface conductor 120, such as a solder ball, solder column,
solder bump, or stud bump, may be mounted on the contact pad 112. The
surface conductor 120 may be made of tin, lead, gold, copper, metal
alloy, or other conductive material. The surface conductor 120 may be
flattened by coining or pressing prior to molding.

[0029]A molded package body 122, having a core section 123, may be formed
on the component side 104 of the area array substrate 102, the first
integrated circuit 110, the contact pad 112, the electrical interconnects
114, the second integrated circuit 118, and the surface conductor 120.
The molded package body 122 may be formed, of an epoxy molding compound,
having a step 124, such as a region coplanar with the area array
substrate 102 and surrounding the core section 123, that provides access
to the exposed portion of the surface conductor 120. The top portion of
the surface conductor 120 may remain clear of the molding compound by a
film assisted molding process whereby a film is applied to the portion of
the surface conductor 120 that is to remain exposed. The film may be
removed after the molded package body 122 is formed. Other materials or
processes may be used to keep the exposed portion of the surface
conductor 120 clear, such as a high temperature organic material inserted
into a mold.

[0030]The core section 123 may protrude above the step 124 and it encases
the first integrated circuit 110, the second integrated circuit 118, and
the electrical interconnects 114. The dimensions of the core section 123
may be adjusted to accommodate the electrical interconnects 114 with
higher wire loops for die with multiple row bonding pads.

[0031]A system contact 126, formed on the system side 106 of the area
array substrate 102, may be connected with the contact pad 112 by a via
128. The combination of the contact pad 112, the via 128 and the system
contact 126 may provide an electrical path through the area array
substrate 102. A system interconnect 130, such as a solder ball, solder
column, solder bump, or stud bump, may provide an electrical connection
to the next level system (not shown). FIG. 1 depicts all of the contact
pads 112 directly coupled to the system contacts 126, but this is by way
of an example only. In the actual implementation, there may be an
electrical connection formed between the first integrated circuit 110,
the second integrated circuit 118, the contact pad 112, the surface
conductor 120, the system interconnect 130, or a combination thereof.

[0032]It has been discovered that the step 124 may provide useful aspects
of the present invention. The molded package body 122 may use less of the
epoxy molding compound than current designs. It may also accommodate
stacking more integrated circuits while providing a package-on-package
platform that may reduce the overall package height of the final product.
The protruding portion of the molded package body 122 may act as a
stand-off for the upper package during reflow which may prevent the upper
package from over-collapsing. The presence of the molded package body 122
in the area of the step 124 may add rigidity to the area array substrate
102 having the surface conductor 120 and help prevent warping of the area
array substrate 102 during the manufacturing or assembly processes.

[0033]Referring now to FIG. 2, therein is shown a cross-sectional view of
an integrated circuit stack 200 using the integrated circuit package
system 100 for package stacking of FIG. 1. The cross-sectional view of
the integrated circuit stack 200 depicts the integrated circuit package
system 100 with an area array device 202, such as a flip chip integrated
circuit, coupled to the surface conductor 120 by a chip interconnect 204.
The chip interconnect 204 may be a solder ball, solder column, solder
bump, or stud bump, for electrically connecting the area array device 202
to the integrated circuit package system 100. The integrated circuit
stack 200 may have a package height 206 that is smaller than prior art
package by a step height 208.

[0034]It has been discovered that the molded package body 122 may support
the area array device 202 during a reflow process, thus preventing
over-collapse of the chip interconnect 204. It is also recognized that
the molded package body 122 may act as a solder resist to prevent the
chip interconnect 204 from spreading beyond the exposed portion of the
surface conductor 120. The size of the step 124 may be controlled in
order to allow a smaller diameter of the chip interconnect 204 on the
area array device 202. This smaller diameter of the chip interconnect 204
may allow for more of the chip interconnects 204 in a given area.

[0035]Referring now to FIG. 3, therein is shown a cross-sectional view of
a package stack 300 using the integrated circuit package system 100 for
package stacking of FIG. 1. The cross-sectional view of the package stack
300 depicts the integrated circuit package system 100 with an area array
device 302, such as a ball grid array package, coupled to the surface
conductor 120 by the chip interconnect 204. The area array device 302 may
be supported by the molded package body 122 during the reflow process of
assembly.

[0036]The package stack 300 may share all of the aspects of the integrated
circuit package system 100 as described above. These aspects may include
a reduced height and enhanced manufacturability.

[0037]Referring now to FIG. 4, therein is shown a cross-sectional view of
an interposer stack 400 using the integrated circuit package system 100
for package stacking of FIG. 1. The cross-sectional view of the
interposer stack 400 depicts the integrated circuit package system 100
with an area array device 401 including an interposer 402 coupled to the
surface conductor 120 by the chip interconnect 204. The interposer 402
may be supported by the molded package body 122 during the reflow process
of assembly.

[0038]The interposer 402 may have an interposer system side 404 and an
interposer component side 406. A discrete component 408, such as a
resistor, capacitor, inductor, diode, or the like, may be coupled to an
interposer contact 410 on the interposer component side 406 of the
interposer 402. An integrated circuit chip 412 may be coupled to the
interposer contact 410 as well.

[0039]This arrangement may allow a great deal of flexibility in the design
of the interposer stack 400. Any of the components mounted on the
interposer component side 406 of the interposer 402 may be electrically
connected to any component in the integrated circuit package system 100
or the system board (not shown) that may be coupled to the interposer
stack 400. Though the integrated circuit chip 412 is shown as a ball grid
array device, this is an example only and the integrated circuit chip 412
may be a quad flat no-lead (QFN), a leaded chip carrier (LCC), or another
type of packaged component.

[0040]Referring now to FIG. 5, therein is shown a cross-sectional view of
an interposer stack 500 in an alternative embodiment using the integrated
circuit package system 100 for package stacking of FIG. 1. The
cross-sectional view of the interposer stack 500 depicts the integrated
circuit package system 100, in an inverted position, with the system
interconnect 130 coupled to the surface conductor 120. An area array
device 501 including an interposer 502 having an interposer system side
504 and an interposer component side 506 may be coupled to the system
contact 126 of the area array substrate 102 by the chip interconnect 204.

[0041]The interposer 502 may support two or more of the integrated circuit
chip 412. In this configuration the height of the interposer stack 500
may be reduced from what is capable by the current practice. It has been
discovered that the protrusion of the molded package body 122 may act as
a support during the reflow assembly process. The molded package body 122
may prevent the over-collapse of the system interconnect 130 during
reflow.

[0042]Referring now to FIG. 6, therein is shown a cross-sectional view of
an integrated circuit package system 600 for package stacking, in a first
alternative embodiment of the present invention. The cross-sectional view
of the integrated circuit package system 600 depicts the area array
substrate 102 having the component side 104 and the system side 106. The
area array substrate 102 may be laminate glass epoxy resin, flexible
tape, ceramic, inorganic materials, low dielectric materials,
semiconductor material, or the like. The contact pad 112 may be
positioned on the component side 104 of the area array substrate 102. The
surface conductor 120 may be coupled to the contact pad 112 in the area
of the step 124. A flip chip integrated circuit 602 may be coupled to the
contact pad 112 by bumps 604, such as solder bumps, stud bumps, solder
balls, or the like.

[0043]The contact pad 112 may be coupled to the system contact 126 by the
via 128. The system interconnect 130 may be coupled to the system contact
126 on the system side 106 of the area array substrate 102. While FIG. 6
depicts all of the contact pads 112 directly coupled to the system
contacts 126, but this is by way of an example only. In the actual
implementation, there may be an electrical connection formed between the
flip chip integrated circuit 602, the contact pad 112, the surface
conductor 120, the system interconnect 130, or a combination thereof.

[0044]The molded package body 122 may be formed on the component side 104
of the area array substrate 102, the surface conductor 120, the flip chip
integrated circuit 602, and the bumps 604. It has been discovered that by
allowing the molded package body to encase the flip chip integrated
circuit 602 and the bumps 604, the overall package fatigue life and
reliability may be improved.

[0045]Referring now to FIG. 7, therein is shown a cross-sectional view of
an integrated circuit package system 700 for package stacking, in a
second alternative embodiment of the present invention. The
cross-sectional view of the integrated circuit package system 700 depicts
the area array substrate 102 having the component side 104 and the system
side 106. The area array substrate 102 may be laminate glass epoxy resin,
flexible tape, ceramic, inorganic materials, low dielectric materials,
semiconductor material, or the like. The contact pad 112 may be
positioned on the component side 104 of the area array substrate 102. The
surface conductor 120 may be coupled to the contact pad 112 in the area
of the step 124. The flip chip integrated circuit 602 may be coupled to
the contact pad 112 by the bumps 604, such as solder bumps, stud bumps,
solder balls, or the like.

[0046]The contact pad 112 may be coupled to the system contact 126 by the
via 128. The system interconnect 130 may be coupled to the system contact
126 on the system side 106 of the area array substrate 102. While FIG. 6
depicts all of the contact pads 112 directly coupled to the system
contacts 126, but this is by way of an example only. In the actual
implementation, there may be an electrical connection formed between the
flip chip integrated circuit 602, the contact pad 112, the surface
conductor 120, the system interconnect 130, or a combination thereof.

[0047]The molded package body 122 may be formed on the component side 104
of the area array substrate 102, the surface conductor 120, the flip chip
integrated circuit 602, and the bumps 604. In this configuration, the
inactive surface of the flip chip integrated circuit 602 may be exposed
to the outside of the package. It has been discovered that by allowing
the molded package body to encase the flip chip integrated circuit 602
and the bumps 604, the overall package fatigue life and reliability may
be improved.

[0048]Referring now to FIG. 8, therein is shown a cross-sectional view of
a package stack 800 using the integrated circuit package system 600 for
package stacking of FIG. 6. The cross-sectional view of the package stack
800 depicts the integrated circuit package system 600 with the area array
package 302, such as a ball grid array package, coupled to the surface
conductor 120 by the chip interconnect 204. The area array package 302
may be supported by the molded package body 122 during the reflow process
of assembly.

[0049]The package stack 800 may share all of the aspects of the integrated
circuit package system 600 as described above. These aspects may include
a reduced height and enhanced manufacturability.

[0050]Referring now to FIG. 9, therein is shown a cross-sectional view of
a package stack 900 using the integrated circuit package system 700 for
package stacking of FIG. 7. The cross-sectional view of the package stack
900 depicts the integrated circuit package system 700, in an inverted
position, with the system interconnect 130 coupled to the surface
conductor 120.

[0051]The integrated circuit chip 412 may be coupled directly to the
system contact 126. In this configuration the height of the package stack
900 may be reduced from what is capable by the current practice. It has
been discovered that the protrusion of the molded package body 122 may
act as a support during the reflow assembly process. The molded package
body 122 may prevent the over-collapse of the system interconnect 130
during reflow.

[0052]Though the integrated circuit chip 412 is shown as a ball grid array
device, this is an example only and the integrated circuit chip 412 may
be a quad flat no-lead (QFN), a leaded chip carrier (LCC), or another
type of packaged component. This configuration may support multiples of
the integrated circuit chip 412 or a combination of the discrete
components 408 and the integrated circuit chip 412.

[0053]Referring now to FIG. 10, therein is shown a cross-sectional view of
an integrated circuit package system 1000 for package stacking, in a
third alternative embodiment of the present invention. The
cross-sectional view of the integrated circuit package system 1000
depicts the area array substrate 102 having the component side 104 and
the system side 106. The area array substrate 102 may be laminate glass
epoxy resin, flexible tape, ceramic, inorganic materials, low dielectric
materials, semiconductor material, or the like. The contact pad 112 may
be positioned on the component side 104 of the area array substrate 102.
The surface conductor 120 may be coupled to the contact pad 112 in the
area of the step 124.

[0054]An embedded chip 1002, such as a wafer level chip scale package, a
redistributed line die, an area array package, or the like, may be
mounted on the component side 104 an adhesive 1004. The embedded chip
1002 may be electrically coupled to the contact pad 112 by the electrical
interconnect 114. The chip interconnect 204 may be electrically connected
to an interconnect pad 1006 on the active surface of the embedded chip
1002.

[0055]The molded package body 122 may be formed on the component side 104
of the area array substrate 102, the surface conductor 120, the embedded
chip 1002, the electrical interconnect 114, and the chip interconnect
204. The chip interconnect 204 may be partially exposed from the molded
package body 122, in a fashion similar to the surface conductor 120. A
first area array device 1008, such as ball grid array, flip chip
integrated circuit, or the like, may be coupled to the exposed portion of
the surface conductor 120 in the area of the step 124.

[0056]A second area array device 1010 may be similarly mounted to the
surface conductor 120 in another portion of the step 124. A third
external chip 1012, such as a flip chip die, a quad flat no-lead package,
or the like, may be coupled to the exposed portion of the chip
interconnect 204 embedded in the molded package body 122 over the
embedded chip 1002.

[0057]The contact pad 112 may be coupled to the system contact 126 by the
via 128. The system interconnect 130 may be coupled to the system contact
126 on the system side 106 of the area array substrate 102. While FIG. 10
depicts all of the contact pads 112 directly coupled to the system
contacts 126, but this is by way of an example only. In the actual
implementation, there may be an electrical connection formed between the
embedded chip 1002, the first area array device 1008, the second area
array device 1010, the third external chip 1012, the contact pad 112, the
surface conductor 120, the system interconnect 130, or a combination
thereof.

[0058]Referring now to FIG. 11, therein is shown a flow chart of an
integrated circuit package system 1100 manufacturing the integrated
circuit package system 100 for package stacking in an embodiment of the
present invention. The system 1100 includes forming an area array
substrate in a block 1102; mounting surface conductors on the area array
substrate in a block 1104; forming a molded package body on the area
array substrate and the surface conductors in a block 1106; providing a
step in the molded package body in a block 1108; and exposing a surface
conductor by the step in a block 1110.

[0059]It has been discovered that the present invention thus has numerous
aspects.

[0060]An aspect that has been unexpectedly discovered is that the present
invention may provide a package-on-package stacking system that can
reduce the vertical height of the final package. By increasing the number
of functions provided in a smaller space, two main objectives of consumer
electronics may be achieved; higher chip density and simplified system
board routing.

[0061]Another aspect is the integrated circuit package system for package
stacking of the present invention may provide additional rigidity to the
substrate, making the finished product more reliable and easier to
manufacture.

[0062]Yet another important aspect of the present invention is that it
valuably supports and services the historical trend of reducing costs,
simplifying systems, and increasing performance.

[0063]These and other valuable aspects of the present invention
consequently further the state of the technology to at least the next
level.

[0064]Thus, it has been discovered that the integrated circuit package
system of the present invention furnishes important and heretofore
unknown and unavailable solutions, capabilities, and functional aspects
for package-on-package devices providing multiple functions in a minimum
of space. The resulting processes and configurations are straightforward,
cost-effective, uncomplicated, highly versatile and effective, can be
surprisingly and unobviously implemented by adapting known technologies,
and are thus readily suited for efficiently and economically
manufacturing package-on-package devices fully compatible with
conventional manufacturing processes and technologies. The resulting
processes and configurations are straightforward, cost-effective,
uncomplicated, highly versatile, accurate, sensitive, and effective, and
can be implemented by adapting known components for ready, efficient, and
economical manufacturing, application, and utilization.

[0065]While the invention has been described in conjunction with a
specific best mode, it is to be understood that many alternatives,
modifications, and variations will be apparent to those skilled in the
art in light of the aforegoing description. Accordingly, it is intended
to embrace all such alternatives, modifications, and variations that fall
within the scope of the included claims. All matters hithertofore set
forth herein or shown in the accompanying drawings are to be interpreted
in an illustrative and non-limiting sense.