DFM: just what doctor ordered

Nice, France -- As design-for-manufacturing and design-for-yield take on critical importance at the 65-nanometer node, discussions proceed apace about how best to handle them. At the recent Design Automation and Test in Europe conference here, experts from chip, EDA and foundry companies used a medical metaphor to frame the debate, asking whether it's better to be "surgeons" who deal with DFM and DFY issues at tapeout or "family doctors" who, with an eye toward prevention, minister to the design starting at the register transfer level.

The consensus: Prevention is always advisable, but surgery may be unavoidable at technology's bleeding edge.

Numerous preventive approaches can be applied when using and developing intellectual property, said ARM Ltd. fellow Rob Aitken. For lithography issues, options depend on the type of IP. A key issue is maximizing DFM compliance without unduly increasing die area. For some classes, such as I/O and analog IP, all foundry DFM recommendations can be followed. For soft IP, recommendations for use of physical IP as well as DFM-friendly reference flows can be provided.

A challenge for the family-doctor approach, Aitken said, is a lack of data: When IP is being developed, mass production in a process node has not begun, so subtle effects are often unknown. Careful design practices can anticipate some issues and avoid them, but the process cannot be perfect.

Similarly, a challenge for the surgical approach is a lack of patient history. "Just as the appropriate treatment of a torn ligament will change depending on whether or not one intends to participate in an upcoming triathlon, the appropriate treatment for design issues changes depending on the criticality of the circuit, the yield and performance targets of the design and other critical factors," Aitken said. "Of course, no matter how much preventive medicine is used, it's good to know that a surgeon is available if you need one."

Antun Domic, senior vice president and general manager of the implementation group at Synopsys Inc., observed that "at 65 nm, design and manufacturing can no longer be handled separately." Physical synthesis has been extended to encompass DFM/DFY, slashing the number of iterations and respins that would otherwise be needed to correct the thousands of problems detected at GDSII (the tapeout specification that links the design process with manufacturing).

"GDSII is just too late and too costly for the correction of topologies that may be critical for particle-induced defects, chemical-mechanical planarization or lithography-related issues," Domic said. He concluded that "surgery is not bad per se, but prevention is better."

As the industry has advanced from 90 to 65 to 45 nm, said Carlo Guardiani, senior director of DFM at PDF Solutions Inc., yields for complex systems-on-chip built with new technologies are increasingly dictated by systematic and variability effects that are probabilistic functions of the actual circuit layout properties.

Every process technology, Guardiani said, is characterized by a unique set of yield sensitivities that is determined by the choice of process integration, lithography equipment and resolution-enhancement technology recipes and equipment calibration. Unless those process sensitivities are accurately quantified and their impact on product yield properly modeled, he said, it is impossible to predict that a particular design choice will always be yield-savvy.

Jean-Pierre Schoellkopf, director for advanced design at STMicroelectronics, said that until the 0.13-micron node, "if you could manufacture each structure, you could manufacture the entire chip--what you designed on the polygon layout tool was what you got on the wafer." Engineers had simple design rules with yes/no, pass/fail criteria for the design rule checker. In "the rare case of an emergency," Schoellkopf said, the surgeons ruled the day.

Today, at 65 nm and beyond, features are manufactured with 193-nm lithography, causing an order-of-magnitude increase in the number of defects and faults. One result is that at 65 nm, the cost of test per transistor is only 200 times lower than the cost of manufacturing, vs. the 1,600x differential seen at 130 nm, said Schoellkopf.

"Designers and process engineers need to collaborate in analyzing the variables that contribute to critical design specifications," he said. "This means that manufacturability must start at the chip design level. The family doctors, with their deep knowledge of the patient's clinical history, can play a fundamental role.

Schoellkopf warned, however, that it is not enough to include DFM specifications in physical design and verification tools, since that method not address how various components will react to each other when integrated into a system-on-chip. That requires looking across hierarchical boundaries to see how the data in one cell interacts with data outside the cell, since it might be possible to improve the manufacturability of one layer by manipulating another.

This more-comprehensive model requires a new infrastructure that supports a feedback loop between designer and manufacturer. The feedback loop should include means of modeling the manufacturing constraints, verifying IC layouts and translating manufacturing-related issues for the designer.

"To make this feedback loop possible," said Schoellkopf, "a complete cultural revolution must take place whereby designers understand the constraints of the lithography experts and, conversely, the yield production engineer participates up-front in the design and design-for-test reviews, inducing a design-for-yield mentality in the design teams."

Douglas Pattullo, technical director for Netherlands-based Taiwan Semiconductor Manufacturing Co. unit TSMC Europe BV, maintained that the core issue is not the skill set of a "surgeon" or a "family doctor," but which one knows the "patient" best and is most focused on that customer's well-being.

"Fundamental here is the knowledge of the operators," said Pattullo. "For the health of my chip, I want to rely on somebody I know, somebody who has experience in the diagnosis and treatment of diseases, and somebody with an analytical mind so that they can use their knowledge base to determine the best treatment, whether that would be a daily vitamin pill or triple-bypass surgery."

Perhaps not surprisingly, Pattullo claimed that foundries are in the best position to determine the patient's condition. "In this analogy, the foundries work like a central medical-records departments for the associated hospitals, clinics, teaching establishments and research groups," he said. The foundries may have produced test chips two years or more before the fabless vendor submits its first design, and they have already seen the success and failure of different implementations.

TSMC believes its DFM Unified Format (DUF) enables it to share essential manufacturing knowledge in a model-based format. The DUF can be used by all parties in a domain familiar to them while protecting their intellectual property. "Working in close collaboration with more than 20 partners, DDKs [DFM design kits] based on this DUF are now available for TSMC's most advanced technologies," said Pattullo.

Joe Sawicki, vice president and general manager of the design-to-silicon division of Mentor Graphics Corp., concurred with the need to find flexible approaches. Sawicki recalled that in a recent customer engagement, Mentor analyzed routing from two tools for litho hot spots. In one moderately sized case, one of the tools gave approximately 600 Category 1 errors; the other tool gave three.

"In the end, each approach has an important role to play," said Sawicki. The design must be delivered downstream meeting the vast majority of manufacturing requirements. Then the DFM tool needs to have sophisticated, flexible analysis and improvement algorithms in place to handle the last--and thereby the most difficult--problems.

And the family physician and surgeon need to consult with each other to ensure the health of the chip, said Sawicki.