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Re: BRAM Acces to write it from PL and read from PS and compute that data

One more confusion I have regarding BRAM read and write / access operation on linux based platform..

I have done the DDR access from PS using "mmap" function call and using "/dev/mem/" access on linux platform.. But when I will need linux platform based BRAM access will this library "xil_io.h" will be valid method for this or any other way to access BRAM on linux platform.

Re: BRAM Acces to write it from PL and read from PS and compute that data

sir can give me the pl code,for that fsm which u mentioned,i have nobody to guide me at my current place,as iam still learning,but this is a part of my project which i should submit,please attach me this pl code,as i can learn how to infer it..please sir send it as soon as possible

Re: BRAM Acces to write it from PL and read from PS and compute that data

i have an axi BRAM controller,connected to Dual port BRAM...port a of dual port bram writes data from PS,and port B Reads data from PL,FSM that reads the data on each address, adds 1 to it, and writes it back. to Read from pl..please help..i can description of code

Re: BRAM Acces to write it from PL and read from PS and compute that data

I just made a custom ip, package it and then include it in the Block Diagram. I am reading from Port A of BRAM from PS side and writing from Port B of BRAM.

Basically on the rising edge of the clock I am updating the data and address by addition of four as shown below. The data and address signals are initialized by 32 bit zeros, please see the source code in attachment.

Re: BRAM Acces to write it from PL and read from PS and compute that data

@sam007, I don't have the time at the moment to write you a FSM, but in the past I did put a good FSM example on the forum, after getting great input from other people.

The FSM uses a 'single process' approach (vs. the classical 2 or 3 process aproach found in books), which makes it very simple to read and understand. This 'single process' approach is also shown in UG901 (Synthesis, chapter 4, HDL coding techniques). Please checkthe code in this answer of the threadt, it should get you going with FSM's. Also read the entire thread from the start, so you can understand it better, there's some great explanation by other forum users on my questions.

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Re: BRAM Acces to write it from PL and read from PS and compute that data

Re: BRAM Acces to write it from PL and read from PS and compute that data

thanks for the reply,but can u explain me the logic,but iam comfortable in verilog...can you suggest me that and can u explain me the logic quoted by you,"you could for example build an FSM that reads the data on each address, adds 1 to it, and writes it back. Then you'll also need something to trigger a 'start' of this caluclation, and optinally signal an end. A small example will help...

HERE I WAS GETTING OUTPUT ON TERTERM,SO DIDNT NEED ILA.

Iam having a problem in implementing the functionality of The "FSM" you suggested please help me out,with the logic part.BLOCK diagram for PS READ AND WRITE THROUGH PORT APS READ AND WRITE OUTPUT IN TERATERM...AS YOU ASKED.PS_PROGRAM FOR READ AND WRITE ..HERE IAM READING THE PL ADDRESS OF AXI BRAM CONTROLLER,AND THUS RESULT IS SHOWN

Re: BRAM Acces to write it from PL and read from PS and compute that data

@sam007, please be a bit more patient ... I'm probably living in a different time zone, and I don't wake up at night to answer forum questions :-)

1) First of all : the screenshot with the waveforms : is this from your simulator? If so, can you add more 'internal signals' to it, like 'state', so you can see the different states your FSM is going through. Better to put enough signals there, so we can see better what's going on there

2) if you would have used 'enum' to name your states, it will be even more easy to see the states in the simulation output, checkout for example this 5 minute video on how to do this

3) can you tell me what you're trying to accomplish in this part of the code - it looks strange to me, like a 'state' (RAM_OPERATION) inside a 'state' (INIT_STATE) - again, I'm not a Verilog programmer, so this might be correct, but it looks kinda strange to me :

5) In your simulation I think your 'we' should be already high when you write the value 'h0a3d70a3'

6) referring to your block diagram : where exactly is this FSM packaged in? Did you build a custom IP with this FSM code inside of it, and named it 'block memory generator' ?? Or are are you just simulating your code and haven't packaged it yet into a custom IP?

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and tell me what i need to do,in order to correct that...I have shared my code.....

4.) I havent packaged it...since iam checking functionlity....

5.)i have attached the simulation shots and the DUT and testbench...

6.) Here since you discussed about this logic"you could for example build an FSM that reads the data on each address, adds 1 to it, and writes it back. Then you'll also need something to trigger a 'start' of this caluclation, and optinally signal an end."..i have written that code itself...and there is one code in VHDL which they tried the same logic...please guide me on how to use it...iam attaching that to...

Re: BRAM Acces to write it from PL and read from PS and compute that data

@sam007, I'd try to find a verilog tutorial that first gives you a working module and testbench, so you can start from that. I googled a bit and found the one attached. I really think you should calm down and have a look at that tutorial first. you'll win back that time later.

Looking at that code quickly, I think at least one issue is here :

I think you should end your init state here. If you do so, you'll need to remove one 'end' statement at the bottom of your code.

Then next, your testbench looks incomplete - you should define signals for all inputs (stimuli) of your DUT, these are :

If I'm correct, you're not defining anything for data_in and address, hence the red signals ..

Also, look at your simulation : next_state shows that immediately after reset ends, you go from 0 -> 1 -> 2 -> 3 -> 4, and you seem to stay in '4' forever ... ? So there's one of your issues I guess, but to be honest, your design looks unclear to me ...

try to draw your system on paper : start drawing an FSM block and a BRAM block, and see how these connect. Then create 2 verilog source files, one for the BRAM, one for the FSM, then hook both up in a testbench. I'm confused by your files : you also showed a screenshot of 'counter_data.vhd' which is a VHDL file... I don't see how / where that is connected to your FSM or BRAM ...?

Also, check UG937 - Logic Simulation Tutorial - it might take you a few hours to go through this, but you'll have a good verilog code and testbench example.

I really recommend you reading a good Verilog book that approaches things in a modular way, you'll win all that time back. A good book IMHO is from Pong P. Chu, it's rather old, but still a good one to start with. He has many other good books.

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Re: BRAM Acces to write it from PL and read from PS and compute that data

i have done changes,here it goes

1.) I have added that "end" in the INIT state,and thus there is a more Systematic flow to the FSM.

2.)i have defined the "Data_in" and "Address values" in the Testbench. I have a Question... is it Required to define these values in the DUT.(ie;0a3d70a3,values so on...) TESTBENCH ATTACHED TOO.

3.) In the simulation it is not getting stuck at that "4" state...but atleast DATA_IN and DATA_OUT are kindof Matching..where DATA_IN is being incremented,and DATA_OUT Increment occurs..(SIMULATION SNAPSHOT ATTACHED)

4.) I Have attached a changed version of this code.(DUT AND TESTBENCH).So i want to understand one thing...BRAM is just basic READ/WRITE..right? or is there something else more to be added within the bram.

Re: BRAM Acces to write it from PL and read from PS and compute that data

sir there is increment in data_out values because of the "data_in <= data_in + 32'h04000004"let me know on this!!,is this simulation,correct..?let me know...i have attached the code were "i have combined both the BRAM and the FSM in one verilog file". sorry for asking ..stupid questions,at the start..

Re: BRAM Acces to write it from PL and read from PS and compute that data

@sam007, not yet sure what's going on, it incremented the lowest byte with 4 and highest byte with 4 too..

again, I think you should design in a more modular way :

create 1 separate file which is the RAM, see for example UG901 (Synthesis guide) on how to infer RAM in code. Later, you will probably replace this RAM module with the Block Memroy Generator + dual port RAM IP in the block diagram. Separating the RAM into 1 module will also simplify your understanding of what is happening.

So in UG901 in the link I gave you, check on page 111 for 'rams_sp_rf_rst.v', and build yourself a separate memory module. (there's are many ways to build a RAM shown in that chapter, single-port, dual-port, and so on. But start with a simple single-port block ram).

Then create a 2nd file for your FSM. Think of your FSM as a 'controller' that connects to the RAM (like a microprocessor). Draw a block diagram of your FSM module connecting to that single port RAM module (connect the ports like dout, we, addr, from the FSM block to the memory). So you need to see 2 blocks on paper, 1 FSM block, 1 RAM block, and then a bunch of connections. Your FSM will then generate all the signals to control the operation of that RAM. The RAM is just a 'slave' module to the FSM.

To make these 'connections', create a 3rd file, which will be your testbench. In that testbench, you instantiate and hook up both the RAM module and FSM with each other, and generate stimuli to your FSM (clock, reset, enable) and RAM (clock, reset). The we, data, ... for the RAM are generated by the FSM.

you really need to think modular, and I also think you should hold your breath, step back a little, read a good verilog book, start from some working examples (like UG937 Logic simulation tutorial), and then move on. I'm sorry I cannot help you much with verilog, but if you make a clean block design and think modular, I"m sure you'll get there. Also checkout that UG901 further, chapter 4 shows a lot of coding techniques, also for FSM on page 162

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