In many applications it is acceptable to allow a small
error in the result if significant improvements are obtained in
terms of performance, area or energy efficiency. Exploiting this
principle is particularly important for FPGA-based solutions that
are inherently subject to many resources- oriented constraints.
This paper devises an automated method that enables to approximate
circuit components which are often implemented in
multiple instances in FPGA-based accelerators. The approximation process starts with a fully functional gate-level circuit, which
is approximated by means of Cartesian Genetic Programming
reflecting the error metric and constraints formulated by the
user. The evolved circuits are then implemented for a particular
FPGA by common FPGA synthesis and optimization tools. It is
shown using five different FPGA tools, that the approximations
obtained by CGP working at the gate level are preserved at the
level look-up tables of FPGAs. The proposed method is evaluated
in the task of 8-bit adder, 8-bit multiplier, 9-input median and 25-input median approximation.