The WDT circuit asserts a hardware reset to the device after a preprogrammed interval, unless it is periodically serviced in firmware.

The value of the reset status register (RESET_SR0) is read and cleared any time the device is booted. That value is saved to a global SRAM variable. The watchdog reset (WRES) and software initiated reset (SRES) sources preserve the RESET_SR0 register. For more information, refer to the device TRM(page#142) available at these link-