No, there are certain limitations of the twin tub technology and N-well technology is world wide preferred in the foundries. So we provide N-well technology.

Q2 Can we modify or create our own technology file?

Yes you can have your own technology file or modify the existing technology file by opening it in notepad and save it as ".rul" file.

Q3 Can we edit to one particular layer and keep others protected in nano lambda?

Yes, by using the 'Protect Layer' option from the 'Edit' menu you can protect selected layers and edit others.

Q4 Can we generate bus in the layout editor (nanolambda) ?

Yes, you can generate bus of the desired parameters by going to the layout generator window from layout palette, selecting the bus menu giving the desired bus parameters and pressing the generate bus button.

Q5 Can we import spice netlist?

No, but you can export your layout in spice file format.

Q6 How to import complete layout from other file?

By using 'insert layout' option from the file menu we can insert complete layout at the right side of the current layout.

Q7 How to find the percentage of memory and area used or remaining while designing?

You can find the percentage of memory and area used or remaining while designing from the 'properties' option in the file menu. It gives the number of devices and nodes.

Q8 How to see critical path of a particular node?

By double clicking on the particular node or from 'view electrical node' option in the view menu. And to unselect press escape.

Q8 How to remove lambda grid?

By disabling the lambda grid from the view menu.

Q10 How to get the number of MOS devices and their sizes?

To view the MOS list, go to the view menu and select the MOS list option.

First go to the edit menu ,select 'duplicate XY' option ,then select the portion you want to duplicate ,now give the multiplication factor for both x and y or you can also give the data to the array in the hexadecimal format.

Q13 Why buried layers are not shown in the technologies beyond the 90nm technology?

Because buried layers does not exists with these technologies.

Q14 How to connect the two nodes with continuous path?

To generate the continues path go to the 'layout generator', select the 'path' option' then give the desire parameters like width, number of contacts, metal for the path etc.

Q15 How to simulate design with virtual capacitor?

By using the capacitor symbol present in the palette and assigning value to it.

Q16 Can we edit the properties of the MOS FETs used in the design?

Yes, from the layout generator you can change the properties (low leakage high speed, high voltage ) of the MOS FETs used in the design.

Q17 Does it supports series or parallel combination of identical devices?

Yes, to choose this option we have to mention number of figures in MOS layout generator.

We can control the padding by setting pad generation either as free placement in which by default pad position is set or by the loading the IBIS file in which pad assignment is planned before going for the compilation of the file.

Q2 How can we give size parameters in the one line compiler?

You can not directly give the size parameters in the one line compiler.For that you have to set the compiler for the desired size, then go for the one line compilation.

Q3 How can we get the inverted output of the layout?

The one line compiler in the compile menu will join an inverter at the output of the layout and we can have the inverted output.