The full VCS documentation may be found at:
/projects/cad/synopsys/vcs/vcs-mx_vX-2005.06-SP2/doc/
In particular the vcsmx_ug.pdf (VCS User Guide) and the vcsmxqr.pdf (VCS Quick Reference Guide) may be useful.
(note: these links will only work from CS unix machines)

Verilog HDL

Verilog HDL is a functional verification and simulation
language for digital systems. There are many sources of information
available on the web for verilog, here are a few highlights:

There is a free (GPL'ed) verilog mode for
emacs available at verilog.com. It can be extremely useful for
those that use emacs as their primary editor. It has auto
indentation, context sensitive colored highlighting, signal and
command completion as well as pre-processor type functions.