1.1 Comparing Synchronous and Non-Synchronous DC/DC Converters

Hi, my name is Anston Lobo, and I am a Systems and Applications engineer with the Simple Switcher group at Texas Instruments. Today, we are going to discuss two very popular converter architectures present widely in the broad marketplace.
First, let's take a look at a simplified schematic to explain the fundamental differences between them. As you can see in the top left image here, the non-synchronous buck converter consists of the top side switch and a controller to regulate its switching. The low side switch is typically a quick recovery diode such as a Schottky.
The synchronous architecture takes the non-synchronous architecture one step into the future and integrates the low side switch within the monolithic die. This enhances several key characteristics of the buck regulator and makes it even easier to implement.
The wave forms on the right show the inductor current during switching action. Under heavy load, as you can see here, the wave forms for both architectures look indistinguishable, and this is ideal.
Under light load we have the standard non-synchronous behavior, where the inductor current levels off at zero, thanks for the diode's conduction path. And the analogous synchronous version of that is called the synchronous discontinuous mode, or DCM, as you can see here. The low side switch in the DCM mode is turned off when it senses inductor current approaching zero. This emulates the diode feature in a non-synchronous architecture.
In synchronous, we also have a new mode to play with called the synchronous forced PWM mode. PWM stands for Pulse Width Modulation. In this mode, the low side switch remains on, in spite of the inductor current going past zero, and allows this current to go negative. While this negatively affects efficiency, it allows a host of other features, such as a flyback topology to be made possible. It also allows the frequency to be held constant instead of folding back for constant frequency critical applications.
Now let's take a look at the solution size and the cost impact between these architectures. Because we integrated an additional low side FEt into the IC, the cost of the IC is slightly higher. This is primarily due to the increased die space, sophisticated controller, and driving circuitry. We also need to optimize the thermal characteristics of the package since we now have an integrated low side switch, which is the diode's counterpart in the non-synchronous architecture.
The benefits of it are significant. We now have a much smaller solution size in the synchronous design and a highly optimized cutting path for large switching currents. The diode no longer takes up bulky solution space, and we save on the costs of this added diode.
Designing a synchronous converter is very easy. There is no need for a Schottky diode, and the current paths are optimized by virtue of the pin configuration of the pin out of the part. The non-synchronous converter, however, has a diode to contend with, and this means having to worry about various diode considerations, such as a reverse voltage rating, which is dependent on the maximum input voltage of your application.
There is also the forward current rating to worry about, which is the maximum load current added with half the inductor ripple. The forward voltage of the diode varies over current and temperature, and this leads to conduction losses. The reverse leakage current also varies over temperature and adds to this loss.
Finally, did our diode parasitic [? suggest ?] capacitance? That is an increased heat dissipation due to losses in the diode, and the size varies with the reverse voltage rating and the forward current rating.
Now let's quickly evaluate a very commonly used power diode characteristic. Keeping instantaneous forward current constant, we can see that as temperature increases from minus 25 degrees C to 125 C the forward voltage does not remain constant. It drops by an order of 0.1 volts for every 50 degrees C rise in temperature. The instantaneous reverse current, our leakage current, increases tenfold with every 50 degrees C rise in temperature.
Now, these characteristics are much, much smaller with an integrated low side FET, as in the case of a synchronous design, thereby increasing the efficiency during light load. The critical part for EMI is now also much smaller for a synchronous converter since the low side FET is integrated. Let's take a look at this example.
During the conduction portion of the high side switch, the critical part is shown in red. During the conduction part of the low side FET, the current part is shown in magenta. To optimize this design, we have to reduce the critical path, which is switching currents between the input capacitor, topside FET, and low side FET. And this is the key to accomplishing a good PCB layout.
Now let's take a look at optimizing EMI a little closer. In a non-synchronous design, it is a lot harder to design a compact PCB, and thereby optimize EMI due to this added diode. However, in a synchronous design, since the low side FET is integrated, the pin out is the only thing standing between a good layout and improved EMI. This means that a non-synchronous design must be carefully laid out even more so than a synchronous design.
A practical example shows us the impact the input capacitor placement can have on minimizing this critical path. In the example here, the input capacitor is placed as close as possible to the input pins of the IC. You can see that the switch voltage just is at 14 and 1/2 volts, and the peak to peak output ripple is about 47 millivolts. We can also see that our EMI peaks out at about 41 dB microvolt per meter.
By placing our input capacitor a little further away, we have now increased this area by 2 and 1/2 times, causing our switch voltage to increase from 14 and 1/2 to 18.1 volts. And our output ripple also increases to 75 millivolts peak to peak. As you can see, we no longer pass [INAUDIBLE] 22 class B because of the added EMI noise. This table summarizes what I just talked about.
Since a synchronous architecture brings with it the highest improvements at light load, let's take a look at how this is possible. Here we have a slide that shows the light load efficiency comparison between the non-synchronous and synchronous architecture. As you can see, the negative inductor current is blocked from traveling below zero by the blocking action of the diode. The synchronous architecture has a similar feature.
Whereby not switching on the low side FET, we prevent inductor current from going negative. Since we can control the low side FET and allow it to conduct, there is a possibility of negative inductor current, and this allows us to keep the switching frequency constant over load. The trade off is a higher conduction and switching losses in force PWM mode.
Let's dive a little deeper and extend this comparison to heavy load efficiency. But first, let's introduce a vital concept called dead-time. Dead-time is defined as the time period when both top side and low side switches are in the off state. This distinct period ensures a smooth transition into the on state.
Of perhaps greater importance, it eliminates the possibility of both switches getting caught in the on state simultaneously. This could cause a shoot through event where the input supply is shorted to ground. As the high side is turning on, we need to turn off the parasitic low side body diode by supplying a very small charge to extinguish the reverse recovery charge. Since this necessitates drawing a small current through the high side switch, it increases the losses in the topside switch.
We can mitigate this by adding a very small Schottky diode external to the part, and this gives us the best of both worlds. In the non-synchronous, we don't have to worry about this. However, the conduction losses by having the external diode far surpass the switching losses created by this parasitic body diode.
Finally, the low side FET in synchronous also lends the benefit of a much lower [INAUDIBLE], facilitating a smaller voltage drop when turned on. Compare this to the mandatory external diode in the non-synchronous, which has a larger forward voltage drop, and therefore even higher conduction losses.
Let's take a closer look at this example. Here we have the parasitic body diode. We know that it conducts during the dead-time. We know that it also has a reverse recovery charge which increases the switching loss. This creates increased ringing in the switch node.
To have the best of both worlds, all we do is add a very, very small Schottky diode that connects the switch node to ground. This bypasses this body diode during that time, and hence there is no reverse recovery charge to worry about. The current rating for the start can be a fraction of the power diode for a non-synchronous buck, because it only conducts during the dead-time.
This chart illustrates the efficiency improvement by adding a small Schottky diode. A configuration without the Schottky diode is shown in red, and with the Schottky added as shown in green. The improvement depends on load current and the switching loss from the recovery charge on the parasitic diode. As you can see, as the load current goes up, the amount of efficiency improved increases by lower losses.
This chart summarizes all of the solutions we discussed. Essentially, by using FPWM, we get fixed switching frequency. But the switching losses at heavy load are more, and the light load efficiency is worse. The synchronous architecture also brings much better dropout performance compared to the non-synchronous architecture. By adding the small Schottky , we not only reduce both the heavy load switching losses, but also get the benefit of the synchronous high light load efficiency.
Let's switch gears a little bit and talk about the thermal performance. Here we have three architectures. We have the non-synchronous, the synchronous, and a synchronous with a small Schottky added. As you can see in the non-synchronous buck, we have better thermal performance, because the heat is dissipated between two packages-- the IC and the diode.
Whereas in the synchronous, it is a lot harder to maintain this heat dissipation, because the diode, or the low side FET, is now integrated within the monolithic IC. By adding a small Schottky diode, the loss and heat is reduced, hence making the IC much cooler compared to a comparable sync without a Schottky.
If we do a quick nice comparison between the two architectures, we expect the synchronous architecture to vent out. This is because there is a smaller critical current part by integrating the low side switch within the IC. As you can see here, the switch ringing peak on the synchronous is much larger than we would expect.
This is because the parasitic body diode of the low side FET needs a small amount of current from the high side switch to turn it off. We can mitigate that by adding a small Schottky external to the synchronous solution. This gives us the benefit of a 50% reduction in the switch ringing noise compared to the non-synchronous.
If you look at the transient between the two architectures, we can see that the load pulse is shown here in magenta, and the V out transient performance is shown in yellow. As we can expect, during the load pulse, the V out drops, but it quickly recovers. And when the load disappears, the pulse overshoot dissipates quickly. This is true in the force PWM case because of the characteristic of negative inductor current. It can sync the current and discharge the output gaps quickly.
However, in the synchronous discontinuous mode method and in the non-synchronous mode, we don't have this benefit, because in the non-synchronous case the diode blocks the negative inductor current. And in DCM we switch off the low side FET to prevent inductor current from going negative. This is one inherent benefit of using force PWM over the standard DCM.
The controllability comparison between non-synchronous and synchronous is shown here. As you can see, we have only limited control since we only control one FET, which is the top side switch. Whereas in a synchronous architecture we control both, the low and the high side.
Which also means, in terms of current limit, we have three architectures that we could implement. We could use a peak current mode, a valley current mode, or an average current mode, and this depends solely on the controller. The non-synchronous is restricted to the peak current since only the top side switch is under control.
In terms of over voltage protection, we cannot actively pull down V out, because the diode blocks negative current through the inductor. Hence, we cannot discharge the output gaps. Whereas in a synchronous, depending on the controller, we can use force PWM mode to actively pull down V out during a transient situation. To summarize, there are more options in the synchronous architecture compared to the non-synchronous.
Finally, let's talk about current limit. As you can see here, we have the peak and the valley limit in full force controlling the current ripple across the inductor. Whereas in a non-synchronous architecture, we only have the peak current limit active. We have no way of controlling the valley limit, because the diode is external to the solution. When we have a slow slew rate, we get a very controlled ramp that's possible. Whereas in a non-synchronous, as you can see here, we depend on only the peak current limit to be able to let the controller decide the end of the switching cycle.
Let's summarize everything we've learned today. We know that the solution size for the non-synchronous is much larger, because it has an external diode. The synchronous integrates the low side switch within the package, making it much easier to use with an optimized pin out.
The light load efficiency might seem better for non-synchronous, but it's far more efficient to run a synchronous in DCM. The heavy load efficiency has more conduction losses in non-synchronous and less switching losses in non-synchronous. However, by adding a small Schottky diode, we get the best of both worlds and get the highest efficiency possible.
The lowest V out possible through dropout is limited by the forward voltage of the diode in non-synchronous. However, the low [INAUDIBLE] of the low side FET combined with a higher efficiency gives us a much better dropout profile in synchronous. In terms of thermal performance, having two packages makes the non-synchronous solution appear better at heat dissipation. However, adding a small Schottky diode reduces power loss to an extent larger than is achievable with non-synchronous.
The switch frequency is not an option in non-synchronous overload. However, with synchronous in FPWM, we can keep the switching frequency constant. In terms of noise, it might seem that the noise in a non-synchronous is lower. However, adding the small Schottky diode reduces noise considerably-- in fact, 50% more than a non-synchronous.
The unloading transient is much worse in a non-synchronous and in a DCM synchronous topology, because there is no way for the inductor to sync current from the output gaps. However, with force PWM mode, this is possible.
Finally, the controllability is far more easier because of the added flexibility of two FETs within the die, compared to just the top side FET in the non-synchronous solution. For more information, please visit simpleswitcher.com. Thank you for watching.

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Date:
September 17, 2015

Anston presents a thorough comparison of synchronous and non-synchronous converters, with the advantages and disadvantages of each. Differences in efficiency, EMI, thermals, and more, are discussed in this training.