The data acquisition board has 16 channels of simultaneous 24 bit delta-sigma analogue to digital converters. The maximum sample rate that can be streamed to the host is 216kSPS. The ADCs have built in lowpass filters which cutoff at half the samplerate, and an input range of +/-10V. The converter (PCM4204) is a delta-sigma device which provides high quantisation linearity.

The X3-SD has an onboard PLL which can be driven by an onboard reference oscillator or by an offboard reference clock. Alternately the user can supply an external clock. Triggering of the start of samples can be done by software or an external active high LVTTL signal.

The X3-SD also has 44 bits of user digital IO. This can be read or written to as a 32 bit register from the host, or if the user modifies the logic, can be used to interface to a variety of digital devices such as serial, parallel ports, I2C devices etc. The Spartan3 device supports LVTTL.

Data acquisition control, signal processing, buffering, and system interface functions are implemented in a Xilinx Spartan3 FPGA, 1M gate device. Two 512Kx32 memory devices are used for data buffering and FPGA computing memory. The data acquisition board has a single lane PCI Express interface to the host which can sustain 160MB/s to the host.

The X3-SD is supported by Malibu, a set of C++ libraries to use the board under Windows and Linux. This includes example programs to use the board to setup the logic, acquire samples and stream them to disk.

The logic can be fully customized using VHDL and MATLAB using the FrameWork Logic toolset. The MATLAB BSP supports real-time hardware-in-the-loop development using the graphical, block diagram Simulink environment with Xilinx System Generator.

The board comes complete with working logic (Framework Logic) and software drivers (Malibu). Please see the data flow diagram.

The simplied data flow from Adc(s) to host application works as follows. Samples from the Adc(s) are clocked into the FPGA. The samples are packed where necessary for efficient use of the RAM chips. The RAM is used as a virtual FIFO to decouple the continuous stream of the Adc(s) from the block transfer nature of PCIe. The user application sets the packetsize. When a whole packet of data is available in the RAM, the PCIe DMA controller does a bus master transfer to the host memory. At configuration time the device drivers reserve physical memory for this purpose. When the transfer is complete, the DMA controller sends an interrupt to Malibu which then copies the packet from the busmaster area to virtual memory and then fires an event in the User application with a reference to the data.