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Abstract:

In one embodiment, an external signal input circuit of a semiconductor
memory may include: an input block configured to receive a plurality of
external signals and to generate a plurality of internal signals; and a
control block configured to output one or more internal signals of the
plurality of internal signals that correspond to a rank configuration of
the semiconductor memory and to block output of one or more internal
signals of the plurality of internal signals that do not correspond to
the rank configuration.

Claims:

1. An external signal input circuit of a semiconductor memory,
comprising: an input block configured to receive a plurality of external
signals and to generate a plurality of internal signals; and a control
block configured to output one or more internal signals of the plurality
of internal signals that correspond to a rank configuration of the
semiconductor memory and to block output of one or more internal signals
of the plurality of internal signals that do not correspond to the rank
configuration.

2. The external signal input circuit according to claim 1, wherein the
control block comprises: a first control unit configured to receive a
first internal signal of the plurality of internal signals and to output
the first internal signal; and a second control unit configured to select
and output one of the first internal signal and a second internal signal
of the plurality of internal signals.

3. The external signal input circuit according to claim 2, wherein the
first internal signal is a signal corresponding to a single-rank
configuration and a multi-rank configuration.

4. The external signal input circuit according to claim 2, wherein the
second internal signal is a signal corresponding only to a multi-rank
configuration.

5. The external signal input circuit according to claim 2, wherein the
second control unit selects and outputs the first internal signal when
the semiconductor memory has a single-rank configuration, and wherein the
second control unit selects and outputs the second internal signal when
the semiconductor memory has a multi-rank configuration.

6. The external signal input circuit according to claim 5, wherein the
second control unit is configured to determine the rank configuration of
the semiconductor memory based on a rank signal.

7. An external signal input circuit of a semiconductor memory,
comprising: a first input unit configured to receive a first external
signal to generate a first internal signal; a second input unit
configured to receive a second external signal to generate a second
internal signal; a first control unit configured to receive the first
internal signal and output the first internal signal; and a second
control unit configured to block an output of the second internal signal
based on a rank configuration of the semiconductor memory.

8. The external signal input circuit according to claim 7, wherein the
first external signal and the second external signal are signals defining
the same type of command.

9. The external signal input circuit according to claim 7, wherein each
one of the first external signal and the second external signal comprises
a clock enable signal or an impedance adjustment signal.

10. The external signal input circuit according to claim 7, wherein the
second control unit selects and outputs the first internal signal when
the semiconductor memory has a single-rank configuration, and wherein the
second control unit selects and outputs the second internal signal when
the semiconductor memory has a multi-rank configuration.

11. The external signal input circuit according to claim 10, wherein the
second control unit is configured to determine the rank configuration of
the semiconductor memory based on a rank signal.

12. An external signal input circuit of a semiconductor memory,
comprising: a first input unit configured to output a first buffering
signal as a first internal signal, the first buffering signal being
generated by receiving a first external signal; and a second input unit
configured to select one of the first buffering signal and a second
buffering signal, generated by receiving a second external signal, based
on a rank configuration of the semiconductor memory and to output the
selected buffering signal as a second internal signal, wherein the second
input unit is configured to block an input of the second external signal
based on the rank configuration.

13. The external signal input circuit according to claim 12, wherein the
first input unit is configured to control a setup/hold time of the first
buffering signal by delaying the first buffering signal by a preset time.

14. The external signal input circuit according to claim 13, wherein the
second input unit is configured to control a setup/hold time of the
selected buffering signal by delaying the selected buffering signal by
the preset time.

15. The external signal input circuit according to claim 12, wherein the
first input unit comprises: a buffer configured to receive the first
external signal in response to an enable signal and to generate the first
buffering signal; and a setup/hold section configured to control a
setup/hold time of the first buffering signal.

16. The external signal input circuit according to claim 12, wherein the
second input unit comprises: a buffer configured to receive the second
external signal in response to a control signal and to generate the
second buffering signal; a control section configured to receive an
enable signal and to output the enable signal as the control signal based
on a rank signal; and a setup/hold section configured to select one of
the first buffering signal and the second buffering signal based on the
rank signal and to control a setup/hold time of the selected buffering
signal.

17. The external signal input circuit according to claim 16, wherein the
control section is configured to output the enable signal as the control
signal when the rank signal is a level signal defining multi-rank
configuration.

18. The external signal input circuit according to claim 16, wherein the
control section is configured to output a deactivation level of the
enable signal as the control signal when the rank signal is a level
signal defining single-rank configuration.

Description:

CROSS-REFERENCES TO RELATED APPLICATION

[0001] The present application claims priority under 35 U.S.C.
§119(a) to Korean Application No. 10-2010-0017744, filed on Feb. 26,
2010, in the Korean Intellectual Property Office, which is incorporated
herein by reference as if set forth in its entirety.

BACKGROUND

[0002] 1. Technical Field

[0003] The present invention relates to semiconductor memory, and more
particularly, to external signal input circuits in a semiconductor
memory.

[0004] 2. Related Art

[0005] A semiconductor memory may have a single-rank configuration or
multi-rank configuration.

[0006] The semiconductor memory may include an external signal input
circuit configured to receive external signals such as a clock enable
signal CKE and an impedance adjustment signal ODT.

[0008] FIG. 1B illustrates an external signal input circuit 20 of another
conventional semiconductor memory having a multi-rank configuration, such
as two or four ranks. The external signal input circuit 20 may include
four input units 21 through 24 configured to buffer first clock enable
signal CKE0, second clock enable signal CKE1, first impedance adjustment
signal ODT0, and second impedance adjustment signal ODT1, respectively,
to generate internal signals CKE--i and ODT--i.

[0009] Here, the first clock enable signal CKE0 and second clock enable
signal CKE1 may be combined to instruct a desired rank among the multi
ranks to activate the clock signal.

[0010] Furthermore, the first impedance adjustment signal ODT0 and second
impedance adjustment signal ODT1 may be combined to instruct a desired
rank among the multi ranks to perform impedance control.

[0011] In this case, the input units 11, 12, and 21 through 24 may be
configured in the same manner. Each one of the input units may control a
setup/hold time of a signal buffered by an internal buffer and may drive
and output the signal.

[0012] As described above, the external signal input circuits of the
conventional semiconductor memories are configured in different manners
based on the rank configurations thereof, that is, the single rank and
the multi ranks.

[0013] The external signal input circuit 10 for the single-rank
configuration may not be used in the multi-rank configuration, and the
external signal input circuit 20 for the multi-rank configuration may not
be used in the single-rank configuration.

SUMMARY

[0014] Disclosed embodiments provide external signal input circuits of
semiconductor memory that may be used in both a single-rank configuration
and a multi-rank configuration.

[0015] In one exemplary embodiment, an external signal input circuit of a
semiconductor memory is provided, including, for example: an input block
configured to receive a plurality of external signals and to generate a
plurality of internal signals; and a control block configured to output
one or more internal signals of the plurality of internal signals that
correspond to a rank configuration of the semiconductor memory and to
block output of one or more internal signals of the plurality of internal
signals that do not correspond to the rank configuration.

[0016] In another exemplary embodiment, an external signal input circuit
of a semiconductor memory is provided, including, for example: a first
input unit configured to receive a first external signal to generate a
first internal signal; a second input unit configured to receive a second
external signal to generate a second internal signal; a first control
unit configured to receive the first internal signal and output the first
internal signal; and a second control unit configured to block an output
of the second internal signal based on a rank configuration of the
semiconductor memory.

[0017] In another exemplary embodiment, an external signal input circuit
of a semiconductor memory is provided, including, for example: a first
input unit configured to output a first buffering signal as a first
internal signal, the first buffering signal being generated by receiving
a first external signal; and a second input unit configured to select one
of the first buffering signal and a second buffering signal, generated by
receiving a second external signal, based on a rank configuration of the
semiconductor memory and to output the selected buffering signal as a
second internal signal. The second input unit may be configured to block
an input of the second external signal based on the rank configuration.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Features, aspects, and embodiments are described in conjunction
with the attached drawings, in which:

[0019] FIG. 1A is a block diagram of one conventional external signal
input circuit of conventional a semiconductor memories;

[0021] FIG. 2 is a block diagram of an external signal input circuit of a
semiconductor memory according to one embodiment of the invention;

[0022] FIG. 3A is a circuit diagram of one exemplary embodiment of the
first control unit shown in FIG. 2;

[0023] FIG. 3B is a circuit diagram of one exemplary embodiment of the
second control unit shown in FIG. 2;

[0024] FIG. 4 is a block diagram of an external signal input circuit of a
semiconductor memory according to another embodiment of the invention;

[0025] FIG. 5 is a block diagram illustrating the internal configuration
of one exemplary embodiment of a first input unit shown in FIG. 4;

[0026] FIG. 6 is a circuit diagram of one exemplary embodiment of the
setup/hold section shown in FIG. 5;

[0027] FIG. 7 is a block diagram illustrating the internal configuration
of one exemplary embodiment of the second input unit shown in FIG. 4; and

[0028] FIG. 8 is a circuit diagram of one exemplary embodiment of the
setup/hold section shown in FIG. 7.

DETAILED DESCRIPTION

[0029] Reference will now be made in detail to the exemplary embodiments
consistent with the present disclosure, examples of which are illustrated
in the accompanying drawings. Whenever possible, same reference numerals
will be used throughout the drawings to refer to the same or like parts.

[0031] FIG. 2 is a block diagram of an external signal input circuit 100
of the semiconductor memory in accordance with one embodiment of the
present invention. The external signal input circuit 100 may include an
input block 110 and a control block 120. The input block 110 may be
configured to receive a plurality of external signals CKE0, CKE1, ODT0,
and ODT1 to generate a plurality of internal signals CKE0_CKE1--i,
ODT0--i, and ODT1--i.

[0032] The external signals CKE0 and ODT0 may be signals that are commonly
used in a single-rank configuration and a multi-rank configuration. The
external signals CKE1 and ODT1 may be external signals that may not be
used in the single-rank configuration, but may only be used in the
multi-rank configuration.

[0033] The input block 110 may include a first input unit 111, a second
input unit 112, a third input unit 113, and a fourth input unit 114.

[0034] The first input unit 111 may be configured to receive the external
signal CKE0 in response to activation of an enable signal EN and to
generate the internal signal CKE0--i. The second input unit 112 may
be configured to receive the external signal CKE1 in response to
activation of the enable signal EN and to generate the internal signal
CKE1--i.

[0035] The third input unit 113 may be configured to receive the external
signal ODT0 in response to activation of the enable signal EN and to
generate the internal signal ODT0--i.

[0036] The fourth input unit 114 may be configured to receive the external
signal ODT1 in response to activation of the enable signal EN and to
generate the internal signal ODT1--i.

[0037] The control block 120 may be configured to output internal signals
corresponding to the rank configuration of the semiconductor memory,
among the plurality of internal signals CKE0--i, CKE1--i,
ODT0--i, and ODT0--i, and to block the output of internal
signals that do not correspond to the rank configuration. That is, the
control block 120 may be configured to output the internal signals
CKE0--i to and ODT0--i and to block the output of the internal
signals CKE1--i and ODT1--i, when the semiconductor memory has
the single-rank configuration.

[0038] Furthermore, the control block 120 may be configured to output all
the internal signals CKE0--i, CKE1--i, ODT0--i, and
ODT1--i, when the semiconductor memory has the multi-rank
configuration.

[0039] The control block 120 may include first control block 121, second
control block 121, third control block 123, and fourth control block 124.

[0040] The first control unit 121 may be configured to receive the
internal signal CKE0--i and to output the internal signal
CKE0--i.

[0041] The second control unit 122 may be configured to block the output
of any one of the two internal signals CKE0--i and CKE1--i and
to select and output the other internal signal, according to a rank
signal RANK1.

[0042] The rank signal RANK1 may define the single-rank configuration and
the multi-rank configuration. For example, when the semiconductor memory
has the single-rank configuration, the rank signal RANK1 may be a
high-level signal. When the semiconductor memory has the multi-rank
configuration, the rank signal RANK1 may be a low-level signal.

[0043] The third control unit 123 may be configured to receive the
internal signal ODT0--i and output the internal signal ODT0--i.

[0044] The fourth control unit 124 may be configured to block the output
of any one of the two internal signals ODT0--i and ODT1--i and
select and output the other internal signal, according to the rank signal
RANK1.

[0045] FIG. 3A is a circuit diagram of one exemplary embodiment of the
first control unit 121 shown in FIG. 2. The first control unit 121 may
include a plurality of pass gates PG1 and PG2 and a plurality is of
inverters IV1 and IV2. Since a PMOS gate of the pass gate PG1 and an NMOS
gate and an input terminal of the pass gate PG2 may be grounded, the
first control unit 121 may receive the internal signal CKE0--i and
output the internal signal CKE0--i.

[0046] FIG. 3B is a circuit diagram of one exemplary embodiment of the
second control unit 122 shown in FIG. 2. The second control unit 122 may
include a plurality of pass gates PG11 and PG12 and a plurality of
inverters IV11 and IV12.

[0047] The rank signal RANK1 may be inputted to a PMOS gate of the pass
gate PG11, an inverted rank signal RANK1B may be inputted to an NMOS
gate, and the internal signal CKE1--i may be inputted to an input
terminal.

[0048] The inverted rank signal RANK1B may: be inputted to a PMOS gate of
the pass gate PG2, the rank signal RANK1 may be inputted to an NMOS gate,
and the internal signal CKE0--i may be inputted to an input
terminal.

[0049] When the rank signal RANK1 is a high-level signal defining the
single-rank configuration, the pass gate PG11 may be turned off and the
pass gate PG12 may be turned on. Therefore, the second control unit 122
may block the input of the internal signal CKE0--i and to output the
internal signal CKE0--i through the pass gate PG12 and the inverters
IV1 and IV2.

[0050] When the rank signal RANK1 is a low-level signal defining the
multi-rank configuration, the pass gate PG12 may be turned off, and the
pass gate PG11 may be turned on. Therefore, the second control unit 122
may block the input of the internal signal CKE0--i and may output
the internal signal CKE1--i through the pass gate PG11 and the
inverters IV1 and IV2.

[0051] The third control unit 123 may be configured in the same manner as
the first control unit 121, except for receiving the internal signal
ODT0_i.

[0052] The fourth control unit 124 may be configured in the same manner as
the second control unit 122, except for receiving the internal signals
ODT0--i and ODT1--i.

[0053] When the rank signal RANK1 is a high-level signal defining the
single-rank configuration, the fourth control unit 124 may block the
input of the internal signal ODT1--i and output the internal signal
ODT0--i.

[0054] When the rank signal RANK1 is a low-level signal defining the
multi-rank configuration, the fourth control unit 124 may block the input
of the internal signal ODT0--i and output the internal signal
ODT1--i.

[0055] As the first through fourth control units 121 through 124 may have
the same circuit configuration, internal signal processing times of the
first through fourth control units 121 through 124 may become
substantially the same.

[0056] In the above-described embodiment, when the semiconductor memory
has the single-rank configuration, the first control unit 121 may output
the internal signal CKE0--i, the second control unit 122 may output
the internal signal CKE0--i, the third control unit 123 may output
the internal signal ODT0--i, and the fourth control unit 124 may
output the internal signal ODT0--i.

[0057] When the output signal of the second control unit 122 is
deactivated in the single rank, for example, when the output signal is
fixed to a low level, it may affect the internal signal CKE0--i
outputted from the first control unit 121.

[0058] Therefore, the second control unit 122 may be configured to output
the same signal as that outputted from the first control unit 121. The
third and fourth control units 123 and 124 may be operated in the same
manner.

[0059] Meanwhile, when the semiconductor memory according to the
embodiment has the multi-rank configuration, the first control unit 121
may output the internal signal CKE0--i, the second control unit 122
may output the internal signal CKE1--i, the third control unit 123
may output the internal signal ODT0--i, and the fourth control unit
124 may output the internal signal ODT1--i.

[0060] FIG. 4 illustrates an external signal input circuit 200 of a
semiconductor memory according to another embodiment of the invention.
The external signal input circuit 200 may include first input unit 210,
second input unit 220, third input unit 230, and fourth input unit 240.

[0061] The first input unit 210 may be configured to receive an external
signal CKE0 and outputs an internal signal CKE0--i.

[0062] The second input unit 220 may be configured to receive an external
signal CKE1 and a buffering signal A in response to a rank signal RANK1.
The second input unit 220 may be further configured to output an internal
signal CKE0--i or CKE1--i.

[0063] The third input unit 230 may be configured to receive an external
signal ODT0 and output an internal signal ODT0--i.

[0064] The fourth input unit 240 may be configured to receive an external
signal ODT1 and a buffering signal E in response to the rank signal
RANK1. The second input unit 240 may be further configured to output an
internal signal ODT0--i or ODT1--i.

[0065] In this case, the third input unit 230 may be configured in the
same manner as the first input unit 210, except for receiving the
external signal ODT0. Furthermore, the fourth input unit 240 may be
configured in the same manner as the second input unit 220, except for
receiving the external signal ODT1 and the buffering signal E.

[0066] FIG. 5 illustrates the internal configuration of one exemplary
embodiment of the first input unit 210 shown in FIG. 4. The first input
unit 210 may include a buffer 211, a setup/hold section 212, and a driver
213.

[0067] The buffer 211 may be configured to receive the external signal
CKE0 in response to activation of an enable signal EN and to generate the
buffering signal A.

[0068] The setup/hold section 212 may be configured to generate an output
signal B by controlling a setup/hold time of the buffering signal A.

[0069] The driver 213 may be configured to drive the output signal B of
the setup/hold section 212 to output the internal signal CKE0--i.

[0070] FIG. 6 is a circuit diagram of one exemplary embodiment of the
setup/hold section 212 shown in FIG. 5. The setup/hold section 212 may
include a plurality of inverters IV11, IV12, IV13, IV14, and IV15.

[0071] The setup/hold section 212 may generate the output signal B by
delaying the buffering signal A by a time determined by the plurality of
inverters IV11 through IV15.

[0072] FIG. 7 illustrates the internal configuration of one exemplary
embodiment of the second input unit 220 shown in FIG. 4. The second input
unit 220 may include a buffer 221, a setup/hold section 222, and a
control section 224.

[0073] When the rank signal RANK1 is a low-level signal defining the
multi-rank configuration, the control section 224 may output the enable
signal EN as a control signal EN_SET. On the other hand, when the rank
signal RANK1 is a high-level signal defining the single-rank
configuration, the control section 224 may output a deactivation level of
the enable signal EN, that is, a ground level as a control signal EN_SEL.

[0074] The control section 224 may be configured in the same manner as the
second control section unit of FIG. 3B. However, unlike in FIG. 3B, the
control section 224 may receive the enable signal EN instead of the
internal signal CKE1--i and may be connected to a ground terminal
VSS instead of the internal signal CKE0--i.

[0075] The buffer 221 may be configured to receive the external signal
CKE1 in response to the control signal EN_SEL and may is generate a
buffering signal C.

[0076] The setup/hold section 222 may be configured to select one of the
buffering signals A and C based on the rank signal RANK1 and to output an
output signal D by controlling a setup/hold time of the selected signal.

[0077] The driver 223 may be configured to drive the output signal D of
the setup/hold section 222 to output the internal signal CKE0--i or
CKE1--i.

[0078] FIG. 8 is a circuit diagram of one exemplary embodiment of the
setup/hold section 222 shown in FIG. 7. The setup/hold section 222 may
include a plurality of NAND gates ND21, ND22, and ND23 and a plurality of
inverters IV21, IV22, and IV23.

[0079] When the rank signal RANK1 is a high-level signal defining the
single-rank configuration, the setup/hold section 222 may control the
setup/hold time of the output signal D by passing the buffering signal A
through the plurality of NAND gates ND21 through ND23 and the plurality
of inverters IV21 through IV23.

[0080] When the rank signal RANK1 is a low-level signal defining the
multi-rank configuration, the setup/hold section 222 may control the
setup/hold time of the output signal D by passing the buffering signal C
through the plurality of NAND gates ND21 through ND23 and the plurality
of inverters IV21 through IV23.

[0081] The setup/hold section 222 of FIG. 8 is designed, in the example,
in such a manner that the number of logic elements through which the
buffering signal A or C passes corresponds to five (the NAND gates ND21
or ND22 and ND23 and the inverters IV21 through IV23).

[0082] Furthermore, the setup/hold section 212 of FIG. 6 is designed, in
the example, in such a manner that the number of logic elements through
which the buffering signal A passes corresponds to five (the inverters
IV11 through IV15).

[0083] Therefore, the setup/hold time of the output signal D in the
setup/hold section 222 of FIG. 8 may be set to be substantially the same
as the setup/hold time of the output signal B in the setup/hold section
212 of FIG. 6.

[0084] When a skew exists between the output signals of the buffers 211
and 221, the setup/hold times of the setup/hold sections 212 and 222 of
the first through fourth input units 210 through 240, may be controlled
to reduce the skew between the output signals of the buffers 211 and 221.
That is, the circuit design may be performed in different manners by
adjusting the numbers of inverters or the size of the inverters in the
setup/hold sections 212 and 222. Then, it may be possible to reduce the
skew between the output signals of the buffers 211 and 221.

[0085] When the semiconductor memory according to this embodiment has the
single-rank configuration, the first input unit 210 may output the
internal signal CKE0--i, the second input unit 220 may output the
internal signal CKE0--i, the third input unit 230 may output the
internal signal ODT0--i, and the fourth input unit 240 may outputs
the internal signal ODT0--i.

[0086] The second input unit 220 may be configured to output the same
signal as that outputted by the first input unit 210 and the fourth input
unit 240 may be configured to output the same signal as that outputted by
the third input unit 230, in order to minimize the effect between the
internal signals.

[0087] When the semiconductor memory has the multi-rank configuration, the
first input unit 210 may output the internal signal CKE0--i, the
second input unit 220 may output the internal signal CKE1--i, the
third input unit 230 may output the internal signal ODT0--i, and the
fourth input unit 240 may output the internal signal ODT1--i.

[0088] According to embodiments of the invention, the external signal
input circuit of the semiconductor memory may be used regardless of a
rank configuration. Therefore, separate circuit design is not required,
and the external signal input may be easily applied to products.

[0089] While certain embodiments have been described above with reference
to illustrative examples for particular applications, it will be
understood to those skilled in the art that the embodiments described are
by way of example only. Those skilled in the art with access to the
teachings provided in this disclosure will recognize additional
modifications, applications, and/or embodiments and additional fields in
which the present disclosure would be of significant utility.
Accordingly, the external signal input circuit of the semiconductor
memory described herein should not be limited based on the described
embodiments. Rather, the external signal input circuit of the
semiconductor memory described herein should only be limited in light of
the claims that follow when taken in conjunction with the above
description and accompanying drawings.