This paper proposes a new ASIC design flow using latch retiming and random clock-gating to cope with power analysis side-channel attacks. We cast the side-channel attack problem as a combination of retiming and clock-gating problems and solve the problems using only existing EDA tool chains. In particular, we achieve light weight time-shifting obfuscation… (More)

—Coarse-grained reconfigurable arrays (CGRAs) are a promising class of architectures conjugating flexibility and efficiency. Devising effective methodologies to map applications onto CGRAs is a challenging task, due to their parallel execution paradigm and constrained hardware resources. In order to handle complex applications, it is important to devise… (More)

An esthesioneuroblastoma in a 16-year-old male was studied ultrastructurally and immunohistochemically, using antiserum against tyrosine hydroxylase (TH), a rate-limiting enzyme in the catecholamine-synthesizing pathway. Tumor cells were fairly uniform in appearance, showing scanty eosinophilic cytoplasm and round to oval hyperchromatic nuclei, and were… (More)