Leakage current leads 90-nm rogues' gallery

SAN MATEO, Calif.  As leakage current shoulders its way to center stage in chip designers' gallery of horrors, leading-edge design teams are rapidly developing ad hoc techniques to minimize its impact. And while the EDA industry is characteristically lagging the leading-edge need, at least one vendor is moving aggressively to catch up, formulating both a tool and a methodology for reducing a specific source of leakage current.

Yet the problem shows every sign of becoming the No. 1 issue with large designs at 90 nanometers and with nearly all designs at 65 nm and beyond.

In context, leakage current is just one component in the overall power management nightmare for sub-100 nm processes. Up to this pointin 130-nm designs, for instancemost of the attention has been focused on dynamic power, or the energy dissipated by charging and discharging the capacitances in the signal paths.

But at 90 nm and below, lower threshold voltages, thinner oxides and shorter effective channel lengths have made
the transistor more like a sieve than like a switch: Many current paths continue to conduct, even when the device is turned solidly off.

Of at least eight identified sources of leakage current in a low-threshold MOSFET, two are attracting the most attention: subthreshold leakage between the source and drain (a result of the inability to close the channel completely) and tunneling leakage from the gate, through the dielectric to the channel (a fact of life in quantum mechanics).

Process and device designers are attacking both problems. Subthreshold leakage can be reduced by lengthening the channel, by biasing a well under the channel or by fabricating multiple-gate devices. Gate leakage can be reduced by switching to thicker, high-k dielectric materials and perhaps by using novel gate materials, in bids to reduce the tunneling current.

But engineers aren't holding their breath for a process-oriented solution. "We watch the process ideas, but we have to maintain a healthy dose of skepticism," said Bob Landers, silicon architect at Texas Instruments Inc.'s ASIC group.

Masaaki Yamada, manager of design methodology at Toshiba's ASIC group, added that while process-based techniques for reducing gate leakage look possible, it might fall to designers and their EDA partners to reduce the effects of subthreshold leakage.

The focus on subthreshold leakage current is indeed fueling some brainstorming in the design and tool development communities. The few design teams working at 90 nm have already had to face the problem and have put together a variety of approaches. Meanwhile, at least one tool vendor, Sequence Design Inc. (Santa Clara, Calif.), is developing a module on its existing tool platform to help physical designers cope with leakage current.

Many of the approaches rest on a process innovation that is already present in announced 90-nm processes: offering a choice of transistors with different threshold voltages. Designers may use low-threshold-voltagethat is, leakybut fast-switching transistors in the critical signal paths but opt for higher-threshold transistors in noncritical paths.

"The process we use today is pretty much spit and baling wire," admitted Scott Becker, chief technology officer at Artisan Components (Sunnyvale, Calif.). "You design your circuit using low-threshold transistors. Then you do a static timing analysis and build up a table of timing slacks. After you have that, you start at the nets that have the most positive slack and replace the leaky transistors with slower, high-threshold transistors.

"After you've gone as far as you think you can with that process, you do the timing analysis again, and either continue or back off. You keep iterating until you have closure on both timing and power."

The approach reduces overall leakage current by simply reducing the number of nets in which subthreshold current is an issue. But it requires a cell library with both high- and low-leakage cells, and it is at best a script-driven, iterative process. Designers suggest that it might be appropriate for such a cell-selection process to migrate into the synthesis tools, but synthesis vendors are tight-lipped about any work going on in that area.

A complementary approach is being used by some advanced design teams, according to TI's Landers. That is to identify periods in which a group of circuits is inactive, and then either reduce or turn off the power to the cells. This is a conceptually simple operation, but in practice it turns out to be remarkably complex.

In the first place, it requires identifying a group of cells and the period during which they will be quiescent. That requires at least a clear understanding of the dynamic behavior of the circuit-well beyond the statistical view taken by most power analysis tools-and may even require participation by the application code and the operating system.

"You have to watch the duty cycle carefully," observed Clive Bittlestone, ASIC technologist at TI. "There is an energy cost to turning the power on and off, as well as system implications to having a group of cells inactive. You have to make sure that you are actually saving energy overall when you turn off the power."

Actually switching the power requires inserting a high-current, low-on-resistance transistor between the supply or ground rail and the supply or ground contacts of a group of cells. To put the cells to sleep, you simply open the switch, eliminating all the current in the cells, including the leakage current. But of course there are complexities.

One is what to do about the inputs and outputs while the block is quiescent. The obvious answer is to surround the block with latches to hold the inputs low and maintain some defined output state. But depending on the design, that may add considerably to real estate andironi-
callypower.

Another key issue is the transition periodswhat exactly happens as the power drops or rises. "It's very important to avoid contention or latchup issues," Bittlestone said. "And you often find that during the transition there are leakage paths that you hadn't anticipated." To address that problem, the TI engineers said, the company has developed quite a large collection of special register and latch flip-flop cells designed specifically for blocks in which power will be switched.