Motorola Electronics Technical Questions

Posted on :11-03-2016

Q1. Using 2:1 Mux make a transparent latch (D flipflop).

Q2. What is the output of the following circuit?

Q3. Draw the state transition diagram for sequence detector for the sequence 011. If the first bit detected is zero then SCRH should be asserted when the second bit is 1 the SCRH should remain asserted when the third bit is 1 the FOUND should be asserted and the SCRH should be deserted. No bits should be left.

Q4. Describe the driving inverter? Which inverter is weak and which has more strength? Why?

Q5.

a. For each gate the delay time is 0.5 ns when will the glitch occur? Draw the glitch waveform.

b. How the circuit should be modified to avoid glitch?

Q6. ts=0.5 and Th=0.7 (for the setup time required and hold time required)

buffer has the delay of 1nsec.

What is the setup time? _________ns

What is the hold time? ___________ns

Q7. Draw the output waveform for the following circuit Vtp= Vtn=1V

Q8. Determine the output waveform, input is

Q9.

a. What is the output waveform for the above circuit?

b. What will happen when the AND gate is replaced by OR gate?

Q10. Using 2:1 Mux and one inverter make XOR gate.

Q11. Design a circuit such that f (clk_out) = 2 f (CLK_in) that is frequency doubling circuit is needed.

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