Breaking the 3Gb/s barrier

You've seen it happening for sometime now, design engineers are replacing shared parallel buses for a variety of products including servers, entertainment products and telecom systems with high-speed point-to-point serial buses. However, it's a double-edged sword reducing traces but causes challenges for enabling reliable signal transmission. Ansoft's Larry Williams offers his thoughts on resolving this dilemma.

Engineers designing servers, storage devices, multimedia PCs, entertainment systems, and telecom systems have driven an industry trend to replace legacy shared parallel buses with high-speed point-to-point serial buses. Standard interfaces like XAUI, XFI, Serial ATA, PCI Express, HDMI, and FB-DIMM have emerged to provide greater throughput using serial signaling rates of 3 to 10 Gb/s. While this trend has greatly reduced the number of traces and connections within the system, it has created new challenges for board designers when considering implementation with multiple connectors, transmission lines, and vias. Reliable signal transmission across a host board or between daughter cards on a backplane at GHz speeds compels adoption of new strategies and tools.

Components should be modeled using full-wave S-parameters
SPICE simulation has been the most popular approach for transient simulation of high-speed interconnects. Lumped equivalent circuits for interconnect elements derived by static field simulations, measurements, or analytical means have been cascaded in SPICE to simulate overall channel response. SPICE simulation has the added benefit of allowing engineers to include nonlinear transistor-level circuits for drivers and receivers providing a more accurate representation of interconnect performance.

Traditional SPICE simulation with lumped equivalent circuits and simplified transmission line models is accurate up to about 3 Gb/s. Beyond 3 Gb/s, S-parameters provide the best representation of the distributed nature of very high-speed interconnects. Electromagnetic field simulation using 3D full-wave techniques provides GHz-accurate S-parameter and full-wave Spice™ models for complex trace routing, vias and transitions, connectors, and IC packages.

Simulator must provide reliability and capacity for multi-gigabit channel modeling
Attempts to extend existing methods by including S-parameters in traditional SPICE simulations are plagued by non-physical behavior such as non-causality and non-passivity. Compounding the problem is that high-speed channels rarely occur in isolation. Multiple channel paths combining transistor-level models of transceivers, pre-emphasis circuits, and equalizers with extracted parasitics create challenging simulation netlists. It is common for transceiver circuits to contain over 10,000 elements. Combining S-parameters, transmission line models, and tens of thousands of circuit elements requires new circuit simulation technology. What is needed for simulation beyond 3 Gb/s are full-wave field solvers providing accurate S-parameters and transmission line modeling, integrated with a circuit simulator that provides the reliability and capacity required for modern serial channel analysis.

GHz designs must include frequency and time domain simulations to predict system performance correctly
High-performance electronic designs often include operating specifications for power integrity in the frequency domain and for signal integrity in the time domain. Common time domain metrics like eye-diagrams, jitter, TDR measurements, and SSN and frequency domain metrics like resonances, phase noise margins, power plane impedance, and insertion losses appear within the same spec sheet. New algorithms in circuit simulation are being adopted that can reliably perform transient and swept frequency simulations using S-parameters.

Higher serial speeds and smaller PCBs have greater power integrity requirements
High package pin count and GHz-speed data rates translate into extremely fast I/O switching and high transient power sinking. Simultaneously, the average PCB size is decreasing, power density is increasing, and power delivery requirements are tightening. Full-wave electromagnetic field simulation should be applied to precisely analyze power nets and planes using layout geometry. Engineers need tools that can model entire PCBs and package structures to eliminate high-frequency coupling between traces and power/ground planes prior to manufacturing.

Design of high-speed serial transmission on PCBs is a new challenge for board design engineers. By adoption of new strategies and tools those engineers can explore high-density designs and accurately predict system performance.

Author info
Larry Williams is the Director of Business Development for Ansoft and you can contact him via email at: williams@ansoft.com