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Optimization and Reliability for FinFET designs at #55DAC

TSMC is the leading foundry worldwide and they make a big splash each year at the DAC exhibit and conference, so I stopped by their theatre area during the presentation from IP vendor Moortec to see what's new this year. Stephen Crosher was the presenter from Moortec and we had exchanged emails before, so this was the first time that we had a chance to meet in person.

Designing an SoC for use in a system is a complex task these days, and even premier design companies like Apple have reported performance issues with their newest MacBook Pro laptops because as they were warming up under high loading the fans came on to cool the system off and then the CPU frequency was throttled to lower the temperature, but it was throttling back too much and actually performing slower than the previous CPU generation used. Fortunately for Apple they will issue a software fix to correct the clock throttling issue. Modern day SoC projects require that the design team have a plan for an optimized system that is also reliable.

MacBook Pro overheats, throttles frequency too much. Source: Apple

Some of the challenges in FinFET design are well known:

Higher thermal density

IR drop and PDN (Power Delivery Network) issues

Noise between coupled signals and injected into the substrate

Reaching timing closure

With each successively smaller process node we enjoy the benefits of increased gate densities, but at the expense of also increased power densities that can cause reliability issues. Narrower and higher-resistance interconnect layers impact timing to a greater degree and increase the variation effects. Add up all of these issues and it makes reaching timing closure even more difficult.

The Moortec approach to these challenges is to provide monitoring IP placed strategically within certain regions of an SoC, where the PVT sensors communicate to a controller that can then perform actions like scale the voltage, or throttle clock frequencies in order to have a reliable chip. Experts at Moortec have engineered this IP across multiple process nodes:

40nm

28nm

16nm

12nm

7nm

Some of the benefits of using this pre-built monitoring IP in your next chip include a reduced risk of failing to meet specs, an improved yield at the foundry, better reliability and chip lifespan, and no up-front development costs to design and qualify your own IP. With the Moortec IP embedded you can better implement dynamic or adaptive schemes like DVFS (Dynamic Voltage Frequency Scaling) or AVS (Adaptive Voltage Scaling).

Moortec has been an IP Alliance Member with TSMC since 2010, starting at the 40nm process node, and in 2016 they received a partner of the year award from TSMC. At DAC there was news from Moortec about supporting the 40nm ULP CMOS technology, useful for the IoT marketplace. It was fun to meet the Moortec team in SFO and see their customer list continue to grow with tier one clients in diverse industries.