Aldec, Inc. has expanded the rule-checking capabilities of its ALINT-PRO tool in response to growing complexity of large-scale modern FPGA and ASIC designs. Rules new to the 2017.12 release of ALINT-PRO assure the integrity of a design’s finite state machines (FSMs) and help identify possible reset domain crossing (RDC) issues.

Verification of RDCs, also new to the 2017.12 release of ALINT-PRO, targets issues with complex SoC reset strategies and circuits with dynamically switchable regions. For instance, a harmless looking data transfer between registers with unrelated asynchronous reset controls may end with unrecoverable metastability, unless properly addressed at the RTL design phase.

Full coverage of block-level constraints for Lattice FPGA libraries for advanced CDC analysis

ALINT-PRO is a design verification solution for RTL code written in VHDL, Verilog, and SystemVerilog, which is focused on verifying coding style and naming conventions, RTL and post-synthesis simulation mismatches, smooth and optimal synthesis, reliable and portable FSM descriptions, avoiding problems on further design stages, clocks and reset tree issues, CDC/RDC, DFT, and coding for portability and reuse. The solution performs static analysis based on RTL and SDC source files uncovering critical design issues early in the design cycle.