First Look at the PIC16F188xx family

Back in August a press release announced the imminent launch of the new PIC16F188xx family [link]. This was bundled with another similar launch for the PIC16F157x family that I have reviewed with a tiny bit more detail in this previous post [link].

Today, I received the first copy of the full (while still preliminary) data sheet of the first two members of the family: the PIC16F18855 – 28 pin model, and PIC16F18875 – 40 pin model, both with 8k words, 16k bytes of Flash memory. (The family will eventually include models up to 32k words or 64k bytes Flash memory size!)

As was the case for the previous family launch, I feel the press release has not been doing justice to these parts, too little detail, too generic a message, invariably designed to impress investors rather than designers…

Here some more juicy details distilled from a first pass through the data (sheet):

The part number choice (188) for this family is one of those rare ones where there seems to be a logic (at least to me), and if you follow me through the next few lines, you will hopefully agree with me too: these parts are at the same time an extension of the (very) successful PIC16F182x family (small pin count + communication) and a remake of the gloriousPIC16F88x family (28/40 pin featured in countless articles/books/courses) with which they remain pin to pin and feature by feature compatible. Merge the two prefixes and voila’…

Being part of the PIC16F1 generation means primarily that they feature the very latest evolution of the PIC16 core (Enhanced Mid Range is the official name) which offers a linear addressing mode for RAM access and improves considerably the performance of C compilers.

As all recent additions to the PIC16F1 family they also get a load of Core Independent Peripherals (CIPs), among which: CLC, NCO, CRC/SCAN, DSM, PPS, CWG. (see the Rocket Science book for more on these)

They also introduce three innovations of their own:

A new 10-bit Analog to Digital Converter with Computation (named ADC2, read ‘ADC-squared’).

Two new low power modes, IDLE and DOZE, borrowed from the PIC18 and larger (PIC24/PIC32) families, but never before seen on a PIC16 class device. These expand the granularity of the low power modes possible and adds interesting new tools for the extreme low power designers.

A Peripheral Module Disable (PMD) unit that allows to disconnect completely any unused peripheral from the clock tree of the device, with a measurable additional power saving for XLP applications. This was also adopted before on PIC18 device, but never seen on PIC16 families.

So B) and C) are not really new-new, it is more a matter of showing how the PIC16 and PIC18 families are converging and borrowing from each other the best features introduced in the last few years (CIPs, XLP).

ADC-squared

The ADC2 deserves some more careful analysis as it promises to be another breakthrough advancement of the Core Independent Philosophy.

The intuition that all peripherals should be connectable directly and capable of performing their functions as independently from the core as possible.

Core Independent Peripheral can be configured and assembled to form complete functions that reduce the core workload, reduce the required clock speed, and eventually reduce code complexity and/or power consumption.

To this end the Computation part (the second C) in the new module, is where things get really interesting.

The idea behind the ADC2 peripheral seems to come from the observation that most applications require some kind of post processing for the data coming from the A/D converter, where some common trends can be identified:

Filtering can be required to clean up a sensor reading

Oversampling can be applied to increase the resolution of the conversion at the expense of time

Thresholds can be applied to detect fault/alert conditions specific to the application

All of the above cases would require the core to respond to an interrupt (or worse to sit on a blocking loop waiting for the conversion result) only to cycle through a step of a state machine of sorts that processes the data received, buffers it and compares it to thresholds. This could be repeated for tens of thousands of times per second, with a work load that can amount to a large percentage of the entire application.

The ADC2, steps in exactly to cover these needs. It adds two post-processing stages to a very traditional 10-bit (and in future versions 12-bit) ADC module that will be otherwise very familiar to all PIC16 and PIC18 users. The first stage is capable of performing a simple accumulation (16-bit signed), optionally followed by a division (shift) to obtain an averaged value. The second stage can continuously or periodically perform a (pair of ) thresholdcomparisons.

Note that the sequence used to obtain each sample includes automatically: a periodic (re)trigger, a timed sampling period but can also include the setting of guard pins and a differential measurement as required for advanced (capacitive) touch sensing operations (HCVD).

The core is interrupted, awakened or simply an event is generated internally only when both stages have completed (on the assigned number of samples/period) and only if/when a particular condition (logic expression combining the two thresholds) is verified.

The result of so much automation can significantly change the performance and power profile of an application. I will need to put my hands on samples of these devices to test it out, but I have a feeling that these features can simplify considerably any touch sensing application, and more in general eliminate so much of the workload from many other sensor applications (wearable/battery powered sensors) where the power consumption was a severe limiting factor before and tending to the ADC was the main/sole occupation of the CPU…