We need to drive a motor with around 40 Amps. The mosfet has an Rdson of about 7 mohms at 90 degrees Celsius. That is a whopping 11.2Watts of heat generated on the poor mosfet.

We are very space constrained so initially we thought we'd use a surface mount mosfet, such as D2PAK. Is it at all possible a surface mount mosfet to handle so much heat? We thought of mounting the mosfet on a large copper pad (that sort of diminishes why we chose the D2PAK in the first place though, since we can't use that board space anymore), and placing many thermal vias on that copper pad all the way to the backside of the board, and on the back, again on a large copper plane, mount an heatsink. Can we dissipate the heat in this fashion? Would the vias on the board be an effective thermal path?

Another option is to use TO220. But we can't figure out a good way to cool TO220's in our restricted space. There are individual heatsinks for TO220s on the market, but without forced airflow, most of them are capable of cooling the device down to about 80 degrees above ambient at 11.2W. That is a bit too much.

I would like to hear your experiences in cooling mosfet packages, any ideas would be appreciated.

\$\begingroup\$Why do you think it's feasible to cool a D2PAK device, but not feasible to cool a TO-220 device in the same volume? It's still the same amount of energy, in the same volume, the constraints are largely the same. Random other remarks: 80°C isn't necessarily a problem for your parts (although I agree it's a bit high for comfort). Also, there are mosfets available with a lower Rdson, consider those. Lowering Rdson is a very effective way of cutting power dissipation (and increasing efficiency).\$\endgroup\$
– marcelmAug 14 '16 at 22:02

4 Answers
4

To directly answer your first question: No, not even close. A little more copper around a surface mount part isn't going to get rid of 11W of heat. No way.

One answer may be to parallel multiple FETs. Not only does that cut the total dissipation by the number of parts, but the dissipation on each FET is reduced by the square of the number of parts. So if one FET dissipates 10W, then two parallel FETs would dissipate 5W total, and each FET would dissipate only 2.5W.

That's in theory. In practise they won't share the load exactly equally, so you have to design for a bit worse than that per FET. The good thing about paralleling FETs is that they have a positive temperature coefficient. The Rdson goes up with temperature. This helps them ballance somewhat and prevents runaway of a single part, like could be the case with bipolar transistors.

Ultimately you have to decide what you really want. Switching 40A is going to make some heat. One way or the other you're going to have to deal with that. You can tell us you're space contrained all you want, but ultimately the physics will dictate a certain amount of space, surface area, forced cooling, or whatever. It may not be possible to meet all the constraints. Not all combinations of small size, high current, and low cost are possible.

\$\begingroup\$Thanks. Running the thermal equations, it looks like we are going to be using dual TO220s with heatsinks. That appears to be a safe solution. At 7 mohms, that is 2.8W per device, and with a proper heatsink, we can get down the surface temp to 30 Celsius above ambient. And the junction would be about 4 Celsius above that.\$\endgroup\$
– SomethingBetterJun 23 '11 at 6:13

Using vias to improve thermal impedance is a valid approach for PCB-mounted MOSFETs and multi-layer PCBs. Without sophisticated modelling tools like Flotherm, however, it's difficult to predict what temperature you'll achieve without actually building and testing the circuit.

11W on the device sounds high, but then again, if you're not exceeding the volts and amps, and can keep the junction temperature within the limits, you're fine.

You may want to consider MOSFETs in parallel to share the load. The \$R_{DS(on)} \$ has a positive temperature coefficient, so the load will balance between them.

Just to give you an idea: The green board in the middle of the first picture is a BLDC driver I made about 2 years ago. The D2PAK FETs are PSMN4R3-30BL, while driving a dummy load at about 50A p-p per winding (second pic) they aren't getting very hot, 45-50C maybe. The But this is 6 FETs, not one, and the Rdson is lower, plus I use wires as heatsinks - see if you can use chassis or motor itself if it's not getting very warm while running.

International Rectifier produces a range of DirectFETs (PDF link), power MOSFETs with packages only slightly larger than the silicon die:

The package allows SMT integration like DxPAKs, but also thermal path separation like TO-220s, at minimum size. RDS(on) performance is maximized by eliminating lead resistance, so given the same silicon, there will be less heat generated in the first place that you need to reject.

There are a couple options for cooling, depending on how tight your integration is. Some of the trade-offs would be between extra mechanical design work, assembly steps, part count & cost, device size, and thermal performance.