If we take TSC-deadline mode timer out of the picture, the Intel SDMdoes not say that the timer is disable when the timer mode is change,either from one-shot to periodic or vice versa.

After this patch, the timer is no longer disarmed on change of mode, sothe counter (TMCCT) keeps counting down.

So what does a write to LVTT changes ? On baremetal, the change of modeis probably taken into account only when the counter reach 0. When thishappen, LVTT is use to figure out if the counter should restard countingdown from TMICT (so periodic mode) or stop counting (if one-shot mode).

This patch is based on observation of the behavior of the APIC timer onbaremetal as well as check that they does not go against the descriptionwritten in the Intel SDM.