topic Re: Alignment of edge with two clock sources in Other FPGA Architecturehttps://forums.xilinx.com/t5/Other-FPGA-Architecture/Finding-the-aligned-edge-of-two-clock/m-p/1074475#M38067
By editing your original post, you have nullified all the following answers !!!!<BR />Wed, 12 Feb 2020 22:07:10 GMTdrjohnsmith2020-02-12T22:07:10ZFinding the aligned edge of two clockhttps://forums.xilinx.com/t5/Other-FPGA-Architecture/Finding-the-aligned-edge-of-two-clock/m-p/1074056#M38057
<P>Hi all,</P><P>&nbsp;</P><P>I am trying to use two different clocks on kintex-7 FPGA KC705 board. 200Mhz (system clock) and 199.9Mhz (sma external clock).&nbsp;</P><P>With two clock domains like this, how do I detect the aligned edge of these two clocks?</P><P>&nbsp;</P><P>Thanks,</P>Wed, 12 Feb 2020 21:59:19 GMThttps://forums.xilinx.com/t5/Other-FPGA-Architecture/Finding-the-aligned-edge-of-two-clock/m-p/1074056#M38057changyuguo2020-02-12T21:59:19ZRe: Alignment of edge with two clock sourceshttps://forums.xilinx.com/t5/Other-FPGA-Architecture/Finding-the-aligned-edge-of-two-clock/m-p/1074432#M38059
<P>Short Answer = Not easily</P>
<P>199.9Mhz period differs from 200mhz clock period be something like 2.5ps, so you will struggle to get this to work in an fpga. Even if you used the mmcm and phase shift one versus the other the best you can do with the mmcm fine phase shift is 1/56 of the VCO period, even with the highest supported VCO frequency this would still only equate to ~11ps</P>
<P>Another thing is what are you planning to do here? Let's say you could align them the edges would only line up very infrequently only once every couple of thousand clocks</P>Wed, 12 Feb 2020 20:03:20 GMThttps://forums.xilinx.com/t5/Other-FPGA-Architecture/Finding-the-aligned-edge-of-two-clock/m-p/1074432#M38059klumsde2020-02-12T20:03:20ZRe: Alignment of edge with two clock sourceshttps://forums.xilinx.com/t5/Other-FPGA-Architecture/Finding-the-aligned-edge-of-two-clock/m-p/1074434#M38060
<P>If the frequencies are different, the edges will align sometime periodically... a stopped watch tells the right time twice a day</P><P>Even if you were able to delay one clock respect to the other, it's going to be for a single period then gone, so why?</P><P>&nbsp;</P>Wed, 12 Feb 2020 20:07:43 GMThttps://forums.xilinx.com/t5/Other-FPGA-Architecture/Finding-the-aligned-edge-of-two-clock/m-p/1074434#M38060satguy2020-02-12T20:07:43ZRe: Alignment of edge with two clock sourceshttps://forums.xilinx.com/t5/Other-FPGA-Architecture/Finding-the-aligned-edge-of-two-clock/m-p/1074436#M38061
<P>Unless someone proves me wrong, with time I'm more and more convinced there are lots of people thinking FPGAs, just because they are big and expensive, can do whatever one can ask. I'll try tomorrow asking a Virtex-7 to fill a glass with water.</P>Wed, 12 Feb 2020 20:10:53 GMThttps://forums.xilinx.com/t5/Other-FPGA-Architecture/Finding-the-aligned-edge-of-two-clock/m-p/1074436#M38061satguy2020-02-12T20:10:53ZRe: Alignment of edge with two clock sourceshttps://forums.xilinx.com/t5/Other-FPGA-Architecture/Finding-the-aligned-edge-of-two-clock/m-p/1074446#M38062
<P>The reason for having two clocks close to each other is for an RF system we had we need to generate some baseband signal that has small clock offset, so we can use correlation to obtain a delay profile.</P><P>All I need to do is as I reset the board(as a signal generator), the two outputs will reset and wait for the next time instant where two clocks have aligned edge with each other and start output on its own clock.</P>Wed, 12 Feb 2020 20:58:50 GMThttps://forums.xilinx.com/t5/Other-FPGA-Architecture/Finding-the-aligned-edge-of-two-clock/m-p/1074446#M38062changyuguo2020-02-12T20:58:50ZRe: Alignment of edge with two clock sourceshttps://forums.xilinx.com/t5/Other-FPGA-Architecture/Finding-the-aligned-edge-of-two-clock/m-p/1074451#M38063
<P>In this case, two clocks will align every 2000 period. And you may see the reason of doing this in my earlier reply.</P><P>Thanks!</P>Wed, 12 Feb 2020 21:01:52 GMThttps://forums.xilinx.com/t5/Other-FPGA-Architecture/Finding-the-aligned-edge-of-two-clock/m-p/1074451#M38063changyuguo2020-02-12T21:01:52ZRe: Alignment of edge with two clock sourceshttps://forums.xilinx.com/t5/Other-FPGA-Architecture/Finding-the-aligned-edge-of-two-clock/m-p/1074454#M38064
<P>??????</P><P>Okay, you may have two base signals with a small delta, but your sampling frequency can be the same.</P><P>anyways, according to</P><P>"<SPAN>reset the board(as a signal generator), the two outputs will reset and wait for the next time instant where two clocks have aligned edge"</SPAN></P><P><SPAN>your problem is not that of manipulating clocks (as I understood) but detecting clock coincidence. That's going to be tricky with an FPGA.</SPAN></P>Wed, 12 Feb 2020 21:08:11 GMThttps://forums.xilinx.com/t5/Other-FPGA-Architecture/Finding-the-aligned-edge-of-two-clock/m-p/1074454#M38064satguy2020-02-12T21:08:11ZRe: Alignment of edge with two clock sourceshttps://forums.xilinx.com/t5/Other-FPGA-Architecture/Finding-the-aligned-edge-of-two-clock/m-p/1074455#M38065
What do you mean by <BR />"how do I align the edge of the two clocks at some point"<BR /><BR />as you say, they will do so anyway on a regular basis.<BR /><BR />Can you draw a diagram of what you want as its not at all clear to me .Wed, 12 Feb 2020 21:10:39 GMThttps://forums.xilinx.com/t5/Other-FPGA-Architecture/Finding-the-aligned-edge-of-two-clock/m-p/1074455#M38065drjohnsmith2020-02-12T21:10:39ZRe: Alignment of edge with two clock sourceshttps://forums.xilinx.com/t5/Other-FPGA-Architecture/Finding-the-aligned-edge-of-two-clock/m-p/1074472#M38066
<P>Yes, I think I express my need inaccurately, and I have edited the original post. Thanks for pointing it out. I am trying to find where the two clocks edge align.</P>Wed, 12 Feb 2020 22:01:10 GMThttps://forums.xilinx.com/t5/Other-FPGA-Architecture/Finding-the-aligned-edge-of-two-clock/m-p/1074472#M38066changyuguo2020-02-12T22:01:10ZRe: Alignment of edge with two clock sourceshttps://forums.xilinx.com/t5/Other-FPGA-Architecture/Finding-the-aligned-edge-of-two-clock/m-p/1074475#M38067
By editing your original post, you have nullified all the following answers !!!!<BR />Wed, 12 Feb 2020 22:07:10 GMThttps://forums.xilinx.com/t5/Other-FPGA-Architecture/Finding-the-aligned-edge-of-two-clock/m-p/1074475#M38067drjohnsmith2020-02-12T22:07:10ZRe: Finding the aligned edge of two clockhttps://forums.xilinx.com/t5/Other-FPGA-Architecture/Finding-the-aligned-edge-of-two-clock/m-p/1074476#M38068
would a phase detector give you the answer your after,<BR /> The output would be proportional to the phase difference, so it will have a signal on it the zero point you have zero off set.<BR />Wed, 12 Feb 2020 22:10:01 GMThttps://forums.xilinx.com/t5/Other-FPGA-Architecture/Finding-the-aligned-edge-of-two-clock/m-p/1074476#M38068drjohnsmith2020-02-12T22:10:01ZRe: Finding the aligned edge of two clockhttps://forums.xilinx.com/t5/Other-FPGA-Architecture/Finding-the-aligned-edge-of-two-clock/m-p/1074500#M38069
<P>Thanks, I will look into it</P>Thu, 13 Feb 2020 00:05:22 GMThttps://forums.xilinx.com/t5/Other-FPGA-Architecture/Finding-the-aligned-edge-of-two-clock/m-p/1074500#M38069changyuguo2020-02-13T00:05:22Z