(programmable array logic)  PLAs (programmable logic array)  Architecture not scalable; Power consumption and delays play an important role in extending the architecture to complex designs  Implementation of larger designs leads to same difficulty as that of discrete components

and interconnection structure has caused a split in the industry
FPGA – Fine grained – Variable length interconnect segments – Timing in general is not predictable; Timing extracted after placement and route

3 LUTs and 2 Flip-flops in a two stage arrangement 2 Outputs: Can be registered or combinational External signals can also be registered More of internal signals are available for connections Can implement any two independent functions of four variables or any single function of five variables

XC4000
 XC4000

Routing Architecture

XC 4000


XC4000 Routing Architecture


Wire segments


Single length lines
Spans single CLB  Connects adjacent CLBs  Used to connect signals that do not have critical timing requirements




Double length lines
Spans two CLBs  Uses half as much switch as a single length connection




Long lines
Low skew; Used for signals such as clock  Relatively rare resource




Switch Matrix
Every line is connected to lines on the other three direction  Each connection requires six transistors


ALTERA CPLDS
 

Altera generic architecture

Hierarchical PLD structure  First level: LABs (Functional




blocks); LAB is similar to SPLDs Second Level: Interconnections among LABs

Three wide AND gate feed an OR gate (Sum of products) XOR gate may be used in arithmetic operations or in polarity selection One flipflop per macrocell; Outputs may be registered Flipflop preset and clear are via product terms; Clock may be either system clock or internally generated Output may be driven out or fedback Feedback is both local and global; Local feedback is within macrocell and is quicker

MAX 5000


MAX5000 Expander Product Term

    

Number of product terms to macrocell limited Wider functions implemented via expander product terms Foldback NAND structure Inputs are from PIA, expander product term and macrocell feedback Outputs of expander product term are sent to other macrocell and to itself

MAX 5000


MAX5000 Architecture
  



Second level of hierarchy: connections among LABs LABs are connected via PIA Interconnections may be global or local; Global interconnects uses PIA PIA consists of long wiring segments:  Spans entire length of chip and
passes adjacent to each LAB



PIA fully populated  Predictable timing

SRAM FPGA -- EEPROM FPGA


An FPGA is similar to several other types of devices which have been around for quite a while, the difference being that an FPGA is simply much more expandable and versatile. The devices which FPGAs get compared to most often are CPLDs (Complex Programmable Logic Devices), which are similar in function but typically have way less logic gates inside them; Customizable CPU design is much more feasible with an FPGA. Once upon a

SRAM FPGA -- EEPROM FPGA


when turned off; When FPGAs first came out, they used simple SRAM to hold their configuration, which of course would be lost when the device lost power. Back then, the FPGA had to be programmed from scratch every time it was turned on, usually from a separate serial ROM chip. But today, FPGAs come in Flash, EPROM, and EEPROM variants, which will retain configuration, and which can also be reprogrammed. (Fuse and anti-fuse

SRAM FPGA -- EEPROM FPGA




afterward.) Despite this, however, most FPGAs still use SRAM for reasons of simplicity (when you need to reprogram it, it's easier to re-encode a small ROM chip than to reprogram a large FPGA chip), so count on having to use a separate boot ROM for the FPGA. Use of an FPGA is broadly divided into two main stages: The first is "configuration mode", the mode in which the FPGA is when you first power it up. Configuration mode is, as you

SRAM FPGA -- EEPROM FPGA
 this

is when you load your code into it, dictating how the pins behave. Once configuration is complete, the FPGA goes into "user mode", its main mode of operation, where the programmed circuit actually starts functioning.