Details

This patch makes adjustments to account for MCLK for the internal pl180 controller being changed from assuming PCLK to assuming IDE_CLK. I noticed that by using the test_disk speed test I could vary the disk throughput of the internal SD by changing the value for IDE_CLK. Then while working on write delays to solve the data crc problems I found that I needed to lower the clock on the internal SD further to induce the problem. When I tried the assumption that MCLK was IDE_CLK instead of PCLK the results lead me to believe quite strongly that this is indeed the case.

This patch changes all references/assumptions of PCLK to IDE_CLK for the internal pl180 controller.
I have lowered the AS3525_IDE_FREQ to 50 MHz in order to be able to divide by 2 for 25 MHz on the internal SD card.
I adjusted the code in debug-as3525.c to account for the change and the frequencies reported should be correct.
I added some #if defined(HAVE_MULTIDRIVE) conditionals to cut out the code dealing with uSD for the clip.
I was also able to isolate the new write delay needed for low frequencies to only run for standard speed uSD cards. That will be the only case for an MCICLK at 15.5 MHz.

With this patch we should have the internal cards running at 25 MHz, HS uSD at 31 MHz, and standard speed uSD cards at 15.5 MHz.