Abstract : UMTS is a new radiocommunication standard aimed at solving today-s second generation networks- problems that are local saturation and slow bitrates. UMTS and previous networks sharing close to nothing regarding the radio link, network equipments as well as user equipments must be rebuilt from scratch. User equipments, in particular, must embed a lot more processing power than their older counterparts. After having introduced UMTS and the first to-be-deployed of its radio interfaces, the Wideband CDMA, we determined that the channel estimation prior to the Rake combining, assuming the receiver uses this well-known receiver structure, is the most complex task to be performed by the user equipment. An algorithmic solution to this problem is proposed through an iterative channel estimation algorithm which suppresses identified paths before trying to find new ones in the considered time window. This algorithm has a major drawback : its computational complexity varies quadratically with the oversampling factor, and thus forbids to work with high oversampling factors, which are the key to a precise channel delay estimation. An optimized version of this algorithme is proposed, whose complexity scales linearly with the oversampling factor, against a quadratic variation for the original one, and who does not cause a noticeable performance loss. The optimized channel estimation algorithm is therefore suitable for a constrained environment such as a user equipment. Furthermore, the performed optimization has the side effect of making the proposed algorithm much more suitable for a hybrid hardware-software implementation than for a pure software one. A system-level design flow is then proposed to realize this hybrid architecture while kee- ping a fast prototyping approach in mind. This methodology revolves around CoWare-s N2C environment and uses a superset of the C language called CoWareC. CoWareC includes several constructs needed to describe partitionned systems and hardware structures. The proposed al- gorithm is mapped onto a hybrid architecture composed of a ST100 DSP core and a hardware coprocessor. Due to major software issues, this hybrid implementation could not be developped following the proposed methodology, but interesting results were nonetheless obtained from a pure software implementation. The application of the first steps of the proposed methodology to the channel estimation algorithm yielded interesting results and suggestions for the improve- ment of the N2C tool. Then, hints are given for the development of a real hybrid prototype and the adequation of the proposed methodology to a fast prototyping environment is discussed.