Abstract: For traditional single or closed sourced instruction set architectures (ISAs), compliance to the ISA specification is addressed during the internal development. With the new, open standard RISC-V ISA, the compliance situation is different. In addition to the multiple IP providers many will also exploit the capability with the open ISA to add custom instructions or other optimizations. Compliance testing therefore has become mission-critical for the RISC-V ecosystem to accommodate the wide adoption and support of compatible features while retaining the optimizations that the Open ISA permits.

This tutorial presentation introduces the methodologies being developed for compliance and verification testing of RISC-V, including a framework for development of additional tests, the development of the tests, reference models, and configurations for the RISC-V specification subsets.

The tutorial covers RISC-V Compliance testing and Verification with the Open Source RISC-V Instruction stream generator developed by Google, Imperas reference simulator and models, together with Metrics cloud-based testing infrastructure with scalable capacity flexibility.

DVCon Europe is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. It brings chip architects, design and verification engineers, and IP integrators the latest methodologies, techniques, applications and demonstrations for the practical use of EDA solutions for electronic design.