Technically Speaking, Inc

Please note: This course is scheduled to run Onsite and Online simultaneously. If there is not adequate enrollment for Onsite, it may run in the Online version only.

Onsite and Online versions of this course have the exact same material and content.

Course Description

﻿This course shows you how to to build an effective FPGA design using synchronous design techniques, using the Vivado® IP integrator to create a sub-system, using proper HDL coding techniques to improve design performance, and debugging a design with multiple clock domains.

Course Outline

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Day 1

UltraFast Design Methodology Introduction {Lecture}

Scripting in Vivado Design Suite Project Mode {Lecture, Lab}

Clocking Resources {Lecture, Lab}

Synchronous Design Techniques {Lecture}

Register Duplication {Lecture}

Resets {Lecture, Lab}

I/O Logic Resources {Lecture}

Timing Summary Report {Lecture, Demo}

Introduction to Timing Exceptions {Lecture, Lab, Demo}

Generated Clocks {Lecture, Demo}

Clock Group Constraints {Lecture, Demo}

Day 2

Creating and Packaging Custom IP {Lecture, Lab}

Using an IP Container {Lecture, Demo}

Designing with IP Integrator {Lecture, Lab, Demo}

Introduction to the HLx Design Flow {Lecture, Lab, Demo}

Configuration Process {Lecture}

Sampling and Capturing Data in Multiple Clock Domains {Lecture, Lab}

Design Analysis Using Tcl Commands {Lecture, Demo, Lab}

Power Analysis and Optimization Using the Vivado Design Suite {Lecture, Lab}