i have a question about read and write using bursts on PCIe. I have a fpga which is connected through PCIe to the cpu. I have a simple driver which is just for testing. The driver writes and reads data to and from the fpga. The fpga includes an sram core where the datas are written to and read from. The read and writes are working well, but without bursts if i read from the device. If i write data to the fpga, bursts working well if i map the BAR with ioremap_wc(). But if i read from the fpga, the cpu just make single access without bursts. I found out that i have to mark the memory as write-back to be able to cache the datas on read an write transfers, but if i mark my adress write-back using /proc/mtrr there is no burst on read and write. The BAR in the PCI header is marked prefetchable. Does anybody of you know how to implement bursts for read and write on pci bus ? I hope anybody of can help me.

1 Answer
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The best way to get burst transfers on the PICe bus it to use a DMA controller instead of processor I/O. If your FPGA is a PCIe bus master, you may be able to program it to transfer the data. Otherwise there are DMA controllers built into most platforms.

I'd expect write combining to perform reads the same as uncached. But even if you use ioremap_cache(), your platform may not burst PIO reads. It can depend on your processor, the instruction doing the read and system logic.