OXFORD, England-- May 01, 2018 -- Imperas Software Ltd., the leader in virtual platforms and high-performance software simulation, and Andes Technology Corporation, today announced Open Virtual Platforms™ (OVP™) models and virtual platform support for powerful new extensions in the AndesCore™ N25 and NX25 IP processors, which are AndeStar™ V5 32-bit and 64-bit architectures based on the RISC-V technologies.

Building on the Imperas and Andes partnership to support Andes’ RISC-V cores announced in November 2017, the new Imperas reference models support the Andes AndeStar™ V5m extensions.

Imperas is the leading provider of RISC-V processor models and virtual prototype solutions, including both of the Andes N25 32-bit and NX25 64-bit cores. The new Andes models, with extensions, are available now from Imperas and the Open Virtual Platforms (OVP) website.

Charlie Hong-Men Su, Ph.D., Andes Technology CTO and Senior VP, commented, “The Imperas virtual platform solutions for software development, debug and test, along with their open-source models, will help accelerate embedded software development for SoCs capitalizing on our new extensions to the V5 AndesCore N25 and NX25 processors.”

“The momentum for RISC-V is accelerating, and Andes is the first established CPU intellectual property (IP) vendor to offer a RISC-V processor for licensing. We are pleased to support their new AndeStar V5m extensions in the OVP models of their 32-bit/64-bit CPU cores, based on RISC-V,” said Simon Davidmann, president and CEO of Imperas.

Imperas delivers a comprehensive environment for embedded software development, debug and verification for Andes N25 and NX25 processors, including open-source Fast Processor Models; extendable virtual platforms including cores and peripherals; high-performance simulation; analytical tools for hardware-dependent multicore software development, debug and test including OS-aware tools. The Extendable Platform Kits (EPKs) for Andes cores run FreeRTOS, and also support heterogeneous designs with mixtures of Andes processors and other vendors’ cores including application processors.

Imperas will provide highlights of these models and virtual platforms for RISC-V designs, based on Andes cores, with the new AndeStar V5m extensions, at the upcoming 8th RISC-V Workshop, Barcelona and the Andes Forum on May 3, 2018 in Taiwan.

These models of the extended Andes cores expand Imperas and OVP processor support to over 200 models across a wide variety of vendors. For the latest list of Imperas models, please see www.OVPworld.org.

About Andes Technology Corporation

Andes Technology, the first CPU IP supplier in Asia, has been devoting to the development of innovative high-performance/low-power 32/64-bit processors and associated SoC platforms since its foundation in 2005. Its powerful CPU lineup covering entry-level, mid-range, high-end, extensible and security families has achieved design wins in numerous embedded applications across the world, making a cumulative record of over 2.5 billion SoC shipment containing Andes IP up to 2017. While delivering advanced features based on proprietary ISAs, Andes is also the first mainstream CPU vendor adopting the open RISC-V.