By all measures, UVM is the most successful verification standard ever created in the EDA community. And that’s no boast. From inception to today, it has swept through project teams worldwide which makes it ready for the next step with the IEEE.
The IEEE 1800 committee is completing the work on UVM as the 1800.2 standard. This rigorous review of the Accellera work has resulted in some changes that improve UVM as a standard for interoperability. The tutorial will focus on those changes and how you can prepare for the IEEE standard today. As we review those changes, we will also examine the impact it will have on your existing verification environments including how to debug and regold those environments improving your ability to share verification IP among globalized teams.

The tutorial will also dive into a “UVM for RTL Designers” track. SystemVerilog is the language of choice for design verification (DV) teams, and UVM is the de-facto approach. Yet RTL designers often find it hard to use for their simple release hand-off checks or parallel verification without support from DV engineers. In this context, register interface and clock/reset-controller are the first modules to be built in any DUT and hence need a quick and easy way for the designer to build a test-bench platform to jump start design verification. The approach is to automate the generation and integration of a UVM-based test-bench through macros and API’s. Early clock, reset, and register interface verification is accomplished and the reusability for other cores/DUTs could be achieved by changing the adapter sequence/interface for the corresponding configuration bus protocol. The test-bench can also eventually be integrated into full DV environment and thus reduce the DV environment development and bring-up effort.