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AR# 25349

Description

In Timing Analyzer, some of the paths on the RGMII physical interface fail to meet timing, because Timing Analyzer is constraining the paths to only half a clock cycle. This occurs because in RGMII mode, EMAC ports EMAC#PHYTXD[3:0], EMAC#PHYTXEN, PHYEMAC#RXD[3:0], and PHYEMAC#RXDV are clocked off the rising edge while ports EMAC#PHYTXD[7:4], EMAC#PHYTXER, PHYEMAC#RXD[7:4], PHYEMAC#RXER are clocked off the falling edge of the clock. However, in the timing models, some of the data and control signals are not clocked on the correct edges, which results in some paths being over constrained to only half a clock cycle. Actually, all of the paths need to be constrained to only one clock period in the Embedded TEMAC wrapper files.

Solution

In the CORE Generator Embedded Tri-mode Ethernet MAC Wrappers v4.4 and later, the FROM-TO constraints were added to the UCF file when the wrappers are generated for RGMII.

For the EDK hard_temac v3.00.a and v3.00.b to properly constrain these paths, the following TIG constraints can be removed from system.ucf and from the hard_temac tcl file in <EDK_install>\hw\XilinxProcessorIPLib\pcores\hard_temac_v3_00_b\data\hard_temac_v2_1_0.tcl: