A certain computer system has the segmented paging architecture for virtual memory. The memory is byte addressable. Both virtual and physical address spaces contain $2^{16}$ bytes each. The virtual address space is divided into $8$ non-overlapping equal size segments. The memory management unit (MMU) has a hardware segment table, each entry of which contains the physical address of the page table for the segment. Page tables are stored in the main memory and consists of $2$ byte page table entries.

What is the minimum page size in bytes so that the page table for a segment requires at most one page to store it? Assume that the page size can only be a power of $2$.

Now suppose that the pages size is $512$ bytes. It is proposed to provide a TLB (Transaction look-aside buffer) for speeding up address translation. The proposed TLB will be capable of storing page table entries for $16$ recently referenced virtual pages, in a fast cache that will use the direct mapping scheme. What is the number of tag bits that will need to be associated with each cache entry?

Assume that each page table entry contains (besides other information) $1$ valid bit, $3$ bits for page protection and $1$ dirty bit. How many bits are available in page table entry for storing the aging information for the page? Assume that the page size is $512$ bytes.

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2 Answers

We need a page table entry for each page. For a segment of size $2^{13}$, number of pages required will be

$2^{13-k}$ and so we need $2^{13-k}$ page table entries. Now, the size of these many entries must be less than or equal to the page size, for the page table of a segment to be requiring at most one page. So,

$2^{13-k} \times 2 = 2^k$ (As a page table entry size is 2 bytes)

$k=7$ bits

So, $\text{ page size } = 2^7 = 128$ bytes

The TLB is placed after the segment table.

Each segment will have $\frac{2^{13}}{2^9}=2^4$ page table entries

So, all page table entries of a segment will reside in the cache and segment number will differentiate between page table entry of each segment in the TLB cache.

@arjun sir in the answer given is not conforming to the question, there are 8 segments, so no of pte bits will be = log(2^13/2^9) + 5 = 9 bits?????? each segment has a seperate page table and each page table entry in that page table requires 9 bits. why is he considering the entire segment as 1,there are 8 segments....

sir i am tlking about c, its given 8 segments so 2^16/8, each segment 2^13 B segmet size i presume? and only after getting the segments i can page them to a page table i presume? so 2^13/2^9 ..so 4 bits for the entries plus the extra 5 bits, so total 9 bits.

In the question it is mentioned that VM is partitioned to 8 non overlapping segments. But what about physical memory? If that is also partitioned then what you telling is correct. But such a partition is never common nor mentioned in question. So as common in most system we must assume that each segment can address any part of physical memory.

sir in part a and part b we are assuming segment size as 2^ 13 but here 2^16, then in part a and part b also can we say each segment can address any part of physical memory? i am a bit confused here sir.

In parts a and b, we are interested in the number of entries in page table/TLB which should be there for every possible page (virtual). And we are given in the question that the virtual address space is divided into 8 non-overlapping segments and hence we didivded by 8.

In 3rd part, we are finding the no. of bits in each page table entry and this is based on the physical address space. We are not dividing by 8 because we are not told that physical address space is divided into 8.

This line is written is wrong and also misleading, as no. of pages for segment would be $2^{13}/2^{9}=2^{4}$

Every segment will have sperate Page Table in Main Memory but a page table entry contains Frame Number, not a Page number, No. of pages will decide "How many entries will be present the Page table which will be 24".

And Each entry in the table will contain a Frame Number i.e 7 bit and other stuff.

Exactly this is making more sense please update that line, part a and b can be simply understood if you have clear knowledge of paging and segmentation . Please refer William stalling page 357. In part c catch is Physical space divided to achieve bits needed for frame nos as page table entry contains frame now + other bits + aging bits= 16.

So 7+5+ aging bits=16 further u can do the maths. Thanks for such beautiful answers.