They aren't orthogonal. QWFET is the result of what you get with III-V/Ge channel materials. It's like saying that branch prediction is orthogonal to out-of-order.

> Are there good reasons to believe these HAVE to be yoked together? Is it possible,
> for example (especially given Intel's difficulties and delays at 14nm) that they produce Skylake
> on 14nm, then Cannonlake on 14nm with QWFET and III-V?

That's possible, but it seems unlikely to me. What is more likely is that they shrink the conventional CMOS transistors, but use larger QWFETs. I don't think they can really get away with just using QWFETs, since some logic in modern SOCs doesn't need better performance/power.

> This would be something of a departure
> from the standard tick-tock model, but that model is merely a guideline.
> Doing this would allow them to maintain the microarchitecture cadence rather than being forced
> to slow down to match process upgrades, would allow them to debug QWFET issues on a somewhat better
> known process, and would give them another 18 months or so to deal with 10nm issues.

You're thinking about the tail wagging the dog here. Process technology is Intel's first concern. It's really easy to think of Intel as a CPU company, but they are first and foremost a manufacturing company.