Update: MIT, TI tip 28-nm app processor

SAN FRANCISCO - At the 2011 International Solid-State Circuits Conference (ISSCC) here, Texas Instruments Inc. and the Massachusetts Institute of Technology (MIT) will outline what could be a major breakthrough in the gap between performance demands and battery capacity in the mobile space.

In a paper, TI and MIT will present research detailing design methodologies for a 28-nm mobile applications processor with ultra-low power. The paper-entitled ''A 28nm 0.6V Low Power Digital Signal Processor (DSP) for Mobile Applications”-demonstrates that a DSP is capable of scaling from a high-performance mode at 1.0 volt down to an ultra-low power (ULP) mode at 0.6 volts.

This DSP is one of the first low-voltage, 28-nm designs for the mobile device market. At present, TI, Nvidia, Qualcomm and others are battling each other in the applications processor market in the mobile space. Each company is also racing each other to ship 28-nm designs.

TI's 28-nm device is based on a 4-issue, 32-register version of the TMS320C64x VLIW DSP. The system-on-a-chip (SoC) includes 32kB L1 and 128kB L2 caches, as well as I2S, SPI, UART, multimediacard and external memory interfaces.

''The design incorporates over 600k instances of custom low-voltage logic cells and 43 instances (1.6 Mb) of 6T SRAM,'' according to the paper from TI and MIT.

''Utilizing ultra-low-voltage (ULV) optimized standard-cell libraries and 6T SRAM macros, and demonstrating a new statistical static timing analysis (SSTA) methology, the SoC scales as designed from high performance at 1.0V down to ultra-low-power at 0.6V.''

The device is operational at 587-MHz at 1.0V (113mW). At 0.5V, the maximum frequency is 43.4-MHz.

The chip is made using 193-nm immersion lithography with double patterning techniques. It also makes use of a dual-gate poly/SiON gate stack. It also utilizes ''epitaxial S/D SiGe for pMOS performance enhancement,'' according to the paper. ''Typical strain techniques are also used for nMOS performance enhancement.''

But there are several challenges to enable high-performance, low-voltage designs. Two of the most prominent are low-voltage functionality and timing closure in the face of process variations, according to TI and MIT. To address these challenges, TI and MIT developed two breakthrough technologies: ultra-low voltage circuits and statistical static timing analysis (SSTA) at low voltage.

At low voltages in deep submicron process nodes, within-die random variation in transistor threshold voltage can cause circuits to have functional failures. ''A standard cell library and custom low-voltage memory using novel ultra-low voltage design methodologies are developed to be robust at 0.6V,’’ according to TI and MIT.

In addition, the delay distribution of standard cells at low voltages is no longer a Gaussian random variable. Traditional SSTA tools based on a Gaussian distribution can suffer from a 10 percent to a 70 percent underestimation of delay at 0.6V. A newly developed SSTA technique has been shown to improve the accuracy of design timing at low voltages to less than eight percent.

“As the multimedia and computing capabilities of TI’s OMAP platform-based smartphones, tablets and other mobile devices increase, there is a continually expanding gap between performance demands and battery capacity,” said Gordon Gammie, Distinguished Member of the Technical Staff at TI.

“TI believes that 28-nm process technology advancements, developed in tandem with TI and MIT’s low power circuit and methodology collaboration, gives us the right knowledge base to successfully meet the next-generation processing demands within the future mobile power envelope,” he said.

“The design of a low-voltage processor in 28-nm requires a system-level approach – from optimizing the circuit styles and memories to the development of a custom low-voltage timing flow,” said Anantha Chandrakasan, MIT professor and pioneer in the area of low-power design. “This chip demonstrates an aggressive low-power methodology to ensure robust low-voltage and ultra-low-power operation for a smartphone application processor.”

In the ISSCC paper, MIT and TI are expected to provide more details on Tuesday (Feb. 22).

Thank you for the article, Mark, and for taking the time to connect about everything. We certainly appreciate it! TingLu, to answer your question about video scaling: The static or leakage power scales approximately 13X from 1.0V down to 0.5V. – Gordon (TI)