AMD's release of its upcoming socket specifications has resulted in some third-party developers designing compatible coprocessors for use in conjunction with AMD64 processors in multi-processor boards. So far, DRC Computer Corp. and XtremeData Inc. are the first two companies to announce new products for this interface. Both companies are using FPGAs for performance optimization in a broad range of fields.

DRC provides two models based on high-speed Xilinx Virtex4 FPGAs with either 60K logic cells or 152K logic cells. XtremeData is using the largest Altera Stratix-II FPGA with 180K logic cells. Prices for these coprocessors are well beyond what most consumers will be able to pay, with XtremeData's solution listed at about US$6,500.

Configuring the FPGAs is still a relatively difficult matter, but as these products mature it is likely to get easier and more efficient. Perhaps in the future they will release products like this at a price point more reasonable for consumer consumption.

Intel Fanboys Beware(11:52am EST Thu Jun 08 2006)If these get cheap enough, it could even the field for AMD against Intel's new Conroe in some areas, including games. This is the advantage AMD's HT bus design has over Intel's. - by Seljo Myeri

GAME HARDWARE(12:23pm EST Thu Jun 08 2006)I just wish we could have Socket 939 or Socket F compatible GPUs with on-board RAM. I think it would be a great accelerator scheme.

If properly implemented, you could include a DVI port right off of a small daughter card.

What on the computer has a faster interconnect the processor socket? - by

Doubt they could survive supplying low end in terms of volume or price. Most compute intensive low end is gaming…would be interesting to see how Nvidia, ATI and other GFX companies react to the possibility of leaving their bread and butter open to the SW companies (i.e. the game companies port their game engines to these types of FPGAs.)

Only other personal coputing application would be a Java engine or something of the sort…. - by Anon

When the FPGA design is complete, it can be sent for manufacturing ASICS in quantity.

These things are too expensive for nearly any general purpose use.- by old sampler

Server chips(1:24pm EST Thu Jun 08 2006)I can see this helping database servers, bioinformatics, rendering or anything with one tight main loop.

I would like to see what it would do for databases. - by Old Timer

Nvidia, ATI, Aegia?(3:45pm EST Thu Jun 08 2006)I think those 3 are a no-brainer at this point… brewing up some kind of accelerator either in physics, graphic processing schemes, or what not. Audio, Creative Labs, may not be worth sacrificing a socket on-board… but I think those 3 big boys have a gold mine if they play their cards right. - by Treatment X

re: old timer(3:49pm EST Thu Jun 08 2006)

Databases – not much.

The main problem for databases is I/O time. There is no “tight main loop”.

Bioinformatics… some. I think it would work reasonably well at some simulations.

Rendering… a fair possibility. Considering that all GPUs are nothing more than an ASIC version of a FPGA (a BIG FPGA). The usual problem here is that a FPGA doesn't have enough logic for a complete solution.

The place I work has one of those Cray systems… with about 300 FPGAs.

So far (all year), nobody has been able to make use of the FPGAs. They work. but the applications can't use them.- by old sampler

Intel fanboys beware??(4:22pm EST Thu Jun 08 2006)I've been designing FPGA offload engines for nearly a decade. This is not a new idea or in any way proprietary to AMD. You haven't got a clue what you are talking about.

I started making video preprocessor engines for Texas Instruments DSP's ~12 years ago. 2 year ago I filed a patent for an FPGA offload engine which calculates and queues up the next tag ID for a CPU's Real Time OS. In fact this was a project we did w/ Intel and used a 1.2Ghz StrongArm CPU. This offload engine sped up it's overall performance by over 30%. Intel has since licensed this technique from us and we are using it on our current ASIC which uses a small ARM9 CPU.

Nearly anyone who has ever designed an FPGA has done some kind of CPU acceleration function in one, it's not hard to find something your CPU is doing very inefficiently and accelerate it in hardware. We do it all the time.

Xilinx's biggest and baddest parts go for well over $2000. The most expensive x86 CPU in the world goes for about 1/2 of that and has a maximum clock speed of 4x to 40x depending on what you put in the FPGA. FPGA offload engines work best when they can do a lot of work totally independent of the CPU and then just hand them the answer. They simply can not 'talk' to a 1Ghz front side bus or other high speed interface fast enough for them to do “real” co-processing (i.e being inserted into the CPU's instruction pipeline and executing certain instructions in parallel which are especially designed the FPGA).

I have done this w/ some small CPU's that were in the FPGA itself at 150Mhz speeds, but not at x86 speeds which are ~3Ghz for AMD and ~4Ghz for Intel. I have yet to see an FPGA clocked at over 1Ghz. - by EE

old sampler – FYI(4:46pm EST Thu Jun 08 2006)FPGA's and ASIC's are designed exactly the same way. Guys like me design circiuts using some flavor of HDL (Hardware Definition Language) the most common are Verilog and VHDL. I prefer Verilog but I use both. As long as the desin doesn't include custom components (i.e PLL's, SERDES, specific SRAM's, DLL's, etc). The same HDL that gets mapped into an FPGA can also be mapped into an ASIC process without altering much code except what we call the pad ring were the pins go, all pins are vendor specific. FPGA parts only have on kind of pin and the FPGA compile tool figures out how to hook them up based on your HDL. ASIC's on the other hand have 100's of different pin structures and you have to hook them up yourself.

But the core logic is 99.9999% of the gates and it's usually identical for either an FPGA or ASIC.

———-

Using HDL a many 1000 logic gate structure can be implemented with just a few lines.

A 64 bit loadable counter which requires several 100 gates boils down to this

reg [63:0] cntr wire [63:0] inc_val wire reset_n, load, cnt_en

always @(posedge clk_200) begin if (~reset_n) cntr = cntr end

This way a million gates ASIC can be designed with only a few 10,000 lines of HDL. Otherwise a designer couldn't live long enough to actually draw a million gate circuit.

Maybe you care, maybe you don't, but this is how we design these parts. - by EE

Supplying their own(9:13pm EST Thu Jun 08 2006)AMD might make their own components to pop into those extra sockets with HT to memory.I could see AMD making chips without SIMD (SSE/2/3) and then having a SIMD component that have improved performance. I guess like a Cell processor only just the SPU's. - by meh

EE(9:19pm EST Thu Jun 08 2006)Homer: Uh, excuse me, Professor Brainiac, but I worked in a nuclear power plant for ten years, and, uh, I think I know how a proton accelerator works.

Buddy, your 64-bit loadable counter doesn't do anything, nor does it come out of X. Plus it is poorly coded and ugly.

And don't say “this is how we design these parts” b/c you can't even design a 64-bit loadable counter. - by EE is dork

Hmmm(10:19pm EST Thu Jun 08 2006)I think FPGA's would be great for stripping/converting X86 code into something simpler (would be good to use on a cell, convert existing X86 data into C for execution)…

I didn't get hard yet(12:00am EST Fri Jun 09 2006)M'fer. LOL. when it gets hard…I can drill your dark charcoaled mom and your sisters at the same time. Of course, I don't want any diseases so I won't. - by then, bammmm!

EDD(2:22am EST Fri Jun 09 2006)2 people died from being overworked at the California Dept… EDD.

apparently, they overworked and was affraid to ask for help.

at age 50 and 53. - by sad, thanks ARNOLD

re: EE(11:07am EST Fri Jun 09 2006)Unlike others, I do have a PRIMITIVE view of the logic. It looks like every access to the counter causes it to increment, with control logic to clear it.

It is my understanding that the primary difference between the ASIC and FPGA is that the FPGA uses RAM(or eeprom) to define the gate structure. The FPGA also has to have the circuits to load the RAM,and control the FPGA (start/stop/load RAM/ reset…).

ASICS on the otherhand, do not have that overhead. The RAM is a rom. The space used for the overhead in the FPGA is/can be dedicated to additional logic. Hence, an ASIC tends to have more available logic than a FPGA. ASICS can also run faster (no need to clock sync with RAM programming).

My contact with FPGAs has been indirect – no real project experience. But seeing the development environment required shows the limitations of FPGAs. Most designs of ASICS I've seen break the design up, then use FPGAs to design and test the parts. The final ASIC design is a combination of all the parts put into prototype ASICs (quantities less than 100, one design I read over had only 10).

When finally debugged/verified/whatever, the final design is put into production ASICs – where desired quantities would be in thousands.

In the suggested use mentioned in the article, it looks like the FPGA can cause catastrophic system failure. Both from a security standpoint, and from an operational one. Not a problem for a standalone development workstation environment – but terrible for a production system.

Even in the Cray environment, the FPGAs can crash nodes (it needs a custom library to be included with the users logic to interface with the rest of the system).- by old sampler

XtremeData's Response(3:32pm EST Fri Jun 09 2006)I hope I can clear up some of the speculation on this thread.

The XD1000 has always been intended for HPC applications that have a high degree of parallelism. Will there ever be a check box for the XD1000 on Dell's web site? Possibly. The strength of an FPGA is that it can be reconfigured for every application that runs. The result is that every software package that runs on a desktop PC could come with its own FPGA co-processor configuration file. Gamers would pay for that. As the quantities go up the cost will come down. Remember, $6,500 is for a quantity of one. If Mr. Dell gives me a call, I'm sure we would be able to work out a better price for his 10 million customers. If you doubt that reconfigurable computing will never make it to the mainstream then go check out Intel's vision of the future, platform 2015. Reconfigurability cost more up front, but is more flexible than fixed computing in the long term.

With respect to crashing and reliability, I can tell you that our group has experience building medical systems consisting largely of FPGAs. In that environment it is ILLEGAL to drop data. Any system is likely to crash during development, but in production, FPGAs are no more likely to fail than any other component.

It's true that FPGA co-processors are not new. The difference today is that now they can be directly coupled to the CPU, they have lots of dedicated DRAM, the power supply and heat dissipation issues are taken care of by the host motherboard, and the dominate CPU company AMD (a little sales here!) is willing to support the whole idea.

If you think the XD1000 is just for designers targetting an ASIC then you should know that we built this board for our own HPC project. Old Timer will not have to wait long to find out what this can do for databases.

EE(8:39pm EST Sat Jun 10 2006)I feel good when I lay the smack down on dumb or inferior people like EE. That's what I do best. - by Xman

EE(5:31am EST Sun Jun 11 2006)“FPGA's and ASIC's are designed exactly the same way. “

Your wrong! - by Einstein

EE(9:29am EST Sun Jun 11 2006)HIS wrong?! - by The REAL Einstein

Xman(1:52am EST Mon Jun 12 2006)oldfart. - by EE

BS from AMD!(9:55pm EST Mon Jun 12 2006)More or less more AMD marketing BS and paper launches… Argue all you want over this vapourware (which is what the AMD marketing peeps wants.. to generate more BUZZ for AMD). - by AMDnoob