EUV Still Promising on IMEC's Road Map

LEUVEN, Belgium -- The view of extreme ultraviolet lithography (EUV) has always been a bit rosy from this part of the world, where it is being born. So it's no surprise that EUV held a relatively sunny spot in an otherwise fairly detailed and balanced semiconductor road map the IMEC research institute showed at an annual press event here.

The development of the latest MOPA light source for EUV put the weakest component in the long-delayed lithography system on a more steady footing, they said. Researchers now expect to demo an 80W light source in a working system by the end of the year, a 125W version next year and a 250W one capable of driving commercial throughput of 125 wafers/hour by the end of 2015.

At that cadence, chip makers still need to rely on prior generation immersion lithography for their initial offering of 10nm technology. However, they could be able to insert a pilot line of EUV at the same time, cutting over at least a few critical steps soon afterwards.

"I would not be surprised if they come up with a 9nm node using EUV," said An Steegen, who manages the IMEC division that handles process technology research.

Immersion systems may need 22 masks at 10nm, up from ten at 28nm, essentially using costly triple patterning in a handful of layers and double patterning at all others. EUV could cut that down to ten masks at 10nm, researchers estimate.

Despite big investments from Intel, TSMC, and Samsung in ASML, EUV's developer, there's still no guarantee it will meet its planned schedule. In addition to the light source issues, EUV faces a handful of other challenges including the potential of embedded reticle defects no existing tool can find yet.

Steegen said EUV could survive additional delays. "I see there are lots of insertion points for EUV down the road in both 10nm and 7nm nodes -- and a node lasts 6-10 years in manufacturing," Steegen said.

In contrast to her upbeat view on EUV, Steegen was down on fully depleted silicon-on-insulator, an alternative to FinFETs championed by STMicroelectronics.

Although IMEC supports work on FD-SOI at 14nm today, it will drop it from its road map beyond that node. "I don't see any demand for it," she said.

FD-SOI offers lower performance than FinFETs and the potential of higher power due to its use of forward biasing. In addition, its relatively thin substrate introduces manufacturability concerns, Steegen said.

The following pages provide excerpts from Steegen's presentation here.

I watched/listened to a video interview in the past year given by Debra Vogler, in that interview An gave enough reasons to show why EUV is basically "out there" forever, saving my efforts. Dragging N10 and N7 nodes to a decade or longer, is "out there" forever.

For the memory portion, I was a bit surprised that there was not more focus on vertical NAND or future vertical 3D-NVM. That technology has just recently been announced, while FinFETs have been around much longer.

Also, why so much focus on STT-MRAM? They should know it is quite a fragile device. More fragile than a transistor at leading edge. The read is not 100% non-destructive, for the spec that is expected (quadrillion times).

"Immersion systems may need 22 masks at 10nm, up from ten at 28nm, essentially using costly triple patterning in a handful of layers and double patterning at all others. EUV could cut that down to ten masks at 10nm, researchers estimate."

So, again confirming, essentially just one node (10 nm) for EUV single patterning. Same situation faced 157 nm, with far less drastic infrastructure changes required.

I nelgected to note IMEC's CTO told me in the last year one of the programs that got the most ramping up at IMEC was on direct self assembly which they now show in their road map as having a significant role at 5nm helping beyond what EUV can/cannot do.