Digital Circuits/Flip-Flops

A flip-flop is a device very much like a latch in that it is a bistable multivibrator, having two states and a feedback path that allows it to store a bit of information. The difference between a latch and a flip-flop is that a latch is asynchronous, and the outputs can change as soon as the inputs do (or at least after a small propagation delay). A flip-flop, on the other hand, is edge-triggered and only changes state when a control signal goes from high to low or low to high. This distinction is relatively recent and is not formal, with many authorities still referring to flip-flops as latches and vice versa, but it is a helpful distinction to make for the sake of clarity.

There are several different types of flip-flop each with its own uses and peculiarities. The four main types of flip-flop are : SR, JK, D, and T.

An SR(Set/Reset) flip-flop is perhaps the simplest flip-flop, and is very similar to the SR latch, other than for the fact that it only transitions on clock edges. While as theoretically valid as any flip-flop, synchronous edge-triggered SR flip-flops are extremely uncommon because they retain the illegal state when both S and R are asserted.

The D flip-flop is the edge-triggered variant of the transparent latch. On the rising (usually, although negative edge triggering is just as possible) edge of the clock, the output is given the value of the D input at that moment. The output can be only changed at the clock edge, and if the input changes at other times, the output will be unaffected.

Clock

D

Qnext

Comment

0

0

Express D at Q

1

1

Express D at Q

Otherwise

X

Qprev

Hold state

D flip-flops are by far the most common type of flip-flops and some devices (for example some FPGAs) are made entirely from D flip-flops. They are also commonly used for shift-registers and input synchronisation.

The JK flip-flop is a simple enhancement of the SR flip-flop where the state J=K=1 is not forbidden. It works just like a SR flip-flop where J is serving as set input and K serving as reset. The only difference is that for the formerly “forbidden” combination J=K=1 this flip-flop now performs an action: it inverts its state. As the behavior of the JK flip-flop is completely predictable under all conditions, this is the preferred type of flip-flop for most logic circuit designs. But there is still a problem i.e. both the outputs are same when one tests the circuit practically. This is because of the internal toggling on every propagation elapse completion. The main remedy is going for master-slave jk flip-flop,this flip-flop overrides the self(internal) recurring toggling through the pulsed clocking feature incorporated.

A circuit symbol for a T-type flip-flop: T is the toggle input and Q is the stored data output.

A T flip-flop is a device which swaps or "toggles" state every time it is triggered if the T input is asserted, otherwise it holds the current output. This behavior is described by the characteristic equation:

and can be described either of the following tables:

Characteristic table

T

Q

Qnext

Comment

0

0

0

Hold state

0

1

1

1

0

1

Toggle

1

1

0

Excitation table

Q

Qnext

T

0

0

0

0

1

1

1

0

1

1

1

0

When T is held high, the toggle flip-flop divides the clock frequency by two; that is, if clock frequency is 4 MHz, the output frequency obtained from the flip-flop will be 2 MHz. This 'divide-by' feature has application in various types of digital counters. A T flip-flop can also be built using a JK flip-flop (J & K pins are connected together and act as T) or D flip-flop (T input and Qprev are connected to the D input through an XOR gate). d t