SoCs need logical virtual prototype

Many of today's system-on-chip (SoC) designs cause significant problems and delays as they go through the physical design process. Yes, physical design is harder than ever. But part of the problem is that many issues are not addressed at the register-transfer level and are a direct reflection on how the RTL is coded.

The old adage "garbage in, garbage out" is very applicable here. If the physical design starts with "clean" code, the process is much smoother. Many first order physical design problems can be addressed at the RTL coding stage, including issues with routability and timing. By addressing these issues before the physical design process, design teams can save weeks or months of physical design time.

This issue was first addressed in the late 1990s by new tools that created a silicon virtual prototype. This helped designers determine, early in the design cycle, the best way to physically connect all the blocks and eliminate many design practices that were leading to virtually unroutable designs.

These tools helped the physical integration problem, but did nothing for the logical integration problem. The silicon virtual prototype tells the design team nothing about the logical structure of the design. As a matter of fact, with a silicon virtual prototype, a chip with logical errors can make it through the design and manufacturing process - with the resulting need for an expensive respins.

The physical design process is already sufficiently challenging without imposing the additional requirement that it filter out poorly integrated RTL. Before it is meaningful to do trial physical design runs with a physical virtual prototype tools, the SoC integrator must be sure that the logical design is correctly hooked up. What we need is a way to make the integration easier and, therefore, the physical design process less challenging.

Before the physical virtual prototype is created, another virtual prototype is needed - a logical virtual prototype. With a logical virtual prototype, each block in the design can be examined and checked carefully for integration issues. The logical virtual prototype can be implemented as the RTL code blocks are designed or as IP is purchased from third parties or corporate databases. As the SoC is built, so too is the logical virtual prototype.

What kinds of issues can a logical virtual prototype find? These issues can be divided into two main categories: issues within blocks and integration issues that cross block boundaries.

Issues within a block seem straightforward - designers have been working on these for years. However, many of these issues are not that simple. Often problems only show up after lengthy simulation runs (if the right test vectors are used) or at the gate level after synthesis. These problems include structural issues such as problems with inferred latches, flip flops, muxes and counters. More complex issues, such as combinational loops, decoding errors, multi-clock domains and complex synchronization problems, also need to be isolated as early in the design cycle as possible, before physical design begins.

There's a wide range of problems that can occur once different blocks are put together. What if different blocks have different clocking schemes? It's essential to check clock domain crossing points and types of synchronization before synthesis because afterwards multiple static timing analyses, requiring days of delay, are required to find these problems. What about testability of the blocks? What if some blocks don't include test mode bypass for ATPG? What if most of the blocks use a positive edge reset, but some reset on the negative edge? There are a number of integration issues along the lines of clock phasing, synchronization, verification, re-use and testability. Simulation does not even address lot of these issues.

As chip size and complexity increases, creating a logical virtual prototype will become even more important than creating a physical virtual prototype. The logical virtual prototype can help prevent time-consuming problems that can show up only during physical design, when it's very difficult to go back to the logical structure of the design and make the necessary changes. Significant time often is wasted re-doing parts of designs because of major integration issues. Or worse yet, designs with logical errors can make their way into today's very expensive production process.

Ghulam Nurie is senior vice president of marketing and business development at Atrenta Inc., a provider of predictive analysis tools.