AMD preps global webcast on next-gen server interconnect tech

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AMD is preparing a global webcast for the sixth anniversary of their Opteron server processor. Next Wednesday, on April 22 at 10am PT (1pm ET), AMD will give us a preview of their future server roadmap, as well as a look at the next generation of Direct Connect Architecture. The 1.5 hour event is entitled, AMD on the Future of Server Technology.{ad}

When Opteron was introduced on April 22, 2003, it was AMD’s first CPU to implement their K10 microarchitecture, which included a single x86-64 core at 1.4 GHz and an 800 MHz FSB. Over time it has evolved to include virtualization extensions for Hypervisor OS support, multiple cores and has migrated to its current 45nm form.

Opteron has seen 130nm SOI, 90nm SOI DDR, 90nm SOI DDR2, 65nm SOI and 45nm SOI to date. A select number of E4 stepping Opterons were recalled due to possible errors when operating floating-point intensive code sequences at elevated processor temperatures. AMD and OEMs replaced the potentially defective (not all of the recalled CPUs were actually defective) free of charge.

AMD’s biggest problem with their AMD64 CPUs came in the form of a Translation Lookaside Buffer (TLB) error which caused AMD to issue a “stop ship” order on all Barcelona-core Opterons. The errata resulted in a required disabling of the TLB, which affected performance in varying degrees up to 50% reduction in throughput on certain types of programs. This errata was later fixed and AMD has not had any such issues since their most recent Shanghai quad-core implementation, though it only clocks to 2.9 GHz — presumably due only to quad-core thermal issues as their older 90nm dual-core versions clock to 3.2 GHz. Unofficial tests have reported Shanghai can actually clock well beyond 3.2 GHz.