News

HIPPEROS Technology Showcase at Hannover Messe 2018

Thursday 22 March 2018

HIPPEROS will be present this year at Hannover Messe on April 25th and 26th in Hall 6 Booth G46 at the stand of the EuroCPS H2020 research project with our partners CEA-LETI, Thales and other members of the project consortium.

HIPPEROS will demonstrate the results of its completed IMICRASAR project to enable efficient mixed criticality applications on multicore platforms, namely a Thales avionics platform and use case. Other HIPPEROS use cases such as high-performance computer vision will also be featured.

Using HIPPEROS middleware is the ideal solution to lower time, cost and effort to create all kinds of smart embedded, high end IoT and edge computing devices.

Take the opportunity to Win a HIPPEROS Development Kit! Come to our stand and take part in the draw to win a complete hardware & software HIPPEROS Development Kit.

Videos

EuroCPS H2020

Thursday 22 March 2018

Publications

Success Story for Mixed Criticality Avionics

Thursday 12 April 2018

The EuroCPS consortium has just released the success story related to the development by HIPPEROS of a high-performance multicore mixed-criticality platform for aerospace, robotics and automotive systems. HIPPEROS ported his RTOS on a Thales platform using a Freescale PowerPC multicore board, which Thales uses for safety critical avionics applications, performance benchmarks and isolation characteristics, and implemented a mixed-criticality scheduler with almost perfect performance scaling.

HIPPEROS is a family of new multicore hard real-time operating systems (RTOS) for safety critical applications, specifically designed to provide the highest reliability, predictability, security and performance while using multicore architectures efficiently, taking into account their specific constraints and features.

HIPPEROS is a highly configurable and modular family or RTOSs. This way, we can produce different kernels that satisfy different requirements, adapting to different use cases. All these "flavors" share nevertheless compatibility for applications.

HIPPEROS is predictable, fully preemptive and multitasking. Its architecture makes it scalable and efficient for multicore platforms. Specific features have been included in its design to ensure fault tolerance, redundancy and to obtain its formally proven reliability.

HIPPEROS is aimed at certifiability by different norms. It is prepared to meet the requirements and growing complexity of different application domains taking into account the specific needs of every case.

Currently available RTOS in the market were not originally designed for multicores. Therefore, they do not scale well and their design is not able to cope efficiently with the challenges of multicore architectures or growing application demands. This is either unsafe or an inefficient use of computing resources.

HIPPEROS was created at the PARTS (Parallel Architectures for Real-Time Systems) Research Center of the ULB, to incorporate major scientific results in the area of real-time scheduling, resource sharing, scalable Inter Process Communication protocols and operating systems kernel architectures.

Preemption avoiding mechanism

HIPPEROS has a small footprint (typical down to <= 20k ELOC, low task switch latency (typical down to ~5μs depending on architectures), almost zero interrupt latency and high task set safe utilization limits (typical >90%).

This small footprint makes it suitable for very high performance computing tasks, as code runs "almost like on bare metal".

HIPPEROS already supports or aims to support supports 32-bits and 64-bits architectures with or without MMU, of different vendors:

ARM A9, ARM Cortex-A8+, ARM Cortex-R+

IA 32 x86, IA 64 x86

ARC

Leon3, 4

PPC

MIPS

HIPPEROS can be tailored for specific MPSoC designs.

Specific versions for 16 bits architectures or hybrid architectures without MMU are foreseen for microcontrollers, eg MSP430 and AVR.

HIPPEROS is compatible with most embedded toolchains, including IAR, Keil, and GCC.

HIPPEROS product features include concurrency mechanisms like spinlocks (avoided when possible), mutexes, semaphores, message passing, mailboxes, signals and shared memory. It includes events, timers, alarms and very efficient and scalable IPC and resource sharing protocols. Starvation and deadlock detection and avoidance mechanisms are part of the design, as well as recovery watchdogs and priority inheritance & priority ceiling mechanisms.

HIPPEROS Monitor serves as a watchdog to ensure no corruptions happens on any component of the system:

Kernel

Drivers

Services

Application Tasks

HIPPEROS Monitor will catch & handle faults, cleanup and restart processes and services. It prevents rogue applications or byzantine processes to create trouble. It can recover any part of the system, including itself. System restart should never happen, unless there is a major hardware fault.

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