BF547 EPPI DMA urgency

I'm running into a problem with using the DMA urgency fields (particularly FIFO_RWM) in the EPPIx_CONTROL register under a specific set of conditions. I am configured in 16-bit word mode, and I am attempting to receive just 2 words over the PPI bus. I realize this type of very short one-shot transfer is not the intended use of a PPI bus, but it seems to be within the bounds of functionality described in the HRM. I have a generic driver that will accept application-level requests to transfer 1 to 2^16 words, and so this type of really short transfer is within the bounds of what I'm attempting to support. All transfers are type GP with 1 external frame sync.

When I leave the FIFO_RWM field at a value of 00b, it works correct for any transfer size. However, when I try to set the FIFO_RWM field to a value of 11b (25% full), the data is not received for very small transfer such as 1, 2, or 3 words. If I attempt a larger transfer, say 512 words, the interface works fine. I have not tried to identify the exact value at which it transitions from non-working to working.

When the FIFO_RWM field is set to a non-zero value for a receive scenario, my understanding is that the initial DMA transfer is not kicked off until the FIFO has accumulated enough words to reach the regular watermark. In my scenario, I believe the transfer in its entirety does not reach that point, and so the data is never moved from the FIFO to L3, even after the PPI transfer count has been satisfied.

Is this plausible? For what it's worth, I am setting the SYNC bit in the DMA config register as well. I am using a BF547 rev 0.3.

Thanks for the reply, but I have thoroughly read section 15 of the HRM and it does not seem to address my question. The page you referred me to states that the data is not DMA'd out of the FIFO until the regular watermark is reached (states T1/T2).

My question is: what happens if the transfer count is so short that the amount of data in the FIFO never reaches the regular watermark, even after the PPI transfer has completed? In this case the DMA never seems to occur, from what I can observe.

Thanks, this answers my question with the resolution that the FIFO_RWM cannot be used in my scenario.

The confusion is that the state flow described on page 15-68 does not show what happens at the end of the transfer. In my case, I was wondering what happens if a PPI transfer is completed and the PPI controller stopped, but we never progressed past state T1 because the number of received words was very small. It seemed intuitive that the PPI controller would avoid loss of data by ensuring that any words pending in the FIFO would be DMA'd out when the PPI controller stops, but I understand now that the data will be lost in this scenario.

In summary, the FIFO_RWM field should only be used on receive if you can guarantee that the number of words received will exceed the watermark, else the received data will be lost.