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AR# 35537

12.4/13.4/14.7 Place - How do I debug Automatic Clock Placement failures?

Description

My design failed with the following clock placement error.

What is the clock placer and what can I do to debug this issue?

ERROR:Place:703 - Automatic clock placement failed. Please attempt to analyze the global clocking required for this design and either lock the clock placement or area locate the logic driven by the clocks so that the clocks may be placed in such a way that all logic driven by them may be routed. The main restriction on clock placement is that only 10 of 32 clocks sourced by global buffers may enter a region. For further information see the "Clock Resources" section in the Virtex-5 User Guide

Solution

The clock placer exists because of the need to manage the routing restrictions of the global clocks.

Each clock region has global routing resources for up to 8 clock domains in a Virtex-4 device, up to 10 in a Virtex-5 device, and up to 12 in a Virtex-6 device.

The clock placer has to first choose locations for each clock component (in concert with the I/O placer) and then automatically control clock region usage using range constraints to floorplan the design.

It will take all user constraints into account when constructing this floorplan.

The clock placer prints a verbose report containing a distribution of the clock domains by clock region and a list of the constraints that were used to achieve that floorplan.

If the clock placer fails to find a solution, the distribution report will allow you to identify the clock regions that are over utilized.

Once you have identified the problem clock region(s) it is possible to take the constraints generated by the automatic placement attempt and tweak them to alleviate the congested clock regions.

Check for the following issues:

Are there a number of components with various clocks constrained to the problem clock region (i.e., I/O clocks)? Can they be moved elsewhere?

Is there a clock domain in the clock region that could easily be constrained elsewhere? Check for a slice-only clock domains with non-critical timing requirements.

Are there large components (PPC, BRAM, DSP, etc.) with multiple clocks that could be constrained elsewhere?

Once you have decided on the constraint changes needed to resolve the clock region congestion, move the clock placement constraints found in the map log file (.map) to your user constraints file (.ucf) and edit them appropriately.

For a complex clocking structure, it might take a few iterations to find a solution.