Applications

Digital rights management (DRM)

HDCP 2.0 implementations for generic wired and wireless interfaces

Components

HDCP software written in C (CPU subsystem is not included)

Hardware accelerators
- AES1-CTR-HDCP: AES encryption/decryption capable of handling the PES streams
- RSA2: An RSA hardware accelerator (optional, high-end CPUs can use the software
implementation)
- TRNG1: A true random number generator (optional, if entropy bits are available in the design, a
software implementation can be used)
- SHA2-256: A Sha-256 hash accelerator (optional, most CPUs can use the software
implementation)

Function Description

The HDCPS suite includes hardware and software components. Supplied components are highlighted on the
diagram below.

Implementation Details

Component

ASIC, NAND gates

Dedicated memory, bits

CPU code size, bytes

CPU data size, bytes

NVRAM, bytes

HDCP protocol

8KB

4KB

6KB

AES1-8CTR-HDCP

10K

RSA2

12K

18K or 6K (note 1)

SHA2-256

18K

TRNG1

9K

RSA software

5KB

3KB

TRNG software

1.5KB

SHA-256 software

2KB

Notes:
1. RSA2 can either have 3072-bit support, or just 1024. In the latter case, the dedicated memory requirements are 3x times lower, yet RSA-3072 will be implemented in software (add the software modules size to the RAM/ROM requirements)