Stacked Die Moves From Drawing Board To Reality

After decades of moving in a straight line from one process geometry shrink to the next, much of the semiconductor industry has taken a step back to figure out what comes next. While companies such as Intel, IBM and Samsung continue to look as far ahead as the 3nm process node, along with new materials to improve electron mobility and new transistor designs based on electron tunneling and carbon nanotubes, there also is a lot of experimentation under way using a combination of techniques at new and older nodes.

For most chipmakers, the sticking point is the price tag. With the aid of multi-patterning, even 193nm immersion lithography can make feature shrinks work. But does manufacturing the entire chip at the most advanced node make sense for the same sales volume if the cost of design and manufacturing are both increasing? And from return-on-investment perspective, where is the greatest power/performance gain per dollar?

A year ago, the answers were almost overwhelmingly tied to process shrinks. Increasingly, that approach is coming under scrutiny, particularly with EUV lithography still not ready for prime time. The result is far more interest in alternatives such as 2.5D—including multiple versions of 2.5D architectures—as well as fan-outs, along with fully depleted silicon on insulator at 28nm where the same tools and manufacturing can be used.

“The number one reason why we are seeing interest in 2.5D is that if you break an SoC down into smaller pieces you get better yield,” said Shafy Eltoukhy, vice president of operations and technology development at Open-Silicon. “You will get two to three times the yield from doing it this way. The number two reason is that you may not need everything in the same process node. If we can get the cost of the interposer down to a penny per square millimeter, that will be about $600 per wafer. Right now it’s about 3 cents per square millimeter, but within two years we will be at a penny.”

Putting this into real numbers, a 300 square millimeter chip that yields 45% will yield 70% at 150 square mm and 80% if there are four die being used in place of one. On top of that there the advantages in NRE and time to market will become more obvious, he said.

Design changes
But just moving to multiple die isn’t so simple—at least not if chipmakers are really looking for improvements in performance and power, which are two other key reasons for connecting multiple chips connected with either interposers or through-silicon vias.

“This isn’t just assembly and ship it off to a foundry,” said Javier DeLaCruz, senior director of engineering at eSilicon. “Right now, most of the 2.5D chip we’ve seen have been from one vendor, so you’ve got the same dies talking to themselves, to memory, and over SerDes. The big shock is that to get the real advantages of 2.5D, you’ve got to make a chip that only works in 2.5D.”

And those advantages are significant for companies that can take advantage of them. A process shrink results in a 20% to 30% power or performance or area improvement, according to Brandon Wang, director of 3D-IC solutions at Cadence. “If you use a full 3D-IC, you get a three to five times improvement in bandwidth, a 40% to 50% improvement in power, and a 40% savings on the package size. And you get all three of those at once. It’s not one or the other.”

While 2.5D doesn’t provide as dramatic improvement as true 3D-ICs, the gains can be significant because the distances are shorter, bandwidth is higher, and the amount of effort need to drive signals is lower. Wang said the goal for both GlobalFoundries and TSMC is to push 2.5D to a very low price point, making it available for broad markets such as the Internet of Things, ultra-mobile devices, and microcontrollers.

“The processor road map for scaling is in very good shape, but the cost is so steep that there will only be three or four customers moving there,” said Wang.

Simplified integration and test
Still, while some companies may waffle on moving to 2.5D, the move to the next process node by shrinking features is getting more difficult, as well. Even test, which is fairly straightforward at 28nm, is a lot different using 16/14nm finFETs.

“With finFETs, the critical dimensions of the features are smaller than the node,” said Steve Pateras, product marketing director at Mentor Graphics. “That affects defectivity and performance. So we’re seeing renewed interest in covering defects with test and are working on how well we can match full-transistor ATPG to the problem. Right now it’s hard to get to volume.”

He said that with finFETs, two of the big challenges are testing the interconnect at the intra-package level, and testing for power. While testing full 3D-ICs with TSVs can more convoluted, testing a 2.5D architecture—particularly a planar version with an interposer in the middle—is much more straightforward.

Also more straightforward is the integration of IP. Steve Smith, senior director of production marketing for AMS verification at Synopsys, said one of the big attractions with 2.5D is the ability to differentiate because the rules are not as rigid. If something doesn’t work with something else, it can simply be moved to a different die—which is particularly important for companies looking to differentiate themselves. Restrictive design rules for 14nm SoCs are significant.

“For companies going to the next generation of chip, this simplifies IP integration and provides them with an advantage,” said Smith. “With mixed signal content most companies try to model that out, but there are so many variations in analog that you have to simulate the digital and analog together.”

Getting stacked die out the door requires some business model changes, though. While interposers add to the cost—at least for now—the savings on integration, IP reuse, yield and NRE collectively may be lower than moving down a process node.

“We’re starting to see this changing in meetings we have with customers,” Smith said. “In the past, the package guys typically wouldn’t talk to the IC design group. We’re seeing all of them in meetings now, along with engineering managers. We’re even seeing this in EDA, where there are more decisions across groups these days.”

It also requires some significant changes in the supply chain and even in how chips are designed, verified and tested.

“When you bring in die from different sources, who owns the yield?” asked eSilicon’s DeLaCruz. “We need to vet suppliers and check out the chips they’re developing. We need to be able to trace how a die performs relative to how centered it is in the foundry process. And we need to be able to subtract out effects to characterize doie, which goes well beyond the limitations of tools and characterization today. What’s also new is that you will have to test each chip by itself, and all of this has to be part of the architecture even before you pull together the RTL. It changes the way chips are designed.”