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AR# 24688

9.1i PAR - Unroutable non-clock pins on global clock nets

Description

Keywords: WARNING:Route:436

My design fails to route successfully, and one of the following warning messages occurs. When I examine the unrouted net in FPGA Editor, I see that this is a clock net driven by a global buffer and some non-clock pins are failing to route successfully. What are the routing restrictions for non-clock pins driven by global buffers?

WARNING:Place:913 - Local congestion has been detected at location SLICE_X76Y156. There is a limitation that at most 4 global signals can drive non-clock pins per CLB. The placer has detected SLICE_X76Y156 is present in a CLB that has5 global signals driving non-clock pins. This may result in an unroutable situation.

WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish the rest of the design and leave them as unrouted, The cause of this behavior is either an issue with the placement or unroutable placement constraints. To allow you to use FPGA editor to isolate the problems, the following is a list of (up to 10) such unroutable connections: Unroutable signal: clk19 pin: net_name/AX

Global buffers can drive non-clock pins on slices, but there are some limits on the routing resources available to do this. Until now, the placer has not taken this into account and occasionally a design will run afoul of these limitations and be unroutable. Beginning with 9.1isp2, the placer checks for these routability restrictions and avoids them. These checks are on by default for Virtex-5 but must be turned on with an environment variable for Virtex-4.

Virtex-4

Rule 1: There can be at most 4 global clocks or constant signals driving non-clock pins per CLB (four slices per CLB).

Windowsset XIL_PAR_ENABLE_CHKNONCLKPINS=1

Linux or Solarissetenv XIL_PAR_ENABLE_CHKNONCLKPINS 1

Virtex-5

Rule 1: There can be at most 2 global clocks driving non-clock pins per CLB (two slices per CLB). Constant signals do not compete for these resources as in Virtex-4.

Rule 2: If the CI pin in a CLB is used, the DX/CX pins cannot be driven by a BUFG. Similar for BI and AX/BX pairs.

A separate check can be enabled for this CI/BI restriction by setting the variable: