Racetrack Memory to Beat Hard Drives & Flash

PORTLAND, Ore. — Racetrack memories -- invented at IBM -- are attracting the attention of researchers at the University of California at Davis (UC Davis) who believe they have a promising new material that can make racetrack memory a reality. Working with the Semiconductor Research Corporation in Research Triangle, N.C., UC Davis researchers are attempting to build racetrack memories from nanowires, resulting in memories that are faster, higher capacity, more reliable, and use less power than hard drives (HDs) or solid-state flash.

"The trend today is to put solid-state flash memory into computers, but it's very expensive compared to hard drives," Bob Havemann, Director of Nanomanufacturing Sciences at SRC told EE Times. "But if we can succeed in configuring these racetrack memories we'll have increased speed, lower costs, higher capacity, more reliability and improved energy efficiency."

The work was prompted by UC Davis researchers who have been studying the unusual properties of a complex oxide called LSMO (La0.67 Sr0.33 Mn O3), which exhibits novel magnetic, electrical, and optical properties.

"We have been studying complex oxide materials or multiferroics, because their magnetic state can be changed not only by magnetic fields, but also by electric fields and by light," Yayoi Takamura, a professor at UC-Davis, told EE Times. "And with SRC we have been patterning them into the kind of geometry you would need to build a racetrack memory -- one-dimensional nanowires with notches in them to trap magnetic domain walls."

A racetrack memory works similarly to a hard disk, but is completely solid state, since instead of the disk spinning its magnetic domains under the write head, in racetrack memories the magnetic domains travel around a closed track consisting of a notched nanowire. The magnetic state of the nanowire can be changed by a write head positioned over it, which can change the magnetic orientation between each notch, then moves all the patterns encoded along the length of the wire to the next notch thus invoking the metaphor of a racetrack.

The team assigned red (magnetization pointing right) to be "1" and blue (magnetization pointing left) to be "0"; four notches along a one-dimensional nanowire with only one domain wall are in white. In Panel (b) (shown on left), the data before the domain wall are "1"s and the data after the domain wall are "0"s, as indicated that in the detail view of Panel (b) (right side). Panel c shows a different shaped domain wall. (Source: UC Davis)

"IBM's previous work was on metallic materials, but we're looking at these complex oxides and trying to understand their differences and how they may work better than metallic materials if configured as a racetrack memory," Takamura told EE Times.

It will be at least a year before Takamura's group attempts to build a complete racetrack memory, for which they will need the help of one of SRC's members to fabricate the chip. Right now UC Davis is growing its own films, but they have to send the wafers to Oak Ridge National Laboratories to pattern them into notched nanometer-sized wires. Other organizations assisting the Takamura Research Group included the Center for Nanophase Materials Sciences and the Advanced Light Source at Lawrence Berkeley National Laboratory.

Takamura told EE Times:

We don't have a [racetrack] prototype device at this point. What we have is a demonstration in which we can see similar phenomena that must occur in the racetrack memory device in a completely different material family, in this case complex oxides, compared to the metal systems that are typically employed. Our next step will be to study the geometry of the nanowires, the optimal shape of the notches and how closely together we can pack them which defines the density of the memory.

The challenges that remain include optimizing the shape of the domain walls formed, controlling their position within the nanowires and mastering their movement along around the nanowire racetrack. The parameters to be optimized include the intensity of the applied magnetic and electrical fields, light irradiation levels, pressure and temperature,

While NVM has found it's way into the secondary storage hierarchy, I was always uncomfortable when folks would say that traditionally architected NVM memory would displace rotational media. Packing bits back to back vs. requiring transistors for storage and decoding will always have the potential for higher density. As such, I used to flippantly assert "rotational media always wins". For awhile, I was worried as NAND densities increased and then I saw the Racetrack Memory annoucement. Whew! A new type of rotational media. What else would you expect from the inventors of the HDD.

Max migjht say "That's a bit too close to home." In his presence bacon-based memory is extremely volatile to be sure! No analog meats (or meat analogs) for him. Digital meat could be a different story.

I suspect that Max is trying to develop memories with a new kind of bit--bacon bits, which would allow him to snack on unused memory. :) "Uh yeah, that was a 1Meg memory but actually only 732Meg is available. A few of the nibbles are dedicated."

I remember reading that bubble memory had fast seek times (no rotational delay/head seek time), but data transfer was equal to the hard drives of the time.

I still get a laugh when a friend was confidently predicting that bubble memory was going to replace main memory back in the 80's.

I got a bigger laugh when a buzzword spouting VP of Technology toured our programming offices in the early 90's and was making the same claim, but with Flash memory. I guess he thought "flash" meant fast.

As I recall, to get this arrangement, there had to be three transistors in the cell, one for handling the read MTJ, one for the write head and finally one (I/O grade) to push the track along. So it's a huge cell size.

Looks more like a DRAM in the sense that reading is destructive and you need to rewrite after read, but because read is serial you effectively need to shift the whole memory out to get to the one word you actually want and rotate the read values back in at the top again. This might lead to very long access times unless each line is very short (eg a few bits long) in which case you need an awful lot of them which might cost a lot of power.

If the read/write circuitry is large then it would not be possible to have that many copies which would force you into having long access times, etc.

BUT if the race track is really a loop, eg two lanes one running left to right the next running right to left, then you might be able to shift it all around without rewriting, you just need to keep track of how many times you need to rotate to reach the value you want. But this still is likely to lead to long access times and a lot of localised caching ie you red out a very wide word and hope that you can work in that for a long time before fetching the next, and also hope that the next wanted value is adjacent.

Random access is not going to be good - but as this is a speculated model for replacing disks rather than RAM the serial access model is actually what we expect.

So does this yield a smaller magnetic domain than you get with a conventional harddrive? As it will need optical patterning that seems unlikely - bit sizes will be comparable to FLASH (ie a few line widths). So it may be a competitor for using FLASH in SSD if the access time, power consumption etc pan out, the gamble being that the bits of the FALSH architecture that enable random access are unnecessary overhead for the SSD application.

If you can get away from optically patterning the memory wires, however, then the tradeoff changes radically. If by self-assembly you can get the separate wires and the notch pattern then the domains could shrink to much smaller than a FLASH memory bit potentially and that is more credible than self-assembling the relatively complex internals of a FLASH cell.