Exclusive: TSMC plots microelectronics future

Taipei, Taiwan -- The world's leading semiconductor foundry, Taiwan Semiconductor Manufacturing Company, (TSMC) recently detailed its plans to dominate the "system super-chip" market in an exclusive EE Times interview with its chief technology officer and vice president of R&D, Jack Sun.

"If anybody pushes Moore's Law to extremes, TSMC will be there too, but that is not all we do," said Sun. "We also have specialized technologies such as embedded flash, high-voltage, power transistors, MEMS and image sensors -- a spectrum of technologies. And as we move monolithic CMOS on to more advanced nodes, all these other technologies can not be moved along with it -- that's where our interposers and 3-D technologies will enable system integration that allows them all to be used together in what we call a system super-chip packages."

Thus 3-D and wafer-scale packaging techniques are not just a way to achieve higher densities than scaling alone can achieve, but a means of delivering super-systems that move beyond system-on-chip (SoC) to systems of diverse integrated technologies that make TSMC unique as a foundry.

"We have three basic focuses: the first is to continue to push monolithically in CMOS to get the most energy efficient transistors -- providing the largest number of transistors running at the lowest power. We consider CMOS to be like the brain of a system. Secondly we provide specialty technologies that are like your eyes and ears and that are analog and mixed signal. Then thirdly, we provide 3-D technologies with TSVs [through silicon vias], interposers and other wafer-level package capabilities, which allows us to integrate the most advanced logic chips with our specialty technologies. Of course, some customers just want SoCs -- and that is fine -- but others will want to take advantage of our ability to use 3-D integration to make the whole system smaller using system-scaling and system integration -- what we call system super-chips."

TSMC's Jack Sun plots the future of semiconductors as its chief technology officer (CTO) and vice president of R&D.

Today Xilinx is the only announced customer of TSMC's first-generation 3-D technology -- so-called 2-1/2 D silicon interposers, which it uses to integrate multiple field-programmable-gate arrays (FPGAs) along with other chips, such as the high-speed transceivers used on the world's fastest single-chip serializer/deserializer, the Virtex-H580T SerDes. TSMC, however, also claims to have many other customers in the process of using its silicon interposers and other wafer-scale technologies for creating system super-chips.

"TSMC, of course, serves a broad spectrum of customers, but the driver of future growth is mobile systems that people want to take everywhere, connected to anybody at anytime, which can all be enabled with silicon-based system-level packaging that is smaller, lighter and lower power," said Sun.

Few topic come to mind if there is a follow up to this article with TSMC:
-what is TSMC's plan to bring the costs down in 3D IC integration?
-why isn't TSMC actively promoting / nurturing ecosystem partners that can perhaps develop cost-effective technologies (such as interposers, cooling technologies, etc) than organic efforts?
-is there a product vision / road map for heterogeneous integration?
MP Divakar

Sure 10nm can be done with ebeam....but at what cost is the right question.
Not cost effective for mainstream SOC. moores law roadmap is becomming clearer. 28nm is lowest cost per transistor and where bulk of cost sensitive SOC made

Chipmonk - you posted this back in November and you were right on the money.
3D is too costly for low priced SoCs
"Haswell is going to be a 2.5 d module with the Level 4 cache chip next to the processor, the chips connected by fine-pitch high-density thin film interconnects on the Si substrate of the module. Will have lots of interconnects, enabling lots of parallelism in memory accesss by multi - core in CPU / SoC. BTW won't be able to stack chips ( true 3D ) because need to take heat out of the 10 watt CPU."

TSMC is right in finally accepting that there is a long way to go in terms of design methodology yield improvement etc. before they can hope to use 3D die stacking for jelly - bean like Smart Phones. Since they seem to be putting a lot of their competitive eggs ( vis a vis Intel ? ) into the basket of stacking dissimilar dice by 3D, wish the EE Times reporter had quizzed them on specifics and not let them get away with "motherhood" type statements.
Oh well !