Intel Outlines 14nm, Broadwell

SANTA CLARA, Calif. -- Intel provided the first details of its 14nm process technology, now qualified for volume production in an Oregon fab, and gave a sneak peak at Broadwell, its first CPU to use it.

Intel claims its 14nm process delivers a lower cost per transistor than its 22nm node thanks to aggressive area scaling using self-aligned double-patterning lithography. It said the process will enable a new class of x86-based 2-in-1 tablet/notebooks less than 9 mm thick that will be on store shelves before the end of the year.

Intel reserved details of Broadwell products until its annual developer forum in San Francisco next month. But it did give some specs for its 14nm FinFETs. Compared to Intel's 22nm process, it will have:

42nm fin pitch, down .70x

70nm gate pitch, down .78x

52nm interconnect pitch down .65x

42nm high fins, up from 34nm

a 0.0588 micron2 SRAM cell, down .54x

~0.53 area scaling compared to 22nm

Products using the 14nm process have been delayed nearly a year due to yield problems. "Scaling the gate and fin pitches as aggressively as we have were reasons for yield challenges, but we are in a very healthy range now and will continue to improve," said Mark Bohr, a senior fellow for the company's logic development group.

Mark Bohr holds a 14nm Intel wafer.

The area shrinks came in part from building taller fins packed more closely together. The shrinks were needed to overcome wafer costs, which rose faster than normal with a new node due to the need for double patterned lithography. Intel rejected the litho etch/litho etch technique, using instead self-aligned double-patterning.

Netting out rising wafer costs and shrinking transistors "for Intel, cost per transistor continues to come down, if anything at a slightly faster rate," said Bohr.

He claimed Intel still has a significant lead over the rest of the chip industry despite delays of nearly a year in shipping 14nm products. "Intel is shipping a second generation of FinFET technology before others shipped their first," he said. With previous planar nodes, "others have tended to have better density than Intel but came to market later," he noted.

@3D guy - Intel gets plenty of incentives from the state of Oregon, Ireland and Israel. Not so sure about Arizona and New Mexico, but I imagine there must be a big carrot to keep them in these 2 dry states where water is at a premium.

The technical achievements by Intel at 14nm are excellent. Achieving 0.53 area scaling compared to 22nm requires incredibly complex processing technology for control of fin height, pitch, and passivation coverage.

The next step of manufacturing 50K or 80K wafers per month with high yields and high reliability is another order of magnitude in complexity. Let us hope for the electronics industry that Intel will achieve its goal of reaching high volume production in Q1 or Q2/2015.

The other vendors of FIN-based products have similar challenges to Intel, and it is realistic to expect them to have a similar time line between when the process was initially stable to when high volume of cost competitive products that also have high reliability is achieved.

Intel's progress to date is an outstanding achievement by the company and its ecosystem partners.

I don't know if it's that Intel uses SADP while foundries use LELE. SADP would restrict layouts strongly, which fits Intel's manufacturing style (they used to be a memory company). Another is they they staged their big technology transitions over many generations (45 nm high-k, 32 nm immersion, 22 nm FinFET, 14 nm double patterning). Instead of one big barrier at 2X nm.

To be fair TSMC has never said they are equal density at 16nm node (they said will catch up at the 10nm node).

Edited.

Asking to other engineers: TSMC and Samsung cells are 1T fin, Intel cell is 2T fins so the comparison is not fair.

Very likely both TSMC and Samsung will utilize a larger 2T cell for faster phone SOCs, still it is only a my idea. Sure the 1T cofiguaration is a limiting factor in abailable clock speed ad low power consumption.

We'll see Intel SOC process, it is unlikely an even smaller cell footprint for certain applications with 1T layout, like is happened on 22nm with the 1T 0.092um2 cell.

A question that always comes up for me when I see Mark Bohr boasting about Intel's process technology load over TSMC:

Intel may show TSMC having higher gate pitch x metal pitch. But I think the true comparison would be cost per transistor. TSMC owns significantly cheaper fabs than Intel, thanks to much better government incentives than exist in Taiwan (vs. the US). My experience is that the cost difference can be ~30% or sometimes even more. I wonder if Intel really has a significant lead in cost per transistor?