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Abstract:

Embodiments herein provide data recovery techniques and configurations
for solid state memory devices. For example, a method includes
identifying a hard error associated with a cell of a solid state memory
device, providing a location of the cell having the identified hard error
to a decoder to recover data originally programmed to the cell, and
recovering the data originally programmed to the cell using the decoder.
Other embodiments may be described and/or claimed.

Claims:

1. A method comprising: reading data programmed in a first plurality of
cells of a memory device; decoding the data read from the first plurality
of cells of the memory device, including in response to a failure to
decode, in a first attempt, the data read from the first plurality of
cells of the memory device, (i) reprogramming the first plurality of
cells with a known data pattern, and, (ii) based on the known data
pattern reprogrammed in the first plurality of cells, identifying a
location of one or more cells of the first plurality of cells of the
memory device that caused the failure, in the first attempt, to decode
the data read from the first plurality of cells of the memory device; and
in a second attempt to decode the data read from the first plurality of
cells of the memory device, decoding the data read from the first
plurality of cells of the memory device in view of the location of the
one or more cells of the first plurality of cells of the memory device
that caused the failure, in the first attempt, to decode the data read
from the first plurality of cells of the memory device.

2. The method of claim 1, wherein identifying the location of the one or
more cells of the first plurality of cells of the memory device that
caused the failure, in the first attempt, to decode the data read from
the first plurality of cells of the memory device comprises: subsequent
to the first plurality of cells of the memory device being reprogrammed
with the known data pattern, reading out readout data from the first
plurality of cells of the memory device; comparing the readout data with
the known data pattern; and based on comparing the readout data with the
known data pattern, identifying the one or more cells of the first
plurality of cells of the memory device that caused the failure, in the
first attempt, to decode the data read from the first plurality of cells
of the memory device.

3. The method of claim 2, wherein identifying the location of the one or
more cells of the first plurality of cells of the memory device that
caused the failure, in the first attempt, to decode the data read from
the first plurality of cells of the memory device further comprises:
identifying the location of the one or more cells of the first plurality
of cells of the memory device, if the readout data pattern is different
than the known data pattern.

4. The method of claim 2, wherein the known data pattern comprises the
data read from the first plurality of cells of the memory device.

5. The method of claim 2, wherein: reprogramming the first plurality of
cells with a known data pattern comprises iteratively reprogramming the
first plurality of cells of the memory device with the known data
pattern; and the location of one or more cells of the first plurality of
cells of the memory device that caused the failure, in the first attempt,
to decode the data read from the first plurality of cells of the memory
device is identified based on the iterative reprogramming the first
plurality of cells of the memory device with the known data pattern.

6. The method of claim 5, wherein iteratively reprogramming the first
plurality of cells of the memory device with the known data pattern
comprises: using a different known data pattern for each iteration.

7. The method of claim 1, wherein decoding the data read from the first
plurality of cells of the memory device comprises: using a soft decoder
or a hard decoder for decoding the data read from the first plurality of
cells of the memory device, wherein the soft decoder or the hard decoder
uses an error correction code (ECC) for decoding the data read from the
first plurality of cells of the memory device.

8. The method of claim 1, wherein decoding the data read from the first
plurality of cells of the memory device in view of the location of the
one or more cells of the first plurality of cells of the memory device
that caused the failure, in the first attempt, to decode the data read
from the first plurality of cells of the memory device comprises: using
erasure decoding for decoding the data read from the first plurality of
cells of the memory device.

9. The method of claim 8, wherein using erasure decoding comprises:
erasing a bit or symbol in the data read from the first plurality of
cells of the memory device that corresponds to the location of the one or
more cells of the first plurality of cells of the memory device that
caused the failure, in the first attempt, to decode the data read from
the first plurality of cells of the memory device.

10. The method of claim 1, wherein decoding the data read from the first
plurality of cells of the memory device in view of the location of the
one or more cells of the first plurality of cells of the memory device
that caused the failure, in the first attempt, to decode the data read
from the first plurality of cells of the memory device comprises:
bit-flipping at a location in the data read from the first plurality of
cells of the memory device that corresponds to the location of the one or
more cells of the first plurality of cells of the memory device that
caused the failure, in the first attempt, to decode the data read from
the first plurality of cells of the memory device.

11. An apparatus comprising: a memory device; a computer-readable storage
medium; and instructions tangibly stored in the computer-readable storage
medium, the instructions being executable by a programmable processor to
enable the programmable processor to read data programmed in a first
plurality of cells of a memory device, decode the data read from the
first plurality of cells of the memory device, including in response to a
failure to decode, in a first attempt, the data read from the first
plurality of cells of the memory device, (i) reprogramming the first
plurality of cells with a known data pattern, and (ii) based on the known
data pattern reprogrammed in the first plurality of cells, identifying a
location of one or more cells of the first plurality of cells of the
memory device that caused the failure, in the first attempt, to decode
the data read from the first plurality of cells of the memory device, and
in a second attempt to decode the data read from the first plurality of
cells of the memory device, decode the data read from the first plurality
of cells of the memory device in view of the location of the one or more
cells of the first plurality of cells of the memory device that caused
the failure, in the first attempt, to decode the data read from the first
plurality of cells of the memory device.

12. The apparatus of claim 11, wherein the instructions are being
executable by the programmable processor to enable the programmable
processor to identify the location of the one or more cells of the first
plurality of cells of the memory device that caused the failure, in the
first attempt, to decode the data read from the first plurality of cells
of the memory device by: subsequent to the first plurality of cells of
the memory device being reprogrammed with the known data pattern, reading
out readout data from the first plurality of cells of the memory device;
comparing the readout data with the known data pattern; and based on
comparing the readout data with the known data pattern, identifying the
one or more cells of the first plurality of cells of the memory device
that caused the failure, in the first attempt, to decode the data read
from the first plurality of cells of the memory device.

13. The apparatus of claim 12, wherein the instructions are being
executable by the programmable processor to enable the programmable
processor to identify the location of the one or more cells of the first
plurality of cells of the memory device that caused the failure, in the
first attempt, to decode the data read from the first plurality of cells
of the memory device by: identifying the location of the one or more
cells of the first plurality of cells of the memory device, if the
readout data pattern is different than the known data pattern.

14. The apparatus of claim 12, wherein the known data pattern comprises
the data read from the first plurality of cells of the memory device.

15. The apparatus of claim 12, wherein: the instructions are being
executable by the programmable processor to enable the programmable
processor to reprogram the first plurality of cells with the known data
pattern by iteratively reprogramming the first plurality of cells of the
memory device with the known data pattern; and the location of one or
more cells of the first plurality of cells of the memory device that
caused the failure, in the first attempt, to decode the data read from
the first plurality of cells of the memory device is identified based on
the iterative reprogramming the first plurality of cells of the memory
device with the known data pattern.

16. The apparatus of claim 15, wherein the instructions are being
executable by the programmable processor to enable the programmable
processor to iteratively reprogram the first plurality of cells of the
memory device with the known data pattern by: using a different known
data pattern for each iteration.

17. The apparatus of claim 11, wherein the instructions are being
executable by the programmable processor to enable the programmable
processor to decode the data read from the first plurality of cells of
the memory device by: using a soft decoder or a hard decoder for decoding
the data read from the first plurality of cells of the memory device,
wherein the soft decoder or the hard decoder uses an error correction
code (ECC) for decoding the data read from the first plurality of cells
of the memory device.

18. The apparatus of claim 11, wherein the instructions are being
executable by the programmable processor to enable the programmable
processor to decode the data read from the first plurality of cells of
the memory device in view of the location of the one or more cells of the
first plurality of cells of the memory device that caused the failure, in
the first attempt, to decode the data read from the first plurality of
cells of the memory device by: using erasure decoding for decoding the
data read from the first plurality of cells of the memory device.

19. The apparatus of claim 18, wherein the instructions are being
executable by the programmable processor to enable the programmable
processor to use the erasure decoding by: erasing a bit or symbol in the
data read from the first plurality of cells of the memory device that
corresponds to the location of the one or more cells of the first
plurality of cells of the memory device that caused the failure, in the
first attempt, to decode the data read from the first plurality of cells
of the memory device.

20. The apparatus of claim 11, wherein the instructions are being
executable by the programmable processor to enable the programmable
processor to decode the data read from the first plurality of cells of
the memory device in view of the location of the one or more cells of the
first plurality of cells of the memory device that caused the failure, in
the first attempt, to decode the data read from the first plurality of
cells of the memory device by: bit-flipping at a location in the data
read from the first plurality of cells of the memory device that
corresponds to the location of the one or more cells of the first
plurality of cells of the memory device that caused the failure, in the
first attempt, to decode the data read from the first plurality of cells
of the memory device.

[0002] Embodiments of the present invention generally relate to memory
devices, and more particularly, to data recovery techniques in solid
state memory devices.

BACKGROUND

[0003] In solid state memory, such as flash memory, data is typically
stored in an array of cells using a charge trap or an isolated region of
the cells. The cells may, for example, store one bit of information per
cell in single-level cell (SLC) devices, or more than one bit per cell in
multi-level cell (MLC) devices. A measured threshold voltage of the cell
generally corresponds with a value of the data stored on the cell.

[0004] Data loss in solid state memory may occur for a variety of reasons
including, for example, wear of cell materials and charge leakage. When
such data loss is due to cell degradation, a shift in the threshold
voltage may occur, resulting in data read errors of the degraded cell.
Simply rereading or retransmitting the signal of the cell generally
results in the same errors for degraded cells and fails to recover the
data. Likewise, erasing and reprogramming the degraded cells generally
results in similar errors.

[0005] As data density increases, a solid state memory device may rely on
error correction code (ECC) for data integrity protection. In the case of
an error correction code (ECC) decoding failure, a simple reread or retry
of a degraded cell generally gives rise to little improvement over single
read operations. Multiple reread and subsequent ECC decoding may be
ineffective, for example, because the decoding failure may be a result of
write-in error.

SUMMARY

[0006] In various embodiments, the present disclosure provides a method
comprising identifying a hard error associated with a cell of a solid
state memory device, providing a location of the cell having the
identified hard error to a decoder to recover data originally programmed
to the cell, and recovering the data originally programmed to the cell
using the decoder.

[0007] In various embodiments, the present disclosure provides a method
comprising reading data stored on a cell of a solid state memory device
using a modified reference signal that is different than a reference
signal normally used to read the data, forming an erasure flag based on
the data read from the cell, the erasure flag indicating that at least
one value of the data read from the cell is marked for erasure, and
decoding the data read from the cell using the erasure flag.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments of the present invention will be readily understood by
the following detailed description in conjunction with the accompanying
drawings. To facilitate this description, like reference numerals
designate like structural elements. Embodiments of the invention are
illustrated by way of example and not by way of limitation in the figures
of the accompanying drawings.

[0009]FIG. 1 is a flow diagram of a method to recover data in a solid
state memory device.

[0010]FIG. 2 is a flow diagram of a method to identify hard errors in a
solid state memory device.

[0011]FIG. 3 is a flow diagram of a method for adjusted re-read using a
modified reference signal and erasure decoding.

[0015]FIG. 7 schematically illustrates an example electronic system for
implementing techniques of a solid state memory device as described
herein.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

[0016] Embodiments of the present invention describe techniques and
configurations for improved data recovery in solid state memory devices
and for data storage systems based on solid state memory devices. In the
following detailed description, reference is made to the accompanying
drawings which form a part hereof wherein like numerals designate like
parts throughout, and in which is shown by way of illustration
embodiments in which the invention may be practiced. It is to be
understood that other embodiments may be utilized and structural or
logical changes may be made without departing from the scope of the
present invention. Therefore, the following detailed description is not
to be taken in a limiting sense, and the scope of embodiments in
accordance with the present invention is defined by the appended claims
and their equivalents.

[0017] The description may use the phrases "in an embodiment," or "in
embodiments," which may each refer to one or more of the same or
different embodiments. The phrase "in some embodiments" may be used
repeatedly. The phrase generally does not refer to the same embodiments;
however, it may. The terms "comprising," "having," and "including" are
synonymous, unless the context dictates otherwise. The phrase "A and/or
B" means (A), (B), or (A and B). The phrase "A/B" means (A), (B), or (A
and B), similar to the phrase "A and/or B." The phrase "at least one of
A, B and C" means (A), (B), (C), (A and B), (A and C), (B and C) or (A, B
and C). The phrase "(A) B" means (B) or (A and B), that is, A is
optional.

[0018] The terms "predictor," "optimizer," "analyzer," or "system level
manager" may refer to respective hardware and/or software implementing
entities, and do not include a human being. For example, the operations
performed by the "predictor", "optimizer," "analyzer," or "system level
manager" are operations performed by the respective hardware and/or
software implementations, e.g., operations that transform data
representative of real things from one state to another state. Such
operations do not include mental operations performed by a human being.

[0019] Various operations may be described as multiple discrete actions or
operations in turn, in a manner that is most helpful in understanding the
claimed subject matter. However, the order of description should not be
construed as to imply that these operations are necessarily order
dependent. In particular, these operations may not be performed in the
order of presentation. Operations described may be performed in a
different order than the described embodiment. Various additional
operations may be performed and/or described operations may be omitted in
additional embodiments.

[0020]FIG. 1 is a flow diagram of a method to recover data in a solid
state memory device. At block 102, the method 100 includes reading data
stored on one or more cells of a solid state memory device. Generally, a
read operation relies on comparing a threshold voltage applied to the one
or more cells with a reference signal to determine a programmed state of
the cell. One or more bits of data may be stored on each cell. The solid
state memory device may include memory devices based on semiconductor
materials, such as flash memory, but is not limited in this regard.

[0021] At block 104, the method 100 includes decoding the read signals.
Decoding may be performed, for example, by a variety of soft or hard
decoders, such as a Bose, Ray-Chaudhuri, Hocquenghem (BCH) decoder or
low-density parity-check (LDPC) decoder. Decoding may include error
correction code (ECC) decoding and associated techniques, such as
Reed-Solomon decoding and/or Hamming decoding. Subject matter is not
limited in this regard and decoding may be performed according to other
suitable decoding techniques in other embodiments.

[0022] At block 106, a determination is made of whether the decoding fails
or succeeds. If the decoding succeeds, the data is output at block 108.
If the decoding fails, one or more hard errors are identified at block
110. A hard error includes read and/or decoding errors associated with
degraded cells that are typically not repairable. In other words, erase
and reprogram operations typically fail to correct hard errors of such
cells. An embodiment of identifying one or more hard errors, at block
110, is further described with respect to FIG. 2.

[0023]FIG. 2 illustrates a method 200 to identify the one or more hard
errors. The method 200 includes, at block 202, copying the data from the
one or more cells that fail decoding at block 106 to another location.
The one or more cells that fail decoding at block 106 may be erased, if
desired. Then, the one or more hard errors are identified by
reprogramming the one or more cells with a known data pattern at block
204, reading out the one or more reprogrammed cells at block 206, and
comparing the known data pattern to the readout data pattern at block
208, to identify the locations of the hard errors at block 210. For
example, a cell may be identified as having a hard error if the readout
data is different than the known data for the cell.

[0024] Operations at blocks 204, 206, 208, and 210 may be repeated one or
more times, at block 212, using the same or different known data patterns
to identify hard errors more accurately and completely. At least one of
the known data patterns reprogrammed at block 204 may be similar or based
on the data readout at block 102. The hard error locations may be output
at block 216. In an embodiment, the known data comprises readout data of
the originally programmed data, at block 102, that results in a failure
to decode the one or more cells, at block 106.

[0025] Returning again to FIG. 1, at block 112, the method 100 includes
providing a location of the one or more hard errors to the decoder. The
locations of the one or more hard errors are output at block 216 (FIG. 2)
of the method 200 and provided to the decoder to improve decoding. Data
bits that are stored in degraded cells having identified hard errors may,
for example, be marked or flagged as erasures for ECC decoding. Other
techniques to record and/or provide locations of cells having identified
hard errors may be implemented in other embodiments.

[0026] At block 114, the method 100 includes decoding using the hard error
locations to recover the originally programmed data, which is the data
programmed to the one or more cells prior to being read at block 102. A
decoder informed with the hard error locations may provide increased
error correction capability. For example, an ECC decoder can erase the
bits identified as hard errors for further decoding or flip the
bits'identified as errors for further decoding. In erasure decoding, a
decoder informed with hard error locations can correct 2T erasures,
comparing to T erroneous symbols for Reed-Solomon code with error
correction power T symbols. Thus, erasure decoding may be used to
increase a number of errors that an ECC decoder can correct if the error
locations are known. In another example, the informed decoder can
implement a bit-flipping technique to retry the decoding with a variety
of value combinations for the bits identified with hard errors. Decoding
with informed hard error locations may recover the originally programmed
data.

[0027] In an embodiment, the originally programmed data is recovered, at
block 114, by an erasure decoding technique. An example of hard decoding
by erasure is provided below to clarify the principles described herein.
For example, the originally programmed data may include bit values (1 0 0
0 1 1 0) encoded with Hamming code having error correction power T=1. At
block 102, the readout data may, for example, provide bit values having
two errors at the third and fourth bits (1 0 1 1 1 1 0). The two errors
in the readout data exceed Hamming code correction capability, resulting
in an ECC decoding failure at block 106. The data is copied to another
block and the current block may be erased, at block 202, to allow
identification of the one or more hard errors at block 110.

[0028] At block 204, the cells are reprogrammed with a known data pattern.
In an embodiment, the known data pattern includes bit values that are
each switched from the data readout at block 102. For example, if the
data readout at block 102 is (1 0 1 1 1 1 0), the known data pattern may
include (0 1 0 0 0 0 1). Reading out the known data pattern, at block
206, may provide bit values (0 1 1 10 0 1), which indicate hard errors at
the third and fourth bit locations because the readout data is different
than the known data pattern at the third and fourth bit locations, in
accordance with blocks 208 and 210.

[0029] In response to the identified hard error locations, at block 110,
the third and fourth bit locations of the originally programmed data are
erased and decoded, at block 114. The two erasures allow Hamming decoding
to succeed and output the recovered data (1 0 0 0 1 1 0) at block 116.

[0030] Similar principles may be used to provide soft decoding by erasure.
For example, log-likelihood ratios (LLRs) can be set to zero for
corresponding bits identified with hard errors. In a case where the
readout data LLRs include (-9.2 +10.5 +13.2 +11.2 -3 -9 +16) and the
third and fourth bits are identified as hard errors, the input to a soft
decoder may include, for example, LLRs (-9.2 +10.5 0 0 -3 -9 +16).

[0031] In another embodiment, the originally programmed data is recovered,
at block 114, by a bit-flipping technique. In bit-flipping, combinations
of bit values are programmed in the identified hard error positions until
decoding succeeds. For example, if originally programmed data (1 0 0 0 1
1 0) encoded with Hamming code is read out as (1 0 1 1 1 1 0), at block
102, then an ECC decoding failure, at block 106, may result because the
two errors exceed Hamming code correction capability for error correction
T=1. Reprogramming with known data (0 10 0 0 0 1) and comparing the
readout data (0 1 1 10 0 1) of the known data with the known data, at
blocks 206 and 208, identifies the hard errors at the third and fourth
bit positions, at block 210.

[0032] Once the hard error locations are identified, a bit at the hard
error position of the originally readout data, at block 102, is flipped
in value. For example, the third bit of the readout data (1 0 1 1 1 1 0)
may be flipped from 1 to 0 to provide (1 0 0 1 1 1 0). As only one error
remains, Hamming decoding at block 114 succeeds to correct the remaining
error, and outputs the recovered data (1 0 0 0 1 1 0), at block 116.

[0033] Although bit-flipping has been described using an example hard
decoder above, bit-flipping may be implemented for a soft decoder as
well. Bits corresponding to hard error locations may be exhaustively
flipped to the opposite sign for soft decoding. For example, LLRs may be
saturated or set to a desired magnitude with sign corresponding to the
flipped value. In a case where readout data LLRs include (-9.2 +10.5
+13.2 +11.2 -3 -9 +16) and the third and fourth bits correspond with hard
error locations, the third bit may be flipped and saturated to provide
(-9.2 +10.5 -16 +11.2 -3 -9 +16) for decoding at block 114. If decoding
is successful, the value is output at block 116, otherwise bit-flipping
may continue. For example, if decoding fails, the fourth bit may be
flipped and saturated and sent to decoding again. If decoding still
fails, both the third and fourth bit may be flipped and saturated and
sent to decoding again. Bit-flipping of the hard error locations may
occur in any order and with any combination of values.

[0034]FIG. 3 is a flow diagram of a method 300 for adjusted re-read using
a modified reference signal and erasure decoding. At block 302, the
method 300 includes reading data stored on one or more cells of a solid
state memory device. The one or more cells may be read, for example, by
comparing a threshold voltage applied to a cell with a reference signal
to determine a programmed state of the cell. Threshold voltages for
different cells may vary for a variety of reasons. For example, the
variations may be due to differences in programming and/or other cell
characteristics, such as wear of the cell material or leakage.

[0035] Referring briefly to FIG. 4, an example plot 400 schematically
illustrates threshold voltage distributions 402, 404, 406, 408,
statistically distributed around an ideal mean S1, S2, S3, S4 for each of
four respective bit values (11), (10), (01), (00) of a two-bit cell. Plot
400 further depicts reference signals v1, v2, v3 that are used to
determine the programmed state of the cell. For example, if the threshold
voltage of a cell is found to be lower than the reference signal, v1,
along voltage axis, V, then the data stored in the cell is read to be
(11).

[0036] Cells that have threshold voltages in the shaded regions 410, 412,
414 are susceptible to read and/or decoding errors due to their proximity
to the reference signals v1, v2, v3. Small noise or disturbance during a
read operation can result in a change in detected bit value across the
nearest reference signal for such cells. Such marginal cells may provide
effective erasure targets for erasure decoding.

[0037] Returning again to FIG. 3, the method 300 further includes decoding
the readout data, at block 304. If decoding is successful, then the
decoded data is output, at block 306. Otherwise, for a decoding failure,
the data is reread using a modified reference signal, at block 308.
Rereading with a modified reference signal may generate more effective
erasures, resulting in more effective erasure decoding.

[0038] Marginal cells are more effectively identified by modifying the
reference signals during reread, at block 308. Referring briefly to FIG.
5, for example, a threshold voltage, r1, represented by the star symbol,
lies within a shaded region 510 near a reference signal, v1, which is
normally used to read the data. If r1 is read using the normally used
reference signal v1, for example, the value would be detected to be (11).
However, the detected data for r1 is becomes (10) instead of (11) if a
modified reference signal v1' is used. The data from rereads using
modified reference signals can be compared with each other and/or the
readout data obtained using the normal reference signal. If any of the
data are different, the locations for the data are marked or flagged as
erasures for erasure decoding.

[0039] Returning again to FIG. 3, the method 300 includes decoding the
readout data, at block 310. Rereading the data using the modified
reference signal, at block 308, may provide a value that allows decoding
to succeed. If decoding is successful, the data may be output at block
306. In an alternative embodiment, if decoding is successful, the
reference signal that corresponds with the fewest errors is recorded, at
block 312, for future use. For example, the decoder may obtain the number
of errors encountered during reread and decoding, at blocks 308 and 310,
corresponding to the reference signal used. The reference signal
corresponding to the fewest errors may be saved, for example, by a system
coupled to the solid state memory device or in the solid state memory
device for future use in reading data from the marginal cell. In various
embodiments, blocks 310 and 312 are not used at all and block 314 follows
block 308.

[0040] At block 314, the method 300 includes forming one or more erasure
flags based on the readout data from block 308. The erasure flag may
indicate that at least one value of the data read from the cell is marked
for erasure. The at least one value may be, for example, a bit value of
the data read from the cell. For example, the readout data from different
rereads according to block 308 and/or the readout data obtained using the
normally used reference signal according to block 302 can be compared
with each other and differences in the data can be marked as erasure
locations for erasure decoding.

[0041] Referring briefly to FIG. 6, an example erasure flag vector 600
that may be used according to various embodiments is schematically
illustrated. The readout data denoted by D correspond with a normally
used reference signal (e.g., v1 of FIG. 5) and may be obtained from the
readout data of block 302. The readout data denoted by D' and D''
correspond with different modified reference signals (e.g., v1' and v1''
of FIG. 5) and may be obtained from the readout data of block 308, which
may iterate as denoted at block 318. The erasure flag vector 600 can be
formed using an OR of XOR(D, D') and XOR(D', DI as depicted, where the
shaded data locations indicate flagged erasures. Subject matter is not
limited to this example and an erasure flag of a bit may be set if the
bit changed during any of the reread operations at block 308 using a
variety of suitable techniques.

[0042] An alternative technique to mark erasures for multiple rereads, for
example, includes flagging for erasure a bit associated with the one or
more marginal cells if a number of times that the bit is read to have a
value favored by a majority decoding principle of the solid state memory
device is less than the number of times that the bit is read to be
another value by a threshold amount (e.g., threshold of 1), otherwise the
bit is set to have the value favored by the majority decoding principle.
Erasure flags may be set, for example, in either bit-wise or symbol-wise.

[0043] At block 316, the method 300 includes decoding the readout data
using the one or more erasure flags. If successful, the reference signal
that corresponds with the fewest errors is optionally recorded, at block
312, and the decoded data is output, at block 306.

[0044] Operations 308, 310, 314, and 316 may repeat until decoding is
successful at block 316 or a number of predetermined rereads are exceeded
at block 318. In an embodiment, the reread operation at block 308 is
performed at least twice. Such reread operation may comprise reading the
data using a modified reference signal (e.g., voltage) that is higher
than the normally used reference signal for the cell being read and
reading the data using a modified reference signal that is lower than the
normally used reference signal. Any suitable number of rereads may be
used as a threshold for block 318. If the threshold is exceeded, a
decoding failure may result at block 320.

[0045] Techniques described herein may be implemented in software,
hardware, or firmware, or combinations thereof. Operations described
herein may be performed, for example, by a decoder or signal transmitters
and/or receivers. In various embodiments, a predictor, optimizer,
analyzer, or system level manager may be used to perform actions
described herein. In various embodiments, techniques described herein are
performed by a module designed to perform such functions. As used herein,
the term module refers to an Application Specific Integrated Circuit
(ASIC), an electronic circuit, a processor (shared, dedicated, or group)
and memory that execute one or more software or firmware programs, a
combinational logic circuit, and/or other suitable components that
provide the described functionality.

[0046]FIG. 7 is a schematic diagram of an example electronic system for
implementing techniques and configurations described herein. Electronic
system 700 may comport with embodiments already described herein.
Electronic system 700 is intended to represent a variety of electronic
devices (either wired or wireless) including, for example, desktop
computer devices, laptop computer devices, personal computers (PC),
servers, telephones, personal digital assistants (PDA) including
cellular-enabled PDAs, set top boxes, pocket PCs, tablet PCs, DVD
players, video players, copiers, printers, or multi-function devices
(MFD), but is not limited to these examples and may include other
electronic devices. Alternative electronic systems may include more,
fewer and/or different components.

[0047] Electronic system 700 includes bus 705 or other communication
device or interface to communicate information, and processor 710 coupled
to bus 705 that may process information. Bus 705 may be a single system
bus or a number of buses of the same or different types bridged together.
System 700 may include one or more processors and/or co-processors.

[0048] In an embodiment, system 700 includes random access memory (RAM) or
other storage device 720 (may be referred to as "memory"), coupled to bus
705. Memory 720 may also be used to store temporary variables or other
intermediate information during execution of instructions by processor
710. Memory 720 may include a flash memory device. In an embodiment,
memory 720 comprises a solid state memory device as described herein.
Processor 710 may be coupled with memory 720 to execute instructions
stored thereon, that if executed, result in the actions or operations
described herein.

[0050] In an embodiment, an article of manufacture is disclosed. The
article of manufacture includes a storage medium such as memory 720,
static storage 730, data storage device 740, or other computer-readable
medium having instructions stored thereon that, if executed, result in
the actions described herein. The instructions may be in the form of
firmware or software according to various embodiments.

[0051] Electronic system 700 is coupled via bus 705 to display device 750,
such as a cathode ray tube (CRT) or liquid crystal display (LCD), to
display information to a user. Alphanumeric input device 760, including
alphanumeric and other keys, may be coupled to bus 705 to communicate
information and command selections to processor 710. Cursor control 770
may be another type of input device and may include, for example, a
mouse, a trackball, or cursor direction keys to communicate information
and command selections to processor 710 and to control cursor movement on
display 750.

[0052] Electronic system 700 further includes one or more network
interfaces 780 to provide access to network 720, such as a local area
network, but is not limited in this regard. Network interface 780 may
include, for example, a wireless network interface having antenna 785,
which may represent one or more antennae. Network interface 780 may also
include, for example, a wired network interface to communicate with
remote devices via network cable 787, including, for example, an Ethernet
cable, a coaxial cable, a fiber optic cable, a serial cable, or a
parallel cable.

[0053] In one embodiment, network interface 780 provides access to a local
area network, for example, by conforming to an Institute of Electrical
and Electronics Engineers (IEEE) standard such as IEEE 802.11b and/or
IEEE 802.11g standards, and/or the wireless network interface may provide
access to a personal area network, for example, by conforming to
Bluetooth standards. Other wireless network interfaces and/or protocols
can also be supported.

[0054] IEEE 802.11b corresponds to IEEE Std. 802.11b-1999 entitled "Local
and Metropolitan Area Networks, Part 11: Wireless LAN Medium Access
Control (MAC) and Physical Layer (PHY) Specifications: Higher-Speed
Physical Layer Extension in the 2.4 GHz Band," approved Sep. 16, 1999 as
well as related documents. IEEE 802.11g corresponds to IEEE Std.
802.11g-2003 entitled "Local and Metropolitan Area Networks, Part 11:
Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY)
Specifications, Amendment 4: Further Higher Rate Extension in the 2.4 GHz
Band," approved Jun. 27, 2003 as well as related documents. Bluetooth
protocols are described in "Specification of the Bluetooth System: Core,
Version 1.1," published Feb. 22, 2001 by the Bluetooth Special Interest
Group, Inc. Previous or subsequent versions of the Bluetooth standard may
also be supported.

[0055] Although certain embodiments have been illustrated and described
herein for purposes of, a wide variety of alternate and/or equivalent
embodiments or implementations calculated to achieve the same purposes
may be substituted for the embodiments illustrated and described without
departing from the scope of the present invention. This application is
intended to cover any adaptations or variations of the embodiments
discussed herein. Therefore, it is manifestly intended that embodiments
in accordance with the present invention be limited only by the claims
and the equivalents thereof.