Why one small company thinks it has the key to extending Moore’s Law

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True breakthroughs in computing don’t happen very often. When they do happen, what looks to the public like an out-of-the-blue announcement is actually the result of years or even decades of work. One company, Atomera, thinks it has developed a technology that could breathe new life into older process nodes and give customers a reason to move to newer, faster, processes — and there’s no reason its technology couldn’t be extended to boost newer chips as well.

Heading up this effort to extend Moore’s Law is Robert Mears, one of the inventors of Erbium Doped Fiber Amplifier (EDFA), a critical method of amplifying optical signals in fiber optic arrays without first converting those signals back into electricity. Atomera’s invention, if successful, could significantly impact the future of computing by offering real improvements to various manufacturers without requiring them to move to smaller process nodes.

Why process nodes stick around

One of the major differences between the various merchant foundries (GlobalFoundries, TSMC, Samsung, SMIC, UMC) and Intel is the process nodes they focus on. Intel has a fast-moving model that emphasizes moving to new nodes fairly quickly. It depends on the latest nodes for the bulk of its revenue, and it transitions older plants to newer nodes on a fairly regular basis. This model has taken a beating over the last few years, due to 14nm difficulties and the cancellation of 450mm wafers, but it’s still the basic way that Intel does business. TSMC and its merchant foundry competitors, however, tend to derive significant amounts of revenue from older hardware.

TSMC’s revenue by process node, Q1 2015

Keep in mind that this image is from Q1 2015, when 20nm was TSMC’s leading-edge node. What it shows is that 39% of TSMC’s revenue is derived from process nodes that the company debuted 10 or more years ago (the foundry’s 65nm semiconductor technology entered bulk production in 2006). If you include 40/45nm, which launched eight years ago, that figure rises to 54%. When merchant foundries refer to long versus short nodes today, what they’re referring to is a belief that certain nodes, like 28nm, will continue to be important for years to come.

There are multiple reasons why companies settle on a specific process node. The benefits of smaller processes tend to be specific to certain kinds of processors. We normally talk about chips built on conventional CMOS, but there are other types of manufacturing — analog, MEMS, and RF, to name a few. Even devices built on CMOS may not benefit from smaller nodes if, for example, they have a minimum pad size that a smaller node can’t shrink.

Alternatively, even a conventional CMOS design may not benefit from a die shrink if the current product doesn’t generate enough revenue to pay for the new design effort, or if the existing hardware is perceived as capable of meeting existing needs. IoT devices don’t necessarily need to be built on cutting-edge silicon nodes, particularly if the hardware in question is selling for $50 or less. These companies would benefit from better silicon technology, but they may not be able to justify moving to a new node to get it. That’s where Atomera’s new technology could come in handy.

How Atomera’s technology works

Atomera’s Mears Silicon Technology (MST) works by inserting a layer of oxygen in between the silicon lattice as the latter forms. Call it “squeezed silicon” (that’s our name, not theirs) as opposed to the well-known “strained silicon” technique for improving silicon’s performance. Mears claims this lowers leakage and improves drive current, while simultaneously improving electron hole mobility. The total gains are estimated to be equivalent to a a half-node to full-node die shrink depending on the characteristics of the chip. The technology has been in development for over a decade, which is actually pretty normal in semiconductor manufacturing.

We’ve seen some evidence that semiconductor companies are looking for ways to improve existing nodes rather than simply chasing after new ones. TSMC rolled out a new 28nm offering, 28HPC+, starting in 2015 — more than three years after its 28nm node had entered volume production. The explicit goal of 28HPC+ was to offer significant improvements compared with TSMC’s older 28nm nodes (HP, LP, HPL, HPM) without requiring a die shrink. When Samsung began building 3D NAND, it announced that it would use an older 40nm process for at least the first few iterations of the product. The idea of improving nodes or taking advantage of older nodes isn’t something unique to Atomera.

We spoke to Atomera and confirmed that the company is ready to move beyond developing its technology and expects to announce some significant customers in the not-too-distant future. The company claims it can offer performance improvements equal to those that might be achieved by adopting III-V semiconductors or moving to sub-10nm nodes, at a fraction of the cost — but only if major fabs sign on. To date, none appear to have done so (EETimes notes that Atomera has won some legacy fabs, but doesn’t state which they are).

Right now, the semiconductor industry is trying to figure out which technologies will shape the future of next-generation nodes. If Atomera can demonstrate that its technology works on older products, it’ll have a much stronger opportunity to sell into major silicon designs in the future. If EUV doesn’t come online in the next few years, TSMC, GloFo, Samsung, and even Intel may all be hungry for a technology that lets them deliver a node worth of scaling without incurring massive additional design costs. Atomera still has to demonstrate that it represents a viable route forward — but design firms and companies across the silicon industry are looking for technology that would help them deliver new improvements without breaking the bank.

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“If EUV doesn’t come online in the next few years, TSMC, GloFo, Samsung, and even Intel may all be hungry for a technology that lets them deliver a node worth of scaling without incurring massive additional design costs.”

Considering how long EUV has been delayed, I have almost no doubt this technology will have ample time to make its case. Not to mention, even if by some miracle EUV finally becomes reality, if the tech makes a good case with legacy products, surely it can add additional value at even EUV nodes.

Joel Hruska

The inefficiencies in current EUV are frankly astounding. Existing infrastructure is perhaps 10% power efficient (meaning you draw 10x more power at the wall than you emit in your lithography laser). EUV is said to be roughly 1% efficient, and the cooling requirements for EUV hardware require vastly more liquid than their equivalents.

Given that it still looks as if *some* progress is being made, I can’t say it just won’t happen, but boy, it’s not looking great.

witeken

About the title: If a small company could extend Moore’s Law, anyone could do it :). Which is of course not what we see.
And EUV is now being forecasted by ASML for a 2018-2019 introduction, and from buying to production could take maybe a year, so at 2020 at the last, we should see EUV in volume production. “Should”.
See ASML’s last earnings call from Q3.
And of course EUV draws a lot of power: you need mirrors to reflect the light to focus it on the wafer, ’cause you can’t use lenses. So you lose about 0.7x or so of your power per mirror, and there are more than 10 mirrors or so.

Joel Hruska

Intel is now on a roughly three-year process cycle. That suggests 10nm next year and 7nm in 2020. They’ve already said they aren’t using EUV at 7nm, which makes 2023 the most likely introduction date.

One of the merchant foundries — I forget if it’s TSMC or Samsung — implied they might try to adopt EUV earlier than their competitors. But I still don’t expect to see it until 2020 at-best. Given that EUV has literally been delayed about 12 years at this point (Christopher Mack put together a presentation on this) I don’t expect anyone to make their timelines.

witeken

They have not said that. It all depends on the maturity of the tool. Intel probably still uses SADP at 10nm to get a metal pitch of perhaps 36-40nm, which is at SADP’s theoretical limit. With SAQP, they can go down to 20nm metal pitch, so that would be the 5nm node. As soon as it makes economic sense, they will switch.
So it’s ASML’s task to make sure all the R&D they’re spending pays off and they can start selling those 100M EUV tools.
But I repeat: just read their most recent earnings call on Seeking Alpha. 12 tools they project in 2017, 24 in 2018 and a production of 48 in 2019. I trust ASML more than your words on this one, sorry.
And why wouldn’t Intel insert EUV midnode?

EUV is not in its baby stage anymore. Of course I don’t expect ASML to meet their doubling projections, but it’s long not just a project on paper anymore. And AFAIK, Intel’s roadmap in 2002 or so was to inject EUV at 32mn.

MissionPeak88_7456

EUV tool shipment projections are unreliable and over-hyped. Historically, projections for shipments have been overoptimistic; they only look real on paper. Industry analysts as of 2002 were projecting (wrongly, as it turned out) that EUV would be used for volume production in 2007.

Your trust may be misplaced for two reasons. Firstly, consider that the top slide of every earnings call has a safe harbor disclaimer, which rightly warns that forecasts should be taken with a grain of salt. Secondly, the earnings call of late 2013 on Seeking Alpha projected 12–15 shipments the following year in 2014, 20-ish shipments in 2015 and 50–60 shipments in 2016. However, three tools were actually shipped in 2013, four in 2014, four in 2015 and four (three shipped and one more forecast later this year) in 2016. Earlier this year, they were projecting six or seven shipments in 2016.

Patrick Proctor

Intel has said it hopes to use EUV at 7nm, but that it can squeeze if it’s not available.

CrazyElf

Seems to me to be worth attempting. Whether or not it will work is another matter entirely. These things tend to be very hard to know for sure until they are actually attempted.

In regards to EUV, we still don’t know if it will even happen at this point. This may be our only way forward.

In my personal opinion (and I’m by no means a person that knows for sure either), a Molybdenum disulfide Van der Waals type transistor seems like the way to go. It would represent a modest performance improvement and offer the potential for power savings. Perhaps something like this with graphene might be “it”:

Of course, this is going to be decades before we see this in your desktop any time soon unfortunately.

Joel, do you think EUV won’t happen at this point? I know ASML has slipped several times now behind schedule. So does that mean that neither 450mm wafers nor EUV is happening?

Joel Hruska

Everyone keeps saying EUV is happening, and the tech has shown slow evolution, despite missing pretty much all the introduction points.

It used to look like future nodes would move too quickly for EUV to catch up, but node progression has slowed markedly and that, in turn, may open a window for EUV. But if Intel now takes ~3 years per node introduction, and they’ve already said EUV won’t be ready for 7nm, that implies we’re at least 7 years from EUV (2017 for 10nm, 2020 for 7nm, and 2023 for 5nm, when EUV will presumably be ready).

MissionPeak88_7456

Best-case forecasts see 450mm wafers entering production in 2020–2025, while others are less optimistic. ASML paused development of 450mm tools in 2013, and they cited uncertain timing of chipmaker demand.

Mat

Looks a lot like FD-SOI and especially SuVolta in what it is supposed to accomplish.

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