Originally posted by Thor66
According to Borbely, the SRC4392 can interpolate without introducing ringing. But SRCs are accused of converting jitter into data and thus often having a signature of their own. Can anyone confirm this ?

How about using an SRC solely for interpolation and feeding it from a low jitter source ?

Looks like they have builtin zero order hold function in cpld before the ASRC to emulate the NOS thing, so it becomes a NOS alike / interpolation hybrid , with the same NOS artifacts as ever , and because of the SRC4392's own filter is set to work at very high frequencies ( up to 192 khz) its not really hurting the squarewave anymore, while they also gain the jitter discarding properties of the SRC . Interesting stuff...
You can check 96-> 44.1 ringing artifacts here: http://src.infinitewave.ca/ , you see a few started to avoid preringing at the cost of "insane " phase shift.

How about using an SRC solely for interpolation and feeding it from a low jitter source ?

the no ringing property of the aforementioned circuit comes from the digital domain zero order hold function, eg. double, quadruple insertion of same successive samples. In a quadruple case its like incoming 44.1 - ZOH -> 176.4 -> ASRC -> ~210 khz and jitter discarded entirely. It must be better than your average NOS

That would increase resolution, reduce glitch energy, and also mostly avoid the MSB transition at bipolar zero.

Full scale currents would need to be matched closely.
A digital servo implemented to avoid drifting of the data too much away from BPZ.
A prozessor to calculate the data values.
And perhaps to make a decision which chip needs to be updated so that all codes stay as close to BPZ or a small value above or below BPZ.
In the example that would be chip 4 with a new value of 4µA.