Memory system and computer system
A memory system according to the present invention includes, in addition to an computing device, a plurality of first blocks that are provided to store information including user information, and...

Data transmission method
A method of transmitting data between a plurality of inter-connected elements. The method comprises receiving a message from a first element, said message comprising a routing key plus optionally...

Lookup table addressing system and method
Lookup table addressing of a set of lookup tables in an external memory is achieved by: transferring a data word from a compute unit to an input register in a data address generator; providing in...

Image forming apparatus
An image forming apparatus includes a memory that stores therein a control program, a central processing unit that executes the control program stored in the memory, a print engine controlled by...

Direct memory access with striding across memory
A DMA device may include an offset determination unit configured to determine a first offset for a DMA transfer and a data transfer unit. The data transfer unit may be configured to receive a...

Data prefetcher
In an embodiment, a processor includes a data cache and a prefetch unit coupled to the data cache. The prefetch unit is configured to detect one or more prefetch streams corresponding to load...

Arbitrary precision floating number processing
Techniques for providing arbitrary precision floating number (APFN) processing are disclosed. In some aspects, an APFN store may be used to store a large number (i.e., an APFN) having many...

Memory mapped register file
A method and apparatus for operating a memory mapped register file. The method includes: receiving a source index input having a length of T−1 bits, the source index input identifying one of a...

Optimization of ROM structure by splitting
A method for designing a read-only memory (ROM), and related device, includes partitioning a dataset into two or more sub-datasets that each have the same address space, but are of a smaller...

Safe and efficient allocation of memory
Aspects of the present invention are directed at centrally managing the allocation of memory to executable images in a way that inhibits malware from identifying the location of the executable...

84

8019969

Self prefetching L3/L4 cache mechanism
Embodiments of the invention provide a look-aside-look-aside buffer (LLB) configured to retain a portion of the real addresses in a translation look-aside (TLB) buffer to allow prefetching of data...

85

8019964

Dynamic address translation with DAT protection
What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of any one of a region first table, a...

Enhanced microprocessor or microcontroller
An n-bit microprocessor device has an n-bit central processing unit (CPU); a plurality of special function registers and general purpose registers which are memory-mapped to a plurality of banks,...

93

7996620

High performance pseudo dynamic 36 bit compare
A cache memory high performance pseudo dynamic address compare path divides the address into two or more address segments. Each segment is separately compared in a comparator comprised of static...

Method for read-only memory devices
A ROM comprises several bit output lines and X address decode lines, and stores a data set. Each address decode line stores a unique data word. Addresses in the data set that have the same data...

Memory system, computer system and memory
The correspondence between logical addresses and physical addresses is determined so that the logical addresses in ascending order may be assigned to the physical addresses in ascending order with...

99

7941595

Methods and systems for a memory section
A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, and a section...