Model-based design brings the promise for an increase in productivity and correctness in the development of complex embedded software. The use of a formal model of computation allows, in principle, for automated support in the verification, simulation and testing of functional and non-functional properties. Automatic generation of a programming code implementation of the model is also a very common asset of modern tools. Unfortunately, despite all research and industrial efforts, a language (or a design methodology) that can provide verification of both functional and time without incurring in excessive inefficiencies (at verification or implementation time) is not available and separation of concerns is the solution advocated by many. Most research and commercial languages and tools focus on providing support for the design and validation of functional properties. At a different level, models and theory have been developed for supporting the description of the threads and resources composing the software architecture, and schedulability analysis provides support for the validation of timing constraints. However, the design of the concurrent structure of the application is still done manually. The system designer has to decide the number of threads, their structure and interactions, without the possibility of evaluating the trade-off between different solutions. This paper presents a solution towards what we believe to be a key objective: the synthesis of the architecturelevel design and the automated logical-to-architectural mapping. Our proposal tries to reduce the overheads and excessive priority inversions of existing solutions that map all functional blocks (or reactions) into a single thread or assign a thread of execution to each action or possibly to each active object. After presenting our algorithm, we compare it with existing solutions and provide a schedulability analysis of the resulting system.