ARRANGEMENT FOR DETECTING THE CHANGE IN A RELATIVE POSITION OF TWO PARTS IN RELATION TO ONE ANOTHER - There is described an arrangement for detecting a change in a position between two parts which can be displaced in relation to one another. The arrangement has at least one electromechanical registering device having a monitoring chamber, which is shielded from manipulations taking effect from the outside, a number of monitoring bodies in the monitoring chamber, the number comprising at least two components and these components differing from one another in terms of a physical parameter, motion transfer means, which, in the event of the change in the positioning being returned to an initial state, cause the monitoring bodies to be moved from a first monitoring arrangement into a second monitoring arrangement. A sensor device has sensors which generate a sensor signal corresponding to the physical parameter of a monitoring body associated with each sensor in the first and second monitoring arrangement, and each sensor signal is fed to an evaluation unit.

ANGLE SENSOR - An angle sensor measures a rotated angle and the angular velocity of a rotary disc by sensing the magnetic field generated by a number of electromagnetic elements disposed on the rotary disc. The precision of the angle sensor is adjusted by selectively magnetizing the electromagnetic elements.

2010-04-29

20100102801

ROTATION SENSOR - A rotation detecting sensor, having excellent sealing capability to prevent water ingress from outside, being so robust that no damage occur in sensor component parts and circuits due to external force and/or thermal strains resulting from self-heating or change in ambient temperature, and inexpensive to manufacture, is provided. The rotation detecting sensor is fixed to a sensor fixing member to be fitted to a wheel support bearing assembly. A sensor unit, including a magnetic sensor element, a cable and a substrate, is fixed to the sensor fixing member through the substrate. A molding segment molded of a molding material bonded with the substrate is provided around the sensor unit. The substrate has a metallic pattern portion formed as a metallic coating on a substrate surface in the vicinity of an electroconductive pattern portion and the molding material is bonded to the metallic pattern portion.

2010-04-29

20100102802

MINIATURE ROTARY ENCODER - A small rotary encoder capable of easily fitting a substrate into a proper position without using an adhesive or the like is provided. Slits are formed in an encoder case so that the encoder case is partially plate-spring shaped, a step portion and a claw portion are formed on the inner circumference of the encoder case, convex portions and concave portions that are combined with each other are formed on the inner circumference of the encoder case and a substrate, respectively. When the substrate is inserted into the encoder case, the encoder case is bent by the slits so that the substrate can be inserted into the encoder case. The substrate is inserted between the step portion and the claw portion, so that the substrate can be fitted into the encoder case, and the substrate is prevented from being incorrectly fitted in a circumferential direction, so that a position can be easily determined.

2010-04-29

20100102803

INDUCTION DETECTING ROTARY ENCODER - An induction detecting rotary encoder has first to third transmitting windings, first to third receiving windings, and first to third flux coupling winding. The first transmitting winding, the first receiving winding, and the first flux coupling body constitute a first angle detection track generating a cyclic change for N

2010-04-29

20100102804

Position/displacement measuring system with an encoded scale body - Position/displacement measuring system, comprising a sensor head and an encoded scale body, the scale body extending in a first direction and in a second direction lying transversely to the first direction, and the scale body having a region for incremental position determination with an encoding in the first direction and a region for absolute position determination with an encoding in the second direction, the sensor head having a first sensor device with a sensor resolution parallel to the first direction, which is associated with the region for incremental position determination, and the sensor head having a second sensor device with a sensor resolution in a second direction, which is associated with the region for absolute position determination.

2010-04-29

20100102805

METHOD AND ARRANGEMENT FOR INFLUENCING AND/OR DETECTING MAGNETIC PARTICLES IN A REGION OF ACTION - A method and an arrangement for influencing and/or detecting magnetic particles in a region of action is disclosed, which method comprises the steps of: —generating a magnetic selection field having a pattern in space of its magnetic field strength such that a first sub-zone having a low magnetic field strength and a second sub-zone having a higher magnetic field strength are formed in the region of action—changing the position in space of the two sub-zones in the region of action by means of a magnetic drive field so that the magnetization of the magnetic particles change locally, —acquiring signals, which signals depend on the magnetization in the region of action, which magnetization is influenced by the change in the position in space of the first and second sub-zone, wherein a magnetic drive vector of the magnetic drive field is rotated in at least one rotation plane.

2010-04-29

20100102806

ARRANGEMENT AND METHOD FOR INFLUENCING AND/OR DETECTING MAGNETIC PARTICLES IN A REGION OF ACTION - An arrangement for influencing and/or detecting magnetic particles, a method for adjusting such an arrangement and a method for influencing and/or detecting magnetic particles in a region of action is disclosed, which arrangement comprises selection means for generating a magnetic selection field having a pattern in space of its magnetic field strength such that a first sub-zone having a low magnetic field strength and a second sub-zone having a higher magnetic field strength are formed in the region of action, drive means for changing the position in space of the two sub-zones in the region of action by means of a magnetic drive field so that the magnetization of the magnetic particles changes locally, receiving means for acquiring signals, which signals depend on the magnetization in the region of action, which magnetization is influenced by the change in the position in space of the first and second sub-zone, wherein the receiving means comprises a first compensation means and a second compensation means the first and second compensation means comprising each a compensation coil.

2010-04-29

20100102807

WIRE ROPE FLAW DETECTOR - A wire rope flaw detector comprises a back yoke and excitation permanent magnets, which form a main magnetic path in a predetermined section of a wire rope in the axial direction; a magnetic path member arranged in the predetermined section to be magnetically insulated from the back yoke and the permanent magnets and making the leakage flux generated from a damaged part of wire rope detour to the outside of the wire rope; and a detection coil wound around the magnetic path member for detecting leakage flux. The amount of leakage flux can be increased by providing the magnetic path member and since the windable area of the detection coil is increased, the number of turns of detection coil can be increased.

2010-04-29

20100102808

METHOD AND APPARATUS FOR NON-DESTRUCTIVE TESTING - A method and apparatus in which at least two different test phases are performed on a test object, selected from: conventional eddy current testing, partial saturation eddy current testing, and ultrasonic testing. Measurement data sets are obtained from the at least two different test phases, with each measurement data set comprising measurement data corresponding to a plurality of test positions. The data sets are combined in a data processing means and the combined measurement data is processed to evaluate a damage condition of the test object. In a preferred embodiment, all of conventional eddy current testing, partial saturation eddy current testing, and ultrasonic testing are performed. The apparatus may be provided in two or more sub-assemblies, of which one may be an internal test tool and one may be an external tool. Alternatively, the apparatus may be capable of carrying out all three of the test phases.

2010-04-29

20100102809

DIFFERENTIAL GRADIOMETRIC MAGNETOMETER, SYSTEM AND METHOD OF USE - A three-dimensional real-time differential gradiometric magnetometer (DGM) array, system and method of use. The DGM exploits differential and gradiometric parametrics of an induced magnetic field anomaly surrounding an object interacting with an applied magnetic field. The DGM integrates differential magnetic field measurement with gradiometric magnetic field measurement into a single system. The DGM detects, locates and maps objects, while simultaneously measuring the distance between the DGM detection array and the object, axial orientation, apparent magnetic mass and magnetic moment. The DGM employs a signal processing technique to nullify source noise from the earth's magnetic field, external radio frequency transmissions and electromagnetic noise. A linear geometric architecture comprising a plurality of magnetometers forming the array enables the DGM to collect information directly in the spatial domain. The DGM is capable of capturing the complete field anomaly contour in three dimensions while the array traverses over, under or adjacent to an object.

2010-04-29

20100102810

MONITORING OF CONVEYOR BELTS - A system for monitoring the condition of a conveyor belt having magnetically permeable cords, has a magnetic field generator for generating a magnetic field to magnetize the cords, in use, a magnetic field sensing unit for sensing the magnetic field provided, in use, by the cords, the sensing unit comprising an array of spaced magnetic field sensors, the spacing of the sensors being sufficiently close to discriminate between adjacent cords. The spacing of the sensors depends on the spacing of the cords, and may be less than half the spacing between cords of a conveyor belt. The sensors may be direction sensitive and the sensors may be oriented in more than one direction, to sense the perpendicular and other components of the magnetic field.

2010-04-29

20100102811

NMR, MRI, and Spectroscopic MRI in Inhomogeneous Fields - A method for locally creating effectively homogeneous or “clean” magnetic field gradients (of high uniformity) for imaging (with NMR, MRI, or spectroscopic MRI) both in in-situ and ex-situ systems with high degrees of inhomogeneous field strength. The method of imaging comprises: a) providing a functional approximation of an inhomogeneous static magnetic field strength B

2010-04-29

20100102812

OPTIMIZED SPECTRAL-SPATIAL PULSE - A computer implemented method for designing a spectral-spatial pulse for exciting at least one passband and minimally exciting at least one stopband is provided. A uniform shaped spectral envelope is generated. For a plurality of k

MAGNETIC RESONANCE IMAGING APPARATUS - A Magnetic Resonance Imaging apparatus having an open U- or C-shaped magnet structure, wherein the magnet structure has at least one vertical connection member for joining two horizontal wall members which lie one above the other and are supported in a cantilever fashion and in a predetermined spaced relationship by the vertical member, the vertical member being eccentrically connected to the two wall members at a side edge thereof. The horizontal wall members and the vertical member delimit the upper and lower sides and at least a vertical lateral band of a space for receiving at least one part of a patient body. The horizontal wall members also support means for generating a static magnetic field that permeates the patient receiving space. The apparatus further includes a patient table, supported in an intermediate position between the two horizontal wall members, and lies slightly above the lower horizontal wall part, the table being displaceable in at least one displacement direction, having at least one component of motion towards and/or away from the vertical connection member, and the table being rotatable about a vertical axis outside the magnet structure, i.e. outside the horizontal wall members.

2010-04-29

20100102815

DYNAMIC COMPOSITE GRADIENT SYSTEMS FOR MRI - A composite gradient system is described, including a body gradient system and an insert gradient system, in which the body gradient system and the insert gradient system can be driven independently and simultaneously. The composite gradient system can provide an operator with the flexibility of imaging a subject using the body gradient system alone, the insert gradient system alone, or both gradient systems simultaneously, and therefore enjoy the advantages of each gradient system. In some embodiments, the body gradient system and the insert gradient system may be driven concurrently during an imaging sequence to produce composite magnetic field gradients having high amplitude and/or fast slew rate, resulting in high image resolution and/or fast image acquisition. In some embodiments, a subject may be imaged using the body gradient system alone while leaving the insert gradient system in place.

2010-04-29

20100102816

EDDY-CURRENT ARTIFACT REDUCTION IN BALANCED STEADY-STATE FREE PRECESSION MAGNETIC RESONANCE IMAGING - Magnetic resonance imaging techniques are described that utilize bSSFP sequences in which two or more gradient waveforms are interleaved in a “groupwise” fashion, i.e., each waveform is executed consecutively two or more times before switching to the other waveform, where “N” counts the number of times each waveform is executed consecutively. As a result, embodiments of the present disclosure can mitigate steady-state signal distortions or artifacts in interleaved balanced steady-state free precession (bSSFP) caused by slightly unbalanced eddy-current fields. Related MRI systems are also described.

2010-04-29

20100102817

HYBRID BIRDCAGE-TEM RADIO FREQUENCY (RF) COIL FOR MULTINUCLEAR MRI/MRS - A radio frequency (RF) coil for a magnetic resonance imaging system includes a plurality of rungs disposed around a volume and a first end ring connected to a first end of the plurality of rungs. The first end ring has a first plurality of birdcage mode tuning capacitors and a first plurality of RF traps. The RF coil also includes a second end ring connected to a second end of the plurality of rungs. The second end ring has a second plurality of birdcage mode tuning capacitors and a second plurality of RF traps. An RF shield is disposed around the plurality of rungs, the first end ring and the second end ring. The RF coil also includes a plurality of transverse electromagnetic (TEM) mode tuning capacitors, where each TEM mode tuning capacitor coupled to one of the plurality of rungs. An RF trap is connected to each of the plurality of TEM mode tuning capacitors.

2010-04-29

20100102818

MULTI-PURPOSE VALVE FOR CRYOGEN GAS EGRESS - A valve for controlling cryogen egress from a cryogen vessel has a housing having a low pressure side and a high pressure side with a fluid path defined between. A valve element is interposed between the low pressure side and the high pressure side of the housing. A mechanism is provided for holding the valve element against a valve seat. The mechanism has a cam shaft that is rotatable to displace the valve element from its seat to open the fluid path.

2010-04-29

20100102819

Sense Shimming (SSH): a fast approach for determining B0 field inhomogeneities using sensitivity encoding - The pursuit for ever higher field strengths and faster data acquisitions has led to the construction of coil arrays with high numbers of elements. With the SENSE technique it has been shown, how the sensitivity of those elements can be used for spatial image encoding. A method in accordance with the present invention, largely abstains from using encoding gradients. The resulting sensitivity encoded free induction decay (FID) data is then not used for imaging, but for determining field inhomogeneity distribution. The method has therefore been termed SSH for Sense SHimming.

2010-04-29

20100102820

Method for determining electromagnetic survey sensor orientation - A method for determining orientation of an electromagnetic survey sensor includes deploying the sensor at a selected position on the bottom of a body of water. An electromagnetic field is generated at a selected position in the body of water. A portion of the electromagnetic field is detected along at least two orthogonal directions at the sensor. A portion of the detected electromagnetic field is selected as having traveled only in a vertical plane which includes both source position and sensor position. The polarization direction of the selected portion of the electromagnetic field is determined from the selected portion. The determined polarization direction is used to determine the sensor orientation.

2010-04-29

20100102821

SURVEYING METHOD USING AN ARRANGEMENT OF PLURAL SIGNAL SOURCES - A survey technique for use in a marine environment to survey a subterranean structure includes providing an arrangement of plural signal sources in a body of water to produce corresponding signals. The signals of the signal sources in the arrangement are set to cause reduction of at least one predetermined signal component in data received by a receiver in response to the signals.

2010-04-29

20100102822

PROCESS AND DEVICE FOR MEASUREMENT OF SPECTRAL INDUCED POLARIZATION RESPONSE USING PSEUDO RANDOM BINARY SEQUENCE (PRBS) CURRENT SOURCE - A process and device for measurement of spectral induced polarization response of subsurface over a wide band of frequencies (0.03 Hz to 100 Hz) using pseudo noise current source, is provided. (Pseudo Random Binary Sequence current source). The measurement setup employs a current source (500 VA) and a computer controlled real time correlator for excitation of the subsurface. The current from the source is reversed through the grounded electrodes in a Pseudo Random Binary Sequence (PRBS) and the computer based receiver essentially computes Auto (input-input) and Cross (input-output) correlation estimates in the field. The collected data (time series) is transformed into frequency domain (DFT) in order to obtain the phase spectrum. The receiver has a provision to stack data for an improved S/N ratio. Measurements taken in laboratory using simple RC network, which simulates the subsurface, are accurate. Accuracy of measurement is better than 2% in Band-I (0.031-2 Hz) and 1% in Band-II (2-100 Hz) respectively.

ELECTRICAL NETWORK FAULT LOCATION BY DISTRIBUTED VOLTAGE MEASUREMENTS - A method of locating a fault on an electrical network energized by a source uses a form of triangulation of voltage measurements at least three different locations on the network, with at least one of the locations situated upstream from the fault with respect to the source. Voltage phasors corresponding to the voltages measured during the fault are time synchronized. Conductors of the network involved in the fault are determined as a function of characteristics of the voltage phasors and a fault current causing a voltage drop at one of the locations with respect to an initial voltage value is evaluated. A position of the fault is evaluated at a point of the network where a ratio between a difference of the voltages measured at two of the locations and an impedance between one of the two locations and the point is equal to the fault current.

2010-04-29

20100102825

Spectral and information theoretic method of test point, partial-scan, and full-scan flip-flop insertion to improve integrated circuit testability - Design for testability (DFT) algorithms, which use both gradient descent and linear programming (LP) algorithms to insert test points (TPs) and/or scanned flip-flops (SFFs) into large circuits to make them testable are described. Scanning of either all flip-flops or a subset of flip-flops is supported. The algorithms measure testability using probabilities computed from logic simulation, Shannon's entropy measure (from information theory), and spectral analysis of the circuit in the frequency domain. The DFT hardware inserter methods uses toggling rates of the flip-flops (analyzed using digital signal processing (DSP) methods) and Shannon entropy measures of flip-flops to select flip-flops for scan. The optimal insertion of the DFT hardware reduces the amount of DFT hardware, since the gradient descent and linear program optimizations trade off inserting a TP versus inserting an SFF. The linear programs find the optimal solution to the optimization, and the entropy measures are used to maximize information flow through the circuit-under-test (CUT). The methods limit the amount of additional circuit hardware for test points and scan flip-flops.

2010-04-29

20100102826

POWER SUPPLY MONITORING SYSTEM - A method for detecting predetermined fault conditions associated with the supply of AC electrical power to a consumer, the supply having an active conductor and a neutral conductor with the neutral conductor being connected to earth. The method comprises providing a first current detector associated with the active conductor, providing a second current detector associated with the neutral conductor; providing a voltage detector to detect voltage between the active conductor and the neutral conductor, and checking a current ratio of neutral current to active current whereby the current ratio is indicative of a predetermined fault condition. Also disclosed is a method of checking the condition of supply line active and neutral conductors in a consumer's supplied premises including determining the impedance of the active conductor and the impedance of the neutral conductor to indicate the condition of each of the active and neutral conductors.

2010-04-29

20100102827

ROTATION ANGLE SENSOR OR LENGTH SENSOR - A rotation angle sensor with two or more oscillators which comprises, in each case, striplines fixed on a dielectric support, as sensor elements, such that the oscillators are arrayed in a curve, for angle measurement, or they are arrayed in a straight line, for position measurement. One or more actuating elements, for example eddy-current actuating elements, are passed over the curve or the line to cause relative movement. The striplines are shaped so that the one or more actuating elements (B

2010-04-29

20100102828

SYSTEM AND METHOD FOR MEASURING RETENTATE IN FILTERS - A system and method for determining loading of a filter having a first dielectric constant with a material having a different dielectric constant, is disclosed. The filter is contained within a metallic container forming a microwave cavity, and microwave or RF energy is created within the cavity and changes in the cavity microwave response are monitored. The changes in cavity microwave response are related to filter loading. In a preferred embodiment, the microwave energy includes multiple cavity modes thereby allowing determination of spatial distribution of the contaminant material loading. In one embodiment, the microwave cavity response includes a shift in frequency of a resonant mode. Alternatively, the microwave cavity response includes a shift in quality factor Q of a resonant mode. The microwave cavity response may include a shift in amplitude or peak width of the microwave's signal at resonance.

2010-04-29

20100102829

Vector Network Analyzer (VNA) on a Chip - A front end of a vector network analyzer (VNA) on an integrated circuit includes a clock generator and two ports. The VNA couples to a device under test (DUT) using the two ports. Each port may include a plurality of receivers and a VSWR bridge, and can be configured as either an input or an output. The clock generator can generate a stimulus signal, an in-phase I clock signal, and a quadrature-phase Q clock signal. The output port provides the stimulus signal to the DUT and measures both reference and reflected power from the DUT, such as by utilizing two receivers by using direct conversion and the I and Q clock signals. The input port measures transmitted power through the DUT using a second VSWR bridge and one of its receivers by using direct conversion along with the I and Q clock signals. The VNA IC can provide S-parameter measurements to a processing unit for further processing and/or analysis to compute the DUT S-parameters.

2010-04-29

20100102830

Physical Force Capacitive Touch Sensor - A physical force capacitive touch sensor comprises a capacitive sensor element on a substrate, a physically deformable electrically insulating spacer over the capacitive sensor element, and a conductive plane over the physically deformable electrically insulating spacer that is substantially parallel to the capacitive sensor element. The conductive plane is connected to a power supply common and/or grounded to form a capacitor with the capacitive sensor element and for improved shielding of the capacitive sensor element from electrostatic disturbances and false triggering thereof. A protective cover may be placed over the conductive plane to act as an environmental seal for improved physical and weather protection, but is not essential to operation of the capacitive touch sensor.

2010-04-29

20100102831

Capacitance Measurement Circuit and Capacitance Measurement Method Thereof - A capacitance measurement circuit and a capacitance measurement method thereof. The capacitance measurement circuit for measuring a capacitor under test includes a capacitance to time unit, a continuous time integrator and an analog to digital converter. The capacitance to time unit generates a first clock signal and a second clock signal reverse to the first clock signal according to a first charge time of the capacitor under test and a second charge time of a variable capacitor. The continuous time integrator receives the first clock signal and outputs an integral signal according to the first clock signal. When the number of clocks of the second clock signal is equal to a default value, the analog to digital converter outputs a digital signal corresponding to a capacitance difference between the capacitor under test and the variable capacitor according to the integral signal.

2010-04-29

20100102832

Automated Capacitive Touch Scan - A scan module of an electronic device scans a capacitive keypad for detection of the actuation of any capacitive touch sensor. This scan module remains in operation even when major power consuming circuits of the electronic device are in a sleep mode, and will not wake up the major power consuming circuits until an action requiring the circuits is needed, thereby, reducing overall power consumption of the electronic device while still maintaining scanning of the capacitive keypad. Upon detection of a valid key press of a capacitive touch sensor, an interrupt to the electronic device brings it out of a sleep mode and into an operating mode for further processing and appropriate action commensurate with the actuation of the specific capacitive touch sensor.

2010-04-29

20100102833

SITTING DETECTION SYSTEM - A sitting detection system determines whether an occupant is seated in a vehicle seat or not by applying a DC voltage to a sheet-like detection electrode that is provided in the seat, and measuring the time for capacitance between the detection electrode and a ground to be charged to a predetermined level using simple implement. The use of the conductive woven cloth, which is formed with the surface member of the seat, as the detection electrode enables not to degrade the texture of the seat. The threshold time for detecting whether an occupant is seated in a seat or not may be set using a charging time which is measured when no occupant is seated in the seat as the initial value.

2010-04-29

20100102834

Sensor switch for sensing human body contact - This invention is a sensor switch capable of sensing the contact by human body, comprising a contact conductor, issuing a signal once a human body touches it; a frequency generator, for the receiving of the signal issued by the contact conductor, converting the signal into a preset frequency to output; and a detecting circuit, for the receiving of the signal issued by the frequency generator, determining if the output frequency of the frequency generator is changed and issuing an electric signal subject to the frequency that is detected. Accordingly, once a human body gets in contact with the contact conductor, the detecting circuit will issue an electric signal to form a sensor switch.

2010-04-29

20100102835

METHOD AND SYSTEM FOR DETECTING A CORROSIVE DEPOSIT IN A COMPRESSOR - An embodiment of the present invention may analyze, in or near real time, a sample of effluent exiting a compressor after an offline water-wash cycle. The results of the analysis may determine the level of fouling or level of corrosive deposits on the compressor. An embodiment of the present invention may allow for a control system to receive the analysis and determine whether an additional offline water-wash cycle should be performed to reduce the level of fouling or level of at least one corrosive deposits. An embodiment of the present invention may link the control system with a remote monitoring and diagnostics center for further review of the effluent and the compressor fouling. An embodiment of the present invention may link to a mitigation process, such as, but not limiting of, an on-line water wash system, if required.

2010-04-29

20100102836

APPARATUS AND METHOD FOR COMPENSATING FOR VOLTAGE DROP IN PORTABLE TERMINAL - An apparatus and method for determining a status of a power unit in a portable terminal are provided. The apparatus includes a power unit for supplying power to a internal circuit, a resistor located between the power unit and the internal circuit, and a voltage determination unit for determining an amount of a current consumption by the internal circuit by considering a difference between a first voltage between the power unit and the resistor and a second voltage between the resistor and the internal circuit, and for determining status information of the power unit by compensating for a voltage drop of the first voltage in accordance with the amount of the current consumption

2010-04-29

20100102837

CONNECTION BOARD, PROBE CARD, AND ELECTRONIC DEVICE TEST APPARATUS COMPRISING SAME - A probe card is provided which includes: probe needles electrically contacting input/output terminals of an IC device formed on a semiconductor wafer W; a mount base on which the probe needles are mounted; a support column supporting the mount base, a circuit board having interconnect patterns electrically connected to the probe needles via bonding wires; and a base member and stiffener for reinforcing the probe card. The mount base and the circuit board are noncontact.

FOUR-WIRE OHMMETER CONNECTOR AND OHMMETER USING SAME - A four-wire ohmmeter connector includes a pair of elongated members spaced apart from each other by an interconnecting web. A pair of elongated contacts are mounted on forwardly projecting portions of each of the elongated members. An insulative housing surrounds the elongated members, contacts and web. The contacts mounted on one of the elongated members are connected through separate wires to a positive probe, and the contacts mounted on the other of the elongated members are connected through separate wires to a negative probe. The elongated members are inserted into respective terminal apertures of a four-wire ohmmeter. A pair of semi-cylindrical conductive sleeves are aligned with each of the apertures, and they make contact with and compress the respective contacts that are inserted into the aperture.

2010-04-29

20100102840

TEST APPARATUS ADDITIONAL MODULE AND TEST METHOD - A test apparatus includes: test modules that communicate with the device under test to test the device under test; additional modules connected between the device under test and the test modules, each additional module performing a communication with the device under test; the communication being at least one of a communication performed at a higher speed and a communication performed with a lower latency, in comparison with a communication performed by the test modules; a test head having a plurality of connectors that connect the test modules and the additional modules, respectively, the test modules and the additional modules are mounted on the test head; a performance board placed on the test head that connects between at least a part of terminals of the plurality of connectors and the device under test. The test modules are connected to the additional modules without through the performance board.

2010-04-29

20100102841

DEVICE, METHOD AND PROBE FOR INSPECTING SUBSTRATE - A device for inspecting a substrate, including a probe and a support member configured to hold the probe is disclosed. The probe comprises a compression spring and includes a conductive material to measure an electric property of a substrate under inspection.

2010-04-29

20100102842

SYSTEM AND METHOD FOR MEASURING NEGATIVE BIAS THERMAL INSTABILITY WITH A RING OSCILLATOR - An integrated circuit, in accordance with one embodiment of the present invention, includes a first device under test (DUT) module coupled to a first ring oscillator module and a second DUT module coupled to a second ring oscillator module. The first DUT module is biased such that interface traps are generated during a first mode. The generated interface traps result in a decrease in a first drive current of the first DUT module. The second device under test module is biased to maintain a reference drive current during the first mode. The operating frequency of the first ring oscillator module, during a second mode, is a function of the first drive current. The operating frequency of the second ring oscillator module, during the second mode, is a function of the reference drive current. The integrated circuit may also include a comparator module for generating an output signal as a function of a difference between the operating frequency of the first and second ring oscillator modules.

2010-04-29

20100102843

SEMICONDUCTOR TEST HEAD APPARATUS USING FIELD PROGRAMMABLE GATE ARRAY - A semiconductor test head apparatus using a field programmable gate array (FPGA) is disclosed. A semiconductor test head apparatus using a field programmable gate array, includes a pattern generator for generating a predetermined memory test pattern, a driver/comparator unit comprising a first transceiver which performs a driver function capable of recording a memory test pattern generated from the pattern generator in a device under test and a comparator function capable of comparing a level of a signal read by the device under test with a predetermined high-level reference value, and a second transceiver which performs the driver function and a comparator function capable of comparing a level of a signal read by the device under test with a predetermined low-level reference value, and a connection unit for electrically connecting the first transceiver in parallel to the second transceiver, and connecting the first transceiver and the second transceiver to the device under test.

2010-04-29

20100102844

PROXIMITY CHARGE SENSING FOR SEMICONDUCTOR DETECTORS - A non-contact charge sensor includes a semiconductor detector having a first surface and an opposing second surface. The detector includes a high resistivity electrode layer on the first surface and a low resistivity electrode on the high resistivity electrode layer. A portion of the low resistivity first surface electrode is deleted to expose the high resistivity electrode layer in a portion of the area. A low resistivity electrode layer is disposed on the second surface of the semiconductor detector. A voltage applied between the first surface low resistivity electrode and the second surface low resistivity electrode causes a free charge to drift toward the first or second surface according to a polarity of the free charge and the voltage. A charge sensitive preamplifier coupled to a non-contact electrode disposed at a distance from the exposed high resistivity electrode layer outputs a signal in response to movement of free charge within the detector.

2010-04-29

20100102845

Proportional Regulation for Optimized Current Sensor Performance - An integrated circuit device comprises a first transistor having a gate coupled to an output of a first operational amplifier, a second transistor having a threshold voltage proportional to a threshold voltage of the first transistor, the second transistor having a gate coupled to an inverting input of a second operational amplifier, an output of the second operational amplifier coupled to an inverting input of the first operational amplifier, a first resistor coupled between the second transistor gate and the inverting input of the second operational amplifier, and a second resistor coupled between the output of the second operational amplifier and the inverting input of the second operational amplifier, a ratio of the second resistor to the first resistor selected based upon a ratio of a production distribution of a transistor source voltage offset to a production distribution of a transistor threshold voltage mismatch.

2010-04-29

20100102846

ROTOR/STATOR RELATIVE POSITION DETERMINING METHOD AND APPARATUS - A data signal indicative of a gap between a sensor and at least one of a surface of a rotor and a surface of a stator rotating relative to the sensor is sent to a computer processor. The computer implements defining a plurality of lowest values of the data signal over a revolution of relative rotation between the rotor and the stator, and displaying the plurality of lowest values for assessment of the distance between the sensor and a surface of at least one of the rotor and the stator in order to determine a position of the rotor relative to the stator.

2010-04-29

20100102847

MODULATED SUPPLY SPREAD SPECTRUM - A system reduces a received RF signal from EMI generated by a digital electronic system that includes a clock. In the present invention the clock frequency, that generates signals and strobes data out, is purposely changed or modulated, by, illustratively, driving the power node of the clock. The typical filter circuit between the clock power node and the power supply is used to advantage in that the filter impedance allows a buffer to more easily drive the clock power node since the low impedance of the power supply is isolated by the filter circuit. The changing of the clock frequency spreads the EMI RF harmonics over a spectrum so that any harmonics received by an RF receiver will be short lived and therefore of small magnitude.

2010-04-29

20100102848

Asynchronous Logic Automata - A family of reconfigurable, charge-conserving asynchronous logic elements that interact with their nearest neighbors permits design and implementation of circuits that are asynchronous at the bit level, rather than at the level of functional blocks. These elements pass information by means of charge packets (tokens), rather than voltages. Each cell is self-timed, and cells that are configured as interconnect perform at propagation delay speeds, so no hardware non-local connections are needed. An asynchronous logic element comprises a set of edges for asynchronous communication with at least one neighboring cell, each edge having an input for receiving tokens from neighboring cells and an output for transferring an output charge packet to at least one neighboring cell, and circuitry configured to perform a logic operation utilizing received charge packets as inputs and to produce an output charge packet reflecting the result of the logic operation.

2010-04-29

20100102849

ELECTRONIC DEVICE, METHOD FOR CONFIGURING REPROGRAMMABLE LOGIC ELEMENT, COMPUTER-READABLE MEDIUM, COMPUTER DATA SIGNAL AND IMAGE FORMING APPARATUS - An electronic device includes a reprogrammable logic element, a configuration data storage, a reading section, a dummy data creating section, a skip determination section, a writing section and a control section. The configuration data storage stores configuration data for the reprogrammable logic element. The reading section successively reads the configuration data from the configuration data storage. The dummy data creating section creates dummy data. The skip determination section determines as to whether or not the configuration data is to be skipped. The writing section writes the configuration data or the dummy data into the reprogrammable logic element. If the skip determination section determines that the configuration data is to be skipped, the control section controls the dummy data, which is created by the dummy data creating section, to be sent to the writing section.

2010-04-29

20100102850

SEMICONDUCTOR DEVICE - A semiconductor device includes an inductor configured to supply a current to a first node based on a higher voltage region power supply voltage. A first switch is configured to selectively supply a current from the first node into a third node based on a voltage on a second node; a second switch is configured to selectively supply a current from the first node into the second node based on a voltage of the third node; a third switch is configured to supply the current from the third node into a ground terminal based on a lower voltage region input logic level; and a fourth switch is configured to be turned ON/OFF alternately with the third switch to supply the current from the second node to the ground terminal.

2010-04-29

20100102851

P-Type Source Bias Virtual Ground Restoration Apparatus - A virtual ground restoration circuit is used to substantially eliminate excessive current from occurring in an integrated circuit device having two or more logic circuit modules in different voltage domains. Excessive current is caused when a signal between the two or more logic circuit modules in different voltage domains is at logic “0” and one of the logic circuit modules is biased at a voltage level above the true ground or common power source voltage, V

2010-04-29

20100102852

CIRCUITS AND METHODS FOR BUFFERING AND COMMUNICATING DATA SIGNALS - Method and apparatus are provided for buffering a data signal to a low voltage logic device. A circuit for buffering the data signal to the low voltage logic device includes an output buffer and an N-type transistor. The output buffer has an input and an output, where the input is configured to receive the data signal. The output buffer is configured to produce an output signal based on the data signal, and the output signal has a maximum potential. The N-type transistor has a source coupled to the output, a drain configured to couple to the low voltage logic device, and a gate configured to receive a bias potential, where the bias potential is greater than the maximum potential.

2010-04-29

20100102853

Circuitry and Methods Minimizing Output Switching Noise Through Split-Level Signaling and Bus Division Enabled by a Third Power Supply - Disclosed herein are circuitry and methods for transmitting data across a parallel bus using both high common mode and low common mode signaling. The transmitter stages are configured to work with two of three possible power supply voltages: a high Vddq voltage, a low Vssq voltage, and an intermediate Vx voltage. In one embodiment, the odd numbered transmitter stages, that drive the odd numbered outputs to the bus, use the Vddq and Vx supplies, such that the odd numbered outputs comprise high common mode signals. The even numbered transmitter stages, that drive the even numbered outputs to the bus, use the Vx and Vssq supplies, such that the even numbered outputs comprise low common mode signals. With the transmitter and power supplies so configured, no one of the three power supplies must source or sink current to or from more than half of the transmitters at any given time, which reduces power supply loading and minimizes switching noise. As a result, use of the technique may dispense with the need to provide power supply isolation at the transmitters.

2010-04-29

20100102854

CIRCULAR EDGE DETECTOR - A circular edge detector on an integrated circuit including a plurality of edge detector cells, each of the plurality of edge detector cells having an input select block operable to receive a data signal and a previous cell signal and to generate a present cell signal, and a state capture block operably connected to receive the present cell signal. The present cell signal of each of the plurality of edge detector cells is provided to a next of the plurality of edge detector cells as the previous cell signal for the next of the plurality of edge detector cells, and the present cell signal from a last edge detector cell is provided to a first edge detector cell as the previous cell signal for the first edge detector cell.

2010-04-29

20100102855

BUFFER DEVICE - In a buffer device a cross couple circuit includes a first power synthesis section in which a source of a first source follower and a drain of a first source-grounded amplifier are connected and a second power synthesis section in which a source of a second source follower and a drain of a second source-grounded amplifier are connected. A first bias circuit adjusts voltage of gates of the first source-grounded amplifier and the second source-grounded amplifier so as to make common-mode voltage of output from the first power synthesis section and output from the second power synthesis section equal to reference voltage. A second bias circuit applies compensation voltage to gates of the first source follower and the second source follower so as to control variation in voltage applied to the gates of the first source follower and the second source follower.

Switching circuit and driving circuit for transistor - A switching circuit includes: a transistor having a first electrode, a second electrode and a control electrode; a zener diode; and a capacitor. A connection between the first electrode and the second electrode is capable of temporally switching between a condition state and a non-conduction state by switching a control voltage of the transistor. The zener diode and the capacitor are coupled in series between the first electrode and the control electrode of the transistor. The first electrode is a drain or a collector.

2010-04-29

20100102858

METHOD AND APPARATUS FOR REDUCING INTERFERENCE - A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

2010-04-29

20100102859

LC VOLTAGE CONTROLLED OSCILLATOR TANK WITH LINEARIZED FREQUENCY CONTROL - Over the past few decades, phased locked loops or PLLs have become increasingly common in a variety of microelectronic applications. As such, the PLLs have both decreased in size and increased in speed, following the same trend as all other microelectronics. With this change in size and speed, alternative designs for voltage controlled oscillator tanks or VCOs (and other components of PLLs) are being developed. Here, an LC VCO with a correction circuit (for linearizing the frequency versus control voltage characteristics of the VCO) is described that can allow a small and fast PLL to remain generally stable over a wide range of frequencies.

2010-04-29

20100102860

WIDEBAND DELAY-LOCKED LOOP (DLL) CIRCUIT - A wideband delay-locked loop (DLL) circuit includes an internal clock signal generating unit providing an internal control signal by selecting and interpolating between two clock delay signals during a primary phase locking operation. The internal clock signal may be modified by a secondary phase locking operation if more delay is required to phase lock the internal clock signal to an external clock signal. A phase detection/control circuit generates various control signals based on a phase comparison of the internal clock signal and the external clock signal.

2010-04-29

20100102861

DLL CIRCUIT AND CONTROL METHOD THEREOF - A DLL circuit includes a first phase comparing circuit that compares phases between an input clock signal and an output clock signal, a first delay circuit that delays the output clock signal, and a second phase comparing circuit that compares phases between the input clock signal and an output signal of the first delay circuit. A delay amount in the variable delay circuit is controlled based on a comparison result of the first phase comparing circuit and a comparison result of the second phase comparing circuit.

DELAY CLOCK GENERATOR - A delay clock generator includes a plurality of delay element arrays arranged in parallel; a feed side transfer line and a return side transfer line provided in each of the delay elements which make up the delay element arrays, and that transfer a clock signal in a feed direction and a return direction; a selector selecting a first transfer route that couples the feed side transfer lines to each other along the preceding and succeeding delay elements and a third transfer route that couples the return side transfer lines to each other along the preceding and succeeding delay elements, and a second transfer route that couples the feed side transfer lines and the return side transfer lines of each of the delay elements; and a decoder causing the selector to select the second transfer route for one of the delay elements in the delay element array.

2010-04-29

20100102864

TRANSMISSION CIRCUIT - A transmission circuit including a first circuit outputting a first signal based on an input data, a second circuit outputting a second signal based on the input data, where each of the first signal and the second signal functions as a differential signal, a correction circuit generating a correction signal for correcting variation in current drive capabilities of two transistors of a first buffer included in at least one of the first circuit and the second circuit, and a second buffer coupled in parallel with the first buffer and reducing, based on the correction signal, the variation in the current drive capabilities of the two transistors.

2010-04-29

20100102865

STANDBY CONTROL CIRCUIT AND METHOD - A standby control circuit for an integrated circuit module includes a first control circuit that is responsive, in a normal operating mode of the integrated circuit module, to an asynchronous standby signal indicating a standby mode entry event to output a standby mode signal synchronous with a primary clock signal to indicate a standby operating mode of the integrated circuit module. The standby control circuit also includes a second control circuit which is responsive, in a reduced power mode of the integrated circuit module, to the asynchronous standby signal indicating the standby mode entry event to control the first control circuit to output the standby mode signal synchronous with a secondary clock signal to indicate the standby operating mode.

2010-04-29

20100102866

SIGNAL PROCESSING APPARATUS INCLUDING LATCH CIRCUIT - A signal processing apparatus includes: a latch circuit; a set pulse generation circuit; a reset pulse generation circuit; and a correction set signal forming circuit. The correction set signal forming circuit forms a correction set signal for applying a set instruction continuously during a time period from a time point of a front edge of the set pulse generated from the set pulse generation circuit or a time point delayed from the time point of the front edge to a time point at which the reset pulse is generated. The correction set signal forming circuit supplies the correction set signal to the set input terminal of the latch circuit.

2010-04-29

20100102867

SENSE AMPLIFIER BASED FLIP-FLOP - A sense amplifier based flip-flop having built-in logic functions. The flip-flop includes a first and second input circuits configured to cause complementary first and second logic values to be provided on first and second logic nodes, respectively. The flip-flop further includes a sense circuit configured to sense and capture the first and second logic values on first and second capture nodes, respectively, during an evaluation phase, and a precharge circuit configured to precharge the first and second logic node and the first and second capture nodes during a precharge phase. The flip-flop also includes a noise immunity circuit, configured to, during the evaluation phase, become active subsequent to the sense circuit capturing the first and second logic values, wherein, when activated, the noise immunity circuit prevents floating voltages on the first and second logic nodes.

2010-04-29

20100102868

Hardware and Method to Test Phase Linearity of Phase Synthesizer - A circuit to test phase linearity of a phase synthesizer, which synthesizes an output clock having a phase corresponding to a digital phase value input to the phase synthesizer. A digital counter provides the digital phase value to the phase synthesizer. The digital counter receives a counter clock synchronized with an input clock. The digital phase value is stepped by the digital counter, thereby shifting the frequency of the output clock. The output clock is analyzed with respect to phase linearity of the phase synthesizer to produce a phase linearity analysis output.

2010-04-29

20100102869

Apparatus and Method for Generating a Clock Signal - An apparatus and method are disclosed for generating one or more clock signals. A clock signal is generated based on pattern signals and a reference clock signal. When the reference clock signal transitions high, the state of a first pattern signal is output, and when the reference clock signal transitions low, the state of a second pattern signal is output. Successive states of the first and second pattern signals, selected according to the reference clock signal, provide the generated clock signal.

2010-04-29

20100102870

WIDEBAND SWITCHED CURRENT SOURCE - A current source block provided according to an aspect of the present invention provides a substantially constant current even when the provision of the current is switched on and off at different frequencies. The current source block contains a main portion and a replica portion, with each portion having a current source and switches to connect output of the current source to corresponding output nodes. Additional connections are provided to enable the replica portion to counter deviations in the current output of the main portion due to parasitic effects. As a result, the current source block provides a constant current even when switched off/on at different (in particular high) frequencies. Such current source blocks may be used in components such as current steering DACs to obtain a linear response even at high operational frequencies.

2010-04-29

20100102871

ELECTRONIC CIRCUIT AND METHOD FOR CONTROLLING A POWER FIELD EFFECT TRANSISTOR - An electronic circuit and a method for controlling a power field effect transistor. The electronic circuit comprises a power field effect transistor having a semiconductor body, which has a drain zone, a drift zone, a source zone and a bulk zone. The power field effect transistor further comprises a gate and a field plate. The field plate is placed adjacent to the drift zone and is isolated from the drift zone. A switch circuitry is provided for electrically connecting the field plate depending on the drain-source voltage such that the field plate is electrically connected to the drain zone, if |UDS|>UT, where UT is a predetermined voltage, and if |UDS|>UT, the field plate is connected to an electrode having an electrode-source voltage UES.

2010-04-29

20100102872

Dynamic Substrate Bias for PMOS Transistors to Alleviate NBTI Degradation - This invention discloses a system and method for suppressing negative bias temperature instability in PMOS transistors, the system comprises a PMOS transistor having a source connected to a power supply, and a voltage control circuitry configured to output a first and a second voltage level, the first and second voltage levels being different from each other, the first voltage level is lower than the power supply voltage, the second voltage level is equal to or higher than the power supply voltage, wherein when the PMOS transistor is turned on, the first voltage level is applied to a substrate of the PMOS transistor, and when the PMOS transistor is turned off, the second voltage level is applied to the substrate of the PMOS transistor.

2010-04-29

20100102873

Output Driving Circuit for an Ethernet Transceiver - An output driving circuit for an Ethernet transceiver is utilized for driving a load, which includes a first loading end and a second loading end. The output driving circuit includes a voltage output driver, a first resistor, a second resistor, a first current source, a second current source, a third current source and a fourth current source. The voltage output driver is utilized for providing an output voltage. The first resistor and the second resistor are utilized for modifying impedance matching with the load. When the output voltage is positive, the first current source and the second current source are turned-on, and the third current source and the fourth current source are turned-off. Whereas when the output voltage is negative, the first current source and the second current source are turned-off, and the third current source and the fourth current source are turned-on.

2010-04-29

20100102874

SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element including a current mirror circuit, a parasitic resistance formed at the current mirror circuit, and a connection terminal electrically connected to a part of the current mirror circuit via an electric conductor including a bonding wire, the connection terminal being configured to perform input and output relative to an outside of the semiconductor device; wherein a resistance value of the bonding wire is controlled so that a shift of an output electric current of the current mirror circuit based on the parasitic resistance is corrected.

2010-04-29

20100102875

SUBSTRATE NOISE PASSIVE CANCELLATION METHOD FOR BUCK CONVERTER - A method for passive cancellation of substrate noise for a buck converter uses an on-chip capacitor to reduce the substrate noise. The capacitor achieves a close-magnitude noise with opposite phase for better noise cancellation effect in the substrate. The capacitor can be realized as a MOS capacitor, NMOS isolation ring n-well capacitor, n-well junction capacitor, isolated p-well junction capacitor, etc. The capacitor is easy to implement. Further, bond wire parasitic inductance in the buck converter is used to reduce substrate noise.

2010-04-29

20100102876

METHOD AND APPARATUS FOR REDUCING INTERFERENCE - A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

2010-04-29

20100102877

METHOD AND APPARATUS FOR REDUCING INTERFERENCE - A method and apparatus is provided for reducing interference in circuits. A management strategy is provided to reduce reference spurs and interference in circuits. The management strategy uses a combination of one or more techniques which reduce the digital current, minimize mutual inductance, utilize field cancellation, prevent leakage current, and/or manage impedance. These techniques may be used alone, or preferably, used on combination with one another.

2010-04-29

20100102878

PHYSICAL QUANTITY SENSOR - A physical quantity sensor includes a sensor element for converting a physical quantity applied from outside into an electric signal, a detection circuit for amplifying and detecting an output signal of the sensor element, and an adjusting circuit for adjusting the output signal from the detection circuit to a predetermined signal. The adjusting circuit has an amplifying circuit for amplifying the output signal from the detection circuit and a reference amplification circuit having an amplification ratio linked with the amplifying circuit. With this configuration, it is possible to change the amplification ratio of the amplifying circuit provided in the adjusting circuit in accordance with a power voltage. As a result, it is possible to realize a physical quantity sensor having stable sensor detection sensitivity and highly accurate ratiometric characteristic.

2010-04-29

20100102879

METHOD AND APPARATUS FOR AUTOMATICALLY CONTROLLING AN XNN.RTM. ENHANCEMENT CIRCUITRY FEEDING A POWER AMPLIFIER - Method and apparatus for automatically controlling the operation of a DC power enhancement circuitry connected to an RF power amplifier (PA) that operates at various input signal levels, according to which the instantaneous magnitude of the input signal is sensed and the instantaneous magnitude and its highest (lowest) peak are stored. For the time period during which the peak remains the highest (lowest) peak, the desired dynamic range of the power amplifier is determined according to the peak and a corresponding threshold level and the gain of the enhancement circuitry are determined according for that time period. Whenever the magnitude exceeds the corresponding threshold level, the enhancement circuitry provides to the power amplifier a level of DC power enhancement required for maintaining the output power of the power amplifier within the output dynamic range. Whenever a higher (lower) peak is detected, the process is repeated for the time period during which the lower peak remains the highest (lowest) peak of all preceding peaks and the value of the stored highest (lowest) peak is updated accordingly.

2010-04-29

20100102880

LOAD DRIVE DEVICE - A load drive device has a load drive unit including an input system electrically connectable to a control power supply and an output system electrically connectable to a load drive power supply. The load drive unit supplies the electrical load with load drive voltage from the load drive power supply via the output system when the control power supply applies control voltage to the input system. A potential difference detection unit detects a potential difference between the control voltage and the load drive voltage. A potential fixing unit fixes a potential at a control system electrical route, connecting the control power supply and the input system of the load drive unit, to a prohibition level that prohibits the output system of the load drive unit from driving the electrical load when the potential difference detected by the potential difference detection unit exceeds a predetermined threshold value.

2010-04-29

20100102881

SAMPLING FREQUENCY REDUCTION FOR SWITCHING AMPLIFIERS - The present invention is directed toward providing a system and method of reducing RF interference in switching amplifiers without degrading performance. In one embodiment, the sampling rate of coarse high voltage modulated pulsewidths are decreased relative to the sampling rate of fine lower voltage modulated pulsewidths. This reduction in the sampling rate of coarse high voltage modulated pulsewidths results in a reduction in EMI. In addition, the higher sampling rate of the fine lower voltage modulated pulsewidths mitigates the distortion caused by the reduced sampling rate of the coarse pulsewidths.

2010-04-29

20100102882

ELECTRIC LOAD DRIVING CIRCUIT - An electric load driving circuit for driving an electric load having a capacity component includes a plurality of power sources generating different voltages, capacitors provided parallel to the plurality of power sources, a switch control unit that switches connections between the capacitors and the electric load and thereby switching a voltage applied to the electric load, discharge paths that enable discharging electric charge stored in the capacitor, and a discharge control unit that controls a quantity of electric charge discharged from the discharge paths.

2010-04-29

20100102883

PWM SIGNAL GENERATION CIRCUIT, CLASS-D AMPLIFIER AND METHOD FOR DRIVING THE SAME - A first situation indicating that the system is in a power-on situation or an un-mute situation, or a second situation indicating that the system is in a power-off situation or in a mute situation, is detected. When the first situation is detected, a differential PWM signal including a plurality of pulses each having a gradually increased or reduced width and the subsequent pulse train of 50% duty cycle pulses is generated and, if the output of an audio processor is in a stable situation, sent to the amplifier via a multiplexer. When the second situation is detected, the differential PWM signal including a plurality of pulses each having a gradually reduced width and the subsequent pulse train of no signal is generated and, at the same time, the generated pulses are sent to the amplifier via the multiplexer.

2010-04-29

20100102884

DRIVER CIRCUIT AND DRIVER IC - A driver circuit comprises: differential amplification stages connected in series, and at least two cross-point adjuster circuits respectively connected to at least two differential amplification stages of the differential amplification stages. The cross-point adjuster circuits control at least one of the positive-phase and negative-phase DC levels of a corresponding differential amplification stage and adjust the cross point of the output signals of the corresponding differential amplification stage.

2010-04-29

20100102885

Method And System For Amplifying A Signal Using A Transformer Matched Transistor - A power amplifier includes a transistor, a transmission line transformer, and a capacitor. The transistor is operable to receive a signal and to generate an amplified signal. The transistor has a source, a drain, and a gate. The gate has a first impedance and is operable to receive the signal to be amplified. The transmission line transformer has a first, second, third, and fourth port, the first port being coupled to the gate of the transistor and the third port, and the fourth port being coupled to a source device having a second impedance. The capacitor has a first end and a second end. The first end of the capacitor is coupled to the second port of the transmission line transformer and the second end is coupled to a ground.

2010-04-29

20100102886

AMPLIFIER DEVICE - Provided is an amplifier device including a J-FET, a bipolar transistor, a first resistor and a second resistor. The amplifier device has a configuration in which a gate of the J-FET is connected to one end of an ECM and one end of the first resistor, a drain of the J-FET is connected to an input terminal of the bipolar transistor, a high-potential side of the bipolar transistor is connected to one end of a load resistor, the other end of the first resistor is grounded, a source of the J-FET and a low-potential side of the bipolar transistor are connected to one end of the second resistor, the other end of the second resistor is grounded, and an output voltage is drawn from the high-potential side of the bipolar transistor.

2010-04-29

20100102887

ELECTRONIC COMPONENT FOR HIGH FREQUENCY POWER AMPLIFICATION - An electronic component for high frequency power amplification realizes an improvement in switching spectrum characteristics. The gain of an amplifying NMOS transistor is controlled by a bias voltage on which a bias control voltage is reflected. Further, a threshold voltage compensator compensates for a variation in threshold voltage with variations in the manufacture of the amplifying NMOS transistor. The threshold voltage compensator includes an NMOS transistor formed in the same process specification as the amplifying NMOS transistor and converts a variation in current flowing through the NMOS transistor depending on the variation in the threshold voltage of the amplifying NMOS transistor to its corresponding voltage by a resistor to compensate for the bias voltage. It is thus possible to reduce variations in so-called precharge level brought to fixed output power in a region (0 dBm or less, for example) low in output power.

2010-04-29

20100102888

TIMING RECOVERY FOR PARTIAL-RESPONSE MAXIMUM LIKELIHOOD SEQUENCE DETECTOR - An embodiment of the present invention is a technique for timing recovery. A frequency acquisition loop locks a voltage controlled oscillator (VCO) clock of a multi-band VCO to a reference clock. The frequency acquisition loop generates first and second feedback clocks from the VCO clock. A data lock phase loop generates a driving signal corresponding to a phase error signal from interleaved partial response signal (PRS) samples based on the second feedback clock. The driving signal controls the multi-band VCO in a data phase lock mode. A lock detect controller detects a frequency lock condition in a frequency lock mode and a data lock condition in the data phase lock mode based on the first feedback clock and the reference clock.

2010-04-29

20100102889

SYSTEMS AND METHODS FOR TRACKING COMMUNICATION PARAMETERS OVER A PLURALITY OF FREQUENCY BANDS - In at least some embodiments, a communication system includes a receiver having a local oscillator (LO) for each of a plurality of frequency bands. Each LO is controlled by a separate phase-locked loop (PLL) that tracks carrier frequency offset (CFO) using a common phase error (CPE). The CPE is selectively weighted based on at least one inter-band frequency correlation (IFC) coefficient.

2010-04-29

20100102890

Variable-Loop-Path Ring Oscillator Test Circuit and Systems and Methods Utilizing Same - Circuitry for determining timing characteristics, for example, access time, setup time, hold time, recovery time and removal time, of as-manufactured digital circuit elements, such as latches, flip-flops and memory cells. Each element under test is embodied in variable-loop-path ring oscillator circuitry that includes multiple ring-oscillator loop paths, each of which differs from the other(s) in terms of inclusion and exclusion of ones of a data input and a data output of the element under test. Each loop path is caused to oscillate at each of a plurality of frequencies, and data regarding the oscillation frequencies is used to determine one or more timing characteristics of the element under test. The variable-loop-path ring oscillator circuitry can be incorporated into a variety of test systems, including automated testing equipment, and built-in self test structures and can be used in performing model-to-hardware correlation of library cells that include testable as-manufactured digital circuit elements.

2010-04-29

20100102891

OSCILLATOR DEVICE AND METHODS THEREOF - An oscillator device includes a plurality of stages. Each stage is a monostable stage having a delay path, whereby a signal transition of a designated type (rising or falling) at the input of the delay path results in a signal transition at the output of the stage of the same transition type. Each stage of the oscillator device also includes a reset module that causes the output signal to be reset to a nominal state a predetermined period of time after the signal transition of the output signal. Each stage thus provides an output signal pulse in response to the signal transition of the designated type at the input. The output of the final stage of the oscillator device is connected to the input, so that the oscillator output provides an oscillating signal having a period based upon the delay path of each the oscillator device stages.

2010-04-29

20100102892

CRYSTAL OSCILLATOR - A crystal oscillator includes a crystal unit and a voltage-variable capacitive element that is connected to the crystal unit in series, the crystal oscillator varying an oscillation frequency by applying a control voltage between terminals of the voltage-variable capacitive element and by varying a series equivalence capacitance at a side of the oscillator circuit when observed between terminals of the crystal unit. The crystal oscillator further includes a first resistor and a second resistor for dividing the control voltage. At least one of the first resistor and the second resistor is a temperature sensing resistor, the resistance of which changes depending on a temperature, so as to correct frequency temperature characteristics of the oscillation frequency.

2010-04-29

20100102893

PHYSICAL SECTION OF ATOMIC OSCILLATOR - A physical section of an atomic oscillator includes at least: a gas cell including a cylindrical portion and first and second windows respectively hermetically-closing openings of both sides of the cylindrical portion to form a cavity in which gaseous metal atoms are sealed; a light reflection unit disposed on the first window; a first heating unit disposed to be closely attached to the second window and heating the gas cell at a predetermined temperature; a light source disposed so as to allow a light emitting part thereof to face the light reflecting unit, emitting excitation light exciting the metal atoms in the gas cell, and provided on a side, which is a reverse side to a side to which the gas cell is provided, of the first heating unit; a light detection unit detecting the excitation light reflected by the light reflection unit and provided also on a side, which is a reverse side to a side to which the gas cell is provided, of the first heating unit; and a Peltier element interposed between the light source and the first heating unit, and between the light detection unit and the first heating unit.

2010-04-29

20100102894

DIGITALLY CONTROLLED OSCILLATOR WITH IMPROVED DIGITAL FREQUENCY CALIBRATION - Techniques for calibrating digitally controlled oscillators (DCOS) are disclosed. In one aspect of the disclosure, an initial set of control codes for operating the DCO with a coarse frequency tuning bank with multiple overlapping coarse frequency tuning segments (LTBs) and one fine main frequency tuning bank (MTB) is determined. A range of output frequencies produced from the initial set is identified. Instances of overlap are identified in the frequency range between consecutive LTB segments. An offset in the MTB is added that corresponds to the overlap instance between consecutive LTBs to establish a revised set. The revised control codes are utilized to tune the DCO over the desired frequency range.

2010-04-29

20100102895

QUADRATURE MODULATION CIRCUITS AND SYSTEMS SUPPORTING MULTIPLE MODULATION MODES AT GIGABIT DATA RATES - Quadrature modulation systems, circuits and methods are provided to support various modulation modes including ASK (amplitude shift key), FSK (frequency shift key) and PSK (phase shift key) modulation at high data rates (e.g., gigabit data rates). For example, a modulation circuit includes a mixer circuit including an integrated sign modulation control circuit and a plurality of mixer ports. The mixer ports include a first input port, a second input port, an output port and a sign modulation control port. The modulation circuit generates a modulated signal by operation of the mixer circuit multiplying a modulating signal applied to the first input port with a carrier signal applied to the second input port to generate a mixed signal output from the output port, and by operation of the integrated sign modulation control circuit controlling polarity switching of a signal at one of the mixer ports in response to a sign modulation control signal input to the sign modulation control port. The sign modulation control signal can be a digital data signal having binary data encoded into the modulated signal.

2010-04-29

20100102896

MICROWAVE CIRCULATOR WITH THIN-FILM EXCHANGE-COUPLED MAGNETIC STRUCTURE - A microwave circulator uses a thin-film exchange-coupled structure to provide an in-plane magnetic field around the circulator. The exchange-coupled structure is a ferromagnetic layer having an in-plane magnetization oriented generally around the circulator and an antiferromagnetic layer exchange-coupled with the ferromagnetic layer that provides an exchange-bias field to the ferromagnetic layer. A plurality of electrically conductive ports are connected to the exchange-coupled structure. Each of the portions or legs of the circulator between the ports may have an electrical coil wrapped around it with each coil connected to an electrical current source. The ferromagnetic resonance (FMR) frequency of the exchange-coupled structure in the absence of an external magnetic field is determined by the properties of the material of ferromagnetic layer and the magnitude of the exchange-bias field due to the exchange-coupling of the ferromagnetic layer to the antiferromagnetic layer. If one or more of the optional coils is used, then the FMR frequency can be tuned by changing the current in the coil or coils to change the magnitude of the externally applied magnetic field.