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MojoKid (1002251) writes For years, we've heard rumors that Intel was building custom chips for Google or Facebook, but these deals have always been assumed to work with standard hardware. Intel might offer a different product SKU with non-standard core counts, or a specific TDP target, or a particular amount of cache — but at the end of the day, these were standard Xeon processors. Today, it looks like that's changing for the first time — Intel is going to start embedding custom FPGAs into its own CPU silicon. The new FPGA-equipped Xeons will occupy precisely the same socket and platform as the standard, non-FPGA Xeons. Nothing will change on the customer front (BIOS updates may be required), but the chips should be drop-in compatible. The company has not stated who provided its integrated FPGA design, but Altera is a safe bet. The two companies have worked together on multiple designs and Altera (which builds FPGAs) is using Intel for its manufacturing. This move should allow Intel to market highly specialized performance hardware to customers willing to pay for it. By using FPGAs to accelerate certain specific types of workloads, Intel Xeon customers can reap higher performance for critical functions without translating the majority of their code to OpenCL or bothering to update it for GPGPU.

No ignore that entire last sentence, it's dumb. FPGAs don't do floating point very well for one and even their integer performance will never rival a GPGU either in performance, or power. For another, I can and do, use both FPGAs and OpenCL/GLSL in my daily life and would infinitely prefer to port my functions to OpenCL over an FPGA. It's quite a bit more work to synthesize and validate an FPGA design than it is to write OpenCL code and debug the usual way.

I think it's far more likely customers are implementing custom hardware solutions using the FPGA related to power management, server management and datastructure infrastructure that can only be done with an FPGA in certain power domains. I say this having designed servers and dealt with the feature requests.

FPGAs don't do floating point very well for one and even their integer performance will never rival a GPGU either in performance, or power.

Sure, and a hammer makes a terrible screwdriver. GPUs are specifically designed for register-to-register SIMD operations, so of course they are going to excel at that. But an FPGA is going to be better at bitstream operations, including many hashing and encryption algorithms.

GPUs are primarily being used because everyone has one. FPGAs are about 10x faster and consume about the same amount of power as a GPU for stuff like bitcoin. the problem is the up-front cost and trust issues from the companies that make these pre-built FPGA boards.

Of course, bitcoin mining using the SHA256 hash which is not a typical application for a GPU. It involves a lot of shuffling at the bit level, which a GPU was not designed for.
For some other workloads, involving standard math operations, or large amounts of memory bandwith, the GPU will likely be faste.r

That's great, so they're going to port their code to Open CL, then run it on your FPGA? Why not just buy a GPU and plug it in?

If they're really set on your FPGA, why not buy a PCIe attached version of your FPGA? Xilinx has them and they go up to pcie v3 x8? What about power? Datacenters care, FPGAs are going to use more power. Why is this a good idea?

Some workloads perform much better on an FPGA, notably, realtime encoding/compression of HD H.264 video. I know because I've worked on such a broadcast quality encoder [currently being used by some major distribution outlets]. While you're right that it's harder to program an FPGA [in particular, validate the design], the performance gains can be huge. In particular, calculating motion vectors gets a win.

"By using FPGAs to accelerate certain specific types of workloads, Intel Xeon customers can reap higher performance for critical functions without translating the majority of their code to OpenCL or bothering to update it for GPGPU"

LOL. But they will have to translate it to Verilog or VHDL, which is far harder.

My guess would be that the real perk is bandwidth and latency. Unless Intel really phones it in on integration, the FPGA should have about the fastest, lowest-latency, link to the CPU, possibly even some of the cache, especially if they throw in a big chunk of eDRAM, as they have for 'Iris Pro' parts, that money can buy.

Less of a "Hey, let's do this instead of GPU compute!" and more of a "It sucks that our weirdo application-specific operation is probably never going to be one of Intel or AMD's extensions to x86; but this is the closest we can get to having it added" thing.

My guess would be that the real perk is bandwidth and latency. Unless Intel really phones it in on integration, the FPGA should have about the fastest, lowest-latency, link to the CPU, possibly even some of the cache, especially if they throw in a big chunk of eDRAM, as they have for 'Iris Pro' parts, that money can buy.

Less of a "Hey, let's do this instead of GPU compute!" and more of a "It sucks that our weirdo application-specific operation is probably never going to be one of Intel or AMD's extensions to x86; but this is the closest we can get to having it added" thing.

What I began fantasizing about immediately upon reading the article was some sort of optimizer that would semi-automatically build functional units to perform whatever function the CPU was grinding on at the moment, with some sort of recognition engine and periodic updates garnered from participating customers to help special-yet-common cases. As well, seeing how customers actually use FPGA with their products will help Intel decide what functionality to add to their next (or next+1, etc) processor.

There are already options to add an FPGA to your Xeon system, with its own blob of RAM. Since they talk about this being fundamentally different, I'm not sure what makes sense except the idea of it being connected at the memory controller. Hopefully there will be a talk with some nice block diagrams released soon.

Bingo. Imagine an LLVM based optimisation pass that uses profiling data to take a hot code block and translate it to run on the FPGA. Anywhere in your implementation where the CPU core is the bottleneck, rather than memory access. And since it's in the CPU, you could shift from running x86 instructions to raw hardware without the complexity and latency increase of piping data to a GPU or other external device.

Any way you set it up, your going to need OS support to reconfigure the FPGA. Perhaps a well defined section in the ELF format, with some kind of locking semantics to prevent more than one process from using it. That would depend on how many FPGA resources / CPU cores you have....

Anyone who is going to spend the money to buy and use these CPU's, will have to solve this problem. For the short term, this is likely to only be used in high end clustered server farms, for workloads where you wouldn't want to sw

These customers have lots of I/O that, if you can do high performance optimized operations on a general CPU how useful would that be ?

Think of something like liberouter or NetFFPGA embedded on the CPU die.

Or maybe the FPGA is used to implement calculations like crypto and hashes like CRC32C. Instead of building them into the silicon, why not make it possible to do research by loading new versions of it.

Maybe you just need to look around on the Internet what other companies

Since this is in the CPU die, it can't add to the I/O throughput of the CPU, unless the code you're running isn't fast enough to saturate the memory bus. Even if your code is saturating I/O you might want to use an FPGA to reduce power consumption.

LOL. But they will have to translate it to Verilog or VHDL, which is far harder.

I suppose it depends on your skill set, but I find Verilog to be much easier than coding GPU pipelines. You just need to realize that you are not coding a program that will be sequentially executed, but a hardware description where everything happens at once. Anyway, these chips sound really slick, and I would definitely pay for a PC containing a CPU with some FPGA fabric instead of a standard X86.

LOL. But they will have to translate it to Verilog or VHDL, which is far harder.

I suppose it depends on your skill set, but I find Verilog to be much easier than coding GPU pipelines. You just need to realize that you are not coding a program that will be sequentially executed, but a hardware description where everything happens at once. Anyway, these chips sound really slick, and I would definitely pay for a PC containing a CPU with some FPGA fabric instead of a standard X86.

You don't have to close timing on an actual circuit when programming GPU. You write your program and off you go.

There are already network cards equipped with FPGAs to cut the latency down for such liquidity harvesting.

Making a general-purpose processor that people use where they used to use a bunch of custom kit is kind of intel's thing. Every so often they try making a specific-purpose processor and then they always return to generalization. This is pretty much the epitome of that trend, now they're not even telling you what the hardware will do.

By using FPGAs to accelerate certain specific types of workloads, Intel Xeon customers can reap higher performance for critical functions without translating the majority of their code to OpenCL or bothering to update it for GPGPU.

What? This doesn't make sense. Unless Intel invented a way to automatically generate parallel code (in which case it could also be used in GPUs), somebody would have to rewrite the relevant parts of the program in VHDL, Verilog, OpenCL, or whatever.

I see this as a really good thing. More options for parallel computing are great. Writing the parallel parts in VHDL/Verilog isn't too bad if you studied computer/electrical engineering. This is a good technology to compete with GPUs.
To me, writing parts in Verilog for parallel data computations would be easier than using OpenCL and similar. I'm sure the development tools would be updated for this kind of support.

By using FPGAs to accelerate certain specific types of workloads, Intel Xeon customers can reap higher performance for critical functions without translating the majority of their code to OpenCL or bothering to update it for GPGPU.

What? This doesn't make sense. Unless Intel invented a way to automatically generate parallel code (in which case it could also be used in GPUs), somebody would have to rewrite the relevant parts of the program in VHDL, Verilog, OpenCL, or whatever.

I would assume the FPGA part of the CPU would be programmed in VHDL. Once programmed, it would act like a set of custom instruction sets in the CPU.

Simple example. An operation like a bit circling (10010 -> 00101 move the bits one step to the left and move the first bit to the end getting 00101) is very inefficient. You can left shift but the first bit falls of and then you have to and it and then put in the end. A lot of operations. A custom FPGA operation to do just that could be just one instruction

IMHO hardware design tools have had far less investment than compiler tools, and we're overdue to invest more effort in improving them.

Since the FPGA is in the CPU, I assume there are either CPU instructions to pipe data in and out of the FPGA. Or the FPGA may have direct access to the memory controller / cache. Either way you need a good way to synchronise between them.

So consider a solution that takes LLVM bitcode and runtime profiling data. Pick out some number of hot code blocks in an optimisation pas

As a hardware hacker, god I want one of these. On chip reprogramable DSP!? While it's a niche market, I'd love to get my hands on some, and not have to give up my favorite OS or build custom boards to do signal processing.

Actually the Virtex parts are faster (IO, at least) and larger, but Altera has OpenCL and. IMO, a much better toolchain than Xilinx. Xilinx has some awesome technology for 2.5D interposer hybrids which is bringing the scale up and the cost of scale down, but Altera has Intel 14nm trigate for their upcoming Stratix 10 parts, which may mean they are faster than Virtex 7.

Yes, I do data acquisition, and we only use board with FPGAs, such as Xilinx' offerings. This way we don't have to deal with the horrors of real-time OSes. Just do the acquisition in VHDL and send the buffer to the OS via a simple to write driver. Those would blow Xilinx out of the water (not that it's necessary for most low-power low-speed applications)

Given that Intel added AES-NI without a ripple several years ago, and somewhat similar crypto acceleration functions were available on Geode LXes and some fairly antique VIA x86 cores(and very likely a lot of embedded stuff that was too feeble for much software crypto, albeit probably not exposed to anybody who hadn't sold their soul to qualcomm for BREW elite developer status or something), probably not many beyond whatever ones apply by default to all kinds of things.

True, though you'll note that many of the changes in the linked document refer to loosening after encryption systems were removed from 'munitions' classification and assorted expansions of 'self-report', new categories with reduced reporting requirements, and so on.

I have no doubt that the amount of paperwork require to fully comply with the law in exporting something every war3z kiddie in Iran already has is still silly, and I don't doubt that there's a cube somewhere in Intel Inc. whose salary is justi

I have a friend in that in graduate school used a motherboard that could take an Altera FPGA in one of the Xeon sockets. This seems like the next logical step; hopefully it's not too expensive so that the hardware is accessible to hobbiest/engineers. I am happy that both Xilinx and Altera offer cheap development boards so that we can play with the new offerings. It's easier to convince a boss to use it if we're familiar with it. (hint hint, wry grin)

I use the zynq processor at my job, and am very happy with the amount of flexibility you can get out of an embedded system having access to the FPGA and processor fabric; you can directly access gigasample ADC's, etc. When I first got into embedded systems on an FPGA, the processor was a soft-IP and not terribly fast. Both Xilinx and Altera now offer ARM processors that run up to 1GHZ. The amount of system flexibility is great. You can make major architectural choices without changing the hardware. You might have a data-path, or computation that is simply too intensive for a processor to handle.. You have the flexibility to port this portion to the logic side. If you're in a rapid prototyping mode and are constrained by board size and mechanical packaging constraints, FPGAs are great.

Debugging SoC still has it's challenges though. It's easy to program FPGAs, and easy to program the microprocessor. The tools are still a little clunky from Xilinx or Altera to handle their hybrid SoC parts. There is still work to be done to make them work more seamlessly.

I'd already been thinking about the possibility of end-user-accessible, on-the-fly-reprogrammable FPGA functionality as part of a "regular" computer before I heard Intel had produced an integrated CPU/FPGA (though it's not clear how easily configurable the FPGA was there). I raised the issue in that previous thread and got a *very* interesting and informative response [slashdot.org] (thank you Tacvek) that pointed out some major problems with the concept of general access to such functionality.

The issues raised there explain why Intel are unlikely to be making an easily-reconfigurable hybrid product like this available to the general public any time soon, however smart and exciting the idea sounds.

I hope they allow customer instructions like the NIOS soft CPU in Altera FPGAs. This lets you create customer HW to implement some function at the ISA level... Altera lets you do single or multi cycle return. And auto generates either an instruction for ASM use or some stubs for C. It really is super useful.

"Bob, we're glad you Intel boys have finally come around"."Hi Jeff. Yeah, well we just about got the marketing boys convinced enough to run with it. They managed to find an angle that flies pretty well. Gets us off the hook and gets your boys into a heck of a lot of servers!""Hey, it's a win-win so far as I'm concerned. Wish it could have been sooner though, but what with all this pressure from the purse-holders, we couldn't bankroll it for you"."Times are getting tough, huh? It wasn't that long ago you NSA