We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome,
Firefox,
Internet Explorer 11,
Safari. Thank you!

AR# 34142

Spartan-6 - What is the best way to find which I/Os are related to a specific BUFIO2 site?

Description

The Spartan-6 FPGA Clocking Resources User Guide (UG382) refers to the BUFIO2 Clocking Region information in the Spartan-6 FPGA Packaging and Pinout Specification (UG385), but the information is not available in this document.

Solution

The BUFIO2 Clocking Region information is scheduled to be added to a future release of the Spartan-6 FPGA Packaging and Pinout Specification (UG385). Please note that the Clocking Region names in the documentation are going to change from "A, B, C, D, E, F, G, H" to "TL, TR, RT, RB, BR, BL, LB, LT". TL = Top Left, or the left half of the top edge, and matches the constraint syntax that can be used on the pins to force them to a particular BUFIO2 Clocking Region. Both UG382 and UG385 are expected to be updated by the end of February 2010. The current Spartan-6 FPGA ASCII package files on www.xilinx.com are also going to be updated with the correct BUFIO2 information (this is expected to be done by early May 2010). To request an advance copy of an ASCII package file, contact Xilinx Support with the part/package combination of interest.

The package files are going to be changed to what is shown below. As you can see, all of these pins are located in the TL BUFIO2 Clock Region (top left of the device):

It is good design practice to use the fewest amount of clock buffer resources as possible.You can accomplish this by staying in one BUFIO2 clock region (half bank). The software tools can assist you when pinning out a design if you use the LOC constraints as follows (which will LOC to a region and not a specific pin):

TL - Top LeftTR- Top RightRT- Right Side TopRB- Right Side BottomBR- Bottom RightBL- Bottom Left LB- Left Side BottomLT- Left Side Top

Using the above constraint allows the designer to ensure that all related I/Os and Clocks are located in the correct half of a bank (BUFIO2 clock region) during the first implementation run. After the first run, the constraints can then be fine-tuned based on the initial placement given by the tools.