PRUs are programmed in [http://en.wikipedia.org/wiki/Assembly_language Assembly], with most commands executing in a single cycle with no caching or pipe-lining, allowing for 100% predictable timings. At 200Mhz, a single cycle will always take 5ns (nanoseconds) to execute.

PRUs are programmed in [http://en.wikipedia.org/wiki/Assembly_language Assembly], with most commands executing in a single cycle with no caching or pipe-lining, allowing for 100% predictable timings. At 200Mhz, a single cycle will always take 5ns (nanoseconds) to execute.

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The documentation for this is [[file:spruh73c.pdf|here]]. TI does not support this subsystem and all questions/inquires/problems should be directed to the community.

====This is a Work In Progress====

====This is a Work In Progress====

Revision as of 08:51, 29 April 2013

The PRUSS (Programmable Real-time Unit Sub System) consists of two 32-bit 200MHz real-time cores, each with 8KB of program memory and direct access to general I/O.
These cores are connected to various data memories, peripheral modules and an interrupt controller for access to the entire system-on-a-chip via a 32-bit interconnect bus.

PRUs are programmed in Assembly, with most commands executing in a single cycle with no caching or pipe-lining, allowing for 100% predictable timings. At 200Mhz, a single cycle will always take 5ns (nanoseconds) to execute.

The documentation for this is File:Spruh73c.pdf. TI does not support this subsystem and all questions/inquires/problems should be directed to the community.

The current PRU loader uses UIO, but this ideally should be replaced with remoteproc rather than poking at the registers from userspace.

PRU to Host (PRU to ARM Cortex-A8)

Host to PRU (ARM Cortex-A8 to PRU)

Interrupts

Each PRU has access to host interrupt channels Host-0 and Host-1 through register R31 bit 30 and bit 31 respectively.
By probing these registers, a PRU can determine if an interrupt is currently present on each host channel.