[[PRUSSv2 Memory Map|Click here for a full list of register mappings.]]

[[PRUSSv2 Memory Map|Click here for a full list of register mappings.]]

Revision as of 12:36, 13 May 2013

The PRUSS (Programmable Real-time Unit Sub System) consists of two 32-bit 200MHz real-time cores, each with 8KB of program memory and direct access to general I/O.
These cores are connected to various data memories, peripheral modules and an interrupt controller for access to the entire system-on-a-chip via a 32-bit interconnect bus.

PRUs are programmed in Assembly, with most commands executing in a single cycle with no caching or pipe-lining, allowing for 100% predictable timings. At 200MHz, a single cycle most operations will take 5ns (nanoseconds) with exception of accessing memory external to PRU to execute.

PRU to Host (PRU to ARM Cortex-A8)

Host to PRU (ARM Cortex-A8 to PRU)

Interrupts

Each PRU has access to host interrupt channels Host-0 and Host-1 through register R31 bit 30 and bit 31 respectively.
By probing these registers, a PRU can determine if an interrupt is currently present on each host channel.

To configure

PRU to external peripherals

External peripherals to PRU

PRU to internal peripherals

Internal peripherals to PRU

Loading a PRU Program

Beaglebone PRU connections and modes

PRU #

R30(input) bit

Pinmux Mode

R31(output) bit

Pinmux Mode

BB Header

BB Pin Name

ZCZ BallName

Offset Reg

DT Offset

Input Mode

Output Mode

0

0

Mode_6

0

Mode_5

P9_31

SPI1_SCLK

mcasp0_aclkx

990h

0x190

0x06

0x25

0

1

Mode_6

1

Mode_5

P9_31

SPI1_D0

mcasp0_fsx

994h

0x194

0x06

0x25

0

2

Mode_6

2

Mode_5

P9_30

SPI1_D1

mcasp0_axr0

998h

0x198

0x06

0x25

0

3

Mode_6

3

Mode_5

P9_28

SPI1_CS0

mcasp0_ahclkr

99Ch

0x19C

0x06

0x25

0

4

Mode_6

4

Mode_5

P9_42

(*see note1 below)

mcasp0_aclkr

9A0h

0x1A0

0x06

0x25

0

5

Mode_6

5

Mode_5

P9_27

GPIO3_19

mcasp0_fsr

9A4h

0x1A4

0x06

0x25

0

6

Mode_6

6

Mode_5

P9_41

(*see note2 below)

mcasp0_axr1

9A8h

0x1A8

0x06

0x25

0

7

Mode_6

7

Mode_5

P9_25

GPIO3_21

mcasp0_ahclkx

9ACh

0x1AC

0x06

0x25

0

N/A

14

Mode_6

P8_12

GPIO1_12

gpmc_ad12

830h

0x030

NA

0x25

0

N/A

15

Mode_6

P8_11

GPIO1_13

gpmc_ad9

824h

0x024

NA

0x25

0

14

Mode_6

N/A

P8_16

GPIO1_14

gpmc_ad14

838h

0x038

0x06

NA

0

15

Mode_6

N/A

P8_15

GPIO1_15

gpmc_ad15

83Ch

0x03C

0x06

NA

0

16

Mode_6

N/A

P9_24

UART1_TXD

uart1_txd

984h

0x184

0x06

NA

1

0

Mode_6

0

Mode_5

P8_45

GPIO2_6

lcd_data0

8A0h

0x0A0

0x06

0x25

1

1

Mode_6

1

Mode_5

P8_46

GPIO2_7

lcd_data1

8A4h

0x0A4

0x06

0x25

1

2

Mode_6

2

Mode_5

P8_43

GPIO2_8

lcd_data2

8A8h

0x0A8

0x06

0x25

1

3

Mode_6

3

Mode_5

P8_44

GPIO2_9

lcd_data3

8ACh

0x0AC

0x06

0x25

1

4

Mode_6

4

Mode_5

P8_41

GPIO2_10

lcd_data4

8B0h

0x0B0

0x06

0x25

1

5

Mode_6

5

Mode_5

P8_42

GPIO2_11

lcd_data5

8B4h

0x0B4

0x06

0x25

1

6

Mode_6

6

Mode_5

P8_39

GPIO2_12

lcd_data6

8B8h

0x0B8

0x06

0x25

1

7

Mode_6

7

Mode_5

P8_40

GPIO2_13

lcd_data7

8BCh

0x0BC

0x06

0x25

1

8

Mode_6

8

Mode_5

P8_27

GPIO2_22

lcd_vsync

8E0h

0x0EO

0x06

0x25

1

9

Mode_6

9

Mode_5

P8_29

GPIO2_23

lcd_hsync

8E4h

0x0E4

0x06

0x25

1

10

Mode_6

10

Mode_5

P8_28

GPIO2_24

lcd_pclk

8E8h

0x0E8

0x06

0x25

1

11

Mode_6

11

Mode_5

P8_30

GPIO2_25

lcd_ac_bias_en

8ECh

0x0EC

0x06

0x25

1

12

Mode_6

12

Mode_5

P8_21

GPIO1_30

gpmc_csn1

880h

0x080

0x06

0x25

1

13

Mode_6

13

Mode_5

P8_20

GPIO1_31

gpmc_csn2

884h

0x084

0x06

0x25

1

16

Mode_6

N/A

P9_26

UART1_RXD

uart1_rxd

980h

0x180

0x06

NA

Note1: The PRU0 Registers{30,31} Bit 4 (GPIO3_18) is routed to P9_42-GPIO0_7 pin. You MUST set GPIO0_7 to input mode in pinmuxing.

Note2: The PRU0 Registers{30,31} Bit 6 (GPIO3_20) is routed to P9_41-GPIO0_20(CLKOUT2). You must set GPIO0_20 to input mode in pinmuxing.