Annonce

NB: The afternoon session will take place in Amphi Emeraude, TélécomParisTech.

Date and Place:

8th of June 2016, Télécom ParisTech, 46 rue Barrault, 75013 Paris:

morning: amphi Estaunié (88 seats);

afternoon : amphi Emeraude (148 seats)

Description:

Energy efficiency is a major issue in the design of modern communication systems. Information theory has widely investigated fundamental limits of communication over noisy channels under transmit power requirements. These fundamental limits led to the design of very efficient error-correction systems, such as LDPC and Turbo Codes. However, it was also observed empirically that processing power can sometimes dominate transmit power, especially for short distance communications.

One of the main current concerns is to design error-correction systems that minimize the total (transmit + process) energy consumption rather than just the transmit energy consumption. This concern has recently received increased attention from both academia and industrials, and the following two issues are being explored. First, from an information theoretic perspective, there is a need to also take into account processing energy, and to design error-correction systems that guarantee the transmission while minimizing the total energy consumption. Second, as the processing energy highly depends on the technology (voltage supply, 45nm or 65nm CMOS, etc.) and on the circuit architecture, there is a need to construct low energy consumption hardware implementations of error-correction systems. These two issues are highly related, since for example, hardware implementation could provide energy models to information theory, while fundamental limits could give insights for the implementation.

The objectives of the meeting will be to present the recent contributions on error-correction systems with low energy consumption, and to explore the connections between the information theory and hardware implementation issues.

Résumés des contributions

Complexity and Energy Efficiency of LDPC Decoders and an Initial Comparison to Polar Codes

In the first part of this talk, we will have a look at different architectures for LDPC decoders with very different performance requirements. To this end, we will systematically categorize architectures of existing decoder designs and discuss two examples in more detail. We will outline key architectural and implementation issues and show how to solve them and how to achieve low power consumption. In the second part of the talk, we will then consider Polar codes as a competing technology to LDPC codes. We will make an initial attempt to systematically compare the two types of codes (especially with respect to their decoder-implementation complexity), based on various implementations (our own and those in the literature).

Energy Optimization of quasi-synchronious LDPC decoders

Quasi-synchronous (QS) systems are systems based on synchronous circuits that experience occasional timing violations, and expose the resulting deviations to the system level. Optimizing the energy consumption of a QS system requires constructing a deviation model that represents the effect of timing violations on the system?s performance, and an energy model that captures the energy gains obtained by permitting these violations. We present a memoryless deviation model for QS LDPC decoders that is compatible with the assumption of codeword-independent errors while remaining accurate, and show how instances of the deviation-energy model can be constructed from a small number of Monte-Carlo simulations of a small test circuit. We can then use this model to find operating conditions that minimize the energy consumption of the decoder, subject to performance constraints and without increasing the size of the circuit. We describe an approximate optimization approach that provides a good sequence of operating conditions to be used in each decoding iteration, while guaranteeing that the solutions are feasible. Finally, we show how the finite-length performance and energy consumption of a QS decoder can be predicted for a specific average channel quality and maximum number of decoding iterations, and compare these predictions with the performance measured on the gate-level model of a decoder.

Non-Surjective Finite Alphabet Iterative Decoders

Speaker: Valentin Savin

In this talk we introduce a new theoretical framework, akin to the use of imprecise message storage in Low Density Parity Check (LDPC) decoders, which is seen as an enabler for cost-effective hardware designs. The proposed framework is the one of Non-Surjective Finite Alphabet Iterative Decoders (NS-FAIDs), and it is shown to provide a unified approach for several designs previously proposed in the literature. NS-FAIDs are optimized by density evolution for WiMAX irregular LDPC codes and we show they provide different trade-offs between hardware complexity and decoding performance. In particular, we derive a set of 27 NS-FAIDs that provide decoding gains up to 0.33 dB, while yielding a memory / interconnect reduction up to 25% / 30% compared to the Min-Sum decoder.

Energy efficiency of high-performance bit-flipping LDPC decoder ASICs

Speaker: Chris Winstead

Recent advances in LDPC decoding have revealed unexpectedly good performance for bit-flipping algorithms. Three important algorithm features are examined: noise enhancement, message memory and decoder rewinding (i.e. re-decoding). While the theory behind these features is still developing, empirical research has shown these methods to be important both for improved performance and reduced complexity. We discuss the architectural advantages and tradeoffs associated with these methods, and provide a review of recent ASIC results showing that bit-flipping decoders offer extremely low energy-per-bit and implementation area compared to traditional architectures.

New Techniques for Improved Decoding of Short LDPC Codes

Speaker: Stefan Scholl

LDPC codes are usually decoded by iterative belief propagation. However, especially for small block lengths it exhibits significant losses in coding gain compared to maximum likelihood decoding. An advanced decoding scheme is proposed, that combines several runs of belief propagation to improve the coding gain by up to 1.6 dB compared to sum-product decoding. Hardware architectures and implementation results for a 28 nm ASIC technology are presented. Besides the additional coding gain, the new decoder implementation copes with the great challenge of "dark silicon" currently arising in microelectronic systems.

Polar coding has attracted lots of attention in research and industry in recent years. Originally developed as a low complexity scheme to provably achieve capacity, polar coding also represents a flexible high-performance scheme for practical code lengths. Rate adaptation is naturally possibly by choosing frozen sets of different sizes; length adaptation, one the other hand, requires careful application of puncturing or shortening in order to ensure performance. Decoding is possible by simple and fast successive-cancellation (SC) decoding or by advanced SC list decoding, where list length and thus complexity may be traded against performance.

Due to its flexibility in terms of code rate, code length, performance and decoding complexity, polar coding is currently being discussed as a candidate coding scheme for 5G. The presentation will review the options for encoding and decoding of polar codes and relate them to complexity and energy efficiency of decoding algorithms and decoding implementations.

In this presentation, we introduce a new and original method for the random generation of bits in the Probabilistic Gradient-Descent Bit-Flipping (PGDBF) decoder, which provides a highly efficient hardware implementation compared to others conventional methods while preserving the outstanding decoding performance of PGDBF. This new random generator method called Intrinsic-Valued Random Generator (IVRG) avoids generating the required random bits by using a sequence of bits from the existing decoder memory. Moreover, we analyze through statistical analysis the behavior of the PGDBF and identify the important features of the random generators, which are important to obtain large coding gains compared to the deterministic GDBF. Our results show that the high PGDBF performance can be obtained with a very small extra hardware complexity, without any performance loss.

Progress in software implementations of ECC decoders

During the last decade, many works on software implementations of decoders for different error correction code families were proposed. Indeed, from an designer point of view, programmable architectures offer some flexibility during development cycle and also at runtime. However, their throughput and energy efficiencies were far from real time application constraints. Since about four years, multiple efficient throughput implementations for ECC decoding were proposed (LDPC, Turbocodes, Polar codes ...). Associated, first, with the drastic reduction of the power consumption of the programmable architectures (x86, GPU, ARM) and secondly, with the Software Defined Radio or Cloud-Ran systems, the interest of such solutions becomes a reality. Whereas their efficiency is always lower than dedicated hardware architectures (e.g. for handled devices), their real time usages in modern communication systems where short development time and flexibility matter (e.g. base stations or embedded systems) is possible. The presentation will review the progresses in the field of ECC decoding on programmable architectures by providing a state of the art of the current throughputs and energy consumptions. Then, future challenges and improvement ways will be discussed.