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Description

I am working on a project for an open source ASIC implemented with an open source EDA flow. This is a pilot project with long term goal to provide makers the possibility to make their own chips. For the pilot some classic CPUs from the nineties with an open source implementation will be used for a micro-controller. The project was presented at ORConf 2017; you can find the slides in the external links.

Project Logs

People who follow my project will have noticed that the crowdfunding campaign has come to an end. Unfortunately it did not reach it funding goal. Fortunately this does not mean the end (yet) for the Retro-uC and the Chips4Makers projects.

The technical stuff seems to finally converge to a phase that launching of the Retro-uC campaign is getting close. In the current state four product options are planned: a chip, a breadboardable board, a prototyping board and a stand-alone board with Arduino MEGA IO layout.

The details are given in my latest blog post. All feedback and suggestions for improvement are welcome here. Do realise I may only be able to reply when I'm back from FOSDEM next weekend.

I really hope to be able to report more technical things in the short term but I am focusing currently on getting the production flow ready and discussions are going slow. Some changes should pup op on the gitlab repository in the coming days/weeks.

It's also mentioned in the article that currently I am busy discussing the cost and the flow of the production run before officially launching the campaign. When this is finished I will be able to share more public information.

Again I like very much the idea. However, there are major flaws which prevent me from backing it. The price ($42+$8+possible toll taxes) and some features are lacking:- 3 cores but only one active for this price? I would rather take the genuine one.- no bus for external storage? I would rather take the genuine one.- speed less than 10MHz? I would rather take the genuine one (Z80: 20MHz, M68K: 25MHz).I don't see what I can do with it.

This is a good point ... No external memory bus means you can't do anything with it that demands attaching devices that either directly access memory or are themselves memory mapped. No graphical output (maybe you can make something text mode work, but bitmapped would be a huge issue), no high speed storage. You won't be able to make any standard OSs for any of the cores run, and the performance will be significantly worse than am AVR or PIC, which are about the only comparable modern architectures (although I wonder where the figure of 10MHz comes from ... simply implementing the simplest possible design for each core on a .35um process ought to result in much better speed than that; at that size I'd have hoped to see at least 30MHz for a Z80 core, although slightly less for the others as they do more per cycle).

Frankly, just using an FPGA would be easier and cheaper. And if open source design is important to you, there are RISCV systems available that tick that box.

The author answered it would be probably under 10MHz in a comment of the hackaday.io article. However, he never answered to my questions (the same as I posted here) - I asked through a CrowdSupply message and the article comments. So I decided to post here... We'll see whether his project reach the goal.

This is a low volume ASIC so the price is what it is. It will never be able to compete with proprietary, high volume chips. So it's up to you if like the Retro-uC enough to want to spend that money. It still does not cost an arm and a leg.

Originally I planned to have a different version for each core but it was easier to combine them on one chip without increased cost. On-chip RAM is big part of the cost.

I did go for microcontroller version of the chip with big number of I/O and not for microprocessor as these are indeed readily available.

I am going to look if I can implement an external SRAM interface that can optionally be enabled. But only when I have tested it successfully and I consider the risk on having a killer bug introduced in the chip minimal, I will add it to the chip.

In general I tried to limit the amount of features as each feature risks introducing a bug and if it is means the chip does not work all backers will loose their money.

I think I replied to reach speed above 10MHz. How far above needs to still be determined, I hope to be able to announce that before end of campaign.

PS: I did reply to your question asked through the campaign page so it seems to not have gone through your SPAM filter.

Thanks. Since you answered here, let us forget about the reply which might have not gone through my SPAM filter. Fine, I certainly mis-interpreted the 10MHz reach speed. I'm glad to hear your thinking about implementing an optional external SRAM interface for those needing one even if its addition is completely conditioned by a succesful test.

I was aware of the WDC parts and assumed there would also be Z80 uCs. But mine will be open source and it should be possible for people to in the future base their own MCU or even full computers chips on them.