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Abstract:

A method for providing a FinFET device with an air gap spacer includes
providing a substrate a plurality of fins and a dummy gate arranged
transverse to the plurality of fins; depositing a sacrificial spacer
around the dummy gate; depositing a first interlayer dielectric (ILD)
layer around the sacrificial spacer; selectively etching the dummy
polysilicon gate relative to the first ILD layer and the sacrificial
spacer; depositing a replacement metal gate (RMG); etching a portion of
the RMG to create a recess surrounded by the sacrificial spacer; and
depositing a gate capping layer in the recess. The gate capping layer is
at least partially surrounded by the sacrificial spacer and is made of
silicon oxycarbide (SiOC).

Claims:

1-30. (canceled)

31. A method for providing a FinFET device with an air gap spacer,
comprising: providing a substrate including a plurality of fins and a
dummy gate arranged transverse to the plurality of fins; depositing a
sacrificial spacer around the dummy gate; depositing a first interlayer
dielectric (ILD) layer around the sacrificial spacer; selectively etching
the dummy gate relative to the first ILD layer and the sacrificial
spacer; depositing a replacement metal gate (RMG); etching a portion of
the RMG to create a recess surrounded by the sacrificial spacer; and
depositing a gate capping layer in the recess, wherein the gate capping
layer is at least partially surrounded by the sacrificial spacer and is
made of silicon oxycarbide (SiOC).

32. The method of claim 31, wherein the gate capping layer is deposited
using a remote plasma process.

33. The method of claim 31, wherein the sacrificial spacer is made of
silicon nitride.

35. The method of claim 31, further comprising: etching the first ILD
layer around opposite ends of the plurality of fins to create recesses
for self-aligned contacts (SACs); and depositing the SACs in the
recesses.

36. The method of claim 35, wherein the depositing the SACs in the
recesses includes: depositing a barrier layer; and depositing a metal
layer.

37. The method of claim 36, wherein the barrier layer includes titanium
and titanium nitride layers.

38. The method of claim 36, wherein the barrier layer includes WCNx,
where x is an integer greater than zero.

39. The method of claim 35, wherein the SACs include a metal layer
including a material selected from a group consisting of tungsten (W) and
cobalt (Co).

40. The method of claim 35, further comprising removing the sacrificial
spacer by selectively etching the sacrificial spacer relative to the
first ILD layer, the gate capping layer, and the SACs to create an air
gap spacer.

41. The method of claim 40, further comprising depositing an air gap seal
in an upper portion of the air gap spacer.

42. The method of claim 41, wherein the air gap seal is made of at least
one of ILD, silicon dioxide, silicon dioxide with carbon doping and SiOC.

43. The method of claim 41, wherein the depositing the air gap seal
includes: depositing a seal layer on a top surface of the substrate; and
performing chemical mechanical polishing (CMP) of the seal layer to
define the air gap seal.

45. The method of claim 43, further comprising depositing an etch stop
layer on the substrate.

46. The method of claim 45, wherein the etch stop layer includes SiOC.

47. The method of claim 45, further comprising depositing a second ILD
layer on the etch stop layer.

48. The method of claim 47, further comprising etching portions of the
second ILD layer and the etch stop layer to open up selected portions of
underlying layers of the substrate.

49. The method of claim 31, wherein the dummy gate is made of
polysilicon.

50. A FinFET device comprising: a plurality of fins ; a source contact
arranged in contact with first ends of the plurality of fins; a drain
contact arranged in contact with second ends of the plurality of fins;
and a metal gate arranged between and spaced from the source contact and
the drain contact and in contact with the plurality of fins, wherein the
metal gate includes a gate capping layer made of silicon oxycarbide
(SiOC).

51. The FinFET device of claim 50, further comprising: a first interlayer
dielectric (ILD) layer; and an air gap located between the first ILD
layer and the metal gate, between the source contact and the gate and
between the drain contact and the gate.

52. The FinFET device of claim 51, further comprising an air gap seal
located in an upper portion of the air gap between the gate capping layer
and the first ILD layer, between the gate capping layer and the drain
contact and between the gate capping layer and the source contact.

53. The FinFET device of claim 52, wherein the air gap seal is made of a
material selected from a group consisting of ILD, silicon dioxide,
silicon dioxide doped with carbon, and silicon oxycarbide (SiOC).

54. The FinFET device of claim 52, further comprising an etch stop layer
arranged above the gate capping layer, the air gap seal and the first ILD
layer.

55. The FinFET device of claim 54, wherein the etch stop layer is made of
silicon oxycarbide (SiOC).

56. The FinFET device of claim 54, further comprising a second ILD layer
arranged above the etch stop layer.

57. A FinFET device comprising: a plurality of fins; a source contact in
contact with first ends of the plurality of fins; a drain contact in
contact with second ends of the plurality of fins; a metal gate arranged
between and spaced from the source contact and the drain contact and in
contact with the plurality of fins; a first interlayer dielectric (ILD)
layer; and an air gap located between the first ILD layer and the metal
gate, between the source contact and the gate and between the drain
contact and the gate.

58. The FinFET device of claim 57, further comprising a gate capping
layer formed on the metal gate.

59. The FinFET device of claim 58, wherein the gate capping layer is made
of silicon oxycarbide (SiOC).

60. The FinFET device of claim 58, further comprising an air gap seal
located in an upper portion of the air gap between the gate capping layer
and the first ILD layer, between the gate capping layer and the drain
contact and between the gate capping layer and the source contact.

61. The FinFET device of claim 60, wherein the air gap seal is made of a
material selected from a group consisting of ILD, silicon dioxide,
silicon dioxide doped with carbon, and silicon oxycarbide (SiOC).

62. The FinFET device of claim 60, further comprising an etch stop layer
arranged above the gate capping layer, the air gap seal and the first ILD
layer.

63. The FinFET device of claim 62, wherein the etch stop layer is made of
silicon oxycarbide (SiOC).

64. The FinFET device of claim 62, further comprising a second ILD layer
arranged above the etch stop layer.

Description:

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application
No. 62/065,284, filed Oct. 17, 2014. The entire disclosure of the
application referenced above is incorporated herein by reference.

FIELD

[0002] The present disclosure relates to methods for processing
substrates, and more particularly to methods for integrating air gap
spacers in FinFET devices.

BACKGROUND

[0003] The background description provided here is for the purpose of
generally presenting the context of the disclosure. Work of the presently
named inventors, to the extent it is described in this background
section, as well as aspects of the description that may not otherwise
qualify as prior art at the time of filing, are neither expressly nor
impliedly admitted as prior art against the present disclosure.

[0004] Referring now to FIG. 1A, a FinFET device 10 is shown to include a
source region 14 and a drain region 18 arranged on one or more underlying
layers 12. Source contact 20 extends in a vertical direction from the
source region 14 to a source contact 22 arranged in a horizontal plane
above the source region 14. Drain contact 28 extends in a vertical
direction from the drain region 18 to a drain contact 30 arranged in a
horizontal plane above the drain region 18. Gate regions 34 and 38 are
arranged between the source region 14 and the drain region 18. A
plurality of fins 40 extends transverse to the gate regions 38 between
the source region 14 and the drain region 18.

[0005] Referring now to FIG. 1B, parasitic capacitance of the FinFET
device 10 limits AC performance. Some of the parasitic capacitances are
illustrated in FIG. 1B. A first parasitic capacitance C1 occurs between
the source contact 22 and the drain contact 30. A second parasitic
capacitance C2 occurs between the source/drain contacts 20, 22, 28 and 30
and gate 38. A third parasitic capacitance C3 occurs between the gate
regions 34 and 38 and the source/drain regions 14 and 18. A fourth
parasitic capacitance C4 occurs between the source contact 20 and the
drain region 18.

[0006] Spacer materials having a relatively low dielectric constant (k)
have been proposed to reduce parasitic capacitance. For example, a
silicon nitride (SiN) spacer with a dielectric constant ˜7.5 has
been used. Although other spacer materials have been proposed with lower
dielectric constants (k˜5 or less), the improvement is incremental.

SUMMARY

[0007] A method for providing a FinFET device with an air gap spacer
includes providing a substrate including a plurality of fins and a dummy
gate arranged transverse to the plurality of fins; depositing a
sacrificial spacer around the dummy gate; depositing a first ILD layer
around the sacrificial spacer; selectively etching the dummy gate
relative to the first ILD layer and the sacrificial spacer; depositing a
replacement metal gate (RMG); etching a portion of the RMG to create a
recess surrounded by the sacrificial spacer; and depositing a gate
capping layer in the recess. The gate capping layer is at least partially
surrounded by the sacrificial spacer and is made of silicon oxycarbide
(SiOC).

[0008] In other features, the gate capping layer is deposited using a
remote plasma process. The sacrificial spacer is made of silicon nitride.
The method includes performing chemical mechanical polishing (CMP) of the
gate capping layer.

[0009] In other features, the method includes etching the first ILD layer
around opposite ends of the plurality of fins to create recesses for
self-aligning contacts (SACs) and depositing the SACs in the recesses.
The depositing the SACs in the recesses includes depositing a barrier
layer and depositing a metal layer.

[0010] In other features, the barrier layer includes titanium and titanium
nitride layers. The barrier layer includes WCNx, where x is an
integer greater than zero. The SACs include a metal layer including a
material selected from a group consisting of tungsten (W) and cobalt
(Co).

[0011] In other features, the method includes removing the sacrificial
spacer by selectively etching the sacrificial spacer relative to the
first ILD layer, the gate capping layer, and the SACs to create an air
gap spacer. The method includes depositing an air gap seal in an upper
portion of the air gap spacer. The air gap seal is made of at least one
of ILD, silicon dioxide, silicon dioxide with carbon doping and SiCO. The
depositing the air gap seal includes depositing a seal layer on a top
surface of the substrate; and performing chemical mechanical polishing
(CMP) of the seal layer to define the air gap seal.

[0012] In other features, the seal layer is deposited using
plasma-enhanced chemical vapor deposition. The method includes depositing
an etch stop layer on the substrate. The etch stop layer includes SiCO.
The method includes depositing a second ILD layer on the etch stop layer.
The method includes etching portions of the second ILD layer and the etch
stop layer to open up selected portions of underlying layers of the
substrate.

[0013] A FinFET device includes a plurality of fins. A source contact is
arranged in contact with first ends of the plurality of fins. A drain
contact is arranged in contact with second ends of the plurality of fins.
A metal gate is arranged on the underlying layer between and spaced from
the source contact and the drain contact and in contact with the
plurality of fins. The metal gate includes a gate capping layer made of
silicon oxycarbide (SiOC).

[0014] In other features, an air gap is located between a first interlayer
dielectric (ILD) layer and the metal gate, between the source contact and
the gate and between the drain contact and the gate. An air gap seal is
located in an upper portion of the air gap between the gate capping layer
and the first ILD layer, between the gate capping layer and the drain
contact and between the gate capping layer and the source contact. The
air gap seal is made of a material selected from a group consisting of
ILD, silicon dioxide, silicon dioxide doped with carbon, and silicon
oxycarbide (SiOC).

[0015] In other features, an etch stop layer is arranged above the gate
capping layer, the air gap seal and the first ILD layer. The etch stop
layer is made of silicon oxycarbide (SiOC).

[0016] In other features, a second ILD layer is arranged above the etch
stop layer.

[0017] A FinFET device includes a plurality of fins. A source contact is
arranged in contact with first ends of the plurality of fins. A drain
contact is arranged in contact with second ends of the plurality of fins.
A metal gate is arranged between and spaced from the source contact and
the drain contact and in contact with the plurality of fins. An air gap
is located between first interlayer dielectric (ILD) layer and the metal
gate, between the source contact and the gate and between the drain
contact and the gate.

[0018] In other features, a gate capping layer is formed on the metal
gate. The gate capping layer is made of silicon oxycarbide (SiOC). An air
gap seal is located in an upper portion of the air gap between the gate
capping layer and the first ILD layer, between the gate capping layer and
the drain contact and between the gate capping layer and the source
contact. The air gap seal is made of a material selected from a group
consisting of ILD, silicon dioxide, silicon dioxide doped with carbon,
and silicon oxycarbide (SiOC).

[0019] In other features, an etch stop layer is arranged above the gate
capping layer, the air gap seal and the first ILD layer. The etch stop
layer is made of silicon oxycarbide (SiOC). A second ILD layer is
arranged above the etch stop layer.

[0020] Further areas of applicability of the present disclosure will
become apparent from the detailed description, the claims and the
drawings. The detailed description and specific examples are intended for
purposes of illustration only and are not intended to limit the scope of
the disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The present disclosure will become more fully understood from the
detailed description and the accompanying drawings, wherein:

[0022] FIG. 1A is a perspective view illustrating a FinFET device
according to the prior art;

[0024] FIG. 2 is a perspective view illustrating an example of a substrate
including a plurality of fins after shallow trench isolation (STI) recess
etch according to the present disclosure;

[0025] FIG. 3 is a perspective view illustrating an example of the
substrate including a dummy gate according to the present disclosure;

[0026] FIG. 4 is a perspective view illustrating an example of the
substrate including a sacrificial spacer deposited around the dummy gate
according to the present disclosure;

[0027] FIG. 5 is a perspective view illustrating an example of the
substrate after the dummy gate is removed and interlayer dielectric (ILD)
is deposited around the sacrificial spacer according to the present
disclosure;

[0028] FIG. 6 is a perspective view illustrating an example of the
substrate including a replacement metal gate (RMG) according to the
present disclosure;

[0029] FIG. 7 is a perspective view illustrating an example of the
substrate after a recess is etched in the RMG according to the present
disclosure;

[0030] FIG. 8 is a perspective view illustrating an example of the
substrate after a gate capping layer is deposited in the recess according
to the present disclosure;

[0031] FIG. 9 is a perspective view illustrating an example of the
substrate after chemical mechanical polishing (CMP) of the gate capping
layer according to the present disclosure;

[0032] FIG. 10 is a perspective view illustrating an example of the
substrate after etching oxide to incorporate a Self-Aligned Contact (SAC)
scheme adjacent to opposite ends of the fins according to the present
disclosure;

[0033] FIG. 11 is a perspective view illustrating an example of the
substrate after filling the SACs with metal according to the present
disclosure;

[0034] FIG. 12 is a perspective view illustrating an example of the
substrate after removing the sacrificial spacer according to the present
disclosure;

[0035] FIG. 13 is a perspective view illustrating an example of the
substrate after deposition of a seal layer over an air gap according to
the present disclosure;

[0036] FIG. 14 is a perspective view illustrating an example of the
substrate after CMP is performed on the seal layer to create an air gap
seal according to the present disclosure;

[0037] FIG. 15 is a perspective, cross-sectional view illustrating an
example of the substrate, the air gap seal and a gap below the air gap
seal according to the present disclosure;

[0038] FIG. 16 is a perspective, cross-sectional view illustrating an
example of an etch stop layer and an ILD layer after deposition according
to the present disclosure;

[0039] FIGS. 17A, 17B, 18A, 18B, and 19 are perspective, cross-sectional
views illustrating various examples of the substrates after processing
steps are used to open up the substrate to various sub-layers of the
substrate according to the present disclosure; and

[0040] FIG. 20 is a method for creating an air gap spacer for a FinFET
device according to the present disclosure.

[0041] In the drawings, reference numbers may be reused to identify
similar and/or identical elements.

DETAILED DESCRIPTION

[0042] The present disclose relates to FinFET devices with air gap spacers
and methods for integrating air gap spacers into FinFET devices. Air gap
spacers are formed using a sacrificial spacer during integration. The
sacrificial spacer is subsequently removed after self-aligned
source/drain contact formation. The air gap spacer reduces FinFET
parasitic capacitance. Low parasitic capacitance can be achieved without
loss of process window or relaxing of lithography overlay requirements.

[0043] Referring now to FIGS. 2-3, the substrate is shown after shallow
trench isolation (STI) recess etch and dummy gate formation,
respectively. In FIG. 2, the substrate 100 includes an ILD layer 110 and
a plurality of fins 114. The ILD layer 110 may be made of low k
dielectrics, doped oxides, flowable oxides, silicon dioxide (SiO2)
or other suitable material. In some examples, the plurality of fins 114
may be made of silicon (Si) with intervening STI oxide. STI oxide may
also be located on a top surface of the plurality of fins 114.

[0044] In FIG. 3, a dummy gate 118 is deposited over the plurality of fins
114 and etched. In some examples, the dummy gate 118 is arranged on the
ILD layer 110 and extends transverse to the plurality of fins 114. In
some examples, the dummy gate 118 is made of polysilicon. A hardmask
layer 122 may be used to mask the dummy gate 118 during etching.

[0045] Referring now to FIGS. 4-5, a sacrificial spacer is deposited and
etched and the dummy gate is removed, respectively. In FIG. 4, a
sacrificial spacer 128 is deposited around an outer surface of the dummy
gate 118 and etched. In some examples, the sacrificial spacer 128 is made
of silicon nitride (SiN). In FIG. 5, ILD layer 132 is deposited around
the sacrificial spacer 128. In addition, the dummy gate 118 and the
hardmask layer 122 are removed by etching or ashing. In some examples,
the silicon forming the dummy gate 118 is selectively etched relative to
the silicon nitride (SiN) and the silicon dioxide (SiO2) material of
the substrate 100.

[0046] In FIG. 6, replacement metal gate (RMG) formation is shown. A
replacement metal gate (RMG) 138 is deposited in a former location of the
dummy gate 118. In some examples, the RMG 138 has a high dielectric (HK)
constant in a predetermined thickness between 1 and 10 nm. In some
examples, the RMG 138 is made of high dielectric constant materials such
as hafnium oxide (HfO2), HfSiO2, aluminum oxide
(Al2O3), zirconium oxide (ZrO2) or titanium oxide
(TiO2); a metal work function-setting material such as titanium
nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride
(WNx) (where x is an integer), tungsten carbon nitride (WCNx),
cobalt (Co), or other metals; and a bulk conductive metal such as
tungsten (W), Cobalt (Co) or aluminum (Al) and alloys thereof. In some
examples, chemical mechanical polishing (CMP) may be performed after
deposition of the RMG 138. In some examples, the top surface of the RMG
138 is coplanar with a top surface of the sacrificial spacer 128 and the
ILD layer 132 after CMP.

[0047] Referring now to FIG. 7, the RMG 138 is selectively and partially
etched relative to the silicon nitride (SiN) and the silicon dioxide
(SiO2). More particularly, the RMG 138 is partially and selectively
etched in a downward direction relative to the top surfaces of the
sacrificial spacer 128 and the ILD layer 132 to create a recess 139 in
the RMG 138. A top surface 141 of the RMG 138 is located below a plane
including the top surfaces of the sacrificial spacer 128 and the ILD
layer 132.

[0048] Referring now to FIGS. 8-9, gate capping layer deposition and gate
capping layer chemical mechanical polishing (CMP) are shown,
respectively. In FIG. 8, a gate capping layer 144 is deposited in the
recess in the RMG 138 and on the top surface of the substrate 100. In
some examples, the gate capping layer 144 may be made of silicon
oxycarbide (SiOC) or another suitable material. In some examples, the
gate capping layer layer 144 is deposited using a process as described in
commonly-assigned U.S. patent application Ser. No. 13/494,836, entitled
"Remote Plasma Based Deposition of SiOC Class Films", which was filed on
Jun. 12, 2012, which is hereby incorporated by reference in its entirety.
In some examples, the gate capping layer 144 is deposited using a remote
plasma process described therein.

[0049] In FIG. 9, CMP of the gate capping layer 144 is performed to create
a gate capping layer 145 to the RMG 138. In some examples, the top
surface of the gate capping layer 145 is coplanar with a top surface of
the sacrificial spacer 128 and the ILD layer 132 after the CMP.

[0050] Referring now to FIGS. 10-12, self-alignment contact (SAC) etch,
SAC fill and sacrificial spacer removal are shown, respectively. In FIG.
10, areas of the ILD layer 132 surrounding opposite sides of the
plurality of fins 114 are masked and etched using an etch which etches
ILD selective to the gate capping layer and sacrificial spacer to expose
the plurality of fins 114 and to create a self-aligned contact area. In
FIG. 11, the self-aligned contact area is filled with SAC material 152.
In some examples, the SAC material 152 includes metal layers 153 or
barrier layers 153 and metal layers 155 deposited on the barrier layers
153. In some examples, the barrier layers 153 include a titanium (Ti) and
titanium nitride (TiN) bilayer and the metal layers 155 include tungsten
(W), although other materials can be used, such as WCNx for the
barrier and Co for the metal layer. In FIG. 12, the sacrificial spacer
128 is removed.

[0051] For example, etching of the sacrificial spacer 128 may be a
selective etching of silicon nitride relative to the other exposed
materials. The etching may be wet or dry etching. In some examples, the
silicon nitride is etched using a process described in commonly-assigned
U.S. patent application Ser. No. 14/676,710, filed on Apr. 1, 2015 and
entitled "Method for Achieving Ultra-High Selectivity While Etching
Silicon Nitride", which is hereby incorporated by reference in its
entirety. In some examples, the silicon nitride is etched using a process
described in in commonly-assigned U.S. Patent Provisional Application
Ser. No. 62/241,827, filed on Oct. 15, 2015 and entitled "Systems and
Methods for Ultrahigh Selective Nitride Etch", which is hereby
incorporated by reference in its entirety.

[0052] Referring now to FIGS. 13-15, a seal layer is deposited on the
substrate and CMP is performed to create an air gap spacer. In FIG. 13, a
seal layer 156 is deposited on a top surface of the substrate 100. During
deposition, an upper portion of an air gap 159 created after the
sacrificial spacer 128 is removed is at least partially filled by the
seal layer 156. In some examples, the seal layer 156 is made of ILD,
silicon dioxide (SiO2), SiO2 with carbon doping, or silicon
oxycarbide (SiOC). In some examples, the seal layer 156 is deposited
using plasma enhanced chemical vapor deposition (PECVD), although other
deposition processes may be used.

[0053] In some examples, the seal layer 156 includes SiOC that is
deposited using plasma enhanced chemical vapor deposition as described in
commonly-assigned U.S. patent application Ser. No. 13/494,836, entitled
"Remote Plasma Based Deposition of SiOC Class Films", which was filed on
Jun. 12, 2012, which is hereby incorporated by reference in its entirety.
In some examples, a bread loaf effect occurs in a top portion of the air
gap to pinch off the air gap.

[0054] In FIG. 14, CMP is used to remove a portion of the seal layer 156
located on the top surface of the substrate 100 to create an air gap seal
157. In some examples, the top surface of the air gap seal 157 is
coplanar with a top surface of the SAC 145 and the ILD layer 132 after
CMP. In FIG. 15, a cross-section of the substrate taken along a plane
parallel to and spaced from the plurality of fins 114 is shown. The air
gap 159 is located below the air gap seal 157.

[0055] Referring now to FIG. 16, an etch stop layer 164 is deposited on
the top surface of the substrate 100. In some examples, the etch stop
layer 164 includes SiOC, although other materials may be used. In some
examples, the SiOC is deposited as described in commonly-assigned U.S.
patent application Ser. No. 13/494,836, entitled "Remote Plasma Based
Deposition of SiOC Class Films", which was filed on Jun. 12, 2012, which
is hereby incorporated by reference in its entirety. ILD layer 166 is
deposited on the etch stop layer 164.

[0056] Referring now to FIGS. 17A-19, various different etching steps are
performed to open up different portions of the substrate. In FIGS.
17A-17B, an example of various etch steps are shown. In FIG. 17A, the ILD
layer 166 is etched to selectively expose underlying layers in a portion
190 of the etch stop layer 164. In FIG. 17B, the etch stop layer 164 is
etched to open up portions of the SAC 145, the air gap seal 157, the
metal layers 155 and the ILD layer 132 for further processing.

[0057] In FIGS. 18A and 18B, the ILD layer 166 and the etch stop layer 164
are etched to selectively expose underlying layers in portions 192 of the
substrate 100. In FIG. 18B, different portions of the air gap seal 157,
the metal layers 155 and the ILD layer 132 are opened up for further
processing.

[0058] In FIG. 19, the ILD layer 166 is patterned and etched to expose
underlying layers in portions 198 and 200 of the substrate 100. Portions
of the air gap seal 157, the metal layers 155, the RMG 138 and the ILD
layer 132 are opened up for further processing. As can be appreciated,
various other sublayers may be opened up for further processing.

[0059] Referring now to FIG. 20, a method 300 for creating an air gap
spacer for a FinFET device is shown. At 304, the substrate is provided
with an ILD layer and a plurality of fins. At 308, a dummy poly gate is
deposited. At 312, a sacrificial spacer is deposited around the dummy
poly gate and an ILD layer is deposited around the sacrificial spacer. At
314, the dummy poly gate is removed. At 320, a replacement metal gate
(RMG) is deposited. At 322, a recess is etched into a portion of the
(RMG). At 326, a recess on top of the RMG is filled with a gate capping
layer. At 328, CMP is performed on the gate capping layer. At 332,
self-aligning contacts (SAC) are etched around the plurality of fins. At
336, the SACs are filled with barrier layers and metal layers. At 338,
the sacrificial spacer is removed to create an air gap. At 342, air gap
spacer material is deposited in part of the gap area formally occupied by
the sacrificial spacer. At 348, an etch stop layer and an ILD layer are
deposited on the substrate. At 350, the ILD and etch stop layers are
selectively opened in portions thereof to allow further connections to
and processing of underlying layers of the substrate.

[0060] The foregoing description is merely illustrative in nature and is
in no way intended to limit the disclosure, its application, or uses. The
broad teachings of the disclosure can be implemented in a variety of
forms. Therefore, while this disclosure includes particular examples, the
true scope of the disclosure should not be so limited since other
modifications will become apparent upon a study of the drawings, the
specification, and the following claims. It should be understood that one
or more steps within a method may be executed in different order (or
concurrently) without altering the principles of the present disclosure.
Further, although each of the embodiments is described above as having
certain features, any one or more of those features described with
respect to any embodiment of the disclosure can be implemented in and/or
combined with features of any of the other embodiments, even if that
combination is not explicitly described. In other words, the described
embodiments are not mutually exclusive, and permutations of one or more
embodiments with one another remain within the scope of this disclosure.

[0061] Spatial and functional relationships between elements (for example,
between modules, circuit elements, semiconductor layers, etc.) are
described using various terms, including "connected," "engaged,"
"coupled," "adjacent," "next to," "on top of," "above," "below," and
"disposed." Unless explicitly described as being "direct," when a
relationship between first and second elements is described in the above
disclosure, that relationship can be a direct relationship where no other
intervening elements are present between the first and second elements,
but can also be an indirect relationship where one or more intervening
elements are present (either spatially or functionally) between the first
and second elements. As used herein, the phrase at least one of A, B, and
C should be construed to mean a logical (A OR B OR C), using a
non-exclusive logical OR, and should not be construed to mean "at least
one of A, at least one of B, and at least one of C."