Title (fr)

Publication

Application

Priority

JP 36946798 A 19981225

Abstract (en)

For a verify operation using potential Vbi', the data of a memory cell (M1 through M16) is preliminarily read by using potential Vai+1 and the state of the memory cell is stored in a latch circuit. Then, a verify/read operation is conducted by using potential Vbi'. If the state of the cell is higher than Ai+1, the outcome of the verify/read operation is forcibly brought down to a low level. Thus, only two latch circuits (LAT(A), LAT(B)) are required for storing an n-bit data, including one for storing the data to be written and one for preliminarily reading if the state of the cell is higher than Ai+1 or not and storing the outcome of the preliminary reading. <IMAGE>