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2. Generate embedded ICAP in HDL for IPROG generation for Spartan-6 FPGA device with following BitGen options: A. For Golden Bitstream: i. In Configuration Option, a) Select SPI Bus width to 4 b) Set Watch Dog timer to 0x1FFF c) Set MultiBoot address to 0x0200000 d) Select Next_Config_new_mode e) Select -g reset_on_err check box f) For MultiBoot Next configuration mode, set the value to 001 (SPI mode)and the Golden address to 0x000044 ii. All other options are default, especially the Configuration clock source which should be CCLK and not JTAG CCLK with Drive Done as a HIGH

B. For MultiBoot bitstream: i. Add BitGen option "-g next_config_register_write:Disable" in Other BitGen Command line options in Project navigator BitGen process properties in General options. ii. For Configuration option: a) Deselect the option - "place MultiBoot settings into Bitstream" b) Select SPIO bus width to by 1 c) Also watchdog settings to 0x1FFF d) Select -g reset_on_err check box iii. All other options are default, especially Configuration clock source should be CCLK and not JTAG CCLK with Drive Done pin as HIGH iv. If you desire a header to be generated with the Multiboot image then you can select SPIO bus width to by 4. Typically no Header is desired for the Multiboot bitstream, since all Register values (Mode_Reg, Gen1-5) are defined by the Golden Header file.