+static void intel_clovertown_quirks(void)+{+ /*+ * PEBS is unreliable due to:+ *+ * AJ67 - PEBS may experience CPL leaks+ * AJ68 - PEBS PMI may be delayed by one event+ * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]+ * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS+ *+ * AJ67 could be worked around by restricting the OS/USR flags.+ * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.+ *+ * AJ106 could possibly be worked around by not allowing LBR+ * usage from PEBS, including the fixup.+ * AJ68 could possibly be worked around by always programming+ * a pebs_event_reset[0] value and coping with the lost events.+ *+ * But taken together it might just make sense to not enable PEBS on+ * these chips.+ */+ printk(KERN_WARNING "PEBS disabled due to CPU errata.\n");+ x86_pmu.pebs = 0;+ x86_pmu.pebs_constraints = NULL;+}+ static __init int intel_pmu_init(void) { union cpuid10_edx edx;@@ -856,6 +882,7 @@ static __init int intel_pmu_init(void) break;