Abstract: The characteristic of trap assisted conduction and interface states for a Pd/TiO2/SiO2/SiC
structure has been investigated at temperatures up to 500 °C. Thermally oxidized Ti/SiO2 gate
capacitors fabricated by dry oxidation in O2 were studied. The electrical measurements show the
current conduction through this capacitor structure is controlled by a trap assisted conduction
mechanism at low bias and the barrier height (φA) between the metal and the TiO2 was extracted.
The current density in the dielectric stacks is also shown to be strongly temperature dependent. The
results demonstrate that the formation of a charge dipole under the Pd contact is responsible for
barrier height and not any changes in the behaviour of the TiO2 film itself, such as a change in
concentration of trapping centres. The reported results indicate electron trapping property across the
SiO2 layer is consistent with fitting experimental results to the trap assisted conduction model.

Abstract: Al2O3 grown by Atomic Layer Chemical Vapour Deposition (ALCVD) on n-type 4H-SiC
with a nominal thickness of 100nm has been characterized by Grazing Incidence X-Ray Diffraction
(GIXD) and Specular X-Ray Reflectivity (SXR) measurements. After post-deposition, the samples
were annealed at different temperatures and durations in argon atmosphere. The GIXD results reveal
crystallization at temperatures above 900°C, most likely in the form of θ-Al2O3 or γ-Al2O3.
However, the formation of a new, non-stoichiometric Al2O3 phase cannot be excluded. The
crystalline domain size, evaluated from the peak FWHMs after subtraction of the instrumental
broadening, is found to be almost equal (18±1nm), independent of T in the range 900°C≤T≤1100°C
and time in the range 1h≤t≤3h. From SXR, mass density profiles are derived. Whereas the as grown
film exhibits the lowest mass density, at 800°C a low-density interface layer forms. At the same
time, it appears that the initial crystallization starts at the surface. At 900°C, the density increases
sharply (this process involves film crystallization) and the film thickness correspondingly reduces.
Whereas the density increase and thickness reduction still continue for T>900°C (tendency to the
density α-Al2O3), the density of the interfacial layer has a minimum at 900°C and gradually
increases for higher temperatures. From Atomic Force Microscopy (AFM) investigations it could be
revealed that the starting of the crystallization at 900°C is accompanied with a substantial surface
roughening. For annealing at higher temperatures, the surface roughness is in the range of the one of
the as-grown sample (about 6Å).

Abstract: The last three years have seen a rapid growth of 600 V and 1200 V SiC Schottky diodes
primarily in the Power Factor Correction (PFC) circuits. The next logical step is introduction of a
SiC MOSFET to not only further improve the power density and efficiency of the PFC circuits but
also to enable the entry of all SiC power modules in Pulse Width Modulated (PWM) based power
converters such as motor control in 600-1200 V range. The combination of SiC MOSFET and
Schottky diodes will offer 60-80% lower losses in most low voltage applications at normal
operating temperatures (< 200°C) where no significant improvements in packaging are required.
This will cover most commercial applications with the exception of those having to function under
extreme environment (>200°C) such as applications in automotive, aerospace and oil/gas
exploration. For these high temperature applications, a case can be made for 600 - 2000 V Bipolar
Junction Transistors (BJTs) and PiN diodes provided we do our homework on high temperature
packaging. A number of interesting device related problems persist in bipolar devices such as
forward voltage increase in PiN diodes and current gain degradation in BJTs. For very high voltage
(>10 kV) applications such as those found in utilities (Transmission and Distribution), Large Drives
and Traction, a case can be made for >10 kV PiN diodes, IGBTs, Thyristors and GTOs. While
IGBTs will be restricted to <200°C junction temperature, the PiN diodes, Thyristors and GTOs may
be operated at >250°C junction temperature provided that the high temperature, high voltage
packaging issues are also addressed. Significant progress has been made in the development of the
p-channel IGBTs and GTOs. The main issues seem to be the VF degradation due to stacking fault
formation and improvement of minority carrier life-time.

Abstract: Employing density functional theory we investigate the model interface between
1 × 1-6H-SiC{0001} surfaces and graphene layers. We find that the first graphene layer is
covalently bonded to the SiC substrate, opposing the earlier assumption of a weak van-der-Waals
bonding. The interface at the Si-face is metallic, while on the C-face it remains semiconducting.
Further graphene layers are then only weakly bound and the typical graphitic properties of the
electronic structure appear.

Abstract: In this work, we have investigated triple and innovative multiple stacked contacts onto ptype
SiC in order to evaluate whether or not there is any improvement in morphology or specific
contact resistivity. The stacked metal contacts are based on Al, Ti and Ni with the specific contact
resistivity measured at a low value of 5.02×10-6'cm2 for an Al(100 nm)/Ti(100 nm)/Al(10 nm)
(where a “/” indicates the deposition sequence) triple stacked metal contact. XRD microstructural
analysis and SEM measurements have been carried out and it has been discovered that the contacts,
which formed the compound Ti3SiC2 at the metal/SiC interface, more readily display low-resistance
ohmic characteristics after a post deposition anneal. Although the same amount of Ti (100 nm in
total) has been deposited closer to the metal/SiC interface, none of the multiple stacked structures
displayed ohmic behaviour after a post deposition anneal.

Abstract: We have studied the electronic structure of the interface between 6H-SiC{0001} and
graphite. On n-type and p-type 6H-SiC(0001) we observe Schottky barriers of ÁSi
b,n = 0.3±0.1
eV and ÁSi
b,p = 2.7±0.1 eV, respectively. The observed barrier is face specific: on n-type 6H-
SiC(0001) we find ÁC
b,n = 1.3±0.1 eV. The impact of these barriers on the electrical properties
of metal/SiC contacts is discussed.

Abstract: The specific contact resistance of Al, Ti and Ni ohmic contacts to N+ implanted
3C-SiC(100) has been investigated by means of TLM method. The p-type epitaxial layer grown on n+
substrate is multiply implanted with N ions with energy ranging from 15 to 120 keV at a total dose of
1.4×1015 cm-2 at room temperature and is subsequently annealed by RF annealer at a temperature of
1400 oC for 10 min in Ar gas flow, resulting in the sheet resistance of 130 0/sq. The deposited Al
layer on the annealed sample shows the extremely low specific contact resistance of about
1×10-7 0cm2. The ohmic contacts of Ti and Ni also show the specific contact resistance of 5×10-6
and 2×10-5 0cm2, respectively. The obtained specific contact resistance is proportional to the
Schottky barrier height of metal cotact to n-type 3C-SiC. The annealing of Ni ohmic contact
above 600 oC results in the considerable reduction of specific contact resistance due to the
silicidation of Ni.

Abstract: In this paper a novel approach to the design and fabrication of a high temperature inverter module
for hybrid electrical vehicles is presented. Firstly, SiC power electronic devices are considered in place of the
conventional Si devices. Use of SiC raises the maximum practical operating junction temperature to well over
200°C, giving much greater thermal headroom between the chips and the coolant. In the first fabrication, a
SiC Schottky barrier diode (SBD) replaces the Si pin diode and is paired with a Si-IGBT. Secondly, doublesided
cooling is employed, in which the semiconductor chips are sandwiched between two substrate tiles. The
tiles provide electrical connections to the top and the bottom of the chips, thus replacing the conventional wire
bonded interconnect. Each tile assembly supports two IGBTs and two SBDs in a half-bridge configuration. Both
sides of the assembly are cooled directly using a high-performance liquid impingement system. Specific features
of the design ensure that thermo-mechanical stresses are controlled so as to achieve long thermal cycling
life. A prototype 10 kW inverter module is described incorporating three half-bridge sandwich assemblies, gate
drives, dc-link capacitance and two heat-exchangers. This achieves a volumetric power density of 30W/cm3.

Abstract: This study deals with the interfacial reactions and electrical properties of Ta/4H-SiC
contacts. Tantalum thin films (~100 nm) were deposited onto SiC wafer at room temperature by
argon ion beam sputtering. The samples were then heated in high vacuum at 650°C, 800°C or
950°C for 30 min. X-ray photoelectron spectroscopy (XPS), glancing angle X-ray diffraction
(XRD), Auger electron spectroscopy (AES) and current-voltage (I-V) technique were used for
characterising the samples. Ohmic contact is formed in the studied samples after annealing at or
above 800°C even though considerable amount of metallic Ta still exists. The reaction zone
possesses a layered structure of Ta2C/Ta2C+Ta5Si3/SiC. High enough temperature is needed to
provide for sufficient interface change to tailor the contact properties.

Abstract: We investigated how surface roughness, intentionally induced by chemical-mechanical
polishing, affects the formation of ohmic contacts to an n-type 4H-SiC using a common circular
transmission length method (CTLM). Nickel metal was used as the cathode ohmic contacts to n-type
SiC. The specific contact resistance (SCR) for the un-polished sample (F1) and polished samples (F2
and F3) was 5.4 × 10-3 ⋅cm2 and 4.2 × 10-3 ⋅cm2, respectively. We found out that the un-polished
sample (F1) had much higher SCR than the samples , F2 and F3. In addition, we did not see any
difference between the differently polished samples, F2 and F3, indicating that there was no
dependence on the face type of SiC (Si- or C-face) in the values of SCR. We also investigated the
die-bonding processes with the surface roughness and metallization schemes' effects.