What’s After CMOS?

Chipmakers continue to scale the CMOS transistor to finer geometries, but the question is for how much longer. The current thinking is that the CMOS transistor could scale at least to the 3nm node in the 2021 timeframe. And then, CMOS could run out of gas, prompting the need for a new switch technology.

So what’s after the CMOS-based transistor? Carbon nanotubes and graphene get the most attention. Over time, the industry could migrate towards stacked-die or monolithic 3D devices. All told, there are nearly 20 viable next-generation transistor candidates on the table, although there is a possibility that CMOS may prevail over the long term.

Surprisingly, based on the latest performance benchmarks from Intel, carbon nanotubes, graphene or even 3D devices failed to make the cut. Conducted in the lab, Intel’s benchmarks are based on throughput, power consumption and other criteria. In simple terms, the most promising devices on Intel’s current list are narrowed down to five technologies—spin-majority gate; spin-wave devices; III-V tunnel field-effect transistors (TFETs); heterojunction TFETs; and graphene nanoribbon (GNR) TFETs.

TFETs are attractive because they are steep sub-threshold slope devices, and an evolutionary step from today’s MOSFETs. The spin-based, or nano-magnetic, technologies are intriguing because they are nonvolatile logic devices.

Intel’s list isn’t set in stone and could easily change. Others may have different ideas. For example, on Imec’s list for the ultimate next-generation switch, the R&D organization currently identifies two technologies right now—the heterojunction TFET and GNR TFET.

In any case, the benchmarks provide a clue where the industry is heading if or when CMOS hits the wall. “There are a lot of research projects in the industry,” said Mark Bohr, a senior fellow and director of process architecture and integration at Intel. “The problem is that many of these projects are not applying rigorous benchmarks.”

The idea behind Intel’s benchmarks is to narrow down the potential choices based on known criteria, Bohr said. “As an industry, we just don’t have enough money to fund all projects,” he added.

Clearly, the development of a next-generation switch will require new materials and fab tools. But even with substantial funding and new breakthroughs, it’s still unclear when the next-generation switch will appear. “They are not that far along to predict an insertion point,” said Thomas Theis, executive director at the Nanoelectronics Research Initiative (NRI), a program at the Semiconductor Research Corp. (SRC). “And it’s certainly too early to pick the winners. But optimistically, I can see some version of tunnel FETs in 10 years. But I am not ready to say that about the nano-magnetic devices.”

Narrowing the choices
In 2005, the SRC launched the NRI, a group that is researching futuristic devices capable of replacing the CMOS transistor by 2020. The NRI include GlobalFoundries, IBM, Intel, Micron, TI and several universities.

Generally, today’s MOSFETs are limited to 60-millivolt per decade swing, making them difficult to scale below 0.5 volts. Seeking a technology that will break this barrier, the NRI is exploring technologies in four basic categories—charged (CMOS, TFET); electric dipole (FeFET); magnetic (spin devices); and orbital state (BisFET). Researchers are also exploring carbon nanotubes, graphene and other technologies.

Most of the next-generation technologies share the same problems. “The principles don’t need to be invented,” said Theis, who is on assignment from IBM. “But none of these technologies actually exist right now in a laboratory as a voltage switch device. That will be a major breakthrough when somebody puts a voltage on one of these technologies and gets it to switch.”

The challenges and costs, according to some experts, could push out the development of a next-generation switch at least for several decades. “Not every change is worth doing,” said Chenming Hu, a professor at the University of California at Berkeley. “Regarding things that go beyond CMOS, we are really talking about 2030 or 2040 or so.”

Considered the father of the finFET, Hu believes that CMOS will likely last much longer and for good reason. Chip-manufacturing and design costs are becoming astronomical. And to get a return, chipmakers could extend the CMOS nodes beyond the traditional two-year cycle. “A pattern is emerging at the 28nm node,” Hu said. “The big difference is that the nodes will last longer. 28nm could be the sweet spot for a long time.”

Some chipmakers have or will soon migrate from planar transistors to finFETs. Today’s silicon-based finFETs will scale to 10nm. Then, at 7nm, finFETs may require new and costly III-V channel materials. “I don’t think the industry will migrate from 14nm to 10nm and to 7nm so quickly,” Hu said. “Once finFET costs come down, the 10nm node will be the sweet spot for a long, long time.”

Regarding 2.5D/3D stacked-die, Hu said the technology is still too expensive for mainstream applications. “It helps with the performance and power, but let’s not forget about cost,” he added.

What’s next?
Still others believe that the industry will require a next-generation switch sooner than later. The prevailing wisdom is that a futuristic technology must have many of the same characteristics as today’s CMOS logic devices.

Based on this criteria alone, the industry has eliminated many of the more exotic candidates—domain wall ring; electron structure modulation FET; excitonic FET; and graphene thermal transistor. However, the industry is still taking a hard look at the following technologies—all spin logic; BisFET; graphene pn junction; spin FET; spin majority gate; spin torque triad; spin torque oscillators; spin wave devices; and the TFET.

Based on the benchmarks from Imec and Intel, the TFET is showing the most promise. Aimed for the 5nm node, the TFET is a gated-diode that makes use of an electron tunneling technology. TFETs can break the 60-millivolt per decade swing barrier at room temperature. “The problem with TFETs is that they have a smaller on-current than the MOSFET,” said Dmitri Nikonov, a research scientist at Intel.

In its benchmarks, Intel lists three types of TFETs. The heterojunction TFET and III-V TFET are somewhat similar, as they use different materials for the PFET and NFET. Recently, Imec described a heterojunction vertical TFET using a germanium-source-on-silicon technology. “Going vertical gives us advantages,” said Aaron Thean, director of the logic program at Imec. “We can selectively convert any of the silicon pillars and grow different types of devices using this method.”

The third TFET, the GNR TFET, utilizes p-doped GNR as the source and n-doped GNR as the drain. The GNR TFET promises to achieve steep sub-threshold slopes, but the challenges include the fabrication of the GNR material.

“New materials like graphene and carbon nanotubes look attractive,” said An Chen, senior member of the technical staff at GlobalFoundries. “But consider the integration challenges with CMOS. For real applications, we need to look at systems instead of just devices with interesting materials and structures. So, for that reason, I don’t think we will see a CMOS replacement. The industry will be building a better system based on the CMOS platform. That means you still have CMOS, but you build more functionality on top of that.”

Chen is more optimistic about a potential TFET technology described by Pennsylvania State University. In that work, Penn State described a 32-core structure that combines CMOS and TFET transistors in the same device. “I think that looks more likely,” he said. “One core could be TFET-based. One core could be CMOS-based. CMOS is doing more of the high-performance things. The TFETs are doing low power things.”

Like Intel, IBM, Imec and others, Chen is also bullish about spin-based logic, which falls into the broad categories of spintronics or nano-magnetics. The technology is associated with MRAM, but it can be extended to logic. “In spin, you don’t need to move electrons. You just flip the spin. In this idea, spintronics would consume lower power, because you are not moving anything like electrons,” Chen said.

Spin-based logic is also attractive because it combines the switching speeds of logic and the non-volatility of memory. “When you shut the power down, and you bring it back up, every device in the logic circuit is still in its state,” NRI’s Theis said. “That might also lead into new approaches in re-configurability. Right now, re-configurability means FPGAs. With spin-based devices, we can explore new ways to get the same kind of function.”

There are also some challenges, however. “The switching speeds are limited by the dynamics of spin, which is pretty fundamental,” Theis said. “I believe you have to re-invent these devices quite a bit.”

There are several types of spin-based technologies, but the most promising one is the spin majority gate device. This technology consists of a gate based on magnetic materials. Vertical nano-pillars, which sit on top of the gate, switch the magnetism in the bottom layer.

“The idea is that you use a spin torque. All of the inputs come in. The magnetism is added together and then the majority wins. And that gives you a majority function,” GlobalFoundries’ Chen said. Spin majority gate provides a steep sub-threshold slope, but the problem is that it has a relatively small on-current performance.

A related technology, the spin wave device, uses a wave of spins within a ferroelectric material to transfer information. The AC current causes an input magnetization to oscillate, which propagates a spin wave. “It’s nonvolatile, but we ready haven’t explored what kind of circuit architectures and applications we need for that kind of logic,” NRI’s Theis said.

Another technology, all spin logic, is also the subject of interest. “All spin logic has gain,” Theis said. “That means you have isolation between input and output. That means you design logic along the confines that a conventional logic circuit designer can understand.”

Spin-based devices, TFETs and the other next-generation technologies are clearly fascinating. But based on the challenges, it’s unclear if the industry will meet its stated goal of developing a viable next-generation switch by 2020. By then, it might be too expensive to design and make devices based on the new technologies, leaving many to believe that CMOS will rule the roost for the foreseeable future.

[…] What’s after CMOS? That link provides a nice, timely summary of the increasingly not-straightforward world of transistor scaling. The first point I make, or at least agree with, is that you need to apply rigorous benchmarks when looking at all of these potential transistor technologies. This means getting a candidate transistor into realistic (below the 10nm node) horizontal and vertical dimensions, with realistic parasitics, construct a realistic circuit out of them, and then and only then measure their relative effectiveness. Case in point: high mobility channels. They receive a ton of attention, but bulk mobility doesn’t translate directly to microprocessor performance. Take germanium, which seems to be battling it out with RRAM for total domination of the IEDM conference. Our group at ARM recently performed some detailed predictive modeling of Germanium for PFETs, and in our study, which we have submitted for publication, we found that with realistic gate lengths, gate oxides, etc., most of the mobility gain was lost. Then, adding in effects of the smaller band gap, which include increased leakage and variability, we didn’t come up with a very encouraging conclusion. Many of the same issues apply to translating large-dimension benefits of compound semiconductors to the nanometer regime. TFETs are another hot topic, but they not only need to find a lot more drive current, they need to be realistically de-rated for what will almost certainly be increased variation. A possible interesting scenario for TFETs would be if they could be integrated in a low cost manner alongside other higher performance FETs. That doesn’t seem entirely out of the question. […]