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Abstract:

A solid-state image sensor which holds a potential for a long time and
includes a thin film transistor with stable electrical characteristics is
provided. When the off-state current of a thin film transistor including
an oxide semiconductor layer is set to 1×10-13 A or less and
the thin film transistor is used as a reset transistor and a transfer
transistor of the solid-state image sensor, the potential of the signal
charge storage portion is kept constant, so that a dynamic range can be
improved. When a silicon semiconductor which can be used for a
complementary metal oxide semiconductor is used for a peripheral circuit,
a high-speed semiconductor device with low power consumption can be
manufactured.

Claims:

1. A semiconductor device comprising: a pixel portion over a substrate
comprising a silicon semiconductor, the pixel portion comprising: a
photoelectric conversion element portion buried in the substrate; a
transfer transistor electrically connected to the photoelectric
conversion element portion; a signal charge storage portion electrically
connected to the transfer transistor; a reset transistor electrically
connected to the signal charge storage portion; an amplifier transistor
electrically connected to the signal charge storage portion; and wherein
a channel formation region of the transfer transistor and a channel
formation region of the reset transistor comprise an oxide semiconductor
and a channel formation region of the amplifier transistor comprises the
silicon semiconductor.

2. The semiconductor device according to claim 1, wherein the transfer
transistor or the reset transistor is formed over the amplifier
transistor.

3. The semiconductor device according to claim 1, wherein off-state
current of each of the transfer transistor and the reset transistor is
1.times.10.sup.-13 A or less.

4. The semiconductor device according to claim 1, wherein a carrier
concentration in the oxide semiconductor is lower than
1.times.10.sup.14/cm.sup.3.

5. The semiconductor device according to claim 1, wherein the pixel
portion is electrically connected to a peripheral circuit portion
including a complementary transistor having a silicon semiconductor in a
channel formation region.

6. The semiconductor device according to claim 1, wherein the signal
charge storage portion includes an insulating layer as a dielectric.

7. An electronic device comprising the semiconductor device according to
claim 1.

Description:

TECHNICAL FIELD

[0001] One embodiment of the present invention relates to a semiconductor
device including a field-effect transistor formed using an oxide
semiconductor.

[0002] Note that in this specification, a semiconductor device refers to
all devices that can function by utilizing semiconductor properties, and
electro-optic devices, semiconductor circuits, and electronic devices are
all semiconductor devices.

BACKGROUND ART

[0003] A technique for forming a thin film transistor with the use of a
semiconductor thin film formed over a substrate having an insulating
surface has attracted attention. A silicon-based semiconductor material
has been known as a semiconductor thin film applicable to a thin film
transistor. As another material, an oxide semiconductor has attracted
attention.

[0004] As oxide semiconductor materials, zinc oxide and a substance
containing zinc oxide have been known. In addition, a thin film
transistor formed using an amorphous oxide (an oxide semiconductor) whose
carrier (electron) concentration is lower than 1018/cm3 has
been disclosed (References 1 to 3).

[0009] In solid-state image sensors which need excellent electrical
characteristics, although they have structures similar to those of
display devices, field-effect transistors formed using SOI substrates or
bulk single crystal silicon substrates are generally used.

[0010] However, it cannot be said that field-effect transistors formed
using single crystal silicon have ideal electrical characteristics. For
example, off-state current (also referred to as leakage current or the
like) is not low enough to be regarded as substantially zero. Further,
the temperature characteristic of silicon is comparatively greatly
changed. In particular, the off-state current of silicon is likely to
change. Therefore, in the case where a charge retention semiconductor
device such as a solid-state image sensor is formed, it is hoped that a
device capable of holding a potential for a long time regardless of the
surrounding environment and having lower off-state current will develop.

[0011] In view of the foregoing problems, it is an object of one
embodiment of the disclosed invention to provide a solid-state image
sensor including a thin film transistor with stable electrical
characteristics (e.g., significantly low off-state current).

[0012] One embodiment of the present invention is a solid-state image
sensor which includes at least a photoelectric conversion element and an
amplifier transistor formed using silicon semiconductors and includes a
pixel where a reset transistor and a transfer transistor are formed using
an oxide semiconductor.

[0013] An oxide semiconductor in one embodiment of the present invention
is a semiconductor which is an intrinsic or substantially intrinsic
semiconductor by removal of an impurity that might be an electron donor
and has a larger energy gap than a silicon semiconductor.

[0014] In other words, in one embodiment of the present invention, a
solid-state image sensor including a thin film transistor whose channel
formation region is formed using an oxide semiconductor film is formed.
In the oxide semiconductor film, hydrogen or an O--H group contained in
an oxide semiconductor is removed so that the concentration of hydrogen
in the oxide semiconductor is 5×1019/cm3 or lower,
preferably 5×1018/cm3 or lower, more preferably
5×1017/cm3 or lower or lower than
1×1016/cm3 as the lowest value measured by secondary ion
mass spectroscopy (SIMS), and the carrier concentration is lower than
1×1014/cm3, preferably 1×1012/cm3 or
lower.

[0015] The energy gap of the oxide semiconductor is 2 eV or higher,
preferably 2.5 eV or higher, more preferably 3 eV or higher. An impurity
such as hydrogen, which forms donors, is reduced as much as possible. The
carrier concentration is set to 1×1014/cm3 or lower,
preferably 1×1012/cm3 or lower.

[0016] When such a highly purified oxide semiconductor is used for a
channel formation region of a thin film transistor, the thin film
transistor has an electrical characteristic of normally off. At a drain
voltage of 1 to 10 V, the off-state current of the thin film transistor
is 1×10-13 A or less or 100 aA/μm (μm indicates the
channel width of the thin film transistor) or less, preferably 10
aA/μm or less, more preferably 1 aA/μm or less.

[0017] One embodiment of the present invention disclosed in this
specification is a semiconductor device which includes a photoelectric
conversion element portion buried in a silicon semiconductor substrate, a
signal charge storage portion electrically connected to the photoelectric
conversion element portion through a transfer transistor, a reset
transistor electrically connected to the signal charge storage portion,
and an amplifier transistor whose gate electrode is electrically
connected to the signal charge storage portion. The semiconductor device
further includes a pixel portion where a channel formation region of the
transfer transistor and a channel formation region of the reset
transistor are formed using an oxide semiconductor and a channel
formation region of the amplifier transistor is formed using a silicon
semiconductor.

[0018] In addition, the amplifier transistor may be a thin film transistor
including an oxide semiconductor. Further, a selection transistor may be
provided in the pixel portion. Furthermore, in a peripheral circuit
portion connected to the pixel portion, a complimentary transistor is
preferably formed using a bulk transistor including a silicon
semiconductor.

[0019] In this specification and the like, terms such as "electrode" and
"wiring" do not limit the functions of components. For example, an
"electrode" can be used as part of a "wiring", and the "wiring" can be
used as part of the "electrode". In addition, the terms such as
"electrode" and "wiring" can also mean a combination of a plurality of
"electrodes" and "wirings", for example.

[0020] In addition, an "SOI substrate" is not limited to a semiconductor
substrate such as a silicon wafer, and may be a non-semiconductor
substrate such as a glass substrate, a quartz substrate, a sapphire
substrate, or a metal substrate. In other words, the "SOI substrate" also
includes, in its category, an insulating substrate over which a layer
formed using a semiconductor material is provided. Further, in this
specification and the like, a "semiconductor substrate" means not only a
substrate formed using only a semiconductor material but also all
substrates including semiconductor materials. That is, in this
specification and the like, the "SOI substrate" is also included in the
category of the "semiconductor substrate".

[0021] According to one embodiment of the present invention, the potential
of a signal charge storage portion can be kept constant when a thin film
transistor which includes an oxide semiconductor and has significantly
low off-state current is used as a reset transistor and a transfer
transistor, so that a dynamic range can be improved. Further, when a
silicon semiconductor which can be used for a complementary transistor is
used for a peripheral circuit, a high-speed semiconductor device with low
power consumption can be manufactured.

BRIEF DESCRIPTION OF DRAWINGS

[0022] In the accompanying drawings:

[0023]FIG. 1 is a cross-sectional view illustrating a structure of a
pixel of a solid-state image sensor;

[0028]FIG. 6 is a graph illustrating Vg-Idcharacteristics of a
thin film transistor including an oxide semiconductor;

[0029] FIGS. 7A and 7B are photographs of a thin film transistor including
an oxide semiconductor;

[0030] FIGS. 8A and 8B are graphs illustrating
Vg-Idcharacteristics (temperature characteristics) of a thin
film transistor including an oxide semiconductor;

[0031]FIG. 9 is a longitudinal cross-sectional view of an inverted
staggered thin film transistor including an oxide semiconductor;

[0032] FIGS. 10A and 10B are energy band diagrams (schematic views) in an
A-A' cross section in FIG. 9;

[0033] FIG. 11A is an energy band diagram (a schematic view) in a B-B'
cross section in FIG. 9 that illustrates a state in which a positive
potential (+VG) is applied to a gate (G1), and FIG. 11B is an energy band
diagram (a schematic view) in the B-B' cross section in FIG. 9 that
illustrates a state in which a negative potential (-VG) is applied to the
gate (G1);

[0034]FIG. 12 illustrates a relationship among a vacuum level, a work
function (φM) of a metal, and electron affinity (χ) of an
oxide semiconductor;

[0035]FIG. 13 illustrates a structure of a pixel of a solid-state image
sensor;

[0036]FIG. 14 illustrates operation of the pixel of the solid-state image
sensor;

[0051] Embodiments of the present invention will be described in detail
with reference to the drawings. Note that the present invention is not
limited to the following description, and it will be readily appreciated
by those skilled in the art that modes and details of the present
invention can be changed in various ways without departing from the
spirit and scope of the present invention. Therefore, the present
invention should not be construed as being limited to the following
description of the embodiments. Note that in structures of the present
invention described below, the same portions or portions having similar
functions are denoted by the same reference numerals in different
drawings, and description thereof is not repeated.

[0052] Note that in each drawing described in this specification, the size
of each component or each region, layer thickness, and the like are
exaggerated for clarity in some cases. Therefore, embodiments of the
present invention are not limited to such scales.

[0053] Note that in this specification, terms such as "first", "second",
and "third" are used in order to avoid confusion among components and do
not limit the order or the like. Therefore, for example, the term "first"
can be replaced with the term "second", "third", or the like as
appropriate.

Embodiment 1

[0054] One embodiment of the present invention is a semiconductor device
including a metal insulator semiconductor element called a MIS (metal
insulator semiconductor) transistor. In this specification, an element
whose channel formation region is formed using a thin film semiconductor
is referred to as a thin film transistor, and an element whose channel
formation region is formed using a bulk semiconductor is referred to as a
bulk transistor. Note that a semiconductor layer formed using an SOI
(silicon on insulator) substrate can be referred to as a thin film, and a
transistor including the semiconductor layer is a kind of bulk transistor
in this specification.

[0055] An example where a pixel of a solid-state image sensor including a
thin film transistor in one embodiment of the present invention is
provided is described below. In this embodiment, as an example, a thin
film transistor included in the pixel of the solid-state image sensor, a
photoelectric conversion element connected to the thin film transistor,
and a bulk transistor formed using a silicon semiconductor are described.
Note that a pixel refers to an element group including elements (e.g., a
photoelectric conversion element, a transistor, and a wiring) provided in
the solid-state image sensor and an element used for outputting an image
by input and output of electrical signals.

[0056] Note that the pixel can have a structure where incident light
enters a photoelectric conversion element 608 through a lens 600, a color
filter 602, an interlayer insulating film 606, and the like which are
formed on the substrate surface side as illustrated in a cross-sectional
view in FIG. 28A. Note that as indicated by a region surrounded with a
dotted frame, some of light paths indicated by arrows are blocked by some
of wiring layers 604 in some cases. Thus, the pixel may have a structure
where incident light efficiently enters a photoelectric conversion
element 618 by the formation of a lens 610 and a color filter 612 on the
substrate rear surface side as illustrated in FIG. 28B.

[0057] Further, when it is described that "A and B are connected to each
other", the case where A and B are electrically connected to each other
and the case where A and B are directly connected to each other are
included. Here, each of A and B is an object (e.g., a device, an element,
a circuit, a wiring, an electrode, a terminal, a conductive film, or a
layer).

[0058]FIG. 1 is a cross-sectional view illustrating an example of a pixel
part of a solid-state image sensor which is one embodiment of the present
invention. FIG. 1 illustrates an example in which a thin film transistor
including an oxide semiconductor is used as a transfer transistor 101 and
a reset transistor 121. An amplifier transistor 131 is formed using an
n-channel bulk transistor formed using a single crystal silicon substrate
100. A photoelectric conversion element 110 is a photodiode including an
n-type region 112 and a thin p-type region 114 and is connected to a
source electrode 104 of the transfer transistor 101. A signal charge
storage portion 116 (also referred to as a floating diffusion) is formed
below a drain electrode of the transfer transistor 101 and a source
electrode of the reset transistor. The transfer transistor 101 and the
reset transistor 121 each have a top-gate structure where an oxide
semiconductor layer serves as a channel region. A drain electrode 106 of
the transfer transistor 101 is electrically connected to a source
electrode 124 of the reset transistor. The amplifier transistor 131 is an
n-channel bulk transistor including n-type regions 132a and 132b and a
gate electrode 138. Although not illustrated, the gate electrode 138 of
the amplifier transistor is electrically connected to the signal charge
storage portion 116.

[0059] Note that in the structure illustrated in FIG. 1, a gate insulating
layer 136 of the bulk transistor serves as a base insulating layer of the
transfer transistor 101 and the reset transistor 121 which are thin film
transistors, and the signal charge storage portion 116 forms a capacitor
with the gate insulating layer 136 used as a dielectric. In addition, a
gate insulating layer 118 of the thin film transistor functions as part
of an interlayer insulating layer of the bulk transistor.

[0060] The thin film transistor including an oxide semiconductor in a
channel formation region is described as the top-gate thin film
transistor as an example; however, the thin film transistor may be a
bottom-gate thin film transistor such as an inverted staggered thin film
transistor. In addition, it is necessary to irradiate the photoelectric
conversion element 110 with light, so that an example is described in
which part of the source electrode of the transfer transistor 101 is
connected to a light reception portion of the photoelectric conversion
element 110; however, the source electrode may be formed using a
light-transmitting conductive material so as to be connected to the
photoelectric conversion element 110 in a different way. For example, as
illustrated in FIG. 2A, when a transistor 201 including a source
electrode 204 which is formed using a light-transmitting conductive
material is used as the transfer transistor, the source electrode can be
connected to part or all of a light reception portion of a photoelectric
conversion element 210. Alternatively, as illustrated in FIG. 2B, in
order to secure a light path for a photoelectric conversion element 310,
a transistor 301 where a source electrode 304 and a drain electrode 306
formed using a low-resistant metal layer and buffer layers 305 and 307
formed using a light-transmitting conductive material layer are stacked
may be used as the transfer transistor.

[0061] As the photoelectric conversion element, a so-called buried
photodiode where an n-type region is formed using a p-type single crystal
silicon substrate (in the case of an SOI, a p-type single crystal silicon
layer) and a thin p-type region is formed thereover is formed. By the
formation of the p-type region on a surface of the photodiode, dark
current (i.e., noise) generated on the surface can be reduced.

[0062] Although an example where a single crystal semiconductor substrate
is used is described above, an SOI substrate may be used. In addition,
the structure of the bulk transistor is not limited to the above
structure. An LDD (lightly doped drain) structure where sidewalls are
provided at ends of a gate electrode or a structure where low-resistant
silicide or the like is formed in part of a source region or a drain
region may be employed.

[0063] A selection transistor which is electrically connected to the
amplifier transistor 131 may be provided in the pixel portion. The
amplifier transistor and the selection transistor can be formed using
either a silicon semiconductor or an oxide semiconductor. Note that the
amplifier transistor is preferably formed using a bulk transistor
including a silicon semiconductor layer having a higher amplification
factor.

[0064] Alternatively, an insulating layer can be formed over the bulk
transistor and a thin film transistor can be formed thereover. For
example, when the transfer transistor formed using a thin film transistor
or the reset transistor is provided over the amplifier transistor formed
using a bulk transistor, the area of the transistor needed per pixel is
about two thirds, so that the integration level can be improved, a light
reception area can be increased, and noise can be reduced. FIG. 3A
illustrates an example of such a structure. A transfer transistor 401
formed using a thin film transistor and an amplifier transistor 431
formed using a bulk transistor are provided, and a reset transistor 421
formed using a thin film transistor is formed thereover with an
insulating layer 441 provided therebetween. Further, in FIG. 3B, a
photoelectric conversion element 510 and an amplifier transistor 531
formed using a bulk transistor are formed as a lower layer, and a
transfer transistor 501 formed using a thin film transistor and a reset
transistor 521 are formed as an upper layer with an insulating film 541
therebetween. A step of forming the photoelectric conversion element and
the bulk transistor and a step of forming the thin film transistor can be
separated from each other; thus, the steps can be controlled easily. Note
that a capacitor electrode 540 used for forming a signal charge storage
portion 516 is preferably provided.

[0065] With a combination of the thin film transistor and the bulk
transistor having the above structures, the signal charge storage portion
can hold a potential for a longer time and a pixel portion of a
solid-state image sensor having a wide dynamic range can be formed. Note
that in order to realize this embodiment of the present invention, a thin
film transistor whose off-state current is significantly low is
preferably used. A method for manufacturing such a thin film transistor
is described below.

[0066] In one embodiment of the present invention, a pixel portion of a
solid-state image sensor is formed with a combination of a bulk
transistor including a single crystal silicon semiconductor and a thin
film transistor including an oxide semiconductor having significantly
favorable electrical characteristics. Therefore, a method for forming the
thin film transistor including an oxide semiconductor is mainly described
in detail.

[0067] As an example, a method for forming the structure illustrated in
FIG. 1 is described with reference to cross-sectional views in FIGS. 4A
to 4C and FIGS. 5A to 5C. First, an element formation region isolated
with an insulating film 140 (also referred to as a field oxide film) is
formed over a p-type single crystal silicon substrate 100. The element
isolation region can be formed by local oxidation of silicon (LOCOS),
shallow trench isolation (STI), or the like.

[0068] Here, the substrate is not limited to the single crystal silicon
substrate. An SOI (silicon on insulator) substrate or the like can be
used.

[0069] Note that in this embodiment, a p-type single crystal silicon
substrate is used because a buried photodiode and an n-channel bulk
transistor are used; however, an n-type single crystal silicon substrate
can be used when a p-well is formed.

[0070] Next, the gate insulating layer 136 is formed so as to cover the
element formation region. For example, a silicon oxide film can be formed
by oxidation of a surface of the element formation region provided in the
single crystal silicon substrate 100 with heat treatment. Alternatively,
the gate insulating layer 136 may have a layered structure of a silicon
oxide film and a silicon oxynitride film by the formation of the silicon
oxide film by thermal oxidation and nitriding of a surface of the silicon
oxide film by nitriding treatment.

[0071] As another method, for example, by oxidation treatment or nitriding
treatment with high-density plasma treatment performed on the surface of
the element formation region provided in the single crystal silicon
substrate 100, a silicon oxide film or a silicon nitride film can be
formed as the gate insulating layer 136. Further, after oxidation
treatment is performed on the surface of the element formation region by
high-density plasma treatment, nitriding treatment may be performed by
high-density plasma treatment. In this case, a silicon oxide film is
formed on and in contact with the surface of the element formation region
and a silicon oxynitride film is formed over the silicon oxide film, so
that the gate insulating layer 136 has a layered structure of the silicon
oxide film and the silicon oxynitride film.

[0072] Next, a conductive layer is formed so as to cover the gate
insulating layer 136. Here, a conductive layer 138a and a conductive
layer 138b are sequentially stacked. Needless to say, the conductive
layer may have a single-layer structure or a layered structure including
two or more layers.

[0073] The conductive layers 138a and 138b can be formed using an element
selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum
(Mo), aluminum (Al), copper (Cu), chromium (Cr), or niobium (Nb), or an
alloy material or a compound material containing the element as its main
component. Alternatively, a metal nitride film obtained by nitriding of
the above element can be used. Alternatively, a semiconductor material
typified by polycrystalline silicon doped with an impurity element such
as phosphorus can be used.

[0074] Here, a layered structure is employed in which the conductive layer
138a is formed using tantalum nitride and the conductive layer 138b is
formed thereover using tungsten. Alternatively, a single layer of
tungsten nitride, molybdenum nitride, or titanium nitride or stacked
films thereof can be used as the conductive layer 138a, and a single
layer of tantalum, molybdenum, or titanium or stacked films thereof can
be used as the conductive layer 138b.

[0075] Next, by selectively etching and removing the conductive layers
138a and 138b which are stacked, the conductive layers 138a and 138b are
partly left over the gate insulating layer 136 so that the gate electrode
138 is formed.

[0076] Next, a resist mask is selectively formed so as to cover regions
except the element formation region, and impurity regions of the n-type
regions 132a and 132b are formed by introduction of an impurity element
with the use of the resist mask and the gate electrode 138 as masks.
Here, since the n-channel bulk transistor is formed, an impurity element
imparting n-type conductivity (e.g., phosphorus (P) or arsenic (As)) can
be used as the impurity element.

[0077] Then, in order to form a photodiode that is a photoelectric
conversion element, a resist mask is selectively formed. First, after a
pn junction is formed by introduction of an impurity element imparting
n-type conductivity (e.g., phosphorus (P) or arsenic (As)) into the
p-type single crystal silicon substrate, an impurity element imparting
p-type conductivity (e.g., boron (B)) is introduced into a surface layer
in the n-type region; thus, the buried photodiode can be formed.

[0078] At this stage, the structures of the bulk transistor illustrated on
the right of FIG. 4A and the photodiode illustrated on the left of FIG.
4A are completed.

[0079] Next, a method for forming a thin film transistor in which an oxide
semiconductor layer is used as a channel region is described.

[0080] In this embodiment, a thin film transistor is formed over the gate
insulating layer 136 of the bulk transistor which has been provided on
the single crystal silicon substrate 100. That is, the gate insulating
layer 136 can serve as a base film of the thin film transistor and the
gate insulating layer of the bulk transistor. Note that an insulating
layer may be formed by the following method and stacked layers may be
used as a base film.

[0081] As the insulating layer which is in contact with the oxide
semiconductor layer, an oxide insulating layer such as a silicon oxide
layer, a silicon oxynitride layer, an aluminum oxide layer, or an
aluminum oxynitride layer is preferably used. As a method for forming the
insulating layer, plasma-enhanced CVD, sputtering, or the like can be
used. In order that a large amount of hydrogen be not contained in the
insulating layer, the insulating layer is preferably formed by
sputtering.

[0082] An example is described in which a silicon oxide layer is formed as
the insulating layer by sputtering. The silicon oxide layer is deposited
over the single crystal silicon substrate 100 as the insulating layer in
such a manner that the single crystal silicon substrate 100 is
transferred to a treatment chamber, a sputtering gas containing
high-purity oxygen from which hydrogen and moisture are removed is
introduced, and a silicon target is used. In addition, the single crystal
silicon substrate 100 may be at room temperature or may be heated.

[0083] For example, the silicon oxide layer is deposited by RF sputtering
under the following condition: quartz (preferably synthetic quartz) is
used as a target; the temperature of the substrate is 108° C.; the
distance between the substrate and a target (the T-S distance) is 60 mm;
the pressure is 0.4 Pa; the high-frequency power is 1.5 kW; the
atmosphere contains oxygen and argon (an oxygen flow rate of 25 sccm: an
argon flow rate of 25 sccm=1:1); and the thickness is 100 nm Instead of
quartz, silicon can be used as a target for depositing the silicon oxide
layer. In this case, oxygen or a mixed gas of oxygen and argon is used as
a sputtering gas.

[0084] In this case, it is preferable to form the insulating layer while
moisture remaining in the treatment chamber is removed in order that
hydrogen, a hydroxyl group, or moisture be not contained in the
insulating layer.

[0085] In order to remove moisture remaining in the treatment chamber, an
adsorption vacuum pump is preferably used. For example, a cryopump, an
ion pump, or a titanium sublimation pump is preferably used. As an
exhaust means, a turbo pump to which a cold trap is added may be used.
For example, a hydrogen atom, a compound containing a hydrogen atom, such
as water (H2O), and the like are exhausted from the treatment
chamber with the use of a cryopump. Therefore, the concentration of an
impurity contained in the insulating layer which is deposited in the
treatment chamber can be lowered.

[0086] As a sputtering gas used for deposition of the insulating layer, a
high-purity gas from which an impurity such as hydrogen, water, a
hydroxyl group, or hydride is removed to about a concentration of ppm or
ppb is preferably used.

[0087] Examples of sputtering include RF sputtering in which a
high-frequency power source is used for a sputtering power source, DC
sputtering, and pulsed DC sputtering in which a bias is applied in a
pulsed manner. RF sputtering is mainly used in the case where an
insulating film is deposited, and DC sputtering is mainly used in the
case where a conductive film is deposited.

[0088] In addition, there is also a multi-source sputtering apparatus in
which a plurality of targets of different materials can be set. With the
multi-source sputtering apparatus, films of different materials can be
deposited to be stacked in the same chamber, or a film of plural kinds of
materials can be deposited by electric discharge at the same time in the
same chamber.

[0089] In addition, there are a sputtering apparatus provided with a
magnet system inside the chamber and used for magnetron sputtering, and a
sputtering apparatus used for ECR sputtering in which plasma generated
with the use of microwaves is used without using glow discharge.

[0090] Further, as a deposition method using sputtering, reactive
sputtering in which a target substance and a sputtering gas component are
chemically reacted with each other during deposition to form a thin
compound film thereof, or bias sputtering in which voltage is also
applied to a substrate during deposition can be used.

[0091] Furthermore, the insulating layer may have a layered structure. For
example, the insulating layer may have a layered structure in which a
nitride insulating layer such as a silicon nitride layer, silicon nitride
oxide layer, an aluminum nitride layer, or an aluminum nitride oxide
layer and the above oxide insulating layer are stacked in that order from
the substrate side.

[0092] For example, a silicon nitride layer is deposited in such a manner
that a sputtering gas containing high-purity nitrogen from which hydrogen
and moisture are removed is introduced between the silicon oxide layer
and the substrate and a silicon target is used. Also in this case, as in
the case of the silicon oxide layer, it is preferable to deposit a
silicon nitride layer while moisture remaining in the treatment chamber
is removed.

[0093] Also in the case where a silicon nitride layer is deposited, the
substrate may be heated in deposition.

[0094] In the case where a silicon nitride layer and a silicon oxide layer
are stacked as the insulating layer, the silicon nitride layer and the
silicon oxide layer can be deposited in the same treatment chamber with
the use of a common silicon target. First, the silicon nitride layer is
deposited in such a manner that a sputtering gas containing nitrogen is
introduced and a silicon target mounted on the treatment chamber is used.
Then, the silicon oxide layer is deposited in such a manner that the gas
is changed to a sputtering gas containing oxygen and the same silicon
target is used. The silicon nitride layer and the silicon oxide layer can
be deposited successively without exposure to the air; thus, adsorption
of an impurity such as hydrogen or moisture on a surface of the silicon
nitride layer can be prevented.

[0095] Then, an oxide semiconductor film with a thickness of 2 to 200 nm
is formed over the insulating layer (the gate insulating layer 136 in
this embodiment) by sputtering.

[0096] In order that hydrogen, a hydroxyl group, and moisture be contained
in the oxide semiconductor film as little as possible, it is preferable
that an impurity such as hydrogen or moisture that is adsorbed on the
single crystal silicon substrate 100 be eliminated and exhausted by
preheating of the single crystal silicon substrate 100 in a preheating
chamber of a sputtering apparatus, as pretreatment for deposition. As an
exhaustion means provided in the preheating chamber, a cryopump is
preferable. Note that the preheating treatment can be omitted. In
addition, the preheating may be performed before the deposition of the
gate insulating layer 118 of the thin film transistor to be formed later,
or may be performed before the deposition of a conductive layer serving
as a source electrode and a drain electrode to be formed later.

[0097] Note that before the oxide semiconductor film is deposited by
sputtering, dust on a surface of the insulating layer is preferably
removed by reverse sputtering in which an argon gas is introduced and
plasma is generated. The reverse sputtering refers to a method in which
voltage is applied to a substrate side with the use of an RF power source
in an argon atmosphere and ionized argon collides with the substrate so
that a substrate surface is modified. Note that nitrogen, helium, oxygen,
or the like may be used instead of argon.

[0098] The oxide semiconductor film is deposited by sputtering. As the
oxide semiconductor film, an oxide semiconductor film, for example, a
four-component metal oxide such as an In--Sn--Ga--Zn--O film; a
three-component metal oxide such as an In--Ga--Zn--O film, an
In--Sn--Zn--O film, an In--Al--Zn--O film, a Sn--Ga--Zn--O film, an
Al--Ga--Zn--O film, or a Sn--Al--Zn--O film; or a two-component metal
oxide such as an In--Zn--O film, a Sn--Zn--O film, an Al--Zn--O film, a
Zn--Mg--O film, a Sn--Mg--O film, an In--Mg--O film, an In--O film, a
Sn--O film, or a Zn--O film can be used. Further, SiO2 may be
contained in the above oxide semiconductor film.

[0099] As the oxide semiconductor film, a thin film expressed by
InMO3(ZnO)m (m>0) can be used. Here, M denotes one or more
metal elements selected from Ga, Al, Mn, or Co. For example, M can be Ga,
Ga and Al, Ga and Mn, Ga and Co, or the like. Among oxide semiconductor
films whose composition formulae are expressed by InMO3(ZnO)m
(m>0), an oxide semiconductor which includes Ga as M is referred to as
an In--Ga--Zn--O-based oxide semiconductor, and a thin film of the
In--Ga--Zn--O-based oxide semiconductor is also referred to as an
In--Ga--Zn--O-based film.

[0100] In this embodiment, the oxide semiconductor film is deposited by
sputtering with the use of an In--Ga--Zn--O-based metal oxide target.
Alternatively, the oxide semiconductor film can be deposited by
sputtering in a rare gas (typically argon) atmosphere, an oxygen
atmosphere, or an atmosphere including a rare gas (typically argon) and
oxygen.

[0101] As a sputtering gas used for deposition of the oxide semiconductor
film, a high-purity gas from which an impurity such as hydrogen, water, a
hydroxyl group, or hydride is removed to about a concentration of ppm or
ppb is preferably used.

[0102] As a target used for forming the oxide semiconductor film by
sputtering, a metal oxide target containing zinc oxide as a main
component can be used. For example, a metal oxide target having a
composition ratio of In2O3:Ga2O3:ZnO=1:1:1 [molar
ratio] may be used. Alternatively, a metal oxide target having a
composition ratio of In2O3:Ga2O3:ZnO=1:1:2 [molar
ratio] may be used. The filling rate of the metal oxide target is 90 to
100%, preferably 95 to 99.9%. With the use of the metal oxide target with
a high filling rate, the deposited oxide semiconductor film has high
density.

[0103] The oxide semiconductor film is deposited over the insulating layer
in such a manner that the substrate is held in a treatment chamber kept
in a reduced pressure state, moisture remaining in the treatment chamber
is removed, a sputtering gas from which hydrogen and moisture are removed
is introduced, and a metal oxide is used as a target. In order to remove
moisture remaining in the treatment chamber, an adsorption vacuum pump is
preferably used. For example, a cryopump, an ion pump, or a titanium
sublimation pump is preferably used. As an exhaust means, a turbo pump to
which a cold trap is added may be used. For example, a hydrogen atom, a
compound containing a hydrogen atom, such as water (H2O), and the
like are exhausted from the treatment chamber with the use of a cryopump.
Therefore, the concentration of an impurity contained in the oxide
semiconductor film which is deposited in the treatment chamber can be
lowered. Further, the substrate may be heated when the oxide
semiconductor film is deposited.

[0104] As an example of the deposition condition, the following condition
is employed: the substrate temperature is room temperature, the distance
between the substrate and the target is 110 mm, the pressure is 0.4 Pa,
the direct current (DC) power is 0.5 kW, and an atmosphere containing
oxygen and argon (the flow rate of oxygen is 15 sccm and the flow rate of
argon is 30 sccm) is used. Note that it is preferable that pulsed
direct-current (DC) power be used because powdered substances (also
referred to as particles or dust) generated in deposition can be reduced
and the film thickness can be uniform. The thickness of the oxide
semiconductor film is preferably 5 to 30 nm. Note that the appropriate
thickness of the oxide semiconductor film differs depending on an oxide
semiconductor material, and the thickness may be set as appropriate
depending on the material.

[0105] Then, the oxide semiconductor film is processed into island-shaped
oxide semiconductor layers 102 and 122 by a first photolithography
process and an etching process (see FIG. 4B). Here, the oxide
semiconductor layer 102 is a semiconductor layer used for the formation
of a channel region of a first thin film transistor, and the oxide
semiconductor layer 122 is a semiconductor layer used for the formation
of a channel region of a second thin film transistor. Note that a resist
mask used for formation of the island-shaped oxide semiconductor layer
may be formed by an inkjet method. A photomask is not used in an inkjet
method; thus, manufacturing cost can be reduced. Further, as the etching
of the oxide semiconductor film, dry etching, wet etching, or both of
them may be employed.

[0107] Alternatively, a gas containing fluorine (a fluorine-based gas such
as carbon tetrafluoride (CF4), sulfur hexafluoride (SF6),
nitrogen trifluoride (NF3), or trifluoromethane (CHF3));
hydrogen bromide (HBr); oxygen (O2); any of these gases to which a
rare gas such as helium (He) or argon (Ar) is added; or the like can be
used.

[0108] As the dry etching, parallel plate RIE (reactive ion etching) or
ICP (inductively coupled plasma) etching can be used. In order to etch
the film to have a desired shape, the etching conditions (the amount of
electric power applied to a coil-shaped electrode, the amount of electric
power applied to an electrode on a substrate side, the temperature of the
electrode on the substrate side, and the like) are adjusted as
appropriate.

[0109] As an etchant used for wet etching, a solution obtained by mixture
of phosphoric acid, acetic acid, and nitric acid, an ammonia hydrogen
peroxide mixture (a hydrogen peroxide solution at 31 wt %: ammonia water
at 28 wt %: water=5:2:2), or the like can be used. Alternatively, ITO-07N
(produced by KANTO CHEMICAL CO., INC.) may be used.

[0110] The etchant used in the wet etching is removed together with the
etched material by cleaning. Waste liquid of the etchant including the
removed material may be purified and the material contained in the waste
liquid may be reused. When a material such as indium contained in the
oxide semiconductor layer is collected from the waste liquid after the
etching and reused, the resources can be efficiently used and cost can be
reduced.

[0111] In order to etch the oxide semiconductor film to have a desired
shape, the etching conditions (an etchant, etching time, temperature, and
the like) are adjusted as appropriate depending on the material.

[0112] In this embodiment, the oxide semiconductor film is processed into
the island-shaped oxide semiconductor layers 102 and 122 by wet etching
with the use of a solution where phosphoric acid, acetic acid, and nitric
acid are mixed as an etchant.

[0113] In this embodiment, the oxide semiconductor layers 102 and 122 are
subjected to first heat treatment in a rare gas (e.g., nitrogen, helium,
neon, or argon) atmosphere. The temperature of the first heat treatment
is 400 to 750° C., preferably higher than or equal to 400°
C. and lower than the strain point of the substrate. Here, after the
substrate is put in an electric furnace which is a kind of heat treatment
apparatus and the oxide semiconductor layer is subjected to heat
treatment at 450° C. for one hour in a nitrogen atmosphere. When
temperature is lowered from the heat treatment temperature, the
atmosphere may be changed into an oxygen atmosphere. Through the first
heat treatment, the oxide semiconductor layers 102 and 122 can be
dehydrated or dehydrogenated.

[0114] The heat treatment apparatus is not limited to an electric furnace,
and may be provided with a device for heating an object to be processed
by thermal conduction or thermal radiation from a heater such as a
resistance heater. For example, an RTA (rapid thermal annealing)
apparatus such as a GRTA (gas rapid thermal annealing) apparatus, or an
LRTA (lamp rapid thermal annealing) apparatus can be used. An LRTA
apparatus is an apparatus for heating an object to be processed by
radiation of light (an electromagnetic wave) emitted from a lamp such as
a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp,
a high pressure sodium lamp, or a high pressure mercury lamp. A GRTA
apparatus is an apparatus with which heat treatment is performed using a
high-temperature gas. As the gas, an inert gas which does not react with
an object to be processed by heat treatment, such as nitrogen or a rare
gas such as argon, is used.

[0115] For example, as the first heat treatment, GRTA may be performed as
follows. The substrate is put in an inert gas heated at a high
temperature of 650 to 700° C., is heated for several minutes, and
is taken out of the inert gas heated at the high temperature. GRTA
enables high-temperature heat treatment in a short time.

[0116] Note that in the first heat treatment, it is preferable that water,
hydrogen, and the like be not contained in an atmosphere gas such as
nitrogen, helium, neon, or argon. Further, the purity of the atmosphere
gas is preferably 6N (99.9999%) or higher, more preferably 7N (99.99999%)
or higher (that is, the impurity concentration is 1 ppm or lower,
preferably 0.1 ppm or lower). In the case where oxygen is used as the
atmosphere gas, the atmosphere gas preferably has similar purity.

[0117] Further, the oxide semiconductor layer is crystallized and the
crystal structure of the oxide semiconductor layer is changed into a
microcrystalline structure or a polycrystalline structure depending on
the condition of the first heat treatment or the material of the oxide
semiconductor layer in some cases. For example, the oxide semiconductor
layer might be crystallized to be a microcrystalline oxide semiconductor
layer having a degree of crystallinity of 90% or more, or 80% or more.
Further, depending on the condition of the first heat treatment or the
material of the oxide semiconductor layer, the oxide semiconductor layer
might become an amorphous oxide semiconductor layer containing no
crystalline component. The oxide semiconductor layer might become an
oxide semiconductor layer in which a microcrystalline portion (with a
grain diameter of 1 to 20 nm, typically 2 to 4 nm) is mixed into an
amorphous oxide semiconductor layer.

[0118] In addition, the first heat treatment for the oxide semiconductor
layer can be performed on the oxide semiconductor film before being
processed into the island-shaped oxide semiconductor layer.

[0119] The heat treatment for dehydration or dehydrogenation of the oxide
semiconductor layer may be performed at any of the following timings:
after the oxide semiconductor layer is formed; after a source electrode
and a drain electrode are formed over the oxide semiconductor layer; and
after a gate insulating layer is formed over the source electrode and the
drain electrode.

[0120] Next, an opening which reaches a p.sup.+ layer in an upper layer of
the photodiode is formed in the insulating layer by a second
photolithography process and an etching process, and a conductive layer
is formed over the insulating layer and the oxide semiconductor layers
102 and 122. The conductive layer may be formed by sputtering or vacuum
evaporation. As the material of the conductive layer, any of the
following materials can be used: an element selected from aluminum,
chromium, copper, tantalum, titanium, molybdenum, or tungsten; an alloy
including any of these elements; an alloy film including the above
elements in combination; or the like. Further, one or more materials
selected from manganese, magnesium, zirconium, beryllium, or yttrium may
be used. Furthermore, the metal conductive layer may have a single-layer
structure or a layered structure of two or more layers. For example, a
single-layer structure of an aluminum film including silicon, a two-layer
structure in which a titanium film is stacked over an aluminum film, a
three-layer structure in which a titanium film, an aluminum film, and a
titanium film are stacked in that order, or the like can be used.
Alternatively, a film, an alloy film, or a nitride film which contains
aluminum and one or more of elements selected from titanium, tantalum,
tungsten, molybdenum, chromium, neodymium, or scandium may be used.

[0121] Next, a resist mask is formed over the conductive layer in a third
photolithography process; the source electrode 104 and the drain
electrode 106 of the first thin film transistor and the source electrode
124 and a drain electrode 126 of the second thin film transistor are
formed by selective etching; then, the resist mask is removed (see FIG.
4C). Here, the drain electrode 106 of the first thin film transistor and
the source electrode 124 of the second thin film transistor are
electrically connected to each other; however, they may be insulated from
each other or may be electrically connected to each other using a wiring
later. Note that when end portions of the formed source electrodes and
the formed drain electrodes are tapered, coverage with a gate insulating
layer stacked thereover is improved, which is preferable.

[0122] In this embodiment, a 150-nm-thick titanium film is formed as the
source electrodes 104 and 124 and the drain electrodes 106 and 126 by
sputtering.

[0123] Note that each material and etching conditions are adjusted as
appropriate so that parts of the oxide semiconductor layers 102 and 122
are not removed in etching of the conductive layer and the insulating
layer formed below the oxide semiconductor layers is not exposed.

[0124] In this embodiment, a titanium film is used as the conductive
layer, an In--Ga--Zn--O-based oxide semiconductor is used for the oxide
semiconductor layers 102 and 122, and an ammonia hydrogen peroxide
mixture (a mixture of ammonia, water, and a hydrogen peroxide solution)
is used as an etchant.

[0125] Note that in the third photolithography process and an etching
process, only parts of the oxide semiconductor layers 102 and 122 are
etched so that oxide semiconductor layers having grooves (depressions)
are formed in some cases. The resist mask used for forming the source
electrodes 104 and 124 and the drain electrodes 106 and 126 may be formed
by an inkjet method. A photomask is not used in an inkjet method; thus,
manufacturing cost can be reduced.

[0126] An ultraviolet ray, a KrF laser beam, or an ArF laser beam is used
for exposure when the resist mask is formed in the third photolithography
process. The channel length L of a thin film transistor to be formed
later is determined by a pitch between a lower end of the source
electrode and a lower end of the drain electrode that are adjacent to
each other over the oxide semiconductor layers 102 and 122. Note that
when exposure is performed under a condition that the channel length L is
less than 25 nm, the exposure when the resist mask is formed in the
second photolithography process is performed using an extreme ultraviolet
ray whose wavelength is extremely short (several nanometers to several
tens of nanometers). In exposure with an extreme ultraviolet ray,
resolution is high and the depth of focus is large. Therefore, the
channel length L of the thin film transistor to be formed later can be 10
to 1000 nm, and a circuit can operate at higher speed. Further, since the
amount of off-state current is extremely small, power consumption can be
reduced.

[0127] Next, the gate insulating layer 118 is formed over the insulating
layer, the oxide semiconductor layers 102 and 122, the source electrodes
104 and 124, and the drain electrodes 106 and 126 (see FIG. 5A). In this
case, the gate insulating layer 118 is also deposited over the bulk
transistor and serves as part of an interlayer insulating film.

[0128] Here, an oxide semiconductor (a highly purified oxide
semiconductor) which is made to be intrinsic (i-type) or substantially
intrinsic by removal of an impurity is highly sensitive to an interface
state and interface charge; thus, an interface between the oxide
semiconductor and the gate insulating layer is important. Therefore, the
gate insulating layer (GI) which is in contact with the highly purified
oxide semiconductor needs high quality.

[0129] For example, high-density plasma-enhanced CVD using microwaves
(2.45 GHz) is preferable because a dense high-quality insulating layer
having high withstand voltage can be formed. This is because when the
highly purified oxide semiconductor is closely in contact with the
high-quality gate insulating layer, the interface state can be reduced
and interface properties can be favorable. Needless to say, a different
deposition method such as sputtering or plasma-enhanced CVD can be used
as long as a high-quality insulating layer can be formed as a gate
insulating layer. In addition, any gate insulating layer can be used as
long as film quality and properties of an interface with an oxide
semiconductor of the gate insulating layer are modified by heat treatment
performed after deposition. In either case, any gate insulating layer can
be used as long as film quality as a gate insulating layer is high,
interface state density with an oxide semiconductor is decreased, and a
favorable interface can be formed.

[0130] In a bias temperature test (BT test) at 85° C. and
2×106 V/cm for 12 hours, if an impurity has been added to an
oxide semiconductor, the bond between the impurity and the main component
of the oxide semiconductor is broken by a high electric field (B: bias)
and high temperature (T: temperature), so that a generated dangling bond
induces a shift in the threshold voltage (Vth). As a countermeasure
against this, in one embodiment of the present invention, the impurity in
the oxide semiconductor, especially, hydrogen, water, or the like is
removed as much as possible so that the properties of an interface with
the gate insulating layer are favorable as described above. Accordingly,
it is possible to obtain a thin film transistor which is stable even when
the BT test is performed.

[0131] In this embodiment, the gate insulating layer 118 is formed using a
high-density plasma-enhanced CVD apparatus using microwaves (2.45 GHz).
Here, a high-density plasma-enhanced CVD apparatus refers to an apparatus
which can realize a plasma density of 1×1011/cm3 or
higher. For example, plasma is generated by application of a microwave
power of 3 to 6 kW so that an insulating layer is formed.

[0132] A monosilane gas (SiH4), nitrous oxide (N2O), and a rare
gas are introduced into a chamber as a source gas, and high-density
plasma is generated at a pressure of 10 to 30 Pa so that an insulating
layer is formed over the substrate. After that, the supply of a
monosilane gas is stopped, and nitrous oxide (N2O) and a rare gas
are introduced without exposure to the air, so that plasma treatment may
be performed on a surface of the insulating layer. The plasma treatment
performed on the surface of the insulating layer by introduction of at
least nitrous oxide (N2O) and a rare gas is performed after the
insulating layer is formed. The insulating layer formed through the above
process is an insulating layer whose reliability can be secured even
though it has small thickness, for example, a thickness less than 100 nm.

[0133] When the gate insulating layer 118 is formed, the flow ratio of the
monosilane gas (SiH4) to nitrous oxide (N2O) which are
introduced into the chamber is in the range of 1:10 to 1:200. In
addition, as the rare gas which is introduced into the chamber, helium,
argon, krypton, xenon, or the like can be used. In particular, argon,
which is inexpensive, is preferably used.

[0134] In addition, the insulating layer formed using the high-density
plasma-enhanced CVD apparatus has excellent step coverage, and the
thickness of the insulating layer can be controlled precisely.

[0135] The film quality of the insulating layer formed through the above
process is greatly different from that of an insulating layer formed
using a conventional parallel plate PECVD apparatus. The etching rate of
the insulating layer formed through the above process is lower than that
of the insulating layer formed using the conventional parallel plate
PECVD apparatus by 10% or more or 20% or more when the etching rates with
the same etchant are compared to each other. Thus, it can be said that
the insulating layer formed using the high-density plasma-enhanced CVD
apparatus is a dense layer.

[0136] In this embodiment, as the gate insulating layer 118, a
100-nm-thick silicon oxynitride layer (also referred to as
SiOxNy, where x>y>0) formed using a high-density
plasma-enhanced CVD apparatus is used.

[0137] The gate insulating layer 118 can be formed to have a single-layer
structure or a layered structure including one or more of a silicon oxide
layer, a silicon nitride layer, a silicon oxynitride layer, a silicon
nitride oxide layer, and an aluminum oxide layer by plasma-enhanced CVD,
sputtering, or the like as a different method. Note that the gate
insulating layer 118 is preferably formed by sputtering in order not to
include a large amount of hydrogen. In the case where a silicon oxide
layer is formed by sputtering, silicon or quartz is used as a target, and
oxygen or a mixed gas of oxygen and argon is used as a sputtering gas.

[0138] The gate insulating layer 118 can have a structure where a silicon
oxide layer and a silicon nitride layer are stacked from the source
electrodes 104 and 124 and the drain electrodes 106 and 126. For example,
a 100-nm-thick gate insulating layer may be formed in such a manner that
a silicon oxide layer (SiOx (x>0)) with a thickness of 5 to 300
nm is formed as a first gate insulating layer and a silicon nitride layer
(SiNy(y>0)) with a thickness of 50 to 200 nm is stacked over the
first gate insulating layer as a second gate insulating film by
sputtering.

[0139] Next, a resist mask is formed in a fourth photolithography process
and part of the gate insulating layer 118 is removed by selective
etching, so that openings which reach the drain electrode 126 of the thin
film transistor and the n-type regions 132a and 132b serving as a source
electrode and a drain electrode of the bulk transistor are formed (see
FIG. 5B).

[0140] Then, a conductive layer is formed over the gate insulating layer
118 in which the openings are formed, and then a gate electrode 108, a
gate electrode 128, and wiring layers 151, 152, and 153 are formed by a
fifth photolithography process and an etching process. Note that a resist
mask may be formed by an inkjet method. A photomask is not used in an
inkjet method; thus, manufacturing cost can be reduced.

[0141] The gate electrodes 108 and 128 and the wiring layers 151, 152, and
153 can be formed to have a single layer or a stacked layer of a metal
material such as molybdenum, titanium, chromium, tantalum, tungsten,
aluminum, copper, neodymium, or scandium, or an alloy material which
includes any of these materials as a main component.

[0142] For example, as a two-layer structure of the gate electrodes 108
and 128 and the wiring layers 151, 152, and 153, the following structures
are preferable: a two-layer structure in which a molybdenum layer is
stacked over an aluminum layer, a two-layer structure in which a
molybdenum layer is stacked over a copper layer, a two-layer structure in
which a titanium nitride layer or a tantalum nitride layer is stacked
over a copper layer, and a two-layer structure in which a titanium
nitride layer and a molybdenum layer are stacked. As a three-layer
structure, a three-layer structure in which a tungsten layer or a
tungsten nitride layer, an alloy of aluminum and silicon or an alloy of
aluminum and titanium, and a titanium nitride layer or a titanium layer
are stacked is preferable. Note that the gate electrode can be formed
using a light-transmitting conductive layer. As an example of the
material of the light-transmitting conductive layer, a light-transmitting
conductive oxide or the like can be given. In this embodiment, as the
gate electrodes 108 and 128 and the wiring layers 151, 152, and 153, a
150-nm-thick titanium film is formed by sputtering.

[0143] Next, second heat treatment (preferably at 200 to 400° C.,
for example, 250 to 350° C.) is performed in an inert gas
atmosphere or an oxygen gas atmosphere. In this embodiment, the second
heat treatment is performed at 250° C. for one hour in a nitrogen
atmosphere. Alternatively, the second heat treatment may be performed
after a protective insulating layer or a planarization insulating layer
is formed over the first thin film transistor, the second thin film
transistor, and the bulk transistor.

[0144] Furthermore, heat treatment may be performed at 100 to 200°
C. for 1 to 30 hours in an air atmosphere. This heat treatment may be
performed at a fixed heating temperature. Alternatively, the following
change in the heating temperature may be conducted plural times
repeatedly: the heating temperature is increased from room temperature to
a temperature of 100 to 200° C. and then decreased to room
temperature. Further, this heat treatment may be performed under a
reduced pressure before the formation of the oxide insulating layer. When
the heat treatment is performed under a reduced pressure, the heating
time can be shortened.

[0145] Through the above steps, the first thin film transistor and the
second thin film transistor each including the oxide semiconductor layer
whose concentration of hydrogen, moisture, hydride, or hydroxide is
lowered can be formed (see FIG. 5C). Here, the first thin film transistor
can be used as the transfer transistor 101; the second thin film
transistor can be used as the reset transistor 121; and the bulk
transistor can be used as the amplifier transistor 131.

[0146] A protective insulating layer 142 or a planarization insulating
layer for planarization may be provided over the thin film transistor and
the bulk transistor. For example, the protective insulating layer 142 can
be formed to have a single-layer structure or a layered structure
including a silicon oxide layer, a silicon nitride layer, a silicon
oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide
layer.

[0147] The planarization insulating layer can be formed using a
heat-resistant organic material such as polyimide, acrylic,
benzocyclobutene, polyamide, or epoxy. Other than such organic materials,
it is possible to use a low-dielectric constant material (a low-k
material), a siloxane-based resin, PSG (phosphosilicate glass), BPSG
(borophosphosilicate glass), or the like. Note that the planarization
insulating layer may be formed by stacking a plurality of insulating
films formed using these materials.

[0148] Note that a siloxane-based resin corresponds to a resin including a
Si--O--Si bond formed using a siloxane-based material as a starting
material. The siloxane-based resin may include an organic group (e.g., an
alkyl group or an aryl group) as a substituent. Further, the organic
group may include a fluoro group.

[0149] There is no particular limitation on the method for forming the
planarization insulating layer. The planarization insulating layer can be
formed, depending on the material, by a method such as sputtering, an SOG
method, a spin coating method, a dipping method, a spray coating method,
or a droplet discharge method (e.g., an inkjet method, screen printing,
or offset printing), or a tool such as a doctor knife, a roll coater, a
curtain coater, or a knife coater.

[0150] When remaining moisture in the atmosphere is removed at the time of
the deposition of the oxide semiconductor film, the concentration of
hydrogen and hydride in the oxide semiconductor film can be lowered.
Thus, the oxide semiconductor film can be stabilized.

[0151] In the above manner, a highly reliable semiconductor device with
stable electrical characteristics that includes a thin film transistor
having an oxide semiconductor layer can be provided.

[0152] This embodiment mode can be combined with any of the other
embodiments as appropriate.

Embodiment 2

[0153] In one embodiment of the present invention, an oxide semiconductor
which is an intrinsic or substantially intrinsic semiconductor by removal
of an impurity that might be a carrier donor (or an acceptor) in the
oxide semiconductor is reduced to a very low level is used for a thin
film transistor. In this embodiment, measured values of off-state current
in a test element group (also referred to as a TEG) are described below.

[0154]FIG. 6 illustrates initial characteristics of a thin film
transistor with L/W=3 μm/10000 μm in which 200 thin film
transistors each with L/W=3 μm/50 μm are connected in parallel. In
addition, a top view of the thin film transistor is illustrated in FIG.
7A and a partly enlarged top view thereof is illustrated in FIG. 7B. The
region enclosed by a dotted line in FIG. 7B is a thin film transistor of
one stage with L/W=3 μm/50 μm and Lov=1.5 μm. In order to
measure the initial characteristics of the thin film transistor, the
changing characteristics of source-drain current (hereinafter referred to
as drain current or Id) were measured under conditions that the
substrate temperature was set to room temperature, source-drain voltage
(hereinafter referred to as drain voltage or Vd) was set to 10 V,
and source-gate voltage (hereinafter referred to as gate voltage or
Vg) was changed from -20 to +20 V. In other words, Vg-Id
characteristics were measured. Note that FIGS. 7A and 7B illustrate
Vg in the range of from -20 to +5 V.

[0155] As illustrated in FIG. 6, the thin film transistor having a channel
width W of 10000 μm has an off-state current of 1×10-13 A
or less at Vd of 1 V and 10 V, which is less than or equal to the
resolution (100 fA) of a measurement device (a semiconductor parameter
analyzer, Agilent 4156C manufactured by Agilent Technologies Inc.).

[0156] In other words, the thin film transistor has an electrical
characteristic of normally off. At a drain voltage of 1 to 10V, the thin
film transistor can operate so that off-state current per micrometer of
the channel width is 100 aA/μm or less, preferably 10 aA/μm or
less, still more preferably 1 aA/μm or less.

[0157] A method for manufacturing the thin film transistor used for the
measurement is described.

[0158] First, as a base layer, by CVD, a silicon nitride layer was formed
over a glass substrate and a silicon oxynitride layer was formed over the
silicon nitride layer. Over the silicon oxynitride layer, a tungsten
layer was formed as a gate electrode by sputtering. Here, the tungsten
layer was selectively etched so that the gate electrode was formed.

[0159] Next, over the gate electrode, a 100-nm-thick silicon oxynitride
layer was formed as a gate insulating layer by CVD.

[0160] Then, a 50-nm-thick oxide semiconductor layer was formed over the
gate insulating layer by sputtering with the use of an
In--Ga--Zn--O-based oxide semiconductor target
(In2O3:Ga2O3:ZnO=1:1:2 in a molar ratio). Here, an
island-shaped oxide semiconductor layer was formed by selective etching
of the oxide semiconductor layer.

[0161] Then, first heat treatment was performed on the oxide semiconductor
layer in a clean oven at 450° C. for 1 hour in a nitrogen
atmosphere.

[0162] Then, as a source electrode and a drain electrode, a 150-nm-thick
titanium layer was formed over the oxide semiconductor layer by
sputtering. Here, the source electrode and the drain electrode were
formed by selective etching of the titanium layer, and 200 thin film
transistors each having a channel length L of 3 μm and a channel width
W of 50 μm were connected in parallel to obtain a thin film transistor
with L/W=3 μm/10000 μm.

[0163] Then, as a protective insulating layer, a 300-nm-thick silicon
oxide layer was formed so as to be in contact with the oxide
semiconductor layer by reactive sputtering. Here, the silicon oxide layer
that was the protective layer was selectively etched so that openings
were formed over the gate electrode, the source electrode, and the drain
electrode. After that, second heat treatment was performed at 250°
C. for 1 hour in a nitrogen atmosphere.

[0164] Then, heat treatment was performed at 150° C. for 10 hours
before the measurement of Vg-Idcharacteristics.

[0165] Through the above steps, a bottom-gate thin film transistor was
manufactured.

[0166] The reason why the off-state current of the thin film transistor is
approximately 1×10-13 A as illustrated in FIG. 6 is that the
concentration of hydrogen in the oxide semiconductor layer can be
sufficiently reduced in the above manufacturing steps. The concentration
of hydrogen in the oxide semiconductor layer is 5×1019
atoms/cm3 or lower, preferably 5×1018 atoms/cm3 or
lower, more preferably 5×1017 atoms/cm3 or lower or lower
than 1×1016/cm3. Note that the concentration of hydrogen
in the oxide semiconductor layer is measured by secondary ion mass
spectroscopy (SIMS).

[0167] Although the example where an In--Ga--Zn--O-based oxide
semiconductor is used is described, this embodiment is not particularly
limited to this. Another oxide semiconductor material, for example, an
In--Sn--Zn--O-based oxide semiconductor, a Sn--Ga--Zn--O-based oxide
semiconductor, an Al--Ga--Zn--O-based oxide semiconductor, a
Sn--Al--Zn--O-based oxide semiconductor, an In--Zn--O-based oxide
semiconductor, an In--Sn--O-based oxide semiconductor, a Sn--Zn--O-based
oxide semiconductor, an Al--Zn--O-based oxide semiconductor, an
In--O-based oxide semiconductor, a Sn--O-based oxide semiconductor, a
Zn--O-based oxide semiconductor, or the like can be used. Further, as an
oxide semiconductor material, an In--Al--Zn--O-based oxide semiconductor
into which Al is mixed at 2.5 to 10 wt % or an In--Zn--O-based oxide
semiconductor into which Si is mixed at 2.5 to 10 wt % can be used.

[0168] The carrier concentration in the oxide semiconductor layer that is
measured by a carrier measurement device is lower than
5×1014/cm3, preferably 5×1012/cm3 or
lower, more preferably lower than or equal to a carrier concentration of
silicon, 1.45×1010/cm3. That is, the carrier
concentration in the oxide semiconductor layer can be as close to zero as
possible.

[0169] Further, the channel length L of the thin film transistor can be 10
to 1000 nm, and a circuit can operate at higher speed. Furthermore, since
the amount of off-state current is extremely small, power consumption can
be further reduced.

[0170] In circuit design, the oxide semiconductor layer can be regarded as
an insulator when the thin film transistor is off.

[0171] After that, the temperature characteristics of off-state current of
the thin film transistor manufactured in this embodiment were evaluated.
The temperature characteristics are important in considering the
environmental resistance, maintenance of performance, or the like of an
end product in which the thin film transistor is used. It is to be
understood that a smaller amount of change is preferable, which increases
the degree of freedom for product design.

[0172] For the temperature characteristics, the
Vg-Idcharacteristics were obtained using a constant-temperature
chamber under conditions that substrates provided with thin film
transistors were kept at respective constant temperatures of -30°
C., 0° C., 25° C., 40° C., 60° C., 80°
C., 100° C., and 120° C., drain voltage was set to 6 V, and
gate voltage was changed from -20 to +20 V.

[0173]FIG. 8A illustrates Vg-Id characteristics measured at the
above temperatures and superimposed on one another, and FIG. 8B
illustrates an enlarged view of the range of off-state current enclosed
by a dotted line in FIG. 8A. The rightmost curve indicated by an arrow in
the diagram is a curve obtained at -30° C.; the leftmost curve is
a curve obtained at 120° C.; and curves obtained at the other
temperatures are located therebetween. The temperature dependence of
on-state current can hardly be observed. On the other hand, as clearly
illustrated also in the enlarged view of FIG. 8B, the off-state current
is 1×10-12 A or less, which is near the resolution of the
measurement device, at all the temperatures except the case where the
gate voltage is around 20 V, and the temperature dependence thereof is
not observed. In other words, even at a high temperature of 120°
C., the off-state current is kept at 1×10-12 A or less, and
given that the channel width W is 10000 mm, it can be seen that the
off-state current is significantly low.

[0174] A thin film transistor including a highly purified oxide
semiconductor shows almost no dependence of off-state current on
temperature. It can be said that an oxide semiconductor does not show
temperature dependence when highly purified because the conductivity type
becomes extremely close to an intrinsic type and the Fermi level is
located in the middle of the forbidden band, as illustrated in the band
diagram of FIG. 10A. This also results from the fact that the oxide
semiconductor has an energy gap of 3 eV or more and includes very few
thermally excited carriers. In addition, the source region and the drain
region are in a degenerated state, which is also a factor for showing no
temperature dependence. The thin film transistor is mainly operated with
carriers which are injected from the degenerated source region to the
oxide semiconductor, and the above characteristics (independence of
off-state current from temperature) can be explained by independence of
carrier density from temperature. Further, this extremely low off-state
current is described below with reference to band diagrams.

[0175]FIG. 9 is a longitudinal cross-sectional view of an inverted
staggered thin film transistor including an oxide semiconductor. An oxide
semiconductor layer (OS) is provided over a gate electrode (GE1) with a
gate insulating film (GI) provided therebetween. A source electrode (S)
and a drain electrode (D) are provided thereover.

[0176] FIGS. 10A and 10B are energy band diagrams (schematic views) in an
A-A' cross section in FIG. 9. FIG. 10A illustrates the case where the
voltage of a source and the voltage of a drain are equal (VD=0 V),
and FIG. 10B illustrates the case where a positive potential
(VD>0 V) is applied to the drain.

[0177] FIGS. 11A and 11B are energy band diagrams (schematic views) in a
B-B' cross section in FIG. 9. FIG. 11A illustrates a state in which a
positive potential (+VG) is applied to a gate (G1) and carriers
(electrons) flow between a source and a drain. Further, FIG. 11B
illustrates a state in which a negative potential (-VG) is applied
to the gate (G1) and the thin film transistor is off (minority carriers
do not flow).

[0178]FIG. 12 illustrates a relationship among a vacuum level, the work
function (φM) of a metal, and electron affinity (χ) of an
oxide semiconductor.

[0179] A conventional oxide semiconductor generally has n-type
conductivity, and the Fermi level (EF) in that case is apart from
the intrinsic Fermi level (Ei) positioned in the middle of the band
gap and is positioned near the conduction band. Note that it is known
that part of hydrogen in an oxide semiconductor serves as a donor and is
a factor which makes the oxide semiconductor have n-type conductivity.

[0180] In contrast, the oxide semiconductor in one embodiment of the
present invention is an intrinsic (i-type) or substantially intrinsic
oxide semiconductor obtained by removal of hydrogen, which is an n-type
impurity, from the oxide semiconductor and the increase in purity so that
an impurity other than the main components of the oxide semiconductor is
not included as much as possible. In other words, the oxide semiconductor
is a highly purified intrinsic (i-type) semiconductor or a semiconductor
which is close to a highly purified i-type semiconductor not by addition
of an impurity but by removal of an impurity such as hydrogen or water as
much as possible. In this manner, the Fermi level (EF) can be the
same level as the intrinsic Fermi level (Ei).

[0181] It is said that in the case where the band gap (Eg) of the oxide
semiconductor is 3.15 eV, electron affinity (χ) is 4.3 eV. The work
function of titanium (Ti) used for the source electrode and the drain
electrode is substantially the same as the electron affinity (χ) of
the oxide semiconductor. In this case, the Schottky electron barrier is
not formed at an interface between the metal and the oxide semiconductor.

[0182] In other words, in the case where the work function (φM)
of the metal is the same as the electron affinity (χ) of the oxide
semiconductor, a state in which the metal and the oxide semiconductor are
in contact with each other is shown as an energy band diagram (a
schematic view) illustrated in FIG. 10A.

[0183] In FIG. 10B, a black circle ( ) indicates an electron. When a
positive potential is applied to the drain, the electron is injected into
the oxide semiconductor over the barrier (h) and flows toward the drain.
In that case, the height of the barrier (h) changes depending on the gate
voltage and the drain voltage; in the case where positive drain voltage
is applied, the height of the barrier (h) is smaller than the height of
the barrier in FIG. 10A where no voltage is applied, i.e., half of the
band gap (Eg).

[0184] The electrons injected into the oxide semiconductor at this time
flow through the oxide semiconductor, as illustrated in FIG. 11A.
Further, in FIG. 11B, holes that are minority carriers are substantially
zero when a negative potential is applied to the gate (G1); thus, almost
no current flows. For example, even in the case of a thin film transistor
whose channel width W is 1×104 μm and whose channel length
L is 3 μm, electrical characteristics of an off-state current of
10-13 A or less and a subthreshold swing (an S value) of 0.1 V/dec
(the thickness of the gate insulating film is 100 nm) can be obtained.

[0185] The intrinsic carrier concentration of a silicon semiconductor is
1.45×1010/cm3 (300 K) and carriers exist even at room
temperature. This means that thermally excited carriers exist even at
room temperature. Further, the band gap of the silicon semiconductor is
1.12 eV; thus, the off-state current of a transistor including a silicon
semiconductor significantly changes depending on temperature.

[0186] Therefore, not by simply using an oxide semiconductor having a wide
band gap for a transistor but by highly purifying the oxide semiconductor
so that an impurity other than the main components of the oxide
semiconductor is not included as much as possible. Thus, in such an oxide
semiconductor, the carrier concentration becomes
1×1014/cm3 or lower, preferably
1×1012/cm3 or lower, so that carriers to be thermally
excited at a practical operation temperature are hardly included and the
transistor can operate only with electrons injected from the source side.
This makes it possible to decrease the off-state current to
1×10-13 A or less and to obtain an extremely stable transistor
whose off-state current hardly changes with a change in temperature.

[0187] A technical idea of one embodiment of the present invention is that
an impurity is not added to an oxide semiconductor and the oxide
semiconductor itself is highly purified by removal of an impurity such as
water or hydrogen which undesirably exists therein. In other words, a
feature of one embodiment of the present invention is that an oxide
semiconductor itself is highly purified by removal of water or hydrogen
which forms a donor level and by supply of oxygen to the oxide
semiconductor which is made to be in an oxygen-deficient state at the
time of removal.

[0188] In an oxide semiconductor, even right after the deposition,
hydrogen is observed on the order of 1020/cm3 by secondary ion
mass spectroscopy (SIMS). One technical idea of the present invention is
to highly purify an oxide semiconductor and to obtain an electrically
i-type (intrinsic) semiconductor by intentional removal of an impurity
such as water or hydrogen which forms a donor level and by compensation
for lack of oxygen that is generated at the time of removal.

[0189] As a result, it is preferable that the amount of hydrogen be as
small as possible, and it is also preferable that the number of carriers
in the oxide semiconductor be as small as possible. The oxide
semiconductor is a so-called highly purified i-type (intrinsic)
semiconductor from which carriers are eliminated and which functions as a
path of carriers (electrons) supplied from a source, rather than
intentionally including carriers for flowing current when used for a thin
film transistor.

[0190] As a result, by eliminating carriers from an oxide semiconductor or
significantly reducing carries therein, the off-state current of a
transistor can be decreased, which is a technical idea of one embodiment
of the present invention. In other words, as a criterion, the
concentration of hydrogen should be 5×1019/cm3 or lower,
preferably 5×1018/cm3 or lower, more preferably
5×1017/cm3 or lower or lower than
1×1016/cm3. The carrier concentration should be lower
than 1×1014/cm3, preferably 1×1012/cm3 or
lower.

[0191] In addition, as a result, the oxide semiconductor functions as a
path, the oxide semiconductor itself is an i-type (intrinsic)
semiconductor which is highly purified so as not to supply carriers or to
supply almost no carrier, and carriers are supplied from a source and a
drain. The degree of supply is determined by the barrier height rather
than the electron affinity χ of the oxide semiconductor, the Fermi
level thereof, which ideally corresponds to the intrinsic Fermi level,
and the work function of the source or drain.

[0192] Therefore, it is preferable that off-state current be as low as
possible, and as characteristics of a transistor to which a drain voltage
in the range of from 1 to 10 V is applied, the off-state current is 100
aA/μm or less (the channel width W=current per micrometer), preferably
10 aA/μm or less, more preferably 1 aA/μm or less.

[0193] In the case where a memory circuit (a memory element) or the like
is formed using such a thin film transistor having extremely low
off-state current, there is very little leakage. Therefore, a potential
can be held for a long time and data stored can be held for a long time.

[0194] This embodiment can be combined with any of the structures
described in the other embodiments as appropriate.

Embodiment 3

[0195] The operation of a solid-state image sensor including a thin film
transistor in one embodiment of the present invention is described.

[0196] A CMOS (complementary metal oxide semiconductor) image sensor is a
solid-state image sensor which holds a potential in a signal charge
storage portion and outputs the potential to a vertical output line
through an amplifier transistor. When leakage current occurs in a reset
transistor and/or a transfer transistor included in a CMOS image sensor,
charge or discharge is generated due to the leakage current, so that the
potential of the signal charge storage portion is changed. When the
potential of the signal charge storage portion is changed, the potential
of the amplifier transistor is also changed; thus, the levels of the
potentials are deviated from the original potentials and an image taken
deteriorates.

[0197] In this embodiment, the effect of the case where the thin film
transistor described in Embodiments 1 and 2 is used as a reset transistor
and a transfer transistor in a CMOS image sensor is described. Note that
either a thin film transistor or a bulk transistor may be used as an
amplifier transistor.

[0198]FIG. 13 illustrates an example of the pixel structure of a CMOS
image sensor. A pixel includes a photodiode 1002 which is a photoelectric
conversion element, a transfer transistor 1004, a reset transistor 1006,
an amplifier transistor 1008, and a variety of wirings. A plurality of
pixels are arranged in matrix to form a sensor. Further, a selection
transistor which is electrically connected to the amplifier transistor
1008 may be provided. Note that in the symbols of the transistors, a
symbol "OS" indicates an oxide semiconductor, and a symbol "Si" indicates
silicon. These symbols indicate suitable materials for these transistors.
The same can be said for the following diagrams.

[0199] Here, the photodiode 1002 is connected to the source side of the
transfer transistor 1004. A signal charge storage portion 1010 (also
referred to as a floating diffusion (FD)) is formed on the drain side of
the transfer transistor 1004. A source of the reset transistor 1006 and a
gate of the amplifier transistor 1008 are connected to the signal charge
storage portion 1010. As another structure, a reset power supply line
1110 can be eliminated. For example, a drain of the reset transistor 1006
is connected not to the reset power supply line 1110 but to a power
supply line 1100 or a vertical output line 1120.

[0200] Next, the operation is described with reference to a timing chart
in FIG. 14. First, power supply voltage is supplied to a power supply
terminal Then, a reset pulse is input to a gate of the reset transistor
1006, so that the reset transistor 1006 is turned on. A reset power
supply potential is stored in the signal charge storage portion 1010.
Then, the reset transistor 1006 is turned off, and the signal charge
storage portion 1010 is held at the reset power supply potential (a
period T1). Here, when almost no leakage current flows to the reset
transistor 1006 and the transfer transistor 1004, the potential is held
until the next operation of the transistor starts. Next, when the
transfer transistor 1004 is turned on, current flows from the signal
charge storage portion 1010 to the photodiode, so that the potential of
the signal charge storage portion 1010 is lowered (a period T2). When the
transfer transistor 1004 is turned off, a potential when the transfer
transistor 1004 is turned off is held in the signal charge storage
portion 1010 (a period T3). When almost no leakage current flows to the
reset transistor 1006 and the transfer transistor 1004, the potential is
held until the next operation of the transistor starts. Then, the
potential is output to a vertical output line 1120 through the amplifier
transistor 1008. After that, the supply of power supply voltage to the
power supply terminal is interrupted. In this manner, a signal is output.

[0201] In other words, almost no leakage current flows from the signal
charge storage portion 1010 through the thin film transistor when the
thin film transistor including an oxide semiconductor whose off-state
current is significantly low that is described in Embodiments 1 and 2 is
used as the reset transistor 1006 and the transfer transistor 1004, and
the potential can be held for a very long time in holding periods in the
periods T1 and T3.

[0202] Next, the operation of the photodiode 1002 is described with
reference to FIG. 15. When light does not enter the photodiode, the
photodiode has the same voltage-current characteristics as a normal diode
(a curve A in FIG. 15). When light enters the photodiode, a larger amount
of current flows especially when a reverse bias is applied, as compared
to the case where light does not enter the photodiode (a curve B in FIG.
15). The operating point of the photodiode is described with reference to
the operation in the pixel illustrated in FIG. 13. When the transfer
transistor 1004 is off, a path for flowing current does not exist in the
photodiode 1002; thus, the cathode of the photodiode is positioned at a
point c in FIG. 15 when light enters the photodiode. When the transfer
transistor 1004 is turned on after the reset transistor 1006 is turned on
and the signal charge storage portion 1010 is held at the reset power
supply potential, the potential of the cathode of the photodiode 1002 is
the same as the reset power supply potential, and the cathode of the
photodiode 1002 is positioned at a point d in FIG. 15. Then, discharge
current flows from the signal charge storage portion 1010 through the
transfer transistor 1004, so that the potential of the signal charge
storage portion 1010 is lowered. When the transfer transistor 1004 is
turned off, discharge is stopped. When it is assumed that the operating
point at this time in FIG. 15 is denoted by e, a potential difference
between the operating point d and the operating point e corresponds to a
potential difference of a signal obtained by discharge of the photodiode
1002.

[0203] Next, operation when a reset transistor, an amplifier transistor,
and signal lines are used in common among a plurality of pixels is
described. FIG. 16 is a basic structure where one reset transistor, one
transfer transistor, one amplifier transistor, one photodiode are
provided in each pixel and a reset line, a transfer switch line, and a
vertical output line are connected to the pixel. The operation in the
basic structure is described with reference to a timing chart in FIG. 17.
In driving of a first line, first, when the potential (RST1) of a first
reset line 1240 becomes a high level, a first reset transistor 1216 is
turned on. Thus, the potential (FD1) of a first signal charge storage
portion 1210 is raised to a power supply potential (hereinafter referred
to as VDD). Even when the potential (RST1) of the first reset line 1240
becomes a low level and the first reset transistor 1216 is turned off,
the potential of the first signal charge storage portion 1210 is held at
VDD when a current path does not exist. Next, when the potential (TRF1)
of a first transfer switch line 1250 becomes a high level, a first
transfer transistor 1214 is turned on, and current corresponding to light
which enters a first photodiode 1212 flows to the first photodiode 1212
and the first transfer transistor 1214, so that the potential (FD1) of
the first signal charge storage portion 1210 is lowered by discharge.
When the potential (TRF1) of the first transfer switch line 1250 becomes
a low level, the first transfer transistor 1214 is turned off, so that
the potential (FD1) of the first signal charge storage portion 1210 is
held because the current path does not exist again. This potential is
output to a vertical output line 1220 through a first amplifier
transistor 1218. Then, driving of a second line including a second reset
line 1340 and a second transfer switch line 1350 is performed. In this
manner, sequential driving is performed. Note that RST2, TRF2, and FD2 in
FIG. 17 corresponds to a timing chart in the driving of the second line.

[0204] Unlike the above basic structure, FIG. 18 illustrates the
structures of four pixels arranged longitudinally, where a reset
transistor, an amplifier transistor, and a reset line are used in common
When the number of transistors and the number of wirings are reduced,
miniaturization due to the decrease in the pixel area and reduction in
noise due to the increase in the light reception area of a photodiode can
be realized. Drains of transfer transistors in the four pixels arranged
longitudinally are electrically connected to each other, so that a signal
charge storage portion 1410 is formed. A source of a reset transistor
1406 and a gate of an amplifier transistor 1408 are connected to the
signal charge storage portion 1410.

[0205] The operation in the structures of four pixels arranged
longitudinally is described with reference to a timing chart in FIG. 19.
In driving of a first line, first, the potential (RST1) of a first reset
line 1461 becomes a high level, so that a first reset transistor 1406 is
turned on. Thus, the potential (FD) of the signal charge storage portion
1410 is raised to VDD. Even when the potential (RST1) of the first reset
line 1461 becomes a low level and the first reset transistor 1406 is
turned off, the potential (FD) of the signal charge storage portion 1410
is held at VDD when a current path does not exist. Next, when the
potential (TRF1) of a first transfer switch line 1451 becomes a high
level, a first transfer transistor 1414 is turned on, and current
corresponding to light which enters a first photodiode 1412 flows to the
first photodiode 1412 and the first transfer transistor 1414, so that the
potential (FD) of the signal charge storage portion 1410 is lowered by
discharge. When the potential (TRF1) of the first transfer switch line
1451 becomes a low level, the first transfer transistor 1414 is turned
off, so that the potential (FD) of the signal charge storage portion 1410
is held because the current path does not exist again. This potential is
output to a vertical output line 1470 through a first amplifier
transistor 1408.

[0206] In driving of a second line, the potential (RST1) of the first
reset line 1461 becomes a high level again, so that the first reset
transistor 1406 is turned on. Thus, the potential (FD) of the signal
charge storage portion 1410 is raised to VDD. Even when the potential
(RST1) of the first reset line 1461 becomes a low level and the first
reset transistor 1406 is turned off, the potential (FD) of the signal
charge storage portion 1410 is held at VDD when a current path does not
exist. Next, when the potential (TRF2) of a second transfer switch line
1452 becomes a high level, a second transfer transistor 1424 is turned
on, and current corresponding to light which enters a second photodiode
1422 flows to the second photodiode 1422 and the second transfer
transistor 1424, so that the potential (FD) of the signal charge storage
portion 1410 is lowered by discharge. When the potential (TRF2) of the
second transfer switch line 1452 becomes a low level, the second transfer
transistor 1424 is turned off, so that the potential (FD) of the signal
charge storage portion 1410 is held because the current path does not
exist again. This potential is output to the vertical output line 1470
through the first amplifier transistor 1408.

[0207] In driving of a third line, the potential (RST1) of the first reset
line 1461 becomes a high level again, so that the first reset transistor
1406 is turned on. Thus, the potential (FD) of the signal charge storage
portion 1410 is raised to VDD. Even when the potential (RST1) of the
first reset line 1461 becomes a low level and the first reset transistor
1406 is turned off, the potential (FD) of the signal charge storage
portion 1410 is held at VDD when a current path does not exist. Next,
when the potential (TRF3) of a third transfer switch line 1453 becomes a
high level, a third transfer transistor 1434 is turned on, and current
corresponding to light which enters a third photodiode 1432 flows to the
third photodiode 1432 and the third transfer transistor 1434, so that the
potential (FD) of the signal charge storage portion 1410 is lowered by
discharge. When the potential (TRF3) of the third transfer switch line
1453 becomes a low level, the third transfer transistor 1434 is turned
off, so that the potential (FD) of the signal charge storage portion 1410
is held because the current path does not exist again. This potential is
output to the vertical output line 1470 through the first amplifier
transistor 1408.

[0208] In driving of a fourth line, the potential (RST1) of the first
reset line 1461 becomes a high level again, so that the first reset
transistor 1406 is turned on. Thus, the potential (FD) of the signal
charge storage portion 1410 is raised to VDD. Even when the potential
(RST1) of the first reset line 1461 becomes a low level and the first
reset transistor 1406 is turned off, the potential (FD) of the signal
charge storage portion 1410 is held at VDD when a current path does not
exist. Next, when the potential (TRF4) of a fourth transfer switch line
1454 becomes a high level, a fourth transfer transistor 1444 is turned
on, and current corresponding to light which enters a fourth photodiode
1442 flows to the fourth photodiode 1442 and the fourth transfer
transistor 1444, so that the potential (FD) of the signal charge storage
portion 1410 is lowered by discharge. When the potential (TRF4) of the
fourth transfer switch line 1454 becomes a low level, the fourth transfer
transistor 1444 is turned off, so that the potential (FD) of the signal
charge storage portion 1410 is held because the current path does not
exist again. This potential is output to the vertical output line 1470
through the first amplifier transistor 1408. In driving of fifth to
eighth lines, sequential driving is performed as in the first to fourth
lines by control of the potential (RST2) of a second reset line.

[0209]FIG. 20 illustrates structures of four pixels arranged
longitudinally and laterally that are different from the structures in
FIG. 18. In the structures illustrated in FIG. 20, a reset line, a reset
transistor, and an amplifier transistor are used in common among two
pixels arranged longitudinally and two pixels arranged laterally. As in
the structures of four pixels arranged longitudinally, when the number of
transistors and the number of wirings are reduced, miniaturization due to
the decrease in the pixel area and reduction in noise due to the increase
in the light reception area of a photodiode can be realized. Drains of
transfer transistors in the four pixels arranged longitudinally and
laterally are electrically connected to each other, so that a signal
charge storage portion 1510 is formed. A source of a reset transistor
1506 and a gate of an amplifier transistor 1508 are connected to the
signal charge storage portion 1510.

[0210] The operation in the structures of four pixels arranged
longitudinally and laterally is described with reference to a timing
chart in FIG. 21. In driving of a first line, first, the potential (RST1)
of a first reset line 1561 becomes a high level, so that a first reset
transistor 1506 is turned on. Thus, the potential (FD) of the signal
charge storage portion 1510 is raised to VDD. The potential (RST1) of the
first reset line 1561 becomes a low level, so that the first reset
transistor 1506 is turned off. Even when the first reset transistor 1506
is turned off, the potential (FD) of the signal charge storage portion
1510 is held at VDD when a current path does not exist. Next, when the
potential (TRF1) of a first transfer switch line 1551 becomes a high
level, a first transfer transistor 1514 is turned on, and current
corresponding to light which enters a first photodiode 1512 flows to the
first photodiode 1512 and the first transfer transistor 1514, so that the
potential (FD) of the signal charge storage portion 1510 is lowered by
discharge. When the potential (TRF1) of the first transfer switch line
1551 becomes a low level, the first transfer transistor 1514 is turned
off, so that the potential (FD) of the signal charge storage portion 1510
is held because the current path does not exist again.

[0211] This potential is output to a vertical output line 1570 through a
first amplifier transistor 1508.

[0212] Next, the potential (RST1) of the first reset line 1561 becomes a
high level again, so that the first reset transistor 1506 is turned on.
Thus, the potential (FD) of the signal charge storage portion 1510 is
raised to VDD. The potential (RST1) of the first reset line 1561 becomes
a low level, so that the first reset transistor 1506 is turned off. Even
when the first reset transistor 1506 is turned off, the potential (FD) of
the signal charge storage portion 1510 is held at VDD when a current path
does not exist. Then, when the potential (TRF2) of a second transfer
switch line 1552 becomes a high level, a second transfer transistor 1524
is turned on, and current corresponding to light which enters a second
photodiode 1522 flows to the second photodiode 1522 and the second
transfer transistor 1524, so that the potential (FD) of the signal charge
storage portion 1510 is lowered by discharge. When the potential (TRF2)
of the second transfer switch line 1552 becomes a low level, the second
transfer transistor 1524 is turned off, so that the potential (FD) of the
signal charge storage portion 1510 is held because the current path does
not exist again. This potential is output to the vertical output line
1570 through the first amplifier transistor 1508. Outputs of the pixels
in the first line are sequentially output to the vertical output line
1570 through the two operations.

[0213] In driving of a second line, the potential (RST1) of the first
reset line 1561 becomes a high level again, so that the first reset
transistor 1506 is turned on. Thus, the potential (FD) of the signal
charge storage portion 1510 is raised to VDD. The potential (RST1) of the
first reset line 1561 becomes a low level, so that the first reset
transistor 1506 is turned off. Even when the first reset transistor 1506
is turned off, the potential (FD) of the signal charge storage portion
1510 is held at VDD when a current path does not exist. Then, when the
potential (TRF3) of a third transfer switch line 1553 becomes a high
level, a third transfer transistor 1534 is turned on, and current
corresponding to light which enters a third photodiode 1532 flows to the
third photodiode 1532 and the third transfer transistor 1534, so that the
potential (FD) of the signal charge storage portion 1510 is lowered by
discharge. When the potential (TRF3) of the third transfer switch line
1553 becomes a low level, the third transfer transistor 1534 is turned
off, so that the potential of the signal charge storage portion 1510 is
held because the current path does not exist again. This potential is
output to the vertical output line 1570 through the first amplifier
transistor 1508.

[0214] Next, the potential (RST1) of the first reset line 1561 becomes a
high level again, so that the first reset transistor 1506 is turned on.
Thus, the potential (FD) of the signal charge storage portion 1510 is
raised to VDD. The potential (RST1) of the first reset line 1561 becomes
a low level, so that the first reset transistor 1506 is turned off. Even
when the first reset transistor 1506 is turned off, the potential (FD) of
the signal charge storage portion 1510 is held at VDD when a current path
does not exist. Next, when the potential (TRF4) of a fourth transfer
switch line 1554 becomes a high level, a fourth transfer transistor 1544
is turned on, and current corresponding to light which enters a fourth
photodiode 1542 flows to the fourth photodiode 1542 and the fourth
transfer transistor 1544, so that the potential (FD) of the signal charge
storage portion 1510 is lowered by discharge. When the potential (TRF4)
of the fourth transfer switch line 1554 becomes a low level, the fourth
transfer transistor 1544 is turned off, so that the potential (FD) of the
signal charge storage portion 1510 is held because the current path does
not exist again. This potential is output to the vertical output line
1570 through the first amplifier transistor 1508. Next, driving of a
third line and driving of a fourth line are sequentially performed as in
the first and second lines by control of the potential (RST2) of a second
reset line 1562.

[0215]FIG. 22 illustrates structures where a transfer switch line is used
in common. In the structures illustrated in FIG. 22, a reset line, a
transfer switch line, a reset transistor, and an amplifier transistor are
used in common among two pixels arranged longitudinally and two pixels
arranged laterally. The transfer switch used in common is added to the
above structures where the reset line, the reset transistor, and the
amplifier transistor are used in common. When the number of transistors
and the number of wirings are reduced, miniaturization due to the
decrease in the pixel area and reduction in noise due to the increase in
the light reception area of a photodiode can be realized. Drains of
transfer transistors in the four pixels arranged longitudinally and
laterally are electrically connected to each other, so that a signal
charge storage portion is formed. A source of the reset transistor and a
gate of an amplifier transistor are connected to the signal charge
storage portion. In the structures, the transfer switch line is used in
common between two transfer transistors positioned longitudinally, so
that transistors which operate in a lateral direction and a longitudinal
direction concurrently are provided.

[0216] The operation of the structures where the transfer switch line is
used in common is described with reference to a timing chart in FIG. 23.
In driving of a first line and a second line, first, the potential (RST1)
of a first reset line 1665 and the potential (RST2) of a second reset
line 1666 become a high level, so that a first reset transistor 1616 and
a second reset transistor 1626 are turned on. Thus, the potential (FD1)
of a first signal charge storage portion 1610 and the potential (FD2) of
a second signal charge storage portion 1620 are raised to VDD. The
potential (RST1) of the first reset line 1665 and the potential (RST2) of
the second reset line 1666 become a low level, so that the first reset
transistor 1616 and the second reset transistor 1626 are turned off. Even
when the first reset transistor 1616 and second the reset transistor 1626
are turned off, the potential (FD1) of the first signal charge storage
portion 1610 and the potential (FD2) of the second signal charge storage
portion 1620 are held at VDD when current paths do not exist.

[0217] Next, when the potential (TRF1) of a first transfer switch line
1751 becomes a high level, a first transfer transistor 1614 and a third
transfer transistor 1634 are turned on, so that current corresponding to
light which enters a first photodiode 1612 flows to the first photodiode
1612 and the first transfer transistor 1614 and current corresponding to
light which enters a third photodiode 1632 flows to the third photodiode
1632 and the third transfer transistor 1634. Thus, the potential (FD1) of
the first signal charge storage portion 1610 and the potential (FD2) of
the second signal charge storage portion 1620 are lowered by discharge.
When the potential (TRF1) of the first transfer switch line 1751 becomes
a low level, the first transfer transistor 1614 and the third transfer
transistor 1634 are turned off, so that the potential (FD1) of the first
signal charge storage portion 1610 and the potential (FD2) of the second
signal charge storage portion 1620 are held because current paths do not
exist again. These potentials are output to a first vertical output line
1675 through a first amplifier transistor 1618 and a second vertical
output line 1676 through a second amplifier transistor 1628.

[0218] Next, the potential (RST1) of the first reset line 1665 and the
potential (RST2) of the second reset line 1666 become a high level again,
so that the first reset transistor 1616 and the second reset transistor
1626 are turned on. Thus, the potential (FD1) of the first signal charge
storage portion 1610 and the potential (FD2) of the second signal charge
storage portion 1620 are raised to VDD. The potential (RST1) of the first
reset line 1665 and the potential (RST2) of the second reset line 1666
become a low level, so that the first reset transistor 1616 and the
second reset transistor 1626 are turned off. Even when the first reset
transistor 1616 and the second reset transistor 1626 are turned off, the
potential (FD1) of the first signal charge storage portion 1610 and the
potential (FD2) of the second signal charge storage portion 1620 are held
at VDD when current paths do not exist.

[0219] Next, when the potential (TRF2) of a second transfer switch line
1752 becomes a high level, a second transfer transistor 1624 and a fourth
transfer transistor 1644 are turned on, so that current corresponding to
light which enters a second photodiode 1622 flows to the second
photodiode 1622 and the second transfer transistor 1624 and current
corresponding to light which enters a fourth photodiode 1642 flows to the
fourth photodiode 1642 and the fourth transfer transistor 1644. Thus, the
potential (FD1) of the first signal charge storage portion 1610 and the
potential (FD2) of the second signal charge storage portion 1620 are
lowered by discharge. When the potential (TRF2) of the second transfer
switch line 1752 becomes a low level, the second transfer transistor 1624
and the fourth transfer transistor 1644 are turned off, so that the
potential (FD1) of the first signal charge storage portion 1610 and the
potential (FD2) of the second signal charge storage portion 1620 are held
because current paths do not exist again. These potentials are output to
the first vertical output line 1675 through the first amplifier
transistor 1618 and the second vertical output line 1676 through the
second amplifier transistor 1628. Outputs of the pixels in the first line
and the second line are sequentially output to the first vertical output
line 1675 and the second vertical output line 1676 through the operation.

[0220] Driving of a third line and a fourth line is described. First, the
potential (RST2) of the second reset line 1666 and the potential (RST3)
of a third reset line 1667 become a high level, so that the second reset
transistor 1626 and a third reset transistor 1636 are turned on. Thus,
the potential (FD2) of the second signal charge storage portion 1620 and
the potential (FD3) of a third signal charge storage portion 1630 are
raised to VDD. The potential (RST2) of the second reset line 1666 and the
potential (RST3) of the third reset line 1667 become a low level, so that
the second reset transistor 1626 and the third reset transistor 1636 are
turned off. Even when the second reset transistor 1626 and the third
reset transistor 1636 are turned off, the potential (FD2) of the second
signal charge storage portion 1620 and the potential (FD3) of the third
signal charge storage portion 1630 are held at VDD when current paths do
not exist.

[0221] Next, when the potential (TRF3) of a third transfer switch line
1753 becomes a high level, a fifth transfer transistor 1654 and a seventh
transfer transistor 1674 are turned on, so that current corresponding to
light which enters a fifth photodiode 1652 flows to the fifth photodiode
1652 and the fifth transfer transistor 1654 and current corresponding to
light which enters a seventh photodiode 1672 flows to the seventh
photodiode 1672 and the seventh transfer transistor 1674. Thus, the
potential (FD2) of the second signal charge storage portion 1620 and the
potential (FD3) of the third signal charge storage portion 1630 are
lowered by discharge. When the potential (TRF3) of the third transfer
switch line 1753 becomes a low level, the fifth transfer transistor 1654
and the seventh transfer transistor 1674 are turned off, so that the
potential (FD2) of the second signal charge storage portion 1620 and the
potential (FD3) of the third signal charge storage portion 1630 are held
because current paths do not exist again. These potentials are output to
the second vertical output line 1676 through the second amplifier
transistor 1628 and the first vertical output line 1675 through the first
amplifier transistor 1618.

[0222] Next, when the potential (RST2) of the second reset line 1666 and
the potential (RST3) of the third reset line 1667 become a high level, so
that the second reset transistor 1626 and the third reset transistor 1636
are turned on. Thus, the potential (FD2) of the second signal charge
storage portion 1620 and the potential (FD3) of the third signal charge
storage portion 1630 are raised to VDD. The potential (RST2) of the
second reset line 1666 and the potential (RST3) of the third reset line
1667 become a low level, so that the second reset transistor 1626 and the
third reset transistor 1636 are turned off. Even when the second reset
transistor 1626 and the third reset transistor 1636 are turned off, the
potential (FD2) of the second signal charge storage portion 1620 and the
potential (FD3) of the third signal charge storage portion 1630 are held
at VDD when current paths do not exist.

[0223] Next, when the potential (TRF4) of a fourth transfer switch line
1754 becomes a high level, a sixth transfer transistor 1664 and an eighth
transfer transistor 1684 are turned on, so that current corresponding to
light which enters a sixth photodiode 1662 flows to the sixth photodiode
1662 and the sixth transfer transistor 1664 and current corresponding to
light which enters an eighth photodiode 1682 flows to the eighth
photodiode 1682 and the eighth transfer transistor 1684. Thus, the
potential (FD2) of the second signal charge storage portion 1620 and the
potential (FD3) of the third signal charge storage portion 1630 are
lowered by discharge. When the potential (TRF4) of the fourth transfer
switch line 1754 becomes a low level, the sixth transfer transistor 1664
and the eighth transfer transistor 1684 are turned off, so that the
potential (FD2) of the second signal charge storage portion 1620 and the
potential (FD3) of the third signal charge storage portion 1630 are held
because current paths do not exist again. These potentials are output to
the second vertical output line 1676 through the second amplifier
transistor 1628 and the first vertical output line 1675 through the first
amplifier transistor 1618. Outputs of the pixels in the third line and
the fourth line are sequentially output to the second vertical output
line 1676 and the first vertical output line 1675 through the operation.
Next, driving of a fifth line and driving of a sixth line are
sequentially performed as in the third and fourth lines by control of the
potential (RST3) of the third reset line 1667 and the potential (RST4) of
a fourth reset line.

[0224]FIG. 24 illustrates the entire CMOS image sensor. A reset terminal
driver circuit 2020 and a transfer terminal driver circuit 2040 are
provided on opposite sides of a pixel matrix 2100 including pixel
portions 2000. The driver circuits are provided on the opposite sides of
the pixel matrix 2100 in FIG. 24; however, the driver circuits may be
provided only one side. In addition, a vertical output line driver
circuit 2060 is provided in a direction vertical to wirings for
outputting signals from the driver circuits.

[0225] The reset terminal driver circuit 2020 and the transfer terminal
driver circuit 2040 are driver circuits for outputting signals having
binary values (a low potential and a high potential); thus, driving can
be performed with a combination of a shift register 2200 and a buffer
circuit 2300, as illustrated in FIG. 25. These driver circuits can be
formed using bulk transistors or thin film transistors. In particular,
these driver circuits are preferably formed using bulk transistors
including silicon semiconductors that can be used for the formation of
complementary (CMOS) transistors.

[0226] The vertical output line driver circuit 2060 can include a shift
register 2210, a buffer circuit 2310, and analog switches 2400, as
illustrated in FIG. 26. Vertical output lines 2120 are selected with the
analog switches 2400, and an image signal is output to an image output
line 2500. The analog switches 2400 are sequentially selected by the
shift register 2210 and the buffer circuit 2310. The vertical output line
driver circuit 2060 can be formed using a bulk transistor or a thin film
transistor. In particular, the vertical output line driver circuit 2060
is preferably formed using a bulk transistor including a silicon
semiconductor that can be used for the formation of a complementary
transistor.

[0227]FIG. 27 illustrates examples of the shift register and the buffer
circuit. Specifically, FIG. 27 illustrates examples of a shift register
2220 including a clocked inverter and a buffer circuit 2320 including an
inverter. The shift register and the buffer circuit are not limited to
these circuits. Further, the structures of the reset terminal driver
circuit 2020, the transfer terminal driver circuit 2040, and the vertical
output line driver circuit 2060 are not limited to the above structures.

[0228] The solid-state image sensor in any of the above embodiments can be
used in a variety of electronic devices (including an amusement machine).
For example, the solid-state image sensor can be used in an electronic
device which has a unit for acquiring image data, such as a digital
camera, digital video camera, a mobile phone, a portable game machine, or
a portable information terminal

[0229] This embodiment mode can be combined with any of the other
embodiments as appropriate.

[0230] This application is based on Japanese Patent Application serial no.
2009-255271 filed with Japan Patent Office on Nov. 6, 2009, the entire
contents of which are hereby incorporated by reference.

Patent applications by Jun Koyama, Sagamihara JP

Patent applications by Shunpei Yamazaki, Setagaya JP

Patent applications by SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Patent applications in class SEMICONDUCTOR IS AN OXIDE OF A METAL (E.G., CUO, ZNO) OR COPPER SULFIDE

Patent applications in all subclasses SEMICONDUCTOR IS AN OXIDE OF A METAL (E.G., CUO, ZNO) OR COPPER SULFIDE