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You Will Learn:

How PCIe is backward compatible with PCI and PCI-X

Motivation for PCIe serial model

Software view of the topology

Definition and responsibilities of each layer in the PCIe interface

PCIe transaction types and definitions

The routing method used for each request and completion

Roles of the Flow Control and ACK / NAK features

Purpose and behavior of the logical blocks within the Physical Layer

Error types and the associated levels of severity

Who Should View?

This course provides a great overview of the basics of the PCI Express 2.0 technology and is for individuals who need to know the fundamentals of PCI Express but not the low-level implementation or validation details. This course was designed with FAEs and managers in mind but is also a great jump-start for design/validation/verification engineers wanting to learn this IO bus. If you are looking for a course that covers more of the low-level details and features, please check out our Comprehensive PCI Express 2.0 eLearning Course.

Course Outline:

PCI Background

- Describes the pieces of PCI and PCI-X that are still relevant for PCIe: configuration, address spaces, interrupts, split transaction, etc.