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Abstract:

A semiconductor device having a low power mode includes a buffer circuit
associated with an interface pad, a power management controller (PMC),
and a wakeup unit for waking up a part of the device from the low power
mode. The buffer circuit is disabled in the low power mode by asserting a
power on reset (POR) signal associated with the PMC. A wakeup signal is
generated and provided to the wakeup unit from an analog power supply
associated with the buffer circuit.

Claims:

1. A semiconductor device having a low power mode, comprising: at least
one interface pad; a power management controller (PMC) coupled to said
interface pad; and a wakeup unit for waking up at least a part of said
semiconductor device from said low power mode, wherein pads are disabled
in said low power mode by asserting a power on reset (PoR) signal
associated with said PMC and wherein a wakeup signal is generated to said
wakeup unit from an analog power supply associated with said at least one
interface pad.

2. The semiconductor device of claim 1, wherein said semiconductor device
includes a system on a chip (SoC) device.

3. The semiconductor device of claim 1, wherein said wakeup signal is
applied to said wakeup unit via a high to low level shifter.

6. The semiconductor device of claim 4, wherein said wakeup signal and
said gating signal are applied to respective inputs of a logical AND
gate.

7. The semiconductor device of claim 6, wherein said gating signal is
applied to said AND gate via a low to high level shifter.

8. The semiconductor device of claim 6, wherein the output of said AND
gate is applied to said wakeup unit.

9. The semiconductor device of claim 8, wherein said output of said AND
gate is applied to said wakeup unit via a high to low level shifter.

10. A method of generating a wakeup signal to a wakeup unit associated
with a semiconductor device, said semiconductor device having a low power
mode and including at least one interface pad, a power management
controller (PMC) and said wakeup unit, said method including the steps
of: asserting a power on reset (POR) signal associated with said PMC; and
generating said wakeup signal from an analog power supply associated with
said at least one interface pad.

11. The method of claim 10, wherein said semiconductor device includes a
system on a chip (SoC) device.

12. The method of claim 10, including applying said wakeup signal to said
wakeup unit via a high to low level shifter.

13. The method of claim 10, including gating said wakeup signal via a
gating signal indicative of package associated data.

14. The method of claim 13, wherein said gating signal is obtained from
flash memory adapted to store package data associated with said
semiconductor device.

15. The method of claim 13, including applying said wakeup signal and
said gating signal to respective inputs of a logical AND gate.

16. The method of claim 15, including applying said gating signal to said
AND gate via a low to high level shifter.

17. The method of claim 15, including applying the output of said AND
gate to said wakeup unit.

18. The method of claim 17, including applying said output of said AND
gate to said wakeup unit via a high to low level shifter.

Description:

BACKGROUND OF THE INVENTION

[0001] The present invention relates to semiconductor devices and more
particularly, to a low power wake-up architecture for system on a chip
(SOC) semiconductor devices including SOC circuitry designed for use with
multiple package types and packages employing various pin counts.

[0002] Microcontroller units (MCUs) such as those used in SOCs typically
have a low power mode including power gating for a major part of a core
of the SOC. To exit from the low power mode, typically an external wakeup
source provides a wake-up signal to the SOC through input/output (I/O)
pads of the SOC. The I/O pads include I/O buffers for driving loads
and/or to provide isolation against external shocks such as electrostatic
discharge (ESD).

[0003] FIG. 1 shows a conventional buffer circuit 10 associated with an
I/O pad (not shown) that has an input buffer 11 that receives an input
signal from the I/O pad and generates a wakeup path signal (Ipp_ind). An
input signal (Ipp_do) to the buffer circuit 10 is routed through an
output buffer or driver 12. The buffer circuit 10 also receives a power
on reset (POR) signal. However, this POR signal is separate from a
general POR signal and this separate POR signal is provided to the buffer
circuits connected to chip wakeup circuitry. This separate POR signal is
inactive in low power mode.

[0004] The output buffer 12 may be disabled in low power mode, but input
buffer 11 remains enabled by keeping the core supply to the input buffer
11 active to enable the wakeup path, which is shown as "core supply ON"
input to the buffer circuit 10. In order to function, an IO supply to the
buffer circuit 10 also is ON, shown as "IO supply ON". However, keeping
the input buffer 11 active adds significant power overhead that can use
an extra 5-10 μA of current in a large circuit.

[0005] The requirement to provide the core supply to input buffers while
in low power mode also presents a physical design overhead since an
always ON power supply must be routed to selected pads/buffers. To
minimize risk of shorting and avoid current leakage the layout and design
of power supplies for pads/buffers should be separated from power
supplies that may be OFF in low power mode. However this requirement
increases complexity of the pad ring since a separate supply rail is
needed to supply these pads/buffers. Customized glue logic may also be
required for different pad ring components. Further, such custom logic
requirements may not be available for circuits designed using a generic
I/O library.

[0006] Therefore, it would be desirable to have a low power architecture
for a semiconductor device that does not need to maintain I/O pads in an
always ON state. It further would be desirable to be able to remove the
requirement of providing a core power supply to the I/O pads.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The following detailed description of a preferred embodiment will
be better understood when read in conjunction with the appended drawings.
The present invention is illustrated by way of example and is not limited
by the accompanying figures in which like references indicate similar
elements. It is to be understood that the drawings are not to scale and
have been simplified for ease of understanding the invention.

[0009]FIG. 2 is a schematic circuit diagram of an I/O pad buffer circuit
with a wakeup path according to one embodiment of the present invention;

[0010]FIG. 3 is a schematic block diagram of a wake-up architecture in
accordance with an embodiment of the present invention; and

[0011]FIG. 4 is a schematic block diagram of a wakeup architecture for a
multi-package device in accordance with an embodiment of the present
invention; and

[0012]FIG. 5 is a table showing the decode logic for wakeup gating
signals associated with the wakeup architecture of FIG. 4.

DETAILED DESCRIPTION OF THE INVENTION

[0013] According to one aspect, the present invention provides a
semiconductor device having a low power mode and including at least one
interface pad, a power management controller (PMC) and a wakeup unit for
waking up at least a part of said device from said low power mode,
wherein pads are disabled in said low power mode by asserting a power on
rest (POR) signal associated with said PMC and wherein a wakeup path is
provided to said wakeup unit from an analog power supply associated with
said at least one interface pad. The semiconductor device may comprise a
system on a chip (SOC) device.

[0014] The wakeup signal may be applied to the wakeup unit via a high to
low level shifter. The wakeup signal may be gated via a gating signal
indicative of package associated data. The gating signal may be obtained
from flash memory adapted to store package data associated with the
semiconductor device.

[0015] The wakeup signal and the gating signal may be applied to
respective inputs of a logical AND gate. The gating signal may be applied
to the AND gate via a low to high level shifter. The output of the AND
gate may be applied to the wakeup unit via a high to low level shifter.

[0016] According to another aspect of the present invention, there is
provided a method of generating a wakeup signal to a wakeup unit
associated with a semiconductor device, said semiconductor device having
a low power mode and including at least one interface pad, a power
management controller (PMC) and said wakeup unit. The method includes the
steps of asserting a power on reset (POR) signal associated with said PMC
and generating said wakeup signal from an analog power supply associated
with said at least one interface PAD.

[0017] Referring to FIG. 2, a buffer circuit 20 associated with an I/O pad
(not shown) in accordance with an embodiment of the invention is shown.
Like the conventional buffer circuit 10, the buffer circuit 20 includes
an input buffer 21 that receives an input signal from the pad and outputs
a signal lpp_ind to a wakeup unit (not shown), and an output buffer 22
that receives an internal signal lpp_do and generates an output signal to
the pad. Power to the buffer circuit 20 may be disabled by asserting the
power on reset (POR) signal for the I/O PAD connected to the buffer
circuit 20. When buffer circuit 20 is in the disabled or low power mode
the core supply is OFF or floating. In the disabled or low power mode
there is no need to gate control signals associated with the I/O PAD to
be at a specific or safe stated level. This may reduce routing complexity
of the associated Pad facilitating a reduction of gate count.

[0018] Since the core power supply of the buffer circuit 20 is OFF, an
alternative signal is used to wakeup the system. The alternate signal may
be obtained via a direct resistive path from the associated pad. In this
embodiment of the present invention, a wakeup signal 23 (Pad_res) may be
propagated via resistor R1 (e.g., 200 ohms). The voltage of the wakeup
signal 23 (Pad_res) is comparable to the analog supply voltage at the I/O
PAD (e.g., 3.3 to 5 volts), so preferably the wakeup signal 23 is shifted
to core supply level voltage (e.g., 1.2 volts) before being applied to a
wakeup unit. Thus, the POR signal used for the buffer circuit 20 may be
the same POR signal that is used for all of the I/O pad buffer circuits,
whereas for the conventional buffer circuit 10, a separate POR signal is
needed for wakeup buffer circuits.

[0019]FIG. 3 shows a wakeup path for the buffer circuit 20, which
includes a level shifter 31 and a wakeup unit 32. The wakeup signal 23
from the resistor R1 of the buffer circuit 20 is provided to the level
shifter 31, which level shifts the wakeup signal 23. The level shifter 31
may be a DC level shifting circuit. The level shifting circuit 31 may
include an op amp based DC shifting circuit or the like. The output of
the level shifting circuit 31 is applied to the wakeup unit 32.

[0020] As discussed above, a single SOC device may be used in multiple
packages including packages employing various pin counts. For example, in
some packages many of the pads may be unbonded, (i.e., no bond wire
connected to the pad) which may cause the corresponding wakeup lines to
float. Unbonded pads may also increase functional current in an
associated level shifter. To avoid current issues in the level shifter it
is desirable to isolate wakeup signals to such unbonded pads.

[0021] Individual pads may be isolated by accessing device options inside
a flash memory of an associated microcontroller unit (MCU) to access
package associated information or data stored in the flash memory. This
package data may be used to block certain functionality notwithstanding
that such options are generally not accessible to end users. In one
embodiment of the present invention, the package data is read from the
flash memory, decoded, and used to isolate pad wakeup signals that are
not being used in a specific package.

[0022]FIG. 4 is a schematic block diagram of a low power architecture for
a single die SOC device that may be assembled in multiple package types
(e.g., package types 176, 208, 324 discussed with reference to FIG. 5
below). In the embodiment of FIG. 4, the buffer circuit 20 is connected
to an unused or unbonded pad and has the wakeup signal 23 generated from
the analog power supply associated with the pad.

[0023] In order to isolate the wakeup signal since it is associated with
an unbonded pad, package information is read from the flash memory and
provided to decode logic 41 and then is decoded and applied to an input
of AND gate 42. The output of the AND gate 42 is used to gate the wakeup
signal 23 that is provided to the wakeup unit 32. As previously
discussed, the wakeup signal may be level shifted before being provided
to the wakeup unit 32 such as with the level shifter 31. The decoded
package information also may be level shifted (low to high) before being
provided to the AND gate 42 with a level shifter 43.

[0024] To reduce current leakage, gating of the wakeup signal (Pad_res) 23
by the AND gate 32 is performed at an analog voltage level (3.3 v to 5 v)
rather than core voltage level (1.2 v). Because the voltage obtained from
the package decode logic 41 is at the lower core voltage level (e.g., 1.2
v), the decoded package information signal is shifted to a higher level
via the low to high level shifter 43. The level shifter 43 may be
configured in any suitable manner and by any suitable means. Similarly,
because the gated wakeup signal at the output of AND gate 42 is at an
analog voltage level (e.g., 3.3 v to 5 v), the gated wakeup signal needs
to be shifted to a lower level (e.g., 1.2 v) via the high to low level
shifter 31 before being applied to the wakeup unit 32.

[0025]FIG. 5 is a table including examples of wakeup gating signals Sig1,
Sig2, Sig3 associated with package types 176, 208, and 324. The table
shows that wakeup pads for package type 176 are gated with Sig1. Sig1 is
logical "1" if the package type is 176 and is logical "0" if the package
is not type 176. Sig1 is used to gate group "G1" pins (e.g., PM10)
associated with a package type 176.

[0026]FIG. 5 also shows package types 208 and 324, which are gated with
Sig2. Sig2 is logical "0" if the package type is 176 and is logical "1"
otherwise (not Sig1). Sig2 is used to gate group "G2" pins (e.g., PM3,
PL9, PK7, PL0, PL2) associated with package types 208, 324.

[0027] Table 1 further show that package type 324 is gated with Sig3. Sig3
is logical "1" if the package type is 324 and is logical "0" otherwise
(not package type 324). Sig3 is used to gate group "G3" pins (e.g., PN0,
PN2, PN10, PO2) associated with a package type 324.

[0028] The proposed wakeup approach eliminates a need to power up wakeup
pads in low power mode. Because the approach uses a global POR signal
from a PMC to disable I/0 digital devices, a need to safe state I/0
controls in lower power mode may be avoided. This saves gate circuit area
and routing overhead.

[0029] The proposed wakeup scheme also works well with a multi-function
and multi-purpose design because it does not require special wakeup
functionality inside I/O drivers. Also unbonded (e.g., pads not connected
to a lead of a lead frame) wakeup I/Os can be marked using package decode
bit data to avoid short circuit currents due to floating input signals.

[0030] In a conventional wakeup implementation such features would require
customized I/O design or SoC integration as well as software overhead for
each package type in order to pull-up unbonded pads.

[0031] As is evident from the foregoing discussion, the present invention
provides a low power wakeup architecture for a SoC semiconductor device.
While the preferred embodiments of the invention have been illustrated
and described, it will be clear that the invention is not limited to
these embodiments only. Numerous modifications, changes, variations,
substitutions and equivalents will be apparent to those skilled in the
art without departing from the spirit and scope of the invention as
described in the claims.