Working scheme

n.u.m.a. there is also an other working schema, called "numa", seeFlameman/numa, useful with a great amount of cpu (cpu >> 8)

it seems that the dual-CPU V460 is featuring a symmetrical architecture allowing the two 68060 CPUs to operate as either tightly-coupled coprocessors sharing the same operating system and peripherals or as two independent CPUs running separate operating systems across separate I/O channels.

If this info is right it should be possible to assign different interrupt level schemes to each CPU via a programmable interrupt control register.
In all of these possible arrangements, the dual CPU V460 Series can provide full multi-ported memory access by both CPUs, the VMEbus, and both EZ-bus modules with varying levels of memory protection as required.

Notes: * This row of pins on P2 connect to the pin listed in row B of the EZ-bus connector (P4).

** This row of pins on P2 connect to the pin listed in row A of the EZ-bus connector (P4).

!!!warning!!!

Pin row B of the P2 backplane is defined
by VMEbus specifications and is bussed
across the entire backplane. Pin rows A
and C are user configured and, if con–
nected at all, are normally connected to
adjacent slots via wirewrap or special ca-
bles.
Because the P2 pinout may vary between
backplanes or even slots in the same
backplane, DO NOT INSTALL the V460
Series into a system slot whose P2
backplane is not compatible with the
V460 Series’ P2 pin-out. Failure to
observe this warning can cause the
complete destruction of many on-board
components and also voids the product
warranty.
The V460 Series pin-out meets standard
VME specifications for row B, but rows A
and C will vary according to the EZ-bus
daughter module installed. Daughter
board pinouts are shown in the
associated daughter module manual. If
no daughter module is present, P2 back-
plane rows A and C are defined as no-
connects.
For a complete list of the V460 Series P2
assignments, see the VMEbus connectors
(P1-P2) chapter in Section 7.

Bootstrap

On V460 Series dual-68060 models, the following boot architecture is
used:

CPU-X executes from EPROM0 at 0xFE000000 to 0xFE0FFFFF

CPU-Y executes from EPROM1 at 0xFE400000 to 0xFE4FFFFF or 0xFD000000 to 0xFDFFFFFF

except for the first 3 fetches in boot state in which CPU-X fetches from PROM0 and CPU-Y fetches from PROM1
either 68060 can execute from either or both of the EPROMs.

about system fail

* * * * * * * * * * * * * * * * * * * * * * * *
ACFail\
* * * * * * * * * * * * * * * * * * * * * * * *
The two red LEDs indicate the run status of the board:
Fail Indicates the SysFail status of the board.
When the CPU is reset (either by the VMEbus
SysRes\ line or the front panel RESET toggle),
the Fail LED turns on
and the board drives the VME SysFail\ signal.
During normal operation the system boot software
clears this condition shortly after RESET.
The SysFail LED and driver signal are cleared
by performing a write of a 0C to
the Primary Mode register at 0XFE38 0003.
The program may also turn this LED on
(i.e. assert SysFail on the VMEbus)
by writing a 04 to 0xFE38 0003.
Halt On single-68060 model boards, this LED provides
a visual indication that the on-board CPU has HALTed.
On dual-68060 boards, this LED indicates that
one or both CPUs has HALTed. If only one CPU has HALTed,
it is possible to identify which one by also looking at
the X and Y LEDs.
Generally, the LED for the HALTed CPU is NOT lit.
However, this indication is very dependent on
the application being run
and how closely coupled the two CPUs are operating
Bus error
time out
Generates a bus error time-out signal if one or
both of the VMEbus data strobes remain asserted
for longer than a specific interval that can be set
under software control.
System reset
generator
Generates a VMEbus reset signal upon system
power-up, upon a board-level reset, and 100
microseconds after the VME ACFail signal is
asserted