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Note In the Ivy Bridge Intel devoted much more emphasis to graphics processing than in the Sandy Bridge to compete with AMD’s graphics superiority. Contrasting the die plots of Ivy Bridge vs Sandy Bridge (at the same feature size)-2 [12] Intel’s Ivy Bridge (3)

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3.2.4 AMD’s Swift Fusion APU plan

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Preliminaries In 10/2006 AMD acquired the graphics firm ATI and at the same day they announced that “AMD plans to create a new class of x86 processors that integrate the central processing unit (CPU) and graphics processing unit (GPU) at the silicon level, codenamed “Fusion [13].” Remark Although in the above statement AMD designated the silicon level integration of the CPU and GPU as the Fusion initiative, in some other publications they call both the package level and the silicon level integration of the CPU and GPU as the Fusion technology, as shown in the next figure [14] AMD’s Swift Fusion APU plan (1)

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Extended interpretation of the term Fusion technology in some AMD publications [14] Despite this disambiguation, subsequently AMD understood the term Fusion usually as the silicon level integration of the CPU and the GPU AMD’s Swift Fusion APU plan (2)

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In 12/2007 at their Financial Analyst Day AMD gave birth to a new term by designating their processors implementing the Fusion concept as APUs (Accelerated Processing Units). At the same time AMD announced their first APU family called the Swift family [15] as well AMD’s Swift Fusion APU plan (3)

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In 11/2008 again at their Financial Analyst Day AMD postponed the introduction of Fusion-based APU processors until the company transitions to the 32 nm technology [16] [17] AMD’s Swift Fusion APU plan (4) No Swift APU!

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This is a similar move as done by Intel with their 45 nm Havendale (DT) and Auburndale (M) in-package integrated multi-chip CPU+GPU projects. As leaked from industry sources in 1/2009 Intel canceled their 45 nm multi-chip processor plans in favor of 32-nm multi-chip processors to be introduced in Q1/2010 [18]. Remark AMD’s Swift Fusion APU plan (5)

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3.2.5 AMD’s K12 (Llano)-based APU lines

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3.2.5 AMD’s K12 (Llano)-based APU lines (1) AMD’s Llano-based APU lines [19] Introduced: 6/2011. The Llano line belongs to the Fusion APU (Accelerated Processing Unit) series as it includes beyond a number of CPUs also a GPU to accelerate vision computing (graphics and media). Processors of the Llano lines have up to 4 CPU cores and a GPU. Nevertheless, AMD sells Llano based desktop lines as well with disabled GPUs. These lines are branded as Athlon II X4/X2 or Sempron lines. 32 nm technology, 228 mm 2, 1450 mtrs.

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Announced in 6/2012 Launched: 10/2012 The Trinity APU is based on the Piledriver Compute Module, which is a redesign of the ill fated Bulldozer Compute Module AMD’s Piledriver-based Trinity desktop APU line (1) 32 nm feature size, 226 mm2, billion transistors (almost the same figures as for Lliano)

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The links between each section of the APU follow in the same footsteps as the previous generation but AMD has refined certain interconnects with the goal of speeding up information transfers. The AMD Fusion Compute Link is still considered to be a medium bandwidth connection which manages the complex interaction between the onboard GPU, the CPU’s cache and the system memory. Unlike in the past, AMD has finally refined this interconnect, giving the GPU direct access to a coherent memory space while the CPU can now directly access the GPU’s dedicated framebuffer if needed. This is one of the primary reasons why Trinity’s theoretical data throughput has jumped from 572 GFLOPS to 736 GFLOPS. The Radeon Memory Bus on the other hand is the all-important link between the onboard graphics coprocessor and the primary on-chip memory controller. Rather than acting like a traffic cop (a la Fusion Compute Link) which tries to direct the flow of information, this memory bus is all about the GPU having unhindered high bandwidth access to the system’s memory controllers. In the previous generations of AMD IGPs, before Llano came around, the Northbridge’s graphics processor had to jump through a series of hoops before gaining access to onboard memory which is partially why 128MB of “SidePort” memory was sometimes added. However, the APU’s single chip, all in one solution allows for the elimination of many potential bottlenecks.

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This unit adds virtual address access discrete graphics, allowing an external GPU to directly access the same virtual address space as the CPU through page tables. As you can imagine, this is a key part of the programming model for AMD’s Heterogeneous Systems Architecture (HSA). Trinity