Note the use of declaration initialization for the clock signal. We need this becuase the default initialization value of a std_ulogic signal is 'U'. The first time the signal assignment executes, not 'U' is 'X' and the remaining executions (every 5 ns) of this statement yield not 'X' is 'X' - no clock sequence at all. The disadvantage of this approach is that the clock runs forever - and so will the simulation!

Rather than continuous generation, what we would like to do is implement the clock generator inside a process so that a known number of clock cycles can be generated, courtesy of a for loop.

Note that a VHDL constant is used to allow easy maintainance of the simulation duration. However, this piece of code doesn't really do the trick. After 320 cycles, the loop exits and the process is re-invoked, generating sets of 320 cycles continuously. In order to stop the simulation from running forever due to continuous clock cycle generation, we can append a wait statement to this process to suspend the process indefinitely after one pass of 320 cycles.