Springsoft announces new tool for chip finishing

Most EDA tools are capable of performing several tasks, even though they may not be optimized for all of them. It is basically too expensive to create point tools for every task. But priorities change over time and what may have been a secondary task at one process node may become a lot more important in another one. That may be the case with an announcement from Springsoft today in which they announce a new tool. Laker™ Blitz is a chip-level layout editor targeting chip finishing applications.

Blitz enables viewing and editing of chip-level layouts to streamline tapeout-to-manufacturing operations. They claim that it is ideally suited for designs with massive data sets, such as advanced-node system-on-chip (SoC) implementations and large memory chips that are widely used in consumer electronics.

Chip finishing is one of the last physical design steps before manufacturing and generally requires engineers to merge large design files, run design rule checks (DRC), and make final corrections, all while under enormous schedule pressures. Currently, they most likely use layout tools or viewers that have been optimized for other tasks and have limited performance or minimal editing capabilities.

According to their press release Blitz is optimized for speed and user productivity during the chip finishing part of the design cycle, in keeping with the company’s focus on providing specialized solutions that address key pain points in the chip development process. They claim that it loads and exports GDSII data files 5 to 20 times faster than conventional layout tools, offers more robust layout editing capabilities than most high-capacity layout viewers, and provides an extensive library of Tool Command Language (Tcl) extensions for automating data manipulation.

What makes it so fast – well they say that they have a new database technology that can handle the rapid import, editing and export of massive GDSII data files, which are typically tens of gigabytes or more in size for current generation chips. This enables designers to easily load, view and manipulate chip-level layouts with access to the complete layout hierarchy. They can perform cell, window or full-chip DRCs, and then find and fix violations without leaving the Laker Blitz environment. Layout editing and debug at the chip-level is further simplified with advanced features, such as net highlighting commands to trace critical nets.

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