III-V silicon lasers integrated on 200mm CMOS wafers

December 06, 2017 //
By Julien Happich

French research institute Leti announced it has successfully integrated hybrid III-V silicon lasers on 200mm silicon wafers using a standard CMOS process flow.

The project, carried out in the framework of the IRT Nanoelec program and coordinated by Leti, demonstrated that the hybrid device’s performance is comparable to the reference device fabricated with the current process on 100mm wafers. "The entire process can be done in a standard CMOS fabrication line with conventional process and materials", notes Bertrand Szelag, co-author of a paper titled “Hybrid III-V/Si DFB Laser Integration on a 200mm Fully CMOS-compatible Silicon Photonics Platform” just presented at IEDM 2017.

The fabrication flow is fully planar and compatible with large-scale integration on silicon-photonic circuits, which enables packaging compatibility with CMOS driving circuits.

The integration required managing a thick silicon film, typically 500nm thick, for the hybrid laser, and a thinner one, typically 300nm, for the baseline silicon-photonic platform. This meant locally thickening the silicon by adding 200nm of amorphous silicon via a damascene process, which presents the advantage of leaving a flat surface favourable for bonding III-V silicon. The laser can then be integrated on a mature silicon photonic platform with a modular approach without compromising the baseline process performance.

The novelty of the approach also included using innovative laser electrical contacts that do not contain any noble metals, such as gold, relying on a Nickel-based metallization and tungsten plugs connecting the device to routing metal lines.

Next, the researchers want to integrate the laser with active silicon-photonic devices such as a modulator and a photodiode, with several interconnect metal levels in a planarized backend. Then they expect III-V die bonding to replace III-V wafer bonding in order to process lasers on the entire silicon wafer.