MINIMISING DYNAMIC POWER CONSUMPTION IN ON-CHIP NETWORKS Robert

MINIMISING DYNAMIC POWER CONSUMPTION IN ON-CHIP NETWORKS Robert Mullins Computer Architecture Group Computer Laboratory University of Cambridge, UK

Communication-Centric Architectures • Future performance gains will primarily come from increasing the number of IP cores in a system not their complexity or operating frequency • Many reasons: – – – Diminishing returns from simply scaling what we have Energy efficiency Complexity Fault tolerance Economics 2

On-Chip Networks • An efficient general purpose chip-wide communication infrastructure is becoming essential • One flexible networking option is to use packetswitched networks with support for virtualchannels 3

Aims of this work • Apply existing power saving techniques to an onchip network design – e. g. clock and signal gating, gate-level optimisations etc. – Importance of applying such techniques before making comparisons • Measure power consumption and provide an accurate breakdown of where the remaining power is dissipated • Where is best place to look for future power savings? 7

Gate-Level Optimizations and Signal Gating • Automated signal gating and gate-level power optimisations had minimal impact • Inserting signal gating logic manually did reduce input FIFO power requirements significantly • The reported results could be further improved (by 12%) by enabling logic optimisation across module boundaries – This was restricted to accurately determine where power is dissipated 12

Analysis of Power Consumption Power consumption of a single router and its links • Simple power optimisations can quarter power requirements + many more opportunities to save power • Network is ~5% of core area • Perhaps 10% of system power at present • Don’t make comparisons without optimizing power! 13

Challenges and Future Work • These are early results in a much more rigorous study on the power requirements of networked on-chip comummunication – Much more soon! • Exploiting a general-purpose on-chip network – – Exploiting execution diversity to improve energy-efficiency Multi-use platforms and Virtual-IP Fault tolerance Networks of processing elements or networks that process? • Scope for removing unnecessary interfaces and boundaries • Impact of networking on IP and processor core design 19