Course Description

The Xilinx® Zynq® All Programmable SoC provides a new level of system design capabilities. This course provides experienced system architects with the knowledge to effectively architect a Zynq All Programmable system on a chip.

This course presents the features and benefits of the Zynq architecture for making decisions on architecting a Zynq All Programmable SoC project. It covers the architecture of the ARM® Cortex®-A9 processor-based processing system (PS) and the integration of programmable logic (PL) at a sufficiently deep level that a system designer can successfully and effectively utilize the Zynq All Programmable SoC.

The course also details the individual components that comprise the PS, I/O peripherals, timers, and caching, as well as the DMA, interrupt, and memory controllers. Emphasis will be placed on effective access and usage of the PS DDR controller from PL user logic, efficient PL-to-PS interfacing, and design techniques, tradeoffs, and advantages of implementing functions in the PS or the PL.

Engineers who need a deeper understanding of the ARM® Cortex®-A9 processor should attend ARM Cortex-A9 for Zynq System Design, which describes the principles and internal details of the Cortex®-A9 processor architecture itself, as opposed to the architecture of the Zynq processing system (PS) of which it is a part.

Training Duration

4 sessions

Who Should Attend?

System architects who are interested in architecting a system on a chip using the Zynq All Programmable SoC.

Prerequisites

Digital system architecture design experience

Basic understanding of microprocessor architecture

Basic understanding of C programming

Basic HDL modeling experience

Software Tools

Vivado® Design or System Edition 2017.1

Skills Gained

After completing this comprehensive training, you will know how to:

Describe the architecture and components that comprise the Zynq All Programmable SoC processing system (PS)

Relate a user design goal to the function, benefit, and use of the Zynq All Programmable SoC

Effectively select and design an interface between the Zynq PS and programmable logic (PL) that meets project goals

Analyze the tradeoffs and advantages of performing a function in software versus PL

Lab 3 (partial demo): Using DMA on the Zynq All Programmable SoC – Experiment with effectively using the PS DMA controller to move data between DDRx memory and a custom PL peripheral.

Lab 4: Impact of Port Selection on System Performance – Evaluate debugging the hardware and software components of a Zynq design.

Lab 5 (Partial demo): Debugging on the Zynq All Programmable SoC – Evaluate debugging the hardware and software components of a Zynq design.

Lab 6 (Partial demo): Running and Debugging a Linux Application on the Zynq All Programmable SoC – Explore a software application executing under the Linux operating system on the Zynq All Programmable SoC.