Macro-fusion and micro-fusion. To increase performance and reduce power, specific combinations of two x86 instructions are combined (fused) into one executable micro-op (macro-fusion). For example, an x86 compare instruction followed by a jump instruction is fused into a single micro-op and executed in one clock. Similarly, multiple micro-ops controlling different execution ports can be fused into a single fused micro-op (micro fusion).

Sophisticated branch prediction. The VIA Isaiah Architecture implements a very powerful and unique branch prediction algorithm using eight different predictors in two different pipeline stages. The first fetch pipeline stage contains three predictors of conditional branch behavior (each more accurate for a particular type of branch), a predictor of which of these predictors to use, and a separate return predictor. The translate stage (where more information about the instructions is known) contains a return predictor, a conditional branch “overflow” predictor, and a default predictor.

Each predictor is designed to be more accurate for a particular type of branch at a particular point in the pipeline. The predictors interact and “vote” to obtain the final prediction.

Smart cache subsystem. The VIA Isaiah Architecture includes many innovations in the cache subsystem that lead to very efficient use of total cache area (and thus cache power). For example, our 64-KB L1 caches are twice as large as Intel’s 32-KB caches and have twice the associativity (16-way versus 8-way). Similarly, our L2 cache (1 MB in the initial product) is 16-way associative while the equivalent-size Intel L2 caches are only eight-way associative. In addition, our L2 cache is “exclusive” versus Intel’s “inclusive” design. This means that our L1 caches contents do not reside in our L2 cache, thus increasing the effective size of our L2 cache over the Intel approach.

Another feature unique to the VIA Isaiah Architecture is that many of the data prefetch algorithms load prefetched data into a special 64-line prefetch cache as opposed to loading it directly into the L2-cache (such as Intel does). This approach improves the efficiency of the L2 cache and the smaller size is adequate since the useful lifetime of prefetched data is short.

Powerful data-prefetch units. VIA Isaiah Architecture processors implement multiple different data-prefetch mechanisms that analyze data-access patterns and try to load the predicted data from the bus before the reference actually occurs. These prefetch mechanisms run asynchronously from micro-op execution and improve performance significantly for some applications. One mechanism predicts future data use based on past load or store requests that miss in the L1. The prefetch data in this case is loaded into our prefetch cache. Another mechanism is a “streaming prefetcher” that loads prefetched data directly into the L1 cache, just as Intel does.

Sophisticated memory access features. The VIA Isaiah Architecture has many powerful features for improving performance of loads and stores. For example, the “memory disambiguation” algorithm detects loads that hit store data that has not yet stored. This algorithm uses both static address formats as well as history about previous instruction execution. The store-to-load forwarding mechanisms are also very powerful, including, for example, the ability to merge a smaller store into larger load data. The VIA Isaiah Architecture also performs speculative TLB tablewalks and provides very fast handling of unaligned data across a page boundary, and so forth. (Intel calls their version of prefetching and memory disambiguation (next point) “Intel Smart Memory Access”.)

Powerful execution units. The VIA Isaiah Architecture has seven execution ports and can issue up to seven execution micro-ops per clock: two integer, a load, a store address, a store data, a “media”, and a multiply micro-op. The media micro-op can be a floating-point add, divide or square root, or a SIMD integer instruction. This unit also overlaps execution of divide and square root with other subsequent media operations; thus, media micro-ops may continue to issue while a divide or square root is executing.

High-performance media computation. The VIA Isaiah Architecture places significant emphasis on high-performance floating-point execution. It can execute four floating-point adds and four floating-point multiplies every clock. It uses a completely new algorithm for floating-point adds that results in the lowest floating-point add latency of any x86 processor—two clocks for any format (SP, DP, DE, packed or scalar). This contrasts with Intel’s three or four clocks (depends on the format). Similarly, the floating-point multiplier has the lowest latency of any x86 processor—three clocks for SP multiply, and four for DP and DE. This contrasts with Intel’s four and five clocks, respectively.

In addition, the integer data path for SIMD integer (SSEx) instructions is 128-bits wide, and almost all SSEx instructions—including all shuffles— execute in only one clock.

Advanced power and thermal management. In addition to our usual aggressive dynamic management of active power, VIA Isaiah Architecture processors utilize new low-power circuit techniques. The latest x86 instruction-level power controls are included along with a new “C6″ power state where the caches are flushed, internal state is saved, and the core voltage is turned off.

Unique to the VIA Isaiah Architecture are several new VIA Adaptive PowerSaver™ features. They include fine-grained algorithms for adaptively transitioning between performance and voltage states (“P” states) while the processor continues to run (Intel stops the bus and execution during these transitions). Yet another feature provides automatic overclocking if the die temperature is low. Another feature allows the processor to automatically maintain the die temperature at a user-specified temperature. Several other new power and thermal management features are provided.

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