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This study explores the formation of circular thin-film hydraulic jumps caused by the normal impact of a jet on an infinite planar surface. For more than a century, it has been believed that all hydraulic jumps are created due to gravity. However, we show that these thin-film hydraulic jumps result from energy loss due to surface tension and viscous forces alone. We show that, at the jump, surface tension and viscous forces balance the momentum in the liquid film and gravity plays no significant role. Experiments show no dependence on the orientation of the surface and a scaling relation balancing viscous forces and surface tension collapses the experimental data. A theoretical analysis shows that the downstream transport of surface energy is the previously neglected critical ingredient in these flows, and that capillary waves play the role of gravity waves in a traditional jump in demarcating the transition from the supercritical to subcritical flow associated with these jumps.

The interaction of a single bubble with a single vortex ring in water has been studied experimentally. Measurements of both the bubble dynamics and vorticity dynamics have been done to help understand the two-way coupled problem. The circulation strength of the vortex ring (
${\it\Gamma}$
) has been systematically varied, while keeping the bubble diameter (
$D_{b}$
) constant, with the bubble volume to vortex core volume ratio (
$V_{R}$
) also kept fixed at about 0.1. The other important parameter in the problem is a Weber number based on the vortex ring strength
$(\mathit{We}=0.87{\it\rho}({\it\Gamma}/2{\rm\pi}a)^{2}/({\it\sigma}/D_{b});a=\text{vortex core radius},{\it\sigma}=\text{surface tension})$
, which is varied over a large range,
$\mathit{We}=3{-}406$
. The interaction between the bubble and ring for each of the
$\mathit{We}$
cases broadly falls into four stages. Stage I is before capture of the bubble by the ring where the bubble is drawn into the low-pressure vortex core, while in stage II the bubble is stretched in the azimuthal direction within the ring and gradually broken up into a number of smaller bubbles. Following this, in stage III the bubble break-up is complete and the resulting smaller bubbles slowly move around the core, and finally in stage IV the bubbles escape. Apart from the effect of the ring on the bubble, the bubble is also shown to significantly affect the vortex ring, especially at low
$\mathit{We}$
(
$\mathit{We}\sim 3$
). In these low-
$\mathit{We}$
cases, the convection speed drops significantly compared to the base case without a bubble, while the core appears to fragment with a resultant large decrease in enstrophy by about 50 %. In the higher-
$\mathit{We}$
cases (
$\mathit{We}>100$
), there are some differences in convection speed and enstrophy, but the effects are relatively small. The most dramatic effects of the bubble on the ring are found for thicker core rings at low
$\mathit{We}$
(
$\mathit{We}\sim 3$
) with the vortex ring almost stopping after interacting with the bubble, and the core fragmenting into two parts. The present idealized experiments exhibit many phenomena also seen in bubbly turbulent flows such as reduction in enstrophy, suppression of structures, enhancement of energy at small scales and reduction in energy at large scales. These similarities suggest that results from the present experiments can be helpful in better understanding interactions of bubbles with eddies in turbulent flows.

The brain-stem cholinergic neurons, having higher activity during rapid eye movement (REM) sleep, located in several isolated nuclei are known as REM-on neurons. In contrast, the monoaminergic neurons in the brain stem and in the forebrain areas exhibit higher activity during wakefulness, almost completely cease their firing during REM sleep and have been termed as REM-off neurons. The norepinephrin (NE)-ergic neurons located in the locus coeruleus (LC) could be the negative REM sleep-executive neurons and their cessation during REM sleep seems to be obligatory for its occurrence. Our findings that the wakefulness-promoting neurons are inhibitory to REM-on neurons and excitatory to the REM-off neurons led us to suggest that the wakefulness-related neurons do not allow REM sleep to occur and cessation of REM-off neurons is a necessity for the generation of REM sleep. The caudal brain-stem reticular formation (CRF), which induces cortical synchronization, facilitates the activity of REM-on neurons. However, the hypothalamic non-REM sleep-related neurons do not seem to have significant effect on the spontaneous activity of the REM-on neurons, although they may be indirectly modulating REM sleep. Taken together these findings suggest that normally waking neurons do not allow REM sleep to appear; at a certain depth of non-REM sleep the CRF facilitates the onset of REM sleep and re-activation of the wake-active neurons in the brain stem is requisite for its termination.

The electronic structure of CeAg2Ge2 single crystal has been investigated by using resonant valence band photoemission and angle-resolved photoemission spectroscopy at different photon energies. Resonant photoemission has been observed near the 4d threshold of Ce at 121 eV. The constant initial state spectra show two photoemission features having 4f character near the Fermi level that exhibits Fano-like sharp resonance profile. Experimental energy bands have been mapped from the normal-emission photoelectron spectra of CeAg2Ge2 (001) surface along the Γ–Z direction. Four photoemission features are observed to show the dispersion related to the Ce 4f states and the hybridized Ag 4d with Ge 4p states. The experimental spectra have been interpreted with the help of calculations based on full potential linear augmented plane wave method using density functional theory.

Discontinuous precipitation involves formation of a two phase aggregate from a supersaturated solid solution behind a migrating boundary. It is established that the solute transport occurs primarily through the migrating boundary, called the reaction front. This report presents a systematic study of discontinuous precipitation in a Zn-Ag alloy and measurement of grain boundary chemical diffusivity of Ag in Zn-Ag using a suitable analytical model for the first time. The necessary kinetic parameters were determined by optical and scanning electron microscopes. The activation energy for boundary chemical diffusion of Ag in Zn-Ag has been estimated to be 65.8 kJ/mol.

Aserinsky & Kleitman (1953) identified within sleep a physiological state that expresses several signs apparently similar to those that occur during wakefulness. This state was termed rapid eye movement (REM) sleep. REM sleep may play a significant role in maintaining normal physiological functions, as its loss has serious detrimental psychopathological effects. The mechanism of REM sleep regulation is still unknown. The pontine cholinergic and noradrenergic transmissions in the brain undergo reciprocal variations in activity associated with the transformation from non-REM sleep to a REM sleep state and vice versa. The cessation of noradrenergic neuronal firing in the locus coeruleus (LC) plays a crucial role in the regulation of REM sleep. Disinhibition of the LC neurons may result in increased levels of noradrenaline (NA) in the brain, and this increased brain NA is likely to be responsible for the pathophysiological effects associated with REM sleep deprivation. Based on recent findings, we discuss the modulation as well as the role of LC neurons and NA in the modulation of REM sleep and the pathophysiological conditions associated with its deprivation. We propose that LC NA neurons are negative executive neurons for the regulation of REM sleep.

Introduction

One of the important characteristics of living beings is to alternate between active and rest phases, but the underlying mechanism/s and functions are not yet known.

The fraction of the industrial semiconductor budget that manufacturing-time testing consumes continues to rise steadily. It has been known for quite some time that tackling the problems associated with testing semiconductor circuits at earlier design levels significantly reduces testing costs. Thus, it is important for hardware designers to be exposed to the concepts in testing which can help them design a better product. In this era of system-on-a-chip, it is not only important to address the testing issues at the gate level, as was traditionally done, but also at all other levels of the integrated circuit design hierarchy.

This textbook is intended for senior undergraduate or beginning graduate levels. Because of its comprehensive treatment of digital circuit testing techniques, it can also be gainfully used by practicing engineers in the semiconductor industry. Its comprehensive nature stems from its coverage of the transistor, gate, register-transfer, behavior and system levels of the design hierarchy. In addition to test generation techniques, it also covers design for testability, synthesis for testability and built-in self-test techniques in detail. The emphasis of the text is on providing a thorough understanding of the basic concepts; access to more advanced concepts is provided through a list of additional reading material at the end of the chapter.

In this chapter, first we describe the full-scan methodology, including example designs of scan flip-flops and latches, organization of scan chains, generation of test vectors for full-scan circuits, application of vectors via scan, and the costs and benefits of scan. This is followed by a description of partial scan techniques that can provide many of the benefits of full scan at lower costs. Techniques to design scan chains and generate and apply vectors so as to reduce the high cost of test application are then presented.

We then present the boundary scan architecture for testing and diagnosis of inter-chip interconnects on printed circuit boards and multi-chip modules.

Finally, we present design for testability techniques that facilitate delay fault testing as well as techniques to generate and apply tests via scan that minimize switching activity in the circuit during test application.

Introduction

The difficulty of testing a digital circuit can be quantified in terms of cost of test development, cost of test application, and costs associated with test escapes. Test development spans circuit modeling, test generation (automatic and/or manual), and fault simulation. Upon completion, test development provides test vectors to be applied to the circuit and the corresponding fault coverage. Test application includes the process of accessing appropriate circuit lines, pads, or pins, followed by application of test vectors and comparison of the captured responses with those expected.

Delay fault testing exposes temporal defects in an integrated circuit. Even when a circuit performs its logic operations correctly, it may be too slow to propagate signals through certain paths or gates. In such cases, incorrect logic values may get latched at the circuit outputs.

In this chapter, we first describe the basic concepts in delay fault testing, such as clocking schemes, testability classification, and delay fault coverage.

Next, we present test generation and fault simulation methods for path, gate and segment delay faults in combinational as well as sequential circuits. We also cover test compaction and fault diagnosis methods for combinational circuits. Under sequential test generation, we look at non-scan designs. Scan designs are addressed in Chapter 11.

We then discuss some pitfalls that have been pointed out in delay fault testing, and some initial attempts to correct these problems.

Delay fault (DF) testing determines the operational correctness of a circuit at its specified speed. Even if the steady-state behavior of a circuit is correct, it may not be reached in the allotted time. DF testing exposes such circuit malfunctions. In Chapter 2 (Section 2.2.6), we presented various DF models, testing for which can ensure that a circuit is free of DFs. These fault models include the gate delay fault (GDF) model and the path delay fault (PDF) model.

In this chapter, we describe functional testing methods which start with a functional description of the circuit and make sure that the circuit's operation corresponds to its description. Since functional testing is not always based on a detailed structural description of the circuit, the test generation complexity can, in general, be substantially reduced. Functional tests can also detect design errors, which testing methods based on the structural fault model cannot.

We first describe methods for deriving universal test sets from the functional description. These test sets are applicable to any implementation of the function from a restricted class of networks.

We then discuss pseudoexhaustive testing of circuits where cones or segments of logic are tested by the set of all possible input vectors for that cone or segment.

Finally, we see how iterative logic arrays can be tested, and how simple design for testability schemes can make such testing easy. We introduce a graph labeling method for this purpose and apply it to adders, multipliers and dividers.

Universal test sets

Suppose the description of a function is given in some form, say a truth table. Consider the case where a fault in the circuit can change the truth table in an arbitrary way. How do we detect all such faults? One obvious way is to apply all 2n vectors to it, where n is the number of inputs.

IDDQ testing refers to detection of defects in integrated circuits through the use of supply current monitoring. This is specially suited to CMOS circuits in which the quiescent supply current is normally very low. Therefore, an abnormally high current indicates the presence of a defect. In order to achieve high quality, it is now well-established that integrated circuits need to be tested with logic, delay as well as IDDQ tests.

In this chapter, we first give an introduction to the types of fault models that IDDQ testing is applicable to, and the advantages and disadvantages of this type of testing. We then present test generation and fault simulation methods for detecting such faults in combinational as well as sequential circuits. We also show how the IDDQ test sets can be compacted.

We look at techniques for IDDQ measurement based fault diagnosis. We derive diagnostic test sets, give methods for diagnosis and evaluate the diagnostic capability of given test sets.

In order to speed up and facilitate IDDQ testing, various built-in current sensor designs have been presented. We look at one of these designs.

We next present some interesting variants of current sensing techniques that hold promise.

Finally, we discuss the economics of IDDQ testing.

Introduction

In the quiescent state, CMOS circuits just draw leakage current. Therefore, if a fault results in a drastic increase in the current drawn by the circuit, it can be detected through the monitoring of the quiescent power supply current, IDDQ.

In this chapter, we discuss automatic test pattern generation (ATPG) for combinational circuits. We begin by introducing preliminary concepts including circuit elements, ways of representing behaviors of their fault-free as well as faulty versions, and various value systems.

Next, we give an informal description of test generation algorithms to introduce some of the test generation terminology. We then describe direct as well as indirect implication techniques.

We discuss a generic structural test generation algorithm and some of its key components. We then describe specific structural test generation paradigms, followed by their comparison and techniques for improvement.

We proceed to some non-structural test generation algorithms. We describe test generation systems that use test generation algorithms in conjunction with other tools to efficiently generate tests.

While most practical circuits are sequential, they often incorporate the full-scan design for testability (DFT) feature (see Chapter 11). The use of full-scan enables tests to be generated using a combinational test generator. The input to the test generator is only the combinational part of the circuit under test (CUT), obtained by removing all the flip-flops and considering all the inputs and outputs of the combinational circuit as primary inputs and outputs, respectively. If the generated tests are applied using the full-scan DFT features and the test application scheme described in Chapter 11, the fault coverage reported by the combinational test generator is achieved.

Synthesis for testability refers to an area in which testability considerations are incorporated during the synthesis process itself. There are two major sub-areas: synthesis for full testability and synthesis for easy testability. In the former, one tries to remove all redundancies from the circuit so that it becomes completely testable. In the latter, one tries to synthesize the circuit in order to achieve one or more of the following: less test generation time, less test application time, and high fault coverage. Of course, one would ideally like to achieve both full and easy testability. Synthesis for easy testability also has the potential for realizing circuits with less hardware and delay overhead than design for testability techniques. However, in practice, this potential is not always easy to achieve.

In this chapter, we look at synthesis for testability techniques applied at the logic level. We discuss synthesis for easy testability as well as synthesis for full testability.

We consider both the stuck-at and delay fault models, and consider both combinational and sequential circuits. Under the stuck-at fault (SAF) model, we look at single as well as multiple faults. Under the delay fault model, we consider both gate delay faults (GDFs) and path delay faults (PDFs).

In order to alleviate the test generation complexity, one needs to model the actual defects that may occur in a chip with fault models at higher levels of abstraction. This process of fault modeling considerably reduces the burden of testing because it obviates the need for deriving tests for each possible defect. This is made possible by the fact that many physical defects map to a single fault at the higher level. This, in general, also makes the fault model more independent of the technology.

We begin this chapter with a description of the various levels of abstraction at which fault modeling is traditionally done. These levels are: behavioral, functional, structural, switch-level and geometric.

We present various fault models at the different levels of the design hierarchy and discuss their advantages and disadvantages. We illustrate the working of these fault models with many examples.

There is currently a lot of interest in verifying not only that the logical behavior of the circuit is correct, but that its temporal behavior is also correct. Problems in the temporal behavior of a circuit are modeled through delay faults. We discuss the main delay fault models.

We discuss a popular fault modeling method called inductive fault analysis next. It uses statistical data from the fabrication process to generate physical defects and extract circuit-level faults from them. It then classifies the circuit-level faults based on how likely they are to occur.

In this chapter, we discuss how CMOS circuits can be tested under various fault models, such as stuck-at, stuck-open and stuck-on. We consider both dynamic and static CMOS circuits. We present test generation techniques based on the gate-level model of CMOS circuits, as well as the switch-level implementation.

Under dynamic CMOS circuits, we look at two popular techniques: domino CMOS and differential cascode voltage switch (DCVS) logic. We consider both single and multiple fault testability of domino CMOS circuits. For DCVS circuits, we also present an error-checker based scheme which facilitates testing.

Under static CMOS circuits, we consider both robust and non-robust test generation. A robust test is one which is not invalidated by arbitrary delays and timing skews. We first show how test invalidation can occur. We then discuss fault collapsing techniques and test generation techniques at the gate level and switch level.

Finally, we show how robustly testable static CMOS designs can be obtained.

Testing of dynamic CMOS circuits

Dynamic CMOS circuits form an important class of CMOS circuits. A dynamic CMOS circuit is distinguished from a static CMOS circuit by the fact that each dynamic CMOS gate is fed by a clock which determines whether it operates in the precharge phase or the evaluation phase. There are two basic types of dynamic CMOS circuits: domino CMOS (Krambeck et al., 1982) and DCVS logic (Heller et al., 1984).

In this chapter, we discuss logic and fault simulation methods for combinational circuits.

We begin by defining what constitutes a test for a fault and defining the main objectives of fault simulation algorithms. We then define some basic concepts and describe the notation used to represent the behavior of fault-free as well as faulty versions of a circuit.

We then describe logic simulation algorithms, including event-driven and parallel algorithms.

Next, we present a simple fault simulation algorithm and some basic procedures used by most fault simulation algorithms to decrease their average run-time complexity. This is followed by a description of the five fault simulation paradigms: parallel fault, parallel-pattern single-fault, deductive, concurrent, and critical path tracing.

Finally, we present some low complexity approaches for obtaining an approximate value of fault coverage for a given set of vectors.

Introduction

The objectives of fault simulation include (i) determination of the quality of given tests, and (ii) generation of information required for fault diagnosis (i.e., location of faults in a chip). In this chapter, we describe fault simulation techniques for combinational circuits. While most practical circuits are sequential, they often incorporate the fullscan design-for-testability (DFT) feature (see Chapter 11). The use of full-scan enables test development and evaluation using only the combinational parts of a sequential circuit, obtained by removing all flip-flops and considering all inputs and outputs of each combinational logic block as primary inputs and outputs, respectively.