This would indeed yield a cpe of 10 our measurement

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Unformatted text preview: incl %edx.0 cmpl %esi, %edx.1 jl-taken cc.1 load cmpl jl
cc.1 t.1 %ecx.1 %edx.1 cc.1 %ecx.0 t.1 imull %ecx.1 Figure 5.13: Operations for First Iteration of Inner Loop of combine4 for integer multiplication. Memory reads are explicitly converted to loads. Register names are tagged with instance numbers. checks whether the newly computed values for the condition codes (cc.1) indicate this was the correct choice. If not, then it signals the ICU to begin fetching instructions at the instruction following the jl. To simplify the notation, we omit any information about the possible jump destinations. In practice, the processor must keep track of the destination for the unpredicted direction, so that it can begin fetching from there in the event the prediction is incorrect. As this example translation shows, our operations mimic the structure of the assembly-language instructions in many ways, except that they refer to their source and destination operations by labels that identify different instances of the registers. In the actual hardware, register renaming dynamically assigns...
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