The present invention relates generally to recovering timing clock
of signals in communication networks, and more particularly, to methods and apparatuses
for recovering timing clock of variable bit rate signals in communication networks.

Background of the Art

High reliability networks, which handle diverse types of traffic from
diverse sources, monitor and manage in the time domain the quality of digital transmission.
Failure to detect and correct transmission impairments results in unacceptable link
error rates and unexpected network failures. Hence, networks must extract from a
stream of transmitted data a clock signal to perform the necessary measurements
and correct for inevitable transmission degradation.

An extracted clock signal is necessary to perform time domain measurements,
such as eye-pattern opening and timing jitter. The extracted clock signal is also
essential for distinguishing the individual data bits in the transmitted data stream
prior to further processing, such as digital demultiplexing, protocol conversion,
packet switching, and measurement of bit error rate (BER).

Clock recovery has traditionally been regarded as a rate specific
process, and as a result, conventional point-to-point transmission systems typically
use only one or two line rates. Emerging network technologies, for example photonic
switching and Wavelength Division Multiplexing (WDM), however, have enabled complex
optical network topologies, where links transport diverse types of traffic, such
as Internet Protocol (IP), Asynchronous Transfer Mode (ATM), Fiberchannel, Synchronous
Optical Network (SONET), and Gigabit Ethernet. Hence, these emerging networks must
use clock recovery circuits that are adaptive to the variable rate of the transmitted
data.

A phase locked loop is one type of tracking filter often used in a
clock recovery circuit for extracting a clock signal from an input data signal.
Figure 1 illustrates the primary components of a prior art clock recovery circuit
100, which includes a phase locked loop. The phase locked loop includes a phase
comparator 120, a low pass filter 130, a stable voltage controlled oscillator 150
(VCO), and feedback loop 165.

As shown, a transition detector 110, for example a dual edge triggered
one-shot, receives a non-return to zero (NRZ) input signal 155, and generates a
single pulse of duration τED for each transition in input signal
155. The phase locked loop, whose passband frequency fc
is centered on the bit rate frequency fbit of input signal 155,
extracts the clock signal from the stream of pulses generated by transition detector
110. Phase comparator 120 compares the phase of the signal at the output of the
phase locked loop with the stream of pulses, and generates a phase difference signal.
Low pass filter 130 filters and amplifies the phase difference signal to generate
a correction signal for adjusting the phase of VCO 150.

For a variable bit rate NRZ input signal, two rate dependent parameters
must be properly adjusted in clock recovery circuit 100 for recovering an associated
clock signal 160. One rate dependent parameter is the width τED of
the pulses generated by transition detector 110. While input signal 155 generally
does not contain energy at its bit rate frequency fbit, the series
of pulses generated by transition detector 110 does contain energy at the bit rate
frequency fbit. The amount of energy at the bit rate frequency
fbit is maximum when the width of the generated pulses τED
equals 1/(2fbit).

The center frequency of VCO 150 is the second rate dependent parameter,
which must be properly set to recover clock signal 160 from input signal 155. An
active or passive stabilization signal 170 initially sets the center frequency of
VCO 150 to a value fc in the absence of a signal from phase comparator
120. Feedback loop 165 causes the center frequency of VCO 150 to shift from the
initial frequency fc to the bit rate frequency fbit
of input signal 155. VCO 150 will lock to the bit rate frequency fbit
when its center frequency is close to the bit rate frequency fbit.
When the center frequency of VCO 150 exactly equals the bit rate frequency
fbit, VCO 150 will phase lock to transitions in input signal 155.

In addition to a phase locked loop, clock recovery circuits may also
include a frequency locked loop for tuning the center frequency fc
of VCO 150 to the bit rate frequency fbit. Figure 2 illustrates
the basic components of a clock recovery circuit 200, which includes a transition
detector 210, phase comparator 220, frequency comparator 260, low pass filter 230,
and VCO 250. Frequency comparator 220 compares the stream of pulses generated by
transition detector 210 with the output of VCO 250, and generates a locking signal
that reflects the difference between the center frequency of VCO 250 and the bit
rate frequency fbit. An adder 270 combines the locking signal
with the output of phase comparator 220. Feedback loop 265 causes the center frequency
of VCO 250 to shift from its initial value offc to the bit rate
frequency fbit causing the locking signal to transition to zero.
At this point, phase comparator 120 continues to control the center frequency and
phase of VCO 250.

The stream of pulses generated by transition detector 210 also contains
at multiples of the bit rate frequency fbit energy, whose relative
amplitude increases as τED decreases. As a result, regular patterns
in block coded input signals may produce both harmonics and sub of the bit rate
frequency fbit. Accordingly, existing clock recovery circuits
track the harmonics or sub-harmonics of the input data signal when the center frequency
of VCO 250 is inappropriately set to a multiple of the bit rate frequency
fbit. Consequently, false locking may occur when a clock recovery
circuit searches for the bit rate frequency fbit by sweeping the
center frequency of VCO 250 across the harmonics. In addition, recurrent patterns
in common block coded input data signals also increase the susceptibility of a clock
recovery circuit to locking.

One specific prior art arrangement using a phase locked loop to recover
timing signals from an input signal which may be at different transmission rates
is disclosed in US 3,908,115, wherein a digital filter is adaptively tuned to the
instantaneous bitrate of a received noisy digital signal.

Although various techniques are known for sweeping the center frequency
of VCO 250 to determine the bit rate frequency fbit these techniques
are too slow and/or lack sufficient accuracy for variable bit rate applications.
One example of variable bit rate applications is Wavelength Division Multiplexing
(WDM), where an input data signal can have a wide range of bit rates. In addition,
the existing techniques cause a clock recovery circuit to readily lock to harmonics
and sub-harmonics of the bit rate frequency fbit.

Thus, it is desirable to have methods and apparatuses that do not
have the above-mentioned and other disadvantages of the prior art clock recovery
circuits for recovering a clock signal from a variable bit rate input data signal.

DESCRIPTION OF THE INVENTION

Methods and apparatuses consistent with the present invention recover
a clock signal of a variable bit rate data signal by estimating the minimum time
interval between transitions in the data signal, and based on the estimated minimum
time interval, determining a center frequency of a narrow band filter that extracts
the clock signal from the data signal. A clock recovery circuit consistent with
the present invention extracts the clock signal from the variable bit rate data
signal by estimating a minimum time interval between transitions in the data signal.
The clock recovery circuit generates a plurality of pulses that correspond to transitions
in the data signal, and adjusts the duration of each of the pulses based on the
estimated minimum time interval. The clock recovery circuit inputs into a narrow
band filter the adjusted pulses, determines a center frequency of the narrow band
filter based on the estimated minimum time interval, and extracts in the narrow-band
filter the clock signal from the adjusted pulses. Unlike US 3,908,115, in the present
invention a feedback architecture including a phase lock loop is not employed to
provide input pulses to a filter. Instead, the present invention uses estimating
a minimum time interval between transitions in the input signal, generating a first
plurality of pulses corresponding respectively to transitions in the input signal,
adjusting the duration of each of the first plurality of pulses based on the estimated
minimum time interval and inputting into a narrow-band filter the adjusted first
plurality of pulses, determining a center frequency of the narrow-band filter based
on the generated minimum time interval, and extracting in the narrow-band filter
the clock signal from the adjusted first plurality of pulses.

Methods and apparatuses consistent with the invention estimate the
bit rate of a data signal independently of a primary phase locked loop and frequency
locked loop. Such methods and apparatuses directly estimate the minimum time interval
between transitions in the data signal, and thus, eliminate the problems of harmonic
and sub-harmonic locking that the prior art clock recovery circuits exhibit in variable
bit rate applications.

The description of the invention and the following description for
carrying out the best mode of the invention should not restrict the scope of the
claimed invention. Both provide examples and explanations to enable others to practice
the invention. The accompanying drawings, which form part of the description for
carrying out the best mode of the invention, show several embodiments of the invention,
and together with the description, explain the principles of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

In the Figures:

Figure 1 is a block diagram of a prior art clock recovery circuit, which includes
a phase locked loop;

Figure 2 is a block diagram of a prior art clock recovery circuit, which includes
a frequency locked loop and a phase locked loop;

Figure 3 is a block diagram of a variable bit rate clock recovery circuit, in
accordance with an embodiment of the invention;

Figure 4 is a block diagram of a variable bit rate clock memory circuit, which
includes a calibration means, in accordance with an embodiment of the invention;

Fig. 5 is a circuit diagram of a forward rate detector, which performs discrete
interval pulse-width auto-correlation, in accordance with an embodiment of the invention;

Figures 6a, 6b, 6c, 6d, and 6e illustrate timing diagrams of an input signal
as it propagates through a set of delay segments, in accordance with an embodiment
of the invention;

Figure 7 is a circuit diagram of a delay segment, in accordance with an embodiment
of the invention;

Figure 8 is a block diagram of a forward rate detector, which performs continuous
pulse-width auto-correlation, in accordance with an embodiment of the invention;

Figures 9a, 9b, 9c, and 9d illustrate the timing diagrams of an input signal,
output of a time interval generator, and output of an edge transition comparator,
in accordance with an embodiment of the invention;

Figure 10 is a circuit diagram of a minimum interval correlator, in accordance
with an embodiment of the invention;

Figure 11 illustrates an emitter coupled logic (ECL) implementation of a unipolar
minimum interval correlator, in accordance with an embodiment of the invention;

Figures 12a, 12b, 12c, and 12d illustrate an analog implementation of a feedback
circuit and associated signals in a forward rate detector, in accordance with an
embodiment of the invention;

Figures 13a, 13b, 13c, 13d, and 13e illustrate a digital implementation of a
feedback circuit and associated signals in a forward rate detector, in accordance
with an embodiment of the invention; and

Figures 14a and 14b are block diagrams of implementations of a rate selector,
in accordance with two embodiments of the invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Reference will now be made in detail to the preferred embodiments
of the invention, examples of which are illustrated in the accompanying drawings.
Wherever possible, the same reference numbers will be used throughout the drawings
to refer to the same or like parts.

Rate estimate signal RE may be represented as follows:
RE = fbit · Kfrd(fbit),
where fbit is the bit rate frequency of input signal 155 and
Kfrd is either a constant or a slowly varying function of
fbit. The pulse width τED from the transition detector
320 may be represented as follows:
1 / (τED)= KED(RS1),
where KED is a monotonic function of control signal
RS1. The center frequency fc of the narrow band
filter 330 may be represented as follows:
fc = Kfc(RS2),
where Kfc is a monotonic function of control signal RS2.
In one embodiment, rate selector 310 may perform a one-to-one mapping of rate estimate
signal RE to predetermined values of τED and fc
as follows:
RS1 = G1 (RE),
where G1 is a monotonic function of rate estimate signal
RE and satisfies the relation:
Kfc-1fbit =
G1 (fbit · Kfrd (fbit)),
and
RS2 = G2 (RE),
where G2 is a monotonic function of rate estimate signal
RE and satisfies the following relation:
KED-1 (2fbit) =
G2(fbit · Kfrd(fbit))

In one embodiment, KED and Kfc
may have an approximately linear dependence on rate estimate signal RE, whereas
Kfrd may be nearly constant. In this embodiment, the solutions
to equations (5) and (7) may be represented as follows:
G1 (RE) = g11 +
g12RE + &epsi;1 (RE),G2 (RE) = g21 +
g22RE + &epsi;2 (RE),
where g11, g12, g21, and
g22 are parameters, which may depend on temperature or the interval
of rate estimate signal RE. Similarly, the functions &epsi;1 (RE)
and &epsi;2 (RE) may be slowly varying functions of rate estimate
signal RE and temperature. The parameters g11,
g12, g21, g22, &epsi;1,
and &epsi;2 may be selected to satisfy, for example, equations (5) and
(7). Alternatively, &epsi;1 and &epsi;2 may be set to zero.

The time interval between transitions in input signal 135 may be represented
as Δt = n τbit where n is an integer greater
than or equal to 1 and τbit is the bit period of input signal 155.
In other words, τbit is equal to the multiplicative inverse of bit
rate frequency fbit of input signal 155. Forward rate detector
301 may estimate the bit rate in input signal 155 from a plurality of consecutive
transitions in input signal 155, which would represent a set {n} of values
for run length n. From this set of transitions, forward rate detector 301
may determine the minimum detected interval between transitions τmin,
which may be represented as follows:
Furthermore, τmin may represent an unbiased estimate of the bit
rate τbit as follows:

Digital signals such as input signal 155 may have random bit patterns
or may have prescribed bit patterns constrained by block coding. For a random sequence
of bits, the discrete probability density for run length n is P(n)
= 2-n. The run length distribution for signals, which are encoded using
block coding, may also be approximately 2-n for small values of
n, for example n < 5. This indicates that single bit intervals with n
= 1 occur quite often with these types of digital signals, for example about 50%
of the time. Based on the high incidence of single bit intervals in input signal
155, forward rate detector 301 may rapidly and reliably estimate fbit
from measurements of τmin. In addition, the preamble of a packet
represented by input signal 155 may include a "1010" pattern, allowing nearly instantaneous
detection of the rate of input signal 155.

Delay segments S1-SN connect to each
other in serial fashion, where each delay segment S1-SN
successively delays by time τi the falling edge initiated by input
signal 155, where 1 ≤ i ≤ N. Depending upon the embodiment, the particular
values of τi may differ between delay segments S1-SN.
As shown in Figure 5, delay segments S1-S3 include resettable
falling edge triggered delay elements 5101-5103 and OR/NOR
gates 5201-5203, respectively. Outputs of each edge triggered
delay elements 5101-5103 connect to a respective first input
5241-5243 of OR/NOR gates 5201-5203.
The last delay segment SN, however, includes delay element 514N
and an inverter 580 instead of an OR/NOR gate.

As the input transition propagates through delay segments S1-SN,
consecutive outputs 5281-5283 may transition from a high state
to a low state, while the corresponding complementary outputs 5261-5263
and 584 may transition from a low state to a high state. Each falling edge transition
in input signal 155 initiates a series of pulses, which are then compared to the
arrival of a subsequent rising transition in input signal 155. D-type flip-flops
5301-530N perform the comparison by latching the state
of delayed outputs 5261-526N and 584 upon the subsequent
rising transition in input signal 155.

High speed operation is achieved by partitioning the net time delays
into small intervals τ1-τN, and simultaneously
resetting each delay element 5102-510N via common control
line 574 of buffer 570. Buffer 570 delays the simultaneous reset signal, such that
the minimum hold-time requirement of D-type flip-flops 5301-530N
is satisfied.

Operation of forward rate detector 301 may be initiated on the rising
edge transitions in input signal 155 as well as the falling edge transitions in
input signal 155. Forward rate detector 301 may, for example, include a duplicate
circuit, which is driven by an inverted replica of input signal 155, for sensing
the length of each pulse in input signal 155 following a rising transition in input
signal 155.

Figures 6a-e illustrate timing diagrams of input signal 155 as it
propagates through delay segments S1-SN,
in accordance with an embodiment of the invention. Figures 6a-c show a falling edge
transition in input signal 155 as it propagates through delay segments S1-SN.
At the end of a pulse in input signal 155, the delayed edge may pass through a portion
or all of delay segments S1-SN.
Because a pulse with the shortest duration in input signal 155 would pass through
the fewest number of delay segments S1-SN,
output 528k of the kth delay segment
Sk is at a high state when the sum of delay times τi
satisfies the constraint
where τbit equals the multiplicative inverse of the bit rate frequency
fbit of input signal 155.

As shown in Figures 6b-e, outputs 5281 and 5282
of delay segments S1 and S2, respectively, are
activated within the nτbit period of input signal 155, whereas outputs
5283 and 584 of delay segments S3 and SN
are not activated within that time period. The waveforms indicated by the dashed
lines in Figures 6d-e show the state of outputs 5283 and 584, respectively,
for an input pulse of longer duration. After a small number of transitions input
signal 155, depending on the run length distribution P(n), a pulse
with n = 1 appears in the input signal 155, after which time the state of outputs
5561-556N represents an upper and lower bound on τbit.
The state of outputs 5561-556N tracks increasing and
decreasing values of τbit when the pulses from counter 540, for example,
occasionally reset R-S latches 5501-550N. Priority
encoder 590 derives at output 598 a binary representation of τbit
from the state of outputs 5561-556N. This binary representation
of τbit is rate estimate signal RE, which is uniquely determined
by τbit and the particular values of τ1-τN.
The resolution of the estimate of τbit may be improved by performing
multiple scans with different combinations of values for τ1-τN.

Table 1 lists several common line rates in input signal 155 and the
segmental delays τi, which may be used to distinguish between the
line rates. The first two columns list some common line rates fbit
and the corresponding bit interval τbit for input signal 155, respectively.
The third column lists the net delays for distinguishing between consecutive rates,
which is the average of τbit for two consecutive rates. Since the
net delay through k delay segments may be represented as
the segmental delays τi represent the differences between the net
delays listed in the third column. The segmental delays, which are listed in the
fourth column and may be readily achieved, demonstrate the feasibility of discrete
rate detector 301 for operating over a wide range of line rates.

Figure 7 is a circuit diagram of delay segment S2
(shown in Figure 5), in accordance with an embodiment of the invention. Although
Figure 7 shows a circuit diagram of delay segment S2, generalization
to delay segments S1 and S3-SN
is readily apparent. High speed performance may be optimized by merging the threshold
function found in a traditional implementation of delay circuit 5102
with OR/NOR gate 5202 using a gated differential amplifier. Input 5122
of delay segment S2 drives the base of transistor
Q702, which serves as a voltage follower. The emitter of
Q702 and a programmable current source I708
connect to capacitor C704 at output 5142 through resistor
R706. Current from the emitter of Q702 rapidly
charges C704 to a preset value while the current from
I708 discharges C704 at a controlled rate. The
voltage at output 5142 is sensed by a gated differential amplifier, which
includes Q720 and Q722. The bases of
Q720 and Q722 connect to output 5142
and to a reference voltage V740, respectively. The emitters of
transistors Q720 and Q722 connect via node 730
to a fixed current source I730.

The base of a gating transistor Q724 connects to
common control line 574 via second input 5222. The collector and emitter
of Q724 connect to output 5262 and node 730, respectively.
The amplifier has inverting and non-inverting outputs at outputs 5262
and 5282, respectively. Output 5282, which connects to the
collector of Q722, is obtained from the voltage drop across
R728. Output 5262, which connects to the collectors
of Q720 and Q724, is obtained from the voltage
drop across R726. The value of reference V740
may be altered by positive feedback via control node 742, which connects to output
5262 to provide threshold level hysteresis. A voltage greater than that
set by reference V740 at either output 5142 or common
control line 574 forces output 5262 to a low state and output 5282
to a high state. In the last delay segment SN, the gating
transistor corresponding to Q724 may be omitted.

In the initial quiescent state, input 5122 and common control
line 574 may be at a high state, and output 5262 may be at a low state.
In this state, the high signal on input 5122 controls Q702
to preset the voltage across capacitor C704. A high signal at
common control line 574 activates Q724 and forces output 5282
to drive the next delay segment S3 to a high state even
before the voltage on C704 reaches the preset value. When input
signal 155 transitions from a high state to a low state, common control line 574
goes low and turns Q724 off. The initial state is held by the
preset voltage across C704, which controls Q720.
Depending on the time constant of the preceding delay segment S1
and the duration of the low state, the voltage at input 5122 may transition
to a low state at some time after input signal 155 transitions from a high state
to a low state. This turns Q702 off and allows C704
to be discharged by current from I708. If the duration of the
low state is still sufficient, the voltage at output 5142 drops below
the reference voltage set by V740 and causes output 5262
to transition to a high state and the output 5282 to transition to a
low state. The low state at output 5282 activates the delay element 5103
in subsequent delay segment S3.

The response time following detection of a threshold may be improved
by a positive feedback from output 5262 to slightly vary V740.
The time delay τ2 associated with delay segment S2 is
governed by the charge conservation at output 5142. The value of time
delay τ2 may be determined by the difference between the preset voltage
across C704, VPRESET, the value Vth740
of reference voltage V740 when control 742 is at a low state,
differential amplifier offset voltage VthOS
at the switching threshold, the value of capacitor C704, stray
capacitance CS associated with output 5142,
current I708, base current Ib of Q720,
and the charge Q2(I708) stored in the emitter
of Q702. This relationship may be represented as follows:
(I708 + Ib) τ2
= (VPRESET - Vth740 -
VthOS)(C704 +
CS) - Qe(I708)
The resolution of the discrete rate detector depends on the selection of time delays
τ1-τN, which may be programmed, for example,
through the value of current I708 for each corresponding delay
segment S1-SN.

Time interval generator 810 receives at inputs 812 and 816 input signal
155 and output 836 of feedback circuit 830, respectively. In response to a transition
in input signal 155, time interval generator 810 generates at output 814 a corresponding
transition delayed by time τ, which is controlled by rate estimate signal
RE. Alternatively, in response to a transition in input signal 155, time
interval generator 810 may generate at output 814 a corresponding set of transitions
delayed by a set of times τ, which may have different values and are controlled
by rate estimate signal RE.

The value of τ is related to rate estimate signal RE through
a known relationship τ = τ(RE). Time interval generator 810 may,
for example, be implemented such that the product of rate estimate signal
RE and τ(RE) is nearly constant to a first order.

Edge transition comparator 820 receives at inputs 822 and 824 input
signal 155 and output 814 of interval generator 810, respectively. Output 826 of
edge transition comparator 820 generates a signal, which is monotonically related
to the difference between τ and τbit. Edge transition comparator
820 generates at output 826 a positive pulse when a subsequent transition in input
signal 155 occurs before τ time has elapsed. Output 826 is received by input
832 of feedback circuit 830, which outputs rate estimate signal RE at output
836 to adjust τ, such that a prescribed rate of pulses are generated at output
826. The time constants within the feedback circuit 830 may be controlled via input
834 by the rate of transitions in input signal 155. The prescribed rate of pulses
from output 826 may have a constant duty cycle. Alternatively, the prescribed rate
may depend on the rate of transitions in input signal 155.

In accordance with another embodiment of the invention, forward rate
detector 301 may estimate τbit using a pulse width auto-correlation
method. Figures 9a-d illustrate the timing diagrams of input signal 155, output
814 of time interval generator 810, output 826 of edge transition comparator 820,
in accordance with this embodiment. Figure 9e illustrates the distribution of values
at output 826 for different values of τ and an arbitrary fixed value of τbit.

Figure 9a shows input signal 155 with a transition occurring at time
Δt = 0 and a subsequent transition at Δt = τbit.
The transition at Δt = 0 triggers time interval generator 810, whose
output pulse is delayed by τ. Three values of τ are indicated by fast F,
slow S, and aligned A.

Figures 9b and 9c illustrate state of output 814 of time interval
generator 810 for two different embodiments. Figure 9d illustrates state of output
826 of edge transition comparator 820 for the two embodiments.

In the first embodiment, time interval generator 810 includes one
or more resettable edge triggered delay elements, for example delay elements 5101-510N
shown in Figure 5. As shown in Figure 9b, in this embodiment, time interval generator
810 generates at output 814 a pulse, which starts after τ time has elapsed and
is reset by the next transition in input signal 155.

In the second embodiment, time interval generator includes an edge
triggered one-shot, which is described below in detail. As shown in Figure 9c, in
this embodiment, time interval generator 810 generates at output 814 a single pulse
starting at time Δt = 0, which has duration τ.

In both embodiments, if time τ is set shorter than τbit,
as indicated by F, the next transition in input signal 155 occurs at Δt
= τbit after τ time has elapsed, and output 826 is set to a low
state. If time τ is set to a longer duration than τbit, as indicated
by S, a subsequent transition in input signal 155 at Δt = τbit
occurs before τ time has elapsed, and output 826 is set to a high state.

There is perfect alignment between the pulse generated at output 814
of time interval generator 810 and input signal 155 when τ = τbit,
as indicated by A, and a transition in input signal 155 that occurs at τbit
overlaps with τ. Output 826 may be in a high or a low state when there is perfect
alignment. Transitions in input signal 155 that occur long after time τ may
be ignored since they may represent a run of bits with Δt = nτbit
and n ≥ 2.

Figure 9e illustrates the distribution of values assumed by output
826 for different values of τ and a given value of τbit. This
distribution represents the transfer function of minium interval correlator 840,
which includes time interval generator 810 and edge transition detector 820. Based
on statistical interpretation of relative frequency, the graph in Figure 9e also
illustrates the mean value at output 826 that would be observed after many instances
of transitions of input signal 155. The graph in Figure 9e has a steep slope at
τ = τbit, which distinguishes between conditions F and S. The
shape of the transition between F and S may be determined by, for example, the distribution
P(n) of run lengths n.

Edge transition comparator 820 compares the interval between the trailing
edge of input signal 155 and output 814 of time interval generator 810, and via
feedback circuit 830, adjusts τ to the value τbit = 1/fbit.
After the settling time of feedback circuit 830, the adjusted τ represents an
estimate of τbit. Hence, in this embodiment, harmonic locking does
not occur because the estimated τbit is uniquely related to
fbit.

MINIMUM INTERVAL CORRELATOR

Figure 10 shows a circuit diagram of minimum interval correlator 840
(shown in Figure 8), in accordance with an embodiment of the invention. In this
embodiment, the response to falling edge transitions and rising edge transitions
in input signal 155 are effectuated through two separate paths. Minimum interval
correlator 840 is partitioned into a falling edge triggered minimum interval correlator
1090 and a rising edge triggered minimum interval correlator 1092. Minimum interval
correlators 1090 and 1092 each perform the functions of time interval generator
810 and transition comparator 820 shown in Figure 8.

The operations of minimum interval correlators 1090 and 1092 are similar
except that all processing is active on opposite transitions in input signal 155.
The operation of minimum interval correlator 1090 is as follows: Output port 1014
assumes a low impedance state with a preset output level of VPRESET
when input 1012 is at a high state, and assumes a high impedance state when input
1012 is at a low state. For example, VPRESET may be more positive
than reference voltage V1038. A high state in input signal 155
causes buffer 1010 to charge capacitor C1018 to VPRESET.

When the input signal 155 undergoes a transition from a high to a
low state, current flow from output 1014 of buffer 1010 is inhibited, and capacitor
C1018 is freely discharged by programmable current from
I1016. If the duration of the low state in input signal 155 is
sufficiently long, the voltage at node 1003 drops below the level set by
V1038, and output 1036 of comparator 1030 transitions to a low
state. D-type flip-flop 1070 captures via the rising edge transition at the output
1054 of buffer 1050 the state of output 1036 at time Δt =
nτbit, when input signal 155 undergoes a subsequent low to
high transition.

The time required for capacitor C1018 to discharge
from VPRESET to V1048 is τ(I1016).
Output 826, may be at a low state if Δt > τ(I1016),
and may be at a high state if Δt < τ(I1016).
Output 8261 may always be low when τ < τbit. If
τ > τbit, there may be small values of run-length n for which
output 8261 may be at a high state. Output 826, may, however, be at a
low state for large n.

Figure 9e shows the distribution of values of output 8261
averaged over typical values of run-length n. The time constant τ(I1016)
may be represented as follows:
(I1016 + Ib)τ = (VPRESET
- V1038 - VthOS)(C1018+CS)
- QO_1014(I1016),
where VthOS is the offset voltage
at a threshold of comparator 1030, CS is the stray capacitance
associated with node 1003, Ib is the input bias current
of comparator 1030, and QO_1014(I1016) is the
charge removed by output 1014 when buffer 1010 is turned off.

Similar operation occurs in minimum interval correlator 1092 for rising
edge transitions in input signal 155. Outputs 8261 and 8262
indicate whether τ is greater or less than τbit. In accordance
with one embodiment, outputs 8261 and 8262 may be used to
control τ through I1016 and I1026 using
negative feedback. Rate estimate signal RE may be determined from the value
of control signal 816 necessary to achieve τ = τbit.

Minimum interval correlator 1090 of Figure 10 constitutes one embodiment
of a unipolar minimum interval correlator, which is active on the falling edge of
input signal 155. Unipolar minimum interval correlator 1090 may include a programmable
gated delay, which includes buffer 1010, capacitor C1018, current
source I1017, comparator 1013, and D-type flip-flop 1070. D-type
flip-flop 1070 may include two latches (not shown), which are controlled by node
3021 via clock input 1074. In one embodiment, one of the latches in 1070
may be shared with the programmable gated delay to create a falling edge triggered
non-retriggerable one-shot. By performing several latching and comparison operations
in parallel, higher operating speeds may be achieved in this embodiment.

Input 1111 of inverter 1110 and node 1144 of one-shot 1102 receive
input signal 155. The falling edge of input signal 155 triggers one-shot 1102 to
generate an output pulse of duration τ(I1016) at output 1127
of buffer 1124. Duration τ is directly controlled by controlled current source
I1016 or indirectly by input 816 via control input 1017 to
I1016. Output 1127 of buffer 1124 is at a high state in the reset
state, and transitions to a low state during time τ. One-shot 1102 cannot be
retriggered by a subsequent change in the state of input signal 155 until after
both time τ has elapsed and input signal 155 returns to a high state.

A high state at node 1144 sets node 1128 to a low state when output
1126 is low, while a high state at output 1126 overrides input 1144 to set node
1128 to a high state. Output 1126 of buffer 1124 may be at a high state during time
τ, and may inhibit NOR gate 1120 from responding to changes in input signal
155. Open emitter output 1123 of NOR gate 1120 connects via node 1166 to the open
emitter output of comparator 1160, capacitor C1164, and input
1125 of buffer 1124.

Capacitor C1164 connects to non-inverting input
1161 of comparator 1160, the cathode of diode D1175, and programmable
current source I1016. Output 1173 of opamp 1170 drives the anode
of diode D1175. Opamp 1170 may be configured, for example, as
a voltage follower with diode D1176 in the feedback loop between
output 1173 and inverting input 1172.

Diode D1176 may be biased at the same current density
as D1175 by programmable current source I1178.
Node 1179 controls current I1178 and node 1017 controls current
I1017. Both control node 1017 and control node 1179 connect to
input 816. Inverting input 1162 of comparator 1160 connects to voltage source
VREF. Non-inverting input 1174 of opamp 1170 connects to voltage
source VCLAMP. Inverting output 1127 of buffer 1124, which is
controlled by node 1166, forms the output of one-shot 1102, and connects to input
1134 of gate 1130 in edge transition comparator 1104.

In the quiescent state, the input signal 155 and input node 1144 may
be in the high state, nodes 1128 and 1166 may be in the low state, and the voltage
at node 1165 may be held at VCLAMP. When the input node 1144 transitions
to a low state due to a negative transition in input signal 155, output 1123 of
NOR gate 1120 transitions to a high state. The coupling through capacitor
C1164 forces node 1165 to a high state. A positive feedback through
comparator 1160 and C1165 holds node 1166 at a high state until
the voltage at node 1165 decreases to VREF.

When node 1166 transitions to a high state after input signal 155
transitions to a low state, buffer 1124 drives node 1128 to a high state, activating
a first latch, which includes inverter 1146 and NOR gate 1140. Output 1123 of NOR
gate 1120 may be subsequently inhibited when node 1128 transitions to a high state.
The first latch continues to hold node 1128 at a high state, and inhibits output
1123, which may only be reset after node 1166 transitions to a low state at time
τ. The first latch is reset to a low state through NOR gate 1140 when both node
1166 returns to a low state and input signal 155 transitions to a high state, restoring
one-shot 1102 to the quiescent state. The voltage on capacitor C1112
has sufficient time to reach steady state since one-shot 1102 triggers only on the
falling edge transitions.

In accordance with an embodiment of the invention, the parameters
associated with comparator 1160 are as follows: Ib is the
input bias current, VthOS is the
input offset at threshold and ΔQthB
is the input charge required to switch comparator 1160. This expression shows that
I1016 may be nearly proportional to fbit when
τ = τbit.

Non-inverting buffer 1114 receives output 1112 of the inverter 1110,
which matches the turn-on delay of one-shot 1102. NOR gate 1130 compares outputs
1116 and 1127 of buffer 1114 and one-shot 1102, respectively. Open emitter output
1136 of NOR gate 1130 may be a current pulse, which may, for example, be a function
of the time interval between the subsequent rising edge in input signal 155 and
the rising edge of output 1127 of one-shot 1102 after delay time τ.

Node 1138 transitions to a high state when input signal 155 transitions
to a high state while output 1127 of one-shot 1102 is at a low state. NOR gate 1150
and inverter 1156 connect to each other to form a second latch, which is activated
by a high state at node 1138. If node 1138 is raised sufficiently high, then feedback
loop around gate 1150 and inverter 1156 holds node 1138 at a high state until input
signal 155 transitions to a low state and output 1116 of gate 1114, which connects
to NOR gate 1150, transitions to a high state.

The relationship between the current pulse from output 1136 of gate
1130 and τ - τbit may be represented as follows: Charge
QO_1136 in the current pulse from gate 1130 is proportional
to τ - τbit - ξτgate, where ξτgate
is a fixed fraction of the nominal gate response-time. The probability that node
1138 may be set to a high state depends on QO_1136 through a function
Fgate (QO_1136), whose characteristics
are shown in Figure 9e. The average time that node 1138 remains at a high state,
once activated, may approximately be n1 τmin
+ τmin - ξτgate. The signal at node 1138 may be
used to control τ through I1016 by using a negative feedback.

ANALOG FEEDBACK CIRCUIT

Figure 12a illustrates an analog implementation of feedback circuit
830, in accordance with an embodiment of the invention. In this embodiment, feedback
circuit 830 comprises a summation circuit 1210, a low pass filter 1220, a differential
amplifier 1230, and a reference voltage V1250. Low pass filter
1220 includes an output 1224, and differential amplifier 1230 includes an output
1236. Figures 12b-d illustrate a change in bit rate of input signal 155, change
in low-pass filter output 1224, and change in amplifier output 1236.

Inputs 1212 and 1214 of summation 1210 receive nodes 8321
and 8322 pulses from outputs 8261 and 8262 of unipolar
minimum interval correlators 1090 and 1092, respectively, when τbit
< τ. Low pass filter 1220 removes high frequency variations from the combined
signal at output 1216 of summation 1210. Differential amplifier 1230 amplifies the
difference between the filtered signal at output 1224 of filter 1220 and reference
voltage V1250. The amplified difference between V1224
and V1250 appears at output 1236, and may be used to control the
period τ of time interval generator 810. Differential amplifier 1230 may incorporate
phase margin compensation, which may be necessary to maintain overall feedback loop
dynamic stability.

Figure 12b illustrates an increase in bit rate fbit
of input signal 155 from fbit1 tofbit2 >
fbit1 occurring at time t = 0. The change in the bit rate
is detected by minimum interval correlator 840, which generates a change in the
rate of pulses that appear at inputs 1212 and 1214 of summation 1210 and consequently
at output 1216. The level at output 1224 for t < 0 may be maintained by
a constant rate of pulses from minimum interval correlator 840. The horizontal dashed
line in figure 12c illustrates that prior to the change at t = 0, a negative
feedback holds output 1224 at nearly V1250. A change in the rate
of pulses at t > 0 at output 1216 generates a transient change in output
1224. The amplified signal appearing at output 1236 changes until period τ of
time interval generator 810 settles to a new value of 1/fbit2.

Minimum interval correlator 840 may generate an output pulse when
isolated "ones" and "zeroes" occur in input signal 155. Input 1212, which is connected
to falling edge transition comparator output 826, via node 8321, may
be active following high-to-low transitions in input signal 155. The probability
that output 8261 transitions to a high state following an isolated "zero"
may be represented by F(τ - τbit), as shown in Figure
9e.

Let P0(n) and P1(n)
denote the distribution of run lengths n for consecutive "zeroes" and "ones,"
respectively, in input signal 155. The probability that an isolated "zero" occurs
following a high-to-low transition is therefore P0(n =
1). The occurrence rate of isolated "zeroes" may be represented as follows:
rate of isolated 0 = P0(1) / ((n0 + n1)τbit),
where n0 and n1 represent the
average length for a run of "zeroes" and "ones," respectively. The average time
interval that output 8261 remains at a high state prior to a subsequent
high-to-low transition can be represented as follows:
persistence time = (n1 + ζ n0) τbit,
The holding property of the edge transition detector 820 may he represented by
parameter ζ. In an embodiment where minimum interval correlator 1090 includes
D-type flip-flop 1070, ζ may equal 1. Alternatively, in an embodiment where
minimum interval correlator 1090 includes falling edge triggered non-retriggerable
one-shot 1102, ζ may equal 0. If the durations of consecutive runs are independent,
the average value of input 1212 may be represented as follows:
V1212 &vprop; (rate of isolated 0) x
F(τ - τbit) x (persistence time)
An analogous expression to equation 13 applies to input 1214 of rising edge transition
comparator output 8262. The filtered output 1224 may be represented as
follows:
V1224 &vprop; (n0 + ζn1)
P1(1) + (n1 + ζn0)
P0(1) / (n0 + n1) F(τ-τbit).
In accordance with an embodiment, the average value V1224
of low-pass filter output 1224 may be used to control τ using a negative feedback.
The small-signal gain has the desirable feature that it is independent of τbit.

In one embodiment, up/down counter 1370 generates a parallel binary
word, which is monotonically related to the difference between the number of pulses
applied to ClkU input 1372 and ClkD input 1374. In another
embodiment, up/down counter 1370 generates a parallel binary signal representing
a successive approximation for rate estimate signal RE using a succession
of step sizes, which may, for example, vary with the pattern of pulses applied to
ClkU input 1372 and ClkD input 1374.

A pulse generated by unipolar minimum interval correlator 1090, which
is active on falling edge transitions in input signal 155, sets output 1316 to a
high state. Similarly, a pulse generated by unipolar minimum interval correlator
1092, which is active on rising edge transitions in input signal 155, sets output
1326 to a high state.

Counter 1390 counts the number of transitions in input signal 155
modulo 2M, where M equals, for example, 4. Second stage
(Q1) output 1394 clocks D-type flip-flops 1330 and 1340 on every
fourth low-to-high transition in input signal 155, storing the prevailing state
of latches 1310 and 1320, respectively.

TC output 1396 transitions to a high state following each 2M
low-to-high transitions in input signal 155, and transitions to a low state after
the next low-to-high transition in input signal 155. The rising edge of TC output
1396 may be near the center of pulses from Q1 output 1394. A high
state on TC output 1396 enables AND gate outputs 1358 and 1368, and resets latches
1310 and 1320 to a low state.

Output 1358 transitions to a high state when TC output 1396 is at
a high state if both D-type flip-flop non-inverting outputs 1336 and 1346 are at
a high state, advancing the state of up/down counter 1370 forward by one count.
Output 1368 transitions to a high state when TC output 1396 is at a high state if
both D-type flip-flop inverting outputs 1338 and 1348 are at a high state, decreasing
the state of up/down counter 1370 by one count. The state of up/down counter 1370
increases when both unipolar minimum interval correlators 1090 and 1092 detect τ
> τbit, and decreases when neither unipolar minimum interval correlator
1090 and 1092 detect τ > τbit. The state of up/down counter
1370 holds when only one of unipolar minimum interval correlators 1090 and 1092
detects τ > τbit. The binary signal at up/down counter output
1376 may be used to control τ using negative feedback.

Figure 13b illustrates an increase in bit rate fbit
of input signal 155 from fbit1 tofbit2 >
fbit1 at time t = 0. Prior to t = 0, negative feedback
may hold period τ of interval generator 810 close to 1/fbit1.
Minimum interval correlator 840 may detect the change in the bit rate, which results
in a change in the rate of pulses that appear at both latch inputs 1312 and 1324.
The presence of pulses at both latch inputs 1312 and 1324 causes both D-type flip-flop
non-inverting outputs 1336 and 1346 to transition to a high state, toggling ClkU
input 1372 as shown in Figures 13c.

Rate selector 310 tracks changes in the bit rate frequency of input
signal 155 while rejecting transient errors in the rate estimate signal
RE, which may be caused by jitter and pattern dependent variation in input
signal 155. Figures 14a-b are block diagrams of implementations of rate selector
310, in accordance with two embodiments of the invention.

In the first embodiment, which is shown in Figure 14a, rate selector
310 comprises a rate translation 1402, which includes a function block 1410 and
a function block 1420. Rate translation 1402 may receive as input rate estimate
signalRE, which is generated by discrete rate detector 301 of Figure 5. The
rate estimate signal RE may also be filtered prior to translation by 1402.

Several conventional techniques may be used to perform the one-to-one
mapping. For example, an analog computer may be used to convert the rate estimate
signal RE into control signals RS1 and RS2.
Alternately, rate detector 301 or rate selector 310 may be implemented using an
A/D converter whose binary outputs select an appropriate entry from a look-up table
for control signals RS1 and RS2. The look-up
table may include rate specific parameters for τED and
fc.

In yet another implementation, rate selector 310 may include a finite-state
machine for converting a digitized rate estimate signal RE into control signals
RS1 andRS2 using, for example, an appropriate
mapping algorithm.

When used in conjunction with, for example, continuous rate detector
301 of Figure 8, rate correction 1430 and adaptive filter 1440 may improve the accuracy
of the line rate estimate, which is received by rate translation 1402. Rate estimate
signalRE is applied to input 1432 of rate correction block 1430. Output 1434
from correction block 1430 goes to input 1442 of adaptive filter 1440, input 1462
of rate change detector 1460, and input 1472 of expected rate comparator 1470.

Rate change detector 1460 includes output 1466, and expected rate
comparator 1470 includes output 1476. Outputs 1466 and 1476 are combined in summation
1480, and applied to input 1452 of filter control 1450. Filter control 1450 includes
output 1454, which is applied to input 1444 of adaptive filter 1440. Adaptive filter
output 1446 connects to inputs 1412 and 1422 of function blocks 1410 and 1420, respectively.

Rate estimate signal RE appearing at input 312 of rate detector
301 may include predictable or measured error. Correction block 1430 may implement
an algorithm, which compensates for predicted or measured discrepancy between the
rate estimate signal RE and the bit rate of input signal 155.

Adaptive filter 1440 outputs a modified rate estimate REF,
which depends on the current value of rate estimate signal RE and the current
value's relationship to the past behavior of rate estimate signal RE. Considering
the behavior of rate estimate signal RE and modified rate estimate signal
REF at a set of discrete times, the current and past values
of rate estimate signal RE may be represented by the set of values {REi}
while the corresponding values of modified rate estimate signal REF
may be represented by the set of values {REFj}. Adaptive
filter 1440 may, for example, construct modified rate estimate signal
REF from rate estimate signal RE using the following
relationship:
where ai and bj are coefficients
which may be programmed through input 1444 subject.

Filter 1440, which includes an implementation of equation 15, reacts
rapidly to changing rate estimate signal RE when coefficient a1
is large, and conversely, reacts slowly when coefficients ai
are large for i >> 1. Coefficients bj may
be selected to affect persistent memory of a particular estimate. The constraint
may prevent bias in modified rate estimate signal REF,
while the constraint
may avert instability. Coefficients ai and bj
may be selected based on patterns in the variation of rate estimate signal
RE following a correction by rate correction 1430.

Rate change detector 1460 may distinguish small or insignificant fluctuations
in rate estimate signal RE, which is applied to input 1462, from rapid or
significant changes in the corrected rate estimate. Rate change detector 1460 may
construct a histogram of rate change values, and compute the likelihood that a current
rate change is significantly different from rate changes in the recent past. The
magnitude of output 1466 may reflect the magnitude or duration of a change in the
current rate estimate relative to previous changes. The response time for performing
rate change discrimination may be set by the rate of transitions at input 1464.

Expected rate comparator 1470 may compare the current rate estimate
signalRE with known common line rates or previous values of {REi},
which have persisted for a significant time interval. The magnitude of output 1476
may reflect the proximity of rate estimate signal RE to known rates or previous
persistent rates. The response time for comparing rate estimate signal
RE against expected rates may be set based on the rate of transitions at
input 1464.

While it has been illustrated and described what are at present considered
to be preferred embodiments and methods of the present invention, it will be understood
by those skilled in the art that various changes and modifications may be made,
and equivalents may be substituted for elements thereof without departing from the
true scope of the invention.

In addition, many modifications may be made to adapt a particular
element, technique or implementation to the teachings of the present invention without
departing from the central scope of the invention. Therefore, it is intended that
this invention not be limited to the particular embodiments and methods disclosed
herein, but that the invention include all embodiments falling within the scope
of the appended claims.

A method for recovering a clock signal from an input signal having a variable
bit rate, said method being characterized in that it comprises the steps
of :

estimating a minimum time interval between transitions in the input signal;

generating a first plurality of pulses corresponding respectively to transitions
in the input signal;

adjusting the duration of each of the first plurality of pulses based on the
estimated minimum time interval and inputting into a narrow-band filter the adjusted
first plurality of pulses;

determining a center frequency of the narrow-band filter based on the generated
minimum time interval; and

extracting in the narrow-band filter the clock signal from the adjusted first
plurality of pulses.

The method of claim 1, wherein the estimating step comprises the steps of:

generating a second plurality of pulses that correlate to the transitions in
the input signal; and

adjusting the duration of each of the second plurality of pulses, such that
the minimum time intervals between the transitions in the input signal match the
durations of the corresponding second plurality of pulses.

The method of claim 1, wherein the extracting step comprises the steps of:

generating a phase correction signal proportional to a difference between a
phase of the clock signal and a phase of the first plurality of pulses; and

adding the phase correction signal to a center frequency of an oscillator generating
the clock signal.

The method of claim 2, wherein the adjusting step comprises the steps of:

generating a voltage signal corresponding to the difference between the minimum
time interval between transitions in the input signal and the duration of the corresponding
second plurality of pulses; and

generating a current signal proportional to the voltage signal, wherein the
current signal controls the durations of each of the second plurality of pulses.

The method of claim 1, wherein the estimating step comprises the steps of:

generating a set of delayed input signals by passing the input signal through
a set of delay segments, wherein the set of delay segments delay the input signal
based on a set of specific delay times, respectively; and

generating a control signal based on a sum of the specific delay times that
are less than the minimum time interval between transitions in the input signal.

The method of claim 1, wherein the estimating step comprises the steps of:

generating a set of delayed input signals by passing the input signal serially
through a set of programmable delay segments, wherein the set of programmable delay
segments delay the input signal based on a set of specific delay times; and

generating a control signal based on a sum of the specific delay times that
are less than the minimum time interval between transitions in the input signal.

The method of claim 1, wherein the estimating step comprises the steps of:

generating one or more delayed transitions by passing the input signal through
a programmable time interval generator, wherein the delayed transitions are generated
based on a set of delay time values, respectively;

comparing transitions in the input signal with the generated delayed transitions,
and

adjusting one or more of the delay time values, such that one of the delay time
values matches the minimum time interval between the transitions in the input signal.

An apparatus for recovering a clock signal from an input signal having a variable
bit rate, said apparatus being characterized in that it comprises:

a rate detector (301) for estimating a minimum time interval between transitions
in the input signal;

a transition detector (320) for generating a first plurality of pulses corresponding
respectively to transitions in the input signal;

a narrow-band filter (330) connected to said transition detector, and

a rate selector (310) connected to said rate detector, said rate selector connected
to said transition detector for adjusting, based on the estimated minimum time interval,
the duration of each of the first plurality of pulses, and connected to said narrow-band
filter for determining a center frequency of the narrow-band filter that receives
the adjusted first plurality of pulses from said transition detector, said narrow-band
filter outputting the recovered clock signal.

The apparatus of claim 8, wherein said rate detector comprises:

a set of delay segments (S1-SN) connected in series for
generating a set of delayed input signals based on a set of specific delay times,
respectively, and

a set of latches (5501-550N) connected to the set of delay
segments, respectively, for generating a control signal based on a sum of the specific
delay times that are less than the minimum time interval between transitions in
the input signal.

The apparatus of claim 8, wherein said rate detector comprises:

a programmable time interval generator (810) for generating a set of delayed
transitions based on a set of delay time values, respectively; and

an edge transition comparator (820) connected to the programmable time interval
generator for comparing the set of delayed transitions with transitions in the input
signal and adjusting one or more the delay time values, such that one of the time
delay values matches the minimum time interval between the transitions in the input
signal.

The apparatus of claim 8, further comprising:

a calibration source (430) for generating a calibration signal having a set
of specific reference bit rates, wherein the rate detector estimates the reference
bit rate of the calibration signal; and

a response monitor (450) for determining differences between the specific reference
bit rates and the estimated reference bit rate and for adjusting the rate selector
until the one of the determined differences equals zero.

The apparatus of claim 8, wherein the rate detector comprises:

an interval generator (810) for generating a second plurality of transitions
that correlate to the transitions of the input signal;

a transition comparator (820) for determining a difference between the duration
of each of the second plurality of transitions and a time interval between each
of the transitions in the input signal; and

a feedback means (830) for adjusting the duration of each of the second plurality
of transitions until the determined difference equals zero.

The apparatus of claim 8, wherein the narrow-band filter comprises:

a phase comparator for generating a phase correction signal proportional to
a difference between a phase of the clock signal and a phase of the adjusted first
plurality of pulses; and

a first adder for adding the phase correction signal to a center frequency of
an oscillator generating the clock signal.

The apparatus of claim 13, wherein the narrow-band filter further comprises:

a frequency comparator for generating a frequency correction signal proportional
to a difference between a frequency of the clock signal and a frequency of the adjusted
first plurality of pulses; and

a second adder for adding the frequency correction signal to a center frequency
of the oscillator generating the clock signal.

The apparatus of claim 12, wherein the interval generator comprises:

an edge triggered one-shot for generating a second plurality of pulses that
correlate to the transitions in the input signal.

The apparatus of claim 12, wherein the interval generator comprises:

one or more resettable edge triggered delay elements (5101-510N)
for generating a second plurality of pulses that correlate to the transitions in
the input signal.