AMD Cayman further detailed

After yesterday's slide that showed all the specs regarding the upcoming Cayman and Antilles GPUs, some other slides have appeared online showing some details regarding the Cayman architecture. New slides show some rather interesting details like the VLIW4 SP design, the new dual graphics engine, and a feature called the "power containment".

After the inital rumours that AMD might switch from VLIW5 to VLIW4 design, came the Barts GPU which still retained the old VLIW5 design, altough it had some neat features regarding the actual design of the chip (individual dispatch processors for each of the SIMD block). The Cayman, on the other hand, feels like a real evolution as this one indeed features the new VLIW4 design which means that it has four stream processing units, as opposed to VLIW5 with four simple and one complex SP unit.

The VLIW4 design should provide similar preformance with a 10 percent reduction in die size, at least according to AMD. Although it looks like all four SM units are equal in size, so it appears that two are assigned with some special functions.

The talk of greater parallelization started with the Barts GPU which had individual dispatch processor for each SIMD Engine Block, something that certainly helped Barts in tessellation. Cayman on the other hand, has two graphics processing engines (GPEs), one for each SIMD engine, which means that it should raise the tessellation performance by up to 3-4x, at least on paper.

Last but not least slide shows something called the "power containment feature". This looks quite similar to the thing seen on Nvidia's GTX 580 card as this should keep the TDP at the pre-determined level. It has an integrated power control processor that monitors power draw every clock cycle and should provide direct control over GPU power draw.

On the other hand, the slide promises that it should be user controllable via AMD OverDrive Utility and AMD obviously learned from Nvidia's mistake.