WT11i-A DATA SHEET. Monday, 28 November Version 1.45

Transcription

1 WT11i-A DATA SHEET Monday, 28 November 2011 Version 1.45

2 Copyright Bluegiga Technologies All rights reserved. Bluegiga Technologies assumes no responsibility for any errors which may appear in this manual. Furthermore, Bluegiga Technologies reserves the right to alter the hardware, software, and/or specifications detailed here at any time without notice and does not make any commitment to update the information contained here. Bluegiga s products are not authorized for use as critical components in life support devices or systems. The WRAP is a registered trademark of Bluegiga Technologies The Bluetooth trademark is owned by the Bluetooth SIG Inc., USA and is licensed to Bluegiga Technologies. All other trademarks listed herein are owned by their respective owners.

12 3.4 PIO Current Sink and Source Capability 3.5 Antenna Specification Figure 2: WT11i PIO Current Drive Capability WT11i uses a monopole type on a chip antenna with maximum gain of 0.5 dbi. The radiation pattern and the total radiated efficiency are dependent on the layout and any metal around the antenna has an effect on the radiation characteristics. Typically the efficiency is 30 50%. WT11i-A Figure 3: Antenna radiation pattern in a USB dongle layout Page 12 of 41

16 4 Layout Guidelines WT11i is pin compatible with WT11 despite of slightly different external dimensions. For new design it recommended to follow the land pattern shown in the figure below. Figure 11: Recommended PCB land pattern for WT11i Do not place any copper under the antenna. The minimum recommended keep out area is shown in the figure 12. Any dielectric material in close proximity to the antenna will effect on the impedance matching of the antenna by lowering the resonance frequency. Figure 13 shows how different FR4 thickness under the antenna effect on the resonance frequency. Recommended PCB thickness for the PCB is 1.6 mm 2.8 mm. Avoid placing plastic cover closer than 3 mm from the antenna as this will also tune the resonance frequency downwards. Page 16 of 41

17 S11 (db) Edge of the PCB Do not place copper or any metal within the area marked with cross lines GND area with stitching vias Figure 12: Recommended metal keep put area for WT11i Effect of PCB thickness to the antenna impedance matching Freq (MHz) Figure 13: Effect of FR4 under the antenna to the resonant frequency 1 mm 2 mm 3 mm BT Band Use good layout practices to avoid excessive noise coupling to supply voltage traces or sensitive analog signal traces, such as analog audio signals. If using overlapping ground planes use stitching vias separated by max 3 mm to avoid emission from the edges of the PCB. Connect all the GND pins directly to a solid GND plane and make sure that there is a low impedance path for the return current following the signal and supply traces all the way from start to the end. Page 17 of 41

18 Place MIC biasing resistors symmetrically as close to microhone as pos Make sure that the bias trace does not cross separated GND regions (D AGND) so that the path for the return current is cut. If this is not possibl not separate GND regions but keep one solid GND plane. Keep the trace as short as possible A good practice is to dedicate one of the inner layers to a solid GND plane and one of the inner layers to supply voltage planes and traces and route all the signals on top and bottom layers of the PCB. This arrangement will make sure that any return current follows the forward current as close as possible and any loops are minimized. Recommended PCB layer configuration Figure 14: Typical 4-layer PCB construction Signals GND Power Signals Overlapping GND layers without GND stitching vias Overlapping GND layers with GND stitching vias shielding the RF energy Figure 15: Use of stitching vias to avoid emissions from the edges of the PCB Page 18 of 41

19 5 UART Interface This is a standard UART interface for communicating with other serial devices.wt11i UART interface provides a simple mechanism for communicating with other serial devices using the RS232 protocol. Four signals are used to implement the UART function. When WT11i is connected to another digital device, UART_RX and UART_TX transfer data between the two devices. The remaining two signals, UART_CTS and UART_RTS, can be used to implement RS232 hardware flow control where both are active low indicators. All UART connections are implemented using CMOS technology and have signalling levels of 0V and VDD. UART configuration parameters, such as data rate and packet format, are set using WT11i software. Note: In order to communicate with the UART at its maximum data rate using a standard PC, an accelerated serial port adapter card is required for the PC. Table 10: Possible UART Settings The UART interface is capable of resetting WT11i upon reception of a break signal. A break is identified by a continuous logic low (0V) on the UART_RX terminal, as shown in Figure 9. If tbrk is longer than the value, defined by PSKEY_HOST_IO_UART_RESET_TIMEOUT, (0x1a4), a reset will occur. This feature allows a host to initialise the system to a known state. Also, WT11i can emit a break character that may be used to wake the host. Figure 16: Break Signal Table 11 shows a list of commonly used data rates and their associated values for PSKEY_UART_BAUD_RATE (0x204). There is no requirement to use these standard values. Any data rate within the supported range can be set in the PS Key according to the formula in Equation 1 Page 19 of 41

20 Equation 1: Data Rate Table 11: Standard Data Rates Page 20 of 41

21 5.1 UART Bypass Figure 17: UART Bypass Architecture 5.2 UART Configuration While Reset is Active The UART interface for WT11i while the chip is being held in reset is tristate. This will allow the user to daisy chain devices onto the physical UART bus. The constraint on this method is that any devices connected to this bus must tristate when WT11i reset is de-asserted and the firmware begins to run. 5.3 UART Bypass Mode Alternatively, for devices that do not tristate the UART bus, the UART bypass mode on BlueCore4-External can be used. The default state of BlueCore4-External after reset is de-asserted; this is for the host UART bus to be connected to the BlueCore4-External UART, thereby allowing communication to BlueCore4-External via the UART. All UART bypass mode connections are implemented using CMOS technology and have signalling levels of 0V and VDD. In order to apply the UART bypass mode, a BCCMD command will be issued to BlueCore4-External. Upon this issue, it will switch the bypass to PIO[7:4] as Figure 17 indicates. Once the bypass mode has been invoked, WT11i will enter the Deep Sleep state indefinitely. In order to re-establish communication with WT11i, the chip must be reset so that the default configuration takes effect. It is important for the host to ensure a clean Bluetooth disconnection of any active links before the bypass mode is invoked. Therefore, it is not possible to have active Bluetooth links while operating the bypass mode. The current consumption for a device in UART bypass mode is equal to the values quoted for a device in standby mode. Page 21 of 41

22 6 USB Interface This is a full speed (12Mbits/s) USB interface for communicating with other compatible digital devices. WT11i acts as a USB peripheral, responding to requests from a master host controller such as a PC. The USB interface is capable of driving a USB cable directly. No external USB transceiver is required. The device operates as a USB peripheral, responding to requests from a master host controller such as a PC. Both the OHCI and the UHCI standards are supported. The set of USB endpoints implemented can behave as specified in the USB section of the Bluetooth v2.1 + EDR specification or alternatively can appear as a set of endpoints appropriate to USB audio devices such as speakers. As USB is a master/slave oriented system (in common with other USB peripherals), WT11i only supports USB Slave operation. 6.1 USB Data Connections The USB data lines emerge as pins USB_DP and USB_DN. These terminals are connected to the internal USB I/O buffers of the BlueCore4-External, therefore, have a low output impedance. To match the connection to the characteristic impedance of the USB cable, resistors must be placed in series with USB_DP/USB_DN and the cable. 6.2 USB Pull-Up resistor WT11i features an internal USB pull-up resistor. This pulls the USB_DP pin weakly high when WT11i is ready to enumerate. It signals to the PC that it is a full speed (12Mbits/s) USB device. The USB internal pull-up is implemented as a current source, and is compliant with section of the USB specification v1.2. The internal pull-up pulls USB_DP high to at least 2.8V when loaded with a 15k 5% pulldown resistor (in the hub/host) when VDD_PADS = 3.1V. This presents a Thevenin resistance to the host of at least 900. Alternatively, an external 1.5k pull-up resistor can be placed between a PIO line and D+ on the USB cable. The firmware must be alerted to which mode is used by setting PSKEY_USB_PIO_PULLUP appropriately. The default setting uses the internal pull-up resistor. 6.3 USB Power Supply The USB specification dictates that the minimum output high voltage for USB data lines is 2.8V. To safely meet the USB specification, the voltage on the VDD supply terminal must be an absolute minimum of 3.1V. Bluegiga recommends 3.3V for optimal USB signal quality. 6.4 Self-Powered Mode In self-powered mode, the circuit is powered from its own power supply and not from the VBUS (5V) line of the USB cable. It draws only a small leakage current (below 0.5mA) from VBUS on the USB cable. This is the easier mode for which to design, as the design is not limited by the power that can be drawn from the USB hub or root port. However, it requires that VBUS be connected to WT11i via a resistor network (Rvb1 and Rvb2), so WT11i can detect when VBUS is powered up. BlueCore4-External will not pull USB_DP high when VBUS is off. Self-powered USB designs (powered from a battery or PSU) must ensure that a PIO line is allocated for USB pullup purposes. A 1.5k 5% pull-up resistor between USB_DP and the selected PIO line should be fitted to the design. Failure to fit this resistor may result in the design failing to be USB compliant in self-powered mode. The internal pull-up in BlueCore is only suitable for bus-powered USB devices, e.g., dongles. Page 22 of 41

23 Figure 18: USB Connections for Self-Powered Mode The terminal marked USB_ON can be any free PIO pin. The PIO pin selected must be registered by setting PSKEY_USB_PIO_VBUS to the corresponding pin number. Identifier Value Function R S 0 to 10 (to be matched per design)** Impedance matching to USB cable R vb1 22k 5% VBUS ON sense divider R vb2 47k 5% VBUS ON sense divider Figure 19: USB Interface Component Values **) WT11i has internal 22 ohm series resistors at the USB lines. 6.5 Bus-Powered Mode In bus-powered mode, the application circuit draws its current from the 5V VBUS supply on the USB cable. WT11i negotiates with the PC during the USB enumeration stage about how much current it is allowed to consume. On power-up the device must not draw more than 100 ma but after being configured it can draw up to 500 ma. For WT11i, the USB power descriptor should be altered to reflect the amount of power required. This is accomplished by setting PSKEY_USB_MAX_POWER (0x2c6). This is higher than for a Class 2 application due to the extra current drawn by the Transmit RF PA. By default for WT11i the setting is 300 ma. When selecting a regulator, be aware that VBUS may go as low as 4.4V. The inrush current (when charging reservoir and supply decoupling capacitors) is limited by the USB specification. See the USB Specification. Some applications may require soft start circuitry to limit inrush current if more than 10uF is present between VBUS and GND. The 5V VBUS line emerging from a PC is often electrically noisy. As well as regulation down to 3.3V and 1.8V, applications should include careful filtering of the 5V line to attenuate noise that is above the voltage regulator bandwidth. Excessive noise on WT11i supply pins will result in reduced receiver sensitivity and a distorted RF transmit signal. Page 23 of 41

24 Figure 20: USB Connections for Bus-Powered Mode 6.6 USB Suspend Current All USB devices must permit the USB controller to place them in a USB suspend mode. While in USB Suspend, bus-powered devices must not draw more than 2.5mA from USB VBUS (self-powered devices may draw more than 2.5mA from their own supply). This current draw requirement prevents operation of the radio by bus-powered devices during USB Suspend. When computing suspend current, the current from VBUS through the bus pull-up and pull-down resistors must be included. The pull-up resistor at the device is 1.5 k. (nominal). The pull-down resistor at the hub is 14.25k. to 24.80k. The pull-up voltage is nominally 3.3V, which means that holding one of the signal lines high takes approximately 200uA, leaving only 2.3mA available from a 2.5mA budget. Ensure that external LEDs and/or amplifiers can be turned off by BlueCore4-External. The entire circuit must be able to enter the suspend mode. 6.7 USB Detach and Wake-Up Signaling WT11i can provide out-of-band signaling to a host controller by using the control lines called USB_DETACH and USB_WAKE_UP. These are outside the USB specification (no wires exist for them inside the USB cable), but can be useful when embedding WT11i into a circuit where no external USB is visible to the user. Both control lines are shared with PIO pins and can be assigned to any PIO pin by setting PSKEY_USB_PIO_DETACH and PSKEY_USB_PIO_WAKEUP to the selected PIO number. USB_DETACH is an input which, when asserted high, causes WT11i to put USB_DN and USB_DP in high impedance state and turns off the pull-up resistor on DP. This detaches the device from the bus and is logically equivalent to unplugging the device. When USB_DETACH is taken low, WT11i will connect back to USB and await enumeration by the USB host. USB_WAKE_UP is an active high output (used only when USB_DETACH is active) to wake up the host and allow USB communication to recommence. It replaces the function of the software USB WAKE_UP message (which runs over the USB cable) and cannot be sent while BlueCore4-External is effectively disconnected from the bus. Page 24 of 41

25 Figure 21: USB_Detach and USB_Wake_Up Signals 6.8 USB Driver A USB Bluetooth device driver is required to provide a software interface between BlueCore4-External and Bluetooth software running on the host computer. Please, contact for suitable drivers. 6.9 USB v2.0 Compliance and Compatibility Although WT11i meets the USB specification, CSR cannot guarantee that an application circuit designed around the module is USB compliant. The choice of application circuit, component choice and PCB layout all affect USB signal quality and electrical characteristics. The information in this document is intended as a guide and should be read in association with the USB specification, with particular attention being given to Chapter 7. Independent USB qualification must be sought before an application is deemed USB compliant and can bear the USB logo. Such qualification can be obtained from a USB plugfest or from an independent USB test house. Terminals USB_DP and USB_DN adhere to the USB Specification v2.0 (Chapter 7) electrical requirements. BlueCore4-External is compatible with USB v2.0 host controllers; under these circumstances the two ends agree the mutually acceptable rate of 12Mbits/s according to the USB v2.0 specification. Page 25 of 41

26 7 Serial Peripheral Interface (SPI) The SPI port can be used for system debugging. It can also be used for programming the Flash memory and setting the PSKEY configurations. WT11i uses 16-bit data and 16-bit address serial peripheral interface, where transactions may occur when the internal processor is running or is stopped. SPI interface is connected using the MOSI, MISO, CSB and CLK pins. Please, contact for detailed information about the instruction cycle. Page 26 of 41

27 8 PCM Codec Interface PCM is a standard method used to digitize audio (particularly voice) for transmission over digital communication channels. Through its PCM interface, WT11i has hardware support for continual transmission and reception of PCM data, thus reducing processor overhead for wireless headset applications. WT11i offers a bidirectional digital audio interface that routes directly into the baseband layer of the on-chip firmware. It does not pass through the HCI protocol layer. Hardware on WT11i allows the data to be sent to and received from a SCO connection. Up to three SCO connections can be supported by the PCM interface at any one time. WT11i can operate as the PCM interface master generating an output clock of 128, 256 or 512kHz. When configured as PCM interface slave, it can operate with an input clock up to 2048kHz. WT11i is compatible with a variety of clock formats, including Long Frame Sync, Short Frame Sync and GCI timing environments. It supports 13-bit or 16-bit linear, 8-bit µ-law or A-law companded sample formats at 8ksamples/s and can receive and transmit on any selection of three of the first four slots following PCM_SYNC. The PCM configuration options are enabled by setting PSKEY_PCM_CONFIG32. WT11i interfaces directly to PCM audio devices. NOTE: Analog audio lines are very sensitive to RF disturbance. Use good layout practices to ensure noise less audio. Make sure that the return path for the audio signals follows the forward current all the way as close as possible and use fully differential signals when possible. Do not compromise audio routing. 8.1 PCM Interface Master/Slave When configured as the master of the PCM interface, WT11i generates PCM_CLK and PCM_SYNC. Figure 22: PCM Interface Master When configured as the Slave of the PCM interface, WT11i accepts PCM_CLK rates up to 2048kHz. Page 27 of 41

28 Figure 23: PCM Interface Slave 8.2 Long Frame Sync Long Frame Sync is the name given to a clocking format that controls the transfer of PCM data words or samples. In Long Frame Sync, the rising edge of PCM_SYNC indicates the start of the PCM word. When WT11i is configured as PCM master, generating PCM_SYNC and PCM_CLK, then PCM_SYNC is 8-bits long. When WT11i is configured as PCM Slave, PCM_SYNC may be from two consecutive falling edges of PCM_CLK to half the PCM_SYNC rate, i.e., 62.5s long. Figure 24: Long Frame Sync (Shown with 8-bit Companded Sample) WT11i samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge. PCM_OUT may be configured to be high impedance on the falling edge of PCM_CLK in the LSB position or on the rising edge. 8.3 Short Frame Sync In Short Frame Sync, the falling edge of PCM_SYNC indicates the start of the PCM word. PCM_SYNC is always one clock cycle long. Page 28 of 41

29 Figure 25: Short Frame Sync (Shown with 16-bit Sample) As with Long Frame Sync, WT11i samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge. PCM_OUT may be configured to be high impedance on the falling edge of PCM_CLK in the LSB position or on the rising edge. 8.4 Multi-slot Operation More than one SCO connection over the PCM interface is supported using multiple slots. Up to three SCO connections can be carried over any of the first four slots. 8.5 GCI Interface Figure 26: Multi-slot Operation with Two Slots and 8-bit Companded Samples WT11i is compatible with the GCI, a standard synchronous 2B+D ISDN timing interface. The two 64kbits/s B channels can be accessed when this mode is configured. Page 29 of 41

30 Figure 27: GCI Interface The start of frame is indicated by the rising edge of PCM_SYNC and runs at 8kHz. With WT11i in Slave mode, the frequency of PCM_CLK can be up to 4.096MHz. 8.6 Slots and Sample Formats WT11i can receive and transmit on any selection of the first four slots following each sync pulse. Slot durations can be either 8 or 16 clock cycles. Durations of 8 clock cycles may only be used with 8-bit sample formats. Durations of 16 clocks may be used with 8-bit, 13-bit or 16-bit sample formats. WT11i supports 13-bit linear, 16-bit linear and 8-bit -law or A-law sample formats. The sample rate is 8ksamples/s. The bit order may be little or big endian. When 16-bit slots are used, the 3 or 8 unused bits in each slot may be filled with sign extension, padded with zeros or a programmable 3-bit audio attenuation compatible with some Motorola codecs. Page 30 of 41

31 Figure 28: 16-bit Slot Length and Sample Formats 8.7 Additional Features WT11i has a mute facility that forces PCM_OUT to be 0. In master mode, PCM_SYNC may also be forced to 0 while keeping PCM_CLK running which some codecs use to control power down. 8.8 PCM_CLK and PCM_SYNC Generation WT11i has two methods of generating PCM_CLK and PCM_SYNC in master mode. The first is generating these signals by DDS from BlueCore4-External internal 4MHz clock. Using this mode limits PCM_CLK to 128, 256 or 512kHz and PCM_SYNC to 8kHz. The second is generating PCM_CLK and PCM_SYNC by DDS from an internal 48MHz clock (which allows a greater range of frequencies to be generated with low jitter but consumes more power). This second method is selected by setting bit 48M_PCM_CLK_GEN_EN in PSKEY_PCM_CONFIG32. When in this mode and with long frame sync, the length of PCM_SYNC can be either 8 or 16 cycles of PCM_CLK, determined by LONG_LENGTH_SYNC_EN in PSKEY_PCM_CONFIG32. The Equation XXX describes PCM_CLK frequency when being generated using the internal 48MHz clock: Page 31 of 41

32 Equation 2: PCM_CLK Frequency When Being Generated Using the Internal 48MHz Clock The frequency of PCM_SYNC relative to PCM_CLK can be set using Equation XXX: Equation 3: PCM_SYNC Frequency Relative to PCM_CLK CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_LOW_JITTER_CONFIG. As an example, to generate PCM_CLK at 512kHz with PCM_SYNC at 8kHz, set PSKEY_PCM_LOW_JITTER_CONFIG to 0x PCM Configuration The PCM configuration is set using two PS Keys, PSKEY_PCM_CONFIG32 detailed in Table 12 and PSKEY_PCM_LOW_JITTER_CONFIG in Table 13. The default for PSKEY_PCM_CONFIG32 is 0x , i.e., first slot following sync is active, 13-bit linear voice format, long frame sync and interface master generating 256kHz PCM_CLK from 4MHz internal clock with no tri-state of PCM_OUT. Page 32 of 41

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