//===-- ARMFeatures.h - Checks for ARM instruction features -----*- C++ -*-===////// The LLVM Compiler Infrastructure//// This file is distributed under the University of Illinois Open Source// License. See LICENSE.TXT for details.////===----------------------------------------------------------------------===////// This file contains the code shared between ARM CodeGen and ARM MC////===----------------------------------------------------------------------===//#ifndef TARGET_ARM_FEATURES_H#define TARGET_ARM_FEATURES_H#include"MCTargetDesc/ARMMCTargetDesc.h"namespacellvm{template<typenameInstrType>// could be MachineInstr or MCInstboolIsCPSRDead(InstrType*Instr);template<typenameInstrType>// could be MachineInstr or MCInstinlineboolisV8EligibleForIT(InstrType*Instr){switch(Instr->getOpcode()){default:returnfalse;caseARM::tADC:caseARM::tADDi3:caseARM::tADDi8:caseARM::tADDrr:caseARM::tAND:caseARM::tASRri:caseARM::tASRrr:caseARM::tBIC:caseARM::tEOR:caseARM::tLSLri:caseARM::tLSLrr:caseARM::tLSRri:caseARM::tLSRrr:caseARM::tMOVi8:caseARM::tMUL:caseARM::tMVN:caseARM::tORR:caseARM::tROR:caseARM::tRSB:caseARM::tSBC:caseARM::tSUBi3:caseARM::tSUBi8:caseARM::tSUBrr:// Outside of an IT block, these set CPSR.returnIsCPSRDead(Instr);caseARM::tADDrSPi:caseARM::tCMNz:caseARM::tCMPi8:caseARM::tCMPr:caseARM::tLDRBi:caseARM::tLDRBr:caseARM::tLDRHi:caseARM::tLDRHr:caseARM::tLDRSB:caseARM::tLDRSH:caseARM::tLDRi:caseARM::tLDRr:caseARM::tLDRspi:caseARM::tSTRBi:caseARM::tSTRBr:caseARM::tSTRHi:caseARM::tSTRHr:caseARM::tSTRi:caseARM::tSTRr:caseARM::tSTRspi:caseARM::tTST:returntrue;// there are some "conditionally deprecated" opcodescaseARM::tADDspr:caseARM::tBLXr:returnInstr->getOperand(2).getReg()!=ARM::PC;// ADD PC, SP and BLX PC were always unpredictable,// now on top of it they're deprecatedcaseARM::tADDrSP:caseARM::tBX:returnInstr->getOperand(0).getReg()!=ARM::PC;caseARM::tADDhirr:returnInstr->getOperand(0).getReg()!=ARM::PC&&Instr->getOperand(2).getReg()!=ARM::PC;caseARM::tCMPhir:caseARM::tMOVr:returnInstr->getOperand(0).getReg()!=ARM::PC&&Instr->getOperand(1).getReg()!=ARM::PC;}}}#endif