The Cadence Academic Network helps build strong relationships between academia and industry, and promotes the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence.

A huge knowledge exchange platform for academia to network with industry. We are looking for academic speakers to talk about their research to the industry attendees at the Academic Track at CDNLive EMEA and Silicon Valley.

The Cadence® Innovus™ Implementation System is optimized for industry-leading embedded processors, as well as for 16nm, 14nm, 10nm, and 7nm processes, helping you get an earlier design start with a faster ramp-up. With unique new capabilities in placement, optimization, routing, and clocking, the Innovus system features an architecture that accounts for upstream and downstream steps and effects in the design flow. This architecture minimizes design iterations and provides the runtime boost you’ll need to get to market faster. Using the Innovus system, you’ll be equipped to build integrated, differentiated systems with less risk.

The Innovus system features a variety of key capabilities. Its massively parallel architecture can handle large designs and take advantage of multi-threading on multi-core workstations, as well as distributed processing over networks of computers.

Next-generation slack-driven routing with track-aware timing optimization addresses signal integrity early on and improves post-route correlation. The Innovus system includes full-flow multi-objective technology, which makes concurrent electrical and physical optimization possible. It also shares a customizable flow via a common UI and user commands with synthesis and signoff tools. As a result, you can take advantage of robust reporting and visualization, improving your design efficiency and productivity.

Cadence’s Genus™ Synthesis Solution is integrated tightly with the Innovus system, which enables a seamless move from RTL synthesis to netlist. With shared placement technology in the GigaPlace™ tool for physical synthesis, this offers a big benefit for advanced-node design convergence.

Cadence’s Tempus™ Timing Signoff Solution, Quantus™ QRC Extraction Solution, and Voltus™ IC Power Integrity Solution are integrated with the Innovus system. With this integration, you can accurately model the parasitics, timing, signal, and power integrity issues at the early stage of physical implementation, and achieve faster convergence on these electrical metrics, resulting in faster design closure.

Our products enable the reception of broadband data and video content, requiring high levels of performance, small silicon die-size, and rapid time to market. Innovus Implementation System has provided us with unprecedented full-flow speed-up, so we can deliver reliable designs to market faster.

We've tested the full Innovus Implementation System flow on some of our most congestion-challenged 28nm networking IP blocks and have achieved excellent results while seeing significant throughput improvements. The new Cadence solution has enabled us to resolve our most difficult timing requirements…

Our next system-on-chip (SoC) projects will be on a 16nm process, and the Innovus Implementation System can enable much larger blocks than previously possible, decreasing area and top-level complexity.

At ARM, we push the limits of silicon and EDA tool technology to deliver products on tight schedules required for consumer markets. We partnered closely with Cadence to utilize the Innovus Implementation System during the development of our ARM® Cortex®-A72 processor. This demonstrated a 5X runtime improvement…

The Innovus Implementation System significantly improved the runtime on a critical multi-million-cell IP core compared to our previous solution. With runtimes improved to deliver more than a million cells per day of implementation throughput, we can confidently drive our aggressive schedules…

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