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Abstract

A digital programmable circuit is described for shaping and adjusting clock pulses. Modern computer systems require several clock pulses to permit adequate communication between the various subunits. The performance of such systems depends, to a considerable degree, on the accuracy with which these clock pulses are timed. The enormous delay tolerances (up to 0 70%) of semiconductor technologies lead to relatively long gaps between the clock pulses (no overlap allowed) or expensive manual tuning by unreliable adjustable resistors or capacitors. The circuit shown in the figure avoids these drawbacks by a programmable delay for each slope of a pulse passing it. By means of the proposed circuit, the timing of a clock pulse is digitally adjusted.

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United States

Language

English (United States)

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Digital Programmable Clock Pulse Shaper

A digital programmable circuit is described for shaping and
adjusting clock pulses. Modern computer systems require several clock
pulses to permit adequate communication between the various subunits.
The performance of such systems depends, to a considerable degree, on
the accuracy with which these clock pulses are timed. The enormous
delay tolerances (up to 0 70%) of semiconductor technologies lead to
relatively long gaps between the clock pulses (no overlap allowed) or
expensive manual tuning by unreliable adjustable resistors or
capacitors. The circuit shown in the figure avoids these drawbacks by
a programmable delay for each slope of a pulse passing it. By means
of the proposed circuit, the timing of a clock pulse is digitally
adjusted. The circuit operates as follows: A clock pulse, fed to
input IN, passes a chain of two inverters I1, I2 with open collector
outputs and a subsequent non-inverting driver (DR). The values of
the pull-up resistors R1, R2 influence the rise time of the output
pulses. As the second inverter I2 receives the inverted pulse, both
the leading and the trailing slopes of an input pulse can be changed.

The different values of the pull-up resistors lead to variable
delays of the chain switching times ton and toff. The resistor
values depend on the contents of the associated registers REG1 and
REG2. This means that the timing of the clock pulse at output OUT
can be influenced by changing the informa...