There were so many changes in the x86/asm, x86/apic and x86/mm topics in this cycle that the topical separation of -tip broke down somewhat - so the result is a more traditional architecture pull request, collected into the 'x86/core' topic.

The topics were still maintained separately as far as possible, so bisectability and conceptual separation should still be pretty good - but there were a handful of merge points to avoid excessive dependencies (and conflicts) that would have been poorly tested in the end.

You should see a single merge conflict when merging this, in tools/testing/selftests/x86/Makefile.

Note: there was also dependency on locking/core changes, due to wide reaching locking changes - please disregard this pull request if you have not merged locking/core by this time yet.

The next cycle will hopefully be much more quiet (or at least will have fewer dependencies).

This now reflects the actual hardware and allowed us to distangle the domain specific code from the underlying parent domain, which can be optional in the case of interrupt remapping. It's a clear separation of functionality and removes quite some duct tape constructs which plugged the remap code between ioapic/msi/hpet and the vector management.

- Tons of cleanups and small speedups, micro-optimizations. This is in preparation to move a good chunk of the low level entry code from assembly to C code. (Denys Vlasenko, Andy Lutomirski, Brian Gerst)

- Moved all system entry related code to a new home under arch/x86/entry/. (Ingo Molnar)

- Removal of the fragile and ugly CFI dwarf debuginfo annotations. Conversion to C will reintroduce many of them - but meanwhile they are only getting in the way, and the upstream kernel does not rely on them. (Ingo Molnar)

- New ioremap_wt()/set_memory_wt() interfaces to support Write-Through cached memory mappings. This is especially important for good performance on NVDIMM hardware. (Toshi Kani)

x86/ras changes:

- Add support for deferred errors on AMD (Aravind Gopalakrishnan)

This is an important RAS feature which adds hardware support for poisoned data. That means roughly that the hardware marks data which it has detected as corrupted but wasn't able to correct, as poisoned data and raises an APIC interrupt to signal that in the form of a deferred error. It is the OS's responsibility then to take proper recovery action and thus prolonge system lifetime as far as possible.