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My name is Sven Andersson and I
work as a consultant in embedded
system design, implemented in ASIC
and FPGA.
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Implementing the hardware platformAfter more than 5 month of hard work we have reached the point of no return, it is time to program the FPGA.After completing hardware platform design entry, we are ready to:

To create the BIT file for downloading and implement the design, we must first set up our User Constraints File (UCF). As in ISE, an FPGA design implemented using EDK requires a UCF. Primarily, the UCF specifies pinouts and timing constraints. It can also control a variety of other hardware implementation features, such as the configurable electrical characteristics of our FPGA I/O signals.

Setting up our User Constraints File

To access the UCF file for our XPS project:

Click the Project tab in the Project Information Area of the main window and look for the UCF file under the Project Files heading.

Double-click the UCF file to open it in the System Assembly panel.

The UCF has the same base filename as the Xilinx Microprocessor Project (XMP) file, and it must reside in the data subfolder of our project directory.

Specifying Pin Constraints

We must often provide a Location (LOC) constraint to define the FPGA pin location for each external port. To view the list of the external ports, do the following:

In the XPS main window, click the System Assembly tab.

Select the Ports filter.

LOC constraints take the following form:

NET RS232_RX_pin LOC=U4;

Specifying Timing Constraints

For most embedded processor designs, we need only specify the input (reference) clock period to ensure that your system meets performance requirements. In some cases, our design might contain off-chip peripherals, such as memory controllers, that have particular input and output timing requirements. We should also declare Timing IGnore (TIG) constraints on signals that are not timing critical to allow better place and route tools to optimize other timing paths. The following are typical of the basic timing constraints we must provide in our UCF file:

Net sys_clk_pin PERIOD = 20000 ps;Net sys_rst_pin TIG;

The implementation directory

The result from netlist generation is stored in the implemenation directory. All the NGC files from the synthesis runs are collected here. The bitstream generation program will include all the netlist files to generate the final bitstream. We have to make sure all netlist files can be found in the implementation directory before we start the bitstream generation. When we generated the ETC_DUAL_PORT_1024x32 memory using Coregen (see part 4) the netlist file ETC_DUAL_PORT_1024x32.edn was created. This file will also be copied to the implementation directory.

Start bitstream generation

From the XPS Hardware menu we choose Generate Bitstream to start the bitstream generation.

Here is a printout from the startup of the program.

At Local date and time: Fri May 25 16:18:25 2007 make -f ETC_system.make bits started...*********************************************

The Bitstream generation uses the XFLOW program to setup and run the complete program flow. XFLOW is a command line program that automates Xilinx synthesis, implementation, and simulation flows. XFLOW reads a design file as input as well as a flow file and an option file. Xilinx provides a default set of flow files that automate which Xilinx programs are run to achieve a specific design flow. For example, a flow file can specify that NGDBuild, MAP, PAR, and TRACE are run to achieve an implementation flow for an FPGA. Here is the xflow log file from our bitstream generation run. For more information about XFLOW read the Xilinx Development System Reference Guide. (Courtesy of Xilinx)

The NGC files are processed, along with the system constraints, through Xilinx tools (NGDBuild, MAP, PAR, and TRACE) when XPS invokes the XFlow command-line program.

Script file to run XFlow

Here is the script file that are generated when we start the bitstream generation.

During the bitstream generation a number of files have been generated.

File Name

Description

Readable

ETC_system.bgn

Bitgen log file

Yes

ETC_system.bit

Bitstream download file

No

ETC_system.bld

Ngdbuild log file

Yes

ETC_system.bmm

Address map bram

Yes

ETC_system.drc

Drc log file

Yes

ETC_system.ncd

Mapping output file

No

ETC_system.ngc

XST synthesis output file

No

ETC_system.ngd

Xilinx native generic database format

No

ETC_system.pad

Pin definition file (spreadsheet import file)

Yes

ETC_system.par

Placer report file

Yes

ETC_system.pcf

Map report file

Yes

ETC_system.twr

Trace report file (timing constraints)

Yes

ETC_system.twx

Trace XML file

Yes

ETC_system.ucf

User constraints file (copied from data dir)

Yes

ETC_system.unroutes

Displays unrouted nets

Yes

ETC_system_pad.cvs

Pin definition file (spreadsheet import file)

Yes

ETC_system_pad.txt

Pin definition file (text format)

Yes

ETC_system_map.mrp

Mapping report file

Yes

Configuration of the FPGA

Virtex-4 devices are configured by loading application-specific configuration data�the bitstream�into internal memory. Because Xilinx FPGA configuration memory is volatile, it must be configured each time it is powered-up. The bitstream is loaded into the device through special configuration pins. These configuration pins serve as the interface for a number of different configuration modes:

Platform Cable USB is a high-performance download cable attaching to user hardware for the purpose of programming or configuring any of the following Xilinx devices:

ISP Configuration PROMs

CPLDs

FPGAs

Platform Cable USB attaches to the USB port on a desktop or laptop PC with an off-the-shelf Hi-Speed USB A-B cable. It derives all operating power from the hub port controller. No external power supply is required. A sustained slave-serial FPGA configuration transfer rate of 24 Mb/s is possible in a Hi-Speed USB environment. Actual transfer rates can vary if bandwidth of the hub is being shared with other USB peripheral devices. Platform Cable USB attaches to target systems using a 14-conductor ribbon cable designed for high-bandwidth data transfers.

In the Xilinx answers database we find answer #22648: 9.1i iMPACT - Installing Xilinx cable drivers on Linux operating system/kernel version 2.6. We will install the drivers in our Ubuntu Linux 7.04 system. To find out which version of the kernel we have installed we use the command:

XILINX JTAG tools on Linux without proprietary kernel modules

When using Xilinx JTAG software like Impact, Chipscope and XMD on Linux, the proprietary kernel module windrvr from Jungo is needed to access the parallel- or usb-cable. As this module does not work with current linux kernel versions (> 2.6.18) a library was developed, which emulates the module in userspace and allows the tools to access the JTAG cable without the need for a proprietary kernel module.Let's give it a try. To me it sounds like a much better solution than the one Xilinx provides. We will follow the instructions found in this README file.

To use the device as an ordinary user, put the following line in the file /etc/udev/rules.d/50-xilinx-usb-pav.rules (or use any file name you like) ACTION=="add",BUS=="usb",SYSFS{idVendor}=="03fd",MODE="666"

sudo gedit /etc/udev/rules.d/50-xilinx-usb-pav.rules and add the line above

Make sure the green status light is on. The USB cable interface must be connected during VMware Fusion Ubuntu bootup. WMware will detect the USB cable interface and automatically connect it.

Permission denied. Change owner

Can't open /dev/parport0: Permission denied

If this message is displayed in the terminal when starting iMPACT, we have to change the owner of this file from root to the current user. Like this: sudo chown svenand /dev/parport0. This has to repeated every time after we have booted the Linux OS.

Unlocking the cable interfaceUse the following commands to unlock the cable interface if needed:

==> impact -batch > setMode -bscan > cleancablelock > quit

iMPACT FPGA configuration tool

iMPACT allows designers to easily perform device configuration and programming either as a batch operation or through a convenient graphical user interface.iMPACT is a full featured software tool used for configuration and programming of all Xilinx PLDs (FPGAs and CPLDs) and PROMs. iMPACT features a series of design wizards that easily guide the user through each step of the configuration process.

Starting iMPACT

==> impact & (xilinx_install_dir/bin/lin/impact)

We will create a new project in iMPACT and give it a name ETC_system.icf

We will use Boundary-Scan (JTAG) to configure the FPGA.

When we click Finish the program connects to our evaluation board. Here is the printout from iMPACT:

Connecting to cable (Usb Port - USB21).Checking cable driver.File version of /home/svenand/cad/xilinx91i/bin/lin/xusbdfwu.hex = 1025(dec), 0x0401.File version of /usr/share/xusbdfwu.hex = 1025(dec), 0x0401. libusb-driver.so version: 2007-05-27 00:37:02. Cable PID = 0008. Max current requested during enumeration is 280 mA. Cable Type = 3, Revision = 0. Cable Type = 0x0605. Setting cable speed to 6 MHz.Cable connection established.Firmware version = 1025.CPLD file version = 0012h.CPLD version = 0006h.WARNING:iMPACT:2356 - Platform Cable USB firmware must be updated. This operation may take up to 10 minutes on a USB 2.0 port or up to 30 minutes on a USB 1.1 port. Please do not stop the process or disconnect the cable prior to completion. The cableSTATUS LED will be RED for the duration of the update process.

Per Bj. BRO October 2, 2009 05:34 PM PDTThank you for a very clear description. If your Xilinx board USB cable is not detected with product ID 000f, when executing 'lsusb', then you might have to copy all of the xusb*.hex files from the /Xilinx/bin/lin directory to /usr/share. This is clear if you look at the rules file. In my case, the product ID was 000d, and I needed the xusb_emb.hex file.