As semiconductor process technology scales down to sub 30nm process node and beyond dimensions, the
printability and process window of the lithographic patterns are seriously reduced due to the fundamental
limit of the lithography and process variations.
In this paper, we introduce a various analysis methodology of pattern variability for higher device
performance using with applications of DBV (Design Based Verification).
Pattern variability is affected by both pattern process margins and electrical margins such as distribution of
gate length.
Even if post lithography verification would carry out after model based OPC, Pattern variability is increased
not only unpredictable OPC hotspots but also unanticipated hotspots by AEI loading skew in full-chip. Secondly, electrical hotspots which are extracted by tail distributions of gate length are not always reliable enough to represent critical path with gate length of full-chip. We constructed New OCV extraction flow with a full-chip pattern classification that is required for both gate distribution accuracy and analysis of gate tail patterns. In this report, we investigated about the relationship between a pattern feature and pattern distribution of transistor length.