Advanced Computer Design

Exercise 4 - Network-on-Chip Analysis

This week's lecture looked at Network-on-Chip (NOC) designs. These can be found on filer here:

/usr/groups/ecad-labs/ACS-ACD/bluespec-examples/SimpleSwitch

Copy this directory into your file space.

This directory contains the following files:

Makefile
FairMerge.bsv
SimpleSwitch.bsv

The Makefile is setup for simulation. FairMerge.bsv is the library mentioned in the lecture that is used to merge N input streams to one output stream. This is used in all of the NoC designs. This module also contains an arbiter that is an interesting example of the use of RWires and inter-rule signalling within one clock cycle.

This gives statistical output at three sample points in time for three
different NoC designs. The NoC configuration is established
by mkTestLinearNetworkReads which creates a linear network of
8 NoCs with node (0,0) acting as a fake memory device and the other
nodes acting as fake processors. The following definitions at the top
SimpleSwitch.bsv control the number of concurrent reads and the delay
between reads for each processor:

// number of concurrent reads
that are allowed to happen `define NUMBER_CONCURRENT_READS 1
// delay between read requests being sent
`define DELAY_BETWEEN_READS 0

The block of numbers in the simulation output represent the current
state of the memory access latencies for the fake processors.

Task

Adjust NUMBER_CONCURRENT_READS between 1 and 5 to see what
impact more traffic has on the processors. Graph the results and
provide an explanation of what happens.

Optional Task

Modify mkTestLinearNetworkReads to add some north-to-south
traffic generators to see how this traffic impacts latency on the
east-west links for different NoC designs.