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Description

The DDR4 IP incorrectly programs the WR value for Mode Register 0 (MR0) for some scenarios. For example, for DDR4 operation at 2400Mb/s tWR=15ns and tCK=833ps so the Write Recovery (WR) time should be 18 clocks.

However, the DDR4 IP incorrectly configured MR0 for 20 clocks which can have a negative impact on controller efficiency or result in DRAM errors when using the PHY Only IP.

For example, the following error message might be seen during PHY Only simulations if the users controller is programmed for 18 clocks but the PHY IP is programmed for 20: