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Acceleration

Acceleration are techniques that are used to address performance shortcomings of traditional simulation. For example, the design model (i.e., DUT) can be mapped into a hardware accelerator and run much faster during verification, while the testbench continues to run in simulation on a workstation. In this section of the Verification Academy, we focus on building verification acceleration skills.

Seminars

Design & Verification Languages

Verification languages are the foundation of the very dynamic electronics industry. Industry continually demands improvements in the process of providing differentiated products into their markets. These verification language courses provide in-depth knowledge of key design and verification languages so that you can identify and deploy them in your upcoming projects.

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Formal-Based Techniques

This topic area focuses on formal-based techniques, ranging from formal property checking to clock-domain crossing (CDC) verification. Assertion-based verification (as it relates to formal property checking) is also covered in this topic area.

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Seminars

FPGA Verification

The definition of what FPGA really means has changed dramatically over the last two decades. Whether blazing the trail or being on the trailing edge of Moore’s Law, this is an exciting time to be an FPGA Designer. New opportunities bring new challenges for the FPGA market. As devices grow and become more complex resembling complete systems, the task of verifying such a system becomes daunting. In this section you will find timely, unbiased information from subject-matter experts that will help you navigate through this ever-changing landscape.

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Seminars

Planning, Measurement, and Analysis

This topic area focuses on the early stages of a verification project. Topics include considerations for analyzing and evolving your verification capabilities, verification planning, and the introduction of metrics into a flow to measure success.

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Seminars

Simulation-Based Techniques

This topic area focuses on simulation-based techniques, ranging from stimulus generation, coverage modeling, and correctness checking. Building a contemporary testbench using UVM is also covered in this topic area.

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Seminars

UVM/OVM

Welcome to the most complete UVM/OVM Online resource collection.

Here you’ll find everything you need to get up to speed on UVM, OVM and latest additions; UVM Express and UVM Connect. Whether it’s downloading the kit(s), discussion forums or online or in-person training. The UVM/OVM Academy Courses provide a great overview of the introductory and advanced methodology concepts, including videos that walk you through some useful code examples.

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Formal Assertion-Based Verification

In this course the instructors will show how to get started with direct property checking including: test planning for formal, SVA coding tricks that get the most out of the formal analysis engines and much more.

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Formal-Based Technology: Automatic Formal Solutions

After a brief introductory session outlining the general architecture of formal apps, in each subsequent session of the course will deep dive on a specific verification challenge and the corresponding formal application.

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Power Aware CDC Verification

This course describes the low power CDC methodology by discussing the low power CDC challenges, describing the UPF-related power logic structures relevant to CDC analysis, and explaining a low power CDC verification methodology.

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VHDL-2008 Why It Matters

VHDL-2008 matters because it facilitates advanced verification, adds reusable data structures, simplifies RTL coding and adds fixed and floating point math packages. VHDL-2008 is the largest change to VHDL since 1993.

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Coverage Cookbook

The Coverage Cookbook describes the different types of coverage that are available to keep track of the progress of the verification process, how to create a functional coverage model from a specification, and provides examples of how to implement functional coverage for different types of designs.

Courses

UVM Cookbook

The UVM library is both a collection of classes and a methodology for how to use those base classes. UVM brings clarity to the SystemVerilog language by providing a structure for how to use the features in SystemVerilog. However, in many cases UVM provides multiple mechanisms to accomplish the same work.

UVM Resources

UVM Documentation

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OVM Cookbook

The OVM is an open source SystemVerilog class library that was the outcome of a collaboration between Mentor Graphics and Cadence Design Systems. There are three main reasons why you should consider using the OVM and these are productivity, commercial considerations and enablement.

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About Us

The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

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Verification Horizons

The Verification Horizons publication expands upon verification topics to provide concepts, values, methodologies and examples to assist with the understanding of what these advanced functional verification technologies can do and how to most effectively apply them.

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Verification Academy is the most comprehensive resource for verification training.

Mentor Graphics' Verification Academy is a first of its kind—unlike anything in the industry. Its goals are to provide the skills necessary to mature an organization's advanced functional verification process capabilities. To this end, the Verification Academy provides a methodological bridge between high-level value propositions (related to advanced verification technology) and the low-level details (related to specific tool and verification language details).