4-bit binary counters feature an internal carry look-ahead and can beused for high-speed counting. Synchronous operation is provided byhaving all flip-flops clocked simultaneously on the positive-goingedge of the clock. The clock input is buffered.

The outputs of the counters may be preset to High or Low level. ALow level at the Parallel Enable (PE) input disables the countingaction and causes the data at the D0­D3 inputs to be loaded intothe counter on the positive-going edge of the clock (provided thatthe setup and hold requirements for PE are met). Preset takes placeregardless of the levels at Count Enable (CEP, CET) inputs.

A Low level at the Master Reset (MR) input sets all the four outputsof the flip-flops (Q0 ­ Q3) in 74F161A to Low levels, regardless ofthe levels at CP, PE, CET and CEP inputs (thus providing anasynchronous clear function). For the 74F163A, the clear function issynchronous. A Low level at the Synchronous Reset (SR) input setsall four outputs of the flip-flops (Q0 ­ Q3) to Low levels after the nextpositive-going transition on the clock (CP) input (provided that thesetup and hold time requirements for SR are met). This actionoccurs regardless of the levels at PE, CET, and CEP inputs. Thesynchronous reset feature enables the designer to modify themaximum count with only one external NAND gate (see Figure 1).The carry look-ahead simplifies serial cascading of the counters.Both Count Enable (CEP and CET) inputs must be High to count.The CET input is fed forward to enable the TC output. The TCoutput thus enabled will produce a High output pulse of a durationapproximately equal to the High level output of Q0. This pulse canbe used to enable the next cascaded stage (see Figure 2). The TCoutput is subjected to decoding spikes due to internal raceconditions. Therefore, it is not recommended for use as clock orasynchronous reset for flip-flops, registers, or counters.

TYPE

TYPICAL

f

MAX

TYPICAL SUPPLY CURRENT

(TOTAL)

74F161A74F163A

130MHz

46mA

ORDERING INFORMATION

ORDER CODE

DRAWING

DESCRIPTION

COMMERCIAL RANGE

V

CC

= 5V

±

10%, T

amb

= 0

°

C to +70

°

C

INDUSTRIAL RANGE

V

CC

= 5V

±

10%, T

amb

= ­40

°

C to +85

°

C

DRAWING

NUMBER

16-pin plastic DIP

N74F161AN, N74F163AN

I74F161AN, I74F163AN

SOT38-4

16-pin plastic SO

N74F161AD, N74F163AD

I74F161AD, I74F163AD

SOT109-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F (U.L.) HIGH/LOW

LOAD VALUE HIGH/LOW

D0 ­ D3

Data inputs

1.0/1.0

20

µ

A/0.6mA

CEP

Count Enable Parallel input

1.0/1.0

20

µ

A/0.6mA

CET

Count Enable Trickle input

1.0/2.0

20

µ

A/1.2mA

CP

Clock input (active rising edge)

1.0/1.0

20

µ

A/0.6mA

PE

Parallel Enable input (active Low)

1.0/2.0

20

µ

A/1.2mA

MR

Asynchronous Master Reset input (active Low) for 74F161A

1.0/1.0

20

µ

A/0.6mA

SR

Synchronous Reset input (active Low) for 74F163A

1.0/1.0

20

µ

A/0.6mA

TC

Terminal count output

50/33

1.0mA/20mA

Q0 ­ Q3

Flip-flop outputs

50/33

1.0mA/20mA

NOTE:One (1.0) FAST unit load is defined as: 20

µ

A in the High state and 0.6mA in the Low state.

Philips Semiconductors

Product specification

74F161A, 74F163A

4-bit binary counters

1996 Jan 29

3

74F161A PIN CONFIGURATION

16

15

14

13

12

11

10

7

6

5

4

3

2

1

CEP

V

CC

Q2

Q3

CET

Q1

TC

Q0

MR

CP

D3

D0

D1

D2

9

8

GND

PE

SF00656

74F163A PIN CONFIGURATION

16

15

14

13

12

11

10

7

6

5

4

3

2

1

CEP

V

CC

Q2

Q3

CET

Q1

TC

Q0

SR

CP

D3

D0

D1

D2

9

8

GND

PE

SF00657

74F161A LOGIC SYMBOL

Q0

Q1

Q2

Q3

14

13

12

11

V

CC

= Pin 16

GND = Pin 8

9

7

10

2

PE

CEP

CET

CP

D1

D2

5

6

SF00658

D3

D0

3

4

1

MR

TC

15

74F163A LOGIC SYMBOL

Q0

Q1

Q2

Q3

14

13

12

11

V

CC

= Pin 16

GND = Pin 8

9

7

10

2

PE

CEP

CET

CP

D1

D2

5

6

SF00659

D3

D0

3

4

1

SR

TC

15

74F161A LOGIC SYMBOL (IEEE/IEC)

SF00660

3

1,2 D

1

9

M1

4

5

6

14

13

12

11

15

4 CT=15

7

G3

10

G4

2

C2 /1,3,4+

R

CTR DIV 16

74F163A LOGIC SYMBOL (IEEE/IEC)

SF00661

3

1,2 D

1

9

M1

4

5

6

14

13

12

11

15

4 CT=15

7

G3

10

G4

2

C2 /1,3,4+

2R

CTR DIV 16

Philips Semiconductors

Product specification

74F161A, 74F163A

4-bit binary counters

1996 Jan 29

4

STATE DIAGRAM

8

7

6

5

4

12

11

10

9

13

14

15

0

1

2

3

SF00664

APPLICATIONS

Q0 Q1 Q2 Q3

CLOCK

PE

CEP

CET

CP

D1

D2

SF00665

D3

D0

SR

TC

74F163A

+V

CC

Figure 1. Maximum count modifying scheme

Terminal count = 6

Q0 Q1 Q2 Q3

PE

CEP

CET

CP

D1

D2

SF00666

D3

D0

SR

TC

74F163A

Q0 Q1 Q2 Q3

PE

CEP

CET

CP

D1

D2 D3

D0

SR

TC

74F163A

Q0 Q1 Q2 Q3

PE

CEP

CET

CP

D1

D2 D3

D0

SR

TC

74F163A

Q0 Q1 Q2 Q3

PE

CEP

CET

CP

D1

D2 D3

D0

SR

TC

74F163A

Q0 Q1 Q2 Q3

PE

CEP

CET

CP

D1

D2 D3

D0

SR

TC

74F163A

CP

H H = Enable countorL L = Disable count

Figure 2. Synchronous multistage counting scheme

74F161A MODE SELECT ­ FUNCTION TABLE

INPUTS

OUTPUTS

OPERATING MODE

MR

CP

CEP

CET

PE

Dn

Qn

TC

OPERATING MODE

L

X

X

X

X

X

L

L

Reset (clear)

H

X

X

l

l

L

L

Parallel load

H

X

X

l

h

H

(1)

Parallel load

H

h

h

h

X

count

(1)

Count

H

X

l

X

h

X

q

n

(1)

Hold (do nothing)

H

X

X

l

h

X

q

n

L

Hold (do nothing)

Philips Semiconductors

Product specification

74F161A, 74F163A

4-bit binary counters

1996 Jan 29

5

74F163A MODE SELECT ­ FUNCTION TABLE

INPUTS

OUTPUTS

OPERATING MODE

SR

CP

CEP

CET

PE

Dn

Qn

TC

OPERATING MODE

l

X

X

X

X

L

L

Reset (clear)

h

X

X

l

l

L

L

Parallel load

h

X

X

l

h

H

(2)

Parallel load

h

h

h

h

X

count

(2)

Count

h

X

l

X

h

X

q

n

(2)

Hold (do nothing)

h

X

X

l

h

X

q

n

L

Hold (do nothing)

H

=

High voltage level

h

=

High voltage level one setup prior to the Low-to-High clock transition

L

=

Low voltage level

l

=

Low voltage level one setup prior to the Low-to-High clock transition

q

n

=

Lower case letters indicate the state of the referenced output prior to the Low-to-High clock transition

X

=

Don't care

=

Low-to-High clock transition

(1)

=

The TC output is High when CET is High and the counter is at Terminal Count (HHHH for 74F161A)

(2)

=

The TC output is High when CET is High and the counter is at Terminal Count (HHHH for 74F163A)