SAN JOSE, Calif. — (BUSINESS WIRE) — June 4, 2015 —
Atrenta Inc., the leading provider of SoC Realization solutions for the
semiconductor and consumer electronics industries, today announced that
it will present key new additions to its RTL Signoff platform at the 52nd
Design Automation Conference to be held June 7-11, 2015 at Moscone
Center in San Francisco, California. Atrenta’s RTL Signoff platform,
built on its industry leading SpyGlass®, BugScope® and
GenSys® tools, enables efficient verification and
optimization of SoCs early in the design cycle, thus minimizing time to
design closure and avoiding critical chip failures.

While SoCs are becoming bigger and more complex, the use of advanced
process nodes has made RTL Signoff a design imperative. At DAC, Atrenta
will showcase how its RTL Signoff platform has been expanded to address
these challenges. Some key highlights are:

SpyGlass Platform

Next generation, SpyGlass Turbo that is “Smarter, Faster, and Deeper”

IP
Signoff solution with a broader industry adoption and hooks for
SoC integration

“It was two years ago at DAC that we launched our RTL Signoff platform,
and the response from our 280+ customers has been overwhelmingly
positive,” said Piyush Sancheti, vice president of marketing at Atrenta.
“We have continued to expand the scope of our RTL platform to address
the next set of SoC challenges of scale, complexity, and advanced
process nodes. We look forward to sharing our progress with prospects,
customers, and partners at DAC.”

Atrenta's SpyGlass Predictive Analyzer® significantly
improves design efficiency for the world's leading semiconductor and
consumer electronics companies. Patented solutions provide early design
insight into the demanding performance, power and area requirements of
the complex system on chips (SoCs) fueling today's consumer electronics
revolution. More than two hundred eighty companies and thousands of
design engineers worldwide rely on SpyGlass to reduce risk and cost
before traditional EDA tools are deployed. With the addition of GenSys®
and BugScope®, RTL modification and verification efficiency
are also enhanced, allowing engineers and managers to find the fastest
and least expensive path to silicon for complex SoCs.