Here is the abstract you requested from the IMAPS_2013 technical program page. This is the original abstract submitted by the author. Any changes to the technical content of the final manuscript published by IMAPS or the presentation that is given during the event is done by the author, not IMAPS.

Both TSV technology and stacked die packaging have been gaining traction due to performance and manufacturing issues associated with transistor scaling. 3D die stacking architecture with through silicon vias offers a unique combination of low power and high bandwidth per watt without increasing the cost significantly. For Xilinx’s FPGAs (Field Programmable Gate Array), due to its repetitive and unique structures, Stacked Silicon Interconnect (SSI) technology becomes a perfect fit to provide a high performance solution to build large homogeneous logic devices with very high logic cell count as well as heterogeneous logic die integration [1].
For superior manufacturability and cost-effectiveness, the full manufacturing sequence requires seamless integration and optimization from TSV/BEOL metal stack in foundry wafer processing through mid-end/back-end processes in OSAT wafer/die processing. The entire flow must be optimized to deliver the greatest performance (yield, reliability) for the highest productivity (cost).
Both line yield and defect density control are two of the most closely guarded secrets in the manufacturing of SSIT technology. Several factors can cause considerable yield loss in foundry TSV and OSAT mid-end processes, factors that include the different definition of critical killer defect from existing fab/OSAT integration, glue residues/contamination at bevel and edge area due to plasma inhomogeneity towards wafer edge, wafer bow due to film stress, nonuniformities in etch profiles and post-CMP film thickness, and plasma- or handling-induced mechanical damage at thin wafer edge. Quite a few efforts have been made to enhance line yield in various aspects of particulate control, wafer-edge yield engineering, any process nonuniformities enhancement, surface treatment/modification, and so on. Critical processes were identified and countermeasures implemented to improve overall yield performance.
Another manufacturing challenge is the need for high yielding and high reliable micro-joining metallurgy and bonding technology. In copper pillar micro-bump structure, there is a limited amount of Sn and an unlimited Cu supply into the Cu pillar solders bumps. There are adverse effects of this on voiding and cracking symptom in joint for long term reliability. In addition to this, IMCs practically occupy a major volume fraction of the solder joint during the assembly process or after long term storage at high temperature [2,3]. Consequently, the mechanical properties of IMCs and other reaction-induced microstructure features play significant roles.
In order to solve this technical limitation, copper dosing process into solder (>0.2 wt% in solder) is invented to minimize the undesirable intermetallic reaction on both interface of top and bottom. This new copper dosing technology and reliability data are introduced.
In the current configuration, four separate 28nm FPGA slices were connected to each other through a 65nm passive TSV (through-silicon via) silicon interposer. Each 28nm FPGAs die having more than tens of thousands micro-bumps (ubumps) are stitched together through the silicon interposer to provide device-scale interconnect hierarchy. Due to both more than 200,000 microbumps and very large FPGA/Interposer die size, any particulate contamination or defect control has an ever increasing impact on micro-joining yields. One part of yield loss in micro-joining can be attributed to random defects. Random defects involve the contamination of fall-on particles, stubborn temporary glue, organics, and any other undesirable contaminants that result from mid-end and back-end processing in OSAT. The other main contributors to yield loss include design margin (bump coplanarity in isolated and dense area) and process variation (warpage and carrier glue).
To overcome these limitations and roadblocks, we have developed a proprietary Pseudo CoW approach based on CoC stacking using releasable self-adhesive layer, which is primarily to get interposer die warpage flat prior to FPGA stacking on it. Moreover, it also enables the wafer scale cleaning technology and AOI inspection for robust defect control and yield improvement.
In addition to discussing the manufacturability of the integration approach, the talk will also address the readiness of the established FA capabilities for 3D technology, since this is critical in ensuring process quality and reliability.
In this paper, technical challenges and solutions in the manufacturing of stack silicon interconnect (SSI) technology have been investigated with the established foundry and OSAT ecosystem.