Doug,
Well , you're correct that you have to know the effects of edgerate, length,
etc., and the other items you mentioned, and lets not forget changes in
driver source/sink current, dV/dt, dI/dt, trace via inductance and
capacitance, resistivity of the planes, inductance of the planes, intrinsic
capacitance of the planes, Zo modulation at dissimilar permittivity
junctions, single or dual stripline, broadside or vertical, asymmetrical or
symmetrical, mutual inductive coupling vs parallel length, mode changes at
the critical length, in phase noise vs out of phase noise effects on
risetime and period... the list goes on and on. That's why we use
simulators. If you are doing crosstalk calculations by hand for design
purposes you're already in trouble, you need to purchase a simulator. If
you want to get a quick estimate of crosstalk, that's another thing. This
is the quick estimate approach. I arrived at those values using the same
formula that everyone else is familiar with from the same familiar source,
Howard Johnson, Chapter 5, which assumes a Gaussian current density
distribution, which of course is a simplification. He didn't invent the
formula, he conceptually condensed it, and said that K = 1 is a good
approximation and an easy mnemonic. This made it easier to get the "big
picture", since most of the rest of the material on the subject is
significantly more math intensive, and it's easy to simply get lost in the
math. So, assume a homogeneous linear time invariant system shorter than
the critical length for the signal edge rate, stripline/microstrip/buried
microstrip topology, whichever you prefer since these geometric changes only
effect the value of K, and use the Gaussian approximation. Generate a table
of values by first keeping the trace width and the per cent allowed
crosstalk constant, varying only the power/ground separation distance.
Crunch the numbers for edge-to-edge separation and pitch. Then increase
your trace width by one mil, lather, rinse, repeat. Do as many of these
iterations as you are concerned with (number of trace width variations on
the PCB you're working on), or just go nuts and generate a large table of
everything from a 1 mil trace to a 10 mil trace with plane separation
distances from 1 to 10 mils. Observe the trending that occurs as the
parameters vary. This will give you a better understanding of geometry
effects. When you are at your next layout meeting you'll be better able to
spot potential cross talk problems on the fly.
Ken

Ken,
Your comments about crosstalk didn't mention the effects of the signal edge
rate, trace length or if you were using stripline ,microstrip, etc. The edge
rate will greatly effect the amount of crosstalk seen by the victim trace
for a given setup. Also, the crosstalk will reach a maximum value when the
round trip time (2*Tpd) is equal to the edge rate (Tr). I was looking at
your example regarding the 5 mil trace width, 5 mil plane separation with
100mV (assume peak-to-peak). What is the trace length and edge rates used in
the calculation? Also you didn't mention the board material, i.e. FR4 is
assumed. The amount of crosstalk decreases by a factor of 4 for each linear
increase in spacing. Can you provide more details on how you arrived at your
values?

Jeff,
I didn't see Doug's question, but in answer to yours, given the same plane
separation distance and allowable % crosstalk the wider the trace width the
closer (edge to edge) you can space the traces. Make yourself a chart of
trace width, plane separation (same permittivity of course), edge-to-edge
separation, and centerline-to-centerline (pitch). Group these parameters in
allowable % crosstalk, i.e., for a 3.3V system 100 mV is 3% crosstalk, and
change the trace width. Example: 5 mil traces, 5 mil plane separation, for
100 mV of crosstalk: edge-to-edge is 23 mils, pitch is 28 mils.
6 mil traces, 5 mil plane separation, 100 mV x-talk: edge-to-edge is 22
mils, pitch is 28 mils. The separation distance edge-to-edge decreases
linearly, a mil at a time in this example. Your CAD guys like to talk
pitch, so that's why I have the pitch column. Pitch varies with plane
separation given a constant trace width and allowable x-talk %. This way
you can design in the allowable level of x-talk.

Is there any reason to specify distance between traces relative to their
width? As far as I know, the most critical dimensions to consider are: 1)
distance between the edges of two traces, relative to 2) distance between
the trace and its ground plane(s). The width of the conductor is not a
significant factor, unless you're using center-to-center separation, where
you'll have to take into account the width. I don't understand why we
wouldn't specify S/H instead of D/W (see below).

Should both Aggressors be in-phase with each other or should one of them be
inverted to get the worst case crosstalk. I am simulating with both
applications and getting much more crosstalk on the victim trace when both
aggressors are in-phase.

The clock edge rate is 950pS and the trace width is set at w = 5 mils. The
Plane to trace layer spacing is 6.5 mils. This provides a nice 50 ohm trace
impedance.
The distance between traces is set at 5 mils (1w). I have been playing with
2w in the simulations as well.

Is it traditional to set the trace-to-trace spacing on the bus traces, i.e.
bits(0:x) for example, at 1w the trace width. The bus-to-adjacent traces
have been set for 2w spacing. The clock spacing is set for a 3w minimum.

Doug Hopperstad

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