CoreLink CCI-400 Cache Coherent Interconnect

Massive growth in system integration places on-chip communication at the center of system performance. The ARM® CoreLink™ CCI-400 Cache Coherent Interconnect provides full cache coherency between two clusters of multi-core CPUs, such as the ARM Cortex®-A7, Cortex-A15, Cortex-A17, Cortex-A57 and Cortex-A53 processors enabling big.LITTLE™; and I/O coherency for devices such as the Mali™-T600 series GPU, and I/O masters like modem and USB. To date ARM has licensed the CCI-400 product to over 20 licensees including Samsung, LSI, Freescale, HiSilicon, STEricsson, Fujitsu, Mediatek and LG.

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CoreLink CCI-400 Cache Coherent Interconnect

The CoreLink CCI-400 is a high performance, power efficient interconnect designed to interface between processors and the dynamic memory controller, such as the CoreLink DMC-400. It is the first product to implement AMBA® 4 ACE™, which brings system wide hardware coherency and virtual memory management.

What is hardware coherency?

Hardware coherency enables scaling and simplifies software. The latest SoC designs combine multiple processor and accelerator engines which all need to share data. These additional processors increase system performance and improve power efficiency, however this shared data needs to be managed to ensure everyone sees the same view of memory.

To manage shared data there are three techniques:

Disable caching: all shared memory is written externally to DDR. This is the simplest solution but expensive in high power external accesses and latency.

Software managed coherency: any data stored in processor caches must be cleaned and flushed to external memory before passing to accelerators and other hardware. This requires the CPU software to actively manage cached data, and requires CPU resources.

Hardware managed coherency: the system interconnect ensures all shared data is coherent in the system, reduces external memory accesses and removes the need for software to manage caches. This can offer improved performance and power efficiency as the CPU can do useful work or enter a lower power state.

Processor support and big.LITTLE

The CoreLink CCI-400 enables hardware managed coherency between two AMBA 4 ACE processor clusters such as the ARM Cortex-A7, Cortex-A15, Cortex-A17, Cortex-A57 Cortex-A53, and Cortex-A72 enabling big.LITTLE. Hardware coherency with CoreLink CCI-400 is an important part of ARM big.LITTLE processing and allows a single operating system to run across two processor clusters simultaneously. With big.LITTLE Global Task Scheduling (GTS) processes and applications can move dynamically between the high performance 'big' and the high efficiency 'LITTLE' cores as demand requires. This technology allows can allow up to 8 cores to run at the same time.

Hardware I/O Coherency and System MMU

I/O coherency, or one-way coherency, is provided for up to three accelerator engines implementing the AMBA 4 ACE-Lite™ protocol. This could include graphics processors such as ARM Mali™-T600 series, Mali-T760, Mali-T860, and Mali-T880 or interface controllers such as PCIe USB, Ethernet, and WiFi. The benefits of hardware coherency include simplification of software drivers, and lower latency access of shared data.

The CoreLink CCI-400 benefits are not limited to coherency, this product also supports the virtualization extensions including a direct connection to the system MMU, such as CoreLink MMU-400 or MMU-500, to allow virtualization of hardware devices. This can take advantage of multiple OS’s running on the same hardware, or simply a more efficient way to share limited physical memory.

High bandwidth, low latency CCI-400

The CoreLink CCI-400 cache coherent interconnect is targeted to run at up to half the frequency of the Cortex-A15 processor to allow high performance, low latency connection to main memory.

All interfaces support 128-bit wide data allowing for systems scaling to 10’s Gbyte/s data bandwidths to support high definition multimedia requirements and the latest high performance networking interfaces.

The CCI-400 design minimizes latency to ensure the maximum performance of latency-sensitive processors.

For smaller designs, the interconnect can be configured for lower bandwidth if required, and reduced latency can be offered for lower frequency targets. This configuration space allows SoC designers to tune for performance and area.

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