In regards to your BCK clock division, it appears that you are synronising BCK and DEM with 2.82Mhz instead of 1.48Mhz as in your previous design. Can you comment on the sound quality difference? Or is this soley to block jitter coming from the receiver chip?

I switched to 2.8224 MHz bit clock and 64 bits / frame for compatibility with popular DAC chips. This also means that the DEM circuit now runs on a 2.8224 MHz clock. Direct comparison between a SD-player with 1.4112 MHz bit / DEM clock and a SD-player with 2.8224 MHz bit / DEM clock revealed smoother sound and more refinement when using 2.8224 MHz bit / DEM clock.

In my humble opinion it's virtually impossible to fully block source jitter, regardless of jitter blocking method. Best way seems to be deriving critical clocks straight from the masterclock, and even this is already extremely critical.

Jitter amplitude at the D/A stage on the DAC chip must be lower than the calculated values I posted earlier, if not, resolution is lost (bits converted to noise).

Built a DAC using TDA1541 myself but want to build one of EC's astonishing designs, they must sound way better than my DAC.

Perceived sound quality is subjective. Not all listeners have the same preferences. So "way better" sound is also subject to listener's interpretation and preferences.

My objective is achieving best possible transparency and highest possible resolution from the popular 44.1/16 format.

Based on calculations and measurements on practical digital audio playback systems I realized that it is already extremely difficult to even approximate 16 bits resolution. Limiting factors appear to be sample timing jitter, speaker properties and resolution of power amplifier. With hi res formats, the extra bits are very likely to be turned into noise. This already starts to occur during A/D conversion in the studio. The increased sample rate / oversampling causes extreme jitter sensitivity (400 ... 800 attoseconds typical). This in turn makes it virtually impossible to approximate jitter compliance using currently available technology.

So I first attempt to get (almost) true 16 bit resolution before even thinking of tackling hi-res formats.

There are some new developments,

I am currently redesigning the MK7 DAC mains power supply. Target is reducing ripple voltage, best performing circuit so far is cascaded ripple suppressors. Each ripple suppressor is based on (Darlington) transistors. When using 2 cascaded suppressors, ripple reduction can be up to 500,000 times. With 200mVpp on the smoothing cap this could result in less than 400nVpp on the input of the discrete voltage regulator in the MK7 DAC, in practice this value would be higher of course (noise / EMI).

Idea is to keep discrete regulator feedback loop as stable as possible. The discrete voltage regulator further reduces ripple voltage by up to 500 times. This theoretically results in 40nV ripple on the regulator output. Grounding becomes extremely important at these low ripple voltage levels. Shifting the GND connection 1mm on the PCB can easily lead to 0.2mV increased ripple.

It is very important to use (local) star grounding scheme. GND of the connected load should run straight to this star ground. Connecting GND to a trace that runs to an electrolytic cap can greatly increase ripple voltage on the connected load. Similar, the load also has to be connected to a local star (plus or minus). It is also important to keep the ripple voltage symmetrical, otherwise unwanted higher harmonics are generated.

I also completed the 4-MOSFET MK2 Circlotron power amp (attached pictures). The MK2 Circlotron is mounted on a single PCB measuring 19 * 25cm. Connections with external terminals was kept as short as possible. Speakers are connected through thick copper strips that are directly connected to the PCB traces. I also made sure the power amp section (top right) was placed as close to in / outputs as possible. The new MK2 just fits in my standard housing.

This power amp is based on only 4 MOSFETs and some diodes (hybrid rectifier diodes and one 62V zener diode). All discrete voltage regulators could be removed. The differential input / driver stage runs on 60 ... 80V DC for increased headroom, larger output voltage swing and reduced distortion. The tail resistor for the differential pair could be increased from 200 Ohms to 2 K Ohms. Similar, the symmetry resistor value could be increased from approx. 7K to 56K, and the film cap value could be reduced from 6.6uF to 2.2uF. The symmetry circuit ensures equal gain when feeding a SE input signal to the differential stage.

The 60V DC power supply contains multiple common-mode filters and a zener diode embedded in these filters to offer a stable and quiet output voltage. The common-mode filter also reduces the effect of ground loops.

Each Circlotron section runs on a separate 24V DC power supply that also contains multiple common-mode filters. This also offers very quiet output voltage. Other advantage is that the ripple current on the reservoir caps stays below approx. 20mVpp @ 400mA bias current. This in turn means that capacitor properties have far less impact on sound quality as they are receiving a low ripple charge voltage. The effects of rectifier switching noise and resulting primary primary smoothing cap resonance effects are attenuated by the common-mode filter. The common mode filters also reduce the effects of ground loops.

Because of the chokes and 52,800uF smoothing caps, power can be delivered instantly, this makes the power amp extremely fast.

Bias setting now "tracks" the power supply, and a choke (with positive temperature coefficient) in series with the differential stage tail resistor offers ambient temperature compensation. This choke is screened. All other transformers and chokes are toroidal versions that offer low external magnetic field and are less sensitive to EMI.

The common mode filters resulted in darkest background so far. The chokes in the Circlotron stage result in very fast transient impulse response. Due to the quiet power supplies and only 4 MOSFETs in the signal path, resolution is much higher than with the Mk1 version.

Sounds like you are making yet more advances in achieving your desired goals.

Im interested in seeing the latest schematics of your Circlotron power amp if i may.

Are you now satisfied with your mk7 dac design?

I will be implementing your latest I2S reclock/attenuation circuit into an old cd player soon, hoping to hear some good results. This project will be my first attempt at etching a board and solding smd, should be fun!

Here is also a discussion on Voltage Regulators, In case it may help you with your own design.

I already read that thread, and many others discussing power supplies and voltage regulators. I also tried many different regulators and regulator concepts including CCS / shunt regulators, Super regulators, and many low noise IC regulators.

Bottom line is that regulators have (local) feedback loops that cause similar problems as in power amplifiers. So I am now using discrete voltage series regulators with few parts in the loop. I don't like shunt regulators as they waste a lot of energy and perform similar to more efficient series regulators. Problem with high power consumption is also that higher currents are required, these in turn cause higher interference (EMI) levels.

Main problem however is 50 ... 120 Hz ripple voltage. This ripple voltage must be attenuated approx. 500,000 times before the DC voltage can be fed to a voltage regulator. The ripple voltage would otherwise disrupt the already critical feedback loop 50 ... 120 times a second, allowing ripple voltage to seep through the regulator. Digital circuits appear to be extremely sensitive to low frequency ripple voltages on the power supply.

Other big problem is the GND path that feeds all (mains) interference straight into the circuit. Transformers have stray capacity between both primary and secondary windings up to a few nF, that easily pass RF interference. So the transformer basically forms a short circuit for RF between mains and connected circuit.

Mains interference (approx. 20Hz ... 50 KHz) is also directly transformed to the secondary that has relatively low impedance.

Mains powered equipment that is connected through GND will create (RF) ground loops between interconnected devices. The interference is added to the passing audio signal, causing significant degrading.

Since I needed ripple voltage reduction anyway, and one single capacitance multiplier cannot easily provide factor 500,000 ripple reduction, I put two of these capacitance multiplier circuits in series.

The best performing circuit (highest ripple rejection and lowest dropout voltage) consists of a Darlington transistor, a resistor and a capacitor.

By placing one capacitance multiplier in the pus rail and one in the minus rail, coupling both, a common-mode capacitance multiplier can be created that provides over 500,000 times ripple reduction and reduces ground loop issues. So typical 100mVpp input ripple is now reduced to approx. 200nVpp ripple before it is fed to the voltage regulator that further reduces this ripple into almost undetectable low levels (<2nVpp).