2 PICmicro MID-RANGE MCU FAMILY 8.1 Introduction PICmicro MCUs can have many sources of interrupt. These sources generally include one interrupt source for each peripheral module, though some modules may generate multiple interrupts (such as the USART module). The current interrupts are: INT Pin Interrupt (external interrupt) TMR0 Overflow Interrupt PORTB Change Interrupt (pins RB7:RB4) Comparator Change Interrupt Parallel Slave Port Interrupt USART Interrupts Receive Interrupt Transmit Interrupt A/D Conversion Complete Interrupt LCD Interrupt. Data EEPROM Write Complete Interrupt Timer1 Overflow Interrupt Timer2 Overflow Interrupt CCP Interrupt SSP Interrupt There is a minimum of one register used in the control and status of the interrupts. This register is: INTCON Additionally, if the device has peripheral interrupts, then it will have registers to enable the peripheral interrupts and registers to hold the interrupt flag s. Depending on the device, the registers are: PIE1 PIR1 PIE2 PIR2 We will generically refer to these registers as PIR and PIE. If future devices provide more interrupt sources, they will be supported by additional register pairs, such as PIR3 and PIE3. The Interrupt Control Register, INTCON, records individual flag s for core interrupt requests. It also has various individual enable s and the global interrupt enable. DS31008A-page Microchip Technology Inc.

3 Interrupts Section 8. Interrupts The Global Interrupt Enable, GIE (INTCON<7>), enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable s in the INTCON register. The GIE is cleared on reset. The return from interrupt instruction, RETFIE, exits the interrupt routine as well as sets the GIE, which allows any pending interrupt to execute. The INTCON register contains these interrupts: INT Pin Interrupt, the RB Port Change Interrupt, and the TMR0 Overflow Interrupt. The INTCON register also contains the Peripheral Interrupt Enable, PEIE. The PEIE will enable/disable the peripheral interrupts from vectoring when the PEIE is set/cleared. When an interrupt is responded to, the GIE is cleared to disable any further interrupt, the return address is pushed into the stack and the PC is loaded with 0004h. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag s. Generally the interrupt flag (s) must be cleared in software before re-enabling the global interrupt to avoid recursive interrupts. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag s. Individual interrupt flag s are set regardless of the status of their corresponding mask or the GIE. Note 1: Individual interrupt flag s are set regardless of the status of their corresponding mask or the GIE. Note 2: When an instruction that clears the GIE is executed, any interrupts that were pending for execution in the next cycle are ignored. The CPU will execute a NOP in the cycle immediately following the instruction which clears the GIE. The interrupts which were ignored are still pending to be serviced when the GIE is set again Microchip Technology Inc. DS31008A-page 8-3

6 PICmicro MID-RANGE MCU FAMILY PIE Register(s) Depending on the number of peripheral interrupt sources, there may be multiple Peripheral Interrupt Enable registers (PIE1, PIE2). These registers contain the individual enable s for the Peripheral interrupts. These registers will be generically referred to as PIE. If the device has a PIE register, The PEIE must be set to enable any of these peripheral interrupts. Note: Bit PEIE (INTCON<6>) must be set to enable any of the peripheral interrupts. Although, the PIE register s have a general location with each register, future devices may not have consistent placement. Bit location inconsistencies will not be a problem if you use the supplied Microchip Include files for the symbolic use of these s. This will allow the Assembler/Compiler to automatically take care of the placement of these s by specifying the correct register and name. DS31008A-page Microchip Technology Inc.

10 PICmicro MID-RANGE MCU FAMILY 8.3 Interrupt Latency Interrupt latency is defined as the time from the interrupt event (the interrupt flag gets set) to the time that the instruction at address 0004h starts execution (when that interrupt is enabled). For synchronous interrupts (typically internal), the latency is 3TCY. For asynchronous interrupts (typically external), such as the INT or Port RB Change Interrupt, the interrupt latency will be TCY (instruction cycles). The exact latency depends upon when the interrupt event occurs (Figure 8-2) in relation to the instruction cycle. The latency is the same for both one and two cycle instructions. 8.4 INT and External Interrupts The external interrupt on the INT pin is edge triggered: either rising if the INTEDG (OPTION<6>) is set, or falling, if the INTEDG is clear. When a valid edge appears on the INT pin, the INTF flag (INTCON<1>) is set. This interrupt can be enabled/disabled by setting/clearing the INTE enable (INTCON<4>). The INTF must be cleared in software in the interrupt service routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from SLEEP, if the INTE was set prior to going into SLEEP. The status of the GIE decides whether or not the processor branches to the interrupt vector following wake-up. See the Watchdog Timer and Sleep Mode section for details on SLEEP and for timing of wake-up from SLEEP through INT interrupt. Figure 8-2: INT Pin and Other External Interrupt Timing Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT INT pin 1 INTF flag (INTCON<1>) GIE (INTCON<7>) INSTRUCTION FLOW 3 PC Instruction fetched 4 Interrupt Latency 2 PC PC+1 PC h 0005h Inst (PC) 5 1 Inst (PC+1) Inst (0004h) Inst (0005h) Instruction executed Inst (PC-1) Inst (PC) Dummy Cycle Dummy Cycle Inst (0004h) Note 1: INTF flag is sampled here (every Q1). 2: Interrupt latency = 3-4 TCY where TCY = instruction cycle time. Latency is the same whether Instruction (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set anytime during the Q4-Q1 cycles. Note: Any interrupts caused by external signals (such as timers, capture, change on port) will have similar timing. DS31008A-page Microchip Technology Inc.

11 Section 8. Interrupts 8.5 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt e.g. W register and STATUS register. This has to be implemented in software. The action of saving information is commonly referred to as PUSHing, while the action of restoring the information before the return is commonly referred to as POPing. These (PUSH, POP) are not instruction mnemonics, but are conceptual actions. This action can be implemented by a sequence of instructions. For ease of code transportability, these code segments can be made into MACROs (see MPASM Assembler User s Guide for details on creating macros). Example 8-1 stores and restores the STATUS and W registers for devices with common RAM (such as the PIC16C77). The user register, W_TEMP, must be defined across all banks and must be defined at the same offset from the bank base address (i.e., W_TEMP is defined at 0x70-0x7F in Bank0). The user register, STATUS_TEMP, must be defined in Bank0, in this example STATUS_TEMP is also in Bank0. The steps of Example 8-1: 1. Stores the W register regardless of current bank. 2. Stores the STATUS register in Bank0. 3. Executes the Interrupt Service Routine (ISR) code. 4. Restores the STATUS (and bank select register). 5. Restores the W register. If additional locations need to be saved before executing the Interrupt Service Routine (ISR) code, they should be saved after the STATUS register is saved (step 2), and restored before the STATUS register is restored (step 4). 8 Example 8-1: Saving the STATUS and W Registers in RAM (for Devices with Common RAM) MOVWF W_TEMP ; Copy W to a Temporary Register ; regardless of current bank SWAPF STATUS,W ; Swap STATUS nibbles and place ; into W register MOVWF STATUS_TEMP ; Save STATUS to a Temporary register ; in Bank0 : : (Interrupt Service Routine (ISR) ) : SWAPF STATUS_TEMP,W ; Swap original STATUS register value ; into W (restores original bank) MOVWF STATUS ; Restore STATUS register from ; W register SWAPF W_TEMP,F ; Swap W_Temp nibbles and return ; value to W_Temp SWAPF W_TEMP,W ; Swap W_Temp to W to restore original ; W value without affecting STATUS Interrupts 1997 Microchip Technology Inc. DS31008A-page 8-11

12 PICmicro MID-RANGE MCU FAMILY Example 8-2 stores and restores the STATUS and W registers for devices without common RAM (such as the PIC16C74A). The user register, W_TEMP, must be defined across all banks and must be defined at the same offset from the bank base address (i.e., W_TEMP is defined at 0x70-0x7F in Bank0). The user register, STATUS_TEMP, must be defined in Bank0. Within the 70h - 7Fh range (Bank0), wherever W_TEMP is expected the corresponding locations in the other banks should be dedicated for the possible saving of the W register. The steps of Example 8-2: 1. Stores the W register regardless of current bank. 2. Stores the STATUS register in Bank0. 3. Executes the Interrupt Service Routine (ISR) code. 4. Restores the STATUS (and bank select register). 5. Restores the W register. If additional locations need to be saved before executing the Interrupt Service Routine (ISR) code, they should be saved after the STATUS register is saved (step 2), and restored before the STATUS register is restored (step 4). Example 8-2: Saving the STATUS and W Registers in RAM (for Devices without Common RAM) MOVWF W_TEMP ; Copy W to a Temporary Register ; regardless of current bank SWAPF STATUS,W ; Swap STATUS nibbles and place ; into W register BCF STATUS,RP0 ; Change to Bank0 regardless of ; current bank MOVWF STATUS_TEMP ; Save STATUS to a Temporary register ; in Bank0 : : (Interrupt Service Routine (ISR) ) : SWAPF STATUS_TEMP,W ; Swap original STATUS register value ; into W (restores original bank) MOVWF STATUS ; Restore STATUS register from ; W register SWAPF W_TEMP,F ; Swap W_Temp nibbles and return ; value to W_Temp SWAPF W_TEMP,W ; Swap W_Temp to W to restore original ; W value without affecting STATUS DS31008A-page Microchip Technology Inc.

16 PICmicro MID-RANGE MCU FAMILY 8.7 Design Tips Question 1: An algorithm does not give the correct results. Answer 1: Assuming that the algorithm is correct and that interrupts are enabled during the algorithm, ensure that are registers that are used by the algorithm and by the interrupt service routine are saved and restored. If not some registers may be corrupted by the execution of the ISR. Question 2: My system seems to lock up. Answer 2: If interrupts are being used, ensure that the interrupt flag is cleared after servicing that interrupt (but before executing the RETFIE instruction). If the interrupt flag remains set when the RETFIE instruction is executed, program execution immediately returns to the interrupt vector, since there is an outstanding enabled interrupt. DS31008A-page Microchip Technology Inc.

17 Interrupts Section 8. Interrupts 8.8 Related Application Notes This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the Mid-Range MCU family (that is they may be written for the Base-Line, or High-End families), but the concepts are pertinent, and could be used (with modification and possible limitations). The current application notes related to this section are: Title Application Note # Using the PortB Interrupt On Change as an External Interrupt AN Microchip Technology Inc. DS31008A-page 8-17

18 PICmicro MID-RANGE MCU FAMILY 8.9 Revision History Revision A This is the initial released revision of the interrupt description. DS31008A-page Microchip Technology Inc.

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