IBM discloses combo strained-silicon/SOI technology

EAST FISHKILL, N.Y.--IBM Corp.'s Microelectronics Division next week is expected to announce a radical and combination strained-silicon/silicon-on-insulator (SOI) technology for use in making high-performance chips at the 65-nm (0.065-micron) node.

IBM has already fabricated an SRAM, based on the "strained-silicon-on-SOI" technology in the lab, but commercial chip products are not due out until the 65-nm node in the 2005 time frame, according to officials from the East Fishkill-based organization.

Initially, the company plans to develop and make high-performance microprocessors, build around the combination strained-silicon/SOI process.

Based on an epitaxial process, IBM's technology combines the inherent advantages of both strained-silicon and SOI. SOI enables lower capacitance in IC designs, while strained silicon provides higher chip frequencies.

Chips based on the combination process offers 20% more performance, as compared to devices with standalone SOI technology, said Byoung Lee, manager of CMOS process integration at IBM Microelectronics. Lee is the lead author of a paper on the subject, which will be will be presented at the International Electron Devices Meeting (IEDM) in San Francisco from Dec. 9-11.

IBM's announcement follows a similar disclosure by AmberWave Systems Corp. In October, the Salem, N.H.-based company claims to have developed a strained-silicon on SOI process. AmberWave also develops a standalone strained-silicon process, of which it licenses to chip makers (see Oct. 16 story ).

IBM--which claims to be taking a different approach to that of AmberWave--appears to be developing a "silicon-germanium-on-SOI" technology. Using IBM's approach, the first layer of the chip would be silicon foundation, followed by a layer of silicon dioxide, silicon-germanium, and then strained-silicon.

Others are also jumping on the strained-silicon bandwagon as well. Recently, for example, Intel Corp. announced plans to develop a strained-silicon technology at the 90-nm node. Intel is also developing SiGe transistors for that node as well, it was noted.

IBM, which is already offering SOI and SiGe, will not have strained-silicon until the 65-nm node. At that time, IBM's process will consist of the combination strained-silicon/SOI process.

The company still claims it is still ahead of Intel in the process technology race. "Intel is developing strained-silicon on bulk at 90-nm," Lee said. "We don't see the need to have strained-silicon at 90-nm, because SOI intrinsically has better performance than strained-silicon at 90-nm," he said.

The IBM technologist was referring to the company's SOI technology, which is being used with its existing high-end processors at the 130-nm node, and most likely, at 90-nm.