GlobalFoundries fabs 20-nm test chip

SAN JOSE, Calif. Ė GlobalFoundries taped out a 20nm test chip using design tools from Cadence Design Systems, Magma Design Automation, Mentor Graphics and Synopsys. The test used double patterning and was implemented with each EDA partner contributing a large placed and routed design.

"Test chip" seems to have a different meaning for every company. 1 company may describe Test Chip as a mask field full of test structures, while another could call a SOC w/ SRAM, logic, etc their "Test Chip". The article doesn't clarify the details of this announcement, I think people are making their own implications which may or may not be accurate.

@Sanjib.Acharya: the chip does what you want it to do! Test chips are one way to validate a given higher technology node but that is 1/4 of the story. Real design with memory / logic / FPGA will of a myriad of problems that a developer of an ASIC will have to hand-hold with GloFo. I am not discounting the packaging challenges either with 20nm process.
Tabula has already demonstrated 22nm FPGA so this news release is no way getting the attention or hype if at all intended!
Dr. MP Divakar

Running test chip now while TSMC and Samsung is already running SOC test chip in 20nm?? Is GF still having an execution issues on 40nm/28nm? Are there any announced takers for gate-first 28nm technology from GF? I understand that there are some from Samsung side but have not heard any from gf side.