Technically Speaking, Inc

Designing FPGAs Using the Vivado Design Suite 3 | Orange County, CA

This course demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, and optimum HDL coding techniques that help with design timing closure. This course also shows you how to debug your design using advanced capabilities of the Vivado® logic analyzer.

Course Outline

Day 1

UltraFast Design Methodology Introduction {Lecture, Demo}

Timing Simulation {Lecture, Lab}

Vivado Design Suite Non-Project Mode {Lecture}

Revision Control Systems in the Vivado Design Suite {Lecture, Lab}

Baselining {Lecture, Lab, Demo}

Pipelining {Lecture, Lab}

Inference {Lecture, Lab}

Synchronization Circuits {Lecture, Demo}

Day 2

Report Datasheet {Lecture, Demo}

Report Clock Interaction {Lecture, Demo}

Configuration Modes {Lecture}

Dynamic Power Estimation Using Vivado Report Power {Lecture, Lab}

Debug Flow in an IP Integrator Block Design {Lecture, Lab}

Remote Debugging Using the Vivado Logic Analyzer {Lecture, Lab}

JTAG to AXI Master Core {Lecture, Demo}

Trigger Using the Trigger State Machine in the Vivado Logic Analyzer {Lecture, Lab}