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Abstract

The figure illustrates a circuit which extends a voltage range of a variable gain amplifier (VGA) by linear control input to a log output which is applied to an analog multiplier. When analog circuits are used as a variable gain control of a VGA, the control voltage range is small and This makes it difficult to use in many The described method addresses this problem linearizes the overall gain-control voltage response of VGA, extending its control voltage range.

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United States

Language

English (United States)

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This is the abbreviated version, containing approximately
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LOG CONVERTER Circuit for GAIN Amplifier Designs

The figure
illustrates a circuit which extends a voltage
range of a variable gain amplifier (VGA) by linear control input to a
log output which is applied to an analog multiplier. When analog
circuits are used as a variable gain control of a VGA, the control
voltage range is small and This makes it
difficult to use in many
The described method addresses this problem linearizes the overall
gain-control voltage response of VGA, extending its control voltage
range.

A log
converter circuit is shown in the figure.
This provides
a linear-to-log conversion function for VGA voltages. The input to
the log converter is called The outputs
are VGAREF and VGALOG which
drive the The log converter does not
provide a true conversion since
the diode characteristics are truly exponential unless bias currents
always remain a microamp. However, this
converter does extend the
voltage range of the VGA several hundred millivolts a closely linear
fashion.

An input to
an analog multiplier circuit used in a VGA applied
to the bases of a differential pair placed a collector resistor and a
collector of one side of differential amplifier. This differential
pair functions a current switch which steers a fraction of the signal
into or away from the collector resistor as an function of its
control voltages. Outputs of log
converter VGAREF and VGALOG drive
the control base inputs of the current switch.

The converter
comprises three sections: a unity gain a
differential transconductance stage with one biased by a (VREF -
.5*Vbe) reference, and a transconductance stage with one side biased
by (VREF + .5*Vbe) reference.

The unity
gain amplifier input is at the base of Q5. current
sources are Q1,R3 and Q2,R4. The high
gain node an on-chip capacitor
C1. The emitter follower output of
drives a negative input at the
base of Q6 to close the An input bias
current cancellation circuit
is used to for the base current drawn by Q5 from the gain This is
necessary since GAIN is often held at a by a capacitor. This
compensation circuit reduces "droop" on this capacitor during a HOLD
state, improving HOLD time. The current
source Q4,R6 of this circuit
each of the current sources Q1,R3 and Q2,R4.
With amplifier at unity
gain, the base current of Q8 equals base current of Q5. The base
current of Q9, less than of Q8 by (B/(B+1)), is mirrored by Q13 back
to the GAIN to complete the inpu...