Author: taigonsong

So, I decided to have a post here to answer some questions that people can have.

Basic Concept

Designing a 3D IC can mean various things. For someone, it can be designing analog circuits, and it maybe designing digital or high-frequency (RF) circuits. Whatever it is, normally what you need is a firm netlist of the design that you wish to perform. It could be either

Verilog (.v or .vhdl)

SPICE (.sp or any relevant type)

or any type that describe the hardware of your design.

With the netlist you have, you need to somehow cut your design into two, three, or more (based on your 3D design: 2-tier?…3-tier? or more?…). We call this ‘partitioning’. Once the partitioning is done, it would be all about using the tools you are familiar to design your circuit. Of course, many significant details are not described how to partition or how to design your partitioned circuits, but this is the very basic concept you need to understand.

Design Tools

If someone knows the complexity that a typical design has, he (or she) would definitely know that proper tools are needed to design these 3D ICs. For example, if we are performing a digital design, we would need a tool that could “Synthesize” the RTL (registor-transistor-level schematic) into gated netlist. Also, we need a “Partitioner” that could partition the design into two, three, or more dies. Finally, once the netlist is partitioned, the design would need to be placed and routed. There are many companies that provide tools to do this (e.g., Cadence, Synopsys, Mentor Graphics).

Synthesis

RTL compiler (Cadence)

Design compiler (Synopsys)

Real-time designer (Mentor Graphics)

Place and Route

Encounter (Cadence)

IC compiler (Synopsys)

Calibre In-route (Mentor Graphics)

However, partitioning is a step that just using commercial tools would not help. If we want to make a 3D design, we need to decide locations for TSVs or any face-to-face connections that we want to make. Some companies have tools to do this, but it has not been released to public. For my case, I use an in-house tool that has been developed from our group.

Analysis Tools

Once the design is done, a designer must do various analysis. Starting from timing analysis (delay), power analysis, and reliability analysis, many kinds of analysis must be performed to check whether the design is done correctly. Since there are many different analysis tools that can do the work for this, i’ll skip the listing.

Noise coupling in 3D IC

Noise coupling (or crosstalk) in 3D ICs is one of the biggest reliability issues in 3D ICs. In ICs, two adjacent metal wires form a parallel capacitor, and this capacitive coupling is the source of the noise between the two wires. In 3D ICs, in addition to this wire coupling, two adjacent TSVs have a coupling network between them due to the silicon substrate and silicon dioxide insulator. This TSV-to-TSV coupling could be very problematic in 3D ICs, because TSVs are big and tall so that the coupling between two adjacent TSVs is huge. In addition, these TSVs are connected to metal wires, so the total coupling of two signal paths cause serious crosstalk problems in 3D ICs.

What is TSV (through-silicon via) ?

TSV is a thick, tall metal that penetrates through the silicon substrate. This technology actually stemmed in the early 90’s. However, due to the expensive fabrication cost, this was a technology that was sleeping for a long time.

TSV in DRAM

As seen in the figure, Note that TSV on the left is significantly big comparing to other components such as metal wires (BEOL) and Trench Cap on the device layer. The importance of this is that now we have a way to provide a direct path to the outer I/Os in both directions (chip surface and chip bottom). Without this TSV technology, chip surface was the only connection that we can make to the outer world.

How significant is the coupling?

Let’s think about two things: (1) Coupling capacitance that forms between TSVs and (2) The noise voltage it causes. Unlike the common belief that only the nearest aggressors impact TSV coupling, TSV coupling occurs even between the non-neighbor aggressors. This is because the far aggressor also has a significant amount of capacitance between the victim (close aggressor: 9.46fF, far aggressor: 4.14fF). Though the close aggressor shields the E-field between the victim and the far aggressor, it cannot be perfect. A strong E-field detours the first aggressor and forms capacitance between the far aggressor and the victim.

Coupling occuring between TSVs

We can see that the far aggressor affects as much coupling voltage (139.6mV) as the close aggressor (184.6mV) Despite the far aggressor has less than 50\% capacitance of the close aggressor, the noise voltage reduces by only 40mV. This is because of the complicated coupling network that TSVs compose.

Do we see commercial 3D ICs?

samsung_64gb_DRAM

For many years, it was actually a myth that commercial products will be designed using 3D IC technology. However, this now does not appear to be a myth anymore. Recently, Samsung announced that their 3D DDR4 DRAM memory modules will be produced using TSV (through-silicon via) technology. Until now (and currently), memories such as DRAM was designed in planar 2D style, meaning that all DRAM circuitry is inside just one die. However, Samsung has announced its first 3D IC DRAM product recently.

DRAM (dynamic random access memory) is a type of memory that goes inside our electronic systems. For example, in all our cell phones and smartphones, DRAMs are inside there in variety of sizes. Not talking about too much in technical detail, 3D-designed DRAM can run faster in lower power, so why not use them? However, since fabricating 3D IC is something totally new for companies like Intel or Samsung, I believe this is why it took longer than expected to have 3D IC in commercial product. Actually, I heard rumor from various sources that there has been some game going on inside the industries of who will commercialize their 3D ICs first because of the risk that they should take.

However, since we at least know Samsung is working on this, let’s expect for more.

3D-MAPS (3D MAssively Parallel processor with Stacked memory) V1 is a logic+memory 2-tier 3D IC, where the logic die consists of 64 general purpose processor cores running at 277MHz, and the memory die contains 256KB SRAM. This 3D IC is arguably the FIRST many-core general purpose 3D processor developed in academia. Funded by the Us Department of Defense, this was a project that was being held when I first joined the lab. Having many collaborators such as KAIST, Tezzaron, Amkor Inc, and Board Lab, Our group could successfully tape out this first 3D IC.