UltraFastDesignMethodology

Course Description

This course describes the FPGA design best practices and skills to be successful using the Vivado® Design Suite. This includes the necessary skills to improve design speed and reliability, including: system reset design, synchronization circuits, optimum HDL coding techniques, and timing closure techniques using the Vivado software. This course encapsulates this information with an UltraFast™ design methodology case study. The UltraFast design methodology checklist is also introduced.

Level

FPGA 3

Training Duration

1 Day

Who should attend

Engineers who seek training for FPGA design best practices that increase design performance and increase development productivity.

Prerequisites

Some knowledge of FPGA design techniques is helpful

Experience with the Vivado Design Suite or attendance of one of our existing Vivado Design Suite training courses is required

Intermediate knowledge of Verilog or VHDL

Software Tools

Vivado Design or System Edition 2016.1

Hardware

Architecture: UltraScale™ and 7 series FPGAs**Demo board: None*

Skills Gained

After completing this comprehensive training, you will have the necessary skills to: