"We are very excited to welcome Pranav back to the Real Intent family,"
commented Prakash Narain, CEO of Real Intent. "As we are increasing our
product offerings by creating innovative solutions to address customer
design challenges, Pranav's expertise in formal technology and his vision
will lead us into the future."

"I am extremely pleased to be a part of the Real Intent team again," stated
Pranav Ashar. "As its numerous customers will testify, Real Intent has
clearly demonstrated that the judicious application of formal methods in
VLSI design measurably improves designer productivity and lowers design
time. With at least five more technology-shrink generations and much
greater system-level complexity on a chip on the anvil, I look forward to
working with Real Intent to develop new technologies to improve designer
productivity and mitigate design risk."

About Pranav Ashar

Dr. Pranav Ashar brings two decades of EDA expertise to Real Intent. Pranav
received his M.S. and Ph.D. in EECS with emphasis on EDA from the
University of California, Berkeley in 1989 and 1991, respectively. He then
joined NEC Labs in Princeton, NJ where he developed a number of EDA
technologies that have influenced the industry. One of his important
accomplishments there was in raising the prominence of formal methods in
VLSI design through the creation of a very successful Verification
Department and the development and widespread deployment in EDA tools of
practical methods for formal verification. Through his leadership, the
department also parlayed its formal methods expertise into practical
methods for formal analysis in software engineering that have been deployed
in the field. Pranav also created a successful department at NEC Labs for
the application of automata and machine learning methods in the management
of large-scale distributed systems. Pranav previously served as CTO at Real
Intent from 2004 through 2006. In the interim, he served as CTO at a
mobile-phone security company called NetFortis that he co-founded for which
he developed low-energy
high-performance algorithms for malware detection, and Chief Scientist at a
simulation acceleration company called Liga Systems that was based on
technology developed by him at NEC Labs for custom-VLIW based parallel
simulation that was recently able to demonstrate a reduction in simulation
time from 21 days to about 1 day on a 25 Million gate design. Pranav has
authored about 70 publications in refereed conferences and journals with
approximately 800 citations, and co-authored a book titled "Sequential
Logic Synthesis." He has 35 patents granted and pending, many of which have
been licensed or part of business enablement. Pranav has been on committees
of ICCD, ICCAD and IWLS. He was ICCD Program Chair in 2004 and 2005, and
ICCD General Chair in 2006. Pranav is an adjunct faculty in the CSEE
department at Columbia University where he has taught graduate and
undergraduate courses on VLSI design automation, VLSI Verification, and
VLSI design. Pranav has also taught a graduate course on Switching Theory
in the EE department at Princeton University.