The DesignWare® STAR Hierarchical System leverages IP- and core-level test to efficiently test the entire SoC, enabling engineering teams to cut their test integration time to a matter of days and bring their designs to market faster and with lower design and test costs.

DFTMAX UltraAs SoCs increase in size and complexity, higher compression levels are required to maintain low test costs and achieve higher test quality, even as fewer pins are being allocated for test. DFTMAX Ultra addresses these challenges with new technology that is built into Synopsys' Design Compiler RTL synthesis: