A little more than six months ago we wrote an editorial
about Intel's future technology after Core 2 Duo, titled "Life After Conroe."
Life after Conroe inches closer, but, in the meantime, more details on the
architecture are available today.

DailyTech had the opportunity to chat with Mark Bohr, Intel Senior Fellow, and
Steve Smith, Intel Vice President DEG Group Operations, about the
upcoming CPU design.

The primary focus of Intel's next-generation process technology is
Penryn. Penryn is the specific codename a 45nm mobile shrink of the Conroe core,
but the codename may also be used to describe the entire product family.
Early last year Intel announced it would optically shrink to the next process
node every two years. Staggered one year later, the company would also
announce a new microarchitecture. This philosophy of shrink followed by
architecture revision will undergo its first real milestone with the node
shrink from 65nm to 45nm Penryn. One year after the 45nm Penryn
shrink, Intel is also expected to announce its next-generation
microarchitecture successor, Nehalem.

Intel claims the upcoming Penryn will fit 410 million transistors for the
dual-core model, and 820 million transistors for the quad-core variants -- dual-core Conroe utilizes just 298 million transistors.
Intel's 45nm SRAM shuttle chip, announced last year, had a little over 1 billion
transistors and fit on a 119mm^2 package. However, the initial Penryn
quad-core processors will use a multi-die packaging, so it's realistic to expect only 410 million transistors per die at launch.

The optical shrink allows the engineers to boost clock speed, but the
additional real estate means the company can put more logic on the processor as
well. "Most of that transistor savings is spent on increasing the cache
over Core 2" added Smith.

Penryn is still not without its mysteries; a primary concern for enthusiasts is
motherboard and socket support. Penryn will launch on Socket 775 -- meaning
existing motherboards can physically harbor the new CPU, but electrically might
not. "Motherboard developers will have to make some minor changes to
support [Penryn]. We can't guarantee that a person could just plug the
chip into every motherboard on the market today." However, Smith
also claimed the Penryn
boot test that grabbed so many headlines last week occurred on unmodified
hardware that included a notebook, several desktop motherboards and several
server motherboards.

The lithography process for Penryn, dubbed P1266, is not just a shrink from
65nm to 45nm. Perhaps the most significant advance on P1266 is the use of
high-k dielectrics and metal gate transistors. In a nutshell, the
polysilicon gate used on transistors today is replaced with a metal layer and
the silicon dioxide dielectric that sits between the substrate and the
transistor is replaced by a high-k dielectric.

Intel's push for high-k dielectrics and metal gate transistors may be more
significant than the node shrink. Intel's guidance documentation claims
with the new high-k dielectric, metal gate transistors offer a 20% increase in
current, which can translate to a 20% increase in performance. When the
new transistor technologies run at the same current and frequencies as Core 2
Duo processors today, translates to a 5-fold reduction in source-drain leakage
and a 10-fold reduction in dielectric leakage.

"The implementation of high-k and metal gate materials marks the biggest
change in transistor technology since the introduction of polysilicongate MOS
transistors in the late 1960s" claims Gordon Moore, Intel co-founder
attributed with coining "Moore's Law."

Intel would not reveal the materials used in its metal gate technology, though
Smith announced that the dielectric is hafnium based. Hafnium dioxide has
been the leading candidate to replace silicon oxide inside academia for
years. A different material is used for PMOS and NMOS gates.

Intel's lithography roadmap no longer ends at P1268, the 32nm node.
Earlier today Intel revealed its 22nm node, dubbed 1270, slated for first
production in 2011.

Smith closed our conversation with "In 2008, we'll have Nehalem."

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quote: Silly silly silly, have you taken an undergraduate device physics course and understand KT/Q? Vt can't be lowered anymore at room temperature without excessive leakage as you will lower the barrier between source and drain. Anything much lower then 400mV and you can't turn the transistors off. Thus you can't just reduced the drain voltage as Vdd-Vt won't be enough to dry that lowK backend.

Thus to get good drive current and minimum leakage you need Vdd about 1 volt or so. Any lower and you get really low performing transistors. Of course in sleep/slow mode you can do all you want reduce Vdd but then you have this thing called SRAM stability to deal with.

High K / Metal gate is as close to having your cake and eating it to!

you and I are talking about differnt voltages because I agree with the Vth statement and sleep mode.

I am talking about after the conducting channel is formed under the gate, the source and drain nodes should not have to be at a voltage level which results in significant tunneling current.

There are probably lots of ways that graduate students and professors dream up in an academic setting that are absolutely worthless for practical applications, sure.

As to actual designs, uhhhh, there aren't all -that- many transistors that are just sitting around not driving anything. (Yes, there are some put in for making logic corrections after base tapeout.) But for actual active logic transistors, how would you propose reducing both gate and channel leakage? Changing gate to channel voltage is going to adversely affect the output voltage, which results in greatly reduced drive current and hence speed of the following logic.

Ayup, and considering that Vd is typically Vg for whatever logic comes next, well, it becomes difficult to do much. There is -always- going to be a Vdd to Vss voltage differential across a gate in typical CMOS logic that's in an active state (not sleep tranistor'd off.)

Lowering the Vdd to Vss voltage is a favored way to decrease leakage, but has adverse performance characteristics. A process change to a different gate dielectric is the only practical way to reduce gate leakage without sacrificing performance. There has been a -lot- of work put into this process change, Intel has taken their time (about three years) since first lab success to get everything right.

The process is not without compromise itself, not everything is "right". The interface with the silicon is still key, and is effectively still native oxide.

If the leakage by itself were so significant, power reduction should be much more aggressive, but it's about par. 5-10X but power is about even, assuming doubling transistors, it still appears limited.

Not to say it is not a great thing. It's a good change, and impressive work. What is the next step now? High-k thickness doesn't scale like SiO2, since there is an unscalable interface layer with silicon. They must be working on next-generation gate dielectric. Follow the DRAM makers.

Hrmmmm? Interface with the silicon is still native oxide? Even if they're using a halfnium oxide dielectric rather than halfnium silicate, there wouldn't be any interface layer of native oxide. Gate dielectric deposition is a -very- well controlled process.

Sure, leakage isn't as much of a problem at 65nm as it was at 90nm, primarily due to smarter design (halt states, sleep transistors.) But 65nm was never anticipated to be a problem node for leakage, the geometries weren't that bad yet. Reducing leakage at 45nm rather than increasing is great, that 5-10X means reduction of idle power from the ~22W current down to 2-4W. And 30% decrease in gate switching power brings, say, 53W (just a guesstimate based off 75W total for 3GHz core 2 duo) down to 37W. So, now your 75W CPU becomes around 40W.

Believe there was an eetimes article a bit back that quoted one of the senior process engineers at Intel stating second gen high-k gate dielectric was in the works, probably for the 32nm node.

SiO2 buffer layer, really? Think thru what you said. Today we can't support a thinner electrical thickness and control leakage. Now you tell me you need a layer of Oxide then add some thicker HiK and get a thinner electrical oxide then a nitrided oxide... Sorry is that HiK have negative effecitive oxide thickness? If you add a buffer of oxide then you negate all the benifits of having HiK helping your eletrical TOX.

quote: SiO2 buffer layer, really? Think thru what you said. Today we can't support a thinner electrical thickness and control leakage. Now you tell me you need a layer of Oxide then add some thicker HiK and get a thinner electrical oxide then a nitrided oxide... Sorry is that HiK have negative effecitive oxide thickness? If you add a buffer of oxide then you negate all the benifits of having HiK helping your eletrical TOX.

It's not that bad, there is some headroom.

The formula used is tsio2/ksio2+thfsio/khfsio+thfo2/khfo2=t(total)/keff . So the first two terms can be made as small as possible for higher keff. khfo2~25,khfsio~16,ksio2~4 roughly (varies in literature).

It's true that you don't get the SiO during gate dielectric deposition. It occurs during annealing. The degree of this oxidation is controllable to some extent (enough for many groups' satisfaction).

I'm not involved in the process engineering, so I don't know exactly what method Intel's high-k process is using. Seeing as how it's a trade secret, I doubt anyone who does would post it. That said, what does the interface between dielectric and silicon have to do with electron mobility through the channel area? Part of the desirability of halfnium in my understanding was that it interfaced so nicely with silicon, the problem was always on the gate electrode.

Extended halt power for core 2 duo is 22/12W (available in Intel's datasheet.) Believe the 12W figure is for the 2MB. Either way, yes, gate leakage can be more of an issue when not in standby, depends upon the design.

Anyway, all those figures are based upon the current conroe at 3GHz. And even if you increase the figure by the amount of core logic increase going into wolfdale, you still only get 50W. Either way, at this point it's all just speculation anyway. Intel's current figures are just based on simulations since silicon isn't at speed. So even if that was an actual roadmap, Intel wouldn't have lowered TDP on it in the least.

quote: Extended halt power for core 2 duo is 22/12W (available in Intel's datasheet.) Believe the 12W figure is for the 2MB. Either way, yes, gate leakage can be more of an issue when not in standby, depends upon the design.

Anyway, all those figures are based upon the current conroe at 3GHz. And even if you increase the figure by the amount of core logic increase going into wolfdale, you still only get 50W. Either way, at this point it's all just speculation anyway. Intel's current figures are just based on simulations since silicon isn't at speed. So even if that was an actual roadmap, Intel wouldn't have lowered TDP on it in the least.

Okay, I see. The clock speeds are going up again. Maybe performance per watt is more important to Intel. And in a laptop, even with a lower wattage CPU, the battery life is still killed by other non-optimized factors anyway (wireless, display).

quote: I'm not involved in the process engineering, so I don't know exactly what method Intel's high-k process is using. Seeing as how it's a trade secret, I doubt anyone who does would post it. That said, what does the interface between dielectric and silicon have to do with electron mobility through the channel area? Part of the desirability of halfnium in my understanding was that it interfaced so nicely with silicon, the problem was always on the gate electrode.

I don't claim to know the Intel or IBM process, I am only familiar with the research work that has gone into it. When using the high-k, a great deal of effort is put into reducing traps and defects which limit the electron (or hole) mobility by unwanted scattering. A SiO interface helps mainly by separating Si from these defects, but obviously the tradeoff is this interface should be as thin as possible to avoid increasing the EOT.

Ahhhh, makes a bit more sense now. I guess that if Intel is using a halfnium oxide, then the lattice that'd be formed would technically be, for one layer, both silicon oxide and halfnium oxide, haha. I'd guess past that point though it'd just be a halfnium oxide, since that's going to take care of all the boundary effects right there.

It'll be interesting to see exactly what's being done once it's in production and they can actually put out more information.

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