OVP Fast Processor Model is written in C. Provides a C API for use in C based platforms. Provides a native C++ interface for use in SystemC TLM2 platforms.

The model is written using the OVP VMI API that provides a Virtual Machine Interface that defines the behavior of the processor.The VMI API makes a clear line between model and simulator allowing very good optimization and world class high speed performance.

The model is provided as a binary shared object and is also available as source (different models have different licensing conditions).
This allows the download and use of the model binary or the use of the source to explore and modify the model.

The model has been run through an extensive QA and regression testing process.

Parallel Simulation using Imperas QuantumLeapTraditionally, processor models and simulators make use of one thread on the host PC.
Imperas have developed a technology, called QuantumLeap, that makes use of the many host cores found in modern PC/workstations to achieve industry leading simulation performance.
To find out about the Imperas parallel simulation lookup Imperas QuantumLeap.
There are videos of QuantumLeap on ARM here,
and MIPS here.
For press information related to QuantumLeap for ARM click here
or for MIPS click here.
Many of the OVP Fast Processor Models have been qualified to work with QuantumLeap - this is indicated for this model below.

Embedded Software Development toolsThis model executes instructions of the target architecture and provides an interface for debug access.
An interface to GDB is provided and this allows the connection of many industry standard debuggers that use the GDB/RSP interface.
For more information watch the OVP video here.
The model also works with the Imperas Multicore Debugger and advanced Verification, Analysis and Profiling tools.

Instruction Set Simulator (ISS) for RISC-V RV32IMACAn ISS is a software development tool that takes in instructions for a target processor and executes them.
The heart of an ISS is the model of the processor.
Imperas has developed a range of ISS products for use in embedded software development that utilize this fast Fast Processor Model.
The Imperas RISC-V RV32IMAC ISS runs on Windows/Linux x86 systems and takes a cross compiled elf file of your program and allows very fast execution.
The RISC-V RV32IMAC ISS also provides access to standard GDB/RSP debuggers and connects to the Eclipse IDE and
Imperas debuggers.

Overview of RISC-V RV32IMAC Fast Processor ModelModel Variant name: RV32IMACDescription: RISC-V RV32IMAC 32-bit processor modelLicensing: This Model is released under the Open Source Apache 2.0Features: The model supports the following architectural features, defined in the misa CSR: extension A (atomic instructions) extension C (compressed instructions) RV32I/64I/128I base ISA extension M (integer multiply/divide instructions) extension S (Supervisor mode) extension U (User mode) 32-bit XLEN If required, supported architectural features may be overridden using parameter "misa_Extensions". Parameter "misa_Extensions_mask" can be used to specify which features can be dynamically enabled or disabled by writes to the misa register. On this variant, the Machine trap-vector base-address register (mtvec) is writable. It can instead be configured as read-only using parameter "mtvec_is_ro". The initial value of "mtvec" is 0x0. A different value may be specified using parameter "mtvec" if required. On reset, the model will restart at address 0x0. A different reset address may be specified using parameter "reset_address" if required. On an NMI, the model will restart at address 0x0. A different NMI address may be specified using parameter "nmi_address" if required. WFI will halt the processor until an interrupt occurs. It can instead be configured as a NOP using parameter "wfi_is_nop". WFI timeout wait is implemented with a time limit of 0 (i.e. WFI causes an Illegal Instruction trap in Supervisor mode when mstatus.TW=1). The "time" CSR is implemented in this variant. Set parameter "time_undefined" to True to instead specify that "time" is unimplemented and reads of it should trap to Machine mode. Usually, the value of the "time" CSR should be provided by the platform - see notes below about the artifact "CSR" bus for information about how this is done. A 9-bit ASID is implemented. Use parameter "ASID_bits" to specify a different implemented ASID size if required. This variant supports address translation modes 0 and 1. Use parameter "Sv_modes" to specify a bit mask of different modes if required. Unaligned memory accesses are not supported by this variant. Set parameter "unaligned" to "T" to enable such accesses. 16 PMP entries are implemented by this variant. Use parameter "PMP_registers" to specify a different number of PMP entries; set the parameter to 0 to disable the PMP unit. LR/SC instructions are implemented with a 1-byte reservation granule. A different granule size may be specified using parameter "lr_sc_grain".Interrupts: The "reset" port is an active-high reset input. The processor is halted when "reset" goes high and resumes execution from the reset address specified using the "reset_address" parameter when the signal goes low. The "mcause" register is cleared to zero. The "nmi" port is an active-high NMI input. The processor is halted when "nmi" goes high and resumes execution from the address specified using the "nmi_address" parameter when the signal goes low. The "mcause" register is cleared to zero. All other interrupt ports are active high.Debug Mask: It is possible to enable model debug messages in various categories. This can be done statically using the "override_debugMask" parameter, or dynamically using the "debugflags" command. Enabled messages are specified using a bitmask value, as follows: Value 0x002: enable debugging of PMP and virtual memory state; Value 0x004: enable debugging of interrupt state. All other bits in the debug bitmask are reserved and must not be set to non-zero values.Integration Support: This model implements a number of non-architectural pseudo-registers and other features to facilitate integration.CSR Register External Implementation: If parameter "enable_CSR_bus" is True, an artifact 16-bit bus "CSR" is enabled. Slave callbacks installed on this bus can be used to implement modified CSR behavior (use opBusSlaveNew or icmMapExternalMemory, depending on the client API). A CSR with index 0xABC is mapped on the bus at address 0xABC0; as a concrete example, implementing CSR "time" (number 0xC01) externally requires installation of callbacks at address 0xC010 on the CSR bus.LR/SC Active Address: Artifact register "LRSCAddress" shows the active LR/SC lock address. The register holds all-ones if there is no LR/SC operation active.Limitations: Instruction pipelines are not modeled in any way. All instructions are assumed to complete immediately. This means that instruction barrier instructions (e.g. fence.i) are treated as NOPs, with the exception of any Illegal Instruction behavior, which is modeled. Caches and write buffers are not modeled in any way. All loads, fetches and stores complete immediately and in order, and are fully synchronous. Data barrier instructions (e.g. fence) are treated as NOPs, with the exception of any Illegal Instruction behavior, which is modeled. Real-world timing effects are not modeled: all instructions are assumed to complete in a single cycle. Hardware Performance Monitor and Debug registers are not implemented and hardwired to zero. The TLB is architecturally-accurate but not device accurate. This means that all TLB maintenance and address translation operations are fully implemented but the cache is larger than in the real device.Verification: All instructions have been extensively tested by Imperas, using tests generated specifically for this model and also reference tests from https://github.com/riscv/riscv-tests.References: The Model details are based upon the following specifications: ---- RISC-V Instruction Set Manual, Volume I: User-Level ISA (User Architecture Version 2.2) ---- RISC-V Instruction Set Manual, Volume II: Privileged Architecture (Privileged Architecture Version 1.10)

Model downloadable (needs registration and to be logged in) in package riscv.model for Windows32 and for Linux32. Note that the Model is also available for 64 bit hosts as part of the commercial products from Imperas.OVP simulator downloadable (needs registration and to be logged in) in package OVPsim for Windows32 and for Linux32. Note that the simulator is also available for 64 bit hosts as part of the commercial products from Imperas.OVP Download page here.OVP documentation that provides overview information on processor models is available OVP_Guide_To_Using_Processor_Models.pdf.

ConfigurationLocation: The Fast Processor Model source and object file is found in the installation VLNV tree: riscv.ovpworld.org/processor/riscv/1.0Processor Endian-ness: This model can be set to either endian-ness (normally by a pin, or the ELF code).Processor ELF Code: The ELF code for this model is: 0xf3QuantumLeap Support: The processor model is qualified to run in a QuantumLeap enabled simulator.