>Find VHDL dependencies:
This utility will find dependencies from your RTL directrory structure:
It takes the top level vhdl file as input, sorts out the dependencies, and
outputs a ordered compile script
To download click Here:

Generate a Template Testbench:
This script will read a vhdl file and generate a template testbench.
This template testbench will instantiate the vhdl design, in the tesbench
and map all the signals at testbench level
To download click Here:

Generate input/output constraints for design compiler
This script will read vhdl file and generate an example constraints file
for its I/Os.
All it does is : it extracts all input output ports, and put a default 70%
input and output delay respectively.
This file then can be customised as required.
To dowload click Here: