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Buster PLCC

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von Dave Haynie anläßlich einer Auktion zu:
Amiga 3000 Fat Buster 2 Schematics, with notes (März 2015)
This is a schematic for the Rev D of the Fat Buster 2 chip, subtitled „The Chip That Ate New Jersey“. Fat Buster was the Zorro III controller for the Amiga 3000 and 4000 computers. This is a printout from the Commodore laser printer on 17„ x 11“ paper. It's got some notes, and a few circuit changes, that were clearly made by me. I think I was looking at a few of the bus master issues we had on the previous chips. Since CSG didn't revise the font number of the gate array when we went from Fat Buster 1 to Fat Buster 2, so this corresponds to Rev 11 of the packaged part. Rev 9 was the first released version of the Fat Buster 2, Rev 10 basically didn't work (CSG was switching from channeled arrays to sea of gates, and had some issues with delivering a full-speed part). The architecture of the Amiga 3000, in particular Commodore's limit on 84 pins on a package, made this a very tricky part to implement properly. Unfortunately, I designed Zorro III for the next 5-10 years of Commodore systems, not just for the Amiga 3000 in 1990. If I knew that was the end-of-the-road, I might have made it a simpler bus.