A new model to predict the dynamic behavior of a self-timed digital system powered by a capacitor is derived. The model demonstrates the hyperbolic shape of the discharging process on the capacitor. It allows a symbolic analysis of the discharging process for complex digital loads comprised of series (stack) and parallel configurations of digital circuits. For example, for a stack configuration, non-trivial relationships between the hyperbolic discharging rates have been derived. The derivations have been validated by simulations and experiments