Abstract:

A display device includes: a pixel array including pixel circuits arranged
in a matrix state, in which each pixel circuit has a light emitting
element, a drive transistor, and a storage capacitor storing a threshold
voltage of the drive transistor and an inputted signal value; a threshold
correction operation means for performing a threshold correction
operation plural times, which allows the storage capacitor to store the
threshold voltage of the drive transistor before giving the signal value
to the storage capacitor; and a cut-off control means for allowing the
drive transistor to be cut off in at least one after-correction period
and for allowing the drive transistor not to be cut off in at least one
after-correction period in plural after-correction periods which are
periods after the plural threshold correction operation periods.

Claims:

1. A display device comprising:a pixel array including pixel circuits
arranged in a matrix state, in which each pixel circuit has at least a
light emitting element, a drive transistor applying electric current to
the light emitting element in accordance with a signal value given
between a gate and a source by a drive voltage applied between the drain
and the source, and a storage capacitor connected between the gate and
the source of the drive transistor and storing a threshold voltage of the
drive transistor and the inputted signal value;a threshold correction
operation means for performing a threshold correction operation plural
times, which allows the storage capacitor to store the threshold voltage
of the drive transistor before giving the signal value to the storage
capacitor; anda cut-off control means for allowing the drive transistor
to be cut off in at least one after-correction period and for allowing
the drive transistor not to be cut off in at least one after-correction
period in plural after-correction periods which are periods after the
plural threshold correction operation periods.

2. The display device according to claim 1,wherein the threshold
correction operation means performs the threshold correction operation by
supplying the drive voltage to the drive transistor in a state in which a
gate potential of the drive transistor is in a reference value in the
threshold correction operation periods, andwherein the cut-off control
means allows the drive transistor to be cut off by supplying an
intermediate voltage which is lower than the drive voltage to the drive
transistor as well as allows the drive transistor not to be cut off by
maintaining the supply of the drive voltage to the drive transistor in
the after-correction periods.

3. The display device according to claim 2, further comprising:a signal
selector supplying potentials as the signal value and the reference value
to respective signal lines arranged in columns on the pixel array;a write
scanner introducing potentials of the signal lines into the pixel
circuits by driving respective write control lines arranged in rows on
the pixel array; anda drive control scanner applying the drive voltage to
the drive transistors in the pixel circuits by using respective power
control lines arranged in rows on the pixel array, and wherein the
threshold correction operation means is realized by an operation of
making the gate potential of the drive transistor be the reference value
given from the signal line by the write scanner and an operation of
supplying the drive voltage to the drive transistor by the drive control
scanner, andwherein the cut-off control means is realized by an operation
of cutting off the drive transistor by supplying the intermediate voltage
which is lower than the drive voltage to the drive transistor by the
drive control scanner and an operation of not cutting off the drive
transistor by maintaining the supply of the drive voltage to the drive
transistor.

4. The display device according to claim 3,wherein the cut-off control
means allows the drive transistor to be cut off in at least a first
after-correction period in plural after-correction periods.

5. The display device according to claim 3,wherein the cut-off control
means allows the drive transistor to be cut off in a first-half
after-correction periods and allows the drive transistor not to be cut
off in a last-half after-correction periods in plural after-correction
periods.

6. The display device according to claim 3,wherein the pixel circuit
further includes a sampling transistor in addition to the light emitting
element, the drive transistor and the storage capacitor,wherein the
sampling transistor is connected to the write control line at a gate
thereof, connected to the signal line at one of source/drain, and
connected to the gate of the drive transistor at the other of
source/drain,wherein the drive transistor is connected to the light
emitting element at one of source/drain and connected to the power
control line at the other of source/drain.

7. The display device according to claim 1,wherein the threshold
correction operation means performs the threshold correction operation by
supplying the drive voltage to the drive transistor in a state in which a
gate potential of the drive transistor is in a reference value given from
the signal line in the threshold correction operation periods, andwherein
the cut-off control means allows the drive transistor to be cut off by
making the gate potential of the drive transistor be a cut-off control
potential as well as allows the drive transistor not to be cut off by not
making the gate potential of the drive transistor be the cut-off control
potential in the after-correction periods.

8. The display device according to claim 7, further comprising:a signal
selector supplying the signal value, the reference value and the cut-off
control potential to respective signal lines arranged in columns on the
pixel array;a write scanner introducing potentials of the signal lines
into the pixel circuits by driving respective write control lines
arranged in rows on the pixel array; anda drive control scanner applying
the drive voltage to the drive transistors in the pixel circuits by using
respective power control lines arranged in rows on the pixel array,
andwherein the threshold correction operation means is realized by a
circuit operation of making the gate potential of the drive transistor be
the reference value given from the signal line by the write scanner and a
circuit operation of supplying the drive voltage to the drive transistor
by the drive control scanner, andwherein the cut-off control means is
realized by an operation of cutting off the drive transistor by supplying
the cut-off control potential from the signal line to the gate of the
drive transistor by the drive control scanner and an operation of not
cutting off the drive transistor by not supplying the cut-off control
potential to the drive transistor.

9. A display drive method of a display device including a pixel array
having pixel circuits arranged in a matrix state, in which each pixel
circuit has at least a light emitting element, a drive transistor
applying electric current to the light emitting element in accordance
with a signal value given between a gate and a source by a drive voltage
applied between the drain and the source, and a storage capacitor
connected between the gate and the source of the drive transistor and
storing a threshold voltage of the drive transistor and the inputted
signal value, comprising the steps of:performing a threshold correction
operation plural times, which allows the storage capacitor to store the
threshold voltage of the drive transistor before giving the signal value
to the storage capacitor; andallowing the drive transistor to be cut off
in at least one after-correction period and for allowing the drive
transistor not to be cut off in at least one after-correction period in
plural after-correction periods which are periods after the plural
threshold correction operation periods.

10. A display device comprising:a pixel array including pixel circuits
arranged in a matrix state, in which each pixel circuit has at least a
light emitting element, a drive transistor applying electric current to
the light emitting element in accordance with a signal value given
between a gate and a source by a drive voltage applied between the drain
and the source, and a storage capacitor connected between the gate and
the source of the drive transistor and storing a threshold voltage of the
drive transistor and the inputted signal value;a threshold correction
operation unit configured to perform a threshold correction operation
plural times, which allows the storage capacitor to store the threshold
voltage of the drive transistor before giving the signal value to the
storage capacitor; anda cut-off control unit configured to allow the
drive transistor to be cut off in at least one after-correction period
and allow the drive transistor not to be cut off in at least one
after-correction period in plural after-correction periods which are
periods after the plural threshold correction operation periods.

Description:

BACKGROUND OF THE INVENTION

[0001]1. Field of the Invention

[0002]The invention relates to a display device including a pixel array in
which pixel circuits are arranged in a matrix state and a display drive
method thereof, and relates to, for example, a display device using an
organic electroluminescence element (organic EL element) as a light
emitting element.

[0003]2. Description of the Related Art

[0004]An image display device in which an organic EL element is used in a
pixel is developed, for example as shown in JP-2003-255856 and
JP-2003-271095 (Patent Documents 2 and 3). Since the organic EL element
is a self-luminous element, it has advantages such that visibility of
images is higher than, for example, a liquid crystal display, a backlight
is not necessary and response speed is high. The luminance level (tone)
of each light emitting element can be controlled by a value of current
flowing therein (so-called current-control type).

[0005]The organic EL display has a passive matrix type and an active
matrix type as a drive method in the same manner as the liquid crystal
display. The former has problems such that it is difficult to realize a
large-sized as well as high-definition display though it has a simple
configuration, therefore, the active-matrix type display device is
vigorously developed at present. The display device of this type controls
electric current flowing in the light emitting element in each pixel
circuit by an active element (commonly, a thin film transistor: TFT)
provided inside the pixel circuit.

SUMMARY OF THE INVENTION

[0006]As the pixel circuit configuration using the organic EL element,
improvement of display quality as well as realization of high luminance,
high definition and a high frame rate (high frequency) by eliminating
luminance unevenness in each pixel and the like are strongly requested.

[0007]From the above viewpoint, various configurations are considered. For
example, pixel circuit configurations and operations are variously
proposed, in which luminance unevenness in each pixel can be eliminated
by cancelling variation of a threshold voltage or mobility of a drive
transistor in each pixel as in JP-2007-133282 (Patent Document 1).

[0008]It is desirable to realize a more suitable threshold cancel
operation as the display device using the organic EL element.

[0009]According to an embodiment of the invention, there is provided a
display device including a pixel array having pixel circuits arranged in
a matrix state, in which each pixel circuit has at least a light emitting
element, a drive transistor applying electric current to the light
emitting element in accordance with a signal value given between a gate
and a source by a drive voltage applied between the drain and the source,
and a storage capacitor connected between the gate and the source of the
drive transistor and storing a threshold voltage of the drive transistor
and the inputted signal value. The display device further includes a
threshold correction operation means for performing a threshold
correction operation plural times, which allows the storage capacitor to
store the threshold voltage of the drive transistor before giving the
signal value to the storage capacitor and a cut-off control means for
allowing the drive transistor to be cut off in at least one
after-correction period and for allowing the drive transistor not to be
cut off in at least one after-correction period in plural
after-correction periods which are periods after the plural threshold
correction operation periods.

[0010]The threshold correction operation means performs the threshold
correction operation by supplying a drive voltage to the drive transistor
in a state in which a gate potential of the drive transistor is in a
reference value in the threshold correction operation periods. The
cut-off control means allows the drive transistor to be cut off by
supplying an intermediate voltage which is lower than the drive voltage
to the drive transistor as well as allows the drive transistor not to be
cut off by maintaining the supply of the drive voltage to the drive
transistor in the after-correction periods.

[0011]The display device also includes a signal selector supplying
potentials as the signal value and the reference value to respective
signal lines arranged in columns on the pixel array, a write scanner
introducing potentials of the signal lines into the pixel circuits by
driving respective write control lines arranged in rows on the pixel
array and a drive control scanner applying the drive voltage to the drive
transistors in the pixel circuits by using respective power control lines
arranged in rows on the pixel array. The threshold correction operation
means is realized by an operation of making the gate potential of the
drive transistor be the reference value given from the signal line by the
write scanner and an operation of supplying the drive voltage to the
drive transistor by the drive control scanner. The cut-off control means
is realized by an operation of cutting off the drive transistor by
supplying the intermediate voltage which is lower than the drive voltage
to the drive transistor by the drive control scanner and an operation of
not cutting off the drive transistor by maintaining the supply of the
drive voltage to the drive transistor.

[0012]The cut-off control means allows the drive transistor to be cut off
in at least a first after-correction period in plural after-correction
periods.

[0013]The cut-off control means also allows the drive transistor to be cut
off in a first-half after-correction periods and allows the drive
transistor not to be cut off in a last-half after-correction periods in
plural after-correction periods.

[0014]The pixel circuit further includes a sampling transistor in addition
to the light emitting element, the drive transistor and the storage
capacitor, in which the sampling transistor is connected to the write
control line at a gate thereof, connected to the signal line at one of
source/drain, and connected to the gate of the drive transistor at the
other of source/drain, and in which the drive transistor is connected to
the light emitting element at one of source/drain and connected to the
power control line at the other of source/drain.

[0015]The threshold correction operation means performs the threshold
correction operation by supplying the drive voltage to the drive
transistor in a state in which a gate potential of the drive transistor
is in a reference value given from the signal line in the threshold
correction operation periods, and the cut-off control means allows the
drive transistor to be cut off by making the gate potential of the drive
transistor be a cut-off control potential as well as allows the drive
transistor not to be cut off by not making the gate potential of the
drive transistor be the cut-off control potential in the after-correction
periods.

[0016]The display device also includes a signal selector supplying the
signal value, the reference value and the cut-off control potential to
respective signal lines arranged in columns on the pixel array, a write
scanner introducing potentials of the signal lines into the pixel
circuits by driving respective write control lines arranged in rows on
the pixel array and a drive control scanner applying the drive voltage to
the drive transistors in the pixel circuits by using respective power
control lines arranged in rows on the pixel array. The threshold
correction operation means is realized by a circuit operation of making
the gate potential of the drive transistor be the reference value given
from the signal line by the write scanner and a circuit operation of
supplying the drive voltage to the drive transistor by the drive control
scanner. The cut-off control means is realized by an operation of cutting
off the drive transistor by supplying the cut-off control potential from
the signal line to the gate of the drive transistor by the drive control
scanner and an operation of not cutting off the drive transistor by not
supplying the cut-off control potential to the drive transistor.

[0017]A display drive method according to another embodiment of the
invention includes the steps of performing a threshold correction
operation plural times, which allows the storage capacitor to store the
threshold voltage of the drive transistor before giving the signal value
to the storage capacitor and allowing the drive transistor to be cut off
in at least one after-correction period and for allowing the drive
transistor not to be cut off in at least one after-correction period in
plural after-correction periods which are periods after the plural
threshold correction operation periods.

[0018]As the pixel circuit operation in the organic EL display device is
performed in a higher frequency, the threshold correction operation of
the drive transistor is performed in a time division manner in some
cases. The threshold correction operation is performed in the time
division manner, thereby securing time necessary for the threshold
correction operation and cancelling variation of the threshold
appropriately. However, when the number of divided correction operations
is increased, complication of one cycle as the pixel circuit operation is
worsened and adverse effects such as power fluctuation may occur.
Accordingly, it is desirable to reduce the number of divided operations.
For that purpose, a rapid threshold correction operation becomes
necessary.

[0019]Here, it is possible to prevent the increase of the gate potential
and the source potential and to perform more accurate threshold
correction by cutting off the drive transistor in periods after the
threshold correction operations (after-correction periods) to suppress
leak current. On the other hand, it is possible to allow the voltage
between the gate and the source of the drive transistor to converge to
the threshold voltage earlier by positively using the leak current. That
is, the threshold correction operation can be accelerated.

[0020]In the embodiments of the invention, both accuracy and quickness in
the threshold correction operation are realized by providing a period in
which the drive transistor is cut off and a period in which the drive
transistor is not cut off in plural after-correction periods.

[0021]According to the embodiments of the invention, when performing
threshold correction in the time division manner, a period in which drive
transistor is cut off and a period in which drive transistor is not cut
off are provided as after-correction periods. In an after-correction
period (for example, the first after-correction period) among the plural
after-correction periods, in which adverse effects due to leak current
are concerned, the drive transistor is cut off to secure the accuracy of
the threshold correction operation. In an after-correction period in
which adverse effects due to leak current are not concerned, the drive
transistor is not cut off, and the voltage between the gate and the
source of the drive transistor is made to be closer to the threshold
voltage earlier by using the potential increase of the source and the
gate due to leak current. Accordingly, it is possible to realize both
accuracy and quickness in the threshold correction operation. Then, it is
possible to reduce the number of divided corrections as well as to reduce
power fluctuation and the like in the power control lines.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022]FIG. 1 is an explanatory diagram of a configuration of a display
device according to an embodiment of the invention;

[0023]FIG. 2 is an explanatory diagram of a pixel circuit configuration
according to the embodiment;

[0024]FIG. 3 is an explanatory chart of a pixel circuit operation before
reaching the embodiment;

[0025]FIG. 4 is an explanatory graph of Ids-Vgs characteristics of a drive
transistor;

[0026]FIG. 5 is an explanatory chart of a pixel circuit operation
according to a first embodiment;

[0027]FIG. 6 is an explanatory diagram of a cut-off control operation
according to the first embodiment; and

[0028]FIG. 7 is an explanatory chart of a pixel circuit operation
according to a second embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0029]Hereinafter, as a display device according to an embodiment of the
invention, an example of a display device using the organic EL element
will be explained in the following order. [0030]1. Configuration of a
display device according to an embodiment [0031]2. Pixel circuit
operation in a process leading to an embodiment of the invention [0032]3.
Pixel circuit operation as a first embodiment of the invention [0033]4.
Pixel circuit operation as a second embodiment of the invention

1. Configuration of a Display Device According to an Embodiment

[0034]FIG. 1 shows the whole configuration of a display device according
to an embodiment. The display device includes pixel circuits 10 having a
correction function with respect to variation of a threshold voltage and
mobility of a drive transistor as described later.

[0035]As shown in FIG. 1, the display device of the embodiment includes a
pixel array unit 20 in which pixel circuits 10 are arranged in a column
direction as well as a row direction in a matrix state. "R", "G" and "B"
are given to the pixel circuits 10, which indicate that the circuits are
light emitting pixels of respective colors of R (red), G (Green) and B
(Blue).

[0036]In order to drive respective pixel circuits 10 in the pixel array
unit 20, a horizontal scanner 11, a write scanner 12 and a drive scanner
(drive control scanner) 13 are included.

[0037]Additionally, signal lines DTL1, DTL2 . . . which are selected by
the horizontal selector 11 and supply video signals corresponding to
luminance information as input signals with respect to the pixel circuits
10 are arranged in the column direction in the pixel array unit 20. The
signal lines DTL1, DTL2 . . . are arranged by the number of columns of
the pixel circuits 10 arranged in the matrix state in the pixel array
unit 20.

[0038]Furthermore, write control lines WSL1, WSL2 . . . and power control
lines DSL1, DLS2 . . . are arranged in the row direction in the pixel
array unit 20. These write control lines WSL and the power control lines
DSL are arranged by the number of rows of the pixel circuits 10 arranged
in the matrix state in the pixel array unit 20.

[0040]The power control lines DSL (DSL1, DLS2 . . . ) are driven by the
drive scanner 13. The drive scanner 13 supplies power pulses DS (DS1, DS2
. . . ) as a power supply voltages switched to three values of a drive
voltage (V1), an intermediate voltage (V2) and an initial voltage (Vini)
to respective power control lines DSL1, DSL2 . . . arranged in rows so as
to correspond to the line-sequential scanning by the write scanner 12.

[0041]The horizontal selector 11 supplies a signal potential (Vsig) and a
reference potential (Vofs) as input signals with respect to the pixel
circuits 10 to the signal lines DTL1, DTL2 . . . arranged in the column
direction so as to correspond to the line-sequential scanning by the
write scanner 12.

[0042]FIG. 2 shows a configuration of the pixel circuit 10. The pixel
circuits 10 are arranged in a matrix state as shown in the pixel circuits
10 in the configuration of FIG. 1. In FIG. 2, only one pixel circuit 10
is shown for simplification, which is arranged at a portion where the
signal line DTL, the write control line WSL and the power control line
DSL cross one another.

[0043]The pixel circuit 10 includes an organic EL element 1 as a light
emitting element, a storage capacitor Cs and two thin-film transistors
(TFT) as a sampling transistor TrS and a drive transistor TrD. The
sampling transistor Trs and the drive transistor TrD are n-channel TFTs.

[0044]One terminal of the storage capacitor Cs is connected to a source of
the drive transistor TrD, and the other terminal is connected to a gate
of also the drive transistor TrD.

[0045]The light emitting element of the pixel circuit 10 is, for example,
an organic EL element 1 of a diode configuration, having an anode and a
cathode. The anode of the organic EL element 1 is connected to the source
S of the drive transistor TrD and the cathod is connected to a given
ground wiring (cathode potential Vcath). A capacitor CEL is a parasitic
capacitor of the organic EL element 1.

[0046]One terminal of drain/source of the sampling transistor TrS is
connected to the signal line DTL and the other terminal is connected to
the gate of the drive transistor TrD. A gate of the sampling transistor
TrS is connected to the write control line WSL.

[0047]A drain of the drive transistor TrD is connected to the power
control line DSL.

[0048]Light emitting drive of the organic EL element 1 is performed in the
following manner.

[0049]The sampling transistor TrS becomes conductive by the scanning pulse
WS given from the write scanner 12 by the write control line WSL at the
timing when the signal potential Vsig is applied to the signal line DTL.
Accordingly, the input signal Vsig from the signal line DTL is written in
the storage capacitor Cs. The drive transistor TrD allows current
corresponding to the signal potential stored in the storage capacitor Cs
in the organic EL element 1 by current supply from the power control line
DSL to which the drive potential V1 is given by the drive scanner 13 to
thereby allow the, organic EL element 1 to emit light.

[0050]In the pixel circuit 10, an operation (hereinafter, referred to as a
Vth cancel operation) for correcting effects of variation of a threshold
voltage Vth of the drive transistor TrD before current drive of the
organic EL element 1 is performed. Further, a mobility correction
operation for cancelling effects of variation of mobility of the drive
transistor TrD is performed simultaneously with the writing the input
signal Vsig from the signal line DTL to the storage capacitor Cs.

2. Pixel Circuit Operation in a Process Leading to an Embodiment of the
Invention

[0051]Here, a circuit operation studied in the process leading to the
invention in the above pixel circuit 10 will be explained. Particularly,
an operation of performing divided correction as the Vth cancel will be
explained with reference to FIG. 3.

[0052]In FIG. 3, the potentials (the signal potential Vsig and the
reference potential Vofs) given to the signal line DTL by the horizontal
selector 11 are shown as the DTL input signal.

[0053]As the scanning pulse WS, a pulse to be applied to the write control
line WSL by the write scanner 12 is shown. The sampling transistor TrS is
controlled to be conductive/non-conductive by the scanning pulse WS.

[0054]As the power pulse DS, voltages to be applied to the power control
line DSL by the drive scanner 13 are shown. As the voltages, the drive
scanner 13 supplies the drive voltage V1 and the initial voltage Vini to
be switched at predetermined timings.

[0055]The variations of a gate potential Vg, a source potential Vs of the
drive transistor TrD are also shown.

[0056]A point "ts" in a timing chart of FIG. 3 indicates a start timing of
one cycle in which the organic EL element 1 as the light emitting element
is driven for emitting light, for example, one frame period of image
display.

[0057]First, the drive scanner 13 supplies the initial potential Vini as
the power pulse DS at the point "ts". Accordingly, the source potential
Vs of the drive transistor TrD is reduced at the initial potential Vini
and the organic EL element 1 is in a non-light emitting state. The gate
potential Vg of the drive transistor TrD in a floating state is also
reduced.

[0058]After that, a preparation for the Vth cancel operation is made
during a period "t30". That is, when the signal line DTL is in the
reference potential Vofs, the scanning pulse WS is made to be H-level to
allow the sampling transistor TrS to be conductive. Accordingly, the gate
potential Vg of the drive transistor TrD is fixed at the potential Vofs.
The source potential Vini maintains the initial potential Vini.

[0059]According to the above, a voltage Vgs between the gate and the
source of the drive transistor TrD is made to be higher than the
threshold voltage Vth to thereby preparing the Vth cancel operation.

[0060]Next, the Vth cancel operation is started. In this case, the
threshold correction is performed in a time division manner in periods
t31, t33, t35 and t37.

[0061]First, in the period "t31", the power pulse DS is made to be in the
drive potential V1 by the drive scanner 13 while the gate potential Vg of
the drive transistor TrD is fixed in the reference potential Vofs,
thereby increasing the source potential Vs.

[0062]At this time, the write scanner 12 turns on the scanning pulse WS
intermittently in periods when the signal line DTL is in the reference
voltage Vofs for preventing the source potential Vs from exceeding the
threshold of the organic EL element 1 as well as for allowing the
sampling transistor TrS to be non-conductive in periods when the DTL
input signal is in the signal potential Vsig. Accordingly, the Vth cancel
operation is performed in periods t31, t33, 335 and t37 in the divided
manner.

[0063]The Vth cancel operation is completed when the voltage Vgs between
the gate and the source of the drive transistor TrD is equal to the
threshold voltage Vth (period t37).

[0064]In a period t32 (after-correction period) after the period t31 when
the Vth correction operation is performed, an after-correction period t34
after the period t33 as well as an after-correction period t36 after the
period t35, the sampling transistor TrS is in an off state by the
scanning pulse WS. This is for preventing signal values from being
applied to the gate of the drive transistor TrD during period in which
the DTL input signal is in signal value voltages (signal values for
pixels of other lines). However, in the after-correction periods t32, t34
and t36, the drive potential V1 from the power control line DSL is
continuously supplied to the drain of the drive transistor TrD.

[0065]Since the drive transistor TrD is not completely cut off, electric
current is not completely stopped, consequently, a phenomenon in which
the source potential Vs is increased and the gate potential Vg is
increased accordingly as shown in the drawing. The increased gate
potential Vg is returned to the reference potential Vofs as the DTL input
signal when the sampling transistor TrS is turned on by the scanning
pulse WS.

[0066]As described above, after the Vth cancel operation is performed in
the divided manner of plural times, the scanning pulse WS is turned on at
a timing (period t39) when the signal line DTL becomes in the signal
potential Vsig with respect to the pixel circuit, thereby writing the
signal potential Vsig in the storage capacitor Cs. The period t39 is also
a mobility correction period of the drive transistor TrD.

[0067]In the period t39, the source potential Vs is increased in
accordance with the mobility of the drive transistor TrD. That is, when
the mobility of the transistor TrD is high, the increased amount of the
source potential Vs is high, and when the mobility is low, the increased
amount of the source potential Vs is low. As a result, this will be the
operation of adjusting the voltage Vgs between the gate and the source of
the drive transistor TrD in the light emitting period in accordance with
the mobility.

[0068]After that, when the source potential Vs is in the potential
exceeding the threshold of the organic EL element 1, the organic EL
element 1 emits light.

[0069]In short, the drive transistor TrD allows drive current to flow in
accordance with the potential stored in the storage capacitor Cs to
thereby emit light in the organic EL element 1. At this time, the source
potential Vs of the drive transistor TrD is held in a given operation
point.

[0070]The drive potential V1 is applied to the drain of the drive
transistor TrD from the power control line DSL so that the drive
transistor TrD is constantly operated in a saturated region, therefore,
the drive transistor TrD functions as a constant current source and an
electric current Ids flowing in the organic El element 1 will be
represented by the following formula 1 in accordance with the voltage Vgs
between the gate and the source of the drive transistor TrD.

I ds = 1 2 μ W L C ox ( V gs - V th ) 2
[ Formula 1 ] ##EQU00001##

[0071]Ids represents the electric current flowing between the drain and
the source of the transistor operating in the saturation region, i
represents the mobility, W represents a channel width, L represents a
channel length, Cox represents a gate capacity, Vth represents a
threshold voltage of the drive transistor TrD and Vgs represents the
voltage between the gate and the source of the drive transistor TrD.

[0072]As can be seen from the Formula 1, the electric current Ids depends
on a square value of the voltage Vgs between the gate and the source of
the drive transistor TrD, therefore, the relation between the electric
current Ids and the voltage Vgs between the gate and the source will be
as shown in FIG. 4.

[0073]The drain current Ids of the drive transistor TrD is controlled by
the voltage Vgs between the gate and the source in the saturation region.
Since the voltage Vgs between the gate and the source of the drive
transistor TrD (=Vsig+Vth) is fixed by the action of the storage
capacitor Cs, therefore, the drive transistor TrD is operated as the
constant current source allowing the fixed current to flow in the organic
EL element 1.

[0074]Accordingly, an anode potential (source potential Vs) of the organic
EL element 1 is increased to a voltage at which electric current flows in
the organic EL element 1 to allow the organic EL element to emit light.
That is, light emission at luminance in accordance with the signal
voltage Vsig in this frame is started.

[0075]Accordingly, in the pixel circuit 10, the operation for light
emission of the organic EL element 1 including the Vth cancel operation
and the mobility correction is performed in one frame period.

[0076]According to the Vth cancel operation, electric current
corresponding to the signal potential Vsig can be given to the organic EL
element 1 regardless of variation of the threshold voltage Vth of the
drive transistor TrD in each pixel circuit 10 or change of the threshold
voltage Vth due to change over time. That is, it is possible to maintain
high image quality without generating luminance variation and the like on
the screen by cancelling the variation of the threshold voltage Vth on
manufacture or by the change over time.

[0077]Since the drain current changes also by the mobility of the drive
transistor TrD, image quality is reduced by variation of the mobility of
the drive transistor TrD at each pixel circuit 10, the source potential
Vs can be obtained according to the degree of mobility of the drive
transistor TrD by the mobility correction, as a result, the source
potential Vs is adjusted to obtain the voltage Vgs between the gate and
the source which absorbs variation of the mobility of the drive
transistor TrD in each pixel circuit 10, therefore, reduction of image
quality due to the variation of mobility is also prevented. [0078]3.
Pixel Circuit Operation as a First Embodiment of the Invention

[0079]As described above, as a pixel circuit operation of one cycle, the
Vth cancel operation is performed in the divided manner plural times. The
reason that the Vth cancel operation is performed plural times in the
time division manner is because there is a request for the high frequency
in the display device.

[0080]As the frame rate becomes higher, operation time of the pixel
circuit becomes relatively shorter, therefore, it is difficult to secure
the continuous Vth cancel period. Accordingly, the period necessary for
the Vth cancel is secured by performing the Vth cancel operation in the
time division manner to thereby allow the voltage between the gate and
the source of the drive transistor TrD to be converged to the threshold
voltage Vth.

[0081]However, when the Vth cancel operation in the time division manner
as FIG. 3 is performed, the source potential Vs and the gate potential Vg
are increased at the after-correction periods t32, t34 and t36 as
described above. This raises fears of malfunctions in the Vth cancel
operation.

[0082]After the source potential Vs and the gate potential Vg are
increased in the after-correction periods t32, t34 and t36 as described
above, the gate potential Vg is returned to the reference potential Vofs
by re-starting the Vth cancel operation, however, the source potential Vs
maintains increased potential. At this time, the voltage between the gate
and the source may possibly be decreased to be lower than the threshold
voltage Vth in some cases. In such case, the accurate Vth cancel
operation is not realized.

[0083]Accordingly, in order to address the circumstances, it becomes
preferable that the drive transistor TrD is forcibly cut off in the
after-correction periods t32, t34 and t36.

[0084]On the other hand, it is also requested that the Vth cancel
operation is performed rapidly.

[0085]For example, in the example of FIG. 3, the Vth cancel operation is
performed by dividing the operation period into periods t31, t33, t35 and
t37.

[0086]When the drive transistor TrD is forcibly cut off in
after-correction periods, the increase of the source potential Vs and the
gate potential Vg can be prevented.

[0087]However, since the drive transistor TrD is cut off by some method
for the above purpose, it is necessary to devise some methods for the DTL
input signal, the scanning pulse WS and the power pulse DS in the
after-correction periods.

[0088]The performance of the above operations complicates the circuit
operation control. That is, the change of the pulse level in the write
control line WSL and the power control line DSL is increased in one
cycle. It is necessary to reduce the number of divided Vth cancel
operations for reducing the change.

[0089]Then, it is requested to speed up the Vth cancel operation and to
shorten the whole period of time necessary as the cancel operation for
reducing the number of divided Vth cancel operations.

[0090]Accordingly, as the pixel circuit operation according to the
embodiment, a method realizing both accuracy and quickness in the Vth
cancel operation will be explained below.

[0092]Also in FIG. 5, potentials (the signal potential Vsig and the
reference potential Vofs) given to the signal line DTL by the horizontal
selector 11 are shown as the DTL input signal in the same manner as FIG.
3.

As the scanning pulse WS, a pulse to be applied to the write control line
WSL by the write scanner 12 is shown.

[0093]As the power pulse DS, voltages to be applied to the power control
line DSL by the drive scanner 13 are shown. In the case of FIG. 5, as
voltages to be applied to the power control line DSL, the intermediate
voltage V2 is generated by the drive scanner 13 in addition to the drive
potential V1 and the initial potential Vini, which are switched at
predetermined timings.

[0094]The changes of the gate potential Vg and the source potential Vs of
the drive transistor TrD are also shown.

[0095]A cycle of the light-emitting drive operation of the organic EL
element 1 is started as a point "ts" at a timing chart of FIG. 5.

[0096]First, the drive scanner 13 allows the power pulse DS given to the
power control line DSL to be the initial potential Vini at the point
"ts". According to this, the source potential Vs of the drive transistor
TrD is reduced at the initial potential Vini and the organic EL element 1
is in the non-light emitting state. The gate potential Vg of the drive
transistor TrD is also reduced.

[0097]After that, a preparation for the Vth cancel operation is made
during a period "t1". That is, when the signal line DTL is in the
reference voltage Vofs, the scanning pulse WS is made to be H-level by
the drive scanner 13 to allow the sampling transistor TrS to be
conductive. Accordingly, the gate potential Vg of the drive transistor
TrD is fixed to the voltage Vofs. The source potential Vs maintains the
initial potential Vini. As the preparation for the Vth cancel, the
voltage Vgs between the gate and the source of the drive transistor TrD
is made to be higher than the threshold voltage Vth in this manner.

[0098]Next, the Vth cancel operation is started. In this case, the
threshold correction is performed in the time division manner in periods
t2, t3 and t6.

[0099]First, in the period t2, the power pulse DS is made to be the drive
potential V1 by the drive scanner 13 while fixing the gate voltage Vg of
the drive transistor TrD to be the reference potential Vofs, thereby
increasing the source potential Vs.

[0100]The Vth cancel operation is executed in the periods t4, t6 in the
same manner.

[0101]The Vth cancel operation is completed when the voltage Vgs between
the gate and the source of the drive transistor TrD is equal to the
threshold voltage Vth (period t6).

[0102]As described above, after the Vth cancel operation is performed in
the divided manner of plural times, the scanning pulse WS is turned on at
a timing (period t8) when the signal line DTL becomes in the signal
potential Vsig with respect to the pixel circuit, thereby writing the
signal potential Vsig in the storage capacitor Cs. The period t8 is also
a mobility correction period of the drive transistor TrD.

[0103]In the period t8, the source potential Vs is increased in accordance
with the mobility of the drive transistor TrD. That is, when the mobility
of the transistor TrD is high, the increased amount of the source
potential Vs is high, and when the mobility is low, the increased amount
of the source potential Vs is low. As a result, this will be the
operation of adjusting the voltage Vgs between the gate and the source of
the drive transistor TrD in the light emitting period in accordance with
the mobility.

[0104]After that, when the source potential Vs is in the potential
exceeding the threshold of the organic EL element 1, the organic EL
element 1 emits light.

[0105]In short, the drive transistor TrD allows drive current to flow in
accordance with the potential stored in the storage capacitor Cs to
thereby emit light in the organic EL element 1. At this time, the source
potential Vs of the drive transistor TrD is held in a given operation
point.

[0106]The drive potential V1 is applied to the drain of the drive
transistor TrD from the power control line DSL so that the drive
transistor TrD is constantly operated in a saturated region, therefore,
the drive transistor TrD functions as a constant current source, and the
electric current Ids represented by the above Formula 1, namely, the
electric current corresponding to the voltage Vgs between the gate and
the source of the drive transistor TrD flows in the organic EL element 1.
According to this, the organic EL element 1 emits light at luminance
corresponding to the signal value Vsig.

[0107]In the above operation of the embodiment, the Vth cancel operation
is performed in the time division manner in periods t2, t4 and t6. In the
after-correction period t3 as the first time, the drive transistor TrD is
completely cut off to thereby prevent the increase of the source
potential Vs and the gate potential Vg. On the other hand, the drive
transistor TrD is not forcibly cut off in the second after-correction
period t5 so as not to stop the electric current Ids completely, thereby
increasing the source potential Vs and the gate potential Vg.

[0108]First, in the first after-correction period t3, the drive transistor
is cut off by making the power pulse DS from the power control line DSL
be the intermediate potential V2.

[0109]The power pulse DS is made to be the intermediate potential V2 to
thereby form a coupling through a parasitic capacitor Cp between the gate
and drain of the drive transistor TrD shown in FIG. 6.

[0110]Accordingly, the voltage between the gate and the source of the
drive transistor TrD is reduced and cut off the drive transistor TrD to
be in the state in which the electric current Ids does not flow.

[0111]As described above, the drive transistor TrD is cut off in the
after-correction periods t3 to prevent the increase of the source
potential Vs and the gate potential Vg as shown in FIG. 5.

[0112]In this case, in order to normally perform the cut-off control
operation, the power pulse DS is reduced to the intermediate potential V2
after the scanning pulse WS is made to be L-level to turn off the
sampling transistor TrS as shown in a start timing and an end timing of
the after-correction period t3. Before the scanning pulse WS rises again,
the power pulse DS is made to be the drive potential V1.

[0113]It is necessary that the intermediate potential V2 is higher than a
value (Vofs-Vth) in which the drive transistor TrD is not turned on. When
the intermediate potential V2 is less than the value (Vofs-Vth), the gate
potential Vg is reduced when the Vth cancel operation in the time
division manner is performed and there is a case in which the threshold
voltage Vth is not held when the scanning pulse WS rises again.

[0114]Additionally, in order to increase a negative coupling value, it is
desirable to apply a value as large as possible as the maximum
power-pulse voltage value within the withstand voltage.

[0115]On the other hand, in the second after-correction period t5, the
drive transistor TrD is not forcibly cut off. That is, as shown in FIG.
5, the power pulse DS from the power control line DSL is held in the
drive potential V1 in the after-correction period t5.

[0116]The source potential Vs and the gate potential Vg increase in the
after-correction period t5 as shown in the drawing because the drive
transistor TrD is not cut off in this case.

[0117]Here, when the scanning pulse WS rises in the next period t6 and the
third Vth cancel operation is started, the reference potential Vofs as
the DTL input signal is applied to the gate of the drive transistor Trd.
That is, the gate potential Vg increased in the after-correction period
t5 is returned to the reference potential Vogs. However, the source
potential Vs holds the increased potential. As a result, the voltage Vgs
between the gate and the source of the drive transistor TrD becomes
narrower than the voltage at the end of the previous period t4, which is
close to the threshold voltage Vth. That is, the increase of the source
potential Vs in the after-correction period t5 accelerates the voltage
Vgs between the gate and the source to attain the threshold voltage Vth.
In other words, the increase amount of the source potential Vs is
appropriated to the voltage for Vth cancel.

[0118]In the case of FIG. 5, the voltage between the gate and the source
is equal to Vth in the period t6 and the Vth cancel operation is
completed.

[0119]As described above, in the case of the embodiment, the drive
transistor TrD is cut off in the first after-correction period t3 and the
drive transistor TrD is not cut off in the second after-correction period
t5, thereby realizing the accuracy of the threshold correction and the
shortening of the correction period.

[0120]First, in the first after-correction period t3, the voltage Vgs
between the gate and the source is relatively high, therefore, if the
cut-off is not performed, relatively high electric current flows and the
source potential Vs and the gate potential Vg largely increase. (For
example, as can be seen from the example of FIG. 3, the degree of
potential increase is considerably large in the first after-correction
period t32 as compared with the second and third after-correction periods
t34, t36).

[0121]Then, the voltage Vgs between the gate and the source may possibly
be decreased to be lower than the threshold voltage Vth in some cases
when the gate potential Vg is equal to the reference potential Vofs in
the period t4 in which the next Vth cancel operation is performed. In
this case, it is difficult to realize the accurate threshold correction
operation. Accordingly, the drive transistor TrD is cut off in the first
after-correction period t3 so as not to allow the source potential Vs and
the gate potential Vg to be increased, thereby securing the accuracy of
the threshold correction operation.

[0122]On the other hand, in the second after-correction period t5 after
the Vth cancel operation is performed twice in the periods t2, t4, the
voltage Vgs between the gate and the source have already been narrowed to
some degree, therefore, the amount of electric current is small and
sudden increase of the source potential Vs and the gate potential Vg does
not occur. Accordingly, the voltage Vgs between the gate and the source
does not become lower than the threshold voltage Vth even when the gate
potential Vg is returned to the reference potential Vofs in the next
period t6.

[0123]Accordingly, the drive transistor TrD is not cut off in the
after-correction period t5, and the voltage Vgs between the gate and the
source is narrowed at the start point of the next Vth cancel operation
(period t6), thereby accelerating the Vth cancel operation by using the
increase amount of the source potential Vs due to the cut-off.

[0124]It is possible to realize the accuracy of the threshold correction
and the shortening of the whole correction period of the threshold
voltage by the above operation. Due to the shortening of time by
accelerating the threshold correction operation, the threshold correction
can be performed by divided correction operations of three times in the
periods t2, t4 and t6, for example, as shown in FIG. 5, as a result, the
number of divided corrections can be reduced as compared with the divided
correction operation of four times shown in FIG. 3.

[0125]The reduction of the number of divided corrections, further, the
cut-off is not performed in plural after-correction periods, thereby
reducing voltage change of the power pulse DS.

[0126]As described above, if the drive transistor TrD is cut off every
time in plural after-correction periods in order to realize the accuracy
of the threshold correction operation, the power pulse DS is made to be
the intermediate potential V2 every time in plural after-correction
periods, when following the cut-off control method of FIG. 5. This causes
frequent change of the pulse level in the power control line WSL within
one cycle, therefore, so-called power fluctuation tends to occur, which
narrows an operation margin of each power supply. However, the power
pulse DS is made to be the intermediate voltage V2 only in the first
after-correction period t5 in the embodiment, therefore, it is not
necessary to change the pulse level frequently in the power control line
WSL. According to this, the operation margin of the power supply is not
considerably narrowed and there is no disadvantage on design. [0127]4.
Pixel Circuit Operation as a Second Embodiment of the Invention

[0128]The pixel circuit operation according to a second embodiment will be
explained with reference to FIG. 7.

[0130]After the preparation for the Vth cancel operation is made in a
period t11, the Vth cancel operation is performed in the time division
manner in periods t12, t14 and t16.

[0131]Then, in this case, the drive transistor TrD is completely cut off
in a first after-correction period t13, thereby preventing the increase
of the source potential Vs and the gate potential Vg as shown in the
drawing.

[0132]On the other hand, the drive transistor TrD is not forcibly cut off
in a second after-correction period t15, as a result, the source
potential Vs and the gate potential Vg increase. Then, the gate potential
Vg is made to be the reference potential Vofs at the time of the Vth
cancel operation in the period t16, thereby accelerating the Vth cancel
operation in the same manner as the first embodiment described above.

[0133]In the case of the embodiment of FIG. 7, in order to cut off the
drive transistor TrD, a low potential Vofs2 for the cut-off is supplied
as the DTL input signal generated by the horizontal selector 11, in
addition to the signal value (Vsig) and the reference potential Vofs.

[0134]For example, a start point of the first after-correction period t13
just after the period t12 is a timing when the DTL input signal is made
to be the low potential Vofs2. Since the sampling transistor TrS
maintains an on state by the scanning pulse WS at that point, the low
potential Vofs2 is given to the gate of the drive transistor TrD.

[0135]At a start point of the second after-correction period 15 just after
the period t14, the sampling transistor TrS is turned off by the scanning
pulse WS before the DTL input signal is made to be in the low potential
Vofs2, thereby preventing the forcible cut-off control.

[0136]According to the case of the second embodiment described above, the
same advantages as the first embodiment can be obtained.

[0137]The embodiments of the invention have been explained as the above,
however, the invention is not limited to the embodiments and various
modifications can be considered.

[0138]For example, the configuration example including two transistors
TrD, TrS and the storage capacitor Cs as shown in FIG. 2 is cited as the
pixel circuit 10 of the embodiment, however, the invention can be applied
to pixel circuits other than the above, for example, a case of the pixel
circuit having a configuration including three or more transistors.

[0139]In the above first and second embodiments, the drive transistor TrD
is cut off in the first after-correction period and the drive transistor
TrD is not cut off in the second after-correction period.

[0140]For example, in the case that there are three after-correction
periods, an operation example in which the cut-off is performed in the
first and second periods and the cut-off is not performed in the third
period, or an operation example in which the cut-off is performed in the
first and third periods and the cut-off is not performed in the second
period can be considered.

[0141]As a matter of course, when there are four or more after-correction
periods, various operation examples can be considered.

[0142]Particularly, the concept in which the cut-off is performed at least
in the first after-correction period is suitable in a point that
malfunction in the Vth cancel operation is avoided by performing the
cut-off in the first period when the amount of leak current is high.
Also, the concept in which plural after-correction periods are divided
into a first half and a last half, the cut-off is performed in
after-correction periods of the first half and the cut-off is not
performed in after-correction periods of the last half is suitable from
the same meaning. However, according to operations by the actual circuit
design, characteristics of the drive transistor TrD and the like, various
states can be considered as states of respective after-correction
periods. Therefore, it is preferable to determine in which
after-correction period the cut-off is performed and in which
after-correction period the cut-off is not performed in plural
after-correction periods according to the actual design circuit and
operations of respective scanners.

[0143]The present application contains subject matter related to that
disclosed in Japanese Priority Patent Application JP 2008-210508 filed in
the Japan Patent Office on Aug. 19, 2008, the entire contents of which is
hereby incorporated by reference.

[0144]It should be understood by those skilled in the art that various
modifications, combinations, sub-combinations and alterations may occur
depending on design requirements and other factors insofar as they are
within the scope of the appended claims or the equivalents thereof.